data/full_repos/permissive/139213403/FPGA/bin2bcd.v
1: b'%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/bin2bcd.v:69: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s ADD generates 14 bits.\n                                                                      : ... In instance bin2bcd\n        p2s_next = ~bin + 1\'b1;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/bin2bcd.v:71: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'bin\' generates 14 bits.\n                                                                      : ... In instance bin2bcd\n        p2s_next = bin;    \n                 ^\n%Error: Exiting due to 2 warning(s)\n'
module bin2bcd
#(
	parameter BCD_N=4,
	          BIN_N=14
)
(
	input wire clk, reset,
	input wire start, sign,
	input wire [BIN_N-1:0] bin,
	output reg ready, done_tick,
	output wire [(BCD_N*4)-1:0] bcd
);

localparam [1:0]
	idle = 2'b00,
	op   = 2'b01,
	done = 2'b10;
	
integer i;
reg [1:0] state_reg, state_next;
reg [BCD_N*3:0] p2s_reg, p2s_next;
reg [BCD_N-1:0] n_reg, n_next;
reg [3:0] bcd_reg [BCD_N-1:0];
reg [3:0] bcd_next [BCD_N-1:0];
wire [3:0] bcd_tmp [BCD_N-1:0];



always @(posedge clk, posedge reset)
	if (reset)
		begin
			state_reg = idle;
			p2s_reg = 0;
			n_reg = 0;
			for (i = 0; i <= BCD_N-1; i = i + 1)
				bcd_reg[i] = 0;
		end
	else
		begin
			state_reg = state_next;
			p2s_reg = p2s_next;
			n_reg = n_next;
			for (i = 0; i <= BCD_N-1; i = i + 1)
				bcd_reg[i] = bcd_next[i];
		end


always @*
	begin
		state_next = state_reg;
		ready = 1'b0;
		done_tick = 1'b0;
		p2s_next = p2s_reg;
		for (i = 0; i <= BCD_N-1; i = i + 1)
			bcd_next[i] = bcd_reg[i];
		n_next = n_reg;
		case (state_reg)
			idle:
				begin
					ready = 1'b1;
					if (start)
						begin
							state_next = op;
							for (i = 0; i <= BCD_N-1; i = i + 1)
								bcd_next[i] = 0;
							n_next = (BCD_N * 4'd3) + 1'b1;
							if (sign)
								p2s_next = ~bin + 1'b1;
							else
								p2s_next = bin;
							state_next = op;
						end
				end
			op:
				begin

					p2s_next = p2s_reg << 1;




					
					for (i = 0; i <= BCD_N-1; i = i + 1)
						begin
							if (i == 0)
								bcd_next[0] = {bcd_tmp[0][2:0], p2s_reg[BCD_N * 3]};
							else
								bcd_next[i] = {bcd_tmp[i][2:0], bcd_tmp[i-1][3]};
						end
					
					n_next = n_reg - 1'b1;
					if (n_next == 0)
						state_next = done;
				end
			done:
				begin
					done_tick = 1'b1;
					state_next = idle;
				end
			default:
				state_next = idle;
		endcase
	end
	

genvar g;
generate
	for (g = 0; g <= BCD_N-1; g = g + 1)
	begin : dataoutput
		assign bcd_tmp[g] = (bcd_reg[g] > 4'd4) ? bcd_reg[g] + 4'd3 : bcd_reg[g];
		assign bcd[(4 * g) + 3:(4 * g)] = bcd_reg[g];
	end
endgenerate
	
endmodule
module bin2bcd
#(
	parameter BCD_N=4,
	          BIN_N=14
)
(
	input wire clk, reset,
	input wire start, sign,
	input wire [BIN_N-1:0] bin,
	output reg ready, done_tick,
	output wire [(BCD_N*4)-1:0] bcd
);


localparam [1:0]
	idle = 2'b00,
	op   = 2'b01,
	done = 2'b10;
	
integer i;
reg [1:0] state_reg, state_next;
reg [BCD_N*3:0] p2s_reg, p2s_next;
reg [BCD_N-1:0] n_reg, n_next;
reg [3:0] bcd_reg [BCD_N-1:0];
reg [3:0] bcd_next [BCD_N-1:0];
wire [3:0] bcd_tmp [BCD_N-1:0];



always @(posedge clk, posedge reset)
	if (reset)
		begin
			state_reg = idle;
			p2s_reg = 0;
			n_reg = 0;
			for (i = 0; i <= BCD_N-1; i = i + 1)
				bcd_reg[i] = 0;
		end
	else
		begin
			state_reg = state_next;
			p2s_reg = p2s_next;
			n_reg = n_next;
			for (i = 0; i <= BCD_N-1; i = i + 1)
				bcd_reg[i] = bcd_next[i];
		end


always @*
	begin
		state_next = state_reg;
		ready = 1'b0;
		done_tick = 1'b0;
		p2s_next = p2s_reg;
		for (i = 0; i <= BCD_N-1; i = i + 1)
			bcd_next[i] = bcd_reg[i];
		n_next = n_reg;
		case (state_reg)
			idle:
				begin
					ready = 1'b1;
					if (start)
						begin
							state_next = op;
							for (i = 0; i <= BCD_N-1; i = i + 1)
								bcd_next[i] = 0;
							n_next = (BCD_N * 4'd3) + 1'b1;
							if (sign)
								p2s_next = ~bin + 1'b1;
							else
								p2s_next = bin;
							state_next = op;
						end
				end
			op:
				begin

					p2s_next = p2s_reg << 1;




					
					for (i = 0; i <= BCD_N-1; i = i + 1)
						begin
							if (i == 0)
								bcd_next[0] = {bcd_tmp[0][2:0], p2s_reg[BCD_N * 3]};
							else
								bcd_next[i] = {bcd_tmp[i][2:0], bcd_tmp[i-1][3]};
						end
					
					n_next = n_reg - 1'b1;
					if (n_next == 0)
						state_next = done;
				end
			done:
				begin
					done_tick = 1'b1;
					state_next = idle;
				end
			default:
				state_next = idle;
		endcase
	end
	

genvar g;
generate
	for (g = 0; g <= BCD_N-1; g = g + 1)
	begin : dataoutput
		assign bcd_tmp[g] = (bcd_reg[g] > 4'd4) ? bcd_reg[g] + 4'd3 : bcd_reg[g];
		assign bcd[(4 * g) + 3:(4 * g)] = bcd_reg[g];
	end
endgenerate
	
endmodule