data/full_repos/permissive/162338081/debounce.v
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data/verilator_xmls/71c37e29-a851-4eda-a252-17d089510e28.xml
module debounce(CLK,  B,ApertaB);
 
    input CLK;
    input B;
    output reg ApertaB;
 
 

 
    parameter PARADO   = 4'b0001;
    parameter FILTRO1  = 4'b0010;
    parameter APERTADO = 4'b0100;
    parameter FILTRO2  = 4'b1000;
 
    reg [19:0] Count;
 
    reg EnableCount;
 
    reg B_1;
    reg B_2;
 
    always@(posedge CLK) begin
		B_1 <= B;
        B_2 <= B_1;
    end
 
 

 
    reg BTemp1;
    reg BTemp2;
 
    always@(posedge CLK ) begin
		BTemp1 <= B_2;
        BTemp2 <= BTemp1;
    end
 
 

 
    wire Pedge;
    wire Nedge;
 
    assign Nedge = (!BTemp1) & BTemp2;
    assign Pedge = BTemp1 & (!BTemp2);
 
 

 
    reg[3:0] estado;
    reg CountFull;
 
    always@(posedge CLK) begin
    
            case(estado)
                PARADO: begin
                    ApertaB <= 1'b1;
                    if(Nedge) begin
                        estado <= FILTRO1;
                        EnableCount <= 1'b1;
                    end
                    else begin
                        estado <= PARADO;
                    end
                end
 
                FILTRO1: begin
                    if(CountFull) begin
                        ApertaB <= 1'b0;
                        EnableCount <= 1'b0;
                        estado <= APERTADO;
                    end
                    else if(Pedge) begin
                        estado <= PARADO;
                        EnableCount <= 1'b0;
                    end
                    else begin
                        estado <= FILTRO1;
                    end
                end
 
                APERTADO: begin
                    ApertaB <= 1'b1;
                    if(Pedge) begin
                        estado <= FILTRO2;
                        EnableCount <= 1'b1;
                    end
                    else begin
                        estado <= APERTADO;
                    end
                end
 
                FILTRO2: begin
                    if(CountFull) begin
                        EnableCount <= 1'b0;
                        estado <= PARADO;
                    end
                    else if(Nedge) begin
                        EnableCount <= 1'b0;
                        estado <= APERTADO;
                    end
                    else begin
                        estado <= FILTRO2;
                    end
                end
 
                default: begin
                    estado <= PARADO;
                    EnableCount <= 1'b0;
                    ApertaB <= 1'b1;
                end
            endcase
            
    end
 
    always@(posedge CLK) begin
        if(EnableCount) begin
            Count <= Count + 1'b1;
        end
        else begin
            Count <= 20'd0;
        end
    end
 
    always@(posedge CLK) begin
        if(Count == 999999) begin
            CountFull <= 1'b1;
        end
        else begin
            CountFull <= 1'b0;
        end
    end
endmodule
module debounce(CLK,  B,ApertaB);

 
    input CLK;
    input B;
    output reg ApertaB;
 
 

 
    parameter PARADO   = 4'b0001;
    parameter FILTRO1  = 4'b0010;
    parameter APERTADO = 4'b0100;
    parameter FILTRO2  = 4'b1000;
 
    reg [19:0] Count;
 
    reg EnableCount;
 
    reg B_1;
    reg B_2;
 
    always@(posedge CLK) begin
		B_1 <= B;
        B_2 <= B_1;
    end
 
 

 
    reg BTemp1;
    reg BTemp2;
 
    always@(posedge CLK ) begin
		BTemp1 <= B_2;
        BTemp2 <= BTemp1;
    end
 
 

 
    wire Pedge;
    wire Nedge;
 
    assign Nedge = (!BTemp1) & BTemp2;
    assign Pedge = BTemp1 & (!BTemp2);
 
 

 
    reg[3:0] estado;
    reg CountFull;
 
    always@(posedge CLK) begin
    
            case(estado)
                PARADO: begin
                    ApertaB <= 1'b1;
                    if(Nedge) begin
                        estado <= FILTRO1;
                        EnableCount <= 1'b1;
                    end
                    else begin
                        estado <= PARADO;
                    end
                end
 
                FILTRO1: begin
                    if(CountFull) begin
                        ApertaB <= 1'b0;
                        EnableCount <= 1'b0;
                        estado <= APERTADO;
                    end
                    else if(Pedge) begin
                        estado <= PARADO;
                        EnableCount <= 1'b0;
                    end
                    else begin
                        estado <= FILTRO1;
                    end
                end
 
                APERTADO: begin
                    ApertaB <= 1'b1;
                    if(Pedge) begin
                        estado <= FILTRO2;
                        EnableCount <= 1'b1;
                    end
                    else begin
                        estado <= APERTADO;
                    end
                end
 
                FILTRO2: begin
                    if(CountFull) begin
                        EnableCount <= 1'b0;
                        estado <= PARADO;
                    end
                    else if(Nedge) begin
                        EnableCount <= 1'b0;
                        estado <= APERTADO;
                    end
                    else begin
                        estado <= FILTRO2;
                    end
                end
 
                default: begin
                    estado <= PARADO;
                    EnableCount <= 1'b0;
                    ApertaB <= 1'b1;
                end
            endcase
            
    end
 
    always@(posedge CLK) begin
        if(EnableCount) begin
            Count <= Count + 1'b1;
        end
        else begin
            Count <= 20'd0;
        end
    end
 
    always@(posedge CLK) begin
        if(Count == 999999) begin
            CountFull <= 1'b1;
        end
        else begin
            CountFull <= 1'b0;
        end
    end
endmodule