data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_rom.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_rom.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10 addr = addr + 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_rom.v:19: Cannot find file containing module: \'Rom\'\n    Rom rom(.addr(addr), .data(data));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim,data/full_repos/permissive/171720620/Rom\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim,data/full_repos/permissive/171720620/Rom.v\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim,data/full_repos/permissive/171720620/Rom.sv\n             Rom\n             Rom.v\n             Rom.sv\n             obj_dir/Rom\n             obj_dir/Rom.v\n             obj_dir/Rom.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_rom;
    reg [9:0] addr;
    wire [31:0] data;

    Rom rom(.addr(addr), .data(data));

    initial begin
        addr = 0;
    end

    always begin
        #10 addr = addr + 1;
    end
endmodule
module test_rom;

    reg [9:0] addr;
    wire [31:0] data;

    Rom rom(.addr(addr), .data(data));

    initial begin
        addr = 0;
    end

    always begin
        #10 addr = addr + 1;
    end
endmodule