data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf/xor_vec.v
data/verilator_xmls/e841077a-062b-4bcb-b82e-4dbf52b9ef9f.xml
module xor_vec #(parameter X=2) (x,y);

	input [X-1:0] x;
	output y;
	
	assign y = ^x;
	
endmodule
module xor_vec #(parameter X=2) (x,y);


	input [X-1:0] x;
	output y;
	
	assign y = ^x;
	
endmodule