data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/new/buslayer_slave.sv
 line:63: before: "logic"
data/verilator_xmls/c1651ced-2a3a-47cd-b950-25fab713bd88.xml
module buslayer_slave(

    input  logic        wb_clk,
    input  logic        wb_rst,
    input  logic        wb_cyc,
    input  logic        wb_stb,
    input  logic        wb_we,
    input  logic [3:0]  wb_sel,
    input  logic [31:0] wb_dat_i,
    input  logic [31:0] wb_adr,
    output logic        wb_ack,
    output logic        wb_err,
    output logic        wb_stall,
    output logic [31:0] wb_dat_o,

    

    output logic        request,
    output logic        write,
    output logic        reset,
    output logic [31:0] address,
    output logic [31:0] data_from_bus,
    output logic [3:0]  byte_sel,
    input  logic [31:0] data_to_bus,
    input  logic        done,
    input  logic        err

);




enum logic [1:0]
{ RESET        = 2'd0,
  IDLE         = 2'd1,
  REQUEST      = 2'd2,
  WAIT_CYC_LOW = 2'd3
} state, next_state;



logic          done_ff, err_ff;
logic [31 : 0] data_to_bus_ff;
 



always_ff @(posedge wb_clk or posedge wb_rst) begin
    state <= (wb_rst)? RESET : next_state;
end





always_comb begin
    case (state)
        RESET: next_state = IDLE;
        IDLE:  next_state = ((wb_cyc && wb_stb) == 1'b1)? REQUEST : IDLE;
        REQUEST: begin
            next_state = (((err || done) && !wb_cyc) == 1'b1)? IDLE
                       : (((err || done) &&  wb_cyc) == 1'b1)? WAIT_CYC_LOW
                       : REQUEST;
        end
        WAIT_CYC_LOW: next_state = (wb_cyc == 1'b0)? IDLE : WAIT_CYC_LOW;
    endcase
end

 



always_ff @(posedge wb_clk) begin : sequential_logic_for_outputs
    case (state)
        RESET: begin
            write           <= 1'b0;
            byte_sel        <= 4'b0;
            address         <= 32'b0;
            data_from_bus   <= 32'b0;
            data_to_bus_ff  <= 32'b0;
            done_ff         <= 1'b0;
            err_ff          <= 1'b0;  
        end
        IDLE: begin


            write           <= wb_we;
            byte_sel        <= wb_sel;
            address         <= wb_adr;
            data_from_bus   <= wb_dat_i;

            data_to_bus_ff  <= 32'b0;
            done_ff         <=  1'b0;
            err_ff          <=  1'b0;
        end
        REQUEST: begin



            data_to_bus_ff  <= data_to_bus;
            done_ff         <= done;
            err_ff          <= err;
        end
        WAIT_CYC_LOW: begin


             write           <= 1'b0;
             byte_sel        <= 4'b0;
             address         <= 32'b0;
             data_from_bus   <= 32'b0;
        end
    endcase
end

always_comb begin : combinational_logic_for_outputs
   
`ifdef BLS_ERR_1
    wb_ack   = done_ff;
    wb_err   = err_ff;
    wb_dat_o = data_to_bus_ff;
`else
    if (state == RESET || state == IDLE || wb_cyc == 1'b0) begin
        wb_ack   = 1'b0;
        wb_err   = 1'b0;
        wb_dat_o = 32'b0;
    end
    else begin
        wb_ack   = (state == REQUEST)? done : done_ff;
        wb_err   = (state == REQUEST)? err : err_ff;
        wb_dat_o = (state == REQUEST)? data_to_bus : data_to_bus_ff;
    end
`endif
       
   reset    = wb_rst;    
   request  = (state == REQUEST);
   wb_stall = (state == RESET || state == IDLE)? 1'b0 
            : (wb_cyc && !(wb_ack || wb_err));
end

      
endmodule
module buslayer_slave(

    input  logic        wb_clk,
    input  logic        wb_rst,
    input  logic        wb_cyc,
    input  logic        wb_stb,
    input  logic        wb_we,
    input  logic [3:0]  wb_sel,
    input  logic [31:0] wb_dat_i,
    input  logic [31:0] wb_adr,
    output logic        wb_ack,
    output logic        wb_err,
    output logic        wb_stall,
    output logic [31:0] wb_dat_o,

    

    output logic        request,
    output logic        write,
    output logic        reset,
    output logic [31:0] address,
    output logic [31:0] data_from_bus,
    output logic [3:0]  byte_sel,
    input  logic [31:0] data_to_bus,
    input  logic        done,
    input  logic        err

);





enum logic [1:0]
{ RESET        = 2'd0,
  IDLE         = 2'd1,
  REQUEST      = 2'd2,
  WAIT_CYC_LOW = 2'd3
} state, next_state;



logic          done_ff, err_ff;
logic [31 : 0] data_to_bus_ff;
 



always_ff @(posedge wb_clk or posedge wb_rst) begin
    state <= (wb_rst)? RESET : next_state;
end





always_comb begin
    case (state)
        RESET: next_state = IDLE;
        IDLE:  next_state = ((wb_cyc && wb_stb) == 1'b1)? REQUEST : IDLE;
        REQUEST: begin
            next_state = (((err || done) && !wb_cyc) == 1'b1)? IDLE
                       : (((err || done) &&  wb_cyc) == 1'b1)? WAIT_CYC_LOW
                       : REQUEST;
        end
        WAIT_CYC_LOW: next_state = (wb_cyc == 1'b0)? IDLE : WAIT_CYC_LOW;
    endcase
end

 



always_ff @(posedge wb_clk) begin : sequential_logic_for_outputs
    case (state)
        RESET: begin
            write           <= 1'b0;
            byte_sel        <= 4'b0;
            address         <= 32'b0;
            data_from_bus   <= 32'b0;
            data_to_bus_ff  <= 32'b0;
            done_ff         <= 1'b0;
            err_ff          <= 1'b0;  
        end
        IDLE: begin


            write           <= wb_we;
            byte_sel        <= wb_sel;
            address         <= wb_adr;
            data_from_bus   <= wb_dat_i;

            data_to_bus_ff  <= 32'b0;
            done_ff         <=  1'b0;
            err_ff          <=  1'b0;
        end
        REQUEST: begin



            data_to_bus_ff  <= data_to_bus;
            done_ff         <= done;
            err_ff          <= err;
        end
        WAIT_CYC_LOW: begin


             write           <= 1'b0;
             byte_sel        <= 4'b0;
             address         <= 32'b0;
             data_from_bus   <= 32'b0;
        end
    endcase
end

always_comb begin : combinational_logic_for_outputs
   
`ifdef BLS_ERR_1
    wb_ack   = done_ff;
    wb_err   = err_ff;
    wb_dat_o = data_to_bus_ff;
`else
    if (state == RESET || state == IDLE || wb_cyc == 1'b0) begin
        wb_ack   = 1'b0;
        wb_err   = 1'b0;
        wb_dat_o = 32'b0;
    end
    else begin
        wb_ack   = (state == REQUEST)? done : done_ff;
        wb_err   = (state == REQUEST)? err : err_ff;
        wb_dat_o = (state == REQUEST)? data_to_bus : data_to_bus_ff;
    end
`endif
       
   reset    = wb_rst;    
   request  = (state == REQUEST);
   wb_stall = (state == RESET || state == IDLE)? 1'b0 
            : (wb_cyc && !(wb_ack || wb_err));
end

      
endmodule