data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v
1: b'%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:25: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:35: Define or directive not defined: \'`VREG_BUS\'\n    input [`VREG_BUS] rs_addr,  \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`VREG_BUS] rs_addr,  \n                    ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:36: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] rs_data,  \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:37: Define or directive not defined: \'`VREG_BUS\'\n    input [`VREG_BUS] rt_addr,  \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:38: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] rt_data,  \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:40: Define or directive not defined: \'`VREG_BUS\'\n    input [`VREG_BUS] write_addr,  \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:41: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] write_data,  \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:42: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] write_read\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:47: Define or directive not defined: \'`DATA_BUS\'\n    reg [`DATA_BUS] file[1:`REG_SIZE - 1];\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`DATA_BUS] file[1:`REG_SIZE - 1];\n                  ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:47: Define or directive not defined: \'`REG_SIZE\'\n    reg [`DATA_BUS] file[1:`REG_SIZE - 1];\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:53: Define or directive not defined: \'`MEM_WRITE\'\n    wire write_enabled = rw == `MEM_WRITE && (write_addr != 0) && !stall_in;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:53: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n    wire write_enabled = rw == `MEM_WRITE && (write_addr != 0) && !stall_in;\n                                          ^~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/register_file.v:59: Define or directive not defined: \'`REG_SIZE\'\n            for (i = 1; i < `REG_SIZE; i = i + 1)\n                            ^~~~~~~~~\n%Error: Exiting due to 15 error(s)\n'
module register_file#(
    parameter DATA_WIDTH = 32
)(
    input clk,
    input rst_n,
    input stall_in,


    input [`VREG_BUS] rs_addr,
    output [`DATA_BUS] rs_data,
    input [`VREG_BUS] rt_addr,
    output [`DATA_BUS] rt_data,
    input rw,
    input [`VREG_BUS] write_addr,
    input [`DATA_BUS] write_data,
    output [`DATA_BUS] write_read
    );

    integer i;

    reg [`DATA_BUS] file[1:`REG_SIZE - 1];

    assign rs_data = (rs_addr == 0) ? 0 : file[rs_addr];
    assign rt_data = (rt_addr == 0) ? 0 : file[rt_addr];
    assign write_read = (write_addr == 0) ? 0 : file[write_addr];

    wire write_enabled = rw == `MEM_WRITE && (write_addr != 0) && !stall_in;

    always @(negedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            for (i = 1; i < `REG_SIZE; i = i + 1)
                file[i] <= 0;
        end
        else
        begin

            if (write_enabled)
            begin
                file[write_addr] <= write_data;
            end
        end
    end
endmodule
module register_file#(
    parameter DATA_WIDTH = 32
)(
    input clk,
    input rst_n,
    input stall_in,


    input [`VREG_BUS] rs_addr,
    output [`DATA_BUS] rs_data,
    input [`VREG_BUS] rt_addr,
    output [`DATA_BUS] rt_data,
    input rw,
    input [`VREG_BUS] write_addr,
    input [`DATA_BUS] write_data,
    output [`DATA_BUS] write_read
    );


    integer i;

    reg [`DATA_BUS] file[1:`REG_SIZE - 1];

    assign rs_data = (rs_addr == 0) ? 0 : file[rs_addr];
    assign rt_data = (rt_addr == 0) ? 0 : file[rt_addr];
    assign write_read = (write_addr == 0) ? 0 : file[write_addr];

    wire write_enabled = rw == `MEM_WRITE && (write_addr != 0) && !stall_in;

    always @(negedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            for (i = 1; i < `REG_SIZE; i = i + 1)
                file[i] <= 0;
        end
        else
        begin

            if (write_enabled)
            begin
                file[write_addr] <= write_data;
            end
        end
    end
endmodule