data/full_repos/permissive/196412397/UART_Loopback_tb.v
1: b'%Error: data/full_repos/permissive/196412397/UART_Loopback_tb.v:1: Cannot find include file: UART_Loopback_module.v\n`include "UART_Loopback_module.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/UART_Loopback_module.v\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/UART_Loopback_module.v.v\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/UART_Loopback_module.v.sv\n             UART_Loopback_module.v\n             UART_Loopback_module.v.v\n             UART_Loopback_module.v.sv\n             obj_dir/UART_Loopback_module.v\n             obj_dir/UART_Loopback_module.v.v\n             obj_dir/UART_Loopback_module.v.sv\n%Error: data/full_repos/permissive/196412397/UART_Loopback_tb.v:2: Cannot find include file: UART_TX.v\n`include "UART_TX.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/196412397/UART_Loopback_tb.v:3: Cannot find include file: UART_RX.v\n`include "UART_RX.v" \n         ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk <= ~clk; \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #0 RsRx = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1736 RsRx = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #1736 RsRx = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #1736 RsRx = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1736 RsRx = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #1736 RsRx = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #1736 RsRx = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #1736 RsRx = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1736 RsRx = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1736 RsRx = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1736 RsRx = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/UART_Loopback_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #100_000;\n    ^\n%Error: data/full_repos/permissive/196412397/UART_Loopback_tb.v:39: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("wave.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/196412397/UART_Loopback_tb.v:40: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0);\n    ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 13 warning(s)\n'
module UART_Loopback_tb();

reg clk = 1'b1;
reg RsRx;
wire RsTx;
wire [7:0]   dout;
wire o_TX_Done;
wire o_RX_DV;

always #1 clk <= ~clk; 

initial begin

    #0 RsRx = 1;
    #1736 RsRx = 0;
    #1736 RsRx = 1;
    #1736 RsRx = 0;
    #1736 RsRx = 1;
    #1736 RsRx = 0;
    #1736 RsRx = 1;
    #1736 RsRx = 0;
    #1736 RsRx = 1;
    #1736 RsRx = 0;
    #1736 RsRx = 1;

    #100_000;
    $finish();
end

initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
    $display("----------------------------------------------");
    $display(" ");
end

UART_Loopback_module Test_Unit(
    .clk(clk),          
    .RsRx(RsRx),         
    .RsTx(RsTx),        
    .dout(dout),  
    .o_TX_Done(o_TX_Done),     
    .o_RX_DV(o_RX_DV)      
);

endmodule
module UART_Loopback_tb();


reg clk = 1'b1;
reg RsRx;
wire RsTx;
wire [7:0]   dout;
wire o_TX_Done;
wire o_RX_DV;

always #1 clk <= ~clk; 

initial begin

    #0 RsRx = 1;
    #1736 RsRx = 0;
    #1736 RsRx = 1;
    #1736 RsRx = 0;
    #1736 RsRx = 1;
    #1736 RsRx = 0;
    #1736 RsRx = 1;
    #1736 RsRx = 0;
    #1736 RsRx = 1;
    #1736 RsRx = 0;
    #1736 RsRx = 1;

    #100_000;
    $finish();
end

initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
    $display("----------------------------------------------");
    $display(" ");
end

UART_Loopback_module Test_Unit(
    .clk(clk),          
    .RsRx(RsRx),         
    .RsTx(RsTx),        
    .dout(dout),  
    .o_TX_Done(o_TX_Done),     
    .o_RX_DV(o_RX_DV)      
);

endmodule