data/full_repos/permissive/14593708/tests/instruction-decoder-testbench.v
 line:21: before: "assign"
1: b'%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/instruction-decoder-testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n     #0 assign instruction_data = \'h00000000;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/14593708/tests/instruction-decoder-testbench.v:24: Unsupported or unknown PLI call: $monitor\n        $monitor("%b\\t%d\\t%d\\t%d\\t%d\\t%d",\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/instruction-decoder-testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n     #1 assign instruction_data = \'b00000010000001111111110000000000;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/instruction-decoder-testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n     #2 assign instruction_data = \'b00010110000001001010100100000000;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/instruction-decoder-testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n     #3 assign instruction_data = \'b00101000000010000000001000000000;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/instruction-decoder-testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n     #4 assign instruction_data = \'b00111111111110100000001100000000;\n     ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module instruction_decoder_testbench();

    reg[31:0] instruction_data;
    wire[3:0] opcode;
    wire      input_type_1;
    wire[1:0] input_register_selector_1;
    wire[7:0] input_immediate_1;
    wire      input_type_2;
    wire[1:0] input_register_selector_2;
    wire[7:0] input_immediate_2;
    wire[1:0] output_register_selector;

    instruction_decoder id(instruction_data, opcode,
                           input_type_1, input_register_selector_1,
                           input_immediate_1, input_type_2, 
                           input_register_selector_2, input_immediate_2,
                           output_register_selector);

    initial
    begin   
     #0 assign instruction_data = 'h00000000;
        
        $display("opcode\treg s1\treg s2\treg d\timm 1\timm 2");
        $monitor("%b\t%d\t%d\t%d\t%d\t%d",
                 opcode, input_register_selector_1, input_register_selector_2,
                 output_register_selector,
                 input_immediate_1, input_immediate_2);
 

     #1 assign instruction_data = 'b00000010000001111111110000000000;

     #2 assign instruction_data = 'b00010110000001001010100100000000;

     #3 assign instruction_data = 'b00101000000010000000001000000000;

     #4 assign instruction_data = 'b00111111111110100000001100000000;
    end

endmodule
module instruction_decoder_testbench();


    reg[31:0] instruction_data;
    wire[3:0] opcode;
    wire      input_type_1;
    wire[1:0] input_register_selector_1;
    wire[7:0] input_immediate_1;
    wire      input_type_2;
    wire[1:0] input_register_selector_2;
    wire[7:0] input_immediate_2;
    wire[1:0] output_register_selector;

    instruction_decoder id(instruction_data, opcode,
                           input_type_1, input_register_selector_1,
                           input_immediate_1, input_type_2, 
                           input_register_selector_2, input_immediate_2,
                           output_register_selector);

    initial
    begin   
     #0 assign instruction_data = 'h00000000;
        
        $display("opcode\treg s1\treg s2\treg d\timm 1\timm 2");
        $monitor("%b\t%d\t%d\t%d\t%d\t%d",
                 opcode, input_register_selector_1, input_register_selector_2,
                 output_register_selector,
                 input_immediate_1, input_immediate_2);
 

     #1 assign instruction_data = 'b00000010000001111111110000000000;

     #2 assign instruction_data = 'b00010110000001001010100100000000;

     #3 assign instruction_data = 'b00101000000010000000001000000000;

     #4 assign instruction_data = 'b00111111111110100000001100000000;
    end

endmodule