data/full_repos/permissive/143278/ivltests/pr307.v
data/verilator_xmls/ca310164-d598-4540-bdc5-e797f2bad667.xml
module top;
   reg [63:0] in1,in2;
   reg [63:0] out;

   initial begin
      in1 = 64'hffffffffffffffff;
      in2 = 64'hfffffffffffffff7;
      out = in1 + in2;
      $display("%h + %h =  %h", in1,in2,out);
      if (out === 64'hfffffffffffffff6)
	$display("PASSED");
      else
	$display("FAILED");
   end
endmodule
module top;

   reg [63:0] in1,in2;
   reg [63:0] out;

   initial begin
      in1 = 64'hffffffffffffffff;
      in2 = 64'hfffffffffffffff7;
      out = in1 + in2;
      $display("%h + %h =  %h", in1,in2,out);
      if (out === 64'hfffffffffffffff6)
	$display("PASSED");
      else
	$display("FAILED");
   end
endmodule