data/full_repos/permissive/177289247/DataMemory.v
 line:21: before: "+"
data/verilator_xmls/26990382-c4b6-4203-82c6-d2dba9fbb641.xml
module DataMemory (
    input clk,

    input rst,

    input[4:0]  DataAddr,
    input[31:0] DataIn,
    input       DMemR,
    input       DMemW,

    output[31:0] DataOut
);


reg [31:0] DataMemory[31:0];
assign DataOut = DataMemory[DataAddr];
integer i;

initial begin
    for (i = 0; i < 32; i++) begin
        DataMemory[i] <= 0;
    end
end

always @(posedge rst) begin
    for (i = 0; i < 32; i++) begin
        DataMemory[i] <= 0;
    end
end

always@(negedge clk)
begin
    if(DMemW) begin
        DataMemory[DataAddr] <= DataIn;
    end
end

endmodule
module DataMemory (
    input clk,

    input rst,

    input[4:0]  DataAddr,
    input[31:0] DataIn,
    input       DMemR,
    input       DMemW,

    output[31:0] DataOut
);



reg [31:0] DataMemory[31:0];
assign DataOut = DataMemory[DataAddr];
integer i;

initial begin
    for (i = 0; i < 32; i++) begin
        DataMemory[i] <= 0;
    end
end

always @(posedge rst) begin
    for (i = 0; i < 32; i++) begin
        DataMemory[i] <= 0;
    end
end

always@(negedge clk)
begin
    if(DMemW) begin
        DataMemory[DataAddr] <= DataIn;
    end
end

endmodule