data/full_repos/permissive/212763527/school_project/6_adder_subtractor/sources/display_16bto4h.v
data/verilator_xmls/b3ae78ef-d551-41af-8bcb-52cf33b27905.xml
module display_16bto4h #(parameter INTERVAL = 10**5/2)
                        (input CLK,
                         input [15:0] x,
                         input neg,
                         output reg[11:0] DISP);

    integer counter = 0;

    reg[1:0] sel = 0;
    reg[3:0] posb;
    reg[3:0] digit;

    always @(posedge CLK) begin
        if (counter == INTERVAL)begin

            if (sel == 3) 
                sel <= 0;
            else
                sel <= sel + 1;

            counter <= 0;
        end else begin
            counter <= counter + 1;
        end
    end

    always @(sel) begin

        digit[0] = x[sel*4];
        digit[1] = x[sel*4 + 1];
        digit[2] = x[sel*4 + 2];
        digit[3] = x[sel*4 + 3];
    end


    always @(sel) begin
        case (sel)
            0: posb = 4'b1110;
            1: posb = 4'b1101;
            2: posb = 4'b1011;
            3: posb = 4'b0111;
            default: posb = 4'b0;
        endcase
    end


    function [6:0] btohDISP; 
        input[3:0] digit;
        case (digit)
            4'h0:    btohDISP = 7'b0000001;
            4'h1:    btohDISP = 7'b1001111;
            4'h2:    btohDISP = 7'b0010010;
            4'h3:    btohDISP = 7'b0000110;
            4'h4:    btohDISP = 7'b1001100;
            4'h5:    btohDISP = 7'b0100100;
            4'h6:    btohDISP = 7'b0100000;
            4'h7:    btohDISP = 7'b0001111;
            4'h8:    btohDISP = 7'b0000000;
            4'h9:    btohDISP = 7'b0000100;
            4'ha:    btohDISP = 7'b0001000;
            4'hb:    btohDISP = 7'b1100000;
            4'hc:    btohDISP = 7'b0110001;
            4'hd:    btohDISP = 7'b1000010;
            4'he:    btohDISP = 7'b0110000;
            4'hf:    btohDISP = 7'b0111000;
            default: btohDISP = 7'b1111111;
        endcase

    endfunction

    always @(posedge CLK) begin
        if (counter == INTERVAL)begin

            if (sel == 0)

                DISP <= {posb, btohDISP(digit), ~neg};
            else
                DISP <= {posb, btohDISP(digit), 1'b1};

        end
    end

endmodule
module display_16bto4h #(parameter INTERVAL = 10**5/2)
                        (input CLK,
                         input [15:0] x,
                         input neg,
                         output reg[11:0] DISP);


    integer counter = 0;

    reg[1:0] sel = 0;
    reg[3:0] posb;
    reg[3:0] digit;

    always @(posedge CLK) begin
        if (counter == INTERVAL)begin

            if (sel == 3) 
                sel <= 0;
            else
                sel <= sel + 1;

            counter <= 0;
        end else begin
            counter <= counter + 1;
        end
    end

    always @(sel) begin

        digit[0] = x[sel*4];
        digit[1] = x[sel*4 + 1];
        digit[2] = x[sel*4 + 2];
        digit[3] = x[sel*4 + 3];
    end


    always @(sel) begin
        case (sel)
            0: posb = 4'b1110;
            1: posb = 4'b1101;
            2: posb = 4'b1011;
            3: posb = 4'b0111;
            default: posb = 4'b0;
        endcase
    end


    function [6:0] btohDISP; 
        input[3:0] digit;
        case (digit)
            4'h0:    btohDISP = 7'b0000001;
            4'h1:    btohDISP = 7'b1001111;
            4'h2:    btohDISP = 7'b0010010;
            4'h3:    btohDISP = 7'b0000110;
            4'h4:    btohDISP = 7'b1001100;
            4'h5:    btohDISP = 7'b0100100;
            4'h6:    btohDISP = 7'b0100000;
            4'h7:    btohDISP = 7'b0001111;
            4'h8:    btohDISP = 7'b0000000;
            4'h9:    btohDISP = 7'b0000100;
            4'ha:    btohDISP = 7'b0001000;
            4'hb:    btohDISP = 7'b1100000;
            4'hc:    btohDISP = 7'b0110001;
            4'hd:    btohDISP = 7'b1000010;
            4'he:    btohDISP = 7'b0110000;
            4'hf:    btohDISP = 7'b0111000;
            default: btohDISP = 7'b1111111;
        endcase

    endfunction

    always @(posedge CLK) begin
        if (counter == INTERVAL)begin

            if (sel == 0)

                DISP <= {posb, btohDISP(digit), ~neg};
            else
                DISP <= {posb, btohDISP(digit), 1'b1};

        end
    end

endmodule