data/full_repos/permissive/136510272/projects/07_reduced86/port_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/port_controller.v:21: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                               : ... In instance port_controller\nreg [3:0]   g_index = 1\'b0;\n                      ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/port_controller.v:32: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                               : ... In instance port_controller\n        default: port_in = 1\'b0;\n                         ^\n%Error: Exiting due to 2 warning(s)\n'
module port_controller(

    input  wire         clock50,
    input  wire  [15:0] port_addr,  
    output reg   [15:0] port_in,
    input  wire  [15:0] port_out,
    input  wire         port_bit,
    input  wire         port_clk,
    input  wire         port_read,
    

    input  wire [7:0]   ps2_data,
    input  wire         ps2_data_clk,
    

    output reg [10:0]   cursor
    
);


reg [3:0]   g_index = 1'b0;
initial     cursor = 11'h0;




always @* begin

    case (port_addr)
    
        16'h0060, 16'h0064: port_in = {8'h00, keyb_data};
        default: port_in = 1'b0;
        
    endcase

end





reg [7:0] keyb_char    = 8'h00;
reg       keyb_ready1  = 1'b0;
reg       keyb_ready2  = 1'b0;
wire      keyb_ready   = keyb_ready1 ^ keyb_ready2;
reg [1:0] keyb_jread   = 2'b00;
reg [7:0] keyb_data    = 8'h0;
reg [7:0] keyb_xt      = 8'h0;
reg       keyb_unpressed = 1'b0;

always @(*) begin

    case (ps2_data)
    
8'h1C: keyb_xt = 8'h1E;
8'h32: keyb_xt = 8'h30;
8'h21: keyb_xt = 8'h2E;
8'h23: keyb_xt = 8'h20;
8'h24: keyb_xt = 8'h12;
8'h2B: keyb_xt = 8'h21;
8'h34: keyb_xt = 8'h22;
8'h33: keyb_xt = 8'h23;
8'h43: keyb_xt = 8'h17;
8'h3B: keyb_xt = 8'h24;
8'h42: keyb_xt = 8'h25;
8'h4B: keyb_xt = 8'h26;
8'h3A: keyb_xt = 8'h32;
8'h31: keyb_xt = 8'h31;
8'h44: keyb_xt = 8'h18;
8'h4D: keyb_xt = 8'h19;
8'h15: keyb_xt = 8'h10;
8'h2D: keyb_xt = 8'h13;
8'h1B: keyb_xt = 8'h1F;
8'h2C: keyb_xt = 8'h14;
8'h3C: keyb_xt = 8'h16;
8'h2A: keyb_xt = 8'h2F;
8'h1D: keyb_xt = 8'h11;
8'h22: keyb_xt = 8'h2D;
8'h35: keyb_xt = 8'h15;
8'h1A: keyb_xt = 8'h2C;
8'h45: keyb_xt = 8'h0B;
8'h16: keyb_xt = 8'h02;
8'h1E: keyb_xt = 8'h03;
8'h26: keyb_xt = 8'h04;
8'h25: keyb_xt = 8'h05;
8'h2E: keyb_xt = 8'h06;
8'h36: keyb_xt = 8'h07;
8'h3D: keyb_xt = 8'h08;
8'h3E: keyb_xt = 8'h09;
8'h46: keyb_xt = 8'h0A;        
8'h0E: keyb_xt = 8'h29;
8'h4E: keyb_xt = 8'h0C;
8'h55: keyb_xt = 8'h0D;
8'h5D: keyb_xt = 8'h2B;
8'h54: keyb_xt = 8'h1A;
8'h5B: keyb_xt = 8'h1B;
8'h4C: keyb_xt = 8'h27;
8'h52: keyb_xt = 8'h28;
8'h41: keyb_xt = 8'h33;
8'h49: keyb_xt = 8'h34;
8'h4A: keyb_xt = 8'h35;
8'h66: keyb_xt = 8'h0E;
8'h29: keyb_xt = 8'h39;
8'h0D: keyb_xt = 8'h0F;
        

8'h58: keyb_xt = 8'h3A;
8'h12: keyb_xt = 8'h2A;
8'h14: keyb_xt = 8'h1D;
8'h11: keyb_xt = 8'h38;
8'h1F: keyb_xt = 8'h5B;
8'h59: keyb_xt = 8'h36;
8'h27: keyb_xt = 8'h5C;
8'h2F: keyb_xt = 8'h5D;
8'h5A: keyb_xt = 8'h1C;
        

8'h76: keyb_xt = 8'h01;        
8'h05: keyb_xt = 8'h3B;
8'h06: keyb_xt = 8'h3C;
8'h04: keyb_xt = 8'h3D;
8'h0C: keyb_xt = 8'h3E;
8'h03: keyb_xt = 8'h3F;
8'h0B: keyb_xt = 8'h40;
8'h83: keyb_xt = 8'h41;
8'h0A: keyb_xt = 8'h42;
8'h01: keyb_xt = 8'h43;
8'h09: keyb_xt = 8'h44;
8'h78: keyb_xt = 8'h57;
8'h07: keyb_xt = 8'h58;
8'h7E: keyb_xt = 8'h46;
        

8'h77: keyb_xt = 8'h45;
8'h7C: keyb_xt = 8'h37;
8'h7B: keyb_xt = 8'h4A;
8'h79: keyb_xt = 8'h4E;
8'h71: keyb_xt = 8'h53;                
8'h70: keyb_xt = 8'h52;
8'h69: keyb_xt = 8'h4F;
8'h72: keyb_xt = 8'h50;
8'h7A: keyb_xt = 8'h51;
8'h6B: keyb_xt = 8'h4B;
8'h73: keyb_xt = 8'h4C;
8'h74: keyb_xt = 8'h4D;
8'h6C: keyb_xt = 8'h47;
8'h75: keyb_xt = 8'h48;
8'h7D: keyb_xt = 8'h49;
        

        default: keyb_xt = ps2_data;
        
    endcase

end


always @(posedge clock50) begin


    keyb_jread <= {keyb_jread[0], port_read};


    if (ps2_data_clk) begin
    

           
        if (ps2_data == 8'hF0) begin
        
            keyb_unpressed <= 1'b1;

        end else begin
        

            keyb_ready1 <= keyb_ready1 ^ keyb_ready ^ 1'b1; 
            


            keyb_char   <= keyb_unpressed ? {1'b1, keyb_xt[6:0] } : keyb_xt;


            keyb_unpressed <= 1'b0;

        end
        
    end
        

    if ({keyb_jread[0], port_read} == 2'b10) begin
    
        case (port_addr)
        

            16'h0060: begin
            

                keyb_data   <= keyb_char;       
                

                keyb_ready2 <= keyb_ready2 ^ keyb_ready; 
                
            end
            

            16'h0064: keyb_data <= {7'h0, keyb_ready};
            
        endcase
        
    end

end


always @(negedge port_clk) begin

    case (port_addr)
    

        16'h03d4: begin g_index <= port_out[3:0]; end
        

        16'h03d5: case (g_index)
            
            4'hE: begin cursor[10:8] <= port_out[2:0]; end
            4'hF: begin cursor[7:0]  <= port_out[7:0]; end
            
        endcase
    
    endcase

end



endmodule
module port_controller(

    input  wire         clock50,
    input  wire  [15:0] port_addr,  
    output reg   [15:0] port_in,
    input  wire  [15:0] port_out,
    input  wire         port_bit,
    input  wire         port_clk,
    input  wire         port_read,
    

    input  wire [7:0]   ps2_data,
    input  wire         ps2_data_clk,
    

    output reg [10:0]   cursor
    
);



reg [3:0]   g_index = 1'b0;
initial     cursor = 11'h0;




always @* begin

    case (port_addr)
    
        16'h0060, 16'h0064: port_in = {8'h00, keyb_data};
        default: port_in = 1'b0;
        
    endcase

end





reg [7:0] keyb_char    = 8'h00;
reg       keyb_ready1  = 1'b0;
reg       keyb_ready2  = 1'b0;
wire      keyb_ready   = keyb_ready1 ^ keyb_ready2;
reg [1:0] keyb_jread   = 2'b00;
reg [7:0] keyb_data    = 8'h0;
reg [7:0] keyb_xt      = 8'h0;
reg       keyb_unpressed = 1'b0;

always @(*) begin

    case (ps2_data)
    
8'h1C: keyb_xt = 8'h1E;
8'h32: keyb_xt = 8'h30;
8'h21: keyb_xt = 8'h2E;
8'h23: keyb_xt = 8'h20;
8'h24: keyb_xt = 8'h12;
8'h2B: keyb_xt = 8'h21;
8'h34: keyb_xt = 8'h22;
8'h33: keyb_xt = 8'h23;
8'h43: keyb_xt = 8'h17;
8'h3B: keyb_xt = 8'h24;
8'h42: keyb_xt = 8'h25;
8'h4B: keyb_xt = 8'h26;
8'h3A: keyb_xt = 8'h32;
8'h31: keyb_xt = 8'h31;
8'h44: keyb_xt = 8'h18;
8'h4D: keyb_xt = 8'h19;
8'h15: keyb_xt = 8'h10;
8'h2D: keyb_xt = 8'h13;
8'h1B: keyb_xt = 8'h1F;
8'h2C: keyb_xt = 8'h14;
8'h3C: keyb_xt = 8'h16;
8'h2A: keyb_xt = 8'h2F;
8'h1D: keyb_xt = 8'h11;
8'h22: keyb_xt = 8'h2D;
8'h35: keyb_xt = 8'h15;
8'h1A: keyb_xt = 8'h2C;
8'h45: keyb_xt = 8'h0B;
8'h16: keyb_xt = 8'h02;
8'h1E: keyb_xt = 8'h03;
8'h26: keyb_xt = 8'h04;
8'h25: keyb_xt = 8'h05;
8'h2E: keyb_xt = 8'h06;
8'h36: keyb_xt = 8'h07;
8'h3D: keyb_xt = 8'h08;
8'h3E: keyb_xt = 8'h09;
8'h46: keyb_xt = 8'h0A;        
8'h0E: keyb_xt = 8'h29;
8'h4E: keyb_xt = 8'h0C;
8'h55: keyb_xt = 8'h0D;
8'h5D: keyb_xt = 8'h2B;
8'h54: keyb_xt = 8'h1A;
8'h5B: keyb_xt = 8'h1B;
8'h4C: keyb_xt = 8'h27;
8'h52: keyb_xt = 8'h28;
8'h41: keyb_xt = 8'h33;
8'h49: keyb_xt = 8'h34;
8'h4A: keyb_xt = 8'h35;
8'h66: keyb_xt = 8'h0E;
8'h29: keyb_xt = 8'h39;
8'h0D: keyb_xt = 8'h0F;
        

8'h58: keyb_xt = 8'h3A;
8'h12: keyb_xt = 8'h2A;
8'h14: keyb_xt = 8'h1D;
8'h11: keyb_xt = 8'h38;
8'h1F: keyb_xt = 8'h5B;
8'h59: keyb_xt = 8'h36;
8'h27: keyb_xt = 8'h5C;
8'h2F: keyb_xt = 8'h5D;
8'h5A: keyb_xt = 8'h1C;
        

8'h76: keyb_xt = 8'h01;        
8'h05: keyb_xt = 8'h3B;
8'h06: keyb_xt = 8'h3C;
8'h04: keyb_xt = 8'h3D;
8'h0C: keyb_xt = 8'h3E;
8'h03: keyb_xt = 8'h3F;
8'h0B: keyb_xt = 8'h40;
8'h83: keyb_xt = 8'h41;
8'h0A: keyb_xt = 8'h42;
8'h01: keyb_xt = 8'h43;
8'h09: keyb_xt = 8'h44;
8'h78: keyb_xt = 8'h57;
8'h07: keyb_xt = 8'h58;
8'h7E: keyb_xt = 8'h46;
        

8'h77: keyb_xt = 8'h45;
8'h7C: keyb_xt = 8'h37;
8'h7B: keyb_xt = 8'h4A;
8'h79: keyb_xt = 8'h4E;
8'h71: keyb_xt = 8'h53;                
8'h70: keyb_xt = 8'h52;
8'h69: keyb_xt = 8'h4F;
8'h72: keyb_xt = 8'h50;
8'h7A: keyb_xt = 8'h51;
8'h6B: keyb_xt = 8'h4B;
8'h73: keyb_xt = 8'h4C;
8'h74: keyb_xt = 8'h4D;
8'h6C: keyb_xt = 8'h47;
8'h75: keyb_xt = 8'h48;
8'h7D: keyb_xt = 8'h49;
        

        default: keyb_xt = ps2_data;
        
    endcase

end


always @(posedge clock50) begin


    keyb_jread <= {keyb_jread[0], port_read};


    if (ps2_data_clk) begin
    

           
        if (ps2_data == 8'hF0) begin
        
            keyb_unpressed <= 1'b1;

        end else begin
        

            keyb_ready1 <= keyb_ready1 ^ keyb_ready ^ 1'b1; 
            


            keyb_char   <= keyb_unpressed ? {1'b1, keyb_xt[6:0] } : keyb_xt;


            keyb_unpressed <= 1'b0;

        end
        
    end
        

    if ({keyb_jread[0], port_read} == 2'b10) begin
    
        case (port_addr)
        

            16'h0060: begin
            

                keyb_data   <= keyb_char;       
                

                keyb_ready2 <= keyb_ready2 ^ keyb_ready; 
                
            end
            

            16'h0064: keyb_data <= {7'h0, keyb_ready};
            
        endcase
        
    end

end


always @(negedge port_clk) begin

    case (port_addr)
    

        16'h03d4: begin g_index <= port_out[3:0]; end
        

        16'h03d5: case (g_index)
            
            4'hE: begin cursor[10:8] <= port_out[2:0]; end
            4'hF: begin cursor[7:0]  <= port_out[7:0]; end
            
        endcase
    
    endcase

end



endmodule