data/full_repos/permissive/105772342/tb/tb_conv8to16.v
 line:23: before: "("
1: b'%Error: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:25: syntax error, unexpected \'@\'\n  @(posedge clk) data8 <= _data8; valid8 <= _valid8; ready16 <= _ready16;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:29: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:32: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("tb_conv_8to16.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:33: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:34: syntax error, unexpected \'@\'\n  @(posedge clk) reset = 0;\n  ^\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:37: syntax error, unexpected \'@\'\n @(negedge clk) \n ^\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to16.v:38: syntax error, unexpected \'(\', expecting IDENTIFIER\n  stimulate(8\'h34, 1, 1);  \n            ^~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module tb_conv_8to16();
	reg clk = 0;
	reg reset = 1;
	reg [7:0] data8;
	reg valid8;
	wire ready8;
	wire [15:0] data16;
	wire valid16;
	reg ready16;

	task stimulate(input [7:0] _data8, input _valid8, input _ready16);
		begin
		@(posedge clk) data8 <= _data8; valid8 <= _valid8; ready16 <= _ready16;
		end
	endtask

	always #10 clk = ~clk;

	initial begin
		$dumpfile("tb_conv_8to16.vcd");
		$dumpvars;
		@(posedge clk) reset = 0;

		stimulate(8'h12, 1, 1);
		`expect(16'hXXXX, 0, 1);
		stimulate(8'h34, 1, 1);
		`expect(16'h1234, 1, 1);


		stimulate(8'h56, 0, 0);
		`expect(16'hXXXX, 0, 1);
		stimulate(8'h56, 1, 0);
		`expect(16'hXXXX, 0, 1);


		stimulate(8'h78, 0, 0);
		`expect(16'h5678, 0, 0);
		stimulate(8'h78, 0, 1);
		`expect(16'h5678, 0, 1);
		stimulate(8'h78, 1, 0);
		`expect(16'h5678, 0, 0);
		stimulate(8'h78, 1, 1);
		`expect(16'h5678, 1, 1);


		stimulate(8'hAB, 1, 1);
		`expect(16'hXXXX, 0, 1);
		stimulate(8'hBC, 1, 1);
		`expect(16'hABBC, 1, 1);

		stimulate(8'hCD, 1, 1);
		`expect(16'hXXXX, 0, 1);
		stimulate(8'hDE, 1, 1);
		`expect(16'hCDDE, 1, 1);

		stimulate(8'hEF, 1, 1);
		`expect(16'hXXXX, 0, 1);
		stimulate(8'hF0, 1, 1);
		`expect(16'hEFF0, 1, 1);

		stimulate(8'h01, 1, 1);
		`expect(16'hXXXX, 0, 1);
		stimulate(8'h12, 1, 1);
		`expect(16'h0112, 1, 1);
		$finish;
	end

	CONV_8TO16 conv_8to16(
			.clk_in(clk),
			.reset_in(reset),
			.data8_in(data8),
			.valid8_in(valid8),
			.ready8_out(ready8),
			.data16_out(data16),
			.valid16_out(valid16),
			.ready16_in(ready16));

endmodule
module tb_conv_8to16();

	reg clk = 0;
	reg reset = 1;
	reg [7:0] data8;
	reg valid8;
	wire ready8;
	wire [15:0] data16;
	wire valid16;
	reg ready16;

	task stimulate(input [7:0] _data8, input _valid8, input _ready16);
		begin
		@(posedge clk) data8 <= _data8; valid8 <= _valid8; ready16 <= _ready16;
		end
	endtask

	always #10 clk = ~clk;

	initial begin
		$dumpfile("tb_conv_8to16.vcd");
		$dumpvars;
		@(posedge clk) reset = 0;

		stimulate(8'h12, 1, 1);
		`expect(16'hXXXX, 0, 1);
		stimulate(8'h34, 1, 1);
		`expect(16'h1234, 1, 1);


		stimulate(8'h56, 0, 0);
		`expect(16'hXXXX, 0, 1);
		stimulate(8'h56, 1, 0);
		`expect(16'hXXXX, 0, 1);


		stimulate(8'h78, 0, 0);
		`expect(16'h5678, 0, 0);
		stimulate(8'h78, 0, 1);
		`expect(16'h5678, 0, 1);
		stimulate(8'h78, 1, 0);
		`expect(16'h5678, 0, 0);
		stimulate(8'h78, 1, 1);
		`expect(16'h5678, 1, 1);


		stimulate(8'hAB, 1, 1);
		`expect(16'hXXXX, 0, 1);
		stimulate(8'hBC, 1, 1);
		`expect(16'hABBC, 1, 1);

		stimulate(8'hCD, 1, 1);
		`expect(16'hXXXX, 0, 1);
		stimulate(8'hDE, 1, 1);
		`expect(16'hCDDE, 1, 1);

		stimulate(8'hEF, 1, 1);
		`expect(16'hXXXX, 0, 1);
		stimulate(8'hF0, 1, 1);
		`expect(16'hEFF0, 1, 1);

		stimulate(8'h01, 1, 1);
		`expect(16'hXXXX, 0, 1);
		stimulate(8'h12, 1, 1);
		`expect(16'h0112, 1, 1);
		$finish;
	end

	CONV_8TO16 conv_8to16(
			.clk_in(clk),
			.reset_in(reset),
			.data8_in(data8),
			.valid8_in(valid8),
			.ready8_out(ready8),
			.data16_out(data16),
			.valid16_out(valid16),
			.ready16_in(ready16));

endmodule