data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:11: Define or directive not defined: \'`RegDataWidth\'\n        input wire[`RegDataWidth-1:0] mem_wdata,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:12: Define or directive not defined: \'`RegAddrWidth\'\n        input wire[`RegAddrWidth-1:0] mem_wd,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:16: Define or directive not defined: \'`RegDataWidth\'\n        output reg[`RegDataWidth-1:0] wb_wdata,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:17: Define or directive not defined: \'`RegAddrWidth\'\n        output reg[`RegAddrWidth-1:0] wb_wd,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:23: Define or directive not defined: \'`RstEnable\'\n        if (rst == `RstEnable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:23: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (rst == `RstEnable) begin\n                             ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:24: Define or directive not defined: \'`ZeroWord\'\n            wb_wdata <= `ZeroWord;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:25: Define or directive not defined: \'`ZeroRegAddr\'\n            wb_wd <= `ZeroRegAddr;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:25: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            wb_wd <= `ZeroRegAddr;\n                                 ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:26: Define or directive not defined: \'`WriteDisable\'\n            wb_wreg <= `WriteDisable;\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:26: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            wb_wreg <= `WriteDisable;\n                                    ^\n%Error: Cannot continue\n'
module mem_wb(
        input wire clk,
        input wire rst,
		input wire[5:0] stall,
        

        input wire[`RegDataWidth-1:0] mem_wdata,
        input wire[`RegAddrWidth-1:0] mem_wd,
        input wire mem_wreg,
        

        output reg[`RegDataWidth-1:0] wb_wdata,
        output reg[`RegAddrWidth-1:0] wb_wd,
        output reg wb_wreg
    );
    
    always @ (posedge clk)
    begin
        if (rst == `RstEnable) begin
            wb_wdata <= `ZeroWord;
            wb_wd <= `ZeroRegAddr;
            wb_wreg <= `WriteDisable;
        end else if(!stall[4]) begin
            wb_wdata <= mem_wdata;
            wb_wd <= mem_wd;
            wb_wreg <= mem_wreg;
        end
    end
    
endmodule
module mem_wb(
        input wire clk,
        input wire rst,
		input wire[5:0] stall,
        

        input wire[`RegDataWidth-1:0] mem_wdata,
        input wire[`RegAddrWidth-1:0] mem_wd,
        input wire mem_wreg,
        

        output reg[`RegDataWidth-1:0] wb_wdata,
        output reg[`RegAddrWidth-1:0] wb_wd,
        output reg wb_wreg
    );

    
    always @ (posedge clk)
    begin
        if (rst == `RstEnable) begin
            wb_wdata <= `ZeroWord;
            wb_wd <= `ZeroRegAddr;
            wb_wreg <= `WriteDisable;
        end else if(!stall[4]) begin
            wb_wdata <= mem_wdata;
            wb_wd <= mem_wd;
            wb_wreg <= mem_wreg;
        end
    end
    
endmodule