data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv
 line:13: before: "read_ptr"
1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv:26: Cannot find file containing module: 'counter_ll'\ncounter_ll #(D) rd_ptr_cnt(CLK, RESET, RE & ~empty,  read_ptr);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/counter_ll\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/counter_ll.v\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/counter_ll.sv\n             counter_ll\n             counter_ll.v\n             counter_ll.sv\n             obj_dir/counter_ll\n             obj_dir/counter_ll.v\n             obj_dir/counter_ll.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv:27: Cannot find file containing module: 'counter'\ncounter    #(D) wr_ptr_cnt(CLK, RESET, WE & ~OVFLOW, write_ptr);\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv:28: Cannot find file containing module: 'ffd'\nffd        #(D) fill_fd(CLK, RESET, 1'b1, next_fill, fill);\n^~~\n%Error: Exiting due to 3 error(s)\n"
module simple_fifo #(parameter D = 11, W = 16)
                    ( input          CLK,
                      input          RESET,
                      input          RE,
                      input          WE,
                      output [W-1:0] R_DATA,
                      input  [W-1:0] W_DATA,
                      output [D-1:0] FILL,
                      output         NOT_EMPTY,
                      output         OVFLOW );

logic unsigned [D-1:0] read_ptr, write_ptr, next_fill, fill;
logic empty;





assign next_fill = write_ptr - read_ptr;
assign empty     = (fill == '0);
assign OVFLOW    = ((next_fill == '1) && WE);
assign NOT_EMPTY = ~empty;
assign FILL      = fill;

counter_ll #(D) rd_ptr_cnt(CLK, RESET, RE & ~empty,  read_ptr);
counter    #(D) wr_ptr_cnt(CLK, RESET, WE & ~OVFLOW, write_ptr);
ffd        #(D) fill_fd(CLK, RESET, 1'b1, next_fill, fill);

dp_ram  #(D, W) dp_ram ( .CLK    ( CLK       ),
                         .R_ADDR ( read_ptr  ),
                         .R_DATA ( R_DATA    ),
                         .WE     ( WE        ),
                         .W_ADDR ( write_ptr ),
                         .W_DATA ( W_DATA    ));

endmodule
module simple_fifo #(parameter D = 11, W = 16)
                    ( input          CLK,
                      input          RESET,
                      input          RE,
                      input          WE,
                      output [W-1:0] R_DATA,
                      input  [W-1:0] W_DATA,
                      output [D-1:0] FILL,
                      output         NOT_EMPTY,
                      output         OVFLOW );


logic unsigned [D-1:0] read_ptr, write_ptr, next_fill, fill;
logic empty;





assign next_fill = write_ptr - read_ptr;
assign empty     = (fill == '0);
assign OVFLOW    = ((next_fill == '1) && WE);
assign NOT_EMPTY = ~empty;
assign FILL      = fill;

counter_ll #(D) rd_ptr_cnt(CLK, RESET, RE & ~empty,  read_ptr);
counter    #(D) wr_ptr_cnt(CLK, RESET, WE & ~OVFLOW, write_ptr);
ffd        #(D) fill_fd(CLK, RESET, 1'b1, next_fill, fill);

dp_ram  #(D, W) dp_ram ( .CLK    ( CLK       ),
                         .R_ADDR ( read_ptr  ),
                         .R_DATA ( R_DATA    ),
                         .WE     ( WE        ),
                         .W_ADDR ( write_ptr ),
                         .W_DATA ( W_DATA    ));

endmodule