data/full_repos/permissive/144785545/progcounter.v
data/verilator_xmls/43ff008d-7f0b-4a44-ae96-827ffdb05fe9.xml
module PROGCOUNTER(
		input CLK,
		input LD,
		input  	  [3:0] IN,
		output reg [3:0] OUT
);

always @( posedge CLK ) begin
		if( LD == 1'b0 )
			OUT <= IN;
		else
			OUT <= OUT + 4'h1;
end

endmodule
module PROGCOUNTER(
		input CLK,
		input LD,
		input  	  [3:0] IN,
		output reg [3:0] OUT
);


always @( posedge CLK ) begin
		if( LD == 1'b0 )
			OUT <= IN;
		else
			OUT <= OUT + 4'h1;
end

endmodule