data/full_repos/permissive/210844779/lab1/1.b.1/fa.v
data/verilator_xmls/27ab5981-0240-407a-9160-23dec925454b.xml
module fa(A,B,C,Sum,Carry);

   input A,B,C;
   output Sum,Carry;
   
   wire [2:0]temp;
    
   xor u0(Sum,A,B,C);
   and u1(temp[0],A,B);
   and u2(temp[1],A,C);
   and u3(temp[2],B,C);
   or u4(Carry,temp[0],temp[1],temp[2]);

endmodule
module fa(A,B,C,Sum,Carry);


   input A,B,C;
   output Sum,Carry;
   
   wire [2:0]temp;
    
   xor u0(Sum,A,B,C);
   and u1(temp[0],A,B);
   and u2(temp[1],A,C);
   and u3(temp[2],B,C);
   or u4(Carry,temp[0],temp[1],temp[2]);

endmodule