data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v
'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte
1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:5: Cannot find include file: defines.v\n `include "defines.v" \n          ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:6: Cannot find include file: openmips.v\n `include "openmips.v" \n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:9: Cannot find include file: mem_sim.v\n `include "mem_sim.v" \n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:10: Cannot find include file: dcache.v\n `include "dcache.v" \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:11: Cannot find include file: icache.v\n `include "icache.v" \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:19: Define or directive not defined: \'`InstAddrBus\'\n   wire [`InstAddrBus] inst_addr;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   wire [`InstAddrBus] inst_addr;\n                     ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:20: Define or directive not defined: \'`InstBus\'\n   wire [`InstBus]     inst;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   wire [`InstBus]     inst;\n                 ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:27: Define or directive not defined: \'`RegBus\'\n   wire [`RegBus]      mem_addr_i;\n         ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   wire [`RegBus]      mem_addr_i;\n                ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:28: Define or directive not defined: \'`RegBus\'\n   wire [`RegBus]      mem_data_i;\n         ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   wire [`RegBus]      mem_data_i;\n                ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:29: Define or directive not defined: \'`RegBus\'\n   wire [`RegBus]      mem_data_o;\n         ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   wire [`RegBus]      mem_data_o;\n                ^\n%Error: Exiting due to 15 error(s)\n'
module openmips_min_sopc
  (
   input wire clk,
   input wire rst
   );

   wire [`InstAddrBus] inst_addr;
   wire [`InstBus]     inst;
   wire 	       rom_ce;
   wire 	       mem_ce;

   wire 	       mem_we_i;
   wire 	       mem_re_i;
   
   wire [`RegBus]      mem_addr_i;
   wire [`RegBus]      mem_data_i;
   wire [`RegBus]      mem_data_o;
   wire [3:0] 	       mem_sel_i;  
   
   wire 	       stallreq_from_if_cache;
   wire 	       stallreq_from_mem_cache;
   
   openmips openmips0
     (
      .clk(clk),
      .rst(rst),
      
      .rom_data_i(inst),
      .rom_addr_o(inst_addr),
      .rom_ce_o(rom_ce),      

      .ram_data_i(mem_data_o),
      .ram_addr_o(mem_addr_i),
      .ram_data_o(mem_data_i),
      .ram_we_o(mem_we_i),
      .ram_re_o(mem_re_i),
      .ram_sel_o(mem_sel_i),
      .ram_ce_o(mem_ce_i),		

      .stallreq_from_if_cache(stallreq_from_if_cache),
      .stallreq_from_mem_cache(stallreq_from_mem_cache)
      );
   
   wire 	       if_cache_req_o;
   wire [31:0]	       if_cache_addr_o;
   wire 	       if_cache_rep_i;
   wire [63:0] 	       if_cache_rep_data_i;   
   
   icache if_cache
     (
      .clk(clk),
      .rst(rst),
      .ce(rom_ce),
      
      .addr(inst_addr),

      .read_flag(1'b1),
      .read_data(inst),

      .cache_req_o(if_cache_req_o),
      .cache_addr_o(if_cache_addr_o),
      
      .cache_rep_i(if_cache_rep_i),
      .cache_rep_data_i(if_cache_rep_data_i),

      .stallreq(stallreq_from_if_cache)
      );

   wire 	       mem_cache_req_o;
   wire [31:0]	       mem_cache_addr_o;
   wire 	       mem_cache_write_o;
   wire [31:0]	       mem_cache_data_o;
   wire [3:0] 	       mem_cache_mask_o;
   wire 	       mem_cache_rep_i;
   wire [63:0]	       mem_cache_rep_data_i;
      
   dcache mem_cache
     (
      .clk(clk),
      .rst(rst),
      .ce(mem_ce),

      .addr(mem_addr_i),

      .read_flag(mem_re_i),
      .read_data(mem_data_o),

      .write_data(mem_data_i),
      .write_mask(mem_sel_i),
      .write_flag(mem_we_i),

      .cache_req_o(mem_cache_req_o),
      .cache_addr_o(mem_cache_addr_o),

      .cache_write_o(mem_cache_write_o),
      .cache_write_data_o(mem_cache_data_o),
      .cache_write_mask_o(mem_cache_mask_o),

      .cache_rep_i(mem_cache_rep_i),
      .cache_rep_data_i(mem_cache_rep_data_i),

      .stallreq(stallreq_from_mem_cache)
      );   
   
    mem_sim mem_sim0
     (
      .clk(clk),

      .if_ms_req_i(if_cache_req_o),
      .if_addr(if_cache_addr_o),

      .mem_ms_req_i(mem_cache_req_o),
      .mem_addr(mem_cache_addr_o),

      .ms_write_i(mem_cache_write_o),
      .ms_write_data_i(mem_cache_data_o),
      .ms_write_mask_i(mem_cache_mask_o),

      .if_ms_rep_o(if_cache_rep_i),
      .if_ms_rep_data_o(if_cache_rep_data_i),

      .mem_ms_rep_o(mem_cache_rep_i),
      .mem_ms_rep_data_o(mem_cache_rep_data_i)
      );
   
endmodule
module openmips_min_sopc
  (
   input wire clk,
   input wire rst
   );


   wire [`InstAddrBus] inst_addr;
   wire [`InstBus]     inst;
   wire 	       rom_ce;
   wire 	       mem_ce;

   wire 	       mem_we_i;
   wire 	       mem_re_i;
   
   wire [`RegBus]      mem_addr_i;
   wire [`RegBus]      mem_data_i;
   wire [`RegBus]      mem_data_o;
   wire [3:0] 	       mem_sel_i;  
   
   wire 	       stallreq_from_if_cache;
   wire 	       stallreq_from_mem_cache;
   
   openmips openmips0
     (
      .clk(clk),
      .rst(rst),
      
      .rom_data_i(inst),
      .rom_addr_o(inst_addr),
      .rom_ce_o(rom_ce),      

      .ram_data_i(mem_data_o),
      .ram_addr_o(mem_addr_i),
      .ram_data_o(mem_data_i),
      .ram_we_o(mem_we_i),
      .ram_re_o(mem_re_i),
      .ram_sel_o(mem_sel_i),
      .ram_ce_o(mem_ce_i),		

      .stallreq_from_if_cache(stallreq_from_if_cache),
      .stallreq_from_mem_cache(stallreq_from_mem_cache)
      );
   
   wire 	       if_cache_req_o;
   wire [31:0]	       if_cache_addr_o;
   wire 	       if_cache_rep_i;
   wire [63:0] 	       if_cache_rep_data_i;   
   
   icache if_cache
     (
      .clk(clk),
      .rst(rst),
      .ce(rom_ce),
      
      .addr(inst_addr),

      .read_flag(1'b1),
      .read_data(inst),

      .cache_req_o(if_cache_req_o),
      .cache_addr_o(if_cache_addr_o),
      
      .cache_rep_i(if_cache_rep_i),
      .cache_rep_data_i(if_cache_rep_data_i),

      .stallreq(stallreq_from_if_cache)
      );

   wire 	       mem_cache_req_o;
   wire [31:0]	       mem_cache_addr_o;
   wire 	       mem_cache_write_o;
   wire [31:0]	       mem_cache_data_o;
   wire [3:0] 	       mem_cache_mask_o;
   wire 	       mem_cache_rep_i;
   wire [63:0]	       mem_cache_rep_data_i;
      
   dcache mem_cache
     (
      .clk(clk),
      .rst(rst),
      .ce(mem_ce),

      .addr(mem_addr_i),

      .read_flag(mem_re_i),
      .read_data(mem_data_o),

      .write_data(mem_data_i),
      .write_mask(mem_sel_i),
      .write_flag(mem_we_i),

      .cache_req_o(mem_cache_req_o),
      .cache_addr_o(mem_cache_addr_o),

      .cache_write_o(mem_cache_write_o),
      .cache_write_data_o(mem_cache_data_o),
      .cache_write_mask_o(mem_cache_mask_o),

      .cache_rep_i(mem_cache_rep_i),
      .cache_rep_data_i(mem_cache_rep_data_i),

      .stallreq(stallreq_from_mem_cache)
      );   
   
    mem_sim mem_sim0
     (
      .clk(clk),

      .if_ms_req_i(if_cache_req_o),
      .if_addr(if_cache_addr_o),

      .mem_ms_req_i(mem_cache_req_o),
      .mem_addr(mem_cache_addr_o),

      .ms_write_i(mem_cache_write_o),
      .ms_write_data_i(mem_cache_data_o),
      .ms_write_mask_i(mem_cache_mask_o),

      .if_ms_rep_o(if_cache_rep_i),
      .if_ms_rep_data_o(if_cache_rep_data_i),

      .mem_ms_rep_o(mem_cache_rep_i),
      .mem_ms_rep_data_o(mem_cache_rep_data_i)
      );
   
endmodule