data/full_repos/permissive/108382235/Pipelined.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC,  SwitchClk_10, reset);\n       ^~~~~~~~~\n                                                                       : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_MEM.M_Dmemory\n  if (MemRead) ReadData=Dmemory[Address[31:2]];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_MEM.M_Dmemory\n  else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n                                                                    : ... In instance Pipelined\n   IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n                ^~\n%Error: Exiting due to 5 warning(s)\n'
module RegisterFile(rddata1,rddata2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, rdreg1,rdreg2,wrtreg,wrtdata,RegWrite,clock,reset);
	input [4:0] rdreg1,rdreg2,wrtreg;
	input [31:0] wrtdata;
	input RegWrite, clock, reset;

	output [31:0] rddata1,rddata2;

	output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;

	reg [31:0] rddata1,rddata2;
	reg [31:0] RegFile [31:0];


	reg [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
	integer i;

	always @(negedge clock, posedge reset) begin
		if (reset==1) begin
			for(i=0; i<32; i=i+1) 
				RegFile[i]=0;
		end
		else if (RegWrite) RegFile[wrtreg] = wrtdata;
	end
	always @(rdreg1, rdreg2, RegFile[rdreg1], RegFile[rdreg2]) begin

			rddata1 = RegFile[rdreg1]; 
			rddata2 = RegFile[rdreg2];

	end
	always @(RegFile[8], RegFile[9], RegFile[10], RegFile[11], RegFile[12], RegFile[13], RegFile[14], RegFile[15], RegFile[16], RegFile[17], RegFile[18], RegFile[19], RegFile[20], RegFile[21], RegFile[22], RegFile[23], RegFile[24], RegFile[25]) begin
		s0=RegFile[16];
		s1=RegFile[17];
		s2=RegFile[18];
		s3=RegFile[19];
		s4=RegFile[20];
		s5=RegFile[21];
		s6=RegFile[22];
		s7=RegFile[23];
		t0=RegFile[8];
		t1=RegFile[9];
		t2=RegFile[10];
		t3=RegFile[11];
		t4=RegFile[12];
		t5=RegFile[13];
		t6=RegFile[14];
		t7=RegFile[15];
		t8=RegFile[24];
		t9=RegFile[25];
	end
endmodule
module RegisterFile(rddata1,rddata2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, rdreg1,rdreg2,wrtreg,wrtdata,RegWrite,clock,reset);

	input [4:0] rdreg1,rdreg2,wrtreg;
	input [31:0] wrtdata;
	input RegWrite, clock, reset;

	output [31:0] rddata1,rddata2;

	output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;

	reg [31:0] rddata1,rddata2;
	reg [31:0] RegFile [31:0];


	reg [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
	integer i;

	always @(negedge clock, posedge reset) begin
		if (reset==1) begin
			for(i=0; i<32; i=i+1) 
				RegFile[i]=0;
		end
		else if (RegWrite) RegFile[wrtreg] = wrtdata;
	end
	always @(rdreg1, rdreg2, RegFile[rdreg1], RegFile[rdreg2]) begin

			rddata1 = RegFile[rdreg1]; 
			rddata2 = RegFile[rdreg2];

	end
	always @(RegFile[8], RegFile[9], RegFile[10], RegFile[11], RegFile[12], RegFile[13], RegFile[14], RegFile[15], RegFile[16], RegFile[17], RegFile[18], RegFile[19], RegFile[20], RegFile[21], RegFile[22], RegFile[23], RegFile[24], RegFile[25]) begin
		s0=RegFile[16];
		s1=RegFile[17];
		s2=RegFile[18];
		s3=RegFile[19];
		s4=RegFile[20];
		s5=RegFile[21];
		s6=RegFile[22];
		s7=RegFile[23];
		t0=RegFile[8];
		t1=RegFile[9];
		t2=RegFile[10];
		t3=RegFile[11];
		t4=RegFile[12];
		t5=RegFile[13];
		t6=RegFile[14];
		t7=RegFile[15];
		t8=RegFile[24];
		t9=RegFile[25];
	end
endmodule