data/full_repos/permissive/14593708/data/alu/arithmetic-addsub.v
data/verilator_xmls/da6e46e1-54bd-4861-84d2-dfc3b0a56dfd.xml
module full_adder(input  a,
                  input  b,
                  input  in_carry,
                  output sum,
                  output carry);

    wire sum0;
    wire carry0;
    wire carry1;

    xor (sum0, a, b);
    and (carry0, a, b);

    xor (sum, sum0, in_carry);
    and (carry1, sum0, in_carry);

    xor (carry, carry0, carry1);

endmodule
module full_adder(input  a,
                  input  b,
                  input  in_carry,
                  output sum,
                  output carry);


    wire sum0;
    wire carry0;
    wire carry1;

    xor (sum0, a, b);
    and (carry0, a, b);

    xor (sum, sum0, in_carry);
    and (carry1, sum0, in_carry);

    xor (carry, carry0, carry1);

endmodule