data/full_repos/permissive/115837888/source-7400/74181.v
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data/verilator_xmls/a2236118-a384-4645-b3c1-23cf1c2213b0.xml
module ttl_74181 #(parameter WIDTH = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
  input [3:0] Select,
  input Mode,
  input C_in,
  input [WIDTH-1:0] A_bar,
  input [WIDTH-1:0] B_bar,
  output CP_bar,
  output CG_bar,
  output Equal,
  output C_out,
  output [WIDTH-1:0] F_bar
);


reg CP_computed;
reg CG_computed;
wire Equal_computed;
reg C_computed;
reg [WIDTH-1:0] F_computed;
wire [WIDTH-1:0] P_internal;
wire [WIDTH-1:0] G_internal;
wire [WIDTH-1:0] C_internal;
wire [WIDTH-1:0] CG_internal;



generate
  genvar i;
  for (i = 0; i < WIDTH; i = i + 1)
  begin: gen_internals
    wire [WIDTH-1:0] C_and_P_term;
    wire [WIDTH-1:0] P_and_G_term;
    wire [WIDTH-1:0] G_term;





    assign P_internal[i] = ~(A_bar[i] & ~B_bar[i] & Select[2] | A_bar[i] & B_bar[i] & Select[3]);
    assign G_internal[i] = ~(A_bar[i] | B_bar[i] & Select[0] | ~B_bar[i] & Select[1]);

















    if (i == 0)
    begin
      assign C_and_P_term[i] = C_in & !Mode;
    end
    else
    begin
      localparam i_minus_1 = i - 1;

      assign C_and_P_term[i] = C_in & (&P_internal[i_minus_1:0]) & !Mode;

      assign G_term[i] = G_internal[i_minus_1] & !Mode;

      if (i > 1)
      begin
        genvar j;
        for (j = 0; j < i_minus_1; j = j + 1)
        begin: gen_P_and_G_term
          localparam j_plus_one = j + 1;


          assign P_and_G_term[j] = (&P_internal[i_minus_1:j_plus_one]) & G_internal[j] & !Mode;
        end
      end
    end


    if (i == 0)
    begin
      assign C_internal[i] = ~C_and_P_term[i];
    end
    else if (i == 1)
    begin
      assign C_internal[i] = ~(C_and_P_term[i] | G_term[i]);
    end
    else
    begin
      assign C_internal[i] = ~(C_and_P_term[i] | (|P_and_G_term[(i - 2):0]) | G_term[i]);
    end











    if (i < WIDTH - 1)
    begin
      assign CG_internal[i] = (&P_internal[(WIDTH - 1):(i + 1)]) & G_internal[i];
    end
    else
    begin
      assign CG_internal[i] = G_internal[i];
    end
  end
endgenerate

always @(*)
begin

  CP_computed = ~(&P_internal);
  CG_computed = ~(|CG_internal);


  C_computed = C_in & (&P_internal) | (|CG_internal);


  F_computed = P_internal ^ G_internal ^ C_internal;
end


assign Equal_computed = &F_computed;



assign #(DELAY_RISE, DELAY_FALL) CP_bar = CP_computed;
assign #(DELAY_RISE, DELAY_FALL) CG_bar = CG_computed;
assign #(DELAY_RISE, DELAY_FALL) Equal = Equal_computed;
assign #(DELAY_RISE, DELAY_FALL) C_out = C_computed;
assign #(DELAY_RISE, DELAY_FALL) F_bar = F_computed;

endmodule
module ttl_74181 #(parameter WIDTH = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
  input [3:0] Select,
  input Mode,
  input C_in,
  input [WIDTH-1:0] A_bar,
  input [WIDTH-1:0] B_bar,
  output CP_bar,
  output CG_bar,
  output Equal,
  output C_out,
  output [WIDTH-1:0] F_bar
);



reg CP_computed;
reg CG_computed;
wire Equal_computed;
reg C_computed;
reg [WIDTH-1:0] F_computed;
wire [WIDTH-1:0] P_internal;
wire [WIDTH-1:0] G_internal;
wire [WIDTH-1:0] C_internal;
wire [WIDTH-1:0] CG_internal;



generate
  genvar i;
  for (i = 0; i < WIDTH; i = i + 1)
  begin: gen_internals
    wire [WIDTH-1:0] C_and_P_term;
    wire [WIDTH-1:0] P_and_G_term;
    wire [WIDTH-1:0] G_term;





    assign P_internal[i] = ~(A_bar[i] & ~B_bar[i] & Select[2] | A_bar[i] & B_bar[i] & Select[3]);
    assign G_internal[i] = ~(A_bar[i] | B_bar[i] & Select[0] | ~B_bar[i] & Select[1]);

















    if (i == 0)
    begin
      assign C_and_P_term[i] = C_in & !Mode;
    end
    else
    begin
      localparam i_minus_1 = i - 1;

      assign C_and_P_term[i] = C_in & (&P_internal[i_minus_1:0]) & !Mode;

      assign G_term[i] = G_internal[i_minus_1] & !Mode;

      if (i > 1)
      begin
        genvar j;
        for (j = 0; j < i_minus_1; j = j + 1)
        begin: gen_P_and_G_term
          localparam j_plus_one = j + 1;


          assign P_and_G_term[j] = (&P_internal[i_minus_1:j_plus_one]) & G_internal[j] & !Mode;
        end
      end
    end


    if (i == 0)
    begin
      assign C_internal[i] = ~C_and_P_term[i];
    end
    else if (i == 1)
    begin
      assign C_internal[i] = ~(C_and_P_term[i] | G_term[i]);
    end
    else
    begin
      assign C_internal[i] = ~(C_and_P_term[i] | (|P_and_G_term[(i - 2):0]) | G_term[i]);
    end











    if (i < WIDTH - 1)
    begin
      assign CG_internal[i] = (&P_internal[(WIDTH - 1):(i + 1)]) & G_internal[i];
    end
    else
    begin
      assign CG_internal[i] = G_internal[i];
    end
  end
endgenerate

always @(*)
begin

  CP_computed = ~(&P_internal);
  CG_computed = ~(|CG_internal);


  C_computed = C_in & (&P_internal) | (|CG_internal);


  F_computed = P_internal ^ G_internal ^ C_internal;
end


assign Equal_computed = &F_computed;



assign #(DELAY_RISE, DELAY_FALL) CP_bar = CP_computed;
assign #(DELAY_RISE, DELAY_FALL) CG_bar = CG_computed;
assign #(DELAY_RISE, DELAY_FALL) Equal = Equal_computed;
assign #(DELAY_RISE, DELAY_FALL) C_out = C_computed;
assign #(DELAY_RISE, DELAY_FALL) F_bar = F_computed;

endmodule