data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v
1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:6: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input wire [`REG_ADDR_BUS]W_dstM_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`REG_ADDR_BUS]W_dstM_i,\n                             ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:7: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input wire [`REG_ADDR_BUS]W_dstE_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:8: Define or directive not defined: \'`DATA_BUS\'\n    input wire [`DATA_BUS]W_valM_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:9: Define or directive not defined: \'`DATA_BUS\'\n    input wire [`DATA_BUS]W_valE_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:10: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input wire [`REG_ADDR_BUS]D_rA_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:11: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input wire [`REG_ADDR_BUS]D_rB_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:13: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS]r_valA_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:14: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS]r_valB_o\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:17: Define or directive not defined: \'`DATA_BUS\'\n    reg [`DATA_BUS]registers[0:`NREG];\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:17: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`DATA_BUS]registers[0:`NREG];\n                  ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:17: Define or directive not defined: \'`NREG\'\n    reg [`DATA_BUS]registers[0:`NREG];\n                               ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:21: Define or directive not defined: \'`RST_EN\'\n            if(rst == ~`RST_EN && W_dstM_i < `NREG)\n                       ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:21: Define or directive not defined: \'`NREG\'\n            if(rst == ~`RST_EN && W_dstM_i < `NREG)\n                                             ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:29: Define or directive not defined: \'`RST_EN\'\n            if(rst == ~`RST_EN && W_dstE_i < `NREG)\n                       ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:29: Define or directive not defined: \'`NREG\'\n            if(rst == ~`RST_EN && W_dstE_i < `NREG)\n                                             ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:37: Define or directive not defined: \'`RST_EN\'\n            if(rst == `RST_EN || D_rA_i >= `NREG)\n                      ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:37: Define or directive not defined: \'`NREG\'\n            if(rst == `RST_EN || D_rA_i >= `NREG)\n                                           ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:39: Define or directive not defined: \'`DATA_ZERO\'\n                r_valA_o = `DATA_ZERO;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:57: Define or directive not defined: \'`RST_EN\'\n            if(rst == `RST_EN || D_rB_i >= `NREG)\n                      ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:57: Define or directive not defined: \'`NREG\'\n            if(rst == `RST_EN || D_rB_i >= `NREG)\n                                           ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/registers.v:59: Define or directive not defined: \'`DATA_ZERO\'\n                r_valB_o = `DATA_ZERO;\n                           ^~~~~~~~~~\n%Error: Exiting due to 23 error(s)\n'
module registers(
    input wire clk,
    input wire rst,
    input wire [`REG_ADDR_BUS]W_dstM_i,
    input wire [`REG_ADDR_BUS]W_dstE_i,
    input wire [`DATA_BUS]W_valM_i,
    input wire [`DATA_BUS]W_valE_i,
    input wire [`REG_ADDR_BUS]D_rA_i,
    input wire [`REG_ADDR_BUS]D_rB_i,
    
    output reg [`DATA_BUS]r_valA_o,
    output reg [`DATA_BUS]r_valB_o
    );
    
    reg [`DATA_BUS]registers[0:`NREG];
    
    always @(posedge clk)
        begin
            if(rst == ~`RST_EN && W_dstM_i < `NREG)
            begin
                registers[W_dstM_i] <= W_valM_i;
            end
        end
        
    always @(posedge clk)
        begin
            if(rst == ~`RST_EN && W_dstE_i < `NREG)
            begin
                registers[W_dstE_i] <= W_valE_i;
            end
        end
        
    always @(*)
        begin
            if(rst == `RST_EN || D_rA_i >= `NREG)
            begin
                r_valA_o = `DATA_ZERO;
            end
            else if(D_rA_i == W_dstM_i)
            begin
                r_valA_o = W_valM_i;
            end
            else if(D_rA_i == W_dstE_i)
            begin
                 r_valA_o = W_valE_i;
            end
            else
            begin
                r_valA_o = registers[D_rA_i];
            end
        end
        
    always @(*)
        begin
            if(rst == `RST_EN || D_rB_i >= `NREG)
            begin
                r_valB_o = `DATA_ZERO;
            end
            else if(D_rB_i == W_dstM_i)
            begin
                r_valB_o = W_valM_i;
            end
            else if(D_rB_i == W_dstE_i)
            begin
                r_valB_o = W_valE_i;
            end
            else
            begin
                r_valB_o = registers[D_rB_i];
            end
        end
endmodule
module registers(
    input wire clk,
    input wire rst,
    input wire [`REG_ADDR_BUS]W_dstM_i,
    input wire [`REG_ADDR_BUS]W_dstE_i,
    input wire [`DATA_BUS]W_valM_i,
    input wire [`DATA_BUS]W_valE_i,
    input wire [`REG_ADDR_BUS]D_rA_i,
    input wire [`REG_ADDR_BUS]D_rB_i,
    
    output reg [`DATA_BUS]r_valA_o,
    output reg [`DATA_BUS]r_valB_o
    );

    
    reg [`DATA_BUS]registers[0:`NREG];
    
    always @(posedge clk)
        begin
            if(rst == ~`RST_EN && W_dstM_i < `NREG)
            begin
                registers[W_dstM_i] <= W_valM_i;
            end
        end
        
    always @(posedge clk)
        begin
            if(rst == ~`RST_EN && W_dstE_i < `NREG)
            begin
                registers[W_dstE_i] <= W_valE_i;
            end
        end
        
    always @(*)
        begin
            if(rst == `RST_EN || D_rA_i >= `NREG)
            begin
                r_valA_o = `DATA_ZERO;
            end
            else if(D_rA_i == W_dstM_i)
            begin
                r_valA_o = W_valM_i;
            end
            else if(D_rA_i == W_dstE_i)
            begin
                 r_valA_o = W_valE_i;
            end
            else
            begin
                r_valA_o = registers[D_rA_i];
            end
        end
        
    always @(*)
        begin
            if(rst == `RST_EN || D_rB_i >= `NREG)
            begin
                r_valB_o = `DATA_ZERO;
            end
            else if(D_rB_i == W_dstM_i)
            begin
                r_valB_o = W_valM_i;
            end
            else if(D_rB_i == W_dstE_i)
            begin
                r_valB_o = W_valE_i;
            end
            else
            begin
                r_valB_o = registers[D_rB_i];
            end
        end
endmodule