data/full_repos/permissive/109846502/write_cycletb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/write_cycletb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/write_cycletb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  forever #1 clk = ~clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/write_cycletb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  forever #25 reg_sel = ~reg_sel;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/write_cycletb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  forever #25 wr_enable = ~wr_enable;\n          ^\n%Error: data/full_repos/permissive/109846502/write_cycletb.v:40: Cannot find file containing module: \'write_cycle\'\n write_cycle uut (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/write_cycle\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/write_cycle.v\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/write_cycle.sv\n             write_cycle\n             write_cycle.v\n             write_cycle.sv\n             obj_dir/write_cycle\n             obj_dir/write_cycle.v\n             obj_dir/write_cycle.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module write_cycletb;


	reg wr_enable;
	reg reg_sel;
	reg rst;
	reg clk;


	wire e_out;
	wire rs_out;
	wire rw_out;
	wire wr_finish;


	write_cycle uut (
		.wr_enable(wr_enable), 
		.reg_sel(reg_sel), 
		.rst(rst), 
		.clk(clk), 
		.e_out(e_out), 
		.rs_out(rs_out), 
		.rw_out(rw_out), 
		.wr_finish(wr_finish)
	);

	initial begin
		clk = 1'b0;
		rst = 1'b1;
		#1;
		rst = 1'b0;
		forever #1 clk = ~clk;
	end
	
	initial begin
		reg_sel = 1'b1;
		forever #25 reg_sel = ~reg_sel;
	end
	
	initial begin
		wr_enable = 1'b1;
		forever #25 wr_enable = ~wr_enable;
	end
	
      
endmodule
module write_cycletb;



	reg wr_enable;
	reg reg_sel;
	reg rst;
	reg clk;


	wire e_out;
	wire rs_out;
	wire rw_out;
	wire wr_finish;


	write_cycle uut (
		.wr_enable(wr_enable), 
		.reg_sel(reg_sel), 
		.rst(rst), 
		.clk(clk), 
		.e_out(e_out), 
		.rs_out(rs_out), 
		.rw_out(rw_out), 
		.wr_finish(wr_finish)
	);

	initial begin
		clk = 1'b0;
		rst = 1'b1;
		#1;
		rst = 1'b0;
		forever #1 clk = ~clk;
	end
	
	initial begin
		reg_sel = 1'b1;
		forever #25 reg_sel = ~reg_sel;
	end
	
	initial begin
		wr_enable = 1'b1;
		forever #25 wr_enable = ~wr_enable;
	end
	
      
endmodule