data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:570: Operator SUB expects 7 bits on the RHS, but RHS\'s VARREF \'master_readdatavalid\' generates 1 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_discards <= pending_discards + pending_reads - master_readdatavalid;\n                                                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:572: Operator COND expects 32 or 7 bits on the Conditional True, but Conditional True\'s VARREF \'master_burstcount\' generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_reads <= pending_reads + (avm_read_accepted ? master_burstcount : 0) - keep_read;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:572: Operator SUB expects 32 or 7 bits on the RHS, but RHS\'s VARREF \'keep_read\' generates 1 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_reads <= pending_reads + (avm_read_accepted ? master_burstcount : 0) - keep_read;\n                                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:573: Operator NOT expects 7 bits on the LHS, but LHS\'s VARREF \'finished_discard\' generates 1 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_discards <= pending_discards - (~finished_discard & master_readdatavalid);\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:573: Operator AND expects 7 bits on the RHS, but RHS\'s VARREF \'master_readdatavalid\' generates 1 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_discards <= pending_discards - (~finished_discard & master_readdatavalid);\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:418: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign user_read_addr_word   = (user_read_addr   >> MBYTE_SELECT_BITS);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:419: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign user_read_addr_r_word = (user_read_addr_r >> MBYTE_SELECT_BITS);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:420: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign avm_read_addr_word    = (avm_read_addr    >> MBYTE_SELECT_BITS);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:421: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign wr_addr_word          = (wr_addr          >> MBYTE_SELECT_BITS);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:422: Operator AND expects 27 bits on the RHS, but RHS\'s REPLICATE generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign wr_fifo_addr = wr_addr_word & {LOG2_DEPTH{1\'b1}};\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:422: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s AND generates 27 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign wr_fifo_addr = wr_addr_word & {LOG2_DEPTH{1\'b1}};\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:425: Operator AND expects 27 bits on the RHS, but RHS\'s REPLICATE generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign rd_fifo_addr = wait_for_read_int_r ? (user_read_addr_r_word & {LOG2_DEPTH{1\'b1}}) : \n                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:426: Operator AND expects 27 bits on the RHS, but RHS\'s REPLICATE generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                                                (user_read_addr_word   & {LOG2_DEPTH{1\'b1}}) ;\n                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:425: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s COND generates 27 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign rd_fifo_addr = wait_for_read_int_r ? (user_read_addr_r_word & {LOG2_DEPTH{1\'b1}}) : \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:428: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SUB generates 28 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign fifo_addr_diff = {1\'b0, avm_read_addr_word} - {1\'b0, user_read_addr_r_word};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:490: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 32 or 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size    <= (first_burst_boundary_word_address & 1) ? 1 : (MAXBURSTCOUNT - first_burst_boundary_word_address);\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:490: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'first_burst_boundary_word_address\' generates 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size    <= (first_burst_boundary_word_address & 1) ? 1 : (MAXBURSTCOUNT - first_burst_boundary_word_address);\n                                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:490: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size    <= (first_burst_boundary_word_address & 1) ? 1 : (MAXBURSTCOUNT - first_burst_boundary_word_address);\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:493: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'avm_burst_size\' generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_read_addr  <= (avm_read_addr + (avm_read_success ? (avm_burst_size << MBYTE_SELECT_BITS) : 0));\n                                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:494: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'avm_burst_boundary_word_address\' generates 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size <= avm_read_success_r ? (MAXBURSTCOUNT - avm_burst_boundary_word_address) : avm_burst_size;  \n                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:494: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'avm_burst_size\' generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size <= avm_read_success_r ? (MAXBURSTCOUNT - avm_burst_boundary_word_address) : avm_burst_size;  \n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:494: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size <= avm_read_success_r ? (MAXBURSTCOUNT - avm_burst_boundary_word_address) : avm_burst_size;  \n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:499: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'num_words_in_fifo\' generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_read <= (avm_ctrl_state == 2) & !empty & (fifo_addr_diff_overflow | (num_words_in_fifo < (DEPTH - MAXBURSTCOUNT)));  \n                                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:513: Operator AND expects 32 bits on the RHS, but RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n            assign first_burst_boundary_word_address = (user_read_addr_r >> MBYTE_SELECT_BITS) & {(BURSTCOUNT_WIDTH - 1){1\'b1}};\n                                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:513: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n            assign first_burst_boundary_word_address = (user_read_addr_r >> MBYTE_SELECT_BITS) & {(BURSTCOUNT_WIDTH - 1){1\'b1}};\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:514: Operator AND expects 32 bits on the RHS, but RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n            assign avm_burst_boundary_word_address   = (avm_read_addr >> MBYTE_SELECT_BITS)    & {(BURSTCOUNT_WIDTH - 1){1\'b1}};\n                                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:514: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n            assign avm_burst_boundary_word_address   = (avm_read_addr >> MBYTE_SELECT_BITS)    & {(BURSTCOUNT_WIDTH - 1){1\'b1}};\n                                                     ^\n%Error: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:83: Cannot find file containing module: \'acl_data_fifo\'\nacl_data_fifo #(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules,data/full_repos/permissive/205229557/acl_data_fifo\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules,data/full_repos/permissive/205229557/acl_data_fifo.v\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules,data/full_repos/permissive/205229557/acl_data_fifo.sv\n             acl_data_fifo\n             acl_data_fifo.v\n             acl_data_fifo.sv\n             obj_dir/acl_data_fifo\n             obj_dir/acl_data_fifo.v\n             obj_dir/acl_data_fifo.sv\n%Error: Exiting due to 1 error(s), 27 warning(s)\n'
module lsu_streaming_prefetch_avalon_bust_master #(
        parameter AWIDTH           = 32,
        parameter MWIDTH           = 256,
        parameter MWIDTH_BYTES     = 32,
        parameter BURSTCOUNT_WIDTH = 6,
        parameter FIFO_DEPTH_LOG2   = 5
    ) (
        input clk,
        input reset,
        input flush,
        output active,


        output                            ready,
        input            [AWIDTH - 1 : 0] fifo_read_addr,
        input                             fifo_read,
        input  [BURSTCOUNT_WIDTH - 1 : 0] fifo_burst_size,
        output                            fifo_data_valid,
        output            [MWIDTH -1 : 0] fifo_data,


        output           [AWIDTH - 1 : 0] master_address,
        output                            master_read,
        output     [MWIDTH_BYTES - 1 : 0] master_byteenable,
        input            [MWIDTH - 1 : 0] master_readdata,
        input                             master_readdatavalid,
        output [BURSTCOUNT_WIDTH - 1 : 0] master_burstcount,
        input                             master_waitrequest
    );

    reg  [FIFO_DEPTH_LOG2 : 0] pending_reads;
    reg  [FIFO_DEPTH_LOG2 : 0] pending_discards;
    wire                      keep_read;
    wire                      avm_read_accepted;
    wire                      finished_discard;
    wire                      can_discard_full_burst;


    always @(posedge clk or posedge reset) begin
        if (reset) begin
            pending_reads <= 0;
            pending_discards <= 0;
        end else begin
            if (flush) begin
                pending_reads <= 0;
                pending_discards <= pending_discards + pending_reads - master_readdatavalid;
            end else begin
                pending_reads <= pending_reads + (avm_read_accepted ? master_burstcount : 0) - keep_read;
                pending_discards <= pending_discards - (~finished_discard & master_readdatavalid);
            end
        end
    end

    assign finished_discard = (pending_discards == 0);
    assign can_discard_full_burst = ~pending_discards[FIFO_DEPTH_LOG2];
    assign keep_read = finished_discard & master_readdatavalid;
    assign avm_read_accepted = master_read & !master_waitrequest;


    assign ready = !master_waitrequest & can_discard_full_burst;

    assign master_address = fifo_read_addr;
    assign master_read = fifo_read & can_discard_full_burst & !flush;
    assign master_byteenable = {MWIDTH_BYTES{1'b1}};
    assign master_burstcount = fifo_burst_size;

    assign fifo_data = master_readdata;
    assign fifo_data_valid = keep_read;

    assign active = |pending_reads | ~finished_discard;

endmodule
module lsu_streaming_prefetch_avalon_bust_master #(
        parameter AWIDTH           = 32,
        parameter MWIDTH           = 256,
        parameter MWIDTH_BYTES     = 32,
        parameter BURSTCOUNT_WIDTH = 6,
        parameter FIFO_DEPTH_LOG2   = 5
    ) (
        input clk,
        input reset,
        input flush,
        output active,


        output                            ready,
        input            [AWIDTH - 1 : 0] fifo_read_addr,
        input                             fifo_read,
        input  [BURSTCOUNT_WIDTH - 1 : 0] fifo_burst_size,
        output                            fifo_data_valid,
        output            [MWIDTH -1 : 0] fifo_data,


        output           [AWIDTH - 1 : 0] master_address,
        output                            master_read,
        output     [MWIDTH_BYTES - 1 : 0] master_byteenable,
        input            [MWIDTH - 1 : 0] master_readdata,
        input                             master_readdatavalid,
        output [BURSTCOUNT_WIDTH - 1 : 0] master_burstcount,
        input                             master_waitrequest
    );


    reg  [FIFO_DEPTH_LOG2 : 0] pending_reads;
    reg  [FIFO_DEPTH_LOG2 : 0] pending_discards;
    wire                      keep_read;
    wire                      avm_read_accepted;
    wire                      finished_discard;
    wire                      can_discard_full_burst;


    always @(posedge clk or posedge reset) begin
        if (reset) begin
            pending_reads <= 0;
            pending_discards <= 0;
        end else begin
            if (flush) begin
                pending_reads <= 0;
                pending_discards <= pending_discards + pending_reads - master_readdatavalid;
            end else begin
                pending_reads <= pending_reads + (avm_read_accepted ? master_burstcount : 0) - keep_read;
                pending_discards <= pending_discards - (~finished_discard & master_readdatavalid);
            end
        end
    end

    assign finished_discard = (pending_discards == 0);
    assign can_discard_full_burst = ~pending_discards[FIFO_DEPTH_LOG2];
    assign keep_read = finished_discard & master_readdatavalid;
    assign avm_read_accepted = master_read & !master_waitrequest;


    assign ready = !master_waitrequest & can_discard_full_burst;

    assign master_address = fifo_read_addr;
    assign master_read = fifo_read & can_discard_full_burst & !flush;
    assign master_byteenable = {MWIDTH_BYTES{1'b1}};
    assign master_burstcount = fifo_burst_size;

    assign fifo_data = master_readdata;
    assign fifo_data_valid = keep_read;

    assign active = |pending_reads | ~finished_discard;

endmodule