data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v
 line:59: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:42: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("address_generator_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:43: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, address_generator_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10 rst_n = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10 rst_n = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #10 strand_offset = 320;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #20 strand_idx = 50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #20 strand_idx = 99;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #20 strand_idx = 100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #20 strand_idx = 101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #20 strand_offset = 640;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #20 strand_idx = 50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #20 strand_idx = 100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #20 strand_idx = 101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/address_generator_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #500 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module address_generator_tb;

    parameter MEM_ADDR_WIDTH = 24;
    parameter STRAND_PARAM_WIDTH = 16;

    reg clk = 0;
    reg rst_n = 1;

    reg [STRAND_PARAM_WIDTH-1:0] strand_offset = 0;
    reg [STRAND_PARAM_WIDTH-1:0] strand_idx = 0;
    reg [STRAND_PARAM_WIDTH-1:0] strand_length = 100;

    wire [MEM_ADDR_WIDTH-1:0] addr;


    address_generator #(MEM_ADDR_WIDTH) ag_inst (
            .clk(clk),
            .rst_n(rst_n),
            .strand_offset(strand_offset),
            .strand_idx(strand_idx),
            .strand_length(strand_length),
            .addr(addr)
        );


    always #10 clk = !clk;


    initial begin

        $dumpfile("address_generator_tb.vcd");
        $dumpvars(0, address_generator_tb);

        #10 rst_n = 0;
        #10 rst_n = 1;
        #10 strand_offset = 320;
        strand_idx = 1;
        #20 strand_idx = 50;
        #20 strand_idx = 99;
        #20 strand_idx = 100;
        #20 strand_idx = 101;
        #20 strand_offset = 640;
        strand_idx = 1;
        #20 strand_idx = 50;
        #20 strand_idx = 100;
        #20 strand_idx = 101;

        #500 $finish;
    end

endmodule
module address_generator_tb;


    parameter MEM_ADDR_WIDTH = 24;
    parameter STRAND_PARAM_WIDTH = 16;

    reg clk = 0;
    reg rst_n = 1;

    reg [STRAND_PARAM_WIDTH-1:0] strand_offset = 0;
    reg [STRAND_PARAM_WIDTH-1:0] strand_idx = 0;
    reg [STRAND_PARAM_WIDTH-1:0] strand_length = 100;

    wire [MEM_ADDR_WIDTH-1:0] addr;


    address_generator #(MEM_ADDR_WIDTH) ag_inst (
            .clk(clk),
            .rst_n(rst_n),
            .strand_offset(strand_offset),
            .strand_idx(strand_idx),
            .strand_length(strand_length),
            .addr(addr)
        );


    always #10 clk = !clk;


    initial begin

        $dumpfile("address_generator_tb.vcd");
        $dumpvars(0, address_generator_tb);

        #10 rst_n = 0;
        #10 rst_n = 1;
        #10 strand_offset = 320;
        strand_idx = 1;
        #20 strand_idx = 50;
        #20 strand_idx = 99;
        #20 strand_idx = 100;
        #20 strand_idx = 101;
        #20 strand_offset = 640;
        strand_idx = 1;
        #20 strand_idx = 50;
        #20 strand_idx = 100;
        #20 strand_idx = 101;

        #500 $finish;
    end

endmodule