data/full_repos/permissive/113780415/src/top_test.v
 line:1736: before: "&&"
1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(posedge clk && enable == 1'b1)\n                                   ^~\n%Error: Cannot continue\n"
module comparator(x, y, greater, lower, same, enable);

	input [4:0] x;

	input [4:0] y;

	output reg [4:0] greater;

	input enable;

	output reg [4:0] lower;

	output reg same;

	

	always @(*)

		begin

		if (enable == 1'b1)

			if (x > y)

				begin

					greater <= x;

				lower <= y;

				same <= 1'b0;

				end

			else if (x < y)

				begin

				greater <= y;

				lower <= x;

				same <= 1'b0;

				end

			else

				begin

				greater <= 5'b00000;

				lower <= 5'b00000;

				same <= 1'b1;

				end

		

	end

endmodule
module comparator(x, y, greater, lower, same, enable);


	input [4:0] x;

	input [4:0] y;

	output reg [4:0] greater;

	input enable;

	output reg [4:0] lower;

	output reg same;

	

	always @(*)

		begin

		if (enable == 1'b1)

			if (x > y)

				begin

					greater <= x;

				lower <= y;

				same <= 1'b0;

				end

			else if (x < y)

				begin

				greater <= y;

				lower <= x;

				same <= 1'b0;

				end

			else

				begin

				greater <= 5'b00000;

				lower <= 5'b00000;

				same <= 1'b1;

				end

		

	end

endmodule