data/full_repos/permissive/173099254/lab3/cod.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10 Aa=1; Ab=1; Ac=1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10 SELa=1; SELb=1; SELc=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #10 Aa=0; Ba=1; Ab=0; Bb=1; Ac=0; Bc=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10 Cin=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #10 Cin=0; B=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10 Cin=1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #10 A=1; Cin=0; B=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10 Cin=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #10 Cin=0; B=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #10 Cin=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:84: Unsupported: Ignoring delay on this delayed statement.\n   #10 A=i;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:87: Unsupported: Ignoring delay on this delayed statement.\n     #10 B=j;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab3/cod.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #10 SEL=i;\n  ^\n%Warning-MULTITOP: data/full_repos/permissive/173099254/lab3/cod.v:47: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                     : ... Top module \'mux_2_1_test\'\nmodule mux_2_1_test();\n       ^~~~~~~~~~~~\n                                                                     : ... Top module \'test_sum_2\'\nmodule test_sum_2();\n       ^~~~~~~~~~\n                                                                     : ... Top module \'sum4_test\'\nmodule sum4_test();\n       ^~~~~~~~~\n                                                                     : ... Top module \'mux_8_1_test\'\nmodule mux_8_1_test();\n       ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173099254/lab3/cod.v:102: Signal definition not found, creating implicitly: \'out30\'\n                                                                      : ... Suggested alternative: \'out\'\nmux4_1 MUX1(IN[3:0], SEL[1:0], out30);\n                               ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173099254/lab3/cod.v:103: Signal definition not found, creating implicitly: \'out74\'\n                                                                      : ... Suggested alternative: \'out\'\nmux4_1 MUX2(IN[7:4], SEL[1:0], out74);\n                               ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173099254/lab3/cod.v:65: Signal definition not found, creating implicitly: \'w1\'\nsum_1 sum0(A[0], B[0], Cin, w1, S[0]);\n                            ^~\n%Warning-IMPLICIT: data/full_repos/permissive/173099254/lab3/cod.v:66: Signal definition not found, creating implicitly: \'w2\'\n                                                                     : ... Suggested alternative: \'w1\'\nsum_1 sum1(A[1], B[1], w1, w2, S[1]);\n                           ^~\n%Warning-IMPLICIT: data/full_repos/permissive/173099254/lab3/cod.v:67: Signal definition not found, creating implicitly: \'w3\'\n                                                                     : ... Suggested alternative: \'w1\'\nsum_1 sum2(A[2], B[2], w2, w3, S[2]);\n                           ^~\n%Warning-IMPLICIT: data/full_repos/permissive/173099254/lab3/cod.v:6: Signal definition not found, creating implicitly: \'w3\'\n                                                                    : ... Suggested alternative: \'s3\'\nand gate2_SI(w3, SEL, B);\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab3/cod.v:65: Input port connection \'Cin\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'Cin\' generates 4 bits.\n                                                                  : ... In instance sum4_test.nume\nsum_1 sum0(A[0], B[0], Cin, w1, S[0]);\n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab3/cod.v:117: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                   : ... In instance mux_8_1_test\n  #10 SEL=i;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab3/cod.v:84: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                  : ... In instance sum4_test\n   #10 A=i;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab3/cod.v:87: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                  : ... In instance sum4_test\n     #10 B=j;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/173099254/lab3/cod.v:91: Input port connection \'Cin\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'Cin\' generates 1 bits.\n                                                                  : ... In instance sum4_test\nsum_4 nume(A,B,Cin, Cout,S);\n               ^~~\n%Error: Exiting due to 25 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux2_1_a(input SEL, A, B, output out);

wire w1, w2, s3;
not gate_NU(w1, SEL);
and gate1_SI(w2, w1, A);
and gate2_SI(w3, SEL, B);
or gate_SAU(out, w2, w3);

endmodule
module mux2_1_a(input SEL, A, B, output out);


wire w1, w2, s3;
not gate_NU(w1, SEL);
and gate1_SI(w2, w1, A);
and gate2_SI(w3, SEL, B);
or gate_SAU(out, w2, w3);

endmodule