data/full_repos/permissive/153866423/_magiccubeImageProcess.srcs/magiccubeImageProcess.srcs_18_12_07/sources_1/imports/MyScripts/vga_cube/clk_div.v
data/verilator_xmls/7013df3a-3dd6-4849-aa58-d084c248c895.xml
module clk_div(
    input clk,
    output clk25,
    output clk1Hz
    );
reg [27:0]state;
always@(posedge clk)
begin
  state <= state+1'b1;
end
assign clk25=state[1];
assign clk1Hz=state[26];
endmodule
module clk_div(
    input clk,
    output clk25,
    output clk1Hz
    );

reg [27:0]state;
always@(posedge clk)
begin
  state <= state+1'b1;
end
assign clk25=state[1];
assign clk1Hz=state[26];
endmodule