data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v:11: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS local_input_clock50_instance (.I(local_clock50_in_p), .IB(local_clock50_in_n), .O(clock50));\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.sv\n             IBUFGDS\n             IBUFGDS.v\n             IBUFGDS.sv\n             obj_dir/IBUFGDS\n             obj_dir/IBUFGDS.v\n             obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v:32: Cannot find file containing module: \'simplepll_BASE\'\n simplepll_BASE #(.OVERALL_DIVIDE(1), .MULTIPLY(10), .DIVIDE0(4), .PHASE0(0.0), .PERIOD(20.0)) other (.clockin(clock50), .reset(reset), .clock0out(rawclock125), .locked(other_pll_locked));  \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v:34: Cannot find file containing module: \'BUFG\'\n BUFG mrt (.I(rawclock125), .O(clock125));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test033.clock50_sine500.althea.revA.v:36: Cannot find file containing module: \'ocyrus_single8\'\n ocyrus_single8 #(.BIT_DEPTH(8), .PERIOD(8.0), .DIVIDE(1), .MULTIPLY(8), .SCOPE("BUFPLL"), .MODE("WORD_CLOCK_IN")) mylei (.clock_in(clock125), .reset(reset), .word_clock_out(), .word_in(clock_word), .D_out(clock500_oddr), .locked(oserdes_pll_locked));\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module mza_test033_clock50_sine500_althea_top (
	input clock50_p, clock50_n,
	output lemo,
	output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
);
	mza_test033_clock50_sine500_althea sharona (
		.local_clock50_in_p(clock50_p), .local_clock50_in_n(clock50_n),
		.lemo(lemo),
		.led_0(led_0), .led_1(led_1), .led_2(led_2), .led_3(led_3),
		.led_4(led_4), .led_5(led_5), .led_6(led_6), .led_7(led_7)
	);
endmodule
module mza_test033_clock50_sine500_althea_top (
	input clock50_p, clock50_n,
	output lemo,
	output led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7
);

	mza_test033_clock50_sine500_althea sharona (
		.local_clock50_in_p(clock50_p), .local_clock50_in_n(clock50_n),
		.lemo(lemo),
		.led_0(led_0), .led_1(led_1), .led_2(led_2), .led_3(led_3),
		.led_4(led_4), .led_5(led_5), .led_6(led_6), .led_7(led_7)
	);
endmodule