data/full_repos/permissive/143278/ivltests/pr1087.v
 line:61: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1087.v:54: Unsupported: Ignoring delay on this delayed statement.\nalways #5 CLOCK=~CLOCK;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1087.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #5 nARST=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1087.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #5 nARST=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1087.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #200 $display("PASSED");\n  ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TEST_COUNTER;

parameter M = 2;
parameter CBITS = 2;

reg	CLOCK;
reg	nARST;
reg	CTRL_I;

wire[M*CBITS-1:0]	COUNTS;

MULTIPLE_COUNTERS #(.M(M),
		    .CBITS(CBITS)) INST_MCTR(CLOCK, nARST, COUNTS);

initial CLOCK=1;
always #5 CLOCK=~CLOCK;

initial
  begin
  nARST=1;
  #5 nARST=0;
  #5 nARST=1;
  #200 $display("PASSED");
  $finish;
  end


endmodule
module TEST_COUNTER;


parameter M = 2;
parameter CBITS = 2;

reg	CLOCK;
reg	nARST;
reg	CTRL_I;

wire[M*CBITS-1:0]	COUNTS;

MULTIPLE_COUNTERS #(.M(M),
		    .CBITS(CBITS)) INST_MCTR(CLOCK, nARST, COUNTS);

initial CLOCK=1;
always #5 CLOCK=~CLOCK;

initial
  begin
  nARST=1;
  #5 nARST=0;
  #5 nARST=1;
  #200 $display("PASSED");
  $finish;
  end


endmodule