data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_main.v
 line:45: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_main.v:37: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD/2) \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_main.v:45: Unsupported: Ignoring delay on this delayed statement.\n        repeat (1*2) #CLK_PERIOD\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_main.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_main.v:51: Unsupported: Ignoring delay on this delayed statement.\n        repeat (1*2) #CLK_PERIOD\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_main.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #CLK_PERIOD\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_main.v:58: Unsupported: Ignoring delay on this delayed statement.\n        repeat(8*2) #CLK_PERIOD\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_main.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*2)\n        ^\n%Error: data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches/tb_main.v:25: Cannot find file containing module: \'main\'\n    main #(0) utt (\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches,data/full_repos/permissive/212763527/main\n             data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches,data/full_repos/permissive/212763527/main.v\n             data/full_repos/permissive/212763527/school_project/16_Mealy/testbenches,data/full_repos/permissive/212763527/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_main;

    reg clk;
    reg rst;


    reg [7:0] din;
    reg read;
    reg btnclk;


    wire ldclk;
    wire ldres;
    wire ldrst;

    initial begin
        din = 8'b0100_1011;
        btnclk = 1'b0;
        clk = 1'b0;
        rst = 1'b1;
    end
    
    main #(0) utt (
        din,
        read,
        rst,
        clk,
        btnclk,
        ldrst,
        ldclk,
        ldres
    );

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;

    initial begin

        read = 1'b1;


        repeat (1*2) #CLK_PERIOD
            btnclk = ~btnclk;
        #3
        rst = 1'b0;


        repeat (1*2) #CLK_PERIOD
            btnclk = ~btnclk;
        #CLK_PERIOD

        read = 1'b0;


        repeat(8*2) #CLK_PERIOD
            btnclk = ~btnclk;
        
        #(CLK_PERIOD*2)

        $finish;
    end

endmodule
module tb_main;


    reg clk;
    reg rst;


    reg [7:0] din;
    reg read;
    reg btnclk;


    wire ldclk;
    wire ldres;
    wire ldrst;

    initial begin
        din = 8'b0100_1011;
        btnclk = 1'b0;
        clk = 1'b0;
        rst = 1'b1;
    end
    
    main #(0) utt (
        din,
        read,
        rst,
        clk,
        btnclk,
        ldrst,
        ldclk,
        ldres
    );

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;

    initial begin

        read = 1'b1;


        repeat (1*2) #CLK_PERIOD
            btnclk = ~btnclk;
        #3
        rst = 1'b0;


        repeat (1*2) #CLK_PERIOD
            btnclk = ~btnclk;
        #CLK_PERIOD

        read = 1'b0;


        repeat(8*2) #CLK_PERIOD
            btnclk = ~btnclk;
        
        #(CLK_PERIOD*2)

        $finish;
    end

endmodule