data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:144: Operator VAR \'STATE_IDLE\' expects 4 bits on the Initial value, but Initial value\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n    STATE_IDLE = 3\'d0,\n    ^~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:145: Operator VAR \'STATE_RUN\' expects 4 bits on the Initial value, but Initial value\'s CONST \'3\'h1\' generates 3 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n    STATE_RUN = 3\'d1,\n    ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:146: Operator VAR \'STATE_TABLE_1\' expects 4 bits on the Initial value, but Initial value\'s CONST \'3\'h2\' generates 3 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n    STATE_TABLE_1 = 3\'d2,\n    ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:147: Operator VAR \'STATE_TABLE_2\' expects 4 bits on the Initial value, but Initial value\'s CONST \'3\'h3\' generates 3 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n    STATE_TABLE_2 = 3\'d3,\n    ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:148: Operator VAR \'STATE_TABLE_3\' expects 4 bits on the Initial value, but Initial value\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n    STATE_TABLE_3 = 3\'d4;\n    ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:150: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\nreg [4:0] state_reg = STATE_IDLE, state_next;\n                      ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:190: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n    state_next = STATE_IDLE;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:219: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_RUN\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_RUN;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:221: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_IDLE;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:237: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_RUN\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_RUN;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:245: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_RUN\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_RUN;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:255: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_RUN\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_RUN;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:260: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_1\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_1;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:268: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_IDLE;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:272: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_RUN\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_RUN;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:281: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_2\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_2;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:286: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_1\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_1;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:290: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_RUN\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_RUN;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:298: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_IDLE;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:302: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_1\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_1;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:313: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_3\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_3;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:318: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_1\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_1;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:322: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_RUN\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_RUN;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:330: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_IDLE;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:334: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_2\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_2;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:350: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_3\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_3;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:358: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_3\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_3;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:366: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_3\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_3;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:376: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_3\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_3;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:381: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_1\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_1;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:385: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_2\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_2;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:389: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_RUN\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_RUN;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:397: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_IDLE;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:401: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_TABLE_3\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n                    state_next = STATE_TABLE_3;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:213: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'STATE_IDLE\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n        case (state_reg)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:213: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'STATE_RUN\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n        case (state_reg)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:213: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'STATE_TABLE_1\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n        case (state_reg)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:213: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'STATE_TABLE_2\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n        case (state_reg)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:213: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'STATE_TABLE_3\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n        case (state_reg)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:410: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE_IDLE\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n        state_reg <= STATE_IDLE;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_RTCC_Op.v:450: Operator NEQ expects 5 bits on the RHS, but RHS\'s VARREF \'STATE_IDLE\' generates 4 bits.\n                                                                                               : ... In instance PMOD_RTCC_Op\n        busy_reg <= (state_reg != STATE_IDLE);\n                               ^~\n%Error: Exiting due to 41 warning(s)\n'
module PMOD_RTCC_Op (
    input  wire        clk,
    input  wire        rst,

    input wire [6:0]   dev_addr,
    input wire [7:0]   reg_addr,
    input wire [7:0]   reg_data,


    output wire [6:0]  cmd_address,
    output wire        cmd_start,
    output wire        cmd_read,
    output wire        cmd_write,
    output wire        cmd_write_multiple,
    output wire        cmd_stop,
    output wire        cmd_valid,
    input  wire        cmd_ready,

    output wire [7:0]  data_out,
    output wire        data_out_valid,
    input  wire        data_out_ready,
    output wire        data_out_last,


    output wire        busy,


    input  wire        start
);




localparam INIT_DATA_LEN = 4;

localparam [3:0]
    STATE_IDLE = 3'd0,
    STATE_RUN = 3'd1,
    STATE_TABLE_1 = 3'd2,
    STATE_TABLE_2 = 3'd3,
    STATE_TABLE_3 = 3'd4;

reg [4:0] state_reg = STATE_IDLE, state_next;

parameter AW = $clog2(INIT_DATA_LEN);

reg [8:0] init_data_reg = 9'd0;

reg [AW-1:0] address_reg = {AW{1'b0}}, address_next;
reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next;
reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next;

reg [6:0] cur_address_reg = 7'd0, cur_address_next;

reg [6:0] cmd_address_reg = 7'd0, cmd_address_next;
reg cmd_start_reg = 1'b0, cmd_start_next;
reg cmd_write_reg = 1'b0, cmd_write_next;
reg cmd_stop_reg = 1'b0, cmd_stop_next;
reg cmd_valid_reg = 1'b0, cmd_valid_next;

reg [7:0] data_out_reg = 8'd0, data_out_next;
reg data_out_valid_reg = 1'b0, data_out_valid_next;

reg start_flag_reg = 1'b0, start_flag_next;

reg busy_reg = 1'b0;

assign cmd_address = cmd_address_reg;
assign cmd_start = cmd_start_reg;
assign cmd_read = 1'b0;
assign cmd_write = cmd_write_reg;
assign cmd_write_multiple = 1'b0;
assign cmd_stop = cmd_stop_reg;
assign cmd_valid = cmd_valid_reg;

assign data_out = data_out_reg;
assign data_out_valid = data_out_valid_reg;
assign data_out_last = 1'b1;

assign busy = busy_reg;

always @* begin
    state_next = STATE_IDLE;

    address_next = address_reg;
    address_ptr_next = address_ptr_reg;
    data_ptr_next = data_ptr_reg;

    cur_address_next = cur_address_reg;

    cmd_address_next = cmd_address_reg;
    cmd_start_next = cmd_start_reg & ~(cmd_valid & cmd_ready);
    cmd_write_next = cmd_write_reg & ~(cmd_valid & cmd_ready);
    cmd_stop_next = cmd_stop_reg & ~(cmd_valid & cmd_ready);
    cmd_valid_next = cmd_valid_reg & ~cmd_ready;

    data_out_next = data_out_reg;
    data_out_valid_next = data_out_valid_reg & ~data_out_ready;

    start_flag_next = start_flag_reg;

    if (cmd_valid | data_out_valid) begin

        state_next = state_reg;
    end else begin
        case (state_reg)
            STATE_IDLE: begin

                if (~start_flag_reg & start) begin
                    address_next = {AW{1'b0}};
                    start_flag_next = 1'b1;
                    state_next = STATE_RUN;
                end else begin
                    state_next = STATE_IDLE;
                end
            end
            STATE_RUN: begin

                if (init_data_reg[8] == 1'b1) begin

                    cmd_write_next = 1'b1;
                    cmd_stop_next = 1'b0;
                    cmd_valid_next = 1'b1;

                    data_out_next = init_data_reg[7:0];
                    data_out_valid_next = 1'b1;
                    
                    address_next = address_reg + 1;
                    
                    state_next = STATE_RUN;
                end else if (init_data_reg[8:7] == 2'b01) begin

                    cmd_address_next = init_data_reg[6:0];
                    cmd_start_next = 1'b1;

                    address_next = address_reg + 1;
                    
                    state_next = STATE_RUN;
                end else if (init_data_reg == 9'b001000001) begin

                    cmd_write_next = 1'b0;
                    cmd_start_next = 1'b0;
                    cmd_stop_next = 1'b1;
                    cmd_valid_next = 1'b1;

                    address_next = address_reg + 1;

                    state_next = STATE_RUN;
                end else if (init_data_reg == 9'b000001001) begin

                    data_ptr_next = address_reg + 1;
                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_1;
                end else if (init_data_reg == 9'd0) begin

                    cmd_start_next = 1'b0;
                    cmd_write_next = 1'b0;
                    cmd_stop_next = 1'b1;
                    cmd_valid_next = 1'b1;

                    state_next = STATE_IDLE;
                end else begin

                    address_next = address_reg + 1;
                    state_next = STATE_RUN;
                end
            end
            STATE_TABLE_1: begin

                if (init_data_reg == 9'b000001000) begin

                    address_ptr_next = address_reg + 1;
                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_2;
                end else if (init_data_reg == 9'b000001001) begin

                    data_ptr_next = address_reg + 1;
                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_1;
                end else if (init_data_reg == 1) begin

                    address_next = address_reg + 1;
                    state_next = STATE_RUN;
                end else if (init_data_reg == 9'd0) begin

                    cmd_start_next = 1'b0;
                    cmd_write_next = 1'b0;
                    cmd_stop_next = 1'b1;
                    cmd_valid_next = 1'b1;

                    state_next = STATE_IDLE;
                end else begin

                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_1;
                end
            end
            STATE_TABLE_2: begin

                if (init_data_reg[8:7] == 2'b01) begin


                    cur_address_next = init_data_reg[6:0];
                    address_ptr_next = address_reg + 1;
                    address_next = data_ptr_reg;
                    state_next = STATE_TABLE_3;
                end else if (init_data_reg == 9'b000001001) begin

                    data_ptr_next = address_reg + 1;
                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_1;
                end else if (init_data_reg == 9'd1) begin

                    address_next = address_reg + 1;
                    state_next = STATE_RUN;
                end else if (init_data_reg == 9'd0) begin

                    cmd_start_next = 1'b0;
                    cmd_write_next = 1'b0;
                    cmd_stop_next = 1'b1;
                    cmd_valid_next = 1'b1;

                    state_next = STATE_IDLE;
                end else begin

                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_2;
                end
            end
            STATE_TABLE_3: begin

                if (init_data_reg[8] == 1'b1) begin

                    cmd_write_next = 1'b1;
                    cmd_stop_next = 1'b0;
                    cmd_valid_next = 1'b1;

                    data_out_next = init_data_reg[7:0];
                    data_out_valid_next = 1'b1;

                    address_next = address_reg + 1;

                    state_next = STATE_TABLE_3;
                end else if (init_data_reg[8:7] == 2'b01) begin

                    cmd_address_next = init_data_reg[6:0];
                    cmd_start_next = 1'b1;

                    address_next = address_reg + 1;

                    state_next = STATE_TABLE_3;
                end else if (init_data_reg == 9'b000000011) begin

                    cmd_address_next = cur_address_reg;
                    cmd_start_next = 1'b1;

                    address_next = address_reg + 1;

                    state_next = STATE_TABLE_3;
                end else if (init_data_reg == 9'b001000001) begin

                    cmd_write_next = 1'b0;
                    cmd_start_next = 1'b0;
                    cmd_stop_next = 1'b1;
                    cmd_valid_next = 1'b1;

                    address_next = address_reg + 1;

                    state_next = STATE_TABLE_3;
                end else if (init_data_reg == 9'b000001001) begin

                    data_ptr_next = address_reg + 1;
                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_1;
                end else if (init_data_reg == 9'b000001000) begin

                    address_next = address_ptr_reg;
                    state_next = STATE_TABLE_2;
                end else if (init_data_reg == 9'd1) begin

                    address_next = address_reg + 1;
                    state_next = STATE_RUN;
                end else if (init_data_reg == 9'd0) begin

                    cmd_start_next = 1'b0;
                    cmd_write_next = 1'b0;
                    cmd_stop_next = 1'b1;
                    cmd_valid_next = 1'b1;

                    state_next = STATE_IDLE;
                end else begin

                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_3;
                end
            end
        endcase
    end
end

always @(posedge clk) begin
    if (rst) begin
        state_reg <= STATE_IDLE;

        init_data_reg <= 9'd0;

        address_reg <= {AW{1'b0}};
        address_ptr_reg <= {AW{1'b0}};
        data_ptr_reg <= {AW{1'b0}};

        cur_address_reg <= 7'd0;

        cmd_valid_reg <= 1'b0;

        data_out_valid_reg <= 1'b0;

        start_flag_reg <= 1'b0;

        busy_reg <= 1'b0;
    end else begin
        state_reg <= state_next;


        case (address_next)
            0: init_data_reg <= {2'b01, dev_addr};
            1: init_data_reg <= {1'b1 , reg_addr};
            2: init_data_reg <= {1'b1 , reg_data};
            3: init_data_reg <= 9'b0;
        endcase

        address_reg <= address_next;
        address_ptr_reg <= address_ptr_next;
        data_ptr_reg <= data_ptr_next;

        cur_address_reg <= cur_address_next;

        cmd_valid_reg <= cmd_valid_next;

        data_out_valid_reg <= data_out_valid_next;

        start_flag_reg <= start & start_flag_next;

        busy_reg <= (state_reg != STATE_IDLE);
    end

    cmd_address_reg <= cmd_address_next;
    cmd_start_reg <= cmd_start_next;
    cmd_write_reg <= cmd_write_next;
    cmd_stop_reg <= cmd_stop_next;

    data_out_reg <= data_out_next;
end

endmodule
module PMOD_RTCC_Op (
    input  wire        clk,
    input  wire        rst,

    input wire [6:0]   dev_addr,
    input wire [7:0]   reg_addr,
    input wire [7:0]   reg_data,


    output wire [6:0]  cmd_address,
    output wire        cmd_start,
    output wire        cmd_read,
    output wire        cmd_write,
    output wire        cmd_write_multiple,
    output wire        cmd_stop,
    output wire        cmd_valid,
    input  wire        cmd_ready,

    output wire [7:0]  data_out,
    output wire        data_out_valid,
    input  wire        data_out_ready,
    output wire        data_out_last,


    output wire        busy,


    input  wire        start
);





localparam INIT_DATA_LEN = 4;

localparam [3:0]
    STATE_IDLE = 3'd0,
    STATE_RUN = 3'd1,
    STATE_TABLE_1 = 3'd2,
    STATE_TABLE_2 = 3'd3,
    STATE_TABLE_3 = 3'd4;

reg [4:0] state_reg = STATE_IDLE, state_next;

parameter AW = $clog2(INIT_DATA_LEN);

reg [8:0] init_data_reg = 9'd0;

reg [AW-1:0] address_reg = {AW{1'b0}}, address_next;
reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next;
reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next;

reg [6:0] cur_address_reg = 7'd0, cur_address_next;

reg [6:0] cmd_address_reg = 7'd0, cmd_address_next;
reg cmd_start_reg = 1'b0, cmd_start_next;
reg cmd_write_reg = 1'b0, cmd_write_next;
reg cmd_stop_reg = 1'b0, cmd_stop_next;
reg cmd_valid_reg = 1'b0, cmd_valid_next;

reg [7:0] data_out_reg = 8'd0, data_out_next;
reg data_out_valid_reg = 1'b0, data_out_valid_next;

reg start_flag_reg = 1'b0, start_flag_next;

reg busy_reg = 1'b0;

assign cmd_address = cmd_address_reg;
assign cmd_start = cmd_start_reg;
assign cmd_read = 1'b0;
assign cmd_write = cmd_write_reg;
assign cmd_write_multiple = 1'b0;
assign cmd_stop = cmd_stop_reg;
assign cmd_valid = cmd_valid_reg;

assign data_out = data_out_reg;
assign data_out_valid = data_out_valid_reg;
assign data_out_last = 1'b1;

assign busy = busy_reg;

always @* begin
    state_next = STATE_IDLE;

    address_next = address_reg;
    address_ptr_next = address_ptr_reg;
    data_ptr_next = data_ptr_reg;

    cur_address_next = cur_address_reg;

    cmd_address_next = cmd_address_reg;
    cmd_start_next = cmd_start_reg & ~(cmd_valid & cmd_ready);
    cmd_write_next = cmd_write_reg & ~(cmd_valid & cmd_ready);
    cmd_stop_next = cmd_stop_reg & ~(cmd_valid & cmd_ready);
    cmd_valid_next = cmd_valid_reg & ~cmd_ready;

    data_out_next = data_out_reg;
    data_out_valid_next = data_out_valid_reg & ~data_out_ready;

    start_flag_next = start_flag_reg;

    if (cmd_valid | data_out_valid) begin

        state_next = state_reg;
    end else begin
        case (state_reg)
            STATE_IDLE: begin

                if (~start_flag_reg & start) begin
                    address_next = {AW{1'b0}};
                    start_flag_next = 1'b1;
                    state_next = STATE_RUN;
                end else begin
                    state_next = STATE_IDLE;
                end
            end
            STATE_RUN: begin

                if (init_data_reg[8] == 1'b1) begin

                    cmd_write_next = 1'b1;
                    cmd_stop_next = 1'b0;
                    cmd_valid_next = 1'b1;

                    data_out_next = init_data_reg[7:0];
                    data_out_valid_next = 1'b1;
                    
                    address_next = address_reg + 1;
                    
                    state_next = STATE_RUN;
                end else if (init_data_reg[8:7] == 2'b01) begin

                    cmd_address_next = init_data_reg[6:0];
                    cmd_start_next = 1'b1;

                    address_next = address_reg + 1;
                    
                    state_next = STATE_RUN;
                end else if (init_data_reg == 9'b001000001) begin

                    cmd_write_next = 1'b0;
                    cmd_start_next = 1'b0;
                    cmd_stop_next = 1'b1;
                    cmd_valid_next = 1'b1;

                    address_next = address_reg + 1;

                    state_next = STATE_RUN;
                end else if (init_data_reg == 9'b000001001) begin

                    data_ptr_next = address_reg + 1;
                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_1;
                end else if (init_data_reg == 9'd0) begin

                    cmd_start_next = 1'b0;
                    cmd_write_next = 1'b0;
                    cmd_stop_next = 1'b1;
                    cmd_valid_next = 1'b1;

                    state_next = STATE_IDLE;
                end else begin

                    address_next = address_reg + 1;
                    state_next = STATE_RUN;
                end
            end
            STATE_TABLE_1: begin

                if (init_data_reg == 9'b000001000) begin

                    address_ptr_next = address_reg + 1;
                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_2;
                end else if (init_data_reg == 9'b000001001) begin

                    data_ptr_next = address_reg + 1;
                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_1;
                end else if (init_data_reg == 1) begin

                    address_next = address_reg + 1;
                    state_next = STATE_RUN;
                end else if (init_data_reg == 9'd0) begin

                    cmd_start_next = 1'b0;
                    cmd_write_next = 1'b0;
                    cmd_stop_next = 1'b1;
                    cmd_valid_next = 1'b1;

                    state_next = STATE_IDLE;
                end else begin

                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_1;
                end
            end
            STATE_TABLE_2: begin

                if (init_data_reg[8:7] == 2'b01) begin


                    cur_address_next = init_data_reg[6:0];
                    address_ptr_next = address_reg + 1;
                    address_next = data_ptr_reg;
                    state_next = STATE_TABLE_3;
                end else if (init_data_reg == 9'b000001001) begin

                    data_ptr_next = address_reg + 1;
                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_1;
                end else if (init_data_reg == 9'd1) begin

                    address_next = address_reg + 1;
                    state_next = STATE_RUN;
                end else if (init_data_reg == 9'd0) begin

                    cmd_start_next = 1'b0;
                    cmd_write_next = 1'b0;
                    cmd_stop_next = 1'b1;
                    cmd_valid_next = 1'b1;

                    state_next = STATE_IDLE;
                end else begin

                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_2;
                end
            end
            STATE_TABLE_3: begin

                if (init_data_reg[8] == 1'b1) begin

                    cmd_write_next = 1'b1;
                    cmd_stop_next = 1'b0;
                    cmd_valid_next = 1'b1;

                    data_out_next = init_data_reg[7:0];
                    data_out_valid_next = 1'b1;

                    address_next = address_reg + 1;

                    state_next = STATE_TABLE_3;
                end else if (init_data_reg[8:7] == 2'b01) begin

                    cmd_address_next = init_data_reg[6:0];
                    cmd_start_next = 1'b1;

                    address_next = address_reg + 1;

                    state_next = STATE_TABLE_3;
                end else if (init_data_reg == 9'b000000011) begin

                    cmd_address_next = cur_address_reg;
                    cmd_start_next = 1'b1;

                    address_next = address_reg + 1;

                    state_next = STATE_TABLE_3;
                end else if (init_data_reg == 9'b001000001) begin

                    cmd_write_next = 1'b0;
                    cmd_start_next = 1'b0;
                    cmd_stop_next = 1'b1;
                    cmd_valid_next = 1'b1;

                    address_next = address_reg + 1;

                    state_next = STATE_TABLE_3;
                end else if (init_data_reg == 9'b000001001) begin

                    data_ptr_next = address_reg + 1;
                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_1;
                end else if (init_data_reg == 9'b000001000) begin

                    address_next = address_ptr_reg;
                    state_next = STATE_TABLE_2;
                end else if (init_data_reg == 9'd1) begin

                    address_next = address_reg + 1;
                    state_next = STATE_RUN;
                end else if (init_data_reg == 9'd0) begin

                    cmd_start_next = 1'b0;
                    cmd_write_next = 1'b0;
                    cmd_stop_next = 1'b1;
                    cmd_valid_next = 1'b1;

                    state_next = STATE_IDLE;
                end else begin

                    address_next = address_reg + 1;
                    state_next = STATE_TABLE_3;
                end
            end
        endcase
    end
end

always @(posedge clk) begin
    if (rst) begin
        state_reg <= STATE_IDLE;

        init_data_reg <= 9'd0;

        address_reg <= {AW{1'b0}};
        address_ptr_reg <= {AW{1'b0}};
        data_ptr_reg <= {AW{1'b0}};

        cur_address_reg <= 7'd0;

        cmd_valid_reg <= 1'b0;

        data_out_valid_reg <= 1'b0;

        start_flag_reg <= 1'b0;

        busy_reg <= 1'b0;
    end else begin
        state_reg <= state_next;


        case (address_next)
            0: init_data_reg <= {2'b01, dev_addr};
            1: init_data_reg <= {1'b1 , reg_addr};
            2: init_data_reg <= {1'b1 , reg_data};
            3: init_data_reg <= 9'b0;
        endcase

        address_reg <= address_next;
        address_ptr_reg <= address_ptr_next;
        data_ptr_reg <= data_ptr_next;

        cur_address_reg <= cur_address_next;

        cmd_valid_reg <= cmd_valid_next;

        data_out_valid_reg <= data_out_valid_next;

        start_flag_reg <= start & start_flag_next;

        busy_reg <= (state_reg != STATE_IDLE);
    end

    cmd_address_reg <= cmd_address_next;
    cmd_start_reg <= cmd_start_next;
    cmd_write_reg <= cmd_write_next;
    cmd_stop_reg <= cmd_stop_next;

    data_out_reg <= data_out_next;
end

endmodule