data/full_repos/permissive/200314387/verilog/74154/hct74154.v
data/verilator_xmls/17cd5d40-5475-4365-b877-618cce1aea4d.xml
module hct74154(_E0, _E1, A, Y);
    input _E0, _E1;
    input [3:0] A;
    output [15:0] Y;

    wire [15:0] x = 16'hffff ^ (2**A);
    
    assign #(13) Y = !_E0 & !_E1 ? x: 16'hffff;

endmodule
module hct74154(_E0, _E1, A, Y);

    input _E0, _E1;
    input [3:0] A;
    output [15:0] Y;

    wire [15:0] x = 16'hffff ^ (2**A);
    
    assign #(13) Y = !_E0 & !_E1 ? x: 16'hffff;

endmodule