data/full_repos/permissive/128426084/src/sources_1/new/draw_rect_char.v
1: b'%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_rect_char.v:21: Cannot find include file: verilog_macro_bus.vh\n`include "verilog_macro_bus.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.v\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.sv\n             verilog_macro_bus.vh\n             verilog_macro_bus.vh.v\n             verilog_macro_bus.vh.sv\n             obj_dir/verilog_macro_bus.vh\n             obj_dir/verilog_macro_bus.vh.v\n             obj_dir/verilog_macro_bus.vh.sv\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_rect_char.v:25: Define or directive not defined: \'`VGA_BUS_SIZE\'\n    input wire [`VGA_BUS_SIZE-1:0] vga_in,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_rect_char.v:30: Define or directive not defined: \'`VGA_BUS_SIZE\'\n    output wire [`VGA_BUS_SIZE-1:0] vga_out\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_rect_char.v:33: Define or directive not defined: \'`VGA_SPLIT_INPUT\'\n    `VGA_SPLIT_INPUT(vga_in)\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_rect_char.v:33: syntax error, unexpected \'(\'\n    `VGA_SPLIT_INPUT(vga_in)\n                     ^~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_rect_char.v:34: Define or directive not defined: \'`VGA_OUT_REG\'\n    `VGA_OUT_REG\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/draw_rect_char.v:35: Define or directive not defined: \'`VGA_MERGE_AT_OUTPUT\'\n    `VGA_MERGE_AT_OUTPUT(vga_out)\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module draw_rect_char(
    input wire pclk,
    input wire [`VGA_BUS_SIZE-1:0] vga_in,
    input wire [7:0] char_pixels,
    input wire playerCount,
    output wire [7:0] char_xy,
    output wire [3:0] char_line,
    output wire [`VGA_BUS_SIZE-1:0] vga_out
);

    `VGA_SPLIT_INPUT(vga_in)
    `VGA_OUT_REG
    `VGA_MERGE_AT_OUTPUT(vga_out)
   
reg [11:0] rgb_nxt;
reg [10:0] hcount_char, vcount_char;
reg choose = 1;

localparam HCOUNT = 100;
localparam VCOUNT = 250;
localparam color = 12'hfff;
localparam color_c = 12'h0ff;
    
 always @*
 begin
    hcount_char = hcount_in - HCOUNT;
    vcount_char = vcount_in - VCOUNT;
    
    if((hblnk_in == 0) && (vblnk_in == 0))
        if (char_pixels[7 - hcount_char[2:0]] == 1)
            if ((hcount_char[10:7] == 0) && (vcount_char[10:8] == 0)) rgb_nxt =(vcount_char[7:4] == 0)?((playerCount == 0)?12'hff0:12'hf_f_f):
            (vcount_char[7:4] == 6)?((playerCount == 1)? 12'hff0:12'hfff):rgb_in;
            else  rgb_nxt = rgb_in;
        else rgb_nxt = rgb_in;
    else rgb_nxt = rgb_in;
 
 
 end   
  
 always @(posedge pclk)
 begin
    hcount_out <= hcount_in;
     hsync_out <= hsync_in;
     hblnk_out <= hblnk_in;
     vcount_out <= vcount_in;
     vsync_out <= vsync_in;
     vblnk_out <= vblnk_in;
     rgb_out <= rgb_nxt;
 end    
    
   
   assign char_xy = {vcount_char[7:4],hcount_char[6:3]};
   assign char_line = vcount_char[3:0];
    
endmodule
module draw_rect_char(
    input wire pclk,
    input wire [`VGA_BUS_SIZE-1:0] vga_in,
    input wire [7:0] char_pixels,
    input wire playerCount,
    output wire [7:0] char_xy,
    output wire [3:0] char_line,
    output wire [`VGA_BUS_SIZE-1:0] vga_out
);


    `VGA_SPLIT_INPUT(vga_in)
    `VGA_OUT_REG
    `VGA_MERGE_AT_OUTPUT(vga_out)
   
reg [11:0] rgb_nxt;
reg [10:0] hcount_char, vcount_char;
reg choose = 1;

localparam HCOUNT = 100;
localparam VCOUNT = 250;
localparam color = 12'hfff;
localparam color_c = 12'h0ff;
    
 always @*
 begin
    hcount_char = hcount_in - HCOUNT;
    vcount_char = vcount_in - VCOUNT;
    
    if((hblnk_in == 0) && (vblnk_in == 0))
        if (char_pixels[7 - hcount_char[2:0]] == 1)
            if ((hcount_char[10:7] == 0) && (vcount_char[10:8] == 0)) rgb_nxt =(vcount_char[7:4] == 0)?((playerCount == 0)?12'hff0:12'hf_f_f):
            (vcount_char[7:4] == 6)?((playerCount == 1)? 12'hff0:12'hfff):rgb_in;
            else  rgb_nxt = rgb_in;
        else rgb_nxt = rgb_in;
    else rgb_nxt = rgb_in;
 
 
 end   
  
 always @(posedge pclk)
 begin
    hcount_out <= hcount_in;
     hsync_out <= hsync_in;
     hblnk_out <= hblnk_in;
     vcount_out <= vcount_in;
     vsync_out <= vsync_in;
     vblnk_out <= vblnk_in;
     rgb_out <= rgb_nxt;
 end    
    
   
   assign char_xy = {vcount_char[7:4],hcount_char[6:3]};
   assign char_line = vcount_char[3:0];
    
endmodule