data/full_repos/permissive/109936328/pipeline/me.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/pipeline/me.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:32: Define or directive not defined: \'`ADDR_W\'\n  input [`ADDR_W - 1:0] i_pc;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:33: Define or directive not defined: \'`INSTR_W\'\n  input [`INSTR_W - 1:0] i_instr;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:35: Define or directive not defined: \'`DEST_SRC_W\'\n  input [`DEST_SRC_W - 1:0] i_dest_src;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:36: Define or directive not defined: \'`REG_IDX_W\'\n  input [`REG_IDX_W - 1:0] i_dest_reg;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:38: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_alu_eval;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:39: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_mem_read;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:41: Define or directive not defined: \'`MEM_OP_W\'\n  input [`MEM_OP_W -1:0] i_mem_op;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:43: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] r_pc;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:44: Define or directive not defined: \'`INSTR_W\'\n  reg [`INSTR_W - 1:0] r_instr;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:46: Define or directive not defined: \'`DEST_SRC_W\'\n  reg [`DEST_SRC_W - 1:0] r_dest_src;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:47: Define or directive not defined: \'`REG_IDX_W\'\n  reg [`REG_IDX_W - 1:0] r_dest_reg;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:49: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] r_alu_eval;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:50: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] r_mem_read;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:51: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] s_final_mem_read;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:53: Define or directive not defined: \'`ADDR_W\'\n  output [`ADDR_W - 1:0] o_pc;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:54: Define or directive not defined: \'`INSTR_W\'\n  output [`INSTR_W - 1:0] o_instr;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:56: Define or directive not defined: \'`DEST_SRC_W\'\n  output [`DEST_SRC_W - 1:0] o_dest_src;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:57: Define or directive not defined: \'`REG_IDX_W\'\n  output [`REG_IDX_W - 1:0] o_dest_reg;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:59: Define or directive not defined: \'`WORD_W\'\n  output reg [`WORD_W - 1:0] o_dest_data;\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:92: Define or directive not defined: \'`MEM_OP_RD_UBYTE\'\n    if(i_mem_op == `MEM_OP_RD_UBYTE || i_mem_op == `MEM_OP_RD_UHALF) begin\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:92: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n    if(i_mem_op == `MEM_OP_RD_UBYTE || i_mem_op == `MEM_OP_RD_UHALF) begin\n                                    ^~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:92: Define or directive not defined: \'`MEM_OP_RD_UHALF\'\n    if(i_mem_op == `MEM_OP_RD_UBYTE || i_mem_op == `MEM_OP_RD_UHALF) begin\n                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:100: Define or directive not defined: \'`DEST_SRC_NONE\'\n      `DEST_SRC_NONE: o_dest_data = 0;\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:101: Define or directive not defined: \'`DEST_SRC_ALU\'\n      `DEST_SRC_ALU: o_dest_data = r_alu_eval;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:102: Define or directive not defined: \'`DEST_SRC_MEM\'\n      `DEST_SRC_MEM: o_dest_data = s_final_mem_read;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:103: Define or directive not defined: \'`DEST_SRC_PC4\'\n      `DEST_SRC_PC4: o_dest_data = r_pc + `INSTR_W / 8;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/me.v:103: Define or directive not defined: \'`INSTR_W\'\n      `DEST_SRC_PC4: o_dest_data = r_pc + `INSTR_W / 8;\n                                          ^~~~~~~~\n%Error: Cannot continue\n'
module me(
  clk,
  clr,
  stall,

  i_pc,
  i_instr,

  i_dest_src,
  i_dest_reg,

  i_alu_eval,
  i_mem_read,

  i_mem_op,

  o_pc,
  o_instr,

  o_dest_src,
  o_dest_reg,

  o_dest_data
);
  input clk;
  input clr;
  input stall;

  input [`ADDR_W - 1:0] i_pc;
  input [`INSTR_W - 1:0] i_instr;

  input [`DEST_SRC_W - 1:0] i_dest_src;
  input [`REG_IDX_W - 1:0] i_dest_reg;

  input [`WORD_W - 1:0] i_alu_eval;
  input [`WORD_W - 1:0] i_mem_read;

  input [`MEM_OP_W -1:0] i_mem_op;

  reg [`ADDR_W - 1:0] r_pc;
  reg [`INSTR_W - 1:0] r_instr;

  reg [`DEST_SRC_W - 1:0] r_dest_src;
  reg [`REG_IDX_W - 1:0] r_dest_reg;

  reg [`WORD_W - 1:0] r_alu_eval;
  reg [`WORD_W - 1:0] r_mem_read;
  reg [`WORD_W - 1:0] s_final_mem_read;

  output [`ADDR_W - 1:0] o_pc;
  output [`INSTR_W - 1:0] o_instr;

  output [`DEST_SRC_W - 1:0] o_dest_src;
  output [`REG_IDX_W - 1:0] o_dest_reg;

  output reg [`WORD_W - 1:0] o_dest_data;

  assign o_pc = r_pc;
  assign o_instr = r_instr;

  assign o_dest_src = r_dest_src;
  assign o_dest_reg = r_dest_reg;

  always@(posedge clk) begin
    if(clr == 1) begin
      r_pc <= 0;
      r_instr <= 0;

      r_dest_src <= 0;
      r_dest_reg <= 0;

      r_alu_eval <= 0;
      r_mem_read <= 0;
    end else if(stall == 0) begin
      r_pc <= i_pc;
      r_instr <= i_instr;

      r_dest_src <= i_dest_src;
      r_dest_reg <= i_dest_reg;

      r_alu_eval <= i_alu_eval;
      r_mem_read <= i_mem_read;
    end
  end

  always@(*) begin

    if(i_mem_op == `MEM_OP_RD_UBYTE || i_mem_op == `MEM_OP_RD_UHALF) begin
      s_final_mem_read = i_mem_read;
    end else begin
      s_final_mem_read = $signed(i_mem_read);
    end


    case(r_dest_src)
      `DEST_SRC_NONE: o_dest_data = 0;
      `DEST_SRC_ALU: o_dest_data = r_alu_eval;
      `DEST_SRC_MEM: o_dest_data = s_final_mem_read;
      `DEST_SRC_PC4: o_dest_data = r_pc + `INSTR_W / 8;
      default: o_dest_data = 0;
    endcase
  end

endmodule
module me(
  clk,
  clr,
  stall,

  i_pc,
  i_instr,

  i_dest_src,
  i_dest_reg,

  i_alu_eval,
  i_mem_read,

  i_mem_op,

  o_pc,
  o_instr,

  o_dest_src,
  o_dest_reg,

  o_dest_data
);

  input clk;
  input clr;
  input stall;

  input [`ADDR_W - 1:0] i_pc;
  input [`INSTR_W - 1:0] i_instr;

  input [`DEST_SRC_W - 1:0] i_dest_src;
  input [`REG_IDX_W - 1:0] i_dest_reg;

  input [`WORD_W - 1:0] i_alu_eval;
  input [`WORD_W - 1:0] i_mem_read;

  input [`MEM_OP_W -1:0] i_mem_op;

  reg [`ADDR_W - 1:0] r_pc;
  reg [`INSTR_W - 1:0] r_instr;

  reg [`DEST_SRC_W - 1:0] r_dest_src;
  reg [`REG_IDX_W - 1:0] r_dest_reg;

  reg [`WORD_W - 1:0] r_alu_eval;
  reg [`WORD_W - 1:0] r_mem_read;
  reg [`WORD_W - 1:0] s_final_mem_read;

  output [`ADDR_W - 1:0] o_pc;
  output [`INSTR_W - 1:0] o_instr;

  output [`DEST_SRC_W - 1:0] o_dest_src;
  output [`REG_IDX_W - 1:0] o_dest_reg;

  output reg [`WORD_W - 1:0] o_dest_data;

  assign o_pc = r_pc;
  assign o_instr = r_instr;

  assign o_dest_src = r_dest_src;
  assign o_dest_reg = r_dest_reg;

  always@(posedge clk) begin
    if(clr == 1) begin
      r_pc <= 0;
      r_instr <= 0;

      r_dest_src <= 0;
      r_dest_reg <= 0;

      r_alu_eval <= 0;
      r_mem_read <= 0;
    end else if(stall == 0) begin
      r_pc <= i_pc;
      r_instr <= i_instr;

      r_dest_src <= i_dest_src;
      r_dest_reg <= i_dest_reg;

      r_alu_eval <= i_alu_eval;
      r_mem_read <= i_mem_read;
    end
  end

  always@(*) begin

    if(i_mem_op == `MEM_OP_RD_UBYTE || i_mem_op == `MEM_OP_RD_UHALF) begin
      s_final_mem_read = i_mem_read;
    end else begin
      s_final_mem_read = $signed(i_mem_read);
    end


    case(r_dest_src)
      `DEST_SRC_NONE: o_dest_data = 0;
      `DEST_SRC_ALU: o_dest_data = r_alu_eval;
      `DEST_SRC_MEM: o_dest_data = s_final_mem_read;
      `DEST_SRC_PC4: o_dest_data = r_pc + `INSTR_W / 8;
      default: o_dest_data = 0;
    endcase
  end

endmodule