data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1000000\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #1000000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #1000000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #1000000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #1500000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #1 clock = ~clock;  \n    ^\n%Error: data/full_repos/permissive/105948944/simulations/CounterUp_TestBench.v:36: Cannot find file containing module: \'counter_up\'\n    counter_up U2(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/counter_up\n             data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/counter_up.v\n             data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/counter_up.sv\n             counter_up\n             counter_up.v\n             counter_up.sv\n             obj_dir/counter_up\n             obj_dir/counter_up.v\n             obj_dir/counter_up.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CounterUp_TestBench(
    );
    
    
    reg clock = 0;
    reg reset = 0;
    reg [27:0] counterPeriod = 0;
    wire [27:0] countedUpTo;
    
    parameter [27:0] PERIOD = 28'd1000000;
    parameter [27:0] HALF_PERIOD = PERIOD >> 1;
    parameter [27:0] QUARTER_PERIOD = PERIOD >> 2;
    parameter [27:0] PERC75_PERIOD = HALF_PERIOD + QUARTER_PERIOD;
    
    counter_up U2(
    .clock(clock),
    .reset(reset),
    .counterPeriod(counterPeriod),
    .countedUpTo(countedUpTo)
    );
     
    initial 
    begin
        clock <=0;
        counterPeriod <= 28'd0;
        reset <= 0;
        #1000000
        
        counterPeriod <= PERIOD;
        #1000000
        
        reset = 1;
        reset = 0;
        counterPeriod = HALF_PERIOD;
        #1000000
        
        reset <= 1;
        reset <= 0;
        counterPeriod <= QUARTER_PERIOD;
        #1000000
        
        reset <= 1;
        reset <= 0;
        counterPeriod <= PERC75_PERIOD;
        #1500000
        
        reset = 1;
        reset = 0;
        counterPeriod = 0;
    end
       
    always 
    #1 clock = ~clock;
         
endmodule
module CounterUp_TestBench(
    );

    
    
    reg clock = 0;
    reg reset = 0;
    reg [27:0] counterPeriod = 0;
    wire [27:0] countedUpTo;
    
    parameter [27:0] PERIOD = 28'd1000000;
    parameter [27:0] HALF_PERIOD = PERIOD >> 1;
    parameter [27:0] QUARTER_PERIOD = PERIOD >> 2;
    parameter [27:0] PERC75_PERIOD = HALF_PERIOD + QUARTER_PERIOD;
    
    counter_up U2(
    .clock(clock),
    .reset(reset),
    .counterPeriod(counterPeriod),
    .countedUpTo(countedUpTo)
    );
     
    initial 
    begin
        clock <=0;
        counterPeriod <= 28'd0;
        reset <= 0;
        #1000000
        
        counterPeriod <= PERIOD;
        #1000000
        
        reset = 1;
        reset = 0;
        counterPeriod = HALF_PERIOD;
        #1000000
        
        reset <= 1;
        reset <= 0;
        counterPeriod <= QUARTER_PERIOD;
        #1000000
        
        reset <= 1;
        reset <= 0;
        counterPeriod <= PERC75_PERIOD;
        #1500000
        
        reset = 1;
        reset = 0;
        counterPeriod = 0;
    end
       
    always 
    #1 clock = ~clock;
         
endmodule