data/full_repos/permissive/141578247/TESTBENCH_simple/INS_atan_tb.v
 line:49: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_atan_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\nalways #(t/2) clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_atan_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #(t*8)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_atan_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #(t*2)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_atan_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #(t)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_atan_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #(t*5)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_atan_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #(t*5)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_atan_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #(t*2)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_atan_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #(t*8)\n ^\n%Error: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_atan_tb.v:73: Cannot find file containing module: \'INS_atan\'\nINS_atan u1(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141578247/TESTBENCH_simple,data/full_repos/permissive/141578247/INS_atan\n             data/full_repos/permissive/141578247/TESTBENCH_simple,data/full_repos/permissive/141578247/INS_atan.v\n             data/full_repos/permissive/141578247/TESTBENCH_simple,data/full_repos/permissive/141578247/INS_atan.sv\n             INS_atan\n             INS_atan.v\n             INS_atan.sv\n             obj_dir/INS_atan\n             obj_dir/INS_atan.v\n             obj_dir/INS_atan.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module INS_atan16_tb;

reg clk, rst, en;
reg [31:0] a, b;

parameter t = 20;

initial begin
	clk = 1'b1;
	rst = 1'b1;
	a = 32'h0;
	b = 32'h0;
	en = 1'b0;
end

always #(t/2) clk = ~clk;

initial begin
	#(t*8)
		rst = 1'b0;
	#(t*2)
		rst = 1'b1;
	#(t*5)


	#(t)
		en = 1'b1;



end

initial begin
	#(t*8)
	#(t*2)
	#(t*5)
		a = 32'h3F13CD3A;
		b = 32'h3F800000;
end

wire rdy;
wire [31:0] result;

INS_atan u1(
	.clk(clk)				,
	.rst(rst)				,
	.en(en)					,
	.a(a)						,
	.b(b)						,
	.result(result)		,
	.atan_finish(rdy)
);



endmodule
module INS_atan16_tb;


reg clk, rst, en;
reg [31:0] a, b;

parameter t = 20;

initial begin
	clk = 1'b1;
	rst = 1'b1;
	a = 32'h0;
	b = 32'h0;
	en = 1'b0;
end

always #(t/2) clk = ~clk;

initial begin
	#(t*8)
		rst = 1'b0;
	#(t*2)
		rst = 1'b1;
	#(t*5)


	#(t)
		en = 1'b1;



end

initial begin
	#(t*8)
	#(t*2)
	#(t*5)
		a = 32'h3F13CD3A;
		b = 32'h3F800000;
end

wire rdy;
wire [31:0] result;

INS_atan u1(
	.clk(clk)				,
	.rst(rst)				,
	.en(en)					,
	.a(a)						,
	.b(b)						,
	.result(result)		,
	.atan_finish(rdy)
);



endmodule