data/full_repos/permissive/157049472/Verilog Test Benches/BranchLogic_tb.v
1: b'%Error: Cannot find file containing module: Test\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Test\n             data/full_repos/permissive/157049472/Verilog/Test.v\n             data/full_repos/permissive/157049472/Verilog/Test.sv\n             Test\n             Test.v\n             Test.sv\n             obj_dir/Test\n             obj_dir/Test.v\n             obj_dir/Test.sv\n%Error: Cannot find file containing module: Benches,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Benches/BranchLogic_tb.v\n%Error: Exiting due to 4 error(s)\n'
module BranchLogic_tb;


	reg [5:0] opcode;
	reg [25:0] offset_in;
	reg [31:0] rs_value;
	reg zflag_ff;
	reg oflag_ff;
	reg cflag_ff;
	reg sflag_ff;
	reg clk;
	reg rst;


	wire [25:0] offset_out;
	wire branch;


	BranchL uut (
		.opcode(opcode), 
		.offset_in(offset_in), 
		.rs_value(rs_value), 
		.zflag_ff(zflag_ff), 
		.oflag_ff(oflag_ff), 
		.cflag_ff(cflag_ff), 
		.sflag_ff(sflag_ff), 
		.clk(clk), 
		.offset_out(offset_out), 
		.rst(rst), 
		.branch(branch)
	);

	initial begin

		opcode = 0;
		offset_in = 0;
		rs_value = 0;
		zflag_ff = 0;
		oflag_ff = 0;
		cflag_ff = 0;
		sflag_ff = 0;
		clk = 0;
		rst = 0;


		#100;
        

		rst = 1;
		#10 rst = 0;

		#10;

		opcode = 6'd5;
		offset_in = 4;
		rs_value = -32;
		zflag_ff = 1;
		oflag_ff = 0;
		cflag_ff = 0;
		sflag_ff = 0;

		#10;

		opcode = 6'd0;
		offset_in = 0;
		rs_value = -32;
		zflag_ff = 1;
		oflag_ff = 0;
		cflag_ff = 0;
		sflag_ff = 0;

		#10;

		opcode = 6'd9;
		offset_in = 0;
		rs_value = -32;
		zflag_ff = 0;
		oflag_ff = 0;
		cflag_ff = 0;
		sflag_ff = 1;

		#10;

		opcode = 6'd5;
		offset_in = 0;
		rs_value = -32;
		zflag_ff = 0;
		oflag_ff = 0;
		cflag_ff = 0;
		sflag_ff = 1;

		#10;

		opcode = 6'd7;
		offset_in = 0;
		rs_value = -32;
		zflag_ff = 0;
		oflag_ff = 0;
		cflag_ff = 1;
		sflag_ff = 0;

		
		#10;

		opcode = 6'd1;
		offset_in = 8;
		rs_value = -32;
		zflag_ff = 0;
		oflag_ff = 0;
		cflag_ff = 1;
		sflag_ff = 0;

		#10;

		opcode = 6'd11;
		offset_in = 0;
		rs_value = -32;
		zflag_ff = 0;
		oflag_ff = 1;
		cflag_ff = 0;
		sflag_ff = 0;

		#10;

		opcode = 6'd0;
		offset_in = 0;
		rs_value = -32;
		zflag_ff = 0;
		oflag_ff = 1;
		cflag_ff = 0;
		sflag_ff = 0;

		#10;

		opcode = 6'd3;
		offset_in = 0;
		rs_value = 12;
		zflag_ff = 0;
		oflag_ff = 1;
		cflag_ff = 0;
		sflag_ff = 0;

		#10;
		opcode = 6'd13;
		offset_in = 20;
		rs_value = 16;
		zflag_ff = 0;
		oflag_ff = 1;
		cflag_ff = 0;
		sflag_ff = 0;

	end
    
    always begin
    	#5 clk = ~clk;
    end 

endmodule
module BranchLogic_tb;



	reg [5:0] opcode;
	reg [25:0] offset_in;
	reg [31:0] rs_value;
	reg zflag_ff;
	reg oflag_ff;
	reg cflag_ff;
	reg sflag_ff;
	reg clk;
	reg rst;


	wire [25:0] offset_out;
	wire branch;


	BranchL uut (
		.opcode(opcode), 
		.offset_in(offset_in), 
		.rs_value(rs_value), 
		.zflag_ff(zflag_ff), 
		.oflag_ff(oflag_ff), 
		.cflag_ff(cflag_ff), 
		.sflag_ff(sflag_ff), 
		.clk(clk), 
		.offset_out(offset_out), 
		.rst(rst), 
		.branch(branch)
	);

	initial begin

		opcode = 0;
		offset_in = 0;
		rs_value = 0;
		zflag_ff = 0;
		oflag_ff = 0;
		cflag_ff = 0;
		sflag_ff = 0;
		clk = 0;
		rst = 0;


		#100;
        

		rst = 1;
		#10 rst = 0;

		#10;

		opcode = 6'd5;
		offset_in = 4;
		rs_value = -32;
		zflag_ff = 1;
		oflag_ff = 0;
		cflag_ff = 0;
		sflag_ff = 0;

		#10;

		opcode = 6'd0;
		offset_in = 0;
		rs_value = -32;
		zflag_ff = 1;
		oflag_ff = 0;
		cflag_ff = 0;
		sflag_ff = 0;

		#10;

		opcode = 6'd9;
		offset_in = 0;
		rs_value = -32;
		zflag_ff = 0;
		oflag_ff = 0;
		cflag_ff = 0;
		sflag_ff = 1;

		#10;

		opcode = 6'd5;
		offset_in = 0;
		rs_value = -32;
		zflag_ff = 0;
		oflag_ff = 0;
		cflag_ff = 0;
		sflag_ff = 1;

		#10;

		opcode = 6'd7;
		offset_in = 0;
		rs_value = -32;
		zflag_ff = 0;
		oflag_ff = 0;
		cflag_ff = 1;
		sflag_ff = 0;

		
		#10;

		opcode = 6'd1;
		offset_in = 8;
		rs_value = -32;
		zflag_ff = 0;
		oflag_ff = 0;
		cflag_ff = 1;
		sflag_ff = 0;

		#10;

		opcode = 6'd11;
		offset_in = 0;
		rs_value = -32;
		zflag_ff = 0;
		oflag_ff = 1;
		cflag_ff = 0;
		sflag_ff = 0;

		#10;

		opcode = 6'd0;
		offset_in = 0;
		rs_value = -32;
		zflag_ff = 0;
		oflag_ff = 1;
		cflag_ff = 0;
		sflag_ff = 0;

		#10;

		opcode = 6'd3;
		offset_in = 0;
		rs_value = 12;
		zflag_ff = 0;
		oflag_ff = 1;
		cflag_ff = 0;
		sflag_ff = 0;

		#10;
		opcode = 6'd13;
		offset_in = 20;
		rs_value = 16;
		zflag_ff = 0;
		oflag_ff = 1;
		cflag_ff = 0;
		sflag_ff = 0;

	end
    
    always begin
    	#5 clk = ~clk;
    end 

endmodule