data/full_repos/permissive/181665138/verilog/capitolo_vi/Interfaccia_Parallela_di_Ingresso.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/181665138/verilog/capitolo_vi/Interfaccia_Parallela_di_Ingresso.v:33: Unsupported: Ignoring delay on this delayed statement.\n    always @(posedge e) #3 RBR<=byte_in;\n                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181665138/verilog/capitolo_vi/Interfaccia_Parallela_di_Ingresso.v:31: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'RBR\' generates 8 bits.\n                                                                                                               : ... In instance Interfaccia_Parallela_di_Ingresso\n    assign d7_d0 = (e == 1)?RBR:\'HZZ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/181665138/verilog/capitolo_vi/Interfaccia_Parallela_di_Ingresso.v:31: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                               : ... In instance Interfaccia_Parallela_di_Ingresso\n    assign d7_d0 = (e == 1)?RBR:\'HZZ;\n                 ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Interfaccia_Parallela_di_Ingresso(d7_d0, s_, ior_, byte_in);
    input           s_, ior_;
    output  [7:0]   d7_d0;
    input   [7:0]   byte_in;
    reg     [7:0]   RBR;
    
    wire   e;
    assign e = ({s_, ior_}=='B00)?1:0;

    assign d7_d0 = (e == 1)?RBR:'HZZ;

    always @(posedge e) #3 RBR<=byte_in;
endmodule
module Interfaccia_Parallela_di_Ingresso(d7_d0, s_, ior_, byte_in);

    input           s_, ior_;
    output  [7:0]   d7_d0;
    input   [7:0]   byte_in;
    reg     [7:0]   RBR;
    
    wire   e;
    assign e = ({s_, ior_}=='B00)?1:0;

    assign d7_d0 = (e == 1)?RBR:'HZZ;

    always @(posedge e) #3 RBR<=byte_in;
endmodule