data/full_repos/permissive/167274925/RegisterFile_tb.v
 line:15: before: "reg"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167274925/RegisterFile_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 Clk <= ~Clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167274925/RegisterFile_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #15;\n    ^\n%Error: data/full_repos/permissive/167274925/RegisterFile_tb.v:46: syntax error, unexpected \'@\'\n    @(posedge Clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/RegisterFile_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegisterFile_tb();

	reg [4:0] ReadRegister1;
	reg [4:0] ReadRegister2;
	reg	[4:0] WriteRegister;
	reg [31:0] WriteData;
	reg RegWrite;
	reg Clk;

	wire [31:0] ReadData1;
	wire [31:0] ReadData2;


	RegisterFile u0(
		.ReadRegister1(ReadRegister1), 
		.ReadRegister2(ReadRegister2), 
		.WriteRegister(WriteRegister), 
		.WriteData(WriteData), 
		.RegWrite(RegWrite), 
		.Clk(Clk), 
		.ReadData1(ReadData1), 
		.ReadData2(ReadData2)
	);

	initial begin
		Clk <= 1'b0;
		forever #10 Clk <= ~Clk;
	end

	initial begin
    RegWrite<=0;
    #15;
    @(posedge Clk);
     RegWrite<=1;
     WriteData<=32'd1;
     WriteRegister<=5'd1;
     ReadRegister1<=5'd1;
	 ReadRegister2<=5'd2;
	 #50;
	end

endmodule
module RegisterFile_tb();


	reg [4:0] ReadRegister1;
	reg [4:0] ReadRegister2;
	reg	[4:0] WriteRegister;
	reg [31:0] WriteData;
	reg RegWrite;
	reg Clk;

	wire [31:0] ReadData1;
	wire [31:0] ReadData2;


	RegisterFile u0(
		.ReadRegister1(ReadRegister1), 
		.ReadRegister2(ReadRegister2), 
		.WriteRegister(WriteRegister), 
		.WriteData(WriteData), 
		.RegWrite(RegWrite), 
		.Clk(Clk), 
		.ReadData1(ReadData1), 
		.ReadData2(ReadData2)
	);

	initial begin
		Clk <= 1'b0;
		forever #10 Clk <= ~Clk;
	end

	initial begin
    RegWrite<=0;
    #15;
    @(posedge Clk);
     RegWrite<=1;
     WriteData<=32'd1;
     WriteRegister<=5'd1;
     ReadRegister1<=5'd1;
	 ReadRegister2<=5'd2;
	 #50;
	end

endmodule