data/full_repos/permissive/128100618/SV/FPU.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/128100618/SV/FPU.v:388: Cell has missing pin: \'oSum\'\n FPadd init_newton(reduced_input_x_2, T1, x0) ;\n       ^~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/128100618/SV/FPU.v:392: Cell has missing pin: \'oSum\'\n FPadd newton12(T2, input_x_x0, two_minus_input_x_x0);\n       ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/128100618/SV/FPU.v:397: Cell has missing pin: \'oSum\'\n FPadd newton22(T2, input_x_x1, two_minus_input_x_x1);\n       ^~~~~~~~\n%Warning-MULTITOP: data/full_repos/permissive/128100618/SV/FPU.v:311: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                    : ... Top module \'FPinv\'\nmodule FPinv (\n       ^~~~~\n                                                                    : ... Top module \'fp2int\'\nmodule fp2int(\n       ^~~~~~\n                                                                    : ... Top module \'FPinv_prof\'\nmodule FPinv_prof (f1, fout);\n       ^~~~~~~~~~\n                                                                    : ... Top module \'fpadd\'\nmodule fpadd (fout, f1, f2);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:209: Operator GT expects 9 bits on the LHS, but LHS\'s VARREF \'exp_diff_A\' generates 8 bits.\n                                                                 : ... In instance FPinv_prof.newton22\n                         (exp_diff_A > 9\'d35) ? 47\'b0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:212: Operator GT expects 9 bits on the LHS, but LHS\'s VARREF \'exp_diff_B\' generates 8 bits.\n                                                                 : ... In instance FPinv_prof.newton22\n                         (exp_diff_B > 9\'d35) ? 47\'b0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:122: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 9 bits.\n                                                                 : ... In instance FPinv_prof.newton23\n    assign oProd_e = pre_prod_frac[45] ? (pre_prod_exp-9\'d126) : (pre_prod_exp - 9\'d127);\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:388: Input port connection \'iCLK\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'reduced_input_x_2\' generates 32 bits.\n                                                                 : ... In instance FPinv_prof\n FPadd init_newton(reduced_input_x_2, T1, x0) ;\n                   ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:392: Input port connection \'iCLK\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'T2\' generates 32 bits.\n                                                                 : ... In instance FPinv_prof\n FPadd newton12(T2, input_x_x0, two_minus_input_x_x0);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:397: Input port connection \'iCLK\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'T2\' generates 32 bits.\n                                                                 : ... In instance FPinv_prof\n FPadd newton22(T2, input_x_x1, two_minus_input_x_x1);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FPU.v:330: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'m_in\' generates 24 bits.\n                                                                 : ... In instance fp2int\n assign abs_int = (e_in>8\'h80)? (m_in >> (8\'d150 - e_in)) : 32\'d0;\n                                      ^~\n%Error: Exiting due to 11 warning(s)\n'
module fpadd (fout, f1, f2);

	input [31:0] f1, f2 ;
	output [31:0] fout ;
	
	wire  [31:0] fout ;
	wire sout ;
	reg [22:0] mout ;
	reg [7:0] eout ;
	reg [23:0] shift_small, denorm_mout ;
	
	wire s1, s2 ;
	reg  sb, ss ;
	wire [22:0] m1, m2 ;
	reg  [22:0] mb, ms ;
	wire [7:0] e1, e2 ;
	wire [7:0] ediff ;
	reg  [7:0] eb, es ;
	reg  [7:0] num_zeros ;
	

	assign s1 = f1[31];
	assign e1 = f1[30:23];
	assign m1 = {1'b1, f1[22:1]} ;

	assign s2 = f2[31];
	assign e2 = f2[30:23];
	assign m2 = {1'b1, f2[22:1]} ;
	

	always @(*)
	begin
		if (e1>e2)
		begin
			sb = s1 ;
			eb = e1 ;
			mb = m1 ;
			ss = s2 ;
			es = e2 ;
			ms = m2 ;
		end
		else if (e2>e1)
		begin
			sb = s2 ;
			eb = e2 ;
			mb = m2 ;
			ss = s1 ;
			es = e1 ;
			ms = m1 ;
		end
		else
		begin
			if (m1>m2)
			begin
				sb = s1 ;
				eb = e1 ;
				mb = m1 ;
				ss = s2 ;
				es = e2 ;
				ms = m2 ;
			end
			else
			begin
				sb = s2 ;
				eb = e2 ;
				mb = m2 ;
				ss = s1 ;
				es = e1 ;
				ms = m1 ;
			end
		end
	end
	

	assign sout = sb ;

	assign fout = {sout, eout, mout} ;	
	




	assign ediff = eb - es ;
	always @(*)
	begin
		if ((ms[22]==0) && (mb[22]==0))
		begin
			mout = 23'b0 ;
			eout = 8'b0 ; 
		end
		else if ((ms[22]==0) || ediff>8)
		begin
			mout = mb ;
			eout = eb ;
		end
		else
		begin


			shift_small = {1'b0, ms} >> ediff ;

			if (sb==ss)
			begin
				denorm_mout = {1'b0, mb} + shift_small ;


				if (denorm_mout[23]==1)
				begin
					mout = denorm_mout[23:1] ;
					eout = eb + 8'b1 ;
				end
				else
				begin
					mout = denorm_mout[22:0] ;
					eout = eb ;
				end
			end
			else
			begin
				denorm_mout = {1'b0, mb} - shift_small ;




				if (denorm_mout[22:0]==23'd0)
				begin
					mout = 23'b0 ;
					eout = 8'b0 ;
				end
				else
				begin

					casex (denorm_mout[22:0])
						23'b1xxxxxxxxxxxxxxxxxxxxxx: num_zeros = 8'd0 ;
						23'b01xxxxxxxxxxxxxxxxxxxxx: num_zeros = 8'd1 ;
						23'b001xxxxxxxxxxxxxxxxxxxx: num_zeros = 8'd2 ;
						23'b0001xxxxxxxxxxxxxxxxxxx: num_zeros = 8'd3 ;
						23'b00001xxxxxxxxxxxxxxxxxx: num_zeros = 8'd4 ;
						23'b000001xxxxxxxxxxxxxxxxx: num_zeros = 8'd5 ;
						23'b0000001xxxxxxxxxxxxxxxx: num_zeros = 8'd6 ;
						23'b00000001xxxxxxxxxxxxxxx: num_zeros = 8'd7 ;
						23'b000000001xxxxxxxxxxxxxx: num_zeros = 8'd8 ;
						23'b0000000001xxxxxxxxxxxxx: num_zeros = 8'd9 ;
						23'b00000000001xxxxxxxxxxxx: num_zeros = 8'd10 ;
						23'b000000000001xxxxxxxxxxx: num_zeros = 8'd11 ;
						23'b0000000000001xxxxxxxxxx: num_zeros = 8'd12 ;
						23'b00000000000001xxxxxxxxx: num_zeros = 8'd13 ;
						23'b000000000000001xxxxxxxx: num_zeros = 8'd14 ;
						23'b0000000000000001xxxxxxx: num_zeros = 8'd15 ;
						23'b00000000000000001xxxxxx: num_zeros = 8'd16 ;
						23'b000000000000000001xxxxx: num_zeros = 8'd17 ;
						23'b0000000000000000001xxxx: num_zeros = 8'd18 ;
						23'b00000000000000000001xxx: num_zeros = 8'd19 ;
						23'b000000000000000000001xx: num_zeros = 8'd20 ;
						23'b0000000000000000000001x: num_zeros = 8'd21 ;
						23'b00000000000000000000001: num_zeros = 8'd22 ;

						
						default:       num_zeros = 8'd23 ;
					endcase	


					eout = eb - num_zeros ;
					mout = denorm_mout[22:0] << num_zeros ;
				end
			end


		end
	end
endmodule
module fpadd (fout, f1, f2);


	input [31:0] f1, f2 ;
	output [31:0] fout ;
	
	wire  [31:0] fout ;
	wire sout ;
	reg [22:0] mout ;
	reg [7:0] eout ;
	reg [23:0] shift_small, denorm_mout ;
	
	wire s1, s2 ;
	reg  sb, ss ;
	wire [22:0] m1, m2 ;
	reg  [22:0] mb, ms ;
	wire [7:0] e1, e2 ;
	wire [7:0] ediff ;
	reg  [7:0] eb, es ;
	reg  [7:0] num_zeros ;
	

	assign s1 = f1[31];
	assign e1 = f1[30:23];
	assign m1 = {1'b1, f1[22:1]} ;

	assign s2 = f2[31];
	assign e2 = f2[30:23];
	assign m2 = {1'b1, f2[22:1]} ;
	

	always @(*)
	begin
		if (e1>e2)
		begin
			sb = s1 ;
			eb = e1 ;
			mb = m1 ;
			ss = s2 ;
			es = e2 ;
			ms = m2 ;
		end
		else if (e2>e1)
		begin
			sb = s2 ;
			eb = e2 ;
			mb = m2 ;
			ss = s1 ;
			es = e1 ;
			ms = m1 ;
		end
		else
		begin
			if (m1>m2)
			begin
				sb = s1 ;
				eb = e1 ;
				mb = m1 ;
				ss = s2 ;
				es = e2 ;
				ms = m2 ;
			end
			else
			begin
				sb = s2 ;
				eb = e2 ;
				mb = m2 ;
				ss = s1 ;
				es = e1 ;
				ms = m1 ;
			end
		end
	end
	

	assign sout = sb ;

	assign fout = {sout, eout, mout} ;	
	




	assign ediff = eb - es ;
	always @(*)
	begin
		if ((ms[22]==0) && (mb[22]==0))
		begin
			mout = 23'b0 ;
			eout = 8'b0 ; 
		end
		else if ((ms[22]==0) || ediff>8)
		begin
			mout = mb ;
			eout = eb ;
		end
		else
		begin


			shift_small = {1'b0, ms} >> ediff ;

			if (sb==ss)
			begin
				denorm_mout = {1'b0, mb} + shift_small ;


				if (denorm_mout[23]==1)
				begin
					mout = denorm_mout[23:1] ;
					eout = eb + 8'b1 ;
				end
				else
				begin
					mout = denorm_mout[22:0] ;
					eout = eb ;
				end
			end
			else
			begin
				denorm_mout = {1'b0, mb} - shift_small ;




				if (denorm_mout[22:0]==23'd0)
				begin
					mout = 23'b0 ;
					eout = 8'b0 ;
				end
				else
				begin

					casex (denorm_mout[22:0])
						23'b1xxxxxxxxxxxxxxxxxxxxxx: num_zeros = 8'd0 ;
						23'b01xxxxxxxxxxxxxxxxxxxxx: num_zeros = 8'd1 ;
						23'b001xxxxxxxxxxxxxxxxxxxx: num_zeros = 8'd2 ;
						23'b0001xxxxxxxxxxxxxxxxxxx: num_zeros = 8'd3 ;
						23'b00001xxxxxxxxxxxxxxxxxx: num_zeros = 8'd4 ;
						23'b000001xxxxxxxxxxxxxxxxx: num_zeros = 8'd5 ;
						23'b0000001xxxxxxxxxxxxxxxx: num_zeros = 8'd6 ;
						23'b00000001xxxxxxxxxxxxxxx: num_zeros = 8'd7 ;
						23'b000000001xxxxxxxxxxxxxx: num_zeros = 8'd8 ;
						23'b0000000001xxxxxxxxxxxxx: num_zeros = 8'd9 ;
						23'b00000000001xxxxxxxxxxxx: num_zeros = 8'd10 ;
						23'b000000000001xxxxxxxxxxx: num_zeros = 8'd11 ;
						23'b0000000000001xxxxxxxxxx: num_zeros = 8'd12 ;
						23'b00000000000001xxxxxxxxx: num_zeros = 8'd13 ;
						23'b000000000000001xxxxxxxx: num_zeros = 8'd14 ;
						23'b0000000000000001xxxxxxx: num_zeros = 8'd15 ;
						23'b00000000000000001xxxxxx: num_zeros = 8'd16 ;
						23'b000000000000000001xxxxx: num_zeros = 8'd17 ;
						23'b0000000000000000001xxxx: num_zeros = 8'd18 ;
						23'b00000000000000000001xxx: num_zeros = 8'd19 ;
						23'b000000000000000000001xx: num_zeros = 8'd20 ;
						23'b0000000000000000000001x: num_zeros = 8'd21 ;
						23'b00000000000000000000001: num_zeros = 8'd22 ;

						
						default:       num_zeros = 8'd23 ;
					endcase	


					eout = eb - num_zeros ;
					mout = denorm_mout[22:0] << num_zeros ;
				end
			end


		end
	end
endmodule