data/full_repos/permissive/220229160/integrateinv-plugin/tests/toplevel/toplevel.v
 line:19: before: "("
1: b"%Error: data/full_repos/permissive/220229160/integrateinv-plugin/tests/toplevel/toplevel.v:31: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    output wire [2:0]  do\n                       ^~\n%Error: data/full_repos/permissive/220229160/integrateinv-plugin/tests/toplevel/toplevel.v:39: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n    box b0 (.A(d[0]), .Y(do[0]));\n                         ^~\n%Error: data/full_repos/permissive/220229160/integrateinv-plugin/tests/toplevel/toplevel.v:40: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n    box b1 (.A(d[1]), .Y(do[1]));\n                         ^~\n%Error: Exiting due to 3 error(s)\n"
module top(
    input  wire [1:0]  di,
    output wire [2:0]  do
);

    wire [1:0] d;

    \$_NOT_ n0 (.A(di[0]), .Y(d[0]));
    \$_NOT_ n1 (.A(di[1]), .Y(d[1]));

    box b0 (.A(d[0]), .Y(do[0]));
    box b1 (.A(d[1]), .Y(do[1]));
    assign do[0] = d[0];

endmodule
module top(
    input  wire [1:0]  di,
    output wire [2:0]  do
);


    wire [1:0] d;

    \$_NOT_ n0 (.A(di[0]), .Y(d[0]));
    \$_NOT_ n1 (.A(di[1]), .Y(d[1]));

    box b0 (.A(d[0]), .Y(do[0]));
    box b1 (.A(d[1]), .Y(do[1]));
    assign do[0] = d[0];

endmodule