data/full_repos/permissive/143278/ivltests/nb_ec_real.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:10: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:11: Unsupported: Ignoring delay on this delayed statement.\n  always #20 in = in + 1.0;\n         ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:15: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n    result <= repeat(count) @(posedge clk) in;\n              ^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:16: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 0 || result != -1.0) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:18: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:21: syntax error, unexpected \'@\'\n    @(result);\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:22: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 50 || result != 0.0) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:24: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #15;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:30: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n    result <= repeat(count) @(posedge clk) in;\n              ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #0;  \n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:32: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 65 || result != 3.0) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:34: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:40: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n    result <= repeat(count) @(posedge clk) in;\n              ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #0;  \n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:42: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 85 || result != 4.0) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:44: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:49: syntax error, unexpected \'@\', expecting TYPE-IDENTIFIER\n    result <= @(posedge clk) 0.0;\n              ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:50: syntax error, unexpected \'@\', expecting TYPE-IDENTIFIER\n    result <= @(posedge clk) in;  \n              ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:52: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 110 || result != 5.0) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:54: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:59: syntax error, unexpected \'@\', expecting TYPE-IDENTIFIER\n    result <= @(posedge clk) 1.0;\n              ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:60: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n    result <= repeat(icount) @(posedge clk) 2.0;\n              ^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:61: syntax error, unexpected repeat, expecting TYPE-IDENTIFIER\n    result <= repeat(3) @(posedge clk) 3.0;\n              ^~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:63: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 130 || result != 1.0) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:65: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:68: syntax error, unexpected \'@\'\n    @(result);\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:69: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 150 || result != 2.0) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:71: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:74: syntax error, unexpected \'@\'\n    @(result);\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:75: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 170 || result != 3.0) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/nb_ec_real.v:77: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Error: Exiting due to 27 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass = 1'b1;

  integer count;
  reg [2:0] icount;
  reg clk = 0;
  real in = 0.0;
  real result = -1.0;

  always #10 clk = ~clk;
  always #20 in = in + 1.0;

  initial begin
    count = 3;
    result <= repeat(count) @(posedge clk) in;
    if ($simtime != 0 || result != -1.0) begin
      $display("Failed repeat(3) blocked at %0t, expected -1.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end
    @(result);
    if ($simtime != 50 || result != 0.0) begin
      $display("Failed repeat(3) at %0t, expected 0.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end

    #15;
    count = 0;
    result <= repeat(count) @(posedge clk) in;
    #0;
    if ($simtime != 65 || result != 3.0) begin
      $display("Failed repeat(0) at %0t, expected 3.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end

    #20;
    count = -1;
    result <= repeat(count) @(posedge clk) in;
    #0;
    if ($simtime != 85 || result != 4.0) begin
      $display("Failed repeat(-1) at %0t, expected 4.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end

    #20;
    result <= @(posedge clk) 0.0;
    result <= @(posedge clk) in;
    @(result);
    if ($simtime != 110 || result != 5.0) begin
      $display("Failed @ at %0t, expected 5.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end

    icount = 3'd2;
    result <= @(posedge clk) 1.0;
    result <= repeat(icount) @(posedge clk) 2.0;
    result <= repeat(3) @(posedge clk) 3.0;
    @(result);
    if ($simtime != 130 || result != 1.0) begin
      $display("Failed first @ at %0t, expected 1.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end
    @(result);
    if ($simtime != 150 || result != 2.0) begin
      $display("Failed second @ at %0t, expected 2.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end
    @(result);
    if ($simtime != 170 || result != 3.0) begin
      $display("Failed third @ at %0t, expected 3.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
    $finish;
  end
endmodule
module top;

  reg pass = 1'b1;

  integer count;
  reg [2:0] icount;
  reg clk = 0;
  real in = 0.0;
  real result = -1.0;

  always #10 clk = ~clk;
  always #20 in = in + 1.0;

  initial begin
    count = 3;
    result <= repeat(count) @(posedge clk) in;
    if ($simtime != 0 || result != -1.0) begin
      $display("Failed repeat(3) blocked at %0t, expected -1.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end
    @(result);
    if ($simtime != 50 || result != 0.0) begin
      $display("Failed repeat(3) at %0t, expected 0.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end

    #15;
    count = 0;
    result <= repeat(count) @(posedge clk) in;
    #0;
    if ($simtime != 65 || result != 3.0) begin
      $display("Failed repeat(0) at %0t, expected 3.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end

    #20;
    count = -1;
    result <= repeat(count) @(posedge clk) in;
    #0;
    if ($simtime != 85 || result != 4.0) begin
      $display("Failed repeat(-1) at %0t, expected 4.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end

    #20;
    result <= @(posedge clk) 0.0;
    result <= @(posedge clk) in;
    @(result);
    if ($simtime != 110 || result != 5.0) begin
      $display("Failed @ at %0t, expected 5.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end

    icount = 3'd2;
    result <= @(posedge clk) 1.0;
    result <= repeat(icount) @(posedge clk) 2.0;
    result <= repeat(3) @(posedge clk) 3.0;
    @(result);
    if ($simtime != 130 || result != 1.0) begin
      $display("Failed first @ at %0t, expected 1.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end
    @(result);
    if ($simtime != 150 || result != 2.0) begin
      $display("Failed second @ at %0t, expected 2.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end
    @(result);
    if ($simtime != 170 || result != 3.0) begin
      $display("Failed third @ at %0t, expected 3.0, got %f",
               $simtime, result);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
    $finish;
  end
endmodule