data/full_repos/permissive/169294490/FPGA/src/VGA/vga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169294490/FPGA/src/VGA/vga.v:41: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                          : ... In instance vga_controller.hs\n reg [10:0] count = 10\'b0000000000;\n                    ^~~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169294490/FPGA/src/VGA/vga.v:6: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance vga_controller.vs\n reg [10:0] count = 10\'b0000000000;\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169294490/FPGA/src/VGA/vga.v:102: Cannot find file containing module: \'framebuffer\'\n framebuffer   fb(clk50, rst, blank, red_out, green_out, blue_out, line_clk, vblank, fb_data, fb_addr, fb_we, framebuffer_addr_rd, framebuffer_data_rd, framebuffer_rd_en);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169294490/FPGA/src/VGA,data/full_repos/permissive/169294490/framebuffer\n             data/full_repos/permissive/169294490/FPGA/src/VGA,data/full_repos/permissive/169294490/framebuffer.v\n             data/full_repos/permissive/169294490/FPGA/src/VGA,data/full_repos/permissive/169294490/framebuffer.sv\n             framebuffer\n             framebuffer.v\n             framebuffer.sv\n             obj_dir/framebuffer\n             obj_dir/framebuffer.v\n             obj_dir/framebuffer.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module vga_controller(clk50, rst, hsync_out, vsync_out, red_out, blue_out, green_out, fb_data, fb_addr, fb_we, framebuffer_addr_rd, framebuffer_data_rd, framebuffer_rd_en);
	input clk50;
	input rst;
	input [7:0] fb_data;
	input [11:0] fb_addr;
	input wire fb_we;
	output hsync_out, vsync_out;
	output [3:0] red_out, blue_out, green_out;
	wire line_clk, blank, hblank, vblank;
	input wire [11:0] framebuffer_addr_rd;
	output wire [7:0] framebuffer_data_rd;
	input wire framebuffer_rd_en;

	hsync   hs(clk50, hsync_out, hblank, line_clk);
	vsync   vs(line_clk, vsync_out, vblank);
	framebuffer   fb(clk50, rst, blank, red_out, green_out, blue_out, line_clk, vblank, fb_data, fb_addr, fb_we, framebuffer_addr_rd, framebuffer_data_rd, framebuffer_rd_en);

	assign blank 	 = hblank || vblank;

endmodule
module vga_controller(clk50, rst, hsync_out, vsync_out, red_out, blue_out, green_out, fb_data, fb_addr, fb_we, framebuffer_addr_rd, framebuffer_data_rd, framebuffer_rd_en);

	input clk50;
	input rst;
	input [7:0] fb_data;
	input [11:0] fb_addr;
	input wire fb_we;
	output hsync_out, vsync_out;
	output [3:0] red_out, blue_out, green_out;
	wire line_clk, blank, hblank, vblank;
	input wire [11:0] framebuffer_addr_rd;
	output wire [7:0] framebuffer_data_rd;
	input wire framebuffer_rd_en;

	hsync   hs(clk50, hsync_out, hblank, line_clk);
	vsync   vs(line_clk, vsync_out, vblank);
	framebuffer   fb(clk50, rst, blank, red_out, green_out, blue_out, line_clk, vblank, fb_data, fb_addr, fb_we, framebuffer_addr_rd, framebuffer_data_rd, framebuffer_rd_en);

	assign blank 	 = hblank || vblank;

endmodule