data/full_repos/permissive/127511545/src/MUX.v
None: at end of input
1: b'%Warning-MULTITOP: data/full_repos/permissive/127511545/src/MUX.v:68: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'MUX2x5to5\'\nmodule MUX2x5to5(AdderOutput, Adder0, Adder1, Selector);\n       ^~~~~~~~~\n                                                                    : ... Top module \'MUX3x32to32\'\nmodule MUX3x32to32(DataOutput, A, B, C, Selector);\n       ^~~~~~~~~~~\n                                                                    : ... Top module \'MUX32x32to32\'\nmodule MUX32x32to32(ReadData, Input0, Input1, Input2, Input3, Input4, Input5, Input6, Input7, Input8, Input9, Input10, Input11, Input12, Input13, Input14, Input15, Input16, Input17, Input18, Input19, Input20, Input21, Input22, Input23, Input24, Input25, Input26, Input27, Input28, Input29, Input30, Input31, ReadRegister);\n       ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:197: Signal definition not found, creating implicitly: \'NotSelector\'\n                                                                     : ... Suggested alternative: \'Selector\'\n not #(50) inv0(NotSelector, Selector);\n                ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:198: Signal definition not found, creating implicitly: \'O1\'\n                                                                     : ... Suggested alternative: \'O\'\n and #(50) a0(O1, A, NotSelector);\n              ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:199: Signal definition not found, creating implicitly: \'O2\'\n                                                                     : ... Suggested alternative: \'O\'\n and #(50) a1(O2, B, Selector);\n              ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:124: Signal definition not found, creating implicitly: \'G3\'\n or #(50) o0(G3, F[0], F[1], F[2], F[3]);\n             ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:125: Signal definition not found, creating implicitly: \'G4\'\n                                                                     : ... Suggested alternative: \'G3\'\n or #(50) o1(G4, F[4], F[5], F[6], F[7]);\n             ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:126: Signal definition not found, creating implicitly: \'G5\'\n                                                                     : ... Suggested alternative: \'G3\'\n or #(50) o2(G5, F[8], F[9], F[10], F[11]);\n             ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:127: Signal definition not found, creating implicitly: \'G6\'\n                                                                     : ... Suggested alternative: \'G3\'\n or #(50) o3(G6, F[12], F[13], F[14], F[15]);\n             ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:128: Signal definition not found, creating implicitly: \'G7\'\n                                                                     : ... Suggested alternative: \'G3\'\n or #(50) o4(G7, F[16], F[17], F[18], F[19]);\n             ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:129: Signal definition not found, creating implicitly: \'G8\'\n                                                                     : ... Suggested alternative: \'G3\'\n or #(50) o5(G8, F[20], F[21], F[22], F[23]);\n             ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:130: Signal definition not found, creating implicitly: \'G9\'\n                                                                     : ... Suggested alternative: \'G3\'\n or #(50) o6(G9, F[24], F[25], F[26], F[27]);\n             ^~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:131: Signal definition not found, creating implicitly: \'G10\'\n or #(50) o7(G10, F[28], F[29], F[30], F[31]);\n             ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:132: Signal definition not found, creating implicitly: \'G11\'\n                                                                     : ... Suggested alternative: \'G10\'\n or #(50) o8(G11, G3, G4, G5, G6);\n             ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/MUX.v:133: Signal definition not found, creating implicitly: \'G12\'\n                                                                     : ... Suggested alternative: \'G10\'\n or #(50) o9(G12, G7, G8, G9, 10);\n             ^~~\n%Error: data/full_repos/permissive/127511545/src/MUX.v:90: Cannot find file containing module: \'Decoder5to32\'\n Decoder5to32 d5t32(OutputEnable, Select);\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/Decoder5to32\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/Decoder5to32.v\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/Decoder5to32.sv\n             Decoder5to32\n             Decoder5to32.v\n             Decoder5to32.sv\n             obj_dir/Decoder5to32\n             obj_dir/Decoder5to32.v\n             obj_dir/Decoder5to32.sv\n%Warning-WIDTH: data/full_repos/permissive/127511545/src/MUX.v:133: Operator OR expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'G7\' generates 1 bits.\n                                                                  : ... In instance MUX32x32to32.mux31\n or #(50) o9(G12, G7, G8, G9, 10);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/127511545/src/MUX.v:133: Operator OR expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'G8\' generates 1 bits.\n                                                                  : ... In instance MUX32x32to32.mux31\n or #(50) o9(G12, G7, G8, G9, 10);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/127511545/src/MUX.v:133: Operator OR expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'G9\' generates 1 bits.\n                                                                  : ... In instance MUX32x32to32.mux31\n or #(50) o9(G12, G7, G8, G9, 10);\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/127511545/src/MUX.v:133: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s OR generates 32 or 4 bits.\n                                                                  : ... In instance MUX32x32to32.mux31\n or #(50) o9(G12, G7, G8, G9, 10);\n          ^~\n%Error: Exiting due to 1 error(s), 18 warning(s)\n'
module MUX32x32to32(ReadData, Input0, Input1, Input2, Input3, Input4, Input5, Input6, Input7, Input8, Input9, Input10, Input11, Input12, Input13, Input14, Input15, Input16, Input17, Input18, Input19, Input20, Input21, Input22, Input23, Input24, Input25, Input26, Input27, Input28, Input29, Input30, Input31, ReadRegister);

	output [31:0] ReadData;
	input[31:0] Input0, Input1, Input2, Input3, Input4, Input5, Input6, Input7, Input8, Input9, Input10, Input11, Input12, Input13, Input14, Input15, Input16, Input17, Input18, Input19, Input20, Input21, Input22, Input23, Input24, Input25, Input26, Input27, Input28, Input29, Input30, Input31;
	input[4:0] ReadRegister;
	reg[31:0] ArrayRegister[0:31];
	integer j;

	always @(*)
		begin
			for (j = 0; j <= 31; j = j + 1)
				ArrayRegister[j] = {Input31[j], Input30[j], Input29[j], Input28[j], Input27[j], Input26[j], Input25[j], Input24[j], Input23[j], Input22[j], Input21[j], Input20[j], Input19[j], Input18[j], Input17[j], Input16[j], Input15[j], Input14[j], Input13[j], Input12[j], Input11[j], Input10[j], Input9[j], Input8[j], Input7[j], Input6[j], Input5[j], Input4[j], Input3[j], Input2[j], Input1[j], Input0[j]};
		end

	MUX32to1 mux0(ReadData[0], ArrayRegister[0], ReadRegister);
	MUX32to1 mux1(ReadData[1], ArrayRegister[1], ReadRegister);
	MUX32to1 mux2(ReadData[2], ArrayRegister[2], ReadRegister);
	MUX32to1 mux3(ReadData[3], ArrayRegister[3], ReadRegister);
	MUX32to1 mux4(ReadData[4], ArrayRegister[4], ReadRegister);
	MUX32to1 mux5(ReadData[5], ArrayRegister[5], ReadRegister);
	MUX32to1 mux6(ReadData[6], ArrayRegister[6], ReadRegister);
	MUX32to1 mux7(ReadData[7], ArrayRegister[7], ReadRegister);
	MUX32to1 mux8(ReadData[8], ArrayRegister[8], ReadRegister);
	MUX32to1 mux9(ReadData[9], ArrayRegister[9], ReadRegister);
	MUX32to1 mux10(ReadData[10], ArrayRegister[10], ReadRegister);
	MUX32to1 mux11(ReadData[11], ArrayRegister[11], ReadRegister);
	MUX32to1 mux12(ReadData[12], ArrayRegister[12], ReadRegister);
	MUX32to1 mux13(ReadData[13], ArrayRegister[13], ReadRegister);
	MUX32to1 mux14(ReadData[14], ArrayRegister[14], ReadRegister);
	MUX32to1 mux15(ReadData[15], ArrayRegister[15], ReadRegister);
	MUX32to1 mux16(ReadData[16], ArrayRegister[16], ReadRegister);
	MUX32to1 mux17(ReadData[17], ArrayRegister[17], ReadRegister);
	MUX32to1 mux18(ReadData[18], ArrayRegister[18], ReadRegister);
	MUX32to1 mux19(ReadData[19], ArrayRegister[19], ReadRegister);
	MUX32to1 mux20(ReadData[20], ArrayRegister[20], ReadRegister);
	MUX32to1 mux21(ReadData[21], ArrayRegister[21], ReadRegister);
	MUX32to1 mux22(ReadData[22], ArrayRegister[22], ReadRegister);
	MUX32to1 mux23(ReadData[23], ArrayRegister[23], ReadRegister);
	MUX32to1 mux24(ReadData[24], ArrayRegister[24], ReadRegister);
	MUX32to1 mux25(ReadData[25], ArrayRegister[25], ReadRegister);
	MUX32to1 mux26(ReadData[26], ArrayRegister[26], ReadRegister);
	MUX32to1 mux27(ReadData[27], ArrayRegister[27], ReadRegister);
	MUX32to1 mux28(ReadData[28], ArrayRegister[28], ReadRegister);
	MUX32to1 mux29(ReadData[29], ArrayRegister[29], ReadRegister);
	MUX32to1 mux30(ReadData[30], ArrayRegister[30], ReadRegister);
	MUX32to1 mux31(ReadData[31], ArrayRegister[31], ReadRegister);

endmodule
module MUX32x32to32(ReadData, Input0, Input1, Input2, Input3, Input4, Input5, Input6, Input7, Input8, Input9, Input10, Input11, Input12, Input13, Input14, Input15, Input16, Input17, Input18, Input19, Input20, Input21, Input22, Input23, Input24, Input25, Input26, Input27, Input28, Input29, Input30, Input31, ReadRegister);


	output [31:0] ReadData;
	input[31:0] Input0, Input1, Input2, Input3, Input4, Input5, Input6, Input7, Input8, Input9, Input10, Input11, Input12, Input13, Input14, Input15, Input16, Input17, Input18, Input19, Input20, Input21, Input22, Input23, Input24, Input25, Input26, Input27, Input28, Input29, Input30, Input31;
	input[4:0] ReadRegister;
	reg[31:0] ArrayRegister[0:31];
	integer j;

	always @(*)
		begin
			for (j = 0; j <= 31; j = j + 1)
				ArrayRegister[j] = {Input31[j], Input30[j], Input29[j], Input28[j], Input27[j], Input26[j], Input25[j], Input24[j], Input23[j], Input22[j], Input21[j], Input20[j], Input19[j], Input18[j], Input17[j], Input16[j], Input15[j], Input14[j], Input13[j], Input12[j], Input11[j], Input10[j], Input9[j], Input8[j], Input7[j], Input6[j], Input5[j], Input4[j], Input3[j], Input2[j], Input1[j], Input0[j]};
		end

	MUX32to1 mux0(ReadData[0], ArrayRegister[0], ReadRegister);
	MUX32to1 mux1(ReadData[1], ArrayRegister[1], ReadRegister);
	MUX32to1 mux2(ReadData[2], ArrayRegister[2], ReadRegister);
	MUX32to1 mux3(ReadData[3], ArrayRegister[3], ReadRegister);
	MUX32to1 mux4(ReadData[4], ArrayRegister[4], ReadRegister);
	MUX32to1 mux5(ReadData[5], ArrayRegister[5], ReadRegister);
	MUX32to1 mux6(ReadData[6], ArrayRegister[6], ReadRegister);
	MUX32to1 mux7(ReadData[7], ArrayRegister[7], ReadRegister);
	MUX32to1 mux8(ReadData[8], ArrayRegister[8], ReadRegister);
	MUX32to1 mux9(ReadData[9], ArrayRegister[9], ReadRegister);
	MUX32to1 mux10(ReadData[10], ArrayRegister[10], ReadRegister);
	MUX32to1 mux11(ReadData[11], ArrayRegister[11], ReadRegister);
	MUX32to1 mux12(ReadData[12], ArrayRegister[12], ReadRegister);
	MUX32to1 mux13(ReadData[13], ArrayRegister[13], ReadRegister);
	MUX32to1 mux14(ReadData[14], ArrayRegister[14], ReadRegister);
	MUX32to1 mux15(ReadData[15], ArrayRegister[15], ReadRegister);
	MUX32to1 mux16(ReadData[16], ArrayRegister[16], ReadRegister);
	MUX32to1 mux17(ReadData[17], ArrayRegister[17], ReadRegister);
	MUX32to1 mux18(ReadData[18], ArrayRegister[18], ReadRegister);
	MUX32to1 mux19(ReadData[19], ArrayRegister[19], ReadRegister);
	MUX32to1 mux20(ReadData[20], ArrayRegister[20], ReadRegister);
	MUX32to1 mux21(ReadData[21], ArrayRegister[21], ReadRegister);
	MUX32to1 mux22(ReadData[22], ArrayRegister[22], ReadRegister);
	MUX32to1 mux23(ReadData[23], ArrayRegister[23], ReadRegister);
	MUX32to1 mux24(ReadData[24], ArrayRegister[24], ReadRegister);
	MUX32to1 mux25(ReadData[25], ArrayRegister[25], ReadRegister);
	MUX32to1 mux26(ReadData[26], ArrayRegister[26], ReadRegister);
	MUX32to1 mux27(ReadData[27], ArrayRegister[27], ReadRegister);
	MUX32to1 mux28(ReadData[28], ArrayRegister[28], ReadRegister);
	MUX32to1 mux29(ReadData[29], ArrayRegister[29], ReadRegister);
	MUX32to1 mux30(ReadData[30], ArrayRegister[30], ReadRegister);
	MUX32to1 mux31(ReadData[31], ArrayRegister[31], ReadRegister);

endmodule