data/full_repos/permissive/125742950/RegisterUnit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/125742950/RegisterUnit.v:114: Operator ADD expects 12 bits on the LHS, but LHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                       : ... In instance RegisterUnit.PA3\n            Phase <= Phase + {4\'b0000 + TuningWord};\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/125742950/RegisterUnit.v:114: Operator ADD expects 16 bits on the RHS, but RHS\'s REPLICATE generates 12 bits.\n                                                                       : ... In instance RegisterUnit.PA3\n            Phase <= Phase + {4\'b0000 + TuningWord};\n                           ^\n%Error: Exiting due to 2 warning(s)\n'
module ToneRegister(CLK, RST, WE, DataIn, DataOut);
    input CLK, RST;
    input WE;
    input[11:0] DataIn;
    output reg[11:0] DataOut;
    
    always @ (posedge CLK or negedge RST) begin
        if(!RST) begin
            DataOut <= 12'd0;
        end else begin
            if(WE) DataOut <= DataIn;
            else DataOut <= DataOut;
        end
    end
endmodule
module ToneRegister(CLK, RST, WE, DataIn, DataOut);

    input CLK, RST;
    input WE;
    input[11:0] DataIn;
    output reg[11:0] DataOut;
    
    always @ (posedge CLK or negedge RST) begin
        if(!RST) begin
            DataOut <= 12'd0;
        end else begin
            if(WE) DataOut <= DataIn;
            else DataOut <= DataOut;
        end
    end
endmodule