data/full_repos/permissive/147086086/Lab2/hw/counter/counter_tb.v
 line:23: before: "i_rst_n"
1: b'%Warning-STMTDLY: data/full_repos/permissive/147086086/Lab2/hw/counter/counter_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    forever #(PERIOD/2) i_clk = ~i_clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/147086086/Lab2/hw/counter/counter_tb.v:23: syntax error, unexpected \'@\'\n    @(negedge i_clk) i_rst_n = 1;\n    ^\n%Error: data/full_repos/permissive/147086086/Lab2/hw/counter/counter_tb.v:25: syntax error, unexpected \'@\'\n    repeat (2000) @(negedge i_clk);\n                  ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

parameter PERIOD = 20;

reg         i_clk, i_rst_n;
wire [9:0]  o_cnt_dat;

counter cnt_inst(.MAX10_CLK1_50(i_clk), 
                    .KEY ({i_rst_n, 1'b0}), 
                    .LEDR (o_cnt_dat)
                );

initial begin
    i_clk = 0;
    forever #(PERIOD/2) i_clk = ~i_clk;
end

initial begin
    i_rst_n = 1'b0;

    @(negedge i_clk) i_rst_n = 1;

    repeat (2000) @(negedge i_clk);

    $finish;  
end
  
endmodule
module testbench;


parameter PERIOD = 20;

reg         i_clk, i_rst_n;
wire [9:0]  o_cnt_dat;

counter cnt_inst(.MAX10_CLK1_50(i_clk), 
                    .KEY ({i_rst_n, 1'b0}), 
                    .LEDR (o_cnt_dat)
                );

initial begin
    i_clk = 0;
    forever #(PERIOD/2) i_clk = ~i_clk;
end

initial begin
    i_rst_n = 1'b0;

    @(negedge i_clk) i_rst_n = 1;

    repeat (2000) @(negedge i_clk);

    $finish;  
end
  
endmodule