data/full_repos/permissive/139213403/FPGA/edge_trigger.v
1: b'%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/edge_trigger.v:19: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'wait_trigger\' generates 2 bits.\n                                                                           : ... In instance edge_trigger\n    state_reg <= wait_trigger;\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/edge_trigger.v:36: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'triggered\' generates 2 bits.\n                                                                           : ... In instance edge_trigger\n       state_next = triggered;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/edge_trigger.v:41: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'wait_trigger\' generates 2 bits.\n                                                                           : ... In instance edge_trigger\n      state_next = wait_trigger;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/edge_trigger.v:32: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'wait_trigger\' generates 2 bits.\n                                                                           : ... In instance edge_trigger\n   case (state_reg)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/edge_trigger.v:32: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'triggered\' generates 2 bits.\n                                                                           : ... In instance edge_trigger\n   case (state_reg)\n   ^~~~\n%Error: Exiting due to 5 warning(s)\n'
module edge_trigger
(
	input wire clk, reset,
	input wire in, en,
	output reg tick
);

	localparam wait_trigger = 2'd0,
	           triggered = 2'd1;

	reg in_reg, in_next;
	reg [2:0] state_reg, state_next;
	
	always @(posedge clk, posedge reset)
		if (reset)
			begin
				in_reg <= 0;
				state_reg <= wait_trigger;
			end
		else
			begin
				in_reg <= in_next;
				state_reg <= state_next;
			end
			
	always @*
		begin
			in_next = in;
			state_next = state_reg;
			tick = 0;
			case (state_reg)
				wait_trigger:
					if (in_next == en && in_reg == ~en)
						begin
							state_next = triggered;
							tick = 1'b1;
						end
				triggered:
					if (in_next == ~en)
						state_next = wait_trigger;
			endcase
		end
				  
endmodule
module edge_trigger
(
	input wire clk, reset,
	input wire in, en,
	output reg tick
);


	localparam wait_trigger = 2'd0,
	           triggered = 2'd1;

	reg in_reg, in_next;
	reg [2:0] state_reg, state_next;
	
	always @(posedge clk, posedge reset)
		if (reset)
			begin
				in_reg <= 0;
				state_reg <= wait_trigger;
			end
		else
			begin
				in_reg <= in_next;
				state_reg <= state_next;
			end
			
	always @*
		begin
			in_next = in;
			state_next = state_reg;
			tick = 0;
			case (state_reg)
				wait_trigger:
					if (in_next == en && in_reg == ~en)
						begin
							state_next = triggered;
							tick = 1'b1;
						end
				triggered:
					if (in_next == ~en)
						state_next = wait_trigger;
			endcase
		end
				  
endmodule