data/full_repos/permissive/105546923/infra/hdl/ram.v
 line:221: before: "for"
1: b'%Warning-MULTITOP: data/full_repos/permissive/105546923/infra/hdl/ram.v:36: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                          : ... Top module \'ram\'\nmodule ram(\n       ^~~\n                                                                          : ... Top module \'dram_256x16\'\nmodule dram_256x16(\n       ^~~~~~~~~~~\n                                                                          : ... Top module \'dram_512x8\'\nmodule dram_512x8(\n       ^~~~~~~~~~\n                                                                          : ... Top module \'dram_1024x4\'\nmodule dram_1024x4(\n       ^~~~~~~~~~~\n                                                                          : ... Top module \'dram_2048x2\'\nmodule dram_2048x2(\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/ram.v:266: Cannot find file containing module: \'SB_RAM40_4K\'\n   SB_RAM40_4K #(\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K\n             data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.v\n             data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.sv\n             SB_RAM40_4K\n             SB_RAM40_4K.v\n             SB_RAM40_4K.sv\n             obj_dir/SB_RAM40_4K\n             obj_dir/SB_RAM40_4K.v\n             obj_dir/SB_RAM40_4K.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module dram_1024x4(
		  input 		      w_clk,
		  input 		      r_clk,
		  input 		      w_clk_en,
		  input 		      r_clk_en,
		  input 		      we,
		  input [ADDR_WIDTH - 1 : 0]  waddr,
		  input [DATA_WIDTH - 1 : 0]  d,
		  input 		      re,
		  input [ADDR_WIDTH - 1 : 0]  raddr,
		  output [DATA_WIDTH - 1 : 0] q
		  );
   
   localparam DATA_WIDTH = 4;
   localparam ADDR_WIDTH = 10;

   localparam RAM_DATA_WIDTH = 16;
   localparam RAM_ADDR_WIDTH = 11;
   
   wire [RAM_DATA_WIDTH - 1 : 0] 	      _d, _q;
   wire [RAM_ADDR_WIDTH - 1 : 0] 	      _waddr, _raddr;			      

   assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
   assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };

   genvar 				      i;
   generate
   for (i = 0; i < 4; i=i+1)
     begin
	assign _d[i * 4 + 0] = 1'b0;
	assign _d[i * 4 + 1] = d[i];
	assign _d[i * 4 + 2] = 1'b0;
	assign _d[i * 4 + 3] = 1'b0;
	
	assign q[i] = _q[i * 4 + 1];
	
     end
   endgenerate
   
   dram_#(
	  .MODE(2)
	  ) dram_(
			.w_clk(w_clk),
			.r_clk(r_clk),
			.w_clk_en(w_clk_en),
			.r_clk_en(r_clk_en),
			.we(we),
			.waddr(_waddr),
			.d(_d),
			.re(re),
			.raddr(_raddr),
			.q(_q),
			.mask(16'b0)
			);
   
endmodule
module dram_1024x4(
		  input 		      w_clk,
		  input 		      r_clk,
		  input 		      w_clk_en,
		  input 		      r_clk_en,
		  input 		      we,
		  input [ADDR_WIDTH - 1 : 0]  waddr,
		  input [DATA_WIDTH - 1 : 0]  d,
		  input 		      re,
		  input [ADDR_WIDTH - 1 : 0]  raddr,
		  output [DATA_WIDTH - 1 : 0] q
		  );

   
   localparam DATA_WIDTH = 4;
   localparam ADDR_WIDTH = 10;

   localparam RAM_DATA_WIDTH = 16;
   localparam RAM_ADDR_WIDTH = 11;
   
   wire [RAM_DATA_WIDTH - 1 : 0] 	      _d, _q;
   wire [RAM_ADDR_WIDTH - 1 : 0] 	      _waddr, _raddr;			      

   assign _waddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {waddr} };
   assign _raddr = { {(RAM_ADDR_WIDTH - ADDR_WIDTH){1'b0}}, {raddr} };

   genvar 				      i;
   generate
   for (i = 0; i < 4; i=i+1)
     begin
	assign _d[i * 4 + 0] = 1'b0;
	assign _d[i * 4 + 1] = d[i];
	assign _d[i * 4 + 2] = 1'b0;
	assign _d[i * 4 + 3] = 1'b0;
	
	assign q[i] = _q[i * 4 + 1];
	
     end
   endgenerate
   
   dram_#(
	  .MODE(2)
	  ) dram_(
			.w_clk(w_clk),
			.r_clk(r_clk),
			.w_clk_en(w_clk_en),
			.r_clk_en(r_clk_en),
			.we(we),
			.waddr(_waddr),
			.d(_d),
			.re(re),
			.raddr(_raddr),
			.q(_q),
			.mask(16'b0)
			);
   
endmodule