data/full_repos/permissive/106966316/control_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n            #50\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n            #50;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n           #100\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n           #100\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n           #100\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n           #100\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/control_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n           #100;\n           ^\n%Error: data/full_repos/permissive/106966316/control_tb.v:36: Cannot find file containing module: \'control\'\n    control uut(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/control\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/control.v\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/control.sv\n             control\n             control.v\n             control.sv\n             obj_dir/control\n             obj_dir/control.v\n             obj_dir/control.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control_tb();
    reg [5:0] instru;
    reg clk;

    wire RegDest;
    wire SaltoCond;
    wire LeerMem;
    wire MemaReg;
    wire [1:0] ALUOp;
    wire EscrMem;
    wire FuenteALU;
    wire EscrReg;
    
    control uut(
        .instru(instru),
        .clk(clk),
        .RegDest(RegDest),
        .SaltoCond(SaltoCond),
        .LeerMem(LeerMem),
        .MemaReg(MemaReg),
        .ALUOp(ALUOp),
        .EscrMem(EscrMem),
        .FuenteALU(FuenteALU),
        .EscrReg(EscrReg)
        );
        
        always 
        begin
            clk=1'b1;
            #50
            clk=1'b0;
            #50;
         end
   initial begin
           instru=6'b000000;
           #100
		   instru=6'b000000;
           #100
           instru=6'b100011;
           #100
           instru=6'b101011;
           #100
           instru=6'b000100;
           #100;
   
   end     
    
        
    
endmodule
module control_tb();

    reg [5:0] instru;
    reg clk;

    wire RegDest;
    wire SaltoCond;
    wire LeerMem;
    wire MemaReg;
    wire [1:0] ALUOp;
    wire EscrMem;
    wire FuenteALU;
    wire EscrReg;
    
    control uut(
        .instru(instru),
        .clk(clk),
        .RegDest(RegDest),
        .SaltoCond(SaltoCond),
        .LeerMem(LeerMem),
        .MemaReg(MemaReg),
        .ALUOp(ALUOp),
        .EscrMem(EscrMem),
        .FuenteALU(FuenteALU),
        .EscrReg(EscrReg)
        );
        
        always 
        begin
            clk=1'b1;
            #50
            clk=1'b0;
            #50;
         end
   initial begin
           instru=6'b000000;
           #100
		   instru=6'b000000;
           #100
           instru=6'b100011;
           #100
           instru=6'b101011;
           #100
           instru=6'b000100;
           #100;
   
   end     
    
        
    
endmodule