data/full_repos/permissive/112219256/cpu_axi_interface.v
1: b'%Warning-WIDTH: data/full_repos/permissive/112219256/cpu_axi_interface.v:123: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n                                                                            : ... In instance cpu_axi_interface\n        do_arsize       <= !resetn        ? 3\'d0 :\n                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112219256/cpu_axi_interface.v:124: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_size\' generates 2 bits.\n                                                                            : ... In instance cpu_axi_interface\n                           r_addr_rcv_pos ? (do_req_raddr_or ? data_size : inst_size) : do_arsize;\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/cpu_axi_interface.v:124: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'inst_size\' generates 2 bits.\n                                                                            : ... In instance cpu_axi_interface\n                           r_addr_rcv_pos ? (do_req_raddr_or ? data_size : inst_size) : do_arsize;\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/cpu_axi_interface.v:217: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'do_arsize\' generates 32 bits.\n                                                                            : ... In instance cpu_axi_interface\n    assign arsize = do_arsize;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/112219256/cpu_axi_interface.v:229: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s VARREF \'do_dsize_r\' generates 2 bits.\n                                                                            : ... In instance cpu_axi_interface\n    assign awsize  = do_req_waddr ? do_dsize_r       : 3\'hx;\n                                  ^\n%Error: Exiting due to 5 warning(s)\n'
module cpu_axi_interface(
    input          clk,
    input          resetn,

    input          inst_req,
    input          inst_wr,
    input   [ 1:0] inst_size,
    input   [31:0] inst_addr,
    input   [31:0] inst_wdata,
    output  [31:0] inst_rdata,
    output         inst_addr_ok,
    output         inst_data_ok,

    input          data_req,
    input          data_wr,
    input   [ 1:0] data_size,
    input   [31:0] data_addr,
    input   [31:0] data_wdata,
    output  [31:0] data_rdata,
    output         data_addr_ok,
    output         data_data_ok,

    output  [ 3:0] arid,
    output  [31:0] araddr,
    output  [ 7:0] arlen,
    output  [ 2:0] arsize,
    output  [ 1:0] arburst,
    output  [ 1:0] arlock,
    output  [ 3:0] arcache,
    output  [ 2:0] arprot,
    output  reg    arvalid,
    input          arready,

    input   [ 3:0] rid,
    input   [31:0] rdata,
    input   [ 1:0] rresp,
    input          rlast,
    input          rvalid,
    output  reg    rready,

    output  [ 3:0] awid,
    output  [31:0] awaddr,
    output  [ 7:0] awlen,
    output  [ 2:0] awsize,
    output  [ 1:0] awburst,
    output  [ 1:0] awlock,
    output  [ 3:0] awcache,
    output  [ 2:0] awprot,
    output  reg    awvalid,
    input          awready,

    output  [ 3:0] wid,
    output  [31:0] wdata,
    output  [ 3:0] wstrb,
    output         wlast,
    output  reg    wvalid,
    input          wready,

    input   [ 3:0] bid,
    input   [ 1:0] bresp,
    input          bvalid,
    output  reg    bready
);    






    



    reg        do_req_raddr_or;
    reg [ 3:0] do_arid;
    reg [31:0] do_araddr;
    reg [31:0] do_arsize;
    reg  r_addr_rcv;
    reg  r_addr_rcv_r;
    wire r_data_back;
    wire r_addr_rcv_pos;


    reg  do_req_waddr;
    reg  do_req_waddr_r;
    wire do_req_waddr_pos;
    reg  do_req_wdata;
    reg  do_req_wdata_r;
    wire do_req_wdata_pos;
    reg  w_addr_rcv;
    reg  w_data_rcv;
    wire w_data_back;

    reg [31:0] do_wdata_r;
    reg [32:0] do_waddr_r;
    reg [ 1:0] do_dsize_r;

    reg [ 1:0] data_in_ready;
    reg [ 1:0] data_in_ready_r;
    wire data_in_ready_pos;

    reg  w_addr_rcv_r;
    reg  w_data_rcv_r;
    wire w_addr_rcv_pos;
    wire w_data_rcv_pos;


    assign inst_addr_ok  = arvalid&&arready && !do_req_raddr_or;
    assign data_addr_ok  = arvalid&&arready &&  do_req_raddr_or ||
                           data_in_ready==2'b01 && wvalid&&wready   && do_waddr_r[32] ||
                           data_in_ready==2'b10 && awvalid&&awready && do_waddr_r[32] ;

    always @ (posedge clk) begin



        do_req_raddr_or <= !resetn          ? 1'b0 :
                           arready&&arvalid ? (data_req&&!data_wr) : do_req_raddr_or;
        do_arid         <= !resetn        ? 4'd0 :
                           r_addr_rcv_pos ? (do_req_raddr_or ? 4'd1 : 4'd0) : do_arid;              
        do_araddr       <= !resetn        ? 32'd0 :
                           r_addr_rcv_pos ? (do_req_raddr_or ? data_addr : inst_addr) : do_araddr;
        do_arsize       <= !resetn        ? 3'd0 :
                           r_addr_rcv_pos ? (do_req_raddr_or ? data_size : inst_size) : do_arsize;
        arvalid         <= !resetn                                        ? 1'b0 :
                           r_addr_rcv_pos&&(inst_req||data_req&&!data_wr) ? 1'b1 :
                           arready                                        ? 1'b0 : 1'b1;

    end


    
    always @(posedge clk) begin
        r_addr_rcv <= !resetn          ? 1'b0 :
                      arvalid&&arready ? 1'b1 :
                      r_data_back      ? 1'b0 : r_addr_rcv;
        rready     <= !resetn          ? 1'b0 :
                      r_addr_rcv_pos   ? 1'b1 :
                      r_data_back      ? 1'b0 : rready;
    end


    assign r_data_back = r_addr_rcv && (rvalid && rready);




















    always @ (posedge clk) begin
        do_req_waddr     <= !resetn                            ? 1'b0 : 
                            data_req&&data_wr && !do_req_waddr ? 1'b1 :
                            w_data_back                        ? 1'b0 : do_req_waddr;
        do_req_wdata     <= !resetn                            ? 1'b0 :
                            data_req&&data_wr && !do_req_wdata ? 1'b1 :
                            w_data_back                        ? 1'b0 : do_req_wdata;
        do_waddr_r       <= !resetn           ? 33'd0 :
                            data_in_ready_pos ? {1'b1,data_addr} : do_waddr_r;
        do_wdata_r       <= data_in_ready_pos ? data_wdata : do_wdata_r;
        do_dsize_r       <= data_in_ready_pos ? data_size  : do_dsize_r;
        data_in_ready    <= !resetn                        ? 2'b00 :
                            w_addr_rcv_pos&&w_data_rcv_pos ? 2'b11 :
                            w_addr_rcv_pos                 ? data_in_ready + 2'b01 :
                            w_data_rcv_pos                 ? data_in_ready + 2'b10 :
                            w_data_back                    ? 2'b00 : data_in_ready;
        
        awvalid          <= !resetn                                ? 1'b0 :
                            do_req_waddr_pos                       ? 1'b1 :
                            awready                                ? 1'b0 : awvalid;
        wvalid           <= !resetn                                ? 1'b0 :
                            do_req_wdata_pos                       ? 1'b1 :
                            wready                                 ? 1'b0 : wvalid;



    end
    





    always @ (posedge clk) begin
        w_addr_rcv <= !resetn            ? 1'b0 :
                      awvalid&&awready   ? 1'b1 :
                      w_data_back        ? 1'b0 : w_addr_rcv; 
        w_data_rcv <= !resetn            ? 1'b0 :
                      wvalid&&wready     ? 1'b1 :
                      w_data_back        ? 1'b0 : w_data_rcv;
        bready     <= !resetn                ? 1'b0 :
                      w_addr_rcv&&w_data_rcv ? 1'b1 :
                      w_data_back            ? 1'b0 : bready;
    end

    assign w_data_back = (w_addr_rcv&&w_data_rcv) && (bvalid && bready);





    assign arid   = do_arid;
    assign araddr = do_araddr;
    assign arsize = do_arsize;

    assign arlen   = 8'd0;
    assign arburst = 2'b01;
    assign arlock  = 2'd0;
    assign arcache = 4'd0;
    assign arprot  = 3'd0;




    assign awaddr  = do_req_waddr ? do_waddr_r[31:0] : 32'hxxxxxxxx;
    assign awsize  = do_req_waddr ? do_dsize_r       : 3'hx;

    assign awid  = 4'd0;
    assign awlen = 8'd0;
    assign awburst = 2'b01;
    assign awlock  = 2'd0;
    assign awcache = 4'd0;
    assign awprot  = 3'd0;



    assign wdata = do_wdata_r;
    assign wstrb = do_dsize_r==2'd0 ? 4'b0001<<do_waddr_r[1:0] :
                   do_dsize_r==2'd1 ? 4'b0011<<do_waddr_r[1:0] : 4'b1111;

    assign wid    = 4'd0;
    assign wlast  = 1'b1;



    assign inst_data_ok =  r_data_back && rid==4'd0;
    assign data_data_ok = (r_data_back && rid==4'd1) || w_data_back;
    assign inst_rdata = rid==4'd0 ? rdata : 32'hxxxxxxxx;
    assign data_rdata = rid==4'd1 ? rdata : 32'hxxxxxxxx;



    always @ (posedge clk) begin
        r_addr_rcv_r    <= !resetn ? 1'b0 : r_addr_rcv;
        data_in_ready_r <= !resetn ? 2'd0 : data_in_ready;
        w_addr_rcv_r    <= !resetn ? 1'b0 : w_addr_rcv;
        w_data_rcv_r    <= !resetn ? 1'b0 : w_data_rcv;
        do_req_waddr_r  <= !resetn ? 1'b0 : do_req_waddr;
        do_req_wdata_r  <= !resetn ? 1'b0 : do_req_wdata;
    end

    assign r_addr_rcv_pos    = r_addr_rcv          & ~r_addr_rcv_r;
    assign data_in_ready_pos = data_in_ready==2'd3 & data_in_ready_r!=2'd3;
    assign w_addr_rcv_pos    = w_addr_rcv          & ~w_addr_rcv_r;
    assign w_data_rcv_pos    = w_data_rcv          & ~w_data_rcv_r;
    assign do_req_waddr_pos  = do_req_waddr        & ~do_req_waddr_r;
    assign do_req_wdata_pos  = do_req_wdata        & ~do_req_wdata_r;

integer wr_cnt;
always @ (posedge clk) begin
    if(!resetn) wr_cnt <= 'd0;
    else if(bvalid&&bready)
        wr_cnt <= wr_cnt + 'd1;
end
 
endmodule
module cpu_axi_interface(
    input          clk,
    input          resetn,

    input          inst_req,
    input          inst_wr,
    input   [ 1:0] inst_size,
    input   [31:0] inst_addr,
    input   [31:0] inst_wdata,
    output  [31:0] inst_rdata,
    output         inst_addr_ok,
    output         inst_data_ok,

    input          data_req,
    input          data_wr,
    input   [ 1:0] data_size,
    input   [31:0] data_addr,
    input   [31:0] data_wdata,
    output  [31:0] data_rdata,
    output         data_addr_ok,
    output         data_data_ok,

    output  [ 3:0] arid,
    output  [31:0] araddr,
    output  [ 7:0] arlen,
    output  [ 2:0] arsize,
    output  [ 1:0] arburst,
    output  [ 1:0] arlock,
    output  [ 3:0] arcache,
    output  [ 2:0] arprot,
    output  reg    arvalid,
    input          arready,

    input   [ 3:0] rid,
    input   [31:0] rdata,
    input   [ 1:0] rresp,
    input          rlast,
    input          rvalid,
    output  reg    rready,

    output  [ 3:0] awid,
    output  [31:0] awaddr,
    output  [ 7:0] awlen,
    output  [ 2:0] awsize,
    output  [ 1:0] awburst,
    output  [ 1:0] awlock,
    output  [ 3:0] awcache,
    output  [ 2:0] awprot,
    output  reg    awvalid,
    input          awready,

    output  [ 3:0] wid,
    output  [31:0] wdata,
    output  [ 3:0] wstrb,
    output         wlast,
    output  reg    wvalid,
    input          wready,

    input   [ 3:0] bid,
    input   [ 1:0] bresp,
    input          bvalid,
    output  reg    bready
);
    






    



    reg        do_req_raddr_or;
    reg [ 3:0] do_arid;
    reg [31:0] do_araddr;
    reg [31:0] do_arsize;
    reg  r_addr_rcv;
    reg  r_addr_rcv_r;
    wire r_data_back;
    wire r_addr_rcv_pos;


    reg  do_req_waddr;
    reg  do_req_waddr_r;
    wire do_req_waddr_pos;
    reg  do_req_wdata;
    reg  do_req_wdata_r;
    wire do_req_wdata_pos;
    reg  w_addr_rcv;
    reg  w_data_rcv;
    wire w_data_back;

    reg [31:0] do_wdata_r;
    reg [32:0] do_waddr_r;
    reg [ 1:0] do_dsize_r;

    reg [ 1:0] data_in_ready;
    reg [ 1:0] data_in_ready_r;
    wire data_in_ready_pos;

    reg  w_addr_rcv_r;
    reg  w_data_rcv_r;
    wire w_addr_rcv_pos;
    wire w_data_rcv_pos;


    assign inst_addr_ok  = arvalid&&arready && !do_req_raddr_or;
    assign data_addr_ok  = arvalid&&arready &&  do_req_raddr_or ||
                           data_in_ready==2'b01 && wvalid&&wready   && do_waddr_r[32] ||
                           data_in_ready==2'b10 && awvalid&&awready && do_waddr_r[32] ;

    always @ (posedge clk) begin



        do_req_raddr_or <= !resetn          ? 1'b0 :
                           arready&&arvalid ? (data_req&&!data_wr) : do_req_raddr_or;
        do_arid         <= !resetn        ? 4'd0 :
                           r_addr_rcv_pos ? (do_req_raddr_or ? 4'd1 : 4'd0) : do_arid;              
        do_araddr       <= !resetn        ? 32'd0 :
                           r_addr_rcv_pos ? (do_req_raddr_or ? data_addr : inst_addr) : do_araddr;
        do_arsize       <= !resetn        ? 3'd0 :
                           r_addr_rcv_pos ? (do_req_raddr_or ? data_size : inst_size) : do_arsize;
        arvalid         <= !resetn                                        ? 1'b0 :
                           r_addr_rcv_pos&&(inst_req||data_req&&!data_wr) ? 1'b1 :
                           arready                                        ? 1'b0 : 1'b1;

    end


    
    always @(posedge clk) begin
        r_addr_rcv <= !resetn          ? 1'b0 :
                      arvalid&&arready ? 1'b1 :
                      r_data_back      ? 1'b0 : r_addr_rcv;
        rready     <= !resetn          ? 1'b0 :
                      r_addr_rcv_pos   ? 1'b1 :
                      r_data_back      ? 1'b0 : rready;
    end


    assign r_data_back = r_addr_rcv && (rvalid && rready);




















    always @ (posedge clk) begin
        do_req_waddr     <= !resetn                            ? 1'b0 : 
                            data_req&&data_wr && !do_req_waddr ? 1'b1 :
                            w_data_back                        ? 1'b0 : do_req_waddr;
        do_req_wdata     <= !resetn                            ? 1'b0 :
                            data_req&&data_wr && !do_req_wdata ? 1'b1 :
                            w_data_back                        ? 1'b0 : do_req_wdata;
        do_waddr_r       <= !resetn           ? 33'd0 :
                            data_in_ready_pos ? {1'b1,data_addr} : do_waddr_r;
        do_wdata_r       <= data_in_ready_pos ? data_wdata : do_wdata_r;
        do_dsize_r       <= data_in_ready_pos ? data_size  : do_dsize_r;
        data_in_ready    <= !resetn                        ? 2'b00 :
                            w_addr_rcv_pos&&w_data_rcv_pos ? 2'b11 :
                            w_addr_rcv_pos                 ? data_in_ready + 2'b01 :
                            w_data_rcv_pos                 ? data_in_ready + 2'b10 :
                            w_data_back                    ? 2'b00 : data_in_ready;
        
        awvalid          <= !resetn                                ? 1'b0 :
                            do_req_waddr_pos                       ? 1'b1 :
                            awready                                ? 1'b0 : awvalid;
        wvalid           <= !resetn                                ? 1'b0 :
                            do_req_wdata_pos                       ? 1'b1 :
                            wready                                 ? 1'b0 : wvalid;



    end
    





    always @ (posedge clk) begin
        w_addr_rcv <= !resetn            ? 1'b0 :
                      awvalid&&awready   ? 1'b1 :
                      w_data_back        ? 1'b0 : w_addr_rcv; 
        w_data_rcv <= !resetn            ? 1'b0 :
                      wvalid&&wready     ? 1'b1 :
                      w_data_back        ? 1'b0 : w_data_rcv;
        bready     <= !resetn                ? 1'b0 :
                      w_addr_rcv&&w_data_rcv ? 1'b1 :
                      w_data_back            ? 1'b0 : bready;
    end

    assign w_data_back = (w_addr_rcv&&w_data_rcv) && (bvalid && bready);





    assign arid   = do_arid;
    assign araddr = do_araddr;
    assign arsize = do_arsize;

    assign arlen   = 8'd0;
    assign arburst = 2'b01;
    assign arlock  = 2'd0;
    assign arcache = 4'd0;
    assign arprot  = 3'd0;




    assign awaddr  = do_req_waddr ? do_waddr_r[31:0] : 32'hxxxxxxxx;
    assign awsize  = do_req_waddr ? do_dsize_r       : 3'hx;

    assign awid  = 4'd0;
    assign awlen = 8'd0;
    assign awburst = 2'b01;
    assign awlock  = 2'd0;
    assign awcache = 4'd0;
    assign awprot  = 3'd0;



    assign wdata = do_wdata_r;
    assign wstrb = do_dsize_r==2'd0 ? 4'b0001<<do_waddr_r[1:0] :
                   do_dsize_r==2'd1 ? 4'b0011<<do_waddr_r[1:0] : 4'b1111;

    assign wid    = 4'd0;
    assign wlast  = 1'b1;



    assign inst_data_ok =  r_data_back && rid==4'd0;
    assign data_data_ok = (r_data_back && rid==4'd1) || w_data_back;
    assign inst_rdata = rid==4'd0 ? rdata : 32'hxxxxxxxx;
    assign data_rdata = rid==4'd1 ? rdata : 32'hxxxxxxxx;



    always @ (posedge clk) begin
        r_addr_rcv_r    <= !resetn ? 1'b0 : r_addr_rcv;
        data_in_ready_r <= !resetn ? 2'd0 : data_in_ready;
        w_addr_rcv_r    <= !resetn ? 1'b0 : w_addr_rcv;
        w_data_rcv_r    <= !resetn ? 1'b0 : w_data_rcv;
        do_req_waddr_r  <= !resetn ? 1'b0 : do_req_waddr;
        do_req_wdata_r  <= !resetn ? 1'b0 : do_req_wdata;
    end

    assign r_addr_rcv_pos    = r_addr_rcv          & ~r_addr_rcv_r;
    assign data_in_ready_pos = data_in_ready==2'd3 & data_in_ready_r!=2'd3;
    assign w_addr_rcv_pos    = w_addr_rcv          & ~w_addr_rcv_r;
    assign w_data_rcv_pos    = w_data_rcv          & ~w_data_rcv_r;
    assign do_req_waddr_pos  = do_req_waddr        & ~do_req_waddr_r;
    assign do_req_wdata_pos  = do_req_wdata        & ~do_req_wdata_r;

integer wr_cnt;
always @ (posedge clk) begin
    if(!resetn) wr_cnt <= 'd0;
    else if(bvalid&&bready)
        wr_cnt <= wr_cnt + 'd1;
end
 
endmodule