data/full_repos/permissive/114091260/material/CPU设计代码/第二步/VGA显示/d_memory.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/fe7ed3a9-4bef-4155-903f-574297a6de71.xml
module d_memory(
    input clk,
    input rst,
    input [7:0] addr,
    input we,
    input [15:0] datain,
    output [15:0] dataout
    );

	reg [15:0] RAM[255:0];
	
	assign dataout = RAM[addr];
	always @(posedge clk or negedge rst)
		begin
			if (!rst)
				begin
					RAM[0] <= 16'h00AB;
					RAM[1] <= 16'h3C00;
					RAM[2] <= 16'h0000;
				end
			else if (we)
				RAM[addr] <= datain;
		end

endmodule
module d_memory(
    input clk,
    input rst,
    input [7:0] addr,
    input we,
    input [15:0] datain,
    output [15:0] dataout
    );


	reg [15:0] RAM[255:0];
	
	assign dataout = RAM[addr];
	always @(posedge clk or negedge rst)
		begin
			if (!rst)
				begin
					RAM[0] <= 16'h00AB;
					RAM[1] <= 16'h3C00;
					RAM[2] <= 16'h0000;
				end
			else if (we)
				RAM[addr] <= datain;
		end

endmodule