data/full_repos/permissive/148201731/rtl/decode/instruction_decoder.v
None: at end of input
1: b'%Error: data/full_repos/permissive/148201731/rtl/decode/instruction_decoder.v:64: Cannot find include file: opcodes.v\n`include "opcodes.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/148201731/rtl/decode,data/full_repos/permissive/148201731/opcodes.v\n             data/full_repos/permissive/148201731/rtl/decode,data/full_repos/permissive/148201731/opcodes.v.v\n             data/full_repos/permissive/148201731/rtl/decode,data/full_repos/permissive/148201731/opcodes.v.sv\n             opcodes.v\n             opcodes.v.v\n             opcodes.v.sv\n             obj_dir/opcodes.v\n             obj_dir/opcodes.v.v\n             obj_dir/opcodes.v.sv\n%Error: Exiting due to 1 error(s)\n'
module instruction_decoder
#(
   parameter INSTRUCTION_WIDTH = 32,
   parameter OPCODE_WIDTH = 6,
   parameter FUNCTION_WIDTH = 5,
   parameter REG_ADDR_WIDTH = 5,
   parameter IMEDIATE_WIDTH = 16,
   parameter PC_OFFSET_WIDTH = 26
)
(
   input [INSTRUCTION_WIDTH-1:0] instruction_in,
   output [OPCODE_WIDTH-1:0] opcode,
   output reg [FUNCTION_WIDTH-1:0] inst_function,
   output reg [REG_ADDR_WIDTH-1:0] reg_rd_addr1_out,
   output reg [REG_ADDR_WIDTH-1:0] reg_rd_addr2_out,
   output reg reg_rd_en1_out,
   output reg reg_rd_en2_out,
   output reg [REG_ADDR_WIDTH-1:0] reg_a_wr_addr_out,
   output reg [REG_ADDR_WIDTH-1:0] reg_b_wr_addr_out,
   output reg reg_a_wr_en_out,
   output reg reg_b_wr_en_out,
   output reg [IMEDIATE_WIDTH-1:0] immediate_out,
   output reg imm_inst_out,
   output reg [PC_OFFSET_WIDTH-1:0] pc_offset,
   output reg mem_data_rd_en_out,
   output reg mem_data_wr_en_out,
   output reg write_back_mux_sel_out,
   output reg branch_inst_out,
   output reg branch_use_r_out,
   output reg jump_inst_out,
   output reg jump_use_r_out
);





`include "opcodes.v"



   wire [FUNCTION_WIDTH-1:0] inst_function_in;

   assign opcode = instruction_in[31:26];
   assign inst_function_in = instruction_in[5:0];

   always @(*) begin
      if(instruction_in=={INSTRUCTION_WIDTH{1'b0}})begin
         inst_function = 0;
         reg_rd_addr1_out = 0;
         reg_rd_addr2_out = 0;
         reg_rd_en1_out = 0;
         reg_rd_en2_out = 0;
         reg_a_wr_addr_out = 0;
         reg_b_wr_addr_out = 0;
         reg_a_wr_en_out = 1'b0;
         reg_b_wr_en_out = 1'b0;
         immediate_out = 0;
         imm_inst_out = 1'b0;
         pc_offset = 0;
         mem_data_rd_en_out = 1'b0;
         mem_data_wr_en_out = 1'b0;
         write_back_mux_sel_out = 1'b0;
         branch_inst_out = 1'b0;
         branch_use_r_out = 1'b0;
         jump_inst_out = 1'b0;
         jump_use_r_out = 1'b0;
      end
      else begin
         case (opcode)




            R_TYPE_OPCODE: begin
              case(inst_function_in)
               MULT_FUNCTION, DIV_FUNCTION : begin
                  inst_function = instruction_in[5:0];
                  reg_rd_addr1_out = instruction_in[25:21];
                  reg_rd_addr2_out = instruction_in[20:16];
                  reg_rd_en1_out = 1'b1;
                  reg_rd_en2_out = 1'b1;
                  reg_a_wr_addr_out = instruction_in[25:21];
                  reg_b_wr_addr_out = instruction_in[20:16];
                  reg_a_wr_en_out = 1'b1;
                  reg_b_wr_en_out = 1'b1;
                  immediate_out = 0;
                  imm_inst_out = 1'b0;
                  pc_offset = 0;
                  mem_data_rd_en_out = 1'b0;
                  mem_data_wr_en_out = 1'b0;
                  write_back_mux_sel_out = 1'b0;
                  branch_inst_out = 1'b0;
                  branch_use_r_out = 1'b0;
                  jump_inst_out = 1'b0;
                  jump_use_r_out = 1'b0;
               end
               JR_FUNCTION: begin
                  reg_rd_addr1_out = instruction_in[25:21];
                  reg_rd_addr2_out = 0;
                  reg_rd_en1_out = 1;
                  reg_rd_en2_out = 0;
                  reg_a_wr_addr_out = 0;
                  reg_b_wr_addr_out = 0;
                  reg_a_wr_en_out = 1'b0;
                  reg_b_wr_en_out = 1'b0;
                  immediate_out = instruction_in[15:0];
                  imm_inst_out = 1'b0;
                  pc_offset = 0;
                  mem_data_rd_en_out = 1'b0;
                  mem_data_wr_en_out = 1'b0;
                  write_back_mux_sel_out = 1'b0;
                  branch_inst_out = 1'b0;
                  branch_use_r_out = 1'b0;
                  jump_inst_out = 1'b1;
                  jump_use_r_out = 1'b1;
               end
               JALR_FUNCTION: begin
                  reg_rd_addr1_out = instruction_in[25:21];
                  reg_rd_addr2_out = 0;
                  reg_rd_en1_out = 1;
                  reg_rd_en2_out = 0;
                  reg_a_wr_addr_out = instruction_in[15:11];
                  reg_b_wr_addr_out = 0;
                  reg_a_wr_en_out = 1'b1;
                  reg_b_wr_en_out = 1'b0;
                  immediate_out = instruction_in[15:0];
                  imm_inst_out = 1'b0;
                  pc_offset = 0;
                  mem_data_rd_en_out = 1'b0;
                  mem_data_wr_en_out = 1'b0;
                  write_back_mux_sel_out = 1'b0;
                  branch_inst_out = 1'b0;
                  branch_use_r_out = 1'b0;
                  jump_inst_out = 1'b1;
                  jump_use_r_out = 1'b1;
               end
               default: begin
                  inst_function = instruction_in[5:0];
                  reg_rd_addr1_out = instruction_in[25:21];
                  reg_rd_addr2_out = instruction_in[20:16];
                  reg_rd_en1_out = 1'b1;
                  reg_rd_en2_out = 1'b1;
                  reg_a_wr_addr_out = instruction_in[15:11];
                  reg_b_wr_addr_out = 0;
                  reg_a_wr_en_out = 1'b1;
                  reg_b_wr_en_out = 1'b0;
                  immediate_out = 0;
                  imm_inst_out = 1'b0;
                  pc_offset = 0;
                  mem_data_rd_en_out = 1'b0;
                  mem_data_wr_en_out = 1'b0;
                  write_back_mux_sel_out = 1'b0;
                  branch_inst_out = 1'b0;
                  branch_use_r_out = 1'b0;
                  jump_inst_out = 1'b0;
                  jump_use_r_out = 1'b0;
               end
	       endcase
            end




            ADDI_OPCODE,SUBI_OPCODE,ANDI_OPCODE,ORI_OPCODE: begin
               reg_rd_addr1_out = instruction_in[25:21];
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 1;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = instruction_in[20:16];
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b1;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[15:0];
               imm_inst_out = 1'b1;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b0;
               jump_use_r_out = 1'b0;
            end




            LW_OPCODE: begin
               reg_rd_addr1_out = instruction_in[25:21];
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 1;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = instruction_in[20:16];
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b1;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[15:0];
               imm_inst_out = 1'b1;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b1;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b1;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b0;
               jump_use_r_out = 1'b0;

            end




            SW_OPCODE: begin
               reg_rd_addr1_out = instruction_in[25:21];
               reg_rd_addr2_out = instruction_in[20:16];
               reg_rd_en1_out = 1;
               reg_rd_en2_out = 1;
               reg_a_wr_addr_out = 0;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b0;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[15:0];
               imm_inst_out = 1'b1;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b1;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b0;
               jump_use_r_out = 1'b0;
            end




            BEQZ_OPCODE,BNEZ_OPCODE: begin
               reg_rd_addr1_out = instruction_in[25:21];
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 1;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = 0;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b0;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[15:0];
               imm_inst_out = 1'b1;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b1;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b0;
               jump_use_r_out = 1'b0;
            end
            BRFL_OPCODE: begin
               reg_rd_addr1_out = instruction_in[25:21];
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 1;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = 0;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b0;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[15:0];
               imm_inst_out = 1'b1;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b1;
               branch_use_r_out = 1'b1;
               jump_inst_out = 1'b0;
               jump_use_r_out = 1'b0;
            end




















































            JPC_OPCODE: begin
               reg_rd_addr1_out = 0;
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 0;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = 0;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b0;
               reg_b_wr_en_out = 1'b0;
               immediate_out = 0;
               imm_inst_out = 1'b0;
               pc_offset = instruction_in[25:0];
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b1;
               jump_use_r_out = 1'b0;
            end




            JAL_OPCODE,CALL_OPCODE: begin
               reg_rd_addr1_out = 0;
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 0;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = 'd31;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b1;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[25:0];
               imm_inst_out = 1'b0;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b1;
               jump_use_r_out = 1'b0;
            end




	    RET_OPCODE :begin
               reg_rd_addr1_out = 31;
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 1;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = 0;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b0;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[15:0];
               imm_inst_out = 1'b0;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b1;
               jump_use_r_out = 1'b1;
            end

            default : begin
               inst_function = 0;
               reg_rd_addr1_out = 0;
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 0;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = 0;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b0;
               reg_b_wr_en_out = 1'b0;
               immediate_out = 0;
               imm_inst_out = 1'b0;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b0;
               jump_use_r_out = 1'b0;
            end
         endcase
      end
   end

endmodule
module instruction_decoder
#(
   parameter INSTRUCTION_WIDTH = 32,
   parameter OPCODE_WIDTH = 6,
   parameter FUNCTION_WIDTH = 5,
   parameter REG_ADDR_WIDTH = 5,
   parameter IMEDIATE_WIDTH = 16,
   parameter PC_OFFSET_WIDTH = 26
)
(
   input [INSTRUCTION_WIDTH-1:0] instruction_in,
   output [OPCODE_WIDTH-1:0] opcode,
   output reg [FUNCTION_WIDTH-1:0] inst_function,
   output reg [REG_ADDR_WIDTH-1:0] reg_rd_addr1_out,
   output reg [REG_ADDR_WIDTH-1:0] reg_rd_addr2_out,
   output reg reg_rd_en1_out,
   output reg reg_rd_en2_out,
   output reg [REG_ADDR_WIDTH-1:0] reg_a_wr_addr_out,
   output reg [REG_ADDR_WIDTH-1:0] reg_b_wr_addr_out,
   output reg reg_a_wr_en_out,
   output reg reg_b_wr_en_out,
   output reg [IMEDIATE_WIDTH-1:0] immediate_out,
   output reg imm_inst_out,
   output reg [PC_OFFSET_WIDTH-1:0] pc_offset,
   output reg mem_data_rd_en_out,
   output reg mem_data_wr_en_out,
   output reg write_back_mux_sel_out,
   output reg branch_inst_out,
   output reg branch_use_r_out,
   output reg jump_inst_out,
   output reg jump_use_r_out
);






`include "opcodes.v"



   wire [FUNCTION_WIDTH-1:0] inst_function_in;

   assign opcode = instruction_in[31:26];
   assign inst_function_in = instruction_in[5:0];

   always @(*) begin
      if(instruction_in=={INSTRUCTION_WIDTH{1'b0}})begin
         inst_function = 0;
         reg_rd_addr1_out = 0;
         reg_rd_addr2_out = 0;
         reg_rd_en1_out = 0;
         reg_rd_en2_out = 0;
         reg_a_wr_addr_out = 0;
         reg_b_wr_addr_out = 0;
         reg_a_wr_en_out = 1'b0;
         reg_b_wr_en_out = 1'b0;
         immediate_out = 0;
         imm_inst_out = 1'b0;
         pc_offset = 0;
         mem_data_rd_en_out = 1'b0;
         mem_data_wr_en_out = 1'b0;
         write_back_mux_sel_out = 1'b0;
         branch_inst_out = 1'b0;
         branch_use_r_out = 1'b0;
         jump_inst_out = 1'b0;
         jump_use_r_out = 1'b0;
      end
      else begin
         case (opcode)




            R_TYPE_OPCODE: begin
              case(inst_function_in)
               MULT_FUNCTION, DIV_FUNCTION : begin
                  inst_function = instruction_in[5:0];
                  reg_rd_addr1_out = instruction_in[25:21];
                  reg_rd_addr2_out = instruction_in[20:16];
                  reg_rd_en1_out = 1'b1;
                  reg_rd_en2_out = 1'b1;
                  reg_a_wr_addr_out = instruction_in[25:21];
                  reg_b_wr_addr_out = instruction_in[20:16];
                  reg_a_wr_en_out = 1'b1;
                  reg_b_wr_en_out = 1'b1;
                  immediate_out = 0;
                  imm_inst_out = 1'b0;
                  pc_offset = 0;
                  mem_data_rd_en_out = 1'b0;
                  mem_data_wr_en_out = 1'b0;
                  write_back_mux_sel_out = 1'b0;
                  branch_inst_out = 1'b0;
                  branch_use_r_out = 1'b0;
                  jump_inst_out = 1'b0;
                  jump_use_r_out = 1'b0;
               end
               JR_FUNCTION: begin
                  reg_rd_addr1_out = instruction_in[25:21];
                  reg_rd_addr2_out = 0;
                  reg_rd_en1_out = 1;
                  reg_rd_en2_out = 0;
                  reg_a_wr_addr_out = 0;
                  reg_b_wr_addr_out = 0;
                  reg_a_wr_en_out = 1'b0;
                  reg_b_wr_en_out = 1'b0;
                  immediate_out = instruction_in[15:0];
                  imm_inst_out = 1'b0;
                  pc_offset = 0;
                  mem_data_rd_en_out = 1'b0;
                  mem_data_wr_en_out = 1'b0;
                  write_back_mux_sel_out = 1'b0;
                  branch_inst_out = 1'b0;
                  branch_use_r_out = 1'b0;
                  jump_inst_out = 1'b1;
                  jump_use_r_out = 1'b1;
               end
               JALR_FUNCTION: begin
                  reg_rd_addr1_out = instruction_in[25:21];
                  reg_rd_addr2_out = 0;
                  reg_rd_en1_out = 1;
                  reg_rd_en2_out = 0;
                  reg_a_wr_addr_out = instruction_in[15:11];
                  reg_b_wr_addr_out = 0;
                  reg_a_wr_en_out = 1'b1;
                  reg_b_wr_en_out = 1'b0;
                  immediate_out = instruction_in[15:0];
                  imm_inst_out = 1'b0;
                  pc_offset = 0;
                  mem_data_rd_en_out = 1'b0;
                  mem_data_wr_en_out = 1'b0;
                  write_back_mux_sel_out = 1'b0;
                  branch_inst_out = 1'b0;
                  branch_use_r_out = 1'b0;
                  jump_inst_out = 1'b1;
                  jump_use_r_out = 1'b1;
               end
               default: begin
                  inst_function = instruction_in[5:0];
                  reg_rd_addr1_out = instruction_in[25:21];
                  reg_rd_addr2_out = instruction_in[20:16];
                  reg_rd_en1_out = 1'b1;
                  reg_rd_en2_out = 1'b1;
                  reg_a_wr_addr_out = instruction_in[15:11];
                  reg_b_wr_addr_out = 0;
                  reg_a_wr_en_out = 1'b1;
                  reg_b_wr_en_out = 1'b0;
                  immediate_out = 0;
                  imm_inst_out = 1'b0;
                  pc_offset = 0;
                  mem_data_rd_en_out = 1'b0;
                  mem_data_wr_en_out = 1'b0;
                  write_back_mux_sel_out = 1'b0;
                  branch_inst_out = 1'b0;
                  branch_use_r_out = 1'b0;
                  jump_inst_out = 1'b0;
                  jump_use_r_out = 1'b0;
               end
	       endcase
            end




            ADDI_OPCODE,SUBI_OPCODE,ANDI_OPCODE,ORI_OPCODE: begin
               reg_rd_addr1_out = instruction_in[25:21];
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 1;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = instruction_in[20:16];
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b1;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[15:0];
               imm_inst_out = 1'b1;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b0;
               jump_use_r_out = 1'b0;
            end




            LW_OPCODE: begin
               reg_rd_addr1_out = instruction_in[25:21];
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 1;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = instruction_in[20:16];
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b1;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[15:0];
               imm_inst_out = 1'b1;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b1;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b1;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b0;
               jump_use_r_out = 1'b0;

            end




            SW_OPCODE: begin
               reg_rd_addr1_out = instruction_in[25:21];
               reg_rd_addr2_out = instruction_in[20:16];
               reg_rd_en1_out = 1;
               reg_rd_en2_out = 1;
               reg_a_wr_addr_out = 0;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b0;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[15:0];
               imm_inst_out = 1'b1;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b1;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b0;
               jump_use_r_out = 1'b0;
            end




            BEQZ_OPCODE,BNEZ_OPCODE: begin
               reg_rd_addr1_out = instruction_in[25:21];
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 1;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = 0;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b0;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[15:0];
               imm_inst_out = 1'b1;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b1;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b0;
               jump_use_r_out = 1'b0;
            end
            BRFL_OPCODE: begin
               reg_rd_addr1_out = instruction_in[25:21];
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 1;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = 0;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b0;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[15:0];
               imm_inst_out = 1'b1;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b1;
               branch_use_r_out = 1'b1;
               jump_inst_out = 1'b0;
               jump_use_r_out = 1'b0;
            end




















































            JPC_OPCODE: begin
               reg_rd_addr1_out = 0;
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 0;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = 0;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b0;
               reg_b_wr_en_out = 1'b0;
               immediate_out = 0;
               imm_inst_out = 1'b0;
               pc_offset = instruction_in[25:0];
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b1;
               jump_use_r_out = 1'b0;
            end




            JAL_OPCODE,CALL_OPCODE: begin
               reg_rd_addr1_out = 0;
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 0;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = 'd31;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b1;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[25:0];
               imm_inst_out = 1'b0;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b1;
               jump_use_r_out = 1'b0;
            end




	    RET_OPCODE :begin
               reg_rd_addr1_out = 31;
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 1;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = 0;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b0;
               reg_b_wr_en_out = 1'b0;
               immediate_out = instruction_in[15:0];
               imm_inst_out = 1'b0;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b1;
               jump_use_r_out = 1'b1;
            end

            default : begin
               inst_function = 0;
               reg_rd_addr1_out = 0;
               reg_rd_addr2_out = 0;
               reg_rd_en1_out = 0;
               reg_rd_en2_out = 0;
               reg_a_wr_addr_out = 0;
               reg_b_wr_addr_out = 0;
               reg_a_wr_en_out = 1'b0;
               reg_b_wr_en_out = 1'b0;
               immediate_out = 0;
               imm_inst_out = 1'b0;
               pc_offset = 0;
               mem_data_rd_en_out = 1'b0;
               mem_data_wr_en_out = 1'b0;
               write_back_mux_sel_out = 1'b0;
               branch_inst_out = 1'b0;
               branch_use_r_out = 1'b0;
               jump_inst_out = 1'b0;
               jump_use_r_out = 1'b0;
            end
         endcase
      end
   end

endmodule