data/full_repos/permissive/194847941/demo/5_RGB_LED/Running_led_tdmap.v
1: b"%Error: data/full_repos/permissive/194847941/demo/5_RGB_LED/Running_led_tdmap.v:83: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    .do({open_n18,open_n19,open_n20,led_b_pad}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/5_RGB_LED/Running_led_tdmap.v:83: syntax error, unexpected '(', expecting ')'\n    .do({open_n18,open_n19,open_n20,led_b_pad}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/5_RGB_LED/Running_led_tdmap.v:177: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n35,open_n36,open_n37,led_g_pad}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/5_RGB_LED/Running_led_tdmap.v:177: syntax error, unexpected '(', expecting ')'\n    .do({open_n35,open_n36,open_n37,led_g_pad}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/5_RGB_LED/Running_led_tdmap.v:269: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n52,open_n53,open_n54,led_r_pad}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/5_RGB_LED/Running_led_tdmap.v:269: syntax error, unexpected '(', expecting ')'\n    .do({open_n52,open_n53,open_n54,led_r_pad}),\n        ^\n%Error: Exiting due to 6 error(s)\n"
module reg_ar_ss_w1
  (
  clk,
  d,
  en,
  reset,
  set,
  q
  );

  input clk;
  input d;
  input en;
  input reset;
  input set;
  output q;

  parameter REGSET = "RESET";
  wire enout;
  wire setout;

  AL_MUX u_en0 (
    .i0(q),
    .i1(d),
    .sel(en),
    .o(enout));
  AL_DFF #(
    .INI((REGSET == "SET") ? 1'b1 : 1'b0))
    u_seq0 (
    .clk(clk),
    .d(setout),
    .reset(reset),
    .set(1'b0),
    .q(q));
  AL_MUX u_set0 (
    .i0(enout),
    .i1(1'b1),
    .sel(set),
    .o(setout));

endmodule
module reg_ar_ss_w1
  (
  clk,
  d,
  en,
  reset,
  set,
  q
  );


  input clk;
  input d;
  input en;
  input reset;
  input set;
  output q;

  parameter REGSET = "RESET";
  wire enout;
  wire setout;

  AL_MUX u_en0 (
    .i0(q),
    .i1(d),
    .sel(en),
    .o(enout));
  AL_DFF #(
    .INI((REGSET == "SET") ? 1'b1 : 1'b0))
    u_seq0 (
    .clk(clk),
    .d(setout),
    .reset(reset),
    .set(1'b0),
    .q(q));
  AL_MUX u_set0 (
    .i0(enout),
    .i1(1'b1),
    .sel(set),
    .o(setout));

endmodule