data/full_repos/permissive/101427397/v/SSeg7_Dev_IO.v
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data/verilator_xmls/3398ffe9-bbac-4572-8055-c2b09c1d63a5.xml
module  SSeg7_Dev(input clk,
						input rst,
						input Start,
						input SW0,
						input flash,
						input[31:0]Hexs,
						input[7:0]point,
						input[7:0]LES,
						output seg_clk,
						output seg_sout,
						output SEG_PEN,
						output seg_clrn
						);

endmodule
module  SSeg7_Dev(input clk,
						input rst,
						input Start,
						input SW0,
						input flash,
						input[31:0]Hexs,
						input[7:0]point,
						input[7:0]LES,
						output seg_clk,
						output seg_sout,
						output SEG_PEN,
						output seg_clrn
						);


endmodule