data/full_repos/permissive/143278/ivltests/pr3197917.v
 line:16: before: "["
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3197917.v:8: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr3197917.v:16: Duplicate declaration of port: \'arg\'\nmodule test(arg[119:96], arg[78:24]);\n                         ^~~\n        data/full_repos/permissive/143278/ivltests/pr3197917.v:17: ... Location of original declaration\n  input [119:24] arg;\n                 ^~~\n%Error: data/full_repos/permissive/143278/ivltests/pr3197917.v:13: Duplicate pin connection: \'__pinNumber2\'\n  test dut(in1, in2);\n                ^~~\n        data/full_repos/permissive/143278/ivltests/pr3197917.v:13: ... Location of original pin connection\n  test dut(in1, in2);\n           ^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test(arg[119:96], arg[78:24]);
  input [119:24] arg;

endmodule
module test(arg[119:96], arg[78:24]);

  input [119:24] arg;

endmodule