data/full_repos/permissive/201267735/rtl/wrapper/frv_bus_splitter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/201267735/rtl/wrapper/frv_bus_splitter.v:74: Operator ADD expects 3 bits on the RHS, but RHS\'s VARREF \'m0_req_now\' generates 1 bits.\n                                                                                      : ... In instance frv_bus_splitter\nwire [2:0] n_m0_reqs_out = (m0_reqs_out + m0_req_now) - m0_rsp_now;\n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/201267735/rtl/wrapper/frv_bus_splitter.v:74: Operator SUB expects 3 bits on the RHS, but RHS\'s VARREF \'m0_rsp_now\' generates 1 bits.\n                                                                                      : ... In instance frv_bus_splitter\nwire [2:0] n_m0_reqs_out = (m0_reqs_out + m0_req_now) - m0_rsp_now;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/201267735/rtl/wrapper/frv_bus_splitter.v:75: Operator ADD expects 3 bits on the RHS, but RHS\'s VARREF \'m1_req_now\' generates 1 bits.\n                                                                                      : ... In instance frv_bus_splitter\nwire [2:0] n_m1_reqs_out = (m1_reqs_out + m1_req_now) - m1_rsp_now;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/201267735/rtl/wrapper/frv_bus_splitter.v:75: Operator SUB expects 3 bits on the RHS, but RHS\'s VARREF \'m1_rsp_now\' generates 1 bits.\n                                                                                      : ... In instance frv_bus_splitter\nwire [2:0] n_m1_reqs_out = (m1_reqs_out + m1_req_now) - m1_rsp_now;\n                                                      ^\n%Error: Exiting due to 4 warning(s)\n'
module frv_bus_splitter (

input               g_clk    ,
input               g_resetn ,



input  wire         s0_req   ,
output wire         s0_gnt   ,
input  wire         s0_wen   ,
input  wire [3:0]   s0_strb  ,
input  wire [31:0]  s0_wdata ,
input  wire [31:0]  s0_addr  ,

output wire         s0_recv  ,
input  wire         s0_ack   ,
output wire         s0_error ,
output wire [31:0]  s0_rdata ,



output wire         m0_req   ,
input  wire         m0_gnt   ,
output wire         m0_wen   ,
output wire [3:0]   m0_strb  ,
output wire [31:0]  m0_wdata ,
output wire [31:0]  m0_addr  ,

input  wire         m0_recv  ,
output wire         m0_ack   ,
input  wire         m0_error ,
input  wire [31:0]  m0_rdata ,



output wire         m1_req   ,
input  wire         m1_gnt   ,
output wire         m1_wen   ,
output wire [3:0]   m1_strb  ,
output wire [31:0]  m1_wdata ,
output wire [31:0]  m1_addr  ,

input  wire         m1_recv  ,
output wire         m1_ack   ,
input  wire         m1_error ,
input  wire [31:0]  m1_rdata

);

parameter M0_ADDR_MASK = 32'hFFFF8000;
parameter M0_ADDR_MATCH= 32'hC0000000;
parameter M0_ADDR_RANGE= 32'h00003FFF;




wire      m0_req_now    = m0_req    && m0_gnt;
wire      m0_rsp_now    = m0_recv   && m0_ack;

wire      m1_req_now    = m1_req    && m1_gnt;
wire      m1_rsp_now    = m1_recv   && m1_ack;

reg  [2:0] m0_reqs_out;
reg  [2:0] m1_reqs_out;

wire [2:0] n_m0_reqs_out = (m0_reqs_out + m0_req_now) - m0_rsp_now;
wire [2:0] n_m1_reqs_out = (m1_reqs_out + m1_req_now) - m1_rsp_now;

always @(posedge g_clk) begin
    if(!g_resetn) begin
        m0_reqs_out <= 0;
        m1_reqs_out <= 0;
    end else begin
        m0_reqs_out <= n_m0_reqs_out;
        m1_reqs_out <= n_m1_reqs_out;
    end
end




wire    addr_to_m0 = (m0_addr &  M0_ADDR_MASK) == M0_ADDR_MATCH &&
                     (m0_addr & ~M0_ADDR_MASK) == (m0_addr & M0_ADDR_RANGE);
wire    addr_to_m1 = !addr_to_m0;

wire    m0_req_en  = addr_to_m0 && m1_reqs_out == 0;
wire    m1_req_en  = addr_to_m1 && m0_reqs_out == 0;




assign m0_req   = s0_req && m0_req_en;

assign m0_wen   = s0_wen  ;
assign m0_strb  = s0_strb ;
assign m0_wdata = s0_wdata;
assign m0_addr  = s0_addr ;

assign m1_req   = s0_req && m1_req_en;

assign m1_wen   = s0_wen  ;
assign m1_strb  = s0_strb ;
assign m1_wdata = s0_wdata;
assign m1_addr  = s0_addr ;

assign s0_gnt   = m0_req && m0_gnt || m1_req && m1_gnt;







assign s0_recv  = m0_recv || m1_recv;
assign s0_error = m0_recv ? m0_error : m1_error;
assign s0_rdata = m0_recv ? m0_rdata : m1_rdata;

endmodule
module frv_bus_splitter (

input               g_clk    ,
input               g_resetn ,



input  wire         s0_req   ,
output wire         s0_gnt   ,
input  wire         s0_wen   ,
input  wire [3:0]   s0_strb  ,
input  wire [31:0]  s0_wdata ,
input  wire [31:0]  s0_addr  ,

output wire         s0_recv  ,
input  wire         s0_ack   ,
output wire         s0_error ,
output wire [31:0]  s0_rdata ,



output wire         m0_req   ,
input  wire         m0_gnt   ,
output wire         m0_wen   ,
output wire [3:0]   m0_strb  ,
output wire [31:0]  m0_wdata ,
output wire [31:0]  m0_addr  ,

input  wire         m0_recv  ,
output wire         m0_ack   ,
input  wire         m0_error ,
input  wire [31:0]  m0_rdata ,



output wire         m1_req   ,
input  wire         m1_gnt   ,
output wire         m1_wen   ,
output wire [3:0]   m1_strb  ,
output wire [31:0]  m1_wdata ,
output wire [31:0]  m1_addr  ,

input  wire         m1_recv  ,
output wire         m1_ack   ,
input  wire         m1_error ,
input  wire [31:0]  m1_rdata

);


parameter M0_ADDR_MASK = 32'hFFFF8000;
parameter M0_ADDR_MATCH= 32'hC0000000;
parameter M0_ADDR_RANGE= 32'h00003FFF;




wire      m0_req_now    = m0_req    && m0_gnt;
wire      m0_rsp_now    = m0_recv   && m0_ack;

wire      m1_req_now    = m1_req    && m1_gnt;
wire      m1_rsp_now    = m1_recv   && m1_ack;

reg  [2:0] m0_reqs_out;
reg  [2:0] m1_reqs_out;

wire [2:0] n_m0_reqs_out = (m0_reqs_out + m0_req_now) - m0_rsp_now;
wire [2:0] n_m1_reqs_out = (m1_reqs_out + m1_req_now) - m1_rsp_now;

always @(posedge g_clk) begin
    if(!g_resetn) begin
        m0_reqs_out <= 0;
        m1_reqs_out <= 0;
    end else begin
        m0_reqs_out <= n_m0_reqs_out;
        m1_reqs_out <= n_m1_reqs_out;
    end
end




wire    addr_to_m0 = (m0_addr &  M0_ADDR_MASK) == M0_ADDR_MATCH &&
                     (m0_addr & ~M0_ADDR_MASK) == (m0_addr & M0_ADDR_RANGE);
wire    addr_to_m1 = !addr_to_m0;

wire    m0_req_en  = addr_to_m0 && m1_reqs_out == 0;
wire    m1_req_en  = addr_to_m1 && m0_reqs_out == 0;




assign m0_req   = s0_req && m0_req_en;

assign m0_wen   = s0_wen  ;
assign m0_strb  = s0_strb ;
assign m0_wdata = s0_wdata;
assign m0_addr  = s0_addr ;

assign m1_req   = s0_req && m1_req_en;

assign m1_wen   = s0_wen  ;
assign m1_strb  = s0_strb ;
assign m1_wdata = s0_wdata;
assign m1_addr  = s0_addr ;

assign s0_gnt   = m0_req && m0_gnt || m1_req && m1_gnt;







assign s0_recv  = m0_recv || m1_recv;
assign s0_error = m0_recv ? m0_error : m1_error;
assign s0_rdata = m0_recv ? m0_rdata : m1_rdata;

endmodule