data/full_repos/permissive/106966316/bankregister_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/bankregister_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n            #50;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/bankregister_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n            #50;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/bankregister_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/bankregister_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/bankregister_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/bankregister_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Error: data/full_repos/permissive/106966316/bankregister_tb.v:35: Cannot find file containing module: \'bankregister\'\n    bankregister uut(\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/bankregister\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/bankregister.v\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/bankregister.sv\n             bankregister\n             bankregister.v\n             bankregister.sv\n             obj_dir/bankregister\n             obj_dir/bankregister.v\n             obj_dir/bankregister.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bankregister_tb;

    reg [5:0] RegLe1;
    reg [5:0] RegLe2;
    reg [5:0] RegEscr;
    reg EscrReg;
    reg clk;
    reg [31:0] datain;
    wire [31:0] data1;
    wire [31:0] data2;
    reg reset;
    
    bankregister uut(
    .RegLe1(RegLe1),
    .RegLe2(RegLe2),
    .RegEscr(RegEscr),
    .EscrReg(EscrReg),
    .clk(clk),
    .datain(datain),
    .data1(data1),
    .data2(data2),
    .reset(reset)
    );
    
    always 
        begin
            clk = 1'b1;
            #50;
            clk = 1'b0;
            #50;
        end          
        
initial begin

reset = 1'b1;
#100;
reset = 1'b0;

RegLe1  = 6'b000000;
RegLe2  = 6'b000001;
RegEscr = 6'b000000;
EscrReg = 1'b0;
datain  = 32'b00000000_00000000_00000000_00000000;

#100;

RegLe1  = 6'b000000;
RegLe2  = 6'b000001;
RegEscr = 6'b000010;
EscrReg = 1'b1;
datain  = 32'b00000000_00000000_00000000_10000101;
#100;

RegLe1  = 6'b000010;
RegLe2  = 6'b000001;
RegEscr = 6'b000000;
EscrReg = 1'b0;
datain  = 32'b00000000_00000000_00000000_00000001;

#100;

end
    
endmodule
module bankregister_tb;


    reg [5:0] RegLe1;
    reg [5:0] RegLe2;
    reg [5:0] RegEscr;
    reg EscrReg;
    reg clk;
    reg [31:0] datain;
    wire [31:0] data1;
    wire [31:0] data2;
    reg reset;
    
    bankregister uut(
    .RegLe1(RegLe1),
    .RegLe2(RegLe2),
    .RegEscr(RegEscr),
    .EscrReg(EscrReg),
    .clk(clk),
    .datain(datain),
    .data1(data1),
    .data2(data2),
    .reset(reset)
    );
    
    always 
        begin
            clk = 1'b1;
            #50;
            clk = 1'b0;
            #50;
        end          
        
initial begin

reset = 1'b1;
#100;
reset = 1'b0;

RegLe1  = 6'b000000;
RegLe2  = 6'b000001;
RegEscr = 6'b000000;
EscrReg = 1'b0;
datain  = 32'b00000000_00000000_00000000_00000000;

#100;

RegLe1  = 6'b000000;
RegLe2  = 6'b000001;
RegEscr = 6'b000010;
EscrReg = 1'b1;
datain  = 32'b00000000_00000000_00000000_10000101;
#100;

RegLe1  = 6'b000010;
RegLe2  = 6'b000001;
RegEscr = 6'b000000;
EscrReg = 1'b0;
datain  = 32'b00000000_00000000_00000000_00000001;

#100;

end
    
endmodule