data/full_repos/permissive/167962127/clock_5MHz_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167962127/clock_5MHz_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/167962127/clock_5MHz_tb.v:9: Cannot find file containing module: \'clock_5MHz\'\n  clock_5MHz UUT(\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/clock_5MHz\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/clock_5MHz.v\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/clock_5MHz.sv\n             clock_5MHz\n             clock_5MHz.v\n             clock_5MHz.sv\n             obj_dir/clock_5MHz\n             obj_dir/clock_5MHz.v\n             obj_dir/clock_5MHz.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock_5MHz_tb();

  reg clk50 = 0;
  wire clk5;

  clock_5MHz UUT(
    .i_clk50mhz(clk50),
    .o_clk5mhz(clk5)
  );

  always
  begin
    #10;
    clk50 = !clk50;
  end
endmodule
module clock_5MHz_tb();


  reg clk50 = 0;
  wire clk5;

  clock_5MHz UUT(
    .i_clk50mhz(clk50),
    .o_clk5mhz(clk5)
  );

  always
  begin
    #10;
    clk50 = !clk50;
  end
endmodule