data/full_repos/permissive/134629786/vga_example.v
1: b"%Error: data/full_repos/permissive/134629786/vga_example.v:37: Cannot find file containing module: 'IBUF'\n  IBUF clk_ibuf (.I(clk),.O(clk_in));\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/134629786,data/full_repos/permissive/134629786/IBUF\n             data/full_repos/permissive/134629786,data/full_repos/permissive/134629786/IBUF.v\n             data/full_repos/permissive/134629786,data/full_repos/permissive/134629786/IBUF.sv\n             IBUF\n             IBUF.v\n             IBUF.sv\n             obj_dir/IBUF\n             obj_dir/IBUF.v\n             obj_dir/IBUF.sv\n%Error: data/full_repos/permissive/134629786/vga_example.v:39: Cannot find file containing module: 'MMCME2_BASE'\n  MMCME2_BASE #(\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/134629786/vga_example.v:64: Cannot find file containing module: 'BUFH'\n  BUFH clk_out_bufh (.I(clk_out),.O(clk_ss));\n  ^~~~\n%Error: data/full_repos/permissive/134629786/vga_example.v:67: Cannot find file containing module: 'BUFGCE'\n  BUFGCE clk_out_bufgce (.I(clk_out),.CE(safe_start[7]),.O(pclk));\n  ^~~~~~\n%Error: data/full_repos/permissive/134629786/vga_example.v:72: Cannot find file containing module: 'ODDR'\n  ODDR pclk_oddr (\n  ^~~~\n%Error: data/full_repos/permissive/134629786/vga_example.v:89: Cannot find file containing module: 'vga_timing'\n  vga_timing my_timing (\n  ^~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module vga_example (
  input wire clk,
  output reg vs,
  output reg hs,
  output reg [3:0] r,
  output reg [3:0] g,
  output reg [3:0] b,
  output wire pclk_mirror
  );





  wire clk_in;
  wire locked;
  wire clk_fb;
  wire clk_ss;
  wire clk_out;
  wire pclk;
  (* KEEP = "TRUE" *) 
  (* ASYNC_REG = "TRUE" *)
  reg [7:0] safe_start = 0;

  IBUF clk_ibuf (.I(clk),.O(clk_in));

  MMCME2_BASE #(
    .CLKIN1_PERIOD(10.000),
    .CLKFBOUT_MULT_F(10.000),
    .CLKOUT0_DIVIDE_F(25.000))
  clk_in_mmcme2 (
    .CLKIN1(clk_in),
    .CLKOUT0(clk_out),
    .CLKOUT0B(),
    .CLKOUT1(),
    .CLKOUT1B(),
    .CLKOUT2(),
    .CLKOUT2B(),
    .CLKOUT3(),
    .CLKOUT3B(),
    .CLKOUT4(),
    .CLKOUT5(),
    .CLKOUT6(),
    .CLKFBOUT(clkfb),
    .CLKFBOUTB(),
    .CLKFBIN(clkfb),
    .LOCKED(locked),
    .PWRDWN(1'b0),
    .RST(1'b0)
  );

  BUFH clk_out_bufh (.I(clk_out),.O(clk_ss));
  always @(posedge clk_ss) safe_start<= {safe_start[6:0],locked};

  BUFGCE clk_out_bufgce (.I(clk_out),.CE(safe_start[7]),.O(pclk));




  ODDR pclk_oddr (
    .Q(pclk_mirror),
    .C(pclk),
    .CE(1'b1),
    .D1(1'b1),
    .D2(1'b0),
    .R(1'b0),
    .S(1'b0)
  );




  wire [10:0] vcount, hcount;
  wire vsync, hsync;
  wire vblnk, hblnk;

  vga_timing my_timing (
    .vcount(vcount),
    .vsync(vsync),
    .vblnk(vblnk),
    .hcount(hcount),
    .hsync(hsync),
    .hblnk(hblnk),
    .pclk(pclk)
  );


  
  always @(posedge pclk)
  begin

    hs <= hsync;
    vs <= vsync;

    if (vblnk || hblnk) {r,g,b} <= 12'h0_0_0; 
    else
    begin

      if (vcount == 0) {r,g,b} <= 12'hf_f_0;

      else if (vcount == 599) {r,g,b} <= 12'hf_0_0;

      else if (hcount == 0) {r,g,b} <= 12'h0_f_0;

      else if (hcount == 799) {r,g,b} <= 12'h0_0_f;



      else if ( (hcount >= 100) && (hcount <= 350) && (vcount == 80) ) {r,g,b} <= 12'hf_f_f; 
      else if ( (hcount >= 100) && (hcount <= 175) && (vcount == 500) ) {r,g,b} <= 12'hf_f_f;
      else if ( (hcount == 175) && (vcount >= 80) && (vcount <= 500) ) {r,g,b} <= 12'hf_f_f;
      

      else if ( (hcount >= 450) && (hcount <= 700) && (vcount == 80) ) {r,g,b} <= 12'hf_f_f; 
      else if ( (hcount >= 450) && (hcount <= 700) && (vcount == 200) ) {r,g,b} <= 12'hf_f_f;
      else if ( (hcount == 450) && (vcount >= 80) && (vcount <= 500) ) {r,g,b} <= 12'hf_f_f;
      else if ( (hcount == 700) && (vcount >= 80) && (vcount <= 200) ) {r,g,b} <= 12'hf_f_f;
      
      else {r,g,b} <= 12'h8_8_8;    
    end
  end

endmodule
module vga_example (
  input wire clk,
  output reg vs,
  output reg hs,
  output reg [3:0] r,
  output reg [3:0] g,
  output reg [3:0] b,
  output wire pclk_mirror
  );






  wire clk_in;
  wire locked;
  wire clk_fb;
  wire clk_ss;
  wire clk_out;
  wire pclk;
  (* KEEP = "TRUE" *) 
  (* ASYNC_REG = "TRUE" *)
  reg [7:0] safe_start = 0;

  IBUF clk_ibuf (.I(clk),.O(clk_in));

  MMCME2_BASE #(
    .CLKIN1_PERIOD(10.000),
    .CLKFBOUT_MULT_F(10.000),
    .CLKOUT0_DIVIDE_F(25.000))
  clk_in_mmcme2 (
    .CLKIN1(clk_in),
    .CLKOUT0(clk_out),
    .CLKOUT0B(),
    .CLKOUT1(),
    .CLKOUT1B(),
    .CLKOUT2(),
    .CLKOUT2B(),
    .CLKOUT3(),
    .CLKOUT3B(),
    .CLKOUT4(),
    .CLKOUT5(),
    .CLKOUT6(),
    .CLKFBOUT(clkfb),
    .CLKFBOUTB(),
    .CLKFBIN(clkfb),
    .LOCKED(locked),
    .PWRDWN(1'b0),
    .RST(1'b0)
  );

  BUFH clk_out_bufh (.I(clk_out),.O(clk_ss));
  always @(posedge clk_ss) safe_start<= {safe_start[6:0],locked};

  BUFGCE clk_out_bufgce (.I(clk_out),.CE(safe_start[7]),.O(pclk));




  ODDR pclk_oddr (
    .Q(pclk_mirror),
    .C(pclk),
    .CE(1'b1),
    .D1(1'b1),
    .D2(1'b0),
    .R(1'b0),
    .S(1'b0)
  );




  wire [10:0] vcount, hcount;
  wire vsync, hsync;
  wire vblnk, hblnk;

  vga_timing my_timing (
    .vcount(vcount),
    .vsync(vsync),
    .vblnk(vblnk),
    .hcount(hcount),
    .hsync(hsync),
    .hblnk(hblnk),
    .pclk(pclk)
  );


  
  always @(posedge pclk)
  begin

    hs <= hsync;
    vs <= vsync;

    if (vblnk || hblnk) {r,g,b} <= 12'h0_0_0; 
    else
    begin

      if (vcount == 0) {r,g,b} <= 12'hf_f_0;

      else if (vcount == 599) {r,g,b} <= 12'hf_0_0;

      else if (hcount == 0) {r,g,b} <= 12'h0_f_0;

      else if (hcount == 799) {r,g,b} <= 12'h0_0_f;



      else if ( (hcount >= 100) && (hcount <= 350) && (vcount == 80) ) {r,g,b} <= 12'hf_f_f; 
      else if ( (hcount >= 100) && (hcount <= 175) && (vcount == 500) ) {r,g,b} <= 12'hf_f_f;
      else if ( (hcount == 175) && (vcount >= 80) && (vcount <= 500) ) {r,g,b} <= 12'hf_f_f;
      

      else if ( (hcount >= 450) && (hcount <= 700) && (vcount == 80) ) {r,g,b} <= 12'hf_f_f; 
      else if ( (hcount >= 450) && (hcount <= 700) && (vcount == 200) ) {r,g,b} <= 12'hf_f_f;
      else if ( (hcount == 450) && (vcount >= 80) && (vcount <= 500) ) {r,g,b} <= 12'hf_f_f;
      else if ( (hcount == 700) && (vcount >= 80) && (vcount <= 200) ) {r,g,b} <= 12'hf_f_f;
      
      else {r,g,b} <= 12'h8_8_8;    
    end
  end

endmodule