data/full_repos/permissive/194847941/demo/12_game/sources/rtl/mcu/timer.v
data/verilator_xmls/71cf77d7-fd2a-4e2f-a5cc-b299a0228bca.xml
module timer
(
    input   wire		clk,
    

    input   wire		timer_wen,
    input   wire [23:0]	timer_wdata,
    
    output  reg			timer_state
);

reg [23:0] cnt;


always@(posedge clk)
begin
    if(timer_wen)
        cnt <= timer_wdata;
    else if(cnt != 0)
        cnt <= cnt - 1;
end


always@(posedge clk)
begin
    timer_state <= (cnt == 0);
end

endmodule
module timer
(
    input   wire		clk,
    

    input   wire		timer_wen,
    input   wire [23:0]	timer_wdata,
    
    output  reg			timer_state
);


reg [23:0] cnt;


always@(posedge clk)
begin
    if(timer_wen)
        cnt <= timer_wdata;
    else if(cnt != 0)
        cnt <= cnt - 1;
end


always@(posedge clk)
begin
    timer_state <= (cnt == 0);
end

endmodule