data/full_repos/permissive/104269513/mem_mod_master2_32bit - FinalFSM - final project_combined.v
 line:310: before: ")"
1: b'%Error: Invalid Option: -\n'
module mem_mod_mast_tb();



reg [31:0] Data_In_hi,Data_In_lo;

reg [8:0] LD_A;
reg [17:0] DUMMY;
reg [31:0] reg_addr_data_out;

reg HW_RDY_in, I_D, R_W;
reg [1:0] MOD;


reg [31:0] Data_out_hi_DM, Data_out_lo_DM, Data_out_IM;

wire [31:0] reg_addr_data_in;
reg [12:0] dummy;
reg HW_RDY_out;
reg [8:0] A_IM, A_DM;	   


reg clk, rst;




wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;


wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;


reg out_rdy, in_wr;
wire in_rdy, out_wr;
	

integer count,fq;
integer i, counter_restart;


reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;


reg[4:0] reg_wa;




reg reg_req_out;
reg reg_ack_out;
reg reg_rd_wr_L_out;
reg [`UDP_REG_SRC_WIDTH-1:0] reg_src_out;
reg[`UDP_REG_ADDR_WIDTH-1:0] addr_out;


	
wire reg_req_in;
wire reg_ack_in;
wire reg_rd_wr_L_in;
wire[`UDP_REG_SRC_WIDTH-1:0] reg_src_in;
wire[`UDP_REG_ADDR_WIDTH-1:0] addr_in;		
	
	
mem_mod_mast UUT (
					.in_data(fifo_data_in),
					.in_ctrl(fifo_ctrl_in),
					.out_data(fifo_data_out),
					.out_ctrl(fifo_ctrl_out),


					.out_rdy(out_rdy),
					.in_wr(in_wr),
					.in_rdy(in_rdy),
					.out_wr(out_wr),








					.reg_req_in(reg_req_out),
					.reg_ack_in(reg_ack_out),
					.reg_rd_wr_L_in(reg_rd_wr_L_out),
					.reg_addr_in(addr_out),

					.reg_data_in(reg_addr_data_out),
					.reg_src_in(reg_src_out),

					.reg_req_out(reg_req_in),
					.reg_ack_out(reg_ack_in),
					.reg_rd_wr_L_out(reg_rd_wr_L_in),
					.reg_addr_out(addr_in),

					.reg_data_out(reg_addr_data_in),						 
					.reg_src_out(reg_src_in),


					.clk(clk),
					.rst(rst)
				);
				
assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];

regfile op_reg(	
				.clk(clk),
				.rst(rst),
				.r0addr(),
				.r1addr(),
				.waddr(reg_wa),
				.wdata(fifo_data_out),
				.wena(out_wr),
				.r0data(),
				.r1data()
			   );
			   
initial begin
	
	clk = 0;
	forever	#10	clk = ~clk;
end
	
initial begin
	rst = 1;
	#30	rst = 0;

end
	
initial begin

	LD_A = 'h0001;


	Data_In_hi = 'h BAAB;
	Data_In_lo = 'h ABBA;
	reg_addr_data_out = 'h BEEF;
	DUMMY = 'h 0;
	dummy = 'h 0; 
	count = 0;

	MOD = 'h0;
	HW_RDY_in = 1;
	I_D = 1;
	R_W = 0;


	out_rdy = 1;
	in_wr = 0;
	reg_wa = 0;
	reg_ra = 0;
	counter_restart = 25;
	

	$readmemh ("ip_reg_init_var_pckt.txt",ip_reg);
	
	fq = $fopen ("mem_mod_mast_tb_op.txt", "w");
	if (!fq) $display ("Failed genrating output file");
end				

always @ (posedge clk)
	begin
		reg_rd_wr_L_out <= 1;
		reg_req_out <= 0;
		count <= count + 1;
	
		if (count < 2)
			begin
				reg_rd_wr_L_out <= 0;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h0	;
				reg_addr_data_out <= Data_In_lo;
			end	

		else if (count < 3)
			begin
				reg_rd_wr_L_out <= 0;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h1;
				reg_addr_data_out <= Data_In_hi;
			end	
	
		else if (count < 4)
			begin
				reg_rd_wr_L_out <= 0;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h2;
				reg_addr_data_out <= {MOD[1],HW_RDY_in,I_D,R_W,MOD[0],DUMMY,LD_A};
			end
		
		else if (count < 8)
			begin
				reg_rd_wr_L_out <= 1;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h6;
			end
		else if (count < 9)
			begin
				reg_rd_wr_L_out <= 1;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h5;
			end
		else if (count < 10)
			begin
				reg_rd_wr_L_out <= 1;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h4;
			end
		else if (count < 11)
			begin
				reg_rd_wr_L_out <= 1;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h3;
			end

























	








































		

		




























































			
			







































		


			
		

		else if (count == 50 )
			begin

				out_rdy <= 0;
				in_wr <= 0;
			end
		else if (count == 100)
				out_rdy <= 1;


		if (addr_in == 'h6)	{dummy,HW_RDY_out,A_IM,A_DM} <= reg_addr_data_in;
		if (addr_in == 'h5)	Data_out_IM <= reg_addr_data_in;
		if (addr_in == 'h4)	Data_out_hi_DM <= reg_addr_data_in;
		if (addr_in == 'h3)	Data_out_lo_DM <= reg_addr_data_in;
		
		
		

		if (count > 13)
		begin
			if (in_rdy && fifo_ctrl_in != 'hab)
				begin
					in_wr <= 1;
					if (in_wr)
						reg_ra <= reg_ra + 1;
				end
			else 
				begin
					reg_ra <= reg_ra;
					in_wr <= 0;
				end
		end
		


		





		





							
		
		
		
		
		

		if(out_wr)
			reg_wa <= reg_wa +1;
		else 
			reg_wa <= reg_wa;
			
		

		if (reg_req_in & reg_ack_in & reg_src_in == 0)
			begin
				$fdisplay (fq,"%d Success!! %h %h\t\t %h_%h",count,A_IM,A_DM, Data_out_hi_DM, Data_out_lo_DM);
			end

		else if (reg_req_in & !reg_ack_in & reg_src_in == 0)
			begin
				$fdisplay (fq,"Failed:( Ja mar ja");
			end
		else if (!reg_req_in)
			begin
				$fdisplay (fq,"Ab to Doob ke mar ja");
			end
		
		if (count == 40)	$fclose(fq);

	end


endmodule
module mem_mod_mast_tb();




reg [31:0] Data_In_hi,Data_In_lo;

reg [8:0] LD_A;
reg [17:0] DUMMY;
reg [31:0] reg_addr_data_out;

reg HW_RDY_in, I_D, R_W;
reg [1:0] MOD;


reg [31:0] Data_out_hi_DM, Data_out_lo_DM, Data_out_IM;

wire [31:0] reg_addr_data_in;
reg [12:0] dummy;
reg HW_RDY_out;
reg [8:0] A_IM, A_DM;	   


reg clk, rst;




wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;


wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;


reg out_rdy, in_wr;
wire in_rdy, out_wr;
	

integer count,fq;
integer i, counter_restart;


reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;


reg[4:0] reg_wa;




reg reg_req_out;
reg reg_ack_out;
reg reg_rd_wr_L_out;
reg [`UDP_REG_SRC_WIDTH-1:0] reg_src_out;
reg[`UDP_REG_ADDR_WIDTH-1:0] addr_out;


	
wire reg_req_in;
wire reg_ack_in;
wire reg_rd_wr_L_in;
wire[`UDP_REG_SRC_WIDTH-1:0] reg_src_in;
wire[`UDP_REG_ADDR_WIDTH-1:0] addr_in;		
	
	
mem_mod_mast UUT (
					.in_data(fifo_data_in),
					.in_ctrl(fifo_ctrl_in),
					.out_data(fifo_data_out),
					.out_ctrl(fifo_ctrl_out),


					.out_rdy(out_rdy),
					.in_wr(in_wr),
					.in_rdy(in_rdy),
					.out_wr(out_wr),








					.reg_req_in(reg_req_out),
					.reg_ack_in(reg_ack_out),
					.reg_rd_wr_L_in(reg_rd_wr_L_out),
					.reg_addr_in(addr_out),

					.reg_data_in(reg_addr_data_out),
					.reg_src_in(reg_src_out),

					.reg_req_out(reg_req_in),
					.reg_ack_out(reg_ack_in),
					.reg_rd_wr_L_out(reg_rd_wr_L_in),
					.reg_addr_out(addr_in),

					.reg_data_out(reg_addr_data_in),						 
					.reg_src_out(reg_src_in),


					.clk(clk),
					.rst(rst)
				);
				
assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];

regfile op_reg(	
				.clk(clk),
				.rst(rst),
				.r0addr(),
				.r1addr(),
				.waddr(reg_wa),
				.wdata(fifo_data_out),
				.wena(out_wr),
				.r0data(),
				.r1data()
			   );
			   
initial begin
	
	clk = 0;
	forever	#10	clk = ~clk;
end
	
initial begin
	rst = 1;
	#30	rst = 0;

end
	
initial begin

	LD_A = 'h0001;


	Data_In_hi = 'h BAAB;
	Data_In_lo = 'h ABBA;
	reg_addr_data_out = 'h BEEF;
	DUMMY = 'h 0;
	dummy = 'h 0; 
	count = 0;

	MOD = 'h0;
	HW_RDY_in = 1;
	I_D = 1;
	R_W = 0;


	out_rdy = 1;
	in_wr = 0;
	reg_wa = 0;
	reg_ra = 0;
	counter_restart = 25;
	

	$readmemh ("ip_reg_init_var_pckt.txt",ip_reg);
	
	fq = $fopen ("mem_mod_mast_tb_op.txt", "w");
	if (!fq) $display ("Failed genrating output file");
end				

always @ (posedge clk)
	begin
		reg_rd_wr_L_out <= 1;
		reg_req_out <= 0;
		count <= count + 1;
	
		if (count < 2)
			begin
				reg_rd_wr_L_out <= 0;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h0	;
				reg_addr_data_out <= Data_In_lo;
			end	

		else if (count < 3)
			begin
				reg_rd_wr_L_out <= 0;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h1;
				reg_addr_data_out <= Data_In_hi;
			end	
	
		else if (count < 4)
			begin
				reg_rd_wr_L_out <= 0;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h2;
				reg_addr_data_out <= {MOD[1],HW_RDY_in,I_D,R_W,MOD[0],DUMMY,LD_A};
			end
		
		else if (count < 8)
			begin
				reg_rd_wr_L_out <= 1;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h6;
			end
		else if (count < 9)
			begin
				reg_rd_wr_L_out <= 1;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h5;
			end
		else if (count < 10)
			begin
				reg_rd_wr_L_out <= 1;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h4;
			end
		else if (count < 11)
			begin
				reg_rd_wr_L_out <= 1;
				reg_req_out <= 1;
				reg_ack_out <= 0;
				reg_src_out <= 2'b00;
				addr_out <= 'h3;
			end

























	








































		

		




























































			
			







































		


			
		

		else if (count == 50 )
			begin

				out_rdy <= 0;
				in_wr <= 0;
			end
		else if (count == 100)
				out_rdy <= 1;


		if (addr_in == 'h6)	{dummy,HW_RDY_out,A_IM,A_DM} <= reg_addr_data_in;
		if (addr_in == 'h5)	Data_out_IM <= reg_addr_data_in;
		if (addr_in == 'h4)	Data_out_hi_DM <= reg_addr_data_in;
		if (addr_in == 'h3)	Data_out_lo_DM <= reg_addr_data_in;
		
		
		

		if (count > 13)
		begin
			if (in_rdy && fifo_ctrl_in != 'hab)
				begin
					in_wr <= 1;
					if (in_wr)
						reg_ra <= reg_ra + 1;
				end
			else 
				begin
					reg_ra <= reg_ra;
					in_wr <= 0;
				end
		end
		


		





		





							
		
		
		
		
		

		if(out_wr)
			reg_wa <= reg_wa +1;
		else 
			reg_wa <= reg_wa;
			
		

		if (reg_req_in & reg_ack_in & reg_src_in == 0)
			begin
				$fdisplay (fq,"%d Success!! %h %h\t\t %h_%h",count,A_IM,A_DM, Data_out_hi_DM, Data_out_lo_DM);
			end

		else if (reg_req_in & !reg_ack_in & reg_src_in == 0)
			begin
				$fdisplay (fq,"Failed:( Ja mar ja");
			end
		else if (!reg_req_in)
			begin
				$fdisplay (fq,"Ab to Doob ke mar ja");
			end
		
		if (count == 40)	$fclose(fq);

	end


endmodule