data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/program_counter.v
data/verilator_xmls/53330b79-6fa6-471b-b8fa-e5e59d0f0aad.xml
module program_counter (

	input         rst_n,
	input         clk,


	input         increment,


	input         write_enable,
	input [31:0]  write_value,


	input         read_enable,
	output [31:0] read_value
	);

	
	reg [19:0]    pc_reg;

	assign read_value = read_enable ? {12'h000,pc_reg} : 32'hzzzzz;

	always @(posedge clk) begin
        if (!rst_n) begin


            pc_reg <= 20'h80000;
            


        end   
        else if (increment) begin
            pc_reg <= pc_reg + 1;
        end
        else if (write_enable) begin 
            pc_reg <= write_value[19:0];
        end
    end

endmodule
module program_counter (

	input         rst_n,
	input         clk,


	input         increment,


	input         write_enable,
	input [31:0]  write_value,


	input         read_enable,
	output [31:0] read_value
	);


	
	reg [19:0]    pc_reg;

	assign read_value = read_enable ? {12'h000,pc_reg} : 32'hzzzzz;

	always @(posedge clk) begin
        if (!rst_n) begin


            pc_reg <= 20'h80000;
            


        end   
        else if (increment) begin
            pc_reg <= pc_reg + 1;
        end
        else if (write_enable) begin 
            pc_reg <= write_value[19:0];
        end
    end

endmodule