data/full_repos/permissive/114553631/test/test_fwdA.v
 line:80: before: "$"
1: b'%Error: data/full_repos/permissive/114553631/test/test_fwdA.v:6: Cannot find include file: ../src/fwdA.v\n`include "../src/fwdA.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/fwdA.v\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/fwdA.v.v\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/fwdA.v.sv\n             ../src/fwdA.v\n             ../src/fwdA.v.v\n             ../src/fwdA.v.sv\n             obj_dir/../src/fwdA.v\n             obj_dir/../src/fwdA.v.v\n             obj_dir/../src/fwdA.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:27: Unsupported: Ignoring delay on this delayed statement.\n    initial #stop_time $finish;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/114553631/test/test_fwdA.v:30: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("./logs/test_fwdA.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/114553631/test/test_fwdA.v:31: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars();\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/114553631/test/test_fwdA.v:35: Define or directive not defined: \'`RNONE\'\n        d_srcA = `RNONE;\n                 ^~~~~~\n%Error: data/full_repos/permissive/114553631/test/test_fwdA.v:35: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        d_srcA = `RNONE;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/114553631/test/test_fwdA.v:69: Unsupported or unknown PLI call: $monitor\n        $monitor("time = ", $time, " valA=%d, srcA=%b", d_valA, d_srcA);\n        ^~~~~~~~\n%Error: Exiting due to 6 error(s), 9 warning(s)\n'
module test_fwdA;
    reg [4:0] d_srcA;
    reg [4:0] E_dstE;
    reg [4:0] M_dstM;
    reg [4:0] M_dstE;
    reg [4:0] W_dstM;
    reg [4:0] W_dstE;
    reg [31:0] d_rvalA;
    reg [31:0] e_valE;
    reg [31:0] m_valM;
    reg [31:0] M_valE;
    reg [31:0] W_valM;
    reg [31:0] W_valE;
    wire [31:0] d_valA;

    parameter stop_time = 80;

    fwdA FWDA(d_valA, d_srcA, E_dstE, M_dstM, M_dstE, W_dstM, W_dstE, d_rvalA, e_valE, m_valM, M_valE, W_valM, W_valE);

    initial #stop_time $finish;

    initial begin
		$dumpfile("./logs/test_fwdA.vcd");
		$dumpvars();
        d_srcA = 0;
        d_rvalA = 0;
        #10;
        d_srcA = `RNONE;
        d_rvalA = 1;
        #10;
        d_srcA = 5'b10101;
        E_dstE = 5'b10101;
        e_valE = 2;
        #10;
        d_srcA = 5'b10110;
        M_dstE = 5'b10110;
        M_valE = 3;
        #10;
        d_srcA = 5'b10111;
        M_dstM = 5'b10111;
        m_valM = 4;
        #10;
        d_srcA = 5'b11000;
        W_dstE = 5'b11000;
        W_valE = 5;
        #10;
        d_srcA = 5'b11001;
        W_dstM = 5'b11001;
        W_valM = 6;
        #10;
        d_srcA = 5'b11010;
        E_dstE = 5'b00001;
        M_dstE = 5'b00010;
        M_dstM = 5'b00011;
        W_dstE = 5'b00100;
        W_dstM = 5'b00101;
        d_rvalA = 7;
        #10;
    end

    initial begin
        $monitor("time = ", $time, " valA=%d, srcA=%b", d_valA, d_srcA);
    end
endmodule
module test_fwdA;

    reg [4:0] d_srcA;
    reg [4:0] E_dstE;
    reg [4:0] M_dstM;
    reg [4:0] M_dstE;
    reg [4:0] W_dstM;
    reg [4:0] W_dstE;
    reg [31:0] d_rvalA;
    reg [31:0] e_valE;
    reg [31:0] m_valM;
    reg [31:0] M_valE;
    reg [31:0] W_valM;
    reg [31:0] W_valE;
    wire [31:0] d_valA;

    parameter stop_time = 80;

    fwdA FWDA(d_valA, d_srcA, E_dstE, M_dstM, M_dstE, W_dstM, W_dstE, d_rvalA, e_valE, m_valM, M_valE, W_valM, W_valE);

    initial #stop_time $finish;

    initial begin
		$dumpfile("./logs/test_fwdA.vcd");
		$dumpvars();
        d_srcA = 0;
        d_rvalA = 0;
        #10;
        d_srcA = `RNONE;
        d_rvalA = 1;
        #10;
        d_srcA = 5'b10101;
        E_dstE = 5'b10101;
        e_valE = 2;
        #10;
        d_srcA = 5'b10110;
        M_dstE = 5'b10110;
        M_valE = 3;
        #10;
        d_srcA = 5'b10111;
        M_dstM = 5'b10111;
        m_valM = 4;
        #10;
        d_srcA = 5'b11000;
        W_dstE = 5'b11000;
        W_valE = 5;
        #10;
        d_srcA = 5'b11001;
        W_dstM = 5'b11001;
        W_valM = 6;
        #10;
        d_srcA = 5'b11010;
        E_dstE = 5'b00001;
        M_dstE = 5'b00010;
        M_dstM = 5'b00011;
        W_dstE = 5'b00100;
        W_dstM = 5'b00101;
        d_rvalA = 7;
        #10;
    end

    initial begin
        $monitor("time = ", $time, " valA=%d, srcA=%b", d_valA, d_srcA);
    end
endmodule