data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v
None: at end of input
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:10: Define or directive not defined: \'`MemAddrWidth\'\n        input wire[`MemAddrWidth-1:0] if_pc,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:11: Define or directive not defined: \'`InstWidth\'\n        input wire[`InstWidth-1:0] if_inst,\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:18: Define or directive not defined: \'`MemAddrWidth\'\n        output reg[`MemAddrWidth-1:0] id_pc,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:19: Define or directive not defined: \'`InstWidth\'\n        output reg[`InstWidth-1:0] id_inst\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:24: Define or directive not defined: \'`RstEnable\'\n        if (rst == `RstEnable)\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (rst == `RstEnable)\n                             ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:26: Define or directive not defined: \'`ZeroWord\'\n            id_pc <= `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:27: Define or directive not defined: \'`ZeroWord\'\n            id_inst <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            id_inst <= `ZeroWord;\n                                ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:29: Define or directive not defined: \'`JumpUncdt\'\n   if (idex_jump_type == `JumpUncdt \n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:30: Define or directive not defined: \'`JumpBranch\'\n    || (idex_jump_type == `JumpBranch && ex_jump)) begin\n                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:31: Define or directive not defined: \'`ZeroWord\'\n    id_pc <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:32: Define or directive not defined: \'`NopInst\'\n    id_inst <= `NopInst;\n               ^~~~~~~~\n%Error: Cannot continue\n'
module if_id(
        input wire clk,
        input wire rst,
		input wire[5:0] stall,


        input wire[`MemAddrWidth-1:0] if_pc,
        input wire[`InstWidth-1:0] if_inst,


		input wire ex_jump,
		input wire[1:0] idex_jump_type,


        output reg[`MemAddrWidth-1:0] id_pc,
        output reg[`InstWidth-1:0] id_inst
    );
    
    always @ (posedge clk)
    begin
        if (rst == `RstEnable)
        begin
            id_pc <= `ZeroWord;
            id_inst <= `ZeroWord;
		end else if (!stall[1]) begin
			if (idex_jump_type == `JumpUncdt 
				|| (idex_jump_type == `JumpBranch && ex_jump)) begin
				id_pc <= `ZeroWord;
				id_inst <= `NopInst;
			end else begin
				id_pc <= if_pc;
				id_inst <= if_inst;
			end
        end
    end
    
endmodule
module if_id(
        input wire clk,
        input wire rst,
		input wire[5:0] stall,


        input wire[`MemAddrWidth-1:0] if_pc,
        input wire[`InstWidth-1:0] if_inst,


		input wire ex_jump,
		input wire[1:0] idex_jump_type,


        output reg[`MemAddrWidth-1:0] id_pc,
        output reg[`InstWidth-1:0] id_inst
    );

    
    always @ (posedge clk)
    begin
        if (rst == `RstEnable)
        begin
            id_pc <= `ZeroWord;
            id_inst <= `ZeroWord;
		end else if (!stall[1]) begin
			if (idex_jump_type == `JumpUncdt 
				|| (idex_jump_type == `JumpBranch && ex_jump)) begin
				id_pc <= `ZeroWord;
				id_inst <= `NopInst;
			end else begin
				id_pc <= if_pc;
				id_inst <= if_inst;
			end
        end
    end
    
endmodule