data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode/register_memory.v
 line:2: before: "-"
1: b'%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode/register_memory.v:2: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode,data/full_repos/permissive/180413071/constants.vh\n             data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode,data/full_repos/permissive/180413071/constants.vh.v\n             data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode,data/full_repos/permissive/180413071/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode/register_memory.v:3: Cannot find include file: files.vh\n`include "files.vh" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode/register_memory.v:6: Define or directive not defined: \'`REGISTER_FILE\'\nmodule register_memory #(parameter PATH=`REGISTER_FILE)(\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode/register_memory.v:6: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule register_memory #(parameter PATH=`REGISTER_FILE)(\n                                                      ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode/register_memory.v:14: Define or directive not defined: \'`WORD\'\n    input      [`WORD-1:0] write_data,\n                ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode/register_memory.v:15: Define or directive not defined: \'`WORD\'\n    output reg [`WORD-1:0] read_data1,\n                ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode/register_memory.v:16: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`WORD-1:0] read_data2\n    ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode/register_memory.v:16: Define or directive not defined: \'`WORD\'\n    output reg [`WORD-1:0] read_data2\n                ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode/register_memory.v:17: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode/register_memory.v:19: Define or directive not defined: \'`WORD\'\n    reg [`WORD-1:0] register_mem [31:0];\n         ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/decode/register_memory.v:21: syntax error, unexpected initial\n    initial \n    ^~~~~~~\n%Error: Exiting due to 11 error(s)\n'
module register_memory #(parameter PATH=`REGISTER_FILE)(
    input                  read_clk,
    input                  write_clk,
    input                  reset,
    input                  reg_write,
    input      [4:0]       read_reg1,
    input      [4:0]       read_reg2,
    input      [4:0]       write_reg,
    input      [`WORD-1:0] write_data,
    output reg [`WORD-1:0] read_data1,
    output reg [`WORD-1:0] read_data2
);
    
    reg [`WORD-1:0] register_mem [31:0];
    
    initial 
        $readmemb(PATH, register_mem);
    
    always @(posedge read_clk, reset) 
        if (!reset) begin
            read_data1 <= register_mem[read_reg1];
            read_data2 <= register_mem[read_reg2];
        end
    
    always @(posedge write_clk, reset) 
        if (!reset && reg_write) 
            register_mem[write_reg] <= write_data;
    
endmodule
module register_memory #(parameter PATH=`REGISTER_FILE)(
    input                  read_clk,
    input                  write_clk,
    input                  reset,
    input                  reg_write,
    input      [4:0]       read_reg1,
    input      [4:0]       read_reg2,
    input      [4:0]       write_reg,
    input      [`WORD-1:0] write_data,
    output reg [`WORD-1:0] read_data1,
    output reg [`WORD-1:0] read_data2
);

    
    reg [`WORD-1:0] register_mem [31:0];
    
    initial 
        $readmemb(PATH, register_mem);
    
    always @(posedge read_clk, reset) 
        if (!reset) begin
            read_data1 <= register_mem[read_reg1];
            read_data2 <= register_mem[read_reg2];
        end
    
    always @(posedge write_clk, reset) 
        if (!reset && reg_write) 
            register_mem[write_reg] <= write_data;
    
endmodule