data/full_repos/permissive/143278/contrib/add32.v
 line:14: before: "assign"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/add32.v:31: Unsupported: Ignoring delay on this delayed statement.\n    always #1 CLOCK = ~ CLOCK;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/contrib/add32.v:35: Unsupported or unknown PLI call: $monitor\n      $monitor($time,, " CLOCK=%d, A=%x, B=%x, C_IN=%d -- SUM=%x, C_OUT=%d",\n      ^~~~~~~~\n%Error: data/full_repos/permissive/143278/contrib/add32.v:35: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      $monitor($time,, " CLOCK=%d, A=%x, B=%x, C_IN=%d -- SUM=%x, C_OUT=%d",\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/add32.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #20 $finish;\n      ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

    reg CLOCK;
    reg [31:0] A, B;
    reg C_IN;
    reg [31:0] SUM;
    wire C_OUT;


    add32 myAdder(SUM, C_OUT, CLOCK, A, B, C_OUT);

    always #1 CLOCK = ~ CLOCK;

    initial
    begin
      $monitor($time,, " CLOCK=%d, A=%x, B=%x, C_IN=%d -- SUM=%x, C_OUT=%d",
CLOCK, A, B, C_IN, SUM, C_OUT);
    end

    initial
    begin
      CLOCK = 0;
      A = 32'h00000001;
      B = 32'h00000002;
      C_IN = 1'b0;
      #20 $finish;
    end

endmodule
module main;


    reg CLOCK;
    reg [31:0] A, B;
    reg C_IN;
    reg [31:0] SUM;
    wire C_OUT;


    add32 myAdder(SUM, C_OUT, CLOCK, A, B, C_OUT);

    always #1 CLOCK = ~ CLOCK;

    initial
    begin
      $monitor($time,, " CLOCK=%d, A=%x, B=%x, C_IN=%d -- SUM=%x, C_OUT=%d",
CLOCK, A, B, C_IN, SUM, C_OUT);
    end

    initial
    begin
      CLOCK = 0;
      A = 32'h00000001;
      B = 32'h00000002;
      C_IN = 1'b0;
      #20 $finish;
    end

endmodule