data/full_repos/permissive/143278/ivltests/sv_interface.v
 line:9: before: "="
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sv_interface.v:16: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/sv_interface.v:35: Unsupported: wait statements\n      wait (cnt == 3*16);\n      ^~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module source #(

   parameter int unsigned RW=1,
   parameter bit [RW-1:0] RP='0,
   parameter bit [RW-1:0] RR='1
)(
   input logic    clk,
   input logic    rst,
   handshake.src  inf,
   output integer cnt
);


   logic [RW-1:0] rnd;


   always @ (posedge clk, posedge rst)
   if (rst) rnd <= RR;
   else     rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);


   always @ (posedge clk, posedge rst)
   if (rst) cnt <= 32'd0;
   else     cnt <= cnt + (inf.req & inf.grt);


   assign inf.req = rnd[0];

endmodule
module source #(

   parameter int unsigned RW=1,
   parameter bit [RW-1:0] RP='0,
   parameter bit [RW-1:0] RR='1
)(
   input logic    clk,
   input logic    rst,
   handshake.src  inf,
   output integer cnt
);



   logic [RW-1:0] rnd;


   always @ (posedge clk, posedge rst)
   if (rst) rnd <= RR;
   else     rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);


   always @ (posedge clk, posedge rst)
   if (rst) cnt <= 32'd0;
   else     cnt <= cnt + (inf.req & inf.grt);


   assign inf.req = rnd[0];

endmodule