data/full_repos/permissive/125927162/MUX/MUX_tb.v
1: b'%Error: data/full_repos/permissive/125927162/MUX/MUX_tb.v:31: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("MUX.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/MUX/MUX_tb.v:32: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, DUT);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/MUX/MUX_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #15\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/MUX/MUX_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #30\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/MUX/MUX_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #45\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/MUX/MUX_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n   always #5 switch = ~switch;\n          ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_tb ();
   localparam BUS_WIDTH = 4;
   reg [BUS_WIDTH - 1:0] a;
   reg [BUS_WIDTH - 1:0] b;
   reg 	     switch;
   wire [BUS_WIDTH - 1:0] q;

   mux #(.BUS_WIDTH(BUS_WIDTH)) DUT(
	      .a(a),
	      .b(b),
	      .q(q),
	      .switch(switch)
	      );

   initial begin
      $dumpfile("MUX.vcd");
      $dumpvars(0, DUT);
      a = 1;
      b = 7;
      switch = 0;
      #15
	b = 3;
      #30
	a = 3;
      b = 5;
      #45
	a = 0;
      b = 1;
      $finish;
   end

   always #5 switch = ~switch;

endmodule
module mux_tb ();

   localparam BUS_WIDTH = 4;
   reg [BUS_WIDTH - 1:0] a;
   reg [BUS_WIDTH - 1:0] b;
   reg 	     switch;
   wire [BUS_WIDTH - 1:0] q;

   mux #(.BUS_WIDTH(BUS_WIDTH)) DUT(
	      .a(a),
	      .b(b),
	      .q(q),
	      .switch(switch)
	      );

   initial begin
      $dumpfile("MUX.vcd");
      $dumpvars(0, DUT);
      a = 1;
      b = 7;
      switch = 0;
      #15
	b = 3;
      #30
	a = 3;
      b = 5;
      #45
	a = 0;
      b = 1;
      $finish;
   end

   always #5 switch = ~switch;

endmodule