data/full_repos/permissive/219943485/vga_ctrl.v
data/verilator_xmls/c395a710-8239-4392-b42f-19e913bbbde1.xml
module vga_ctrl(
				 rst_n  
				,clk_pixel  
				,h_sync  
				,v_sync 
				,h_pixel_cnt  
				,v_line_cnt				
            ,vga_sync_n
            ,vga_blank_n
				,h_enable_write
				,v_enable_write
			 );
			 
    input 					rst_n;
    input 					clk_pixel;
    output 					h_sync;
    output 					v_sync;

    output 	[9:0] 		h_pixel_cnt;
    output 	[9:0] 		v_line_cnt;
    output			vga_sync_n;
    output			vga_blank_n;
	 output	h_enable_write;
    output	v_enable_write;


    reg			        vga_sync_n;
    reg			        vga_blank_n;
	 
    reg 			h_sync;
    reg 			v_sync;
    reg		[9:0]		h_pixel_cnt;
    reg 	[9:0] 		v_line_cnt;
    reg	h_enable_write;
    reg	v_enable_write;
	 
	 parameter H_PIXELS = 800;
	 parameter V_LINES  = 525;
	 parameter H_ACTIVE_REGION = 640;
	 parameter V_ACTIVE_REGION = 480;
	 parameter H_FRONT_PORCH = 16;
	 parameter H_BACK_PORCH  = 48;
	 parameter H_SYNC_PERIOD = 96;
	 parameter V_FRONT_PORCH = 10;
	 parameter V_BACK_PORCH  = 23;
	 parameter V_SYNC_PERIOD = 2;
	 





always @(posedge clk_pixel or negedge rst_n)
if(!rst_n)
begin	
	vga_sync_n <=1'b0;
	vga_blank_n<=1'b1;
end
else
begin	
	vga_sync_n <=vga_sync_n;
	vga_blank_n<=vga_blank_n;
end


	 





	 always @ ( posedge clk_pixel or negedge rst_n )
	 if(!rst_n)
	 	h_pixel_cnt <= 0;
	
	 else if(h_pixel_cnt==H_PIXELS - 1)

		h_pixel_cnt<=10'b0;
	 else 
		h_pixel_cnt<=h_pixel_cnt+1'b1;

	
	 always @ ( posedge clk_pixel or negedge rst_n )
	 if(!rst_n)
	 	v_line_cnt <= 0;
	
	 else if((v_line_cnt==V_LINES - 1) && (h_pixel_cnt==H_PIXELS - 1))

		v_line_cnt<=10'b0;
	
	 else if(h_pixel_cnt==H_PIXELS - 1)
		 
		v_line_cnt<=v_line_cnt+1'b1;
	 else
		v_line_cnt<=v_line_cnt;

	






	 always @ ( posedge clk_pixel or negedge rst_n )
	 if(!rst_n)
	 	h_sync <= 1'b1;
	
	 else if(h_pixel_cnt==H_FRONT_PORCH - 1)
		
		h_sync<=1'b0;

	 else if(h_pixel_cnt==H_FRONT_PORCH +  H_SYNC_PERIOD - 1)

		h_sync<=1'b1;
	else
		h_sync<=h_sync;

	 
	 always @ ( posedge clk_pixel or negedge rst_n )
	 if(!rst_n)
	 	v_sync <= 1'b1;
	
	 else if(v_line_cnt==V_FRONT_PORCH - 1)
		
		v_sync<=1'b0;

	 else if(v_line_cnt==V_FRONT_PORCH +  V_SYNC_PERIOD - 1)

		v_sync<=1'b1;
	else
		v_sync<=v_sync;






	 always @ ( posedge clk_pixel or negedge rst_n )
	 if(!rst_n)
	 	h_enable_write <= 0;
	
	 else if(h_pixel_cnt==H_FRONT_PORCH + H_SYNC_PERIOD + H_BACK_PORCH - 1)
		 
		h_enable_write <=1'b1;
	
	 else if(h_pixel_cnt == H_PIXELS - 1)

		h_enable_write <=1'b0;


	 always @ ( posedge clk_pixel or negedge rst_n )
	 if(!rst_n)
	 	v_enable_write <= 0;
	
	 else if(v_line_cnt==V_FRONT_PORCH + V_SYNC_PERIOD + V_BACK_PORCH - 1)
		 
		v_enable_write <=1'b1;
	
	 else if(v_line_cnt == V_LINES - 1)

		v_enable_write <=1'b0;

endmodule
module vga_ctrl(
				 rst_n  
				,clk_pixel  
				,h_sync  
				,v_sync 
				,h_pixel_cnt  
				,v_line_cnt				
            ,vga_sync_n
            ,vga_blank_n
				,h_enable_write
				,v_enable_write
			 );

			 
    input 					rst_n;
    input 					clk_pixel;
    output 					h_sync;
    output 					v_sync;

    output 	[9:0] 		h_pixel_cnt;
    output 	[9:0] 		v_line_cnt;
    output			vga_sync_n;
    output			vga_blank_n;
	 output	h_enable_write;
    output	v_enable_write;


    reg			        vga_sync_n;
    reg			        vga_blank_n;
	 
    reg 			h_sync;
    reg 			v_sync;
    reg		[9:0]		h_pixel_cnt;
    reg 	[9:0] 		v_line_cnt;
    reg	h_enable_write;
    reg	v_enable_write;
	 
	 parameter H_PIXELS = 800;
	 parameter V_LINES  = 525;
	 parameter H_ACTIVE_REGION = 640;
	 parameter V_ACTIVE_REGION = 480;
	 parameter H_FRONT_PORCH = 16;
	 parameter H_BACK_PORCH  = 48;
	 parameter H_SYNC_PERIOD = 96;
	 parameter V_FRONT_PORCH = 10;
	 parameter V_BACK_PORCH  = 23;
	 parameter V_SYNC_PERIOD = 2;
	 





always @(posedge clk_pixel or negedge rst_n)
if(!rst_n)
begin	
	vga_sync_n <=1'b0;
	vga_blank_n<=1'b1;
end
else
begin	
	vga_sync_n <=vga_sync_n;
	vga_blank_n<=vga_blank_n;
end


	 





	 always @ ( posedge clk_pixel or negedge rst_n )
	 if(!rst_n)
	 	h_pixel_cnt <= 0;
	
	 else if(h_pixel_cnt==H_PIXELS - 1)

		h_pixel_cnt<=10'b0;
	 else 
		h_pixel_cnt<=h_pixel_cnt+1'b1;

	
	 always @ ( posedge clk_pixel or negedge rst_n )
	 if(!rst_n)
	 	v_line_cnt <= 0;
	
	 else if((v_line_cnt==V_LINES - 1) && (h_pixel_cnt==H_PIXELS - 1))

		v_line_cnt<=10'b0;
	
	 else if(h_pixel_cnt==H_PIXELS - 1)
		 
		v_line_cnt<=v_line_cnt+1'b1;
	 else
		v_line_cnt<=v_line_cnt;

	






	 always @ ( posedge clk_pixel or negedge rst_n )
	 if(!rst_n)
	 	h_sync <= 1'b1;
	
	 else if(h_pixel_cnt==H_FRONT_PORCH - 1)
		
		h_sync<=1'b0;

	 else if(h_pixel_cnt==H_FRONT_PORCH +  H_SYNC_PERIOD - 1)

		h_sync<=1'b1;
	else
		h_sync<=h_sync;

	 
	 always @ ( posedge clk_pixel or negedge rst_n )
	 if(!rst_n)
	 	v_sync <= 1'b1;
	
	 else if(v_line_cnt==V_FRONT_PORCH - 1)
		
		v_sync<=1'b0;

	 else if(v_line_cnt==V_FRONT_PORCH +  V_SYNC_PERIOD - 1)

		v_sync<=1'b1;
	else
		v_sync<=v_sync;






	 always @ ( posedge clk_pixel or negedge rst_n )
	 if(!rst_n)
	 	h_enable_write <= 0;
	
	 else if(h_pixel_cnt==H_FRONT_PORCH + H_SYNC_PERIOD + H_BACK_PORCH - 1)
		 
		h_enable_write <=1'b1;
	
	 else if(h_pixel_cnt == H_PIXELS - 1)

		h_enable_write <=1'b0;


	 always @ ( posedge clk_pixel or negedge rst_n )
	 if(!rst_n)
	 	v_enable_write <= 0;
	
	 else if(v_line_cnt==V_FRONT_PORCH + V_SYNC_PERIOD + V_BACK_PORCH - 1)
		 
		v_enable_write <=1'b1;
	
	 else if(v_line_cnt == V_LINES - 1)

		v_enable_write <=1'b0;

endmodule