data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath/datapath.v
1: b"%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath/datapath.v:39: Cannot find file containing module: 'dreg'\n    dreg pc_reg (\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath,data/full_repos/permissive/168234415/dreg\n             data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath,data/full_repos/permissive/168234415/dreg.v\n             data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath,data/full_repos/permissive/168234415/dreg.sv\n             dreg\n             dreg.v\n             dreg.sv\n             obj_dir/dreg\n             obj_dir/dreg.v\n             obj_dir/dreg.sv\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath/datapath.v:46: Cannot find file containing module: 'adder'\n    adder pc_plus_4 (\n    ^~~~~\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath/datapath.v:52: Cannot find file containing module: 'adder'\n    adder pc_plus_br (\n    ^~~~~\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath/datapath.v:58: Cannot find file containing module: 'mux2'\n    mux2 #(32) pc_src_mux (\n    ^~~~\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath/datapath.v:65: Cannot find file containing module: 'mux2'\n    mux2 #(32) pc_jmp_mux (\n    ^~~~\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath/datapath.v:73: Cannot find file containing module: 'mux2'\n    mux2 #(5) rf_wa_mux (\n    ^~~~\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath/datapath.v:80: Cannot find file containing module: 'regfile'\n    regfile rf (\n    ^~~~~~~\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath/datapath.v:93: Cannot find file containing module: 'signext'\n    signext se (\n    ^~~~~~~\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath/datapath.v:99: Cannot find file containing module: 'mux2'\n    mux2 #(32) alu_pb_mux (\n    ^~~~\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath/datapath.v:106: Cannot find file containing module: 'alu'\n    alu alu (\n    ^~~\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/datapath/datapath.v:115: Cannot find file containing module: 'mux2'\n    mux2 #(32) rf_wd_mux (\n    ^~~~\n%Error: Exiting due to 11 error(s)\n"
module datapath (
        input  wire        clk,
        input  wire        rst,
        input  wire        branch,
        input  wire        jump,
        input  wire        reg_dst,
        input  wire        we_reg,
        input  wire        alu_src,
        input  wire        dm2reg,
        input  wire [2:0]  alu_ctrl,
        input  wire [4:0]  ra3,
        input  wire [31:0] instr,
        input  wire [31:0] rd_dm,
        output wire [31:0] pc_current,
        output wire [31:0] alu_out,
        output wire [31:0] wd_dm,
        output wire [31:0] rd3
    );

    wire [4:0]  rf_wa;
    wire        pc_src;
    wire [31:0] pc_plus4;
    wire [31:0] pc_pre;
    wire [31:0] pc_next;
    wire [31:0] sext_imm;
    wire [31:0] ba;
    wire [31:0] bta;
    wire [31:0] jta;
    wire [31:0] alu_pa;
    wire [31:0] alu_pb;
    wire [31:0] wd_rf;
    wire        zero;
    
    assign pc_src = branch & zero;
    assign ba = {sext_imm[29:0], 2'b00};
    assign jta = {pc_plus4[31:28], instr[25:0], 2'b00};
    

    dreg pc_reg (
            .clk            (clk),
            .rst            (rst),
            .d              (pc_next),
            .q              (pc_current)
        );

    adder pc_plus_4 (
            .a              (pc_current),
            .b              (32'd4),
            .y              (pc_plus4)
        );

    adder pc_plus_br (
            .a              (pc_plus4),
            .b              (ba),
            .y              (bta)
        );

    mux2 #(32) pc_src_mux (
            .sel            (pc_src),
            .a              (pc_plus4),
            .b              (bta),
            .y              (pc_pre)
        );

    mux2 #(32) pc_jmp_mux (
            .sel            (jump),
            .a              (pc_pre),
            .b              (jta),
            .y              (pc_next)
        );


    mux2 #(5) rf_wa_mux (
            .sel            (reg_dst),
            .a              (instr[20:16]),
            .b              (instr[15:11]),
            .y              (rf_wa)
        );

    regfile rf (
            .clk            (clk),
            .we             (we_reg),
            .ra1            (instr[25:21]),
            .ra2            (instr[20:16]),
            .ra3            (ra3),
            .wa             (rf_wa),
            .wd             (wd_rf),
            .rd1            (alu_pa),
            .rd2            (wd_dm),
            .rd3            (rd3)
        );

    signext se (
            .a              (instr[15:0]),
            .y              (sext_imm)
        );


    mux2 #(32) alu_pb_mux (
            .sel            (alu_src),
            .a              (wd_dm),
            .b              (sext_imm),
            .y              (alu_pb)
        );

    alu alu (
            .op             (alu_ctrl),
            .a              (alu_pa),
            .b              (alu_pb),
            .zero           (zero),
            .y              (alu_out)
        );


    mux2 #(32) rf_wd_mux (
            .sel            (dm2reg),
            .a              (alu_out),
            .b              (rd_dm),
            .y              (wd_rf)
        );

endmodule
module datapath (
        input  wire        clk,
        input  wire        rst,
        input  wire        branch,
        input  wire        jump,
        input  wire        reg_dst,
        input  wire        we_reg,
        input  wire        alu_src,
        input  wire        dm2reg,
        input  wire [2:0]  alu_ctrl,
        input  wire [4:0]  ra3,
        input  wire [31:0] instr,
        input  wire [31:0] rd_dm,
        output wire [31:0] pc_current,
        output wire [31:0] alu_out,
        output wire [31:0] wd_dm,
        output wire [31:0] rd3
    );


    wire [4:0]  rf_wa;
    wire        pc_src;
    wire [31:0] pc_plus4;
    wire [31:0] pc_pre;
    wire [31:0] pc_next;
    wire [31:0] sext_imm;
    wire [31:0] ba;
    wire [31:0] bta;
    wire [31:0] jta;
    wire [31:0] alu_pa;
    wire [31:0] alu_pb;
    wire [31:0] wd_rf;
    wire        zero;
    
    assign pc_src = branch & zero;
    assign ba = {sext_imm[29:0], 2'b00};
    assign jta = {pc_plus4[31:28], instr[25:0], 2'b00};
    

    dreg pc_reg (
            .clk            (clk),
            .rst            (rst),
            .d              (pc_next),
            .q              (pc_current)
        );

    adder pc_plus_4 (
            .a              (pc_current),
            .b              (32'd4),
            .y              (pc_plus4)
        );

    adder pc_plus_br (
            .a              (pc_plus4),
            .b              (ba),
            .y              (bta)
        );

    mux2 #(32) pc_src_mux (
            .sel            (pc_src),
            .a              (pc_plus4),
            .b              (bta),
            .y              (pc_pre)
        );

    mux2 #(32) pc_jmp_mux (
            .sel            (jump),
            .a              (pc_pre),
            .b              (jta),
            .y              (pc_next)
        );


    mux2 #(5) rf_wa_mux (
            .sel            (reg_dst),
            .a              (instr[20:16]),
            .b              (instr[15:11]),
            .y              (rf_wa)
        );

    regfile rf (
            .clk            (clk),
            .we             (we_reg),
            .ra1            (instr[25:21]),
            .ra2            (instr[20:16]),
            .ra3            (ra3),
            .wa             (rf_wa),
            .wd             (wd_rf),
            .rd1            (alu_pa),
            .rd2            (wd_dm),
            .rd3            (rd3)
        );

    signext se (
            .a              (instr[15:0]),
            .y              (sext_imm)
        );


    mux2 #(32) alu_pb_mux (
            .sel            (alu_src),
            .a              (wd_dm),
            .b              (sext_imm),
            .y              (alu_pb)
        );

    alu alu (
            .op             (alu_ctrl),
            .a              (alu_pa),
            .b              (alu_pb),
            .zero           (zero),
            .y              (alu_out)
        );


    mux2 #(32) rf_wd_mux (
            .sel            (dm2reg),
            .a              (alu_out),
            .b              (rd_dm),
            .y              (wd_rf)
        );

endmodule