data/full_repos/permissive/137045072/pipeline_dec2exec.v
1: b'%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:22: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:34: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] pc_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input      [`DATA_BUS] pc_in,\n                         ^\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:35: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] pc_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:36: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] raw_inst_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:37: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] raw_inst_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:38: Define or directive not defined: \'`INST_BUS\'\n    input      [`INST_BUS] inst_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:39: Define or directive not defined: \'`INST_BUS\'\n    output reg [`INST_BUS] inst_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:40: Define or directive not defined: \'`ALU_OP_BUS\'\n    input      [`ALU_OP_BUS] alu_op_in,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:41: Define or directive not defined: \'`ALU_OP_BUS\'\n    output reg [`ALU_OP_BUS] alu_op_out,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:42: Define or directive not defined: \'`EX_SRC_BUS\'\n    input      [`EX_SRC_BUS] exec_src_in,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:43: Define or directive not defined: \'`EX_SRC_BUS\'\n    output reg [`EX_SRC_BUS] exec_src_out,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:44: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] alu_rs_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:45: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] alu_rs_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:46: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] alu_rt_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:47: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] alu_rt_out,  \n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:50: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input      [`DATA_BUS] mem_write_in,\n    ^~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:50: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] mem_write_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:51: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] mem_write_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:54: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input                  wb_reg_in,\n    ^~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:56: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input                  branch_in,\n    ^~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:58: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input                  trap_in,\n    ^~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:60: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input                  illegal_in,\n    ^~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:61: Define or directive not defined: \'`EXCEPT_MASK_BUS\'\n    output reg [`EXCEPT_MASK_BUS] exception_mask,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:62: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] branch_target_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:63: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] branch_target_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:64: Define or directive not defined: \'`VREG_BUS\'\n    input      [`VREG_BUS] virtual_write_addr_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:65: Define or directive not defined: \'`VREG_BUS\'\n    output reg [`VREG_BUS] virtual_write_addr_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:66: Define or directive not defined: \'`PREG_BUS\'\n    input      [`PREG_BUS] physical_write_addr_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:67: Define or directive not defined: \'`PREG_BUS\'\n    output reg [`PREG_BUS] physical_write_addr_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:70: syntax error, unexpected \')\', expecting \',\' or \';\'\n    );\n    ^\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:72: Define or directive not defined: \'`EXCEPT_MASK_BUS\'\n    reg [`EXCEPT_MASK_BUS] exception_mask_reg;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:72: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`EXCEPT_MASK_BUS] exception_mask_reg;\n                         ^\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:154: Define or directive not defined: \'`EXCEPT_ILLEGAL\'\n            exception_mask_reg = exception_mask_reg | (1 << `EXCEPT_ILLEGAL);\n                                                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:155: Define or directive not defined: \'`INST_SYSCALL\'\n        if (inst_in == `INST_SYSCALL)\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_dec2exec.v:156: Define or directive not defined: \'`EXCEPT_SYSCALL\'\n            exception_mask_reg = exception_mask_reg | (1 << `EXCEPT_SYSCALL);\n                                                            ^~~~~~~~~~~~~~~\n%Error: Exiting due to 36 error(s)\n'
module pipeline_dec2exec #(
    parameter DATA_WIDTH = 32,
    parameter FREE_LIST_WIDTH = 3
)(
    input clk,
    input rst_n,
    input flush,
    input global_flush,
    input stall,
    
    input      [`DATA_BUS] pc_in,
    output reg [`DATA_BUS] pc_out,
    input      [`DATA_BUS] raw_inst_in,
    output reg [`DATA_BUS] raw_inst_out,
    input      [`INST_BUS] inst_in,
    output reg [`INST_BUS] inst_out,
    input      [`ALU_OP_BUS] alu_op_in,
    output reg [`ALU_OP_BUS] alu_op_out,
    input      [`EX_SRC_BUS] exec_src_in,
    output reg [`EX_SRC_BUS] exec_src_out,
    input      [`DATA_BUS] alu_rs_in,
    output reg [`DATA_BUS] alu_rs_out,
    input      [`DATA_BUS] alu_rt_in,
    output reg [`DATA_BUS] alu_rt_out,
    input                  mem_enable_in,
    output reg             mem_enable_out,
    input      [`DATA_BUS] mem_write_in,
    output reg [`DATA_BUS] mem_write_out,
    input                  wb_src_in,
    output reg             wb_src_out,
    input                  wb_reg_in,
    output reg             wb_reg_out,
    input                  branch_in,
    output reg             branch_out,
    input                  trap_in,
    output reg             trap_out,
    input                  illegal_in,
    output reg [`EXCEPT_MASK_BUS] exception_mask,
    input      [`DATA_BUS] branch_target_in,
    output reg [`DATA_BUS] branch_target_out,
    input      [`VREG_BUS] virtual_write_addr_in,
    output reg [`VREG_BUS] virtual_write_addr_out,
    input      [`PREG_BUS] physical_write_addr_in,
    output reg [`PREG_BUS] physical_write_addr_out,
    input      [FREE_LIST_WIDTH-1:0] active_list_index_in,
    output reg [FREE_LIST_WIDTH-1:0] active_list_index_out
    );
    
    reg [`EXCEPT_MASK_BUS] exception_mask_reg;

    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            pc_out <= 0;
            raw_inst_out <= 0;
            inst_out <= 0;
            alu_op_out <= 0;
            exec_src_out <= 0;
            alu_rs_out <= 0;
            alu_rt_out <= 0;
            inst_out <= 0;
            mem_enable_out <= 0;
            mem_write_out <= 0;
            wb_src_out <= 0;
            wb_reg_out <= 0;
            branch_out <= 0;
            trap_out <= 0;
            branch_target_out <= 0;
            virtual_write_addr_out <= 0;
            physical_write_addr_out <= 0;
            active_list_index_out <= 0;
            exception_mask <= 0;
        end
        else
        begin
            if (!stall)
            begin
                if (flush || global_flush)
                begin
                    pc_out <= 0;
                    raw_inst_out <= 0;
                    inst_out <= 0;
                    alu_op_out <= 0;
                    exec_src_out <= 0;
                    alu_rs_out <= 0;
                    alu_rt_out <= 0;
                    inst_out <= 0;
                    mem_enable_out <= 0;
                    mem_write_out <= 0;
                    wb_src_out <= 0;
                    wb_reg_out <= 0;
                    branch_out <= 0;
                    trap_out <= 0;
                    branch_target_out <= 0;
                    virtual_write_addr_out <= 0;
                    physical_write_addr_out <= 0;
                    active_list_index_out <= 0;
                    exception_mask <= 0;
                end
                else
                begin
                    pc_out <= pc_in;
                    raw_inst_out <= raw_inst_in;
                    inst_out <= inst_in;
                    alu_op_out <= alu_op_in;
                    exec_src_out <= exec_src_in;
                    alu_rs_out <= alu_rs_in;
                    alu_rt_out <= alu_rt_in;
                    inst_out <= inst_in;
                    mem_enable_out <= mem_enable_in;
                    mem_write_out <= mem_write_in;
                    wb_src_out <= wb_src_in;
                    wb_reg_out <= wb_reg_in;
                    branch_out <= branch_in;
                    trap_out <= trap_in;
                    branch_target_out <= branch_target_in;
                    virtual_write_addr_out <= virtual_write_addr_in;
                    physical_write_addr_out <= physical_write_addr_in;
                    active_list_index_out <= active_list_index_in;
                    exception_mask <= exception_mask_reg;
                end
            end
        end
    end
    
    always @*
    begin
        exception_mask_reg = 0;
        if (illegal_in)
            exception_mask_reg = exception_mask_reg | (1 << `EXCEPT_ILLEGAL);
        if (inst_in == `INST_SYSCALL)
            exception_mask_reg = exception_mask_reg | (1 << `EXCEPT_SYSCALL);
    end
endmodule
module pipeline_dec2exec #(
    parameter DATA_WIDTH = 32,
    parameter FREE_LIST_WIDTH = 3
)(
    input clk,
    input rst_n,
    input flush,
    input global_flush,
    input stall,
    
    input      [`DATA_BUS] pc_in,
    output reg [`DATA_BUS] pc_out,
    input      [`DATA_BUS] raw_inst_in,
    output reg [`DATA_BUS] raw_inst_out,
    input      [`INST_BUS] inst_in,
    output reg [`INST_BUS] inst_out,
    input      [`ALU_OP_BUS] alu_op_in,
    output reg [`ALU_OP_BUS] alu_op_out,
    input      [`EX_SRC_BUS] exec_src_in,
    output reg [`EX_SRC_BUS] exec_src_out,
    input      [`DATA_BUS] alu_rs_in,
    output reg [`DATA_BUS] alu_rs_out,
    input      [`DATA_BUS] alu_rt_in,
    output reg [`DATA_BUS] alu_rt_out,
    input                  mem_enable_in,
    output reg             mem_enable_out,
    input      [`DATA_BUS] mem_write_in,
    output reg [`DATA_BUS] mem_write_out,
    input                  wb_src_in,
    output reg             wb_src_out,
    input                  wb_reg_in,
    output reg             wb_reg_out,
    input                  branch_in,
    output reg             branch_out,
    input                  trap_in,
    output reg             trap_out,
    input                  illegal_in,
    output reg [`EXCEPT_MASK_BUS] exception_mask,
    input      [`DATA_BUS] branch_target_in,
    output reg [`DATA_BUS] branch_target_out,
    input      [`VREG_BUS] virtual_write_addr_in,
    output reg [`VREG_BUS] virtual_write_addr_out,
    input      [`PREG_BUS] physical_write_addr_in,
    output reg [`PREG_BUS] physical_write_addr_out,
    input      [FREE_LIST_WIDTH-1:0] active_list_index_in,
    output reg [FREE_LIST_WIDTH-1:0] active_list_index_out
    );

    
    reg [`EXCEPT_MASK_BUS] exception_mask_reg;

    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            pc_out <= 0;
            raw_inst_out <= 0;
            inst_out <= 0;
            alu_op_out <= 0;
            exec_src_out <= 0;
            alu_rs_out <= 0;
            alu_rt_out <= 0;
            inst_out <= 0;
            mem_enable_out <= 0;
            mem_write_out <= 0;
            wb_src_out <= 0;
            wb_reg_out <= 0;
            branch_out <= 0;
            trap_out <= 0;
            branch_target_out <= 0;
            virtual_write_addr_out <= 0;
            physical_write_addr_out <= 0;
            active_list_index_out <= 0;
            exception_mask <= 0;
        end
        else
        begin
            if (!stall)
            begin
                if (flush || global_flush)
                begin
                    pc_out <= 0;
                    raw_inst_out <= 0;
                    inst_out <= 0;
                    alu_op_out <= 0;
                    exec_src_out <= 0;
                    alu_rs_out <= 0;
                    alu_rt_out <= 0;
                    inst_out <= 0;
                    mem_enable_out <= 0;
                    mem_write_out <= 0;
                    wb_src_out <= 0;
                    wb_reg_out <= 0;
                    branch_out <= 0;
                    trap_out <= 0;
                    branch_target_out <= 0;
                    virtual_write_addr_out <= 0;
                    physical_write_addr_out <= 0;
                    active_list_index_out <= 0;
                    exception_mask <= 0;
                end
                else
                begin
                    pc_out <= pc_in;
                    raw_inst_out <= raw_inst_in;
                    inst_out <= inst_in;
                    alu_op_out <= alu_op_in;
                    exec_src_out <= exec_src_in;
                    alu_rs_out <= alu_rs_in;
                    alu_rt_out <= alu_rt_in;
                    inst_out <= inst_in;
                    mem_enable_out <= mem_enable_in;
                    mem_write_out <= mem_write_in;
                    wb_src_out <= wb_src_in;
                    wb_reg_out <= wb_reg_in;
                    branch_out <= branch_in;
                    trap_out <= trap_in;
                    branch_target_out <= branch_target_in;
                    virtual_write_addr_out <= virtual_write_addr_in;
                    physical_write_addr_out <= physical_write_addr_in;
                    active_list_index_out <= active_list_index_in;
                    exception_mask <= exception_mask_reg;
                end
            end
        end
    end
    
    always @*
    begin
        exception_mask_reg = 0;
        if (illegal_in)
            exception_mask_reg = exception_mask_reg | (1 << `EXCEPT_ILLEGAL);
        if (inst_in == `INST_SYSCALL)
            exception_mask_reg = exception_mask_reg | (1 << `EXCEPT_SYSCALL);
    end
endmodule