data/full_repos/permissive/127883252/rtl/bug_top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:125: Unterminated string\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:38: syntax error, unexpected \')\', expecting \'[\'\n);\n^\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:40: Unsupported: Verilog 2001-config reserved word not implemented; suggest you want `include instead: include\n#include "bug_cfg.vh"\n ^~~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:43: syntax error, unexpected always\nalways @(clk) begin\n^~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:55: syntax error, unexpected always\nalways @(posedge clk or negedge rst_n) begin\n^~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:70: syntax error, unexpected always\nalways @(posedge clk or negedge rst_n) begin\n^~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:76: Define or directive not defined: \'`NUM_3\'\nwire div_pulse_1hz = clk_div_cnt==`NUM_3;\n                                  ^~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nwire div_pulse_1hz = clk_div_cnt==`NUM_3;\n                                        ^\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:82: Define or directive not defined: \'`NUM_1\'\n        patn_1[7:0] <= `NUM_1;        \n                       ^~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:93: syntax error, unexpected initial\ninitial begin\n^~~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:94: Define or directive not defined: \'`NUM_2\'\n    patn_2 = `NUM_2;\n             ^~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:104: syntax error, unexpected always\nalways @(posedge clk or negedge rst_n) begin\n^~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:106: Define or directive not defined: \'`NUM_5\'\n        patn_3 <= `NUM_5;\n                  ^~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:115: syntax error, unexpected IDENTIFIER\nblink_fancy blink_fancy (BITS(8)) (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:131: syntax error, unexpected parameter, expecting \'[\'\n    parameter BITS=8,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:132: syntax error, unexpected \')\', expecting IDENTIFIER\n)(\n^\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:142: syntax error, unexpected localparam, expecting IDENTIFIER\nlocalparam ST_INV = 2;\n^~~~~~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:144: syntax error, unexpected always\nalways @(posedge clk or negedge rst_n) begin\n^~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:146: Define or directive not defined: \'`ST_IDLE\'\n        state = `ST_IDLE;\n                ^~~~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:165: Define or directive not defined: \'`NUM_5\'\n        dout <= `NUM_5;\n                ^~~~~~\n%Error: data/full_repos/permissive/127883252/rtl/bug_top.v:168: Define or directive not defined: \'`NUM_5\'\n            ST_IDLE : dout = `NUM_5;\n                             ^~~~~~\n%Error: Exiting due to 21 error(s)\n'
module bug_top (


    input  clk, 
    

    input  rst_n,    
    

    input  [1:0] i_sw, 
    

    output [7:0] o_led, 
);

#include "bug_cfg.vh"

reg [7:0] o_led;
always @(clk) begin
    if(rst_n) o_led <= 0;
    else o_led <= led_state
end


wire [7:0] led_state;

reg  [3:0] sw_sync;
wire [1:0] sw_mode;


always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        sw_sync <= 'd0;
    end
    else begin
        sw_sync <= {sw_sync[3:0],i_sw};
    end

end

sw_mode = sw_sync[3:2];


reg [31:0] clk_div_cnt;

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) 
        clk_div_cnt <= 0;
    else 
        clk_div_cnt <= clk_div_cnt + 1;

wire div_pulse_1hz = clk_div_cnt==`NUM_3;



always @(posedge clk or posedge rst_n) begin
    if(rst_n) begin
        patn_1[7:0] <= `NUM_1;        
    end
    else if(div_pulse) begin
        patn_1 <= cnt + NUM_2;
    end
end




reg [7:0] patn_2;
initial begin
    patn_2 = `NUM_2;
end
always @* begin
    patn_2 = patn_2<<1;
end



reg [7:0] patn_3;

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        patn_3 <= `NUM_5;
    else if(div_pulse_1hz) begin
        patn_3 <= patn_3>>>1;
    end
end



reg [7:0] patn_4;
blink_fancy blink_fancy (BITS(8)) (
    .clk ( clk),
    rst_n,
    dout( patn_4),
;

always @(sw_mode) begin
    case(sw_mode)
        2'd0: led_state = patn_1;
        2"d1: led_state = patn_2;
        2'd2: led_state = patn_3;
    endcase
end


module blink_fancy (
    parameter BITS=8,
)(
    input clk,
    input rst_n,
    output [BITS-1:0] dout 
);

reg [1:0] state;
reg [1:0] state_next;
localparam ST_IDLE = 0;
localparam ST_SHIFT = 1,
localparam ST_INV = 2;

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) 
        state = `ST_IDLE;
    else 
        state <= state_next;
end

always @(state) begin
    case(state)
        ST_IDLE:
            state_next <= ST_SHIFT;
        ST_SHIFT:
            state_next <= ST_INV;
        ST_INV:
            state_next <= ST_SHIFT;
    endcase

end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) 
        dout <= `NUM_5;
    else begin
        case(state_next):
            ST_IDLE : dout = `NUM_5;
            ST_SHIFT: dout < = {dout[BITS:0],1'b0};
            ST_IDLE : dout <= !dout;
        endcase
    end

endmodule
module bug_top (


    input  clk, 
    

    input  rst_n,    
    

    input  [1:0] i_sw, 
    

    output [7:0] o_led, 
);


#include "bug_cfg.vh"

reg [7:0] o_led;
always @(clk) begin
    if(rst_n) o_led <= 0;
    else o_led <= led_state
end


wire [7:0] led_state;

reg  [3:0] sw_sync;
wire [1:0] sw_mode;


always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        sw_sync <= 'd0;
    end
    else begin
        sw_sync <= {sw_sync[3:0],i_sw};
    end

end

sw_mode = sw_sync[3:2];


reg [31:0] clk_div_cnt;

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) 
        clk_div_cnt <= 0;
    else 
        clk_div_cnt <= clk_div_cnt + 1;

wire div_pulse_1hz = clk_div_cnt==`NUM_3;



always @(posedge clk or posedge rst_n) begin
    if(rst_n) begin
        patn_1[7:0] <= `NUM_1;        
    end
    else if(div_pulse) begin
        patn_1 <= cnt + NUM_2;
    end
end




reg [7:0] patn_2;
initial begin
    patn_2 = `NUM_2;
end
always @* begin
    patn_2 = patn_2<<1;
end



reg [7:0] patn_3;

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        patn_3 <= `NUM_5;
    else if(div_pulse_1hz) begin
        patn_3 <= patn_3>>>1;
    end
end



reg [7:0] patn_4;
blink_fancy blink_fancy (BITS(8)) (
    .clk ( clk),
    rst_n,
    dout( patn_4),
;

always @(sw_mode) begin
    case(sw_mode)
        2'd0: led_state = patn_1;
        2"d1: led_state = patn_2;
        2'd2: led_state = patn_3;
    endcase
end


module blink_fancy (
    parameter BITS=8,
)(
    input clk,
    input rst_n,
    output [BITS-1:0] dout 
);

reg [1:0] state;
reg [1:0] state_next;
localparam ST_IDLE = 0;
localparam ST_SHIFT = 1,
localparam ST_INV = 2;

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) 
        state = `ST_IDLE;
    else 
        state <= state_next;
end

always @(state) begin
    case(state)
        ST_IDLE:
            state_next <= ST_SHIFT;
        ST_SHIFT:
            state_next <= ST_INV;
        ST_INV:
            state_next <= ST_SHIFT;
    endcase

end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) 
        dout <= `NUM_5;
    else begin
        case(state_next):
            ST_IDLE : dout = `NUM_5;
            ST_SHIFT: dout < = {dout[BITS:0],1'b0};
            ST_IDLE : dout <= !dout;
        endcase
    end

endmodule