data/full_repos/permissive/143278/ivltests/pr2395835.v
 line:21: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2395835.v:20: Unsupported: Ignoring delay on this delayed statement.\n #1 ;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2395835.v:21: Operator TASKREF \'abc\' expects 8 bits on the Function Argument, but Function Argument\'s SHIFTR generates 32 or 9 bits.\n                                                                         : ... In instance t\n abc(500 >> 8);\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2395835.v:22: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 or 9 bits.\n                                                                         : ... In instance t\n b = 500 >> 8;\n   ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t();

   reg passed = 1;

   task abc;
      input [7:0] a;

      begin
	 if(a == 1)
	   $display("OK");
	 else
	   begin $display("FAILURE"); passed = 0; end
      end
   endtask

   reg [7:0] b;

   initial
     begin
	#1 ;
	abc(500 >> 8);
	b = 500 >> 8;
	abc(b);

	if (passed)
	  $display("PASSED");
     end
endmodule
module t();


   reg passed = 1;

   task abc;
      input [7:0] a;

      begin
	 if(a == 1)
	   $display("OK");
	 else
	   begin $display("FAILURE"); passed = 0; end
      end
   endtask

   reg [7:0] b;

   initial
     begin
	#1 ;
	abc(500 >> 8);
	b = 500 >> 8;
	abc(b);

	if (passed)
	  $display("PASSED");
     end
endmodule