data/full_repos/permissive/138443719/07-clock/src/clock.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/138443719/07-clock/src/clock.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #(PERIOD/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/138443719/07-clock/src/clock.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #(PERIOD/2);\n  ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock_gen(clk);

parameter PERIOD = 10;

output reg clk;
	 
always
	begin: CLOCK_DRIVER
		clk <= 1'b0;
		#(PERIOD/2);
		clk <= 1'b1;
		#(PERIOD/2);
	end
endmodule
module clock_gen(clk);


parameter PERIOD = 10;

output reg clk;
	 
always
	begin: CLOCK_DRIVER
		clk <= 1'b0;
		#(PERIOD/2);
		clk <= 1'b1;
		#(PERIOD/2);
	end
endmodule