data/full_repos/permissive/21310161/hdl/core_wrap.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/21310161/hdl/core_wrap.v:19: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21310161/hdl,data/full_repos/permissive/21310161/config.vh\n             data/full_repos/permissive/21310161/hdl,data/full_repos/permissive/21310161/config.vh.v\n             data/full_repos/permissive/21310161/hdl,data/full_repos/permissive/21310161/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/21310161/hdl/core_wrap.v:25: Define or directive not defined: \'`NLANES\'\n   output [`NLANES-1:0]    pci_exp_txp,\n           ^~~~~~~\n%Error: data/full_repos/permissive/21310161/hdl/core_wrap.v:26: Define or directive not defined: \'`NLANES\'\n   output [`NLANES-1:0]    pci_exp_txn,\n           ^~~~~~~\n%Error: data/full_repos/permissive/21310161/hdl/core_wrap.v:27: Define or directive not defined: \'`NLANES\'\n   input [`NLANES-1:0]     pci_exp_rxp,\n          ^~~~~~~\n%Error: data/full_repos/permissive/21310161/hdl/core_wrap.v:28: Define or directive not defined: \'`NLANES\'\n   input [`NLANES-1:0]     pci_exp_rxn,\n          ^~~~~~~\n%Error: data/full_repos/permissive/21310161/hdl/core_wrap.v:39: Define or directive not defined: \'`NLANES\'\n   input [9*`NLANES-1:0]   gt_drp_address,\n            ^~~~~~~\n%Error: data/full_repos/permissive/21310161/hdl/core_wrap.v:40: Define or directive not defined: \'`NLANES\'\n   input [`NLANES-1:0]     gt_drp_en,\n          ^~~~~~~\n%Error: data/full_repos/permissive/21310161/hdl/core_wrap.v:41: Define or directive not defined: \'`NLANES\'\n   input [16*`NLANES-1:0]  gt_drp_di,\n             ^~~~~~~\n%Error: data/full_repos/permissive/21310161/hdl/core_wrap.v:42: Define or directive not defined: \'`NLANES\'\n   output [16*`NLANES-1:0] gt_drp_do,\n              ^~~~~~~\n%Error: data/full_repos/permissive/21310161/hdl/core_wrap.v:43: Define or directive not defined: \'`NLANES\'\n   output [`NLANES-1:0]    gt_drp_ready,\n           ^~~~~~~\n%Error: data/full_repos/permissive/21310161/hdl/core_wrap.v:44: Define or directive not defined: \'`NLANES\'\n   input [`NLANES-1:0]     gt_drp_we,\n          ^~~~~~~\n%Error: Exiting due to 11 error(s)\n'
module pcie_core_wrap
  (

   output [`NLANES-1:0]    pci_exp_txp,
   output [`NLANES-1:0]    pci_exp_txn,
   input [`NLANES-1:0] 	   pci_exp_rxp,
   input [`NLANES-1:0] 	   pci_exp_rxn,
   input 		   sys_clk_p,
   input 		   sys_clk_n,
   input 		   sys_rst_n,
   output reg [15:0] 	   pci_id = 16'hDEAD,
   input 		   interrupt,
   output reg 		   interrupt_rdy = 0,
   output reg 		   pci_reset = 0,
   output reg 		   clock = 0,

   input [9*`NLANES-1:0]   gt_drp_address,
   input [`NLANES-1:0] 	   gt_drp_en,
   input [16*`NLANES-1:0]  gt_drp_di,
   output [16*`NLANES-1:0] gt_drp_do,
   output [`NLANES-1:0]    gt_drp_ready,
   input [`NLANES-1:0] 	   gt_drp_we,
   output 		   gt_drp_clock,

   output reg 		   s_axis_tx_tready = 0,
   input [63:0] 	   s_axis_tx_tdata,
   input 		   s_axis_tx_1dw,
   input 		   s_axis_tx_tlast,
   input 		   s_axis_tx_tvalid,

   output reg 		   m_axis_rx_tvalid = 0,
   output reg 		   m_axis_rx_tlast = 0,
   output reg [63:0] 	   m_axis_rx_tdata = 0
   );

   always @ (posedge clock)
     interrupt_rdy <= interrupt;
endmodule
module pcie_core_wrap
  (

   output [`NLANES-1:0]    pci_exp_txp,
   output [`NLANES-1:0]    pci_exp_txn,
   input [`NLANES-1:0] 	   pci_exp_rxp,
   input [`NLANES-1:0] 	   pci_exp_rxn,
   input 		   sys_clk_p,
   input 		   sys_clk_n,
   input 		   sys_rst_n,
   output reg [15:0] 	   pci_id = 16'hDEAD,
   input 		   interrupt,
   output reg 		   interrupt_rdy = 0,
   output reg 		   pci_reset = 0,
   output reg 		   clock = 0,

   input [9*`NLANES-1:0]   gt_drp_address,
   input [`NLANES-1:0] 	   gt_drp_en,
   input [16*`NLANES-1:0]  gt_drp_di,
   output [16*`NLANES-1:0] gt_drp_do,
   output [`NLANES-1:0]    gt_drp_ready,
   input [`NLANES-1:0] 	   gt_drp_we,
   output 		   gt_drp_clock,

   output reg 		   s_axis_tx_tready = 0,
   input [63:0] 	   s_axis_tx_tdata,
   input 		   s_axis_tx_1dw,
   input 		   s_axis_tx_tlast,
   input 		   s_axis_tx_tvalid,

   output reg 		   m_axis_rx_tvalid = 0,
   output reg 		   m_axis_rx_tlast = 0,
   output reg [63:0] 	   m_axis_rx_tdata = 0
   );


   always @ (posedge clock)
     interrupt_rdy <= interrupt;
endmodule