data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:22: Cannot find include file: GP_LED_v1_0_tb_include.vh\n`include "GP_LED_v1_0_tb_include.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design,data/full_repos/permissive/135295301/GP_LED_v1_0_tb_include.vh\n             data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design,data/full_repos/permissive/135295301/GP_LED_v1_0_tb_include.vh.v\n             data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design,data/full_repos/permissive/135295301/GP_LED_v1_0_tb_include.vh.sv\n             GP_LED_v1_0_tb_include.vh\n             GP_LED_v1_0_tb_include.vh.v\n             GP_LED_v1_0_tb_include.vh.sv\n             obj_dir/GP_LED_v1_0_tb_include.vh\n             obj_dir/GP_LED_v1_0_tb_include.vh.v\n             obj_dir/GP_LED_v1_0_tb_include.vh.sv\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:43: Define or directive not defined: \'`BD_WRAPPER\'\n `BD_WRAPPER dut ( .ACLK(tb_ACLK),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:43: syntax error, unexpected \'(\', expecting IDENTIFIER\n `BD_WRAPPER dut ( .ACLK(tb_ACLK),\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n   #500;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:62: syntax error, unexpected \'@\'\n  @(posedge tb_ACLK);\n  ^\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:64: syntax error, unexpected \'@\'\n  @(posedge tb_ACLK);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n always #10 tb_ACLK = !tb_ACLK;\n        ^\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:74: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:74: Unsupported: wait statements\n  wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:75: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:75: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:76: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:76: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:77: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:77: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:78: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);  \n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:78: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);  \n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:86: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:86: Unsupported: wait statements\n  wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:87: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:87: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:88: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:88: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:89: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:89: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:90: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:90: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/GP_LED_1.0/example_designs/bfm_design/GP_LED_v1_0_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: Exiting due to 25 error(s), 4 warning(s)\n'
module GP_LED_v1_0_tb;
	reg tb_ACLK;
	reg tb_ARESETn;
	reg tb_IN_0;
	reg tb_IN_1;
	reg tb_IN_2;
	reg tb_IN_3;
	reg tb_IN_4;
	reg tb_IN_5;
	wire [7:0] tb_LED_Port;


	`BD_WRAPPER dut (	.ACLK(tb_ACLK),
				.ARESETN(tb_ARESETn),
				.IN_0(tb_IN_0),
				.IN_1(tb_IN_1),
				.IN_2(tb_IN_2),
				.IN_3(tb_IN_3),
				.IN_4(tb_IN_4),
				.IN_5(tb_IN_5),
				.LED_Port(tb_LED_Port)
			);





	initial begin
		tb_ARESETn = 1'b0;
	  #500;

		@(posedge tb_ACLK);
	  tb_ARESETn = 1'b1;
		@(posedge tb_ACLK);
	end


	initial tb_ACLK = 1'b0;
	always #10 tb_ACLK = !tb_ACLK;


	initial begin

		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);  


	end


	initial begin

		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     

		#100;

		tb_IN_0 = 1'b1;
		tb_IN_1 = 1'b1;
		tb_IN_2 = 1'b1;
		tb_IN_3 = 1'b1;
		tb_IN_4 = 1'b1;
		tb_IN_5 = 1'b1;

		#100;

		tb_IN_0 = 1'b0;
		tb_IN_1 = 1'b1;
		tb_IN_2 = 1'b0;
		tb_IN_3 = 1'b1;
		tb_IN_4 = 1'b0;
		tb_IN_5 = 1'b1;

	end

endmodule
module GP_LED_v1_0_tb;

	reg tb_ACLK;
	reg tb_ARESETn;
	reg tb_IN_0;
	reg tb_IN_1;
	reg tb_IN_2;
	reg tb_IN_3;
	reg tb_IN_4;
	reg tb_IN_5;
	wire [7:0] tb_LED_Port;


	`BD_WRAPPER dut (	.ACLK(tb_ACLK),
				.ARESETN(tb_ARESETn),
				.IN_0(tb_IN_0),
				.IN_1(tb_IN_1),
				.IN_2(tb_IN_2),
				.IN_3(tb_IN_3),
				.IN_4(tb_IN_4),
				.IN_5(tb_IN_5),
				.LED_Port(tb_LED_Port)
			);





	initial begin
		tb_ARESETn = 1'b0;
	  #500;

		@(posedge tb_ACLK);
	  tb_ARESETn = 1'b1;
		@(posedge tb_ACLK);
	end


	initial tb_ACLK = 1'b0;
	always #10 tb_ACLK = !tb_ACLK;


	initial begin

		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);  


	end


	initial begin

		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     

		#100;

		tb_IN_0 = 1'b1;
		tb_IN_1 = 1'b1;
		tb_IN_2 = 1'b1;
		tb_IN_3 = 1'b1;
		tb_IN_4 = 1'b1;
		tb_IN_5 = 1'b1;

		#100;

		tb_IN_0 = 1'b0;
		tb_IN_1 = 1'b1;
		tb_IN_2 = 1'b0;
		tb_IN_3 = 1'b1;
		tb_IN_4 = 1'b0;
		tb_IN_5 = 1'b1;

	end

endmodule