data/full_repos/permissive/219943485/top.v
1: b"%Error: data/full_repos/permissive/219943485/top.v:96: Cannot find file containing module: 'keyboard'\nkeyboard keyboard_1(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219943485,data/full_repos/permissive/219943485/keyboard\n             data/full_repos/permissive/219943485,data/full_repos/permissive/219943485/keyboard.v\n             data/full_repos/permissive/219943485,data/full_repos/permissive/219943485/keyboard.sv\n             keyboard\n             keyboard.v\n             keyboard.sv\n             obj_dir/keyboard\n             obj_dir/keyboard.v\n             obj_dir/keyboard.sv\n%Error: data/full_repos/permissive/219943485/top.v:109: Cannot find file containing module: 'disp_top'\ndisp_top disp_top_1(\n^~~~~~~~\n%Error: data/full_repos/permissive/219943485/top.v:128: Cannot find file containing module: 'hdmi'\nhdmi hdmi_1(\n^~~~\n%Error: Exiting due to 3 error(s)\n"
module top(
		sys_clk,
		sys_rst,

		ps2_clk,
		ps2_data,
		CH7301_clk_p,
		CH7301_clk_n,
		CH7301_data,
		CH7301_h_sync,
		CH7301_v_sync,
		CH7301_de,
		CH7301_scl,
		CH7301_sda,
		CH7301_rstn,

		xsvi_debug
		
		);
		


input sys_clk;
input sys_rst;



input ps2_clk;
input ps2_data;
	
output            CH7301_clk_p;
output            CH7301_clk_n;
output	[11:0]   CH7301_data;
output            CH7301_h_sync;
output            CH7301_v_sync;
output            CH7301_de;
output            CH7301_scl;
output            CH7301_sda;
output            CH7301_rstn;
output	[7:0]    xsvi_debug;






wire h_sync;
wire v_sync;


wire sw_en;
wire sw_en_inv;
assign sw_en=~sw_en_inv;

wire	[7:0]  r_data;
wire	[7:0]  g_data;
wire	[7:0]  b_data;  

wire vga_out_pixel_clock;
wire [23:0] xsvi_video_data = {r_data,g_data,b_data};

wire h_enable_write;
wire v_enable_write;
wire xsvi_video_active = h_enable_write & v_enable_write;

wire up, down, right, left;





reg Bus2IP_Clk;
always @(posedge sys_clk)
			Bus2IP_Clk <= ~Bus2IP_Clk;
	
keyboard keyboard_1(
							.clk(sys_clk), 
							.rst_n(~sys_rst),
							.ps2_data(ps2_data),
							.ps2_clk(ps2_clk),
							.left(left),
							.down(down),
							.right(right),
							.up(up)						
);

	

disp_top disp_top_1(
							.rst_n(~sys_rst),
							.vga_clk(sys_clk),
							.up(up),
							.down(down),
							.left(left),
							.right(right),
							.h_sync(h_sync),
							.v_sync(v_sync),


							.r_data(r_data),
							.g_data(g_data),
							.b_data(b_data),
							.vga_out_pixel_clock(vga_out_pixel_clock),
							.h_enable_write(h_enable_write),
							.v_enable_write(v_enable_write)
							);

hdmi hdmi_1(
							.sys_clk(sys_clk),
							.Bus2IP_Reset(sys_rst),
							.xsvi_pix_clk(vga_out_pixel_clock),
							.xsvi_h_sync(h_sync),
							.xsvi_v_sync(v_sync),
							.xsvi_video_data(xsvi_video_data),
							.xsvi_video_active(xsvi_video_active),
							.Bus2IP_Clk(Bus2IP_Clk),
							
							.CH7301_clk_p(CH7301_clk_p),
							.CH7301_clk_n(CH7301_clk_n),
							.CH7301_data(CH7301_data),
							.CH7301_h_sync(CH7301_h_sync),
							.CH7301_v_sync(CH7301_v_sync),
							.CH7301_de(CH7301_de),
							.CH7301_scl(CH7301_scl),
							.CH7301_sda(CH7301_sda),
							.CH7301_rstn(CH7301_rstn),
							.xsvi_debug(xsvi_debug)
							
							);




endmodule
module top(
		sys_clk,
		sys_rst,

		ps2_clk,
		ps2_data,
		CH7301_clk_p,
		CH7301_clk_n,
		CH7301_data,
		CH7301_h_sync,
		CH7301_v_sync,
		CH7301_de,
		CH7301_scl,
		CH7301_sda,
		CH7301_rstn,

		xsvi_debug
		
		);

		


input sys_clk;
input sys_rst;



input ps2_clk;
input ps2_data;
	
output            CH7301_clk_p;
output            CH7301_clk_n;
output	[11:0]   CH7301_data;
output            CH7301_h_sync;
output            CH7301_v_sync;
output            CH7301_de;
output            CH7301_scl;
output            CH7301_sda;
output            CH7301_rstn;
output	[7:0]    xsvi_debug;






wire h_sync;
wire v_sync;


wire sw_en;
wire sw_en_inv;
assign sw_en=~sw_en_inv;

wire	[7:0]  r_data;
wire	[7:0]  g_data;
wire	[7:0]  b_data;  

wire vga_out_pixel_clock;
wire [23:0] xsvi_video_data = {r_data,g_data,b_data};

wire h_enable_write;
wire v_enable_write;
wire xsvi_video_active = h_enable_write & v_enable_write;

wire up, down, right, left;





reg Bus2IP_Clk;
always @(posedge sys_clk)
			Bus2IP_Clk <= ~Bus2IP_Clk;
	
keyboard keyboard_1(
							.clk(sys_clk), 
							.rst_n(~sys_rst),
							.ps2_data(ps2_data),
							.ps2_clk(ps2_clk),
							.left(left),
							.down(down),
							.right(right),
							.up(up)						
);

	

disp_top disp_top_1(
							.rst_n(~sys_rst),
							.vga_clk(sys_clk),
							.up(up),
							.down(down),
							.left(left),
							.right(right),
							.h_sync(h_sync),
							.v_sync(v_sync),


							.r_data(r_data),
							.g_data(g_data),
							.b_data(b_data),
							.vga_out_pixel_clock(vga_out_pixel_clock),
							.h_enable_write(h_enable_write),
							.v_enable_write(v_enable_write)
							);

hdmi hdmi_1(
							.sys_clk(sys_clk),
							.Bus2IP_Reset(sys_rst),
							.xsvi_pix_clk(vga_out_pixel_clock),
							.xsvi_h_sync(h_sync),
							.xsvi_v_sync(v_sync),
							.xsvi_video_data(xsvi_video_data),
							.xsvi_video_active(xsvi_video_active),
							.Bus2IP_Clk(Bus2IP_Clk),
							
							.CH7301_clk_p(CH7301_clk_p),
							.CH7301_clk_n(CH7301_clk_n),
							.CH7301_data(CH7301_data),
							.CH7301_h_sync(CH7301_h_sync),
							.CH7301_v_sync(CH7301_v_sync),
							.CH7301_de(CH7301_de),
							.CH7301_scl(CH7301_scl),
							.CH7301_sda(CH7301_sda),
							.CH7301_rstn(CH7301_rstn),
							.xsvi_debug(xsvi_debug)
							
							);




endmodule