data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_hk.v
1: b"%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/red_pitaya_hk.v:95: Cannot find file containing module: 'DNA_PORT'\nDNA_PORT #(.SIM_DNA_VALUE (DNA)) i_DNA (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl,data/full_repos/permissive/113454857/DNA_PORT\n             data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl,data/full_repos/permissive/113454857/DNA_PORT.v\n             data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl,data/full_repos/permissive/113454857/DNA_PORT.sv\n             DNA_PORT\n             DNA_PORT.v\n             DNA_PORT.sv\n             obj_dir/DNA_PORT\n             obj_dir/DNA_PORT.v\n             obj_dir/DNA_PORT.sv\n%Error: Exiting due to 1 error(s)\n"
module red_pitaya_hk #(
  parameter DWL = 8,
  parameter DWE = 8,
  parameter [57-1:0] DNA = 57'h0823456789ABCDE
)(

  input                clk_i      ,
  input                rstn_i     ,

  output reg [DWL-1:0] led_o      ,

  output reg           digital_loop,

  input      [DWE-1:0] exp_p_dat_i,
  output reg [DWE-1:0] exp_p_dat_o,
  output reg [DWE-1:0] exp_p_dir_o,
  input      [DWE-1:0] exp_n_dat_i,
  output reg [  7-1:0] exp_n_dat_o,
  output reg [  7-1:0] exp_n_dir_o,

  input      [ 32-1:0] sys_addr   ,
  input      [ 32-1:0] sys_wdata  ,
  input      [  4-1:0] sys_sel    ,
  input                sys_wen    ,
  input                sys_ren    ,
  output reg [ 32-1:0] sys_rdata  ,
  output reg           sys_err    ,
  output reg           sys_ack
);





wire           dna_dout ;
reg            dna_clk  ;
reg            dna_read ;
reg            dna_shift;
reg  [ 9-1: 0] dna_cnt  ;
reg  [57-1: 0] dna_value;
reg            dna_done ;

always @(posedge clk_i)
if (rstn_i == 1'b0) begin
  dna_clk   <=  1'b0;
  dna_read  <=  1'b0;
  dna_shift <=  1'b0;
  dna_cnt   <=  9'd0;
  dna_value <= 57'd0;
  dna_done  <=  1'b0;
end else begin
  if (!dna_done)
    dna_cnt <= dna_cnt + 1'd1;

  dna_clk <= dna_cnt[2] ;
  dna_read  <= (dna_cnt < 9'd10);
  dna_shift <= (dna_cnt > 9'd18);

  if ((dna_cnt[2:0]==3'h0) && !dna_done)
    dna_value <= {dna_value[57-2:0], dna_dout};

  if (dna_cnt > 9'd465)
    dna_done <= 1'b1;
end


DNA_PORT #(.SIM_DNA_VALUE (DNA)) i_DNA (
  .DOUT  ( dna_dout   ),
  .CLK   ( dna_clk    ),
  .DIN   ( 1'b0       ),
  .READ  ( dna_read   ),
  .SHIFT ( dna_shift  )
);





wire [32-1: 0] id_value;

assign id_value[31: 4] = 28'h0;
assign id_value[ 3: 0] =  4'h1;





always @(posedge clk_i)
if (rstn_i == 1'b0) begin
  led_o        <= {DWL{1'b0}};
  exp_p_dat_o  <= {DWE{1'b0}};
  exp_p_dir_o  <= {DWE{1'b0}};
  exp_n_dat_o  <= {7{1'b0}};
  exp_n_dir_o  <= {7{1'b0}};
end else if (sys_wen) begin
  if (sys_addr[19:0]==20'h0c)   digital_loop <= sys_wdata[0];

  if (sys_addr[19:0]==20'h10)   exp_p_dir_o  <= sys_wdata[DWE-1:0];
  if (sys_addr[19:0]==20'h14)   exp_n_dir_o  <= sys_wdata[  7-1:0];
  if (sys_addr[19:0]==20'h18)   exp_p_dat_o  <= sys_wdata[DWE-1:0];
  if (sys_addr[19:0]==20'h1C)   exp_n_dat_o  <= sys_wdata[  7-1:0];

  if (sys_addr[19:0]==20'h30)   led_o        <= sys_wdata[DWL-1:0];
end

wire sys_en;
assign sys_en = sys_wen | sys_ren;

always @(posedge clk_i)
if (rstn_i == 1'b0) begin
  sys_err <= 1'b0;
  sys_ack <= 1'b0;
end else begin
  sys_err <= 1'b0;

  casez (sys_addr[19:0])
    20'h00000: begin sys_ack <= sys_en;  sys_rdata <= {                id_value          }; end
    20'h00004: begin sys_ack <= sys_en;  sys_rdata <= {                dna_value[32-1: 0]}; end
    20'h00008: begin sys_ack <= sys_en;  sys_rdata <= {{64- 57{1'b0}}, dna_value[57-1:32]}; end
    20'h0000c: begin sys_ack <= sys_en;  sys_rdata <= {{32-  1{1'b0}}, digital_loop      }; end

    20'h00010: begin sys_ack <= sys_en;  sys_rdata <= {{32-DWE{1'b0}}, exp_p_dir_o}       ; end
    20'h00014: begin sys_ack <= sys_en;  sys_rdata <= {{32-7{1'b0}}  , exp_n_dir_o}       ; end
    20'h00018: begin sys_ack <= sys_en;  sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_o}       ; end
    20'h0001C: begin sys_ack <= sys_en;  sys_rdata <= {{32-7{1'b0}}  , exp_n_dat_o}       ; end
    20'h00020: begin sys_ack <= sys_en;  sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_i}       ; end
    20'h00024: begin sys_ack <= sys_en;  sys_rdata <= {{32-DWE{1'b0}}, exp_n_dat_i}       ; end

    20'h00030: begin sys_ack <= sys_en;  sys_rdata <= {{32-DWL{1'b0}}, led_o}             ; end

      default: begin sys_ack <= sys_en;  sys_rdata <=  32'h0                              ; end
  endcase
end

endmodule
module red_pitaya_hk #(
  parameter DWL = 8,
  parameter DWE = 8,
  parameter [57-1:0] DNA = 57'h0823456789ABCDE
)(

  input                clk_i      ,
  input                rstn_i     ,

  output reg [DWL-1:0] led_o      ,

  output reg           digital_loop,

  input      [DWE-1:0] exp_p_dat_i,
  output reg [DWE-1:0] exp_p_dat_o,
  output reg [DWE-1:0] exp_p_dir_o,
  input      [DWE-1:0] exp_n_dat_i,
  output reg [  7-1:0] exp_n_dat_o,
  output reg [  7-1:0] exp_n_dir_o,

  input      [ 32-1:0] sys_addr   ,
  input      [ 32-1:0] sys_wdata  ,
  input      [  4-1:0] sys_sel    ,
  input                sys_wen    ,
  input                sys_ren    ,
  output reg [ 32-1:0] sys_rdata  ,
  output reg           sys_err    ,
  output reg           sys_ack
);






wire           dna_dout ;
reg            dna_clk  ;
reg            dna_read ;
reg            dna_shift;
reg  [ 9-1: 0] dna_cnt  ;
reg  [57-1: 0] dna_value;
reg            dna_done ;

always @(posedge clk_i)
if (rstn_i == 1'b0) begin
  dna_clk   <=  1'b0;
  dna_read  <=  1'b0;
  dna_shift <=  1'b0;
  dna_cnt   <=  9'd0;
  dna_value <= 57'd0;
  dna_done  <=  1'b0;
end else begin
  if (!dna_done)
    dna_cnt <= dna_cnt + 1'd1;

  dna_clk <= dna_cnt[2] ;
  dna_read  <= (dna_cnt < 9'd10);
  dna_shift <= (dna_cnt > 9'd18);

  if ((dna_cnt[2:0]==3'h0) && !dna_done)
    dna_value <= {dna_value[57-2:0], dna_dout};

  if (dna_cnt > 9'd465)
    dna_done <= 1'b1;
end


DNA_PORT #(.SIM_DNA_VALUE (DNA)) i_DNA (
  .DOUT  ( dna_dout   ),
  .CLK   ( dna_clk    ),
  .DIN   ( 1'b0       ),
  .READ  ( dna_read   ),
  .SHIFT ( dna_shift  )
);





wire [32-1: 0] id_value;

assign id_value[31: 4] = 28'h0;
assign id_value[ 3: 0] =  4'h1;





always @(posedge clk_i)
if (rstn_i == 1'b0) begin
  led_o        <= {DWL{1'b0}};
  exp_p_dat_o  <= {DWE{1'b0}};
  exp_p_dir_o  <= {DWE{1'b0}};
  exp_n_dat_o  <= {7{1'b0}};
  exp_n_dir_o  <= {7{1'b0}};
end else if (sys_wen) begin
  if (sys_addr[19:0]==20'h0c)   digital_loop <= sys_wdata[0];

  if (sys_addr[19:0]==20'h10)   exp_p_dir_o  <= sys_wdata[DWE-1:0];
  if (sys_addr[19:0]==20'h14)   exp_n_dir_o  <= sys_wdata[  7-1:0];
  if (sys_addr[19:0]==20'h18)   exp_p_dat_o  <= sys_wdata[DWE-1:0];
  if (sys_addr[19:0]==20'h1C)   exp_n_dat_o  <= sys_wdata[  7-1:0];

  if (sys_addr[19:0]==20'h30)   led_o        <= sys_wdata[DWL-1:0];
end

wire sys_en;
assign sys_en = sys_wen | sys_ren;

always @(posedge clk_i)
if (rstn_i == 1'b0) begin
  sys_err <= 1'b0;
  sys_ack <= 1'b0;
end else begin
  sys_err <= 1'b0;

  casez (sys_addr[19:0])
    20'h00000: begin sys_ack <= sys_en;  sys_rdata <= {                id_value          }; end
    20'h00004: begin sys_ack <= sys_en;  sys_rdata <= {                dna_value[32-1: 0]}; end
    20'h00008: begin sys_ack <= sys_en;  sys_rdata <= {{64- 57{1'b0}}, dna_value[57-1:32]}; end
    20'h0000c: begin sys_ack <= sys_en;  sys_rdata <= {{32-  1{1'b0}}, digital_loop      }; end

    20'h00010: begin sys_ack <= sys_en;  sys_rdata <= {{32-DWE{1'b0}}, exp_p_dir_o}       ; end
    20'h00014: begin sys_ack <= sys_en;  sys_rdata <= {{32-7{1'b0}}  , exp_n_dir_o}       ; end
    20'h00018: begin sys_ack <= sys_en;  sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_o}       ; end
    20'h0001C: begin sys_ack <= sys_en;  sys_rdata <= {{32-7{1'b0}}  , exp_n_dat_o}       ; end
    20'h00020: begin sys_ack <= sys_en;  sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_i}       ; end
    20'h00024: begin sys_ack <= sys_en;  sys_rdata <= {{32-DWE{1'b0}}, exp_n_dat_i}       ; end

    20'h00030: begin sys_ack <= sys_en;  sys_rdata <= {{32-DWL{1'b0}}, led_o}             ; end

      default: begin sys_ack <= sys_en;  sys_rdata <=  32'h0                              ; end
  endcase
end

endmodule