data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v
 line:112: before: "("
1: b'%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:1: Cannot find include file: sell.v\n`include "sell.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149231262/FPGA_sell_machine/verilog,data/full_repos/permissive/149231262/sell.v\n             data/full_repos/permissive/149231262/FPGA_sell_machine/verilog,data/full_repos/permissive/149231262/sell.v.v\n             data/full_repos/permissive/149231262/FPGA_sell_machine/verilog,data/full_repos/permissive/149231262/sell.v.sv\n             sell.v\n             sell.v.v\n             sell.v.sv\n             obj_dir/sell.v\n             obj_dir/sell.v.v\n             obj_dir/sell.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:29: Unsupported: Ignoring delay on this delayed statement.\n #100 reset=0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:30: syntax error, unexpected \'@\'\n repeat(2)@(posedge clk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:31: Unsupported: Ignoring delay on this delayed statement.\n #2 one_dollar=1;\n ^\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:32: syntax error, unexpected \'@\'\n repeat(1)@(posedge clk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:33: Unsupported: Ignoring delay on this delayed statement.\n #2 one_dollar=0;\n ^\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:34: syntax error, unexpected \'@\'\n repeat(2)@(posedge clk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:35: Unsupported: Ignoring delay on this delayed statement.\n #2 one_dollar=1;\n ^\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:36: syntax error, unexpected \'@\'\n repeat(1)@(posedge clk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:37: Unsupported: Ignoring delay on this delayed statement.\n #2 one_dollar=0;\n ^\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:38: syntax error, unexpected \'@\'\n repeat(2)@(posedge clk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:39: Unsupported: Ignoring delay on this delayed statement.\n #2 one_dollar=1;\n ^\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:40: syntax error, unexpected \'@\'\n repeat(1)@(posedge clk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:41: Unsupported: Ignoring delay on this delayed statement.\n #2 one_dollar=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:42: Unsupported: Ignoring delay on this delayed statement.\n #20 reset=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:44: Unsupported: Ignoring delay on this delayed statement.\n #100 reset=0;\n ^\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:45: syntax error, unexpected \'@\'\n repeat(2)@(posedge clk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:46: Unsupported: Ignoring delay on this delayed statement.\n #2 one_dollar=1;\n ^\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:47: syntax error, unexpected \'@\'\n repeat(1)@(posedge clk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:48: Unsupported: Ignoring delay on this delayed statement.\n #2 one_dollar=0;\n ^\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:49: syntax error, unexpected \'@\'\n repeat(2)@(posedge clk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:50: Unsupported: Ignoring delay on this delayed statement.\n #2 one_dollar=1;\n ^\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:51: syntax error, unexpected \'@\'\n repeat(1)@(posedge clk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:52: Unsupported: Ignoring delay on this delayed statement.\n #2 one_dollar=0;\n ^\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:53: syntax error, unexpected \'@\'\n repeat(2)@(posedge clk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:54: Unsupported: Ignoring delay on this delayed statement.\n #2 one_dollar=1;\n ^\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:55: syntax error, unexpected \'@\'\n repeat(1)@(posedge clk);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:56: Unsupported: Ignoring delay on this delayed statement.\n #2 one_dollar=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:57: Unsupported: Ignoring delay on this delayed statement.\n #20 reset=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:58: Unsupported: Ignoring delay on this delayed statement.\n #5 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:60: Unsupported: Ignoring delay on this delayed statement.\n always#10 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:62: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("C:/Users/Administrator/Desktop/robei/selltest.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/149231262/FPGA_sell_machine/verilog/selltest.v:63: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: Exiting due to 15 error(s), 18 warning(s)\n'
module selltest();

	reg one_dollar;
	reg half_dollar;
	reg reset;
	reg clk;
	wire collect;
	wire half_out;
	wire dispense;


	sell sell1(
		.one_dollar(one_dollar),
		.half_dollar(half_dollar),
		.reset(reset),
		.clk(clk),
		.collect(collect),
		.half_out(half_out),
		.dispense(dispense));

	initial begin
	one_dollar=0;
	half_dollar=0;
	reset=1;
	clk=0;
	
	#100 reset=0;
	repeat(2)@(posedge clk);
	#2 one_dollar=1;
	repeat(1)@(posedge clk);
	#2 one_dollar=0;
	repeat(2)@(posedge clk);
	#2 one_dollar=1;
	repeat(1)@(posedge clk);
	#2 one_dollar=0;
	repeat(2)@(posedge clk);
	#2 one_dollar=1;
	repeat(1)@(posedge clk);
	#2 one_dollar=0;
	#20 reset=1;
	
	#100 reset=0;
	repeat(2)@(posedge clk);
	#2 one_dollar=1;
	repeat(1)@(posedge clk);
	#2 one_dollar=0;
	repeat(2)@(posedge clk);
	#2 one_dollar=1;
	repeat(1)@(posedge clk);
	#2 one_dollar=0;
	repeat(2)@(posedge clk);
	#2 one_dollar=1;
	repeat(1)@(posedge clk);
	#2 one_dollar=0;
	#20 reset=1;
	#5 $finish;
	end
	always#10 clk=~clk;
	initial begin
		$dumpfile ("C:/Users/Administrator/Desktop/robei/selltest.vcd");
		$dumpvars;
	end
endmodule
module selltest();


	reg one_dollar;
	reg half_dollar;
	reg reset;
	reg clk;
	wire collect;
	wire half_out;
	wire dispense;


	sell sell1(
		.one_dollar(one_dollar),
		.half_dollar(half_dollar),
		.reset(reset),
		.clk(clk),
		.collect(collect),
		.half_out(half_out),
		.dispense(dispense));

	initial begin
	one_dollar=0;
	half_dollar=0;
	reset=1;
	clk=0;
	
	#100 reset=0;
	repeat(2)@(posedge clk);
	#2 one_dollar=1;
	repeat(1)@(posedge clk);
	#2 one_dollar=0;
	repeat(2)@(posedge clk);
	#2 one_dollar=1;
	repeat(1)@(posedge clk);
	#2 one_dollar=0;
	repeat(2)@(posedge clk);
	#2 one_dollar=1;
	repeat(1)@(posedge clk);
	#2 one_dollar=0;
	#20 reset=1;
	
	#100 reset=0;
	repeat(2)@(posedge clk);
	#2 one_dollar=1;
	repeat(1)@(posedge clk);
	#2 one_dollar=0;
	repeat(2)@(posedge clk);
	#2 one_dollar=1;
	repeat(1)@(posedge clk);
	#2 one_dollar=0;
	repeat(2)@(posedge clk);
	#2 one_dollar=1;
	repeat(1)@(posedge clk);
	#2 one_dollar=0;
	#20 reset=1;
	#5 $finish;
	end
	always#10 clk=~clk;
	initial begin
		$dumpfile ("C:/Users/Administrator/Desktop/robei/selltest.vcd");
		$dumpvars;
	end
endmodule