data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v
 line:14: before: "."
1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #5 clock <= ~clock;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d23;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d21;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d17;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d16;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10 write_enable <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d9;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d11;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d12;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d13;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d14;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d15;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #10 size <= 2\'b01;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d9;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d11;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d12;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d13;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d14;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d15;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #10 size <= 2\'b10;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d9;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d11;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d12;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d13;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d14;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d15;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #10 size <= 2\'b11;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d9;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d11;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d12;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d13;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d14;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'d15;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #10 $stop;\n  ^\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:27: Can\'t find definition of \'ram7\' in dotted scope/variable: \'dut.ram7\'\n assign word1 = {dut.ram7.mem[1], dut.ram6.mem[1], dut.ram5.mem[1], dut.ram4.mem[1], dut.ram3.mem[1], dut.ram2.mem[1], dut.ram1.mem[1], dut.ram0.mem[1]};\n                     ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:27: Can\'t find definition of \'ram6\' in dotted scope/variable: \'dut.ram6\'\n assign word1 = {dut.ram7.mem[1], dut.ram6.mem[1], dut.ram5.mem[1], dut.ram4.mem[1], dut.ram3.mem[1], dut.ram2.mem[1], dut.ram1.mem[1], dut.ram0.mem[1]};\n                                      ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:27: Can\'t find definition of \'ram5\' in dotted scope/variable: \'dut.ram5\'\n assign word1 = {dut.ram7.mem[1], dut.ram6.mem[1], dut.ram5.mem[1], dut.ram4.mem[1], dut.ram3.mem[1], dut.ram2.mem[1], dut.ram1.mem[1], dut.ram0.mem[1]};\n                                                       ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:27: Can\'t find definition of \'ram4\' in dotted scope/variable: \'dut.ram4\'\n assign word1 = {dut.ram7.mem[1], dut.ram6.mem[1], dut.ram5.mem[1], dut.ram4.mem[1], dut.ram3.mem[1], dut.ram2.mem[1], dut.ram1.mem[1], dut.ram0.mem[1]};\n                                                                        ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:27: Can\'t find definition of \'ram3\' in dotted scope/variable: \'dut.ram3\'\n assign word1 = {dut.ram7.mem[1], dut.ram6.mem[1], dut.ram5.mem[1], dut.ram4.mem[1], dut.ram3.mem[1], dut.ram2.mem[1], dut.ram1.mem[1], dut.ram0.mem[1]};\n                                                                                         ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:27: Can\'t find definition of \'ram2\' in dotted scope/variable: \'dut.ram2\'\n assign word1 = {dut.ram7.mem[1], dut.ram6.mem[1], dut.ram5.mem[1], dut.ram4.mem[1], dut.ram3.mem[1], dut.ram2.mem[1], dut.ram1.mem[1], dut.ram0.mem[1]};\n                                                                                                          ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:27: Can\'t find definition of \'ram1\' in dotted scope/variable: \'dut.ram1\'\n assign word1 = {dut.ram7.mem[1], dut.ram6.mem[1], dut.ram5.mem[1], dut.ram4.mem[1], dut.ram3.mem[1], dut.ram2.mem[1], dut.ram1.mem[1], dut.ram0.mem[1]};\n                                                                                                                           ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:27: Can\'t find definition of \'ram0\' in dotted scope/variable: \'dut.ram0\'\n assign word1 = {dut.ram7.mem[1], dut.ram6.mem[1], dut.ram5.mem[1], dut.ram4.mem[1], dut.ram3.mem[1], dut.ram2.mem[1], dut.ram1.mem[1], dut.ram0.mem[1]};\n                                                                                                                                            ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:29: Can\'t find definition of \'ram7\' in dotted scope/variable: \'dut.ram7\'\n assign word2 = {dut.ram7.mem[2], dut.ram6.mem[2], dut.ram5.mem[2], dut.ram4.mem[2], dut.ram3.mem[2], dut.ram2.mem[2], dut.ram1.mem[2], dut.ram0.mem[2]};\n                     ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:29: Can\'t find definition of \'ram6\' in dotted scope/variable: \'dut.ram6\'\n assign word2 = {dut.ram7.mem[2], dut.ram6.mem[2], dut.ram5.mem[2], dut.ram4.mem[2], dut.ram3.mem[2], dut.ram2.mem[2], dut.ram1.mem[2], dut.ram0.mem[2]};\n                                      ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:29: Can\'t find definition of \'ram5\' in dotted scope/variable: \'dut.ram5\'\n assign word2 = {dut.ram7.mem[2], dut.ram6.mem[2], dut.ram5.mem[2], dut.ram4.mem[2], dut.ram3.mem[2], dut.ram2.mem[2], dut.ram1.mem[2], dut.ram0.mem[2]};\n                                                       ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:29: Can\'t find definition of \'ram4\' in dotted scope/variable: \'dut.ram4\'\n assign word2 = {dut.ram7.mem[2], dut.ram6.mem[2], dut.ram5.mem[2], dut.ram4.mem[2], dut.ram3.mem[2], dut.ram2.mem[2], dut.ram1.mem[2], dut.ram0.mem[2]};\n                                                                        ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:29: Can\'t find definition of \'ram3\' in dotted scope/variable: \'dut.ram3\'\n assign word2 = {dut.ram7.mem[2], dut.ram6.mem[2], dut.ram5.mem[2], dut.ram4.mem[2], dut.ram3.mem[2], dut.ram2.mem[2], dut.ram1.mem[2], dut.ram0.mem[2]};\n                                                                                         ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:29: Can\'t find definition of \'ram2\' in dotted scope/variable: \'dut.ram2\'\n assign word2 = {dut.ram7.mem[2], dut.ram6.mem[2], dut.ram5.mem[2], dut.ram4.mem[2], dut.ram3.mem[2], dut.ram2.mem[2], dut.ram1.mem[2], dut.ram0.mem[2]};\n                                                                                                          ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:29: Can\'t find definition of \'ram1\' in dotted scope/variable: \'dut.ram1\'\n assign word2 = {dut.ram7.mem[2], dut.ram6.mem[2], dut.ram5.mem[2], dut.ram4.mem[2], dut.ram3.mem[2], dut.ram2.mem[2], dut.ram1.mem[2], dut.ram0.mem[2]};\n                                                                                                                           ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:29: Can\'t find definition of \'ram0\' in dotted scope/variable: \'dut.ram0\'\n assign word2 = {dut.ram7.mem[2], dut.ram6.mem[2], dut.ram5.mem[2], dut.ram4.mem[2], dut.ram3.mem[2], dut.ram2.mem[2], dut.ram1.mem[2], dut.ram0.mem[2]};\n                                                                                                                                            ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:31: Can\'t find definition of \'ram7\' in dotted scope/variable: \'dut.ram7\'\n assign word3 = {dut.ram7.mem[3], dut.ram6.mem[3], dut.ram5.mem[3], dut.ram4.mem[3], dut.ram3.mem[3], dut.ram2.mem[3], dut.ram1.mem[3], dut.ram0.mem[3]};\n                     ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:31: Can\'t find definition of \'ram6\' in dotted scope/variable: \'dut.ram6\'\n assign word3 = {dut.ram7.mem[3], dut.ram6.mem[3], dut.ram5.mem[3], dut.ram4.mem[3], dut.ram3.mem[3], dut.ram2.mem[3], dut.ram1.mem[3], dut.ram0.mem[3]};\n                                      ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:31: Can\'t find definition of \'ram5\' in dotted scope/variable: \'dut.ram5\'\n assign word3 = {dut.ram7.mem[3], dut.ram6.mem[3], dut.ram5.mem[3], dut.ram4.mem[3], dut.ram3.mem[3], dut.ram2.mem[3], dut.ram1.mem[3], dut.ram0.mem[3]};\n                                                       ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:31: Can\'t find definition of \'ram4\' in dotted scope/variable: \'dut.ram4\'\n assign word3 = {dut.ram7.mem[3], dut.ram6.mem[3], dut.ram5.mem[3], dut.ram4.mem[3], dut.ram3.mem[3], dut.ram2.mem[3], dut.ram1.mem[3], dut.ram0.mem[3]};\n                                                                        ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:31: Can\'t find definition of \'ram3\' in dotted scope/variable: \'dut.ram3\'\n assign word3 = {dut.ram7.mem[3], dut.ram6.mem[3], dut.ram5.mem[3], dut.ram4.mem[3], dut.ram3.mem[3], dut.ram2.mem[3], dut.ram1.mem[3], dut.ram0.mem[3]};\n                                                                                         ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:31: Can\'t find definition of \'ram2\' in dotted scope/variable: \'dut.ram2\'\n assign word3 = {dut.ram7.mem[3], dut.ram6.mem[3], dut.ram5.mem[3], dut.ram4.mem[3], dut.ram3.mem[3], dut.ram2.mem[3], dut.ram1.mem[3], dut.ram0.mem[3]};\n                                                                                                          ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:31: Can\'t find definition of \'ram1\' in dotted scope/variable: \'dut.ram1\'\n assign word3 = {dut.ram7.mem[3], dut.ram6.mem[3], dut.ram5.mem[3], dut.ram4.mem[3], dut.ram3.mem[3], dut.ram2.mem[3], dut.ram1.mem[3], dut.ram0.mem[3]};\n                                                                                                                           ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:31: Can\'t find definition of \'ram0\' in dotted scope/variable: \'dut.ram0\'\n assign word3 = {dut.ram7.mem[3], dut.ram6.mem[3], dut.ram5.mem[3], dut.ram4.mem[3], dut.ram3.mem[3], dut.ram2.mem[3], dut.ram1.mem[3], dut.ram0.mem[3]};\n                                                                                                                                            ^~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:33: Can\'t find definition of \'ram_in\' in dotted variable: \'dut.ram_in\'\n assign ram_in = dut.ram_in;\n                     ^~~~~~\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:34: Can\'t find definition of \'cs\' in dotted variable: \'dut.cs\'\n assign ram_cs = dut.cs;\n                     ^~\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit_testbench.v:35: Can\'t find definition of \'a_select\' in dotted variable: \'dut.a_select\'\n assign address_select = dut.a_select;\n                             ^~~~~~~~\n%Error: Exiting due to 27 error(s), 38 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RAM_64bit_testbench();
	reg clock, chip_select, write_enable, output_enable;
	reg [1:0] size;
	reg [63:0] data_in;
	reg [11:0] address;
	tri [63:0] data;
	


	assign data = (chip_select & write_enable) ? data_in : 64'bz;
	
	RAM_64bit dut (clock, address, data, chip_select, write_enable, output_enable, size);

	defparam dut.ADDR_WIDTH = 12;
	

	wire [63:0] word1, word2, word3;

	wire [63:0] ram_in;

	wire [7:0] ram_cs;

	wire [7:0] address_select;



	assign word1 = {dut.ram7.mem[1], dut.ram6.mem[1], dut.ram5.mem[1], dut.ram4.mem[1], dut.ram3.mem[1], dut.ram2.mem[1], dut.ram1.mem[1], dut.ram0.mem[1]};

	assign word2 = {dut.ram7.mem[2], dut.ram6.mem[2], dut.ram5.mem[2], dut.ram4.mem[2], dut.ram3.mem[2], dut.ram2.mem[2], dut.ram1.mem[2], dut.ram0.mem[2]};

	assign word3 = {dut.ram7.mem[3], dut.ram6.mem[3], dut.ram5.mem[3], dut.ram4.mem[3], dut.ram3.mem[3], dut.ram2.mem[3], dut.ram1.mem[3], dut.ram0.mem[3]};

	assign ram_in = dut.ram_in;
	assign ram_cs = dut.cs;
	assign address_select = dut.a_select;
	
	initial begin
		clock <= 1'b0;
	end
	
	always
		#5 clock <= ~clock;
		
	always begin



		chip_select <= 1'b1;
		write_enable <= 1'b1;
		output_enable <= 1'b0;

		address <= 12'd8;
		data_in <= 64'h0706050403020100;
		size <= 2'b11;

		#10 address <= 12'd23;
		data_in <= 64'h000000000000000F;
		size <= 2'b00;

		#10 address <= 12'd21;
		data_in <= 64'h0000000000000E0D;
		size <= 2'b01;

		#10 address <= 12'd17;
		data_in <= 64'h000000000C0B0A09;
		size <= 2'b10;

		#10 address <= 12'd16;
		data_in <= 64'h0000000000000008;
		size <= 2'b00;

		#10 write_enable <= 1'b0;
		output_enable <= 1'b1;
		address <= 12'd8;
		#10 address <= 12'd9;
		#10 address <= 12'd10;
		#10 address <= 12'd11;
		#10 address <= 12'd12;
		#10 address <= 12'd13;
		#10 address <= 12'd14;
		#10 address <= 12'd15;

		#10 size <= 2'b01;
		address <= 12'd8;
		#10 address <= 12'd9;
		#10 address <= 12'd10;
		#10 address <= 12'd11;
		#10 address <= 12'd12;
		#10 address <= 12'd13;
		#10 address <= 12'd14;
		#10 address <= 12'd15;

		#10 size <= 2'b10;
		address <= 12'd8;
		#10 address <= 12'd9;
		#10 address <= 12'd10;
		#10 address <= 12'd11;
		#10 address <= 12'd12;
		#10 address <= 12'd13;
		#10 address <= 12'd14;
		#10 address <= 12'd15;

		#10 size <= 2'b11;
		address <= 12'd8;
		#10 address <= 12'd9;
		#10 address <= 12'd10;
		#10 address <= 12'd11;
		#10 address <= 12'd12;
		#10 address <= 12'd13;
		#10 address <= 12'd14;
		#10 address <= 12'd15;
		#10 $stop;
	end
endmodule
module RAM_64bit_testbench();

	reg clock, chip_select, write_enable, output_enable;
	reg [1:0] size;
	reg [63:0] data_in;
	reg [11:0] address;
	tri [63:0] data;
	


	assign data = (chip_select & write_enable) ? data_in : 64'bz;
	
	RAM_64bit dut (clock, address, data, chip_select, write_enable, output_enable, size);

	defparam dut.ADDR_WIDTH = 12;
	

	wire [63:0] word1, word2, word3;

	wire [63:0] ram_in;

	wire [7:0] ram_cs;

	wire [7:0] address_select;



	assign word1 = {dut.ram7.mem[1], dut.ram6.mem[1], dut.ram5.mem[1], dut.ram4.mem[1], dut.ram3.mem[1], dut.ram2.mem[1], dut.ram1.mem[1], dut.ram0.mem[1]};

	assign word2 = {dut.ram7.mem[2], dut.ram6.mem[2], dut.ram5.mem[2], dut.ram4.mem[2], dut.ram3.mem[2], dut.ram2.mem[2], dut.ram1.mem[2], dut.ram0.mem[2]};

	assign word3 = {dut.ram7.mem[3], dut.ram6.mem[3], dut.ram5.mem[3], dut.ram4.mem[3], dut.ram3.mem[3], dut.ram2.mem[3], dut.ram1.mem[3], dut.ram0.mem[3]};

	assign ram_in = dut.ram_in;
	assign ram_cs = dut.cs;
	assign address_select = dut.a_select;
	
	initial begin
		clock <= 1'b0;
	end
	
	always
		#5 clock <= ~clock;
		
	always begin



		chip_select <= 1'b1;
		write_enable <= 1'b1;
		output_enable <= 1'b0;

		address <= 12'd8;
		data_in <= 64'h0706050403020100;
		size <= 2'b11;

		#10 address <= 12'd23;
		data_in <= 64'h000000000000000F;
		size <= 2'b00;

		#10 address <= 12'd21;
		data_in <= 64'h0000000000000E0D;
		size <= 2'b01;

		#10 address <= 12'd17;
		data_in <= 64'h000000000C0B0A09;
		size <= 2'b10;

		#10 address <= 12'd16;
		data_in <= 64'h0000000000000008;
		size <= 2'b00;

		#10 write_enable <= 1'b0;
		output_enable <= 1'b1;
		address <= 12'd8;
		#10 address <= 12'd9;
		#10 address <= 12'd10;
		#10 address <= 12'd11;
		#10 address <= 12'd12;
		#10 address <= 12'd13;
		#10 address <= 12'd14;
		#10 address <= 12'd15;

		#10 size <= 2'b01;
		address <= 12'd8;
		#10 address <= 12'd9;
		#10 address <= 12'd10;
		#10 address <= 12'd11;
		#10 address <= 12'd12;
		#10 address <= 12'd13;
		#10 address <= 12'd14;
		#10 address <= 12'd15;

		#10 size <= 2'b10;
		address <= 12'd8;
		#10 address <= 12'd9;
		#10 address <= 12'd10;
		#10 address <= 12'd11;
		#10 address <= 12'd12;
		#10 address <= 12'd13;
		#10 address <= 12'd14;
		#10 address <= 12'd15;

		#10 size <= 2'b11;
		address <= 12'd8;
		#10 address <= 12'd9;
		#10 address <= 12'd10;
		#10 address <= 12'd11;
		#10 address <= 12'd12;
		#10 address <= 12'd13;
		#10 address <= 12'd14;
		#10 address <= 12'd15;
		#10 $stop;
	end
endmodule