data/full_repos/permissive/143278/ivltests/pr2219441b.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441b.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 1\'b0) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441b.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 1\'b1) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441b.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 1\'bx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441b.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 1\'bz) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441b.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 1\'b1) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441b.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 1\'b0) begin\n    ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg passed;
  reg [1:0] sel;
  reg [1:0] A;
  wire Z;

  parent parent(.sel(sel), .A(A), .Z(Z));

  initial begin

    passed = 1'b1;
    sel = 2'b11;
    A = 2'b00;
    #1 if (Z !== 1'b0) begin
      $display("FAILED: selected both, expected 1'b0, got %b", Z);
      passed = 1'b0;
    end

    A = 2'b11;
    #1 if (Z !== 1'b1) begin
      $display("FAILED: selected both, expected 1'b1, got %b", Z);
      passed = 1'b0;
    end

    A = 2'b10;
    #1 if (Z !== 1'bx) begin
      $display("FAILED: selected both, expected 1'bx, got %b", Z);
      passed = 1'b0;
    end

    sel = 2'b00;
    #1 if (Z !== 1'bz) begin
      $display("FAILED: deselected, expected 1'bz, got %b", Z);
      passed = 1'b0;
    end

    sel = 2'b10;
    #1 if (Z !== 1'b1) begin
      $display("FAILED: selected (1), expected 1'b1, got %b", Z);
      passed = 1'b0;
    end

    sel = 2'b01;
    #1 if (Z !== 1'b0) begin
      $display("FAILED: selected (0), expected 1'b0, got %b", Z);
      passed = 1'b0;
    end

    if (passed) $display("PASSED");
  end
endmodule
module top;

  reg passed;
  reg [1:0] sel;
  reg [1:0] A;
  wire Z;

  parent parent(.sel(sel), .A(A), .Z(Z));

  initial begin

    passed = 1'b1;
    sel = 2'b11;
    A = 2'b00;
    #1 if (Z !== 1'b0) begin
      $display("FAILED: selected both, expected 1'b0, got %b", Z);
      passed = 1'b0;
    end

    A = 2'b11;
    #1 if (Z !== 1'b1) begin
      $display("FAILED: selected both, expected 1'b1, got %b", Z);
      passed = 1'b0;
    end

    A = 2'b10;
    #1 if (Z !== 1'bx) begin
      $display("FAILED: selected both, expected 1'bx, got %b", Z);
      passed = 1'b0;
    end

    sel = 2'b00;
    #1 if (Z !== 1'bz) begin
      $display("FAILED: deselected, expected 1'bz, got %b", Z);
      passed = 1'b0;
    end

    sel = 2'b10;
    #1 if (Z !== 1'b1) begin
      $display("FAILED: selected (1), expected 1'b1, got %b", Z);
      passed = 1'b0;
    end

    sel = 2'b01;
    #1 if (Z !== 1'b0) begin
      $display("FAILED: selected (0), expected 1'b0, got %b", Z);
      passed = 1'b0;
    end

    if (passed) $display("PASSED");
  end
endmodule