data/full_repos/permissive/181665138/verilog/capitolo_vi/Memoria_Video.v
 line:111: before: "*"
data/verilator_xmls/2e7d5dd6-a199-4e5c-b1f5-5641393006c6.xml
module Memoria_Video(d7_d0, a15_a0, s_, mw_, q7_q0, a15_a0_ag);
    input   [7:0]   d7_d0;
    input   [15:0]  a15_a0;
    input           mw_;
    input           s_;
    input   [15:0]  a15_a0_ag;
    output  [7:0]   q7_q0;


    reg [7:0]   D_LATCH[0:65535];

    wire beta;
    assign beta = ({s_, mw_} == 'B00)?1:0;


    assign q7_q0 = D_LATCH[a15_a0_ag];


    always @(beta or d7_d0) if (beta == 1) D_LATCH[a15_a0] = d7_d0;
endmodule
module Memoria_Video(d7_d0, a15_a0, s_, mw_, q7_q0, a15_a0_ag);

    input   [7:0]   d7_d0;
    input   [15:0]  a15_a0;
    input           mw_;
    input           s_;
    input   [15:0]  a15_a0_ag;
    output  [7:0]   q7_q0;


    reg [7:0]   D_LATCH[0:65535];

    wire beta;
    assign beta = ({s_, mw_} == 'B00)?1:0;


    assign q7_q0 = D_LATCH[a15_a0_ag];


    always @(beta or d7_d0) if (beta == 1) D_LATCH[a15_a0] = d7_d0;
endmodule