data/full_repos/permissive/194106100/DE0/sys_reset.v
data/verilator_xmls/ec8933ce-0615-4cea-ab43-cdec1cd37904.xml
module sys_reset (
	RSTn, CLK, DOUT
);

input RSTn;
input CLK;
output DOUT;

reg [15:0]count;
wire count_up;

	always @(negedge RSTn or posedge CLK) begin
		if(~RSTn)
			count <= 16'h0000;
		else if(count_up==1'b0)
			count <= count + 1;
	end


	assign count_up = count[15];

	assign DOUT = ~count_up;

endmodule
module sys_reset (
	RSTn, CLK, DOUT
);


input RSTn;
input CLK;
output DOUT;

reg [15:0]count;
wire count_up;

	always @(negedge RSTn or posedge CLK) begin
		if(~RSTn)
			count <= 16'h0000;
		else if(count_up==1'b0)
			count <= count + 1;
	end


	assign count_up = count[15];

	assign DOUT = ~count_up;

endmodule