data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:570: Operator SUB expects 7 bits on the RHS, but RHS\'s VARREF \'master_readdatavalid\' generates 1 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_discards <= pending_discards + pending_reads - master_readdatavalid;\n                                                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:572: Operator COND expects 32 or 7 bits on the Conditional True, but Conditional True\'s VARREF \'master_burstcount\' generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_reads <= pending_reads + (avm_read_accepted ? master_burstcount : 0) - keep_read;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:572: Operator SUB expects 32 or 7 bits on the RHS, but RHS\'s VARREF \'keep_read\' generates 1 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_reads <= pending_reads + (avm_read_accepted ? master_burstcount : 0) - keep_read;\n                                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:573: Operator NOT expects 7 bits on the LHS, but LHS\'s VARREF \'finished_discard\' generates 1 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_discards <= pending_discards - (~finished_discard & master_readdatavalid);\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:573: Operator AND expects 7 bits on the RHS, but RHS\'s VARREF \'master_readdatavalid\' generates 1 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_discards <= pending_discards - (~finished_discard & master_readdatavalid);\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:418: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign user_read_addr_word   = (user_read_addr   >> MBYTE_SELECT_BITS);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:419: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign user_read_addr_r_word = (user_read_addr_r >> MBYTE_SELECT_BITS);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:420: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign avm_read_addr_word    = (avm_read_addr    >> MBYTE_SELECT_BITS);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:421: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign wr_addr_word          = (wr_addr          >> MBYTE_SELECT_BITS);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:422: Operator AND expects 27 bits on the RHS, but RHS\'s REPLICATE generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign wr_fifo_addr = wr_addr_word & {LOG2_DEPTH{1\'b1}};\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:422: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s AND generates 27 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign wr_fifo_addr = wr_addr_word & {LOG2_DEPTH{1\'b1}};\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:425: Operator AND expects 27 bits on the RHS, but RHS\'s REPLICATE generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign rd_fifo_addr = wait_for_read_int_r ? (user_read_addr_r_word & {LOG2_DEPTH{1\'b1}}) : \n                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:426: Operator AND expects 27 bits on the RHS, but RHS\'s REPLICATE generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                                                (user_read_addr_word   & {LOG2_DEPTH{1\'b1}}) ;\n                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:425: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s COND generates 27 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign rd_fifo_addr = wait_for_read_int_r ? (user_read_addr_r_word & {LOG2_DEPTH{1\'b1}}) : \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:428: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SUB generates 28 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign fifo_addr_diff = {1\'b0, avm_read_addr_word} - {1\'b0, user_read_addr_r_word};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:490: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 32 or 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size    <= (first_burst_boundary_word_address & 1) ? 1 : (MAXBURSTCOUNT - first_burst_boundary_word_address);\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:490: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'first_burst_boundary_word_address\' generates 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size    <= (first_burst_boundary_word_address & 1) ? 1 : (MAXBURSTCOUNT - first_burst_boundary_word_address);\n                                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:490: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size    <= (first_burst_boundary_word_address & 1) ? 1 : (MAXBURSTCOUNT - first_burst_boundary_word_address);\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:493: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'avm_burst_size\' generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_read_addr  <= (avm_read_addr + (avm_read_success ? (avm_burst_size << MBYTE_SELECT_BITS) : 0));\n                                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:494: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'avm_burst_boundary_word_address\' generates 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size <= avm_read_success_r ? (MAXBURSTCOUNT - avm_burst_boundary_word_address) : avm_burst_size;  \n                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:494: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'avm_burst_size\' generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size <= avm_read_success_r ? (MAXBURSTCOUNT - avm_burst_boundary_word_address) : avm_burst_size;  \n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:494: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size <= avm_read_success_r ? (MAXBURSTCOUNT - avm_burst_boundary_word_address) : avm_burst_size;  \n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:499: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'num_words_in_fifo\' generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_read <= (avm_ctrl_state == 2) & !empty & (fifo_addr_diff_overflow | (num_words_in_fifo < (DEPTH - MAXBURSTCOUNT)));  \n                                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:513: Operator AND expects 32 bits on the RHS, but RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n            assign first_burst_boundary_word_address = (user_read_addr_r >> MBYTE_SELECT_BITS) & {(BURSTCOUNT_WIDTH - 1){1\'b1}};\n                                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:513: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n            assign first_burst_boundary_word_address = (user_read_addr_r >> MBYTE_SELECT_BITS) & {(BURSTCOUNT_WIDTH - 1){1\'b1}};\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:514: Operator AND expects 32 bits on the RHS, but RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n            assign avm_burst_boundary_word_address   = (avm_read_addr >> MBYTE_SELECT_BITS)    & {(BURSTCOUNT_WIDTH - 1){1\'b1}};\n                                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:514: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n            assign avm_burst_boundary_word_address   = (avm_read_addr >> MBYTE_SELECT_BITS)    & {(BURSTCOUNT_WIDTH - 1){1\'b1}};\n                                                     ^\n%Error: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:83: Cannot find file containing module: \'acl_data_fifo\'\nacl_data_fifo #(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules,data/full_repos/permissive/205229557/acl_data_fifo\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules,data/full_repos/permissive/205229557/acl_data_fifo.v\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules,data/full_repos/permissive/205229557/acl_data_fifo.sv\n             acl_data_fifo\n             acl_data_fifo.v\n             acl_data_fifo.sv\n             obj_dir/acl_data_fifo\n             obj_dir/acl_data_fifo.v\n             obj_dir/acl_data_fifo.sv\n%Error: Exiting due to 1 error(s), 27 warning(s)\n'
module lsu_streaming_prefetch_fifo # (
        parameter DEPTH             = 64,
        parameter LOG2_DEPTH        = 6,
        parameter MWIDTH             = 256,
        parameter AWIDTH            = 32,
        parameter MBYTE_SELECT_BITS = 5,
        parameter MAXBURSTCOUNT     = 64,
        parameter BURSTCOUNT_WIDTH  = 6
    ) (
        input clk,
        input reset,
        input flush_external,
        input flush_internal,


        input          [AWIDTH - 1 : 0] user_read_addr   ,
        input          [AWIDTH - 1 : 0] user_read_addr_r ,
        input                           user_valid       ,
        input                           user_valid_r     ,
        output         [MWIDTH - 1 : 0] user_data_out    ,
        output                          wait_for_read    ,
        input                           i_stall          ,


        output reg              empty,
        output [AWIDTH - 1 : 0] fifo_high_addr,


        output reg          [AWIDTH - 1 : 0] avm_read_addr,
        output reg                           avm_read,
        output reg [BURSTCOUNT_WIDTH -1 : 0] avm_burst_size,
        input                                avm_data_valid,
        input                [MWIDTH -1 : 0] avm_data,
        input                                avm_ready
    );






    reg [MWIDTH - 1 : 0] mem [0 : DEPTH - 1];    


    wire [LOG2_DEPTH - 1 : 0] rd_fifo_addr;
    wire [LOG2_DEPTH - 1 : 0] wr_fifo_addr;
    reg  [LOG2_DEPTH - 1 : 0] num_words_in_fifo;
    reg      [AWIDTH - 1 : 0] wr_addr;

    reg [MWIDTH - 1 : 0] fifo_data_out;

    wire avm_read_success;
    reg  avm_read_success_r;
    wire [BURSTCOUNT_WIDTH - 2 : 0] first_burst_boundary_word_address;
    wire [BURSTCOUNT_WIDTH - 2 : 0] avm_burst_boundary_word_address;

    wire [AWIDTH - MBYTE_SELECT_BITS - 1 : 0] user_read_addr_word;
    wire [AWIDTH - MBYTE_SELECT_BITS - 1 : 0] user_read_addr_r_word;
    wire [AWIDTH - MBYTE_SELECT_BITS - 1 : 0] avm_read_addr_word;
    wire [AWIDTH - MBYTE_SELECT_BITS - 1 : 0] wr_addr_word;
    wire [AWIDTH - MBYTE_SELECT_BITS - 1 : 0] fifo_addr_diff;

    wire flush;
    wire fifo_flush;
    reg flush_r;

    reg fifo_addr_diff_overflow;
    reg [1:0] avm_ctrl_state;

    wire wait_for_read_int;
    reg wait_for_read_int_r;







    assign flush = flush_external | flush_internal;


    always @(posedge clk or posedge reset) begin
        if (reset) begin
            flush_r <= 0;
        end else begin
            flush_r <= flush;
        end
    end

    assign fifo_flush = flush & !flush_r;


    always @(posedge clk or posedge reset) begin
        if (reset) begin
            wr_addr <= 0;
            empty <= 1;
        end else begin
            if (fifo_flush) begin
                wr_addr <= user_read_addr_r;
                empty   <= ~user_valid_r;
            end else begin

                if (avm_data_valid) begin
                    wr_addr <= wr_addr + (1 << MBYTE_SELECT_BITS);
                end

                empty <= empty & ~user_valid;
            end
        end
    end

    assign user_read_addr_word   = (user_read_addr   >> MBYTE_SELECT_BITS);
    assign user_read_addr_r_word = (user_read_addr_r >> MBYTE_SELECT_BITS);
    assign avm_read_addr_word    = (avm_read_addr    >> MBYTE_SELECT_BITS);
    assign wr_addr_word          = (wr_addr          >> MBYTE_SELECT_BITS);
    assign wr_fifo_addr = wr_addr_word & {LOG2_DEPTH{1'b1}};


    assign rd_fifo_addr = wait_for_read_int_r ? (user_read_addr_r_word & {LOG2_DEPTH{1'b1}}) : 
                                                (user_read_addr_word   & {LOG2_DEPTH{1'b1}}) ;

    assign fifo_addr_diff = {1'b0, avm_read_addr_word} - {1'b0, user_read_addr_r_word};



    always @(posedge clk) begin
        if (avm_data_valid) begin
            mem[wr_fifo_addr] <= avm_data;
        end

        if (!i_stall) begin
            fifo_data_out <= mem[rd_fifo_addr];
        end
    end




    assign user_data_out = fifo_data_out;


    assign fifo_high_addr = avm_read_addr;







    assign wait_for_read_int = (user_read_addr_word >= wr_addr_word);


    always @(posedge clk or posedge reset) begin
        if (reset) begin
            wait_for_read_int_r <= 0;

        end else begin
            wait_for_read_int_r  <= flush_external ? 0 : ( flush_internal | (wait_for_read_int_r ? ((user_read_addr_r_word >= wr_addr_word) | i_stall) : wait_for_read_int));


        end
    end
    assign wait_for_read = wait_for_read_int_r;



    always @(posedge clk or posedge reset) begin
        if (reset) begin
            avm_read_addr  <= 0;
            avm_burst_size <= 0;
            avm_read       <= 0;
            num_words_in_fifo <= 0;
            fifo_addr_diff_overflow <= 0;
            avm_ctrl_state    <= 0;
            avm_read_success_r <= 0;
        end else begin

            if (fifo_flush) begin
                num_words_in_fifo <= 0;
                fifo_addr_diff_overflow <= 0;
                avm_ctrl_state    <= 0;
                avm_read          <= user_valid_r;
                avm_read_addr     <= user_read_addr_r;
                avm_burst_size    <= (first_burst_boundary_word_address & 1) ? 1 : (MAXBURSTCOUNT - first_burst_boundary_word_address);
                avm_read_success_r <= 0;
            end else begin
                avm_read_addr  <= (avm_read_addr + (avm_read_success ? (avm_burst_size << MBYTE_SELECT_BITS) : 0));
                avm_burst_size <= avm_read_success_r ? (MAXBURSTCOUNT - avm_burst_boundary_word_address) : avm_burst_size;
                num_words_in_fifo <= fifo_addr_diff[LOG2_DEPTH - 1 : 0];
                fifo_addr_diff_overflow <= fifo_addr_diff[AWIDTH - MBYTE_SELECT_BITS - 1];

                avm_ctrl_state <= avm_ctrl_state[1] ? 0 : (avm_ctrl_state + 1);
                avm_read <= (avm_ctrl_state == 2) & !empty & (fifo_addr_diff_overflow | (num_words_in_fifo < (DEPTH - MAXBURSTCOUNT)));
                avm_read_success_r <= avm_read_success;
            end

        end
    end


    generate
        if(BURSTCOUNT_WIDTH == 1) begin

            assign first_burst_boundary_word_address = 0;
            assign avm_burst_boundary_word_address = 0;
        end else begin
            assign first_burst_boundary_word_address = (user_read_addr_r >> MBYTE_SELECT_BITS) & {(BURSTCOUNT_WIDTH - 1){1'b1}};
            assign avm_burst_boundary_word_address   = (avm_read_addr >> MBYTE_SELECT_BITS)    & {(BURSTCOUNT_WIDTH - 1){1'b1}};
        end
    endgenerate

    assign avm_read_success = avm_read & avm_ready;

endmodule
module lsu_streaming_prefetch_fifo # (
        parameter DEPTH             = 64,
        parameter LOG2_DEPTH        = 6,
        parameter MWIDTH             = 256,
        parameter AWIDTH            = 32,
        parameter MBYTE_SELECT_BITS = 5,
        parameter MAXBURSTCOUNT     = 64,
        parameter BURSTCOUNT_WIDTH  = 6
    ) (
        input clk,
        input reset,
        input flush_external,
        input flush_internal,


        input          [AWIDTH - 1 : 0] user_read_addr   ,
        input          [AWIDTH - 1 : 0] user_read_addr_r ,
        input                           user_valid       ,
        input                           user_valid_r     ,
        output         [MWIDTH - 1 : 0] user_data_out    ,
        output                          wait_for_read    ,
        input                           i_stall          ,


        output reg              empty,
        output [AWIDTH - 1 : 0] fifo_high_addr,


        output reg          [AWIDTH - 1 : 0] avm_read_addr,
        output reg                           avm_read,
        output reg [BURSTCOUNT_WIDTH -1 : 0] avm_burst_size,
        input                                avm_data_valid,
        input                [MWIDTH -1 : 0] avm_data,
        input                                avm_ready
    );







    reg [MWIDTH - 1 : 0] mem [0 : DEPTH - 1];    


    wire [LOG2_DEPTH - 1 : 0] rd_fifo_addr;
    wire [LOG2_DEPTH - 1 : 0] wr_fifo_addr;
    reg  [LOG2_DEPTH - 1 : 0] num_words_in_fifo;
    reg      [AWIDTH - 1 : 0] wr_addr;

    reg [MWIDTH - 1 : 0] fifo_data_out;

    wire avm_read_success;
    reg  avm_read_success_r;
    wire [BURSTCOUNT_WIDTH - 2 : 0] first_burst_boundary_word_address;
    wire [BURSTCOUNT_WIDTH - 2 : 0] avm_burst_boundary_word_address;

    wire [AWIDTH - MBYTE_SELECT_BITS - 1 : 0] user_read_addr_word;
    wire [AWIDTH - MBYTE_SELECT_BITS - 1 : 0] user_read_addr_r_word;
    wire [AWIDTH - MBYTE_SELECT_BITS - 1 : 0] avm_read_addr_word;
    wire [AWIDTH - MBYTE_SELECT_BITS - 1 : 0] wr_addr_word;
    wire [AWIDTH - MBYTE_SELECT_BITS - 1 : 0] fifo_addr_diff;

    wire flush;
    wire fifo_flush;
    reg flush_r;

    reg fifo_addr_diff_overflow;
    reg [1:0] avm_ctrl_state;

    wire wait_for_read_int;
    reg wait_for_read_int_r;







    assign flush = flush_external | flush_internal;


    always @(posedge clk or posedge reset) begin
        if (reset) begin
            flush_r <= 0;
        end else begin
            flush_r <= flush;
        end
    end

    assign fifo_flush = flush & !flush_r;


    always @(posedge clk or posedge reset) begin
        if (reset) begin
            wr_addr <= 0;
            empty <= 1;
        end else begin
            if (fifo_flush) begin
                wr_addr <= user_read_addr_r;
                empty   <= ~user_valid_r;
            end else begin

                if (avm_data_valid) begin
                    wr_addr <= wr_addr + (1 << MBYTE_SELECT_BITS);
                end

                empty <= empty & ~user_valid;
            end
        end
    end

    assign user_read_addr_word   = (user_read_addr   >> MBYTE_SELECT_BITS);
    assign user_read_addr_r_word = (user_read_addr_r >> MBYTE_SELECT_BITS);
    assign avm_read_addr_word    = (avm_read_addr    >> MBYTE_SELECT_BITS);
    assign wr_addr_word          = (wr_addr          >> MBYTE_SELECT_BITS);
    assign wr_fifo_addr = wr_addr_word & {LOG2_DEPTH{1'b1}};


    assign rd_fifo_addr = wait_for_read_int_r ? (user_read_addr_r_word & {LOG2_DEPTH{1'b1}}) : 
                                                (user_read_addr_word   & {LOG2_DEPTH{1'b1}}) ;

    assign fifo_addr_diff = {1'b0, avm_read_addr_word} - {1'b0, user_read_addr_r_word};



    always @(posedge clk) begin
        if (avm_data_valid) begin
            mem[wr_fifo_addr] <= avm_data;
        end

        if (!i_stall) begin
            fifo_data_out <= mem[rd_fifo_addr];
        end
    end




    assign user_data_out = fifo_data_out;


    assign fifo_high_addr = avm_read_addr;







    assign wait_for_read_int = (user_read_addr_word >= wr_addr_word);


    always @(posedge clk or posedge reset) begin
        if (reset) begin
            wait_for_read_int_r <= 0;

        end else begin
            wait_for_read_int_r  <= flush_external ? 0 : ( flush_internal | (wait_for_read_int_r ? ((user_read_addr_r_word >= wr_addr_word) | i_stall) : wait_for_read_int));


        end
    end
    assign wait_for_read = wait_for_read_int_r;



    always @(posedge clk or posedge reset) begin
        if (reset) begin
            avm_read_addr  <= 0;
            avm_burst_size <= 0;
            avm_read       <= 0;
            num_words_in_fifo <= 0;
            fifo_addr_diff_overflow <= 0;
            avm_ctrl_state    <= 0;
            avm_read_success_r <= 0;
        end else begin

            if (fifo_flush) begin
                num_words_in_fifo <= 0;
                fifo_addr_diff_overflow <= 0;
                avm_ctrl_state    <= 0;
                avm_read          <= user_valid_r;
                avm_read_addr     <= user_read_addr_r;
                avm_burst_size    <= (first_burst_boundary_word_address & 1) ? 1 : (MAXBURSTCOUNT - first_burst_boundary_word_address);
                avm_read_success_r <= 0;
            end else begin
                avm_read_addr  <= (avm_read_addr + (avm_read_success ? (avm_burst_size << MBYTE_SELECT_BITS) : 0));
                avm_burst_size <= avm_read_success_r ? (MAXBURSTCOUNT - avm_burst_boundary_word_address) : avm_burst_size;
                num_words_in_fifo <= fifo_addr_diff[LOG2_DEPTH - 1 : 0];
                fifo_addr_diff_overflow <= fifo_addr_diff[AWIDTH - MBYTE_SELECT_BITS - 1];

                avm_ctrl_state <= avm_ctrl_state[1] ? 0 : (avm_ctrl_state + 1);
                avm_read <= (avm_ctrl_state == 2) & !empty & (fifo_addr_diff_overflow | (num_words_in_fifo < (DEPTH - MAXBURSTCOUNT)));
                avm_read_success_r <= avm_read_success;
            end

        end
    end


    generate
        if(BURSTCOUNT_WIDTH == 1) begin

            assign first_burst_boundary_word_address = 0;
            assign avm_burst_boundary_word_address = 0;
        end else begin
            assign first_burst_boundary_word_address = (user_read_addr_r >> MBYTE_SELECT_BITS) & {(BURSTCOUNT_WIDTH - 1){1'b1}};
            assign avm_burst_boundary_word_address   = (avm_read_addr >> MBYTE_SELECT_BITS)    & {(BURSTCOUNT_WIDTH - 1){1'b1}};
        end
    endgenerate

    assign avm_read_success = avm_read & avm_ready;

endmodule