data/full_repos/permissive/203526788/GoBoard/BetterDebouncer/BetterDebouncer.v
1: b'%Error: data/full_repos/permissive/203526788/GoBoard/BetterDebouncer/BetterDebouncer.v:4: Cannot find include file: ../D-FlipFlop/DFF.v\n`include "../D-FlipFlop/DFF.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203526788/GoBoard/BetterDebouncer,data/full_repos/permissive/203526788/../D-FlipFlop/DFF.v\n             data/full_repos/permissive/203526788/GoBoard/BetterDebouncer,data/full_repos/permissive/203526788/../D-FlipFlop/DFF.v.v\n             data/full_repos/permissive/203526788/GoBoard/BetterDebouncer,data/full_repos/permissive/203526788/../D-FlipFlop/DFF.v.sv\n             ../D-FlipFlop/DFF.v\n             ../D-FlipFlop/DFF.v.v\n             ../D-FlipFlop/DFF.v.sv\n             obj_dir/../D-FlipFlop/DFF.v\n             obj_dir/../D-FlipFlop/DFF.v.v\n             obj_dir/../D-FlipFlop/DFF.v.sv\n%Error: Exiting due to 1 error(s)\n'
module BetterDebouncer (
	input CLK,
	input INPUT_BUT,
	output reg OUTPUT
	);

wire slowClock;
wire Q1, Q2, Q2_bar;

ClockDivider #(.FREQ(500)) u1(CLK, slowClock);

DFF d1(slowClock, INPUT_BUT, Q1);
DFF d2(slowClock, Q1, Q2);

assign Q2_bar = ~Q2;
assign OUTPUT = Q1 & Q2_bar;


endmodule
module BetterDebouncer (
	input CLK,
	input INPUT_BUT,
	output reg OUTPUT
	);


wire slowClock;
wire Q1, Q2, Q2_bar;

ClockDivider #(.FREQ(500)) u1(CLK, slowClock);

DFF d1(slowClock, INPUT_BUT, Q1);
DFF d2(slowClock, Q1, Q2);

assign Q2_bar = ~Q2;
assign OUTPUT = Q1 & Q2_bar;


endmodule