data/full_repos/permissive/119715647/sim/gameFunct/control.v
 line:23: before: "if"
1: b'%Error: data/full_repos/permissive/119715647/sim/gameFunct/control.v:23: syntax error, unexpected if, expecting endcase\n     if(lineNum > 6) begin\n     ^~\n%Error: data/full_repos/permissive/119715647/sim/gameFunct/control.v:27: syntax error, unexpected begin, expecting assert or assume or cover or restrict\n    IDLE: begin\n          ^~~~~\n%Error: Cannot continue\n'
module control(clk, rst, update, enable, lineNum);
	input clk, rst, update;
	input [7:0] newBlockLoc;
	output reg enable;
	output reg [2:0] lineNum;
	
	reg State;
	parameter INIT = 0, IDLE = 1;
		
	always @(posedge clk) begin
		if(rst == 0) begin
			lineNum <= 0;
			State <= INIT;
		end
		else begin
			case (State)
				INIT: begin
					enable = 1;
					if(update == 1) begin
							lineNum <= lineNum + 1;
						end	
					end
					if(lineNum > 6) begin
						State <= IDLE;
					end
				end
				IDLE: begin
					lineNum <= 0;
					enable = 0;
				end
				default: begin
					State <= INIT;
				end			
			endcase
		end
	end
endmodule
module control(clk, rst, update, enable, lineNum);

	input clk, rst, update;
	input [7:0] newBlockLoc;
	output reg enable;
	output reg [2:0] lineNum;
	
	reg State;
	parameter INIT = 0, IDLE = 1;
		
	always @(posedge clk) begin
		if(rst == 0) begin
			lineNum <= 0;
			State <= INIT;
		end
		else begin
			case (State)
				INIT: begin
					enable = 1;
					if(update == 1) begin
							lineNum <= lineNum + 1;
						end	
					end
					if(lineNum > 6) begin
						State <= IDLE;
					end
				end
				IDLE: begin
					lineNum <= 0;
					enable = 0;
				end
				default: begin
					State <= INIT;
				end			
			endcase
		end
	end
endmodule