data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interrupt.v
1: b'%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interrupt.v:65: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                                           : ... In instance interrupt\n  count<=15\'h0;\n       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interrupt.v:73: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                                           : ... In instance interrupt\n   count<=15\'d0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Mips/MultiCycleWithPipeline-Mips/interrupt.v:70: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'15\'h1f4\' generates 15 bits.\n                                                                                                           : ... In instance interrupt\n  if(count==15\'d500)\n          ^~\n%Error: Exiting due to 3 warning(s)\n'
module interrupt(
	input clk,
	input rst_n,
	
	input buttonint,
	input syscall,
	
	input RTI,
	
	output reg to_syscall,
	output reg to_button,
	
	output reg start_int,
	output reg [31:0] int_id
);


always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		to_syscall<=0;
		to_button<=0;
	end
	else
	begin
		to_syscall<=syscall;
		to_button<=buttonint;
	end
end

reg has_int;

reg citai;



reg [15:0] count;
reg resetflag;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		count<=15'h0;
		resetflag<=0;
	end
	else if(has_int)
	begin
		if(count==15'd500)
		begin
			resetflag<=1;
			count<=15'd0;
		end
		else
		begin
			resetflag<=0;
			count<=count+15'h1;
		end
	end
	else
	begin
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		has_int<=0;
		start_int<=0;
		int_id<=0;
	end
	else if(!citai)
	begin
		if(buttonint)
		begin
			int_id<=32'h4;
			has_int<=1;
			start_int<=1;
		end
		else if(syscall)
		begin
			int_id<=32'h0;
			has_int<=1;
			start_int<=1;
		end
		else
		begin
		end
	end
	else
	begin
		if(RTI)
			has_int<=0;
		else if(resetflag)
			has_int<=0;
		else
			has_int<=citai;
		start_int<=0;
	end
end

always@(*)
begin
	citai=has_int;
end


endmodule
module interrupt(
	input clk,
	input rst_n,
	
	input buttonint,
	input syscall,
	
	input RTI,
	
	output reg to_syscall,
	output reg to_button,
	
	output reg start_int,
	output reg [31:0] int_id
);



always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		to_syscall<=0;
		to_button<=0;
	end
	else
	begin
		to_syscall<=syscall;
		to_button<=buttonint;
	end
end

reg has_int;

reg citai;



reg [15:0] count;
reg resetflag;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		count<=15'h0;
		resetflag<=0;
	end
	else if(has_int)
	begin
		if(count==15'd500)
		begin
			resetflag<=1;
			count<=15'd0;
		end
		else
		begin
			resetflag<=0;
			count<=count+15'h1;
		end
	end
	else
	begin
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		has_int<=0;
		start_int<=0;
		int_id<=0;
	end
	else if(!citai)
	begin
		if(buttonint)
		begin
			int_id<=32'h4;
			has_int<=1;
			start_int<=1;
		end
		else if(syscall)
		begin
			int_id<=32'h0;
			has_int<=1;
			start_int<=1;
		end
		else
		begin
		end
	end
	else
	begin
		if(RTI)
			has_int<=0;
		else if(resetflag)
			has_int<=0;
		else
			has_int<=citai;
		start_int<=0;
	end
end

always@(*)
begin
	citai=has_int;
end


endmodule