data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:616: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:616: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:619: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_left\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n    out[63:32] <= out_left;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:623: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_right\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n    out[31:0] <= out_right;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:625: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:625: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:628: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  {temp[0], temp[31:1]} = out_left & key_left;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:593: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:593: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:596: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_left\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n    out[63:32] <= out_left;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:600: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_right\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n    out[31:0] <= out_right;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:602: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:602: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:604: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  {temp[0], temp[31:1]} = in_left & key_left;\n                                ^\n%Error: Exiting due to 14 warning(s)\n'
module camellia( Kin, Din, Dout, Krdy, Drdy, EncDec, RSTn, EN, CLK, BSY, Kvld, Dvld );
  input         CLK, RSTn, EN;
  input         EncDec;
  input         Drdy, Krdy;
  input [127:0] Din, Kin;

  output [127:0] Dout;
  output reg BSY, Kvld, Dvld;


  parameter ST_IDLE                = 4'h0;
  parameter ST_IDLE_READY          = 4'h1;


  parameter ST_KEY_GET             = 4'h3;
  parameter ST_KEY_F_FUNC          = 4'h4;
  parameter ST_KEY_XOR             = 4'h5;


  parameter ST_RANDOMIZE_GET         = 4'h7;
  parameter ST_RANDOMIZE_INITIAL_XOR = 4'h8;
  parameter ST_RANDOMIZE_FINAL_XOR   = 4'h9;
  parameter ST_RANDOMIZE_F_FUNC      = 4'ha;
  parameter ST_RANDOMIZE_FL_1        = 4'hb;
  parameter ST_RANDOMIZE_FL_2        = 4'hc;

  reg Dvld_reg, Kvld_reg;
  always @(Dvld_reg)
  begin
    Dvld <= Dvld_reg;
  end
  always @(Kvld_reg)
  begin
    Kvld <= Kvld_reg;
  end

  wire [127:0] 	 kl, ka;
  wire [127:0] 	 ka_in;
  wire [3:0] 	 state;
  wire [4:0] 	 round;


  always @(posedge CLK) begin
    if(RSTn == 1'b0)
      Dvld_reg <= 1'b0;
    else if( EN == 1'b1 )
      if( state == ST_RANDOMIZE_FINAL_XOR )
	Dvld_reg <= 1'b1;
      else
	Dvld_reg <= 1'b0;
  end


  always @(posedge CLK) begin
    if(RSTn == 1'b0)
      Kvld_reg <= 1'b0;
    else if( EN == 1'b1 )
      if( (state == ST_KEY_F_FUNC) && (round ==5'h04) )
	Kvld_reg <= 1'b1;
      else
  	Kvld_reg <= 1'b0;
  end

  always @(state)
  begin
    BSY <= (state == ST_IDLE || state == ST_IDLE_READY) ? 0 : 1;
  end

  Camellia_sequencer Camellia_sequencer( .state (state[3:0]),
					 .round (round[4:0]),
					 .CLK	  (CLK),
					 .EN    (EN), 
					 .RSTn  (RSTn),
					 .Drdy  (Drdy),
					 .Krdy  (Krdy) );

  Camellia_key_scheduler Camellia_key_scheduler( .kl_in (Kin),
						 .kl    (kl[127:0]),
						 .ka    (ka[127:0]),
						 .CLK   (CLK),
						 .EN    (EN), 
						 .RSTn  (RSTn),
						 .state (state[3:0]),
						 .round (round[4:0]),
						 .ka_in (ka_in[127:0]),
						 .EncDec(EncDec) );

  Camellia_randomize Camellia_randomize( .ka_out (ka_in),
					 .Dout   (Dout[127:0]),
					 .CLK    (CLK),
					 .EN     (EN), 
					 .RSTn   (RSTn),
					 .state  (state[3:0]),
					 .round  (round[4:0]),
					 .Din    (Din[127:0]),
					 .Kin    (Kin[127:0]),
					 .kl     (kl[127:0]),
					 .ka     (ka[127:0]),
					 .EncDec (EncDec) );
endmodule
module camellia( Kin, Din, Dout, Krdy, Drdy, EncDec, RSTn, EN, CLK, BSY, Kvld, Dvld );

  input         CLK, RSTn, EN;
  input         EncDec;
  input         Drdy, Krdy;
  input [127:0] Din, Kin;

  output [127:0] Dout;
  output reg BSY, Kvld, Dvld;


  parameter ST_IDLE                = 4'h0;
  parameter ST_IDLE_READY          = 4'h1;


  parameter ST_KEY_GET             = 4'h3;
  parameter ST_KEY_F_FUNC          = 4'h4;
  parameter ST_KEY_XOR             = 4'h5;


  parameter ST_RANDOMIZE_GET         = 4'h7;
  parameter ST_RANDOMIZE_INITIAL_XOR = 4'h8;
  parameter ST_RANDOMIZE_FINAL_XOR   = 4'h9;
  parameter ST_RANDOMIZE_F_FUNC      = 4'ha;
  parameter ST_RANDOMIZE_FL_1        = 4'hb;
  parameter ST_RANDOMIZE_FL_2        = 4'hc;

  reg Dvld_reg, Kvld_reg;
  always @(Dvld_reg)
  begin
    Dvld <= Dvld_reg;
  end
  always @(Kvld_reg)
  begin
    Kvld <= Kvld_reg;
  end

  wire [127:0] 	 kl, ka;
  wire [127:0] 	 ka_in;
  wire [3:0] 	 state;
  wire [4:0] 	 round;


  always @(posedge CLK) begin
    if(RSTn == 1'b0)
      Dvld_reg <= 1'b0;
    else if( EN == 1'b1 )
      if( state == ST_RANDOMIZE_FINAL_XOR )
	Dvld_reg <= 1'b1;
      else
	Dvld_reg <= 1'b0;
  end


  always @(posedge CLK) begin
    if(RSTn == 1'b0)
      Kvld_reg <= 1'b0;
    else if( EN == 1'b1 )
      if( (state == ST_KEY_F_FUNC) && (round ==5'h04) )
	Kvld_reg <= 1'b1;
      else
  	Kvld_reg <= 1'b0;
  end

  always @(state)
  begin
    BSY <= (state == ST_IDLE || state == ST_IDLE_READY) ? 0 : 1;
  end

  Camellia_sequencer Camellia_sequencer( .state (state[3:0]),
					 .round (round[4:0]),
					 .CLK	  (CLK),
					 .EN    (EN), 
					 .RSTn  (RSTn),
					 .Drdy  (Drdy),
					 .Krdy  (Krdy) );

  Camellia_key_scheduler Camellia_key_scheduler( .kl_in (Kin),
						 .kl    (kl[127:0]),
						 .ka    (ka[127:0]),
						 .CLK   (CLK),
						 .EN    (EN), 
						 .RSTn  (RSTn),
						 .state (state[3:0]),
						 .round (round[4:0]),
						 .ka_in (ka_in[127:0]),
						 .EncDec(EncDec) );

  Camellia_randomize Camellia_randomize( .ka_out (ka_in),
					 .Dout   (Dout[127:0]),
					 .CLK    (CLK),
					 .EN     (EN), 
					 .RSTn   (RSTn),
					 .state  (state[3:0]),
					 .round  (round[4:0]),
					 .Din    (Din[127:0]),
					 .Kin    (Kin[127:0]),
					 .kl     (kl[127:0]),
					 .ka     (ka[127:0]),
					 .EncDec (EncDec) );
endmodule