data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v
1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:3: Cannot find include file: sm_config.vh\n`include "sm_config.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102870077/engine/static/school_mips/mmio,data/full_repos/permissive/102870077/sm_config.vh\n             data/full_repos/permissive/102870077/engine/static/school_mips/mmio,data/full_repos/permissive/102870077/sm_config.vh.v\n             data/full_repos/permissive/102870077/engine/static/school_mips/mmio,data/full_repos/permissive/102870077/sm_config.vh.sv\n             sm_config.vh\n             sm_config.vh.v\n             sm_config.vh.sv\n             obj_dir/sm_config.vh\n             obj_dir/sm_config.vh.v\n             obj_dir/sm_config.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:20: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    input  [`SM_GPIO_WIDTH - 1:0] gpioInput,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:21: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    output [`SM_GPIO_WIDTH - 1:0] gpioOutput\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:23: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    wire   [`SM_GPIO_WIDTH - 1:0] gpioIn;     \n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:25: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    wire   [`SM_GPIO_WIDTH - 1:0] gpioOut;    \n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:27: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    assign gpioOut   = bWData [`SM_GPIO_WIDTH - 1:0];\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:30: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    sm_debouncer   #(.SIZE(`SM_GPIO_WIDTH)) debounce(clk, gpioInput, gpioIn);\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:31: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    sm_register_we #(.SIZE(`SM_GPIO_WIDTH)) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:33: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;\n                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:33: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;\n                                                ^\n%Error: Exiting due to 10 error(s)\n'
module sm_gpio
(

    input             clk,
    input             rst_n,
    input             bSel,
    input      [31:0] bAddr,
    input             bWrite,
    input      [31:0] bWData,
    output reg [31:0] bRData,


    input  [`SM_GPIO_WIDTH - 1:0] gpioInput,
    output [`SM_GPIO_WIDTH - 1:0] gpioOutput
);
    wire   [`SM_GPIO_WIDTH - 1:0] gpioIn;
    wire                          gpioOutWe;
    wire   [`SM_GPIO_WIDTH - 1:0] gpioOut;

    assign gpioOut   = bWData [`SM_GPIO_WIDTH - 1:0];
    assign gpioOutWe = bSel & bWrite & (bAddr[3:0] == `SM_GPIO_REG_OUTPUT);

    sm_debouncer   #(.SIZE(`SM_GPIO_WIDTH)) debounce(clk, gpioInput, gpioIn);
    sm_register_we #(.SIZE(`SM_GPIO_WIDTH)) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);

    localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;

    always @ (*)
        case(bAddr[3:0])
            default              : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn  };
            `SM_GPIO_REG_INPUT   : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn  };
            `SM_GPIO_REG_OUTPUT  : bRData = { { BLANK_WIDTH {1'b0}}, gpioOut };
        endcase

endmodule
module sm_gpio
(

    input             clk,
    input             rst_n,
    input             bSel,
    input      [31:0] bAddr,
    input             bWrite,
    input      [31:0] bWData,
    output reg [31:0] bRData,


    input  [`SM_GPIO_WIDTH - 1:0] gpioInput,
    output [`SM_GPIO_WIDTH - 1:0] gpioOutput
);

    wire   [`SM_GPIO_WIDTH - 1:0] gpioIn;
    wire                          gpioOutWe;
    wire   [`SM_GPIO_WIDTH - 1:0] gpioOut;

    assign gpioOut   = bWData [`SM_GPIO_WIDTH - 1:0];
    assign gpioOutWe = bSel & bWrite & (bAddr[3:0] == `SM_GPIO_REG_OUTPUT);

    sm_debouncer   #(.SIZE(`SM_GPIO_WIDTH)) debounce(clk, gpioInput, gpioIn);
    sm_register_we #(.SIZE(`SM_GPIO_WIDTH)) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);

    localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;

    always @ (*)
        case(bAddr[3:0])
            default              : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn  };
            `SM_GPIO_REG_INPUT   : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn  };
            `SM_GPIO_REG_OUTPUT  : bRData = { { BLANK_WIDTH {1'b0}}, gpioOut };
        endcase

endmodule