data/full_repos/permissive/183843067/passwd.v
1: b'%Warning-WIDTH: data/full_repos/permissive/183843067/passwd.v:195: Input port connection \'K\' expects 10 bits on the pin connection, but pin connection\'s VARREF \'SYS_K\' generates 1 bits.\n                                                                 : ... In instance Top\nPasswd PASS(.CLK(SYS_CLK),.del(SYS_DEL),.K(SYS_K),.lock(SYS_LOCK),.Data(USER_DATA));\n                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Top(
  input SYS_CLK,
  input SYS_DEL,
  input SYS_K,
  output SYS_LOCK,
  output wire [3:0] SYS_DATA,
  output wire [3:0] SYS_CTRL
);
wire [15:0] USER_DATA;
Passwd PASS(.CLK(SYS_CLK),.del(SYS_DEL),.K(SYS_K),.lock(SYS_LOCK),.Data(USER_DATA));
Display DS(.DataIn(USER_DATA),.CLK(SYS_CLK),.Data(SYS_DATA),.Ctrl(SYS_CTRL));
endmodule
module Top(
  input SYS_CLK,
  input SYS_DEL,
  input SYS_K,
  output SYS_LOCK,
  output wire [3:0] SYS_DATA,
  output wire [3:0] SYS_CTRL
);

wire [15:0] USER_DATA;
Passwd PASS(.CLK(SYS_CLK),.del(SYS_DEL),.K(SYS_K),.lock(SYS_LOCK),.Data(USER_DATA));
Display DS(.DataIn(USER_DATA),.CLK(SYS_CLK),.Data(SYS_DATA),.Ctrl(SYS_CTRL));
endmodule