data/full_repos/permissive/174369527/UART/src/top_module_tb.v
 line:429: before: "r_rst_uartrx_n"
1: b'%Error: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:1: Cannot find include file: ../src/top_module.v\n`include "../src/top_module.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174369527/UART/src,data/full_repos/permissive/174369527/../src/top_module.v\n             data/full_repos/permissive/174369527/UART/src,data/full_repos/permissive/174369527/../src/top_module.v.v\n             data/full_repos/permissive/174369527/UART/src,data/full_repos/permissive/174369527/../src/top_module.v.sv\n             ../src/top_module.v\n             ../src/top_module.v.v\n             ../src/top_module.v.sv\n             obj_dir/../src/top_module.v\n             obj_dir/../src/top_module.v.v\n             obj_dir/../src/top_module.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n       #1 data_cnt <= data_cnt + 1;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n      #1 uartrx_cnt <= uartrx_cnt + 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n      #1 uartrx_cnt <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n      #1 uartrx_cnt <= uartrx_cnt + 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n     #1 r_uartrx_state <= s_IDLE;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #1 r_Rx_Serial <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #(c_BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #1 r_Rx_Serial <= i_Data[ii];\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #(c_BIT_PERIOD);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n #1 r_Rx_Serial <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n #(c_BIT_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n    #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;\n    ^\n%Error: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:134: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("mydump.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:135: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, UUT);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n   #9000000\n   ^\n%Error: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:145: syntax error, unexpected \'@\'\n      @(posedge r_Clock);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n   #9000000\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/UART/src/top_module_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n   #9000000\n   ^\n%Error: Exiting due to 4 error(s), 16 warning(s)\n'
module top_module_tb ();


  parameter c_CLOCK_PERIOD_NS = 50;
  parameter c_CLKS_PER_BIT    = 868;
  parameter c_BIT_PERIOD      = 43400;

  reg r_Clock = 0;
  reg r_Rx_Serial = 1;
  wire w_Tx_Serial;
  wire [7:0] w_led;
  reg [4:0] r_btn;
  reg [7:0] r_sw;


	reg [7:0] r_tmp_rx = 0;
	reg r_rst_uartrx_n = 1'b0;
	parameter s_IDLE = 2'b00;
	parameter s_START = 2'b01;
	parameter s_DATA = 2'b11;
	parameter s_STOP = 2'b10;
	parameter CLOCK_FREQ = 100_000_000;
	parameter BAUD_RATE = 115_200;
	parameter SAMPLE_FULL_BIT = (CLOCK_FREQ / BAUD_RATE);
	parameter SAMPLE_HALF_BIT = (SAMPLE_FULL_BIT / 2);
	reg [2:0] r_uartrx_state = s_IDLE;
	integer uartrx_cnt = 0;
	integer data_cnt = 0;

	always @ (posedge r_Clock or r_rst_uartrx_n)
	begin
		if (r_rst_uartrx_n==1'b0) begin
			r_uartrx_state <= s_IDLE;
			uartrx_cnt <= 0;
		end else begin
			case (r_uartrx_state)
				s_IDLE:
				begin
					if (w_Tx_Serial==1'b0) begin

						r_uartrx_state <= s_START;
						uartrx_cnt <= 0;
					end
				end
				s_START:
				begin
					if (uartrx_cnt == SAMPLE_HALF_BIT) begin
						uartrx_cnt <= 0;
						if (w_Tx_Serial==1'b0) begin

							r_uartrx_state <= s_DATA;
						end else begin

							r_uartrx_state <= s_IDLE;
						end
					end else begin
						uartrx_cnt <= uartrx_cnt + 1;
					end
				end
				s_DATA:
				begin
					if (uartrx_cnt == SAMPLE_FULL_BIT) begin
						uartrx_cnt <= 0;
						r_tmp_rx <= {w_Tx_Serial, r_tmp_rx[7:1]};
						if (data_cnt == 7) begin
							data_cnt <= 0;
							r_uartrx_state <= s_STOP;
						end else begin
							#1 data_cnt <= data_cnt + 1;

						end
					end else begin
						#1 uartrx_cnt <= uartrx_cnt + 1;
					end
				end
				s_STOP:
				begin
					if (uartrx_cnt == SAMPLE_FULL_BIT) begin
						$display("TB: UART Received %d", r_tmp_rx);
						#1 uartrx_cnt <= 0;
						r_uartrx_state <= s_IDLE;
					end else begin
						#1 uartrx_cnt <= uartrx_cnt + 1;
					end
				end
				default:
				begin
					#1 r_uartrx_state <= s_IDLE;
				end
			endcase
		end
	end

  task UART_WRITE_BYTE;
    input [7:0] i_Data;
    integer     ii;
    begin
	$display("TB: UART Send => Data = %d", i_Data);

	#1 r_Rx_Serial <= 1'b0;
	#(c_BIT_PERIOD);
	#1000;

	for (ii=0; ii<8; ii=ii+1)
	begin
		#1 r_Rx_Serial <= i_Data[ii];
		#(c_BIT_PERIOD);
	end

	#1 r_Rx_Serial <= 1'b1;
	#(c_BIT_PERIOD);
	end
  endtask

	top_module #(.CLKS_PER_BIT(868)) UUT
	(
	 .clk(r_Clock),
	 .Led(w_led),
	 .btn(r_btn),
	 .Rx(r_Rx_Serial),
	 .Tx(w_Tx_Serial),
	 .sw(r_sw)
	);

  always
    #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;

  initial
    begin
	$dumpfile("mydump.vcd");
	$dumpvars(0, UUT);
	$display("Start simulation");

	  r_btn = 5'b10010;
	  r_sw = 8'hAB;
	  r_rst_uartrx_n = 1'b1;


	  #9000000
	  r_btn[0] = 1'b1;
      @(posedge r_Clock);
      @(posedge r_Clock);
	  r_btn[0] = 1'b0;
       

	  #9000000
      UART_WRITE_BYTE(8'h3F);
	  #9000000
             
	  $finish;
    end
endmodule
module top_module_tb ();



  parameter c_CLOCK_PERIOD_NS = 50;
  parameter c_CLKS_PER_BIT    = 868;
  parameter c_BIT_PERIOD      = 43400;

  reg r_Clock = 0;
  reg r_Rx_Serial = 1;
  wire w_Tx_Serial;
  wire [7:0] w_led;
  reg [4:0] r_btn;
  reg [7:0] r_sw;


	reg [7:0] r_tmp_rx = 0;
	reg r_rst_uartrx_n = 1'b0;
	parameter s_IDLE = 2'b00;
	parameter s_START = 2'b01;
	parameter s_DATA = 2'b11;
	parameter s_STOP = 2'b10;
	parameter CLOCK_FREQ = 100_000_000;
	parameter BAUD_RATE = 115_200;
	parameter SAMPLE_FULL_BIT = (CLOCK_FREQ / BAUD_RATE);
	parameter SAMPLE_HALF_BIT = (SAMPLE_FULL_BIT / 2);
	reg [2:0] r_uartrx_state = s_IDLE;
	integer uartrx_cnt = 0;
	integer data_cnt = 0;

	always @ (posedge r_Clock or r_rst_uartrx_n)
	begin
		if (r_rst_uartrx_n==1'b0) begin
			r_uartrx_state <= s_IDLE;
			uartrx_cnt <= 0;
		end else begin
			case (r_uartrx_state)
				s_IDLE:
				begin
					if (w_Tx_Serial==1'b0) begin

						r_uartrx_state <= s_START;
						uartrx_cnt <= 0;
					end
				end
				s_START:
				begin
					if (uartrx_cnt == SAMPLE_HALF_BIT) begin
						uartrx_cnt <= 0;
						if (w_Tx_Serial==1'b0) begin

							r_uartrx_state <= s_DATA;
						end else begin

							r_uartrx_state <= s_IDLE;
						end
					end else begin
						uartrx_cnt <= uartrx_cnt + 1;
					end
				end
				s_DATA:
				begin
					if (uartrx_cnt == SAMPLE_FULL_BIT) begin
						uartrx_cnt <= 0;
						r_tmp_rx <= {w_Tx_Serial, r_tmp_rx[7:1]};
						if (data_cnt == 7) begin
							data_cnt <= 0;
							r_uartrx_state <= s_STOP;
						end else begin
							#1 data_cnt <= data_cnt + 1;

						end
					end else begin
						#1 uartrx_cnt <= uartrx_cnt + 1;
					end
				end
				s_STOP:
				begin
					if (uartrx_cnt == SAMPLE_FULL_BIT) begin
						$display("TB: UART Received %d", r_tmp_rx);
						#1 uartrx_cnt <= 0;
						r_uartrx_state <= s_IDLE;
					end else begin
						#1 uartrx_cnt <= uartrx_cnt + 1;
					end
				end
				default:
				begin
					#1 r_uartrx_state <= s_IDLE;
				end
			endcase
		end
	end

  task UART_WRITE_BYTE;
    input [7:0] i_Data;
    integer     ii;
    begin
	$display("TB: UART Send => Data = %d", i_Data);

	#1 r_Rx_Serial <= 1'b0;
	#(c_BIT_PERIOD);
	#1000;

	for (ii=0; ii<8; ii=ii+1)
	begin
		#1 r_Rx_Serial <= i_Data[ii];
		#(c_BIT_PERIOD);
	end

	#1 r_Rx_Serial <= 1'b1;
	#(c_BIT_PERIOD);
	end
  endtask

	top_module #(.CLKS_PER_BIT(868)) UUT
	(
	 .clk(r_Clock),
	 .Led(w_led),
	 .btn(r_btn),
	 .Rx(r_Rx_Serial),
	 .Tx(w_Tx_Serial),
	 .sw(r_sw)
	);

  always
    #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;

  initial
    begin
	$dumpfile("mydump.vcd");
	$dumpvars(0, UUT);
	$display("Start simulation");

	  r_btn = 5'b10010;
	  r_sw = 8'hAB;
	  r_rst_uartrx_n = 1'b1;


	  #9000000
	  r_btn[0] = 1'b1;
      @(posedge r_Clock);
      @(posedge r_Clock);
	  r_btn[0] = 1'b0;
       

	  #9000000
      UART_WRITE_BYTE(8'h3F);
	  #9000000
             
	  $finish;
    end
endmodule