data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/shift_reg_8192/rtl/shift_reg_8192.v
data/verilator_xmls/b2cb108d-1d50-4420-aa55-79162b8ce79f.xml
module shift_reg_8192 #( parameter size = 8191 ) (shift_in, clk, shift_out);


   input   shift_in;
   input   clk;
   output  shift_out;
   
   reg [ size:0 ] shift;
   
    always @ (posedge clk)
     begin
	  shift = { shift[size-1:0] , shift_in } ;	
     end
   
   assign shift_out = shift[size];   
   
endmodule
module shift_reg_8192 #( parameter size = 8191 ) (shift_in, clk, shift_out);



   input   shift_in;
   input   clk;
   output  shift_out;
   
   reg [ size:0 ] shift;
   
    always @ (posedge clk)
     begin
	  shift = { shift[size-1:0] , shift_in } ;	
     end
   
   assign shift_out = shift[size];   
   
endmodule