data/full_repos/permissive/187199324/stannel/Receive_tb.v
 line:98: before: "begin"
1: b'%Error: data/full_repos/permissive/187199324/stannel/Receive_tb.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Receive_tb.v:6: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = clk !== 1\'b1;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/187199324/stannel/Receive_tb.v:11: Define or directive not defined: \'`ADDRESS_BITS\'\n  localparam addrBits = `ADDRESS_BITS;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive_tb.v:11: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam addrBits = `ADDRESS_BITS;\n                                     ^\n%Error: data/full_repos/permissive/187199324/stannel/Receive_tb.v:12: Define or directive not defined: \'`DATA_BITS\'\n  localparam dataBits = `DATA_BITS;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive_tb.v:12: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam dataBits = `DATA_BITS;\n                                  ^\n%Error: data/full_repos/permissive/187199324/stannel/Receive_tb.v:62: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Receive_tb.v:70: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive_tb.v:80: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Receive_tb.v:90: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive_tb.v:95: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("Receive_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Receive_tb.v:96: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, Receive_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Receive_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n    #3 receiveNoSender;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Receive_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #2 receiveSomeSender;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Receive_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #2 $finish;\n    ^\n%Error: data/full_repos/permissive/187199324/stannel/Receive_tb.v:102: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n'
module Receive_tb();

  reg clk;
  always #1 clk = clk !== 1'b1;


  parameter romFile = "zeroes.hex";

  localparam addrBits = `ADDRESS_BITS;
  localparam dataBits = `DATA_BITS;

  reg  [addrBits-1:0] address;
  reg  [dataBits-1:0] dataIn;
  wire [dataBits-1:0] dataOut;
  reg                 readWriteMode;

  IceRam #(.addrBits(addrBits), .dataBits(dataBits), .romFile(romFile)) memory (
    .clk          (clk),
    .address      (address),
    .readWriteMode(readWriteMode),
    .dataIn       (dataIn),
    .dataOut      (dataOut)
  );


  reg                reset = 0;
  reg [addrBits-1:0] channel = 0;
  reg [dataBits-1:0] message;
  reg [addrBits-1:0] rxPid;

  reg                finished;
  reg                shouldScheduleSender;
  reg                shouldDescheduleReceiver;
  reg [addrBits-1:0] scheduleTxPid;
  reg                hasDeliveredMessage;
  reg [dataBits-1:0] deliveredMessage;

  Receive #(.addrBits(addrBits), .dataBits(dataBits)) rcv0 (
    .clk                     (clk),
    .reset                   (reset),
    .finished                (finished),
    .address                 (address),
    .readWriteMode           (readWriteMode),
    .dataOut                 (dataOut),
    .dataIn                  (dataIn),
    .channel                 (channel),
    .rxPid                   (rxPid),
    .shouldScheduleSender    (shouldScheduleSender),
    .shouldDescheduleReceiver(shouldDescheduleReceiver),
    .scheduleTxPid           (scheduleTxPid),
    .hasDeliveredMessage     (hasDeliveredMessage),
    .deliveredMessage        (deliveredMessage)
  );

  task receiveNoSender;
    begin
      reset <= 1;
      channel <= 2;
      rxPid <= 7;
      @(posedge finished)
        begin
          reset <= 0;
          if (!shouldDescheduleReceiver) $error("Expected to deschedule receiver");
          if (shouldScheduleSender) $error("Shouldn't schedule sender, both should wait");
          if (hasDeliveredMessage) $error("Shouldn't have delivered message");
          if (memory.ram[2] != rxPid) $error("Didn't write rx pid to memory");
        end
    end
  endtask

  task receiveSomeSender;
    begin
      reset <= 1;
      channel <= 8;
      memory.ram[8] = 8;
      memory.ram[9] = 42;
      rxPid <= 3;
      @(posedge finished)
        begin
          reset <= 0;
          if (shouldDescheduleReceiver) $error("Receiver should continue");
          if (!shouldScheduleSender) $error("Sender should be scheduled");
          if (scheduleTxPid != 8) $error("Scheduled tx pid not sending pid");
          if (!hasDeliveredMessage) $error("Doesn't have message");
          if (deliveredMessage != 42) $error("Delivered message not as expected");
          if (memory.ram[8] != 0) $error("Memory not zeroed");
        end
    end
  endtask


   initial begin
    $dumpfile("Receive_tb.vcd");
    $dumpvars(0, Receive_tb);

    #3 receiveNoSender;
    #2 receiveSomeSender;

    #2 $finish;
  end
endmodule
module Receive_tb();


  reg clk;
  always #1 clk = clk !== 1'b1;


  parameter romFile = "zeroes.hex";

  localparam addrBits = `ADDRESS_BITS;
  localparam dataBits = `DATA_BITS;

  reg  [addrBits-1:0] address;
  reg  [dataBits-1:0] dataIn;
  wire [dataBits-1:0] dataOut;
  reg                 readWriteMode;

  IceRam #(.addrBits(addrBits), .dataBits(dataBits), .romFile(romFile)) memory (
    .clk          (clk),
    .address      (address),
    .readWriteMode(readWriteMode),
    .dataIn       (dataIn),
    .dataOut      (dataOut)
  );


  reg                reset = 0;
  reg [addrBits-1:0] channel = 0;
  reg [dataBits-1:0] message;
  reg [addrBits-1:0] rxPid;

  reg                finished;
  reg                shouldScheduleSender;
  reg                shouldDescheduleReceiver;
  reg [addrBits-1:0] scheduleTxPid;
  reg                hasDeliveredMessage;
  reg [dataBits-1:0] deliveredMessage;

  Receive #(.addrBits(addrBits), .dataBits(dataBits)) rcv0 (
    .clk                     (clk),
    .reset                   (reset),
    .finished                (finished),
    .address                 (address),
    .readWriteMode           (readWriteMode),
    .dataOut                 (dataOut),
    .dataIn                  (dataIn),
    .channel                 (channel),
    .rxPid                   (rxPid),
    .shouldScheduleSender    (shouldScheduleSender),
    .shouldDescheduleReceiver(shouldDescheduleReceiver),
    .scheduleTxPid           (scheduleTxPid),
    .hasDeliveredMessage     (hasDeliveredMessage),
    .deliveredMessage        (deliveredMessage)
  );

  task receiveNoSender;
    begin
      reset <= 1;
      channel <= 2;
      rxPid <= 7;
      @(posedge finished)
        begin
          reset <= 0;
          if (!shouldDescheduleReceiver) $error("Expected to deschedule receiver");
          if (shouldScheduleSender) $error("Shouldn't schedule sender, both should wait");
          if (hasDeliveredMessage) $error("Shouldn't have delivered message");
          if (memory.ram[2] != rxPid) $error("Didn't write rx pid to memory");
        end
    end
  endtask

  task receiveSomeSender;
    begin
      reset <= 1;
      channel <= 8;
      memory.ram[8] = 8;
      memory.ram[9] = 42;
      rxPid <= 3;
      @(posedge finished)
        begin
          reset <= 0;
          if (shouldDescheduleReceiver) $error("Receiver should continue");
          if (!shouldScheduleSender) $error("Sender should be scheduled");
          if (scheduleTxPid != 8) $error("Scheduled tx pid not sending pid");
          if (!hasDeliveredMessage) $error("Doesn't have message");
          if (deliveredMessage != 42) $error("Delivered message not as expected");
          if (memory.ram[8] != 0) $error("Memory not zeroed");
        end
    end
  endtask


   initial begin
    $dumpfile("Receive_tb.vcd");
    $dumpvars(0, Receive_tb);

    #3 receiveNoSender;
    #2 receiveSomeSender;

    #2 $finish;
  end
endmodule