data/full_repos/permissive/117880471/HW3/d_flip_flop.v
 line:33: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:12: Unsupported: Ignoring delay on this delayed statement.\n #00 clock = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:13: Unsupported: Ignoring delay on this delayed statement.\n forever #20 clock = ~clock;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:18: Unsupported: Ignoring delay on this delayed statement.\n #00 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:19: Unsupported: Ignoring delay on this delayed statement.\n #40 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:24: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:26: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:27: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:29: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:31: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10 d = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10 $stop;\n ^\n%Error: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:38: Unsupported or unknown PLI call: $monitor\n $monitor("time=%3d, q=%b, d=%b, clock=%b, reset=%b", $time, q, d, clock, reset);\n ^~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:43: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("d_flip_flop.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/d_flip_flop.v:44: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_d_flip_flop();

reg q;
wire d, clock, reset;

d_flip_flop uut(q, d, clock, reset);

initial
begin
	#00 clock = 1'b0;
	forever #20 clock = ~clock;
end

initial
begin
	#00 reset = 1'b1;
	#40 reset = 1'b0;
end

initial
begin
	#10 d = 1'b1;
	#10 d = 1'b0;
	#10 d = 1'b1;
	#10 d = 1'b0;
	#10 d = 1'b1;
	#10 d = 1'b0;
	#10 d = 1'b1;
	#10 d = 1'b0;
	#10 d = 1'b1;
	#10 $stop;
end

initial
begin
	$monitor("time=%3d, q=%b, d=%b, clock=%b, reset=%b", $time, q, d, clock, reset);
end

initial
begin
	$dumpfile("d_flip_flop.vcd");
	$dumpvars;
end
endmodule
module tb_d_flip_flop();


reg q;
wire d, clock, reset;

d_flip_flop uut(q, d, clock, reset);

initial
begin
	#00 clock = 1'b0;
	forever #20 clock = ~clock;
end

initial
begin
	#00 reset = 1'b1;
	#40 reset = 1'b0;
end

initial
begin
	#10 d = 1'b1;
	#10 d = 1'b0;
	#10 d = 1'b1;
	#10 d = 1'b0;
	#10 d = 1'b1;
	#10 d = 1'b0;
	#10 d = 1'b1;
	#10 d = 1'b0;
	#10 d = 1'b1;
	#10 $stop;
end

initial
begin
	$monitor("time=%3d, q=%b, d=%b, clock=%b, reset=%b", $time, q, d, clock, reset);
end

initial
begin
	$dumpfile("d_flip_flop.vcd");
	$dumpvars;
end
endmodule