data/full_repos/permissive/219917900/rx_rtl_files/super_asyncFIFO.v
1: b'%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/super_asyncFIFO.v:45: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                      : ... In instance super_asyncFIFO\n        dout <= ram[radr_reg[WA-1:0]+(rd_en? 1\'b1:1\'b0)];\n                                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/super_asyncFIFO.v:45: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance super_asyncFIFO\n        dout <= ram[radr_reg[WA-1:0]+(rd_en? 1\'b1:1\'b0)];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/super_asyncFIFO.v:48: Bit extraction of array[15:0] requires 4 bit index, not 1 bits.\n                                                                                      : ... In instance super_asyncFIFO\n            dout <= ram[radr_reg[WA-1]];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/super_asyncFIFO.v:49: Unsized constant being X/Z extended to 256 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                      : ... In instance super_asyncFIFO\n    else dout<=\'hx;\n               ^~~\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/super_asyncFIFO.v:46: Operator EQ expects 40 bits on the LHS, but LHS\'s VARREF \'FWFT_mode\' generates 32 bits.\n                                                                                      : ... In instance super_asyncFIFO\n    else if (FWFT_mode == "FALSE")\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/super_asyncFIFO.v:66: Operator AND expects 5 bits on the LHS, but LHS\'s VARREF \'wr_en\' generates 1 bits.\n                                                                                      : ... In instance super_asyncFIFO\nassign next_wadr = wadr_reg + (wr_en & ~full);      \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/super_asyncFIFO.v:66: Operator NOT expects 5 bits on the LHS, but LHS\'s VARREF \'full\' generates 1 bits.\n                                                                                      : ... In instance super_asyncFIFO\nassign next_wadr = wadr_reg + (wr_en & ~full);      \n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/super_asyncFIFO.v:92: Operator SUB expects 4 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                      : ... In instance super_asyncFIFO\nassign almost_full = (wadr_reg == {!rdbinary[WA],(rdbinary[WA-1:0]-2\'d2)}) ? 1\'b1 : 1\'b0;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/super_asyncFIFO.v:109: Operator AND expects 5 bits on the LHS, but LHS\'s VARREF \'rd_en\' generates 1 bits.\n                                                                                       : ... In instance super_asyncFIFO\nassign next_radr = radr_reg + (rd_en & ~empty);     \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/super_asyncFIFO.v:109: Operator NOT expects 5 bits on the LHS, but LHS\'s VARREF \'empty\' generates 1 bits.\n                                                                                       : ... In instance super_asyncFIFO\nassign next_radr = radr_reg + (rd_en & ~empty);     \n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/super_asyncFIFO.v:135: Operator SUB expects 5 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                       : ... In instance super_asyncFIFO\nassign almost_empty = (wrbinary-2\'d2 == radr_reg) ? 1\'b1 : 1\'b0;\n                               ^\n%Error: Exiting due to 11 warning(s)\n'
module super_asyncFIFO #(parameter WA=4,WD=256,FWFT_mode="TRUE")
    (input  wire            rst
    ,input  wire            wr_clk
    ,input  wire            wr_en
    ,input  wire [WD-1:0]   din
    ,output wire            almost_full
    ,output wire            full
    ,input  wire            rd_clk
    ,input  wire            rd_en
    ,output reg [WD-1:0]    dout
    ,output wire            empty
    ,output wire            almost_empty
    );

reg  [WA:0]      wadr_reg;
reg  [WA:0]      radr_reg;
reg  [WA:0]      wptr_reg,wptr0_reg,wptr1_reg,wrbinary;
reg  [WA:0]      rptr_reg,rptr0_reg,rptr1_reg,rdbinary;
wire [WA:0]      next_wadr,next_wptr;
wire [WA:0]      next_radr,next_rptr;
reg  [WD-1:0]    ram [0:2**WA-1];

always @(posedge wr_clk) begin
    if(wr_en) ram[wadr_reg[WA-1:0]] <= din;
end



always @(posedge rd_clk) begin
    if (FWFT_mode == "TRUE")
        dout <= ram[radr_reg[WA-1:0]+(rd_en? 1'b1:1'b0)];
    else if (FWFT_mode == "FALSE")
        if (rd_en)
            dout <= ram[radr_reg[WA-1]];
    else dout<='hx;
end
    


always @(posedge wr_clk or posedge rst) begin
    if(rst) begin
        wadr_reg <= {(WA+1){1'b0}};
        wptr_reg <= {(WA+1){1'b0}};
    end else if(wr_en) begin
        wadr_reg <= next_wadr;
        wptr_reg <= next_wptr;
    end
end

assign next_wadr = wadr_reg + (wr_en & ~full);
assign next_wptr = next_wadr ^ (next_wadr>>1'b1);


always @(posedge wr_clk or posedge rst) begin
    if(rst) begin
        rptr1_reg <= {(WA+1){1'b0}};
        rptr0_reg <= {(WA+1){1'b0}};
    end else begin
        rptr1_reg <= rptr0_reg;
        rptr0_reg <= rptr_reg;
    end
end


always @* begin : READ_GRAY2BINARY
    integer j;
    for(j=WA; j>=0; j=j-1) begin
        if (j==WA)
         rdbinary[j] <= rptr1_reg[j];
        else
         rdbinary[j] <= rptr1_reg[j] ^ rdbinary[j+1];
    end
end

assign full       = (wadr_reg == {!rdbinary[WA],rdbinary[WA-1:0]}) ? 1'b1 : 1'b0;
assign almost_full = (wadr_reg == {!rdbinary[WA],(rdbinary[WA-1:0]-2'd2)}) ? 1'b1 : 1'b0;




always @(posedge rd_clk or posedge rst) begin
    if(rst) begin
        radr_reg <= {(WA+1){1'b0}};
        rptr_reg <= {(WA+1){1'b0}};
    end else if(rd_en) begin
        radr_reg <= next_radr;
        rptr_reg <= next_rptr;
    end
end

assign next_radr = radr_reg + (rd_en & ~empty);
assign next_rptr = next_radr ^ (next_radr >> 1);


always @(posedge rd_clk or posedge rst) begin
    if(rst) begin
        wptr1_reg <= {(WA+1){1'b0}};
        wptr0_reg <= {(WA+1){1'b0}};
    end else begin
        wptr1_reg <= wptr0_reg;
        wptr0_reg <= wptr_reg;
    end
end


always @* begin : WRITE_GRAY2BINARY
    integer j;
    for(j=WA; j>=0; j=j-1) begin
        if (j==WA)
            wrbinary[j] <= wptr1_reg[j];
        else
            wrbinary[j] <= wptr1_reg[j] ^ wrbinary[j+1];
    end
end

assign empty = (wrbinary == radr_reg) ? 1'b1 : 1'b0;
assign almost_empty = (wrbinary-2'd2 == radr_reg) ? 1'b1 : 1'b0;


endmodule
module super_asyncFIFO #(parameter WA=4,WD=256,FWFT_mode="TRUE")
    (input  wire            rst
    ,input  wire            wr_clk
    ,input  wire            wr_en
    ,input  wire [WD-1:0]   din
    ,output wire            almost_full
    ,output wire            full
    ,input  wire            rd_clk
    ,input  wire            rd_en
    ,output reg [WD-1:0]    dout
    ,output wire            empty
    ,output wire            almost_empty
    );


reg  [WA:0]      wadr_reg;
reg  [WA:0]      radr_reg;
reg  [WA:0]      wptr_reg,wptr0_reg,wptr1_reg,wrbinary;
reg  [WA:0]      rptr_reg,rptr0_reg,rptr1_reg,rdbinary;
wire [WA:0]      next_wadr,next_wptr;
wire [WA:0]      next_radr,next_rptr;
reg  [WD-1:0]    ram [0:2**WA-1];

always @(posedge wr_clk) begin
    if(wr_en) ram[wadr_reg[WA-1:0]] <= din;
end



always @(posedge rd_clk) begin
    if (FWFT_mode == "TRUE")
        dout <= ram[radr_reg[WA-1:0]+(rd_en? 1'b1:1'b0)];
    else if (FWFT_mode == "FALSE")
        if (rd_en)
            dout <= ram[radr_reg[WA-1]];
    else dout<='hx;
end
    


always @(posedge wr_clk or posedge rst) begin
    if(rst) begin
        wadr_reg <= {(WA+1){1'b0}};
        wptr_reg <= {(WA+1){1'b0}};
    end else if(wr_en) begin
        wadr_reg <= next_wadr;
        wptr_reg <= next_wptr;
    end
end

assign next_wadr = wadr_reg + (wr_en & ~full);
assign next_wptr = next_wadr ^ (next_wadr>>1'b1);


always @(posedge wr_clk or posedge rst) begin
    if(rst) begin
        rptr1_reg <= {(WA+1){1'b0}};
        rptr0_reg <= {(WA+1){1'b0}};
    end else begin
        rptr1_reg <= rptr0_reg;
        rptr0_reg <= rptr_reg;
    end
end


always @* begin : READ_GRAY2BINARY
    integer j;
    for(j=WA; j>=0; j=j-1) begin
        if (j==WA)
         rdbinary[j] <= rptr1_reg[j];
        else
         rdbinary[j] <= rptr1_reg[j] ^ rdbinary[j+1];
    end
end

assign full       = (wadr_reg == {!rdbinary[WA],rdbinary[WA-1:0]}) ? 1'b1 : 1'b0;
assign almost_full = (wadr_reg == {!rdbinary[WA],(rdbinary[WA-1:0]-2'd2)}) ? 1'b1 : 1'b0;




always @(posedge rd_clk or posedge rst) begin
    if(rst) begin
        radr_reg <= {(WA+1){1'b0}};
        rptr_reg <= {(WA+1){1'b0}};
    end else if(rd_en) begin
        radr_reg <= next_radr;
        rptr_reg <= next_rptr;
    end
end

assign next_radr = radr_reg + (rd_en & ~empty);
assign next_rptr = next_radr ^ (next_radr >> 1);


always @(posedge rd_clk or posedge rst) begin
    if(rst) begin
        wptr1_reg <= {(WA+1){1'b0}};
        wptr0_reg <= {(WA+1){1'b0}};
    end else begin
        wptr1_reg <= wptr0_reg;
        wptr0_reg <= wptr_reg;
    end
end


always @* begin : WRITE_GRAY2BINARY
    integer j;
    for(j=WA; j>=0; j=j-1) begin
        if (j==WA)
            wrbinary[j] <= wptr1_reg[j];
        else
            wrbinary[j] <= wptr1_reg[j] ^ wrbinary[j+1];
    end
end

assign empty = (wrbinary == radr_reg) ? 1'b1 : 1'b0;
assign almost_empty = (wrbinary-2'd2 == radr_reg) ? 1'b1 : 1'b0;


endmodule