data/full_repos/permissive/212020337/clock_base10.v
data/verilator_xmls/bad0e6ca-6f63-498b-a27e-3423c433d6de.xml
module clock(clk, clk_scale, CCLK);

output reg   clk;
input [31:0] clk_scale;
input 		 CCLK;

reg [31:0]   clkq = 0;

always @(posedge CCLK)
begin
	clkq <= clkq + 1;
	if (clkq >= clk_scale)
	begin
		clk <= ~clk;
		clkq <= 0;
	end
end

endmodule
module clock(clk, clk_scale, CCLK);


output reg   clk;
input [31:0] clk_scale;
input 		 CCLK;

reg [31:0]   clkq = 0;

always @(posedge CCLK)
begin
	clkq <= clkq + 1;
	if (clkq >= clk_scale)
	begin
		clk <= ~clk;
		clkq <= 0;
	end
end

endmodule