data/full_repos/permissive/129527056/cores/gng/ver/jtgng_video/test.v
1: b"%Error: data/full_repos/permissive/129527056/cores/gng/ver/jtgng_video/test.v:19: Cannot find file containing module: 'jtgng_timer'\njtgng_timer timers(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129527056/cores/gng/ver/jtgng_video,data/full_repos/permissive/129527056/jtgng_timer\n             data/full_repos/permissive/129527056/cores/gng/ver/jtgng_video,data/full_repos/permissive/129527056/jtgng_timer.v\n             data/full_repos/permissive/129527056/cores/gng/ver/jtgng_video,data/full_repos/permissive/129527056/jtgng_timer.sv\n             jtgng_timer\n             jtgng_timer.v\n             jtgng_timer.sv\n             obj_dir/jtgng_timer\n             obj_dir/jtgng_timer.v\n             obj_dir/jtgng_timer.sv\n%Error: data/full_repos/permissive/129527056/cores/gng/ver/jtgng_video/test.v:40: Cannot find file containing module: 'jtgng_video'\njtgng_video u_video(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/129527056/cores/gng/ver/jtgng_video/test.v:129: Cannot find file containing module: 'jtgng_rom'\njtgng_rom rom (\n^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module test(
    input           rst,
    input           SDRAM_CLK,
    input           clk,
    input           cen6,
    input           flip,
    output   [3:0]  red,
    output   [3:0]  green,
    output   [3:0]  blue,
    output          LHBL,
    output          LVBL,
    output          rom_ready
);

wire [8:0] V;
wire [8:0] H;
wire HINIT;

jtgng_timer timers(
    .clk       ( clk      ),
    .clk_en    ( cen6     ),
    .V         ( V        ),
    .H         ( H        ),
    .Hinit     ( HINIT    ),
    .LHBL      ( LHBL     ),
    .LVBL      ( LVBL     )
);

wire char_mrdy;
wire [12:0] char_addr;
wire [ 7:0] chram_dout,scram_dout;
wire [15:0] chrom_data;
wire [ 8:0] obj_AB;
wire bus_req, blen;
wire [14:0] obj_addr;
wire [15:0] obj_data;
wire [23:0] scr_dout;
wire [14:0] scr_addr;

jtgng_video u_video(
    .rst        ( rst           ),
    .clk        ( clk           ),
    .cen6       ( cen6          ),
    .cpu_AB     ( 11'd0         ),
    .V          ( V[7:0]        ),
    .H          ( H             ),
    .RnW        ( 1'b0          ),
    .flip       ( flip          ),
    .cpu_dout   ( 8'd0          ),

    .char_cs    ( 1'b0          ),
    .chram_dout ( chram_dout    ),
    .char_mrdy  ( char_mrdy     ),
    .char_addr  ( char_addr     ),
    .chrom_data ( chrom_data    ),

    .scr_cs     ( 1'b0          ),
    .scrpos_cs  ( 1'b0          ),
    .scram_dout ( scram_dout    ),
    .scr_addr   ( scr_addr      ),
    .scrom_data ( scr_dout      ),

    .HINIT      ( HINIT         ),
    .obj_AB     ( obj_AB        ),
    .main_ram   ( 8'd0          ),
    .OKOUT      ( 1'b0          ),
    .bus_req    ( bus_req       ),
    .bus_ack    ( 1'b0          ),
    .blcnten    ( blcnten       ),
    .obj_addr   ( obj_addr      ),
    .obj_data   ( obj_data      ),

    .LHBL       ( LHBL          ),
    .LVBL       ( LVBL          ),
    .blue_cs    ( 1'b0          ),
    .redgreen_cs( 1'b0          ),
    .enable_char( 1'b1          ),
    .enable_obj ( 1'b0          ),
    .enable_scr ( 1'b0          ),
    .red        ( red           ),
    .green      ( green         ),
    .blue       ( blue          )
);


wire [15:0] SDRAM_DQ;
wire [12:0] SDRAM_A;
wire        SDRAM_DQML;
wire        SDRAM_DQMH;
wire        SDRAM_nWE;
wire        SDRAM_nCAS;
wire        SDRAM_nRAS;
wire        SDRAM_nCS;
wire  [1:0] SDRAM_BA;
wire        SDRAM_CKE;


wire [1:0] Dqm = { SDRAM_DQMH, SDRAM_DQML };



reg  [15:0] sdram_mem[0:2**18-1];
reg  [12:0] sdram_row;

reg  [15:0] sdram_data;
reg  [17:0] sdram_compound;
assign SDRAM_DQ = sdram_data;
initial $readmemh("../../../rom/gng.hex",  sdram_mem, 0, 180223);
always @(posedge SDRAM_CLK) begin
    if( !SDRAM_nCS && !SDRAM_nRAS &&  SDRAM_nCAS && SDRAM_nWE && SDRAM_CKE ) sdram_row <= SDRAM_A;
    if( !SDRAM_nCS &&  SDRAM_nRAS && !SDRAM_nCAS && SDRAM_nWE && SDRAM_CKE ) sdram_compound <= {sdram_row[8:0], SDRAM_A[8:0]};
    sdram_data <= sdram_mem[ sdram_compound ];
end


jtgng_rom rom (
    .clk        ( SDRAM_CLK     ),
    .rst        ( rst           ),
    .char_addr  ( char_addr     ),
    .main_addr  ( 17'd0         ),
    .snd_addr   ( 15'd0         ),
    .obj_addr   ( obj_addr      ),
    .scr_addr   ( scr_addr      ),

    .char_dout  ( chrom_data    ),
    .main_dout  (               ),
    .snd_dout   (               ),
    .obj_dout   ( obj_data      ),
    .scr_dout   ( scr_dout      ),
    .ready      ( rom_ready     ),

    .SDRAM_DQ   ( SDRAM_DQ      ),
    .SDRAM_A    ( SDRAM_A       ),
    .SDRAM_DQML ( SDRAM_DQML    ),
    .SDRAM_DQMH ( SDRAM_DQMH    ),
    .SDRAM_nWE  ( SDRAM_nWE     ),
    .SDRAM_nCAS ( SDRAM_nCAS    ),
    .SDRAM_nRAS ( SDRAM_nRAS    ),
    .SDRAM_nCS  ( SDRAM_nCS     ),
    .SDRAM_BA   ( SDRAM_BA      ),
    .SDRAM_CKE  ( SDRAM_CKE     ),

    .downloading ( 1'b0         ),
    .romload_addr( 25'd0        ),
    .romload_data( 16'd0        ),
    .romload_wr  ( 1'b0         )
);

endmodule
module test(
    input           rst,
    input           SDRAM_CLK,
    input           clk,
    input           cen6,
    input           flip,
    output   [3:0]  red,
    output   [3:0]  green,
    output   [3:0]  blue,
    output          LHBL,
    output          LVBL,
    output          rom_ready
);


wire [8:0] V;
wire [8:0] H;
wire HINIT;

jtgng_timer timers(
    .clk       ( clk      ),
    .clk_en    ( cen6     ),
    .V         ( V        ),
    .H         ( H        ),
    .Hinit     ( HINIT    ),
    .LHBL      ( LHBL     ),
    .LVBL      ( LVBL     )
);

wire char_mrdy;
wire [12:0] char_addr;
wire [ 7:0] chram_dout,scram_dout;
wire [15:0] chrom_data;
wire [ 8:0] obj_AB;
wire bus_req, blen;
wire [14:0] obj_addr;
wire [15:0] obj_data;
wire [23:0] scr_dout;
wire [14:0] scr_addr;

jtgng_video u_video(
    .rst        ( rst           ),
    .clk        ( clk           ),
    .cen6       ( cen6          ),
    .cpu_AB     ( 11'd0         ),
    .V          ( V[7:0]        ),
    .H          ( H             ),
    .RnW        ( 1'b0          ),
    .flip       ( flip          ),
    .cpu_dout   ( 8'd0          ),

    .char_cs    ( 1'b0          ),
    .chram_dout ( chram_dout    ),
    .char_mrdy  ( char_mrdy     ),
    .char_addr  ( char_addr     ),
    .chrom_data ( chrom_data    ),

    .scr_cs     ( 1'b0          ),
    .scrpos_cs  ( 1'b0          ),
    .scram_dout ( scram_dout    ),
    .scr_addr   ( scr_addr      ),
    .scrom_data ( scr_dout      ),

    .HINIT      ( HINIT         ),
    .obj_AB     ( obj_AB        ),
    .main_ram   ( 8'd0          ),
    .OKOUT      ( 1'b0          ),
    .bus_req    ( bus_req       ),
    .bus_ack    ( 1'b0          ),
    .blcnten    ( blcnten       ),
    .obj_addr   ( obj_addr      ),
    .obj_data   ( obj_data      ),

    .LHBL       ( LHBL          ),
    .LVBL       ( LVBL          ),
    .blue_cs    ( 1'b0          ),
    .redgreen_cs( 1'b0          ),
    .enable_char( 1'b1          ),
    .enable_obj ( 1'b0          ),
    .enable_scr ( 1'b0          ),
    .red        ( red           ),
    .green      ( green         ),
    .blue       ( blue          )
);


wire [15:0] SDRAM_DQ;
wire [12:0] SDRAM_A;
wire        SDRAM_DQML;
wire        SDRAM_DQMH;
wire        SDRAM_nWE;
wire        SDRAM_nCAS;
wire        SDRAM_nRAS;
wire        SDRAM_nCS;
wire  [1:0] SDRAM_BA;
wire        SDRAM_CKE;


wire [1:0] Dqm = { SDRAM_DQMH, SDRAM_DQML };



reg  [15:0] sdram_mem[0:2**18-1];
reg  [12:0] sdram_row;

reg  [15:0] sdram_data;
reg  [17:0] sdram_compound;
assign SDRAM_DQ = sdram_data;
initial $readmemh("../../../rom/gng.hex",  sdram_mem, 0, 180223);
always @(posedge SDRAM_CLK) begin
    if( !SDRAM_nCS && !SDRAM_nRAS &&  SDRAM_nCAS && SDRAM_nWE && SDRAM_CKE ) sdram_row <= SDRAM_A;
    if( !SDRAM_nCS &&  SDRAM_nRAS && !SDRAM_nCAS && SDRAM_nWE && SDRAM_CKE ) sdram_compound <= {sdram_row[8:0], SDRAM_A[8:0]};
    sdram_data <= sdram_mem[ sdram_compound ];
end


jtgng_rom rom (
    .clk        ( SDRAM_CLK     ),
    .rst        ( rst           ),
    .char_addr  ( char_addr     ),
    .main_addr  ( 17'd0         ),
    .snd_addr   ( 15'd0         ),
    .obj_addr   ( obj_addr      ),
    .scr_addr   ( scr_addr      ),

    .char_dout  ( chrom_data    ),
    .main_dout  (               ),
    .snd_dout   (               ),
    .obj_dout   ( obj_data      ),
    .scr_dout   ( scr_dout      ),
    .ready      ( rom_ready     ),

    .SDRAM_DQ   ( SDRAM_DQ      ),
    .SDRAM_A    ( SDRAM_A       ),
    .SDRAM_DQML ( SDRAM_DQML    ),
    .SDRAM_DQMH ( SDRAM_DQMH    ),
    .SDRAM_nWE  ( SDRAM_nWE     ),
    .SDRAM_nCAS ( SDRAM_nCAS    ),
    .SDRAM_nRAS ( SDRAM_nRAS    ),
    .SDRAM_nCS  ( SDRAM_nCS     ),
    .SDRAM_BA   ( SDRAM_BA      ),
    .SDRAM_CKE  ( SDRAM_CKE     ),

    .downloading ( 1'b0         ),
    .romload_addr( 25'd0        ),
    .romload_data( 16'd0        ),
    .romload_wr  ( 1'b0         )
);

endmodule