data/full_repos/permissive/154804262/testBench/DetectLow2High_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/DetectLow2High_tb.v:7: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/DetectLow2High_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #100 reset = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/DetectLow2High_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #180 reset = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/DetectLow2High_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #1000 signal = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/DetectLow2High_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #180 signal = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/DetectLow2High_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #100 signal = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/DetectLow2High_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #100 signal = 1\'b1;\n  ^\n%Error: data/full_repos/permissive/154804262/testBench/DetectLow2High_tb.v:29: Cannot find file containing module: \'DetectLow2High\'\n DetectLow2High DetectLow2HighIns(\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154804262/testBench,data/full_repos/permissive/154804262/DetectLow2High\n             data/full_repos/permissive/154804262/testBench,data/full_repos/permissive/154804262/DetectLow2High.v\n             data/full_repos/permissive/154804262/testBench,data/full_repos/permissive/154804262/DetectLow2High.sv\n             DetectLow2High\n             DetectLow2High.v\n             DetectLow2High.sv\n             obj_dir/DetectLow2High\n             obj_dir/DetectLow2High.v\n             obj_dir/DetectLow2High.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DetectLow2High_tb;

	reg clk;
	initial
		clk = 1'b0;
	always
		#5 clk = ~clk;

	reg reset;
	initial
	begin
		reset = 1'b1;
		#100 reset = 1'b0;
		#180 reset = 1'b1;

	end
	
	reg signal;
	initial
	begin
		signal = 1'b1;
		#1000 signal = 1'b0;
		#180 signal = 1'b1;
		#100 signal = 1'b0;
		#100 signal = 1'b1;
	end
	
	wire low2HighSignal;
	DetectLow2High DetectLow2HighIns(
		.clk(clk),
		.reset(reset),
		.signal(signal),
		.low2HighSignal(low2HighSignal)
		);

endmodule
module DetectLow2High_tb;


	reg clk;
	initial
		clk = 1'b0;
	always
		#5 clk = ~clk;

	reg reset;
	initial
	begin
		reset = 1'b1;
		#100 reset = 1'b0;
		#180 reset = 1'b1;

	end
	
	reg signal;
	initial
	begin
		signal = 1'b1;
		#1000 signal = 1'b0;
		#180 signal = 1'b1;
		#100 signal = 1'b0;
		#100 signal = 1'b1;
	end
	
	wire low2HighSignal;
	DetectLow2High DetectLow2HighIns(
		.clk(clk),
		.reset(reset),
		.signal(signal),
		.low2HighSignal(low2HighSignal)
		);

endmodule