data/full_repos/permissive/162571337/multiplers/8x2_unsigned/pareto_pwr_mae/mul8x2u_0SJ.v
data/verilator_xmls/5893cb09-06cf-4723-8425-9fed009aeb48.xml
module mul8x2u_0SJ (
    A,
    B,
    O
);

input [7:0] A;
input [1:0] B;
output [9:0] O;

wire sig_14,sig_15,sig_17,sig_20,sig_25,sig_31,sig_40,sig_42,sig_65;

assign sig_14 = ~(B[1] & A[6]);
assign sig_15 = B[0] & A[5];
assign sig_17 = A[7] & B[0];
assign sig_20 = ~A[6];
assign sig_25 = A[7] & B[1];
assign sig_31 = ~(A[7] | sig_14);
assign sig_40 = sig_25 & sig_20;
assign sig_42 = ~(sig_14 | sig_31);
assign sig_65 = sig_40 | sig_31;

assign O[9] = sig_42;
assign O[8] = sig_65;
assign O[7] = sig_17;
assign O[6] = sig_15;
assign O[5] = 1'b0;
assign O[4] = 1'b0;
assign O[3] = sig_17;
assign O[2] = 1'b0;
assign O[1] = sig_25;
assign O[0] = 1'b0;

endmodule
module mul8x2u_0SJ (
    A,
    B,
    O
);


input [7:0] A;
input [1:0] B;
output [9:0] O;

wire sig_14,sig_15,sig_17,sig_20,sig_25,sig_31,sig_40,sig_42,sig_65;

assign sig_14 = ~(B[1] & A[6]);
assign sig_15 = B[0] & A[5];
assign sig_17 = A[7] & B[0];
assign sig_20 = ~A[6];
assign sig_25 = A[7] & B[1];
assign sig_31 = ~(A[7] | sig_14);
assign sig_40 = sig_25 & sig_20;
assign sig_42 = ~(sig_14 | sig_31);
assign sig_65 = sig_40 | sig_31;

assign O[9] = sig_42;
assign O[8] = sig_65;
assign O[7] = sig_17;
assign O[6] = sig_15;
assign O[5] = 1'b0;
assign O[4] = 1'b0;
assign O[3] = sig_17;
assign O[2] = 1'b0;
assign O[1] = sig_25;
assign O[0] = 1'b0;

endmodule