data/full_repos/permissive/105546923/projects/blink/hdl/top.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/86cb1451-5f2a-431d-92c0-9d0c5b44826f.xml
module top(
	   input 	ice_clk_i,
	   output [7:0] led_o
	   );
   
   reg [31:0] 		ctr;

   always @(posedge ice_clk_i)
     begin
	ctr <= ctr +1;
     end

   genvar i;
   generate
      for (i = 0; i<8; i = i + 1) begin
	 assign led_o[i] = ctr[i + 18];
      end
   endgenerate
   

endmodule
module top(
	   input 	ice_clk_i,
	   output [7:0] led_o
	   );

   
   reg [31:0] 		ctr;

   always @(posedge ice_clk_i)
     begin
	ctr <= ctr +1;
     end

   genvar i;
   generate
      for (i = 0; i<8; i = i + 1) begin
	 assign led_o[i] = ctr[i + 18];
      end
   endgenerate
   

endmodule