data/full_repos/permissive/148200700/Quartus/designFiles/ip/KBandIPsubPro/KBandIPsubPro_mm_bridge_FPGA_Slave/KBandIPsubPro_mm_bridge_FPGA_Slave_bb.v
data/verilator_xmls/d5420b3f-02a8-4151-ab60-568d82893c42.xml
module KBandIPsubPro_mm_bridge_FPGA_Slave #(
		parameter DATA_WIDTH        = 64,
		parameter SYMBOL_WIDTH      = 8,
		parameter HDL_ADDR_WIDTH    = 18,
		parameter BURSTCOUNT_WIDTH  = 1,
		parameter PIPELINE_COMMAND  = 1,
		parameter PIPELINE_RESPONSE = 1,
		parameter SYNC_RESET        = 0
	) (
		input  wire                        clk,
		input  wire                        reset,
		output wire                        s0_waitrequest,
		output wire [DATA_WIDTH-1:0]       s0_readdata,
		output wire                        s0_readdatavalid,
		input  wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
		input  wire [DATA_WIDTH-1:0]       s0_writedata,
		input  wire [HDL_ADDR_WIDTH-1:0]   s0_address,
		input  wire                        s0_write,
		input  wire                        s0_read,
		input  wire [7:0]                  s0_byteenable,
		input  wire                        s0_debugaccess,
		input  wire                        m0_waitrequest,
		input  wire [DATA_WIDTH-1:0]       m0_readdata,
		input  wire                        m0_readdatavalid,
		output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
		output wire [DATA_WIDTH-1:0]       m0_writedata,
		output wire [HDL_ADDR_WIDTH-1:0]   m0_address,
		output wire                        m0_write,
		output wire                        m0_read,
		output wire [7:0]                  m0_byteenable,
		output wire                        m0_debugaccess
	);
endmodule
module KBandIPsubPro_mm_bridge_FPGA_Slave #(
		parameter DATA_WIDTH        = 64,
		parameter SYMBOL_WIDTH      = 8,
		parameter HDL_ADDR_WIDTH    = 18,
		parameter BURSTCOUNT_WIDTH  = 1,
		parameter PIPELINE_COMMAND  = 1,
		parameter PIPELINE_RESPONSE = 1,
		parameter SYNC_RESET        = 0
	) (
		input  wire                        clk,
		input  wire                        reset,
		output wire                        s0_waitrequest,
		output wire [DATA_WIDTH-1:0]       s0_readdata,
		output wire                        s0_readdatavalid,
		input  wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
		input  wire [DATA_WIDTH-1:0]       s0_writedata,
		input  wire [HDL_ADDR_WIDTH-1:0]   s0_address,
		input  wire                        s0_write,
		input  wire                        s0_read,
		input  wire [7:0]                  s0_byteenable,
		input  wire                        s0_debugaccess,
		input  wire                        m0_waitrequest,
		input  wire [DATA_WIDTH-1:0]       m0_readdata,
		input  wire                        m0_readdatavalid,
		output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
		output wire [DATA_WIDTH-1:0]       m0_writedata,
		output wire [HDL_ADDR_WIDTH-1:0]   m0_address,
		output wire                        m0_write,
		output wire                        m0_read,
		output wire [7:0]                  m0_byteenable,
		output wire                        m0_debugaccess
	);

endmodule