data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new/Control.v
'utf-8' codec can't decode byte 0xb6 in position 972: invalid start byte
1: b"%Error: data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new/Control.v:39: Cannot find file containing module: 'ALUct'\n    ALUct aluct0(rst, aluct_inst, ct_alu_op, ct_alu);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new,data/full_repos/permissive/141745123/ALUct\n             data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new,data/full_repos/permissive/141745123/ALUct.v\n             data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new,data/full_repos/permissive/141745123/ALUct.sv\n             ALUct\n             ALUct.v\n             ALUct.sv\n             obj_dir/ALUct\n             obj_dir/ALUct.v\n             obj_dir/ALUct.sv\n%Error: Exiting due to 1 error(s)\n"
module Control(
    input rst,
    input[5:0] ct_inst,
    input[5:0] aluct_inst,
    output ct_rf_dst,
    output ct_rf_wen,
    output ct_alu_src,
    output[3:0] ct_alu,
    output ct_mem_wen,
    output ct_mem_ren,
    output ct_data_rf,
    output ct_branch,
    output ct_jump
    );
    wire inst_r, inst_lw, inst_sw, inst_beq, inst_j, inst_addiu, inst_lui, inst_ori, inst_r2, inst_andi, inst_xori, inst_slti;
    wire[7:0] ct_alu_op;
    ALUct aluct0(rst, aluct_inst, ct_alu_op, ct_alu);


    assign inst_r = (!ct_inst[5])&&(!ct_inst[4])&&(!ct_inst[3])&&(!ct_inst[2])&&(!ct_inst[1])&&(!ct_inst[0]);
    assign inst_beq = (!ct_inst[5])&&(!ct_inst[4])&&(!ct_inst[3])&&(ct_inst[2])&&(!ct_inst[1])&&(!ct_inst[0]);
    assign inst_lw = (ct_inst[5])&&(!ct_inst[4])&&(!ct_inst[3])&&(!ct_inst[2])&&(ct_inst[1])&&(ct_inst[0]);
    assign inst_sw = (ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(!ct_inst[2])&&(ct_inst[1])&&(ct_inst[0]);
    assign inst_j = (!ct_inst[5])&&(!ct_inst[4])&&(!ct_inst[3])&&(!ct_inst[2])&&(ct_inst[1])&&(!ct_inst[0]);
    assign inst_addiu = (!ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(!ct_inst[2])&&(!ct_inst[1])&&(ct_inst[0]);
    assign inst_lui = (!ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(ct_inst[2])&&(ct_inst[1])&&(ct_inst[0]);
    assign inst_ori = (!ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(ct_inst[2])&&(!ct_inst[1])&&(ct_inst[0]);
    assign inst_r2 = (!ct_inst[5])&&(ct_inst[4])&&(ct_inst[3])&&(ct_inst[2])&&(!ct_inst[1])&&(!ct_inst[0]);
    assign inst_andi = (!ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(ct_inst[2])&&(!ct_inst[1])&&(!ct_inst[0]);
    assign inst_xori = (!ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(ct_inst[2])&&(ct_inst[1])&&(!ct_inst[0]);
    assign inst_slti = (!ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(!ct_inst[2])&&(ct_inst[1])&&(!ct_inst[0]);
    

    assign ct_rf_dst = rst?inst_r:0;
    assign ct_rf_wen = rst?(inst_r||inst_lw||inst_addiu||inst_lui||inst_ori||inst_andi||inst_xori||inst_slti):0;
    assign ct_alu_src = (inst_lw||inst_sw||inst_addiu||inst_lui||inst_ori||inst_andi||inst_xori||inst_slti);
    assign ct_alu_op[7:0] = {inst_slti,inst_xori,inst_andi,inst_r2,inst_r,inst_ori,inst_beq,inst_lui};
    assign ct_branch = rst?inst_beq:0;
    assign ct_mem_ren = rst?inst_lw:0;
    assign ct_mem_wen = rst?inst_sw:0;
    assign ct_data_rf = rst?inst_lw:0;
    assign ct_jump = rst?inst_j:0;
    




    
endmodule
module Control(
    input rst,
    input[5:0] ct_inst,
    input[5:0] aluct_inst,
    output ct_rf_dst,
    output ct_rf_wen,
    output ct_alu_src,
    output[3:0] ct_alu,
    output ct_mem_wen,
    output ct_mem_ren,
    output ct_data_rf,
    output ct_branch,
    output ct_jump
    );

    wire inst_r, inst_lw, inst_sw, inst_beq, inst_j, inst_addiu, inst_lui, inst_ori, inst_r2, inst_andi, inst_xori, inst_slti;
    wire[7:0] ct_alu_op;
    ALUct aluct0(rst, aluct_inst, ct_alu_op, ct_alu);


    assign inst_r = (!ct_inst[5])&&(!ct_inst[4])&&(!ct_inst[3])&&(!ct_inst[2])&&(!ct_inst[1])&&(!ct_inst[0]);
    assign inst_beq = (!ct_inst[5])&&(!ct_inst[4])&&(!ct_inst[3])&&(ct_inst[2])&&(!ct_inst[1])&&(!ct_inst[0]);
    assign inst_lw = (ct_inst[5])&&(!ct_inst[4])&&(!ct_inst[3])&&(!ct_inst[2])&&(ct_inst[1])&&(ct_inst[0]);
    assign inst_sw = (ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(!ct_inst[2])&&(ct_inst[1])&&(ct_inst[0]);
    assign inst_j = (!ct_inst[5])&&(!ct_inst[4])&&(!ct_inst[3])&&(!ct_inst[2])&&(ct_inst[1])&&(!ct_inst[0]);
    assign inst_addiu = (!ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(!ct_inst[2])&&(!ct_inst[1])&&(ct_inst[0]);
    assign inst_lui = (!ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(ct_inst[2])&&(ct_inst[1])&&(ct_inst[0]);
    assign inst_ori = (!ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(ct_inst[2])&&(!ct_inst[1])&&(ct_inst[0]);
    assign inst_r2 = (!ct_inst[5])&&(ct_inst[4])&&(ct_inst[3])&&(ct_inst[2])&&(!ct_inst[1])&&(!ct_inst[0]);
    assign inst_andi = (!ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(ct_inst[2])&&(!ct_inst[1])&&(!ct_inst[0]);
    assign inst_xori = (!ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(ct_inst[2])&&(ct_inst[1])&&(!ct_inst[0]);
    assign inst_slti = (!ct_inst[5])&&(!ct_inst[4])&&(ct_inst[3])&&(!ct_inst[2])&&(ct_inst[1])&&(!ct_inst[0]);
    

    assign ct_rf_dst = rst?inst_r:0;
    assign ct_rf_wen = rst?(inst_r||inst_lw||inst_addiu||inst_lui||inst_ori||inst_andi||inst_xori||inst_slti):0;
    assign ct_alu_src = (inst_lw||inst_sw||inst_addiu||inst_lui||inst_ori||inst_andi||inst_xori||inst_slti);
    assign ct_alu_op[7:0] = {inst_slti,inst_xori,inst_andi,inst_r2,inst_r,inst_ori,inst_beq,inst_lui};
    assign ct_branch = rst?inst_beq:0;
    assign ct_mem_ren = rst?inst_lw:0;
    assign ct_mem_wen = rst?inst_sw:0;
    assign ct_data_rf = rst?inst_lw:0;
    assign ct_jump = rst?inst_j:0;
    




    
endmodule