data/full_repos/permissive/208556773/src/register_input.v
data/verilator_xmls/0c783a7a-2338-4085-bd93-25ca94d264e4.xml
module register_input
#(
  parameter width = 1
  )(
  input clk,
  input [width-1:0] in,
  output reg [width-1:0] out
);

  always @(posedge clk) out <= in;

endmodule
module register_input
#(
  parameter width = 1
  )(
  input clk,
  input [width-1:0] in,
  output reg [width-1:0] out
);


  always @(posedge clk) out <= in;

endmodule