data/full_repos/permissive/167580717/sys/sysmem.sv
1: b"%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:224: Cannot find file containing module: 'cyclonev_hps_interface_clocks_resets'\ncyclonev_hps_interface_clocks_resets clocks_resets(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167580717/sys,data/full_repos/permissive/167580717/cyclonev_hps_interface_clocks_resets\n             data/full_repos/permissive/167580717/sys,data/full_repos/permissive/167580717/cyclonev_hps_interface_clocks_resets.v\n             data/full_repos/permissive/167580717/sys,data/full_repos/permissive/167580717/cyclonev_hps_interface_clocks_resets.sv\n             cyclonev_hps_interface_clocks_resets\n             cyclonev_hps_interface_clocks_resets.v\n             cyclonev_hps_interface_clocks_resets.sv\n             obj_dir/cyclonev_hps_interface_clocks_resets\n             obj_dir/cyclonev_hps_interface_clocks_resets.v\n             obj_dir/cyclonev_hps_interface_clocks_resets.sv\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:246: Cannot find file containing module: 'cyclonev_hps_interface_dbg_apb'\ncyclonev_hps_interface_dbg_apb debug_apb(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:256: Cannot find file containing module: 'cyclonev_hps_interface_tpiu_trace'\ncyclonev_hps_interface_tpiu_trace tpiu(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:263: Cannot find file containing module: 'cyclonev_hps_interface_boot_from_fpga'\ncyclonev_hps_interface_boot_from_fpga boot_from_fpga(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:285: Cannot find file containing module: 'cyclonev_hps_interface_fpga2hps'\ncyclonev_hps_interface_fpga2hps fpga2hps(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:292: Cannot find file containing module: 'cyclonev_hps_interface_hps2fpga'\ncyclonev_hps_interface_hps2fpga hps2fpga(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:299: Cannot find file containing module: 'cyclonev_hps_interface_fpga2sdram'\ncyclonev_hps_interface_fpga2sdram f2sdram(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:464: Cannot find file containing module: 'cyclonev_hps_interface_peripheral_uart'\ncyclonev_hps_interface_peripheral_uart peripheral_uart1\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:109: Cannot find file containing module: 'reset_source'\nreset_source reset_source (\n^~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module sysmem_HPS_fpga_interfaces
(

	output wire [1 - 1 : 0 ] h2f_rst_n


	,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n


	,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n


	,output wire [1 - 1 : 0 ] h2f_user0_clk


	,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
	,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
	,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
	,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
	,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
	,input wire [1 - 1 : 0 ] f2h_sdram0_READ
	,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
	,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
	,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE


	,input wire [1 - 1 : 0 ] f2h_sdram0_clk


	,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
	,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
	,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
	,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
	,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
	,input wire [1 - 1 : 0 ] f2h_sdram1_READ
	,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
	,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
	,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE


	,input wire [1 - 1 : 0 ] f2h_sdram1_clk


	,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
	,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
	,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
	,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
	,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
	,input wire [1 - 1 : 0 ] f2h_sdram2_READ
	,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
	,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
	,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE


	,input wire [1 - 1 : 0 ] f2h_sdram2_clk

	,input          uart_cts
	,input          uart_dsr
	,input          uart_dcd
	,input          uart_ri
	,output         uart_dtr
	,output         uart_rts
	,output         uart_out1_n
	,output         uart_out2_n
	,input          uart_rxd
	,output         uart_txd
);


wire [29 - 1 : 0] intermediate;
assign intermediate[0:0] = ~intermediate[1:1];
assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
assign intermediate[2:2] = intermediate[9:9];
assign intermediate[3:3] = intermediate[9:9];
assign intermediate[5:5] = intermediate[9:9];
assign intermediate[6:6] = intermediate[9:9];
assign intermediate[10:10] = intermediate[9:9];
assign intermediate[11:11] = ~intermediate[12:12];
assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
assign intermediate[13:13] = intermediate[18:18];
assign intermediate[15:15] = intermediate[18:18];
assign intermediate[19:19] = intermediate[18:18];
assign intermediate[20:20] = ~intermediate[21:21];
assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
assign intermediate[22:22] = intermediate[27:27];
assign intermediate[24:24] = intermediate[27:27];
assign intermediate[28:28] = intermediate[27:27];
assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
assign intermediate[4:4] = f2h_sdram0_READ[0:0];
assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
assign intermediate[9:9] = f2h_sdram0_clk[0:0];
assign intermediate[14:14] = f2h_sdram1_READ[0:0];
assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
assign intermediate[18:18] = f2h_sdram1_clk[0:0];
assign intermediate[23:23] = f2h_sdram2_READ[0:0];
assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
assign intermediate[27:27] = f2h_sdram2_clk[0:0];

cyclonev_hps_interface_clocks_resets clocks_resets(
 .f2h_warm_rst_req_n({
    f2h_warm_rst_req_n[0:0]
  })
,.f2h_pending_rst_ack({
    1'b1
  })
,.f2h_dbg_rst_req_n({
    1'b1
  })
,.h2f_rst_n({
    h2f_rst_n[0:0]
  })
,.f2h_cold_rst_req_n({
    f2h_cold_rst_req_n[0:0]
  })
,.h2f_user0_clk({
    h2f_user0_clk[0:0]
  })
);


cyclonev_hps_interface_dbg_apb debug_apb(
 .DBG_APB_DISABLE({
    1'b0
  })
,.P_CLK_EN({
    1'b0
  })
);


cyclonev_hps_interface_tpiu_trace tpiu(
 .traceclk_ctl({
    1'b1
  })
);


cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
 .boot_from_fpga_ready({
    1'b0
  })
,.boot_from_fpga_on_failure({
    1'b0
  })
,.bsel_en({
    1'b0
  })
,.csel_en({
    1'b0
  })
,.csel({
    2'b01
  })
,.bsel({
    3'b001
  })
);


cyclonev_hps_interface_fpga2hps fpga2hps(
 .port_size_config({
    2'b11
  })
);


cyclonev_hps_interface_hps2fpga hps2fpga(
 .port_size_config({
    2'b11
  })
);


cyclonev_hps_interface_fpga2sdram f2sdram(
 .cfg_rfifo_cport_map({
    16'b0010000100000000
  })
,.cfg_wfifo_cport_map({
    16'b0010000100000000
  })
,.rd_ready_3({
    1'b1
  })
,.cmd_port_clk_2({
    intermediate[28:28]
  })
,.rd_ready_2({
    1'b1
  })
,.cmd_port_clk_1({
    intermediate[19:19]
  })
,.rd_ready_1({
    1'b1
  })
,.cmd_port_clk_0({
    intermediate[10:10]
  })
,.rd_ready_0({
    1'b1
  })
,.wrack_ready_2({
    1'b1
  })
,.wrack_ready_1({
    1'b1
  })
,.wrack_ready_0({
    1'b1
  })
,.cmd_ready_2({
    intermediate[21:21]
  })
,.cmd_ready_1({
    intermediate[12:12]
  })
,.cmd_ready_0({
    intermediate[1:1]
  })
,.cfg_port_width({
    12'b000000010110
  })
,.rd_valid_3({
    f2h_sdram2_READDATAVALID[0:0]
  })
,.rd_valid_2({
    f2h_sdram1_READDATAVALID[0:0]
  })
,.rd_valid_1({
    f2h_sdram0_READDATAVALID[0:0]
  })
,.rd_clk_3({
    intermediate[22:22]
  })
,.rd_data_3({
    f2h_sdram2_READDATA[63:0]
  })
,.rd_clk_2({
    intermediate[13:13]
  })
,.rd_data_2({
    f2h_sdram1_READDATA[63:0]
  })
,.rd_clk_1({
    intermediate[3:3]
  })
,.rd_data_1({
    f2h_sdram0_READDATA[127:64]
  })
,.rd_clk_0({
    intermediate[2:2]
  })
,.rd_data_0({
    f2h_sdram0_READDATA[63:0]
  })
,.cfg_axi_mm_select({
    6'b000000
  })
,.cmd_valid_2({
    intermediate[26:26]
  })
,.cmd_valid_1({
    intermediate[17:17]
  })
,.cmd_valid_0({
    intermediate[8:8]
  })
,.cfg_cport_rfifo_map({
    18'b000000000011010000
  })
,.wr_data_3({
    2'b00
   ,f2h_sdram2_BYTEENABLE[7:0]
   ,16'b0000000000000000
   ,f2h_sdram2_WRITEDATA[63:0]
  })
,.wr_data_2({
    2'b00
   ,f2h_sdram1_BYTEENABLE[7:0]
   ,16'b0000000000000000
   ,f2h_sdram1_WRITEDATA[63:0]
  })
,.wr_data_1({
    2'b00
   ,f2h_sdram0_BYTEENABLE[15:8]
   ,16'b0000000000000000
   ,f2h_sdram0_WRITEDATA[127:64]
  })
,.cfg_cport_type({
    12'b000000111111
  })
,.wr_data_0({
    2'b00
   ,f2h_sdram0_BYTEENABLE[7:0]
   ,16'b0000000000000000
   ,f2h_sdram0_WRITEDATA[63:0]
  })
,.cfg_cport_wfifo_map({
    18'b000000000011010000
  })
,.wr_clk_3({
    intermediate[24:24]
  })
,.wr_clk_2({
    intermediate[15:15]
  })
,.wr_clk_1({
    intermediate[6:6]
  })
,.wr_clk_0({
    intermediate[5:5]
  })
,.cmd_data_2({
    18'b000000000000000000
   ,f2h_sdram2_BURSTCOUNT[7:0]
   ,3'b000
   ,f2h_sdram2_ADDRESS[28:0]
   ,intermediate[25:25]
   ,intermediate[23:23]
  })
,.cmd_data_1({
    18'b000000000000000000
   ,f2h_sdram1_BURSTCOUNT[7:0]
   ,3'b000
   ,f2h_sdram1_ADDRESS[28:0]
   ,intermediate[16:16]
   ,intermediate[14:14]
  })
,.cmd_data_0({
    18'b000000000000000000
   ,f2h_sdram0_BURSTCOUNT[7:0]
   ,4'b0000
   ,f2h_sdram0_ADDRESS[27:0]
   ,intermediate[7:7]
   ,intermediate[4:4]
  })
);

cyclonev_hps_interface_peripheral_uart peripheral_uart1
(
	 .txd(uart_txd)
	,.cts(uart_cts)
	,.out1_n(uart_out1_n)
	,.dtr(uart_dtr)
	,.rts(uart_rts)
	,.out2_n(uart_out2_n)
	,.rxd(uart_rxd)
	,.ri(uart_ri)
	,.dsr(uart_dsr)
	,.dcd(uart_dcd)
);

endmodule
module sysmem_HPS_fpga_interfaces
(

	output wire [1 - 1 : 0 ] h2f_rst_n


	,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n


	,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n


	,output wire [1 - 1 : 0 ] h2f_user0_clk


	,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
	,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
	,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
	,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
	,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
	,input wire [1 - 1 : 0 ] f2h_sdram0_READ
	,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
	,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
	,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE


	,input wire [1 - 1 : 0 ] f2h_sdram0_clk


	,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
	,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
	,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
	,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
	,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
	,input wire [1 - 1 : 0 ] f2h_sdram1_READ
	,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
	,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
	,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE


	,input wire [1 - 1 : 0 ] f2h_sdram1_clk


	,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
	,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
	,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
	,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
	,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
	,input wire [1 - 1 : 0 ] f2h_sdram2_READ
	,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
	,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
	,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE


	,input wire [1 - 1 : 0 ] f2h_sdram2_clk

	,input          uart_cts
	,input          uart_dsr
	,input          uart_dcd
	,input          uart_ri
	,output         uart_dtr
	,output         uart_rts
	,output         uart_out1_n
	,output         uart_out2_n
	,input          uart_rxd
	,output         uart_txd
);



wire [29 - 1 : 0] intermediate;
assign intermediate[0:0] = ~intermediate[1:1];
assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
assign intermediate[2:2] = intermediate[9:9];
assign intermediate[3:3] = intermediate[9:9];
assign intermediate[5:5] = intermediate[9:9];
assign intermediate[6:6] = intermediate[9:9];
assign intermediate[10:10] = intermediate[9:9];
assign intermediate[11:11] = ~intermediate[12:12];
assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
assign intermediate[13:13] = intermediate[18:18];
assign intermediate[15:15] = intermediate[18:18];
assign intermediate[19:19] = intermediate[18:18];
assign intermediate[20:20] = ~intermediate[21:21];
assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
assign intermediate[22:22] = intermediate[27:27];
assign intermediate[24:24] = intermediate[27:27];
assign intermediate[28:28] = intermediate[27:27];
assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
assign intermediate[4:4] = f2h_sdram0_READ[0:0];
assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
assign intermediate[9:9] = f2h_sdram0_clk[0:0];
assign intermediate[14:14] = f2h_sdram1_READ[0:0];
assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
assign intermediate[18:18] = f2h_sdram1_clk[0:0];
assign intermediate[23:23] = f2h_sdram2_READ[0:0];
assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
assign intermediate[27:27] = f2h_sdram2_clk[0:0];

cyclonev_hps_interface_clocks_resets clocks_resets(
 .f2h_warm_rst_req_n({
    f2h_warm_rst_req_n[0:0]
  })
,.f2h_pending_rst_ack({
    1'b1
  })
,.f2h_dbg_rst_req_n({
    1'b1
  })
,.h2f_rst_n({
    h2f_rst_n[0:0]
  })
,.f2h_cold_rst_req_n({
    f2h_cold_rst_req_n[0:0]
  })
,.h2f_user0_clk({
    h2f_user0_clk[0:0]
  })
);


cyclonev_hps_interface_dbg_apb debug_apb(
 .DBG_APB_DISABLE({
    1'b0
  })
,.P_CLK_EN({
    1'b0
  })
);


cyclonev_hps_interface_tpiu_trace tpiu(
 .traceclk_ctl({
    1'b1
  })
);


cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
 .boot_from_fpga_ready({
    1'b0
  })
,.boot_from_fpga_on_failure({
    1'b0
  })
,.bsel_en({
    1'b0
  })
,.csel_en({
    1'b0
  })
,.csel({
    2'b01
  })
,.bsel({
    3'b001
  })
);


cyclonev_hps_interface_fpga2hps fpga2hps(
 .port_size_config({
    2'b11
  })
);


cyclonev_hps_interface_hps2fpga hps2fpga(
 .port_size_config({
    2'b11
  })
);


cyclonev_hps_interface_fpga2sdram f2sdram(
 .cfg_rfifo_cport_map({
    16'b0010000100000000
  })
,.cfg_wfifo_cport_map({
    16'b0010000100000000
  })
,.rd_ready_3({
    1'b1
  })
,.cmd_port_clk_2({
    intermediate[28:28]
  })
,.rd_ready_2({
    1'b1
  })
,.cmd_port_clk_1({
    intermediate[19:19]
  })
,.rd_ready_1({
    1'b1
  })
,.cmd_port_clk_0({
    intermediate[10:10]
  })
,.rd_ready_0({
    1'b1
  })
,.wrack_ready_2({
    1'b1
  })
,.wrack_ready_1({
    1'b1
  })
,.wrack_ready_0({
    1'b1
  })
,.cmd_ready_2({
    intermediate[21:21]
  })
,.cmd_ready_1({
    intermediate[12:12]
  })
,.cmd_ready_0({
    intermediate[1:1]
  })
,.cfg_port_width({
    12'b000000010110
  })
,.rd_valid_3({
    f2h_sdram2_READDATAVALID[0:0]
  })
,.rd_valid_2({
    f2h_sdram1_READDATAVALID[0:0]
  })
,.rd_valid_1({
    f2h_sdram0_READDATAVALID[0:0]
  })
,.rd_clk_3({
    intermediate[22:22]
  })
,.rd_data_3({
    f2h_sdram2_READDATA[63:0]
  })
,.rd_clk_2({
    intermediate[13:13]
  })
,.rd_data_2({
    f2h_sdram1_READDATA[63:0]
  })
,.rd_clk_1({
    intermediate[3:3]
  })
,.rd_data_1({
    f2h_sdram0_READDATA[127:64]
  })
,.rd_clk_0({
    intermediate[2:2]
  })
,.rd_data_0({
    f2h_sdram0_READDATA[63:0]
  })
,.cfg_axi_mm_select({
    6'b000000
  })
,.cmd_valid_2({
    intermediate[26:26]
  })
,.cmd_valid_1({
    intermediate[17:17]
  })
,.cmd_valid_0({
    intermediate[8:8]
  })
,.cfg_cport_rfifo_map({
    18'b000000000011010000
  })
,.wr_data_3({
    2'b00
   ,f2h_sdram2_BYTEENABLE[7:0]
   ,16'b0000000000000000
   ,f2h_sdram2_WRITEDATA[63:0]
  })
,.wr_data_2({
    2'b00
   ,f2h_sdram1_BYTEENABLE[7:0]
   ,16'b0000000000000000
   ,f2h_sdram1_WRITEDATA[63:0]
  })
,.wr_data_1({
    2'b00
   ,f2h_sdram0_BYTEENABLE[15:8]
   ,16'b0000000000000000
   ,f2h_sdram0_WRITEDATA[127:64]
  })
,.cfg_cport_type({
    12'b000000111111
  })
,.wr_data_0({
    2'b00
   ,f2h_sdram0_BYTEENABLE[7:0]
   ,16'b0000000000000000
   ,f2h_sdram0_WRITEDATA[63:0]
  })
,.cfg_cport_wfifo_map({
    18'b000000000011010000
  })
,.wr_clk_3({
    intermediate[24:24]
  })
,.wr_clk_2({
    intermediate[15:15]
  })
,.wr_clk_1({
    intermediate[6:6]
  })
,.wr_clk_0({
    intermediate[5:5]
  })
,.cmd_data_2({
    18'b000000000000000000
   ,f2h_sdram2_BURSTCOUNT[7:0]
   ,3'b000
   ,f2h_sdram2_ADDRESS[28:0]
   ,intermediate[25:25]
   ,intermediate[23:23]
  })
,.cmd_data_1({
    18'b000000000000000000
   ,f2h_sdram1_BURSTCOUNT[7:0]
   ,3'b000
   ,f2h_sdram1_ADDRESS[28:0]
   ,intermediate[16:16]
   ,intermediate[14:14]
  })
,.cmd_data_0({
    18'b000000000000000000
   ,f2h_sdram0_BURSTCOUNT[7:0]
   ,4'b0000
   ,f2h_sdram0_ADDRESS[27:0]
   ,intermediate[7:7]
   ,intermediate[4:4]
  })
);

cyclonev_hps_interface_peripheral_uart peripheral_uart1
(
	 .txd(uart_txd)
	,.cts(uart_cts)
	,.out1_n(uart_out1_n)
	,.dtr(uart_dtr)
	,.rts(uart_rts)
	,.out2_n(uart_out2_n)
	,.rxd(uart_rxd)
	,.ri(uart_ri)
	,.dsr(uart_dsr)
	,.dcd(uart_dcd)
);

endmodule