data/full_repos/permissive/173814379/implementation/io/controller_v1r0.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/173814379/implementation/io/controller_v1r0.v:76: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                              : ... Top module \'EmulatedIOPLL\'\nmodule EmulatedIOPLL(iIn, oOutUART, oOutSPI, oOutVGA, oOutFast);\n       ^~~~~~~~~~~~~\n                                                                                              : ... Top module \'epRISC_iocontroller\'\nmodule epRISC_iocontroller(iBusClock, iBusSelect, iBusMOSI, oBusInterrupt, oBusMISO,\n       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173814379/implementation/io/controller_v1r0.v:161: Cannot find file containing module: \'OnChipPLL\'\n    OnChipPLL           clock(iBoardClock, wSerialClock, wSPIClock, wVGAClock, wFastClock);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173814379/implementation/io,data/full_repos/permissive/173814379/OnChipPLL\n             data/full_repos/permissive/173814379/implementation/io,data/full_repos/permissive/173814379/OnChipPLL.v\n             data/full_repos/permissive/173814379/implementation/io,data/full_repos/permissive/173814379/OnChipPLL.sv\n             OnChipPLL\n             OnChipPLL.v\n             OnChipPLL.sv\n             obj_dir/OnChipPLL\n             obj_dir/OnChipPLL.v\n             obj_dir/OnChipPLL.sv\n%Error: data/full_repos/permissive/173814379/implementation/io/controller_v1r0.v:164: Cannot find file containing module: \'epRISC_GPIO\'\n    epRISC_GPIO         gpio(iBusClock, mBusReset, oBusInterrupt, mBusAddress, mBusData, wGPIOInternalMISO, mBusWrite, wEnableGPIO, \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/173814379/implementation/io/controller_v1r0.v:167: Cannot find file containing module: \'epRISC_UART\'\n    epRISC_UART         uart(iBusClock, mBusReset, oBvusInterrupt, mBusAddress, mBusData, wUARTInternalMISO, mBusWrite, wEnableUART, wSerialClock, iTTLSerialRX, oTTLSerialTX);   \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/173814379/implementation/io/controller_v1r0.v:169: Cannot find file containing module: \'epRISC_SPI\'\n    epRISC_SPI          bspi(iBusClock, mBusReset, oBrusInterrupt, mBusAddress, mBusData, wSPIInternalMISO, mBusWrite, wEnableSPI, wSPIClock, iSPIMISO, oSPIMOSI, oSPISelect, oSPIClock);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/173814379/implementation/io/controller_v1r0.v:171: Cannot find file containing module: \'epRISC_VideoTerm\'\n    epRISC_VideoTerm    bvga(iBusClock, mBusReset, mBusAddress, mBusData, wVideoInternalMISO, mBusWrite, wEnableVideo, wFastClock, wVGAClock, oVGAColor, oVGAHorizontal, oVGAVertical);\n    ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module EmulatedIOPLL(iIn, oOutUART, oOutSPI, oOutVGA, oOutFast);
    input iIn;
    output reg oOutUART, oOutSPI;
    output wire oOutVGA, oOutFast;

    reg [6:0] rClockSplit;

    assign oOutFast = iIn;
    assign oOutVGA = iIn;
    
    initial begin
        rClockSplit <= 0;
        oOutUART <= 0;
        oOutSPI <= 0;
    end

    always @(posedge iIn) begin
        rClockSplit <= rClockSplit + 1;

        if(rClockSplit[3] == 1)
            oOutUART = !oOutUART;
            
        if(rClockSplit == 5'd27)
            oOutSPI = !oOutSPI;
    end

endmodule
module EmulatedIOPLL(iIn, oOutUART, oOutSPI, oOutVGA, oOutFast);

    input iIn;
    output reg oOutUART, oOutSPI;
    output wire oOutVGA, oOutFast;

    reg [6:0] rClockSplit;

    assign oOutFast = iIn;
    assign oOutVGA = iIn;
    
    initial begin
        rClockSplit <= 0;
        oOutUART <= 0;
        oOutSPI <= 0;
    end

    always @(posedge iIn) begin
        rClockSplit <= rClockSplit + 1;

        if(rClockSplit[3] == 1)
            oOutUART = !oOutUART;
            
        if(rClockSplit == 5'd27)
            oOutSPI = !oOutSPI;
    end

endmodule