data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v
None: at end of input
1: b'%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:28: Cannot find include file: spio_spinnaker_link.h\n`include "spio_spinnaker_link.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.v\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.sv\n             spio_spinnaker_link.h\n             spio_spinnaker_link.h.v\n             spio_spinnaker_link.h.sv\n             obj_dir/spio_spinnaker_link.h\n             obj_dir/spio_spinnaker_link.h.v\n             obj_dir/spio_spinnaker_link.h.sv\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:44: Define or directive not defined: \'`PKT_BITS\'\n  input      [`PKT_BITS - 1:0] PKT_DATA_IN,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:105: Define or directive not defined: \'`PKT_BITS\'\n  input       [`PKT_BITS - 1:0] PKT_DATA_IN,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:129: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] pkt_buf;    \n         ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module spio_spinnaker_link_synchronous_sender
(
  input                        CLK_IN,
  input                        RESET_IN,


  output wire                  ACK_ERR_OUT,
  output wire                  TMO_ERR_OUT,


  input      [`PKT_BITS - 1:0] PKT_DATA_IN,
  input                        PKT_VLD_IN,
  output                       PKT_RDY_OUT,


  output                 [6:0] SL_DATA_2OF7_OUT,
  input                        SL_ACK_IN
);




  wire       synced_sl_ack;

  wire [6:0] flt_data;
  wire       flt_vld;
  wire       flt_rdy;

		
  pkt_serializer ps
  (
    .CLK_IN           (CLK_IN),
    .RESET_IN         (RESET_IN),
    .PKT_DATA_IN      (PKT_DATA_IN),
    .PKT_VLD_IN       (PKT_VLD_IN),
    .PKT_RDY_OUT      (PKT_RDY_OUT),
    .flt_data         (flt_data),
    .flt_vld          (flt_vld),
    .flt_rdy          (flt_rdy)
  );

  flit_output_if fo
  (
    .CLK_IN           (CLK_IN),
    .RESET_IN         (RESET_IN),
    .ACK_ERR_OUT      (ACK_ERR_OUT),
    .TMO_ERR_OUT      (TMO_ERR_OUT),
    .flt_data         (flt_data),
    .flt_vld          (flt_vld),
    .flt_rdy          (flt_rdy),
    .SL_DATA_2OF7_OUT (SL_DATA_2OF7_OUT),
    .SL_ACK_IN        (synced_sl_ack)
  );

  spio_spinnaker_link_sync #(.SIZE(1)) sync
  ( .CLK_IN (CLK_IN),
    .IN     (SL_ACK_IN),
    .OUT    (synced_sl_ack)
  );
endmodule
module spio_spinnaker_link_synchronous_sender
(
  input                        CLK_IN,
  input                        RESET_IN,


  output wire                  ACK_ERR_OUT,
  output wire                  TMO_ERR_OUT,


  input      [`PKT_BITS - 1:0] PKT_DATA_IN,
  input                        PKT_VLD_IN,
  output                       PKT_RDY_OUT,


  output                 [6:0] SL_DATA_2OF7_OUT,
  input                        SL_ACK_IN
);





  wire       synced_sl_ack;

  wire [6:0] flt_data;
  wire       flt_vld;
  wire       flt_rdy;

		
  pkt_serializer ps
  (
    .CLK_IN           (CLK_IN),
    .RESET_IN         (RESET_IN),
    .PKT_DATA_IN      (PKT_DATA_IN),
    .PKT_VLD_IN       (PKT_VLD_IN),
    .PKT_RDY_OUT      (PKT_RDY_OUT),
    .flt_data         (flt_data),
    .flt_vld          (flt_vld),
    .flt_rdy          (flt_rdy)
  );

  flit_output_if fo
  (
    .CLK_IN           (CLK_IN),
    .RESET_IN         (RESET_IN),
    .ACK_ERR_OUT      (ACK_ERR_OUT),
    .TMO_ERR_OUT      (TMO_ERR_OUT),
    .flt_data         (flt_data),
    .flt_vld          (flt_vld),
    .flt_rdy          (flt_rdy),
    .SL_DATA_2OF7_OUT (SL_DATA_2OF7_OUT),
    .SL_ACK_IN        (synced_sl_ack)
  );

  spio_spinnaker_link_sync #(.SIZE(1)) sync
  ( .CLK_IN (CLK_IN),
    .IN     (SL_ACK_IN),
    .OUT    (synced_sl_ack)
  );
endmodule