data/full_repos/permissive/21716763/uncle_gates/ncl_simlib_ref.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/21716763/uncle_gates/ncl_simlib_ref.v:38: Multiple top level modules\n                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                      : ... Top module \'th34w32_ref\'\nmodule th34w32_ref (y,a,b,c,d);\n       ^~~~~~~~~~~\n                                                                                      : ... Top module \'th54w32_ref\'\nmodule th54w32_ref (y,a,b,c,d);\n       ^~~~~~~~~~~\n                                                                                      : ... Top module \'thxor0_ref\'\nmodule thxor0_ref (y,a,b,c,d);\n       ^~~~~~~~~~\n                                                                                      : ... Top module \'thxor0n_ref\'\nmodule thxor0n_ref (y,a,b,c,d,rsb);\n       ^~~~~~~~~~~\n                                                                                      : ... Top module \'th24w2_ref\'\nmodule th24w2_ref (y,a,b,c,d);\n       ^~~~~~~~~~\n                                                                                      : ... Top module \'th44w22_ref\'\nmodule th44w22_ref (y,a,b,c,d);\n       ^~~~~~~~~~~\n                                                                                      : ... Top module \'th34w2_ref\'\nmodule th34w2_ref (y,a,b,c,d);\n       ^~~~~~~~~~\n                                                                                      : ... Top module \'th34w3_ref\'\nmodule th34w3_ref (y,a,b,c,d);\n       ^~~~~~~~~~\n                                                                                      : ... Top module \'th24_ref\'\nmodule th24_ref (y,a,b,c,d);\n       ^~~~~~~~\n                                                                                      : ... Top module \'th24comp_ref\'\nmodule th24comp_ref (y,a,b,c,d);\n       ^~~~~~~~~~~~\n                                                                                      : ... Top module \'th22_ref\'\nmodule th22_ref (y,a,b);\n       ^~~~~~~~\n                                                                                      : ... Top module \'th22x8_ref\'\nmodule th22x8_ref (y,a,b);\n       ^~~~~~~~~~\n                                                                                      : ... Top module \'th22r_ref\'\nmodule th22r_ref (y,a,b,rsb);\n       ^~~~~~~~~\n                                                                                      : ... Top module \'th22s_ref\'\nmodule th22s_ref (y,a,b,rsb);\n       ^~~~~~~~~\n                                                                                      : ... Top module \'th23_ref\'\nmodule th23_ref (y,a,b,c);\n       ^~~~~~~~\n                                                                                      : ... Top module \'th54w22_ref\'\nmodule th54w22_ref (y,a,b,c,d);\n       ^~~~~~~~~~~\n                                                                                      : ... Top module \'th34w22_ref\'\nmodule th34w22_ref (y,a,b,c,d);\n       ^~~~~~~~~~~\n                                                                                      : ... Top module \'th44_ref\'\nmodule th44_ref (y,a,b,c,d);\n       ^~~~~~~~\n                                                                                      : ... Top module \'th24w22_ref\'\nmodule th24w22_ref (y,a,b,c,d);\n       ^~~~~~~~~~~\n                                                                                      : ... Top module \'th44w3_ref\'\nmodule th44w3_ref (y,a,b,c,d);\n       ^~~~~~~~~~\n                                                                                      : ... Top module \'th44w2_ref\'\nmodule th44w2_ref (y,a,b,c,d);\n       ^~~~~~~~~~\n                                                                                      : ... Top module \'th33w2_ref\'\nmodule th33w2_ref (y,a,b,c);\n       ^~~~~~~~~~\n                                                                                      : ... Top module \'th34_ref\'\nmodule th34_ref (y,a,b,c,d);\n       ^~~~~~~~\n                                                                                      : ... Top module \'th23w2_ref\'\nmodule th23w2_ref (y,a,b,c);\n       ^~~~~~~~~~\n                                                                                      : ... Top module \'th13_ref\'\nmodule th13_ref (y,a,b,c);\n       ^~~~~~~~\n                                                                                      : ... Top module \'th12_ref\'\nmodule th12_ref (y,a,b);\n       ^~~~~~~~\n                                                                                      : ... Top module \'th54w322_ref\'\nmodule th54w322_ref (y,a,b,c,d);\n       ^~~~~~~~~~~~\n                                                                                      : ... Top module \'th14_ref\'\nmodule th14_ref (y,a,b,c,d);\n       ^~~~~~~~\n                                                                                      : ... Top module \'th33_ref\'\nmodule th33_ref (y,a,b,c);\n       ^~~~~~~~\n                                                                                      : ... Top module \'th33r_ref\'\nmodule th33r_ref (y,a,b,c,rsb);\n       ^~~~~~~~~\n                                                                                      : ... Top module \'thand0_ref\'\nmodule thand0_ref (y,a,b,c,d);\n       ^~~~~~~~~~\n                                                                                      : ... Top module \'th44w322_ref\'\nmodule th44w322_ref (y,a,b,c,d);\n       ^~~~~~~~~~~~\n                                                                                      : ... Top module \'th44w322a_ref\'\nmodule th44w322a_ref (y,a,b,c,d);\n       ^~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module th22r_ref (y,a,b,rsb);
 output y;
 input a;
 input b;
 input rsb;

 reg yi;

  always @(a or b or rsb) begin
   if (rsb == 0) begin
      yi <=  0;
   end
   else if (((a) & (b))) 
    begin
      yi <=  1;
    end
    else if (((a==0) & (b==0))) 
    begin
      yi <=  0;
    end
   end
  assign #1 y = yi; 
endmodule
module th22r_ref (y,a,b,rsb);

 output y;
 input a;
 input b;
 input rsb;

 reg yi;

  always @(a or b or rsb) begin
   if (rsb == 0) begin
      yi <=  0;
   end
   else if (((a) & (b))) 
    begin
      yi <=  1;
    end
    else if (((a==0) & (b==0))) 
    begin
      yi <=  0;
    end
   end
  assign #1 y = yi; 
endmodule