data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v
 line:57: before: "$"
1: b'%Error: data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v:18: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("fsm_wave.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v:19: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v:28: Unsupported: Ignoring delay on this delayed statement.\n #14\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v:31: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v:43: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v:49: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v:53: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v:56: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-02/fsm/fsm_tester.v:62: Unsupported: Ignoring delay on this delayed statement.\n      #5 CLK <= ~CLK;\n      ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fsm_tester(
  output reg CLK,
  output reg sReset,
  output reg sInit,
  output reg [3:0] sEmpty,
  output reg [3:0] sFull,
  output reg [3:0] sPause,
  output reg [3:0] sContinue);

initial
	begin
	CLK <= 0;
	end

initial
	begin
	$dumpfile("fsm_wave.vcd");
	$dumpvars;


	sReset <= 0;
	sInit <= 1;
	sEmpty <= 4'd0;
	sFull <= 4'd0;
	sPause <= 4'd0;
	sContinue <= 4'd0;
	#14

	sReset <= 1;
	#10

	sInit <= 0;
  sEmpty <= 4'd15;


	#10

	sEmpty <= 4'd0;
	#10

	sPause <= 4'b0110;
	#10

	sContinue <= 4'b0000;
	#10

	sContinue <= 4'b0110;
	#10
  sContinue <= 4'd0;

	sFull <= 4'd4;
	#10

	sReset <= 1;
	#20
	$finish;
	end

	always
		begin
      #5 CLK <= ~CLK;
    end

endmodule
module fsm_tester(
  output reg CLK,
  output reg sReset,
  output reg sInit,
  output reg [3:0] sEmpty,
  output reg [3:0] sFull,
  output reg [3:0] sPause,
  output reg [3:0] sContinue);


initial
	begin
	CLK <= 0;
	end

initial
	begin
	$dumpfile("fsm_wave.vcd");
	$dumpvars;


	sReset <= 0;
	sInit <= 1;
	sEmpty <= 4'd0;
	sFull <= 4'd0;
	sPause <= 4'd0;
	sContinue <= 4'd0;
	#14

	sReset <= 1;
	#10

	sInit <= 0;
  sEmpty <= 4'd15;


	#10

	sEmpty <= 4'd0;
	#10

	sPause <= 4'b0110;
	#10

	sContinue <= 4'b0000;
	#10

	sContinue <= 4'b0110;
	#10
  sContinue <= 4'd0;

	sFull <= 4'd4;
	#10

	sReset <= 1;
	#20
	$finish;
	end

	always
		begin
      #5 CLK <= ~CLK;
    end

endmodule