data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/sram_tb.v
 line:71: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/sram_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #prog_clk_period prog_clock = ~prog_clock;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/sram_tb.v:52: syntax error, unexpected \'@\'\n    @(posedge prog_clock);\n    ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sram6T_rram_tb;

wire read;
wire nequalize;
wire din;
wire dout;
wire doutb;
reg [0:2] bl;
reg [0:2] wl;
reg prog_clock;


parameter prog_clk_period = 2;


sram6T_rram U0 (read, nequalize, din, dout, doutb, bl, wl);



assign read = 1'b0;


assign nequalize = 1'b1;


assign din = 1'b0;


initial
begin 
  prog_clock = 1'b0;
end 
always
begin
  #prog_clk_period prog_clock = ~prog_clock;
end


task prog_blwl;
  input [0:2] bl_val;
  input [0:2] wl_val;
  begin
    @(posedge prog_clock);
    bl = bl_val;
    wl = wl_val;  
  end 
endtask








initial 
begin
  bl = 3'b000;
  wl = 3'b000;


  prog_blwl(3'b100, 3'b001);

  prog_blwl(3'b001, 3'b100);


  prog_blwl(3'b010, 3'b001);

  prog_blwl(3'b100, 3'b010);


  prog_blwl(3'b100, 3'b001);

  prog_blwl(3'b001, 3'b100);
end



endmodule
module sram6T_rram_tb;


wire read;
wire nequalize;
wire din;
wire dout;
wire doutb;
reg [0:2] bl;
reg [0:2] wl;
reg prog_clock;


parameter prog_clk_period = 2;


sram6T_rram U0 (read, nequalize, din, dout, doutb, bl, wl);



assign read = 1'b0;


assign nequalize = 1'b1;


assign din = 1'b0;


initial
begin 
  prog_clock = 1'b0;
end 
always
begin
  #prog_clk_period prog_clock = ~prog_clock;
end


task prog_blwl;
  input [0:2] bl_val;
  input [0:2] wl_val;
  begin
    @(posedge prog_clock);
    bl = bl_val;
    wl = wl_val;  
  end 
endtask








initial 
begin
  bl = 3'b000;
  wl = 3'b000;


  prog_blwl(3'b100, 3'b001);

  prog_blwl(3'b001, 3'b100);


  prog_blwl(3'b010, 3'b001);

  prog_blwl(3'b100, 3'b010);


  prog_blwl(3'b100, 3'b001);

  prog_blwl(3'b001, 3'b100);
end



endmodule