data/full_repos/permissive/186491764/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/186491764/test.v:39: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/186491764/test.v:45: Unsupported: Ignoring delay on this delayed statement.\n   #5 clk = ~clk;\n   ^\n%Error: data/full_repos/permissive/186491764/test.v:31: Cannot find file containing module: \'RISC_8bit\'\n RISC_8bit uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/186491764,data/full_repos/permissive/186491764/RISC_8bit\n             data/full_repos/permissive/186491764,data/full_repos/permissive/186491764/RISC_8bit.v\n             data/full_repos/permissive/186491764,data/full_repos/permissive/186491764/RISC_8bit.sv\n             RISC_8bit\n             RISC_8bit.v\n             RISC_8bit.sv\n             obj_dir/RISC_8bit\n             obj_dir/RISC_8bit.v\n             obj_dir/RISC_8bit.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;


	reg clk;
	reg [7:0] sw;
   wire [7:0] led;

	RISC_8bit uut (
		.clk(clk),.led(led),.sw(sw)
	);

	initial 
  begin
   clk <=0;
	sw <= 8'b00001010;
   #50;
   $finish;
  end

 always 
  begin
   #5 clk = ~clk;
  end
      
endmodule
module test;



	reg clk;
	reg [7:0] sw;
   wire [7:0] led;

	RISC_8bit uut (
		.clk(clk),.led(led),.sw(sw)
	);

	initial 
  begin
   clk <=0;
	sw <= 8'b00001010;
   #50;
   $finish;
  end

 always 
  begin
   #5 clk = ~clk;
  end
      
endmodule