data/full_repos/permissive/199129998/hardware/mmu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/199129998/hardware/mmu.v:115: Operator GT expects 32 or 18 bits on the LHS, but LHS\'s VARREF \'tick\' generates 16 bits.\n                                                                       : ... In instance mmu\n  else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC + MRS_TO_NEW_COMMAND_tMRD) begin\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/199129998/hardware/mmu.v:112: Operator GT expects 32 or 18 bits on the LHS, but LHS\'s VARREF \'tick\' generates 16 bits.\n                                                                       : ... In instance mmu\n  else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC + MRS_TO_NEW_COMMAND_tMRD) begin\n                ^\n%Warning-WIDTH: data/full_repos/permissive/199129998/hardware/mmu.v:112: Operator LTE expects 32 or 18 bits on the LHS, but LHS\'s VARREF \'tick\' generates 16 bits.\n                                                                       : ... In instance mmu\n  else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC + MRS_TO_NEW_COMMAND_tMRD) begin\n                                                                                                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/199129998/hardware/mmu.v:109: Operator GT expects 32 or 18 bits on the LHS, but LHS\'s VARREF \'tick\' generates 16 bits.\n                                                                       : ... In instance mmu\n  else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC) begin\n                ^\n%Warning-WIDTH: data/full_repos/permissive/199129998/hardware/mmu.v:109: Operator LTE expects 32 or 18 bits on the LHS, but LHS\'s VARREF \'tick\' generates 16 bits.\n                                                                       : ... In instance mmu\n  else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC) begin\n                                                                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/199129998/hardware/mmu.v:106: Operator GT expects 32 or 18 bits on the LHS, but LHS\'s VARREF \'tick\' generates 16 bits.\n                                                                       : ... In instance mmu\n  else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC) begin\n                ^\n%Warning-WIDTH: data/full_repos/permissive/199129998/hardware/mmu.v:106: Operator LTE expects 32 or 18 bits on the LHS, but LHS\'s VARREF \'tick\' generates 16 bits.\n                                                                       : ... In instance mmu\n  else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC) begin\n                                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/199129998/hardware/mmu.v:103: Operator GT expects 32 or 18 bits on the LHS, but LHS\'s VARREF \'tick\' generates 16 bits.\n                                                                       : ... In instance mmu\n  else if (tick > POWER_UP_VCC_AND_CLK_STABLE && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP) begin\n                ^\n%Warning-WIDTH: data/full_repos/permissive/199129998/hardware/mmu.v:103: Operator LTE expects 32 or 18 bits on the LHS, but LHS\'s VARREF \'tick\' generates 16 bits.\n                                                                       : ... In instance mmu\n  else if (tick > POWER_UP_VCC_AND_CLK_STABLE && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP) begin\n                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/199129998/hardware/mmu.v:100: Operator LTE expects 32 or 18 bits on the LHS, but LHS\'s VARREF \'tick\' generates 16 bits.\n                                                                       : ... In instance mmu\n  else if (tick > 0 && tick <= POWER_UP_VCC_AND_CLK_STABLE) begin\n                            ^~\n%Error: Exiting due to 10 warning(s)\n'
module mmu(
	input clk, 
	input rst_n,
	
	output reg[15:0] S_DQ,
	output reg[11:0] S_A,
	output S_CLK,
	output reg[1:0] S_BA,
	output reg S_nCAS,
	output reg S_CKE,
	output reg S_nRAS,
	output reg S_nWE,
	output reg S_nCS,
	output reg[1:0] S_DQM
	
);



localparam TICK_INTERVAL = 20;
assign S_CLK = clk;
	












































	localparam STATUS_DEFAULT = 0;
	localparam STATUS_POWER_UP = 1;
	localparam STATUS_PRE_CHARGE = 2;
	localparam STATUS_AUTO_REFRESH_1 = 3;
	localparam STATUS_AUTO_REFRESH_2 = 4;
	localparam STATUS_MODE_SET = 5;
	localparam STATUS_IDLE = 6;
	
	reg[3:0] status;
	
	reg[15:0] tick, last_tick;
	
	localparam POWER_UP_VCC_AND_CLK_STABLE = 200_000 / TICK_INTERVAL;
	localparam RAS_PRECHARGE_TIME_tRP = 18 / TICK_INTERVAL + 1;
	localparam RAS_CYCLE_TIME_tRC = 60 / TICK_INTERVAL;
	localparam MRS_TO_NEW_COMMAND_tMRD = 2;
	


	always @(posedge clk or negedge rst_n) 
	begin
		if (!rst_n) begin
			tick <= 0;
			last_tick <= 0;
		end 
		else begin
			tick <= tick + 1;
		end	
		
		if (!rst_n) begin

			status <= STATUS_DEFAULT;
		end 
		else if (tick > 0 && tick <= POWER_UP_VCC_AND_CLK_STABLE) begin
			status <= STATUS_POWER_UP;
		end
		else if (tick > POWER_UP_VCC_AND_CLK_STABLE && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP) begin
			status <= STATUS_PRE_CHARGE;
		end
		else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC) begin
			status <= STATUS_AUTO_REFRESH_1;
		end
		else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC) begin
			status <= STATUS_AUTO_REFRESH_2;
		end
		else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC + MRS_TO_NEW_COMMAND_tMRD) begin
			status <= STATUS_MODE_SET;
		end
		else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC + MRS_TO_NEW_COMMAND_tMRD) begin
			status <= STATUS_IDLE;
		end
		else begin
		
		end
	end

	always @(posedge clk or negedge rst_n) 
	begin
		case(status)
			STATUS_DEFAULT : begin
				S_CKE <= 0;
				S_nCS <= 1;
				S_nRAS <= 1;
				S_nCAS <= 1;
				S_nWE <= 1;
				S_DQM <= 0;
				S_A <= 0;
				S_A[10] <= 0;
				S_BA <= 0;
			end
			STATUS_POWER_UP : begin

				S_nCS <= 0;
				S_nRAS <= 1;
				S_nCAS <= 1;
				S_nWE <= 1;




			end
			STATUS_PRE_CHARGE : begin

				S_nCS <= 0;
				S_nRAS <= 0;
				S_nCAS <= 1;
				S_nWE <= 0;


				S_A[10] <= 1;

			end
			STATUS_AUTO_REFRESH_1 : begin
				S_CKE <= 1;
				S_nCS <= 0;
				S_nRAS <= 0;
				S_nCAS <= 0;
				S_nWE <= 1;




			end
			STATUS_AUTO_REFRESH_2 : begin
				S_CKE <= 1;
				S_nCS <= 0;
				S_nRAS <= 0;
				S_nCAS <= 0;
				S_nWE <= 1;




			end
			STATUS_MODE_SET : begin
				S_CKE <= 1;
				S_nCS <= 0;
				S_nRAS <= 0;
				S_nCAS <= 0;
				S_nWE <= 1;




				S_A <= 12'b00_0_00_010_0_011;
				S_BA <= 0;
			end
			STATUS_IDLE : begin











			end
		endcase
	end

	reg[15:0] refresh_tick;
	
	always @(posedge clk or negedge rst_n) 
	begin



		if (!rst_n) begin
			refresh_tick <= 0;
		end
		else begin
			if (refresh_tick == 15_000 / TICK_INTERVAL) begin
				refresh_tick <= 0;
			end
			else begin
				refresh_tick <= refresh_tick + 1;
			end
		end



	end

endmodule
module mmu(
	input clk, 
	input rst_n,
	
	output reg[15:0] S_DQ,
	output reg[11:0] S_A,
	output S_CLK,
	output reg[1:0] S_BA,
	output reg S_nCAS,
	output reg S_CKE,
	output reg S_nRAS,
	output reg S_nWE,
	output reg S_nCS,
	output reg[1:0] S_DQM
	
);




localparam TICK_INTERVAL = 20;
assign S_CLK = clk;
	












































	localparam STATUS_DEFAULT = 0;
	localparam STATUS_POWER_UP = 1;
	localparam STATUS_PRE_CHARGE = 2;
	localparam STATUS_AUTO_REFRESH_1 = 3;
	localparam STATUS_AUTO_REFRESH_2 = 4;
	localparam STATUS_MODE_SET = 5;
	localparam STATUS_IDLE = 6;
	
	reg[3:0] status;
	
	reg[15:0] tick, last_tick;
	
	localparam POWER_UP_VCC_AND_CLK_STABLE = 200_000 / TICK_INTERVAL;
	localparam RAS_PRECHARGE_TIME_tRP = 18 / TICK_INTERVAL + 1;
	localparam RAS_CYCLE_TIME_tRC = 60 / TICK_INTERVAL;
	localparam MRS_TO_NEW_COMMAND_tMRD = 2;
	


	always @(posedge clk or negedge rst_n) 
	begin
		if (!rst_n) begin
			tick <= 0;
			last_tick <= 0;
		end 
		else begin
			tick <= tick + 1;
		end	
		
		if (!rst_n) begin

			status <= STATUS_DEFAULT;
		end 
		else if (tick > 0 && tick <= POWER_UP_VCC_AND_CLK_STABLE) begin
			status <= STATUS_POWER_UP;
		end
		else if (tick > POWER_UP_VCC_AND_CLK_STABLE && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP) begin
			status <= STATUS_PRE_CHARGE;
		end
		else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC) begin
			status <= STATUS_AUTO_REFRESH_1;
		end
		else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC) begin
			status <= STATUS_AUTO_REFRESH_2;
		end
		else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC && tick <= POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC + MRS_TO_NEW_COMMAND_tMRD) begin
			status <= STATUS_MODE_SET;
		end
		else if (tick > POWER_UP_VCC_AND_CLK_STABLE + RAS_PRECHARGE_TIME_tRP + RAS_CYCLE_TIME_tRC + RAS_CYCLE_TIME_tRC + MRS_TO_NEW_COMMAND_tMRD) begin
			status <= STATUS_IDLE;
		end
		else begin
		
		end
	end

	always @(posedge clk or negedge rst_n) 
	begin
		case(status)
			STATUS_DEFAULT : begin
				S_CKE <= 0;
				S_nCS <= 1;
				S_nRAS <= 1;
				S_nCAS <= 1;
				S_nWE <= 1;
				S_DQM <= 0;
				S_A <= 0;
				S_A[10] <= 0;
				S_BA <= 0;
			end
			STATUS_POWER_UP : begin

				S_nCS <= 0;
				S_nRAS <= 1;
				S_nCAS <= 1;
				S_nWE <= 1;




			end
			STATUS_PRE_CHARGE : begin

				S_nCS <= 0;
				S_nRAS <= 0;
				S_nCAS <= 1;
				S_nWE <= 0;


				S_A[10] <= 1;

			end
			STATUS_AUTO_REFRESH_1 : begin
				S_CKE <= 1;
				S_nCS <= 0;
				S_nRAS <= 0;
				S_nCAS <= 0;
				S_nWE <= 1;




			end
			STATUS_AUTO_REFRESH_2 : begin
				S_CKE <= 1;
				S_nCS <= 0;
				S_nRAS <= 0;
				S_nCAS <= 0;
				S_nWE <= 1;




			end
			STATUS_MODE_SET : begin
				S_CKE <= 1;
				S_nCS <= 0;
				S_nRAS <= 0;
				S_nCAS <= 0;
				S_nWE <= 1;




				S_A <= 12'b00_0_00_010_0_011;
				S_BA <= 0;
			end
			STATUS_IDLE : begin











			end
		endcase
	end

	reg[15:0] refresh_tick;
	
	always @(posedge clk or negedge rst_n) 
	begin



		if (!rst_n) begin
			refresh_tick <= 0;
		end
		else begin
			if (refresh_tick == 15_000 / TICK_INTERVAL) begin
				refresh_tick <= 0;
			end
			else begin
				refresh_tick <= refresh_tick + 1;
			end
		end



	end

endmodule