data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:63: Unsupported: Ignoring delay on this delayed statement.\n #(T_PD);\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #(T_SER) adc_dco_int = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #(T_SER) adc_dco_int = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #(T_SER/2) adc_dco_p = adc_dco_int;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:80: Unsupported: Ignoring delay on this delayed statement.\n #(T_PD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #(T_Clk) adc_fr_p = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #(T_Clk) adc_fr_p = 1\'b1;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:50: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                                          : ... In instance adc_data_gen\nreg  [8:0] adc_count = 12\'h000;\n                       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:96: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h7\' generates 8 bits.\n                                                                                          : ... In instance adc_data_gen\n  adc_count <= 8\'h7;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:95: Operator EQ expects 9 bits on the RHS, but RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                          : ... In instance adc_data_gen\n if(adc_count == 8\'h0) begin\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:101: Operator GT expects 9 bits on the RHS, but RHS\'s CONST \'8\'h1\' generates 8 bits.\n                                                                                           : ... In instance adc_data_gen\n if(adc_count > 8\'h1) begin\n              ^\n%Warning-INFINITELOOP: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:64: Infinite loop (condition always true)\n                                                                                                 : ... In instance adc_data_gen\n forever begin\n ^~~~~~~\n%Warning-INFINITELOOP: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:72: Infinite loop (condition always true)\n                                                                                                 : ... In instance adc_data_gen\n forever begin\n ^~~~~~~\n%Warning-INFINITELOOP: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/adc-data-gen.v:82: Infinite loop (condition always true)\n                                                                                                 : ... In instance adc_data_gen\n forever begin\n ^~~~~~~\n%Error: Exiting due to 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adc_data_gen (
	input  wire       encode,

	output reg  [1:0] adc_out_1p,
	output wire [1:0] adc_out_1n,
	output reg  [1:0] adc_out_2p,
	output wire [1:0] adc_out_2n,

	output reg        adc_dco_p,
	output wire       adc_dco_n,
	output reg        adc_fr_p,
	output wire       adc_fr_n
	);

parameter T_Clk = 25;
parameter T_SER = T_Clk / 4.0;
parameter T_PD = 1.1 + T_SER;

reg  [11:0] adc_signal = 12'h000;
reg  [11:0] adc_signal_output;
reg  [8:0] adc_count = 12'h000;

reg  adc_dco_int;

assign adc_out_1n = ~adc_out_1p;
assign adc_out_2n = ~adc_out_2p;
assign adc_dco_n = ~adc_dco_p;
assign adc_fr_n = ~adc_fr_p;

initial begin
	adc_dco_p = 0;
	adc_dco_int = 0;

	#(T_PD);
	forever begin
		#(T_SER) adc_dco_int = 1'b1;
		#(T_SER) adc_dco_int = 1'b0;
	end

end

initial begin
	forever begin
		#(T_SER/2) adc_dco_p = adc_dco_int;
	end
end

initial begin
	adc_fr_p = 0;

	#(T_PD);
	adc_fr_p = 1'b1;
	forever begin
		#(T_Clk) adc_fr_p = 1'b0;
		#(T_Clk) adc_fr_p = 1'b1;
	end
end

always @(posedge encode) begin
	adc_signal <= adc_signal + 1'b1;
end

always @(posedge adc_dco_int or negedge adc_dco_int) begin
	adc_count <= adc_count - 1'b1;

	if(adc_count == 8'h0) begin
		adc_count <= 8'h7;
	end
end

always @(*) begin
	if(adc_count > 8'h1) begin
		adc_out_1p[0] = adc_signal_output[(2*(adc_count - 1)) - 1];
		adc_out_1p[1] = adc_signal_output[(2*(adc_count - 1)) - 2];
		adc_out_2p[0] = ~adc_signal_output[(2*(adc_count - 1)) - 1];
		adc_out_2p[1] = ~adc_signal_output[(2*(adc_count - 1)) - 2];
	end else begin
		adc_out_1p = 2'b00;
		adc_out_2p = 2'b00;
	end
end

always @(posedge adc_fr_p) begin
	adc_signal_output <= adc_signal;
end

endmodule
module adc_data_gen (
	input  wire       encode,

	output reg  [1:0] adc_out_1p,
	output wire [1:0] adc_out_1n,
	output reg  [1:0] adc_out_2p,
	output wire [1:0] adc_out_2n,

	output reg        adc_dco_p,
	output wire       adc_dco_n,
	output reg        adc_fr_p,
	output wire       adc_fr_n
	);


parameter T_Clk = 25;
parameter T_SER = T_Clk / 4.0;
parameter T_PD = 1.1 + T_SER;

reg  [11:0] adc_signal = 12'h000;
reg  [11:0] adc_signal_output;
reg  [8:0] adc_count = 12'h000;

reg  adc_dco_int;

assign adc_out_1n = ~adc_out_1p;
assign adc_out_2n = ~adc_out_2p;
assign adc_dco_n = ~adc_dco_p;
assign adc_fr_n = ~adc_fr_p;

initial begin
	adc_dco_p = 0;
	adc_dco_int = 0;

	#(T_PD);
	forever begin
		#(T_SER) adc_dco_int = 1'b1;
		#(T_SER) adc_dco_int = 1'b0;
	end

end

initial begin
	forever begin
		#(T_SER/2) adc_dco_p = adc_dco_int;
	end
end

initial begin
	adc_fr_p = 0;

	#(T_PD);
	adc_fr_p = 1'b1;
	forever begin
		#(T_Clk) adc_fr_p = 1'b0;
		#(T_Clk) adc_fr_p = 1'b1;
	end
end

always @(posedge encode) begin
	adc_signal <= adc_signal + 1'b1;
end

always @(posedge adc_dco_int or negedge adc_dco_int) begin
	adc_count <= adc_count - 1'b1;

	if(adc_count == 8'h0) begin
		adc_count <= 8'h7;
	end
end

always @(*) begin
	if(adc_count > 8'h1) begin
		adc_out_1p[0] = adc_signal_output[(2*(adc_count - 1)) - 1];
		adc_out_1p[1] = adc_signal_output[(2*(adc_count - 1)) - 2];
		adc_out_2p[0] = ~adc_signal_output[(2*(adc_count - 1)) - 1];
		adc_out_2p[1] = ~adc_signal_output[(2*(adc_count - 1)) - 2];
	end else begin
		adc_out_1p = 2'b00;
		adc_out_2p = 2'b00;
	end
end

always @(posedge adc_fr_p) begin
	adc_signal_output <= adc_signal;
end

endmodule