data/full_repos/permissive/143278/fpga_tests/ornor4.v
data/verilator_xmls/79ab9844-3b6b-42b1-8819-b002ba4a78af.xml
module ornor4(output wire O_OR, output wire O_NOR,
	      input wire I0, I1, I2, I3);

   assign O_OR  =  | {I0, I1, I2, I3};
   assign O_NOR = ~| {I0, I1, I2, I3};

endmodule
module ornor4(output wire O_OR, output wire O_NOR,
	      input wire I0, I1, I2, I3);


   assign O_OR  =  | {I0, I1, I2, I3};
   assign O_NOR = ~| {I0, I1, I2, I3};

endmodule