data/full_repos/permissive/220281533/mips_core.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/220281533/mips_core.v:65: Signal definition not found, creating implicitly: \'wd\'\n                                                                      : ... Suggested alternative: \'rd\'\n assign wd=32\'b10;\n        ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/220281533/mips_core.v:50: Cannot find file containing module: \'read_instructions\'\n read_instructions inst_mem (instruction, PC);\n ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220281533,data/full_repos/permissive/220281533/read_instructions\n             data/full_repos/permissive/220281533,data/full_repos/permissive/220281533/read_instructions.v\n             data/full_repos/permissive/220281533,data/full_repos/permissive/220281533/read_instructions.sv\n             read_instructions\n             read_instructions.v\n             read_instructions.sv\n             obj_dir/read_instructions\n             obj_dir/read_instructions.v\n             obj_dir/read_instructions.sv\n%Error: data/full_repos/permissive/220281533/mips_core.v:52: Cannot find file containing module: \'inst_parser\'\n inst_parser parse (opcode, rs, rt, rd, shamt, funct, immediate, address, instruction, PC);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220281533/mips_core.v:54: Cannot find file containing module: \'control_unit\'\n control_unit signals (read_reg_signal, write_reg_signal,read_mem_signal, write_mem_signal, regDst_signal, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/220281533/mips_core.v:57: Cannot find file containing module: \'ALU32bit\'\n ALU32bit alu_process (write_data, branch_signal, opcode, rs_content, rt_content, shamt, funct, immediate);\n ^~~~~~~~\n%Error: data/full_repos/permissive/220281533/mips_core.v:59: Cannot find file containing module: \'read_data_memory\'\n read_data_memory dataMemory (memory_read_data, write_data, rt_content, opcode, read_mem_signal, write_mem_signal);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220281533/mips_core.v:61: Cannot find file containing module: \'read_registers\'\n read_registers contents (rs_content, rt_content, write_data, rs, rt, rd, opcode, \n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/220281533/mips_core.v:65: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h2\' generates 32 bits.\n                                                                   : ... In instance mips_core\n assign wd=32\'b10;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/220281533/mips_core.v:69: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'address\' generates 26 bits.\n                                                                   : ... In instance mips_core\n   PC = address;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/220281533/mips_core.v:77: Operator ADD expects 32 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n                                                                   : ... In instance mips_core\n   PC = PC + 1 + $signed(immediate); \n               ^\n%Error: Exiting due to 6 error(s), 4 warning(s)\n'
module mips_core(clock);

	input clock;
	

	reg[31:0] PC = 32'b0;
	

	wire [31:0] instruction;
	

	wire [5:0] funct;
	wire [4:0] rs, rt, rd, shamt;
	wire [25:0] address;
	wire [15:0] immediate;
	wire [5:0] opcode;
	

	wire read_reg_signal, write_reg_signal, regDst_signal;
	wire read_mem_signal, write_mem_signal;
	wire branch_signal;
	

	wire [31:0] write_data, rs_content, rt_content, memory_read_data;
	
	

	read_instructions inst_mem (instruction, PC);

	inst_parser parse (opcode, rs, rt, rd, shamt, funct, immediate, address, instruction, PC);
	
	control_unit signals (read_reg_signal, write_reg_signal,read_mem_signal, write_mem_signal, regDst_signal, 
								 branch_signal, opcode, funct);
								 
	ALU32bit alu_process (write_data, branch_signal, opcode, rs_content, rt_content, shamt, funct, immediate);
	
	read_data_memory dataMemory (memory_read_data, write_data, rt_content, opcode, read_mem_signal, write_mem_signal);
	
	read_registers contents (rs_content, rt_content, write_data, rs, rt, rd, opcode, 
									read_reg_signal, write_reg_signal, regDst_signal, clock);
	

	assign wd=32'b10;
	always @(posedge clock) begin 

		if(opcode == 6'h2) begin
			PC = address;
		end

		else if(opcode == 6'h0 & funct == 6'h08)begin
			PC = rs_content;
		end

		else if(write_data == 0 & branch_signal == 1) begin
			PC = PC + 1 + $signed(immediate); 
		end
		else begin
			PC = PC+1;
		end
		$display("Program Counter = %b",PC);
		$display("ALU output = %d", write_data);
		$display("rs = %b, rt = %b, rd = %b",rs_content,rt_content,rd);
		$display("opcode = %b, funct = %b",opcode,funct);
		$display(" ");
	end 
	




	
endmodule
module mips_core(clock);


	input clock;
	

	reg[31:0] PC = 32'b0;
	

	wire [31:0] instruction;
	

	wire [5:0] funct;
	wire [4:0] rs, rt, rd, shamt;
	wire [25:0] address;
	wire [15:0] immediate;
	wire [5:0] opcode;
	

	wire read_reg_signal, write_reg_signal, regDst_signal;
	wire read_mem_signal, write_mem_signal;
	wire branch_signal;
	

	wire [31:0] write_data, rs_content, rt_content, memory_read_data;
	
	

	read_instructions inst_mem (instruction, PC);

	inst_parser parse (opcode, rs, rt, rd, shamt, funct, immediate, address, instruction, PC);
	
	control_unit signals (read_reg_signal, write_reg_signal,read_mem_signal, write_mem_signal, regDst_signal, 
								 branch_signal, opcode, funct);
								 
	ALU32bit alu_process (write_data, branch_signal, opcode, rs_content, rt_content, shamt, funct, immediate);
	
	read_data_memory dataMemory (memory_read_data, write_data, rt_content, opcode, read_mem_signal, write_mem_signal);
	
	read_registers contents (rs_content, rt_content, write_data, rs, rt, rd, opcode, 
									read_reg_signal, write_reg_signal, regDst_signal, clock);
	

	assign wd=32'b10;
	always @(posedge clock) begin 

		if(opcode == 6'h2) begin
			PC = address;
		end

		else if(opcode == 6'h0 & funct == 6'h08)begin
			PC = rs_content;
		end

		else if(write_data == 0 & branch_signal == 1) begin
			PC = PC + 1 + $signed(immediate); 
		end
		else begin
			PC = PC+1;
		end
		$display("Program Counter = %b",PC);
		$display("ALU output = %d", write_data);
		$display("rs = %b, rt = %b, rd = %b",rs_content,rt_content,rd);
		$display("opcode = %b, funct = %b",opcode,funct);
		$display(" ");
	end 
	




	
endmodule