data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v
1: b'%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v:47: Cannot find file containing module: \'DSP48A1\'\nDSP48A1 #(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6,data/full_repos/permissive/161356276/DSP48A1\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6,data/full_repos/permissive/161356276/DSP48A1.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6,data/full_repos/permissive/161356276/DSP48A1.sv\n             DSP48A1\n             DSP48A1.v\n             DSP48A1.sv\n             obj_dir/DSP48A1\n             obj_dir/DSP48A1.v\n             obj_dir/DSP48A1.sv\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v:96: Cannot find file containing module: \'DSP48A1\'\nDSP48A1 #(\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v:144: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s SEL generates 17 bits.\n                                                                                                                                                                  : ... In instance lm32_multiplier\nassign result[31:17] = r_full[16:0];\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v:146: Cannot find file containing module: \'DSP48A1\'\nDSP48A1 #(\n^~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module lm32_multiplier(
	input clk_i,
	input rst_i,
	input stall_x,
	input stall_m,
	input [31:0] operand_0,
	input [31:0] operand_1,
	output [31:0] result
);



wire [17:0] au = {3'd0, operand_0[31:17]};
wire [17:0] al = {1'b0, operand_0[16:0]};
wire [17:0] bu = {3'd0, operand_1[31:17]};
wire [17:0] bl = {1'b0, operand_1[16:0]};

wire [17:0] bl_forward;
wire [35:0] al_bl;

reg [16:0] result_low;
always @(posedge clk_i) begin
	if(rst_i)
		result_low <= 17'd0;
	else
		result_low <= al_bl[16:0];
end
assign result[16:0] = result_low;

DSP48A1 #(
	.A0REG(1),
	.A1REG(0),
	.B0REG(1),
	.B1REG(0),
	.CARRYINREG(0),
	.CARRYINSEL("OPMODE5"),
	.CARRYOUTREG(0),
	.CREG(0),
	.DREG(0),
	.MREG(1),
	.OPMODEREG(0),
	.PREG(0),
	.RSTTYPE("SYNC")
) D1 (
	.BCOUT(bl_forward),
	.PCOUT(),
	.CARRYOUT(),
	.CARRYOUTF(),
	.M(al_bl),
	.P(),
	.PCIN(),
	.CLK(clk_i),
	.OPMODE(8'd1),
	.A(al),
	.B(bl),
	.C(48'h0),
	.CARRYIN(),
	.D(18'b0),
	.CEA(~stall_x),
	.CEB(~stall_x),
	.CEC(1'b0),
	.CECARRYIN(1'b0),
	.CED(1'b0),
	.CEM(~stall_m),
	.CEOPMODE(1'b0),
	.CEP(1'b1),
	.RSTA(rst_i),
	.RSTB(rst_i),
	.RSTC(1'b0),
	.RSTCARRYIN(1'b0),
	.RSTD(1'b0),
	.RSTM(rst_i),
	.RSTOPMODE(1'b0),
	.RSTP(1'b0)
);

wire [47:0] au_bl_sum;

DSP48A1 #(
	.A0REG(1),
	.A1REG(0),
	.B0REG(0),
	.B1REG(0),
	.CARRYINREG(0),
	.CARRYINSEL("OPMODE5"),
	.CARRYOUTREG(0),
	.CREG(0),
	.DREG(0),
	.MREG(1),
	.OPMODEREG(0),
	.PREG(0),
	.RSTTYPE("SYNC")
) D2 (
	.BCOUT(),
	.PCOUT(au_bl_sum),
	.CARRYOUT(),
	.CARRYOUTF(),
	.M(),
	.P(),
	.PCIN(),
	.CLK(clk_i),
	.OPMODE(8'd13),
	.A(au),
	.B(bl_forward),
	.C({31'd0, al_bl[33:17]}),
	.CARRYIN(),
	.D(18'h0),
	.CEA(~stall_x),
	.CEB(1'b0),
	.CEC(1'b0),
	.CECARRYIN(1'b0),
	.CED(1'b0),
	.CEM(~stall_m),
	.CEOPMODE(1'b0),
	.CEP(1'b0),
	.RSTA(rst_i),
	.RSTB(1'b0),
	.RSTC(1'b0),
	.RSTCARRYIN(1'b0),
	.RSTD(1'b0),
	.RSTM(rst_i),
	.RSTOPMODE(1'b0),
	.RSTP(1'b0)
);

wire [47:0] r_full;
assign result[31:17] = r_full[16:0];

DSP48A1 #(
	.A0REG(1),
	.A1REG(0),
	.B0REG(1),
	.B1REG(0),
	.CARRYINREG(0),
	.CARRYINSEL("OPMODE5"),
	.CARRYOUTREG(0),
	.CREG(0),
	.DREG(0),
	.MREG(1),
	.OPMODEREG(0),
	.PREG(1),
	.RSTTYPE("SYNC")
) D3 (
	.BCOUT(),
	.PCOUT(),
	.CARRYOUT(),
	.CARRYOUTF(),
	.M(),
	.P(r_full),
	.PCIN(au_bl_sum),
	.CLK(clk_i),
	.OPMODE(8'd5),
	.A(bu),
	.B(al),
	.C(48'b0),
	.CARRYIN(),
	.D(18'b0),
	.CEA(~stall_x),
	.CEB(~stall_x),
	.CEC(1'b0),
	.CECARRYIN(1'b0),
	.CED(1'b0),
	.CEM(~stall_m),
	.CEOPMODE(1'b0),
	.CEP(1'b1),
	.RSTA(rst_i),
	.RSTB(rst_i),
	.RSTC(1'b0),
	.RSTCARRYIN(1'b0),
	.RSTD(1'b0),
	.RSTM(rst_i),
	.RSTOPMODE(1'b0),
	.RSTP(rst_i)
);

endmodule
module lm32_multiplier(
	input clk_i,
	input rst_i,
	input stall_x,
	input stall_m,
	input [31:0] operand_0,
	input [31:0] operand_1,
	output [31:0] result
);




wire [17:0] au = {3'd0, operand_0[31:17]};
wire [17:0] al = {1'b0, operand_0[16:0]};
wire [17:0] bu = {3'd0, operand_1[31:17]};
wire [17:0] bl = {1'b0, operand_1[16:0]};

wire [17:0] bl_forward;
wire [35:0] al_bl;

reg [16:0] result_low;
always @(posedge clk_i) begin
	if(rst_i)
		result_low <= 17'd0;
	else
		result_low <= al_bl[16:0];
end
assign result[16:0] = result_low;

DSP48A1 #(
	.A0REG(1),
	.A1REG(0),
	.B0REG(1),
	.B1REG(0),
	.CARRYINREG(0),
	.CARRYINSEL("OPMODE5"),
	.CARRYOUTREG(0),
	.CREG(0),
	.DREG(0),
	.MREG(1),
	.OPMODEREG(0),
	.PREG(0),
	.RSTTYPE("SYNC")
) D1 (
	.BCOUT(bl_forward),
	.PCOUT(),
	.CARRYOUT(),
	.CARRYOUTF(),
	.M(al_bl),
	.P(),
	.PCIN(),
	.CLK(clk_i),
	.OPMODE(8'd1),
	.A(al),
	.B(bl),
	.C(48'h0),
	.CARRYIN(),
	.D(18'b0),
	.CEA(~stall_x),
	.CEB(~stall_x),
	.CEC(1'b0),
	.CECARRYIN(1'b0),
	.CED(1'b0),
	.CEM(~stall_m),
	.CEOPMODE(1'b0),
	.CEP(1'b1),
	.RSTA(rst_i),
	.RSTB(rst_i),
	.RSTC(1'b0),
	.RSTCARRYIN(1'b0),
	.RSTD(1'b0),
	.RSTM(rst_i),
	.RSTOPMODE(1'b0),
	.RSTP(1'b0)
);

wire [47:0] au_bl_sum;

DSP48A1 #(
	.A0REG(1),
	.A1REG(0),
	.B0REG(0),
	.B1REG(0),
	.CARRYINREG(0),
	.CARRYINSEL("OPMODE5"),
	.CARRYOUTREG(0),
	.CREG(0),
	.DREG(0),
	.MREG(1),
	.OPMODEREG(0),
	.PREG(0),
	.RSTTYPE("SYNC")
) D2 (
	.BCOUT(),
	.PCOUT(au_bl_sum),
	.CARRYOUT(),
	.CARRYOUTF(),
	.M(),
	.P(),
	.PCIN(),
	.CLK(clk_i),
	.OPMODE(8'd13),
	.A(au),
	.B(bl_forward),
	.C({31'd0, al_bl[33:17]}),
	.CARRYIN(),
	.D(18'h0),
	.CEA(~stall_x),
	.CEB(1'b0),
	.CEC(1'b0),
	.CECARRYIN(1'b0),
	.CED(1'b0),
	.CEM(~stall_m),
	.CEOPMODE(1'b0),
	.CEP(1'b0),
	.RSTA(rst_i),
	.RSTB(1'b0),
	.RSTC(1'b0),
	.RSTCARRYIN(1'b0),
	.RSTD(1'b0),
	.RSTM(rst_i),
	.RSTOPMODE(1'b0),
	.RSTP(1'b0)
);

wire [47:0] r_full;
assign result[31:17] = r_full[16:0];

DSP48A1 #(
	.A0REG(1),
	.A1REG(0),
	.B0REG(1),
	.B1REG(0),
	.CARRYINREG(0),
	.CARRYINSEL("OPMODE5"),
	.CARRYOUTREG(0),
	.CREG(0),
	.DREG(0),
	.MREG(1),
	.OPMODEREG(0),
	.PREG(1),
	.RSTTYPE("SYNC")
) D3 (
	.BCOUT(),
	.PCOUT(),
	.CARRYOUT(),
	.CARRYOUTF(),
	.M(),
	.P(r_full),
	.PCIN(au_bl_sum),
	.CLK(clk_i),
	.OPMODE(8'd5),
	.A(bu),
	.B(al),
	.C(48'b0),
	.CARRYIN(),
	.D(18'b0),
	.CEA(~stall_x),
	.CEB(~stall_x),
	.CEC(1'b0),
	.CECARRYIN(1'b0),
	.CED(1'b0),
	.CEM(~stall_m),
	.CEOPMODE(1'b0),
	.CEP(1'b1),
	.RSTA(rst_i),
	.RSTB(rst_i),
	.RSTC(1'b0),
	.RSTCARRYIN(1'b0),
	.RSTD(1'b0),
	.RSTM(rst_i),
	.RSTOPMODE(1'b0),
	.RSTP(rst_i)
);

endmodule