data/full_repos/permissive/119187354/CPU.v
1: b"%Error: data/full_repos/permissive/119187354/CPU.v:21: Cannot find file containing module: 'Register_4bit'\n Register_4bit RegA (CLOCK_50,ALU_OUT,LD[0],~KEY[0],REG_A);\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119187354,data/full_repos/permissive/119187354/Register_4bit\n             data/full_repos/permissive/119187354,data/full_repos/permissive/119187354/Register_4bit.v\n             data/full_repos/permissive/119187354,data/full_repos/permissive/119187354/Register_4bit.sv\n             Register_4bit\n             Register_4bit.v\n             Register_4bit.sv\n             obj_dir/Register_4bit\n             obj_dir/Register_4bit.v\n             obj_dir/Register_4bit.sv\n%Error: data/full_repos/permissive/119187354/CPU.v:22: Cannot find file containing module: 'Register_4bit'\n Register_4bit RegB (CLOCK_50,ALU_OUT,LD[1],~KEY[0],REG_B);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/119187354/CPU.v:23: Cannot find file containing module: 'Register_4bit'\n Register_4bit OutputReg (CLOCK_50,ALU_OUT,LD[2],~KEY[0],OUTPUT);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/119187354/CPU.v:24: Cannot find file containing module: 'Counter_4bit'\n Counter_4bit Counter (CLOCK_50,ALU_OUT,LD[3],~KEY[0],ROM_ADDR);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/119187354/CPU.v:26: Cannot find file containing module: 'MUX_4IN_1OUT'\n MUX_4IN_1OUT Mux (REG_A,REG_B,SW[3:0],DEF,SELECT,MUX_OUT);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/119187354/CPU.v:28: Cannot find file containing module: 'ALU'\n ALU Alu (MUX_OUT,ROM_DATA[3:0],ALU_OUT,ALU_OUT_C);\n ^~~\n%Error: data/full_repos/permissive/119187354/CPU.v:30: Cannot find file containing module: 'DFF_1bit'\n DFF_1bit Dff (CLOCK_50,ALU_OUT,~KEY[0],C);\n ^~~~~~~~\n%Error: data/full_repos/permissive/119187354/CPU.v:32: Cannot find file containing module: 'ROM'\n ROM Rom (ROM_ADDR,ROM_DATA);\n ^~~\n%Error: data/full_repos/permissive/119187354/CPU.v:34: Cannot find file containing module: 'Decoder'\n Decoder Decoder (ROM_DATA[7:4],C,SELECT,LD);\n ^~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module CPU(
	input [9:0]SW,
	output [9:0]LEDR,
	input CLOCK_50,
	input [1:0]KEY
);
	
	wire [3:0]REG_A,REG_B,OUTPUT;
	wire [3:0]LD;
	wire [1:0]SELECT;
	wire [3:0]MUX_OUT;
	wire [3:0]ALU_OUT;
	wire [3:0]ROM_ADDR;
	wire [7:0]ROM_DATA;
	wire ALU_OUT_C,C;
	wire [3:0]INPUT;
	wire [3:0]DEF;
	
	assign DEF = 4'b0000;
	
	Register_4bit RegA (CLOCK_50,ALU_OUT,LD[0],~KEY[0],REG_A);
	Register_4bit RegB (CLOCK_50,ALU_OUT,LD[1],~KEY[0],REG_B);
	Register_4bit OutputReg (CLOCK_50,ALU_OUT,LD[2],~KEY[0],OUTPUT);
	Counter_4bit Counter (CLOCK_50,ALU_OUT,LD[3],~KEY[0],ROM_ADDR);
	
	MUX_4IN_1OUT Mux (REG_A,REG_B,SW[3:0],DEF,SELECT,MUX_OUT);
	
	ALU Alu (MUX_OUT,ROM_DATA[3:0],ALU_OUT,ALU_OUT_C);
	
	DFF_1bit Dff (CLOCK_50,ALU_OUT,~KEY[0],C);
	
	ROM Rom (ROM_ADDR,ROM_DATA);
	
	Decoder Decoder (ROM_DATA[7:4],C,SELECT,LD);
	
	assign LEDR[9:6] = OUTPUT[3:0];
	assign LEDR[3:0] = SW[3:0];
	assign LEDR[5:4] = ~KEY[1:0];
	
endmodule
module CPU(
	input [9:0]SW,
	output [9:0]LEDR,
	input CLOCK_50,
	input [1:0]KEY
);

	
	wire [3:0]REG_A,REG_B,OUTPUT;
	wire [3:0]LD;
	wire [1:0]SELECT;
	wire [3:0]MUX_OUT;
	wire [3:0]ALU_OUT;
	wire [3:0]ROM_ADDR;
	wire [7:0]ROM_DATA;
	wire ALU_OUT_C,C;
	wire [3:0]INPUT;
	wire [3:0]DEF;
	
	assign DEF = 4'b0000;
	
	Register_4bit RegA (CLOCK_50,ALU_OUT,LD[0],~KEY[0],REG_A);
	Register_4bit RegB (CLOCK_50,ALU_OUT,LD[1],~KEY[0],REG_B);
	Register_4bit OutputReg (CLOCK_50,ALU_OUT,LD[2],~KEY[0],OUTPUT);
	Counter_4bit Counter (CLOCK_50,ALU_OUT,LD[3],~KEY[0],ROM_ADDR);
	
	MUX_4IN_1OUT Mux (REG_A,REG_B,SW[3:0],DEF,SELECT,MUX_OUT);
	
	ALU Alu (MUX_OUT,ROM_DATA[3:0],ALU_OUT,ALU_OUT_C);
	
	DFF_1bit Dff (CLOCK_50,ALU_OUT,~KEY[0],C);
	
	ROM Rom (ROM_ADDR,ROM_DATA);
	
	Decoder Decoder (ROM_DATA[7:4],C,SELECT,LD);
	
	assign LEDR[9:6] = OUTPUT[3:0];
	assign LEDR[3:0] = SW[3:0];
	assign LEDR[5:4] = ~KEY[1:0];
	
endmodule