data/full_repos/permissive/20289584/mux_ledd.v
data/verilator_xmls/0df1d05e-8773-4f14-bd4a-3a2bd6774a73.xml
module mux_ledd(input select,s0,rst, input[1:0] d, output reg q );

reg sel;
always @( select)
begin

					if (select==0)
						begin
							q = d[0];
						end
					else
						q = d[1];		

end
endmodule
module mux_ledd(input select,s0,rst, input[1:0] d, output reg q );


reg sel;
always @( select)
begin

					if (select==0)
						begin
							q = d[0];
						end
					else
						q = d[1];		

end
endmodule