data/full_repos/permissive/135077285/hazardUnit.v
data/verilator_xmls/3fa12330-5a26-4abc-a8dc-6a7549a9957c.xml
module hazardUnit (

  input wire reset,
  input wire [4:0] rt,
  input wire memRead,
  input wire [31:0] instruction,


  output reg controller,
  output reg hzdPcWrite,
  output reg hzdIfIdWrite
);

  always @(reset) begin
    hzdPcWrite <= 1'b0;
    hzdIfIdWrite <= 1'b0;
    controller <= 1'b1;
  end


  always @ (*) begin
    if (memRead && ((rt == instruction[25:21]) || (rt == instruction[20:16]))) begin
      controller <= 1'b1;
      hzdIfIdWrite <= 1'b0;
      hzdPcWrite <= 1'b0;
    end else begin
      controller <= 1'b0;
      hzdIfIdWrite <= 1'b1;
      hzdPcWrite <= 1'b1;
    end
  end
endmodule
module hazardUnit (

  input wire reset,
  input wire [4:0] rt,
  input wire memRead,
  input wire [31:0] instruction,


  output reg controller,
  output reg hzdPcWrite,
  output reg hzdIfIdWrite
);


  always @(reset) begin
    hzdPcWrite <= 1'b0;
    hzdIfIdWrite <= 1'b0;
    controller <= 1'b1;
  end


  always @ (*) begin
    if (memRead && ((rt == instruction[25:21]) || (rt == instruction[20:16]))) begin
      controller <= 1'b1;
      hzdIfIdWrite <= 1'b0;
      hzdPcWrite <= 1'b0;
    end else begin
      controller <= 1'b0;
      hzdIfIdWrite <= 1'b1;
      hzdPcWrite <= 1'b1;
    end
  end
endmodule