data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:96: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:112: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-WIDTH: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:72: Operator ASSIGN expects 73 bits on the Assign RHS, but Assign RHS\'s CONST \'80\'h0\' generates 80 bits.\n                                                                                               : ... In instance tb_idle_pattern_inserter\n    in_data      = 80\'b0;\n                 ^\n%Error: data/full_repos/permissive/172201645/test_benches/tb_idle_pattern_inserter.v:118: Cannot find file containing module: \'idle_pattern_inserter\'\nidle_pattern_inserter  i_idle_pattern_inserter(\n^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/idle_pattern_inserter\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/idle_pattern_inserter.v\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/idle_pattern_inserter.sv\n             idle_pattern_inserter\n             idle_pattern_inserter.v\n             idle_pattern_inserter.sv\n             obj_dir/idle_pattern_inserter\n             obj_dir/idle_pattern_inserter.v\n             obj_dir/idle_pattern_inserter.sv\n%Error: Exiting due to 1 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_idle_pattern_inserter;

    reg clk = 1'b1;

    reg channel_ready = 1'b1;
    reg source_ready  = 1'b1;

    reg  [72:0] in_data;
    wire [71:0] out_data;
    reg  [15:0] count;

initial begin
    
    in_data      = 80'b0;
    channel_ready = 1'b1;
    source_ready  = 1'b1;
    count         =    0;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
   
    forever begin
        case(count)
           100: in_data = 73'h1444333332222211111;
           200: in_data = 73'h0444333332222211111;
        endcase
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        count = count + 1;
    end
end

idle_pattern_inserter  i_idle_pattern_inserter(
    .clk            (clk),
    .channel_ready  (channel_ready),
    .source_ready   (source_ready),
    .in_data        (in_data),
    .out_data       (out_data)
);

endmodule
module tb_idle_pattern_inserter;


    reg clk = 1'b1;

    reg channel_ready = 1'b1;
    reg source_ready  = 1'b1;

    reg  [72:0] in_data;
    wire [71:0] out_data;
    reg  [15:0] count;

initial begin
    
    in_data      = 80'b0;
    channel_ready = 1'b1;
    source_ready  = 1'b1;
    count         =    0;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
   
    forever begin
        case(count)
           100: in_data = 73'h1444333332222211111;
           200: in_data = 73'h0444333332222211111;
        endcase
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        count = count + 1;
    end
end

idle_pattern_inserter  i_idle_pattern_inserter(
    .clk            (clk),
    .channel_ready  (channel_ready),
    .source_ready   (source_ready),
    .in_data        (in_data),
    .out_data       (out_data)
);

endmodule