data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v
 line:47: before: "end"
1: b'%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:26: Unsupported: Ignoring delay on this delayed statement.\n  reg_f4 <= 1\'b0; reg_f5 <= 1\'b0; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00001; RT_f3 <= 5\'b00010; #100\n                                                                                                                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:28: Unsupported: Ignoring delay on this delayed statement.\n  reg_f4 <= 1\'b1; reg_f5 <= 1\'b0; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00001; RT_f3 <= 5\'b00010; #100\n                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:30: Unsupported: Ignoring delay on this delayed statement.\n  reg_f4 <= 1\'b0; reg_f5 <= 1\'b1; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00001; RT_f3 <= 5\'b00010; #100\n                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:32: Unsupported: Ignoring delay on this delayed statement.\n    reg_f4 <= 1\'b1; reg_f5 <= 1\'b0; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00100; RT_f3 <= 5\'b00010; #100\n                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:34: Unsupported: Ignoring delay on this delayed statement.\n  reg_f4 <= 1\'b1; reg_f5 <= 1\'b0; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00110; RT_f3 <= 5\'b00100; #100\n                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:36: Unsupported: Ignoring delay on this delayed statement.\n    reg_f4 <= 1\'b0; reg_f5 <= 1\'b1; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b10000; RT_f3 <= 5\'b00010; #100\n                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:38: Unsupported: Ignoring delay on this delayed statement.\n  reg_f4 <= 1\'b0; reg_f5 <= 1\'b1; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00110; RT_f3 <= 5\'b10000; #100\n                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:40: Unsupported: Ignoring delay on this delayed statement.\n    reg_f4 <= 1\'b1; reg_f5 <= 1\'b0; escrita_f4 <= 5\'b00100; escrita_f5 <= 5\'b10000; RS_f3 <= 5\'b00100; RT_f3 <= 5\'b00100; #100\n                                                                                                                          ^\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Foward.v:47: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_Foward ();
	wire clock;

	reg reg_f4, reg_f5;

	reg [4:0] escrita_f4, escrita_f5;

	reg [4:0] RS_f3, RT_f3;

	wire [1:0] fw_A, fw_B;
		
	Foward teste_foward(
		.clock(clock), 
		.reg_f4(reg_f4), 
		.reg_f5(reg_f5), 
		.escrita_f4(escrita_f4), 
		.escrita_f5(escrita_f5), 
		.RS_f3(RS_f3), 
		.RT_f3(RT_f3), 
		.fw_A(fw_A), 
		.fw_B(fw_B)
	);
	
	initial begin

		reg_f4 <= 1'b0; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00001;	RT_f3 <= 5'b00010; #100

		reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00001;	RT_f3 <= 5'b00010; #100

		reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00001;	RT_f3 <= 5'b00010; #100

	   reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00100;	RT_f3 <= 5'b00010; #100

		reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00110;	RT_f3 <= 5'b00100; #100

	   reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b10000;	RT_f3 <= 5'b00010; #100

		reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00110;	RT_f3 <= 5'b10000; #100

	   reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00100;	RT_f3 <= 5'b00100; #100

	   reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b10000;	RT_f3 <= 5'b10000; #100



		
	end
endmodule
module TB_Foward ();

	wire clock;

	reg reg_f4, reg_f5;

	reg [4:0] escrita_f4, escrita_f5;

	reg [4:0] RS_f3, RT_f3;

	wire [1:0] fw_A, fw_B;
		
	Foward teste_foward(
		.clock(clock), 
		.reg_f4(reg_f4), 
		.reg_f5(reg_f5), 
		.escrita_f4(escrita_f4), 
		.escrita_f5(escrita_f5), 
		.RS_f3(RS_f3), 
		.RT_f3(RT_f3), 
		.fw_A(fw_A), 
		.fw_B(fw_B)
	);
	
	initial begin

		reg_f4 <= 1'b0; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00001;	RT_f3 <= 5'b00010; #100

		reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00001;	RT_f3 <= 5'b00010; #100

		reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00001;	RT_f3 <= 5'b00010; #100

	   reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00100;	RT_f3 <= 5'b00010; #100

		reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00110;	RT_f3 <= 5'b00100; #100

	   reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b10000;	RT_f3 <= 5'b00010; #100

		reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00110;	RT_f3 <= 5'b10000; #100

	   reg_f4 <= 1'b1; reg_f5 <= 1'b0; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b00100;	RT_f3 <= 5'b00100; #100

	   reg_f4 <= 1'b0; reg_f5 <= 1'b1; escrita_f4 <= 5'b00100; escrita_f5 <= 5'b10000; RS_f3 <= 5'b10000;	RT_f3 <= 5'b10000; #100



		
	end
endmodule