data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v
1: b'%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:18: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_1, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:19: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_1, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:20: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_1, coutb, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:21: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(gnd, net_11, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:22: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, coutb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:23: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, net_23, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:24: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_23, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:25: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_7(gnd, net_23, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:26: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_8(net_23, sb, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:27: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_9(gnd, net_33, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:28: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_10(net_33, net_32, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:29: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_11(net_32, sb, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:30: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_12(gnd, cout, coutb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:31: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_13(gnd, s, sb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:32: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(sb, net_92, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:33: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(net_92, net_90, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:34: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_90, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:35: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(sb, net_94, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:36: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(net_94, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:37: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_6(net_94, vdd, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:38: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_7(net_94, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:39: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_8(cout, vdd, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:40: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_9(net_95, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:41: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_10(coutb, net_95, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:42: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_11(net_111, vdd, a);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:43: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_12(net_111, vdd, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:44: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_13(coutb, net_111, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:45: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_14(s, vdd, sb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:54: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, y, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:55: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:67: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_5, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:68: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_5, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:69: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:70: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:82: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_0, net_1, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:83: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_0, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:84: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, Y, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:85: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(net_11, Y, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:86: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_11, net_1);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:87: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_1, vdd, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:88: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_1, vdd, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:89: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(Y, vdd, net_1);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:90: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_28, vdd, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.v:91: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(Y, net_28, A);\n          ^~~~~~\n%Error: Exiting due to 44 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module muddlib07__inv_1x(a, y);
  input a;
  output y;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(gnd, y, a);
  tranif0 pmos_0(y, vdd, a);
endmodule
module muddlib07__inv_1x(a, y);

  input a;
  output y;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(gnd, y, a);
  tranif0 pmos_0(y, vdd, a);
endmodule