data/full_repos/permissive/150266237/parte2.v
1: b'%Error: data/full_repos/permissive/150266237/parte2.v:119: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile ("out.vcd"); \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/150266237/parte2.v:120: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars; \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/150266237/parte2.v:125: Unsupported or unknown PLI call: $monitor\n     $monitor($time," c %b res %b a %b s %d smem %d sporta %d",c,res,a,saida,saida1,saida2);\n     ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:126: Unsupported: Ignoring delay on this delayed statement.\n      #1 res=0; a=0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:127: Unsupported: Ignoring delay on this delayed statement.\n      #1 res=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:128: Unsupported: Ignoring delay on this delayed statement.\n      #8 a=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:129: Unsupported: Ignoring delay on this delayed statement.\n      #16 a=0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:130: Unsupported: Ignoring delay on this delayed statement.\n      #12 a=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:131: Unsupported: Ignoring delay on this delayed statement.\n      #4;\n      ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
reg c,res,a;
wire [2:0] saida;
wire [2:0] saida1;
wire [2:0] saida2;

stateCase estadocase(c,res,a,saida);
statePorta estadoporta(c,res,a,saida2);
stateMem estadoMem(c,res,a,saida1);


initial
    c = 1'b0;
  always
    c= #(1) ~c;


initial  begin
     $dumpfile ("out.vcd"); 
     $dumpvars; 
   end 

  initial 
    begin
     $monitor($time," c %b res %b a %b s %d smem %d sporta %d",c,res,a,saida,saida1,saida2);
      #1 res=0; a=0;
      #1 res=1;
      #8 a=1;
      #16 a=0;
      #12 a=1;
      #4;
      $finish ;
    end
endmodule
module main;

reg c,res,a;
wire [2:0] saida;
wire [2:0] saida1;
wire [2:0] saida2;

stateCase estadocase(c,res,a,saida);
statePorta estadoporta(c,res,a,saida2);
stateMem estadoMem(c,res,a,saida1);


initial
    c = 1'b0;
  always
    c= #(1) ~c;


initial  begin
     $dumpfile ("out.vcd"); 
     $dumpvars; 
   end 

  initial 
    begin
     $monitor($time," c %b res %b a %b s %d smem %d sporta %d",c,res,a,saida,saida1,saida2);
      #1 res=0; a=0;
      #1 res=1;
      #8 a=1;
      #16 a=0;
      #12 a=1;
      #4;
      $finish ;
    end
endmodule