data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v
Syntax Error
1: b'%Error: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:43: Cannot find file containing module: \'data_extract\'\ndata_extract #(.N(N),.es(es)) uut_de1(.in(xin1), .rc(rc1), .regime(regime1), .exp(e1), .mant(mant1), .Lshift(Lshift1));\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/112176817/Posit-Multiplier,data/full_repos/permissive/112176817/data_extract\n             data/full_repos/permissive/112176817/Posit-Multiplier,data/full_repos/permissive/112176817/data_extract.v\n             data/full_repos/permissive/112176817/Posit-Multiplier,data/full_repos/permissive/112176817/data_extract.sv\n             data_extract\n             data_extract.v\n             data_extract.sv\n             obj_dir/data_extract\n             obj_dir/data_extract.v\n             obj_dir/data_extract.sv\n%Error: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:44: Cannot find file containing module: \'data_extract\'\ndata_extract #(.N(N),.es(es)) uut_de2(.in(xin2), .rc(rc2), .regime(regime2), .exp(e2), .mant(mant2), .Lshift(Lshift2));\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:56: Operator NEGATE expects 6 bits on the LHS, but LHS\'s VARREF \'regime1\' generates 4 bits.\n                                                                                     : ... In instance posit_mult\nwire [Bs+1:0] r1 = rc1 ? {2\'b0,regime1} : -regime1;\n                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:57: Operator NEGATE expects 6 bits on the LHS, but LHS\'s VARREF \'regime2\' generates 4 bits.\n                                                                                     : ... In instance posit_mult\nwire [Bs+1:0] r2 = rc2 ? {2\'b0,regime2} : -regime2;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:58: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'mult_m_ovf\' generates 1 bits.\n                                                                                     : ... In instance posit_mult\nwire [Bs+es+1:0] mult_e  =  {r1, e1} + {r2, e2} + mult_m_ovf;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:61: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 9 bits.\n                                                                                     : ... In instance posit_mult\nwire [es+Bs:0] mult_eN = mult_e[es+Bs+1] ? -mult_e : mult_e;\n                       ^\n%Error: data/full_repos/permissive/112176817/Posit-Multiplier/posit_mult.v:71: Cannot find file containing module: \'DSR_right_N_S\'\nDSR_right_N_S #(.N(2*N), .S(Bs+1)) dsr2 (.a(tmp_o), .b(r_o[Bs] ? {Bs{1\'b1}} : r_o), .c(tmp1_o));\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction
function [31:0] log2;

input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction