data/full_repos/permissive/192449736/WS2812.v
1: b'%Error: data/full_repos/permissive/192449736/WS2812.v:46: Cannot find file containing module: \'RAM2P\'\nRAM2P ram(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/192449736,data/full_repos/permissive/192449736/RAM2P\n             data/full_repos/permissive/192449736,data/full_repos/permissive/192449736/RAM2P.v\n             data/full_repos/permissive/192449736,data/full_repos/permissive/192449736/RAM2P.sv\n             RAM2P\n             RAM2P.v\n             RAM2P.sv\n             obj_dir/RAM2P\n             obj_dir/RAM2P.v\n             obj_dir/RAM2P.sv\n%Warning-WIDTH: data/full_repos/permissive/192449736/WS2812.v:70: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'LED_IDX\' generates 9 bits.\n                                                                : ... In instance WS2812\n  if (LED_IDX+1 > ledCount && LED_IDX)\n                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/192449736/WS2812.v:110: Operator LT expects 13 bits on the RHS, but RHS\'s VARREF \'TH\' generates 7 bits.\n                                                                 : ... In instance WS2812\n   rCTRL_OUT<=(signal_timer < TH)?1:0; \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/192449736/WS2812.v:111: Operator GTE expects 13 bits on the RHS, but RHS\'s VARREF \'TE\' generates 7 bits.\n                                                                 : ... In instance WS2812\n   if (signal_timer >= TE)\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/192449736/WS2812.v:142: Operator GTE expects 13 bits on the RHS, but RHS\'s VARREF \'TE\' generates 7 bits.\n                                                                 : ... In instance WS2812\n   if (signal_timer >= TE) begin\n                    ^~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module WS2812(iSIGNAL_CLOCK,iDATA_CLOCK,dR, dG, dB,oCTRL_OUT, LED_IDX, ext_reset);
	input 		iSIGNAL_CLOCK;
	input 		iDATA_CLOCK;
	input [7:0]	dR, dG, dB;
	input [8:0] LED_IDX;
	input ext_reset;
	output 		oCTRL_OUT;
	


	parameter T0H = 40;
	parameter T1H = 80; 
	parameter T0L = 85;
	parameter T1L = 45;
	parameter TRS = 5100;

	


wire [23:0] wRamData;

wire [23:0] wCDATA;
wire true;


reg wRCLK;
reg [8:0] read_address;
reg [8:0] ledCount;
reg [12:0] signal_timer;
reg [4:0] bit_counter;
reg [23:0] srCDATA;
reg rCTRL_OUT;
reg sig_reset;
reg [6:0] TH;
reg [6:0] TE;

assign true=1;
assign oCTRL_OUT=rCTRL_OUT;
assign wRamData={dG,dR,dB};


RAM2P ram(
	.data(wRamData),
	.wraddress(LED_IDX),
	.wrclock(iDATA_CLOCK),
	.wren(true),
	
	.rdaddress(read_address),
	.rdclock(iSIGNAL_CLOCK),
	.q(wCDATA)
);



always @(posedge iDATA_CLOCK or posedge ext_reset)
begin
	if (ext_reset) begin
		ledCount=0;
	end
	else begin
		if (LED_IDX+1 > ledCount && LED_IDX)
		begin
			ledCount <= LED_IDX+1;
		end
	end
end








always @(posedge iSIGNAL_CLOCK or posedge ext_reset)
begin
	if (ext_reset) begin
		read_address=0;
		
		bit_counter=0;
		signal_timer=0;
		rCTRL_OUT=0;
		sig_reset=0;
	end
	else begin
		if (signal_timer==0 && ~sig_reset)
		begin
			rCTRL_OUT<=1;
		end
		if (~sig_reset) begin
			if (srCDATA[23])
			begin
				TH<=T1H;
				TE<=T1H+T1L;
			end
			else
			begin
				TH<=T0H;
				TE<=T0H+T0L;
			end
			rCTRL_OUT<=(signal_timer < TH)?1:0;
			if (signal_timer >= TE)
			begin
				srCDATA<=srCDATA<<1;
				if (bit_counter == 11) begin
					if (read_address >= ledCount) begin
						read_address<=0;
					end
					else begin
						read_address<=read_address+1;
					end
				end
				if (bit_counter == 23)
				begin
					bit_counter <= 0;
					srCDATA <= wCDATA;
					if (read_address == 0) begin
						sig_reset <= 1;
					end
				end
				else
				begin
					bit_counter<=bit_counter+1;
				end
			end
		end
		if (sig_reset && signal_timer>TRS) begin
			signal_timer <= 0;
			sig_reset <= 0;
			srCDATA <= wCDATA;
		end
		else begin
			if (signal_timer >= TE) begin
				signal_timer <= 0;
			end
			else begin
				signal_timer <= signal_timer+1; 
			end
		end
	end
end




endmodule
module WS2812(iSIGNAL_CLOCK,iDATA_CLOCK,dR, dG, dB,oCTRL_OUT, LED_IDX, ext_reset);

	input 		iSIGNAL_CLOCK;
	input 		iDATA_CLOCK;
	input [7:0]	dR, dG, dB;
	input [8:0] LED_IDX;
	input ext_reset;
	output 		oCTRL_OUT;
	


	parameter T0H = 40;
	parameter T1H = 80; 
	parameter T0L = 85;
	parameter T1L = 45;
	parameter TRS = 5100;

	


wire [23:0] wRamData;

wire [23:0] wCDATA;
wire true;


reg wRCLK;
reg [8:0] read_address;
reg [8:0] ledCount;
reg [12:0] signal_timer;
reg [4:0] bit_counter;
reg [23:0] srCDATA;
reg rCTRL_OUT;
reg sig_reset;
reg [6:0] TH;
reg [6:0] TE;

assign true=1;
assign oCTRL_OUT=rCTRL_OUT;
assign wRamData={dG,dR,dB};


RAM2P ram(
	.data(wRamData),
	.wraddress(LED_IDX),
	.wrclock(iDATA_CLOCK),
	.wren(true),
	
	.rdaddress(read_address),
	.rdclock(iSIGNAL_CLOCK),
	.q(wCDATA)
);



always @(posedge iDATA_CLOCK or posedge ext_reset)
begin
	if (ext_reset) begin
		ledCount=0;
	end
	else begin
		if (LED_IDX+1 > ledCount && LED_IDX)
		begin
			ledCount <= LED_IDX+1;
		end
	end
end








always @(posedge iSIGNAL_CLOCK or posedge ext_reset)
begin
	if (ext_reset) begin
		read_address=0;
		
		bit_counter=0;
		signal_timer=0;
		rCTRL_OUT=0;
		sig_reset=0;
	end
	else begin
		if (signal_timer==0 && ~sig_reset)
		begin
			rCTRL_OUT<=1;
		end
		if (~sig_reset) begin
			if (srCDATA[23])
			begin
				TH<=T1H;
				TE<=T1H+T1L;
			end
			else
			begin
				TH<=T0H;
				TE<=T0H+T0L;
			end
			rCTRL_OUT<=(signal_timer < TH)?1:0;
			if (signal_timer >= TE)
			begin
				srCDATA<=srCDATA<<1;
				if (bit_counter == 11) begin
					if (read_address >= ledCount) begin
						read_address<=0;
					end
					else begin
						read_address<=read_address+1;
					end
				end
				if (bit_counter == 23)
				begin
					bit_counter <= 0;
					srCDATA <= wCDATA;
					if (read_address == 0) begin
						sig_reset <= 1;
					end
				end
				else
				begin
					bit_counter<=bit_counter+1;
				end
			end
		end
		if (sig_reset && signal_timer>TRS) begin
			signal_timer <= 0;
			sig_reset <= 0;
			srCDATA <= wCDATA;
		end
		else begin
			if (signal_timer >= TE) begin
				signal_timer <= 0;
			end
			else begin
				signal_timer <= signal_timer+1; 
			end
		end
	end
end




endmodule