data/full_repos/permissive/154352170/DM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/154352170/DM.v:43: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                            : ... In instance DM\n  assign DM_Out = (IR_In[31:26] == 2\'b000011) ? (PC_Out + 4) : RAM[Addr];\n                                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module DM(
    input clk,
	 input reset,
	 input MemWrite,
	 input [31:0] IR_In,
	 input [31:0] PC_Out,
	 input [31:0] ALU_Out,
	 input [31:0] WD,	 
	 output [31:0] DM_Out
    );
	 
	 reg [31:0] RAM [1023:0];
	 integer i;
	 wire [9:0] Addr;
	 wire [31:0] Addr_Out;
	 
	 initial begin
	    for(i = 0; i < 1024; i = i + 1)
		    RAM[i] = 32'h00000000;
	 end
	 
	 assign Addr = ALU_Out[11:2];
	 assign DM_Out = (IR_In[31:26] == 2'b000011) ? (PC_Out + 4) : RAM[Addr];
	 assign Addr_Out = {20'b0, Addr, 2'b0};
	 
	 always @ (posedge clk) begin
	    		 
		 if (reset) begin
		    for(i = 0; i < 1024; i = i + 1)
			    RAM[i] <= 32'h00000000;
		 end
		 
		 else if (MemWrite) begin
		    RAM[Addr] <= WD;
			 $display("%d@%h: *%h <= %h", $time, PC_Out, Addr_Out, WD);
		 end
		 
	 end
		 
endmodule
module DM(
    input clk,
	 input reset,
	 input MemWrite,
	 input [31:0] IR_In,
	 input [31:0] PC_Out,
	 input [31:0] ALU_Out,
	 input [31:0] WD,	 
	 output [31:0] DM_Out
    );

	 
	 reg [31:0] RAM [1023:0];
	 integer i;
	 wire [9:0] Addr;
	 wire [31:0] Addr_Out;
	 
	 initial begin
	    for(i = 0; i < 1024; i = i + 1)
		    RAM[i] = 32'h00000000;
	 end
	 
	 assign Addr = ALU_Out[11:2];
	 assign DM_Out = (IR_In[31:26] == 2'b000011) ? (PC_Out + 4) : RAM[Addr];
	 assign Addr_Out = {20'b0, Addr, 2'b0};
	 
	 always @ (posedge clk) begin
	    		 
		 if (reset) begin
		    for(i = 0; i < 1024; i = i + 1)
			    RAM[i] <= 32'h00000000;
		 end
		 
		 else if (MemWrite) begin
		    RAM[Addr] <= WD;
			 $display("%d@%h: *%h <= %h", $time, PC_Out, Addr_Out, WD);
		 end
		 
	 end
		 
endmodule