data/full_repos/permissive/170267528/state1/tclProject/impBRAM/top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/top.v:42: Cannot find file containing module: 'blk_mem_gen_0'\nblk_mem_gen_0 rom (\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170267528/state1/tclProject/impBRAM,data/full_repos/permissive/170267528/blk_mem_gen_0\n             data/full_repos/permissive/170267528/state1/tclProject/impBRAM,data/full_repos/permissive/170267528/blk_mem_gen_0.v\n             data/full_repos/permissive/170267528/state1/tclProject/impBRAM,data/full_repos/permissive/170267528/blk_mem_gen_0.sv\n             blk_mem_gen_0\n             blk_mem_gen_0.v\n             blk_mem_gen_0.sv\n             obj_dir/blk_mem_gen_0\n             obj_dir/blk_mem_gen_0.v\n             obj_dir/blk_mem_gen_0.sv\n%Error: data/full_repos/permissive/170267528/state1/tclProject/impBRAM/top.v:53: Cannot find file containing module: 'prm_chk_v1_0'\nprm_chk_v1_0 i_prm_sel\n^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module top (

	input CLK,
	input [1:0] sel1,
	input [7:0] sel2,
	input [11:0] xyzInput,

	output [31:0] result_imp
);

wire [3:0] X_Wire;
wire [3:0] Y_Wire;
wire [3:0] Z_Wire;

wire [2047:0] edge_mask;


blk_mem_gen_0 rom (
	.addra({X_Wire,Y_Wire,Z_Wire}),
	.clka(CLK),
	.douta(edge_mask)
	);






prm_chk_v1_0 i_prm_sel
	(
		.CLK(CLK),
		.RST_n(1'b1),

		.sel1(sel1),
		.sel2(sel2),

		.xyzInput(xyzInput),

		.x(X_Wire),
		.y(Y_Wire),
		.z(Z_Wire),

		.edge_mask(edge_mask),


		.result_imp(result_imp)


	);


endmodule
module top (

	input CLK,
	input [1:0] sel1,
	input [7:0] sel2,
	input [11:0] xyzInput,

	output [31:0] result_imp
);


wire [3:0] X_Wire;
wire [3:0] Y_Wire;
wire [3:0] Z_Wire;

wire [2047:0] edge_mask;


blk_mem_gen_0 rom (
	.addra({X_Wire,Y_Wire,Z_Wire}),
	.clka(CLK),
	.douta(edge_mask)
	);






prm_chk_v1_0 i_prm_sel
	(
		.CLK(CLK),
		.RST_n(1'b1),

		.sel1(sel1),
		.sel2(sel2),

		.xyzInput(xyzInput),

		.x(X_Wire),
		.y(Y_Wire),
		.z(Z_Wire),

		.edge_mask(edge_mask),


		.result_imp(result_imp)


	);


endmodule