data/full_repos/permissive/219219909/Complex_Multiplier/vedic_24x24.v
1: b"%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_24x24.v:33: Cannot find file containing module: 'vedic_12x12'\nvedic_12x12 M0 (.a(a[11:0]),.b(b[11:0]),.clk(clk),.c(q0));\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219219909/Complex_Multiplier,data/full_repos/permissive/219219909/vedic_12x12\n             data/full_repos/permissive/219219909/Complex_Multiplier,data/full_repos/permissive/219219909/vedic_12x12.v\n             data/full_repos/permissive/219219909/Complex_Multiplier,data/full_repos/permissive/219219909/vedic_12x12.sv\n             vedic_12x12\n             vedic_12x12.v\n             vedic_12x12.sv\n             obj_dir/vedic_12x12\n             obj_dir/vedic_12x12.v\n             obj_dir/vedic_12x12.sv\n%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_24x24.v:34: Cannot find file containing module: 'vedic_12x12'\nvedic_12x12 M1 (.a(a[23:12]),.b(b[11:0]),.clk(clk),.c(q1));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_24x24.v:35: Cannot find file containing module: 'vedic_12x12'\nvedic_12x12 M2 (.a(a[11:0]),.b(b[23:12]),.clk(clk),.c(q2));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_24x24.v:36: Cannot find file containing module: 'vedic_12x12'\nvedic_12x12 M3 (.a(a[23:12]),.b(b[23:12]),.clk(clk),.c(q3));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_24x24.v:38: Cannot find file containing module: 'buf240'\nbuf240 M7 (.a(q0),.b(q1),.c(q2),.d(q3),.clk(clk),.a1(p0),.b1(p1),.c1(p2),.d1(p3));\n^~~~~~\n%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_24x24.v:44: Cannot find file containing module: 'adder24'\nadder24 M4 (.a(t1),.b(p1),.s(t5));\n^~~~~~~\n%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_24x24.v:45: Cannot find file containing module: 'adder36'\nadder36 M5 (.a(t2),.b(t3),.s(t4));\n^~~~~~~\n%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_24x24.v:48: Cannot find file containing module: 'buf36'\nbuf36 M8 (.a(t6),.b(t4),.clk(clk),.a1(t8),.b1(t9));\n^~~~~\n%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_24x24.v:50: Cannot find file containing module: 'adder36'\nadder36 M6 (.a(t8),.b(t9),.s(t7));\n^~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module vedic_24x24(
    input [23:0] a,
    input [23:0] b,
	 input clk,
    output [47:0] c
    );


wire [23:0] q0,q1,q2,q3,p0,p1,p2,p3;
wire [23:0] t1,t5;
wire [35:0] t2,t3,t4,t6,t7,t8,t9;
wire [47:0] c1;
vedic_12x12 M0 (.a(a[11:0]),.b(b[11:0]),.clk(clk),.c(q0));
vedic_12x12 M1 (.a(a[23:12]),.b(b[11:0]),.clk(clk),.c(q1));
vedic_12x12 M2 (.a(a[11:0]),.b(b[23:12]),.clk(clk),.c(q2));
vedic_12x12 M3 (.a(a[23:12]),.b(b[23:12]),.clk(clk),.c(q3));

buf240 M7 (.a(q0),.b(q1),.c(q2),.d(q3),.clk(clk),.a1(p0),.b1(p1),.c1(p2),.d1(p3));

assign t1={12'b0,p0[23:12]};
assign t2={12'b0,p2};
assign t3={p3,12'b0};

adder24 M4 (.a(t1),.b(p1),.s(t5));
adder36 M5 (.a(t2),.b(t3),.s(t4));
assign t6={12'b0,t5};

buf36 M8 (.a(t6),.b(t4),.clk(clk),.a1(t8),.b1(t9));

adder36 M6 (.a(t8),.b(t9),.s(t7));

assign c[11:0]=p0[11:0];
assign c[47:12]=t7;
endmodule
module vedic_24x24(
    input [23:0] a,
    input [23:0] b,
	 input clk,
    output [47:0] c
    );



wire [23:0] q0,q1,q2,q3,p0,p1,p2,p3;
wire [23:0] t1,t5;
wire [35:0] t2,t3,t4,t6,t7,t8,t9;
wire [47:0] c1;
vedic_12x12 M0 (.a(a[11:0]),.b(b[11:0]),.clk(clk),.c(q0));
vedic_12x12 M1 (.a(a[23:12]),.b(b[11:0]),.clk(clk),.c(q1));
vedic_12x12 M2 (.a(a[11:0]),.b(b[23:12]),.clk(clk),.c(q2));
vedic_12x12 M3 (.a(a[23:12]),.b(b[23:12]),.clk(clk),.c(q3));

buf240 M7 (.a(q0),.b(q1),.c(q2),.d(q3),.clk(clk),.a1(p0),.b1(p1),.c1(p2),.d1(p3));

assign t1={12'b0,p0[23:12]};
assign t2={12'b0,p2};
assign t3={p3,12'b0};

adder24 M4 (.a(t1),.b(p1),.s(t5));
adder36 M5 (.a(t2),.b(t3),.s(t4));
assign t6={12'b0,t5};

buf36 M8 (.a(t6),.b(t4),.clk(clk),.a1(t8),.b1(t9));

adder36 M6 (.a(t8),.b(t9),.s(t7));

assign c[11:0]=p0[11:0];
assign c[47:12]=t7;
endmodule