data/full_repos/permissive/189013641/src/runcnt_tmp.v
 line:95: before: "slot2_dout"
1: b'%Warning-WIDTH: data/full_repos/permissive/189013641/src/runcnt_tmp.v:77: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'k\' generates 4 bits.\n                                                                        : ... In instance runcnt_tmp\n   k_out<=k;\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/runcnt_tmp.v:78: Operator SUB expects 32 or 6 bits on the RHS, but RHS\'s VARREF \'limit_reduce\' generates 4 bits.\n                                                                        : ... In instance runcnt_tmp\n   glimit<=31-limit_reduce;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/runcnt_tmp.v:80: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'codes_len2_in\' generates 4 bits.\n                                                                        : ... In instance runcnt_tmp\n   codes_r_len<=codes_len1_in+codes_len2_in;\n                             ^\n%Error: Exiting due to 3 warning(s)\n'
module runcnt_tmp(clk,en,reset,
                 k,
                 limit_reduce,
					  codes_len1_in,
					  codes_2_in,
					  codes_len2_in,
					  mode_in,
                 k_out,
                 glimit,
					  codes_r,
					  codes_r_len,
					  en_out 
						);

input         clk,en,reset;
input [3:0]   k;
input [3:0]   limit_reduce;
input [5:0]   codes_len1_in;
input [10:0]  codes_2_in;
input [3:0]   codes_len2_in;
input [1:0]   mode_in;
					  
output [4:0]  k_out;
output [5:0]  glimit;
output [31:0]  codes_r;
output [5:0] codes_r_len;

output        en_out;

reg [4:0]  k_out;
reg [5:0]  glimit;
 
reg [31:0] codes_r;
reg [5:0]  codes_r_len;
reg [5:0]  mode_out;
reg        en_out;

wire [31:0] code_temp1,code_tmp1,code_temp2,code_temp3;

assign code_temp1=(1<<codes_len1_in);
assign code_tmp1=code_temp1-1;
assign code_temp2=(code_tmp1<<codes_len2_in);
assign code_temp3=code_temp2|{21'd0,codes_2_in};

always@(posedge clk or negedge reset)
if(!reset)
 begin
   k_out<=0;
   glimit<=0;
	
   codes_r<=0;
   codes_r_len<=0; 
   en_out<=0; 
 end
else if(en)
 begin
   k_out<=k;
   glimit<=31-limit_reduce;
   codes_r<=code_temp3;
   codes_r_len<=codes_len1_in+codes_len2_in;
   en_out<=1; 
 end
else
 begin
   k_out<=0;
   glimit<=0;
   codes_r<=0;
   codes_r_len<=0; 
   en_out<=0; 
 end



endmodule
module runcnt_tmp(clk,en,reset,
                 k,
                 limit_reduce,
					  codes_len1_in,
					  codes_2_in,
					  codes_len2_in,
					  mode_in,
                 k_out,
                 glimit,
					  codes_r,
					  codes_r_len,
					  en_out 
						);


input         clk,en,reset;
input [3:0]   k;
input [3:0]   limit_reduce;
input [5:0]   codes_len1_in;
input [10:0]  codes_2_in;
input [3:0]   codes_len2_in;
input [1:0]   mode_in;
					  
output [4:0]  k_out;
output [5:0]  glimit;
output [31:0]  codes_r;
output [5:0] codes_r_len;

output        en_out;

reg [4:0]  k_out;
reg [5:0]  glimit;
 
reg [31:0] codes_r;
reg [5:0]  codes_r_len;
reg [5:0]  mode_out;
reg        en_out;

wire [31:0] code_temp1,code_tmp1,code_temp2,code_temp3;

assign code_temp1=(1<<codes_len1_in);
assign code_tmp1=code_temp1-1;
assign code_temp2=(code_tmp1<<codes_len2_in);
assign code_temp3=code_temp2|{21'd0,codes_2_in};

always@(posedge clk or negedge reset)
if(!reset)
 begin
   k_out<=0;
   glimit<=0;
	
   codes_r<=0;
   codes_r_len<=0; 
   en_out<=0; 
 end
else if(en)
 begin
   k_out<=k;
   glimit<=31-limit_reduce;
   codes_r<=code_temp3;
   codes_r_len<=codes_len1_in+codes_len2_in;
   en_out<=1; 
 end
else
 begin
   k_out<=0;
   glimit<=0;
   codes_r<=0;
   codes_r_len<=0; 
   en_out<=0; 
 end



endmodule