data/full_repos/permissive/216210370/soc/rtc.v
1: b"%Error: data/full_repos/permissive/216210370/soc/rtc.v:892: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.v\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:510: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:469: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:409: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:197: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module rtc_cnt(
  aou_pdu_cnt,
  cnt_en,
  count_val,
  match_val,
  pdu_aou_clr_reg,
  pdu_aou_wen_clr_sync,
  presetn,
  rtc_clk,
  wrap_en
);
input           cnt_en;              
input   [31:0]  match_val;           
input   [31:0]  pdu_aou_clr_reg;     
input           pdu_aou_wen_clr_sync; 
input           presetn;             
input           rtc_clk;             
input           wrap_en;             
output  [31:0]  aou_pdu_cnt;         
output  [31:0]  count_val;           
reg     [31:0]  cnt;                 
wire    [31:0]  aou_pdu_cnt;         
wire            cnt_en;              
wire    [31:0]  count_val;           
wire    [31:0]  match_val;           
wire    [31:0]  pdu_aou_clr_reg;     
wire            pdu_aou_wen_clr_sync; 
wire            presetn;             
wire            rtc_clk;             
wire            wrap_en;             
 always @ (posedge rtc_clk or negedge presetn)
 begin
   if(~presetn)
     begin
         cnt[31:0] <= {32{1'b0}};
     end
   else if(pdu_aou_wen_clr_sync)
     begin
         cnt[31:0] <= pdu_aou_clr_reg[31:0];
     end
   else if(cnt_en)
     begin
        if((cnt[31:0] == match_val[31:0]) && wrap_en)
           begin
             cnt[31:0] <= {32{1'b0}};
           end
	else
	   begin
             cnt[31:0] <= cnt[31:0] + 1'b1;
           end
     end
 end 
 assign aou_pdu_cnt[31:0] = cnt[31:0];
 assign count_val[31:0] = cnt[31:0];
endmodule
module rtc_cnt(
  aou_pdu_cnt,
  cnt_en,
  count_val,
  match_val,
  pdu_aou_clr_reg,
  pdu_aou_wen_clr_sync,
  presetn,
  rtc_clk,
  wrap_en
);

input           cnt_en;              
input   [31:0]  match_val;           
input   [31:0]  pdu_aou_clr_reg;     
input           pdu_aou_wen_clr_sync; 
input           presetn;             
input           rtc_clk;             
input           wrap_en;             
output  [31:0]  aou_pdu_cnt;         
output  [31:0]  count_val;           
reg     [31:0]  cnt;                 
wire    [31:0]  aou_pdu_cnt;         
wire            cnt_en;              
wire    [31:0]  count_val;           
wire    [31:0]  match_val;           
wire    [31:0]  pdu_aou_clr_reg;     
wire            pdu_aou_wen_clr_sync; 
wire            presetn;             
wire            rtc_clk;             
wire            wrap_en;             
 always @ (posedge rtc_clk or negedge presetn)
 begin
   if(~presetn)
     begin
         cnt[31:0] <= {32{1'b0}};
     end
   else if(pdu_aou_wen_clr_sync)
     begin
         cnt[31:0] <= pdu_aou_clr_reg[31:0];
     end
   else if(cnt_en)
     begin
        if((cnt[31:0] == match_val[31:0]) && wrap_en)
           begin
             cnt[31:0] <= {32{1'b0}};
           end
	else
	   begin
             cnt[31:0] <= cnt[31:0] + 1'b1;
           end
     end
 end 
 assign aou_pdu_cnt[31:0] = cnt[31:0];
 assign count_val[31:0] = cnt[31:0];
endmodule