data/full_repos/permissive/156129873/verilog/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/156129873/verilog/test.v:83: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156129873/verilog/test.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #50 rst = 1\'b1;\n  ^\n%Error: data/full_repos/permissive/156129873/verilog/test.v:51: Cannot find file containing module: \'top\'\n top uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/top\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/top.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: data/full_repos/permissive/156129873/verilog/test.v:67: Cannot find file containing module: \'VirtualSram\'\n VirtualSram mySram(\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;


	reg clk;
	reg rst;


	wire [17:0] ramAddr;
	wire ramOE;
	wire ramWE;
	wire ramEN;
	wire [15:0] led;
	wire [6:0] dispL;
	wire [6:0] dispR;


	wire [15:0] ramData;
	wire [15:0] getRamData;
	wire [15:0] giveRamData;
	

	wire [15:0] debug_pc;
	wire [15:0] debug_ins;
	wire clk100_out;
	

	top uut (
		.clk1(clk), 
		.rst(rst), 
		.ramData(ramData), 
		.ramAddr(ramAddr), 
		.ramOE(ramOE), 
		.ramWE(ramWE), 
		.ramEN(ramEN),
		.led(led), 
		.dispL(dispL), 
		.dispR(dispR),
		.debug_pc(debug_pc),
		.debug_ins(debug_ins),
		.clk100_out(clk100_out)
	);
	
	VirtualSram mySram(
		.ramInputData(giveRamData), 
		.ramOutputData(getRamData),
		.ramAddr(ramAddr), 
		.ramOE(ramOE), 
		.ramWE(ramWE), 
		.ramEN(ramEN)
	);
	wire getRamValid;
	
	assign getRamValid = (ramOE == 1'b0 && ramWE == 1'b1)? 1'b1 : 1'b0;
	assign giveRamData = ramData;
	assign ramData = (getRamValid == 1'b1)? getRamData : 16'hZZ;

	initial begin
		clk = 1'b1;
		forever #10 clk = ~clk;
   end
   initial begin
		rst = 1'b0;
		#50 rst = 1'b1;
   end
      
endmodule
module test;



	reg clk;
	reg rst;


	wire [17:0] ramAddr;
	wire ramOE;
	wire ramWE;
	wire ramEN;
	wire [15:0] led;
	wire [6:0] dispL;
	wire [6:0] dispR;


	wire [15:0] ramData;
	wire [15:0] getRamData;
	wire [15:0] giveRamData;
	

	wire [15:0] debug_pc;
	wire [15:0] debug_ins;
	wire clk100_out;
	

	top uut (
		.clk1(clk), 
		.rst(rst), 
		.ramData(ramData), 
		.ramAddr(ramAddr), 
		.ramOE(ramOE), 
		.ramWE(ramWE), 
		.ramEN(ramEN),
		.led(led), 
		.dispL(dispL), 
		.dispR(dispR),
		.debug_pc(debug_pc),
		.debug_ins(debug_ins),
		.clk100_out(clk100_out)
	);
	
	VirtualSram mySram(
		.ramInputData(giveRamData), 
		.ramOutputData(getRamData),
		.ramAddr(ramAddr), 
		.ramOE(ramOE), 
		.ramWE(ramWE), 
		.ramEN(ramEN)
	);
	wire getRamValid;
	
	assign getRamValid = (ramOE == 1'b0 && ramWE == 1'b1)? 1'b1 : 1'b0;
	assign giveRamData = ramData;
	assign ramData = (getRamValid == 1'b1)? getRamData : 16'hZZ;

	initial begin
		clk = 1'b1;
		forever #10 clk = ~clk;
   end
   initial begin
		rst = 1'b0;
		#50 rst = 1'b1;
   end
      
endmodule