data/full_repos/permissive/211235278/08. Harvard Arch Cached CPU/ICache.v
None: at end of input
1: b'%Error: Cannot find file containing module: Harvard\n        ... Looked in:\n             data/full_repos/permissive/211235278/08./Harvard\n             data/full_repos/permissive/211235278/08./Harvard.v\n             data/full_repos/permissive/211235278/08./Harvard.sv\n             Harvard\n             Harvard.v\n             Harvard.sv\n             obj_dir/Harvard\n             obj_dir/Harvard.v\n             obj_dir/Harvard.sv\n%Error: Cannot find file containing module: Arch\n%Error: Cannot find file containing module: Cached\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/211235278\n%Error: Cannot find file containing module: data/full_repos/permissive/211235278/08.\n%Error: Cannot find file containing module: CPU/ICache.v\n%Error: Exiting due to 6 error(s)\n'
module ICache(
    input clk,
    input reset_n,


    input i_readC,
    input [15:0] i_address,
    output [15:0] i_data,
    output InstCacheBusy,


    output reg i_readM,
    output [13:0] i_address_mem,
    input [63:0] i_data_mem
    );
    

    
    reg [11:0] TagBank [3:0];
    reg Valid [3:0];
    reg [63:0] DataBank [3:0];
    
    wire [11:0] tag;
    wire [1:0] idx;
    wire [1:0] block;
    wire hit;
    

    reg [2:0] InstCacheCounter;
    

    reg prefetching;
    reg [2:0] PrefetchCounter;
    reg [13:0] fetched_block, prefetched_block;
    
    assign tag = i_address[15:4];
    assign idx = i_address[3:2];
    assign block = i_address[1:0];
    
    assign hit = (TagBank[idx]==tag) && Valid[idx];
    
    assign i_data = (i_readC && hit) ? DataBank[idx][16*block+:16] : 16'hz;
    
    assign i_address_mem = prefetching ? (fetched_block + 1) : { tag, idx };
    

    assign InstCacheBusy = i_readC && !hit;
    

    always @(posedge clk) begin
        if (!reset_n) begin
            { TagBank[3], TagBank[2], TagBank[1], TagBank[0] } <= 0;
            { Valid[3], Valid[2], Valid[1], Valid[0] } <= 0;
            { DataBank[3], DataBank[2], DataBank[1], DataBank[0] } <= 0;
            i_readM <= 0;
            InstCacheCounter <= 0;
            PrefetchCounter <= 0;
            prefetching <= 0;
            prefetched_block <= 0;
        end
    end
    
    always @(posedge clk) begin
        if (reset_n) begin
            if (i_readC && !hit) begin
            
                if (prefetching) begin
                    if (i_address_mem == {tag, idx}) begin
                        if (PrefetchCounter == 1) begin
                            TagBank[(fetched_block[1:0]+1)%4] <= i_address_mem[13:2];
                            Valid[(fetched_block[1:0]+1)%4] <= 1;
                            DataBank[(fetched_block[1:0]+1)%4] <= i_data_mem;
                            i_readM <= 0;
                            fetched_block <= i_address_mem;
                        end else begin
                            InstCacheCounter <= PrefetchCounter - 1;
                        end
                    end else begin
                        i_readM <= 0;
                    end
                    PrefetchCounter <= 0;
                    prefetching <= 0;

                end else if (InstCacheCounter == 0) begin
                    i_readM <= 1;
                    InstCacheCounter <= `LATENCY;
                end else if (InstCacheCounter == 1) begin
                    TagBank[idx] <= tag;
                    Valid[idx] <= 1;
                    DataBank[idx] <= i_data_mem;
                    i_readM <= 0;
                    fetched_block <= i_address_mem;
                end else begin
                    InstCacheCounter <= InstCacheCounter - 1;
                end
                
            end else begin
            
                if (prefetched_block != fetched_block + 1) begin
                    if (PrefetchCounter == 0) begin
                        prefetching <= 1;
                        i_readM <= 1;
                        PrefetchCounter <= `LATENCY;
                    end else if (PrefetchCounter == 1) begin
                        TagBank[(fetched_block[1:0]+1)%4] <= i_address_mem[13:2];
                        Valid[(fetched_block[1:0]+1)%4] <= 1;
                        DataBank[(fetched_block[1:0]+1)%4] <= i_data_mem;
                        i_readM <= 0;
                        prefetched_block <= fetched_block + 1;
                        prefetching <= 0;
                        PrefetchCounter <= 0;
                    end else begin
                        PrefetchCounter <= PrefetchCounter - 1;
                    end
                end else begin
                    i_readM <= 0;
                end
                
                InstCacheCounter <= 0;
                
            end
        end
    end
    
    

    integer inst_hit_instructions, inst_total_instructions;
    
    always @(posedge clk) begin
        if (!reset_n) begin
            inst_total_instructions <= 0;
            inst_hit_instructions <= 0;
        end
    end
    
    always @(negedge clk) begin
        if (i_readC && hit) inst_total_instructions <= inst_total_instructions + 1;
        if (i_readC && hit && InstCacheCounter==0) inst_hit_instructions <= inst_hit_instructions + 1;
    end
    
endmodule
module ICache(
    input clk,
    input reset_n,


    input i_readC,
    input [15:0] i_address,
    output [15:0] i_data,
    output InstCacheBusy,


    output reg i_readM,
    output [13:0] i_address_mem,
    input [63:0] i_data_mem
    );

    

    
    reg [11:0] TagBank [3:0];
    reg Valid [3:0];
    reg [63:0] DataBank [3:0];
    
    wire [11:0] tag;
    wire [1:0] idx;
    wire [1:0] block;
    wire hit;
    

    reg [2:0] InstCacheCounter;
    

    reg prefetching;
    reg [2:0] PrefetchCounter;
    reg [13:0] fetched_block, prefetched_block;
    
    assign tag = i_address[15:4];
    assign idx = i_address[3:2];
    assign block = i_address[1:0];
    
    assign hit = (TagBank[idx]==tag) && Valid[idx];
    
    assign i_data = (i_readC && hit) ? DataBank[idx][16*block+:16] : 16'hz;
    
    assign i_address_mem = prefetching ? (fetched_block + 1) : { tag, idx };
    

    assign InstCacheBusy = i_readC && !hit;
    

    always @(posedge clk) begin
        if (!reset_n) begin
            { TagBank[3], TagBank[2], TagBank[1], TagBank[0] } <= 0;
            { Valid[3], Valid[2], Valid[1], Valid[0] } <= 0;
            { DataBank[3], DataBank[2], DataBank[1], DataBank[0] } <= 0;
            i_readM <= 0;
            InstCacheCounter <= 0;
            PrefetchCounter <= 0;
            prefetching <= 0;
            prefetched_block <= 0;
        end
    end
    
    always @(posedge clk) begin
        if (reset_n) begin
            if (i_readC && !hit) begin
            
                if (prefetching) begin
                    if (i_address_mem == {tag, idx}) begin
                        if (PrefetchCounter == 1) begin
                            TagBank[(fetched_block[1:0]+1)%4] <= i_address_mem[13:2];
                            Valid[(fetched_block[1:0]+1)%4] <= 1;
                            DataBank[(fetched_block[1:0]+1)%4] <= i_data_mem;
                            i_readM <= 0;
                            fetched_block <= i_address_mem;
                        end else begin
                            InstCacheCounter <= PrefetchCounter - 1;
                        end
                    end else begin
                        i_readM <= 0;
                    end
                    PrefetchCounter <= 0;
                    prefetching <= 0;

                end else if (InstCacheCounter == 0) begin
                    i_readM <= 1;
                    InstCacheCounter <= `LATENCY;
                end else if (InstCacheCounter == 1) begin
                    TagBank[idx] <= tag;
                    Valid[idx] <= 1;
                    DataBank[idx] <= i_data_mem;
                    i_readM <= 0;
                    fetched_block <= i_address_mem;
                end else begin
                    InstCacheCounter <= InstCacheCounter - 1;
                end
                
            end else begin
            
                if (prefetched_block != fetched_block + 1) begin
                    if (PrefetchCounter == 0) begin
                        prefetching <= 1;
                        i_readM <= 1;
                        PrefetchCounter <= `LATENCY;
                    end else if (PrefetchCounter == 1) begin
                        TagBank[(fetched_block[1:0]+1)%4] <= i_address_mem[13:2];
                        Valid[(fetched_block[1:0]+1)%4] <= 1;
                        DataBank[(fetched_block[1:0]+1)%4] <= i_data_mem;
                        i_readM <= 0;
                        prefetched_block <= fetched_block + 1;
                        prefetching <= 0;
                        PrefetchCounter <= 0;
                    end else begin
                        PrefetchCounter <= PrefetchCounter - 1;
                    end
                end else begin
                    i_readM <= 0;
                end
                
                InstCacheCounter <= 0;
                
            end
        end
    end
    
    

    integer inst_hit_instructions, inst_total_instructions;
    
    always @(posedge clk) begin
        if (!reset_n) begin
            inst_total_instructions <= 0;
            inst_hit_instructions <= 0;
        end
    end
    
    always @(negedge clk) begin
        if (i_readC && hit) inst_total_instructions <= inst_total_instructions + 1;
        if (i_readC && hit && InstCacheCounter==0) inst_hit_instructions <= inst_hit_instructions + 1;
    end
    
endmodule