data/full_repos/permissive/119715647/src/ScoreBoard/ScoreBoardDisplay.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/119715647/src/ScoreBoard/ScoreBoardDisplay.v:54: Operator NEQCASE expects 16 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                          : ... In instance ScoreBoardDisplay\n     if (data[15] !== 16\'hFFFF) begin\n                  ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/119715647/src/ScoreBoard/ScoreBoardDisplay.v:66: Bit extraction of array[2:0] requires 2 bit index, not 3 bits.\n                                                                                          : ... In instance ScoreBoardDisplay\n      userid_score_output <= scoreboard[count];\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/119715647/src/ScoreBoard/ScoreBoardDisplay.v:64: Operator NEQCASE expects 3 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                          : ... In instance ScoreBoardDisplay\n     end else if(count !== 2\'b11) begin\n                       ^~~\n%Error: Exiting due to 3 warning(s)\n'
module ScoreBoardDisplay(
	input [0:0] clk, 
	input [0:0] rst, 
	input [31:0] data,
	input [2:0] buttons, 
	input [0:0] parity_toggle,
	output reg [0:0] scoreboard_eof,
	output reg [31:0] userid_score_output); 
	

	parameter INIT = 0, 
			  STORE = 1,
			  DISPLAY = 2; 
	reg [2:0] State;
	reg [2:0] count;  
	
	reg [31:0] scoreboard[2:0]; 



	always @ (parity_toggle) begin













	end  

	always @ (posedge clk) begin
		if(!rst) begin
			State <= INIT; 
		end	else begin
			case(State)
				INIT: begin
					count <= 0; 
					scoreboard_eof <= 0;
					scoreboard[0][31:0] <= 32'd0; 
					scoreboard[1][31:0] <= 32'd1;
					scoreboard[2][31:0] <= 32'd3;
					State <= DISPLAY;  
				end
				STORE: begin
					if (data[15] !== 16'hFFFF) begin
						State <= STORE;
					end 
					else begin
						State <= DISPLAY; 	
					end
				end
				DISPLAY: begin
					if(buttons[0] == 1) begin
						count <=count +1;
					end else if(count !== 2'b11) begin
						scoreboard_eof <= 0; 
						userid_score_output <= scoreboard[count];
						State <= DISPLAY; 
					end else begin
						scoreboard_eof <= 1; 
						userid_score_output <= 0;
						State <= INIT;
					end
				end
				default: begin
					State <= INIT; 
				end
			endcase
		end
	end
endmodule
module ScoreBoardDisplay(
	input [0:0] clk, 
	input [0:0] rst, 
	input [31:0] data,
	input [2:0] buttons, 
	input [0:0] parity_toggle,
	output reg [0:0] scoreboard_eof,
	output reg [31:0] userid_score_output);
 
	

	parameter INIT = 0, 
			  STORE = 1,
			  DISPLAY = 2; 
	reg [2:0] State;
	reg [2:0] count;  
	
	reg [31:0] scoreboard[2:0]; 



	always @ (parity_toggle) begin













	end  

	always @ (posedge clk) begin
		if(!rst) begin
			State <= INIT; 
		end	else begin
			case(State)
				INIT: begin
					count <= 0; 
					scoreboard_eof <= 0;
					scoreboard[0][31:0] <= 32'd0; 
					scoreboard[1][31:0] <= 32'd1;
					scoreboard[2][31:0] <= 32'd3;
					State <= DISPLAY;  
				end
				STORE: begin
					if (data[15] !== 16'hFFFF) begin
						State <= STORE;
					end 
					else begin
						State <= DISPLAY; 	
					end
				end
				DISPLAY: begin
					if(buttons[0] == 1) begin
						count <=count +1;
					end else if(count !== 2'b11) begin
						scoreboard_eof <= 0; 
						userid_score_output <= scoreboard[count];
						State <= DISPLAY; 
					end else begin
						scoreboard_eof <= 1; 
						userid_score_output <= 0;
						State <= INIT;
					end
				end
				default: begin
					State <= INIT; 
				end
			endcase
		end
	end
endmodule