data/full_repos/permissive/219917900/rx_rtl_files/detect_errors2.v
 line:5: before: "("
1: b'%Error: data/full_repos/permissive/219917900/rx_rtl_files/detect_errors2.v:49: Cannot find file containing module: \'loss_calculator\'\nloss_calculator #(.maxaux(maxaux),.maxaux_bits(maxaux_bits)) loss_calculator_this (\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219917900/rx_rtl_files,data/full_repos/permissive/219917900/loss_calculator\n             data/full_repos/permissive/219917900/rx_rtl_files,data/full_repos/permissive/219917900/loss_calculator.v\n             data/full_repos/permissive/219917900/rx_rtl_files,data/full_repos/permissive/219917900/loss_calculator.sv\n             loss_calculator\n             loss_calculator.v\n             loss_calculator.sv\n             obj_dir/loss_calculator\n             obj_dir/loss_calculator.v\n             obj_dir/loss_calculator.sv\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/detect_errors2.v:107: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'ok_sub\' generates 16 bits.\n                                                                                      : ... In instance detect_errors2\n                   ok <= ok + ok_sub;\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/detect_errors2.v:108: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'ng_sub\' generates 16 bits.\n                                                                                      : ... In instance detect_errors2\n                   ng <= ng + ng_sub;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/detect_errors2.v:109: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'count_sub\' generates 16 bits.\n                                                                                      : ... In instance detect_errors2\n                   count <= count + count_sub;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/detect_errors2.v:110: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'lostnum_sub\' generates 16 bits.\n                                                                                      : ... In instance detect_errors2\n                   lostnum <= lostnum + lostnum_sub;\n                                      ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module detect_errors2 #(parameter whereis_aux = 0, maxaux = 16'h0fff, maxaux_bits = 'd12)(
	input wire clk,
	(* mark_debug = "true" *) input wire rst,
	(* mark_debug = "true" *) input wire [15:0] segment_number_max,
	(* mark_debug = "true" *) input wire [15:0] seg,
	(* mark_debug = "true" *) input wire rx_en,
	(* mark_debug = "true" *) input wire [7:0] rx_data,
	(* mark_debug = "true" *) output reg [31:0] count,
	(* mark_debug = "true" *) output reg [31:0] ok,
	(* mark_debug = "true" *) output reg [31:0] ng,
	(* mark_debug = "true" *) output reg [31:0] lostnum,
	output reg valid,
	(* mark_debug = "true" *) output reg [2:0] state='d0
);

localparam maxcount = 500000;


reg [15:0] count_edge;

reg [15:0] seg_prev,seg_tmp;

wire aux_on = (whereis_aux == count_edge && rx_en);

wire aux_on_1 = (whereis_aux + 5 == count_edge);
wire aux_on_2 = (whereis_aux + 6 == count_edge);
wire aux_on_3 = (whereis_aux + 7 == count_edge);




reg count_on;

reg [15:0] aux_tmp;
reg [15:0] addr;
(* mark_debug = "true" *) reg [15:0] aux_new,aux_old;
reg endflag;

localparam state_wait = 0;
wire [15:0] aux_new_pros = (aux_old < 16'hffff) ? aux_old + 1'b1 : 0;
wire [15:0] aux_oldp1 = aux_old + 1'b1;


wire [15:0] ok_sub,ng_sub,lostnum_sub,count_sub;
(* mark_debug = "true" *) reg cal_rst = 1'b0;
wire done;
loss_calculator #(.maxaux(maxaux),.maxaux_bits(maxaux_bits)) loss_calculator_this (
    .clk(clk),
    .rst(rst || cal_rst),
    .segment_number_max(segment_number_max),
    .segment_number(seg),
    .valid_in(aux_on_2),
    .aux(aux_new[maxaux_bits: 0]),
    .ok(ok_sub),
    .ng(ng_sub),
    .lostnum(lostnum_sub),
    .count(count_sub),
    .done(done)
);



always @(posedge clk) begin
    if (rst) begin
        count_edge <= 16'b0;
        endflag <= 0;
        count <= 0;
        ok <= 0;
        lostnum = 0;
        valid <= 1'b0;

        ng <= 0;
        addr <= 0;
        aux_new <= 0;
        aux_old <= 0;

        count_on = 0;
        seg_prev = 0;
        state = 0;

    end
    else begin
        if (rx_en) begin
            count_edge <= count_edge + 1'b1;
            if (aux_on) begin
                aux_old <= aux_new;
                aux_new[15:8] <= rx_data;
            end
            else if (aux_on_1) begin
            aux_new[7:0] <= rx_data;
            end
        end
        else begin
            count_edge <= 0;
        end

        case (state)
            0: 
            begin
                if (count > maxcount) begin
                    state <= 'd3;
                    cal_rst <= 1'b0;
                end
                else if (done) begin
                   ok <= ok + ok_sub;
                   ng <= ng + ng_sub;
                   count <= count + count_sub;
                   lostnum <= lostnum + lostnum_sub;
                   cal_rst <= 1'b1;
                   state <= 'd2;
               end 
               else begin
                   cal_rst <= 1'b0;

               end
            end
            2:
            begin
                if (count>maxcount) begin
                    state<='d3;
                    cal_rst = 1'b0;
                end
                else begin
                    cal_rst = 1'b0;
                    state <= 'd0;
                end
                
            end
            3:
            begin
            cal_rst = 1'b0;
                
            end
            default: begin
                state<='d0;
                cal_rst = 1'b0;
                end
        endcase
    end
end










                    



































endmodule
module detect_errors2 #(parameter whereis_aux = 0, maxaux = 16'h0fff, maxaux_bits = 'd12)(
	input wire clk,
	(* mark_debug = "true" *) input wire rst,
	(* mark_debug = "true" *) input wire [15:0] segment_number_max,
	(* mark_debug = "true" *) input wire [15:0] seg,
	(* mark_debug = "true" *) input wire rx_en,
	(* mark_debug = "true" *) input wire [7:0] rx_data,
	(* mark_debug = "true" *) output reg [31:0] count,
	(* mark_debug = "true" *) output reg [31:0] ok,
	(* mark_debug = "true" *) output reg [31:0] ng,
	(* mark_debug = "true" *) output reg [31:0] lostnum,
	output reg valid,
	(* mark_debug = "true" *) output reg [2:0] state='d0
);


localparam maxcount = 500000;


reg [15:0] count_edge;

reg [15:0] seg_prev,seg_tmp;

wire aux_on = (whereis_aux == count_edge && rx_en);

wire aux_on_1 = (whereis_aux + 5 == count_edge);
wire aux_on_2 = (whereis_aux + 6 == count_edge);
wire aux_on_3 = (whereis_aux + 7 == count_edge);




reg count_on;

reg [15:0] aux_tmp;
reg [15:0] addr;
(* mark_debug = "true" *) reg [15:0] aux_new,aux_old;
reg endflag;

localparam state_wait = 0;
wire [15:0] aux_new_pros = (aux_old < 16'hffff) ? aux_old + 1'b1 : 0;
wire [15:0] aux_oldp1 = aux_old + 1'b1;


wire [15:0] ok_sub,ng_sub,lostnum_sub,count_sub;
(* mark_debug = "true" *) reg cal_rst = 1'b0;
wire done;
loss_calculator #(.maxaux(maxaux),.maxaux_bits(maxaux_bits)) loss_calculator_this (
    .clk(clk),
    .rst(rst || cal_rst),
    .segment_number_max(segment_number_max),
    .segment_number(seg),
    .valid_in(aux_on_2),
    .aux(aux_new[maxaux_bits: 0]),
    .ok(ok_sub),
    .ng(ng_sub),
    .lostnum(lostnum_sub),
    .count(count_sub),
    .done(done)
);



always @(posedge clk) begin
    if (rst) begin
        count_edge <= 16'b0;
        endflag <= 0;
        count <= 0;
        ok <= 0;
        lostnum = 0;
        valid <= 1'b0;

        ng <= 0;
        addr <= 0;
        aux_new <= 0;
        aux_old <= 0;

        count_on = 0;
        seg_prev = 0;
        state = 0;

    end
    else begin
        if (rx_en) begin
            count_edge <= count_edge + 1'b1;
            if (aux_on) begin
                aux_old <= aux_new;
                aux_new[15:8] <= rx_data;
            end
            else if (aux_on_1) begin
            aux_new[7:0] <= rx_data;
            end
        end
        else begin
            count_edge <= 0;
        end

        case (state)
            0: 
            begin
                if (count > maxcount) begin
                    state <= 'd3;
                    cal_rst <= 1'b0;
                end
                else if (done) begin
                   ok <= ok + ok_sub;
                   ng <= ng + ng_sub;
                   count <= count + count_sub;
                   lostnum <= lostnum + lostnum_sub;
                   cal_rst <= 1'b1;
                   state <= 'd2;
               end 
               else begin
                   cal_rst <= 1'b0;

               end
            end
            2:
            begin
                if (count>maxcount) begin
                    state<='d3;
                    cal_rst = 1'b0;
                end
                else begin
                    cal_rst = 1'b0;
                    state <= 'd0;
                end
                
            end
            3:
            begin
            cal_rst = 1'b0;
                
            end
            default: begin
                state<='d0;
                cal_rst = 1'b0;
                end
        endcase
    end
end










                    



































endmodule