data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v
None: at end of input
1: b'%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:28: Cannot find include file: spio_spinnaker_link.h\n`include "spio_spinnaker_link.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.v\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.sv\n             spio_spinnaker_link.h\n             spio_spinnaker_link.h.v\n             spio_spinnaker_link.h.sv\n             obj_dir/spio_spinnaker_link.h\n             obj_dir/spio_spinnaker_link.h.v\n             obj_dir/spio_spinnaker_link.h.sv\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:44: Define or directive not defined: \'`PKT_BITS\'\n  input      [`PKT_BITS - 1:0] PKT_DATA_IN,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:105: Define or directive not defined: \'`PKT_BITS\'\n  input       [`PKT_BITS - 1:0] PKT_DATA_IN,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:129: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] pkt_buf;    \n         ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
function [6:0] encode_nrz_2of7 ;
    input [4:0] din;
    input [6:0] old_din;

    casex (din)
      5'b00000 : encode_nrz_2of7 = old_din ^ 7'b0010001;
      5'b00001 : encode_nrz_2of7 = old_din ^ 7'b0010010;
      5'b00010 : encode_nrz_2of7 = old_din ^ 7'b0010100;
      5'b00011 : encode_nrz_2of7 = old_din ^ 7'b0011000;
      5'b00100 : encode_nrz_2of7 = old_din ^ 7'b0100001;
      5'b00101 : encode_nrz_2of7 = old_din ^ 7'b0100010;
      5'b00110 : encode_nrz_2of7 = old_din ^ 7'b0100100;
      5'b00111 : encode_nrz_2of7 = old_din ^ 7'b0101000;
      5'b01000 : encode_nrz_2of7 = old_din ^ 7'b1000001;
      5'b01001 : encode_nrz_2of7 = old_din ^ 7'b1000010;
      5'b01010 : encode_nrz_2of7 = old_din ^ 7'b1000100;
      5'b01011 : encode_nrz_2of7 = old_din ^ 7'b1001000;
      5'b01100 : encode_nrz_2of7 = old_din ^ 7'b0000011;
      5'b01101 : encode_nrz_2of7 = old_din ^ 7'b0000110;
      5'b01110 : encode_nrz_2of7 = old_din ^ 7'b0001100;
      5'b01111 : encode_nrz_2of7 = old_din ^ 7'b0001001;
      5'b1xxxx : encode_nrz_2of7 = old_din ^ 7'b1100000;
      default  : encode_nrz_2of7 = 7'bxxxxxxx;
    endcase
  endfunction
function [6:0] encode_nrz_2of7 ;

    input [4:0] din;
    input [6:0] old_din;

    casex (din)
      5'b00000 : encode_nrz_2of7 = old_din ^ 7'b0010001;
      5'b00001 : encode_nrz_2of7 = old_din ^ 7'b0010010;
      5'b00010 : encode_nrz_2of7 = old_din ^ 7'b0010100;
      5'b00011 : encode_nrz_2of7 = old_din ^ 7'b0011000;
      5'b00100 : encode_nrz_2of7 = old_din ^ 7'b0100001;
      5'b00101 : encode_nrz_2of7 = old_din ^ 7'b0100010;
      5'b00110 : encode_nrz_2of7 = old_din ^ 7'b0100100;
      5'b00111 : encode_nrz_2of7 = old_din ^ 7'b0101000;
      5'b01000 : encode_nrz_2of7 = old_din ^ 7'b1000001;
      5'b01001 : encode_nrz_2of7 = old_din ^ 7'b1000010;
      5'b01010 : encode_nrz_2of7 = old_din ^ 7'b1000100;
      5'b01011 : encode_nrz_2of7 = old_din ^ 7'b1001000;
      5'b01100 : encode_nrz_2of7 = old_din ^ 7'b0000011;
      5'b01101 : encode_nrz_2of7 = old_din ^ 7'b0000110;
      5'b01110 : encode_nrz_2of7 = old_din ^ 7'b0001100;
      5'b01111 : encode_nrz_2of7 = old_din ^ 7'b0001001;
      5'b1xxxx : encode_nrz_2of7 = old_din ^ 7'b1100000;
      default  : encode_nrz_2of7 = 7'bxxxxxxx;
    endcase
  endfunction