data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/wb_spi/bench/verilog/spi_slave_model.v
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/wb_spi/bench/verilog/spi_slave_model.v:41: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/wb_spi/bench/verilog,data/full_repos/permissive/214858095/timescale.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/wb_spi/bench/verilog,data/full_repos/permissive/214858095/timescale.v.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/wb_spi/bench/verilog,data/full_repos/permissive/214858095/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/wb_spi/bench/verilog/spi_slave_model.v:59: syntax error, unexpected &&, expecting \')\'\n  always @(posedge(sclk && !rx_negedge) or negedge(sclk && rx_negedge) or rst)\n                        ^~\n%Error: Cannot continue\n'
module spi_slave_model (rst, ss, sclk, mosi, miso);

  input         rst;
  input         ss;
  input         sclk;
  input         mosi;
  output        miso;

  reg           miso;

  reg           rx_negedge;
  reg           tx_negedge;
  reg    [31:0] data;

  parameter     Tp = 1;

  always @(posedge(sclk && !rx_negedge) or negedge(sclk && rx_negedge) or rst)
  begin
    if (rst)
      data <= #Tp 32'b0;
    else if (!ss)
      data <= #Tp {data[30:0], mosi};
  end

  always @(posedge(sclk && !tx_negedge) or negedge(sclk && tx_negedge))
  begin
    miso <= #Tp data[31];
  end

endmodule
module spi_slave_model (rst, ss, sclk, mosi, miso);


  input         rst;
  input         ss;
  input         sclk;
  input         mosi;
  output        miso;

  reg           miso;

  reg           rx_negedge;
  reg           tx_negedge;
  reg    [31:0] data;

  parameter     Tp = 1;

  always @(posedge(sclk && !rx_negedge) or negedge(sclk && rx_negedge) or rst)
  begin
    if (rst)
      data <= #Tp 32'b0;
    else if (!ss)
      data <= #Tp {data[30:0], mosi};
  end

  always @(posedge(sclk && !tx_negedge) or negedge(sclk && tx_negedge))
  begin
    miso <= #Tp data[31];
  end

endmodule