data/full_repos/permissive/143278/ivltests/pr1574175.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1574175.v:7: Operator ITORD expects 32 bits on the LHS, but LHS\'s VARREF \'bits\' generates 6 bits.\n                                                                        : ... In instance top\n    incorrect = -180 + bits*(360.0/63.0);\n                       ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/pr1574175.v:7: Implicit conversion of real to integer\n    incorrect = -180 + bits*(360.0/63.0);\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1574175.v:8: Operator ITORD expects 32 bits on the LHS, but LHS\'s VARREF \'bits\' generates 6 bits.\n                                                                        : ... In instance top\n    correct = bits*(360.0/63.0) - 180;\n              ^~~~\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/pr1574175.v:8: Implicit conversion of real to integer\n    correct = bits*(360.0/63.0) - 180;\n                                ^\n%Error: Exiting due to 4 warning(s)\n'
module top;
  integer correct, incorrect;
  reg [5:0] bits;

  initial begin
    bits = 32;
    incorrect = -180 + bits*(360.0/63.0);
    correct = bits*(360.0/63.0) - 180;
    $display("Both of these should be the same (3): %3d, %3d", incorrect,
                                                               correct);
    $finish(0);
  end
endmodule
module top;

  integer correct, incorrect;
  reg [5:0] bits;

  initial begin
    bits = 32;
    incorrect = -180 + bits*(360.0/63.0);
    correct = bits*(360.0/63.0) - 180;
    $display("Both of these should be the same (3): %3d, %3d", incorrect,
                                                               correct);
    $finish(0);
  end
endmodule