data/full_repos/permissive/129127690/decoder.v
data/verilator_xmls/9fbc6271-241e-4bae-8240-81ad3d8ee9d6.xml
module decoder #(parameter bus_size_out = 4, bus_size_in = 2)(
	input [bus_size_in-1:0] select,
	input enabled,
	output [bus_size_out-1:0] out);
	
	wire [bus_size_out-1:0] tmp = {{bus_size_out-1{1'b0}}, 1'b1};

	assign out = enabled ? 0 : (tmp << select);

endmodule
module decoder #(parameter bus_size_out = 4, bus_size_in = 2)(
	input [bus_size_in-1:0] select,
	input enabled,
	output [bus_size_out-1:0] out);

	
	wire [bus_size_out-1:0] tmp = {{bus_size_out-1{1'b0}}, 1'b1};

	assign out = enabled ? 0 : (tmp << select);

endmodule