data/full_repos/permissive/137301388/source/spi_slave_mm_top.v
1: b"%Error: data/full_repos/permissive/137301388/source/spi_slave_mm_top.v:128: Cannot find file containing module: 'spi_slave'\nspi_slave #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) spi_slave_inst(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137301388/source,data/full_repos/permissive/137301388/spi_slave\n             data/full_repos/permissive/137301388/source,data/full_repos/permissive/137301388/spi_slave.v\n             data/full_repos/permissive/137301388/source,data/full_repos/permissive/137301388/spi_slave.sv\n             spi_slave\n             spi_slave.v\n             spi_slave.sv\n             obj_dir/spi_slave\n             obj_dir/spi_slave.v\n             obj_dir/spi_slave.sv\n%Error: data/full_repos/permissive/137301388/source/spi_slave_mm_top.v:152: Cannot find file containing module: 'mm_con'\nmm_con #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) mm_con_inst(\n^~~~~~\n%Error: data/full_repos/permissive/137301388/source/spi_slave_mm_top.v:171: Cannot find file containing module: 'product_test'\nproduct_test #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) product_test_inst(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/137301388/source/spi_slave_mm_top.v:183: Cannot find file containing module: 'int_ctrl'\nint_ctrl #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) int_ctrl_inst(\n^~~~~~~~\n%Error: data/full_repos/permissive/137301388/source/spi_slave_mm_top.v:199: Cannot find file containing module: 'sys_wdt'\nsys_wdt #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) sys_wdt_inst(\n^~~~~~~\n%Error: data/full_repos/permissive/137301388/source/spi_slave_mm_top.v:212: Cannot find file containing module: 'led_ctrl'\nled_ctrl #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) led_ctrl_inst(\n^~~~~~~~\n%Error: data/full_repos/permissive/137301388/source/spi_slave_mm_top.v:229: Cannot find file containing module: 'clock_div'\nclock_div clock_div_inst(\n^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module spi_slave_mm_top(










ext_clk,
rst_n,


spi_sclk,
spi_mosi,
spi_miso,
spi_cs_n,


led_ctrl,
led_debug,


int_ext,
int_sys,


pid_strap
);


parameter MM_ADDR_WIDTH = 8;
parameter MM_DATA_WIDTH = 16;




input ext_clk, rst_n;


input spi_sclk, spi_mosi, spi_cs_n;
output spi_miso;


input[3:0] pid_strap;


output[3:0] led_ctrl, led_debug;

input[2:0] int_ext;
output int_sys;












wire[MM_ADDR_WIDTH-1:0] m_addr;
wire[MM_DATA_WIDTH-1:0] m_wdata;
wire[MM_DATA_WIDTH-1:0] m_rdata;
wire m_we;

wire[MM_ADDR_WIDTH-1:0] s_addr;
wire[MM_DATA_WIDTH-1:0] s_wdata;
wire[MM_DATA_WIDTH-1:0] s_rdata0, s_rdata1, s_rdata2, s_rdata3, s_rdata4;
wire s_we;

reg[1:0] sync_rst;

wire clk_16hz, clk_8hz, clk_1hz, clk_128hz;
wire[3:0] led_ctrl, led_debug;
wire wdt_ot;











always @(posedge ext_clk)
begin
	sync_rst[0] <= rst_n;
	sync_rst[1] <= sync_rst[0];
end


spi_slave #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) spi_slave_inst(








	
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),

	.spi_sclk_i(spi_sclk),
	.spi_mosi_i(spi_mosi),
	.spi_miso_o(spi_miso),
	.spi_cs_n_i(spi_cs_n),
	
	.mm_m_addr_o(m_addr),
	.mm_m_wdata_o(m_wdata),
	.mm_m_rdata_i(m_rdata),
	.mm_m_we_o(m_we)
	);

mm_con #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) mm_con_inst(
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),
	
	.m_addr_i(m_addr),
	.m_wdata_i(m_wdata),
	.m_rdata_o(m_rdata),
	.m_we_i(m_we),
	
	.s_addr_o(s_addr),
	.s_wdata_o(s_wdata),
	.s_rdata0_i(s_rdata0),
	.s_rdata1_i(s_rdata1),
	.s_rdata2_i(s_rdata2),
	.s_rdata3_i(s_rdata3),
	.s_rdata4_i(s_rdata4),
	.s_we_o(s_we)
	);

product_test #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) product_test_inst(
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),
	
	.mm_s_addr_i(s_addr),
	.mm_s_wdata_i(s_wdata),
	.mm_s_rdata_o(s_rdata0),
	.mm_s_we_i(s_we),
	
	.pid_strap_i(pid_strap)
	);	
	
int_ctrl #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) int_ctrl_inst(
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),

	.mm_s_addr_i(s_addr),
	.mm_s_wdata_i(s_wdata),
	.mm_s_rdata_o(s_rdata1),
	.mm_s_we_i(s_we),

	.int_a_i(int_ext[0]), 
	.int_b_i(int_ext[1]), 
	.int_c_i(int_ext[2]), 
	.int_wdt_i(wdt_ot),
	.sys_int_o(int_sys)
);

sys_wdt #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) sys_wdt_inst(
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),

	.mm_s_addr_i(s_addr),
	.mm_s_wdata_i(s_wdata),
	.mm_s_rdata_o(s_rdata2),
	.mm_s_we_i(s_we),

	.clk_8hz_i(clk_8hz),
	.wdt_ot_o(wdt_ot)
);

led_ctrl #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) led_ctrl_inst(
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),

	.mm_s_addr_i(s_addr),
	.mm_s_wdata_i(s_wdata),
	.mm_s_rdata_o(s_rdata3),
	.mm_s_we_i(s_we),

	.clk_16hz_i(clk_16hz),
	.clk_8hz_i(clk_8hz),
	.clk_1hz_i(clk_1hz),

	.led_ctrl_o(led_ctrl),
	.led_debug_o(led_debug)
);
	
clock_div clock_div_inst(
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),
	
	.clk_16hz_o(clk_16hz),
	.clk_8hz_o(clk_8hz),
	.clk_1hz_o(clk_1hz),
	.clk_128hz_o(clk_128hz)
	);	
	













endmodule
module spi_slave_mm_top(










ext_clk,
rst_n,


spi_sclk,
spi_mosi,
spi_miso,
spi_cs_n,


led_ctrl,
led_debug,


int_ext,
int_sys,


pid_strap
);



parameter MM_ADDR_WIDTH = 8;
parameter MM_DATA_WIDTH = 16;




input ext_clk, rst_n;


input spi_sclk, spi_mosi, spi_cs_n;
output spi_miso;


input[3:0] pid_strap;


output[3:0] led_ctrl, led_debug;

input[2:0] int_ext;
output int_sys;












wire[MM_ADDR_WIDTH-1:0] m_addr;
wire[MM_DATA_WIDTH-1:0] m_wdata;
wire[MM_DATA_WIDTH-1:0] m_rdata;
wire m_we;

wire[MM_ADDR_WIDTH-1:0] s_addr;
wire[MM_DATA_WIDTH-1:0] s_wdata;
wire[MM_DATA_WIDTH-1:0] s_rdata0, s_rdata1, s_rdata2, s_rdata3, s_rdata4;
wire s_we;

reg[1:0] sync_rst;

wire clk_16hz, clk_8hz, clk_1hz, clk_128hz;
wire[3:0] led_ctrl, led_debug;
wire wdt_ot;











always @(posedge ext_clk)
begin
	sync_rst[0] <= rst_n;
	sync_rst[1] <= sync_rst[0];
end


spi_slave #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) spi_slave_inst(








	
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),

	.spi_sclk_i(spi_sclk),
	.spi_mosi_i(spi_mosi),
	.spi_miso_o(spi_miso),
	.spi_cs_n_i(spi_cs_n),
	
	.mm_m_addr_o(m_addr),
	.mm_m_wdata_o(m_wdata),
	.mm_m_rdata_i(m_rdata),
	.mm_m_we_o(m_we)
	);

mm_con #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) mm_con_inst(
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),
	
	.m_addr_i(m_addr),
	.m_wdata_i(m_wdata),
	.m_rdata_o(m_rdata),
	.m_we_i(m_we),
	
	.s_addr_o(s_addr),
	.s_wdata_o(s_wdata),
	.s_rdata0_i(s_rdata0),
	.s_rdata1_i(s_rdata1),
	.s_rdata2_i(s_rdata2),
	.s_rdata3_i(s_rdata3),
	.s_rdata4_i(s_rdata4),
	.s_we_o(s_we)
	);

product_test #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) product_test_inst(
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),
	
	.mm_s_addr_i(s_addr),
	.mm_s_wdata_i(s_wdata),
	.mm_s_rdata_o(s_rdata0),
	.mm_s_we_i(s_we),
	
	.pid_strap_i(pid_strap)
	);	
	
int_ctrl #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) int_ctrl_inst(
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),

	.mm_s_addr_i(s_addr),
	.mm_s_wdata_i(s_wdata),
	.mm_s_rdata_o(s_rdata1),
	.mm_s_we_i(s_we),

	.int_a_i(int_ext[0]), 
	.int_b_i(int_ext[1]), 
	.int_c_i(int_ext[2]), 
	.int_wdt_i(wdt_ot),
	.sys_int_o(int_sys)
);

sys_wdt #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) sys_wdt_inst(
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),

	.mm_s_addr_i(s_addr),
	.mm_s_wdata_i(s_wdata),
	.mm_s_rdata_o(s_rdata2),
	.mm_s_we_i(s_we),

	.clk_8hz_i(clk_8hz),
	.wdt_ot_o(wdt_ot)
);

led_ctrl #(.MM_ADDR_WIDTH(MM_ADDR_WIDTH), .MM_DATA_WIDTH(MM_DATA_WIDTH)) led_ctrl_inst(
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),

	.mm_s_addr_i(s_addr),
	.mm_s_wdata_i(s_wdata),
	.mm_s_rdata_o(s_rdata3),
	.mm_s_we_i(s_we),

	.clk_16hz_i(clk_16hz),
	.clk_8hz_i(clk_8hz),
	.clk_1hz_i(clk_1hz),

	.led_ctrl_o(led_ctrl),
	.led_debug_o(led_debug)
);
	
clock_div clock_div_inst(
	.clk_sys_i(ext_clk),
	.rst_n_i(sync_rst[1]),
	
	.clk_16hz_o(clk_16hz),
	.clk_8hz_o(clk_8hz),
	.clk_1hz_o(clk_1hz),
	.clk_128hz_o(clk_128hz)
	);	
	













endmodule