data/full_repos/permissive/148200700/Quartus/designFiles/ip/KBandIPsubPro/KBandIPsubPro_clk_0/KBandIPsubPro_clk_0_bb.v
data/verilator_xmls/9de19e90-059d-48cc-aba5-ffba16678e27.xml
module KBandIPsubPro_clk_0 (
		input  wire  in_clk,
		input  wire  reset_n,
		output wire  clk_out,
		output wire  reset_n_out
	);
endmodule
module KBandIPsubPro_clk_0 (
		input  wire  in_clk,
		input  wire  reset_n,
		output wire  clk_out,
		output wire  reset_n_out
	);

endmodule