data/full_repos/permissive/157135695/logical.v
None: at end of input
data/verilator_xmls/f9240ce0-7d82-4f5e-b443-598fbdbcd1b5.xml
module logical(A, B, OP, Y);

	input [7:0] A; 
	input [7:0] B; 
	input OP;  

	output [7:0] Y;
  









  
  assign Y=OP?(A&B):(A|B);
  




endmodule
module logical(A, B, OP, Y);


	input [7:0] A; 
	input [7:0] B; 
	input OP;  

	output [7:0] Y;
  









  
  assign Y=OP?(A&B):(A|B);
  




endmodule