data/full_repos/permissive/172538466/hw/src/synth/top_syn.v
None: at end of input
1: b'%Error: data/full_repos/permissive/172538466/hw/src/synth/top_syn.v:1: Cannot find include file: defs.vh\n`include "defs.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172538466/hw/src/synth,data/full_repos/permissive/172538466/defs.vh\n             data/full_repos/permissive/172538466/hw/src/synth,data/full_repos/permissive/172538466/defs.vh.v\n             data/full_repos/permissive/172538466/hw/src/synth,data/full_repos/permissive/172538466/defs.vh.sv\n             defs.vh\n             defs.vh.v\n             defs.vh.sv\n             obj_dir/defs.vh\n             obj_dir/defs.vh.v\n             obj_dir/defs.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module top_syn
  (
   input        CLK_I,

   output [7:0] LED_IO,


   input        UART_RTS_N_I,
   input        UART_RX_I,
   output       UART_TX_O,
   output       UART_CTS_N_O
   );



   assign UART_CTS_N_O = 0;



   wire [7:0]   data_in;
   wire [7:0]   data_out;
   wire [7:0]   dir;
   assign data_in = LED_IO;




   assign LED_IO = dir & data_out;


   top top0
     (
      .CLK_I(CLK_I),
      .RESET_I(UART_RTS_N_I),

      .RX_I(UART_RX_I),
      .TX_O(UART_TX_O),

      .PORT_I(data_in),
      .PORT_O(data_out),
      .DIR_O(dir)
      );

endmodule
module top_syn
  (
   input        CLK_I,

   output [7:0] LED_IO,


   input        UART_RTS_N_I,
   input        UART_RX_I,
   output       UART_TX_O,
   output       UART_CTS_N_O
   );




   assign UART_CTS_N_O = 0;



   wire [7:0]   data_in;
   wire [7:0]   data_out;
   wire [7:0]   dir;
   assign data_in = LED_IO;




   assign LED_IO = dir & data_out;


   top top0
     (
      .CLK_I(CLK_I),
      .RESET_I(UART_RTS_N_I),

      .RX_I(UART_RX_I),
      .TX_O(UART_TX_O),

      .PORT_I(data_in),
      .PORT_O(data_out),
      .DIR_O(dir)
      );

endmodule