data/full_repos/permissive/164251444/analog/cdk_oa/NSW1/netlist/Pre_netlist/verilog.v
 line:14: before: "CDS_LIBNAME"
1: b'%Warning-MULTITOP: data/full_repos/permissive/164251444/analog/cdk_oa/NSW1/netlist/Pre_netlist/verilog.v:29: Multiple top level modules\n                                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                           : ... Top module \'nsw1\'\nmodule nsw1 ( NEG, POS, VDD, VNW, VPW, VSS, SW );\n       ^~~~\n                                                                                                           : ... Top module \'nfet1\'\nmodule nfet1 ( D, G, S, VDD, VNW, VPW, VSS );\n       ^~~~~\n%Error: data/full_repos/permissive/164251444/analog/cdk_oa/NSW1/netlist/Pre_netlist/verilog.v:44: Cannot find file containing module: \'NFET_B\'\nNFET_B  N0 ( .b(VPW), .s(S), .g(G), .d(D));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164251444/analog/cdk_oa/NSW1/netlist/Pre_netlist,data/full_repos/permissive/164251444/NFET_B\n             data/full_repos/permissive/164251444/analog/cdk_oa/NSW1/netlist/Pre_netlist,data/full_repos/permissive/164251444/NFET_B.v\n             data/full_repos/permissive/164251444/analog/cdk_oa/NSW1/netlist/Pre_netlist,data/full_repos/permissive/164251444/NFET_B.sv\n             NFET_B\n             NFET_B.v\n             NFET_B.sv\n             obj_dir/NFET_B\n             obj_dir/NFET_B.v\n             obj_dir/NFET_B.sv\n%Error: data/full_repos/permissive/164251444/analog/cdk_oa/NSW1/netlist/Pre_netlist/verilog.v:19: Cannot find file containing module: \'NFET1\'\nNFET1 I0 ( .VDD(VDD), .VSS(VSS), .VNW(VNW), .VPW(VPW), .S(NEG),\n^~~~~\n%Error: data/full_repos/permissive/164251444/analog/cdk_oa/NSW1/netlist/Pre_netlist/verilog.v:21: Cannot find file containing module: \'SC7P5T_INVX0P5_SSC14R\'\nSC7P5T_INVX0P5_SSC14R I2 ( .VPW(VPW), .VNW(VNW), .VSS(VSS), .VDD(VDD),\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/164251444/analog/cdk_oa/NSW1/netlist/Pre_netlist/verilog.v:23: Cannot find file containing module: \'SC7P5T_INVX0P5_SSC14R\'\nSC7P5T_INVX0P5_SSC14R I1 ( .VPW(VPW), .VNW(VNW), .VSS(VSS), .VDD(VDD),\n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module nsw1 ( NEG, POS, VDD, VNW, VPW, VSS, SW );

  inout POS;
  inout NEG;
  inout VNW;
  inout VDD;
  input SW;
  inout VSS;
  inout VPW;
specify 
    specparam CDS_LIBNAME  = "RAIL12";
    specparam CDS_CELLNAME = "nsw1";
    specparam CDS_VIEWNAME = "schematic";
endspecify

NFET1 I0 ( .VDD(VDD), .VSS(VSS), .VNW(VNW), .VPW(VPW), .S(NEG),
     .D(POS), .G(NET7));
SC7P5T_INVX0P5_SSC14R I2 ( .VPW(VPW), .VNW(VNW), .VSS(VSS), .VDD(VDD),
     .Z(NET6), .A(SW));
SC7P5T_INVX0P5_SSC14R I1 ( .VPW(VPW), .VNW(VNW), .VSS(VSS), .VDD(VDD),
     .Z(NET7), .A(NET6));


endmodule
module nsw1 ( NEG, POS, VDD, VNW, VPW, VSS, SW );


  inout POS;
  inout NEG;
  inout VNW;
  inout VDD;
  input SW;
  inout VSS;
  inout VPW;
specify 
    specparam CDS_LIBNAME  = "RAIL12";
    specparam CDS_CELLNAME = "nsw1";
    specparam CDS_VIEWNAME = "schematic";
endspecify

NFET1 I0 ( .VDD(VDD), .VSS(VSS), .VNW(VNW), .VPW(VPW), .S(NEG),
     .D(POS), .G(NET7));
SC7P5T_INVX0P5_SSC14R I2 ( .VPW(VPW), .VNW(VNW), .VSS(VSS), .VDD(VDD),
     .Z(NET6), .A(SW));
SC7P5T_INVX0P5_SSC14R I1 ( .VPW(VPW), .VNW(VNW), .VSS(VSS), .VDD(VDD),
     .Z(NET7), .A(NET6));


endmodule