data/full_repos/permissive/175316557/system.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/175316557/system.v:93: Multiple top level modules\n                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                   : ... Top module \'game_levels\'\nmodule game_levels(\n       ^~~~~~~~~~~\n                                                                   : ... Top module \'level_handler\'\n    module level_handler(\n           ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/175316557/system.v:291: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                 : ... In instance level_handler\n        cur_x <= 8\'b00000000;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/175316557/system.v:290: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'cur_x\' generates 5 bits.\n                                                                 : ... In instance level_handler\n      if (cur_x == 8\'d19) begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/175316557/system.v:24: Operator NEQ expects 3 bits on the LHS, but LHS\'s VARREF \'keycode\' generates 1 bits.\n                                                                : ... In instance game_levels\nassign wkeypressed = (keycode != 3\'b000);\n                              ^~\n%Error: Exiting due to 4 warning(s)\n'
module game_levels(
           input clock,
           input keycode,
           input reset_n,
           input w_level_complete,
           output reg ld_loading,
           output reg [3:0] ld_level_num
       );

reg [3:0] current_state, next_state;

localparam  S_INTRO = 4'd0,
            S_LEVEL_1 = 4'd1,
            S_LEVEL_1_WAIT = 4'd2,
            S_LEVEL_2 = 4'd3,
            S_LEVEL_2_WAIT = 4'd4,
            S_LEVEL_3 = 4'd5,
            S_LEVEL_3_WAIT = 4'd6,
            S_LEVEL_4 = 4'd7,
            S_OUTRO = 4'd8;

wire wkeypressed;
assign wkeypressed = (keycode != 3'b000);

always @(*)
begin: state_table
    case (current_state)
        S_INTRO: next_state = wkeypressed ? S_LEVEL_1 : S_INTRO;
        S_LEVEL_1: next_state = w_level_complete ? S_LEVEL_1_WAIT: S_LEVEL_1;
        S_LEVEL_1_WAIT: next_state = wkeypressed ? S_LEVEL_2 : S_LEVEL_1_WAIT;
        S_LEVEL_2: next_state = w_level_complete ? S_LEVEL_2_WAIT: S_LEVEL_2;
        S_LEVEL_2_WAIT: next_state = wkeypressed ? S_LEVEL_3 : S_LEVEL_2_WAIT;
        S_LEVEL_3: next_state = w_level_complete ? S_LEVEL_3_WAIT: S_LEVEL_3;
        S_LEVEL_3_WAIT: next_state = wkeypressed ? S_LEVEL_4 : S_LEVEL_3_WAIT;
        S_LEVEL_4: next_state = w_level_complete ? S_OUTRO: S_LEVEL_4;
        S_OUTRO: next_state = wkeypressed ? S_LEVEL_1 : S_OUTRO;
    endcase
end
always @(*)
begin

    ld_level_num = 4'b0000;
    ld_loading = 1'b0;
    case (current_state)
        S_INTRO: begin
            ld_level_num = 4'b0000;
            ld_loading = 1'b1;
        end
        S_LEVEL_1: begin
            ld_level_num = 4'b0000;
        end
        S_LEVEL_1_WAIT: begin
            ld_level_num = 4'b0001;
            ld_loading = 1'b1;
        end
        S_LEVEL_2: begin
            ld_level_num = 4'b0001;
        end
        S_LEVEL_2_WAIT: begin
            ld_level_num = 4'b0010;
            ld_loading = 1'b1;
        end
        S_LEVEL_3: begin
            ld_level_num = 4'b0010;
        end
        S_LEVEL_3_WAIT: begin
            ld_level_num = 4'b0011;
            ld_loading = 1'b1;
        end
        S_LEVEL_4: begin
            ld_level_num = 4'b0011;
        end
        S_OUTRO: begin
            ld_level_num = 4'b0000;
            ld_loading = 1'b1;
        end
    endcase
end

always @(posedge clock)
begin: state_FFS
    if (!reset_n)
        current_state = S_INTRO;
    else
        current_state = next_state;
end

endmodule
module game_levels(
           input clock,
           input keycode,
           input reset_n,
           input w_level_complete,
           output reg ld_loading,
           output reg [3:0] ld_level_num
       );


reg [3:0] current_state, next_state;

localparam  S_INTRO = 4'd0,
            S_LEVEL_1 = 4'd1,
            S_LEVEL_1_WAIT = 4'd2,
            S_LEVEL_2 = 4'd3,
            S_LEVEL_2_WAIT = 4'd4,
            S_LEVEL_3 = 4'd5,
            S_LEVEL_3_WAIT = 4'd6,
            S_LEVEL_4 = 4'd7,
            S_OUTRO = 4'd8;

wire wkeypressed;
assign wkeypressed = (keycode != 3'b000);

always @(*)
begin: state_table
    case (current_state)
        S_INTRO: next_state = wkeypressed ? S_LEVEL_1 : S_INTRO;
        S_LEVEL_1: next_state = w_level_complete ? S_LEVEL_1_WAIT: S_LEVEL_1;
        S_LEVEL_1_WAIT: next_state = wkeypressed ? S_LEVEL_2 : S_LEVEL_1_WAIT;
        S_LEVEL_2: next_state = w_level_complete ? S_LEVEL_2_WAIT: S_LEVEL_2;
        S_LEVEL_2_WAIT: next_state = wkeypressed ? S_LEVEL_3 : S_LEVEL_2_WAIT;
        S_LEVEL_3: next_state = w_level_complete ? S_LEVEL_3_WAIT: S_LEVEL_3;
        S_LEVEL_3_WAIT: next_state = wkeypressed ? S_LEVEL_4 : S_LEVEL_3_WAIT;
        S_LEVEL_4: next_state = w_level_complete ? S_OUTRO: S_LEVEL_4;
        S_OUTRO: next_state = wkeypressed ? S_LEVEL_1 : S_OUTRO;
    endcase
end
always @(*)
begin

    ld_level_num = 4'b0000;
    ld_loading = 1'b0;
    case (current_state)
        S_INTRO: begin
            ld_level_num = 4'b0000;
            ld_loading = 1'b1;
        end
        S_LEVEL_1: begin
            ld_level_num = 4'b0000;
        end
        S_LEVEL_1_WAIT: begin
            ld_level_num = 4'b0001;
            ld_loading = 1'b1;
        end
        S_LEVEL_2: begin
            ld_level_num = 4'b0001;
        end
        S_LEVEL_2_WAIT: begin
            ld_level_num = 4'b0010;
            ld_loading = 1'b1;
        end
        S_LEVEL_3: begin
            ld_level_num = 4'b0010;
        end
        S_LEVEL_3_WAIT: begin
            ld_level_num = 4'b0011;
            ld_loading = 1'b1;
        end
        S_LEVEL_4: begin
            ld_level_num = 4'b0011;
        end
        S_OUTRO: begin
            ld_level_num = 4'b0000;
            ld_loading = 1'b1;
        end
    endcase
end

always @(posedge clock)
begin: state_FFS
    if (!reset_n)
        current_state = S_INTRO;
    else
        current_state = next_state;
end

endmodule