data/full_repos/permissive/109608368/check/Summarize12.v
data/verilator_xmls/177ac7e2-f299-4a69-9016-bd9932ab677c.xml
module Summarize12(check_ans, out);
    input [23:0] check_ans;
    output reg [1:0] out;

    always@(*)
    begin

        if((check_ans[1:0] == 2'b00) && (check_ans[3:2] == 2'b00)  && (check_ans[5:4] == 2'b00) && (check_ans[7:6] == 2'b00)
           && (check_ans[9:8] == 2'b00) && (check_ans[11:10] == 2'b00) && (check_ans[13:12] == 2'b00) && (check_ans[15:14] == 2'b00)
           && (check_ans[17:16] == 2'b00) && (check_ans[19:18] == 2'b00) && (check_ans[21:20] == 2'b00) && (check_ans[23:22] == 2'b00))
            out = 2'b00;

        else if((check_ans[1:0] == 2'b01) || (check_ans[3:2] == 2'b01)  || (check_ans[5:4] == 2'b01) || (check_ans[7:6] == 2'b01)
            || (check_ans[9:8] == 2'b01) || (check_ans[11:10] == 2'b01) || (check_ans[13:12] == 2'b01) || (check_ans[15:14] == 2'b01)
            || (check_ans[17:16] == 2'b01) || (check_ans[19:18] == 2'b01) || (check_ans[21:20] == 2'b01) || (check_ans[23:22] == 2'b01))
           out = 2'b01;

        else 
           out = 2'b10;

    end

endmodule
module Summarize12(check_ans, out);

    input [23:0] check_ans;
    output reg [1:0] out;

    always@(*)
    begin

        if((check_ans[1:0] == 2'b00) && (check_ans[3:2] == 2'b00)  && (check_ans[5:4] == 2'b00) && (check_ans[7:6] == 2'b00)
           && (check_ans[9:8] == 2'b00) && (check_ans[11:10] == 2'b00) && (check_ans[13:12] == 2'b00) && (check_ans[15:14] == 2'b00)
           && (check_ans[17:16] == 2'b00) && (check_ans[19:18] == 2'b00) && (check_ans[21:20] == 2'b00) && (check_ans[23:22] == 2'b00))
            out = 2'b00;

        else if((check_ans[1:0] == 2'b01) || (check_ans[3:2] == 2'b01)  || (check_ans[5:4] == 2'b01) || (check_ans[7:6] == 2'b01)
            || (check_ans[9:8] == 2'b01) || (check_ans[11:10] == 2'b01) || (check_ans[13:12] == 2'b01) || (check_ans[15:14] == 2'b01)
            || (check_ans[17:16] == 2'b01) || (check_ans[19:18] == 2'b01) || (check_ans[21:20] == 2'b01) || (check_ans[23:22] == 2'b01))
           out = 2'b01;

        else 
           out = 2'b10;

    end

endmodule