data/full_repos/permissive/220347822/fpga-shells/xilinx/vcu118/vsrc/vcu118reset.v
1: b'%Warning-WIDTH: data/full_repos/permissive/220347822/fpga-shells/xilinx/vcu118/vsrc/vcu118reset.v:53: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                                    : ... In instance vcu118reset.hold_clock0\n  reg [8:0] debounce_reset = {8{1\'b1}};\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/220347822/fpga-shells/xilinx/vcu118/vsrc/vcu118reset.v:70: Operator SUB expects 9 bits on the RHS, but RHS\'s VARREF \'out_reset\' generates 1 bits.\n                                                                                                    : ... In instance vcu118reset.hold_clock0\n      debounce_reset <= debounce_reset - out_reset;\n                                       ^\n%Error: Exiting due to 2 warning(s)\n'
module sifive_reset_hold(
  input  wire areset,
  input  wire clock,
  output wire reset
);
  wire raw_reset;
  reg [`RESET_SYNC-1:0] sync_reset = {`RESET_SYNC{1'b1}};
  reg [`DEBOUNCE_BITS:0] debounce_reset = {`DEBOUNCE_BITS{1'b1}};
  wire out_reset;


  sifive_reset_sync capture(areset, clock, raw_reset);


  always @(posedge clock) begin
    sync_reset <= {raw_reset,sync_reset[`RESET_SYNC-1:1]};
  end


  assign out_reset = debounce_reset[`DEBOUNCE_BITS];
  always @(posedge clock) begin
    if (sync_reset[0]) begin
      debounce_reset <= {(`DEBOUNCE_BITS+1){1'b1}};
    end else begin
      debounce_reset <= debounce_reset - out_reset;
    end
  end

  assign reset = out_reset;

endmodule
module sifive_reset_hold(
  input  wire areset,
  input  wire clock,
  output wire reset
);

  wire raw_reset;
  reg [`RESET_SYNC-1:0] sync_reset = {`RESET_SYNC{1'b1}};
  reg [`DEBOUNCE_BITS:0] debounce_reset = {`DEBOUNCE_BITS{1'b1}};
  wire out_reset;


  sifive_reset_sync capture(areset, clock, raw_reset);


  always @(posedge clock) begin
    sync_reset <= {raw_reset,sync_reset[`RESET_SYNC-1:1]};
  end


  assign out_reset = debounce_reset[`DEBOUNCE_BITS];
  always @(posedge clock) begin
    if (sync_reset[0]) begin
      debounce_reset <= {(`DEBOUNCE_BITS+1){1'b1}};
    end else begin
      debounce_reset <= debounce_reset - out_reset;
    end
  end

  assign reset = out_reset;

endmodule