data/full_repos/permissive/114324064/src/cpu-riscv.v
1: b'%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.v\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:11: Define or directive not defined: \'`RegBus\'\n    output wire[`RegBus]           rom_addr_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    output wire[`RegBus]           rom_addr_o,\n                       ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`RegBus]            ram_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:15: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus]            ram_data_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:16: Define or directive not defined: \'`RegBus\'\n    output wire[`RegBus]           ram_addr_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:17: Define or directive not defined: \'`RegBus\'\n    output wire[`RegBus]           ram_data_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[3:0]               ram_sel_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                    ram_ce_o\n    ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:25: Define or directive not defined: \'`RegBus\'\n    wire [`RegBus] id_branch_target_addr_o;\n          ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`RegBus] id_branch_target_addr_o;\n                 ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:32: syntax error, unexpected IDENTIFIER\n    ctrl ctrl0(\n    ^~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:40: Define or directive not defined: \'`InstAddrBus\'\n    wire[`InstAddrBus] pc;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`InstAddrBus] pc;\n                     ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:52: Define or directive not defined: \'`InstBus\'\n    wire[`InstBus] inst;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`InstBus] inst;\n                 ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:69: Define or directive not defined: \'`InstAddrBus\'\n    wire[`InstAddrBus] id_pc_i;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:69: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`InstAddrBus] id_pc_i;\n                     ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:70: Define or directive not defined: \'`InstBus\'\n    wire[`InstBus] id_inst_i;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:70: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`InstBus] id_inst_i;\n                 ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:83: Define or directive not defined: \'`AluOpBus\'\n    wire[`AluOpBus] id_aluop_o;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:83: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`AluOpBus] id_aluop_o;\n                  ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:84: Define or directive not defined: \'`AluSelBus\'\n    wire[`AluSelBus] id_alusel_o;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:84: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`AluSelBus] id_alusel_o;\n                   ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:85: Define or directive not defined: \'`RegBus\'\n    wire[`RegBus] id_reg1_o;\n         ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:85: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegBus] id_reg1_o;\n                ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:86: Define or directive not defined: \'`RegBus\'\n    wire[`RegBus] id_reg2_o;\n         ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:86: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegBus] id_reg2_o;\n                ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:88: Define or directive not defined: \'`RegAddrBus\'\n    wire[`RegAddrBus] id_wd_o;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:88: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegAddrBus] id_wd_o;\n                    ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:89: Define or directive not defined: \'`RegBus\'\n    wire[`RegBus] id_link_addr_o;\n         ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:89: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegBus] id_link_addr_o;\n                ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:90: Define or directive not defined: \'`RegBus\'\n    wire[`RegBus] id_offset_o;\n         ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:90: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegBus] id_offset_o;\n                ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:96: Define or directive not defined: \'`RegBus\'\n    wire[`RegBus] reg1_data;\n         ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:96: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegBus] reg1_data;\n                ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:97: Define or directive not defined: \'`RegBus\'\n    wire[`RegBus] reg2_data;\n         ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:97: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegBus] reg2_data;\n                ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:98: Define or directive not defined: \'`RegAddrBus\'\n    wire[`RegAddrBus] reg1_addr;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:98: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegAddrBus] reg1_addr;\n                    ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:99: Define or directive not defined: \'`RegAddrBus\'\n    wire[`RegAddrBus] reg2_addr;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:99: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegAddrBus] reg2_addr;\n                    ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:102: Define or directive not defined: \'`RegAddrBus\'\n    wire[`RegAddrBus] ex_wd_o;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:102: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegAddrBus] ex_wd_o;\n                    ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:103: Define or directive not defined: \'`RegBus\'\n    wire[`RegBus] ex_wdata_o;\n         ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:103: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegBus] ex_wdata_o;\n                ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:104: Define or directive not defined: \'`AluOpBus\'\n    wire[`AluOpBus] ex_aluop_o;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:104: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`AluOpBus] ex_aluop_o;\n                  ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:105: Define or directive not defined: \'`RegBus\'\n    wire[`RegBus] ex_mem_addr_o;\n         ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:105: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`RegBus] ex_mem_addr_o;\n                ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module cpu_riscv(

    input wire                     clk,
    input wire                     rst,


    input wire[127:0]              rom_data_i,
    input wire                     rom_done_i,
    output wire[`RegBus]           rom_addr_o,
    output wire                    rom_read_o,


    input wire[`RegBus]            ram_data_i,
    output wire[`RegBus]           ram_addr_o,
    output wire[`RegBus]           ram_data_o,
    output wire                    ram_we_o,
    output wire[3:0]               ram_sel_o,
    output wire                    ram_ce_o
);


    wire id_branch_flag_o;
    wire [`RegBus] id_branch_target_addr_o;


    wire[5:0] stall;
    wire stallreq_from_ic;
    wire stallreq_from_id;

    ctrl ctrl0(
        .rst(rst),
        .stallreq_from_id(stallreq_from_id),
        .stallreq_from_ic(stallreq_from_ic),
        .stall(stall)
    );


    wire[`InstAddrBus] pc;

    pc_reg pc_reg0(
        .clk(clk),
        .rst(rst),
        .stall(stall),
        .branch_flag_i(id_branch_flag_o),
        .branch_target_addr_i(id_branch_target_addr_o),
        .pc(pc)
    );


    wire[`InstBus] inst;

    i_cache i_cache0(
        .clk(clk),
        .rst(rst),

        .core_addr_i(pc),
        .core_data_o(inst),
        .core_stallreq_o(stallreq_from_ic),

        .mem_data_i(rom_data_i),
        .mem_done_i(rom_done_i),
        .mem_read_o(rom_read_o),
        .mem_addr_o(rom_addr_o)
    );


    wire[`InstAddrBus] id_pc_i;
    wire[`InstBus] id_inst_i;

    if_id if_id0(
        .clk(clk),
        .rst(rst),
        .stall(stall),
        .if_pc(pc),
        .if_inst(inst),
        .id_pc(id_pc_i),
        .id_inst(id_inst_i)
    );


    wire[`AluOpBus] id_aluop_o;
    wire[`AluSelBus] id_alusel_o;
    wire[`RegBus] id_reg1_o;
    wire[`RegBus] id_reg2_o;
    wire id_wreg_o;
    wire[`RegAddrBus] id_wd_o;
    wire[`RegBus] id_link_addr_o;
    wire[`RegBus] id_offset_o;
    wire id_next_inst_invalid_o;
    wire id_inst_invalid_i;

    wire reg1_read;
    wire reg2_read;
    wire[`RegBus] reg1_data;
    wire[`RegBus] reg2_data;
    wire[`RegAddrBus] reg1_addr;
    wire[`RegAddrBus] reg2_addr;

    wire ex_wreg_o;
    wire[`RegAddrBus] ex_wd_o;
    wire[`RegBus] ex_wdata_o;
    wire[`AluOpBus] ex_aluop_o;
    wire[`RegBus] ex_mem_addr_o;
    wire[`RegBus] ex_reg2_o;

    wire mem_wreg_o;
    wire[`RegAddrBus] mem_wd_o;
    wire[`RegBus] mem_wdata_o;

    wire wb_wreg_i;
    wire[`RegAddrBus] wb_wd_i;
    wire[`RegBus] wb_wdata_i;

    id id0(
        .rst(rst),

        .pc_i(id_pc_i),
        .inst_i(id_inst_i),

        .ex_wreg_i(ex_wreg_o),
        .ex_wdata_i(ex_wdata_o),
        .ex_wd_i(ex_wd_o),

        .mem_wreg_i(mem_wreg_o),
        .mem_wdata_i(mem_wdata_o),
        .mem_wd_i(mem_wd_o),

        .ex_aluop_i(ex_aluop_o),

        .reg1_data_i(reg1_data),
        .reg2_data_i(reg2_data),

        .inst_invalid_i(id_inst_invalid_i),

        .reg1_read_o(reg1_read),
        .reg2_read_o(reg2_read),
        .reg1_addr_o(reg1_addr),
        .reg2_addr_o(reg2_addr),

        .aluop_o(id_aluop_o),
        .alusel_o(id_alusel_o),
        .reg1_o(id_reg1_o),
        .reg2_o(id_reg2_o),
        .wd_o(id_wd_o),
        .wreg_o(id_wreg_o),
        .offset_o(id_offset_o),
        .next_inst_invalid_o(id_next_inst_invalid_o),

        .branch_flag_o(id_branch_flag_o),
        .branch_target_addr_o(id_branch_target_addr_o),
        .link_addr_o(id_link_addr_o),

        .stallreq(stallreq_from_id)
    );

    regfile regfile0(
        .clk(clk),
        .rst(rst),
        .we(wb_wreg_i),
        .waddr(wb_wd_i),
        .wdata(wb_wdata_i),
        .re1(reg1_read),
        .raddr1(reg1_addr),
        .rdata1(reg1_data),
        .re2(reg2_read),
        .raddr2(reg2_addr),
        .rdata2(reg2_data)
    );


    wire[`AluOpBus] ex_aluop_i;
    wire[`AluSelBus] ex_alusel_i;
    wire[`RegBus] ex_reg1_i;
    wire[`RegBus] ex_reg2_i;
    wire ex_wreg_i;
    wire[`RegAddrBus] ex_wd_i;
    wire[`RegBus] ex_link_addr_i;
    wire[`RegBus] ex_offset_i;

    id_ex id_ex0(
        .clk(clk),
        .rst(rst),
        .stall(stall),

        .id_aluop(id_aluop_o),
        .id_alusel(id_alusel_o),
        .id_reg1(id_reg1_o),
        .id_reg2(id_reg2_o),
        .id_wd(id_wd_o),
        .id_wreg(id_wreg_o),
        .id_link_addr(id_link_addr_o),
        .id_offset(id_offset_o),
        .id_next_inst_invalid(id_next_inst_invalid_o),

        .ex_aluop(ex_aluop_i),
        .ex_alusel(ex_alusel_i),
        .ex_reg1(ex_reg1_i),
        .ex_reg2(ex_reg2_i),
        .ex_wd(ex_wd_i),
        .ex_wreg(ex_wreg_i),
        .ex_link_addr(ex_link_addr_i),
        .ex_offset(ex_offset_i),

        .id_inst_invalid(id_inst_invalid_i)
    );
    
    ex ex0(
        .rst(rst),

        .aluop_i(ex_aluop_i),
        .alusel_i(ex_alusel_i),
        .reg1_i(ex_reg1_i),
        .reg2_i(ex_reg2_i),
        .wd_i(ex_wd_i),
        .wreg_i(ex_wreg_i),
        .link_addr_i(ex_link_addr_i),
        .offset_i(ex_offset_i),

        .wd_o(ex_wd_o),
        .wreg_o(ex_wreg_o),
        .wdata_o(ex_wdata_o),
        .aluop_o(ex_aluop_o),
        .mem_addr_o(ex_mem_addr_o),
        .reg2_o(ex_reg2_o)
    );


    wire mem_wreg_i;
    wire[`RegAddrBus] mem_wd_i;
    wire[`RegBus] mem_wdata_i;
    wire[`AluOpBus] mem_aluop_i;
    wire[`RegBus] mem_mem_addr_i;
    wire[`RegBus] mem_reg2_i;

    ex_mem ex_mem0(
        .clk(clk),
        .rst(rst),

        .stall(stall),

        .ex_wd(ex_wd_o),
        .ex_wreg(ex_wreg_o),
        .ex_wdata(ex_wdata_o),
        .ex_aluop(ex_aluop_o),
        .ex_mem_addr(ex_mem_addr_o),
        .ex_reg2(ex_reg2_o),

        .mem_wd(mem_wd_i),
        .mem_wreg(mem_wreg_i),
        .mem_wdata(mem_wdata_i),
        .mem_aluop(mem_aluop_i),
        .mem_mem_addr(mem_mem_addr_i),
        .mem_reg2(mem_reg2_i)
    );

    mem mem0(
        .rst(rst),

        .wd_i(mem_wd_i),
        .wreg_i(mem_wreg_i),
        .wdata_i(mem_wdata_i),
        .aluop_i(mem_aluop_i),
        .mem_addr_i(mem_mem_addr_i),
        .reg2_i(mem_reg2_i),

        .mem_data_i(ram_data_i),

        .wd_o(mem_wd_o),
        .wreg_o(mem_wreg_o),
        .wdata_o(mem_wdata_o),

        .mem_addr_o(ram_addr_o),
        .mem_we_o(ram_we_o),
        .mem_sel_o(ram_sel_o),
        .mem_data_o(ram_data_o),
        .mem_ce_o(ram_ce_o)
    );

    mem_wb mem_wb0(
        .clk(clk),
        .rst(rst),

        .stall(stall),

        .mem_wd(mem_wd_o),
        .mem_wreg(mem_wreg_o),
        .mem_wdata(mem_wdata_o),

        .wb_wd(wb_wd_i),
        .wb_wreg(wb_wreg_i),
        .wb_wdata(wb_wdata_i)
    );

endmodule
module cpu_riscv(

    input wire                     clk,
    input wire                     rst,


    input wire[127:0]              rom_data_i,
    input wire                     rom_done_i,
    output wire[`RegBus]           rom_addr_o,
    output wire                    rom_read_o,


    input wire[`RegBus]            ram_data_i,
    output wire[`RegBus]           ram_addr_o,
    output wire[`RegBus]           ram_data_o,
    output wire                    ram_we_o,
    output wire[3:0]               ram_sel_o,
    output wire                    ram_ce_o
);



    wire id_branch_flag_o;
    wire [`RegBus] id_branch_target_addr_o;


    wire[5:0] stall;
    wire stallreq_from_ic;
    wire stallreq_from_id;

    ctrl ctrl0(
        .rst(rst),
        .stallreq_from_id(stallreq_from_id),
        .stallreq_from_ic(stallreq_from_ic),
        .stall(stall)
    );


    wire[`InstAddrBus] pc;

    pc_reg pc_reg0(
        .clk(clk),
        .rst(rst),
        .stall(stall),
        .branch_flag_i(id_branch_flag_o),
        .branch_target_addr_i(id_branch_target_addr_o),
        .pc(pc)
    );


    wire[`InstBus] inst;

    i_cache i_cache0(
        .clk(clk),
        .rst(rst),

        .core_addr_i(pc),
        .core_data_o(inst),
        .core_stallreq_o(stallreq_from_ic),

        .mem_data_i(rom_data_i),
        .mem_done_i(rom_done_i),
        .mem_read_o(rom_read_o),
        .mem_addr_o(rom_addr_o)
    );


    wire[`InstAddrBus] id_pc_i;
    wire[`InstBus] id_inst_i;

    if_id if_id0(
        .clk(clk),
        .rst(rst),
        .stall(stall),
        .if_pc(pc),
        .if_inst(inst),
        .id_pc(id_pc_i),
        .id_inst(id_inst_i)
    );


    wire[`AluOpBus] id_aluop_o;
    wire[`AluSelBus] id_alusel_o;
    wire[`RegBus] id_reg1_o;
    wire[`RegBus] id_reg2_o;
    wire id_wreg_o;
    wire[`RegAddrBus] id_wd_o;
    wire[`RegBus] id_link_addr_o;
    wire[`RegBus] id_offset_o;
    wire id_next_inst_invalid_o;
    wire id_inst_invalid_i;

    wire reg1_read;
    wire reg2_read;
    wire[`RegBus] reg1_data;
    wire[`RegBus] reg2_data;
    wire[`RegAddrBus] reg1_addr;
    wire[`RegAddrBus] reg2_addr;

    wire ex_wreg_o;
    wire[`RegAddrBus] ex_wd_o;
    wire[`RegBus] ex_wdata_o;
    wire[`AluOpBus] ex_aluop_o;
    wire[`RegBus] ex_mem_addr_o;
    wire[`RegBus] ex_reg2_o;

    wire mem_wreg_o;
    wire[`RegAddrBus] mem_wd_o;
    wire[`RegBus] mem_wdata_o;

    wire wb_wreg_i;
    wire[`RegAddrBus] wb_wd_i;
    wire[`RegBus] wb_wdata_i;

    id id0(
        .rst(rst),

        .pc_i(id_pc_i),
        .inst_i(id_inst_i),

        .ex_wreg_i(ex_wreg_o),
        .ex_wdata_i(ex_wdata_o),
        .ex_wd_i(ex_wd_o),

        .mem_wreg_i(mem_wreg_o),
        .mem_wdata_i(mem_wdata_o),
        .mem_wd_i(mem_wd_o),

        .ex_aluop_i(ex_aluop_o),

        .reg1_data_i(reg1_data),
        .reg2_data_i(reg2_data),

        .inst_invalid_i(id_inst_invalid_i),

        .reg1_read_o(reg1_read),
        .reg2_read_o(reg2_read),
        .reg1_addr_o(reg1_addr),
        .reg2_addr_o(reg2_addr),

        .aluop_o(id_aluop_o),
        .alusel_o(id_alusel_o),
        .reg1_o(id_reg1_o),
        .reg2_o(id_reg2_o),
        .wd_o(id_wd_o),
        .wreg_o(id_wreg_o),
        .offset_o(id_offset_o),
        .next_inst_invalid_o(id_next_inst_invalid_o),

        .branch_flag_o(id_branch_flag_o),
        .branch_target_addr_o(id_branch_target_addr_o),
        .link_addr_o(id_link_addr_o),

        .stallreq(stallreq_from_id)
    );

    regfile regfile0(
        .clk(clk),
        .rst(rst),
        .we(wb_wreg_i),
        .waddr(wb_wd_i),
        .wdata(wb_wdata_i),
        .re1(reg1_read),
        .raddr1(reg1_addr),
        .rdata1(reg1_data),
        .re2(reg2_read),
        .raddr2(reg2_addr),
        .rdata2(reg2_data)
    );


    wire[`AluOpBus] ex_aluop_i;
    wire[`AluSelBus] ex_alusel_i;
    wire[`RegBus] ex_reg1_i;
    wire[`RegBus] ex_reg2_i;
    wire ex_wreg_i;
    wire[`RegAddrBus] ex_wd_i;
    wire[`RegBus] ex_link_addr_i;
    wire[`RegBus] ex_offset_i;

    id_ex id_ex0(
        .clk(clk),
        .rst(rst),
        .stall(stall),

        .id_aluop(id_aluop_o),
        .id_alusel(id_alusel_o),
        .id_reg1(id_reg1_o),
        .id_reg2(id_reg2_o),
        .id_wd(id_wd_o),
        .id_wreg(id_wreg_o),
        .id_link_addr(id_link_addr_o),
        .id_offset(id_offset_o),
        .id_next_inst_invalid(id_next_inst_invalid_o),

        .ex_aluop(ex_aluop_i),
        .ex_alusel(ex_alusel_i),
        .ex_reg1(ex_reg1_i),
        .ex_reg2(ex_reg2_i),
        .ex_wd(ex_wd_i),
        .ex_wreg(ex_wreg_i),
        .ex_link_addr(ex_link_addr_i),
        .ex_offset(ex_offset_i),

        .id_inst_invalid(id_inst_invalid_i)
    );
    
    ex ex0(
        .rst(rst),

        .aluop_i(ex_aluop_i),
        .alusel_i(ex_alusel_i),
        .reg1_i(ex_reg1_i),
        .reg2_i(ex_reg2_i),
        .wd_i(ex_wd_i),
        .wreg_i(ex_wreg_i),
        .link_addr_i(ex_link_addr_i),
        .offset_i(ex_offset_i),

        .wd_o(ex_wd_o),
        .wreg_o(ex_wreg_o),
        .wdata_o(ex_wdata_o),
        .aluop_o(ex_aluop_o),
        .mem_addr_o(ex_mem_addr_o),
        .reg2_o(ex_reg2_o)
    );


    wire mem_wreg_i;
    wire[`RegAddrBus] mem_wd_i;
    wire[`RegBus] mem_wdata_i;
    wire[`AluOpBus] mem_aluop_i;
    wire[`RegBus] mem_mem_addr_i;
    wire[`RegBus] mem_reg2_i;

    ex_mem ex_mem0(
        .clk(clk),
        .rst(rst),

        .stall(stall),

        .ex_wd(ex_wd_o),
        .ex_wreg(ex_wreg_o),
        .ex_wdata(ex_wdata_o),
        .ex_aluop(ex_aluop_o),
        .ex_mem_addr(ex_mem_addr_o),
        .ex_reg2(ex_reg2_o),

        .mem_wd(mem_wd_i),
        .mem_wreg(mem_wreg_i),
        .mem_wdata(mem_wdata_i),
        .mem_aluop(mem_aluop_i),
        .mem_mem_addr(mem_mem_addr_i),
        .mem_reg2(mem_reg2_i)
    );

    mem mem0(
        .rst(rst),

        .wd_i(mem_wd_i),
        .wreg_i(mem_wreg_i),
        .wdata_i(mem_wdata_i),
        .aluop_i(mem_aluop_i),
        .mem_addr_i(mem_mem_addr_i),
        .reg2_i(mem_reg2_i),

        .mem_data_i(ram_data_i),

        .wd_o(mem_wd_o),
        .wreg_o(mem_wreg_o),
        .wdata_o(mem_wdata_o),

        .mem_addr_o(ram_addr_o),
        .mem_we_o(ram_we_o),
        .mem_sel_o(ram_sel_o),
        .mem_data_o(ram_data_o),
        .mem_ce_o(ram_ce_o)
    );

    mem_wb mem_wb0(
        .clk(clk),
        .rst(rst),

        .stall(stall),

        .mem_wd(mem_wd_o),
        .mem_wreg(mem_wreg_o),
        .mem_wdata(mem_wdata_o),

        .wb_wd(wb_wd_i),
        .wb_wreg(wb_wreg_i),
        .wb_wdata(wb_wdata_i)
    );

endmodule