data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n     forever #5 clk_source = !clk_source;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n     forever #5 clk = !clk;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n     #5\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n     #5\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n     #30000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n     #1000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n     #50000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n     #50000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n     #50000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n     #50000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n     #50000\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n     #1000 \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n     #1000 \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n     #1000 \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n      #1000 $stop;\n      ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:27: Cannot find file containing module: \'wave_gen\'\n wave_gen tb(clk,reset_n,avs_s0_chipselect,avs_s0_write,avs_s0_read,avs_s0_writedata,avs_s0_readdata,avs_s0_address,clk_source,dac);\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl,data/full_repos/permissive/117851934/wave_gen\n             data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl,data/full_repos/permissive/117851934/wave_gen.v\n             data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl,data/full_repos/permissive/117851934/wave_gen.sv\n             wave_gen\n             wave_gen.v\n             wave_gen.sv\n             obj_dir/wave_gen\n             obj_dir/wave_gen.v\n             obj_dir/wave_gen.sv\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:68: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'14\'h3fff\' generates 14 bits.\n                                                                                                   : ... In instance wave_gen_tb\n     avalon_write(3\'h0,14\'h3fff);\n     ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:69: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'14\'h0\' generates 14 bits.\n                                                                                                   : ... In instance wave_gen_tb\n     avalon_write(3\'h1,14\'h0); \n     ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:71: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'16\'h100\' generates 16 bits.\n                                                                                                   : ... In instance wave_gen_tb\n     avalon_write(3\'h3,16\'d256); \n     ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:72: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'8\'h1\' generates 8 bits.\n                                                                                                   : ... In instance wave_gen_tb\n     avalon_write(3\'h4,8\'h1); \n     ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:74: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                                   : ... In instance wave_gen_tb\n      avalon_write(3\'h4,8\'h0);\n      ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:76: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'8\'h3\' generates 8 bits.\n                                                                                                   : ... In instance wave_gen_tb\n      avalon_write(3\'h4,8\'h3);\n      ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:78: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'8\'h5\' generates 8 bits.\n                                                                                                   : ... In instance wave_gen_tb\n      avalon_write(3\'h4,8\'h5);\n      ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:80: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'14\'h1fff\' generates 14 bits.\n                                                                                                   : ... In instance wave_gen_tb\n      avalon_write(3\'h0,14\'h1fff);\n      ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:82: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'14\'h1000\' generates 14 bits.\n                                                                                                   : ... In instance wave_gen_tb\n      avalon_write(3\'h1,14\'h1000);\n      ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:86: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'8\'h7\' generates 8 bits.\n                                                                                                   : ... In instance wave_gen_tb\n      avalon_write(3\'h4,8\'h7);\n      ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:87: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'14\'h3fff\' generates 14 bits.\n                                                                                                   : ... In instance wave_gen_tb\n      avalon_write(3\'h5,14\'h3fff);\n      ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:89: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'14\'h2fff\' generates 14 bits.\n                                                                                                   : ... In instance wave_gen_tb\n      avalon_write(3\'h5,14\'h2fff); \n      ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:91: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'14\'h1fff\' generates 14 bits.\n                                                                                                   : ... In instance wave_gen_tb\n      avalon_write(3\'h5,14\'h1fff);\n      ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/wave_gen_tb.v:93: Operator TASKREF \'avalon_write\' expects 32 bits on the Function Argument, but Function Argument\'s CONST \'14\'h0\' generates 14 bits.\n                                                                                                   : ... In instance wave_gen_tb\n      avalon_write(3\'h5,14\'h0);            \n      ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s), 31 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module wave_gen_tb;

 	reg clk,reset_n,avs_s0_chipselect,avs_s0_read,avs_s0_write;
 	reg [31:0] avs_s0_writedata;
 	wire [31:0] avs_s0_readdata;
 	reg [2:0] avs_s0_address;
 	reg clk_source;
 	wire [13:0] dac;			
 			
 wave_gen tb(clk,reset_n,avs_s0_chipselect,avs_s0_write,avs_s0_read,avs_s0_writedata,avs_s0_readdata,avs_s0_address,clk_source,dac);
 
  defparam tb.AmpMax=14'h3fff;
	defparam tb.AmpMin=14'h0;
	defparam tb.FreqDiv=32'd20;
	defparam tb.SamplePonint=16'd256;
	

 initial                         
   begin
     clk_source = 0;
     forever #`delay clk_source = !clk_source;
   end
 initial                         
   begin
     clk=0;
     forever #`delay clk = !clk;
   end
task  avalon_write;
  input [2:0] addr;
  input [31:0] data;
  begin
  #`delay;
	avs_s0_address=addr;
	avs_s0_writedata=data;
	avs_s0_chipselect=1;
	avs_s0_write=1;
	#`delay;
	avs_s0_chipselect=0;
	avs_s0_write=0;
	end
endtask
   
 initial                         
   begin
     reset_n = 1;
     #`delay
     reset_n = 0;
     #`delay
     reset_n = 1;
     
     avalon_write(`ADDR_AMP_MAX,14'h3fff);
     avalon_write(`ADDR_AMP_MIN,14'h0); 
     avalon_write(`ADDR_FREQ_DIV,32'd3); 
     avalon_write(`ADDR_POINT,16'd256); 
     avalon_write(`ADDR_CONTROL,8'h1); 
     #30000
      avalon_write(`ADDR_CONTROL,8'h0);
     #1000
      avalon_write(`ADDR_CONTROL,8'h3);
     #50000
      avalon_write(`ADDR_CONTROL,8'h5);
     #50000
      avalon_write(`ADDR_AMP_MAX,14'h1fff);
     #50000
      avalon_write(`ADDR_AMP_MIN,14'h1000);
     #50000
      avalon_write(`ADDR_FREQ_DIV,32'h5);
     #50000
      avalon_write(`ADDR_CONTROL,8'h7);
      avalon_write(`ADDR_DAC,14'h3fff);
     #1000 
      avalon_write(`ADDR_DAC,14'h2fff); 
     #1000 
      avalon_write(`ADDR_DAC,14'h1fff);
     #1000 
      avalon_write(`ADDR_DAC,14'h0);            
      #1000 $stop;
     
   end

 endmodule
module wave_gen_tb;


 	reg clk,reset_n,avs_s0_chipselect,avs_s0_read,avs_s0_write;
 	reg [31:0] avs_s0_writedata;
 	wire [31:0] avs_s0_readdata;
 	reg [2:0] avs_s0_address;
 	reg clk_source;
 	wire [13:0] dac;			
 			
 wave_gen tb(clk,reset_n,avs_s0_chipselect,avs_s0_write,avs_s0_read,avs_s0_writedata,avs_s0_readdata,avs_s0_address,clk_source,dac);
 
  defparam tb.AmpMax=14'h3fff;
	defparam tb.AmpMin=14'h0;
	defparam tb.FreqDiv=32'd20;
	defparam tb.SamplePonint=16'd256;
	

 initial                         
   begin
     clk_source = 0;
     forever #`delay clk_source = !clk_source;
   end
 initial                         
   begin
     clk=0;
     forever #`delay clk = !clk;
   end
task  avalon_write;
  input [2:0] addr;
  input [31:0] data;
  begin
  #`delay;
	avs_s0_address=addr;
	avs_s0_writedata=data;
	avs_s0_chipselect=1;
	avs_s0_write=1;
	#`delay;
	avs_s0_chipselect=0;
	avs_s0_write=0;
	end
endtask
   
 initial                         
   begin
     reset_n = 1;
     #`delay
     reset_n = 0;
     #`delay
     reset_n = 1;
     
     avalon_write(`ADDR_AMP_MAX,14'h3fff);
     avalon_write(`ADDR_AMP_MIN,14'h0); 
     avalon_write(`ADDR_FREQ_DIV,32'd3); 
     avalon_write(`ADDR_POINT,16'd256); 
     avalon_write(`ADDR_CONTROL,8'h1); 
     #30000
      avalon_write(`ADDR_CONTROL,8'h0);
     #1000
      avalon_write(`ADDR_CONTROL,8'h3);
     #50000
      avalon_write(`ADDR_CONTROL,8'h5);
     #50000
      avalon_write(`ADDR_AMP_MAX,14'h1fff);
     #50000
      avalon_write(`ADDR_AMP_MIN,14'h1000);
     #50000
      avalon_write(`ADDR_FREQ_DIV,32'h5);
     #50000
      avalon_write(`ADDR_CONTROL,8'h7);
      avalon_write(`ADDR_DAC,14'h3fff);
     #1000 
      avalon_write(`ADDR_DAC,14'h2fff); 
     #1000 
      avalon_write(`ADDR_DAC,14'h1fff);
     #1000 
      avalon_write(`ADDR_DAC,14'h0);            
      #1000 $stop;
     
   end

 endmodule