data/full_repos/permissive/20101677/mux2to1_32.v
data/verilator_xmls/da90cfa4-a904-40d9-bca2-be2f9810539c.xml
module mux2to1_32(
	input wire sel,
	input wire [31:0] a,
	input wire [31:0] b,
	output wire [31:0] o
);

assign o = sel ? a : b;

endmodule
module mux2to1_32(
	input wire sel,
	input wire [31:0] a,
	input wire [31:0] b,
	output wire [31:0] o
);


assign o = sel ? a : b;

endmodule