data/full_repos/permissive/143278/ivltests/case3.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module switch (q,a,b,c,d,sel);
input a,b,c,d;
input [1:0] sel;
output q;
reg q;
always @ *
     case (sel)
         2'b00: q = a;
	 2'b01: q = b;
	 2'b10: q = c;
	 2'b11: q = d;
     endcase

endmodule
module switch (q,a,b,c,d,sel);

input a,b,c,d;
input [1:0] sel;
output q;
reg q;
always @ *
     case (sel)
         2'b00: q = a;
	 2'b01: q = b;
	 2'b10: q = c;
	 2'b11: q = d;
     endcase

endmodule