data/full_repos/permissive/113654920/hdl/IDE_DMA.v
data/verilator_xmls/24876274-6682-4532-96a6-769826a2d186.xml
module IDE_DMA(

	input CLK4		,
	input Phase3	,

	output reg iDK	,
	input iDQ		,
	input SiRdy1	,
	input SiRdy2	,

	input DMA_ARM  ,
	input PS2WrIDE	 ,
	input [2:0] UDMA ,
	input [2:0] MDMA,
	output iDMARd		,
	output iDMAWr	 ,
	output reg iDMA_OE	 ,
	output reg iD_245_In  ,
	output reg CRC_MUX	 ,
	output reg CRC_ARM	 ,
	output reg CRC_ENB	 ,

	input A0	,
	input PA_Full		,
	input PA_HvSpace	 ,
	input PA_OD_Rdy	 ,
	input WithinABlock	 ,
	input PA_AlmostFull  ,
	input PA_Empty		,
	output IDE_DSTB,
	output reg HWOE,
	output reg RegEA,
	output reg IncAddrA , 
	output reg EnbA ,
	output reg WrA 
);










reg HDMARDY,HSTROBE,STOP;
reg ND_Rd,ND_Wr;

wire NBrkOut;
reg	iWait;
wire UDMAC,MDMAC;
reg	ND_ARM;
reg	UHO_ARM;
reg	UDI_ARM;
reg	ILatch;

wire	Proceed;
wire XiRdy1;

parameter iIdle1	= 6'b00_0000;
parameter iIdle2	= 6'b00_0001;
parameter ND_2 	= 6'b00_0010;
parameter ND_3 	= 6'b00_0011;
parameter ND_4 	= 6'b00_0100;
parameter ND_5 	= 6'b00_0101;
parameter ND_6 	= 6'b00_0110;
parameter ND_7 	= 6'b00_0111;
parameter ND_8 	= 6'b00_1000;
parameter ND_9 	= 6'b00_1001;
parameter ND_A 	= 6'b00_1010;
parameter ND_B 	= 6'b00_1011;
parameter ND_C 	= 6'b00_1100;
parameter Udi1 	= 6'b01_0000;
parameter Udi2 	= 6'b01_0001;
parameter Udi3 	= 6'b01_0010;

parameter Udi10	= 6'b01_0100;
parameter Udi11	= 6'b01_0101;
parameter Udix1 	= 6'b10_0001;
parameter Udix2 	= 6'b10_0010;
parameter Udix3 	= 6'b10_0011;
parameter Udix4 	= 6'b10_0100;
parameter Udix5 	= 6'b10_0101;
parameter Udix6 	= 6'b10_0110;
parameter Uho_G 	= 6'b10_0111;
parameter Uhx_0 	= 6'b10_1000;
parameter Uhx_1 	= 6'b10_1001;
parameter Uhx_2 	= 6'b10_1010;
parameter Uhx_3 	= 6'b10_1011;
parameter Uhx_4 	= 6'b10_1100;
parameter Uhx_5 	= 6'b10_1101;
parameter Uhx_6 	= 6'b10_1110;

parameter Uho_0	= 6'b11_0000;
parameter Uho_1	= 6'b11_0001;
parameter Uho_2	= 6'b11_0010;
parameter Uho_3	= 6'b11_0011;
parameter Uho_4	= 6'b11_0100;
parameter Uho_5	= 6'b11_0101;
parameter Uho_6	= 6'b11_0110;
parameter Uho_7	= 6'b11_0111;
parameter Uho_8	= 6'b11_1000;
parameter Uho_9	= 6'b11_1001;
parameter Uho_A	= 6'b11_1010;
parameter Uho_B	= 6'b11_1011;
parameter Uho_C	= 6'b11_1100;
parameter Uho_D	= 6'b11_1101;
parameter Uho_E	= 6'b11_1110;
parameter Uho_F	= 6'b11_1111;


reg [5:0] iSTATE;
reg [4:0] iCount;
reg PipeEmpty;
reg IDE_DSTB1;










assign iDMAWr  =	(ND_ARM & ND_Wr) | ((UDI_ARM | UHO_ARM) & ~(STOP));
assign iDMARd  =	(ND_ARM & ND_Rd) |
						(UDI_ARM & HDMARDY) |
						(UHO_ARM & ~HSTROBE);






assign 	NBrkOut	= ~iDQ | (PS2WrIDE & PA_Empty) | (~PS2WrIDE & PA_Full);



assign	UDMAC	= (UDMA[2] | UDMA[1] | UDMA[0]) & ~(MDMAC);
assign	MDMAC	= MDMA[2] | MDMA[1] | MDMA[0];
assign	Proceed = PA_OD_Rdy | WithinABlock;
assign	XiRdy1	= SiRdy1 ^ SiRdy2;
assign	IDE_DSTB = (XiRdy1 & UDI_ARM) | ((UHO_ARM | ND_ARM) & ILatch );

always @(posedge CLK4) begin
	IDE_DSTB1	<= IDE_DSTB;
	CRC_ENB		<= IDE_DSTB1 & ~IDE_DSTB;
end

always @(posedge CLK4)begin



if (DMA_ARM == 1'b0) begin

	UDI_ARM	<= 1'b0;
	UHO_ARM	<= 1'b0;
	STOP		<= 1'b1;
	HDMARDY	<= 1'b0;
	iWait		<= 1'b0;
	HSTROBE	<= 1'b1;

	ND_ARM	<= 1'b0;
	ND_Rd		<= 1'b0;
	ND_Wr		<= 1'b0;
	ILatch	<= 1'b0;

	iDK		<= 1'b0;
	iDMA_OE	<= 1'b0;
	iD_245_In	<= 1'b0;
	CRC_ARM	<= 1'b0;
	CRC_MUX	<= 1'b0;


	RegEA		<= 1'b0;
	IncAddrA	<= 1'b0;
	EnbA		<= 1'b0;
	WrA		<= 1'b0;
	iCount	<= 5'b0000;
	HWOE		<= 1'b0;
	PipeEmpty	<= 1'b1;
	iSTATE	<= iIdle1;

end else begin

if (UHO_ARM == 1'b1) begin
	if (SiRdy2 == 1'b1) begin
		iWait		<= 1'b1;
		iCount	<= 5'd00;
	end else begin
		iCount	<= iCount + 1;
		if (iCount[4] == 1'b1) begin
			iWait	<= 1'b0;
		end
	end
end

case (iSTATE)
iIdle1: begin

	UDI_ARM	<= 1'b0;
	STOP		<= 1'b1;
	HDMARDY	<= 1'b0;

	UHO_ARM	<= 1'b0;
	HSTROBE	<= 1'b1;

	ND_ARM	<= 1'b0;
	ND_Rd		<= 1'b0;
	ND_Wr		<= 1'b0;
	ILatch	<= 1'b0;

	iDK		<= 1'b0;
	iDMA_OE	<= 1'b0;
	iD_245_In	<= 1'b0;
	CRC_ARM	<= 1'b0;
	CRC_MUX	<= 1'b0;

	RegEA		<= 1'b0;
	IncAddrA	<= 1'b0;
	EnbA		<= 1'b0;
	WrA		<= 1'b0;
	iCount	<= 5'b0000;

	iSTATE	<= iIdle2;
end

iIdle2: begin
	iCount	<= 5'd00;
	if (iDQ == 1'b1) begin
		if (UDMAC == 1'b1) begin
			if (PS2WrIDE == 1'b1) begin
				if (Proceed == 1'b1) begin
					iSTATE <= Uho_0;
				end
			end else begin
				if (PA_HvSpace == 1'b1) begin
					iSTATE	<= Udi1;
				end
			end
		end else begin
			if (PS2WrIDE == 1'b1) begin
				if (Proceed == 1'b1) begin
					iSTATE <= ND_2;
				end
			end else begin
				if (PA_HvSpace == 1'b1) begin
					iSTATE <= ND_2;
				end
			end
		end
	end else begin
		iSTATE <= iIdle2;
	end
end






ND_2: begin
	iSTATE		<= ND_3;
	iDK			<= iDQ;
	ND_ARM		<= 1'b1;
	iD_245_In	<= ~PS2WrIDE;
end

ND_3: begin
	iDK		<= iDQ;
	if (NBrkOut == 1'b0) begin
		EnbA		<= PS2WrIDE;
		iSTATE	<= ND_4;
	end else begin
		iD_245_In	<= 1'b0;
		ND_ARM		<= 1'b0;
		iSTATE		<= iIdle1;
	end
end

ND_4: begin
	iSTATE	<= ND_5;
	EnbA		<= 1'b0;
	RegEA		<= PS2WrIDE;
end

ND_5: begin
	iSTATE	<= ND_6;
	RegEA		<=	1'b0;
	iCount	<= 5'd00;
	iDMA_OE	<= PS2WrIDE;
end

ND_6: begin
	iSTATE	<= ND_7;
	ND_Rd		<= ~PS2WrIDE;
	ND_Wr		<=  PS2WrIDE;
end

ND_7:	begin
	iCount	<= iCount + 1;
	if (((iCount == 5'd05) && (MDMA[2] == 1'b1)) ||
		 ((iCount == 5'd07) && (MDMA[1] == 1'b1)) ||
		  (iCount == 5'd31) ) begin
		iSTATE	<= ND_8;
	end
end

ND_8: begin
	ILatch	<= ~PS2WrIDE;
	iSTATE	<= ND_9;
end
ND_9: begin

		iSTATE	<= ND_A;

end

ND_A: begin
	WrA		<= ~PS2WrIDE;
	EnbA		<= ~PS2WrIDE;
	iCount	<= 5'd00;
	iSTATE	<= ND_B;
end
ND_B: begin
	WrA		<=	1'b0;
	EnbA		<= 1'b0;
	ND_Rd		<=	1'b0;
	ND_Wr		<= 1'b0;
	ILatch	<= 1'b0;
	IncAddrA	<= 1'b1;
	iSTATE	<= ND_C;
end

ND_C: begin
	iDMA_OE	<= 1'b0;
	IncAddrA	<= 1'b0;
	HWOE		<= A0;
	iCount	<= iCount + 1;
	if (((iCount == 5'd03) && (MDMA[2] == 1'b1)) ||
		 ((iCount == 5'd05) && (MDMA[1] == 1'b1)) ||
		  (iCount == 5'd31) ) begin
		iSTATE	<= ND_3;
	end
end



Udi1:	begin
	UDI_ARM		<= 1'b1;
	iDK			<= 1'b0;
	iDMA_OE		<= 1'b0;
	STOP			<= 1'b1;
	HDMARDY		<= 1'b0;
	if (Phase3 == 1'b1) begin
		iSTATE	<= Udi2;
	end
end
Udi2:	begin
	if (iDQ == 1'b1) begin
		if ((Phase3 == 1'b1) && (SiRdy2 == 1'b1)) begin
			iSTATE	<= Udi3;
		end
	end else begin
		iSTATE	<= iIdle1;
	end
end
Udi3:	begin
	iDK			<= 1'b1;
	iD_245_In	<= 1'b1;
	CRC_ARM		<=	1'b1;
	if (Phase3 == 1'b1) begin
		iSTATE	<= Udi10;
	end
end



Udi10:	begin
	IncAddrA	<= 1'b0;
	if (XiRdy1 == 1'b1) begin
		EnbA		<= 1'b1;
		WrA		<= 1'b1;

		iSTATE	<= Udi11;
	end else begin
		if (iDQ	== 1'b1) begin
			HDMARDY	<= ~PA_AlmostFull;
			STOP		<= 1'b0;
			iSTATE	<= Udi10;
		end else begin
			HDMARDY	<= 1'b0;
			STOP		<= 1'b1;
			iSTATE	<= Udix1;
		end
	end
end
Udi11:	begin
	iSTATE	<= Udi10;
	EnbA		<= 1'b0;
	WrA		<= 1'b0;

	IncAddrA	<=	1'b1;
end

Udix1:	begin
	if ((Phase3 == 1'b1) && (SiRdy2 == 1'b1)) begin
		iSTATE 	<= Udix2;
	end
end
Udix2:	begin
	CRC_MUX		<= 1'b1;
	iD_245_In	<= 1'b0;
	if (Phase3 == 1'b1) begin
		iSTATE 	<= Udix3;
	end
end
Udix3:	begin
	iDMA_OE		<= 1'b1;
	if (Phase3 == 1'b1) begin
		iSTATE <= Udix4;
	end
end
Udix4:	begin
	if (Phase3 == 1'b1) begin
		iSTATE <= Udix5;
	end
end
Udix5:	begin
	iDK		<= 1'b0;
	if (Phase3 == 1'b1) begin
		iSTATE <= Udix6;
	end
end
Udix6:	begin
	if (Phase3 == 1'b1) begin
		iSTATE <= iIdle1;
	end
end







Uho_0: begin
	UHO_ARM		<= 1'b1;
	iDK			<= 1'b1;
	STOP			<= 1'b1;
	HSTROBE		<= 1'b1;
	EnbA			<=	PipeEmpty;
	iSTATE		<= Uho_1;
end

Uho_1: begin
	iDK			<= 1'b1;
	EnbA			<= 1'b0;
	RegEA			<= PipeEmpty;
	iD_245_In	<= 1'b0;
	iSTATE		<= Uho_2;
end

Uho_2: begin
	RegEA			<= 1'b0;
	HWOE			<= ~PipeEmpty ^ A0;
	iSTATE		<= Uho_3;
end

Uho_3: begin
	STOP			<= 1'b0;
	if ((SiRdy2 == 1'b0) && (Phase3 == 1'b1)) begin
		iSTATE	<= Uho_4;
		iDMA_OE	<= 1'b1;
	end
end

Uho_4: begin
	if ((SiRdy2 == 1'b0) && (Phase3 == 1'b1)) begin
		IncAddrA	<=	PipeEmpty;
		iSTATE	<= Uho_5;
	end
end

Uho_5: begin
	IncAddrA	<= 1'b0;
	if ((SiRdy2 == 1'b0) && (Phase3 == 1'b1)) begin
		EnbA		<=	1'b1;
		iSTATE	<= Uho_6;
	end
end

Uho_6:	begin
	iSTATE	<= Uho_7;
	EnbA		<= 1'b0;
	iWait		<= 1'b0;
	HSTROBE	<= 1'b0;
	CRC_ARM	<= 1'b1;
end

Uho_7:	begin

	ILatch	<= 1'b1;

	if (PA_Empty == 1'b1) begin
		iSTATE	<= Uho_F;
	end else begin
		RegEA		<= UDMA[2];
		iSTATE	<= Uho_8;
	end
end

Uho_8:	begin

	RegEA		<= UDMA[1];
	ILatch	<= 1'b0;
	HWOE		<= (UDMA[2] == 1'b1) ? A0 : HWOE;

	if (UDMA[2] == 1'b1) begin
		IncAddrA	<=	1'b1;
		iSTATE	<= Uho_D;
	end else begin
		iSTATE	<= Uho_9;
	end
end

Uho_9: begin

	RegEA		<= 1'b0;
	HWOE		<= (UDMA[1] == 1'b1) ? A0 : HWOE;

	if (UDMA[1] == 1'b1) begin
		iSTATE	<= Uho_C;
	end else begin
		iSTATE	<= Uho_A;
	end
end

Uho_A: begin
	RegEA		<= UDMA[0];
	iSTATE	<= Uho_B;
end

Uho_B: begin

	RegEA		<= 1'b0;
	HWOE		<= (UDMA[0] == 1'b1) ? A0 : HWOE;
	iSTATE	<= Uho_C;
end
Uho_C:	begin
	iSTATE	<= Uho_D;
	IncAddrA	<=	1'b1;
end
Uho_D:	begin
	iSTATE	<= Uho_E;
	IncAddrA	<= 1'b0;
	EnbA		<=	1'b1;
end
Uho_E: begin
	EnbA		<= 1'b0;
	if (iDQ	== 1'b0) begin
		iSTATE	<= Uhx_0;
	end else begin
		if (iWait == 1'b0) begin

			HSTROBE	<= ~HSTROBE;
			iSTATE	<= Uho_7;
		end else begin
			iSTATE	<= Uho_E;
		end
	end
end


Uho_F:	begin
	PipeEmpty	<= 1'b1;
	ILatch	<= 1'b0;
	if (Phase3 == 1'b1) begin
		iSTATE		<= Uho_G;
	end
end
Uho_G:	begin
	STOP			<= 1'b1;
	if (Phase3 == 1'b1) begin
		if ((SiRdy2 == 1'b1) && (iDQ == 1'b0)) begin
			iSTATE <= Uhx_3;
		end else begin
			if (PA_OD_Rdy == 1'b1) begin
				EnbA		<=	PipeEmpty;
				iSTATE 	<= Uho_1;
			end
		end
	end
end

Uhx_0:	begin
	PipeEmpty	<= 1'b0;
	if (Phase3 == 1'b1) begin
		iSTATE		<= Uhx_1;
	end
end
Uhx_1:	begin
	if (Phase3 == 1'b1) begin
		iSTATE 	<= Uhx_2;
	end
end
Uhx_2:	begin
	STOP			<= 1'b1;
	if ((Phase3 == 1'b1) && (SiRdy2 == 1'b1) && (iDQ == 1'b0)) begin
		iSTATE <= Uhx_3;
	end
end
Uhx_3:	begin
	HSTROBE		<= 1'b1;
	CRC_MUX		<= 1'b1;
	if (Phase3 == 1'b1) begin
		iSTATE <= Uhx_4;
	end
end
Uhx_4:	begin
	if (Phase3 == 1'b1) begin
		iSTATE <= Uhx_5;
	end
end
Uhx_5:	begin
	iDK		<= 1'b0;
	if (Phase3 == 1'b1) begin
		iSTATE <= Uhx_6;
	end
end
Uhx_6:	begin
	if (Phase3 == 1'b1) begin
		iSTATE <= iIdle1;
	end
end

default: begin
	iSTATE <= iIdle1;
end
endcase
end
end

endmodule
module IDE_DMA(

	input CLK4		,
	input Phase3	,

	output reg iDK	,
	input iDQ		,
	input SiRdy1	,
	input SiRdy2	,

	input DMA_ARM  ,
	input PS2WrIDE	 ,
	input [2:0] UDMA ,
	input [2:0] MDMA,
	output iDMARd		,
	output iDMAWr	 ,
	output reg iDMA_OE	 ,
	output reg iD_245_In  ,
	output reg CRC_MUX	 ,
	output reg CRC_ARM	 ,
	output reg CRC_ENB	 ,

	input A0	,
	input PA_Full		,
	input PA_HvSpace	 ,
	input PA_OD_Rdy	 ,
	input WithinABlock	 ,
	input PA_AlmostFull  ,
	input PA_Empty		,
	output IDE_DSTB,
	output reg HWOE,
	output reg RegEA,
	output reg IncAddrA , 
	output reg EnbA ,
	output reg WrA 
);











reg HDMARDY,HSTROBE,STOP;
reg ND_Rd,ND_Wr;

wire NBrkOut;
reg	iWait;
wire UDMAC,MDMAC;
reg	ND_ARM;
reg	UHO_ARM;
reg	UDI_ARM;
reg	ILatch;

wire	Proceed;
wire XiRdy1;

parameter iIdle1	= 6'b00_0000;
parameter iIdle2	= 6'b00_0001;
parameter ND_2 	= 6'b00_0010;
parameter ND_3 	= 6'b00_0011;
parameter ND_4 	= 6'b00_0100;
parameter ND_5 	= 6'b00_0101;
parameter ND_6 	= 6'b00_0110;
parameter ND_7 	= 6'b00_0111;
parameter ND_8 	= 6'b00_1000;
parameter ND_9 	= 6'b00_1001;
parameter ND_A 	= 6'b00_1010;
parameter ND_B 	= 6'b00_1011;
parameter ND_C 	= 6'b00_1100;
parameter Udi1 	= 6'b01_0000;
parameter Udi2 	= 6'b01_0001;
parameter Udi3 	= 6'b01_0010;

parameter Udi10	= 6'b01_0100;
parameter Udi11	= 6'b01_0101;
parameter Udix1 	= 6'b10_0001;
parameter Udix2 	= 6'b10_0010;
parameter Udix3 	= 6'b10_0011;
parameter Udix4 	= 6'b10_0100;
parameter Udix5 	= 6'b10_0101;
parameter Udix6 	= 6'b10_0110;
parameter Uho_G 	= 6'b10_0111;
parameter Uhx_0 	= 6'b10_1000;
parameter Uhx_1 	= 6'b10_1001;
parameter Uhx_2 	= 6'b10_1010;
parameter Uhx_3 	= 6'b10_1011;
parameter Uhx_4 	= 6'b10_1100;
parameter Uhx_5 	= 6'b10_1101;
parameter Uhx_6 	= 6'b10_1110;

parameter Uho_0	= 6'b11_0000;
parameter Uho_1	= 6'b11_0001;
parameter Uho_2	= 6'b11_0010;
parameter Uho_3	= 6'b11_0011;
parameter Uho_4	= 6'b11_0100;
parameter Uho_5	= 6'b11_0101;
parameter Uho_6	= 6'b11_0110;
parameter Uho_7	= 6'b11_0111;
parameter Uho_8	= 6'b11_1000;
parameter Uho_9	= 6'b11_1001;
parameter Uho_A	= 6'b11_1010;
parameter Uho_B	= 6'b11_1011;
parameter Uho_C	= 6'b11_1100;
parameter Uho_D	= 6'b11_1101;
parameter Uho_E	= 6'b11_1110;
parameter Uho_F	= 6'b11_1111;


reg [5:0] iSTATE;
reg [4:0] iCount;
reg PipeEmpty;
reg IDE_DSTB1;










assign iDMAWr  =	(ND_ARM & ND_Wr) | ((UDI_ARM | UHO_ARM) & ~(STOP));
assign iDMARd  =	(ND_ARM & ND_Rd) |
						(UDI_ARM & HDMARDY) |
						(UHO_ARM & ~HSTROBE);






assign 	NBrkOut	= ~iDQ | (PS2WrIDE & PA_Empty) | (~PS2WrIDE & PA_Full);



assign	UDMAC	= (UDMA[2] | UDMA[1] | UDMA[0]) & ~(MDMAC);
assign	MDMAC	= MDMA[2] | MDMA[1] | MDMA[0];
assign	Proceed = PA_OD_Rdy | WithinABlock;
assign	XiRdy1	= SiRdy1 ^ SiRdy2;
assign	IDE_DSTB = (XiRdy1 & UDI_ARM) | ((UHO_ARM | ND_ARM) & ILatch );

always @(posedge CLK4) begin
	IDE_DSTB1	<= IDE_DSTB;
	CRC_ENB		<= IDE_DSTB1 & ~IDE_DSTB;
end

always @(posedge CLK4)begin



if (DMA_ARM == 1'b0) begin

	UDI_ARM	<= 1'b0;
	UHO_ARM	<= 1'b0;
	STOP		<= 1'b1;
	HDMARDY	<= 1'b0;
	iWait		<= 1'b0;
	HSTROBE	<= 1'b1;

	ND_ARM	<= 1'b0;
	ND_Rd		<= 1'b0;
	ND_Wr		<= 1'b0;
	ILatch	<= 1'b0;

	iDK		<= 1'b0;
	iDMA_OE	<= 1'b0;
	iD_245_In	<= 1'b0;
	CRC_ARM	<= 1'b0;
	CRC_MUX	<= 1'b0;


	RegEA		<= 1'b0;
	IncAddrA	<= 1'b0;
	EnbA		<= 1'b0;
	WrA		<= 1'b0;
	iCount	<= 5'b0000;
	HWOE		<= 1'b0;
	PipeEmpty	<= 1'b1;
	iSTATE	<= iIdle1;

end else begin

if (UHO_ARM == 1'b1) begin
	if (SiRdy2 == 1'b1) begin
		iWait		<= 1'b1;
		iCount	<= 5'd00;
	end else begin
		iCount	<= iCount + 1;
		if (iCount[4] == 1'b1) begin
			iWait	<= 1'b0;
		end
	end
end

case (iSTATE)
iIdle1: begin

	UDI_ARM	<= 1'b0;
	STOP		<= 1'b1;
	HDMARDY	<= 1'b0;

	UHO_ARM	<= 1'b0;
	HSTROBE	<= 1'b1;

	ND_ARM	<= 1'b0;
	ND_Rd		<= 1'b0;
	ND_Wr		<= 1'b0;
	ILatch	<= 1'b0;

	iDK		<= 1'b0;
	iDMA_OE	<= 1'b0;
	iD_245_In	<= 1'b0;
	CRC_ARM	<= 1'b0;
	CRC_MUX	<= 1'b0;

	RegEA		<= 1'b0;
	IncAddrA	<= 1'b0;
	EnbA		<= 1'b0;
	WrA		<= 1'b0;
	iCount	<= 5'b0000;

	iSTATE	<= iIdle2;
end

iIdle2: begin
	iCount	<= 5'd00;
	if (iDQ == 1'b1) begin
		if (UDMAC == 1'b1) begin
			if (PS2WrIDE == 1'b1) begin
				if (Proceed == 1'b1) begin
					iSTATE <= Uho_0;
				end
			end else begin
				if (PA_HvSpace == 1'b1) begin
					iSTATE	<= Udi1;
				end
			end
		end else begin
			if (PS2WrIDE == 1'b1) begin
				if (Proceed == 1'b1) begin
					iSTATE <= ND_2;
				end
			end else begin
				if (PA_HvSpace == 1'b1) begin
					iSTATE <= ND_2;
				end
			end
		end
	end else begin
		iSTATE <= iIdle2;
	end
end






ND_2: begin
	iSTATE		<= ND_3;
	iDK			<= iDQ;
	ND_ARM		<= 1'b1;
	iD_245_In	<= ~PS2WrIDE;
end

ND_3: begin
	iDK		<= iDQ;
	if (NBrkOut == 1'b0) begin
		EnbA		<= PS2WrIDE;
		iSTATE	<= ND_4;
	end else begin
		iD_245_In	<= 1'b0;
		ND_ARM		<= 1'b0;
		iSTATE		<= iIdle1;
	end
end

ND_4: begin
	iSTATE	<= ND_5;
	EnbA		<= 1'b0;
	RegEA		<= PS2WrIDE;
end

ND_5: begin
	iSTATE	<= ND_6;
	RegEA		<=	1'b0;
	iCount	<= 5'd00;
	iDMA_OE	<= PS2WrIDE;
end

ND_6: begin
	iSTATE	<= ND_7;
	ND_Rd		<= ~PS2WrIDE;
	ND_Wr		<=  PS2WrIDE;
end

ND_7:	begin
	iCount	<= iCount + 1;
	if (((iCount == 5'd05) && (MDMA[2] == 1'b1)) ||
		 ((iCount == 5'd07) && (MDMA[1] == 1'b1)) ||
		  (iCount == 5'd31) ) begin
		iSTATE	<= ND_8;
	end
end

ND_8: begin
	ILatch	<= ~PS2WrIDE;
	iSTATE	<= ND_9;
end
ND_9: begin

		iSTATE	<= ND_A;

end

ND_A: begin
	WrA		<= ~PS2WrIDE;
	EnbA		<= ~PS2WrIDE;
	iCount	<= 5'd00;
	iSTATE	<= ND_B;
end
ND_B: begin
	WrA		<=	1'b0;
	EnbA		<= 1'b0;
	ND_Rd		<=	1'b0;
	ND_Wr		<= 1'b0;
	ILatch	<= 1'b0;
	IncAddrA	<= 1'b1;
	iSTATE	<= ND_C;
end

ND_C: begin
	iDMA_OE	<= 1'b0;
	IncAddrA	<= 1'b0;
	HWOE		<= A0;
	iCount	<= iCount + 1;
	if (((iCount == 5'd03) && (MDMA[2] == 1'b1)) ||
		 ((iCount == 5'd05) && (MDMA[1] == 1'b1)) ||
		  (iCount == 5'd31) ) begin
		iSTATE	<= ND_3;
	end
end



Udi1:	begin
	UDI_ARM		<= 1'b1;
	iDK			<= 1'b0;
	iDMA_OE		<= 1'b0;
	STOP			<= 1'b1;
	HDMARDY		<= 1'b0;
	if (Phase3 == 1'b1) begin
		iSTATE	<= Udi2;
	end
end
Udi2:	begin
	if (iDQ == 1'b1) begin
		if ((Phase3 == 1'b1) && (SiRdy2 == 1'b1)) begin
			iSTATE	<= Udi3;
		end
	end else begin
		iSTATE	<= iIdle1;
	end
end
Udi3:	begin
	iDK			<= 1'b1;
	iD_245_In	<= 1'b1;
	CRC_ARM		<=	1'b1;
	if (Phase3 == 1'b1) begin
		iSTATE	<= Udi10;
	end
end



Udi10:	begin
	IncAddrA	<= 1'b0;
	if (XiRdy1 == 1'b1) begin
		EnbA		<= 1'b1;
		WrA		<= 1'b1;

		iSTATE	<= Udi11;
	end else begin
		if (iDQ	== 1'b1) begin
			HDMARDY	<= ~PA_AlmostFull;
			STOP		<= 1'b0;
			iSTATE	<= Udi10;
		end else begin
			HDMARDY	<= 1'b0;
			STOP		<= 1'b1;
			iSTATE	<= Udix1;
		end
	end
end
Udi11:	begin
	iSTATE	<= Udi10;
	EnbA		<= 1'b0;
	WrA		<= 1'b0;

	IncAddrA	<=	1'b1;
end

Udix1:	begin
	if ((Phase3 == 1'b1) && (SiRdy2 == 1'b1)) begin
		iSTATE 	<= Udix2;
	end
end
Udix2:	begin
	CRC_MUX		<= 1'b1;
	iD_245_In	<= 1'b0;
	if (Phase3 == 1'b1) begin
		iSTATE 	<= Udix3;
	end
end
Udix3:	begin
	iDMA_OE		<= 1'b1;
	if (Phase3 == 1'b1) begin
		iSTATE <= Udix4;
	end
end
Udix4:	begin
	if (Phase3 == 1'b1) begin
		iSTATE <= Udix5;
	end
end
Udix5:	begin
	iDK		<= 1'b0;
	if (Phase3 == 1'b1) begin
		iSTATE <= Udix6;
	end
end
Udix6:	begin
	if (Phase3 == 1'b1) begin
		iSTATE <= iIdle1;
	end
end







Uho_0: begin
	UHO_ARM		<= 1'b1;
	iDK			<= 1'b1;
	STOP			<= 1'b1;
	HSTROBE		<= 1'b1;
	EnbA			<=	PipeEmpty;
	iSTATE		<= Uho_1;
end

Uho_1: begin
	iDK			<= 1'b1;
	EnbA			<= 1'b0;
	RegEA			<= PipeEmpty;
	iD_245_In	<= 1'b0;
	iSTATE		<= Uho_2;
end

Uho_2: begin
	RegEA			<= 1'b0;
	HWOE			<= ~PipeEmpty ^ A0;
	iSTATE		<= Uho_3;
end

Uho_3: begin
	STOP			<= 1'b0;
	if ((SiRdy2 == 1'b0) && (Phase3 == 1'b1)) begin
		iSTATE	<= Uho_4;
		iDMA_OE	<= 1'b1;
	end
end

Uho_4: begin
	if ((SiRdy2 == 1'b0) && (Phase3 == 1'b1)) begin
		IncAddrA	<=	PipeEmpty;
		iSTATE	<= Uho_5;
	end
end

Uho_5: begin
	IncAddrA	<= 1'b0;
	if ((SiRdy2 == 1'b0) && (Phase3 == 1'b1)) begin
		EnbA		<=	1'b1;
		iSTATE	<= Uho_6;
	end
end

Uho_6:	begin
	iSTATE	<= Uho_7;
	EnbA		<= 1'b0;
	iWait		<= 1'b0;
	HSTROBE	<= 1'b0;
	CRC_ARM	<= 1'b1;
end

Uho_7:	begin

	ILatch	<= 1'b1;

	if (PA_Empty == 1'b1) begin
		iSTATE	<= Uho_F;
	end else begin
		RegEA		<= UDMA[2];
		iSTATE	<= Uho_8;
	end
end

Uho_8:	begin

	RegEA		<= UDMA[1];
	ILatch	<= 1'b0;
	HWOE		<= (UDMA[2] == 1'b1) ? A0 : HWOE;

	if (UDMA[2] == 1'b1) begin
		IncAddrA	<=	1'b1;
		iSTATE	<= Uho_D;
	end else begin
		iSTATE	<= Uho_9;
	end
end

Uho_9: begin

	RegEA		<= 1'b0;
	HWOE		<= (UDMA[1] == 1'b1) ? A0 : HWOE;

	if (UDMA[1] == 1'b1) begin
		iSTATE	<= Uho_C;
	end else begin
		iSTATE	<= Uho_A;
	end
end

Uho_A: begin
	RegEA		<= UDMA[0];
	iSTATE	<= Uho_B;
end

Uho_B: begin

	RegEA		<= 1'b0;
	HWOE		<= (UDMA[0] == 1'b1) ? A0 : HWOE;
	iSTATE	<= Uho_C;
end
Uho_C:	begin
	iSTATE	<= Uho_D;
	IncAddrA	<=	1'b1;
end
Uho_D:	begin
	iSTATE	<= Uho_E;
	IncAddrA	<= 1'b0;
	EnbA		<=	1'b1;
end
Uho_E: begin
	EnbA		<= 1'b0;
	if (iDQ	== 1'b0) begin
		iSTATE	<= Uhx_0;
	end else begin
		if (iWait == 1'b0) begin

			HSTROBE	<= ~HSTROBE;
			iSTATE	<= Uho_7;
		end else begin
			iSTATE	<= Uho_E;
		end
	end
end


Uho_F:	begin
	PipeEmpty	<= 1'b1;
	ILatch	<= 1'b0;
	if (Phase3 == 1'b1) begin
		iSTATE		<= Uho_G;
	end
end
Uho_G:	begin
	STOP			<= 1'b1;
	if (Phase3 == 1'b1) begin
		if ((SiRdy2 == 1'b1) && (iDQ == 1'b0)) begin
			iSTATE <= Uhx_3;
		end else begin
			if (PA_OD_Rdy == 1'b1) begin
				EnbA		<=	PipeEmpty;
				iSTATE 	<= Uho_1;
			end
		end
	end
end

Uhx_0:	begin
	PipeEmpty	<= 1'b0;
	if (Phase3 == 1'b1) begin
		iSTATE		<= Uhx_1;
	end
end
Uhx_1:	begin
	if (Phase3 == 1'b1) begin
		iSTATE 	<= Uhx_2;
	end
end
Uhx_2:	begin
	STOP			<= 1'b1;
	if ((Phase3 == 1'b1) && (SiRdy2 == 1'b1) && (iDQ == 1'b0)) begin
		iSTATE <= Uhx_3;
	end
end
Uhx_3:	begin
	HSTROBE		<= 1'b1;
	CRC_MUX		<= 1'b1;
	if (Phase3 == 1'b1) begin
		iSTATE <= Uhx_4;
	end
end
Uhx_4:	begin
	if (Phase3 == 1'b1) begin
		iSTATE <= Uhx_5;
	end
end
Uhx_5:	begin
	iDK		<= 1'b0;
	if (Phase3 == 1'b1) begin
		iSTATE <= Uhx_6;
	end
end
Uhx_6:	begin
	if (Phase3 == 1'b1) begin
		iSTATE <= iIdle1;
	end
end

default: begin
	iSTATE <= iIdle1;
end
endcase
end
end

endmodule