data/full_repos/permissive/140999934/CPU/axi_cpu/exe.v
1: b'%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/exe.v:65: syntax error, unexpected break, expecting IDENTIFIER or do or final\n wire break;\n      ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/exe.v:93: syntax error, unexpected break, expecting TYPE-IDENTIFIER\n   break,\n   ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/exe.v:185: syntax error, unexpected break, expecting TYPE-IDENTIFIER\n        cp0r_addr,syscall,eret,break,   \n                               ^~~~~\n%Error: Exiting due to 3 error(s)\n'
module exe(
	input wire 		    EXE_valid,
	input wire [181:0]  ID_EXE_bus_r,
	output wire 	    EXE_over,
	output wire [166:0]	EXE_MEM_bus,


	input wire 			clk,
	output wire [  4:0] EXE_wdest,
    output wire [ 31:0] EXE_result_quick_get,
    output wire         EXE_quick_en,


	output wire [ 31:0]	EXE_pc
	





);


	wire [1:0] muldiv;
	wire muldiv_signed;
	wire mthi;
	wire mtlo;
	wire [11:0] alu_control;
	wire [31:0] alu_operand1;
	wire [31:0] alu_operand2;
	wire data_related_en;


	wire [5:0] mem_control;
	wire [31:0] store_data;
	

	wire mfhi;
	wire mflo;
	wire mtc0;
	wire mfc0;
	wire [7:0] cp0r_addr;
	wire syscall;
	wire eret;
	wire break;
	wire addr_exc;
	wire ri_exc;
	wire ov_exc_en;
	wire is_ds;
	wire [1:0] halfword;
	wire [3:0] rf_wen;
	wire [4:0] rf_wdest;
	

	wire [31:0] pc;
	assign {muldiv,
	        muldiv_signed,
			mthi,
			mtlo,
			alu_control,
			alu_operand1,
			alu_operand2,
			data_related_en,
			mem_control,
			store_data,
			mfhi,
			mflo,
			mtc0,
			mfc0,
			cp0r_addr,
			syscall,
			eret,
			break,
			addr_exc,
			ri_exc,
			ov_exc_en,
			is_ds,
			halfword,
			rf_wen,
			rf_wdest,
			pc} = ID_EXE_bus_r;



	wire [31:0] alu_result;
	wire ov_exc;
	alu alu_module(
		.alu_control	(alu_control),
		.alu_src1		(alu_operand1),
		.alu_src2		(alu_operand2),
		.alu_result		(alu_result),
		.ov_exc 		(ov_exc)
	);



	wire  		div_begin;
	wire [31:0] div_result;
	wire [31:0] div_remainder;
	wire 		div_end;

	assign div_begin = muldiv[1] & EXE_valid;
	divider divider_module(
		.clk 			(clk),
		.div_begin 		(div_begin),
		.div_signed     (muldiv_signed),
		.div_op1 		(alu_operand1),
		.div_op2		(alu_operand2),
		.div_result		(div_result),
		.div_remainder	(div_remainder),
		.div_end 		(div_end)
	);

	wire 		mult_begin;
	wire [63:0] product;
	wire 		mult_end;

	assign mult_begin = muldiv[0] & EXE_valid;
	multiply multiply_module (
		.clk		(clk),
		.mult_begin (mult_begin),
		.mult_signed(muldiv_signed),
		.mult_op1 	(alu_operand1),
		.mult_op2	(alu_operand2),
		.product 	(product),
		.mult_end 	(mult_end)
	);





	assign EXE_over = EXE_valid & (~muldiv[0] | mult_end) & (~muldiv[1] | div_end);




	assign EXE_wdest = rf_wdest & {5{EXE_valid}};



	wire [31:0] exe_result;
	wire [31:0] lo_result;
	wire 		hi_write;
	wire 		lo_write;
	wire        ov_exc_final;


	assign exe_result = mthi 		? alu_operand1 :
						mtc0 		? alu_operand2 :
						muldiv[0]	? product[63:32] : 
						muldiv[1] 	? div_remainder : alu_result;
	assign lo_result = mtlo ? alu_operand1 : 
					   muldiv[0] ? product[31:0] : div_result;
	assign hi_write = muldiv[0] | muldiv[1] | mthi;
	assign lo_write = muldiv[0] | muldiv[1] | mtlo;
    assign ov_exc_final = ov_exc_en & ov_exc;
	assign EXE_MEM_bus = {mem_control,store_data,
						  data_related_en,                  
						  exe_result,
						  lo_result,
						  hi_write,lo_write,
						  mfhi,mflo,
						  mtc0,mfc0,
						  cp0r_addr,syscall,eret,break,
						  addr_exc, ov_exc_final, ri_exc,
						  is_ds,halfword,rf_wen,rf_wdest,
						  pc};
	assign EXE_result_quick_get = exe_result;
	assign EXE_quick_en = data_related_en;



	assign EXE_pc = pc;







endmodule
module exe(
	input wire 		    EXE_valid,
	input wire [181:0]  ID_EXE_bus_r,
	output wire 	    EXE_over,
	output wire [166:0]	EXE_MEM_bus,


	input wire 			clk,
	output wire [  4:0] EXE_wdest,
    output wire [ 31:0] EXE_result_quick_get,
    output wire         EXE_quick_en,


	output wire [ 31:0]	EXE_pc
	





);



	wire [1:0] muldiv;
	wire muldiv_signed;
	wire mthi;
	wire mtlo;
	wire [11:0] alu_control;
	wire [31:0] alu_operand1;
	wire [31:0] alu_operand2;
	wire data_related_en;


	wire [5:0] mem_control;
	wire [31:0] store_data;
	

	wire mfhi;
	wire mflo;
	wire mtc0;
	wire mfc0;
	wire [7:0] cp0r_addr;
	wire syscall;
	wire eret;
	wire break;
	wire addr_exc;
	wire ri_exc;
	wire ov_exc_en;
	wire is_ds;
	wire [1:0] halfword;
	wire [3:0] rf_wen;
	wire [4:0] rf_wdest;
	

	wire [31:0] pc;
	assign {muldiv,
	        muldiv_signed,
			mthi,
			mtlo,
			alu_control,
			alu_operand1,
			alu_operand2,
			data_related_en,
			mem_control,
			store_data,
			mfhi,
			mflo,
			mtc0,
			mfc0,
			cp0r_addr,
			syscall,
			eret,
			break,
			addr_exc,
			ri_exc,
			ov_exc_en,
			is_ds,
			halfword,
			rf_wen,
			rf_wdest,
			pc} = ID_EXE_bus_r;



	wire [31:0] alu_result;
	wire ov_exc;
	alu alu_module(
		.alu_control	(alu_control),
		.alu_src1		(alu_operand1),
		.alu_src2		(alu_operand2),
		.alu_result		(alu_result),
		.ov_exc 		(ov_exc)
	);



	wire  		div_begin;
	wire [31:0] div_result;
	wire [31:0] div_remainder;
	wire 		div_end;

	assign div_begin = muldiv[1] & EXE_valid;
	divider divider_module(
		.clk 			(clk),
		.div_begin 		(div_begin),
		.div_signed     (muldiv_signed),
		.div_op1 		(alu_operand1),
		.div_op2		(alu_operand2),
		.div_result		(div_result),
		.div_remainder	(div_remainder),
		.div_end 		(div_end)
	);

	wire 		mult_begin;
	wire [63:0] product;
	wire 		mult_end;

	assign mult_begin = muldiv[0] & EXE_valid;
	multiply multiply_module (
		.clk		(clk),
		.mult_begin (mult_begin),
		.mult_signed(muldiv_signed),
		.mult_op1 	(alu_operand1),
		.mult_op2	(alu_operand2),
		.product 	(product),
		.mult_end 	(mult_end)
	);





	assign EXE_over = EXE_valid & (~muldiv[0] | mult_end) & (~muldiv[1] | div_end);




	assign EXE_wdest = rf_wdest & {5{EXE_valid}};



	wire [31:0] exe_result;
	wire [31:0] lo_result;
	wire 		hi_write;
	wire 		lo_write;
	wire        ov_exc_final;


	assign exe_result = mthi 		? alu_operand1 :
						mtc0 		? alu_operand2 :
						muldiv[0]	? product[63:32] : 
						muldiv[1] 	? div_remainder : alu_result;
	assign lo_result = mtlo ? alu_operand1 : 
					   muldiv[0] ? product[31:0] : div_result;
	assign hi_write = muldiv[0] | muldiv[1] | mthi;
	assign lo_write = muldiv[0] | muldiv[1] | mtlo;
    assign ov_exc_final = ov_exc_en & ov_exc;
	assign EXE_MEM_bus = {mem_control,store_data,
						  data_related_en,                  
						  exe_result,
						  lo_result,
						  hi_write,lo_write,
						  mfhi,mflo,
						  mtc0,mfc0,
						  cp0r_addr,syscall,eret,break,
						  addr_exc, ov_exc_final, ri_exc,
						  is_ds,halfword,rf_wen,rf_wdest,
						  pc};
	assign EXE_result_quick_get = exe_result;
	assign EXE_quick_en = data_related_en;



	assign EXE_pc = pc;







endmodule