data/full_repos/permissive/156609923/fifo/probador.v
 line:136: before: "$"
1: b'%Error: data/full_repos/permissive/156609923/fifo/probador.v:29: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("fifo.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:30: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:31: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:35: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:41: syntax error, unexpected \'@\'\n   @(posedge clk); \n   ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:46: syntax error, unexpected \'@\'\n     @(posedge clk); \n     ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:51: syntax error, unexpected \'@\'\n      @(posedge clk); \n      ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:56: syntax error, unexpected \'@\'\n      @(posedge clk); \n      ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:61: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:65: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:70: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:75: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:80: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:85: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:91: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:95: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:101: syntax error, unexpected \'@\'\n   @(posedge clk); \n   ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:106: syntax error, unexpected \'@\'\n     @(posedge clk); \n     ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:111: syntax error, unexpected \'@\'\n      @(posedge clk); \n      ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:116: syntax error, unexpected \'@\'\n      @(posedge clk); \n      ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:121: syntax error, unexpected \'@\'\n      @(posedge clk); \n      ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:126: syntax error, unexpected \'@\'\n      @(posedge clk); \n      ^\n%Error: data/full_repos/permissive/156609923/fifo/probador.v:131: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/fifo/probador.v:135: Unsupported: Ignoring delay on this delayed statement.\n      #1000\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156609923/fifo/probador.v:147: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk <= ~clk;\n          ^\n%Error: Exiting due to 23 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador #(
parameter ADDR_WIDTH = 3,
parameter BUS_SIZE = 5,
parameter MEM_LENGTH = 1 << ADDR_WIDTH)(

 output reg 		   clk,
 output reg 		   reset ,
 output reg 		   push,pop,
 output reg [BUS_SIZE-1:0] data_in,
 output reg 		   valid, 
 
 input [BUS_SIZE-1:0] 	   data_out_synth,
 input [BUS_SIZE-1:0] 	   data_out_cond,
 input 			   empty,
 input 			   continua,
 input 			   pause,
 input 			   valid_out,
 
input 			   empty_syn,
 input 			   continua_syn,
 input 			   pause_syn,
 input 			   valid_out_syn				

);
   
   

   initial begin
   $dumpfile("fifo.vcd");
	$dumpvars();
   @(posedge clk);
      reset<=0;
   
   
   @(posedge clk);
      data_in<='b1;
      push <= 1;
      valid <= ~valid;
      
   
   @(posedge clk); 
      push <= 1;	
      data_in <= $random;
      valid <= ~valid;

     @(posedge clk); 
      push <= 1;	
      data_in <= $random;
      valid <= ~valid;

      @(posedge clk); 
      push <= 1;	
      data_in <= $random;
      valid <= ~valid;
       
      @(posedge clk); 
      push <= 1;
      data_in <= $random;
      valid <= ~valid;
      
      @(posedge clk);
      push <=0;
      pop<= 0;

      @(posedge clk);
      data_in<=$random;
      valid <= ~valid;
      pop <= 1;
      
       @(posedge clk);
      data_in<=$random;
      valid <= ~valid;
      pop <= 1;

       @(posedge clk);
      data_in<=$random;
      valid <= ~valid;
      pop <= 1;
      
    @(posedge clk);
      data_in<=$random;
      valid <= ~valid;
      pop <= 1;

       @(posedge clk);
      data_in<=$random;
      valid <= ~valid;
      pop <= 1;
   
   
   @(posedge clk);
      pop<=0;


      @(posedge clk);
      data_in<='b1;
      push <= 1;
      valid <= ~valid;
      
   
   @(posedge clk); 
      push <= 1;	
      data_in <= $random;
      valid <= ~valid;

     @(posedge clk); 
      push <= 1;	
      data_in <= $random;
      valid <= ~valid;

      @(posedge clk); 
      push <= 1;	
      data_in <= $random;
      valid <= ~valid;
       
      @(posedge clk); 
      push <= 1;
      data_in <= $random;
      valid <= ~valid;

      @(posedge clk); 
      push <= 1;
      data_in <= $random;
      valid <= ~valid;

      @(posedge clk); 
      push <= 1;
      data_in <= $random;
      valid <= ~valid;

      @(posedge clk);
      push <=0;
      
      
      #1000
   $finish;
end  
   
   initial clk <= 0;
   initial reset<=1;
   initial valid<=0;

   initial pop<=0;
   initial push<=0;
   
   
   always #1 clk <= ~clk;
   

endmodule
module probador #(
parameter ADDR_WIDTH = 3,
parameter BUS_SIZE = 5,
parameter MEM_LENGTH = 1 << ADDR_WIDTH)(

 output reg 		   clk,
 output reg 		   reset ,
 output reg 		   push,pop,
 output reg [BUS_SIZE-1:0] data_in,
 output reg 		   valid, 
 
 input [BUS_SIZE-1:0] 	   data_out_synth,
 input [BUS_SIZE-1:0] 	   data_out_cond,
 input 			   empty,
 input 			   continua,
 input 			   pause,
 input 			   valid_out,
 
input 			   empty_syn,
 input 			   continua_syn,
 input 			   pause_syn,
 input 			   valid_out_syn				

);

   
   

   initial begin
   $dumpfile("fifo.vcd");
	$dumpvars();
   @(posedge clk);
      reset<=0;
   
   
   @(posedge clk);
      data_in<='b1;
      push <= 1;
      valid <= ~valid;
      
   
   @(posedge clk); 
      push <= 1;	
      data_in <= $random;
      valid <= ~valid;

     @(posedge clk); 
      push <= 1;	
      data_in <= $random;
      valid <= ~valid;

      @(posedge clk); 
      push <= 1;	
      data_in <= $random;
      valid <= ~valid;
       
      @(posedge clk); 
      push <= 1;
      data_in <= $random;
      valid <= ~valid;
      
      @(posedge clk);
      push <=0;
      pop<= 0;

      @(posedge clk);
      data_in<=$random;
      valid <= ~valid;
      pop <= 1;
      
       @(posedge clk);
      data_in<=$random;
      valid <= ~valid;
      pop <= 1;

       @(posedge clk);
      data_in<=$random;
      valid <= ~valid;
      pop <= 1;
      
    @(posedge clk);
      data_in<=$random;
      valid <= ~valid;
      pop <= 1;

       @(posedge clk);
      data_in<=$random;
      valid <= ~valid;
      pop <= 1;
   
   
   @(posedge clk);
      pop<=0;


      @(posedge clk);
      data_in<='b1;
      push <= 1;
      valid <= ~valid;
      
   
   @(posedge clk); 
      push <= 1;	
      data_in <= $random;
      valid <= ~valid;

     @(posedge clk); 
      push <= 1;	
      data_in <= $random;
      valid <= ~valid;

      @(posedge clk); 
      push <= 1;	
      data_in <= $random;
      valid <= ~valid;
       
      @(posedge clk); 
      push <= 1;
      data_in <= $random;
      valid <= ~valid;

      @(posedge clk); 
      push <= 1;
      data_in <= $random;
      valid <= ~valid;

      @(posedge clk); 
      push <= 1;
      data_in <= $random;
      valid <= ~valid;

      @(posedge clk);
      push <=0;
      
      
      #1000
   $finish;
end  
   
   initial clk <= 0;
   initial reset<=1;
   initial valid<=0;

   initial pop<=0;
   initial push<=0;
   
   
   always #1 clk <= ~clk;
   

endmodule