data/full_repos/permissive/212897440/top_tb.v
 line:23: before: ","
1: b'%Error: data/full_repos/permissive/212897440/top_tb.v:11: Cannot find include file: clock_divider_param.v\n`include "clock_divider_param.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/clock_divider_param.v\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/clock_divider_param.v.v\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/clock_divider_param.v.sv\n             clock_divider_param.v\n             clock_divider_param.v.v\n             clock_divider_param.v.sv\n             obj_dir/clock_divider_param.v\n             obj_dir/clock_divider_param.v.v\n             obj_dir/clock_divider_param.v.sv\n%Error: data/full_repos/permissive/212897440/top_tb.v:12: Cannot find include file: clock_enable_param.v\n`include "clock_enable_param.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/212897440/top_tb.v:13: Cannot find include file: debounce_switch.v\n`include "debounce_switch.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/212897440/top_tb.v:17: Cannot find include file: top.v\n`include "top.v" \n         ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/212897440/top_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212897440/top_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #030_000; \n    ^\n%Error: data/full_repos/permissive/212897440/top_tb.v:48: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("wave.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/212897440/top_tb.v:49: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0);\n    ^~~~~~~~~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n'
module top_tb();

reg clk = 1'b0;


always #0.5 clk <= ~clk;

top UUT(
    .clk(clk)
);



initial begin
    #030_000; 
    $display("*");

    $display(" ");
    $display("Use this command to open timing diagram:");
    $display("gtkwave -f wave.vcd");
    $display("----------------------------------------------");
    $finish();
end

initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
end

endmodule
module top_tb();


reg clk = 1'b0;


always #0.5 clk <= ~clk;

top UUT(
    .clk(clk)
);



initial begin
    #030_000; 
    $display("*");

    $display(" ");
    $display("Use this command to open timing diagram:");
    $display("gtkwave -f wave.vcd");
    $display("----------------------------------------------");
    $finish();
end

initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
end

endmodule