data/full_repos/permissive/173150157/rtl/demo/display_demo_vga.v
1: b"%Error: data/full_repos/permissive/173150157/rtl/demo/display_demo_vga.v:27: Cannot find file containing module: 'display_clocks'\n    display_clocks #(                \n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173150157/rtl/demo,data/full_repos/permissive/173150157/display_clocks\n             data/full_repos/permissive/173150157/rtl/demo,data/full_repos/permissive/173150157/display_clocks.v\n             data/full_repos/permissive/173150157/rtl/demo,data/full_repos/permissive/173150157/display_clocks.sv\n             display_clocks\n             display_clocks.v\n             display_clocks.sv\n             obj_dir/display_clocks\n             obj_dir/display_clocks.v\n             obj_dir/display_clocks.sv\n%Error: data/full_repos/permissive/173150157/rtl/demo/display_demo_vga.v:51: Cannot find file containing module: 'display_timings'\n    display_timings #(               \n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173150157/rtl/demo/display_demo_vga.v:80: Cannot find file containing module: 'test_card_simple'\n    test_card_simple #(\n    ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module display_demo_vga(
    input  wire CLK,
    input  wire RST_BTN,
    output wire VGA_HS,
    output wire VGA_VS,
    output wire [3:0] VGA_R,
    output wire [3:0] VGA_G,
    output wire [3:0] VGA_B
    );


    wire pix_clk;
    wire clk_lock;

    display_clocks #(
        .MULT_MASTER(31.5),
        .DIV_MASTER(5),
        .DIV_5X(5.0),
        .DIV_1X(25),
        .IN_PERIOD(10.0)
    )
    display_clocks_inst
    (
       .i_clk(CLK),
       .i_rst(~RST_BTN),
       .o_clk_1x(pix_clk),
       .o_clk_5x(),
       .o_locked(clk_lock)
    );


    wire signed [15:0] sx;
    wire signed [15:0] sy;
    wire h_sync;
    wire v_sync;
    wire de;
    wire frame;

    display_timings #(
        .H_RES(640),
        .V_RES(480),
        .H_FP(16),
        .H_SYNC(96),
        .H_BP(48),
        .V_FP(10),
        .V_SYNC(2),
        .V_BP(33),
        .H_POL(0),
        .V_POL(0)
    )
    display_timings_inst (
        .i_pix_clk(pix_clk),
        .i_rst(!clk_lock),
        .o_hs(h_sync),
        .o_vs(v_sync),
        .o_de(de),
        .o_frame(frame),
        .o_sx(sx),
        .o_sy(sy)
    );


    wire [7:0] red;
    wire [7:0] green;
    wire [7:0] blue;


    test_card_simple #(
        .H_RES(640)
    ) test_card_inst (
        .i_x(sx),
        .o_red(red),
        .o_green(green),
        .o_blue(blue)
    );


























    assign VGA_HS   = h_sync;
    assign VGA_VS   = v_sync;
    assign VGA_R    = de ? red[7:4] : 4'b0;
    assign VGA_G    = de ? green[7:4] : 4'b0;
    assign VGA_B    = de ? blue[7:4] : 4'b0;
endmodule
module display_demo_vga(
    input  wire CLK,
    input  wire RST_BTN,
    output wire VGA_HS,
    output wire VGA_VS,
    output wire [3:0] VGA_R,
    output wire [3:0] VGA_G,
    output wire [3:0] VGA_B
    );



    wire pix_clk;
    wire clk_lock;

    display_clocks #(
        .MULT_MASTER(31.5),
        .DIV_MASTER(5),
        .DIV_5X(5.0),
        .DIV_1X(25),
        .IN_PERIOD(10.0)
    )
    display_clocks_inst
    (
       .i_clk(CLK),
       .i_rst(~RST_BTN),
       .o_clk_1x(pix_clk),
       .o_clk_5x(),
       .o_locked(clk_lock)
    );


    wire signed [15:0] sx;
    wire signed [15:0] sy;
    wire h_sync;
    wire v_sync;
    wire de;
    wire frame;

    display_timings #(
        .H_RES(640),
        .V_RES(480),
        .H_FP(16),
        .H_SYNC(96),
        .H_BP(48),
        .V_FP(10),
        .V_SYNC(2),
        .V_BP(33),
        .H_POL(0),
        .V_POL(0)
    )
    display_timings_inst (
        .i_pix_clk(pix_clk),
        .i_rst(!clk_lock),
        .o_hs(h_sync),
        .o_vs(v_sync),
        .o_de(de),
        .o_frame(frame),
        .o_sx(sx),
        .o_sy(sy)
    );


    wire [7:0] red;
    wire [7:0] green;
    wire [7:0] blue;


    test_card_simple #(
        .H_RES(640)
    ) test_card_inst (
        .i_x(sx),
        .o_red(red),
        .o_green(green),
        .o_blue(blue)
    );


























    assign VGA_HS   = h_sync;
    assign VGA_VS   = v_sync;
    assign VGA_R    = de ? red[7:4] : 4'b0;
    assign VGA_G    = de ? green[7:4] : 4'b0;
    assign VGA_B    = de ? blue[7:4] : 4'b0;
endmodule