data/full_repos/permissive/197263932/main.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/197263932/main.v:18: syntax error, unexpected $end, expecting ',' or ':'\n6   b000000: controls <= 9   b110000010;  \n ^\n%Error: Cannot continue\n"
module maindec(
	input logic [5:0] op,
	output logic memtoreg, memwrite,
	output logic branch, alusrc,
	output logic regdst, regwrite,
	output logic jump,
	output logic [1:0] aluop);
	
logic [8:0] controls;
assign {
	regwrite, regdst, 
	alusrc, branch, 
	memwrite, memtoreg, 
	jump, aluop} = controls;

always_comb
	case(op)
6’b000000: controls <= 9’b110000010;
6’b100011: controls <= 9’b101001000;
6’b101011: controls <= 9’b001010000;
6’b000100: controls <= 9’b000100001;
6’b001000: controls <= 9’b101000000;
6’b000010: controls <= 9’b000000100;
	default:
controls <= 9’bxxxxxxxxx;
	endcase

endmodule
module maindec(
	input logic [5:0] op,
	output logic memtoreg, memwrite,
	output logic branch, alusrc,
	output logic regdst, regwrite,
	output logic jump,
	output logic [1:0] aluop);

	
logic [8:0] controls;
assign {
	regwrite, regdst, 
	alusrc, branch, 
	memwrite, memtoreg, 
	jump, aluop} = controls;

always_comb
	case(op)
6’b000000: controls <= 9’b110000010;
6’b100011: controls <= 9’b101001000;
6’b101011: controls <= 9’b001010000;
6’b000100: controls <= 9’b000100001;
6’b001000: controls <= 9’b101000000;
6’b000010: controls <= 9’b000000100;
	default:
controls <= 9’bxxxxxxxxx;
	endcase

endmodule