data/full_repos/permissive/118800618/InstMem.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/118800618/InstMem.v:31: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'instr'\n                                                                     : ... In instance InstMem\n            instr <= mem[pc >> 2];\n            ^~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module InstMem( pc, instr
    );
	 input[31:0] pc;
	 output [31:0] instr;
	 reg [31:0] mem [0:64];
    initial begin
        $readmemb("my_test_rom.txt", mem);
   end

    always@(pc) begin
            instr <= mem[pc >> 2];

        end


endmodule
module InstMem( pc, instr
    );

	 input[31:0] pc;
	 output [31:0] instr;
	 reg [31:0] mem [0:64];
    initial begin
        $readmemb("my_test_rom.txt", mem);
   end

    always@(pc) begin
            instr <= mem[pc >> 2];

        end


endmodule