data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v
1: b'%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:43: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [100] <= instruction1[31:24];\n                                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:44: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [101] <= instruction1[23:16];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:45: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [102] <= instruction1[15:8];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:46: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [103] <= instruction1[7:0];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:48: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [104] <= instruction2[31:24];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:49: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [105] <= instruction2[23:16];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:50: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [106] <= instruction2[15:8];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:51: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [107] <= instruction2[7:0];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:53: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [108] <= instruction3[31:24];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:54: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [109] <= instruction3[23:16];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:55: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [110] <= instruction3[15:8];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:56: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [111] <= instruction3[7:0];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:58: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [112] <= instruction4[31:24];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:59: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [113] <= instruction4[23:16];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:60: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [114] <= instruction4[15:8];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:61: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [115] <= instruction4[7:0];   \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:63: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [116] <= instruction5[31:24];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:64: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [117] <= instruction5[23:16];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:65: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [118] <= instruction5[15:8];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:66: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                               : ... In instance instruction_module\n        instruction_memory [119] <= instruction5[7:0];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:72: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                                                               : ... In instance instruction_module\n        data_out[31:24] <= instruction_memory [PC];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:73: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                                                               : ... In instance instruction_module\n        data_out[23:16] <= instruction_memory [PC+1];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:74: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                                                               : ... In instance instruction_module\n        data_out[15:8] <= instruction_memory [PC+2];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/instruction_module.v:75: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                                                               : ... In instance instruction_module\n        data_out[7:0] <= instruction_memory [PC+3];\n                      ^~\n%Error: Exiting due to 24 warning(s)\n'
module instruction_module(PC, data_out);
    
    input [31:0] PC;
    output reg [31:0] data_out;
    
    reg [8:0] instruction_memory [0:1023];
    

    parameter [31:0] instruction1 = 32'b00000000001000100001100000100000;

    parameter [31:0] instruction2 = 32'b00000001001000110001000000100010;

    parameter [31:0] instruction3 = 32'b00000000011010010010100000100101;

    parameter [31:0] instruction4 = 32'b00000000011010010011000000100110;

    parameter [31:0] instruction5 = 32'b00000000011010010011100000100100;

    initial
    begin
        instruction_memory [100] <= instruction1[31:24];
        instruction_memory [101] <= instruction1[23:16];
        instruction_memory [102] <= instruction1[15:8];
        instruction_memory [103] <= instruction1[7:0];
        
        instruction_memory [104] <= instruction2[31:24];
        instruction_memory [105] <= instruction2[23:16];
        instruction_memory [106] <= instruction2[15:8];
        instruction_memory [107] <= instruction2[7:0];
        
        instruction_memory [108] <= instruction3[31:24];
        instruction_memory [109] <= instruction3[23:16];
        instruction_memory [110] <= instruction3[15:8];
        instruction_memory [111] <= instruction3[7:0];
        
        instruction_memory [112] <= instruction4[31:24];
        instruction_memory [113] <= instruction4[23:16];
        instruction_memory [114] <= instruction4[15:8];
        instruction_memory [115] <= instruction4[7:0];   
        
        instruction_memory [116] <= instruction5[31:24];
        instruction_memory [117] <= instruction5[23:16];
        instruction_memory [118] <= instruction5[15:8];
        instruction_memory [119] <= instruction5[7:0];
        
    end
    
    always @(PC)
    begin
        data_out[31:24] <= instruction_memory [PC];
        data_out[23:16] <= instruction_memory [PC+1];
        data_out[15:8] <= instruction_memory [PC+2];
        data_out[7:0] <= instruction_memory [PC+3];
    end

endmodule
module instruction_module(PC, data_out);

    
    input [31:0] PC;
    output reg [31:0] data_out;
    
    reg [8:0] instruction_memory [0:1023];
    

    parameter [31:0] instruction1 = 32'b00000000001000100001100000100000;

    parameter [31:0] instruction2 = 32'b00000001001000110001000000100010;

    parameter [31:0] instruction3 = 32'b00000000011010010010100000100101;

    parameter [31:0] instruction4 = 32'b00000000011010010011000000100110;

    parameter [31:0] instruction5 = 32'b00000000011010010011100000100100;

    initial
    begin
        instruction_memory [100] <= instruction1[31:24];
        instruction_memory [101] <= instruction1[23:16];
        instruction_memory [102] <= instruction1[15:8];
        instruction_memory [103] <= instruction1[7:0];
        
        instruction_memory [104] <= instruction2[31:24];
        instruction_memory [105] <= instruction2[23:16];
        instruction_memory [106] <= instruction2[15:8];
        instruction_memory [107] <= instruction2[7:0];
        
        instruction_memory [108] <= instruction3[31:24];
        instruction_memory [109] <= instruction3[23:16];
        instruction_memory [110] <= instruction3[15:8];
        instruction_memory [111] <= instruction3[7:0];
        
        instruction_memory [112] <= instruction4[31:24];
        instruction_memory [113] <= instruction4[23:16];
        instruction_memory [114] <= instruction4[15:8];
        instruction_memory [115] <= instruction4[7:0];   
        
        instruction_memory [116] <= instruction5[31:24];
        instruction_memory [117] <= instruction5[23:16];
        instruction_memory [118] <= instruction5[15:8];
        instruction_memory [119] <= instruction5[7:0];
        
    end
    
    always @(PC)
    begin
        data_out[31:24] <= instruction_memory [PC];
        data_out[23:16] <= instruction_memory [PC+1];
        data_out[15:8] <= instruction_memory [PC+2];
        data_out[7:0] <= instruction_memory [PC+3];
    end

endmodule