data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv
 line:27: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:33: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2.0);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:35: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2.0);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:78: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:80: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 10);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:85: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:88: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 0.5);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:91: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:106: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:120: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:124: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:127: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:141: Unsupported: Ignoring delay on this delayed statement.\n  #(0.1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:154: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD * 1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:161: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD);  \n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_AHB_master.sv:39: Cannot find file containing module: \'AHB_master\'\n AHB_master DUT(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120518070/main/source,data/full_repos/permissive/120518070/AHB_master\n             data/full_repos/permissive/120518070/main/source,data/full_repos/permissive/120518070/AHB_master.v\n             data/full_repos/permissive/120518070/main/source,data/full_repos/permissive/120518070/AHB_master.sv\n             AHB_master\n             AHB_master.v\n             AHB_master.sv\n             obj_dir/AHB_master\n             obj_dir/AHB_master.v\n             obj_dir/AHB_master.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_AHB_master();


	localparam CLK_PERIOD 	= 35;
	localparam CLK_DELAY 	= 30;
	localparam RESET_VALUE  = 0;


	reg tb_HRESETn,tb_HCLK,tb_HREADY, tb_startAddr_sel, tb_HWRITE, tb_data_feedback;
	reg [31:0] tb_HRDATA, tb_wdata, tb_HADDR, tb_HWDATA, tb_rdata;
	reg [1:0] tb_mode, tb_size, tb_HSIZE;
	reg [11:0]tb_image_width, tb_image_height;
	reg [19:0] tb_pixNum, tb_image_startAddr;



	integer tb_test_num;
	string tb_test_case;


	always
	begin
		tb_HCLK = 1'b0;
		#(CLK_PERIOD/2.0);
		tb_HCLK = 1'b1;
		#(CLK_PERIOD/2.0);
	end
	

	AHB_master DUT(
		.clk(tb_HCLK),
		.n_rst(tb_HRESETn),
		.HREADY(tb_HREADY),
		.HRDATA(tb_HRDATA),
		.mode(tb_mode),
		.wdata(tb_wdata),
		.pixNum(tb_pixNum),
		.image_startAddr(tb_image_startAddr),
		.size(tb_size),
		.image_width(tb_image_width),
		.image_height(tb_image_height),
		.startAddr_sel(tb_startAddr_sel),
		.HADDR(tb_HADDR),
		.HWDATA(tb_HWDATA),
		.HWRITE(tb_HWRITE),
		.HSIZE(tb_HSIZE),
		.data_feedback(tb_data_feedback),
		.rdata(tb_rdata)
	);
	

	initial 
	begin
		

		tb_HRESETn	= 1'b1;
		tb_test_num = 0;
		tb_HREADY = 1;
		tb_HRDATA = '0;
		tb_mode = '0;
		tb_wdata = '0;
		tb_pixNum = '0;
		tb_image_startAddr = '0;
		tb_size = '0;
		tb_image_width = 640;
		tb_image_height = 480;
		tb_startAddr_sel = 0;

		#(0.1);

		#(CLK_PERIOD * 10);


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Reset everything";
		#(0.1);
		tb_HRESETn	= 1'b0;

		#(CLK_PERIOD * 0.5);


		#(CLK_PERIOD);
		if((tb_HWRITE == RESET_VALUE) && (tb_HSIZE == RESET_VALUE) && (tb_HWDATA == RESET_VALUE) && (tb_rdata == RESET_VALUE) && (tb_data_feedback == RESET_VALUE) && (tb_HADDR[31:28] == RESET_VALUE))
		begin
			$info("Reset done in %s test case", tb_test_case);
		end
		else
		begin
			$error("Reset not done in %s test case", tb_test_case);
		end

		


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Read Instruction";
		#(0.1);
		tb_HRESETn	= 1'b1;

		tb_HREADY = 1;
		tb_HRDATA = '0;
		tb_mode = 2'b01;
		tb_wdata = '1;
		tb_pixNum = 311;
		tb_image_startAddr = '0;
		tb_size = 2'b10;
		tb_image_width = 640;
		tb_image_height = 480;
		tb_startAddr_sel = 0;

		#(CLK_PERIOD * 1);

		tb_HREADY = 0;

		#(CLK_PERIOD * 1);


		#(CLK_PERIOD);
		if(tb_HSIZE == tb_size)
		begin
			$info("State changes correctly in %s test case", tb_test_case);
		end
		else
		begin
			$error("State does not change correctly in %s test case", tb_test_case);
		end

	

		tb_test_num = tb_test_num + 1;
		tb_test_case = "Read Done";
		#(0.1);
		tb_HRESETn	= 1'b1;

		tb_HREADY = 0;
		tb_HRDATA = '0;
		tb_mode = 2'b00;
		tb_wdata = '1;
		tb_pixNum = 311;
		tb_image_startAddr = '0;
		tb_size = 2'b10;
		tb_image_width = 640;
		tb_image_height = 480;

		#(CLK_PERIOD * 1);

		tb_HRDATA = 3748897;
		tb_HREADY = 1;
		tb_startAddr_sel = 1;


		#(CLK_PERIOD);
		if(tb_rdata == tb_HRDATA)
		begin
			$info("State changes correctly in %s test case", tb_test_case);
		end
		else
		begin
			$error("State does not change correctly in %s test case", tb_test_case);
		end



		



	end

endmodule
module tb_AHB_master();



	localparam CLK_PERIOD 	= 35;
	localparam CLK_DELAY 	= 30;
	localparam RESET_VALUE  = 0;


	reg tb_HRESETn,tb_HCLK,tb_HREADY, tb_startAddr_sel, tb_HWRITE, tb_data_feedback;
	reg [31:0] tb_HRDATA, tb_wdata, tb_HADDR, tb_HWDATA, tb_rdata;
	reg [1:0] tb_mode, tb_size, tb_HSIZE;
	reg [11:0]tb_image_width, tb_image_height;
	reg [19:0] tb_pixNum, tb_image_startAddr;



	integer tb_test_num;
	string tb_test_case;


	always
	begin
		tb_HCLK = 1'b0;
		#(CLK_PERIOD/2.0);
		tb_HCLK = 1'b1;
		#(CLK_PERIOD/2.0);
	end
	

	AHB_master DUT(
		.clk(tb_HCLK),
		.n_rst(tb_HRESETn),
		.HREADY(tb_HREADY),
		.HRDATA(tb_HRDATA),
		.mode(tb_mode),
		.wdata(tb_wdata),
		.pixNum(tb_pixNum),
		.image_startAddr(tb_image_startAddr),
		.size(tb_size),
		.image_width(tb_image_width),
		.image_height(tb_image_height),
		.startAddr_sel(tb_startAddr_sel),
		.HADDR(tb_HADDR),
		.HWDATA(tb_HWDATA),
		.HWRITE(tb_HWRITE),
		.HSIZE(tb_HSIZE),
		.data_feedback(tb_data_feedback),
		.rdata(tb_rdata)
	);
	

	initial 
	begin
		

		tb_HRESETn	= 1'b1;
		tb_test_num = 0;
		tb_HREADY = 1;
		tb_HRDATA = '0;
		tb_mode = '0;
		tb_wdata = '0;
		tb_pixNum = '0;
		tb_image_startAddr = '0;
		tb_size = '0;
		tb_image_width = 640;
		tb_image_height = 480;
		tb_startAddr_sel = 0;

		#(0.1);

		#(CLK_PERIOD * 10);


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Reset everything";
		#(0.1);
		tb_HRESETn	= 1'b0;

		#(CLK_PERIOD * 0.5);


		#(CLK_PERIOD);
		if((tb_HWRITE == RESET_VALUE) && (tb_HSIZE == RESET_VALUE) && (tb_HWDATA == RESET_VALUE) && (tb_rdata == RESET_VALUE) && (tb_data_feedback == RESET_VALUE) && (tb_HADDR[31:28] == RESET_VALUE))
		begin
			$info("Reset done in %s test case", tb_test_case);
		end
		else
		begin
			$error("Reset not done in %s test case", tb_test_case);
		end

		


		tb_test_num = tb_test_num + 1;
		tb_test_case = "Read Instruction";
		#(0.1);
		tb_HRESETn	= 1'b1;

		tb_HREADY = 1;
		tb_HRDATA = '0;
		tb_mode = 2'b01;
		tb_wdata = '1;
		tb_pixNum = 311;
		tb_image_startAddr = '0;
		tb_size = 2'b10;
		tb_image_width = 640;
		tb_image_height = 480;
		tb_startAddr_sel = 0;

		#(CLK_PERIOD * 1);

		tb_HREADY = 0;

		#(CLK_PERIOD * 1);


		#(CLK_PERIOD);
		if(tb_HSIZE == tb_size)
		begin
			$info("State changes correctly in %s test case", tb_test_case);
		end
		else
		begin
			$error("State does not change correctly in %s test case", tb_test_case);
		end

	

		tb_test_num = tb_test_num + 1;
		tb_test_case = "Read Done";
		#(0.1);
		tb_HRESETn	= 1'b1;

		tb_HREADY = 0;
		tb_HRDATA = '0;
		tb_mode = 2'b00;
		tb_wdata = '1;
		tb_pixNum = 311;
		tb_image_startAddr = '0;
		tb_size = 2'b10;
		tb_image_width = 640;
		tb_image_height = 480;

		#(CLK_PERIOD * 1);

		tb_HRDATA = 3748897;
		tb_HREADY = 1;
		tb_startAddr_sel = 1;


		#(CLK_PERIOD);
		if(tb_rdata == tb_HRDATA)
		begin
			$info("State changes correctly in %s test case", tb_test_case);
		end
		else
		begin
			$error("State does not change correctly in %s test case", tb_test_case);
		end



		



	end

endmodule