data/full_repos/permissive/143278/ivltests/packeda2.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/packeda2.v:12: Unsupported: Ignoring delay on this delayed statement.\n      #0;  \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire logic [3:0][7:0] foo;

   genvar idx;
   for (idx = 0 ; idx <= 3 ; idx = idx+1) begin: test
      test dut (.sum(foo[idx]), .a(idx));
   end

   logic [7:0] tmp;
   initial begin
      #0;
      for (tmp = 0 ; tmp <= 3 ; tmp = tmp+1) begin




	 if (foo[tmp] !== (tmp+8'd5)) begin
	    $display("FAILED -- foo[%d] = %b", tmp, foo[tmp]);
	    $finish;
	 end
      end
      $display("PASSED");
   end

endmodule
module main;


   wire logic [3:0][7:0] foo;

   genvar idx;
   for (idx = 0 ; idx <= 3 ; idx = idx+1) begin: test
      test dut (.sum(foo[idx]), .a(idx));
   end

   logic [7:0] tmp;
   initial begin
      #0;
      for (tmp = 0 ; tmp <= 3 ; tmp = tmp+1) begin




	 if (foo[tmp] !== (tmp+8'd5)) begin
	    $display("FAILED -- foo[%d] = %b", tmp, foo[tmp]);
	    $finish;
	 end
      end
      $display("PASSED");
   end

endmodule