data/full_repos/permissive/202237519/verilog/ripple_carry_adder/full_adder.v
1: b'%Error: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/full_adder.v:1: Cannot find include file: half_adder.v\n`include "half_adder.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/ripple_carry_adder,data/full_repos/permissive/202237519/half_adder.v\n             data/full_repos/permissive/202237519/verilog/ripple_carry_adder,data/full_repos/permissive/202237519/half_adder.v.v\n             data/full_repos/permissive/202237519/verilog/ripple_carry_adder,data/full_repos/permissive/202237519/half_adder.v.sv\n             half_adder.v\n             half_adder.v.v\n             half_adder.v.sv\n             obj_dir/half_adder.v\n             obj_dir/half_adder.v.v\n             obj_dir/half_adder.v.sv\n%Error: Exiting due to 1 error(s)\n'
module full_adder (A,B,Cin,Cout,S);

input A, B, Cin;
output Cout, S;
wire xor_out, half_out, and_out;

xor xor0(xor_out,A,B);
or or0(Cout,half_out,and_out);
half_adder h0(S,half_out,xor_out,Cin);
and and0(and_out,A,B);

endmodule
module full_adder (A,B,Cin,Cout,S);


input A, B, Cin;
output Cout, S;
wire xor_out, half_out, and_out;

xor xor0(xor_out,A,B);
or or0(Cout,half_out,and_out);
half_adder h0(S,half_out,xor_out,Cin);
and and0(and_out,A,B);

endmodule