data/full_repos/permissive/219219909/Radix-5/test/test3.v
 line:77: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/219219909/Radix-5/test/test3.v:77: Unsupported: Ignoring delay on this delayed statement.\n#1000 $stop;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/219219909/Radix-5/test/test3.v:80: Unsupported: Ignoring delay on this delayed statement.\n#n clk=~clk;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219219909/Radix-5/test/test3.v:96: Unsupported: Ignoring delay on this delayed statement.\n#(2*n) a_re=32\'hc142a3d7;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219219909/Radix-5/test/test3.v:107: Unsupported: Ignoring delay on this delayed statement.\n#(2*n) a_re=32\'hbf491a30;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219219909/Radix-5/test/test3.v:118: Unsupported: Ignoring delay on this delayed statement.\n#(2*n) a_re=32\'hc23cc097;\n^\n%Error: data/full_repos/permissive/219219909/Radix-5/test/test3.v:52: Cannot find file containing module: \'Radix_5\'\n Radix_5 uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219219909/Radix-5/test,data/full_repos/permissive/219219909/Radix_5\n             data/full_repos/permissive/219219909/Radix-5/test,data/full_repos/permissive/219219909/Radix_5.v\n             data/full_repos/permissive/219219909/Radix-5/test,data/full_repos/permissive/219219909/Radix_5.sv\n             Radix_5\n             Radix_5.v\n             Radix_5.sv\n             obj_dir/Radix_5\n             obj_dir/Radix_5.v\n             obj_dir/Radix_5.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test3;
parameter n=5;

	reg [31:0] a_re;
	reg [31:0] b_re;
	reg [31:0] c_re;
	reg [31:0] d_re;
	reg [31:0] e_re;
	reg [31:0] a_img;
	reg [31:0] b_img;
	reg [31:0] c_img;
	reg [31:0] d_img;
	reg [31:0] e_img;
	reg clk;


	wire [31:0] a_1_re;
	wire [31:0] b_1_re;
	wire [31:0] c_1_re;
	wire [31:0] d_1_re;
	wire [31:0] e_1_re;
	wire [31:0] a_1_img;
	wire [31:0] b_1_img;
	wire [31:0] c_1_img;
	wire [31:0] d_1_img;
	wire [31:0] e_1_img;

	Radix_5 uut (
		.a_re(a_re), 
		.b_re(b_re), 
		.c_re(c_re),
		.d_re(d_re),
		.e_re(e_re),
		.a_img(a_img), 
		.b_img(b_img), 
		.c_img(c_img),
		.d_img(d_img),
		.e_img(e_img),
		.ao_re(a_1_re), 
		.bo_re(b_1_re), 
		.co_re(c_1_re),
		.do_re(d_1_re),
		.eo_re(e_1_re),
		.ao_img(a_1_img), 
		.bo_img(b_1_img), 
		.co_img(c_1_img), 
		.do_img(d_1_img),
		.eo_img(e_1_img),
		.clk(clk)
	);
initial begin
      clk=1;
#1000 $stop;
end
always begin
#n clk=~clk;
end

	initial begin

a_re=32'h3f491a30;
b_re=32'h3f15c290;
c_re=32'hc14c0000;
d_re=32'hc1361234;
e_re=32'hc0341a18;
a_img=32'h4246570a;
b_img=32'hc14c0000;
c_img=32'h4246570a;
d_img=32'h42acd70a;
e_img=32'h42a5ed71;

#(2*n) a_re=32'hc142a3d7;
b_re=32'h41555c29;
c_re=32'hc1361234;
d_re=32'h40dbc71d;
e_re=32'hc13905ea;
a_img=32'h4213570a;
b_img=32'hc279570a;
c_img=32'h42acd70a;
d_img=32'h41f9570a;
e_img=32'h4258397a;

#(2*n) a_re=32'hbf491a30;
b_re=32'h3f15c290;
c_re=32'h414c0000;
d_re=32'hc1361234;
e_re=32'h40341a18;
a_img=32'hc1361234;
b_img=32'h414c0000;
c_img=32'hc246570a;
d_img=32'hc2acd70a;
e_img=32'h419dd415;

#(2*n) a_re=32'hc23cc097;
b_re=32'hbf15c290;
c_re=32'h422b6cff;
d_re=32'h41361234;
e_re=32'hc0341a18;
a_img=32'h4246570a;
b_img=32'hc14c0000;
c_img=32'h4246570a;
d_img=32'h42acd70a;
e_img=32'h42a5ed71;
end
endmodule
module test3;

parameter n=5;

	reg [31:0] a_re;
	reg [31:0] b_re;
	reg [31:0] c_re;
	reg [31:0] d_re;
	reg [31:0] e_re;
	reg [31:0] a_img;
	reg [31:0] b_img;
	reg [31:0] c_img;
	reg [31:0] d_img;
	reg [31:0] e_img;
	reg clk;


	wire [31:0] a_1_re;
	wire [31:0] b_1_re;
	wire [31:0] c_1_re;
	wire [31:0] d_1_re;
	wire [31:0] e_1_re;
	wire [31:0] a_1_img;
	wire [31:0] b_1_img;
	wire [31:0] c_1_img;
	wire [31:0] d_1_img;
	wire [31:0] e_1_img;

	Radix_5 uut (
		.a_re(a_re), 
		.b_re(b_re), 
		.c_re(c_re),
		.d_re(d_re),
		.e_re(e_re),
		.a_img(a_img), 
		.b_img(b_img), 
		.c_img(c_img),
		.d_img(d_img),
		.e_img(e_img),
		.ao_re(a_1_re), 
		.bo_re(b_1_re), 
		.co_re(c_1_re),
		.do_re(d_1_re),
		.eo_re(e_1_re),
		.ao_img(a_1_img), 
		.bo_img(b_1_img), 
		.co_img(c_1_img), 
		.do_img(d_1_img),
		.eo_img(e_1_img),
		.clk(clk)
	);
initial begin
      clk=1;
#1000 $stop;
end
always begin
#n clk=~clk;
end

	initial begin

a_re=32'h3f491a30;
b_re=32'h3f15c290;
c_re=32'hc14c0000;
d_re=32'hc1361234;
e_re=32'hc0341a18;
a_img=32'h4246570a;
b_img=32'hc14c0000;
c_img=32'h4246570a;
d_img=32'h42acd70a;
e_img=32'h42a5ed71;

#(2*n) a_re=32'hc142a3d7;
b_re=32'h41555c29;
c_re=32'hc1361234;
d_re=32'h40dbc71d;
e_re=32'hc13905ea;
a_img=32'h4213570a;
b_img=32'hc279570a;
c_img=32'h42acd70a;
d_img=32'h41f9570a;
e_img=32'h4258397a;

#(2*n) a_re=32'hbf491a30;
b_re=32'h3f15c290;
c_re=32'h414c0000;
d_re=32'hc1361234;
e_re=32'h40341a18;
a_img=32'hc1361234;
b_img=32'h414c0000;
c_img=32'hc246570a;
d_img=32'hc2acd70a;
e_img=32'h419dd415;

#(2*n) a_re=32'hc23cc097;
b_re=32'hbf15c290;
c_re=32'h422b6cff;
d_re=32'h41361234;
e_re=32'hc0341a18;
a_img=32'h4246570a;
b_img=32'hc14c0000;
c_img=32'h4246570a;
d_img=32'h42acd70a;
e_img=32'h42a5ed71;
end
endmodule