data/full_repos/permissive/127883252/sim/tb/tb.v
 line:55: before: "rst_n"
1: b'%Warning-STMTDLY: data/full_repos/permissive/127883252/sim/tb/tb.v:46: Unsupported: Ignoring delay on this delayed statement.\nalways #(1000/2) clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/127883252/sim/tb/tb.v:55: syntax error, unexpected \'*\'\n    #100*CLOCK_CYCLE rst_n = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/127883252/sim/tb/tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #100*CLOCK_CYCLE rst_n = 1;\n    ^\n%Error: data/full_repos/permissive/127883252/sim/tb/tb.v:68: syntax error, unexpected \'*\'\n    #500*CLOCK_CYCLE sw = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/127883252/sim/tb/tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #500*CLOCK_CYCLE sw = 1;\n    ^\n%Error: data/full_repos/permissive/127883252/sim/tb/tb.v:69: syntax error, unexpected \'*\'\n    #500*CLOCK_CYCLE sw = 2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/127883252/sim/tb/tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #500*CLOCK_CYCLE sw = 2;\n    ^\n%Error: data/full_repos/permissive/127883252/sim/tb/tb.v:70: syntax error, unexpected \'*\'\n    #500*CLOCK_CYCLE sw = 3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/127883252/sim/tb/tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #500*CLOCK_CYCLE sw = 3;\n    ^\n%Error: data/full_repos/permissive/127883252/sim/tb/tb.v:71: syntax error, unexpected \'*\'\n    #500*CLOCK_CYCLE sw = 2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/127883252/sim/tb/tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #500*CLOCK_CYCLE sw = 2;\n    ^\n%Error: data/full_repos/permissive/127883252/sim/tb/tb.v:72: syntax error, unexpected \'*\'\n    #500*CLOCK_CYCLE sw = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/127883252/sim/tb/tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #500*CLOCK_CYCLE sw = 1;\n    ^\n%Error: data/full_repos/permissive/127883252/sim/tb/tb.v:73: syntax error, unexpected \'*\'\n    #500*CLOCK_CYCLE sw = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/127883252/sim/tb/tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #500*CLOCK_CYCLE sw = 0;\n    ^\n%Error: data/full_repos/permissive/127883252/sim/tb/tb.v:74: syntax error, unexpected \'*\'\n    #500*CLOCK_CYCLE sw = 3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/127883252/sim/tb/tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #500*CLOCK_CYCLE sw = 3;\n    ^\n%Error: data/full_repos/permissive/127883252/sim/tb/tb.v:75: syntax error, unexpected \'*\'\n    #500*CLOCK_CYCLE sw = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/127883252/sim/tb/tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #500*CLOCK_CYCLE sw = 1;\n    ^\n%Error: data/full_repos/permissive/127883252/sim/tb/tb.v:76: syntax error, unexpected \'*\'\n    #500*CLOCK_CYCLE sw = 2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/127883252/sim/tb/tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #500*CLOCK_CYCLE sw = 2;\n    ^\n%Error: data/full_repos/permissive/127883252/sim/tb/tb.v:77: syntax error, unexpected \'*\'\n    #500*CLOCK_CYCLE sw = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/127883252/sim/tb/tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #500*CLOCK_CYCLE sw = 0;\n    ^\n%Error: Exiting due to 11 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;







reg clk;
reg rst_n;

initial begin
    clk = 0;
end


always #(`CLOCK_CYCLE/2) clk=~clk;





task reset;
    begin
    rst_n = 0;
    #`RESET_PERIOD rst_n = 1;
    end
endtask





reg [1:0] sw;

initial begin
    sw = 0;
    reset;
    #500*CLOCK_CYCLE sw = 1;
    #500*CLOCK_CYCLE sw = 2;
    #500*CLOCK_CYCLE sw = 3;
    #500*CLOCK_CYCLE sw = 2;
    #500*CLOCK_CYCLE sw = 1;
    #500*CLOCK_CYCLE sw = 0;
    #500*CLOCK_CYCLE sw = 3;
    #500*CLOCK_CYCLE sw = 1;
    #500*CLOCK_CYCLE sw = 2;
    #500*CLOCK_CYCLE sw = 0;
end

mini_top u_DUT (
    .clk       ( clk    ) ,
    .rst_n     ( rst_n  ) ,
    .i_sw      ( sw     ) ,
    .o_led     (        ) 
);





`ifdef DUMP_FSDB 
initial begin
    $fsdbDumpfile("tb.fsdb");
    $fsdbDumpvars(0,tb);
    #`MAX_RUN_TIME
    $finish(2);
end
`endif

endmodule
module tb;








reg clk;
reg rst_n;

initial begin
    clk = 0;
end


always #(`CLOCK_CYCLE/2) clk=~clk;





task reset;
    begin
    rst_n = 0;
    #`RESET_PERIOD rst_n = 1;
    end
endtask





reg [1:0] sw;

initial begin
    sw = 0;
    reset;
    #500*CLOCK_CYCLE sw = 1;
    #500*CLOCK_CYCLE sw = 2;
    #500*CLOCK_CYCLE sw = 3;
    #500*CLOCK_CYCLE sw = 2;
    #500*CLOCK_CYCLE sw = 1;
    #500*CLOCK_CYCLE sw = 0;
    #500*CLOCK_CYCLE sw = 3;
    #500*CLOCK_CYCLE sw = 1;
    #500*CLOCK_CYCLE sw = 2;
    #500*CLOCK_CYCLE sw = 0;
end

mini_top u_DUT (
    .clk       ( clk    ) ,
    .rst_n     ( rst_n  ) ,
    .i_sw      ( sw     ) ,
    .o_led     (        ) 
);





`ifdef DUMP_FSDB 
initial begin
    $fsdbDumpfile("tb.fsdb");
    $fsdbDumpvars(0,tb);
    #`MAX_RUN_TIME
    $finish(2);
end
`endif

endmodule