data/full_repos/permissive/214325244/fsm.v
1: b"%Error: data/full_repos/permissive/214325244/fsm.v:51: Cannot find file containing module: 'counter'\ncounter timerNG(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214325244,data/full_repos/permissive/214325244/counter\n             data/full_repos/permissive/214325244,data/full_repos/permissive/214325244/counter.v\n             data/full_repos/permissive/214325244,data/full_repos/permissive/214325244/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: data/full_repos/permissive/214325244/fsm.v:60: Cannot find file containing module: 'counter'\ncounter timerEWG(\n^~~~~~~\n%Error: data/full_repos/permissive/214325244/fsm.v:67: Cannot find file containing module: 'counter'\ncounter timerYEL(\n^~~~~~~\n%Error: data/full_repos/permissive/214325244/fsm.v:74: Cannot find file containing module: 'counter'\ncounter timerRED(\n^~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module fsm(Clock, Reset, S1, S2, S3, L1, L2, L3);
input Clock;
input Reset;
input
S1,
S2,
S3;

output reg [1:0]
L1,
L2,
L3;


wire
	timer_ng,
	timer_ewg,
	timer_yellow,
	timer_red;

wire reset, load, decr, value;



parameter
	FS	= 6'b000001,
	REDL	= 6'b000010,
	NG	= 6'b000100,
	NY	= 6'b001000,
	EWG	= 6'b010000,
	EWY	= 6'b100000;



parameter
	FAIL	= 2'b00,
	GREEN	= 2'b01,
	YELLOW	= 2'b10,
	RED	= 2'b11;

reg [5:0] state;
reg [5:0] next_state;



counter timerNG(
		.clk(Clock),
		.reset(reset),
		.load(load),
		.decr(decr),
		.timeup(timer_ng),
		.value(value));
		

counter timerEWG(
		.clk(Clock),
		.reset(reset),
		.load(load),
		.decr(decr),
		.timeup(timer_ewg));

counter timerYEL(
		.clk(Clock),
		.reset(reset),
		.load(load),
		.decr(decr),
		.timeup(timer_yellow));

counter timerRED(
		.clk(Clock),
		.reset(reset),
		.load(load),
		.decr(decr),
		.timeup(timer_red));



always @(posedge Clock, posedge Reset)
begin
	if(Reset)
		state <= FS;
	else
		state <= next_state;
end

always @(state)
begin
	
	
	case(state)
		FS:	begin
			L1 = FAIL;
			L2 = FAIL;
			L3 = FAIL;
			end

		REDL:	begin
			L1 = RED;			
			L2 = RED;
			L3 = RED;
			end

		NG:	begin
			L1 = GREEN;			
			L2 = RED;
			L3 = RED;
			end


		NY:	begin
			L1 = YELLOW;			
			L2 = RED;
			L3 = RED;
			end


		EWG:	begin
			L1 = RED;			
			L2 = GREEN;
			L3 = GREEN;
			end

		EWY:	begin
			L1 = RED;			
			L2 = YELLOW;
			L3 = YELLOW;
			end
	endcase
end



always @(state, next_state)
begin
	case(state)
					

		REDL:	begin
			if(timer_red && S1)
				next_state = NG;

			else if(timer_red && ~S1 && (S2 || S3))
				next_state = EWG;

			else
				next_state = REDL;
			end
	 
		NG:	begin
			if(timer_ng && S1 && ~S2 && ~S3)
				next_state = NG;
			
			else if(timer_ng && ~S1 && (S2 || S3))
				next_state = NY;
			
			else
				next_state = NG;
			end


		NY:	begin
			if(timer_yellow)
				next_state = REDL;
			else
				next_state = NY;
			end


		EWG:	begin
			if(timer_ewg && ~S1 && (S2 || S3))
				next_state = EWG;
			
			else if(timer_ewg && S1)
				next_state = EWY;
			
			else
				next_state = EWY;
			end

		EWY:	begin
			if(timer_yellow)
				next_state = REDL;

			else
				next_state = EWY;
			end 
		
	endcase
end

endmodule
module fsm(Clock, Reset, S1, S2, S3, L1, L2, L3);

input Clock;
input Reset;
input
S1,
S2,
S3;

output reg [1:0]
L1,
L2,
L3;


wire
	timer_ng,
	timer_ewg,
	timer_yellow,
	timer_red;

wire reset, load, decr, value;



parameter
	FS	= 6'b000001,
	REDL	= 6'b000010,
	NG	= 6'b000100,
	NY	= 6'b001000,
	EWG	= 6'b010000,
	EWY	= 6'b100000;



parameter
	FAIL	= 2'b00,
	GREEN	= 2'b01,
	YELLOW	= 2'b10,
	RED	= 2'b11;

reg [5:0] state;
reg [5:0] next_state;



counter timerNG(
		.clk(Clock),
		.reset(reset),
		.load(load),
		.decr(decr),
		.timeup(timer_ng),
		.value(value));
		

counter timerEWG(
		.clk(Clock),
		.reset(reset),
		.load(load),
		.decr(decr),
		.timeup(timer_ewg));

counter timerYEL(
		.clk(Clock),
		.reset(reset),
		.load(load),
		.decr(decr),
		.timeup(timer_yellow));

counter timerRED(
		.clk(Clock),
		.reset(reset),
		.load(load),
		.decr(decr),
		.timeup(timer_red));



always @(posedge Clock, posedge Reset)
begin
	if(Reset)
		state <= FS;
	else
		state <= next_state;
end

always @(state)
begin
	
	
	case(state)
		FS:	begin
			L1 = FAIL;
			L2 = FAIL;
			L3 = FAIL;
			end

		REDL:	begin
			L1 = RED;			
			L2 = RED;
			L3 = RED;
			end

		NG:	begin
			L1 = GREEN;			
			L2 = RED;
			L3 = RED;
			end


		NY:	begin
			L1 = YELLOW;			
			L2 = RED;
			L3 = RED;
			end


		EWG:	begin
			L1 = RED;			
			L2 = GREEN;
			L3 = GREEN;
			end

		EWY:	begin
			L1 = RED;			
			L2 = YELLOW;
			L3 = YELLOW;
			end
	endcase
end



always @(state, next_state)
begin
	case(state)
					

		REDL:	begin
			if(timer_red && S1)
				next_state = NG;

			else if(timer_red && ~S1 && (S2 || S3))
				next_state = EWG;

			else
				next_state = REDL;
			end
	 
		NG:	begin
			if(timer_ng && S1 && ~S2 && ~S3)
				next_state = NG;
			
			else if(timer_ng && ~S1 && (S2 || S3))
				next_state = NY;
			
			else
				next_state = NG;
			end


		NY:	begin
			if(timer_yellow)
				next_state = REDL;
			else
				next_state = NY;
			end


		EWG:	begin
			if(timer_ewg && ~S1 && (S2 || S3))
				next_state = EWG;
			
			else if(timer_ewg && S1)
				next_state = EWY;
			
			else
				next_state = EWY;
			end

		EWY:	begin
			if(timer_yellow)
				next_state = REDL;

			else
				next_state = EWY;
			end 
		
	endcase
end

endmodule