data/full_repos/permissive/110372367/marioProj/FPU.v
 line:5: before: "shift"
1: b'%Error: data/full_repos/permissive/110372367/marioProj/FPU.v:5: syntax error, unexpected IDENTIFIER\nshift( dir ,\n^~~~~\n%Error: Exiting due to 1 error(s)\n'
module fpu(
    operand1 ,
    operand2 ,
    opcode   ,
    result   
    );


parameter S = 1 ;
parameter E = 8 ;
parameter M = 23;



input               opcode ;
input  [S+E+M-1:0]  op1    ;
input  [S+E+M-1:0]  op2    ;
output [S+E+M-1:0]  result ;

wire              opcode ;
wire [S+E+M-1:0]  op1    ;
wire [S+E+M-1:0]  op2    ;
wire [S+E+M-1:0]  result ;












sctrl #( .S(S), .E(E), .M(M)) fpu_sctrl (

    .opcode ( opcode ) ,
    .sdiff  ( sdiff  ) ,
    .s1     ( s1     ) ,
    .s2     ( s2     ) ,

    .inv1   ( inv1   ) ,
    .inv2   ( inv2   ) ,
    );


wire [M-1:0]    m1;
wire [M-1:0]    m2;

wire [M-1:0]    m1_muxed;
wire [M-1:0]    m2_muxed;

assign m1_muxed = (sdiff) ? m1 : m2;
assign m2_muxed = (sdiff) ? m2 : m1;


rshift #( .S(S), .E(E), .M(M)) fpu_rshift (
    .dir ( 0          ) ,
    .val ( rshift_val ) ,
    .in  ( m2_muxed   ) ,
    .out ( rshift_out )
    );


complement #( .S(S), .E(E), .M(M)) m1_complement (
    .enable ( inv1              ) ,
    .in     ( m1_muxed          ) ,
    .out    ( m1_complement_out )
);

complement #( .S(S), .E(E), .M(M)) m2_complement (
    .enable ( inv2              ) ,
    .in     ( rshift_out        ) ,
    .out    ( m2_complement_out )
);

endmodule
module fpu(
    operand1 ,
    operand2 ,
    opcode   ,
    result   
    );



parameter S = 1 ;
parameter E = 8 ;
parameter M = 23;



input               opcode ;
input  [S+E+M-1:0]  op1    ;
input  [S+E+M-1:0]  op2    ;
output [S+E+M-1:0]  result ;

wire              opcode ;
wire [S+E+M-1:0]  op1    ;
wire [S+E+M-1:0]  op2    ;
wire [S+E+M-1:0]  result ;












sctrl #( .S(S), .E(E), .M(M)) fpu_sctrl (

    .opcode ( opcode ) ,
    .sdiff  ( sdiff  ) ,
    .s1     ( s1     ) ,
    .s2     ( s2     ) ,

    .inv1   ( inv1   ) ,
    .inv2   ( inv2   ) ,
    );


wire [M-1:0]    m1;
wire [M-1:0]    m2;

wire [M-1:0]    m1_muxed;
wire [M-1:0]    m2_muxed;

assign m1_muxed = (sdiff) ? m1 : m2;
assign m2_muxed = (sdiff) ? m2 : m1;


rshift #( .S(S), .E(E), .M(M)) fpu_rshift (
    .dir ( 0          ) ,
    .val ( rshift_val ) ,
    .in  ( m2_muxed   ) ,
    .out ( rshift_out )
    );


complement #( .S(S), .E(E), .M(M)) m1_complement (
    .enable ( inv1              ) ,
    .in     ( m1_muxed          ) ,
    .out    ( m1_complement_out )
);

complement #( .S(S), .E(E), .M(M)) m2_complement (
    .enable ( inv2              ) ,
    .in     ( rshift_out        ) ,
    .out    ( m2_complement_out )
);

endmodule