data/full_repos/permissive/146618947/compuertas/libreria.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/libreria.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #(1.4:3:4.6) Q <= D;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/146618947/compuertas/libreria.v:114: Multiple top level modules\n                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                 : ... Top module \'flip_flop_delay\'\nmodule flip_flop_delay (\n       ^~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'mux_21_4_delay\'\nmodule mux_21_4_delay (\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_21_delay (
                     output reg Q,
                     input A,
                     input B,
                     input S,
                     input Reset_L
                     );

   parameter PwrC = 0.00003;

   wire                    nand_a_out,
                           selector_out,
                           nand_b_out,
                           a_and_b_not,
                           out_not,
                           out;

   nand_delay nand_a (A, !S, nand_a_out);

   nand_delay nand_b (B, S, nand_b_out);
   nand_delay a_and_b_not_ (nand_a_out, nand_b_out, a_and_b_not);
   nand_delay reset_out (a_and_b_not, Reset_L, out_not);
   not_delay out_ (out_not, out);

   always @ (out)
     begin
        Q <= out;
     end

















endmodule
module mux_21_delay (
                     output reg Q,
                     input A,
                     input B,
                     input S,
                     input Reset_L
                     );


   parameter PwrC = 0.00003;

   wire                    nand_a_out,
                           selector_out,
                           nand_b_out,
                           a_and_b_not,
                           out_not,
                           out;

   nand_delay nand_a (A, !S, nand_a_out);

   nand_delay nand_b (B, S, nand_b_out);
   nand_delay a_and_b_not_ (nand_a_out, nand_b_out, a_and_b_not);
   nand_delay reset_out (a_and_b_not, Reset_L, out_not);
   not_delay out_ (out_not, out);

   always @ (out)
     begin
        Q <= out;
     end

















endmodule