data/full_repos/permissive/172538466/hw/src/rstgen.v
None: at end of input
1: b'%Error: data/full_repos/permissive/172538466/hw/src/rstgen.v:1: Cannot find include file: defs.vh\n`include "defs.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh.v\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh.sv\n             defs.vh\n             defs.vh.v\n             defs.vh.sv\n             obj_dir/defs.vh\n             obj_dir/defs.vh.v\n             obj_dir/defs.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module rstgen
(
 input             CLK_I,
 input             RESET_I,
 output            RESET_O,
 output            RESET_N_O
 );

   reg [3:0]       rstv = 4'b1111;

   always @(posedge CLK_I, posedge RESET_I)
     if(RESET_I)
       rstv <= 4'b1111;
     else
       rstv <= rstv >> 1;

   reg             rst = 1'b1;
   reg             rst_n = 1'b0;

   always @(posedge CLK_I) begin
     rst <= rstv[0];
     rst_n <= ~rstv[0];
   end

   assign RESET_O = rst;
   assign RESET_N_O = rst_n;

endmodule
module rstgen
(
 input             CLK_I,
 input             RESET_I,
 output            RESET_O,
 output            RESET_N_O
 );


   reg [3:0]       rstv = 4'b1111;

   always @(posedge CLK_I, posedge RESET_I)
     if(RESET_I)
       rstv <= 4'b1111;
     else
       rstv <= rstv >> 1;

   reg             rst = 1'b1;
   reg             rst_n = 1'b0;

   always @(posedge CLK_I) begin
     rst <= rstv[0];
     rst_n <= ~rstv[0];
   end

   assign RESET_O = rst;
   assign RESET_N_O = rst_n;

endmodule