data/full_repos/permissive/167962127/quad_sine.v
data/verilator_xmls/ad7b0cd3-80eb-40ff-ab81-b29ac5fc7039.xml
module quad_sine(
  input i_clk,
  input [13:0] i_addr,
  output reg [15:0] o_data
);


  (* romstyle = "M9K" *)
  reg [15:0] r_lut [0:(2**14)-1];


  initial begin
    $readmemb("quad_lut.mem", r_lut);
  end

	always @ (posedge i_clk)
	begin
    o_data <= r_lut[i_addr[13:0]];
	end


endmodule
module quad_sine(
  input i_clk,
  input [13:0] i_addr,
  output reg [15:0] o_data
);



  (* romstyle = "M9K" *)
  reg [15:0] r_lut [0:(2**14)-1];


  initial begin
    $readmemb("quad_lut.mem", r_lut);
  end

	always @ (posedge i_clk)
	begin
    o_data <= r_lut[i_addr[13:0]];
	end


endmodule