data/full_repos/permissive/211316121/lab5_2/one_min.v
data/verilator_xmls/2bfdc64b-c298-4070-a7f3-08f87a9dec84.xml
module one_min(
input clk,
output reg onemin
    );
    parameter N=99_999999;
    reg [31:0] count;
    
    always @(posedge clk)
    begin
            onemin<=0;
            if(count<N) count<=count+1;
            else
            begin
                count<=0;
                onemin<=1;
        end
    end
         
endmodule
module one_min(
input clk,
output reg onemin
    );

    parameter N=99_999999;
    reg [31:0] count;
    
    always @(posedge clk)
    begin
            onemin<=0;
            if(count<N) count<=count+1;
            else
            begin
                count<=0;
                onemin<=1;
        end
    end
         
endmodule