data/full_repos/permissive/15946916/Lab6/lab6_3_test.v
 line:59: before: "$"
1: b'%Error: data/full_repos/permissive/15946916/Lab6/lab6_3_test.v:2: Cannot find include file: lab6_3.v\n`include "lab6_3.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/15946916/Lab6,data/full_repos/permissive/15946916/lab6_3.v\n             data/full_repos/permissive/15946916/Lab6,data/full_repos/permissive/15946916/lab6_3.v.v\n             data/full_repos/permissive/15946916/Lab6,data/full_repos/permissive/15946916/lab6_3.v.sv\n             lab6_3.v\n             lab6_3.v.v\n             lab6_3.v.sv\n             obj_dir/lab6_3.v\n             obj_dir/lab6_3.v.v\n             obj_dir/lab6_3.v.sv\n%Error: data/full_repos/permissive/15946916/Lab6/lab6_3_test.v:14: Unsupported or unknown PLI call: $monitor\n        $monitor ($time,"\\ta=%b\\tb=%b\\tcin=%b\\tsum=%b\\tcarry=%b",a,b,cin, S, Cout);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_3_test.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #1 \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_3_test.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_3_test.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_3_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #1 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_3_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #1 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_3_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_3_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_3_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module full_adder_test();
    reg    a, b, cin;
    wire   S, Cout;

    full_adder test(S,Cout,a,b,cin);

    initial begin
        $monitor ($time,"\ta=%b\tb=%b\tcin=%b\tsum=%b\tcarry=%b",a,b,cin, S, Cout);
		
        a = 0; b = 0; cin=0;
        #1 
         a = 0; b = 0; cin=1;
        #1
         a = 0; b = 1; cin=0;
        #1
         a = 0; b = 1; cin=1;
        #1 
		 a = 1; b = 0; cin=0;
        #1 
         a = 1; b = 0; cin=1;
        #1
         a = 1; b = 1; cin=0;
        #1
         a = 1; b = 1; cin=1;
		#1
        $finish;
    end
endmodule
module full_adder_test();

    reg    a, b, cin;
    wire   S, Cout;

    full_adder test(S,Cout,a,b,cin);

    initial begin
        $monitor ($time,"\ta=%b\tb=%b\tcin=%b\tsum=%b\tcarry=%b",a,b,cin, S, Cout);
		
        a = 0; b = 0; cin=0;
        #1 
         a = 0; b = 0; cin=1;
        #1
         a = 0; b = 1; cin=0;
        #1
         a = 0; b = 1; cin=1;
        #1 
		 a = 1; b = 0; cin=0;
        #1 
         a = 1; b = 0; cin=1;
        #1
         a = 1; b = 1; cin=0;
        #1
         a = 1; b = 1; cin=1;
		#1
        $finish;
    end
endmodule