data/full_repos/permissive/184332405/adder_subtractor.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/184332405/adder_subtractor.v:26: Cannot find file containing module: 'full_adder'\nfull_adder a0(s[0], carry[0], a[0], bxor[0], op);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/184332405,data/full_repos/permissive/184332405/full_adder\n             data/full_repos/permissive/184332405,data/full_repos/permissive/184332405/full_adder.v\n             data/full_repos/permissive/184332405,data/full_repos/permissive/184332405/full_adder.sv\n             full_adder\n             full_adder.v\n             full_adder.sv\n             obj_dir/full_adder\n             obj_dir/full_adder.v\n             obj_dir/full_adder.sv\n%Error: data/full_repos/permissive/184332405/adder_subtractor.v:27: Cannot find file containing module: 'full_adder'\nfull_adder a1(s[1], carry[1], a[1], bxor[1], carry[0]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/184332405/adder_subtractor.v:28: Cannot find file containing module: 'full_adder'\nfull_adder a2(s[2], carry[2], a[2], bxor[2], carry[1]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/184332405/adder_subtractor.v:29: Cannot find file containing module: 'full_adder'\nfull_adder a3(s[3], carry[3], a[3], bxor[3], carry[2]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/184332405/adder_subtractor.v:30: Cannot find file containing module: 'full_adder'\nfull_adder a4(s[4], carry[4], a[4], bxor[4], carry[3]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/184332405/adder_subtractor.v:31: Cannot find file containing module: 'full_adder'\nfull_adder a5(s[5], carry[5], a[5], bxor[5], carry[4]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/184332405/adder_subtractor.v:32: Cannot find file containing module: 'full_adder'\nfull_adder a6(s[6], carry[6], a[6], bxor[6], carry[5]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/184332405/adder_subtractor.v:33: Cannot find file containing module: 'full_adder'\nfull_adder a7(s[7], last_cout,a[7], bxor[7], carry[6]);\n^~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module adder_subtractor( s, overflow, a, b, op);
input  signed [7:0] a;
input  signed [7:0] b;
output signed [7:0] s;
output overflow;
input  op;


wire [6:0] carry;
wire [7:0] bxor;
wire last_cout;


xor(bxor[0], b[0], op);
xor(bxor[1], b[1], op);
xor(bxor[2], b[2], op);
xor(bxor[3], b[3], op);
xor(bxor[4], b[4], op);
xor(bxor[5], b[5], op);
xor(bxor[6], b[6], op);
xor(bxor[7], b[7], op);


full_adder a0(s[0], carry[0], a[0], bxor[0], op);
full_adder a1(s[1], carry[1], a[1], bxor[1], carry[0]);
full_adder a2(s[2], carry[2], a[2], bxor[2], carry[1]);
full_adder a3(s[3], carry[3], a[3], bxor[3], carry[2]);
full_adder a4(s[4], carry[4], a[4], bxor[4], carry[3]);
full_adder a5(s[5], carry[5], a[5], bxor[5], carry[4]);
full_adder a6(s[6], carry[6], a[6], bxor[6], carry[5]);
full_adder a7(s[7], last_cout,a[7], bxor[7], carry[6]);


xor(overflow, carry[6], last_cout);

endmodule
module adder_subtractor( s, overflow, a, b, op);

input  signed [7:0] a;
input  signed [7:0] b;
output signed [7:0] s;
output overflow;
input  op;


wire [6:0] carry;
wire [7:0] bxor;
wire last_cout;


xor(bxor[0], b[0], op);
xor(bxor[1], b[1], op);
xor(bxor[2], b[2], op);
xor(bxor[3], b[3], op);
xor(bxor[4], b[4], op);
xor(bxor[5], b[5], op);
xor(bxor[6], b[6], op);
xor(bxor[7], b[7], op);


full_adder a0(s[0], carry[0], a[0], bxor[0], op);
full_adder a1(s[1], carry[1], a[1], bxor[1], carry[0]);
full_adder a2(s[2], carry[2], a[2], bxor[2], carry[1]);
full_adder a3(s[3], carry[3], a[3], bxor[3], carry[2]);
full_adder a4(s[4], carry[4], a[4], bxor[4], carry[3]);
full_adder a5(s[5], carry[5], a[5], bxor[5], carry[4]);
full_adder a6(s[6], carry[6], a[6], bxor[6], carry[5]);
full_adder a7(s[7], last_cout,a[7], bxor[7], carry[6]);


xor(overflow, carry[6], last_cout);

endmodule