data/full_repos/permissive/159016511/src/rtl/ahb/ahb2apb.v
1: b"%Error: data/full_repos/permissive/159016511/src/rtl/ahb/ahb2apb.v:111: Cannot find file containing module: 'COREAHBTOAPB3'\nCOREAHBTOAPB3 #( \n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159016511/src/rtl/ahb,data/full_repos/permissive/159016511/COREAHBTOAPB3\n             data/full_repos/permissive/159016511/src/rtl/ahb,data/full_repos/permissive/159016511/COREAHBTOAPB3.v\n             data/full_repos/permissive/159016511/src/rtl/ahb,data/full_repos/permissive/159016511/COREAHBTOAPB3.sv\n             COREAHBTOAPB3\n             COREAHBTOAPB3.v\n             COREAHBTOAPB3.sv\n             obj_dir/COREAHBTOAPB3\n             obj_dir/COREAHBTOAPB3.v\n             obj_dir/COREAHBTOAPB3.sv\n%Error: Exiting due to 1 error(s)\n"
module ahb2apb(

    HADDR,
    HCLK,
    HREADY,
    HRESETN,
    HSEL,
    HTRANS,
    HWDATA,
    HWRITE,
    PRDATA,
    PREADY,
    PSLVERR,

    HRDATA,
    HREADYOUT,
    HRESP,
    PADDR,
    PENABLE,
    PSEL,
    PWDATA,
    PWRITE
);




input  [31:0] HADDR;
input         HCLK;
input         HREADY;
input         HRESETN;
input         HSEL;
input  [1:0]  HTRANS;
input  [31:0] HWDATA;
input         HWRITE;
input  [31:0] PRDATA;
input         PREADY;
input         PSLVERR;



output [31:0] HRDATA;
output        HREADYOUT;
output [1:0]  HRESP;
output [31:0] PADDR;
output        PENABLE;
output        PSEL;
output [31:0] PWDATA;
output        PWRITE;



wire   [31:0] HADDR;
wire   [31:0] AHBslave_HRDATA;
wire          HREADY;
wire          AHBslave_HREADYOUT;
wire   [1:0]  AHBslave_HRESP;
wire          HSEL;
wire   [1:0]  HTRANS;
wire   [31:0] HWDATA;
wire          HWRITE;
wire   [31:0] APBmaster_PADDR;
wire          APBmaster_PENABLE;
wire   [31:0] PRDATA;
wire          PREADY;
wire          APBmaster_PSELx;
wire          PSLVERR;
wire   [31:0] APBmaster_PWDATA;
wire          APBmaster_PWRITE;
wire          HCLK;
wire          HRESETN;
wire          AHBslave_HREADYOUT_net_0;
wire          APBmaster_PSELx_net_0;
wire          APBmaster_PENABLE_net_0;
wire          APBmaster_PWRITE_net_0;
wire   [31:0] AHBslave_HRDATA_net_0;
wire   [1:0]  AHBslave_HRESP_net_0;
wire   [31:0] APBmaster_PADDR_net_0;
wire   [31:0] APBmaster_PWDATA_net_0;



assign AHBslave_HREADYOUT_net_0 = AHBslave_HREADYOUT;
assign HREADYOUT                = AHBslave_HREADYOUT_net_0;
assign APBmaster_PSELx_net_0    = APBmaster_PSELx;
assign PSEL                     = APBmaster_PSELx_net_0;
assign APBmaster_PENABLE_net_0  = APBmaster_PENABLE;
assign PENABLE                  = APBmaster_PENABLE_net_0;
assign APBmaster_PWRITE_net_0   = APBmaster_PWRITE;
assign PWRITE                   = APBmaster_PWRITE_net_0;
assign AHBslave_HRDATA_net_0    = AHBslave_HRDATA;
assign HRDATA[31:0]             = AHBslave_HRDATA_net_0;
assign AHBslave_HRESP_net_0     = AHBslave_HRESP;
assign HRESP[1:0]               = AHBslave_HRESP_net_0;
assign APBmaster_PADDR_net_0    = APBmaster_PADDR;
assign PADDR[31:0]              = APBmaster_PADDR_net_0;
assign APBmaster_PWDATA_net_0   = APBmaster_PWDATA;
assign PWDATA[31:0]             = APBmaster_PWDATA_net_0;




COREAHBTOAPB3 #( 
        .FAMILY ( 19 ) )
ahb2apb_0(

        .HCLK      ( HCLK ),
        .HRESETN   ( HRESETN ),
        .HWRITE    ( HWRITE ),
        .HSEL      ( HSEL ),
        .HREADY    ( HREADY ),
        .PREADY    ( PREADY ),
        .PSLVERR   ( PSLVERR ),
        .HADDR     ( HADDR ),
        .HTRANS    ( HTRANS ),
        .HWDATA    ( HWDATA ),
        .PRDATA    ( PRDATA ),

        .HREADYOUT ( AHBslave_HREADYOUT ),
        .PENABLE   ( APBmaster_PENABLE ),
        .PWRITE    ( APBmaster_PWRITE ),
        .PSEL      ( APBmaster_PSELx ),
        .HRDATA    ( AHBslave_HRDATA ),
        .HRESP     ( AHBslave_HRESP ),
        .PWDATA    ( APBmaster_PWDATA ),
        .PADDR     ( APBmaster_PADDR ) 
        );


endmodule
module ahb2apb(

    HADDR,
    HCLK,
    HREADY,
    HRESETN,
    HSEL,
    HTRANS,
    HWDATA,
    HWRITE,
    PRDATA,
    PREADY,
    PSLVERR,

    HRDATA,
    HREADYOUT,
    HRESP,
    PADDR,
    PENABLE,
    PSEL,
    PWDATA,
    PWRITE
);





input  [31:0] HADDR;
input         HCLK;
input         HREADY;
input         HRESETN;
input         HSEL;
input  [1:0]  HTRANS;
input  [31:0] HWDATA;
input         HWRITE;
input  [31:0] PRDATA;
input         PREADY;
input         PSLVERR;



output [31:0] HRDATA;
output        HREADYOUT;
output [1:0]  HRESP;
output [31:0] PADDR;
output        PENABLE;
output        PSEL;
output [31:0] PWDATA;
output        PWRITE;



wire   [31:0] HADDR;
wire   [31:0] AHBslave_HRDATA;
wire          HREADY;
wire          AHBslave_HREADYOUT;
wire   [1:0]  AHBslave_HRESP;
wire          HSEL;
wire   [1:0]  HTRANS;
wire   [31:0] HWDATA;
wire          HWRITE;
wire   [31:0] APBmaster_PADDR;
wire          APBmaster_PENABLE;
wire   [31:0] PRDATA;
wire          PREADY;
wire          APBmaster_PSELx;
wire          PSLVERR;
wire   [31:0] APBmaster_PWDATA;
wire          APBmaster_PWRITE;
wire          HCLK;
wire          HRESETN;
wire          AHBslave_HREADYOUT_net_0;
wire          APBmaster_PSELx_net_0;
wire          APBmaster_PENABLE_net_0;
wire          APBmaster_PWRITE_net_0;
wire   [31:0] AHBslave_HRDATA_net_0;
wire   [1:0]  AHBslave_HRESP_net_0;
wire   [31:0] APBmaster_PADDR_net_0;
wire   [31:0] APBmaster_PWDATA_net_0;



assign AHBslave_HREADYOUT_net_0 = AHBslave_HREADYOUT;
assign HREADYOUT                = AHBslave_HREADYOUT_net_0;
assign APBmaster_PSELx_net_0    = APBmaster_PSELx;
assign PSEL                     = APBmaster_PSELx_net_0;
assign APBmaster_PENABLE_net_0  = APBmaster_PENABLE;
assign PENABLE                  = APBmaster_PENABLE_net_0;
assign APBmaster_PWRITE_net_0   = APBmaster_PWRITE;
assign PWRITE                   = APBmaster_PWRITE_net_0;
assign AHBslave_HRDATA_net_0    = AHBslave_HRDATA;
assign HRDATA[31:0]             = AHBslave_HRDATA_net_0;
assign AHBslave_HRESP_net_0     = AHBslave_HRESP;
assign HRESP[1:0]               = AHBslave_HRESP_net_0;
assign APBmaster_PADDR_net_0    = APBmaster_PADDR;
assign PADDR[31:0]              = APBmaster_PADDR_net_0;
assign APBmaster_PWDATA_net_0   = APBmaster_PWDATA;
assign PWDATA[31:0]             = APBmaster_PWDATA_net_0;




COREAHBTOAPB3 #( 
        .FAMILY ( 19 ) )
ahb2apb_0(

        .HCLK      ( HCLK ),
        .HRESETN   ( HRESETN ),
        .HWRITE    ( HWRITE ),
        .HSEL      ( HSEL ),
        .HREADY    ( HREADY ),
        .PREADY    ( PREADY ),
        .PSLVERR   ( PSLVERR ),
        .HADDR     ( HADDR ),
        .HTRANS    ( HTRANS ),
        .HWDATA    ( HWDATA ),
        .PRDATA    ( PRDATA ),

        .HREADYOUT ( AHBslave_HREADYOUT ),
        .PENABLE   ( APBmaster_PENABLE ),
        .PWRITE    ( APBmaster_PWRITE ),
        .PSEL      ( APBmaster_PSELx ),
        .HRDATA    ( AHBslave_HRDATA ),
        .HRESP     ( AHBslave_HRESP ),
        .PWDATA    ( APBmaster_PWDATA ),
        .PADDR     ( APBmaster_PADDR ) 
        );


endmodule