data/full_repos/permissive/18477150/lib/sonic/xcvr_xg/misc/avalon_mm_master/latency_aware_read_master.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/18477150/lib/sonic/xcvr_xg/misc/avalon_mm_master/latency_aware_read_master.v:331: Cannot find file containing module: 'scfifo'\n scfifo the_master_to_user_fifo (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18477150/lib/sonic/xcvr_xg/misc/avalon_mm_master,data/full_repos/permissive/18477150/scfifo\n             data/full_repos/permissive/18477150/lib/sonic/xcvr_xg/misc/avalon_mm_master,data/full_repos/permissive/18477150/scfifo.v\n             data/full_repos/permissive/18477150/lib/sonic/xcvr_xg/misc/avalon_mm_master,data/full_repos/permissive/18477150/scfifo.sv\n             scfifo\n             scfifo.v\n             scfifo.sv\n             obj_dir/scfifo\n             obj_dir/scfifo.v\n             obj_dir/scfifo.sv\n%Error: Exiting due to 1 error(s)\n"
module latency_aware_read_master (
	clk,
	reset,


	avs_csr_address,
	avs_csr_readdata,
	avs_csr_write,
	avs_csr_read,
	avs_csr_writedata,


	master_address,
	master_read,
	master_byteenable,
	master_readdata,
	master_readdatavalid,
	master_waitrequest
);

	parameter DATAWIDTH = 32;
	parameter BYTEENABLEWIDTH = 4;
	parameter ADDRESSWIDTH = 32;
	parameter FIFODEPTH = 32;
	parameter FIFODEPTH_LOG2 = 5;
	parameter FIFOUSEMEMORY = 1;
	
	localparam AVL_CONTROL = 0;
	localparam AVL_STATUS  = 1;
	localparam AVL_READ_ADDR_BASE = 2;
	localparam AVL_USER_DATA = 4;
	localparam AVL_READ_BUFFER = 5;

	input clk;
	input reset;


	input [3:0]				avs_csr_address;
	input					avs_csr_write;
	input					avs_csr_read;
	input [31:0]		avs_csr_writedata;
	output reg [31:0] 	avs_csr_readdata;


	input master_waitrequest;
	input master_readdatavalid;
    input [DATAWIDTH-1:0] master_readdata;
	output wire [ADDRESSWIDTH-1:0] master_address;
	output wire master_read;
	output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
	
	reg control_fixed_location;
	reg [ADDRESSWIDTH-1:0] control_read_base;
	reg [ADDRESSWIDTH-1:0] control_read_length;
	reg control_go;
	wire control_done;
	wire control_early_done;
	

	reg user_read_buffer;
	wire [DATAWIDTH-1:0] user_buffer_data;
	wire user_data_available;


	reg control_fixed_location_d1;
	wire fifo_empty;
	reg [ADDRESSWIDTH-1:0] address;
	reg [ADDRESSWIDTH-1:0] length;
	reg [FIFODEPTH_LOG2-1:0] reads_pending;
	wire increment_address;
	wire too_many_pending_reads;
	reg too_many_pending_reads_d1;
	wire [FIFODEPTH_LOG2-1:0] fifo_used;


	reg			avs_csr_read_reg;
	reg			avs_csr_write_reg;
	reg [3:0]	avs_csr_read_address_reg;
	reg [3:0]	avs_csr_write_address_reg;

	always @ (posedge clk or posedge reset) begin
		if (reset == 1) begin
			avs_csr_read_reg <= 0;
			avs_csr_write_reg <= 0;
		end
		else begin
			avs_csr_read_reg <= avs_csr_read;
			avs_csr_write_reg <= avs_csr_write;
		end
	end


	always @ (posedge avs_csr_read or posedge reset) begin
		if (reset == 1) begin
			avs_csr_read_address_reg <= 0;
		end
		else begin
			avs_csr_read_address_reg <= avs_csr_address;
		end
	end

	always @ (posedge avs_csr_write or posedge reset) begin
		if (reset == 1'b1) begin
			avs_csr_write_address_reg <= 0;
		end
		else begin
			avs_csr_write_address_reg <= avs_csr_address;
		end
	end


	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1) begin
			control_read_base <= 32'h0;
		end
		else begin
			if (avs_csr_write_reg == 1) begin
				case (avs_csr_write_address_reg)
					AVL_READ_ADDR_BASE:

						control_read_base <= avs_csr_writedata;
				endcase
			end
		end
	end

	always @ (posedge clk)
	begin
		control_fixed_location <= 1;
		control_read_length <= 4;
	end




	always @ (posedge clk) begin
		if ((avs_csr_write_reg == 1) && (avs_csr_write_address_reg == AVL_CONTROL)) begin
			control_go <= avs_csr_writedata[0];
		end
		else begin
			control_go <= 0;
		end
	end




	always @ (posedge clk) begin
		if ((avs_csr_read == 1) && (avs_csr_address == AVL_USER_DATA) && (user_read_buffer == 0)) begin
			user_read_buffer <= 1;
		end
		else begin
			user_read_buffer <= 0;
		end
	end

	reg [DATAWIDTH-1:0] csr_status;
	
	always @ (posedge clk or posedge reset) begin
		if (reset == 1) begin
			csr_status <= 32'h0;
		end
		else begin
			csr_status <= {{30{1'b0}}, user_data_available, control_done};
		end
	end
	

	always @ (posedge avs_csr_read_reg or posedge reset) begin
		case (avs_csr_read_address_reg)
			AVL_READ_ADDR_BASE:
				avs_csr_readdata <= control_read_base;
			AVL_USER_DATA:
				avs_csr_readdata <= user_buffer_data;
			default:
				avs_csr_readdata <= csr_status;
		endcase
	end



	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			control_fixed_location_d1 <= 0;
		end
		else
		begin
			if (control_go == 1)
			begin
				control_fixed_location_d1 <= control_fixed_location;
			end
		end
	end


	assign master_address = address;
	assign master_byteenable = -1;
	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			address <= 0;
		end
		else
		begin
			if(control_go == 1)
			begin
				address <= control_read_base;
			end
			else if((increment_address == 1) & (control_fixed_location_d1 == 0))
			begin
				address <= address + BYTEENABLEWIDTH;
			end
		end
	end


	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			length <= 0;
		end
		else
		begin
			if(control_go == 1)
			begin
				length <= control_read_length;
			end
			else if(increment_address == 1)
			begin
				length <= length - BYTEENABLEWIDTH;
			end
		end
	end	
	

	assign too_many_pending_reads = (fifo_used + reads_pending) >= (FIFODEPTH - 4);
	assign master_read = (length != 0) & (too_many_pending_reads_d1 == 0);
	assign increment_address = (length != 0) & (too_many_pending_reads_d1 == 0) & (master_waitrequest == 0);
	assign control_done = (reads_pending == 0) & (length == 0);
	assign control_early_done = (length == 0);

	always @ (posedge clk)
	begin
		if (reset == 1)
		begin
			too_many_pending_reads_d1 <= 0;
		end
		else
		begin
			too_many_pending_reads_d1 <= too_many_pending_reads;
		end
	end

	

	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			reads_pending <= 0;
		end
		else
		begin
			if(increment_address == 1)
			begin
				if(master_readdatavalid == 0)
				begin
					reads_pending <= reads_pending + 1;
				end
				else
				begin
					reads_pending <= reads_pending;
				end			
			end
			else
			begin
				if(master_readdatavalid == 0)
				begin
					reads_pending <= reads_pending;
				end
				else
				begin
					reads_pending <= reads_pending - 1;
				end				
			end
		end
	end

	

	assign user_data_available = !fifo_empty;
	scfifo the_master_to_user_fifo (
		.aclr (reset),
		.clock (clk),
		.data (master_readdata),
		.empty (fifo_empty),
		.q (user_buffer_data),
		.rdreq (user_read_buffer),
		.usedw (fifo_used),
		.wrreq (master_readdatavalid)
	);
	defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
	defparam the_master_to_user_fifo.lpm_widthu = FIFODEPTH_LOG2;
	defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
	defparam the_master_to_user_fifo.lpm_showahead = "ON";
	defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
	defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
	defparam the_master_to_user_fifo.underflow_checking = "OFF";
	defparam the_master_to_user_fifo.overflow_checking = "OFF";

endmodule
module latency_aware_read_master (
	clk,
	reset,


	avs_csr_address,
	avs_csr_readdata,
	avs_csr_write,
	avs_csr_read,
	avs_csr_writedata,


	master_address,
	master_read,
	master_byteenable,
	master_readdata,
	master_readdatavalid,
	master_waitrequest
);


	parameter DATAWIDTH = 32;
	parameter BYTEENABLEWIDTH = 4;
	parameter ADDRESSWIDTH = 32;
	parameter FIFODEPTH = 32;
	parameter FIFODEPTH_LOG2 = 5;
	parameter FIFOUSEMEMORY = 1;
	
	localparam AVL_CONTROL = 0;
	localparam AVL_STATUS  = 1;
	localparam AVL_READ_ADDR_BASE = 2;
	localparam AVL_USER_DATA = 4;
	localparam AVL_READ_BUFFER = 5;

	input clk;
	input reset;


	input [3:0]				avs_csr_address;
	input					avs_csr_write;
	input					avs_csr_read;
	input [31:0]		avs_csr_writedata;
	output reg [31:0] 	avs_csr_readdata;


	input master_waitrequest;
	input master_readdatavalid;
    input [DATAWIDTH-1:0] master_readdata;
	output wire [ADDRESSWIDTH-1:0] master_address;
	output wire master_read;
	output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
	
	reg control_fixed_location;
	reg [ADDRESSWIDTH-1:0] control_read_base;
	reg [ADDRESSWIDTH-1:0] control_read_length;
	reg control_go;
	wire control_done;
	wire control_early_done;
	

	reg user_read_buffer;
	wire [DATAWIDTH-1:0] user_buffer_data;
	wire user_data_available;


	reg control_fixed_location_d1;
	wire fifo_empty;
	reg [ADDRESSWIDTH-1:0] address;
	reg [ADDRESSWIDTH-1:0] length;
	reg [FIFODEPTH_LOG2-1:0] reads_pending;
	wire increment_address;
	wire too_many_pending_reads;
	reg too_many_pending_reads_d1;
	wire [FIFODEPTH_LOG2-1:0] fifo_used;


	reg			avs_csr_read_reg;
	reg			avs_csr_write_reg;
	reg [3:0]	avs_csr_read_address_reg;
	reg [3:0]	avs_csr_write_address_reg;

	always @ (posedge clk or posedge reset) begin
		if (reset == 1) begin
			avs_csr_read_reg <= 0;
			avs_csr_write_reg <= 0;
		end
		else begin
			avs_csr_read_reg <= avs_csr_read;
			avs_csr_write_reg <= avs_csr_write;
		end
	end


	always @ (posedge avs_csr_read or posedge reset) begin
		if (reset == 1) begin
			avs_csr_read_address_reg <= 0;
		end
		else begin
			avs_csr_read_address_reg <= avs_csr_address;
		end
	end

	always @ (posedge avs_csr_write or posedge reset) begin
		if (reset == 1'b1) begin
			avs_csr_write_address_reg <= 0;
		end
		else begin
			avs_csr_write_address_reg <= avs_csr_address;
		end
	end


	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1) begin
			control_read_base <= 32'h0;
		end
		else begin
			if (avs_csr_write_reg == 1) begin
				case (avs_csr_write_address_reg)
					AVL_READ_ADDR_BASE:

						control_read_base <= avs_csr_writedata;
				endcase
			end
		end
	end

	always @ (posedge clk)
	begin
		control_fixed_location <= 1;
		control_read_length <= 4;
	end




	always @ (posedge clk) begin
		if ((avs_csr_write_reg == 1) && (avs_csr_write_address_reg == AVL_CONTROL)) begin
			control_go <= avs_csr_writedata[0];
		end
		else begin
			control_go <= 0;
		end
	end




	always @ (posedge clk) begin
		if ((avs_csr_read == 1) && (avs_csr_address == AVL_USER_DATA) && (user_read_buffer == 0)) begin
			user_read_buffer <= 1;
		end
		else begin
			user_read_buffer <= 0;
		end
	end

	reg [DATAWIDTH-1:0] csr_status;
	
	always @ (posedge clk or posedge reset) begin
		if (reset == 1) begin
			csr_status <= 32'h0;
		end
		else begin
			csr_status <= {{30{1'b0}}, user_data_available, control_done};
		end
	end
	

	always @ (posedge avs_csr_read_reg or posedge reset) begin
		case (avs_csr_read_address_reg)
			AVL_READ_ADDR_BASE:
				avs_csr_readdata <= control_read_base;
			AVL_USER_DATA:
				avs_csr_readdata <= user_buffer_data;
			default:
				avs_csr_readdata <= csr_status;
		endcase
	end



	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			control_fixed_location_d1 <= 0;
		end
		else
		begin
			if (control_go == 1)
			begin
				control_fixed_location_d1 <= control_fixed_location;
			end
		end
	end


	assign master_address = address;
	assign master_byteenable = -1;
	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			address <= 0;
		end
		else
		begin
			if(control_go == 1)
			begin
				address <= control_read_base;
			end
			else if((increment_address == 1) & (control_fixed_location_d1 == 0))
			begin
				address <= address + BYTEENABLEWIDTH;
			end
		end
	end


	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			length <= 0;
		end
		else
		begin
			if(control_go == 1)
			begin
				length <= control_read_length;
			end
			else if(increment_address == 1)
			begin
				length <= length - BYTEENABLEWIDTH;
			end
		end
	end	
	

	assign too_many_pending_reads = (fifo_used + reads_pending) >= (FIFODEPTH - 4);
	assign master_read = (length != 0) & (too_many_pending_reads_d1 == 0);
	assign increment_address = (length != 0) & (too_many_pending_reads_d1 == 0) & (master_waitrequest == 0);
	assign control_done = (reads_pending == 0) & (length == 0);
	assign control_early_done = (length == 0);

	always @ (posedge clk)
	begin
		if (reset == 1)
		begin
			too_many_pending_reads_d1 <= 0;
		end
		else
		begin
			too_many_pending_reads_d1 <= too_many_pending_reads;
		end
	end

	

	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			reads_pending <= 0;
		end
		else
		begin
			if(increment_address == 1)
			begin
				if(master_readdatavalid == 0)
				begin
					reads_pending <= reads_pending + 1;
				end
				else
				begin
					reads_pending <= reads_pending;
				end			
			end
			else
			begin
				if(master_readdatavalid == 0)
				begin
					reads_pending <= reads_pending;
				end
				else
				begin
					reads_pending <= reads_pending - 1;
				end				
			end
		end
	end

	

	assign user_data_available = !fifo_empty;
	scfifo the_master_to_user_fifo (
		.aclr (reset),
		.clock (clk),
		.data (master_readdata),
		.empty (fifo_empty),
		.q (user_buffer_data),
		.rdreq (user_read_buffer),
		.usedw (fifo_used),
		.wrreq (master_readdatavalid)
	);
	defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
	defparam the_master_to_user_fifo.lpm_widthu = FIFODEPTH_LOG2;
	defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
	defparam the_master_to_user_fifo.lpm_showahead = "ON";
	defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
	defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
	defparam the_master_to_user_fifo.underflow_checking = "OFF";
	defparam the_master_to_user_fifo.overflow_checking = "OFF";

endmodule