data/full_repos/permissive/201425860/svf/MakeResetA.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/201425860/svf/MakeResetA.v:86: Unsupported: Ignoring delay on this delayed statement.\n      #0 ;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/201425860/svf/MakeResetA.v:66: Cannot find file containing module: \'SyncResetA\'\n   SyncResetA #(RSTDELAY) rstSync (.CLK(DST_CLK),\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201425860/svf,data/full_repos/permissive/201425860/SyncResetA\n             data/full_repos/permissive/201425860/svf,data/full_repos/permissive/201425860/SyncResetA.v\n             data/full_repos/permissive/201425860/svf,data/full_repos/permissive/201425860/SyncResetA.sv\n             SyncResetA\n             SyncResetA.v\n             SyncResetA.sv\n             obj_dir/SyncResetA\n             obj_dir/SyncResetA.v\n             obj_dir/SyncResetA.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MakeResetA (
		  CLK,
		  RST,
                  ASSERT_IN,
		  ASSERT_OUT,

                  DST_CLK,
                  OUT_RST
                  );

   parameter          RSTDELAY = 2  ;
   parameter          init = 1 ;

   input              CLK ;
   input              RST ;
   input              ASSERT_IN ;
   output             ASSERT_OUT ;

   input              DST_CLK ;
   output             OUT_RST ;

   reg                rst ;
   wire               OUT_RST ;

   assign ASSERT_OUT =  rst == `BSV_RESET_VALUE ;

   SyncResetA #(RSTDELAY) rstSync (.CLK(DST_CLK),
				   .IN_RST(rst),
				   .OUT_RST(OUT_RST));

   always@(posedge CLK or `BSV_RESET_EDGE RST) begin
      if (RST == `BSV_RESET_VALUE)
        rst <= `BSV_ASSIGNMENT_DELAY init ? ~ `BSV_RESET_VALUE : `BSV_RESET_VALUE ;
      else
        begin
           if (ASSERT_IN)
             rst <= `BSV_ASSIGNMENT_DELAY `BSV_RESET_VALUE;
           else
             rst <= `BSV_ASSIGNMENT_DELAY ~ `BSV_RESET_VALUE;
        end
   end

`ifdef BSV_NO_INITIAL_BLOCKS
`else

   initial begin
      #0 ;
      rst = ~ `BSV_RESET_VALUE ;
   end

`endif

endmodule
module MakeResetA (
		  CLK,
		  RST,
                  ASSERT_IN,
		  ASSERT_OUT,

                  DST_CLK,
                  OUT_RST
                  );


   parameter          RSTDELAY = 2  ;
   parameter          init = 1 ;

   input              CLK ;
   input              RST ;
   input              ASSERT_IN ;
   output             ASSERT_OUT ;

   input              DST_CLK ;
   output             OUT_RST ;

   reg                rst ;
   wire               OUT_RST ;

   assign ASSERT_OUT =  rst == `BSV_RESET_VALUE ;

   SyncResetA #(RSTDELAY) rstSync (.CLK(DST_CLK),
				   .IN_RST(rst),
				   .OUT_RST(OUT_RST));

   always@(posedge CLK or `BSV_RESET_EDGE RST) begin
      if (RST == `BSV_RESET_VALUE)
        rst <= `BSV_ASSIGNMENT_DELAY init ? ~ `BSV_RESET_VALUE : `BSV_RESET_VALUE ;
      else
        begin
           if (ASSERT_IN)
             rst <= `BSV_ASSIGNMENT_DELAY `BSV_RESET_VALUE;
           else
             rst <= `BSV_ASSIGNMENT_DELAY ~ `BSV_RESET_VALUE;
        end
   end

`ifdef BSV_NO_INITIAL_BLOCKS
`else

   initial begin
      #0 ;
      rst = ~ `BSV_RESET_VALUE ;
   end

`endif

endmodule