data/full_repos/permissive/212495825/src/gaplus_io.v
1: b'%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:356: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'INP\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h0: out <= INP;  \n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:357: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h1: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'hF;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:357: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h1: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'hF;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'he\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:359: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h3: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'h1;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:359: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'h1\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h3: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'h1;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:276: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_add\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp1\n    regs[4\'h0] <= credit_add;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:277: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_sub\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp1\n    regs[4\'h1] <= credit_sub;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:144: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_add\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp0\n    regs[4\'h2] <= credit_add;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:145: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_sub\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp0\n    regs[4\'h3] <= credit_sub;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:46: Output port connection \'rd\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'iocust_rd\' generates 4 bits.\n                                                                       : ... In instance GAPLUS_IO\nGAPLUS_IO_CUS2 iocust( reset, clk, iocust_cs, cpu_ad[3:0], iocust_rd, cpu_wd, cpu_wr,  pcm_kick, INP2 );\n                                                           ^~~~~~~~~\n%Error: Exiting due to 13 warning(s)\n'
module BCDCONV(A,ONES,TENS);

input  [7:0] A;
output [3:0] ONES, TENS;
wire   [3:0] c1,c2,c3,c4,c5,c6,c7;
wire   [3:0] d1,d2,d3,d4,d5,d6,d7;

assign d1 = {1'b0,A[7:5]};
assign d2 = {c1[2:0],A[4]};
assign d3 = {c2[2:0],A[3]};
assign d4 = {c3[2:0],A[2]};
assign d5 = {c4[2:0],A[1]};
assign d6 = {1'b0,c1[3],c2[3],c3[3]};
assign d7 = {c6[2:0],c4[3]};

add3 m1(d1,c1);
add3 m2(d2,c2);
add3 m3(d3,c3);
add3 m4(d4,c4);
add3 m5(d5,c5);
add3 m6(d6,c6);
add3 m7(d7,c7);

assign ONES = {c5[2:0],A[0]};
assign TENS = {c7[2:0],c5[3]};

endmodule
module BCDCONV(A,ONES,TENS);


input  [7:0] A;
output [3:0] ONES, TENS;
wire   [3:0] c1,c2,c3,c4,c5,c6,c7;
wire   [3:0] d1,d2,d3,d4,d5,d6,d7;

assign d1 = {1'b0,A[7:5]};
assign d2 = {c1[2:0],A[4]};
assign d3 = {c2[2:0],A[3]};
assign d4 = {c3[2:0],A[2]};
assign d5 = {c4[2:0],A[1]};
assign d6 = {1'b0,c1[3],c2[3],c3[3]};
assign d7 = {c6[2:0],c4[3]};

add3 m1(d1,c1);
add3 m2(d2,c2);
add3 m3(d3,c3);
add3 m4(d4,c4);
add3 m5(d5,c5);
add3 m6(d6,c6);
add3 m7(d7,c7);

assign ONES = {c5[2:0],A[0]};
assign TENS = {c7[2:0],c5[3]};

endmodule