data/full_repos/permissive/178917770/design.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/178917770/design.v:237: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'flopenr\'\nmodule flopenr #(parameter WIDTH = 4)\n       ^~~~~~~\n                                                                    : ... Top module \'processor\'\nmodule processor(input clk, reset,\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/178917770/design.v:250: Duplicate declaration of signal: \'MemWrite\'\n                                                         : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire MemToReg, MemWrite, RegWrite, ALUSrc, J, initRd;\n                   ^~~~~~~~\n        data/full_repos/permissive/178917770/design.v:240: ... Location of original declaration\n                 output MemWrite,BeqFlag,\n                        ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module controlUnit(input [10:0] Instr,
                   input BeqFlag,
                   output  [1:0] AdrRd,
                   output  [1:0] AdrRa,
                   output  reg [1:0] AdrRb,
                   output  [3:0] imm,
                   output [6:0] Adr,
                   output reg[1:0] ALUControl,
                   output reg MemToReg, MemWrite, RegWrite, ALUSrc, J,initRd,
                   output Beq);
  
  reg Beq_;
  always @(*) begin
    case(Instr[10:8])

      3'b000: begin
        	MemToReg=1'b0;MemWrite=1'b0;RegWrite=1'b1; ALUSrc=1'b0; Beq_=1'b0; J=1'b0; ALUControl = Instr[1:0]; AdrRb = Instr[3:2];initRd=1'b0;
      end

      3'b001: begin
       	 MemToReg=1'b0;MemWrite=1'b0;RegWrite=1'b1; ALUSrc=1'b1; Beq_=1'b0; J=1'b0; ALUControl=2'b00;  AdrRb = Instr[3:2];initRd=1'b0;
      end

      3'b010: begin
        MemToReg=1'b1;MemWrite=1'b0;RegWrite=1'b1; ALUSrc=1'b1; Beq_=1'b0; J=1'b0; ALUControl=2'b00;  AdrRb = Instr[3:2];initRd=1'b0;
      end

      3'b011: begin
        MemToReg=1'b0;MemWrite=1'b1;RegWrite=1'b0; ALUSrc=1'b1; Beq_=1'b0; J=1'b0; ALUControl=2'b00;  AdrRb = Instr[7:6];initRd=1'b0;
      end

      3'b100: begin
        MemToReg=1'b0;MemWrite=1'b0;RegWrite=1'b0; ALUSrc=1'b1; Beq_=1'b1; J=1'b0; ALUControl=2'b00;  AdrRb = Instr[3:2];initRd=1'b0;
      end

      3'b101: begin
         MemToReg=1'b0;MemWrite=1'b0;RegWrite=1'b0; ALUSrc=1'b0; Beq_=1'b0; J=1'b1; ALUControl=2'b00;  AdrRb = Instr[3:2];initRd=1'b0;
      end

      3'b110: begin
        MemToReg=1'b0;MemWrite=1'b0;RegWrite=1'b1; ALUSrc=1'b0; Beq_=1'b0; J=1'b0; ALUControl=2'b00;  AdrRb = Instr[3:2]; initRd=1'b1;initRd=1'b1;
      end 
      default:  begin
        MemToReg=1'b0;MemWrite=1'b0;RegWrite=1'b0; ALUSrc=1'b0; Beq_=1'b0; J=1'b0; ALUControl=2'b00;  AdrRb = Instr[3:2];initRd=1'b0;
      end
    endcase
    
  end
   assign Beq = Beq_ &  BeqFlag;

  assign AdrRd = Instr[7:6];
    assign AdrRa = Instr[5:4];
    
  assign imm = Instr[3:0];
    assign Adr = Instr[6:0];
    
    endmodule
module controlUnit(input [10:0] Instr,
                   input BeqFlag,
                   output  [1:0] AdrRd,
                   output  [1:0] AdrRa,
                   output  reg [1:0] AdrRb,
                   output  [3:0] imm,
                   output [6:0] Adr,
                   output reg[1:0] ALUControl,
                   output reg MemToReg, MemWrite, RegWrite, ALUSrc, J,initRd,
                   output Beq);

  
  reg Beq_;
  always @(*) begin
    case(Instr[10:8])

      3'b000: begin
        	MemToReg=1'b0;MemWrite=1'b0;RegWrite=1'b1; ALUSrc=1'b0; Beq_=1'b0; J=1'b0; ALUControl = Instr[1:0]; AdrRb = Instr[3:2];initRd=1'b0;
      end

      3'b001: begin
       	 MemToReg=1'b0;MemWrite=1'b0;RegWrite=1'b1; ALUSrc=1'b1; Beq_=1'b0; J=1'b0; ALUControl=2'b00;  AdrRb = Instr[3:2];initRd=1'b0;
      end

      3'b010: begin
        MemToReg=1'b1;MemWrite=1'b0;RegWrite=1'b1; ALUSrc=1'b1; Beq_=1'b0; J=1'b0; ALUControl=2'b00;  AdrRb = Instr[3:2];initRd=1'b0;
      end

      3'b011: begin
        MemToReg=1'b0;MemWrite=1'b1;RegWrite=1'b0; ALUSrc=1'b1; Beq_=1'b0; J=1'b0; ALUControl=2'b00;  AdrRb = Instr[7:6];initRd=1'b0;
      end

      3'b100: begin
        MemToReg=1'b0;MemWrite=1'b0;RegWrite=1'b0; ALUSrc=1'b1; Beq_=1'b1; J=1'b0; ALUControl=2'b00;  AdrRb = Instr[3:2];initRd=1'b0;
      end

      3'b101: begin
         MemToReg=1'b0;MemWrite=1'b0;RegWrite=1'b0; ALUSrc=1'b0; Beq_=1'b0; J=1'b1; ALUControl=2'b00;  AdrRb = Instr[3:2];initRd=1'b0;
      end

      3'b110: begin
        MemToReg=1'b0;MemWrite=1'b0;RegWrite=1'b1; ALUSrc=1'b0; Beq_=1'b0; J=1'b0; ALUControl=2'b00;  AdrRb = Instr[3:2]; initRd=1'b1;initRd=1'b1;
      end 
      default:  begin
        MemToReg=1'b0;MemWrite=1'b0;RegWrite=1'b0; ALUSrc=1'b0; Beq_=1'b0; J=1'b0; ALUControl=2'b00;  AdrRb = Instr[3:2];initRd=1'b0;
      end
    endcase
    
  end
   assign Beq = Beq_ &  BeqFlag;

  assign AdrRd = Instr[7:6];
    assign AdrRa = Instr[5:4];
    
  assign imm = Instr[3:0];
    assign Adr = Instr[6:0];
    
    endmodule