data/full_repos/permissive/143286506/Ver2/resisterfile.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/143286506/Ver2/resisterfile.v:24: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'resisterfile\'\nmodule resisterfile(\n       ^~~~~~~~~~~~\n                                                                              : ... Top module \'writeback\'\nmodule writeback(clk,rstd,nextpc,pc);\n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module writeback(clk,rstd,nextpc,pc);
input clk,rstd;
input [31:0] nextpc;
output [31:0] pc;
reg [31:0] pc;

always @(negedge rstd or posedge clk)
    begin
      if(rstd == 0) pc <= 32'h00000000;
      else if(clk == 1) pc <= nextpc;
    end
endmodule
module writeback(clk,rstd,nextpc,pc);

input clk,rstd;
input [31:0] nextpc;
output [31:0] pc;
reg [31:0] pc;

always @(negedge rstd or posedge clk)
    begin
      if(rstd == 0) pc <= 32'h00000000;
      else if(clk == 1) pc <= nextpc;
    end
endmodule