data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/config_loader/configuration_manager.v
None: at end of input
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/config_loader/configuration_manager.v:22: Cannot find include file: clock_divider.v\n`include "clock_divider.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/config_loader,data/full_repos/permissive/137416811/clock_divider.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/config_loader,data/full_repos/permissive/137416811/clock_divider.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/config_loader,data/full_repos/permissive/137416811/clock_divider.v.sv\n             clock_divider.v\n             clock_divider.v.v\n             clock_divider.v.sv\n             obj_dir/clock_divider.v\n             obj_dir/clock_divider.v.v\n             obj_dir/clock_divider.v.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/config_loader/configuration_manager.v:23: Cannot find include file: pulse_generator.v\n`include "pulse_generator.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module configuration_manager(
    input clk_in,
    output prog_reset,
    output prog_clk,
    output ccff_head,
    output configuration_done
    );
    
    parameter START_CYCLE=3;
    parameter CONFIGURATION_CLK_DIV_SIZE=12;
    
    wire prog_clk_out;
    wire ccff_head_out;
    
    assign ccff_head = ccff_head_out & ~prog_reset;
    assign prog_clk = prog_clk_out & ~configuration_done;
    


    reset_generator #(
      .INITIAL_VALUE(1),
      .ACTIVE_CYCLES(START_CYCLE)
    ) prog_reset_generator(
      .clk(~prog_clk),
      .pulse(prog_reset)
    );
    
    


    clock_divider #(
      .CLK_DIVIDER_SIZE(CONFIGURATION_CLK_DIV_SIZE)
      ) prog_clk_divider (
        .clk_in(clk_in),
        .clk_out(prog_clk_out)
      ); 
      
      

    bitstream_loader loader (
      .prog_clk(prog_clk),
      .config_chain_head(ccff_head_out),
      .start(~prog_reset),
      .done(configuration_done)
    );
    
endmodule
module configuration_manager(
    input clk_in,
    output prog_reset,
    output prog_clk,
    output ccff_head,
    output configuration_done
    );

    
    parameter START_CYCLE=3;
    parameter CONFIGURATION_CLK_DIV_SIZE=12;
    
    wire prog_clk_out;
    wire ccff_head_out;
    
    assign ccff_head = ccff_head_out & ~prog_reset;
    assign prog_clk = prog_clk_out & ~configuration_done;
    


    reset_generator #(
      .INITIAL_VALUE(1),
      .ACTIVE_CYCLES(START_CYCLE)
    ) prog_reset_generator(
      .clk(~prog_clk),
      .pulse(prog_reset)
    );
    
    


    clock_divider #(
      .CLK_DIVIDER_SIZE(CONFIGURATION_CLK_DIV_SIZE)
      ) prog_clk_divider (
        .clk_in(clk_in),
        .clk_out(prog_clk_out)
      ); 
      
      

    bitstream_loader loader (
      .prog_clk(prog_clk),
      .config_chain_head(ccff_head_out),
      .start(~prog_reset),
      .done(configuration_done)
    );
    
endmodule