data/full_repos/permissive/126366342/verilog modules/MMU.v
1: b'%Error: Cannot find file containing module: modules,data/full_repos/permissive/126366342\n        ... Looked in:\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342.v\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342.sv\n             modules,data/full_repos/permissive/126366342\n             modules,data/full_repos/permissive/126366342.v\n             modules,data/full_repos/permissive/126366342.sv\n             obj_dir/modules,data/full_repos/permissive/126366342\n             obj_dir/modules,data/full_repos/permissive/126366342.v\n             obj_dir/modules,data/full_repos/permissive/126366342.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/126366342/verilog\n%Error: Cannot find file containing module: modules/MMU.v\n%Error: Exiting due to 3 error(s)\n'
module mmu(
    input [31:0] ADDR,
    input rdWR,
    input clk,
    inout [31:0] DATA,
    inout [7:0] PORT0_PHYS,
	 input MOSI,
    output MISO,
    input SCK,
    input nCS 
);


wire [31:0] ROM_DATA_OUT, RAM_DATA_OUT, mmu_data_out,des_data_out;
wire [7:0] PORT0_DATA_OUT, SPI_DATA_OUT;
reg [0:2] decision;

wire [31:0] data_in;
wire [7:0] port0_data_in;
wire [7:0] spi_data_in;


wire rom_sel, ram_sel, port0_sel, port0_update, spi_sel;
wire rdWR_RAM, rdWR_PORT0,rdWR_SPI;


assign data_in = DATA;
assign DATA = (rdWR) ? 32'hZZZZ_ZZZZ : mmu_data_out;






assign rom_sel = ((ADDR >= 32'h0000_0000) & (ADDR < 32'h0000_8000));
assign ram_sel = ((ADDR >= 32'h0000_8000) & (ADDR < 32'h0000_C000));
assign port0_sel = ((ADDR == 32'h0000_C000) | (ADDR == 32'h0000_C004));
assign port0_update = (ADDR == 32'h0000_C004);
assign spi_sel =  ((ADDR == 32'h0000_C100) | (ADDR ==  32'h0000_C104));
assign des_sel = ((ADDR == 32'h0000_C200) | (ADDR == 32'h0000_C204) | (ADDR == 32'h0000_C208) | (ADDR == 32'h0000_C20C));




data_read_mux DATA_MUX(
    .A(ROM_DATA_OUT),
    .B(RAM_DATA_OUT),
    .C({24'd0, PORT0_DATA_OUT}),
	 .D({24'd0, SPI_DATA_OUT}),
	 .E({des_data_out}),
    .Sel({des_sel,spi_sel,port0_sel, ram_sel, rom_sel}),
    .Y(mmu_data_out)
);


mips_rom ROM(
    .address(ADDR),
    .data(ROM_DATA_OUT)
);



assign rdWR_RAM = rdWR & ram_sel;
mips_ram RAM(
    .address(ADDR),
    .data_in(data_in),
    .rdWR_RAM(rdWR_RAM),
    .clk(clk),
    .data_out(RAM_DATA_OUT)
);


assign rdWR_PORT0 = rdWR & port0_sel;
gpio_port PORT0(
    .data_in(data_in[7:0]),
    .UPDATE(port0_update),
    .clk(clk),
    .rdWR(rdWR_PORT0),
    .data_out(PORT0_DATA_OUT),
    .PORT(PORT0_PHYS)
);


assign rdWR_SPI = rdWR & spi_sel;
mips_spi_module SPI(.spi_data_in(data_in), .rdWR(rdWR_SPI),.clk(clk),.spi_data_out(data_out),.MOSI(MOSI),.MISO(MISO),.SCK(SCK),.nCS(nCS));

always @ (ADDR)
begin
if(ADDR == 32'h0000_C200)
begin
	decision =  3'b000;

end
else if(ADDR == 32'h0000_C204)
begin
	decision = 3'b001;

end 
else if(ADDR == 32'h0000_C208)
begin 
	decision = 3'b010;


end
else if(ADDR == 32'h0000_C20C)
begin 
	decision = 3'b011;

end
else 
begin
decision = 3'b110;

end

end


assign rdWR_DES = rdWR & des_sel;
des_top2 des1(.data(data_in),.decision(decision),.data_out(des_data_out));



endmodule
module mmu(
    input [31:0] ADDR,
    input rdWR,
    input clk,
    inout [31:0] DATA,
    inout [7:0] PORT0_PHYS,
	 input MOSI,
    output MISO,
    input SCK,
    input nCS 
);



wire [31:0] ROM_DATA_OUT, RAM_DATA_OUT, mmu_data_out,des_data_out;
wire [7:0] PORT0_DATA_OUT, SPI_DATA_OUT;
reg [0:2] decision;

wire [31:0] data_in;
wire [7:0] port0_data_in;
wire [7:0] spi_data_in;


wire rom_sel, ram_sel, port0_sel, port0_update, spi_sel;
wire rdWR_RAM, rdWR_PORT0,rdWR_SPI;


assign data_in = DATA;
assign DATA = (rdWR) ? 32'hZZZZ_ZZZZ : mmu_data_out;






assign rom_sel = ((ADDR >= 32'h0000_0000) & (ADDR < 32'h0000_8000));
assign ram_sel = ((ADDR >= 32'h0000_8000) & (ADDR < 32'h0000_C000));
assign port0_sel = ((ADDR == 32'h0000_C000) | (ADDR == 32'h0000_C004));
assign port0_update = (ADDR == 32'h0000_C004);
assign spi_sel =  ((ADDR == 32'h0000_C100) | (ADDR ==  32'h0000_C104));
assign des_sel = ((ADDR == 32'h0000_C200) | (ADDR == 32'h0000_C204) | (ADDR == 32'h0000_C208) | (ADDR == 32'h0000_C20C));




data_read_mux DATA_MUX(
    .A(ROM_DATA_OUT),
    .B(RAM_DATA_OUT),
    .C({24'd0, PORT0_DATA_OUT}),
	 .D({24'd0, SPI_DATA_OUT}),
	 .E({des_data_out}),
    .Sel({des_sel,spi_sel,port0_sel, ram_sel, rom_sel}),
    .Y(mmu_data_out)
);


mips_rom ROM(
    .address(ADDR),
    .data(ROM_DATA_OUT)
);



assign rdWR_RAM = rdWR & ram_sel;
mips_ram RAM(
    .address(ADDR),
    .data_in(data_in),
    .rdWR_RAM(rdWR_RAM),
    .clk(clk),
    .data_out(RAM_DATA_OUT)
);


assign rdWR_PORT0 = rdWR & port0_sel;
gpio_port PORT0(
    .data_in(data_in[7:0]),
    .UPDATE(port0_update),
    .clk(clk),
    .rdWR(rdWR_PORT0),
    .data_out(PORT0_DATA_OUT),
    .PORT(PORT0_PHYS)
);


assign rdWR_SPI = rdWR & spi_sel;
mips_spi_module SPI(.spi_data_in(data_in), .rdWR(rdWR_SPI),.clk(clk),.spi_data_out(data_out),.MOSI(MOSI),.MISO(MISO),.SCK(SCK),.nCS(nCS));

always @ (ADDR)
begin
if(ADDR == 32'h0000_C200)
begin
	decision =  3'b000;

end
else if(ADDR == 32'h0000_C204)
begin
	decision = 3'b001;

end 
else if(ADDR == 32'h0000_C208)
begin 
	decision = 3'b010;


end
else if(ADDR == 32'h0000_C20C)
begin 
	decision = 3'b011;

end
else 
begin
decision = 3'b110;

end

end


assign rdWR_DES = rdWR & des_sel;
des_top2 des1(.data(data_in),.decision(decision),.data_out(des_data_out));



endmodule