data/full_repos/permissive/194847941/demo/16_ov2640_sdram/RTL/test_camera.v
None: at end of input
1: b"%Error: data/full_repos/permissive/194847941/demo/16_ov2640_sdram/RTL/test_camera.v:89: Cannot find file containing module: 'ip_pll'\nip_pll u_pll(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/16_ov2640_sdram/RTL,data/full_repos/permissive/194847941/ip_pll\n             data/full_repos/permissive/194847941/demo/16_ov2640_sdram/RTL,data/full_repos/permissive/194847941/ip_pll.v\n             data/full_repos/permissive/194847941/demo/16_ov2640_sdram/RTL,data/full_repos/permissive/194847941/ip_pll.sv\n             ip_pll\n             ip_pll.v\n             ip_pll.sv\n             obj_dir/ip_pll\n             obj_dir/ip_pll.v\n             obj_dir/ip_pll.sv\n%Error: data/full_repos/permissive/194847941/demo/16_ov2640_sdram/RTL/test_camera.v:100: Cannot find file containing module: 'camera_init'\ncamera_init u_camera_init\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/194847941/demo/16_ov2640_sdram/RTL/test_camera.v:112: Cannot find file containing module: 'Driver'\nDriver u_cam_vga_out\n^~~~~~\n%Error: data/full_repos/permissive/194847941/demo/16_ov2640_sdram/RTL/test_camera.v:145: Cannot find file containing module: 'camera_reader'\ncamera_reader u_camera_reader\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/194847941/demo/16_ov2640_sdram/RTL/test_camera.v:161: Cannot find file containing module: 'Sdram_Control_4Port'\nSdram_Control_4Port Sdram_Control_4Port(\n^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module test_camera

(
	input 	wire 		clk_24m,
	input 	wire 		rst_n,

	input 	wire 		cam_pclk,
	output 	wire 		cam_xclk,
	input 	wire 		cam_href,
	input 	wire 		cam_vsync,
	output 	wire 		cam_pwdn,
	output 	wire 		cam_rst,
	output 	wire 		cam_soic,
	inout 	wire 		cam_soid,
	input 	wire [7:0]	cam_data,

	output 	wire [7:0] 	vga_r,
	output 	wire [7:0] 	vga_g,
	output 	wire [7:0] 	vga_b,
	output 	wire 		vga_clk,
	output 	wire 		vga_hsync,
	output 	wire 		vga_vsync

 );
 

 localparam IMG_W = 800;
 localparam IMG_H = 600;
 localparam IMG_X = 0;
 localparam IMG_Y = 0;
 

wire 		clk_lcd;   
wire 		clk_cam;
wire 		clk_sccb;
wire 		clk_sdr_ctrl;
wire 		clk_sdram;

wire        camera_wrreq;
wire        camera_wclk;
wire [15:0] camera_wrdat;
wire [15:0] camera_addr;

reg 		init_state;
wire 		init_ready;
wire 		sda_oe;
wire 		sda;
wire 		sda_in;
wire 		scl;


wire 	[23:0] 	vga_data;
reg				vga_rden;
wire 	[15:0]	vga_rddat;	
reg  	[15:0]	vga_rdaddr;
wire vga_data_req;


assign cam_soid = (sda_oe == 1'b1) ? sda : 1'bz;
assign sda_in 	= cam_soid;
assign cam_soic = scl;
assign cam_pwdn = 1'b0;
assign cam_rst 	= rst_n;


assign 	vga_data [23:0] = vga_rden ? {vga_rddat[15:11],3'h0,vga_rddat[10:5],2'h0,vga_rddat[4:0],3'h0} : 24'h0;

wire 	vga_den;



wire	[11:0]	lcd_xpos;
wire 	[11:0]	lcd_ypos;


ip_pll u_pll(
	.refclk(clk_24m),
	.reset(!rst_n),
	.clk0_out(clk_sdr_ctrl),
	.clk1_out(clk_sdram),
	.clk2_out(clk_lcd),
	.clk3_out(clk_cam),
	.clk4_out(clk_sccb)
	
);

camera_init u_camera_init
(
	.clk(clk_sccb),
	.reset_n(rst_n),
	.ready(init_ready),
	.sda_oe(sda_oe),
	.sda(sda),
	.sda_in(sda_in),
	.scl(scl)
);
	

Driver u_cam_vga_out
(
	.clk(clk_lcd),			
	.rst_n(rst_n),
	.lcd_data(vga_data),
	

	.lcd_dclk(vga_clk),
	.lcd_hs(vga_hsync),
	.lcd_vs(vga_vsync),
	.lcd_en(vga_den),
	.lcd_rgb({vga_r,vga_g,vga_b}),


	.lcd_xpos(lcd_xpos),
	.lcd_ypos(lcd_ypos)
);
















camera_reader u_camera_reader
(
	.clk		(clk_cam		),
	.reset_n	(rst_n			),
	.csi_xclk	(cam_xclk		),
	.csi_pclk	(cam_pclk		),
	.csi_data	(cam_data		),
	.csi_vsync	(cam_vsync		),
	.csi_hsync	(cam_href		),
	.data_out	(camera_wrdat	),
	.wrreq		(camera_wrreq	),
	.wrclk		(camera_wclk	),
	.wraddr		(camera_addr	)
);


Sdram_Control_4Port Sdram_Control_4Port(

		.CTRL_CLK(clk_sdr_ctrl),
		.SDRAM_CLK(clk_sdram),
		.RESET_N(rst_n),


		.WR1_DATA(camera_wrdat),
		.WR1(camera_wrreq),
		.WR1_ADDR(21'b0),
		.WR1_MAX_ADDR(800*600),
		.WR1_LENGTH(10'd256),
		.WR1_LOAD((~rst_n) &(init_ready) ),

		.WR1_CLK(camera_wclk),
		.WR1_FULL(),
		.WR1_USE(),

		.WR2_DATA(16'b0),
		.WR2(1'b0),
		.WR2_ADDR(21'b0),
		.WR2_MAX_ADDR(200*200),
		.WR2_LENGTH(9'd0),
		.WR2_LOAD(1'b0),
		.WR2_CLK(1'b0),
		.WR2_FULL(),
		.WR2_USE(),

		.RD1_DATA(vga_rddat),
		.RD1(vga_den),
		.RD1_ADDR(21'b0),
		.RD1_MAX_ADDR(800*600),
		.RD1_LENGTH(10'd256),
		.RD1_LOAD((~rst_n) & (init_ready)),

		.RD1_CLK(clk_lcd),
		.RD1_EMPTY(),
		.RD1_USE(),


		.RD2_DATA(),
		.RD2(1'b0),
		.RD2_ADDR(21'b0),
		.RD2_MAX_ADDR(0),
		.RD2_LENGTH(9'd0),
		.RD2_LOAD(1'b0),
		.RD2_CLK(1'b0),
		.RD2_EMPTY(),
		.RD2_USE()
	);	












	





	


always @(negedge clk_lcd)
begin
	if(!rst_n)
	begin
		vga_rden <= 1'b0;

	end
	else 
	begin
	if (vga_den) 
			begin
			if(lcd_xpos >= IMG_X && lcd_xpos < (IMG_X + IMG_W) && lcd_ypos >= IMG_Y && lcd_ypos < (IMG_Y + IMG_H))
				begin
				vga_rden <= 1'b1;

				end
			else
				begin
					vga_rden <= 1'b0;

				end
			end
		else 
			begin
				vga_rden <= 1'b0;

			end	
	end 
end



	
endmodule
module test_camera

(
	input 	wire 		clk_24m,
	input 	wire 		rst_n,

	input 	wire 		cam_pclk,
	output 	wire 		cam_xclk,
	input 	wire 		cam_href,
	input 	wire 		cam_vsync,
	output 	wire 		cam_pwdn,
	output 	wire 		cam_rst,
	output 	wire 		cam_soic,
	inout 	wire 		cam_soid,
	input 	wire [7:0]	cam_data,

	output 	wire [7:0] 	vga_r,
	output 	wire [7:0] 	vga_g,
	output 	wire [7:0] 	vga_b,
	output 	wire 		vga_clk,
	output 	wire 		vga_hsync,
	output 	wire 		vga_vsync

 );

 

 localparam IMG_W = 800;
 localparam IMG_H = 600;
 localparam IMG_X = 0;
 localparam IMG_Y = 0;
 

wire 		clk_lcd;   
wire 		clk_cam;
wire 		clk_sccb;
wire 		clk_sdr_ctrl;
wire 		clk_sdram;

wire        camera_wrreq;
wire        camera_wclk;
wire [15:0] camera_wrdat;
wire [15:0] camera_addr;

reg 		init_state;
wire 		init_ready;
wire 		sda_oe;
wire 		sda;
wire 		sda_in;
wire 		scl;


wire 	[23:0] 	vga_data;
reg				vga_rden;
wire 	[15:0]	vga_rddat;	
reg  	[15:0]	vga_rdaddr;
wire vga_data_req;


assign cam_soid = (sda_oe == 1'b1) ? sda : 1'bz;
assign sda_in 	= cam_soid;
assign cam_soic = scl;
assign cam_pwdn = 1'b0;
assign cam_rst 	= rst_n;


assign 	vga_data [23:0] = vga_rden ? {vga_rddat[15:11],3'h0,vga_rddat[10:5],2'h0,vga_rddat[4:0],3'h0} : 24'h0;

wire 	vga_den;



wire	[11:0]	lcd_xpos;
wire 	[11:0]	lcd_ypos;


ip_pll u_pll(
	.refclk(clk_24m),
	.reset(!rst_n),
	.clk0_out(clk_sdr_ctrl),
	.clk1_out(clk_sdram),
	.clk2_out(clk_lcd),
	.clk3_out(clk_cam),
	.clk4_out(clk_sccb)
	
);

camera_init u_camera_init
(
	.clk(clk_sccb),
	.reset_n(rst_n),
	.ready(init_ready),
	.sda_oe(sda_oe),
	.sda(sda),
	.sda_in(sda_in),
	.scl(scl)
);
	

Driver u_cam_vga_out
(
	.clk(clk_lcd),			
	.rst_n(rst_n),
	.lcd_data(vga_data),
	

	.lcd_dclk(vga_clk),
	.lcd_hs(vga_hsync),
	.lcd_vs(vga_vsync),
	.lcd_en(vga_den),
	.lcd_rgb({vga_r,vga_g,vga_b}),


	.lcd_xpos(lcd_xpos),
	.lcd_ypos(lcd_ypos)
);
















camera_reader u_camera_reader
(
	.clk		(clk_cam		),
	.reset_n	(rst_n			),
	.csi_xclk	(cam_xclk		),
	.csi_pclk	(cam_pclk		),
	.csi_data	(cam_data		),
	.csi_vsync	(cam_vsync		),
	.csi_hsync	(cam_href		),
	.data_out	(camera_wrdat	),
	.wrreq		(camera_wrreq	),
	.wrclk		(camera_wclk	),
	.wraddr		(camera_addr	)
);


Sdram_Control_4Port Sdram_Control_4Port(

		.CTRL_CLK(clk_sdr_ctrl),
		.SDRAM_CLK(clk_sdram),
		.RESET_N(rst_n),


		.WR1_DATA(camera_wrdat),
		.WR1(camera_wrreq),
		.WR1_ADDR(21'b0),
		.WR1_MAX_ADDR(800*600),
		.WR1_LENGTH(10'd256),
		.WR1_LOAD((~rst_n) &(init_ready) ),

		.WR1_CLK(camera_wclk),
		.WR1_FULL(),
		.WR1_USE(),

		.WR2_DATA(16'b0),
		.WR2(1'b0),
		.WR2_ADDR(21'b0),
		.WR2_MAX_ADDR(200*200),
		.WR2_LENGTH(9'd0),
		.WR2_LOAD(1'b0),
		.WR2_CLK(1'b0),
		.WR2_FULL(),
		.WR2_USE(),

		.RD1_DATA(vga_rddat),
		.RD1(vga_den),
		.RD1_ADDR(21'b0),
		.RD1_MAX_ADDR(800*600),
		.RD1_LENGTH(10'd256),
		.RD1_LOAD((~rst_n) & (init_ready)),

		.RD1_CLK(clk_lcd),
		.RD1_EMPTY(),
		.RD1_USE(),


		.RD2_DATA(),
		.RD2(1'b0),
		.RD2_ADDR(21'b0),
		.RD2_MAX_ADDR(0),
		.RD2_LENGTH(9'd0),
		.RD2_LOAD(1'b0),
		.RD2_CLK(1'b0),
		.RD2_EMPTY(),
		.RD2_USE()
	);	












	





	


always @(negedge clk_lcd)
begin
	if(!rst_n)
	begin
		vga_rden <= 1'b0;

	end
	else 
	begin
	if (vga_den) 
			begin
			if(lcd_xpos >= IMG_X && lcd_xpos < (IMG_X + IMG_W) && lcd_ypos >= IMG_Y && lcd_ypos < (IMG_Y + IMG_H))
				begin
				vga_rden <= 1'b1;

				end
			else
				begin
					vga_rden <= 1'b0;

				end
			end
		else 
			begin
				vga_rden <= 1'b0;

			end	
	end 
end



	
endmodule