data/full_repos/permissive/137454634/count.v
None: at end of input
1: b'%Warning-MULTITOP: data/full_repos/permissive/137454634/count.v:40: Multiple top level modules\n                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                  : ... Top module \'counter_run\'\nmodule counter_run(endRun,CP,CP_H,StRun);\n       ^~~~~~~~~~~\n                                                                  : ... Top module \'counter_open\'\nmodule counter_open(endOpen,dispStage,CP,StOpen,pause,close);\n       ^~~~~~~~~~~~\n                                                                  : ... Top module \'delaybutton\'\nmodule delaybutton(pause,CP,delay);\n       ^~~~~~~~~~~\n                                                                  : ... Top module \'divideclk\'\nmodule divideclk(clk4hz,clk32hz,StRun,StOpen);\n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module delaybutton(pause,CP,delay);

input delay,CP;
output reg pause=0;
reg delay_reg=0;
reg [6:0] counter;
parameter conuntEnd = 7'd20;

always @ (posedge CP)
	begin
		delay_reg <= delay|delay_reg;
		if(!delay_reg) begin counter<=7'd0;pause<=0;end
		else if (delay == delay_reg) begin counter<=counter+1'b1;pause<=1;end
		else if (counter==conuntEnd) begin counter<=7'd0;delay_reg<=0;pause<=1'b0;end
		else begin counter<=counter+1'b1;pause<=1;end
	end

endmodule
module delaybutton(pause,CP,delay);


input delay,CP;
output reg pause=0;
reg delay_reg=0;
reg [6:0] counter;
parameter conuntEnd = 7'd20;

always @ (posedge CP)
	begin
		delay_reg <= delay|delay_reg;
		if(!delay_reg) begin counter<=7'd0;pause<=0;end
		else if (delay == delay_reg) begin counter<=counter+1'b1;pause<=1;end
		else if (counter==conuntEnd) begin counter<=7'd0;delay_reg<=0;pause<=1'b0;end
		else begin counter<=counter+1'b1;pause<=1;end
	end

endmodule