data/full_repos/permissive/170402453/BusSplitter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170402453/BusSplitter.v:26: Operator ASSIGNW expects 26 bits on the Assign RHS, but Assign RHS\'s VARREF \'IN1\' generates 8 bits.\n                                                                     : ... In instance BusSplitter8_26\n assign T1 = IN1;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module BusSplitter8_26(
    input [7:0] IN1,
    output [25:0] T1
    );

	assign T1 = IN1;

endmodule
module BusSplitter8_26(
    input [7:0] IN1,
    output [25:0] T1
    );


	assign T1 = IN1;

endmodule