data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/bufram.v
1: b"%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/bufram.v:43: Cannot find file containing module: 'dpram_altera'\ndpram_altera #(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog,data/full_repos/permissive/19905110/dpram_altera\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog,data/full_repos/permissive/19905110/dpram_altera.v\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog,data/full_repos/permissive/19905110/dpram_altera.sv\n             dpram_altera\n             dpram_altera.v\n             dpram_altera.sv\n             obj_dir/dpram_altera\n             obj_dir/dpram_altera.v\n             obj_dir/dpram_altera.sv\n%Error: Exiting due to 1 error(s)\n"
module bufram #(
	parameter ADDR_WIDTH = 3
)
(
	input			clk_a,
	input  [ADDR_WIDTH-1:0]	addr_a,
	input  [3:0]		we_a,
	input  [31:0]		di_a,
	output [31:0]		do_a,

	input			clk_b,
	input  [ADDR_WIDTH-1:0]	addr_b,
	input  [3:0]		we_b,
	input  [31:0]		di_b,
	output [31:0]		do_b
);

dpram_altera #(
	.ADDR_WIDTH(ADDR_WIDTH)
) dpram_altera (
	.clk_a		(clk_a),
	.addr_a		(addr_a),
	.we_a		(we_a),
	.di_a		(di_a),
	.do_a		(do_a),

	.clk_b		(clk_b),
	.addr_b		(addr_b),
	.we_b		(we_b),
	.di_b		(di_b),
	.do_b		(do_b)
);

endmodule
module bufram #(
	parameter ADDR_WIDTH = 3
)
(
	input			clk_a,
	input  [ADDR_WIDTH-1:0]	addr_a,
	input  [3:0]		we_a,
	input  [31:0]		di_a,
	output [31:0]		do_a,

	input			clk_b,
	input  [ADDR_WIDTH-1:0]	addr_b,
	input  [3:0]		we_b,
	input  [31:0]		di_b,
	output [31:0]		do_b
);


dpram_altera #(
	.ADDR_WIDTH(ADDR_WIDTH)
) dpram_altera (
	.clk_a		(clk_a),
	.addr_a		(addr_a),
	.we_a		(we_a),
	.di_a		(di_a),
	.do_a		(do_a),

	.clk_b		(clk_b),
	.addr_b		(addr_b),
	.we_b		(we_b),
	.di_b		(di_b),
	.do_b		(do_b)
);

endmodule