data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0502/lab5.srcs/sim_1/new/assembly.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0502/lab5.srcs/sim_1/new/assembly.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2) clk = 1\'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0502/lab5.srcs/sim_1/new/assembly.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0502/lab5.srcs/sim_1/new/assembly.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0502/lab5.srcs/sim_1/new/assembly.v:76: Unsupported: Ignoring delay on this delayed statement.\n       #10000; \n       ^\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0502/lab5.srcs/sim_1/new/assembly.v:42: Cannot find file containing module: \'Top\'\n    Top u(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0502/lab5.srcs/sim_1/new,data/full_repos/permissive/194376374/Top\n             data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0502/lab5.srcs/sim_1/new,data/full_repos/permissive/194376374/Top.v\n             data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0502/lab5.srcs/sim_1/new,data/full_repos/permissive/194376374/Top.sv\n             Top\n             Top.v\n             Top.sv\n             obj_dir/Top\n             obj_dir/Top.v\n             obj_dir/Top.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module assembly( );

    reg clk;
    wire Clkin;
    reg reset;
    reg [2:0] regnum;

    wire Clk;
	wire [7:0] LED;
	wire [31:0] R0;
	wire [31:0] R1;
	wire [31:0] R2;
	wire [31:0] R3;
	wire [31:0] R4;
	wire [31:0] R5;
	wire [31:0] R6;
	wire [31:0] R7;


    Top u(
    .clk_p(clk),
    .clk_n(~clk),
    .regnum(regnum),
    .Clk(Clk),
    .reset(reset),
    .Clkin(Clkin),
    .R0(R0),
    .R1(R1),
    .R2(R2),
    .R3(R3),
    .R4(R4),
    .R5(R5),
    .R6(R6),
    .R7(R7),
    .LED(LED)
    );
    
    parameter PERIOD = 100;

    always begin
        clk = 1'b0;
        #(PERIOD/2) clk = 1'b1;
        #(PERIOD/2);
    end
    
    initial begin

    reset<=1;
    regnum=3'b001;    
    #50

       reset <= 0;

       #10000; 
    end
endmodule
module assembly( );


    reg clk;
    wire Clkin;
    reg reset;
    reg [2:0] regnum;

    wire Clk;
	wire [7:0] LED;
	wire [31:0] R0;
	wire [31:0] R1;
	wire [31:0] R2;
	wire [31:0] R3;
	wire [31:0] R4;
	wire [31:0] R5;
	wire [31:0] R6;
	wire [31:0] R7;


    Top u(
    .clk_p(clk),
    .clk_n(~clk),
    .regnum(regnum),
    .Clk(Clk),
    .reset(reset),
    .Clkin(Clkin),
    .R0(R0),
    .R1(R1),
    .R2(R2),
    .R3(R3),
    .R4(R4),
    .R5(R5),
    .R6(R6),
    .R7(R7),
    .LED(LED)
    );
    
    parameter PERIOD = 100;

    always begin
        clk = 1'b0;
        #(PERIOD/2) clk = 1'b1;
        #(PERIOD/2);
    end
    
    initial begin

    reset<=1;
    regnum=3'b001;    
    #50

       reset <= 0;

       #10000; 
    end
endmodule