data/full_repos/permissive/143286506/Ver2/execute.v
 line:209: before: "/"
1: b"%Error: data/full_repos/permissive/143286506/Ver2/execute.v:18: Input/output/inout declaration not found for port: 'storeselector'\n  storeselector\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143286506/Ver2/execute.v:36: Input/output/inout does not appear in port list: 'rdresult'\noutput [31:0]rdresult;\n             ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module memaccess(
  address,
  reg_data,
  mem_result,
  mainop,
  subop,
  clk
);
input [31:0] address;
input [31:0] reg_data;
input [2:0] mainop;
input subop;
input clk;
output [31:0] mem_result;
wire [3:0] dren;
wire [31:0] dm_r_data;
wire [31:0] dm_w_data;
    function [3:0]create_op;
        input [3:0]op;
        case (op)
          4'b1_000:create_op = 4'b0111;
          4'b1_001:create_op = 4'b0011;
          4'b1_010:create_op = 4'b0000;
          default: create_op = 4'b1111;
        endcase
    endfunction

    function [31:0]endian_w;
        input [31:0]source;
        input [2:0]op;
		  case (op)
          3'b000:endian_w = source[31:0];
          3'b001:endian_w = {source[31:16],source[7:0],source[15:8]}; 
          3'b010:endian_w = {source[7:0],source[15:8],source[23:16],source[31:24]};
          default:endian_w = source[31:0];
        endcase
    endfunction

    function [31:0]endian_r;
        input [31:0]source;
        input [2:0]op;
        case (op)
          3'b000:endian_r = $signed(source[7:0]);
          3'b001:endian_r = {{16{source[7]}},source[7:0],source[15:8]}; 
          3'b010:endian_r = {source[7:0],source[15:8],source[23:16],source[31:24]};
          3'b000:endian_r = {{24{1'b0}},source[7:0]};
          3'b001:endian_r = {{16{source[7]}},source[7:0],source[15:8]}; 
          default:endian_r = source;
        endcase
    endfunction


    assign dren = create_op({subop,mainop[2:0]});
    assign dm_w_data = endian_w(reg_data,mainop);
    data_mem data_mem_body0(address[17:2], clk, dm_w_data[7:0], dren[0], dm_r_data [7:0]);
    data_mem data_mem_body1(address[17:2], clk, dm_w_data[15:8], dren[1], dm_r_data[15:8]);
    data_mem data_mem_body2(address[17:2], clk, dm_w_data[23:16], dren[2], dm_r_data[23:16]);
    data_mem data_mem_body3(address[17:2], clk, dm_w_data[31:24], dren[3], dm_r_data[31:24]);
    assign mem_result = endian_r(dm_r_data,mainop);
endmodule
module memaccess(
  address,
  reg_data,
  mem_result,
  mainop,
  subop,
  clk
);

input [31:0] address;
input [31:0] reg_data;
input [2:0] mainop;
input subop;
input clk;
output [31:0] mem_result;
wire [3:0] dren;
wire [31:0] dm_r_data;
wire [31:0] dm_w_data;
    function [3:0]create_op;
        input [3:0]op;
        case (op)
          4'b1_000:create_op = 4'b0111;
          4'b1_001:create_op = 4'b0011;
          4'b1_010:create_op = 4'b0000;
          default: create_op = 4'b1111;
        endcase
    endfunction

    function [31:0]endian_w;
        input [31:0]source;
        input [2:0]op;
		  case (op)
          3'b000:endian_w = source[31:0];
          3'b001:endian_w = {source[31:16],source[7:0],source[15:8]}; 
          3'b010:endian_w = {source[7:0],source[15:8],source[23:16],source[31:24]};
          default:endian_w = source[31:0];
        endcase
    endfunction

    function [31:0]endian_r;
        input [31:0]source;
        input [2:0]op;
        case (op)
          3'b000:endian_r = $signed(source[7:0]);
          3'b001:endian_r = {{16{source[7]}},source[7:0],source[15:8]}; 
          3'b010:endian_r = {source[7:0],source[15:8],source[23:16],source[31:24]};
          3'b000:endian_r = {{24{1'b0}},source[7:0]};
          3'b001:endian_r = {{16{source[7]}},source[7:0],source[15:8]}; 
          default:endian_r = source;
        endcase
    endfunction


    assign dren = create_op({subop,mainop[2:0]});
    assign dm_w_data = endian_w(reg_data,mainop);
    data_mem data_mem_body0(address[17:2], clk, dm_w_data[7:0], dren[0], dm_r_data [7:0]);
    data_mem data_mem_body1(address[17:2], clk, dm_w_data[15:8], dren[1], dm_r_data[15:8]);
    data_mem data_mem_body2(address[17:2], clk, dm_w_data[23:16], dren[2], dm_r_data[23:16]);
    data_mem data_mem_body3(address[17:2], clk, dm_w_data[31:24], dren[3], dm_r_data[31:24]);
    assign mem_result = endian_r(dm_r_data,mainop);
endmodule