data/full_repos/permissive/120024308/src/LCDController/buffer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/120024308/src/LCDController/buffer.v:58: Bit extraction of array[63:0] requires 6 bit index, not 7 bits.\n                                                                                  : ... In instance CmdBuffer\n   assign data_out = buffer[tail];\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/120024308/src/LCDController/buffer.v:96: Bit extraction of array[63:0] requires 6 bit index, not 7 bits.\n                                                                                  : ... In instance CmdBuffer\n                  buffer[head] <= data_in;\n                        ^\n%Error: Exiting due to 2 warning(s)\n'
module CmdBuffer #(
                    parameter DATA_WIDTH = 10,
                    parameter BUFF_SIZE = 64
                    )(
                      input wire                  clk,
                      input wire                  reset,
                      input wire [DATA_WIDTH-1:0] data_in,
                      input wire                  req_read,
                      input wire                  req_write,
                      output wire [DATA_WIDTH-1:0] data_out,
                      output reg                  not_empty,
                      output reg                  full		   
                      );


   reg [DATA_WIDTH-1:0]                buffer [BUFF_SIZE-1:0];


   reg [`CLOG2(BUFF_SIZE)-1:0]                                head, tail, next_head, next_tail;

   assign data_out = buffer[tail];

  
   
   always @(posedge clk)
     begin
        if(reset)
          begin
             head <= 0;
             tail <= 0;
             full <= 0;
             not_empty <= 0;
	     next_head <=0;
	     next_tail <=0;
	     

          end
        else
          begin

             full <= 0;
             not_empty <= 1;
	     head <= next_head;
	     tail <= next_tail;
	     


             if(head == tail)
               begin
                  not_empty <= 0;
               end
             if(head == tail-1)
               begin
                  full <= 1;
               end

             if(req_write)
               begin
                  buffer[head] <= data_in;
                  next_head <= head+1;
               end
             if(req_read)
               begin
                  next_tail <= tail+1;
               end
          end
     end
        endmodule
module CmdBuffer #(
                    parameter DATA_WIDTH = 10,
                    parameter BUFF_SIZE = 64
                    )(
                      input wire                  clk,
                      input wire                  reset,
                      input wire [DATA_WIDTH-1:0] data_in,
                      input wire                  req_read,
                      input wire                  req_write,
                      output wire [DATA_WIDTH-1:0] data_out,
                      output reg                  not_empty,
                      output reg                  full		   
                      );



   reg [DATA_WIDTH-1:0]                buffer [BUFF_SIZE-1:0];


   reg [`CLOG2(BUFF_SIZE)-1:0]                                head, tail, next_head, next_tail;

   assign data_out = buffer[tail];

  
   
   always @(posedge clk)
     begin
        if(reset)
          begin
             head <= 0;
             tail <= 0;
             full <= 0;
             not_empty <= 0;
	     next_head <=0;
	     next_tail <=0;
	     

          end
        else
          begin

             full <= 0;
             not_empty <= 1;
	     head <= next_head;
	     tail <= next_tail;
	     


             if(head == tail)
               begin
                  not_empty <= 0;
               end
             if(head == tail-1)
               begin
                  full <= 1;
               end

             if(req_write)
               begin
                  buffer[head] <= data_in;
                  next_head <= head+1;
               end
             if(req_read)
               begin
                  next_tail <= tail+1;
               end
          end
     end
        endmodule