data/full_repos/permissive/155656868/src/alu.v
data/verilator_xmls/8d7cb5c9-2462-42cc-8d47-980cd2fc6251.xml
module module_alu #(parameter BUS_WIDTH=32, OPCODE=3)
                   (input  [BUS_WIDTH-1:0] a_in, b_in,
                    input  [OPCODE-1:0] operation,
                    input  alu_en,
                    output [BUS_WIDTH-1:0] out,
                    output zero);


    parameter ADD = 3'b000;
    parameter SUB = 3'b001;
    parameter AND = 3'b011;
    parameter OR  = 3'b010;

    reg [BUS_WIDTH-1:0] result = 0;

    always @(operation or a_in or b_in) begin
        case (operation)
            ADD:     result <= a_in + b_in;
            SUB:     result <= a_in - b_in;
            AND:     result <= a_in & b_in;
            OR:      result <= a_in | b_in;
            default: result <= 0;
        endcase
    end

    assign out  = (alu_en == 1'b1) ? result : 0;
    assign zero = (result == 0) ? 1'b1 : 1'b0;

endmodule
module module_alu #(parameter BUS_WIDTH=32, OPCODE=3)
                   (input  [BUS_WIDTH-1:0] a_in, b_in,
                    input  [OPCODE-1:0] operation,
                    input  alu_en,
                    output [BUS_WIDTH-1:0] out,
                    output zero);



    parameter ADD = 3'b000;
    parameter SUB = 3'b001;
    parameter AND = 3'b011;
    parameter OR  = 3'b010;

    reg [BUS_WIDTH-1:0] result = 0;

    always @(operation or a_in or b_in) begin
        case (operation)
            ADD:     result <= a_in + b_in;
            SUB:     result <= a_in - b_in;
            AND:     result <= a_in & b_in;
            OR:      result <= a_in | b_in;
            default: result <= 0;
        endcase
    end

    assign out  = (alu_en == 1'b1) ? result : 0;
    assign zero = (result == 0) ? 1'b1 : 1'b0;

endmodule