data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/strobe_generator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_1_pow_5/common/synthesis/strobe_generator.v:23: Operator EQ expects 24 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                     : ... In instance strobe_generator\n            strobe <= (cnt [w - 1:0] == 1\'b0);\n                                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module strobe_generator
# (
    parameter w = 24
)
(
    input      clk,
    input      rst_n,
    output reg strobe
);

    reg [w - 1:0] cnt;

    always @ (posedge clk or negedge rst_n)
        if (! rst_n)
            cnt <= { w { 1'b0 } };
        else
            cnt <= cnt + 1'b1;

    always @ (posedge clk or negedge rst_n)
        if (! rst_n)
            strobe <= 1'b0;
        else
            strobe <= (cnt [w - 1:0] == 1'b0);

endmodule
module strobe_generator
# (
    parameter w = 24
)
(
    input      clk,
    input      rst_n,
    output reg strobe
);


    reg [w - 1:0] cnt;

    always @ (posedge clk or negedge rst_n)
        if (! rst_n)
            cnt <= { w { 1'b0 } };
        else
            cnt <= cnt + 1'b1;

    always @ (posedge clk or negedge rst_n)
        if (! rst_n)
            strobe <= 1'b0;
        else
            strobe <= (cnt [w - 1:0] == 1'b0);

endmodule