data/full_repos/permissive/129155059/proyecto-01/byte_joining/testbench.v
 line:750: before: "negedge"
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/testbench.v:7: Cannot find include file: sintetizado.v\n`include "sintetizado.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/byte_joining,data/full_repos/permissive/129155059/sintetizado.v\n             data/full_repos/permissive/129155059/proyecto-01/byte_joining,data/full_repos/permissive/129155059/sintetizado.v.v\n             data/full_repos/permissive/129155059/proyecto-01/byte_joining,data/full_repos/permissive/129155059/sintetizado.v.sv\n             sintetizado.v\n             sintetizado.v.v\n             sintetizado.v.sv\n             obj_dir/sintetizado.v\n             obj_dir/sintetizado.v.v\n             obj_dir/sintetizado.v.sv\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/testbench.v:8: Cannot find include file: memoria.v\n`include "memoria.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/testbench.v:10: Cannot find include file: cmos_cells_delay_cont.v\n`include "cmos_cells_delay_cont.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/testbench.v:11: Cannot find include file: bytejoining_cond.v\n`include "bytejoining_cond.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/testbench.v:12: Cannot find include file: tester.v\n`include "tester.v" \n         ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module Testbench;
	wire [7:0] byte_joining_desc_estruc;
	wire [7:0] byte_joining_desc_cond;
  wire [7:0] Lane_0;
  wire [7:0] Lane_1;
  wire [7:0] Lane_2;
  wire [7:0] Lane_3;
  wire clk250k;
	wire [1:0] ctr_3;



	byte_joining_conductual	bj_conduc(	.out		(byte_joining_desc_cond),
					.Lane_0		(Lane_0),
					.Lane_1		(Lane_1),
					.Lane_2		(Lane_2),
					.Lane_3		(Lane_3),
					.ctr_3		(ctr_3),
					.clk250k		(clk250k)
	);

	byte_joining_estructural	bj_estruc(	.out		(byte_joining_desc_estruc),
					.Lane_0		(Lane_0),
					.Lane_1		(Lane_1),
					.Lane_2		(Lane_2),
					.Lane_3		(Lane_3),
					.ctr_3		(ctr_3),
					.clk250k		(clk250k)
	);
	tester	tester_(	.byte_joining_desc_cond		(byte_joining_desc_cond),
					.byte_joining_desc_estruc		(byte_joining_desc_estruc),
					.Lane_0		(Lane_0),
          .Lane_1		(Lane_1),
          .Lane_2		(Lane_2),
          .Lane_3		(Lane_3),
					.ctr_3		(ctr_3),
					.clk250k		(clk250k)

	);

endmodule
module Testbench;

	wire [7:0] byte_joining_desc_estruc;
	wire [7:0] byte_joining_desc_cond;
  wire [7:0] Lane_0;
  wire [7:0] Lane_1;
  wire [7:0] Lane_2;
  wire [7:0] Lane_3;
  wire clk250k;
	wire [1:0] ctr_3;



	byte_joining_conductual	bj_conduc(	.out		(byte_joining_desc_cond),
					.Lane_0		(Lane_0),
					.Lane_1		(Lane_1),
					.Lane_2		(Lane_2),
					.Lane_3		(Lane_3),
					.ctr_3		(ctr_3),
					.clk250k		(clk250k)
	);

	byte_joining_estructural	bj_estruc(	.out		(byte_joining_desc_estruc),
					.Lane_0		(Lane_0),
					.Lane_1		(Lane_1),
					.Lane_2		(Lane_2),
					.Lane_3		(Lane_3),
					.ctr_3		(ctr_3),
					.clk250k		(clk250k)
	);
	tester	tester_(	.byte_joining_desc_cond		(byte_joining_desc_cond),
					.byte_joining_desc_estruc		(byte_joining_desc_estruc),
					.Lane_0		(Lane_0),
          .Lane_1		(Lane_1),
          .Lane_2		(Lane_2),
          .Lane_3		(Lane_3),
					.ctr_3		(ctr_3),
					.clk250k		(clk250k)

	);

endmodule