data/full_repos/permissive/174323821/hdl/clocking/jtframe_crossclk_cen.v
data/verilator_xmls/4a5a08ad-d7cb-4fd4-9390-8b9ab13e31b2.xml
module jtframe_crossclk_cen(
    input       clk_in,
    input       cen_in,
    input       clk_out,
    output reg  cen_out
);

reg flag;

initial begin
    flag    = 0;
    cen_out = 0;
end

always @(posedge clk_in) begin
    if( cen_in  ) flag <= 1;
    if( cen_out ) flag <= 0;
end

reg flag_l;

always @(posedge clk_out) begin
    flag_l  <= flag;
    cen_out <= flag && !flag_l;
end

endmodule
module jtframe_crossclk_cen(
    input       clk_in,
    input       cen_in,
    input       clk_out,
    output reg  cen_out
);


reg flag;

initial begin
    flag    = 0;
    cen_out = 0;
end

always @(posedge clk_in) begin
    if( cen_in  ) flag <= 1;
    if( cen_out ) flag <= 0;
end

reg flag_l;

always @(posedge clk_out) begin
    flag_l  <= flag;
    cen_out <= flag && !flag_l;
end

endmodule