data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:74: Cannot find include file: pci_constants.v\n`include "pci_constants.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/pci_constants.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/pci_constants.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/pci_constants.v.sv\n             pci_constants.v\n             pci_constants.v.v\n             pci_constants.v.sv\n             obj_dir/pci_constants.v\n             obj_dir/pci_constants.v.v\n             obj_dir/pci_constants.v.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:75: Cannot find include file: bus_commands.v\n`include "bus_commands.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:78: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:189: Define or directive not defined: \'`FF_DELAY\'\n        addr_out  <= #`FF_DELAY 32\'h0000_0000 ;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:190: Define or directive not defined: \'`FF_DELAY\'\n        be_out    <= #`FF_DELAY 4\'h0 ;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:191: Define or directive not defined: \'`FF_DELAY\'\n        we_out    <= #`FF_DELAY 1\'b0 ;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:192: Define or directive not defined: \'`FF_DELAY\'\n        bc_out    <= #`FF_DELAY `BC_RESERVED0 ;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:192: Define or directive not defined: \'`BC_RESERVED0\'\n        bc_out    <= #`FF_DELAY `BC_RESERVED0 ;\n                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:192: syntax error, unexpected \';\', expecting IDENTIFIER\n        bc_out    <= #`FF_DELAY `BC_RESERVED0 ;\n                                              ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:193: Define or directive not defined: \'`FF_DELAY\'\n        burst_out <= #`FF_DELAY 1\'b0 ;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:198: Define or directive not defined: \'`FF_DELAY\'\n            addr_out  <= #`FF_DELAY addr_in ;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:198: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            addr_out  <= #`FF_DELAY addr_in ;\n                                            ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:199: Define or directive not defined: \'`FF_DELAY\'\n            be_out    <= #`FF_DELAY be_in ;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:199: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            be_out    <= #`FF_DELAY be_in ;\n                                          ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:200: Define or directive not defined: \'`FF_DELAY\'\n            we_out    <= #`FF_DELAY we_in ;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:200: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            we_out    <= #`FF_DELAY we_in ;\n                                          ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:201: Define or directive not defined: \'`FF_DELAY\'\n            bc_out    <= #`FF_DELAY bc_in ;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:201: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            bc_out    <= #`FF_DELAY bc_in ;\n                                          ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:202: Define or directive not defined: \'`FF_DELAY\'\n            burst_out <= #`FF_DELAY burst_in ;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:202: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            burst_out <= #`FF_DELAY burst_in ;\n                                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:219: Define or directive not defined: \'`FF_DELAY\'\n        req_req_pending <= #`FF_DELAY 1\'b0 ;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:222: Define or directive not defined: \'`FF_DELAY\'\n        req_req_pending <= #`FF_DELAY 1\'b0 ;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:225: Define or directive not defined: \'`FF_DELAY\'\n        req_req_pending <= #`FF_DELAY 1\'b1 ;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:248: Define or directive not defined: \'`FF_DELAY\'\n        comp_req_pending <= #`FF_DELAY 1\'b0 ;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:251: Define or directive not defined: \'`FF_DELAY\'\n        comp_req_pending <= #`FF_DELAY 1\'b0 ;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:254: Define or directive not defined: \'`FF_DELAY\'\n        comp_req_pending <= #`FF_DELAY sync_comp_req_pending ;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:254: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        comp_req_pending <= #`FF_DELAY sync_comp_req_pending ;\n                                                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:272: Define or directive not defined: \'`FF_DELAY\'\n        comp_comp_pending <= #`FF_DELAY 1\'b0 ;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:275: Define or directive not defined: \'`FF_DELAY\'\n        comp_comp_pending <= #`FF_DELAY 1\'b0 ;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:278: Define or directive not defined: \'`FF_DELAY\'\n        comp_comp_pending <= #`FF_DELAY 1\'b1 ;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:302: Define or directive not defined: \'`FF_DELAY\'\n        req_comp_pending <= #`FF_DELAY 1\'b0 ;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:305: Define or directive not defined: \'`FF_DELAY\'\n        req_comp_pending <= #`FF_DELAY 1\'b0 ;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:308: Define or directive not defined: \'`FF_DELAY\'\n        req_comp_pending <= #`FF_DELAY sync_req_comp_pending ;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:308: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        req_comp_pending <= #`FF_DELAY sync_req_comp_pending ;\n                                                             ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:315: Define or directive not defined: \'`FF_DELAY\'\n        req_comp_pending_sample <= #`FF_DELAY 1\'b0 ;\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:317: Define or directive not defined: \'`FF_DELAY\'\n        req_comp_pending_sample <= #`FF_DELAY sync_req_comp_pending ;\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:317: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        req_comp_pending_sample <= #`FF_DELAY sync_req_comp_pending ;\n                                                                    ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:333: Define or directive not defined: \'`FF_DELAY\'\n        req_done_reg <= #`FF_DELAY 1\'b0 ;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:336: Define or directive not defined: \'`FF_DELAY\'\n        req_done_reg <= #`FF_DELAY 1\'b0 ;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:339: Define or directive not defined: \'`FF_DELAY\'\n        req_done_reg <= #`FF_DELAY 1\'b1 ;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:353: Define or directive not defined: \'`FF_DELAY\'\n        comp_done_reg_main <= #`FF_DELAY 1\'b0 ;\n                               ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:355: Define or directive not defined: \'`FF_DELAY\'\n        comp_done_reg_main <= #`FF_DELAY sync_comp_done ;\n                               ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:355: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        comp_done_reg_main <= #`FF_DELAY sync_comp_done ;\n                                                        ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:361: Define or directive not defined: \'`FF_DELAY\'\n        comp_done_reg_clr <= #`FF_DELAY 1\'b0 ;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:363: Define or directive not defined: \'`FF_DELAY\'\n        comp_done_reg_clr <= #`FF_DELAY comp_done_reg_main ;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:363: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        comp_done_reg_clr <= #`FF_DELAY comp_done_reg_main ;\n                                                           ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:380: Define or directive not defined: \'`FF_DELAY\'\n        comp_rty_exp_reg <= #`FF_DELAY 1\'b0 ;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:383: Define or directive not defined: \'`FF_DELAY\'\n        comp_rty_exp_reg <= #`FF_DELAY 1\'b0 ;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:386: Define or directive not defined: \'`FF_DELAY\'\n        comp_rty_exp_reg <= #`FF_DELAY 1\'b1 ;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v:402: Define or directive not defined: \'`FF_DELAY\'\n        req_rty_exp_reg <= #`FF_DELAY 1\'b0 ;\n                            ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module pci_delayed_sync
(
    reset_in,
    req_clk_in,
    comp_clk_in,
    req_in,
    comp_in,
    done_in,
    in_progress_in,
    comp_req_pending_out,
    req_req_pending_out,
    req_comp_pending_out,
    comp_comp_pending_out,
    addr_in,
    be_in,
    addr_out,
    be_out,
    we_in,
    we_out,
    bc_in,
    bc_out,
    status_in,
    status_out,
    comp_flush_out,
    burst_in,
    burst_out,
    retry_expired_in
);


input reset_in,
      req_clk_in,
      comp_clk_in ;


input req_in,
      comp_in,
      done_in,
      in_progress_in ;


output  comp_req_pending_out,
        req_req_pending_out,
        req_comp_pending_out,
        comp_comp_pending_out ;


reg     comp_req_pending,
        req_req_pending,
        req_comp_pending,
        req_comp_pending_sample,
        comp_comp_pending,
        req_done_reg,
        comp_done_reg_main,
        comp_done_reg_clr,
        req_rty_exp_reg,
        req_rty_exp_clr,
        comp_rty_exp_reg,
        comp_rty_exp_clr ;

wire    sync_comp_req_pending,
        sync_req_comp_pending,
        sync_comp_done,
        sync_req_rty_exp,
        sync_comp_rty_exp_clr ;




input [31:0]    addr_in ;
input [3:0]     be_in ;
input           we_in ;
input [3:0]     bc_in ;
input           burst_in ;



output [31:0]   addr_out ;
output [3:0]    be_out ;
output          we_out ;
output [3:0]    bc_out ;
output          burst_out ;


input          status_in ;
output         status_out ;




input   retry_expired_in ;


output  comp_flush_out ;


reg [31:0]   addr_out ;
reg [3:0]    be_out ;
reg          we_out ;
reg [3:0]    bc_out ;
reg          burst_out ;


wire new_request = req_in && ~req_comp_pending_out && ~req_req_pending_out ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if (reset_in)
    begin
        addr_out  <= #`FF_DELAY 32'h0000_0000 ;
        be_out    <= #`FF_DELAY 4'h0 ;
        we_out    <= #`FF_DELAY 1'b0 ;
        bc_out    <= #`FF_DELAY `BC_RESERVED0 ;
        burst_out <= #`FF_DELAY 1'b0 ;
    end
    else
        if (new_request)
        begin
            addr_out  <= #`FF_DELAY addr_in ;
            be_out    <= #`FF_DELAY be_in ;
            we_out    <= #`FF_DELAY we_in ;
            bc_out    <= #`FF_DELAY bc_in ;
            burst_out <= #`FF_DELAY burst_in ;
        end
end


reg [16:0] comp_cycle_count ;




wire req_req_clear = req_comp_pending || (req_rty_exp_reg && ~req_rty_exp_clr) ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_req_clear )
        req_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_in )
        req_req_pending <= #`FF_DELAY 1'b1 ;
end



pci_synchronizer_flop #(1, 0) req_sync
(
    .data_in        (req_req_pending),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_req_pending),
    .async_reset    (reset_in)
) ;


wire comp_req_pending_clear = comp_req_pending && ( comp_in || retry_expired_in) ;


wire comp_req_pending_ena   = ~comp_comp_pending && ~comp_done_reg_main && ~comp_rty_exp_reg ;


always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_req_pending_clear )
        comp_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_req_pending_ena )
        comp_req_pending <= #`FF_DELAY sync_comp_req_pending ;
end


assign comp_req_pending_out = comp_req_pending ;


assign req_req_pending_out  = req_req_pending ;



wire comp_comp_clear = comp_done_reg_main && ~comp_done_reg_clr ;
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_comp_clear )
        comp_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_in && comp_req_pending )
        comp_comp_pending <= #`FF_DELAY 1'b1 ;
end

assign comp_comp_pending_out = comp_comp_pending ;


pci_synchronizer_flop #(1, 0) comp_sync
(
    .data_in        (comp_comp_pending),
    .clk_out        (req_clk_in),
    .sync_data_out  (sync_req_comp_pending),
    .async_reset    (reset_in)
) ;


wire req_comp_pending_clear = done_in || comp_cycle_count[16];


wire req_comp_pending_ena   = ~req_done_reg ;


always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_comp_pending_clear )
        req_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_comp_pending_ena )
        req_comp_pending <= #`FF_DELAY sync_req_comp_pending ;
end


always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_comp_pending_sample <= #`FF_DELAY 1'b0 ;
    else
        req_comp_pending_sample <= #`FF_DELAY sync_req_comp_pending ;
end


assign req_comp_pending_out = req_comp_pending && ~req_req_pending ;




wire req_done_clear = ~req_comp_pending_sample ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_done_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( req_done_clear )
        req_done_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( done_in || comp_cycle_count[16] )
        req_done_reg <= #`FF_DELAY 1'b1 ;
end

pci_synchronizer_flop  #(1, 0) done_sync
(
    .data_in        (req_done_reg),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_done),
    .async_reset    (reset_in)
) ;

always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_done_reg_main <= #`FF_DELAY 1'b0 ;
    else
        comp_done_reg_main <= #`FF_DELAY sync_comp_done ;
end

always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_done_reg_clr <= #`FF_DELAY 1'b0 ;
    else
        comp_done_reg_clr <= #`FF_DELAY comp_done_reg_main ;
end



wire comp_rty_exp_clear = comp_rty_exp_clr && comp_rty_exp_reg ;





always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_rty_exp_clear )
        comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( retry_expired_in && comp_req_pending)
        comp_rty_exp_reg <= #`FF_DELAY 1'b1 ;
end


pci_synchronizer_flop #(1, 0) rty_exp_sync
(
    .data_in        (comp_rty_exp_reg),
    .clk_out        (req_clk_in),
    .sync_data_out  (sync_req_rty_exp),
    .async_reset    (reset_in)
) ;


always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_rty_exp_reg <= #`FF_DELAY 1'b0 ;
    else
        req_rty_exp_reg <= #`FF_DELAY sync_req_rty_exp ;
end

always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_rty_exp_clr <= #`FF_DELAY 1'b0 ;
    else
        req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ;
end

pci_synchronizer_flop #(1, 0) rty_exp_back_prop_sync
(
    .data_in        (req_rty_exp_reg && req_rty_exp_clr),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_rty_exp_clr),
    .async_reset    (reset_in)
) ;

always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_rty_exp_clr <= #`FF_DELAY 1'b0 ;
    else
        comp_rty_exp_clr <= #`FF_DELAY sync_comp_rty_exp_clr ;
end


reg status_out ;
always@(posedge comp_clk_in or posedge reset_in)
begin
    if (reset_in)
        status_out <= #`FF_DELAY 1'b0 ;
    else
    if (comp_in && comp_req_pending)
        status_out <= #`FF_DELAY status_in ;
end





wire clear_count = in_progress_in || ~req_comp_pending_out || comp_cycle_count[16] ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if (reset_in)
        comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
    else
    if (clear_count)
        comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
    else
        comp_cycle_count <= #`FF_DELAY comp_cycle_count + 1'b1 ;
end



reg comp_flush_out ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if (reset_in)
        comp_flush_out <= #`FF_DELAY 1'b0 ;
    else
        comp_flush_out <= #`FF_DELAY comp_cycle_count[16] ;
end

endmodule
module pci_delayed_sync
(
    reset_in,
    req_clk_in,
    comp_clk_in,
    req_in,
    comp_in,
    done_in,
    in_progress_in,
    comp_req_pending_out,
    req_req_pending_out,
    req_comp_pending_out,
    comp_comp_pending_out,
    addr_in,
    be_in,
    addr_out,
    be_out,
    we_in,
    we_out,
    bc_in,
    bc_out,
    status_in,
    status_out,
    comp_flush_out,
    burst_in,
    burst_out,
    retry_expired_in
);



input reset_in,
      req_clk_in,
      comp_clk_in ;


input req_in,
      comp_in,
      done_in,
      in_progress_in ;


output  comp_req_pending_out,
        req_req_pending_out,
        req_comp_pending_out,
        comp_comp_pending_out ;


reg     comp_req_pending,
        req_req_pending,
        req_comp_pending,
        req_comp_pending_sample,
        comp_comp_pending,
        req_done_reg,
        comp_done_reg_main,
        comp_done_reg_clr,
        req_rty_exp_reg,
        req_rty_exp_clr,
        comp_rty_exp_reg,
        comp_rty_exp_clr ;

wire    sync_comp_req_pending,
        sync_req_comp_pending,
        sync_comp_done,
        sync_req_rty_exp,
        sync_comp_rty_exp_clr ;




input [31:0]    addr_in ;
input [3:0]     be_in ;
input           we_in ;
input [3:0]     bc_in ;
input           burst_in ;



output [31:0]   addr_out ;
output [3:0]    be_out ;
output          we_out ;
output [3:0]    bc_out ;
output          burst_out ;


input          status_in ;
output         status_out ;




input   retry_expired_in ;


output  comp_flush_out ;


reg [31:0]   addr_out ;
reg [3:0]    be_out ;
reg          we_out ;
reg [3:0]    bc_out ;
reg          burst_out ;


wire new_request = req_in && ~req_comp_pending_out && ~req_req_pending_out ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if (reset_in)
    begin
        addr_out  <= #`FF_DELAY 32'h0000_0000 ;
        be_out    <= #`FF_DELAY 4'h0 ;
        we_out    <= #`FF_DELAY 1'b0 ;
        bc_out    <= #`FF_DELAY `BC_RESERVED0 ;
        burst_out <= #`FF_DELAY 1'b0 ;
    end
    else
        if (new_request)
        begin
            addr_out  <= #`FF_DELAY addr_in ;
            be_out    <= #`FF_DELAY be_in ;
            we_out    <= #`FF_DELAY we_in ;
            bc_out    <= #`FF_DELAY bc_in ;
            burst_out <= #`FF_DELAY burst_in ;
        end
end


reg [16:0] comp_cycle_count ;




wire req_req_clear = req_comp_pending || (req_rty_exp_reg && ~req_rty_exp_clr) ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_req_clear )
        req_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_in )
        req_req_pending <= #`FF_DELAY 1'b1 ;
end



pci_synchronizer_flop #(1, 0) req_sync
(
    .data_in        (req_req_pending),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_req_pending),
    .async_reset    (reset_in)
) ;


wire comp_req_pending_clear = comp_req_pending && ( comp_in || retry_expired_in) ;


wire comp_req_pending_ena   = ~comp_comp_pending && ~comp_done_reg_main && ~comp_rty_exp_reg ;


always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_req_pending_clear )
        comp_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_req_pending_ena )
        comp_req_pending <= #`FF_DELAY sync_comp_req_pending ;
end


assign comp_req_pending_out = comp_req_pending ;


assign req_req_pending_out  = req_req_pending ;



wire comp_comp_clear = comp_done_reg_main && ~comp_done_reg_clr ;
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_comp_clear )
        comp_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_in && comp_req_pending )
        comp_comp_pending <= #`FF_DELAY 1'b1 ;
end

assign comp_comp_pending_out = comp_comp_pending ;


pci_synchronizer_flop #(1, 0) comp_sync
(
    .data_in        (comp_comp_pending),
    .clk_out        (req_clk_in),
    .sync_data_out  (sync_req_comp_pending),
    .async_reset    (reset_in)
) ;


wire req_comp_pending_clear = done_in || comp_cycle_count[16];


wire req_comp_pending_ena   = ~req_done_reg ;


always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_comp_pending_clear )
        req_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_comp_pending_ena )
        req_comp_pending <= #`FF_DELAY sync_req_comp_pending ;
end


always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_comp_pending_sample <= #`FF_DELAY 1'b0 ;
    else
        req_comp_pending_sample <= #`FF_DELAY sync_req_comp_pending ;
end


assign req_comp_pending_out = req_comp_pending && ~req_req_pending ;




wire req_done_clear = ~req_comp_pending_sample ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_done_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( req_done_clear )
        req_done_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( done_in || comp_cycle_count[16] )
        req_done_reg <= #`FF_DELAY 1'b1 ;
end

pci_synchronizer_flop  #(1, 0) done_sync
(
    .data_in        (req_done_reg),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_done),
    .async_reset    (reset_in)
) ;

always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_done_reg_main <= #`FF_DELAY 1'b0 ;
    else
        comp_done_reg_main <= #`FF_DELAY sync_comp_done ;
end

always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_done_reg_clr <= #`FF_DELAY 1'b0 ;
    else
        comp_done_reg_clr <= #`FF_DELAY comp_done_reg_main ;
end



wire comp_rty_exp_clear = comp_rty_exp_clr && comp_rty_exp_reg ;





always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_rty_exp_clear )
        comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( retry_expired_in && comp_req_pending)
        comp_rty_exp_reg <= #`FF_DELAY 1'b1 ;
end


pci_synchronizer_flop #(1, 0) rty_exp_sync
(
    .data_in        (comp_rty_exp_reg),
    .clk_out        (req_clk_in),
    .sync_data_out  (sync_req_rty_exp),
    .async_reset    (reset_in)
) ;


always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_rty_exp_reg <= #`FF_DELAY 1'b0 ;
    else
        req_rty_exp_reg <= #`FF_DELAY sync_req_rty_exp ;
end

always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_rty_exp_clr <= #`FF_DELAY 1'b0 ;
    else
        req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ;
end

pci_synchronizer_flop #(1, 0) rty_exp_back_prop_sync
(
    .data_in        (req_rty_exp_reg && req_rty_exp_clr),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_rty_exp_clr),
    .async_reset    (reset_in)
) ;

always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_rty_exp_clr <= #`FF_DELAY 1'b0 ;
    else
        comp_rty_exp_clr <= #`FF_DELAY sync_comp_rty_exp_clr ;
end


reg status_out ;
always@(posedge comp_clk_in or posedge reset_in)
begin
    if (reset_in)
        status_out <= #`FF_DELAY 1'b0 ;
    else
    if (comp_in && comp_req_pending)
        status_out <= #`FF_DELAY status_in ;
end





wire clear_count = in_progress_in || ~req_comp_pending_out || comp_cycle_count[16] ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if (reset_in)
        comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
    else
    if (clear_count)
        comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
    else
        comp_cycle_count <= #`FF_DELAY comp_cycle_count + 1'b1 ;
end



reg comp_flush_out ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if (reset_in)
        comp_flush_out <= #`FF_DELAY 1'b0 ;
    else
        comp_flush_out <= #`FF_DELAY comp_cycle_count[16] ;
end

endmodule