data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v
1: b'%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:15: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_1, net_2, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:16: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_1, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:17: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(gnd, y, net_2);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:18: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_2, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:19: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_2, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:20: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, vdd, net_2);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:32: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_3, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:33: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_4, ab);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:34: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_3, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:35: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(net_4, y, bb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:36: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(gnd, bb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:37: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, ab, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:38: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, net_7, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:39: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_7, vdd, ab);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:40: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, net_8, bb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:41: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_8, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:42: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(bb, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:43: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(ab, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:64: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, y, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:65: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:77: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_5, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:78: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_5, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:79: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:80: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:92: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, y, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:93: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:94: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, net_9, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:95: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_9, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:144: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_15, net_4, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:145: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(net_4, y, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:146: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(gnd, net_15, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:147: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:148: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(y, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:149: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, vdd, a);\n          ^~~~~~\n%Error: Exiting due to 34 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module wordlib8__PPGen_9bits(Double, Negate, Single, Y, PP, Sign);
  input Double;
  input Negate;
  input Single;
  input [7:0] Y;
  output [8:0] PP;
  output Sign;

  supply1 vdd;
  supply0 gnd;
  wire HalfAdde_8_Cout, net_111, net_113, net_168, net_177, net_51, net_52;
  wire net_53, net_54, net_55, net_56, net_57, net_58, net_59, net_64, net_69;
  wire net_74, net_79, net_84, net_92;

  wordlib8__HalfAdder HalfAdde_0(.A(net_58), .Cin(net_59), .Cout(net_113), 
      .Sum(PP[7]));
  wordlib8__HalfAdder HalfAdde_1(.A(net_57), .Cin(net_64), .Cout(net_59), 
      .Sum(PP[6]));
  wordlib8__HalfAdder HalfAdde_2(.A(net_56), .Cin(net_69), .Cout(net_64), 
      .Sum(PP[5]));
  wordlib8__HalfAdder HalfAdde_3(.A(net_55), .Cin(net_74), .Cout(net_69), 
      .Sum(PP[4]));
  wordlib8__HalfAdder HalfAdde_4(.A(net_54), .Cin(net_79), .Cout(net_74), 
      .Sum(PP[3]));
  wordlib8__HalfAdder HalfAdde_5(.A(net_53), .Cin(net_84), .Cout(net_79), 
      .Sum(PP[2]));
  wordlib8__HalfAdder HalfAdde_6(.A(net_52), .Cin(net_92), .Cout(net_84), 
      .Sum(PP[1]));
  wordlib8__HalfAdder HalfAdde_7(.A(net_51), .Cin(Negate), .Cout(net_92), 
      .Sum(PP[0]));
  wordlib8__HalfAdder HalfAdde_8(.A(net_111), .Cin(net_113), 
      .Cout(HalfAdde_8_Cout), .Sum(PP[8]));
  wordlib8__NAND8_reducer NAND8_re_0(.inY(Y[7:0]), .reduced_AND(net_177));
  wordlib8__PPGen_1bit PPGen_1b_0(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[7]), .Yi_m1(Y[6]), .PPi(net_58));
  wordlib8__PPGen_1bit PPGen_1b_1(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[6]), .Yi_m1(Y[5]), .PPi(net_57));
  wordlib8__PPGen_1bit PPGen_1b_2(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[5]), .Yi_m1(Y[4]), .PPi(net_56));
  wordlib8__PPGen_1bit PPGen_1b_3(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[4]), .Yi_m1(Y[3]), .PPi(net_55));
  wordlib8__PPGen_1bit PPGen_1b_4(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[3]), .Yi_m1(Y[2]), .PPi(net_54));
  wordlib8__PPGen_1bit PPGen_1b_5(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[2]), .Yi_m1(Y[1]), .PPi(net_53));
  wordlib8__PPGen_1bit PPGen_1b_6(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[1]), .Yi_m1(Y[0]), .PPi(net_52));
  wordlib8__PPGen_1bit PPGen_1b_7(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[0]), .Yi_m1(gnd), .PPi(net_51));
  wordlib8__PPGen_1bit PPGen_1b_8(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[7]), .Yi_m1(Y[7]), .PPi(net_111));
  muddlib07__and2_1x and2_1x_0(.a(net_168), .b(PP[8]), .y(Sign));
  muddlib07__nand3_1x nand3_1x_0(.a(net_177), .b(Negate), .c(Double), 
      .y(net_168));
endmodule
module wordlib8__PPGen_9bits(Double, Negate, Single, Y, PP, Sign);

  input Double;
  input Negate;
  input Single;
  input [7:0] Y;
  output [8:0] PP;
  output Sign;

  supply1 vdd;
  supply0 gnd;
  wire HalfAdde_8_Cout, net_111, net_113, net_168, net_177, net_51, net_52;
  wire net_53, net_54, net_55, net_56, net_57, net_58, net_59, net_64, net_69;
  wire net_74, net_79, net_84, net_92;

  wordlib8__HalfAdder HalfAdde_0(.A(net_58), .Cin(net_59), .Cout(net_113), 
      .Sum(PP[7]));
  wordlib8__HalfAdder HalfAdde_1(.A(net_57), .Cin(net_64), .Cout(net_59), 
      .Sum(PP[6]));
  wordlib8__HalfAdder HalfAdde_2(.A(net_56), .Cin(net_69), .Cout(net_64), 
      .Sum(PP[5]));
  wordlib8__HalfAdder HalfAdde_3(.A(net_55), .Cin(net_74), .Cout(net_69), 
      .Sum(PP[4]));
  wordlib8__HalfAdder HalfAdde_4(.A(net_54), .Cin(net_79), .Cout(net_74), 
      .Sum(PP[3]));
  wordlib8__HalfAdder HalfAdde_5(.A(net_53), .Cin(net_84), .Cout(net_79), 
      .Sum(PP[2]));
  wordlib8__HalfAdder HalfAdde_6(.A(net_52), .Cin(net_92), .Cout(net_84), 
      .Sum(PP[1]));
  wordlib8__HalfAdder HalfAdde_7(.A(net_51), .Cin(Negate), .Cout(net_92), 
      .Sum(PP[0]));
  wordlib8__HalfAdder HalfAdde_8(.A(net_111), .Cin(net_113), 
      .Cout(HalfAdde_8_Cout), .Sum(PP[8]));
  wordlib8__NAND8_reducer NAND8_re_0(.inY(Y[7:0]), .reduced_AND(net_177));
  wordlib8__PPGen_1bit PPGen_1b_0(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[7]), .Yi_m1(Y[6]), .PPi(net_58));
  wordlib8__PPGen_1bit PPGen_1b_1(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[6]), .Yi_m1(Y[5]), .PPi(net_57));
  wordlib8__PPGen_1bit PPGen_1b_2(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[5]), .Yi_m1(Y[4]), .PPi(net_56));
  wordlib8__PPGen_1bit PPGen_1b_3(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[4]), .Yi_m1(Y[3]), .PPi(net_55));
  wordlib8__PPGen_1bit PPGen_1b_4(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[3]), .Yi_m1(Y[2]), .PPi(net_54));
  wordlib8__PPGen_1bit PPGen_1b_5(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[2]), .Yi_m1(Y[1]), .PPi(net_53));
  wordlib8__PPGen_1bit PPGen_1b_6(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[1]), .Yi_m1(Y[0]), .PPi(net_52));
  wordlib8__PPGen_1bit PPGen_1b_7(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[0]), .Yi_m1(gnd), .PPi(net_51));
  wordlib8__PPGen_1bit PPGen_1b_8(.Double(Double), .Negate(Negate), 
      .Single(Single), .Yi(Y[7]), .Yi_m1(Y[7]), .PPi(net_111));
  muddlib07__and2_1x and2_1x_0(.a(net_168), .b(PP[8]), .y(Sign));
  muddlib07__nand3_1x nand3_1x_0(.a(net_177), .b(Negate), .c(Double), 
      .y(net_168));
endmodule