data/full_repos/permissive/175122930/buffer_tb.v
1: b'%Error: data/full_repos/permissive/175122930/buffer_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("buffer_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/175122930/buffer_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars (1, buffer_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/175122930/buffer_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/175122930/buffer_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/buffer_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/buffer_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/buffer_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/buffer_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/buffer_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/buffer_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/buffer_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/buffer_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #2\n  ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module buffer_tb ();
	reg write_clock;
	reg [7:0] write_data;
	reg [7:0] write_addr;

	reg read_clock;
	wire [7:0] read_data;
	reg [7:0] read_addr;

	buffer #(.AW(8), .DW(8))
		MEM (
			.clock(clock),
			.write_clock_enable(read_clock_enable),
			.write_data(write_data),
			.write_addr(write_addr),
			.read_clock_enable(read_clock_enable),
			.read_data(read_data),
			.read_addr(read_addr));

	initial begin
		$dumpfile ("buffer_tb.vcd");
		$dumpvars (1, buffer_tb);
		#1;
		write_addr = 0;
		write_data = 'hf1;
		write_clock = 1;
		#1;
		write_clock = 0;
		#1;
		read_addr = 0;
		read_clock = 1;
		#1;
		read_clock = 0;
		if (read_data != 'hf1) begin
			$display("wrong data read at addr %x. expect data: %x, but read %x", read_addr, 'hf1, read_data);
			$stop;
		end
		#1;


		write_data = 'hee;
		read_clock = 1;
		#1;
		read_clock = 0;
		#1;
		if (read_data != 'hf1) begin
			$display("read data changed even write_clock wasn\'t triggered. read addr %x. expect data: %x, but read %x", read_addr, 'hf1, read_data);
			$stop;
		end

		#1;
		write_clock = 1;

		if (read_data != 'hf1) begin
			$display("read data changed even read_clock wasn\'t triggered. read addr %x. expect data: %x, but read %x", read_addr, 'hf1, read_data);
			$stop;
		end

		#2;
		read_clock = 1;
		#2
		read_clock = 0;
		if (read_data != 'hee) begin
			$display("read wrong data. read addr %x. expect data: %x, but read %x", read_addr, 'hee, read_data);
			$stop;
		end

		$finish;
	end
endmodule
module buffer_tb ();

	reg write_clock;
	reg [7:0] write_data;
	reg [7:0] write_addr;

	reg read_clock;
	wire [7:0] read_data;
	reg [7:0] read_addr;

	buffer #(.AW(8), .DW(8))
		MEM (
			.clock(clock),
			.write_clock_enable(read_clock_enable),
			.write_data(write_data),
			.write_addr(write_addr),
			.read_clock_enable(read_clock_enable),
			.read_data(read_data),
			.read_addr(read_addr));

	initial begin
		$dumpfile ("buffer_tb.vcd");
		$dumpvars (1, buffer_tb);
		#1;
		write_addr = 0;
		write_data = 'hf1;
		write_clock = 1;
		#1;
		write_clock = 0;
		#1;
		read_addr = 0;
		read_clock = 1;
		#1;
		read_clock = 0;
		if (read_data != 'hf1) begin
			$display("wrong data read at addr %x. expect data: %x, but read %x", read_addr, 'hf1, read_data);
			$stop;
		end
		#1;


		write_data = 'hee;
		read_clock = 1;
		#1;
		read_clock = 0;
		#1;
		if (read_data != 'hf1) begin
			$display("read data changed even write_clock wasn\'t triggered. read addr %x. expect data: %x, but read %x", read_addr, 'hf1, read_data);
			$stop;
		end

		#1;
		write_clock = 1;

		if (read_data != 'hf1) begin
			$display("read data changed even read_clock wasn\'t triggered. read addr %x. expect data: %x, but read %x", read_addr, 'hf1, read_data);
			$stop;
		end

		#2;
		read_clock = 1;
		#2
		read_clock = 0;
		if (read_data != 'hee) begin
			$display("read wrong data. read addr %x. expect data: %x, but read %x", read_addr, 'hee, read_data);
			$stop;
		end

		$finish;
	end
endmodule