data/full_repos/permissive/175808891/verilog/rv32cpu.v
1: b"%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:234: syntax error, unexpected type\n    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));\n                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:285: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\nmodule shifter(input[31:0] a, input [4:0] shamt, input[1:0] type,  output [31:0] r);\n                                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:288: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:343: syntax error, unexpected ',', expecting IDENTIFIER or do or final\n input   wire            int,\n                            ^\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:345: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input   wire            nmi\n ^~~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:369: syntax error, unexpected always\nalways @(posedge clk or posedge rst)\n^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module IMMGen (
    input  wire [31:0]  IR,
    output reg  [31:0]  Imm
);

always @(*) begin
	case (`OPCODE)
		`OPCODE_Arith_I   : 	Imm = { {21{IR[31]}}, IR[30:25], IR[24:21], IR[20] };
		`OPCODE_Store     :     Imm = { {21{IR[31]}}, IR[30:25], IR[11:8], IR[7] };
		`OPCODE_LUI       :     Imm = { IR[31], IR[30:20], IR[19:12], 12'b0 };
		`OPCODE_AUIPC     :     Imm = { IR[31], IR[30:20], IR[19:12], 12'b0 };
		`OPCODE_JAL       : 	Imm = { {12{IR[31]}}, IR[19:12], IR[20], IR[30:25], IR[24:21], 1'b0 };
		`OPCODE_JALR      : 	Imm = { {21{IR[31]}}, IR[30:25], IR[24:21], IR[20] };
		`OPCODE_Branch    : 	Imm = { {20{IR[31]}}, IR[7], IR[30:25], IR[11:8], 1'b0};
		default           : 	Imm = { {21{IR[31]}}, IR[30:25], IR[24:21], IR[20] };
	endcase 
end

endmodule
module IMMGen (
    input  wire [31:0]  IR,
    output reg  [31:0]  Imm
);


always @(*) begin
	case (`OPCODE)
		`OPCODE_Arith_I   : 	Imm = { {21{IR[31]}}, IR[30:25], IR[24:21], IR[20] };
		`OPCODE_Store     :     Imm = { {21{IR[31]}}, IR[30:25], IR[11:8], IR[7] };
		`OPCODE_LUI       :     Imm = { IR[31], IR[30:20], IR[19:12], 12'b0 };
		`OPCODE_AUIPC     :     Imm = { IR[31], IR[30:20], IR[19:12], 12'b0 };
		`OPCODE_JAL       : 	Imm = { {12{IR[31]}}, IR[19:12], IR[20], IR[30:25], IR[24:21], 1'b0 };
		`OPCODE_JALR      : 	Imm = { {21{IR[31]}}, IR[30:25], IR[24:21], IR[20] };
		`OPCODE_Branch    : 	Imm = { {20{IR[31]}}, IR[7], IR[30:25], IR[11:8], 1'b0};
		default           : 	Imm = { {21{IR[31]}}, IR[30:25], IR[24:21], IR[20] };
	endcase 
end

endmodule