data/full_repos/permissive/198548420/nexys4ddr/ch04_counter_verilog/counter.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/12a9e649-f003-4523-86f0-c3245832b620.xml
module counter(
    input BTNC,
    output reg [3:0] Q
    );
	 
always @(posedge BTNC)
begin
	Q <= Q + 1;
end

endmodule
module counter(
    input BTNC,
    output reg [3:0] Q
    );

	 
always @(posedge BTNC)
begin
	Q <= Q + 1;
end

endmodule