data/full_repos/permissive/148324174/CombLogic/alu.v
data/verilator_xmls/0c314843-86b0-42c8-b703-6269507d2eb0.xml
module alu(
	output reg [7:0] out,
	input [2:0] opcode,
	input [7:0] a,b
	);

always @(opcode, a, b) begin
	case(opcode)
		`PLUS: out = a+b;
		`MINUS: out = a-b;
		`BAND: out = a&b;
		`BOR: out = a|b;
		`BINV: out = ~out;
		default: out = 8'hx;
	endcase
end

endmodule
module alu(
	output reg [7:0] out,
	input [2:0] opcode,
	input [7:0] a,b
	);


always @(opcode, a, b) begin
	case(opcode)
		`PLUS: out = a+b;
		`MINUS: out = a-b;
		`BAND: out = a&b;
		`BOR: out = a|b;
		`BINV: out = ~out;
		default: out = 8'hx;
	endcase
end

endmodule