data/full_repos/permissive/125927162/SPI/SPI_SLAVE_tb.v
 line:49: before: "$"
1: b'%Error: data/full_repos/permissive/125927162/SPI/SPI_SLAVE_tb.v:27: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("SPI_SLAVE.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/SPI/SPI_SLAVE_tb.v:28: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, DUT);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_SLAVE_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_SLAVE_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_SLAVE_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #19\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_SLAVE_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #2\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_SLAVE_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #17\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_SLAVE_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n      #80\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_SLAVE_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n   always #1 sclk = !sclk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_SLAVE_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n   always #2 begin\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SPI/SPI_SLAVE_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n   always #3\n          ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SPI_SLAVE_tb();
   localparam data = 8'hC5;
   localparam BITS = 8;
   
   reg sclk;
   reg ss_n;
   reg mosi;
   wire miso;
   reg 	latch;
   
   reg [BITS - 1:0] mdata;
   reg [BITS - 1:0] sdata;

   reg [BITS - 1:0] readData;
   
   SPI_SLAVE #(.BITS(BITS))
   DUT (
	.sclk(sclk),
	.ss_n(ss_n),
	.mosi(mosi),
	.miso(miso),
	.latch(latch),
	.inData(sdata)
	);
   
   initial begin
      $dumpfile("SPI_SLAVE.vcd");
      $dumpvars(0, DUT);
      readData = 8'bX;
      sdata = 8'h65;
      mdata = data;
      latch = 1;
      #1
	latch = 0;
      #1
      sdata = 0;
      sclk = 0;
      ss_n = 0;
      #19
      mdata = readData;
      ss_n = 1;
      #2
	ss_n = 0;
      #17
	ss_n = 1;
      
      
      #80
	$finish;      
   end

   always #1 sclk = !sclk;
   always #2 begin
      mosi <= mdata[BITS - 1];
      mdata[BITS - 1:1] <= mdata[BITS - 2:0];
      readData[BITS - 1:1] <= readData[BITS - 2:0];
      readData[0] <= miso;
   end
   always #3
      mdata[0] <= miso;
endmodule
module SPI_SLAVE_tb();

   localparam data = 8'hC5;
   localparam BITS = 8;
   
   reg sclk;
   reg ss_n;
   reg mosi;
   wire miso;
   reg 	latch;
   
   reg [BITS - 1:0] mdata;
   reg [BITS - 1:0] sdata;

   reg [BITS - 1:0] readData;
   
   SPI_SLAVE #(.BITS(BITS))
   DUT (
	.sclk(sclk),
	.ss_n(ss_n),
	.mosi(mosi),
	.miso(miso),
	.latch(latch),
	.inData(sdata)
	);
   
   initial begin
      $dumpfile("SPI_SLAVE.vcd");
      $dumpvars(0, DUT);
      readData = 8'bX;
      sdata = 8'h65;
      mdata = data;
      latch = 1;
      #1
	latch = 0;
      #1
      sdata = 0;
      sclk = 0;
      ss_n = 0;
      #19
      mdata = readData;
      ss_n = 1;
      #2
	ss_n = 0;
      #17
	ss_n = 1;
      
      
      #80
	$finish;      
   end

   always #1 sclk = !sclk;
   always #2 begin
      mosi <= mdata[BITS - 1];
      mdata[BITS - 1:1] <= mdata[BITS - 2:0];
      readData[BITS - 1:1] <= readData[BITS - 2:0];
      readData[0] <= miso;
   end
   always #3
      mdata[0] <= miso;
endmodule