data/full_repos/permissive/118800618/ADC32.v
1: b'%Warning-WIDTH: data/full_repos/permissive/118800618/ADC32.v:27: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'CI\' generates 1 bits.\n                                                               : ... In instance ADC32\n assign S = A + B + CI + {33{CI}} - {32{CI}};\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ADC32(input [31:0] A,
			 input [31:0] B, 
			 input CI,
			 output [32:0] S
			); 

	assign S = A + B + CI + {33{CI}} - {32{CI}};

endmodule
module ADC32(input [31:0] A,
			 input [31:0] B, 
			 input CI,
			 output [32:0] S
			);
 

	assign S = A + B + CI + {33{CI}} - {32{CI}};

endmodule