data/full_repos/permissive/260351496/src/clk_prescaler.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/899282cd-ab35-4f6a-ba44-89325acc6af0.xml
module clk_prescaler(i_clk, i_arst, i_on, i_divide_by, o_clk_enable);

input i_clk;
input i_arst;
input i_on;
input [6:0] i_divide_by;
output o_clk_enable;

reg [6:0] counter;
reg [6:0] buffer;

assign o_clk_enable = (i_on & (counter == buffer));

always @(posedge i_clk, posedge i_arst, negedge i_on) begin
	if(i_arst) begin
		buffer <= {7{1'b0}};
	end else if(~i_on) begin
		buffer <= {7{1'b0}};
	end else begin
		buffer <= i_divide_by;
	end
end

wire is_not_changed;
assign is_not_changed = (buffer == i_divide_by);
																
reg is_not_changed_state;

always @(negedge is_not_changed) begin			
	is_not_changed_state <= 1'b1;
	counter <= {7{1'b0}};
end				

always @(posedge i_clk, posedge i_arst, negedge i_on) begin
	if(i_arst) begin
		counter <= {7{1'b0}};
	end else if(~i_on) begin
		counter <= {7{1'b0}};
	end else if(is_not_changed_state) begin		
		counter <= {7{1'b0}};			
		is_not_changed_state <= 1'b0;		
	end else begin
		if(o_clk_enable) begin			
			counter <= {7{1'b0}};
		end else begin
			if(i_on) begin
				counter <= counter + 1'b1;
			end else begin
				counter <= {7{1'b0}};
			end
		end
	end
end
endmodule
module clk_prescaler(i_clk, i_arst, i_on, i_divide_by, o_clk_enable);


input i_clk;
input i_arst;
input i_on;
input [6:0] i_divide_by;
output o_clk_enable;

reg [6:0] counter;
reg [6:0] buffer;

assign o_clk_enable = (i_on & (counter == buffer));

always @(posedge i_clk, posedge i_arst, negedge i_on) begin
	if(i_arst) begin
		buffer <= {7{1'b0}};
	end else if(~i_on) begin
		buffer <= {7{1'b0}};
	end else begin
		buffer <= i_divide_by;
	end
end

wire is_not_changed;
assign is_not_changed = (buffer == i_divide_by);
																
reg is_not_changed_state;

always @(negedge is_not_changed) begin			
	is_not_changed_state <= 1'b1;
	counter <= {7{1'b0}};
end				

always @(posedge i_clk, posedge i_arst, negedge i_on) begin
	if(i_arst) begin
		counter <= {7{1'b0}};
	end else if(~i_on) begin
		counter <= {7{1'b0}};
	end else if(is_not_changed_state) begin		
		counter <= {7{1'b0}};			
		is_not_changed_state <= 1'b0;		
	end else begin
		if(o_clk_enable) begin			
			counter <= {7{1'b0}};
		end else begin
			if(i_on) begin
				counter <= counter + 1'b1;
			end else begin
				counter <= {7{1'b0}};
			end
		end
	end
end
endmodule