data/full_repos/permissive/158845296/data_mem_ctrl.v
1: b'%Error: data/full_repos/permissive/158845296/data_mem_ctrl.v:45: syntax error, unexpected byte\n        .byte         (cache_byte),      \n         ^~~~\n%Error: Exiting due to 1 error(s)\n'
module data_mem_ctrl
(
    input         clock,
    input         reset,
    input         read,
    input         write,
    input         byte_access,
    input  [31:0] address,
    input  [31:0] write_data,
    output [31:0] read_data,
    output        stall
);


    wire  [1:0] cache_line;
    wire  [1:0] cache_word;
    wire  [1:0] cache_byte;
    wire [25:0] cache_tag_in;


    wire         cache_hit;
    wire         cache_dirty;
    wire         cache_valid;
    wire [127:0] cache_block;
    wire  [25:0] cache_tag_out;


    wire         mem_read;
    wire [127:0] mem_read_data;
    wire         mem_read_valid;
    wire         mem_write;
    wire [31:0]  mem_write_addr;
    wire         mem_write_done;


    cache d_cache
    (
        .clock        (clock),
        .reset        (reset),
        .write_word   (write),
        .write_block  (mem_read_valid),
        .byte_access  (byte_access),
        .index        (cache_line),
        .word         (cache_word),
        .byte         (cache_byte),
        .tag_in       (cache_tag_in),
        .word_in      (write_data),
        .block_in     (mem_read_data),
        .hit          (cache_hit),
        .dirty        (cache_dirty),
        .word_out     (read_data),
        .word_valid   (cache_valid),
        .block_out    (cache_block),
        .tag_out      (cache_tag_out)
    );

    data_mem d_mem
    (
        .clock          (clock),
        .read           (mem_read),
        .write          (mem_write),
        .write_address  (mem_write_addr),
        .read_address   (address),
        .write_data     (cache_block),
        .read_data      (mem_read_data),
        .write_done     (mem_write_done),
        .read_valid     (mem_read_valid)
    );


    assign cache_tag_in = address[31:6];
    assign cache_line   = address[5:4];
    assign cache_word   = address[3:2];
    assign cache_byte   = address[1:0];


    assign mem_read  = (read | write) & (~cache_hit | ~cache_valid);
    assign mem_write = (read | write) & (~cache_hit && cache_dirty);
    assign mem_write_addr = {cache_tag_out, 6'b0};


    assign stall = mem_read || mem_write;

endmodule
module data_mem_ctrl
(
    input         clock,
    input         reset,
    input         read,
    input         write,
    input         byte_access,
    input  [31:0] address,
    input  [31:0] write_data,
    output [31:0] read_data,
    output        stall
);



    wire  [1:0] cache_line;
    wire  [1:0] cache_word;
    wire  [1:0] cache_byte;
    wire [25:0] cache_tag_in;


    wire         cache_hit;
    wire         cache_dirty;
    wire         cache_valid;
    wire [127:0] cache_block;
    wire  [25:0] cache_tag_out;


    wire         mem_read;
    wire [127:0] mem_read_data;
    wire         mem_read_valid;
    wire         mem_write;
    wire [31:0]  mem_write_addr;
    wire         mem_write_done;


    cache d_cache
    (
        .clock        (clock),
        .reset        (reset),
        .write_word   (write),
        .write_block  (mem_read_valid),
        .byte_access  (byte_access),
        .index        (cache_line),
        .word         (cache_word),
        .byte         (cache_byte),
        .tag_in       (cache_tag_in),
        .word_in      (write_data),
        .block_in     (mem_read_data),
        .hit          (cache_hit),
        .dirty        (cache_dirty),
        .word_out     (read_data),
        .word_valid   (cache_valid),
        .block_out    (cache_block),
        .tag_out      (cache_tag_out)
    );

    data_mem d_mem
    (
        .clock          (clock),
        .read           (mem_read),
        .write          (mem_write),
        .write_address  (mem_write_addr),
        .read_address   (address),
        .write_data     (cache_block),
        .read_data      (mem_read_data),
        .write_done     (mem_write_done),
        .read_valid     (mem_read_valid)
    );


    assign cache_tag_in = address[31:6];
    assign cache_line   = address[5:4];
    assign cache_word   = address[3:2];
    assign cache_byte   = address[1:0];


    assign mem_read  = (read | write) & (~cache_hit | ~cache_valid);
    assign mem_write = (read | write) & (~cache_hit && cache_dirty);
    assign mem_write_addr = {cache_tag_out, 6'b0};


    assign stall = mem_read || mem_write;

endmodule