data/full_repos/permissive/201267735/rtl/core/frv_bitwise.v
1: b"%Error: data/full_repos/permissive/201267735/rtl/core/frv_bitwise.v:83: Cannot find file containing module: 'b_lut'\nb_lut i_b_lut (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/201267735/rtl/core,data/full_repos/permissive/201267735/b_lut\n             data/full_repos/permissive/201267735/rtl/core,data/full_repos/permissive/201267735/b_lut.v\n             data/full_repos/permissive/201267735/rtl/core,data/full_repos/permissive/201267735/b_lut.sv\n             b_lut\n             b_lut.v\n             b_lut.sv\n             obj_dir/b_lut\n             obj_dir/b_lut.v\n             obj_dir/b_lut.sv\n%Error: data/full_repos/permissive/201267735/rtl/core/frv_bitwise.v:104: Cannot find file containing module: 'b_bop'\nb_bop i_b_bop(\n^~~~~\n%Error: Exiting due to 2 error(s)\n"
module frv_bitwise (

input  wire [31:0]  rs1             ,
input  wire [31:0]  rs2             ,
input  wire [31:0]  rs3             ,

input  wire [ 7:0]  bop_lut         ,

input  wire         flush           ,
input  wire         valid           ,

input  wire         uop_fsl         ,
input  wire         uop_fsr         ,
input  wire         uop_mror        ,
input  wire         uop_cmov        ,
input  wire         uop_lut         ,
input  wire         uop_bop         ,

output wire [63:0]  result          ,
output wire         ready

);




parameter XC_CLASS_BIT        = 1'b1;





wire [31:0] result_cmov = |rs2 ? rs1 : rs3;





wire [ 5:0] ramt    = uop_mror ? rs3[5:0] : rs2[5:0];

wire [63:0] rword_r = {rs1, uop_mror ? rs2 : rs3};
wire [63:0] rword_l;

wire [63:0] r_in    = uop_fsl ? rword_l : rword_r;

wire [63:0] rt_5    = ramt[5] ? {r_in[31:0], r_in[63:32]} : r_in;
wire [63:0] rt_4    = ramt[4] ? {rt_5[15:0], rt_5[63:16]} : rt_5;
wire [63:0] rt_3    = ramt[3] ? {rt_4[ 7:0], rt_4[63: 8]} : rt_4;
wire [63:0] rt_2    = ramt[2] ? {rt_3[ 3:0], rt_3[63: 4]} : rt_3;
wire [63:0] rt_1    = ramt[1] ? {rt_2[ 1:0], rt_2[63: 2]} : rt_2;
wire [63:0] rt_0    = ramt[0] ? {rt_1[   0], rt_1[63: 1]} : rt_1;

wire [63:0] rout_l  ;

wire [63:0] r_out   = uop_fsl ? rout_l  : rt_0   ;

genvar i;

generate for(i = 0; i < 64; i = i +1) begin
    
    assign rword_l[i] = rword_r[63-i];
    
    assign rout_l[i]  = rt_0   [63-i];

end endgenerate





wire [31:0] result_lut;

generate if(XC_CLASS_BIT) begin


b_lut i_b_lut (
.crs1  (rs1         ),
.crs2  (rs2         ),
.crs3  (rs3         ),
.result(result_lut  )
);

end else begin

    assign result_lut = 0;

end endgenerate





wire [31:0] result_bop  ;

generate if(XC_CLASS_BIT) begin

b_bop i_b_bop(
.rs1   (rs1         ),
.rs2   (rs2         ),
.rd    (rs3         ),
.lut   (bop_lut     ),
.result(result_bop  ) 
);

end else begin

    assign result_bop = 0;

end endgenerate






wire result_fsl     = uop_fsl || uop_fsr;

assign result =
    {64{result_fsl}} & {32'b0, r_out[63:32]} |
    {64{uop_mror  }} & {       r_out       } |
    {64{uop_cmov  }} & {32'b0, result_cmov } |
    {64{uop_bop   }} & {32'b0, result_bop  } |
    {64{uop_lut   }} & {32'b0, result_lut  } ;


assign ready = valid;

endmodule
module frv_bitwise (

input  wire [31:0]  rs1             ,
input  wire [31:0]  rs2             ,
input  wire [31:0]  rs3             ,

input  wire [ 7:0]  bop_lut         ,

input  wire         flush           ,
input  wire         valid           ,

input  wire         uop_fsl         ,
input  wire         uop_fsr         ,
input  wire         uop_mror        ,
input  wire         uop_cmov        ,
input  wire         uop_lut         ,
input  wire         uop_bop         ,

output wire [63:0]  result          ,
output wire         ready

);





parameter XC_CLASS_BIT        = 1'b1;





wire [31:0] result_cmov = |rs2 ? rs1 : rs3;





wire [ 5:0] ramt    = uop_mror ? rs3[5:0] : rs2[5:0];

wire [63:0] rword_r = {rs1, uop_mror ? rs2 : rs3};
wire [63:0] rword_l;

wire [63:0] r_in    = uop_fsl ? rword_l : rword_r;

wire [63:0] rt_5    = ramt[5] ? {r_in[31:0], r_in[63:32]} : r_in;
wire [63:0] rt_4    = ramt[4] ? {rt_5[15:0], rt_5[63:16]} : rt_5;
wire [63:0] rt_3    = ramt[3] ? {rt_4[ 7:0], rt_4[63: 8]} : rt_4;
wire [63:0] rt_2    = ramt[2] ? {rt_3[ 3:0], rt_3[63: 4]} : rt_3;
wire [63:0] rt_1    = ramt[1] ? {rt_2[ 1:0], rt_2[63: 2]} : rt_2;
wire [63:0] rt_0    = ramt[0] ? {rt_1[   0], rt_1[63: 1]} : rt_1;

wire [63:0] rout_l  ;

wire [63:0] r_out   = uop_fsl ? rout_l  : rt_0   ;

genvar i;

generate for(i = 0; i < 64; i = i +1) begin
    
    assign rword_l[i] = rword_r[63-i];
    
    assign rout_l[i]  = rt_0   [63-i];

end endgenerate





wire [31:0] result_lut;

generate if(XC_CLASS_BIT) begin


b_lut i_b_lut (
.crs1  (rs1         ),
.crs2  (rs2         ),
.crs3  (rs3         ),
.result(result_lut  )
);

end else begin

    assign result_lut = 0;

end endgenerate





wire [31:0] result_bop  ;

generate if(XC_CLASS_BIT) begin

b_bop i_b_bop(
.rs1   (rs1         ),
.rs2   (rs2         ),
.rd    (rs3         ),
.lut   (bop_lut     ),
.result(result_bop  ) 
);

end else begin

    assign result_bop = 0;

end endgenerate






wire result_fsl     = uop_fsl || uop_fsr;

assign result =
    {64{result_fsl}} & {32'b0, r_out[63:32]} |
    {64{uop_mror  }} & {       r_out       } |
    {64{uop_cmov  }} & {32'b0, result_cmov } |
    {64{uop_bop   }} & {32'b0, result_bop  } |
    {64{uop_lut   }} & {32'b0, result_lut  } ;


assign ready = valid;

endmodule