data/full_repos/permissive/159001439/src/edge_counter.v
'utf-8' codec can't decode byte 0xb1 in position 117: invalid start byte
1: b'%Warning-WIDTH: data/full_repos/permissive/159001439/src/edge_counter.v:35: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                          : ... In instance edge_counter\n  strobe_r<={strobe_r,strobe_i};\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module edge_counter
#(parameterwidth=32,polarity=1'b1)
(
	input clk_i,
	input rst_i,
	input strobe_i,
	output [width-1:0] counter_o
);

(* ASYNC_REG="TRUE" *)
reg [3:0] strobe_r;
reg [width-1:0] counter_r;
assign counter_o = counter_r;
always @(posedge clk_i, posedge rst_i)
begin
	if(rst_i)
	begin
		counter_r<= 'b0;
		strobe_r<= {4{!polarity}};
	end
	else
	begin
		if((strobe_r[3]!=polarity) && (strobe_r[2]==polarity))
			counter_r<=counter_r +1;
		strobe_r<={strobe_r,strobe_i};
	end
end

endmodule
module edge_counter
#(parameterwidth=32,polarity=1'b1)
(
	input clk_i,
	input rst_i,
	input strobe_i,
	output [width-1:0] counter_o
);


(* ASYNC_REG="TRUE" *)
reg [3:0] strobe_r;
reg [width-1:0] counter_r;
assign counter_o = counter_r;
always @(posedge clk_i, posedge rst_i)
begin
	if(rst_i)
	begin
		counter_r<= 'b0;
		strobe_r<= {4{!polarity}};
	end
	else
	begin
		if((strobe_r[3]!=polarity) && (strobe_r[2]==polarity))
			counter_r<=counter_r +1;
		strobe_r<={strobe_r,strobe_i};
	end
end

endmodule