data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer3.v
data/verilator_xmls/a40bb31b-9fa8-430f-963c-6cdacfb3a67f.xml
module muxer3 #(
   parameter     RES = 14 
)
(

   input      [  3-1: 0] sel,
   input      [RES-1: 0] in0,
   input      [RES-1: 0] in1,
   input      [RES-1: 0] in2,
   input      [RES-1: 0] in3,
   input      [RES-1: 0] in4,
   input      [RES-1: 0] in5,
   input      [RES-1: 0] in6,
   input      [RES-1: 0] in7,


   output     [RES-1: 0] out
);


wire ensel0 ,ensel1 ,ensel2 ,ensel3 ,ensel4 ,ensel5 ,ensel6 ,ensel7 ;

     

assign ensel0  = (sel==3'd0 );
assign ensel1  = (sel==3'd1 );
assign ensel2  = (sel==3'd2 );
assign ensel3  = (sel==3'd3 );
assign ensel4  = (sel==3'd4 );
assign ensel5  = (sel==3'd5 );
assign ensel6  = (sel==3'd6 );
assign ensel7  = (sel==3'd7 );


wire [RES-1: 0] en0 ;
wire [RES-1: 0] en1 ;
wire [RES-1: 0] en2 ;
wire [RES-1: 0] en3 ;
wire [RES-1: 0] en4 ;
wire [RES-1: 0] en5 ;
wire [RES-1: 0] en6 ;
wire [RES-1: 0] en7 ;


assign en0  = {RES{ ensel0  }} & in0  ;
assign en1  = {RES{ ensel1  }} & in1  ;
assign en2  = {RES{ ensel2  }} & in2  ;
assign en3  = {RES{ ensel3  }} & in3  ;
assign en4  = {RES{ ensel4  }} & in4  ;
assign en5  = {RES{ ensel5  }} & in5  ;
assign en6  = {RES{ ensel6  }} & in6  ;
assign en7  = {RES{ ensel7  }} & in7  ;


assign  out = en0 |en1 |en2 |en3 |en4 |en5 |en6 |en7 ;

              

endmodule
module muxer3 #(
   parameter     RES = 14 
)
(

   input      [  3-1: 0] sel,
   input      [RES-1: 0] in0,
   input      [RES-1: 0] in1,
   input      [RES-1: 0] in2,
   input      [RES-1: 0] in3,
   input      [RES-1: 0] in4,
   input      [RES-1: 0] in5,
   input      [RES-1: 0] in6,
   input      [RES-1: 0] in7,


   output     [RES-1: 0] out
);



wire ensel0 ,ensel1 ,ensel2 ,ensel3 ,ensel4 ,ensel5 ,ensel6 ,ensel7 ;

     

assign ensel0  = (sel==3'd0 );
assign ensel1  = (sel==3'd1 );
assign ensel2  = (sel==3'd2 );
assign ensel3  = (sel==3'd3 );
assign ensel4  = (sel==3'd4 );
assign ensel5  = (sel==3'd5 );
assign ensel6  = (sel==3'd6 );
assign ensel7  = (sel==3'd7 );


wire [RES-1: 0] en0 ;
wire [RES-1: 0] en1 ;
wire [RES-1: 0] en2 ;
wire [RES-1: 0] en3 ;
wire [RES-1: 0] en4 ;
wire [RES-1: 0] en5 ;
wire [RES-1: 0] en6 ;
wire [RES-1: 0] en7 ;


assign en0  = {RES{ ensel0  }} & in0  ;
assign en1  = {RES{ ensel1  }} & in1  ;
assign en2  = {RES{ ensel2  }} & in2  ;
assign en3  = {RES{ ensel3  }} & in3  ;
assign en4  = {RES{ ensel4  }} & in4  ;
assign en5  = {RES{ ensel5  }} & in5  ;
assign en6  = {RES{ ensel6  }} & in6  ;
assign en7  = {RES{ ensel7  }} & in7  ;


assign  out = en0 |en1 |en2 |en3 |en4 |en5 |en6 |en7 ;

              

endmodule