data/full_repos/permissive/181665138/verilog/capitolo_i/Rete_Totale_1.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/181665138/verilog/capitolo_i/Rete_Totale_1.v:50: Signal definition not found, creating implicitly: \'A_R1_e_R2\'\n                                                                                             : ... Suggested alternative: \'a_R1_e_R2\'\n                   R2(da_R2, a_R2, A_R1_e_R2);\n                                   ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Rete_Totale_1(z3_z0, x7_x0);
    input   [7:0]   x7_x0;
    output  [3:0]   z3_z0;
    wire    [3:0]   a_R1, a_R2;
    wire    [7:0]   da_R1, da_R2;
    wire    [15:0]  a_R3;
    wire    [3:0]   da_R3;
    wire            a_R1_e_R2;






    assign a_R1 = x7_x0[7:4];
    assign a_R2 = x7_x0[3:0];
    assign a_R3 = {da_R1, da_R2};
    assign a_R1_e_R2 = da_R3[0];
    assign z3_z0 = da_R3;

    Rete_di_Tipo_A R1(da_R1, a_R1, a_R1_e_R2),
                   R2(da_R2, a_R2, A_R1_e_R2);

    Rete_di_Tipo_B R3(da_R3, a_R3);
endmodule
module Rete_Totale_1(z3_z0, x7_x0);

    input   [7:0]   x7_x0;
    output  [3:0]   z3_z0;
    wire    [3:0]   a_R1, a_R2;
    wire    [7:0]   da_R1, da_R2;
    wire    [15:0]  a_R3;
    wire    [3:0]   da_R3;
    wire            a_R1_e_R2;






    assign a_R1 = x7_x0[7:4];
    assign a_R2 = x7_x0[3:0];
    assign a_R3 = {da_R1, da_R2};
    assign a_R1_e_R2 = da_R3[0];
    assign z3_z0 = da_R3;

    Rete_di_Tipo_A R1(da_R1, a_R1, a_R1_e_R2),
                   R2(da_R2, a_R2, A_R1_e_R2);

    Rete_di_Tipo_B R3(da_R3, a_R3);
endmodule