data/full_repos/permissive/174155074/basic-code/combinational-logic/not1/not1.v
data/verilator_xmls/011c7335-6aa0-40bc-bdba-72b2318bcdde.xml
module not1 (
    input           a,
    output          y
);


assign y = ~a;

endmodule
module not1 (
    input           a,
    output          y
);



assign y = ~a;

endmodule