data/full_repos/permissive/211866113/ASTRA_RAM_BIST_MAIN_module.v
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1: b'%Error: data/full_repos/permissive/211866113/ASTRA_RAM_BIST_MAIN_module.v:1: Cannot find include file: Accumulator.v\n`include "Accumulator.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/Accumulator.v\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/Accumulator.v.v\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/Accumulator.v.sv\n             Accumulator.v\n             Accumulator.v.v\n             Accumulator.v.sv\n             obj_dir/Accumulator.v\n             obj_dir/Accumulator.v.v\n             obj_dir/Accumulator.v.sv\n%Error: Exiting due to 1 error(s)\n'
module ASTRA_RAM_BIST (

		       input wire 	in_clk,
		       input wire 	start,
		       output reg 	marching,
		       output reg 	success,

		       output reg [1:0] ADDRESS,
		       output reg [2:0] DATA,
		       input wire [2:0] OUT,
		       output reg 	CS,
		       output reg 	WE,
		       output reg 	OE
		       );

    parameter FALSE = 1'b0;
    parameter TRUE = 1'b1;

    reg 				reset;
    reg 				direction;
    reg 				march_element_done;
	reg 				START;

    wire [2:0] 				acc_in;
    wire [2:0] 				acc_out;

	reg [2:0] 				current_RAM_out;
	reg [2:0] 				march_count;
    reg [1:0] 				operation;






	wire clk;
	assign clk = (marching) ? in_clk : 1'b0;

	accumulator ACC(clk, reset, acc_in, acc_out);

	initial begin
		marching = FALSE;
		START = TRUE;
		success = FALSE;
		current_RAM_out = 3'b111;
	end

    always @ ( posedge start ) begin
	if (!marching) begin
		START = TRUE;
        success = FALSE;

        ADDRESS = 2'b00;
        DATA = 3'bzzz;

        march_count = 3'd0;
        operation = 2'd0;
        direction = TRUE;
		march_element_done = FALSE;


        WE = FALSE;
        CS <= FALSE;
        OE = FALSE;

		marching = TRUE;
	end
	end


	always @ (CS) begin
		if (OE) begin
			current_RAM_out = OUT;
		end
	end



	always @ ( negedge clk ) begin
	CS <= FALSE;
	if (!START) begin

		WE = FALSE;
		$display("Stop Writing RAM. :: time is %0t", $time);

		if (direction) begin
			ADDRESS++;
			if(ADDRESS == 2'b00) march_element_done = TRUE;
		end else begin
			ADDRESS--;
			if(ADDRESS == 2'b11) march_element_done = TRUE;
		end

        if (march_element_done) begin
	    	march_count++;
			march_element_done = FALSE;

            if (march_count == 3'd0) begin
                operation = 2'd0;
            end else if (march_count < 3'd5) begin
                operation = 2'd2;
            end else begin
                operation =2'd1;
            end


            if (march_count < 3'd3) begin

				ADDRESS = 2'b00;
                direction = TRUE;
            end else if (march_count < 3'd6) begin

				ADDRESS = 2'b11;
                direction = FALSE;
            end else begin

            	$display("END OF BIST :: time is %0t", $time);
                if (acc_out == 3'b111) begin
                    success = TRUE;
					$display("ASTRA RAM BIST SUCCESSFUL! :: time is %0t", $time);
                end
				marching = FALSE;

				reset = FALSE;

				START = TRUE;

                ADDRESS = 2'b00;
                DATA = 3'bzzz;

                march_count = 3'd0;
                operation = 2'd0;
                direction = TRUE;


                CS <= FALSE;
                OE = FALSE;
                WE = FALSE;

            end
        end
	end else begin
		$display("START SEQUENCE ENDED! :: time is %0t", $time);
		START = FALSE;

        reset = TRUE;
	end
	if(marching) begin
		$display("Start Reading RAM. :: time is %0t", $time);

		OE = TRUE;
		CS = TRUE;
		current_RAM_out <= OUT;
	end
	end


	assign acc_in = (marching) ?
		(operation == 2'd0) ? ~current_RAM_out : current_RAM_out
		: 3'b000;


	always @ ( posedge clk) begin
	reset = FALSE;
	if (!START) begin

		OE = FALSE;
		CS <= FALSE;
		$display("Stop Reading RAM. :: time is %0t", $time);


		if (operation == 2'd2) begin

			$display("Start Writing RAM. :: time is %0t", $time);
			DATA = ~current_RAM_out;

			WE = TRUE;
			CS = TRUE;
		end
	end
	end

endmodule
module ASTRA_RAM_BIST (

		       input wire 	in_clk,
		       input wire 	start,
		       output reg 	marching,
		       output reg 	success,

		       output reg [1:0] ADDRESS,
		       output reg [2:0] DATA,
		       input wire [2:0] OUT,
		       output reg 	CS,
		       output reg 	WE,
		       output reg 	OE
		       );


    parameter FALSE = 1'b0;
    parameter TRUE = 1'b1;

    reg 				reset;
    reg 				direction;
    reg 				march_element_done;
	reg 				START;

    wire [2:0] 				acc_in;
    wire [2:0] 				acc_out;

	reg [2:0] 				current_RAM_out;
	reg [2:0] 				march_count;
    reg [1:0] 				operation;






	wire clk;
	assign clk = (marching) ? in_clk : 1'b0;

	accumulator ACC(clk, reset, acc_in, acc_out);

	initial begin
		marching = FALSE;
		START = TRUE;
		success = FALSE;
		current_RAM_out = 3'b111;
	end

    always @ ( posedge start ) begin
	if (!marching) begin
		START = TRUE;
        success = FALSE;

        ADDRESS = 2'b00;
        DATA = 3'bzzz;

        march_count = 3'd0;
        operation = 2'd0;
        direction = TRUE;
		march_element_done = FALSE;


        WE = FALSE;
        CS <= FALSE;
        OE = FALSE;

		marching = TRUE;
	end
	end


	always @ (CS) begin
		if (OE) begin
			current_RAM_out = OUT;
		end
	end



	always @ ( negedge clk ) begin
	CS <= FALSE;
	if (!START) begin

		WE = FALSE;
		$display("Stop Writing RAM. :: time is %0t", $time);

		if (direction) begin
			ADDRESS++;
			if(ADDRESS == 2'b00) march_element_done = TRUE;
		end else begin
			ADDRESS--;
			if(ADDRESS == 2'b11) march_element_done = TRUE;
		end

        if (march_element_done) begin
	    	march_count++;
			march_element_done = FALSE;

            if (march_count == 3'd0) begin
                operation = 2'd0;
            end else if (march_count < 3'd5) begin
                operation = 2'd2;
            end else begin
                operation =2'd1;
            end


            if (march_count < 3'd3) begin

				ADDRESS = 2'b00;
                direction = TRUE;
            end else if (march_count < 3'd6) begin

				ADDRESS = 2'b11;
                direction = FALSE;
            end else begin

            	$display("END OF BIST :: time is %0t", $time);
                if (acc_out == 3'b111) begin
                    success = TRUE;
					$display("ASTRA RAM BIST SUCCESSFUL! :: time is %0t", $time);
                end
				marching = FALSE;

				reset = FALSE;

				START = TRUE;

                ADDRESS = 2'b00;
                DATA = 3'bzzz;

                march_count = 3'd0;
                operation = 2'd0;
                direction = TRUE;


                CS <= FALSE;
                OE = FALSE;
                WE = FALSE;

            end
        end
	end else begin
		$display("START SEQUENCE ENDED! :: time is %0t", $time);
		START = FALSE;

        reset = TRUE;
	end
	if(marching) begin
		$display("Start Reading RAM. :: time is %0t", $time);

		OE = TRUE;
		CS = TRUE;
		current_RAM_out <= OUT;
	end
	end


	assign acc_in = (marching) ?
		(operation == 2'd0) ? ~current_RAM_out : current_RAM_out
		: 3'b000;


	always @ ( posedge clk) begin
	reset = FALSE;
	if (!START) begin

		OE = FALSE;
		CS <= FALSE;
		$display("Stop Reading RAM. :: time is %0t", $time);


		if (operation == 2'd2) begin

			$display("Start Writing RAM. :: time is %0t", $time);
			DATA = ~current_RAM_out;

			WE = TRUE;
			CS = TRUE;
		end
	end
	end

endmodule