data/full_repos/permissive/118895561/Project 1/dmext.v
None: at end of input
1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/118895561\n        ... Looked in:\n             data/full_repos/permissive/118895561/Project/1,data/full_repos/permissive/118895561\n             data/full_repos/permissive/118895561/Project/1,data/full_repos/permissive/118895561.v\n             data/full_repos/permissive/118895561/Project/1,data/full_repos/permissive/118895561.sv\n             1,data/full_repos/permissive/118895561\n             1,data/full_repos/permissive/118895561.v\n             1,data/full_repos/permissive/118895561.sv\n             obj_dir/1,data/full_repos/permissive/118895561\n             obj_dir/1,data/full_repos/permissive/118895561.v\n             obj_dir/1,data/full_repos/permissive/118895561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/118895561/Project\n%Error: Cannot find file containing module: 1/dmext.v\n%Error: Exiting due to 3 error(s)\n'
module dmext(
    input [31:0] DM_Out,
    input [31:26] Op,
    input [1:0] ALU_Out_M,
    output reg [31:0] DM_Out_M
    );
  always@(*) begin
	case(Op)
	 6'b100000 : case(ALU_Out_M)
						2'b00 : DM_Out_M <= {{24{DM_Out[7]}} ,DM_Out[7:0]};
						2'b01 : DM_Out_M <= {{24{DM_Out[15]}},DM_Out[15:8]};
						2'b10 : DM_Out_M <= {{24{DM_Out[23]}},DM_Out[23:16]};
						2'b11 : DM_Out_M <= {{24{DM_Out[31]}},DM_Out[31:24]};
					 endcase
	 6'b100100 : case(ALU_Out_M)
						2'b00 : DM_Out_M <= {{24'b0},DM_Out[7:0]};
						2'b01 : DM_Out_M <= {{24'b0},DM_Out[15:8]};
						2'b10 : DM_Out_M <= {{24'b0},DM_Out[23:16]};
						2'b11 : DM_Out_M <= {{24'b0},DM_Out[31:24]};
					 endcase
	 6'b100001 : case(ALU_Out_M[1])
	               1'b0 : DM_Out_M <= {{24{DM_Out[15]}},DM_Out[15:0]};
						1'b1 : DM_Out_M <= {{24{DM_Out[31]}},DM_Out[31:16]};
					 endcase
	 6'b100101 : case(ALU_Out_M[1])
	               1'b0 : DM_Out_M <= {24'b0,DM_Out[15:0]};
						1'b1 : DM_Out_M <= {24'b0,DM_Out[31:16]};
					 endcase
	 default :  DM_Out_M <= DM_Out;
	endcase
  end
endmodule
module dmext(
    input [31:0] DM_Out,
    input [31:26] Op,
    input [1:0] ALU_Out_M,
    output reg [31:0] DM_Out_M
    );

  always@(*) begin
	case(Op)
	 6'b100000 : case(ALU_Out_M)
						2'b00 : DM_Out_M <= {{24{DM_Out[7]}} ,DM_Out[7:0]};
						2'b01 : DM_Out_M <= {{24{DM_Out[15]}},DM_Out[15:8]};
						2'b10 : DM_Out_M <= {{24{DM_Out[23]}},DM_Out[23:16]};
						2'b11 : DM_Out_M <= {{24{DM_Out[31]}},DM_Out[31:24]};
					 endcase
	 6'b100100 : case(ALU_Out_M)
						2'b00 : DM_Out_M <= {{24'b0},DM_Out[7:0]};
						2'b01 : DM_Out_M <= {{24'b0},DM_Out[15:8]};
						2'b10 : DM_Out_M <= {{24'b0},DM_Out[23:16]};
						2'b11 : DM_Out_M <= {{24'b0},DM_Out[31:24]};
					 endcase
	 6'b100001 : case(ALU_Out_M[1])
	               1'b0 : DM_Out_M <= {{24{DM_Out[15]}},DM_Out[15:0]};
						1'b1 : DM_Out_M <= {{24{DM_Out[31]}},DM_Out[31:16]};
					 endcase
	 6'b100101 : case(ALU_Out_M[1])
	               1'b0 : DM_Out_M <= {24'b0,DM_Out[15:0]};
						1'b1 : DM_Out_M <= {24'b0,DM_Out[31:16]};
					 endcase
	 default :  DM_Out_M <= DM_Out;
	endcase
  end
endmodule