data/full_repos/permissive/114811571/test/samples/mips-cpu/im_cached.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/114811571/test/samples/mips-cpu/im_cached.v:18: Cannot find include file: im_slow.v\n`include "im_slow.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114811571/test/samples/mips-cpu,data/full_repos/permissive/114811571/im_slow.v\n             data/full_repos/permissive/114811571/test/samples/mips-cpu,data/full_repos/permissive/114811571/im_slow.v.v\n             data/full_repos/permissive/114811571/test/samples/mips-cpu,data/full_repos/permissive/114811571/im_slow.v.sv\n             im_slow.v\n             im_slow.v.v\n             im_slow.v.sv\n             obj_dir/im_slow.v\n             obj_dir/im_slow.v.v\n             obj_dir/im_slow.v.sv\n%Error: Exiting due to 1 error(s)\n'
module im_cached(
		input wire			clk,
		input wire 	[31:0] 	addr,
		output wire			hit,
		output wire [31:0] 	data);



	parameter NMEM = 128;
	parameter IM_DATA = "im_data.txt";
	parameter MEM_SIZE = 128;
	parameter ND = 3;

	wire		rdy;
	wire [31:0] mem_data;

	im_slow #(.NMEM(NMEM), .IM_DATA(IM_DATA), .ND(ND))
			ims1(.clk(clk), .addr(addr), .rdy(rdy), .data(mem_data));






















	wire [1:0]		index;
	wire [27:0]		addr_tag;


	assign index 		= addr[3:2];
	assign addr_tag 	= addr[31:4];

	reg [60:0] block;
	reg [60:0] block0;
	reg [60:0] block1;
	reg [60:0] block2;
	reg [60:0] block3;


	initial begin
		block0[60] = 1'b0;
		block1[60] = 1'b0;
		block2[60] = 1'b0;
		block3[60] = 1'b0;
	end


	always @(*) begin
		case (index)
			0: block = block0;
			1: block = block1;
			2: block = block2;

			default: block = block3;
		endcase
	end


	wire 			valid;
	wire [27:0]		block_tag;


	assign valid		= block[60];
	assign block_tag	= block[59:32];



	assign data = (rdy == 1'b1) ? mem_data : block[31:0];







	always @(posedge clk) begin

		block0 <= block0;
		block1 <= block1;
		block2 <= block2;
		block3 <= block3;

		if (index == 2'd0 && rdy)
			block0 <= {1'b1, addr_tag, mem_data};

		if (index == 2'd1 && rdy)
			block1 <= {1'b1, addr_tag, mem_data};

		if (index == 2'd2 && rdy)
			block2 <= {1'b1, addr_tag, mem_data};

		if (index == 2'd3 && rdy)
			block3 <= {1'b1, addr_tag, mem_data};
	end

	assign hit = (rdy || (valid && (addr_tag == block_tag))) ? 1'b1 : 1'b0;

endmodule
module im_cached(
		input wire			clk,
		input wire 	[31:0] 	addr,
		output wire			hit,
		output wire [31:0] 	data);




	parameter NMEM = 128;
	parameter IM_DATA = "im_data.txt";
	parameter MEM_SIZE = 128;
	parameter ND = 3;

	wire		rdy;
	wire [31:0] mem_data;

	im_slow #(.NMEM(NMEM), .IM_DATA(IM_DATA), .ND(ND))
			ims1(.clk(clk), .addr(addr), .rdy(rdy), .data(mem_data));






















	wire [1:0]		index;
	wire [27:0]		addr_tag;


	assign index 		= addr[3:2];
	assign addr_tag 	= addr[31:4];

	reg [60:0] block;
	reg [60:0] block0;
	reg [60:0] block1;
	reg [60:0] block2;
	reg [60:0] block3;


	initial begin
		block0[60] = 1'b0;
		block1[60] = 1'b0;
		block2[60] = 1'b0;
		block3[60] = 1'b0;
	end


	always @(*) begin
		case (index)
			0: block = block0;
			1: block = block1;
			2: block = block2;

			default: block = block3;
		endcase
	end


	wire 			valid;
	wire [27:0]		block_tag;


	assign valid		= block[60];
	assign block_tag	= block[59:32];



	assign data = (rdy == 1'b1) ? mem_data : block[31:0];







	always @(posedge clk) begin

		block0 <= block0;
		block1 <= block1;
		block2 <= block2;
		block3 <= block3;

		if (index == 2'd0 && rdy)
			block0 <= {1'b1, addr_tag, mem_data};

		if (index == 2'd1 && rdy)
			block1 <= {1'b1, addr_tag, mem_data};

		if (index == 2'd2 && rdy)
			block2 <= {1'b1, addr_tag, mem_data};

		if (index == 2'd3 && rdy)
			block3 <= {1'b1, addr_tag, mem_data};
	end

	assign hit = (rdy || (valid && (addr_tag == block_tag))) ? 1'b1 : 1'b0;

endmodule