data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/new/SignZeroExtend.v
data/verilator_xmls/15ed2a0f-64ce-4e86-b2d3-6b5df294bf61.xml
module SignZeroExtend(
	 ExtSel,
	 inputNum,
	 outputNum
);

	input ExtSel;
	input wire[15:0] inputNum;
	output reg[31:0] outputNum;

	initial begin
		outputNum = 0;
	end

	always @ (ExtSel or  inputNum)begin 
		if(ExtSel)begin
			outputNum = {{16{inputNum[15]}}, inputNum[15:0]};
		end
		else begin
		  outputNum = {{16{1'b0}},inputNum[15:0]};
		end
	end

endmodule
module SignZeroExtend(
	 ExtSel,
	 inputNum,
	 outputNum
);


	input ExtSel;
	input wire[15:0] inputNum;
	output reg[31:0] outputNum;

	initial begin
		outputNum = 0;
	end

	always @ (ExtSel or  inputNum)begin 
		if(ExtSel)begin
			outputNum = {{16{inputNum[15]}}, inputNum[15:0]};
		end
		else begin
		  outputNum = {{16{1'b0}},inputNum[15:0]};
		end
	end

endmodule