data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/and_gate.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/b19eb996-606e-4a6b-9f65-902ba5e04f5b.xml
module and_gate(input wire x, input wire y, output wire z);




assign z = x & y;

endmodule
module and_gate(input wire x, input wire y, output wire z);





assign z = x & y;

endmodule