data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v
 line:99: before: ")"
1: b'%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:2: Cannot find include file: def.v\n`include "def.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.v\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.sv\n             def.v\n             def.v.v\n             def.v.sv\n             obj_dir/def.v\n             obj_dir/def.v.v\n             obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:43: syntax error, unexpected \')\', expecting \'[\'\n );\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:47: syntax error, unexpected input\n input wire [ 31:0] i_id;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:48: syntax error, unexpected output\n output reg [ 31:0] i_id_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:50: syntax error, unexpected input\n input wire        wrIs;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:51: syntax error, unexpected input\n input wire [ 4:0] wr;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:52: syntax error, unexpected input\n input wire [31:0] wrData;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:53: syntax error, unexpected input\n input wire [ 6:0] opCode;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:54: syntax error, unexpected output\n output reg [ 6:0] opCode_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:55: syntax error, unexpected input\n input wire [ 2:0] opType;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:56: syntax error, unexpected output\n output reg [ 2:0] opType_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:57: syntax error, unexpected input\n input wire [31:0] rd0, rd1, imm;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:59: syntax error, unexpected output\n output reg     memIs;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:60: syntax error, unexpected output\n output reg [ 3:0] memType;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:61: syntax error, unexpected output\n output reg [31:0] memData_o, memAdd;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:63: syntax error, unexpected input\n input wire [31:0] memData_i;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:65: syntax error, unexpected output\n output reg     wrIs_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:66: syntax error, unexpected output\n output reg [ 4:0] wr_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:67: syntax error, unexpected output\n output reg [31:0] wrData_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:69: syntax error, unexpected input\n input wire cacheMiss, cacheReady;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:70: syntax error, unexpected output\n output reg stall_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:75: syntax error, unexpected always\n always @( * ) begin\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:79: Define or directive not defined: \'`True\'\n  if (rst == `True) begin\n             ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:81: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n   wrIs_o   <= `False;\n               ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:88: Define or directive not defined: \'`True\'\n  end else if (stall != `True) begin\n                        ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:93: Define or directive not defined: \'`LOAD\'\n    `LOAD: begin\n    ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:95: Define or directive not defined: \'`DEBUG\'\n     if(`DEBUG == 1\'b1) $display("[MEM]load");\n        ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:96: Define or directive not defined: \'`True\'\n     memIs     <= `True;\n                  ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:101: Define or directive not defined: \'`STORE\'\n    `STORE: begin\n    ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:102: Define or directive not defined: \'`DEBUG\'\n     if(`DEBUG == 1\'b1) $display("[MEM]store");\n        ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:103: Define or directive not defined: \'`True\'\n     memIs     <= `True;\n                  ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:110: Define or directive not defined: \'`False\'\n                                                                               : ... Suggested alternative: \'`else\'\n     memIs     <= `False;\n                  ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:120: Define or directive not defined: \'`False\'\n                                                                               : ... Suggested alternative: \'`else\'\n  wrIs_o   <= `False;\n              ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:124: Define or directive not defined: \'`True\'\n  wating    = `True;\n              ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:130: Define or directive not defined: \'`False\'\n                                                                               : ... Suggested alternative: \'`else\'\n  wating   = `False;\n             ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:134: Define or directive not defined: \'`True\'\n  if (rst == `True) begin\n             ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:135: Define or directive not defined: \'`False\'\n                                                                               : ... Suggested alternative: \'`else\'\n   wrIs_o   <= `False;\n               ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:138: Define or directive not defined: \'`True\'\n  end else if (stall != `True) begin\n                        ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:139: Define or directive not defined: \'`LOAD\'\n   if (opCode == `LOAD && wating != `True) begin\n                 ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:139: Define or directive not defined: \'`True\'\n   if (opCode == `LOAD && wating != `True) begin\n                                    ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:140: Define or directive not defined: \'`True\'\n    wrIs_o   <= `True;\n                ^~~~~\n%Error: Exiting due to 41 error(s)\n'
module CPU_MEM(
	clk, rst, state, stall,

	i_id, i_id_o,

	wrIs, wr, wrData,
	opCode, opType,
	rd0, rd1, imm,

	opCode_o, opType_o,

	memIs, memType,
	memData_o, memAdd,
	memData_i,

	wrIs_o, wr_o, wrData_o,

	stall_o,
	cacheMiss, cacheReady,


	);

	input wire clk, rst, state, stall;

	input wire [ 31:0] i_id;
	output reg [ 31:0] i_id_o;

	input wire        wrIs;
	input wire [ 4:0] wr;
	input wire [31:0] wrData;
	input wire [ 6:0] opCode;
	output reg [ 6:0] opCode_o;
	input wire [ 2:0] opType;
	output reg [ 2:0] opType_o;
	input wire [31:0] rd0, rd1, imm;

	output reg 		  memIs;
	output reg [ 3:0] memType;
	output reg [31:0] memData_o, memAdd;

	input wire [31:0] memData_i;

	output reg 		  wrIs_o;
	output reg [ 4:0] wr_o;
	output reg [31:0] wrData_o;

	input wire cacheMiss, cacheReady;
	output reg stall_o;


	reg wating;

	always @( * ) begin



		if (rst == `True) begin
			i_id_o   <= 5'b0;
			wrIs_o   <= `False;
			wr_o     <= 4'b0;
			wrData_o <= 32'b0;
			opCode_o <= 7'b0;
			opType_o <= 3'b0;
			wating   <= 1'b0;
			stall_o  <= 1'b0;
		end	else if (stall != `True) begin
			i_id_o   <= i_id;
			opCode_o <= opCode;
			opType_o <= opType;
			case (opCode)
				`LOAD: begin

					if(`DEBUG == 1'b1)	$display("[MEM]load");
					memIs     <= `True;
					memType   <= {1'b0, opType};
					memAdd    <= wrData;
					memData_o <= 32'b0;
				end
				`STORE: begin
					if(`DEBUG == 1'b1)	$display("[MEM]store");
					memIs     <= `True;
					memType   <= {1'b1, opType};
					memAdd    <= wrData;
					memData_o <= rd1;
				end
				default: begin

					memIs     <= `False;
					memType   <= 4'b0;
					memAdd    <= 32'b0;
					memData_o <= 32'b0;
				end
			endcase
		end
	end

	always @ ( posedge cacheMiss ) begin
		wrIs_o   <= `False;
		wr_o     <= 1'b0;
		wrData_o <= 32'b0;
		stall_o  <= 1'b1;
		wating    = `True;
	end


	always @ ( posedge cacheReady ) begin
		stall_o <= 1'b0;
		wating   = `False;
	end

	always @ ( * ) begin
		if (rst == `True) begin
			wrIs_o   <= `False;
			wr_o     <= 1'b0;
			wrData_o <= 32'b0;
		end	else if (stall != `True) begin
			if (opCode == `LOAD && wating != `True) begin
				wrIs_o   <= `True;
				wr_o     <= wr;
				wrData_o <= memData_i;
			end else begin
				wrIs_o   <= wrIs;
				wr_o     <= wr;
				wrData_o <= wrData;
			end
		end
	end
endmodule
module CPU_MEM(
	clk, rst, state, stall,

	i_id, i_id_o,

	wrIs, wr, wrData,
	opCode, opType,
	rd0, rd1, imm,

	opCode_o, opType_o,

	memIs, memType,
	memData_o, memAdd,
	memData_i,

	wrIs_o, wr_o, wrData_o,

	stall_o,
	cacheMiss, cacheReady,


	);


	input wire clk, rst, state, stall;

	input wire [ 31:0] i_id;
	output reg [ 31:0] i_id_o;

	input wire        wrIs;
	input wire [ 4:0] wr;
	input wire [31:0] wrData;
	input wire [ 6:0] opCode;
	output reg [ 6:0] opCode_o;
	input wire [ 2:0] opType;
	output reg [ 2:0] opType_o;
	input wire [31:0] rd0, rd1, imm;

	output reg 		  memIs;
	output reg [ 3:0] memType;
	output reg [31:0] memData_o, memAdd;

	input wire [31:0] memData_i;

	output reg 		  wrIs_o;
	output reg [ 4:0] wr_o;
	output reg [31:0] wrData_o;

	input wire cacheMiss, cacheReady;
	output reg stall_o;


	reg wating;

	always @( * ) begin



		if (rst == `True) begin
			i_id_o   <= 5'b0;
			wrIs_o   <= `False;
			wr_o     <= 4'b0;
			wrData_o <= 32'b0;
			opCode_o <= 7'b0;
			opType_o <= 3'b0;
			wating   <= 1'b0;
			stall_o  <= 1'b0;
		end	else if (stall != `True) begin
			i_id_o   <= i_id;
			opCode_o <= opCode;
			opType_o <= opType;
			case (opCode)
				`LOAD: begin

					if(`DEBUG == 1'b1)	$display("[MEM]load");
					memIs     <= `True;
					memType   <= {1'b0, opType};
					memAdd    <= wrData;
					memData_o <= 32'b0;
				end
				`STORE: begin
					if(`DEBUG == 1'b1)	$display("[MEM]store");
					memIs     <= `True;
					memType   <= {1'b1, opType};
					memAdd    <= wrData;
					memData_o <= rd1;
				end
				default: begin

					memIs     <= `False;
					memType   <= 4'b0;
					memAdd    <= 32'b0;
					memData_o <= 32'b0;
				end
			endcase
		end
	end

	always @ ( posedge cacheMiss ) begin
		wrIs_o   <= `False;
		wr_o     <= 1'b0;
		wrData_o <= 32'b0;
		stall_o  <= 1'b1;
		wating    = `True;
	end


	always @ ( posedge cacheReady ) begin
		stall_o <= 1'b0;
		wating   = `False;
	end

	always @ ( * ) begin
		if (rst == `True) begin
			wrIs_o   <= `False;
			wr_o     <= 1'b0;
			wrData_o <= 32'b0;
		end	else if (stall != `True) begin
			if (opCode == `LOAD && wating != `True) begin
				wrIs_o   <= `True;
				wr_o     <= wr;
				wrData_o <= memData_i;
			end else begin
				wrIs_o   <= wrIs;
				wr_o     <= wr;
				wrData_o <= wrData;
			end
		end
	end
endmodule