data/full_repos/permissive/166981199/rtl/siphash_top.v
data/verilator_xmls/f0442f6b-51be-4c9e-93b2-f7e5a72838b3.xml
module siphash_top (clk, reset_n, we, cs, key, nonce, done, result);
    
    input                    clk;
    input                    reset_n;
    input                    we;
    input            [255:0] key;
    input                    cs;
    input            [63:0]  nonce;

    output    wire           done;
    output    wire   [63:0]  result;

    reg              [63:0]  reg_result;
    reg              [63:0]  reg_nonce;
    reg              [255:0] reg_key;
    reg                      reg_done;

    reg              [32:0]   counter;

    assign result = reg_result;
    assign done = reg_done;

    always @(posedge clk) begin : latch_nonce_and_key
        if (~reset_n)
        begin
            reg_nonce <= 0;
            reg_key <= 0;
        end else
        if (we)
        begin
            reg_nonce <= nonce;
            reg_key   <= key;
        end
    end

    always @(posedge clk) begin : set_result
        if (~reset_n)
        begin
            counter <= 0;
            reg_done <= 0;
            reg_result <= 0;
        end else
        begin
            counter <= counter + 1;

            if (counter >= 10)
            begin
                reg_done <= 1;
                reg_result <= (s9_v0 ^ s9_v1) ^ (s9_v2 ^ s9_v3);
            end else
            begin
                reg_result <= 0;
            end
        end
    end



    reg [63:0]    s1_v0, s1_v1, s1_v2, s1_v3;
    reg [63:0]    s1_nonce;

    always @(posedge clk) begin : stage_1
        if (~reset_n)
        begin
            s1_v0 <= 0;
            s1_v1 <= 0;
            s1_v2 <= 0;
            s1_v3 <= 0;

            s1_nonce <= 0;
        end else
        begin
            s1_v0 <= reg_key[63:0];
            s1_v1 <= reg_key[127:64];
            s1_v2 <= reg_key[191:128];
            s1_v3 <= reg_key[255:192];

            s1_nonce <= reg_nonce;
        end
    end



    reg [63:0]    s2_v0, s2_v1, s2_v2, s2_v3;
    reg [63:0]    s2_nonce;

    always @(posedge clk) begin : stage_2
        if (~reset_n)
        begin
            s2_v0 <= 0;
            s2_v1 <= 0;
            s2_v2 <= 0;
            s2_v3 <= 0;

            s2_nonce <= 0;
        end else
        begin        
            s2_v0 <= s1_v0;
            s2_v1 <= s1_v1;
            s2_v2 <= s1_v2;
            s2_v3 <= s1_v3 ^ s1_nonce;

            s2_nonce <= s1_nonce;
        end
    end



    wire [63:0]    s3_v0, s3_v1, s3_v2, s3_v3;
    reg  [63:0]    s3_nonce;

    always @(posedge clk) begin : stage_3
        if (~reset_n)
        begin
            s3_nonce <= 0;
        end else
        begin        
            s3_nonce <= s2_nonce;
        end
    end

    sipround sr11(
        .clk(clk), 
        .reset_n(reset_n),
        
        .iv0(s2_v0),
        .iv1(s2_v1),
        .iv2(s2_v2),
        .iv3(s2_v3),

        .ov0(s3_v0),
        .ov1(s3_v1),
        .ov2(s3_v2),
        .ov3(s3_v3)
    );



    wire [63:0]    s4_v0, s4_v1, s4_v2, s4_v3;
    reg  [63:0]    s4_nonce;

    always @(posedge clk) begin : stage_4
        if (~reset_n)
        begin
            s4_nonce <= 0;
        end else
        begin
            s4_nonce <= s3_nonce;
        end
    end

    sipround sr12(
        .clk(clk), 
        .reset_n(reset_n),
        
        .iv0(s3_v0),
        .iv1(s3_v1),
        .iv2(s3_v2),
        .iv3(s3_v3),

        .ov0(s4_v0),
        .ov1(s4_v1),
        .ov2(s4_v2),
        .ov3(s4_v3)
    );


    reg [63:0] s5_v0, s5_v1, s5_v2, s5_v3;

    always @(posedge clk) begin : stage_5
        if (~reset_n)
        begin
            s5_v0 <= 0;
            s5_v1 <= 0;
            s5_v2 <= 0;
            s5_v3 <= 0;
        end else
        begin        
            s5_v0 <= s4_v0 ^ s4_nonce;
            s5_v1 <= s4_v1;
            s5_v2 <= s4_v2 ^ 64'hff;
            s5_v3 <= s4_v3;
        end
    end



    wire [63:0] s6_v0, s6_v1, s6_v2, s6_v3;

    sipround sr21(
        .clk(clk), 
        .reset_n(reset_n),
        
        .iv0(s5_v0),
        .iv1(s5_v1),
        .iv2(s5_v2),
        .iv3(s5_v3),

        .ov0(s6_v0),
        .ov1(s6_v1),
        .ov2(s6_v2),
        .ov3(s6_v3)
    );



    wire [63:0] s7_v0, s7_v1, s7_v2, s7_v3;

    sipround sr22(
        .clk(clk), 
        .reset_n(reset_n),
        
        .iv0(s6_v0),
        .iv1(s6_v1),
        .iv2(s6_v2),
        .iv3(s6_v3),

        .ov0(s7_v0),
        .ov1(s7_v1),
        .ov2(s7_v2),
        .ov3(s7_v3)
    );



    wire [63:0] s8_v0, s8_v1, s8_v2, s8_v3;

    sipround sr23(
        .clk(clk), 
        .reset_n(reset_n),
        
        .iv0(s7_v0),
        .iv1(s7_v1),
        .iv2(s7_v2),
        .iv3(s7_v3),

        .ov0(s8_v0),
        .ov1(s8_v1),
        .ov2(s8_v2),
        .ov3(s8_v3)
    );



    wire [63:0] s9_v0, s9_v1, s9_v2, s9_v3;

    sipround sr24(
        .clk(clk),
        .reset_n(reset_n),
        
        .iv0(s8_v0),
        .iv1(s8_v1),
        .iv2(s8_v2),
        .iv3(s8_v3),

        .ov0(s9_v0),
        .ov1(s9_v1),
        .ov2(s9_v2),
        .ov3(s9_v3)
    );
endmodule
module siphash_top (clk, reset_n, we, cs, key, nonce, done, result);

    
    input                    clk;
    input                    reset_n;
    input                    we;
    input            [255:0] key;
    input                    cs;
    input            [63:0]  nonce;

    output    wire           done;
    output    wire   [63:0]  result;

    reg              [63:0]  reg_result;
    reg              [63:0]  reg_nonce;
    reg              [255:0] reg_key;
    reg                      reg_done;

    reg              [32:0]   counter;

    assign result = reg_result;
    assign done = reg_done;

    always @(posedge clk) begin : latch_nonce_and_key
        if (~reset_n)
        begin
            reg_nonce <= 0;
            reg_key <= 0;
        end else
        if (we)
        begin
            reg_nonce <= nonce;
            reg_key   <= key;
        end
    end

    always @(posedge clk) begin : set_result
        if (~reset_n)
        begin
            counter <= 0;
            reg_done <= 0;
            reg_result <= 0;
        end else
        begin
            counter <= counter + 1;

            if (counter >= 10)
            begin
                reg_done <= 1;
                reg_result <= (s9_v0 ^ s9_v1) ^ (s9_v2 ^ s9_v3);
            end else
            begin
                reg_result <= 0;
            end
        end
    end



    reg [63:0]    s1_v0, s1_v1, s1_v2, s1_v3;
    reg [63:0]    s1_nonce;

    always @(posedge clk) begin : stage_1
        if (~reset_n)
        begin
            s1_v0 <= 0;
            s1_v1 <= 0;
            s1_v2 <= 0;
            s1_v3 <= 0;

            s1_nonce <= 0;
        end else
        begin
            s1_v0 <= reg_key[63:0];
            s1_v1 <= reg_key[127:64];
            s1_v2 <= reg_key[191:128];
            s1_v3 <= reg_key[255:192];

            s1_nonce <= reg_nonce;
        end
    end



    reg [63:0]    s2_v0, s2_v1, s2_v2, s2_v3;
    reg [63:0]    s2_nonce;

    always @(posedge clk) begin : stage_2
        if (~reset_n)
        begin
            s2_v0 <= 0;
            s2_v1 <= 0;
            s2_v2 <= 0;
            s2_v3 <= 0;

            s2_nonce <= 0;
        end else
        begin        
            s2_v0 <= s1_v0;
            s2_v1 <= s1_v1;
            s2_v2 <= s1_v2;
            s2_v3 <= s1_v3 ^ s1_nonce;

            s2_nonce <= s1_nonce;
        end
    end



    wire [63:0]    s3_v0, s3_v1, s3_v2, s3_v3;
    reg  [63:0]    s3_nonce;

    always @(posedge clk) begin : stage_3
        if (~reset_n)
        begin
            s3_nonce <= 0;
        end else
        begin        
            s3_nonce <= s2_nonce;
        end
    end

    sipround sr11(
        .clk(clk), 
        .reset_n(reset_n),
        
        .iv0(s2_v0),
        .iv1(s2_v1),
        .iv2(s2_v2),
        .iv3(s2_v3),

        .ov0(s3_v0),
        .ov1(s3_v1),
        .ov2(s3_v2),
        .ov3(s3_v3)
    );



    wire [63:0]    s4_v0, s4_v1, s4_v2, s4_v3;
    reg  [63:0]    s4_nonce;

    always @(posedge clk) begin : stage_4
        if (~reset_n)
        begin
            s4_nonce <= 0;
        end else
        begin
            s4_nonce <= s3_nonce;
        end
    end

    sipround sr12(
        .clk(clk), 
        .reset_n(reset_n),
        
        .iv0(s3_v0),
        .iv1(s3_v1),
        .iv2(s3_v2),
        .iv3(s3_v3),

        .ov0(s4_v0),
        .ov1(s4_v1),
        .ov2(s4_v2),
        .ov3(s4_v3)
    );


    reg [63:0] s5_v0, s5_v1, s5_v2, s5_v3;

    always @(posedge clk) begin : stage_5
        if (~reset_n)
        begin
            s5_v0 <= 0;
            s5_v1 <= 0;
            s5_v2 <= 0;
            s5_v3 <= 0;
        end else
        begin        
            s5_v0 <= s4_v0 ^ s4_nonce;
            s5_v1 <= s4_v1;
            s5_v2 <= s4_v2 ^ 64'hff;
            s5_v3 <= s4_v3;
        end
    end



    wire [63:0] s6_v0, s6_v1, s6_v2, s6_v3;

    sipround sr21(
        .clk(clk), 
        .reset_n(reset_n),
        
        .iv0(s5_v0),
        .iv1(s5_v1),
        .iv2(s5_v2),
        .iv3(s5_v3),

        .ov0(s6_v0),
        .ov1(s6_v1),
        .ov2(s6_v2),
        .ov3(s6_v3)
    );



    wire [63:0] s7_v0, s7_v1, s7_v2, s7_v3;

    sipround sr22(
        .clk(clk), 
        .reset_n(reset_n),
        
        .iv0(s6_v0),
        .iv1(s6_v1),
        .iv2(s6_v2),
        .iv3(s6_v3),

        .ov0(s7_v0),
        .ov1(s7_v1),
        .ov2(s7_v2),
        .ov3(s7_v3)
    );



    wire [63:0] s8_v0, s8_v1, s8_v2, s8_v3;

    sipround sr23(
        .clk(clk), 
        .reset_n(reset_n),
        
        .iv0(s7_v0),
        .iv1(s7_v1),
        .iv2(s7_v2),
        .iv3(s7_v3),

        .ov0(s8_v0),
        .ov1(s8_v1),
        .ov2(s8_v2),
        .ov3(s8_v3)
    );



    wire [63:0] s9_v0, s9_v1, s9_v2, s9_v3;

    sipround sr24(
        .clk(clk),
        .reset_n(reset_n),
        
        .iv0(s8_v0),
        .iv1(s8_v1),
        .iv2(s8_v2),
        .iv3(s8_v3),

        .ov0(s9_v0),
        .ov1(s9_v1),
        .ov2(s9_v2),
        .ov3(s9_v3)
    );
endmodule