data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:48: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'adder_lut4\'\nmodule adder_lut4(\n       ^~~~~~~~~~\n                                                                                             : ... Top module \'frac_lut4\'\nmodule frac_lut4(\n       ^~~~~~~~~\n                                                                                             : ... Top module \'scff\'\nmodule scff(\n       ^~~~\n                                                                                             : ... Top module \'dff\'\nmodule dff(\n       ^~~\n                                                                                             : ... Top module \'dffr\'\nmodule dffr(\n       ^~~~\n                                                                                             : ... Top module \'sh_dff\'\nmodule sh_dff(\n       ^~~~~~\n                                                                                             : ... Top module \'dffs\'\nmodule dffs(\n       ^~~~\n                                                                                             : ... Top module \'dffn\'\nmodule dffn(\n       ^~~~\n                                                                                             : ... Top module \'dffnr\'\nmodule dffnr(\n       ^~~~~\n                                                                                             : ... Top module \'dffns\'\nmodule dffns(\n       ^~~~~\n                                                                                             : ... Top module \'dffsr\'\nmodule dffsr(\n       ^~~~~\n                                                                                             : ... Top module \'dffnsr\'\nmodule dffnsr(\n       ^~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:26: Little bit endian vector: MSB < LSB of bit range: 0:15\n    parameter [0:15] LUT=0;\n              ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:53: Little bit endian vector: MSB < LSB of bit range: 0:15\n    parameter [0:15] LUT = 0;\n              ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:49: Little bit endian vector: MSB < LSB of bit range: 0:3\n   input [0:3] in,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:50: Little bit endian vector: MSB < LSB of bit range: 0:1\n   output [0:1] lut2_out,\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:56: Little bit endian vector: MSB < LSB of bit range: 0:3\n    wire [0:3] li = in;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:59: Little bit endian vector: MSB < LSB of bit range: 0:7\n    wire [0:7] s1 = li[0] ?\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:63: Little bit endian vector: MSB < LSB of bit range: 0:3\n    wire [0:3] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6]} : \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:66: Little bit endian vector: MSB < LSB of bit range: 0:1\n    wire [0:1] s3 = li[2] ? {s2[0], s2[2]} : {s2[1], s2[3]};\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:22: Little bit endian vector: MSB < LSB of bit range: 0:3\n   input [0:3] in,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:29: Little bit endian vector: MSB < LSB of bit range: 0:3\n    wire [0:3] li = (IN2_IS_CIN) ? {in[0], in[1], cin, in[3]} : {in[0], in[1], in[2], in[3]};\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:32: Little bit endian vector: MSB < LSB of bit range: 0:7\n    wire [0:7] s1 = li[0] ?\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:36: Little bit endian vector: MSB < LSB of bit range: 0:3\n    wire [0:3] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6]} : \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k4n8/cells_sim.v:39: Little bit endian vector: MSB < LSB of bit range: 0:1\n    wire [0:1] s3 = li[2] ? {s2[0], s2[2]} : {s2[1], s2[3]};\n         ^\n%Error: Exiting due to 14 warning(s)\n'
module dffnr(
    output reg Q,
    input D,
    (* clkbuf_sink *)
    input C,
    input R
);
    parameter [0:0] INIT = 1'b0;
    initial Q = INIT;

    always @(negedge C or negedge R)
        if (!R)
            Q <= 1'b0;
        else 
            Q <= D;
endmodule
module dffnr(
    output reg Q,
    input D,
    (* clkbuf_sink *)
    input C,
    input R
);

    parameter [0:0] INIT = 1'b0;
    initial Q = INIT;

    always @(negedge C or negedge R)
        if (!R)
            Q <= 1'b0;
        else 
            Q <= D;
endmodule