data/full_repos/permissive/15431697/src/rx_fsm.v
 line:124: before: ":"
1: b"%Error: data/full_repos/permissive/15431697/src/rx_fsm.v:124: syntax error, unexpected ':'\n            state[DATA4]: begin\n                        ^\n%Error: data/full_repos/permissive/15431697/src/rx_fsm.v:131: syntax error, unexpected ':', expecting clocking\n            default: begin \n                   ^\n%Error: data/full_repos/permissive/15431697/src/rx_fsm.v:219: syntax error, unexpected ==\n                    if (optype[1]) == 1'b0) begin\n                                   ^~\n%Error: data/full_repos/permissive/15431697/src/rx_fsm.v:234: syntax error, unexpected <=, expecting IDENTIFIER\n                        ocp_readreq         <= 1'b1;                 \n                                            ^~\n%Error: data/full_repos/permissive/15431697/src/rx_fsm.v:238: syntax error, unexpected <=, expecting IDENTIFIER\n                        ocp_readreq         <= 1'b0;\n                                            ^~\n%Error: data/full_repos/permissive/15431697/src/rx_fsm.v:251: syntax error, unexpected <=, expecting IDENTIFIER\n                        ocp_readreq         <= 1'b1;                 \n                                            ^~\n%Error: data/full_repos/permissive/15431697/src/rx_fsm.v:255: syntax error, unexpected <=, expecting IDENTIFIER\n                        ocp_readreq         <= 1'b0;\n                                            ^~\n%Error: data/full_repos/permissive/15431697/src/rx_fsm.v:265: syntax error, unexpected <=, expecting IDENTIFIER\n                        ocp_readreq         <= 1'b1;                 \n                                            ^~\n%Error: data/full_repos/permissive/15431697/src/rx_fsm.v:269: syntax error, unexpected <=, expecting IDENTIFIER\n                        ocp_readreq         <= 1'b0;\n                                            ^~\n%Error: Cannot continue\n"
module rx_fsm(


    input wire rx_reset,



    input wire rx_clk,
    input wire rx_valid,
    input wire [keep_width - 1:0] rx_keep,
    input wire rx_last,
    output reg rx_ready,



    input wire tx_header_fifo_ready,
    output reg tx_header_fifo_valid,



    input wire [1:0] optype,
    output reg [2:0] ocp_reg_ctl,


    input wire ocp_ready,
    output reg ocp_valid,
    output reg ocp_readreq,
    output reg ocp_writereq

    );






    parameter keep_width = 8;


    localparam IDLE     = 3'b000;
    localparam H1       = 3'b001;
    localparam H2       = 3'b010;
    localparam DATA3    = 3'b011;
    localparam DATA4    = 3'b100;
   

    reg [3:0] state;
    reg [3:0] next;




    always @(posedge clk) begin
        if (reset) begin
            state       <= 4'b0;
            state[IDLE] <= 1'b1; end
        else begin
            state <= next; end
    end



    always @(state) begin
        next <= 4'b0;

        case (1'b1)



            state[IDLE]: begin
                if (rx_valid && tx_header_fifo_ready) begin
                    next[H1]    = 1'b1; end     
                else begin
                    next[IDLE]  = 1'b1; end     
            end






            state[H1]: begin
                if (rx_valid && tx_header_fifo_ready) begin
                    next[H2]    = 1'b1; end     
                else begin
                    next[H1]    = 1'b1; end    
            end




            state[H2]: begin
                if (rx_valid && tx_header_fifo_ready && optype[1]) begin
                    if (optype[0] == 0) begin
                        next[DATA3] = 1'b1; end
                    else begin
                        next[DATA4] = 1'b1; end
                end
                else if (rx_valid && tx_header_fifo_ready && rx_last) begin
                    next[IDLE]  = 1'b1; end   
                else begin
                    next[H2]    = 1'b1; end    
            end




            state[DATA3]: begin
                if (rx_valid && ocp_ready && rx_last) begin
                    next[IDLE]  = 1'b1; end   
                else begin
                    next[DATA3] = 1'b1; end   
            
            state[DATA4]: begin
                if (rx_valid && ocp_ready && rx_last) begin
                    next[IDLE]  = 1'b1; end   
                else begin
                    next[DATA4] = 1'b1; end   
            /

            default: begin 
                    next[IDLE]  = 1'b1; end
        endcase
    end



    always @(posedge rx_clk) begin
        case (1'b1)



            state[IDLE]: begin
                rx_ready                    <= 1'b0;
                tx_header_fifo_valid        <= 1'b0;
                ocp_reg_ctl                 <= IDLE;
                ocp_valid                   <= 1'b0;
                ocp_readreq                 <= 1'b0;
                ocp_writereq                <= 1'b0;
            end




            state[H1]: begin
                if (rx_valid && tx_header_fifo_ready) begin
                    rx_ready                <= 1'b1;
                    tx_header_fifo_valid    <= 1'b1;
                    ocp_reg_ctl             <= H1;
                    ocp_valid               <= 1'b0;
                    ocp_readreq             <= 1'b0;
                    ocp_writereq            <= 1'b0;
                end
                else if (rx_valid && ~tx_header_fifo_ready) begin
                    rx_ready                <= 1'b0;
                    tx_header_fifo_valid    <= 1'b1;
                    ocp_reg_ctl             <= H1;
                    ocp_valid               <= 1'b0;
                    ocp_readreq             <= 1'b0;
                    ocp_writereq            <= 1'b0;
                 end
                else begin
                    rx_ready                <= 1'b0;
                    tx_header_fifo_valid    <= 1'b0;
                    ocp_reg_ctl             <= H1;
                    ocp_valid               <= 1'b0;
                    ocp_readreq             <= 1'b0;
                    ocp_writereq            <= 1'b0;
                end




            state[H2]: begin
                if (rx_valid && tx_header_fifo_ready) begin
                    rx_ready                <= 1'b1;
                    tx_header_fifo_valid    <= 1'b1;
                    ocp_reg_ctl             <= H2;
                    ocp_valid               <= 1'b0;
                    ocp_readreq             <= 1'b0;
                    ocp_writereq            <= 1'b0;
                end
                else if (rx_valid && ~tx_header_fifo_ready) begin
                    rx_ready                <= 1'b0;
                    tx_header_fifo_valid    <= 1'b1;
                    ocp_reg_ctl             <= H2;
                    ocp_valid               <= 1'b0;
                    ocp_readreq             <= 1'b0;
                    ocp_writereq            <= 1'b0;
                end
                else begin
                    rx_ready                <= 1'b0;
                    tx_header_fifo_valid    <= 1'b0;
                    ocp_reg_ctl             <= H2;
                    ocp_valid               <= 1'b0;
                    ocp_readreq             <= 1'b0;
                    ocp_writereq            <= 1'b0;
            end




            state[DATA3]: begin
                if (rx_valid && ocp_ready) begin
                    rx_ready                <= 1'b1;
                    tx_header_fifo_valid    <= 1'b0;
                    ocp_reg_ctl             <= DATA3;
                    ocp_valid               <= 1'b1;
                    if (optype[1]) == 1'b0) begin
                        ocp_readreq         <= 1'b1;
                        ocp_writereq        <= 1'b0;
                    end
                    else begin 
                        ocp_readreq         <= 1'b0;
                        ocp_writereq        <= 1'b1;
                    end
                end
                else begin
                    rx_ready                <= 1'b0;
                    tx_header_fifo_valid    <= 1'b0;
                    ocp_reg_ctl             <= DATA3;
                    ocp_valid               <= rx_valid;
                    if (optype[1] == 1'b0) begin
                        ocp_readreq         <= 1'b1;
                        ocp_writereq        <= 1'b0;
                    end
                    else begin
                        ocp_readreq         <= 1'b0;
                        ocp_writereq        <= 1'b1;
                    end
                end
            end
            
            state[DATA4]: begin
                if (rx_valid && ocp_ready) begin
                    rx_ready                <= 1'b1;
                    tx_header_fifo_valid    <= 1'b0;
                    ocp_reg_ctl             <= DATA4;
                    ocp_valid               <= 1'b1;
                    if (optype[1] == 1'b0) begin
                        ocp_readreq         <= 1'b1;
                        ocp_writereq        <= 1'b0;
                    end
                    else begin
                        ocp_readreq         <= 1'b0;
                        ocp_writereq        <= 1'b1;
                    end
                end
                else begin
                    rx_ready                <= 1'b0;
                    tx_header_fifo_valid    <= 1'b0;
                    ocp_reg_ctl             <= DATA4;
                    ocp_valid               <= rx_valid;
                    if (optype[1] == 1'b0) begin
                        ocp_readreq         <= 1'b1;
                        ocp_writereq        <= 1'b0;
                    end
                    else begin
                        ocp_readreq         <= 1'b0;
                        ocp_writereq        <= 1'b1;
                    end
                end
            end
            /

            default: begin 
                    next[IDLE]  = 1'b1; end
        endcase
    end

endmodule
module rx_fsm(


    input wire rx_reset,



    input wire rx_clk,
    input wire rx_valid,
    input wire [keep_width - 1:0] rx_keep,
    input wire rx_last,
    output reg rx_ready,



    input wire tx_header_fifo_ready,
    output reg tx_header_fifo_valid,



    input wire [1:0] optype,
    output reg [2:0] ocp_reg_ctl,


    input wire ocp_ready,
    output reg ocp_valid,
    output reg ocp_readreq,
    output reg ocp_writereq

    );







    parameter keep_width = 8;


    localparam IDLE     = 3'b000;
    localparam H1       = 3'b001;
    localparam H2       = 3'b010;
    localparam DATA3    = 3'b011;
    localparam DATA4    = 3'b100;
   

    reg [3:0] state;
    reg [3:0] next;




    always @(posedge clk) begin
        if (reset) begin
            state       <= 4'b0;
            state[IDLE] <= 1'b1; end
        else begin
            state <= next; end
    end



    always @(state) begin
        next <= 4'b0;

        case (1'b1)



            state[IDLE]: begin
                if (rx_valid && tx_header_fifo_ready) begin
                    next[H1]    = 1'b1; end     
                else begin
                    next[IDLE]  = 1'b1; end     
            end






            state[H1]: begin
                if (rx_valid && tx_header_fifo_ready) begin
                    next[H2]    = 1'b1; end     
                else begin
                    next[H1]    = 1'b1; end    
            end




            state[H2]: begin
                if (rx_valid && tx_header_fifo_ready && optype[1]) begin
                    if (optype[0] == 0) begin
                        next[DATA3] = 1'b1; end
                    else begin
                        next[DATA4] = 1'b1; end
                end
                else if (rx_valid && tx_header_fifo_ready && rx_last) begin
                    next[IDLE]  = 1'b1; end   
                else begin
                    next[H2]    = 1'b1; end    
            end




            state[DATA3]: begin
                if (rx_valid && ocp_ready && rx_last) begin
                    next[IDLE]  = 1'b1; end   
                else begin
                    next[DATA3] = 1'b1; end   
            
            state[DATA4]: begin
                if (rx_valid && ocp_ready && rx_last) begin
                    next[IDLE]  = 1'b1; end   
                else begin
                    next[DATA4] = 1'b1; end   
            /

            default: begin 
                    next[IDLE]  = 1'b1; end
        endcase
    end



    always @(posedge rx_clk) begin
        case (1'b1)



            state[IDLE]: begin
                rx_ready                    <= 1'b0;
                tx_header_fifo_valid        <= 1'b0;
                ocp_reg_ctl                 <= IDLE;
                ocp_valid                   <= 1'b0;
                ocp_readreq                 <= 1'b0;
                ocp_writereq                <= 1'b0;
            end




            state[H1]: begin
                if (rx_valid && tx_header_fifo_ready) begin
                    rx_ready                <= 1'b1;
                    tx_header_fifo_valid    <= 1'b1;
                    ocp_reg_ctl             <= H1;
                    ocp_valid               <= 1'b0;
                    ocp_readreq             <= 1'b0;
                    ocp_writereq            <= 1'b0;
                end
                else if (rx_valid && ~tx_header_fifo_ready) begin
                    rx_ready                <= 1'b0;
                    tx_header_fifo_valid    <= 1'b1;
                    ocp_reg_ctl             <= H1;
                    ocp_valid               <= 1'b0;
                    ocp_readreq             <= 1'b0;
                    ocp_writereq            <= 1'b0;
                 end
                else begin
                    rx_ready                <= 1'b0;
                    tx_header_fifo_valid    <= 1'b0;
                    ocp_reg_ctl             <= H1;
                    ocp_valid               <= 1'b0;
                    ocp_readreq             <= 1'b0;
                    ocp_writereq            <= 1'b0;
                end




            state[H2]: begin
                if (rx_valid && tx_header_fifo_ready) begin
                    rx_ready                <= 1'b1;
                    tx_header_fifo_valid    <= 1'b1;
                    ocp_reg_ctl             <= H2;
                    ocp_valid               <= 1'b0;
                    ocp_readreq             <= 1'b0;
                    ocp_writereq            <= 1'b0;
                end
                else if (rx_valid && ~tx_header_fifo_ready) begin
                    rx_ready                <= 1'b0;
                    tx_header_fifo_valid    <= 1'b1;
                    ocp_reg_ctl             <= H2;
                    ocp_valid               <= 1'b0;
                    ocp_readreq             <= 1'b0;
                    ocp_writereq            <= 1'b0;
                end
                else begin
                    rx_ready                <= 1'b0;
                    tx_header_fifo_valid    <= 1'b0;
                    ocp_reg_ctl             <= H2;
                    ocp_valid               <= 1'b0;
                    ocp_readreq             <= 1'b0;
                    ocp_writereq            <= 1'b0;
            end




            state[DATA3]: begin
                if (rx_valid && ocp_ready) begin
                    rx_ready                <= 1'b1;
                    tx_header_fifo_valid    <= 1'b0;
                    ocp_reg_ctl             <= DATA3;
                    ocp_valid               <= 1'b1;
                    if (optype[1]) == 1'b0) begin
                        ocp_readreq         <= 1'b1;
                        ocp_writereq        <= 1'b0;
                    end
                    else begin 
                        ocp_readreq         <= 1'b0;
                        ocp_writereq        <= 1'b1;
                    end
                end
                else begin
                    rx_ready                <= 1'b0;
                    tx_header_fifo_valid    <= 1'b0;
                    ocp_reg_ctl             <= DATA3;
                    ocp_valid               <= rx_valid;
                    if (optype[1] == 1'b0) begin
                        ocp_readreq         <= 1'b1;
                        ocp_writereq        <= 1'b0;
                    end
                    else begin
                        ocp_readreq         <= 1'b0;
                        ocp_writereq        <= 1'b1;
                    end
                end
            end
            
            state[DATA4]: begin
                if (rx_valid && ocp_ready) begin
                    rx_ready                <= 1'b1;
                    tx_header_fifo_valid    <= 1'b0;
                    ocp_reg_ctl             <= DATA4;
                    ocp_valid               <= 1'b1;
                    if (optype[1] == 1'b0) begin
                        ocp_readreq         <= 1'b1;
                        ocp_writereq        <= 1'b0;
                    end
                    else begin
                        ocp_readreq         <= 1'b0;
                        ocp_writereq        <= 1'b1;
                    end
                end
                else begin
                    rx_ready                <= 1'b0;
                    tx_header_fifo_valid    <= 1'b0;
                    ocp_reg_ctl             <= DATA4;
                    ocp_valid               <= rx_valid;
                    if (optype[1] == 1'b0) begin
                        ocp_readreq         <= 1'b1;
                        ocp_writereq        <= 1'b0;
                    end
                    else begin
                        ocp_readreq         <= 1'b0;
                        ocp_writereq        <= 1'b1;
                    end
                end
            end
            /

            default: begin 
                    next[IDLE]  = 1'b1; end
        endcase
    end

endmodule