data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:3: Cannot find include file: ../../uart.v\n`include "../../uart.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/155085421/testbenches/uart,data/full_repos/permissive/155085421/../../uart.v\n             data/full_repos/permissive/155085421/testbenches/uart,data/full_repos/permissive/155085421/../../uart.v.v\n             data/full_repos/permissive/155085421/testbenches/uart,data/full_repos/permissive/155085421/../../uart.v.sv\n             ../../uart.v\n             ../../uart.v.v\n             ../../uart.v.sv\n             obj_dir/../../uart.v\n             obj_dir/../../uart.v.v\n             obj_dir/../../uart.v.sv\n%Error: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:7: Unsupported or unknown PLI call: $dumpvars\ninitial $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:11: Unsupported: Ignoring delay on this delayed statement.\ninitial #1 reset <= 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:12: Unsupported: Ignoring delay on this delayed statement.\ninitial #8 reset <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:16: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clock_144mhz <= ~clock_144mhz;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #6000 uart_rx <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #2500 uart_rx <= test_data[0];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #2500 uart_rx <= test_data[1];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #2500 uart_rx <= test_data[2];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #2500 uart_rx <= test_data[3];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #2500 uart_rx <= test_data[4];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #2500 uart_rx <= test_data[5];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #2500 uart_rx <= test_data[6];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #2500 uart_rx <= test_data[7];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #2500 uart_rx <= 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/155085421/testbenches/uart/testbench-uart.v:78: Unsupported: Ignoring delay on this delayed statement.\ninitial #40000\n        ^\n%Error: Exiting due to 2 error(s), 14 warning(s)\n'
module test;

initial $dumpvars;


reg reset;
initial #1 reset <= 1;
initial #8 reset <= 0;

reg clock_144mhz;
initial clock_144mhz <= 0;
always #1 clock_144mhz <= ~clock_144mhz;

reg clock_12mhz;
initial clock_12mhz <= 0;
reg[2:0] clock_12mhz_counter = 0;
always @(posedge clock_144mhz)
begin
    if (clock_12mhz_counter == 5)
    begin
        clock_12mhz_counter <= 0;
        clock_12mhz <= ~clock_12mhz;
    end
    else begin
        clock_12mhz_counter <= clock_12mhz_counter + 1;
    end
end

reg clock_115200hz;
initial clock_115200hz <= 0;
reg[9:0] clock_115200hz_counter = 0;
always @(posedge clock_144mhz)
begin
    if (clock_115200hz_counter == 625)
    begin
        clock_115200hz_counter <= 0;
        clock_115200hz <= ~clock_115200hz;
    end
    else begin
        clock_115200hz_counter <= clock_115200hz_counter + 1;
    end
end


reg uart_rx;
reg uart_rts;
wire uart_cts;
wire[7:0] data;
wire data_ready;

reg[7:0] test_data = 32'h62;
initial
begin
    uart_rx <= 1;

    #6000 uart_rx <= 0;

    #2500 uart_rx <= test_data[0];
    #2500 uart_rx <= test_data[1];
    #2500 uart_rx <= test_data[2];
    #2500 uart_rx <= test_data[3];
    #2500 uart_rx <= test_data[4];
    #2500 uart_rx <= test_data[5];
    #2500 uart_rx <= test_data[6];
    #2500 uart_rx <= test_data[7];

    #2500 uart_rx <= 1;
end


wire[7:0] data_readback;
initial #40000
begin
    if (data_readback[7:0] == test_data[7:0])
        $display("Success: Data readback matches test data.");
    else
        $display("Failed: Data readback doesn't match test data.");
    $finish;
end



uart uart0(
    .clock_115200hz(clock_115200hz),
    .reset(reset),
    .rx(uart_rx),
    .rts(uart_rts),
    .cts(uart_cts),
    .rx_data(data_readback),
    .rx_data_ready(data_ready)
    );

endmodule
module test;


initial $dumpvars;


reg reset;
initial #1 reset <= 1;
initial #8 reset <= 0;

reg clock_144mhz;
initial clock_144mhz <= 0;
always #1 clock_144mhz <= ~clock_144mhz;

reg clock_12mhz;
initial clock_12mhz <= 0;
reg[2:0] clock_12mhz_counter = 0;
always @(posedge clock_144mhz)
begin
    if (clock_12mhz_counter == 5)
    begin
        clock_12mhz_counter <= 0;
        clock_12mhz <= ~clock_12mhz;
    end
    else begin
        clock_12mhz_counter <= clock_12mhz_counter + 1;
    end
end

reg clock_115200hz;
initial clock_115200hz <= 0;
reg[9:0] clock_115200hz_counter = 0;
always @(posedge clock_144mhz)
begin
    if (clock_115200hz_counter == 625)
    begin
        clock_115200hz_counter <= 0;
        clock_115200hz <= ~clock_115200hz;
    end
    else begin
        clock_115200hz_counter <= clock_115200hz_counter + 1;
    end
end


reg uart_rx;
reg uart_rts;
wire uart_cts;
wire[7:0] data;
wire data_ready;

reg[7:0] test_data = 32'h62;
initial
begin
    uart_rx <= 1;

    #6000 uart_rx <= 0;

    #2500 uart_rx <= test_data[0];
    #2500 uart_rx <= test_data[1];
    #2500 uart_rx <= test_data[2];
    #2500 uart_rx <= test_data[3];
    #2500 uart_rx <= test_data[4];
    #2500 uart_rx <= test_data[5];
    #2500 uart_rx <= test_data[6];
    #2500 uart_rx <= test_data[7];

    #2500 uart_rx <= 1;
end


wire[7:0] data_readback;
initial #40000
begin
    if (data_readback[7:0] == test_data[7:0])
        $display("Success: Data readback matches test data.");
    else
        $display("Failed: Data readback doesn't match test data.");
    $finish;
end



uart uart0(
    .clock_115200hz(clock_115200hz),
    .reset(reset),
    .rx(uart_rx),
    .rts(uart_rts),
    .cts(uart_cts),
    .rx_data(data_readback),
    .rx_data_ready(data_ready)
    );

endmodule