data/full_repos/permissive/154590168/rtl_cpu/Multiply.v
 line:1 column:1: Illegal character '\x00'
1: b'%Error: data/full_repos/permissive/154590168/rtl_cpu/Multiply.v:18: Cannot find include file: OpNumber.v\n`include "OpNumber.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v.v\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v.sv\n             OpNumber.v\n             OpNumber.v.v\n             OpNumber.v.sv\n             obj_dir/OpNumber.v\n             obj_dir/OpNumber.v.v\n             obj_dir/OpNumber.v.sv\n%Error: Exiting due to 1 error(s)\n'
module  Multiply (
    input           clock,
    input   [7:0]   ai,
    input   [7:0]   bi,
    input   [0:82]  op_decode,
    output  [15:0]  ro,
    output          cf,
    output          zf
);

parameter   IREG = 1;
parameter   OREG = 0;


`include "OpNumber.v"
wire    op_mul    = op_decode[B_MUL   ];
wire    op_muls   = op_decode[B_MULS  ];
wire    op_mulsu  = op_decode[B_MULSU ];
wire    op_fmul   = op_decode[B_FMUL  ];
wire    op_fmuls  = op_decode[B_FMULS ];
wire    op_fmulsu = op_decode[B_FMULSU];


wire signed [8:0]   mu_ai_comb;
wire signed [8:0]   mu_bi_comb;
reg  signed [8:0]   mu_ai_ff;
reg  signed [8:0]   mu_bi_ff;
wire signed [8:0]   mu_ai;
wire signed [8:0]   mu_bi;
wire signed [16:0]  mu_po_comb;
reg  signed [16:0]  mu_po_ff;
wire signed [16:0]  mu_po;
wire                mul_en;
wire                fmul_en;


assign  mu_ai_comb = (op_muls
                     |op_mulsu
                     |op_fmuls
                     |op_fmulsu) ? {ai[7], ai} : {1'b0, ai};

assign  mu_bi_comb = (op_muls
                     |op_fmuls) ? {bi[7], bi} : {1'b0, bi};

always @(posedge clock) begin
    mu_ai_ff <= mu_ai_comb;
    mu_bi_ff <= mu_bi_comb;
end

assign  mu_ai = IREG ? mu_ai_ff : mu_ai_comb;
assign  mu_bi = IREG ? mu_bi_ff : mu_bi_comb;


assign  mu_po_comb = mu_ai * mu_bi;

always @(posedge clock) begin
    mu_po_ff <= mu_po_comb;
end

assign  mu_po = OREG ? mu_po_ff : mu_po_comb;


assign  mul_en  = op_mul
                | op_muls
                | op_mulsu;
assign  fmul_en = op_fmul
                | op_fmuls
                | op_fmulsu;

assign  ro = (mul_en ? mu_po : 16'h0000)
           | (fmul_en ? (mu_po << 1) : 16'h0000);

assign  cf = (mul_en | fmul_en) ? mu_po[15] : 1'b0;
assign  zf = (mul_en | fmul_en) ? (ro == 16'h0000) : 1'b0;

endmodule
module  Multiply (
    input           clock,
    input   [7:0]   ai,
    input   [7:0]   bi,
    input   [0:82]  op_decode,
    output  [15:0]  ro,
    output          cf,
    output          zf
);


parameter   IREG = 1;
parameter   OREG = 0;


`include "OpNumber.v"
wire    op_mul    = op_decode[B_MUL   ];
wire    op_muls   = op_decode[B_MULS  ];
wire    op_mulsu  = op_decode[B_MULSU ];
wire    op_fmul   = op_decode[B_FMUL  ];
wire    op_fmuls  = op_decode[B_FMULS ];
wire    op_fmulsu = op_decode[B_FMULSU];


wire signed [8:0]   mu_ai_comb;
wire signed [8:0]   mu_bi_comb;
reg  signed [8:0]   mu_ai_ff;
reg  signed [8:0]   mu_bi_ff;
wire signed [8:0]   mu_ai;
wire signed [8:0]   mu_bi;
wire signed [16:0]  mu_po_comb;
reg  signed [16:0]  mu_po_ff;
wire signed [16:0]  mu_po;
wire                mul_en;
wire                fmul_en;


assign  mu_ai_comb = (op_muls
                     |op_mulsu
                     |op_fmuls
                     |op_fmulsu) ? {ai[7], ai} : {1'b0, ai};

assign  mu_bi_comb = (op_muls
                     |op_fmuls) ? {bi[7], bi} : {1'b0, bi};

always @(posedge clock) begin
    mu_ai_ff <= mu_ai_comb;
    mu_bi_ff <= mu_bi_comb;
end

assign  mu_ai = IREG ? mu_ai_ff : mu_ai_comb;
assign  mu_bi = IREG ? mu_bi_ff : mu_bi_comb;


assign  mu_po_comb = mu_ai * mu_bi;

always @(posedge clock) begin
    mu_po_ff <= mu_po_comb;
end

assign  mu_po = OREG ? mu_po_ff : mu_po_comb;


assign  mul_en  = op_mul
                | op_muls
                | op_mulsu;
assign  fmul_en = op_fmul
                | op_fmuls
                | op_fmulsu;

assign  ro = (mul_en ? mu_po : 16'h0000)
           | (fmul_en ? (mu_po << 1) : 16'h0000);

assign  cf = (mul_en | fmul_en) ? mu_po[15] : 1'b0;
assign  zf = (mul_en | fmul_en) ? (ro == 16'h0000) : 1'b0;

endmodule