data/full_repos/permissive/161004496/multiplication_unit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161004496/multiplication_unit.v:16: Operator ASSIGN expects 60 bits on the Assign RHS, but Assign RHS\'s VARREF \'p\' generates 30 bits.\n                                                                             : ... In instance multiplication_unit\n        t = p;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module multiplication_unit(p,q,clk,signal,p_out);
parameter n = 30;
input [n-1:0]p,q;
input clk;
input signal;
output reg [2*n-1:0]p_out;
integer i;
reg [(2*n-1):0]t;


always @(posedge clk)

    if(signal==1)
        begin
        i = 0;
        t = p;
        p_out = 0;
        end
    else
        begin
        if(i<n)
            begin

            if(i==0)
                if(q[i]==0)
                    p_out=0;
                else
                    p_out = t;
            else if(q[i]==1)
                p_out = p_out|t;
            else
                p_out = p_out;
            t = t<<1;
            i = i+1;
            end
        end
endmodule
module multiplication_unit(p,q,clk,signal,p_out);

parameter n = 30;
input [n-1:0]p,q;
input clk;
input signal;
output reg [2*n-1:0]p_out;
integer i;
reg [(2*n-1):0]t;


always @(posedge clk)

    if(signal==1)
        begin
        i = 0;
        t = p;
        p_out = 0;
        end
    else
        begin
        if(i<n)
            begin

            if(i==0)
                if(q[i]==0)
                    p_out=0;
                else
                    p_out = t;
            else if(q[i]==1)
                p_out = p_out|t;
            else
                p_out = p_out;
            t = t<<1;
            i = i+1;
            end
        end
endmodule