data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v
1: b'%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:10: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_buffer_allocator.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:11: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_buffer_allocator);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #100000;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:22: Unsupported: Ignoring delay on this delayed statement.\n    always #(RATE/2.0)    clk   = ~clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:25: Unsupported: Ignoring delay on this delayed statement.\n    initial #(RATE*100)   reset = 1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:102: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:104: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:106: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:110: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:113: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:115: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:120: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:123: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:126: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:128: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:132: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:135: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:137: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:142: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:145: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:148: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:150: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:154: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:157: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_buffer_allocator/tb_buffer_allocator.v:159: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: Exiting due to 20 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_buffer_allocator();
    localparam RATE = 1000.0/200.0;
    
    initial begin
        $dumpfile("tb_buffer_allocator.vcd");
        $dumpvars(0, tb_buffer_allocator);
        
        #100000;
            $finish;
    end
    
    
    parameter   RAND_BUSY = 0;
    
    
    reg     clk = 1'b1;
    always #(RATE/2.0)    clk   = ~clk;
    
    reg     reset = 1'b1;
    initial #(RATE*100)   reset = 1'b0;
    
    reg     cke = 1'b1;
    always @(posedge clk) cke <= RAND_BUSY ? {$random()} : 1'b1;
    
    
    parameter   BUFFER_NUM   = 4;
    parameter   READER_NUM   = 2;
    parameter   ADDR_WIDTH   = 32;
    parameter   REFCNT_WIDTH = 4;
    parameter   INDEX_WIDTH  = BUFFER_NUM < 2 ? 1 :
                               BUFFER_NUM < 4 ? 2 :
                               BUFFER_NUM < 8 ? 3 : 4;
    
    
    reg     [ADDR_WIDTH-1:0]     param_buf_addr0 = 32'h0001_0000;
    reg     [ADDR_WIDTH-1:0]     param_buf_addr1 = 32'h0002_0000;
    reg     [ADDR_WIDTH-1:0]     param_buf_addr2 = 32'h0003_0000;
    reg     [ADDR_WIDTH-1:0]     param_buf_addr3 = 32'h0004_0000;
    
    reg                          writer_request = 0;
    reg                          writer_release = 0;
    wire     [ADDR_WIDTH-1:0]    writer_addr;
    wire     [INDEX_WIDTH-1:0]   writer_index;
    
    reg                          reader0_request = 0;
    reg                          reader0_release = 0;
    wire    [ADDR_WIDTH-1:0]     reader0_addr;
    wire    [INDEX_WIDTH-1:0]    reader0_index;
    
    reg                          reader1_request = 0;
    reg                          reader1_release = 0;
    wire    [ADDR_WIDTH-1:0]     reader1_addr;
    wire    [INDEX_WIDTH-1:0]    reader1_index;
    
    wire    [INDEX_WIDTH-1:0]    status_newest;
    wire    [REFCNT_WIDTH-1:0]   status_refcnt0;
    wire    [REFCNT_WIDTH-1:0]   status_refcnt1;
    wire    [REFCNT_WIDTH-1:0]   status_refcnt2;
    wire    [REFCNT_WIDTH-1:0]   status_refcnt3;
    
    
    jelly_buffer_allocator
            #(
                .BUFFER_NUM     (BUFFER_NUM),
                .READER_NUM     (READER_NUM),
                .ADDR_WIDTH     (ADDR_WIDTH),
                .REFCNT_WIDTH   (REFCNT_WIDTH),
                .INDEX_WIDTH    (INDEX_WIDTH)
            )
        i_buffer_allocator
            (
                .reset          (reset),
                .clk            (clk),
                .cke            (cke),
                
                .param_buf_addr ({param_buf_addr3, param_buf_addr2, param_buf_addr1, param_buf_addr0}),
                
                .writer_request (writer_request),
                .writer_release (writer_release),
                .writer_addr    (writer_addr),
                .writer_index   (writer_index),
                
                .reader_request ({reader1_request, reader0_request}),
                .reader_release ({reader1_release, reader0_release}),
                .reader_addr    ({reader1_addr,    reader0_addr   }),
                .reader_index   ({reader1_index,   reader0_index  }),
                
                .status_newest  (status_newest),
                .status_refcnt  ({status_refcnt3, status_refcnt2, status_refcnt1, status_refcnt0})
            );
    
    
    initial begin
    #10000;
        while ( 1 ) begin
            while ( {$random()} % 10 != 0 )
                @(posedge clk);
            writer_request <= 1'b1;
            @(posedge clk);
            writer_request <= 1'b0;
            @(posedge clk);
            
            @(posedge clk);
            while ( {$random()} % 100 != 0 )
                @(posedge clk);
            
            writer_release <= 1'b1;
            @(posedge clk);
            writer_release <= 1'b0;
            @(posedge clk);
        end
    end
    
    initial begin
    #10000;
        while ( 1 ) begin
            while ( {$random()} % 10 != 0 )
                @(posedge clk);
            
            reader0_request <= 1'b1;
            @(posedge clk);
            reader0_request <= 1'b0;
            @(posedge clk);
            
            @(posedge clk);
            while ( {$random()} % 100 != 0 )
                @(posedge clk);
            
            reader0_release <= 1'b1;
            @(posedge clk);
            reader0_release <= 1'b0;
            @(posedge clk);
        end
    end
    
    initial begin
    #10000;
        while ( 1 ) begin
            while ( {$random()} % 10 != 0 )
                @(posedge clk);
            
            reader1_request <= 1'b1;
            @(posedge clk);
            reader1_request <= 1'b0;
            @(posedge clk);
            
            @(posedge clk);
            while ( {$random()} % 100 != 0 )
                @(posedge clk);
            
            reader1_release <= 1'b1;
            @(posedge clk);
            reader1_release <= 1'b0;
            @(posedge clk);
        end
    end
    
    
endmodule
module tb_buffer_allocator();

    localparam RATE = 1000.0/200.0;
    
    initial begin
        $dumpfile("tb_buffer_allocator.vcd");
        $dumpvars(0, tb_buffer_allocator);
        
        #100000;
            $finish;
    end
    
    
    parameter   RAND_BUSY = 0;
    
    
    reg     clk = 1'b1;
    always #(RATE/2.0)    clk   = ~clk;
    
    reg     reset = 1'b1;
    initial #(RATE*100)   reset = 1'b0;
    
    reg     cke = 1'b1;
    always @(posedge clk) cke <= RAND_BUSY ? {$random()} : 1'b1;
    
    
    parameter   BUFFER_NUM   = 4;
    parameter   READER_NUM   = 2;
    parameter   ADDR_WIDTH   = 32;
    parameter   REFCNT_WIDTH = 4;
    parameter   INDEX_WIDTH  = BUFFER_NUM < 2 ? 1 :
                               BUFFER_NUM < 4 ? 2 :
                               BUFFER_NUM < 8 ? 3 : 4;
    
    
    reg     [ADDR_WIDTH-1:0]     param_buf_addr0 = 32'h0001_0000;
    reg     [ADDR_WIDTH-1:0]     param_buf_addr1 = 32'h0002_0000;
    reg     [ADDR_WIDTH-1:0]     param_buf_addr2 = 32'h0003_0000;
    reg     [ADDR_WIDTH-1:0]     param_buf_addr3 = 32'h0004_0000;
    
    reg                          writer_request = 0;
    reg                          writer_release = 0;
    wire     [ADDR_WIDTH-1:0]    writer_addr;
    wire     [INDEX_WIDTH-1:0]   writer_index;
    
    reg                          reader0_request = 0;
    reg                          reader0_release = 0;
    wire    [ADDR_WIDTH-1:0]     reader0_addr;
    wire    [INDEX_WIDTH-1:0]    reader0_index;
    
    reg                          reader1_request = 0;
    reg                          reader1_release = 0;
    wire    [ADDR_WIDTH-1:0]     reader1_addr;
    wire    [INDEX_WIDTH-1:0]    reader1_index;
    
    wire    [INDEX_WIDTH-1:0]    status_newest;
    wire    [REFCNT_WIDTH-1:0]   status_refcnt0;
    wire    [REFCNT_WIDTH-1:0]   status_refcnt1;
    wire    [REFCNT_WIDTH-1:0]   status_refcnt2;
    wire    [REFCNT_WIDTH-1:0]   status_refcnt3;
    
    
    jelly_buffer_allocator
            #(
                .BUFFER_NUM     (BUFFER_NUM),
                .READER_NUM     (READER_NUM),
                .ADDR_WIDTH     (ADDR_WIDTH),
                .REFCNT_WIDTH   (REFCNT_WIDTH),
                .INDEX_WIDTH    (INDEX_WIDTH)
            )
        i_buffer_allocator
            (
                .reset          (reset),
                .clk            (clk),
                .cke            (cke),
                
                .param_buf_addr ({param_buf_addr3, param_buf_addr2, param_buf_addr1, param_buf_addr0}),
                
                .writer_request (writer_request),
                .writer_release (writer_release),
                .writer_addr    (writer_addr),
                .writer_index   (writer_index),
                
                .reader_request ({reader1_request, reader0_request}),
                .reader_release ({reader1_release, reader0_release}),
                .reader_addr    ({reader1_addr,    reader0_addr   }),
                .reader_index   ({reader1_index,   reader0_index  }),
                
                .status_newest  (status_newest),
                .status_refcnt  ({status_refcnt3, status_refcnt2, status_refcnt1, status_refcnt0})
            );
    
    
    initial begin
    #10000;
        while ( 1 ) begin
            while ( {$random()} % 10 != 0 )
                @(posedge clk);
            writer_request <= 1'b1;
            @(posedge clk);
            writer_request <= 1'b0;
            @(posedge clk);
            
            @(posedge clk);
            while ( {$random()} % 100 != 0 )
                @(posedge clk);
            
            writer_release <= 1'b1;
            @(posedge clk);
            writer_release <= 1'b0;
            @(posedge clk);
        end
    end
    
    initial begin
    #10000;
        while ( 1 ) begin
            while ( {$random()} % 10 != 0 )
                @(posedge clk);
            
            reader0_request <= 1'b1;
            @(posedge clk);
            reader0_request <= 1'b0;
            @(posedge clk);
            
            @(posedge clk);
            while ( {$random()} % 100 != 0 )
                @(posedge clk);
            
            reader0_release <= 1'b1;
            @(posedge clk);
            reader0_release <= 1'b0;
            @(posedge clk);
        end
    end
    
    initial begin
    #10000;
        while ( 1 ) begin
            while ( {$random()} % 10 != 0 )
                @(posedge clk);
            
            reader1_request <= 1'b1;
            @(posedge clk);
            reader1_request <= 1'b0;
            @(posedge clk);
            
            @(posedge clk);
            while ( {$random()} % 100 != 0 )
                @(posedge clk);
            
            reader1_release <= 1'b1;
            @(posedge clk);
            reader1_release <= 1'b0;
            @(posedge clk);
        end
    end
    
    
endmodule