data/full_repos/permissive/119126104/myCPU/tlb.v
data/verilator_xmls/8a72b614-e306-4e11-a3b3-f7f476d54827.xml
module TLB (
    input  wire        clk,
    input  wire [31:0] inst_vaddr,
    output wire [31:0] inst_paddr,
    output wire [ 1:0] inst_ex,
    input  wire [31:0] data_vaddr,
    output wire [31:0] data_paddr,
    output wire [ 1:0] data_ex,
    input  wire [31:0] cp0_index,
    input  wire [31:0] cp0_entryhi,
    input  wire [31:0] cp0_pagemask,
    input  wire [31:0] cp0_entrylo0,
    input  wire [31:0] cp0_entrylo1,
    input  wire [31:0] cp0_random,
    output wire [31:0] tlbp_index,
    output wire [89:0] tlbr_tlb,
    input  wire        tlbwi,
    input  wire        tlbwr
);
    reg  [89:0] heap [31:0];

    wire [89:0] cp0_tlb;
    assign cp0_tlb = {cp0_entryhi[31:13], cp0_entryhi[7:0], cp0_pagemask[24:13], cp0_entrylo0[0]
                    & cp0_entrylo1[0], cp0_entrylo0[25:1], cp0_entrylo1[25:1]};

    always @(posedge clk) begin
        if(tlbwi) begin
            heap[cp0_index[4:0]]  <= cp0_tlb;
        end
        if(tlbwr) begin
            heap[cp0_random[4:0]] <= cp0_tlb;
        end
    end

    genvar i;

    wire [31:0] inst_found;
    wire [ 4:0] inst_index;
    wire [89:0] inst_tlb;
    wire [19:0] inst_pfn;
    wire [31:0] data_found;
    wire [ 4:0] data_index;
    wire [89:0] data_tlb;
    wire [19:0] data_pfn;
    wire [31:0] tlbp_found;

    generate
    for(i=0;i<32;i=i+1)
    begin: inst_f
        assign inst_found[i] = ((heap[i][89:71] & ~{7'd0, heap[i][62:51]}) == (inst_vaddr[31:13] & ~{7'd0, heap[i][62:51]}))
                            && (heap[i][50] || heap[i][70:63] == cp0_entryhi[7:0]);
    end
    endgenerate

    encoder inst_encoder (.in(inst_found), .out(inst_index));
    assign  inst_tlb   = heap[inst_index];
    assign  inst_pfn   = inst_vaddr[12] ? inst_tlb[24:5] : inst_tlb[49:30];
    assign  inst_paddr = !inst_vaddr[31] ? {inst_pfn, inst_vaddr[11:0]} :
                         !inst_vaddr[30] ? {3'd0, inst_vaddr[28:0]} :
                         inst_vaddr ;
    assign  inst_ex    = inst_vaddr[31] ? 2'd0 :
                         (!(|inst_found)) ? 2'd1 :
                         (inst_vaddr[12] && !inst_tlb[0] || ~inst_vaddr[12] && !inst_tlb[25]) ? 2'd2 :
                         (inst_vaddr[12] && !inst_tlb[1] || ~inst_vaddr[12] && !inst_tlb[26]) ? 2'd3 :
                         2'd0;

    generate
    for(i=0;i<32;i=i+1)
    begin: data_f
        assign data_found[i] = ((heap[i][89:71] & ~{7'd0, heap[i][62:51]}) == (data_vaddr[31:13] & ~{7'd0, heap[i][62:51]}))
                            && (heap[i][50] || heap[i][70:63] == cp0_entryhi[7:0]);
    end
    endgenerate

    encoder data_encoder (.in(data_found), .out(data_index));
    assign  data_tlb   = heap[data_index];
    assign  data_pfn   = data_vaddr[12] ? data_tlb[24:5] : data_tlb[49:30];
    assign  data_paddr = !data_vaddr[31] ? {data_pfn, data_vaddr[11:0]} :
                         !data_vaddr[30] ? {3'd0, data_vaddr[28:0]} :
                         data_vaddr ;
    assign  data_ex    = data_vaddr[31] ? 2'd0 :
                         (!(|data_found)) ? 2'd1 :
                         (data_vaddr[12] && !data_tlb[0] || ~data_vaddr[12] && !data_tlb[25]) ? 2'd2 :
                         (data_vaddr[12] && !data_tlb[1] || ~data_vaddr[12] && !data_tlb[26]) ? 2'd3 :
                         2'd0;

    generate
    for(i=0;i<32;i=i+1)
    begin: tlbp
        assign tlbp_found[i] = ((heap[i][89:71] & ~{7'd0, heap[i][62:51]}) == (cp0_entryhi[31:13] & ~cp0_pagemask[31:13]))
                            && (heap[i][50] || heap[i][70:63] == cp0_entryhi[7:0]);
    end
    endgenerate

    encoder tlbp_encoder (.in(tlbp_found), .out(tlbp_index[4:0]));
    assign  tlbp_index[31:5] = {~|tlbp_found, 26'd0};
    assign  tlbr_tlb         = heap[cp0_index[4:0]];

endmodule
module TLB (
    input  wire        clk,
    input  wire [31:0] inst_vaddr,
    output wire [31:0] inst_paddr,
    output wire [ 1:0] inst_ex,
    input  wire [31:0] data_vaddr,
    output wire [31:0] data_paddr,
    output wire [ 1:0] data_ex,
    input  wire [31:0] cp0_index,
    input  wire [31:0] cp0_entryhi,
    input  wire [31:0] cp0_pagemask,
    input  wire [31:0] cp0_entrylo0,
    input  wire [31:0] cp0_entrylo1,
    input  wire [31:0] cp0_random,
    output wire [31:0] tlbp_index,
    output wire [89:0] tlbr_tlb,
    input  wire        tlbwi,
    input  wire        tlbwr
);

    reg  [89:0] heap [31:0];

    wire [89:0] cp0_tlb;
    assign cp0_tlb = {cp0_entryhi[31:13], cp0_entryhi[7:0], cp0_pagemask[24:13], cp0_entrylo0[0]
                    & cp0_entrylo1[0], cp0_entrylo0[25:1], cp0_entrylo1[25:1]};

    always @(posedge clk) begin
        if(tlbwi) begin
            heap[cp0_index[4:0]]  <= cp0_tlb;
        end
        if(tlbwr) begin
            heap[cp0_random[4:0]] <= cp0_tlb;
        end
    end

    genvar i;

    wire [31:0] inst_found;
    wire [ 4:0] inst_index;
    wire [89:0] inst_tlb;
    wire [19:0] inst_pfn;
    wire [31:0] data_found;
    wire [ 4:0] data_index;
    wire [89:0] data_tlb;
    wire [19:0] data_pfn;
    wire [31:0] tlbp_found;

    generate
    for(i=0;i<32;i=i+1)
    begin: inst_f
        assign inst_found[i] = ((heap[i][89:71] & ~{7'd0, heap[i][62:51]}) == (inst_vaddr[31:13] & ~{7'd0, heap[i][62:51]}))
                            && (heap[i][50] || heap[i][70:63] == cp0_entryhi[7:0]);
    end
    endgenerate

    encoder inst_encoder (.in(inst_found), .out(inst_index));
    assign  inst_tlb   = heap[inst_index];
    assign  inst_pfn   = inst_vaddr[12] ? inst_tlb[24:5] : inst_tlb[49:30];
    assign  inst_paddr = !inst_vaddr[31] ? {inst_pfn, inst_vaddr[11:0]} :
                         !inst_vaddr[30] ? {3'd0, inst_vaddr[28:0]} :
                         inst_vaddr ;
    assign  inst_ex    = inst_vaddr[31] ? 2'd0 :
                         (!(|inst_found)) ? 2'd1 :
                         (inst_vaddr[12] && !inst_tlb[0] || ~inst_vaddr[12] && !inst_tlb[25]) ? 2'd2 :
                         (inst_vaddr[12] && !inst_tlb[1] || ~inst_vaddr[12] && !inst_tlb[26]) ? 2'd3 :
                         2'd0;

    generate
    for(i=0;i<32;i=i+1)
    begin: data_f
        assign data_found[i] = ((heap[i][89:71] & ~{7'd0, heap[i][62:51]}) == (data_vaddr[31:13] & ~{7'd0, heap[i][62:51]}))
                            && (heap[i][50] || heap[i][70:63] == cp0_entryhi[7:0]);
    end
    endgenerate

    encoder data_encoder (.in(data_found), .out(data_index));
    assign  data_tlb   = heap[data_index];
    assign  data_pfn   = data_vaddr[12] ? data_tlb[24:5] : data_tlb[49:30];
    assign  data_paddr = !data_vaddr[31] ? {data_pfn, data_vaddr[11:0]} :
                         !data_vaddr[30] ? {3'd0, data_vaddr[28:0]} :
                         data_vaddr ;
    assign  data_ex    = data_vaddr[31] ? 2'd0 :
                         (!(|data_found)) ? 2'd1 :
                         (data_vaddr[12] && !data_tlb[0] || ~data_vaddr[12] && !data_tlb[25]) ? 2'd2 :
                         (data_vaddr[12] && !data_tlb[1] || ~data_vaddr[12] && !data_tlb[26]) ? 2'd3 :
                         2'd0;

    generate
    for(i=0;i<32;i=i+1)
    begin: tlbp
        assign tlbp_found[i] = ((heap[i][89:71] & ~{7'd0, heap[i][62:51]}) == (cp0_entryhi[31:13] & ~cp0_pagemask[31:13]))
                            && (heap[i][50] || heap[i][70:63] == cp0_entryhi[7:0]);
    end
    endgenerate

    encoder tlbp_encoder (.in(tlbp_found), .out(tlbp_index[4:0]));
    assign  tlbp_index[31:5] = {~|tlbp_found, 26'd0};
    assign  tlbr_tlb         = heap[cp0_index[4:0]];

endmodule