data/full_repos/permissive/136510272/projects/05_nes/ppu.v
 line:108: before: "]"
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:92: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                             : ... In instance ppu\nreg [9:0]   x = 1\'b0;  \n                ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:93: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                             : ... In instance ppu\nreg [9:0]   y = 1\'b0;\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:98: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                             : ... In instance ppu\nreg [8:0] PPUX      = 1\'b0;      \n                      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:99: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                             : ... In instance ppu\nreg [8:0] PPUY      = 1\'b0;      \n                      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:154: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance ppu\n    SAR    = 1\'b0;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:250: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance ppu\nreg  [3:0] ns      = 1\'b0;                   \n                     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:255: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'PPUX\' generates 9 bits.\n                                                                              : ... In instance ppu\nwire [4:0] SpIdTX  = PPUX - 16\'h110;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:255: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 16 bits.\n                                                                              : ... In instance ppu\nwire [4:0] SpIdTX  = PPUX - 16\'h110;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:271: Operator LTE expects 9 bits on the LHS, but LHS\'s VARREF \'SRD\' generates 8 bits.\n                                                                              : ... In instance ppu\nwire SpTest = (SRD <= PPUY) && (PPUY < SRD + (CTRL0[5] ? 16 : 8));\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:274: Operator ASSIGN expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance ppu\nreg [23:0] Joy1Latch = 1\'b0; reg Joy1L = 1\'b0;\n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:453: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'SADDR\' generates 8 bits.\n                                                                              : ... In instance ppu\n                    3\'h4: if (RD | WREQ) begin WADDR <= SADDR; WDATA <= din; end\n                                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:460: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                              : ... In instance ppu\n                            RegFH <= din[2:0];\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:464: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                              : ... In instance ppu\n                            RegFV <= din[2:0];\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:480: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                              : ... In instance ppu\n                            RegFV <= din[5:4];                   \n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:523: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 6 bits.\n                                                                              : ... In instance ppu\n                                DOUT <= PALBG[ ADDR[3:0] ];\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:526: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 6 bits.\n                                                                              : ... In instance ppu\n                                DOUT <= PALSP[ ADDR[3:0] ];\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:560: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s CONST \'6\'h20\' generates 6 bits.\n                                                                              : ... In instance ppu\n                        ADDR <= ADDR + (CTRL0[2] ? 6\'h20 : 1\'b1);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:560: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s CONST \'1\'h1\' generates 1 bits.\n                                                                              : ... In instance ppu\n                        ADDR <= ADDR + (CTRL0[2] ? 6\'h20 : 1\'b1);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:591: Operator CASE expects 3 bits on the Case expression, but Case expression\'s SEL generates 2 bits.\n                                                                              : ... In instance ppu\n        if (PPUX < 16\'h110 + 32) case (PPUX[1:0])\n                                 ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:591: Operator LT expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'PPUX\' generates 9 bits.\n                                                                              : ... In instance ppu\n        if (PPUX < 16\'h110 + 32) case (PPUX[1:0])\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:635: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance ppu\n            SAR     <= 1\'b0; \n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:654: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 9 bits.\n                                                                              : ... In instance ppu\n                    Sprites[ ns[2:0] ][ 31:24 ] <= (PPUY - SRD);\n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:641: Operator LT expects 16 bits on the LHS, but LHS\'s VARREF \'PPUX\' generates 9 bits.\n                                                                              : ... In instance ppu\n        else if (PPUX < 16\'h108) case (PPUX[1:0])\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:588: Operator GTE expects 16 bits on the LHS, but LHS\'s VARREF \'PPUX\' generates 9 bits.\n                                                                              : ... In instance ppu\n    if (PPUX >= 16\'h110) begin\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:742: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance ppu\n        PPUY <= 1\'b0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:749: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance ppu\n        PPUX <= 1\'b0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:772: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance ppu\n    x <= x == (horiz_whole - 1) ? 1\'b0 : (x + 1\'b1);\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:776: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance ppu\n        y <= y == (vert_whole - 1) ? 1\'b0 : (y + 1\'b1);\n                                   ^\n%Error: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:791: Cannot find file containing module: \'evaluator\'\nevaluator Sprite1( HitLatch[0], SpritesLatch[0], {1\'b0, colmp}, SPRX, scolor[0], CTRL1);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/projects/05_nes,data/full_repos/permissive/136510272/evaluator\n             data/full_repos/permissive/136510272/projects/05_nes,data/full_repos/permissive/136510272/evaluator.v\n             data/full_repos/permissive/136510272/projects/05_nes,data/full_repos/permissive/136510272/evaluator.sv\n             evaluator\n             evaluator.v\n             evaluator.sv\n             obj_dir/evaluator\n             obj_dir/evaluator.v\n             obj_dir/evaluator.sv\n%Error: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:792: Cannot find file containing module: \'evaluator\'\nevaluator Sprite2( HitLatch[1], SpritesLatch[1], scolor[0], SPRX, scolor[1], CTRL1);\n^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:793: Cannot find file containing module: \'evaluator\'\nevaluator Sprite3( HitLatch[2], SpritesLatch[2], scolor[1], SPRX, scolor[2], CTRL1);\n^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:794: Cannot find file containing module: \'evaluator\'\nevaluator Sprite4( HitLatch[3], SpritesLatch[3], scolor[2], SPRX, scolor[3], CTRL1);\n^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:795: Cannot find file containing module: \'evaluator\'\nevaluator Sprite5( HitLatch[4], SpritesLatch[4], scolor[3], SPRX, scolor[4], CTRL1);\n^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:796: Cannot find file containing module: \'evaluator\'\nevaluator Sprite6( HitLatch[5], SpritesLatch[5], scolor[4], SPRX, scolor[5], CTRL1);\n^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:797: Cannot find file containing module: \'evaluator\'\nevaluator Sprite7( HitLatch[6], SpritesLatch[6], scolor[5], SPRX, scolor[6], CTRL1);\n^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:798: Cannot find file containing module: \'evaluator\'\nevaluator Sprite8( HitLatch[7], SpritesLatch[7], scolor[6], SPRX, scolor[7], CTRL1);\n^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/ppu.v:855: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance ppu\n default: rgb = 1\'b0;\n              ^\n%Error: Exiting due to 8 error(s), 29 warning(s)\n'
module ppu(


    input   wire        CLK25,
    input   wire        RESET,


    output  reg  [4:0]  red,
    output  reg  [5:0]  green,
    output  reg  [4:0]  blue,
    output  wire        hs,
    output  wire        vs,


    output  reg  [10:0] vaddr,
    input   wire [ 7:0] vdata,


    input   wire [7:0]  VIN,
    output  reg         WVREQ,
    output  reg  [15:0] WADDR,
    output  reg  [7:0]  WDATA,




    output  reg  [12:0] faddr,
    input   wire [ 7:0] fdata,
    input   wire [ 7:0] FIN,


    output  wire        CLKPPU,
    output  reg         CLKCPU,


    input   wire [15:0] ea,
    input   wire [ 7:0] din,
    input   wire        RD,
    input   wire        WREQ,
    output  reg  [ 7:0] DOUT,


    output  reg         DMA,
    output  reg         OAMW,
    input   wire [7:0]  DATAIN,
    input   wire [7:0]  SPIN,
    output  reg  [7:0]  SAR,
    input   wire [7:0]  SRD,


    output  reg         NMI,
    output  wire [ 7:0] DEBUG,
    

    input   wire [ 7:0] JOY1,
    input   wire [ 7:0] JOY2

);


assign CLKPPU = !DE2Y & DE2X;


assign DEBUG = ADDR[7:0];




parameter horiz_visible = 640;
parameter horiz_back    = 48;
parameter horiz_sync    = 96;
parameter horiz_front   = 16;
parameter horiz_whole   = 800;



parameter vert_visible = 480;
parameter vert_back    = 33;
parameter vert_sync    = 2;
parameter vert_front   = 10;
parameter vert_whole   = 525;




assign hs = x >= (horiz_visible + horiz_front) && x < (horiz_visible + horiz_front + horiz_sync);
assign vs = y >= (vert_visible  + vert_front)  && y < (vert_visible  + vert_front  + vert_sync);


reg [9:0]   x = 1'b0;
reg [9:0]   y = 1'b0;


reg       DE2X      = 1'b0;
reg       DE2Y      = 1'b0;
reg [8:0] PPUX      = 1'b0;
reg [8:0] PPUY      = 1'b0;


reg         odd = 1'b0;
reg  [ 1:0] div     = 2'b00;
reg  [15:0] rgb;
reg  [15:0] ADDR    = 16'h2000;


reg  [ 5:0] PALBG[16];
reg  [ 5:0] PALSP[16];



reg  [7:0]  chrl;
reg  [7:0]  chrh;
reg  [7:0]  hiclr;
reg  [1:0]  colorpad;
reg  [15:0] colormap;


wire [3:0]  curclr = {colorpad[ 1 ],
                      colorpad[ 0 ],
                      colormap[ {X[2:0], 1'b1} ],
                      colormap[ {X[2:0], 1'b0} ]};


wire [3:0]  colmp = (curclr[1:0] == 2'b00) ||

                    ((x < (64 + 16) && CTRL1[1] == 1'b0) || (CTRL1[3] == 1'b0)) ? 4'h0 : curclr[3:0];


wire [5:0]  color = (x < 64 || x >= 575) ?
            PALBG[0] :
            (final_color[4] ? 
                PALSP[ final_color[3:0] ] :
                PALBG[ final_color[3:0] ]
            );



wire VBlank     = VBlankPPU ^ VBlankCPU;
reg  VBlankPPU  = 1'b0;
reg  VBlankCPU  = 1'b0;


initial begin

    CLKCPU = 1'b0;
    DOUT   = 8'h00;
    WVREQ  = 1'b0;
    NMI    = 1'b0;
    WADDR  = 16'h0000;
    DMA    = 1'b0;
    OAMW   = 1'b0;
    SAR    = 1'b0;


    Sprites[0] = 32'h0;
    Sprites[1] = 32'h0;
    Sprites[2] = 32'h0;
    Sprites[3] = 32'h0;
    Sprites[4] = 32'h0;
    Sprites[5] = 32'h0;
    Sprites[6] = 32'h0;
    Sprites[7] = 32'h0;

PALBG[0]  = 6'h12;
PALBG[1]  = 6'h16;
PALBG[2]  = 6'h30;
PALBG[3]  = 6'h38;

PALBG[5]  = 6'h17;
PALBG[6]  = 6'h26;
PALBG[7]  = 6'h07;

PALBG[9]  = 6'h16;
PALBG[10] = 6'h00;
PALBG[11] = 6'h30;

PALBG[13] = 6'h38;
PALBG[14] = 6'h28;
PALBG[15] = 6'h10;

end



reg [7:0]  CTRL0  = 8'b0_00_00_0_00;



reg [7:0]  CTRL1  = 8'b000_11_00_0;


reg [7:0]  SADDR = 8'h0;


reg  [7:0] BUFF = 8'hFF;


reg  [1:0] NTA;


wire       NTBank = NTA[0] ^ NTA[0] ^ X[8] ^ Y[8] ^ RegH ^ RegV;

reg        RegH  = 1'b0;
reg        RegV  = 1'b0;
reg  [4:0] RegHT = 5'h0;
reg  [4:0] RegVT = 5'h0;
reg  [3:0] RegFH = 4'h0;
reg  [3:0] RegFV = 4'h0;
reg        FIRSTW = 1;


wire [8:0] X = PPUX[8:0] + {RegHT[4:0], RegFH[2:0]} - 8;
wire [8:0] Y = PPUY[8:0] + {RegVT[4:0], RegFV[2:0]};




reg [31:0] Sprites[8];
reg [31:0] SpritesLatch[8];




reg        SpHit   = 1'b0;
reg  [3:0] ns      = 1'b0;
reg  [7:0] HitLine  = 8'h00;
reg  [7:0] HitLatch = 8'h00;


wire [4:0] SpIdTX  = PPUX - 16'h110;
wire [2:0] SpId    = SpIdTX[4:2];


wire [7:0] SpIcon  = Sprites[ SpId ][ 15:8 ];


wire       VMirror = Sprites[ SpId ][ 16 + 7 ];
wire       HMirror = Sprites[ SpId ][ 16 + 6 ];


wire [3:0] Ydiff   = Sprites[ SpId ][ 27:24 ];
wire [3:0] YVert   = VMirror ? ((CTRL0[5] ? 15 : 7) - Ydiff) : Ydiff;
wire [7:0] FMirr   = HMirror ? {fdata[0],fdata[1],fdata[2],fdata[3],fdata[4],fdata[5],fdata[6],fdata[7]} : fdata[7:0];


wire SpTest = (SRD <= PPUY) && (PPUY < SRD + (CTRL0[5] ? 16 : 8));


reg [23:0] Joy1Latch = 1'b0; reg Joy1L = 1'b0;




always @(posedge CLK25) begin


    if (x == 0 && y == 0) DE2X <= 1'b0;



    else if (x >= (64 - 31) && x < (746 - 31)) DE2X <= ~DE2X;

end


always @(posedge CLKPPU) begin

    case (div)

        2'b00: begin div <= 2'b01; CLKCPU <= 1'b1; end
        2'b01: begin div <= 2'b10; CLKCPU <= 1'b0; end
        2'b10: begin div <= 2'b00; end

    endcase

end


always @(posedge CLKPPU) begin






    if (div == 2'b01) begin

        if (PPUY == 241) begin

            NMI       <= CTRL0[7];
            VBlankPPU <= VBlankPPU ^ VBlank ^ 1'b1;

        end


        else if (PPUY == 260) begin

            NMI       <= 1'b0;
            VBlankPPU <= VBlankPPU ^ VBlank ^ 1'b0;

        end

    end














    if (RESET) begin

        DMA <= 1'b0;
        odd <= 1'b0;

    end


    else if (DMA) begin


        case ({odd, div})

            3'b000: OAMW  <= 1'b0;
            3'b001: WDATA <= DATAIN;
            3'b010: begin OAMW <= 1'b1; odd <= 1'b1; end
            3'b100: OAMW  <= 1'b0;
            3'b101: WADDR[7:0] <= WADDR[7:0] + 1'b1;
            3'b110: begin odd <= 1'b0; if (WADDR[7:0] == 8'h00) DMA <= 1'b0; end

        endcase

    end





    
    else if (ea == 16'h4016) begin
    
        case (div)
        
            2'b01: if (WREQ) begin
            
                if (Joy1L == 1'b1 && din[0] == 1'b0)
                    Joy1Latch <= { 8'h08, 8'h00, JOY1 };
                    
                Joy1L <= din[0];

            end else if (RD) begin
            
                DOUT <= {7'b0100_000, Joy1Latch[0]};
                Joy1Latch <= {1'b0, Joy1Latch[23:1]};
            
            end
        
        endcase
    
    end
    

    else if (ea == 16'h4014 && WREQ && div == 2'b10) begin

        DMA   <= 1'b1;
        odd   <= 1'b0;
        WADDR <= {din, 8'h00};
        WVREQ <= 1'b0;

    end






    else if (ea[15:13] == 3'b001) begin


        WVREQ   <= (ea[2:0] == 3'h7) && (div == 2'b01) && WREQ && (ADDR >= 16'h2000 && ADDR < 16'h3F00);

        case (div)


            2'b00: begin OAMW <= 1'b0; end


            2'b01: begin

                case (ea[2:0])


                    3'h0: if (WREQ) CTRL0 <= din;


                    3'h1: if (WREQ) CTRL1 <= din;


                    3'h2: if (RD) begin

                        DOUT <= {
                            VBlank,
                            1'b0,
                            1'b0,
                            (PPUY > 241),
                            4'b0000
                        };


                        VBlankCPU <= VBlankCPU ^ VBlank ^ 1'b0;


                        FIRSTW <= 1;

                    end


                    3'h3: if (WREQ) SADDR <= din;


                    3'h4: if (RD | WREQ) begin WADDR <= SADDR; WDATA <= din; end


                    3'h5: if (WREQ) begin

                        if (FIRSTW) begin
                            RegHT <= din[7:3];
                            RegFH <= din[2:0];
                        end
                        else begin
                            RegVT <= din[7:3];
                            RegFV <= din[2:0];
                        end

                        FIRSTW <= ~FIRSTW;
                    end


                    3'h6: if (WREQ) begin

                        if (FIRSTW)begin

                            ADDR[15:8] <= din;

                            RegVT <= {din[1:0], RegVT[2:0]};
                            RegH  <= din[2];
                            RegV  <= din[3];
                            RegFV <= din[5:4];

                        end
                        elsebegin

                            RegVT <= {RegVT[4:3], din[7:5]};
                            RegHT <=  din[4:0];

                            ADDR[7:0]  <= din;

                        end

                        FIRSTW <= ~FIRSTW;
                    end


                    3'h7: begin


                        if (WREQ) begin

                            WADDR <= ADDR;


                            if (ADDR < 16'h3F00) begin WDATA <= din; end


                            else if (ADDR < 16'h3F10) begin PALBG[ ADDR[3:0] ] <= din[5:0]; end


                            else if (ADDR < 16'h3F20) begin PALSP[ ADDR[3:0] ] <= din[5:0]; end

                        end

                        else if (RD) begin


                            if (ADDR < 16'h3F00) begin
                                WADDR <= ADDR;
                                DOUT  <= BUFF;
                            end

                            else if (ADDR < 16'h3F10) begin
                                DOUT <= PALBG[ ADDR[3:0] ];
                            end
                            else if (ADDR < 16'h3F20) begin
                                DOUT <= PALSP[ ADDR[3:0] ];
                            end

                        end

                    end

                endcase

            end


            2'b10: begin

                case (ea[2:0])


                    3'h4: begin

                             if (RD  ) DOUT <= SPIN;
                        else if (WREQ) OAMW <= 1'b1;

                        if (RD | WREQ) SADDR <= SADDR + 1'b1;

                    end


                    3'h7: if (WREQ | RD) begin


                        if (RD && ADDR < 16'h3F00) begin
                            BUFF <= (ADDR < 16'h2000 ? FIN : VIN);
                        end

                        ADDR <= ADDR + (CTRL0[2] ? 6'h20 : 1'b1);

                    end

                endcase

            end

        endcase

    end

    else begin

        WVREQ <= 1'b0;

    end
end




always @(posedge DE2X) begin





    if (PPUX >= 16'h110) begin


        if (PPUX < 16'h110 + 32) case (PPUX[1:0])

            3'h0: begin

                if (CTRL0[5])
faddr <= {SpIcon[0], SpIcon[7:1], YVert[3], 1'b0, YVert[2:0]};
                else
faddr <= {CTRL0[3],  SpIcon[7:0],           1'b0, YVert[2:0]};

            end


            3'h1: begin Sprites[ SpId ][ 15:8 ]  <= FMirr; faddr[3] <= 1'b1; end
            3'h2: begin Sprites[ SpId ][ 31:24 ] <= FMirr; end

        endcase

    end




    else begin


        if (PPUX == 0) begin
        
            HitLatch <= HitLine;


            SpritesLatch[0] <= Sprites[0];
            SpritesLatch[1] <= Sprites[1];
            SpritesLatch[2] <= Sprites[2];
            SpritesLatch[3] <= Sprites[3];
            SpritesLatch[4] <= Sprites[4];
            SpritesLatch[5] <= Sprites[5];
            SpritesLatch[6] <= Sprites[6];
            SpritesLatch[7] <= Sprites[7];
            
            HitLine  <= 8'h00;
        
        end
        else if (PPUX < 8) begin 
        
            SAR     <= 1'b0; 
            ns      <= 4'h0; 

        end
        

        else if (PPUX < 16'h108) case (PPUX[1:0])



            2'h0: begin


                if (SpTest && !ns[3]) begin


                    SpHit <= 1'b1;


                    Sprites[ ns[2:0] ][ 31:24 ] <= (PPUY - SRD);


                end else SpHit <= 1'b0;

                SAR <= SAR + 1'b1;

            end


            2'h1: begin

                if (SpHit) Sprites[ ns[2:0] ][15:8] <= SRD;
                SAR <= SAR + 1'b1;

            end


            2'h2: begin

                if (SpHit) Sprites[ ns[2:0] ][23:16] = SRD;
                SAR <= SAR + 1'b1;

            end


            2'h3: begin

                if (SpHit) begin

                    Sprites[ ns[2:0] ][7:0] <= SRD;


                    HitLine[ ns[2:0] ] <= 1'b1;


                    ns <= ns[3] ? {4'b1000} : ns + 1'b1;

                end

                SAR <= SAR + 1'b1;

            end

        endcase

        case (X[2:0])



            3'h0: begin vaddr <= {NTBank, Y[7:3], X[7:3]};end


            3'h1: begin faddr <= {CTRL0[4], vdata[7:0], 1'b0, Y[2:0]};
                        vaddr <= {NTBank, 4'b1111, Y[7:5], X[7:5] }; end


            3'h2: begin faddr[3] <= 1'b1; chrl <= fdata; hiclr <= vdata; end


            3'h3: begin chrh <= fdata; end




            3'h7: begin


                colorpad <= {hiclr[ {Y[4], X[4], 1'b1} ],
                             hiclr[ {Y[4], X[4], 1'b0} ]};


                colormap <= {chrh[0], chrl[0],chrh[1], chrl[1],
chrh[2], chrl[2],chrh[3], chrl[3],
chrh[4], chrl[4],chrh[5], chrl[5],
chrh[6], chrl[6],chrh[7], chrl[7]};
            end

        endcase

    end




    if (y == vert_whole - 1) begin

        NTA  <= 2'b00;
        PPUY <= 1'b0;

    end


    else if (PPUX == 9'd340) begin

        PPUX <= 1'b0;
        DE2Y <= ~DE2Y;




        NTA  <= {1'b0, CTRL0[0]};


        if (DE2Y) PPUY <= PPUY + 1'b1;

    end else begin

        PPUX <= PPUX + 1'b1;

    end

end


always @(posedge CLK25) begin


    x <= x == (horiz_whole - 1) ? 1'b0 : (x + 1'b1);


    if (x == (horiz_whole - 1)) begin
        y <= y == (vert_whole - 1) ? 1'b0 : (y + 1'b1);
    end

    if (x < horiz_visible && y < vert_visible)
         {red, green, blue} <= {rgb[4:0], rgb[10:5], rgb[15:11]};
    else {red, green, blue} <= 16'h0000;

end


wire [4:0] scolor[8];
wire [4:0] final_color = scolor[7][4:0];
wire [8:0] SPRX = PPUX - 16;


evaluator Sprite1( HitLatch[0], SpritesLatch[0], {1'b0, colmp}, SPRX, scolor[0], CTRL1);
evaluator Sprite2( HitLatch[1], SpritesLatch[1], scolor[0], SPRX, scolor[1], CTRL1);
evaluator Sprite3( HitLatch[2], SpritesLatch[2], scolor[1], SPRX, scolor[2], CTRL1);
evaluator Sprite4( HitLatch[3], SpritesLatch[3], scolor[2], SPRX, scolor[3], CTRL1);
evaluator Sprite5( HitLatch[4], SpritesLatch[4], scolor[3], SPRX, scolor[4], CTRL1);
evaluator Sprite6( HitLatch[5], SpritesLatch[5], scolor[4], SPRX, scolor[5], CTRL1);
evaluator Sprite7( HitLatch[6], SpritesLatch[6], scolor[5], SPRX, scolor[6], CTRL1);
evaluator Sprite8( HitLatch[7], SpritesLatch[7], scolor[6], SPRX, scolor[7], CTRL1);


always @* case (color)

    6'd0:  rgb = 16'h73ae;
	6'd1:  rgb = 16'h88c4;
	6'd2:  rgb = 16'ha800;
	6'd3:  rgb = 16'h9808;
	6'd4:  rgb = 16'h7011;
	6'd5:  rgb = 16'h1015;
	6'd6:  rgb = 16'h0014;
	6'd7:  rgb = 16'h004f;
	6'd8:  rgb = 16'h0168;
	6'd9:  rgb = 16'h0220;
	6'd10: rgb = 16'h0280;
	6'd11: rgb = 16'h11e0;
	6'd12: rgb = 16'h59e3;
	6'd16: rgb = 16'hbdf7;
	6'd17: rgb = 16'heb80;
	6'd18: rgb = 16'he9c4;
	6'd19: rgb = 16'hf010;
	6'd20: rgb = 16'hb817;
	6'd21: rgb = 16'h581c;
	6'd22: rgb = 16'h015b;
	6'd23: rgb = 16'h0a79;
	6'd24: rgb = 16'h0391;
	6'd25: rgb = 16'h04a0;
	6'd26: rgb = 16'h0540;
	6'd27: rgb = 16'h3c80;
	6'd28: rgb = 16'h8c00;
	6'd32: rgb = 16'hffff;
	6'd33: rgb = 16'hfde7;
	6'd34: rgb = 16'hfcab;
	6'd35: rgb = 16'hfc54;
	6'd36: rgb = 16'hfbde;
	6'd37: rgb = 16'hb3bf;
	6'd38: rgb = 16'h63bf;
	6'd39: rgb = 16'h3cdf;
	6'd40: rgb = 16'h3dfe;
	6'd41: rgb = 16'h1690;
	6'd42: rgb = 16'h4ee9;
	6'd43: rgb = 16'h9fcb;
	6'd44: rgb = 16'hdf40;
	6'd48: rgb = 16'hffff;
	6'd49: rgb = 16'hff35;
	6'd50: rgb = 16'hfeb8;
	6'd51: rgb = 16'hfe5a;
	6'd52: rgb = 16'hfe3f;
	6'd53: rgb = 16'hde3f;
	6'd54: rgb = 16'hb5ff;
	6'd55: rgb = 16'haedf;
	6'd56: rgb = 16'ha73f;
	6'd57: rgb = 16'ha7fc;
	6'd58: rgb = 16'hbf95;
	6'd59: rgb = 16'hcff6;
	6'd60: rgb = 16'hf7f3;
	default: rgb = 1'b0;

endcase

endmodule
module ppu(


    input   wire        CLK25,
    input   wire        RESET,


    output  reg  [4:0]  red,
    output  reg  [5:0]  green,
    output  reg  [4:0]  blue,
    output  wire        hs,
    output  wire        vs,


    output  reg  [10:0] vaddr,
    input   wire [ 7:0] vdata,


    input   wire [7:0]  VIN,
    output  reg         WVREQ,
    output  reg  [15:0] WADDR,
    output  reg  [7:0]  WDATA,




    output  reg  [12:0] faddr,
    input   wire [ 7:0] fdata,
    input   wire [ 7:0] FIN,


    output  wire        CLKPPU,
    output  reg         CLKCPU,


    input   wire [15:0] ea,
    input   wire [ 7:0] din,
    input   wire        RD,
    input   wire        WREQ,
    output  reg  [ 7:0] DOUT,


    output  reg         DMA,
    output  reg         OAMW,
    input   wire [7:0]  DATAIN,
    input   wire [7:0]  SPIN,
    output  reg  [7:0]  SAR,
    input   wire [7:0]  SRD,


    output  reg         NMI,
    output  wire [ 7:0] DEBUG,
    

    input   wire [ 7:0] JOY1,
    input   wire [ 7:0] JOY2

);



assign CLKPPU = !DE2Y & DE2X;


assign DEBUG = ADDR[7:0];




parameter horiz_visible = 640;
parameter horiz_back    = 48;
parameter horiz_sync    = 96;
parameter horiz_front   = 16;
parameter horiz_whole   = 800;



parameter vert_visible = 480;
parameter vert_back    = 33;
parameter vert_sync    = 2;
parameter vert_front   = 10;
parameter vert_whole   = 525;




assign hs = x >= (horiz_visible + horiz_front) && x < (horiz_visible + horiz_front + horiz_sync);
assign vs = y >= (vert_visible  + vert_front)  && y < (vert_visible  + vert_front  + vert_sync);


reg [9:0]   x = 1'b0;
reg [9:0]   y = 1'b0;


reg       DE2X      = 1'b0;
reg       DE2Y      = 1'b0;
reg [8:0] PPUX      = 1'b0;
reg [8:0] PPUY      = 1'b0;


reg         odd = 1'b0;
reg  [ 1:0] div     = 2'b00;
reg  [15:0] rgb;
reg  [15:0] ADDR    = 16'h2000;


reg  [ 5:0] PALBG[16];
reg  [ 5:0] PALSP[16];



reg  [7:0]  chrl;
reg  [7:0]  chrh;
reg  [7:0]  hiclr;
reg  [1:0]  colorpad;
reg  [15:0] colormap;


wire [3:0]  curclr = {colorpad[ 1 ],
                      colorpad[ 0 ],
                      colormap[ {X[2:0], 1'b1} ],
                      colormap[ {X[2:0], 1'b0} ]};


wire [3:0]  colmp = (curclr[1:0] == 2'b00) ||

                    ((x < (64 + 16) && CTRL1[1] == 1'b0) || (CTRL1[3] == 1'b0)) ? 4'h0 : curclr[3:0];


wire [5:0]  color = (x < 64 || x >= 575) ?
            PALBG[0] :
            (final_color[4] ? 
                PALSP[ final_color[3:0] ] :
                PALBG[ final_color[3:0] ]
            );



wire VBlank     = VBlankPPU ^ VBlankCPU;
reg  VBlankPPU  = 1'b0;
reg  VBlankCPU  = 1'b0;


initial begin

    CLKCPU = 1'b0;
    DOUT   = 8'h00;
    WVREQ  = 1'b0;
    NMI    = 1'b0;
    WADDR  = 16'h0000;
    DMA    = 1'b0;
    OAMW   = 1'b0;
    SAR    = 1'b0;


    Sprites[0] = 32'h0;
    Sprites[1] = 32'h0;
    Sprites[2] = 32'h0;
    Sprites[3] = 32'h0;
    Sprites[4] = 32'h0;
    Sprites[5] = 32'h0;
    Sprites[6] = 32'h0;
    Sprites[7] = 32'h0;

PALBG[0]  = 6'h12;
PALBG[1]  = 6'h16;
PALBG[2]  = 6'h30;
PALBG[3]  = 6'h38;

PALBG[5]  = 6'h17;
PALBG[6]  = 6'h26;
PALBG[7]  = 6'h07;

PALBG[9]  = 6'h16;
PALBG[10] = 6'h00;
PALBG[11] = 6'h30;

PALBG[13] = 6'h38;
PALBG[14] = 6'h28;
PALBG[15] = 6'h10;

end



reg [7:0]  CTRL0  = 8'b0_00_00_0_00;



reg [7:0]  CTRL1  = 8'b000_11_00_0;


reg [7:0]  SADDR = 8'h0;


reg  [7:0] BUFF = 8'hFF;


reg  [1:0] NTA;


wire       NTBank = NTA[0] ^ NTA[0] ^ X[8] ^ Y[8] ^ RegH ^ RegV;

reg        RegH  = 1'b0;
reg        RegV  = 1'b0;
reg  [4:0] RegHT = 5'h0;
reg  [4:0] RegVT = 5'h0;
reg  [3:0] RegFH = 4'h0;
reg  [3:0] RegFV = 4'h0;
reg        FIRSTW = 1;


wire [8:0] X = PPUX[8:0] + {RegHT[4:0], RegFH[2:0]} - 8;
wire [8:0] Y = PPUY[8:0] + {RegVT[4:0], RegFV[2:0]};




reg [31:0] Sprites[8];
reg [31:0] SpritesLatch[8];




reg        SpHit   = 1'b0;
reg  [3:0] ns      = 1'b0;
reg  [7:0] HitLine  = 8'h00;
reg  [7:0] HitLatch = 8'h00;


wire [4:0] SpIdTX  = PPUX - 16'h110;
wire [2:0] SpId    = SpIdTX[4:2];


wire [7:0] SpIcon  = Sprites[ SpId ][ 15:8 ];


wire       VMirror = Sprites[ SpId ][ 16 + 7 ];
wire       HMirror = Sprites[ SpId ][ 16 + 6 ];


wire [3:0] Ydiff   = Sprites[ SpId ][ 27:24 ];
wire [3:0] YVert   = VMirror ? ((CTRL0[5] ? 15 : 7) - Ydiff) : Ydiff;
wire [7:0] FMirr   = HMirror ? {fdata[0],fdata[1],fdata[2],fdata[3],fdata[4],fdata[5],fdata[6],fdata[7]} : fdata[7:0];


wire SpTest = (SRD <= PPUY) && (PPUY < SRD + (CTRL0[5] ? 16 : 8));


reg [23:0] Joy1Latch = 1'b0; reg Joy1L = 1'b0;




always @(posedge CLK25) begin


    if (x == 0 && y == 0) DE2X <= 1'b0;



    else if (x >= (64 - 31) && x < (746 - 31)) DE2X <= ~DE2X;

end


always @(posedge CLKPPU) begin

    case (div)

        2'b00: begin div <= 2'b01; CLKCPU <= 1'b1; end
        2'b01: begin div <= 2'b10; CLKCPU <= 1'b0; end
        2'b10: begin div <= 2'b00; end

    endcase

end


always @(posedge CLKPPU) begin






    if (div == 2'b01) begin

        if (PPUY == 241) begin

            NMI       <= CTRL0[7];
            VBlankPPU <= VBlankPPU ^ VBlank ^ 1'b1;

        end


        else if (PPUY == 260) begin

            NMI       <= 1'b0;
            VBlankPPU <= VBlankPPU ^ VBlank ^ 1'b0;

        end

    end














    if (RESET) begin

        DMA <= 1'b0;
        odd <= 1'b0;

    end


    else if (DMA) begin


        case ({odd, div})

            3'b000: OAMW  <= 1'b0;
            3'b001: WDATA <= DATAIN;
            3'b010: begin OAMW <= 1'b1; odd <= 1'b1; end
            3'b100: OAMW  <= 1'b0;
            3'b101: WADDR[7:0] <= WADDR[7:0] + 1'b1;
            3'b110: begin odd <= 1'b0; if (WADDR[7:0] == 8'h00) DMA <= 1'b0; end

        endcase

    end





    
    else if (ea == 16'h4016) begin
    
        case (div)
        
            2'b01: if (WREQ) begin
            
                if (Joy1L == 1'b1 && din[0] == 1'b0)
                    Joy1Latch <= { 8'h08, 8'h00, JOY1 };
                    
                Joy1L <= din[0];

            end else if (RD) begin
            
                DOUT <= {7'b0100_000, Joy1Latch[0]};
                Joy1Latch <= {1'b0, Joy1Latch[23:1]};
            
            end
        
        endcase
    
    end
    

    else if (ea == 16'h4014 && WREQ && div == 2'b10) begin

        DMA   <= 1'b1;
        odd   <= 1'b0;
        WADDR <= {din, 8'h00};
        WVREQ <= 1'b0;

    end






    else if (ea[15:13] == 3'b001) begin


        WVREQ   <= (ea[2:0] == 3'h7) && (div == 2'b01) && WREQ && (ADDR >= 16'h2000 && ADDR < 16'h3F00);

        case (div)


            2'b00: begin OAMW <= 1'b0; end


            2'b01: begin

                case (ea[2:0])


                    3'h0: if (WREQ) CTRL0 <= din;


                    3'h1: if (WREQ) CTRL1 <= din;


                    3'h2: if (RD) begin

                        DOUT <= {
                            VBlank,
                            1'b0,
                            1'b0,
                            (PPUY > 241),
                            4'b0000
                        };


                        VBlankCPU <= VBlankCPU ^ VBlank ^ 1'b0;


                        FIRSTW <= 1;

                    end


                    3'h3: if (WREQ) SADDR <= din;


                    3'h4: if (RD | WREQ) begin WADDR <= SADDR; WDATA <= din; end


                    3'h5: if (WREQ) begin

                        if (FIRSTW) begin
                            RegHT <= din[7:3];
                            RegFH <= din[2:0];
                        end
                        else begin
                            RegVT <= din[7:3];
                            RegFV <= din[2:0];
                        end

                        FIRSTW <= ~FIRSTW;
                    end


                    3'h6: if (WREQ) begin

                        if (FIRSTW)begin

                            ADDR[15:8] <= din;

                            RegVT <= {din[1:0], RegVT[2:0]};
                            RegH  <= din[2];
                            RegV  <= din[3];
                            RegFV <= din[5:4];

                        end
                        elsebegin

                            RegVT <= {RegVT[4:3], din[7:5]};
                            RegHT <=  din[4:0];

                            ADDR[7:0]  <= din;

                        end

                        FIRSTW <= ~FIRSTW;
                    end


                    3'h7: begin


                        if (WREQ) begin

                            WADDR <= ADDR;


                            if (ADDR < 16'h3F00) begin WDATA <= din; end


                            else if (ADDR < 16'h3F10) begin PALBG[ ADDR[3:0] ] <= din[5:0]; end


                            else if (ADDR < 16'h3F20) begin PALSP[ ADDR[3:0] ] <= din[5:0]; end

                        end

                        else if (RD) begin


                            if (ADDR < 16'h3F00) begin
                                WADDR <= ADDR;
                                DOUT  <= BUFF;
                            end

                            else if (ADDR < 16'h3F10) begin
                                DOUT <= PALBG[ ADDR[3:0] ];
                            end
                            else if (ADDR < 16'h3F20) begin
                                DOUT <= PALSP[ ADDR[3:0] ];
                            end

                        end

                    end

                endcase

            end


            2'b10: begin

                case (ea[2:0])


                    3'h4: begin

                             if (RD  ) DOUT <= SPIN;
                        else if (WREQ) OAMW <= 1'b1;

                        if (RD | WREQ) SADDR <= SADDR + 1'b1;

                    end


                    3'h7: if (WREQ | RD) begin


                        if (RD && ADDR < 16'h3F00) begin
                            BUFF <= (ADDR < 16'h2000 ? FIN : VIN);
                        end

                        ADDR <= ADDR + (CTRL0[2] ? 6'h20 : 1'b1);

                    end

                endcase

            end

        endcase

    end

    else begin

        WVREQ <= 1'b0;

    end
end




always @(posedge DE2X) begin





    if (PPUX >= 16'h110) begin


        if (PPUX < 16'h110 + 32) case (PPUX[1:0])

            3'h0: begin

                if (CTRL0[5])
faddr <= {SpIcon[0], SpIcon[7:1], YVert[3], 1'b0, YVert[2:0]};
                else
faddr <= {CTRL0[3],  SpIcon[7:0],           1'b0, YVert[2:0]};

            end


            3'h1: begin Sprites[ SpId ][ 15:8 ]  <= FMirr; faddr[3] <= 1'b1; end
            3'h2: begin Sprites[ SpId ][ 31:24 ] <= FMirr; end

        endcase

    end




    else begin


        if (PPUX == 0) begin
        
            HitLatch <= HitLine;


            SpritesLatch[0] <= Sprites[0];
            SpritesLatch[1] <= Sprites[1];
            SpritesLatch[2] <= Sprites[2];
            SpritesLatch[3] <= Sprites[3];
            SpritesLatch[4] <= Sprites[4];
            SpritesLatch[5] <= Sprites[5];
            SpritesLatch[6] <= Sprites[6];
            SpritesLatch[7] <= Sprites[7];
            
            HitLine  <= 8'h00;
        
        end
        else if (PPUX < 8) begin 
        
            SAR     <= 1'b0; 
            ns      <= 4'h0; 

        end
        

        else if (PPUX < 16'h108) case (PPUX[1:0])



            2'h0: begin


                if (SpTest && !ns[3]) begin


                    SpHit <= 1'b1;


                    Sprites[ ns[2:0] ][ 31:24 ] <= (PPUY - SRD);


                end else SpHit <= 1'b0;

                SAR <= SAR + 1'b1;

            end


            2'h1: begin

                if (SpHit) Sprites[ ns[2:0] ][15:8] <= SRD;
                SAR <= SAR + 1'b1;

            end


            2'h2: begin

                if (SpHit) Sprites[ ns[2:0] ][23:16] = SRD;
                SAR <= SAR + 1'b1;

            end


            2'h3: begin

                if (SpHit) begin

                    Sprites[ ns[2:0] ][7:0] <= SRD;


                    HitLine[ ns[2:0] ] <= 1'b1;


                    ns <= ns[3] ? {4'b1000} : ns + 1'b1;

                end

                SAR <= SAR + 1'b1;

            end

        endcase

        case (X[2:0])



            3'h0: begin vaddr <= {NTBank, Y[7:3], X[7:3]};end


            3'h1: begin faddr <= {CTRL0[4], vdata[7:0], 1'b0, Y[2:0]};
                        vaddr <= {NTBank, 4'b1111, Y[7:5], X[7:5] }; end


            3'h2: begin faddr[3] <= 1'b1; chrl <= fdata; hiclr <= vdata; end


            3'h3: begin chrh <= fdata; end




            3'h7: begin


                colorpad <= {hiclr[ {Y[4], X[4], 1'b1} ],
                             hiclr[ {Y[4], X[4], 1'b0} ]};


                colormap <= {chrh[0], chrl[0],chrh[1], chrl[1],
chrh[2], chrl[2],chrh[3], chrl[3],
chrh[4], chrl[4],chrh[5], chrl[5],
chrh[6], chrl[6],chrh[7], chrl[7]};
            end

        endcase

    end




    if (y == vert_whole - 1) begin

        NTA  <= 2'b00;
        PPUY <= 1'b0;

    end


    else if (PPUX == 9'd340) begin

        PPUX <= 1'b0;
        DE2Y <= ~DE2Y;




        NTA  <= {1'b0, CTRL0[0]};


        if (DE2Y) PPUY <= PPUY + 1'b1;

    end else begin

        PPUX <= PPUX + 1'b1;

    end

end


always @(posedge CLK25) begin


    x <= x == (horiz_whole - 1) ? 1'b0 : (x + 1'b1);


    if (x == (horiz_whole - 1)) begin
        y <= y == (vert_whole - 1) ? 1'b0 : (y + 1'b1);
    end

    if (x < horiz_visible && y < vert_visible)
         {red, green, blue} <= {rgb[4:0], rgb[10:5], rgb[15:11]};
    else {red, green, blue} <= 16'h0000;

end


wire [4:0] scolor[8];
wire [4:0] final_color = scolor[7][4:0];
wire [8:0] SPRX = PPUX - 16;


evaluator Sprite1( HitLatch[0], SpritesLatch[0], {1'b0, colmp}, SPRX, scolor[0], CTRL1);
evaluator Sprite2( HitLatch[1], SpritesLatch[1], scolor[0], SPRX, scolor[1], CTRL1);
evaluator Sprite3( HitLatch[2], SpritesLatch[2], scolor[1], SPRX, scolor[2], CTRL1);
evaluator Sprite4( HitLatch[3], SpritesLatch[3], scolor[2], SPRX, scolor[3], CTRL1);
evaluator Sprite5( HitLatch[4], SpritesLatch[4], scolor[3], SPRX, scolor[4], CTRL1);
evaluator Sprite6( HitLatch[5], SpritesLatch[5], scolor[4], SPRX, scolor[5], CTRL1);
evaluator Sprite7( HitLatch[6], SpritesLatch[6], scolor[5], SPRX, scolor[6], CTRL1);
evaluator Sprite8( HitLatch[7], SpritesLatch[7], scolor[6], SPRX, scolor[7], CTRL1);


always @* case (color)

    6'd0:  rgb = 16'h73ae;
	6'd1:  rgb = 16'h88c4;
	6'd2:  rgb = 16'ha800;
	6'd3:  rgb = 16'h9808;
	6'd4:  rgb = 16'h7011;
	6'd5:  rgb = 16'h1015;
	6'd6:  rgb = 16'h0014;
	6'd7:  rgb = 16'h004f;
	6'd8:  rgb = 16'h0168;
	6'd9:  rgb = 16'h0220;
	6'd10: rgb = 16'h0280;
	6'd11: rgb = 16'h11e0;
	6'd12: rgb = 16'h59e3;
	6'd16: rgb = 16'hbdf7;
	6'd17: rgb = 16'heb80;
	6'd18: rgb = 16'he9c4;
	6'd19: rgb = 16'hf010;
	6'd20: rgb = 16'hb817;
	6'd21: rgb = 16'h581c;
	6'd22: rgb = 16'h015b;
	6'd23: rgb = 16'h0a79;
	6'd24: rgb = 16'h0391;
	6'd25: rgb = 16'h04a0;
	6'd26: rgb = 16'h0540;
	6'd27: rgb = 16'h3c80;
	6'd28: rgb = 16'h8c00;
	6'd32: rgb = 16'hffff;
	6'd33: rgb = 16'hfde7;
	6'd34: rgb = 16'hfcab;
	6'd35: rgb = 16'hfc54;
	6'd36: rgb = 16'hfbde;
	6'd37: rgb = 16'hb3bf;
	6'd38: rgb = 16'h63bf;
	6'd39: rgb = 16'h3cdf;
	6'd40: rgb = 16'h3dfe;
	6'd41: rgb = 16'h1690;
	6'd42: rgb = 16'h4ee9;
	6'd43: rgb = 16'h9fcb;
	6'd44: rgb = 16'hdf40;
	6'd48: rgb = 16'hffff;
	6'd49: rgb = 16'hff35;
	6'd50: rgb = 16'hfeb8;
	6'd51: rgb = 16'hfe5a;
	6'd52: rgb = 16'hfe3f;
	6'd53: rgb = 16'hde3f;
	6'd54: rgb = 16'hb5ff;
	6'd55: rgb = 16'haedf;
	6'd56: rgb = 16'ha73f;
	6'd57: rgb = 16'ha7fc;
	6'd58: rgb = 16'hbf95;
	6'd59: rgb = 16'hcff6;
	6'd60: rgb = 16'hf7f3;
	default: rgb = 1'b0;

endcase

endmodule