data/full_repos/permissive/143278/ivltests/force_lval_part.v
 line:16: before: "value"
1: b'%Error: data/full_repos/permissive/143278/ivltests/force_lval_part.v:16: Unsupported: Verilog 1995 force\n    force value[0 +: 4] = in;\n    ^~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass;
  reg [3:0] value;
  reg [3:0] in;

  initial begin
    pass = 1'b1;
    value = 4'b1001;
    if (value !== 4'b1001) begin
      $display("Failed: initial value, expected 4'b1001, got %b", value);
      pass = 1'b0;
    end

    in = 4'bzx10;

    force value[0 +: 4] = in;
    if (value !== 4'bzx10) begin
      $display("Failed: force value, expected 4'bzx10, got %b", value);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;
  reg [3:0] value;
  reg [3:0] in;

  initial begin
    pass = 1'b1;
    value = 4'b1001;
    if (value !== 4'b1001) begin
      $display("Failed: initial value, expected 4'b1001, got %b", value);
      pass = 1'b0;
    end

    in = 4'bzx10;

    force value[0 +: 4] = in;
    if (value !== 4'bzx10) begin
      $display("Failed: force value, expected 4'bzx10, got %b", value);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule