data/full_repos/permissive/148201731/rtl/top/top.v
1: b"%Error: data/full_repos/permissive/148201731/rtl/top/top.v:77: Cannot find file containing module: 'dlx_processor'\ndlx_processor\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/148201731/rtl/top,data/full_repos/permissive/148201731/dlx_processor\n             data/full_repos/permissive/148201731/rtl/top,data/full_repos/permissive/148201731/dlx_processor.v\n             data/full_repos/permissive/148201731/rtl/top,data/full_repos/permissive/148201731/dlx_processor.sv\n             dlx_processor\n             dlx_processor.v\n             dlx_processor.sv\n             obj_dir/dlx_processor\n             obj_dir/dlx_processor.v\n             obj_dir/dlx_processor.sv\n%Error: data/full_repos/permissive/148201731/rtl/top/top.v:101: Cannot find file containing module: 'mux_sram'\nmux_sram\n^~~~~~~~\n%Error: data/full_repos/permissive/148201731/rtl/top/top.v:127: Cannot find file containing module: 'bootloader'\nbootloader \n^~~~~~~~~~\n%Error: data/full_repos/permissive/148201731/rtl/top/top.v:146: Cannot find file containing module: 'sram_ctrl'\nsram_ctrl \n^~~~~~~~~\n%Error: data/full_repos/permissive/148201731/rtl/top/top.v:167: Cannot find file containing module: 'mux_sdram'\nmux_sdram\n^~~~~~~~~\n%Error: data/full_repos/permissive/148201731/rtl/top/top.v:186: Cannot find file containing module: 'data_memory_controll'\ndata_memory_controll\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module top
      #(
         parameter DATA_WIDTH = 32,
         parameter DATA_ADDR_WIDTH = 32,
         parameter INST_ADDR_WIDTH = 20,
         parameter DQM_WIDTH = 4,
         parameter BA_WIDTH = 2
      )
      (
         input clk,
         input rst_n,
         input clk_proc,

         output boot_rom_rd_en,
         output [INST_ADDR_WIDTH-1:0] boot_rom_addr,
         input [DATA_WIDTH-1:0] boot_rom_rd_data,

         output sram_ub_n,
         output sram_lb_n,
         output sram_ce_n,
         output sram_we_n,
         output sram_oe_n,
         output [DATA_ADDR_WIDTH-1:0] sram_addr,
         output [DATA_WIDTH-1:0] sram_wr_data,
         input [DATA_WIDTH-1:0] sram_rd_data,

         input [DATA_WIDTH-1:0] dram_dq_in,
         output [DATA_WIDTH-1:0] dram_dq_out,
         output [INST_ADDR_WIDTH-1:0] dram_addr,
         output [DQM_WIDTH-1:0] dram_dqm,
         output dram_we_n,
         output dram_cas_n,
         output dram_ras_n,
         output dram_cs_n,
         output [BA_WIDTH-1:0] dram_ba,
         output dram_clk,
         output dram_cke,
         output [DATA_WIDTH-1:0] gpio_o,
         output we_gpio

      );

/

   .boot_mode(boot_mode),
   .boot_mem_wr_en(boot_mem_wr_en),
   .boot_mem_addr(boot_mem_addr),
   .boot_mem_rd_data(boot_mem_wr_data),

   .inst_mem_wr_en(1'b0),
   .inst_mem_rd_en(inst_mem_rd_en_proc),
   .inst_mem_wr_data(32'd0),
   .inst_mem_rd_data(inst_mem_rd_data_proc),
   .inst_mem_addr(inst_mem_addr_proc),

   .sram_mem_wr_en(sram_mem_wr_en),
   .sram_mem_rd_en(sram_mem_rd_en),
   .sram_mem_wr_data(sram_mem_wr_data),
   .sram_mem_rd_data(sram_mem_rd_data),
   .sram_mem_addr(sram_mem_addr)
   );

bootloader 
   #(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(INST_ADDR_WIDTH)
   )
   bootloader_u0
   (
   .clk(clk_proc),
   .rst_n(rst_n),
   .boot_mode(boot_mode),
   .boot_mem_rd_en(boot_rom_rd_en),
   .boot_mem_addr(boot_rom_addr),
   .boot_mem_rd_data(boot_rom_rd_data),

   .inst_mem_wr_en(boot_mem_wr_en),
   .inst_mem_wr_data(boot_mem_wr_data),
   .inst_mem_addr(boot_mem_addr)
   );

sram_ctrl 
   sram_ctrl_u0
   (
   .clk(clk),
   .rst_n(rst_n),
   .clk_proc(clk_proc),
   .wr_en(sram_mem_wr_en),
   .rd_en(sram_mem_rd_en),
   .wr_data(sram_mem_wr_data),
   .addr({1'b0,sram_mem_addr[19:0]}),
   .rd_data(sram_mem_rd_data),
   .sram_ub_n(sram_ub_n),
   .sram_lb_n(sram_lb_n),
   .sram_ce_n(sram_ce_n),
   .sram_we_n(sram_we_n),
   .sram_oe_n(sram_oe_n),
   .sram_addr(sram_addr),
   .sram_wr_data(sram_wr_data),
   .sram_rd_data(sram_rd_data)
   );

mux_sdram
#(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(DATA_ADDR_WIDTH)
      
)
mux_sdram_u0
(

   .wr_en(data_wr_en_proc),
   .wr_data(data_write_proc),
   .wr_address(data_addr_proc),

   .wr_en_sdram(wr_en_sdram),
   .wr_data_gpio(gpio_o),
   .we_gpio(we_gpio),
   .wr_data_sdram(wr_data_sdram)
);

data_memory_controll
  #(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(DATA_ADDR_WIDTH),
   .SDRAM_DATA_WIDTH(DATA_WIDTH),
   .SDRAM_ADDR_WIDTH(DATA_WIDTH)

  )
  data_memory_controll_u0
  (
   .clk(clk),
   .rst_n(rst_n),
   .data_rd_en(data_rd_en_proc),
   .data_wr_en(wr_en_sdram),
   .data_addr(data_addr_proc),
   .data_out(data_read_proc),
   .data_in(wr_data_sdram),

   .dram_dq_in(dram_dq_in),
   .dram_dq_out(dram_dq_out),
   .dram_addr(dram_addr),
   .dram_dqm(dram_dqm),
   .dram_we_n(dram_we_n),
   .dram_cas_n(dram_cas_n),
   .dram_ras_n(dram_ras_n),
   .dram_cs_n(dram_cs_n),
   .dram_ba(dram_ba),
   .dram_clk(dram_clk),
   .dram_cke(dram_cke)
  );

endmodule
module top
      #(
         parameter DATA_WIDTH = 32,
         parameter DATA_ADDR_WIDTH = 32,
         parameter INST_ADDR_WIDTH = 20,
         parameter DQM_WIDTH = 4,
         parameter BA_WIDTH = 2
      )
      (
         input clk,
         input rst_n,
         input clk_proc,

         output boot_rom_rd_en,
         output [INST_ADDR_WIDTH-1:0] boot_rom_addr,
         input [DATA_WIDTH-1:0] boot_rom_rd_data,

         output sram_ub_n,
         output sram_lb_n,
         output sram_ce_n,
         output sram_we_n,
         output sram_oe_n,
         output [DATA_ADDR_WIDTH-1:0] sram_addr,
         output [DATA_WIDTH-1:0] sram_wr_data,
         input [DATA_WIDTH-1:0] sram_rd_data,

         input [DATA_WIDTH-1:0] dram_dq_in,
         output [DATA_WIDTH-1:0] dram_dq_out,
         output [INST_ADDR_WIDTH-1:0] dram_addr,
         output [DQM_WIDTH-1:0] dram_dqm,
         output dram_we_n,
         output dram_cas_n,
         output dram_ras_n,
         output dram_cs_n,
         output [BA_WIDTH-1:0] dram_ba,
         output dram_clk,
         output dram_cke,
         output [DATA_WIDTH-1:0] gpio_o,
         output we_gpio

      );


/

   .boot_mode(boot_mode),
   .boot_mem_wr_en(boot_mem_wr_en),
   .boot_mem_addr(boot_mem_addr),
   .boot_mem_rd_data(boot_mem_wr_data),

   .inst_mem_wr_en(1'b0),
   .inst_mem_rd_en(inst_mem_rd_en_proc),
   .inst_mem_wr_data(32'd0),
   .inst_mem_rd_data(inst_mem_rd_data_proc),
   .inst_mem_addr(inst_mem_addr_proc),

   .sram_mem_wr_en(sram_mem_wr_en),
   .sram_mem_rd_en(sram_mem_rd_en),
   .sram_mem_wr_data(sram_mem_wr_data),
   .sram_mem_rd_data(sram_mem_rd_data),
   .sram_mem_addr(sram_mem_addr)
   );

bootloader 
   #(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(INST_ADDR_WIDTH)
   )
   bootloader_u0
   (
   .clk(clk_proc),
   .rst_n(rst_n),
   .boot_mode(boot_mode),
   .boot_mem_rd_en(boot_rom_rd_en),
   .boot_mem_addr(boot_rom_addr),
   .boot_mem_rd_data(boot_rom_rd_data),

   .inst_mem_wr_en(boot_mem_wr_en),
   .inst_mem_wr_data(boot_mem_wr_data),
   .inst_mem_addr(boot_mem_addr)
   );

sram_ctrl 
   sram_ctrl_u0
   (
   .clk(clk),
   .rst_n(rst_n),
   .clk_proc(clk_proc),
   .wr_en(sram_mem_wr_en),
   .rd_en(sram_mem_rd_en),
   .wr_data(sram_mem_wr_data),
   .addr({1'b0,sram_mem_addr[19:0]}),
   .rd_data(sram_mem_rd_data),
   .sram_ub_n(sram_ub_n),
   .sram_lb_n(sram_lb_n),
   .sram_ce_n(sram_ce_n),
   .sram_we_n(sram_we_n),
   .sram_oe_n(sram_oe_n),
   .sram_addr(sram_addr),
   .sram_wr_data(sram_wr_data),
   .sram_rd_data(sram_rd_data)
   );

mux_sdram
#(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(DATA_ADDR_WIDTH)
      
)
mux_sdram_u0
(

   .wr_en(data_wr_en_proc),
   .wr_data(data_write_proc),
   .wr_address(data_addr_proc),

   .wr_en_sdram(wr_en_sdram),
   .wr_data_gpio(gpio_o),
   .we_gpio(we_gpio),
   .wr_data_sdram(wr_data_sdram)
);

data_memory_controll
  #(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(DATA_ADDR_WIDTH),
   .SDRAM_DATA_WIDTH(DATA_WIDTH),
   .SDRAM_ADDR_WIDTH(DATA_WIDTH)

  )
  data_memory_controll_u0
  (
   .clk(clk),
   .rst_n(rst_n),
   .data_rd_en(data_rd_en_proc),
   .data_wr_en(wr_en_sdram),
   .data_addr(data_addr_proc),
   .data_out(data_read_proc),
   .data_in(wr_data_sdram),

   .dram_dq_in(dram_dq_in),
   .dram_dq_out(dram_dq_out),
   .dram_addr(dram_addr),
   .dram_dqm(dram_dqm),
   .dram_we_n(dram_we_n),
   .dram_cas_n(dram_cas_n),
   .dram_ras_n(dram_ras_n),
   .dram_cs_n(dram_cs_n),
   .dram_ba(dram_ba),
   .dram_clk(dram_clk),
   .dram_cke(dram_cke)
  );

endmodule