data/full_repos/permissive/162533945/mux_8to1_32bit.v
1: b"%Error: data/full_repos/permissive/162533945/mux_8to1_32bit.v:10: Cannot find file containing module: 'mux_8to1_1bit'\n    mux_8to1_1bit mux(i0[i], i1[i], i2[i], i3[i], i4[i], i5[i], i6[i], i7[i], s0, s1, s2, out[i]);\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/mux_8to1_1bit\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/mux_8to1_1bit.v\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/mux_8to1_1bit.sv\n             mux_8to1_1bit\n             mux_8to1_1bit.v\n             mux_8to1_1bit.sv\n             obj_dir/mux_8to1_1bit\n             obj_dir/mux_8to1_1bit.v\n             obj_dir/mux_8to1_1bit.sv\n%Error: Exiting due to 1 error(s)\n"
module mux_8to1_32bit(i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2, out);

	input [31:0] i0, i1, i2, i3, i4, i5, i6, i7;
	input s0, s1, s2;
	output [31:0] out;
	
	genvar i;
		generate
			for (i=0; i<32; i=i+1) begin: mux
				mux_8to1_1bit mux(i0[i], i1[i], i2[i], i3[i], i4[i], i5[i], i6[i], i7[i], s0, s1, s2, out[i]);
			end
		endgenerate
		
endmodule
module mux_8to1_32bit(i0, i1, i2, i3, i4, i5, i6, i7, s0, s1, s2, out);


	input [31:0] i0, i1, i2, i3, i4, i5, i6, i7;
	input s0, s1, s2;
	output [31:0] out;
	
	genvar i;
		generate
			for (i=0; i<32; i=i+1) begin: mux
				mux_8to1_1bit mux(i0[i], i1[i], i2[i], i3[i], i4[i], i5[i], i6[i], i7[i], s0, s1, s2, out[i]);
			end
		endgenerate
		
endmodule