data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v
1: b'%Error: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:11: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("fsm111.vcd"); \n^~~~~~~~~\n%Error: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:12: Unsupported or unknown PLI call: $dumpvars\n$dumpvars; \n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:17: Unsupported: Ignoring delay on this delayed statement.\n#00 clk <= 1\'b0 ; \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:18: Unsupported: Ignoring delay on this delayed statement.\nforever #50 clk <= ~ clk ; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:21: Unsupported: Ignoring delay on this delayed statement.\ninitial forever #100 in = $random %2 ; \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:25: Unsupported: Ignoring delay on this delayed statement.\n#0000 rst = 1\'b1; #0050 rst = 1\'b0; #0050 rst = 1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:25: Unsupported: Ignoring delay on this delayed statement.\n#0000 rst = 1\'b1; #0050 rst = 1\'b0; #0050 rst = 1\'b1; \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:25: Unsupported: Ignoring delay on this delayed statement.\n#0000 rst = 1\'b1; #0050 rst = 1\'b0; #0050 rst = 1\'b1; \n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:26: Unsupported: Ignoring delay on this delayed statement.\n#2000 rst = 1\'b0; #0050 rst = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:26: Unsupported: Ignoring delay on this delayed statement.\n#2000 rst = 1\'b0; #0050 rst = 1\'b1;\n                  ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fsm111(z,y,clk,rst);

output reg z ; 
input y,clk,rst ;


parameter idle =2'b00 , got1 = 2'b01, got11 = 2'b11, got111 = 2'b10 ; 


reg [1:0] NextState, CurrentState ; 


always @(posedge clk, negedge rst)
begin 
if(!rst) CurrentState <= idle ; 
else     CurrentState <= NextState ;
end


always @(*)
begin 
case(CurrentState)
2'b00   :begin 
            if(y) NextState <= got1 ; 
            else NextState <= idle ;
         end
2'b01   :begin 
            if(y) NextState <= got11 ; 
            else NextState <= idle ;
         end
2'b11   :begin 
            if(y) NextState <= got111 ; 
            else NextState <= idle ;
         end
2'b10   :begin 
            if(y) NextState <= got1 ; 
            else NextState <= idle ;
         end
default : NextState <= idle ;
endcase  
end


always @(*)
begin 
case(CurrentState)
2'b00   : z <= 1'b0 ;
2'b01   : z <= 1'b0 ;
2'b11   : z <= 1'b0 ; 
2'b10   : z <= 1'b1 ; 
default : z <= 1'b0 ;  
endcase
end

endmodule
module fsm111(z,y,clk,rst);


output reg z ; 
input y,clk,rst ;


parameter idle =2'b00 , got1 = 2'b01, got11 = 2'b11, got111 = 2'b10 ; 


reg [1:0] NextState, CurrentState ; 


always @(posedge clk, negedge rst)
begin 
if(!rst) CurrentState <= idle ; 
else     CurrentState <= NextState ;
end


always @(*)
begin 
case(CurrentState)
2'b00   :begin 
            if(y) NextState <= got1 ; 
            else NextState <= idle ;
         end
2'b01   :begin 
            if(y) NextState <= got11 ; 
            else NextState <= idle ;
         end
2'b11   :begin 
            if(y) NextState <= got111 ; 
            else NextState <= idle ;
         end
2'b10   :begin 
            if(y) NextState <= got1 ; 
            else NextState <= idle ;
         end
default : NextState <= idle ;
endcase  
end


always @(*)
begin 
case(CurrentState)
2'b00   : z <= 1'b0 ;
2'b01   : z <= 1'b0 ;
2'b11   : z <= 1'b0 ; 
2'b10   : z <= 1'b1 ; 
default : z <= 1'b0 ;  
endcase
end

endmodule