data/full_repos/permissive/109594910/vga.v
1: b"%Error: data/full_repos/permissive/109594910/vga.v:20: Duplicate declaration of signal: 'clk_vga'\n                                                     : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire clk_vga;\n         ^~~~~~~\n        data/full_repos/permissive/109594910/vga.v:2: ... Location of original declaration\n    input clk_vga,\n          ^~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:21: Duplicate declaration of signal: 'vga_frame'\n    reg [7:0] vga_frame = 0;\n              ^~~~~~~~~\n        data/full_repos/permissive/109594910/vga.v:3: ... Location of original declaration\n    output [7:0] vga_frame,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:22: Duplicate declaration of signal: 'vga_r'\n    wire [3:0] vga_r, vga_g, vga_b;\n               ^~~~~\n        data/full_repos/permissive/109594910/vga.v:4: ... Location of original declaration\n    output [3:0] vga_r,\n                 ^~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:22: Duplicate declaration of signal: 'vga_g'\n    wire [3:0] vga_r, vga_g, vga_b;\n                      ^~~~~\n        data/full_repos/permissive/109594910/vga.v:5: ... Location of original declaration\n    output [3:0] vga_g,\n                 ^~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:22: Duplicate declaration of signal: 'vga_b'\n    wire [3:0] vga_r, vga_g, vga_b;\n                             ^~~~~\n        data/full_repos/permissive/109594910/vga.v:6: ... Location of original declaration\n    output [3:0] vga_b,\n                 ^~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:23: Duplicate declaration of signal: 'vga_hs'\n    wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift;  \n         ^~~~~~\n        data/full_repos/permissive/109594910/vga.v:7: ... Location of original declaration\n    output vga_hs,\n           ^~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:23: Duplicate declaration of signal: 'vga_vs'\n    wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift;  \n                 ^~~~~~\n        data/full_repos/permissive/109594910/vga.v:8: ... Location of original declaration\n    output vga_vs,\n           ^~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:23: Duplicate declaration of signal: 'vga_blank'\n    wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift;  \n                         ^~~~~~~~~\n        data/full_repos/permissive/109594910/vga.v:9: ... Location of original declaration\n    output vga_blank,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:23: Duplicate declaration of signal: 'fetch_cell'\n    wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift;  \n                                    ^~~~~~~~~~\n        data/full_repos/permissive/109594910/vga.v:13: ... Location of original declaration\n    output fetch_cell,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:23: Duplicate declaration of signal: 'fetch_font'\n    wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift;  \n                                                ^~~~~~~~~~\n        data/full_repos/permissive/109594910/vga.v:14: ... Location of original declaration\n    output fetch_font,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:23: Duplicate declaration of signal: 'load_nshift'\n    wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift;  \n                                                            ^~~~~~~~~~~\n        data/full_repos/permissive/109594910/vga.v:15: ... Location of original declaration\n    output load_nshift,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:24: Duplicate declaration of signal: 'cell_addr'\n    reg [11:0] cell_addr;\n               ^~~~~~~~~\n        data/full_repos/permissive/109594910/vga.v:16: ... Location of original declaration\n    output [11:0] cell_addr,\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:69: Duplicate declaration of signal: 'hpos'\n    reg [9:0] hpos = -hfp;\n              ^~~~\n        data/full_repos/permissive/109594910/vga.v:17: ... Location of original declaration\n    output [9:0] hpos,\n                 ^~~~\n%Error: data/full_repos/permissive/109594910/vga.v:70: Duplicate declaration of signal: 'vpos'\n    reg [9:0] vpos = -vfp;\n              ^~~~\n        data/full_repos/permissive/109594910/vga.v:18: ... Location of original declaration\n    output [9:0] vpos\n                 ^~~~\n%Error: data/full_repos/permissive/109594910/vga.v:91: Duplicate declaration of signal: 'fetch_start'\n    wire fetch_start = hpos == -10'd9;\n         ^~~~~~~~~~~\n        data/full_repos/permissive/109594910/vga.v:12: ... Location of original declaration\n    output fetch_start,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:93: Duplicate declaration of signal: 'fetch_first'\n    wire fetch_first = vpos == 0;\n         ^~~~~~~~~~~\n        data/full_repos/permissive/109594910/vga.v:10: ... Location of original declaration\n    output fetch_first,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109594910/vga.v:94: Duplicate declaration of signal: 'line_top'\n    wire line_top = vpos[3:0] == 0;\n         ^~~~~~~~\n        data/full_repos/permissive/109594910/vga.v:11: ... Location of original declaration\n    output line_top,\n           ^~~~~~~~\n%Error: Exiting due to 17 error(s)\n"
module vga (
    input clk_vga,
    output [7:0] vga_frame,
    output [3:0] vga_r,
    output [3:0] vga_g,
    output [3:0] vga_b,
    output vga_hs,
    output vga_vs,
    output vga_blank,
    output fetch_first,
    output line_top,
    output fetch_start,
    output fetch_cell,
    output fetch_font,
    output load_nshift,
    output [11:0] cell_addr,
    output [9:0] hpos,
    output [9:0] vpos
);
    wire clk_vga;
    reg [7:0] vga_frame = 0;
    wire [3:0] vga_r, vga_g, vga_b;
    wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift;  
    reg [11:0] cell_addr;

    



    localparam hfp = 10'd18;
    localparam hsp = 10'd108;
    localparam hbp = 10'd54;
    localparam hactive = 10'd720;
    localparam htotal = hactive + hfp + hsp + hbp;
    localparam hend = hactive + hfp + hsp - 1;
    localparam hstart =  -hbp;




    localparam vfp = 10'd13;
    localparam vsp = 10'd2;
    localparam vbp = 10'd34;
    localparam vactive = 10'd400;
    localparam vtotal = vactive + vfp + vsp + vbp;
    localparam vend = vactive + vfp + vsp - 1;
    localparam vstart = -vbp;


  

    reg [9:0] hpos = -hfp;
    reg [9:0] vpos = -vfp;



    wire hblank_start = hpos == hactive - 1;
    wire hblank_stop  = hpos == -10'd1;
    wire hsync_start  = hpos == (hactive + hfp) - 1;
    wire hsync_stop   = hpos == (hactive + hfp + hsp) - 1;    
    wire hreset       = hpos == hend;

    wire vblank_start = vpos == vactive;
    wire vblank_stop  = vpos == 10'd0;
    wire vsync_start  = vpos == (vactive + vfp);
    wire vsync_stop   = vpos == vstart;
    wire vreset       = vpos == vend;

    reg hblank=1;
    reg vblank=1;
    reg hsync=0;
    reg vsync=0;

    wire fetch_start = hpos == -10'd9;
    wire fetch_stop = hpos == hactive - 9;
    wire fetch_first = vpos == 0;
    wire line_top = vpos[3:0] == 0;
    reg fetching=0;



    always@(posedge clk_vga) begin
        if (hreset) begin
            hpos <= hstart;
            if (vreset) begin
                vpos <= vstart;
                vga_frame <= vga_frame + 1;
            end else
                vpos <= vpos + 1;
        end else begin
            hpos <= (hpos + 1);
        end
    end


    always@(posedge clk_vga) begin
        hblank <= hblank_start ? 1 : (hblank_stop ? 0 : hblank);
        hsync <= hsync_start ? 1 : (hsync_stop ? 0 : hsync);
        vblank <= vblank_start ? 1 : (vblank_stop ? 0 : vblank);
        vsync <= vsync_start ? 1 : (vsync_stop ? 0 : vsync);
        fetching <= fetch_start ? ~vblank : (fetch_stop ? 0 : fetching);
    end

    assign vga_hs = ~hsync;
    assign vga_vs = vsync;

    wire blank = vblank | hblank;

    assign fetch_cell = fetching ? hpos[2:0] == 3'b000 : 0;
    assign fetch_font = fetching ? hpos[2:0] == 3'b100 : 0;
    assign load_nshift = fetching ? hpos[2:0] == 3'b111 : 0;
    
    reg new_line;
    reg [11:0] text_line_addr;

    always @(posedge clk_vga) begin
        new_line <= hreset;
        if (new_line) begin
            if (vpos == 0)  begin
                cell_addr <= 0;
                text_line_addr <= 0;
            end else if (line_top) begin
                text_line_addr <= cell_addr;
            end else begin
                cell_addr <= text_line_addr;
            end

        end
        if (fetch_cell)
            cell_addr <= cell_addr + 1;
    end




    wire border = ((hpos == 0) || (hpos == hactive - 1) ||
                   (vpos == 0) || (vpos == vactive -1) ||
                   (hpos == hactive / 2) || (vpos == vactive / 2));

    



    wire [3:0] rgbi = blank ? 4'h0 : (border ? 4'hf : hpos[8:5] ^ vpos[7:4]);
    wire r = rgbi[2];
    wire g = rgbi[1];
    wire b = rgbi[0];
    wire i = rgbi[3];

    wire [7:0] rgbii = blank ? 8'h0 : (border ? 8'hff : hpos[8:1] - vpos[7:0]);
    wire [1:0] bb = rgbii[1:0];
    wire [1:0] gg = rgbii[3:2];
    wire [1:0] rr = rgbii[5:4];
    wire [1:0] ii = rgbii[7:6];

    wire left = hpos < hactive /2;

    assign vga_r = left?{rr[1], ii[1], rr[0], ii[0]}:{rr,ii};
    assign vga_g = left?{gg[1], ii[1], gg[0], gg[0]}:{gg,ii};
    assign vga_b = left?{bb[1], ii[1], bb[0], bb[0]}:{bb,ii};

    assign vga_blank = blank;

endmodule
module vga (
    input clk_vga,
    output [7:0] vga_frame,
    output [3:0] vga_r,
    output [3:0] vga_g,
    output [3:0] vga_b,
    output vga_hs,
    output vga_vs,
    output vga_blank,
    output fetch_first,
    output line_top,
    output fetch_start,
    output fetch_cell,
    output fetch_font,
    output load_nshift,
    output [11:0] cell_addr,
    output [9:0] hpos,
    output [9:0] vpos
);

    wire clk_vga;
    reg [7:0] vga_frame = 0;
    wire [3:0] vga_r, vga_g, vga_b;
    wire vga_hs, vga_vs, vga_blank, fetch_cell, fetch_font, load_nshift;  
    reg [11:0] cell_addr;

    



    localparam hfp = 10'd18;
    localparam hsp = 10'd108;
    localparam hbp = 10'd54;
    localparam hactive = 10'd720;
    localparam htotal = hactive + hfp + hsp + hbp;
    localparam hend = hactive + hfp + hsp - 1;
    localparam hstart =  -hbp;




    localparam vfp = 10'd13;
    localparam vsp = 10'd2;
    localparam vbp = 10'd34;
    localparam vactive = 10'd400;
    localparam vtotal = vactive + vfp + vsp + vbp;
    localparam vend = vactive + vfp + vsp - 1;
    localparam vstart = -vbp;


  

    reg [9:0] hpos = -hfp;
    reg [9:0] vpos = -vfp;



    wire hblank_start = hpos == hactive - 1;
    wire hblank_stop  = hpos == -10'd1;
    wire hsync_start  = hpos == (hactive + hfp) - 1;
    wire hsync_stop   = hpos == (hactive + hfp + hsp) - 1;    
    wire hreset       = hpos == hend;

    wire vblank_start = vpos == vactive;
    wire vblank_stop  = vpos == 10'd0;
    wire vsync_start  = vpos == (vactive + vfp);
    wire vsync_stop   = vpos == vstart;
    wire vreset       = vpos == vend;

    reg hblank=1;
    reg vblank=1;
    reg hsync=0;
    reg vsync=0;

    wire fetch_start = hpos == -10'd9;
    wire fetch_stop = hpos == hactive - 9;
    wire fetch_first = vpos == 0;
    wire line_top = vpos[3:0] == 0;
    reg fetching=0;



    always@(posedge clk_vga) begin
        if (hreset) begin
            hpos <= hstart;
            if (vreset) begin
                vpos <= vstart;
                vga_frame <= vga_frame + 1;
            end else
                vpos <= vpos + 1;
        end else begin
            hpos <= (hpos + 1);
        end
    end


    always@(posedge clk_vga) begin
        hblank <= hblank_start ? 1 : (hblank_stop ? 0 : hblank);
        hsync <= hsync_start ? 1 : (hsync_stop ? 0 : hsync);
        vblank <= vblank_start ? 1 : (vblank_stop ? 0 : vblank);
        vsync <= vsync_start ? 1 : (vsync_stop ? 0 : vsync);
        fetching <= fetch_start ? ~vblank : (fetch_stop ? 0 : fetching);
    end

    assign vga_hs = ~hsync;
    assign vga_vs = vsync;

    wire blank = vblank | hblank;

    assign fetch_cell = fetching ? hpos[2:0] == 3'b000 : 0;
    assign fetch_font = fetching ? hpos[2:0] == 3'b100 : 0;
    assign load_nshift = fetching ? hpos[2:0] == 3'b111 : 0;
    
    reg new_line;
    reg [11:0] text_line_addr;

    always @(posedge clk_vga) begin
        new_line <= hreset;
        if (new_line) begin
            if (vpos == 0)  begin
                cell_addr <= 0;
                text_line_addr <= 0;
            end else if (line_top) begin
                text_line_addr <= cell_addr;
            end else begin
                cell_addr <= text_line_addr;
            end

        end
        if (fetch_cell)
            cell_addr <= cell_addr + 1;
    end




    wire border = ((hpos == 0) || (hpos == hactive - 1) ||
                   (vpos == 0) || (vpos == vactive -1) ||
                   (hpos == hactive / 2) || (vpos == vactive / 2));

    



    wire [3:0] rgbi = blank ? 4'h0 : (border ? 4'hf : hpos[8:5] ^ vpos[7:4]);
    wire r = rgbi[2];
    wire g = rgbi[1];
    wire b = rgbi[0];
    wire i = rgbi[3];

    wire [7:0] rgbii = blank ? 8'h0 : (border ? 8'hff : hpos[8:1] - vpos[7:0]);
    wire [1:0] bb = rgbii[1:0];
    wire [1:0] gg = rgbii[3:2];
    wire [1:0] rr = rgbii[5:4];
    wire [1:0] ii = rgbii[7:6];

    wire left = hpos < hactive /2;

    assign vga_r = left?{rr[1], ii[1], rr[0], ii[0]}:{rr,ii};
    assign vga_g = left?{gg[1], ii[1], gg[0], gg[0]}:{gg,ii};
    assign vga_b = left?{bb[1], ii[1], bb[0], bb[0]}:{bb,ii};

    assign vga_blank = blank;

endmodule