data/full_repos/permissive/112626266/PIPELINE.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/112626266/PIPELINE.v:23: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'IFID\'\nmodule IFID(clock,Inst,IFIDWrite ,PcPlusFour,InstReg,PcPlusFourReg);\n       ^~~~\n                                                                     : ... Top module \'IDEX\'\nmodule IDEX(clock,WB,M,EX,DataA,DataB,imm_value,RegRs,RegRt,RegRd,WBreg,Mreg,EXreg,DataAreg,\n       ^~~~\n                                                                     : ... Top module \'EXMEM\'\nmodule EXMEM(clock,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);\n       ^~~~~\n                                                                     : ... Top module \'MEMWB\'\nmodule MEMWB(clock,WB,Memout,ALUOut,RegRD,WBreg,Memreg,ALUreg,RegRDreg);\n       ^~~~~\n%Error: Exiting due to 1 warning(s)\n'
module IFID(clock,Inst,IFIDWrite ,PcPlusFour,InstReg,PcPlusFourReg);
input           clock,IFIDWrite;

input           [31:0] PcPlusFour,Inst;
output  reg     [31:0] InstReg, PcPlusFourReg;
initial 
begin                   
InstReg = 0;
PcPlusFourReg = 0;
end
always@(posedge clock)
begin
if(IFIDWrite)
begin
InstReg <= Inst;
PcPlusFourReg <= PcPlusFour;
end
end
endmodule
module IFID(clock,Inst,IFIDWrite ,PcPlusFour,InstReg,PcPlusFourReg);

input           clock,IFIDWrite;

input           [31:0] PcPlusFour,Inst;
output  reg     [31:0] InstReg, PcPlusFourReg;
initial 
begin                   
InstReg = 0;
PcPlusFourReg = 0;
end
always@(posedge clock)
begin
if(IFIDWrite)
begin
InstReg <= Inst;
PcPlusFourReg <= PcPlusFour;
end
end
endmodule