data/full_repos/permissive/106408053/verilog/trigger.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger.v:75: Cannot find file containing module: \'stage\'\nstage stage0 (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/stage\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/stage.v\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/stage.sv\n             stage\n             stage.v\n             stage.sv\n             obj_dir/stage\n             obj_dir/stage.v\n             obj_dir/stage.sv\n%Error: data/full_repos/permissive/106408053/verilog/trigger.v:82: Cannot find file containing module: \'stage\'\nstage stage1 (\n^~~~~\n%Error: data/full_repos/permissive/106408053/verilog/trigger.v:89: Cannot find file containing module: \'stage\'\nstage stage2 (\n^~~~~\n%Error: data/full_repos/permissive/106408053/verilog/trigger.v:96: Cannot find file containing module: \'stage\'\nstage stage3 (\n^~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module trigger(
  clock, reset, 
  dataIn, validIn, 
  wrMask, wrValue,
  wrConfig, wrEdge,
  config_data,
  arm, demux_mode, 

  capture, run);

input clock, reset;
input validIn;
input [31:0] dataIn;
input [3:0] wrMask;
input [3:0] wrValue;
input [3:0] wrConfig;
input [3:0] wrEdge;
input [31:0] config_data;
input arm;
input demux_mode;
output capture;
output run;

reg capture, next_capture;
reg [1:0] levelReg, next_levelReg;


wire [3:0] stageRun;
wire run = |stageRun;





wire [3:0] stageMatch;
stage stage0 (
  .clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn), 
  .wrMask(wrMask[0]), .wrValue(wrValue[0]), .wrEdge(wrEdge[0]), 
  .wrConfig(wrConfig[0]), .config_data(config_data),
  .arm(arm), .level(levelReg), .demux_mode(demux_mode),
  .run(stageRun[0]), .match(stageMatch[0]));

stage stage1 (
  .clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn), 
  .wrMask(wrMask[1]), .wrValue(wrValue[1]), .wrEdge(wrEdge[1]), 
  .wrConfig(wrConfig[1]), .config_data(config_data),
  .arm(arm), .level(levelReg), .demux_mode(demux_mode),
  .run(stageRun[1]), .match(stageMatch[1]));

stage stage2 (
  .clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn), 
  .wrMask(wrMask[2]), .wrValue(wrValue[2]), .wrEdge(wrEdge[2]), 
  .wrConfig(wrConfig[2]), .config_data(config_data),
  .arm(arm), .level(levelReg), .demux_mode(demux_mode),
  .run(stageRun[2]), .match(stageMatch[2]));

stage stage3 (
  .clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn), 
  .wrMask(wrMask[3]), .wrValue(wrValue[3]), .wrEdge(wrEdge[3]), 
  .wrConfig(wrConfig[3]), .config_data(config_data),
  .arm(arm), .level(levelReg), .demux_mode(demux_mode),
  .run(stageRun[3]), .match(stageMatch[3]));





initial levelReg = 2'b00;
always @(posedge clock or posedge reset) 
begin : P2
  if (reset) 
    begin
      capture = 1'b0;
      levelReg = 2'b00;
    end
  else 
    begin
      capture = next_capture;
      levelReg = next_levelReg;
    end
end

always @*
begin
  #1;
  next_capture = arm | capture;
  next_levelReg = levelReg;
  if (|stageMatch) next_levelReg = levelReg + 1;
end
endmodule
module trigger(
  clock, reset, 
  dataIn, validIn, 
  wrMask, wrValue,
  wrConfig, wrEdge,
  config_data,
  arm, demux_mode, 

  capture, run);


input clock, reset;
input validIn;
input [31:0] dataIn;
input [3:0] wrMask;
input [3:0] wrValue;
input [3:0] wrConfig;
input [3:0] wrEdge;
input [31:0] config_data;
input arm;
input demux_mode;
output capture;
output run;

reg capture, next_capture;
reg [1:0] levelReg, next_levelReg;


wire [3:0] stageRun;
wire run = |stageRun;





wire [3:0] stageMatch;
stage stage0 (
  .clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn), 
  .wrMask(wrMask[0]), .wrValue(wrValue[0]), .wrEdge(wrEdge[0]), 
  .wrConfig(wrConfig[0]), .config_data(config_data),
  .arm(arm), .level(levelReg), .demux_mode(demux_mode),
  .run(stageRun[0]), .match(stageMatch[0]));

stage stage1 (
  .clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn), 
  .wrMask(wrMask[1]), .wrValue(wrValue[1]), .wrEdge(wrEdge[1]), 
  .wrConfig(wrConfig[1]), .config_data(config_data),
  .arm(arm), .level(levelReg), .demux_mode(demux_mode),
  .run(stageRun[1]), .match(stageMatch[1]));

stage stage2 (
  .clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn), 
  .wrMask(wrMask[2]), .wrValue(wrValue[2]), .wrEdge(wrEdge[2]), 
  .wrConfig(wrConfig[2]), .config_data(config_data),
  .arm(arm), .level(levelReg), .demux_mode(demux_mode),
  .run(stageRun[2]), .match(stageMatch[2]));

stage stage3 (
  .clock(clock), .reset(reset), .dataIn(dataIn), .validIn(validIn), 
  .wrMask(wrMask[3]), .wrValue(wrValue[3]), .wrEdge(wrEdge[3]), 
  .wrConfig(wrConfig[3]), .config_data(config_data),
  .arm(arm), .level(levelReg), .demux_mode(demux_mode),
  .run(stageRun[3]), .match(stageMatch[3]));





initial levelReg = 2'b00;
always @(posedge clock or posedge reset) 
begin : P2
  if (reset) 
    begin
      capture = 1'b0;
      levelReg = 2'b00;
    end
  else 
    begin
      capture = next_capture;
      levelReg = next_levelReg;
    end
end

always @*
begin
  #1;
  next_capture = arm | capture;
  next_levelReg = levelReg;
  if (|stageMatch) next_levelReg = levelReg + 1;
end
endmodule