data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/oq_regs_eval_empty.v
 line:76: before: "integer"
data/verilator_xmls/4bde67d5-5aac-4802-9a18-2fe6abd531fe.xml
function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction
function integer log2;

      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction