data/full_repos/permissive/130536678/Single-Cycle/ARM_CPU.v
 line:98: before: "INSTRUCTION"
1: b"%Error: data/full_repos/permissive/130536678/Single-Cycle/ARM_CPU.v:506: syntax error, unexpected $end, expecting ';'\n    Data[31] = 64   h00000000;\n                 ^\n%Error: Cannot continue\n"
module ALU_Control
(
  input [1:0] ALU_Op,
  input [10:0] ALU_INSTRUCTION,
  output reg [3:0] ALU_Out
);

  always @(ALU_Op or ALU_INSTRUCTION) begin

    case (ALU_Op)
      2'b00 : ALU_Out = 4'b0010;
      2'b01 : ALU_Out = 4'b0111;
      2'b10 : begin

        case (ALU_INSTRUCTION)
          11'b10001011000 : ALU_Out = 4'b0010;
          11'b11001011000 : ALU_Out = 4'b0110;
          11'b10001010000 : ALU_Out = 4'b0000;
          11'b10101010000 : ALU_Out = 4'b0001;
        endcase
      end
    endcase
  end
endmodule
module ALU_Control
(
  input [1:0] ALU_Op,
  input [10:0] ALU_INSTRUCTION,
  output reg [3:0] ALU_Out
);


  always @(ALU_Op or ALU_INSTRUCTION) begin

    case (ALU_Op)
      2'b00 : ALU_Out = 4'b0010;
      2'b01 : ALU_Out = 4'b0111;
      2'b10 : begin

        case (ALU_INSTRUCTION)
          11'b10001011000 : ALU_Out = 4'b0010;
          11'b11001011000 : ALU_Out = 4'b0110;
          11'b10001010000 : ALU_Out = 4'b0000;
          11'b10101010000 : ALU_Out = 4'b0001;
        endcase
      end
    endcase
  end
endmodule