data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C/salsa_piped.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C/salsa_piped.v:169: Cannot find include file: sgen.inc\n`include "sgen.inc"   // .inc so it does not accidentally get compiled separately as .v \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C,data/full_repos/permissive/11584509/sgen.inc\n             data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C,data/full_repos/permissive/11584509/sgen.inc.v\n             data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C,data/full_repos/permissive/11584509/sgen.inc.sv\n             sgen.inc\n             sgen.inc.v\n             sgen.inc.sv\n             obj_dir/sgen.inc\n             obj_dir/sgen.inc.v\n             obj_dir/sgen.inc.sv\n%Error: Exiting due to 1 error(s)\n'
module salsa (clk, feedback, B, Bx, Bo, X0out, X1out, Xaddr);



input clk;
input feedback;
input [511:0]B;
input [511:0]Bx;
output [511:0]Bo;
output [511:0]X0out;
output [511:0]X1out;
output [9:0]Xaddr;

wire [511:0]xx;
wire [511:0]xxd9;

wire [511:0]xr;
reg [511:0]xrd;
reg [511:0]xrd2;

wire [9:0]addr;
reg [9:0]xxd7_addr;



reg [511:0]x0d1;
reg [511:0]x0d2;
reg [511:0]x0d3;
reg [511:0]x0d4;
reg [511:0]x0d5;
reg [511:0]x0d6;
reg [511:0]x0d7;
reg [511:0]x0d8;
reg [511:0]x0d9;

reg [511:0]x1d1;
reg [511:0]x1d2;
reg [511:0]x1d3;
reg [511:0]x1d4;
reg [511:0]x1d5;
reg [511:0]x1d6;
reg [511:0]x1d7;
reg [511:0]x1d8;
reg [511:0]x1d9;

assign X0out = x0d9;
assign X1out = x1d9;

salsa_core salsa1 (clk, feedback ? xrd2 : xx, xr, addr);

always @ (posedge clk)
begin
	xrd <= xr;
	xrd2 <= xrd;

	x0d1 <= B;
	x0d2 <= x0d1;
	x0d3 <= x0d2;
	x0d4 <= x0d3;
	x0d5 <= x0d4;
	x0d6 <= x0d5;
	x0d7 <= x0d6;
	x0d8 <= x0d7;
	x0d9 <= x0d8;
	
	x1d1 <= Bx;
	x1d2 <= x1d1;
	x1d3 <= x1d2;
	x1d4 <= x1d3;
	x1d5 <= x1d4;
	x1d6 <= x1d5;
	x1d7 <= x1d6;
	x1d8 <= x1d7;
	x1d9 <= x1d8;
	
	xxd7_addr <= x0d6[9:0] ^ x1d6[9:0];
end
	
genvar i;
generate
	for (i = 0; i < 16; i = i + 1) begin : XX

		assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];
		assign xxd9[`IDX(i)] = x0d9[`IDX(i)] ^ x1d9[`IDX(i)];

		assign Bo[`IDX(i)] = xxd9[`IDX(i)] + xrd[`IDX(i)];
	end
endgenerate

assign Xaddr = xxd7_addr + addr;

endmodule
module salsa (clk, feedback, B, Bx, Bo, X0out, X1out, Xaddr);




input clk;
input feedback;
input [511:0]B;
input [511:0]Bx;
output [511:0]Bo;
output [511:0]X0out;
output [511:0]X1out;
output [9:0]Xaddr;

wire [511:0]xx;
wire [511:0]xxd9;

wire [511:0]xr;
reg [511:0]xrd;
reg [511:0]xrd2;

wire [9:0]addr;
reg [9:0]xxd7_addr;



reg [511:0]x0d1;
reg [511:0]x0d2;
reg [511:0]x0d3;
reg [511:0]x0d4;
reg [511:0]x0d5;
reg [511:0]x0d6;
reg [511:0]x0d7;
reg [511:0]x0d8;
reg [511:0]x0d9;

reg [511:0]x1d1;
reg [511:0]x1d2;
reg [511:0]x1d3;
reg [511:0]x1d4;
reg [511:0]x1d5;
reg [511:0]x1d6;
reg [511:0]x1d7;
reg [511:0]x1d8;
reg [511:0]x1d9;

assign X0out = x0d9;
assign X1out = x1d9;

salsa_core salsa1 (clk, feedback ? xrd2 : xx, xr, addr);

always @ (posedge clk)
begin
	xrd <= xr;
	xrd2 <= xrd;

	x0d1 <= B;
	x0d2 <= x0d1;
	x0d3 <= x0d2;
	x0d4 <= x0d3;
	x0d5 <= x0d4;
	x0d6 <= x0d5;
	x0d7 <= x0d6;
	x0d8 <= x0d7;
	x0d9 <= x0d8;
	
	x1d1 <= Bx;
	x1d2 <= x1d1;
	x1d3 <= x1d2;
	x1d4 <= x1d3;
	x1d5 <= x1d4;
	x1d6 <= x1d5;
	x1d7 <= x1d6;
	x1d8 <= x1d7;
	x1d9 <= x1d8;
	
	xxd7_addr <= x0d6[9:0] ^ x1d6[9:0];
end
	
genvar i;
generate
	for (i = 0; i < 16; i = i + 1) begin : XX

		assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];
		assign xxd9[`IDX(i)] = x0d9[`IDX(i)] ^ x1d9[`IDX(i)];

		assign Bo[`IDX(i)] = xxd9[`IDX(i)] + xrd[`IDX(i)];
	end
endgenerate

assign Xaddr = xxd7_addr + addr;

endmodule