data/full_repos/permissive/174642777/Experiments/Lab X7/1. TC_Parade (ver2)/TC_Parade.v
1: b'%Error: Cannot find file containing module: X7/1.\n        ... Looked in:\n             data/full_repos/permissive/174642777/Experiments/Lab/X7/1.\n             data/full_repos/permissive/174642777/Experiments/Lab/X7/1..v\n             data/full_repos/permissive/174642777/Experiments/Lab/X7/1..sv\n             X7/1.\n             X7/1..v\n             X7/1..sv\n             obj_dir/X7/1.\n             obj_dir/X7/1..v\n             obj_dir/X7/1..sv\n%Error: Cannot find file containing module: TC_Parade\n%Error: Cannot find file containing module: (ver2),data/full_repos/permissive/174642777\n%Error: Cannot find file containing module: data/full_repos/permissive/174642777/Experiments/Lab\n%Error: Cannot find file containing module: (ver2)/TC_Parade.v\n%Error: Exiting due to 5 error(s)\n'
module TC_Parade(
  input wire CLK,
  input wire RESET,
  input wire P, R,
  input wire T_A, T_B,
  output wire[2:0] L_A,
  output wire[2:0] L_B
);


  reg mode;
  reg[1:0] state;
  

  initial begin

    mode = 1'b0;
    

    state = 2'b00;
  end
  

  assign L_A[2] = (state == 2'b00);
  assign L_A[1] = (state == 2'b01);
  assign L_A[0] = (state[1] == 1'b1);
  assign L_B[2] = (state == 2'b10);
  assign L_B[1] = (state == 2'b11);
  assign L_B[0] = (state[1] == 1'b0);
  

  always@(posedge CLK) begin

    if(state[1] & !state[0] & ((P&!mode)|(R&mode))) mode = !mode;
    

    if( !(( !state[1]&!state[0]&T_A ) | ( state[1]&!state[0]&(mode|T_B) )) ) state = state + 2'b01;
  end

endmodule
module TC_Parade(
  input wire CLK,
  input wire RESET,
  input wire P, R,
  input wire T_A, T_B,
  output wire[2:0] L_A,
  output wire[2:0] L_B
);



  reg mode;
  reg[1:0] state;
  

  initial begin

    mode = 1'b0;
    

    state = 2'b00;
  end
  

  assign L_A[2] = (state == 2'b00);
  assign L_A[1] = (state == 2'b01);
  assign L_A[0] = (state[1] == 1'b1);
  assign L_B[2] = (state == 2'b10);
  assign L_B[1] = (state == 2'b11);
  assign L_B[0] = (state[1] == 1'b0);
  

  always@(posedge CLK) begin

    if(state[1] & !state[0] & ((P&!mode)|(R&mode))) mode = !mode;
    

    if( !(( !state[1]&!state[0]&T_A ) | ( state[1]&!state[0]&(mode|T_B) )) ) state = state + 2'b01;
  end

endmodule