data/full_repos/permissive/135838100/zpdaxrom/soc/pmi_def.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/135838100/zpdaxrom/soc/pmi_def.v:48: Multiple top level modules\n                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                 : ... Top module \'pmi_distributed_dpram\'\nmodule pmi_distributed_dpram \n       ^~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'pmi_addsub\'\nmodule pmi_addsub #(parameter pmi_data_width = 8,\n       ^~~~~~~~~~\n                                                                                 : ... Top module \'pmi_ram_dp\'\nmodule pmi_ram_dp\n       ^~~~~~~~~~\n                                                                                 : ... Top module \'pmi_ram_dp_true\'\nmodule pmi_ram_dp_true\n       ^~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'pmi_ram_dq\'\nmodule pmi_ram_dq\n       ^~~~~~~~~~\n                                                                                 : ... Top module \'pmi_fifo_dc\'\nmodule pmi_fifo_dc #(\n       ^~~~~~~~~~~\n                                                                                 : ... Top module \'pmi_fifo\'\nmodule pmi_fifo #(\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module pmi_ram_dp
  #(parameter pmi_wr_addr_depth = 512,
    parameter pmi_wr_addr_width = 9,
    parameter pmi_wr_data_width = 18,
    parameter pmi_rd_addr_depth = 512,
    parameter pmi_rd_addr_width = 9,
    parameter pmi_rd_data_width = 18,
    parameter pmi_regmode = "reg",
    parameter pmi_gsr = "disable",
    parameter pmi_resetmode = "sync",
    parameter pmi_optimization = "speed",
    parameter pmi_init_file = "none",
    parameter pmi_init_file_format = "binary",
    parameter pmi_family = "EC",
    parameter module_type = "pmi_ram_dp")
    
    (input [(pmi_wr_data_width-1):0] Data,
     input [(pmi_wr_addr_width-1):0] WrAddress,
     input [(pmi_rd_addr_width-1):0] RdAddress,
     input  WrClock,
     input  RdClock,
     input  WrClockEn,
     input  RdClockEn,
     input  WE,
     input  Reset,
     output [(pmi_rd_data_width-1):0]  Q);

endmodule
module pmi_ram_dp
  #(parameter pmi_wr_addr_depth = 512,
    parameter pmi_wr_addr_width = 9,
    parameter pmi_wr_data_width = 18,
    parameter pmi_rd_addr_depth = 512,
    parameter pmi_rd_addr_width = 9,
    parameter pmi_rd_data_width = 18,
    parameter pmi_regmode = "reg",
    parameter pmi_gsr = "disable",
    parameter pmi_resetmode = "sync",
    parameter pmi_optimization = "speed",
    parameter pmi_init_file = "none",
    parameter pmi_init_file_format = "binary",
    parameter pmi_family = "EC",
    parameter module_type = "pmi_ram_dp")
    
    (input [(pmi_wr_data_width-1):0] Data,
     input [(pmi_wr_addr_width-1):0] WrAddress,
     input [(pmi_rd_addr_width-1):0] RdAddress,
     input  WrClock,
     input  RdClock,
     input  WrClockEn,
     input  RdClockEn,
     input  WE,
     input  Reset,
     output [(pmi_rd_data_width-1):0]  Q);


endmodule