data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_datapath.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_datapath.v:20: Unsupported: Ignoring delay on this delayed statement.\n     #1\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_datapath.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #50000  ;\n    ^\n%Error: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_datapath.v:26: Cannot find file containing module: \'datapath\'\ndatapath DATAPATH( clk,sw,seg,an );\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1,data/full_repos/permissive/173691730/datapath\n             data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1,data/full_repos/permissive/173691730/datapath.v\n             data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1,data/full_repos/permissive/173691730/datapath.sv\n             datapath\n             datapath.v\n             datapath.sv\n             obj_dir/datapath\n             obj_dir/datapath.v\n             obj_dir/datapath.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_datapath;
 reg clk;
 reg [15:0]sw;

wire [7:0]seg;
wire [7:0]an; 






initial begin
     clk = 0;
     sw = 0;
     forever begin
     #1
     clk = ~clk;
     end
end


datapath DATAPATH( clk,sw,seg,an );

initial begin

    #50000  ;
    end
    
    
    
    

endmodule
module sim_datapath;

 reg clk;
 reg [15:0]sw;

wire [7:0]seg;
wire [7:0]an; 






initial begin
     clk = 0;
     sw = 0;
     forever begin
     #1
     clk = ~clk;
     end
end


datapath DATAPATH( clk,sw,seg,an );

initial begin

    #50000  ;
    end
    
    
    
    

endmodule