data/full_repos/permissive/177039499/pipeline-regs/IF-ID.v
data/verilator_xmls/d7a2dac1-628f-4c1a-8e26-edc21d997290.xml
module rIFID(
    input  wire        clk,
    input  wire        reset,
    input  wire        flush,
    input  wire        freeze,
    
    input  wire [31:0] PCIn,
    input  wire [31:0] instIn,
    
    output reg  [31:0] PC,
    output reg  [31:0] inst
);

    always @(posedge clk) begin
        if (reset) begin
            { PC, inst } <= 0;
        end else if (~freeze) begin
            if (flush) begin
                PC      <= 0;
                inst    <= 0;
            end else begin
                PC      <= PCIn;
                inst    <= instIn;
            end
        end
    end

endmodule
module rIFID(
    input  wire        clk,
    input  wire        reset,
    input  wire        flush,
    input  wire        freeze,
    
    input  wire [31:0] PCIn,
    input  wire [31:0] instIn,
    
    output reg  [31:0] PC,
    output reg  [31:0] inst
);


    always @(posedge clk) begin
        if (reset) begin
            { PC, inst } <= 0;
        end else if (~freeze) begin
            if (flush) begin
                PC      <= 0;
                inst    <= 0;
            end else begin
                PC      <= PCIn;
                inst    <= instIn;
            end
        end
    end

endmodule