data/full_repos/permissive/143278/ivltests/sv_interface.v
 line:9: before: "="
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sv_interface.v:16: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/sv_interface.v:35: Unsupported: wait statements\n      wait (cnt == 3*16);\n      ^~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ();


   bit err = 0;

   logic   clk = 1'b1;
   logic   rst = 1'b1;
   integer rst_cnt = 0;


   always #5 clk = ~clk;


   always @ (posedge clk)
   begin
      rst_cnt <= rst_cnt + 1;
      rst     <= rst_cnt <= 3;
   end


   int cnt;
   int cnt_src;
   int cnt_drn;


   assign cnt = cnt_src + cnt_drn + inf.cnt;


   initial begin
      wait (cnt == 3*16);
      if (!err) $display("PASSED");
      $finish;
   end


   handshake inf (
      .clk (clk),
      .rst (rst)
   );


   source #(
      .RW  (8),
      .RP  (8'b11100001)
   ) source (
      .clk  (clk),
      .rst  (rst),
      .inf  (inf),
      .cnt  (cnt_src)
   );


   drain #(
      .RW  (8),
      .RP  (8'b11010100)
   ) drain (
      .clk  (clk),
      .rst  (rst),
      .inf  (inf),
      .cnt  (cnt_drn)
   );

endmodule
module test ();



   bit err = 0;

   logic   clk = 1'b1;
   logic   rst = 1'b1;
   integer rst_cnt = 0;


   always #5 clk = ~clk;


   always @ (posedge clk)
   begin
      rst_cnt <= rst_cnt + 1;
      rst     <= rst_cnt <= 3;
   end


   int cnt;
   int cnt_src;
   int cnt_drn;


   assign cnt = cnt_src + cnt_drn + inf.cnt;


   initial begin
      wait (cnt == 3*16);
      if (!err) $display("PASSED");
      $finish;
   end


   handshake inf (
      .clk (clk),
      .rst (rst)
   );


   source #(
      .RW  (8),
      .RP  (8'b11100001)
   ) source (
      .clk  (clk),
      .rst  (rst),
      .inf  (inf),
      .cnt  (cnt_src)
   );


   drain #(
      .RW  (8),
      .RP  (8'b11010100)
   ) drain (
      .clk  (clk),
      .rst  (rst),
      .inf  (inf),
      .cnt  (cnt_drn)
   );

endmodule