data/full_repos/permissive/163728837/src/mmap_tb.v
 line:64: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/163728837/src/mmap_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    forever #10 clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:64: syntax error, unexpected \'@\'\n        repeat(6) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:66: syntax error, unexpected \'@\'\n        repeat(2) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:70: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:73: syntax error, unexpected \'@\'\n  repeat(2) @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:76: syntax error, unexpected \'@\'\n  repeat(4) @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:79: syntax error, unexpected \'@\'\n  repeat(4) @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:83: syntax error, unexpected \'@\'\n        repeat(8) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:87: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:90: syntax error, unexpected \'@\'\n        repeat(2) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:93: syntax error, unexpected \'@\'\n        repeat(4) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:98: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:105: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/163728837/src/mmap_tb.v:108: syntax error, unexpected \'@\'\n        repeat(25) @(posedge clk)\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/163728837/src/mmap_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n        #500000000\n        ^\n%Error: Exiting due to 13 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mmap_interface_tb(
    );

    reg clk;
    reg rst;

  wire [7:0] tx_data;
  wire new_tx_data;
  reg tx_busy;
  reg [7:0] rx_data;
  reg new_rx_data;

wire m_new_cmd;
wire m_write;
wire [5:0] m_cmd;
wire [31:0] m_address;
reg [31:0] s_data;
reg s_drdy;

    mmap_protocol DUT (
        .clk(clk),
        .rst(rst),
        .tx_data(tx_data),
        .new_tx_data(new_tx_data),
        .tx_busy(tx_busy),
        .rx_data(rx_data),
        .new_rx_data(new_rx_data),
         .m_new_cmd(m_new_cmd),
			.m_cmd(m_cmd),
         .m_write(m_write),
         .m_address(m_address),
         .s_data(s_data),
         .s_drdy(s_drdy)
    );


	 initial begin
	     clk = 0;
		  forever #10 clk = ~clk;
	 end

    initial begin
        rst = 1'b1;
        repeat(6) @(posedge clk);
        rst = 1'b0;
   	    repeat(2) @(posedge clk);

        new_rx_data = 1'b1;
        rx_data = 8'b11000000;
        @(posedge clk);

		rx_data = 8'd0;
		repeat(2) @(posedge clk);

        rx_data = 8'b00000001;
		repeat(4) @(posedge clk);

		rx_data = 8'b01111111;
		repeat(4) @(posedge clk);

		new_rx_data = 1'b0;
		rx_data = 8'd0;
        repeat(8) @(posedge clk);

        new_rx_data = 1'b1;
        rx_data = 8'b00000001;
        @(posedge clk);

        rx_data = 8'b00000000;
        repeat(2) @(posedge clk);

        rx_data = 8'b00010000;
        repeat(4) @(posedge clk);



        new_rx_data = 1'b0;
        @(posedge clk);
        @(posedge clk);


        s_data = {16{2'b10}};
        s_drdy = 1'b1;
        tx_busy = 1'b0;
        @(posedge clk);
        s_drdy = 1'b0;

        repeat(25) @(posedge clk)
        #5000
        $finish;
    end

    initial begin
        #500000000
        $finish;
    end
endmodule
module mmap_interface_tb(
    );


    reg clk;
    reg rst;

  wire [7:0] tx_data;
  wire new_tx_data;
  reg tx_busy;
  reg [7:0] rx_data;
  reg new_rx_data;

wire m_new_cmd;
wire m_write;
wire [5:0] m_cmd;
wire [31:0] m_address;
reg [31:0] s_data;
reg s_drdy;

    mmap_protocol DUT (
        .clk(clk),
        .rst(rst),
        .tx_data(tx_data),
        .new_tx_data(new_tx_data),
        .tx_busy(tx_busy),
        .rx_data(rx_data),
        .new_rx_data(new_rx_data),
         .m_new_cmd(m_new_cmd),
			.m_cmd(m_cmd),
         .m_write(m_write),
         .m_address(m_address),
         .s_data(s_data),
         .s_drdy(s_drdy)
    );


	 initial begin
	     clk = 0;
		  forever #10 clk = ~clk;
	 end

    initial begin
        rst = 1'b1;
        repeat(6) @(posedge clk);
        rst = 1'b0;
   	    repeat(2) @(posedge clk);

        new_rx_data = 1'b1;
        rx_data = 8'b11000000;
        @(posedge clk);

		rx_data = 8'd0;
		repeat(2) @(posedge clk);

        rx_data = 8'b00000001;
		repeat(4) @(posedge clk);

		rx_data = 8'b01111111;
		repeat(4) @(posedge clk);

		new_rx_data = 1'b0;
		rx_data = 8'd0;
        repeat(8) @(posedge clk);

        new_rx_data = 1'b1;
        rx_data = 8'b00000001;
        @(posedge clk);

        rx_data = 8'b00000000;
        repeat(2) @(posedge clk);

        rx_data = 8'b00010000;
        repeat(4) @(posedge clk);



        new_rx_data = 1'b0;
        @(posedge clk);
        @(posedge clk);


        s_data = {16{2'b10}};
        s_drdy = 1'b1;
        tx_busy = 1'b0;
        @(posedge clk);
        s_drdy = 1'b0;

        repeat(25) @(posedge clk)
        #5000
        $finish;
    end

    initial begin
        #500000000
        $finish;
    end
endmodule