data/full_repos/permissive/129918634/shift_mul.v
1: b'%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:77: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'x1\' generates 17 bits.\n                                                                   : ... In instance shift_mul\n   add_10 <= x3 + x1;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:78: Operator ADD expects 21 bits on the LHS, but LHS\'s VARREF \'x1\' generates 17 bits.\n                                                                   : ... In instance shift_mul\n   add_18 <= x1 + x4;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:79: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'x3\' generates 19 bits.\n                                                                   : ... In instance shift_mul\n   add_24 <= x4 + x3;        \n                ^\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:80: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'x2\' generates 18 bits.\n                                                                   : ... In instance shift_mul\n   add_36 <= x5 + x2;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:81: Operator ADD expects 23 bits on the RHS, but RHS\'s VARREF \'x0\' generates 16 bits.\n                                                                   : ... In instance shift_mul\n   add_65 <= x6 + x0;    \n                ^\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:87: Operator ADD expects 23 bits on the RHS, but RHS\'s VARREF \'add_10\' generates 20 bits.\n                                                                   : ... In instance shift_mul\nassign add_75 = add_65 + add_10;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:88: Operator ADD expects 23 bits on the RHS, but RHS\'s VARREF \'add_18\' generates 21 bits.\n                                                                   : ... In instance shift_mul\nassign add_83 = add_65 + add_18;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:89: Operator ADD expects 23 bits on the RHS, but RHS\'s VARREF \'add_24\' generates 21 bits.\n                                                                   : ... In instance shift_mul\nassign add_89 = add_65 + add_24;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:110: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'x6_d\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y0 <= x6_d;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:111: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'x6_d\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y1 <= x6_d;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:118: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_36\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y1 <= add_36;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:124: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'x6_d\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y0 <= x6_d;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:125: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'x6_d\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y1 <= x6_d;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:131: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_36\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y0 <= add_36;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:142: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'x6_d\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y0 <= x6_d;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:143: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'x6_d\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y1 <= x6_d;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:144: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'x6_d\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y2 <= x6_d;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:145: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'x6_d\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y3 <= x6_d;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:151: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_50\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y2 <= add_50;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:152: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_18\' generates 21 bits.\n                                                                    : ... In instance shift_mul\n    y3 <= add_18;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:157: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_36\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y1 <= add_36;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:158: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_36\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y2 <= add_36;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:164: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_18\' generates 21 bits.\n                                                                    : ... In instance shift_mul\n    y1 <= add_18;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:166: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_50\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y3 <= add_50;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:170: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'x6_d\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y0 <= x6_d;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:171: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'x6_d\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y1 <= x6_d;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:172: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'x6_d\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y2 <= x6_d;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:173: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'x6_d\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y3 <= x6_d;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:177: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_50\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y0 <= add_50;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:179: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_18\' generates 21 bits.\n                                                                    : ... In instance shift_mul\n    y2 <= add_18;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:184: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_36\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y0 <= add_36;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:187: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_36\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y3 <= add_36;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:191: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_18\' generates 21 bits.\n                                                                    : ... In instance shift_mul\n    y0 <= add_18;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/129918634/shift_mul.v:192: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_50\' generates 22 bits.\n                                                                    : ... In instance shift_mul\n    y1 <= add_50;\n       ^~\n%Error: Exiting due to 34 warning(s)\n'
module shift_mul
#(
	parameter WIDTH_X = 16,
	parameter WIDTH_Y = 23
)

(   input clk,
	input rst_n,
    input signed [WIDTH_X-1:0] x_in,
	input [2:0] mode,
	input [1:0]idct4_1,
	output reg [1:0]idct4_3,
	output reg signed [WIDTH_Y-1:0] y0,
	output reg signed [WIDTH_Y-1:0] y1,
	output reg signed [WIDTH_Y-1:0] y2,
	output reg signed [WIDTH_Y-1:0] y3
);

wire signed [WIDTH_X-1:0] x0;
wire signed [WIDTH_X:0] x1;
wire signed [WIDTH_X+1:0] x2;
wire signed [WIDTH_X+2:0] x3;
wire signed [WIDTH_X+3:0] x4; 
wire signed [WIDTH_X+4:0] x5; 
wire signed [WIDTH_X+5:0] x6;


reg signed [WIDTH_Y-4:0] add_10;
reg signed [WIDTH_Y-3:0] add_18;
reg signed [WIDTH_Y-3:0] add_24;
reg signed [WIDTH_Y-2:0] add_36;
reg signed [WIDTH_Y-1:0] add_65;
reg signed [WIDTH_X+4:0] x5_d;
reg signed [WIDTH_X+5:0] x6_d;

reg [1:0] idct4_2;


wire signed [WIDTH_Y-2:0] add_50;
wire signed [WIDTH_Y-1:0] add_75;
wire signed [WIDTH_Y-1:0] add_83;
wire signed [WIDTH_Y-1:0] add_89;


assign x0 = x_in;
assign x1 = {x_in,1'b0};
assign x2 = {x_in,2'b0};
assign x3 = {x1,2'b0};
assign x4 = {x_in,4'b0};
assign x5 = {x2,3'b0};    
assign x6 = {x_in,6'b0};



always @(posedge clk ) begin
  if (!rst_n) begin
    idct4_2 <= 2'b0;
  end else begin
    idct4_2 <= idct4_1;
  end
end


always @(posedge clk) begin
	if (!rst_n) begin
	  x5_d <= 21'b0;	
	  x6_d <= 22'b0;
	  add_10 <= 20'b0;
	  add_18 <= 21'b0;
	  add_24 <= 21'b0;        
	  add_36 <= 22'b0;
	  add_65 <= 23'b0;          
	end
	else begin
	  x5_d <= x5;		
	  x6_d <= x6;	  
	  add_10 <= x3 + x1;
	  add_18 <= x1 + x4;
	  add_24 <= x4 + x3;        
	  add_36 <= x5 + x2;
	  add_65 <= x6 + x0; 	  
	end
end


assign add_50 = x5_d + add_18;
assign add_75 = add_65 + add_10;
assign add_83 = add_65 + add_18;
assign add_89 = add_65 + add_24;

always @(posedge clk) begin
  if (!rst_n)
	idct4_3 <= 2'b0;
  else 
	idct4_3 <= idct4_2;
end

always @(posedge clk) begin
	if (!rst_n)
		begin
			y0 <= 23'b0;
			y1 <= 23'b0;
			y2 <= 23'b0;
			y3 <= 23'b0;
		end
    else if (idct4_2==2'b01) begin
		case (mode[1:0])
		2'b00: 
			begin
				y0 <= x6_d;
				y1 <= x6_d;
				y2 <= y2;
				y3 <= y3;
			end
		2'b01:
			begin
				y0 <= add_83;
				y1 <= add_36;
				y2 <= y2;
				y3 <= y3;				
			end
		2'b10:
			begin
				y0 <= x6_d;
				y1 <= x6_d;
				y2 <= y2;
				y3 <= y3;
			end	
		2'b11:
			begin
				y0 <= add_36;
				y1 <= add_83;
				y2 <= y2;
				y3 <= y3;
		    end
	   endcase
	 end
	else if (idct4_2==2'b10) begin
		  case(mode)
		3'b000:
			begin
				y0 <= x6_d;
				y1 <= x6_d;
				y2 <= x6_d;
				y3 <= x6_d;
			end
		3'b001:
			begin
				y0 <= add_89;
				y1 <= add_75;
				y2 <= add_50;
				y3 <= add_18;
			end	
		3'b010:
			begin
				y0 <= add_83;
				y1 <= add_36;
				y2 <= add_36;
				y3 <= add_83;
			end	
		3'b011:
			begin
				y0 <= add_75;
				y1 <= add_18;
				y2 <= add_89;
				y3 <= add_50;
			end	
		3'b100:
			begin
				y0 <= x6_d;
				y1 <= x6_d;
				y2 <= x6_d;
				y3 <= x6_d;
			end	
		3'b101:
			begin
				y0 <= add_50;
				y1 <= add_89;
				y2 <= add_18;
				y3 <= add_75;
			end	
		3'b110:
			begin
				y0 <= add_36;
				y1 <= add_83;
				y2 <= add_83;
				y3 <= add_36;
			end				
		3'b111:
			begin
				y0 <= add_18;
				y1 <= add_50;
				y2 <= add_75;
				y3 <= add_89;
			end
		endcase	  
	 end
	else
		begin
			y0 <= 23'b0;
			y1 <= 23'b0;
			y2 <= 23'b0;
			y3 <= 23'b0;
		end
 end
endmodule
module shift_mul
#(
	parameter WIDTH_X = 16,
	parameter WIDTH_Y = 23
)

(   input clk,
	input rst_n,
    input signed [WIDTH_X-1:0] x_in,
	input [2:0] mode,
	input [1:0]idct4_1,
	output reg [1:0]idct4_3,
	output reg signed [WIDTH_Y-1:0] y0,
	output reg signed [WIDTH_Y-1:0] y1,
	output reg signed [WIDTH_Y-1:0] y2,
	output reg signed [WIDTH_Y-1:0] y3
);


wire signed [WIDTH_X-1:0] x0;
wire signed [WIDTH_X:0] x1;
wire signed [WIDTH_X+1:0] x2;
wire signed [WIDTH_X+2:0] x3;
wire signed [WIDTH_X+3:0] x4; 
wire signed [WIDTH_X+4:0] x5; 
wire signed [WIDTH_X+5:0] x6;


reg signed [WIDTH_Y-4:0] add_10;
reg signed [WIDTH_Y-3:0] add_18;
reg signed [WIDTH_Y-3:0] add_24;
reg signed [WIDTH_Y-2:0] add_36;
reg signed [WIDTH_Y-1:0] add_65;
reg signed [WIDTH_X+4:0] x5_d;
reg signed [WIDTH_X+5:0] x6_d;

reg [1:0] idct4_2;


wire signed [WIDTH_Y-2:0] add_50;
wire signed [WIDTH_Y-1:0] add_75;
wire signed [WIDTH_Y-1:0] add_83;
wire signed [WIDTH_Y-1:0] add_89;


assign x0 = x_in;
assign x1 = {x_in,1'b0};
assign x2 = {x_in,2'b0};
assign x3 = {x1,2'b0};
assign x4 = {x_in,4'b0};
assign x5 = {x2,3'b0};    
assign x6 = {x_in,6'b0};



always @(posedge clk ) begin
  if (!rst_n) begin
    idct4_2 <= 2'b0;
  end else begin
    idct4_2 <= idct4_1;
  end
end


always @(posedge clk) begin
	if (!rst_n) begin
	  x5_d <= 21'b0;	
	  x6_d <= 22'b0;
	  add_10 <= 20'b0;
	  add_18 <= 21'b0;
	  add_24 <= 21'b0;        
	  add_36 <= 22'b0;
	  add_65 <= 23'b0;          
	end
	else begin
	  x5_d <= x5;		
	  x6_d <= x6;	  
	  add_10 <= x3 + x1;
	  add_18 <= x1 + x4;
	  add_24 <= x4 + x3;        
	  add_36 <= x5 + x2;
	  add_65 <= x6 + x0; 	  
	end
end


assign add_50 = x5_d + add_18;
assign add_75 = add_65 + add_10;
assign add_83 = add_65 + add_18;
assign add_89 = add_65 + add_24;

always @(posedge clk) begin
  if (!rst_n)
	idct4_3 <= 2'b0;
  else 
	idct4_3 <= idct4_2;
end

always @(posedge clk) begin
	if (!rst_n)
		begin
			y0 <= 23'b0;
			y1 <= 23'b0;
			y2 <= 23'b0;
			y3 <= 23'b0;
		end
    else if (idct4_2==2'b01) begin
		case (mode[1:0])
		2'b00: 
			begin
				y0 <= x6_d;
				y1 <= x6_d;
				y2 <= y2;
				y3 <= y3;
			end
		2'b01:
			begin
				y0 <= add_83;
				y1 <= add_36;
				y2 <= y2;
				y3 <= y3;				
			end
		2'b10:
			begin
				y0 <= x6_d;
				y1 <= x6_d;
				y2 <= y2;
				y3 <= y3;
			end	
		2'b11:
			begin
				y0 <= add_36;
				y1 <= add_83;
				y2 <= y2;
				y3 <= y3;
		    end
	   endcase
	 end
	else if (idct4_2==2'b10) begin
		  case(mode)
		3'b000:
			begin
				y0 <= x6_d;
				y1 <= x6_d;
				y2 <= x6_d;
				y3 <= x6_d;
			end
		3'b001:
			begin
				y0 <= add_89;
				y1 <= add_75;
				y2 <= add_50;
				y3 <= add_18;
			end	
		3'b010:
			begin
				y0 <= add_83;
				y1 <= add_36;
				y2 <= add_36;
				y3 <= add_83;
			end	
		3'b011:
			begin
				y0 <= add_75;
				y1 <= add_18;
				y2 <= add_89;
				y3 <= add_50;
			end	
		3'b100:
			begin
				y0 <= x6_d;
				y1 <= x6_d;
				y2 <= x6_d;
				y3 <= x6_d;
			end	
		3'b101:
			begin
				y0 <= add_50;
				y1 <= add_89;
				y2 <= add_18;
				y3 <= add_75;
			end	
		3'b110:
			begin
				y0 <= add_36;
				y1 <= add_83;
				y2 <= add_83;
				y3 <= add_36;
			end				
		3'b111:
			begin
				y0 <= add_18;
				y1 <= add_50;
				y2 <= add_75;
				y3 <= add_89;
			end
		endcase	  
	 end
	else
		begin
			y0 <= 23'b0;
			y1 <= 23'b0;
			y2 <= 23'b0;
			y3 <= 23'b0;
		end
 end
endmodule