data/full_repos/permissive/10490967/src/timer_tb.v
 line:110: before: ";"
1: b'%Error: data/full_repos/permissive/10490967/src/timer_tb.v:18: Cannot find include file: timer.v\n`include "timer.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10490967/src,data/full_repos/permissive/10490967/timer.v\n             data/full_repos/permissive/10490967/src,data/full_repos/permissive/10490967/timer.v.v\n             data/full_repos/permissive/10490967/src,data/full_repos/permissive/10490967/timer.v.sv\n             timer.v\n             timer.v.v\n             timer.v.sv\n             obj_dir/timer.v\n             obj_dir/timer.v.v\n             obj_dir/timer.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/10490967/src/timer_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:32: Unsupported: event data types\n    event end_trigger;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/10490967/src/timer_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    initial #1 display_header();\n            ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:106: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:136: syntax error, unexpected \'@\'\n        repeat(10) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:138: syntax error, unexpected \'@\'\n        repeat(10) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:141: syntax error, unexpected \'@\'\n        repeat(20) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:149: syntax error, unexpected \'@\'\n        repeat(5) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:151: syntax error, unexpected \'@\'\n        repeat(15) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:153: syntax error, unexpected \'@\'\n        repeat(15) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:155: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:162: syntax error, unexpected ->\n        -> end_trigger;\n        ^~\n%Error: Exiting due to 11 error(s), 2 warning(s)\n'
module timer_tb;




    reg clk;
    always #1 clk = !clk;



    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    parameter TIMEOUT = 10;

`ifdef TB_VERBOSE
    initial $display("Testbench for unit 'timer'");
`endif


    reg     rst;

    reg     up_req;
    wire    up_grant;
    wire    down_req;
    wire    down_grant;



    timer #(
        .TIMEOUT (TIMEOUT))
    uut (
        .clk       (clk),
        .rst       (rst),

        .up_req     (up_req),
        .up_grant   (up_grant),
        .up_ack     (),

        .down_req   (down_req),
        .down_grant (down_grant),
        .down_ack   ()
    );




    task display_signals;
        $display(
            "%d\t%d",
            $time, rst,

            "\t%b\t%b",
            up_req,
            down_req,

            "\t%b\t%b",
            up_grant,
            down_grant,
        );
    endtask

    task display_header;
        $display({
            "\t\ttime\trst",
            ""});
    endtask




    assign down_grant = down_req;


    initial begin

        clk = 0;
        rst = 0;

        up_req = 1'b0;



`ifdef TB_VERBOSE
    $display("RESET");
`endif

        repeat(10) @(posedge clk);
        rst <= 1'b1;
        repeat(10) @(posedge clk);
        rst <= 1'b0;

        repeat(20) @(posedge clk);


`ifdef TB_VERBOSE
    $display("TEST different ports request priority");
`endif

        up_req = 1'b1;
        repeat(5) @(posedge clk);
        up_req = 1'b0;
        repeat(15) @(posedge clk);
        up_req = 1'b1;
        repeat(15) @(posedge clk);
        up_req = 1'b0;
        @(posedge clk);


        @(posedge clk);
`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end


endmodule
module timer_tb;





    reg clk;
    always #1 clk = !clk;



    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    parameter TIMEOUT = 10;

`ifdef TB_VERBOSE
    initial $display("Testbench for unit 'timer'");
`endif


    reg     rst;

    reg     up_req;
    wire    up_grant;
    wire    down_req;
    wire    down_grant;



    timer #(
        .TIMEOUT (TIMEOUT))
    uut (
        .clk       (clk),
        .rst       (rst),

        .up_req     (up_req),
        .up_grant   (up_grant),
        .up_ack     (),

        .down_req   (down_req),
        .down_grant (down_grant),
        .down_ack   ()
    );




    task display_signals;
        $display(
            "%d\t%d",
            $time, rst,

            "\t%b\t%b",
            up_req,
            down_req,

            "\t%b\t%b",
            up_grant,
            down_grant,
        );
    endtask

    task display_header;
        $display({
            "\t\ttime\trst",
            ""});
    endtask




    assign down_grant = down_req;


    initial begin

        clk = 0;
        rst = 0;

        up_req = 1'b0;



`ifdef TB_VERBOSE
    $display("RESET");
`endif

        repeat(10) @(posedge clk);
        rst <= 1'b1;
        repeat(10) @(posedge clk);
        rst <= 1'b0;

        repeat(20) @(posedge clk);


`ifdef TB_VERBOSE
    $display("TEST different ports request priority");
`endif

        up_req = 1'b1;
        repeat(5) @(posedge clk);
        up_req = 1'b0;
        repeat(15) @(posedge clk);
        up_req = 1'b1;
        repeat(15) @(posedge clk);
        up_req = 1'b0;
        @(posedge clk);


        @(posedge clk);
`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end


endmodule