data/full_repos/permissive/208519918/Cache Processor/cache_test.v
1: b'%Error: Cannot find file containing module: Processor,data/full_repos/permissive/208519918\n        ... Looked in:\n             data/full_repos/permissive/208519918/Cache/Processor,data/full_repos/permissive/208519918\n             data/full_repos/permissive/208519918/Cache/Processor,data/full_repos/permissive/208519918.v\n             data/full_repos/permissive/208519918/Cache/Processor,data/full_repos/permissive/208519918.sv\n             Processor,data/full_repos/permissive/208519918\n             Processor,data/full_repos/permissive/208519918.v\n             Processor,data/full_repos/permissive/208519918.sv\n             obj_dir/Processor,data/full_repos/permissive/208519918\n             obj_dir/Processor,data/full_repos/permissive/208519918.v\n             obj_dir/Processor,data/full_repos/permissive/208519918.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/208519918/Cache\n%Error: Cannot find file containing module: Processor/cache_test.v\n%Error: Exiting due to 3 error(s)\n'
module cache_test;

reg [23:0] address, data;
reg mode, clk;
wire [23:0] out;
wire status;
wire addBlock;

processor tb (
    .address(address),
    .data(data),
    .mode(mode),
    .clk(clk),
    .out(out),
    .status(status),
    .addBlock(addBlock)
);



integer fd;
integer temp;

integer idx = 0;
integer missCount = 0;
integer hitCount = 0;
reg [31:0] missRate;
real result;

reg [23:0] traceData[59999:0];
reg [23:0] parsedAddress;
reg [23:0] flippedAddress;
reg [7:0] byte1, byte2, byte3;
reg [23:0] dataMem = 0;


initial begin
    clk = 1'b1;


    fd = $fopen("TRACE1.DAT","rb");
    temp = $fread(traceData, fd);
    $fclose(fd);
    

    

    

    
end


always @(posedge clk) begin
    parsedAddress = traceData[idx];

    byte1 = parsedAddress[7:0];
    byte2 = parsedAddress[15:8];
    byte3 = parsedAddress[23:16];
    
    flippedAddress = {byte1,byte2,byte3};

    
    #50

    address = flippedAddress;
    data = idx;
    mode = 1'b1;
    
    #50

    address = flippedAddress;
    data = idx;
    mode = 1'b0;
    

    idx = idx + 1;
    
    if (idx == 57961) begin
        $display("TRACE FILE FINSHED PARSING");
        missRate = $itor(missCount) / $itor(idx);
        result = $itor(missCount) / $itor(idx);
        $display("misses = %d, miss rate = %f",missCount,result);
        $finish;
    end
    
    #50
    
    if (status == 0) begin
        missCount = missCount + 1;
    end
end

    


initial $monitor("address = %d data = %x mode = %d out = %x\n", address, data, mode, out);

always #25 clk = ~clk;

endmodule
module cache_test;


reg [23:0] address, data;
reg mode, clk;
wire [23:0] out;
wire status;
wire addBlock;

processor tb (
    .address(address),
    .data(data),
    .mode(mode),
    .clk(clk),
    .out(out),
    .status(status),
    .addBlock(addBlock)
);



integer fd;
integer temp;

integer idx = 0;
integer missCount = 0;
integer hitCount = 0;
reg [31:0] missRate;
real result;

reg [23:0] traceData[59999:0];
reg [23:0] parsedAddress;
reg [23:0] flippedAddress;
reg [7:0] byte1, byte2, byte3;
reg [23:0] dataMem = 0;


initial begin
    clk = 1'b1;


    fd = $fopen("TRACE1.DAT","rb");
    temp = $fread(traceData, fd);
    $fclose(fd);
    

    

    

    
end


always @(posedge clk) begin
    parsedAddress = traceData[idx];

    byte1 = parsedAddress[7:0];
    byte2 = parsedAddress[15:8];
    byte3 = parsedAddress[23:16];
    
    flippedAddress = {byte1,byte2,byte3};

    
    #50

    address = flippedAddress;
    data = idx;
    mode = 1'b1;
    
    #50

    address = flippedAddress;
    data = idx;
    mode = 1'b0;
    

    idx = idx + 1;
    
    if (idx == 57961) begin
        $display("TRACE FILE FINSHED PARSING");
        missRate = $itor(missCount) / $itor(idx);
        result = $itor(missCount) / $itor(idx);
        $display("misses = %d, miss rate = %f",missCount,result);
        $finish;
    end
    
    #50
    
    if (status == 0) begin
        missCount = missCount + 1;
    end
end

    


initial $monitor("address = %d data = %x mode = %d out = %x\n", address, data, mode, out);

always #25 clk = ~clk;

endmodule