data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v
1: b'%Error: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:1: Cannot find include file: urnaeletronica.v\n`include "urnaeletronica.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251,data/full_repos/permissive/161314640/urnaeletronica.v\n             data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251,data/full_repos/permissive/161314640/urnaeletronica.v.v\n             data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251,data/full_repos/permissive/161314640/urnaeletronica.v.sv\n             urnaeletronica.v\n             urnaeletronica.v.v\n             urnaeletronica.v.sv\n             obj_dir/urnaeletronica.v\n             obj_dir/urnaeletronica.v.v\n             obj_dir/urnaeletronica.v.sv\n%Error: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:16: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("urnaeletronica.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:17: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, testbench);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:19: Unsupported or unknown PLI call: $monitor\n  $monitor("- Votos para Isabella: %d\\n- Votos para Claudio: %d\\n- Votos para Filipe: %d\\n- Votos para Guilherme: %d\\n- Votos nulos:%d\\n", tisabella, tclaudio, tfilipe, tguilherme, tnulo);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; finish = 0; valid = 0;digit = 4\'b0011; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0100; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0111; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0100; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0011; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0100; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b1001; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0010; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0011; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0101; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0000; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0010; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0011; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0101; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0000; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b1001; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0011; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0101; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b0000; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; valid = 0; digit = 4\'b1111; valid = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; finish = 1; clock = 0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1 ;control = 3\'b001;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; control = 3\'b010;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; control = 3\'b011;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; control = 3\'b100;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; control = 3\'b101;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #1; clock = 1; control = 3\'b000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/testbench.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 4 error(s), 54 warning(s)\n'
module testbench();
reg clock,valid,finish;
reg [3:0]digit;
reg [2:0]control;
wire [7:0]tisabella;
wire [7:0]tclaudio;
wire [7:0]tfilipe;
wire [7:0]tguilherme;
wire [7:0]tnulo;
wire votestatus;

urnaeletronica instancial(.votestatus(votestatus), .control(control), .clock(clock), .valid(valid), .finish(finish), .digit(digit), .tisabella(tisabella), .tclaudio(tclaudio), .tfilipe(tfilipe), .tguilherme(tguilherme), .tnulo(tnulo));

initial begin
  $dumpfile("urnaeletronica.vcd");
  $dumpvars(0, testbench);
  $display("-----Urna Eletronica-----");
  $monitor("- Votos para Isabella: %d\n- Votos para Claudio: %d\n- Votos para Filipe: %d\n- Votos para Guilherme: %d\n- Votos nulos:%d\n", tisabella, tclaudio, tfilipe, tguilherme, tnulo);
end

initial begin


  #1; clock = 0;
  #1; clock = 1; finish = 0; valid = 0;digit = 4'b0011; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0100; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0111; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0100; valid = 1;


  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0011; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0100; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b1001; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0010; valid = 1;


  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0011; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0101; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0000; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0010; valid = 1;


  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0011; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0101; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0000; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b1001; valid = 1;


  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0011; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0101; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0000; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b1111; valid = 1;


  #1; clock = 0;
  #1; clock = 1; finish = 1; clock = 0;
  #1; clock = 1 ;control = 3'b001;
  #1; clock = 0;
  #1; clock = 1; control = 3'b010;
  #1; clock = 0;
  #1; clock = 1; control = 3'b011;
  #1; clock = 0;
  #1; clock = 1; control = 3'b100;
  #1; clock = 0;
  #1; clock = 1; control = 3'b101;
  #1; clock = 0;
  #1; clock = 1; control = 3'b000;
  #1;
  $finish;
end

endmodule
module testbench();

reg clock,valid,finish;
reg [3:0]digit;
reg [2:0]control;
wire [7:0]tisabella;
wire [7:0]tclaudio;
wire [7:0]tfilipe;
wire [7:0]tguilherme;
wire [7:0]tnulo;
wire votestatus;

urnaeletronica instancial(.votestatus(votestatus), .control(control), .clock(clock), .valid(valid), .finish(finish), .digit(digit), .tisabella(tisabella), .tclaudio(tclaudio), .tfilipe(tfilipe), .tguilherme(tguilherme), .tnulo(tnulo));

initial begin
  $dumpfile("urnaeletronica.vcd");
  $dumpvars(0, testbench);
  $display("-----Urna Eletronica-----");
  $monitor("- Votos para Isabella: %d\n- Votos para Claudio: %d\n- Votos para Filipe: %d\n- Votos para Guilherme: %d\n- Votos nulos:%d\n", tisabella, tclaudio, tfilipe, tguilherme, tnulo);
end

initial begin


  #1; clock = 0;
  #1; clock = 1; finish = 0; valid = 0;digit = 4'b0011; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0100; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0111; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0100; valid = 1;


  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0011; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0100; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b1001; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0010; valid = 1;


  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0011; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0101; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0000; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0010; valid = 1;


  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0011; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0101; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0000; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b1001; valid = 1;


  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0011; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0101; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b0000; valid = 1;
  #1; clock = 0;
  #1; clock = 1; valid = 0; digit = 4'b1111; valid = 1;


  #1; clock = 0;
  #1; clock = 1; finish = 1; clock = 0;
  #1; clock = 1 ;control = 3'b001;
  #1; clock = 0;
  #1; clock = 1; control = 3'b010;
  #1; clock = 0;
  #1; clock = 1; control = 3'b011;
  #1; clock = 0;
  #1; clock = 1; control = 3'b100;
  #1; clock = 0;
  #1; clock = 1; control = 3'b101;
  #1; clock = 0;
  #1; clock = 1; control = 3'b000;
  #1;
  $finish;
end

endmodule