data/full_repos/permissive/156129873/verilog/ex_mem.v
1: b'%Error: data/full_repos/permissive/156129873/verilog/ex_mem.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/156129873/verilog/ex_mem.v:33: Define or directive not defined: \'`RstEnable\'\n        if (rst == `RstEnable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex_mem.v:33: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (rst == `RstEnable) begin\n                             ^\n%Error: data/full_repos/permissive/156129873/verilog/ex_mem.v:35: Define or directive not defined: \'`ZERO\'\n                writeData_o <= `ZERO;\n                               ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex_mem.v:38: Define or directive not defined: \'`MEM_NOP_OP\'\n                memOp_o <= `MEM_NOP_OP;\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex_mem.v:38: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                memOp_o <= `MEM_NOP_OP;\n                                      ^\n%Error: data/full_repos/permissive/156129873/verilog/ex_mem.v:39: Define or directive not defined: \'`ZERO\'\n                memAddr_o <= `ZERO;\n                             ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex_mem.v:39: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                memAddr_o <= `ZERO;\n                                  ^\n%Error: data/full_repos/permissive/156129873/verilog/ex_mem.v:42: Define or directive not defined: \'`Disable\'\n                writeReg_o <= `Disable;\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex_mem.v:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                writeReg_o <= `Disable;\n                                      ^\n%Error: data/full_repos/permissive/156129873/verilog/ex_mem.v:43: Define or directive not defined: \'`ZERO\'\n                writeRegAddr_o <= `ZERO;\n                                  ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex_mem.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                writeRegAddr_o <= `ZERO;\n                                       ^\n%Error: Cannot continue\n'
module ex_mem(
    input wire clk,
    input wire rst,



    input wire[15:0] writeData_i,


    input wire[1:0] memOp_i,
    input wire[15:0] memAddr_i,


    input wire writeReg_i,
    input wire[3:0] writeRegAddr_i,



    output reg[15:0] writeData_o,


    output reg[1:0] memOp_o,
    output reg[15:0] memAddr_o,


    output reg writeReg_o,
    output reg[3:0] writeRegAddr_o
    );

    always @(posedge clk) begin
        if (rst == `RstEnable) begin

                writeData_o <= `ZERO;


                memOp_o <= `MEM_NOP_OP;
                memAddr_o <= `ZERO;


                writeReg_o <= `Disable;
                writeRegAddr_o <= `ZERO;
        end else begin

                writeData_o <= writeData_i;


                memOp_o <= memOp_i;
                memAddr_o <= memAddr_i;


                writeReg_o <= writeReg_i;
                writeRegAddr_o <= writeRegAddr_i;
        end
    end

endmodule
module ex_mem(
    input wire clk,
    input wire rst,



    input wire[15:0] writeData_i,


    input wire[1:0] memOp_i,
    input wire[15:0] memAddr_i,


    input wire writeReg_i,
    input wire[3:0] writeRegAddr_i,



    output reg[15:0] writeData_o,


    output reg[1:0] memOp_o,
    output reg[15:0] memAddr_o,


    output reg writeReg_o,
    output reg[3:0] writeRegAddr_o
    );


    always @(posedge clk) begin
        if (rst == `RstEnable) begin

                writeData_o <= `ZERO;


                memOp_o <= `MEM_NOP_OP;
                memAddr_o <= `ZERO;


                writeReg_o <= `Disable;
                writeRegAddr_o <= `ZERO;
        end else begin

                writeData_o <= writeData_i;


                memOp_o <= memOp_i;
                memAddr_o <= memAddr_i;


                writeReg_o <= writeReg_i;
                writeRegAddr_o <= writeRegAddr_i;
        end
    end

endmodule