data/full_repos/permissive/143278/ivltests/pr1866215b.v
 line:37: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1866215b.v:37: Unsupported: Ignoring delay on this delayed statement.\n   initial #1 $display("CH=%h, CL=%h, SH=%h, SL=%h", CH, CL, SH, SL);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1866215b.v:26: Input port connection \'CH\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'CH\' generates 6 bits.\n                                                                          : ... In instance A.B0\nC C0 (CH, CL, SH, SL);\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1866215b.v:26: Input port connection \'SH\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'SH\' generates 7 bits.\n                                                                          : ... In instance A.B0\nC C0 (CH, CL, SH, SL);\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1866215b.v:10: Input port connection \'CH\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'CH\' generates 16 bits.\n                                                                          : ... In instance A\nB B0 (CH, CL, SH, SL);\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1866215b.v:10: Input port connection \'SH\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'SH\' generates 16 bits.\n                                                                          : ... In instance A\nB B0 (CH, CL, SH, SL);\n              ^~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module A (CH, CL, SH, SL);

output	[31:0]	SL;
output	[31:0]	CL;
output	[47:32]	SH;
output	[47:32]	CH;

B B0	(CH, CL, SH, SL);

   assign	SH = 'hff;
   assign	SL = 32'haaaaaaaa;
   assign	CH = 'hff;
   assign	CL = 32'h55555555;

endmodule
module A (CH, CL, SH, SL);


output	[31:0]	SL;
output	[31:0]	CL;
output	[47:32]	SH;
output	[47:32]	CH;

B B0	(CH, CL, SH, SL);

   assign	SH = 'hff;
   assign	SL = 32'haaaaaaaa;
   assign	CH = 'hff;
   assign	CL = 32'h55555555;

endmodule