data/full_repos/permissive/176378198/src/sev_seg_out.v
1: b"%Error: data/full_repos/permissive/176378198/src/sev_seg_out.v:4: Expecting include filename. Found: TEXT\n`include `GRVM_PATH(io/seven_segment_displays/sev_seg_hex_multiplexed.v) \n                   ^\n%Error: data/full_repos/permissive/176378198/src/sev_seg_out.v:5: Expecting include filename. Found: TEXT\n`include `GRVM_PATH(interfacing/register.v) \n                   ^\n%Error: data/full_repos/permissive/176378198/src/sev_seg_out.v:6: Expecting include filename. Found: TEXT\n`include `GRVM_PATH(encoding/binary_to_bcd_8.v) \n                   ^\n%Error: data/full_repos/permissive/176378198/src/sev_seg_out.v:4: Define or directive not defined: '`GRVM_PATHio'\n `GRVM_PATHio/seven_segment_displays/sev_seg_hex_multiplexed.v)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/176378198/src/sev_seg_out.v:4: syntax error, unexpected '/'\n `GRVM_PATHio/seven_segment_displays/sev_seg_hex_multiplexed.v)\n             ^\n%Error: data/full_repos/permissive/176378198/src/sev_seg_out.v:5: Define or directive not defined: '`GRVM_PATHinterfacing'\n `GRVM_PATHinterfacing/register.v)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/176378198/src/sev_seg_out.v:6: Define or directive not defined: '`GRVM_PATHencoding'\n `GRVM_PATHencoding/binary_to_bcd_8.v)\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module sev_seg_out (
    inout [7 : 0] bus,
    input bus_clk,
    input sev_seg_clk,

    input OI,


    input twos_complement,

    input rst,

    output [7 : 0] segs,
    output [3 : 0] sel
    );

    wire [7 : 0] display_data_bin;
    register output_register [7 : 0] (
        .in(bus),
        .out(display_data_bin),

        .clk(bus_clk),
        .clr(rst),
        .load(OI)
    );

    wire [11 : 0] display_data_bcd;
    binary_to_bcd_8 binary_to_bcd_8_inst (
        .binary(display_data_bin),
        .bcd(display_data_bcd)
    );

    sev_seg_hex_multiplexed #(
        .ACTIVE_HIGH(0),
        .NUMBER_OF_SEGMENTS(4)
        ) sev_seg (
        .in({4'b0, display_data_bcd}),

        .clk(sev_seg_clk),
        .rst(1'b0),

        .segs(segs),
        .sel(sel)
    );

endmodule
module sev_seg_out (
    inout [7 : 0] bus,
    input bus_clk,
    input sev_seg_clk,

    input OI,


    input twos_complement,

    input rst,

    output [7 : 0] segs,
    output [3 : 0] sel
    );


    wire [7 : 0] display_data_bin;
    register output_register [7 : 0] (
        .in(bus),
        .out(display_data_bin),

        .clk(bus_clk),
        .clr(rst),
        .load(OI)
    );

    wire [11 : 0] display_data_bcd;
    binary_to_bcd_8 binary_to_bcd_8_inst (
        .binary(display_data_bin),
        .bcd(display_data_bcd)
    );

    sev_seg_hex_multiplexed #(
        .ACTIVE_HIGH(0),
        .NUMBER_OF_SEGMENTS(4)
        ) sev_seg (
        .in({4'b0, display_data_bcd}),

        .clk(sev_seg_clk),
        .rst(1'b0),

        .segs(segs),
        .sel(sel)
    );

endmodule