data/full_repos/permissive/143278/ivltests/sched2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sched2.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sched2.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #0 if (q !== 1) begin\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg a;
   reg b;
   wire q = a & b;

   initial begin
      a = 1;
      b = 0;
      #1;
      if (q !== 0) begin
	 $display("FAILED -- q did not start out right: %b", q);
	 $finish;
      end

      b = 1;
      if (q !== 0) begin



	 $display("FAILED -- q changed too soon? %b", q);
	 $finish;
      end

      if (b !== 1) begin
	 $display("FAILED -- b value did not stick: %b", b);
	 $finish;
      end



      #0 if (q !== 1) begin
	 $display("FAILED -- q did not change when it should: %b", q);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg a;
   reg b;
   wire q = a & b;

   initial begin
      a = 1;
      b = 0;
      #1;
      if (q !== 0) begin
	 $display("FAILED -- q did not start out right: %b", q);
	 $finish;
      end

      b = 1;
      if (q !== 0) begin



	 $display("FAILED -- q changed too soon? %b", q);
	 $finish;
      end

      if (b !== 1) begin
	 $display("FAILED -- b value did not stick: %b", b);
	 $finish;
      end



      #0 if (q !== 1) begin
	 $display("FAILED -- q did not change when it should: %b", q);
	 $finish;
      end

      $display("PASSED");
   end

endmodule