data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/sram_sim.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/sram_sim.v:17: Bit extraction of array[1048576:0] requires 21 bit index, not 20 bits.\n                                                                                              : ... In instance sram_sim\n   ram_dq[SRAM_ADDR][7:0] <= SRAM_DQ[7:0];\n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/sram_sim.v:19: Bit extraction of array[1048576:0] requires 21 bit index, not 20 bits.\n                                                                                              : ... In instance sram_sim\n   ram_dq[SRAM_ADDR][15:8] <= SRAM_DQ[15:8];\n         ^\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/02_testbench/sram_sim.v:22: Bit extraction of array[1048576:0] requires 21 bit index, not 20 bits.\n                                                                                              : ... In instance sram_sim\n assign  SRAM_DQ = (!SRAM_OE_N)? ram_dq[SRAM_ADDR] : 16\'HZZZZ;\n                                       ^\n%Error: Exiting due to 3 warning(s)\n'
module sram_sim
(

	input	[19:0]	SRAM_ADDR,
	inout   [15:0]  SRAM_DQ,

    input	        SRAM_CE_N,
    input           SRAM_LB_N, SRAM_UB_N,
    input           SRAM_WE_N, SRAM_OE_N
);

	reg		[15:0]	ram_dq	[0:1048576];

	always @(*)
	begin
		if(!SRAM_LB_N & !SRAM_WE_N)
			ram_dq[SRAM_ADDR][7:0] <= SRAM_DQ[7:0];
		if(!SRAM_UB_N & !SRAM_WE_N)
			ram_dq[SRAM_ADDR][15:8] <= SRAM_DQ[15:8];
	end

	assign		SRAM_DQ = (!SRAM_OE_N)? ram_dq[SRAM_ADDR] : 16'HZZZZ;
	
endmodule
module sram_sim
(

	input	[19:0]	SRAM_ADDR,
	inout   [15:0]  SRAM_DQ,

    input	        SRAM_CE_N,
    input           SRAM_LB_N, SRAM_UB_N,
    input           SRAM_WE_N, SRAM_OE_N
);


	reg		[15:0]	ram_dq	[0:1048576];

	always @(*)
	begin
		if(!SRAM_LB_N & !SRAM_WE_N)
			ram_dq[SRAM_ADDR][7:0] <= SRAM_DQ[7:0];
		if(!SRAM_UB_N & !SRAM_WE_N)
			ram_dq[SRAM_ADDR][15:8] <= SRAM_DQ[15:8];
	end

	assign		SRAM_DQ = (!SRAM_OE_N)? ram_dq[SRAM_ADDR] : 16'HZZZZ;
	
endmodule