data/full_repos/permissive/210737016/wam_hit.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/210737016/wam_hit.v:46: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'wam_tap\'\nmodule wam_tap (             \n       ^~~~~~~\n                                                                    : ... Top module \'wam_hit\'\nmodule wam_hit (             \n       ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module wam_tap (
    input wire clk_19,
    input wire [7:0] sw,
    output reg [7:0] tap
    );

    reg [7:0]  sw_pre;
    wire [7:0] sw_edg;
    reg [31:0] sw_cnt;
    integer i;

    always @(posedge clk_19)
        sw_pre <= sw;
    assign sw_edg = ((sw_pre) & (~sw)) | ((~sw_pre) & (sw));

    always @ (posedge clk_19) begin
        for (i=0; i<8; i=i+1) begin
            if (sw_cnt[4*i+:4] > 0) begin
                if (sw_cnt[4*i+:4] > 4'b0100) begin
                    sw_cnt[4*i+:4] <= 4'b0000;
                    tap[i] <= 1;
                end
                else begin
                    if (sw_edg[i]) begin
                        sw_cnt[4*i+:4] <= 0;
                    end
                    else begin
                        sw_cnt[4*i+:4] <= sw_cnt[4*i+:4] + 1;
                    end
                end
            end
            else begin
                tap[i] <= 0;
                if (sw_edg[i]) begin
                    sw_cnt[4*i+:4] <= 4'b0001;
                end
            end
        end
    end
endmodule
module wam_tap (
    input wire clk_19,
    input wire [7:0] sw,
    output reg [7:0] tap
    );


    reg [7:0]  sw_pre;
    wire [7:0] sw_edg;
    reg [31:0] sw_cnt;
    integer i;

    always @(posedge clk_19)
        sw_pre <= sw;
    assign sw_edg = ((sw_pre) & (~sw)) | ((~sw_pre) & (sw));

    always @ (posedge clk_19) begin
        for (i=0; i<8; i=i+1) begin
            if (sw_cnt[4*i+:4] > 0) begin
                if (sw_cnt[4*i+:4] > 4'b0100) begin
                    sw_cnt[4*i+:4] <= 4'b0000;
                    tap[i] <= 1;
                end
                else begin
                    if (sw_edg[i]) begin
                        sw_cnt[4*i+:4] <= 0;
                    end
                    else begin
                        sw_cnt[4*i+:4] <= sw_cnt[4*i+:4] + 1;
                    end
                end
            end
            else begin
                tap[i] <= 0;
                if (sw_edg[i]) begin
                    sw_cnt[4*i+:4] <= 4'b0001;
                end
            end
        end
    end
endmodule