data/full_repos/permissive/118800618/srl32.v
data/verilator_xmls/d3ba0a8e-9970-4c5d-9113-aa30536af0ee.xml
module srl32(input [31:0] A,
				 input [31:0] B,
				 output [31:0] res
				);
	
	assign res = A>>B[10:6];

endmodule
module srl32(input [31:0] A,
				 input [31:0] B,
				 output [31:0] res
				);

	
	assign res = A>>B[10:6];

endmodule