data/full_repos/permissive/174783592/Adder_PL/sum16bitPLTB.sv
 line:42: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/174783592/Adder_PL/sum16bitPLTB.sv:42: Unsupported: Ignoring delay on this delayed statement.\n  #30 $finish; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174783592/Adder_PL/sum16bitPLTB.sv:45: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/174783592/Adder_PL/sum16bitPLTB.sv:47: Unsupported: Ignoring delay on this delayed statement.\n    always #5 a<=a+1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/174783592/Adder_PL/sum16bitPLTB.sv:48: Unsupported: Ignoring delay on this delayed statement.\n    always #5 b<=b+1;\n           ^\n%Error: data/full_repos/permissive/174783592/Adder_PL/sum16bitPLTB.sv:50: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dumpfile_adder.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/174783592/Adder_PL/sum16bitPLTB.sv:51: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars (0,sum16bitPLTB);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/174783592/Adder_PL/sum16bitPLTB.sv:52: Unsupported or unknown PLI call: $monitor\n  $monitor ($time," clk=%d  a=%d   b=%d temp=%b wl4[15]=%b\\nsum=%d \\n",clk,a,b,s1.temp,s1.wl4[15],sum); \n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174783592/Adder_PL/sum16bitPLTB.sv:55: Unsupported: Ignoring delay on this delayed statement.\n #20 $display ("kpgIn[%d]=%b",i,s1.wl4[i]);\n ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sum16bitPLTB();
	reg [15:0] a;
	reg    [15:0] b;
	reg [1:0] kIn;
    reg clk;
       	integer i;
	wire [16:0] sum ;
	wire     [1:0] kOut;
	
	sum16bitPL s1(a,b,kIn,  sum,clk);
	initial
	begin
		a <= {4{4'b1001}};
		b <= {4{4'b1111}};
		kIn <= 2'b00;
       clk <= 0;
		#30 $finish;	
	end

    always #5 clk = ~clk;

    always #5 a<=a+1;
    always #5 b<=b+1;
	initial begin
		$dumpfile("dumpfile_adder.vcd");
		$dumpvars (0,sum16bitPLTB);
		$monitor ($time," clk=%d  a=%d   b=%d temp=%b wl4[15]=%b\nsum=%d \n",clk,a,b,s1.temp,s1.wl4[15],sum);
	for(i=0;i<16;i=i+1) 
		begin
	#20	$display ("kpgIn[%d]=%b",i,s1.wl4[i]);

		end
	end	

endmodule
module sum16bitPLTB();

	reg [15:0] a;
	reg    [15:0] b;
	reg [1:0] kIn;
    reg clk;
       	integer i;
	wire [16:0] sum ;
	wire     [1:0] kOut;
	
	sum16bitPL s1(a,b,kIn,  sum,clk);
	initial
	begin
		a <= {4{4'b1001}};
		b <= {4{4'b1111}};
		kIn <= 2'b00;
       clk <= 0;
		#30 $finish;	
	end

    always #5 clk = ~clk;

    always #5 a<=a+1;
    always #5 b<=b+1;
	initial begin
		$dumpfile("dumpfile_adder.vcd");
		$dumpvars (0,sum16bitPLTB);
		$monitor ($time," clk=%d  a=%d   b=%d temp=%b wl4[15]=%b\nsum=%d \n",clk,a,b,s1.temp,s1.wl4[15],sum);
	for(i=0;i<16;i=i+1) 
		begin
	#20	$display ("kpgIn[%d]=%b",i,s1.wl4[i]);

		end
	end	

endmodule