data/full_repos/permissive/151904248/Triple Buffer/clock_dividers.v
1: b'%Error: Cannot find file containing module: Buffer,data/full_repos/permissive/151904248\n        ... Looked in:\n             data/full_repos/permissive/151904248/Triple/Buffer,data/full_repos/permissive/151904248\n             data/full_repos/permissive/151904248/Triple/Buffer,data/full_repos/permissive/151904248.v\n             data/full_repos/permissive/151904248/Triple/Buffer,data/full_repos/permissive/151904248.sv\n             Buffer,data/full_repos/permissive/151904248\n             Buffer,data/full_repos/permissive/151904248.v\n             Buffer,data/full_repos/permissive/151904248.sv\n             obj_dir/Buffer,data/full_repos/permissive/151904248\n             obj_dir/Buffer,data/full_repos/permissive/151904248.v\n             obj_dir/Buffer,data/full_repos/permissive/151904248.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/151904248/Triple\n%Error: Cannot find file containing module: Buffer/clock_dividers.v\n%Error: Exiting due to 3 error(s)\n'
module MHz_25(
input wire clk_in,
input wire reset,
output reg clk_out
);

initial begin
	clk_out <= 1'b0;
end

always @ (posedge clk_in or negedge reset) begin
	if(reset == 1'b0) begin
		clk_out <= 1'b0;
	end
	else begin
		clk_out <= ~clk_out;
	end
end


endmodule
module MHz_25(
input wire clk_in,
input wire reset,
output reg clk_out
);


initial begin
	clk_out <= 1'b0;
end

always @ (posedge clk_in or negedge reset) begin
	if(reset == 1'b0) begin
		clk_out <= 1'b0;
	end
	else begin
		clk_out <= ~clk_out;
	end
end


endmodule