data/full_repos/permissive/21918193/group_size_is_911_bits/testbench/test_ram.v
 line:100: before: "forever"
1: b'%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_911_bits/testbench/test_ram.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/21918193/group_size_is_911_bits/testbench/test_ram.v:64: syntax error, unexpected \'@\'\n        @ (negedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_911_bits/testbench/test_ram.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_911_bits/testbench/test_ram.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_911_bits/testbench/test_ram.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_911_bits/testbench/test_ram.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_911_bits/testbench/test_ram.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_911_bits/testbench/test_ram.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_911_bits/testbench/test_ram.v:100: Unsupported: Ignoring delay on this delayed statement.\n    initial #100 forever #(20/2) clk = ~clk;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/21918193/group_size_is_911_bits/testbench/test_ram.v:100: Unsupported: Ignoring delay on this delayed statement.\n    initial #100 forever #(20/2) clk = ~clk;\n            ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_ram;


	reg clk;
	reg reset;
	reg sel;
	reg [5:0] addr;
	reg w;
	reg [`WIDTH_D0:0] data;


	wire [`WIDTH_D0:0] out;
	wire done;


	tiny uut (
		.clk(clk), 
		.reset(reset), 
		.sel(sel), 
		.addr(addr), 
		.w(w), 
		.data(data), 
		.out(out), 
		.done(done)
	);

	initial begin

		clk = 0;
		reset = 0;
		sel = 0;
		addr = 0;
		w = 0;
		data = 0;


		#100;
        

        @ (negedge clk);
        

        sel = 1; w = 1;
        data = 198'h115a25886512165251569195908560596a6695612620504191;
        addr = 0;
        #(`P);
        data = 198'h1559546442405a181195655549614540592955a15a26984015;
        addr = 3;
        #(`P);

        w = 0;
        data = 198'h12222222222222222222222222222222222222222222222222;
        addr = 3;
        #(`P);
        

        sel = 1; w = 0;
        addr = 0;
        #(`P);
        if (out !== 198'h115a25886512165251569195908560596a6695612620504191) begin
            $display("E"); $finish;
        end

        addr = 3;
        #(`P);
        if (out !== 198'h1559546442405a181195655549614540592955a15a26984015) begin
            $display("E"); $finish;
        end

        #(`P);
        
        $display("Good");
        $finish;
	end
    
    initial #100 forever #(`P/2) clk = ~clk;
endmodule
module test_ram;



	reg clk;
	reg reset;
	reg sel;
	reg [5:0] addr;
	reg w;
	reg [`WIDTH_D0:0] data;


	wire [`WIDTH_D0:0] out;
	wire done;


	tiny uut (
		.clk(clk), 
		.reset(reset), 
		.sel(sel), 
		.addr(addr), 
		.w(w), 
		.data(data), 
		.out(out), 
		.done(done)
	);

	initial begin

		clk = 0;
		reset = 0;
		sel = 0;
		addr = 0;
		w = 0;
		data = 0;


		#100;
        

        @ (negedge clk);
        

        sel = 1; w = 1;
        data = 198'h115a25886512165251569195908560596a6695612620504191;
        addr = 0;
        #(`P);
        data = 198'h1559546442405a181195655549614540592955a15a26984015;
        addr = 3;
        #(`P);

        w = 0;
        data = 198'h12222222222222222222222222222222222222222222222222;
        addr = 3;
        #(`P);
        

        sel = 1; w = 0;
        addr = 0;
        #(`P);
        if (out !== 198'h115a25886512165251569195908560596a6695612620504191) begin
            $display("E"); $finish;
        end

        addr = 3;
        #(`P);
        if (out !== 198'h1559546442405a181195655549614540592955a15a26984015) begin
            $display("E"); $finish;
        end

        #(`P);
        
        $display("Good");
        $finish;
	end
    
    initial #100 forever #(`P/2) clk = ~clk;
endmodule