data/full_repos/permissive/214823094/submissions/lab_5/project_5/binary_counter.v
data/verilator_xmls/71f5d023-728a-45d9-a242-2e8416a71566.xml
module binary_counter(A,B,C,D,clear,load,P,T,clk,Q,RCO);
    
    input A,B,C,D;
    input clear,load,P,T;
    input clk;
    output [3:0]Q;
    output RCO;
    reg [3:0]Q;
    reg RCO;
    wire myclk;
    clkdiv a(clk,myclk);
    always@(posedge myclk)
    begin
        if(!clear)
        begin 
        Q<=4'b0000;
        end
        else 
        if(!load)
        begin 
        Q<={D,C,B,A};
        end
        else 
        casex({P,T})
            2'b0x:begin Q<=Q;end
            2'bx0:begin Q<=Q;end
            2'b11:
            begin
                if(Q==4'b1110)
                begin
                    Q<=Q+1;
                    RCO<=1'b1;
                end
                else
                begin
                    Q<=Q+1;
                    RCO<=1'b0;
                end
            end
        endcase
    end
    
endmodule
module binary_counter(A,B,C,D,clear,load,P,T,clk,Q,RCO);

    
    input A,B,C,D;
    input clear,load,P,T;
    input clk;
    output [3:0]Q;
    output RCO;
    reg [3:0]Q;
    reg RCO;
    wire myclk;
    clkdiv a(clk,myclk);
    always@(posedge myclk)
    begin
        if(!clear)
        begin 
        Q<=4'b0000;
        end
        else 
        if(!load)
        begin 
        Q<={D,C,B,A};
        end
        else 
        casex({P,T})
            2'b0x:begin Q<=Q;end
            2'bx0:begin Q<=Q;end
            2'b11:
            begin
                if(Q==4'b1110)
                begin
                    Q<=Q+1;
                    RCO<=1'b1;
                end
                else
                begin
                    Q<=Q+1;
                    RCO<=1'b0;
                end
            end
        endcase
    end
    
endmodule