data/full_repos/permissive/143278/ivltests/real_delay.v
 line:3: before: "primitive"
1: b'%Error: data/full_repos/permissive/143278/ivltests/real_delay.v:33: Unsupported or unknown PLI call: $monitor\n    $monitor("%.3f", $realtime,, sml_const.test, sml_var.test,\n    ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/real_delay.v:33: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    $monitor("%.3f", $realtime,, sml_const.test, sml_var.test,\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_delay.v:50: Unsupported: Ignoring delay on this delayed statement.\n     #1.3 $finish(0);\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/real_delay.v:67: Unsupported or unknown PLI call: $sdf_annotate\n    $sdf_annotate("ivltests/real_delay.sdf");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/real_delay.v:68: Unsupported or unknown PLI call: $sdf_annotate\n    $sdf_annotate("ivltests/real_delay_sml.sdf");\n    ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_delay.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #1.234 test = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_delay.v:117: Unsupported: Ignoring delay on this delayed statement.\n    #(dly) test = 1\'b1;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/real_delay.v:136: Unsupported or unknown PLI call: $sdf_annotate\n    $sdf_annotate("ivltests/real_delay.sdf");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/real_delay.v:137: Unsupported or unknown PLI call: $sdf_annotate\n    $sdf_annotate("ivltests/real_delay_med.sdf");\n    ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_delay.v:141: Unsupported: Ignoring delay on this delayed statement.\n    #1.234 test = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_delay.v:185: Unsupported: Ignoring delay on this delayed statement.\n    #(dly) test = 1\'b1;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/real_delay.v:204: Unsupported or unknown PLI call: $sdf_annotate\n    $sdf_annotate("ivltests/real_delay.sdf");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/real_delay.v:205: Unsupported or unknown PLI call: $sdf_annotate\n    $sdf_annotate("ivltests/real_delay_lrg.sdf");\n    ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_delay.v:209: Unsupported: Ignoring delay on this delayed statement.\n    #1.234 test = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_delay.v:253: Unsupported: Ignoring delay on this delayed statement.\n    #(dly) test = 1\'b1;\n    ^\n%Error: Exiting due to 8 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lrg_const;
  reg test, in;
  wire out_g, out_u, out_m, out_s, out_f;
  not #(1.134, 0) gate (out_g, in);
  not_u #(1.134, 0) dut_u (out_u, in);
  lrg_inv dut_m (out_m, in);
  gate_sdf dut_f (out_f, in);
  lrg_sdf dut_s (out_s, in);
  initial begin
    $sdf_annotate("ivltests/real_delay.sdf");
    $sdf_annotate("ivltests/real_delay_lrg.sdf");
    in = 1'b1;
    in <= #0.1 1'b0;
    test = 1'b0;
    #1.234 test = 1'b1;
  end
endmodule
module lrg_const;

  reg test, in;
  wire out_g, out_u, out_m, out_s, out_f;
  not #(1.134, 0) gate (out_g, in);
  not_u #(1.134, 0) dut_u (out_u, in);
  lrg_inv dut_m (out_m, in);
  gate_sdf dut_f (out_f, in);
  lrg_sdf dut_s (out_s, in);
  initial begin
    $sdf_annotate("ivltests/real_delay.sdf");
    $sdf_annotate("ivltests/real_delay_lrg.sdf");
    in = 1'b1;
    in <= #0.1 1'b0;
    test = 1'b0;
    #1.234 test = 1'b1;
  end
endmodule