data/full_repos/permissive/146618947/valid_tarea6/mux_41_tb.v
 line:133: before: "("
1: b'%Error: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tb.v:2: Cannot find include file: mux_41.v\n`include "mux_41.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146618947/valid_tarea6,data/full_repos/permissive/146618947/mux_41.v\n             data/full_repos/permissive/146618947/valid_tarea6,data/full_repos/permissive/146618947/mux_41.v.v\n             data/full_repos/permissive/146618947/valid_tarea6,data/full_repos/permissive/146618947/mux_41.v.sv\n             mux_41.v\n             mux_41.v.v\n             mux_41.v.sv\n             obj_dir/mux_41.v\n             obj_dir/mux_41.v.v\n             obj_dir/mux_41.v.sv\n%Error: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tb.v:3: Cannot find include file: mux_41_tester.v\n`include "mux_41_tester.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/146618947/valid_tarea6/mux_41_tb.v:4: Cannot find include file: mux_41_estructural.v\n`include "mux_41_estructural.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module mux_tb;
   wire reset_L, clk;
   wire [3:0] data_0;
   wire [3:0] data_1;
   wire [3:0] data_2;
   wire [3:0] data_3;
   wire [3:0] data_out_cond;
   wire [3:0] data_out_est;
   wire       valid_0;
   wire       valid_1;
   wire       valid_2;
   wire       valid_3;
   wire       valid_out_cond;
   wire       valid_out_est;

   mux_41 mux_41_( .reset_L (reset_L),
             .clk (clk),
             .data_0 (data_0),
             .data_1 (data_1),
             .data_2 (data_2),
             .data_3 (data_3),
             .data_out (data_out_cond),
             .valid_0 (valid_0),
             .valid_1 (valid_1),
             .valid_2 (valid_2),
             .valid_3 (valid_3),
             .valid_out (valid_out_cond)
             );

   mux_41_tester mux_41_tester_( .reset_L (reset_L),
                           .clk (clk),
                           .data_0 (data_0),
                           .data_1 (data_1),
                           .data_2 (data_2),
                           .data_3 (data_3),
                           .data_out_cond (data_out_cond),
                           .data_out_est (data_out_est),
                           .valid_0 (valid_0),
                           .valid_1 (valid_1),
                           .valid_2 (valid_2),
                           .valid_3 (valid_3),
                           .valid_out_cond (valid_out_cond),
                           .valid_out_est (valid_out_est)
                           );

   mux_41_estructural mux_41_est_( .reset_L (reset_L),
                             .clk (clk),
                             .data_0 (data_0),
                             .data_1 (data_1),
                             .data_2 (data_2),
                             .data_3 (data_3),
                             .data_out (data_out_est),
                             .valid_0 (valid_0),
                             .valid_1 (valid_1),
                             .valid_2 (valid_2),
                             .valid_3 (valid_3),
                             .valid_out (valid_out_est)
                             );

endmodule
module mux_tb;

   wire reset_L, clk;
   wire [3:0] data_0;
   wire [3:0] data_1;
   wire [3:0] data_2;
   wire [3:0] data_3;
   wire [3:0] data_out_cond;
   wire [3:0] data_out_est;
   wire       valid_0;
   wire       valid_1;
   wire       valid_2;
   wire       valid_3;
   wire       valid_out_cond;
   wire       valid_out_est;

   mux_41 mux_41_( .reset_L (reset_L),
             .clk (clk),
             .data_0 (data_0),
             .data_1 (data_1),
             .data_2 (data_2),
             .data_3 (data_3),
             .data_out (data_out_cond),
             .valid_0 (valid_0),
             .valid_1 (valid_1),
             .valid_2 (valid_2),
             .valid_3 (valid_3),
             .valid_out (valid_out_cond)
             );

   mux_41_tester mux_41_tester_( .reset_L (reset_L),
                           .clk (clk),
                           .data_0 (data_0),
                           .data_1 (data_1),
                           .data_2 (data_2),
                           .data_3 (data_3),
                           .data_out_cond (data_out_cond),
                           .data_out_est (data_out_est),
                           .valid_0 (valid_0),
                           .valid_1 (valid_1),
                           .valid_2 (valid_2),
                           .valid_3 (valid_3),
                           .valid_out_cond (valid_out_cond),
                           .valid_out_est (valid_out_est)
                           );

   mux_41_estructural mux_41_est_( .reset_L (reset_L),
                             .clk (clk),
                             .data_0 (data_0),
                             .data_1 (data_1),
                             .data_2 (data_2),
                             .data_3 (data_3),
                             .data_out (data_out_est),
                             .valid_0 (valid_0),
                             .valid_1 (valid_1),
                             .valid_2 (valid_2),
                             .valid_3 (valid_3),
                             .valid_out (valid_out_est)
                             );

endmodule