data/full_repos/permissive/163494071/countdown/countdown.v
data/verilator_xmls/6e16eec9-367d-4c49-897e-b8eb9f339097.xml
module two_ten(clk,num,ten,one);
input [4:0] num;
input clk;
output reg [3:0] ten;
output reg [3:0] one;

integer i;
	
			always @(posedge clk)
			begin
				ten=4'd0;
				one=4'd0;
		
				for(i=4;i>=0;i=i-1)
				begin
					if(ten>4)
						ten=ten+4'd3;
					if(one>4)
						one=one+4'd3;
					ten=ten<<1;
					ten[0]=one[3];
					one=one<<1;
					one[0]=num[i];
				end
			end
endmodule
module two_ten(clk,num,ten,one);

input [4:0] num;
input clk;
output reg [3:0] ten;
output reg [3:0] one;

integer i;
	
			always @(posedge clk)
			begin
				ten=4'd0;
				one=4'd0;
		
				for(i=4;i>=0;i=i-1)
				begin
					if(ten>4)
						ten=ten+4'd3;
					if(one>4)
						one=one+4'd3;
					ten=ten<<1;
					ten[0]=one[3];
					one=one<<1;
					one[0]=num[i];
				end
			end
endmodule