data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:5: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.v\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.sv\n             lib/generic.v\n             lib/generic.v.v\n             lib/generic.v.sv\n             obj_dir/lib/generic.v\n             obj_dir/lib/generic.v.v\n             obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:6: Cannot find include file: lib/DebugInfoWarningError.sv\n`include "lib/DebugInfoWarningError.sv" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:341: Expecting `error string. Found: TEXT\n   `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:344: Expecting `error string. Found: TEXT\n   `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:738: Expecting `error string. Found: TEXT\n   `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:741: Expecting `error string. Found: TEXT\n   `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:905: Expecting `error string. Found: TEXT\n   `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:908: Expecting `error string. Found: TEXT\n   `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:7: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport DebugInfoWarningError::*;\n       ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:99: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n      ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:105: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n                  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:106: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n                  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:107: syntax error, unexpected \'.\', expecting ::\n wire  wbeat =  axi.wready &  axi.wvalid;\n                   ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:108: syntax error, unexpected \'.\', expecting ::\n wire  rbeat =  axi.rready &  axi.rvalid;\n                   ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:109: syntax error, unexpected \'.\', expecting ::\n wire  bbeat =  axi.bready &  axi.bvalid;\n                   ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:112: syntax error, unexpected \'.\', expecting ::\n always @(posedge  wbeat) begin $display("%t,  wbeat %08x", $time, axi.wdata); end\n                                                                      ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:113: syntax error, unexpected \'.\', expecting ::\n always @(posedge  rbeat) begin $display("%t,  rbeat %08x", $time, axi.rdata); end\n                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:118: Unsupported: Ignoring delay on this delayed statement.\n   #DELAY_BETWEEN_TRANSACTIONS;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:121: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD_OF_CLOCK_NS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:128: Unsupported: Ignoring delay on this delayed statement.\n   #DELAY_BETWEEN_TRANSACTIONS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:131: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD_OF_CLOCK_NS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:135: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD_OF_CLOCK_NS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:142: Unsupported: Ignoring delay on this delayed statement.\n  #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:143: Unsupported: Dynamic array new\n  data = new[1];\n         ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:148: Unsupported: Ignoring delay on this delayed statement.\n  #LONG_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:153: Unsupported: Ignoring delay on this delayed statement.\n  #LONG_DELAY; $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:157: Unsupported: Ignoring delay on this delayed statement.\n  #DELAY;\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:190: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n                 ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:208: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:347: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n                 ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:348: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n                           ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:376: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n      ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:386: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n                  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:387: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n                  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:388: syntax error, unexpected \'.\', expecting ::\n wire  wbeat =  axi.wready &  axi.wvalid;\n                   ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:389: syntax error, unexpected \'.\', expecting ::\n wire  rbeat =  axi.rready &  axi.rvalid;\n                   ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:390: syntax error, unexpected \'.\', expecting ::\n wire  bbeat =  axi.bready &  axi.bvalid;\n                   ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:393: syntax error, unexpected \'.\', expecting ::\n always @(posedge  wbeat) begin $display("%t,  wbeat %08x", $time, axi.wdata); end\n                                                                      ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:394: syntax error, unexpected \'.\', expecting ::\n always @(posedge  rbeat) begin $display("%t,  rbeat %08x", $time, axi.rdata); end\n                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:399: Unsupported: Ignoring delay on this delayed statement.\n   #DELAY_BETWEEN_TRANSACTIONS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:403: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD_OF_CLOCK_NS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:407: Unsupported: Ignoring delay on this delayed statement.\n    #PERIOD_OF_CLOCK_NS;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:410: Unsupported: Ignoring delay on this delayed statement.\n     #DELAY_BETWEEN_READ_BEATS;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:418: Unsupported: Ignoring delay on this delayed statement.\n   #DELAY_BETWEEN_TRANSACTIONS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:422: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD_OF_CLOCK_NS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:428: Unsupported: Ignoring delay on this delayed statement.\n    #PERIOD_OF_CLOCK_NS;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:436: Unsupported: Ignoring delay on this delayed statement.\n   #DELAY_BETWEEN_TRANSACTIONS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:440: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD_OF_CLOCK_NS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:446: Unsupported: Ignoring delay on this delayed statement.\n    #PERIOD_OF_CLOCK_NS;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:449: Unsupported: Ignoring delay on this delayed statement.\n     #DELAY_BETWEEN_WRITE_BEATS;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:453: Unsupported: Ignoring delay on this delayed statement.\n     #DELAY_BETWEEN_WRITE_BEATS;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:454: Unsupported: Ignoring delay on this delayed statement.\n     #DELAY_BETWEEN_WRITE_BEATS;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:455: Unsupported: Ignoring delay on this delayed statement.\n     #DELAY_BETWEEN_WRITE_BEATS;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:456: Unsupported: Ignoring delay on this delayed statement.\n     #DELAY_BETWEEN_WRITE_BEATS;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:465: Unsupported: Ignoring delay on this delayed statement.\n  #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:466: Unsupported: Dynamic array new\n  data = new[2**LEN_WIDTH];\n         ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:490: Unsupported: Ignoring delay on this delayed statement.\n  #LONG_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:502: Unsupported: Ignoring delay on this delayed statement.\n  #LONG_DELAY; $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:506: Unsupported: Ignoring delay on this delayed statement.\n  #DELAY;\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:546: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n                 ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:566: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:744: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n                 ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:745: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n                           ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:753: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.peripheral axi\n                 ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:766: syntax error, unexpected IDENTIFIER\n axi4 modified_copy(clock, reset);\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:768: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: Exiting due to 38 error(s), 28 warning(s)\n'
module parallel_peripheral__axi4_controller #(
	parameter ADDRESS_WIDTH = 4,
	parameter DATA_WIDTH = 32
) (

	input [ADDRESS_WIDTH-1:0] parallel_write_address,
	input parallel_write_address_valid,
	input [DATA_WIDTH-1:0] parallel_write_data,
	input parallel_write_data_valid,

	input [ADDRESS_WIDTH-1:0] parallel_read_address,
	input parallel_read_address_valid,
	output reg [DATA_WIDTH-1:0] parallel_read_data = 0,
	output reg parallel_read_data_valid = 0,
	axi4.controller axi
);

	assign axi.awburst = axi::FIXED;


	assign axi.arburst = axi::FIXED;

	assign axi.awlen = 0;
	assign axi.arlen = 0;
	reg [1:0] rstate = 0;
	reg [2:0] wstate = 0;
	reg last_write_was_succecssful = 0;
	reg our_rlast = 0;
	axi::state_t cw_state;
	axi::state_t cr_state;
	reg [31:0] error_count = 0;
	localparam DELAY = 0;
	always @(posedge axi.clock) begin
		#DELAY;
		if (axi.reset) begin
			axi.awaddr  <= 0;
			axi.awvalid <= 0;
			axi.wdata   <= 0;
			axi.wvalid  <= 0;
			axi.araddr  <= 0;
			axi.arvalid <= 0;
			axi.wlast   <= 0;
			axi.bready  <= 0;
			axi.rready  <= 0;
			wstate <= 0;
			rstate <= 0;
			last_write_was_succecssful <= 0;
			parallel_read_data <= 0;
			our_rlast <= 0;
			cw_state <= axi::IDLE;
			cr_state <= axi::IDLE;
		end else begin

			case (cw_state)
				axi::IDLE: begin
						axi.awvalid <= 0;
						axi.wvalid <= 0;
						axi.wlast <= 0;
						axi.bready <= 0;
						if (parallel_write_address_valid) begin
							axi.awaddr <= parallel_write_address;
							axi.awvalid <= 1;
							axi.wlast <= 1;
							if (axi.awready) begin
								cw_state <= axi::WAITING_FOR_WREADY;
							end else begin
								cw_state <= axi::WAITING_FOR_AWREADY;
							end
						end
					end
				axi::WAITING_FOR_AWREADY: begin
						axi.awvalid <= 1;
						axi.wvalid <= 0;
						axi.wlast <= 0;
						axi.bready <= 0;
						if (axi.awready) begin
							axi.awvalid <= 0;
							if (parallel_write_data_valid) begin
								axi.wdata <= parallel_write_data;
								axi.wvalid <= 1;
								axi.wlast <= 1;
							end
							cw_state <= axi::WAITING_FOR_WREADY;
						end
					end
				axi::WAITING_FOR_WREADY: begin
						axi.awvalid <= 0;
						if (parallel_write_data_valid) begin
							axi.wdata <= parallel_write_data;
							axi.wvalid <= 1'b1;
						end
						axi.wlast <= 1;
						axi.bready <= 0;
						if (axi.wready) begin
							axi.wvalid <= 0;
							axi.wlast <= 0;
							axi.bready <= 1;
							cw_state <= axi::WAITING_FOR_BVALID;
						end
					end
				axi::WAITING_FOR_BVALID: begin
						axi.awvalid <= 0;
						axi.wvalid <= 0;
						axi.wlast <= 0;
						axi.bready <= 1;
						if (axi.bvalid) begin
							axi.bready <= 0;
							cw_state <= axi::IDLE;
						end
					end
				default: begin
						error_count <= error_count + 1'b1;
						cw_state <= axi::IDLE;
				end
			endcase

			case (cr_state)
				axi::IDLE: begin
						axi.arvalid <= 0;
						axi.rready <= 0;
						our_rlast <= 0;
						parallel_read_data_valid <= 0;
						if (parallel_read_address_valid) begin
							axi.araddr <= parallel_read_address;
							axi.arvalid <= 1;
							cr_state <= axi::WAITING_FOR_ARREADY;
						end
					end
				axi::WAITING_FOR_ARREADY: begin
						axi.arvalid <= 1;
						axi.rready <= 0;
						our_rlast <= 0;
						parallel_read_data_valid <= 0;
						if (axi.arready) begin
							axi.arvalid <= 0;
							axi.rready <= 1;
							our_rlast <= 1;
							cr_state <= axi::WAITING_FOR_RVALID;
						end
					end
				axi::WAITING_FOR_RVALID: begin
						axi.arvalid <= 0;
						axi.rready <= 1;
						our_rlast <= 1;
						parallel_read_data_valid <= 0;
						if (axi.rvalid) begin
							parallel_read_data <= axi.rdata;
							parallel_read_data_valid <= 1;
							axi.arvalid <= 0;
							axi.rready <= 0;
							our_rlast <= 0;
							cr_state <= axi::IDLE;

						end
					end
				default: begin
						error_count <= error_count + 1'b1;
						cr_state <= axi::IDLE;
				end
			endcase
		end
	end
	initial begin
		#0;
		assert (^axi.awburst!==1'bx && axi.awburst==axi::FIXED || axi.awburst==axi::INCR) else begin
			`error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name);
		end
		assert (^axi.arburst!==1'bx && axi.arburst==axi::FIXED || axi.arburst==axi::INCR) else begin
			`error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name);
		end
	end
	wire rbeat = axi.rready & axi.rvalid;
	wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;
endmodule
module parallel_peripheral__axi4_controller #(
	parameter ADDRESS_WIDTH = 4,
	parameter DATA_WIDTH = 32
) (

	input [ADDRESS_WIDTH-1:0] parallel_write_address,
	input parallel_write_address_valid,
	input [DATA_WIDTH-1:0] parallel_write_data,
	input parallel_write_data_valid,

	input [ADDRESS_WIDTH-1:0] parallel_read_address,
	input parallel_read_address_valid,
	output reg [DATA_WIDTH-1:0] parallel_read_data = 0,
	output reg parallel_read_data_valid = 0,
	axi4.controller axi
);


	assign axi.awburst = axi::FIXED;


	assign axi.arburst = axi::FIXED;

	assign axi.awlen = 0;
	assign axi.arlen = 0;
	reg [1:0] rstate = 0;
	reg [2:0] wstate = 0;
	reg last_write_was_succecssful = 0;
	reg our_rlast = 0;
	axi::state_t cw_state;
	axi::state_t cr_state;
	reg [31:0] error_count = 0;
	localparam DELAY = 0;
	always @(posedge axi.clock) begin
		#DELAY;
		if (axi.reset) begin
			axi.awaddr  <= 0;
			axi.awvalid <= 0;
			axi.wdata   <= 0;
			axi.wvalid  <= 0;
			axi.araddr  <= 0;
			axi.arvalid <= 0;
			axi.wlast   <= 0;
			axi.bready  <= 0;
			axi.rready  <= 0;
			wstate <= 0;
			rstate <= 0;
			last_write_was_succecssful <= 0;
			parallel_read_data <= 0;
			our_rlast <= 0;
			cw_state <= axi::IDLE;
			cr_state <= axi::IDLE;
		end else begin

			case (cw_state)
				axi::IDLE: begin
						axi.awvalid <= 0;
						axi.wvalid <= 0;
						axi.wlast <= 0;
						axi.bready <= 0;
						if (parallel_write_address_valid) begin
							axi.awaddr <= parallel_write_address;
							axi.awvalid <= 1;
							axi.wlast <= 1;
							if (axi.awready) begin
								cw_state <= axi::WAITING_FOR_WREADY;
							end else begin
								cw_state <= axi::WAITING_FOR_AWREADY;
							end
						end
					end
				axi::WAITING_FOR_AWREADY: begin
						axi.awvalid <= 1;
						axi.wvalid <= 0;
						axi.wlast <= 0;
						axi.bready <= 0;
						if (axi.awready) begin
							axi.awvalid <= 0;
							if (parallel_write_data_valid) begin
								axi.wdata <= parallel_write_data;
								axi.wvalid <= 1;
								axi.wlast <= 1;
							end
							cw_state <= axi::WAITING_FOR_WREADY;
						end
					end
				axi::WAITING_FOR_WREADY: begin
						axi.awvalid <= 0;
						if (parallel_write_data_valid) begin
							axi.wdata <= parallel_write_data;
							axi.wvalid <= 1'b1;
						end
						axi.wlast <= 1;
						axi.bready <= 0;
						if (axi.wready) begin
							axi.wvalid <= 0;
							axi.wlast <= 0;
							axi.bready <= 1;
							cw_state <= axi::WAITING_FOR_BVALID;
						end
					end
				axi::WAITING_FOR_BVALID: begin
						axi.awvalid <= 0;
						axi.wvalid <= 0;
						axi.wlast <= 0;
						axi.bready <= 1;
						if (axi.bvalid) begin
							axi.bready <= 0;
							cw_state <= axi::IDLE;
						end
					end
				default: begin
						error_count <= error_count + 1'b1;
						cw_state <= axi::IDLE;
				end
			endcase

			case (cr_state)
				axi::IDLE: begin
						axi.arvalid <= 0;
						axi.rready <= 0;
						our_rlast <= 0;
						parallel_read_data_valid <= 0;
						if (parallel_read_address_valid) begin
							axi.araddr <= parallel_read_address;
							axi.arvalid <= 1;
							cr_state <= axi::WAITING_FOR_ARREADY;
						end
					end
				axi::WAITING_FOR_ARREADY: begin
						axi.arvalid <= 1;
						axi.rready <= 0;
						our_rlast <= 0;
						parallel_read_data_valid <= 0;
						if (axi.arready) begin
							axi.arvalid <= 0;
							axi.rready <= 1;
							our_rlast <= 1;
							cr_state <= axi::WAITING_FOR_RVALID;
						end
					end
				axi::WAITING_FOR_RVALID: begin
						axi.arvalid <= 0;
						axi.rready <= 1;
						our_rlast <= 1;
						parallel_read_data_valid <= 0;
						if (axi.rvalid) begin
							parallel_read_data <= axi.rdata;
							parallel_read_data_valid <= 1;
							axi.arvalid <= 0;
							axi.rready <= 0;
							our_rlast <= 0;
							cr_state <= axi::IDLE;

						end
					end
				default: begin
						error_count <= error_count + 1'b1;
						cr_state <= axi::IDLE;
				end
			endcase
		end
	end
	initial begin
		#0;
		assert (^axi.awburst!==1'bx && axi.awburst==axi::FIXED || axi.awburst==axi::INCR) else begin
			`error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name);
		end
		assert (^axi.arburst!==1'bx && axi.arburst==axi::FIXED || axi.arburst==axi::INCR) else begin
			`error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name);
		end
	end
	wire rbeat = axi.rready & axi.rvalid;
	wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;
endmodule