data/full_repos/permissive/106408053/verilog/trigger_adv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n              ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module trigterm_32bit (dataIn, clock, wrenb, din, dout, hit);
input [31:0] dataIn;
input clock, wrenb, din;
output dout;
output [7:0] hit;
trigterm_4bit nyb0 (dataIn[3:0], clock, wrenb, din, n0, hit[0]);
trigterm_4bit nyb1 (dataIn[7:4], clock, wrenb, n0, n1, hit[1]);
trigterm_4bit nyb2 (dataIn[11:8], clock, wrenb, n1, n2, hit[2]);
trigterm_4bit nyb3 (dataIn[15:12], clock, wrenb, n2, n3, hit[3]);
trigterm_4bit nyb4 (dataIn[19:16], clock, wrenb, n3, n4, hit[4]);
trigterm_4bit nyb5 (dataIn[23:20], clock, wrenb, n4, n5, hit[5]);
trigterm_4bit nyb6 (dataIn[27:24], clock, wrenb, n5, n6, hit[6]);
trigterm_4bit nyb7 (dataIn[31:28], clock, wrenb, n6, dout, hit[7]);
endmodule
module trigterm_32bit (dataIn, clock, wrenb, din, dout, hit);

input [31:0] dataIn;
input clock, wrenb, din;
output dout;
output [7:0] hit;
trigterm_4bit nyb0 (dataIn[3:0], clock, wrenb, din, n0, hit[0]);
trigterm_4bit nyb1 (dataIn[7:4], clock, wrenb, n0, n1, hit[1]);
trigterm_4bit nyb2 (dataIn[11:8], clock, wrenb, n1, n2, hit[2]);
trigterm_4bit nyb3 (dataIn[15:12], clock, wrenb, n2, n3, hit[3]);
trigterm_4bit nyb4 (dataIn[19:16], clock, wrenb, n3, n4, hit[4]);
trigterm_4bit nyb5 (dataIn[23:20], clock, wrenb, n4, n5, hit[5]);
trigterm_4bit nyb6 (dataIn[27:24], clock, wrenb, n5, n6, hit[6]);
trigterm_4bit nyb7 (dataIn[31:28], clock, wrenb, n6, dout, hit[7]);
endmodule