data/full_repos/permissive/177136805/full_adder.v
data/verilator_xmls/feae2220-abdd-45b5-b678-12970242c38a.xml
module FullAdder(a, b, cin, s, cout);



  input wire a, b, cin;
  


  output wire s, cout;


  assign s = cin ^ a ^ b;
  assign cout = (b & cin) | (a & cin) | (a & b); 
  
endmodule
module FullAdder(a, b, cin, s, cout);




  input wire a, b, cin;
  


  output wire s, cout;


  assign s = cin ^ a ^ b;
  assign cout = (b & cin) | (a & cin) | (a & b); 
  
endmodule