data/full_repos/permissive/147086086/Lab6/hw/multiplexer/mux_5in1_tb.v
 line:29: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/147086086/Lab6/hw/multiplexer/mux_5in1_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n            #DELAY;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/147086086/Lab6/hw/multiplexer/mux_5in1_tb.v:14: Cannot find file containing module: \'mux_5in1\'\nmux_5in1 #(.WIDTH(WIDTH)) mux_inst(.i_dat0 (i_dat0), \n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147086086/Lab6/hw/multiplexer,data/full_repos/permissive/147086086/mux_5in1\n             data/full_repos/permissive/147086086/Lab6/hw/multiplexer,data/full_repos/permissive/147086086/mux_5in1.v\n             data/full_repos/permissive/147086086/Lab6/hw/multiplexer,data/full_repos/permissive/147086086/mux_5in1.sv\n             mux_5in1\n             mux_5in1.v\n             mux_5in1.sv\n             obj_dir/mux_5in1\n             obj_dir/mux_5in1.v\n             obj_dir/mux_5in1.sv\n%Warning-WIDTH: data/full_repos/permissive/147086086/Lab6/hw/multiplexer/mux_5in1_tb.v:27: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                         : ... In instance testbench\n        i_sel = i;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/147086086/Lab6/hw/multiplexer/mux_5in1_tb.v:30: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                         : ... In instance testbench\n            i_dat0 = $random;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/147086086/Lab6/hw/multiplexer/mux_5in1_tb.v:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                         : ... In instance testbench\n            i_dat1 = $random;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/147086086/Lab6/hw/multiplexer/mux_5in1_tb.v:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                         : ... In instance testbench\n            i_dat2 = $random;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/147086086/Lab6/hw/multiplexer/mux_5in1_tb.v:33: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                         : ... In instance testbench\n            i_dat3 = $random;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/147086086/Lab6/hw/multiplexer/mux_5in1_tb.v:34: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                         : ... In instance testbench\n            i_dat4 = $random;\n                   ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

parameter DELAY = 20;
parameter WIDTH = 8;

reg     [WIDTH-1:0]  i_dat0, i_dat1, i_dat2, i_dat3, i_dat4;
reg     [2:0]        i_sel;
wire    [WIDTH-1:0]  o_dat;

integer i;

mux_5in1 #(.WIDTH(WIDTH)) mux_inst(.i_dat0 (i_dat0), 
                                   .i_dat1 (i_dat1), 
                                   .i_dat2 (i_dat2), 
                                   .i_dat3 (i_dat3), 
                                   .i_dat4 (i_dat4), 
                                   .i_sel (i_sel), 
                                   .o_dat (o_dat)
                                   );

initial begin
    
    for (i=0; i<8; i=i+1) begin

        i_sel = i;

        repeat (10) begin
            i_dat0 = $random;
            i_dat1 = $random;
            i_dat2 = $random;
            i_dat3 = $random;
            i_dat4 = $random;
            #DELAY;
        end

    end

    $finish;

end

endmodule
module testbench;


parameter DELAY = 20;
parameter WIDTH = 8;

reg     [WIDTH-1:0]  i_dat0, i_dat1, i_dat2, i_dat3, i_dat4;
reg     [2:0]        i_sel;
wire    [WIDTH-1:0]  o_dat;

integer i;

mux_5in1 #(.WIDTH(WIDTH)) mux_inst(.i_dat0 (i_dat0), 
                                   .i_dat1 (i_dat1), 
                                   .i_dat2 (i_dat2), 
                                   .i_dat3 (i_dat3), 
                                   .i_dat4 (i_dat4), 
                                   .i_sel (i_sel), 
                                   .o_dat (o_dat)
                                   );

initial begin
    
    for (i=0; i<8; i=i+1) begin

        i_sel = i;

        repeat (10) begin
            i_dat0 = $random;
            i_dat1 = $random;
            i_dat2 = $random;
            i_dat3 = $random;
            i_dat4 = $random;
            #DELAY;
        end

    end

    $finish;

end

endmodule