data/full_repos/permissive/143278/ivltests/ca_time.v
 line:10: before: ","
1: b'%Error: data/full_repos/permissive/143278/ivltests/ca_time.v:10: Unsupported or unknown PLI call: $monitor\n    $monitor(tm,, stm);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/ca_time.v:10: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    $monitor(tm,, stm);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ca_time.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #1 itrig = 1\'b1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ca_time.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #1 itrig = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ca_time.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1 itrig = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ca_time.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1 itrig = 1\'b0;\n    ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg itrig = 1'b0;
  wire [31:0] tm, stm;

  assign tm = itrig * $time;
  assign stm = itrig * $stime;

  initial begin
    $monitor(tm,, stm);
    #1 itrig = 1'b1;
    #1 itrig = 1'b0;
    #1 itrig = 1'b1;
    #1 itrig = 1'b0;
  end

endmodule
module top;

  reg itrig = 1'b0;
  wire [31:0] tm, stm;

  assign tm = itrig * $time;
  assign stm = itrig * $stime;

  initial begin
    $monitor(tm,, stm);
    #1 itrig = 1'b1;
    #1 itrig = 1'b0;
    #1 itrig = 1'b1;
    #1 itrig = 1'b0;
  end

endmodule