data/full_repos/permissive/111021593/horizontal_counter_generator_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/111021593/horizontal_counter_generator_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100 reset = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111021593/horizontal_counter_generator_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #20 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/111021593/horizontal_counter_generator_tb.v:9: Cannot find file containing module: \'horizontal_counter_generator\'\nhorizontal_counter_generator DUT(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/horizontal_counter_generator\n             data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/horizontal_counter_generator.v\n             data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/horizontal_counter_generator.sv\n             horizontal_counter_generator\n             horizontal_counter_generator.v\n             horizontal_counter_generator.sv\n             obj_dir/horizontal_counter_generator\n             obj_dir/horizontal_counter_generator.v\n             obj_dir/horizontal_counter_generator.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module horizontal_counter_generator_tb ();

reg clk, reset;
wire [9:0]hor_cnt;
wire [7:0]scl_hor_cnt;
wire new_line;


horizontal_counter_generator DUT(
	.clk(clk),
	.reset(reset),
	.hor_cnt(hor_cnt),
	.scl_hor_cnt(scl_hor_cnt),
	.new_line(new_line)
);

initial begin
	clk = 0;
	reset = 1;
	#100 reset = 0;
end

always begin
	#20 clk = ~clk;
end

endmodule
module horizontal_counter_generator_tb ();


reg clk, reset;
wire [9:0]hor_cnt;
wire [7:0]scl_hor_cnt;
wire new_line;


horizontal_counter_generator DUT(
	.clk(clk),
	.reset(reset),
	.hor_cnt(hor_cnt),
	.scl_hor_cnt(scl_hor_cnt),
	.new_line(new_line)
);

initial begin
	clk = 0;
	reset = 1;
	#100 reset = 0;
end

always begin
	#20 clk = ~clk;
end

endmodule