data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave/wb_spi_slave.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave/wb_spi_slave.v:80: Signal definition not found, creating implicitly: \'data_enable\'\n                                                                                                     : ... Suggested alternative: \'addr_enable\'\n          if(data_enable)\n             ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave/wb_spi_slave.v:85: Signal definition not found, creating implicitly: \'spi_active\'\n          if(~spi_active)\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave/wb_spi_slave.v:35: Value too wide for 32-bits expected in this context 72\'h6d616e6461746f7278\n  output [DATA_WIDTH-1:0] data_bus_r,\n                    ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave/wb_spi_slave.v:35: Width of bit range is huge; vector of over 1billion bits: 0x746f7279\n  output [DATA_WIDTH-1:0] data_bus_r,\n         ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave/wb_spi_slave.v:36: Value too wide for 32-bits expected in this context 72\'h6d616e6461746f7278\n  input  [DATA_WIDTH-1:0] data_bus_w,\n                    ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave/wb_spi_slave.v:36: Width of bit range is huge; vector of over 1billion bits: 0x746f7279\n  input  [DATA_WIDTH-1:0] data_bus_w,\n         ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave/wb_spi_slave.v:37: Value too wide for 32-bits expected in this context 72\'h6d616e6461746f7278\n  output reg [ADDR_WIDTH-1:0] addr_bus,\n                        ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave/wb_spi_slave.v:37: Width of bit range is huge; vector of over 1billion bits: 0x746f7279\n  output reg [ADDR_WIDTH-1:0] addr_bus,\n             ^\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave/wb_spi_slave.v:43: Cannot find file containing module: \'spi_slave\'\n  spi_slave #(.DATA_WIDTH(DATA_WIDTH)) spi0 (\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave,data/full_repos/permissive/141596082/spi_slave\n             data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave,data/full_repos/permissive/141596082/spi_slave.v\n             data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave,data/full_repos/permissive/141596082/spi_slave.sv\n             spi_slave\n             spi_slave.v\n             spi_slave.sv\n             obj_dir/spi_slave\n             obj_dir/spi_slave.v\n             obj_dir/spi_slave.sv\n%Error: data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave/wb_spi_slave.v:182: Value too wide for 32-bits expected in this context 72\'h6d616e6461746f7278\n        addr_bus <= data_bus_r[DATA_WIDTH-1:1];\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_spi_slave/wb_spi_slave.v:182: Operator ASSIGNDLY expects 746f7279 bits on the Assign RHS, but Assign RHS\'s SEL generates 746f7278 bits.\n                                                                                                   : ... In instance wb_spi_slave\n        addr_bus <= data_bus_r[DATA_WIDTH-1:1];\n                 ^~\n%Error: Exiting due to 8 error(s), 3 warning(s)\n'
module wb_spi_slave #(
  parameter ADDR_WIDTH = "mandatory",
  parameter DATA_WIDTH = "mandatory"
) (
  input  clk,
  input  resetn,

  input  mosi,
  input  ss,
  input  sck,
  output miso,

  input ack,
  output [DATA_WIDTH-1:0] data_bus_r,
  input  [DATA_WIDTH-1:0] data_bus_w,
  output reg [ADDR_WIDTH-1:0] addr_bus,
  output reg wr,
  output reg strobe,
  output cycle
);

  spi_slave #(.DATA_WIDTH(DATA_WIDTH)) spi0 (
    .clk            (clk                                         ),
    .resetn         (resetn                                      ),
    
    .mosi           (mosi                                        ),
    .ss             (ss                                          ),
    .sck            (sck                                         ),
    .miso           (miso                                        ),
    
    .data_bus_r     ({data_bus_r[7:0],data_bus_r[DATA_WIDTH-1:8]}),
    .data_bus_w     ({data_bus_w[7:0],data_bus_w[DATA_WIDTH-1:8]}),
    
    .data_enable    (data_enable                                 ),
    .SSEL_active(spi_active                                  ),
    .load_data_miso (ack                                         )
  );

  reg [3:0] state;
  reg rd,addr_enable,addr_inc;
  assign cycle = strobe;

  localparam [3:0] S_IDLE        = 4'd0;
  localparam [3:0] S_ADDRES      = 4'd1;
  localparam [3:0] S_MODE        = 4'd2;
  localparam [3:0] S_WRITE       = 4'd3;
  localparam [3:0] S_READ        = 4'd4;
  localparam [3:0] S_WAIT        = 4'd5;
  localparam [3:0] S_WAIT_ACK_RD = 4'd6;
  localparam [3:0] S_WAIT_ACK_WR = 4'd7;
  localparam [3:0] S_ADDR_INC    = 4'd8;

  always @(posedge clk or posedge resetn) begin
    if(resetn)
      state <= S_IDLE;
    else begin
      case(state)
        S_IDLE :
          if(data_enable)
            state <= S_ADDRES;
        else
          state <= S_IDLE;
        S_ADDRES :
          if(~spi_active)
            state <= S_IDLE;
        else
          state <= S_MODE;
        S_MODE :
          if(~spi_active)
            state <= S_IDLE;
        else if (rd_nwr)
          state <= S_READ;
        else if (~rd_nwr)
          state <= S_WAIT;
        else
          state <= S_MODE;
        S_READ :
          if(~spi_active)
            state <= S_IDLE;
        else if (ack)
          state <= S_WAIT;
        else
          state <= S_WAIT_ACK_RD;
        S_WAIT :
          if(~spi_active)
            state <= S_IDLE;
        else if (data_enable & ~rd_nwr)
          state <= S_WRITE;
        else if (data_enable)
          state <= S_MODE;
        else
          state <= S_WAIT;
        S_WRITE :
          if(~spi_active)
            state <= S_IDLE;
        else
          state <= S_WAIT_ACK_WR;
        S_WAIT_ACK_RD :
          if(~spi_active)
            state <= S_IDLE;
        else if(ack & rd_nwr)
          state <= S_ADDR_INC;
        else
          state <= S_WAIT_ACK_RD;
        S_WAIT_ACK_WR :
          if(~spi_active)
            state <= S_IDLE;
        else if(ack & ~rd_nwr)
          state <= S_ADDR_INC;
        else
          state <= S_WAIT_ACK_WR;
        S_ADDR_INC :
          if(~spi_active)
            state <= S_IDLE;
        else if(rd_nwr)
          state <= S_WAIT;
        else if(~rd_nwr)
          state <= S_MODE;
        else
          state <= S_IDLE;
        default :
          state <= S_IDLE;
      endcase
    end
  end

  always @(state) begin
    case(state)
      S_IDLE :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b0,1'b0,1'b0};
      S_ADDRES :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b1,1'b0,1'b0,1'b0,1'b0};
      S_MODE :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b0,1'b0,1'b0};
      S_READ :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b1,1'b1,1'b0};
      S_WRITE :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b1,1'b0,1'b1,1'b0};
      S_WAIT_ACK_RD :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b1,1'b1,1'b0};
      S_WAIT_ACK_WR :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b1,1'b0,1'b1,1'b0};
      S_WAIT :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b0,1'b0,1'b0};
      S_ADDR_INC :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b0,1'b0,1'b1};
      default :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b0,1'b0,1'b0};
    endcase
  end

  reg rd_nwr;

  always @(posedge clk or posedge resetn) begin
    if (resetn | ~spi_active) begin
      addr_bus <= 0;
      rd_nwr   <= 0;
    end
    else begin
      if(addr_enable) begin
        addr_bus <= data_bus_r[DATA_WIDTH-1:1];
        rd_nwr   <= data_bus_r[0];
      end else if(addr_inc)
        addr_bus <= addr_bus + 1;
      else begin
        rd_nwr   <= rd_nwr;
        addr_bus <= addr_bus;
      end
    end
  end

endmodule
module wb_spi_slave #(
  parameter ADDR_WIDTH = "mandatory",
  parameter DATA_WIDTH = "mandatory"
) (
  input  clk,
  input  resetn,

  input  mosi,
  input  ss,
  input  sck,
  output miso,

  input ack,
  output [DATA_WIDTH-1:0] data_bus_r,
  input  [DATA_WIDTH-1:0] data_bus_w,
  output reg [ADDR_WIDTH-1:0] addr_bus,
  output reg wr,
  output reg strobe,
  output cycle
);


  spi_slave #(.DATA_WIDTH(DATA_WIDTH)) spi0 (
    .clk            (clk                                         ),
    .resetn         (resetn                                      ),
    
    .mosi           (mosi                                        ),
    .ss             (ss                                          ),
    .sck            (sck                                         ),
    .miso           (miso                                        ),
    
    .data_bus_r     ({data_bus_r[7:0],data_bus_r[DATA_WIDTH-1:8]}),
    .data_bus_w     ({data_bus_w[7:0],data_bus_w[DATA_WIDTH-1:8]}),
    
    .data_enable    (data_enable                                 ),
    .SSEL_active(spi_active                                  ),
    .load_data_miso (ack                                         )
  );

  reg [3:0] state;
  reg rd,addr_enable,addr_inc;
  assign cycle = strobe;

  localparam [3:0] S_IDLE        = 4'd0;
  localparam [3:0] S_ADDRES      = 4'd1;
  localparam [3:0] S_MODE        = 4'd2;
  localparam [3:0] S_WRITE       = 4'd3;
  localparam [3:0] S_READ        = 4'd4;
  localparam [3:0] S_WAIT        = 4'd5;
  localparam [3:0] S_WAIT_ACK_RD = 4'd6;
  localparam [3:0] S_WAIT_ACK_WR = 4'd7;
  localparam [3:0] S_ADDR_INC    = 4'd8;

  always @(posedge clk or posedge resetn) begin
    if(resetn)
      state <= S_IDLE;
    else begin
      case(state)
        S_IDLE :
          if(data_enable)
            state <= S_ADDRES;
        else
          state <= S_IDLE;
        S_ADDRES :
          if(~spi_active)
            state <= S_IDLE;
        else
          state <= S_MODE;
        S_MODE :
          if(~spi_active)
            state <= S_IDLE;
        else if (rd_nwr)
          state <= S_READ;
        else if (~rd_nwr)
          state <= S_WAIT;
        else
          state <= S_MODE;
        S_READ :
          if(~spi_active)
            state <= S_IDLE;
        else if (ack)
          state <= S_WAIT;
        else
          state <= S_WAIT_ACK_RD;
        S_WAIT :
          if(~spi_active)
            state <= S_IDLE;
        else if (data_enable & ~rd_nwr)
          state <= S_WRITE;
        else if (data_enable)
          state <= S_MODE;
        else
          state <= S_WAIT;
        S_WRITE :
          if(~spi_active)
            state <= S_IDLE;
        else
          state <= S_WAIT_ACK_WR;
        S_WAIT_ACK_RD :
          if(~spi_active)
            state <= S_IDLE;
        else if(ack & rd_nwr)
          state <= S_ADDR_INC;
        else
          state <= S_WAIT_ACK_RD;
        S_WAIT_ACK_WR :
          if(~spi_active)
            state <= S_IDLE;
        else if(ack & ~rd_nwr)
          state <= S_ADDR_INC;
        else
          state <= S_WAIT_ACK_WR;
        S_ADDR_INC :
          if(~spi_active)
            state <= S_IDLE;
        else if(rd_nwr)
          state <= S_WAIT;
        else if(~rd_nwr)
          state <= S_MODE;
        else
          state <= S_IDLE;
        default :
          state <= S_IDLE;
      endcase
    end
  end

  always @(state) begin
    case(state)
      S_IDLE :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b0,1'b0,1'b0};
      S_ADDRES :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b1,1'b0,1'b0,1'b0,1'b0};
      S_MODE :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b0,1'b0,1'b0};
      S_READ :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b1,1'b1,1'b0};
      S_WRITE :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b1,1'b0,1'b1,1'b0};
      S_WAIT_ACK_RD :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b1,1'b1,1'b0};
      S_WAIT_ACK_WR :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b1,1'b0,1'b1,1'b0};
      S_WAIT :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b0,1'b0,1'b0};
      S_ADDR_INC :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b0,1'b0,1'b1};
      default :
        {addr_enable,wr,rd,strobe,addr_inc} = {1'b0,1'b0,1'b0,1'b0,1'b0};
    endcase
  end

  reg rd_nwr;

  always @(posedge clk or posedge resetn) begin
    if (resetn | ~spi_active) begin
      addr_bus <= 0;
      rd_nwr   <= 0;
    end
    else begin
      if(addr_enable) begin
        addr_bus <= data_bus_r[DATA_WIDTH-1:1];
        rd_nwr   <= data_bus_r[0];
      end else if(addr_inc)
        addr_bus <= addr_bus + 1;
      else begin
        rd_nwr   <= rd_nwr;
        addr_bus <= addr_bus;
      end
    end
  end

endmodule