data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:67: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h1\' generates 16 bits.\n                                                                                  : ... In instance arbiter\n        program_counter <= 16\'d1;\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:68: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h3\' generates 16 bits.\n                                                                                  : ... In instance arbiter\n        program_counter <= 16\'d3;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:74: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h3\' generates 16 bits.\n                                                                                  : ... In instance arbiter\n        program_counter <= 16\'d3;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:80: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h2\' generates 16 bits.\n                                                                                  : ... In instance arbiter\n        program_counter <= 16\'d2;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:87: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h6\' generates 16 bits.\n                                                                                  : ... In instance arbiter\n        program_counter <= 16\'d6;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:94: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h7\' generates 16 bits.\n                                                                                  : ... In instance arbiter\n        program_counter <= 16\'d7;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:97: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                  : ... In instance arbiter\n        s_input_a_ack <= 1\'b1;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:99: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                  : ... In instance arbiter\n          s_input_a_ack <= 1\'b0;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:100: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h7\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n          program_counter <= 16\'d7;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:98: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                  : ... In instance arbiter\n       if (s_input_a_ack == 1\'b1 && input_a_stb == 1\'b1) begin\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:106: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= 16\'d5;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:109: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                   : ... In instance arbiter\n        s_output_z_stb <= 1\'b1;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:111: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance arbiter\n          s_output_z_stb <= 1\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:110: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                   : ... In instance arbiter\n        if (s_output_z_stb == 1\'b1 && output_z_ack == 1\'b1) begin\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:118: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h4\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= 16\'d4;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:119: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h4\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= 16\'d4;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:124: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hc\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= 16\'d12;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:131: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hd\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= 16\'d13;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:138: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hf\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= 16\'d15;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:141: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                   : ... In instance arbiter\n        s_input_b_ack <= 1\'b1;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:143: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance arbiter\n          s_input_b_ack <= 1\'b0;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:144: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hf\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n          program_counter <= 16\'d15;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:142: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                   : ... In instance arbiter\n       if (s_input_b_ack == 1\'b1 && input_b_stb == 1\'b1) begin\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:150: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'he\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= 16\'d14;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:153: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                   : ... In instance arbiter\n        s_output_z_stb <= 1\'b1;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:155: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance arbiter\n          s_output_z_stb <= 1\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:154: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                   : ... In instance arbiter\n        if (s_output_z_stb == 1\'b1 && output_z_ack == 1\'b1) begin\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:162: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'ha\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= 16\'d10;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:163: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'ha\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= 16\'d10;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:168: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hb\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= 16\'d11;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:169: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h3\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= 16\'d3;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:174: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h9\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= 16\'d9;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:175: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'register_0\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n        program_counter <= register_0;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:63: Operator CASE expects 16 bits on the Case expression, but Case expression\'s VARREF \'program_counter\' generates 4 bits.\n                                                                                  : ... In instance arbiter\n    case(program_counter)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:186: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_input_a_ack\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n  assign input_a_ack = s_input_a_ack;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:187: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_input_b_ack\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n  assign input_b_ack = s_input_b_ack;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/21918161/chips2/test_suite/arbiter.v:188: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_output_z_stb\' generates 16 bits.\n                                                                                   : ... In instance arbiter\n  assign output_z_stb = s_output_z_stb;\n                      ^\n%Error: Exiting due to 37 warning(s)\n'
module arbiter(input_a,input_b,input_a_stb,input_b_stb,output_z_ack,clk,rst,output_z,output_z_stb,input_a_ack,input_b_ack);
  integer file_count;
  input     [15:0] input_a;
  input     [15:0] input_b;
  input     input_a_stb;
  input     input_b_stb;
  input     output_z_ack;
  input     clk;
  input     rst;
  output    [15:0] output_z;
  output    output_z_stb;
  output    input_a_ack;
  output    input_b_ack;
  reg       [15:0] timer;
  reg       [3:0] program_counter;
  reg       [15:0] address_2;
  reg       [15:0] data_out_2;
  reg       [15:0] data_in_2;
  reg       write_enable_2;
  reg       [15:0] address_4;
  reg       [31:0] data_out_4;
  reg       [31:0] data_in_4;
  reg       write_enable_4;
  reg       [15:0] register_0;
  reg       [15:0] register_1;
  reg       [15:0] s_output_z_stb;
  reg       [15:0] s_output_z;
  reg       [15:0] s_input_a_ack;
  reg       [15:0] s_input_b_ack;









  
  always @(posedge clk)
  begin


    timer <= 16'h0000;

    case(program_counter)

      16'd0:
      begin
        program_counter <= 16'd1;
        program_counter <= 16'd3;
        register_0 <= 16'd1;
      end

      16'd1:
      begin
        program_counter <= 16'd3;
        program_counter <= program_counter;
      end

      16'd3:
      begin
        program_counter <= 16'd2;
        register_1 <= 0;
        register_1[0] <= input_a_stb;
      end

      16'd2:
      begin
        program_counter <= 16'd6;
        if (register_1 == 0)
          program_counter <= 4;
      end

      16'd6:
      begin
        program_counter <= 16'd7;
        register_1 <= input_a;
        program_counter <= 6;
        s_input_a_ack <= 1'b1;
       if (s_input_a_ack == 1'b1 && input_a_stb == 1'b1) begin
          s_input_a_ack <= 1'b0;
          program_counter <= 16'd7;
        end
      end

      16'd7:
      begin
        program_counter <= 16'd5;
        s_output_z <= register_1;
        program_counter <= 7;
        s_output_z_stb <= 1'b1;
        if (s_output_z_stb == 1'b1 && output_z_ack == 1'b1) begin
          s_output_z_stb <= 1'b0;
          program_counter <= 5;
        end
      end

      16'd5:
      begin
        program_counter <= 16'd4;
        program_counter <= 16'd4;
      end

      16'd4:
      begin
        program_counter <= 16'd12;
        register_1 <= 0;
        register_1[0] <= input_b_stb;
      end

      16'd12:
      begin
        program_counter <= 16'd13;
        if (register_1 == 0)
          program_counter <= 10;
      end

      16'd13:
      begin
        program_counter <= 16'd15;
        register_1 <= input_b;
        program_counter <= 13;
        s_input_b_ack <= 1'b1;
       if (s_input_b_ack == 1'b1 && input_b_stb == 1'b1) begin
          s_input_b_ack <= 1'b0;
          program_counter <= 16'd15;
        end
      end

      16'd15:
      begin
        program_counter <= 16'd14;
        s_output_z <= register_1;
        program_counter <= 15;
        s_output_z_stb <= 1'b1;
        if (s_output_z_stb == 1'b1 && output_z_ack == 1'b1) begin
          s_output_z_stb <= 1'b0;
          program_counter <= 14;
        end
      end

      16'd14:
      begin
        program_counter <= 16'd10;
        program_counter <= 16'd10;
      end

      16'd10:
      begin
        program_counter <= 16'd11;
        program_counter <= 16'd3;
      end

      16'd11:
      begin
        program_counter <= 16'd9;
        program_counter <= register_0;
      end

    endcase
    if (rst == 1'b1) begin
      program_counter <= 0;
      s_input_a_ack <= 0;
      s_input_b_ack <= 0;
      s_output_z_stb <= 0;
    end
  end
  assign input_a_ack = s_input_a_ack;
  assign input_b_ack = s_input_b_ack;
  assign output_z_stb = s_output_z_stb;
  assign output_z = s_output_z;

endmodule
module arbiter(input_a,input_b,input_a_stb,input_b_stb,output_z_ack,clk,rst,output_z,output_z_stb,input_a_ack,input_b_ack);

  integer file_count;
  input     [15:0] input_a;
  input     [15:0] input_b;
  input     input_a_stb;
  input     input_b_stb;
  input     output_z_ack;
  input     clk;
  input     rst;
  output    [15:0] output_z;
  output    output_z_stb;
  output    input_a_ack;
  output    input_b_ack;
  reg       [15:0] timer;
  reg       [3:0] program_counter;
  reg       [15:0] address_2;
  reg       [15:0] data_out_2;
  reg       [15:0] data_in_2;
  reg       write_enable_2;
  reg       [15:0] address_4;
  reg       [31:0] data_out_4;
  reg       [31:0] data_in_4;
  reg       write_enable_4;
  reg       [15:0] register_0;
  reg       [15:0] register_1;
  reg       [15:0] s_output_z_stb;
  reg       [15:0] s_output_z;
  reg       [15:0] s_input_a_ack;
  reg       [15:0] s_input_b_ack;









  
  always @(posedge clk)
  begin


    timer <= 16'h0000;

    case(program_counter)

      16'd0:
      begin
        program_counter <= 16'd1;
        program_counter <= 16'd3;
        register_0 <= 16'd1;
      end

      16'd1:
      begin
        program_counter <= 16'd3;
        program_counter <= program_counter;
      end

      16'd3:
      begin
        program_counter <= 16'd2;
        register_1 <= 0;
        register_1[0] <= input_a_stb;
      end

      16'd2:
      begin
        program_counter <= 16'd6;
        if (register_1 == 0)
          program_counter <= 4;
      end

      16'd6:
      begin
        program_counter <= 16'd7;
        register_1 <= input_a;
        program_counter <= 6;
        s_input_a_ack <= 1'b1;
       if (s_input_a_ack == 1'b1 && input_a_stb == 1'b1) begin
          s_input_a_ack <= 1'b0;
          program_counter <= 16'd7;
        end
      end

      16'd7:
      begin
        program_counter <= 16'd5;
        s_output_z <= register_1;
        program_counter <= 7;
        s_output_z_stb <= 1'b1;
        if (s_output_z_stb == 1'b1 && output_z_ack == 1'b1) begin
          s_output_z_stb <= 1'b0;
          program_counter <= 5;
        end
      end

      16'd5:
      begin
        program_counter <= 16'd4;
        program_counter <= 16'd4;
      end

      16'd4:
      begin
        program_counter <= 16'd12;
        register_1 <= 0;
        register_1[0] <= input_b_stb;
      end

      16'd12:
      begin
        program_counter <= 16'd13;
        if (register_1 == 0)
          program_counter <= 10;
      end

      16'd13:
      begin
        program_counter <= 16'd15;
        register_1 <= input_b;
        program_counter <= 13;
        s_input_b_ack <= 1'b1;
       if (s_input_b_ack == 1'b1 && input_b_stb == 1'b1) begin
          s_input_b_ack <= 1'b0;
          program_counter <= 16'd15;
        end
      end

      16'd15:
      begin
        program_counter <= 16'd14;
        s_output_z <= register_1;
        program_counter <= 15;
        s_output_z_stb <= 1'b1;
        if (s_output_z_stb == 1'b1 && output_z_ack == 1'b1) begin
          s_output_z_stb <= 1'b0;
          program_counter <= 14;
        end
      end

      16'd14:
      begin
        program_counter <= 16'd10;
        program_counter <= 16'd10;
      end

      16'd10:
      begin
        program_counter <= 16'd11;
        program_counter <= 16'd3;
      end

      16'd11:
      begin
        program_counter <= 16'd9;
        program_counter <= register_0;
      end

    endcase
    if (rst == 1'b1) begin
      program_counter <= 0;
      s_input_a_ack <= 0;
      s_input_b_ack <= 0;
      s_output_z_stb <= 0;
    end
  end
  assign input_a_ack = s_input_a_ack;
  assign input_b_ack = s_input_b_ack;
  assign output_z_stb = s_output_z_stb;
  assign output_z = s_output_z;

endmodule