data/full_repos/permissive/143278/ivltests/uncon_drive.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/uncon_drive.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/uncon_drive.v:17: Unsupported: Ignoring delay on this delayed statement.\n  initial #1 if (in !== 1\'bz) begin\n          ^\n%Error: data/full_repos/permissive/143278/ivltests/uncon_drive.v:23: Define or directive not defined: \'`unconnected_drive\'\n                                                                   : ... Suggested alternative: \'`nounconnected_drive\'\n`unconnected_drive pull0\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/uncon_drive.v:23: syntax error, unexpected STRENGTH keyword (strong1/etc)\n`unconnected_drive pull0\n                   ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/uncon_drive.v:26: Unsupported: Ignoring delay on this delayed statement.\n  initial #1 if (in !== 1\'b0) begin\n          ^\n%Error: data/full_repos/permissive/143278/ivltests/uncon_drive.v:33: Define or directive not defined: \'`unconnected_drive\'\n                                                                   : ... Suggested alternative: \'`nounconnected_drive\'\n`unconnected_drive pull1\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/uncon_drive.v:33: syntax error, unexpected STRENGTH keyword (strong1/etc)\n`unconnected_drive pull1\n                   ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/uncon_drive.v:36: Unsupported: Ignoring delay on this delayed statement.\n  initial #1 if (in !== 1\'b1) begin\n          ^\n%Error: Exiting due to 4 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass;

  highz dutz();
  pulllow dut0();
  pullhigh dut1();

  initial begin
    pass = 1'b1;
    #10;
    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;

  highz dutz();
  pulllow dut0();
  pullhigh dut1();

  initial begin
    pass = 1'b1;
    #10;
    if (pass) $display("PASSED");
  end
endmodule