data/full_repos/permissive/160156109/mips-work/mips.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160156109/mips-work/mips.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #5 reset = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160156109/mips-work/mips.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #5 reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160156109/mips-work/mips.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #20 clk =~ clk;\n    ^\n%Error: data/full_repos/permissive/160156109/mips-work/mips.v:12: Cannot find file containing module: \'ifu\'\n  ifu ifu1(clk, reset, nPC_sel, zero, ins, jumpCtr, tarAddr);\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/160156109/mips-work,data/full_repos/permissive/160156109/ifu\n             data/full_repos/permissive/160156109/mips-work,data/full_repos/permissive/160156109/ifu.v\n             data/full_repos/permissive/160156109/mips-work,data/full_repos/permissive/160156109/ifu.sv\n             ifu\n             ifu.v\n             ifu.sv\n             obj_dir/ifu\n             obj_dir/ifu.v\n             obj_dir/ifu.sv\n%Error: data/full_repos/permissive/160156109/mips-work/mips.v:14: Cannot find file containing module: \'ctrl\'\n  ctrl ctrl1(ins, nPC_sel, RegWr, RegDst, ExtOp, ALUSrc, ALUctr, MemWr, MemtoReg, jumpCtr, rs, rt, rd, tarAddr, imm16);\n  ^~~~\n%Error: data/full_repos/permissive/160156109/mips-work/mips.v:16: Cannot find file containing module: \'regfile\'\n  regfile regfile1(clk, reset, busw, RegWr, rs, rt, rw, busa, busb, RegDst, rd);\n  ^~~~~~~\n%Error: data/full_repos/permissive/160156109/mips-work/mips.v:17: Cannot find file containing module: \'extender\'\n  extender extender1(imm16, dout1, ExtOp);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/160156109/mips-work/mips.v:19: Cannot find file containing module: \'mux\'\n  mux mux1(dout1, busb, dout2, ALUSrc);\n  ^~~\n%Error: data/full_repos/permissive/160156109/mips-work/mips.v:21: Cannot find file containing module: \'alu\'\n  alu alu1(ALUctr, busa, dout2, zero, dout3);\n  ^~~\n%Error: data/full_repos/permissive/160156109/mips-work/mips.v:22: Cannot find file containing module: \'dm\'\n  dm dm1(clk, reset, dout3, busb, dout4, MemWr);\n  ^~\n%Error: data/full_repos/permissive/160156109/mips-work/mips.v:24: Cannot find file containing module: \'mux\'\n  mux mux2(dout4, dout3, busw, MemtoReg);\n  ^~~\n%Error: Exiting due to 8 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips;
  reg clk, reset;

  wire [31:0] ins, busw, busa, busb, dout1, dout2, dout3, dout4;
  wire [25:0] tarAddr;
  wire [15:0] imm16;
  wire [4:0] rs, rt, rw, rd;
  wire [3:0] ALUctr;
  wire nPC_sel, RegWr, RegDst, ExtOp, ALUSrc, MemWr, MemtoReg, jumpCtr, zero;
  

  ifu ifu1(clk, reset, nPC_sel, zero, ins, jumpCtr, tarAddr);

  ctrl ctrl1(ins, nPC_sel, RegWr, RegDst, ExtOp, ALUSrc, ALUctr, MemWr, MemtoReg, jumpCtr, rs, rt, rd, tarAddr, imm16);

  regfile regfile1(clk, reset, busw, RegWr, rs, rt, rw, busa, busb, RegDst, rd);
  extender extender1(imm16, dout1, ExtOp);

  mux mux1(dout1, busb, dout2, ALUSrc);

  alu alu1(ALUctr, busa, dout2, zero, dout3);
  dm dm1(clk, reset, dout3, busb, dout4, MemWr);

  mux mux2(dout4, dout3, busw, MemtoReg);


  initial
  begin
    clk = 0;
    #5 reset = 1;
    #5 reset = 0;
  end

  always
    #20 clk =~ clk;

  
endmodule
module mips;

  reg clk, reset;

  wire [31:0] ins, busw, busa, busb, dout1, dout2, dout3, dout4;
  wire [25:0] tarAddr;
  wire [15:0] imm16;
  wire [4:0] rs, rt, rw, rd;
  wire [3:0] ALUctr;
  wire nPC_sel, RegWr, RegDst, ExtOp, ALUSrc, MemWr, MemtoReg, jumpCtr, zero;
  

  ifu ifu1(clk, reset, nPC_sel, zero, ins, jumpCtr, tarAddr);

  ctrl ctrl1(ins, nPC_sel, RegWr, RegDst, ExtOp, ALUSrc, ALUctr, MemWr, MemtoReg, jumpCtr, rs, rt, rd, tarAddr, imm16);

  regfile regfile1(clk, reset, busw, RegWr, rs, rt, rw, busa, busb, RegDst, rd);
  extender extender1(imm16, dout1, ExtOp);

  mux mux1(dout1, busb, dout2, ALUSrc);

  alu alu1(ALUctr, busa, dout2, zero, dout3);
  dm dm1(clk, reset, dout3, busb, dout4, MemWr);

  mux mux2(dout4, dout3, busw, MemtoReg);


  initial
  begin
    clk = 0;
    #5 reset = 1;
    #5 reset = 0;
  end

  always
    #20 clk =~ clk;

  
endmodule