data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/rf.v
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data/verilator_xmls/3daa17e5-09ad-4e7f-9656-0847df8e92d6.xml
module rf(
    input wire[4:0] rf_r1_address,
    input wire[4:0] rf_r2_address,
    input wire[4:0] rf_w_address,
    input wire[31:0] rf_w_data,
    input wire rf_we,
    input wire clk,

    output wire[31:0] rf_r1_data,
    output wire[31:0] rf_r2_data
    );


    reg[31:0] gpr[31:0];
    

    assign rf_r1_data = (rf_r1_address == 0) ? 32'h0000_0000 : gpr[rf_r1_address];
    assign rf_r2_data = (rf_r2_address == 0) ? 32'h0000_0000 : gpr[rf_r2_address];


    always @ (posedge clk) begin
        if (rf_we) begin
            gpr[rf_w_address] <= rf_w_data;
        end
    end
endmodule
module rf(
    input wire[4:0] rf_r1_address,
    input wire[4:0] rf_r2_address,
    input wire[4:0] rf_w_address,
    input wire[31:0] rf_w_data,
    input wire rf_we,
    input wire clk,

    output wire[31:0] rf_r1_data,
    output wire[31:0] rf_r2_data
    );



    reg[31:0] gpr[31:0];
    

    assign rf_r1_data = (rf_r1_address == 0) ? 32'h0000_0000 : gpr[rf_r1_address];
    assign rf_r2_data = (rf_r2_address == 0) ? 32'h0000_0000 : gpr[rf_r2_address];


    always @ (posedge clk) begin
        if (rf_we) begin
            gpr[rf_w_address] <= rf_w_data;
        end
    end
endmodule