data/full_repos/permissive/105152503/core/uart_test.v
 line:47: before: ";"
1: b'%Error: data/full_repos/permissive/105152503/core/uart_test.v:6: Cannot find include file: uart.v\n`include "uart.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105152503/core,data/full_repos/permissive/105152503/uart.v\n             data/full_repos/permissive/105152503/core,data/full_repos/permissive/105152503/uart.v.v\n             data/full_repos/permissive/105152503/core,data/full_repos/permissive/105152503/uart.v.sv\n             uart.v\n             uart.v.v\n             uart.v.sv\n             obj_dir/uart.v\n             obj_dir/uart.v.v\n             obj_dir/uart.v.sv\n%Error: data/full_repos/permissive/105152503/core/uart_test.v:18: Unsupported or unknown PLI call: $monitor\n  $monitor("%4g %1b %1b %10b %5b %10b %1b", $time, clk, tx_ready, ctr, stage, tx_data, tx);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/uart_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #5     rst= 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/uart_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #10    rst= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/uart_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #100   tx_en= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/uart_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #105   tx_data= 8\'hf;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/uart_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #1000  $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/uart_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk=~ clk;\n  ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n'
module uart_test();
	
	reg clk, rst, tx_en;
	reg [7:0] tx_data;
	wire tx_ready;
	wire tx;
	wire [10:0] ctr;
	wire [ 4:0] stage;

	initial begin
		$monitor("%4g %1b %1b %10b %5b %10b %1b", $time, clk, tx_ready, ctr, stage, tx_data, tx);
		clk= 1;
		rst= 0;
		tx_en= 0;
		tx_data= 8'b01010101;
		#5     rst= 1;
		#10    rst= 0;
		#100   tx_en= 1;
		#105   tx_data= 8'hf;
		#1000  $finish;
	end

	always begin
		#5 clk=~ clk;
	end

	uart #(.BAUD_THRESHOLD(4)) u0(
		.clk(clk),
		.rst(rst),
		.tx_data(tx_data),
		.tx_en(tx_en),
		.tx(tx),
		.tx_ready(tx_ready),
		.ctr(ctr),
		.stage(stage)
		);
endmodule
module uart_test();

	
	reg clk, rst, tx_en;
	reg [7:0] tx_data;
	wire tx_ready;
	wire tx;
	wire [10:0] ctr;
	wire [ 4:0] stage;

	initial begin
		$monitor("%4g %1b %1b %10b %5b %10b %1b", $time, clk, tx_ready, ctr, stage, tx_data, tx);
		clk= 1;
		rst= 0;
		tx_en= 0;
		tx_data= 8'b01010101;
		#5     rst= 1;
		#10    rst= 0;
		#100   tx_en= 1;
		#105   tx_data= 8'hf;
		#1000  $finish;
	end

	always begin
		#5 clk=~ clk;
	end

	uart #(.BAUD_THRESHOLD(4)) u0(
		.clk(clk),
		.rst(rst),
		.tx_data(tx_data),
		.tx_en(tx_en),
		.tx(tx),
		.tx_ready(tx_ready),
		.ctr(ctr),
		.stage(stage)
		);
endmodule