data/full_repos/permissive/169294490/FPGA/src/main.sv
1: b"%Error: data/full_repos/permissive/169294490/FPGA/src/main.sv:79: Cannot find file containing module: 'hex_bus_display'\nhex_bus_display hex_bus_display_instance_0 (\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169294490/FPGA/src,data/full_repos/permissive/169294490/hex_bus_display\n             data/full_repos/permissive/169294490/FPGA/src,data/full_repos/permissive/169294490/hex_bus_display.v\n             data/full_repos/permissive/169294490/FPGA/src,data/full_repos/permissive/169294490/hex_bus_display.sv\n             hex_bus_display\n             hex_bus_display.v\n             hex_bus_display.sv\n             obj_dir/hex_bus_display\n             obj_dir/hex_bus_display.v\n             obj_dir/hex_bus_display.sv\n%Error: data/full_repos/permissive/169294490/FPGA/src/main.sv:85: Cannot find file containing module: 'hex_bus_display'\nhex_bus_display hex_bus_display_instance_1 (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169294490/FPGA/src/main.sv:91: Cannot find file containing module: 'hex_bus_display'\nhex_bus_display hex_bus_display_instance_2 (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169294490/FPGA/src/main.sv:97: Cannot find file containing module: 'hex_bus_display'\nhex_bus_display hex_bus_display_instance_3 (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169294490/FPGA/src/main.sv:103: Cannot find file containing module: 'hex_bus_display'\nhex_bus_display hex_bus_display_instance_4 (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169294490/FPGA/src/main.sv:109: Cannot find file containing module: 'hex_bus_display'\nhex_bus_display hex_bus_display_instance_5 (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169294490/FPGA/src/main.sv:127: Cannot find file containing module: 'vga_controller'\nvga_controller vga_controller_instance (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169294490/FPGA/src/main.sv:151: Cannot find file containing module: 'counter'\ncounter counter_instance_debug_clock (\n^~~~~~~\n%Error: data/full_repos/permissive/169294490/FPGA/src/main.sv:175: Cannot find file containing module: 'PS2_Controller'\nPS2_Controller ps2_instance (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169294490/FPGA/src/main.sv:206: Cannot find file containing module: 'cpu'\ncpu cpu_instance (\n^~~\n%Error: Exiting due to 10 error(s)\n"
module main (

	input 		          		ADC_CLK_10,
	input 		          		MAX10_CLK1_50,
	input 		          		MAX10_CLK2_50,


	output		    [12:0]		DRAM_ADDR,
	output		     [1:0]		DRAM_BA,
	output		          		DRAM_CAS_N,
	output		          		DRAM_CKE,
	output		          		DRAM_CLK,
	output		          		DRAM_CS_N,
	inout 		    [15:0]		DRAM_DQ,
	output		          		DRAM_LDQM,
	output		          		DRAM_RAS_N,
	output		          		DRAM_UDQM,
	output		          		DRAM_WE_N,


	output		     [7:0]		HEX0,
	output		     [7:0]		HEX1,
	output		     [7:0]		HEX2,
	output		     [7:0]		HEX3,
	output		     [7:0]		HEX4,
	output		     [7:0]		HEX5,


	input 		     [1:0]		KEY,


	output		     [9:0]		LEDR,


	input 		     [9:0]		SW,


	output		     [3:0]		VGA_B,
	output		     [3:0]		VGA_G,
	output		          		VGA_HS,
	output		     [3:0]		VGA_R,
	output		          		VGA_VS,


	output		          		GSENSOR_CS_N,
	input 		     [2:1]		GSENSOR_INT,
	output		          		GSENSOR_SCLK,
	inout 		          		GSENSOR_SDI,
	inout 		          		GSENSOR_SDO,


	inout 		    [15:0]		ARDUINO_IO,
	inout			[35:0]		GPIO,
	inout						CLK_I2C_SCL,
	inout						CLK_I2C_SDA,
	inout 		          		ARDUINO_RESET_N
);



reg [32:0] PWR_RST = 0;
always @(posedge MAX10_CLK1_50) begin
	if (rstReq) begin
		PWR_RST <= 0;
	end else if (!PWR_RST[25]) begin
		PWR_RST <= PWR_RST + 1'b1;
	end
end



wire RST;
assign RST = (RST & core_clock) | (~PWR_RST[25]) | (~KEY[0]);



hex_bus_display hex_bus_display_instance_0 (
	.bus(debug_bus[0 +: 4]),
	.hex_port(HEX0),
	.comma(1'h1)
);

hex_bus_display hex_bus_display_instance_1 (
	.bus(debug_bus[4 +: 4]),
	.hex_port(HEX1),
	.comma(1'h1)
);

hex_bus_display hex_bus_display_instance_2 (
	.bus(debug_bus[8 +: 4]),
	.hex_port(HEX2),
	.comma(1'h1)
);

hex_bus_display hex_bus_display_instance_3 (
	.bus(debug_bus[12 +: 4]),
	.hex_port(HEX3),
	.comma(1'h1)
);

hex_bus_display hex_bus_display_instance_4 (
	.bus(irq_count[0 +: 4]),
	.hex_port(HEX4),
	.comma(1'h0)
);

hex_bus_display hex_bus_display_instance_5 (
	.bus(irq_count[4 +: 4]),
	.hex_port(HEX5),
	.comma(1'h1)
);




wire [7:0] fb_data_bus;
wire [11:0] fb_addr_bus;
wire fb_we;
wire [11:0] framebuffer_addr_rd;
wire [7:0] framebuffer_data_rd;
wire framebuffer_rd_en;



vga_controller vga_controller_instance (
	.clk50(MAX10_CLK1_50),
	.rst(RST),
	.hsync_out(VGA_HS),
	.vsync_out(VGA_VS),
	.red_out(VGA_R),
	.blue_out(VGA_B),
	.green_out(VGA_G),
	.fb_data(fb_data_bus),
	.fb_addr(fb_addr_bus),
	.fb_we(fb_we),
	.framebuffer_addr_rd(framebuffer_addr_rd),
	.framebuffer_data_rd(framebuffer_data_rd),
	.framebuffer_rd_en(framebuffer_rd_en)
);



reg manual_clock;
always @(*) begin
	manual_clock <= !KEY[1];
end

wire [31:0] debug_clock;
counter counter_instance_debug_clock (
	.clk(MAX10_CLK1_50),
	.reset(),
	.enable(1'b1),
	.out(debug_clock)
);

wire core_clock_fast = debug_clock[1];
wire core_clock;
wire clkbreak_act = clkbreak && !RST;

always @(posedge core_clock_fast) begin
	if (SW[0] && !clkbreak_act) begin
		core_clock <= ~core_clock;
	end else if (debug_clock[1]) begin
		core_clock <= manual_clock;
	end
end



wire [7:0] ps2_data;
wire ps2_data_en;

PS2_Controller ps2_instance (

	.CLOCK_50(MAX10_CLK1_50),
	.reset(|PWR_RST[23:0]),

	.the_command(16'hFF),
	.send_command(RST),


	.PS2_CLK(ARDUINO_IO[6]),
 	.PS2_DAT(ARDUINO_IO[7]),


	.command_was_sent(a),
	.error_communication_timed_out(b),

	.received_data(ps2_data),
	.received_data_en(ps2_data_en)
);

wire a, b;




wire [15:0] debug_bus;
wire [7:0] irq_count;
wire debugEn;
wire rstReq;
wire clkbreak;

cpu cpu_instance (
	.clkCore(core_clock),
	.clk50(MAX10_CLK1_50),
	.rst(RST),
	
	.DRAM_ADDR(DRAM_ADDR),
	.DRAM_BA(DRAM_BA),
	.DRAM_CAS_N(DRAM_CAS_N),
	.DRAM_CKE(DRAM_CKE),
	.DRAM_CLK(DRAM_CLK),
	.DRAM_CS_N(DRAM_CS_N),
	.DRAM_DQ(DRAM_DQ),
	.DRAM_LDQM(DRAM_LDQM),
	.DRAM_RAS_N(DRAM_RAS_N),
	.DRAM_UDQM(DRAM_UDQM),
	.DRAM_WE_N(DRAM_WE_N),

	.ps2_data(ps2_data),
	.ps2_data_en(ps2_data_en),
	
	.DEBUG_BUS(debug_bus),
	.LEDR(LEDR),
	.SW(SW),
	.irq_count(irq_count),

    .fb_data(fb_data_bus),
    .fb_addr(fb_addr_bus),
    .fb_we(fb_we),
	.framebuffer_rd_en(framebuffer_rd_en),
	.framebuffer_data_rd(framebuffer_data_rd),
	.framebuffer_addr_rd(framebuffer_addr_rd),

	.debugEnOut(debugEn),
	.rstReq(rstReq),
	.clkbreak(clkbreak),

	.ARDUINO_IO(ARDUINO_IO),
	.GPIO(GPIO)
);

endmodule
module main (

	input 		          		ADC_CLK_10,
	input 		          		MAX10_CLK1_50,
	input 		          		MAX10_CLK2_50,


	output		    [12:0]		DRAM_ADDR,
	output		     [1:0]		DRAM_BA,
	output		          		DRAM_CAS_N,
	output		          		DRAM_CKE,
	output		          		DRAM_CLK,
	output		          		DRAM_CS_N,
	inout 		    [15:0]		DRAM_DQ,
	output		          		DRAM_LDQM,
	output		          		DRAM_RAS_N,
	output		          		DRAM_UDQM,
	output		          		DRAM_WE_N,


	output		     [7:0]		HEX0,
	output		     [7:0]		HEX1,
	output		     [7:0]		HEX2,
	output		     [7:0]		HEX3,
	output		     [7:0]		HEX4,
	output		     [7:0]		HEX5,


	input 		     [1:0]		KEY,


	output		     [9:0]		LEDR,


	input 		     [9:0]		SW,


	output		     [3:0]		VGA_B,
	output		     [3:0]		VGA_G,
	output		          		VGA_HS,
	output		     [3:0]		VGA_R,
	output		          		VGA_VS,


	output		          		GSENSOR_CS_N,
	input 		     [2:1]		GSENSOR_INT,
	output		          		GSENSOR_SCLK,
	inout 		          		GSENSOR_SDI,
	inout 		          		GSENSOR_SDO,


	inout 		    [15:0]		ARDUINO_IO,
	inout			[35:0]		GPIO,
	inout						CLK_I2C_SCL,
	inout						CLK_I2C_SDA,
	inout 		          		ARDUINO_RESET_N
);




reg [32:0] PWR_RST = 0;
always @(posedge MAX10_CLK1_50) begin
	if (rstReq) begin
		PWR_RST <= 0;
	end else if (!PWR_RST[25]) begin
		PWR_RST <= PWR_RST + 1'b1;
	end
end



wire RST;
assign RST = (RST & core_clock) | (~PWR_RST[25]) | (~KEY[0]);



hex_bus_display hex_bus_display_instance_0 (
	.bus(debug_bus[0 +: 4]),
	.hex_port(HEX0),
	.comma(1'h1)
);

hex_bus_display hex_bus_display_instance_1 (
	.bus(debug_bus[4 +: 4]),
	.hex_port(HEX1),
	.comma(1'h1)
);

hex_bus_display hex_bus_display_instance_2 (
	.bus(debug_bus[8 +: 4]),
	.hex_port(HEX2),
	.comma(1'h1)
);

hex_bus_display hex_bus_display_instance_3 (
	.bus(debug_bus[12 +: 4]),
	.hex_port(HEX3),
	.comma(1'h1)
);

hex_bus_display hex_bus_display_instance_4 (
	.bus(irq_count[0 +: 4]),
	.hex_port(HEX4),
	.comma(1'h0)
);

hex_bus_display hex_bus_display_instance_5 (
	.bus(irq_count[4 +: 4]),
	.hex_port(HEX5),
	.comma(1'h1)
);




wire [7:0] fb_data_bus;
wire [11:0] fb_addr_bus;
wire fb_we;
wire [11:0] framebuffer_addr_rd;
wire [7:0] framebuffer_data_rd;
wire framebuffer_rd_en;



vga_controller vga_controller_instance (
	.clk50(MAX10_CLK1_50),
	.rst(RST),
	.hsync_out(VGA_HS),
	.vsync_out(VGA_VS),
	.red_out(VGA_R),
	.blue_out(VGA_B),
	.green_out(VGA_G),
	.fb_data(fb_data_bus),
	.fb_addr(fb_addr_bus),
	.fb_we(fb_we),
	.framebuffer_addr_rd(framebuffer_addr_rd),
	.framebuffer_data_rd(framebuffer_data_rd),
	.framebuffer_rd_en(framebuffer_rd_en)
);



reg manual_clock;
always @(*) begin
	manual_clock <= !KEY[1];
end

wire [31:0] debug_clock;
counter counter_instance_debug_clock (
	.clk(MAX10_CLK1_50),
	.reset(),
	.enable(1'b1),
	.out(debug_clock)
);

wire core_clock_fast = debug_clock[1];
wire core_clock;
wire clkbreak_act = clkbreak && !RST;

always @(posedge core_clock_fast) begin
	if (SW[0] && !clkbreak_act) begin
		core_clock <= ~core_clock;
	end else if (debug_clock[1]) begin
		core_clock <= manual_clock;
	end
end



wire [7:0] ps2_data;
wire ps2_data_en;

PS2_Controller ps2_instance (

	.CLOCK_50(MAX10_CLK1_50),
	.reset(|PWR_RST[23:0]),

	.the_command(16'hFF),
	.send_command(RST),


	.PS2_CLK(ARDUINO_IO[6]),
 	.PS2_DAT(ARDUINO_IO[7]),


	.command_was_sent(a),
	.error_communication_timed_out(b),

	.received_data(ps2_data),
	.received_data_en(ps2_data_en)
);

wire a, b;




wire [15:0] debug_bus;
wire [7:0] irq_count;
wire debugEn;
wire rstReq;
wire clkbreak;

cpu cpu_instance (
	.clkCore(core_clock),
	.clk50(MAX10_CLK1_50),
	.rst(RST),
	
	.DRAM_ADDR(DRAM_ADDR),
	.DRAM_BA(DRAM_BA),
	.DRAM_CAS_N(DRAM_CAS_N),
	.DRAM_CKE(DRAM_CKE),
	.DRAM_CLK(DRAM_CLK),
	.DRAM_CS_N(DRAM_CS_N),
	.DRAM_DQ(DRAM_DQ),
	.DRAM_LDQM(DRAM_LDQM),
	.DRAM_RAS_N(DRAM_RAS_N),
	.DRAM_UDQM(DRAM_UDQM),
	.DRAM_WE_N(DRAM_WE_N),

	.ps2_data(ps2_data),
	.ps2_data_en(ps2_data_en),
	
	.DEBUG_BUS(debug_bus),
	.LEDR(LEDR),
	.SW(SW),
	.irq_count(irq_count),

    .fb_data(fb_data_bus),
    .fb_addr(fb_addr_bus),
    .fb_we(fb_we),
	.framebuffer_rd_en(framebuffer_rd_en),
	.framebuffer_data_rd(framebuffer_data_rd),
	.framebuffer_addr_rd(framebuffer_addr_rd),

	.debugEnOut(debugEn),
	.rstReq(rstReq),
	.clkbreak(clkbreak),

	.ARDUINO_IO(ARDUINO_IO),
	.GPIO(GPIO)
);

endmodule