data/full_repos/permissive/127217549/rtl/flipFlopNbit.v
 line:20: before: "("
data/verilator_xmls/e5fbf4a4-6574-40a3-8ac6-a1ffb0127cda.xml
module flipFlopNbit #(
		      parameter busWidth = 8
		    )
     (
      input [(busWidth - 1):0] D,
      input 			clk,
      input 			reset_n,
      output [(busWidth - 1):0] Q      
      );
   


	reg [(busWidth - 1):0] q = 0;
   assign Q = q;
   
  
  always @(posedge(clk), negedge(reset_n)) begin

     if(reset_n == 1'b0) begin
	q <= 0;
     end


     else if (clk == 1'b1) begin
	q <= D;
     end

     else begin
	q <= q;
     end
  end
   
  endmodule
module flipFlopNbit #(
		      parameter busWidth = 8
		    )
     (
      input [(busWidth - 1):0] D,
      input 			clk,
      input 			reset_n,
      output [(busWidth - 1):0] Q      
      );

   


	reg [(busWidth - 1):0] q = 0;
   assign Q = q;
   
  
  always @(posedge(clk), negedge(reset_n)) begin

     if(reset_n == 1'b0) begin
	q <= 0;
     end


     else if (clk == 1'b1) begin
	q <= D;
     end

     else begin
	q <= q;
     end
  end
   
  endmodule