data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v
None: at end of input
1: b'%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:22: Cannot find include file: opcode.h\n`include "opcode.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h\n             data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.v\n             data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.sv\n             opcode.h\n             opcode.h.v\n             opcode.h.sv\n             obj_dir/opcode.h\n             obj_dir/opcode.h.v\n             obj_dir/opcode.h.sv\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:39: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n input [`MEM_OPCODE_WIDTH-1:0] mem_opcode,\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LB\'\n   `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n   ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: syntax error, unexpected \',\', expecting endcase\n   `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n          ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LBU\'\n   `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LH\'\n   `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n                      ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LHU\'\n   `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n                               ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LW\'\n   `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n                                         ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:74: Define or directive not defined: \'`MEM_LH\'\n    if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2\'b11) \n                       ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:74: Define or directive not defined: \'`MEM_LHU\'\n    if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2\'b11) \n                                                ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:75: Define or directive not defined: \'`MEM_LW\'\n     || (mem_opcode == `MEM_LW && mem_src1[1:0] != 2\'b00)) begin\n                       ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:85: Define or directive not defined: \'`MEM_SB\'\n   `MEM_SB: begin\n   ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:85: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `MEM_SB: begin\n            ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:102: Define or directive not defined: \'`MEM_SH\'\n   `MEM_SH: begin\n   ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:102: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `MEM_SH: begin\n            ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:119: Define or directive not defined: \'`MEM_SW\'\n   `MEM_SW: begin\n   ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:119: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `MEM_SW: begin\n            ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:124: syntax error, unexpected else\n    end else begin\n        ^~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:136: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n reg [`MEM_OPCODE_WIDTH-1:0] buf_opcode;\n      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:189: Define or directive not defined: \'`MEM_NOP\'\n  if(buf_opcode == `MEM_NOP) begin\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:189: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if(buf_opcode == `MEM_NOP) begin\n                           ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:193: syntax error, unexpected else\n  end else if(mem_done) begin\n      ^~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:197: Define or directive not defined: \'`MEM_LB\'\n   `MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));\n   ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:197: syntax error, unexpected \':\', expecting endcase\n   `MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));\n          ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:198: Define or directive not defined: \'`MEM_LBU\'\n   `MEM_LBU: mem_output = {24\'b0, get_byte(buf_src1[1:0], read_data)};\n   ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:199: Define or directive not defined: \'`MEM_LH\'\n   `MEM_LH: mem_output = sext_half(get_half(buf_src1[1:0], read_data));\n   ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:200: Define or directive not defined: \'`MEM_LHU\'\n   `MEM_LHU: mem_output = {16\'b0, get_half(buf_src1[1:0], read_data)};\n   ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:201: Define or directive not defined: \'`MEM_LW\'\n   `MEM_LW: mem_output = read_data;\n   ^~~~~~~\n%Error: Cannot continue\n'
function [31:0] sext_half;
		input [15:0] in;
		sext_half = {{16{in[15]}}, in};
	endfunction
function [31:0] sext_half;

		input [15:0] in;
		sext_half = {{16{in[15]}}, in};
	endfunction