data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v
None: at end of input
1: b'%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:11: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/171607226/rtl/e203/redundant_core,data/full_repos/permissive/171607226/e203_defines.v\n             data/full_repos/permissive/171607226/rtl/e203/redundant_core,data/full_repos/permissive/171607226/e203_defines.v.v\n             data/full_repos/permissive/171607226/rtl/e203/redundant_core,data/full_repos/permissive/171607226/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:14: Define or directive not defined: \'`E203_PC_SIZE\'\n  output[`E203_PC_SIZE-1:0] inspect_pc,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:29: Define or directive not defined: \'`E203_PC_SIZE\'\n  input  [`E203_PC_SIZE-1:0] pc_rtvec,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:31: Define or directive not defined: \'`E203_HART_ID_W\'\n  input  [`E203_HART_ID_W-1:0] core_mhartid,\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:33: Define or directive not defined: \'`E203_LIRQ_NUM\'\n  input  [`E203_LIRQ_NUM-1:0] lcl_irq_r,\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:34: Define or directive not defined: \'`E203_EVT_NUM\'\n  input  [`E203_EVT_NUM-1:0] evt_r,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:50: Define or directive not defined: \'`E203_PC_SIZE\'\n  input  [`E203_PC_SIZE-1:0] dpc_r     ,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:53: Define or directive not defined: \'`E203_PC_SIZE\'\n  output  [`E203_PC_SIZE-1:0] cmt_dpc,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:92: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  input [`E203_ADDR_SIZE-1:0]    ppi_region_indic,\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:98: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  output [`E203_ADDR_SIZE-1:0]   ppi_icb_cmd_addr, \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:100: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0]        ppi_icb_cmd_wdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:101: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN/8-1:0]      ppi_icb_cmd_wmask,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:101: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n  output [`E203_XLEN/8-1:0]      ppi_icb_cmd_wmask,\n                    ^\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:111: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0]        ppi_icb_rsp_rdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:114: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  input [`E203_ADDR_SIZE-1:0]    clint_region_indic,\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:119: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:121: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:122: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:132: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:134: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  input [`E203_ADDR_SIZE-1:0]    plic_region_indic,\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:139: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:141: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:142: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:152: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:289: Define or directive not defined: \'`E203_INSTR_SIZE\'\n  wire [`E203_INSTR_SIZE-1:0] ifu_o_ir;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:290: Define or directive not defined: \'`E203_PC_SIZE\'\n  wire [`E203_PC_SIZE-1:0] ifu_o_pc;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:294: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx;\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:295: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx;\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:303: Define or directive not defined: \'`E203_PC_SIZE\'\n  wire [`E203_PC_SIZE-1:0] pipe_flush_add_op1;  \n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:304: Define or directive not defined: \'`E203_PC_SIZE\'\n  wire [`E203_PC_SIZE-1:0] pipe_flush_add_op2;  \n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:310: Define or directive not defined: \'`E203_XLEN\'\n  wire [`E203_XLEN-1:0] rf2ifu_x1;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:311: Define or directive not defined: \'`E203_XLEN\'\n  wire [`E203_XLEN-1:0] rf2ifu_rs1;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:314: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  wire [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx;\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:324: syntax error, unexpected IDENTIFIER\n  e203_ifu u_e203_ifu(\n  ^~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:403: Define or directive not defined: \'`E203_PC_SIZE\'\n  wire [`E203_PC_SIZE-1:0] bufout_inspect_pc;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:418: Define or directive not defined: \'`E203_INSTR_SIZE\'\n  wire [`E203_INSTR_SIZE-1:0] bufout_ifu_o_ir; \n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:419: Define or directive not defined: \'`E203_PC_SIZE\'\n  wire [`E203_PC_SIZE-1:0] bufout_ifu_o_pc;    \n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:423: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  wire [`E203_RFIDX_WIDTH-1:0] bufout_ifu_o_rs1idx;\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:424: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n  wire [`E203_RFIDX_WIDTH-1:0] bufout_ifu_o_rs2idx;\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:438: syntax error, unexpected IDENTIFIER\n  ifu_buffer u_ifu_buffer(\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:526: Define or directive not defined: \'`E203_XLEN\'\n  wire [`E203_XLEN-1:0]        lsu_o_wbck_wdat;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:527: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n  wire [`E203_ITAG_WIDTH -1:0] lsu_o_wbck_itag;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:532: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  wire [`E203_ADDR_SIZE -1:0]  lsu_o_cmt_badaddr;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:536: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  wire [`E203_ADDR_SIZE-1:0]   agu_icb_cmd_addr; \n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:538: Define or directive not defined: \'`E203_XLEN\'\n  wire [`E203_XLEN-1:0]        agu_icb_cmd_wdata; \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:539: Define or directive not defined: \'`E203_XLEN\'\n  wire [`E203_XLEN/8-1:0]      agu_icb_cmd_wmask; \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:539: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n  wire [`E203_XLEN/8-1:0]      agu_icb_cmd_wmask; \n                  ^\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:545: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n  wire [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:550: Define or directive not defined: \'`E203_XLEN\'\n  wire [`E203_XLEN-1:0]        agu_icb_rsp_rdata;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/171607226/rtl/e203/redundant_core/new_core.v:556: syntax error, unexpected IDENTIFIER\n  e203_exu u_e203_exu(\n  ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module new_core(
  output[`E203_PC_SIZE-1:0] inspect_pc,

  `ifdef E203_HAS_CSR_EAI
  output         eai_csr_valid,
  input          eai_csr_ready,
  output  [31:0] eai_csr_addr,
  output         eai_csr_wr,
  output  [31:0] eai_csr_wdata,
  input   [31:0] eai_csr_rdata,
  `endif
  output core_wfi,
  output tm_stop,
  output core_cgstop,
  output tcm_cgstop,

  input  [`E203_PC_SIZE-1:0] pc_rtvec,

  input  [`E203_HART_ID_W-1:0] core_mhartid,
  input  dbg_irq_r,
  input  [`E203_LIRQ_NUM-1:0] lcl_irq_r,
  input  [`E203_EVT_NUM-1:0] evt_r,
  input  ext_irq_r,
  input  sft_irq_r,
  input  tmr_irq_r,



  output  wr_dcsr_ena    ,
  output  wr_dpc_ena     ,
  output  wr_dscratch_ena,



  output  [32-1:0] wr_csr_nxt    ,

  input  [32-1:0] dcsr_r    ,
  input  [`E203_PC_SIZE-1:0] dpc_r     ,
  input  [32-1:0] dscratch_r,

  output  [`E203_PC_SIZE-1:0] cmt_dpc,
  output  cmt_dpc_ena,
  output  [3-1:0] cmt_dcause,
  output  cmt_dcause_ena,

  input  dbg_mode,
  input  dbg_halt_r,
  input  dbg_step_r,
  input  dbg_ebreakm_r,
  input  dbg_stopcycle,

  `ifdef E203_HAS_ITCM

  input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
  input  ifu2itcm_holdup,






  output ifu2itcm_icb_cmd_valid,
  input  ifu2itcm_icb_cmd_ready,


  output [`E203_ITCM_ADDR_WIDTH-1:0]   ifu2itcm_icb_cmd_addr,


  input  ifu2itcm_icb_rsp_valid,
  output ifu2itcm_icb_rsp_ready,
  input  ifu2itcm_icb_rsp_err,

  input  [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata, 
  `endif





  input [`E203_ADDR_SIZE-1:0]    ppi_region_indic,

  input                          ppi_icb_enable,

  output                         ppi_icb_cmd_valid,
  input                          ppi_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   ppi_icb_cmd_addr, 
  output                         ppi_icb_cmd_read, 
  output [`E203_XLEN-1:0]        ppi_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      ppi_icb_cmd_wmask,
  output                         ppi_icb_cmd_lock,
  output                         ppi_icb_cmd_excl,
  output [1:0]                   ppi_icb_cmd_size,


  input                          ppi_icb_rsp_valid,
  output                         ppi_icb_rsp_ready,
  input                          ppi_icb_rsp_err  ,
  input                          ppi_icb_rsp_excl_ok  ,
  input  [`E203_XLEN-1:0]        ppi_icb_rsp_rdata,

  
  input [`E203_ADDR_SIZE-1:0]    clint_region_indic,
  input                          clint_icb_enable,

  output                         clint_icb_cmd_valid,
  input                          clint_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, 
  output                         clint_icb_cmd_read, 
  output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,
  output                         clint_icb_cmd_lock,
  output                         clint_icb_cmd_excl,
  output [1:0]                   clint_icb_cmd_size,


  input                          clint_icb_rsp_valid,
  output                         clint_icb_rsp_ready,
  input                          clint_icb_rsp_err  ,
  input                          clint_icb_rsp_excl_ok  ,
  input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,

  input [`E203_ADDR_SIZE-1:0]    plic_region_indic,
  input                          plic_icb_enable,

  output                         plic_icb_cmd_valid,
  input                          plic_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, 
  output                         plic_icb_cmd_read, 
  output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,
  output                         plic_icb_cmd_lock,
  output                         plic_icb_cmd_excl,
  output [1:0]                   plic_icb_cmd_size,


  input                          plic_icb_rsp_valid,
  output                         plic_icb_rsp_ready,
  input                          plic_icb_rsp_err  ,
  input                          plic_icb_rsp_excl_ok  ,
  input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,


  `ifdef E203_HAS_FIO



  input [`E203_ADDR_SIZE-1:0]    fio_region_indic,

  input                          fio_icb_enable,

  output                         fio_icb_cmd_valid,
  input                          fio_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   fio_icb_cmd_addr, 
  output                         fio_icb_cmd_read, 
  output [`E203_XLEN-1:0]        fio_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      fio_icb_cmd_wmask,
  output                         fio_icb_cmd_lock,
  output                         fio_icb_cmd_excl,
  output [1:0]                   fio_icb_cmd_size,


  input                          fio_icb_rsp_valid,
  output                         fio_icb_rsp_ready,
  input                          fio_icb_rsp_err  ,
  input                          fio_icb_rsp_excl_ok  ,
  input  [`E203_XLEN-1:0]        fio_icb_rsp_rdata,
  `endif

  `ifdef E203_HAS_MEM_ITF




  input                          mem_icb_enable,

  output                         mem_icb_cmd_valid,
  input                          mem_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   mem_icb_cmd_addr, 
  output                         mem_icb_cmd_read, 
  output [`E203_XLEN-1:0]        mem_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      mem_icb_cmd_wmask,
  output                         mem_icb_cmd_lock,
  output                         mem_icb_cmd_excl,
  output [1:0]                   mem_icb_cmd_size,
  output [1:0]                   mem_icb_cmd_burst,
  output [1:0]                   mem_icb_cmd_beat,


  input                          mem_icb_rsp_valid,
  output                         mem_icb_rsp_ready,
  input                          mem_icb_rsp_err  ,
  input                          mem_icb_rsp_excl_ok  ,
  input  [`E203_XLEN-1:0]        mem_icb_rsp_rdata,
  `endif

  `ifdef E203_HAS_ITCM





  output                         lsu2itcm_icb_cmd_valid,
  input                          lsu2itcm_icb_cmd_ready,
  output [`E203_ITCM_ADDR_WIDTH-1:0]   lsu2itcm_icb_cmd_addr, 
  output                         lsu2itcm_icb_cmd_read, 
  output [`E203_XLEN-1:0]        lsu2itcm_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      lsu2itcm_icb_cmd_wmask,
  output                         lsu2itcm_icb_cmd_lock,
  output                         lsu2itcm_icb_cmd_excl,
  output [1:0]                   lsu2itcm_icb_cmd_size,


  input                          lsu2itcm_icb_rsp_valid,
  output                         lsu2itcm_icb_rsp_ready,
  input                          lsu2itcm_icb_rsp_err  ,
  input                          lsu2itcm_icb_rsp_excl_ok  ,
  input  [`E203_XLEN-1:0]        lsu2itcm_icb_rsp_rdata,
  `endif

    `ifdef E203_HAS_DTCM
  input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,





  output                         lsu2dtcm_icb_cmd_valid,
  input                          lsu2dtcm_icb_cmd_ready,
  output [`E203_DTCM_ADDR_WIDTH-1:0]   lsu2dtcm_icb_cmd_addr, 
  output                         lsu2dtcm_icb_cmd_read, 
  output [`E203_XLEN-1:0]        lsu2dtcm_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      lsu2dtcm_icb_cmd_wmask,
  output                         lsu2dtcm_icb_cmd_lock,
  output                         lsu2dtcm_icb_cmd_excl,
  output [1:0]                   lsu2dtcm_icb_cmd_size,


  input                          lsu2dtcm_icb_rsp_valid,
  output                         lsu2dtcm_icb_rsp_ready,
  input                          lsu2dtcm_icb_rsp_err  ,
  input                          lsu2dtcm_icb_rsp_excl_ok,
  input  [`E203_XLEN-1:0]        lsu2dtcm_icb_rsp_rdata,
  `endif

  output exu_active,
  output ifu_active,
  output lsu_active,
  output biu_active,

  input  clk_core_ifu,
  input  clk_core_exu,
  input  clk_core_lsu,
  input  clk_core_biu,
  input  clk_aon,

  input test_mode,
  input  rst_n
  );

    `ifdef E203_HAS_MEM_ITF
  wire                         ifu2biu_icb_cmd_valid;
  wire                         ifu2biu_icb_cmd_ready;
  wire [`E203_ADDR_SIZE-1:0]   ifu2biu_icb_cmd_addr; 
  wire                         ifu2biu_icb_rsp_valid;
  wire                         ifu2biu_icb_rsp_ready;
  wire                         ifu2biu_icb_rsp_err  ;
  wire                         ifu2biu_icb_rsp_excl_ok;
  wire [`E203_XLEN-1:0]        ifu2biu_icb_rsp_rdata;
   
  `endif




  wire ifu_o_valid;
  wire ifu_o_ready;
  wire [`E203_INSTR_SIZE-1:0] ifu_o_ir;
  wire [`E203_PC_SIZE-1:0] ifu_o_pc;
  wire ifu_o_pc_vld; 
  wire ifu_o_misalgn; 
  wire ifu_o_buserr; 
  wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx;
  wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx;
  wire ifu_o_prdt_taken;
  wire ifu_o_muldiv_b2b;

  wire wfi_halt_ifu_req;
  wire wfi_halt_ifu_ack;
  wire pipe_flush_ack;
  wire pipe_flush_req;
  wire [`E203_PC_SIZE-1:0] pipe_flush_add_op1;  
  wire [`E203_PC_SIZE-1:0] pipe_flush_add_op2;  
  `ifdef E203_TIMING_BOOST
  wire [`E203_PC_SIZE-1:0] pipe_flush_pc;  
  `endif

  wire oitf_empty;
  wire [`E203_XLEN-1:0] rf2ifu_x1;
  wire [`E203_XLEN-1:0] rf2ifu_rs1;
  wire dec2ifu_rden;
  wire dec2ifu_rs1en;
  wire [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx;
  wire dec2ifu_mulhsu;
  wire dec2ifu_div   ;
  wire dec2ifu_rem   ;
  wire dec2ifu_divu  ;
  wire dec2ifu_remu  ;


  wire itcm_nohold;

  e203_ifu u_e203_ifu(
    .inspect_pc   (inspect_pc),

    .ifu_active      (ifu_active),
    .pc_rtvec        (pc_rtvec),  

    .itcm_nohold     (itcm_nohold),

  `ifdef E203_HAS_ITCM
    .ifu2itcm_holdup (ifu2itcm_holdup),



    .itcm_region_indic (itcm_region_indic),

    .ifu2itcm_icb_cmd_valid(ifu2itcm_icb_cmd_valid),
    .ifu2itcm_icb_cmd_ready(ifu2itcm_icb_cmd_ready),
    .ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
    .ifu2itcm_icb_rsp_valid(ifu2itcm_icb_rsp_valid),
    .ifu2itcm_icb_rsp_ready(ifu2itcm_icb_rsp_ready),
    .ifu2itcm_icb_rsp_err  (ifu2itcm_icb_rsp_err  ),
    .ifu2itcm_icb_rsp_rdata(ifu2itcm_icb_rsp_rdata),
  `endif

  `ifdef E203_HAS_MEM_ITF
    .ifu2biu_icb_cmd_valid  (ifu2biu_icb_cmd_valid),
    .ifu2biu_icb_cmd_ready  (ifu2biu_icb_cmd_ready),
    .ifu2biu_icb_cmd_addr   (ifu2biu_icb_cmd_addr ),
    
    .ifu2biu_icb_rsp_valid  (ifu2biu_icb_rsp_valid),
    .ifu2biu_icb_rsp_ready  (ifu2biu_icb_rsp_ready),
    .ifu2biu_icb_rsp_err    (ifu2biu_icb_rsp_err  ),
    .ifu2biu_icb_rsp_rdata  (ifu2biu_icb_rsp_rdata),

  `endif


    .ifu_o_valid            (ifu_o_valid         ),
    .ifu_o_ready            (ifu_o_ready         ),
    .ifu_o_ir               (ifu_o_ir            ),
    .ifu_o_pc               (ifu_o_pc            ),
    .ifu_o_pc_vld           (ifu_o_pc_vld        ),
    .ifu_o_misalgn          (ifu_o_misalgn       ), 
    .ifu_o_buserr           (ifu_o_buserr        ), 
    .ifu_o_rs1idx           (ifu_o_rs1idx        ),
    .ifu_o_rs2idx           (ifu_o_rs2idx        ),
    .ifu_o_prdt_taken       (ifu_o_prdt_taken    ),
    .ifu_o_muldiv_b2b       (ifu_o_muldiv_b2b    ),

    .ifu_halt_req           (wfi_halt_ifu_req),
    .ifu_halt_ack           (wfi_halt_ifu_ack),
    .pipe_flush_ack         (pipe_flush_ack      ),
    .pipe_flush_req         (pipe_flush_req      ),
    .pipe_flush_add_op1     (pipe_flush_add_op1  ),  
    .pipe_flush_add_op2     (pipe_flush_add_op2  ),  
  `ifdef E203_TIMING_BOOST
    .pipe_flush_pc          (pipe_flush_pc),  
  `endif

                                 
    .oitf_empty             (oitf_empty   ),
    .rf2ifu_x1              (rf2ifu_x1    ),
    .rf2ifu_rs1             (rf2ifu_rs1   ),
    .dec2ifu_rden           (dec2ifu_rden ),
    .dec2ifu_rs1en          (dec2ifu_rs1en),
    .dec2ifu_rdidx          (dec2ifu_rdidx),
    .dec2ifu_mulhsu         (dec2ifu_mulhsu),
    .dec2ifu_div            (dec2ifu_div   ),
    .dec2ifu_rem            (dec2ifu_rem   ),
    .dec2ifu_divu           (dec2ifu_divu  ),
    .dec2ifu_remu           (dec2ifu_remu  ),

    .clk                    (clk_core_ifu  ),
    .rst_n                  (rst_n         ) 
  );
  
  


  wire [`E203_PC_SIZE-1:0] bufout_inspect_pc;
  wire bufout_ifu_active;

  `ifdef E203_HAS_ITCM
  wire bufout_ifu2itcm_icb_cmd_valid;
  wire [`E203_ITCM_ADDR_WIDTH-1:0]   bufout_ifu2itcm_icb_cmd_addr;
  wire bufout_ifu2itcm_icb_rsp_ready;
  `endif

  `ifdef E203_HAS_MEM_ITF
  wire bufout_ifu2biu_icb_cmd_valid;
  wire [`E203_ADDR_SIZE-1:0]   bufout_ifu2biu_icb_cmd_addr;
  wire bufout_ifu2biu_icb_rsp_ready;

  `endif
  wire [`E203_INSTR_SIZE-1:0] bufout_ifu_o_ir;
  wire [`E203_PC_SIZE-1:0] bufout_ifu_o_pc;
  wire bufout_ifu_o_pc_vld;
  wire bufout_ifu_o_misalgn;
  wire bufout_ifu_o_buserr;
  wire [`E203_RFIDX_WIDTH-1:0] bufout_ifu_o_rs1idx;
  wire [`E203_RFIDX_WIDTH-1:0] bufout_ifu_o_rs2idx;
  wire bufout_ifu_o_prdt_taken;
  wire bufout_ifu_o_muldiv_b2b;               
  wire bufout_ifu_o_valid;
  wire bufout_pipe_flush_ack;
  `ifdef E203_TIMING_BOOST
  `endif

  wire  bufout_ifu_halt_ack;
  

   wire ifu_buffer_enable; 

  
  ifu_buffer u_ifu_buffer(
  
    .clk(clk_core_ifu),
    .lden(ifu_buffer_enable),  
  
  


      .inspect_pc(bufout_inspect_pc),
      .ifu_active(bufout_ifu_active),

  `ifdef E203_HAS_ITCM
      .ifu2itcm_icb_cmd_valid(bufout_ifu2itcm_icb_cmd_valid),
      .ifu2itcm_icb_cmd_addr(bufout_ifu2itcm_icb_cmd_addr),
      .ifu2itcm_icb_rsp_ready(bufout_ifu2biu_icb_rsp_ready),
  `endif

  `ifdef E203_HAS_MEM_ITF
      .ifu2biu_icb_cmd_valid(bufout_ifu2biu_icb_cmd_valid),
      .ifu2biu_icb_cmd_addr(bufout_ifu2biu_icb_cmd_addr),
      .ifu2biu_icb_rsp_ready(bufout_ifu2biu_icb_rsp_ready),

  `endif
      .ifu_o_ir(bufout_ifu_o_ir),
      .ifu_o_pc(bufout_ifu_o_pc),
      .ifu_o_pc_vld(bufout_ifu_o_pc_vld),
      .ifu_o_misalgn(bufout_ifu_o_misalgn),
      .ifu_o_buserr(bufout_ifu_o_buserr),
      .ifu_o_rs1idx(bufout_ifu_o_rs1idx),
      .ifu_o_rs2idx(bufout_ifu_o_rs2idx),
      .ifu_o_prdt_taken(bufout_ifu_o_prdt_taken),
      .ifu_o_muldiv_b2b(bufout_ifu_o_muldiv_b2b),               
      .ifu_o_valid(bufout_ifu_o_valid),
      .pipe_flush_ack(bufout_pipe_flush_ack),
  `ifdef E203_TIMING_BOOST
  `endif
       .ifu_halt_ack(bufout_ifu_halt_ack),





      .in_inspect_pc(inspect_pc),
      .in_ifu_active(ifu_active),

  `ifdef E203_HAS_ITCM
      .in_ifu2itcm_icb_cmd_valid(ifu2itcm_icb_cmd_valid),
      .in_ifu2itcm_icb_cmd_addr(ifu2itcm_icb_cmd_addr),
      .in_ifu2itcm_icb_rsp_ready(ifu2biu_icb_rsp_ready),
  `endif

  `ifdef E203_HAS_MEM_ITF
      .in_ifu2biu_icb_cmd_valid(ifu2biu_icb_cmd_valid),
      .in_ifu2biu_icb_cmd_addr(ifu2biu_icb_cmd_addr),
      .in_ifu2biu_icb_rsp_ready(ifu2biu_icb_rsp_ready),

  `endif
      .in_ifu_o_ir(ifu_o_ir),
      .in_ifu_o_pc(ifu_o_pc),
      .in_ifu_o_pc_vld(ifu_o_pc_vld),
      .in_ifu_o_misalgn(ifu_o_misalgn),
      .in_ifu_o_buserr(ifu_o_buserr),
      .in_ifu_o_rs1idx(ifu_o_rs1idx),
      .in_ifu_o_rs2idx(ifu_o_rs2idx),
      .in_ifu_o_prdt_taken(ifu_o_prdt_taken),
      .in_ifu_o_muldiv_b2b(ifu_o_muldiv_b2b),               
      .in_ifu_o_valid(ifu_o_valid),
      .in_pipe_flush_ack(pipe_flush_ack),
  `ifdef E203_TIMING_BOOST
  `endif
       .in_ifu_halt_ack(wfi_halt_ifu_ack)  

  );
  
  
  
  
  
  
  
  
  
  

  

  wire                         lsu_o_valid; 
  wire                         lsu_o_ready; 
  wire [`E203_XLEN-1:0]        lsu_o_wbck_wdat;
  wire [`E203_ITAG_WIDTH -1:0] lsu_o_wbck_itag;
  wire                         lsu_o_wbck_err ; 
  wire                         lsu_o_cmt_buserr ; 
  wire                         lsu_o_cmt_ld;
  wire                         lsu_o_cmt_st;
  wire [`E203_ADDR_SIZE -1:0]  lsu_o_cmt_badaddr;

  wire                         agu_icb_cmd_valid; 
  wire                         agu_icb_cmd_ready; 
  wire [`E203_ADDR_SIZE-1:0]   agu_icb_cmd_addr; 
  wire                         agu_icb_cmd_read;   
  wire [`E203_XLEN-1:0]        agu_icb_cmd_wdata; 
  wire [`E203_XLEN/8-1:0]      agu_icb_cmd_wmask; 
  wire                         agu_icb_cmd_lock;
  wire                         agu_icb_cmd_excl;
  wire [1:0]                   agu_icb_cmd_size;
  wire                         agu_icb_cmd_back2agu; 
  wire                         agu_icb_cmd_usign;
  wire [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag;
  wire                         agu_icb_rsp_valid; 
  wire                         agu_icb_rsp_ready; 
  wire                         agu_icb_rsp_err  ; 
  wire                         agu_icb_rsp_excl_ok  ; 
  wire [`E203_XLEN-1:0]        agu_icb_rsp_rdata;

  wire commit_mret;
  wire commit_trap;
  wire excp_active;

  e203_exu u_e203_exu(

  `ifdef E203_HAS_CSR_EAI
    .eai_csr_valid (eai_csr_valid),
    .eai_csr_ready (eai_csr_ready),
    .eai_csr_addr  (eai_csr_addr ),
    .eai_csr_wr    (eai_csr_wr   ),
    .eai_csr_wdata (eai_csr_wdata),
    .eai_csr_rdata (eai_csr_rdata),
  `endif


    .excp_active            (excp_active),
    .commit_mret            (commit_mret),
    .commit_trap            (commit_trap),
    .test_mode              (test_mode),
    .core_wfi               (core_wfi),
    .tm_stop                (tm_stop),
    .itcm_nohold            (itcm_nohold),
    .core_cgstop            (core_cgstop),
    .tcm_cgstop             (tcm_cgstop),
    .exu_active             (exu_active),

    .core_mhartid           (core_mhartid),
    .dbg_irq_r              (dbg_irq_r),
    .lcl_irq_r              (lcl_irq_r    ),
    .ext_irq_r              (ext_irq_r    ),
    .sft_irq_r              (sft_irq_r    ),
    .tmr_irq_r              (tmr_irq_r    ),
    .evt_r                  (evt_r    ),

    .cmt_dpc                (cmt_dpc        ),
    .cmt_dpc_ena            (cmt_dpc_ena    ),
    .cmt_dcause             (cmt_dcause     ),
    .cmt_dcause_ena         (cmt_dcause_ena ),

    .wr_dcsr_ena     (wr_dcsr_ena    ),
    .wr_dpc_ena      (wr_dpc_ena     ),
    .wr_dscratch_ena (wr_dscratch_ena),


                                     
    .wr_csr_nxt      (wr_csr_nxt    ),
                                     
    .dcsr_r          (dcsr_r         ),
    .dpc_r           (dpc_r          ),
    .dscratch_r      (dscratch_r     ),

    .dbg_mode               (dbg_mode  ),
    .dbg_halt_r             (dbg_halt_r),
    .dbg_step_r             (dbg_step_r),
    .dbg_ebreakm_r          (dbg_ebreakm_r),
    .dbg_stopcycle          (dbg_stopcycle),

    .i_valid                (ifu_o_valid         ),
    .i_ready                (ifu_o_ready         ),
    .i_ir                   (ifu_o_ir            ),
    .i_pc                   (ifu_o_pc            ),
    .i_pc_vld               (ifu_o_pc_vld        ),
    .i_misalgn              (ifu_o_misalgn       ), 
    .i_buserr               (ifu_o_buserr        ), 
    .i_rs1idx               (ifu_o_rs1idx        ),
    .i_rs2idx               (ifu_o_rs2idx        ),
    .i_prdt_taken           (ifu_o_prdt_taken    ),
    .i_muldiv_b2b           (ifu_o_muldiv_b2b    ),

    .wfi_halt_ifu_req       (wfi_halt_ifu_req),
    .wfi_halt_ifu_ack       (wfi_halt_ifu_ack),

    .pipe_flush_ack         (pipe_flush_ack      ),
    .pipe_flush_req         (pipe_flush_req      ),
    .pipe_flush_add_op1     (pipe_flush_add_op1  ),  
    .pipe_flush_add_op2     (pipe_flush_add_op2  ),  
  `ifdef E203_TIMING_BOOST
    .pipe_flush_pc          (pipe_flush_pc),  
  `endif

    .lsu_o_valid            (lsu_o_valid   ),
    .lsu_o_ready            (lsu_o_ready   ),
    .lsu_o_wbck_wdat        (lsu_o_wbck_wdat    ),
    .lsu_o_wbck_itag        (lsu_o_wbck_itag    ),
    .lsu_o_wbck_err         (lsu_o_wbck_err     ),
    .lsu_o_cmt_buserr       (lsu_o_cmt_buserr     ),
    .lsu_o_cmt_ld           (lsu_o_cmt_ld),
    .lsu_o_cmt_st           (lsu_o_cmt_st),
    .lsu_o_cmt_badaddr      (lsu_o_cmt_badaddr     ),

    .agu_icb_cmd_valid      (agu_icb_cmd_valid   ),
    .agu_icb_cmd_ready      (agu_icb_cmd_ready   ),
    .agu_icb_cmd_addr       (agu_icb_cmd_addr    ),
    .agu_icb_cmd_read       (agu_icb_cmd_read    ),
    .agu_icb_cmd_wdata      (agu_icb_cmd_wdata   ),
    .agu_icb_cmd_wmask      (agu_icb_cmd_wmask   ),
    .agu_icb_cmd_lock       (agu_icb_cmd_lock    ),
    .agu_icb_cmd_excl       (agu_icb_cmd_excl    ),
    .agu_icb_cmd_size       (agu_icb_cmd_size    ),
    .agu_icb_cmd_back2agu   (agu_icb_cmd_back2agu),
    .agu_icb_cmd_usign      (agu_icb_cmd_usign   ),
    .agu_icb_cmd_itag       (agu_icb_cmd_itag    ),
    .agu_icb_rsp_valid      (agu_icb_rsp_valid   ),
    .agu_icb_rsp_ready      (agu_icb_rsp_ready   ),
    .agu_icb_rsp_err        (agu_icb_rsp_err     ),
    .agu_icb_rsp_excl_ok    (agu_icb_rsp_excl_ok ),
    .agu_icb_rsp_rdata      (agu_icb_rsp_rdata   ),

    .oitf_empty             (oitf_empty   ),
    .rf2ifu_x1              (rf2ifu_x1    ),
    .rf2ifu_rs1             (rf2ifu_rs1   ),
    .dec2ifu_rden           (dec2ifu_rden ),
    .dec2ifu_rs1en          (dec2ifu_rs1en),
    .dec2ifu_rdidx          (dec2ifu_rdidx),
    .dec2ifu_mulhsu         (dec2ifu_mulhsu),
    .dec2ifu_div            (dec2ifu_div   ),
    .dec2ifu_rem            (dec2ifu_rem   ),
    .dec2ifu_divu           (dec2ifu_divu  ),
    .dec2ifu_remu           (dec2ifu_remu  ),


    .clk_aon                (clk_aon),
    .clk                    (clk_core_exu),
    .rst_n                  (rst_n  ) 
  );

  wire                         lsu2biu_icb_cmd_valid;
  wire                         lsu2biu_icb_cmd_ready;
  wire [`E203_ADDR_SIZE-1:0]   lsu2biu_icb_cmd_addr; 
  wire                         lsu2biu_icb_cmd_read; 
  wire [`E203_XLEN-1:0]        lsu2biu_icb_cmd_wdata;
  wire [`E203_XLEN/8-1:0]      lsu2biu_icb_cmd_wmask;
  wire                         lsu2biu_icb_cmd_lock;
  wire                         lsu2biu_icb_cmd_excl;
  wire [1:0]                   lsu2biu_icb_cmd_size;

  wire                         lsu2biu_icb_rsp_valid;
  wire                         lsu2biu_icb_rsp_ready;
  wire                         lsu2biu_icb_rsp_err  ;
  wire                         lsu2biu_icb_rsp_excl_ok;
  wire [`E203_XLEN-1:0]        lsu2biu_icb_rsp_rdata;

  e203_lsu u_e203_lsu(
    .excp_active         (excp_active),
    .commit_mret            (commit_mret),
    .commit_trap         (commit_trap),
    .lsu_active          (lsu_active),
    .lsu_o_valid         (lsu_o_valid   ),
    .lsu_o_ready         (lsu_o_ready   ),
    .lsu_o_wbck_wdat     (lsu_o_wbck_wdat    ),
    .lsu_o_wbck_itag     (lsu_o_wbck_itag    ),
    .lsu_o_wbck_err      (lsu_o_wbck_err     ),
    .lsu_o_cmt_buserr    (lsu_o_cmt_buserr     ),
    .lsu_o_cmt_ld        (lsu_o_cmt_ld),
    .lsu_o_cmt_st        (lsu_o_cmt_st),
    .lsu_o_cmt_badaddr   (lsu_o_cmt_badaddr     ),
                        
    .agu_icb_cmd_valid   (agu_icb_cmd_valid ),
    .agu_icb_cmd_ready   (agu_icb_cmd_ready ),
    .agu_icb_cmd_addr    (agu_icb_cmd_addr  ),
    .agu_icb_cmd_read    (agu_icb_cmd_read  ),
    .agu_icb_cmd_wdata   (agu_icb_cmd_wdata ),
    .agu_icb_cmd_wmask   (agu_icb_cmd_wmask ),
    .agu_icb_cmd_lock    (agu_icb_cmd_lock  ),
    .agu_icb_cmd_excl    (agu_icb_cmd_excl  ),
    .agu_icb_cmd_size    (agu_icb_cmd_size  ),
   
    .agu_icb_cmd_back2agu(agu_icb_cmd_back2agu ),
    .agu_icb_cmd_usign   (agu_icb_cmd_usign),
    .agu_icb_cmd_itag    (agu_icb_cmd_itag),
  
    .agu_icb_rsp_valid   (agu_icb_rsp_valid ),
    .agu_icb_rsp_ready   (agu_icb_rsp_ready ),
    .agu_icb_rsp_err     (agu_icb_rsp_err   ),
    .agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok),
    .agu_icb_rsp_rdata   (agu_icb_rsp_rdata),



  `ifdef E203_HAS_ITCM
    .itcm_region_indic   (itcm_region_indic),
    .itcm_icb_cmd_valid  (lsu2itcm_icb_cmd_valid),
    .itcm_icb_cmd_ready  (lsu2itcm_icb_cmd_ready),
    .itcm_icb_cmd_addr   (lsu2itcm_icb_cmd_addr ),
    .itcm_icb_cmd_read   (lsu2itcm_icb_cmd_read ),
    .itcm_icb_cmd_wdata  (lsu2itcm_icb_cmd_wdata),
    .itcm_icb_cmd_wmask  (lsu2itcm_icb_cmd_wmask),
    .itcm_icb_cmd_lock   (lsu2itcm_icb_cmd_lock ),
    .itcm_icb_cmd_excl   (lsu2itcm_icb_cmd_excl ),
    .itcm_icb_cmd_size   (lsu2itcm_icb_cmd_size ),
     
    .itcm_icb_rsp_valid  (lsu2itcm_icb_rsp_valid),
    .itcm_icb_rsp_ready  (lsu2itcm_icb_rsp_ready),
    .itcm_icb_rsp_err    (lsu2itcm_icb_rsp_err  ),
    .itcm_icb_rsp_excl_ok(lsu2itcm_icb_rsp_excl_ok  ),
    .itcm_icb_rsp_rdata  (lsu2itcm_icb_rsp_rdata),

  `endif

  `ifdef E203_HAS_DTCM
    .dtcm_region_indic   (dtcm_region_indic),

    .dtcm_icb_cmd_valid  (lsu2dtcm_icb_cmd_valid),
    .dtcm_icb_cmd_ready  (lsu2dtcm_icb_cmd_ready),
    .dtcm_icb_cmd_addr   (lsu2dtcm_icb_cmd_addr ),
    .dtcm_icb_cmd_read   (lsu2dtcm_icb_cmd_read ),
    .dtcm_icb_cmd_wdata  (lsu2dtcm_icb_cmd_wdata),
    .dtcm_icb_cmd_wmask  (lsu2dtcm_icb_cmd_wmask),
    .dtcm_icb_cmd_lock   (lsu2dtcm_icb_cmd_lock ),
    .dtcm_icb_cmd_excl   (lsu2dtcm_icb_cmd_excl ),
    .dtcm_icb_cmd_size   (lsu2dtcm_icb_cmd_size ),
     
    .dtcm_icb_rsp_valid  (lsu2dtcm_icb_rsp_valid),
    .dtcm_icb_rsp_ready  (lsu2dtcm_icb_rsp_ready),
    .dtcm_icb_rsp_err    (lsu2dtcm_icb_rsp_err  ),
    .dtcm_icb_rsp_excl_ok(lsu2dtcm_icb_rsp_excl_ok  ),
    .dtcm_icb_rsp_rdata  (lsu2dtcm_icb_rsp_rdata),

  `endif

    .biu_icb_cmd_valid  (lsu2biu_icb_cmd_valid),
    .biu_icb_cmd_ready  (lsu2biu_icb_cmd_ready),
    .biu_icb_cmd_addr   (lsu2biu_icb_cmd_addr ),
    .biu_icb_cmd_read   (lsu2biu_icb_cmd_read ),
    .biu_icb_cmd_wdata  (lsu2biu_icb_cmd_wdata),
    .biu_icb_cmd_wmask  (lsu2biu_icb_cmd_wmask),
    .biu_icb_cmd_lock   (lsu2biu_icb_cmd_lock ),
    .biu_icb_cmd_excl   (lsu2biu_icb_cmd_excl ),
    .biu_icb_cmd_size   (lsu2biu_icb_cmd_size ),
    
    .biu_icb_rsp_valid  (lsu2biu_icb_rsp_valid),
    .biu_icb_rsp_ready  (lsu2biu_icb_rsp_ready),
    .biu_icb_rsp_err    (lsu2biu_icb_rsp_err  ),
    .biu_icb_rsp_excl_ok(lsu2biu_icb_rsp_excl_ok),
    .biu_icb_rsp_rdata  (lsu2biu_icb_rsp_rdata),

    .clk           (clk_core_lsu ),
    .rst_n         (rst_n        ) 
  );


  e203_biu u_e203_biu(


    .biu_active             (biu_active),

    .lsu2biu_icb_cmd_valid  (lsu2biu_icb_cmd_valid),
    .lsu2biu_icb_cmd_ready  (lsu2biu_icb_cmd_ready),
    .lsu2biu_icb_cmd_addr   (lsu2biu_icb_cmd_addr ),
    .lsu2biu_icb_cmd_read   (lsu2biu_icb_cmd_read ),
    .lsu2biu_icb_cmd_wdata  (lsu2biu_icb_cmd_wdata),
    .lsu2biu_icb_cmd_wmask  (lsu2biu_icb_cmd_wmask),
    .lsu2biu_icb_cmd_lock   (lsu2biu_icb_cmd_lock ),
    .lsu2biu_icb_cmd_excl   (lsu2biu_icb_cmd_excl ),
    .lsu2biu_icb_cmd_size   (lsu2biu_icb_cmd_size ),
    .lsu2biu_icb_cmd_burst  (2'b0),
    .lsu2biu_icb_cmd_beat   (2'b0 ),

    .lsu2biu_icb_rsp_valid  (lsu2biu_icb_rsp_valid),
    .lsu2biu_icb_rsp_ready  (lsu2biu_icb_rsp_ready),
    .lsu2biu_icb_rsp_err    (lsu2biu_icb_rsp_err  ),
    .lsu2biu_icb_rsp_excl_ok(lsu2biu_icb_rsp_excl_ok),
    .lsu2biu_icb_rsp_rdata  (lsu2biu_icb_rsp_rdata),

  `ifdef E203_HAS_MEM_ITF
    .ifu2biu_icb_cmd_valid  (ifu2biu_icb_cmd_valid),
    .ifu2biu_icb_cmd_ready  (ifu2biu_icb_cmd_ready),
    .ifu2biu_icb_cmd_addr   (ifu2biu_icb_cmd_addr ),
    .ifu2biu_icb_cmd_read   (1'b1 ),
    .ifu2biu_icb_cmd_wdata  (`E203_XLEN'b0),
    .ifu2biu_icb_cmd_wmask  ({`E203_XLEN/8{1'b0}}),
    .ifu2biu_icb_cmd_lock   (1'b0 ),
    .ifu2biu_icb_cmd_excl   (1'b0 ),
    .ifu2biu_icb_cmd_size   (2'b10),
    .ifu2biu_icb_cmd_burst  (2'b0),
    .ifu2biu_icb_cmd_beat   (2'b0),
    
    .ifu2biu_icb_rsp_valid  (ifu2biu_icb_rsp_valid),
    .ifu2biu_icb_rsp_ready  (ifu2biu_icb_rsp_ready),
    .ifu2biu_icb_rsp_err    (ifu2biu_icb_rsp_err  ),
    .ifu2biu_icb_rsp_excl_ok(ifu2biu_icb_rsp_excl_ok),
    .ifu2biu_icb_rsp_rdata  (ifu2biu_icb_rsp_rdata),

  `endif

    .ppi_region_indic      (ppi_region_indic ),
    .ppi_icb_enable        (ppi_icb_enable),
    .ppi_icb_cmd_valid     (ppi_icb_cmd_valid),
    .ppi_icb_cmd_ready     (ppi_icb_cmd_ready),
    .ppi_icb_cmd_addr      (ppi_icb_cmd_addr ),
    .ppi_icb_cmd_read      (ppi_icb_cmd_read ),
    .ppi_icb_cmd_wdata     (ppi_icb_cmd_wdata),
    .ppi_icb_cmd_wmask     (ppi_icb_cmd_wmask),
    .ppi_icb_cmd_lock      (ppi_icb_cmd_lock ),
    .ppi_icb_cmd_excl      (ppi_icb_cmd_excl ),
    .ppi_icb_cmd_size      (ppi_icb_cmd_size ),
    .ppi_icb_cmd_burst     (),
    .ppi_icb_cmd_beat      (),
    
    .ppi_icb_rsp_valid     (ppi_icb_rsp_valid),
    .ppi_icb_rsp_ready     (ppi_icb_rsp_ready),
    .ppi_icb_rsp_err       (ppi_icb_rsp_err  ),
    .ppi_icb_rsp_excl_ok   (ppi_icb_rsp_excl_ok),
    .ppi_icb_rsp_rdata     (ppi_icb_rsp_rdata),


    .plic_icb_enable        (plic_icb_enable),
    .plic_region_indic      (plic_region_indic ),
    .plic_icb_cmd_valid     (plic_icb_cmd_valid),
    .plic_icb_cmd_ready     (plic_icb_cmd_ready),
    .plic_icb_cmd_addr      (plic_icb_cmd_addr ),
    .plic_icb_cmd_read      (plic_icb_cmd_read ),
    .plic_icb_cmd_wdata     (plic_icb_cmd_wdata),
    .plic_icb_cmd_wmask     (plic_icb_cmd_wmask),
    .plic_icb_cmd_lock      (plic_icb_cmd_lock ),
    .plic_icb_cmd_excl      (plic_icb_cmd_excl ),
    .plic_icb_cmd_size      (plic_icb_cmd_size ),
    .plic_icb_cmd_burst     (),
    .plic_icb_cmd_beat      (),
    
    .plic_icb_rsp_valid     (plic_icb_rsp_valid),
    .plic_icb_rsp_ready     (plic_icb_rsp_ready),
    .plic_icb_rsp_err       (plic_icb_rsp_err  ),
    .plic_icb_rsp_excl_ok   (plic_icb_rsp_excl_ok),
    .plic_icb_rsp_rdata     (plic_icb_rsp_rdata),

    .clint_icb_enable        (clint_icb_enable),
    .clint_region_indic      (clint_region_indic ),
    .clint_icb_cmd_valid     (clint_icb_cmd_valid),
    .clint_icb_cmd_ready     (clint_icb_cmd_ready),
    .clint_icb_cmd_addr      (clint_icb_cmd_addr ),
    .clint_icb_cmd_read      (clint_icb_cmd_read ),
    .clint_icb_cmd_wdata     (clint_icb_cmd_wdata),
    .clint_icb_cmd_wmask     (clint_icb_cmd_wmask),
    .clint_icb_cmd_lock      (clint_icb_cmd_lock ),
    .clint_icb_cmd_excl      (clint_icb_cmd_excl ),
    .clint_icb_cmd_size      (clint_icb_cmd_size ),
    .clint_icb_cmd_burst     (),
    .clint_icb_cmd_beat      (),
    
    .clint_icb_rsp_valid     (clint_icb_rsp_valid),
    .clint_icb_rsp_ready     (clint_icb_rsp_ready),
    .clint_icb_rsp_err       (clint_icb_rsp_err  ),
    .clint_icb_rsp_excl_ok   (clint_icb_rsp_excl_ok),
    .clint_icb_rsp_rdata     (clint_icb_rsp_rdata),


  `ifdef E203_HAS_FIO
    .fio_region_indic      (fio_region_indic ),
    .fio_icb_enable        (fio_icb_enable),
    .fio_icb_cmd_valid     (fio_icb_cmd_valid),
    .fio_icb_cmd_ready     (fio_icb_cmd_ready),
    .fio_icb_cmd_addr      (fio_icb_cmd_addr ),
    .fio_icb_cmd_read      (fio_icb_cmd_read ),
    .fio_icb_cmd_wdata     (fio_icb_cmd_wdata),
    .fio_icb_cmd_wmask     (fio_icb_cmd_wmask),
    .fio_icb_cmd_lock      (fio_icb_cmd_lock ),
    .fio_icb_cmd_excl      (fio_icb_cmd_excl ),
    .fio_icb_cmd_size      (fio_icb_cmd_size ),
    .fio_icb_cmd_burst     (),
    .fio_icb_cmd_beat      (),
    
    .fio_icb_rsp_valid     (fio_icb_rsp_valid),
    .fio_icb_rsp_ready     (fio_icb_rsp_ready),
    .fio_icb_rsp_err       (fio_icb_rsp_err  ),
    .fio_icb_rsp_excl_ok   (fio_icb_rsp_excl_ok  ),
    .fio_icb_rsp_rdata     (fio_icb_rsp_rdata),
  `endif

  `ifdef E203_HAS_MEM_ITF
    .mem_icb_enable        (mem_icb_enable),
    .mem_icb_cmd_valid     (mem_icb_cmd_valid),
    .mem_icb_cmd_ready     (mem_icb_cmd_ready),
    .mem_icb_cmd_addr      (mem_icb_cmd_addr ),
    .mem_icb_cmd_read      (mem_icb_cmd_read ),
    .mem_icb_cmd_wdata     (mem_icb_cmd_wdata),
    .mem_icb_cmd_wmask     (mem_icb_cmd_wmask),
    .mem_icb_cmd_lock      (mem_icb_cmd_lock ),
    .mem_icb_cmd_excl      (mem_icb_cmd_excl ),
    .mem_icb_cmd_size      (mem_icb_cmd_size ),
    .mem_icb_cmd_burst     (mem_icb_cmd_burst),
    .mem_icb_cmd_beat      (mem_icb_cmd_beat ),
    
    .mem_icb_rsp_valid     (mem_icb_rsp_valid),
    .mem_icb_rsp_ready     (mem_icb_rsp_ready),
    .mem_icb_rsp_err       (mem_icb_rsp_err  ),
    .mem_icb_rsp_excl_ok   (mem_icb_rsp_excl_ok  ),
    .mem_icb_rsp_rdata     (mem_icb_rsp_rdata),
  `endif

    .clk                    (clk_core_biu ),
    .rst_n                  (rst_n        ) 
  );
  


  wire bufout_lsu_o_valid;
  wire [`E203_XLEN-1:0] bufout_lsu_o_wbck_wdat;
  wire [`E203_ITAG_WIDTH -1:0] bufout_lsu_o_wbck_itag;
  wire bufout_lsu_o_wbck_err; 
  wire bufout_lsu_o_cmt_ld;
  wire bufout_lsu_o_cmt_st;
  wire [`E203_ADDR_SIZE -1:0] bufout_lsu_o_cmt_badaddr;
  wire bufout_lsu_o_cmt_buserr;
  wire bufout_agu_icb_cmd_ready;
  wire bufout_agu_icb_rsp_valid;
  wire bufout_agu_icb_rsp_err;
  wire bufout_agu_icb_rsp_excl_ok;
  wire [`E203_XLEN-1:0]  bufout_agu_icb_rsp_rdata;

  

   wire lsu_buffer_enable; 



  lsu_buffer u_lsu_buffer(
  
   .clk(clk_core_lsu),
   .lden(lsu_buffer_enable),  





  .in_lsu_o_valid(lsu_o_valid),
  .in_lsu_o_wbck_wdat(lsu_o_wbck_wdat),
  .in_lsu_o_wbck_itag(lsu_o_wbck_itag),
  .in_lsu_o_wbck_err(lsu_o_wbck_err), 
  .in_lsu_o_cmt_ld(lsu_o_cmt_ld),
  .in_lsu_o_cmt_st(lsu_o_cmt_st),
  .in_lsu_o_cmt_badaddr(lsu_o_cmt_badaddr),
  .in_lsu_o_cmt_buserr(lsu_o_cmt_buserr),
  .in_agu_icb_cmd_ready(agu_icb_cmd_ready),
  .in_agu_icb_rsp_valid(agu_icb_rsp_valid),
  .in_agu_icb_rsp_err(agu_icb_rsp_err),
  .in_agu_icb_rsp_excl_ok(agu_icb_rsp_excl_ok),
  .in_agu_icb_rsp_rdata(agu_icb_rsp_rdata),







  .lsu_o_valid(bufout_lsu_o_valid),
  .lsu_o_wbck_wdat(bufout_lsu_o_wbck_wdat),
  .lsu_o_wbck_itag(bufout_lsu_o_wbck_itag),
  .lsu_o_wbck_err(bufout_lsu_o_wbck_err), 
  .lsu_o_cmt_ld(bufout_lsu_o_cmt_ld),
  .lsu_o_cmt_st(bufout_lsu_o_cmt_st),
  .lsu_o_cmt_badaddr(bufout_lsu_o_cmt_badaddr),
  .lsu_o_cmt_buserr(bufout_lsu_o_cmt_buserr),
  .agu_icb_cmd_ready(bufout_agu_icb_cmd_ready),
  .agu_icb_rsp_valid(bufout_agu_icb_rsp_valid),
  .agu_icb_rsp_err(bufout_agu_icb_rsp_err),
  .agu_icb_rsp_excl_ok(bufout_agu_icb_rsp_excl_ok),
  .agu_icb_rsp_rdata(bufout_agu_icb_rsp_rdata)

  );
  
  


  redundant_exu u_redundant_exu(













  .core_mhartid(core_mhartid),
  .dbg_irq_r(dbg_irq_r),
  .lcl_irq_r(lcl_irq_r),
  .evt_r(evt_r),
  .ext_irq_r(ext_irq_r),
  .sft_irq_r(sft_irq_r),
  .tmr_irq_r(tmr_irq_r),
















  .dcsr_r(dcsr_r)    ,
  .dpc_r(dpc_r)     ,
  .dscratch_r(dscratch_r),

  .dbg_mode(dbg_mode),
  .dbg_halt_r(dbg_halt_r),
  .dbg_step_r(dbg_step_r),
  .dbg_ebreakm_r(dbg_ebreakm_r),
  .dbg_stopcycle(dbg_stopcycle),





  .i_valid(bufout_ifu_o_valid),

  .i_ir(bufout_ifu_o_ir),
  .i_pc(bufout_ifu_o_pc),
  .i_pc_vld(bufout_ifu_o_pc_vld),
  .i_misalgn(bufout_ifu_o_misalgn),
  .i_buserr(bufout_ifu_o_buserr),
  .i_prdt_taken(bufout_ifu_o_prdt_taken),               
  .i_muldiv_b2b(bufout_ifu_o_muldiv_b2b),               
  .i_rs1idx(bufout_ifu_o_rs1idx),
  .i_rs2idx(bufout_ifu_o_rs2idx),











  .pipe_flush_ack(bufout_pipe_flush_ack),










  .lsu_o_valid(bufout_lsu_o_valid),

  .lsu_o_wbck_wdat(bufout_lsu_o_wbck_wdat),
  .lsu_o_wbck_itag(bufout_lsu_o_wbck_itag),
  .lsu_o_wbck_err(bufout_lsu_o_wbck_err) , 
  .lsu_o_cmt_ld(bufout_lsu_o_cmt_ld),
  .lsu_o_cmt_st(bufout_lsu_o_cmt_st),
  .lsu_o_cmt_badaddr(bufout_lsu_o_cmt_badaddr),
  .lsu_o_cmt_buserr(bufout_lsu_o_cmt_buserr) ,


  .wfi_halt_ifu_ack(bufout_ifu_halt_ack),


















  .agu_icb_cmd_ready(bufout_agu_icb_cmd_ready),


















  .agu_icb_rsp_valid(bufout_agu_icb_rsp_valid),

  .agu_icb_rsp_err(bufout_agu_icb_rsp_err),
  .agu_icb_rsp_excl_ok(bufout_agu_icb_rsp_excl_ok),
  .agu_icb_rsp_rdata(bufout_agu_icb_rsp_rdata),

  `ifdef E203_HAS_CSR_EAI

  .eai_csr_ready(eai_csr_ready),



  .eai_csr_rdata(eai_csr_rdata),
  `endif




  .test_mode(test_mode),
  .clk_aon(clk_aon),
  .clk(clk_core_exu),
  .rst_n(rst_n)
  );



endmodule
module new_core(
  output[`E203_PC_SIZE-1:0] inspect_pc,

  `ifdef E203_HAS_CSR_EAI
  output         eai_csr_valid,
  input          eai_csr_ready,
  output  [31:0] eai_csr_addr,
  output         eai_csr_wr,
  output  [31:0] eai_csr_wdata,
  input   [31:0] eai_csr_rdata,
  `endif
  output core_wfi,
  output tm_stop,
  output core_cgstop,
  output tcm_cgstop,

  input  [`E203_PC_SIZE-1:0] pc_rtvec,

  input  [`E203_HART_ID_W-1:0] core_mhartid,
  input  dbg_irq_r,
  input  [`E203_LIRQ_NUM-1:0] lcl_irq_r,
  input  [`E203_EVT_NUM-1:0] evt_r,
  input  ext_irq_r,
  input  sft_irq_r,
  input  tmr_irq_r,



  output  wr_dcsr_ena    ,
  output  wr_dpc_ena     ,
  output  wr_dscratch_ena,



  output  [32-1:0] wr_csr_nxt    ,

  input  [32-1:0] dcsr_r    ,
  input  [`E203_PC_SIZE-1:0] dpc_r     ,
  input  [32-1:0] dscratch_r,

  output  [`E203_PC_SIZE-1:0] cmt_dpc,
  output  cmt_dpc_ena,
  output  [3-1:0] cmt_dcause,
  output  cmt_dcause_ena,

  input  dbg_mode,
  input  dbg_halt_r,
  input  dbg_step_r,
  input  dbg_ebreakm_r,
  input  dbg_stopcycle,

  `ifdef E203_HAS_ITCM

  input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
  input  ifu2itcm_holdup,






  output ifu2itcm_icb_cmd_valid,
  input  ifu2itcm_icb_cmd_ready,


  output [`E203_ITCM_ADDR_WIDTH-1:0]   ifu2itcm_icb_cmd_addr,


  input  ifu2itcm_icb_rsp_valid,
  output ifu2itcm_icb_rsp_ready,
  input  ifu2itcm_icb_rsp_err,

  input  [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata, 
  `endif





  input [`E203_ADDR_SIZE-1:0]    ppi_region_indic,

  input                          ppi_icb_enable,

  output                         ppi_icb_cmd_valid,
  input                          ppi_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   ppi_icb_cmd_addr, 
  output                         ppi_icb_cmd_read, 
  output [`E203_XLEN-1:0]        ppi_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      ppi_icb_cmd_wmask,
  output                         ppi_icb_cmd_lock,
  output                         ppi_icb_cmd_excl,
  output [1:0]                   ppi_icb_cmd_size,


  input                          ppi_icb_rsp_valid,
  output                         ppi_icb_rsp_ready,
  input                          ppi_icb_rsp_err  ,
  input                          ppi_icb_rsp_excl_ok  ,
  input  [`E203_XLEN-1:0]        ppi_icb_rsp_rdata,

  
  input [`E203_ADDR_SIZE-1:0]    clint_region_indic,
  input                          clint_icb_enable,

  output                         clint_icb_cmd_valid,
  input                          clint_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, 
  output                         clint_icb_cmd_read, 
  output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,
  output                         clint_icb_cmd_lock,
  output                         clint_icb_cmd_excl,
  output [1:0]                   clint_icb_cmd_size,


  input                          clint_icb_rsp_valid,
  output                         clint_icb_rsp_ready,
  input                          clint_icb_rsp_err  ,
  input                          clint_icb_rsp_excl_ok  ,
  input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,

  input [`E203_ADDR_SIZE-1:0]    plic_region_indic,
  input                          plic_icb_enable,

  output                         plic_icb_cmd_valid,
  input                          plic_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, 
  output                         plic_icb_cmd_read, 
  output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,
  output                         plic_icb_cmd_lock,
  output                         plic_icb_cmd_excl,
  output [1:0]                   plic_icb_cmd_size,


  input                          plic_icb_rsp_valid,
  output                         plic_icb_rsp_ready,
  input                          plic_icb_rsp_err  ,
  input                          plic_icb_rsp_excl_ok  ,
  input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,


  `ifdef E203_HAS_FIO



  input [`E203_ADDR_SIZE-1:0]    fio_region_indic,

  input                          fio_icb_enable,

  output                         fio_icb_cmd_valid,
  input                          fio_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   fio_icb_cmd_addr, 
  output                         fio_icb_cmd_read, 
  output [`E203_XLEN-1:0]        fio_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      fio_icb_cmd_wmask,
  output                         fio_icb_cmd_lock,
  output                         fio_icb_cmd_excl,
  output [1:0]                   fio_icb_cmd_size,


  input                          fio_icb_rsp_valid,
  output                         fio_icb_rsp_ready,
  input                          fio_icb_rsp_err  ,
  input                          fio_icb_rsp_excl_ok  ,
  input  [`E203_XLEN-1:0]        fio_icb_rsp_rdata,
  `endif

  `ifdef E203_HAS_MEM_ITF




  input                          mem_icb_enable,

  output                         mem_icb_cmd_valid,
  input                          mem_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   mem_icb_cmd_addr, 
  output                         mem_icb_cmd_read, 
  output [`E203_XLEN-1:0]        mem_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      mem_icb_cmd_wmask,
  output                         mem_icb_cmd_lock,
  output                         mem_icb_cmd_excl,
  output [1:0]                   mem_icb_cmd_size,
  output [1:0]                   mem_icb_cmd_burst,
  output [1:0]                   mem_icb_cmd_beat,


  input                          mem_icb_rsp_valid,
  output                         mem_icb_rsp_ready,
  input                          mem_icb_rsp_err  ,
  input                          mem_icb_rsp_excl_ok  ,
  input  [`E203_XLEN-1:0]        mem_icb_rsp_rdata,
  `endif

  `ifdef E203_HAS_ITCM





  output                         lsu2itcm_icb_cmd_valid,
  input                          lsu2itcm_icb_cmd_ready,
  output [`E203_ITCM_ADDR_WIDTH-1:0]   lsu2itcm_icb_cmd_addr, 
  output                         lsu2itcm_icb_cmd_read, 
  output [`E203_XLEN-1:0]        lsu2itcm_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      lsu2itcm_icb_cmd_wmask,
  output                         lsu2itcm_icb_cmd_lock,
  output                         lsu2itcm_icb_cmd_excl,
  output [1:0]                   lsu2itcm_icb_cmd_size,


  input                          lsu2itcm_icb_rsp_valid,
  output                         lsu2itcm_icb_rsp_ready,
  input                          lsu2itcm_icb_rsp_err  ,
  input                          lsu2itcm_icb_rsp_excl_ok  ,
  input  [`E203_XLEN-1:0]        lsu2itcm_icb_rsp_rdata,
  `endif

    `ifdef E203_HAS_DTCM
  input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,





  output                         lsu2dtcm_icb_cmd_valid,
  input                          lsu2dtcm_icb_cmd_ready,
  output [`E203_DTCM_ADDR_WIDTH-1:0]   lsu2dtcm_icb_cmd_addr, 
  output                         lsu2dtcm_icb_cmd_read, 
  output [`E203_XLEN-1:0]        lsu2dtcm_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      lsu2dtcm_icb_cmd_wmask,
  output                         lsu2dtcm_icb_cmd_lock,
  output                         lsu2dtcm_icb_cmd_excl,
  output [1:0]                   lsu2dtcm_icb_cmd_size,


  input                          lsu2dtcm_icb_rsp_valid,
  output                         lsu2dtcm_icb_rsp_ready,
  input                          lsu2dtcm_icb_rsp_err  ,
  input                          lsu2dtcm_icb_rsp_excl_ok,
  input  [`E203_XLEN-1:0]        lsu2dtcm_icb_rsp_rdata,
  `endif

  output exu_active,
  output ifu_active,
  output lsu_active,
  output biu_active,

  input  clk_core_ifu,
  input  clk_core_exu,
  input  clk_core_lsu,
  input  clk_core_biu,
  input  clk_aon,

  input test_mode,
  input  rst_n
  );


    `ifdef E203_HAS_MEM_ITF
  wire                         ifu2biu_icb_cmd_valid;
  wire                         ifu2biu_icb_cmd_ready;
  wire [`E203_ADDR_SIZE-1:0]   ifu2biu_icb_cmd_addr; 
  wire                         ifu2biu_icb_rsp_valid;
  wire                         ifu2biu_icb_rsp_ready;
  wire                         ifu2biu_icb_rsp_err  ;
  wire                         ifu2biu_icb_rsp_excl_ok;
  wire [`E203_XLEN-1:0]        ifu2biu_icb_rsp_rdata;
   
  `endif




  wire ifu_o_valid;
  wire ifu_o_ready;
  wire [`E203_INSTR_SIZE-1:0] ifu_o_ir;
  wire [`E203_PC_SIZE-1:0] ifu_o_pc;
  wire ifu_o_pc_vld; 
  wire ifu_o_misalgn; 
  wire ifu_o_buserr; 
  wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx;
  wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx;
  wire ifu_o_prdt_taken;
  wire ifu_o_muldiv_b2b;

  wire wfi_halt_ifu_req;
  wire wfi_halt_ifu_ack;
  wire pipe_flush_ack;
  wire pipe_flush_req;
  wire [`E203_PC_SIZE-1:0] pipe_flush_add_op1;  
  wire [`E203_PC_SIZE-1:0] pipe_flush_add_op2;  
  `ifdef E203_TIMING_BOOST
  wire [`E203_PC_SIZE-1:0] pipe_flush_pc;  
  `endif

  wire oitf_empty;
  wire [`E203_XLEN-1:0] rf2ifu_x1;
  wire [`E203_XLEN-1:0] rf2ifu_rs1;
  wire dec2ifu_rden;
  wire dec2ifu_rs1en;
  wire [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx;
  wire dec2ifu_mulhsu;
  wire dec2ifu_div   ;
  wire dec2ifu_rem   ;
  wire dec2ifu_divu  ;
  wire dec2ifu_remu  ;


  wire itcm_nohold;

  e203_ifu u_e203_ifu(
    .inspect_pc   (inspect_pc),

    .ifu_active      (ifu_active),
    .pc_rtvec        (pc_rtvec),  

    .itcm_nohold     (itcm_nohold),

  `ifdef E203_HAS_ITCM
    .ifu2itcm_holdup (ifu2itcm_holdup),



    .itcm_region_indic (itcm_region_indic),

    .ifu2itcm_icb_cmd_valid(ifu2itcm_icb_cmd_valid),
    .ifu2itcm_icb_cmd_ready(ifu2itcm_icb_cmd_ready),
    .ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
    .ifu2itcm_icb_rsp_valid(ifu2itcm_icb_rsp_valid),
    .ifu2itcm_icb_rsp_ready(ifu2itcm_icb_rsp_ready),
    .ifu2itcm_icb_rsp_err  (ifu2itcm_icb_rsp_err  ),
    .ifu2itcm_icb_rsp_rdata(ifu2itcm_icb_rsp_rdata),
  `endif

  `ifdef E203_HAS_MEM_ITF
    .ifu2biu_icb_cmd_valid  (ifu2biu_icb_cmd_valid),
    .ifu2biu_icb_cmd_ready  (ifu2biu_icb_cmd_ready),
    .ifu2biu_icb_cmd_addr   (ifu2biu_icb_cmd_addr ),
    
    .ifu2biu_icb_rsp_valid  (ifu2biu_icb_rsp_valid),
    .ifu2biu_icb_rsp_ready  (ifu2biu_icb_rsp_ready),
    .ifu2biu_icb_rsp_err    (ifu2biu_icb_rsp_err  ),
    .ifu2biu_icb_rsp_rdata  (ifu2biu_icb_rsp_rdata),

  `endif


    .ifu_o_valid            (ifu_o_valid         ),
    .ifu_o_ready            (ifu_o_ready         ),
    .ifu_o_ir               (ifu_o_ir            ),
    .ifu_o_pc               (ifu_o_pc            ),
    .ifu_o_pc_vld           (ifu_o_pc_vld        ),
    .ifu_o_misalgn          (ifu_o_misalgn       ), 
    .ifu_o_buserr           (ifu_o_buserr        ), 
    .ifu_o_rs1idx           (ifu_o_rs1idx        ),
    .ifu_o_rs2idx           (ifu_o_rs2idx        ),
    .ifu_o_prdt_taken       (ifu_o_prdt_taken    ),
    .ifu_o_muldiv_b2b       (ifu_o_muldiv_b2b    ),

    .ifu_halt_req           (wfi_halt_ifu_req),
    .ifu_halt_ack           (wfi_halt_ifu_ack),
    .pipe_flush_ack         (pipe_flush_ack      ),
    .pipe_flush_req         (pipe_flush_req      ),
    .pipe_flush_add_op1     (pipe_flush_add_op1  ),  
    .pipe_flush_add_op2     (pipe_flush_add_op2  ),  
  `ifdef E203_TIMING_BOOST
    .pipe_flush_pc          (pipe_flush_pc),  
  `endif

                                 
    .oitf_empty             (oitf_empty   ),
    .rf2ifu_x1              (rf2ifu_x1    ),
    .rf2ifu_rs1             (rf2ifu_rs1   ),
    .dec2ifu_rden           (dec2ifu_rden ),
    .dec2ifu_rs1en          (dec2ifu_rs1en),
    .dec2ifu_rdidx          (dec2ifu_rdidx),
    .dec2ifu_mulhsu         (dec2ifu_mulhsu),
    .dec2ifu_div            (dec2ifu_div   ),
    .dec2ifu_rem            (dec2ifu_rem   ),
    .dec2ifu_divu           (dec2ifu_divu  ),
    .dec2ifu_remu           (dec2ifu_remu  ),

    .clk                    (clk_core_ifu  ),
    .rst_n                  (rst_n         ) 
  );
  
  


  wire [`E203_PC_SIZE-1:0] bufout_inspect_pc;
  wire bufout_ifu_active;

  `ifdef E203_HAS_ITCM
  wire bufout_ifu2itcm_icb_cmd_valid;
  wire [`E203_ITCM_ADDR_WIDTH-1:0]   bufout_ifu2itcm_icb_cmd_addr;
  wire bufout_ifu2itcm_icb_rsp_ready;
  `endif

  `ifdef E203_HAS_MEM_ITF
  wire bufout_ifu2biu_icb_cmd_valid;
  wire [`E203_ADDR_SIZE-1:0]   bufout_ifu2biu_icb_cmd_addr;
  wire bufout_ifu2biu_icb_rsp_ready;

  `endif
  wire [`E203_INSTR_SIZE-1:0] bufout_ifu_o_ir;
  wire [`E203_PC_SIZE-1:0] bufout_ifu_o_pc;
  wire bufout_ifu_o_pc_vld;
  wire bufout_ifu_o_misalgn;
  wire bufout_ifu_o_buserr;
  wire [`E203_RFIDX_WIDTH-1:0] bufout_ifu_o_rs1idx;
  wire [`E203_RFIDX_WIDTH-1:0] bufout_ifu_o_rs2idx;
  wire bufout_ifu_o_prdt_taken;
  wire bufout_ifu_o_muldiv_b2b;               
  wire bufout_ifu_o_valid;
  wire bufout_pipe_flush_ack;
  `ifdef E203_TIMING_BOOST
  `endif

  wire  bufout_ifu_halt_ack;
  

   wire ifu_buffer_enable; 

  
  ifu_buffer u_ifu_buffer(
  
    .clk(clk_core_ifu),
    .lden(ifu_buffer_enable),  
  
  


      .inspect_pc(bufout_inspect_pc),
      .ifu_active(bufout_ifu_active),

  `ifdef E203_HAS_ITCM
      .ifu2itcm_icb_cmd_valid(bufout_ifu2itcm_icb_cmd_valid),
      .ifu2itcm_icb_cmd_addr(bufout_ifu2itcm_icb_cmd_addr),
      .ifu2itcm_icb_rsp_ready(bufout_ifu2biu_icb_rsp_ready),
  `endif

  `ifdef E203_HAS_MEM_ITF
      .ifu2biu_icb_cmd_valid(bufout_ifu2biu_icb_cmd_valid),
      .ifu2biu_icb_cmd_addr(bufout_ifu2biu_icb_cmd_addr),
      .ifu2biu_icb_rsp_ready(bufout_ifu2biu_icb_rsp_ready),

  `endif
      .ifu_o_ir(bufout_ifu_o_ir),
      .ifu_o_pc(bufout_ifu_o_pc),
      .ifu_o_pc_vld(bufout_ifu_o_pc_vld),
      .ifu_o_misalgn(bufout_ifu_o_misalgn),
      .ifu_o_buserr(bufout_ifu_o_buserr),
      .ifu_o_rs1idx(bufout_ifu_o_rs1idx),
      .ifu_o_rs2idx(bufout_ifu_o_rs2idx),
      .ifu_o_prdt_taken(bufout_ifu_o_prdt_taken),
      .ifu_o_muldiv_b2b(bufout_ifu_o_muldiv_b2b),               
      .ifu_o_valid(bufout_ifu_o_valid),
      .pipe_flush_ack(bufout_pipe_flush_ack),
  `ifdef E203_TIMING_BOOST
  `endif
       .ifu_halt_ack(bufout_ifu_halt_ack),





      .in_inspect_pc(inspect_pc),
      .in_ifu_active(ifu_active),

  `ifdef E203_HAS_ITCM
      .in_ifu2itcm_icb_cmd_valid(ifu2itcm_icb_cmd_valid),
      .in_ifu2itcm_icb_cmd_addr(ifu2itcm_icb_cmd_addr),
      .in_ifu2itcm_icb_rsp_ready(ifu2biu_icb_rsp_ready),
  `endif

  `ifdef E203_HAS_MEM_ITF
      .in_ifu2biu_icb_cmd_valid(ifu2biu_icb_cmd_valid),
      .in_ifu2biu_icb_cmd_addr(ifu2biu_icb_cmd_addr),
      .in_ifu2biu_icb_rsp_ready(ifu2biu_icb_rsp_ready),

  `endif
      .in_ifu_o_ir(ifu_o_ir),
      .in_ifu_o_pc(ifu_o_pc),
      .in_ifu_o_pc_vld(ifu_o_pc_vld),
      .in_ifu_o_misalgn(ifu_o_misalgn),
      .in_ifu_o_buserr(ifu_o_buserr),
      .in_ifu_o_rs1idx(ifu_o_rs1idx),
      .in_ifu_o_rs2idx(ifu_o_rs2idx),
      .in_ifu_o_prdt_taken(ifu_o_prdt_taken),
      .in_ifu_o_muldiv_b2b(ifu_o_muldiv_b2b),               
      .in_ifu_o_valid(ifu_o_valid),
      .in_pipe_flush_ack(pipe_flush_ack),
  `ifdef E203_TIMING_BOOST
  `endif
       .in_ifu_halt_ack(wfi_halt_ifu_ack)  

  );
  
  
  
  
  
  
  
  
  
  

  

  wire                         lsu_o_valid; 
  wire                         lsu_o_ready; 
  wire [`E203_XLEN-1:0]        lsu_o_wbck_wdat;
  wire [`E203_ITAG_WIDTH -1:0] lsu_o_wbck_itag;
  wire                         lsu_o_wbck_err ; 
  wire                         lsu_o_cmt_buserr ; 
  wire                         lsu_o_cmt_ld;
  wire                         lsu_o_cmt_st;
  wire [`E203_ADDR_SIZE -1:0]  lsu_o_cmt_badaddr;

  wire                         agu_icb_cmd_valid; 
  wire                         agu_icb_cmd_ready; 
  wire [`E203_ADDR_SIZE-1:0]   agu_icb_cmd_addr; 
  wire                         agu_icb_cmd_read;   
  wire [`E203_XLEN-1:0]        agu_icb_cmd_wdata; 
  wire [`E203_XLEN/8-1:0]      agu_icb_cmd_wmask; 
  wire                         agu_icb_cmd_lock;
  wire                         agu_icb_cmd_excl;
  wire [1:0]                   agu_icb_cmd_size;
  wire                         agu_icb_cmd_back2agu; 
  wire                         agu_icb_cmd_usign;
  wire [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag;
  wire                         agu_icb_rsp_valid; 
  wire                         agu_icb_rsp_ready; 
  wire                         agu_icb_rsp_err  ; 
  wire                         agu_icb_rsp_excl_ok  ; 
  wire [`E203_XLEN-1:0]        agu_icb_rsp_rdata;

  wire commit_mret;
  wire commit_trap;
  wire excp_active;

  e203_exu u_e203_exu(

  `ifdef E203_HAS_CSR_EAI
    .eai_csr_valid (eai_csr_valid),
    .eai_csr_ready (eai_csr_ready),
    .eai_csr_addr  (eai_csr_addr ),
    .eai_csr_wr    (eai_csr_wr   ),
    .eai_csr_wdata (eai_csr_wdata),
    .eai_csr_rdata (eai_csr_rdata),
  `endif


    .excp_active            (excp_active),
    .commit_mret            (commit_mret),
    .commit_trap            (commit_trap),
    .test_mode              (test_mode),
    .core_wfi               (core_wfi),
    .tm_stop                (tm_stop),
    .itcm_nohold            (itcm_nohold),
    .core_cgstop            (core_cgstop),
    .tcm_cgstop             (tcm_cgstop),
    .exu_active             (exu_active),

    .core_mhartid           (core_mhartid),
    .dbg_irq_r              (dbg_irq_r),
    .lcl_irq_r              (lcl_irq_r    ),
    .ext_irq_r              (ext_irq_r    ),
    .sft_irq_r              (sft_irq_r    ),
    .tmr_irq_r              (tmr_irq_r    ),
    .evt_r                  (evt_r    ),

    .cmt_dpc                (cmt_dpc        ),
    .cmt_dpc_ena            (cmt_dpc_ena    ),
    .cmt_dcause             (cmt_dcause     ),
    .cmt_dcause_ena         (cmt_dcause_ena ),

    .wr_dcsr_ena     (wr_dcsr_ena    ),
    .wr_dpc_ena      (wr_dpc_ena     ),
    .wr_dscratch_ena (wr_dscratch_ena),


                                     
    .wr_csr_nxt      (wr_csr_nxt    ),
                                     
    .dcsr_r          (dcsr_r         ),
    .dpc_r           (dpc_r          ),
    .dscratch_r      (dscratch_r     ),

    .dbg_mode               (dbg_mode  ),
    .dbg_halt_r             (dbg_halt_r),
    .dbg_step_r             (dbg_step_r),
    .dbg_ebreakm_r          (dbg_ebreakm_r),
    .dbg_stopcycle          (dbg_stopcycle),

    .i_valid                (ifu_o_valid         ),
    .i_ready                (ifu_o_ready         ),
    .i_ir                   (ifu_o_ir            ),
    .i_pc                   (ifu_o_pc            ),
    .i_pc_vld               (ifu_o_pc_vld        ),
    .i_misalgn              (ifu_o_misalgn       ), 
    .i_buserr               (ifu_o_buserr        ), 
    .i_rs1idx               (ifu_o_rs1idx        ),
    .i_rs2idx               (ifu_o_rs2idx        ),
    .i_prdt_taken           (ifu_o_prdt_taken    ),
    .i_muldiv_b2b           (ifu_o_muldiv_b2b    ),

    .wfi_halt_ifu_req       (wfi_halt_ifu_req),
    .wfi_halt_ifu_ack       (wfi_halt_ifu_ack),

    .pipe_flush_ack         (pipe_flush_ack      ),
    .pipe_flush_req         (pipe_flush_req      ),
    .pipe_flush_add_op1     (pipe_flush_add_op1  ),  
    .pipe_flush_add_op2     (pipe_flush_add_op2  ),  
  `ifdef E203_TIMING_BOOST
    .pipe_flush_pc          (pipe_flush_pc),  
  `endif

    .lsu_o_valid            (lsu_o_valid   ),
    .lsu_o_ready            (lsu_o_ready   ),
    .lsu_o_wbck_wdat        (lsu_o_wbck_wdat    ),
    .lsu_o_wbck_itag        (lsu_o_wbck_itag    ),
    .lsu_o_wbck_err         (lsu_o_wbck_err     ),
    .lsu_o_cmt_buserr       (lsu_o_cmt_buserr     ),
    .lsu_o_cmt_ld           (lsu_o_cmt_ld),
    .lsu_o_cmt_st           (lsu_o_cmt_st),
    .lsu_o_cmt_badaddr      (lsu_o_cmt_badaddr     ),

    .agu_icb_cmd_valid      (agu_icb_cmd_valid   ),
    .agu_icb_cmd_ready      (agu_icb_cmd_ready   ),
    .agu_icb_cmd_addr       (agu_icb_cmd_addr    ),
    .agu_icb_cmd_read       (agu_icb_cmd_read    ),
    .agu_icb_cmd_wdata      (agu_icb_cmd_wdata   ),
    .agu_icb_cmd_wmask      (agu_icb_cmd_wmask   ),
    .agu_icb_cmd_lock       (agu_icb_cmd_lock    ),
    .agu_icb_cmd_excl       (agu_icb_cmd_excl    ),
    .agu_icb_cmd_size       (agu_icb_cmd_size    ),
    .agu_icb_cmd_back2agu   (agu_icb_cmd_back2agu),
    .agu_icb_cmd_usign      (agu_icb_cmd_usign   ),
    .agu_icb_cmd_itag       (agu_icb_cmd_itag    ),
    .agu_icb_rsp_valid      (agu_icb_rsp_valid   ),
    .agu_icb_rsp_ready      (agu_icb_rsp_ready   ),
    .agu_icb_rsp_err        (agu_icb_rsp_err     ),
    .agu_icb_rsp_excl_ok    (agu_icb_rsp_excl_ok ),
    .agu_icb_rsp_rdata      (agu_icb_rsp_rdata   ),

    .oitf_empty             (oitf_empty   ),
    .rf2ifu_x1              (rf2ifu_x1    ),
    .rf2ifu_rs1             (rf2ifu_rs1   ),
    .dec2ifu_rden           (dec2ifu_rden ),
    .dec2ifu_rs1en          (dec2ifu_rs1en),
    .dec2ifu_rdidx          (dec2ifu_rdidx),
    .dec2ifu_mulhsu         (dec2ifu_mulhsu),
    .dec2ifu_div            (dec2ifu_div   ),
    .dec2ifu_rem            (dec2ifu_rem   ),
    .dec2ifu_divu           (dec2ifu_divu  ),
    .dec2ifu_remu           (dec2ifu_remu  ),


    .clk_aon                (clk_aon),
    .clk                    (clk_core_exu),
    .rst_n                  (rst_n  ) 
  );

  wire                         lsu2biu_icb_cmd_valid;
  wire                         lsu2biu_icb_cmd_ready;
  wire [`E203_ADDR_SIZE-1:0]   lsu2biu_icb_cmd_addr; 
  wire                         lsu2biu_icb_cmd_read; 
  wire [`E203_XLEN-1:0]        lsu2biu_icb_cmd_wdata;
  wire [`E203_XLEN/8-1:0]      lsu2biu_icb_cmd_wmask;
  wire                         lsu2biu_icb_cmd_lock;
  wire                         lsu2biu_icb_cmd_excl;
  wire [1:0]                   lsu2biu_icb_cmd_size;

  wire                         lsu2biu_icb_rsp_valid;
  wire                         lsu2biu_icb_rsp_ready;
  wire                         lsu2biu_icb_rsp_err  ;
  wire                         lsu2biu_icb_rsp_excl_ok;
  wire [`E203_XLEN-1:0]        lsu2biu_icb_rsp_rdata;

  e203_lsu u_e203_lsu(
    .excp_active         (excp_active),
    .commit_mret            (commit_mret),
    .commit_trap         (commit_trap),
    .lsu_active          (lsu_active),
    .lsu_o_valid         (lsu_o_valid   ),
    .lsu_o_ready         (lsu_o_ready   ),
    .lsu_o_wbck_wdat     (lsu_o_wbck_wdat    ),
    .lsu_o_wbck_itag     (lsu_o_wbck_itag    ),
    .lsu_o_wbck_err      (lsu_o_wbck_err     ),
    .lsu_o_cmt_buserr    (lsu_o_cmt_buserr     ),
    .lsu_o_cmt_ld        (lsu_o_cmt_ld),
    .lsu_o_cmt_st        (lsu_o_cmt_st),
    .lsu_o_cmt_badaddr   (lsu_o_cmt_badaddr     ),
                        
    .agu_icb_cmd_valid   (agu_icb_cmd_valid ),
    .agu_icb_cmd_ready   (agu_icb_cmd_ready ),
    .agu_icb_cmd_addr    (agu_icb_cmd_addr  ),
    .agu_icb_cmd_read    (agu_icb_cmd_read  ),
    .agu_icb_cmd_wdata   (agu_icb_cmd_wdata ),
    .agu_icb_cmd_wmask   (agu_icb_cmd_wmask ),
    .agu_icb_cmd_lock    (agu_icb_cmd_lock  ),
    .agu_icb_cmd_excl    (agu_icb_cmd_excl  ),
    .agu_icb_cmd_size    (agu_icb_cmd_size  ),
   
    .agu_icb_cmd_back2agu(agu_icb_cmd_back2agu ),
    .agu_icb_cmd_usign   (agu_icb_cmd_usign),
    .agu_icb_cmd_itag    (agu_icb_cmd_itag),
  
    .agu_icb_rsp_valid   (agu_icb_rsp_valid ),
    .agu_icb_rsp_ready   (agu_icb_rsp_ready ),
    .agu_icb_rsp_err     (agu_icb_rsp_err   ),
    .agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok),
    .agu_icb_rsp_rdata   (agu_icb_rsp_rdata),



  `ifdef E203_HAS_ITCM
    .itcm_region_indic   (itcm_region_indic),
    .itcm_icb_cmd_valid  (lsu2itcm_icb_cmd_valid),
    .itcm_icb_cmd_ready  (lsu2itcm_icb_cmd_ready),
    .itcm_icb_cmd_addr   (lsu2itcm_icb_cmd_addr ),
    .itcm_icb_cmd_read   (lsu2itcm_icb_cmd_read ),
    .itcm_icb_cmd_wdata  (lsu2itcm_icb_cmd_wdata),
    .itcm_icb_cmd_wmask  (lsu2itcm_icb_cmd_wmask),
    .itcm_icb_cmd_lock   (lsu2itcm_icb_cmd_lock ),
    .itcm_icb_cmd_excl   (lsu2itcm_icb_cmd_excl ),
    .itcm_icb_cmd_size   (lsu2itcm_icb_cmd_size ),
     
    .itcm_icb_rsp_valid  (lsu2itcm_icb_rsp_valid),
    .itcm_icb_rsp_ready  (lsu2itcm_icb_rsp_ready),
    .itcm_icb_rsp_err    (lsu2itcm_icb_rsp_err  ),
    .itcm_icb_rsp_excl_ok(lsu2itcm_icb_rsp_excl_ok  ),
    .itcm_icb_rsp_rdata  (lsu2itcm_icb_rsp_rdata),

  `endif

  `ifdef E203_HAS_DTCM
    .dtcm_region_indic   (dtcm_region_indic),

    .dtcm_icb_cmd_valid  (lsu2dtcm_icb_cmd_valid),
    .dtcm_icb_cmd_ready  (lsu2dtcm_icb_cmd_ready),
    .dtcm_icb_cmd_addr   (lsu2dtcm_icb_cmd_addr ),
    .dtcm_icb_cmd_read   (lsu2dtcm_icb_cmd_read ),
    .dtcm_icb_cmd_wdata  (lsu2dtcm_icb_cmd_wdata),
    .dtcm_icb_cmd_wmask  (lsu2dtcm_icb_cmd_wmask),
    .dtcm_icb_cmd_lock   (lsu2dtcm_icb_cmd_lock ),
    .dtcm_icb_cmd_excl   (lsu2dtcm_icb_cmd_excl ),
    .dtcm_icb_cmd_size   (lsu2dtcm_icb_cmd_size ),
     
    .dtcm_icb_rsp_valid  (lsu2dtcm_icb_rsp_valid),
    .dtcm_icb_rsp_ready  (lsu2dtcm_icb_rsp_ready),
    .dtcm_icb_rsp_err    (lsu2dtcm_icb_rsp_err  ),
    .dtcm_icb_rsp_excl_ok(lsu2dtcm_icb_rsp_excl_ok  ),
    .dtcm_icb_rsp_rdata  (lsu2dtcm_icb_rsp_rdata),

  `endif

    .biu_icb_cmd_valid  (lsu2biu_icb_cmd_valid),
    .biu_icb_cmd_ready  (lsu2biu_icb_cmd_ready),
    .biu_icb_cmd_addr   (lsu2biu_icb_cmd_addr ),
    .biu_icb_cmd_read   (lsu2biu_icb_cmd_read ),
    .biu_icb_cmd_wdata  (lsu2biu_icb_cmd_wdata),
    .biu_icb_cmd_wmask  (lsu2biu_icb_cmd_wmask),
    .biu_icb_cmd_lock   (lsu2biu_icb_cmd_lock ),
    .biu_icb_cmd_excl   (lsu2biu_icb_cmd_excl ),
    .biu_icb_cmd_size   (lsu2biu_icb_cmd_size ),
    
    .biu_icb_rsp_valid  (lsu2biu_icb_rsp_valid),
    .biu_icb_rsp_ready  (lsu2biu_icb_rsp_ready),
    .biu_icb_rsp_err    (lsu2biu_icb_rsp_err  ),
    .biu_icb_rsp_excl_ok(lsu2biu_icb_rsp_excl_ok),
    .biu_icb_rsp_rdata  (lsu2biu_icb_rsp_rdata),

    .clk           (clk_core_lsu ),
    .rst_n         (rst_n        ) 
  );


  e203_biu u_e203_biu(


    .biu_active             (biu_active),

    .lsu2biu_icb_cmd_valid  (lsu2biu_icb_cmd_valid),
    .lsu2biu_icb_cmd_ready  (lsu2biu_icb_cmd_ready),
    .lsu2biu_icb_cmd_addr   (lsu2biu_icb_cmd_addr ),
    .lsu2biu_icb_cmd_read   (lsu2biu_icb_cmd_read ),
    .lsu2biu_icb_cmd_wdata  (lsu2biu_icb_cmd_wdata),
    .lsu2biu_icb_cmd_wmask  (lsu2biu_icb_cmd_wmask),
    .lsu2biu_icb_cmd_lock   (lsu2biu_icb_cmd_lock ),
    .lsu2biu_icb_cmd_excl   (lsu2biu_icb_cmd_excl ),
    .lsu2biu_icb_cmd_size   (lsu2biu_icb_cmd_size ),
    .lsu2biu_icb_cmd_burst  (2'b0),
    .lsu2biu_icb_cmd_beat   (2'b0 ),

    .lsu2biu_icb_rsp_valid  (lsu2biu_icb_rsp_valid),
    .lsu2biu_icb_rsp_ready  (lsu2biu_icb_rsp_ready),
    .lsu2biu_icb_rsp_err    (lsu2biu_icb_rsp_err  ),
    .lsu2biu_icb_rsp_excl_ok(lsu2biu_icb_rsp_excl_ok),
    .lsu2biu_icb_rsp_rdata  (lsu2biu_icb_rsp_rdata),

  `ifdef E203_HAS_MEM_ITF
    .ifu2biu_icb_cmd_valid  (ifu2biu_icb_cmd_valid),
    .ifu2biu_icb_cmd_ready  (ifu2biu_icb_cmd_ready),
    .ifu2biu_icb_cmd_addr   (ifu2biu_icb_cmd_addr ),
    .ifu2biu_icb_cmd_read   (1'b1 ),
    .ifu2biu_icb_cmd_wdata  (`E203_XLEN'b0),
    .ifu2biu_icb_cmd_wmask  ({`E203_XLEN/8{1'b0}}),
    .ifu2biu_icb_cmd_lock   (1'b0 ),
    .ifu2biu_icb_cmd_excl   (1'b0 ),
    .ifu2biu_icb_cmd_size   (2'b10),
    .ifu2biu_icb_cmd_burst  (2'b0),
    .ifu2biu_icb_cmd_beat   (2'b0),
    
    .ifu2biu_icb_rsp_valid  (ifu2biu_icb_rsp_valid),
    .ifu2biu_icb_rsp_ready  (ifu2biu_icb_rsp_ready),
    .ifu2biu_icb_rsp_err    (ifu2biu_icb_rsp_err  ),
    .ifu2biu_icb_rsp_excl_ok(ifu2biu_icb_rsp_excl_ok),
    .ifu2biu_icb_rsp_rdata  (ifu2biu_icb_rsp_rdata),

  `endif

    .ppi_region_indic      (ppi_region_indic ),
    .ppi_icb_enable        (ppi_icb_enable),
    .ppi_icb_cmd_valid     (ppi_icb_cmd_valid),
    .ppi_icb_cmd_ready     (ppi_icb_cmd_ready),
    .ppi_icb_cmd_addr      (ppi_icb_cmd_addr ),
    .ppi_icb_cmd_read      (ppi_icb_cmd_read ),
    .ppi_icb_cmd_wdata     (ppi_icb_cmd_wdata),
    .ppi_icb_cmd_wmask     (ppi_icb_cmd_wmask),
    .ppi_icb_cmd_lock      (ppi_icb_cmd_lock ),
    .ppi_icb_cmd_excl      (ppi_icb_cmd_excl ),
    .ppi_icb_cmd_size      (ppi_icb_cmd_size ),
    .ppi_icb_cmd_burst     (),
    .ppi_icb_cmd_beat      (),
    
    .ppi_icb_rsp_valid     (ppi_icb_rsp_valid),
    .ppi_icb_rsp_ready     (ppi_icb_rsp_ready),
    .ppi_icb_rsp_err       (ppi_icb_rsp_err  ),
    .ppi_icb_rsp_excl_ok   (ppi_icb_rsp_excl_ok),
    .ppi_icb_rsp_rdata     (ppi_icb_rsp_rdata),


    .plic_icb_enable        (plic_icb_enable),
    .plic_region_indic      (plic_region_indic ),
    .plic_icb_cmd_valid     (plic_icb_cmd_valid),
    .plic_icb_cmd_ready     (plic_icb_cmd_ready),
    .plic_icb_cmd_addr      (plic_icb_cmd_addr ),
    .plic_icb_cmd_read      (plic_icb_cmd_read ),
    .plic_icb_cmd_wdata     (plic_icb_cmd_wdata),
    .plic_icb_cmd_wmask     (plic_icb_cmd_wmask),
    .plic_icb_cmd_lock      (plic_icb_cmd_lock ),
    .plic_icb_cmd_excl      (plic_icb_cmd_excl ),
    .plic_icb_cmd_size      (plic_icb_cmd_size ),
    .plic_icb_cmd_burst     (),
    .plic_icb_cmd_beat      (),
    
    .plic_icb_rsp_valid     (plic_icb_rsp_valid),
    .plic_icb_rsp_ready     (plic_icb_rsp_ready),
    .plic_icb_rsp_err       (plic_icb_rsp_err  ),
    .plic_icb_rsp_excl_ok   (plic_icb_rsp_excl_ok),
    .plic_icb_rsp_rdata     (plic_icb_rsp_rdata),

    .clint_icb_enable        (clint_icb_enable),
    .clint_region_indic      (clint_region_indic ),
    .clint_icb_cmd_valid     (clint_icb_cmd_valid),
    .clint_icb_cmd_ready     (clint_icb_cmd_ready),
    .clint_icb_cmd_addr      (clint_icb_cmd_addr ),
    .clint_icb_cmd_read      (clint_icb_cmd_read ),
    .clint_icb_cmd_wdata     (clint_icb_cmd_wdata),
    .clint_icb_cmd_wmask     (clint_icb_cmd_wmask),
    .clint_icb_cmd_lock      (clint_icb_cmd_lock ),
    .clint_icb_cmd_excl      (clint_icb_cmd_excl ),
    .clint_icb_cmd_size      (clint_icb_cmd_size ),
    .clint_icb_cmd_burst     (),
    .clint_icb_cmd_beat      (),
    
    .clint_icb_rsp_valid     (clint_icb_rsp_valid),
    .clint_icb_rsp_ready     (clint_icb_rsp_ready),
    .clint_icb_rsp_err       (clint_icb_rsp_err  ),
    .clint_icb_rsp_excl_ok   (clint_icb_rsp_excl_ok),
    .clint_icb_rsp_rdata     (clint_icb_rsp_rdata),


  `ifdef E203_HAS_FIO
    .fio_region_indic      (fio_region_indic ),
    .fio_icb_enable        (fio_icb_enable),
    .fio_icb_cmd_valid     (fio_icb_cmd_valid),
    .fio_icb_cmd_ready     (fio_icb_cmd_ready),
    .fio_icb_cmd_addr      (fio_icb_cmd_addr ),
    .fio_icb_cmd_read      (fio_icb_cmd_read ),
    .fio_icb_cmd_wdata     (fio_icb_cmd_wdata),
    .fio_icb_cmd_wmask     (fio_icb_cmd_wmask),
    .fio_icb_cmd_lock      (fio_icb_cmd_lock ),
    .fio_icb_cmd_excl      (fio_icb_cmd_excl ),
    .fio_icb_cmd_size      (fio_icb_cmd_size ),
    .fio_icb_cmd_burst     (),
    .fio_icb_cmd_beat      (),
    
    .fio_icb_rsp_valid     (fio_icb_rsp_valid),
    .fio_icb_rsp_ready     (fio_icb_rsp_ready),
    .fio_icb_rsp_err       (fio_icb_rsp_err  ),
    .fio_icb_rsp_excl_ok   (fio_icb_rsp_excl_ok  ),
    .fio_icb_rsp_rdata     (fio_icb_rsp_rdata),
  `endif

  `ifdef E203_HAS_MEM_ITF
    .mem_icb_enable        (mem_icb_enable),
    .mem_icb_cmd_valid     (mem_icb_cmd_valid),
    .mem_icb_cmd_ready     (mem_icb_cmd_ready),
    .mem_icb_cmd_addr      (mem_icb_cmd_addr ),
    .mem_icb_cmd_read      (mem_icb_cmd_read ),
    .mem_icb_cmd_wdata     (mem_icb_cmd_wdata),
    .mem_icb_cmd_wmask     (mem_icb_cmd_wmask),
    .mem_icb_cmd_lock      (mem_icb_cmd_lock ),
    .mem_icb_cmd_excl      (mem_icb_cmd_excl ),
    .mem_icb_cmd_size      (mem_icb_cmd_size ),
    .mem_icb_cmd_burst     (mem_icb_cmd_burst),
    .mem_icb_cmd_beat      (mem_icb_cmd_beat ),
    
    .mem_icb_rsp_valid     (mem_icb_rsp_valid),
    .mem_icb_rsp_ready     (mem_icb_rsp_ready),
    .mem_icb_rsp_err       (mem_icb_rsp_err  ),
    .mem_icb_rsp_excl_ok   (mem_icb_rsp_excl_ok  ),
    .mem_icb_rsp_rdata     (mem_icb_rsp_rdata),
  `endif

    .clk                    (clk_core_biu ),
    .rst_n                  (rst_n        ) 
  );
  


  wire bufout_lsu_o_valid;
  wire [`E203_XLEN-1:0] bufout_lsu_o_wbck_wdat;
  wire [`E203_ITAG_WIDTH -1:0] bufout_lsu_o_wbck_itag;
  wire bufout_lsu_o_wbck_err; 
  wire bufout_lsu_o_cmt_ld;
  wire bufout_lsu_o_cmt_st;
  wire [`E203_ADDR_SIZE -1:0] bufout_lsu_o_cmt_badaddr;
  wire bufout_lsu_o_cmt_buserr;
  wire bufout_agu_icb_cmd_ready;
  wire bufout_agu_icb_rsp_valid;
  wire bufout_agu_icb_rsp_err;
  wire bufout_agu_icb_rsp_excl_ok;
  wire [`E203_XLEN-1:0]  bufout_agu_icb_rsp_rdata;

  

   wire lsu_buffer_enable; 



  lsu_buffer u_lsu_buffer(
  
   .clk(clk_core_lsu),
   .lden(lsu_buffer_enable),  





  .in_lsu_o_valid(lsu_o_valid),
  .in_lsu_o_wbck_wdat(lsu_o_wbck_wdat),
  .in_lsu_o_wbck_itag(lsu_o_wbck_itag),
  .in_lsu_o_wbck_err(lsu_o_wbck_err), 
  .in_lsu_o_cmt_ld(lsu_o_cmt_ld),
  .in_lsu_o_cmt_st(lsu_o_cmt_st),
  .in_lsu_o_cmt_badaddr(lsu_o_cmt_badaddr),
  .in_lsu_o_cmt_buserr(lsu_o_cmt_buserr),
  .in_agu_icb_cmd_ready(agu_icb_cmd_ready),
  .in_agu_icb_rsp_valid(agu_icb_rsp_valid),
  .in_agu_icb_rsp_err(agu_icb_rsp_err),
  .in_agu_icb_rsp_excl_ok(agu_icb_rsp_excl_ok),
  .in_agu_icb_rsp_rdata(agu_icb_rsp_rdata),







  .lsu_o_valid(bufout_lsu_o_valid),
  .lsu_o_wbck_wdat(bufout_lsu_o_wbck_wdat),
  .lsu_o_wbck_itag(bufout_lsu_o_wbck_itag),
  .lsu_o_wbck_err(bufout_lsu_o_wbck_err), 
  .lsu_o_cmt_ld(bufout_lsu_o_cmt_ld),
  .lsu_o_cmt_st(bufout_lsu_o_cmt_st),
  .lsu_o_cmt_badaddr(bufout_lsu_o_cmt_badaddr),
  .lsu_o_cmt_buserr(bufout_lsu_o_cmt_buserr),
  .agu_icb_cmd_ready(bufout_agu_icb_cmd_ready),
  .agu_icb_rsp_valid(bufout_agu_icb_rsp_valid),
  .agu_icb_rsp_err(bufout_agu_icb_rsp_err),
  .agu_icb_rsp_excl_ok(bufout_agu_icb_rsp_excl_ok),
  .agu_icb_rsp_rdata(bufout_agu_icb_rsp_rdata)

  );
  
  


  redundant_exu u_redundant_exu(













  .core_mhartid(core_mhartid),
  .dbg_irq_r(dbg_irq_r),
  .lcl_irq_r(lcl_irq_r),
  .evt_r(evt_r),
  .ext_irq_r(ext_irq_r),
  .sft_irq_r(sft_irq_r),
  .tmr_irq_r(tmr_irq_r),
















  .dcsr_r(dcsr_r)    ,
  .dpc_r(dpc_r)     ,
  .dscratch_r(dscratch_r),

  .dbg_mode(dbg_mode),
  .dbg_halt_r(dbg_halt_r),
  .dbg_step_r(dbg_step_r),
  .dbg_ebreakm_r(dbg_ebreakm_r),
  .dbg_stopcycle(dbg_stopcycle),





  .i_valid(bufout_ifu_o_valid),

  .i_ir(bufout_ifu_o_ir),
  .i_pc(bufout_ifu_o_pc),
  .i_pc_vld(bufout_ifu_o_pc_vld),
  .i_misalgn(bufout_ifu_o_misalgn),
  .i_buserr(bufout_ifu_o_buserr),
  .i_prdt_taken(bufout_ifu_o_prdt_taken),               
  .i_muldiv_b2b(bufout_ifu_o_muldiv_b2b),               
  .i_rs1idx(bufout_ifu_o_rs1idx),
  .i_rs2idx(bufout_ifu_o_rs2idx),











  .pipe_flush_ack(bufout_pipe_flush_ack),










  .lsu_o_valid(bufout_lsu_o_valid),

  .lsu_o_wbck_wdat(bufout_lsu_o_wbck_wdat),
  .lsu_o_wbck_itag(bufout_lsu_o_wbck_itag),
  .lsu_o_wbck_err(bufout_lsu_o_wbck_err) , 
  .lsu_o_cmt_ld(bufout_lsu_o_cmt_ld),
  .lsu_o_cmt_st(bufout_lsu_o_cmt_st),
  .lsu_o_cmt_badaddr(bufout_lsu_o_cmt_badaddr),
  .lsu_o_cmt_buserr(bufout_lsu_o_cmt_buserr) ,


  .wfi_halt_ifu_ack(bufout_ifu_halt_ack),


















  .agu_icb_cmd_ready(bufout_agu_icb_cmd_ready),


















  .agu_icb_rsp_valid(bufout_agu_icb_rsp_valid),

  .agu_icb_rsp_err(bufout_agu_icb_rsp_err),
  .agu_icb_rsp_excl_ok(bufout_agu_icb_rsp_excl_ok),
  .agu_icb_rsp_rdata(bufout_agu_icb_rsp_rdata),

  `ifdef E203_HAS_CSR_EAI

  .eai_csr_ready(eai_csr_ready),



  .eai_csr_rdata(eai_csr_rdata),
  `endif




  .test_mode(test_mode),
  .clk_aon(clk_aon),
  .clk(clk_core_exu),
  .rst_n(rst_n)
  );



endmodule