data/full_repos/permissive/10003806/cpu.v
1: b'%Error: data/full_repos/permissive/10003806/cpu.v:80: Cannot find file containing module: \'instruction_rom\'\n    instruction_rom #(.ADDR_WIDTH(IADDR_WIDTH)) rom (\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/instruction_rom\n             data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/instruction_rom.v\n             data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/instruction_rom.sv\n             instruction_rom\n             instruction_rom.v\n             instruction_rom.sv\n             obj_dir/instruction_rom\n             obj_dir/instruction_rom.v\n             obj_dir/instruction_rom.sv\n%Error: data/full_repos/permissive/10003806/cpu.v:85: Cannot find file containing module: \'data_ram\'\n    data_ram #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(DADDR_WIDTH), .INIT_RAM(INIT_RAM)) ram (\n    ^~~~~~~~\n%Error: data/full_repos/permissive/10003806/cpu.v:93: Cannot find file containing module: \'stack\'\n    stack #(.DATA_WIDTH(IADDR_WIDTH), .ADDR_WIDTH(SADDR_WIDTH)) loop_stack (\n    ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/10003806/cpu.v:113: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                             : ... In instance cpu\n        data_out = 32\'bX;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/10003806/cpu.v:116: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                             : ... In instance cpu\n        data_to_ram = 32\'bX;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/10003806/cpu.v:118: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                             : ... In instance cpu\n        stack_data = 32\'bX;\n                   ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module cpu(clk, data_in, data_available, data_out, data_out_en, data_read);


    parameter IADDR_WIDTH = 8;


    parameter DADDR_WIDTH = 15;


    parameter SADDR_WIDTH = 5;


    parameter DATA_WIDTH = 8;


    parameter INIT_RAM = 0;


    output reg [DATA_WIDTH - 1:0] data_out;
    output reg                  data_out_en;
    output reg                  data_read;

    input                       clk;

    input [DATA_WIDTH - 1:0]    data_in;
    input                       data_available;


    reg  [IADDR_WIDTH - 1:0]    pc;
    reg  [DADDR_WIDTH - 1:0]    dp;
    reg  [SADDR_WIDTH - 1:0]    lsc;



    wire [3:0]                  ci;

    wire [DATA_WIDTH - 1:0]     data_from_ram;
    reg  [DATA_WIDTH - 1:0]     data_to_ram;
    reg                         ram_write;

    wire [IADDR_WIDTH - 1:0]    stack_top;
    reg  [IADDR_WIDTH - 1:0]    stack_data;
    reg                         stack_push;
    reg                         stack_pop;

    reg  [IADDR_WIDTH - 1:0]    next_pc;
    reg  [DADDR_WIDTH - 1:0]    next_dp;
    reg  [SADDR_WIDTH - 1:0]    next_lsc;


    instruction_rom #(.ADDR_WIDTH(IADDR_WIDTH)) rom (
        .address(pc),
        .data_out(ci)
    );

    data_ram #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(DADDR_WIDTH), .INIT_RAM(INIT_RAM)) ram (
        .data_out(data_from_ram),
        .clk(clk),
        .address(next_dp),
        .data_in(data_to_ram),
        .write(ram_write)
    );

    stack #(.DATA_WIDTH(IADDR_WIDTH), .ADDR_WIDTH(SADDR_WIDTH)) loop_stack (
        .top(stack_top),
        .clk(clk),
        .pushd(stack_data),
        .push_en(stack_push),
        .pop_en(stack_pop)
    );


    initial
    begin
        pc = 0;
        dp = 0;
        lsc = 0;
    end


    always @(*)
    begin

        data_out = 32'bX;
        data_out_en = 0;
        data_read = 0;
        data_to_ram = 32'bX;
        ram_write = 0;
        stack_data = 32'bX;
        stack_push = 0;
        stack_pop = 0;
        next_dp = dp;
        next_pc = pc + 1'b1;
        next_lsc = lsc;


        if (lsc == 0)
        begin

            case (ci)
                4'h0:
                    begin

                        next_pc = pc;
                    end

                4'h8:
                    begin

                        next_dp = dp + 1'b1;
                    end

                4'h9:
                    begin

                        next_dp = dp - 1'b1;
                    end

                4'hA:
                    begin

                        data_to_ram = data_from_ram + 1'b1;
                        ram_write = 1;
                    end

                4'hB:
                    begin

                        data_to_ram = data_from_ram - 1'b1;
                        ram_write = 1;
                    end

                4'hC:
                    begin

                        if (data_from_ram == 0)
                        begin

                            next_lsc = 1;
                        end
                        else
                        begin

                            stack_data = next_pc;
                            stack_push = 1;
                        end
                    end

                4'hD:
                    begin

                        if (data_from_ram == 0)
                            stack_pop = 1;
                        else
                            next_pc = stack_top;
                    end

                4'hE:
                    begin

                        data_out = data_from_ram;
                        data_out_en = 1;
                    end

                4'hF:
                    begin

                        if (data_available)
                        begin

                            data_to_ram = data_in;
                            ram_write = 1;
                            data_read = 1;
                        end
                        else
                        begin

                            next_pc = pc;
                        end
                    end


            endcase
        end
        else
        begin

            case (ci)
                4'hC:
                    begin

                        next_lsc = lsc + 1'b1;
                    end

                4'hD:
                    begin

                        next_lsc = lsc - 1'b1;
                    end
            endcase
        end
    end


    always @(posedge clk)
    begin

        pc <= next_pc;
        dp <= next_dp;
        lsc <= next_lsc;
    end
endmodule
module cpu(clk, data_in, data_available, data_out, data_out_en, data_read);



    parameter IADDR_WIDTH = 8;


    parameter DADDR_WIDTH = 15;


    parameter SADDR_WIDTH = 5;


    parameter DATA_WIDTH = 8;


    parameter INIT_RAM = 0;


    output reg [DATA_WIDTH - 1:0] data_out;
    output reg                  data_out_en;
    output reg                  data_read;

    input                       clk;

    input [DATA_WIDTH - 1:0]    data_in;
    input                       data_available;


    reg  [IADDR_WIDTH - 1:0]    pc;
    reg  [DADDR_WIDTH - 1:0]    dp;
    reg  [SADDR_WIDTH - 1:0]    lsc;



    wire [3:0]                  ci;

    wire [DATA_WIDTH - 1:0]     data_from_ram;
    reg  [DATA_WIDTH - 1:0]     data_to_ram;
    reg                         ram_write;

    wire [IADDR_WIDTH - 1:0]    stack_top;
    reg  [IADDR_WIDTH - 1:0]    stack_data;
    reg                         stack_push;
    reg                         stack_pop;

    reg  [IADDR_WIDTH - 1:0]    next_pc;
    reg  [DADDR_WIDTH - 1:0]    next_dp;
    reg  [SADDR_WIDTH - 1:0]    next_lsc;


    instruction_rom #(.ADDR_WIDTH(IADDR_WIDTH)) rom (
        .address(pc),
        .data_out(ci)
    );

    data_ram #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(DADDR_WIDTH), .INIT_RAM(INIT_RAM)) ram (
        .data_out(data_from_ram),
        .clk(clk),
        .address(next_dp),
        .data_in(data_to_ram),
        .write(ram_write)
    );

    stack #(.DATA_WIDTH(IADDR_WIDTH), .ADDR_WIDTH(SADDR_WIDTH)) loop_stack (
        .top(stack_top),
        .clk(clk),
        .pushd(stack_data),
        .push_en(stack_push),
        .pop_en(stack_pop)
    );


    initial
    begin
        pc = 0;
        dp = 0;
        lsc = 0;
    end


    always @(*)
    begin

        data_out = 32'bX;
        data_out_en = 0;
        data_read = 0;
        data_to_ram = 32'bX;
        ram_write = 0;
        stack_data = 32'bX;
        stack_push = 0;
        stack_pop = 0;
        next_dp = dp;
        next_pc = pc + 1'b1;
        next_lsc = lsc;


        if (lsc == 0)
        begin

            case (ci)
                4'h0:
                    begin

                        next_pc = pc;
                    end

                4'h8:
                    begin

                        next_dp = dp + 1'b1;
                    end

                4'h9:
                    begin

                        next_dp = dp - 1'b1;
                    end

                4'hA:
                    begin

                        data_to_ram = data_from_ram + 1'b1;
                        ram_write = 1;
                    end

                4'hB:
                    begin

                        data_to_ram = data_from_ram - 1'b1;
                        ram_write = 1;
                    end

                4'hC:
                    begin

                        if (data_from_ram == 0)
                        begin

                            next_lsc = 1;
                        end
                        else
                        begin

                            stack_data = next_pc;
                            stack_push = 1;
                        end
                    end

                4'hD:
                    begin

                        if (data_from_ram == 0)
                            stack_pop = 1;
                        else
                            next_pc = stack_top;
                    end

                4'hE:
                    begin

                        data_out = data_from_ram;
                        data_out_en = 1;
                    end

                4'hF:
                    begin

                        if (data_available)
                        begin

                            data_to_ram = data_in;
                            ram_write = 1;
                            data_read = 1;
                        end
                        else
                        begin

                            next_pc = pc;
                        end
                    end


            endcase
        end
        else
        begin

            case (ci)
                4'hC:
                    begin

                        next_lsc = lsc + 1'b1;
                    end

                4'hD:
                    begin

                        next_lsc = lsc - 1'b1;
                    end
            endcase
        end
    end


    always @(posedge clk)
    begin

        pc <= next_pc;
        dp <= next_dp;
        lsc <= next_lsc;
    end
endmodule