data/full_repos/permissive/121864698/DataMemory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/121864698/DataMemory.v:13: Bit extraction of array[30:0] requires 5 bit index, not 8 bits.\n                                                                    : ... In instance RAM\nmem[address] = data_in;\n   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/121864698/DataMemory.v:18: Bit extraction of array[30:0] requires 5 bit index, not 8 bits.\n                                                                    : ... In instance RAM\ndata = mem[address];\n          ^\n%Error: Exiting due to 2 warning(s)\n'
module RAM(address,clk,data_in,data_out,re,wr);
input [7:0]address;
input [7:0]data_in;
input clk,re,wr;
output [7:0]data_out;
reg[7:0] mem [0:30];
reg[7:0] data;
assign data_out = data;
initial
mem[16]=25;
always @(posedge clk)begin
if(wr)begin
mem[address] = data_in;
end
end
always @(address or re)begin
if(re)begin
data = mem[address];
end
end

endmodule
module RAM(address,clk,data_in,data_out,re,wr);

input [7:0]address;
input [7:0]data_in;
input clk,re,wr;
output [7:0]data_out;
reg[7:0] mem [0:30];
reg[7:0] data;
assign data_out = data;
initial
mem[16]=25;
always @(posedge clk)begin
if(wr)begin
mem[address] = data_in;
end
end
always @(address or re)begin
if(re)begin
data = mem[address];
end
end

endmodule