data/full_repos/permissive/114714167/Source-Code/PreviousTeamPorted/reciever_reader.v
data/verilator_xmls/539559c7-3d27-4fd1-acee-122040e727b1.xml
module reciever_reader(
		       sys_clk,
		       pwm_in,
		       pwm_out
                       );
   


   parameter COUNTER_SIZE = 10;

   parameter DIVIDER_SIZE  = 133;

   parameter MAX_COUNT  = 400;
   parameter LONG_SEQUENCE = 10'b0000000000;
   parameter SHORT_SEQUENCE = 10'b0000000000;

   input wire sys_clk, pwm_in;
   

   output wire [COUNTER_SIZE-1 : 0] pwm_out; 
   

   reg [COUNTER_SIZE-1 : 0] 	    counter_int;
   reg [COUNTER_SIZE : 0] 		    counter_div;
   reg [COUNTER_SIZE-1 : 0] 	    out_holder;
   reg 				    pwm_h;
   

   assign pwm_out = out_holder;
   

   always @ (posedge sys_clk)
     begin
	if(~pwm_in)
	  begin
	     if(counter_int > MAX_COUNT)
	       begin
		  out_holder[COUNTER_SIZE-1 : 0] <= (counter_int[COUNTER_SIZE-1 :0] - MAX_COUNT);	  
		  counter_int <= SHORT_SEQUENCE;	
	       end
	     else
	       begin
		  counter_int <= SHORT_SEQUENCE;	
	       end
	  end
	
	else
	  begin
	     out_holder <= out_holder;
	  end	
	
	if (pwm_in && (counter_div == 0))
	  begin
	     counter_int <= counter_int + 1;
	     counter_div <= DIVIDER_SIZE;
	  end
	else
	  begin
	     counter_div <= counter_div - 1;
	  end
     end
endmodule
module reciever_reader(
		       sys_clk,
		       pwm_in,
		       pwm_out
                       );

   


   parameter COUNTER_SIZE = 10;

   parameter DIVIDER_SIZE  = 133;

   parameter MAX_COUNT  = 400;
   parameter LONG_SEQUENCE = 10'b0000000000;
   parameter SHORT_SEQUENCE = 10'b0000000000;

   input wire sys_clk, pwm_in;
   

   output wire [COUNTER_SIZE-1 : 0] pwm_out; 
   

   reg [COUNTER_SIZE-1 : 0] 	    counter_int;
   reg [COUNTER_SIZE : 0] 		    counter_div;
   reg [COUNTER_SIZE-1 : 0] 	    out_holder;
   reg 				    pwm_h;
   

   assign pwm_out = out_holder;
   

   always @ (posedge sys_clk)
     begin
	if(~pwm_in)
	  begin
	     if(counter_int > MAX_COUNT)
	       begin
		  out_holder[COUNTER_SIZE-1 : 0] <= (counter_int[COUNTER_SIZE-1 :0] - MAX_COUNT);	  
		  counter_int <= SHORT_SEQUENCE;	
	       end
	     else
	       begin
		  counter_int <= SHORT_SEQUENCE;	
	       end
	  end
	
	else
	  begin
	     out_holder <= out_holder;
	  end	
	
	if (pwm_in && (counter_div == 0))
	  begin
	     counter_int <= counter_int + 1;
	     counter_div <= DIVIDER_SIZE;
	  end
	else
	  begin
	     counter_div <= counter_div - 1;
	  end
     end
endmodule