data/full_repos/permissive/174783592/FloatMul/Mul/CarryL1.v
None: at end of input
1: b'%Error: data/full_repos/permissive/174783592/FloatMul/Mul/CarryL1.v:2: Cannot find include file: Mul/FullAdder.v\n`include"Mul/FullAdder.v" \n        ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174783592/FloatMul/Mul,data/full_repos/permissive/174783592/Mul/FullAdder.v\n             data/full_repos/permissive/174783592/FloatMul/Mul,data/full_repos/permissive/174783592/Mul/FullAdder.v.v\n             data/full_repos/permissive/174783592/FloatMul/Mul,data/full_repos/permissive/174783592/Mul/FullAdder.v.sv\n             Mul/FullAdder.v\n             Mul/FullAdder.v.v\n             Mul/FullAdder.v.sv\n             obj_dir/Mul/FullAdder.v\n             obj_dir/Mul/FullAdder.v.v\n             obj_dir/Mul/FullAdder.v.sv\n%Error: data/full_repos/permissive/174783592/FloatMul/Mul/CarryL1.v:3: Cannot find include file: Mul/HalfAdder.v\n`include"Mul/HalfAdder.v" \n        ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module CarryL1(m0, m1, m2, u,v);

	input  [10:0] m0 ;
	input  [11:1] m1 ;
	input  [12:2] m2;
	output [12:0] u; 
	output [12:2] v;
    

    assign u[0] = m0[0];
    HalfAdder h1(m0[1],m1[1],u[1],v[2]);

    generate
        genvar i;
        for (i=2; i<=10; i = i + 1) begin
            FullAdder fa0(m0[i],m1[i],m2[i],u[i],v[i+1]);
            
        end
    endgenerate
    
    HalfAdder h2(m1[11],m2[11],u[11],v[12]);
	assign u[12] = m2[12];

endmodule
module CarryL1(m0, m1, m2, u,v);


	input  [10:0] m0 ;
	input  [11:1] m1 ;
	input  [12:2] m2;
	output [12:0] u; 
	output [12:2] v;
    

    assign u[0] = m0[0];
    HalfAdder h1(m0[1],m1[1],u[1],v[2]);

    generate
        genvar i;
        for (i=2; i<=10; i = i + 1) begin
            FullAdder fa0(m0[i],m1[i],m2[i],u[i],v[i+1]);
            
        end
    endgenerate
    
    HalfAdder h2(m1[11],m2[11],u[11],v[12]);
	assign u[12] = m2[12];

endmodule