data/full_repos/permissive/127601528/rtl/mini_sp_ram.v
 line:46: before: "b"
1: b'%Error: data/full_repos/permissive/127601528/rtl/mini_sp_ram.v:24: Extra underscore in meta-comment; use /*synopsys {...}*/ not /*synopsys_{...}*/\n// synopsys_translate_off \n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127601528/rtl/mini_sp_ram.v:31: Extra underscore in meta-comment; use /*synopsys {...}*/ not /*synopsys_{...}*/\n// synopsys_translate_on \n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module mini_sp_ram #(
    parameter ADDR_BITS=8
)(    
    input             clk,
    input      [ 7:0] addr,
    input      [ 7:0] din,
    input             ce,
    input             we,
    output reg [ 7:0] dout
);

localparam MEM_DEPTH= 1<<ADDR_BITS;

reg [7:0] mem[MEM_DEPTH-1:0];


integer i;
initial begin
    for(i=0; i<MEM_DEPTH;i=i+1) begin
        mem[i] = 8'h00;
    end
end


always @(posedge clk) begin
    if(ce & we) begin
        mem[addr] = din;
    end
end

always @(posedge clk) begin
    if(ce && (!we)) begin
        dout <= mem[addr];
    end
end

endmodule
module mini_sp_ram #(
    parameter ADDR_BITS=8
)(    
    input             clk,
    input      [ 7:0] addr,
    input      [ 7:0] din,
    input             ce,
    input             we,
    output reg [ 7:0] dout
);


localparam MEM_DEPTH= 1<<ADDR_BITS;

reg [7:0] mem[MEM_DEPTH-1:0];


integer i;
initial begin
    for(i=0; i<MEM_DEPTH;i=i+1) begin
        mem[i] = 8'h00;
    end
end


always @(posedge clk) begin
    if(ce & we) begin
        mem[addr] = din;
    end
end

always @(posedge clk) begin
    if(ce && (!we)) begin
        dout <= mem[addr];
    end
end

endmodule