data/full_repos/permissive/188595972/src/clocks.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/188595972/src/clocks.v:32: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'ClockModule\'\nmodule ClockModule(clk,rst_n,clk_m); \n       ^~~~~~~~~~~\n                                                                       : ... Top module \'KeyboardClockModule\'\nmodule KeyboardClockModule(clk_modified,clk,rst_n);\n       ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module KeyboardClockModule(clk_modified,clk,rst_n);
    input clk;
    input rst_n;
    output reg clk_modified;
    reg [16:0]Q;
    always@(negedge clk or negedge rst_n)
      begin
        if(!rst_n){clk_modified,Q}<=18'b0;
        else {clk_modified,Q}<={clk_modified,Q}+18'b1;
      end
    endmodule
module KeyboardClockModule(clk_modified,clk,rst_n);

    input clk;
    input rst_n;
    output reg clk_modified;
    reg [16:0]Q;
    always@(negedge clk or negedge rst_n)
      begin
        if(!rst_n){clk_modified,Q}<=18'b0;
        else {clk_modified,Q}<={clk_modified,Q}+18'b1;
      end
    endmodule