data/full_repos/permissive/16142629/rtl/v1_3_1/zet_shrot.v
1: b'%Error: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_shrot.v:82: Cannot find file containing module: \'zet_rxr8\'\n  zet_rxr8 rxr8 (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/16142629/rtl/v1_3_1,data/full_repos/permissive/16142629/zet_rxr8\n             data/full_repos/permissive/16142629/rtl/v1_3_1,data/full_repos/permissive/16142629/zet_rxr8.v\n             data/full_repos/permissive/16142629/rtl/v1_3_1,data/full_repos/permissive/16142629/zet_rxr8.sv\n             zet_rxr8\n             zet_rxr8.v\n             zet_rxr8.sv\n             obj_dir/zet_rxr8\n             obj_dir/zet_rxr8.v\n             obj_dir/zet_rxr8.sv\n%Error: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_shrot.v:91: Cannot find file containing module: \'zet_rxr16\'\n  zet_rxr16 rxr16 (\n  ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_shrot.v:101: Operator EQ expects 8 bits on the LHS, but LHS\'s SEL generates 5 bits.\n                                                                              : ... In instance zet_shrot\n  assign unchanged = word_op ? (y[4:0]==8\'b0)\n                                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_shrot.v:123: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x\' generates 16 bits.\n                                                                              : ... In instance zet_shrot\n  assign { cfo_sal16, sal16 } = x << y;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_shrot.v:124: Operator GT expects 8 bits on the RHS, but RHS\'s CONST \'5\'h10\' generates 5 bits.\n                                                                              : ... In instance zet_shrot\n  assign { sar16, cfo_sar16 } = (y > 5\'d16) ? 17\'h1ffff\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_shrot.v:129: Operator SHIFTL expects 9 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                              : ... In instance zet_shrot\n  assign { cfo_sal8, sal8 } = x[7:0] << y;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_shrot.v:130: Operator GT expects 8 bits on the RHS, but RHS\'s CONST \'5\'h8\' generates 5 bits.\n                                                                              : ... In instance zet_shrot\n  assign { sar8, cfo_sar8 } = (y > 5\'d8) ? 9\'h1ff\n                                 ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n'
module zet_shrot (
    input  [15:0] x,
    input  [ 7:0] y,
    output [15:0] out,
    input  [ 2:0] func,

    input         word_op,
    input         cfi,
    input         ofi,
    output        cfo,
    output        ofo
  );


  wire [4:0] ror16;
  wire [4:0] rol16;
  wire [4:0] rcr16;
  wire [4:0] rcl16;
  wire [4:0] rot16;

  wire [15:0] sal;
  wire [15:0] sar;
  wire [15:0] shr;
  wire [15:0] sal16;
  wire [15:0] sar16;
  wire [15:0] shr16;

  wire [7:0] sal8;
  wire [7:0] sar8;
  wire [7:0] shr8;

  wire [3:0] ror8;
  wire [3:0] rol8;
  wire [3:0] rcr8;
  wire [3:0] rcl8;
  wire [3:0] rot8;

  wire [ 7:0] outr8;
  wire [15:0] outr16;
  wire [15:0] rot;

  wire cor8;
  wire cor16;
  wire unchanged;

  wire ofo_sal;
  wire ofo_sar;
  wire ofo_shr;
  wire cfo_sal;
  wire cfo_sal8;
  wire cfo_sal16;
  wire cfo_sar;
  wire cfo_sar8;
  wire cfo_sar16;
  wire cfo_shr;
  wire cfo_shr8;
  wire cfo_shr16;

  wire ofor;
  wire cfor;


  zet_rxr8 rxr8 (
    .x  (x[7:0]),
    .ci (cfi),
    .y  (rot8),
    .e  (func[1]),
    .w  (outr8),
    .co (cor8)
  );

  zet_rxr16 rxr16 (
    .x  (x),
    .ci (cfi),
    .y  (rot16),
    .e  (func[1]),
    .w  (outr16),
    .co (cor16)
  );


  assign unchanged = word_op ? (y[4:0]==8'b0)
                             : (y[3:0]==4'b0);


  assign ror16 = { 1'b0, y[3:0] };
  assign rol16 = { 1'b0, -y[3:0] };
  assign ror8  = { 1'b0, y[2:0] };
  assign rol8  = { 1'b0, -y[2:0] };

  assign rcr16 = (y[4:0] <= 5'd16) ? y[4:0] : { 1'b0, y[3:0] - 4'b1 };
  assign rcl16 = (y[4:0] <= 5'd17) ? 5'd17 - y[4:0] : 5'd2 - y[4:0];
  assign rcr8  = y[3:0] <= 4'd8 ? y[3:0] : { 1'b0, y[2:0] - 3'b1 };
  assign rcl8  = y[3:0] <= 4'd9 ? 4'd9 - y[3:0] : 4'd2 - y[3:0];

  assign rot8 = func[1] ? (func[0] ? rcr8 : rcl8 )
                        : (func[0] ? ror8 : rol8 );
  assign rot16 = func[1] ? (func[0] ? rcr16 : rcl16 )
                         : (func[0] ? ror16 : rol16 );

  assign rot = word_op ? outr16 : { x[15:8], outr8 };


  assign { cfo_sal16, sal16 } = x << y;
  assign { sar16, cfo_sar16 } = (y > 5'd16) ? 17'h1ffff
    : (({x,1'b0} >> y) | (x[15] ? (17'h1ffff << (17 - y))
                                     : 17'h0));
  assign { shr16, cfo_shr16 } = ({x,1'b0} >> y);

  assign { cfo_sal8, sal8 } = x[7:0] << y;
  assign { sar8, cfo_sar8 } = (y > 5'd8) ? 9'h1ff
    : (({x[7:0],1'b0} >> y) | (x[7] ? (9'h1ff << (9 - y))
                                         : 9'h0));
  assign { shr8, cfo_shr8 } = ({x[7:0],1'b0} >> y);

  assign sal     = word_op ? sal16 : { 8'd0, sal8 };
  assign shr     = word_op ? shr16 : { 8'd0, shr8 };
  assign sar     = word_op ? sar16 : { {8{sar8[7]}}, sar8 };


  assign ofor = func[0] ?
                  (word_op ? out[15]^out[14] : out[7]^out[6])
              :
                  (word_op ? cfo^out[15] : cfo^out[7]);

  assign ofo_sal = word_op ? (out[15] != cfo) : (out[7] != cfo);
  assign ofo_sar = 1'b0;
  assign ofo_shr = word_op ? x[15] : x[7];

  assign ofo = unchanged ? ofi
             : (func[2] ? (func[1] ? ofo_sar : (func[0] ? ofo_shr : ofo_sal))
                        : ofor);


  assign cfor = func[1] ? (word_op ? cor16 : cor8)
                        : (func[0] ? (word_op ? out[15] : out[7])
                                   : out[0]);

  assign cfo_sal = word_op ? cfo_sal16 : cfo_sal8;
  assign cfo_shr = word_op ? cfo_shr16 : cfo_shr8;
  assign cfo_sar = word_op ? cfo_sar16 : cfo_sar8;

  assign cfo = unchanged ? cfi
    : (func[2] ? (func[1] ? cfo_sar
                          : (func[0] ? cfo_shr : cfo_sal))
                : cfor);


  assign out = func[2] ? (func[1] ? sar : (func[0] ? shr : sal)) : rot;
endmodule
module zet_shrot (
    input  [15:0] x,
    input  [ 7:0] y,
    output [15:0] out,
    input  [ 2:0] func,

    input         word_op,
    input         cfi,
    input         ofi,
    output        cfo,
    output        ofo
  );



  wire [4:0] ror16;
  wire [4:0] rol16;
  wire [4:0] rcr16;
  wire [4:0] rcl16;
  wire [4:0] rot16;

  wire [15:0] sal;
  wire [15:0] sar;
  wire [15:0] shr;
  wire [15:0] sal16;
  wire [15:0] sar16;
  wire [15:0] shr16;

  wire [7:0] sal8;
  wire [7:0] sar8;
  wire [7:0] shr8;

  wire [3:0] ror8;
  wire [3:0] rol8;
  wire [3:0] rcr8;
  wire [3:0] rcl8;
  wire [3:0] rot8;

  wire [ 7:0] outr8;
  wire [15:0] outr16;
  wire [15:0] rot;

  wire cor8;
  wire cor16;
  wire unchanged;

  wire ofo_sal;
  wire ofo_sar;
  wire ofo_shr;
  wire cfo_sal;
  wire cfo_sal8;
  wire cfo_sal16;
  wire cfo_sar;
  wire cfo_sar8;
  wire cfo_sar16;
  wire cfo_shr;
  wire cfo_shr8;
  wire cfo_shr16;

  wire ofor;
  wire cfor;


  zet_rxr8 rxr8 (
    .x  (x[7:0]),
    .ci (cfi),
    .y  (rot8),
    .e  (func[1]),
    .w  (outr8),
    .co (cor8)
  );

  zet_rxr16 rxr16 (
    .x  (x),
    .ci (cfi),
    .y  (rot16),
    .e  (func[1]),
    .w  (outr16),
    .co (cor16)
  );


  assign unchanged = word_op ? (y[4:0]==8'b0)
                             : (y[3:0]==4'b0);


  assign ror16 = { 1'b0, y[3:0] };
  assign rol16 = { 1'b0, -y[3:0] };
  assign ror8  = { 1'b0, y[2:0] };
  assign rol8  = { 1'b0, -y[2:0] };

  assign rcr16 = (y[4:0] <= 5'd16) ? y[4:0] : { 1'b0, y[3:0] - 4'b1 };
  assign rcl16 = (y[4:0] <= 5'd17) ? 5'd17 - y[4:0] : 5'd2 - y[4:0];
  assign rcr8  = y[3:0] <= 4'd8 ? y[3:0] : { 1'b0, y[2:0] - 3'b1 };
  assign rcl8  = y[3:0] <= 4'd9 ? 4'd9 - y[3:0] : 4'd2 - y[3:0];

  assign rot8 = func[1] ? (func[0] ? rcr8 : rcl8 )
                        : (func[0] ? ror8 : rol8 );
  assign rot16 = func[1] ? (func[0] ? rcr16 : rcl16 )
                         : (func[0] ? ror16 : rol16 );

  assign rot = word_op ? outr16 : { x[15:8], outr8 };


  assign { cfo_sal16, sal16 } = x << y;
  assign { sar16, cfo_sar16 } = (y > 5'd16) ? 17'h1ffff
    : (({x,1'b0} >> y) | (x[15] ? (17'h1ffff << (17 - y))
                                     : 17'h0));
  assign { shr16, cfo_shr16 } = ({x,1'b0} >> y);

  assign { cfo_sal8, sal8 } = x[7:0] << y;
  assign { sar8, cfo_sar8 } = (y > 5'd8) ? 9'h1ff
    : (({x[7:0],1'b0} >> y) | (x[7] ? (9'h1ff << (9 - y))
                                         : 9'h0));
  assign { shr8, cfo_shr8 } = ({x[7:0],1'b0} >> y);

  assign sal     = word_op ? sal16 : { 8'd0, sal8 };
  assign shr     = word_op ? shr16 : { 8'd0, shr8 };
  assign sar     = word_op ? sar16 : { {8{sar8[7]}}, sar8 };


  assign ofor = func[0] ?
                  (word_op ? out[15]^out[14] : out[7]^out[6])
              :
                  (word_op ? cfo^out[15] : cfo^out[7]);

  assign ofo_sal = word_op ? (out[15] != cfo) : (out[7] != cfo);
  assign ofo_sar = 1'b0;
  assign ofo_shr = word_op ? x[15] : x[7];

  assign ofo = unchanged ? ofi
             : (func[2] ? (func[1] ? ofo_sar : (func[0] ? ofo_shr : ofo_sal))
                        : ofor);


  assign cfor = func[1] ? (word_op ? cor16 : cor8)
                        : (func[0] ? (word_op ? out[15] : out[7])
                                   : out[0]);

  assign cfo_sal = word_op ? cfo_sal16 : cfo_sal8;
  assign cfo_shr = word_op ? cfo_shr16 : cfo_shr8;
  assign cfo_sar = word_op ? cfo_sar16 : cfo_sar8;

  assign cfo = unchanged ? cfi
    : (func[2] ? (func[1] ? cfo_sar
                          : (func[0] ? cfo_shr : cfo_sal))
                : cfor);


  assign out = func[2] ? (func[1] ? sar : (func[0] ? shr : sal)) : rot;
endmodule