data/full_repos/permissive/143278/ivltests/inout4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/inout4.v:11: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (DB !== 32\'hzzzzzzzz) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/inout4.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (DB !== 32\'h9zzzzz87) begin\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/inout4.v:35: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                      : ... In instance main.U.uu\n   wire foo = DB[31:28];\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/inout4.v:42: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                      : ... In instance main.V\n   wire foo = DB[7:0];\n            ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire [31:0] DB;
   reg	       E;

   X2 U (.DB(DB[31:8]), .E(E));
   Y1 V (.DB(DB[7:0]),  .E(E));

   initial begin
      E = 0;
      #1 if (DB !== 32'hzzzzzzzz) begin
	 $display("FAILED -- DB=%b", DB);
	 $finish;
      end

      E = 1;
      #1 if (DB !== 32'h9zzzzz87) begin
	 $display("FAILED -- DB=%b", DB);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   wire [31:0] DB;
   reg	       E;

   X2 U (.DB(DB[31:8]), .E(E));
   Y1 V (.DB(DB[7:0]),  .E(E));

   initial begin
      E = 0;
      #1 if (DB !== 32'hzzzzzzzz) begin
	 $display("FAILED -- DB=%b", DB);
	 $finish;
      end

      E = 1;
      #1 if (DB !== 32'h9zzzzz87) begin
	 $display("FAILED -- DB=%b", DB);
	 $finish;
      end

      $display("PASSED");
   end

endmodule