data/full_repos/permissive/158845296/decode_to_execute.v
1: b'%Warning-WIDTH: data/full_repos/permissive/158845296/decode_to_execute.v:46: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s CONST \'31\'h0\' generates 31 bits.\n                                                                           : ... In instance decode_to_execute\n        x_pc          <= (reset) ? 31\'b0 : (x_stall ? x_pc                            : d_pc);\n                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/158845296/decode_to_execute.v:48: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'x_dst_reg\' generates 5 bits.\n                                                                           : ... In instance decode_to_execute\n        x_dst_reg     <= (reset) ?  6\'b0 : (x_stall ? x_dst_reg                       : d_dst_reg);\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/158845296/decode_to_execute.v:48: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'d_dst_reg\' generates 5 bits.\n                                                                           : ... In instance decode_to_execute\n        x_dst_reg     <= (reset) ?  6\'b0 : (x_stall ? x_dst_reg                       : d_dst_reg);\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/158845296/decode_to_execute.v:48: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s COND generates 6 bits.\n                                                                           : ... In instance decode_to_execute\n        x_dst_reg     <= (reset) ?  6\'b0 : (x_stall ? x_dst_reg                       : d_dst_reg);\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/158845296/decode_to_execute.v:49: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'x_src_reg_1\' generates 5 bits.\n                                                                           : ... In instance decode_to_execute\n        x_src_reg_1   <= (reset) ?  6\'b0 : (x_stall ? x_src_reg_1                     : d_src_reg_1);\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/158845296/decode_to_execute.v:49: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'d_src_reg_1\' generates 5 bits.\n                                                                           : ... In instance decode_to_execute\n        x_src_reg_1   <= (reset) ?  6\'b0 : (x_stall ? x_src_reg_1                     : d_src_reg_1);\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/158845296/decode_to_execute.v:49: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s COND generates 6 bits.\n                                                                           : ... In instance decode_to_execute\n        x_src_reg_1   <= (reset) ?  6\'b0 : (x_stall ? x_src_reg_1                     : d_src_reg_1);\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/158845296/decode_to_execute.v:50: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'x_src_reg_2\' generates 5 bits.\n                                                                           : ... In instance decode_to_execute\n        x_src_reg_2   <= (reset) ?  6\'b0 : (x_stall ? x_src_reg_2                     : d_src_reg_2);\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/158845296/decode_to_execute.v:50: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'d_src_reg_2\' generates 5 bits.\n                                                                           : ... In instance decode_to_execute\n        x_src_reg_2   <= (reset) ?  6\'b0 : (x_stall ? x_src_reg_2                     : d_src_reg_2);\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/158845296/decode_to_execute.v:50: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s COND generates 6 bits.\n                                                                           : ... In instance decode_to_execute\n        x_src_reg_2   <= (reset) ?  6\'b0 : (x_stall ? x_src_reg_2                     : d_src_reg_2);\n                      ^~\n%Error: Exiting due to 10 warning(s)\n'
module decode_to_execute
(
    input clock,
    input reset,


    input [31:0] d_pc,
    input [6:0]  d_opcode,
    input [4:0]  d_dst_reg,
    input [4:0]  d_src_reg_1,
    input [4:0]  d_src_reg_2,
    input [31:0] d_mem_offset,
    input [31:0] d_brn_offset,
    input [19:0] d_jmp_offset,
    input [31:0] d_read_data_1,
    input [31:0] d_read_data_2,
    input        d_alu_imm_src,
    input        d_mem_read,
    input        d_mem_write,
    input        d_mem_byte,
    input        d_reg_write,
    input        d_mem_to_reg,
    input        d_stall,


    input             x_stall,
    output reg [31:0] x_pc,
    output reg [6:0]  x_opcode,
    output reg [4:0]  x_dst_reg,
    output reg [4:0]  x_src_reg_1,
    output reg [4:0]  x_src_reg_2,
    output reg [31:0] x_mem_offset,
    output reg [31:0] x_brn_offset,
    output reg [19:0] x_jmp_offset,
    output reg [31:0] x_read_data_1,
    output reg [31:0] x_read_data_2,
    output reg        x_alu_imm_src,
    output reg        x_mem_read,
    output reg        x_mem_write,
    output reg        x_mem_byte,
    output reg        x_reg_write,
    output reg        x_mem_to_reg
);

    always @(posedge clock) begin
        x_pc          <= (reset) ? 31'b0 : (x_stall ? x_pc                            : d_pc);
        x_opcode      <= (reset) ?  7'b0 : (x_stall ? x_opcode      : (d_stall ? 7'b0 : d_opcode));
        x_dst_reg     <= (reset) ?  6'b0 : (x_stall ? x_dst_reg                       : d_dst_reg);
        x_src_reg_1   <= (reset) ?  6'b0 : (x_stall ? x_src_reg_1                     : d_src_reg_1);
        x_src_reg_2   <= (reset) ?  6'b0 : (x_stall ? x_src_reg_2                     : d_src_reg_2);
        x_mem_offset  <= (reset) ? 32'b0 : (x_stall ? x_mem_offset                    : d_mem_offset);
        x_brn_offset  <= (reset) ? 32'b0 : (x_stall ? x_brn_offset                    : d_brn_offset);
        x_jmp_offset  <= (reset) ? 20'b0 : (x_stall ? x_jmp_offset                    : d_jmp_offset);
        x_read_data_1 <= (reset) ? 32'b0 : (x_stall ? x_read_data_1                   : d_read_data_1);
        x_read_data_2 <= (reset) ? 32'b0 : (x_stall ? x_read_data_2                   : d_read_data_2);
        x_alu_imm_src <= (reset) ?  1'b0 : (x_stall ? x_alu_imm_src                   : d_alu_imm_src);
        x_mem_read    <= (reset) ?  1'b0 : (x_stall ? x_mem_read    : (d_stall ? 1'b0 : d_mem_read));
        x_mem_write   <= (reset) ?  1'b0 : (x_stall ? x_mem_write   : (d_stall ? 1'b0 : d_mem_write));
        x_mem_byte    <= (reset) ?  1'b0 : (x_stall ? x_mem_byte                      : d_mem_byte);
        x_reg_write   <= (reset) ?  1'b0 : (x_stall ? x_reg_write   : (d_stall ? 1'b0 : d_reg_write));
        x_mem_to_reg  <= (reset) ?  1'b0 : (x_stall ? x_mem_to_reg                    : d_mem_to_reg);
    end

endmodule
module decode_to_execute
(
    input clock,
    input reset,


    input [31:0] d_pc,
    input [6:0]  d_opcode,
    input [4:0]  d_dst_reg,
    input [4:0]  d_src_reg_1,
    input [4:0]  d_src_reg_2,
    input [31:0] d_mem_offset,
    input [31:0] d_brn_offset,
    input [19:0] d_jmp_offset,
    input [31:0] d_read_data_1,
    input [31:0] d_read_data_2,
    input        d_alu_imm_src,
    input        d_mem_read,
    input        d_mem_write,
    input        d_mem_byte,
    input        d_reg_write,
    input        d_mem_to_reg,
    input        d_stall,


    input             x_stall,
    output reg [31:0] x_pc,
    output reg [6:0]  x_opcode,
    output reg [4:0]  x_dst_reg,
    output reg [4:0]  x_src_reg_1,
    output reg [4:0]  x_src_reg_2,
    output reg [31:0] x_mem_offset,
    output reg [31:0] x_brn_offset,
    output reg [19:0] x_jmp_offset,
    output reg [31:0] x_read_data_1,
    output reg [31:0] x_read_data_2,
    output reg        x_alu_imm_src,
    output reg        x_mem_read,
    output reg        x_mem_write,
    output reg        x_mem_byte,
    output reg        x_reg_write,
    output reg        x_mem_to_reg
);


    always @(posedge clock) begin
        x_pc          <= (reset) ? 31'b0 : (x_stall ? x_pc                            : d_pc);
        x_opcode      <= (reset) ?  7'b0 : (x_stall ? x_opcode      : (d_stall ? 7'b0 : d_opcode));
        x_dst_reg     <= (reset) ?  6'b0 : (x_stall ? x_dst_reg                       : d_dst_reg);
        x_src_reg_1   <= (reset) ?  6'b0 : (x_stall ? x_src_reg_1                     : d_src_reg_1);
        x_src_reg_2   <= (reset) ?  6'b0 : (x_stall ? x_src_reg_2                     : d_src_reg_2);
        x_mem_offset  <= (reset) ? 32'b0 : (x_stall ? x_mem_offset                    : d_mem_offset);
        x_brn_offset  <= (reset) ? 32'b0 : (x_stall ? x_brn_offset                    : d_brn_offset);
        x_jmp_offset  <= (reset) ? 20'b0 : (x_stall ? x_jmp_offset                    : d_jmp_offset);
        x_read_data_1 <= (reset) ? 32'b0 : (x_stall ? x_read_data_1                   : d_read_data_1);
        x_read_data_2 <= (reset) ? 32'b0 : (x_stall ? x_read_data_2                   : d_read_data_2);
        x_alu_imm_src <= (reset) ?  1'b0 : (x_stall ? x_alu_imm_src                   : d_alu_imm_src);
        x_mem_read    <= (reset) ?  1'b0 : (x_stall ? x_mem_read    : (d_stall ? 1'b0 : d_mem_read));
        x_mem_write   <= (reset) ?  1'b0 : (x_stall ? x_mem_write   : (d_stall ? 1'b0 : d_mem_write));
        x_mem_byte    <= (reset) ?  1'b0 : (x_stall ? x_mem_byte                      : d_mem_byte);
        x_reg_write   <= (reset) ?  1'b0 : (x_stall ? x_reg_write   : (d_stall ? 1'b0 : d_reg_write));
        x_mem_to_reg  <= (reset) ?  1'b0 : (x_stall ? x_mem_to_reg                    : d_mem_to_reg);
    end

endmodule