data/full_repos/permissive/134057391/2018_cpu/code/testbench/pc_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/pc_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n     #(1.1*PERIOD) reset = 1\'b0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2018_cpu/code/testbench/pc_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2) clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/134057391/2018_cpu/code/testbench/pc_tb.v:48: Cannot find file containing module: \'pc\'\n    pc uut (\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/134057391/2018_cpu/code/testbench,data/full_repos/permissive/134057391/pc\n             data/full_repos/permissive/134057391/2018_cpu/code/testbench,data/full_repos/permissive/134057391/pc.v\n             data/full_repos/permissive/134057391/2018_cpu/code/testbench,data/full_repos/permissive/134057391/pc.sv\n             pc\n             pc.v\n             pc.sv\n             obj_dir/pc\n             obj_dir/pc.v\n             obj_dir/pc.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pc_tb;

    parameter PERIOD = 10;
    parameter PC_WIDTH = 4;

    reg                 clk;
    reg                 reset;
    wire [PC_WIDTH-1:0] pc;

	initial begin
        clk = 1'b1;
	    reset = 1'b1;
	    #(1.1*PERIOD) reset = 1'b0;
	end
			
    always begin
        #(PERIOD/2) clk = ~clk;
    end
	
    pc uut (
        .clk(clk),
        .reset(reset),
        .pc(pc)
    );
        
endmodule
module pc_tb;


    parameter PERIOD = 10;
    parameter PC_WIDTH = 4;

    reg                 clk;
    reg                 reset;
    wire [PC_WIDTH-1:0] pc;

	initial begin
        clk = 1'b1;
	    reset = 1'b1;
	    #(1.1*PERIOD) reset = 1'b0;
	end
			
    always begin
        #(PERIOD/2) clk = ~clk;
    end
	
    pc uut (
        .clk(clk),
        .reset(reset),
        .pc(pc)
    );
        
endmodule