data/full_repos/permissive/205673649/BIP/Source/cpu.v
1: b"%Error: data/full_repos/permissive/205673649/BIP/Source/cpu.v:61: Cannot find file containing module: 'control'\n    control\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/BIP/Source,data/full_repos/permissive/205673649/control\n             data/full_repos/permissive/205673649/BIP/Source,data/full_repos/permissive/205673649/control.v\n             data/full_repos/permissive/205673649/BIP/Source,data/full_repos/permissive/205673649/control.sv\n             control\n             control.v\n             control.sv\n             obj_dir/control\n             obj_dir/control.v\n             obj_dir/control.sv\n%Error: data/full_repos/permissive/205673649/BIP/Source/cpu.v:81: Cannot find file containing module: 'datapath'\n    datapath\n    ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module cpu
#(
    parameter NB_DECODER_SEL_A = 2,
    parameter NB_OPCODE = 5,
    parameter NB_ADDR = 11,
    parameter NB_OPERANDO = 11,
    parameter RAM_WIDTH = 16
)
(
    i_clk,
    i_rst,
    i_opcode_pm,
    i_operando_pm,
    i_data,
    o_wr_en,
    o_data,
    o_addr_pm
);


input i_clk;
input i_rst;
input [NB_OPCODE-1:0] i_opcode_pm;
input [NB_OPERANDO-1:0] i_operando_pm;
input [RAM_WIDTH-1:0] i_data;
output o_wr_en;
output [RAM_WIDTH-1:0] o_data;
output [NB_ADDR-1:0] o_addr_pm;



wire [NB_DECODER_SEL_A-1:0] selA;
wire selB;
wire wrAcc;
wire [NB_OPCODE-1:0] op;
wire wrRam;
wire rdRam;

assign o_wr_en = (wrRam == 1'b1) ? 1'b1 : 1'b0;

    control
#(  
    .NB_OPCODE(NB_OPCODE),
    .NB_ADDR(NB_ADDR),
    .NB_DECODER_SEL_A(NB_DECODER_SEL_A)
)
    u_control
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_opcode(i_opcode_pm), 
    .o_addr(o_addr_pm),
    .o_selA(selA),
    .o_selB(selB),
    .o_wrAcc(wrAcc),
    .o_op(op),
    .o_wrRam(wrRam),
    .o_rdRam(rdRam)
);

    datapath
#(
    .NB_OPCODE(NB_OPCODE),
    .NB_DECODER_SEL_A(NB_DECODER_SEL_A),
    .NB_DATA(RAM_WIDTH),
    .NB_OPERANDO(NB_OPERANDO)
)
    u_datapath
(
   .i_clk(i_clk),
   .i_rst(i_rst),
   .i_selA(selA),
   .i_selB(selB),
   .i_wrAcc(wrAcc),
   .i_op(op),
   .i_operando(i_operando_pm),
   .i_data(i_data),
   .o_data(o_data)
);
endmodule
module cpu
#(
    parameter NB_DECODER_SEL_A = 2,
    parameter NB_OPCODE = 5,
    parameter NB_ADDR = 11,
    parameter NB_OPERANDO = 11,
    parameter RAM_WIDTH = 16
)
(
    i_clk,
    i_rst,
    i_opcode_pm,
    i_operando_pm,
    i_data,
    o_wr_en,
    o_data,
    o_addr_pm
);



input i_clk;
input i_rst;
input [NB_OPCODE-1:0] i_opcode_pm;
input [NB_OPERANDO-1:0] i_operando_pm;
input [RAM_WIDTH-1:0] i_data;
output o_wr_en;
output [RAM_WIDTH-1:0] o_data;
output [NB_ADDR-1:0] o_addr_pm;



wire [NB_DECODER_SEL_A-1:0] selA;
wire selB;
wire wrAcc;
wire [NB_OPCODE-1:0] op;
wire wrRam;
wire rdRam;

assign o_wr_en = (wrRam == 1'b1) ? 1'b1 : 1'b0;

    control
#(  
    .NB_OPCODE(NB_OPCODE),
    .NB_ADDR(NB_ADDR),
    .NB_DECODER_SEL_A(NB_DECODER_SEL_A)
)
    u_control
(
    .i_clk(i_clk),
    .i_rst(i_rst),
    .i_opcode(i_opcode_pm), 
    .o_addr(o_addr_pm),
    .o_selA(selA),
    .o_selB(selB),
    .o_wrAcc(wrAcc),
    .o_op(op),
    .o_wrRam(wrRam),
    .o_rdRam(rdRam)
);

    datapath
#(
    .NB_OPCODE(NB_OPCODE),
    .NB_DECODER_SEL_A(NB_DECODER_SEL_A),
    .NB_DATA(RAM_WIDTH),
    .NB_OPERANDO(NB_OPERANDO)
)
    u_datapath
(
   .i_clk(i_clk),
   .i_rst(i_rst),
   .i_selA(selA),
   .i_selB(selB),
   .i_wrAcc(wrAcc),
   .i_op(op),
   .i_operando(i_operando_pm),
   .i_data(i_data),
   .o_data(o_data)
);
endmodule