data/full_repos/permissive/141582589/src/common_rtl/clock_out.v
 line:36: before: "."
1: b"%Error: data/full_repos/permissive/141582589/src/common_rtl/clock_out.v:23: Cannot find file containing module: 'altddio_out'\n altddio_out ALTDDIO_OUT_component (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141582589/src/common_rtl,data/full_repos/permissive/141582589/altddio_out\n             data/full_repos/permissive/141582589/src/common_rtl,data/full_repos/permissive/141582589/altddio_out.v\n             data/full_repos/permissive/141582589/src/common_rtl,data/full_repos/permissive/141582589/altddio_out.sv\n             altddio_out\n             altddio_out.v\n             altddio_out.sv\n             obj_dir/altddio_out\n             obj_dir/altddio_out.v\n             obj_dir/altddio_out.sv\n%Error: Exiting due to 1 error(s)\n"
module clock_out
(
	input clk_in,
	output clk_out
);
`ifdef Xilinx
	ODDR2 #(
		.DDR_ALIGNMENT("NONE"),
		.INIT(1'b0),
		.SRTYPE("ASYNC")
		) U_ODDR2
	(
		  .Q(clk_out),
		  .C0(clk_in),
		  .C1(~clk_in),
		  .CE(1'b1),
		  .D0(1'b1),
		  .D1(1'b0),
		  .R(1'b0),
		  .S(1'b0)
	);
`else
	altddio_out	ALTDDIO_OUT_component (
				.datain_h (1'b1),
				.datain_l (1'b0),
				.outclock (clk_in),
				.dataout (clk_out),
				.aclr (1'b0),
				.aset (1'b0),
				.oe (1'b1),
				.oe_out (),
				.outclocken (1'b1),
				.sclr (1'b0),
				.sset (1'b0));
	defparam
		ALTDDIO_OUT_component.extend_oe_disable = "OFF",
		ALTDDIO_OUT_component.intended_device_family = "Cyclone III",
		ALTDDIO_OUT_component.invert_output = "OFF",
		ALTDDIO_OUT_component.lpm_hint = "UNUSED",
		ALTDDIO_OUT_component.lpm_type = "altddio_out",
		ALTDDIO_OUT_component.oe_reg = "UNREGISTERED",
		ALTDDIO_OUT_component.power_up_high = "OFF",
		ALTDDIO_OUT_component.width = 1;
`endif
endmodule
module clock_out
(
	input clk_in,
	output clk_out
);

`ifdef Xilinx
	ODDR2 #(
		.DDR_ALIGNMENT("NONE"),
		.INIT(1'b0),
		.SRTYPE("ASYNC")
		) U_ODDR2
	(
		  .Q(clk_out),
		  .C0(clk_in),
		  .C1(~clk_in),
		  .CE(1'b1),
		  .D0(1'b1),
		  .D1(1'b0),
		  .R(1'b0),
		  .S(1'b0)
	);
`else
	altddio_out	ALTDDIO_OUT_component (
				.datain_h (1'b1),
				.datain_l (1'b0),
				.outclock (clk_in),
				.dataout (clk_out),
				.aclr (1'b0),
				.aset (1'b0),
				.oe (1'b1),
				.oe_out (),
				.outclocken (1'b1),
				.sclr (1'b0),
				.sset (1'b0));
	defparam
		ALTDDIO_OUT_component.extend_oe_disable = "OFF",
		ALTDDIO_OUT_component.intended_device_family = "Cyclone III",
		ALTDDIO_OUT_component.invert_output = "OFF",
		ALTDDIO_OUT_component.lpm_hint = "UNUSED",
		ALTDDIO_OUT_component.lpm_type = "altddio_out",
		ALTDDIO_OUT_component.oe_reg = "UNREGISTERED",
		ALTDDIO_OUT_component.power_up_high = "OFF",
		ALTDDIO_OUT_component.width = 1;
`endif
endmodule