data/full_repos/permissive/147086086/Lab6/hw/barrel_shifter_rtl/barrel_shifter_right.v
1: b'%Warning-WIDTH: data/full_repos/permissive/147086086/Lab6/hw/barrel_shifter_rtl/barrel_shifter_right.v:14: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 11 bits.\n                                                                                                         : ... In instance barrel_shifter_right\n    shift_result = $signed({ (i_st & i_data[DATA_WIDTH-1]) , i_data}) >>> i_sa;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module barrel_shifter_right (i_data, i_sa, i_st, o_data);

parameter DATA_WIDTH = 10;
parameter SA_WIDTH = $clog2(DATA_WIDTH);

input                     i_st;
input   [DATA_WIDTH-1:0]  i_data;
input   [SA_WIDTH-1:0]    i_sa;
output  [DATA_WIDTH-1:0]  o_data;

reg     [DATA_WIDTH-1:0]  shift_result;

always @* begin
    shift_result = $signed({ (i_st & i_data[DATA_WIDTH-1]) , i_data}) >>> i_sa;
end

assign o_data = shift_result;

endmodule
module barrel_shifter_right (i_data, i_sa, i_st, o_data);


parameter DATA_WIDTH = 10;
parameter SA_WIDTH = $clog2(DATA_WIDTH);

input                     i_st;
input   [DATA_WIDTH-1:0]  i_data;
input   [SA_WIDTH-1:0]    i_sa;
output  [DATA_WIDTH-1:0]  o_data;

reg     [DATA_WIDTH-1:0]  shift_result;

always @* begin
    shift_result = $signed({ (i_st & i_data[DATA_WIDTH-1]) , i_data}) >>> i_sa;
end

assign o_data = shift_result;

endmodule