data/full_repos/permissive/143278/ivltests/br993b.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br993b.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br993b.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br993b.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br993b.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br993b.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br993b.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br993b.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br993b.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br993b.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br993b.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Error: Exiting due to 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module br993a();

reg       clk;
reg       a;
reg       b;
reg [1:0] q;

(* ivl_synthesis_on *)
always @(posedge clk) begin
  if (a) q <= 1;
  if (b) q <= 2;
end
(* ivl_synthesis_off *)

reg failed;
initial begin
  clk = 0;

  a = 1;
  b = 1;
  #1 clk = 1;
  #1 clk = 0;
  $display("%d", q);
  if (q !== 2'd2) failed = 1;

  a = 0;
  b = 0;
  #1 clk = 1;
  #1 clk = 0;
  $display("%d", q);
  if (q !== 2'd2) failed = 1;

  a = 1;
  b = 0;
  #1 clk = 1;
  #1 clk = 0;
  $display("%d", q);
  if (q !== 2'd1) failed = 1;

  a = 0;
  b = 0;
  #1 clk = 1;
  #1 clk = 0;
  $display("%d", q);
  if (q !== 2'd1) failed = 1;

  a = 0;
  b = 1;
  #1 clk = 1;
  #1 clk = 0;
  $display("%d", q);
  if (q !== 2'd2) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module br993a();


reg       clk;
reg       a;
reg       b;
reg [1:0] q;

(* ivl_synthesis_on *)
always @(posedge clk) begin
  if (a) q <= 1;
  if (b) q <= 2;
end
(* ivl_synthesis_off *)

reg failed;
initial begin
  clk = 0;

  a = 1;
  b = 1;
  #1 clk = 1;
  #1 clk = 0;
  $display("%d", q);
  if (q !== 2'd2) failed = 1;

  a = 0;
  b = 0;
  #1 clk = 1;
  #1 clk = 0;
  $display("%d", q);
  if (q !== 2'd2) failed = 1;

  a = 1;
  b = 0;
  #1 clk = 1;
  #1 clk = 0;
  $display("%d", q);
  if (q !== 2'd1) failed = 1;

  a = 0;
  b = 0;
  #1 clk = 1;
  #1 clk = 0;
  $display("%d", q);
  if (q !== 2'd1) failed = 1;

  a = 0;
  b = 1;
  #1 clk = 1;
  #1 clk = 0;
  $display("%d", q);
  if (q !== 2'd2) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule