data/full_repos/permissive/19905110/minsoc/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/minsoc/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v:58: Cannot find include file: minsoc_defines.v\n`include "minsoc_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/utils/contributions/initialized_onchip_ram,data/full_repos/permissive/19905110/minsoc_defines.v\n             data/full_repos/permissive/19905110/minsoc/utils/contributions/initialized_onchip_ram,data/full_repos/permissive/19905110/minsoc_defines.v.v\n             data/full_repos/permissive/19905110/minsoc/utils/contributions/initialized_onchip_ram,data/full_repos/permissive/19905110/minsoc_defines.v.sv\n             minsoc_defines.v\n             minsoc_defines.v.v\n             minsoc_defines.v.sv\n             obj_dir/minsoc_defines.v\n             obj_dir/minsoc_defines.v.v\n             obj_dir/minsoc_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module mux21(sel,in1,in2,out);

parameter dw = 32;

input sel;
input [dw-1:0] in1, in2;
output reg [dw-1:0] out;

always @ (sel or in1 or in2)
begin
	case (sel)
		1'b0: out = in1;
		1'b1: out = in2;
	endcase
end

endmodule
module mux21(sel,in1,in2,out);


parameter dw = 32;

input sel;
input [dw-1:0] in1, in2;
output reg [dw-1:0] out;

always @ (sel or in1 or in2)
begin
	case (sel)
		1'b0: out = in1;
		1'b1: out = in2;
	endcase
end

endmodule