data/full_repos/permissive/167489907/Data Path/With RAM/ram_datapath_tb.v
1: b'%Error: Cannot find file containing module: Path/With\n        ... Looked in:\n             data/full_repos/permissive/167489907/Data/Path/With\n             data/full_repos/permissive/167489907/Data/Path/With.v\n             data/full_repos/permissive/167489907/Data/Path/With.sv\n             Path/With\n             Path/With.v\n             Path/With.sv\n             obj_dir/Path/With\n             obj_dir/Path/With.v\n             obj_dir/Path/With.sv\n%Error: Cannot find file containing module: RAM,data/full_repos/permissive/167489907\n%Error: Cannot find file containing module: data/full_repos/permissive/167489907/Data\n%Error: Cannot find file containing module: RAM/ram_datapath_tb.v\n%Error: Exiting due to 4 error(s)\n'
module ram_datapath_tb;

reg W, clk, rst, EN_ALU, EN_B, EN_ADDR, K_SEL, PC_SEL, C0, WE, OE;
reg [4:0] SA, SB, DA, FS;
reg [63:0] K, CU;
wire [3:0] Status;
wire [63:0] r0, r1, r2, r3, r4, r5, r6, r7, PC_in;
wire [63:0] mem0, mem1, D_debug;

assign mem0 = dut.ram0.mem[12'h00F];
assign mem1 = dut.ram3.mem[12'h1F0];
assign D_debug = dut.D;

ram_datapath dut(.W(W), .clk(clk), .rst(rst), .EN_ALU(EN_ALU), .EN_B(EN_B), .EN_ADDR(EN_ADDR), 
.K_SEL(K_SEL), .PC_SEL(PC_SEL), .C0(C0), .WE(WE), .OE(OE), .SA(SA), .SB(SB), .DA(DA), .FS(FS), .K(K), .CU(CU), 
.Status(Status), .r0(r0), .r1(r1), .r2(r2), .r3(r3), .r4(r4), .r5(r5), .r6(r6), .r7(r7), .PC_in(PC_in));


always begin
	#5 clk = ~clk;
end

initial begin
	clk <= 1'b0;
	rst <= 1'b1;
	#10;
	rst <= 1'b0;
	


	K <= 64'h0000_FFFF_0000_000F;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b11111;
	SB <= 5'bx;
	DA <= 5'b00000;
	EN_ALU <= 1'b1;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b0;
	W <= 1'b1;
	OE <= 1'b0;
	WE <= 1'b0;
	


	#10;
	K <= 64'hFFFF_0000_0000_31F0;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b11111;
	SB <= 5'bx;
	DA <= 5'b00001;
	EN_ALU <= 1'b1;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b0;
	W <= 1'b1;
	OE <= 1'b0;
	WE <= 1'b0;
	


	#10;
	K <= 64'h0123_4567_89AB_CDEF;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b11111;
	SB <= 5'bx;
	DA <= 5'b00010;
	EN_ALU <= 1'b1;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b0;
	W <= 1'b1;
	OE <= 1'b0;
	WE <= 1'b0;
	


	#10;
	K <= 64'hCCCC_CCCC_CCCC_CCCC;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b11111;
	SB <= 5'bx;
	DA <= 5'b00011;
	EN_ALU <= 1'b1;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b0;
	W <= 1'b1;
	OE <= 1'b0;
	WE <= 1'b0;

	


	#10;
	K <= 64'hFFFF_FFFF_FFFF_FFFF;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b1;
	FS <= 5'b01010;
	SA <= 5'b00001;
	SB <= 5'bx;
	DA <= 5'b00100;
	EN_ALU <= 1'b1;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b0;
	W <= 1'b1;
	OE <= 1'b0;
	WE <= 1'b0;
	


	#10;
	K <= 64'hx;
	CU <= 64'hx;
	K_SEL <= 1'b0;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'bx;
	SA <= 5'b11111;
	SB <= 5'b00001;
	DA <= 5'b00101;
	EN_ALU <= 1'b0;
	EN_B <= 1'b1;
	EN_ADDR <= 1'b0;
	W <= 1'b1;
	OE <= 1'b0;
	WE <= 1'b0;
	


	#20;
	K <= 64'h0000_0000_0000_0000;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b00000;
	SB <= 5'b00010;
	DA <= 5'bx;
	EN_ALU <= 1'b0;
	EN_B <= 1'b1;
	EN_ADDR <= 1'b1;
	W <= 1'b0;
	OE <= 1'b0;
	WE <= 1'b1;
	


	#20;
	K <= 64'h0000_0000_0000_0000;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b00001;
	SB <= 5'b00011;
	DA <= 5'bx;
	EN_ALU <= 1'b0;
	EN_B <= 1'b1;
	EN_ADDR <= 1'b1;
	W <= 1'b0;
	OE <= 1'b0;
	WE <= 1'b1;

	


	#15;
	K <= 64'h0000_0000_0000_0000;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b00000;
	SB <= 5'b00000;
	DA <= 5'b00110;
	EN_ALU <= 1'b0;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b1;
	W <= 1'b1;
	WE <= 1'b0;
	OE <= 1'b1;
	
	


	#20;
	K <= 64'h0000_0000_0000_0000;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b00001;
	SB <= 5'b00001;
	DA <= 5'b00111;
	EN_ALU <= 1'b0;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b1;
	WE <= 1'b0;
	OE <= 1'b1;
	W <= 1'b1;
	
	


	#30;
	K <= 64'hx;
	CU <= 64'hx;
	K_SEL <= 1'b0;
	PC_SEL <= 1'b1;
	C0 <= 1'b0;
	FS <= 5'bx;
	SA <= 5'b00110;
	SB <= 5'bx;
	DA <= 5'bx;
	EN_ALU <= 1'b0;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b0;
	OE <= 1'b0;
	WE <= 1'b0;
	W <= 1'b1;
	
	#30;
	$stop;
	
end

endmodule
module ram_datapath_tb;


reg W, clk, rst, EN_ALU, EN_B, EN_ADDR, K_SEL, PC_SEL, C0, WE, OE;
reg [4:0] SA, SB, DA, FS;
reg [63:0] K, CU;
wire [3:0] Status;
wire [63:0] r0, r1, r2, r3, r4, r5, r6, r7, PC_in;
wire [63:0] mem0, mem1, D_debug;

assign mem0 = dut.ram0.mem[12'h00F];
assign mem1 = dut.ram3.mem[12'h1F0];
assign D_debug = dut.D;

ram_datapath dut(.W(W), .clk(clk), .rst(rst), .EN_ALU(EN_ALU), .EN_B(EN_B), .EN_ADDR(EN_ADDR), 
.K_SEL(K_SEL), .PC_SEL(PC_SEL), .C0(C0), .WE(WE), .OE(OE), .SA(SA), .SB(SB), .DA(DA), .FS(FS), .K(K), .CU(CU), 
.Status(Status), .r0(r0), .r1(r1), .r2(r2), .r3(r3), .r4(r4), .r5(r5), .r6(r6), .r7(r7), .PC_in(PC_in));


always begin
	#5 clk = ~clk;
end

initial begin
	clk <= 1'b0;
	rst <= 1'b1;
	#10;
	rst <= 1'b0;
	


	K <= 64'h0000_FFFF_0000_000F;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b11111;
	SB <= 5'bx;
	DA <= 5'b00000;
	EN_ALU <= 1'b1;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b0;
	W <= 1'b1;
	OE <= 1'b0;
	WE <= 1'b0;
	


	#10;
	K <= 64'hFFFF_0000_0000_31F0;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b11111;
	SB <= 5'bx;
	DA <= 5'b00001;
	EN_ALU <= 1'b1;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b0;
	W <= 1'b1;
	OE <= 1'b0;
	WE <= 1'b0;
	


	#10;
	K <= 64'h0123_4567_89AB_CDEF;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b11111;
	SB <= 5'bx;
	DA <= 5'b00010;
	EN_ALU <= 1'b1;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b0;
	W <= 1'b1;
	OE <= 1'b0;
	WE <= 1'b0;
	


	#10;
	K <= 64'hCCCC_CCCC_CCCC_CCCC;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b11111;
	SB <= 5'bx;
	DA <= 5'b00011;
	EN_ALU <= 1'b1;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b0;
	W <= 1'b1;
	OE <= 1'b0;
	WE <= 1'b0;

	


	#10;
	K <= 64'hFFFF_FFFF_FFFF_FFFF;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b1;
	FS <= 5'b01010;
	SA <= 5'b00001;
	SB <= 5'bx;
	DA <= 5'b00100;
	EN_ALU <= 1'b1;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b0;
	W <= 1'b1;
	OE <= 1'b0;
	WE <= 1'b0;
	


	#10;
	K <= 64'hx;
	CU <= 64'hx;
	K_SEL <= 1'b0;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'bx;
	SA <= 5'b11111;
	SB <= 5'b00001;
	DA <= 5'b00101;
	EN_ALU <= 1'b0;
	EN_B <= 1'b1;
	EN_ADDR <= 1'b0;
	W <= 1'b1;
	OE <= 1'b0;
	WE <= 1'b0;
	


	#20;
	K <= 64'h0000_0000_0000_0000;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b00000;
	SB <= 5'b00010;
	DA <= 5'bx;
	EN_ALU <= 1'b0;
	EN_B <= 1'b1;
	EN_ADDR <= 1'b1;
	W <= 1'b0;
	OE <= 1'b0;
	WE <= 1'b1;
	


	#20;
	K <= 64'h0000_0000_0000_0000;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b00001;
	SB <= 5'b00011;
	DA <= 5'bx;
	EN_ALU <= 1'b0;
	EN_B <= 1'b1;
	EN_ADDR <= 1'b1;
	W <= 1'b0;
	OE <= 1'b0;
	WE <= 1'b1;

	


	#15;
	K <= 64'h0000_0000_0000_0000;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b00000;
	SB <= 5'b00000;
	DA <= 5'b00110;
	EN_ALU <= 1'b0;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b1;
	W <= 1'b1;
	WE <= 1'b0;
	OE <= 1'b1;
	
	


	#20;
	K <= 64'h0000_0000_0000_0000;
	CU <= 64'hx;
	K_SEL <= 1'b1;
	PC_SEL <= 1'b0;
	C0 <= 1'b0;
	FS <= 5'b01000;
	SA <= 5'b00001;
	SB <= 5'b00001;
	DA <= 5'b00111;
	EN_ALU <= 1'b0;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b1;
	WE <= 1'b0;
	OE <= 1'b1;
	W <= 1'b1;
	
	


	#30;
	K <= 64'hx;
	CU <= 64'hx;
	K_SEL <= 1'b0;
	PC_SEL <= 1'b1;
	C0 <= 1'b0;
	FS <= 5'bx;
	SA <= 5'b00110;
	SB <= 5'bx;
	DA <= 5'bx;
	EN_ALU <= 1'b0;
	EN_B <= 1'b0;
	EN_ADDR <= 1'b0;
	OE <= 1'b0;
	WE <= 1'b0;
	W <= 1'b1;
	
	#30;
	$stop;
	
end

endmodule