data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v
Syntax Error
1: b'%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:1: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench,data/full_repos/permissive/114714167/timescale.v\n             data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench,data/full_repos/permissive/114714167/timescale.v.v\n             data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench,data/full_repos/permissive/114714167/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:112: syntax error, unexpected \'@\'\n  @(posedge CLK_I);\n  ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:117: syntax error, unexpected \'@\'\n    @(posedge CLK_I);\n    ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:121: syntax error, unexpected \'@\'\n    @(posedge CLK_I);\n    ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:141: syntax error, unexpected \'@\'\n  @(posedge CLK_I);\n  ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:146: syntax error, unexpected \'@\'\n    @(posedge CLK_I);\n    ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:150: syntax error, unexpected \'@\'\n    @(posedge CLK_I);\n    ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:167: syntax error, unexpected \'@\'\n  @(posedge CLK_I);\n  ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:171: syntax error, unexpected \'@\'\n    @(posedge CLK_I);\n    ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:190: syntax error, unexpected \'@\'\n  @(posedge CLK_I);\n  ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:194: syntax error, unexpected \'@\'\n    @(posedge CLK_I);\n    ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:212: syntax error, unexpected \'@\'\n  @(posedge CLK_I);\n  ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:216: syntax error, unexpected \'@\'\n    @(posedge CLK_I);\n    ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:227: syntax error, unexpected \'@\'\n  @(posedge CLK_I);\n  ^\n%Error: data/full_repos/permissive/114714167/Source-Code/openCoresPID/openCores_pid_controller/trunk/bench/wb_master.v:231: syntax error, unexpected \'@\'\n    @(posedge CLK_I);\n    ^\n%Error: Exiting due to 15 error(s)\n'
function [1:0] data_width;
      input [31:0] adr;
      begin
	 casex (adr[31:29])
	   3'b000: data_width = mem_sizes[15:14];
	   3'b001: data_width = mem_sizes[13:12];
	   3'b010: data_width = mem_sizes[11:10];
	   3'b011: data_width = mem_sizes[9:8];
	   3'b100: data_width = mem_sizes[7:6];
	   3'b101: data_width = mem_sizes[5:4];
	   3'b110: data_width = mem_sizes[3:2];
	   3'b111: data_width = mem_sizes[1:0];
	   3'bxxx: data_width = 2'bxx;
	 endcase
      end
   endfunction
function [1:0] data_width;

      input [31:0] adr;
      begin
	 casex (adr[31:29])
	   3'b000: data_width = mem_sizes[15:14];
	   3'b001: data_width = mem_sizes[13:12];
	   3'b010: data_width = mem_sizes[11:10];
	   3'b011: data_width = mem_sizes[9:8];
	   3'b100: data_width = mem_sizes[7:6];
	   3'b101: data_width = mem_sizes[5:4];
	   3'b110: data_width = mem_sizes[3:2];
	   3'b111: data_width = mem_sizes[1:0];
	   3'bxxx: data_width = 2'bxx;
	 endcase
      end
   endfunction