data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp
 line:82: before: ","
1: b"%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:81: Define or directive not defined: '`mname'\nmodule `mname` (\n       ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:81: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule `mname` (\n             ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:91: Unsupported or unknown PLI call: $bus\nout_`$bus`_S`$i`_T`$j`,\n     ^~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:91: Define or directive not defined: '`_S'\nout_`$bus`_S`$i`_T`$j`,\n         ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:91: Unsupported or unknown PLI call: $i\nout_`$bus`_S`$i`_T`$j`,\n             ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:91: Define or directive not defined: '`_T'\nout_`$bus`_S`$i`_T`$j`,\n               ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:91: Unsupported or unknown PLI call: $j\nout_`$bus`_S`$i`_T`$j`,\n                   ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:92: Unsupported or unknown PLI call: $bus\nin_`$bus`_S`$i`_T`$j`,\n    ^~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:92: Define or directive not defined: '`_S'\nin_`$bus`_S`$i`_T`$j`,\n        ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:92: Unsupported or unknown PLI call: $i\nin_`$bus`_S`$i`_T`$j`,\n            ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:92: Define or directive not defined: '`_T'\nin_`$bus`_S`$i`_T`$j`,\n              ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:92: Unsupported or unknown PLI call: $j\nin_`$bus`_S`$i`_T`$j`,\n                  ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:115: Unsupported or unknown PLI call: $bus_width\n  output [`$bus_width-1`:0] out_`$bus`_S`$i`_T`$j`;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:115: Unsupported or unknown PLI call: $bus\n  output [`$bus_width-1`:0] out_`$bus`_S`$i`_T`$j`;\n                                 ^~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:115: Define or directive not defined: '`_S'\n  output [`$bus_width-1`:0] out_`$bus`_S`$i`_T`$j`;\n                                     ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:115: Unsupported or unknown PLI call: $i\n  output [`$bus_width-1`:0] out_`$bus`_S`$i`_T`$j`;\n                                         ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:115: Define or directive not defined: '`_T'\n  output [`$bus_width-1`:0] out_`$bus`_S`$i`_T`$j`;\n                                           ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:115: Unsupported or unknown PLI call: $j\n  output [`$bus_width-1`:0] out_`$bus`_S`$i`_T`$j`;\n                                               ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:116: Unsupported or unknown PLI call: $bus_width\n  input [`$bus_width-1`:0] in_`$bus`_S`$i`_T`$j`;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:116: Unsupported or unknown PLI call: $bus\n  input [`$bus_width-1`:0] in_`$bus`_S`$i`_T`$j`;\n                               ^~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:116: Define or directive not defined: '`_S'\n  input [`$bus_width-1`:0] in_`$bus`_S`$i`_T`$j`;\n                                   ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:116: Unsupported or unknown PLI call: $i\n  input [`$bus_width-1`:0] in_`$bus`_S`$i`_T`$j`;\n                                       ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:116: Define or directive not defined: '`_T'\n  input [`$bus_width-1`:0] in_`$bus`_S`$i`_T`$j`;\n                                         ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:116: Unsupported or unknown PLI call: $j\n  input [`$bus_width-1`:0] in_`$bus`_S`$i`_T`$j`;\n                                             ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:124: syntax error, unexpected input\n  input [15:0] tile_id;\n  ^~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: syntax error, unexpected $undefined, expecting ',' or ';'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                       ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                              ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                              ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                              ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                         ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                  ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                          ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                       ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                  ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                                      ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                                                        ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                                                                        ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                                                                                     ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                                                                                                  ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                                                                                                                ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                                                                                                                              ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                                                                                                                                             ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                                                                                                                                                            ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                                                                                                                                                                         ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                                                                                                                                                                                     ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:129: Define or directive not defined: '`_'\n  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;\n                                                                                                                                                                                                                                                                                                                                                                    ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:137: syntax error, unexpected always\n   always @(*) begin\n   ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:141: Number is missing value digits: 8'd\n        if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)&&config_write) begin\n                                                               ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:141: Unsupported or unknown PLI call: $intra_tile_addr\n        if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)&&config_write) begin\n                                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_tile_new/pe_tile_new.svp:160: syntax error, unexpected always\n  always @(posedge clk_in or posedge reset) begin\n  ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module `mname` (
clk_in,
config_addr,
config_data,
config_read,
config_write,




out_`$bus`_S`$i`_T`$j`,
in_`$bus`_S`$i`_T`$j`,




gin_`${i}`,

gout,
reset,
tile_id,
read_data
);

  input clk_in;
  input [31:0] config_addr;
  input [31:0] config_data;
  input config_read;
  input config_write;





  output [`$bus_width-1`:0] out_`$bus`_S`$i`_T`$j`;
  input [`$bus_width-1`:0] in_`$bus`_S`$i`_T`$j`;




  input gin_`${i}`;

  output reg gout;
  input [15:0] tile_id;
  input reset;
  output reg [31:0] read_data;
  wire clk_en;

  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;






   reg config_en_pe;
   always @(*) begin
     if (reset) begin
        config_en_pe = 1'b0;
     end else begin
        if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)&&config_write) begin
          config_en_pe = 1'b1;
        end else begin
          config_en_pe = 1'b0;
        end
     end
   end




     logic [31:0] read_data_pe;
   
   

   

  reg [31:0] opcode;

  always @(posedge clk_in or posedge reset) begin
    if (reset) begin
       opcode <= 32'd0;
    end else begin
       if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)) begin
         opcode <= config_data;
       end
    end
  end





  















































  reg config_en_cb_`$pe_input_name`;
  always @(*) begin
    if (reset) begin
       config_en_cb_`$pe_input_name` = 1'b0;
    end else begin
       if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)&&config_write) begin
         config_en_cb_`$pe_input_name` = 1'b1;
       end else begin
         config_en_cb_`$pe_input_name` = 1'b0;
       end
    end
  end
  logic [31:0] read_data_cb_`$pe_input_name`;























  wire [15:0] `$pe_input_name`;

  wire `$pe_input_name`;

  `$cb->instantiate()`
  (
    .clk(clk_in),
    .reset(reset),
    .out(`$pe_input_name`),











    .in_`$k`(`${dirn}`_BUS16_S`${xside}`_T`${track}`),


    .in_`$k`(`${dirn}`_BUS1_S`${xside}`_T`${track}`),






    .in_`$k`(gin_`${i}`),



    .config_addr(config_addr),
    .config_data(config_data),
    .config_en(config_en_cb_`$pe_input_name`),
    .read_data(read_data_cb_`$pe_input_name`)
  );







    wire pe_out_irq;

  assign clk_en = ~cg_en;







  reg config_en_sb_wide;
  always @(*) begin
    if (reset) begin
       config_en_sb_wide = 1'b0;
    end else begin
       if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)&&config_write) begin
         config_en_sb_wide = 1'b1;
       end else begin
         config_en_sb_wide = 1'b0;
       end
    end
  end
  logic [31:0] read_data_sb_wide;























  wire [`2*$wide_bus_width-1`:0] pe_out_`$pe_output`;

  wire [`$wide_bus_width-1`:0] pe_out_`$pe_output`;




  `$sb_wide->instantiate()`
  (
    .clk(clk_in),
    .clk_en(clk_en),
    .reset(reset),

    .pe_output_`$output_count`(pe_out_`$pe_output`),





    .out_`$i`_`$j`(out_BUS16_S`$i`_T`$j`),
    .in_`$i`_`$j`(in_BUS16_S`$i`_T`$j`),




    .config_addr(config_addr),
    .config_data(config_data),
    .config_en(config_en_sb_wide),
    .read_data(read_data_sb_wide)
  );













  reg config_en_sb_1bit;
  always @(*) begin
    if (reset) begin
       config_en_sb_1bit = 1'b0;
    end else begin
       if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)&&config_write) begin
         config_en_sb_1bit = 1'b1;
       end else begin
         config_en_sb_1bit = 1'b0;
       end
    end
  end
  logic [31:0] read_data_sb_1bit;












  wire pe_out_`$pe_output`;



  `$sb_1b->instantiate()`
  (
    .clk(clk_in),
    .clk_en(clk_en),
    .reset(reset),

    .pe_output_`$output_count`(pe_out_`$pe_output`),





    .out_`$i`_`$j`(out_BUS1_S`$i`_T`$j`),
    .in_`$i`_`$j`(in_BUS1_S`$i`_T`$j`),




    .config_addr(config_addr),
    .config_data(config_data),
    .config_en(config_en_sb_1bit),
    .read_data(read_data_sb_1bit)
  );



















  reg [`$number_of_gout_select_bits_needed - 1`:0] gout_sel;
  always @(posedge clk_in or posedge reset) begin
    if (reset==1'b1) begin
       gout_sel <= `$number_of_gout_select_bits_needed`'d0;
    end else begin
       if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)) begin
         gout_sel  <= config_data[`$number_of_gout_select_bits_needed - 1`:0];
       end
    end
  end


  always @(*) begin
    case (gout_sel)





      default: gout = 1'b0;

      `$number_of_gout_select_bits_needed`'d`$count`: gout = `${pe_output}`;





    endcase
  end
























`$pe->instantiate()`
 (

  .clk(clk_in),
  .rst_n(~reset),
  .clk_en(clk_en),


  .cfg_d(config_data[31:0]),
  .cfg_a(config_addr[31:24]),
  .cfg_en(config_en_pe),

  .op_code(opcode[15:0]),







  .`$1`(`$1`),


  .`$port`(pe_out_`$port`),





  .`$port`(pe_out_`$port`),

  .`$port`(pe_out_`$port`),



      .irq(pe_out_irq),

  .read_data(read_data_pe)
);








always_comb begin
    if (config_read && (config_addr[15:0]==tile_id)) begin
        case (config_addr[23:16])


          8'd`$tile_info_hash->{$key}->{'address'}` : read_data = read_data_`$key`;

               8'd`$tile_info_hash->{$key}->{'address'}` : read_data = gout_sel;


          default : read_data = 'd0;
        endcase
    end 
    else
        read_data = 'd0;
end







































































endmodule
module `mname` (
clk_in,
config_addr,
config_data,
config_read,
config_write,




out_`$bus`_S`$i`_T`$j`,
in_`$bus`_S`$i`_T`$j`,




gin_`${i}`,

gout,
reset,
tile_id,
read_data
);


  input clk_in;
  input [31:0] config_addr;
  input [31:0] config_data;
  input config_read;
  input config_write;





  output [`$bus_width-1`:0] out_`$bus`_S`$i`_T`$j`;
  input [`$bus_width-1`:0] in_`$bus`_S`$i`_T`$j`;




  input gin_`${i}`;

  output reg gout;
  input [15:0] tile_id;
  input reset;
  output reg [31:0] read_data;
  wire clk_en;

  wire ___genesis_wire_`${global_signal_count}`_`${bus_config}`_`${all_segments_for_all_tiles}`_`${sides}`_`${feedthrough_outputs}`_`${registered_outputs}`_`${is_bidi}`_`${sb_fs}`_`${cb_connections}`_`${has_constant}`_`${reg_inputs}`_`${reg_out}`_`${use_add}`_`${use_cntr}`_`${use_bool}`_`${use_shift}`_`${mult_mode}`_`${use_div}`_`${is_msb}`_`${en_double}`_`${lut_inps}`;






   reg config_en_pe;
   always @(*) begin
     if (reset) begin
        config_en_pe = 1'b0;
     end else begin
        if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)&&config_write) begin
          config_en_pe = 1'b1;
        end else begin
          config_en_pe = 1'b0;
        end
     end
   end




     logic [31:0] read_data_pe;
   
   

   

  reg [31:0] opcode;

  always @(posedge clk_in or posedge reset) begin
    if (reset) begin
       opcode <= 32'd0;
    end else begin
       if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)) begin
         opcode <= config_data;
       end
    end
  end





  















































  reg config_en_cb_`$pe_input_name`;
  always @(*) begin
    if (reset) begin
       config_en_cb_`$pe_input_name` = 1'b0;
    end else begin
       if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)&&config_write) begin
         config_en_cb_`$pe_input_name` = 1'b1;
       end else begin
         config_en_cb_`$pe_input_name` = 1'b0;
       end
    end
  end
  logic [31:0] read_data_cb_`$pe_input_name`;























  wire [15:0] `$pe_input_name`;

  wire `$pe_input_name`;

  `$cb->instantiate()`
  (
    .clk(clk_in),
    .reset(reset),
    .out(`$pe_input_name`),











    .in_`$k`(`${dirn}`_BUS16_S`${xside}`_T`${track}`),


    .in_`$k`(`${dirn}`_BUS1_S`${xside}`_T`${track}`),






    .in_`$k`(gin_`${i}`),



    .config_addr(config_addr),
    .config_data(config_data),
    .config_en(config_en_cb_`$pe_input_name`),
    .read_data(read_data_cb_`$pe_input_name`)
  );







    wire pe_out_irq;

  assign clk_en = ~cg_en;







  reg config_en_sb_wide;
  always @(*) begin
    if (reset) begin
       config_en_sb_wide = 1'b0;
    end else begin
       if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)&&config_write) begin
         config_en_sb_wide = 1'b1;
       end else begin
         config_en_sb_wide = 1'b0;
       end
    end
  end
  logic [31:0] read_data_sb_wide;























  wire [`2*$wide_bus_width-1`:0] pe_out_`$pe_output`;

  wire [`$wide_bus_width-1`:0] pe_out_`$pe_output`;




  `$sb_wide->instantiate()`
  (
    .clk(clk_in),
    .clk_en(clk_en),
    .reset(reset),

    .pe_output_`$output_count`(pe_out_`$pe_output`),





    .out_`$i`_`$j`(out_BUS16_S`$i`_T`$j`),
    .in_`$i`_`$j`(in_BUS16_S`$i`_T`$j`),




    .config_addr(config_addr),
    .config_data(config_data),
    .config_en(config_en_sb_wide),
    .read_data(read_data_sb_wide)
  );













  reg config_en_sb_1bit;
  always @(*) begin
    if (reset) begin
       config_en_sb_1bit = 1'b0;
    end else begin
       if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)&&config_write) begin
         config_en_sb_1bit = 1'b1;
       end else begin
         config_en_sb_1bit = 1'b0;
       end
    end
  end
  logic [31:0] read_data_sb_1bit;












  wire pe_out_`$pe_output`;



  `$sb_1b->instantiate()`
  (
    .clk(clk_in),
    .clk_en(clk_en),
    .reset(reset),

    .pe_output_`$output_count`(pe_out_`$pe_output`),





    .out_`$i`_`$j`(out_BUS1_S`$i`_T`$j`),
    .in_`$i`_`$j`(in_BUS1_S`$i`_T`$j`),




    .config_addr(config_addr),
    .config_data(config_data),
    .config_en(config_en_sb_1bit),
    .read_data(read_data_sb_1bit)
  );



















  reg [`$number_of_gout_select_bits_needed - 1`:0] gout_sel;
  always @(posedge clk_in or posedge reset) begin
    if (reset==1'b1) begin
       gout_sel <= `$number_of_gout_select_bits_needed`'d0;
    end else begin
       if ((config_addr[15:0]==tile_id)&&(config_addr[23:16]==8'd`$intra_tile_addr`)) begin
         gout_sel  <= config_data[`$number_of_gout_select_bits_needed - 1`:0];
       end
    end
  end


  always @(*) begin
    case (gout_sel)





      default: gout = 1'b0;

      `$number_of_gout_select_bits_needed`'d`$count`: gout = `${pe_output}`;





    endcase
  end
























`$pe->instantiate()`
 (

  .clk(clk_in),
  .rst_n(~reset),
  .clk_en(clk_en),


  .cfg_d(config_data[31:0]),
  .cfg_a(config_addr[31:24]),
  .cfg_en(config_en_pe),

  .op_code(opcode[15:0]),







  .`$1`(`$1`),


  .`$port`(pe_out_`$port`),





  .`$port`(pe_out_`$port`),

  .`$port`(pe_out_`$port`),



      .irq(pe_out_irq),

  .read_data(read_data_pe)
);








always_comb begin
    if (config_read && (config_addr[15:0]==tile_id)) begin
        case (config_addr[23:16])


          8'd`$tile_info_hash->{$key}->{'address'}` : read_data = read_data_`$key`;

               8'd`$tile_info_hash->{$key}->{'address'}` : read_data = gout_sel;


          default : read_data = 'd0;
        endcase
    end 
    else
        read_data = 'd0;
end







































































endmodule