data/full_repos/permissive/170402453/TestPWM.v
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-STMTDLY: data/full_repos/permissive/170402453/TestPWM.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/170402453/TestPWM.v:52: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Error: data/full_repos/permissive/170402453/TestPWM.v:36: Cannot find file containing module: \'PWM\'\n PWM uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/PWM\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/PWM.v\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/PWM.sv\n             PWM\n             PWM.v\n             PWM.sv\n             obj_dir/PWM\n             obj_dir/PWM.v\n             obj_dir/PWM.sv\n%Warning-WIDTH: data/full_repos/permissive/170402453/TestPWM.v:51: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                 : ... In instance TestPWM\n   DUTY_CYCLE=i;\n             ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestPWM(input CLK);


	reg [7:0] DUTY_CYCLE;
	
	integer i;


	wire PWM_OUT;


	PWM uut (
		.CLK(CLK), 
		.DUTY_CYCLE(DUTY_CYCLE), 
		.PWM_OUT(PWM_OUT)
	);

	initial begin

		DUTY_CYCLE = 0;


		#100;
        

		for(i=0;i<100;i=i+1) begin
			DUTY_CYCLE=i;
			#1;
		end

	end
	
      
endmodule
module TestPWM(input CLK);



	reg [7:0] DUTY_CYCLE;
	
	integer i;


	wire PWM_OUT;


	PWM uut (
		.CLK(CLK), 
		.DUTY_CYCLE(DUTY_CYCLE), 
		.PWM_OUT(PWM_OUT)
	);

	initial begin

		DUTY_CYCLE = 0;


		#100;
        

		for(i=0;i<100;i=i+1) begin
			DUTY_CYCLE=i;
			#1;
		end

	end
	
      
endmodule