data/full_repos/permissive/162400762/firewall_action.v
1: b'%Error: data/full_repos/permissive/162400762/firewall_action.v:77: Cannot find file containing module: \'ram_1_8\'\nram_1_8 action_table (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162400762,data/full_repos/permissive/162400762/ram_1_8\n             data/full_repos/permissive/162400762,data/full_repos/permissive/162400762/ram_1_8.v\n             data/full_repos/permissive/162400762,data/full_repos/permissive/162400762/ram_1_8.sv\n             ram_1_8\n             ram_1_8.v\n             ram_1_8.sv\n             obj_dir/ram_1_8\n             obj_dir/ram_1_8.v\n             obj_dir/ram_1_8.sv\n%Error: data/full_repos/permissive/162400762/firewall_action.v:90: Cannot find file containing module: \'fifo_134_64\'\nfifo_134_64 cdata_buffer(\n^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/162400762/firewall_action.v:153: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n                                                                          : ... In instance Firewall_action\n  idx_actionTb_conf <= {w_actionTb{1\'b0}};\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module Firewall_action(
	clk,
	reset,

	ruleID_valid,
	ruleID,
	action_valid,
	action,


	cin_data_wr,
	cin_data,
	cin_ready,
	cout_data_wr,
	cout_data,
	cout_ready
);

parameter 	LMID = 7,
			w_pkt = 134,
			w_ruleID = 16,
			w_actionTb = 1,
			d_actionTb = 3,
			words_actionTb = 8;

input								clk;
input								reset;
input								ruleID_valid;
input			[w_ruleID-1:0]		ruleID;
output	reg							action_valid;
output	reg							action;

input								cin_data_wr;
input			[w_pkt-1:0]			cin_data;
output	reg							cin_ready;
output	reg							cout_data_wr;
output reg		[w_pkt-1:0]			cout_data;
input								cout_ready;





reg				[d_actionTb-1:0]	idx_actionTb_search, idx_actionTb_conf;
reg									rden_actionTb_search, rden_actionTb_conf;
reg									wren_actionTb_conf;
reg									data_actionTb_conf;
wire								ctx_actionTb_search, ctx_actionTb_conf;


reg									rdreq_cdata;
wire								empty_cdata;
wire			[133:0]				q_cdata;


reg						valid_temp[2:0], hit_temp[2:0];

reg				[3:0]				state_conf;
parameter		IDLE_S				= 4'd0,
				READ_FIFO_S		= 4'd1,
				WAIT_RAM_1_S		= 4'd2,
				WAIT_RAM_2_S		= 4'd3,
				READ_RAM_S		= 4'd4,
				WAIT_END			= 4'd5;


ram_1_8 action_table (
  .clka(clk),
  .wea(1'b0),
  .addra(idx_actionTb_search),
  .dina(1'b0),
  .douta(ctx_actionTb_search),
  .clkb(clk),
  .web(wren_actionTb_conf),
  .addrb(idx_actionTb_conf),
  .dinb(data_actionTb_conf),
  .doutb(ctx_actionTb_conf)
);

fifo_134_64 cdata_buffer(
  .clk(clk),
  .srst(!reset),
  .din(cin_data),
  .wr_en(cin_data_wr),
  .rd_en(rdreq_cdata),
  .dout(q_cdata),
  .full(),
  .empty(empty_cdata)

);



always @(posedge clk or negedge reset) begin
	if (!reset) begin

		rden_actionTb_search <= 1'b0;
		idx_actionTb_search <= {d_actionTb{1'b0}};
		valid_temp[0] <= 1'b0;
		valid_temp[1] <= 1'b0;
		valid_temp[2] <= 1'b0;
	end
	else begin
		if(ruleID_valid == 1'b1) begin
			rden_actionTb_search <= 1'b1;
			idx_actionTb_search <= ruleID[d_actionTb-1:0];
			valid_temp[0] <= 1'b1;
		end
		else begin
			rden_actionTb_search <= 1'b0;
			valid_temp[0] <= 1'b0;
		end
		valid_temp[1] <= valid_temp[0];
		valid_temp[2] <= valid_temp[1];
	end
end



always @(posedge clk or negedge reset) begin
	if (!reset) begin

		action_valid <= 1'b0;
		action <= 1'b0;
	end
	else begin
		action_valid <= valid_temp[2];
		if(ctx_actionTb_search == 1'b1) action <= 1'b1;
		else action <= 1'b0;

	end
end



always @(posedge clk or negedge reset) begin
	if (!reset) begin

		cout_data_wr <= 1'b0;
		cout_data <= 134'b0;
		cin_ready <= 1'b1;

		idx_actionTb_conf <= {w_actionTb{1'b0}};
		wren_actionTb_conf <= 1'b0;
		data_actionTb_conf <= 1'b0;
		rden_actionTb_conf <= 1'b1;
		rdreq_cdata <= 1'b0;

		state_conf <= IDLE_S;
	end
	else begin
		case(state_conf)
			IDLE_S: begin

				wren_actionTb_conf <= 1'b0;
				rden_actionTb_conf <= 1'b0;
				cout_data_wr <= 1'b0;

				if((empty_cdata == 1'b0) && (cout_ready == 1'b1)) begin
					rdreq_cdata <= 1'b1;
					state_conf <= READ_FIFO_S;
				end
				else begin
					rdreq_cdata <= 1'b0;
					state_conf <= IDLE_S;
				end
			end
			READ_FIFO_S: begin
				if(q_cdata[103:96] == LMID) begin
					if(q_cdata[126:124] == 3'b001) begin

						cout_data <= {q_cdata[133:127], 3'b011, q_cdata[123:112], q_cdata[103:96],
							q_cdata[111:104],q_cdata[95:64], 64'b0};
						rdreq_cdata <= 1'b0;
						rden_actionTb_conf <= 1'b1;
						idx_actionTb_conf <= q_cdata[71+d_actionTb:72];
						state_conf <= WAIT_RAM_1_S;
					end
					else if((q_cdata[126:124] == 3'b010)&&(q_cdata[66:64] == 3'b0)) begin

						cout_data_wr <= 1'b0;
						cout_data <= q_cdata;

						idx_actionTb_conf <= q_cdata[71+d_actionTb:72];
						wren_actionTb_conf <= 1'b1;
						data_actionTb_conf <= q_cdata[0];
						state_conf <= WAIT_END;
					end
					else begin
						cout_data_wr <= 1'b0;
						state_conf <= WAIT_END;
					end
				end
				else begin
					cout_data_wr <= 1'b1;
					cout_data <= q_cdata;
					state_conf <= WAIT_END;
				end
			end
			WAIT_RAM_1_S: begin
				state_conf <= WAIT_RAM_2_S;
			end
			WAIT_RAM_2_S: begin
				state_conf <= READ_RAM_S;
			end
			READ_RAM_S: begin
				cout_data_wr <= 1'b1;
				if(ctx_actionTb_conf == 1'b1) cout_data[0] <= 1'b1;
				else cout_data[0] <= 1'b0;

				rdreq_cdata <= 1'b1;
				state_conf <= WAIT_END;
			end
			WAIT_END: begin
				wren_actionTb_conf <= 1'b0;
				cout_data <= q_cdata;
				if(q_cdata[133:132] == 2'b10) begin
					rdreq_cdata <= 1'b0;
					state_conf <= IDLE_S;
				end
				else begin
					state_conf <= WAIT_END;
				end
			end
			default: begin
				state_conf <= IDLE_S;
			end
		endcase
	end
end


endmodule
module Firewall_action(
	clk,
	reset,

	ruleID_valid,
	ruleID,
	action_valid,
	action,


	cin_data_wr,
	cin_data,
	cin_ready,
	cout_data_wr,
	cout_data,
	cout_ready
);


parameter 	LMID = 7,
			w_pkt = 134,
			w_ruleID = 16,
			w_actionTb = 1,
			d_actionTb = 3,
			words_actionTb = 8;

input								clk;
input								reset;
input								ruleID_valid;
input			[w_ruleID-1:0]		ruleID;
output	reg							action_valid;
output	reg							action;

input								cin_data_wr;
input			[w_pkt-1:0]			cin_data;
output	reg							cin_ready;
output	reg							cout_data_wr;
output reg		[w_pkt-1:0]			cout_data;
input								cout_ready;





reg				[d_actionTb-1:0]	idx_actionTb_search, idx_actionTb_conf;
reg									rden_actionTb_search, rden_actionTb_conf;
reg									wren_actionTb_conf;
reg									data_actionTb_conf;
wire								ctx_actionTb_search, ctx_actionTb_conf;


reg									rdreq_cdata;
wire								empty_cdata;
wire			[133:0]				q_cdata;


reg						valid_temp[2:0], hit_temp[2:0];

reg				[3:0]				state_conf;
parameter		IDLE_S				= 4'd0,
				READ_FIFO_S		= 4'd1,
				WAIT_RAM_1_S		= 4'd2,
				WAIT_RAM_2_S		= 4'd3,
				READ_RAM_S		= 4'd4,
				WAIT_END			= 4'd5;


ram_1_8 action_table (
  .clka(clk),
  .wea(1'b0),
  .addra(idx_actionTb_search),
  .dina(1'b0),
  .douta(ctx_actionTb_search),
  .clkb(clk),
  .web(wren_actionTb_conf),
  .addrb(idx_actionTb_conf),
  .dinb(data_actionTb_conf),
  .doutb(ctx_actionTb_conf)
);

fifo_134_64 cdata_buffer(
  .clk(clk),
  .srst(!reset),
  .din(cin_data),
  .wr_en(cin_data_wr),
  .rd_en(rdreq_cdata),
  .dout(q_cdata),
  .full(),
  .empty(empty_cdata)

);



always @(posedge clk or negedge reset) begin
	if (!reset) begin

		rden_actionTb_search <= 1'b0;
		idx_actionTb_search <= {d_actionTb{1'b0}};
		valid_temp[0] <= 1'b0;
		valid_temp[1] <= 1'b0;
		valid_temp[2] <= 1'b0;
	end
	else begin
		if(ruleID_valid == 1'b1) begin
			rden_actionTb_search <= 1'b1;
			idx_actionTb_search <= ruleID[d_actionTb-1:0];
			valid_temp[0] <= 1'b1;
		end
		else begin
			rden_actionTb_search <= 1'b0;
			valid_temp[0] <= 1'b0;
		end
		valid_temp[1] <= valid_temp[0];
		valid_temp[2] <= valid_temp[1];
	end
end



always @(posedge clk or negedge reset) begin
	if (!reset) begin

		action_valid <= 1'b0;
		action <= 1'b0;
	end
	else begin
		action_valid <= valid_temp[2];
		if(ctx_actionTb_search == 1'b1) action <= 1'b1;
		else action <= 1'b0;

	end
end



always @(posedge clk or negedge reset) begin
	if (!reset) begin

		cout_data_wr <= 1'b0;
		cout_data <= 134'b0;
		cin_ready <= 1'b1;

		idx_actionTb_conf <= {w_actionTb{1'b0}};
		wren_actionTb_conf <= 1'b0;
		data_actionTb_conf <= 1'b0;
		rden_actionTb_conf <= 1'b1;
		rdreq_cdata <= 1'b0;

		state_conf <= IDLE_S;
	end
	else begin
		case(state_conf)
			IDLE_S: begin

				wren_actionTb_conf <= 1'b0;
				rden_actionTb_conf <= 1'b0;
				cout_data_wr <= 1'b0;

				if((empty_cdata == 1'b0) && (cout_ready == 1'b1)) begin
					rdreq_cdata <= 1'b1;
					state_conf <= READ_FIFO_S;
				end
				else begin
					rdreq_cdata <= 1'b0;
					state_conf <= IDLE_S;
				end
			end
			READ_FIFO_S: begin
				if(q_cdata[103:96] == LMID) begin
					if(q_cdata[126:124] == 3'b001) begin

						cout_data <= {q_cdata[133:127], 3'b011, q_cdata[123:112], q_cdata[103:96],
							q_cdata[111:104],q_cdata[95:64], 64'b0};
						rdreq_cdata <= 1'b0;
						rden_actionTb_conf <= 1'b1;
						idx_actionTb_conf <= q_cdata[71+d_actionTb:72];
						state_conf <= WAIT_RAM_1_S;
					end
					else if((q_cdata[126:124] == 3'b010)&&(q_cdata[66:64] == 3'b0)) begin

						cout_data_wr <= 1'b0;
						cout_data <= q_cdata;

						idx_actionTb_conf <= q_cdata[71+d_actionTb:72];
						wren_actionTb_conf <= 1'b1;
						data_actionTb_conf <= q_cdata[0];
						state_conf <= WAIT_END;
					end
					else begin
						cout_data_wr <= 1'b0;
						state_conf <= WAIT_END;
					end
				end
				else begin
					cout_data_wr <= 1'b1;
					cout_data <= q_cdata;
					state_conf <= WAIT_END;
				end
			end
			WAIT_RAM_1_S: begin
				state_conf <= WAIT_RAM_2_S;
			end
			WAIT_RAM_2_S: begin
				state_conf <= READ_RAM_S;
			end
			READ_RAM_S: begin
				cout_data_wr <= 1'b1;
				if(ctx_actionTb_conf == 1'b1) cout_data[0] <= 1'b1;
				else cout_data[0] <= 1'b0;

				rdreq_cdata <= 1'b1;
				state_conf <= WAIT_END;
			end
			WAIT_END: begin
				wren_actionTb_conf <= 1'b0;
				cout_data <= q_cdata;
				if(q_cdata[133:132] == 2'b10) begin
					rdreq_cdata <= 1'b0;
					state_conf <= IDLE_S;
				end
				else begin
					state_conf <= WAIT_END;
				end
			end
			default: begin
				state_conf <= IDLE_S;
			end
		endcase
	end
end


endmodule