data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v
 line:64: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:7: Unsupported: Ignoring delay on this delayed statement.\n        #20 reset = 1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #2 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #21  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #8\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #4 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #4 #4 #4 \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #4 #4 #4 \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #4 #4 #4 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #4 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #8\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #4 #4 #4\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #4 #4 #4\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #4 #4 #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:96: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #4 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:112: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:114: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:117: Unsupported: Ignoring delay on this delayed statement.\n        #8\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #8\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:126: Unsupported: Ignoring delay on this delayed statement.\n        #8\n        ^\n%Error: data/full_repos/permissive/161029703/src/uma/BusController/BusController_stimulus.v:30: Cannot find file containing module: \'BusController\'\n    BusController controller(.clk(clk), .reset(reset), \n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161029703/src/uma/BusController,data/full_repos/permissive/161029703/BusController\n             data/full_repos/permissive/161029703/src/uma/BusController,data/full_repos/permissive/161029703/BusController.v\n             data/full_repos/permissive/161029703/src/uma/BusController,data/full_repos/permissive/161029703/BusController.sv\n             BusController\n             BusController.v\n             BusController.sv\n             obj_dir/BusController\n             obj_dir/BusController.v\n             obj_dir/BusController.sv\n%Error: Exiting due to 1 error(s), 26 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module BusController_stimulus;
    reg clk, reset;
  
    initial begin
        clk = 1'b1;
        reset = 1'b1;
        #20 reset = 1'b0;
    end
    always
        #2 clk = ~clk;
  
    reg  [31:0] master_addr0, master_addr1, master_addr2;
    wire [31:0] master_rdata;
    reg  [31:0] master_wdata0, master_wdata1, master_wdata2;
    reg         master_rreq0, master_wreq0, master_rreq1, master_wreq1, master_rreq2, master_wreq2;
    wire [3:0]  master_acc;
    wire        master_busy;
  
    wire [31:0] slave_addr;
    reg  [31:0] slave_rdata0, slave_rdata1, slave_rdata2;
    wire [31:0] slave_wdata;
    wire        slave_rreq, slave_wreq;
    reg         slave_busy0, slave_busy1, slave_busy2;
    reg         slave_ack0, slave_ack1, slave_ack2;
    
    wire        seg_fault;
    wire [2:0]  seg_reason;
    wire [31:0] seg_addr;
  
    BusController controller(.clk(clk), .reset(reset), 
                              .master_addr({32'b0, master_addr2, master_addr1, master_addr0}), 
                              .master_rdata(master_rdata), 
                              .master_wdata({32'b0, master_wdata2, master_wdata1, master_wdata0}), 
                              .master_rreq({1'b0, master_rreq2, master_rreq1, master_rreq0}), 
                              .master_wreq({1'b0, master_wreq2, master_wreq1, master_wreq0}), 
                              .master_acc(master_acc), 
                              .master_busy(master_busy),
                              .slave_addr(slave_addr), 
                              .slave_rdata({160'b0, slave_rdata2, slave_rdata1, slave_rdata0}), 
                              .slave_wdata(slave_wdata), 
                              .slave_rreq(slave_rreq), 
                              .slave_wreq(slave_wreq), 
                              .slave_busy({5'h0, slave_busy2, slave_busy1, slave_busy0}),
                              .slave_ack({5'h0, slave_ack2, slave_ack1, slave_ack0}),
                              .seg_fault(seg_fault),
                              .seg_reason(seg_reason),
                              .seg_addr(seg_addr));
  
  
    initial begin
        master_rreq0 = 0;
        master_wreq0 = 0;
        master_rreq1 = 0;
        master_wreq1 = 0;
        master_rreq2 = 0;
        master_wreq2 = 0;
        slave_ack0 = 0;
        slave_ack1 = 0;
        slave_ack2 = 0;
        slave_busy0 = 0;
        slave_busy1 = 0;
        slave_busy2 = 0;
        #21  
        #4
        master_rreq0 = 1;
        master_rreq1 = 1;
        #8
        master_addr0 = 32'h8004;
        slave_ack0 = 1;
        #4
        master_addr0 = 32'h8008;
        slave_busy0 = 0;
        slave_rdata0 = 32'h2333;
        #4
        master_rreq0 = 0;
        master_addr0 = 32'h800C;
        slave_rdata0 = 32'h2444;
        #4 
        slave_ack0 = 0;
        slave_rdata0 = 32'h2555;
        #4 #4 #4 
        master_rreq1 = 0;
        master_addr1 = 32'h2004;
        slave_ack1 = 1;
        master_wreq2 = 1;
        #4 
        slave_ack1 = 0;
        slave_busy1 = 1;
        #8
        slave_busy1 = 0;
        slave_rdata1 = 32'h7444;
        #4 #4 #4
        master_addr2 = 32'h100;
        master_wdata2 = 32'h23;
        slave_ack2 = 1;
        #4
        master_addr2 = 32'h104;
        master_wdata2 = 32'h24;
        slave_busy2 = 1;
        #4 
        master_addr2 = 32'hx;
        master_wdata2 = 32'hx;
        slave_busy2 = 0;
        #4
        master_wreq2 = 0;
        master_addr2 = 32'h108;
        master_wdata2 = 32'h25;
        slave_busy2 = 1;
        #4
        master_addr2 = 32'hx;
        master_wdata2 = 32'hx;
        #4
        slave_busy2 = 0;
        #4
        slave_busy2 = 1;
        slave_ack2 = 0;
        #8
        slave_busy2 = 0;
        #4
        master_wreq0 = 1;
        #8
        master_wreq0 = 0;
        master_addr0 = 32'h10C;
        master_wdata0 = 32'h66;
        slave_ack2 = 1;
        #8
        slave_ack2 = 0;
    end

endmodule
module BusController_stimulus;

    reg clk, reset;
  
    initial begin
        clk = 1'b1;
        reset = 1'b1;
        #20 reset = 1'b0;
    end
    always
        #2 clk = ~clk;
  
    reg  [31:0] master_addr0, master_addr1, master_addr2;
    wire [31:0] master_rdata;
    reg  [31:0] master_wdata0, master_wdata1, master_wdata2;
    reg         master_rreq0, master_wreq0, master_rreq1, master_wreq1, master_rreq2, master_wreq2;
    wire [3:0]  master_acc;
    wire        master_busy;
  
    wire [31:0] slave_addr;
    reg  [31:0] slave_rdata0, slave_rdata1, slave_rdata2;
    wire [31:0] slave_wdata;
    wire        slave_rreq, slave_wreq;
    reg         slave_busy0, slave_busy1, slave_busy2;
    reg         slave_ack0, slave_ack1, slave_ack2;
    
    wire        seg_fault;
    wire [2:0]  seg_reason;
    wire [31:0] seg_addr;
  
    BusController controller(.clk(clk), .reset(reset), 
                              .master_addr({32'b0, master_addr2, master_addr1, master_addr0}), 
                              .master_rdata(master_rdata), 
                              .master_wdata({32'b0, master_wdata2, master_wdata1, master_wdata0}), 
                              .master_rreq({1'b0, master_rreq2, master_rreq1, master_rreq0}), 
                              .master_wreq({1'b0, master_wreq2, master_wreq1, master_wreq0}), 
                              .master_acc(master_acc), 
                              .master_busy(master_busy),
                              .slave_addr(slave_addr), 
                              .slave_rdata({160'b0, slave_rdata2, slave_rdata1, slave_rdata0}), 
                              .slave_wdata(slave_wdata), 
                              .slave_rreq(slave_rreq), 
                              .slave_wreq(slave_wreq), 
                              .slave_busy({5'h0, slave_busy2, slave_busy1, slave_busy0}),
                              .slave_ack({5'h0, slave_ack2, slave_ack1, slave_ack0}),
                              .seg_fault(seg_fault),
                              .seg_reason(seg_reason),
                              .seg_addr(seg_addr));
  
  
    initial begin
        master_rreq0 = 0;
        master_wreq0 = 0;
        master_rreq1 = 0;
        master_wreq1 = 0;
        master_rreq2 = 0;
        master_wreq2 = 0;
        slave_ack0 = 0;
        slave_ack1 = 0;
        slave_ack2 = 0;
        slave_busy0 = 0;
        slave_busy1 = 0;
        slave_busy2 = 0;
        #21  
        #4
        master_rreq0 = 1;
        master_rreq1 = 1;
        #8
        master_addr0 = 32'h8004;
        slave_ack0 = 1;
        #4
        master_addr0 = 32'h8008;
        slave_busy0 = 0;
        slave_rdata0 = 32'h2333;
        #4
        master_rreq0 = 0;
        master_addr0 = 32'h800C;
        slave_rdata0 = 32'h2444;
        #4 
        slave_ack0 = 0;
        slave_rdata0 = 32'h2555;
        #4 #4 #4 
        master_rreq1 = 0;
        master_addr1 = 32'h2004;
        slave_ack1 = 1;
        master_wreq2 = 1;
        #4 
        slave_ack1 = 0;
        slave_busy1 = 1;
        #8
        slave_busy1 = 0;
        slave_rdata1 = 32'h7444;
        #4 #4 #4
        master_addr2 = 32'h100;
        master_wdata2 = 32'h23;
        slave_ack2 = 1;
        #4
        master_addr2 = 32'h104;
        master_wdata2 = 32'h24;
        slave_busy2 = 1;
        #4 
        master_addr2 = 32'hx;
        master_wdata2 = 32'hx;
        slave_busy2 = 0;
        #4
        master_wreq2 = 0;
        master_addr2 = 32'h108;
        master_wdata2 = 32'h25;
        slave_busy2 = 1;
        #4
        master_addr2 = 32'hx;
        master_wdata2 = 32'hx;
        #4
        slave_busy2 = 0;
        #4
        slave_busy2 = 1;
        slave_ack2 = 0;
        #8
        slave_busy2 = 0;
        #4
        master_wreq0 = 1;
        #8
        master_wreq0 = 0;
        master_addr0 = 32'h10C;
        master_wdata0 = 32'h66;
        slave_ack2 = 1;
        #8
        slave_ack2 = 0;
    end

endmodule