data/full_repos/permissive/206842334/src/sig_altmult_accum2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/206842334/src/sig_altmult_accum2.v:27: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'accum_out\' generates 18 bits.\n                                                                                : ... In instance sig_altmult_accum2\n   old_result <= accum_out;\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sig_altmult_accum2
(
	input [7:0] dataa,
	input [7:0] datab,
	input clk, aclr, clken, sload,
	output signed [17:0] adder_out
);


	reg signed [7:0] datab_reg;
	reg signed [8:0] dataa_reg;
	reg	signed [16:0] old_result;
	reg signed [17:0] accum_out;
	wire signed [17:0] multa;
	reg sload_reg;
	

	assign multa = dataa_reg * datab_reg;

	

	always @ (accum_out, sload_reg)
	begin
		if (sload_reg)
			old_result <= 0;
		else
			old_result <= accum_out;
	end

	assign adder_out = accum_out;
	

	always @ (posedge clk or posedge aclr)
	begin
		if (aclr)
		begin
			dataa_reg <= 0;
			datab_reg <= 0;
			sload_reg <= 0;
			accum_out <= 0;
		end
		
		else if (clken)
		begin
			dataa_reg <= $signed({1'b0, dataa});
			datab_reg <= $signed(datab);
			sload_reg <= sload;
			accum_out <= old_result + multa;
		end

	end
endmodule
module sig_altmult_accum2
(
	input [7:0] dataa,
	input [7:0] datab,
	input clk, aclr, clken, sload,
	output signed [17:0] adder_out
);



	reg signed [7:0] datab_reg;
	reg signed [8:0] dataa_reg;
	reg	signed [16:0] old_result;
	reg signed [17:0] accum_out;
	wire signed [17:0] multa;
	reg sload_reg;
	

	assign multa = dataa_reg * datab_reg;

	

	always @ (accum_out, sload_reg)
	begin
		if (sload_reg)
			old_result <= 0;
		else
			old_result <= accum_out;
	end

	assign adder_out = accum_out;
	

	always @ (posedge clk or posedge aclr)
	begin
		if (aclr)
		begin
			dataa_reg <= 0;
			datab_reg <= 0;
			sload_reg <= 0;
			accum_out <= 0;
		end
		
		else if (clken)
		begin
			dataa_reg <= $signed({1'b0, dataa});
			datab_reg <= $signed(datab);
			sload_reg <= sload;
			accum_out <= old_result + multa;
		end

	end
endmodule