data/full_repos/permissive/127519632/lfsr_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/127519632/lfsr_tb.sv:29: Unsupported: Ignoring delay on this delayed statement.\n #12\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/127519632/lfsr_tb.sv:33: Unsupported: Ignoring delay on this delayed statement.\n #11 rst_n = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/lfsr_tb.sv:34: Unsupported: Ignoring delay on this delayed statement.\n #200\n ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/lfsr_tb.sv:36: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/lfsr_tb.sv:40: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/127519632/lfsr_tb.sv:10: Cannot find file containing module: \'lfsr\'\nlfsr U1(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/lfsr\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/lfsr.v\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/lfsr.sv\n             lfsr\n             lfsr.v\n             lfsr.sv\n             obj_dir/lfsr\n             obj_dir/lfsr.v\n             obj_dir/lfsr.sv\n%Error: data/full_repos/permissive/127519632/lfsr_tb.sv:18: Cannot find file containing module: \'lfsr\'\nlfsr U2(\n^~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lfsr_tv;

wire carry, carry_2;
wire [3:0]random_out, random_out_2;
reg [3:0]reset_in, reset_in_2;
reg rst_n, clk, enable_n;

lfsr U1(
	carry,
	random_out,
	reset_in,
	enable_n,
	rst_n,
	clk);

lfsr U2(
	carry_2,
	random_out_2,
	reset_in_2,
	carry,
	rst_n,
	clk);

initial begin
	clk = 0;
	enable_n = 1;
	#12
	rst_n = 0;
	reset_in = 4'b1001;
	reset_in_2 = 4'b0110;
	#11 rst_n = 1;
	#200
	enable_n = 0;
	#200;
	$stop;
end

always #5 clk = ~clk;

endmodule
module lfsr_tv;


wire carry, carry_2;
wire [3:0]random_out, random_out_2;
reg [3:0]reset_in, reset_in_2;
reg rst_n, clk, enable_n;

lfsr U1(
	carry,
	random_out,
	reset_in,
	enable_n,
	rst_n,
	clk);

lfsr U2(
	carry_2,
	random_out_2,
	reset_in_2,
	carry,
	rst_n,
	clk);

initial begin
	clk = 0;
	enable_n = 1;
	#12
	rst_n = 0;
	reset_in = 4'b1001;
	reset_in_2 = 4'b0110;
	#11 rst_n = 1;
	#200
	enable_n = 0;
	#200;
	$stop;
end

always #5 clk = ~clk;

endmodule