data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v:36: Multiple top level modules\n                                                                                                                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                                                                  : ... Top module \'const0\'\nmodule const0(const0);\n       ^~~~~~\n                                                                                                                                                                                  : ... Top module \'const1\'\nmodule const1(const1);\n       ^~~~~~\n                                                                                                                                                                                  : ... Top module \'INVTX1\'\nmodule INVTX1(in,\n       ^~~~~~\n                                                                                                                                                                                  : ... Top module \'buf4\'\nmodule buf4(in,\n       ^~~~\n                                                                                                                                                                                  : ... Top module \'tap_buf4\'\nmodule tap_buf4(in,\n       ^~~~~~~~\n                                                                                                                                                                                  : ... Top module \'OR2\'\nmodule OR2(a,\n       ^~~\n                                                                                                                                                                                  : ... Top module \'TGATE\'\nmodule TGATE(in,\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v:141: Operator NOT expects 32 bits on the LHS, but LHS\'s VARREF \'in\' generates 1 bits.\n                                                                                                                                                                                : ... In instance tap_buf4\n assign out = (in === 1\'bz)? $random : ~in;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v:141: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                                                                                : ... In instance tap_buf4\n assign out = (in === 1\'bz)? $random : ~in;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v:107: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                                                                                : ... In instance buf4\n assign out = (in === 1\'bz)? $random : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v:107: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                                                                                : ... In instance buf4\n assign out = (in === 1\'bz)? $random : in;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v:73: Operator NOT expects 32 bits on the LHS, but LHS\'s VARREF \'in\' generates 1 bits.\n                                                                                                                                                                               : ... In instance INVTX1\n assign out = (in === 1\'bz)? $random : ~in;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v:73: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                                                                               : ... In instance INVTX1\n assign out = (in === 1\'bz)? $random : ~in;\n            ^\n%Error: Exiting due to 7 warning(s)\n'
module TGATE(in,
             sel,
             selb,
             out);

input [0:0] in;

input [0:0] sel;

input [0:0] selb;

output [0:0] out;








	assign out = sel ? in : 1'bz;

`ifdef ENABLE_TIMING

	specify
		(in => out) = (0.01, 0.01);
		(sel => out) = (0.005, 0.005);
		(selb => out) = (0.005, 0.005);
	endspecify

`endif
endmodule
module TGATE(in,
             sel,
             selb,
             out);


input [0:0] in;

input [0:0] sel;

input [0:0] selb;

output [0:0] out;








	assign out = sel ? in : 1'bz;

`ifdef ENABLE_TIMING

	specify
		(in => out) = (0.01, 0.01);
		(sel => out) = (0.005, 0.005);
		(selb => out) = (0.005, 0.005);
	endspecify

`endif
endmodule