data/full_repos/permissive/162533945/sll.v
1: b"%Error: data/full_repos/permissive/162533945/sll.v:13: Cannot find file containing module: 'mux_2to1_1bit'\n   mux_2to1_1bit mux0(in[i0], t0[i0], amt[4], t1[i0]);\n   ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/mux_2to1_1bit\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/mux_2to1_1bit.v\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/mux_2to1_1bit.sv\n             mux_2to1_1bit\n             mux_2to1_1bit.v\n             mux_2to1_1bit.sv\n             obj_dir/mux_2to1_1bit\n             obj_dir/mux_2to1_1bit.v\n             obj_dir/mux_2to1_1bit.sv\n%Error: data/full_repos/permissive/162533945/sll.v:24: Cannot find file containing module: 'mux_2to1_1bit'\n   mux_2to1_1bit mux1(t1[i1], t2[i1], amt[3], t3[i1]);\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162533945/sll.v:33: Cannot find file containing module: 'mux_2to1_1bit'\n   mux_2to1_1bit mux2(t3[i2], t4[i2], amt[2], t5[i2]);\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162533945/sll.v:42: Cannot find file containing module: 'mux_2to1_1bit'\n   mux_2to1_1bit mux3(t5[i3], t6[i3], amt[1], t7[i3]);\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162533945/sll.v:51: Cannot find file containing module: 'mux_2to1_1bit'\n   mux_2to1_1bit mux4(t7[i4], t8[i4], amt[0], out[i4]);\n   ^~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module shifter_left_16(in, out);

	input [31:0] in;
	output [31:0] out;
	
	genvar i;
	generate
		for (i=0;i<16;i=i+1) begin: zero
			and and0(out[i], 1'b0, 1'b0);
		end
	endgenerate
		
	genvar j;
	generate
		for (j=16;j<32;j=j+1) begin: other
			and and1(out[j], 1'b1, in[j-16]);
		end
	endgenerate

endmodule
module shifter_left_16(in, out);


	input [31:0] in;
	output [31:0] out;
	
	genvar i;
	generate
		for (i=0;i<16;i=i+1) begin: zero
			and and0(out[i], 1'b0, 1'b0);
		end
	endgenerate
		
	genvar j;
	generate
		for (j=16;j<32;j=j+1) begin: other
			and and1(out[j], 1'b1, in[j-16]);
		end
	endgenerate

endmodule