data/full_repos/permissive/122497324/assignment_4/assignment_4_tb.v
 line:63: before: "50"
1: b'%Warning-STMTDLY: data/full_repos/permissive/122497324/assignment_4/assignment_4_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/122497324/assignment_4/assignment_4_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n      #5; \n      ^\n%Error: data/full_repos/permissive/122497324/assignment_4/assignment_4_tb.v:35: Cannot find file containing module: \'assignment_4\'\n  assignment_4 dut\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122497324/assignment_4,data/full_repos/permissive/122497324/assignment_4\n             data/full_repos/permissive/122497324/assignment_4,data/full_repos/permissive/122497324/assignment_4.v\n             data/full_repos/permissive/122497324/assignment_4,data/full_repos/permissive/122497324/assignment_4.sv\n             assignment_4\n             assignment_4.v\n             assignment_4.sv\n             obj_dir/assignment_4\n             obj_dir/assignment_4.v\n             obj_dir/assignment_4.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module assignment_4_tb();


  reg clk;


  wire [31:0] databus;



  wire [31:0] cdbus;

  reg [32:0] numtests, error;
  integer num_cycles, i;
  assignment_4 dut
  (
    .clk(clk)
    
  );
  initial begin










    $display("reservation station IDs: 001=MULT, 010=ADD, 011=ST, 100=LD");
    $display("execution unit IDs:      001=MULT, 010=ADD, 011=LD/ST");
    num_cycles = 30;
    for(i=0;i < num_cycles; i= i+1) begin
      clk=0;
      $display ("\nTime=%t,  clk=%b", $realtime, clk);
      #5
      clk=1;
      $display ("\nTime=%t,  clk=%b, cycle=%d", $realtime, clk, i+1);
      #5;
    end
  end
endmodule
module assignment_4_tb();



  reg clk;


  wire [31:0] databus;



  wire [31:0] cdbus;

  reg [32:0] numtests, error;
  integer num_cycles, i;
  assignment_4 dut
  (
    .clk(clk)
    
  );
  initial begin










    $display("reservation station IDs: 001=MULT, 010=ADD, 011=ST, 100=LD");
    $display("execution unit IDs:      001=MULT, 010=ADD, 011=LD/ST");
    num_cycles = 30;
    for(i=0;i < num_cycles; i= i+1) begin
      clk=0;
      $display ("\nTime=%t,  clk=%b", $realtime, clk);
      #5
      clk=1;
      $display ("\nTime=%t,  clk=%b, cycle=%d", $realtime, clk, i+1);
      #5;
    end
  end
endmodule