data/full_repos/permissive/161526648/SingleCycle.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:300: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                      : ... In instance SingleCycle.alu\n    result = ALUsrc1 < ALUsrc2;  \n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:227: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                      : ... In instance SingleCycle.ImExtend\n assign out = $signed(in);\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module DataMem(Address,WriteData,MemWrite,MemRead,ReadData);
	input [31:0]Address,WriteData;
	input MemWrite,MemRead;
	output reg[31:0]ReadData;
	reg [31:0]DM[31:0];
	
	initial begin
		DM[0] = 32'b0;
		DM[1] = 32'b0;
		DM[2] = 32'b0;
		DM[3] = 32'b0;
		DM[4] = 32'b0;
		DM[5] = 32'b0;
		DM[6] = 32'b0;
		DM[7] = 32'b0;
		DM[8] = 32'b0;
		DM[9] = 32'b0;
		DM[10] = 32'b0;
		DM[11] = 32'b0;
		DM[12] = 32'b0;
		DM[13] = 32'b0;
		DM[14] = 32'b0;
		DM[15] = 32'b0;
		DM[16] = 32'b0;
		DM[17] = 32'b0;
		DM[18] = 32'b0;
		DM[19] = 32'b0;
		DM[20] = 32'b0;
		DM[21] = 32'b0;
		DM[22] = 32'b0;
		DM[23] = 32'b0;
		DM[24] = 32'b0;
		DM[25] = 32'b0;
		DM[26] = 32'b0;
		DM[27] = 32'b0;
		DM[28] = 32'b0;
		DM[29] = 32'b0;
		DM[30] = 32'b0;
		DM[31] = 32'b0;
	end
	
	always @(Address or WriteData or MemWrite or MemRead) begin
		if (MemRead) ReadData = DM[Address];
		if (MemWrite) DM[Address] = WriteData;
	end
endmodule
module DataMem(Address,WriteData,MemWrite,MemRead,ReadData);

	input [31:0]Address,WriteData;
	input MemWrite,MemRead;
	output reg[31:0]ReadData;
	reg [31:0]DM[31:0];
	
	initial begin
		DM[0] = 32'b0;
		DM[1] = 32'b0;
		DM[2] = 32'b0;
		DM[3] = 32'b0;
		DM[4] = 32'b0;
		DM[5] = 32'b0;
		DM[6] = 32'b0;
		DM[7] = 32'b0;
		DM[8] = 32'b0;
		DM[9] = 32'b0;
		DM[10] = 32'b0;
		DM[11] = 32'b0;
		DM[12] = 32'b0;
		DM[13] = 32'b0;
		DM[14] = 32'b0;
		DM[15] = 32'b0;
		DM[16] = 32'b0;
		DM[17] = 32'b0;
		DM[18] = 32'b0;
		DM[19] = 32'b0;
		DM[20] = 32'b0;
		DM[21] = 32'b0;
		DM[22] = 32'b0;
		DM[23] = 32'b0;
		DM[24] = 32'b0;
		DM[25] = 32'b0;
		DM[26] = 32'b0;
		DM[27] = 32'b0;
		DM[28] = 32'b0;
		DM[29] = 32'b0;
		DM[30] = 32'b0;
		DM[31] = 32'b0;
	end
	
	always @(Address or WriteData or MemWrite or MemRead) begin
		if (MemRead) ReadData = DM[Address];
		if (MemWrite) DM[Address] = WriteData;
	end
endmodule