data/full_repos/permissive/198223683/rtl/video/hshrink.v
1: b"%Error: data/full_repos/permissive/198223683/rtl/video/hshrink.v:60: Cannot find file containing module: 'FS2'\n FS2 U193(CK, U193_P, 1'b1, ~L, U193_REG);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/198223683/rtl/video,data/full_repos/permissive/198223683/FS2\n             data/full_repos/permissive/198223683/rtl/video,data/full_repos/permissive/198223683/FS2.v\n             data/full_repos/permissive/198223683/rtl/video,data/full_repos/permissive/198223683/FS2.sv\n             FS2\n             FS2.v\n             FS2.sv\n             obj_dir/FS2\n             obj_dir/FS2.v\n             obj_dir/FS2.sv\n%Error: data/full_repos/permissive/198223683/rtl/video/hshrink.v:61: Cannot find file containing module: 'BD3'\n BD3 T193A(U193_REG[3], T193A_OUT);\n ^~~\n%Error: data/full_repos/permissive/198223683/rtl/video/hshrink.v:62: Cannot find file containing module: 'FS2'\n FS2 T196(CK, T196_P, T193A_OUT, ~L, T196_REG);\n ^~~\n%Error: data/full_repos/permissive/198223683/rtl/video/hshrink.v:64: Cannot find file containing module: 'FS2'\n FS2 U243(CK, U243_P, 1'b1, ~L, U243_REG);\n ^~~\n%Error: data/full_repos/permissive/198223683/rtl/video/hshrink.v:65: Cannot find file containing module: 'BD3'\n BD3 U258A(U243_REG[3], U258A_OUT);\n ^~~\n%Error: data/full_repos/permissive/198223683/rtl/video/hshrink.v:66: Cannot find file containing module: 'FS2'\n FS2 U226(CK, U226_P, U258A_OUT, ~L, U226_REG);\n ^~~\n%Error: Exiting due to 6 error(s)\n"
module hshrink(
	input [3:0] SHRINK,
	input CK, L,
	output OUTA, OUTB
);

	wire [3:0] nSHRINK;

	wire [3:0] U193_REG;
	wire [3:0] T196_REG;
	wire [3:0] U243_REG;
	wire [3:0] U226_REG;
	
	wire [3:0] U193_P;
	wire [3:0] T196_P;
	wire [3:0] U243_P;
	wire [3:0] U226_P;
	
	assign nSHRINK[3:0] = ~SHRINK[3:0];
	

	assign U193_P[0] = ~&{nSHRINK[3:2]};
	assign U193_P[1] = ~&{nSHRINK[3:1]};
	assign U193_P[2] = ~&{nSHRINK[3], ~&{SHRINK[2:1]}};
	assign U193_P[3] = 1'b1;
	
	assign T196_P[0] = ~|{&{SHRINK[2], ~|{SHRINK[1:0], SHRINK[3]}}, ~|{SHRINK[3:2]}};
	assign T196_P[1] = ~&{nSHRINK[3:0]};
	assign T196_P[2] = ~&{~&{SHRINK[1:0]}, ~|{SHRINK[3:2]}};
	assign T196_P[3] = ~&{nSHRINK[3], ~&{SHRINK[2:0]}};
	
	assign U243_P[0] = ~|{nSHRINK[3], ~|{SHRINK[2:1]}};
	assign U243_P[1] = ~|{nSHRINK[3:2]};
	assign U243_P[2] = ~|{nSHRINK[3:1]};
	assign U243_P[3] = SHRINK[3];
	
	assign U226_P[0] = ~&{~&{SHRINK[1:0], nSHRINK[2], SHRINK[3]}, ~&{SHRINK[3:2]}};
	assign U226_P[1] = &{SHRINK[3:0]};
	assign U226_P[2] = ~|{nSHRINK[3], ~|{SHRINK[2:0]}};
	assign U226_P[3] = ~|{~&{SHRINK[3:2]}, ~|{SHRINK[1:0]}};


	wire T193A_OUT, U258A_OUT;
	FS2 U193(CK, U193_P, 1'b1, ~L, U193_REG);
	BD3 T193A(U193_REG[3], T193A_OUT);
	FS2 T196(CK, T196_P, T193A_OUT, ~L, T196_REG);
	
	FS2 U243(CK, U243_P, 1'b1, ~L, U243_REG);
	BD3 U258A(U243_REG[3], U258A_OUT);
	FS2 U226(CK, U226_P, U258A_OUT, ~L, U226_REG);
	
	assign OUTA = T196_REG[3];
	assign OUTB = U226_REG[3];

endmodule
module hshrink(
	input [3:0] SHRINK,
	input CK, L,
	output OUTA, OUTB
);


	wire [3:0] nSHRINK;

	wire [3:0] U193_REG;
	wire [3:0] T196_REG;
	wire [3:0] U243_REG;
	wire [3:0] U226_REG;
	
	wire [3:0] U193_P;
	wire [3:0] T196_P;
	wire [3:0] U243_P;
	wire [3:0] U226_P;
	
	assign nSHRINK[3:0] = ~SHRINK[3:0];
	

	assign U193_P[0] = ~&{nSHRINK[3:2]};
	assign U193_P[1] = ~&{nSHRINK[3:1]};
	assign U193_P[2] = ~&{nSHRINK[3], ~&{SHRINK[2:1]}};
	assign U193_P[3] = 1'b1;
	
	assign T196_P[0] = ~|{&{SHRINK[2], ~|{SHRINK[1:0], SHRINK[3]}}, ~|{SHRINK[3:2]}};
	assign T196_P[1] = ~&{nSHRINK[3:0]};
	assign T196_P[2] = ~&{~&{SHRINK[1:0]}, ~|{SHRINK[3:2]}};
	assign T196_P[3] = ~&{nSHRINK[3], ~&{SHRINK[2:0]}};
	
	assign U243_P[0] = ~|{nSHRINK[3], ~|{SHRINK[2:1]}};
	assign U243_P[1] = ~|{nSHRINK[3:2]};
	assign U243_P[2] = ~|{nSHRINK[3:1]};
	assign U243_P[3] = SHRINK[3];
	
	assign U226_P[0] = ~&{~&{SHRINK[1:0], nSHRINK[2], SHRINK[3]}, ~&{SHRINK[3:2]}};
	assign U226_P[1] = &{SHRINK[3:0]};
	assign U226_P[2] = ~|{nSHRINK[3], ~|{SHRINK[2:0]}};
	assign U226_P[3] = ~|{~&{SHRINK[3:2]}, ~|{SHRINK[1:0]}};


	wire T193A_OUT, U258A_OUT;
	FS2 U193(CK, U193_P, 1'b1, ~L, U193_REG);
	BD3 T193A(U193_REG[3], T193A_OUT);
	FS2 T196(CK, T196_P, T193A_OUT, ~L, T196_REG);
	
	FS2 U243(CK, U243_P, 1'b1, ~L, U243_REG);
	BD3 U258A(U243_REG[3], U258A_OUT);
	FS2 U226(CK, U226_P, U258A_OUT, ~L, U226_REG);
	
	assign OUTA = T196_REG[3];
	assign OUTB = U226_REG[3];

endmodule