data/full_repos/permissive/203526788/GoBoard/SPI_slave/top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/203526788/GoBoard/SPI_slave/top.v:3: Cannot find include file: SPI_Slave.v\n`include "SPI_Slave.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203526788/GoBoard/SPI_slave,data/full_repos/permissive/203526788/SPI_Slave.v\n             data/full_repos/permissive/203526788/GoBoard/SPI_slave,data/full_repos/permissive/203526788/SPI_Slave.v.v\n             data/full_repos/permissive/203526788/GoBoard/SPI_slave,data/full_repos/permissive/203526788/SPI_Slave.v.sv\n             SPI_Slave.v\n             SPI_Slave.v.v\n             SPI_Slave.v.sv\n             obj_dir/SPI_Slave.v\n             obj_dir/SPI_Slave.v.v\n             obj_dir/SPI_Slave.v.sv\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_slave/top.v:4: Cannot find include file: UART_TX.v\n`include "UART_TX.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_slave/top.v:5: Cannot find include file: Display.v\n`include "Display.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_slave/top.v:23: syntax error, unexpected \')\', expecting \'[\'\n);\n^\n%Error: data/full_repos/permissive/203526788/GoBoard/SPI_slave/top.v:29: syntax error, unexpected IDENTIFIER\n  DisplayNumber ns (CLK, SEG1, SEG2, in);\n  ^~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module top(
  	  input CLK,
	    output [6:0] SEG1,
	    output [6:0] SEG2,
	    output [3:0] LED,
      input SCK,
      output MISO,
      input MOSI,
      input CS,
      input SW1,
      input SW2,
      output UARTTX,
);

  wire [7:0] in;
  reg [7:0] data = 8'd0;
  wire done;

  DisplayNumber ns (CLK, SEG1, SEG2, in);



  SPI_Slave #(.SPI_MODE(0)) slave
  (

   .i_Rst_L(1'b1),
   .i_Clk(CLK),
   .o_RX_DV(done),
   .o_RX_Byte(in),
   .i_TX_DV(),
   .i_TX_Byte(),


   .i_SPI_Clk(SCK),
   .o_SPI_MISO(MISO),
   .i_SPI_MOSI(MOSI),
   .i_SPI_CS_n(CS)
   );



  UART_TX #(.CLKS_PER_BIT(217)) UART_TX_Inst
  (
     .i_Rst_L(1'b1),
     .i_Clock(CLK),
     .i_TX_DV(done),
     .i_TX_Byte(in),
     .o_TX_Active(),
     .o_TX_Serial(UARTTX),
     .o_TX_Done()
  );


  
endmodule
module top(
  	  input CLK,
	    output [6:0] SEG1,
	    output [6:0] SEG2,
	    output [3:0] LED,
      input SCK,
      output MISO,
      input MOSI,
      input CS,
      input SW1,
      input SW2,
      output UARTTX,
);


  wire [7:0] in;
  reg [7:0] data = 8'd0;
  wire done;

  DisplayNumber ns (CLK, SEG1, SEG2, in);



  SPI_Slave #(.SPI_MODE(0)) slave
  (

   .i_Rst_L(1'b1),
   .i_Clk(CLK),
   .o_RX_DV(done),
   .o_RX_Byte(in),
   .i_TX_DV(),
   .i_TX_Byte(),


   .i_SPI_Clk(SCK),
   .o_SPI_MISO(MISO),
   .i_SPI_MOSI(MOSI),
   .i_SPI_CS_n(CS)
   );



  UART_TX #(.CLKS_PER_BIT(217)) UART_TX_Inst
  (
     .i_Rst_L(1'b1),
     .i_Clock(CLK),
     .i_TX_DV(done),
     .i_TX_Byte(in),
     .o_TX_Active(),
     .o_TX_Serial(UARTTX),
     .o_TX_Done()
  );


  
endmodule