data/full_repos/permissive/144785545/FourBitCPU.v
1: b"%Error: data/full_repos/permissive/144785545/FourBitCPU.v:12: Cannot find file containing module: 'DECODER'\nDECODER dec(.CLK(CLK), .ORDER(order[7:4]), .DECODED({sela, selb, load}));\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/144785545,data/full_repos/permissive/144785545/DECODER\n             data/full_repos/permissive/144785545,data/full_repos/permissive/144785545/DECODER.v\n             data/full_repos/permissive/144785545,data/full_repos/permissive/144785545/DECODER.sv\n             DECODER\n             DECODER.v\n             DECODER.sv\n             obj_dir/DECODER\n             obj_dir/DECODER.v\n             obj_dir/DECODER.sv\n%Error: data/full_repos/permissive/144785545/FourBitCPU.v:19: Cannot find file containing module: 'DATASELECTOR'\nDATASELECTOR dataselector(.CLK(CLK), .C0(A), .C1(B), .C2(C), .OUT(Y), .SELA(sela), .SELB(selb));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/144785545/FourBitCPU.v:23: Cannot find file containing module: 'ALU'\nALU alu(.CLK(CLK), .REGDATA(Y), .IMMDATA(Imm), .OUT(sigma));\n^~~\n%Error: data/full_repos/permissive/144785545/FourBitCPU.v:25: Cannot find file containing module: 'REGISTER'\nREGISTER regA(.CLK(CLK), .LD(load[3]), .IN(sigma), .OUT(A)); \n^~~~~~~~\n%Error: data/full_repos/permissive/144785545/FourBitCPU.v:26: Cannot find file containing module: 'REGISTER'\nREGISTER regB(.CLK(CLK), .LD(load[2]), .IN(sigma), .OUT(B));\n^~~~~~~~\n%Error: data/full_repos/permissive/144785545/FourBitCPU.v:27: Cannot find file containing module: 'REGISTER'\nREGISTER regC(.CLK(CLK), .LD(load[1]), .IN(sigma), .OUT(C));\n^~~~~~~~\n%Error: data/full_repos/permissive/144785545/FourBitCPU.v:28: Cannot find file containing module: 'PROGCOUNTER'\nPROGCOUNTER regD(.CLK(CLK), .LD(load[0]), .IN(sigma), .OUT(D));\n^~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module FourBitCPU(
		input		CLK, RST,
		input		[7:0]	order,
		output 	reg [3:0]	OUT,
		output	reg [3:0] CNT
);


wire sela, selb;
wire [3:0] load;

DECODER dec(.CLK(CLK), .ORDER(order[7:4]), .DECODED({sela, selb, load}));

wire [3:0] A;
wire [3:0] B;
wire [3:0] C;
wire [3:0] D;
wire [3:0] Y;
DATASELECTOR dataselector(.CLK(CLK), .C0(A), .C1(B), .C2(C), .OUT(Y), .SELA(sela), .SELB(selb));

wire [3:0] sigma;
wire [3:0] Imm = order[3:0];
ALU alu(.CLK(CLK), .REGDATA(Y), .IMMDATA(Imm), .OUT(sigma));

REGISTER regA(.CLK(CLK), .LD(load[3]), .IN(sigma), .OUT(A)); 
REGISTER regB(.CLK(CLK), .LD(load[2]), .IN(sigma), .OUT(B));
REGISTER regC(.CLK(CLK), .LD(load[1]), .IN(sigma), .OUT(C));
PROGCOUNTER regD(.CLK(CLK), .LD(load[0]), .IN(sigma), .OUT(D));

always @( posedge CLK ) begin
	OUT <= C;
	CNT <= D;
end


endmodule
module FourBitCPU(
		input		CLK, RST,
		input		[7:0]	order,
		output 	reg [3:0]	OUT,
		output	reg [3:0] CNT
);



wire sela, selb;
wire [3:0] load;

DECODER dec(.CLK(CLK), .ORDER(order[7:4]), .DECODED({sela, selb, load}));

wire [3:0] A;
wire [3:0] B;
wire [3:0] C;
wire [3:0] D;
wire [3:0] Y;
DATASELECTOR dataselector(.CLK(CLK), .C0(A), .C1(B), .C2(C), .OUT(Y), .SELA(sela), .SELB(selb));

wire [3:0] sigma;
wire [3:0] Imm = order[3:0];
ALU alu(.CLK(CLK), .REGDATA(Y), .IMMDATA(Imm), .OUT(sigma));

REGISTER regA(.CLK(CLK), .LD(load[3]), .IN(sigma), .OUT(A)); 
REGISTER regB(.CLK(CLK), .LD(load[2]), .IN(sigma), .OUT(B));
REGISTER regC(.CLK(CLK), .LD(load[1]), .IN(sigma), .OUT(C));
PROGCOUNTER regD(.CLK(CLK), .LD(load[0]), .IN(sigma), .OUT(D));

always @( posedge CLK ) begin
	OUT <= C;
	CNT <= D;
end


endmodule