data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:5: Cannot find include file: st7735s.v\n`include "st7735s.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174369527/ST7735S,data/full_repos/permissive/174369527/st7735s.v\n             data/full_repos/permissive/174369527/ST7735S,data/full_repos/permissive/174369527/st7735s.v.v\n             data/full_repos/permissive/174369527/ST7735S,data/full_repos/permissive/174369527/st7735s.v.sv\n             st7735s.v\n             st7735s.v.v\n             st7735s.v.sv\n             obj_dir/st7735s.v\n             obj_dir/st7735s.v.v\n             obj_dir/st7735s.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #(c_CLOCK_PERIOD_NS/2) r_clk <= !r_clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:53: syntax error, unexpected \'@\'\n        @(~w_spi_ss);\n        ^\n%Error: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:59: syntax error, unexpected \'@\'\n            @(posedge w_spi_clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:73: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("testbench.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:74: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #(200);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #(10000);\n        ^\n%Error: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:82: syntax error, unexpected \'@\'\n        @(posedge r_clk);\n        ^\n%Error: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:86: syntax error, unexpected \'@\'\n        @(posedge r_clk);\n        ^\n%Error: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:90: syntax error, unexpected \'@\'\n        @(posedge w_waiting);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/ST7735S/st7735s_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #(10000);\n        ^\n%Error: Exiting due to 8 error(s), 5 warning(s)\n'
module st7735s_tb ();

parameter c_CLOCK_PERIOD_NS = 20;
parameter c_CLOCK_PER_SPI_HALF_BIT = 50;

reg r_clk = 1'b0;
reg r_nrst = 1'b0;
reg r_ncommand = 1'b0;
reg [7:0] r_data = 8'h00;
reg r_data_rdy = 1'b0;

wire w_waiting;
wire w_spi_clk;
wire w_spi_mosi;
wire w_spi_dc;
wire w_spi_ss;

reg v_dc = 1'b0;
reg [7:0] v_mosi = 0;
integer ii;


always
    #(c_CLOCK_PERIOD_NS/2) r_clk <= !r_clk;

st7735s 
    #(
        .c_CLOCK_PER_SPI_HALF_BIT(c_CLOCK_PER_SPI_HALF_BIT)
    )
    ST7735S_INST
    (
        .i_clk(r_clk),
        .i_nrst(r_nrst),
        .i_ncommand(r_ncommand),
        .i_data(r_data),
        .i_data_rdy(r_data_rdy),
        .o_waiting(w_waiting),
        .o_spi_clk(w_spi_clk),
        .o_spi_mosi(w_spi_mosi),
        .o_spi_dc(w_spi_dc),
        .o_spi_ss(w_spi_ss)
     );


     always
     begin
        @(~w_spi_ss);
        @(posedge w_spi_clk);
        v_dc <= w_spi_dc;
        v_mosi[7] <= w_spi_mosi;
        for (ii=6; ii>=0; ii=ii-1)
        begin
            @(posedge w_spi_clk);
            v_mosi[ii] <= w_spi_mosi;
        end

        #1;
        if (v_dc == 1'b0)
            $display("\n%0t Command 0x%0h", $time, v_mosi);
        else
            $display("%0t Argument 0x%0h", $time, v_mosi);
     end


    initial
    begin
        $dumpfile("testbench.vcd");
        $dumpvars;
        r_nrst <= 0;

        #(200);
        r_nrst <= 1;
        #(10000);


        @(posedge r_clk);
        r_ncommand <= 1'b0;
        r_data <= 8'h95;
        r_data_rdy <= 1'b1;
        @(posedge r_clk);
        r_data_rdy <= 1'b0;
        

        @(posedge w_waiting);

        #(10000);
        $display("Simulation finished");
        $finish;
    end
endmodule
module st7735s_tb ();


parameter c_CLOCK_PERIOD_NS = 20;
parameter c_CLOCK_PER_SPI_HALF_BIT = 50;

reg r_clk = 1'b0;
reg r_nrst = 1'b0;
reg r_ncommand = 1'b0;
reg [7:0] r_data = 8'h00;
reg r_data_rdy = 1'b0;

wire w_waiting;
wire w_spi_clk;
wire w_spi_mosi;
wire w_spi_dc;
wire w_spi_ss;

reg v_dc = 1'b0;
reg [7:0] v_mosi = 0;
integer ii;


always
    #(c_CLOCK_PERIOD_NS/2) r_clk <= !r_clk;

st7735s 
    #(
        .c_CLOCK_PER_SPI_HALF_BIT(c_CLOCK_PER_SPI_HALF_BIT)
    )
    ST7735S_INST
    (
        .i_clk(r_clk),
        .i_nrst(r_nrst),
        .i_ncommand(r_ncommand),
        .i_data(r_data),
        .i_data_rdy(r_data_rdy),
        .o_waiting(w_waiting),
        .o_spi_clk(w_spi_clk),
        .o_spi_mosi(w_spi_mosi),
        .o_spi_dc(w_spi_dc),
        .o_spi_ss(w_spi_ss)
     );


     always
     begin
        @(~w_spi_ss);
        @(posedge w_spi_clk);
        v_dc <= w_spi_dc;
        v_mosi[7] <= w_spi_mosi;
        for (ii=6; ii>=0; ii=ii-1)
        begin
            @(posedge w_spi_clk);
            v_mosi[ii] <= w_spi_mosi;
        end

        #1;
        if (v_dc == 1'b0)
            $display("\n%0t Command 0x%0h", $time, v_mosi);
        else
            $display("%0t Argument 0x%0h", $time, v_mosi);
     end


    initial
    begin
        $dumpfile("testbench.vcd");
        $dumpvars;
        r_nrst <= 0;

        #(200);
        r_nrst <= 1;
        #(10000);


        @(posedge r_clk);
        r_ncommand <= 1'b0;
        r_data <= 8'h95;
        r_data_rdy <= 1'b1;
        @(posedge r_clk);
        r_data_rdy <= 1'b0;
        

        @(posedge w_waiting);

        #(10000);
        $display("Simulation finished");
        $finish;
    end
endmodule