data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:15: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:17: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:48: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:59: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:62: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:64: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:67: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:70: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:72: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:79: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:82: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:87: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:96: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:99: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:104: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:113: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:116: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:121: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:130: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:133: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:138: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:148: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_CORE_STATE_MACH.sv:151: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: Exiting due to 21 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_RC4_CORE_STATE_MACH();
	localparam CLK_PERIOD = 35;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end


	reg tb_n_rst_i;
	reg tb_rc4_dfb_i;
	reg tb_rc4_start_i;
	reg tb_sarrGenerated_i;
	reg tb_valReady_i;
	reg [19:0] tb_img_width_i;
	reg [19:0] tb_img_hight_i;
	reg [19:0] tb_counterPixel_i;
	reg tb_ready_to_read_o;
	reg [1:0] tb_rc4_mode_o;
	reg tb_rc4_done_o;
	reg tb_enable_counter_pix_o;
	reg tb_clearPixels_o;
	reg tb_ready_to_write_o;
	reg tb_xor_sig_o;
	reg tb_ready_data_o;
	reg tb_genStateArr_o;
	reg tb_genVal_o;

	RC4_CORE_STATE_MACH DUT (.clk(tb_clk),.n_rst_i(tb_n_rst_i),.rc4_dfb_i(tb_rc4_dfb_i),.rc4_start_i(tb_rc4_start_i),.sarrGenerated_i(tb_sarrGenerated_i),.valReady_i(tb_valReady_i)
				,.img_width_i(tb_img_width_i),.img_hight_i(tb_img_hight_i),.counterPixel_i(tb_counterPixel_i)
				,.ready_to_read_o(tb_ready_to_read_o),.rc4_mode_o(tb_rc4_mode_o),.rc4_done_o(tb_rc4_done_o)
				,.enable_counter_pix_o(tb_enable_counter_pix_o),.clearPixels_o(tb_clearPixels_o),.ready_to_write_o(tb_ready_to_write_o)
				,.xor_sig_o(tb_xor_sig_o),.ready_data_o(tb_ready_data_o),.genStateArr_o(tb_genStateArr_o),.genVal_o(tb_genVal_o));

	initial	
	begin
	@(negedge tb_clk);
	tb_n_rst_i = 0;
	tb_rc4_dfb_i = 0;
	tb_rc4_start_i = 0;
	tb_sarrGenerated_i = 0;
	tb_valReady_i = 0;
	tb_img_width_i = 3;
	tb_img_hight_i = 3;
	tb_counterPixel_i = 0;
	tb_ready_to_read_o = 0;

	@(negedge tb_clk);
	tb_n_rst_i = 1;
	tb_rc4_start_i = 1;
	@(negedge tb_clk);
	tb_rc4_start_i = 0;
	@(negedge tb_clk);
	tb_sarrGenerated_i = 1;

	@(negedge tb_clk);
	tb_sarrGenerated_i = 0;

	@(negedge tb_clk);
	tb_rc4_dfb_i = 1;
	@(negedge tb_clk);



	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	tb_valReady_i = 1;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);

	tb_counterPixel_i = tb_counterPixel_i + 1;
	@(negedge tb_clk);

	@(negedge tb_clk);



	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	tb_valReady_i = 1;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);

	tb_counterPixel_i = tb_counterPixel_i + 1;
	@(negedge tb_clk);

	@(negedge tb_clk);
	


	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	tb_valReady_i = 1;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);

	tb_counterPixel_i = tb_counterPixel_i + 1;
	@(negedge tb_clk);

	@(negedge tb_clk);
	


	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	tb_valReady_i = 1;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);

	tb_counterPixel_i = tb_counterPixel_i + 1;
	@(negedge tb_clk);

	@(negedge tb_clk);




	@(negedge tb_clk);
	@(negedge tb_clk);
	tb_rc4_dfb_i = 1;
	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	tb_counterPixel_i = 8;
	@(negedge tb_clk);
	@(negedge tb_clk);
	@(negedge tb_clk);
	end

endmodule
module tb_RC4_CORE_STATE_MACH();

	localparam CLK_PERIOD = 35;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end


	reg tb_n_rst_i;
	reg tb_rc4_dfb_i;
	reg tb_rc4_start_i;
	reg tb_sarrGenerated_i;
	reg tb_valReady_i;
	reg [19:0] tb_img_width_i;
	reg [19:0] tb_img_hight_i;
	reg [19:0] tb_counterPixel_i;
	reg tb_ready_to_read_o;
	reg [1:0] tb_rc4_mode_o;
	reg tb_rc4_done_o;
	reg tb_enable_counter_pix_o;
	reg tb_clearPixels_o;
	reg tb_ready_to_write_o;
	reg tb_xor_sig_o;
	reg tb_ready_data_o;
	reg tb_genStateArr_o;
	reg tb_genVal_o;

	RC4_CORE_STATE_MACH DUT (.clk(tb_clk),.n_rst_i(tb_n_rst_i),.rc4_dfb_i(tb_rc4_dfb_i),.rc4_start_i(tb_rc4_start_i),.sarrGenerated_i(tb_sarrGenerated_i),.valReady_i(tb_valReady_i)
				,.img_width_i(tb_img_width_i),.img_hight_i(tb_img_hight_i),.counterPixel_i(tb_counterPixel_i)
				,.ready_to_read_o(tb_ready_to_read_o),.rc4_mode_o(tb_rc4_mode_o),.rc4_done_o(tb_rc4_done_o)
				,.enable_counter_pix_o(tb_enable_counter_pix_o),.clearPixels_o(tb_clearPixels_o),.ready_to_write_o(tb_ready_to_write_o)
				,.xor_sig_o(tb_xor_sig_o),.ready_data_o(tb_ready_data_o),.genStateArr_o(tb_genStateArr_o),.genVal_o(tb_genVal_o));

	initial	
	begin
	@(negedge tb_clk);
	tb_n_rst_i = 0;
	tb_rc4_dfb_i = 0;
	tb_rc4_start_i = 0;
	tb_sarrGenerated_i = 0;
	tb_valReady_i = 0;
	tb_img_width_i = 3;
	tb_img_hight_i = 3;
	tb_counterPixel_i = 0;
	tb_ready_to_read_o = 0;

	@(negedge tb_clk);
	tb_n_rst_i = 1;
	tb_rc4_start_i = 1;
	@(negedge tb_clk);
	tb_rc4_start_i = 0;
	@(negedge tb_clk);
	tb_sarrGenerated_i = 1;

	@(negedge tb_clk);
	tb_sarrGenerated_i = 0;

	@(negedge tb_clk);
	tb_rc4_dfb_i = 1;
	@(negedge tb_clk);



	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	tb_valReady_i = 1;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);

	tb_counterPixel_i = tb_counterPixel_i + 1;
	@(negedge tb_clk);

	@(negedge tb_clk);



	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	tb_valReady_i = 1;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);

	tb_counterPixel_i = tb_counterPixel_i + 1;
	@(negedge tb_clk);

	@(negedge tb_clk);
	


	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	tb_valReady_i = 1;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);

	tb_counterPixel_i = tb_counterPixel_i + 1;
	@(negedge tb_clk);

	@(negedge tb_clk);
	


	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	tb_valReady_i = 1;
	@(negedge tb_clk);
	tb_valReady_i = 0;

	@(negedge tb_clk);

	@(negedge tb_clk);

	tb_counterPixel_i = tb_counterPixel_i + 1;
	@(negedge tb_clk);

	@(negedge tb_clk);




	@(negedge tb_clk);
	@(negedge tb_clk);
	tb_rc4_dfb_i = 1;
	@(negedge tb_clk);
	tb_rc4_dfb_i = 0;
	tb_counterPixel_i = 8;
	@(negedge tb_clk);
	@(negedge tb_clk);
	@(negedge tb_clk);
	end

endmodule