data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:41: Cannot find include file: tartcfg.v\n`include "tartcfg.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench,data/full_repos/permissive/20430511/tartcfg.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench,data/full_repos/permissive/20430511/tartcfg.v.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench,data/full_repos/permissive/20430511/tartcfg.v.sv\n             tartcfg.v\n             tartcfg.v.v\n             tartcfg.v.sv\n             obj_dir/tartcfg.v\n             obj_dir/tartcfg.v.v\n             obj_dir/tartcfg.v.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:384: Cannot find include file: ../include/tart_pairs.v\n`include "../include/tart_pairs.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:64: Define or directive not defined: \'`NUM_ANTENNA\'\n   parameter AXNUM = `NUM_ANTENNA;  \n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:64: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter AXNUM = `NUM_ANTENNA;  \n                                 ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:66: Define or directive not defined: \'`ACCUM_BITS\'\n   parameter ACCUM = `ACCUM_BITS;   \n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter ACCUM = `ACCUM_BITS;   \n                                ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:69: Define or directive not defined: \'`TMUX_RATE\'\n   parameter TRATE = `TMUX_RATE;    \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:69: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter TRATE = `TMUX_RATE;    \n                               ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:70: Define or directive not defined: \'`TMUX_BITS\'\n   parameter TBITS = `TMUX_BITS;    \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:70: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter TBITS = `TMUX_BITS;    \n                               ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:80: Define or directive not defined: \'`BANK_BITS\'\n   parameter XBITS = `BANK_BITS;  \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter XBITS = `BANK_BITS;  \n                               ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:93: Define or directive not defined: \'`READ_BITS\'\n   parameter FBITS = `READ_BITS;  \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:93: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter FBITS = `READ_BITS;  \n                               ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:101: Define or directive not defined: \'`RANDOM_DATA\'\n   parameter RNG   = `RANDOM_DATA;  \n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:101: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter RNG   = `RANDOM_DATA;  \n                                 ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:102: Define or directive not defined: \'`DELAY\'\n   parameter DELAY = `DELAY;        \n                     ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:102: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter DELAY = `DELAY;        \n                           ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:144: Define or directive not defined: \'`CLK_X\'\n   always #`CLK_X  clk_x <= ~clk_x;\n           ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:144: syntax error, unexpected <=\n   always #`CLK_X  clk_x <= ~clk_x;\n                         ^~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n   always #`CLK_X  clk_x <= ~clk_x;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:145: Define or directive not defined: \'`CLK_B\'\n   always #`CLK_B  b_clk <= ~b_clk;\n           ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:145: syntax error, unexpected <=\n   always #`CLK_B  b_clk <= ~b_clk;\n                         ^~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n   always #`CLK_B  b_clk <= ~b_clk;\n          ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:154: Unsupported or unknown PLI call: $dumpfile\n         $dumpfile ("vcd/block_tb.vcd");\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:155: Unsupported or unknown PLI call: $dumpvars\n         $dumpvars;\n         ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n      #20 $display("\\n%12t: Issuing RESET.\\n", $time);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n      #13 rst <= 1; #40 rst <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n      #13 rst <= 1; #40 rst <= 0;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n      #40 blocksize <= BSIZE; enable <= 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n      while (!switch) #10; while (switch) #10;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n      while (!switch) #10; while (switch) #10;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n      #10 $display("\\n%12t: Fetching back visibilities (bank 0)", $time);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n      #10 fetch <= 1\'b1; #10 while (fetch) #10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n      #10 fetch <= 1\'b1; #10 while (fetch) #10;\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n      #10 fetch <= 1\'b1; #10 while (fetch) #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n      while (!switch) #10; while (switch) #10;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n      while (!switch) #10; while (switch) #10;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:199: Unsupported: Ignoring delay on this delayed statement.\n      #10 enable <= 1\'b0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:202: Unsupported: Ignoring delay on this delayed statement.\n      #10 $display("\\n%12t: Fetching back visibilities (bank 1)", $time);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n      #10 fetch <= 1\'b1; #10 while (fetch) #10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n      #10 fetch <= 1\'b1; #10 while (fetch) #10;\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n      #10 fetch <= 1\'b1; #10 while (fetch) #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n      #80 $display("\\n%12t: Simulation finished:", $time);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/tart_block_tb.v:261: Unsupported: Ignoring delay on this delayed statement.\n      #LIMIT $display ("\\nTIMEOUT!\\n");\n      ^\n%Error: Exiting due to 24 error(s), 21 warning(s)\n'
module tart_block_tb;







   parameter AXNUM = `NUM_ANTENNA;
   parameter NSB   = AXNUM-1;
   parameter ACCUM = `ACCUM_BITS;
   parameter BLOCK = ACCUM;
   parameter MSB   = BLOCK-1;
   parameter TRATE = `TMUX_RATE;
   parameter TBITS = `TMUX_BITS;
   parameter TSB   = TBITS-1;


   parameter RSIZE = TRATE*2;
   parameter RBITS = TBITS+1;
   parameter RSB   = RBITS-1;


   parameter BREAD = NREAD << 2;
   parameter XBITS = `BANK_BITS;
   parameter XSB   = XBITS-1;
   parameter BANKS = 1 << XBITS;


   parameter CBITS = XBITS+FBITS;
   parameter CSB   = CBITS-1;


   parameter ABITS = 2+XBITS+RBITS;
   parameter ASB   = ABITS-1;


   parameter FBITS = `READ_BITS;
   parameter FSB   = FBITS-1;
   parameter NREAD = 96;
   parameter COUNT = 6;
   parameter BSIZE = (1 << COUNT) - 1;
   parameter READS = 2;


   parameter RNG   = `RANDOM_DATA;
   parameter DELAY = `DELAY;








   wire [NSB:0] antenna;
   reg          enable = 1'b0;
   reg [NSB:0]  data [0:255];


   reg          clk_x = 1'b1, b_clk = 1'b1, rst = 1'b0;
   wire         b_rst = rst;         


   wire [NSB:0] re, im;
   wire         valid, strobe, frame;


   reg [MSB:0]  blocksize;
   wire [XSB:0] bank;
   wire         swap_x, switch;


   wire         b_cyc, b_stb, b_we, b_bst, b_ack, b_wat, b_err;
   wire [RSB:0] b_adr;
   wire [MSB:0] b_dat, b_vis, b_viz;


   reg          fetch = 1'b0, read = 1'b0;
   wire         done;








   always #`CLK_X  clk_x <= ~clk_x;
   always #`CLK_B  b_clk <= ~b_clk;




   integer      num = 0;
   integer      ptr = 0;
   initial begin : SIM_BLOCK
      if (COUNT < 7) begin
         $dumpfile ("vcd/block_tb.vcd");
         $dumpvars;
      end


      $display("\n%12t: TART correlator settings:", $time);
      $display(  "%12t:  Simulated correlator settings:", $time);
      $display(  "%12t:   Accumulator bit-width:   \t\t%4d", $time, ACCUM);
      $display(  "%12t:   Correlator bus data-width:       \t%4d", $time, ACCUM);
      $display(  "%12t:   Correlator bus address-width:    \t%4d", $time, ABITS);
      $display(  "%12t:   Number of correlator banks:      \t%4d", $time, BANKS);
      $display(  "%12t:   Number of counter bits:          \t%4d", $time, COUNT);
      $display(  "%12t:   Max count value (samples/bank):  \t%4d", $time, BSIZE);
      $display(  "%12t:   Data prefetch block-size (words):\t%4d", $time, RSIZE);


      $display("\n%12t: Generating fake antenna data:", $time);
      if (RNG)
        $display("%12t:  (Data is random values)", $time);
      else
        $display("%12t:  (Data is just increasing counter values)", $time);
      for (ptr = 0; ptr < 256; ptr = ptr+1) begin
         if (RNG) data[ptr] <= $random;
         else     data[ptr] <= ptr;
      end


      #20 $display("\n%12t: Issuing RESET.\n", $time);
      #13 rst <= 1; #40 rst <= 0;


      $display("\n%12t: Setting block-size & beginning correlation (bank 0)", $time);
      #40 blocksize <= BSIZE; enable <= 1'b1;


      while (!switch) #10; while (switch) #10;
      $display("%12t: Switching banks (bank 1)", $time);


      #10 $display("\n%12t: Fetching back visibilities (bank 0)", $time);
      #10 fetch <= 1'b1; #10 while (fetch) #10;


      while (!switch) #10; while (switch) #10;
      $display("\n%12t: Stopping data-correlation (bank 1)", $time);
      #10 enable <= 1'b0;


      #10 $display("\n%12t: Fetching back visibilities (bank 1)", $time);
      #10 fetch <= 1'b1; #10 while (fetch) #10;


      #80 $display("\n%12t: Simulation finished:", $time);
      $finish;
   end








   reg [TSB:0]  cnt = 0;
   wire [TSB:0] next_cnt = wrap_cnt ? 0 : cnt + 1 ;
   wire         wrap_cnt = cnt == TRATE-1;
   integer      rd_adr = 0;

`ifdef CONST_DATA
   assign antenna = `CONST_WORD;
`else
   assign antenna = RNG ? mfsr_reg : data[rd_adr[7:0]];
`endif

   always @(posedge clk_x)
     if (rst) cnt <= #DELAY 0;
     else     cnt <= #DELAY enable ? next_cnt : cnt;

   always @(posedge clk_x)
     if (rst) rd_adr <= #DELAY 0;
     else     rd_adr <= #DELAY enable && wrap_cnt ? rd_adr + 1 : rd_adr;




   wire [31:0]     mfsr_new;
   reg [31:0]      mfsr_reg = RNG;

   always @(posedge clk_x)
     if (rst) mfsr_reg <= #DELAY RNG;
     else     mfsr_reg <= #DELAY enable && wrap_cnt ? mfsr_new : mfsr_reg;



   mfsr32 MFSR32 (.count_i(mfsr_reg), .count_o(mfsr_new));








   parameter LIMIT = 1000 + (1 << COUNT) * 320;

   initial begin : SIM_FAILED
      $display("%12t: Simulation TIMEOUT limit:\t%12d", $time, LIMIT);
      #LIMIT $display ("\nTIMEOUT!\n");
      $finish;
   end







   wire [FBITS:0] f_nxt = f_adr + 1;
   reg [MSB:0]    fetched [0:NREAD-1];
   reg [FSB:0]    f_adr = {FBITS{1'b0}};


   always @(posedge b_clk) begin
      if (switch)
        $display("%12t: New block available.", $time);
   end

`ifdef  __USE_COLUMN_DISPLAY


   always @(posedge b_clk) begin
      if (b_cyc && !b_we && b_ack)
        $display("%12t: Vis = %08x (d: %8d)", $time, b_viz, b_viz);
   end
`else




   always @(posedge b_clk)
     if (rst || !fetch) begin
        f_adr <= #DELAY {FBITS{1'b0}};
     end
     else if (b_cyc && !b_we && b_ack) begin
        f_adr <= #DELAY f_nxt;
        fetched[f_adr] <= #DELAY b_viz;
     end



   always @(negedge fetch)
     if (f_adr > 0) begin
        $display("\n%12t: Fetched visibilities (num = %d):", $time, f_adr);
        for (ptr = 0; ptr < NREAD; ptr = ptr + TRATE) begin
           $write("\t");
           for (num = 0; num < TRATE; num = num + 1)
 `ifdef __USE_DECIMAL_DISPLAY
             $write("%7d ", fetched[ptr + num]);
 `else
             $write("%06x ", fetched[ptr + num]);
 `endif
           $write("\n");
        end
     end
`endif







   wire [XBITS:0] n_blk = c_blk + 1;
   wire [2:0]     n_cor = c_cor + 1;
   reg [XSB:0]    c_blk = {XBITS{1'b0}};
   reg [1:0]      c_cor = 2'b00;
   wire [ASB:0]   c_adr = {c_blk, b_adr[RSB:1], c_cor, b_adr[0]};

   assign b_viz = fetch ? b_vis : {ACCUM{1'bz}};

   always @(posedge b_clk)
     if (b_rst)
       {fetch, read, c_blk, c_cor} <= #DELAY {XBITS+4{1'b0}};
     else if (fetch && done && c_cor == 2'b11)
       {fetch, c_blk} <= #DELAY {1'b0, n_blk[XSB:0]};
     else if (fetch && done)
       {read, c_cor} <= #DELAY {1'b1, n_cor[1:0]};
     else if (fetch && !b_cyc && !read)
       {read, c_cor} <= #DELAY 3'b100;
     else
       read <= #DELAY 1'b0;





   fake_hilbert #( .WIDTH(AXNUM) ) HILB0
     (  .clk(clk_x),
        .rst(rst),
        .en(enable),
        .d(antenna),
        .valid(valid),
        .strobe(strobe),
        .frame(frame),
        .re(re),
        .im(im)
        );





   tart_bank_switch #( .COUNT(BLOCK) ) SW0
     ( .clk_x(clk_x),
       .clk_i(b_clk),
       .rst_i(rst),
       .ce_i (valid),
       .frame_i(frame),
       .bcount_i(blocksize),
       .swap_x(swap_x),
       .swap_o(switch)
       );








`include "../include/tart_pairs.v"
`ifdef  __TEST_DSP_BLOCK
   assign b_ack = dsp_ack;
   assign b_vis = dsp_vis;
   assign bank  = dsp_bank;
`else
   assign b_ack = sdp_ack;
   assign b_vis = sdp_vis;
   assign bank  = sdp_bank;
`endif

   wire           dsp_ack;
   wire [MSB:0]   dsp_vis;
   wire [XSB:0]   dsp_bank;

   correlator_block_DSP
     #(  .ACCUM (BLOCK),
         .PAIRS0(PAIRS00_00),
         .PAIRS1(PAIRS00_01),
         .PAIRS2(PAIRS00_02),
         .PAIRS3(PAIRS00_03),
         .DELAY (DELAY)
         ) DSPB
       ( .clk_x(clk_x),
         .rst(rst),

         .clk_i(b_clk),
         .cyc_i(b_cyc),
         .stb_i(b_stb),
         .we_i (1'b0),
         .bst_i(b_bst),
         .ack_o(dsp_ack),
         .adr_i(c_adr),
         .dat_i(b_dat),
         .dat_o(dsp_vis),

         .sw_i(swap_x),
         .en_i(valid),
         .re_i(re),
         .im_i(im),

         .bank_o(dsp_bank)
         );

   wire           sdp_ack;
   wire [MSB:0]   sdp_vis;
   wire [XSB:0]   sdp_bank;

   correlator_block_SDP
     #(  .ACCUM (BLOCK),
         .PAIRS0(PAIRS00_00),
         .PAIRS1(PAIRS00_01),
         .PAIRS2(PAIRS00_02),
         .PAIRS3(PAIRS00_03),
         .DELAY (DELAY)
         ) SDPB
       ( .clk_x(clk_x),
         .rst(rst),

         .clk_i(b_clk),
         .cyc_i(b_cyc),
         .stb_i(b_stb),
         .we_i (1'b0),
         .bst_i(b_bst),
         .ack_o(sdp_ack),
         .adr_i(c_adr),
         .dat_i(b_dat),
         .dat_o(sdp_vis),

         .sw_i(swap_x),
         .en_i(valid),
         .re_i(re),
         .im_i(im),

         .bank_o(sdp_bank)
         );





   assign b_we  = 1'b0;
   assign b_wat = 1'b0;
   assign b_err = 1'b0;

   wb_get_block
     #(.BSIZE(RSIZE), .BBITS(RBITS), .DELAY(DELAY)
       ) FETCH0
       ( .clk_i(b_clk),
         .rst_i(b_rst),
         .cyc_o(b_cyc),
         .stb_o(b_stb),
         .we_o (b_we),
         .bst_o(b_bst),
         .ack_i(b_ack),
         .wat_i(b_wat),
         .err_i(b_err),
         .adr_o(b_adr),

         .read_i(read),
         .done_o(done)
         );


endmodule
module tart_block_tb;








   parameter AXNUM = `NUM_ANTENNA;
   parameter NSB   = AXNUM-1;
   parameter ACCUM = `ACCUM_BITS;
   parameter BLOCK = ACCUM;
   parameter MSB   = BLOCK-1;
   parameter TRATE = `TMUX_RATE;
   parameter TBITS = `TMUX_BITS;
   parameter TSB   = TBITS-1;


   parameter RSIZE = TRATE*2;
   parameter RBITS = TBITS+1;
   parameter RSB   = RBITS-1;


   parameter BREAD = NREAD << 2;
   parameter XBITS = `BANK_BITS;
   parameter XSB   = XBITS-1;
   parameter BANKS = 1 << XBITS;


   parameter CBITS = XBITS+FBITS;
   parameter CSB   = CBITS-1;


   parameter ABITS = 2+XBITS+RBITS;
   parameter ASB   = ABITS-1;


   parameter FBITS = `READ_BITS;
   parameter FSB   = FBITS-1;
   parameter NREAD = 96;
   parameter COUNT = 6;
   parameter BSIZE = (1 << COUNT) - 1;
   parameter READS = 2;


   parameter RNG   = `RANDOM_DATA;
   parameter DELAY = `DELAY;








   wire [NSB:0] antenna;
   reg          enable = 1'b0;
   reg [NSB:0]  data [0:255];


   reg          clk_x = 1'b1, b_clk = 1'b1, rst = 1'b0;
   wire         b_rst = rst;         


   wire [NSB:0] re, im;
   wire         valid, strobe, frame;


   reg [MSB:0]  blocksize;
   wire [XSB:0] bank;
   wire         swap_x, switch;


   wire         b_cyc, b_stb, b_we, b_bst, b_ack, b_wat, b_err;
   wire [RSB:0] b_adr;
   wire [MSB:0] b_dat, b_vis, b_viz;


   reg          fetch = 1'b0, read = 1'b0;
   wire         done;








   always #`CLK_X  clk_x <= ~clk_x;
   always #`CLK_B  b_clk <= ~b_clk;




   integer      num = 0;
   integer      ptr = 0;
   initial begin : SIM_BLOCK
      if (COUNT < 7) begin
         $dumpfile ("vcd/block_tb.vcd");
         $dumpvars;
      end


      $display("\n%12t: TART correlator settings:", $time);
      $display(  "%12t:  Simulated correlator settings:", $time);
      $display(  "%12t:   Accumulator bit-width:   \t\t%4d", $time, ACCUM);
      $display(  "%12t:   Correlator bus data-width:       \t%4d", $time, ACCUM);
      $display(  "%12t:   Correlator bus address-width:    \t%4d", $time, ABITS);
      $display(  "%12t:   Number of correlator banks:      \t%4d", $time, BANKS);
      $display(  "%12t:   Number of counter bits:          \t%4d", $time, COUNT);
      $display(  "%12t:   Max count value (samples/bank):  \t%4d", $time, BSIZE);
      $display(  "%12t:   Data prefetch block-size (words):\t%4d", $time, RSIZE);


      $display("\n%12t: Generating fake antenna data:", $time);
      if (RNG)
        $display("%12t:  (Data is random values)", $time);
      else
        $display("%12t:  (Data is just increasing counter values)", $time);
      for (ptr = 0; ptr < 256; ptr = ptr+1) begin
         if (RNG) data[ptr] <= $random;
         else     data[ptr] <= ptr;
      end


      #20 $display("\n%12t: Issuing RESET.\n", $time);
      #13 rst <= 1; #40 rst <= 0;


      $display("\n%12t: Setting block-size & beginning correlation (bank 0)", $time);
      #40 blocksize <= BSIZE; enable <= 1'b1;


      while (!switch) #10; while (switch) #10;
      $display("%12t: Switching banks (bank 1)", $time);


      #10 $display("\n%12t: Fetching back visibilities (bank 0)", $time);
      #10 fetch <= 1'b1; #10 while (fetch) #10;


      while (!switch) #10; while (switch) #10;
      $display("\n%12t: Stopping data-correlation (bank 1)", $time);
      #10 enable <= 1'b0;


      #10 $display("\n%12t: Fetching back visibilities (bank 1)", $time);
      #10 fetch <= 1'b1; #10 while (fetch) #10;


      #80 $display("\n%12t: Simulation finished:", $time);
      $finish;
   end








   reg [TSB:0]  cnt = 0;
   wire [TSB:0] next_cnt = wrap_cnt ? 0 : cnt + 1 ;
   wire         wrap_cnt = cnt == TRATE-1;
   integer      rd_adr = 0;

`ifdef CONST_DATA
   assign antenna = `CONST_WORD;
`else
   assign antenna = RNG ? mfsr_reg : data[rd_adr[7:0]];
`endif

   always @(posedge clk_x)
     if (rst) cnt <= #DELAY 0;
     else     cnt <= #DELAY enable ? next_cnt : cnt;

   always @(posedge clk_x)
     if (rst) rd_adr <= #DELAY 0;
     else     rd_adr <= #DELAY enable && wrap_cnt ? rd_adr + 1 : rd_adr;




   wire [31:0]     mfsr_new;
   reg [31:0]      mfsr_reg = RNG;

   always @(posedge clk_x)
     if (rst) mfsr_reg <= #DELAY RNG;
     else     mfsr_reg <= #DELAY enable && wrap_cnt ? mfsr_new : mfsr_reg;



   mfsr32 MFSR32 (.count_i(mfsr_reg), .count_o(mfsr_new));








   parameter LIMIT = 1000 + (1 << COUNT) * 320;

   initial begin : SIM_FAILED
      $display("%12t: Simulation TIMEOUT limit:\t%12d", $time, LIMIT);
      #LIMIT $display ("\nTIMEOUT!\n");
      $finish;
   end







   wire [FBITS:0] f_nxt = f_adr + 1;
   reg [MSB:0]    fetched [0:NREAD-1];
   reg [FSB:0]    f_adr = {FBITS{1'b0}};


   always @(posedge b_clk) begin
      if (switch)
        $display("%12t: New block available.", $time);
   end

`ifdef  __USE_COLUMN_DISPLAY


   always @(posedge b_clk) begin
      if (b_cyc && !b_we && b_ack)
        $display("%12t: Vis = %08x (d: %8d)", $time, b_viz, b_viz);
   end
`else




   always @(posedge b_clk)
     if (rst || !fetch) begin
        f_adr <= #DELAY {FBITS{1'b0}};
     end
     else if (b_cyc && !b_we && b_ack) begin
        f_adr <= #DELAY f_nxt;
        fetched[f_adr] <= #DELAY b_viz;
     end



   always @(negedge fetch)
     if (f_adr > 0) begin
        $display("\n%12t: Fetched visibilities (num = %d):", $time, f_adr);
        for (ptr = 0; ptr < NREAD; ptr = ptr + TRATE) begin
           $write("\t");
           for (num = 0; num < TRATE; num = num + 1)
 `ifdef __USE_DECIMAL_DISPLAY
             $write("%7d ", fetched[ptr + num]);
 `else
             $write("%06x ", fetched[ptr + num]);
 `endif
           $write("\n");
        end
     end
`endif







   wire [XBITS:0] n_blk = c_blk + 1;
   wire [2:0]     n_cor = c_cor + 1;
   reg [XSB:0]    c_blk = {XBITS{1'b0}};
   reg [1:0]      c_cor = 2'b00;
   wire [ASB:0]   c_adr = {c_blk, b_adr[RSB:1], c_cor, b_adr[0]};

   assign b_viz = fetch ? b_vis : {ACCUM{1'bz}};

   always @(posedge b_clk)
     if (b_rst)
       {fetch, read, c_blk, c_cor} <= #DELAY {XBITS+4{1'b0}};
     else if (fetch && done && c_cor == 2'b11)
       {fetch, c_blk} <= #DELAY {1'b0, n_blk[XSB:0]};
     else if (fetch && done)
       {read, c_cor} <= #DELAY {1'b1, n_cor[1:0]};
     else if (fetch && !b_cyc && !read)
       {read, c_cor} <= #DELAY 3'b100;
     else
       read <= #DELAY 1'b0;





   fake_hilbert #( .WIDTH(AXNUM) ) HILB0
     (  .clk(clk_x),
        .rst(rst),
        .en(enable),
        .d(antenna),
        .valid(valid),
        .strobe(strobe),
        .frame(frame),
        .re(re),
        .im(im)
        );





   tart_bank_switch #( .COUNT(BLOCK) ) SW0
     ( .clk_x(clk_x),
       .clk_i(b_clk),
       .rst_i(rst),
       .ce_i (valid),
       .frame_i(frame),
       .bcount_i(blocksize),
       .swap_x(swap_x),
       .swap_o(switch)
       );








`include "../include/tart_pairs.v"
`ifdef  __TEST_DSP_BLOCK
   assign b_ack = dsp_ack;
   assign b_vis = dsp_vis;
   assign bank  = dsp_bank;
`else
   assign b_ack = sdp_ack;
   assign b_vis = sdp_vis;
   assign bank  = sdp_bank;
`endif

   wire           dsp_ack;
   wire [MSB:0]   dsp_vis;
   wire [XSB:0]   dsp_bank;

   correlator_block_DSP
     #(  .ACCUM (BLOCK),
         .PAIRS0(PAIRS00_00),
         .PAIRS1(PAIRS00_01),
         .PAIRS2(PAIRS00_02),
         .PAIRS3(PAIRS00_03),
         .DELAY (DELAY)
         ) DSPB
       ( .clk_x(clk_x),
         .rst(rst),

         .clk_i(b_clk),
         .cyc_i(b_cyc),
         .stb_i(b_stb),
         .we_i (1'b0),
         .bst_i(b_bst),
         .ack_o(dsp_ack),
         .adr_i(c_adr),
         .dat_i(b_dat),
         .dat_o(dsp_vis),

         .sw_i(swap_x),
         .en_i(valid),
         .re_i(re),
         .im_i(im),

         .bank_o(dsp_bank)
         );

   wire           sdp_ack;
   wire [MSB:0]   sdp_vis;
   wire [XSB:0]   sdp_bank;

   correlator_block_SDP
     #(  .ACCUM (BLOCK),
         .PAIRS0(PAIRS00_00),
         .PAIRS1(PAIRS00_01),
         .PAIRS2(PAIRS00_02),
         .PAIRS3(PAIRS00_03),
         .DELAY (DELAY)
         ) SDPB
       ( .clk_x(clk_x),
         .rst(rst),

         .clk_i(b_clk),
         .cyc_i(b_cyc),
         .stb_i(b_stb),
         .we_i (1'b0),
         .bst_i(b_bst),
         .ack_o(sdp_ack),
         .adr_i(c_adr),
         .dat_i(b_dat),
         .dat_o(sdp_vis),

         .sw_i(swap_x),
         .en_i(valid),
         .re_i(re),
         .im_i(im),

         .bank_o(sdp_bank)
         );





   assign b_we  = 1'b0;
   assign b_wat = 1'b0;
   assign b_err = 1'b0;

   wb_get_block
     #(.BSIZE(RSIZE), .BBITS(RBITS), .DELAY(DELAY)
       ) FETCH0
       ( .clk_i(b_clk),
         .rst_i(b_rst),
         .cyc_o(b_cyc),
         .stb_o(b_stb),
         .we_o (b_we),
         .bst_o(b_bst),
         .ack_i(b_ack),
         .wat_i(b_wat),
         .err_i(b_err),
         .adr_o(b_adr),

         .read_i(read),
         .done_o(done)
         );


endmodule