data/full_repos/permissive/149070951/examples/user-test/kitt.v
1: b'%Error: data/full_repos/permissive/149070951/examples/user-test/kitt.v:9: Cannot find file containing module: \'prescaler\'\nprescaler\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149070951/examples/user-test,data/full_repos/permissive/149070951/prescaler\n             data/full_repos/permissive/149070951/examples/user-test,data/full_repos/permissive/149070951/prescaler.v\n             data/full_repos/permissive/149070951/examples/user-test,data/full_repos/permissive/149070951/prescaler.sv\n             prescaler\n             prescaler.v\n             prescaler.sv\n             obj_dir/prescaler\n             obj_dir/prescaler.v\n             obj_dir/prescaler.sv\n%Warning-WIDTH: data/full_repos/permissive/149070951/examples/user-test/kitt.v:30: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s XOR generates 4 bits.\n                                                                                 : ... In instance kitt\nassign pos2 = pos ^ {a,a,a,a};\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/149070951/examples/user-test/kitt.v:32: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'in0\' generates 1 bits.\n                                                                                 : ... In instance kitt\nassign ledb = in0 << pos2;\n                  ^~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module kitt (input wire clk,
             output wire [7:0] ledb);

wire clk_kitt;


prescaler
       #(.N(19))
      press1 (
         .clk_in(clk),
         .ena(1'b1),
         .clk_out(clk_kitt)
         );


reg [3:0] pos = 0;

always @ (posedge clk_kitt ) begin
    pos <= pos + 1;
end


wire in0 = 1'b1;

wire a = pos[3];
wire [2:0] pos2;

assign pos2 = pos ^ {a,a,a,a};

assign ledb = in0 << pos2;


endmodule
module kitt (input wire clk,
             output wire [7:0] ledb);


wire clk_kitt;


prescaler
       #(.N(19))
      press1 (
         .clk_in(clk),
         .ena(1'b1),
         .clk_out(clk_kitt)
         );


reg [3:0] pos = 0;

always @ (posedge clk_kitt ) begin
    pos <= pos + 1;
end


wire in0 = 1'b1;

wire a = pos[3];
wire [2:0] pos2;

assign pos2 = pos ^ {a,a,a,a};

assign ledb = in0 << pos2;


endmodule