data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/extmem/rvmemspv.v
1: b"%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/extmem/rvmemspv.v:28: Cannot find file containing module: 'axi_bram'\naxi_bram axi_bram (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/extmem,data/full_repos/permissive/125344718/axi_bram\n             data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/extmem,data/full_repos/permissive/125344718/axi_bram.v\n             data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/extmem,data/full_repos/permissive/125344718/axi_bram.sv\n             axi_bram\n             axi_bram.v\n             axi_bram.sv\n             obj_dir/axi_bram\n             obj_dir/axi_bram.v\n             obj_dir/axi_bram.sv\n%Error: Exiting due to 1 error(s)\n"
module rvmemspv #( 

    parameter MEM_ADDR_WIDTH = 32,
    parameter MEM_DATA_WIDTH = 32,
    parameter MASK_WIDTH = MEM_DATA_WIDTH/8


)(
    input waen,
    input wden,
    input [MEM_ADDR_WIDTH-1:0] waddr,
    input [MEM_DATA_WIDTH-1:0] wdata,
    input [MASK_WIDTH-1:0] wmask,
    output wardy,
    output wdrdy,
    output wbvld,
    input raen,
    input rden,
    input [MEM_ADDR_WIDTH-1:0] raddr,
    output [MEM_DATA_WIDTH-1:0] rdata,
    output rardy,
    output rdrdy,
    
    input reset,
    input clock
);

axi_bram axi_bram (
    .s_axi_aclk(clock),
    .s_axi_aresetn(~reset),
    .s_axi_awaddr(waddr[12:0]),
    .s_axi_awlen(8'h00),
    .s_axi_awsize(3'h2),
    .s_axi_awburst(2'h0),
    .s_axi_awlock(1'b0),
    .s_axi_awcache(4'h0),
    .s_axi_awprot(3'h0),
    .s_axi_awvalid(waen),
    .s_axi_awready(wardy),
    .s_axi_wdata(wdata),
    .s_axi_wstrb(wmask),
    .s_axi_wlast(wden),
    .s_axi_wvalid(wden),
    .s_axi_wready(wdrdy),
    .s_axi_bresp(),
    .s_axi_bvalid(wbvld),
    .s_axi_bready(1'b1),
    .s_axi_araddr(raddr[12:0]),
    .s_axi_arlen(8'h00),
    .s_axi_arsize(3'h2),
    .s_axi_arburst(2'h0),
    .s_axi_arlock(1'b0),
    .s_axi_arcache(4'h0),
    .s_axi_arprot(3'h0),
    .s_axi_arvalid(raen),
    .s_axi_arready(rardy),
    .s_axi_rdata(rdata),
    .s_axi_rresp(),
    .s_axi_rlast(),
    .s_axi_rvalid(rdrdy),
    .s_axi_rready(1'b1)
);

endmodule
module rvmemspv #( 

    parameter MEM_ADDR_WIDTH = 32,
    parameter MEM_DATA_WIDTH = 32,
    parameter MASK_WIDTH = MEM_DATA_WIDTH/8


)(
    input waen,
    input wden,
    input [MEM_ADDR_WIDTH-1:0] waddr,
    input [MEM_DATA_WIDTH-1:0] wdata,
    input [MASK_WIDTH-1:0] wmask,
    output wardy,
    output wdrdy,
    output wbvld,
    input raen,
    input rden,
    input [MEM_ADDR_WIDTH-1:0] raddr,
    output [MEM_DATA_WIDTH-1:0] rdata,
    output rardy,
    output rdrdy,
    
    input reset,
    input clock
);


axi_bram axi_bram (
    .s_axi_aclk(clock),
    .s_axi_aresetn(~reset),
    .s_axi_awaddr(waddr[12:0]),
    .s_axi_awlen(8'h00),
    .s_axi_awsize(3'h2),
    .s_axi_awburst(2'h0),
    .s_axi_awlock(1'b0),
    .s_axi_awcache(4'h0),
    .s_axi_awprot(3'h0),
    .s_axi_awvalid(waen),
    .s_axi_awready(wardy),
    .s_axi_wdata(wdata),
    .s_axi_wstrb(wmask),
    .s_axi_wlast(wden),
    .s_axi_wvalid(wden),
    .s_axi_wready(wdrdy),
    .s_axi_bresp(),
    .s_axi_bvalid(wbvld),
    .s_axi_bready(1'b1),
    .s_axi_araddr(raddr[12:0]),
    .s_axi_arlen(8'h00),
    .s_axi_arsize(3'h2),
    .s_axi_arburst(2'h0),
    .s_axi_arlock(1'b0),
    .s_axi_arcache(4'h0),
    .s_axi_arprot(3'h0),
    .s_axi_arvalid(raen),
    .s_axi_arready(rardy),
    .s_axi_rdata(rdata),
    .s_axi_rresp(),
    .s_axi_rlast(),
    .s_axi_rvalid(rdrdy),
    .s_axi_rready(1'b1)
);

endmodule