data/full_repos/permissive/143278/ivltests/pr848.v
 line:8: before: "forever"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr848.v:8: Unsupported: Ignoring delay on this delayed statement.\n      #3 forever #10 clk=~clk;\n                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr848.v:8: Unsupported: Ignoring delay on this delayed statement.\n      #3 forever #10 clk=~clk;\n      ^\n%Warning-INFINITELOOP: data/full_repos/permissive/143278/ivltests/pr848.v:8: Infinite loop (condition always true)\n                                                                           : ... In instance err\n      #3 forever #10 clk=~clk;\n         ^~~~~~~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module err ();

reg clk;
initial begin
      clk = 1'b1;
      #3 forever #10 clk=~clk;
end

reg [31:0] mem [10:0];

wire [32:0] kuku = {1'b0,mem[3]};

always @(posedge clk) begin
   if (kuku !== 33'h0_xx_xx_xx_xx) begin
      $display("FAILED -- kuku has wrong value %h", kuku);
      $finish;
   end

   $display("PASSED");
   $finish;
end

endmodule
module err ();


reg clk;
initial begin
      clk = 1'b1;
      #3 forever #10 clk=~clk;
end

reg [31:0] mem [10:0];

wire [32:0] kuku = {1'b0,mem[3]};

always @(posedge clk) begin
   if (kuku !== 33'h0_xx_xx_xx_xx) begin
      $display("FAILED -- kuku has wrong value %h", kuku);
      $finish;
   end

   $display("PASSED");
   $finish;
end

endmodule