data/full_repos/permissive/143278/vhdl_tests/pr2391405.v
data/verilator_xmls/a15ca4be-e820-4f8a-b5ed-08d819d3c477.xml
module bar

  (

  result,

  clk, enable, reset
  );


  input                 clk;
  input                 enable;

  input                 reset;

  output                result;














  reg                   result;








  always @ (posedge clk) begin
    if (reset) begin
      result <= 1'd0;
    end else begin
      result <= enable;
    end
  end



endmodule
module bar

  (

  result,

  clk, enable, reset
  );



  input                 clk;
  input                 enable;

  input                 reset;

  output                result;














  reg                   result;








  always @ (posedge clk) begin
    if (reset) begin
      result <= 1'd0;
    end else begin
      result <= enable;
    end
  end



endmodule