data/full_repos/permissive/109846502/Calkko.v
1: b'%Error: data/full_repos/permissive/109846502/Calkko.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/Calkko.v:34: Define or directive not defined: \'`S_OBL\'\nassign set = ST == `S_OBL;\n                   ^~~~~~\n%Error: data/full_repos/permissive/109846502/Calkko.v:34: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign set = ST == `S_OBL;\n                         ^\n%Error: data/full_repos/permissive/109846502/Calkko.v:48: Define or directive not defined: \'`SL_ADD\'\n   `SL_ADD:\n   ^~~~~~~\n%Error: data/full_repos/permissive/109846502/Calkko.v:48: syntax error, unexpected \':\', expecting endcase\n   `SL_ADD:\n          ^\n%Error: data/full_repos/permissive/109846502/Calkko.v:50: Define or directive not defined: \'`SL_SUB\'\n   `SL_SUB:\n   ^~~~~~~\n%Error: data/full_repos/permissive/109846502/Calkko.v:52: Define or directive not defined: \'`SL_XOR\'\n   `SL_XOR:\n   ^~~~~~~\n%Error: data/full_repos/permissive/109846502/Calkko.v:54: Define or directive not defined: \'`SL_AND\'\n   `SL_AND: \n   ^~~~~~~\n%Error: data/full_repos/permissive/109846502/Calkko.v:56: Define or directive not defined: \'`SL_OR\'\n   `SL_OR: binaryResult <= binaryA | binaryB;\n   ^~~~~~\n%Error: Exiting due to 9 error(s)\n'
module Calkko(
		input [3:0] A1,A2,A3,A4,
		input [3:0] B1,B2,B3,B4,
		input [1:0] ST,
		input [2:0] ST_L,
		output set,
		output reg [15:0] number
    );

wire [13:0] binaryA, binaryB;
reg [13:0] binaryResult;

assign set = ST == `S_OBL;

wire [3:0] BCD1, BCD2, BCD3, BCD4;

bcd2bin bikko( .N1(A1), .N2(A2), .N3(A3), .N4(A4), .out(binaryA));
bcd2bin akko( .N1(B1), .N2(B2), .N3(B3), .N4(B4), .out(binaryB));
bin2bcd resultto (.bin(binaryResult), 
.thousands(BCD1), .hundreds(BCD2), .tens(BCD3), .ones(BCD4));



always @* begin
	if(set) begin
		case(ST_L) 
			`SL_ADD:
				binaryResult <= binaryA + binaryB;
			`SL_SUB:
				binaryResult <= binaryA - binaryB;
			`SL_XOR:
				binaryResult <= binaryA ^ binaryB;
			`SL_AND: 
				binaryResult <= binaryA & binaryB;
			`SL_OR: binaryResult <= binaryA | binaryB;
			default:
				binaryResult <= 14'd0;

		endcase
		number[15:12] <= BCD4;
				number[11:8] <= BCD3;
				number [7:4] <= BCD2;
				number[3:0] <= BCD1;
	end
	else 
	begin
		number <= 16'd0;
		binaryResult <= 14'd0;
	end
end


endmodule
module Calkko(
		input [3:0] A1,A2,A3,A4,
		input [3:0] B1,B2,B3,B4,
		input [1:0] ST,
		input [2:0] ST_L,
		output set,
		output reg [15:0] number
    );


wire [13:0] binaryA, binaryB;
reg [13:0] binaryResult;

assign set = ST == `S_OBL;

wire [3:0] BCD1, BCD2, BCD3, BCD4;

bcd2bin bikko( .N1(A1), .N2(A2), .N3(A3), .N4(A4), .out(binaryA));
bcd2bin akko( .N1(B1), .N2(B2), .N3(B3), .N4(B4), .out(binaryB));
bin2bcd resultto (.bin(binaryResult), 
.thousands(BCD1), .hundreds(BCD2), .tens(BCD3), .ones(BCD4));



always @* begin
	if(set) begin
		case(ST_L) 
			`SL_ADD:
				binaryResult <= binaryA + binaryB;
			`SL_SUB:
				binaryResult <= binaryA - binaryB;
			`SL_XOR:
				binaryResult <= binaryA ^ binaryB;
			`SL_AND: 
				binaryResult <= binaryA & binaryB;
			`SL_OR: binaryResult <= binaryA | binaryB;
			default:
				binaryResult <= 14'd0;

		endcase
		number[15:12] <= BCD4;
				number[11:8] <= BCD3;
				number [7:4] <= BCD2;
				number[3:0] <= BCD1;
	end
	else 
	begin
		number <= 16'd0;
		binaryResult <= 14'd0;
	end
end


endmodule