data/full_repos/permissive/109936328/memory_peripheral/timer.v
 line:58: before: "*"
1: b"%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:21: Define or directive not defined: '`ADDR_W'\n  parameter [`ADDR_W - 1:0] ADDR_START = 0;\n             ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:35: Define or directive not defined: '`ADDR_W'\n  input [`ADDR_W - 1:0] i_req_addr;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:36: Define or directive not defined: '`WORD_W'\n  input [`WORD_W - 1:0] i_req_wr_data;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:38: Define or directive not defined: '`MEM_COUNT_W'\n  input [`MEM_COUNT_W - 1:0] i_req_count;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:40: Define or directive not defined: '`WORD_W'\n  output reg [`WORD_W - 1:0] o_res_rd_data;\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:41: Define or directive not defined: '`MEM_CODE_W'\n  output reg [`MEM_CODE_W - 1:0] o_res_code;\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:53: Define or directive not defined: '`WORD_W'\n  wire [`WORD_W - 1:0] threshold;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:54: Define or directive not defined: '`WORD_W'\n  wire [`WORD_W - 1:0] load_val;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:56: Define or directive not defined: '`WORD_W'\n  wire [RW_WORD_COUNT * `WORD_W - 1:0] s_readwrite_data;\n                        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:58: Define or directive not defined: '`WORD_W'\n  assign load_val = s_readwrite_data[`WORD_W * 3 - 1:`WORD_W * 2];\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:58: syntax error, unexpected '*', expecting TYPE-IDENTIFIER\n  assign load_val = s_readwrite_data[`WORD_W * 3 - 1:`WORD_W * 2];\n                                             ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:58: Define or directive not defined: '`WORD_W'\n  assign load_val = s_readwrite_data[`WORD_W * 3 - 1:`WORD_W * 2];\n                                                     ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:59: Define or directive not defined: '`WORD_W'\n  assign threshold = s_readwrite_data[`WORD_W * 2 - 1:`WORD_W * 1];\n                                      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:59: syntax error, unexpected '*', expecting TYPE-IDENTIFIER\n  assign threshold = s_readwrite_data[`WORD_W * 2 - 1:`WORD_W * 1];\n                                              ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:59: Define or directive not defined: '`WORD_W'\n  assign threshold = s_readwrite_data[`WORD_W * 2 - 1:`WORD_W * 1];\n                                                      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:67: Define or directive not defined: '`WORD_W'\n  reg [`WORD_W - 1:0] count;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:71: Define or directive not defined: '`WORD_W'\n  wire [RO_WORD_COUNT * `WORD_W - 1:0] s_readonly_data;\n                        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:74: Define or directive not defined: '`WORD_W'\n    {(`WORD_W - 1){1'b0}}, threshold_trigger  \n      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:77: Define or directive not defined: '`WORD_W'\n  wire [`WORD_W - 1:0] s_rw_rd_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:78: Define or directive not defined: '`MEM_CODE_W'\n  wire [`MEM_CODE_W - 1:0] s_rw_code;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:80: Define or directive not defined: '`WORD_W'\n  wire [`WORD_W - 1:0] s_ro_rd_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:81: Define or directive not defined: '`MEM_CODE_W'\n  wire [`MEM_CODE_W - 1:0] s_ro_code;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:139: Define or directive not defined: '`WORD_W'\n  wire [`WORD_W - 2 - 1:0] word_addr;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/timer.v:140: Define or directive not defined: '`WORD_W'\n  assign word_addr = i_req_addr[`WORD_W - 1:2];\n                                ^~~~~~~\n%Error: Exiting due to 24 error(s)\n"
module timer(
  clk,
  aresetn,

  i_req_addr,
  i_req_wr_data,
  i_req_wr_en,
  i_req_count,

  o_res_rd_data,
  o_res_code
);
  parameter [`ADDR_W - 1:0] ADDR_START = 0;

  localparam RW_ADDR_START = ADDR_START;
  localparam RW_ADDR_COUNT = 12;
  localparam RW_ADDR_END = RW_ADDR_START + RW_ADDR_COUNT - 1;
  localparam RW_WORD_COUNT = $ceil(RW_ADDR_COUNT / 4);
  localparam RO_ADDR_START = RW_ADDR_END;
  localparam RO_ADDR_COUNT = 8;
  localparam RO_ADDR_END = RO_ADDR_START + RO_ADDR_COUNT - 1;
  localparam RO_WORD_COUNT = $ceil(RO_ADDR_COUNT / 4);

  input clk;
  input aresetn;

  input [`ADDR_W - 1:0] i_req_addr;
  input [`WORD_W - 1:0] i_req_wr_data;
  input i_req_wr_en;
  input [`MEM_COUNT_W - 1:0] i_req_count;

  output reg [`WORD_W - 1:0] o_res_rd_data;
  output reg [`MEM_CODE_W - 1:0] o_res_code;



  wire en;

  wire backward;

  wire load;

  wire threshold_en;
  wire [`WORD_W - 1:0] threshold;
  wire [`WORD_W - 1:0] load_val;

  wire [RW_WORD_COUNT * `WORD_W - 1:0] s_readwrite_data;

  assign load_val = s_readwrite_data[`WORD_W * 3 - 1:`WORD_W * 2];
  assign threshold = s_readwrite_data[`WORD_W * 2 - 1:`WORD_W * 1];

  assign threshold_en = s_readwrite_data[0];
  assign load = s_readwrite_data[1];
  assign backward = s_readwrite_data[2];
  assign en = s_readwrite_data[3];


  reg [`WORD_W - 1:0] count;

  wire threshold_trigger;

  wire [RO_WORD_COUNT * `WORD_W - 1:0] s_readonly_data;
  assign s_readonly_data = {
    count,
    {(`WORD_W - 1){1'b0}}, threshold_trigger
  };

  wire [`WORD_W - 1:0] s_rw_rd_data;
  wire [`MEM_CODE_W - 1:0] s_rw_code;

  wire [`WORD_W - 1:0] s_ro_rd_data;
  wire [`MEM_CODE_W - 1:0] s_ro_code;

  assign threshold_trigger = count == threshold && aresetn == 1 &&
    threshold_en == 1;
  always@(posedge clk, negedge aresetn) begin
    if(aresetn == 0) begin
      count <= 0;
    end else begin
      if(load == 1) begin
        count <= load_val;
      end else if(en == 1) begin
        if(backward == 0) begin
          count <= count + 1;
        end else begin
          count <= count - 1;
        end
      end
    end
  end


  readwrite_registers#(
    .ADDR_START(RW_ADDR_START),
    .WORD_COUNT(RW_WORD_COUNT)
  ) rw_reg(
    .clk(clk),
    .aresetn(aresetn),

    .i_req_addr(i_req_addr),
    .i_req_wr_data(i_req_wr_data),
    .i_req_wr_en(i_req_wr_en),
    .i_req_count(i_req_count),

    .o_res_rd_data(s_rw_rd_data),
    .o_res_code(s_rw_code),

    .o_exposed_mem(s_readwrite_data)
  );


  readonly_registers#(
    .ADDR_START(RO_ADDR_START),
    .WORD_COUNT(RO_WORD_COUNT)
  ) ro_reg(
    .clk(clk),
    .aresetn(aresetn),

    .i_registers(s_readonly_data),

    .i_req_addr(i_req_addr),
    .i_req_count(i_req_count),

    .o_res_rd_data(s_ro_rd_data),
    .o_res_code(s_ro_code)
  );


  wire [`WORD_W - 2 - 1:0] word_addr;
  assign word_addr = i_req_addr[`WORD_W - 1:2];
  always@(*) begin: output_mux
    if(word_addr >= RW_ADDR_START && word_addr <= RW_ADDR_END) begin
      o_res_rd_data = s_rw_rd_data;
      o_res_code = s_rw_code;
    end else if(word_addr >= RO_ADDR_START && word_addr <= RO_ADDR_END) begin
      o_res_rd_data = s_ro_rd_data;
      o_res_code = s_ro_code;
    end else begin
      o_res_rd_data = 'bz;
      o_res_code = 'bz;
    end
  end
endmodule
module timer(
  clk,
  aresetn,

  i_req_addr,
  i_req_wr_data,
  i_req_wr_en,
  i_req_count,

  o_res_rd_data,
  o_res_code
);

  parameter [`ADDR_W - 1:0] ADDR_START = 0;

  localparam RW_ADDR_START = ADDR_START;
  localparam RW_ADDR_COUNT = 12;
  localparam RW_ADDR_END = RW_ADDR_START + RW_ADDR_COUNT - 1;
  localparam RW_WORD_COUNT = $ceil(RW_ADDR_COUNT / 4);
  localparam RO_ADDR_START = RW_ADDR_END;
  localparam RO_ADDR_COUNT = 8;
  localparam RO_ADDR_END = RO_ADDR_START + RO_ADDR_COUNT - 1;
  localparam RO_WORD_COUNT = $ceil(RO_ADDR_COUNT / 4);

  input clk;
  input aresetn;

  input [`ADDR_W - 1:0] i_req_addr;
  input [`WORD_W - 1:0] i_req_wr_data;
  input i_req_wr_en;
  input [`MEM_COUNT_W - 1:0] i_req_count;

  output reg [`WORD_W - 1:0] o_res_rd_data;
  output reg [`MEM_CODE_W - 1:0] o_res_code;



  wire en;

  wire backward;

  wire load;

  wire threshold_en;
  wire [`WORD_W - 1:0] threshold;
  wire [`WORD_W - 1:0] load_val;

  wire [RW_WORD_COUNT * `WORD_W - 1:0] s_readwrite_data;

  assign load_val = s_readwrite_data[`WORD_W * 3 - 1:`WORD_W * 2];
  assign threshold = s_readwrite_data[`WORD_W * 2 - 1:`WORD_W * 1];

  assign threshold_en = s_readwrite_data[0];
  assign load = s_readwrite_data[1];
  assign backward = s_readwrite_data[2];
  assign en = s_readwrite_data[3];


  reg [`WORD_W - 1:0] count;

  wire threshold_trigger;

  wire [RO_WORD_COUNT * `WORD_W - 1:0] s_readonly_data;
  assign s_readonly_data = {
    count,
    {(`WORD_W - 1){1'b0}}, threshold_trigger
  };

  wire [`WORD_W - 1:0] s_rw_rd_data;
  wire [`MEM_CODE_W - 1:0] s_rw_code;

  wire [`WORD_W - 1:0] s_ro_rd_data;
  wire [`MEM_CODE_W - 1:0] s_ro_code;

  assign threshold_trigger = count == threshold && aresetn == 1 &&
    threshold_en == 1;
  always@(posedge clk, negedge aresetn) begin
    if(aresetn == 0) begin
      count <= 0;
    end else begin
      if(load == 1) begin
        count <= load_val;
      end else if(en == 1) begin
        if(backward == 0) begin
          count <= count + 1;
        end else begin
          count <= count - 1;
        end
      end
    end
  end


  readwrite_registers#(
    .ADDR_START(RW_ADDR_START),
    .WORD_COUNT(RW_WORD_COUNT)
  ) rw_reg(
    .clk(clk),
    .aresetn(aresetn),

    .i_req_addr(i_req_addr),
    .i_req_wr_data(i_req_wr_data),
    .i_req_wr_en(i_req_wr_en),
    .i_req_count(i_req_count),

    .o_res_rd_data(s_rw_rd_data),
    .o_res_code(s_rw_code),

    .o_exposed_mem(s_readwrite_data)
  );


  readonly_registers#(
    .ADDR_START(RO_ADDR_START),
    .WORD_COUNT(RO_WORD_COUNT)
  ) ro_reg(
    .clk(clk),
    .aresetn(aresetn),

    .i_registers(s_readonly_data),

    .i_req_addr(i_req_addr),
    .i_req_count(i_req_count),

    .o_res_rd_data(s_ro_rd_data),
    .o_res_code(s_ro_code)
  );


  wire [`WORD_W - 2 - 1:0] word_addr;
  assign word_addr = i_req_addr[`WORD_W - 1:2];
  always@(*) begin: output_mux
    if(word_addr >= RW_ADDR_START && word_addr <= RW_ADDR_END) begin
      o_res_rd_data = s_rw_rd_data;
      o_res_code = s_rw_code;
    end else if(word_addr >= RO_ADDR_START && word_addr <= RO_ADDR_END) begin
      o_res_rd_data = s_ro_rd_data;
      o_res_code = s_ro_code;
    end else begin
      o_res_rd_data = 'bz;
      o_res_code = 'bz;
    end
  end
endmodule