data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/control.v
 line:101: before: ","
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/control.v:200: Cannot find file containing module: 'rmw_address_unit'\n   rmw_address_unit\n   ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/rmw_address_unit\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/rmw_address_unit.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/rmw_address_unit.sv\n             rmw_address_unit\n             rmw_address_unit.v\n             rmw_address_unit.sv\n             obj_dir/rmw_address_unit\n             obj_dir/rmw_address_unit.v\n             obj_dir/rmw_address_unit.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/control.v:217: Cannot find file containing module: 'rmw_address_unit'\n   rmw_address_unit\n   ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module control
  #(
    parameter IBITS = 24,
    parameter ISB   = IBITS-1,


    parameter TICKS = 4,
    parameter SLOW  = 0,
    parameter DUPS  = 0,


    parameter TRATE = 12,
    parameter TBITS = 4,
    parameter TSB   = TBITS-1,


    parameter XBITS = 4,
    parameter XSB   = XBITS-1,


    parameter DELAY = 3)
   (
    input          clk_x,
    input          rst,


    input          sw_i,
    input          en_i,
    input [ISB:0]  re_i,
    input [ISB:0]  im_i,


    output [TSB:0] x_rd_adr_o,
    output [TSB:0] x_wr_adr_o,

    output [TSB:0] y_rd_adr_o,
    output [TSB:0] y_wr_adr_o,

    output         swap_o,
    output         en_o,
    output [XSB:0] bank_o,
    output [ISB:0] real_o,
    output [ISB:0] imag_o
    );



   reg             swap = 1'b0, clear = 1'b1, clear_r = 1'b1;
   reg [XSB:0]     bank = {XBITS{1'b0}};
   wire [XBITS:0]  next_bank;


   wire            sw, en;
   wire [ISB:0]    re, im;
   reg             sw_r = 1'b0, en_r = 1'b0;
   reg [ISB:0]     re_r, im_r;


   wire            wrap_x_rd_adr, wrap_x_wr_adr;
   wire            w_swp, w_inc;
   (* NOMERGE = "TRUE" *) wire [TSB:0] x_rd_adr;
   (* NOMERGE = "TRUE" *) wire [TSB:0] x_wr_adr;
   (* NOMERGE = "TRUE" *) wire [TSB:0] y_rd_adr;
   (* NOMERGE = "TRUE" *) wire [TSB:0] y_wr_adr;





   assign en_o   = en;
   assign swap_o = TICKS == 3 ? clear : clear_r;
   assign bank_o = bank;
   assign real_o = re;
   assign imag_o = im;





   assign x_rd_adr_o = x_rd_adr;
   assign x_wr_adr_o = x_wr_adr;


   assign y_rd_adr_o = DUPS ? y_rd_adr : x_rd_adr;
   assign y_wr_adr_o = DUPS ? y_wr_adr : x_wr_adr;

   assign w_swp = wrap_x_rd_adr && (sw || swap);
   assign w_inc = wrap_x_wr_adr && clear;





   assign sw        = SLOW ? sw_i : sw_r;
   assign en        = SLOW ? en_i : en_r;
   assign re        = SLOW ? re_i : re_r;
   assign im        = SLOW ? im_i : im_r;

   assign next_bank = bank + 1;






   always @(posedge clk_x)
     if (rst || w_swp)
       swap <= #DELAY 1'b0;
     else if (sw && !swap)
       swap <= #DELAY 1'b1;
   


   always @(posedge clk_x)
     if (rst || !en)
        clear <= #DELAY 1'b1;
     else if (w_swp)
        clear <= #DELAY 1'b1;
     else if (wrap_x_rd_adr && clear)
        clear <= #DELAY 1'b0;



   always @(posedge clk_x)
     if (rst)
       bank <= #DELAY {XBITS{1'b0}};
     else if (w_inc)
       bank <= #DELAY next_bank[XSB:0];






   always @(posedge clk_x)
     {sw_r, en_r, im_r, re_r} <= #DELAY {sw_i, en_i, im_i, re_i};



   always @(posedge clk_x)
     clear_r <= #DELAY clear;





   rmw_address_unit
     #(  .ABITS(TBITS),
         .UPPER(TRATE-1),
         .TICKS(TICKS),
         .DELAY(DELAY)
         ) RMWX
       ( .clk_i(clk_x),
         .rst_i(rst),
         .ce_i(en),
         .rd_adr_o(x_rd_adr),
         .rd_wrap_o(wrap_x_rd_adr),
         .wr_adr_o(x_wr_adr),
         .wr_wrap_o(wrap_x_wr_adr)
         );



   rmw_address_unit
     #(  .ABITS(TBITS),
         .UPPER(TRATE-1),
         .TICKS(TICKS),
         .DELAY(DELAY)
         ) RMWY
       ( .clk_i(DUPS ? clk_x : 1'b0),
         .rst_i(DUPS ? rst   : 1'b0),
         .ce_i (DUPS ? en    : 1'b0),
         .rd_adr_o(y_rd_adr),
         .rd_wrap_o(),
         .wr_adr_o(y_wr_adr),
         .wr_wrap_o()
         );


endmodule
module control
  #(
    parameter IBITS = 24,
    parameter ISB   = IBITS-1,


    parameter TICKS = 4,
    parameter SLOW  = 0,
    parameter DUPS  = 0,


    parameter TRATE = 12,
    parameter TBITS = 4,
    parameter TSB   = TBITS-1,


    parameter XBITS = 4,
    parameter XSB   = XBITS-1,


    parameter DELAY = 3)
   (
    input          clk_x,
    input          rst,


    input          sw_i,
    input          en_i,
    input [ISB:0]  re_i,
    input [ISB:0]  im_i,


    output [TSB:0] x_rd_adr_o,
    output [TSB:0] x_wr_adr_o,

    output [TSB:0] y_rd_adr_o,
    output [TSB:0] y_wr_adr_o,

    output         swap_o,
    output         en_o,
    output [XSB:0] bank_o,
    output [ISB:0] real_o,
    output [ISB:0] imag_o
    );




   reg             swap = 1'b0, clear = 1'b1, clear_r = 1'b1;
   reg [XSB:0]     bank = {XBITS{1'b0}};
   wire [XBITS:0]  next_bank;


   wire            sw, en;
   wire [ISB:0]    re, im;
   reg             sw_r = 1'b0, en_r = 1'b0;
   reg [ISB:0]     re_r, im_r;


   wire            wrap_x_rd_adr, wrap_x_wr_adr;
   wire            w_swp, w_inc;
   (* NOMERGE = "TRUE" *) wire [TSB:0] x_rd_adr;
   (* NOMERGE = "TRUE" *) wire [TSB:0] x_wr_adr;
   (* NOMERGE = "TRUE" *) wire [TSB:0] y_rd_adr;
   (* NOMERGE = "TRUE" *) wire [TSB:0] y_wr_adr;





   assign en_o   = en;
   assign swap_o = TICKS == 3 ? clear : clear_r;
   assign bank_o = bank;
   assign real_o = re;
   assign imag_o = im;





   assign x_rd_adr_o = x_rd_adr;
   assign x_wr_adr_o = x_wr_adr;


   assign y_rd_adr_o = DUPS ? y_rd_adr : x_rd_adr;
   assign y_wr_adr_o = DUPS ? y_wr_adr : x_wr_adr;

   assign w_swp = wrap_x_rd_adr && (sw || swap);
   assign w_inc = wrap_x_wr_adr && clear;





   assign sw        = SLOW ? sw_i : sw_r;
   assign en        = SLOW ? en_i : en_r;
   assign re        = SLOW ? re_i : re_r;
   assign im        = SLOW ? im_i : im_r;

   assign next_bank = bank + 1;






   always @(posedge clk_x)
     if (rst || w_swp)
       swap <= #DELAY 1'b0;
     else if (sw && !swap)
       swap <= #DELAY 1'b1;
   


   always @(posedge clk_x)
     if (rst || !en)
        clear <= #DELAY 1'b1;
     else if (w_swp)
        clear <= #DELAY 1'b1;
     else if (wrap_x_rd_adr && clear)
        clear <= #DELAY 1'b0;



   always @(posedge clk_x)
     if (rst)
       bank <= #DELAY {XBITS{1'b0}};
     else if (w_inc)
       bank <= #DELAY next_bank[XSB:0];






   always @(posedge clk_x)
     {sw_r, en_r, im_r, re_r} <= #DELAY {sw_i, en_i, im_i, re_i};



   always @(posedge clk_x)
     clear_r <= #DELAY clear;





   rmw_address_unit
     #(  .ABITS(TBITS),
         .UPPER(TRATE-1),
         .TICKS(TICKS),
         .DELAY(DELAY)
         ) RMWX
       ( .clk_i(clk_x),
         .rst_i(rst),
         .ce_i(en),
         .rd_adr_o(x_rd_adr),
         .rd_wrap_o(wrap_x_rd_adr),
         .wr_adr_o(x_wr_adr),
         .wr_wrap_o(wrap_x_wr_adr)
         );



   rmw_address_unit
     #(  .ABITS(TBITS),
         .UPPER(TRATE-1),
         .TICKS(TICKS),
         .DELAY(DELAY)
         ) RMWY
       ( .clk_i(DUPS ? clk_x : 1'b0),
         .rst_i(DUPS ? rst   : 1'b0),
         .ce_i (DUPS ? en    : 1'b0),
         .rd_adr_o(y_rd_adr),
         .rd_wrap_o(),
         .wr_adr_o(y_wr_adr),
         .wr_wrap_o()
         );


endmodule