data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-pmod-i2s2/szg-i2s2-pmod-phy.v
1: b'%Warning-WIDTH: data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-pmod-i2s2/szg-i2s2-pmod-phy.v:74: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                                             : ... In instance szg_i2s2_pmod_phy\n  if (lrck != lrck_r) valid_count <= 32\'d0;\n                                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module szg_i2s2_pmod_phy(
	input  wire        clk,
	input  wire        reset,

	output wire        mclk,
	output wire        lrck,
	output wire        sclk,
	input  wire        sdin,

	output reg  [23:0] r_channel,
	output reg  [23:0] l_channel
);

reg [23:0] r_channel_r, l_channel_r;
reg [6:0]  valid_count;
reg [10:0] count;
reg        sclk_r, lrck_r;


assign     mclk     = count[1];

assign     sclk     = count[4];

assign     lrck     = count[10];


localparam up_shift = 24'h7FFFFF;

always @(posedge clk) begin
	if (reset) begin
		r_channel   <= 24'd0;
		l_channel   <= 24'd0;
		r_channel_r <= 24'd0;
		l_channel_r <= 24'd0;
		valid_count <= 7'd0;
		count       <= 11'd0;
		sclk_r      <= 1'b0;
		lrck_r      <= 1'b0;
	end else begin

		count       <= count + 1;


		if (lrck != lrck_r) valid_count <= 32'd0;


			if (sclk && ~sclk_r) begin
				valid_count <= valid_count + 1;
				if (valid_count >= 1 && valid_count <= 24) begin

					if (lrck) begin
						r_channel_r <= {r_channel_r[22:0], sdin};

						l_channel   <= l_channel_r + up_shift;
					end else begin
						l_channel_r <= {l_channel_r[22:0], sdin};

						r_channel   <= r_channel_r + up_shift;
					end
				end
			end

		sclk_r      <= sclk;
		lrck_r      <= lrck;
	end
end

endmodule
module szg_i2s2_pmod_phy(
	input  wire        clk,
	input  wire        reset,

	output wire        mclk,
	output wire        lrck,
	output wire        sclk,
	input  wire        sdin,

	output reg  [23:0] r_channel,
	output reg  [23:0] l_channel
);


reg [23:0] r_channel_r, l_channel_r;
reg [6:0]  valid_count;
reg [10:0] count;
reg        sclk_r, lrck_r;


assign     mclk     = count[1];

assign     sclk     = count[4];

assign     lrck     = count[10];


localparam up_shift = 24'h7FFFFF;

always @(posedge clk) begin
	if (reset) begin
		r_channel   <= 24'd0;
		l_channel   <= 24'd0;
		r_channel_r <= 24'd0;
		l_channel_r <= 24'd0;
		valid_count <= 7'd0;
		count       <= 11'd0;
		sclk_r      <= 1'b0;
		lrck_r      <= 1'b0;
	end else begin

		count       <= count + 1;


		if (lrck != lrck_r) valid_count <= 32'd0;


			if (sclk && ~sclk_r) begin
				valid_count <= valid_count + 1;
				if (valid_count >= 1 && valid_count <= 24) begin

					if (lrck) begin
						r_channel_r <= {r_channel_r[22:0], sdin};

						l_channel   <= l_channel_r + up_shift;
					end else begin
						l_channel_r <= {l_channel_r[22:0], sdin};

						r_channel   <= r_channel_r + up_shift;
					end
				end
			end

		sclk_r      <= sclk;
		lrck_r      <= lrck;
	end
end

endmodule