data/full_repos/permissive/2084115/rtl/dma/jelly_buffer_manager.v
 line:89: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_buffer_manager.v:120: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 8 bits.\n                                                                                     : ... In instance jelly_buffer_manager\n                    if ( s_wb_adr_i == ADR_BUFFER0_ADDR + i ) begin\n                                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_buffer_manager.v:120: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'ADR_BUFFER0_ADDR\' generates 8 bits.\n                                                                                     : ... In instance jelly_buffer_manager\n                    if ( s_wb_adr_i == ADR_BUFFER0_ADDR + i ) begin\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_buffer_manager.v:136: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'newest_index\' generates 2 bits.\n                                                                                     : ... In instance jelly_buffer_manager\n        ADR_NEWEST_INDEX:   wb_dat_o = newest_index;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_buffer_manager.v:137: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'writer_index\' generates 2 bits.\n                                                                                     : ... In instance jelly_buffer_manager\n        ADR_WRITER_INDEX:   wb_dat_o = writer_index;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_buffer_manager.v:141: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 8 bits.\n                                                                                     : ... In instance jelly_buffer_manager\n            if ( s_wb_adr_i == ADR_BUFFER0_ADDR + i ) begin\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_buffer_manager.v:141: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'ADR_BUFFER0_ADDR\' generates 8 bits.\n                                                                                     : ... In instance jelly_buffer_manager\n            if ( s_wb_adr_i == ADR_BUFFER0_ADDR + i ) begin\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_buffer_manager.v:145: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                     : ... In instance jelly_buffer_manager\n                wb_dat_o = status_refcnt[i*REFCNT_WIDTH +: REFCNT_WIDTH];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_buffer_manager.v:144: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 8 bits.\n                                                                                     : ... In instance jelly_buffer_manager\n            if ( s_wb_adr_i == ADR_BUFFER0_REFCNT + i ) begin\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/dma/jelly_buffer_manager.v:144: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'ADR_BUFFER0_REFCNT\' generates 8 bits.\n                                                                                     : ... In instance jelly_buffer_manager\n            if ( s_wb_adr_i == ADR_BUFFER0_REFCNT + i ) begin\n                                                  ^\n%Error: data/full_repos/permissive/2084115/rtl/dma/jelly_buffer_manager.v:155: Cannot find file containing module: \'jelly_buffer_arbiter\'\n    jelly_buffer_arbiter\n    ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/dma,data/full_repos/permissive/2084115/jelly_buffer_arbiter\n             data/full_repos/permissive/2084115/rtl/dma,data/full_repos/permissive/2084115/jelly_buffer_arbiter.v\n             data/full_repos/permissive/2084115/rtl/dma,data/full_repos/permissive/2084115/jelly_buffer_arbiter.sv\n             jelly_buffer_arbiter\n             jelly_buffer_arbiter.v\n             jelly_buffer_arbiter.sv\n             obj_dir/jelly_buffer_arbiter\n             obj_dir/jelly_buffer_arbiter.v\n             obj_dir/jelly_buffer_arbiter.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n'
function [WB_DAT_WIDTH-1:0] write_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] dat,
                                        input [WB_SEL_WIDTH-1:0] sel
                                    );
    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            write_mask[i] = sel[i/8] ? dat[i] : org[i];
        end
    end
    endfunction
function [WB_DAT_WIDTH-1:0] write_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] dat,
                                        input [WB_SEL_WIDTH-1:0] sel
                                    );

    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            write_mask[i] = sel[i/8] ? dat[i] : org[i];
        end
    end
    endfunction