data/full_repos/permissive/167489907/Testbenches/ALU_LEGv8_tb.v
 line:26: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/ALU_LEGv8_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #5 \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/ALU_LEGv8_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #5 \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/ALU_LEGv8_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #5 FS <= 5\'b01100;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/ALU_LEGv8_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #5 FS <= 5\'b00011;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/ALU_LEGv8_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #5 FS <= 5\'b00111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/ALU_LEGv8_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #5 FS <= 5\'b10000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/ALU_LEGv8_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #5 FS <= 5\'b10100;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/ALU_LEGv8_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #5 A <= 64\'h8000000000000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/ALU_LEGv8_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #5 $stop;\n  ^\n%Error: data/full_repos/permissive/167489907/Testbenches/ALU_LEGv8_tb.v:8: Cannot find file containing module: \'ALU_LEGv8\'\n ALU_LEGv8 dut (A, B, FS, C0, F, status);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167489907/Testbenches,data/full_repos/permissive/167489907/ALU_LEGv8\n             data/full_repos/permissive/167489907/Testbenches,data/full_repos/permissive/167489907/ALU_LEGv8.v\n             data/full_repos/permissive/167489907/Testbenches,data/full_repos/permissive/167489907/ALU_LEGv8.sv\n             ALU_LEGv8\n             ALU_LEGv8.v\n             ALU_LEGv8.sv\n             obj_dir/ALU_LEGv8\n             obj_dir/ALU_LEGv8.v\n             obj_dir/ALU_LEGv8.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_LEGv8_tb;
	reg [63:0] A, B;
	reg [4:0] FS;
	reg C0;
	wire [63:0] F;
	wire [3:0] status;
	
	ALU_LEGv8 dut (A, B, FS, C0, F, status);
	
	
	initial begin
		FS <= 5'b00000;
		A <= 64'b110;
		B <= 64'b011;
		#5 
		FS <= 5'b00100;
		#5 
		FS <= 5'b01000;
		C0 <= 1'b0;
		#5 FS <= 5'b01100;
		#5 FS <= 5'b00011;
		#5 FS <= 5'b00111;
		#5 FS <= 5'b10000;
		#5 FS <= 5'b10100;
		#5 A <= 64'h8000000000000000;
		#5 $stop;
	end
endmodule
module ALU_LEGv8_tb;

	reg [63:0] A, B;
	reg [4:0] FS;
	reg C0;
	wire [63:0] F;
	wire [3:0] status;
	
	ALU_LEGv8 dut (A, B, FS, C0, F, status);
	
	
	initial begin
		FS <= 5'b00000;
		A <= 64'b110;
		B <= 64'b011;
		#5 
		FS <= 5'b00100;
		#5 
		FS <= 5'b01000;
		C0 <= 1'b0;
		#5 FS <= 5'b01100;
		#5 FS <= 5'b00011;
		#5 FS <= 5'b00111;
		#5 FS <= 5'b10000;
		#5 FS <= 5'b10100;
		#5 A <= 64'h8000000000000000;
		#5 $stop;
	end
endmodule