data/full_repos/permissive/107499099/ex1/rom8x1024_sim.v
'utf-8' codec can't decode byte 0xa4 in position 174: invalid start byte
1: b'%Warning-WIDTH: data/full_repos/permissive/107499099/ex1/rom8x1024_sim.v:23: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                           : ... In instance rom8x1024_sim\n  assign word_addr = rom_addr[9:2];\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module rom8x1024_sim (rom_addr, rom_data);

  input   [11:0]  rom_addr;
  output  [31:0]  rom_data;

  reg     [31:0]  data;


  wire     [9:0]  word_addr;

  assign word_addr = rom_addr[9:2];
   
  always @(word_addr) begin
    case (word_addr)
      10'h000: data = 32'he000000c;
      10'h001: data = 32'h00000000;
      10'h002: data = 32'h00000000;
      10'h003: data = 32'h00000000;
      10'h004: data = 32'h00000000;
      10'h005: data = 32'h00408050;
      10'h006: data = 32'h00000000;
      10'h007: data = 32'h00000000;
      10'h008: data = 32'h27bdfff8;
      10'h009: data = 32'hafbe0000;
      10'h00a: data = 32'h03a0f021;
      10'h00b: data = 32'h24020300;
      10'h00c: data = 32'hac400000;
      10'h00d: data = 32'h24030304;
      10'h00e: data = 32'h24020002;
      10'h00f: data = 32'hac620000;
      10'h010: data = 32'h24030300;
      10'h011: data = 32'h24020001;
      10'h012: data = 32'hac620000;
      10'h013: data = 32'h03c0e821;
      10'h014: data = 32'h8fbe0000;
      10'h015: data = 32'h27bd0008;
      10'h016: data = 32'h03e00008;
      10'h017: data = 32'h00000000;
    endcase
  end

  assign rom_data = data;
endmodule
module rom8x1024_sim (rom_addr, rom_data);


  input   [11:0]  rom_addr;
  output  [31:0]  rom_data;

  reg     [31:0]  data;


  wire     [9:0]  word_addr;

  assign word_addr = rom_addr[9:2];
   
  always @(word_addr) begin
    case (word_addr)
      10'h000: data = 32'he000000c;
      10'h001: data = 32'h00000000;
      10'h002: data = 32'h00000000;
      10'h003: data = 32'h00000000;
      10'h004: data = 32'h00000000;
      10'h005: data = 32'h00408050;
      10'h006: data = 32'h00000000;
      10'h007: data = 32'h00000000;
      10'h008: data = 32'h27bdfff8;
      10'h009: data = 32'hafbe0000;
      10'h00a: data = 32'h03a0f021;
      10'h00b: data = 32'h24020300;
      10'h00c: data = 32'hac400000;
      10'h00d: data = 32'h24030304;
      10'h00e: data = 32'h24020002;
      10'h00f: data = 32'hac620000;
      10'h010: data = 32'h24030300;
      10'h011: data = 32'h24020001;
      10'h012: data = 32'hac620000;
      10'h013: data = 32'h03c0e821;
      10'h014: data = 32'h8fbe0000;
      10'h015: data = 32'h27bd0008;
      10'h016: data = 32'h03e00008;
      10'h017: data = 32'h00000000;
    endcase
  end

  assign rom_data = data;
endmodule