data/full_repos/permissive/155514739/servant/servix_clock_gen.v
1: b"%Error: data/full_repos/permissive/155514739/servant/servix_clock_gen.v:14: Cannot find file containing module: 'PLLE2_BASE'\n   PLLE2_BASE\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/155514739/servant,data/full_repos/permissive/155514739/PLLE2_BASE\n             data/full_repos/permissive/155514739/servant,data/full_repos/permissive/155514739/PLLE2_BASE.v\n             data/full_repos/permissive/155514739/servant,data/full_repos/permissive/155514739/PLLE2_BASE.sv\n             PLLE2_BASE\n             PLLE2_BASE.v\n             PLLE2_BASE.sv\n             obj_dir/PLLE2_BASE\n             obj_dir/PLLE2_BASE.v\n             obj_dir/PLLE2_BASE.sv\n%Error: Exiting due to 1 error(s)\n"
module servix_clock_gen
  (input wire  i_clk,
   input wire  i_rst,
   output wire o_clk,
   output reg  o_rst);

   parameter frequency = 32;

   wire   clkfb;
   wire   locked;
   reg 	  locked_r;

   PLLE2_BASE
     #(.BANDWIDTH("OPTIMIZED"),
       .CLKFBOUT_MULT(16),
       .CLKIN1_PERIOD(10.0),
       .CLKOUT0_DIVIDE((frequency == 32) ? 50 : 100),
       .DIVCLK_DIVIDE(1),
       .STARTUP_WAIT("FALSE"))
   PLLE2_BASE_inst
     (.CLKOUT0(o_clk),
      .CLKOUT1(),
      .CLKOUT2(),
      .CLKOUT3(),
      .CLKOUT4(),
      .CLKOUT5(),
      .CLKFBOUT(clkfb),
      .LOCKED(locked),
      .CLKIN1(i_clk),
      .PWRDWN(1'b0),
      .RST(i_rst),
      .CLKFBIN(clkfb));

   always @(posedge o_clk) begin
      locked_r <= locked;
      o_rst  <= !locked_r;
   end

endmodule
module servix_clock_gen
  (input wire  i_clk,
   input wire  i_rst,
   output wire o_clk,
   output reg  o_rst);


   parameter frequency = 32;

   wire   clkfb;
   wire   locked;
   reg 	  locked_r;

   PLLE2_BASE
     #(.BANDWIDTH("OPTIMIZED"),
       .CLKFBOUT_MULT(16),
       .CLKIN1_PERIOD(10.0),
       .CLKOUT0_DIVIDE((frequency == 32) ? 50 : 100),
       .DIVCLK_DIVIDE(1),
       .STARTUP_WAIT("FALSE"))
   PLLE2_BASE_inst
     (.CLKOUT0(o_clk),
      .CLKOUT1(),
      .CLKOUT2(),
      .CLKOUT3(),
      .CLKOUT4(),
      .CLKOUT5(),
      .CLKFBOUT(clkfb),
      .LOCKED(locked),
      .CLKIN1(i_clk),
      .PWRDWN(1'b0),
      .RST(i_rst),
      .CLKFBIN(clkfb));

   always @(posedge o_clk) begin
      locked_r <= locked;
      o_rst  <= !locked_r;
   end

endmodule