data/full_repos/permissive/216344104/multiple_uart.v
1: b"%Error: data/full_repos/permissive/216344104/multiple_uart.v:31: Cannot find file containing module: 'speed_setting'\nspeed_setting  speed_tx1( \n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216344104,data/full_repos/permissive/216344104/speed_setting\n             data/full_repos/permissive/216344104,data/full_repos/permissive/216344104/speed_setting.v\n             data/full_repos/permissive/216344104,data/full_repos/permissive/216344104/speed_setting.sv\n             speed_setting\n             speed_setting.v\n             speed_setting.sv\n             obj_dir/speed_setting\n             obj_dir/speed_setting.v\n             obj_dir/speed_setting.sv\n%Error: data/full_repos/permissive/216344104/multiple_uart.v:37: Cannot find file containing module: 'my_uart_tx'\nmy_uart_tx   my_uart_tx1(  \n^~~~~~~~~~\n%Error: data/full_repos/permissive/216344104/multiple_uart.v:48: Cannot find file containing module: 'speed_setting'\nspeed_setting  speed_tx2( \n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216344104/multiple_uart.v:54: Cannot find file containing module: 'my_uart_tx'\nmy_uart_tx   my_uart_tx2(  \n^~~~~~~~~~\n%Error: data/full_repos/permissive/216344104/multiple_uart.v:65: Cannot find file containing module: 'speed_setting'\nspeed_setting  speed_tx3( \n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216344104/multiple_uart.v:71: Cannot find file containing module: 'my_uart_tx'\nmy_uart_tx   my_uart_tx3(  \n^~~~~~~~~~\n%Error: data/full_repos/permissive/216344104/multiple_uart.v:82: Cannot find file containing module: 'speed_setting'\nspeed_setting  speed_tx4( \n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216344104/multiple_uart.v:88: Cannot find file containing module: 'my_uart_tx'\nmy_uart_tx   my_uart_tx4(  \n^~~~~~~~~~\n%Error: data/full_repos/permissive/216344104/multiple_uart.v:101: Cannot find file containing module: 'fdivision'\nfdivision fdivision(\n^~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module multiple_uart(
	input clk,
	input rst_n,
	input [7:0] data1,
	input [7:0] data2,
	input [7:0] data3,
	input [7:0] data4,
	output uart_tx,
	output total_pulse_test
);	




wire uart_clk1,uart_clk2,uart_clk3,uart_clk4;
wire uart_tx1,uart_tx2,uart_tx3,uart_tx4;
assign 	uart_tx = uart_tx1|uart_tx2|uart_tx3|uart_tx4;


wire bps_start1;
wire clk_bps1;
wire bps_start2;	
wire clk_bps2;		
wire bps_start3;	
wire clk_bps3;		
wire bps_start4;	
wire clk_bps4;	



speed_setting		speed_tx1(	
							.clk(clk),
							.rst_n(rst_n),
							.bps_start(bps_start1),
							.clk_bps(clk_bps1)
						);
my_uart_tx			my_uart_tx1(		
							.clk(clk),
							.rst_n(rst_n),
							.rx_data(data1),
							.rx_int(uart_clk1),
							.uart_tx(uart_tx1),
							.clk_bps(clk_bps1),
							.bps_start(bps_start1)
						);


speed_setting		speed_tx2(	
							.clk(clk),
							.rst_n(rst_n),
							.bps_start(bps_start2),
							.clk_bps(clk_bps2)
						);
my_uart_tx			my_uart_tx2(		
							.clk(clk),
							.rst_n(rst_n),
							.rx_data(data2),
							.rx_int(uart_clk2),
							.uart_tx(uart_tx2),
							.clk_bps(clk_bps2),
							.bps_start(bps_start2)
						);


speed_setting		speed_tx3(	
							.clk(clk),
							.rst_n(rst_n),
							.bps_start(bps_start3),
							.clk_bps(clk_bps3)
						);
my_uart_tx			my_uart_tx3(		
							.clk(clk),
							.rst_n(rst_n),
							.rx_data(data3),
							.rx_int(uart_clk3),
							.uart_tx(uart_tx3),
							.clk_bps(clk_bps3),
							.bps_start(bps_start3)
						);


speed_setting		speed_tx4(	
							.clk(clk),
							.rst_n(rst_n),
							.bps_start(bps_start4),
							.clk_bps(clk_bps4)
						);
my_uart_tx			my_uart_tx4(		
							.clk(clk),
							.rst_n(rst_n),
							.rx_data(data4),
							.rx_int(uart_clk4),
							.uart_tx(uart_tx4),
							.clk_bps(clk_bps4),
							.bps_start(bps_start4)
						);




fdivision fdivision(
    .RESET(rst_n), 
    .F50M(clk), 
    .pulse1(uart_clk1), 
    .pulse2(uart_clk2), 
    .pulse3(uart_clk3), 
    .pulse4(uart_clk4), 
    .total_pulse_test(total_pulse_test)
    );						
endmodule
module multiple_uart(
	input clk,
	input rst_n,
	input [7:0] data1,
	input [7:0] data2,
	input [7:0] data3,
	input [7:0] data4,
	output uart_tx,
	output total_pulse_test
);
	




wire uart_clk1,uart_clk2,uart_clk3,uart_clk4;
wire uart_tx1,uart_tx2,uart_tx3,uart_tx4;
assign 	uart_tx = uart_tx1|uart_tx2|uart_tx3|uart_tx4;


wire bps_start1;
wire clk_bps1;
wire bps_start2;	
wire clk_bps2;		
wire bps_start3;	
wire clk_bps3;		
wire bps_start4;	
wire clk_bps4;	



speed_setting		speed_tx1(	
							.clk(clk),
							.rst_n(rst_n),
							.bps_start(bps_start1),
							.clk_bps(clk_bps1)
						);
my_uart_tx			my_uart_tx1(		
							.clk(clk),
							.rst_n(rst_n),
							.rx_data(data1),
							.rx_int(uart_clk1),
							.uart_tx(uart_tx1),
							.clk_bps(clk_bps1),
							.bps_start(bps_start1)
						);


speed_setting		speed_tx2(	
							.clk(clk),
							.rst_n(rst_n),
							.bps_start(bps_start2),
							.clk_bps(clk_bps2)
						);
my_uart_tx			my_uart_tx2(		
							.clk(clk),
							.rst_n(rst_n),
							.rx_data(data2),
							.rx_int(uart_clk2),
							.uart_tx(uart_tx2),
							.clk_bps(clk_bps2),
							.bps_start(bps_start2)
						);


speed_setting		speed_tx3(	
							.clk(clk),
							.rst_n(rst_n),
							.bps_start(bps_start3),
							.clk_bps(clk_bps3)
						);
my_uart_tx			my_uart_tx3(		
							.clk(clk),
							.rst_n(rst_n),
							.rx_data(data3),
							.rx_int(uart_clk3),
							.uart_tx(uart_tx3),
							.clk_bps(clk_bps3),
							.bps_start(bps_start3)
						);


speed_setting		speed_tx4(	
							.clk(clk),
							.rst_n(rst_n),
							.bps_start(bps_start4),
							.clk_bps(clk_bps4)
						);
my_uart_tx			my_uart_tx4(		
							.clk(clk),
							.rst_n(rst_n),
							.rx_data(data4),
							.rx_int(uart_clk4),
							.uart_tx(uart_tx4),
							.clk_bps(clk_bps4),
							.bps_start(bps_start4)
						);




fdivision fdivision(
    .RESET(rst_n), 
    .F50M(clk), 
    .pulse1(uart_clk1), 
    .pulse2(uart_clk2), 
    .pulse3(uart_clk3), 
    .pulse4(uart_clk4), 
    .total_pulse_test(total_pulse_test)
    );						
endmodule