data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh
 line:19: before: "typedef"
1: b'%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:4: Cannot find include file: if_wishbone_types.svh\n`include "if_wishbone_types.svh" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim,data/full_repos/permissive/161356276/if_wishbone_types.svh\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim,data/full_repos/permissive/161356276/if_wishbone_types.svh.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim,data/full_repos/permissive/161356276/if_wishbone_types.svh.sv\n             if_wishbone_types.svh\n             if_wishbone_types.svh.v\n             if_wishbone_types.svh.sv\n             obj_dir/if_wishbone_types.svh\n             obj_dir/if_wishbone_types.svh.v\n             obj_dir/if_wishbone_types.svh.sv\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:6: Unsupported: virtual classes\nvirtual class CWishboneAccessor extends CBusAccessor;\n^~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:6: Unsupported: classes\nvirtual class CWishboneAccessor extends CBusAccessor;\n        ^~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:6: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nvirtual class CWishboneAccessor extends CBusAccessor;\n                                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:8: Unsupported: Static in this context\n   static int _null  = 0;\n   ^~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:9: syntax error, unexpected protected\n   protected wb_cycle_type_t m_cycle_type;\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:11: Unsupported: new constructor\n   function new();\n            ^~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:15: syntax error, unexpected virtual\n   virtual task set_mode(wb_cycle_type_t mode);\n           ^~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:15: syntax error, unexpected IDENTIFIER, expecting \')\'\n   virtual task set_mode(wb_cycle_type_t mode);\n                                         ^~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:31: syntax error, unexpected virtual\n   virtual task add_event(wba_sim_event_t evt, wba_sim_behavior_t behv, int dly_start, real prob, int rep_rate);\n           ^~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n   virtual task add_event(wba_sim_event_t evt, wba_sim_behavior_t behv, int dly_start, real prob, int rep_rate);\n                                          ^~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:31: syntax error, unexpected real, expecting IDENTIFIER or \'=\' or do or final\n   virtual task add_event(wba_sim_event_t evt, wba_sim_behavior_t behv, int dly_start, real prob, int rep_rate);\n                                                                                       ^~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:31: syntax error, unexpected int, expecting IDENTIFIER or \'=\' or do or final\n   virtual task add_event(wba_sim_event_t evt, wba_sim_behavior_t behv, int dly_start, real prob, int rep_rate);\n                                                                                                  ^~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:37: syntax error, unexpected IDENTIFIER, expecting \')\'\n   virtual task get(ref wb_cycle_t xfer);\n                                   ^~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:42: syntax error, unexpected IDENTIFIER, expecting \')\'\n   virtual task put(ref wb_cycle_t xfer);\n                                   ^~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:51: syntax error, unexpected virtual\n   virtual task writem(uint64_t addr[], uint64_t data[], int size = 4, ref int result = _null);\n           ^~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:51: syntax error, unexpected IDENTIFIER, expecting \')\'\n   virtual task writem(uint64_t addr[], uint64_t data[], int size = 4, ref int result = _null);\n                                ^~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:51: syntax error, unexpected ref, expecting IDENTIFIER or \'=\' or do or final\n   virtual task writem(uint64_t addr[], uint64_t data[], int size = 4, ref int result = _null);\n                                                                       ^~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:51: syntax error, unexpected \')\', expecting \',\' or \';\'\n   virtual task writem(uint64_t addr[], uint64_t data[], int size = 4, ref int result = _null);\n                                                                                             ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:55: syntax error, unexpected IDENTIFIER\n      cycle.ctype  = m_cycle_type;\n      ^~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:76: syntax error, unexpected IDENTIFIER, expecting \')\'\n   virtual task readm(uint64_t addr[], ref uint64_t data[],input int size = 4, ref int result = _null);\n                               ^~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:76: syntax error, unexpected ref, expecting IDENTIFIER or \'=\' or do or final\n   virtual task readm(uint64_t addr[], ref uint64_t data[],input int size = 4, ref int result = _null);\n                                                                               ^~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:76: syntax error, unexpected \')\', expecting \',\' or \';\'\n   virtual task readm(uint64_t addr[], ref uint64_t data[],input int size = 4, ref int result = _null);\n                                                                                                     ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:80: syntax error, unexpected IDENTIFIER\n      cycle.ctype  = m_cycle_type;\n      ^~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:101: syntax error, unexpected IDENTIFIER, expecting \')\'\n   virtual task read(uint64_t addr, ref uint64_t data, input int size = 4, ref int result = _null);\n                              ^~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:101: syntax error, unexpected ref, expecting IDENTIFIER or \'=\' or do or final\n   virtual task read(uint64_t addr, ref uint64_t data, input int size = 4, ref int result = _null);\n                                                                           ^~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:101: syntax error, unexpected \')\', expecting \',\' or \';\'\n   virtual task read(uint64_t addr, ref uint64_t data, input int size = 4, ref int result = _null);\n                                                                                                 ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:110: syntax error, unexpected IDENTIFIER, expecting \')\'\n   virtual task write(uint64_t addr, uint64_t data, int size = 4, ref int result = _null);\n                               ^~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:110: syntax error, unexpected ref, expecting IDENTIFIER or \'=\' or do or final\n   virtual task write(uint64_t addr, uint64_t data, int size = 4, ref int result = _null);\n                                                                  ^~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:110: syntax error, unexpected \')\', expecting \',\' or \';\'\n   virtual task write(uint64_t addr, uint64_t data, int size = 4, ref int result = _null);\n                                                                                        ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:122: Unsupported: Static in this context\nstatic int seed = 0;\n^~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/sim/if_wishbone_accessor.svh:126: Unsupported or unknown PLI call: $dist_uniform\n   rand_val  = real\'($dist_uniform(seed, 0, 1000)) / 1000.0;\n                     ^~~~~~~~~~~~~\n%Error: Exiting due to 32 error(s)\n'
function new();
      m_cycle_type  = CLASSIC;
   endfunction
function new();

      m_cycle_type  = CLASSIC;
   endfunction