data/full_repos/permissive/177039499/execution/stage.v
1: b'%Error: data/full_repos/permissive/177039499/execution/stage.v:5: Cannot find include file: execution/ALU.v\n`include "execution/ALU.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/177039499/execution,data/full_repos/permissive/177039499/execution/ALU.v\n             data/full_repos/permissive/177039499/execution,data/full_repos/permissive/177039499/execution/ALU.v.v\n             data/full_repos/permissive/177039499/execution,data/full_repos/permissive/177039499/execution/ALU.v.sv\n             execution/ALU.v\n             execution/ALU.v.v\n             execution/ALU.v.sv\n             obj_dir/execution/ALU.v\n             obj_dir/execution/ALU.v.v\n             obj_dir/execution/ALU.v.sv\n%Error: data/full_repos/permissive/177039499/execution/stage.v:6: Cannot find include file: aux-blocks.v\n`include "aux-blocks.v" \n         ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module stageEX(

    input  wire  [3:0] ALUOp,
    input  wire        NotEqual, IsBranch,
    input  wire [31:0] IDEX_ALUVal1,IDEX_ALUVal2,
    input  wire [31:0] IDEX_regRead2,

    input  wire [31:0] EXMEM_ForwardVal,

    input  wire [31:0] MEMWB_ForwardVal,

    input  wire  [1:0] forwardA,forwardB,forwardC,


	output wire [31:0] ALUResult,
	output wire [31:0] storeVal,

	output wire        BranchTaken
);




    wire [31:0] ALUVal1, ALUVal2;
    wire        Zero;



    assign BranchTaken = (Zero ^ NotEqual) & IsBranch;



    ALU_32bit ALU(ALUOp, ALUVal1, ALUVal2, ALUResult, Zero);



    mux_32bit_4in muxVal1(forwardA, IDEX_ALUVal1,  EXMEM_ForwardVal, MEMWB_ForwardVal, 32'b0, ALUVal1);
    mux_32bit_4in muxVal2(forwardB, IDEX_ALUVal2,  EXMEM_ForwardVal, MEMWB_ForwardVal, 32'b0, ALUVal2);
    mux_32bit_4in muxAddr(forwardC, IDEX_regRead2, EXMEM_ForwardVal, MEMWB_ForwardVal, 32'b0, storeVal);

endmodule
module stageEX(

    input  wire  [3:0] ALUOp,
    input  wire        NotEqual, IsBranch,
    input  wire [31:0] IDEX_ALUVal1,IDEX_ALUVal2,
    input  wire [31:0] IDEX_regRead2,

    input  wire [31:0] EXMEM_ForwardVal,

    input  wire [31:0] MEMWB_ForwardVal,

    input  wire  [1:0] forwardA,forwardB,forwardC,


	output wire [31:0] ALUResult,
	output wire [31:0] storeVal,

	output wire        BranchTaken
);





    wire [31:0] ALUVal1, ALUVal2;
    wire        Zero;



    assign BranchTaken = (Zero ^ NotEqual) & IsBranch;



    ALU_32bit ALU(ALUOp, ALUVal1, ALUVal2, ALUResult, Zero);



    mux_32bit_4in muxVal1(forwardA, IDEX_ALUVal1,  EXMEM_ForwardVal, MEMWB_ForwardVal, 32'b0, ALUVal1);
    mux_32bit_4in muxVal2(forwardB, IDEX_ALUVal2,  EXMEM_ForwardVal, MEMWB_ForwardVal, 32'b0, ALUVal2);
    mux_32bit_4in muxAddr(forwardC, IDEX_regRead2, EXMEM_ForwardVal, MEMWB_ForwardVal, 32'b0, storeVal);

endmodule