data/full_repos/permissive/148201731/rtl/inst_memory_controll/inst_memory_controll.v
data/verilator_xmls/d4d4fc76-a106-4e87-99e1-681fbcd406ed.xml
module inst_memory_controll
#(
   parameter DATA_WIDTH = 32,
   parameter DATA_ADDR_WIDTH = 32,      
   parameter SRAM_ADDR_WIDTH = 20,     
   parameter SRAM_DATA_WIDTH = 16      
)
(

   input clk,
   input rst_n,
   output data_rd_en,
   output data_wr_en,
   output [DATA_ADDR_WIDTH-1:0] data_addr,
   input [DATA_WIDTH-1:0] data_in,
   output [DATA_WIDTH-1:0] data_out,

   output   [SRAM_ADDR_WIDTH-1:0]    sram_addr,
   output   sram_ce_n,
   inout    [SRAM_DATA_WIDTH-1:0]   sram_dq,
   output   sram_lb_n,
   output   sram_oe_n,
   output   sram_ub_n,
   output   sram_we_n
);





















endmodule
module inst_memory_controll
#(
   parameter DATA_WIDTH = 32,
   parameter DATA_ADDR_WIDTH = 32,      
   parameter SRAM_ADDR_WIDTH = 20,     
   parameter SRAM_DATA_WIDTH = 16      
)
(

   input clk,
   input rst_n,
   output data_rd_en,
   output data_wr_en,
   output [DATA_ADDR_WIDTH-1:0] data_addr,
   input [DATA_WIDTH-1:0] data_in,
   output [DATA_WIDTH-1:0] data_out,

   output   [SRAM_ADDR_WIDTH-1:0]    sram_addr,
   output   sram_ce_n,
   inout    [SRAM_DATA_WIDTH-1:0]   sram_dq,
   output   sram_lb_n,
   output   sram_oe_n,
   output   sram_ub_n,
   output   sram_we_n
);






















endmodule