data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_mult_wide/nexus_mult_wide.v
 line:69: before: ")"
1: b"%Error: data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_mult_wide/nexus_mult_wide.v:43: Cannot find file containing module: 'MULTADDSUB9X9WIDE'\n    MULTADDSUB9X9WIDE # (\n    ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_mult_wide,data/full_repos/permissive/220229160/MULTADDSUB9X9WIDE\n             data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_mult_wide,data/full_repos/permissive/220229160/MULTADDSUB9X9WIDE.v\n             data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_mult_wide,data/full_repos/permissive/220229160/MULTADDSUB9X9WIDE.sv\n             MULTADDSUB9X9WIDE\n             MULTADDSUB9X9WIDE.v\n             MULTADDSUB9X9WIDE.sv\n             obj_dir/MULTADDSUB9X9WIDE\n             obj_dir/MULTADDSUB9X9WIDE.v\n             obj_dir/MULTADDSUB9X9WIDE.sv\n%Error: Exiting due to 1 error(s)\n"
module mult_wide (
    input  wire        CLK,
    input  wire [ 8:0] A0,
    input  wire [ 8:0] A1,
    input  wire [ 8:0] A2,
    input  wire [ 8:0] A3,
    input  wire [ 8:0] B0,
    input  wire [ 8:0] B1,
    input  wire [ 8:0] B2,
    input  wire [ 8:0] B3,
    input  wire [53:0] C,
    output wire [53:0] Z
);

    reg [8:0] ra0;
    always @(posedge CLK)
        ra0 <= A0;

    reg [8:0] rb0;
    always @(posedge CLK)
        rb0 <= B0;

    reg [8:0] rb2;
    always @(posedge CLK)
        rb2 <= B2;

    MULTADDSUB9X9WIDE # (
        .REGINPUTAB0("BYPASS"),
        .REGINPUTAB1("BYPASS"),
        .REGINPUTAB2("BYPASS"),
        .REGINPUTAB3("BYPASS"),
        .REGINPUTC("BYPASS"),
        .REGADDSUB("BYPASS"),
        .REGLOADC("BYPASS"),
        .REGLOADC2("BYPASS"),
        .REGPIPELINE("BYPASS"),
        .REGOUTPUT("REGISTER")
    ) mult (
        .A0 (ra0),
        .A1 (A1),
        .A2 (A2),
        .A3 (A3),
        .B0 (rb0),
        .B1 (B1),
        .B2 (rb2),
        .B3 (B3),
        .C  (C),
        .Z  (Z),

        .LOADC      (1'b0),
        .ADDSUB     (4'hF),
        .SIGNED     (1'b1),
    );

endmodule
module mult_wide (
    input  wire        CLK,
    input  wire [ 8:0] A0,
    input  wire [ 8:0] A1,
    input  wire [ 8:0] A2,
    input  wire [ 8:0] A3,
    input  wire [ 8:0] B0,
    input  wire [ 8:0] B1,
    input  wire [ 8:0] B2,
    input  wire [ 8:0] B3,
    input  wire [53:0] C,
    output wire [53:0] Z
);


    reg [8:0] ra0;
    always @(posedge CLK)
        ra0 <= A0;

    reg [8:0] rb0;
    always @(posedge CLK)
        rb0 <= B0;

    reg [8:0] rb2;
    always @(posedge CLK)
        rb2 <= B2;

    MULTADDSUB9X9WIDE # (
        .REGINPUTAB0("BYPASS"),
        .REGINPUTAB1("BYPASS"),
        .REGINPUTAB2("BYPASS"),
        .REGINPUTAB3("BYPASS"),
        .REGINPUTC("BYPASS"),
        .REGADDSUB("BYPASS"),
        .REGLOADC("BYPASS"),
        .REGLOADC2("BYPASS"),
        .REGPIPELINE("BYPASS"),
        .REGOUTPUT("REGISTER")
    ) mult (
        .A0 (ra0),
        .A1 (A1),
        .A2 (A2),
        .A3 (A3),
        .B0 (rb0),
        .B1 (B1),
        .B2 (rb2),
        .B3 (B3),
        .C  (C),
        .Z  (Z),

        .LOADC      (1'b0),
        .ADDSUB     (4'hF),
        .SIGNED     (1'b1),
    );

endmodule