data/full_repos/permissive/214491501/Oscilloscope_project/fifo_control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/214491501/Oscilloscope_project/fifo_control.v:24: Operator EQ expects 12 bits on the RHS, but RHS\'s CONST \'11\'h400\' generates 11 bits.\n                                                                                           : ... In instance fifo_control\n if(cnt == 11\'b10000000000 || gather_set == 2\'b00)  \n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214491501/Oscilloscope_project/fifo_control.v:53: Operator EQ expects 12 bits on the RHS, but RHS\'s CONST \'11\'h400\' generates 11 bits.\n                                                                                           : ... In instance fifo_control\n else if(cnt == 11\'b10000000000)  \n             ^~\n%Warning-WIDTH: data/full_repos/permissive/214491501/Oscilloscope_project/fifo_control.v:47: Operator EQ expects 12 bits on the RHS, but RHS\'s CONST \'11\'h200\' generates 11 bits.\n                                                                                           : ... In instance fifo_control\n else if(cnt == 11\'b01000000000)  \n             ^~\n%Warning-WIDTH: data/full_repos/permissive/214491501/Oscilloscope_project/fifo_control.v:40: Operator EQ expects 12 bits on the RHS, but RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                                           : ... In instance fifo_control\n begin if(cnt == 11\'b00000000000 && trigger_activation == 1 && fifo_2_empty == 1) \n              ^~\n%Warning-WIDTH: data/full_repos/permissive/214491501/Oscilloscope_project/fifo_control.v:80: Operator EQ expects 12 bits on the RHS, but RHS\'s CONST \'11\'h400\' generates 11 bits.\n                                                                                           : ... In instance fifo_control\n else if(cnt == 11\'b10000000000) \n             ^~\n%Warning-WIDTH: data/full_repos/permissive/214491501/Oscilloscope_project/fifo_control.v:74: Operator EQ expects 12 bits on the RHS, but RHS\'s CONST \'11\'h200\' generates 11 bits.\n                                                                                           : ... In instance fifo_control\n else if(cnt == 11\'b01000000000) \n             ^~\n%Warning-WIDTH: data/full_repos/permissive/214491501/Oscilloscope_project/fifo_control.v:67: Operator EQ expects 12 bits on the RHS, but RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                                           : ... In instance fifo_control\n begin if(cnt == 11\'b00000000000 && trigger_activation == 1 && fifo_1_empty == 1) \n              ^~\n%Error: Exiting due to 7 warning(s)\n'
module fifo_control(clk_20M,fifo_1_full,fifo_1_empty,fifo_2_empty,fifo_1_wr,fifo_1_rd,fifo_2_wr,fifo_2_rd,fifo_full_rst,gather_set,trigger_activation);

input clk_20M;
input fifo_1_full;
input fifo_1_empty;
input fifo_2_empty;
input[1:0] gather_set;
input trigger_activation;


output reg fifo_1_wr;
output reg fifo_1_rd;
output reg fifo_2_wr;
output reg fifo_2_rd;
output reg fifo_full_rst = 1'b1;


reg[11:0] cnt;
reg flag;


always @(posedge clk_20M) begin
	if(cnt == 11'b10000000000 || gather_set == 2'b00)
		cnt <= 0;
	else if(fifo_1_wr == 1)
		cnt <= cnt + 1'b1;
	end
	

	
always @(posedge clk_20M) begin
	case(gather_set)
	2'b00:
	begin
		fifo_full_rst <= 1;
		flag <= 0;
	end
	2'b01:
	begin	if(cnt == 11'b00000000000 && trigger_activation == 1 && fifo_2_empty == 1) 
		begin
			fifo_1_wr <= 1;
			fifo_1_rd <= 0;
			fifo_2_wr <= 0;
			fifo_full_rst <= 0;
		end
	else if(cnt == 11'b01000000000)
		begin
			fifo_1_wr <= 1;
			fifo_1_rd <= 1;
			fifo_2_wr <= 1;
		end
	else if(cnt == 11'b10000000000)
		begin
			fifo_1_wr <= 0;
			fifo_1_rd <= 1;
			fifo_2_wr <= 1;
		end
	else if(fifo_1_empty == 1 && fifo_2_empty == 0)
		begin
			fifo_1_wr <= 0;
			fifo_1_rd <= 0;
			fifo_2_wr <= 0;
		end
	end
	2'b10:
	begin	if(cnt == 11'b00000000000 && trigger_activation == 1 && fifo_1_empty == 1) 
		begin
			fifo_1_wr <= 1;
			fifo_1_rd <= 0;
			fifo_2_wr <= 0;
			fifo_full_rst <= 0;
		end
	else if(cnt == 11'b01000000000) 
		begin
			fifo_1_wr <= 1;
			fifo_1_rd <= 1;
			fifo_2_wr <= 1;
		end
	else if(cnt == 11'b10000000000) 
		begin
			fifo_1_wr <= 0;
			fifo_1_rd <= 1;
			fifo_2_wr <= 1;
		end
	else if(fifo_1_empty == 1 && fifo_2_empty == 0)
		begin
			fifo_1_wr <= 0;
			fifo_1_rd <= 0;
			fifo_2_wr <= 0;
		end
	end	
	default:
	begin
			fifo_1_wr <= 0;
			fifo_1_rd <= 0;
			fifo_2_wr <= 0;
	end
	endcase
end


always @(posedge clk_20M) begin
	if(fifo_2_empty == 0)
		fifo_2_rd <= 1;
	else
		fifo_2_rd <=0;
end


endmodule
module fifo_control(clk_20M,fifo_1_full,fifo_1_empty,fifo_2_empty,fifo_1_wr,fifo_1_rd,fifo_2_wr,fifo_2_rd,fifo_full_rst,gather_set,trigger_activation);


input clk_20M;
input fifo_1_full;
input fifo_1_empty;
input fifo_2_empty;
input[1:0] gather_set;
input trigger_activation;


output reg fifo_1_wr;
output reg fifo_1_rd;
output reg fifo_2_wr;
output reg fifo_2_rd;
output reg fifo_full_rst = 1'b1;


reg[11:0] cnt;
reg flag;


always @(posedge clk_20M) begin
	if(cnt == 11'b10000000000 || gather_set == 2'b00)
		cnt <= 0;
	else if(fifo_1_wr == 1)
		cnt <= cnt + 1'b1;
	end
	

	
always @(posedge clk_20M) begin
	case(gather_set)
	2'b00:
	begin
		fifo_full_rst <= 1;
		flag <= 0;
	end
	2'b01:
	begin	if(cnt == 11'b00000000000 && trigger_activation == 1 && fifo_2_empty == 1) 
		begin
			fifo_1_wr <= 1;
			fifo_1_rd <= 0;
			fifo_2_wr <= 0;
			fifo_full_rst <= 0;
		end
	else if(cnt == 11'b01000000000)
		begin
			fifo_1_wr <= 1;
			fifo_1_rd <= 1;
			fifo_2_wr <= 1;
		end
	else if(cnt == 11'b10000000000)
		begin
			fifo_1_wr <= 0;
			fifo_1_rd <= 1;
			fifo_2_wr <= 1;
		end
	else if(fifo_1_empty == 1 && fifo_2_empty == 0)
		begin
			fifo_1_wr <= 0;
			fifo_1_rd <= 0;
			fifo_2_wr <= 0;
		end
	end
	2'b10:
	begin	if(cnt == 11'b00000000000 && trigger_activation == 1 && fifo_1_empty == 1) 
		begin
			fifo_1_wr <= 1;
			fifo_1_rd <= 0;
			fifo_2_wr <= 0;
			fifo_full_rst <= 0;
		end
	else if(cnt == 11'b01000000000) 
		begin
			fifo_1_wr <= 1;
			fifo_1_rd <= 1;
			fifo_2_wr <= 1;
		end
	else if(cnt == 11'b10000000000) 
		begin
			fifo_1_wr <= 0;
			fifo_1_rd <= 1;
			fifo_2_wr <= 1;
		end
	else if(fifo_1_empty == 1 && fifo_2_empty == 0)
		begin
			fifo_1_wr <= 0;
			fifo_1_rd <= 0;
			fifo_2_wr <= 0;
		end
	end	
	default:
	begin
			fifo_1_wr <= 0;
			fifo_1_rd <= 0;
			fifo_2_wr <= 0;
	end
	endcase
end


always @(posedge clk_20M) begin
	if(fifo_2_empty == 0)
		fifo_2_rd <= 1;
	else
		fifo_2_rd <=0;
end


endmodule