data/full_repos/permissive/147690299/lab/17_comb_hex/rtl/board_terasic.sv
None: at end of input
1: b"%Error: data/full_repos/permissive/147690299/lab/17_comb_hex/rtl/board_terasic.sv:34: Cannot find file containing module: 'seven_seg_N'\n    seven_seg_N #(6) hex\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147690299/lab/17_comb_hex/rtl,data/full_repos/permissive/147690299/seven_seg_N\n             data/full_repos/permissive/147690299/lab/17_comb_hex/rtl,data/full_repos/permissive/147690299/seven_seg_N.v\n             data/full_repos/permissive/147690299/lab/17_comb_hex/rtl,data/full_repos/permissive/147690299/seven_seg_N.sv\n             seven_seg_N\n             seven_seg_N.v\n             seven_seg_N.sv\n             obj_dir/seven_seg_N\n             obj_dir/seven_seg_N.v\n             obj_dir/seven_seg_N.sv\n%Error: Exiting due to 1 error(s)\n"
module board_terasic
(
    input  [ 9:0] SW,
    output [ 9:0] LED,
    output [ 7:0] HEX0,
    output [ 7:0] HEX1,
    output [ 7:0] HEX2,
    output [ 7:0] HEX3,
    output [ 7:0] HEX4,
    output [ 7:0] HEX5 
);
    wire [23:0] data = { 14'b0, SW };


`ifndef USE_SYSTEM_VERILOG
    seven_seg_6 hex
    (
        .data ( data ),
        .hex0 ( HEX0 ),
        .hex1 ( HEX1 ),
        .hex2 ( HEX2 ),
        .hex3 ( HEX3 ),
        .hex4 ( HEX4 ),
        .hex5 ( HEX5 ) 
    );
`else

    wire [5:0][7:0] seg;
    assign { HEX5, HEX4, HEX3, HEX2, HEX1, HEX0 } = seg;

    seven_seg_N #(6) hex
    (
        .data   ( data ),
        .seg    ( seg  )
    );
`endif

    assign LED = 10'b0;

endmodule
module board_terasic
(
    input  [ 9:0] SW,
    output [ 9:0] LED,
    output [ 7:0] HEX0,
    output [ 7:0] HEX1,
    output [ 7:0] HEX2,
    output [ 7:0] HEX3,
    output [ 7:0] HEX4,
    output [ 7:0] HEX5 
);

    wire [23:0] data = { 14'b0, SW };


`ifndef USE_SYSTEM_VERILOG
    seven_seg_6 hex
    (
        .data ( data ),
        .hex0 ( HEX0 ),
        .hex1 ( HEX1 ),
        .hex2 ( HEX2 ),
        .hex3 ( HEX3 ),
        .hex4 ( HEX4 ),
        .hex5 ( HEX5 ) 
    );
`else

    wire [5:0][7:0] seg;
    assign { HEX5, HEX4, HEX3, HEX2, HEX1, HEX0 } = seg;

    seven_seg_N #(6) hex
    (
        .data   ( data ),
        .seg    ( seg  )
    );
`endif

    assign LED = 10'b0;

endmodule