data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_watchdog.v
1: b'%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_watchdog.v:45: Cannot find include file: openMSP430_defines.v\n`include "openMSP430_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/185287750/openmsp430/msp_core,data/full_repos/permissive/185287750/openMSP430_defines.v\n             data/full_repos/permissive/185287750/openmsp430/msp_core,data/full_repos/permissive/185287750/openMSP430_defines.v.v\n             data/full_repos/permissive/185287750/openmsp430/msp_core,data/full_repos/permissive/185287750/openMSP430_defines.v.sv\n             openMSP430_defines.v\n             openMSP430_defines.v.v\n             openMSP430_defines.v.sv\n             obj_dir/openMSP430_defines.v\n             obj_dir/openMSP430_defines.v.v\n             obj_dir/openMSP430_defines.v.sv\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_watchdog.v:566: Cannot find include file: openMSP430_undefines.v\n`include "openMSP430_undefines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module  omsp_watchdog (


    per_dout,
    wdt_irq,
    wdt_reset,
    wdt_wkup,
    wdtifg,
    wdtnmies,


    aclk,
    aclk_en,
    dbg_freeze,
    mclk,
    per_addr,
    per_din,
    per_en,
    per_we,
    por,
    puc_rst,
    scan_enable,
    scan_mode,
    smclk,
    smclk_en,
    wdtie,
    wdtifg_irq_clr,
    wdtifg_sw_clr,
    wdtifg_sw_set
);



output       [15:0] per_dout;
output              wdt_irq;
output              wdt_reset;
output              wdt_wkup;
output              wdtifg;
output              wdtnmies;



input               aclk;
input               aclk_en;
input               dbg_freeze;
input               mclk;
input        [13:0] per_addr;
input        [15:0] per_din;
input               per_en;
input         [1:0] per_we;
input               por;
input               puc_rst;
input               scan_enable;
input               scan_mode;
input               smclk;
input               smclk_en;
input               wdtie;
input               wdtifg_irq_clr;
input               wdtifg_sw_clr;
input               wdtifg_sw_set;







parameter       [14:0] BASE_ADDR   = 15'h0120;


parameter              DEC_WD      =  2;


parameter [DEC_WD-1:0] WDTCTL      = 'h0;


parameter              DEC_SZ      =  (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};


parameter [DEC_SZ-1:0] WDTCTL_D    = (BASE_REG << WDTCTL);







wire              reg_sel   =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);


wire [DEC_WD-1:0] reg_addr  =  {per_addr[DEC_WD-2:0], 1'b0};


wire [DEC_SZ-1:0] reg_dec   =  (WDTCTL_D & {DEC_SZ{(reg_addr==WDTCTL)}});


wire              reg_write =  |per_we & reg_sel;
wire              reg_read  = ~|per_we & reg_sel;


wire [DEC_SZ-1:0] reg_wr    = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd    = reg_dec & {DEC_SZ{reg_read}};










reg  [7:0] wdtctl;

wire       wdtctl_wr = reg_wr[WDTCTL];

`ifdef CLOCK_GATING
wire       mclk_wdtctl;
omsp_clock_gate clock_gate_wdtctl (.gclk(mclk_wdtctl),
                                   .clk (mclk), .enable(wdtctl_wr), .scan_enable(scan_enable));
`else
wire       UNUSED_scan_enable = scan_enable;
wire       mclk_wdtctl        = mclk;
`endif

`ifdef NMI
parameter [7:0] WDTNMIES_MASK = 8'h40;
`else
parameter [7:0] WDTNMIES_MASK = 8'h00;
`endif

`ifdef ASIC_CLOCKING
  `ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_MASK  = 8'h04;
  `else
parameter [7:0] WDTSSEL_MASK  = 8'h00;
  `endif
`else
parameter [7:0] WDTSSEL_MASK  = 8'h04;
`endif

parameter [7:0] WDTCTL_MASK   = (8'b1001_0011 | WDTSSEL_MASK | WDTNMIES_MASK);

always @ (posedge mclk_wdtctl or posedge puc_rst)
  if (puc_rst)        wdtctl <=  8'h00;
`ifdef CLOCK_GATING
  else                wdtctl <=  per_din[7:0] & WDTCTL_MASK;
`else
  else if (wdtctl_wr) wdtctl <=  per_din[7:0] & WDTCTL_MASK;
`endif

wire       wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
wire       wdttmsel    = wdtctl[4];
wire       wdtnmies    = wdtctl[6];






`ifdef NMI
parameter [7:0] WDTNMI_RD_MASK  = 8'h20;
`else
parameter [7:0] WDTNMI_RD_MASK  = 8'h00;
`endif
`ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_RD_MASK = 8'h00;
`else
  `ifdef WATCHDOG_NOMUX_ACLK
parameter [7:0] WDTSSEL_RD_MASK = 8'h04;
  `else
parameter [7:0] WDTSSEL_RD_MASK = 8'h00;
  `endif
`endif
parameter [7:0] WDTCTL_RD_MASK  = WDTNMI_RD_MASK | WDTSSEL_RD_MASK;


wire [15:0] wdtctl_rd  = {8'h69, wdtctl | WDTCTL_RD_MASK} & {16{reg_rd[WDTCTL]}};
wire [15:0] per_dout   =  wdtctl_rd;





`ifdef ASIC_CLOCKING



wire wdt_clk;

`ifdef WATCHDOG_MUX
omsp_clock_mux clock_mux_watchdog (
   .clk_out   (wdt_clk),
   .clk_in0   (smclk),
   .clk_in1   (aclk),
   .reset     (puc_rst),
   .scan_mode (scan_mode),
   .select_in (wdtctl[2])
);
`else
  `ifdef WATCHDOG_NOMUX_ACLK
     assign wdt_clk      = aclk;
     wire   UNUSED_smclk = smclk;
  `else
     wire   UNUSED_aclk  = aclk;
     assign wdt_clk      = smclk;
  `endif
`endif




wire wdt_rst_noscan;
wire wdt_rst;


omsp_sync_reset sync_reset_por (
    .rst_s        (wdt_rst_noscan),
    .clk          (wdt_clk),
    .rst_a        (puc_rst)
);


omsp_scan_mux scan_mux_wdt_rst (
    .scan_mode    (scan_mode),
    .data_in_scan (puc_rst),
    .data_in_func (wdt_rst_noscan),
    .data_out     (wdt_rst)
);






reg        wdtcnt_clr_toggle;
wire       wdtcnt_clr_detect = (wdtctl_wr & per_din[3]);
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)                wdtcnt_clr_toggle <= 1'b0;
  else if (wdtcnt_clr_detect) wdtcnt_clr_toggle <= ~wdtcnt_clr_toggle;


wire wdtcnt_clr_sync;
omsp_sync_cell sync_cell_wdtcnt_clr (
    .data_out  (wdtcnt_clr_sync),
    .data_in   (wdtcnt_clr_toggle),
    .clk       (wdt_clk),
    .rst       (wdt_rst)
);


reg wdtcnt_clr_sync_dly;
always @ (posedge wdt_clk or posedge wdt_rst)
  if (wdt_rst)  wdtcnt_clr_sync_dly <= 1'b0;
  else          wdtcnt_clr_sync_dly <= wdtcnt_clr_sync;

wire wdtqn_edge;
wire wdtcnt_clr = (wdtcnt_clr_sync ^ wdtcnt_clr_sync_dly) | wdtqn_edge;




wire wdtcnt_incr;

omsp_sync_cell sync_cell_wdtcnt_incr (
    .data_out  (wdtcnt_incr),
    .data_in   (~wdtctl[7] & ~dbg_freeze),
    .clk       (wdt_clk),
    .rst       (wdt_rst)
);




reg  [15:0] wdtcnt;

wire [15:0] wdtcnt_nxt  = wdtcnt+16'h0001;

`ifdef CLOCK_GATING
wire       wdtcnt_en   = wdtcnt_clr | wdtcnt_incr;
wire       wdt_clk_cnt;
omsp_clock_gate clock_gate_wdtcnt (.gclk(wdt_clk_cnt),
                                   .clk (wdt_clk), .enable(wdtcnt_en), .scan_enable(scan_enable));
`else
wire       wdt_clk_cnt = wdt_clk;
`endif

always @ (posedge wdt_clk_cnt or posedge wdt_rst)
  if (wdt_rst)           wdtcnt <= 16'h0000;
  else if (wdtcnt_clr)   wdtcnt <= 16'h0000;
`ifdef CLOCK_GATING
  else                   wdtcnt <= wdtcnt_nxt;
`else
  else if (wdtcnt_incr)  wdtcnt <= wdtcnt_nxt;
`endif








reg [1:0] wdtisx_s;
reg [1:0] wdtisx_ss;
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
  if (wdt_rst)
    begin
       wdtisx_s  <=  2'h0;
       wdtisx_ss <=  2'h0;
    end
  else
    begin
       wdtisx_s  <=  wdtctl[1:0];
       wdtisx_ss <=  wdtisx_s;
    end




reg        wdtqn;

always @(wdtisx_ss or wdtcnt_nxt)
    case(wdtisx_ss)
      2'b00  : wdtqn =  wdtcnt_nxt[15];
      2'b01  : wdtqn =  wdtcnt_nxt[13];
      2'b10  : wdtqn =  wdtcnt_nxt[9];
      default: wdtqn =  wdtcnt_nxt[6];
    endcase






assign     wdtqn_edge =  (wdtqn & wdtcnt_incr);


reg        wdt_evt_toggle;
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
  if (wdt_rst)         wdt_evt_toggle <= 1'b0;
  else if (wdtqn_edge) wdt_evt_toggle <= ~wdt_evt_toggle;


wire       wdt_evt_toggle_sync;
omsp_sync_cell sync_cell_wdt_evt (
    .data_out  (wdt_evt_toggle_sync),
    .data_in   (wdt_evt_toggle),
    .clk       (mclk),
    .rst       (puc_rst)
);


reg        wdt_evt_toggle_sync_dly;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) wdt_evt_toggle_sync_dly <= 1'b0;
  else         wdt_evt_toggle_sync_dly <= wdt_evt_toggle_sync;

wire       wdtifg_evt =  (wdt_evt_toggle_sync_dly ^ wdt_evt_toggle_sync) | wdtpw_error;






reg  wdtifg_clr_reg;
wire wdtifg_clr;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) wdtifg_clr_reg <= 1'b1;
  else         wdtifg_clr_reg <= wdtifg_clr;


reg  wdtqn_edge_reg;
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
  if (wdt_rst) wdtqn_edge_reg <= 1'b0;
  else         wdtqn_edge_reg <= wdtqn_edge;


wire wdt_wkup_pre;
omsp_wakeup_cell wakeup_cell_wdog (
                                   .wkup_out   (wdt_wkup_pre),
                                   .scan_clk   (mclk),
                                   .scan_mode  (scan_mode),
                                   .scan_rst   (puc_rst),
                                   .wkup_clear (wdtifg_clr_reg),
                                   .wkup_event (wdtqn_edge_reg)
);




reg  wdt_wkup_en;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) wdt_wkup_en <= 1'b0;
  else         wdt_wkup_en <= ~wdtctl[7] & (~wdttmsel | (wdttmsel & wdtie));


wire wdt_wkup;
omsp_and_gate and_wdt_wkup (.y(wdt_wkup), .a(wdt_wkup_pre), .b(wdt_wkup_en));




reg        wdtifg;

wire       wdtifg_set =  wdtifg_evt                  |  wdtifg_sw_set;
assign     wdtifg_clr =  (wdtifg_irq_clr & wdttmsel) |  wdtifg_sw_clr;

always @ (posedge mclk or posedge por)
  if (por)             wdtifg <=  1'b0;
  else if (wdtifg_set) wdtifg <=  1'b1;
  else if (wdtifg_clr) wdtifg <=  1'b0;




wire    wdt_irq       = wdttmsel & wdtifg & wdtie;




reg     wdt_reset;

always @ (posedge mclk or posedge por)
  if (por) wdt_reset <= 1'b0;
  else     wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);



wire        UNUSED_smclk_en = smclk_en;
wire        UNUSED_aclk_en  = aclk_en;





`else



wire  clk_src_en = wdtctl[2] ? aclk_en : smclk_en;




reg [15:0] wdtcnt;

wire        wdtifg_evt;
wire        wdtcnt_clr  = (wdtctl_wr & per_din[3]) | wdtifg_evt;
wire        wdtcnt_incr = ~wdtctl[7] & clk_src_en & ~dbg_freeze;

wire [15:0] wdtcnt_nxt  = wdtcnt+16'h0001;

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)           wdtcnt <= 16'h0000;
  else if (wdtcnt_clr)   wdtcnt <= 16'h0000;
  else if (wdtcnt_incr)  wdtcnt <= wdtcnt_nxt;




reg        wdtqn;

always @(wdtctl or wdtcnt_nxt)
    case(wdtctl[1:0])
      2'b00  : wdtqn =  wdtcnt_nxt[15];
      2'b01  : wdtqn =  wdtcnt_nxt[13];
      2'b10  : wdtqn =  wdtcnt_nxt[9];
      default: wdtqn =  wdtcnt_nxt[6];
    endcase





assign     wdtifg_evt =  (wdtqn & wdtcnt_incr) | wdtpw_error;




reg        wdtifg;

wire       wdtifg_set =  wdtifg_evt                  |  wdtifg_sw_set;
wire       wdtifg_clr =  (wdtifg_irq_clr & wdttmsel) |  wdtifg_sw_clr;

always @ (posedge mclk or posedge por)
  if (por)             wdtifg <=  1'b0;
  else if (wdtifg_set) wdtifg <=  1'b1;
  else if (wdtifg_clr) wdtifg <=  1'b0;




wire    wdt_irq       = wdttmsel & wdtifg & wdtie;
wire    wdt_wkup      =  1'b0;




reg     wdt_reset;

always @ (posedge mclk or posedge por)
  if (por) wdt_reset <= 1'b0;
  else     wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);



wire        UNUSED_scan_mode = scan_mode;
wire        UNUSED_smclk     = smclk;
wire        UNUSED_aclk      = aclk;
`endif
wire [15:0] UNUSED_per_din   = per_din;

endmodule
module  omsp_watchdog (


    per_dout,
    wdt_irq,
    wdt_reset,
    wdt_wkup,
    wdtifg,
    wdtnmies,


    aclk,
    aclk_en,
    dbg_freeze,
    mclk,
    per_addr,
    per_din,
    per_en,
    per_we,
    por,
    puc_rst,
    scan_enable,
    scan_mode,
    smclk,
    smclk_en,
    wdtie,
    wdtifg_irq_clr,
    wdtifg_sw_clr,
    wdtifg_sw_set
);




output       [15:0] per_dout;
output              wdt_irq;
output              wdt_reset;
output              wdt_wkup;
output              wdtifg;
output              wdtnmies;



input               aclk;
input               aclk_en;
input               dbg_freeze;
input               mclk;
input        [13:0] per_addr;
input        [15:0] per_din;
input               per_en;
input         [1:0] per_we;
input               por;
input               puc_rst;
input               scan_enable;
input               scan_mode;
input               smclk;
input               smclk_en;
input               wdtie;
input               wdtifg_irq_clr;
input               wdtifg_sw_clr;
input               wdtifg_sw_set;







parameter       [14:0] BASE_ADDR   = 15'h0120;


parameter              DEC_WD      =  2;


parameter [DEC_WD-1:0] WDTCTL      = 'h0;


parameter              DEC_SZ      =  (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};


parameter [DEC_SZ-1:0] WDTCTL_D    = (BASE_REG << WDTCTL);







wire              reg_sel   =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);


wire [DEC_WD-1:0] reg_addr  =  {per_addr[DEC_WD-2:0], 1'b0};


wire [DEC_SZ-1:0] reg_dec   =  (WDTCTL_D & {DEC_SZ{(reg_addr==WDTCTL)}});


wire              reg_write =  |per_we & reg_sel;
wire              reg_read  = ~|per_we & reg_sel;


wire [DEC_SZ-1:0] reg_wr    = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd    = reg_dec & {DEC_SZ{reg_read}};










reg  [7:0] wdtctl;

wire       wdtctl_wr = reg_wr[WDTCTL];

`ifdef CLOCK_GATING
wire       mclk_wdtctl;
omsp_clock_gate clock_gate_wdtctl (.gclk(mclk_wdtctl),
                                   .clk (mclk), .enable(wdtctl_wr), .scan_enable(scan_enable));
`else
wire       UNUSED_scan_enable = scan_enable;
wire       mclk_wdtctl        = mclk;
`endif

`ifdef NMI
parameter [7:0] WDTNMIES_MASK = 8'h40;
`else
parameter [7:0] WDTNMIES_MASK = 8'h00;
`endif

`ifdef ASIC_CLOCKING
  `ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_MASK  = 8'h04;
  `else
parameter [7:0] WDTSSEL_MASK  = 8'h00;
  `endif
`else
parameter [7:0] WDTSSEL_MASK  = 8'h04;
`endif

parameter [7:0] WDTCTL_MASK   = (8'b1001_0011 | WDTSSEL_MASK | WDTNMIES_MASK);

always @ (posedge mclk_wdtctl or posedge puc_rst)
  if (puc_rst)        wdtctl <=  8'h00;
`ifdef CLOCK_GATING
  else                wdtctl <=  per_din[7:0] & WDTCTL_MASK;
`else
  else if (wdtctl_wr) wdtctl <=  per_din[7:0] & WDTCTL_MASK;
`endif

wire       wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
wire       wdttmsel    = wdtctl[4];
wire       wdtnmies    = wdtctl[6];






`ifdef NMI
parameter [7:0] WDTNMI_RD_MASK  = 8'h20;
`else
parameter [7:0] WDTNMI_RD_MASK  = 8'h00;
`endif
`ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_RD_MASK = 8'h00;
`else
  `ifdef WATCHDOG_NOMUX_ACLK
parameter [7:0] WDTSSEL_RD_MASK = 8'h04;
  `else
parameter [7:0] WDTSSEL_RD_MASK = 8'h00;
  `endif
`endif
parameter [7:0] WDTCTL_RD_MASK  = WDTNMI_RD_MASK | WDTSSEL_RD_MASK;


wire [15:0] wdtctl_rd  = {8'h69, wdtctl | WDTCTL_RD_MASK} & {16{reg_rd[WDTCTL]}};
wire [15:0] per_dout   =  wdtctl_rd;





`ifdef ASIC_CLOCKING



wire wdt_clk;

`ifdef WATCHDOG_MUX
omsp_clock_mux clock_mux_watchdog (
   .clk_out   (wdt_clk),
   .clk_in0   (smclk),
   .clk_in1   (aclk),
   .reset     (puc_rst),
   .scan_mode (scan_mode),
   .select_in (wdtctl[2])
);
`else
  `ifdef WATCHDOG_NOMUX_ACLK
     assign wdt_clk      = aclk;
     wire   UNUSED_smclk = smclk;
  `else
     wire   UNUSED_aclk  = aclk;
     assign wdt_clk      = smclk;
  `endif
`endif




wire wdt_rst_noscan;
wire wdt_rst;


omsp_sync_reset sync_reset_por (
    .rst_s        (wdt_rst_noscan),
    .clk          (wdt_clk),
    .rst_a        (puc_rst)
);


omsp_scan_mux scan_mux_wdt_rst (
    .scan_mode    (scan_mode),
    .data_in_scan (puc_rst),
    .data_in_func (wdt_rst_noscan),
    .data_out     (wdt_rst)
);






reg        wdtcnt_clr_toggle;
wire       wdtcnt_clr_detect = (wdtctl_wr & per_din[3]);
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)                wdtcnt_clr_toggle <= 1'b0;
  else if (wdtcnt_clr_detect) wdtcnt_clr_toggle <= ~wdtcnt_clr_toggle;


wire wdtcnt_clr_sync;
omsp_sync_cell sync_cell_wdtcnt_clr (
    .data_out  (wdtcnt_clr_sync),
    .data_in   (wdtcnt_clr_toggle),
    .clk       (wdt_clk),
    .rst       (wdt_rst)
);


reg wdtcnt_clr_sync_dly;
always @ (posedge wdt_clk or posedge wdt_rst)
  if (wdt_rst)  wdtcnt_clr_sync_dly <= 1'b0;
  else          wdtcnt_clr_sync_dly <= wdtcnt_clr_sync;

wire wdtqn_edge;
wire wdtcnt_clr = (wdtcnt_clr_sync ^ wdtcnt_clr_sync_dly) | wdtqn_edge;




wire wdtcnt_incr;

omsp_sync_cell sync_cell_wdtcnt_incr (
    .data_out  (wdtcnt_incr),
    .data_in   (~wdtctl[7] & ~dbg_freeze),
    .clk       (wdt_clk),
    .rst       (wdt_rst)
);




reg  [15:0] wdtcnt;

wire [15:0] wdtcnt_nxt  = wdtcnt+16'h0001;

`ifdef CLOCK_GATING
wire       wdtcnt_en   = wdtcnt_clr | wdtcnt_incr;
wire       wdt_clk_cnt;
omsp_clock_gate clock_gate_wdtcnt (.gclk(wdt_clk_cnt),
                                   .clk (wdt_clk), .enable(wdtcnt_en), .scan_enable(scan_enable));
`else
wire       wdt_clk_cnt = wdt_clk;
`endif

always @ (posedge wdt_clk_cnt or posedge wdt_rst)
  if (wdt_rst)           wdtcnt <= 16'h0000;
  else if (wdtcnt_clr)   wdtcnt <= 16'h0000;
`ifdef CLOCK_GATING
  else                   wdtcnt <= wdtcnt_nxt;
`else
  else if (wdtcnt_incr)  wdtcnt <= wdtcnt_nxt;
`endif








reg [1:0] wdtisx_s;
reg [1:0] wdtisx_ss;
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
  if (wdt_rst)
    begin
       wdtisx_s  <=  2'h0;
       wdtisx_ss <=  2'h0;
    end
  else
    begin
       wdtisx_s  <=  wdtctl[1:0];
       wdtisx_ss <=  wdtisx_s;
    end




reg        wdtqn;

always @(wdtisx_ss or wdtcnt_nxt)
    case(wdtisx_ss)
      2'b00  : wdtqn =  wdtcnt_nxt[15];
      2'b01  : wdtqn =  wdtcnt_nxt[13];
      2'b10  : wdtqn =  wdtcnt_nxt[9];
      default: wdtqn =  wdtcnt_nxt[6];
    endcase






assign     wdtqn_edge =  (wdtqn & wdtcnt_incr);


reg        wdt_evt_toggle;
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
  if (wdt_rst)         wdt_evt_toggle <= 1'b0;
  else if (wdtqn_edge) wdt_evt_toggle <= ~wdt_evt_toggle;


wire       wdt_evt_toggle_sync;
omsp_sync_cell sync_cell_wdt_evt (
    .data_out  (wdt_evt_toggle_sync),
    .data_in   (wdt_evt_toggle),
    .clk       (mclk),
    .rst       (puc_rst)
);


reg        wdt_evt_toggle_sync_dly;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) wdt_evt_toggle_sync_dly <= 1'b0;
  else         wdt_evt_toggle_sync_dly <= wdt_evt_toggle_sync;

wire       wdtifg_evt =  (wdt_evt_toggle_sync_dly ^ wdt_evt_toggle_sync) | wdtpw_error;






reg  wdtifg_clr_reg;
wire wdtifg_clr;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) wdtifg_clr_reg <= 1'b1;
  else         wdtifg_clr_reg <= wdtifg_clr;


reg  wdtqn_edge_reg;
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
  if (wdt_rst) wdtqn_edge_reg <= 1'b0;
  else         wdtqn_edge_reg <= wdtqn_edge;


wire wdt_wkup_pre;
omsp_wakeup_cell wakeup_cell_wdog (
                                   .wkup_out   (wdt_wkup_pre),
                                   .scan_clk   (mclk),
                                   .scan_mode  (scan_mode),
                                   .scan_rst   (puc_rst),
                                   .wkup_clear (wdtifg_clr_reg),
                                   .wkup_event (wdtqn_edge_reg)
);




reg  wdt_wkup_en;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) wdt_wkup_en <= 1'b0;
  else         wdt_wkup_en <= ~wdtctl[7] & (~wdttmsel | (wdttmsel & wdtie));


wire wdt_wkup;
omsp_and_gate and_wdt_wkup (.y(wdt_wkup), .a(wdt_wkup_pre), .b(wdt_wkup_en));




reg        wdtifg;

wire       wdtifg_set =  wdtifg_evt                  |  wdtifg_sw_set;
assign     wdtifg_clr =  (wdtifg_irq_clr & wdttmsel) |  wdtifg_sw_clr;

always @ (posedge mclk or posedge por)
  if (por)             wdtifg <=  1'b0;
  else if (wdtifg_set) wdtifg <=  1'b1;
  else if (wdtifg_clr) wdtifg <=  1'b0;




wire    wdt_irq       = wdttmsel & wdtifg & wdtie;




reg     wdt_reset;

always @ (posedge mclk or posedge por)
  if (por) wdt_reset <= 1'b0;
  else     wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);



wire        UNUSED_smclk_en = smclk_en;
wire        UNUSED_aclk_en  = aclk_en;





`else



wire  clk_src_en = wdtctl[2] ? aclk_en : smclk_en;




reg [15:0] wdtcnt;

wire        wdtifg_evt;
wire        wdtcnt_clr  = (wdtctl_wr & per_din[3]) | wdtifg_evt;
wire        wdtcnt_incr = ~wdtctl[7] & clk_src_en & ~dbg_freeze;

wire [15:0] wdtcnt_nxt  = wdtcnt+16'h0001;

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)           wdtcnt <= 16'h0000;
  else if (wdtcnt_clr)   wdtcnt <= 16'h0000;
  else if (wdtcnt_incr)  wdtcnt <= wdtcnt_nxt;




reg        wdtqn;

always @(wdtctl or wdtcnt_nxt)
    case(wdtctl[1:0])
      2'b00  : wdtqn =  wdtcnt_nxt[15];
      2'b01  : wdtqn =  wdtcnt_nxt[13];
      2'b10  : wdtqn =  wdtcnt_nxt[9];
      default: wdtqn =  wdtcnt_nxt[6];
    endcase





assign     wdtifg_evt =  (wdtqn & wdtcnt_incr) | wdtpw_error;




reg        wdtifg;

wire       wdtifg_set =  wdtifg_evt                  |  wdtifg_sw_set;
wire       wdtifg_clr =  (wdtifg_irq_clr & wdttmsel) |  wdtifg_sw_clr;

always @ (posedge mclk or posedge por)
  if (por)             wdtifg <=  1'b0;
  else if (wdtifg_set) wdtifg <=  1'b1;
  else if (wdtifg_clr) wdtifg <=  1'b0;




wire    wdt_irq       = wdttmsel & wdtifg & wdtie;
wire    wdt_wkup      =  1'b0;




reg     wdt_reset;

always @ (posedge mclk or posedge por)
  if (por) wdt_reset <= 1'b0;
  else     wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);



wire        UNUSED_scan_mode = scan_mode;
wire        UNUSED_smclk     = smclk;
wire        UNUSED_aclk      = aclk;
`endif
wire [15:0] UNUSED_per_din   = per_din;

endmodule