data/full_repos/permissive/19591557/modules/uart/spio_uart_baud_gen.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/19591557/modules/uart/spio_uart_baud_gen.v:8: Cannot find include file: spio_uart_common.h\n`include "spio_uart_common.h" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/modules/uart,data/full_repos/permissive/19591557/spio_uart_common.h\n             data/full_repos/permissive/19591557/modules/uart,data/full_repos/permissive/19591557/spio_uart_common.h.v\n             data/full_repos/permissive/19591557/modules/uart,data/full_repos/permissive/19591557/spio_uart_common.h.sv\n             spio_uart_common.h\n             spio_uart_common.h.v\n             spio_uart_common.h.sv\n             obj_dir/spio_uart_common.h\n             obj_dir/spio_uart_common.h.v\n             obj_dir/spio_uart_common.h.sv\n%Error: Exiting due to 1 error(s)\n'
module spio_uart_baud_gen#(
                            parameter PERIOD = 100


                          , parameter NUM_BITS = 7
                          )
                          (
                            input wire CLK_IN

                          , input wire RESET_IN

                          , output wire BAUD_PULSE_OUT



                          , output wire SUBSAMPLE_PULSE_OUT
                          );


reg [NUM_BITS-1:0] counter_i;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		counter_i <= PERIOD-1;
	else
		if (counter_i == 0)
			counter_i <= PERIOD-1;
		else
			counter_i <= counter_i - 1;

assign BAUD_PULSE_OUT = counter_i == {NUM_BITS{1'b0}};


reg [NUM_BITS-3-1:0] counter8_i;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		counter8_i <= (PERIOD>>3)-1;
	else
		if (counter8_i == 0)
			counter8_i <= (PERIOD>>3)-1;
		else
			counter8_i <= counter8_i - 1;

assign SUBSAMPLE_PULSE_OUT = counter8_i == {(NUM_BITS-3){1'b0}};

endmodule
module spio_uart_baud_gen#(
                            parameter PERIOD = 100


                          , parameter NUM_BITS = 7
                          )
                          (
                            input wire CLK_IN

                          , input wire RESET_IN

                          , output wire BAUD_PULSE_OUT



                          , output wire SUBSAMPLE_PULSE_OUT
                          );



reg [NUM_BITS-1:0] counter_i;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		counter_i <= PERIOD-1;
	else
		if (counter_i == 0)
			counter_i <= PERIOD-1;
		else
			counter_i <= counter_i - 1;

assign BAUD_PULSE_OUT = counter_i == {NUM_BITS{1'b0}};


reg [NUM_BITS-3-1:0] counter8_i;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		counter8_i <= (PERIOD>>3)-1;
	else
		if (counter8_i == 0)
			counter8_i <= (PERIOD>>3)-1;
		else
			counter8_i <= counter8_i - 1;

assign SUBSAMPLE_PULSE_OUT = counter8_i == {(NUM_BITS-3){1'b0}};

endmodule