data/full_repos/permissive/148200700/Quartus/designFiles/ip/KBandIPsubPro/KBandIPsubPro_onchip_mem_FPGA_Slave/KBandIPsubPro_onchip_mem_FPGA_Slave_bb.v
data/verilator_xmls/cd102263-e178-40ce-af26-77d87afe6f4c.xml
module KBandIPsubPro_onchip_mem_FPGA_Slave (
		input  wire         clk,
		input  wire [13:0]  address,
		input  wire         clken,
		input  wire         chipselect,
		input  wire         write,
		output wire [127:0] readdata,
		input  wire [127:0] writedata,
		input  wire [15:0]  byteenable,
		input  wire         reset,
		input  wire         reset_req
	);
endmodule
module KBandIPsubPro_onchip_mem_FPGA_Slave (
		input  wire         clk,
		input  wire [13:0]  address,
		input  wire         clken,
		input  wire         chipselect,
		input  wire         write,
		output wire [127:0] readdata,
		input  wire [127:0] writedata,
		input  wire [15:0]  byteenable,
		input  wire         reset,
		input  wire         reset_req
	);

endmodule