data/full_repos/permissive/132220215/JK_FF.v
1: b"%Error: data/full_repos/permissive/132220215/JK_FF.v:9: Duplicate declaration of signal: 'Q'\n                                                      : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  reg Q;\n      ^\n        data/full_repos/permissive/132220215/JK_FF.v:4: ... Location of original declaration\nmodule jk_ff(output Q,\n                    ^\n%Error: Exiting due to 1 error(s)\n"
module jk_ff(output Q,
	     output Q_b,
	     input J,
	     input K,
	     input clk);
  reg Q;
  assign Q_b = ~Q;

  always @(posedge clk)
  begin
	  case({J,K})
		  {1'b0,1'b1} : Q <= 1'b0;
		  {1'b1,1'b0} : Q <= 1'b1;
		  {1'b1,1'b1} :
			  if(Q == 1'b0)
				  Q <= 1'b1;
			  else
				  Q <= 1'b0;
	  endcase
  end
  
endmodule
module jk_ff(output Q,
	     output Q_b,
	     input J,
	     input K,
	     input clk);

  reg Q;
  assign Q_b = ~Q;

  always @(posedge clk)
  begin
	  case({J,K})
		  {1'b0,1'b1} : Q <= 1'b0;
		  {1'b1,1'b0} : Q <= 1'b1;
		  {1'b1,1'b1} :
			  if(Q == 1'b0)
				  Q <= 1'b1;
			  else
				  Q <= 1'b0;
	  endcase
  end
  
endmodule