data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:52: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'int_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                int_enable_wire = 1'b1;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:53: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'vec_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                vec_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:54: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'lsu_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                lsu_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:55: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'bru_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                bru_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:57: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'int_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                int_uop = exec_uop_in;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:58: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'vec_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                vec_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:59: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'lsu_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                lsu_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:60: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'bru_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                bru_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:64: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'int_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                int_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:65: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'vec_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                vec_enable_wire = 1'b1;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:66: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'lsu_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                lsu_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:67: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'bru_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                bru_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:69: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'int_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                int_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:70: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'vec_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                vec_uop = exec_uop_in;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:71: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'lsu_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                lsu_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:72: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'bru_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                bru_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:76: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'int_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                int_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:77: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'vec_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                vec_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:78: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'lsu_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                lsu_enable_wire = 1'b1;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:79: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'bru_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                bru_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:81: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'int_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                int_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:82: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'vec_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                vec_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:83: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'lsu_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                lsu_uop = exec_uop_in;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:84: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'bru_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                bru_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:88: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'int_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                int_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:89: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'vec_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                vec_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:90: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'lsu_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                lsu_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:91: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'bru_enable_wire'\n                                                                                    : ... In instance ISSUE_UNIT\n                bru_enable_wire = 1'b1;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:93: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'int_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                int_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:94: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'vec_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                vec_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:95: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'lsu_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                lsu_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:96: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'bru_uop'\n                                                                                    : ... In instance ISSUE_UNIT\n                bru_uop = exec_uop_in;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:100: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'int_enable_wire'\n                                                                                     : ... In instance ISSUE_UNIT\n                int_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:101: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'vec_enable_wire'\n                                                                                     : ... In instance ISSUE_UNIT\n                vec_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:102: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'lsu_enable_wire'\n                                                                                     : ... In instance ISSUE_UNIT\n                lsu_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:103: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'bru_enable_wire'\n                                                                                     : ... In instance ISSUE_UNIT\n                bru_enable_wire = 1'b0;\n                ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:105: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'int_uop'\n                                                                                     : ... In instance ISSUE_UNIT\n                int_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:106: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'vec_uop'\n                                                                                     : ... In instance ISSUE_UNIT\n                vec_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:107: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'lsu_uop'\n                                                                                     : ... In instance ISSUE_UNIT\n                lsu_uop = 4'b0000;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/ISSUE_UNIT.v:108: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'bru_uop'\n                                                                                     : ... In instance ISSUE_UNIT\n                bru_uop = 4'b0000;\n                ^~~~~~~\n%Error: Exiting due to 40 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module ISSUE_UNIT (

  input [3:0] exec_unit_sel_in,
  input [3:0] exec_uop_in,


  output int_enable_out,
  output vec_enable_out,
  output lsu_enable_out,
  output bru_enable_out,


  output [3:0] int_exec_uop_out,
  output [3:0] vec_exec_uop_out,
  output [3:0] lsu_exec_uop_out,
  output [3:0] bru_exec_uop_out
);



wire int_enable_wire;
wire vec_enable_wire;
wire lsu_enable_wire;
wire bru_enable_wire;


wire [3:0] int_uop;
wire [3:0] vec_uop;
wire [3:0] lsu_uop;
wire [3:0] bru_uop;


always@(*) begin
  case(exec_unit_sel_in)
    4'b0001:   begin
                int_enable_wire = 1'b1;
                vec_enable_wire = 1'b0;
                lsu_enable_wire = 1'b0;
                bru_enable_wire = 1'b0;

                int_uop = exec_uop_in;
                vec_uop = 4'b0000;
                lsu_uop = 4'b0000;
                bru_uop = 4'b0000;
              end

    4'b1000:   begin
                int_enable_wire = 1'b0;
                vec_enable_wire = 1'b1;
                lsu_enable_wire = 1'b0;
                bru_enable_wire = 1'b0;

                int_uop = 4'b0000;
                vec_uop = exec_uop_in;
                lsu_uop = 4'b0000;
                bru_uop = 4'b0000;
              end

    4'b0100:   begin
                int_enable_wire = 1'b0;
                vec_enable_wire = 1'b0;
                lsu_enable_wire = 1'b1;
                bru_enable_wire = 1'b0;

                int_uop = 4'b0000;
                vec_uop = 4'b0000;
                lsu_uop = exec_uop_in;
                bru_uop = 4'b0000;
              end

    4'b0010:   begin
                int_enable_wire = 1'b0;
                vec_enable_wire = 1'b0;
                lsu_enable_wire = 1'b0;
                bru_enable_wire = 1'b1;

                int_uop = 4'b0000;
                vec_uop = 4'b0000;
                lsu_uop = 4'b0000;
                bru_uop = exec_uop_in;
              end

    default:  begin
                int_enable_wire = 1'b0;
                vec_enable_wire = 1'b0;
                lsu_enable_wire = 1'b0;
                bru_enable_wire = 1'b0;

                int_uop = 4'b0000;
                vec_uop = 4'b0000;
                lsu_uop = 4'b0000;
                bru_uop = 4'b0000;
              end
  endcase
end


assign int_enable_out = int_enable_wire;
assign vec_enable_out = vec_enable_wire;
assign lsu_enable_out = lsu_enable_wire;
assign bru_enable_out = bru_enable_wire;


assign int_exec_uop_out = int_uop;
assign vec_exec_uop_out = vec_uop;
assign lsu_exec_uop_out = lsu_uop;
assign bru_exec_uop_out = bru_uop;

endmodule
module ISSUE_UNIT (

  input [3:0] exec_unit_sel_in,
  input [3:0] exec_uop_in,


  output int_enable_out,
  output vec_enable_out,
  output lsu_enable_out,
  output bru_enable_out,


  output [3:0] int_exec_uop_out,
  output [3:0] vec_exec_uop_out,
  output [3:0] lsu_exec_uop_out,
  output [3:0] bru_exec_uop_out
);




wire int_enable_wire;
wire vec_enable_wire;
wire lsu_enable_wire;
wire bru_enable_wire;


wire [3:0] int_uop;
wire [3:0] vec_uop;
wire [3:0] lsu_uop;
wire [3:0] bru_uop;


always@(*) begin
  case(exec_unit_sel_in)
    4'b0001:   begin
                int_enable_wire = 1'b1;
                vec_enable_wire = 1'b0;
                lsu_enable_wire = 1'b0;
                bru_enable_wire = 1'b0;

                int_uop = exec_uop_in;
                vec_uop = 4'b0000;
                lsu_uop = 4'b0000;
                bru_uop = 4'b0000;
              end

    4'b1000:   begin
                int_enable_wire = 1'b0;
                vec_enable_wire = 1'b1;
                lsu_enable_wire = 1'b0;
                bru_enable_wire = 1'b0;

                int_uop = 4'b0000;
                vec_uop = exec_uop_in;
                lsu_uop = 4'b0000;
                bru_uop = 4'b0000;
              end

    4'b0100:   begin
                int_enable_wire = 1'b0;
                vec_enable_wire = 1'b0;
                lsu_enable_wire = 1'b1;
                bru_enable_wire = 1'b0;

                int_uop = 4'b0000;
                vec_uop = 4'b0000;
                lsu_uop = exec_uop_in;
                bru_uop = 4'b0000;
              end

    4'b0010:   begin
                int_enable_wire = 1'b0;
                vec_enable_wire = 1'b0;
                lsu_enable_wire = 1'b0;
                bru_enable_wire = 1'b1;

                int_uop = 4'b0000;
                vec_uop = 4'b0000;
                lsu_uop = 4'b0000;
                bru_uop = exec_uop_in;
              end

    default:  begin
                int_enable_wire = 1'b0;
                vec_enable_wire = 1'b0;
                lsu_enable_wire = 1'b0;
                bru_enable_wire = 1'b0;

                int_uop = 4'b0000;
                vec_uop = 4'b0000;
                lsu_uop = 4'b0000;
                bru_uop = 4'b0000;
              end
  endcase
end


assign int_enable_out = int_enable_wire;
assign vec_enable_out = vec_enable_wire;
assign lsu_enable_out = lsu_enable_wire;
assign bru_enable_out = bru_enable_wire;


assign int_exec_uop_out = int_uop;
assign vec_exec_uop_out = vec_uop;
assign lsu_exec_uop_out = lsu_uop;
assign bru_exec_uop_out = bru_uop;

endmodule