data/full_repos/permissive/170402453/RISC/RegisterFile_2Bit_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/RegisterFile_2Bit_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/RegisterFile_2Bit_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/RegisterFile_2Bit_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/RegisterFile_2Bit_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/RegisterFile_2Bit_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/RegisterFile_2Bit_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n always #0.1 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/170402453/RISC/RegisterFile_2Bit_tb.v:41: Cannot find file containing module: \'RegisterFile_2Bit\'\n RegisterFile_2Bit uut (\n ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170402453/RISC,data/full_repos/permissive/170402453/RegisterFile_2Bit\n             data/full_repos/permissive/170402453/RISC,data/full_repos/permissive/170402453/RegisterFile_2Bit.v\n             data/full_repos/permissive/170402453/RISC,data/full_repos/permissive/170402453/RegisterFile_2Bit.sv\n             RegisterFile_2Bit\n             RegisterFile_2Bit.v\n             RegisterFile_2Bit.sv\n             obj_dir/RegisterFile_2Bit\n             obj_dir/RegisterFile_2Bit.v\n             obj_dir/RegisterFile_2Bit.sv\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/RegisterFile_2Bit_tb.v:71: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                   : ... In instance RegisterFile_2Bit_tb\n   DestAddr = i;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/RegisterFile_2Bit_tb.v:73: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                   : ... In instance RegisterFile_2Bit_tb\n   DestData = i; \n            ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/RegisterFile_2Bit_tb.v:83: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                   : ... In instance RegisterFile_2Bit_tb\n     AddrA = i;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/RegisterFile_2Bit_tb.v:84: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                                   : ... In instance RegisterFile_2Bit_tb\n     AddrB = j;\n           ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegisterFile_2Bit_tb;


	reg clk;
	reg Write;
	reg [1:0] AddrA;
	reg [1:0] AddrB;
	reg [1:0] DestAddr;
	reg [15:0] DestData;
	integer i, j;


	wire [15:0] DataA;
	wire [15:0] DataB;


	RegisterFile_2Bit uut (
		.clk(clk),
		.Write(Write), 
		.AddrA(AddrA), 
		.AddrB(AddrB), 
		.DestAddr(DestAddr), 
		.DestData(DestData), 
		.DataA(DataA), 
		.DataB(DataB)
	);

	initial begin

		clk=0;
		Write = 0;
		AddrA = 0;
		AddrB = 0;
		DestAddr = 0;
		DestData = 0;
		i=0;
		j=0;


		#100;
        



		Write = 1;
		for(i=0;i<4;i=i+1) begin
			DestAddr = i;
			#5;
			DestData = i;	
			#10;
		end
		#20;
		Write = 0;
		

		while(1) begin
			for(i=0;i<4;i=i+1) begin
				for(j=0;j<4;j=j+1) begin
					AddrA = i;
					AddrB = j;
					#10;
				end
			end
		end
	end
	
	
	always #0.1 clk = ~clk;
endmodule
module RegisterFile_2Bit_tb;



	reg clk;
	reg Write;
	reg [1:0] AddrA;
	reg [1:0] AddrB;
	reg [1:0] DestAddr;
	reg [15:0] DestData;
	integer i, j;


	wire [15:0] DataA;
	wire [15:0] DataB;


	RegisterFile_2Bit uut (
		.clk(clk),
		.Write(Write), 
		.AddrA(AddrA), 
		.AddrB(AddrB), 
		.DestAddr(DestAddr), 
		.DestData(DestData), 
		.DataA(DataA), 
		.DataB(DataB)
	);

	initial begin

		clk=0;
		Write = 0;
		AddrA = 0;
		AddrB = 0;
		DestAddr = 0;
		DestData = 0;
		i=0;
		j=0;


		#100;
        



		Write = 1;
		for(i=0;i<4;i=i+1) begin
			DestAddr = i;
			#5;
			DestData = i;	
			#10;
		end
		#20;
		Write = 0;
		

		while(1) begin
			for(i=0;i<4;i=i+1) begin
				for(j=0;j<4;j=j+1) begin
					AddrA = i;
					AddrB = j;
					#10;
				end
			end
		end
	end
	
	
	always #0.1 clk = ~clk;
endmodule