data/full_repos/permissive/135701568/TB.v
 line:2: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/135701568/TB.v:5: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135701568/TB.v:7: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135701568/TB.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135701568/TB.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135701568/TB.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135701568/TB.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135701568/TB.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135701568/TB.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135701568/TB.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135701568/TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n    repeat(500) #100 clk=~clk;\n                ^\n%Error: data/full_repos/permissive/135701568/TB.v:3: Cannot find file containing module: \'CPU\'\n  CPU UUT(.clk(clk), .rst(rst), .start(start));\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/135701568,data/full_repos/permissive/135701568/CPU\n             data/full_repos/permissive/135701568,data/full_repos/permissive/135701568/CPU.v\n             data/full_repos/permissive/135701568,data/full_repos/permissive/135701568/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB();
  reg clk=0,rst=0,start;
  CPU UUT(.clk(clk), .rst(rst), .start(start));
  initial begin
    #100
    rst=1;
    #100
    rst=0;
    #100
    start=0;
    clk=1;
    #100
    clk=0;
    #100
    start=1;
    clk=1;
    #100
    clk=0;
    #100
    start=0;
    #100
    clk=1;
    #100
    clk=0;
  end
  initial begin
    repeat(500) #100 clk=~clk;
  end
endmodule
module TB();

  reg clk=0,rst=0,start;
  CPU UUT(.clk(clk), .rst(rst), .start(start));
  initial begin
    #100
    rst=1;
    #100
    rst=0;
    #100
    start=0;
    clk=1;
    #100
    clk=0;
    #100
    start=1;
    clk=1;
    #100
    clk=0;
    #100
    start=0;
    #100
    clk=1;
    #100
    clk=0;
  end
  initial begin
    repeat(500) #100 clk=~clk;
  end
endmodule