data/full_repos/permissive/128117771/Automaton-VGA-80bit/image_tb.v
 line:38: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/128117771/Automaton-VGA-80bit/image_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/128117771/Automaton-VGA-80bit/image_tb.v:35: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("image_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/128117771/Automaton-VGA-80bit/image_tb.v:36: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, image_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128117771/Automaton-VGA-80bit/image_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #2 begin\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/128117771/Automaton-VGA-80bit/image_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #2  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/128117771/Automaton-VGA-80bit/image_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  # 1 $display("FIN de la simulacion");\n  ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module image_tb();

    reg[6:0] row = 0;
    reg[6:0] col = 0;

    reg[6:0] rowW = 0;
    reg[6:0] colW = 0;


	reg clk = 0;

	always #1 clk = ~clk;

	wire data;
	reg we, dataW;



	image image01 (
		.clk(clk),
		.row(row),
		.col(col),
		.data(data),
		.clkW(clk),
		.we(we),
		.rowW(rowW),
		.colW(colW),
		.dataW(dataW)
	);


	initial begin


		$dumpfile("image_tb.vcd");
		$dumpvars(0, image_tb);

		#2 begin
			we = 1'b1;
			rowW = 0;
			colW = 37;
			dataW = 1'b1;
		end

		for(row=0; row<5; row= row+1)
		begin
			$display("row: (%d)", row);
			for (col=35; col<=45; col=col+1)
			begin
				#2
				$display("data: %b (%d, %d)", data, row, col);
			end
		end
		# 1 $display("FIN de la simulacion");
		$finish;

	end

endmodule
module image_tb();


    reg[6:0] row = 0;
    reg[6:0] col = 0;

    reg[6:0] rowW = 0;
    reg[6:0] colW = 0;


	reg clk = 0;

	always #1 clk = ~clk;

	wire data;
	reg we, dataW;



	image image01 (
		.clk(clk),
		.row(row),
		.col(col),
		.data(data),
		.clkW(clk),
		.we(we),
		.rowW(rowW),
		.colW(colW),
		.dataW(dataW)
	);


	initial begin


		$dumpfile("image_tb.vcd");
		$dumpvars(0, image_tb);

		#2 begin
			we = 1'b1;
			rowW = 0;
			colW = 37;
			dataW = 1'b1;
		end

		for(row=0; row<5; row= row+1)
		begin
			$display("row: (%d)", row);
			for (col=35; col<=45; col=col+1)
			begin
				#2
				$display("data: %b (%d, %d)", data, row, col);
			end
		end
		# 1 $display("FIN de la simulacion");
		$finish;

	end

endmodule