data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:2: Cannot find include file: ./mig_7series_v4_0_traffic_gen_top.v\n`include "./mig_7series_v4_0_traffic_gen_top.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181310803/cs.srcs/sim_1/new,data/full_repos/permissive/181310803/./mig_7series_v4_0_traffic_gen_top.v\n             data/full_repos/permissive/181310803/cs.srcs/sim_1/new,data/full_repos/permissive/181310803/./mig_7series_v4_0_traffic_gen_top.v.v\n             data/full_repos/permissive/181310803/cs.srcs/sim_1/new,data/full_repos/permissive/181310803/./mig_7series_v4_0_traffic_gen_top.v.sv\n             ./mig_7series_v4_0_traffic_gen_top.v\n             ./mig_7series_v4_0_traffic_gen_top.v.v\n             ./mig_7series_v4_0_traffic_gen_top.v.sv\n             obj_dir/./mig_7series_v4_0_traffic_gen_top.v\n             obj_dir/./mig_7series_v4_0_traffic_gen_top.v.v\n             obj_dir/./mig_7series_v4_0_traffic_gen_top.v.sv\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:7: syntax error, unexpected wire, expecting \'[\'\n   wire                          app_en,\n   ^~~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:8: syntax error, unexpected reg, expecting IDENTIFIER or do or final\n   reg                           app_rdy,\n   ^~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:9: syntax error, unexpected reg, expecting IDENTIFIER or \'=\' or do or final\n   reg    [DATA_WIDTH-1:0]       app_wdf_rdy,\n   ^~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:10: syntax error, unexpected reg, expecting IDENTIFIER or \'=\' or do or final\n   reg   [DATA_WIDTH-1:0]        app_rd_data,\n   ^~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:11: syntax error, unexpected wire, expecting IDENTIFIER or \'=\' or do or final\n   wire                          app_rd_data_valid,\n   ^~~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:12: syntax error, unexpected reg, expecting IDENTIFIER or do or final\n   reg                           reset,\n   ^~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:13: syntax error, unexpected reg, expecting IDENTIFIER or \'=\' or do or final\n   reg    [2:0]                  app_cmd,\n   ^~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:14: syntax error, unexpected wire, expecting IDENTIFIER or \'=\' or do or final\n   wire   [31:0]                 app_addr,\n   ^~~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:15: syntax error, unexpected reg, expecting IDENTIFIER or do or final\n   reg   [DATA_WIDTH/8-1:0]      app_wdf_mask,\n   ^~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:16: syntax error, unexpected wire, expecting IDENTIFIER or \'=\' or do or final\n   wire   [DATA_WIDTH-1:0]       app_wdf_data,\n   ^~~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:17: syntax error, unexpected reg, expecting IDENTIFIER or do or final\n   reg                           app_wdf_wren,\n   ^~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:18: syntax error, unexpected reg, expecting IDENTIFIER or \'=\' or do or final\n   reg                           app_wdf_end,\n   ^~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sim_1/new/mig_7series_v4_0_traffic_gen_top_tb.v:19: syntax error, unexpected wire, expecting IDENTIFIER or \'=\' or do or final\n   wire                          compare_error\n   ^~~~\n%Error: Exiting due to 14 error(s)\n'
module mig_7series_v4_0_traffic_gen_top_tb #

   (
   reg                           clk,
   wire                          app_en,
   reg                           app_rdy,
   reg    [DATA_WIDTH-1:0]       app_wdf_rdy,
   reg   [DATA_WIDTH-1:0]        app_rd_data,
   wire                          app_rd_data_valid,
   reg                           reset,
   reg    [2:0]                  app_cmd,
   wire   [31:0]                 app_addr,
   reg   [DATA_WIDTH/8-1:0]      app_wdf_mask,
   wire   [DATA_WIDTH-1:0]       app_wdf_data,
   reg                           app_wdf_wren,
   reg                           app_wdf_end,
   wire                          compare_error
    )
 
 
initial
 begin
 DATA_WIDTH=64;
 clk=0;
 app_addr=0;
app_wdf_data=0;
reset=1
#50 reset=0;
#10 app_cmd=3'b000;
 app_rdy=1;
app_wdf_mask=0;
app_wdf_rdy=1;
app_en=1;
app_wdf_wren=1��
#300 app_en=0;
app_wdf_wren=1��
always #10 clk=~clk;
#500 $stop;
end

always #10 clk=~clk;

endmodule
module mig_7series_v4_0_traffic_gen_top_tb #

   (
   reg                           clk,
   wire                          app_en,
   reg                           app_rdy,
   reg    [DATA_WIDTH-1:0]       app_wdf_rdy,
   reg   [DATA_WIDTH-1:0]        app_rd_data,
   wire                          app_rd_data_valid,
   reg                           reset,
   reg    [2:0]                  app_cmd,
   wire   [31:0]                 app_addr,
   reg   [DATA_WIDTH/8-1:0]      app_wdf_mask,
   wire   [DATA_WIDTH-1:0]       app_wdf_data,
   reg                           app_wdf_wren,
   reg                           app_wdf_end,
   wire                          compare_error
    )
 
 
initial
 begin
 DATA_WIDTH=64;

 clk=0;
 app_addr=0;
app_wdf_data=0;
reset=1
#50 reset=0;
#10 app_cmd=3'b000;
 app_rdy=1;
app_wdf_mask=0;
app_wdf_rdy=1;
app_en=1;
app_wdf_wren=1��
#300 app_en=0;
app_wdf_wren=1��
always #10 clk=~clk;
#500 $stop;
end

always #10 clk=~clk;

endmodule