data/full_repos/permissive/197806087/task_based_matrix_mul/tb/test_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/197806087/task_based_matrix_mul/tb/test_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n            #5; clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/197806087/task_based_matrix_mul/tb/test_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n            #5; clk = ~clk;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/task_based_matrix_mul/tb/test_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #12; rst = 0; #12; rst = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/task_based_matrix_mul/tb/test_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #12; rst = 0; #12; rst = 1;\n                      ^\n%Error: data/full_repos/permissive/197806087/task_based_matrix_mul/tb/test_tb.v:69: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("data/dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/197806087/task_based_matrix_mul/tb/test_tb.v:70: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb);\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;

localparam CYCLES = 2;
localparam ADDR_WIDTH = 8;
localparam ARR_LENGTH = 8;
localparam DATA_WIDTH = 8;

reg clk;
reg rst;

wire init;
reg wr;
wire [7:0]addr;
wire [7:0]data;

wire busy;

delay #(CYCLES) test_del (
    .clk(clk),
    .rst(rst),
    .init(init),
    .wr(wr),
    .addr(addr),
    .data_out(data),
    .busy(busy)
);

ping #(ADDR_WIDTH, ARR_LENGTH, DATA_WIDTH) test_ping (
    .clk(clk),
    .rst(rst),
    .mem_busy(busy),
    .init_out(init),
    .data_in(data),
    .addr_out(addr)
);

    integer k;
    initial begin
    for(k = 0; k < (1<<8); k = k + 1) begin
        test_del.mem[k] = k;
    end
    end

    integer i;
    initial begin

        clk = 0;
        rst = 1;
        for(i = 0; i <= 1000; i = i+1) begin
            #5; clk = ~clk;
            #5; clk = ~clk;
        end
    end

    integer j;
    initial begin
        #12; rst = 0; #12; rst = 1;
    end

    integer l;
    initial begin
        for(l = 0; l < (1<<8); l = l + 1) begin

        end
    end

    initial begin
        $dumpfile("data/dumpfile.vcd");
        $dumpvars(0, tb);
    end

    integer x, y;
    always @(negedge busy) begin
        if(rst) begin


        end
    end

endmodule
module tb;


localparam CYCLES = 2;
localparam ADDR_WIDTH = 8;
localparam ARR_LENGTH = 8;
localparam DATA_WIDTH = 8;

reg clk;
reg rst;

wire init;
reg wr;
wire [7:0]addr;
wire [7:0]data;

wire busy;

delay #(CYCLES) test_del (
    .clk(clk),
    .rst(rst),
    .init(init),
    .wr(wr),
    .addr(addr),
    .data_out(data),
    .busy(busy)
);

ping #(ADDR_WIDTH, ARR_LENGTH, DATA_WIDTH) test_ping (
    .clk(clk),
    .rst(rst),
    .mem_busy(busy),
    .init_out(init),
    .data_in(data),
    .addr_out(addr)
);

    integer k;
    initial begin
    for(k = 0; k < (1<<8); k = k + 1) begin
        test_del.mem[k] = k;
    end
    end

    integer i;
    initial begin

        clk = 0;
        rst = 1;
        for(i = 0; i <= 1000; i = i+1) begin
            #5; clk = ~clk;
            #5; clk = ~clk;
        end
    end

    integer j;
    initial begin
        #12; rst = 0; #12; rst = 1;
    end

    integer l;
    initial begin
        for(l = 0; l < (1<<8); l = l + 1) begin

        end
    end

    initial begin
        $dumpfile("data/dumpfile.vcd");
        $dumpvars(0, tb);
    end

    integer x, y;
    always @(negedge busy) begin
        if(rst) begin


        end
    end

endmodule