data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:85: Signal definition not found, creating implicitly: \'BTND_pressed\'\n                                                                                        : ... Suggested alternative: \'BTND_pressed_prev\'\n        BTND_pressed_prev <= BTND_pressed;\n                             ^~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:97: Signal definition not found, creating implicitly: \'BTNU_pressed\'\n                                                                                        : ... Suggested alternative: \'BTND_pressed\'\n        BTNU_pressed_prev <= BTNU_pressed;\n                             ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:103: Signal definition not found, creating implicitly: \'BT2_RTS\'\n    assign BT2_RTS = JB1;\n           ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:104: Signal definition not found, creating implicitly: \'BT2_TXD\'\n    assign BT2_TXD = JB3;\n           ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:105: Signal definition not found, creating implicitly: \'BT2_STS\'\n                                                                                         : ... Suggested alternative: \'BT2_RTS\'\n    assign BT2_STS = JB7;\n           ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:120: Signal definition not found, creating implicitly: \'BT2_RXD\'\n                                                                                         : ... Suggested alternative: \'BT2_TXD\'\n    assign JB2 = BT2_RXD;\n                 ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:121: Signal definition not found, creating implicitly: \'BT2_CTS\'\n                                                                                         : ... Suggested alternative: \'BT2_RTS\'\n    assign JB4 = BT2_CTS;\n                 ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:122: Signal definition not found, creating implicitly: \'BT2_RST_N\'\n                                                                                         : ... Suggested alternative: \'BT2_RTS\'\n    assign JB8 = BT2_RST_N;\n                 ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:149: Signal definition not found, creating implicitly: \'BT2_receive\'\n                                                                                         : ... Suggested alternative: \'BT2_receive_prev\'\n    assign BT2_send = BT2_receive && !BT2_sent;\n                      ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:149: Signal definition not found, creating implicitly: \'BT2_sent\'\n    assign BT2_send = BT2_receive && !BT2_sent;\n                                      ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:149: Signal definition not found, creating implicitly: \'BT2_send\'\n                                                                                         : ... Suggested alternative: \'BT2_sent\'\n    assign BT2_send = BT2_receive && !BT2_sent;\n           ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:150: Signal definition not found, creating implicitly: \'BT2_received\'\n                                                                                         : ... Suggested alternative: \'BT2_receive\'\n    assign BT2_received = BT2_sent;\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:76: Cannot find file containing module: \'DeBounce\'\n    DeBounce BTND_debounce (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new,data/full_repos/permissive/189468210/DeBounce\n             data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new,data/full_repos/permissive/189468210/DeBounce.v\n             data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new,data/full_repos/permissive/189468210/DeBounce.sv\n             DeBounce\n             DeBounce.v\n             DeBounce.sv\n             obj_dir/DeBounce\n             obj_dir/DeBounce.v\n             obj_dir/DeBounce.sv\n%Error: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:88: Cannot find file containing module: \'DeBounce\'\n    DeBounce BTNU_debounce (\n    ^~~~~~~~\n%Error: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:128: Cannot find file containing module: \'PMOD_BT2\'\n    PMOD_BT2 bt2 (\n    ^~~~~~~~\n%Error: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:166: Cannot find file containing module: \'StepMotorInterface\'\n    StepMotorInterface #(\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:178: Cannot find file containing module: \'StepMotorInterface\'\n    StepMotorInterface #(\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:190: Cannot find file containing module: \'PMOD_Step\'\n    PMOD_Step stepLeft (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:205: Cannot find file containing module: \'PMOD_Step\'\n    PMOD_Step stepRight (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/Top.v:240: Cannot find file containing module: \'PMOD_RTCC\'\n    PMOD_RTCC rtcc (\n    ^~~~~~~~~\n%Error: Exiting due to 8 error(s), 12 warning(s)\n'
module top(
    input GCLK,
    input BTNC,
    input BTND,
    input BTNU,

    output LD0,
    output LD1,
    output LD2,
    output LD3,
    output LD4,
    output LD5,
    output LD6,
    output LD7,
    

    
    output JA1,
    input  JA2,
    inout  JA3,
    inout  JA4,
    inout  JA9,
    inout  JA10,


    input  JB1,
    output JB2,
    input  JB3,
    output JB4,
    input  JB7,
    output JB8,
    input  JB9,
    input  JB10,
    

    output JC1_N,
    output JC1_P,
    output JC2_N,
    output JC2_P,
    output JC3_N,
    output JC3_P,
    output JC4_N,
    output JC4_P
    );
    

    wire CLK = GCLK;


    wire RST_N = !BTNC;
    






    DeBounce BTND_debounce (
        .clk(CLK),
        .n_reset(RST_N),
        .button_in(BTND),
        .DB_out(BTND_pressed)
        );

    reg BTND_pressed_prev;
    always @(posedge CLK) begin
        BTND_pressed_prev <= BTND_pressed;
    end
    
    DeBounce BTNU_debounce (
        .clk(CLK),
        .n_reset(RST_N),
        .button_in(BTNU),
        .DB_out(BTNU_pressed)
        );

    reg BTNU_pressed_prev;
    always @(posedge CLK) begin
        BTNU_pressed_prev <= BTNU_pressed;
    end
    

    

    assign BT2_RTS = JB1;
    assign BT2_TXD = JB3;
    assign BT2_STS = JB7;


    assign LD0 = BT2_STS;




    assign JB2 = BT2_RXD;
    assign JB4 = BT2_CTS;
    assign JB8 = BT2_RST_N;

    wire [7:0] BT2_char_out;
    wire [7:0] BT2_char_in;


    PMOD_BT2 bt2 (
        .CLK        (CLK),
        .RST_N      (RST_N),

        .RTS        (BT2_RTS),
        .RXD        (BT2_RXD),
        .TXD        (BT2_TXD),
        .CTS        (BT2_CTS),
        .STS        (BT2_STS),
        .RST_N_Out  (BT2_RST_N),
        
        .char_in    (BT2_char_in),
        .char_out   (BT2_char_out),
        .send       (BT2_send),
        .sent       (BT2_sent),
        .receive    (BT2_receive),
        .received   (BT2_received)
        );
        

    assign BT2_char_in = BT2_char_out;
    assign BT2_send = BT2_receive && !BT2_sent;
    assign BT2_received = BT2_sent;
    
    reg BT2_receive_prev;
    always @(posedge CLK) begin
        BT2_receive_prev <= BT2_receive;
    end
    





    wire step_dirL, step_dirR;
    wire step_enbL, step_enbR;
    wire step_steppedL, step_steppedR;

    StepMotorInterface #(
        .SIDE (1'b1)
        ) stepMotorIntfL (
        .CLK        (CLK),
        .RST_N      (RST_N),
        .char_vld   (BT2_receive),
        .char       (BT2_char_out),
        .enb        (step_enbL),
        .dir        (step_dirL),
        .stepped    (step_steppedL)
        );

    StepMotorInterface #(
        .SIDE (1'b0)
        ) stepMotorIntfR (
        .CLK        (CLK),
        .RST_N      (RST_N),
        .char_vld   (BT2_receive),
        .char       (BT2_char_out),
        .enb        (step_enbR),
        .dir        (step_dirR),
        .stepped    (step_steppedR)
        );

    PMOD_Step stepLeft (
        .CLK    (CLK),
        .RST_N  (RST_N),

        .DIR    (step_dirL),
        .ENB    (step_enbL),
        
        .stepped (step_steppedL),

        .SIG1   (JC3_N),
        .SIG2   (JC3_P),
        .SIG3   (JC4_N),
        .SIG4   (JC4_P)
        );

    PMOD_Step stepRight (
        .CLK    (CLK),
        .RST_N  (RST_N),

        .DIR    (step_dirR),
        .ENB    (step_enbR),
        
        .stepped (step_steppedR),

        .SIG1   (JC1_N),
        .SIG2   (JC1_P),
        .SIG3   (JC2_N),
        .SIG4   (JC2_P)
        );



    
    reg rtcc_mfiState;
    wire triggerMFIToggle = BT2_receive && (BT2_receive != BT2_receive_prev) && BT2_char_out == "T";
    
    assign LD6 = rtcc_mfiState;
    assign LD7 = JA2;
        
    always @(posedge CLK) begin
        if (!RST_N) begin
            rtcc_mfiState <= 0;
        end
        else begin
            if (triggerMFIToggle) begin
                rtcc_mfiState <= !rtcc_mfiState;
            end
        end
    end
    
    PMOD_RTCC rtcc (
        .CLK    (CLK),
        .RST_N  (RST_N),
        
        .mfiState (rtcc_mfiState),
        .busy (LD5),
        
        .SCL_1    (JA3),
        .SDA_1    (JA4),
        .SCL_2    (JA9),
        .SDA_2    (JA10),
        
        .missed_ack (JA1)
        );

endmodule
module top(
    input GCLK,
    input BTNC,
    input BTND,
    input BTNU,

    output LD0,
    output LD1,
    output LD2,
    output LD3,
    output LD4,
    output LD5,
    output LD6,
    output LD7,
    

    
    output JA1,
    input  JA2,
    inout  JA3,
    inout  JA4,
    inout  JA9,
    inout  JA10,


    input  JB1,
    output JB2,
    input  JB3,
    output JB4,
    input  JB7,
    output JB8,
    input  JB9,
    input  JB10,
    

    output JC1_N,
    output JC1_P,
    output JC2_N,
    output JC2_P,
    output JC3_N,
    output JC3_P,
    output JC4_N,
    output JC4_P
    );

    

    wire CLK = GCLK;


    wire RST_N = !BTNC;
    






    DeBounce BTND_debounce (
        .clk(CLK),
        .n_reset(RST_N),
        .button_in(BTND),
        .DB_out(BTND_pressed)
        );

    reg BTND_pressed_prev;
    always @(posedge CLK) begin
        BTND_pressed_prev <= BTND_pressed;
    end
    
    DeBounce BTNU_debounce (
        .clk(CLK),
        .n_reset(RST_N),
        .button_in(BTNU),
        .DB_out(BTNU_pressed)
        );

    reg BTNU_pressed_prev;
    always @(posedge CLK) begin
        BTNU_pressed_prev <= BTNU_pressed;
    end
    

    

    assign BT2_RTS = JB1;
    assign BT2_TXD = JB3;
    assign BT2_STS = JB7;


    assign LD0 = BT2_STS;




    assign JB2 = BT2_RXD;
    assign JB4 = BT2_CTS;
    assign JB8 = BT2_RST_N;

    wire [7:0] BT2_char_out;
    wire [7:0] BT2_char_in;


    PMOD_BT2 bt2 (
        .CLK        (CLK),
        .RST_N      (RST_N),

        .RTS        (BT2_RTS),
        .RXD        (BT2_RXD),
        .TXD        (BT2_TXD),
        .CTS        (BT2_CTS),
        .STS        (BT2_STS),
        .RST_N_Out  (BT2_RST_N),
        
        .char_in    (BT2_char_in),
        .char_out   (BT2_char_out),
        .send       (BT2_send),
        .sent       (BT2_sent),
        .receive    (BT2_receive),
        .received   (BT2_received)
        );
        

    assign BT2_char_in = BT2_char_out;
    assign BT2_send = BT2_receive && !BT2_sent;
    assign BT2_received = BT2_sent;
    
    reg BT2_receive_prev;
    always @(posedge CLK) begin
        BT2_receive_prev <= BT2_receive;
    end
    





    wire step_dirL, step_dirR;
    wire step_enbL, step_enbR;
    wire step_steppedL, step_steppedR;

    StepMotorInterface #(
        .SIDE (1'b1)
        ) stepMotorIntfL (
        .CLK        (CLK),
        .RST_N      (RST_N),
        .char_vld   (BT2_receive),
        .char       (BT2_char_out),
        .enb        (step_enbL),
        .dir        (step_dirL),
        .stepped    (step_steppedL)
        );

    StepMotorInterface #(
        .SIDE (1'b0)
        ) stepMotorIntfR (
        .CLK        (CLK),
        .RST_N      (RST_N),
        .char_vld   (BT2_receive),
        .char       (BT2_char_out),
        .enb        (step_enbR),
        .dir        (step_dirR),
        .stepped    (step_steppedR)
        );

    PMOD_Step stepLeft (
        .CLK    (CLK),
        .RST_N  (RST_N),

        .DIR    (step_dirL),
        .ENB    (step_enbL),
        
        .stepped (step_steppedL),

        .SIG1   (JC3_N),
        .SIG2   (JC3_P),
        .SIG3   (JC4_N),
        .SIG4   (JC4_P)
        );

    PMOD_Step stepRight (
        .CLK    (CLK),
        .RST_N  (RST_N),

        .DIR    (step_dirR),
        .ENB    (step_enbR),
        
        .stepped (step_steppedR),

        .SIG1   (JC1_N),
        .SIG2   (JC1_P),
        .SIG3   (JC2_N),
        .SIG4   (JC2_P)
        );



    
    reg rtcc_mfiState;
    wire triggerMFIToggle = BT2_receive && (BT2_receive != BT2_receive_prev) && BT2_char_out == "T";
    
    assign LD6 = rtcc_mfiState;
    assign LD7 = JA2;
        
    always @(posedge CLK) begin
        if (!RST_N) begin
            rtcc_mfiState <= 0;
        end
        else begin
            if (triggerMFIToggle) begin
                rtcc_mfiState <= !rtcc_mfiState;
            end
        end
    end
    
    PMOD_RTCC rtcc (
        .CLK    (CLK),
        .RST_N  (RST_N),
        
        .mfiState (rtcc_mfiState),
        .busy (LD5),
        
        .SCL_1    (JA3),
        .SDA_1    (JA4),
        .SCL_2    (JA9),
        .SDA_2    (JA10),
        
        .missed_ack (JA1)
        );

endmodule