data/full_repos/permissive/131358616/test/uart_rx_tb.v
 line:48: before: "("
1: b'%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:37: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,uart_rx);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/uart_rx_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\nalways #(clk_pulse_width/2) clk = !clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:45: Unsupported or unknown PLI call: $monitor\n $monitor("Time %d", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:48: syntax error, unexpected \'@\'\n repeat (5) @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:56: Unsupported: wait statements\n wait( rst_n );\n ^~~~\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:57: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:58: Unsupported or unknown PLI call: $monitor\n $monitor("[Time %d]: Started testbench", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:62: syntax error, unexpected \'@\'\n repeat (clock_frequency/baud_rate) @(negedge clk);\n                                    ^\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:66: syntax error, unexpected \'@\'\n    repeat (clock_frequency/baud_rate) @(negedge clk);\n                                       ^\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:68: syntax error, unexpected \'@\'\n    repeat (clock_frequency/baud_rate) @(negedge clk);\n                                       ^\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:70: syntax error, unexpected \'@\'\n    repeat (clock_frequency/baud_rate) @(negedge clk);\n                                       ^\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:72: syntax error, unexpected \'@\'\n    repeat (clock_frequency/baud_rate) @(negedge clk);\n                                       ^\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:74: syntax error, unexpected \'@\'\n    repeat (clock_frequency/baud_rate) @(negedge clk);\n                                       ^\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:76: syntax error, unexpected \'@\'\n    repeat (clock_frequency/baud_rate) @(negedge clk);\n                                       ^\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:78: syntax error, unexpected \'@\'\n    repeat (clock_frequency/baud_rate) @(negedge clk);\n                                       ^\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:80: syntax error, unexpected \'@\'\n    repeat (clock_frequency/baud_rate) @(negedge clk);\n                                       ^\n%Error: data/full_repos/permissive/131358616/test/uart_rx_tb.v:85: syntax error, unexpected \'@\'\n    repeat (clock_frequency/baud_rate) @(negedge clk);\n                                       ^\n%Error: Exiting due to 16 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_rx_tb;

reg clk, rst_n;
reg rx, clear;
wire [7:0] data;
wire busy, error, new_value;

localparam clock_frequency = 12000000;
localparam clk_pulse_width = 1000000000/clock_frequency;

localparam baud_rate = 9600;

uart_rx uart_rx(
	.rst_n(rst_n),
	.clk(clk),
	.rx(rx),
	.clear(clear),
	.data(data),
	.busy(busy),
    .error(error),
    .new_value(new_value)
);


initial begin
    $dumpvars(0,uart_rx);
end


always #(clk_pulse_width/2) clk = !clk;


initial begin
	$monitor("Time %d", $time);
	clk = 0;
    rst_n = 0;
	repeat (5) @(negedge clk);
	rst_n = 1;
end


initial begin
	rx = 1;
    clear = 0;
	wait( rst_n );
	@(negedge clk);
	$monitor("[Time %d]: Started testbench", $time);


	rx = 0;
	repeat (clock_frequency/baud_rate) @(negedge clk);


    rx = 1;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 0;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 1;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 0;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 1;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 0;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 1;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 0;
    repeat (clock_frequency/baud_rate) @(negedge clk);


    rx = 1;
    
    repeat (clock_frequency/baud_rate) @(negedge clk);
    
	$finish;
end

endmodule
module uart_rx_tb;


reg clk, rst_n;
reg rx, clear;
wire [7:0] data;
wire busy, error, new_value;

localparam clock_frequency = 12000000;
localparam clk_pulse_width = 1000000000/clock_frequency;

localparam baud_rate = 9600;

uart_rx uart_rx(
	.rst_n(rst_n),
	.clk(clk),
	.rx(rx),
	.clear(clear),
	.data(data),
	.busy(busy),
    .error(error),
    .new_value(new_value)
);


initial begin
    $dumpvars(0,uart_rx);
end


always #(clk_pulse_width/2) clk = !clk;


initial begin
	$monitor("Time %d", $time);
	clk = 0;
    rst_n = 0;
	repeat (5) @(negedge clk);
	rst_n = 1;
end


initial begin
	rx = 1;
    clear = 0;
	wait( rst_n );
	@(negedge clk);
	$monitor("[Time %d]: Started testbench", $time);


	rx = 0;
	repeat (clock_frequency/baud_rate) @(negedge clk);


    rx = 1;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 0;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 1;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 0;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 1;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 0;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 1;
    repeat (clock_frequency/baud_rate) @(negedge clk);
    rx = 0;
    repeat (clock_frequency/baud_rate) @(negedge clk);


    rx = 1;
    
    repeat (clock_frequency/baud_rate) @(negedge clk);
    
	$finish;
end

endmodule