data/full_repos/permissive/123690745/tctb.v
'utf-8' codec can't decode byte 0xa1 in position 812: invalid start byte
1: b'%Warning-STMTDLY: data/full_repos/permissive/123690745/tctb.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #90;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123690745/tctb.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123690745/tctb.v:82: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/123690745/tctb.v:49: Cannot find file containing module: \'TC\'\n TC uut (\n ^~\n        ... Looked in:\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/TC\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/TC.v\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/TC.sv\n             TC\n             TC.v\n             TC.sv\n             obj_dir/TC\n             obj_dir/TC.v\n             obj_dir/TC.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tctb;


	reg clk;
	reg reset;
	reg [3:2] PrAddr;
	reg WE;
	reg [31:0] DataIn;


	wire [31:0] DataOut;
	wire InterruptRequest;








	



	TC uut (
		.clk(clk), 
		.reset(reset), 
		.PrAddr(PrAddr), 
		.WE(WE), 
		.DataIn(DataIn), 
		.DataOut(DataOut), 
		.InterruptRequest(InterruptRequest)
	);

	initial begin

		clk = 0;
		reset = 0;
		PrAddr = 0;
		WE = 0;
		DataIn = 0;





		#90;
		WE = 1;
		PrAddr = 0;
		DataIn = 32'b1011;
		#20
		WE = 1;
		PrAddr = 1;
		DataIn = 10;
		

	end
   always #10 clk = ~clk;
endmodule
module tctb;



	reg clk;
	reg reset;
	reg [3:2] PrAddr;
	reg WE;
	reg [31:0] DataIn;


	wire [31:0] DataOut;
	wire InterruptRequest;








	



	TC uut (
		.clk(clk), 
		.reset(reset), 
		.PrAddr(PrAddr), 
		.WE(WE), 
		.DataIn(DataIn), 
		.DataOut(DataOut), 
		.InterruptRequest(InterruptRequest)
	);

	initial begin

		clk = 0;
		reset = 0;
		PrAddr = 0;
		WE = 0;
		DataIn = 0;





		#90;
		WE = 1;
		PrAddr = 0;
		DataIn = 32'b1011;
		#20
		WE = 1;
		PrAddr = 1;
		DataIn = 10;
		

	end
   always #10 clk = ~clk;
endmodule