data/full_repos/permissive/143278/ivltests/eq.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eq.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #1 if (s_ones !== 1) begin\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/eq.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #1 if (s_ones !== 0) begin\n   ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module netnet();

reg [2:0] s;
wire s_ones;
assign s_ones = (s==7);

initial begin
   s = 3'b111;

   #1 if (s_ones !== 1) begin
      $display("FAILED -- %b==7 returns %b", s, s_ones);
      $finish;
   end
   s = 3'b011;

   #1 if (s_ones !== 0) begin
      $display("FAILED -- %b==7 returns %b", s, s_ones);
      $finish;
   end

   $display("PASSED");
end
endmodule
module netnet();


reg [2:0] s;
wire s_ones;
assign s_ones = (s==7);

initial begin
   s = 3'b111;

   #1 if (s_ones !== 1) begin
      $display("FAILED -- %b==7 returns %b", s, s_ones);
      $finish;
   end
   s = 3'b011;

   #1 if (s_ones !== 0) begin
      $display("FAILED -- %b==7 returns %b", s, s_ones);
      $finish;
   end

   $display("PASSED");
end
endmodule