data/full_repos/permissive/125927162/PWM/pwm.v
data/verilator_xmls/47e042cb-1064-4dca-a5d4-6e7dffbd88f7.xml
module pwm (clk, rst, in, out);
   parameter WIDTH = 8;
   input clk;
   input rst;
   input [WIDTH-1:0] in;
   output 	     out;
   reg [WIDTH-1:0]   counter;
   reg [WIDTH-1:0]   in_d;
   
   always @ (posedge clk) begin
      in_d <= in;
      if (rst)
	counter <= {WIDTH{1'b0}};
      else
	 counter <= counter + 1'b1;
   end
   
   assign out = (in_d[WIDTH-1:0] > counter[WIDTH-1:0]);
   
endmodule
module pwm (clk, rst, in, out);

   parameter WIDTH = 8;
   input clk;
   input rst;
   input [WIDTH-1:0] in;
   output 	     out;
   reg [WIDTH-1:0]   counter;
   reg [WIDTH-1:0]   in_d;
   
   always @ (posedge clk) begin
      in_d <= in;
      if (rst)
	counter <= {WIDTH{1'b0}};
      else
	 counter <= counter + 1'b1;
   end
   
   assign out = (in_d[WIDTH-1:0] > counter[WIDTH-1:0]);
   
endmodule