data/full_repos/permissive/139213403/FPGA/led_bar.v
1: b'%Error: data/full_repos/permissive/139213403/FPGA/led_bar.v:37: Cannot find file containing module: \'blinker_counter\'\n blinker_counter #(.C_ON(C_ON), .C_OFF(C_OFF), .C_BITS(C_BITS)) bc(.clk(clk), .reset(reset), .blink(blink), .b_en(b_en));\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/blinker_counter\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/blinker_counter.v\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/blinker_counter.sv\n             blinker_counter\n             blinker_counter.v\n             blinker_counter.sv\n             obj_dir/blinker_counter\n             obj_dir/blinker_counter.v\n             obj_dir/blinker_counter.sv\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_bar.v:98: Operator AND expects 4 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                      : ... In instance led_bar\n     in_en_next = (1\'b1 & b_en & en) << i_next;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_bar.v:98: Operator AND expects 4 bits on the RHS, but RHS\'s VARREF \'b_en\' generates 1 bits.\n                                                                      : ... In instance led_bar\n     in_en_next = (1\'b1 & b_en & en) << i_next;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_bar.v:98: Operator AND expects 4 bits on the RHS, but RHS\'s VARREF \'en\' generates 1 bits.\n                                                                      : ... In instance led_bar\n     in_en_next = (1\'b1 & b_en & en) << i_next;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_bar.v:99: Operator AND expects 2 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                      : ... In instance led_bar\n     out_en_next = (1\'b1 & b_en & en) << o_next;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_bar.v:99: Operator AND expects 2 bits on the RHS, but RHS\'s VARREF \'b_en\' generates 1 bits.\n                                                                      : ... In instance led_bar\n     out_en_next = (1\'b1 & b_en & en) << o_next;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/139213403/FPGA/led_bar.v:99: Operator AND expects 2 bits on the RHS, but RHS\'s VARREF \'en\' generates 1 bits.\n                                                                      : ... In instance led_bar\n     out_en_next = (1\'b1 & b_en & en) << o_next;\n                                ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module led_bar
#(

	parameter LEDS_N=8,
				 LEDS_I=4,
				 LEDS_O=2,
				 LEDS_BITS=4,
	

	          VAL_L=0,
				 VAL_U=7,
				 VAL_Z=3,
				 VAL_BITS=3,
				 

				 C_ON=2,
				 C_OFF=3,
				 C_BITS=3
)
(
	input wire clk, reset,
	input wire en,
	input wire [VAL_BITS-1:0] value,
	input wire blink,
	output wire [LEDS_I-1:0] in_en,
	output wire [LEDS_O-1:0] out_en
);

	reg [LEDS_I-1:0] in_en_reg, in_en_next;
	reg [LEDS_O-1:0] out_en_reg, out_en_next;
	reg [VAL_BITS-1:0] val_reg, val_next;
	reg [VAL_BITS-1:0] cur_reg, cur_next;
	reg [LEDS_BITS-1:0] i_reg, i_next, o_reg, o_next;
	wire val_en;
	wire b_en;

	blinker_counter #(.C_ON(C_ON), .C_OFF(C_OFF), .C_BITS(C_BITS)) bc(.clk(clk), .reset(reset), .blink(blink), .b_en(b_en));
	

	always @(posedge clk, posedge reset)
		if (reset)
			begin
				in_en_reg <= 0;
				out_en_reg <= 0;
				val_reg <= 0;
				cur_reg <= 0;
				i_reg <= 0;
				o_reg <= 0;
			end
		else
			begin
				in_en_reg <= in_en_next;
				out_en_reg <= out_en_next;
				val_reg <= val_next;
				cur_reg <= cur_next;
				i_reg <= i_next;
				o_reg <= o_next;
			end


	always @*
		begin
			val_next = value;
			if (val_next < VAL_L)
				val_next = VAL_L;
			if (val_next > VAL_U)
				val_next = VAL_U;
		end
			

	always @*
		begin
			cur_next = cur_reg + 1'b1;
			if (cur_next == VAL_U)
				cur_next = VAL_L;
		
			i_next = i_reg + 1'b1;
			o_next = o_reg;
			if (i_next == LEDS_I)
				begin
					i_next = 0;
					o_next = o_reg + 1'b1;
					if (o_next == LEDS_O)
						o_next = 0;
				end
		end
		
	assign val_en = (val_reg >= VAL_Z) ? (cur_next >= VAL_Z) && (cur_next <= val_reg)
	              : (cur_next >= val_reg) && (cur_next <= VAL_Z);
	

	always @*
		begin
			in_en_next = 0;
			out_en_next = 0;
			if (val_en)
				begin
					in_en_next = (1'b1 & b_en & en) << i_next;
					out_en_next = (1'b1 & b_en & en) << o_next;
				end
		end
			
	assign in_en = in_en_reg;
	assign out_en = out_en_reg;
			
endmodule
module led_bar
#(

	parameter LEDS_N=8,
				 LEDS_I=4,
				 LEDS_O=2,
				 LEDS_BITS=4,
	

	          VAL_L=0,
				 VAL_U=7,
				 VAL_Z=3,
				 VAL_BITS=3,
				 

				 C_ON=2,
				 C_OFF=3,
				 C_BITS=3
)
(
	input wire clk, reset,
	input wire en,
	input wire [VAL_BITS-1:0] value,
	input wire blink,
	output wire [LEDS_I-1:0] in_en,
	output wire [LEDS_O-1:0] out_en
);


	reg [LEDS_I-1:0] in_en_reg, in_en_next;
	reg [LEDS_O-1:0] out_en_reg, out_en_next;
	reg [VAL_BITS-1:0] val_reg, val_next;
	reg [VAL_BITS-1:0] cur_reg, cur_next;
	reg [LEDS_BITS-1:0] i_reg, i_next, o_reg, o_next;
	wire val_en;
	wire b_en;

	blinker_counter #(.C_ON(C_ON), .C_OFF(C_OFF), .C_BITS(C_BITS)) bc(.clk(clk), .reset(reset), .blink(blink), .b_en(b_en));
	

	always @(posedge clk, posedge reset)
		if (reset)
			begin
				in_en_reg <= 0;
				out_en_reg <= 0;
				val_reg <= 0;
				cur_reg <= 0;
				i_reg <= 0;
				o_reg <= 0;
			end
		else
			begin
				in_en_reg <= in_en_next;
				out_en_reg <= out_en_next;
				val_reg <= val_next;
				cur_reg <= cur_next;
				i_reg <= i_next;
				o_reg <= o_next;
			end


	always @*
		begin
			val_next = value;
			if (val_next < VAL_L)
				val_next = VAL_L;
			if (val_next > VAL_U)
				val_next = VAL_U;
		end
			

	always @*
		begin
			cur_next = cur_reg + 1'b1;
			if (cur_next == VAL_U)
				cur_next = VAL_L;
		
			i_next = i_reg + 1'b1;
			o_next = o_reg;
			if (i_next == LEDS_I)
				begin
					i_next = 0;
					o_next = o_reg + 1'b1;
					if (o_next == LEDS_O)
						o_next = 0;
				end
		end
		
	assign val_en = (val_reg >= VAL_Z) ? (cur_next >= VAL_Z) && (cur_next <= val_reg)
	              : (cur_next >= val_reg) && (cur_next <= VAL_Z);
	

	always @*
		begin
			in_en_next = 0;
			out_en_next = 0;
			if (val_en)
				begin
					in_en_next = (1'b1 & b_en & en) << i_next;
					out_en_next = (1'b1 & b_en & en) << o_next;
				end
		end
			
	assign in_en = in_en_reg;
	assign out_en = out_en_reg;
			
endmodule