data/full_repos/permissive/2012679/t_block_memory.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/2012679/t_block_memory.v:35: Unsupported: Ignoring delay on this delayed statement.\n always #1 clock = ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2012679/t_block_memory.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/2012679/t_block_memory.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/2012679/t_block_memory.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/2012679/t_block_memory.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/2012679/t_block_memory.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/2012679/t_block_memory.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/2012679/t_block_memory.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/2012679/t_block_memory.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/2012679/t_block_memory.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/2012679/t_block_memory.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Error: data/full_repos/permissive/2012679/t_block_memory.v:21: Cannot find file containing module: \'block_memory\'\n block_memory uut (\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2012679,data/full_repos/permissive/2012679/block_memory\n             data/full_repos/permissive/2012679,data/full_repos/permissive/2012679/block_memory.v\n             data/full_repos/permissive/2012679,data/full_repos/permissive/2012679/block_memory.sv\n             block_memory\n             block_memory.v\n             block_memory.sv\n             obj_dir/block_memory\n             obj_dir/block_memory.v\n             obj_dir/block_memory.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_block_memory;


	reg clock;
	reg reset;
	reg enable;
	reg [4:0] row1;
	reg [4:0] row2;
	reg [4:0] col1;
	reg [4:0] col2;
	reg [1:0] func;
	reg [1:0] stage;


	wire [2:0] block1;
	wire [2:0] block2;
	wire busy;


	block_memory uut (
		.clock(clock), 
		.reset(reset), 
		.enable(enable), 
		.row1(row1), 
		.row2(row2), 
		.col1(col1), 
		.col2(col2), 
		.func(func), 
		.stage(stage), 
		.block1(block1), 
		.block2(block2), 
		.busy(busy)
	);
	always #1 clock = ~clock;
	initial begin

		clock = 0;
		reset = 0;
		enable = 0;
		row1 = 0;
		row2 = 0;
		col1 = 0;
		col2 = 0;
		func = 0;
		stage = 1;


		#100;
        

		reset = 1;
		#10;
		reset = 0;
		#10;

		enable = 1;
		func = 1;
		#10;
		enable = 0;
		func = 0;
		#200;

		col1 = 8;
		row1 = 8;
		enable = 1;
		func = 0;
		#10;

		enable = 1;
		func = 2;
		#10
		enable = 0;
		#100;
		func = 3;
		enable = 1;
		#10;
		enable = 0;
		#200;
	end
endmodule
module t_block_memory;



	reg clock;
	reg reset;
	reg enable;
	reg [4:0] row1;
	reg [4:0] row2;
	reg [4:0] col1;
	reg [4:0] col2;
	reg [1:0] func;
	reg [1:0] stage;


	wire [2:0] block1;
	wire [2:0] block2;
	wire busy;


	block_memory uut (
		.clock(clock), 
		.reset(reset), 
		.enable(enable), 
		.row1(row1), 
		.row2(row2), 
		.col1(col1), 
		.col2(col2), 
		.func(func), 
		.stage(stage), 
		.block1(block1), 
		.block2(block2), 
		.busy(busy)
	);
	always #1 clock = ~clock;
	initial begin

		clock = 0;
		reset = 0;
		enable = 0;
		row1 = 0;
		row2 = 0;
		col1 = 0;
		col2 = 0;
		func = 0;
		stage = 1;


		#100;
        

		reset = 1;
		#10;
		reset = 0;
		#10;

		enable = 1;
		func = 1;
		#10;
		enable = 0;
		func = 0;
		#200;

		col1 = 8;
		row1 = 8;
		enable = 1;
		func = 0;
		#10;

		enable = 1;
		func = 2;
		#10
		enable = 0;
		#100;
		func = 3;
		enable = 1;
		#10;
		enable = 0;
		#200;
	end
endmodule