data/full_repos/permissive/125927162/PISO/piso_tb.v
 line:69: before: "#"
1: b'%Error: data/full_repos/permissive/125927162/PISO/piso_tb.v:33: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("piso_test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/PISO/piso_tb.v:34: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, piso_tb);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/PISO/piso_tb.v:35: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("piso.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/PISO/piso_tb.v:36: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, DUT);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #15\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n      #7\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n      #7\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PISO/piso_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n   always #5\n          ^\n%Error: Exiting due to 4 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module piso_tb();
   reg clk;
   reg latch;
   reg rst;
   reg [7:0] din;
   reg 	     ser;
   wire 	   dout;

   piso #(.WIDTH(8)) DUT(
			 .clk(clk),
			 .latch(latch),
			 .rst(rst),
			 .din(din),
			 .ser(ser),
			 .dout(dout)
			 );
   initial begin
      $dumpfile("piso_test.vcd");
      $dumpvars(0, piso_tb);
      $dumpfile("piso.vcd");
      $dumpvars(0, DUT);
      rst = 1;
      ser = 0;
      latch = 0;
      clk = 0;
      din = 8'b0;
      #10
	rst = 0;
      #5
	din = 8'h55;
      latch = 1;
      #15
	latch = 0;
      din = 0;
      #100
	din = 8'hAA;
      latch = 1;
      #7
	latch = 0;
      din = 0;
      #100
	din = 8'h0f;
      latch = 1;
      #10
	latch = 0;
      din = 0;
      #100
	din = 8'hcd;
      latch = 1;
      #7
	latch = 0;
      din = 0;
      #100
      #100
	din = 8'b10000000;
      latch = 1;
      #5
	latch = 0;
      din = 0;
      #100
	din = 8'hf0;
      latch = 1;
      #5
	latch = 0;
      din = 0;
      #100
	
	$finish;
   end

   always #5
     clk = ~clk;
endmodule
module piso_tb();

   reg clk;
   reg latch;
   reg rst;
   reg [7:0] din;
   reg 	     ser;
   wire 	   dout;

   piso #(.WIDTH(8)) DUT(
			 .clk(clk),
			 .latch(latch),
			 .rst(rst),
			 .din(din),
			 .ser(ser),
			 .dout(dout)
			 );
   initial begin
      $dumpfile("piso_test.vcd");
      $dumpvars(0, piso_tb);
      $dumpfile("piso.vcd");
      $dumpvars(0, DUT);
      rst = 1;
      ser = 0;
      latch = 0;
      clk = 0;
      din = 8'b0;
      #10
	rst = 0;
      #5
	din = 8'h55;
      latch = 1;
      #15
	latch = 0;
      din = 0;
      #100
	din = 8'hAA;
      latch = 1;
      #7
	latch = 0;
      din = 0;
      #100
	din = 8'h0f;
      latch = 1;
      #10
	latch = 0;
      din = 0;
      #100
	din = 8'hcd;
      latch = 1;
      #7
	latch = 0;
      din = 0;
      #100
      #100
	din = 8'b10000000;
      latch = 1;
      #5
	latch = 0;
      din = 0;
      #100
	din = 8'hf0;
      latch = 1;
      #5
	latch = 0;
      din = 0;
      #100
	
	$finish;
   end

   always #5
     clk = ~clk;
endmodule