data/full_repos/permissive/160895047/Register_File_Test.v
 line:33: before: "posedge"
1: b'%Error: data/full_repos/permissive/160895047/Register_File_Test.v:1: Cannot find include file: Register_File.v\n`include "Register_File.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160895047,data/full_repos/permissive/160895047/Register_File.v\n             data/full_repos/permissive/160895047,data/full_repos/permissive/160895047/Register_File.v.v\n             data/full_repos/permissive/160895047,data/full_repos/permissive/160895047/Register_File.v.sv\n             Register_File.v\n             Register_File.v.v\n             Register_File.v.sv\n             obj_dir/Register_File.v\n             obj_dir/Register_File.v.v\n             obj_dir/Register_File.v.sv\n%Error: data/full_repos/permissive/160895047/Register_File_Test.v:17: Unsupported or unknown PLI call: $monitor\n $monitor("%g\\t%g\\t%g\\t%g\\t%g\\t%g\\t%g", A1, A2, A3, RD1, RD2, WE, WD);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/160895047/Register_File_Test.v:25: Unsupported: Ignoring delay on this delayed statement.\n #64 WE = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160895047/Register_File_Test.v:26: Unsupported: Ignoring delay on this delayed statement.\n #64 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/160895047/Register_File_Test.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1 CLOCK <= ~CLOCK;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/160895047/Register_File_Test.v:36: Unsupported: Ignoring delay on this delayed statement.\n #2 WDCLOCK <= ~WDCLOCK;\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module Register_File_Test();
reg CLOCK;
reg [4:0] A1;
reg [4:0] A2;
reg [4:0] A3;
wire [7:0] RD1;
wire [7:0] RD2;
reg WE;
reg [7:0] WD;

reg WDCLOCK;

initial
begin
	$display("A1\tA2\tA3\tRD1\tRD2\tWE\tWD");
	$monitor("%g\t%g\t%g\t%g\t%g\t%g\t%g", A1, A2, A3, RD1, RD2, WE, WD);
	CLOCK = 0;
	A1 = 0;
	A2 = 0;
	A3 = 0;
	WD = 0;
	WE = 1;
	WDCLOCK = 0;
	#64 WE = 0;
	#64 $finish;
end

always
begin
	#1 CLOCK <= ~CLOCK;
end

always
begin
	#2 WDCLOCK <= ~WDCLOCK;
	A1 = A1 - 1;
	A2 = A1 + 1;
	A3 = A3 + 1;
	WD = WD - 1;
end

Register_File U0 (
	CLOCK,
	A1,
	A2,
	A3,
	RD1,
	RD2,
	WE,
	WD
);
endmodule
module Register_File_Test();

reg CLOCK;
reg [4:0] A1;
reg [4:0] A2;
reg [4:0] A3;
wire [7:0] RD1;
wire [7:0] RD2;
reg WE;
reg [7:0] WD;

reg WDCLOCK;

initial
begin
	$display("A1\tA2\tA3\tRD1\tRD2\tWE\tWD");
	$monitor("%g\t%g\t%g\t%g\t%g\t%g\t%g", A1, A2, A3, RD1, RD2, WE, WD);
	CLOCK = 0;
	A1 = 0;
	A2 = 0;
	A3 = 0;
	WD = 0;
	WE = 1;
	WDCLOCK = 0;
	#64 WE = 0;
	#64 $finish;
end

always
begin
	#1 CLOCK <= ~CLOCK;
end

always
begin
	#2 WDCLOCK <= ~WDCLOCK;
	A1 = A1 - 1;
	A2 = A1 + 1;
	A3 = A3 + 1;
	WD = WD - 1;
end

Register_File U0 (
	CLOCK,
	A1,
	A2,
	A3,
	RD1,
	RD2,
	WE,
	WD
);
endmodule