data/full_repos/permissive/189570969/1180300220-崔涵/1180300220-崔涵-完整工程/project_1.srcs/sources_1/new/xishi2.v
1: b"%Error: data/full_repos/permissive/189570969/1180300220-\xe5\xb4\x94\xe6\xb6\xb5/1180300220-\xe5\xb4\x94\xe6\xb6\xb5-\xe5\xae\x8c\xe6\x95\xb4\xe5\xb7\xa5\xe7\xa8\x8b/project_1.srcs/sources_1/new/xishi2.v:29: Duplicate declaration of signal: 'outp1'\n                                                                                                                                      : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    reg outp1,outp2;\n        ^~~~~\n        data/full_repos/permissive/189570969/1180300220-\xe5\xb4\x94\xe6\xb6\xb5/1180300220-\xe5\xb4\x94\xe6\xb6\xb5-\xe5\xae\x8c\xe6\x95\xb4\xe5\xb7\xa5\xe7\xa8\x8b/project_1.srcs/sources_1/new/xishi2.v:25: ... Location of original declaration\n    output outp1,\n           ^~~~~\n%Error: data/full_repos/permissive/189570969/1180300220-\xe5\xb4\x94\xe6\xb6\xb5/1180300220-\xe5\xb4\x94\xe6\xb6\xb5-\xe5\xae\x8c\xe6\x95\xb4\xe5\xb7\xa5\xe7\xa8\x8b/project_1.srcs/sources_1/new/xishi2.v:29: Duplicate declaration of signal: 'outp2'\n    reg outp1,outp2;\n              ^~~~~\n        data/full_repos/permissive/189570969/1180300220-\xe5\xb4\x94\xe6\xb6\xb5/1180300220-\xe5\xb4\x94\xe6\xb6\xb5-\xe5\xae\x8c\xe6\x95\xb4\xe5\xb7\xa5\xe7\xa8\x8b/project_1.srcs/sources_1/new/xishi2.v:26: ... Location of original declaration\n    output outp2\n           ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module xishi2(
    input clk,
    output outp1,
    output outp2
    );
    integer cnt1=0,cnt2=0;
    reg outp1,outp2;
    always @(posedge clk)
    begin
        if (cnt1 >= 500000000) begin cnt1 <= 0; end
        else begin cnt1 = cnt1 + 1; end
    end
    always @(*)
    begin
        if (cnt1 == 500000000) begin outp1 <= 1'b1; end
        else outp1 <= 1'b0;
    end
    always @(posedge clk)
        begin
            if (cnt2 >= 50000000) begin cnt2 <= 0; end
            else begin cnt2 = cnt2 + 1; end
        end
        always @(*)
        begin
            if (cnt2 == 50000000) begin outp2 <= 1'b1; end
            else outp2 <= 1'b0;
        end
endmodule
module xishi2(
    input clk,
    output outp1,
    output outp2
    );

    integer cnt1=0,cnt2=0;
    reg outp1,outp2;
    always @(posedge clk)
    begin
        if (cnt1 >= 500000000) begin cnt1 <= 0; end
        else begin cnt1 = cnt1 + 1; end
    end
    always @(*)
    begin
        if (cnt1 == 500000000) begin outp1 <= 1'b1; end
        else outp1 <= 1'b0;
    end
    always @(posedge clk)
        begin
            if (cnt2 >= 50000000) begin cnt2 <= 0; end
            else begin cnt2 = cnt2 + 1; end
        end
        always @(*)
        begin
            if (cnt2 == 50000000) begin outp2 <= 1'b1; end
            else outp2 <= 1'b0;
        end
endmodule