data/full_repos/permissive/113780415/src/top_test.v
 line:1736: before: "&&"
1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(posedge clk && enable == 1'b1)\n                                   ^~\n%Error: Cannot continue\n"
module top(SW, KEY, CLOCK_50, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR);

        input CLOCK_50;

        input [3:0] KEY;

        input [9:0] SW;

	 

	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;

	output [9:0] LEDR;


	 wire load_left, load_right, load_user;

	 

	 wire [1:0] status;

	 wire three_wins;

	 

	 wire same_leftright;

	 wire [1:0] consecutive_win;

	 wire enable_winner_indicator;

	 wire [1:0] computer;

	 wire enable_aalu;

	 wire [4:0] score;

	 reg enable_high_score;

	 wire clear_done;

	 reg return_to_load_left;

	 reg go_to_get_user;

	 wire plot;

	 wire [2:0] color;

	 wire [7:0] x;

	 wire [6:0] y;

	 wire clk; 

	 


	 wire [5:0] current_state;



	 control cont (

	             

	             .clk(clk),
	             .resetn(KEY[3]),

	             .confirm(SW[2:2]),

	             .status(status[1:0]),

	             .return_to_load_left(return_to_load_left),

	             .go_to_get_user(go_to_get_user),

	             .stop_left(KEY[2]),

	             .stop_right(KEY[0]),

	             .stop_user(KEY[1]),

	             .enable_winner_indicator(enable_winner_indicator),

	             .enable_aalu(enable_aalu),

	             .ld_user(load_user),

	             .ld_left(load_left),

	             .ld_right(load_right),

	             .curr_state(current_state[5:0]),
	             .opponent(computer[1:0]),
	             .plot(plot),

	             .color(color[2:0]),

	             .xOut(x),

	             .yOut(y)

	             );

	             

	 data data (

	             .clk(clk),

	             .load_left(load_left),

	             .load_right(load_right),

	             .stop_left(KEY[2]),

	             .stop_right(KEY[0]),

	             .resetn(KEY[3]),

	             .enable_aalu(enable_aalu),

	             .enable_winner_indicator(enable_winner_indicator),

	             .load_user(load_user),

	             .user_input_player(SW[1:0]),

	             .computer(computer[1:0]),

	             .HEX0(HEX0[6:0]),

	             .HEX1(HEX1[6:0]),

	             .HEX4(HEX4[6:0]),

	             .HEX5(HEX5[6:0]),

	             .LEDR(LEDR[9:8]),

	             .score(score[4:0]),

	             

	             .status(status[1:0]),

	             .same_leftright(same_leftright)

	             );



	

	             

    assign LEDR[7:3] = score[4:0];

	 assign LEDR[1:0] = consecutive_win[1:0];

    always@(*)

    begin

        if (same_leftright == 1'b1 || status == 2'b01)

            return_to_load_left <= 1'b1;

        else

            return_to_load_left <= 1'b0;

    end

	 

	 

    SevenSegment seg(

	     .HEXleft(HEX3[6:0]),

		  .HEXright(HEX2[6:0]),

		  .num({3'b000 ,consecutive_win[1:0]})

		  );

    

	 ratedivider rd (

	     .clk(CLOCK_50),

		  .clear_b(KEY[3]),

		  .out(clk)

		  );

		  

    always@(posedge three_wins)

    begin

        if (three_wins == 1'b1)

            enable_high_score <= 1'b1;

        else

            enable_high_score <= 1'b0;

    end

    


        

    consecutive_win_counter cwc (

                .clk(clk),

		.clear_b(KEY[3]),

		.q(consecutive_win),

		.enable(status[1:0]),

		.three_wins(three_wins)

		);

	 

    endmodule
module top(SW, KEY, CLOCK_50, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR);


        input CLOCK_50;

        input [3:0] KEY;

        input [9:0] SW;

	 

	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;

	output [9:0] LEDR;


	 wire load_left, load_right, load_user;

	 

	 wire [1:0] status;

	 wire three_wins;

	 

	 wire same_leftright;

	 wire [1:0] consecutive_win;

	 wire enable_winner_indicator;

	 wire [1:0] computer;

	 wire enable_aalu;

	 wire [4:0] score;

	 reg enable_high_score;

	 wire clear_done;

	 reg return_to_load_left;

	 reg go_to_get_user;

	 wire plot;

	 wire [2:0] color;

	 wire [7:0] x;

	 wire [6:0] y;

	 wire clk; 

	 


	 wire [5:0] current_state;



	 control cont (

	             

	             .clk(clk),
	             .resetn(KEY[3]),

	             .confirm(SW[2:2]),

	             .status(status[1:0]),

	             .return_to_load_left(return_to_load_left),

	             .go_to_get_user(go_to_get_user),

	             .stop_left(KEY[2]),

	             .stop_right(KEY[0]),

	             .stop_user(KEY[1]),

	             .enable_winner_indicator(enable_winner_indicator),

	             .enable_aalu(enable_aalu),

	             .ld_user(load_user),

	             .ld_left(load_left),

	             .ld_right(load_right),

	             .curr_state(current_state[5:0]),
	             .opponent(computer[1:0]),
	             .plot(plot),

	             .color(color[2:0]),

	             .xOut(x),

	             .yOut(y)

	             );

	             

	 data data (

	             .clk(clk),

	             .load_left(load_left),

	             .load_right(load_right),

	             .stop_left(KEY[2]),

	             .stop_right(KEY[0]),

	             .resetn(KEY[3]),

	             .enable_aalu(enable_aalu),

	             .enable_winner_indicator(enable_winner_indicator),

	             .load_user(load_user),

	             .user_input_player(SW[1:0]),

	             .computer(computer[1:0]),

	             .HEX0(HEX0[6:0]),

	             .HEX1(HEX1[6:0]),

	             .HEX4(HEX4[6:0]),

	             .HEX5(HEX5[6:0]),

	             .LEDR(LEDR[9:8]),

	             .score(score[4:0]),

	             

	             .status(status[1:0]),

	             .same_leftright(same_leftright)

	             );



	

	             

    assign LEDR[7:3] = score[4:0];

	 assign LEDR[1:0] = consecutive_win[1:0];

    always@(*)

    begin

        if (same_leftright == 1'b1 || status == 2'b01)

            return_to_load_left <= 1'b1;

        else

            return_to_load_left <= 1'b0;

    end

	 

	 

    SevenSegment seg(

	     .HEXleft(HEX3[6:0]),

		  .HEXright(HEX2[6:0]),

		  .num({3'b000 ,consecutive_win[1:0]})

		  );

    

	 ratedivider rd (

	     .clk(CLOCK_50),

		  .clear_b(KEY[3]),

		  .out(clk)

		  );

		  

    always@(posedge three_wins)

    begin

        if (three_wins == 1'b1)

            enable_high_score <= 1'b1;

        else

            enable_high_score <= 1'b0;

    end

    


        

    consecutive_win_counter cwc (

                .clk(clk),

		.clear_b(KEY[3]),

		.q(consecutive_win),

		.enable(status[1:0]),

		.three_wins(three_wins)

		);

	 

    endmodule