data/full_repos/permissive/218110222/src/dbSta/test/reg5.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/218110222/src/dbSta/test/reg5.v:7: Little bit endian vector: MSB < LSB of bit range: 0:1\n input [0:1] in;\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/218110222/src/dbSta/test/reg5.v:14: Cannot find file containing module: \'snl_ffqx1\'\n snl_ffqx1 r1 (.Q(r1q),\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/218110222/src/dbSta/test,data/full_repos/permissive/218110222/snl_ffqx1\n             data/full_repos/permissive/218110222/src/dbSta/test,data/full_repos/permissive/218110222/snl_ffqx1.v\n             data/full_repos/permissive/218110222/src/dbSta/test,data/full_repos/permissive/218110222/snl_ffqx1.sv\n             snl_ffqx1\n             snl_ffqx1.v\n             snl_ffqx1.sv\n             obj_dir/snl_ffqx1\n             obj_dir/snl_ffqx1.v\n             obj_dir/snl_ffqx1.sv\n%Error: data/full_repos/permissive/218110222/src/dbSta/test/reg5.v:17: Cannot find file containing module: \'snl_ffqx1\'\n snl_ffqx1 r2 (.Q(r2q),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/218110222/src/dbSta/test/reg5.v:20: Cannot find file containing module: \'snl_ffqx1\'\n snl_ffqx1 r3 (.Q(out),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/218110222/src/dbSta/test/reg5.v:23: Cannot find file containing module: \'snl_bufx1\'\n snl_bufx1 u1 (.Z(u1z),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/218110222/src/dbSta/test/reg5.v:25: Cannot find file containing module: \'snl_and02x1\'\n snl_and02x1 u2 (.Z(u2z),\n ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module reg5 (out,
    clk,
    in);
 output out;
 input [2:0] clk;
 input [0:1] in;

 wire r1q;
 wire r2q;
 wire u1z;
 wire u2z;

 snl_ffqx1 r1 (.Q(r1q),
    .D(in[0]),
    .CP(clk[0]));
 snl_ffqx1 r2 (.Q(r2q),
    .D(in[1]),
    .CP(clk[1]));
 snl_ffqx1 r3 (.Q(out),
    .D(u2z),
    .CP(clk[2]));
 snl_bufx1 u1 (.Z(u1z),
    .A(r2q));
 snl_and02x1 u2 (.Z(u2z),
    .A(r1q),
    .B(u1z));
endmodule
module reg5 (out,
    clk,
    in);

 output out;
 input [2:0] clk;
 input [0:1] in;

 wire r1q;
 wire r2q;
 wire u1z;
 wire u2z;

 snl_ffqx1 r1 (.Q(r1q),
    .D(in[0]),
    .CP(clk[0]));
 snl_ffqx1 r2 (.Q(r2q),
    .D(in[1]),
    .CP(clk[1]));
 snl_ffqx1 r3 (.Q(out),
    .D(u2z),
    .CP(clk[2]));
 snl_bufx1 u1 (.Z(u1z),
    .A(r2q));
 snl_and02x1 u2 (.Z(u2z),
    .A(r1q),
    .B(u1z));
endmodule