data/full_repos/permissive/160794640/example/genvarexample.v
 line:1: before: "NUM_SOURCES"
data/verilator_xmls/ab9d56d2-1683-49df-8fb1-d21debdaaeb6.xml
module myinstance(input clk, input rst, output logic [31:0] counter);

always @(posedge clk or posedge rst)
  if (rst)
    counter <= '0;
  else
    counter <= counter + 1;

endmodule
module myinstance(input clk, input rst, output logic [31:0] counter);


always @(posedge clk or posedge rst)
  if (rst)
    counter <= '0;
  else
    counter <= counter + 1;

endmodule