data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/syncCorrector.v
1: b'%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/syncCorrector.v:85: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                 : ... In instance syncCorrector.vdect\n    lowCount <= 24\'d0;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/syncCorrector.v:86: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                 : ... In instance syncCorrector.vdect\n    highCount <= 24\'d0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/syncCorrector.v:92: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                 : ... In instance syncCorrector.vdect\n        lowCount <= 24\'d0;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/syncCorrector.v:93: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                 : ... In instance syncCorrector.vdect\n        highCount <= 24\'d0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/syncCorrector.v:99: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                 : ... In instance syncCorrector.vdect\n        lowCount <= 24\'d0;\n                 ^~\n%Error: Exiting due to 5 warning(s)\n'
module syncCorrector(
  input wire pxlClk,
  input wire rst,
  
  input wire vsync,
  input wire hsync,
  input wire de,
  
  output wire vsync_o,
  output wire hsync_o,
  output wire de_o
);

wire normalVsync, normalHsync;

syncPolDecter hdect (
  .pxlClk(pxlClk),
  .rst(rst),
  
  .sync(hsync),
  .normalSync(normalHsync)
);

syncPolDecter vdect (
  .pxlClk(pxlClk),
  .rst(rst),
  
  .sync(vsync),
  .normalSync(normalVsync)
);

assign de_o = de && hsync_o && vsync_o;
assign hsync_o = normalHsync == hsync;
assign vsync_o = normalVsync == vsync;



endmodule
module syncCorrector(
  input wire pxlClk,
  input wire rst,
  
  input wire vsync,
  input wire hsync,
  input wire de,
  
  output wire vsync_o,
  output wire hsync_o,
  output wire de_o
);


wire normalVsync, normalHsync;

syncPolDecter hdect (
  .pxlClk(pxlClk),
  .rst(rst),
  
  .sync(hsync),
  .normalSync(normalHsync)
);

syncPolDecter vdect (
  .pxlClk(pxlClk),
  .rst(rst),
  
  .sync(vsync),
  .normalSync(normalVsync)
);

assign de_o = de && hsync_o && vsync_o;
assign hsync_o = normalHsync == hsync;
assign vsync_o = normalVsync == vsync;



endmodule