data/full_repos/permissive/123796236/reg_file.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123796236/reg_file.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100 clk <= ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123796236/reg_file.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #300 regWriteCtrl = 1;\n  ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reg_file(readData1,
readData2,
readRegister1,
readRegister2,
writeRegister,
writeData, 
regWriteCtrl,
clk);

output reg [31:0] readData1, readData2;
input [4:0] readRegister1, readRegister2, writeRegister;
input [31:0] writeData;
input clk, regWriteCtrl;

reg [31:0] reg_file_Array [31:0];

initial 
	begin
$readmemb("C:\\Users\\Ibrahim\\Desktop\\pipeline\\reg_file.txt", reg_file_Array);
	end
always@(readRegister1 or reg_file_Array[readRegister1])
	begin
		readData1 = reg_file_Array[readRegister1];
	end

always@(readRegister2 or reg_file_Array[readRegister2])
	begin
		readData2 = reg_file_Array[readRegister2];
	end

always@(negedge clk)
	begin
		if(regWriteCtrl)
			reg_file_Array[writeRegister] <= writeData;
	end

endmodule
module reg_file(readData1,
readData2,
readRegister1,
readRegister2,
writeRegister,
writeData, 
regWriteCtrl,
clk);


output reg [31:0] readData1, readData2;
input [4:0] readRegister1, readRegister2, writeRegister;
input [31:0] writeData;
input clk, regWriteCtrl;

reg [31:0] reg_file_Array [31:0];

initial 
	begin
$readmemb("C:\\Users\\Ibrahim\\Desktop\\pipeline\\reg_file.txt", reg_file_Array);
	end
always@(readRegister1 or reg_file_Array[readRegister1])
	begin
		readData1 = reg_file_Array[readRegister1];
	end

always@(readRegister2 or reg_file_Array[readRegister2])
	begin
		readData2 = reg_file_Array[readRegister2];
	end

always@(negedge clk)
	begin
		if(regWriteCtrl)
			reg_file_Array[writeRegister] <= writeData;
	end

endmodule