data/full_repos/permissive/211316121/lab5_4_nexys4/74LS194.v
data/verilator_xmls/72844cc1-2a5b-49c9-8cdc-211970544e33.xml
module LS194(
	input [3:0] D,
	input SL,
	input SR,
	input S0,
	input S1,
	input CP,
	input CR,
	output reg [3:0] Q
);

always@(posedge CP,negedge CR)
if(~CR)
    Q<='b0000;
else 
begin
    case({S1,S0})
        'b00:;
        'b01:
            begin
               Q<=(Q>>1);
               Q[3]<=SR;
            end
        'b10:
            begin
                Q<=(Q<<1);
                Q[0]<=SL;
            end
        'b11:Q<=D;
     endcase
end 

endmodule
module LS194(
	input [3:0] D,
	input SL,
	input SR,
	input S0,
	input S1,
	input CP,
	input CR,
	output reg [3:0] Q
);


always@(posedge CP,negedge CR)
if(~CR)
    Q<='b0000;
else 
begin
    case({S1,S0})
        'b00:;
        'b01:
            begin
               Q<=(Q>>1);
               Q[3]<=SR;
            end
        'b10:
            begin
                Q<=(Q<<1);
                Q[0]<=SL;
            end
        'b11:Q<=D;
     endcase
end 

endmodule