data/full_repos/permissive/207178704/control.v
data/verilator_xmls/deb58a63-1f4d-4a81-813b-8e31d3b19fe6.xml
module control(OP, CISEL, BSEL,OSEL,SHIFT_LA,SHIFT_LR,LOGICAL_OP);


input [2:0] OP; 


output reg CISEL;
output reg BSEL;
output reg [1:0] OSEL;
output reg SHIFT_LA;
output reg SHIFT_LR;
output reg LOGICAL_OP;





parameter [2:0]  	ADD = 3'b000,
						SUB = 3'b001,
						SRA = 3'b010,
						SRL = 3'b011,
						SLL = 3'b100,
						AND = 3'b101,
						OR  = 3'b110;
					

always @ (*)
begin
	if(OP==ADD) begin
		BSEL = 1'b0;
		CISEL = 1'b0;
		OSEL = 2'b00;
		SHIFT_LA = 0;
		SHIFT_LR = 0;
		LOGICAL_OP = 0;
	end
	else if(OP==SUB) begin
		BSEL = 1'b1;
		CISEL = 1'b1;
		OSEL = 2'b00;
		SHIFT_LA = 0;
		SHIFT_LR = 0;
		LOGICAL_OP = 0;
	end
	else if(OP==SRA) begin
		BSEL = 0;
		CISEL = 0;
		OSEL = 2'b01;
		SHIFT_LA = 1;
		SHIFT_LR = 1;
		LOGICAL_OP = 0;
	end
	else if(OP==SRL) begin
		BSEL = 0;
		CISEL = 0;
		OSEL = 2'b01;
		SHIFT_LA = 0;
		SHIFT_LR = 1;
		LOGICAL_OP = 0;
	end
	else if(OP==SLL) begin
		BSEL = 0;
		CISEL = 0;
		OSEL = 2'b01;
		SHIFT_LA = 0;
		SHIFT_LR = 0;
		LOGICAL_OP = 0;
	end
	else if(OP==AND) begin
		BSEL = 0;
		CISEL = 0;
		OSEL = 2'b10;
		SHIFT_LA = 0;
		SHIFT_LR = 0;
		LOGICAL_OP = 1;
	end
	else begin
		BSEL = 0;
		CISEL = 0;
		OSEL = 2'b10;
		SHIFT_LA = 0;
		SHIFT_LR = 0;
		LOGICAL_OP = 0;
	end
	
	
end


endmodule
module control(OP, CISEL, BSEL,OSEL,SHIFT_LA,SHIFT_LR,LOGICAL_OP);



input [2:0] OP; 


output reg CISEL;
output reg BSEL;
output reg [1:0] OSEL;
output reg SHIFT_LA;
output reg SHIFT_LR;
output reg LOGICAL_OP;





parameter [2:0]  	ADD = 3'b000,
						SUB = 3'b001,
						SRA = 3'b010,
						SRL = 3'b011,
						SLL = 3'b100,
						AND = 3'b101,
						OR  = 3'b110;
					

always @ (*)
begin
	if(OP==ADD) begin
		BSEL = 1'b0;
		CISEL = 1'b0;
		OSEL = 2'b00;
		SHIFT_LA = 0;
		SHIFT_LR = 0;
		LOGICAL_OP = 0;
	end
	else if(OP==SUB) begin
		BSEL = 1'b1;
		CISEL = 1'b1;
		OSEL = 2'b00;
		SHIFT_LA = 0;
		SHIFT_LR = 0;
		LOGICAL_OP = 0;
	end
	else if(OP==SRA) begin
		BSEL = 0;
		CISEL = 0;
		OSEL = 2'b01;
		SHIFT_LA = 1;
		SHIFT_LR = 1;
		LOGICAL_OP = 0;
	end
	else if(OP==SRL) begin
		BSEL = 0;
		CISEL = 0;
		OSEL = 2'b01;
		SHIFT_LA = 0;
		SHIFT_LR = 1;
		LOGICAL_OP = 0;
	end
	else if(OP==SLL) begin
		BSEL = 0;
		CISEL = 0;
		OSEL = 2'b01;
		SHIFT_LA = 0;
		SHIFT_LR = 0;
		LOGICAL_OP = 0;
	end
	else if(OP==AND) begin
		BSEL = 0;
		CISEL = 0;
		OSEL = 2'b10;
		SHIFT_LA = 0;
		SHIFT_LR = 0;
		LOGICAL_OP = 1;
	end
	else begin
		BSEL = 0;
		CISEL = 0;
		OSEL = 2'b10;
		SHIFT_LA = 0;
		SHIFT_LR = 0;
		LOGICAL_OP = 0;
	end
	
	
end


endmodule