data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v
 line:22: before: "."
1: b'%Warning-MULTITOP: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:347: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'fpga_top\'\nmodule fpga_top(output wire WF_NEO);\n       ^~~~~~~~\n                                                                                                : ... Top module \'WF_random_5\'\n   module WF_random_5 (\n          ^~~~~~~~~~~\n                                                                                                : ... Top module \'WF_switch_debounce\'\n   module WF_switch_debounce (\n          ^~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:26: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:28: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:34: Signal definition not found, creating implicitly: \'two_ms\'\n           .timer_pulse(two_ms));\n                        ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:262: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance fpga_top.neopixel_inst\n                   pixel_bit_cnt <= 1\'b0;\n                                 ^~\n%Error: data/full_repos/permissive/179884651/examples/WF_neopixelx1_fading_demo.v:16: Cannot find file containing module: \'SB_HFOSC\'\n  SB_HFOSC OSC_i (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.v\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.sv\n             SB_HFOSC\n             SB_HFOSC.v\n             SB_HFOSC.sv\n             obj_dir/SB_HFOSC\n             obj_dir/SB_HFOSC.v\n             obj_dir/SB_HFOSC.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module WF_neopixel_if(
    input  wire        clk,    
    input  wire        ten_us,
    output reg  [7:0]  ram_rd_addr,
    input  wire [23:0] ram_rd_data,
    output reg         DOUT
);

  parameter NUM_OF_PIXELS = 8;
  parameter [3:0] BIT1_HI = 10;                                                 
  parameter [3:0] BIT1_LO =  5;                                                 
  parameter [3:0] BIT0_HI =  5;                                                 
  parameter [3:0] BIT0_LO = 10;                                                 
  parameter [3:0] NEO_PERIOD = 15; 
  parameter [3:0] NEO_RESET = 6;



    reg [23:0]  shift_pixels;
    reg [4:0]   pixel_bit_cnt;
    reg         np_eof;
    wire        np_sof;
    reg [3:0]   np_clk_cnt;
    reg         tog_bit0;
    reg         tog_bit1;
    reg         pixel_bit_end;
    wire        phase;
    reg         phase_d;
    reg         phase_tmp;
    reg [3:0]   reset_cnt;




   always @(posedge clk)
     begin
       if (np_sof)
         begin
           np_clk_cnt <= 4'b1;

         end
       else if (phase == 1'b1)
         begin
           if (np_clk_cnt == NEO_PERIOD - 4'h1)
             begin
               np_clk_cnt     <= 4'b0;
               pixel_bit_end  <= 1'b1;
             end
           else
             np_clk_cnt <= np_clk_cnt + 4'b1;

           if (np_clk_cnt == BIT0_HI - 4'h1)
             tog_bit0 <= 1'b1;
           else
             tog_bit0 <= 1'b0;

           if (np_clk_cnt == BIT1_HI - 4'h1)    
             tog_bit1 <= 1'b1;
           else
             tog_bit1 <= 1'b0;

           if (pixel_bit_end) pixel_bit_end <= 1'b0;
         end
     end


   always @(posedge clk)
     begin 
       if (phase==0)
         begin
           if (np_sof)
             begin
               DOUT      <= 1'b1;
               ram_rd_addr<= 8'b1;
             end
           else
             begin
               DOUT         <= 1'b0;
               shift_pixels <= ram_rd_data;
               pixel_bit_cnt<= 5'b0;
               ram_rd_addr  <= 8'b0;
               np_eof       <= 1'b0;
             end
         end
       else
         begin
           if (( shift_pixels[0] && tog_bit1) ||
               (~shift_pixels[0] && tog_bit0) )
             DOUT <= 1'b0;

           if (pixel_bit_end)
             if (pixel_bit_cnt != 23)
               begin
                 DOUT          <= 1'b1;
                 shift_pixels  <= {1'b0,shift_pixels[23:1]};
                 pixel_bit_cnt <= pixel_bit_cnt + 1'b1;
               end
             else
	       if ( ram_rd_addr != NUM_OF_PIXELS)
                 begin
                   DOUT          <= 1'b1;
                   shift_pixels  <= ram_rd_data;
                   pixel_bit_cnt <= 1'b0;
                   ram_rd_addr   <= ram_rd_addr + 8'b1;
                 end
	       else
	         begin
                   np_eof <= 1'b1;
                   DOUT   <= 1'b0; 
	         end
         end
     end



   always @(posedge clk)
     begin
       if (phase_tmp == 0)
	 begin
           if (ten_us)
             begin
               if (reset_cnt == NEO_RESET)
                 begin
                   phase_tmp <= 1'b1;
                   reset_cnt <= 'd0;
                 end
               else
                 reset_cnt <= reset_cnt + 'd1;
             end	 
         end

      if (np_eof)
        phase_tmp <= 1'b0;


      phase_d <= phase_tmp;

    end

    assign np_sof =  ~phase_d && phase_tmp; 
    assign phase = phase_d;

endmodule
module WF_neopixel_if(
    input  wire        clk,    
    input  wire        ten_us,
    output reg  [7:0]  ram_rd_addr,
    input  wire [23:0] ram_rd_data,
    output reg         DOUT
);


  parameter NUM_OF_PIXELS = 8;
  parameter [3:0] BIT1_HI = 10;                                                 
  parameter [3:0] BIT1_LO =  5;                                                 
  parameter [3:0] BIT0_HI =  5;                                                 
  parameter [3:0] BIT0_LO = 10;                                                 
  parameter [3:0] NEO_PERIOD = 15; 
  parameter [3:0] NEO_RESET = 6;



    reg [23:0]  shift_pixels;
    reg [4:0]   pixel_bit_cnt;
    reg         np_eof;
    wire        np_sof;
    reg [3:0]   np_clk_cnt;
    reg         tog_bit0;
    reg         tog_bit1;
    reg         pixel_bit_end;
    wire        phase;
    reg         phase_d;
    reg         phase_tmp;
    reg [3:0]   reset_cnt;




   always @(posedge clk)
     begin
       if (np_sof)
         begin
           np_clk_cnt <= 4'b1;

         end
       else if (phase == 1'b1)
         begin
           if (np_clk_cnt == NEO_PERIOD - 4'h1)
             begin
               np_clk_cnt     <= 4'b0;
               pixel_bit_end  <= 1'b1;
             end
           else
             np_clk_cnt <= np_clk_cnt + 4'b1;

           if (np_clk_cnt == BIT0_HI - 4'h1)
             tog_bit0 <= 1'b1;
           else
             tog_bit0 <= 1'b0;

           if (np_clk_cnt == BIT1_HI - 4'h1)    
             tog_bit1 <= 1'b1;
           else
             tog_bit1 <= 1'b0;

           if (pixel_bit_end) pixel_bit_end <= 1'b0;
         end
     end


   always @(posedge clk)
     begin 
       if (phase==0)
         begin
           if (np_sof)
             begin
               DOUT      <= 1'b1;
               ram_rd_addr<= 8'b1;
             end
           else
             begin
               DOUT         <= 1'b0;
               shift_pixels <= ram_rd_data;
               pixel_bit_cnt<= 5'b0;
               ram_rd_addr  <= 8'b0;
               np_eof       <= 1'b0;
             end
         end
       else
         begin
           if (( shift_pixels[0] && tog_bit1) ||
               (~shift_pixels[0] && tog_bit0) )
             DOUT <= 1'b0;

           if (pixel_bit_end)
             if (pixel_bit_cnt != 23)
               begin
                 DOUT          <= 1'b1;
                 shift_pixels  <= {1'b0,shift_pixels[23:1]};
                 pixel_bit_cnt <= pixel_bit_cnt + 1'b1;
               end
             else
	       if ( ram_rd_addr != NUM_OF_PIXELS)
                 begin
                   DOUT          <= 1'b1;
                   shift_pixels  <= ram_rd_data;
                   pixel_bit_cnt <= 1'b0;
                   ram_rd_addr   <= ram_rd_addr + 8'b1;
                 end
	       else
	         begin
                   np_eof <= 1'b1;
                   DOUT   <= 1'b0; 
	         end
         end
     end



   always @(posedge clk)
     begin
       if (phase_tmp == 0)
	 begin
           if (ten_us)
             begin
               if (reset_cnt == NEO_RESET)
                 begin
                   phase_tmp <= 1'b1;
                   reset_cnt <= 'd0;
                 end
               else
                 reset_cnt <= reset_cnt + 'd1;
             end	 
         end

      if (np_eof)
        phase_tmp <= 1'b0;


      phase_d <= phase_tmp;

    end

    assign np_sof =  ~phase_d && phase_tmp; 
    assign phase = phase_d;

endmodule