data/full_repos/permissive/157494568/Part1/seven_segment_decoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/157494568/Part1/seven_segment_decoder.v:11: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'n\' generates 4 bits.\n                                                                                     : ... In instance seven_segment_decoder\n in = n;\n    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/157494568/Part1/seven_segment_decoder.v:13: Operator CASE expects 32 or 11 bits on the Case expression, but Case expression\'s VARREF \'in\' generates 1 bits.\n                                                                                     : ... In instance seven_segment_decoder\n case (in)\n ^~~~\n%Error: Exiting due to 2 warning(s)\n'
module seven_segment_decoder(n, display);

input [3:0] n;
output reg [6:0] display;
reg in;

always @* begin

	in = n;

	case (in)
	0000: display = 7'b1000000;
   0001: display = 7'b1111001;
   0010: display = 7'b0100100;
   0011: display = 7'b0110000;
   0100: display = 7'b0011001;
   0101: display = 7'b0010010;
   0110: display = 7'b0000010;
   0111: display = 7'b1111000;
   1000: display = 7'b0000000;
   1001: display = 7'b0011000;
   1010: display = 7'b0001000;
   1011: display = 7'b0000011;
   1100: display = 7'b0100111;
   1101: display = 7'b0100001;
   1110: display = 7'b0000110;
   1111: display = 7'b0001110;
	default: display = 7'b0000000;
	endcase
 end
 
endmodule
module seven_segment_decoder(n, display);


input [3:0] n;
output reg [6:0] display;
reg in;

always @* begin

	in = n;

	case (in)
	0000: display = 7'b1000000;
   0001: display = 7'b1111001;
   0010: display = 7'b0100100;
   0011: display = 7'b0110000;
   0100: display = 7'b0011001;
   0101: display = 7'b0010010;
   0110: display = 7'b0000010;
   0111: display = 7'b1111000;
   1000: display = 7'b0000000;
   1001: display = 7'b0011000;
   1010: display = 7'b0001000;
   1011: display = 7'b0000011;
   1100: display = 7'b0100111;
   1101: display = 7'b0100001;
   1110: display = 7'b0000110;
   1111: display = 7'b0001110;
	default: display = 7'b0000000;
	endcase
 end
 
endmodule