data/full_repos/permissive/205769493/src/memory.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/205769493/src/memory.v:22: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'m_instruction_memory\'\nmodule m_instruction_memory (w_bus_data, w_bus_addr);\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                       : ... Top module \'m_data_memory\'\nmodule m_data_memory (w_bus_data_inout, w_bus_addr, w_write_enable, w_reset, w_clock);\n       ^~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module m_data_memory (w_bus_data_inout, w_bus_addr, w_write_enable, w_reset, w_clock);
	inout [7:0] w_bus_data_inout;
	input [7:0] w_bus_addr;
	input w_write_enable, w_reset, w_clock;

	reg [7:0] r_data_mem [0:255];

	integer i;
	
	assign w_bus_data_inout = (w_write_enable) ? 8'bzzzzzzzz : r_data_mem[w_bus_addr];

	always @ (negedge w_clock) begin
		if (w_write_enable) r_data_mem[w_bus_addr] <= w_bus_data_inout;
		if (w_reset) for (i = 0; i < 256; i = i + 1) r_data_mem[i] <= 8'b00000000;
	end
endmodule
module m_data_memory (w_bus_data_inout, w_bus_addr, w_write_enable, w_reset, w_clock);

	inout [7:0] w_bus_data_inout;
	input [7:0] w_bus_addr;
	input w_write_enable, w_reset, w_clock;

	reg [7:0] r_data_mem [0:255];

	integer i;
	
	assign w_bus_data_inout = (w_write_enable) ? 8'bzzzzzzzz : r_data_mem[w_bus_addr];

	always @ (negedge w_clock) begin
		if (w_write_enable) r_data_mem[w_bus_addr] <= w_bus_data_inout;
		if (w_reset) for (i = 0; i < 256; i = i + 1) r_data_mem[i] <= 8'b00000000;
	end
endmodule