data/full_repos/permissive/201425860/svf/ResetInverter.v
data/verilator_xmls/efb77e86-d4f7-4fb2-98a7-e0d59f32d8b2.xml
module ResetInverter(RESET_IN, RESET_OUT);

   input     RESET_IN;
   output    RESET_OUT;

   wire      RESET_OUT;
   
   assign    RESET_OUT = ! RESET_IN ;
   
endmodule
module ResetInverter(RESET_IN, RESET_OUT);


   input     RESET_IN;
   output    RESET_OUT;

   wire      RESET_OUT;
   
   assign    RESET_OUT = ! RESET_IN ;
   
endmodule