data/full_repos/permissive/208556773/src/microstepper/mytimer_8.v
None: at end of input
data/verilator_xmls/09df2433-56ce-45f7-a724-481ce866d671.xml
module mytimer_8 (
    input               clk,
    input               resetn,
    input               start_enable,
    input  [WIDTH-1:0]  start_time,
    output [WIDTH-1:0]  timer
);
  parameter WIDTH = 8;

  reg [WIDTH-1:0] counter;
  assign timer = counter;

  always @(posedge clk) begin
  if (!resetn) begin
    counter <= 0;
  end
  else if( start_enable ) begin
    counter <= start_time;
  end
  else if( counter > 0 )
    counter <= counter - 1'b1;
end

endmodule
module mytimer_8 (
    input               clk,
    input               resetn,
    input               start_enable,
    input  [WIDTH-1:0]  start_time,
    output [WIDTH-1:0]  timer
);

  parameter WIDTH = 8;

  reg [WIDTH-1:0] counter;
  assign timer = counter;

  always @(posedge clk) begin
  if (!resetn) begin
    counter <= 0;
  end
  else if( start_enable ) begin
    counter <= start_time;
  end
  else if( counter > 0 )
    counter <= counter - 1'b1;
end

endmodule