data/full_repos/permissive/129155059/03-library/cosa.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/cosa.v:120: Unsupported: Ignoring delay on this delayed statement.\n    #1 LE = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/cosa.v:123: Unsupported: Ignoring delay on this delayed statement.\n      #1 Contador = 0;\n      ^\n%Error: data/full_repos/permissive/129155059/03-library/cosa.v:128: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n    oprA = $random(semilla);\n           ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/129155059/03-library/cosa.v:128: ../V3Ast.cpp:358: Null item passed to setOp1p\n    oprA = $random(semilla);\n         ^\n                        ... See the manual and https://verilator.org for more assistance.\n'
module SUM8(a, b, ci, s, co);
  parameter PwrC = 0;
  input [7:0] a, b;
  input ci;
  output [7:0] s;
  output co;
  wire [6:0] carry;

  Sum_comp #(PwrC) sum0(a[0],b[0], ci,s[0], carry[0]);
  Sum_comp #(PwrC) sum1(a[1],b[1], carry[0],s[1], carry[1]);
  Sum_comp #(PwrC) sum2(a[2],b[2], carry[1],s[2], carry[2]);
  Sum_comp #(PwrC) sum3(a[3],b[3], carry[2],s[3], carry[3]);
  Sum_comp #(PwrC) sum4(a[4],b[4], carry[3],s[4], carry[4]);
  Sum_comp #(PwrC) sum5(a[5],b[5], carry[4],s[5], carry[5]);
  Sum_comp #(PwrC) sum6(a[6],b[6], carry[5],s[6], carry[6]);
  Sum_comp #(PwrC) sum7(a[7],b[7], carry[6],s[7], co);

endmodule
module SUM8(a, b, ci, s, co);

  parameter PwrC = 0;
  input [7:0] a, b;
  input ci;
  output [7:0] s;
  output co;
  wire [6:0] carry;

  Sum_comp #(PwrC) sum0(a[0],b[0], ci,s[0], carry[0]);
  Sum_comp #(PwrC) sum1(a[1],b[1], carry[0],s[1], carry[1]);
  Sum_comp #(PwrC) sum2(a[2],b[2], carry[1],s[2], carry[2]);
  Sum_comp #(PwrC) sum3(a[3],b[3], carry[2],s[3], carry[3]);
  Sum_comp #(PwrC) sum4(a[4],b[4], carry[3],s[4], carry[4]);
  Sum_comp #(PwrC) sum5(a[5],b[5], carry[4],s[5], carry[5]);
  Sum_comp #(PwrC) sum6(a[6],b[6], carry[5],s[6], carry[6]);
  Sum_comp #(PwrC) sum7(a[7],b[7], carry[6],s[7], co);

endmodule