data/full_repos/permissive/101171422/de2-115/exled/exled.v
data/verilator_xmls/b619f43d-a5ad-4d75-b58e-521bedb57d85.xml
module exled
(
	input wire         clk50,
	output wire [35:0] gpio
);
	localparam FREQ = 50_000_000;

	reg [31:0] cnt;
	reg [35:0] tog;

	initial begin
		cnt <= 0;
		tog <= 0;
	end
	
	always @ (posedge clk50) begin
		if (cnt == FREQ) begin
			cnt <= 0;
			tog <= ~tog;
		end
		else
			cnt <= cnt + 1;
	end

	assign gpio = tog;
endmodule
module exled
(
	input wire         clk50,
	output wire [35:0] gpio
);

	localparam FREQ = 50_000_000;

	reg [31:0] cnt;
	reg [35:0] tog;

	initial begin
		cnt <= 0;
		tog <= 0;
	end
	
	always @ (posedge clk50) begin
		if (cnt == FREQ) begin
			cnt <= 0;
			tog <= ~tog;
		end
		else
			cnt <= cnt + 1;
	end

	assign gpio = tog;
endmodule