data/full_repos/permissive/161275071/io/c1_wait.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161275071/io/c1_wait.v:53: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'WAIT_CNT\' generates 3 bits.\n                                                                    : ... In instance c1_wait\n   if (WAIT_CNT)\n   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module c1_wait(
	input CLK_68KCLK, nAS,
	input SYSTEM_CDx,
	input nROM_ZONE, nWRAM_ZONE, nPORT_ZONE, nCARD_ZONE, nSROM_ZONE,
	input nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
	output nDTACK
);

	reg [2:0] WAIT_CNT;
	




	
	parameter WAIT_SDRAM = 4;
	
	assign nDTACK = nAS | ~WAIT_MUX;
	
	wire WAIT_MUX = (!nROM_ZONE) ? (WAIT_CNT < WAIT_SDRAM) :
			(!nWRAM_ZONE & SYSTEM_CDx) ? (WAIT_CNT < WAIT_SDRAM) :
			(!nPORT_ZONE) ? (WAIT_CNT < WAIT_SDRAM) :
			(!nCARD_ZONE) ? (WAIT_CNT < 3) :
			(!nSROM_ZONE) ? (WAIT_CNT < WAIT_SDRAM) :
			1'b1;
	

	
	always @(posedge CLK_68KCLK)
	begin
		if (!nAS)
		begin
			if (WAIT_CNT)
				WAIT_CNT <= WAIT_CNT - 1'b1;
		end
		else
		begin
			WAIT_CNT <= 5;
		end
	end
	
endmodule
module c1_wait(
	input CLK_68KCLK, nAS,
	input SYSTEM_CDx,
	input nROM_ZONE, nWRAM_ZONE, nPORT_ZONE, nCARD_ZONE, nSROM_ZONE,
	input nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
	output nDTACK
);


	reg [2:0] WAIT_CNT;
	




	
	parameter WAIT_SDRAM = 4;
	
	assign nDTACK = nAS | ~WAIT_MUX;
	
	wire WAIT_MUX = (!nROM_ZONE) ? (WAIT_CNT < WAIT_SDRAM) :
			(!nWRAM_ZONE & SYSTEM_CDx) ? (WAIT_CNT < WAIT_SDRAM) :
			(!nPORT_ZONE) ? (WAIT_CNT < WAIT_SDRAM) :
			(!nCARD_ZONE) ? (WAIT_CNT < 3) :
			(!nSROM_ZONE) ? (WAIT_CNT < WAIT_SDRAM) :
			1'b1;
	

	
	always @(posedge CLK_68KCLK)
	begin
		if (!nAS)
		begin
			if (WAIT_CNT)
				WAIT_CNT <= WAIT_CNT - 1'b1;
		end
		else
		begin
			WAIT_CNT <= 5;
		end
	end
	
endmodule