data/full_repos/permissive/129155059/03-library/tester.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/129155059/03-library/tester.v:32: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("library.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/03-library/tester.v:33: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1, tester);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/tester.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #1 LE = 0;  \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/tester.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/tester.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1 Contador = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/tester.v:52: Unsupported: Ignoring delay on this delayed statement.\n      repeat(2) #10 CLK = ~CLK;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/tester.v:54: Unsupported: Ignoring delay on this delayed statement.\n      forever #10 CLK = ~CLK;\n              ^\n%Error: data/full_repos/permissive/129155059/03-library/tester.v:58: syntax error, unexpected \'@\'\n      @(posedge ENB);\n      ^\n%Error: data/full_repos/permissive/129155059/03-library/tester.v:61: syntax error, unexpected \'@\'\n         @(posedge CLK);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/tester.v:63: Unsupported: Ignoring delay on this delayed statement.\n         #1 D = ~D;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/tester.v:67: Unsupported: Ignoring delay on this delayed statement.\n      #10 LE = 1;  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/tester.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #1 Contador = dato;\n        ^\n%Error: data/full_repos/permissive/129155059/03-library/tester.v:70: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        $display(,,"PwrCntr[%d]: %d", dir, Contador);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/tester.v:72: Unsupported: Ignoring delay on this delayed statement.\n      #1 $finish;\n      ^\n%Error: Exiting due to 5 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester(
                input      NOT,
                input      NAND,
                input      NOR,
                input      MUX,
                input      Q,
                input      Qn,
                output reg iA,
                output reg iB,
                output reg D,
                output reg SEL,
                output reg ENB,
                output reg CLK
                );

   reg [31:0]              Contador;
   reg [`Ndir:0]           dir;
   reg                     LE;
   wire [31:0]             dato;


   memTrans        m1(dir,
                      LE,
                      dato
                      );

   assign dato = (~LE)? Contador : 32'bz;

   initial begin
      $dumpfile("library.vcd");
      $dumpvars(1, tester);
   end

   initial begin
      #1 LE = 0;
      CLK = 1'b0;
      ENB = 1'b0;
      iA = 1'b0;
      iB = 1'b0;
      D = 1'b0;
      SEL = 1'b0;
      #1
      Contador = 0;
      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin
        $display("Inicializando contador %d", dir);
        #1 Contador = 0;
        $display("Contador %d: %d ",dir, Contador);
      end

      repeat(2) #10 CLK = ~CLK;
      ENB = 1'b1;
      forever #10 CLK = ~CLK;
   end

   initial begin
      @(posedge ENB);

      repeat (10) begin
         @(posedge CLK);
         {SEL, iA, iB} <= {SEL, iA, iB} + 1;
         #1 D = ~D;
      end


      #10 LE = 1;
      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin
        #1 Contador = dato;
        $display(,,"PwrCntr[%d]: %d", dir, Contador);
      end
      #1 $finish;
   end

endmodule
module tester(
                input      NOT,
                input      NAND,
                input      NOR,
                input      MUX,
                input      Q,
                input      Qn,
                output reg iA,
                output reg iB,
                output reg D,
                output reg SEL,
                output reg ENB,
                output reg CLK
                );


   reg [31:0]              Contador;
   reg [`Ndir:0]           dir;
   reg                     LE;
   wire [31:0]             dato;


   memTrans        m1(dir,
                      LE,
                      dato
                      );

   assign dato = (~LE)? Contador : 32'bz;

   initial begin
      $dumpfile("library.vcd");
      $dumpvars(1, tester);
   end

   initial begin
      #1 LE = 0;
      CLK = 1'b0;
      ENB = 1'b0;
      iA = 1'b0;
      iB = 1'b0;
      D = 1'b0;
      SEL = 1'b0;
      #1
      Contador = 0;
      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin
        $display("Inicializando contador %d", dir);
        #1 Contador = 0;
        $display("Contador %d: %d ",dir, Contador);
      end

      repeat(2) #10 CLK = ~CLK;
      ENB = 1'b1;
      forever #10 CLK = ~CLK;
   end

   initial begin
      @(posedge ENB);

      repeat (10) begin
         @(posedge CLK);
         {SEL, iA, iB} <= {SEL, iA, iB} + 1;
         #1 D = ~D;
      end


      #10 LE = 1;
      for (dir = 0; dir <= `NumPwrCntr; dir = dir + 1) begin
        #1 Contador = dato;
        $display(,,"PwrCntr[%d]: %d", dir, Contador);
      end
      #1 $finish;
   end

endmodule