data/full_repos/permissive/173670949/gtkwave/counter.v
 line:16: before: "assign"
1: b'%Error: data/full_repos/permissive/173670949/gtkwave/counter.v:18: Unsupported: Verilog 1995 deassign\n           deassign out;\n           ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter(
    input        clk,
    output [7:0] out,
    input        reset);

    reg [7:0] out;

    always @(posedge clk) begin
        out = out + 1;
    end

    always @(reset) begin
        if (reset)
           assign out = 0;
        else
           deassign out;
    end

endmodule
module counter(
    input        clk,
    output [7:0] out,
    input        reset);


    reg [7:0] out;

    always @(posedge clk) begin
        out = out + 1;
    end

    always @(reset) begin
        if (reset)
           assign out = 0;
        else
           deassign out;
    end

endmodule