data/full_repos/permissive/143278/ivltests/multiply_large.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/multiply_large.v:68: Unsupported: Ignoring delay on this delayed statement.\n                #1;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/multiply_large.v:86: Unsupported: Ignoring delay on this delayed statement.\n                #1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/multiply_large.v:104: Unsupported: Ignoring delay on this delayed statement.\n                #1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/multiply_large.v:122: Unsupported: Ignoring delay on this delayed statement.\n                #1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/multiply_large.v:140: Unsupported: Ignoring delay on this delayed statement.\n                #1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/multiply_large.v:158: Unsupported: Ignoring delay on this delayed statement.\n                #1;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/multiply_large.v:38: Operator ASSIGN expects 129 bits on the Assign RHS, but Assign RHS\'s ADD generates 130 bits.\n                                                                              : ... In instance multiply_large.mpy\n  if(b[i]) tmp=tmp + ({{N{1\'b0}}, a} << i);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/multiply_large.v:42: Operator ASSIGNW expects 65 bits on the Assign RHS, but Assign RHS\'s SEL generates 66 bits.\n                                                                              : ... In instance multiply_large.mpy\nassign sum = tmp[N:0];\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/143278/ivltests/multiply_large.v:49: Little bit endian vector: MSB < LSB of bit range: 0:64\nreg [0:(65)-1] a, b;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/143278/ivltests/multiply_large.v:50: Little bit endian vector: MSB < LSB of bit range: 0:64\nwire [0:(65)-1] c, s;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/143278/ivltests/multiply_large.v:51: Little bit endian vector: MSB < LSB of bit range: 0:64\nreg [0:(65)-1] d;\n    ^\n%Error: Exiting due to 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multiplier(a,b,sum);
parameter N=1;

input[N-1:0] a, b;
output[N-1:0] sum;

reg [(N-1)*2:0] tmp;
integer i;

always @(a or b)
	begin
	tmp = 0;
	for(i=0;i<N;i=i+1)
		begin
		if(b[i]) tmp=tmp + ({{N{1'b0}}, a} << i);
		end
	end

assign sum = tmp[N:0];

endmodule
module multiplier(a,b,sum);

parameter N=1;

input[N-1:0] a, b;
output[N-1:0] sum;

reg [(N-1)*2:0] tmp;
integer i;

always @(a or b)
	begin
	tmp = 0;
	for(i=0;i<N;i=i+1)
		begin
		if(b[i]) tmp=tmp + ({{N{1'b0}}, a} << i);
		end
	end

assign sum = tmp[N:0];

endmodule