data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new/DP.v
1: b"%Error: data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new/DP.v:94: Cannot find file containing module: 'UD_counter'\nUD_counter           #(3) COUNT  (.D(UD_D), .Q(cnt_out), .ld(UD_ld), .ud(UD_ud), .ce(UD_ce),.clk(clk), .rst(UD_rst));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new,data/full_repos/permissive/128497744/UD_counter\n             data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new,data/full_repos/permissive/128497744/UD_counter.v\n             data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new,data/full_repos/permissive/128497744/UD_counter.sv\n             UD_counter\n             UD_counter.v\n             UD_counter.sv\n             obj_dir/UD_counter\n             obj_dir/UD_counter.v\n             obj_dir/UD_counter.sv\n%Error: data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new/DP.v:95: Cannot find file containing module: 'mux_2_to_1'\nmux_2_to_1           #(5) RINMUX (.d1(sub_out), .d0(5'b0), .sel(RIN_mux_sel), .y(RIN_mux_out));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new/DP.v:96: Cannot find file containing module: 'mux_2_to_1'\nmux_2_to_1           #(4) RMUX   (.d1(R_out[3:0]), .d0(4'b0), .sel(R_mux_sel), .y(R_mux_out));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new/DP.v:97: Cannot find file containing module: 'mux_2_to_1'\nmux_2_to_1           #(4) QMUX   (.d1(X_out), .d0(4'b0), .sel(Q_mux_sel), .y(Q_mux_out));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new/DP.v:98: Cannot find file containing module: 'shift_register'\nshift_register       #(4) X      (.D(dividend), .Q(X_out), .sl(SRX_sl), .sr(1'b0), .ld(SRX_ld), .leftIn(1'b0), .rightIn(SRX_rightIn), .rst(SRX_rst), .clk(clk));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new/DP.v:99: Cannot find file containing module: 'shift_register'\nshift_register       #(4) Y      (.D(divisor),  .Q(Y_out), .sl(1'b0), .sr(1'b0), .ld(SRY_ld), .leftIn(1'b0), .rightIn(1'b0), .rst(SRY_rst), .clk(clk));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new/DP.v:100: Cannot find file containing module: 'shift_register'\nshift_register       #(5) R      (.D(RIN_mux_out), .Q({R_out}), .sl(SRR_sl), .sr(SRR_sr), .ld(SRR_ld), .leftIn(1'b0), .rightIn(SRR_rightIn), .rst(SRR_rst), .clk(clk));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new/DP.v:101: Cannot find file containing module: 'subractor'\nsubractor            #(5) SUB    (.A(R_out), .B({1'b0,Y_out}), .C(sub_out));\n^~~~~~~~~\n%Error: data/full_repos/permissive/128497744/fsm_calculator_part2/fsm_integer_divider/fsm_integer_divider.srcs/sources_1/new/DP.v:102: Cannot find file containing module: 'magnitude_comparator'\nmagnitude_comparator #(4) COMP   (.A(R_out[3:0]), .B(Y_out), .less_than(R_lt_Y));\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module DP(
input [3:0] dividend, divisor,
input clk, rst,
input [2:0] mux_cw,
input [6:0] UD_counter_cw,
input [3:0] SRX_cw,
input [1:0] SRY_cw,
input [3:0] SRR_cw,
output [7:0] sw,
output R_lt_Y_inf,
output [3:0] quotient, remainder

    );


wire R_lt_Y;
wire [2:0] cnt_out;
assign sw = {R_lt_Y, cnt_out, divisor};



wire [4:0] RIN_mux_out; 
wire [3:0] R_mux_out, Q_mux_out;
wire [4:0] sub_out;
wire [3:0] Y_out, X_out;
wire [4:0] R_out;


assign quotient = Q_mux_out;
assign remainder = R_mux_out;




            wire RIN_mux_sel;

            wire R_mux_sel;

            wire Q_mux_sel;

        wire [2:0] UD_D;
        wire UD_ld;
        wire UD_ud;
        wire UD_ce;
        wire UD_rst;


           wire SRX_rst;
           wire SRX_sl;
           wire SRX_ld;
           wire SRX_rightIn;

           wire SRY_rst;
           wire SRY_ld;

           wire SRR_rst;
           wire SRR_sl;
           wire SRR_sr;
           wire SRR_ld;
           wire SRR_rightIn;
           assign SRR_rightIn = X_out[3];

assign {RIN_mux_sel, R_mux_sel, Q_mux_sel}            = mux_cw;
assign {UD_D, UD_ld, UD_ud, UD_ce, UD_rst}            = UD_counter_cw;
assign {SRX_rst, SRX_sl, SRX_ld, SRX_rightIn}         = SRX_cw;
assign {SRY_rst, SRY_ld}                              = SRY_cw;
assign {SRR_rst, SRR_sl, SRR_sr, SRR_ld}              = SRR_cw;

assign R_lt_Y_inf = R_out[3:0] < Y_out;


UD_counter           #(3) COUNT  (.D(UD_D), .Q(cnt_out), .ld(UD_ld), .ud(UD_ud), .ce(UD_ce),.clk(clk), .rst(UD_rst));
mux_2_to_1           #(5) RINMUX (.d1(sub_out), .d0(5'b0), .sel(RIN_mux_sel), .y(RIN_mux_out));
mux_2_to_1           #(4) RMUX   (.d1(R_out[3:0]), .d0(4'b0), .sel(R_mux_sel), .y(R_mux_out));
mux_2_to_1           #(4) QMUX   (.d1(X_out), .d0(4'b0), .sel(Q_mux_sel), .y(Q_mux_out));
shift_register       #(4) X      (.D(dividend), .Q(X_out), .sl(SRX_sl), .sr(1'b0), .ld(SRX_ld), .leftIn(1'b0), .rightIn(SRX_rightIn), .rst(SRX_rst), .clk(clk));
shift_register       #(4) Y      (.D(divisor),  .Q(Y_out), .sl(1'b0), .sr(1'b0), .ld(SRY_ld), .leftIn(1'b0), .rightIn(1'b0), .rst(SRY_rst), .clk(clk));
shift_register       #(5) R      (.D(RIN_mux_out), .Q({R_out}), .sl(SRR_sl), .sr(SRR_sr), .ld(SRR_ld), .leftIn(1'b0), .rightIn(SRR_rightIn), .rst(SRR_rst), .clk(clk));
subractor            #(5) SUB    (.A(R_out), .B({1'b0,Y_out}), .C(sub_out));
magnitude_comparator #(4) COMP   (.A(R_out[3:0]), .B(Y_out), .less_than(R_lt_Y));




endmodule
module DP(
input [3:0] dividend, divisor,
input clk, rst,
input [2:0] mux_cw,
input [6:0] UD_counter_cw,
input [3:0] SRX_cw,
input [1:0] SRY_cw,
input [3:0] SRR_cw,
output [7:0] sw,
output R_lt_Y_inf,
output [3:0] quotient, remainder

    );



wire R_lt_Y;
wire [2:0] cnt_out;
assign sw = {R_lt_Y, cnt_out, divisor};



wire [4:0] RIN_mux_out; 
wire [3:0] R_mux_out, Q_mux_out;
wire [4:0] sub_out;
wire [3:0] Y_out, X_out;
wire [4:0] R_out;


assign quotient = Q_mux_out;
assign remainder = R_mux_out;




            wire RIN_mux_sel;

            wire R_mux_sel;

            wire Q_mux_sel;

        wire [2:0] UD_D;
        wire UD_ld;
        wire UD_ud;
        wire UD_ce;
        wire UD_rst;


           wire SRX_rst;
           wire SRX_sl;
           wire SRX_ld;
           wire SRX_rightIn;

           wire SRY_rst;
           wire SRY_ld;

           wire SRR_rst;
           wire SRR_sl;
           wire SRR_sr;
           wire SRR_ld;
           wire SRR_rightIn;
           assign SRR_rightIn = X_out[3];

assign {RIN_mux_sel, R_mux_sel, Q_mux_sel}            = mux_cw;
assign {UD_D, UD_ld, UD_ud, UD_ce, UD_rst}            = UD_counter_cw;
assign {SRX_rst, SRX_sl, SRX_ld, SRX_rightIn}         = SRX_cw;
assign {SRY_rst, SRY_ld}                              = SRY_cw;
assign {SRR_rst, SRR_sl, SRR_sr, SRR_ld}              = SRR_cw;

assign R_lt_Y_inf = R_out[3:0] < Y_out;


UD_counter           #(3) COUNT  (.D(UD_D), .Q(cnt_out), .ld(UD_ld), .ud(UD_ud), .ce(UD_ce),.clk(clk), .rst(UD_rst));
mux_2_to_1           #(5) RINMUX (.d1(sub_out), .d0(5'b0), .sel(RIN_mux_sel), .y(RIN_mux_out));
mux_2_to_1           #(4) RMUX   (.d1(R_out[3:0]), .d0(4'b0), .sel(R_mux_sel), .y(R_mux_out));
mux_2_to_1           #(4) QMUX   (.d1(X_out), .d0(4'b0), .sel(Q_mux_sel), .y(Q_mux_out));
shift_register       #(4) X      (.D(dividend), .Q(X_out), .sl(SRX_sl), .sr(1'b0), .ld(SRX_ld), .leftIn(1'b0), .rightIn(SRX_rightIn), .rst(SRX_rst), .clk(clk));
shift_register       #(4) Y      (.D(divisor),  .Q(Y_out), .sl(1'b0), .sr(1'b0), .ld(SRY_ld), .leftIn(1'b0), .rightIn(1'b0), .rst(SRY_rst), .clk(clk));
shift_register       #(5) R      (.D(RIN_mux_out), .Q({R_out}), .sl(SRR_sl), .sr(SRR_sr), .ld(SRR_ld), .leftIn(1'b0), .rightIn(SRR_rightIn), .rst(SRR_rst), .clk(clk));
subractor            #(5) SUB    (.A(R_out), .B({1'b0,Y_out}), .C(sub_out));
magnitude_comparator #(4) COMP   (.A(R_out[3:0]), .B(Y_out), .less_than(R_lt_Y));




endmodule