data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/dma_queue.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/dma_queue.v:60: Cannot find file containing module: 'rx_queue'\n   rx_queue\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path,data/full_repos/permissive/121277233/rx_queue\n             data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path,data/full_repos/permissive/121277233/rx_queue.v\n             data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path,data/full_repos/permissive/121277233/rx_queue.sv\n             rx_queue\n             rx_queue.v\n             rx_queue.sv\n             obj_dir/rx_queue\n             obj_dir/rx_queue.v\n             obj_dir/rx_queue.sv\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/dma_queue.v:93: Cannot find file containing module: 'dma_tx_queue'\n   dma_tx_queue\n   ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module dma_queue
#(
   parameter DATA_WIDTH = 64,
   parameter CTRL_WIDTH=DATA_WIDTH/8,
   parameter ENABLE_HEADER = 0,
   parameter STAGE_NUMBER = 'hff,
   parameter PORT_NUMBER = 0
)(



   output [DATA_WIDTH-1:0]                out_data,
   output [CTRL_WIDTH-1:0]                out_ctrl,
   output                                 out_wr,
   input                                  out_rdy,


   input  [DATA_WIDTH-1:0]                in_data,
   input  [CTRL_WIDTH-1:0]                in_ctrl,
   input                                  in_wr,
   output                                 in_rdy,


   input  [31:0]                          s_rx_axis_tdata,
   input                                  s_rx_axis_tvalid,
   input                                  s_rx_axis_tlast,
   output                                 s_rx_axis_tready,
   input  [3:0]                           s_rx_axis_tkeep,

   output                                 m_tx_axis_tvalid,
   output [31:0]                          m_tx_axis_tdata,
   output                                 m_tx_axis_tlast,
   output [3:0]                           m_tx_axis_tkeep,
   input                                  m_tx_axis_tready,


   output [11:0]                          tx_pkt_byte_cnt,
   output                                 tx_pkt_byte_cnt_vld,
   input                                  axis_aclk,
   input                                  clk,
   input                                  reset
);


   wire [9:0]     tx_pkt_word_cnt;

   wire [11:0]    rx_pkt_byte_cnt;
   wire [9:0]     rx_pkt_word_cnt;

   rx_queue
   #(
      .DATA_WIDTH(DATA_WIDTH),
      .CTRL_WIDTH(CTRL_WIDTH),
      .ENABLE_HEADER(ENABLE_HEADER),
      .STAGE_NUMBER(STAGE_NUMBER),
      .PORT_NUMBER(PORT_NUMBER)
   ) rx_queue
   (
      .out_ctrl                        (out_ctrl),
      .out_wr                          (out_wr),
      .out_data                        (out_data),
      .out_rdy                         (out_rdy),

      .s_rx_axis_aclk                  (axis_aclk),
      .s_rx_axis_tdata                 (s_rx_axis_tdata),
      .s_rx_axis_tvalid                (s_rx_axis_tvalid),
      .s_rx_axis_tlast                 (s_rx_axis_tlast),
      .s_rx_axis_tkeep                 (s_rx_axis_tkeep),
      .s_rx_axis_tready                (s_rx_axis_tready),

      .rx_pkt_good                     (rx_pkt_good),
      .rx_pkt_bad                      (rx_pkt_bad),
      .rx_pkt_dropped                  (rx_pkt_dropped),
      .rx_pkt_byte_cnt                 (rx_pkt_byte_cnt),
      .rx_pkt_word_cnt                 (rx_pkt_word_cnt),
      .rx_pkt_pulled                   (rx_pkt_pulled),


      .reset                           (reset),
      .clk                             (clk)
   );

   dma_tx_queue
   #(
      .DATA_WIDTH(DATA_WIDTH),
      .CTRL_WIDTH(CTRL_WIDTH),
      .ENABLE_HEADER(ENABLE_HEADER),
      .STAGE_NUMBER(STAGE_NUMBER)
   ) tx_queue
     (
      .in_ctrl                         (in_ctrl),
      .in_wr                           (in_wr),
      .in_data                         (in_data),
      .in_rdy                          (in_rdy),

      .m_tx_axis_aclk                  (axis_aclk),
      .m_tx_axis_tdata                 (m_tx_axis_tdata),
      .m_tx_axis_tvalid                (m_tx_axis_tvalid),
      .m_tx_axis_tlast                 (m_tx_axis_tlast),   
      .m_tx_axis_tkeep                 (m_tx_axis_tkeep),
      .m_tx_axis_tready                (m_tx_axis_tready),



      .tx_pkt_stored                   (tx_pkt_stored),
      .tx_pkt_byte_cnt                 (tx_pkt_byte_cnt),
      .tx_pkt_byte_cnt_vld             (tx_pkt_byte_cnt_vld),
      .tx_pkt_word_cnt                 (tx_pkt_word_cnt),

      .reset                           (reset),
      .clk                             (clk)
   );


endmodule
module dma_queue
#(
   parameter DATA_WIDTH = 64,
   parameter CTRL_WIDTH=DATA_WIDTH/8,
   parameter ENABLE_HEADER = 0,
   parameter STAGE_NUMBER = 'hff,
   parameter PORT_NUMBER = 0
)(



   output [DATA_WIDTH-1:0]                out_data,
   output [CTRL_WIDTH-1:0]                out_ctrl,
   output                                 out_wr,
   input                                  out_rdy,


   input  [DATA_WIDTH-1:0]                in_data,
   input  [CTRL_WIDTH-1:0]                in_ctrl,
   input                                  in_wr,
   output                                 in_rdy,


   input  [31:0]                          s_rx_axis_tdata,
   input                                  s_rx_axis_tvalid,
   input                                  s_rx_axis_tlast,
   output                                 s_rx_axis_tready,
   input  [3:0]                           s_rx_axis_tkeep,

   output                                 m_tx_axis_tvalid,
   output [31:0]                          m_tx_axis_tdata,
   output                                 m_tx_axis_tlast,
   output [3:0]                           m_tx_axis_tkeep,
   input                                  m_tx_axis_tready,


   output [11:0]                          tx_pkt_byte_cnt,
   output                                 tx_pkt_byte_cnt_vld,
   input                                  axis_aclk,
   input                                  clk,
   input                                  reset
);



   wire [9:0]     tx_pkt_word_cnt;

   wire [11:0]    rx_pkt_byte_cnt;
   wire [9:0]     rx_pkt_word_cnt;

   rx_queue
   #(
      .DATA_WIDTH(DATA_WIDTH),
      .CTRL_WIDTH(CTRL_WIDTH),
      .ENABLE_HEADER(ENABLE_HEADER),
      .STAGE_NUMBER(STAGE_NUMBER),
      .PORT_NUMBER(PORT_NUMBER)
   ) rx_queue
   (
      .out_ctrl                        (out_ctrl),
      .out_wr                          (out_wr),
      .out_data                        (out_data),
      .out_rdy                         (out_rdy),

      .s_rx_axis_aclk                  (axis_aclk),
      .s_rx_axis_tdata                 (s_rx_axis_tdata),
      .s_rx_axis_tvalid                (s_rx_axis_tvalid),
      .s_rx_axis_tlast                 (s_rx_axis_tlast),
      .s_rx_axis_tkeep                 (s_rx_axis_tkeep),
      .s_rx_axis_tready                (s_rx_axis_tready),

      .rx_pkt_good                     (rx_pkt_good),
      .rx_pkt_bad                      (rx_pkt_bad),
      .rx_pkt_dropped                  (rx_pkt_dropped),
      .rx_pkt_byte_cnt                 (rx_pkt_byte_cnt),
      .rx_pkt_word_cnt                 (rx_pkt_word_cnt),
      .rx_pkt_pulled                   (rx_pkt_pulled),


      .reset                           (reset),
      .clk                             (clk)
   );

   dma_tx_queue
   #(
      .DATA_WIDTH(DATA_WIDTH),
      .CTRL_WIDTH(CTRL_WIDTH),
      .ENABLE_HEADER(ENABLE_HEADER),
      .STAGE_NUMBER(STAGE_NUMBER)
   ) tx_queue
     (
      .in_ctrl                         (in_ctrl),
      .in_wr                           (in_wr),
      .in_data                         (in_data),
      .in_rdy                          (in_rdy),

      .m_tx_axis_aclk                  (axis_aclk),
      .m_tx_axis_tdata                 (m_tx_axis_tdata),
      .m_tx_axis_tvalid                (m_tx_axis_tvalid),
      .m_tx_axis_tlast                 (m_tx_axis_tlast),   
      .m_tx_axis_tkeep                 (m_tx_axis_tkeep),
      .m_tx_axis_tready                (m_tx_axis_tready),



      .tx_pkt_stored                   (tx_pkt_stored),
      .tx_pkt_byte_cnt                 (tx_pkt_byte_cnt),
      .tx_pkt_byte_cnt_vld             (tx_pkt_byte_cnt_vld),
      .tx_pkt_word_cnt                 (tx_pkt_word_cnt),

      .reset                           (reset),
      .clk                             (clk)
   );


endmodule