data/full_repos/permissive/200314387/verilog/registerFile/registerFile.v
 line:54: before: ">"
1: b'%Error: data/full_repos/permissive/200314387/verilog/registerFile/registerFile.v:10: Cannot find include file: ../74670/hct74670.v\n`include "../74670/hct74670.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/registerFile,data/full_repos/permissive/200314387/../74670/hct74670.v\n             data/full_repos/permissive/200314387/verilog/registerFile,data/full_repos/permissive/200314387/../74670/hct74670.v.v\n             data/full_repos/permissive/200314387/verilog/registerFile,data/full_repos/permissive/200314387/../74670/hct74670.v.sv\n             ../74670/hct74670.v\n             ../74670/hct74670.v.v\n             ../74670/hct74670.v.sv\n             obj_dir/../74670/hct74670.v\n             obj_dir/../74670/hct74670.v.v\n             obj_dir/../74670/hct74670.v.sv\n%Error: Exiting due to 1 error(s)\n'
function [7:0] get([1:0] r);
        get = {bankL_hi.registers[r], bankL_lo.registers[r]};
    endfunction
function [7:0] get([1:0] r);

        get = {bankL_hi.registers[r], bankL_lo.registers[r]};
    endfunction