data/full_repos/permissive/113654920/hdl/CRC_CAL.v
1: b"%Error: data/full_repos/permissive/113654920/hdl/CRC_CAL.v:33: Cannot find file containing module: 'CRC_CL'\nCRC_CL CF( .D(D),    \n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/CRC_CL\n             data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/CRC_CL.v\n             data/full_repos/permissive/113654920/hdl,data/full_repos/permissive/113654920/CRC_CL.sv\n             CRC_CL\n             CRC_CL.v\n             CRC_CL.sv\n             obj_dir/CRC_CL\n             obj_dir/CRC_CL.v\n             obj_dir/CRC_CL.sv\n%Error: Exiting due to 1 error(s)\n"
module CRC_CAL(CLK4, D, CRC_ARM, CRC_ENB, CRC_Q);
    input CLK4;
    input [15:0] D;
    input CRC_ARM;
    input CRC_ENB;
    output [15:0] CRC_Q;

wire [15:0] R_D;
reg  [15:0] R_Q;



CRC_CL CF(	.D(D),
				.C(R_Q),
				.Q(R_D)
				);
				
assign CRC_Q =	R_Q;


always @(posedge CLK4) begin
  if(CRC_ARM == 1'b0) begin
    R_Q <= 16'h4ABA;				
  end else if(CRC_ENB == 1'b1) begin
    R_Q <= R_D;
  end
end

endmodule
module CRC_CAL(CLK4, D, CRC_ARM, CRC_ENB, CRC_Q);

    input CLK4;
    input [15:0] D;
    input CRC_ARM;
    input CRC_ENB;
    output [15:0] CRC_Q;

wire [15:0] R_D;
reg  [15:0] R_Q;



CRC_CL CF(	.D(D),
				.C(R_Q),
				.Q(R_D)
				);
				
assign CRC_Q =	R_Q;


always @(posedge CLK4) begin
  if(CRC_ARM == 1'b0) begin
    R_Q <= 16'h4ABA;				
  end else if(CRC_ENB == 1'b1) begin
    R_Q <= R_D;
  end
end

endmodule