data/full_repos/permissive/168753118/rtl/memory/MEMORY.v
1: b"%Error: data/full_repos/permissive/168753118/rtl/memory/MEMORY.v:51: Can't find definition of variable: 'MEM_ADDR'\n                                                                   : ... Suggested alternative: 'INS_MEM_ADDR'\n      ins_mem[ins_mem_addr_in[MEM_ADDR-1:0] + 3],\n                              ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module MEMORY #(
  parameter DATA_WIDTH    = 32,
  parameter INS_MEM_ADDR  = 8,
  parameter DATA_MEM_ADDR = 6
) (


  input       clock_in,
  input       reset_in,


  input       ins_mem_valid_in,
  input       [DATA_WIDTH-1:0] ins_mem_addr_in,
  output reg  ins_mem_ready_out,
  output reg  [DATA_WIDTH-1:0] ins_mem_data_out,


  input       data_mem_valid_in,
  input       [2:0] data_mem_opcode_in,
  input       [DATA_WIDTH-1:0] data_mem_addr_in,
  input       [DATA_WIDTH-1:0] data_mem_data_in,
  output reg  data_mem_ready_out,
  output reg  [DATA_WIDTH-1:0] data_mem_data_out

);


localparam INS_MEM_LEN  = 2 ** INS_MEM_ADDR;
localparam DATA_MEM_LEN = 2 ** DATA_MEM_ADDR;


reg [7:0] ins_mem [0:INS_MEM_LEN-1];
reg [7:0] data_mem [0:DATA_MEM_LEN-1];




initial
  $readmemh("./rtl/memory/ins_mem.hex", ins_mem);


always @ ( * ) begin


  if(ins_mem_valid_in == 1'b1) begin


    ins_mem_data_out = {
      ins_mem[ins_mem_addr_in[MEM_ADDR-1:0] + 3],
      ins_mem[ins_mem_addr_in[MEM_ADDR-1:0] + 2],
      ins_mem[ins_mem_addr_in[MEM_ADDR-1:0] + 1],
      ins_mem[ins_mem_addr_in[MEM_ADDR-1:0]]
    };


    ins_mem_ready_out = 1'b1;

  end


  if(data_mem_valid_in == 1'b1) begin


  end

end


endmodule
module MEMORY #(
  parameter DATA_WIDTH    = 32,
  parameter INS_MEM_ADDR  = 8,
  parameter DATA_MEM_ADDR = 6
) (


  input       clock_in,
  input       reset_in,


  input       ins_mem_valid_in,
  input       [DATA_WIDTH-1:0] ins_mem_addr_in,
  output reg  ins_mem_ready_out,
  output reg  [DATA_WIDTH-1:0] ins_mem_data_out,


  input       data_mem_valid_in,
  input       [2:0] data_mem_opcode_in,
  input       [DATA_WIDTH-1:0] data_mem_addr_in,
  input       [DATA_WIDTH-1:0] data_mem_data_in,
  output reg  data_mem_ready_out,
  output reg  [DATA_WIDTH-1:0] data_mem_data_out

);



localparam INS_MEM_LEN  = 2 ** INS_MEM_ADDR;
localparam DATA_MEM_LEN = 2 ** DATA_MEM_ADDR;


reg [7:0] ins_mem [0:INS_MEM_LEN-1];
reg [7:0] data_mem [0:DATA_MEM_LEN-1];




initial
  $readmemh("./rtl/memory/ins_mem.hex", ins_mem);


always @ ( * ) begin


  if(ins_mem_valid_in == 1'b1) begin


    ins_mem_data_out = {
      ins_mem[ins_mem_addr_in[MEM_ADDR-1:0] + 3],
      ins_mem[ins_mem_addr_in[MEM_ADDR-1:0] + 2],
      ins_mem[ins_mem_addr_in[MEM_ADDR-1:0] + 1],
      ins_mem[ins_mem_addr_in[MEM_ADDR-1:0]]
    };


    ins_mem_ready_out = 1'b1;

  end


  if(data_mem_valid_in == 1'b1) begin


  end

end


endmodule