data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv
 line:13: before: "read_ptr"
1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv:26: Cannot find file containing module: 'counter_ll'\ncounter_ll #(D) rd_ptr_cnt(CLK, RESET, RE & ~empty,  read_ptr);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/counter_ll\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/counter_ll.v\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/counter_ll.sv\n             counter_ll\n             counter_ll.v\n             counter_ll.sv\n             obj_dir/counter_ll\n             obj_dir/counter_ll.v\n             obj_dir/counter_ll.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv:27: Cannot find file containing module: 'counter'\ncounter    #(D) wr_ptr_cnt(CLK, RESET, WE & ~OVFLOW, write_ptr);\n^~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/simple_fifo.sv:28: Cannot find file containing module: 'ffd'\nffd        #(D) fill_fd(CLK, RESET, 1'b1, next_fill, fill);\n^~~\n%Error: Exiting due to 3 error(s)\n"
module dp_ram  #( parameter          DEPTH = 11,
                  parameter          WIDTH = 16 )

                ( input              CLK,

                  input  [DEPTH-1:0] R_ADDR,
                  output [WIDTH-1:0] R_DATA,

                  input              WE,
                  input  [DEPTH-1:0] W_ADDR,
                  input  [WIDTH-1:0] W_DATA );


logic [WIDTH-1:0] ram[0:2**DEPTH-1];
logic [WIDTH-1:0] rd;

  initial
    begin
    for(int i = 0; i < (2**DEPTH); i = i + 1)
      ram[i] = '0;
    end


  always_ff@(posedge CLK)
    begin
    if(WE) ram[W_ADDR] <= W_DATA;
    rd  <= ram[R_ADDR];
    end

assign R_DATA = rd;
    
endmodule
module dp_ram  #( parameter          DEPTH = 11,
                  parameter          WIDTH = 16 )

                ( input              CLK,

                  input  [DEPTH-1:0] R_ADDR,
                  output [WIDTH-1:0] R_DATA,

                  input              WE,
                  input  [DEPTH-1:0] W_ADDR,
                  input  [WIDTH-1:0] W_DATA );



logic [WIDTH-1:0] ram[0:2**DEPTH-1];
logic [WIDTH-1:0] rd;

  initial
    begin
    for(int i = 0; i < (2**DEPTH); i = i + 1)
      ram[i] = '0;
    end


  always_ff@(posedge CLK)
    begin
    if(WE) ram[W_ADDR] <= W_DATA;
    rd  <= ram[R_ADDR];
    end

assign R_DATA = rd;
    
endmodule