data/full_repos/permissive/117026779/src/Motherboard.v
1: b'%Error: data/full_repos/permissive/117026779/src/Motherboard.v:187: Cannot find file containing module: \'Syncronizer\'\n Syncronizer #(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/Syncronizer\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/Syncronizer.v\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/Syncronizer.sv\n             Syncronizer\n             Syncronizer.v\n             Syncronizer.sv\n             obj_dir/Syncronizer\n             obj_dir/Syncronizer.v\n             obj_dir/Syncronizer.sv\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:199: Cannot find file containing module: \'MUX\'\nMUX #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:208: Cannot find file containing module: \'ROM\'\nROM #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:217: Cannot find file containing module: \'MIPS\'\nMIPS mips(\n^~~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:234: Cannot find file containing module: \'RAM\'\nRAM #(\n^~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:250: Cannot find file containing module: \'DECODER\'\nDECODER #(.INPUT_WIDTH(3)) address_decoder\n^~~~~~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:257: Cannot find file containing module: \'AND\'\nAND #(.WIDTH(3)) key_cs_and (\n^~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:262: Cannot find file containing module: \'AND\'\nAND #(.WIDTH(3)) key_ready_cs_and (\n^~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:267: Cannot find file containing module: \'AND\'\nAND #(.WIDTH(4)) vga_fifo_cs_and (\n^~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:279: Cannot find file containing module: \'ASCII_Keyboard\'\nASCII_Keyboard keyboard(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:293: Cannot find file containing module: \'TRIBUFFER\'\nTRIBUFFER #(.WIDTH(32))\n^~~~~~~~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:302: Cannot find file containing module: \'TRIBUFFER\'\nTRIBUFFER #(.WIDTH(32))\n^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Motherboard.v:312: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 35 bits.\n                                                                          : ... In instance Motherboard\nwire [31:0] ControlBus      = { {(32-12){1\'b0}}, 3\'b0, BusCycle, 3\'b0, MemRead, 3\'b0, MemWrite };\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Motherboard.v:313: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n                                                                          : ... In instance Motherboard\nwire [31:0] KeyboardSignals = { 20\'b0, keyboard_ascii, scan_code, 3\'b0, keyboard_ready};\n                            ^\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:315: Cannot find file containing module: \'FIFO\'\nFIFO #(\n^~~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:332: Cannot find file containing module: \'FIFO\'\nFIFO #(\n^~~~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:349: Cannot find file containing module: \'OR\'\nOR #(.WIDTH(2)) fifo_to_vga_cs_and (\n^~\n%Error: data/full_repos/permissive/117026779/src/Motherboard.v:354: Cannot find file containing module: \'VGA_Terminal\'\nVGA_Terminal vga_term(\n^~~~~~~~~~~~\n%Error: Exiting due to 16 error(s), 2 warning(s)\n'
module Motherboard #(parameter CLOCK_DIVIDER = 100)
(

    input wire clk100Mhz,
    input wire rst,
    input wire ps2_clk,
    input wire ps2_data,

    output wire hsync,

    output wire vsync,

    output wire [`RGB_RESOLUTION-1:0] r,
    output wire [`RGB_RESOLUTION-1:0] g,
    output wire [`RGB_RESOLUTION-1:0] b,
    input wire clk_select,
    input wire button_clock,
    output wire show_button
);




parameter ROM_SIZE      = 32'h400/4;
`define ROM_PC_RANGE    ($clog2(ROM_SIZE)+2):2




wire clk;
wire button_clock_sync;
wire cpu_clk;

wire [31:0] AddressBus, DataBus;
wire [31:0] ProgramCounter, ALUResult, RegOut1, RegOut2, RegWriteData, RegWriteAddress;
wire [31:0] Instruction;
wire [3:0] MemWrite;
wire MemRead, BusCycle;

wire text_access;
wire extern_access;
wire ram_access;
wire key_cs;
wire key_ready_cs;
wire vga_fifo_cs;

wire keyboard_ready;
wire [7:0] keyboard_ascii;
wire [7:0] scan_code;
wire [31:0] extended_count;
wire next_key;

wire vga_busy;
wire [7:0] vga_DataBus;
wire [11:0] vga_AddressBus;



assign show_button = button_clock_sync;



CLOCK_GENERATOR #(.DIVIDE(CLOCK_DIVIDER)
) clock (
    .rst(rst),
    .fast_clk(clk100Mhz),
    .slow_clk(cpu_clk)
);

 Syncronizer #(
 	.WIDTH(1),
 	.DEFAULT_DISABLED(0)
 ) button_clk (
 	.clk(clk100Mhz),
 	.rst(rst),
 	.en(1'b1),
 	.in(button_clock),
 	.sync_out(button_clock_sync)
);


MUX #(
    .WIDTH(1),
    .INPUTS(2)
) register_destination_mux (
    .select(clk_select),
    .in({ cpu_clk, button_clock_sync }),
    .out(clk)
);

ROM #(
    .LENGTH(ROM_SIZE),
    .WIDTH(32),
    .FILE_NAME("rom.mem")
) rom (
	.a(ProgramCounter[`ROM_PC_RANGE]),
	.out(Instruction)
);

MIPS mips(
    .clk(!clk),
    .rst(rst),
    .BusCycle(BusCycle),
    .MemWrite(MemWrite),
    .MemRead(MemRead),
    .AddressBus(AddressBus),
    .DataBus(DataBus),
    .ProgramCounter(ProgramCounter),
    .ALUResult(ALUResult),
    .RegOut1(RegOut1),
    .RegOut2(RegOut2),
    .RegWriteData(RegWriteData),
    .RegWriteAddress(RegWriteAddress),
    .Instruction(Instruction)
);

RAM #(
    .LENGTH(32'h1000/4),
    .USE_FILE(1),
    .WIDTH(32),
    .MINIMUM_SECTIONAL_WIDTH(8),
    .FILE_NAME("ram.mem")
) ram (
    .clk(clk),
    .we(MemWrite),
    .cs(ram_access),
    .oe(MemRead),
    .address(AddressBus[13:2]),
    .data(DataBus)
);


DECODER #(.INPUT_WIDTH(3)) address_decoder
(
	.enable(1'b1),
	.in(AddressBus[14:12]),
	.out({ ram_access, extern_access, text_access })
);

AND #(.WIDTH(3)) key_cs_and (
	.in({ extern_access, (AddressBus == `KEYBOARD_ADDRESS), MemRead}),
	.out(key_cs)
);

AND #(.WIDTH(3)) key_ready_cs_and (
	.in({ extern_access, (AddressBus == `KEYBOARD_READY_ADDRESS), MemRead}),
	.out(key_ready_cs)
);

AND #(.WIDTH(4)) vga_fifo_cs_and (
	.in({ !key_cs, !key_ready_cs, !ram_access, extern_access}),
	.out(vga_fifo_cs)
);

ONESHOT oneshot_next_key(
    .clk(!clk100Mhz),
    .rst(rst),
    .signal(key_cs),
    .out(next_key)
);

ASCII_Keyboard keyboard(
    .clk(clk100Mhz),
    .rst(rst),
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),
    .oe(key_cs),
    .next(next_key),
    .ascii(keyboard_ascii),
    .ready(keyboard_ready),
    .scan_code_reg(scan_code),
    .extended_count(extended_count),
    .command()
);

TRIBUFFER #(.WIDTH(32))
key_ready_buffer
(
	.oe(key_ready_cs),
	.in({ 31'b0, keyboard_ready }),
	.out(DataBus)
);


TRIBUFFER #(.WIDTH(32))
key_ascii_buffer
(
	.oe(key_cs),
	.in({ 24'b0, keyboard_ascii }),
	.out(DataBus)
);

wire ascii_fifo_empty, address_fifo_empty;
wire vga_cs;
wire [31:0] ControlBus      = { {(32-12){1'b0}}, 3'b0, BusCycle, 3'b0, MemRead, 3'b0, MemWrite };
wire [31:0] KeyboardSignals = { 20'b0, keyboard_ascii, scan_code, 3'b0, keyboard_ready};

FIFO #(
    .LENGTH(32),
    .WIDTH(8)
) vga_ascii_fifo (
    .clk(clk),
    .rst(rst),
    .wr_cs(vga_fifo_cs),
    .wr_en(|MemWrite),
    .rd_cs(!vga_busy),
    .rd_en(!vga_busy),
    .full(),
    .empty(ascii_fifo_empty),
    .out(vga_DataBus),
    .in(DataBus[7:0])
);


FIFO #(
    .LENGTH(32),
    .WIDTH(12)
) vga_address_fifo (
    .clk(clk),
    .rst(rst),
    .wr_cs(vga_fifo_cs),
    .wr_en(|MemWrite),
    .rd_cs(!vga_busy),
    .rd_en(!vga_busy),
    .full(),
    .empty(address_fifo_empty),
    .out(vga_AddressBus),
    .in({ 1'b0, AddressBus[10:0] })
);


OR #(.WIDTH(2)) fifo_to_vga_cs_and (
	.in({ !ascii_fifo_empty, !address_fifo_empty }),
	.out(vga_cs)
);

VGA_Terminal vga_term(
    .clk(clk100Mhz),
    .rst(rst),
    .hsync(hsync),
    .vsync(vsync),
    .r(r),
    .g(g),
    .b(b),
    .value0(ProgramCounter), .value1 (RegWriteAddress), .value2(KeyboardSignals),  .value3(32'h0),
    .value4(ALUResult),      .value5 (DataBus),         .value6(extended_count),  .value7(32'h0),
    .value8(RegOut1),        .value9 (AddressBus),      .value10(32'h0), .value11(32'h0),
    .value12(RegOut2),       .value13(ControlBus),      .value14(32'h0), .value15(32'h0),
    .value16(RegWriteData),  .value17(Instruction),     .value18(32'h0), .value19(32'h0),
    .address(vga_AddressBus),
    .data(vga_DataBus),
    .cs(vga_cs),
    .busy(vga_busy),
    .text(3'b010),
    .background(3'b000)
);








endmodule
module Motherboard #(parameter CLOCK_DIVIDER = 100)
(

    input wire clk100Mhz,
    input wire rst,
    input wire ps2_clk,
    input wire ps2_data,

    output wire hsync,

    output wire vsync,

    output wire [`RGB_RESOLUTION-1:0] r,
    output wire [`RGB_RESOLUTION-1:0] g,
    output wire [`RGB_RESOLUTION-1:0] b,
    input wire clk_select,
    input wire button_clock,
    output wire show_button
);





parameter ROM_SIZE      = 32'h400/4;
`define ROM_PC_RANGE    ($clog2(ROM_SIZE)+2):2




wire clk;
wire button_clock_sync;
wire cpu_clk;

wire [31:0] AddressBus, DataBus;
wire [31:0] ProgramCounter, ALUResult, RegOut1, RegOut2, RegWriteData, RegWriteAddress;
wire [31:0] Instruction;
wire [3:0] MemWrite;
wire MemRead, BusCycle;

wire text_access;
wire extern_access;
wire ram_access;
wire key_cs;
wire key_ready_cs;
wire vga_fifo_cs;

wire keyboard_ready;
wire [7:0] keyboard_ascii;
wire [7:0] scan_code;
wire [31:0] extended_count;
wire next_key;

wire vga_busy;
wire [7:0] vga_DataBus;
wire [11:0] vga_AddressBus;



assign show_button = button_clock_sync;



CLOCK_GENERATOR #(.DIVIDE(CLOCK_DIVIDER)
) clock (
    .rst(rst),
    .fast_clk(clk100Mhz),
    .slow_clk(cpu_clk)
);

 Syncronizer #(
 	.WIDTH(1),
 	.DEFAULT_DISABLED(0)
 ) button_clk (
 	.clk(clk100Mhz),
 	.rst(rst),
 	.en(1'b1),
 	.in(button_clock),
 	.sync_out(button_clock_sync)
);


MUX #(
    .WIDTH(1),
    .INPUTS(2)
) register_destination_mux (
    .select(clk_select),
    .in({ cpu_clk, button_clock_sync }),
    .out(clk)
);

ROM #(
    .LENGTH(ROM_SIZE),
    .WIDTH(32),
    .FILE_NAME("rom.mem")
) rom (
	.a(ProgramCounter[`ROM_PC_RANGE]),
	.out(Instruction)
);

MIPS mips(
    .clk(!clk),
    .rst(rst),
    .BusCycle(BusCycle),
    .MemWrite(MemWrite),
    .MemRead(MemRead),
    .AddressBus(AddressBus),
    .DataBus(DataBus),
    .ProgramCounter(ProgramCounter),
    .ALUResult(ALUResult),
    .RegOut1(RegOut1),
    .RegOut2(RegOut2),
    .RegWriteData(RegWriteData),
    .RegWriteAddress(RegWriteAddress),
    .Instruction(Instruction)
);

RAM #(
    .LENGTH(32'h1000/4),
    .USE_FILE(1),
    .WIDTH(32),
    .MINIMUM_SECTIONAL_WIDTH(8),
    .FILE_NAME("ram.mem")
) ram (
    .clk(clk),
    .we(MemWrite),
    .cs(ram_access),
    .oe(MemRead),
    .address(AddressBus[13:2]),
    .data(DataBus)
);


DECODER #(.INPUT_WIDTH(3)) address_decoder
(
	.enable(1'b1),
	.in(AddressBus[14:12]),
	.out({ ram_access, extern_access, text_access })
);

AND #(.WIDTH(3)) key_cs_and (
	.in({ extern_access, (AddressBus == `KEYBOARD_ADDRESS), MemRead}),
	.out(key_cs)
);

AND #(.WIDTH(3)) key_ready_cs_and (
	.in({ extern_access, (AddressBus == `KEYBOARD_READY_ADDRESS), MemRead}),
	.out(key_ready_cs)
);

AND #(.WIDTH(4)) vga_fifo_cs_and (
	.in({ !key_cs, !key_ready_cs, !ram_access, extern_access}),
	.out(vga_fifo_cs)
);

ONESHOT oneshot_next_key(
    .clk(!clk100Mhz),
    .rst(rst),
    .signal(key_cs),
    .out(next_key)
);

ASCII_Keyboard keyboard(
    .clk(clk100Mhz),
    .rst(rst),
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),
    .oe(key_cs),
    .next(next_key),
    .ascii(keyboard_ascii),
    .ready(keyboard_ready),
    .scan_code_reg(scan_code),
    .extended_count(extended_count),
    .command()
);

TRIBUFFER #(.WIDTH(32))
key_ready_buffer
(
	.oe(key_ready_cs),
	.in({ 31'b0, keyboard_ready }),
	.out(DataBus)
);


TRIBUFFER #(.WIDTH(32))
key_ascii_buffer
(
	.oe(key_cs),
	.in({ 24'b0, keyboard_ascii }),
	.out(DataBus)
);

wire ascii_fifo_empty, address_fifo_empty;
wire vga_cs;
wire [31:0] ControlBus      = { {(32-12){1'b0}}, 3'b0, BusCycle, 3'b0, MemRead, 3'b0, MemWrite };
wire [31:0] KeyboardSignals = { 20'b0, keyboard_ascii, scan_code, 3'b0, keyboard_ready};

FIFO #(
    .LENGTH(32),
    .WIDTH(8)
) vga_ascii_fifo (
    .clk(clk),
    .rst(rst),
    .wr_cs(vga_fifo_cs),
    .wr_en(|MemWrite),
    .rd_cs(!vga_busy),
    .rd_en(!vga_busy),
    .full(),
    .empty(ascii_fifo_empty),
    .out(vga_DataBus),
    .in(DataBus[7:0])
);


FIFO #(
    .LENGTH(32),
    .WIDTH(12)
) vga_address_fifo (
    .clk(clk),
    .rst(rst),
    .wr_cs(vga_fifo_cs),
    .wr_en(|MemWrite),
    .rd_cs(!vga_busy),
    .rd_en(!vga_busy),
    .full(),
    .empty(address_fifo_empty),
    .out(vga_AddressBus),
    .in({ 1'b0, AddressBus[10:0] })
);


OR #(.WIDTH(2)) fifo_to_vga_cs_and (
	.in({ !ascii_fifo_empty, !address_fifo_empty }),
	.out(vga_cs)
);

VGA_Terminal vga_term(
    .clk(clk100Mhz),
    .rst(rst),
    .hsync(hsync),
    .vsync(vsync),
    .r(r),
    .g(g),
    .b(b),
    .value0(ProgramCounter), .value1 (RegWriteAddress), .value2(KeyboardSignals),  .value3(32'h0),
    .value4(ALUResult),      .value5 (DataBus),         .value6(extended_count),  .value7(32'h0),
    .value8(RegOut1),        .value9 (AddressBus),      .value10(32'h0), .value11(32'h0),
    .value12(RegOut2),       .value13(ControlBus),      .value14(32'h0), .value15(32'h0),
    .value16(RegWriteData),  .value17(Instruction),     .value18(32'h0), .value19(32'h0),
    .address(vga_AddressBus),
    .data(vga_DataBus),
    .cs(vga_cs),
    .busy(vga_busy),
    .text(3'b010),
    .background(3'b000)
);








endmodule