data/full_repos/permissive/115035459/verilog/src/mza-test010.SB_PLL_CORE.easypll.v
 line:106: before: "="
1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test010.SB_PLL_CORE.easypll.v:5: Cannot find include file: lib/easypll.v\n`include "lib/easypll.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/easypll.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/easypll.v.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/easypll.v.sv\n             lib/easypll.v\n             lib/easypll.v.v\n             lib/easypll.v.sv\n             obj_dir/lib/easypll.v\n             obj_dir/lib/easypll.v.v\n             obj_dir/lib/easypll.v.sv\n%Error: Exiting due to 1 error(s)\n'
module mypll (
	input clock,
	output fast_clock,
	output pll_is_locked,
	output divided_clock,
	output reg [31:0] counter = 0
);
	assign divided_clock = counter[15];

	easypll my_96MHz_pll_instance (.clock_input(clock), .reset_active_low(1), .global_clock_output(fast_clock), .pll_is_locked(pll_is_locked));

	always @(posedge fast_clock) begin
		counter++;
	end
endmodule
module mypll (
	input clock,
	output fast_clock,
	output pll_is_locked,
	output divided_clock,
	output reg [31:0] counter = 0
);

	assign divided_clock = counter[15];

	easypll my_96MHz_pll_instance (.clock_input(clock), .reset_active_low(1), .global_clock_output(fast_clock), .pll_is_locked(pll_is_locked));

	always @(posedge fast_clock) begin
		counter++;
	end
endmodule