data/full_repos/permissive/216210370/soc/rtc.v
1: b"%Error: data/full_repos/permissive/216210370/soc/rtc.v:892: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.v\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:510: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:469: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:409: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:197: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module rtc0_sec_top(
  aortc_paddr,
  aortc_pclk,
  aortc_penable,
  aortc_pprot,
  aortc_prdata,
  aortc_psel,
  aortc_pwdata,
  aortc_pwrite,
  aortc_rst_n,
  etb_rtc_trig,
  i_rtc_ext_clk,
  rtc0_vic_intr,
  rtc_etb_trig,
  test_mode,
  tipc_rtc0_trust
);
input   [31:0]  aortc_paddr;         
input           aortc_pclk;          
input           aortc_penable;       
input   [2 :0]  aortc_pprot;         
input           aortc_psel;          
input   [31:0]  aortc_pwdata;        
input           aortc_pwrite;        
input           aortc_rst_n;         
input           etb_rtc_trig;        
input           i_rtc_ext_clk;       
input           test_mode;           
input           tipc_rtc0_trust;     
output  [31:0]  aortc_prdata;        
output          rtc0_vic_intr;       
output          rtc_etb_trig;        
wire    [31:0]  aortc_paddr;         
wire            aortc_pclk;          
wire            aortc_penable;       
wire    [2 :0]  aortc_pprot;         
wire    [31:0]  aortc_prdata;        
wire            aortc_psel;          
wire    [31:0]  aortc_pwdata;        
wire            aortc_pwrite;        
wire            aortc_rst_n;         
wire    [31:0]  aou_pdu_cnt;         
wire    [3 :0]  aou_pdu_cr_reg;      
wire    [19:0]  aou_pdu_div_reg;     
wire            aou_pdu_intr_mask;   
wire    [31:0]  aou_pdu_mr_reg;      
wire            etb_rtc_trig;        
wire            i_rtc_ext_clk;       
wire            int_flag;            
wire    [31:0]  pdu_aou_clr_reg;     
wire            pdu_aou_int_clr;     
wire            pdu_aou_wen_clr_sync; 
wire            pdu_aou_wen_cr;      
wire            pdu_aou_wen_div;     
wire            pdu_aou_wen_mr;      
wire            rtc0_vic_intr;       
wire            rtc_clk;             
wire            rtc_etb_trig;        
wire            test_mode;           
wire            tipc_rtc0_trust;     
wire    [31:0]  w_prdata;            
wire            w_psel;              
wire            w_pwrite;            
rtc_pdu_top  x_rtc_pdu_top (
  .aou_pdu_cnt          (aou_pdu_cnt         ),
  .aou_pdu_cr_reg       (aou_pdu_cr_reg      ),
  .aou_pdu_div_reg      (aou_pdu_div_reg     ),
  .aou_pdu_intr_mask    (aou_pdu_intr_mask   ),
  .aou_pdu_mr_reg       (aou_pdu_mr_reg      ),
  .int_flag             (int_flag            ),
  .paddr                (aortc_paddr[31:0]   ),
  .pclk                 (aortc_pclk          ),
  .pdu_aou_clr_reg      (pdu_aou_clr_reg     ),
  .pdu_aou_int_clr      (pdu_aou_int_clr     ),
  .pdu_aou_wen_clr_sync (pdu_aou_wen_clr_sync),
  .pdu_aou_wen_cr       (pdu_aou_wen_cr      ),
  .pdu_aou_wen_div      (pdu_aou_wen_div     ),
  .pdu_aou_wen_mr       (pdu_aou_wen_mr      ),
  .penable              (aortc_penable       ),
  .prdata               (w_prdata[31:0]      ),
  .presetn              (aortc_rst_n         ),
  .psel                 (w_psel              ),
  .pwdata               (aortc_pwdata[31:0]  ),
  .pwrite               (w_pwrite            ),
  .rtc_clk              (rtc_clk             ),
  .test_mode            (test_mode           )
);
rtc_aou_top  x_rtc_aou_top (
  .aou_pdu_cnt          (aou_pdu_cnt         ),
  .aou_pdu_cr_reg       (aou_pdu_cr_reg      ),
  .aou_pdu_div_reg      (aou_pdu_div_reg     ),
  .aou_pdu_intr_mask    (aou_pdu_intr_mask   ),
  .aou_pdu_mr_reg       (aou_pdu_mr_reg      ),
  .etb_rtc_trig         (etb_rtc_trig        ),
  .i_rtc_ext_clk        (i_rtc_ext_clk       ),
  .int_flag             (int_flag            ),
  .pclk                 (aortc_pclk          ),
  .pdu_aou_clr_reg      (pdu_aou_clr_reg     ),
  .pdu_aou_int_clr      (pdu_aou_int_clr     ),
  .pdu_aou_pwdata       (aortc_pwdata[31:0]  ),
  .pdu_aou_wen_clr_sync (pdu_aou_wen_clr_sync),
  .pdu_aou_wen_cr       (pdu_aou_wen_cr      ),
  .pdu_aou_wen_div      (pdu_aou_wen_div     ),
  .pdu_aou_wen_mr       (pdu_aou_wen_mr      ),
  .rtc0_vic_intr        (rtc0_vic_intr       ),
  .rtc_clk              (rtc_clk             ),
  .rtc_etb_trig         (rtc_etb_trig        ),
  .rtc_por_rst_n        (aortc_rst_n         ),
  .test_mode            (test_mode           )
);
assign aortc_prdata[31:0] = w_prdata[31:0];
assign w_pwrite = aortc_pwrite;
assign w_psel = aortc_psel;
endmodule
module rtc0_sec_top(
  aortc_paddr,
  aortc_pclk,
  aortc_penable,
  aortc_pprot,
  aortc_prdata,
  aortc_psel,
  aortc_pwdata,
  aortc_pwrite,
  aortc_rst_n,
  etb_rtc_trig,
  i_rtc_ext_clk,
  rtc0_vic_intr,
  rtc_etb_trig,
  test_mode,
  tipc_rtc0_trust
);

input   [31:0]  aortc_paddr;         
input           aortc_pclk;          
input           aortc_penable;       
input   [2 :0]  aortc_pprot;         
input           aortc_psel;          
input   [31:0]  aortc_pwdata;        
input           aortc_pwrite;        
input           aortc_rst_n;         
input           etb_rtc_trig;        
input           i_rtc_ext_clk;       
input           test_mode;           
input           tipc_rtc0_trust;     
output  [31:0]  aortc_prdata;        
output          rtc0_vic_intr;       
output          rtc_etb_trig;        
wire    [31:0]  aortc_paddr;         
wire            aortc_pclk;          
wire            aortc_penable;       
wire    [2 :0]  aortc_pprot;         
wire    [31:0]  aortc_prdata;        
wire            aortc_psel;          
wire    [31:0]  aortc_pwdata;        
wire            aortc_pwrite;        
wire            aortc_rst_n;         
wire    [31:0]  aou_pdu_cnt;         
wire    [3 :0]  aou_pdu_cr_reg;      
wire    [19:0]  aou_pdu_div_reg;     
wire            aou_pdu_intr_mask;   
wire    [31:0]  aou_pdu_mr_reg;      
wire            etb_rtc_trig;        
wire            i_rtc_ext_clk;       
wire            int_flag;            
wire    [31:0]  pdu_aou_clr_reg;     
wire            pdu_aou_int_clr;     
wire            pdu_aou_wen_clr_sync; 
wire            pdu_aou_wen_cr;      
wire            pdu_aou_wen_div;     
wire            pdu_aou_wen_mr;      
wire            rtc0_vic_intr;       
wire            rtc_clk;             
wire            rtc_etb_trig;        
wire            test_mode;           
wire            tipc_rtc0_trust;     
wire    [31:0]  w_prdata;            
wire            w_psel;              
wire            w_pwrite;            
rtc_pdu_top  x_rtc_pdu_top (
  .aou_pdu_cnt          (aou_pdu_cnt         ),
  .aou_pdu_cr_reg       (aou_pdu_cr_reg      ),
  .aou_pdu_div_reg      (aou_pdu_div_reg     ),
  .aou_pdu_intr_mask    (aou_pdu_intr_mask   ),
  .aou_pdu_mr_reg       (aou_pdu_mr_reg      ),
  .int_flag             (int_flag            ),
  .paddr                (aortc_paddr[31:0]   ),
  .pclk                 (aortc_pclk          ),
  .pdu_aou_clr_reg      (pdu_aou_clr_reg     ),
  .pdu_aou_int_clr      (pdu_aou_int_clr     ),
  .pdu_aou_wen_clr_sync (pdu_aou_wen_clr_sync),
  .pdu_aou_wen_cr       (pdu_aou_wen_cr      ),
  .pdu_aou_wen_div      (pdu_aou_wen_div     ),
  .pdu_aou_wen_mr       (pdu_aou_wen_mr      ),
  .penable              (aortc_penable       ),
  .prdata               (w_prdata[31:0]      ),
  .presetn              (aortc_rst_n         ),
  .psel                 (w_psel              ),
  .pwdata               (aortc_pwdata[31:0]  ),
  .pwrite               (w_pwrite            ),
  .rtc_clk              (rtc_clk             ),
  .test_mode            (test_mode           )
);
rtc_aou_top  x_rtc_aou_top (
  .aou_pdu_cnt          (aou_pdu_cnt         ),
  .aou_pdu_cr_reg       (aou_pdu_cr_reg      ),
  .aou_pdu_div_reg      (aou_pdu_div_reg     ),
  .aou_pdu_intr_mask    (aou_pdu_intr_mask   ),
  .aou_pdu_mr_reg       (aou_pdu_mr_reg      ),
  .etb_rtc_trig         (etb_rtc_trig        ),
  .i_rtc_ext_clk        (i_rtc_ext_clk       ),
  .int_flag             (int_flag            ),
  .pclk                 (aortc_pclk          ),
  .pdu_aou_clr_reg      (pdu_aou_clr_reg     ),
  .pdu_aou_int_clr      (pdu_aou_int_clr     ),
  .pdu_aou_pwdata       (aortc_pwdata[31:0]  ),
  .pdu_aou_wen_clr_sync (pdu_aou_wen_clr_sync),
  .pdu_aou_wen_cr       (pdu_aou_wen_cr      ),
  .pdu_aou_wen_div      (pdu_aou_wen_div     ),
  .pdu_aou_wen_mr       (pdu_aou_wen_mr      ),
  .rtc0_vic_intr        (rtc0_vic_intr       ),
  .rtc_clk              (rtc_clk             ),
  .rtc_etb_trig         (rtc_etb_trig        ),
  .rtc_por_rst_n        (aortc_rst_n         ),
  .test_mode            (test_mode           )
);
assign aortc_prdata[31:0] = w_prdata[31:0];
assign w_pwrite = aortc_pwrite;
assign w_psel = aortc_psel;
endmodule