data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:403: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                               : ... In instance top.wrapper.in_fifo.unhardened_fifo.mem_1r1w.synth\n                                  (N5)? { 1\'b0, 1\'b0, 1\'b0, 1\'b0 } : 1\'b0;\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:144: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                               : ... In instance top.wrapper.in_fifo.unhardened_fifo.ft.wptr\n                      (N1)? n_o : 1\'b0;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:148: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                               : ... In instance top.wrapper.in_fifo.unhardened_fifo.ft.wptr\n               (N3)? o : 1\'b0;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:665: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                               : ... In instance top.wrapper.out_fifo.mem_1r1w.synth\n                      (N2)? { 1\'b0, 1\'b0 } : 1\'b0;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:103: Operator ADD expects 3 bits on the RHS, but RHS\'s VARREF \'up_i\' generates 1 bits.\n                                                                                                                                                                               : ... In instance top.wrapper.dma_counter\n  assign { N8, N7, N6 } = { N14, N13, N12 } + up_i;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:105: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                               : ... In instance top.wrapper.dma_counter\n                            (N1)? { N8, N7, N6 } : 1\'b0;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_dma/bsg_cache_dma_ways_p_2_addr_width_p_28_data_width_p_32_block_size_in_words_p_4_sets_p_64/top.v:1206: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                                : ... In instance top.wrapper\n                       (N8)? { 1\'b0, 1\'b0 } : 1\'b0;\n                           ^\n%Error: Exiting due to 7 warning(s)\n'
module top
(
  clk_i,
  reset_i,
  dma_cmd_i,
  dma_way_i,
  dma_addr_i,
  done_o,
  snoop_word_o,
  dma_pkt_o,
  dma_pkt_v_o,
  dma_pkt_yumi_i,
  dma_data_i,
  dma_data_v_i,
  dma_data_ready_o,
  dma_data_o,
  dma_data_v_o,
  dma_data_yumi_i,
  data_mem_v_o,
  data_mem_w_o,
  data_mem_addr_o,
  data_mem_w_mask_o,
  data_mem_data_o,
  data_mem_data_i,
  dma_evict_o
);

  input [3:0] dma_cmd_i;
  input [0:0] dma_way_i;
  input [27:0] dma_addr_i;
  output [31:0] snoop_word_o;
  output [28:0] dma_pkt_o;
  input [31:0] dma_data_i;
  output [31:0] dma_data_o;
  output [7:0] data_mem_addr_o;
  output [7:0] data_mem_w_mask_o;
  output [63:0] data_mem_data_o;
  input [63:0] data_mem_data_i;
  input clk_i;
  input reset_i;
  input dma_pkt_yumi_i;
  input dma_data_v_i;
  input dma_data_yumi_i;
  output done_o;
  output dma_pkt_v_o;
  output dma_data_ready_o;
  output dma_data_v_o;
  output data_mem_v_o;
  output data_mem_w_o;
  output dma_evict_o;

  bsg_cache_dma
  wrapper
  (
    .dma_cmd_i(dma_cmd_i),
    .dma_way_i(dma_way_i),
    .dma_addr_i(dma_addr_i),
    .snoop_word_o(snoop_word_o),
    .dma_pkt_o(dma_pkt_o),
    .dma_data_i(dma_data_i),
    .dma_data_o(dma_data_o),
    .data_mem_addr_o(data_mem_addr_o),
    .data_mem_w_mask_o(data_mem_w_mask_o),
    .data_mem_data_o(data_mem_data_o),
    .data_mem_data_i(data_mem_data_i),
    .clk_i(clk_i),
    .reset_i(reset_i),
    .dma_pkt_yumi_i(dma_pkt_yumi_i),
    .dma_data_v_i(dma_data_v_i),
    .dma_data_yumi_i(dma_data_yumi_i),
    .done_o(done_o),
    .dma_pkt_v_o(dma_pkt_v_o),
    .dma_data_ready_o(dma_data_ready_o),
    .dma_data_v_o(dma_data_v_o),
    .data_mem_v_o(data_mem_v_o),
    .data_mem_w_o(data_mem_w_o),
    .dma_evict_o(dma_evict_o)
  );


endmodule
module top
(
  clk_i,
  reset_i,
  dma_cmd_i,
  dma_way_i,
  dma_addr_i,
  done_o,
  snoop_word_o,
  dma_pkt_o,
  dma_pkt_v_o,
  dma_pkt_yumi_i,
  dma_data_i,
  dma_data_v_i,
  dma_data_ready_o,
  dma_data_o,
  dma_data_v_o,
  dma_data_yumi_i,
  data_mem_v_o,
  data_mem_w_o,
  data_mem_addr_o,
  data_mem_w_mask_o,
  data_mem_data_o,
  data_mem_data_i,
  dma_evict_o
);


  input [3:0] dma_cmd_i;
  input [0:0] dma_way_i;
  input [27:0] dma_addr_i;
  output [31:0] snoop_word_o;
  output [28:0] dma_pkt_o;
  input [31:0] dma_data_i;
  output [31:0] dma_data_o;
  output [7:0] data_mem_addr_o;
  output [7:0] data_mem_w_mask_o;
  output [63:0] data_mem_data_o;
  input [63:0] data_mem_data_i;
  input clk_i;
  input reset_i;
  input dma_pkt_yumi_i;
  input dma_data_v_i;
  input dma_data_yumi_i;
  output done_o;
  output dma_pkt_v_o;
  output dma_data_ready_o;
  output dma_data_v_o;
  output data_mem_v_o;
  output data_mem_w_o;
  output dma_evict_o;

  bsg_cache_dma
  wrapper
  (
    .dma_cmd_i(dma_cmd_i),
    .dma_way_i(dma_way_i),
    .dma_addr_i(dma_addr_i),
    .snoop_word_o(snoop_word_o),
    .dma_pkt_o(dma_pkt_o),
    .dma_data_i(dma_data_i),
    .dma_data_o(dma_data_o),
    .data_mem_addr_o(data_mem_addr_o),
    .data_mem_w_mask_o(data_mem_w_mask_o),
    .data_mem_data_o(data_mem_data_o),
    .data_mem_data_i(data_mem_data_i),
    .clk_i(clk_i),
    .reset_i(reset_i),
    .dma_pkt_yumi_i(dma_pkt_yumi_i),
    .dma_data_v_i(dma_data_v_i),
    .dma_data_yumi_i(dma_data_yumi_i),
    .done_o(done_o),
    .dma_pkt_v_o(dma_pkt_v_o),
    .dma_data_ready_o(dma_data_ready_o),
    .dma_data_v_o(dma_data_v_o),
    .data_mem_v_o(data_mem_v_o),
    .data_mem_w_o(data_mem_w_o),
    .dma_evict_o(dma_evict_o)
  );


endmodule