data/full_repos/permissive/197289583/postcode.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/0460ca91-3a97-4654-8b5a-da5d46adfdae.xml
module postcode

#(




	parameter TIMER_MAX = (15*2)-1


)

(

	input refclk,
	

	input testreq,
	output testack,
	

	output [7:0] rxout,
	input rxready,
	output rxstrobe,
	

	input [7:0] txin,
	input tx_pending
);




	reg testack_int;
	assign testack = (testreq & testack_int);
	
	



	reg[7:0] timer;
	wire timer_expired = (timer == TIMER_MAX);
	
	always @(posedge refclk or posedge testreq) begin
		if (testreq) begin

			timer <= 8'b0;
		end else begin

			if (timer <= TIMER_MAX) begin
				timer <= timer + 8'd1;
			end
		end
	end
		

	

	reg[7:0] rxshift;
	wire rx_ready = rxready;
	assign rxout = rxshift;
	assign rxstrobe = tx_done;
	

	reg[7:0] txshift;
	wire tx_ready = tx_pending;
	wire tx_done;
	assign tx_done = (state == S_INPUT_BIT0) & testreq;

	

	
	
	

	reg[4:0] state;
	
	localparam S_INITIAL		= 5'd0;
	localparam S_SHIFTONE	= 5'd1;
	localparam S_SHIFTZERO	= 5'd2;
	localparam S_OUTPUTPOLL	= 5'd3;
	localparam S_INPUTPOLL	= 5'd4;
	localparam S_INPUT_BIT7	= 5'd5;
	localparam S_INPUT_BIT6	= 5'd6;
	localparam S_INPUT_BIT5	= 5'd7;
	localparam S_INPUT_BIT4	= 5'd8;
	localparam S_INPUT_BIT3	= 5'd9;
	localparam S_INPUT_BIT2	= 5'd10;
	localparam S_INPUT_BIT1	= 5'd11;
	localparam S_INPUT_BIT0	= 5'd12;
	
	always @(posedge timer_expired) begin


		if (state == S_SHIFTONE) begin

			rxshift <= {rxshift[6:0], 1'b1};
		end else if (state == S_SHIFTZERO) begin

			rxshift <= {rxshift[6:0], 1'b0};
		end else begin

			rxshift <= rxshift;
		end
	end


	reg timer_expired_d;
	always @(posedge refclk) begin
		timer_expired_d <= timer_expired;
	end
	
	always @(posedge testreq or posedge timer_expired_d) begin
	


		if (timer_expired_d) begin



			state <= S_INITIAL;
		end else begin
		

			case (state)
				S_INITIAL:		begin

										

										testack_int <= 1'b1;


										state <= S_SHIFTONE;
									end
									
				S_SHIFTONE:		begin



										testack_int <= 1'b1;


										state <= S_SHIFTZERO;
									end
									
				S_SHIFTZERO:	begin

										



										testack_int <= rx_ready;
										state <= S_OUTPUTPOLL;
									end
									
				S_OUTPUTPOLL:	begin














										


										testack_int <= tx_ready;
										state <= S_INPUTPOLL;
									end
									
				S_INPUTPOLL:	begin





										txshift <= txin;
										

										if (!testack_int) begin

											testack_int <= tx_ready;
											state <= S_INPUTPOLL;
										end else begin

											testack_int <= txin[7];
											state <= S_INPUT_BIT7;
										end
									end
									
				S_INPUT_BIT7:	begin

										testack_int <= txshift[6];
										state <= S_INPUT_BIT6;
									end

				S_INPUT_BIT6:	begin

										testack_int <= txshift[5];
										state <= S_INPUT_BIT5;
									end

				S_INPUT_BIT5:	begin

										testack_int <= txshift[4];
										state <= S_INPUT_BIT4;
									end

				S_INPUT_BIT4:	begin

										testack_int <= txshift[3];
										state <= S_INPUT_BIT3;
									end

				S_INPUT_BIT3:	begin

										testack_int <= txshift[2];
										state <= S_INPUT_BIT2;
									end

				S_INPUT_BIT2:	begin

										testack_int <= txshift[1];
										state <= S_INPUT_BIT1;
									end

				S_INPUT_BIT1:	begin

										testack_int <= txshift[0];
										state <= S_INPUT_BIT0;
									end

				S_INPUT_BIT0:	begin



										testack_int <= tx_ready;
										state <= S_INPUTPOLL;
									end
			
				default:			begin

										state <= S_INITIAL;
									end
			endcase
		end	
	end
	
endmodule
module postcode

#(




	parameter TIMER_MAX = (15*2)-1


)

(

	input refclk,
	

	input testreq,
	output testack,
	

	output [7:0] rxout,
	input rxready,
	output rxstrobe,
	

	input [7:0] txin,
	input tx_pending
);





	reg testack_int;
	assign testack = (testreq & testack_int);
	
	



	reg[7:0] timer;
	wire timer_expired = (timer == TIMER_MAX);
	
	always @(posedge refclk or posedge testreq) begin
		if (testreq) begin

			timer <= 8'b0;
		end else begin

			if (timer <= TIMER_MAX) begin
				timer <= timer + 8'd1;
			end
		end
	end
		

	

	reg[7:0] rxshift;
	wire rx_ready = rxready;
	assign rxout = rxshift;
	assign rxstrobe = tx_done;
	

	reg[7:0] txshift;
	wire tx_ready = tx_pending;
	wire tx_done;
	assign tx_done = (state == S_INPUT_BIT0) & testreq;

	

	
	
	

	reg[4:0] state;
	
	localparam S_INITIAL		= 5'd0;
	localparam S_SHIFTONE	= 5'd1;
	localparam S_SHIFTZERO	= 5'd2;
	localparam S_OUTPUTPOLL	= 5'd3;
	localparam S_INPUTPOLL	= 5'd4;
	localparam S_INPUT_BIT7	= 5'd5;
	localparam S_INPUT_BIT6	= 5'd6;
	localparam S_INPUT_BIT5	= 5'd7;
	localparam S_INPUT_BIT4	= 5'd8;
	localparam S_INPUT_BIT3	= 5'd9;
	localparam S_INPUT_BIT2	= 5'd10;
	localparam S_INPUT_BIT1	= 5'd11;
	localparam S_INPUT_BIT0	= 5'd12;
	
	always @(posedge timer_expired) begin


		if (state == S_SHIFTONE) begin

			rxshift <= {rxshift[6:0], 1'b1};
		end else if (state == S_SHIFTZERO) begin

			rxshift <= {rxshift[6:0], 1'b0};
		end else begin

			rxshift <= rxshift;
		end
	end


	reg timer_expired_d;
	always @(posedge refclk) begin
		timer_expired_d <= timer_expired;
	end
	
	always @(posedge testreq or posedge timer_expired_d) begin
	


		if (timer_expired_d) begin



			state <= S_INITIAL;
		end else begin
		

			case (state)
				S_INITIAL:		begin

										

										testack_int <= 1'b1;


										state <= S_SHIFTONE;
									end
									
				S_SHIFTONE:		begin



										testack_int <= 1'b1;


										state <= S_SHIFTZERO;
									end
									
				S_SHIFTZERO:	begin

										



										testack_int <= rx_ready;
										state <= S_OUTPUTPOLL;
									end
									
				S_OUTPUTPOLL:	begin














										


										testack_int <= tx_ready;
										state <= S_INPUTPOLL;
									end
									
				S_INPUTPOLL:	begin





										txshift <= txin;
										

										if (!testack_int) begin

											testack_int <= tx_ready;
											state <= S_INPUTPOLL;
										end else begin

											testack_int <= txin[7];
											state <= S_INPUT_BIT7;
										end
									end
									
				S_INPUT_BIT7:	begin

										testack_int <= txshift[6];
										state <= S_INPUT_BIT6;
									end

				S_INPUT_BIT6:	begin

										testack_int <= txshift[5];
										state <= S_INPUT_BIT5;
									end

				S_INPUT_BIT5:	begin

										testack_int <= txshift[4];
										state <= S_INPUT_BIT4;
									end

				S_INPUT_BIT4:	begin

										testack_int <= txshift[3];
										state <= S_INPUT_BIT3;
									end

				S_INPUT_BIT3:	begin

										testack_int <= txshift[2];
										state <= S_INPUT_BIT2;
									end

				S_INPUT_BIT2:	begin

										testack_int <= txshift[1];
										state <= S_INPUT_BIT1;
									end

				S_INPUT_BIT1:	begin

										testack_int <= txshift[0];
										state <= S_INPUT_BIT0;
									end

				S_INPUT_BIT0:	begin



										testack_int <= tx_ready;
										state <= S_INPUTPOLL;
									end
			
				default:			begin

										state <= S_INITIAL;
									end
			endcase
		end	
	end
	
endmodule