data/full_repos/permissive/201025648/Verilog/3.55.v
 line:61 column:4: Illegal character '：'
1: b"%Error: data/full_repos/permissive/201025648/Verilog/3.55.v:61: syntax error, unexpected $end, expecting ',' or ':'\ns2   state next=s0;\n  ^\n%Error: Cannot continue\n"
module fsm_eg_mult_seg
(
input wire clk, reset, 
input wire a, b,
output wire y0, y1
);


localparam [1: 0] s0=2'b00,

s1=2'b01,
s2=2'b10;



reg [1: 0] state_reg, state_next;

always@ (posedge clk, posedge reset)
begin

if (reset)

state_reg <= s0;
else

state_reg <= state_next; 
end


always @*

case (state_reg)

s0: begin if (a)
begin

if(b)

state_next=s2;
else

state_next=s1;

end

else

state_next = s0;
end
s1: begin

if (a) 

state_next = s0;

else

state_next=s1;
end

s2： state next=s0;

default: state_next=s0

endcase

end



assign yl =(state_reg==s0)||(state_reg = s1);


assign y0 =(state_ reg== s0)&a&b;

endmodule
module fsm_eg_mult_seg
(
input wire clk, reset, 
input wire a, b,
output wire y0, y1
);



localparam [1: 0] s0=2'b00,

s1=2'b01,
s2=2'b10;



reg [1: 0] state_reg, state_next;

always@ (posedge clk, posedge reset)
begin

if (reset)

state_reg <= s0;
else

state_reg <= state_next; 
end


always @*

case (state_reg)

s0: begin if (a)
begin

if(b)

state_next=s2;
else

state_next=s1;

end

else

state_next = s0;
end
s1: begin

if (a) 

state_next = s0;

else

state_next=s1;
end

s2： state next=s0;

default: state_next=s0

endcase

end



assign yl =(state_reg==s0)||(state_reg = s1);


assign y0 =(state_ reg== s0)&a&b;

endmodule