data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:31: Cannot find include file: spio_hss_multiplexer_common.h\n`include "spio_hss_multiplexer_common.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h.v\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h.sv\n             spio_hss_multiplexer_common.h\n             spio_hss_multiplexer_common.h.v\n             spio_hss_multiplexer_common.h.sv\n             obj_dir/spio_hss_multiplexer_common.h\n             obj_dir/spio_hss_multiplexer_common.h.v\n             obj_dir/spio_hss_multiplexer_common.h.sv\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:52: Define or directive not defined: \'`SEQ_BITS\'\n  input wire [`SEQ_BITS - 1:0] ack_seq,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:55: Define or directive not defined: \'`PKT_BITS\'\n  input wire [`PKT_BITS - 1:0] pkt_data,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:60: Define or directive not defined: \'`SEQ_BITS\'\n  input wire [`SEQ_BITS - 1:0] bpkt_seq,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:61: Define or directive not defined: \'`PKT_BITS\'\n  output reg [`PKT_BITS - 1:0] bpkt_data,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:76: Define or directive not defined: \'`BUF_BITS\'\n  reg   [`BUF_BITS - 1:0] ba;       \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:77: Define or directive not defined: \'`BUF_BITS\'\n  reg   [`BUF_BITS - 1:0] br;       \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:78: Define or directive not defined: \'`BUF_BITS\'\n  reg   [`BUF_BITS - 1:0] bo;       \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:79: Define or directive not defined: \'`BUF_BITS\'\n  reg   [`BUF_BITS - 1:0] bw;       \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:80: Define or directive not defined: \'`BUF_BITS\'\n  reg   [`BUF_BITS - 1:0] nxt_ba;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:81: Define or directive not defined: \'`BUF_BITS\'\n  reg   [`BUF_BITS - 1:0] nxt_br;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:82: Define or directive not defined: \'`BUF_BITS\'\n  reg   [`BUF_BITS - 1:0] nxt_bw;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:99: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] pkt_dbuf [0 : `BUF_LEN - 1];\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:99: Define or directive not defined: \'`BUF_LEN\'\n  reg   [`PKT_BITS - 1:0] pkt_dbuf [0 : `BUF_LEN - 1];\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:100: Define or directive not defined: \'`BUF_LEN\'\n  reg                     pkt_pld  [0 : `BUF_LEN - 1];\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:105: Define or directive not defined: \'`BUF_BITS\'\n  reg   [`BUF_BITS - 1:0] seq_map [0 : `BUF_LEN - 1];\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:105: Define or directive not defined: \'`BUF_LEN\'\n  reg   [`BUF_BITS - 1:0] seq_map [0 : `BUF_LEN - 1];\n                                       ^~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:106: Define or directive not defined: \'`BUF_BITS\'\n  reg   [`BUF_BITS - 1:0] seq_to_reg;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:148: Define or directive not defined: \'`BUF_BITS\'\n  reg [`BUF_BITS - 1:0] inc_bw;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:161: Define or directive not defined: \'`BUF_BITS\'\n      bw <= `BUF_BITS\'d0;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:177: Define or directive not defined: \'`BUF_BITS\'\n      br <= `BUF_BITS\'d0;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:194: Define or directive not defined: \'`BUF_BITS\'\n      ba <= `BUF_BITS\'d0;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:217: Define or directive not defined: \'`BUF_BITS\'\n      bo <= `BUF_BITS\'d0;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:242: Define or directive not defined: \'`BUF_BITS\'\n      seq_map[bpkt_seq[`BUF_BITS - 1:0]] <= br;   \n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_pkt_store.v:249: Define or directive not defined: \'`BUF_BITS\'\n     seq_to_reg = seq_map[ack_seq[`BUF_BITS - 1:0]];\n                                  ^~~~~~~~~\n%Error: Exiting due to 25 error(s)\n'
module spio_hss_multiplexer_pkt_store
(
  input wire 		       clk,
  input wire 		       rst,




  output reg 		       empty,
  output reg 		       full,


  input wire 		       cfc_rem,
 

  input wire 		       vld_ack,
  input wire 		       vld_nak,
  input wire [`SEQ_BITS - 1:0] ack_seq,


  input wire [`PKT_BITS - 1:0] pkt_data,
  input wire 		       pkt_vld,
  output reg 		       pkt_rdy,


  input wire [`SEQ_BITS - 1:0] bpkt_seq,
  output reg [`PKT_BITS - 1:0] bpkt_data,
  output reg 		       bpkt_pres,
  output reg 		       bpkt_pld,
  input wire 		       bpkt_rq,
  output reg 		       bpkt_gt
);









  reg   [`BUF_BITS - 1:0] ba;
  reg   [`BUF_BITS - 1:0] br;
  reg   [`BUF_BITS - 1:0] bo;
  reg   [`BUF_BITS - 1:0] bw;
  reg   [`BUF_BITS - 1:0] nxt_ba;
  reg   [`BUF_BITS - 1:0] nxt_br;
  reg   [`BUF_BITS - 1:0] nxt_bw;

  reg                     nxt_full;

  reg                     unread;
  reg                     nxt_unread;

  reg                     reading;
  reg                     writing;








  reg   [`PKT_BITS - 1:0] pkt_dbuf [0 : `BUF_LEN - 1];
  reg                     pkt_pld  [0 : `BUF_LEN - 1];




  reg   [`BUF_BITS - 1:0] seq_map [0 : `BUF_LEN - 1];
  reg   [`BUF_BITS - 1:0] seq_to_reg;





  always @ (*)
    reading = bpkt_rq && unread && cfc_rem;


  always @ (*)
    writing = pkt_vld && !full;




  always @ (*)
    empty = !unread;




  always @ (posedge clk or posedge rst)
    if (rst)
      unread <= 1'b0;
    else
      unread <= nxt_unread;

  always @ (*)
    nxt_unread = (nxt_br != nxt_bw);





  always @ (posedge clk or posedge rst)
    if (rst)
      full <= 1'b0;
    else
      full <= nxt_full;


  reg [`BUF_BITS - 1:0] inc_bw;
  always @ (*)
   inc_bw = nxt_bw + 1;

  always @ (*)
   nxt_full = (nxt_ba == inc_bw);





  always @ (posedge clk or posedge rst)
    if (rst)
      bw <= `BUF_BITS'd0;
    else
      bw <= nxt_bw;

  always @ (*)
    if (writing)
      nxt_bw = bw + 1;
    else
      nxt_bw = bw;





  always @ (posedge clk or posedge rst)
    if (rst)
      br <= `BUF_BITS'd0;
    else
      br <= nxt_br;

  always @ (*)
    casex ({vld_nak, bpkt_gt})
        2'b1x:   nxt_br = seq_to_reg;
        2'b01:   nxt_br = br + 1;
        default: nxt_br = br;
    endcase





  always @ (posedge clk or posedge rst)
    if (rst)
      ba <= `BUF_BITS'd0;
    else
      ba <= nxt_ba;




  always @ (*)
    casex ({vld_nak, vld_ack, (ack_seq == bpkt_seq)})
        3'b1xx,
        3'bx10:  nxt_ba = seq_to_reg;

        3'bx11:  nxt_ba = br;

        default: nxt_ba = ba;
    endcase





  always @ (posedge clk or posedge rst)
    if (rst)
      bo <= `BUF_BITS'd0;
    else
      if (reading)
        bo <= br;
      else
        bo <= bo;





  always @ (posedge clk)
    if (writing)
      pkt_dbuf[bw] <= pkt_data;

  always @ (posedge clk)
    if (writing)
      pkt_pld[bw] <= pkt_data[1];





  always @ (posedge clk)
    if (bpkt_rq)
      seq_map[bpkt_seq[`BUF_BITS - 1:0]] <= br;





  always @ (*)
     seq_to_reg = seq_map[ack_seq[`BUF_BITS - 1:0]];





  always @ (posedge clk)
    bpkt_data <= pkt_dbuf[bo];

  always @ (*)
    bpkt_pld = pkt_pld[bo];





  always @ (posedge clk or posedge rst)
    if (rst)
      bpkt_pres <= 1'b0;
    else
      if (bpkt_rq)
        bpkt_pres <= reading;





  always @ (posedge clk or posedge rst)
    if (rst)
      bpkt_gt <= 1'b0;
    else
      bpkt_gt <= reading;





  always @ (posedge clk or posedge rst)
    if (rst)
      pkt_rdy <= 1'b0;
    else
      pkt_rdy <= !nxt_full;


endmodule
module spio_hss_multiplexer_pkt_store
(
  input wire 		       clk,
  input wire 		       rst,




  output reg 		       empty,
  output reg 		       full,


  input wire 		       cfc_rem,
 

  input wire 		       vld_ack,
  input wire 		       vld_nak,
  input wire [`SEQ_BITS - 1:0] ack_seq,


  input wire [`PKT_BITS - 1:0] pkt_data,
  input wire 		       pkt_vld,
  output reg 		       pkt_rdy,


  input wire [`SEQ_BITS - 1:0] bpkt_seq,
  output reg [`PKT_BITS - 1:0] bpkt_data,
  output reg 		       bpkt_pres,
  output reg 		       bpkt_pld,
  input wire 		       bpkt_rq,
  output reg 		       bpkt_gt
);










  reg   [`BUF_BITS - 1:0] ba;
  reg   [`BUF_BITS - 1:0] br;
  reg   [`BUF_BITS - 1:0] bo;
  reg   [`BUF_BITS - 1:0] bw;
  reg   [`BUF_BITS - 1:0] nxt_ba;
  reg   [`BUF_BITS - 1:0] nxt_br;
  reg   [`BUF_BITS - 1:0] nxt_bw;

  reg                     nxt_full;

  reg                     unread;
  reg                     nxt_unread;

  reg                     reading;
  reg                     writing;








  reg   [`PKT_BITS - 1:0] pkt_dbuf [0 : `BUF_LEN - 1];
  reg                     pkt_pld  [0 : `BUF_LEN - 1];




  reg   [`BUF_BITS - 1:0] seq_map [0 : `BUF_LEN - 1];
  reg   [`BUF_BITS - 1:0] seq_to_reg;





  always @ (*)
    reading = bpkt_rq && unread && cfc_rem;


  always @ (*)
    writing = pkt_vld && !full;




  always @ (*)
    empty = !unread;




  always @ (posedge clk or posedge rst)
    if (rst)
      unread <= 1'b0;
    else
      unread <= nxt_unread;

  always @ (*)
    nxt_unread = (nxt_br != nxt_bw);





  always @ (posedge clk or posedge rst)
    if (rst)
      full <= 1'b0;
    else
      full <= nxt_full;


  reg [`BUF_BITS - 1:0] inc_bw;
  always @ (*)
   inc_bw = nxt_bw + 1;

  always @ (*)
   nxt_full = (nxt_ba == inc_bw);





  always @ (posedge clk or posedge rst)
    if (rst)
      bw <= `BUF_BITS'd0;
    else
      bw <= nxt_bw;

  always @ (*)
    if (writing)
      nxt_bw = bw + 1;
    else
      nxt_bw = bw;





  always @ (posedge clk or posedge rst)
    if (rst)
      br <= `BUF_BITS'd0;
    else
      br <= nxt_br;

  always @ (*)
    casex ({vld_nak, bpkt_gt})
        2'b1x:   nxt_br = seq_to_reg;
        2'b01:   nxt_br = br + 1;
        default: nxt_br = br;
    endcase





  always @ (posedge clk or posedge rst)
    if (rst)
      ba <= `BUF_BITS'd0;
    else
      ba <= nxt_ba;




  always @ (*)
    casex ({vld_nak, vld_ack, (ack_seq == bpkt_seq)})
        3'b1xx,
        3'bx10:  nxt_ba = seq_to_reg;

        3'bx11:  nxt_ba = br;

        default: nxt_ba = ba;
    endcase





  always @ (posedge clk or posedge rst)
    if (rst)
      bo <= `BUF_BITS'd0;
    else
      if (reading)
        bo <= br;
      else
        bo <= bo;





  always @ (posedge clk)
    if (writing)
      pkt_dbuf[bw] <= pkt_data;

  always @ (posedge clk)
    if (writing)
      pkt_pld[bw] <= pkt_data[1];





  always @ (posedge clk)
    if (bpkt_rq)
      seq_map[bpkt_seq[`BUF_BITS - 1:0]] <= br;





  always @ (*)
     seq_to_reg = seq_map[ack_seq[`BUF_BITS - 1:0]];





  always @ (posedge clk)
    bpkt_data <= pkt_dbuf[bo];

  always @ (*)
    bpkt_pld = pkt_pld[bo];





  always @ (posedge clk or posedge rst)
    if (rst)
      bpkt_pres <= 1'b0;
    else
      if (bpkt_rq)
        bpkt_pres <= reading;





  always @ (posedge clk or posedge rst)
    if (rst)
      bpkt_gt <= 1'b0;
    else
      bpkt_gt <= reading;





  always @ (posedge clk or posedge rst)
    if (rst)
      pkt_rdy <= 1'b0;
    else
      pkt_rdy <= !nxt_full;


endmodule