data/full_repos/permissive/120851390/pod-dac-ad9116/hdl/sync_reset.v
data/verilator_xmls/e2ce9de5-ed15-4453-8c90-76ffa2641ca3.xml
module sync_reset(
 input  wire   clk,
 input  wire   async_reset,
 output wire   sync_reset
 );


reg   async_d;
reg   async_dd;
always @(posedge clk) begin
 async_d  <= async_reset;
 async_dd <= async_d;
end

assign sync_reset = async_dd | async_reset;

endmodule
module sync_reset(
 input  wire   clk,
 input  wire   async_reset,
 output wire   sync_reset
 );



reg   async_d;
reg   async_dd;
always @(posedge clk) begin
 async_d  <= async_reset;
 async_dd <= async_d;
end

assign sync_reset = async_dd | async_reset;

endmodule