data/full_repos/permissive/202237519/verilog/digitalsystem6/reg_tb.v
 line:24: before: ";"
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/reg_tb.v:1: Cannot find include file: reg.v\n`include "reg.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/reg.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/reg.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/reg.v.sv\n             reg.v\n             reg.v.v\n             reg.v.sv\n             obj_dir/reg.v\n             obj_dir/reg.v.v\n             obj_dir/reg.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/reg_tb.v:7: Unsupported: Ignoring delay on this delayed statement.\nalways #5 CLK <= ~CLK;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/reg_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("reg_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/reg_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,register_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/reg_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    SI <= 1\'b0; #50;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/reg_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    SI <= 1\'b1; #50;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/reg_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    SI <= 1\'b0; #50;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/reg_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    SI <= 1\'b1; #50;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/reg_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    SI <= 1\'b0; #50;\n                ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n'
module register_tb;

reg SI,CLK;
wire [3:0]SO;

always #5 CLK <= ~CLK;

register reg1(CLK, SI, SO);

initial begin
    $dumpfile("reg_tb.vcd");
    $dumpvars(0,register_tb);
    CLK <= 1'b0;
    SI <= 1'b0; #50;
    SI <= 1'b1; #50;
    SI <= 1'b0; #50;
    SI <= 1'b1; #50;
    SI <= 1'b0; #50;
    $finish;
end

endmodule
module register_tb;


reg SI,CLK;
wire [3:0]SO;

always #5 CLK <= ~CLK;

register reg1(CLK, SI, SO);

initial begin
    $dumpfile("reg_tb.vcd");
    $dumpvars(0,register_tb);
    CLK <= 1'b0;
    SI <= 1'b0; #50;
    SI <= 1'b1; #50;
    SI <= 1'b0; #50;
    SI <= 1'b1; #50;
    SI <= 1'b0; #50;
    $finish;
end

endmodule