data/full_repos/permissive/135820056/rtl/jt12/adpcm/jt10_adpcmb_gain.v
data/verilator_xmls/caec7bd2-2fec-487d-b6f7-c58915962b61.xml
module jt10_adpcmb_gain(
    input                    rst_n,
    input                    clk,
    input                    cen55,
    input             [ 7:0] tl,
    input      signed [15:0] pcm_in,
    output reg signed [15:0] pcm_out
);

wire signed [15:0] factor = {8'd0, tl};
wire signed [31:0] pcm_mul = pcm_in * factor;

always @(posedge clk) if(cen55)
    pcm_out <= pcm_mul[23:8];

endmodule
module jt10_adpcmb_gain(
    input                    rst_n,
    input                    clk,
    input                    cen55,
    input             [ 7:0] tl,
    input      signed [15:0] pcm_in,
    output reg signed [15:0] pcm_out
);


wire signed [15:0] factor = {8'd0, tl};
wire signed [31:0] pcm_mul = pcm_in * factor;

always @(posedge clk) if(cen55)
    pcm_out <= pcm_mul[23:8];

endmodule