data/full_repos/permissive/168753118/rtl/Core101.v
1: b"%Error: data/full_repos/permissive/168753118/rtl/Core101.v:147: Cannot find file containing module: 'PC_CALC'\nPC_CALC #(.XLEN(XLEN)) pc_calc (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/168753118/rtl,data/full_repos/permissive/168753118/PC_CALC\n             data/full_repos/permissive/168753118/rtl,data/full_repos/permissive/168753118/PC_CALC.v\n             data/full_repos/permissive/168753118/rtl,data/full_repos/permissive/168753118/PC_CALC.sv\n             PC_CALC\n             PC_CALC.v\n             PC_CALC.sv\n             obj_dir/PC_CALC\n             obj_dir/PC_CALC.v\n             obj_dir/PC_CALC.sv\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:163: Cannot find file containing module: 'REG'\nREG #(.XLEN(PC_IF_WIDTH)) pc_if_pipeline_reg (\n^~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:180: Cannot find file containing module: 'PREDICTOR'\nPREDICTOR predictor0 (\n^~~~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:195: Cannot find file containing module: 'REG'\nREG #(.XLEN(IF_DEC_WIDTH)) if_dec_pipeline_reg (\n^~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:210: Cannot find file containing module: 'FORWARDING_UNIT'\nFORWARDING_UNIT forwarding_unit0 (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:218: Cannot find file containing module: 'IMM_GEN'\nIMM_GEN imm_gen (\n^~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:225: Cannot find file containing module: 'DECODE_UNIT'\nDECODE_UNIT decode0 (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:245: Cannot find file containing module: 'REG'\nREG #(.XLEN(DEC_REG_WIDTH)) dec_reg_pipeline_reg (\n^~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:270: Cannot find file containing module: 'GPR'\nGPR gpr0 (\n^~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:287: Cannot find file containing module: 'ISSUE_UNIT'\nISSUE_UNIT issue0 (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:306: Cannot find file containing module: 'REG'\nREG #(.XLEN(REG_EX_WIDTH)) reg_ex_pipeline_reg (\n^~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:336: Cannot find file containing module: 'MUX_A'\nMUX_A rs1_fwd (\n^~~~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:343: Cannot find file containing module: 'MUX_A'\nMUX_A rs2_fwd (\n^~~~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:350: Cannot find file containing module: 'MUX_A'\nMUX_A pc_mux (\n^~~~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:357: Cannot find file containing module: 'MUX_A'\nMUX_A imm_mux (\n^~~~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:365: Cannot find file containing module: 'BRU'\nBRU bru0 (\n^~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:381: Cannot find file containing module: 'ALU'\nALU alu0 (\n^~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:389: Cannot find file containing module: 'LSU'\nLSU lsu0 (\n^~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:402: Cannot find file containing module: 'ENCODE_B'\nENCODE_B ex_encoder0 (\n^~~~~~~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:408: Cannot find file containing module: 'MUX_B'\nMUX_B ex_out_mux0 (\n^~~~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:418: Cannot find file containing module: 'REG'\nREG #() ex_wb_pipeline_reg (\n^~~\n%Error: data/full_repos/permissive/168753118/rtl/Core101.v:432: Cannot find file containing module: 'PIPELINE_CONTROL'\nPIPELINE_CONTROL pipeline_control (\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n"
module Core101 (

  input clock_in,
  input reset_in,


  output ins_mem_valid_out,
  output [31:0] ins_mem_addr_out,
  input ins_mem_ready_in,
  input [31:0] ins_mem_data_in,


  output data_mem_valid_out,
  output data_mem_write_out,
  output [31:0] data_mem_addr_out,
  output [31:0] data_mem_data_out,
  input data_mem_ready_in,
  input [31:0] data_mem_data_in
);



parameter XLEN = 32;


parameter PC_IF_WIDTH = 33;
parameter IF_DEC_WIDTH = 65;
parameter DEC_REG_WIDTH = 95;
parameter REG_EX_WIDTH = 161;
parameter EX_WB_WIDTH = 10;





wire pc_calc_pred_wire;
wire [31:0] pc_calc_addr_wire;


wire [PC_IF_WIDTH-1:0] pc_if_pipeline_data_wire;


wire predictor_pred_enable_wire;
wire [31:00] predictor_pred_addr_wire;


wire [IF_DEC_WIDTH-1:0] if_dec_pipeline_data_wire;


wire [1:0] fwd_mux_sel_wire;


wire [XLEN-1:0] imm_gen_data_wire;


wire decode_imm_mux_sel_wire;
wire decode_pc_mux_sel_wire;
wire decode_rd_write_en_wire;
wire decode_rd_mux_sel_wire;
wire decode_jump_mux_sel_wire;
wire decode_invalid_ins_wire;
wire [3:0] decode_exec_unit_sel_wire;
wire [3:0] decode_exec_uop_sel_wire;


wire [DEC_REG_WIDTH-1:0] dec_reg_pipeline_data_wire;


wire [XLEN-1:0] gpr_rs1_data_wire;
wire [XLEN-1:0] gpr_rs2_data_wire;


wire issue_int_en_wire;
wire issue_vec_en_wire;
wire issue_lsu_en_wire;
wire issue_bru_en_wire;
wire [3:0] issue_int_uop_wire;
wire [3:0] issue_vec_uop_wire;
wire [3:0] issue_lsu_uop_wire;
wire [3:0] issue_bru_uop_wire;


wire [REG_EX_WIDTH-1:0] reg_ex_pipeline_data_wire;


wire [XLEN-1:0] fwd_mux_rs1_data_wire;
wire [XLEN-1:0] fwd_mux_rs2_data_wire;


wire [XLEN-1:0] pc_mux_data_wire;
wire [XLEN-1:0] imm_mux_data_wire;


wire bru_pipeline_flush_wire;
wire bru_predictor_taken_wire;
wire bru_predictor_en_wire;
wire bru_pc_enable_wire;
wire [XLEN-1:0] bru_pc_address_wire;


wire [XLEN-1:0] alu_result_wire;


wire [3:0] lsu_mem_op_wire;
wire [XLEN-1:0] lsu_data_wire;
wire [XLEN-1:0] lsu_addr_wire;
wire [XLEN-1:0] lsu_result_wire;


wire [EX_WB_WIDTH-1:0] ex_wb_pipeline_data_wire;


wire pipeline_ins_mem_valid_wire;

wire pipeline_pc_if_set_wire;
wire pipeline_if_dec_set_wire;
wire pipeline_dec_reg_set_wire;
wire pipeline_reg_ex_set_wire;
wire pipeline_ex_wb_set_wire;

wire pipeline_pc_if_clear_wire;
wire pipeline_if_dec_clear_wire;
wire pipeline_dec_reg_clear_wire;
wire pipeline_reg_ex_clear_wire;
wire pipeline_ex_wb_clear_wire;



PC_CALC #(.XLEN(XLEN)) pc_calc (

  .pc_calc_correction_en_in(bru_pc_enable_wire),
  .pc_calc_prediction_en_in(predictor_pred_enable_wire),

  .pc_calc_current_in(pc_if_pipeline_data_wire[XLEN-1:0]),

  .pc_calc_correction_in(bru_pc_address_wire),
  .pc_calc_prediction_in(predictor_pred_addr_wire),

  .pc_calc_addr_out(pc_calc_addr_wire),
  .pc_calc_pred_out(pc_calc_pred_wire)
);



REG #(.XLEN(PC_IF_WIDTH)) pc_if_pipeline_reg (
  .reg_clock_in(clock_in),
  .reg_reset_in(reset_in),
  .reg_clear_in(pipeline_pc_if_clear_wire),
  .reg_set_in(pipeline_pc_if_set_wire),
  .reg_data_in({
      pc_calc_pred_wire,
      pc_calc_addr_wire
    }),
  .reg_data_out(pc_if_pipeline_data_wire)
);


assign ins_mem_addr_out = pc_if_pipeline_data_wire[XLEN-1:0];
assign ins_mem_valid_out = pipeline_ins_mem_valid_wire;


PREDICTOR predictor0 (
  .predictor_clock_in(clock_in),
  .predictor_reset_in(reset_in),

  .predictor_pred_addr_in(pc_if_pipeline_data_wire[XLEN-1:0]),
  .predictor_pred_enable_out(predictor_pred_enable_wire),
  .predictor_pred_addr_out(predictor_pred_addr_wire),

  .predictor_feedback_result_in(),
  .predictor_feedback_write_enable_in(),
  .predictor_feedback_addr_in(),
  .predictor_feedback_return_in()
);


REG #(.XLEN(IF_DEC_WIDTH)) if_dec_pipeline_reg (
  .reg_clock_in(clock_in),
  .reg_reset_in(reset_in),
  .reg_clear_in(pipeline_if_dec_clear_wire),
  .reg_set_in(pipeline_if_dec_set_wire),
  .reg_data_in({
      pc_if_pipeline_data_wire[XLEN],
      ins_mem_data_in,
      pc_if_pipeline_data_wire[XLEN-1:0]
    }),
  .reg_data_out(if_dec_pipeline_data_wire)
);



FORWARDING_UNIT forwarding_unit0 (
  .fwd_if_ra_addr_in(if_dec_pipeline_data_wire[51:47]),
  .fwd_if_rb_addr_in(if_dec_pipeline_data_wire[56:52]),
  .fwd_id_rd_addr_in(if_dec_pipeline_data_wire[43:39]),
  .fwd_mux_sel_out(fwd_mux_sel_wire)
);


IMM_GEN imm_gen (
  .imm_gen_opcode_in(if_dec_pipeline_data_wire[38:32]),
  .imm_gen_ins_in(if_dec_pipeline_data_wire[63:39]),
  .imm_gen_data_out(imm_gen_data_wire)
);


DECODE_UNIT decode0 (
  .dec_opcode_in(if_dec_pipeline_data_wire[38:32]),
  .dec_funct3_in(if_dec_pipeline_data_wire[46:44]),
  .dec_funct7_in(if_dec_pipeline_data_wire[63:57]),

  .dec_imm_mux_sel_out(decode_imm_mux_sel_wire),
  .dec_pc_mux_sel_out(decode_pc_mux_sel_wire),
  .dec_rd_write_enable_out(decode_rd_write_en_wire),
  .dec_rd_data_sel_out(decode_rd_mux_sel_wire),
  .dec_jump_sel_out(decode_jump_mux_sel_wire),


  .dec_invalid_ins_exception(decode_invalid_ins_wire),


  .dec_exec_unit_sel_out(decode_exec_unit_sel_wire),
  .dec_exec_unit_uop_out(decode_exec_uop_sel_wire)
);


REG #(.XLEN(DEC_REG_WIDTH)) dec_reg_pipeline_reg (
  .reg_clock_in(clock_in),
  .reg_reset_in(reset_in),
  .reg_clear_in(pipeline_dec_reg_clear_wire),
  .reg_set_in(pipeline_dec_reg_set_wire),
  .reg_data_in({
      if_dec_pipeline_data_wire[64],
      decode_jump_mux_sel_wire,
      decode_rd_mux_sel_wire,
      decode_rd_write_en_wire,
      decode_imm_mux_sel_wire,
      decode_pc_mux_sel_wire,
      fwd_mux_sel_wire,
      decode_exec_unit_sel_wire,
      decode_exec_uop_sel_wire,
      if_dec_pipeline_data_wire[56:52],
      if_dec_pipeline_data_wire[51:47],
      if_dec_pipeline_data_wire[43:39],
      imm_gen_data_wire,
      if_dec_pipeline_data_wire[31:0]
    }),
  .reg_data_out(dec_reg_pipeline_data_wire)
);


GPR gpr0 (
  .clock_in(clock_in),
  .reset_in(reset_in),


  .write_enable_in(),
  .rd_addr_in(),
  .rd_data_in(),


  .rs1_addr_in(dec_reg_pipeline_data_wire[73:69]),
  .rs2_addr_in(dec_reg_pipeline_data_wire[78:74]),
  .rs1_data_out(gpr_rs1_data_wire),
  .rs2_data_out(gpr_rs2_data_wire)
);


ISSUE_UNIT issue0 (

  .exec_unit_sel_in(dec_reg_pipeline_data_wire[86:83]),
  .exec_uop_in(dec_reg_pipeline_data_wire[82:79]),


  .int_enable_out(issue_int_en_wire),
  .vec_enable_out(issue_vec_en_wire),
  .lsu_enable_out(issue_lsu_en_wire),
  .bru_enable_out(issue_bru_en_wire),


  .int_exec_uop_out(issue_int_uop_wire),
  .vec_exec_uop_out(issue_vec_uop_wire),
  .lsu_exec_uop_out(issue_lsu_uop_wire),
  .bru_exec_uop_out(issue_bru_uop_wire)
);


REG #(.XLEN(REG_EX_WIDTH)) reg_ex_pipeline_reg (
  .reg_clock_in(clock_in),
  .reg_reset_in(reset_in),
  .reg_clear_in(pipeline_reg_ex_clear_wire),
  .reg_set_in(pipeline_reg_ex_set_wire),
  .reg_data_in({
      dec_reg_pipeline_data_wire[94],
      dec_reg_pipeline_data_wire[93],
      dec_reg_pipeline_data_wire[92],
      dec_reg_pipeline_data_wire[91],
      dec_reg_pipeline_data_wire[90],
      dec_reg_pipeline_data_wire[89],
      issue_int_en_wire,
      issue_lsu_en_wire,
      issue_vec_en_wire,
      issue_bru_en_wire,
      dec_reg_pipeline_data_wire[88:87],
      issue_int_uop_wire,
      issue_lsu_uop_wire,
      issue_vec_uop_wire,
      issue_bru_uop_wire,
      dec_reg_pipeline_data_wire[68:64],
      gpr_rs2_data_wire,
      gpr_rs1_data_wire,
      dec_reg_pipeline_data_wire[63:32],
      dec_reg_pipeline_data_wire[31:0]
    }),
  .reg_data_out(reg_ex_pipeline_data_wire)
);

MUX_A rs1_fwd (
  .data_sel_in(reg_ex_pipeline_data_wire[149]),
  .a_data_src_in(reg_ex_pipeline_data_wire[95:64]),
  .b_data_src_in(),
  .data_out(fwd_mux_rs1_data_wire)
);

MUX_A rs2_fwd (
  .data_sel_in(reg_ex_pipeline_data_wire[150]),
  .a_data_src_in(reg_ex_pipeline_data_wire[127:96]),
  .b_data_src_in(),
  .data_out(fwd_mux_rs2_data_wire)
);

MUX_A pc_mux (
  .data_sel_in(reg_ex_pipeline_data_wire[155]),
  .a_data_src_in(fwd_mux_rs1_data_wire),
  .b_data_src_in(reg_ex_pipeline_data_wire[31:0]),
  .data_out(pc_mux_data_wire)
);

MUX_A imm_mux (
  .data_sel_in(reg_ex_pipeline_data_wire[156]),
  .a_data_src_in(fwd_mux_rs2_data_wire),
  .b_data_src_in(reg_ex_pipeline_data_wire[63:32]),
  .data_out(imm_mux_data_wire)
);


BRU bru0 (
  .pred_in(),
  .enable_in(),
  .uop_in(),
  .pc_in(),
  .rs1_in(),
  .rs2_in(),
  .imm_in(),
  .flush_out(),
  .taken_out(),
  .enable_out(),
  .mux_out(),
  .target_out()
);


ALU alu0 (
  .a_data_in(pc_mux_data_wire),
  .b_data_in(imm_mux_data_wire),
  .uop_in(reg_ex_pipeline_data_wire[148:145]),
  .result_out(alu_result_wire)
);


LSU lsu0 (
  .lsu_enable_in(),
  .lsu_uop_in(),
  .lsu_a_data_in(),
  .lsu_b_data_in(),
  .lsu_c_data_in(),
  .lsu_mem_data_in(),
  .lsu_mem_op_out(),
  .lsu_result_out(),
  .lsu_mem_data_out(),
  .lsu_mem_addr_out()
);

ENCODE_B ex_encoder0 (
  .data_in(),
  .data_out()
);


MUX_B ex_out_mux0 (
  .data_sel_in(),
  .a_data_src_in(),
  .b_data_src_in(),
  .c_data_src_in(),
  .d_data_src_in(),
  .data_out()
);


REG #() ex_wb_pipeline_reg (
  .reg_clock_in(clock_in),
  .reg_reset_in(reset_in),
  .reg_clear_in(pipeline_ex_wb_clear_wire),
  .reg_set_in(pipeline_ex_wb_set_wire),
  .reg_data_in(),
  .reg_data_out()
);






PIPELINE_CONTROL pipeline_control (


  .pipeline_clock_in(clock_in),
  .pipeline_reset_in(reset_in),

  .pipeline_correction_flag_in(),
  .pipeline_prediction_flag_in(),


  .pipeline_ins_mem_valid_out(pipeline_ins_mem_valid_wire),
  .pipeline_ins_mem_ready_in(ins_mem_ready_in),


  .pipeline_pc_if_set_out(pipeline_pc_if_set_wire),
  .pipeline_if_dec_set_out(pipeline_if_dec_set_wire),
  .pipeline_dec_reg_set_out(pipeline_dec_reg_set_wire),
  .pipeline_reg_ex_set_out(pipeline_reg_ex_set_wire),
  .pipeline_ex_wb_set_out(pipeline_ex_wb_set_wire),


  .pipeline_pc_if_clear_out(pipeline_pc_if_clear_wire),
  .pipeline_if_dec_clear_out(pipeline_if_dec_clear_wire),
  .pipeline_dec_reg_clear_out(pipeline_dec_reg_clear_wire),
  .pipeline_reg_ex_clear_out(pipeline_reg_ex_clear_wire),
  .pipeline_ex_wb_clear_out(pipeline_ex_wb_clear_wire)
);



endmodule
module Core101 (

  input clock_in,
  input reset_in,


  output ins_mem_valid_out,
  output [31:0] ins_mem_addr_out,
  input ins_mem_ready_in,
  input [31:0] ins_mem_data_in,


  output data_mem_valid_out,
  output data_mem_write_out,
  output [31:0] data_mem_addr_out,
  output [31:0] data_mem_data_out,
  input data_mem_ready_in,
  input [31:0] data_mem_data_in
);




parameter XLEN = 32;


parameter PC_IF_WIDTH = 33;
parameter IF_DEC_WIDTH = 65;
parameter DEC_REG_WIDTH = 95;
parameter REG_EX_WIDTH = 161;
parameter EX_WB_WIDTH = 10;





wire pc_calc_pred_wire;
wire [31:0] pc_calc_addr_wire;


wire [PC_IF_WIDTH-1:0] pc_if_pipeline_data_wire;


wire predictor_pred_enable_wire;
wire [31:00] predictor_pred_addr_wire;


wire [IF_DEC_WIDTH-1:0] if_dec_pipeline_data_wire;


wire [1:0] fwd_mux_sel_wire;


wire [XLEN-1:0] imm_gen_data_wire;


wire decode_imm_mux_sel_wire;
wire decode_pc_mux_sel_wire;
wire decode_rd_write_en_wire;
wire decode_rd_mux_sel_wire;
wire decode_jump_mux_sel_wire;
wire decode_invalid_ins_wire;
wire [3:0] decode_exec_unit_sel_wire;
wire [3:0] decode_exec_uop_sel_wire;


wire [DEC_REG_WIDTH-1:0] dec_reg_pipeline_data_wire;


wire [XLEN-1:0] gpr_rs1_data_wire;
wire [XLEN-1:0] gpr_rs2_data_wire;


wire issue_int_en_wire;
wire issue_vec_en_wire;
wire issue_lsu_en_wire;
wire issue_bru_en_wire;
wire [3:0] issue_int_uop_wire;
wire [3:0] issue_vec_uop_wire;
wire [3:0] issue_lsu_uop_wire;
wire [3:0] issue_bru_uop_wire;


wire [REG_EX_WIDTH-1:0] reg_ex_pipeline_data_wire;


wire [XLEN-1:0] fwd_mux_rs1_data_wire;
wire [XLEN-1:0] fwd_mux_rs2_data_wire;


wire [XLEN-1:0] pc_mux_data_wire;
wire [XLEN-1:0] imm_mux_data_wire;


wire bru_pipeline_flush_wire;
wire bru_predictor_taken_wire;
wire bru_predictor_en_wire;
wire bru_pc_enable_wire;
wire [XLEN-1:0] bru_pc_address_wire;


wire [XLEN-1:0] alu_result_wire;


wire [3:0] lsu_mem_op_wire;
wire [XLEN-1:0] lsu_data_wire;
wire [XLEN-1:0] lsu_addr_wire;
wire [XLEN-1:0] lsu_result_wire;


wire [EX_WB_WIDTH-1:0] ex_wb_pipeline_data_wire;


wire pipeline_ins_mem_valid_wire;

wire pipeline_pc_if_set_wire;
wire pipeline_if_dec_set_wire;
wire pipeline_dec_reg_set_wire;
wire pipeline_reg_ex_set_wire;
wire pipeline_ex_wb_set_wire;

wire pipeline_pc_if_clear_wire;
wire pipeline_if_dec_clear_wire;
wire pipeline_dec_reg_clear_wire;
wire pipeline_reg_ex_clear_wire;
wire pipeline_ex_wb_clear_wire;



PC_CALC #(.XLEN(XLEN)) pc_calc (

  .pc_calc_correction_en_in(bru_pc_enable_wire),
  .pc_calc_prediction_en_in(predictor_pred_enable_wire),

  .pc_calc_current_in(pc_if_pipeline_data_wire[XLEN-1:0]),

  .pc_calc_correction_in(bru_pc_address_wire),
  .pc_calc_prediction_in(predictor_pred_addr_wire),

  .pc_calc_addr_out(pc_calc_addr_wire),
  .pc_calc_pred_out(pc_calc_pred_wire)
);



REG #(.XLEN(PC_IF_WIDTH)) pc_if_pipeline_reg (
  .reg_clock_in(clock_in),
  .reg_reset_in(reset_in),
  .reg_clear_in(pipeline_pc_if_clear_wire),
  .reg_set_in(pipeline_pc_if_set_wire),
  .reg_data_in({
      pc_calc_pred_wire,
      pc_calc_addr_wire
    }),
  .reg_data_out(pc_if_pipeline_data_wire)
);


assign ins_mem_addr_out = pc_if_pipeline_data_wire[XLEN-1:0];
assign ins_mem_valid_out = pipeline_ins_mem_valid_wire;


PREDICTOR predictor0 (
  .predictor_clock_in(clock_in),
  .predictor_reset_in(reset_in),

  .predictor_pred_addr_in(pc_if_pipeline_data_wire[XLEN-1:0]),
  .predictor_pred_enable_out(predictor_pred_enable_wire),
  .predictor_pred_addr_out(predictor_pred_addr_wire),

  .predictor_feedback_result_in(),
  .predictor_feedback_write_enable_in(),
  .predictor_feedback_addr_in(),
  .predictor_feedback_return_in()
);


REG #(.XLEN(IF_DEC_WIDTH)) if_dec_pipeline_reg (
  .reg_clock_in(clock_in),
  .reg_reset_in(reset_in),
  .reg_clear_in(pipeline_if_dec_clear_wire),
  .reg_set_in(pipeline_if_dec_set_wire),
  .reg_data_in({
      pc_if_pipeline_data_wire[XLEN],
      ins_mem_data_in,
      pc_if_pipeline_data_wire[XLEN-1:0]
    }),
  .reg_data_out(if_dec_pipeline_data_wire)
);



FORWARDING_UNIT forwarding_unit0 (
  .fwd_if_ra_addr_in(if_dec_pipeline_data_wire[51:47]),
  .fwd_if_rb_addr_in(if_dec_pipeline_data_wire[56:52]),
  .fwd_id_rd_addr_in(if_dec_pipeline_data_wire[43:39]),
  .fwd_mux_sel_out(fwd_mux_sel_wire)
);


IMM_GEN imm_gen (
  .imm_gen_opcode_in(if_dec_pipeline_data_wire[38:32]),
  .imm_gen_ins_in(if_dec_pipeline_data_wire[63:39]),
  .imm_gen_data_out(imm_gen_data_wire)
);


DECODE_UNIT decode0 (
  .dec_opcode_in(if_dec_pipeline_data_wire[38:32]),
  .dec_funct3_in(if_dec_pipeline_data_wire[46:44]),
  .dec_funct7_in(if_dec_pipeline_data_wire[63:57]),

  .dec_imm_mux_sel_out(decode_imm_mux_sel_wire),
  .dec_pc_mux_sel_out(decode_pc_mux_sel_wire),
  .dec_rd_write_enable_out(decode_rd_write_en_wire),
  .dec_rd_data_sel_out(decode_rd_mux_sel_wire),
  .dec_jump_sel_out(decode_jump_mux_sel_wire),


  .dec_invalid_ins_exception(decode_invalid_ins_wire),


  .dec_exec_unit_sel_out(decode_exec_unit_sel_wire),
  .dec_exec_unit_uop_out(decode_exec_uop_sel_wire)
);


REG #(.XLEN(DEC_REG_WIDTH)) dec_reg_pipeline_reg (
  .reg_clock_in(clock_in),
  .reg_reset_in(reset_in),
  .reg_clear_in(pipeline_dec_reg_clear_wire),
  .reg_set_in(pipeline_dec_reg_set_wire),
  .reg_data_in({
      if_dec_pipeline_data_wire[64],
      decode_jump_mux_sel_wire,
      decode_rd_mux_sel_wire,
      decode_rd_write_en_wire,
      decode_imm_mux_sel_wire,
      decode_pc_mux_sel_wire,
      fwd_mux_sel_wire,
      decode_exec_unit_sel_wire,
      decode_exec_uop_sel_wire,
      if_dec_pipeline_data_wire[56:52],
      if_dec_pipeline_data_wire[51:47],
      if_dec_pipeline_data_wire[43:39],
      imm_gen_data_wire,
      if_dec_pipeline_data_wire[31:0]
    }),
  .reg_data_out(dec_reg_pipeline_data_wire)
);


GPR gpr0 (
  .clock_in(clock_in),
  .reset_in(reset_in),


  .write_enable_in(),
  .rd_addr_in(),
  .rd_data_in(),


  .rs1_addr_in(dec_reg_pipeline_data_wire[73:69]),
  .rs2_addr_in(dec_reg_pipeline_data_wire[78:74]),
  .rs1_data_out(gpr_rs1_data_wire),
  .rs2_data_out(gpr_rs2_data_wire)
);


ISSUE_UNIT issue0 (

  .exec_unit_sel_in(dec_reg_pipeline_data_wire[86:83]),
  .exec_uop_in(dec_reg_pipeline_data_wire[82:79]),


  .int_enable_out(issue_int_en_wire),
  .vec_enable_out(issue_vec_en_wire),
  .lsu_enable_out(issue_lsu_en_wire),
  .bru_enable_out(issue_bru_en_wire),


  .int_exec_uop_out(issue_int_uop_wire),
  .vec_exec_uop_out(issue_vec_uop_wire),
  .lsu_exec_uop_out(issue_lsu_uop_wire),
  .bru_exec_uop_out(issue_bru_uop_wire)
);


REG #(.XLEN(REG_EX_WIDTH)) reg_ex_pipeline_reg (
  .reg_clock_in(clock_in),
  .reg_reset_in(reset_in),
  .reg_clear_in(pipeline_reg_ex_clear_wire),
  .reg_set_in(pipeline_reg_ex_set_wire),
  .reg_data_in({
      dec_reg_pipeline_data_wire[94],
      dec_reg_pipeline_data_wire[93],
      dec_reg_pipeline_data_wire[92],
      dec_reg_pipeline_data_wire[91],
      dec_reg_pipeline_data_wire[90],
      dec_reg_pipeline_data_wire[89],
      issue_int_en_wire,
      issue_lsu_en_wire,
      issue_vec_en_wire,
      issue_bru_en_wire,
      dec_reg_pipeline_data_wire[88:87],
      issue_int_uop_wire,
      issue_lsu_uop_wire,
      issue_vec_uop_wire,
      issue_bru_uop_wire,
      dec_reg_pipeline_data_wire[68:64],
      gpr_rs2_data_wire,
      gpr_rs1_data_wire,
      dec_reg_pipeline_data_wire[63:32],
      dec_reg_pipeline_data_wire[31:0]
    }),
  .reg_data_out(reg_ex_pipeline_data_wire)
);

MUX_A rs1_fwd (
  .data_sel_in(reg_ex_pipeline_data_wire[149]),
  .a_data_src_in(reg_ex_pipeline_data_wire[95:64]),
  .b_data_src_in(),
  .data_out(fwd_mux_rs1_data_wire)
);

MUX_A rs2_fwd (
  .data_sel_in(reg_ex_pipeline_data_wire[150]),
  .a_data_src_in(reg_ex_pipeline_data_wire[127:96]),
  .b_data_src_in(),
  .data_out(fwd_mux_rs2_data_wire)
);

MUX_A pc_mux (
  .data_sel_in(reg_ex_pipeline_data_wire[155]),
  .a_data_src_in(fwd_mux_rs1_data_wire),
  .b_data_src_in(reg_ex_pipeline_data_wire[31:0]),
  .data_out(pc_mux_data_wire)
);

MUX_A imm_mux (
  .data_sel_in(reg_ex_pipeline_data_wire[156]),
  .a_data_src_in(fwd_mux_rs2_data_wire),
  .b_data_src_in(reg_ex_pipeline_data_wire[63:32]),
  .data_out(imm_mux_data_wire)
);


BRU bru0 (
  .pred_in(),
  .enable_in(),
  .uop_in(),
  .pc_in(),
  .rs1_in(),
  .rs2_in(),
  .imm_in(),
  .flush_out(),
  .taken_out(),
  .enable_out(),
  .mux_out(),
  .target_out()
);


ALU alu0 (
  .a_data_in(pc_mux_data_wire),
  .b_data_in(imm_mux_data_wire),
  .uop_in(reg_ex_pipeline_data_wire[148:145]),
  .result_out(alu_result_wire)
);


LSU lsu0 (
  .lsu_enable_in(),
  .lsu_uop_in(),
  .lsu_a_data_in(),
  .lsu_b_data_in(),
  .lsu_c_data_in(),
  .lsu_mem_data_in(),
  .lsu_mem_op_out(),
  .lsu_result_out(),
  .lsu_mem_data_out(),
  .lsu_mem_addr_out()
);

ENCODE_B ex_encoder0 (
  .data_in(),
  .data_out()
);


MUX_B ex_out_mux0 (
  .data_sel_in(),
  .a_data_src_in(),
  .b_data_src_in(),
  .c_data_src_in(),
  .d_data_src_in(),
  .data_out()
);


REG #() ex_wb_pipeline_reg (
  .reg_clock_in(clock_in),
  .reg_reset_in(reset_in),
  .reg_clear_in(pipeline_ex_wb_clear_wire),
  .reg_set_in(pipeline_ex_wb_set_wire),
  .reg_data_in(),
  .reg_data_out()
);






PIPELINE_CONTROL pipeline_control (


  .pipeline_clock_in(clock_in),
  .pipeline_reset_in(reset_in),

  .pipeline_correction_flag_in(),
  .pipeline_prediction_flag_in(),


  .pipeline_ins_mem_valid_out(pipeline_ins_mem_valid_wire),
  .pipeline_ins_mem_ready_in(ins_mem_ready_in),


  .pipeline_pc_if_set_out(pipeline_pc_if_set_wire),
  .pipeline_if_dec_set_out(pipeline_if_dec_set_wire),
  .pipeline_dec_reg_set_out(pipeline_dec_reg_set_wire),
  .pipeline_reg_ex_set_out(pipeline_reg_ex_set_wire),
  .pipeline_ex_wb_set_out(pipeline_ex_wb_set_wire),


  .pipeline_pc_if_clear_out(pipeline_pc_if_clear_wire),
  .pipeline_if_dec_clear_out(pipeline_if_dec_clear_wire),
  .pipeline_dec_reg_clear_out(pipeline_dec_reg_clear_wire),
  .pipeline_reg_ex_clear_out(pipeline_reg_ex_clear_wire),
  .pipeline_ex_wb_clear_out(pipeline_ex_wb_clear_wire)
);



endmodule