data/full_repos/permissive/143278/ivltests/vhdl_xnor23_bit.v
 line:1: before: "["
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_xnor23_bit.v:7: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_xnor23_bit.v:25: Unsupported: Ignoring delay on this delayed statement.\n       #1 A = {$random} % MAX;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_xnor23_bit.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #20000;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_xnor23_bit.v:25: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                               : ... In instance test.stim\n       #1 A = {$random} % MAX;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_xnor23_bit.v:26: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                               : ... In instance test.stim\n          B = {$random} % MAX;\n            ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_xnor23_bit.v:38: Cannot find file containing module: \'xnor23\'\n  xnor23       duv            (.a_i(a), .b_i(b), .c_o(r) );\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/xnor23\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/xnor23.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/xnor23.sv\n             xnor23\n             xnor23.v\n             xnor23.sv\n             obj_dir/xnor23\n             obj_dir/xnor23.v\n             obj_dir/xnor23.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stimulus (output reg unsigned [22:0] A, B);
  parameter MAX = 1 << 23;
  parameter S = 10000;
  int unsigned i;


  initial begin
    A = 0; B= 0;
    for (i=0; i<S; i=i+1) begin
       #1 A = {$random} % MAX;
          B = {$random} % MAX;
    end
  end

endmodule
module stimulus (output reg unsigned [22:0] A, B);

  parameter MAX = 1 << 23;
  parameter S = 10000;
  int unsigned i;


  initial begin
    A = 0; B= 0;
    for (i=0; i<S; i=i+1) begin
       #1 A = {$random} % MAX;
          B = {$random} % MAX;
    end
  end

endmodule