data/full_repos/permissive/143278/ivltests/vhdl_test4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_test4.v:7: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (o1 !== 8\'h00) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_test4.v:4: Cannot find file containing module: \'dummy\'\n   dummy foo(.o1(o1), .o2(o2), .o3(o3));\n   ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/dummy\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/dummy.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/dummy.sv\n             dummy\n             dummy.v\n             dummy.sv\n             obj_dir/dummy\n             obj_dir/dummy.v\n             obj_dir/dummy.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

   wire [7:0] o1, o2, o3;
   dummy foo(.o1(o1), .o2(o2), .o3(o3));

   initial begin
      #1 if (o1 !== 8'h00) begin
	 $display("FAILED -- o1 = %b", o1);
	 $finish;
      end

      if (o2 !== 8'h08) begin
	 $display("FAILED -- o2 = %b", o2);
	 $finish;
      end

      if (o3 !== 8'h80) begin
	 $display("FAILED == o3 = %b", o3);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module test;


   wire [7:0] o1, o2, o3;
   dummy foo(.o1(o1), .o2(o2), .o3(o3));

   initial begin
      #1 if (o1 !== 8'h00) begin
	 $display("FAILED -- o1 = %b", o1);
	 $finish;
      end

      if (o2 !== 8'h08) begin
	 $display("FAILED -- o2 = %b", o2);
	 $finish;
      end

      if (o3 !== 8'h80) begin
	 $display("FAILED == o3 = %b", o3);
	 $finish;
      end

      $display("PASSED");
   end

endmodule