data/full_repos/permissive/143278/ivltests/wildsense2.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wildsense2.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("data=%b", data);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wildsense2.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("data=%b", data);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wildsense2.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("data=%b", data);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wildsense2.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("data=%b", data);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wildsense2.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("data=%b", data);\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/wildsense2.v:19: Operator NEQCASE expects 3 bits on the LHS, but LHS\'s VARREF \'data\' generates 2 bits.\n                                                                          : ... In instance main\n      if (data !== ADDR) begin\n               ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/wildsense2.v:26: Operator NEQCASE expects 3 bits on the LHS, but LHS\'s VARREF \'data\' generates 2 bits.\n                                                                          : ... In instance main\n      if (data !== ADDR) begin\n               ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/wildsense2.v:33: Operator NEQCASE expects 3 bits on the LHS, but LHS\'s VARREF \'data\' generates 2 bits.\n                                                                          : ... In instance main\n      if (data !== ADDR) begin\n               ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/wildsense2.v:40: Operator NEQCASE expects 3 bits on the LHS, but LHS\'s VARREF \'data\' generates 2 bits.\n                                                                          : ... In instance main\n      if (data !== ADDR) begin\n               ^~~\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [2:0] ADDR;
   wire [1:0] data0 = 0, data1 = 1, data2 = 2, data3 = 3;

   reg [1:0]  data;
   always @*
     case (ADDR[2:0])
       3'b000: data = data0;
       3'b001: data = data1;
       3'b010: data = data2;
       3'b011: data = data3;
       default: data = 0;
     endcase

   initial begin
      ADDR = 0;
      #1 $display("data=%b", data);
      if (data !== ADDR) begin
	 $display("FAILED");
	 $finish;
      end

      ADDR = 1;
      #1 $display("data=%b", data);
      if (data !== ADDR) begin
	 $display("FAILED");
	 $finish;
      end

      ADDR = 2;
      #1 $display("data=%b", data);
      if (data !== ADDR) begin
	 $display("FAILED");
	 $finish;
      end

      ADDR = 3;
      #1 $display("data=%b", data);
      if (data !== ADDR) begin
	 $display("FAILED");
	 $finish;
      end

      ADDR = 4;
      #1 $display("data=%b", data);
      if (data !== 0)begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg [2:0] ADDR;
   wire [1:0] data0 = 0, data1 = 1, data2 = 2, data3 = 3;

   reg [1:0]  data;
   always @*
     case (ADDR[2:0])
       3'b000: data = data0;
       3'b001: data = data1;
       3'b010: data = data2;
       3'b011: data = data3;
       default: data = 0;
     endcase

   initial begin
      ADDR = 0;
      #1 $display("data=%b", data);
      if (data !== ADDR) begin
	 $display("FAILED");
	 $finish;
      end

      ADDR = 1;
      #1 $display("data=%b", data);
      if (data !== ADDR) begin
	 $display("FAILED");
	 $finish;
      end

      ADDR = 2;
      #1 $display("data=%b", data);
      if (data !== ADDR) begin
	 $display("FAILED");
	 $finish;
      end

      ADDR = 3;
      #1 $display("data=%b", data);
      if (data !== ADDR) begin
	 $display("FAILED");
	 $finish;
      end

      ADDR = 4;
      #1 $display("data=%b", data);
      if (data !== 0)begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
   end

endmodule