data/full_repos/permissive/119387855/mips_control_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_control_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10 op_code = 6\'b100011; \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_control_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10 op_code = 6\'b000000; funct = 6\'b100010; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_control_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n #10 op_code = 6\'b000000; funct = 6\'b000111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_control_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10 op_code = 6\'b000000; funct = 6\'b100011;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_control_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n #10 op_code = 6\'b000010;\n ^\n%Error: data/full_repos/permissive/119387855/mips_control_testbench.v:29: Unsupported or unknown PLI call: $monitor\n $monitor("opCode: %b, funct: %b, reg_dst: %b, alu_src: %b, mem_to_reg: %b, reg_write: %b, mem_read: %b, mem_write: %b, branch: %b, alu_op: %b, jump: %b, byte_number: %b",op_code,funct,reg_dst,alu_src,mem_to_reg,reg_write,mem_read,mem_write,branch,alu_op,jump,byte_number);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_control_testbench();

wire [1:0] reg_dst ;
wire alu_src;
wire [1:0] mem_to_reg ;
wire reg_write;
wire mem_read;
wire mem_write;
wire [1:0] branch ;
wire [3:0] alu_op ;
wire [1:0] jump ;
wire [1:0] byte_number ;

reg [5:0] op_code;
reg [5:0] funct;

mips_control test(reg_dst, alu_src, mem_to_reg, reg_write, mem_read, mem_write, branch, alu_op, jump, byte_number, op_code, funct);

initial begin
	#10 op_code = 6'b100011; 
	#10 op_code = 6'b000000; funct = 6'b100010; 
	#10 op_code = 6'b000000; funct = 6'b000111;
	#10 op_code = 6'b000000; funct = 6'b100011; 	
	#10 op_code = 6'b000010;
		
end

initial begin
	$monitor("opCode: %b, funct: %b, reg_dst: %b, alu_src: %b, mem_to_reg: %b, reg_write: %b, mem_read: %b, mem_write: %b, branch: %b, alu_op: %b, jump: %b, byte_number: %b",op_code,funct,reg_dst,alu_src,mem_to_reg,reg_write,mem_read,mem_write,branch,alu_op,jump,byte_number);
end

endmodule
module mips_control_testbench();


wire [1:0] reg_dst ;
wire alu_src;
wire [1:0] mem_to_reg ;
wire reg_write;
wire mem_read;
wire mem_write;
wire [1:0] branch ;
wire [3:0] alu_op ;
wire [1:0] jump ;
wire [1:0] byte_number ;

reg [5:0] op_code;
reg [5:0] funct;

mips_control test(reg_dst, alu_src, mem_to_reg, reg_write, mem_read, mem_write, branch, alu_op, jump, byte_number, op_code, funct);

initial begin
	#10 op_code = 6'b100011; 
	#10 op_code = 6'b000000; funct = 6'b100010; 
	#10 op_code = 6'b000000; funct = 6'b000111;
	#10 op_code = 6'b000000; funct = 6'b100011; 	
	#10 op_code = 6'b000010;
		
end

initial begin
	$monitor("opCode: %b, funct: %b, reg_dst: %b, alu_src: %b, mem_to_reg: %b, reg_write: %b, mem_read: %b, mem_write: %b, branch: %b, alu_op: %b, jump: %b, byte_number: %b",op_code,funct,reg_dst,alu_src,mem_to_reg,reg_write,mem_read,mem_write,branch,alu_op,jump,byte_number);
end

endmodule