data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Division/Div_Radix4.v
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module Div_Radix4

		#(parameter	WL = 24,
						WF = 23,
						RADIX = 4,
						N = 12,
						LUT_size = 8,
						LUT_bits = 7,
						LUT_addWidth = RADIX,
						addpointer = cLog2(N)
		 )

		(
			input CLK,
			input nRST,
			input CE,
			input [WL-1:0] din_x,

			input [WL-1:0] din_d,
			output reg[WL-1:0] dout
		);
		

		reg  [LUT_bits-1 : 0]  LUT_m2  [LUT_size-1 : 0];
		reg  [LUT_bits-1 : 0]  LUT_m1  [LUT_size-1 : 0];
		reg  [LUT_bits-1 : 0]  LUT_mm1 [LUT_size-1 : 0];
		reg  [LUT_bits-1 : 0]  LUT_m0  [LUT_size-1 : 0];
		
		reg  [LUT_addWidth-1:0] reg_cmp, index;

		reg  											Sel;
		reg  [2:0]									fpSeven = 0;

		reg  [LUT_bits-1:0]						m2, m1, m0, mm1;
		reg  [WL+2-1:0]  							rwj_ini = 0;
		reg  [WL+2-1:0]  							rwj_shf;
		wire [WL+2-1:0]  							rwj;
		reg  signed  [2+4 :0]					yHatTimesr = 0;
		reg  signed  [2:0]						q;
		wire signed  [2:0]						q_abs;
		
		wire signed  [WL+2-1:0] 				qjd;
		reg  signed  [WL+2-1:0] 				wjp;
		wire  		 [WL-1:0]					tmp_result_1;

		reg  [WL-1:0]		  		  QM;
		reg  [WL-1:0]  	  		  QN;
		reg  [WL-1:0]		  		  QM_tmp;
		reg  [WL-1:0]  	  		  QN_tmp;
		reg  [1:0]					  QM_next;
		reg  [1:0]					  QN_next;
		



	reg [addpointer-1:0] pointer = 0;

	integer looper_2 = 0;
		always @ (posedge CLK) begin
			if(~nRST) begin
					Sel <= 1'b0;							
					pointer <= 0;
					dout <= 0;
					QN <= 0;
					QM <= 0;
			end
			else begin
				if (CE) begin

					if (pointer == N-1) begin					
						dout <= QN << 3;
						pointer <= 0;
						Sel <= 1'b0;				
						QN <= 0;
						QM <= 0;
					end else begin

						pointer <= pointer + 1;
						Sel <= 1'b1;


						if(q>=0) begin
							QN[WL-1:2] <= QN_tmp[WL-3:0];
						end else begin
							QN[WL-1:2] <= QM_tmp[WL-3:0]; 
						end
						
						if(q>0) begin
							QM[WL-1:2] <= QN_tmp[WL-3:0];
						end else begin
							QM[WL-1:2] <= QM_tmp[WL-3:0];
						end

						QN[1:0]		 <= QN_next;						
						QM[1:0]      <= QM_next;
						
					end
					rwj_shf <= wjp << 2;
				end
			end
		end	

	multiplexer #(.N(WL+2)) Sel_input_mux (.a(rwj_ini),.b(rwj_shf),.Sel(Sel),.out(rwj));			

	abs #(.WL(3)) abs_Fang (.in(q), .out(q_abs));

	sMult #(.WI1(3), .WF1(0), .WI2(WL-WF), .WF2(WF), .WIO(WL+2-WF), .WFO(WF)) multiplier 
						(.CLK(CLK), .RST(nRST), .in1(q), .in2(din_d), .out(qjd));




	always @ * begin
			if(~nRST) begin
					reg_cmp = 0;
					index = 0;
					fpSeven[RADIX-2:0] = 3'b111;
					rwj_ini = 0;
					wjp = 0;
					yHatTimesr = 0;
					q = 0;
					QN_tmp = 0;
					QM_tmp = 0;
			end else begin
				if (CE) begin
					reg_cmp   = din_d[WL-2 : WL-1-RADIX];   
					index = reg_cmp - fpSeven;
					m2 = LUT_m2[index-1];
					m1 = LUT_m1[index-1];
					m0 = LUT_m0[index-1];
					mm1 = LUT_mm1[index-1];

					rwj_ini[WL-1:0] = din_x;
					yHatTimesr = rwj[WL+2-1 : WL+2-(1+2+RADIX)];
					
					if (yHatTimesr[6]==1'b0) begin
						if (yHatTimesr >= m2)
							q = 3'b010;
						else if ((yHatTimesr<m2)&&(yHatTimesr>=m1))
							q = 3'b001;
						else if (yHatTimesr<m1)
							q = 3'b000;
					end else begin
						if ((-yHatTimesr)<=-m0)
							q = 3'b000;
						else if (((-yHatTimesr)>-m0)&&((-yHatTimesr)<=-mm1))
							q = 3'b111;
						else
							q = 3'b110;
					end
						
					if (q > 0) begin

						QM_next = q - 1;				

						QN_next = q;
					end else if (q==0) begin

						QN_next = 0;

						QM_next = RADIX-1;
					end else begin

						QM_next = RADIX-1-q_abs;

						QN_next = RADIX-q_abs;
					end
					
					QN_tmp = QN;
					QM_tmp = QM;
					
					wjp = rwj - qjd;
					
				end
			end
	end
	



		function integer cLog2;
			input [31:0] value;
			integer i;
			begin
			  i = value;
				for (cLog2=0; i>0; cLog2=cLog2+1)
					i = i >> 1;
			end		
		endfunction	

endmodule
module Div_Radix4

		#(parameter	WL = 24,
						WF = 23,
						RADIX = 4,
						N = 12,
						LUT_size = 8,
						LUT_bits = 7,
						LUT_addWidth = RADIX,
						addpointer = cLog2(N)
		 )

		(
			input CLK,
			input nRST,
			input CE,
			input [WL-1:0] din_x,

			input [WL-1:0] din_d,
			output reg[WL-1:0] dout
		);

		

		reg  [LUT_bits-1 : 0]  LUT_m2  [LUT_size-1 : 0];
		reg  [LUT_bits-1 : 0]  LUT_m1  [LUT_size-1 : 0];
		reg  [LUT_bits-1 : 0]  LUT_mm1 [LUT_size-1 : 0];
		reg  [LUT_bits-1 : 0]  LUT_m0  [LUT_size-1 : 0];
		
		reg  [LUT_addWidth-1:0] reg_cmp, index;

		reg  											Sel;
		reg  [2:0]									fpSeven = 0;

		reg  [LUT_bits-1:0]						m2, m1, m0, mm1;
		reg  [WL+2-1:0]  							rwj_ini = 0;
		reg  [WL+2-1:0]  							rwj_shf;
		wire [WL+2-1:0]  							rwj;
		reg  signed  [2+4 :0]					yHatTimesr = 0;
		reg  signed  [2:0]						q;
		wire signed  [2:0]						q_abs;
		
		wire signed  [WL+2-1:0] 				qjd;
		reg  signed  [WL+2-1:0] 				wjp;
		wire  		 [WL-1:0]					tmp_result_1;

		reg  [WL-1:0]		  		  QM;
		reg  [WL-1:0]  	  		  QN;
		reg  [WL-1:0]		  		  QM_tmp;
		reg  [WL-1:0]  	  		  QN_tmp;
		reg  [1:0]					  QM_next;
		reg  [1:0]					  QN_next;
		



	reg [addpointer-1:0] pointer = 0;

	integer looper_2 = 0;
		always @ (posedge CLK) begin
			if(~nRST) begin
					Sel <= 1'b0;							
					pointer <= 0;
					dout <= 0;
					QN <= 0;
					QM <= 0;
			end
			else begin
				if (CE) begin

					if (pointer == N-1) begin					
						dout <= QN << 3;
						pointer <= 0;
						Sel <= 1'b0;				
						QN <= 0;
						QM <= 0;
					end else begin

						pointer <= pointer + 1;
						Sel <= 1'b1;


						if(q>=0) begin
							QN[WL-1:2] <= QN_tmp[WL-3:0];
						end else begin
							QN[WL-1:2] <= QM_tmp[WL-3:0]; 
						end
						
						if(q>0) begin
							QM[WL-1:2] <= QN_tmp[WL-3:0];
						end else begin
							QM[WL-1:2] <= QM_tmp[WL-3:0];
						end

						QN[1:0]		 <= QN_next;						
						QM[1:0]      <= QM_next;
						
					end
					rwj_shf <= wjp << 2;
				end
			end
		end	

	multiplexer #(.N(WL+2)) Sel_input_mux (.a(rwj_ini),.b(rwj_shf),.Sel(Sel),.out(rwj));			

	abs #(.WL(3)) abs_Fang (.in(q), .out(q_abs));

	sMult #(.WI1(3), .WF1(0), .WI2(WL-WF), .WF2(WF), .WIO(WL+2-WF), .WFO(WF)) multiplier 
						(.CLK(CLK), .RST(nRST), .in1(q), .in2(din_d), .out(qjd));




	always @ * begin
			if(~nRST) begin
					reg_cmp = 0;
					index = 0;
					fpSeven[RADIX-2:0] = 3'b111;
					rwj_ini = 0;
					wjp = 0;
					yHatTimesr = 0;
					q = 0;
					QN_tmp = 0;
					QM_tmp = 0;
			end else begin
				if (CE) begin
					reg_cmp   = din_d[WL-2 : WL-1-RADIX];   
					index = reg_cmp - fpSeven;
					m2 = LUT_m2[index-1];
					m1 = LUT_m1[index-1];
					m0 = LUT_m0[index-1];
					mm1 = LUT_mm1[index-1];

					rwj_ini[WL-1:0] = din_x;
					yHatTimesr = rwj[WL+2-1 : WL+2-(1+2+RADIX)];
					
					if (yHatTimesr[6]==1'b0) begin
						if (yHatTimesr >= m2)
							q = 3'b010;
						else if ((yHatTimesr<m2)&&(yHatTimesr>=m1))
							q = 3'b001;
						else if (yHatTimesr<m1)
							q = 3'b000;
					end else begin
						if ((-yHatTimesr)<=-m0)
							q = 3'b000;
						else if (((-yHatTimesr)>-m0)&&((-yHatTimesr)<=-mm1))
							q = 3'b111;
						else
							q = 3'b110;
					end
						
					if (q > 0) begin

						QM_next = q - 1;				

						QN_next = q;
					end else if (q==0) begin

						QN_next = 0;

						QM_next = RADIX-1;
					end else begin

						QM_next = RADIX-1-q_abs;

						QN_next = RADIX-q_abs;
					end
					
					QN_tmp = QN;
					QM_tmp = QM;
					
					wjp = rwj - qjd;
					
				end
			end
	end
	



		function integer cLog2;
			input [31:0] value;
			integer i;
			begin
			  i = value;
				for (cLog2=0; i>0; cLog2=cLog2+1)
					i = i >> 1;
			end		
		endfunction	

endmodule