data/full_repos/permissive/169639758/ice40/regressions/issue0106/top.v
data/verilator_xmls/30088b98-123e-4674-8d16-e3d0d28276df.xml
module top(input clock,
	   output led);

   reg [23:0] 	 count = 0;

   always @ (posedge clock)
     begin
	count <= count + 1'b1;
     end

   assign led = count[23];

endmodule
module top(input clock,
	   output led);


   reg [23:0] 	 count = 0;

   always @ (posedge clock)
     begin
	count <= count + 1'b1;
     end

   assign led = count[23];

endmodule