data/full_repos/permissive/133819542/test/inst_shift_test.v
1: b'%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:2: Cannot find include file: ../test/assert.v\n`include "../test/assert.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133819542/test,data/full_repos/permissive/133819542/../test/assert.v\n             data/full_repos/permissive/133819542/test,data/full_repos/permissive/133819542/../test/assert.v.v\n             data/full_repos/permissive/133819542/test,data/full_repos/permissive/133819542/../test/assert.v.sv\n             ../test/assert.v\n             ../test/assert.v.v\n             ../test/assert.v.sv\n             obj_dir/../test/assert.v\n             obj_dir/../test/assert.v.v\n             obj_dir/../test/assert.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:10: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:12: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("../test/inst_shift_test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:13: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:14: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[2]);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:15: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[5]);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:16: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[7]);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[8]);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #20 rst = 0;\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:24: Define or directive not defined: \'`AR\'\n        #12 `AR(2, 32\'h04040000);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:24: syntax error, unexpected \',\'\n        #12 `AR(2, 32\'h04040000);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #12 `AR(2, 32\'h04040000);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:25: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h04040404);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:25: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h04040404);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(2, 32\'h04040404);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:26: Define or directive not defined: \'`AR\'\n        #2  `AR(7, 32\'h00000007);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:26: syntax error, unexpected \',\'\n        #2  `AR(7, 32\'h00000007);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(7, 32\'h00000007);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:27: Define or directive not defined: \'`AR\'\n        #2  `AR(5, 32\'h00000005);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:27: syntax error, unexpected \',\'\n        #2  `AR(5, 32\'h00000005);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(5, 32\'h00000005);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:28: Define or directive not defined: \'`AR\'\n        #2  `AR(8, 32\'h00000008);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:28: syntax error, unexpected \',\'\n        #2  `AR(8, 32\'h00000008);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(8, 32\'h00000008);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:29: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h04040404); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:29: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h04040404); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(2, 32\'h04040404); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:29: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h04040404); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                                  ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:29: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h04040404); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                                       ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:29: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h04040404); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                                                        ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:29: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h04040404); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                                                             ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:29: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h04040404); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                                                                              ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:29: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h04040404); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                                                                                   ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:30: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h04040400);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:30: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h04040400);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(2, 32\'h04040400);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:31: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h02020000);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:31: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h02020000);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(2, 32\'h02020000);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:32: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h00020200);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:32: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h00020200);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(2, 32\'h00020200);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:33: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h00001010);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:33: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h00001010);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(2, 32\'h00001010);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:34: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h00001010);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:34: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h00001010);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(2, 32\'h00001010);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:35: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h00001010); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:35: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h00001010); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(2, 32\'h00001010); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:35: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h00001010); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                                  ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:35: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h00001010); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                                       ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:35: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h00001010); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                                                        ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:35: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h00001010); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                                                             ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:35: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h00001010); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                                                                              ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:35: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h00001010); `AR(7, 32\'h00000007); `AR(5, 32\'h00000005); `AR(8, 32\'h00000008);\n                                                                                   ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:36: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h80800000);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:36: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h80800000);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(2, 32\'h80800000);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:37: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'h80800000);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:37: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'h80800000);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(2, 32\'h80800000);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:38: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'hffff8080);\n            ^~~\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:38: syntax error, unexpected \',\'\n        #2  `AR(2, 32\'hffff8080);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/133819542/test/inst_shift_test.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #2  `AR(2, 32\'hffff8080);\n        ^\n%Error: data/full_repos/permissive/133819542/test/inst_shift_test.v:39: Define or directive not defined: \'`AR\'\n        #2  `AR(2, 32\'hffffff80);\n            ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module inst_shift_test();
    reg     clk, rst;
    integer i  ;

    open_mips_min_sopc open_mips_min_sopc0 (clk,rst);

    always #1 clk = ~clk;
    initial begin
        $dumpfile("../test/inst_shift_test.vcd");
        $dumpvars;
        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[2]);
        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[5]);
        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[7]);
        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[8]);

        $readmemh("../data/inst_shift_test.txt", open_mips_min_sopc0.openmips0.inst_rom0.inst_mem, 0, 15);

        clk = 0;
        rst = 1;
        #20 rst = 0;
        #12 `AR(2, 32'h04040000);
        #2  `AR(2, 32'h04040404);
        #2  `AR(7, 32'h00000007);
        #2  `AR(5, 32'h00000005);
        #2  `AR(8, 32'h00000008);
        #2  `AR(2, 32'h04040404); `AR(7, 32'h00000007); `AR(5, 32'h00000005); `AR(8, 32'h00000008);
        #2  `AR(2, 32'h04040400);
        #2  `AR(2, 32'h02020000);
        #2  `AR(2, 32'h00020200);
        #2  `AR(2, 32'h00001010);
        #2  `AR(2, 32'h00001010);
        #2  `AR(2, 32'h00001010); `AR(7, 32'h00000007); `AR(5, 32'h00000005); `AR(8, 32'h00000008);
        #2  `AR(2, 32'h80800000);
        #2  `AR(2, 32'h80800000);
        #2  `AR(2, 32'hffff8080);
        #2  `AR(2, 32'hffffff80);
        `PASS(shift instruction test);
    end

endmodule
module inst_shift_test();

    reg     clk, rst;
    integer i  ;

    open_mips_min_sopc open_mips_min_sopc0 (clk,rst);

    always #1 clk = ~clk;
    initial begin
        $dumpfile("../test/inst_shift_test.vcd");
        $dumpvars;
        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[2]);
        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[5]);
        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[7]);
        $dumpvars(0, open_mips_min_sopc0.openmips0.regfile1.regs[8]);

        $readmemh("../data/inst_shift_test.txt", open_mips_min_sopc0.openmips0.inst_rom0.inst_mem, 0, 15);

        clk = 0;
        rst = 1;
        #20 rst = 0;
        #12 `AR(2, 32'h04040000);
        #2  `AR(2, 32'h04040404);
        #2  `AR(7, 32'h00000007);
        #2  `AR(5, 32'h00000005);
        #2  `AR(8, 32'h00000008);
        #2  `AR(2, 32'h04040404); `AR(7, 32'h00000007); `AR(5, 32'h00000005); `AR(8, 32'h00000008);
        #2  `AR(2, 32'h04040400);
        #2  `AR(2, 32'h02020000);
        #2  `AR(2, 32'h00020200);
        #2  `AR(2, 32'h00001010);
        #2  `AR(2, 32'h00001010);
        #2  `AR(2, 32'h00001010); `AR(7, 32'h00000007); `AR(5, 32'h00000005); `AR(8, 32'h00000008);
        #2  `AR(2, 32'h80800000);
        #2  `AR(2, 32'h80800000);
        #2  `AR(2, 32'hffff8080);
        #2  `AR(2, 32'hffffff80);
        `PASS(shift instruction test);
    end

endmodule