data/full_repos/permissive/17656033/filter/filter.srcs/sources_1/new/filter.v
1: b'%Error: data/full_repos/permissive/17656033/filter/filter.srcs/sources_1/new/filter.v:63: Cannot find file containing module: \'xbip_dsp48_macro_preadder_l3\'\n       xbip_dsp48_macro_preadder_l3 pre_adder ( \n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17656033/filter/filter.srcs/sources_1/new,data/full_repos/permissive/17656033/xbip_dsp48_macro_preadder_l3\n             data/full_repos/permissive/17656033/filter/filter.srcs/sources_1/new,data/full_repos/permissive/17656033/xbip_dsp48_macro_preadder_l3.v\n             data/full_repos/permissive/17656033/filter/filter.srcs/sources_1/new,data/full_repos/permissive/17656033/xbip_dsp48_macro_preadder_l3.sv\n             xbip_dsp48_macro_preadder_l3\n             xbip_dsp48_macro_preadder_l3.v\n             xbip_dsp48_macro_preadder_l3.sv\n             obj_dir/xbip_dsp48_macro_preadder_l3\n             obj_dir/xbip_dsp48_macro_preadder_l3.v\n             obj_dir/xbip_dsp48_macro_preadder_l3.sv\n%Error: data/full_repos/permissive/17656033/filter/filter.srcs/sources_1/new/filter.v:74: Cannot find file containing module: \'xbip_dsp48_macro_macc_l3\'\n   xbip_dsp48_macro_macc_l3 macc_ABC ( \n   ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/17656033/filter/filter.srcs/sources_1/new/filter.v:123: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n                                                                                                 : ... In instance filter\n   layer_valid <= {layer_valid, din_valid};\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module filter
	(
		input	clk,
		input	resetn,
		input	[71:0]	din,		
		input 	[53:0] 	kernel,		
		input	din_valid,
		output	[15:0]	dout,				
		output	dout_valid
    );
	parameter latency = 9;
    wire [8:0] din_array [8:0];
    wire [5:0] kernel_array [8:0];
	wire plus_or_minus [2:0];
    genvar i;
    generate
        for(i = 0; i < 9; i = i + 1) begin
            assign din_array[i] = {1'b0, din[i*8 +: 8]};
            assign kernel_array[i] = kernel[i*6 +: 6];
        end     
		for(i = 0; i < 3; i = i + 1) begin
			assign plus_or_minus[i] = (kernel_array[i*3] == kernel_array[i*3+2]) ? 1'b0 : 1'b1;
		end
    endgenerate  
	
	
	reg  [latency-1:0] layer_valid;		
	wire [14:0] layer_1_2 [2:0];
	reg  [8:0]  layer_1_2_buf [3*3-1:0];
	wire [15:0] layer_2_3 [2:0];
	reg  [15:0] layer_3_4 [1:0];
	reg  [15:0] layer_4_5;
	reg  [15:0] layer_5_end;	
	
	assign dout = layer_5_end;
	assign dout_valid = layer_valid[latency-1]; 
  
	generate 	
		for(i = 0; i < 3; i = i + 1) 
		begin:layer1
		     xbip_dsp48_macro_preadder_l3 pre_adder (
                .CLK(clk),
                .A(din_array[i*3]),
                .B(kernel_array[i*3]),
                .D(plus_or_minus[i] == 1'b0 ? din_array[i*3+2] : -din_array[i*3+2]),
                .P(layer_1_2[i])
            );			
		end

		for(i = 0; i < 3; i = i + 1) 
		begin:layer2
			xbip_dsp48_macro_macc_l3 macc_ABC (
				.CLK(clk),
				.A(layer_1_2_buf[i*3+2]),
				.B(kernel_array[i*3+1]),
				.C(layer_1_2[i]),
				.P(layer_2_3[i])
			);
		end		
		
    endgenerate
    
    integer j;    
    always@(posedge clk) begin    
        
    	if( resetn == 1'b0 ) begin    
			layer_valid <= 0;
    		
			
			for(j = 0; j < 9; j = j + 1)begin
				layer_1_2_buf[j] <= 9'b0;							
			end		
			
			for(j = 0; j < 2; j = j + 1)begin						
				layer_3_4[j] <= 16'b0;			
			end		
			layer_4_5 <= 16'b0;			
			layer_5_end <= 16'b0;
			
    	end
    	else begin

			for(j = 0; j < 3; j = j + 1) begin
				layer_1_2_buf[j*3] <= din_array[j*3+1];		
				layer_1_2_buf[j*3+1] <= layer_1_2_buf[j*3];
				layer_1_2_buf[j*3+2] <= layer_1_2_buf[j*3+1];
			end		
		


			layer_3_4[0] <= layer_2_3[0] + layer_2_3[1];
			layer_3_4[1] <= layer_2_3[2];			
			

			layer_4_5 <= layer_3_4[0] + layer_3_4[1];
			

			layer_5_end <= layer_4_5;
			

			layer_valid <= {layer_valid, din_valid};

        end
    end	
	
endmodule
module filter
	(
		input	clk,
		input	resetn,
		input	[71:0]	din,		
		input 	[53:0] 	kernel,		
		input	din_valid,
		output	[15:0]	dout,				
		output	dout_valid
    );

	parameter latency = 9;
    wire [8:0] din_array [8:0];
    wire [5:0] kernel_array [8:0];
	wire plus_or_minus [2:0];
    genvar i;
    generate
        for(i = 0; i < 9; i = i + 1) begin
            assign din_array[i] = {1'b0, din[i*8 +: 8]};
            assign kernel_array[i] = kernel[i*6 +: 6];
        end     
		for(i = 0; i < 3; i = i + 1) begin
			assign plus_or_minus[i] = (kernel_array[i*3] == kernel_array[i*3+2]) ? 1'b0 : 1'b1;
		end
    endgenerate  
	
	
	reg  [latency-1:0] layer_valid;		
	wire [14:0] layer_1_2 [2:0];
	reg  [8:0]  layer_1_2_buf [3*3-1:0];
	wire [15:0] layer_2_3 [2:0];
	reg  [15:0] layer_3_4 [1:0];
	reg  [15:0] layer_4_5;
	reg  [15:0] layer_5_end;	
	
	assign dout = layer_5_end;
	assign dout_valid = layer_valid[latency-1]; 
  
	generate 	
		for(i = 0; i < 3; i = i + 1) 
		begin:layer1
		     xbip_dsp48_macro_preadder_l3 pre_adder (
                .CLK(clk),
                .A(din_array[i*3]),
                .B(kernel_array[i*3]),
                .D(plus_or_minus[i] == 1'b0 ? din_array[i*3+2] : -din_array[i*3+2]),
                .P(layer_1_2[i])
            );			
		end

		for(i = 0; i < 3; i = i + 1) 
		begin:layer2
			xbip_dsp48_macro_macc_l3 macc_ABC (
				.CLK(clk),
				.A(layer_1_2_buf[i*3+2]),
				.B(kernel_array[i*3+1]),
				.C(layer_1_2[i]),
				.P(layer_2_3[i])
			);
		end		
		
    endgenerate
    
    integer j;    
    always@(posedge clk) begin    
        
    	if( resetn == 1'b0 ) begin    
			layer_valid <= 0;
    		
			
			for(j = 0; j < 9; j = j + 1)begin
				layer_1_2_buf[j] <= 9'b0;							
			end		
			
			for(j = 0; j < 2; j = j + 1)begin						
				layer_3_4[j] <= 16'b0;			
			end		
			layer_4_5 <= 16'b0;			
			layer_5_end <= 16'b0;
			
    	end
    	else begin

			for(j = 0; j < 3; j = j + 1) begin
				layer_1_2_buf[j*3] <= din_array[j*3+1];		
				layer_1_2_buf[j*3+1] <= layer_1_2_buf[j*3];
				layer_1_2_buf[j*3+2] <= layer_1_2_buf[j*3+1];
			end		
		


			layer_3_4[0] <= layer_2_3[0] + layer_2_3[1];
			layer_3_4[1] <= layer_2_3[2];			
			

			layer_4_5 <= layer_3_4[0] + layer_3_4[1];
			

			layer_5_end <= layer_4_5;
			

			layer_valid <= {layer_valid, din_valid};

        end
    end	
	
endmodule