data/full_repos/permissive/10379745/hw_de0/hard/hp_display/hp_display.sv
 line:58 column:26: Illegal character "'"
1: b'%Error: data/full_repos/permissive/10379745/hw_de0/hard/hp_display/hp_display.sv:74: Cannot find include file: log2.inc\n`include "log2.inc" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc\n             data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc.v\n             data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc.sv\n             log2.inc\n             log2.inc.v\n             log2.inc.sv\n             obj_dir/log2.inc\n             obj_dir/log2.inc.v\n             obj_dir/log2.inc.sv\n%Error: Exiting due to 1 error(s)\n'
module so_reg_left #( parameter      D = 8)
                    ( input         CLK,
                      input         UPDATE,
                      input         SHIFT,
                      input [D-1:0] DATA,
                      output        OUT,
                      output        EMPTY );

`include "log2.inc"

localparam C = log2(D-1); 

logic [D-1:0] sreg;
logic [C-1:0] cnt;

always_ff@(posedge CLK)
  if     (UPDATE)  sreg <= DATA;
  else if(SHIFT)   sreg <= {sreg[D-2:0], 1'b0};

always_ff@(posedge CLK)
  if     (UPDATE)  cnt <= (D-1);
  else if(SHIFT)   cnt <= cnt - 1'b1;

assign OUT   = sreg[D-1];
assign EMPTY = (cnt == '0);

endmodule
module so_reg_left #( parameter      D = 8)
                    ( input         CLK,
                      input         UPDATE,
                      input         SHIFT,
                      input [D-1:0] DATA,
                      output        OUT,
                      output        EMPTY );


`include "log2.inc"

localparam C = log2(D-1); 

logic [D-1:0] sreg;
logic [C-1:0] cnt;

always_ff@(posedge CLK)
  if     (UPDATE)  sreg <= DATA;
  else if(SHIFT)   sreg <= {sreg[D-2:0], 1'b0};

always_ff@(posedge CLK)
  if     (UPDATE)  cnt <= (D-1);
  else if(SHIFT)   cnt <= cnt - 1'b1;

assign OUT   = sreg[D-1];
assign EMPTY = (cnt == '0);

endmodule