data/full_repos/permissive/159029085/src/cpld_fifo.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/159029085/src/cpld_fifo.v:239: Signal definition not found, creating implicitly: \'slave_rd\'\n                                                                           : ... Suggested alternative: \'slave_rd_b\'\n                      .oeb(slave_rd),\n                           ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module glue(
            input [15:0] adr,
            input	ioreq_b,
            input	clk,
            input	reset_b,
            input	wr_b,
            input	rd_b,
            input	slave_rd_b,
            input	slave_wr,

            output	host_slave_wclk,
            output	slave_host_oeb,
            
            output	slave_dor,
            inout	host_dor,
            output	slave_dir,
            inout	host_dir
            );

  reg	slave_wr_q;
  reg	slave_rd_qb;
  reg	host_wr_qb;
  reg	host_rd_qb;
  reg	host_dor_q;
  reg	slave_dor_q;
  reg	host_slave_wclk_en_lat_qb;
  



  wire fd1_decode_b;
  
  wire host_sel_data_b = ( fd1_decode_b | adr[9] |  adr[0] | ioreq_b) ;
  wire host_sel_stat_b = ( fd1_decode_b | adr[9] | !adr[0] | ioreq_b) ;

  always @ ( clk )
    if ( !clk )
      host_slave_wclk_en_lat_qb <= host_sel_data_b | wr_b;
  
  assign host_slave_wclk = !host_slave_wclk_en_lat_qb & clk;
  
  assign slave_host_oeb =  host_sel_data_b | rd_b;


  
  assign {host_dir, host_dor} = ( host_sel_stat_b | rd_b ) ? 2'bz: { !slave_dor_q & slave_rd_qb, host_dor_q & !slave_wr_q};  
  assign {slave_dir, slave_dor} = { !host_dor_q & host_rd_qb , slave_dor_q & host_wr_qb};

  nand8 nand8_u(
                .i({adr[15:10], adr[8], adr[7]} ),
                .o(fd1_decode_b)
                );
  
  always @ ( posedge clk or negedge reset_b )
    if (!reset_b) 
      { slave_wr_q, slave_rd_qb, host_wr_qb, host_rd_qb, host_dor_q, slave_dor_q} <= 6'b011100;
    else begin 
      slave_wr_q  <= slave_wr;
      slave_rd_qb  <= slave_rd_b;    
      host_wr_qb   <= host_sel_data_b | wr_b;
      host_rd_qb <= host_sel_data_b  | rd_b;
      slave_dor_q <= !host_wr_qb | (slave_rd_qb & slave_dor_q);
      host_dor_q  <= slave_wr_q  | (host_rd_qb & host_dor_q);      
    end
  
  
endmodule
module glue(
            input [15:0] adr,
            input	ioreq_b,
            input	clk,
            input	reset_b,
            input	wr_b,
            input	rd_b,
            input	slave_rd_b,
            input	slave_wr,

            output	host_slave_wclk,
            output	slave_host_oeb,
            
            output	slave_dor,
            inout	host_dor,
            output	slave_dir,
            inout	host_dir
            );


  reg	slave_wr_q;
  reg	slave_rd_qb;
  reg	host_wr_qb;
  reg	host_rd_qb;
  reg	host_dor_q;
  reg	slave_dor_q;
  reg	host_slave_wclk_en_lat_qb;
  



  wire fd1_decode_b;
  
  wire host_sel_data_b = ( fd1_decode_b | adr[9] |  adr[0] | ioreq_b) ;
  wire host_sel_stat_b = ( fd1_decode_b | adr[9] | !adr[0] | ioreq_b) ;

  always @ ( clk )
    if ( !clk )
      host_slave_wclk_en_lat_qb <= host_sel_data_b | wr_b;
  
  assign host_slave_wclk = !host_slave_wclk_en_lat_qb & clk;
  
  assign slave_host_oeb =  host_sel_data_b | rd_b;


  
  assign {host_dir, host_dor} = ( host_sel_stat_b | rd_b ) ? 2'bz: { !slave_dor_q & slave_rd_qb, host_dor_q & !slave_wr_q};  
  assign {slave_dir, slave_dor} = { !host_dor_q & host_rd_qb , slave_dor_q & host_wr_qb};

  nand8 nand8_u(
                .i({adr[15:10], adr[8], adr[7]} ),
                .o(fd1_decode_b)
                );
  
  always @ ( posedge clk or negedge reset_b )
    if (!reset_b) 
      { slave_wr_q, slave_rd_qb, host_wr_qb, host_rd_qb, host_dor_q, slave_dor_q} <= 6'b011100;
    else begin 
      slave_wr_q  <= slave_wr;
      slave_rd_qb  <= slave_rd_b;    
      host_wr_qb   <= host_sel_data_b | wr_b;
      host_rd_qb <= host_sel_data_b  | rd_b;
      slave_dor_q <= !host_wr_qb | (slave_rd_qb & slave_dor_q);
      host_dor_q  <= slave_wr_q  | (host_rd_qb & host_dor_q);      
    end
  
  
endmodule