data/full_repos/permissive/143278/ivltests/pr2219441b.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441b.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 1\'b0) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441b.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 1\'b1) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441b.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 1\'bx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441b.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 1\'bz) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441b.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 1\'b1) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441b.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 1\'b0) begin\n    ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module parent(input[1:0] sel, input [1:0] A, inout Z);
  child child[1:0](.sel(sel), .A(A), .Z(Z));
endmodule
module parent(input[1:0] sel, input [1:0] A, inout Z);

  child child[1:0](.sel(sel), .A(A), .Z(Z));
endmodule