data/full_repos/permissive/157587577/Basics/verilog/Labs/SyncAutomates/example_automates/milley_automate/milley_automate_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/157587577/Basics/verilog/Labs/SyncAutomates/example_automates/milley_automate/milley_automate_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n    # 400\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157587577/Basics/verilog/Labs/SyncAutomates/example_automates/milley_automate/milley_automate_testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #50 clk <= ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157587577/Basics/verilog/Labs/SyncAutomates/example_automates/milley_automate/milley_automate_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #100 counter <= counter + 1;\n    ^\n%Error: data/full_repos/permissive/157587577/Basics/verilog/Labs/SyncAutomates/example_automates/milley_automate/milley_automate_testbench.v:30: Cannot find file containing module: \'milley_automate\'\nmilley_automate uut(.clk(clk), .reset(reset), .a(a), .b(b));\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157587577/Basics/verilog/Labs/SyncAutomates/example_automates/milley_automate,data/full_repos/permissive/157587577/milley_automate\n             data/full_repos/permissive/157587577/Basics/verilog/Labs/SyncAutomates/example_automates/milley_automate,data/full_repos/permissive/157587577/milley_automate.v\n             data/full_repos/permissive/157587577/Basics/verilog/Labs/SyncAutomates/example_automates/milley_automate,data/full_repos/permissive/157587577/milley_automate.sv\n             milley_automate\n             milley_automate.v\n             milley_automate.sv\n             obj_dir/milley_automate\n             obj_dir/milley_automate.v\n             obj_dir/milley_automate.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module milley_automate_testbench();

reg [1:0] a;
wire [1:0] b;
reg clk;
reg reset;

reg [31:0] counter;

milley_automate uut(.clk(clk), .reset(reset), .a(a), .b(b));

initial
begin
    clk <= 0;
    reset <= 1;
    a <= 0;
    counter <= 0;
    # 400
    reset <= 0;
end

always
begin
    #50 clk <= ~clk;
    #100 counter <= counter + 1;
    if (counter == 5)
    begin
        a <= 2'b11;
    end
    if (counter == 7)
    begin
        a <= 2'b01;
    end

    if (counter == 8)
    begin
        a <= 2'b00;
    end
    if (counter == 11)
    begin
        a <= 2'b01;
    end
    if (counter == 13)
    begin
        a <= 2'b11;
    end
    if (counter == 14)
    begin
        a <= 2'b11;
    end
    if (counter == 16)
    begin
        a <= 0;
        counter <= 0;
    end
end

endmodule
module milley_automate_testbench();


reg [1:0] a;
wire [1:0] b;
reg clk;
reg reset;

reg [31:0] counter;

milley_automate uut(.clk(clk), .reset(reset), .a(a), .b(b));

initial
begin
    clk <= 0;
    reset <= 1;
    a <= 0;
    counter <= 0;
    # 400
    reset <= 0;
end

always
begin
    #50 clk <= ~clk;
    #100 counter <= counter + 1;
    if (counter == 5)
    begin
        a <= 2'b11;
    end
    if (counter == 7)
    begin
        a <= 2'b01;
    end

    if (counter == 8)
    begin
        a <= 2'b00;
    end
    if (counter == 11)
    begin
        a <= 2'b01;
    end
    if (counter == 13)
    begin
        a <= 2'b11;
    end
    if (counter == 14)
    begin
        a <= 2'b11;
    end
    if (counter == 16)
    begin
        a <= 0;
        counter <= 0;
    end
end

endmodule