data/full_repos/permissive/164033466/Tests/testbench.v
1: b'%Error: data/full_repos/permissive/164033466/Tests/testbench.v:3: Cannot find include file: cpu.v\n`include "cpu.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164033466/Tests,data/full_repos/permissive/164033466/cpu.v\n             data/full_repos/permissive/164033466/Tests,data/full_repos/permissive/164033466/cpu.v.v\n             data/full_repos/permissive/164033466/Tests,data/full_repos/permissive/164033466/cpu.v.sv\n             cpu.v\n             cpu.v.v\n             cpu.v.sv\n             obj_dir/cpu.v\n             obj_dir/cpu.v.v\n             obj_dir/cpu.v.sv\n%Error: data/full_repos/permissive/164033466/Tests/testbench.v:4: Cannot find include file: peripheral.v\n`include "peripheral.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/164033466/Tests/testbench.v:34: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/164033466/Tests/testbench.v:35: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/164033466/Tests/testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/164033466/Tests/testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/164033466/Tests/testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\nalways #7 perClock = !perClock;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/164033466/Tests/testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\nalways #5 cpuClock = !cpuClock;\n       ^\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module testbench;

	reg cpuClock, perClock, reset;

	wire [0:0] ACK;
	wire [0:0] SEND;
	wire [31:0] DATA;


	fsmCPU uutCPU(
		.ACK(ACK),   
		.clk(cpuClock),  
		.rst(reset),
		.outDATA(DATA),
		.outSEND(SEND)
	);


	fsmPeripheral uutPeripheral(
		.SEND(SEND),  
		.clk(perClock),  
		.rst(reset),
    	.inputData(DATA),
    	.outACK(ACK)
	);

initial begin
	$dumpfile("dump.vcd");
	$dumpvars;


	cpuClock = 0;  
	perClock = 0;
	reset = 1;      
  

	#50;
	reset = 0;

  	#100;
  	
	$finish;
end  

always #7 perClock = !perClock;
always #5 cpuClock = !cpuClock;
  
endmodule
module testbench;


	reg cpuClock, perClock, reset;

	wire [0:0] ACK;
	wire [0:0] SEND;
	wire [31:0] DATA;


	fsmCPU uutCPU(
		.ACK(ACK),   
		.clk(cpuClock),  
		.rst(reset),
		.outDATA(DATA),
		.outSEND(SEND)
	);


	fsmPeripheral uutPeripheral(
		.SEND(SEND),  
		.clk(perClock),  
		.rst(reset),
    	.inputData(DATA),
    	.outACK(ACK)
	);

initial begin
	$dumpfile("dump.vcd");
	$dumpvars;


	cpuClock = 0;  
	perClock = 0;
	reset = 1;      
  

	#50;
	reset = 0;

  	#100;
  	
	$finish;
end  

always #7 perClock = !perClock;
always #5 cpuClock = !cpuClock;
  
endmodule