data/full_repos/permissive/134057391/cpld/m6502_db/rtl/m6502_db.v
None: at end of input
1: b"%Error: data/full_repos/permissive/134057391/cpld/m6502_db/rtl/m6502_db.v:60: Cannot find file containing module: 'rs_latch'\n    rs_latch reset_debounce (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/134057391/cpld/m6502_db/rtl,data/full_repos/permissive/134057391/rs_latch\n             data/full_repos/permissive/134057391/cpld/m6502_db/rtl,data/full_repos/permissive/134057391/rs_latch.v\n             data/full_repos/permissive/134057391/cpld/m6502_db/rtl,data/full_repos/permissive/134057391/rs_latch.sv\n             rs_latch\n             rs_latch.v\n             rs_latch.sv\n             obj_dir/rs_latch\n             obj_dir/rs_latch.v\n             obj_dir/rs_latch.sv\n%Error: data/full_repos/permissive/134057391/cpld/m6502_db/rtl/m6502_db.v:80: Cannot find file containing module: 'rs_latch'\n    rs_latch run_debounce (\n    ^~~~~~~~\n%Error: data/full_repos/permissive/134057391/cpld/m6502_db/rtl/m6502_db.v:96: Cannot find file containing module: 'rs_latch'\n    rs_latch run_latch (\n    ^~~~~~~~\n%Error: data/full_repos/permissive/134057391/cpld/m6502_db/rtl/m6502_db.v:119: Cannot find file containing module: 'rs_latch3'\n    rs_latch3 ss_debounce (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/134057391/cpld/m6502_db/rtl/m6502_db.v:128: Cannot find file containing module: 'ss_core'\n    ss_core ss_mod (\n    ^~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module m6502_db(
    input RESET_NO,
    input RESET_NC,
    input RUN_N,
    input HALT_N,
    input PHI2,
    input SYNC_N,
    input SS_COM,
    input SI_NC,
    input SC_NC,
    input W_N,
    output RESET_N,
    output RDY,

    output LED_WR_N,
    output LED_SYN_N
    );

    wire sync;
    assign sync = ! SYNC_N;






    wire reset;

    (* NOREDUCE = "TRUE"*)
    rs_latch reset_debounce (
        .s_n(RESET_NO),
        .r_n(RESET_NC),
        .q(reset));

    assign RESET_N = (reset) ? !reset : 1'bZ;








    wire run, halt;
    wire gated_run, gated_halt;
    wire rdy_run;


    (* NOREDUCE = "TRUE"*)
    rs_latch run_debounce (
        .s_n(RUN_N),
        .r_n(HALT_N),
        .q(run),
        .q_n(halt));




    assign gated_run = run && ! PHI2;



    assign gated_halt = halt && ! PHI2 && sync;

    (* NOREDUCE = "TRUE"*)
    rs_latch run_latch (
        .s_n( ! gated_run),
        .r_n( ! gated_halt),
        .q(rdy_run));







    wire gated_set_n;
    wire single_step;
    wire single_inst_n;
    wire rdy_cycle;
    wire rdy_inst;
    wire wcycle;


    assign gated_set_n = SS_COM || PHI2;


    (* NOREDUCE = "TRUE"*)
    rs_latch3 ss_debounce (
        .r1_n(SC_NC),
        .s_n(gated_set_n),
        .r2_n(SI_NC),
        .q(single_step),
        .q2_n(single_inst_n)
    );


    ss_core ss_mod (
        .phi2(PHI2),
        .sync(sync),
        .rd(W_N),
        .ss(single_step),
        .si_n(single_inst_n),
        .rdy_cycle(rdy_cycle),
        .rdy_inst(rdy_inst),
        .wcycle(wcycle)
    );





    assign RDY = rdy_run || rdy_cycle || rdy_inst;

    assign LED_SYN_N = ! (sync && ! wcycle);

    assign LED_WR_N = ! wcycle;


endmodule
module m6502_db(
    input RESET_NO,
    input RESET_NC,
    input RUN_N,
    input HALT_N,
    input PHI2,
    input SYNC_N,
    input SS_COM,
    input SI_NC,
    input SC_NC,
    input W_N,
    output RESET_N,
    output RDY,

    output LED_WR_N,
    output LED_SYN_N
    );


    wire sync;
    assign sync = ! SYNC_N;






    wire reset;

    (* NOREDUCE = "TRUE"*)
    rs_latch reset_debounce (
        .s_n(RESET_NO),
        .r_n(RESET_NC),
        .q(reset));

    assign RESET_N = (reset) ? !reset : 1'bZ;








    wire run, halt;
    wire gated_run, gated_halt;
    wire rdy_run;


    (* NOREDUCE = "TRUE"*)
    rs_latch run_debounce (
        .s_n(RUN_N),
        .r_n(HALT_N),
        .q(run),
        .q_n(halt));




    assign gated_run = run && ! PHI2;



    assign gated_halt = halt && ! PHI2 && sync;

    (* NOREDUCE = "TRUE"*)
    rs_latch run_latch (
        .s_n( ! gated_run),
        .r_n( ! gated_halt),
        .q(rdy_run));







    wire gated_set_n;
    wire single_step;
    wire single_inst_n;
    wire rdy_cycle;
    wire rdy_inst;
    wire wcycle;


    assign gated_set_n = SS_COM || PHI2;


    (* NOREDUCE = "TRUE"*)
    rs_latch3 ss_debounce (
        .r1_n(SC_NC),
        .s_n(gated_set_n),
        .r2_n(SI_NC),
        .q(single_step),
        .q2_n(single_inst_n)
    );


    ss_core ss_mod (
        .phi2(PHI2),
        .sync(sync),
        .rd(W_N),
        .ss(single_step),
        .si_n(single_inst_n),
        .rdy_cycle(rdy_cycle),
        .rdy_inst(rdy_inst),
        .wcycle(wcycle)
    );





    assign RDY = rdy_run || rdy_cycle || rdy_inst;

    assign LED_SYN_N = ! (sync && ! wcycle);

    assign LED_WR_N = ! wcycle;


endmodule