data/full_repos/permissive/217697217/problems/04_hex_display/top.v
1: b"%Error: data/full_repos/permissive/217697217/problems/04_hex_display/top.v:22: Cannot find file containing module: 'clk_div'\n  clk_div #(.x(16)) div(.clk(CLK),.clk_out(clk2));\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/217697217/problems/04_hex_display,data/full_repos/permissive/217697217/clk_div\n             data/full_repos/permissive/217697217/problems/04_hex_display,data/full_repos/permissive/217697217/clk_div.v\n             data/full_repos/permissive/217697217/problems/04_hex_display,data/full_repos/permissive/217697217/clk_div.sv\n             clk_div\n             clk_div.v\n             clk_div.sv\n             obj_dir/clk_div\n             obj_dir/clk_div.v\n             obj_dir/clk_div.sv\n%Error: data/full_repos/permissive/217697217/problems/04_hex_display/top.v:30: Cannot find file containing module: 'hex_display'\n  hex_display display(.clk(clk2),.data(d),.anodes(anodes),.segments(segments));\n  ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module top(
    input CLK,

    output DS_EN1, DS_EN2, DS_EN3, DS_EN4,
    output DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G
);

wire [15:0]d = 16'hCAFE;

wire [3:0]anodes;
assign {DS_EN1, DS_EN2, DS_EN3, DS_EN4} = ~anodes;

wire [6:0]segments;
assign {DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G} = segments;



  clk_div #(.x(16)) div(.clk(CLK),.clk_out(clk2));


  hex_display display(.clk(clk2),.data(d),.anodes(anodes),.segments(segments));
endmodule
module top(
    input CLK,

    output DS_EN1, DS_EN2, DS_EN3, DS_EN4,
    output DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G
);


wire [15:0]d = 16'hCAFE;

wire [3:0]anodes;
assign {DS_EN1, DS_EN2, DS_EN3, DS_EN4} = ~anodes;

wire [6:0]segments;
assign {DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G} = segments;



  clk_div #(.x(16)) div(.clk(CLK),.clk_out(clk2));


  hex_display display(.clk(clk2),.data(d),.anodes(anodes),.segments(segments));
endmodule