data/full_repos/permissive/143278/ivltests/string3.v
data/verilator_xmls/83fea92d-ec6d-4f0c-9206-ffe73b686a98.xml
module main;

   reg [8*7:1] foo;
   reg [7:0]   tmp;


   initial
     begin
	foo = "PASSED";
	tmp = foo[8*7:8*6+1];

	if (tmp !== 8'h00) begin
	   $display("FAILED -- high bits are %b", tmp);
	   $finish;
	end
	$display("%s", foo);
     end

endmodule
module main;


   reg [8*7:1] foo;
   reg [7:0]   tmp;


   initial
     begin
	foo = "PASSED";
	tmp = foo[8*7:8*6+1];

	if (tmp !== 8'h00) begin
	   $display("FAILED -- high bits are %b", tmp);
	   $finish;
	end
	$display("%s", foo);
     end

endmodule