data/full_repos/permissive/179198883/test.sv
 line:2 column:2: Illegal character "'"
1: b'%Error: data/full_repos/permissive/179198883/test.sv:2: syntax error, unexpected "\'"\n\'timescale 1ns/ps\n^\n%Error: data/full_repos/permissive/179198883/test.sv:13: syntax error, unexpected \'.\', expecting \')\'\n  .din(din),\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/179198883/test.sv:19: Unsupported: Ignoring delay on this delayed statement.\n  #1 din = $random;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/179198883/test.sv:20: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n'
module tb;
'timescale 1ns/ps
logic clock, rd_en, wr_en, full, empty, rst;
logic [15 : 0] dout, din;

sync_fifo fifo(
  .clock(clock),
  .rst(rst),
  .empty(empty),
  .full(full),
  .wr_en(wr_en),
  .rd_en(rd_en)
  .din(din),
  .dout(dout)
);

assign #5 clock = !clock; 
always@(posedge clock)
  #1 din = $random;
  end
  
initial 
begin
clock = 0;
reset = 1;
din = 16'h0;
wr_en = 0;
rd_en = 0;

#100 reset = 0;
#10 wr_en = 1;
#250 wr_en = 0;

#10 rd_en = 1;

#1000 $finish;

end 
endmodule
module tb;

'timescale 1ns/ps
logic clock, rd_en, wr_en, full, empty, rst;
logic [15 : 0] dout, din;

sync_fifo fifo(
  .clock(clock),
  .rst(rst),
  .empty(empty),
  .full(full),
  .wr_en(wr_en),
  .rd_en(rd_en)
  .din(din),
  .dout(dout)
);

assign #5 clock = !clock; 
always@(posedge clock)
  #1 din = $random;
  end
  
initial 
begin
clock = 0;
reset = 1;
din = 16'h0;
wr_en = 0;
rd_en = 0;

#100 reset = 0;
#10 wr_en = 1;
#250 wr_en = 0;

#10 rd_en = 1;

#1000 $finish;

end 
endmodule