data/full_repos/permissive/127519632/mean_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:13: Unsupported: Ignoring delay on this delayed statement.\n    #12 rst_n = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:14: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 128;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:15: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 124;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:16: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 127;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:17: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 120;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:18: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 124;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:19: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 122;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:20: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 124;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:21: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 126;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:22: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 128;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:23: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 123;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:24: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 128;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:25: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 124;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:26: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 127;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:27: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 120;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:28: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 124;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 122;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 124;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:31: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:32: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:34: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:35: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:36: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:41: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:42: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:43: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/mean_tb.sv:47: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/127519632/mean_tb.sv:7: Cannot find file containing module: \'mean\'\nmean #(8, 8, 3)U1(out, in, rst_n, clk);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/mean\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/mean.v\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/mean.sv\n             mean\n             mean.v\n             mean.sv\n             obj_dir/mean\n             obj_dir/mean.v\n             obj_dir/mean.sv\n%Error: Exiting due to 1 error(s), 32 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mean_tb;
    
reg [7:0] in;
reg rst_n, clk;
wire [7:0] out;

mean #(8, 8, 3)U1(out, in, rst_n, clk);

initial begin
    clk = 1;
    rst_n = 0;
    in = 1;
    #12 rst_n = 1;
    #10 in = 128;
    #10 in = 124;
    #10 in = 127;
    #10 in = 120;
    #10 in = 124;
    #10 in = 122;
    #10 in = 124;
    #10 in = 126;
    #10 in = 128;
    #10 in = 123;
    #10 in = 128;
    #10 in = 124;
    #10 in = 127;
    #10 in = 120;
    #10 in = 124;
    #10 in = 122;
    #10 in = 124;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    $stop;
end

always #5 clk = ~clk;

endmodule
module mean_tb;

    
reg [7:0] in;
reg rst_n, clk;
wire [7:0] out;

mean #(8, 8, 3)U1(out, in, rst_n, clk);

initial begin
    clk = 1;
    rst_n = 0;
    in = 1;
    #12 rst_n = 1;
    #10 in = 128;
    #10 in = 124;
    #10 in = 127;
    #10 in = 120;
    #10 in = 124;
    #10 in = 122;
    #10 in = 124;
    #10 in = 126;
    #10 in = 128;
    #10 in = 123;
    #10 in = 128;
    #10 in = 124;
    #10 in = 127;
    #10 in = 120;
    #10 in = 124;
    #10 in = 122;
    #10 in = 124;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    #10 in = 0;
    $stop;
end

always #5 clk = ~clk;

endmodule