data/full_repos/permissive/200314387/verilog/74139/hct74139.v
 line:27: before: "("
data/verilator_xmls/ecf5967d-4f3a-4aef-9e2a-36ddb0b1b012.xml
function [3:0] f74139(input [1:0] A, input _E); 

        logic [3:0] f74139;


        if (_E == 0) begin 
            case (A) 

                0: f74139 = 4'b1110;
                1: f74139 = 4'b1101;
                2: f74139 = 4'b1011; 
                3: f74139 = 4'b0111; 
            endcase
        end 
        else
        if (_E == 1) begin 
            f74139 = 4'b1111;
        end

    endfunction
function [3:0] f74139(input [1:0] A, input _E);
 

        logic [3:0] f74139;


        if (_E == 0) begin 
            case (A) 

                0: f74139 = 4'b1110;
                1: f74139 = 4'b1101;
                2: f74139 = 4'b1011; 
                3: f74139 = 4'b0111; 
            endcase
        end 
        else
        if (_E == 1) begin 
            f74139 = 4'b1111;
        end

    endfunction