data/full_repos/permissive/2084115/rtl/library/jelly_pulse_async.v
data/verilator_xmls/800569d7-f7ae-4111-b97d-bf985f7a74d9.xml
module jelly_pulse_async
        #(
            parameter   ASYNC = 1
        )
        (
            input   wire                        s_reset,
            input   wire                        s_clk,
            input   wire                        s_pulse,
            
            input   wire                        m_reset,
            input   wire                        m_clk,
            output  wire                        m_pulse
        );
    
    generate
    if ( ASYNC ) begin : blk_async

                                    reg                         reg_s_sem0;
        
        (* ASYNC_REG = "true" *)    reg                         reg_m_sem0_ff;
                                    reg                         reg_m_sem0;
                                    reg                         reg_m_sem1;
        
        
        

        always @(posedge s_clk) begin
            if ( s_reset ) begin
                reg_s_sem0 <= 1'b0;
            end
            else begin
                if ( s_pulse ) begin
                    reg_s_sem0 <= ~reg_s_sem0;
                end
            end
        end
        
        

        always @(posedge m_clk) begin
            if ( m_reset ) begin
                reg_m_sem0_ff <= 1'b0;
                reg_m_sem0    <= 1'b0;
                reg_m_sem1    <= 1'b0;
            end
            else begin

                reg_m_sem0_ff <= reg_s_sem0;
                reg_m_sem0    <= reg_m_sem0_ff;
                
                if ( m_pulse ) begin
                    reg_m_sem1 <= ~reg_m_sem1;
                end
            end
        end
        
        assign m_pulse = (reg_m_sem0 != reg_m_sem1);
    end
    else begin : blk_sync
        assign m_pulse = s_pulse;
    end
    endgenerate
    
    
endmodule
module jelly_pulse_async
        #(
            parameter   ASYNC = 1
        )
        (
            input   wire                        s_reset,
            input   wire                        s_clk,
            input   wire                        s_pulse,
            
            input   wire                        m_reset,
            input   wire                        m_clk,
            output  wire                        m_pulse
        );

    
    generate
    if ( ASYNC ) begin : blk_async

                                    reg                         reg_s_sem0;
        
        (* ASYNC_REG = "true" *)    reg                         reg_m_sem0_ff;
                                    reg                         reg_m_sem0;
                                    reg                         reg_m_sem1;
        
        
        

        always @(posedge s_clk) begin
            if ( s_reset ) begin
                reg_s_sem0 <= 1'b0;
            end
            else begin
                if ( s_pulse ) begin
                    reg_s_sem0 <= ~reg_s_sem0;
                end
            end
        end
        
        

        always @(posedge m_clk) begin
            if ( m_reset ) begin
                reg_m_sem0_ff <= 1'b0;
                reg_m_sem0    <= 1'b0;
                reg_m_sem1    <= 1'b0;
            end
            else begin

                reg_m_sem0_ff <= reg_s_sem0;
                reg_m_sem0    <= reg_m_sem0_ff;
                
                if ( m_pulse ) begin
                    reg_m_sem1 <= ~reg_m_sem1;
                end
            end
        end
        
        assign m_pulse = (reg_m_sem0 != reg_m_sem1);
    end
    else begin : blk_sync
        assign m_pulse = s_pulse;
    end
    endgenerate
    
    
endmodule