data/full_repos/permissive/147690299/lab/31_fsm_basic/rtl/clk_divider.v
data/verilator_xmls/a9ab9c3f-516d-4e20-9a76-34ccd2123aaa.xml
module clk_divider
#( 
    parameter WIDTH = 24 
)(
    input  clk,
    input  rst_n,
    output strobe,
    output half
);
    localparam ZERO = { WIDTH { 1'b0 } };


    reg [WIDTH-1:0] counter;
    always @ (posedge clk or negedge rst_n)
    begin
        if (~rst_n)
            counter <= ZERO;
        else
            counter <= counter + 1;
    end


    assign strobe = (counter == ZERO);
    assign half   =  counter[WIDTH-1];

endmodule
module clk_divider
#( 
    parameter WIDTH = 24 
)(
    input  clk,
    input  rst_n,
    output strobe,
    output half
);

    localparam ZERO = { WIDTH { 1'b0 } };


    reg [WIDTH-1:0] counter;
    always @ (posedge clk or negedge rst_n)
    begin
        if (~rst_n)
            counter <= ZERO;
        else
            counter <= counter + 1;
    end


    assign strobe = (counter == ZERO);
    assign half   =  counter[WIDTH-1];

endmodule