data/full_repos/permissive/143278/ivltests/long_div.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/long_div.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

  reg [31:0] a, b;
  reg [65:0] a_l, b_l;

  wire [31:0] result = a / b;
  wire [31:0] mod = a % b;
  wire [65:0] result_l = a_l / b_l;
  wire [65:0] mod_l = a_l % b_l;

  initial begin
    a = 'h1;
    b = 'h1;
    a_l = 'h1;
    b_l = 'h1;
    #1;

    $display("Using normal math routines.");
    $display("Result:  %0d\nModulus: %h", result, mod);
    $display("\nUsing wide math routines.");
    $display("Result:  %0d\nModulus: %h", result_l, mod_l);
  end

endmodule
module test();


  reg [31:0] a, b;
  reg [65:0] a_l, b_l;

  wire [31:0] result = a / b;
  wire [31:0] mod = a % b;
  wire [65:0] result_l = a_l / b_l;
  wire [65:0] mod_l = a_l % b_l;

  initial begin
    a = 'h1;
    b = 'h1;
    a_l = 'h1;
    b_l = 'h1;
    #1;

    $display("Using normal math routines.");
    $display("Result:  %0d\nModulus: %h", result, mod);
    $display("\nUsing wide math routines.");
    $display("Result:  %0d\nModulus: %h", result_l, mod_l);
  end

endmodule