data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/cells_sim.v
 line:48: before: "="
1: b'%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/cells_sim.v:492: Cannot find include file: qlal4s3b_sim.v\n`include "qlal4s3b_sim.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220229160/ql-qlf-plugin/pp3,data/full_repos/permissive/220229160/qlal4s3b_sim.v\n             data/full_repos/permissive/220229160/ql-qlf-plugin/pp3,data/full_repos/permissive/220229160/qlal4s3b_sim.v.v\n             data/full_repos/permissive/220229160/ql-qlf-plugin/pp3,data/full_repos/permissive/220229160/qlal4s3b_sim.v.sv\n             qlal4s3b_sim.v\n             qlal4s3b_sim.v.v\n             qlal4s3b_sim.v.sv\n             obj_dir/qlal4s3b_sim.v\n             obj_dir/qlal4s3b_sim.v.v\n             obj_dir/qlal4s3b_sim.v.sv\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/cells_sim.v:494: Cannot find include file: qlal3_sim.v\n`include "qlal3_sim.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/cells_sim.v:496: Cannot find include file: brams_sim.v\n`include "brams_sim.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/cells_sim.v:498: Cannot find include file: mult_sim.v\n`include "mult_sim.v" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module LUT4 (
    output O,
    input  I0,
    I1,
    I2,
    I3
);
  parameter [15:0] INIT = 16'h0;
  parameter EQN = "(I0)";


  specify
    (I0 => O) = 995;
    (I1 => O) = 1437;
    (I2 => O) = 1593;
    (I3 => O) = 1887;
  endspecify

  wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
  wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
  assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT4 (
    output O,
    input  I0,
    I1,
    I2,
    I3
);

  parameter [15:0] INIT = 16'h0;
  parameter EQN = "(I0)";


  specify
    (I0 => O) = 995;
    (I1 => O) = 1437;
    (I2 => O) = 1593;
    (I3 => O) = 1887;
  endspecify

  wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
  wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
  wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
  assign O = I0 ? s1[1] : s1[0];
endmodule