data/full_repos/permissive/204736068/SoM/RTL/servo/tb_top.sv
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/servo/tb_top.sv:60: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/204736068/SoM/RTL/servo/tb_top.sv:64: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("tb_top.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/204736068/SoM/RTL/servo/tb_top.sv:65: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/servo/tb_top.sv:70: Unsupported: Ignoring delay on this delayed statement.\n      #50000000;\n      ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top;
   
   parameter debug = 0;
   
   logic               clk = 1'b0;
   logic               rst, rst_in;
   logic		led_blue;
   logic		led_green;
   logic		led_red;
   logic [2:0] gpio;   
   
   top #()
   dut 
   (

    .gpio				(gpio[2:0]),
    .led_red				(led_red),
    .led_green				(led_green),
    .led_blue				(led_blue)
   );   


   always #10 clk = ~clk;

   initial begin
      $display("Starting simulation");
      $dumpfile("tb_top.vcd");
      $dumpvars;
      


      
      #50000000;
      $display("Finishing simulation");
      $finish;
      
   end
   
   
endmodule
module tb_top;

   
   parameter debug = 0;
   
   logic               clk = 1'b0;
   logic               rst, rst_in;
   logic		led_blue;
   logic		led_green;
   logic		led_red;
   logic [2:0] gpio;   
   
   top #()
   dut 
   (

    .gpio				(gpio[2:0]),
    .led_red				(led_red),
    .led_green				(led_green),
    .led_blue				(led_blue)
   );   


   always #10 clk = ~clk;

   initial begin
      $display("Starting simulation");
      $dumpfile("tb_top.vcd");
      $dumpvars;
      


      
      #50000000;
      $display("Finishing simulation");
      $finish;
      
   end
   
   
endmodule