data/full_repos/permissive/181082280/lab_6/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_6/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #10; a = 3\'h1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_6/tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #10; a = 3\'h4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_6/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #10; a = 3\'h7;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_6/tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/181082280/lab_6/tb.v:23: Unsupported or unknown PLI call: $monitor\n        $monitor ("a=%3b %1h y=%8b %2h", a, a, y, y);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/181082280/lab_6/tb.v:27: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;   \n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;

    reg  [2:0] a;
    wire [7:0] y;


    demux_1 dut (a, y);

    initial begin
        #10; a = 3'h1;
        #10; a = 3'h4;
        #10; a = 3'h7;
        #10;
    end



    initial
        $monitor ("a=%3b %1h y=%8b %2h", a, a, y, y);


    initial 
        $dumpvars;

endmodule
module tb;


    reg  [2:0] a;
    wire [7:0] y;


    demux_1 dut (a, y);

    initial begin
        #10; a = 3'h1;
        #10; a = 3'h4;
        #10; a = 3'h7;
        #10;
    end



    initial
        $monitor ("a=%3b %1h y=%8b %2h", a, a, y, y);


    initial 
        $dumpvars;

endmodule