data/full_repos/permissive/162696624/Traffic Light.v
 line:32: before: "["
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/162696624/Traffic\n        ... Looked in:\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.sv\n             data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624/Traffic.sv\n             obj_dir/data/full_repos/permissive/162696624/Traffic\n             obj_dir/data/full_repos/permissive/162696624/Traffic.v\n             obj_dir/data/full_repos/permissive/162696624/Traffic.sv\n%Error: Cannot find file containing module: Light.v\n%Error: Exiting due to 2 error(s)\n'
module number_set (D1,D0,EN,L0,L1,L2,L3,CLK,RST);
  input EN,L0,L1,L2,L3,CLK,RST;
  output [3:0]D0;
  output [3:0]D1;
  wire [3:0]ATL0;
  wire [3:0]ATH0;
  wire [3:0]ATL1;
  wire [3:0]ATH1;
  wire [3:0]ATL2;
  wire [3:0]ATH2;
  


  
  two_bit_bcd cnt0(ATH0,ATL0,~L0,L0&EN,4'b1001,4'b0000,CLK,RST);
  two_bit_bcd cnt1(ATH1,ATL1,~(L1|L3),(L1|L3)&EN,4'b0000,4'b0101,CLK,RST);
  two_bit_bcd cnt2(ATH2,ATL2,~L2,L2&EN,4'b0011,4'b0000,CLK,RST);
  
  mux4x1 mx0(ATH0,ATH1,ATH2,ATH1,(L3|L2),(L3|L1),D0);
  mux4x1 mx1(ATL0,ATL1,ATL2,ATL1,(L3|L2),(L3|L1),D1);
 
endmodule
module number_set (D1,D0,EN,L0,L1,L2,L3,CLK,RST);

  input EN,L0,L1,L2,L3,CLK,RST;
  output [3:0]D0;
  output [3:0]D1;
  wire [3:0]ATL0;
  wire [3:0]ATH0;
  wire [3:0]ATL1;
  wire [3:0]ATH1;
  wire [3:0]ATL2;
  wire [3:0]ATH2;
  


  
  two_bit_bcd cnt0(ATH0,ATL0,~L0,L0&EN,4'b1001,4'b0000,CLK,RST);
  two_bit_bcd cnt1(ATH1,ATL1,~(L1|L3),(L1|L3)&EN,4'b0000,4'b0101,CLK,RST);
  two_bit_bcd cnt2(ATH2,ATL2,~L2,L2&EN,4'b0011,4'b0000,CLK,RST);
  
  mux4x1 mx0(ATH0,ATH1,ATH2,ATH1,(L3|L2),(L3|L1),D0);
  mux4x1 mx1(ATL0,ATL1,ATL2,ATL1,(L3|L2),(L3|L1),D1);
 
endmodule