data/full_repos/permissive/131921633/tv/Data/Arith/extend.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.v:1: Cannot find include file: Data/Arith/SignedUnsigned.v\n`include "Data/Arith/SignedUnsigned.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Data/Arith,data/full_repos/permissive/131921633/Data/Arith/SignedUnsigned.v\n             data/full_repos/permissive/131921633/tv/Data/Arith,data/full_repos/permissive/131921633/Data/Arith/SignedUnsigned.v.v\n             data/full_repos/permissive/131921633/tv/Data/Arith,data/full_repos/permissive/131921633/Data/Arith/SignedUnsigned.v.sv\n             Data/Arith/SignedUnsigned.v\n             Data/Arith/SignedUnsigned.v.v\n             Data/Arith/SignedUnsigned.v.sv\n             obj_dir/Data/Arith/SignedUnsigned.v\n             obj_dir/Data/Arith/SignedUnsigned.v.v\n             obj_dir/Data/Arith/SignedUnsigned.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.v:2: Cannot find include file: Data/Array/Pack.v\n`include "Data/Array/Pack.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.v:3: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.v:11: Define or directive not defined: \'`Data_Array_Pack_T\'\n ( `Data_Array_Pack_T(input, DEPTH, IN_W)  in\n   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.v:11: syntax error, unexpected \'(\', expecting \'[\'\n ( `Data_Array_Pack_T(input, DEPTH, IN_W)  in\n                      ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.v:12: Define or directive not defined: \'`Data_Array_Pack_T\'\n , `Data_Array_Pack_T(output, DEPTH, OUT_W) out\n   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.v:13: Define or directive not defined: \'`Data_Control_Control_T\'\n , `Data_Control_Control_T(input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.v:16: Define or directive not defined: \'`Data_Array_Pack_unpackDecl\'\n`Data_Array_Pack_unpackDecl(wire, DEPTH, IN_W, in, in$, i1, updl1)\n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.v:17: Define or directive not defined: \'`Data_Array_Pack_packDecl\'\n`Data_Array_Pack_packDecl(reg, DEPTH, IN_W, out$, out, i2, pdl1)\n^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.v:20: syntax error, unexpected always\nalways @(posedge `Data_Control_Control_Clock(ctrl))\n^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.v:20: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways @(posedge `Data_Control_Control_Clock(ctrl))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n'
module Data_Arith_extend #
	( parameter IN_W  = 16
	, parameter OUT_W = 32
	, parameter DEPTH = 2
	, parameter DELAY = 0
	)
	( `Data_Array_Pack_T(input, DEPTH, IN_W)  in
	, `Data_Array_Pack_T(output, DEPTH, OUT_W) out
	, `Data_Control_Control_T(input) ctrl
	);

`Data_Array_Pack_unpackDecl(wire, DEPTH, IN_W, in, in$, i1, updl1)
`Data_Array_Pack_packDecl(reg, DEPTH, IN_W, out$, out, i2, pdl1)

integer i;
always @(posedge `Data_Control_Control_Clock(ctrl))
	for(i = 0; i < DEPTH; i = i + 1)
		out$[i] <= OUT_W'(in$[i]);
endmodule
module Data_Arith_extend #
	( parameter IN_W  = 16
	, parameter OUT_W = 32
	, parameter DEPTH = 2
	, parameter DELAY = 0
	)
	( `Data_Array_Pack_T(input, DEPTH, IN_W)  in
	, `Data_Array_Pack_T(output, DEPTH, OUT_W) out
	, `Data_Control_Control_T(input) ctrl
	);


`Data_Array_Pack_unpackDecl(wire, DEPTH, IN_W, in, in$, i1, updl1)
`Data_Array_Pack_packDecl(reg, DEPTH, IN_W, out$, out, i2, pdl1)

integer i;
always @(posedge `Data_Control_Control_Clock(ctrl))
	for(i = 0; i < DEPTH; i = i + 1)
		out$[i] <= OUT_W'(in$[i]);
endmodule