data/full_repos/permissive/186443491/model/beforeExtend.v
 line:70: before: ")"
1: b"%Error: data/full_repos/permissive/186443491/model/beforeExtend.v:70: syntax error, unexpected ')', expecting '['\n );\n ^\n%Error: data/full_repos/permissive/186443491/model/beforeExtend.v:72: syntax error, unexpected input\n    input clock, resetn, generateEn;\n    ^~~~~\n%Error: data/full_repos/permissive/186443491/model/beforeExtend.v:76: syntax error, unexpected input\n    input moveEn;\n    ^~~~~\n%Error: data/full_repos/permissive/186443491/model/beforeExtend.v:86: syntax error, unexpected IDENTIFIER\n    Rand rand_gen(\n    ^~~~\n%Error: data/full_repos/permissive/186443491/model/beforeExtend.v:101: syntax error, unexpected always\n    always @(posedge clock, negedge generateEn) begin\n    ^~~~~~\n%Error: Exiting due to 5 error(s)\n"
module Rand(
    input clock, resetn, enable,
    output reg [8 : 0] out
 );
    parameter SEED = 16'd163;
    parameter parA = 16'd43;
    parameter parB = 16'd181;
    wire[40: 0] temp;
    reg [5: 0] counter;
    assign temp = counter * out + parB;
    always @(posedge clock) begin
        if (!resetn) begin 
            out = SEED;
            counter = 1;
        end
        else if (enable) begin 
            out <= temp % 457;
            counter = counter + temp[5:2];
        end
    end
 endmodule
module Rand(
    input clock, resetn, enable,
    output reg [8 : 0] out
 );

    parameter SEED = 16'd163;
    parameter parA = 16'd43;
    parameter parB = 16'd181;
    wire[40: 0] temp;
    reg [5: 0] counter;
    assign temp = counter * out + parB;
    always @(posedge clock) begin
        if (!resetn) begin 
            out = SEED;
            counter = 1;
        end
        else if (enable) begin 
            out <= temp % 457;
            counter = counter + temp[5:2];
        end
    end
 endmodule