data/full_repos/permissive/143278/ivltests/pr1478121.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1478121.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q !== 2\'bzz) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1478121.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q !== 2\'b01) begin\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire [1:0] di;
   reg [1:0]  do;
   reg	      dir;

   wire [1:0] q;

   sub dut(.Q({q[0],q[1]}), .Di(di), .Do(do), .dir(dir));

   initial begin
      dir = 0;
      do = 2'b10;

      #1 if (q !== 2'bzz) begin
	 $display("FAILED -- q=%b, dir=%b", q, dir);
	 $finish;
      end

      dir = 1;

      #1 if (q !== 2'b01) begin
	 $display("FAILED -- q=%b, dir=%b, do=%b", q, dir, do);
	 $finish;
      end

      if (di !== 2'b10) begin
	 $display("FAILED -- di=%b, dir=%b, do=%b", di, dir, do);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   wire [1:0] di;
   reg [1:0]  do;
   reg	      dir;

   wire [1:0] q;

   sub dut(.Q({q[0],q[1]}), .Di(di), .Do(do), .dir(dir));

   initial begin
      dir = 0;
      do = 2'b10;

      #1 if (q !== 2'bzz) begin
	 $display("FAILED -- q=%b, dir=%b", q, dir);
	 $finish;
      end

      dir = 1;

      #1 if (q !== 2'b01) begin
	 $display("FAILED -- q=%b, dir=%b, do=%b", q, dir, do);
	 $finish;
      end

      if (di !== 2'b10) begin
	 $display("FAILED -- di=%b, dir=%b, do=%b", di, dir, do);
	 $finish;
      end

      $display("PASSED");
   end

endmodule