data/full_repos/permissive/114459345/srcCache/regfile.v
1: b'%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:11: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] waddr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegAddrBus] waddr,\n                       ^\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:12: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] wdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] ex_waddr,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:16: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] ex_waddr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:17: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] ex_wdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] mem_waddr,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:21: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] mem_waddr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:22: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_wdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] raddr1,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:26: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] raddr1,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:28: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] rdata1,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:28: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] rdata1,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] raddr2,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:32: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] raddr2,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] rdata2\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:34: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] rdata2\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:38: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] regs[0:`RegNum-1];\n     ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] regs[0:`RegNum-1];\n            ^\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:38: Define or directive not defined: \'`RegNum\'\n reg[`RegBus] regs[0:`RegNum-1];\n                     ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:41: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:49: Define or directive not defined: \'`RstDisable\'\n  if(rst == `RstDisable) begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:50: Define or directive not defined: \'`WriteEnable\'\n   if(we == `WriteEnable && (waddr != `RegNumLog2\'h0)) begin\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:50: Define or directive not defined: \'`RegNumLog2\'\n   if(we == `WriteEnable && (waddr != `RegNumLog2\'h0)) begin\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:58: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:59: Define or directive not defined: \'`ReadFailed\'\n   rsuc1 <= `ReadFailed;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:60: Define or directive not defined: \'`ZeroWord\'\n   rdata1 <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:62: Define or directive not defined: \'`RegNumLog2\'\n  else if(raddr1 == `RegNumLog2\'h0) begin\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:63: Define or directive not defined: \'`ReadSucceed\'\n   rsuc1 <= `ReadSucceed;\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:64: Define or directive not defined: \'`ZeroWord\'\n   rdata1 <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:66: Define or directive not defined: \'`ReadEnable\'\n  else if((raddr1 == ex_waddr) && (re1 == `ReadEnable)) begin\n                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:67: Define or directive not defined: \'`WriteEnable\'\n   if(ex_we == `WriteEnable) begin\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:68: Define or directive not defined: \'`ReadSucceed\'\n    rsuc1 <= `ReadSucceed;\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:72: Define or directive not defined: \'`ReadFailed\'\n    rsuc1 <= `ReadFailed;\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:73: Define or directive not defined: \'`ZeroWord\'\n    rdata1 <= `ZeroWord;    \n              ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:76: Define or directive not defined: \'`WriteEnable\'\n  else if((raddr1 == mem_waddr) && (mem_we == `WriteEnable) && (re1 == `ReadEnable)) begin\n                                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:76: Define or directive not defined: \'`ReadEnable\'\n  else if((raddr1 == mem_waddr) && (mem_we == `WriteEnable) && (re1 == `ReadEnable)) begin\n                                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:77: Define or directive not defined: \'`ReadSucceed\'\n   rsuc1 <= `ReadSucceed;\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:80: Define or directive not defined: \'`WriteEnable\'\n  else if((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `ReadEnable)) begin\n                                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:80: Define or directive not defined: \'`ReadEnable\'\n  else if((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `ReadEnable)) begin\n                                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:81: Define or directive not defined: \'`ReadSucceed\'\n   rsuc1 <= `ReadSucceed;\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:84: Define or directive not defined: \'`ReadEnable\'\n  else if(re1 == `ReadEnable) begin\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:85: Define or directive not defined: \'`ReadSucceed\'\n   rsuc1 <= `ReadSucceed;\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:89: Define or directive not defined: \'`ReadFailed\'\n   rsuc1 <= `ReadFailed;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:90: Define or directive not defined: \'`ZeroWord\'\n   rdata1 <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:96: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:97: Define or directive not defined: \'`ReadFailed\'\n   rsuc2 <= `ReadFailed;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:98: Define or directive not defined: \'`ZeroWord\'\n   rdata2 <= `ZeroWord;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:100: Define or directive not defined: \'`RegNumLog2\'\n  else if(raddr2 == `RegNumLog2\'h0) begin\n                    ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module regfile(

	input wire clk,
	input wire rst,
	

	input wire we,
	input wire[`RegAddrBus] waddr,
	input wire[`RegBus]	wdata,
	

	input wire ex_we,
	input wire[`RegAddrBus] ex_waddr,
	input wire[`RegBus] ex_wdata,
	

	input wire mem_we,
	input wire[`RegAddrBus] mem_waddr,
	input wire[`RegBus] mem_wdata,
	

	input wire re1,
	input wire[`RegAddrBus] raddr1,
	output reg rsuc1,
	output reg[`RegBus] rdata1,
	

	input wire re2,
	input wire[`RegAddrBus] raddr2,
	output reg rsuc2,
	output reg[`RegBus] rdata2
	
);
	
	reg[`RegBus] regs[0:`RegNum-1];

	integer i;
	initial begin
		for(i = 0; i < 32; i = i + 1)	begin
			regs[i] = 0;
		end
	end
	

	always @ (posedge clk) begin
		if(rst == `RstDisable) begin
			if(we == `WriteEnable && (waddr != `RegNumLog2'h0)) begin
				regs[waddr] <= wdata;
			end
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			rsuc1 <= `ReadFailed;
			rdata1 <= `ZeroWord;
		end
		else if(raddr1 == `RegNumLog2'h0) begin
			rsuc1 <= `ReadSucceed;
			rdata1 <= `ZeroWord;
		end
		else if((raddr1 == ex_waddr) && (re1 == `ReadEnable)) begin
			if(ex_we == `WriteEnable) begin
				rsuc1 <= `ReadSucceed;
				rdata1 <= ex_wdata;			
			end
			else begin
				rsuc1 <= `ReadFailed;
				rdata1 <= `ZeroWord;
			end
		end
		else if((raddr1 == mem_waddr) && (mem_we == `WriteEnable) && (re1 == `ReadEnable)) begin
			rsuc1 <= `ReadSucceed;
			rdata1 <= mem_wdata;
		end
		else if((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `ReadEnable)) begin
			rsuc1 <= `ReadSucceed;
			rdata1 <= wdata;
		end 
		else if(re1 == `ReadEnable) begin
			rsuc1 <= `ReadSucceed;
			rdata1 <= regs[raddr1];
		end
		else begin
			rsuc1 <= `ReadFailed;
			rdata1 <= `ZeroWord;
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			rsuc2 <= `ReadFailed;
			rdata2 <= `ZeroWord;
		end
		else if(raddr2 == `RegNumLog2'h0) begin
			rsuc2 <= `ReadSucceed;
			rdata2 <= `ZeroWord;
		end
		else if((raddr2 == ex_waddr) && (ex_we == `WriteEnable) && (re2 == `ReadEnable)) begin
			if(ex_we == `WriteEnable) begin
				rsuc2 <= `ReadSucceed;
				rdata2 <= ex_wdata;			
			end
			else begin
				rsuc2 <= `ReadFailed;
				rdata2 <= `ZeroWord;
			end
		end
		else if((raddr2 == mem_waddr) && (mem_we == `WriteEnable) && (re2 == `ReadEnable)) begin
			rsuc2 <= `ReadSucceed;
			rdata2 <= mem_wdata;
		end
		else if((raddr2 == waddr) && (we == `WriteEnable) && (re2 == `ReadEnable)) begin
			rsuc2 <= `ReadSucceed;
			rdata2 <= wdata;
		end 
		else if(re2 == `ReadEnable) begin
			rsuc2 <= `ReadSucceed;
			rdata2 <= regs[raddr2];
		end
		else begin
			rsuc2 <= `ReadFailed;
			rdata2 <= `ZeroWord;
		end
	end
	
endmodule
module regfile(

	input wire clk,
	input wire rst,
	

	input wire we,
	input wire[`RegAddrBus] waddr,
	input wire[`RegBus]	wdata,
	

	input wire ex_we,
	input wire[`RegAddrBus] ex_waddr,
	input wire[`RegBus] ex_wdata,
	

	input wire mem_we,
	input wire[`RegAddrBus] mem_waddr,
	input wire[`RegBus] mem_wdata,
	

	input wire re1,
	input wire[`RegAddrBus] raddr1,
	output reg rsuc1,
	output reg[`RegBus] rdata1,
	

	input wire re2,
	input wire[`RegAddrBus] raddr2,
	output reg rsuc2,
	output reg[`RegBus] rdata2
	
);

	
	reg[`RegBus] regs[0:`RegNum-1];

	integer i;
	initial begin
		for(i = 0; i < 32; i = i + 1)	begin
			regs[i] = 0;
		end
	end
	

	always @ (posedge clk) begin
		if(rst == `RstDisable) begin
			if(we == `WriteEnable && (waddr != `RegNumLog2'h0)) begin
				regs[waddr] <= wdata;
			end
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			rsuc1 <= `ReadFailed;
			rdata1 <= `ZeroWord;
		end
		else if(raddr1 == `RegNumLog2'h0) begin
			rsuc1 <= `ReadSucceed;
			rdata1 <= `ZeroWord;
		end
		else if((raddr1 == ex_waddr) && (re1 == `ReadEnable)) begin
			if(ex_we == `WriteEnable) begin
				rsuc1 <= `ReadSucceed;
				rdata1 <= ex_wdata;			
			end
			else begin
				rsuc1 <= `ReadFailed;
				rdata1 <= `ZeroWord;
			end
		end
		else if((raddr1 == mem_waddr) && (mem_we == `WriteEnable) && (re1 == `ReadEnable)) begin
			rsuc1 <= `ReadSucceed;
			rdata1 <= mem_wdata;
		end
		else if((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `ReadEnable)) begin
			rsuc1 <= `ReadSucceed;
			rdata1 <= wdata;
		end 
		else if(re1 == `ReadEnable) begin
			rsuc1 <= `ReadSucceed;
			rdata1 <= regs[raddr1];
		end
		else begin
			rsuc1 <= `ReadFailed;
			rdata1 <= `ZeroWord;
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			rsuc2 <= `ReadFailed;
			rdata2 <= `ZeroWord;
		end
		else if(raddr2 == `RegNumLog2'h0) begin
			rsuc2 <= `ReadSucceed;
			rdata2 <= `ZeroWord;
		end
		else if((raddr2 == ex_waddr) && (ex_we == `WriteEnable) && (re2 == `ReadEnable)) begin
			if(ex_we == `WriteEnable) begin
				rsuc2 <= `ReadSucceed;
				rdata2 <= ex_wdata;			
			end
			else begin
				rsuc2 <= `ReadFailed;
				rdata2 <= `ZeroWord;
			end
		end
		else if((raddr2 == mem_waddr) && (mem_we == `WriteEnable) && (re2 == `ReadEnable)) begin
			rsuc2 <= `ReadSucceed;
			rdata2 <= mem_wdata;
		end
		else if((raddr2 == waddr) && (we == `WriteEnable) && (re2 == `ReadEnable)) begin
			rsuc2 <= `ReadSucceed;
			rdata2 <= wdata;
		end 
		else if(re2 == `ReadEnable) begin
			rsuc2 <= `ReadSucceed;
			rdata2 <= regs[raddr2];
		end
		else begin
			rsuc2 <= `ReadFailed;
			rdata2 <= `ZeroWord;
		end
	end
	
endmodule