data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v
 line:63: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n always #15 rclk <= ~rclk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n always #5 wclk <= ~wclk;\n        ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:29: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("mm.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:30: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #2\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #60\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Error: Exiting due to 2 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifo15l_tb;
	
	reg	rclk		= 1;
	reg	wclk		= 1;
	
	reg	reset		= 0;
	reg	read		= 0;
	reg	write		= 0;
	
	reg	[17:0]	wr_data	= 0;
	wire	[17:0]	rd_data;
	
	wire	full;
	wire	not_empty;
	wire	one;
	
	always	#15	rclk	<= ~rclk;
	always	#5	wclk	<= ~wclk;
	
	
	initial begin : Sim


		$write ("%% ");
		$dumpfile ("mm.vcd");
		$dumpvars;
		
		#2
		reset	= 1;
		
		#10
		reset	= 0;
		
		#10
		write	= 1;
		wr_data	= 18'h30F0;
		
		#10
		read	= 1;
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= $random;
		
		#10
		wr_data	= $random;
		
		#10
		read	= 0;
		write	= 0;
		
		#30
		read	= 1;
		
		#60
		read	= 0;
		
		#100
		$finish;
	end
	
	

	fifo15l #('d18) FIFO0(
		.reset_i	(reset),
		
		.rd_clk_i	(rclk),
		.rd_en_i	(read),
		.rd_data_o	(rd_data),
		
		.wr_clk_i	(wclk),
		.wr_en_i	(write),
		.wr_data_i	(wr_data),
		
		.full_o		(full),
		.empty_no	(not_empty),
		.one_o		(one)
		

	);
	
	
endmodule
module fifo15l_tb;

	
	reg	rclk		= 1;
	reg	wclk		= 1;
	
	reg	reset		= 0;
	reg	read		= 0;
	reg	write		= 0;
	
	reg	[17:0]	wr_data	= 0;
	wire	[17:0]	rd_data;
	
	wire	full;
	wire	not_empty;
	wire	one;
	
	always	#15	rclk	<= ~rclk;
	always	#5	wclk	<= ~wclk;
	
	
	initial begin : Sim


		$write ("%% ");
		$dumpfile ("mm.vcd");
		$dumpvars;
		
		#2
		reset	= 1;
		
		#10
		reset	= 0;
		
		#10
		write	= 1;
		wr_data	= 18'h30F0;
		
		#10
		read	= 1;
		wr_data	= 18'h0A0A;
		
		#10
		wr_data	= $random;
		
		#10
		wr_data	= $random;
		
		#10
		read	= 0;
		write	= 0;
		
		#30
		read	= 1;
		
		#60
		read	= 0;
		
		#100
		$finish;
	end
	
	

	fifo15l #('d18) FIFO0(
		.reset_i	(reset),
		
		.rd_clk_i	(rclk),
		.rd_en_i	(read),
		.rd_data_o	(rd_data),
		
		.wr_clk_i	(wclk),
		.wr_en_i	(write),
		.wr_data_i	(wr_data),
		
		.full_o		(full),
		.empty_no	(not_empty),
		.one_o		(one)
		

	);
	
	
endmodule