data/full_repos/permissive/195330302/ScreamAtSnake/game_overlay.v
1: b'%Error: data/full_repos/permissive/195330302/ScreamAtSnake/game_overlay.v:97: Cannot find file containing module: \'random\'\n    random generator(\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/195330302/ScreamAtSnake,data/full_repos/permissive/195330302/random\n             data/full_repos/permissive/195330302/ScreamAtSnake,data/full_repos/permissive/195330302/random.v\n             data/full_repos/permissive/195330302/ScreamAtSnake,data/full_repos/permissive/195330302/random.sv\n             random\n             random.v\n             random.sv\n             obj_dir/random\n             obj_dir/random.v\n             obj_dir/random.sv\n%Warning-WIDTH: data/full_repos/permissive/195330302/ScreamAtSnake/game_overlay.v:63: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'500\'h0\' generates 500 bits.\n                                                                                    : ... In instance game_overlay.high_score_winner\n    wire clear = 500\'d0;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/195330302/ScreamAtSnake/game_overlay.v:84: Operator ASSIGN expects 500 bits on the Assign RHS, but Assign RHS\'s VARREF \'clear\' generates 1 bits.\n                                                                                    : ... In instance game_overlay.high_score_winner\n    OUT = clear;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/195330302/ScreamAtSnake/game_overlay.v:12: Operator ASSIGNW expects 200 bits on the Assign RHS, but Assign RHS\'s CONST \'300\'h0\' generates 300 bits.\n                                                                                    : ... In instance game_overlay\n    assign line_break = 300\'d0;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/195330302/ScreamAtSnake/game_overlay.v:32: Operator ASSIGNW expects 2700 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2300 bits.\n                                                                                    : ... In instance game_overlay\n    assign OUT = {high_score_winner_wire, line_break, motivation_text_wire, line_break, game_over_text_wire};\n               ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module high_score_winner_text(
    output reg [499:0] OUT,
    input is_high_score,
    input is_win,
    input clock
);

    wire clear = 500'd0;

    always@(*)
    begin
        if(is_win)
            begin
                OUT[99:0] 		= 100'b0000000000000000000000000000000000000111101111010011010011010100010000000000000000000000000000000000;
                OUT[199:100] 	= 100'b0000000000000000000000000000000000001000100001010101010101010100010000000000000000000000000000000000;
                OUT[299:200] 	= 100'b0000000000000000000000000000000000000111100011011001011001010101010000000000000000000000000000000000;
                OUT[399:300] 	= 100'b0000000000000000000000000000000000000100100001010001010001010110110000000000000000000000000000000000;
                OUT[499:400] 	= 100'b0000000000000000000000000000000000001000101111010001010001010100010000000000000000000000000000000000;
            end
        else if(is_high_score)
            begin
                OUT[99:0] 		= 100'b0000000000000000000000011110001111001111000111000111000010001011110001001000100000000000000000000000;
                OUT[199:100] 	= 100'b0000000000000000000000000010010001010000101000100000100010001000001001001000100000000000000000000000;
                OUT[299:200] 	= 100'b0000000000000000000000001110001001010000100000100011000011111010001001001111100000000000000000000000;
                OUT[399:300] 	= 100'b0000000000000000000000000010010001010000101000100100000010001010001001001000100000000000000000000000;
                OUT[499:400] 	= 100'b0000000000000000000000011110100001001111000111000111100010001001110001001000100000000000000000000000;
            end
			else
				OUT = clear;
    end
endmodule
module high_score_winner_text(
    output reg [499:0] OUT,
    input is_high_score,
    input is_win,
    input clock
);


    wire clear = 500'd0;

    always@(*)
    begin
        if(is_win)
            begin
                OUT[99:0] 		= 100'b0000000000000000000000000000000000000111101111010011010011010100010000000000000000000000000000000000;
                OUT[199:100] 	= 100'b0000000000000000000000000000000000001000100001010101010101010100010000000000000000000000000000000000;
                OUT[299:200] 	= 100'b0000000000000000000000000000000000000111100011011001011001010101010000000000000000000000000000000000;
                OUT[399:300] 	= 100'b0000000000000000000000000000000000000100100001010001010001010110110000000000000000000000000000000000;
                OUT[499:400] 	= 100'b0000000000000000000000000000000000001000101111010001010001010100010000000000000000000000000000000000;
            end
        else if(is_high_score)
            begin
                OUT[99:0] 		= 100'b0000000000000000000000011110001111001111000111000111000010001011110001001000100000000000000000000000;
                OUT[199:100] 	= 100'b0000000000000000000000000010010001010000101000100000100010001000001001001000100000000000000000000000;
                OUT[299:200] 	= 100'b0000000000000000000000001110001001010000100000100011000011111010001001001111100000000000000000000000;
                OUT[399:300] 	= 100'b0000000000000000000000000010010001010000101000100100000010001010001001001000100000000000000000000000;
                OUT[499:400] 	= 100'b0000000000000000000000011110100001001111000111000111100010001001110001001000100000000000000000000000;
            end
			else
				OUT = clear;
    end
endmodule