data/full_repos/permissive/152142712/v1/framegen.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/152142712/v1/framegen.v:80: Multiple top level modules\n                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                        : ... Top module \'framegen\'\nmodule framegen (\n       ^~~~~~~~\n                                                                        : ... Top module \'framebuffer\'\nmodule framebuffer (\n       ^~~~~~~~~~~\n                                                                        : ... Top module \'audiogen\'\nmodule audiogen (\n       ^~~~~~~~\n%Warning-UNSIGNED: data/full_repos/permissive/152142712/v1/framegen.v:47: Comparison is constant due to unsigned arithmetic\n                                                                        : ... In instance framegen\n      if (hc >= 9\'d0 && hc < 9\'d384 && vc >= 9\'d0 && vc < 9\'d288) begin   \n             ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152142712/v1/framegen.v:47: Comparison is constant due to unsigned arithmetic\n                                                                        : ... In instance framegen\n      if (hc >= 9\'d0 && hc < 9\'d384 && vc >= 9\'d0 && vc < 9\'d288) begin   \n                                          ^~\n%Error: Exiting due to 3 warning(s)\n'
module framegen (
  input wire clk7,
  input wire [8:0] hc,
  input wire [8:0] vc,
  output reg [13:0] ram_addr,
  input wire [7:0] din,
  output wire video_out
  );

  reg load_ramdata, load_shifter, incr_addr, reset_addr;
  reg [7:0] ramdata_din;
  always @* begin  
    load_ramdata = 1'b0;
    load_shifter = 1'b0;
    ramdata_din = 8'h00;
    incr_addr = 1'b0;
    reset_addr = 1'b0;
    
    if (hc[2:0] == 3'd2)
      load_shifter = 1'b1;
    if (hc[2:0] == 3'd0) begin
      load_ramdata = 1'b1;
      if (hc >= 9'd0 && hc < 9'd384 && vc >= 9'd0 && vc < 9'd288) begin
        ramdata_din = din;
        incr_addr = 1'b1;
      end
      else
        ramdata_din = 8'h00;
    end
    if (vc >= 9'd288)
      reset_addr = 1'b1;
  end

  reg [7:0] ramdata, shifter;
  initial ram_addr = 14'h0000;
  always @(posedge clk7) begin
      if (load_ramdata == 1'b1)
        ramdata <= ramdata_din;
        
      if (load_shifter == 1'b1)
        shifter <= ramdata;
      else
        shifter <= {shifter[6:0], 1'b0};
        
      if (reset_addr == 1'b1)
        ram_addr <= 14'h0000;
      else if (incr_addr == 1'b1)
        ram_addr <= ram_addr + 14'd1;
  end

  assign video_out = shifter[7];
endmodule
module framegen (
  input wire clk7,
  input wire [8:0] hc,
  input wire [8:0] vc,
  output reg [13:0] ram_addr,
  input wire [7:0] din,
  output wire video_out
  );


  reg load_ramdata, load_shifter, incr_addr, reset_addr;
  reg [7:0] ramdata_din;
  always @* begin  
    load_ramdata = 1'b0;
    load_shifter = 1'b0;
    ramdata_din = 8'h00;
    incr_addr = 1'b0;
    reset_addr = 1'b0;
    
    if (hc[2:0] == 3'd2)
      load_shifter = 1'b1;
    if (hc[2:0] == 3'd0) begin
      load_ramdata = 1'b1;
      if (hc >= 9'd0 && hc < 9'd384 && vc >= 9'd0 && vc < 9'd288) begin
        ramdata_din = din;
        incr_addr = 1'b1;
      end
      else
        ramdata_din = 8'h00;
    end
    if (vc >= 9'd288)
      reset_addr = 1'b1;
  end

  reg [7:0] ramdata, shifter;
  initial ram_addr = 14'h0000;
  always @(posedge clk7) begin
      if (load_ramdata == 1'b1)
        ramdata <= ramdata_din;
        
      if (load_shifter == 1'b1)
        shifter <= ramdata;
      else
        shifter <= {shifter[6:0], 1'b0};
        
      if (reset_addr == 1'b1)
        ram_addr <= 14'h0000;
      else if (incr_addr == 1'b1)
        ram_addr <= ram_addr + 14'd1;
  end

  assign video_out = shifter[7];
endmodule