data/full_repos/permissive/161029703/src/uma/InternalMemory/InternalMemory_stimulus.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/InternalMemory/InternalMemory_stimulus.v:7: Unsupported: Ignoring delay on this delayed statement.\n        #20 reset = 1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/InternalMemory/InternalMemory_stimulus.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #2 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/InternalMemory/InternalMemory_stimulus.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #21\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/InternalMemory/InternalMemory_stimulus.v:30: Unsupported: Ignoring delay on this delayed statement.\n            #4 \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/src/uma/InternalMemory/InternalMemory_stimulus.v:38: Unsupported: Ignoring delay on this delayed statement.\n            #4\n            ^\n%Error: data/full_repos/permissive/161029703/src/uma/InternalMemory/InternalMemory_stimulus.v:17: Cannot find file containing module: \'InternalMemory\'\n    InternalMemory memory(.clk(clk), .reset(reset), \n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161029703/src/uma/InternalMemory,data/full_repos/permissive/161029703/InternalMemory\n             data/full_repos/permissive/161029703/src/uma/InternalMemory,data/full_repos/permissive/161029703/InternalMemory.v\n             data/full_repos/permissive/161029703/src/uma/InternalMemory,data/full_repos/permissive/161029703/InternalMemory.sv\n             InternalMemory\n             InternalMemory.v\n             InternalMemory.sv\n             obj_dir/InternalMemory\n             obj_dir/InternalMemory.v\n             obj_dir/InternalMemory.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module InternalMemory_stimulus;
    reg clk, reset;
  
    initial begin
        clk = 1'b1;
        reset = 1'b1;
        #20 reset = 1'b0;
    end
    always
        #2 clk = ~clk;
    
    reg rreq, wreq;
    reg [31:0] addr;
    reg [31:0] wdata;
    wire [31:0] rdata;
    wire busy, ack;
    InternalMemory memory(.clk(clk), .reset(reset), 
                          .rreq(rreq), .wreq(wreq), .addr(addr), .wdata(rdata), 
                          .rdata(wdata), .busy(busy), .ack(ack));
    
    integer i;    
    initial begin
        rreq = 0;
        wreq = 0;
        #21
        wreq = 1;
        addr = 32'h0000;
        wdata = 32'h1234;
        for (i = 0; i < 50; i = i + 1) begin
            #4 
            addr = addr + 32'h1000;
            wdata = wdata + 32'h1;
        end
        wreq = 0;
        rreq = 1;
        addr = 32'h0000;
        for (i = 0; i < 50; i = i + 1) begin
            #4
            addr = addr + 32'h1000;
        end
        rreq = 0;
    end
endmodule
module InternalMemory_stimulus;

    reg clk, reset;
  
    initial begin
        clk = 1'b1;
        reset = 1'b1;
        #20 reset = 1'b0;
    end
    always
        #2 clk = ~clk;
    
    reg rreq, wreq;
    reg [31:0] addr;
    reg [31:0] wdata;
    wire [31:0] rdata;
    wire busy, ack;
    InternalMemory memory(.clk(clk), .reset(reset), 
                          .rreq(rreq), .wreq(wreq), .addr(addr), .wdata(rdata), 
                          .rdata(wdata), .busy(busy), .ack(ack));
    
    integer i;    
    initial begin
        rreq = 0;
        wreq = 0;
        #21
        wreq = 1;
        addr = 32'h0000;
        wdata = 32'h1234;
        for (i = 0; i < 50; i = i + 1) begin
            #4 
            addr = addr + 32'h1000;
            wdata = wdata + 32'h1;
        end
        wreq = 0;
        rreq = 1;
        addr = 32'h0000;
        for (i = 0; i < 50; i = i + 1) begin
            #4
            addr = addr + 32'h1000;
        end
        rreq = 0;
    end
endmodule