data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/RAM/xilinx_bram_tdp.v
1: b'%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/RAM/xilinx_bram_tdp.v:6: Operator VAR \'INIT_A\' expects 32 bits on the Initial value, but Initial value\'s CONST \'36\'h0\' generates 36 bits.\n                                                                                                                             : ... In instance xilix_bram_tdp\n    parameter integer INIT_A                = 36\'d0,          \n                      ^~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/RAM/xilinx_bram_tdp.v:7: Operator VAR \'INIT_B\' expects 32 bits on the Initial value, but Initial value\'s CONST \'36\'h0\' generates 36 bits.\n                                                                                                                             : ... In instance xilix_bram_tdp\n    parameter integer INIT_B                = 36\'d0,          \n                      ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/RAM/xilinx_bram_tdp.v:12: Operator VAR \'SRVAL_A\' expects 32 bits on the Initial value, but Initial value\'s CONST \'36\'h0\' generates 36 bits.\n                                                                                                                              : ... In instance xilix_bram_tdp\n    parameter integer SRVAL_A               = 36\'d0,          \n                      ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/RAM/xilinx_bram_tdp.v:13: Operator VAR \'SRVAL_B\' expects 32 bits on the Initial value, but Initial value\'s CONST \'36\'h0\' generates 36 bits.\n                                                                                                                              : ... In instance xilix_bram_tdp\n    parameter integer SRVAL_B               = 36\'d0,          \n                      ^~~~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/RAM/xilinx_bram_tdp.v:49: Cannot find file containing module: \'BRAM_TDP_MACRO\'\nBRAM_TDP_MACRO #(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/RAM,data/full_repos/permissive/150133337/BRAM_TDP_MACRO\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/RAM,data/full_repos/permissive/150133337/BRAM_TDP_MACRO.v\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/RAM,data/full_repos/permissive/150133337/BRAM_TDP_MACRO.sv\n             BRAM_TDP_MACRO\n             BRAM_TDP_MACRO.v\n             BRAM_TDP_MACRO.sv\n             obj_dir/BRAM_TDP_MACRO\n             obj_dir/BRAM_TDP_MACRO.v\n             obj_dir/BRAM_TDP_MACRO.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module xilix_bram_tdp
#(
    parameter         BRAM_SIZE             = "36Kb",
    parameter integer PORT_A_OUT_REG        = 1,
    parameter integer PORT_B_OUT_REG        = 1,
    parameter integer INIT_A                = 36'd0,
    parameter integer INIT_B                = 36'd0,
    parameter         INIT_FILE             = "NONE",                  
    parameter integer READ_WIDTH_A          = 16,
    parameter integer READ_WIDTH_B          = 16,
    parameter         SIM_COLLISION_CHK     = "ALL",
    parameter integer SRVAL_A               = 36'd0,
    parameter integer SRVAL_B               = 36'd0,
    parameter         WRITE_MODE_A          = "WRITE_FIRST",
    parameter         WRITE_MODE_B          = "WRITE_FIRST",
    parameter         WRITE_WIDTH_A         = 16,
    parameter         WRITE_WIDTH_B         = 16
)(
    output wire [ READ_WIDTH_A    -1 : 0 ]  DOA,
    output wire [ READ_WIDTH_B    -1 : 0 ]  DOB,
    input  wire [ ADDRA_WIDTH     -1 : 0 ]  ADDRA,
    input  wire [ ADDRB_WIDTH     -1 : 0 ]  ADDRB,
    input  wire                             CLKA,
    input  wire                             CLKB,
    input  wire [ WRITE_WIDTH_A   -1 : 0 ]  DIA,
    input  wire [ WRITE_WIDTH_B   -1 : 0 ]  DIB,
    input  wire                             ENA,
    input  wire                             ENB,
    input  wire                             REGCEA,
    input  wire                             REGCEB,
    input  wire                             RSTA,
    input  wire                             RSTB,
    input  wire [ WEA_WIDTH       -1 : 0 ]  WEA,
    input  wire [ WEB_WIDTH       -1 : 0 ]  WEB
);

localparam least_width_A =  (READ_WIDTH_A <= WRITE_WIDTH_A) ? READ_WIDTH_A : WRITE_WIDTH_A;
localparam least_width_B =  (READ_WIDTH_B <= WRITE_WIDTH_B) ? READ_WIDTH_B : WRITE_WIDTH_B;
localparam ADDRA_WIDTH   =  (BRAM_SIZE == "9Kb") ? ( (least_width_A == 1) ? 13 : (least_width_A == 2) ? 12 : (least_width_A > 2 && least_width_A <= 4) ? 11 : (least_width_A > 4 && least_width_A <= 9) ? 10 : (least_width_A > 9 && least_width_A <= 18) ? 9 : 13 ) : (BRAM_SIZE == "18Kb") ? ( (least_width_A == 1) ? 14 : (least_width_A == 2) ? 13 : (least_width_A > 2 && least_width_A <= 4) ? 12 : (least_width_A > 4 && least_width_A <= 9) ? 11 : (least_width_A > 9 && least_width_A <= 18) ? 10 : (least_width_A > 18 && least_width_A < 36) ? 9 : 14 ) : (BRAM_SIZE == "36Kb") ? ( (least_width_A == 1) ? 15 : (least_width_A == 2) ? 14 : (least_width_A > 2 && least_width_A <= 4) ? 13 : (least_width_A > 4 && least_width_A <= 9) ? 12 : (least_width_A > 9 && least_width_A <= 18) ? 11 : (least_width_A > 18 && least_width_A <= 36) ? 10 : 15 ) : 15;
localparam ADDRB_WIDTH   = (BRAM_SIZE == "9Kb") ? ( (least_width_B == 1) ? 13 : (least_width_B == 2) ? 12 : (least_width_B > 2 && least_width_B <= 4) ? 11 : (least_width_B > 4 && least_width_B <= 9) ? 10 : (least_width_B > 9 && least_width_B <= 18) ? 9 : 13 ) : (BRAM_SIZE == "18Kb") ? ( (least_width_B == 1) ? 14 : (least_width_B == 2) ? 13 : (least_width_B > 2 && least_width_B <= 4) ? 12 : (least_width_B > 4 && least_width_B <= 9) ? 11 : (least_width_B > 9 && least_width_B <= 18) ? 10 : (least_width_B > 18 && least_width_B <= 36 ) ? 9 : 14 ) : (BRAM_SIZE == "36Kb") ? ( (least_width_B == 1) ? 15 : (least_width_B == 2) ? 14 : (least_width_B > 2 && least_width_B <= 4) ? 13 : (least_width_B > 4 && least_width_B <= 9) ? 12 : (least_width_B > 9 && least_width_B <= 18) ? 11 : (least_width_B > 18 && least_width_B <= 36) ? 10 : 15 ) : 15;


localparam WEA_WIDTH = (WRITE_WIDTH_A <= 9) ? 1 : (WRITE_WIDTH_A > 9 && WRITE_WIDTH_A <= 18) ? 2 : (WRITE_WIDTH_A > 18 && WRITE_WIDTH_A <= 36) ? 4 : (BRAM_SIZE == "18Kb") ? 2 : 4;
localparam WEB_WIDTH = (WRITE_WIDTH_B <= 9) ? 1 : (WRITE_WIDTH_B > 9 && WRITE_WIDTH_B <= 18) ? 2 : (WRITE_WIDTH_B > 18 && WRITE_WIDTH_B <= 36) ? 4 : (BRAM_SIZE == "18Kb") ? 2 : 4;




BRAM_TDP_MACRO #(
    .BRAM_SIZE              ( BRAM_SIZE         ), 
    .DEVICE                 ( "7SERIES"         ), 
    .DOA_REG                ( PORT_A_OUT_REG    ), 
    .DOB_REG                ( PORT_B_OUT_REG    ), 
    .INIT_A                 ( INIT_A            ), 
    .INIT_B                 ( INIT_B            ), 
    .INIT_FILE              ( INIT_FILE         ),
    .READ_WIDTH_A           ( READ_WIDTH_A      ), 
    .READ_WIDTH_B           ( READ_WIDTH_B      ), 
    .SIM_COLLISION_CHECK    ( SIM_COLLISION_CHK ), 
    .SRVAL_A                ( SRVAL_A           ), 
    .SRVAL_B                ( SRVAL_B           ), 
    .WRITE_MODE_A           ( WRITE_MODE_A      ), 
    .WRITE_MODE_B           ( WRITE_MODE_B      ), 
    .WRITE_WIDTH_A          ( WRITE_WIDTH_A     ), 
    .WRITE_WIDTH_B          ( WRITE_WIDTH_B     )  
) BRAM_TDP_MACRO_inst (
    .DOA                    ( DOA               ), 
    .DOB                    ( DOB               ), 
    .ADDRA                  ( ADDRA             ), 
    .ADDRB                  ( ADDRB             ), 
    .CLKA                   ( CLKA              ), 
    .CLKB                   ( CLKB              ), 
    .DIA                    ( DIA               ), 
    .DIB                    ( DIB               ), 
    .ENA                    ( ENA               ), 
    .ENB                    ( ENB               ), 
    .REGCEA                 ( REGCEA            ), 
    .REGCEB                 ( REGCEB            ), 
    .RSTA                   ( RSTA              ), 
    .RSTB                   ( RSTB              ), 
    .WEA                    ( WEA               ), 
    .WEB                    ( WEB               )  
);

endmodule
module xilix_bram_tdp
#(
    parameter         BRAM_SIZE             = "36Kb",
    parameter integer PORT_A_OUT_REG        = 1,
    parameter integer PORT_B_OUT_REG        = 1,
    parameter integer INIT_A                = 36'd0,
    parameter integer INIT_B                = 36'd0,
    parameter         INIT_FILE             = "NONE",                  
    parameter integer READ_WIDTH_A          = 16,
    parameter integer READ_WIDTH_B          = 16,
    parameter         SIM_COLLISION_CHK     = "ALL",
    parameter integer SRVAL_A               = 36'd0,
    parameter integer SRVAL_B               = 36'd0,
    parameter         WRITE_MODE_A          = "WRITE_FIRST",
    parameter         WRITE_MODE_B          = "WRITE_FIRST",
    parameter         WRITE_WIDTH_A         = 16,
    parameter         WRITE_WIDTH_B         = 16
)(
    output wire [ READ_WIDTH_A    -1 : 0 ]  DOA,
    output wire [ READ_WIDTH_B    -1 : 0 ]  DOB,
    input  wire [ ADDRA_WIDTH     -1 : 0 ]  ADDRA,
    input  wire [ ADDRB_WIDTH     -1 : 0 ]  ADDRB,
    input  wire                             CLKA,
    input  wire                             CLKB,
    input  wire [ WRITE_WIDTH_A   -1 : 0 ]  DIA,
    input  wire [ WRITE_WIDTH_B   -1 : 0 ]  DIB,
    input  wire                             ENA,
    input  wire                             ENB,
    input  wire                             REGCEA,
    input  wire                             REGCEB,
    input  wire                             RSTA,
    input  wire                             RSTB,
    input  wire [ WEA_WIDTH       -1 : 0 ]  WEA,
    input  wire [ WEB_WIDTH       -1 : 0 ]  WEB
);


localparam least_width_A =  (READ_WIDTH_A <= WRITE_WIDTH_A) ? READ_WIDTH_A : WRITE_WIDTH_A;
localparam least_width_B =  (READ_WIDTH_B <= WRITE_WIDTH_B) ? READ_WIDTH_B : WRITE_WIDTH_B;
localparam ADDRA_WIDTH   =  (BRAM_SIZE == "9Kb") ? ( (least_width_A == 1) ? 13 : (least_width_A == 2) ? 12 : (least_width_A > 2 && least_width_A <= 4) ? 11 : (least_width_A > 4 && least_width_A <= 9) ? 10 : (least_width_A > 9 && least_width_A <= 18) ? 9 : 13 ) : (BRAM_SIZE == "18Kb") ? ( (least_width_A == 1) ? 14 : (least_width_A == 2) ? 13 : (least_width_A > 2 && least_width_A <= 4) ? 12 : (least_width_A > 4 && least_width_A <= 9) ? 11 : (least_width_A > 9 && least_width_A <= 18) ? 10 : (least_width_A > 18 && least_width_A < 36) ? 9 : 14 ) : (BRAM_SIZE == "36Kb") ? ( (least_width_A == 1) ? 15 : (least_width_A == 2) ? 14 : (least_width_A > 2 && least_width_A <= 4) ? 13 : (least_width_A > 4 && least_width_A <= 9) ? 12 : (least_width_A > 9 && least_width_A <= 18) ? 11 : (least_width_A > 18 && least_width_A <= 36) ? 10 : 15 ) : 15;
localparam ADDRB_WIDTH   = (BRAM_SIZE == "9Kb") ? ( (least_width_B == 1) ? 13 : (least_width_B == 2) ? 12 : (least_width_B > 2 && least_width_B <= 4) ? 11 : (least_width_B > 4 && least_width_B <= 9) ? 10 : (least_width_B > 9 && least_width_B <= 18) ? 9 : 13 ) : (BRAM_SIZE == "18Kb") ? ( (least_width_B == 1) ? 14 : (least_width_B == 2) ? 13 : (least_width_B > 2 && least_width_B <= 4) ? 12 : (least_width_B > 4 && least_width_B <= 9) ? 11 : (least_width_B > 9 && least_width_B <= 18) ? 10 : (least_width_B > 18 && least_width_B <= 36 ) ? 9 : 14 ) : (BRAM_SIZE == "36Kb") ? ( (least_width_B == 1) ? 15 : (least_width_B == 2) ? 14 : (least_width_B > 2 && least_width_B <= 4) ? 13 : (least_width_B > 4 && least_width_B <= 9) ? 12 : (least_width_B > 9 && least_width_B <= 18) ? 11 : (least_width_B > 18 && least_width_B <= 36) ? 10 : 15 ) : 15;


localparam WEA_WIDTH = (WRITE_WIDTH_A <= 9) ? 1 : (WRITE_WIDTH_A > 9 && WRITE_WIDTH_A <= 18) ? 2 : (WRITE_WIDTH_A > 18 && WRITE_WIDTH_A <= 36) ? 4 : (BRAM_SIZE == "18Kb") ? 2 : 4;
localparam WEB_WIDTH = (WRITE_WIDTH_B <= 9) ? 1 : (WRITE_WIDTH_B > 9 && WRITE_WIDTH_B <= 18) ? 2 : (WRITE_WIDTH_B > 18 && WRITE_WIDTH_B <= 36) ? 4 : (BRAM_SIZE == "18Kb") ? 2 : 4;




BRAM_TDP_MACRO #(
    .BRAM_SIZE              ( BRAM_SIZE         ), 
    .DEVICE                 ( "7SERIES"         ), 
    .DOA_REG                ( PORT_A_OUT_REG    ), 
    .DOB_REG                ( PORT_B_OUT_REG    ), 
    .INIT_A                 ( INIT_A            ), 
    .INIT_B                 ( INIT_B            ), 
    .INIT_FILE              ( INIT_FILE         ),
    .READ_WIDTH_A           ( READ_WIDTH_A      ), 
    .READ_WIDTH_B           ( READ_WIDTH_B      ), 
    .SIM_COLLISION_CHECK    ( SIM_COLLISION_CHK ), 
    .SRVAL_A                ( SRVAL_A           ), 
    .SRVAL_B                ( SRVAL_B           ), 
    .WRITE_MODE_A           ( WRITE_MODE_A      ), 
    .WRITE_MODE_B           ( WRITE_MODE_B      ), 
    .WRITE_WIDTH_A          ( WRITE_WIDTH_A     ), 
    .WRITE_WIDTH_B          ( WRITE_WIDTH_B     )  
) BRAM_TDP_MACRO_inst (
    .DOA                    ( DOA               ), 
    .DOB                    ( DOB               ), 
    .ADDRA                  ( ADDRA             ), 
    .ADDRB                  ( ADDRB             ), 
    .CLKA                   ( CLKA              ), 
    .CLKB                   ( CLKB              ), 
    .DIA                    ( DIA               ), 
    .DIB                    ( DIB               ), 
    .ENA                    ( ENA               ), 
    .ENB                    ( ENB               ), 
    .REGCEA                 ( REGCEA            ), 
    .REGCEB                 ( REGCEB            ), 
    .RSTA                   ( RSTA              ), 
    .RSTB                   ( RSTB              ), 
    .WEA                    ( WEA               ), 
    .WEB                    ( WEB               )  
);

endmodule