data/full_repos/permissive/190698744/7 - Sequential Logic/1 - Latches & Flipflops/10 - DFF+gate (XOR).v
1: b'%Error: Invalid Option: -\n'
module top_module (
    input clk,
    input in, 
    output out);
	
    always @ (posedge clk) begin
    	out <= out ^ in;
    end
endmodule
module top_module (
    input clk,
    input in, 
    output out);

	
    always @ (posedge clk) begin
    	out <= out ^ in;
    end
endmodule