data/full_repos/permissive/212495825/src/roms.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/212495825/src/roms.v:52: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'MAIN_ROM\'\nmodule MAIN_ROM\n       ^~~~~~~~\n                                                                     : ... Top module \'SUB_ROM\'\nmodule SUB_ROM\n       ^~~~~~~\n                                                                     : ... Top module \'BGCH_ROM\'\nmodule BGCH_ROM\n       ^~~~~~~~\n                                                                     : ... Top module \'SPCH_ROM\'\nmodule SPCH_ROM\n       ^~~~~~~~\n                                                                     : ... Top module \'CLUT1_ROM\'\nmodule CLUT1_ROM\n       ^~~~~~~~~\n                                                                     : ... Top module \'PALET_ROM\'\nmodule PALET_ROM\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/roms.v:20: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                  : ... In instance MAIN_ROM.mrom0\nalways @(posedge CL0) DO0 <= core[AD0];\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/roms.v:21: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'DI1\' generates 8 bits.\n                                                                  : ... In instance MAIN_ROM.mrom0\nalways @(posedge CL1) if (WE1) core[AD1] <= DI1;\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/roms.v:20: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 5 bits.\n                                                                  : ... In instance CLUT1_ROM.clut1l\nalways @(posedge CL0) DO0 <= core[AD0];\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/roms.v:21: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DI1\' generates 4 bits.\n                                                                  : ... In instance CLUT1_ROM.clut1l\nalways @(posedge CL1) if (WE1) core[AD1] <= DI1;\n                                         ^~\n%Error: Exiting due to 5 warning(s)\n'
module CLUT1_ROM
(
	input				clk,
	input   [8:0]	adr,
	output  [7:0] 	data,

	input				ROMCL,
	input	 [17:0]	ROMAD,
	input	  [7:0]	ROMDT,
	input				ROMEN
);

DLROM #(9,4) clut1l( clk, adr, data[3:0], ROMCL,ROMAD[8:0],ROMDT[3:0],ROMEN & (ROMAD[17:9]==9'b10_0000_000) );
DLROM #(9,4) clut1h( clk, adr, data[7:4], ROMCL,ROMAD[8:0],ROMDT[3:0],ROMEN & (ROMAD[17:9]==9'b10_0000_001) );

endmodule
module CLUT1_ROM
(
	input				clk,
	input   [8:0]	adr,
	output  [7:0] 	data,

	input				ROMCL,
	input	 [17:0]	ROMAD,
	input	  [7:0]	ROMDT,
	input				ROMEN
);


DLROM #(9,4) clut1l( clk, adr, data[3:0], ROMCL,ROMAD[8:0],ROMDT[3:0],ROMEN & (ROMAD[17:9]==9'b10_0000_000) );
DLROM #(9,4) clut1h( clk, adr, data[7:4], ROMCL,ROMAD[8:0],ROMDT[3:0],ROMEN & (ROMAD[17:9]==9'b10_0000_001) );

endmodule