data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Alu.v
data/verilator_xmls/cbc50465-4b48-4ac7-94df-81592fe57fd7.xml
module Alu(
input [31:0]src_a,
input [31:0]src_b,
input [3:0]alu_op,
input [4:0]shmat,
output reg eq,
output reg [31:0]result1,
output reg [31:0]result2
    );
reg [63:0]mul_tmp;
    initial
    begin
        eq = 0;
        result1 <= 32'h00000;
        result2 <= 32'h00000; 
    end
    always@(src_a or src_b or alu_op or shmat)
    begin
        if(src_a==src_b)
            eq = 1;
        else 
            eq = 0;
        case(alu_op)
            4'b0000:
            begin
                result1 <= src_b<<shmat;
                result2 <= 0;
            end
            4'b0001:
            begin
                result1 <= ($signed(src_b))>>>shmat;
                result2 <= 0;
            end
            4'b0010:
            begin
                result1 <= src_b>>shmat; 
                result2 <= 0;           
            end
            4'b0011:
            begin
                mul_tmp = src_a*src_b;
                result1 <= mul_tmp[31:0];
                result2 <= mul_tmp[63:32];          
            end
            4'b0100:
            begin
                result1 <= src_a / src_b; 
                result2 <= src_a % src_b;         
            end 
            4'b0101:
            begin
                result1 <= src_a + src_b;
                result2 <= 0;            
            end 
            4'b0110:
            begin
                result1 <= src_a - src_b;
                result2 <= 0;            
            end  
            4'b0111:
            begin
                result1 <= src_a & src_b;
                result2 <= 0;    
            end 
            4'b1000:
            begin
                result1 <= src_a | src_b;
                result2 <= 0;            
            end
            4'b1001:
            begin
                result1 <= src_a ^ src_b;
                result2 <= 0;           
            end
            4'b1010:
            begin
                result1 <= ~(src_a | src_b);
                result2 <= 0;            
            end
            4'b1011:
            begin
                if(src_a[15:15]^src_b[15:15])
                    result1 <= (src_a < src_b) ? 0 : 1;
                else
                    result1 <= (src_a < src_b) ? 1 : 0;    
                result2 <= 0;           
            end
            4'b1100:
            begin
                result1 <= (src_a < src_b) ? 1 : 0; 
                result2 <= 0;             
            end          
            default:
            begin
                result1 <= 0;
                result2 <= 0;
            end
        endcase
    end
endmodule
module Alu(
input [31:0]src_a,
input [31:0]src_b,
input [3:0]alu_op,
input [4:0]shmat,
output reg eq,
output reg [31:0]result1,
output reg [31:0]result2
    );

reg [63:0]mul_tmp;
    initial
    begin
        eq = 0;
        result1 <= 32'h00000;
        result2 <= 32'h00000; 
    end
    always@(src_a or src_b or alu_op or shmat)
    begin
        if(src_a==src_b)
            eq = 1;
        else 
            eq = 0;
        case(alu_op)
            4'b0000:
            begin
                result1 <= src_b<<shmat;
                result2 <= 0;
            end
            4'b0001:
            begin
                result1 <= ($signed(src_b))>>>shmat;
                result2 <= 0;
            end
            4'b0010:
            begin
                result1 <= src_b>>shmat; 
                result2 <= 0;           
            end
            4'b0011:
            begin
                mul_tmp = src_a*src_b;
                result1 <= mul_tmp[31:0];
                result2 <= mul_tmp[63:32];          
            end
            4'b0100:
            begin
                result1 <= src_a / src_b; 
                result2 <= src_a % src_b;         
            end 
            4'b0101:
            begin
                result1 <= src_a + src_b;
                result2 <= 0;            
            end 
            4'b0110:
            begin
                result1 <= src_a - src_b;
                result2 <= 0;            
            end  
            4'b0111:
            begin
                result1 <= src_a & src_b;
                result2 <= 0;    
            end 
            4'b1000:
            begin
                result1 <= src_a | src_b;
                result2 <= 0;            
            end
            4'b1001:
            begin
                result1 <= src_a ^ src_b;
                result2 <= 0;           
            end
            4'b1010:
            begin
                result1 <= ~(src_a | src_b);
                result2 <= 0;            
            end
            4'b1011:
            begin
                if(src_a[15:15]^src_b[15:15])
                    result1 <= (src_a < src_b) ? 0 : 1;
                else
                    result1 <= (src_a < src_b) ? 1 : 0;    
                result2 <= 0;           
            end
            4'b1100:
            begin
                result1 <= (src_a < src_b) ? 1 : 0; 
                result2 <= 0;             
            end          
            default:
            begin
                result1 <= 0;
                result2 <= 0;
            end
        endcase
    end
endmodule