data/full_repos/permissive/104784866/NovaCORE/Verilog/src/NovaCORE.v
1: b"%Error: data/full_repos/permissive/104784866/NovaCORE/Verilog/src/NovaCORE.v:142: Cannot find file containing module: 'CBox'\n    CBox#(((CLB_WIDTH << 1) * i) + j, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), LUT_WIDTH+1, 1, LUT_WIDTH_WIDTH+1, UID_WIDTH, DIMENSION_WIDTH) cboxInst(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/104784866/NovaCORE/Verilog/src,data/full_repos/permissive/104784866/CBox\n             data/full_repos/permissive/104784866/NovaCORE/Verilog/src,data/full_repos/permissive/104784866/CBox.v\n             data/full_repos/permissive/104784866/NovaCORE/Verilog/src,data/full_repos/permissive/104784866/CBox.sv\n             CBox\n             CBox.v\n             CBox.sv\n             obj_dir/CBox\n             obj_dir/CBox.v\n             obj_dir/CBox.sv\n%Error: data/full_repos/permissive/104784866/NovaCORE/Verilog/src/NovaCORE.v:158: Cannot find file containing module: 'SBox'\n    SBox#(((CLB_WIDTH << 1) * i) + j + 1, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), UID_WIDTH, DIMENSION_WIDTH, CH_WIDTH_WIDTH) sboxInst(\n    ^~~~\n%Error: data/full_repos/permissive/104784866/NovaCORE/Verilog/src/NovaCORE.v:176: Cannot find file containing module: 'CLB'\n    CLB#(((CLB_WIDTH << 1) * (i + 1)) + j, DIMENSION, UID_WIDTH, LUT_WIDTH, DIMENSION_WIDTH) clbInst(\n    ^~~\n%Error: data/full_repos/permissive/104784866/NovaCORE/Verilog/src/NovaCORE.v:190: Cannot find file containing module: 'CBox'\n    CBox#(((CLB_WIDTH << 1) * (i + 1)) + j + 1, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), 1, 1, 1, UID_WIDTH, DIMENSION_WIDTH) cboxInst2(\n    ^~~~\n%Error: Exiting due to 4 error(s)\n"
module NovaCORE#(

		parameter DIMENSION = 4,

		parameter CLB_WIDTH = 16,

		parameter CH_WIDTH = 4,

		parameter LUT_WIDTH = 2,

		parameter DIMENSION_WIDTH = 2,

		parameter CH_WIDTH_WIDTH = 2,

		parameter LUT_WIDTH_WIDTH = 1,

		parameter UID_WIDTH = 16
	) (

		clk,


		mode,
		c_clk,
		c_bus,
		c_uid,
		c_dimension,
		c_dimswitch,


		io_up_n,
		io_up_s,
		io_dn_n,
		io_dn_s,
		io_lt_n,
		io_lt_s,
		io_rt_n,
		io_rt_s
	);


	parameter CONFIG_WORD_WIDTH = (`CLB_CONFIG_WORD_WIDTH > `CBOX_CONFIG_WORD_WIDTH)?
									(`CLB_CONFIG_WORD_WIDTH > `SBOX_CONFIG_WORD_WIDTH)?
										`CLB_CONFIG_WORD_WIDTH
										:
										`SBOX_CONFIG_WORD_WIDTH
									:
									(`CBOX_CONFIG_WORD_WIDTH > `SBOX_CONFIG_WORD_WIDTH)?
										`CBOX_CONFIG_WORD_WIDTH
										:
										`SBOX_CONFIG_WORD_WIDTH;


	input clk;


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [UID_WIDTH-1:0] c_uid;
	input [DIMENSION_WIDTH-1:0] c_dimension;
	input c_dimswitch;


	output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_up_n;
	input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_up_s;
	input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_dn_n;
	output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_dn_s;
	output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_lt_n;
	input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_lt_s;
	input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_rt_n;
	output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_rt_s;


	generate

		if(DIMENSION != 1) begin : configRegGen
			reg [DIMENSION_WIDTH-1:0] configReg;


			always @(posedge c_dimswitch) begin
				if(mode) begin
					`CONFIGREG_DIMENSION = c_dimension;
				end
			end
		end

		else begin : configRegGen
			wire configReg;
			assign configReg = 'b0;
		end
	endgenerate


	wire [(CH_WIDTH>>1)-1:0] vUpChannels [0:(CLB_WIDTH<<2)][0:CLB_WIDTH-1];
	wire [(CH_WIDTH>>1)-1:0] vDnChannels [0:(CLB_WIDTH<<2)][0:CLB_WIDTH-1];
	wire [(CH_WIDTH>>1)-1:0] hLtChannels [0:CLB_WIDTH-1][0:(CLB_WIDTH<<2)];
	wire [(CH_WIDTH>>1)-1:0] hRtChannels [0:CLB_WIDTH-1][0:(CLB_WIDTH<<2)];


	wire [LUT_WIDTH:0] vCLBIn [0:CLB_WIDTH-1][0:CLB_WIDTH-1];
	wire hCLBOut [0:CLB_WIDTH-1][0:CLB_WIDTH-1];


	genvar i, j;
	generate
		for(i = 0; i < (CLB_WIDTH << 1); i = i+2) begin : ArrayGen
			for(j = 0; j < (CLB_WIDTH << 1); j = j+2) begin : CBoxGen

				CBox#(((CLB_WIDTH << 1) * i) + j, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), LUT_WIDTH+1, 1, LUT_WIDTH_WIDTH+1, UID_WIDTH, DIMENSION_WIDTH) cboxInst(
					.mode(mode),
					.c_clk(c_clk),
					.c_bus(c_bus[`CBOX_CONFIG_WORD_WIDTH-1:0]),
					.c_uid(c_uid),
					.c_dimension(`CONFIGREG_DIMENSION),

					.ch_up_n(hLtChannels[i>>1][j]),
					.ch_up_s(hLtChannels[i>>1][j+1]),
					.ch_dn_n(hRtChannels[i>>1][j]),
					.ch_dn_s(hRtChannels[i>>1][j+1]),

					.clb_in(vCLBIn[(i >> 1)][(j >> 1)]),
					.clb_out()
				);

				SBox#(((CLB_WIDTH << 1) * i) + j + 1, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), UID_WIDTH, DIMENSION_WIDTH, CH_WIDTH_WIDTH) sboxInst(
					.mode(mode),
					.c_clk(c_clk),
					.c_bus(c_bus[`SBOX_CONFIG_WORD_WIDTH-1:0]),
					.c_uid(c_uid),
					.c_dimension(`CONFIGREG_DIMENSION),

					.ch_up_n(vUpChannels[i][j>>1]),
					.ch_up_s(vUpChannels[i+1][j>>1]),
					.ch_dn_n(vDnChannels[i][j>>1]),
					.ch_dn_s(vDnChannels[i+1][j>>1]),

					.ch_lt_n(hLtChannels[i>>1][j+1]),
					.ch_lt_s(hLtChannels[i>>1][j+2]),
					.ch_rt_n(hRtChannels[i>>1][j+1]),
					.ch_rt_s(hRtChannels[i>>1][j+2])
				);

				CLB#(((CLB_WIDTH << 1) * (i + 1)) + j, DIMENSION, UID_WIDTH, LUT_WIDTH, DIMENSION_WIDTH) clbInst(
					.clk(clk),
					.clk_en(vCLBIn[(i >> 1)][(j >> 1)][2]),

					.mode(mode),
					.c_clk(c_clk),
					.c_bus(c_bus[`CLB_CONFIG_WORD_WIDTH-1:0]),
					.c_uid(c_uid),
					.c_dimension(`CONFIGREG_DIMENSION),

					.b_in(vCLBIn[(i >> 1)][(j >> 1)][1:0]),
					.b_out(hCLBOut[(i >> 1)][(j >> 1)])
				);

				CBox#(((CLB_WIDTH << 1) * (i + 1)) + j + 1, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), 1, 1, 1, UID_WIDTH, DIMENSION_WIDTH) cboxInst2(
					.mode(mode),
					.c_clk(c_clk),
					.c_bus(c_bus[`CBOX2_CONFIG_WORD_WIDTH-1:0]),
					.c_uid(c_uid),
					.c_dimension(`CONFIGREG_DIMENSION),

					.ch_up_n(vUpChannels[i+1][j>>1]),
					.ch_up_s(vUpChannels[i+2][j>>1]),
					.ch_dn_n(vDnChannels[i+1][j>>1]),
					.ch_dn_s(vDnChannels[i+2][j>>1]),

					.clb_in(),
					.clb_out(hCLBOut[(i >> 1)][(j >> 1)])
				);
			end
		end

		for(i = 0; i < CLB_WIDTH; i = i+1) begin : IOGen
			assign io_up_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = vUpChannels[0][CLB_WIDTH-i-1];
			assign vUpChannels[(CLB_WIDTH<<1)][CLB_WIDTH-i-1] = io_up_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
			assign vDnChannels[0][CLB_WIDTH-i-1] = io_dn_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
			assign io_dn_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = vDnChannels[(CLB_WIDTH<<1)][CLB_WIDTH-i-1];
			assign io_lt_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = hLtChannels[i][0];
			assign hLtChannels[i][(CLB_WIDTH<<1)] = io_lt_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
			assign hRtChannels[i][0] = io_rt_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
			assign io_rt_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = hRtChannels[i][(CLB_WIDTH<<1)];
		end
	endgenerate

endmodule
module NovaCORE#(

		parameter DIMENSION = 4,

		parameter CLB_WIDTH = 16,

		parameter CH_WIDTH = 4,

		parameter LUT_WIDTH = 2,

		parameter DIMENSION_WIDTH = 2,

		parameter CH_WIDTH_WIDTH = 2,

		parameter LUT_WIDTH_WIDTH = 1,

		parameter UID_WIDTH = 16
	) (

		clk,


		mode,
		c_clk,
		c_bus,
		c_uid,
		c_dimension,
		c_dimswitch,


		io_up_n,
		io_up_s,
		io_dn_n,
		io_dn_s,
		io_lt_n,
		io_lt_s,
		io_rt_n,
		io_rt_s
	);



	parameter CONFIG_WORD_WIDTH = (`CLB_CONFIG_WORD_WIDTH > `CBOX_CONFIG_WORD_WIDTH)?
									(`CLB_CONFIG_WORD_WIDTH > `SBOX_CONFIG_WORD_WIDTH)?
										`CLB_CONFIG_WORD_WIDTH
										:
										`SBOX_CONFIG_WORD_WIDTH
									:
									(`CBOX_CONFIG_WORD_WIDTH > `SBOX_CONFIG_WORD_WIDTH)?
										`CBOX_CONFIG_WORD_WIDTH
										:
										`SBOX_CONFIG_WORD_WIDTH;


	input clk;


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [UID_WIDTH-1:0] c_uid;
	input [DIMENSION_WIDTH-1:0] c_dimension;
	input c_dimswitch;


	output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_up_n;
	input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_up_s;
	input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_dn_n;
	output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_dn_s;
	output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_lt_n;
	input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_lt_s;
	input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_rt_n;
	output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_rt_s;


	generate

		if(DIMENSION != 1) begin : configRegGen
			reg [DIMENSION_WIDTH-1:0] configReg;


			always @(posedge c_dimswitch) begin
				if(mode) begin
					`CONFIGREG_DIMENSION = c_dimension;
				end
			end
		end

		else begin : configRegGen
			wire configReg;
			assign configReg = 'b0;
		end
	endgenerate


	wire [(CH_WIDTH>>1)-1:0] vUpChannels [0:(CLB_WIDTH<<2)][0:CLB_WIDTH-1];
	wire [(CH_WIDTH>>1)-1:0] vDnChannels [0:(CLB_WIDTH<<2)][0:CLB_WIDTH-1];
	wire [(CH_WIDTH>>1)-1:0] hLtChannels [0:CLB_WIDTH-1][0:(CLB_WIDTH<<2)];
	wire [(CH_WIDTH>>1)-1:0] hRtChannels [0:CLB_WIDTH-1][0:(CLB_WIDTH<<2)];


	wire [LUT_WIDTH:0] vCLBIn [0:CLB_WIDTH-1][0:CLB_WIDTH-1];
	wire hCLBOut [0:CLB_WIDTH-1][0:CLB_WIDTH-1];


	genvar i, j;
	generate
		for(i = 0; i < (CLB_WIDTH << 1); i = i+2) begin : ArrayGen
			for(j = 0; j < (CLB_WIDTH << 1); j = j+2) begin : CBoxGen

				CBox#(((CLB_WIDTH << 1) * i) + j, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), LUT_WIDTH+1, 1, LUT_WIDTH_WIDTH+1, UID_WIDTH, DIMENSION_WIDTH) cboxInst(
					.mode(mode),
					.c_clk(c_clk),
					.c_bus(c_bus[`CBOX_CONFIG_WORD_WIDTH-1:0]),
					.c_uid(c_uid),
					.c_dimension(`CONFIGREG_DIMENSION),

					.ch_up_n(hLtChannels[i>>1][j]),
					.ch_up_s(hLtChannels[i>>1][j+1]),
					.ch_dn_n(hRtChannels[i>>1][j]),
					.ch_dn_s(hRtChannels[i>>1][j+1]),

					.clb_in(vCLBIn[(i >> 1)][(j >> 1)]),
					.clb_out()
				);

				SBox#(((CLB_WIDTH << 1) * i) + j + 1, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), UID_WIDTH, DIMENSION_WIDTH, CH_WIDTH_WIDTH) sboxInst(
					.mode(mode),
					.c_clk(c_clk),
					.c_bus(c_bus[`SBOX_CONFIG_WORD_WIDTH-1:0]),
					.c_uid(c_uid),
					.c_dimension(`CONFIGREG_DIMENSION),

					.ch_up_n(vUpChannels[i][j>>1]),
					.ch_up_s(vUpChannels[i+1][j>>1]),
					.ch_dn_n(vDnChannels[i][j>>1]),
					.ch_dn_s(vDnChannels[i+1][j>>1]),

					.ch_lt_n(hLtChannels[i>>1][j+1]),
					.ch_lt_s(hLtChannels[i>>1][j+2]),
					.ch_rt_n(hRtChannels[i>>1][j+1]),
					.ch_rt_s(hRtChannels[i>>1][j+2])
				);

				CLB#(((CLB_WIDTH << 1) * (i + 1)) + j, DIMENSION, UID_WIDTH, LUT_WIDTH, DIMENSION_WIDTH) clbInst(
					.clk(clk),
					.clk_en(vCLBIn[(i >> 1)][(j >> 1)][2]),

					.mode(mode),
					.c_clk(c_clk),
					.c_bus(c_bus[`CLB_CONFIG_WORD_WIDTH-1:0]),
					.c_uid(c_uid),
					.c_dimension(`CONFIGREG_DIMENSION),

					.b_in(vCLBIn[(i >> 1)][(j >> 1)][1:0]),
					.b_out(hCLBOut[(i >> 1)][(j >> 1)])
				);

				CBox#(((CLB_WIDTH << 1) * (i + 1)) + j + 1, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), 1, 1, 1, UID_WIDTH, DIMENSION_WIDTH) cboxInst2(
					.mode(mode),
					.c_clk(c_clk),
					.c_bus(c_bus[`CBOX2_CONFIG_WORD_WIDTH-1:0]),
					.c_uid(c_uid),
					.c_dimension(`CONFIGREG_DIMENSION),

					.ch_up_n(vUpChannels[i+1][j>>1]),
					.ch_up_s(vUpChannels[i+2][j>>1]),
					.ch_dn_n(vDnChannels[i+1][j>>1]),
					.ch_dn_s(vDnChannels[i+2][j>>1]),

					.clb_in(),
					.clb_out(hCLBOut[(i >> 1)][(j >> 1)])
				);
			end
		end

		for(i = 0; i < CLB_WIDTH; i = i+1) begin : IOGen
			assign io_up_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = vUpChannels[0][CLB_WIDTH-i-1];
			assign vUpChannels[(CLB_WIDTH<<1)][CLB_WIDTH-i-1] = io_up_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
			assign vDnChannels[0][CLB_WIDTH-i-1] = io_dn_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
			assign io_dn_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = vDnChannels[(CLB_WIDTH<<1)][CLB_WIDTH-i-1];
			assign io_lt_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = hLtChannels[i][0];
			assign hLtChannels[i][(CLB_WIDTH<<1)] = io_lt_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
			assign hRtChannels[i][0] = io_rt_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
			assign io_rt_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = hRtChannels[i][(CLB_WIDTH<<1)];
		end
	endgenerate

endmodule