data/full_repos/permissive/150947952/scratch/cyclone10/ip/PIO/PIO.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/150947952/scratch/cyclone10/ip/PIO/PIO.sv:51: Operator SUB expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'iADDRESS\' generates 4 bits.\n                                                                                       : ... In instance PIO\n          oMUXSEL[(iADDRESS-3)*pBITS-1 -:pBITS] <= iWRITE_DATA;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/150947952/scratch/cyclone10/ip/PIO/PIO.sv:62: Operator SUB expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'iADDRESS\' generates 4 bits.\n                                                                                       : ... In instance PIO\n          oREAD_DATA <= oMUXSEL[(iADDRESS-3)*pBITS-1 -:pBITS];\n                                         ^\n%Error: Exiting due to 2 warning(s)\n'
module PIO #(
  parameter pBITS =32,
  parameter pMUX_BITS = 2
) 
(
  input                                 iCLK,
  input                                 iRESET,
                           
  input      [3:0]                      iADDRESS,
  input                                 iWRITE,
  input                                 iREAD,
  input      [31:0]                     iWRITE_DATA,
  output reg [31:0]                     oREAD_DATA,
  
  input      [pBITS-1:0]                iPIO,
  output reg [pBITS-1:0]                oPIO,
  output reg [pBITS-1:0]                oDIR,
  output reg [pBITS*pMUX_BITS-1:0]      oMUXSEL
);

always @(posedge iCLK)
begin
  if (iWRITE) begin
    case (iADDRESS)
      0: oPIO           <= iWRITE_DATA;
      1: oDIR           <= iWRITE_DATA;
      2: oPIO           <= oPIO&~iWRITE_DATA;
      3: oPIO           <= oPIO|iWRITE_DATA;
      default:
        if (iADDRESS<(4+pMUX_BITS))
          oMUXSEL[(iADDRESS-3)*pBITS-1 -:pBITS] <= iWRITE_DATA;
    endcase
  end
  if (iREAD) begin
    case (iADDRESS)
      0: oREAD_DATA <= iPIO;
      1: oREAD_DATA <= oDIR;
      2: oREAD_DATA <= oPIO;
      3: oREAD_DATA <= oPIO;
      default:
        if (iADDRESS<(4+pMUX_BITS))
          oREAD_DATA <= oMUXSEL[(iADDRESS-3)*pBITS-1 -:pBITS];
    endcase
  end
end

endmodule
module PIO #(
  parameter pBITS =32,
  parameter pMUX_BITS = 2
) 
(
  input                                 iCLK,
  input                                 iRESET,
                           
  input      [3:0]                      iADDRESS,
  input                                 iWRITE,
  input                                 iREAD,
  input      [31:0]                     iWRITE_DATA,
  output reg [31:0]                     oREAD_DATA,
  
  input      [pBITS-1:0]                iPIO,
  output reg [pBITS-1:0]                oPIO,
  output reg [pBITS-1:0]                oDIR,
  output reg [pBITS*pMUX_BITS-1:0]      oMUXSEL
);


always @(posedge iCLK)
begin
  if (iWRITE) begin
    case (iADDRESS)
      0: oPIO           <= iWRITE_DATA;
      1: oDIR           <= iWRITE_DATA;
      2: oPIO           <= oPIO&~iWRITE_DATA;
      3: oPIO           <= oPIO|iWRITE_DATA;
      default:
        if (iADDRESS<(4+pMUX_BITS))
          oMUXSEL[(iADDRESS-3)*pBITS-1 -:pBITS] <= iWRITE_DATA;
    endcase
  end
  if (iREAD) begin
    case (iADDRESS)
      0: oREAD_DATA <= iPIO;
      1: oREAD_DATA <= oDIR;
      2: oREAD_DATA <= oPIO;
      3: oREAD_DATA <= oPIO;
      default:
        if (iADDRESS<(4+pMUX_BITS))
          oREAD_DATA <= oMUXSEL[(iADDRESS-3)*pBITS-1 -:pBITS];
    endcase
  end
end

endmodule