data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:41: Unsupported: Ignoring delay on this delayed statement.\n     #1\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #5 str = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #5 addr = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #5 data_in = 32\'h11111111;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #5 addr = 2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #5 data_in = 32\'h22222222;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #5 addr = 3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #5 data_in = 32\'h33333333;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #5 ld = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #5 addr = 2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #5 addr = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #5 sel = 4\'b0101;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #5 sel = 4\'b1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #5 sel = 4\'b1111;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #5 clr = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #5 clr = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #5 addr = 3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #5 addr = 2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #5 addr = 1;\n    ^\n%Error: data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1/sim_data_mem.v:47: Cannot find file containing module: \'Memory\'\nMemory memory( clk,str, sel,ld,   clr, addr,data_in,data_out );\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1,data/full_repos/permissive/173691730/Memory\n             data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1,data/full_repos/permissive/173691730/Memory.v\n             data/full_repos/permissive/173691730/ccmb28_FPGA/sim_1,data/full_repos/permissive/173691730/Memory.sv\n             Memory\n             Memory.v\n             Memory.sv\n             obj_dir/Memory\n             obj_dir/Memory.v\n             obj_dir/Memory.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_data_mem;
 reg clk;
 reg str;
 reg [3:0]sel;
 reg ld;
 reg clr;
 reg [19:0]addr;
 reg [31:0]data_in;
 wire [31:0]data_out;
initial begin
     clk = 0;
     str = 0;
     sel = 4'b1111;
     ld = 0;
     clr = 0;
     addr = 0;
     data_in = 0;
     forever begin
     #1
     clk = ~clk;
     end
end


Memory memory( clk,str, sel,ld,   clr, addr,data_in,data_out );

initial begin

    #5 str = 1;
    #5 addr = 1;
    #5 data_in = 32'h11111111;
    #5 addr = 2;
    #5 data_in = 32'h22222222;
    #5 addr = 3;
    #5 data_in = 32'h33333333;

    str = 0;
    #5 ld = 1;
    #5 addr = 2;
    #5 addr = 1;

    #5 sel = 4'b0101;
    #5 sel = 4'b1000;
    #5 sel = 4'b1111;

    #5 clr = 1;
    #5 clr = 0;
    #5 addr = 3;
    #5 addr = 2;
    #5 addr = 1;
end
endmodule
module sim_data_mem;

 reg clk;
 reg str;
 reg [3:0]sel;
 reg ld;
 reg clr;
 reg [19:0]addr;
 reg [31:0]data_in;
 wire [31:0]data_out;
initial begin
     clk = 0;
     str = 0;
     sel = 4'b1111;
     ld = 0;
     clr = 0;
     addr = 0;
     data_in = 0;
     forever begin
     #1
     clk = ~clk;
     end
end


Memory memory( clk,str, sel,ld,   clr, addr,data_in,data_out );

initial begin

    #5 str = 1;
    #5 addr = 1;
    #5 data_in = 32'h11111111;
    #5 addr = 2;
    #5 data_in = 32'h22222222;
    #5 addr = 3;
    #5 data_in = 32'h33333333;

    str = 0;
    #5 ld = 1;
    #5 addr = 2;
    #5 addr = 1;

    #5 sel = 4'b0101;
    #5 sel = 4'b1000;
    #5 sel = 4'b1111;

    #5 clr = 1;
    #5 clr = 0;
    #5 addr = 3;
    #5 addr = 2;
    #5 addr = 1;
end
endmodule