data/full_repos/permissive/140357212/Tomasulo/iQueue.v
1: b'%Warning-WIDTH: data/full_repos/permissive/140357212/Tomasulo/iQueue.v:28: Bit extraction of array[127:0] requires 7 bit index, not 8 bits.\n                                                                         : ... In instance iQueue.iMem\n assign out = MEM[source];\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module iQueue(clk,clear,inst,addSubFull,mulDivFull);
	parameter ADD = 3'b000;
	parameter SUB = 3'b001;
	parameter MUL = 3'b010;
	parameter DIV = 3'b011;
	
	input [2:0]addSubFull,mulDivFull;
	input clk,clear;
	output [8:0]inst;
	wire [7:0]PC;
	reg stop;
	
	wire [2:0]I;
	assign I = inst[2:0];
	
	always @(clk) begin
		stop = 0;
		if(addSubFull == 3 && (I == ADD || I == SUB))begin
			stop = 1;
		end
		if(mulDivFull == 3 && (I == MUL || I == DIV)) begin
			stop = 1;
		end
	end
	modulePC my_pc(clk,clear,stop,PC);
	mem iMem(PC,inst);

endmodule
module iQueue(clk,clear,inst,addSubFull,mulDivFull);

	parameter ADD = 3'b000;
	parameter SUB = 3'b001;
	parameter MUL = 3'b010;
	parameter DIV = 3'b011;
	
	input [2:0]addSubFull,mulDivFull;
	input clk,clear;
	output [8:0]inst;
	wire [7:0]PC;
	reg stop;
	
	wire [2:0]I;
	assign I = inst[2:0];
	
	always @(clk) begin
		stop = 0;
		if(addSubFull == 3 && (I == ADD || I == SUB))begin
			stop = 1;
		end
		if(mulDivFull == 3 && (I == MUL || I == DIV)) begin
			stop = 1;
		end
	end
	modulePC my_pc(clk,clear,stop,PC);
	mem iMem(PC,inst);

endmodule