data/full_repos/permissive/205055389/test/tkgate/symbol.v
 line:358: before: "."
1: b'%Error: data/full_repos/permissive/205055389/test/tkgate/symbol.v:358: syntax error, unexpected \'.\', expecting \'[\'\nmodule _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK);\n                 ^\n%Error: data/full_repos/permissive/205055389/test/tkgate/symbol.v:364: syntax error, unexpected assign\n  assign #Dck_q Q = Qreg;\n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/test/tkgate/symbol.v:378: syntax error, unexpected \'.\', expecting \'[\'\nmodule _GGMUX4x8 #(.Dsz(1), .Diz(1)) (I0, I1, I2, I3, S, Z);\n                   ^\n%Error: data/full_repos/permissive/205055389/test/tkgate/symbol.v:384: syntax error, unexpected always\n  always @(*)\n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/test/tkgate/symbol.v:399: syntax error, unexpected \'.\', expecting \'[\'\nmodule _GGOR2x8 #(.Diz(1)) (I0, I1, Z);\n                  ^\n%Error: data/full_repos/permissive/205055389/test/tkgate/symbol.v:410: syntax error, unexpected \'.\', expecting \'[\'\nmodule _GGADD8 #(.Dab_s(1), .Dab_co(1), .Dci_s(1), .Dci_co(1)) (A, B, S, CI, CO);\n                 ^\n%Error: data/full_repos/permissive/205055389/test/tkgate/symbol.v:429: syntax error, unexpected \'.\', expecting \'[\'\nmodule _GGNDEMUX4 #(.Dez(1), .Diz(1)) (I, E, Z0, Z1, Z2, Z3);\n                    ^\n%Error: data/full_repos/permissive/205055389/test/tkgate/symbol.v:434: syntax error, unexpected assign\n  assign Zcat = 4\'b1 << I;\n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/test/tkgate/symbol.v:444: syntax error, unexpected \'.\', expecting \'[\'\nmodule _GGAND2x8 #(.Diz(1)) (I0, I1, Z);\n                   ^\n%Error: data/full_repos/permissive/205055389/test/tkgate/symbol.v:455: syntax error, unexpected \'.\', expecting \'[\'\nmodule _GGMUX2x8 #(.Dsz(1), .Diz(1)) (I0, I1, S, Z);\n                   ^\n%Error: data/full_repos/permissive/205055389/test/tkgate/symbol.v:461: syntax error, unexpected always\n  always @(*)\n  ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/tkgate/symbol.v:483: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/tkgate/symbol.v:485: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/tkgate/symbol.v:478: Unsupported: Ignoring delay on this delayed statement.\ninitial #0\n        ^\n%Error: Exiting due to 11 error(s), 3 warning(s)\n'
module ALU(F, A, B, Z);

input [7:0] B;




input [1:0] F;
supply0 w0;
input [7:0] A;






output [7:0] Z;
wire [7:0] w14;
wire w4;
wire [7:0] w11;
wire [7:0] w10;


  _GGADD8 #(68, 70, 62, 64) g4 (.A(B), .B(A), .S(w10), .CI(w0), .CO(w4));







  _GGAND2x8 #(6) g6 (.I0(B), .I1(A), .Z(w11));
  _GGOR2x8 #(6) g7 (.I0(B), .I1(A), .Z(w14));


  _GGMUX4x8 #(12, 12) g0 (.I0(A), .I1(w14), .I2(w11), .I3(w10), .S(F), .Z(Z));


endmodule
module ALU(F, A, B, Z);


input [7:0] B;




input [1:0] F;
supply0 w0;
input [7:0] A;






output [7:0] Z;
wire [7:0] w14;
wire w4;
wire [7:0] w11;
wire [7:0] w10;


  _GGADD8 #(68, 70, 62, 64) g4 (.A(B), .B(A), .S(w10), .CI(w0), .CO(w4));







  _GGAND2x8 #(6) g6 (.I0(B), .I1(A), .Z(w11));
  _GGOR2x8 #(6) g7 (.I0(B), .I1(A), .Z(w14));


  _GGMUX4x8 #(12, 12) g0 (.I0(A), .I1(w14), .I2(w11), .I3(w10), .S(F), .Z(Z));


endmodule