data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v
 line:66: before: "initions"
1: b'%Warning-STMTDLY: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:124: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_HALF_PERIOD;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:138: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:194: Unsupported: Ignoring delay on this delayed statement.\n      #(2 * CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:208: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:293: Unsupported: Ignoring delay on this delayed statement.\n      #(1 * CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:298: Unsupported: Ignoring delay on this delayed statement.\n      #(2 * CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:361: Unsupported: Ignoring delay on this delayed statement.\n      #(2 * CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:364: Unsupported: Ignoring delay on this delayed statement.\n      #(1 * CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:369: Unsupported: Ignoring delay on this delayed statement.\n      #(2 * CLK_PERIOD);\n      ^\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:158: Can\'t find definition of \'start\' in dotted variable: \'dut.start\'\n      $display("start: 0x%01x, ready: 0x%01x", dut.start, dut.ready);\n                                                   ^~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:158: Can\'t find definition of \'ready\' in dotted variable: \'dut.ready\'\n      $display("start: 0x%01x, ready: 0x%01x", dut.start, dut.ready);\n                                                              ^~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:160: Can\'t find definition of \'h0\' in dotted variable: \'dut.h0\'\n               dut.h0, dut.h1, dut.h2, dut.h3, dut.h4);\n                   ^~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:160: Can\'t find definition of \'h1\' in dotted variable: \'dut.h1\'\n               dut.h0, dut.h1, dut.h2, dut.h3, dut.h4);\n                           ^~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:160: Can\'t find definition of \'h2\' in dotted variable: \'dut.h2\'\n               dut.h0, dut.h1, dut.h2, dut.h3, dut.h4);\n                                   ^~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:160: Can\'t find definition of \'h3\' in dotted variable: \'dut.h3\'\n               dut.h0, dut.h1, dut.h2, dut.h3, dut.h4);\n                                           ^~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:160: Can\'t find definition of \'h4\' in dotted variable: \'dut.h4\'\n               dut.h0, dut.h1, dut.h2, dut.h3, dut.h4);\n                                                   ^~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:162: Can\'t find definition of \'s0\' in dotted variable: \'dut.s0\'\n               dut.s0, dut.s1, dut.s2, dut.s3);\n                   ^~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:162: Can\'t find definition of \'s1\' in dotted variable: \'dut.s1\'\n               dut.s0, dut.s1, dut.s2, dut.s3);\n                           ^~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:162: Can\'t find definition of \'s2\' in dotted variable: \'dut.s2\'\n               dut.s0, dut.s1, dut.s2, dut.s3);\n                                   ^~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:162: Can\'t find definition of \'s3\' in dotted variable: \'dut.s3\'\n               dut.s0, dut.s1, dut.s2, dut.s3);\n                                           ^~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:164: Can\'t find definition of \'hres0\' in dotted variable: \'dut.hres0\'\n               dut.hres0, dut.hres1, dut.hres2, dut.hres3);\n                   ^~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:164: Can\'t find definition of \'hres1\' in dotted variable: \'dut.hres1\'\n               dut.hres0, dut.hres1, dut.hres2, dut.hres3);\n                              ^~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:164: Can\'t find definition of \'hres2\' in dotted variable: \'dut.hres2\'\n               dut.hres0, dut.hres1, dut.hres2, dut.hres3);\n                                         ^~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:164: Can\'t find definition of \'hres3\' in dotted variable: \'dut.hres3\'\n               dut.hres0, dut.hres1, dut.hres2, dut.hres3);\n                                                    ^~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:168: Can\'t find definition of \'cycle_ctr_reg\' in dotted variable: \'dut.cycle_ctr_reg\'\n      $display("cycle_ctr: 0x%01x", dut.cycle_ctr_reg);\n                                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:169: Can\'t find definition of \'final_ctrl_reg\' in dotted variable: \'dut.final_ctrl_reg\'\n      $display("ctrl:      0x%01x", dut.final_ctrl_reg);\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:173: Can\'t find definition of \'u0_reg\' in dotted variable: \'dut.u0_reg\'\n               dut.u0_reg, dut.u1_reg, dut.u2_reg);\n                   ^~~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:173: Can\'t find definition of \'u1_reg\' in dotted variable: \'dut.u1_reg\'\n               dut.u0_reg, dut.u1_reg, dut.u2_reg);\n                               ^~~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:173: Can\'t find definition of \'u2_reg\' in dotted variable: \'dut.u2_reg\'\n               dut.u0_reg, dut.u1_reg, dut.u2_reg);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:175: Can\'t find definition of \'u3_reg\' in dotted variable: \'dut.u3_reg\'\n               dut.u3_reg, dut.u4_reg);\n                   ^~~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:175: Can\'t find definition of \'u4_reg\' in dotted variable: \'dut.u4_reg\'\n               dut.u3_reg, dut.u4_reg);\n                               ^~~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:176: Can\'t find definition of \'uu0_reg\' in dotted variable: \'dut.uu0_reg\'\n      $display("uu0:  0x%016x  uu1: 0x%016x", dut.uu0_reg, dut.uu1_reg);\n                                                  ^~~~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:176: Can\'t find definition of \'uu1_reg\' in dotted variable: \'dut.uu1_reg\'\n      $display("uu0:  0x%016x  uu1: 0x%016x", dut.uu0_reg, dut.uu1_reg);\n                                                               ^~~~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:177: Can\'t find definition of \'uu2_reg\' in dotted variable: \'dut.uu2_reg\'\n      $display("uu2:  0x%016x  uu3: 0x%016x", dut.uu2_reg, dut.uu3_reg);\n                                                  ^~~~~~~\n%Error: data/full_repos/permissive/133480136/src/tb/tb_poly1305_final.v:177: Can\'t find definition of \'uu3_reg\' in dotted variable: \'dut.uu3_reg\'\n      $display("uu2:  0x%016x  uu3: 0x%016x", dut.uu2_reg, dut.uu3_reg);\n                                                               ^~~~~~~\n%Error: Exiting due to 26 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_poly1305_final();




  parameter DEBUG     = 0;
  parameter DUMP_WAIT = 0;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;





  reg [31 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;
  integer      incorrect;

  reg           tb_debug;

  reg           tb_clk;
  reg           tb_reset_n;

  reg           tb_start;
  wire          tb_ready;

  reg [31 : 0]  tb_h0;
  reg [31 : 0]  tb_h1;
  reg [31 : 0]  tb_h2;
  reg [31 : 0]  tb_h3;
  reg [31 : 0]  tb_h4;

  reg [31 : 0]  tb_s0;
  reg [31 : 0]  tb_s1;
  reg [31 : 0]  tb_s2;
  reg [31 : 0]  tb_s3;

  wire [31 : 0] tb_hres0;
  wire [31 : 0] tb_hres1;
  wire [31 : 0] tb_hres2;
  wire [31 : 0] tb_hres3;





  poly1305_final dut(
                     .clk(tb_clk),
                     .reset_n(tb_reset_n),

                     .start(tb_start),
                     .ready(tb_ready),

                     .h0(tb_h0),
                     .h1(tb_h1),
                     .h2(tb_h2),
                     .h3(tb_h3),
                     .h4(tb_h4),

                     .s0(tb_s0),
                     .s1(tb_s1),
                     .s2(tb_s2),
                     .s3(tb_s3),

                     .hres0(tb_hres0),
                     .hres1(tb_hres1),
                     .hres2(tb_hres2),
                     .hres3(tb_hres3)
                    );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD;
      tb_clk = !tb_clk;
    end








  always
    begin : sys_monitor
      cycle_ctr = cycle_ctr + 1;
      #(CLK_PERIOD);
      if (tb_debug)
        begin
          dump_dut_state();
        end
    end







  task dump_dut_state;
    begin
      $display("=====================================================");
      $display("cycle %08d", cycle_ctr);
      $display("State of DUT");
      $display("------------");
      $display("Inputs and outputs:");
      $display("start: 0x%01x, ready: 0x%01x", dut.start, dut.ready);
      $display("h0: 0x%08x  h1: 0x%08x  h2: 0x%08x  h3: 0x%08x  h4: 0x%08x",
               dut.h0, dut.h1, dut.h2, dut.h3, dut.h4);
      $display("s0: 0x%08x  s1: 0x%08x  s2: 0x%08x  s3: 0x%08x",
               dut.s0, dut.s1, dut.s2, dut.s3);
      $display("hres0: 0x%08x  hres1: 0x%08x  hres2: 0x%08x  hres3:0x%08x",
               dut.hres0, dut.hres1, dut.hres2, dut.hres3);
      $display("");

      $display("Control:");
      $display("cycle_ctr: 0x%01x", dut.cycle_ctr_reg);
      $display("ctrl:      0x%01x", dut.final_ctrl_reg);
      $display("");
      $display("Internal values:");
      $display("u0:   0x%016x  u1: 0x%016x  u2: 0x%016x",
               dut.u0_reg, dut.u1_reg, dut.u2_reg);
      $display("u3:   0x%016x  u4: 0x%016x",
               dut.u3_reg, dut.u4_reg);
      $display("uu0:  0x%016x  uu1: 0x%016x", dut.uu0_reg, dut.uu1_reg);
      $display("uu2:  0x%016x  uu3: 0x%016x", dut.uu2_reg, dut.uu3_reg);

      $display("=====================================================");
      $display("\n");
    end
  endtask







  task reset_dut;
    begin
      $display("*** Toggle reset.");
      tb_reset_n = 0;
      #(2 * CLK_PERIOD);
      tb_reset_n = 1;
    end
  endtask







  task wait_ready;
    begin : wready
      while (!tb_ready)
        #(CLK_PERIOD);
    end
  endtask








  task init_sim;
    begin
      $display("*** Initializing the simulation.");
      cycle_ctr  = 0;
      error_ctr  = 0;
      tc_ctr     = 0;
      tb_debug   = 0;

      tb_clk     = 0;
      tb_reset_n = 1;

      tb_start   = 0;

      tb_h0      = 32'h0;
      tb_h1      = 32'h0;
      tb_h2      = 32'h0;
      tb_h3      = 32'h0;
      tb_h4      = 32'h0;

      tb_s0      = 32'h0;
      tb_s1      = 32'h0;
      tb_s2      = 32'h0;
      tb_s3      = 32'h0;
    end
  endtask







  task display_test_result;
    begin
      if (error_ctr == 0)
        begin
          $display("*** All %02d test cases completed successfully", tc_ctr);
        end
      else
        begin
          $display("*** %02d tests completed - %02d test cases did not complete successfully.",
                   tc_ctr, error_ctr);
        end
    end
  endtask









  task test_rfc8349;
    begin : test_rfc8349
      $display("*** test_rfc8349 started.\n");

      tc_ctr = tc_ctr + 1;
      incorrect = 0;

      tb_h0 = 32'h369d03a7;
      tb_h1 = 32'hc8844335;
      tb_h2 = 32'hff946c77;
      tb_h3 = 32'h8d31b7ca;
      tb_h4 = 32'h00000002;

      tb_s0 = 32'h8a800301;
      tb_s1 = 32'hfdb20dfb;
      tb_s2 = 32'haff6bf4a;
      tb_s3 = 32'h1bf54941;

      tb_debug = 1;
      tb_start = 1;
      #(1 * CLK_PERIOD);
      tb_start = 0;
      wait_ready();
      $display("DUT should be done.");

      #(2 * CLK_PERIOD);
      tb_debug = 0;

      if (tb_hres0 != 32'hc11d06a8)
        begin
          $display("Error in hres0. Expected: 0xc11d06a8. Got: 0x%08x\n",
                   tb_hres0);
          incorrect = incorrect + 1;
        end

      if (tb_hres1 != 32'hc6365130)
        begin
          $display("Error in hres1. Expected: 0xc6365130. Got: 0x%08x\n",
                   tb_hres1);
          incorrect = incorrect + 1;
        end

      if (tb_hres2 != 32'haf8b2bc2)
        begin
          $display("Error in hres2. Expected: 0xaf8b2bc2. Got: 0x%08x\n",
                   tb_hres2);
          incorrect = incorrect + 1;
        end

      if (tb_hres3 != 32'ha927010c)
        begin
          $display("Error in hres3. Expected: 0xa927010c. Got: 0x%08x\n",
                   tb_hres3);
          incorrect = incorrect + 1;
        end

      if (!incorrect)
        $display("*** test_rfc8349 successfully completed.\n");
      else
        $display("*** test_rfc8349 completed with %d errors.\n", incorrect);
    end
  endtask







  task test_bytes16;
    begin : test_bytes16
      $display("*** test_bytes16 started.\n");

      tc_ctr = tc_ctr + 1;
      incorrect = 0;

      tb_h0 = 32'ha344603a;
      tb_h1 = 32'hb694ccc5;
      tb_h2 = 32'h94a85081;
      tb_h3 = 32'hd04d254c;
      tb_h4 = 32'h00000003;

      tb_s0 = 32'h8a800301;
      tb_s1 = 32'hfdb20dfb;
      tb_s2 = 32'haff6bf4a;
      tb_s3 = 32'h1bf54941;

      tb_debug = 1;
      #(2 * CLK_PERIOD);

      tb_start = 1;
      #(1 * CLK_PERIOD);
      tb_start = 0;
      wait_ready();
      $display("DUT should be done.");

      #(2 * CLK_PERIOD);
      tb_debug = 0;

      if (tb_hres0 != 32'h2dc4633b)
        begin
          $display("Error in hres0. Expected: 0x2dc4633b. Got: 0x%08x\n",
                   tb_hres0);
          incorrect = incorrect + 1;
        end

      if (tb_hres1 != 32'hb446dac1)
        begin
          $display("Error in hres1. Expected: 0xb446dac1. Got: 0x%08x\n",
                   tb_hres1);
          incorrect = incorrect + 1;
        end

      if (tb_hres2 != 32'h449f0fcc)
        begin
          $display("Error in hres2. Expected: 0x449f0fcc. Got: 0x%08x\n",
                   tb_hres2);
          incorrect = incorrect + 1;
        end

      if (tb_hres3 != 32'hec426e8e)
        begin
          $display("Error in hres3. Expected: 0xec426e8e. Got: 0x%08x\n",
                   tb_hres3);
          incorrect = incorrect + 1;
        end

      if (!incorrect)
        $display("*** test_bytes16 successfully completed.\n");
      else
        $display("*** test_bytes16 completed with %d errors.\n", incorrect);
    end
  endtask





  initial
    begin : poly1305_final_test
      $display("*** Poly1305 final simulation started.\n");

      init_sim();
      dump_dut_state();
      reset_dut();
      dump_dut_state();


      test_rfc8349();
      test_bytes16();

      display_test_result();

      $display("");
      $display("*** Poly1305 final simulation done.\n");
      $finish;
    end
endmodule
module tb_poly1305_final();





  parameter DEBUG     = 0;
  parameter DUMP_WAIT = 0;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;





  reg [31 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;
  integer      incorrect;

  reg           tb_debug;

  reg           tb_clk;
  reg           tb_reset_n;

  reg           tb_start;
  wire          tb_ready;

  reg [31 : 0]  tb_h0;
  reg [31 : 0]  tb_h1;
  reg [31 : 0]  tb_h2;
  reg [31 : 0]  tb_h3;
  reg [31 : 0]  tb_h4;

  reg [31 : 0]  tb_s0;
  reg [31 : 0]  tb_s1;
  reg [31 : 0]  tb_s2;
  reg [31 : 0]  tb_s3;

  wire [31 : 0] tb_hres0;
  wire [31 : 0] tb_hres1;
  wire [31 : 0] tb_hres2;
  wire [31 : 0] tb_hres3;





  poly1305_final dut(
                     .clk(tb_clk),
                     .reset_n(tb_reset_n),

                     .start(tb_start),
                     .ready(tb_ready),

                     .h0(tb_h0),
                     .h1(tb_h1),
                     .h2(tb_h2),
                     .h3(tb_h3),
                     .h4(tb_h4),

                     .s0(tb_s0),
                     .s1(tb_s1),
                     .s2(tb_s2),
                     .s3(tb_s3),

                     .hres0(tb_hres0),
                     .hres1(tb_hres1),
                     .hres2(tb_hres2),
                     .hres3(tb_hres3)
                    );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD;
      tb_clk = !tb_clk;
    end








  always
    begin : sys_monitor
      cycle_ctr = cycle_ctr + 1;
      #(CLK_PERIOD);
      if (tb_debug)
        begin
          dump_dut_state();
        end
    end







  task dump_dut_state;
    begin
      $display("=====================================================");
      $display("cycle %08d", cycle_ctr);
      $display("State of DUT");
      $display("------------");
      $display("Inputs and outputs:");
      $display("start: 0x%01x, ready: 0x%01x", dut.start, dut.ready);
      $display("h0: 0x%08x  h1: 0x%08x  h2: 0x%08x  h3: 0x%08x  h4: 0x%08x",
               dut.h0, dut.h1, dut.h2, dut.h3, dut.h4);
      $display("s0: 0x%08x  s1: 0x%08x  s2: 0x%08x  s3: 0x%08x",
               dut.s0, dut.s1, dut.s2, dut.s3);
      $display("hres0: 0x%08x  hres1: 0x%08x  hres2: 0x%08x  hres3:0x%08x",
               dut.hres0, dut.hres1, dut.hres2, dut.hres3);
      $display("");

      $display("Control:");
      $display("cycle_ctr: 0x%01x", dut.cycle_ctr_reg);
      $display("ctrl:      0x%01x", dut.final_ctrl_reg);
      $display("");
      $display("Internal values:");
      $display("u0:   0x%016x  u1: 0x%016x  u2: 0x%016x",
               dut.u0_reg, dut.u1_reg, dut.u2_reg);
      $display("u3:   0x%016x  u4: 0x%016x",
               dut.u3_reg, dut.u4_reg);
      $display("uu0:  0x%016x  uu1: 0x%016x", dut.uu0_reg, dut.uu1_reg);
      $display("uu2:  0x%016x  uu3: 0x%016x", dut.uu2_reg, dut.uu3_reg);

      $display("=====================================================");
      $display("\n");
    end
  endtask







  task reset_dut;
    begin
      $display("*** Toggle reset.");
      tb_reset_n = 0;
      #(2 * CLK_PERIOD);
      tb_reset_n = 1;
    end
  endtask







  task wait_ready;
    begin : wready
      while (!tb_ready)
        #(CLK_PERIOD);
    end
  endtask








  task init_sim;
    begin
      $display("*** Initializing the simulation.");
      cycle_ctr  = 0;
      error_ctr  = 0;
      tc_ctr     = 0;
      tb_debug   = 0;

      tb_clk     = 0;
      tb_reset_n = 1;

      tb_start   = 0;

      tb_h0      = 32'h0;
      tb_h1      = 32'h0;
      tb_h2      = 32'h0;
      tb_h3      = 32'h0;
      tb_h4      = 32'h0;

      tb_s0      = 32'h0;
      tb_s1      = 32'h0;
      tb_s2      = 32'h0;
      tb_s3      = 32'h0;
    end
  endtask







  task display_test_result;
    begin
      if (error_ctr == 0)
        begin
          $display("*** All %02d test cases completed successfully", tc_ctr);
        end
      else
        begin
          $display("*** %02d tests completed - %02d test cases did not complete successfully.",
                   tc_ctr, error_ctr);
        end
    end
  endtask









  task test_rfc8349;
    begin : test_rfc8349
      $display("*** test_rfc8349 started.\n");

      tc_ctr = tc_ctr + 1;
      incorrect = 0;

      tb_h0 = 32'h369d03a7;
      tb_h1 = 32'hc8844335;
      tb_h2 = 32'hff946c77;
      tb_h3 = 32'h8d31b7ca;
      tb_h4 = 32'h00000002;

      tb_s0 = 32'h8a800301;
      tb_s1 = 32'hfdb20dfb;
      tb_s2 = 32'haff6bf4a;
      tb_s3 = 32'h1bf54941;

      tb_debug = 1;
      tb_start = 1;
      #(1 * CLK_PERIOD);
      tb_start = 0;
      wait_ready();
      $display("DUT should be done.");

      #(2 * CLK_PERIOD);
      tb_debug = 0;

      if (tb_hres0 != 32'hc11d06a8)
        begin
          $display("Error in hres0. Expected: 0xc11d06a8. Got: 0x%08x\n",
                   tb_hres0);
          incorrect = incorrect + 1;
        end

      if (tb_hres1 != 32'hc6365130)
        begin
          $display("Error in hres1. Expected: 0xc6365130. Got: 0x%08x\n",
                   tb_hres1);
          incorrect = incorrect + 1;
        end

      if (tb_hres2 != 32'haf8b2bc2)
        begin
          $display("Error in hres2. Expected: 0xaf8b2bc2. Got: 0x%08x\n",
                   tb_hres2);
          incorrect = incorrect + 1;
        end

      if (tb_hres3 != 32'ha927010c)
        begin
          $display("Error in hres3. Expected: 0xa927010c. Got: 0x%08x\n",
                   tb_hres3);
          incorrect = incorrect + 1;
        end

      if (!incorrect)
        $display("*** test_rfc8349 successfully completed.\n");
      else
        $display("*** test_rfc8349 completed with %d errors.\n", incorrect);
    end
  endtask







  task test_bytes16;
    begin : test_bytes16
      $display("*** test_bytes16 started.\n");

      tc_ctr = tc_ctr + 1;
      incorrect = 0;

      tb_h0 = 32'ha344603a;
      tb_h1 = 32'hb694ccc5;
      tb_h2 = 32'h94a85081;
      tb_h3 = 32'hd04d254c;
      tb_h4 = 32'h00000003;

      tb_s0 = 32'h8a800301;
      tb_s1 = 32'hfdb20dfb;
      tb_s2 = 32'haff6bf4a;
      tb_s3 = 32'h1bf54941;

      tb_debug = 1;
      #(2 * CLK_PERIOD);

      tb_start = 1;
      #(1 * CLK_PERIOD);
      tb_start = 0;
      wait_ready();
      $display("DUT should be done.");

      #(2 * CLK_PERIOD);
      tb_debug = 0;

      if (tb_hres0 != 32'h2dc4633b)
        begin
          $display("Error in hres0. Expected: 0x2dc4633b. Got: 0x%08x\n",
                   tb_hres0);
          incorrect = incorrect + 1;
        end

      if (tb_hres1 != 32'hb446dac1)
        begin
          $display("Error in hres1. Expected: 0xb446dac1. Got: 0x%08x\n",
                   tb_hres1);
          incorrect = incorrect + 1;
        end

      if (tb_hres2 != 32'h449f0fcc)
        begin
          $display("Error in hres2. Expected: 0x449f0fcc. Got: 0x%08x\n",
                   tb_hres2);
          incorrect = incorrect + 1;
        end

      if (tb_hres3 != 32'hec426e8e)
        begin
          $display("Error in hres3. Expected: 0xec426e8e. Got: 0x%08x\n",
                   tb_hres3);
          incorrect = incorrect + 1;
        end

      if (!incorrect)
        $display("*** test_bytes16 successfully completed.\n");
      else
        $display("*** test_bytes16 completed with %d errors.\n", incorrect);
    end
  endtask





  initial
    begin : poly1305_final_test
      $display("*** Poly1305 final simulation started.\n");

      init_sim();
      dump_dut_state();
      reset_dut();
      dump_dut_state();


      test_rfc8349();
      test_bytes16();

      display_test_result();

      $display("");
      $display("*** Poly1305 final simulation done.\n");
      $finish;
    end
endmodule