data/full_repos/permissive/102394571/FSM_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #10 c_type = 2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #10 ok = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/FSM_sim.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #5  clk =  ! clk; \n  ^\n%Error: data/full_repos/permissive/102394571/FSM_sim.v:40: Cannot find file containing module: \'FSM\'\n FSM uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/102394571,data/full_repos/permissive/102394571/FSM\n             data/full_repos/permissive/102394571,data/full_repos/permissive/102394571/FSM.v\n             data/full_repos/permissive/102394571,data/full_repos/permissive/102394571/FSM.sv\n             FSM\n             FSM.v\n             FSM.sv\n             obj_dir/FSM\n             obj_dir/FSM.v\n             obj_dir/FSM.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FSM_sim;


	reg clk;
	reg ok;
	reg [1:0] c_type;
	reg t_expired;
	reg reset;


	wire [2:0] ing_type;
	wire start_timer;
	wire [7:3] ingredientes;


	FSM uut (
		.clk(clk), 
		.ok(ok), 
		.c_type(c_type), 
		.t_expired(t_expired), 
		.reset(reset), 
		.ing_type(ing_type), 
		.start_timer(start_timer), 
		.ingredientes(ingredientes)
	);

	initial begin

		clk = 0;
		ok = 0;
		c_type = 0;
		t_expired = 0;
		reset = 0;


		#100;
        

		#10 c_type = 2;
		#10 ok = 1;
		#10 t_expired = 1;
		#10 t_expired = 0;
		#10 t_expired = 1;
		#10 t_expired = 0;
		#10 t_expired = 1;
		#10 t_expired = 0;
		#10 t_expired = 1;
		#10 t_expired = 0;
		#10 t_expired = 1;
		#10 t_expired = 0;
		
	end
	
	always 
		#5  clk =  ! clk; 
endmodule
module FSM_sim;



	reg clk;
	reg ok;
	reg [1:0] c_type;
	reg t_expired;
	reg reset;


	wire [2:0] ing_type;
	wire start_timer;
	wire [7:3] ingredientes;


	FSM uut (
		.clk(clk), 
		.ok(ok), 
		.c_type(c_type), 
		.t_expired(t_expired), 
		.reset(reset), 
		.ing_type(ing_type), 
		.start_timer(start_timer), 
		.ingredientes(ingredientes)
	);

	initial begin

		clk = 0;
		ok = 0;
		c_type = 0;
		t_expired = 0;
		reset = 0;


		#100;
        

		#10 c_type = 2;
		#10 ok = 1;
		#10 t_expired = 1;
		#10 t_expired = 0;
		#10 t_expired = 1;
		#10 t_expired = 0;
		#10 t_expired = 1;
		#10 t_expired = 0;
		#10 t_expired = 1;
		#10 t_expired = 0;
		#10 t_expired = 1;
		#10 t_expired = 0;
		
	end
	
	always 
		#5  clk =  ! clk; 
endmodule