data/full_repos/permissive/154804262/src/BpsClkGen.v
'utf-8' codec can't decode byte 0xb0 in position 20: invalid start byte
1: b'%Warning-WIDTH: data/full_repos/permissive/154804262/src/BpsClkGen.v:17: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 27 bits.\n                                                                       : ... In instance BpsClkGen\n reg [bpsWIDTH - 1:0] bps = CLKFREQ / BAUDRATE;\n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154804262/src/BpsClkGen.v:20: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance BpsClkGen\n reg [bpsWIDTH - 1:0] bpsCount = 1\'d0;\n                                 ^~~~\n%Warning-WIDTH: data/full_repos/permissive/154804262/src/BpsClkGen.v:24: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance BpsClkGen\n   bpsCount <= 1\'d0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/154804262/src/BpsClkGen.v:26: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance BpsClkGen\n   bpsCount <= 1\'d0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/154804262/src/BpsClkGen.v:30: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance BpsClkGen\n   bpsCount <= 1\'d0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/154804262/src/BpsClkGen.v:34: Operator ASSIGNW expects 13 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 14 bits.\n                                                                       : ... In instance BpsClkGen\n wire [bpsWIDTH - 2:0] BPS_CLK_V = (bps >> 1);\n                                 ^\n%Error: Exiting due to 6 warning(s)\n'
module BpsClkGen

#(
	parameter CLKFREQ = 100_000_000,
	parameter BAUDRATE = 115200,
	parameter bpsWIDTH = 14
)

(
	input clk,
	input reset,
	input countEnable,
	output bpsClk
);


	reg [bpsWIDTH - 1:0] bps = CLKFREQ / BAUDRATE;
	

	reg [bpsWIDTH - 1:0] bpsCount = 1'd0;
	always @ (posedge clk or negedge reset)
	begin
		if (!reset)
			bpsCount <= 1'd0;
		else if (bpsCount == (bps - 1))
			bpsCount <= 1'd0;
		else if (countEnable)
			bpsCount <= bpsCount + 1'd1;
		else
			bpsCount <= 1'd0;
	end


	wire [bpsWIDTH - 2:0] BPS_CLK_V = (bps >> 1);
	reg bpsClkEnable;
	always @(posedge clk or negedge reset)
	begin
		if (!reset)
			bpsClkEnable <= 1'd0;
		else if (bpsCount == BPS_CLK_V - 1)
			bpsClkEnable <= 1'd1;
		else
			bpsClkEnable <= 1'd0;
	end

	assign bpsClk = bpsClkEnable;
	
endmodule
module BpsClkGen

#(
	parameter CLKFREQ = 100_000_000,
	parameter BAUDRATE = 115200,
	parameter bpsWIDTH = 14
)

(
	input clk,
	input reset,
	input countEnable,
	output bpsClk
);



	reg [bpsWIDTH - 1:0] bps = CLKFREQ / BAUDRATE;
	

	reg [bpsWIDTH - 1:0] bpsCount = 1'd0;
	always @ (posedge clk or negedge reset)
	begin
		if (!reset)
			bpsCount <= 1'd0;
		else if (bpsCount == (bps - 1))
			bpsCount <= 1'd0;
		else if (countEnable)
			bpsCount <= bpsCount + 1'd1;
		else
			bpsCount <= 1'd0;
	end


	wire [bpsWIDTH - 2:0] BPS_CLK_V = (bps >> 1);
	reg bpsClkEnable;
	always @(posedge clk or negedge reset)
	begin
		if (!reset)
			bpsClkEnable <= 1'd0;
		else if (bpsCount == BPS_CLK_V - 1)
			bpsClkEnable <= 1'd1;
		else
			bpsClkEnable <= 1'd0;
	end

	assign bpsClk = bpsClkEnable;
	
endmodule