data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v
 line:112: before: "$"
1: b'%Error: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:87: Unsupported or unknown PLI call: $dumpvars\n           $dumpvars(0,A);\n           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:88: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:99: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:102: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:105: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:108: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:111: Unsupported: Ignoring delay on this delayed statement.\n           #40\n           ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sing(
    input [11:0] PTX,
    input [11:0] PTY,

    input [11:0] P1X,
    input [11:0] P1Y,

    input [11:0] P2X,
    input [11:0] P2Y,

    output sin
);

    wire signed [11:0] Sub1;
    wire signed [11:0] Sub2;
    wire signed [11:0] Sub3;
    wire signed [11:0] Sub4;

    wire signed [22:0] Sub5;

    wire signed [22:0] Mult1;
    wire signed [22:0] Mult2;


    assign Sub1 = PTX - P2X;
    assign Sub2 = P1Y - P2Y;
    assign Sub3 = P1X - P2X;
    assign Sub4 = PTY - P2Y;

    assign Mult1 = Sub1 * Sub2;
    assign Mult2 = Sub3 * Sub4;

    assign Sub5 = Mult1 - Mult2;

    assign sin = (Sub5 >= 0) ? 1 : 0;

endmodule
module sing(
    input [11:0] PTX,
    input [11:0] PTY,

    input [11:0] P1X,
    input [11:0] P1Y,

    input [11:0] P2X,
    input [11:0] P2Y,

    output sin
);


    wire signed [11:0] Sub1;
    wire signed [11:0] Sub2;
    wire signed [11:0] Sub3;
    wire signed [11:0] Sub4;

    wire signed [22:0] Sub5;

    wire signed [22:0] Mult1;
    wire signed [22:0] Mult2;


    assign Sub1 = PTX - P2X;
    assign Sub2 = P1Y - P2Y;
    assign Sub3 = P1X - P2X;
    assign Sub4 = PTY - P2Y;

    assign Mult1 = Sub1 * Sub2;
    assign Mult2 = Sub3 * Sub4;

    assign Sub5 = Mult1 - Mult2;

    assign sin = (Sub5 >= 0) ? 1 : 0;

endmodule