data/full_repos/permissive/211316121/lab5_1/_74LS163.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/211316121/lab5_1/_74LS163.v:18: Signal definition not found, creating implicitly: \'E\'\n                                                                            : ... Suggested alternative: \'EP\'\n    assign E={EP,ET};\n           ^\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/211316121/lab5_1/_74LS163.v:18: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                         : ... In instance _74LS163\n    assign E={EP,ET};\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module _74LS163(
input CLK,
input CLR,
input LOAD,
input EP,
input ET,
input D,
input C,
input B,
input A,
output wire QD,
output wire QC,
output wire QB,
output wire QA,
output wire RCO
    );
    assign E={EP,ET};
    wire [3:0]Date;
    reg [3:0] Q;
    assign Date={D,C,B,A};
    assign RCO=ET&EP&(Q=='b1111);
    
    always@(posedge CLK)
    begin
        if(~CLR) Q<='b0000;
        else if(~LOAD) Q<=Date;
        else if(LOAD==1&&EP==1&&ET==1) Q<=Q+1;
        else if(LOAD==1&& (EP==0||ET==0)) Q<=Q;
     end
     
     assign QD=Q[3];
     assign QC=Q[2];
     assign QB=Q[1];
     assign QA=Q[0];
     

                
endmodule
module _74LS163(
input CLK,
input CLR,
input LOAD,
input EP,
input ET,
input D,
input C,
input B,
input A,
output wire QD,
output wire QC,
output wire QB,
output wire QA,
output wire RCO
    );

    assign E={EP,ET};
    wire [3:0]Date;
    reg [3:0] Q;
    assign Date={D,C,B,A};
    assign RCO=ET&EP&(Q=='b1111);
    
    always@(posedge CLK)
    begin
        if(~CLR) Q<='b0000;
        else if(~LOAD) Q<=Date;
        else if(LOAD==1&&EP==1&&ET==1) Q<=Q+1;
        else if(LOAD==1&& (EP==0||ET==0)) Q<=Q;
     end
     
     assign QD=Q[3];
     assign QC=Q[2];
     assign QB=Q[1];
     assign QA=Q[0];
     

                
endmodule