data/full_repos/permissive/104269513/control_logic.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/control_logic.v:238: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/104269513/control_logic.v:229: Cell has missing pin: \'PL_done\'\ncontrol control(.instruction(instruction), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .Jump(Jump), .ble(ble), .imme(imme), .ALUop(ALUop), .Master_reg(Master_reg), .mem_sel(mem_sel));\n        ^~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/104269513/control_logic.v:229: Cell has missing pin: \'FW_ld\'\ncontrol control(.instruction(instruction), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .Jump(Jump), .ble(ble), .imme(imme), .ALUop(ALUop), .Master_reg(Master_reg), .mem_sel(mem_sel));\n        ^~~~~~~\n%Warning-INFINITELOOP: data/full_repos/permissive/104269513/control_logic.v:238: Infinite loop (condition always true)\n                                                                               : ... In instance control_tb\nforever #10 clk = ~clk;\n^~~~~~~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control_tb;

reg clk;
reg [31:0]instruction;
wire RegWrite;
wire ALUSrc;
wire MemWrite;
wire MemtoReg;
wire Jump;
wire ble;
wire imme;
wire [3:0] ALUop;
wire [2:0]Master_reg;
wire mem_sel;
integer count;
					
control control(.instruction(instruction), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .Jump(Jump), .ble(ble), .imme(imme), .ALUop(ALUop), .Master_reg(Master_reg), .mem_sel(mem_sel));

initial
begin

instruction = 'h00000000;
clk = 0;
count = 0;

forever #10 clk = ~clk;
end

always @(posedge clk)
begin
	count <= count + 1;
	
	if (count == 1)
		begin

		instruction <= 'h0000001e;
		end
	
	if (count == 2)
		begin

		instruction <= 'h0000101e;
		end
		
	if (count == 3)
		begin

		instruction <= 'h0000201e;
		end
		
	if (count == 4)
		begin

		instruction <= 'h0000301e;
		end
	
	if (count == 5)
		begin

		instruction <= 'h0000401e;
		end
		
	if (count == 6)
		begin

		instruction <= 'h0000501e;
		end
		
	if (count == 7)
		begin

		instruction <= 'h0000601e;
		end
		
	if (count == 8)
		begin

		instruction <= 'hfe047623;
		end 
		




end
					
endmodule
module control_tb;


reg clk;
reg [31:0]instruction;
wire RegWrite;
wire ALUSrc;
wire MemWrite;
wire MemtoReg;
wire Jump;
wire ble;
wire imme;
wire [3:0] ALUop;
wire [2:0]Master_reg;
wire mem_sel;
integer count;
					
control control(.instruction(instruction), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .Jump(Jump), .ble(ble), .imme(imme), .ALUop(ALUop), .Master_reg(Master_reg), .mem_sel(mem_sel));

initial
begin

instruction = 'h00000000;
clk = 0;
count = 0;

forever #10 clk = ~clk;
end

always @(posedge clk)
begin
	count <= count + 1;
	
	if (count == 1)
		begin

		instruction <= 'h0000001e;
		end
	
	if (count == 2)
		begin

		instruction <= 'h0000101e;
		end
		
	if (count == 3)
		begin

		instruction <= 'h0000201e;
		end
		
	if (count == 4)
		begin

		instruction <= 'h0000301e;
		end
	
	if (count == 5)
		begin

		instruction <= 'h0000401e;
		end
		
	if (count == 6)
		begin

		instruction <= 'h0000501e;
		end
		
	if (count == 7)
		begin

		instruction <= 'h0000601e;
		end
		
	if (count == 8)
		begin

		instruction <= 'hfe047623;
		end 
		




end
					
endmodule