data/full_repos/permissive/106330868/verilog/controller/xlat_tb.v
1: b'%Error: data/full_repos/permissive/106330868/verilog/controller/xlat_tb.v:33: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile ("xlat.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/106330868/verilog/controller/xlat_tb.v:34: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106330868/verilog/controller/xlat_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module XLAT_TB;    
    reg [7:0]  c8_in;
    wire [9:0] c10_out;

    XLAT u_xlat (
        c8_in, 
        c10_out
    );

    integer i;
    initial
    begin
        $dumpfile ("xlat.vcd");
        $dumpvars;
        c8_in[7] = 0;
        for(i=0; i<128; i=i+1)
        begin
            c8_in[6:0] = i;
            #10;
        end
        $finish;
    end

endmodule
module XLAT_TB;
    
    reg [7:0]  c8_in;
    wire [9:0] c10_out;

    XLAT u_xlat (
        c8_in, 
        c10_out
    );

    integer i;
    initial
    begin
        $dumpfile ("xlat.vcd");
        $dumpvars;
        c8_in[7] = 0;
        for(i=0; i<128; i=i+1)
        begin
            c8_in[6:0] = i;
            #10;
        end
        $finish;
    end

endmodule