data/full_repos/permissive/20270692/labs/lab7/res/mux81c.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/20270692/labs/lab7/res/mux81c.v:4: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input [0:7] I;\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/20270692/labs/lab7/res/mux81c.v:7: Little bit endian vector: MSB < LSB of bit range: 0:2\n  input [0:2] S;  \n        ^\n%Error: Exiting due to 2 warning(s)\n'
module mux81c (I,S,Y);
  input [0:7] I;
  wire [0:7] I;

  input [0:2] S;
  wire [0:2] S;
  output Y;
  reg Y;

  wire A,B,C;





  always @(S or I)
  begin

    if(S[0]==1)
    begin
      if(S[1]==1)
      begin
        if(S[2]==1)
          Y=I[7];
        else
          Y=I[6];
      end
      else
      begin
      if(S[2]==1)
        Y=I[5];
      else
        Y=I[4];
      end
    end
    else
    begin
      if(S[1]==1)
      begin
        if(S[2]==1)
          Y=I[3];
        else
        begin
          $display("time=%0d,S=%b,I2=%b, Y=%b",$time,S,I[2],Y);
          Y=I[2];
          $display("time=%0d,S=%b,I2=%b, Y=%b",$time,S,I[2],Y);
        end
      end
      else
        begin
        if(S[2]==1)
          Y=I[1];
        else
          Y=I[0];
      end
    end
  end

endmodule
module mux81c (I,S,Y);

  input [0:7] I;
  wire [0:7] I;

  input [0:2] S;
  wire [0:2] S;
  output Y;
  reg Y;

  wire A,B,C;





  always @(S or I)
  begin

    if(S[0]==1)
    begin
      if(S[1]==1)
      begin
        if(S[2]==1)
          Y=I[7];
        else
          Y=I[6];
      end
      else
      begin
      if(S[2]==1)
        Y=I[5];
      else
        Y=I[4];
      end
    end
    else
    begin
      if(S[1]==1)
      begin
        if(S[2]==1)
          Y=I[3];
        else
        begin
          $display("time=%0d,S=%b,I2=%b, Y=%b",$time,S,I[2],Y);
          Y=I[2];
          $display("time=%0d,S=%b,I2=%b, Y=%b",$time,S,I[2],Y);
        end
      end
      else
        begin
        if(S[2]==1)
          Y=I[1];
        else
          Y=I[0];
      end
    end
  end

endmodule