data/full_repos/permissive/111393021/test/CLA_tb.v
 line:89: before: "reset"
1: b'%Warning-STMTDLY: data/full_repos/permissive/111393021/test/CLA_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n always begin #(30/2) clk = ~clk; end\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:82: Unsupported or unknown PLI call: $fsdbDumpfile\n   $fsdbDumpfile("CLA.fsdb");\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:84: Unsupported or unknown PLI call: $fsdbDumpvars\n  $fsdbDumpvars;\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:89: syntax error, unexpected \'@\'\n    @(negedge clk)  reset = 1\'b1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/CLA_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #(30*2);    reset = 1\'b0; \n    ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:91: syntax error, unexpected \'@\'\n    @(negedge clk)  gray_ready = 1\'b1; \n    ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:111: syntax error, unexpected \'@\'\n       @(negedge clk); \n       ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:114: syntax error, unexpected \'@\'\n  @(posedge clk) result_compare = 1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/CLA_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #(30*3); \n  ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:122: Unsupported: wait statements\n  wait( finish ) ;\n  ^~~~\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:123: syntax error, unexpected \'@\'\n  @(posedge clk); @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/111393021/test/CLA_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #10000000 ;\n  ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:175: syntax error, unexpected \'@\'\n       @(posedge over)      \n       ^\n%Error: data/full_repos/permissive/111393021/test/CLA_tb.v:192: syntax error, unexpected \'#\'\n       #(30/2); $finish;\n       ^\n%Error: Exiting due to 10 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ipf_mem (ipf_valid, ipf_data, ipf_addr, clk);

	input	ipf_valid;
	input	[13:0] ipf_addr;
	input	[7:0]  ipf_data;
	input	clk;

	reg [7:0] ipf_M [0:16383];
	integer i;

	initial begin
		for (i=0; i<=16383; i=i+1) ipf_M[i] = 0;
	end

	always@(negedge clk) 
		if (ipf_valid) ipf_M[ ipf_addr ] <= ipf_data;

endmodule
module ipf_mem (ipf_valid, ipf_data, ipf_addr, clk);


	input	ipf_valid;
	input	[13:0] ipf_addr;
	input	[7:0]  ipf_data;
	input	clk;

	reg [7:0] ipf_M [0:16383];
	integer i;

	initial begin
		for (i=0; i<=16383; i=i+1) ipf_M[i] = 0;
	end

	always@(negedge clk) 
		if (ipf_valid) ipf_M[ ipf_addr ] <= ipf_data;

endmodule