data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v
None: at end of input
1: b'%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:67: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175132042/behavioral/wb_master,data/full_repos/permissive/175132042/timescale.v\n             data/full_repos/permissive/175132042/behavioral/wb_master,data/full_repos/permissive/175132042/timescale.v.v\n             data/full_repos/permissive/175132042/behavioral/wb_master,data/full_repos/permissive/175132042/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:111: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:143: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:151: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:152: syntax error, unexpected \'@\'\n         while(~ack & ~err) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:153: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:186: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:187: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:194: syntax error, unexpected \'@\'\n           @(posedge clk);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:195: Unsupported: Ignoring delay on this delayed statement.\n           #1;\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:201: syntax error, unexpected \'@\'\n         while(~ack & ~err) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:202: Unsupported: Ignoring delay on this delayed statement.\n         #2;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:211: syntax error, unexpected \'@\'\n           @(posedge clk);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:212: Unsupported: Ignoring delay on this delayed statement.\n           #1;\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:218: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:219: syntax error, unexpected \'@\'\n         while(~ack & ~err) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:220: Unsupported: Ignoring delay on this delayed statement.\n         #2;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:227: syntax error, unexpected \'@\'\n           @(posedge clk);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:228: Unsupported: Ignoring delay on this delayed statement.\n           #1;\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:234: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:235: syntax error, unexpected \'@\'\n         while(~ack & ~err) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:236: Unsupported: Ignoring delay on this delayed statement.\n         #2;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:244: syntax error, unexpected \'@\'\n           @(posedge clk);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:245: Unsupported: Ignoring delay on this delayed statement.\n           #1;\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:251: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:252: syntax error, unexpected \'@\'\n         while(~ack & ~err) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:253: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:282: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:289: syntax error, unexpected \'@\'\n             @(posedge clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:290: Unsupported: Ignoring delay on this delayed statement.\n             #1;\n             ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:297: syntax error, unexpected \'@\'\n           if(n!=0) @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:298: syntax error, unexpected \'@\'\n           while(~ack & ~err) @(posedge clk);\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:299: Unsupported: Ignoring delay on this delayed statement.\n           #2;\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:332: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:333: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:337: syntax error, unexpected \'@\'\n         repeat(delay) @(posedge clk);\n                       ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:343: syntax error, unexpected \'@\'\n           while(~ack & ~err) @(posedge clk);\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:346: Unsupported: Ignoring delay on this delayed statement.\n           #2;\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:353: syntax error, unexpected \'@\'\n             @(posedge clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:354: Unsupported: Ignoring delay on this delayed statement.\n             #1;\n             ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:362: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:363: syntax error, unexpected \'@\'\n         while(~ack & ~err) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:366: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:381: syntax error, unexpected \'@\'\n             @(posedge clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:382: Unsupported: Ignoring delay on this delayed statement.\n             #1;\n             ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:390: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:391: syntax error, unexpected \'@\'\n           while(~ack & ~err) @(posedge clk);\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:392: Unsupported: Ignoring delay on this delayed statement.\n           #2;\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:426: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:427: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:437: syntax error, unexpected \'@\'\n             @(posedge clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:438: Unsupported: Ignoring delay on this delayed statement.\n             #1;\n             ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:445: syntax error, unexpected \'@\'\n           @(posedge clk);\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:446: syntax error, unexpected \'@\'\n           while(~ack & ~err) @(posedge clk);\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:447: Unsupported: Ignoring delay on this delayed statement.\n           #2;\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:457: syntax error, unexpected \'@\'\n         repeat(delay) @(posedge clk);\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:458: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:466: syntax error, unexpected \'@\'\n           while(~ack & ~err) @(posedge clk);\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:469: Unsupported: Ignoring delay on this delayed statement.\n           #2;\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:476: syntax error, unexpected \'@\'\n             @(posedge clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:477: Unsupported: Ignoring delay on this delayed statement.\n             #1;\n             ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:485: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:486: syntax error, unexpected \'@\'\n         while(~ack & ~err) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:490: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:517: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:525: syntax error, unexpected \'@\'\n         while(~ack & ~err) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:527: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:561: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:562: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:567: syntax error, unexpected \'@\'\n         repeat(delay) @(posedge clk);\n                       ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:571: syntax error, unexpected \'@\'\n         while(~ack & ~err) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:573: Unsupported: Ignoring delay on this delayed statement.\n         #2;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:580: syntax error, unexpected \'@\'\n           @(posedge clk);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:581: Unsupported: Ignoring delay on this delayed statement.\n           #1;\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:588: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:589: syntax error, unexpected \'@\'\n         while(~ack & ~err) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:591: Unsupported: Ignoring delay on this delayed statement.\n         #2;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:598: syntax error, unexpected \'@\'\n           @(posedge clk);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:599: Unsupported: Ignoring delay on this delayed statement.\n           #1;\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:607: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:608: syntax error, unexpected \'@\'\n         while(~ack & ~err) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:610: Unsupported: Ignoring delay on this delayed statement.\n         #2;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:617: syntax error, unexpected \'@\'\n           @(posedge clk);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:618: Unsupported: Ignoring delay on this delayed statement.\n           #1;\n           ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:625: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:626: syntax error, unexpected \'@\'\n         while(~ack & ~err) @(posedge clk);\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:628: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:653: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_master/wb_master_model.v:657: syntax error, unexpected \'@\'\n         repeat(delay) @(posedge clk);\n                       ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
   
   input		clk, rst;
   output [31:0] adr;
   input [31:0]  din;
   output [31:0] dout;
   output        cyc, stb;
   output [3:0]  sel;
   output        we;
   input         ack, err, rty;
   




   
   parameter mem_size = 4096;
   
   reg [31:0]    adr;
   reg [31:0]    dout;
   reg           cyc, stb;
   reg [3:0]     sel;
   reg           we;
   
   reg [31:0]    mem[mem_size:0];
   integer       cnt;
   




   
   initial
     begin


	    adr = 32'hffff_ffff;
	    dout = 32'hxxxx_xxxx;
	    cyc = 0;
	    stb = 0;
	    sel = 4'hx;
	    we = 1'hx;
	    cnt = 0;
	    #1;
	    $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
     end
   
   
   
   task mem_fill;
      
      integer n;
      begin
         cnt = 0;
         cnt = 0;
         for(n=0;n<mem_size;n=n+1)
           begin
	          mem[n] = $random;
           end
      end
   endtask
   




   
   task wb_wr1;
      input	[31:0]	a;
      input [3:0]   s;
      input [31:0]  d;
      
      begin
         

         #1;
         adr = a;
         dout = d;
         cyc = 1;
         stb = 1;
         we=1;
         sel = s;
         
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         #1;
         cyc=0;
         stb=0;




         we = 1'h0;
         sel = 4'h0;
         adr = $random;
         dout = $random;
	     
      end
   endtask
   




   
   task wb_wr4;
      input	[31:0]	a;
      input [3:0]   s;
      input         delay;
      input [31:0]  d1;
      input [31:0]  d2;
      input [31:0]  d3;
      input [31:0]  d4;
      
      integer		delay;
      
      begin
         
         @(posedge clk);
         #1;
         cyc = 1;
         sel = s;
         
         adr = $random;
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         adr = a;
         dout = d1;
         stb = 1;
         we=1;
         while(~ack & ~err)	@(posedge clk);
         #2;
         stb=0;
         we=1'bx;
         dout = 32'hxxxx_xxxx;
         adr = $random;
         
         
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         stb=1;
         adr = a+4;
         dout = d2;
         we=1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         #2;
         stb=0;
         we=1'bx;
         dout = 32'hxxxx_xxxx;
         
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         stb=1;
         adr = a+8;
         dout = d3;
         we=1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         #2;
         stb=0;
         we=1'bx;
         dout = 32'hxxxx_xxxx;
         adr = $random;
         
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         stb=1;
         adr = a+12;
         dout = d4;
         we=1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         #1;
         stb=0;
         cyc=0;
         
         adr = 32'hxxxx_xxxx;
         adr = $random;


         dout = 32'hxxxx_xxxx;
         we = 1'hx;
         sel = 4'hx;
         
      end
   endtask
   
   
   task wb_wr_mult;
      input	[31:0]	a;
      input [3:0]   s;
      input         delay;
      input         count;
      
      integer		delay;
      integer		count;
      integer		n;
      
      begin
         

         #1;
         cyc = 1;
         adr = $random;
         for(n=0;n<count;n=n+1)
           begin
	          repeat(delay)
	            begin
		           @(posedge clk);
		           #1;
	            end
	          adr = a + (n*4);
	          dout = mem[n + cnt];
	          stb = 1;
	          we=1;
	          sel = s;
	          if(n!=0)	@(posedge clk);
	          while(~ack & ~err)	@(posedge clk);
	          #2;
	          stb=0;
	          we=1'bx;
	          sel = 4'hx;
	          dout = 32'hxxxx_xxxx;

	          adr = $random;
           end
         
         cyc=0;
         
         adr = 32'hxxxx_xxxx;

         
         cnt = cnt + count;
      end
   endtask
   
   
   task wb_rmw;
      input	[31:0]	a;
      input [3:0]   s;
      input         delay;
      input         rcount;
      input         wcount;
      
      integer		delay;
      integer		rcount;
      integer		wcount;
      integer		n;
      
      begin
         
         @(posedge clk);
         #1;
         cyc = 1;
         we = 0;
         sel = s;
         repeat(delay)	@(posedge clk);
         
         for(n=0;n<rcount-1;n=n+1)
           begin
	          adr = a + (n*4);
	          stb = 1;
	          while(~ack & ~err)	@(posedge clk);
	          mem[n + cnt] = din;

	          #2;
	          stb=0;
	          we = 1'hx;
	          sel = 4'hx;
	          adr = 32'hxxxx_xxxx;
	          repeat(delay)
	            begin
		           @(posedge clk);
		           #1;
	            end
	          we = 0;
	          sel = s;
           end
         
         adr = a+(n*4);
         stb = 1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         mem[n + cnt] = din;

         #1;
         stb=0;
         we = 1'hx;
         sel = 4'hx;
         adr = 32'hxxxx_xxxx;
         
         cnt = cnt + rcount;
         

         
         
         for(n=0;n<wcount;n=n+1)
           begin
	          repeat(delay)
	            begin
		           @(posedge clk);
		           #1;
	            end
	          adr = a + (n*4);
	          dout = mem[n + cnt];
	          stb = 1;
	          we=1;
	          sel = s;

		      @(posedge clk);
	          while(~ack & ~err)	@(posedge clk);
	          #2;
	          stb=0;
	          we=1'bx;
	          sel = 4'hx;
	          dout = 32'hxxxx_xxxx;
	          adr = 32'hxxxx_xxxx;
           end
         
         cyc=0;
         
         adr = 32'hxxxx_xxxx;

         
         cnt = cnt + wcount;
      end
   endtask
   
   
   
   
   task wb_wmr;
      input	[31:0]	a;
      input [3:0]   s;
      input         delay;
      input         rcount;
      input         wcount;
      
      integer		delay;
      integer		rcount;
      integer		wcount;
      integer		n;
      
      begin
         
         @(posedge clk);
         #1;
         cyc = 1;
         we = 1'bx;
         sel = 4'hx;
         sel = s;
         
         for(n=0;n<wcount;n=n+1)
           begin
	          repeat(delay)
	            begin
		           @(posedge clk);
		           #1;
	            end
	          adr = a + (n*4);
	          dout = mem[n + cnt];
	          stb = 1;
	          we=1;
	          sel = s;
	          @(posedge clk);
	          while(~ack & ~err)	@(posedge clk);
	          #2;
	          stb=0;
	          we=1'bx;
	          sel = 4'hx;
	          dout = 32'hxxxx_xxxx;
	          adr = 32'hxxxx_xxxx;
           end
         
         cnt = cnt + wcount;
         stb=0;
         repeat(delay)	@(posedge clk);
         #1;
         
         sel = s;
         we = 0;
         for(n=0;n<rcount-1;n=n+1)
           begin
	          adr = a + (n*4);
	          stb = 1;
	          while(~ack & ~err)	@(posedge clk);
	          mem[n + cnt] = din;

	          #2;
	          stb=0;
	          we = 1'hx;
	          sel = 4'hx;
	          adr = 32'hxxxx_xxxx;
	          repeat(delay)
	            begin
		           @(posedge clk);
		           #1;
	            end
	          we = 0;
	          sel = s;
           end
         
         adr = a+(n*4);
         stb = 1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         mem[n + cnt] = din;
         cnt = cnt + rcount;

         #1;
         
         cyc = 0;
         stb = 0;
         we  = 1'hx;
         sel = 4'hx;
         adr = 32'hxxxx_xxxx;
         
      end
   endtask
   
   
   
   




   
   task wb_rd1;
      input	[31:0]	a;
      input [3:0]   s;
      output [31:0] d;
      
      begin
         

         #1;
         adr = a;
         cyc = 1;
         stb = 1;
         we  = 0;
         sel = s;
         

         while(~ack & ~err)	@(posedge clk);
         d = din;
         #1;
         cyc=0;
         stb=0;


         adr = 32'hffff_ffff;

         we = 1'h0;
         sel = 4'h0;
         adr = $random;
         dout = $random;
	     
      end
   endtask
   
   




   
   
   task wb_rd4;
      input	[31:0]	a;
      input [3:0]   s;
      input         delay;
      output [31:0] d1;
      output [31:0] d2;
      output [31:0] d3;
      output [31:0] d4;
      
      integer		delay;
      begin
         
         @(posedge clk);
         #1;
         cyc = 1;
         we = 0;
         adr = $random;
         sel = s;
         repeat(delay)	@(posedge clk);
         
         adr = a;
         stb = 1;
         while(~ack & ~err)	@(posedge clk);
         d1 = din;
         #2;
         stb=0;
         we = 1'hx;
         sel = 4'hx;
         adr = $random;
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         we = 0;
         sel = s;
         
         adr = a+4;
         stb = 1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         d2 = din;
         #2;
         stb=0;
         we = 1'hx;
         sel = 4'hx;
         adr = $random;
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         we = 0;
         sel = s;
         
         
         adr = a+8;
         stb = 1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         d3 = din;
         #2;
         stb=0;
         we = 1'hx;
         sel = 4'hx;
         adr = $random;
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         we = 0;
         sel = s;
         
         adr = a+12;
         stb = 1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         d4 = din;
         #1;
         stb=0;
         cyc=0;
         we = 1'hx;
         sel = 4'hx;
         adr = 32'hffff_ffff;
         adr = $random;
      end
   endtask
   
   
   
   task wb_rd_mult;
      input	[31:0]	a;
      input [3:0]   s;
      input         delay;
      input         count;
      
      integer		delay;
      integer		count;
      integer		n;
      
      begin
         

         #1;
         cyc = 1;
         we = 0;
         sel = s;
         repeat(delay)	@(posedge clk);
         
         for(n=0;n<count-1;n=n+1)
           begin
	          adr = a + (n*4);
	          stb = 1;
	          while(~ack & ~err)	@(posedge clk);
	          mem[n + cnt] = din;
	          #2;
	          stb=0;
	          we = 1'hx;
	          sel = 4'hx;

	          adr = $random;
	          repeat(delay)
	            begin
		           @(posedge clk);
		           #1;
	            end
	          we = 0;
	          sel = s;
           end
         
         adr = a+(n*4);
         stb = 1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         mem[n + cnt] = din;
         #1;
         stb=0;
         cyc=0;
         we = 1'hx;
         sel = 4'hx;


         adr = $random;
         
         cnt = cnt + count;
      end
   endtask
   
endmodule
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);

   
   input		clk, rst;
   output [31:0] adr;
   input [31:0]  din;
   output [31:0] dout;
   output        cyc, stb;
   output [3:0]  sel;
   output        we;
   input         ack, err, rty;
   




   
   parameter mem_size = 4096;
   
   reg [31:0]    adr;
   reg [31:0]    dout;
   reg           cyc, stb;
   reg [3:0]     sel;
   reg           we;
   
   reg [31:0]    mem[mem_size:0];
   integer       cnt;
   




   
   initial
     begin


	    adr = 32'hffff_ffff;
	    dout = 32'hxxxx_xxxx;
	    cyc = 0;
	    stb = 0;
	    sel = 4'hx;
	    we = 1'hx;
	    cnt = 0;
	    #1;
	    $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
     end
   
   
   
   task mem_fill;
      
      integer n;
      begin
         cnt = 0;
         cnt = 0;
         for(n=0;n<mem_size;n=n+1)
           begin
	          mem[n] = $random;
           end
      end
   endtask
   




   
   task wb_wr1;
      input	[31:0]	a;
      input [3:0]   s;
      input [31:0]  d;
      
      begin
         

         #1;
         adr = a;
         dout = d;
         cyc = 1;
         stb = 1;
         we=1;
         sel = s;
         
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         #1;
         cyc=0;
         stb=0;




         we = 1'h0;
         sel = 4'h0;
         adr = $random;
         dout = $random;
	     
      end
   endtask
   




   
   task wb_wr4;
      input	[31:0]	a;
      input [3:0]   s;
      input         delay;
      input [31:0]  d1;
      input [31:0]  d2;
      input [31:0]  d3;
      input [31:0]  d4;
      
      integer		delay;
      
      begin
         
         @(posedge clk);
         #1;
         cyc = 1;
         sel = s;
         
         adr = $random;
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         adr = a;
         dout = d1;
         stb = 1;
         we=1;
         while(~ack & ~err)	@(posedge clk);
         #2;
         stb=0;
         we=1'bx;
         dout = 32'hxxxx_xxxx;
         adr = $random;
         
         
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         stb=1;
         adr = a+4;
         dout = d2;
         we=1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         #2;
         stb=0;
         we=1'bx;
         dout = 32'hxxxx_xxxx;
         
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         stb=1;
         adr = a+8;
         dout = d3;
         we=1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         #2;
         stb=0;
         we=1'bx;
         dout = 32'hxxxx_xxxx;
         adr = $random;
         
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         stb=1;
         adr = a+12;
         dout = d4;
         we=1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         #1;
         stb=0;
         cyc=0;
         
         adr = 32'hxxxx_xxxx;
         adr = $random;


         dout = 32'hxxxx_xxxx;
         we = 1'hx;
         sel = 4'hx;
         
      end
   endtask
   
   
   task wb_wr_mult;
      input	[31:0]	a;
      input [3:0]   s;
      input         delay;
      input         count;
      
      integer		delay;
      integer		count;
      integer		n;
      
      begin
         

         #1;
         cyc = 1;
         adr = $random;
         for(n=0;n<count;n=n+1)
           begin
	          repeat(delay)
	            begin
		           @(posedge clk);
		           #1;
	            end
	          adr = a + (n*4);
	          dout = mem[n + cnt];
	          stb = 1;
	          we=1;
	          sel = s;
	          if(n!=0)	@(posedge clk);
	          while(~ack & ~err)	@(posedge clk);
	          #2;
	          stb=0;
	          we=1'bx;
	          sel = 4'hx;
	          dout = 32'hxxxx_xxxx;

	          adr = $random;
           end
         
         cyc=0;
         
         adr = 32'hxxxx_xxxx;

         
         cnt = cnt + count;
      end
   endtask
   
   
   task wb_rmw;
      input	[31:0]	a;
      input [3:0]   s;
      input         delay;
      input         rcount;
      input         wcount;
      
      integer		delay;
      integer		rcount;
      integer		wcount;
      integer		n;
      
      begin
         
         @(posedge clk);
         #1;
         cyc = 1;
         we = 0;
         sel = s;
         repeat(delay)	@(posedge clk);
         
         for(n=0;n<rcount-1;n=n+1)
           begin
	          adr = a + (n*4);
	          stb = 1;
	          while(~ack & ~err)	@(posedge clk);
	          mem[n + cnt] = din;

	          #2;
	          stb=0;
	          we = 1'hx;
	          sel = 4'hx;
	          adr = 32'hxxxx_xxxx;
	          repeat(delay)
	            begin
		           @(posedge clk);
		           #1;
	            end
	          we = 0;
	          sel = s;
           end
         
         adr = a+(n*4);
         stb = 1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         mem[n + cnt] = din;

         #1;
         stb=0;
         we = 1'hx;
         sel = 4'hx;
         adr = 32'hxxxx_xxxx;
         
         cnt = cnt + rcount;
         

         
         
         for(n=0;n<wcount;n=n+1)
           begin
	          repeat(delay)
	            begin
		           @(posedge clk);
		           #1;
	            end
	          adr = a + (n*4);
	          dout = mem[n + cnt];
	          stb = 1;
	          we=1;
	          sel = s;

		      @(posedge clk);
	          while(~ack & ~err)	@(posedge clk);
	          #2;
	          stb=0;
	          we=1'bx;
	          sel = 4'hx;
	          dout = 32'hxxxx_xxxx;
	          adr = 32'hxxxx_xxxx;
           end
         
         cyc=0;
         
         adr = 32'hxxxx_xxxx;

         
         cnt = cnt + wcount;
      end
   endtask
   
   
   
   
   task wb_wmr;
      input	[31:0]	a;
      input [3:0]   s;
      input         delay;
      input         rcount;
      input         wcount;
      
      integer		delay;
      integer		rcount;
      integer		wcount;
      integer		n;
      
      begin
         
         @(posedge clk);
         #1;
         cyc = 1;
         we = 1'bx;
         sel = 4'hx;
         sel = s;
         
         for(n=0;n<wcount;n=n+1)
           begin
	          repeat(delay)
	            begin
		           @(posedge clk);
		           #1;
	            end
	          adr = a + (n*4);
	          dout = mem[n + cnt];
	          stb = 1;
	          we=1;
	          sel = s;
	          @(posedge clk);
	          while(~ack & ~err)	@(posedge clk);
	          #2;
	          stb=0;
	          we=1'bx;
	          sel = 4'hx;
	          dout = 32'hxxxx_xxxx;
	          adr = 32'hxxxx_xxxx;
           end
         
         cnt = cnt + wcount;
         stb=0;
         repeat(delay)	@(posedge clk);
         #1;
         
         sel = s;
         we = 0;
         for(n=0;n<rcount-1;n=n+1)
           begin
	          adr = a + (n*4);
	          stb = 1;
	          while(~ack & ~err)	@(posedge clk);
	          mem[n + cnt] = din;

	          #2;
	          stb=0;
	          we = 1'hx;
	          sel = 4'hx;
	          adr = 32'hxxxx_xxxx;
	          repeat(delay)
	            begin
		           @(posedge clk);
		           #1;
	            end
	          we = 0;
	          sel = s;
           end
         
         adr = a+(n*4);
         stb = 1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         mem[n + cnt] = din;
         cnt = cnt + rcount;

         #1;
         
         cyc = 0;
         stb = 0;
         we  = 1'hx;
         sel = 4'hx;
         adr = 32'hxxxx_xxxx;
         
      end
   endtask
   
   
   
   




   
   task wb_rd1;
      input	[31:0]	a;
      input [3:0]   s;
      output [31:0] d;
      
      begin
         

         #1;
         adr = a;
         cyc = 1;
         stb = 1;
         we  = 0;
         sel = s;
         

         while(~ack & ~err)	@(posedge clk);
         d = din;
         #1;
         cyc=0;
         stb=0;


         adr = 32'hffff_ffff;

         we = 1'h0;
         sel = 4'h0;
         adr = $random;
         dout = $random;
	     
      end
   endtask
   
   




   
   
   task wb_rd4;
      input	[31:0]	a;
      input [3:0]   s;
      input         delay;
      output [31:0] d1;
      output [31:0] d2;
      output [31:0] d3;
      output [31:0] d4;
      
      integer		delay;
      begin
         
         @(posedge clk);
         #1;
         cyc = 1;
         we = 0;
         adr = $random;
         sel = s;
         repeat(delay)	@(posedge clk);
         
         adr = a;
         stb = 1;
         while(~ack & ~err)	@(posedge clk);
         d1 = din;
         #2;
         stb=0;
         we = 1'hx;
         sel = 4'hx;
         adr = $random;
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         we = 0;
         sel = s;
         
         adr = a+4;
         stb = 1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         d2 = din;
         #2;
         stb=0;
         we = 1'hx;
         sel = 4'hx;
         adr = $random;
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         we = 0;
         sel = s;
         
         
         adr = a+8;
         stb = 1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         d3 = din;
         #2;
         stb=0;
         we = 1'hx;
         sel = 4'hx;
         adr = $random;
         repeat(delay)
           begin
	          @(posedge clk);
	          #1;
           end
         we = 0;
         sel = s;
         
         adr = a+12;
         stb = 1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         d4 = din;
         #1;
         stb=0;
         cyc=0;
         we = 1'hx;
         sel = 4'hx;
         adr = 32'hffff_ffff;
         adr = $random;
      end
   endtask
   
   
   
   task wb_rd_mult;
      input	[31:0]	a;
      input [3:0]   s;
      input         delay;
      input         count;
      
      integer		delay;
      integer		count;
      integer		n;
      
      begin
         

         #1;
         cyc = 1;
         we = 0;
         sel = s;
         repeat(delay)	@(posedge clk);
         
         for(n=0;n<count-1;n=n+1)
           begin
	          adr = a + (n*4);
	          stb = 1;
	          while(~ack & ~err)	@(posedge clk);
	          mem[n + cnt] = din;
	          #2;
	          stb=0;
	          we = 1'hx;
	          sel = 4'hx;

	          adr = $random;
	          repeat(delay)
	            begin
		           @(posedge clk);
		           #1;
	            end
	          we = 0;
	          sel = s;
           end
         
         adr = a+(n*4);
         stb = 1;
         @(posedge clk);
         while(~ack & ~err)	@(posedge clk);
         mem[n + cnt] = din;
         #1;
         stb=0;
         cyc=0;
         we = 1'hx;
         sel = 4'hx;


         adr = $random;
         
         cnt = cnt + count;
      end
   endtask
   
endmodule