data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/hdl/one_second_clk.v
data/verilator_xmls/e28e8827-f52f-4b54-a7c9-24c62597e784.xml
module one_seond_clk(Reset,Clk,Count,Cout);
input Reset,Clk;
output reg[9:0]Count;
output reg Cout;
always@(posedge Clk)
 if(Reset)begin Count=0;Cout=0;end
 else if(Count==999)begin Count=0;Cout=1;end
 else begin Count=Count+1;Cout=0;end
endmodule
module one_seond_clk(Reset,Clk,Count,Cout);

input Reset,Clk;
output reg[9:0]Count;
output reg Cout;
always@(posedge Clk)
 if(Reset)begin Count=0;Cout=0;end
 else if(Count==999)begin Count=0;Cout=1;end
 else begin Count=Count+1;Cout=0;end
endmodule