data/full_repos/permissive/194847941/demo/8_VGA_Demo/source/rtl/Clk_div.v
1: b"%Error: data/full_repos/permissive/194847941/demo/8_VGA_Demo/source/rtl/Clk_div.v:12: Cannot find file containing module: 'PLL'\nPLL uut\n^~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/8_VGA_Demo/source/rtl,data/full_repos/permissive/194847941/PLL\n             data/full_repos/permissive/194847941/demo/8_VGA_Demo/source/rtl,data/full_repos/permissive/194847941/PLL.v\n             data/full_repos/permissive/194847941/demo/8_VGA_Demo/source/rtl,data/full_repos/permissive/194847941/PLL.sv\n             PLL\n             PLL.v\n             PLL.sv\n             obj_dir/PLL\n             obj_dir/PLL.v\n             obj_dir/PLL.sv\n%Error: Exiting due to 1 error(s)\n"
module Clk_div
( 
	input  wire		clk,
	input  wire		rst_n,

	output wire 	clk_div
);

wire	Clk_Lock;

PLL uut
(
	.refclk		(clk		),
	.reset		(!rst_n		),
	
	.clk0_out	(clk_div	),
	.extlock	(Clk_Lock	)
);

endmodule
module Clk_div
( 
	input  wire		clk,
	input  wire		rst_n,

	output wire 	clk_div
);


wire	Clk_Lock;

PLL uut
(
	.refclk		(clk		),
	.reset		(!rst_n		),
	
	.clk0_out	(clk_div	),
	.extlock	(Clk_Lock	)
);

endmodule