data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v
None: at end of input
1: b'%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:20: Cannot find include file: RV2T_common.vh\n`include "RV2T_common.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158824477/source/Intel/PulseRain_M10,data/full_repos/permissive/158824477/RV2T_common.vh\n             data/full_repos/permissive/158824477/source/Intel/PulseRain_M10,data/full_repos/permissive/158824477/RV2T_common.vh.v\n             data/full_repos/permissive/158824477/source/Intel/PulseRain_M10,data/full_repos/permissive/158824477/RV2T_common.vh.sv\n             RV2T_common.vh\n             RV2T_common.vh.v\n             RV2T_common.vh.sv\n             obj_dir/RV2T_common.vh\n             obj_dir/RV2T_common.vh.v\n             obj_dir/RV2T_common.vh.sv\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:21: Cannot find include file: debug_coprocessor.vh\n`include "debug_coprocessor.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:22: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:53: Define or directive not defined: \'`DEBUG_PRAM_ADDR_WIDTH\'\n        wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0]                   pram_read_addr;\n              ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:54: Define or directive not defined: \'`DEBUG_PRAM_ADDR_WIDTH\'\n        wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0]                   pram_write_addr;\n              ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:59: Define or directive not defined: \'`MEM_ADDR_BITS\'\n        wire  [`MEM_ADDR_BITS - 1 : 0]                          ocd_rw_addr;\n               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:60: Define or directive not defined: \'`XLEN\'\n        wire  [`XLEN - 1 : 0]                                   ocd_write_word;\n               ^~~~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:63: Define or directive not defined: \'`XLEN\'\n        wire  [`XLEN - 1 : 0]                                   ocd_mem_word_out;      \n               ^~~~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:66: Define or directive not defined: \'`DEBUG_DATA_WIDTH\'\n        wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0]  cpu_start_addr;\n              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:66: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n        wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0]  cpu_start_addr;\n                                ^\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:66: Define or directive not defined: \'`DEBUG_FRAME_DATA_LEN\'\n        wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0]  cpu_start_addr;\n                                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:119: Define or directive not defined: \'`DEFAULT_STACK_ADDR\'\n            .ocd_reg_write_data (`DEFAULT_STACK_ADDR),\n                                 ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:139: Define or directive not defined: \'`DISABLE_OCD\'\n            if (`DISABLE_OCD == 0) begin\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:139: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\n            if (`DISABLE_OCD == 0) begin\n                             ^~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:141: Define or directive not defined: \'`UART_TX_BAUD_PERIOD\'\n                debug_coprocessor_wrapper #(.BAUD_PERIOD (`UART_TX_BAUD_PERIOD)) ocd_i (\n                                                          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:166: syntax error, unexpected end\n            end\n            ^~~\n%Error: data/full_repos/permissive/158824477/source/Intel/PulseRain_M10/Reindeer.v:204: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module Reindeer (




        input   wire                                            osc_in,                          
        input   wire                                            reset_button,                      
  




        output  reg                                             TXD, 
        input   wire                                            RXD,
    



        output wire                                             processor_active
        
);




        wire                                                    debug_uart_tx_sel_ocd1_cpu0;
        wire                                                    cpu_reset;
        wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0]                   pram_read_addr;
        wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0]                   pram_write_addr;
        
        wire                                                    ocd_read_enable;
        wire                                                    ocd_write_enable;
        
        wire  [`MEM_ADDR_BITS - 1 : 0]                          ocd_rw_addr;
        wire  [`XLEN - 1 : 0]                                   ocd_write_word;
        
        wire                                                    ocd_mem_enable_out;
        wire  [`XLEN - 1 : 0]                                   ocd_mem_word_out;      
        
        wire                                                      cpu_start;
        wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0]  cpu_start_addr;
       
        wire                                                      uart_tx_cpu;
        wire                                                      uart_tx_ocd;
       
        wire                                                      clk_24MHz;
        wire                                                      clk_2MHz;
        wire                                                      clk;
        
        wire                                                      pll_locked;

        wire                                                      processor_paused;
        



            
        PLL PLL_i (
            .areset (1'b0),
            .inclk0 (osc_in),
            .c0 (clk),
            .c1 (clk_24MHz),
            .c2 (clk_2MHz),
            .locked (pll_locked));
      




     
        PulseRain_RV2T_MCU PulseRain_RV2T_MCU_i (
            .clk (clk),
            .reset_n ((~cpu_reset) & pll_locked),
            .sync_reset (1'b0),

            .ocd_read_enable (ocd_read_enable),
            .ocd_write_enable (ocd_write_enable),
            
            .ocd_rw_addr (ocd_rw_addr),
            .ocd_write_word (ocd_write_word),
            
            .ocd_mem_enable_out (ocd_mem_enable_out),
            .ocd_mem_word_out (ocd_mem_word_out),        
        
            .ocd_reg_read_addr (5'd2),
            .ocd_reg_we (1'b0),
            .ocd_reg_write_addr (5'd2),
            .ocd_reg_write_data (`DEFAULT_STACK_ADDR),
        
            .TXD (uart_tx_cpu),
    
            .start (cpu_start),
            .start_address (cpu_start_addr),
        
            .processor_paused (processor_paused),
            
            .peek_pc (),
            .peek_ir () );
     
        assign processor_active = ~processor_paused;
        



        
        generate
        
            if (`DISABLE_OCD == 0) begin
            
                debug_coprocessor_wrapper #(.BAUD_PERIOD (`UART_TX_BAUD_PERIOD)) ocd_i (
                    .clk (clk),
                    .reset_n (pll_locked),
                    
                    .RXD (RXD),
                    .TXD (uart_tx_ocd),
                        
                    .pram_read_enable_in (ocd_mem_enable_out),
                    .pram_read_data_in (ocd_mem_word_out),
                    
                    .pram_read_enable_out (ocd_read_enable),
                    .pram_read_addr_out (pram_read_addr),
                    
                    .pram_write_enable_out (ocd_write_enable),
                    .pram_write_addr_out (pram_write_addr),
                    .pram_write_data_out (ocd_write_word),
                    
                    .cpu_reset (cpu_reset),
                    
                    .cpu_start (cpu_start),
                    .cpu_start_addr (cpu_start_addr),        
                    
                    .debug_uart_tx_sel_ocd1_cpu0 (debug_uart_tx_sel_ocd1_cpu0));
                
                assign ocd_rw_addr = ocd_read_enable ? pram_read_addr : pram_write_addr;
            end
            
        endgenerate
        
        always @(posedge clk, negedge pll_locked) begin : uart_proc
            if (!pll_locked) begin
                TXD <= 0;
            end else if (!debug_uart_tx_sel_ocd1_cpu0) begin
                TXD <= uart_tx_cpu;
            end else begin
                TXD <= uart_tx_ocd;
            end
        end 
     
    wire [127 : 0]      acq_data_in;
    
    assign acq_data_in [0] = debug_uart_tx_sel_ocd1_cpu0;
    assign acq_data_in [1] = cpu_reset;
    assign acq_data_in [2] = cpu_start;
    assign acq_data_in [3] = pll_locked;
    assign acq_data_in [35 : 4] = cpu_start_addr;
    assign acq_data_in [36] = ocd_write_enable;
    assign acq_data_in [37] = ocd_read_enable;
    assign acq_data_in [51 : 38] = pram_write_addr;
    assign acq_data_in [83 : 52] = ocd_write_word;
    assign acq_data_in [97 : 84] = pram_read_addr;
    assign acq_data_in [127 : 98] =  ocd_mem_word_out [29 : 0];
    
    

     
     
endmodule
module Reindeer (




        input   wire                                            osc_in,                          
        input   wire                                            reset_button,                      
  




        output  reg                                             TXD, 
        input   wire                                            RXD,
    



        output wire                                             processor_active
        
);





        wire                                                    debug_uart_tx_sel_ocd1_cpu0;
        wire                                                    cpu_reset;
        wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0]                   pram_read_addr;
        wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0]                   pram_write_addr;
        
        wire                                                    ocd_read_enable;
        wire                                                    ocd_write_enable;
        
        wire  [`MEM_ADDR_BITS - 1 : 0]                          ocd_rw_addr;
        wire  [`XLEN - 1 : 0]                                   ocd_write_word;
        
        wire                                                    ocd_mem_enable_out;
        wire  [`XLEN - 1 : 0]                                   ocd_mem_word_out;      
        
        wire                                                      cpu_start;
        wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0]  cpu_start_addr;
       
        wire                                                      uart_tx_cpu;
        wire                                                      uart_tx_ocd;
       
        wire                                                      clk_24MHz;
        wire                                                      clk_2MHz;
        wire                                                      clk;
        
        wire                                                      pll_locked;

        wire                                                      processor_paused;
        



            
        PLL PLL_i (
            .areset (1'b0),
            .inclk0 (osc_in),
            .c0 (clk),
            .c1 (clk_24MHz),
            .c2 (clk_2MHz),
            .locked (pll_locked));
      




     
        PulseRain_RV2T_MCU PulseRain_RV2T_MCU_i (
            .clk (clk),
            .reset_n ((~cpu_reset) & pll_locked),
            .sync_reset (1'b0),

            .ocd_read_enable (ocd_read_enable),
            .ocd_write_enable (ocd_write_enable),
            
            .ocd_rw_addr (ocd_rw_addr),
            .ocd_write_word (ocd_write_word),
            
            .ocd_mem_enable_out (ocd_mem_enable_out),
            .ocd_mem_word_out (ocd_mem_word_out),        
        
            .ocd_reg_read_addr (5'd2),
            .ocd_reg_we (1'b0),
            .ocd_reg_write_addr (5'd2),
            .ocd_reg_write_data (`DEFAULT_STACK_ADDR),
        
            .TXD (uart_tx_cpu),
    
            .start (cpu_start),
            .start_address (cpu_start_addr),
        
            .processor_paused (processor_paused),
            
            .peek_pc (),
            .peek_ir () );
     
        assign processor_active = ~processor_paused;
        



        
        generate
        
            if (`DISABLE_OCD == 0) begin
            
                debug_coprocessor_wrapper #(.BAUD_PERIOD (`UART_TX_BAUD_PERIOD)) ocd_i (
                    .clk (clk),
                    .reset_n (pll_locked),
                    
                    .RXD (RXD),
                    .TXD (uart_tx_ocd),
                        
                    .pram_read_enable_in (ocd_mem_enable_out),
                    .pram_read_data_in (ocd_mem_word_out),
                    
                    .pram_read_enable_out (ocd_read_enable),
                    .pram_read_addr_out (pram_read_addr),
                    
                    .pram_write_enable_out (ocd_write_enable),
                    .pram_write_addr_out (pram_write_addr),
                    .pram_write_data_out (ocd_write_word),
                    
                    .cpu_reset (cpu_reset),
                    
                    .cpu_start (cpu_start),
                    .cpu_start_addr (cpu_start_addr),        
                    
                    .debug_uart_tx_sel_ocd1_cpu0 (debug_uart_tx_sel_ocd1_cpu0));
                
                assign ocd_rw_addr = ocd_read_enable ? pram_read_addr : pram_write_addr;
            end
            
        endgenerate
        
        always @(posedge clk, negedge pll_locked) begin : uart_proc
            if (!pll_locked) begin
                TXD <= 0;
            end else if (!debug_uart_tx_sel_ocd1_cpu0) begin
                TXD <= uart_tx_cpu;
            end else begin
                TXD <= uart_tx_ocd;
            end
        end 
     
    wire [127 : 0]      acq_data_in;
    
    assign acq_data_in [0] = debug_uart_tx_sel_ocd1_cpu0;
    assign acq_data_in [1] = cpu_reset;
    assign acq_data_in [2] = cpu_start;
    assign acq_data_in [3] = pll_locked;
    assign acq_data_in [35 : 4] = cpu_start_addr;
    assign acq_data_in [36] = ocd_write_enable;
    assign acq_data_in [37] = ocd_read_enable;
    assign acq_data_in [51 : 38] = pram_write_addr;
    assign acq_data_in [83 : 52] = ocd_write_word;
    assign acq_data_in [97 : 84] = pram_read_addr;
    assign acq_data_in [127 : 98] =  ocd_mem_word_out [29 : 0];
    
    

     
     
endmodule