data/full_repos/permissive/106966316/sram_tb.v
 line:56 column:13: Illegal character "'"
1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/sram_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/106966316/sram_tb.v:34: Cannot find file containing module: \'sram\'\nsram uut(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/sram\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/sram.v\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/sram.sv\n             sram\n             sram.v\n             sram.sv\n             obj_dir/sram\n             obj_dir/sram.v\n             obj_dir/sram.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sram_tb();
reg clk;
reg CSram;
reg [7:0] Direc;
reg [31:0] Datain;
reg LeerMem;
reg EscrMem;

wire [31:0] Dataout;


sram uut(
	.clk(clk),
	.CSram(CSram),
	.Direc(Direc),
	.Datain(Datain),
	.LeerMem(LeerMem),
	.EscrMem(EscrMem),
	.Dataout(Dataout)
	
);

always begin
	clk=1'b1;
	#50;
	clk=1'b0;
	#50;
end

initial begin
	CSram=1'b1;
	EscrMem	=	1'b1;
    LeerMem	=	1'b0;
	Direc 	=	8'b_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0001;
	#100;
	
	CSram=1'b1;
	EscrMem	=	1'b0;
    LeerMem	=	1'b1;
	Direc 	=	8'b_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0001;
	#100;

	CSram=1'b1;
	EscrMem	=	1'b1;
    LeerMem	=	1'b0;
	Direc 	=	8'b_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0011;
	#100;

	CSram=1'b1;
	EscrMem	=	1'b0;
    LeerMem	=	1'b1;
	Direc 	=	8'b_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0001;
	#100;

	CSram=1'b1;
	EscrMem	=	1'b1;
    LeerMem	=	1'b0;
	Direc 	=	8'b_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0001;
	#100;
	

end

endmodule
module sram_tb();

reg clk;
reg CSram;
reg [7:0] Direc;
reg [31:0] Datain;
reg LeerMem;
reg EscrMem;

wire [31:0] Dataout;


sram uut(
	.clk(clk),
	.CSram(CSram),
	.Direc(Direc),
	.Datain(Datain),
	.LeerMem(LeerMem),
	.EscrMem(EscrMem),
	.Dataout(Dataout)
	
);

always begin
	clk=1'b1;
	#50;
	clk=1'b0;
	#50;
end

initial begin
	CSram=1'b1;
	EscrMem	=	1'b1;
    LeerMem	=	1'b0;
	Direc 	=	8'b_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0001;
	#100;
	
	CSram=1'b1;
	EscrMem	=	1'b0;
    LeerMem	=	1'b1;
	Direc 	=	8'b_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0001;
	#100;

	CSram=1'b1;
	EscrMem	=	1'b1;
    LeerMem	=	1'b0;
	Direc 	=	8'b_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0011;
	#100;

	CSram=1'b1;
	EscrMem	=	1'b0;
    LeerMem	=	1'b1;
	Direc 	=	8'b_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0001;
	#100;

	CSram=1'b1;
	EscrMem	=	1'b1;
    LeerMem	=	1'b0;
	Direc 	=	8'b_0110_0000;
	Datain	=	32'b0000_0000_0000_0000__0000_0000_0000_0001;
	#100;
	

end

endmodule