data/full_repos/permissive/159479522/clk_div.v
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data/verilator_xmls/8bd56aba-6fb2-4e42-9ccc-1e00cae152c0.xml
module clk_div(clk,clk_sec,clk_KHZ,clk_buzzer);
input  wire clk;
output reg  clk_KHZ=0;
output reg  clk_sec=0;
output reg  clk_buzzer=0;
reg   [35:0]counter1,counter2,counter3;
    always@(posedge clk)      
    begin   
    if(counter1>=9999)   begin    
    counter1=0;
    clk_KHZ=~clk_KHZ;    
      end
    else  counter1=counter1+1;
    end
    
    always@(posedge clk)
    begin   
    if(counter2>=49999999)   begin
    counter2=0;
    clk_sec=~clk_sec;
      end
    else  counter2=counter2+1;
    end
    
     always@(posedge clk)      
       begin   
       if(counter3>=125_000_000)   begin    
       counter3=0;
       clk_buzzer=~clk_buzzer;    
         end
       else  counter3=counter3+1;
       end
endmodule
module clk_div(clk,clk_sec,clk_KHZ,clk_buzzer);

input  wire clk;
output reg  clk_KHZ=0;
output reg  clk_sec=0;
output reg  clk_buzzer=0;
reg   [35:0]counter1,counter2,counter3;
    always@(posedge clk)      
    begin   
    if(counter1>=9999)   begin    
    counter1=0;
    clk_KHZ=~clk_KHZ;    
      end
    else  counter1=counter1+1;
    end
    
    always@(posedge clk)
    begin   
    if(counter2>=49999999)   begin
    counter2=0;
    clk_sec=~clk_sec;
      end
    else  counter2=counter2+1;
    end
    
     always@(posedge clk)      
       begin   
       if(counter3>=125_000_000)   begin    
       counter3=0;
       clk_buzzer=~clk_buzzer;    
         end
       else  counter3=counter3+1;
       end
endmodule