data/full_repos/permissive/117026779/sim/TestDemux.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/TestDemux.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/TestDemux.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/TestDemux.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/TestDemux.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/TestDemux.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/TestDemux.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/TestDemux.v:98: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/TestDemux.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/TestDemux.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: data/full_repos/permissive/117026779/sim/TestDemux.v:33: Cannot find file containing module: \'DEMUX\'\nDEMUX #(8, 2) D0 (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/DEMUX\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/DEMUX.v\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/DEMUX.sv\n             DEMUX\n             DEMUX.v\n             DEMUX.sv\n             obj_dir/DEMUX\n             obj_dir/DEMUX.v\n             obj_dir/DEMUX.sv\n%Error: data/full_repos/permissive/117026779/sim/TestDemux.v:64: Cannot find file containing module: \'DECODER\'\nDECODER #(3) D1 (\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/sim/TestDemux.v:77: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                       : ... In instance TestDemux\n        d_in = i;\n             ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestDemux;

reg success_flag;
integer i;

reg [7:0] select;
reg [7:0] in;
wire [7:0] a;
wire [7:0] b;

DEMUX #(8, 2) D0 (
    .select(select),
    .in(in),
    .out({b, a})
);

task TEST_DEMUX;
begin
    in = 'hAA;
    select = 0;
    #1
    if(a != 'hAA && b != 0)
    begin
    	success_flag = 0;
		$display("!!ERROR!! @ %d A == 0x%X :: B == 0x%X :: select == %d", $time, a, b, select);
    end
    #10
    select = 1;
    #1
    if(b != 'hAA && a != 0)
    begin
    	success_flag = 0;
		$display("!!ERROR!! @ %d A == 0x%X :: B == 0x%X :: select == %d", $time, a, b, select);
    end
end
endtask;

reg enable;
reg [2:0] d_in;
wire [7:0] out;

DECODER #(3) D1 (
    .enable(enable),
    .in(d_in),
    .out(out)
);

task TEST_DECODER;
begin
    enable = 1;
    d_in = 0;
    #1
    for (i = 0; i < 8; i = i + 1)
    begin
        d_in = i;
        #1
        if(out != (1 << i))
        begin
        	success_flag = 0;
    		$display("!!ERROR!! @ %d Out == 0x%X", $time, out);
        end
    end
    enable = 0;
    #1
    if(out != 0)
    begin
        success_flag = 0;
        $display("!!ERROR!! @ %d Out == 0x%X", $time, out);
    end
end
endtask;

initial begin
	success_flag = 1;
    TEST_DEMUX;
    #10
    TEST_DECODER;
    #10 $stop;
    #5 $finish;
end

endmodule
module TestDemux;


reg success_flag;
integer i;

reg [7:0] select;
reg [7:0] in;
wire [7:0] a;
wire [7:0] b;

DEMUX #(8, 2) D0 (
    .select(select),
    .in(in),
    .out({b, a})
);

task TEST_DEMUX;
begin
    in = 'hAA;
    select = 0;
    #1
    if(a != 'hAA && b != 0)
    begin
    	success_flag = 0;
		$display("!!ERROR!! @ %d A == 0x%X :: B == 0x%X :: select == %d", $time, a, b, select);
    end
    #10
    select = 1;
    #1
    if(b != 'hAA && a != 0)
    begin
    	success_flag = 0;
		$display("!!ERROR!! @ %d A == 0x%X :: B == 0x%X :: select == %d", $time, a, b, select);
    end
end
endtask;

reg enable;
reg [2:0] d_in;
wire [7:0] out;

DECODER #(3) D1 (
    .enable(enable),
    .in(d_in),
    .out(out)
);

task TEST_DECODER;
begin
    enable = 1;
    d_in = 0;
    #1
    for (i = 0; i < 8; i = i + 1)
    begin
        d_in = i;
        #1
        if(out != (1 << i))
        begin
        	success_flag = 0;
    		$display("!!ERROR!! @ %d Out == 0x%X", $time, out);
        end
    end
    enable = 0;
    #1
    if(out != 0)
    begin
        success_flag = 0;
        $display("!!ERROR!! @ %d Out == 0x%X", $time, out);
    end
end
endtask;

initial begin
	success_flag = 1;
    TEST_DEMUX;
    #10
    TEST_DECODER;
    #10 $stop;
    #5 $finish;
end

endmodule