data/full_repos/permissive/143278/ivltests/initmod2.v
 line:25: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/initmod2.v:24: Unsupported: Ignoring delay on this delayed statement.\n    initial begin clk = 0 ; forever #5 clk = ~clk ; end\n                                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/initmod2.v:25: Unsupported: Ignoring delay on this delayed statement.\n    initial #20 $finish;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/initmod2.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/initmod2.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #19;\n      ^\n%Warning-INFINITELOOP: data/full_repos/permissive/143278/ivltests/initmod2.v:24: Infinite loop (condition always true)\n                                                                               : ... In instance main\n    initial begin clk = 0 ; forever #5 clk = ~clk ; end\n                            ^~~~~~~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module  main;

    reg     clk ;
    initial begin clk = 0 ; forever #5 clk = ~clk ; end
    initial #20 $finish;

    wire    w,   ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o ;
    reg     r,   rw ;
    reg    error;


    assign  ww  =   w       ;
    assign  wr  =   r       ;
    assign  w1  =   'b1     ;
    assign  wwr =   w & r   ;
    assign  ww1 =   w & 'b1 ;
    assign  wr1 =   r & 'b1 ;

    assign  wwro=   w | r   ;
    assign  ww1o=   w | 'b1 ;
    assign  wr1o=   r | 'b1 ;

    always @(posedge clk)
          rw <= w ;

    always @(posedge clk)
      begin
        #1;
        $display("%b %b %b %b %b %b %b : %b %b %b : %b %b",
        w, ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o, r, rw );
      end

initial
   begin
      error = 0;
      #19;
      if(ww !== 1'bz)  begin
        error = 1;
        $display("FAILED - ww s/b z, is %h",ww);
      end
      if(wr !== 1'bx)  begin
        error = 1;
        $display("FAILED - wr s/b x, is %h",wr);
      end
      if(w1 !== 1'b1)  begin
        error = 1;
        $display("FAILED - wr s/b 1, is %h",wr);
      end
      if(wwr !== 1'bx)  begin
        error = 1;
        $display("FAILED - wwr s/b x, is %h",wwr);
      end
      if(ww1 !== 1'bx)  begin
        error = 1;
        $display("FAILED - ww1 s/b x, is %h",ww1);
      end
      if(wr1 !== 1'bx)  begin
        error = 1;
        $display("FAILED - wr1 s/b x, is %h",wr1);
      end
      if(wwro !== 1'bx)  begin
        error = 1;
        $display("FAILED - wwro s/b 1, is %h",wwro);
      end
      if(wr1o !== 1'b1)  begin
        error = 1;
        $display("FAILED - wr1o s/b 1, is %h",wr1o);
      end
      if(r !== 1'bx)  begin
        error = 1;
        $display("FAILED - r s/b x, is %h",r);
      end
      if(r !== 1'bx)  begin
        error = 1;
        $display("FAILED - r s/b x, is %h",r);
      end
      if(rw !== 1'bz)  begin
        error = 1;
        $display("FAILED - rw s/b z, is %h",r);
      end
      if(error === 0)
        $display("PASSED");
      $finish(0);
   end

endmodule
module  main;


    reg     clk ;
    initial begin clk = 0 ; forever #5 clk = ~clk ; end
    initial #20 $finish;

    wire    w,   ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o ;
    reg     r,   rw ;
    reg    error;


    assign  ww  =   w       ;
    assign  wr  =   r       ;
    assign  w1  =   'b1     ;
    assign  wwr =   w & r   ;
    assign  ww1 =   w & 'b1 ;
    assign  wr1 =   r & 'b1 ;

    assign  wwro=   w | r   ;
    assign  ww1o=   w | 'b1 ;
    assign  wr1o=   r | 'b1 ;

    always @(posedge clk)
          rw <= w ;

    always @(posedge clk)
      begin
        #1;
        $display("%b %b %b %b %b %b %b : %b %b %b : %b %b",
        w, ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o, r, rw );
      end

initial
   begin
      error = 0;
      #19;
      if(ww !== 1'bz)  begin
        error = 1;
        $display("FAILED - ww s/b z, is %h",ww);
      end
      if(wr !== 1'bx)  begin
        error = 1;
        $display("FAILED - wr s/b x, is %h",wr);
      end
      if(w1 !== 1'b1)  begin
        error = 1;
        $display("FAILED - wr s/b 1, is %h",wr);
      end
      if(wwr !== 1'bx)  begin
        error = 1;
        $display("FAILED - wwr s/b x, is %h",wwr);
      end
      if(ww1 !== 1'bx)  begin
        error = 1;
        $display("FAILED - ww1 s/b x, is %h",ww1);
      end
      if(wr1 !== 1'bx)  begin
        error = 1;
        $display("FAILED - wr1 s/b x, is %h",wr1);
      end
      if(wwro !== 1'bx)  begin
        error = 1;
        $display("FAILED - wwro s/b 1, is %h",wwro);
      end
      if(wr1o !== 1'b1)  begin
        error = 1;
        $display("FAILED - wr1o s/b 1, is %h",wr1o);
      end
      if(r !== 1'bx)  begin
        error = 1;
        $display("FAILED - r s/b x, is %h",r);
      end
      if(r !== 1'bx)  begin
        error = 1;
        $display("FAILED - r s/b x, is %h",r);
      end
      if(rw !== 1'bz)  begin
        error = 1;
        $display("FAILED - rw s/b z, is %h",r);
      end
      if(error === 0)
        $display("PASSED");
      $finish(0);
   end

endmodule