data/full_repos/permissive/158984095/Homework2/Question1_a/HW_2_1_h_tb.v
1: b'%Error: data/full_repos/permissive/158984095/Homework2/Question1_a/HW_2_1_h_tb.v:8: Unsupported or unknown PLI call: $monitor\n$monitor($time,"in1=%b \\t in2=%b \\t out=%b \\n",in1[15:0],in2[15:0],out[31:0]);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question1_a/HW_2_1_h_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n# 10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question1_a/HW_2_1_h_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n# 10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question1_a/HW_2_1_h_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n# 10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question1_a/HW_2_1_h_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n# 10;\n^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multiplier_16bit_tb();
reg [15:0] in1;
reg [15:0] in2;
wire [31:0] out;
multiplier_16bit testbench_instantiation(in1[15:0],in2[15:0],out[31:0]);

initial begin
$monitor($time,"in1=%b \t in2=%b \t out=%b \n",in1[15:0],in2[15:0],out[31:0]);
# 10;
in1[15:0]=16'h0001;
in2[15:0]=16'h1010;
# 10;
in1[15:0]=16'h0002;
in2[15:0]=16'h0802;
# 10;
in1[15:0]=16'hFFFF;
in2[15:0]=16'hFFFF;
# 10;
end
endmodule
module multiplier_16bit_tb();

reg [15:0] in1;
reg [15:0] in2;
wire [31:0] out;
multiplier_16bit testbench_instantiation(in1[15:0],in2[15:0],out[31:0]);

initial begin
$monitor($time,"in1=%b \t in2=%b \t out=%b \n",in1[15:0],in2[15:0],out[31:0]);
# 10;
in1[15:0]=16'h0001;
in2[15:0]=16'h1010;
# 10;
in1[15:0]=16'h0002;
in2[15:0]=16'h0802;
# 10;
in1[15:0]=16'hFFFF;
in2[15:0]=16'hFFFF;
# 10;
end
endmodule