data/full_repos/permissive/16157344/uart_tx.v
1: b"%Error: data/full_repos/permissive/16157344/uart_tx.v:19: Cannot find file containing module: 'prescaler'\n prescaler #(.bitTime(M), .N(N)) freqDiv\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/16157344,data/full_repos/permissive/16157344/prescaler\n             data/full_repos/permissive/16157344,data/full_repos/permissive/16157344/prescaler.v\n             data/full_repos/permissive/16157344,data/full_repos/permissive/16157344/prescaler.sv\n             prescaler\n             prescaler.v\n             prescaler.sv\n             obj_dir/prescaler\n             obj_dir/prescaler.v\n             obj_dir/prescaler.sv\n%Error: data/full_repos/permissive/16157344/uart_tx.v:22: Cannot find file containing module: 'dataSend'\n dataSend #(.BITS(N_BITS)) transmitter\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module uart_tx
	#(
		parameter
			N_BITS = 8,
			M = 10417,
			N = 14

	)
	(
		input wire clk, rst, enable,

		input wire [7:0] data_i,
		output wire done, tx
	);

	wire [N-1:0] w_q;


	prescaler #(.bitTime(M), .N(N)) freqDiv
						(.clk(clk), .rst(rst), .q(w_q));

	dataSend #(.BITS(N_BITS)) transmitter
					 (.clk(clk), .rst(~rst), .enable(enable), .q(w_q),
					 	.data_i(data_i), .done(done), .tx(tx));



endmodule
module uart_tx
	#(
		parameter
			N_BITS = 8,
			M = 10417,
			N = 14

	)
	(
		input wire clk, rst, enable,

		input wire [7:0] data_i,
		output wire done, tx
	);


	wire [N-1:0] w_q;


	prescaler #(.bitTime(M), .N(N)) freqDiv
						(.clk(clk), .rst(rst), .q(w_q));

	dataSend #(.BITS(N_BITS)) transmitter
					 (.clk(clk), .rst(~rst), .enable(enable), .q(w_q),
					 	.data_i(data_i), .done(done), .tx(tx));



endmodule