data/full_repos/permissive/143278/ivltests/br_gh307.v
 line:2: before: "typedef"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh307.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 ;  \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simple(input two_bits b2in,
              output two_bits b2out);
   assign b2out.b1.b = b2in.b1.b;
endmodule
module simple(input two_bits b2in,
              output two_bits b2out);

   assign b2out.b1.b = b2in.b1.b;
endmodule