data/full_repos/permissive/215874117/src/ninjakun_shareio.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:86: Multiple top level modules\n                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                 : ... Top module \'NINJAKUN_IO_VIDEO\'\nmodule NINJAKUN_IO_VIDEO\n       ^~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'NINJAKUN_CPUMUX\'\nmodule NINJAKUN_CPUMUX\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:197: Cannot find file containing module: \'YM2149\'\nYM2149 psg0(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/215874117/src,data/full_repos/permissive/215874117/YM2149\n             data/full_repos/permissive/215874117/src,data/full_repos/permissive/215874117/YM2149.v\n             data/full_repos/permissive/215874117/src,data/full_repos/permissive/215874117/YM2149.sv\n             YM2149\n             YM2149.v\n             YM2149.sv\n             obj_dir/YM2149\n             obj_dir/YM2149.v\n             obj_dir/YM2149.sv\n%Error: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:205: Cannot find file containing module: \'YM2149\'\nYM2149 psg1(\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:214: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'SA0\' generates 8 bits.\n                                                                               : ... In instance NINJAKUN_IO_VIDEO.psg\nwire [11:0] SND = SA0+SB0+SC0+SA1+SB1+SC1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:214: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'SB0\' generates 8 bits.\n                                                                               : ... In instance NINJAKUN_IO_VIDEO.psg\nwire [11:0] SND = SA0+SB0+SC0+SA1+SB1+SC1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:214: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'SC0\' generates 8 bits.\n                                                                               : ... In instance NINJAKUN_IO_VIDEO.psg\nwire [11:0] SND = SA0+SB0+SC0+SA1+SB1+SC1;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:214: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'SA1\' generates 8 bits.\n                                                                               : ... In instance NINJAKUN_IO_VIDEO.psg\nwire [11:0] SND = SA0+SB0+SC0+SA1+SB1+SC1;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:214: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'SB1\' generates 8 bits.\n                                                                               : ... In instance NINJAKUN_IO_VIDEO.psg\nwire [11:0] SND = SA0+SB0+SC0+SA1+SB1+SC1;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:214: Operator ADD expects 12 bits on the RHS, but RHS\'s VARREF \'SC1\' generates 8 bits.\n                                                                               : ... In instance NINJAKUN_IO_VIDEO.psg\nwire [11:0] SND = SA0+SB0+SC0+SA1+SB1+SC1;\n                                     ^\n%Error: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:44: Cannot find file containing module: \'NINJAKUN_VIDEO\'\nNINJAKUN_VIDEO video (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:56: Cannot find file containing module: \'NINJAKUN_SADEC\'\nNINJAKUN_SADEC sadec( CPADR, CS_PSG, CS_FGV, CS_BGV, CS_SPA, CS_PAL );\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:63: Cannot find file containing module: \'VDPRAM400x2\'\nVDPRAM400x2 fgv( SHCLK, CPADR[10:0], CS_FGV & CPWRT, CPODT, FGDAT, VRCLK, FGVAD, FGVDT );\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:64: Cannot find file containing module: \'VDPRAM400x2\'\nVDPRAM400x2 bgv( SHCLK, BGADR      , CS_BGV & CPWRT, CPODT, BGDAT, VRCLK, BGVAD, BGVDT );\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:65: Cannot find file containing module: \'DPRAM800\'\nDPRAM800  spa( SHCLK, CPADR[10:0], CS_SPA & CPWRT, CPODT, SPDAT, VRCLK, SPAAD, 1\'b0, 8\'h0, SPADT );\n^~~~~~~~\n%Error: data/full_repos/permissive/215874117/src/ninjakun_shareio.v:66: Cannot find file containing module: \'DPRAM200\'\nDPRAM200  pal( SHCLK, CPADR[ 8:0], CS_PAL & CPWRT, CPODT, PLDAT,  VCLK, PALET, 1\'b0, 8\'h0, POUT  );\n^~~~~~~~\n%Error: Exiting due to 8 error(s), 7 warning(s)\n'
module NINJAKUN_PSG
(
	input				AXSCLK,
	input				CLK,
	input	 [1:0]	ADR,
	input				CS,
	input				WR,
	input	 [7:0]	ID,
	output [7:0]	OD,

	input				RESET,
	input				RD,

	input	 [7:0]	DSW1,
	input	 [7:0]	DSW2,

	output [7:0]	SCRPX,
	output [7:0]	SCRPY,

	output [15:0]	SNDO
);

wire [7:0] OD0, OD1;
assign OD = ADR[1] ? OD1 : OD0;

reg [7:0] SA0, SB0, SC0; wire [7:0] S0x; wire [1:0] S0c;
reg [7:0] SA1, SB1, SC1; wire [7:0] S1x; wire [1:0] S1c;

reg [1:0] encnt;
reg ENA;
always @(posedge AXSCLK) begin
	ENA <= (encnt==0);
	encnt <= encnt+1;
	case (S0c)
	2'd0: SA0 <= S0x;
	2'd1: SB0 <= S0x;
	2'd2: SC0 <= S0x;
	default:;
	endcase
	case (S1c)
	2'd0: SA1 <= S1x;
	2'd1: SB1 <= S1x;
	2'd2: SC1 <= S1x;
	default:;
	endcase
end

wire psgxad = ~ADR[0];
wire psg0cs = CS & (~ADR[1]);
wire psg0bd = psg0cs & (WR|psgxad);
wire psg0bc = psg0cs & ((~WR)|psgxad);

wire psg1cs = CS & ADR[1];
wire psg1bd = psg1cs & (WR|psgxad);
wire psg1bc = psg1cs & ((~WR)|psgxad);

YM2149 psg0(
	.I_DA(ID),.O_DA(OD0),.I_A9_L(~psg0cs),.I_BDIR(psg0bd),.I_BC1(psg0bc),
	.I_A8(1'b1),.I_BC2(1'b1),.I_SEL_L(1'b0),
	.O_AUDIO(S0x),.O_CHAN(S0c),
	.I_IOA(DSW1),.I_IOB(DSW2),
	.ENA(ENA),.RESET_L(~RESET),.CLK(AXSCLK)
);

YM2149 psg1(
	.I_DA(ID),.O_DA(OD1),.I_A9_L(~psg1cs),.I_BDIR(psg1bd),.I_BC1(psg1bc),
	.I_A8(1'b1),.I_BC2(1'b1),.I_SEL_L(1'b0),
	.O_AUDIO(S1x),.O_CHAN(S1c),
	.I_IOA(8'd0),.I_IOB(8'd0),
	.O_IOA(SCRPX),.O_IOB(SCRPY),
	.ENA(ENA),.RESET_L(~RESET),.CLK(AXSCLK)
);

wire [11:0] SND = SA0+SB0+SC0+SA1+SB1+SC1;
assign SNDO = {SND,SND[3:0]};

endmodule
module NINJAKUN_PSG
(
	input				AXSCLK,
	input				CLK,
	input	 [1:0]	ADR,
	input				CS,
	input				WR,
	input	 [7:0]	ID,
	output [7:0]	OD,

	input				RESET,
	input				RD,

	input	 [7:0]	DSW1,
	input	 [7:0]	DSW2,

	output [7:0]	SCRPX,
	output [7:0]	SCRPY,

	output [15:0]	SNDO
);


wire [7:0] OD0, OD1;
assign OD = ADR[1] ? OD1 : OD0;

reg [7:0] SA0, SB0, SC0; wire [7:0] S0x; wire [1:0] S0c;
reg [7:0] SA1, SB1, SC1; wire [7:0] S1x; wire [1:0] S1c;

reg [1:0] encnt;
reg ENA;
always @(posedge AXSCLK) begin
	ENA <= (encnt==0);
	encnt <= encnt+1;
	case (S0c)
	2'd0: SA0 <= S0x;
	2'd1: SB0 <= S0x;
	2'd2: SC0 <= S0x;
	default:;
	endcase
	case (S1c)
	2'd0: SA1 <= S1x;
	2'd1: SB1 <= S1x;
	2'd2: SC1 <= S1x;
	default:;
	endcase
end

wire psgxad = ~ADR[0];
wire psg0cs = CS & (~ADR[1]);
wire psg0bd = psg0cs & (WR|psgxad);
wire psg0bc = psg0cs & ((~WR)|psgxad);

wire psg1cs = CS & ADR[1];
wire psg1bd = psg1cs & (WR|psgxad);
wire psg1bc = psg1cs & ((~WR)|psgxad);

YM2149 psg0(
	.I_DA(ID),.O_DA(OD0),.I_A9_L(~psg0cs),.I_BDIR(psg0bd),.I_BC1(psg0bc),
	.I_A8(1'b1),.I_BC2(1'b1),.I_SEL_L(1'b0),
	.O_AUDIO(S0x),.O_CHAN(S0c),
	.I_IOA(DSW1),.I_IOB(DSW2),
	.ENA(ENA),.RESET_L(~RESET),.CLK(AXSCLK)
);

YM2149 psg1(
	.I_DA(ID),.O_DA(OD1),.I_A9_L(~psg1cs),.I_BDIR(psg1bd),.I_BC1(psg1bc),
	.I_A8(1'b1),.I_BC2(1'b1),.I_SEL_L(1'b0),
	.O_AUDIO(S1x),.O_CHAN(S1c),
	.I_IOA(8'd0),.I_IOB(8'd0),
	.O_IOA(SCRPX),.O_IOB(SCRPY),
	.ENA(ENA),.RESET_L(~RESET),.CLK(AXSCLK)
);

wire [11:0] SND = SA0+SB0+SC0+SA1+SB1+SC1;
assign SNDO = {SND,SND[3:0]};

endmodule