data/full_repos/permissive/193439230/sbox.v
data/verilator_xmls/9e770880-de7d-4db0-ab4b-be45e1c0d585.xml
module Input(b, g, m);
    input[7:0] b;
    output[7:0] g;
    output[9:0] m;
    wire t1,
        t2,
        t3,
        t4,
        t5,
        t6,
        t7,
        t8,
        t9,
        t10,
        t11,
        t12,
        t13,
        t14,
        t15,
        t16,
        t17;
    XOR m1(t1, b[7], b[5]);
    XNOR m2(t2, b[5], b[1]);
    XNOR m3(t3, b[0], t2);
    XOR m4(t4, b[6], b[2]);
    XOR m5(t5, b[3], t3);
    XOR m6(t6, b[4], t1);
    XOR m7(t7, b[1], t5);
    XOR m8(t8, b[1], t4);
    XOR m9(t9, t6, t8);
    XOR m10(t10, t6, t7);
    XNOR m11(t11, b[3], t1);
    XNOR m12(t12, b[6], t9);
    XOR m13(t13, t4, t10);
    XOR m14(t14, t2, t11);
    XOR m15(t15, t12, t14);
    XOR m16(t16, t3, t12);
    XOR m17(t17, t11, t16);
    assign g = {t15, t14, ~b[0], t2, t5, t13, t7, t10};
    assign m = {t12, t9, t17, b[1], t11, t4, t16, t8, t3, t6};
endmodule
module Input(b, g, m);

    input[7:0] b;
    output[7:0] g;
    output[9:0] m;
    wire t1,
        t2,
        t3,
        t4,
        t5,
        t6,
        t7,
        t8,
        t9,
        t10,
        t11,
        t12,
        t13,
        t14,
        t15,
        t16,
        t17;
    XOR m1(t1, b[7], b[5]);
    XNOR m2(t2, b[5], b[1]);
    XNOR m3(t3, b[0], t2);
    XOR m4(t4, b[6], b[2]);
    XOR m5(t5, b[3], t3);
    XOR m6(t6, b[4], t1);
    XOR m7(t7, b[1], t5);
    XOR m8(t8, b[1], t4);
    XOR m9(t9, t6, t8);
    XOR m10(t10, t6, t7);
    XNOR m11(t11, b[3], t1);
    XNOR m12(t12, b[6], t9);
    XOR m13(t13, t4, t10);
    XOR m14(t14, t2, t11);
    XOR m15(t15, t12, t14);
    XOR m16(t16, t3, t12);
    XOR m17(t17, t11, t16);
    assign g = {t15, t14, ~b[0], t2, t5, t13, t7, t10};
    assign m = {t12, t9, t17, b[1], t11, t4, t16, t8, t3, t6};
endmodule