data/full_repos/permissive/117880471/HW1/comparator_1bit.v
 line:52: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #00 AeqB_LSB = 1\'b1; AgtB_LSB = 1\'b0; AltB_LSB = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = 1\'b0; B = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = 1\'b0; B = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = 1\'b1; B = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = 1\'b1; B = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #20 AeqB_LSB = 1\'b0; AgtB_LSB = 1\'b1; AltB_LSB = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = 1\'b0; B = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = 1\'b0; B = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = 1\'b1; B = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = 1\'b1; B = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #20 AeqB_LSB = 1\'b0; AgtB_LSB = 1\'b0; AltB_LSB = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = 1\'b0; B = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = 1\'b0; B = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = 1\'b1; B = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #20 A = 1\'b1; B = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #20 $stop;\n  ^\n%Error: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:57: Unsupported or unknown PLI call: $monitor\n  $monitor("time=%3d, AeqB=%b, AgtB=%b, AltB=%b, AeqB_LSB=%b, AgtB_LSB=%b, AltB_LSB=%b, A=%b, B=%b", $time, AeqB, AgtB, AltB, AeqB_LSB, AgtB_LSB, AltB_LSB, A, B);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:62: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("comparator_1bit.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW1/comparator_1bit.v:63: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_comparator_1bit();
	wire AeqB, AgtB, AltB;
	reg AeqB_LSB, AgtB_LSB, AltB_LSB, A, B;

	comparator_1bit uut(AeqB, AgtB, AltB, AeqB_LSB, AgtB_LSB, AltB_LSB, A, B);

	initial
	begin
		#00	AeqB_LSB = 1'b1; AgtB_LSB = 1'b0; AltB_LSB = 1'b0;
		#20 A = 1'b0; B = 1'b0;
		#20 A = 1'b0; B = 1'b1;
		#20 A = 1'b1; B = 1'b0;
		#20 A = 1'b1; B = 1'b1;

		#20	AeqB_LSB = 1'b0; AgtB_LSB = 1'b1; AltB_LSB = 1'b0;
		#20 A = 1'b0; B = 1'b0;
		#20 A = 1'b0; B = 1'b1;
		#20 A = 1'b1; B = 1'b0;
		#20 A = 1'b1; B = 1'b1;

		#20	AeqB_LSB = 1'b0; AgtB_LSB = 1'b0; AltB_LSB = 1'b1;
		#20 A = 1'b0; B = 1'b0;
		#20 A = 1'b0; B = 1'b1;
		#20 A = 1'b1; B = 1'b0;
		#20 A = 1'b1; B = 1'b1;

		#20 $stop;
	end
	
	initial
	begin
		$monitor("time=%3d, AeqB=%b, AgtB=%b, AltB=%b, AeqB_LSB=%b, AgtB_LSB=%b, AltB_LSB=%b, A=%b, B=%b", $time, AeqB, AgtB, AltB, AeqB_LSB, AgtB_LSB, AltB_LSB, A, B);
	end

	initial
	begin
		$dumpfile("comparator_1bit.vcd");
		$dumpvars;
	end
endmodule
module tb_comparator_1bit();

	wire AeqB, AgtB, AltB;
	reg AeqB_LSB, AgtB_LSB, AltB_LSB, A, B;

	comparator_1bit uut(AeqB, AgtB, AltB, AeqB_LSB, AgtB_LSB, AltB_LSB, A, B);

	initial
	begin
		#00	AeqB_LSB = 1'b1; AgtB_LSB = 1'b0; AltB_LSB = 1'b0;
		#20 A = 1'b0; B = 1'b0;
		#20 A = 1'b0; B = 1'b1;
		#20 A = 1'b1; B = 1'b0;
		#20 A = 1'b1; B = 1'b1;

		#20	AeqB_LSB = 1'b0; AgtB_LSB = 1'b1; AltB_LSB = 1'b0;
		#20 A = 1'b0; B = 1'b0;
		#20 A = 1'b0; B = 1'b1;
		#20 A = 1'b1; B = 1'b0;
		#20 A = 1'b1; B = 1'b1;

		#20	AeqB_LSB = 1'b0; AgtB_LSB = 1'b0; AltB_LSB = 1'b1;
		#20 A = 1'b0; B = 1'b0;
		#20 A = 1'b0; B = 1'b1;
		#20 A = 1'b1; B = 1'b0;
		#20 A = 1'b1; B = 1'b1;

		#20 $stop;
	end
	
	initial
	begin
		$monitor("time=%3d, AeqB=%b, AgtB=%b, AltB=%b, AeqB_LSB=%b, AgtB_LSB=%b, AltB_LSB=%b, A=%b, B=%b", $time, AeqB, AgtB, AltB, AeqB_LSB, AgtB_LSB, AltB_LSB, A, B);
	end

	initial
	begin
		$dumpfile("comparator_1bit.vcd");
		$dumpvars;
	end
endmodule