data/full_repos/permissive/143278/vhdl_tests/pr2661101.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/pr2661101.v:6: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/pr2661101.v:8: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/pr2661101.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top();
  reg [7:0] a, a_a, a__a;

  initial begin
    a = 1;
    #1;
    a_a = 2;
    #1;
    a__a = 3;
    #1;

    if (a == 1 && a_a == 2 && a__a == 3)
      $display("PASSED");
    else
      $display("FAILED");

    $finish;
  end

endmodule
module top();

  reg [7:0] a, a_a, a__a;

  initial begin
    a = 1;
    #1;
    a_a = 2;
    #1;
    a__a = 3;
    #1;

    if (a == 1 && a_a == 2 && a__a == 3)
      $display("PASSED");
    else
      $display("FAILED");

    $finish;
  end

endmodule