data/full_repos/permissive/136510272/projects/atmega/icarus_memory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/icarus_memory.v:48: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance memory\n    q_0  = 1\'b0;              q  = 1\'b0;\n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/icarus_memory.v:48: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance memory\n    q_0  = 1\'b0;              q  = 1\'b0;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/icarus_memory.v:49: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance memory\n    qw_0 = 1\'b0; qw_1 = 1\'b0; qw = 1\'b0;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/icarus_memory.v:49: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance memory\n    qw_0 = 1\'b0; qw_1 = 1\'b0; qw = 1\'b0;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/icarus_memory.v:49: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance memory\n    qw_0 = 1\'b0; qw_1 = 1\'b0; qw = 1\'b0;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/icarus_memory.v:60: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 19 bits.\n                                                                                       : ... In instance memory\n    q_0  <= memory[ addr_rd ];  \n         ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/icarus_memory.v:65: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 19 bits.\n                                                                                       : ... In instance memory\n    qw_1 <= memory[ addr_wr ];\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/icarus_memory.v:70: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_wr\' generates 16 bits.\n                                                                                       : ... In instance memory\n    if (wren) memory[ addr_wr ] <= data_wr;\n                                ^~\n%Error: Exiting due to 8 warning(s)\n'
module memory(

    input  wire                      clk,
    input  wire [(`BITS_ADDR - 1):0] addr_rd,
    output reg  [(`BITS_DATA - 1):0] q,
    input  wire [(`BITS_ADDR - 1):0] addr_wr,
    input  wire [(`BITS_DATA - 1):0] data_wr,
    input  wire                      wren,
    output reg  [(`BITS_DATA - 1):0] qw

);


reg [`BITS_ADDR - 1 : 0] memory [`ADDR_SIZE - 1: 0];




initial begin

    $readmemh(`MEM_BINFILE, memory) ;
    
    q_0  = 1'b0;              q  = 1'b0;
    qw_0 = 1'b0; qw_1 = 1'b0; qw = 1'b0;
    
end

reg  [(`BITS_DATA - 1):0]  q_0;
reg  [(`BITS_DATA - 1):0] qw_0; 
reg  [(`BITS_DATA - 1):0] qw_1;

always @(posedge clk) begin


    q_0  <= memory[ addr_rd ];  
    q    <= q_0;                
    


    qw_1 <= memory[ addr_wr ];
    qw_0 <= qw_1;
    qw   <= qw_0;
    

    if (wren) memory[ addr_wr ] <= data_wr;

end

endmodule
module memory(

    input  wire                      clk,
    input  wire [(`BITS_ADDR - 1):0] addr_rd,
    output reg  [(`BITS_DATA - 1):0] q,
    input  wire [(`BITS_ADDR - 1):0] addr_wr,
    input  wire [(`BITS_DATA - 1):0] data_wr,
    input  wire                      wren,
    output reg  [(`BITS_DATA - 1):0] qw

);



reg [`BITS_ADDR - 1 : 0] memory [`ADDR_SIZE - 1: 0];




initial begin

    $readmemh(`MEM_BINFILE, memory) ;
    
    q_0  = 1'b0;              q  = 1'b0;
    qw_0 = 1'b0; qw_1 = 1'b0; qw = 1'b0;
    
end

reg  [(`BITS_DATA - 1):0]  q_0;
reg  [(`BITS_DATA - 1):0] qw_0; 
reg  [(`BITS_DATA - 1):0] qw_1;

always @(posedge clk) begin


    q_0  <= memory[ addr_rd ];  
    q    <= q_0;                
    


    qw_1 <= memory[ addr_wr ];
    qw_0 <= qw_1;
    qw   <= qw_0;
    

    if (wren) memory[ addr_wr ] <= data_wr;

end

endmodule