data/full_repos/permissive/158845296/fetch_to_decode.v
data/verilator_xmls/9e2e6683-6777-450f-b220-5eb687b06708.xml
module fetch_to_decode
(
    input clock,
    input reset,
    

    input [31:0] f_instr,
    input [31:0] f_pc,
    input        f_stall,
    

    input             d_stall,
    output reg [31:0] d_instr,
    output reg [31:0] d_pc
);

    always @(posedge clock) begin
        d_instr <= (reset) ? 32'b0 : (d_stall ? d_instr : (f_stall ? 32'b0 : f_instr));
        d_pc    <= (reset) ? 32'b0 : (d_stall ? d_pc                       : f_pc);
    end

endmodule
module fetch_to_decode
(
    input clock,
    input reset,
    

    input [31:0] f_instr,
    input [31:0] f_pc,
    input        f_stall,
    

    input             d_stall,
    output reg [31:0] d_instr,
    output reg [31:0] d_pc
);


    always @(posedge clock) begin
        d_instr <= (reset) ? 32'b0 : (d_stall ? d_instr : (f_stall ? 32'b0 : f_instr));
        d_pc    <= (reset) ? 32'b0 : (d_stall ? d_pc                       : f_pc);
    end

endmodule