data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Led.v
 line:55: before: "/"
1: b'%Warning-MULTITOP: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/Led.v:40: Multiple top level modules\n                                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                        : ... Top module \'Led\'\nmodule Led(\n       ^~~\n                                                                                                        : ... Top module \'RGB\'\nmodule RGB (\n       ^~~\n%Error: Exiting due to 1 warning(s)\n'
module Led(
    input [3:0] ticketnum,
    input clk,
    output [15:0] led
    );
    reg [15:0] led_ = 16'h0000;
    always @(posedge clk) begin : lit
        integer i;
        for (i = 0; i < 16; i = i + 1)
            if (i < ticketnum)
                led_[i] = 1;
            else
                led_[i] = 0;
    end
    assign led = led_;
endmodule
module Led(
    input [3:0] ticketnum,
    input clk,
    output [15:0] led
    );

    reg [15:0] led_ = 16'h0000;
    always @(posedge clk) begin : lit
        integer i;
        for (i = 0; i < 16; i = i + 1)
            if (i < ticketnum)
                led_[i] = 1;
            else
                led_[i] = 0;
    end
    assign led = led_;
endmodule