data/full_repos/permissive/143278/ivltests/pr1367855.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1367855.v:9: Unsupported: Ignoring delay on this delayed statement.\n   S=3; #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1367855.v:10: Unsupported: Ignoring delay on this delayed statement.\n   S=2; #100;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1367855.v:22: Operator ADD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                         : ... In instance test.m\n   offset = SEL[3] + SEL[0]*128 + SEL[2:1]*2;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1367855.v:25: Operator CASE expects 32 bits on the Case expression, but Case expression\'s VARREF \'SEL\' generates 4 bits.\n                                                                         : ... In instance test.m\n   case (SEL)\n   ^~~~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();
  reg [3:0] S;

  mux m( .SEL(S) );

  initial begin
   S=3; #100;
   S=2; #100;
   $display("PASSED");
   $finish;
  end
endmodule
module test();

  reg [3:0] S;

  mux m( .SEL(S) );

  initial begin
   S=3; #100;
   S=2; #100;
   $display("PASSED");
   $finish;
  end
endmodule