data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/tart_correlator.v
None: at end of input
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/tart_correlator.v:53: Cannot find include file: tartcfg.v\n`include "tartcfg.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/tartcfg.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/tartcfg.v.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/tartcfg.v.sv\n             tartcfg.v\n             tartcfg.v.v\n             tartcfg.v.sv\n             obj_dir/tartcfg.v\n             obj_dir/tartcfg.v.v\n             obj_dir/tartcfg.v.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/tart_correlator.v:271: Cannot find include file: ../include/tart_pairs.v\n`include "../include/tart_pairs.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module tart_correlator
  #(
    parameter ACCUM = 24,
    parameter MSB   = ACCUM-1,
    parameter BYTES = ACCUM>>3,
    parameter IBITS = 24,
    parameter ISB   = IBITS-1,


    parameter WIDTH = ACCUM*2,
    parameter WSB   = WIDTH-1,
    parameter QBITS = WIDTH*4,
    parameter QSB   = QBITS-1,


    parameter TRATE = 12,
    parameter TBITS = 4,
    parameter TSB   = TBITS-1,


    parameter XBITS = 4,
    parameter XSB   = XBITS-1,


    parameter ABITS = 14,
    parameter ASB   = ABITS-1,
    parameter NSRAM = ACCUM>>2,
    parameter SEQRD = 1,


    parameter DSLOW = 0,
    parameter SSLOW = 0,
    parameter DDUPS = 0,
    parameter SDUPS = 0,


    parameter KBITS = TBITS+XBITS,
    parameter KSB   = KBITS-1,
    parameter JBITS = KBITS+3,
    parameter JSB   = JBITS-1,


    parameter ASYNC = 1,
    parameter PIPED = 1,
    parameter CHECK = 1,


    parameter DELAY = 3)
   (
    input          clk_x,
    input          clk_i,
    input          rst_i,


    input          cyc_i,
    input          stb_i,
    input          we_i,
    output         ack_o,
    output         wat_o,
    output         rty_o,
    output         err_o,
    input [ASB:0]  adr_i,
    input [MSB:0]  dat_i,
    output [MSB:0] dat_o,


    input          vld_i,
    input          new_i,
    input [ISB:0]  sig_i,


    output         switching_o,


    input [MSB:0]  sums_x_i,
    output         swap_x_o,
    output [XSB:0] bank_x_o
    );




   wire            sram_ce;
   wire [JSB:0]    sram_ad;
   wire [MSB:0]    sram_d0, sram_d1, sram_d2, sram_d3, sram_d4, sram_d5;
   wire [MSB:0]    sram_do;
   reg [MSB:0]     sram_out;



   reg [2:0]       sel0, sel1;
   wire [2:0]      sel_w, sel;
   wire [JSB:0]    adr_w;
   wire            stb_w;




   reg          pre_x, strobe_x, go_x;
   reg [ISB:0]  re_x, im_x;
   wire         sw_x, go_b, strobe_b;
   wire [ISB:0] re_b, im_b;







   assign stb_w = CHECK ? cyc_i && stb_i : stb_i;


   assign adr_w = {adr_i[ASB:10], adr_i[4:1], adr_i[6:5], adr_i[0]};


   assign sel_w = adr_i[9:7];



   assign sel   = SEQRD ? sel_w : sel1;

   assign swap_x_o = sw_x;









   always @(posedge clk_i)
     if (stb_w)
       {sel1, sel0} <= #DELAY {sel0, sel_w};


   always @(posedge clk_i)
     sram_out <= #DELAY sram_do;





   always @(posedge clk_x)
     begin
        pre_x    <= #DELAY strobe_b && !pre_x && !strobe_x;
        strobe_x <= #DELAY pre_x;
        go_x     <= #DELAY go_b;
        re_x     <= #DELAY re_b;
        im_x     <= #DELAY im_b;
     end






   (* NOMERGE *) reg rst_x = 1'b1, rst_s = 1'b1;

   always @(posedge clk_x)
     {rst_x, rst_s} <= #DELAY {rst_s, rst_i};





   (* AREA_GROUP = "hilb" *)
   fake_hilbert
     #(  .WIDTH(IBITS)
         ) HILB0
       ( .clock_i (clk_i),
         .reset_i (rst_i),

         .enable_i(vld_i),
         .strobe_i(new_i),
         .signal_i(sig_i),

         .locked_o(go_b),
         .strobe_o(strobe_b),
         .framed_o(),
         .sig_re_o(re_b),
         .sig_im_o(im_b)
         );






   (* NOMERGE *) reg rst_b = 1'b1;

   always @(posedge clk_x)
     rst_b <= #DELAY rst_x;


   bank_switch
     #(  .COUNT(ACCUM),
         .TICKS(4)
         ) SW0
       ( .clk_x   (clk_x),
         .rst_x   (rst_b),
         .clk_i   (clk_i),
         .rst_i   (rst_i),
         .ce_i    (go_x),
         .frame_i (strobe_x),
         .bcount_i(sums_x_i),
         .swap_x  (sw_x),
         .swap_o  (switching_o)
         );







`include "../include/tart_pairs.v"

   (* AREA_GROUP = "cblk0" *)
   correlator_block
     #( .PAIRS0(PAIRS00_00),
        .PAIRS1(PAIRS00_01),
        .PAIRS2(PAIRS00_02),
        .PAIRS3(PAIRS00_03),

        .ACCUM(ACCUM),
        .IBITS(IBITS),
        .WIDTH(WIDTH),
        .QBITS(QBITS),
        .TRATE(TRATE),
        .TBITS(TBITS),
        .XBITS(XBITS),
        .NSRAM(NSRAM),
        .CARRY(0),
        .TICKS(4),
        .SLOW (DSLOW),
        .DUPS (DDUPS),
        .ABITS(KBITS),
        .DELAY(DELAY)
        ) CXB0
       (
        .clk_x(clk_x),
        .rst_x(rst_x),
        .clk_i(clk_i),


        .sw_i(sw_x),
        .en_i(go_x),
        .re_i(re_x),
        .im_i(im_x),

        .bank_o(bank_x_o),


        .sram_ce_i(sram_ce),
        .sram_ad_i(sram_ad),
        .sram_do_o(sram_d0)
        );

   (* AREA_GROUP = "cblk1" *)
   correlator_block
     #( .PAIRS0(PAIRS01_00),
        .PAIRS1(PAIRS01_01),
        .PAIRS2(PAIRS01_02),
        .PAIRS3(PAIRS01_03),

        .ACCUM(ACCUM),
        .IBITS(IBITS),
        .WIDTH(WIDTH),
        .QBITS(QBITS),
        .TRATE(TRATE),
        .TBITS(TBITS),
        .XBITS(XBITS),
        .NSRAM(NSRAM),
        .CARRY(0),
        .TICKS(4),
        .SLOW (DSLOW),
        .DUPS (DDUPS),
        .ABITS(KBITS),
        .DELAY(DELAY)
        ) CXB1
       (
        .clk_x(clk_x),
        .rst_x(rst_x),
        .clk_i(clk_i),


        .sw_i(sw_x),
        .en_i(go_x),
        .re_i(re_x),
        .im_i(im_x),

        .bank_o(),


        .sram_ce_i(sram_ce),
        .sram_ad_i(sram_ad),
        .sram_do_o(sram_d1)
        );

   (* AREA_GROUP = "cblk2" *)
   correlator_block
     #( .PAIRS0(PAIRS02_00),
        .PAIRS1(PAIRS02_01),
        .PAIRS2(PAIRS02_02),
        .PAIRS3(PAIRS02_03),

        .ACCUM(ACCUM),
        .IBITS(IBITS),
        .WIDTH(WIDTH),
        .QBITS(QBITS),
        .TRATE(TRATE),
        .TBITS(TBITS),
        .XBITS(XBITS),
        .NSRAM(NSRAM),
        .CARRY(0),
        .TICKS(4),
        .SLOW (DSLOW),
        .DUPS (DDUPS),
        .ABITS(KBITS),
        .DELAY(DELAY)
        ) CXB2
       (
        .clk_x(clk_x),
        .rst_x(rst_x),
        .clk_i(clk_i),


        .sw_i(sw_x),
        .en_i(go_x),
        .re_i(re_x),
        .im_i(im_x),

        .bank_o(),


        .sram_ce_i(sram_ce),
        .sram_ad_i(sram_ad),
        .sram_do_o(sram_d2)
        );

   (* AREA_GROUP = "cblk3" *)
   correlator_block
     #( .PAIRS0(PAIRS03_00),
        .PAIRS1(PAIRS03_01),
        .PAIRS2(PAIRS03_02),
        .PAIRS3(PAIRS03_03),

        .ACCUM(ACCUM),
        .IBITS(IBITS),
        .WIDTH(WIDTH),
        .QBITS(QBITS),
        .TRATE(TRATE),
        .TBITS(TBITS),
        .XBITS(XBITS),
        .NSRAM(NSRAM),
        .CARRY(0),
        .TICKS(4),
        .SLOW (DSLOW),
        .DUPS (DDUPS),
        .ABITS(KBITS),
        .DELAY(DELAY)
        ) CXB3
       (
        .clk_x(clk_x),
        .rst_x(rst_x),
        .clk_i(clk_i),


        .sw_i(sw_x),
        .en_i(go_x),
        .re_i(re_x),
        .im_i(im_x),

        .bank_o(),


        .sram_ce_i(sram_ce),
        .sram_ad_i(sram_ad),
        .sram_do_o(sram_d3)
        );





   (* AREA_GROUP = "cblk4" *)
   correlator_block
     #( .PAIRS0(PAIRS04_00),
        .PAIRS1(PAIRS04_01),
        .PAIRS2(PAIRS04_02),
        .PAIRS3(PAIRS04_03),

        .ACCUM(ACCUM),
        .IBITS(IBITS),
        .WIDTH(WIDTH),
        .QBITS(QBITS),
        .TRATE(TRATE),
        .TBITS(TBITS),
        .XBITS(XBITS),
        .NSRAM(NSRAM),
        .CARRY(1),
        .TICKS(3),
        .SLOW (SSLOW),
        .DUPS (SDUPS),
        .ABITS(KBITS),
        .DELAY(DELAY)
        ) CXB4
       (
        .clk_x(clk_x),
        .rst_x(rst_x),
        .clk_i(clk_i),


        .sw_i(sw_x),
        .en_i(go_x),
        .re_i(re_x),
        .im_i(im_x),

        .bank_o(),


        .sram_ce_i(sram_ce),
        .sram_ad_i(sram_ad),
        .sram_do_o(sram_d4)
        );

   (* AREA_GROUP = "cblk5" *)
   correlator_block
     #( .PAIRS0(PAIRS05_00),
        .PAIRS1(PAIRS05_01),
        .PAIRS2(PAIRS05_02),
        .PAIRS3(PAIRS05_03),

        .ACCUM(ACCUM),
        .IBITS(IBITS),
        .WIDTH(WIDTH),
        .QBITS(QBITS),
        .TRATE(TRATE),
        .TBITS(TBITS),
        .XBITS(XBITS),
        .NSRAM(NSRAM),
        .CARRY(1),
        .TICKS(3),
        .SLOW (SSLOW),
        .DUPS (SDUPS),
        .ABITS(KBITS),
        .DELAY(DELAY)
        ) CXB5
       (
        .clk_x(clk_x),
        .rst_x(rst_x),
        .clk_i(clk_i),


        .sw_i(sw_x),
        .en_i(go_x),
        .re_i(re_x),
        .im_i(im_x),

        .bank_o(),


        .sram_ce_i(sram_ce),
        .sram_ad_i(sram_ad),
        .sram_do_o(sram_d5)
        );






   MUX8 #( .WIDTH(ACCUM) ) DMUX
     ( .a(sram_d0),
       .b(sram_d1),
       .c(sram_d2),
       .d(sram_d3),
       .e(sram_d4),
       .f(sram_d5),
       .g({ACCUM{1'bx}}),
       .h({ACCUM{1'bx}}),
       .s(sel),
       .x(sram_do)
       );





   wb_sram_port
     #( .WIDTH(ACCUM),
        .ABITS(JBITS),
        .TICKS(3),
        .READ (1),
        .WRITE(0),
        .USEBE(0),
        .PIPED(PIPED),
        .ASYNC(0),
        .CHECK(CHECK),
        .DELAY(DELAY)
        ) SCTRL
       (
        .clk_i(clk_i),
        .rst_i(rst_i),

        .cyc_i(cyc_i),
        .stb_i(stb_i),
        .we_i (1'b0 ),
        .ack_o(ack_o),
        .wat_o(wat_o),
        .rty_o(rty_o),
        .err_o(err_o),
        .adr_i(adr_w),
        .sel_i({BYTES{1'b1}}),
        .dat_i({ACCUM{1'bx}}),
        .dat_o(dat_o),

        .sram_ce_o(sram_ce),
        .sram_we_o(),
        .sram_ad_o(sram_ad),
        .sram_be_o(),
        .sram_do_i(sram_out),
        .sram_di_o()
        );


endmodule
module tart_correlator
  #(
    parameter ACCUM = 24,
    parameter MSB   = ACCUM-1,
    parameter BYTES = ACCUM>>3,
    parameter IBITS = 24,
    parameter ISB   = IBITS-1,


    parameter WIDTH = ACCUM*2,
    parameter WSB   = WIDTH-1,
    parameter QBITS = WIDTH*4,
    parameter QSB   = QBITS-1,


    parameter TRATE = 12,
    parameter TBITS = 4,
    parameter TSB   = TBITS-1,


    parameter XBITS = 4,
    parameter XSB   = XBITS-1,


    parameter ABITS = 14,
    parameter ASB   = ABITS-1,
    parameter NSRAM = ACCUM>>2,
    parameter SEQRD = 1,


    parameter DSLOW = 0,
    parameter SSLOW = 0,
    parameter DDUPS = 0,
    parameter SDUPS = 0,


    parameter KBITS = TBITS+XBITS,
    parameter KSB   = KBITS-1,
    parameter JBITS = KBITS+3,
    parameter JSB   = JBITS-1,


    parameter ASYNC = 1,
    parameter PIPED = 1,
    parameter CHECK = 1,


    parameter DELAY = 3)
   (
    input          clk_x,
    input          clk_i,
    input          rst_i,


    input          cyc_i,
    input          stb_i,
    input          we_i,
    output         ack_o,
    output         wat_o,
    output         rty_o,
    output         err_o,
    input [ASB:0]  adr_i,
    input [MSB:0]  dat_i,
    output [MSB:0] dat_o,


    input          vld_i,
    input          new_i,
    input [ISB:0]  sig_i,


    output         switching_o,


    input [MSB:0]  sums_x_i,
    output         swap_x_o,
    output [XSB:0] bank_x_o
    );





   wire            sram_ce;
   wire [JSB:0]    sram_ad;
   wire [MSB:0]    sram_d0, sram_d1, sram_d2, sram_d3, sram_d4, sram_d5;
   wire [MSB:0]    sram_do;
   reg [MSB:0]     sram_out;



   reg [2:0]       sel0, sel1;
   wire [2:0]      sel_w, sel;
   wire [JSB:0]    adr_w;
   wire            stb_w;




   reg          pre_x, strobe_x, go_x;
   reg [ISB:0]  re_x, im_x;
   wire         sw_x, go_b, strobe_b;
   wire [ISB:0] re_b, im_b;







   assign stb_w = CHECK ? cyc_i && stb_i : stb_i;


   assign adr_w = {adr_i[ASB:10], adr_i[4:1], adr_i[6:5], adr_i[0]};


   assign sel_w = adr_i[9:7];



   assign sel   = SEQRD ? sel_w : sel1;

   assign swap_x_o = sw_x;









   always @(posedge clk_i)
     if (stb_w)
       {sel1, sel0} <= #DELAY {sel0, sel_w};


   always @(posedge clk_i)
     sram_out <= #DELAY sram_do;





   always @(posedge clk_x)
     begin
        pre_x    <= #DELAY strobe_b && !pre_x && !strobe_x;
        strobe_x <= #DELAY pre_x;
        go_x     <= #DELAY go_b;
        re_x     <= #DELAY re_b;
        im_x     <= #DELAY im_b;
     end






   (* NOMERGE *) reg rst_x = 1'b1, rst_s = 1'b1;

   always @(posedge clk_x)
     {rst_x, rst_s} <= #DELAY {rst_s, rst_i};





   (* AREA_GROUP = "hilb" *)
   fake_hilbert
     #(  .WIDTH(IBITS)
         ) HILB0
       ( .clock_i (clk_i),
         .reset_i (rst_i),

         .enable_i(vld_i),
         .strobe_i(new_i),
         .signal_i(sig_i),

         .locked_o(go_b),
         .strobe_o(strobe_b),
         .framed_o(),
         .sig_re_o(re_b),
         .sig_im_o(im_b)
         );






   (* NOMERGE *) reg rst_b = 1'b1;

   always @(posedge clk_x)
     rst_b <= #DELAY rst_x;


   bank_switch
     #(  .COUNT(ACCUM),
         .TICKS(4)
         ) SW0
       ( .clk_x   (clk_x),
         .rst_x   (rst_b),
         .clk_i   (clk_i),
         .rst_i   (rst_i),
         .ce_i    (go_x),
         .frame_i (strobe_x),
         .bcount_i(sums_x_i),
         .swap_x  (sw_x),
         .swap_o  (switching_o)
         );







`include "../include/tart_pairs.v"

   (* AREA_GROUP = "cblk0" *)
   correlator_block
     #( .PAIRS0(PAIRS00_00),
        .PAIRS1(PAIRS00_01),
        .PAIRS2(PAIRS00_02),
        .PAIRS3(PAIRS00_03),

        .ACCUM(ACCUM),
        .IBITS(IBITS),
        .WIDTH(WIDTH),
        .QBITS(QBITS),
        .TRATE(TRATE),
        .TBITS(TBITS),
        .XBITS(XBITS),
        .NSRAM(NSRAM),
        .CARRY(0),
        .TICKS(4),
        .SLOW (DSLOW),
        .DUPS (DDUPS),
        .ABITS(KBITS),
        .DELAY(DELAY)
        ) CXB0
       (
        .clk_x(clk_x),
        .rst_x(rst_x),
        .clk_i(clk_i),


        .sw_i(sw_x),
        .en_i(go_x),
        .re_i(re_x),
        .im_i(im_x),

        .bank_o(bank_x_o),


        .sram_ce_i(sram_ce),
        .sram_ad_i(sram_ad),
        .sram_do_o(sram_d0)
        );

   (* AREA_GROUP = "cblk1" *)
   correlator_block
     #( .PAIRS0(PAIRS01_00),
        .PAIRS1(PAIRS01_01),
        .PAIRS2(PAIRS01_02),
        .PAIRS3(PAIRS01_03),

        .ACCUM(ACCUM),
        .IBITS(IBITS),
        .WIDTH(WIDTH),
        .QBITS(QBITS),
        .TRATE(TRATE),
        .TBITS(TBITS),
        .XBITS(XBITS),
        .NSRAM(NSRAM),
        .CARRY(0),
        .TICKS(4),
        .SLOW (DSLOW),
        .DUPS (DDUPS),
        .ABITS(KBITS),
        .DELAY(DELAY)
        ) CXB1
       (
        .clk_x(clk_x),
        .rst_x(rst_x),
        .clk_i(clk_i),


        .sw_i(sw_x),
        .en_i(go_x),
        .re_i(re_x),
        .im_i(im_x),

        .bank_o(),


        .sram_ce_i(sram_ce),
        .sram_ad_i(sram_ad),
        .sram_do_o(sram_d1)
        );

   (* AREA_GROUP = "cblk2" *)
   correlator_block
     #( .PAIRS0(PAIRS02_00),
        .PAIRS1(PAIRS02_01),
        .PAIRS2(PAIRS02_02),
        .PAIRS3(PAIRS02_03),

        .ACCUM(ACCUM),
        .IBITS(IBITS),
        .WIDTH(WIDTH),
        .QBITS(QBITS),
        .TRATE(TRATE),
        .TBITS(TBITS),
        .XBITS(XBITS),
        .NSRAM(NSRAM),
        .CARRY(0),
        .TICKS(4),
        .SLOW (DSLOW),
        .DUPS (DDUPS),
        .ABITS(KBITS),
        .DELAY(DELAY)
        ) CXB2
       (
        .clk_x(clk_x),
        .rst_x(rst_x),
        .clk_i(clk_i),


        .sw_i(sw_x),
        .en_i(go_x),
        .re_i(re_x),
        .im_i(im_x),

        .bank_o(),


        .sram_ce_i(sram_ce),
        .sram_ad_i(sram_ad),
        .sram_do_o(sram_d2)
        );

   (* AREA_GROUP = "cblk3" *)
   correlator_block
     #( .PAIRS0(PAIRS03_00),
        .PAIRS1(PAIRS03_01),
        .PAIRS2(PAIRS03_02),
        .PAIRS3(PAIRS03_03),

        .ACCUM(ACCUM),
        .IBITS(IBITS),
        .WIDTH(WIDTH),
        .QBITS(QBITS),
        .TRATE(TRATE),
        .TBITS(TBITS),
        .XBITS(XBITS),
        .NSRAM(NSRAM),
        .CARRY(0),
        .TICKS(4),
        .SLOW (DSLOW),
        .DUPS (DDUPS),
        .ABITS(KBITS),
        .DELAY(DELAY)
        ) CXB3
       (
        .clk_x(clk_x),
        .rst_x(rst_x),
        .clk_i(clk_i),


        .sw_i(sw_x),
        .en_i(go_x),
        .re_i(re_x),
        .im_i(im_x),

        .bank_o(),


        .sram_ce_i(sram_ce),
        .sram_ad_i(sram_ad),
        .sram_do_o(sram_d3)
        );





   (* AREA_GROUP = "cblk4" *)
   correlator_block
     #( .PAIRS0(PAIRS04_00),
        .PAIRS1(PAIRS04_01),
        .PAIRS2(PAIRS04_02),
        .PAIRS3(PAIRS04_03),

        .ACCUM(ACCUM),
        .IBITS(IBITS),
        .WIDTH(WIDTH),
        .QBITS(QBITS),
        .TRATE(TRATE),
        .TBITS(TBITS),
        .XBITS(XBITS),
        .NSRAM(NSRAM),
        .CARRY(1),
        .TICKS(3),
        .SLOW (SSLOW),
        .DUPS (SDUPS),
        .ABITS(KBITS),
        .DELAY(DELAY)
        ) CXB4
       (
        .clk_x(clk_x),
        .rst_x(rst_x),
        .clk_i(clk_i),


        .sw_i(sw_x),
        .en_i(go_x),
        .re_i(re_x),
        .im_i(im_x),

        .bank_o(),


        .sram_ce_i(sram_ce),
        .sram_ad_i(sram_ad),
        .sram_do_o(sram_d4)
        );

   (* AREA_GROUP = "cblk5" *)
   correlator_block
     #( .PAIRS0(PAIRS05_00),
        .PAIRS1(PAIRS05_01),
        .PAIRS2(PAIRS05_02),
        .PAIRS3(PAIRS05_03),

        .ACCUM(ACCUM),
        .IBITS(IBITS),
        .WIDTH(WIDTH),
        .QBITS(QBITS),
        .TRATE(TRATE),
        .TBITS(TBITS),
        .XBITS(XBITS),
        .NSRAM(NSRAM),
        .CARRY(1),
        .TICKS(3),
        .SLOW (SSLOW),
        .DUPS (SDUPS),
        .ABITS(KBITS),
        .DELAY(DELAY)
        ) CXB5
       (
        .clk_x(clk_x),
        .rst_x(rst_x),
        .clk_i(clk_i),


        .sw_i(sw_x),
        .en_i(go_x),
        .re_i(re_x),
        .im_i(im_x),

        .bank_o(),


        .sram_ce_i(sram_ce),
        .sram_ad_i(sram_ad),
        .sram_do_o(sram_d5)
        );






   MUX8 #( .WIDTH(ACCUM) ) DMUX
     ( .a(sram_d0),
       .b(sram_d1),
       .c(sram_d2),
       .d(sram_d3),
       .e(sram_d4),
       .f(sram_d5),
       .g({ACCUM{1'bx}}),
       .h({ACCUM{1'bx}}),
       .s(sel),
       .x(sram_do)
       );





   wb_sram_port
     #( .WIDTH(ACCUM),
        .ABITS(JBITS),
        .TICKS(3),
        .READ (1),
        .WRITE(0),
        .USEBE(0),
        .PIPED(PIPED),
        .ASYNC(0),
        .CHECK(CHECK),
        .DELAY(DELAY)
        ) SCTRL
       (
        .clk_i(clk_i),
        .rst_i(rst_i),

        .cyc_i(cyc_i),
        .stb_i(stb_i),
        .we_i (1'b0 ),
        .ack_o(ack_o),
        .wat_o(wat_o),
        .rty_o(rty_o),
        .err_o(err_o),
        .adr_i(adr_w),
        .sel_i({BYTES{1'b1}}),
        .dat_i({ACCUM{1'bx}}),
        .dat_o(dat_o),

        .sram_ce_o(sram_ce),
        .sram_we_o(),
        .sram_ad_o(sram_ad),
        .sram_be_o(),
        .sram_do_i(sram_out),
        .sram_di_o()
        );


endmodule