data/full_repos/permissive/124982712/src/RateDivider.v
1: b'%Warning-WIDTH: data/full_repos/permissive/124982712/src/RateDivider.v:28: Operator EQ expects 28 bits on the RHS, but RHS\'s CONST \'27\'h1\' generates 27 bits.\n                                                                         : ... In instance RateDivider\n   if (cur_time == 27\'d1)  \n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module RateDivider(
	input [27:0] interval,
	input reset,
	input en,
	input clock_50,
	output reg reduced_clock);

	reg [27:0] cur_time;

	always @(posedge clock_50)
	begin
		if (reset == 1'b1)
		begin
			cur_time <= interval;
			reduced_clock <= 1'b0;
		end
		else if (en == 1'b1)
		begin
			if (cur_time == 27'd1)
			begin
				cur_time <= interval;
				reduced_clock <= ~reduced_clock;
			end
			else
			begin
				cur_time <= cur_time - 1'b1;
			end
		end
	end
endmodule
module RateDivider(
	input [27:0] interval,
	input reset,
	input en,
	input clock_50,
	output reg reduced_clock);


	reg [27:0] cur_time;

	always @(posedge clock_50)
	begin
		if (reset == 1'b1)
		begin
			cur_time <= interval;
			reduced_clock <= 1'b0;
		end
		else if (en == 1'b1)
		begin
			if (cur_time == 27'd1)
			begin
				cur_time <= interval;
				reduced_clock <= ~reduced_clock;
			end
			else
			begin
				cur_time <= cur_time - 1'b1;
			end
		end
	end
endmodule