data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_deserializer.v
data/verilator_xmls/3a3cb389-8510-49c0-983a-a87c3c581db5.xml
module stream_deserializer #(
  parameter DataBits = 8,
  parameter Ratio    = 2)
(
  input                       clk,
  input                       rst,

  input                       in_valid,
  output                      in_ready,
  input [DataBits-1:0]        in_data,

  output                      out_valid,
  input                       out_ready,
  output [Ratio*DataBits-1:0] out_data
);


  reg [(Ratio-1)*DataBits-1:0] data_r;
  reg [Ratio-1:0]              count;
  wire                         last = count[Ratio-1];
  integer                      i;

  always @(posedge clk) begin


    if (in_valid & in_ready) begin
      count <= last ? 1 : count << 1;
    end


    for (i=0; i < Ratio-1; i=i+1) begin
      if (count[i] && in_valid) begin

        data_r[i*DataBits +: DataBits] <= in_data;
      end
    end

    if (rst) begin
      count <= 1;
    end

  end

  assign in_ready   = last ? out_ready  : 1;
  assign out_valid  = last ? in_valid : 0;
  assign out_data   = {in_data, data_r};



endmodule
module stream_deserializer #(
  parameter DataBits = 8,
  parameter Ratio    = 2)
(
  input                       clk,
  input                       rst,

  input                       in_valid,
  output                      in_ready,
  input [DataBits-1:0]        in_data,

  output                      out_valid,
  input                       out_ready,
  output [Ratio*DataBits-1:0] out_data
);



  reg [(Ratio-1)*DataBits-1:0] data_r;
  reg [Ratio-1:0]              count;
  wire                         last = count[Ratio-1];
  integer                      i;

  always @(posedge clk) begin


    if (in_valid & in_ready) begin
      count <= last ? 1 : count << 1;
    end


    for (i=0; i < Ratio-1; i=i+1) begin
      if (count[i] && in_valid) begin

        data_r[i*DataBits +: DataBits] <= in_data;
      end
    end

    if (rst) begin
      count <= 1;
    end

  end

  assign in_ready   = last ? out_ready  : 1;
  assign out_valid  = last ? in_valid : 0;
  assign out_data   = {in_data, data_r};



endmodule