data/full_repos/permissive/216210370/soc/sim_lib/fpga_byte_spram.v
data/verilator_xmls/51d8da45-9059-4489-b03f-4f84d2af2e94.xml
module fpga_byte_spram(
  A,
  CEN,
  CLK,
  D,
  Q,
  WEN   
);

parameter  ADDRWIDTH = 17;
parameter  DATAWIDTH = 8;
parameter  MEMDEPTH  = 2**(ADDRWIDTH);


input   [(ADDRWIDTH-1) :0]  A;
input           CEN;
input           CLK;
input   [(DATAWIDTH-1):0]  D;
input           WEN;
output  [(DATAWIDTH-1):0]  Q;

reg     [(DATAWIDTH-1):0]  Q;
reg     [(DATAWIDTH-1):0]  mem[(MEMDEPTH-1):0];

always@(posedge CLK)
begin
  if(!CEN)
  begin
    if(!WEN)
    begin
      mem[A] <= D;
      Q      <= D;
    end
    else
    begin
      Q      <= mem[A];
    end
  end
end
endmodule
module fpga_byte_spram(
  A,
  CEN,
  CLK,
  D,
  Q,
  WEN   
);


parameter  ADDRWIDTH = 17;
parameter  DATAWIDTH = 8;
parameter  MEMDEPTH  = 2**(ADDRWIDTH);


input   [(ADDRWIDTH-1) :0]  A;
input           CEN;
input           CLK;
input   [(DATAWIDTH-1):0]  D;
input           WEN;
output  [(DATAWIDTH-1):0]  Q;

reg     [(DATAWIDTH-1):0]  Q;
reg     [(DATAWIDTH-1):0]  mem[(MEMDEPTH-1):0];

always@(posedge CLK)
begin
  if(!CEN)
  begin
    if(!WEN)
    begin
      mem[A] <= D;
      Q      <= D;
    end
    else
    begin
      Q      <= mem[A];
    end
  end
end
endmodule