data/full_repos/permissive/113582216/Experiment/design/digitSeg.v
data/verilator_xmls/0ab3e60d-1466-4520-bb49-fb655648b05a.xml
module digitSeg(
    input [3:0] bcd_i,
    output a_o,
    output b_o,
    output c_o,
    output d_o,
    output e_o,
    output f_o,
    output g_o
    );

    assign {a_o,b_o,c_o,d_o,e_o,f_o,g_o} =
        (bcd_i == 4'd0) ? 7'b0000001 :
        (bcd_i == 4'd1) ? 7'b1001111 :
        (bcd_i == 4'd2) ? 7'b0010010 :
        (bcd_i == 4'd3) ? 7'b0000110 :
        (bcd_i == 4'd4) ? 7'b1001100 :
        (bcd_i == 4'd5) ? 7'b0100100 :
        (bcd_i == 4'd6) ? 7'b0100000 :
        (bcd_i == 4'd7) ? 7'b0001111 :
        (bcd_i == 4'd8) ? 7'b0000000 :
        (bcd_i == 4'd9) ? 7'b0000100 :
        7'bx;

endmodule
module digitSeg(
    input [3:0] bcd_i,
    output a_o,
    output b_o,
    output c_o,
    output d_o,
    output e_o,
    output f_o,
    output g_o
    );


    assign {a_o,b_o,c_o,d_o,e_o,f_o,g_o} =
        (bcd_i == 4'd0) ? 7'b0000001 :
        (bcd_i == 4'd1) ? 7'b1001111 :
        (bcd_i == 4'd2) ? 7'b0010010 :
        (bcd_i == 4'd3) ? 7'b0000110 :
        (bcd_i == 4'd4) ? 7'b1001100 :
        (bcd_i == 4'd5) ? 7'b0100100 :
        (bcd_i == 4'd6) ? 7'b0100000 :
        (bcd_i == 4'd7) ? 7'b0001111 :
        (bcd_i == 4'd8) ? 7'b0000000 :
        (bcd_i == 4'd9) ? 7'b0000100 :
        7'bx;

endmodule