data/full_repos/permissive/174642777/Experiments/Lab X5/2.1 S2P_4bit/S2P_4bit_test.v
1: b'%Error: Cannot find file containing module: X5/2.1\n        ... Looked in:\n             data/full_repos/permissive/174642777/Experiments/Lab/X5/2.1\n             data/full_repos/permissive/174642777/Experiments/Lab/X5/2.1.v\n             data/full_repos/permissive/174642777/Experiments/Lab/X5/2.1.sv\n             X5/2.1\n             X5/2.1.v\n             X5/2.1.sv\n             obj_dir/X5/2.1\n             obj_dir/X5/2.1.v\n             obj_dir/X5/2.1.sv\n%Error: Cannot find file containing module: S2P_4bit,data/full_repos/permissive/174642777\n%Error: Cannot find file containing module: data/full_repos/permissive/174642777/Experiments/Lab\n%Error: Cannot find file containing module: S2P_4bit/S2P_4bit_test.v\n%Error: Exiting due to 4 error(s)\n'
module S2P_4bit_test;


	reg CLK;
	reg CLR;
	reg D;


	wire DR;
	wire [3:0] Q;


	S2P_4bit uut (
		.CLK(CLK), 
		.CLR(CLR), 
		.D(D), 
		.DR(DR), 
		.Q(Q)
	);

	initial begin

		CLK = 0;
		CLR = 0;
		D = 0;


		#100;
    

    #50 D=0; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    #50 D=0; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    
    #50 D=0; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    #50 D=0; CLK=1; #50; CLK=0;
    
    #50 D=1; CLK=1; #50; CLK=0;
    #50 D=0; CLK=1; #50; CLK=0;
    #50 D=0; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    
    #50 D=0; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    #50 D=0; CLK=1; #50; CLK=0;
	end
      
endmodule
module S2P_4bit_test;



	reg CLK;
	reg CLR;
	reg D;


	wire DR;
	wire [3:0] Q;


	S2P_4bit uut (
		.CLK(CLK), 
		.CLR(CLR), 
		.D(D), 
		.DR(DR), 
		.Q(Q)
	);

	initial begin

		CLK = 0;
		CLR = 0;
		D = 0;


		#100;
    

    #50 D=0; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    #50 D=0; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    
    #50 D=0; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    #50 D=0; CLK=1; #50; CLK=0;
    
    #50 D=1; CLK=1; #50; CLK=0;
    #50 D=0; CLK=1; #50; CLK=0;
    #50 D=0; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    
    #50 D=0; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    #50 D=1; CLK=1; #50; CLK=0;
    #50 D=0; CLK=1; #50; CLK=0;
	end
      
endmodule