data/full_repos/permissive/139213403/FPGA/mod_m_counter.v
data/verilator_xmls/e701517a-b7ef-4b2a-a9b2-0c6e419ab9ca.xml
module mod_m_counter
#(
	parameter M_BITS=8
)
(
	input wire clk, reset,
	input wire [M_BITS-1:0] m,
	output wire max_tick,
	output wire [M_BITS-1:0] q
);


reg [M_BITS-1:0] r_reg, r_next;
reg max_tick_reg, max_tick_next;



always @(posedge clk, posedge reset)
	if (reset)
		begin
			r_reg <= 0;
			max_tick_reg <= 0;
		end
	else
		begin
			r_reg <= r_next;
			max_tick_reg <= max_tick_next;
		end
		
always @*
	begin
		max_tick_next = max_tick_reg;
		begin
			r_next = r_reg;
			if (r_next == m)
				begin
					max_tick_next = 1'b1;
					r_next = 0;
				end
			else
				begin
					r_next = r_next + 1;
					max_tick_next = 0;
				end
		end
		
	end


assign q = r_reg;
assign max_tick = max_tick_reg;

endmodule
module mod_m_counter
#(
	parameter M_BITS=8
)
(
	input wire clk, reset,
	input wire [M_BITS-1:0] m,
	output wire max_tick,
	output wire [M_BITS-1:0] q
);



reg [M_BITS-1:0] r_reg, r_next;
reg max_tick_reg, max_tick_next;



always @(posedge clk, posedge reset)
	if (reset)
		begin
			r_reg <= 0;
			max_tick_reg <= 0;
		end
	else
		begin
			r_reg <= r_next;
			max_tick_reg <= max_tick_next;
		end
		
always @*
	begin
		max_tick_next = max_tick_reg;
		begin
			r_next = r_reg;
			if (r_next == m)
				begin
					max_tick_next = 1'b1;
					r_next = 0;
				end
			else
				begin
					r_next = r_next + 1;
					max_tick_next = 0;
				end
		end
		
	end


assign q = r_reg;
assign max_tick = max_tick_reg;

endmodule