data/full_repos/permissive/191827066/ikernels/verilog/last_heap_stage.v
data/verilator_xmls/06603a2e-aba8-4944-9135-061672fdd704.xml
module last_heap_stage #(
    parameter VALUE_WIDTH	= 32,
    parameter KEY_WIDTH 	= 32
) (
    input wire 			    ap_clk,
    input wire 			    ap_reset,

    input wire [KEY_WIDTH - 1:0]    key_test_in,
    input wire [KEY_WIDTH - 1:0]    key_in,
    input wire [VALUE_WIDTH - 1:0]  value_in,
    input wire 			    kv_in_valid,
    input wire 			    heap_read,


    output wire [KEY_WIDTH - 1:0]   key_out,
    output wire [VALUE_WIDTH - 1:0] value_out,
    output wire 		    kv_out_valid
);


localparam
  K_TEST      = 2'd0,
  V_TEST      = 2'd1,
  KV_WRITE    = 2'd2,
  PASSTHRU    = 2'd3;




  reg 				    kv_valid;
  reg 				    stage_valid;
  reg [KEY_WIDTH - 1:0] 	    key;
  reg [VALUE_WIDTH - 1:0] 	    value;


  

  reg [1:0] 			    hstate;
  wire 				    key_is_tested;
  wire 				    heap_entry_is_bubbled;

  assign kv_out_valid = kv_valid;

  assign key_out = key;
  assign value_out = value;
			
  always @(posedge ap_clk) begin
    
    if (ap_reset) begin
      key <= 0;
      value <= 0;
      kv_valid <= 0;
      hstate <= K_TEST;
      stage_valid <= 0;
    end
    
    else begin


      if (hstate == K_TEST) begin
	kv_valid <= 1'b0;
	
	if (heap_read) begin
	  hstate = PASSTHRU;
	  





	  key <= key_in;	
	  value <= value_in;
	end	    

	else if (kv_in_valid) begin
	  if (stage_valid & (key_test_in == key) | !stage_valid) begin
	    hstate = KV_WRITE;
	  end
	  else begin
	    hstate = V_TEST;
	  end
	end
      end
	
      else if (hstate == KV_WRITE) begin




	hstate = K_TEST;
	stage_valid <= 1'b1;
	

	key <= key_in;	
	value <= value_in;
	



      end
      
      else if (hstate == V_TEST) begin
	hstate = K_TEST;
	kv_valid <= 1'b1;

	
	if (value_in > value) begin


	  key <= key_in;	
	  value <= value_in;


	end
	else begin




	end
      end
	  
      else if (hstate == PASSTHRU) begin
	hstate = K_TEST;
	stage_valid <= 0;
	





	key <= key_in;	
	value <= value_in;
      end	
	
      else
	hstate = K_TEST;
      
    end
  end

endmodule
module last_heap_stage #(
    parameter VALUE_WIDTH	= 32,
    parameter KEY_WIDTH 	= 32
) (
    input wire 			    ap_clk,
    input wire 			    ap_reset,

    input wire [KEY_WIDTH - 1:0]    key_test_in,
    input wire [KEY_WIDTH - 1:0]    key_in,
    input wire [VALUE_WIDTH - 1:0]  value_in,
    input wire 			    kv_in_valid,
    input wire 			    heap_read,


    output wire [KEY_WIDTH - 1:0]   key_out,
    output wire [VALUE_WIDTH - 1:0] value_out,
    output wire 		    kv_out_valid
);



localparam
  K_TEST      = 2'd0,
  V_TEST      = 2'd1,
  KV_WRITE    = 2'd2,
  PASSTHRU    = 2'd3;




  reg 				    kv_valid;
  reg 				    stage_valid;
  reg [KEY_WIDTH - 1:0] 	    key;
  reg [VALUE_WIDTH - 1:0] 	    value;


  

  reg [1:0] 			    hstate;
  wire 				    key_is_tested;
  wire 				    heap_entry_is_bubbled;

  assign kv_out_valid = kv_valid;

  assign key_out = key;
  assign value_out = value;
			
  always @(posedge ap_clk) begin
    
    if (ap_reset) begin
      key <= 0;
      value <= 0;
      kv_valid <= 0;
      hstate <= K_TEST;
      stage_valid <= 0;
    end
    
    else begin


      if (hstate == K_TEST) begin
	kv_valid <= 1'b0;
	
	if (heap_read) begin
	  hstate = PASSTHRU;
	  





	  key <= key_in;	
	  value <= value_in;
	end	    

	else if (kv_in_valid) begin
	  if (stage_valid & (key_test_in == key) | !stage_valid) begin
	    hstate = KV_WRITE;
	  end
	  else begin
	    hstate = V_TEST;
	  end
	end
      end
	
      else if (hstate == KV_WRITE) begin




	hstate = K_TEST;
	stage_valid <= 1'b1;
	

	key <= key_in;	
	value <= value_in;
	



      end
      
      else if (hstate == V_TEST) begin
	hstate = K_TEST;
	kv_valid <= 1'b1;

	
	if (value_in > value) begin


	  key <= key_in;	
	  value <= value_in;


	end
	else begin




	end
      end
	  
      else if (hstate == PASSTHRU) begin
	hstate = K_TEST;
	stage_valid <= 0;
	





	key <= key_in;	
	value <= value_in;
      end	
	
      else
	hstate = K_TEST;
      
    end
  end

endmodule