data/full_repos/permissive/115771353/rtl/dpram/dpram.v
data/verilator_xmls/3fc3c751-677e-4786-a3eb-cd97a75aaa89.xml
module dpram #(
  parameter DATA_WIDTH = 8,
  parameter ADDR_WIDTH = 8,
  parameter RAM_DEPTH = (1 << ADDR_WIDTH)
)
(
  input  wire                  clk,
  input  wire [ADDR_WIDTH-1:0] WrAddress,
  input  wire [DATA_WIDTH-1:0] Data,
  input  wire                  WE,
  input  wire [ADDR_WIDTH-1:0] RdAddress,
  output wire [DATA_WIDTH-1:0] Q
); 

	

reg [DATA_WIDTH-1:0] data_1_out;
reg [DATA_WIDTH-1:0] Q_out;
reg [DATA_WIDTH-1:0] mem [RAM_DEPTH-1:0];




always @ (posedge clk)
begin : MEM_WRITE
  if ( WE ) begin
    mem[WrAddress] = Data;
  end
end




assign Q = data_1_out; 


always @ (posedge clk)
begin : MEM_READ_1
  data_1_out = mem[RdAddress]; 
end

endmodule
module dpram #(
  parameter DATA_WIDTH = 8,
  parameter ADDR_WIDTH = 8,
  parameter RAM_DEPTH = (1 << ADDR_WIDTH)
)
(
  input  wire                  clk,
  input  wire [ADDR_WIDTH-1:0] WrAddress,
  input  wire [DATA_WIDTH-1:0] Data,
  input  wire                  WE,
  input  wire [ADDR_WIDTH-1:0] RdAddress,
  output wire [DATA_WIDTH-1:0] Q
);
 

	

reg [DATA_WIDTH-1:0] data_1_out;
reg [DATA_WIDTH-1:0] Q_out;
reg [DATA_WIDTH-1:0] mem [RAM_DEPTH-1:0];




always @ (posedge clk)
begin : MEM_WRITE
  if ( WE ) begin
    mem[WrAddress] = Data;
  end
end




assign Q = data_1_out; 


always @ (posedge clk)
begin : MEM_READ_1
  data_1_out = mem[RdAddress]; 
end

endmodule