data/full_repos/permissive/133863909/Analysis of a Sequential Circuit/source.v
1: b'%Error: Cannot find file containing module: of\n        ... Looked in:\n             data/full_repos/permissive/133863909/Analysis/of\n             data/full_repos/permissive/133863909/Analysis/of.v\n             data/full_repos/permissive/133863909/Analysis/of.sv\n             of\n             of.v\n             of.sv\n             obj_dir/of\n             obj_dir/of.v\n             obj_dir/of.sv\n%Error: Cannot find file containing module: a\n%Error: Cannot find file containing module: Sequential\n%Error: Cannot find file containing module: Circuit,data/full_repos/permissive/133863909\n%Error: Cannot find file containing module: data/full_repos/permissive/133863909/Analysis\n%Error: Cannot find file containing module: Circuit/source.v\n%Error: Exiting due to 6 error(s)\n'
module analysis(output reg [1:0] output_y, input input_a, input input_b, input clock, input reset);

	reg [1:0] state, nextState;
	
	parameter output_00 = 2'b00, output_01 = 2'b01, output_10 = 2'b10, output_11 = 2'b11;
	parameter state_00 = 2'b00, state_01 = 2'b01, state_10 = 2'b10, state_11 = 2'b11;


	always @(posedge clock) begin
		if (reset == 1)
			state <= state_00;
		else
			state <= nextState;
	end
	

	always @(state, input_a, input_b) begin
	
		case(state)
			
			state_00: begin
			
				if (input_a == 0 && input_b == 0 ) begin
				
					nextState <= state_00;
					output_y <= output_00;
				
				end
				
				else if (input_a == 0 && input_b == 1 ) begin
					
					nextState <= state_01;
					output_y <= output_01;
				
				end
				
				else if (input_a == 1 && input_b == 0 ) begin
					
					nextState <= state_10;
					output_y <= output_10;
				
				end
				
				else begin
				
					nextState <= state_11;
					output_y <= output_10;
				
				end
				
			end			
			
			state_01: begin
			
				if (input_a == 0 && input_b == 0 ) begin
				
					nextState <= state_00;
					output_y <= output_00;
				
				end
				
				else if (input_a == 0 && input_b == 1 ) begin
				
					nextState <= state_00;
					output_y <= output_01;
				
				end
				
				else if (input_a == 1 && input_b == 0 ) begin
				
					nextState <= state_10;
					output_y <= output_10;
				
				end
				
				else begin
				
					nextState <= state_10;
					output_y <= output_10;
				
				end
				
			end
			
			state_10: begin
				
				if (input_a == 0 && input_b == 0 ) begin
					
					nextState <= state_00;
					output_y <= output_00;
					
				end
				
				else if (input_a == 0 && input_b == 1 ) begin
				
					nextState <= state_01;
					output_y <= output_01;
				
				end
				
				else if (input_a == 1 && input_b == 0 ) begin
				
					nextState <= state_10;
					output_y <= output_10;
				
				end
				
				else begin
				
					nextState <= state_01;
					output_y <= output_01;
				
				end
			end
			
			state_11: begin
			
				if (input_a == 0 && input_b == 0 ) begin
				
					nextState <= state_01;
					output_y <= output_01;
				
				end
				
				else if (input_a == 0 && input_b == 1 ) begin
				
					nextState <= state_01;
					output_y <= output_01;
				
				end
				
				else if (input_a == 1 && input_b == 0 ) begin
				
					nextState <= state_01;
					output_y <= output_01;
				
				end
				
				else begin
				
					nextState <= state_01;
					output_y <= output_01;
				
				end
			
			end
			
		endcase
	
	end
	

endmodule
module analysis(output reg [1:0] output_y, input input_a, input input_b, input clock, input reset);


	reg [1:0] state, nextState;
	
	parameter output_00 = 2'b00, output_01 = 2'b01, output_10 = 2'b10, output_11 = 2'b11;
	parameter state_00 = 2'b00, state_01 = 2'b01, state_10 = 2'b10, state_11 = 2'b11;


	always @(posedge clock) begin
		if (reset == 1)
			state <= state_00;
		else
			state <= nextState;
	end
	

	always @(state, input_a, input_b) begin
	
		case(state)
			
			state_00: begin
			
				if (input_a == 0 && input_b == 0 ) begin
				
					nextState <= state_00;
					output_y <= output_00;
				
				end
				
				else if (input_a == 0 && input_b == 1 ) begin
					
					nextState <= state_01;
					output_y <= output_01;
				
				end
				
				else if (input_a == 1 && input_b == 0 ) begin
					
					nextState <= state_10;
					output_y <= output_10;
				
				end
				
				else begin
				
					nextState <= state_11;
					output_y <= output_10;
				
				end
				
			end			
			
			state_01: begin
			
				if (input_a == 0 && input_b == 0 ) begin
				
					nextState <= state_00;
					output_y <= output_00;
				
				end
				
				else if (input_a == 0 && input_b == 1 ) begin
				
					nextState <= state_00;
					output_y <= output_01;
				
				end
				
				else if (input_a == 1 && input_b == 0 ) begin
				
					nextState <= state_10;
					output_y <= output_10;
				
				end
				
				else begin
				
					nextState <= state_10;
					output_y <= output_10;
				
				end
				
			end
			
			state_10: begin
				
				if (input_a == 0 && input_b == 0 ) begin
					
					nextState <= state_00;
					output_y <= output_00;
					
				end
				
				else if (input_a == 0 && input_b == 1 ) begin
				
					nextState <= state_01;
					output_y <= output_01;
				
				end
				
				else if (input_a == 1 && input_b == 0 ) begin
				
					nextState <= state_10;
					output_y <= output_10;
				
				end
				
				else begin
				
					nextState <= state_01;
					output_y <= output_01;
				
				end
			end
			
			state_11: begin
			
				if (input_a == 0 && input_b == 0 ) begin
				
					nextState <= state_01;
					output_y <= output_01;
				
				end
				
				else if (input_a == 0 && input_b == 1 ) begin
				
					nextState <= state_01;
					output_y <= output_01;
				
				end
				
				else if (input_a == 1 && input_b == 0 ) begin
				
					nextState <= state_01;
					output_y <= output_01;
				
				end
				
				else begin
				
					nextState <= state_01;
					output_y <= output_01;
				
				end
			
			end
			
		endcase
	
	end
	

endmodule