data/full_repos/permissive/212897440/top.v
1: b"%Error: data/full_repos/permissive/212897440/top.v:71: Cannot find file containing module: 'clk_wiz_0'\nclk_wiz_0 m_clk(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/clk_wiz_0\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/clk_wiz_0.v\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/clk_wiz_0.sv\n             clk_wiz_0\n             clk_wiz_0.v\n             clk_wiz_0.sv\n             obj_dir/clk_wiz_0\n             obj_dir/clk_wiz_0.v\n             obj_dir/clk_wiz_0.sv\n%Error: data/full_repos/permissive/212897440/top.v:80: Cannot find file containing module: 'd_flipflop_sync_rst'\nd_flipflop_sync_rst D_flipflop1 (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/212897440/top.v:86: Cannot find file containing module: 'd_flipflop_sync_rst'\nd_flipflop_sync_rst D_flipflop2 (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/212897440/top.v:92: Cannot find file containing module: 'd_flipflop_sync_rst'\nd_flipflop_sync_rst D_flipflop3 (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/212897440/top.v:100: Cannot find file containing module: 'io_module'\nio_module  #(\n^~~~~~~~~\n%Error: data/full_repos/permissive/212897440/top.v:137: Cannot find file containing module: 'effect_controler'\neffect_controler #(\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/212897440/top.v:165: Cannot find file containing module: 'effect_module'\neffect_module #(\n^~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module top #( parameter
    sclk_ws_ratio = 64,
    mclk_sclk_ratio = 4,
    d_width = 24,
    memory_d_width = 16
)(
    input           clk,
    input           btnC,
    output  [15:0]  led, 

    input   [15:0]   sw,
    output          da_mclk,
    output          ad_mclk,
    output          da_sclk,
    output          ad_sclk,
    output          da_lrck,
    output          ad_lrck,
    input           ad_sdout,
    output          da_sdin,
    output  [7: 0]  JXADC
    );


assign led = l_data_tx[d_width-1: d_width-16];

assign da_mclk = master_clk;
assign ad_mclk = master_clk;




wire master_clk;

wire clk_50MHz;

wire                w_reset, w_reset1, w_reset2;
wire                w_internal_reset;

wire signed [d_width-1: 0] r_data_tx;
wire signed [d_width-1: 0] l_data_tx;
wire signed [d_width-1: 0] r_data_rx;
wire signed [d_width-1: 0] l_data_rx;


wire [d_width-1: 0] w_data_to_eff;
wire                w_dv_to_eff;  

wire                w_dv_from_eff; 
wire                w_rd_en_from_eff;

wire                w_read_done_eff;
wire                w_read_ready_eff;


wire [d_width-1: 0] w_data_from_eff_sw0;
wire [d_width-1: 0] w_data_from_eff_sw1;









clk_wiz_0 m_clk(
    .clk_in1(clk),
    .clk_out1(master_clk),
    .clk_out2(clk_50MHz),
    .locked(w_internal_reset),
    .reset(btnC)
);


d_flipflop_sync_rst D_flipflop1 (
    .D(1'b0),
    .Q(w_reset1),
    .clk(master_clk),
    .reset(~w_internal_reset));

d_flipflop_sync_rst D_flipflop2 (
    .D(w_reset1),
    .Q(w_reset2),
    .clk(master_clk),
    .reset(~w_internal_reset));

d_flipflop_sync_rst D_flipflop3 (
    .D(w_reset2),
    .Q(w_reset),
    .clk(master_clk),
    .reset(~w_internal_reset));



io_module  #(
    .mclk_sclk_ratio(mclk_sclk_ratio),
    .sclk_ws_ratio(sclk_ws_ratio),
    .d_width(d_width)
) io_module (

    .mclk(master_clk),
    .da_sclk(da_sclk),
    .da_ws(da_lrck),
    .ad_sclk(ad_sclk),
    .ad_ws(ad_lrck),
    .sd_tx(da_sdin),
    .sd_rx(ad_sdout),
    .l_data_tx(l_data_tx),
    .r_data_tx(r_data_tx),

    .reset(w_reset),

    .l_data_rx(l_data_rx),
    .r_data_rx(r_data_rx),












    .JXADC(JXADC)
);



effect_controler #(
    .d_width(d_width),
    .memory_d_width(memory_d_width)
) effect_controler (
    .reset(w_reset),
    .mclk(master_clk),
    .sw(sw[1:0]),
    .clk(clk_50MHz),
    .i_l_data(l_data_rx),
    .i_r_data(r_data_rx),


    .o_l_data(l_data_tx),
    .o_r_data(r_data_tx),
    .o_read_done(w_read_done_eff),
    .o_read_ready(w_read_ready_eff),

    .o_data_to_eff(w_data_to_eff),
    .o_data_valid(w_dv_to_eff),
    
    .i_read_enable(w_rd_en_from_eff),
    .i_dv_from_eff(w_dv_from_eff),
    .i_data_from_eff_sw0(w_data_from_eff_sw0),
    .i_data_from_eff_sw1(w_data_from_eff_sw1)
);



effect_module #(
    .d_width(memory_d_width)
) effect_module (
    .clk(clk_50MHz),
    .reset(w_reset),
    .sw(sw[1:0]),
    .i_treshhold(sw[15:2]),
    .i_data_ready(w_dv_to_eff),
    .i_read_done(w_read_done_eff),
    .i_data(w_data_to_eff),
    .o_read_enable(w_rd_en_from_eff),
    .o_data_valid(w_dv_from_eff),
    .o_data_sw0(w_data_from_eff_sw0),
    .o_data_sw1(w_data_from_eff_sw1)

);


endmodule
module top #( parameter
    sclk_ws_ratio = 64,
    mclk_sclk_ratio = 4,
    d_width = 24,
    memory_d_width = 16
)(
    input           clk,
    input           btnC,
    output  [15:0]  led, 

    input   [15:0]   sw,
    output          da_mclk,
    output          ad_mclk,
    output          da_sclk,
    output          ad_sclk,
    output          da_lrck,
    output          ad_lrck,
    input           ad_sdout,
    output          da_sdin,
    output  [7: 0]  JXADC
    );



assign led = l_data_tx[d_width-1: d_width-16];

assign da_mclk = master_clk;
assign ad_mclk = master_clk;




wire master_clk;

wire clk_50MHz;

wire                w_reset, w_reset1, w_reset2;
wire                w_internal_reset;

wire signed [d_width-1: 0] r_data_tx;
wire signed [d_width-1: 0] l_data_tx;
wire signed [d_width-1: 0] r_data_rx;
wire signed [d_width-1: 0] l_data_rx;


wire [d_width-1: 0] w_data_to_eff;
wire                w_dv_to_eff;  

wire                w_dv_from_eff; 
wire                w_rd_en_from_eff;

wire                w_read_done_eff;
wire                w_read_ready_eff;


wire [d_width-1: 0] w_data_from_eff_sw0;
wire [d_width-1: 0] w_data_from_eff_sw1;









clk_wiz_0 m_clk(
    .clk_in1(clk),
    .clk_out1(master_clk),
    .clk_out2(clk_50MHz),
    .locked(w_internal_reset),
    .reset(btnC)
);


d_flipflop_sync_rst D_flipflop1 (
    .D(1'b0),
    .Q(w_reset1),
    .clk(master_clk),
    .reset(~w_internal_reset));

d_flipflop_sync_rst D_flipflop2 (
    .D(w_reset1),
    .Q(w_reset2),
    .clk(master_clk),
    .reset(~w_internal_reset));

d_flipflop_sync_rst D_flipflop3 (
    .D(w_reset2),
    .Q(w_reset),
    .clk(master_clk),
    .reset(~w_internal_reset));



io_module  #(
    .mclk_sclk_ratio(mclk_sclk_ratio),
    .sclk_ws_ratio(sclk_ws_ratio),
    .d_width(d_width)
) io_module (

    .mclk(master_clk),
    .da_sclk(da_sclk),
    .da_ws(da_lrck),
    .ad_sclk(ad_sclk),
    .ad_ws(ad_lrck),
    .sd_tx(da_sdin),
    .sd_rx(ad_sdout),
    .l_data_tx(l_data_tx),
    .r_data_tx(r_data_tx),

    .reset(w_reset),

    .l_data_rx(l_data_rx),
    .r_data_rx(r_data_rx),












    .JXADC(JXADC)
);



effect_controler #(
    .d_width(d_width),
    .memory_d_width(memory_d_width)
) effect_controler (
    .reset(w_reset),
    .mclk(master_clk),
    .sw(sw[1:0]),
    .clk(clk_50MHz),
    .i_l_data(l_data_rx),
    .i_r_data(r_data_rx),


    .o_l_data(l_data_tx),
    .o_r_data(r_data_tx),
    .o_read_done(w_read_done_eff),
    .o_read_ready(w_read_ready_eff),

    .o_data_to_eff(w_data_to_eff),
    .o_data_valid(w_dv_to_eff),
    
    .i_read_enable(w_rd_en_from_eff),
    .i_dv_from_eff(w_dv_from_eff),
    .i_data_from_eff_sw0(w_data_from_eff_sw0),
    .i_data_from_eff_sw1(w_data_from_eff_sw1)
);



effect_module #(
    .d_width(memory_d_width)
) effect_module (
    .clk(clk_50MHz),
    .reset(w_reset),
    .sw(sw[1:0]),
    .i_treshhold(sw[15:2]),
    .i_data_ready(w_dv_to_eff),
    .i_read_done(w_read_done_eff),
    .i_data(w_data_to_eff),
    .o_read_enable(w_rd_en_from_eff),
    .o_data_valid(w_dv_from_eff),
    .o_data_sw0(w_data_from_eff_sw0),
    .o_data_sw1(w_data_from_eff_sw1)

);


endmodule