data/full_repos/permissive/187199324/stannel/Send.v
1: b'%Error: data/full_repos/permissive/187199324/stannel/Send.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:4: Define or directive not defined: \'`ADDRESS_BITS\'\nmodule Send #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (\n                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:4: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nmodule Send #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (\n                                                 ^\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:4: Define or directive not defined: \'`DATA_BITS\'\nmodule Send #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (\n                                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:4: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule Send #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (\n                                                                                   ^\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:7: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                reset,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:8: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                 finished,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:10: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg  [addrBits-1:0] address,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:11: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                 readWriteMode,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:13: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire [dataBits-1:0] dataOut,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg  [dataBits-1:0] dataIn,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:17: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire [addrBits-1:0] channel,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [dataBits-1:0] message,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [addrBits-1:0] txPid,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [`CELL_COUNT:0] alternationSet,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:20: Define or directive not defined: \'`CELL_COUNT\'\n    input  wire [`CELL_COUNT:0] alternationSet,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:21: Define or directive not defined: \'`CELL_COUNT\'\n    input  wire [`CELL_COUNT:0] alternationReadySet,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:24: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                 shouldDescheduleSender,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg  [addrBits-1:0] scheduleRxPid,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:26: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                 addToAlternationReadySet,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg  [dataBits-1:0] deliveredMessage\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:30: syntax error, unexpected \')\', expecting \',\' or \';\'\n  );\n  ^\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:36: Define or directive not defined: \'`CELL_COUNT\'\n  wire [`CELL_COUNT:0] alternationFlag = `CELL_COUNT_CONST_1 << scheduleRxPid;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:36: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  wire [`CELL_COUNT:0] alternationFlag = `CELL_COUNT_CONST_1 << scheduleRxPid;\n                   ^\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:36: Define or directive not defined: \'`CELL_COUNT_CONST_1\'\n  wire [`CELL_COUNT:0] alternationFlag = `CELL_COUNT_CONST_1 << scheduleRxPid;\n                                         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:68: syntax error, unexpected always\n  always @(posedge clk)\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:107: Define or directive not defined: \'`RAM_READ\'\n    readWriteMode             = `RAM_READ;\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:134: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode     = `RAM_WRITE;\n                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:168: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode = `RAM_WRITE;\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:175: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode = `RAM_WRITE;\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:182: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode = `RAM_WRITE;\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:189: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode = `RAM_WRITE;\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send.v:196: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode = `RAM_WRITE;\n                          ^~~~~~~~~~\n%Error: Exiting due to 33 error(s)\n'
module Send #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    output reg                 finished,

    output reg  [addrBits-1:0] address,
    output reg                 readWriteMode,

    input  wire [dataBits-1:0] dataOut,

    output reg  [dataBits-1:0] dataIn,

    input  wire [addrBits-1:0] channel,
    input  wire [dataBits-1:0] message,
    input  wire [addrBits-1:0] txPid,
    input  wire [`CELL_COUNT:0] alternationSet,
    input  wire [`CELL_COUNT:0] alternationReadySet,

    output reg                 shouldScheduleReceiver,
    output reg                 shouldDescheduleSender,
    output reg  [addrBits-1:0] scheduleRxPid,
    output reg                 addToAlternationReadySet,


    output reg  [dataBits-1:0] deliveredMessage
  );


  wire [addrBits-1:0] messageAddress = channel + 1;


  wire [`CELL_COUNT:0] alternationFlag = `CELL_COUNT_CONST_1 << scheduleRxPid;
  wire inAlternationSet = (alternationSet & alternationFlag) != 0;
  wire inAlternationReadySet = (alternationReadySet & alternationFlag) != 0;



  localparam STATE_INIT            = 3'd0;
  localparam STATE_READ_RX_PROC    = 3'd1;
  localparam STATE_HANDLE_RX_PROC  = 3'd2;
  localparam STATE_NULL_RX_PROC    = 3'd3;
  localparam STATE_ALT_RX_PROC     = 3'd4;
  localparam STATE_NORMAL_RX_PROC  = 3'd5;
  localparam STATE_WRITE_TX_PROC_0 = 3'd6;
  localparam STATE_WRITE_TX_PROC_1 = 3'd7;

  reg [2:0] rState;
  reg [dataBits-1:0] rPidToWrite;



  reg        wSaveMessage;
  reg        wFinished;
  reg [2:0]  wNextState;
  reg        wUpdateRxPid;
  reg        wShouldScheduleReceiver;
  reg        wShouldDescheduleSender;
  reg        wAddToAlternationReadySet;

  reg                wUpdatePidToWrite;
  reg [dataBits-1:0] wPidToWrite;


  always @(posedge clk)
  begin
    if (!reset)
      begin
        rState                   <= STATE_INIT;
        rPidToWrite              <= 0;
        shouldScheduleReceiver   <= 0;
        shouldDescheduleSender   <= 0;
        finished                 <= 0;
        addToAlternationReadySet <= 0;
      end
    else
      begin
        rState <= wNextState;
        finished <= wFinished;

        if (wUpdateRxPid)
          scheduleRxPid <= dataOut[7:0];

        if (wShouldScheduleReceiver)
          shouldScheduleReceiver <= 1;

        if (wShouldDescheduleSender)
          shouldDescheduleSender <= 1;

        if (wUpdatePidToWrite)
          rPidToWrite <= wPidToWrite;

        if (wSaveMessage)
          deliveredMessage <= message;
        addToAlternationReadySet <= wAddToAlternationReadySet;
      end
  end


  always @(*)
  begin
    address                   = {addrBits{1'bx}};
    dataIn                    = {dataBits{1'bx}};
    readWriteMode             = `RAM_READ;
    wFinished                 = 0;
    wUpdateRxPid              = 0;
    wSaveMessage              = 0;
    wShouldScheduleReceiver   = 0;
    wShouldDescheduleSender   = 0;
    wUpdatePidToWrite         = 0;
    wPidToWrite               = {dataBits{1'bx}};
    wNextState                = rState;
    wAddToAlternationReadySet = addToAlternationReadySet;
    case (rState)
      STATE_INIT:
        begin
          address = channel;
          wNextState = STATE_READ_RX_PROC;
          wSaveMessage = 1;
        end
      STATE_READ_RX_PROC:
        begin
          address = channel;
          wUpdateRxPid = 1;
          wNextState = STATE_HANDLE_RX_PROC;
        end
      STATE_HANDLE_RX_PROC:
        begin
          address           = messageAddress;
          dataIn            = message;
          readWriteMode     = `RAM_WRITE;
          wUpdatePidToWrite = 1;
          wPidToWrite = {8'b0, txPid};
          if (scheduleRxPid == 0)
            begin
              wNextState = STATE_NULL_RX_PROC;
              wShouldDescheduleSender = 1;
            end
          else if (inAlternationSet && ~inAlternationReadySet)
            begin
              wAddToAlternationReadySet = 1;
              wNextState = STATE_ALT_RX_PROC;
              wShouldScheduleReceiver = ~inAlternationReadySet;


              wShouldDescheduleSender = 1;
            end
          else
            begin
              wNextState = STATE_NORMAL_RX_PROC;


              wShouldScheduleReceiver = ~inAlternationReadySet;



              wShouldDescheduleSender = inAlternationReadySet;
              wPidToWrite = 0;
            end
        end
      STATE_NULL_RX_PROC:
        begin
          address       = messageAddress;
          dataIn        = message;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_WRITE_TX_PROC_0;
        end
      STATE_ALT_RX_PROC:
        begin
          address       = messageAddress;
          dataIn        = message;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_WRITE_TX_PROC_0;
        end
      STATE_NORMAL_RX_PROC:
        begin
          address       = messageAddress;
          dataIn        = message;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_WRITE_TX_PROC_1;
        end
      STATE_WRITE_TX_PROC_0:
        begin
          address       = channel;
          dataIn        = rPidToWrite;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_WRITE_TX_PROC_1;
        end
      STATE_WRITE_TX_PROC_1:
        begin
          address       = channel;
          dataIn        = rPidToWrite;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_INIT;
          wFinished     = 1;
        end
      default:
        begin
        end
    endcase
  end

endmodule
module Send #(parameter addrBits  = `ADDRESS_BITS, parameter dataBits  = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    output reg                 finished,

    output reg  [addrBits-1:0] address,
    output reg                 readWriteMode,

    input  wire [dataBits-1:0] dataOut,

    output reg  [dataBits-1:0] dataIn,

    input  wire [addrBits-1:0] channel,
    input  wire [dataBits-1:0] message,
    input  wire [addrBits-1:0] txPid,
    input  wire [`CELL_COUNT:0] alternationSet,
    input  wire [`CELL_COUNT:0] alternationReadySet,

    output reg                 shouldScheduleReceiver,
    output reg                 shouldDescheduleSender,
    output reg  [addrBits-1:0] scheduleRxPid,
    output reg                 addToAlternationReadySet,


    output reg  [dataBits-1:0] deliveredMessage
  );



  wire [addrBits-1:0] messageAddress = channel + 1;


  wire [`CELL_COUNT:0] alternationFlag = `CELL_COUNT_CONST_1 << scheduleRxPid;
  wire inAlternationSet = (alternationSet & alternationFlag) != 0;
  wire inAlternationReadySet = (alternationReadySet & alternationFlag) != 0;



  localparam STATE_INIT            = 3'd0;
  localparam STATE_READ_RX_PROC    = 3'd1;
  localparam STATE_HANDLE_RX_PROC  = 3'd2;
  localparam STATE_NULL_RX_PROC    = 3'd3;
  localparam STATE_ALT_RX_PROC     = 3'd4;
  localparam STATE_NORMAL_RX_PROC  = 3'd5;
  localparam STATE_WRITE_TX_PROC_0 = 3'd6;
  localparam STATE_WRITE_TX_PROC_1 = 3'd7;

  reg [2:0] rState;
  reg [dataBits-1:0] rPidToWrite;



  reg        wSaveMessage;
  reg        wFinished;
  reg [2:0]  wNextState;
  reg        wUpdateRxPid;
  reg        wShouldScheduleReceiver;
  reg        wShouldDescheduleSender;
  reg        wAddToAlternationReadySet;

  reg                wUpdatePidToWrite;
  reg [dataBits-1:0] wPidToWrite;


  always @(posedge clk)
  begin
    if (!reset)
      begin
        rState                   <= STATE_INIT;
        rPidToWrite              <= 0;
        shouldScheduleReceiver   <= 0;
        shouldDescheduleSender   <= 0;
        finished                 <= 0;
        addToAlternationReadySet <= 0;
      end
    else
      begin
        rState <= wNextState;
        finished <= wFinished;

        if (wUpdateRxPid)
          scheduleRxPid <= dataOut[7:0];

        if (wShouldScheduleReceiver)
          shouldScheduleReceiver <= 1;

        if (wShouldDescheduleSender)
          shouldDescheduleSender <= 1;

        if (wUpdatePidToWrite)
          rPidToWrite <= wPidToWrite;

        if (wSaveMessage)
          deliveredMessage <= message;
        addToAlternationReadySet <= wAddToAlternationReadySet;
      end
  end


  always @(*)
  begin
    address                   = {addrBits{1'bx}};
    dataIn                    = {dataBits{1'bx}};
    readWriteMode             = `RAM_READ;
    wFinished                 = 0;
    wUpdateRxPid              = 0;
    wSaveMessage              = 0;
    wShouldScheduleReceiver   = 0;
    wShouldDescheduleSender   = 0;
    wUpdatePidToWrite         = 0;
    wPidToWrite               = {dataBits{1'bx}};
    wNextState                = rState;
    wAddToAlternationReadySet = addToAlternationReadySet;
    case (rState)
      STATE_INIT:
        begin
          address = channel;
          wNextState = STATE_READ_RX_PROC;
          wSaveMessage = 1;
        end
      STATE_READ_RX_PROC:
        begin
          address = channel;
          wUpdateRxPid = 1;
          wNextState = STATE_HANDLE_RX_PROC;
        end
      STATE_HANDLE_RX_PROC:
        begin
          address           = messageAddress;
          dataIn            = message;
          readWriteMode     = `RAM_WRITE;
          wUpdatePidToWrite = 1;
          wPidToWrite = {8'b0, txPid};
          if (scheduleRxPid == 0)
            begin
              wNextState = STATE_NULL_RX_PROC;
              wShouldDescheduleSender = 1;
            end
          else if (inAlternationSet && ~inAlternationReadySet)
            begin
              wAddToAlternationReadySet = 1;
              wNextState = STATE_ALT_RX_PROC;
              wShouldScheduleReceiver = ~inAlternationReadySet;


              wShouldDescheduleSender = 1;
            end
          else
            begin
              wNextState = STATE_NORMAL_RX_PROC;


              wShouldScheduleReceiver = ~inAlternationReadySet;



              wShouldDescheduleSender = inAlternationReadySet;
              wPidToWrite = 0;
            end
        end
      STATE_NULL_RX_PROC:
        begin
          address       = messageAddress;
          dataIn        = message;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_WRITE_TX_PROC_0;
        end
      STATE_ALT_RX_PROC:
        begin
          address       = messageAddress;
          dataIn        = message;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_WRITE_TX_PROC_0;
        end
      STATE_NORMAL_RX_PROC:
        begin
          address       = messageAddress;
          dataIn        = message;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_WRITE_TX_PROC_1;
        end
      STATE_WRITE_TX_PROC_0:
        begin
          address       = channel;
          dataIn        = rPidToWrite;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_WRITE_TX_PROC_1;
        end
      STATE_WRITE_TX_PROC_1:
        begin
          address       = channel;
          dataIn        = rPidToWrite;
          readWriteMode = `RAM_WRITE;
          wNextState    = STATE_INIT;
          wFinished     = 1;
        end
      default:
        begin
        end
    endcase
  end

endmodule