data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/control_unit.v
data/verilator_xmls/d72f9c1c-a90f-4b6d-8be5-4c462143fda2.xml
module control_unit(input clk, input wire [5:0] instruction, output reg reg_dst, output reg jump, output reg branch, output reg mem_read, 
                    output reg mem_to_reg, output reg [1:0] alu_op, output reg mem_write, output reg alu_src, output reg reg_write);
    
    always@(negedge clk) begin
        case(instruction)

            6'b000000: begin
                reg_dst=1; 
                alu_src=0;
                mem_to_reg=0;
                reg_write=1;
                mem_read=0;
                mem_write=0;
                branch=0;
                jump=0;
                alu_op=2'b10;
            end

            6'b100011: begin
                reg_dst=0; 
                alu_src=1;
                mem_to_reg=1;
                reg_write=1;
                mem_read=1;
                mem_write=0;
                branch=0;
                jump=0;
                alu_op=2'b00;
            end

            6'b101011: begin
                reg_dst=1'bx; 
                alu_src=1;
                mem_to_reg=1'bx;
                reg_write=0;
                mem_read=0;
                mem_write=1;
                branch=0;
                jump=0;
                alu_op=2'b00;
            end

            6'b000100: begin
                reg_dst=1'bx; 
                alu_src=0;
                mem_to_reg=1'bx;
                reg_write=0;
                mem_read=0;
                mem_write=0;
                branch=1;
                jump=0;
                alu_op=2'b01;
            end

            6'b000010: begin
                reg_dst=1'bx; 
                alu_src=0;
                mem_to_reg=1'bx;
                reg_write=0;
                mem_read=0;
                mem_write=0;
                branch=0;
                jump=1;
                alu_op=2'b01;
            end            
        endcase
    end            
endmodule
module control_unit(input clk, input wire [5:0] instruction, output reg reg_dst, output reg jump, output reg branch, output reg mem_read, 
                    output reg mem_to_reg, output reg [1:0] alu_op, output reg mem_write, output reg alu_src, output reg reg_write);

    
    always@(negedge clk) begin
        case(instruction)

            6'b000000: begin
                reg_dst=1; 
                alu_src=0;
                mem_to_reg=0;
                reg_write=1;
                mem_read=0;
                mem_write=0;
                branch=0;
                jump=0;
                alu_op=2'b10;
            end

            6'b100011: begin
                reg_dst=0; 
                alu_src=1;
                mem_to_reg=1;
                reg_write=1;
                mem_read=1;
                mem_write=0;
                branch=0;
                jump=0;
                alu_op=2'b00;
            end

            6'b101011: begin
                reg_dst=1'bx; 
                alu_src=1;
                mem_to_reg=1'bx;
                reg_write=0;
                mem_read=0;
                mem_write=1;
                branch=0;
                jump=0;
                alu_op=2'b00;
            end

            6'b000100: begin
                reg_dst=1'bx; 
                alu_src=0;
                mem_to_reg=1'bx;
                reg_write=0;
                mem_read=0;
                mem_write=0;
                branch=1;
                jump=0;
                alu_op=2'b01;
            end

            6'b000010: begin
                reg_dst=1'bx; 
                alu_src=0;
                mem_to_reg=1'bx;
                reg_write=0;
                mem_read=0;
                mem_write=0;
                branch=0;
                jump=1;
                alu_op=2'b01;
            end            
        endcase
    end            
endmodule