data/full_repos/permissive/214823094/lab_7/project_1/project_1.srcs/sources_1/new/bus.v
data/verilator_xmls/7f7dd0f0-285f-46b7-bf12-d5571dcce98b.xml
module register(
    input myclk,
    input en,
    input [3:0] d,
    output reg [3:0] q
    );
    
    always@(posedge myclk,posedge en)
    begin
        if(en)
            q<=d;
    end

endmodule
module register(
    input myclk,
    input en,
    input [3:0] d,
    output reg [3:0] q
    );

    
    always@(posedge myclk,posedge en)
    begin
        if(en)
            q<=d;
    end

endmodule