data/full_repos/permissive/135820056/rtl/EEPROM_STM95.sv
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1: b'%Warning-WIDTH: data/full_repos/permissive/135820056/rtl/EEPROM_STM95.sv:81: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'3\'h7\' generates 3 bits.\n                                                                           : ... In instance STM95XXX\n    if (bit_count == 3\'h7) begin\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module STM95XXX
(
	input clk,
	input enable,

	output        so,
	input         si,
	input         sck,
	input         hold_n,
	input         cs_n,
	input         wp_n,

	output [11:0] ram_addr,
	input  [7:0]  ram_q,
	output [7:0]  ram_di,
	output        ram_RnW
);

assign ram_di = data_out;
assign ram_addr = address[11:0];
assign ram_RnW = ram_write;
assign so = bit_out;

localparam ADDRESS_LEN = 32'hF;
localparam ROM_SIZE = 'hFFF;


localparam WRSR  = 8'b0000_0001;
localparam WRITE = 8'b0000_0010;
localparam READ  = 8'b0000_0011;
localparam WRDI  = 8'b0000_0100;
localparam RDSR  = 8'b0000_0101;
localparam WREN  = 8'b0000_0110;

enum bit [2:0] {
	M95_IDLE,
	M95_WRSR,
	M95_WRITE,
	M95_READ,
	M95_RDSR,
	M95_WAIT
} state;

int bit_count;

logic [15:0] address;
logic [7:0] data_in, data_out;
logic [2:0] byte_ptr;
logic old_sck;
logic bit_out;
logic ram_write;


logic [7:0] status;
logic WEL;
logic WIP;
logic SRWD, BP1, BP0;

always_ff @(posedge clk) begin
	if (~enable || (~hold_n && cs_n)) begin
		state <= M95_IDLE;
		data_in <= 8'b0;
		WIP <= 1'b0;
		WEL <= 1'b0;
		SRWD <= 1'b0;
		BP1 <= 1'b0;
		BP0 <= 1'b0;
	end else begin

	old_sck <= sck;
	if (~old_sck & sck & hold_n & ~cs_n) begin
		case (state)
			M95_IDLE: begin
				bit_count <= bit_count + 1'b1;
				data_in <= {data_in[6:0], si};
				ram_write <= 1'b0;
				if (bit_count == 3'h7) begin
					bit_count <= 0;
					data_in <= 8'h0;
					byte_ptr <= 3'h7;
					case ({data_in[6:0], si})
						WRSR: begin
							if (WEL) begin
								state <= M95_WRSR;
							end
							WEL <= 1'b0;
						end

						WRITE: begin
							if (WEL) begin
								state <= M95_WRITE;
							end
							WEL <= 1'b0;
						end

						READ: begin
							state <= M95_READ;
						end

						WRDI: begin
							WEL <= 1'b0;
						end

						RDSR: begin
							state <= M95_RDSR;
							status <= {SRWD, 3'b000, BP1, BP0, WEL, WIP};
						end

						WREN: begin
							WEL <= 1'b1;
						end

						default: begin
							state <= M95_WAIT;
						end
					endcase
				end
			end

			M95_WRSR: begin
				status[byte_ptr] <= si;
				byte_ptr <= byte_ptr - 1'b1;
				WEL <= status[1];



			end

			M95_RDSR: begin
				byte_ptr <= byte_ptr - 1'b1;
				bit_out <= status[byte_ptr];
			end

			M95_READ: begin
				if (bit_count <= ADDRESS_LEN) begin
					address <= {address[14:0], si};
					bit_count <= bit_count + 1'b1;
				end else begin
					byte_ptr <= byte_ptr - 1'b1;
					bit_out <= ram_q[byte_ptr];
					if (byte_ptr == 0)
						address <= (address == ROM_SIZE) ? 16'h0 : address + 1'b1;
				end
			end

			M95_WRITE: begin
				if (bit_count <= ADDRESS_LEN) begin
					address <= {address[14:0], si};
					bit_count <= bit_count + 1'b1;
				end else begin
					byte_ptr <= byte_ptr - 1'b1;
					data_out[byte_ptr] <= si;
					ram_write <= (byte_ptr == 0);
					if (ram_write)
						address <= (address == ROM_SIZE) ? 16'h0 : address + 1'b1;
				end
			end

			default:;
		endcase

	end
	if (cs_n) begin
		state <= M95_IDLE;
		bit_count <= 0;
		bit_out <= 1'b1;
	end
	end
end
endmodule
module STM95XXX
(
	input clk,
	input enable,

	output        so,
	input         si,
	input         sck,
	input         hold_n,
	input         cs_n,
	input         wp_n,

	output [11:0] ram_addr,
	input  [7:0]  ram_q,
	output [7:0]  ram_di,
	output        ram_RnW
);


assign ram_di = data_out;
assign ram_addr = address[11:0];
assign ram_RnW = ram_write;
assign so = bit_out;

localparam ADDRESS_LEN = 32'hF;
localparam ROM_SIZE = 'hFFF;


localparam WRSR  = 8'b0000_0001;
localparam WRITE = 8'b0000_0010;
localparam READ  = 8'b0000_0011;
localparam WRDI  = 8'b0000_0100;
localparam RDSR  = 8'b0000_0101;
localparam WREN  = 8'b0000_0110;

enum bit [2:0] {
	M95_IDLE,
	M95_WRSR,
	M95_WRITE,
	M95_READ,
	M95_RDSR,
	M95_WAIT
} state;

int bit_count;

logic [15:0] address;
logic [7:0] data_in, data_out;
logic [2:0] byte_ptr;
logic old_sck;
logic bit_out;
logic ram_write;


logic [7:0] status;
logic WEL;
logic WIP;
logic SRWD, BP1, BP0;

always_ff @(posedge clk) begin
	if (~enable || (~hold_n && cs_n)) begin
		state <= M95_IDLE;
		data_in <= 8'b0;
		WIP <= 1'b0;
		WEL <= 1'b0;
		SRWD <= 1'b0;
		BP1 <= 1'b0;
		BP0 <= 1'b0;
	end else begin

	old_sck <= sck;
	if (~old_sck & sck & hold_n & ~cs_n) begin
		case (state)
			M95_IDLE: begin
				bit_count <= bit_count + 1'b1;
				data_in <= {data_in[6:0], si};
				ram_write <= 1'b0;
				if (bit_count == 3'h7) begin
					bit_count <= 0;
					data_in <= 8'h0;
					byte_ptr <= 3'h7;
					case ({data_in[6:0], si})
						WRSR: begin
							if (WEL) begin
								state <= M95_WRSR;
							end
							WEL <= 1'b0;
						end

						WRITE: begin
							if (WEL) begin
								state <= M95_WRITE;
							end
							WEL <= 1'b0;
						end

						READ: begin
							state <= M95_READ;
						end

						WRDI: begin
							WEL <= 1'b0;
						end

						RDSR: begin
							state <= M95_RDSR;
							status <= {SRWD, 3'b000, BP1, BP0, WEL, WIP};
						end

						WREN: begin
							WEL <= 1'b1;
						end

						default: begin
							state <= M95_WAIT;
						end
					endcase
				end
			end

			M95_WRSR: begin
				status[byte_ptr] <= si;
				byte_ptr <= byte_ptr - 1'b1;
				WEL <= status[1];



			end

			M95_RDSR: begin
				byte_ptr <= byte_ptr - 1'b1;
				bit_out <= status[byte_ptr];
			end

			M95_READ: begin
				if (bit_count <= ADDRESS_LEN) begin
					address <= {address[14:0], si};
					bit_count <= bit_count + 1'b1;
				end else begin
					byte_ptr <= byte_ptr - 1'b1;
					bit_out <= ram_q[byte_ptr];
					if (byte_ptr == 0)
						address <= (address == ROM_SIZE) ? 16'h0 : address + 1'b1;
				end
			end

			M95_WRITE: begin
				if (bit_count <= ADDRESS_LEN) begin
					address <= {address[14:0], si};
					bit_count <= bit_count + 1'b1;
				end else begin
					byte_ptr <= byte_ptr - 1'b1;
					data_out[byte_ptr] <= si;
					ram_write <= (byte_ptr == 0);
					if (ram_write)
						address <= (address == ROM_SIZE) ? 16'h0 : address + 1'b1;
				end
			end

			default:;
		endcase

	end
	if (cs_n) begin
		state <= M95_IDLE;
		bit_count <= 0;
		bit_out <= 1'b1;
	end
	end
end
endmodule