data/full_repos/permissive/156417892/hdl/Execute/AdderBranch/AdderBranch_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/AdderBranch/AdderBranch_test.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/AdderBranch/AdderBranch_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/AdderBranch/AdderBranch_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Error: data/full_repos/permissive/156417892/hdl/Execute/AdderBranch/AdderBranch_test.v:31: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("./AdderBranch.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/156417892/hdl/Execute/AdderBranch/AdderBranch_test.v:32: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_test;


   reg [31:0] pc, imm32;   

   wire [31:0] pcAddResult;
   
   integer  i;

   AdderBranch uut (pc,
                    imm32,
                    pcAddResult);
           
   initial begin

      #50;
      pc = 10;
      imm32 = 10;
      
      
      #50;
      pc = 10;
      imm32 = 20;
      #50;
      
   end

   initial begin
      $dumpfile("./AdderBranch.vcd");
      $dumpvars;
   end

endmodule
module main_test;



   reg [31:0] pc, imm32;   

   wire [31:0] pcAddResult;
   
   integer  i;

   AdderBranch uut (pc,
                    imm32,
                    pcAddResult);
           
   initial begin

      #50;
      pc = 10;
      imm32 = 10;
      
      
      #50;
      pc = 10;
      imm32 = 20;
      #50;
      
   end

   initial begin
      $dumpfile("./AdderBranch.vcd");
      $dumpvars;
   end

endmodule