data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_サンプル回路/FPGA-CPU/FPGA_counter/dynamic_display.v
data/verilator_xmls/5767c452-141b-41c3-8293-86a2defbf7ae.xml
module dynamic_display(

		CLK,
		RSTN,
		RSW,
		SEG_A_0,
		SEG_B_0,
		SEG_C_0,
		SEG_D_0,


		SEG_A,




		SEG_SEL
);


input  	CLK;
input  	RSTN;
input  	[3:0] RSW;
input  	[7:0] SEG_A_0,SEG_B_0,SEG_C_0,SEG_D_0;




output [7:0] SEG_A;
output [3:0] SEG_SEL;


reg    [7:0] SEG_A,SEG_B,SEG_C,SEG_D;



reg [23:0] DEF_COUNT;
reg [23:0] SEC_COUNT;
reg [3:0]  GATE;
reg SEC_SIG;

wire [3:0] SEG_SEL;

	always@( posedge CLK or negedge RSTN ) begin
	  	if( !RSTN )begin
	    	DEF_COUNT <= 24'd10000000;
		end
		else begin
	    	case( RSW )
	      		4'd0: DEF_COUNT <= 24'd1000000;
	      		4'd1: DEF_COUNT <= 24'd100000;
	      		4'd2: DEF_COUNT <= 24'd10000;
	      		4'd3: DEF_COUNT <= 24'd1000;
	      		4'd4: DEF_COUNT <= 24'd100;
	      		4'd5: DEF_COUNT <= 24'd10;
                    default: DEF_COUNT <= 24'd10000000;
			endcase
		end
	end


	always@( posedge CLK or negedge RSTN) begin
  		if( !RSTN )begin
    		SEC_COUNT <= 24'd0;
		end
		else if( SEC_COUNT >= DEF_COUNT - 24'd1)begin
			SEC_COUNT <= 24'd0;
		end
  		else begin
    		SEC_COUNT <= SEC_COUNT + 24'd1;
		end
	end

	always@( posedge CLK or negedge RSTN) begin
		if( !RSTN )begin
    		SEC_SIG <= 1'b0;
		end
  		else if( SEC_COUNT >= DEF_COUNT - 24'd1 )begin
    		SEC_SIG <= 1'b1;
		end
  		else begin
   	 		SEC_SIG <= 1'b0;
		end
	end

	always@( posedge CLK or negedge RSTN) begin
		if( !RSTN )begin
    		GATE <= 4'b0001;
		end
  		else if( SEC_SIG == 1'b1 )begin
    		GATE[0] <= GATE[3];
    		GATE[1] <= GATE[0];
    		GATE[2] <= GATE[1];
    		GATE[3] <= GATE[2];
		end
  		else begin
   	 		GATE <= GATE;
		end
	end


	always@( posedge CLK or negedge RSTN ) begin
	  	if( !RSTN )begin
	    	SEG_A <= 8'd0;
		end
		else begin
	    	case( GATE )
	      		4'd1: begin
  	    			SEG_A <= SEG_A_0;
			      end
	      		4'd2: begin
  	    			SEG_A <= SEG_B_0;
			      end
	      		4'd4: begin
  	    			SEG_A <= SEG_C_0;
			      end
	      		4'd8: begin
  	    			SEG_A <= SEG_D_0;
			      end
                    default: begin
			    	SEG_A <= 8'd0;
			      end

			endcase
		end
	end

assign  SEG_SEL = ~GATE;

endmodule
module dynamic_display(

		CLK,
		RSTN,
		RSW,
		SEG_A_0,
		SEG_B_0,
		SEG_C_0,
		SEG_D_0,


		SEG_A,




		SEG_SEL
);



input  	CLK;
input  	RSTN;
input  	[3:0] RSW;
input  	[7:0] SEG_A_0,SEG_B_0,SEG_C_0,SEG_D_0;




output [7:0] SEG_A;
output [3:0] SEG_SEL;


reg    [7:0] SEG_A,SEG_B,SEG_C,SEG_D;



reg [23:0] DEF_COUNT;
reg [23:0] SEC_COUNT;
reg [3:0]  GATE;
reg SEC_SIG;

wire [3:0] SEG_SEL;

	always@( posedge CLK or negedge RSTN ) begin
	  	if( !RSTN )begin
	    	DEF_COUNT <= 24'd10000000;
		end
		else begin
	    	case( RSW )
	      		4'd0: DEF_COUNT <= 24'd1000000;
	      		4'd1: DEF_COUNT <= 24'd100000;
	      		4'd2: DEF_COUNT <= 24'd10000;
	      		4'd3: DEF_COUNT <= 24'd1000;
	      		4'd4: DEF_COUNT <= 24'd100;
	      		4'd5: DEF_COUNT <= 24'd10;
                    default: DEF_COUNT <= 24'd10000000;
			endcase
		end
	end


	always@( posedge CLK or negedge RSTN) begin
  		if( !RSTN )begin
    		SEC_COUNT <= 24'd0;
		end
		else if( SEC_COUNT >= DEF_COUNT - 24'd1)begin
			SEC_COUNT <= 24'd0;
		end
  		else begin
    		SEC_COUNT <= SEC_COUNT + 24'd1;
		end
	end

	always@( posedge CLK or negedge RSTN) begin
		if( !RSTN )begin
    		SEC_SIG <= 1'b0;
		end
  		else if( SEC_COUNT >= DEF_COUNT - 24'd1 )begin
    		SEC_SIG <= 1'b1;
		end
  		else begin
   	 		SEC_SIG <= 1'b0;
		end
	end

	always@( posedge CLK or negedge RSTN) begin
		if( !RSTN )begin
    		GATE <= 4'b0001;
		end
  		else if( SEC_SIG == 1'b1 )begin
    		GATE[0] <= GATE[3];
    		GATE[1] <= GATE[0];
    		GATE[2] <= GATE[1];
    		GATE[3] <= GATE[2];
		end
  		else begin
   	 		GATE <= GATE;
		end
	end


	always@( posedge CLK or negedge RSTN ) begin
	  	if( !RSTN )begin
	    	SEG_A <= 8'd0;
		end
		else begin
	    	case( GATE )
	      		4'd1: begin
  	    			SEG_A <= SEG_A_0;
			      end
	      		4'd2: begin
  	    			SEG_A <= SEG_B_0;
			      end
	      		4'd4: begin
  	    			SEG_A <= SEG_C_0;
			      end
	      		4'd8: begin
  	    			SEG_A <= SEG_D_0;
			      end
                    default: begin
			    	SEG_A <= 8'd0;
			      end

			endcase
		end
	end

assign  SEG_SEL = ~GATE;

endmodule