data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v
'utf-8' codec can't decode bytes in position 322-323: invalid continuation byte
1: b"%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:74: Cannot find file containing module: 'PC'\n PC U_PC (\n ^~\n        ... Looked in:\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/PC\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/PC.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/PC.sv\n             PC\n             PC.v\n             PC.sv\n             obj_dir/PC\n             obj_dir/PC.v\n             obj_dir/PC.sv\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:80: Cannot find file containing module: 'NPC'\n NPC U_NPC (\n ^~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:86: Cannot find file containing module: 'im_4k'\n im_4k U_IM ( \n ^~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:91: Cannot find file containing module: 'Reg_IF_ID'\n Reg_IF_ID U_Reg_IF_ID (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:103: Cannot find file containing module: 'ctrl'\n ctrl ID_ctrl(\n ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:113: Cannot find file containing module: 'HazardDetector'\n HazardDetector U_HazardDetector (\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:121: Cannot find file containing module: 'RF'\n  RF U_RF (\n  ^~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:129: Cannot find file containing module: 'EXT'\n EXT U_EXT ( \n ^~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:135: Cannot find file containing module: 'brancher'\n brancher U_brancher (\n ^~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:145: Cannot find file containing module: 'Reg_ID_EX'\n Reg_ID_EX U_Reg_ID_EX(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:159: Cannot find file containing module: 'ctrl'\n ctrl EX_ctrl (\n ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:165: Cannot find file containing module: 'byPasser'\n byPasser U_byPasser (\n ^~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:174: Cannot find file containing module: 'mux4'\n mux4 #(.WIDTH(32)) A_Reg_Mux (\n ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:180: Cannot find file containing module: 'mux4'\n mux4 #(.WIDTH(32)) A_Mux (\n ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:185: Cannot find file containing module: 'mux4'\n mux4 #(.WIDTH(32)) B_Reg_Mux (\n ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:190: Cannot find file containing module: 'mux2'\n mux2 #(.WIDTH(32)) B_Mux (\n ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:195: Cannot find file containing module: 'alu'\n alu U_ALU ( \n ^~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:200: Cannot find file containing module: 'mux2'\n mux2 #(.WIDTH(5)) RegDst_Mux (\n ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:206: Cannot find file containing module: 'Reg_EX_MEM'\n Reg_EX_MEM U_Reg_EX_MEM (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:220: Cannot find file containing module: 'ctrl'\n ctrl MEM_ctrl (\n ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:228: Cannot find file containing module: 'dm_4k'\n dm_4k U_DM ( \n ^~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:235: Cannot find file containing module: 'Reg_MEM_WB'\n Reg_MEM_WB U_Reg_MEM_WB (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:249: Cannot find file containing module: 'ctrl'\n ctrl WB_ctrl (\n ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:254: Cannot find file containing module: 'mux2'\n mux2 #(.WIDTH(5)) WriteDstReg (\n ^~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips.v:259: Cannot find file containing module: 'mux4'\n mux4 #(.WIDTH(32)) WriteContent_MUX (\n ^~~~\n%Error: Exiting due to 25 error(s)\n"
module mips( clk, rst );

	input   clk;
	input   rst;
   

	wire	[29:0]	PC;
	wire	[29:0]	NPC;
	wire	[29:0]	IF_ID_PC_r;
	wire	[29:0]	ID_EX_PC_r;
	wire	[29:0]	EX_MEM_PC_r;
	wire	[29:0]	MEM_WB_PC_r;
	wire	[31:0]	im_dout;
	wire	[31:0]	dm_dout;
	wire	[31:0]	DataMem_r;
	wire	[31:0]	ID_instr;
	wire	[31:0]	EX_instr;
	wire	[31:0]	MEM_instr;
	wire	[31:0]	WB_instr;
	wire	[4:0]	WriteReg;
	wire	[31:0]	WriteData;
	wire	[31:0]	RD1;
	wire	[31:0]	RD1_r;
	wire	[31:0]	RD2;
	wire	[31:0]	RD2_r;
	wire	[31:0]	Imm32;
	wire	[31:0]	ImmExt_r;
	wire	[31:0]	ALUOut_C;
	wire	[31:0]	ALUOut_C_r;
	wire	[31:0]	ALUOut_C_MEM_WB_r;
	wire	[31:0]	A_Reg;
	wire	[31:0]	B_Reg;
	wire	[31:0]	B_Reg_r;
	wire	[31:0]	ALUSource_A;
	wire	[31:0]	ALUSource_B;
	wire	[31:0]	ALUSource_B_r;
	wire	[4:0]	WriteDst_EX;
	wire	[4:0]	WriteDst_MEM;
	wire	[4:0]	WriteDst_WB;
		


	wire			jmpSignal;
	wire			brSignal;
	wire			brSignal_r;
	wire			jmpRSignal;
	wire			stallSignal;
	
	wire	[1:0]	EXTOp;
	wire			control_EX_MemRead;

	wire	[1:0]	ASel;
	wire			BSel;
	wire	[4:0]	ALUOp;
	wire			WriteDstSel;
	wire	[1:0]	byPasserSelA;
	wire	[1:0]	byPasserSelB;
	wire			EX_ctrl_RegWr;

	
	wire			MEM_ctrl_RegWr;
	wire	[1:0]	be;
	wire			DMWr;

	wire	[1:0]	WriteContentSel;
	wire			WB_ctrl_RegWr;
	wire			WriteDstRegSel;

   




	PC U_PC (
      .clk(clk), .rst(rst), .NPC(NPC), 
	    .PC(PC)
	); 


	NPC U_NPC (
		.PC(PC), .Imm(ID_instr[25:0]), .jmpReg(RD1), 
		.jmpSignal(jmpSignal), .brSignal(brSignal), .jmpRSignal(jmpRSignal), .stallSignal(stallSignal), 		.NPC(NPC)
	);
   

	im_4k U_IM ( 
      .addr(PC[9:0]) , .dout(im_dout)
	);
   

	Reg_IF_ID U_Reg_IF_ID (
		.stallSignal(stallSignal), .jmpSignal(jmpSignal), .jmpRSignal(jmpRSignal),
		.clk(clk), .rst(rst), 
		.PC(PC), .IF_ID_PC_r(IF_ID_PC_r),
		.instr(im_dout), .instr_IF_ID_r(ID_instr)
	);
   





	ctrl ID_ctrl(
		.clk(clk), .rst(rst), .instr(ID_instr), .step(2'b00),
		.EXTOp(EXTOp), .jmpSignal(jmpSignal), .jmpRSignal(jmpRSignal)
	);






	HazardDetector U_HazardDetector (
	   .rs_ID(ID_instr[25:21]), .rt_ID(ID_instr[20:16]), 
	   .MemRead_EX(control_EX_MemRead), .WriteDst_EX(WriteDst_EX), 
	   .brSignal(brSignal), .EX_ctrl_regWr(EX_ctrl_RegWr),
	   .stallSignal(stallSignal)
	);
      

		RF U_RF (
		.clk(clk), .RFWr(WB_ctrl_RegWr),
		.A1(ID_instr[25:21]), .A2(ID_instr[20:16]), .A3(WriteReg), .WD(WriteData), 
		.RD1(RD1), .RD2(RD2)
	);
   


	EXT U_EXT ( 
      .Imm16(ID_instr[15:0]), .EXTOp(EXTOp), 
	   .Imm32(Imm32) 
	);
	

	brancher U_brancher (
		.clk(clk), .rst(rst),
		.Op(ID_instr[31:26]), .rs(ID_instr[25:21]), .rt(ID_instr[20:16]), .Imm(ID_instr[15:0]),
		.brSignal(brSignal),
		.WriteDst_EX(WriteDst_EX), .WriteDst_MEM(WriteDst_MEM),
		.RD1(RD1), .RD2(RD2), .ALUOut_C(ALUOut_C), .dm_dout(dm_dout),
		.EX_ctrl_RegWr(EX_ctrl_RegWr), .MEM_ctrl_RegWr(MEM_ctrl_RegWr)
		);


	Reg_ID_EX U_Reg_ID_EX(
		.clk(clk), .rst(rst), .stallSignal(stallSignal), 
		.ID_instr_r(ID_instr), .ID_EX_instr(EX_instr), 
		.RD1(RD1), .RD2(RD2), .ImmExt(Imm32),
		.RD1_ID_EX_r(RD1_r), .RD2_ID_EX_r(RD2_r), .ImmExt_r(ImmExt_r),
		.brSignal(brSignal), .brSignal_r(brSignal_r),
		.IF_ID_PC_r(IF_ID_PC_r), .ID_EX_PC_r(ID_EX_PC_r)
		);






	ctrl EX_ctrl (
		.clk(clk), .rst(rst), .instr(EX_instr), .step(2'b01),
		.control_EX_MemRead(control_EX_MemRead), .ASel(ASel), .BSel(BSel), .ALUOp(ALUOp), .WriteDstSel(WriteDstSel), .EX_ctrl_regWr(EX_ctrl_RegWr)
		);


	byPasser U_byPasser (
		.clk(clk), .rst(rst),
		.WriteDst_MEM(WriteDst_MEM), .WriteDst_WB(WriteReg),
		.rs_EX(EX_instr[25:21]), .rt_EX(EX_instr[20:16]),
		.MEM_ctrl_RegWr(MEM_ctrl_RegWr), .WB_ctrl_RegWr(WB_ctrl_RegWr),
		.byPasserSelA(byPasserSelA), .byPasserSelB(byPasserSelB)
	);


	mux4 #(.WIDTH(32)) A_Reg_Mux (
		.d0(RD1_r), .d1(WriteData), .d2(ALUOut_C_r), .d3(0), .s(byPasserSelA), .y(A_Reg)
	);



	mux4 #(.WIDTH(32)) A_Mux (
		.d0(A_Reg), .d1(5'b10000), .d2({27'b0, EX_instr[10:6]}), .d3(0), .s(ASel), .y(ALUSource_A)
	);
   

	mux4 #(.WIDTH(32)) B_Reg_Mux (
		.d0(RD2_r), .d1(WriteData), .d2(ALUOut_C_r), .d3(0), .s(byPasserSelB), .y(B_Reg)
	);


	mux2 #(.WIDTH(32)) B_Mux (
		.d0(B_Reg), .d1(ImmExt_r), .s(BSel), .y(ALUSource_B)
	);
   

	alu U_ALU ( 
		.A(ALUSource_A), .B(ALUSource_B), .ALUOp(ALUOp), .C(ALUOut_C)
	);
   

	mux2 #(.WIDTH(5)) RegDst_Mux (
		.d0(EX_instr[20:16]), .d1(EX_instr[15:11]), .s(WriteDstSel), .y(WriteDst_EX)
	);



	Reg_EX_MEM U_Reg_EX_MEM (
	   .clk(clk), .rst(rst), 
	   .EX_instr(EX_instr), .EX_MEM_instr(MEM_instr),
	   .ALUOut(ALUOut_C), .ALUSource_B(ALUSource_B), .WriteDst(WriteDst_EX),
	   .ALUOut_EX_MEM_r(ALUOut_C_r), .ALUSource_B_EX_MEM_r(ALUSource_B_r), .WriteDst_EX_MEM_r(WriteDst_MEM),
	   .B_Reg(B_Reg), .B_Reg_r(B_Reg_r),
	   .ID_EX_PC_r(ID_EX_PC_r), .EX_MEM_PC_r(EX_MEM_PC_r)
   );






	ctrl MEM_ctrl (
		.clk(clk), .rst(rst), .instr(MEM_instr), .step(2'b10),
		.MEM_ctrl_regWr(MEM_ctrl_RegWr), .be(be), .DMWr(DMWr)
	);




	dm_4k U_DM ( 
		.addr(ALUOut_C_r[11:2]), .din(B_Reg_r), 
		.be(4'b1111), .DMWr(DMWr), 
		.clk(clk), .dout(dm_dout)
	);
   

	Reg_MEM_WB U_Reg_MEM_WB (
		.clk(clk), .rst(rst), 
		.MEM_instr(MEM_instr), .MEM_WB_instr(WB_instr),
		.DataMem(dm_dout), .DataMem_MEM_WB_r(DataMem_r),
		.ALUOut(ALUOut_C_r), .ALUOut_MEM_WB_r(ALUOut_C_MEM_WB_r),
		.WriteDst(WriteDst_MEM), .WriteDst_MEM_WB_r(WriteDst_WB),
		.EX_MEM_PC_r(EX_MEM_PC_r), .MEM_WB_PC_r(MEM_WB_PC_r)
	);






	ctrl WB_ctrl (
		.clk(clk), .rst(rst), .instr(WB_instr), .step(2'b11),
		.WB_ctrl_regWr(WB_ctrl_RegWr), .WriteContentSel(WriteContentSel), .WriteDstRegSel(WriteDstRegSel)
	);
	
	mux2 #(.WIDTH(5)) WriteDstReg (
		.d0(WriteDst_WB), .d1(5'd31), .s(WriteDstRegSel), .y(WriteReg)
	);
	

	mux4 #(.WIDTH(32)) WriteContent_MUX (
		.d0(ALUOut_C_MEM_WB_r), .d1(DataMem_r), .d2({MEM_WB_PC_r+1, 2'b00}), .d3(0), 
		.s(WriteContentSel), .y(WriteData)
	);
endmodule
module mips( clk, rst );


	input   clk;
	input   rst;
   

	wire	[29:0]	PC;
	wire	[29:0]	NPC;
	wire	[29:0]	IF_ID_PC_r;
	wire	[29:0]	ID_EX_PC_r;
	wire	[29:0]	EX_MEM_PC_r;
	wire	[29:0]	MEM_WB_PC_r;
	wire	[31:0]	im_dout;
	wire	[31:0]	dm_dout;
	wire	[31:0]	DataMem_r;
	wire	[31:0]	ID_instr;
	wire	[31:0]	EX_instr;
	wire	[31:0]	MEM_instr;
	wire	[31:0]	WB_instr;
	wire	[4:0]	WriteReg;
	wire	[31:0]	WriteData;
	wire	[31:0]	RD1;
	wire	[31:0]	RD1_r;
	wire	[31:0]	RD2;
	wire	[31:0]	RD2_r;
	wire	[31:0]	Imm32;
	wire	[31:0]	ImmExt_r;
	wire	[31:0]	ALUOut_C;
	wire	[31:0]	ALUOut_C_r;
	wire	[31:0]	ALUOut_C_MEM_WB_r;
	wire	[31:0]	A_Reg;
	wire	[31:0]	B_Reg;
	wire	[31:0]	B_Reg_r;
	wire	[31:0]	ALUSource_A;
	wire	[31:0]	ALUSource_B;
	wire	[31:0]	ALUSource_B_r;
	wire	[4:0]	WriteDst_EX;
	wire	[4:0]	WriteDst_MEM;
	wire	[4:0]	WriteDst_WB;
		


	wire			jmpSignal;
	wire			brSignal;
	wire			brSignal_r;
	wire			jmpRSignal;
	wire			stallSignal;
	
	wire	[1:0]	EXTOp;
	wire			control_EX_MemRead;

	wire	[1:0]	ASel;
	wire			BSel;
	wire	[4:0]	ALUOp;
	wire			WriteDstSel;
	wire	[1:0]	byPasserSelA;
	wire	[1:0]	byPasserSelB;
	wire			EX_ctrl_RegWr;

	
	wire			MEM_ctrl_RegWr;
	wire	[1:0]	be;
	wire			DMWr;

	wire	[1:0]	WriteContentSel;
	wire			WB_ctrl_RegWr;
	wire			WriteDstRegSel;

   




	PC U_PC (
      .clk(clk), .rst(rst), .NPC(NPC), 
	    .PC(PC)
	); 


	NPC U_NPC (
		.PC(PC), .Imm(ID_instr[25:0]), .jmpReg(RD1), 
		.jmpSignal(jmpSignal), .brSignal(brSignal), .jmpRSignal(jmpRSignal), .stallSignal(stallSignal), 		.NPC(NPC)
	);
   

	im_4k U_IM ( 
      .addr(PC[9:0]) , .dout(im_dout)
	);
   

	Reg_IF_ID U_Reg_IF_ID (
		.stallSignal(stallSignal), .jmpSignal(jmpSignal), .jmpRSignal(jmpRSignal),
		.clk(clk), .rst(rst), 
		.PC(PC), .IF_ID_PC_r(IF_ID_PC_r),
		.instr(im_dout), .instr_IF_ID_r(ID_instr)
	);
   





	ctrl ID_ctrl(
		.clk(clk), .rst(rst), .instr(ID_instr), .step(2'b00),
		.EXTOp(EXTOp), .jmpSignal(jmpSignal), .jmpRSignal(jmpRSignal)
	);






	HazardDetector U_HazardDetector (
	   .rs_ID(ID_instr[25:21]), .rt_ID(ID_instr[20:16]), 
	   .MemRead_EX(control_EX_MemRead), .WriteDst_EX(WriteDst_EX), 
	   .brSignal(brSignal), .EX_ctrl_regWr(EX_ctrl_RegWr),
	   .stallSignal(stallSignal)
	);
      

		RF U_RF (
		.clk(clk), .RFWr(WB_ctrl_RegWr),
		.A1(ID_instr[25:21]), .A2(ID_instr[20:16]), .A3(WriteReg), .WD(WriteData), 
		.RD1(RD1), .RD2(RD2)
	);
   


	EXT U_EXT ( 
      .Imm16(ID_instr[15:0]), .EXTOp(EXTOp), 
	   .Imm32(Imm32) 
	);
	

	brancher U_brancher (
		.clk(clk), .rst(rst),
		.Op(ID_instr[31:26]), .rs(ID_instr[25:21]), .rt(ID_instr[20:16]), .Imm(ID_instr[15:0]),
		.brSignal(brSignal),
		.WriteDst_EX(WriteDst_EX), .WriteDst_MEM(WriteDst_MEM),
		.RD1(RD1), .RD2(RD2), .ALUOut_C(ALUOut_C), .dm_dout(dm_dout),
		.EX_ctrl_RegWr(EX_ctrl_RegWr), .MEM_ctrl_RegWr(MEM_ctrl_RegWr)
		);


	Reg_ID_EX U_Reg_ID_EX(
		.clk(clk), .rst(rst), .stallSignal(stallSignal), 
		.ID_instr_r(ID_instr), .ID_EX_instr(EX_instr), 
		.RD1(RD1), .RD2(RD2), .ImmExt(Imm32),
		.RD1_ID_EX_r(RD1_r), .RD2_ID_EX_r(RD2_r), .ImmExt_r(ImmExt_r),
		.brSignal(brSignal), .brSignal_r(brSignal_r),
		.IF_ID_PC_r(IF_ID_PC_r), .ID_EX_PC_r(ID_EX_PC_r)
		);






	ctrl EX_ctrl (
		.clk(clk), .rst(rst), .instr(EX_instr), .step(2'b01),
		.control_EX_MemRead(control_EX_MemRead), .ASel(ASel), .BSel(BSel), .ALUOp(ALUOp), .WriteDstSel(WriteDstSel), .EX_ctrl_regWr(EX_ctrl_RegWr)
		);


	byPasser U_byPasser (
		.clk(clk), .rst(rst),
		.WriteDst_MEM(WriteDst_MEM), .WriteDst_WB(WriteReg),
		.rs_EX(EX_instr[25:21]), .rt_EX(EX_instr[20:16]),
		.MEM_ctrl_RegWr(MEM_ctrl_RegWr), .WB_ctrl_RegWr(WB_ctrl_RegWr),
		.byPasserSelA(byPasserSelA), .byPasserSelB(byPasserSelB)
	);


	mux4 #(.WIDTH(32)) A_Reg_Mux (
		.d0(RD1_r), .d1(WriteData), .d2(ALUOut_C_r), .d3(0), .s(byPasserSelA), .y(A_Reg)
	);



	mux4 #(.WIDTH(32)) A_Mux (
		.d0(A_Reg), .d1(5'b10000), .d2({27'b0, EX_instr[10:6]}), .d3(0), .s(ASel), .y(ALUSource_A)
	);
   

	mux4 #(.WIDTH(32)) B_Reg_Mux (
		.d0(RD2_r), .d1(WriteData), .d2(ALUOut_C_r), .d3(0), .s(byPasserSelB), .y(B_Reg)
	);


	mux2 #(.WIDTH(32)) B_Mux (
		.d0(B_Reg), .d1(ImmExt_r), .s(BSel), .y(ALUSource_B)
	);
   

	alu U_ALU ( 
		.A(ALUSource_A), .B(ALUSource_B), .ALUOp(ALUOp), .C(ALUOut_C)
	);
   

	mux2 #(.WIDTH(5)) RegDst_Mux (
		.d0(EX_instr[20:16]), .d1(EX_instr[15:11]), .s(WriteDstSel), .y(WriteDst_EX)
	);



	Reg_EX_MEM U_Reg_EX_MEM (
	   .clk(clk), .rst(rst), 
	   .EX_instr(EX_instr), .EX_MEM_instr(MEM_instr),
	   .ALUOut(ALUOut_C), .ALUSource_B(ALUSource_B), .WriteDst(WriteDst_EX),
	   .ALUOut_EX_MEM_r(ALUOut_C_r), .ALUSource_B_EX_MEM_r(ALUSource_B_r), .WriteDst_EX_MEM_r(WriteDst_MEM),
	   .B_Reg(B_Reg), .B_Reg_r(B_Reg_r),
	   .ID_EX_PC_r(ID_EX_PC_r), .EX_MEM_PC_r(EX_MEM_PC_r)
   );






	ctrl MEM_ctrl (
		.clk(clk), .rst(rst), .instr(MEM_instr), .step(2'b10),
		.MEM_ctrl_regWr(MEM_ctrl_RegWr), .be(be), .DMWr(DMWr)
	);




	dm_4k U_DM ( 
		.addr(ALUOut_C_r[11:2]), .din(B_Reg_r), 
		.be(4'b1111), .DMWr(DMWr), 
		.clk(clk), .dout(dm_dout)
	);
   

	Reg_MEM_WB U_Reg_MEM_WB (
		.clk(clk), .rst(rst), 
		.MEM_instr(MEM_instr), .MEM_WB_instr(WB_instr),
		.DataMem(dm_dout), .DataMem_MEM_WB_r(DataMem_r),
		.ALUOut(ALUOut_C_r), .ALUOut_MEM_WB_r(ALUOut_C_MEM_WB_r),
		.WriteDst(WriteDst_MEM), .WriteDst_MEM_WB_r(WriteDst_WB),
		.EX_MEM_PC_r(EX_MEM_PC_r), .MEM_WB_PC_r(MEM_WB_PC_r)
	);






	ctrl WB_ctrl (
		.clk(clk), .rst(rst), .instr(WB_instr), .step(2'b11),
		.WB_ctrl_regWr(WB_ctrl_RegWr), .WriteContentSel(WriteContentSel), .WriteDstRegSel(WriteDstRegSel)
	);
	
	mux2 #(.WIDTH(5)) WriteDstReg (
		.d0(WriteDst_WB), .d1(5'd31), .s(WriteDstRegSel), .y(WriteReg)
	);
	

	mux4 #(.WIDTH(32)) WriteContent_MUX (
		.d0(ALUOut_C_MEM_WB_r), .d1(DataMem_r), .d2({MEM_WB_PC_r+1, 2'b00}), .d3(0), 
		.s(WriteContentSel), .y(WriteData)
	);
endmodule