data/full_repos/permissive/205682213/src_v/audio.v
None: at end of input
1: b'%Error: data/full_repos/permissive/205682213/src_v/audio.v:35: Cannot find include file: audio_defs.v\n`include "audio_defs.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205682213/src_v,data/full_repos/permissive/205682213/audio_defs.v\n             data/full_repos/permissive/205682213/src_v,data/full_repos/permissive/205682213/audio_defs.v.v\n             data/full_repos/permissive/205682213/src_v,data/full_repos/permissive/205682213/audio_defs.v.sv\n             audio_defs.v\n             audio_defs.v.v\n             audio_defs.v.sv\n             obj_dir/audio_defs.v\n             obj_dir/audio_defs.v.v\n             obj_dir/audio_defs.v.sv\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:106: Define or directive not defined: \'`AUDIO_CFG\'\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:106: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                                       ^\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:116: Number is missing value digits: 16\'d\n    audio_cfg_int_threshold_q <= 16\'d`AUDIO_CFG_INT_THRESHOLD_DEFAULT;\n                                 ^~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:116: Define or directive not defined: \'`AUDIO_CFG_INT_THRESHOLD_DEFAULT\'\n    audio_cfg_int_threshold_q <= 16\'d`AUDIO_CFG_INT_THRESHOLD_DEFAULT;\n                                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:117: Define or directive not defined: \'`AUDIO_CFG\'\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:117: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                                       ^\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:118: Define or directive not defined: \'`AUDIO_CFG_INT_THRESHOLD_R\'\n    audio_cfg_int_threshold_q <= cfg_wdata_i[`AUDIO_CFG_INT_THRESHOLD_R];\n                                             ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:128: Number is missing value digits: 1\'d\n    audio_cfg_byte_swap_q <= 1\'d`AUDIO_CFG_BYTE_SWAP_DEFAULT;\n                             ^~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:128: Define or directive not defined: \'`AUDIO_CFG_BYTE_SWAP_DEFAULT\'\n    audio_cfg_byte_swap_q <= 1\'d`AUDIO_CFG_BYTE_SWAP_DEFAULT;\n                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:129: Define or directive not defined: \'`AUDIO_CFG\'\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:129: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                                       ^\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:130: Define or directive not defined: \'`AUDIO_CFG_BYTE_SWAP_R\'\n    audio_cfg_byte_swap_q <= cfg_wdata_i[`AUDIO_CFG_BYTE_SWAP_R];\n                                         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:140: Number is missing value digits: 1\'d\n    audio_cfg_ch_swap_q <= 1\'d`AUDIO_CFG_CH_SWAP_DEFAULT;\n                           ^~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:140: Define or directive not defined: \'`AUDIO_CFG_CH_SWAP_DEFAULT\'\n    audio_cfg_ch_swap_q <= 1\'d`AUDIO_CFG_CH_SWAP_DEFAULT;\n                              ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:141: Define or directive not defined: \'`AUDIO_CFG\'\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:141: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                                       ^\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:142: Define or directive not defined: \'`AUDIO_CFG_CH_SWAP_R\'\n    audio_cfg_ch_swap_q <= cfg_wdata_i[`AUDIO_CFG_CH_SWAP_R];\n                                       ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:152: Number is missing value digits: 2\'d\n    audio_cfg_target_q <= 2\'d`AUDIO_CFG_TARGET_DEFAULT;\n                          ^~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:152: Define or directive not defined: \'`AUDIO_CFG_TARGET_DEFAULT\'\n    audio_cfg_target_q <= 2\'d`AUDIO_CFG_TARGET_DEFAULT;\n                             ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:153: Define or directive not defined: \'`AUDIO_CFG\'\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:153: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                                       ^\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:154: Define or directive not defined: \'`AUDIO_CFG_TARGET_R\'\n    audio_cfg_target_q <= cfg_wdata_i[`AUDIO_CFG_TARGET_R];\n                                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:164: Number is missing value digits: 3\'d\n    audio_cfg_vol_ctrl_q <= 3\'d`AUDIO_CFG_VOL_CTRL_DEFAULT;\n                            ^~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:164: Define or directive not defined: \'`AUDIO_CFG_VOL_CTRL_DEFAULT\'\n    audio_cfg_vol_ctrl_q <= 3\'d`AUDIO_CFG_VOL_CTRL_DEFAULT;\n                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:165: Define or directive not defined: \'`AUDIO_CFG\'\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:165: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                                       ^\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:166: Define or directive not defined: \'`AUDIO_CFG_VOL_CTRL_R\'\n    audio_cfg_vol_ctrl_q <= cfg_wdata_i[`AUDIO_CFG_VOL_CTRL_R];\n                                        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:176: Number is missing value digits: 1\'d\n    audio_cfg_buffer_rst_q <= 1\'d`AUDIO_CFG_BUFFER_RST_DEFAULT;\n                              ^~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:176: Define or directive not defined: \'`AUDIO_CFG_BUFFER_RST_DEFAULT\'\n    audio_cfg_buffer_rst_q <= 1\'d`AUDIO_CFG_BUFFER_RST_DEFAULT;\n                                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:177: Define or directive not defined: \'`AUDIO_CFG\'\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:177: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))\n                                                       ^\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:178: Define or directive not defined: \'`AUDIO_CFG_BUFFER_RST_R\'\n    audio_cfg_buffer_rst_q <= cfg_wdata_i[`AUDIO_CFG_BUFFER_RST_R];\n                                          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:180: Number is missing value digits: 1\'d\n    audio_cfg_buffer_rst_q <= 1\'d`AUDIO_CFG_BUFFER_RST_DEFAULT;\n                              ^~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:180: Define or directive not defined: \'`AUDIO_CFG_BUFFER_RST_DEFAULT\'\n    audio_cfg_buffer_rst_q <= 1\'d`AUDIO_CFG_BUFFER_RST_DEFAULT;\n                                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:193: Define or directive not defined: \'`AUDIO_STATUS\'\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_STATUS))\n                                             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:193: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_STATUS))\n                                                          ^\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:209: Define or directive not defined: \'`AUDIO_CLK_DIV\'\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_DIV))\n                                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:209: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_DIV))\n                                                           ^\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:219: Number is missing value digits: 16\'d\n    audio_clk_div_whole_cycles_q <= 16\'d`AUDIO_CLK_DIV_WHOLE_CYCLES_DEFAULT;\n                                    ^~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:219: Define or directive not defined: \'`AUDIO_CLK_DIV_WHOLE_CYCLES_DEFAULT\'\n    audio_clk_div_whole_cycles_q <= 16\'d`AUDIO_CLK_DIV_WHOLE_CYCLES_DEFAULT;\n                                        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:220: Define or directive not defined: \'`AUDIO_CLK_DIV\'\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_DIV))\n                                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:220: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_DIV))\n                                                           ^\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:221: Define or directive not defined: \'`AUDIO_CLK_DIV_WHOLE_CYCLES_R\'\n    audio_clk_div_whole_cycles_q <= cfg_wdata_i[`AUDIO_CLK_DIV_WHOLE_CYCLES_R];\n                                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:234: Define or directive not defined: \'`AUDIO_CLK_FRAC\'\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))\n                                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:234: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))\n                                                            ^\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:244: Number is missing value digits: 16\'d\n    audio_clk_frac_numerator_q <= 16\'d`AUDIO_CLK_FRAC_NUMERATOR_DEFAULT;\n                                  ^~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:244: Define or directive not defined: \'`AUDIO_CLK_FRAC_NUMERATOR_DEFAULT\'\n    audio_clk_frac_numerator_q <= 16\'d`AUDIO_CLK_FRAC_NUMERATOR_DEFAULT;\n                                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:245: Define or directive not defined: \'`AUDIO_CLK_FRAC\'\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))\n                                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205682213/src_v/audio.v:245: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))\n                                                            ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module audio
(

     input          clk_i
    ,input          rst_i
    ,input          cfg_awvalid_i
    ,input  [31:0]  cfg_awaddr_i
    ,input          cfg_wvalid_i
    ,input  [31:0]  cfg_wdata_i
    ,input  [3:0]   cfg_wstrb_i
    ,input          cfg_bready_i
    ,input          cfg_arvalid_i
    ,input  [31:0]  cfg_araddr_i
    ,input          cfg_rready_i


    ,output         cfg_awready_o
    ,output         cfg_wready_o
    ,output         cfg_bvalid_o
    ,output [1:0]   cfg_bresp_o
    ,output         cfg_arready_o
    ,output         cfg_rvalid_o
    ,output [31:0]  cfg_rdata_o
    ,output [1:0]   cfg_rresp_o
    ,output         audio_l_o
    ,output         audio_r_o
    ,output         spdif_o
    ,output         i2s_sck_o
    ,output         i2s_sdata_o
    ,output         i2s_ws_o
    ,output         intr_o
);




reg [31:0] wr_data_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    wr_data_q <= 32'b0;
else
    wr_data_q <= cfg_wdata_i;




wire read_en_w  = cfg_arvalid_i & cfg_arready_o;
wire write_en_w = cfg_awvalid_i & cfg_awready_o;




assign cfg_arready_o = ~cfg_rvalid_o;
assign cfg_awready_o = ~cfg_bvalid_o && ~cfg_arvalid_i; 
assign cfg_wready_o  = cfg_awready_o;





reg audio_cfg_wr_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_wr_q <= 1'b1;
else
    audio_cfg_wr_q <= 1'b0;


reg [15:0]  audio_cfg_int_threshold_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_int_threshold_q <= 16'd`AUDIO_CFG_INT_THRESHOLD_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_int_threshold_q <= cfg_wdata_i[`AUDIO_CFG_INT_THRESHOLD_R];

wire [15:0]  audio_cfg_int_threshold_out_w = audio_cfg_int_threshold_q;



reg        audio_cfg_byte_swap_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_byte_swap_q <= 1'd`AUDIO_CFG_BYTE_SWAP_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_byte_swap_q <= cfg_wdata_i[`AUDIO_CFG_BYTE_SWAP_R];

wire        audio_cfg_byte_swap_out_w = audio_cfg_byte_swap_q;



reg        audio_cfg_ch_swap_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_ch_swap_q <= 1'd`AUDIO_CFG_CH_SWAP_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_ch_swap_q <= cfg_wdata_i[`AUDIO_CFG_CH_SWAP_R];

wire        audio_cfg_ch_swap_out_w = audio_cfg_ch_swap_q;



reg [1:0]  audio_cfg_target_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_target_q <= 2'd`AUDIO_CFG_TARGET_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_target_q <= cfg_wdata_i[`AUDIO_CFG_TARGET_R];

wire [1:0]  audio_cfg_target_out_w = audio_cfg_target_q;



reg [2:0]  audio_cfg_vol_ctrl_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_vol_ctrl_q <= 3'd`AUDIO_CFG_VOL_CTRL_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_vol_ctrl_q <= cfg_wdata_i[`AUDIO_CFG_VOL_CTRL_R];

wire [2:0]  audio_cfg_vol_ctrl_out_w = audio_cfg_vol_ctrl_q;



reg        audio_cfg_buffer_rst_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_buffer_rst_q <= 1'd`AUDIO_CFG_BUFFER_RST_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_buffer_rst_q <= cfg_wdata_i[`AUDIO_CFG_BUFFER_RST_R];
else
    audio_cfg_buffer_rst_q <= 1'd`AUDIO_CFG_BUFFER_RST_DEFAULT;

wire        audio_cfg_buffer_rst_out_w = audio_cfg_buffer_rst_q;





reg audio_status_wr_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_status_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_STATUS))
    audio_status_wr_q <= 1'b1;
else
    audio_status_wr_q <= 1'b0;







reg audio_clk_div_wr_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_clk_div_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_DIV))
    audio_clk_div_wr_q <= 1'b1;
else
    audio_clk_div_wr_q <= 1'b0;


reg [15:0]  audio_clk_div_whole_cycles_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_clk_div_whole_cycles_q <= 16'd`AUDIO_CLK_DIV_WHOLE_CYCLES_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_DIV))
    audio_clk_div_whole_cycles_q <= cfg_wdata_i[`AUDIO_CLK_DIV_WHOLE_CYCLES_R];

wire [15:0]  audio_clk_div_whole_cycles_out_w = audio_clk_div_whole_cycles_q;





reg audio_clk_frac_wr_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_clk_frac_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))
    audio_clk_frac_wr_q <= 1'b1;
else
    audio_clk_frac_wr_q <= 1'b0;


reg [15:0]  audio_clk_frac_numerator_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_clk_frac_numerator_q <= 16'd`AUDIO_CLK_FRAC_NUMERATOR_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))
    audio_clk_frac_numerator_q <= cfg_wdata_i[`AUDIO_CLK_FRAC_NUMERATOR_R];

wire [15:0]  audio_clk_frac_numerator_out_w = audio_clk_frac_numerator_q;



reg [15:0]  audio_clk_frac_denominator_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_clk_frac_denominator_q <= 16'd`AUDIO_CLK_FRAC_DENOMINATOR_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))
    audio_clk_frac_denominator_q <= cfg_wdata_i[`AUDIO_CLK_FRAC_DENOMINATOR_R];

wire [15:0]  audio_clk_frac_denominator_out_w = audio_clk_frac_denominator_q;





reg audio_fifo_write_wr_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_fifo_write_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] >= `AUDIO_FIFO_WRITE && cfg_awaddr_i[7:0] < (`AUDIO_FIFO_WRITE + 8'd32)))
    audio_fifo_write_wr_q <= 1'b1;
else
    audio_fifo_write_wr_q <= 1'b0;


wire [15:0]  audio_fifo_write_ch_b_out_w = wr_data_q[`AUDIO_FIFO_WRITE_CH_B_R];



wire [15:0]  audio_fifo_write_ch_a_out_w = wr_data_q[`AUDIO_FIFO_WRITE_CH_A_R];


wire [15:0]  audio_status_level_in_w;
wire        audio_status_full_in_w;
wire        audio_status_empty_in_w;





reg [31:0] data_r;

always @ *
begin
    data_r = 32'b0;

    case (cfg_araddr_i[7:0])

    `AUDIO_CFG:
    begin
        data_r[`AUDIO_CFG_INT_THRESHOLD_R] = audio_cfg_int_threshold_q;
        data_r[`AUDIO_CFG_BYTE_SWAP_R] = audio_cfg_byte_swap_q;
        data_r[`AUDIO_CFG_CH_SWAP_R] = audio_cfg_ch_swap_q;
        data_r[`AUDIO_CFG_TARGET_R] = audio_cfg_target_q;
        data_r[`AUDIO_CFG_VOL_CTRL_R] = audio_cfg_vol_ctrl_q;
    end
    `AUDIO_STATUS:
    begin
        data_r[`AUDIO_STATUS_LEVEL_R] = audio_status_level_in_w;
        data_r[`AUDIO_STATUS_FULL_R] = audio_status_full_in_w;
        data_r[`AUDIO_STATUS_EMPTY_R] = audio_status_empty_in_w;
    end
    `AUDIO_CLK_DIV:
    begin
        data_r[`AUDIO_CLK_DIV_WHOLE_CYCLES_R] = audio_clk_div_whole_cycles_q;
    end
    `AUDIO_CLK_FRAC:
    begin
        data_r[`AUDIO_CLK_FRAC_NUMERATOR_R] = audio_clk_frac_numerator_q;
        data_r[`AUDIO_CLK_FRAC_DENOMINATOR_R] = audio_clk_frac_denominator_q;
    end
    default :
        data_r = 32'b0;
    endcase
end




reg rvalid_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    rvalid_q <= 1'b0;
else if (read_en_w)
    rvalid_q <= 1'b1;
else if (cfg_rready_i)
    rvalid_q <= 1'b0;

assign cfg_rvalid_o = rvalid_q;




reg [31:0] rd_data_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    rd_data_q <= 32'b0;
else if (!cfg_rvalid_o || cfg_rready_i)
    rd_data_q <= data_r;

assign cfg_rdata_o = rd_data_q;
assign cfg_rresp_o = 2'b0;




reg bvalid_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    bvalid_q <= 1'b0;
else if (write_en_w)
    bvalid_q <= 1'b1;
else if (cfg_bready_i)
    bvalid_q <= 1'b0;

assign cfg_bvalid_o = bvalid_q;
assign cfg_bresp_o  = 2'b0;


wire audio_fifo_write_wr_req_w = audio_fifo_write_wr_q;

`define TARGET_W      2
`define TARGET_I2S    2'd0
`define TARGET_SPDIF  2'd1
`define TARGET_ANALOG 2'd2




reg [15:0] sample_a_r;
reg [15:0] sample_b_r;

always @ *
begin
    sample_a_r = audio_fifo_write_ch_a_out_w;
    sample_b_r = audio_fifo_write_ch_b_out_w;

    if (audio_cfg_ch_swap_out_w)
    begin
        if (audio_cfg_byte_swap_out_w)
        begin
            sample_a_r = {audio_fifo_write_ch_b_out_w[7:0], audio_fifo_write_ch_b_out_w[15:8]};
            sample_b_r = {audio_fifo_write_ch_a_out_w[7:0], audio_fifo_write_ch_a_out_w[15:8]};
        end
        else
        begin
            sample_a_r = audio_fifo_write_ch_b_out_w;
            sample_b_r = audio_fifo_write_ch_a_out_w;
        end
    end
    else
    begin
        if (audio_cfg_byte_swap_out_w)
        begin
            sample_a_r = {audio_fifo_write_ch_a_out_w[7:0], audio_fifo_write_ch_a_out_w[15:8]};
            sample_b_r = {audio_fifo_write_ch_b_out_w[7:0], audio_fifo_write_ch_b_out_w[15:8]};
        end
        else
        begin
            sample_a_r = audio_fifo_write_ch_a_out_w;
            sample_b_r = audio_fifo_write_ch_b_out_w;
        end
    end
end


wire        fifo_valid_w;
wire [31:0] fifo_data_w;
reg         fifo_pop_r;
wire        fifo_accept_w;

audio_fifo
u_fifo
(
     .clk_i(clk_i)
    ,.rst_i(rst_i)

    ,.flush_i(audio_cfg_buffer_rst_out_w)

    ,.push_i(audio_fifo_write_wr_q)
    ,.data_in_i({sample_b_r, sample_a_r})
    ,.accept_o(fifo_accept_w)

    ,.valid_o(fifo_valid_w)
    ,.data_out_o(fifo_data_w)
    ,.pop_i(fifo_pop_r)
);

reg [15:0] fifo_level_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    fifo_level_q <= 16'b0;
else if (audio_cfg_buffer_rst_out_w)
    fifo_level_q <= 16'b0;

else if ((audio_fifo_write_wr_q & fifo_accept_w) & ~(fifo_pop_r & fifo_valid_w))
    fifo_level_q <= fifo_level_q + 16'd1;

else if (~(audio_fifo_write_wr_q & fifo_accept_w) & (fifo_pop_r & fifo_valid_w))
    fifo_level_q <= fifo_level_q - 16'd1;

assign audio_status_level_in_w = fifo_level_q;
assign audio_status_full_in_w  = ~fifo_accept_w;
assign audio_status_empty_in_w = ~fifo_valid_w;




reg irq_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    irq_q <= 1'b0;
else
    irq_q <= (audio_status_level_in_w <= audio_cfg_int_threshold_out_w);

assign intr_o = irq_q;




reg        clk_out_q;
reg [15:0] clk_div_q;
reg [15:0] clk_div_r;
reg [31:0] fraction_q;
reg [31:0] fraction_r;


always @ *
begin
    clk_div_r = clk_div_q;
    fraction_r = fraction_q;

    case (clk_div_q)
    0 :
    begin
        clk_div_r = clk_div_q + 16'd1;
    end
    audio_clk_div_whole_cycles_out_w - 16'd1:
    begin
        if (fraction_q < (audio_clk_frac_denominator_out_w - audio_clk_frac_numerator_out_w))
        begin
            fraction_r = fraction_q + audio_clk_frac_numerator_out_w;
            clk_div_r  = 16'd0;
        end
        else
        begin
            fraction_r = fraction_q + audio_clk_frac_numerator_out_w - audio_clk_frac_denominator_out_w;
            clk_div_r = clk_div_q + 16'd1;
        end
    end
    audio_clk_div_whole_cycles_out_w:
    begin
        clk_div_r = 16'd0;
    end

    default:
    begin
        clk_div_r = clk_div_q + 16'd1;
    end
    endcase
end


always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    clk_div_q <= 16'd0;
else
    clk_div_q <= clk_div_r;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    fraction_q <= 32'd0;
else
    fraction_q <= fraction_r;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    clk_out_q <= 1'b0;
else
    clk_out_q <= (clk_div_q == 16'd0);






function [15:0] vol_adjust;
    input  [15:0] x;
    input  [2:0] y;
    reg [15:0] val;
begin 

    case (y)



   0 : 
   begin
         val = x;
   end



   1 : 
   begin

        if (x[15] == 1'b1)
             val = {1'b1,x[15:1]};
        else
             val = {1'b0,x[15:1]};
   end   



   2 : 
   begin

        if (x[15] == 1'b1)
             val = {2'b11,x[15:2]};
        else
             val = {2'b00,x[15:2]};
   end



   3 : 
   begin

        if (x[15] == 1'b1)
             val = {3'b111,x[15:3]};
        else
             val = {3'b000,x[15:3]};
   end



   4 : 
   begin

        if (x[15] == 1'b1)
             val = {4'b1111,x[15:4]};
        else
             val = {4'b0000,x[15:4]};
   end   



   5 : 
   begin

        if (x[15] == 1'b1)
             val = {5'b11111,x[15:5]};
        else
             val = {5'b00000,x[15:5]};
   end    



   6 : 
   begin

        if (x[15] == 1'b1)
             val = {6'b111111,x[15:6]};
        else
             val = {6'b000000,x[15:6]};         
   end



   7 : 
   begin

        if (x[15] == 1'b1)
             val = {7'b1111111,x[15:7]};
        else
             val = {7'b0000000,x[15:7]};         
   end   
   default : 
        val = x;
   endcase

   vol_adjust = val;
end
endfunction




wire [15:0] output_b_w = vol_adjust(fifo_data_w[31:16], audio_cfg_vol_ctrl_out_w);
wire [15:0] output_a_w = vol_adjust(fifo_data_w[15:0],  audio_cfg_vol_ctrl_out_w);




wire i2s_accept_w;

audio_i2s
u_i2s
(
     .clk_i(clk_i)
    ,.rst_i(rst_i)

    ,.audio_clk_i(clk_out_q && (audio_cfg_target_out_w == `TARGET_I2S))

    ,.inport_tvalid_i(fifo_valid_w && (audio_cfg_target_out_w == `TARGET_I2S))
    ,.inport_tdata_i({output_b_w, output_a_w})
    ,.inport_tstrb_i(4'hF)
    ,.inport_tdest_i(4'b0)
    ,.inport_tlast_i(1'b0)
    ,.inport_tready_o(i2s_accept_w)

    ,.i2s_sck_o(i2s_sck_o)
    ,.i2s_sdata_o(i2s_sdata_o)
    ,.i2s_ws_o(i2s_ws_o)
);




wire spdif_accept_w;

audio_spdif
u_spdif
(
     .clk_i(clk_i)
    ,.rst_i(rst_i)

    ,.audio_clk_i(clk_out_q && (audio_cfg_target_out_w == `TARGET_SPDIF))

    ,.inport_tvalid_i(fifo_valid_w && (audio_cfg_target_out_w == `TARGET_SPDIF))
    ,.inport_tdata_i({output_b_w, output_a_w})
    ,.inport_tstrb_i(4'hF)
    ,.inport_tdest_i(4'b0)
    ,.inport_tlast_i(1'b0)
    ,.inport_tready_o(spdif_accept_w)

    ,.spdif_o(spdif_o)
);




wire analog_accept_w;

audio_dac
u_dac
(
     .clk_i(clk_i)
    ,.rst_i(rst_i)

    ,.audio_clk_i(clk_out_q && (audio_cfg_target_out_w == `TARGET_ANALOG))

    ,.inport_tvalid_i(fifo_valid_w && (audio_cfg_target_out_w == `TARGET_ANALOG))
    ,.inport_tdata_i({output_b_w, output_a_w})
    ,.inport_tstrb_i(4'hF)
    ,.inport_tdest_i(4'b0)
    ,.inport_tlast_i(1'b0)
    ,.inport_tready_o(analog_accept_w)

    ,.audio_l_o(audio_l_o)
    ,.audio_r_o(audio_r_o)
);


always @ *
begin
    fifo_pop_r = 1'b0;

    case (audio_cfg_target_out_w)
    `TARGET_I2S:    fifo_pop_r = i2s_accept_w;
    `TARGET_SPDIF:  fifo_pop_r = spdif_accept_w;
    `TARGET_ANALOG: fifo_pop_r = analog_accept_w;
    default:        fifo_pop_r = 1'b0;
    endcase
end


endmodule
module audio
(

     input          clk_i
    ,input          rst_i
    ,input          cfg_awvalid_i
    ,input  [31:0]  cfg_awaddr_i
    ,input          cfg_wvalid_i
    ,input  [31:0]  cfg_wdata_i
    ,input  [3:0]   cfg_wstrb_i
    ,input          cfg_bready_i
    ,input          cfg_arvalid_i
    ,input  [31:0]  cfg_araddr_i
    ,input          cfg_rready_i


    ,output         cfg_awready_o
    ,output         cfg_wready_o
    ,output         cfg_bvalid_o
    ,output [1:0]   cfg_bresp_o
    ,output         cfg_arready_o
    ,output         cfg_rvalid_o
    ,output [31:0]  cfg_rdata_o
    ,output [1:0]   cfg_rresp_o
    ,output         audio_l_o
    ,output         audio_r_o
    ,output         spdif_o
    ,output         i2s_sck_o
    ,output         i2s_sdata_o
    ,output         i2s_ws_o
    ,output         intr_o
);





reg [31:0] wr_data_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    wr_data_q <= 32'b0;
else
    wr_data_q <= cfg_wdata_i;




wire read_en_w  = cfg_arvalid_i & cfg_arready_o;
wire write_en_w = cfg_awvalid_i & cfg_awready_o;




assign cfg_arready_o = ~cfg_rvalid_o;
assign cfg_awready_o = ~cfg_bvalid_o && ~cfg_arvalid_i; 
assign cfg_wready_o  = cfg_awready_o;





reg audio_cfg_wr_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_wr_q <= 1'b1;
else
    audio_cfg_wr_q <= 1'b0;


reg [15:0]  audio_cfg_int_threshold_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_int_threshold_q <= 16'd`AUDIO_CFG_INT_THRESHOLD_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_int_threshold_q <= cfg_wdata_i[`AUDIO_CFG_INT_THRESHOLD_R];

wire [15:0]  audio_cfg_int_threshold_out_w = audio_cfg_int_threshold_q;



reg        audio_cfg_byte_swap_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_byte_swap_q <= 1'd`AUDIO_CFG_BYTE_SWAP_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_byte_swap_q <= cfg_wdata_i[`AUDIO_CFG_BYTE_SWAP_R];

wire        audio_cfg_byte_swap_out_w = audio_cfg_byte_swap_q;



reg        audio_cfg_ch_swap_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_ch_swap_q <= 1'd`AUDIO_CFG_CH_SWAP_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_ch_swap_q <= cfg_wdata_i[`AUDIO_CFG_CH_SWAP_R];

wire        audio_cfg_ch_swap_out_w = audio_cfg_ch_swap_q;



reg [1:0]  audio_cfg_target_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_target_q <= 2'd`AUDIO_CFG_TARGET_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_target_q <= cfg_wdata_i[`AUDIO_CFG_TARGET_R];

wire [1:0]  audio_cfg_target_out_w = audio_cfg_target_q;



reg [2:0]  audio_cfg_vol_ctrl_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_vol_ctrl_q <= 3'd`AUDIO_CFG_VOL_CTRL_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_vol_ctrl_q <= cfg_wdata_i[`AUDIO_CFG_VOL_CTRL_R];

wire [2:0]  audio_cfg_vol_ctrl_out_w = audio_cfg_vol_ctrl_q;



reg        audio_cfg_buffer_rst_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_cfg_buffer_rst_q <= 1'd`AUDIO_CFG_BUFFER_RST_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
    audio_cfg_buffer_rst_q <= cfg_wdata_i[`AUDIO_CFG_BUFFER_RST_R];
else
    audio_cfg_buffer_rst_q <= 1'd`AUDIO_CFG_BUFFER_RST_DEFAULT;

wire        audio_cfg_buffer_rst_out_w = audio_cfg_buffer_rst_q;





reg audio_status_wr_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_status_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_STATUS))
    audio_status_wr_q <= 1'b1;
else
    audio_status_wr_q <= 1'b0;







reg audio_clk_div_wr_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_clk_div_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_DIV))
    audio_clk_div_wr_q <= 1'b1;
else
    audio_clk_div_wr_q <= 1'b0;


reg [15:0]  audio_clk_div_whole_cycles_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_clk_div_whole_cycles_q <= 16'd`AUDIO_CLK_DIV_WHOLE_CYCLES_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_DIV))
    audio_clk_div_whole_cycles_q <= cfg_wdata_i[`AUDIO_CLK_DIV_WHOLE_CYCLES_R];

wire [15:0]  audio_clk_div_whole_cycles_out_w = audio_clk_div_whole_cycles_q;





reg audio_clk_frac_wr_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_clk_frac_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))
    audio_clk_frac_wr_q <= 1'b1;
else
    audio_clk_frac_wr_q <= 1'b0;


reg [15:0]  audio_clk_frac_numerator_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_clk_frac_numerator_q <= 16'd`AUDIO_CLK_FRAC_NUMERATOR_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))
    audio_clk_frac_numerator_q <= cfg_wdata_i[`AUDIO_CLK_FRAC_NUMERATOR_R];

wire [15:0]  audio_clk_frac_numerator_out_w = audio_clk_frac_numerator_q;



reg [15:0]  audio_clk_frac_denominator_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_clk_frac_denominator_q <= 16'd`AUDIO_CLK_FRAC_DENOMINATOR_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))
    audio_clk_frac_denominator_q <= cfg_wdata_i[`AUDIO_CLK_FRAC_DENOMINATOR_R];

wire [15:0]  audio_clk_frac_denominator_out_w = audio_clk_frac_denominator_q;





reg audio_fifo_write_wr_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    audio_fifo_write_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] >= `AUDIO_FIFO_WRITE && cfg_awaddr_i[7:0] < (`AUDIO_FIFO_WRITE + 8'd32)))
    audio_fifo_write_wr_q <= 1'b1;
else
    audio_fifo_write_wr_q <= 1'b0;


wire [15:0]  audio_fifo_write_ch_b_out_w = wr_data_q[`AUDIO_FIFO_WRITE_CH_B_R];



wire [15:0]  audio_fifo_write_ch_a_out_w = wr_data_q[`AUDIO_FIFO_WRITE_CH_A_R];


wire [15:0]  audio_status_level_in_w;
wire        audio_status_full_in_w;
wire        audio_status_empty_in_w;





reg [31:0] data_r;

always @ *
begin
    data_r = 32'b0;

    case (cfg_araddr_i[7:0])

    `AUDIO_CFG:
    begin
        data_r[`AUDIO_CFG_INT_THRESHOLD_R] = audio_cfg_int_threshold_q;
        data_r[`AUDIO_CFG_BYTE_SWAP_R] = audio_cfg_byte_swap_q;
        data_r[`AUDIO_CFG_CH_SWAP_R] = audio_cfg_ch_swap_q;
        data_r[`AUDIO_CFG_TARGET_R] = audio_cfg_target_q;
        data_r[`AUDIO_CFG_VOL_CTRL_R] = audio_cfg_vol_ctrl_q;
    end
    `AUDIO_STATUS:
    begin
        data_r[`AUDIO_STATUS_LEVEL_R] = audio_status_level_in_w;
        data_r[`AUDIO_STATUS_FULL_R] = audio_status_full_in_w;
        data_r[`AUDIO_STATUS_EMPTY_R] = audio_status_empty_in_w;
    end
    `AUDIO_CLK_DIV:
    begin
        data_r[`AUDIO_CLK_DIV_WHOLE_CYCLES_R] = audio_clk_div_whole_cycles_q;
    end
    `AUDIO_CLK_FRAC:
    begin
        data_r[`AUDIO_CLK_FRAC_NUMERATOR_R] = audio_clk_frac_numerator_q;
        data_r[`AUDIO_CLK_FRAC_DENOMINATOR_R] = audio_clk_frac_denominator_q;
    end
    default :
        data_r = 32'b0;
    endcase
end




reg rvalid_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    rvalid_q <= 1'b0;
else if (read_en_w)
    rvalid_q <= 1'b1;
else if (cfg_rready_i)
    rvalid_q <= 1'b0;

assign cfg_rvalid_o = rvalid_q;




reg [31:0] rd_data_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    rd_data_q <= 32'b0;
else if (!cfg_rvalid_o || cfg_rready_i)
    rd_data_q <= data_r;

assign cfg_rdata_o = rd_data_q;
assign cfg_rresp_o = 2'b0;




reg bvalid_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    bvalid_q <= 1'b0;
else if (write_en_w)
    bvalid_q <= 1'b1;
else if (cfg_bready_i)
    bvalid_q <= 1'b0;

assign cfg_bvalid_o = bvalid_q;
assign cfg_bresp_o  = 2'b0;


wire audio_fifo_write_wr_req_w = audio_fifo_write_wr_q;

`define TARGET_W      2
`define TARGET_I2S    2'd0
`define TARGET_SPDIF  2'd1
`define TARGET_ANALOG 2'd2




reg [15:0] sample_a_r;
reg [15:0] sample_b_r;

always @ *
begin
    sample_a_r = audio_fifo_write_ch_a_out_w;
    sample_b_r = audio_fifo_write_ch_b_out_w;

    if (audio_cfg_ch_swap_out_w)
    begin
        if (audio_cfg_byte_swap_out_w)
        begin
            sample_a_r = {audio_fifo_write_ch_b_out_w[7:0], audio_fifo_write_ch_b_out_w[15:8]};
            sample_b_r = {audio_fifo_write_ch_a_out_w[7:0], audio_fifo_write_ch_a_out_w[15:8]};
        end
        else
        begin
            sample_a_r = audio_fifo_write_ch_b_out_w;
            sample_b_r = audio_fifo_write_ch_a_out_w;
        end
    end
    else
    begin
        if (audio_cfg_byte_swap_out_w)
        begin
            sample_a_r = {audio_fifo_write_ch_a_out_w[7:0], audio_fifo_write_ch_a_out_w[15:8]};
            sample_b_r = {audio_fifo_write_ch_b_out_w[7:0], audio_fifo_write_ch_b_out_w[15:8]};
        end
        else
        begin
            sample_a_r = audio_fifo_write_ch_a_out_w;
            sample_b_r = audio_fifo_write_ch_b_out_w;
        end
    end
end


wire        fifo_valid_w;
wire [31:0] fifo_data_w;
reg         fifo_pop_r;
wire        fifo_accept_w;

audio_fifo
u_fifo
(
     .clk_i(clk_i)
    ,.rst_i(rst_i)

    ,.flush_i(audio_cfg_buffer_rst_out_w)

    ,.push_i(audio_fifo_write_wr_q)
    ,.data_in_i({sample_b_r, sample_a_r})
    ,.accept_o(fifo_accept_w)

    ,.valid_o(fifo_valid_w)
    ,.data_out_o(fifo_data_w)
    ,.pop_i(fifo_pop_r)
);

reg [15:0] fifo_level_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    fifo_level_q <= 16'b0;
else if (audio_cfg_buffer_rst_out_w)
    fifo_level_q <= 16'b0;

else if ((audio_fifo_write_wr_q & fifo_accept_w) & ~(fifo_pop_r & fifo_valid_w))
    fifo_level_q <= fifo_level_q + 16'd1;

else if (~(audio_fifo_write_wr_q & fifo_accept_w) & (fifo_pop_r & fifo_valid_w))
    fifo_level_q <= fifo_level_q - 16'd1;

assign audio_status_level_in_w = fifo_level_q;
assign audio_status_full_in_w  = ~fifo_accept_w;
assign audio_status_empty_in_w = ~fifo_valid_w;




reg irq_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    irq_q <= 1'b0;
else
    irq_q <= (audio_status_level_in_w <= audio_cfg_int_threshold_out_w);

assign intr_o = irq_q;




reg        clk_out_q;
reg [15:0] clk_div_q;
reg [15:0] clk_div_r;
reg [31:0] fraction_q;
reg [31:0] fraction_r;


always @ *
begin
    clk_div_r = clk_div_q;
    fraction_r = fraction_q;

    case (clk_div_q)
    0 :
    begin
        clk_div_r = clk_div_q + 16'd1;
    end
    audio_clk_div_whole_cycles_out_w - 16'd1:
    begin
        if (fraction_q < (audio_clk_frac_denominator_out_w - audio_clk_frac_numerator_out_w))
        begin
            fraction_r = fraction_q + audio_clk_frac_numerator_out_w;
            clk_div_r  = 16'd0;
        end
        else
        begin
            fraction_r = fraction_q + audio_clk_frac_numerator_out_w - audio_clk_frac_denominator_out_w;
            clk_div_r = clk_div_q + 16'd1;
        end
    end
    audio_clk_div_whole_cycles_out_w:
    begin
        clk_div_r = 16'd0;
    end

    default:
    begin
        clk_div_r = clk_div_q + 16'd1;
    end
    endcase
end


always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    clk_div_q <= 16'd0;
else
    clk_div_q <= clk_div_r;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    fraction_q <= 32'd0;
else
    fraction_q <= fraction_r;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    clk_out_q <= 1'b0;
else
    clk_out_q <= (clk_div_q == 16'd0);






function [15:0] vol_adjust;
    input  [15:0] x;
    input  [2:0] y;
    reg [15:0] val;
begin 

    case (y)



   0 : 
   begin
         val = x;
   end



   1 : 
   begin

        if (x[15] == 1'b1)
             val = {1'b1,x[15:1]};
        else
             val = {1'b0,x[15:1]};
   end   



   2 : 
   begin

        if (x[15] == 1'b1)
             val = {2'b11,x[15:2]};
        else
             val = {2'b00,x[15:2]};
   end



   3 : 
   begin

        if (x[15] == 1'b1)
             val = {3'b111,x[15:3]};
        else
             val = {3'b000,x[15:3]};
   end



   4 : 
   begin

        if (x[15] == 1'b1)
             val = {4'b1111,x[15:4]};
        else
             val = {4'b0000,x[15:4]};
   end   



   5 : 
   begin

        if (x[15] == 1'b1)
             val = {5'b11111,x[15:5]};
        else
             val = {5'b00000,x[15:5]};
   end    



   6 : 
   begin

        if (x[15] == 1'b1)
             val = {6'b111111,x[15:6]};
        else
             val = {6'b000000,x[15:6]};         
   end



   7 : 
   begin

        if (x[15] == 1'b1)
             val = {7'b1111111,x[15:7]};
        else
             val = {7'b0000000,x[15:7]};         
   end   
   default : 
        val = x;
   endcase

   vol_adjust = val;
end
endfunction




wire [15:0] output_b_w = vol_adjust(fifo_data_w[31:16], audio_cfg_vol_ctrl_out_w);
wire [15:0] output_a_w = vol_adjust(fifo_data_w[15:0],  audio_cfg_vol_ctrl_out_w);




wire i2s_accept_w;

audio_i2s
u_i2s
(
     .clk_i(clk_i)
    ,.rst_i(rst_i)

    ,.audio_clk_i(clk_out_q && (audio_cfg_target_out_w == `TARGET_I2S))

    ,.inport_tvalid_i(fifo_valid_w && (audio_cfg_target_out_w == `TARGET_I2S))
    ,.inport_tdata_i({output_b_w, output_a_w})
    ,.inport_tstrb_i(4'hF)
    ,.inport_tdest_i(4'b0)
    ,.inport_tlast_i(1'b0)
    ,.inport_tready_o(i2s_accept_w)

    ,.i2s_sck_o(i2s_sck_o)
    ,.i2s_sdata_o(i2s_sdata_o)
    ,.i2s_ws_o(i2s_ws_o)
);




wire spdif_accept_w;

audio_spdif
u_spdif
(
     .clk_i(clk_i)
    ,.rst_i(rst_i)

    ,.audio_clk_i(clk_out_q && (audio_cfg_target_out_w == `TARGET_SPDIF))

    ,.inport_tvalid_i(fifo_valid_w && (audio_cfg_target_out_w == `TARGET_SPDIF))
    ,.inport_tdata_i({output_b_w, output_a_w})
    ,.inport_tstrb_i(4'hF)
    ,.inport_tdest_i(4'b0)
    ,.inport_tlast_i(1'b0)
    ,.inport_tready_o(spdif_accept_w)

    ,.spdif_o(spdif_o)
);




wire analog_accept_w;

audio_dac
u_dac
(
     .clk_i(clk_i)
    ,.rst_i(rst_i)

    ,.audio_clk_i(clk_out_q && (audio_cfg_target_out_w == `TARGET_ANALOG))

    ,.inport_tvalid_i(fifo_valid_w && (audio_cfg_target_out_w == `TARGET_ANALOG))
    ,.inport_tdata_i({output_b_w, output_a_w})
    ,.inport_tstrb_i(4'hF)
    ,.inport_tdest_i(4'b0)
    ,.inport_tlast_i(1'b0)
    ,.inport_tready_o(analog_accept_w)

    ,.audio_l_o(audio_l_o)
    ,.audio_r_o(audio_r_o)
);


always @ *
begin
    fifo_pop_r = 1'b0;

    case (audio_cfg_target_out_w)
    `TARGET_I2S:    fifo_pop_r = i2s_accept_w;
    `TARGET_SPDIF:  fifo_pop_r = spdif_accept_w;
    `TARGET_ANALOG: fifo_pop_r = analog_accept_w;
    default:        fifo_pop_r = 1'b0;
    endcase
end


endmodule