data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:3: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/src/cpu/core/stage/pc,data/full_repos/permissive/201275379/bus.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/pc,data/full_repos/permissive/201275379/bus.v.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/pc,data/full_repos/permissive/201275379/bus.v.sv\n             bus.v\n             bus.v.v\n             bus.v.sv\n             obj_dir/bus.v\n             obj_dir/bus.v.v\n             obj_dir/bus.v.sv\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:4: Cannot find include file: exception.v\n`include "exception.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:5: Cannot find include file: branch.v\n`include "branch.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:13: Define or directive not defined: \'`ADDR_BUS\'\n  input   [`ADDR_BUS] exc_pc,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:13: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  input   [`ADDR_BUS] exc_pc,\n                    ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:18: Define or directive not defined: \'`GHR_BUS\'\n  input   [`GHR_BUS]  last_pht_index,    \n           ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:19: Define or directive not defined: \'`ADDR_BUS\'\n  input   [`ADDR_BUS] inst_pc,           \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:20: Define or directive not defined: \'`ADDR_BUS\'\n  input   [`ADDR_BUS] target_in,         \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:23: Define or directive not defined: \'`GHR_BUS\'\n  output  [`GHR_BUS]  pht_index_out,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:24: Define or directive not defined: \'`ADDR_BUS\'\n  output  [`ADDR_BUS] pc_out\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:28: Define or directive not defined: \'`ADDR_BUS\'\n  reg[`ADDR_BUS] pc_reg, pc_out_reg;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`ADDR_BUS] pc_reg, pc_out_reg;\n               ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:32: Define or directive not defined: \'`GHR_BUS\'\n  wire[`GHR_BUS] ghr_out;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`GHR_BUS] ghr_out;\n               ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:43: Define or directive not defined: \'`GHR_BUS\'\n  wire[`GHR_BUS] pht_index;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`GHR_BUS] pht_index;\n               ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:45: syntax error, unexpected assign\n  assign pht_index = pc_out[`GHR_WIDTH + 1:2] ^ ghr_out;   \n  ^~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:45: Define or directive not defined: \'`GHR_WIDTH\'\n  assign pht_index = pc_out[`GHR_WIDTH + 1:2] ^ ghr_out;   \n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:60: Define or directive not defined: \'`ADDR_BUS\'\n  wire[`ADDR_BUS] btb_target;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:60: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`ADDR_BUS] btb_target;\n                ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:76: Define or directive not defined: \'`ADDR_BUS\'\n  reg[`ADDR_BUS] next_pc;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:76: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`ADDR_BUS] next_pc;\n               ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:97: Define or directive not defined: \'`INIT_PC\'\n      pc_reg <= `INIT_PC + 4;\n                ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:98: Define or directive not defined: \'`INIT_PC\'\n      pc_out_reg <= `INIT_PC;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PC.v:104: Define or directive not defined: \'`INVALID_PC\'\n      pc_out_reg <= is_branch_in ? inst_pc + 4 : `INVALID_PC;\n                                                 ^~~~~~~~~~~\n%Error: Exiting due to 25 error(s)\n'
module PC(
  input               clk,
  input               rst,

  input               flush,
  input               stall,
  input   [`ADDR_BUS] exc_pc,

  input               is_branch_in,
  input               is_jump_in,
  input               is_taken_in,
  input   [`GHR_BUS]  last_pht_index,
  input   [`ADDR_BUS] inst_pc,
  input   [`ADDR_BUS] target_in,

  output              is_branch_taken,
  output  [`GHR_BUS]  pht_index_out,
  output  [`ADDR_BUS] pc_out
);


  reg[`ADDR_BUS] pc_reg, pc_out_reg;
  assign pc_out = pc_out_reg;


  wire[`GHR_BUS] ghr_out;

  GHR ghr_reg(
    .clk              (clk),
    .rst              (rst),
    .is_branch        (is_branch_in),
    .is_taken         (is_taken_in),
    .ghr_out          (ghr_out)
  );


  wire[`GHR_BUS] pht_index;
  wire pht_is_taken;
  assign pht_index = pc_out[`GHR_WIDTH + 1:2] ^ ghr_out;
  assign pht_index_out = pht_index;

  PHT pht(
    .clk              (clk),
    .rst              (rst),
    .is_last_branch   (is_branch_in),
    .is_last_taken    (is_taken_in),
    .last_index       (last_pht_index),
    .index            (pht_index),
    .is_taken_out     (pht_is_taken)
  );


  wire btb_is_branch, btb_is_jump;
  wire[`ADDR_BUS] btb_target;

  BTB btb(
    .clk              (clk),
    .rst              (rst),
    .is_branch_in     (is_branch_in),
    .is_jump_in       (is_jump_in),
    .inst_pc          (inst_pc),
    .target_in        (target_in),
    .pc_in            (pc_out),
    .is_branch_out    (btb_is_branch),
    .is_jump_out      (btb_is_jump),
    .target_out       (btb_target)
  );


  reg[`ADDR_BUS] next_pc;
  assign is_branch_taken = btb_is_branch && (pht_is_taken || btb_is_jump);

  always @(*) begin
    if (flush) begin
      next_pc <= exc_pc;
    end
    else if (stall) begin
      next_pc <= pc_reg;
    end
    else if (is_branch_taken) begin
      next_pc <= btb_target;
    end
    else begin
      next_pc <= pc_reg + 4;
    end
  end


  always @(posedge clk) begin
    if (!rst) begin
      pc_reg <= `INIT_PC + 4;
      pc_out_reg <= `INIT_PC;
    end
    else if (flush) begin
      pc_reg <= next_pc;


      pc_out_reg <= is_branch_in ? inst_pc + 4 : `INVALID_PC;
    end
    else if (!stall) begin



      pc_reg <= next_pc;
      pc_out_reg <= pc_reg;
    end
  end

endmodule
module PC(
  input               clk,
  input               rst,

  input               flush,
  input               stall,
  input   [`ADDR_BUS] exc_pc,

  input               is_branch_in,
  input               is_jump_in,
  input               is_taken_in,
  input   [`GHR_BUS]  last_pht_index,
  input   [`ADDR_BUS] inst_pc,
  input   [`ADDR_BUS] target_in,

  output              is_branch_taken,
  output  [`GHR_BUS]  pht_index_out,
  output  [`ADDR_BUS] pc_out
);



  reg[`ADDR_BUS] pc_reg, pc_out_reg;
  assign pc_out = pc_out_reg;


  wire[`GHR_BUS] ghr_out;

  GHR ghr_reg(
    .clk              (clk),
    .rst              (rst),
    .is_branch        (is_branch_in),
    .is_taken         (is_taken_in),
    .ghr_out          (ghr_out)
  );


  wire[`GHR_BUS] pht_index;
  wire pht_is_taken;
  assign pht_index = pc_out[`GHR_WIDTH + 1:2] ^ ghr_out;
  assign pht_index_out = pht_index;

  PHT pht(
    .clk              (clk),
    .rst              (rst),
    .is_last_branch   (is_branch_in),
    .is_last_taken    (is_taken_in),
    .last_index       (last_pht_index),
    .index            (pht_index),
    .is_taken_out     (pht_is_taken)
  );


  wire btb_is_branch, btb_is_jump;
  wire[`ADDR_BUS] btb_target;

  BTB btb(
    .clk              (clk),
    .rst              (rst),
    .is_branch_in     (is_branch_in),
    .is_jump_in       (is_jump_in),
    .inst_pc          (inst_pc),
    .target_in        (target_in),
    .pc_in            (pc_out),
    .is_branch_out    (btb_is_branch),
    .is_jump_out      (btb_is_jump),
    .target_out       (btb_target)
  );


  reg[`ADDR_BUS] next_pc;
  assign is_branch_taken = btb_is_branch && (pht_is_taken || btb_is_jump);

  always @(*) begin
    if (flush) begin
      next_pc <= exc_pc;
    end
    else if (stall) begin
      next_pc <= pc_reg;
    end
    else if (is_branch_taken) begin
      next_pc <= btb_target;
    end
    else begin
      next_pc <= pc_reg + 4;
    end
  end


  always @(posedge clk) begin
    if (!rst) begin
      pc_reg <= `INIT_PC + 4;
      pc_out_reg <= `INIT_PC;
    end
    else if (flush) begin
      pc_reg <= next_pc;


      pc_out_reg <= is_branch_in ? inst_pc + 4 : `INVALID_PC;
    end
    else if (!stall) begin



      pc_reg <= next_pc;
      pc_out_reg <= pc_reg;
    end
  end

endmodule