data/full_repos/permissive/209997170/6. time counter/work/planAhead/decimal selector/decimal selector.srcs/sources_1/imports/verilog/decimal_counter_9.v
 line:17: before: "="
1: b'%Error: Cannot find file containing module: time\n        ... Looked in:\n             data/full_repos/permissive/209997170/6./time\n             data/full_repos/permissive/209997170/6./time.v\n             data/full_repos/permissive/209997170/6./time.sv\n             time\n             time.v\n             time.sv\n             obj_dir/time\n             obj_dir/time.v\n             obj_dir/time.sv\n%Error: Cannot find file containing module: counter/work/planAhead/decimal\n%Error: Cannot find file containing module: selector/decimal\n%Error: Cannot find file containing module: selector.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170\n%Error: Cannot find file containing module: data/full_repos/permissive/209997170/6.\n%Error: Cannot find file containing module: selector.srcs/sources_1/imports/verilog/decimal_counter_9.v\n%Error: Exiting due to 6 error(s)\n'
module decimal_counter_9 (
    input clk,
    input rst,
    input inc,
    output reg ovf,
    output reg [3:0] value
  );
  
  
  
  reg [3:0] M_val_d, M_val_q = 1'h0;
  
  always @* begin
    M_val_d = M_val_q;
    
    value = M_val_q;
    ovf = M_val_q == 4'h9 && inc;
    if (inc) begin
      if (M_val_q == 4'h9) begin
        M_val_d = 1'h0;
      end else begin
        M_val_d = M_val_q + 1'h1;
      end
    end
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_val_q <= 1'h0;
    end else begin
      M_val_q <= M_val_d;
    end
  end
  
endmodule
module decimal_counter_9 (
    input clk,
    input rst,
    input inc,
    output reg ovf,
    output reg [3:0] value
  );

  
  
  
  reg [3:0] M_val_d, M_val_q = 1'h0;
  
  always @* begin
    M_val_d = M_val_q;
    
    value = M_val_q;
    ovf = M_val_q == 4'h9 && inc;
    if (inc) begin
      if (M_val_q == 4'h9) begin
        M_val_d = 1'h0;
      end else begin
        M_val_d = M_val_q + 1'h1;
      end
    end
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_val_q <= 1'h0;
    end else begin
      M_val_q <= M_val_d;
    end
  end
  
endmodule