data/full_repos/permissive/150152921/apps/dotproduct/step2/tb/dot16_tb.v
 line:127: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/150152921/apps/dotproduct/step2/tb/dot16_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_P/2) clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150152921/apps/dotproduct/step2/tb/dot16_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #0   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150152921/apps/dotproduct/step2/tb/dot16_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #(20*CLK_P)     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150152921/apps/dotproduct/step2/tb/dot16_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n        #(10*CLK_P)     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150152921/apps/dotproduct/step2/tb/dot16_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_P)\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150152921/apps/dotproduct/step2/tb/dot16_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n        #(100*CLK_P)    \n        ^\n%Error: data/full_repos/permissive/150152921/apps/dotproduct/step2/tb/dot16_tb.v:54: Cannot find file containing module: \'top\'\n    top #(DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot_inst\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/150152921/apps/dotproduct/step2/tb,data/full_repos/permissive/150152921/top\n             data/full_repos/permissive/150152921/apps/dotproduct/step2/tb,data/full_repos/permissive/150152921/top.v\n             data/full_repos/permissive/150152921/apps/dotproduct/step2/tb,data/full_repos/permissive/150152921/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dot16_tb;


    localparam DATA_WIDTH = 8;
    localparam MULT_LATENCY = 4;
    localparam TREE_DELAY = 1;
    localparam CLK_P = 10;


    reg     clk;
    reg     rst;
    reg     ena;

    reg     [DATA_WIDTH-1:0]    a[0:15];
    reg     [DATA_WIDTH-1:0]    b[0:15];
    wire    [DATA_WIDTH*2-1+4:0]    results;

    reg     [DATA_WIDTH*2-1+4:0]    acc;
    reg     [DATA_WIDTH*2-1+4:0]    exp_res;

    integer i, j, k;


    top #(DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot_inst
    (
        .clk(clk),
        .rst(rst),
        .ena(ena),

        .a1_in(a[0]),
        .a2_in(a[1]),
        .a3_in(a[2]),
        .a4_in(a[3]),
        .a5_in(a[4]),
        .a6_in(a[5]),
        .a7_in(a[6]),
        .a8_in(a[7]),
        .a9_in(a[8]),
        .a10_in(a[9]),
        .a11_in(a[10]),
        .a12_in(a[11]),
        .a13_in(a[12]),
        .a14_in(a[13]),
        .a15_in(a[14]),
        .a16_in(a[15]),

        .b1_in(b[0]),
        .b2_in(b[1]),
        .b3_in(b[2]),
        .b4_in(b[3]),
        .b5_in(b[4]),
        .b6_in(b[5]),
        .b7_in(b[6]),
        .b8_in(b[7]),
        .b9_in(b[8]),
        .b10_in(b[9]),
        .b11_in(b[10]),
        .b12_in(b[11]),
        .b13_in(b[12]),
        .b14_in(b[13]),
        .b15_in(b[14]),
        .b16_in(b[15]),

        .res_out(results)
    );


    always #(CLK_P/2) clk = ~clk;


    initial begin
        #0
        clk = 1;
        rst = 1;
        ena = 1;


        for(i = 0; i < 16; i = i + 1) begin
            a[i] = 0;
            b[i] = 0;
        end

        #(20*CLK_P)
        rst = 0;

        #(10*CLK_P)
        a[1] = 3;
        b[1] = 4;

        #(CLK_P)
        a[2] = 5;
        b[2] = 10;
        a[5] = 6;
        b[5] = 9;

        #(100*CLK_P)
        $display("PASS!");
        $finish;
    end


    always @(*) begin
        acc = 0;
        for (j = 0; j < 16; j = j + 1) begin
            acc = acc + a[j] * b[j];
        end
        exp_res <= #(CLK_P*11) acc;
    end


    always @(posedge clk) begin

        if (exp_res !== results && rst == 0) begin
            $display("Error: results %d != expected results %d @ %t", results, exp_res, $time);
            $stop;
        end
    end


endmodule
module dot16_tb;



    localparam DATA_WIDTH = 8;
    localparam MULT_LATENCY = 4;
    localparam TREE_DELAY = 1;
    localparam CLK_P = 10;


    reg     clk;
    reg     rst;
    reg     ena;

    reg     [DATA_WIDTH-1:0]    a[0:15];
    reg     [DATA_WIDTH-1:0]    b[0:15];
    wire    [DATA_WIDTH*2-1+4:0]    results;

    reg     [DATA_WIDTH*2-1+4:0]    acc;
    reg     [DATA_WIDTH*2-1+4:0]    exp_res;

    integer i, j, k;


    top #(DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot_inst
    (
        .clk(clk),
        .rst(rst),
        .ena(ena),

        .a1_in(a[0]),
        .a2_in(a[1]),
        .a3_in(a[2]),
        .a4_in(a[3]),
        .a5_in(a[4]),
        .a6_in(a[5]),
        .a7_in(a[6]),
        .a8_in(a[7]),
        .a9_in(a[8]),
        .a10_in(a[9]),
        .a11_in(a[10]),
        .a12_in(a[11]),
        .a13_in(a[12]),
        .a14_in(a[13]),
        .a15_in(a[14]),
        .a16_in(a[15]),

        .b1_in(b[0]),
        .b2_in(b[1]),
        .b3_in(b[2]),
        .b4_in(b[3]),
        .b5_in(b[4]),
        .b6_in(b[5]),
        .b7_in(b[6]),
        .b8_in(b[7]),
        .b9_in(b[8]),
        .b10_in(b[9]),
        .b11_in(b[10]),
        .b12_in(b[11]),
        .b13_in(b[12]),
        .b14_in(b[13]),
        .b15_in(b[14]),
        .b16_in(b[15]),

        .res_out(results)
    );


    always #(CLK_P/2) clk = ~clk;


    initial begin
        #0
        clk = 1;
        rst = 1;
        ena = 1;


        for(i = 0; i < 16; i = i + 1) begin
            a[i] = 0;
            b[i] = 0;
        end

        #(20*CLK_P)
        rst = 0;

        #(10*CLK_P)
        a[1] = 3;
        b[1] = 4;

        #(CLK_P)
        a[2] = 5;
        b[2] = 10;
        a[5] = 6;
        b[5] = 9;

        #(100*CLK_P)
        $display("PASS!");
        $finish;
    end


    always @(*) begin
        acc = 0;
        for (j = 0; j < 16; j = j + 1) begin
            acc = acc + a[j] * b[j];
        end
        exp_res <= #(CLK_P*11) acc;
    end


    always @(posedge clk) begin

        if (exp_res !== results && rst == 0) begin
            $display("Error: results %d != expected results %d @ %t", results, exp_res, $time);
            $stop;
        end
    end


endmodule