data/full_repos/permissive/133161058/cla/hdl/BitMux21.v
 line:43: before: "ays"
data/verilator_xmls/639c9e33-13be-4fb9-b89c-dd30086dd80d.xml
module BitMux2_1 (out,a,b,select);
        output out;
        input a,b,select;
reg out;

always @ (select or a or b)
	case (select)
		1'b0:  out <= a;
		1'b1:  out <= b;
		default:  out <= b;
	endcase
endmodule
module BitMux2_1 (out,a,b,select);

        output out;
        input a,b,select;
reg out;

always @ (select or a or b)
	case (select)
		1'b0:  out <= a;
		1'b1:  out <= b;
		default:  out <= b;
	endcase
endmodule