data/full_repos/permissive/114421971/clbpips/top.v
None: at end of input
1: b'%Error: data/full_repos/permissive/114421971/clbpips/top.v:1: Cannot find include file: setseed.vh\n`include "setseed.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh\n             data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh.v\n             data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh.sv\n             setseed.vh\n             setseed.vh.v\n             setseed.vh.sv\n             obj_dir/setseed.vh\n             obj_dir/setseed.vh.v\n             obj_dir/setseed.vh.sv\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:3: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n                                      ^~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n        ^~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:45: Define or directive not defined: \'`SEED\'\n   hash32 = v ^ `SEED;\n                ^~~~~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   hash32 = v ^ `SEED;\n                     ^\n%Error: Exiting due to 5 error(s)\n'
function [63:0] hash64(input [31:0] v);
		begin
			hash64[63:32] = hash32(v);
			hash64[31: 0] = hash32(~v);
		end
	endfunction
function [63:0] hash64(input [31:0] v);

		begin
			hash64[63:32] = hash32(v);
			hash64[31: 0] = hash32(~v);
		end
	endfunction