data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog/seg_execute.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog/seg_execute.v:62: Signal definition not found, creating implicitly: \'RegDst\'\n    assign RegDst           = i_ctrl_exc_bus[0];\n           ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog/seg_execute.v:98: Cannot find file containing module: \'seg_execute_alu_control\'\n    seg_execute_alu_control \n    ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog,data/full_repos/permissive/206437232/seg_execute_alu_control\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog,data/full_repos/permissive/206437232/seg_execute_alu_control.v\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog,data/full_repos/permissive/206437232/seg_execute_alu_control.sv\n             seg_execute_alu_control\n             seg_execute_alu_control.v\n             seg_execute_alu_control.sv\n             obj_dir/seg_execute_alu_control\n             obj_dir/seg_execute_alu_control.v\n             obj_dir/seg_execute_alu_control.sv\n%Error: data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog/seg_execute.v:110: Cannot find file containing module: \'seg_execute_alu\'\n    seg_execute_alu\n    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module seg_execute
    #( parameter    LEN             = 32,
       parameter    NB_ALUOP        = 4,
       parameter    NB_ALUCTL       = 4,
       parameter    NB_ADDR         = 5,
       parameter    NB_FUNC         = 6,
       parameter    NB_CTRL_WB      = 2,
       parameter    NB_CTRL_M       = 9,
       parameter    NB_CTRL_EX      = 6
    )
    (

        input wire                          i_clk,
        input wire                          i_rst,
        input wire [LEN - 1 : 0]            i_PC,
        input wire [LEN - 1 : 0]            i_read_data_1,
        input wire [LEN - 1 : 0]            i_read_data_2,
        input wire [LEN - 1 : 0]            i_addr_ext,
        input wire [NB_ADDR - 1 : 0]        i_rt,
        input wire [NB_ADDR - 1 : 0]        i_rd,
        input wire                          i_flush,

        input wire [NB_CTRL_WB - 1 : 0]     i_ctrl_wb_bus,
        input wire [NB_CTRL_M - 1 :  0]     i_ctrl_mem_bus,
        input wire [NB_CTRL_EX - 1 : 0]     i_ctrl_exc_bus,

        input wire [1:0]                    i_muxA_forwarding,
        input wire [1:0]                    i_muxB_forwarding, 
        input wire [LEN - 1 : 0]            i_rd_mem_forwarding,
        input wire [LEN - 1 : 0]            i_rd_wb_forwarding, 

        output wire [LEN - 1 : 0]           o_PC_branch,
        output wire [LEN - 1 : 0]           o_ALU_result,
        output wire [LEN - 1 : 0]           o_write_data,
        output wire [NB_ADDR - 1 : 0]       o_write_register,
        output wire                         o_ALU_zero,

        output wire [NB_CTRL_WB - 1 : 0]    o_ctrl_wb_bus,
        output wire [NB_CTRL_M - 1 : 0]     o_ctrl_mem_bus
    );


    wire        [NB_ALUOP - 1 : 0]  ALUOp;
    wire                            ALUSrc;

    reg         [LEN - 1 : 0]       reg_PC;

    wire        [LEN - 1 : 0]       data_b;
    wire        [NB_ALUCTL - 1 : 0] ALUctl;
    wire        [NB_FUNC - 1 : 0]   funct;


    wire        [LEN - 1 : 0]       muxA_Alu;
    wire        [LEN - 1 : 0]       muxB_Alu;
    
    assign funct            = i_addr_ext[NB_FUNC-1:0];

    assign ALUSrc           = i_ctrl_exc_bus[NB_ALUOP + 1];
    assign ALUOp            = i_ctrl_exc_bus[NB_ALUOP : 1];
    assign RegDst           = i_ctrl_exc_bus[0];

    assign o_PC_branch      = reg_PC;

    assign o_ctrl_wb_bus    = (i_flush) ? 0 : i_ctrl_wb_bus;
    assign o_ctrl_mem_bus   = (i_flush) ? 0 : i_ctrl_mem_bus;
    

    always @(posedge i_clk) begin
        if (!i_rst) begin
            reg_PC <= {LEN{1'b0}};
        end else begin
            reg_PC <= i_PC + i_addr_ext;
        end
    end


    assign muxA_Alu = (i_muxA_forwarding == 2'b00) ? i_read_data_1 :
                      (i_muxA_forwarding == 2'b01) ? i_rd_mem_forwarding :
                      (i_muxA_forwarding == 2'b10) ? i_rd_wb_forwarding :
                      i_read_data_1;


    assign muxB_Alu = (i_muxB_forwarding == 2'b00) ? i_read_data_2 :
                      (i_muxB_forwarding == 2'b01) ? i_rd_mem_forwarding :
                      (i_muxB_forwarding == 2'b10) ? i_rd_wb_forwarding :
                      i_read_data_2;

    assign o_write_data = muxB_Alu;


    assign data_b = (ALUSrc) ? i_addr_ext : muxB_Alu ;

    assign o_write_register = (RegDst) ? i_rd : i_rt;
    

    seg_execute_alu_control 
    #(
        .NB_ALUCTL (NB_ALUCTL),
        .NB_OP     (NB_ALUOP),
        .NB_FUNC   (NB_FUNC)
    )
    u_seg_execute_alu_control(
    	.i_funct  (funct),
        .i_ALUOp  (ALUOp),
        .o_ALUctl (ALUctl)
    );
    
    seg_execute_alu
    #(
        .LEN        (LEN),
        .NB_ALUCTL  (NB_ALUCTL)
    )
    u_seg_execute_alu(
    	.i_ALUctl (ALUctl),
        .i_data_a (muxA_Alu),
        .i_data_b (data_b),
        .o_ALUOut (o_ALU_result),
        .o_zero   (o_ALU_zero)
    );

endmodule
module seg_execute
    #( parameter    LEN             = 32,
       parameter    NB_ALUOP        = 4,
       parameter    NB_ALUCTL       = 4,
       parameter    NB_ADDR         = 5,
       parameter    NB_FUNC         = 6,
       parameter    NB_CTRL_WB      = 2,
       parameter    NB_CTRL_M       = 9,
       parameter    NB_CTRL_EX      = 6
    )
    (

        input wire                          i_clk,
        input wire                          i_rst,
        input wire [LEN - 1 : 0]            i_PC,
        input wire [LEN - 1 : 0]            i_read_data_1,
        input wire [LEN - 1 : 0]            i_read_data_2,
        input wire [LEN - 1 : 0]            i_addr_ext,
        input wire [NB_ADDR - 1 : 0]        i_rt,
        input wire [NB_ADDR - 1 : 0]        i_rd,
        input wire                          i_flush,

        input wire [NB_CTRL_WB - 1 : 0]     i_ctrl_wb_bus,
        input wire [NB_CTRL_M - 1 :  0]     i_ctrl_mem_bus,
        input wire [NB_CTRL_EX - 1 : 0]     i_ctrl_exc_bus,

        input wire [1:0]                    i_muxA_forwarding,
        input wire [1:0]                    i_muxB_forwarding, 
        input wire [LEN - 1 : 0]            i_rd_mem_forwarding,
        input wire [LEN - 1 : 0]            i_rd_wb_forwarding, 

        output wire [LEN - 1 : 0]           o_PC_branch,
        output wire [LEN - 1 : 0]           o_ALU_result,
        output wire [LEN - 1 : 0]           o_write_data,
        output wire [NB_ADDR - 1 : 0]       o_write_register,
        output wire                         o_ALU_zero,

        output wire [NB_CTRL_WB - 1 : 0]    o_ctrl_wb_bus,
        output wire [NB_CTRL_M - 1 : 0]     o_ctrl_mem_bus
    );



    wire        [NB_ALUOP - 1 : 0]  ALUOp;
    wire                            ALUSrc;

    reg         [LEN - 1 : 0]       reg_PC;

    wire        [LEN - 1 : 0]       data_b;
    wire        [NB_ALUCTL - 1 : 0] ALUctl;
    wire        [NB_FUNC - 1 : 0]   funct;


    wire        [LEN - 1 : 0]       muxA_Alu;
    wire        [LEN - 1 : 0]       muxB_Alu;
    
    assign funct            = i_addr_ext[NB_FUNC-1:0];

    assign ALUSrc           = i_ctrl_exc_bus[NB_ALUOP + 1];
    assign ALUOp            = i_ctrl_exc_bus[NB_ALUOP : 1];
    assign RegDst           = i_ctrl_exc_bus[0];

    assign o_PC_branch      = reg_PC;

    assign o_ctrl_wb_bus    = (i_flush) ? 0 : i_ctrl_wb_bus;
    assign o_ctrl_mem_bus   = (i_flush) ? 0 : i_ctrl_mem_bus;
    

    always @(posedge i_clk) begin
        if (!i_rst) begin
            reg_PC <= {LEN{1'b0}};
        end else begin
            reg_PC <= i_PC + i_addr_ext;
        end
    end


    assign muxA_Alu = (i_muxA_forwarding == 2'b00) ? i_read_data_1 :
                      (i_muxA_forwarding == 2'b01) ? i_rd_mem_forwarding :
                      (i_muxA_forwarding == 2'b10) ? i_rd_wb_forwarding :
                      i_read_data_1;


    assign muxB_Alu = (i_muxB_forwarding == 2'b00) ? i_read_data_2 :
                      (i_muxB_forwarding == 2'b01) ? i_rd_mem_forwarding :
                      (i_muxB_forwarding == 2'b10) ? i_rd_wb_forwarding :
                      i_read_data_2;

    assign o_write_data = muxB_Alu;


    assign data_b = (ALUSrc) ? i_addr_ext : muxB_Alu ;

    assign o_write_register = (RegDst) ? i_rd : i_rt;
    

    seg_execute_alu_control 
    #(
        .NB_ALUCTL (NB_ALUCTL),
        .NB_OP     (NB_ALUOP),
        .NB_FUNC   (NB_FUNC)
    )
    u_seg_execute_alu_control(
    	.i_funct  (funct),
        .i_ALUOp  (ALUOp),
        .o_ALUctl (ALUctl)
    );
    
    seg_execute_alu
    #(
        .LEN        (LEN),
        .NB_ALUCTL  (NB_ALUCTL)
    )
    u_seg_execute_alu(
    	.i_ALUctl (ALUctl),
        .i_data_a (muxA_Alu),
        .i_data_b (data_b),
        .o_ALUOut (o_ALU_result),
        .o_zero   (o_ALU_zero)
    );

endmodule