data/full_repos/permissive/178052224/Tarea8/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/178052224/Tarea8/testbench.v:11: Cannot find include file: contador_gray_cond.v\n`include "contador_gray_cond.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/178052224/Tarea8,data/full_repos/permissive/178052224/contador_gray_cond.v\n             data/full_repos/permissive/178052224/Tarea8,data/full_repos/permissive/178052224/contador_gray_cond.v.v\n             data/full_repos/permissive/178052224/Tarea8,data/full_repos/permissive/178052224/contador_gray_cond.v.sv\n             contador_gray_cond.v\n             contador_gray_cond.v.v\n             contador_gray_cond.v.sv\n             obj_dir/contador_gray_cond.v\n             obj_dir/contador_gray_cond.v.v\n             obj_dir/contador_gray_cond.v.sv\n%Error: data/full_repos/permissive/178052224/Tarea8/testbench.v:12: Cannot find include file: contador_gray_synth.v\n`include "contador_gray_synth.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea8/testbench.v:13: Cannot find include file: probador.v\n`include "probador.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea8/testbench.v:14: Cannot find include file: CMOS/cmos_cells.v\n`include "CMOS/cmos_cells.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module testbench();


	wire		clk;
	wire		enable;
	wire		reset_L;
	wire [4:0]	salida_gray_cond;
    wire [4:0]  salida_gray_estruct;


	

    contador_gray_cond contador_con(

				    .salida_gray	(salida_gray_cond[4:0]),

				    .clk		    (clk),
				    .enable		    (enable),
				    .reset_L		(reset_L));

	contador_gray_synth contador_est(

					 .salida_gray		(salida_gray_estruct[4:0]),

					 .clk			(clk),
					 .enable		(enable),
					 .reset_L		(reset_L));
	
    probador test0(

		   .clk			(clk),
		   .enable		(enable),
		   .reset_L		(reset_L),

		   .salida_gray_cond	(salida_gray_cond[4:0]),
		   .salida_gray_estruct	(salida_gray_estruct[4:0]));

endmodule
module testbench();



	wire		clk;
	wire		enable;
	wire		reset_L;
	wire [4:0]	salida_gray_cond;
    wire [4:0]  salida_gray_estruct;


	

    contador_gray_cond contador_con(

				    .salida_gray	(salida_gray_cond[4:0]),

				    .clk		    (clk),
				    .enable		    (enable),
				    .reset_L		(reset_L));

	contador_gray_synth contador_est(

					 .salida_gray		(salida_gray_estruct[4:0]),

					 .clk			(clk),
					 .enable		(enable),
					 .reset_L		(reset_L));
	
    probador test0(

		   .clk			(clk),
		   .enable		(enable),
		   .reset_L		(reset_L),

		   .salida_gray_cond	(salida_gray_cond[4:0]),
		   .salida_gray_estruct	(salida_gray_estruct[4:0]));

endmodule