data/full_repos/permissive/11584509/source/ltcminer.v
 line:101: before: "integer"
1: b'%Error: data/full_repos/permissive/11584509/source/ltcminer.v:49: Cannot find file containing module: \'main_pll\'\n  main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/11584509/source,data/full_repos/permissive/11584509/main_pll\n             data/full_repos/permissive/11584509/source,data/full_repos/permissive/11584509/main_pll.v\n             data/full_repos/permissive/11584509/source,data/full_repos/permissive/11584509/main_pll.sv\n             main_pll\n             main_pll.v\n             main_pll.sv\n             obj_dir/main_pll\n             obj_dir/main_pll.v\n             obj_dir/main_pll.sv\n%Warning-WIDTH: data/full_repos/permissive/11584509/source/ltcminer.v:70: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h7ff\' generates 31 bits.\n                                                                        : ... In instance ltcminer\n reg [31:0] target = 31\'h000007ff;  \n                     ^~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:85: Cannot find file containing module: \'hashcore\'\n   hashcore M (hash_clk, data1, data2, data3, target, nonce_core, nonce_out_i, golden_nonce_i[(i+1)*32-1:i*32], golden_nonce_match[i], loadnonce);\n   ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/source/ltcminer.v:131: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n                                                                         : ... In instance ltcminer\n   clear_nonces[port_counter] <= 1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/source/ltcminer.v:128: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n                                                                         : ... In instance ltcminer\n  if (new_nonces_flag[port_counter])\n                     ^\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:149: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:150: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:151: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:152: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:164: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/source/ltcminer.v:165: Cannot find file containing module: \'virtual_wire\'\n virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());\n ^~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 3 warning(s)\n'
module ltcminer (osc_clk);
`else
	module ltcminer (osc_clk, LEDS_out);
`endif
	
`ifdef SPEED_MHZ
	parameter SPEED_MHZ = `SPEED_MHZ;
`else
	parameter SPEED_MHZ = 25;
`endif


`ifdef LOCAL_MINERS
	parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
	parameter LOCAL_MINERS = 1;
`endif

	input osc_clk;
`ifndef NOLEDS
	output reg [7:0]LEDS_out;
`endif

	wire hash_clk;
	`ifndef SIM
		main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);
	`else
	 	assign hash_clk = osc_clk;
	`endif



`ifndef SIM

	reg [255:0] data1 = 256'd0;
	reg [255:0] data2 = 256'd0;
	reg [127:0] data3 = 128'd0;

`else

	reg [255:0] data1 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
	reg [255:0] data2 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
	reg [127:0] data3 = 128'h0000318f7e71441b141fe951b2b0c7df;

`endif
	
	reg [31:0] target = 31'h000007ff;

	wire [31:0]golden_nonce_out;
	wire [31:0] nonce_out;
	wire loadnonce = 1'b0;
	wire [LOCAL_MINERS*32-1:0] golden_nonce_i;
	wire [LOCAL_MINERS-1:0] golden_nonce_match;

	generate
		genvar i;
		for (i = 0; i < LOCAL_MINERS; i = i + 1)
		begin: for_local_miners
			wire [31:0] nonce_out_i;
			wire [3:0] nonce_core = i;
		
			hashcore M (hash_clk, data1, data2, data3, target, nonce_core, nonce_out_i, golden_nonce_i[(i+1)*32-1:i*32], golden_nonce_match[i], loadnonce);
			
			if (i==0)
				assign nonce_out = nonce_out_i;

		end
	endgenerate
	

	


	
	reg [LOCAL_MINERS-1:0]new_nonces_flag = 0;
   
	function integer clog2;
	input integer value;
	begin
		value = value-1;
		for (clog2=0; value>0; clog2=clog2+1)
		value = value>>1;
	end
	endfunction

	reg [clog2(LOCAL_MINERS)+1:0] port_counter = 0;
	reg [LOCAL_MINERS*32-1:0] nonces_shifted = 0;
	assign golden_nonce_out = nonces_shifted[31:0];


	reg [LOCAL_MINERS-1:0] clear_nonces = 0;

	always @(posedge hash_clk)
	begin

		new_nonces_flag <= (new_nonces_flag & ~clear_nonces) | golden_nonce_match;

		if (port_counter == LOCAL_MINERS-1)
			port_counter <= 0;
		else
			port_counter <= port_counter + 1'd1;
		


		if (new_nonces_flag[port_counter])
		begin
			nonces_shifted <= golden_nonce_i >> port_counter*32;
			clear_nonces[port_counter] <= 1;
		end
		else 
		begin
			clear_nonces <= 0;
		end
	end
	
	`ifndef SIM


	wire [255:0] data1_vw;
	wire [255:0] data2_vw;
	wire [127:0] data3_vw;


	wire [31:0] target_vw;

	virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));
	virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));
	virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));
	virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));

	always @ (posedge hash_clk)
	begin
		data1 <= data1_vw;
		data2 <= data2_vw;
		data3 <= data3_vw;
		target <= target_vw;
	end


	
	virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());
	virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());

	`endif
	

`ifndef NOLEDS

	always @(posedge hash_clk) begin
	`ifdef INVERTLEDS
		LEDS_out <= ~nonce_out[15:8];
	`else
		LEDS_out <= nonce_out[15:8];
	`endif
	end
`endif

endmodule
module ltcminer (osc_clk);

`else
	module ltcminer (osc_clk, LEDS_out);
`endif
	
`ifdef SPEED_MHZ
	parameter SPEED_MHZ = `SPEED_MHZ;
`else
	parameter SPEED_MHZ = 25;
`endif


`ifdef LOCAL_MINERS
	parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
	parameter LOCAL_MINERS = 1;
`endif

	input osc_clk;
`ifndef NOLEDS
	output reg [7:0]LEDS_out;
`endif

	wire hash_clk;
	`ifndef SIM
		main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);
	`else
	 	assign hash_clk = osc_clk;
	`endif



`ifndef SIM

	reg [255:0] data1 = 256'd0;
	reg [255:0] data2 = 256'd0;
	reg [127:0] data3 = 128'd0;

`else

	reg [255:0] data1 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
	reg [255:0] data2 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
	reg [127:0] data3 = 128'h0000318f7e71441b141fe951b2b0c7df;

`endif
	
	reg [31:0] target = 31'h000007ff;

	wire [31:0]golden_nonce_out;
	wire [31:0] nonce_out;
	wire loadnonce = 1'b0;
	wire [LOCAL_MINERS*32-1:0] golden_nonce_i;
	wire [LOCAL_MINERS-1:0] golden_nonce_match;

	generate
		genvar i;
		for (i = 0; i < LOCAL_MINERS; i = i + 1)
		begin: for_local_miners
			wire [31:0] nonce_out_i;
			wire [3:0] nonce_core = i;
		
			hashcore M (hash_clk, data1, data2, data3, target, nonce_core, nonce_out_i, golden_nonce_i[(i+1)*32-1:i*32], golden_nonce_match[i], loadnonce);
			
			if (i==0)
				assign nonce_out = nonce_out_i;

		end
	endgenerate
	

	


	
	reg [LOCAL_MINERS-1:0]new_nonces_flag = 0;
   
	function integer clog2;
	input integer value;
	begin
		value = value-1;
		for (clog2=0; value>0; clog2=clog2+1)
		value = value>>1;
	end
	endfunction

	reg [clog2(LOCAL_MINERS)+1:0] port_counter = 0;
	reg [LOCAL_MINERS*32-1:0] nonces_shifted = 0;
	assign golden_nonce_out = nonces_shifted[31:0];


	reg [LOCAL_MINERS-1:0] clear_nonces = 0;

	always @(posedge hash_clk)
	begin

		new_nonces_flag <= (new_nonces_flag & ~clear_nonces) | golden_nonce_match;

		if (port_counter == LOCAL_MINERS-1)
			port_counter <= 0;
		else
			port_counter <= port_counter + 1'd1;
		


		if (new_nonces_flag[port_counter])
		begin
			nonces_shifted <= golden_nonce_i >> port_counter*32;
			clear_nonces[port_counter] <= 1;
		end
		else 
		begin
			clear_nonces <= 0;
		end
	end
	
	`ifndef SIM


	wire [255:0] data1_vw;
	wire [255:0] data2_vw;
	wire [127:0] data3_vw;


	wire [31:0] target_vw;

	virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));
	virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));
	virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));
	virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));

	always @ (posedge hash_clk)
	begin
		data1 <= data1_vw;
		data2 <= data2_vw;
		data3 <= data3_vw;
		target <= target_vw;
	end


	
	virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());
	virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());

	`endif
	

`ifndef NOLEDS

	always @(posedge hash_clk) begin
	`ifdef INVERTLEDS
		LEDS_out <= ~nonce_out[15:8];
	`else
		LEDS_out <= nonce_out[15:8];
	`endif
	end
`endif

endmodule