data/full_repos/permissive/123304708/src/control/ctrl.v
None: at end of input
1: b'%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:1: Cannot find include file: ././define/ctrl_def.v\n`include "././define/ctrl_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123304708/src/control,data/full_repos/permissive/123304708/././define/ctrl_def.v\n             data/full_repos/permissive/123304708/src/control,data/full_repos/permissive/123304708/././define/ctrl_def.v.v\n             data/full_repos/permissive/123304708/src/control,data/full_repos/permissive/123304708/././define/ctrl_def.v.sv\n             ././define/ctrl_def.v\n             ././define/ctrl_def.v.v\n             ././define/ctrl_def.v.sv\n             obj_dir/././define/ctrl_def.v\n             obj_dir/././define/ctrl_def.v.v\n             obj_dir/././define/ctrl_def.v.sv\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:2: Cannot find include file: ././define/instr_def.v\n`include "././define/instr_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:28: Define or directive not defined: \'`ALUOP_ADD\'\n    ALUOp = `ALUOP_ADD;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:28: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    ALUOp = `ALUOP_ADD;\n                      ^\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:31: Define or directive not defined: \'`EXTOP_ZERO\'\n    EXTOp = `EXTOP_ZERO;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:31: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    EXTOp = `EXTOP_ZERO;\n                       ^\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:43: Define or directive not defined: \'`OP_RTYPE\'\n      `OP_RTYPE:\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:43: syntax error, unexpected \':\', expecting endcase\n      `OP_RTYPE:\n               ^\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:46: Define or directive not defined: \'`FUNCT_ADD\'\n          `FUNCT_ADD,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:47: Define or directive not defined: \'`FUNCT_ADDU\'\n          `FUNCT_ADDU:\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:50: Define or directive not defined: \'`ALUOP_ADD\'\n            ALUOp = `ALUOP_ADD;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:50: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            ALUOp = `ALUOP_ADD;\n                              ^\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:53: Define or directive not defined: \'`EXTOP_ZERO\'\n            EXTOp = `EXTOP_ZERO;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            EXTOp = `EXTOP_ZERO;\n                               ^\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:61: Define or directive not defined: \'`FUNCT_SUB\'\n          `FUNCT_SUB,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:61: syntax error, unexpected \',\'\n          `FUNCT_SUB,\n                    ^\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:62: Define or directive not defined: \'`FUNCT_SUBU\'\n          `FUNCT_SUBU:\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:65: Define or directive not defined: \'`ALUOP_SUB\'\n            ALUOp = `ALUOP_SUB;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:68: Define or directive not defined: \'`EXTOP_ZERO\'\n            EXTOp = `EXTOP_ZERO;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:76: Define or directive not defined: \'`FUNCT_AND\'\n          `FUNCT_AND:\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:79: Define or directive not defined: \'`ALUOP_AND\'\n            ALUOp = `ALUOP_AND;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:82: Define or directive not defined: \'`EXTOP_ZERO\'\n            EXTOp = `EXTOP_ZERO;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:90: Define or directive not defined: \'`FUNCT_OR\'\n          `FUNCT_OR:\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:93: Define or directive not defined: \'`ALUOP_OR\'\n            ALUOp = `ALUOP_OR;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:96: Define or directive not defined: \'`EXTOP_ZERO\'\n            EXTOp = `EXTOP_ZERO;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:104: Define or directive not defined: \'`FUNCT_XOR\'\n          `FUNCT_XOR:\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:107: Define or directive not defined: \'`ALUOP_XOR\'\n            ALUOp = `ALUOP_XOR;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:110: Define or directive not defined: \'`EXTOP_ZERO\'\n            EXTOp = `EXTOP_ZERO;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:118: Define or directive not defined: \'`FUNCT_NOR\'\n          `FUNCT_NOR:\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:121: Define or directive not defined: \'`ALUOP_NOR\'\n            ALUOp = `ALUOP_NOR;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:124: Define or directive not defined: \'`EXTOP_ZERO\'\n            EXTOp = `EXTOP_ZERO;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:132: Define or directive not defined: \'`FUNCT_SLT\'\n          `FUNCT_SLT:\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:135: Define or directive not defined: \'`ALUOP_SLT\'\n            ALUOp = `ALUOP_SLT;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:138: Define or directive not defined: \'`EXTOP_ZERO\'\n            EXTOp = `EXTOP_ZERO;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:146: Define or directive not defined: \'`FUNCT_SLTU\'\n          `FUNCT_SLTU:\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:149: Define or directive not defined: \'`ALUOP_SLTU\'\n            ALUOp = `ALUOP_SLTU;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:152: Define or directive not defined: \'`EXTOP_ZERO\'\n            EXTOp = `EXTOP_ZERO;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:160: Define or directive not defined: \'`FUNCT_SLL\'\n          `FUNCT_SLL:\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:163: Define or directive not defined: \'`ALUOP_SLL\'\n            ALUOp = `ALUOP_SLL;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:166: Define or directive not defined: \'`EXTOP_ZERO\'\n            EXTOp = `EXTOP_ZERO;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:174: Define or directive not defined: \'`FUNCT_SLLV\'\n          `FUNCT_SLLV:\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:177: Define or directive not defined: \'`ALUOP_SLL\'\n            ALUOp = `ALUOP_SLL;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:180: Define or directive not defined: \'`EXTOP_ZERO\'\n            EXTOp = `EXTOP_ZERO;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:188: Define or directive not defined: \'`FUNCT_SRA\'\n          `FUNCT_SRA:\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:191: Define or directive not defined: \'`ALUOP_SRA\'\n            ALUOp = `ALUOP_SRA;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:194: Define or directive not defined: \'`EXTOP_ZERO\'\n            EXTOp = `EXTOP_ZERO;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:202: Define or directive not defined: \'`FUNCT_SRAV\'\n          `FUNCT_SRAV:\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:205: Define or directive not defined: \'`ALUOP_SRA\'\n            ALUOp = `ALUOP_SRA;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:208: Define or directive not defined: \'`EXTOP_ZERO\'\n            EXTOp = `EXTOP_ZERO;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/control/ctrl.v:216: Define or directive not defined: \'`FUNCT_SRL\'\n          `FUNCT_SRL:\n          ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ctrl(
  input [31:0] instr,

  output reg[1:0] RegDst,
  output reg[4:0] ALUOp,
  output reg[1:0] ALUSrcA,
  output reg[1:0] ALUSrcB,
  output reg[1:0] EXTOp,
  output reg MemRead,
  output reg MemWrite,
  output reg RegWrite,
  output reg[1:0] MemtoReg,
  output reg[1:0] Jump
  );
  
  wire[5:0] OP;
  wire[5:0] Funct;
  
  assign OP = instr[31:26];
  assign Funct = instr[5:0];  
  
  initial
  begin
    RegDst = 2'b00;
    ALUOp = `ALUOP_ADD;
    ALUSrcA = 2'b00;
    ALUSrcB = 2'b00;
    EXTOp = `EXTOP_ZERO;
    MemRead = 0;
    MemWrite = 0;
    RegWrite = 0;
    MemtoReg = 2'b00;
    Jump = 2'b00;
  end
  

  always@(*) 
  begin
    case(OP)
      `OP_RTYPE:
      begin
        case(Funct)
          `FUNCT_ADD,
          `FUNCT_ADDU:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_ADD;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
          
          `FUNCT_SUB,
          `FUNCT_SUBU:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SUB;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_AND:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_AND;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_OR:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_OR;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_XOR:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_XOR;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_NOR:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_NOR;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_SLT:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SLT;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_SLTU:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SLTU;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_SLL:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SLL;
            ALUSrcA = 2'b01;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
          
          `FUNCT_SLLV:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SLL;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_SRA:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SRA;
            ALUSrcA = 2'b01;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
          
          `FUNCT_SRAV:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SRA;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_SRL:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SRL;
            ALUSrcA = 2'b01;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
          
          `FUNCT_SRLV:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SRL;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
              
          `FUNCT_JALR:
          begin 
            RegDst = 2'b10;
            ALUOp = `ALUOP_ADD;
            ALUSrcA = 2'b10;
            ALUSrcB = 2'b10;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b10;
          end
          
          `FUNCT_JR:
          begin 
            RegDst = 2'b00;
            ALUOp = `ALUOP_ADD;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 0;
            MemtoReg = 2'b00;
            Jump = 2'b10;
          end
        endcase
      end
              
      `OP_ADDI:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_ADDIU:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_SIGN;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
      
      `OP_ANDI:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_AND;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_ORI:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_OR;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_XORI:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_XOR;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_LUI:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_LUI;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_SLTI:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_SLT;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_SLTIU:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_SLTU;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
    
      `OP_LB,
      `OP_LBU,
      `OP_LH,
      `OP_LHU,
      `OP_LW:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 1;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b01;
        Jump = 2'b00; 
      end
      
      `OP_SB,
      `OP_SH,
      `OP_SW:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 1;
        RegWrite = 0;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_BEQ,
      `OP_BNE,
      `OP_BLEZ,
      `OP_BGTZ,
      `OP_BLTZ,
      `OP_BGEZ: 
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b00;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 0;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
      
      `OP_J:
      begin 
        RegDst = 2'b00;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b00;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 0;
        MemtoReg = 2'b00;
        Jump = 2'b01;
      end
      
      `OP_JAL:
      begin 
        RegDst = 2'b10;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b10;
        ALUSrcB = 2'b10;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b01;
      end
    endcase
  end 
     
endmodule
module ctrl(
  input [31:0] instr,

  output reg[1:0] RegDst,
  output reg[4:0] ALUOp,
  output reg[1:0] ALUSrcA,
  output reg[1:0] ALUSrcB,
  output reg[1:0] EXTOp,
  output reg MemRead,
  output reg MemWrite,
  output reg RegWrite,
  output reg[1:0] MemtoReg,
  output reg[1:0] Jump
  );

  
  wire[5:0] OP;
  wire[5:0] Funct;
  
  assign OP = instr[31:26];
  assign Funct = instr[5:0];  
  
  initial
  begin
    RegDst = 2'b00;
    ALUOp = `ALUOP_ADD;
    ALUSrcA = 2'b00;
    ALUSrcB = 2'b00;
    EXTOp = `EXTOP_ZERO;
    MemRead = 0;
    MemWrite = 0;
    RegWrite = 0;
    MemtoReg = 2'b00;
    Jump = 2'b00;
  end
  

  always@(*) 
  begin
    case(OP)
      `OP_RTYPE:
      begin
        case(Funct)
          `FUNCT_ADD,
          `FUNCT_ADDU:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_ADD;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
          
          `FUNCT_SUB,
          `FUNCT_SUBU:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SUB;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_AND:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_AND;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_OR:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_OR;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_XOR:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_XOR;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_NOR:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_NOR;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_SLT:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SLT;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_SLTU:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SLTU;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_SLL:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SLL;
            ALUSrcA = 2'b01;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
          
          `FUNCT_SLLV:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SLL;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_SRA:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SRA;
            ALUSrcA = 2'b01;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
          
          `FUNCT_SRAV:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SRA;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
            
          `FUNCT_SRL:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SRL;
            ALUSrcA = 2'b01;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
          
          `FUNCT_SRLV:
          begin 
            RegDst = 2'b01;
            ALUOp = `ALUOP_SRL;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b00;
          end
              
          `FUNCT_JALR:
          begin 
            RegDst = 2'b10;
            ALUOp = `ALUOP_ADD;
            ALUSrcA = 2'b10;
            ALUSrcB = 2'b10;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 1;
            MemtoReg = 2'b00;
            Jump = 2'b10;
          end
          
          `FUNCT_JR:
          begin 
            RegDst = 2'b00;
            ALUOp = `ALUOP_ADD;
            ALUSrcA = 2'b00;
            ALUSrcB = 2'b00;
            EXTOp = `EXTOP_ZERO;
            MemRead = 0;
            MemWrite = 0;
            RegWrite = 0;
            MemtoReg = 2'b00;
            Jump = 2'b10;
          end
        endcase
      end
              
      `OP_ADDI:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_ADDIU:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_SIGN;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
      
      `OP_ANDI:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_AND;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_ORI:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_OR;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_XORI:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_XOR;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_LUI:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_LUI;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_SLTI:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_SLT;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_SLTIU:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_SLTU;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
    
      `OP_LB,
      `OP_LBU,
      `OP_LH,
      `OP_LHU,
      `OP_LW:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 1;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b01;
        Jump = 2'b00; 
      end
      
      `OP_SB,
      `OP_SH,
      `OP_SW:
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b01;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 1;
        RegWrite = 0;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
        
      `OP_BEQ,
      `OP_BNE,
      `OP_BLEZ,
      `OP_BGTZ,
      `OP_BLTZ,
      `OP_BGEZ: 
      begin
        RegDst = 2'b00;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b00;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 0;
        MemtoReg = 2'b00;
        Jump = 2'b00;
      end
      
      `OP_J:
      begin 
        RegDst = 2'b00;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b00;
        ALUSrcB = 2'b00;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 0;
        MemtoReg = 2'b00;
        Jump = 2'b01;
      end
      
      `OP_JAL:
      begin 
        RegDst = 2'b10;
        ALUOp = `ALUOP_ADD;
        ALUSrcA = 2'b10;
        ALUSrcB = 2'b10;
        EXTOp = `EXTOP_ZERO;
        MemRead = 0;
        MemWrite = 0;
        RegWrite = 1;
        MemtoReg = 2'b00;
        Jump = 2'b01;
      end
    endcase
  end 
     
endmodule