data/full_repos/permissive/143278/ivltests/time5.v
 line:31: before: ";"
1: b'%Error: data/full_repos/permissive/143278/ivltests/time5.v:35: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      $display($time,, "set out1 == 1");\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/time5.v:34: Unsupported: Ignoring delay on this delayed statement.\n   always @(posedge clk) #2.4 begin\n                         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/time5.v:41: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      $display($time,, "set out2 == 1");\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/time5.v:40: Unsupported: Ignoring delay on this delayed statement.\n   always @(posedge clk) #2.6 begin\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/time5.v:53: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (out1 !== 0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/time5.v:60: Unsupported: Ignoring delay on this delayed statement.\n      #3 if (out1 !== 1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/time5.v:70: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (time2 != 4) begin\n      ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n'
module main;

   reg clk;
   reg out1, out2;
   time time1;
   time time2;

   always @(posedge clk) #2.4 begin
      $display($time,, "set out1 == 1");
      time1 = $time;
      out1 = 1;
   end

   always @(posedge clk) #2.6 begin
      $display($time,, "set out2 == 1");
      time2 = $time;
      out2 = 1;
   end

   initial begin
      clk = 0;
      out1 = 0;
      out2 = 0;
      time1 = 0;
      time2 = 0;

      #1 if (out1 !== 0) begin
	 $display("FAILED -- out1 is not 0: %b", out1);
	 $finish;
      end

      clk = 1;

      #3 if (out1 !== 1) begin
	 $display("FAILED -- out is not 1 at time 3: %b", out1);
	 $finish;
      end

      if (time1 != 3) begin
	 $display("FAILED -- time1 = %d", time1);
	 $finish;
      end

      #1 if (time2 != 4) begin
	 $display("FAILED -- time2 = %d", time2);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg clk;
   reg out1, out2;
   time time1;
   time time2;

   always @(posedge clk) #2.4 begin
      $display($time,, "set out1 == 1");
      time1 = $time;
      out1 = 1;
   end

   always @(posedge clk) #2.6 begin
      $display($time,, "set out2 == 1");
      time2 = $time;
      out2 = 1;
   end

   initial begin
      clk = 0;
      out1 = 0;
      out2 = 0;
      time1 = 0;
      time2 = 0;

      #1 if (out1 !== 0) begin
	 $display("FAILED -- out1 is not 0: %b", out1);
	 $finish;
      end

      clk = 1;

      #3 if (out1 !== 1) begin
	 $display("FAILED -- out is not 1 at time 3: %b", out1);
	 $finish;
      end

      if (time1 != 3) begin
	 $display("FAILED -- time1 = %d", time1);
	 $finish;
      end

      #1 if (time2 != 4) begin
	 $display("FAILED -- time2 = %d", time2);
	 $finish;
      end

      $display("PASSED");
   end

endmodule