data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n always  #25 clock=~clock;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #40 TB = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #60 reset = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #38 TA = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #206 TB = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #302 TA = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #40 TB = 1\'b1;\n  ^\n%Error: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:17: Cannot find file containing module: \'semaforo_FSM\'\n semaforo_FSM DUT(\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new,data/full_repos/permissive/104660645/semaforo_FSM\n             data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new,data/full_repos/permissive/104660645/semaforo_FSM.v\n             data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new,data/full_repos/permissive/104660645/semaforo_FSM.sv\n             semaforo_FSM\n             semaforo_FSM.v\n             semaforo_FSM.sv\n             obj_dir/semaforo_FSM\n             obj_dir/semaforo_FSM.v\n             obj_dir/semaforo_FSM.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
  

	reg clock;
	reg reset;
	reg TA, TB;
	


	wire [1:0] LA, LB;
	

	semaforo_FSM DUT(
        .clock (clock),
        .reset (reset),
        .TA (TA),
        .TB (TB),
        .LA (LA),
        .LB (LB)
        );
            

	always  #25 clock=~clock;
	

	initial begin
		clock = 1'b0;
		reset = 1'b0;
		TA = 1'b1;
		TB = 1'b0;
		#40 TB = 1'b1;
		#60 reset = 1'b1;
		#10 reset = 1'b0;
		
		
		#38 TA = 1'b0;
		    
		
		#206 TB = 1'b0;
		#302 TA = 1'b1;
		#40 TB = 1'b1;
	end

endmodule
module testbench();

  

	reg clock;
	reg reset;
	reg TA, TB;
	


	wire [1:0] LA, LB;
	

	semaforo_FSM DUT(
        .clock (clock),
        .reset (reset),
        .TA (TA),
        .TB (TB),
        .LA (LA),
        .LB (LB)
        );
            

	always  #25 clock=~clock;
	

	initial begin
		clock = 1'b0;
		reset = 1'b0;
		TA = 1'b1;
		TB = 1'b0;
		#40 TB = 1'b1;
		#60 reset = 1'b1;
		#10 reset = 1'b0;
		
		
		#38 TA = 1'b0;
		    
		
		#206 TB = 1'b0;
		#302 TA = 1'b1;
		#40 TB = 1'b1;
	end

endmodule