data/full_repos/permissive/201488448/2_circuits/2_sequential/02_dff8.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/8240abfa-f5c5-4ef3-bdf9-810a70c3e1d5.xml
module top_module(
	input clk,
	input [7:0] d,
	output reg [7:0] q);
	

	always @(posedge clk)
		q <= d;
	
endmodule
module top_module(
	input clk,
	input [7:0] d,
	output reg [7:0] q);

	

	always @(posedge clk)
		q <= d;
	
endmodule