data/full_repos/permissive/212897440/effects_tb.v
 line:30: before: ","
1: b'%Error: data/full_repos/permissive/212897440/effects_tb.v:10: Cannot find include file: clipping.v\n`include "clipping.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/clipping.v\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/clipping.v.v\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/clipping.v.sv\n             clipping.v\n             clipping.v.v\n             clipping.v.sv\n             obj_dir/clipping.v\n             obj_dir/clipping.v.v\n             obj_dir/clipping.v.sv\n%Error: data/full_repos/permissive/212897440/effects_tb.v:11: Cannot find include file: no_effect.v\n`include "no_effect.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/212897440/effects_tb.v:14: Cannot find include file: effect_module.v\n`include "effect_module.v"     \n         ^~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #030; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #005;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #005;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #002;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #005;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #002;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #005;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #002;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/212897440/effects_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #030_000; \n    ^\n%Error: data/full_repos/permissive/212897440/effects_tb.v:91: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("wave.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/212897440/effects_tb.v:92: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0);\n    ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 13 warning(s)\n'
module effect_tb#( parameter
    data_width = 16
)();

reg clk = 1'b0;
reg signed [data_width-1 : 0]  i_data = 'b0; 
reg i_read_done = 0;
reg i_data_ready = 0;
reg [1 : 0]  sw = 2'b01; 



always #0.5 clk <= ~clk;


effect_module #(
    .d_width(data_width)
) effect_module (
    .clk(clk),
    .reset(1'b0),
    .sw(sw),
    .i_treshhold(14'h0ff),
    .i_data_ready(i_data_ready),
    .i_read_done(i_read_done),
    .i_data(i_data),
    .o_read_enable(),
    .o_data_valid(),
    .o_data_sw0(),
    .o_data_sw1()

);

initial begin
    #030; 
    i_data  = 'haaa;
    #005;
    i_data_ready = 1;
    #005;
    i_data  = 'h0fa;
    i_data_ready = 0;
    #002;
    i_read_done = 1;
    #001;
    i_read_done = 0;
    #005;
    i_data  =  -16'd3000;
    #002;
    i_read_done = 1;
    #001;
    i_read_done = 0;
    #005;
    i_data  =  852;
    #002;
    i_read_done = 1;
    #001;
    i_read_done = 0;
end


initial begin
    #030_000; 
    $display("*");

    $display(" ");
    $display("Use this command to open timing diagram:");
    $display("gtkwave -f wave.vcd");
    $display("----------------------------------------------");
    $finish();
end

initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
end

endmodule
module effect_tb#( parameter
    data_width = 16
)();


reg clk = 1'b0;
reg signed [data_width-1 : 0]  i_data = 'b0; 
reg i_read_done = 0;
reg i_data_ready = 0;
reg [1 : 0]  sw = 2'b01; 



always #0.5 clk <= ~clk;


effect_module #(
    .d_width(data_width)
) effect_module (
    .clk(clk),
    .reset(1'b0),
    .sw(sw),
    .i_treshhold(14'h0ff),
    .i_data_ready(i_data_ready),
    .i_read_done(i_read_done),
    .i_data(i_data),
    .o_read_enable(),
    .o_data_valid(),
    .o_data_sw0(),
    .o_data_sw1()

);

initial begin
    #030; 
    i_data  = 'haaa;
    #005;
    i_data_ready = 1;
    #005;
    i_data  = 'h0fa;
    i_data_ready = 0;
    #002;
    i_read_done = 1;
    #001;
    i_read_done = 0;
    #005;
    i_data  =  -16'd3000;
    #002;
    i_read_done = 1;
    #001;
    i_read_done = 0;
    #005;
    i_data  =  852;
    #002;
    i_read_done = 1;
    #001;
    i_read_done = 0;
end


initial begin
    #030_000; 
    $display("*");

    $display(" ");
    $display("Use this command to open timing diagram:");
    $display("gtkwave -f wave.vcd");
    $display("----------------------------------------------");
    $finish();
end

initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
end

endmodule