data/full_repos/permissive/106596430/displayTest.v
1: b"%Error: data/full_repos/permissive/106596430/displayTest.v:28: Cannot find file containing module: 'clockReset'\n    clockReset  clkGen  (\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/clockReset\n             data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/clockReset.v\n             data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/clockReset.sv\n             clockReset\n             clockReset.v\n             clockReset.sv\n             obj_dir/clockReset\n             obj_dir/clockReset.v\n             obj_dir/clockReset.sv\n%Error: data/full_repos/permissive/106596430/displayTest.v:57: Cannot find file containing module: 'DisplayInterface'\n   DisplayInterface disp1 (\n   ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module displayTest(
        input clk100,
        input rstPBn,
        input [3:0] point,
        output [7:0] digit,
        output [7:0] segment
        );



    wire clk5;
    wire reset;
    wire [15:0] dispVal;



    clockReset  clkGen  (
            .clk100 (clk100),
            .rstPBn (rstPBn),
            .clk5   (clk5),
            .reset  (reset) );





   reg [28:0] testCount;
   always @ (posedge clk5)
      begin
         if (reset) testCount <= 29'b0;
         else testCount <= testCount + 1'b1;
      end





   assign dispVal[15:12] = testCount[28:25];
   assign dispVal[11:8]  = testCount[27:24];
   assign dispVal[7:4]   = testCount[26:23];
   assign dispVal[3:0]   = testCount[25:22];




   DisplayInterface disp1 (
				.clk5(clk5),
				.reset(reset),
            .point(point),
				.dispVal(dispVal),
				.digit(digit),
				.segment(segment));

endmodule
module displayTest(
        input clk100,
        input rstPBn,
        input [3:0] point,
        output [7:0] digit,
        output [7:0] segment
        );




    wire clk5;
    wire reset;
    wire [15:0] dispVal;



    clockReset  clkGen  (
            .clk100 (clk100),
            .rstPBn (rstPBn),
            .clk5   (clk5),
            .reset  (reset) );





   reg [28:0] testCount;
   always @ (posedge clk5)
      begin
         if (reset) testCount <= 29'b0;
         else testCount <= testCount + 1'b1;
      end





   assign dispVal[15:12] = testCount[28:25];
   assign dispVal[11:8]  = testCount[27:24];
   assign dispVal[7:4]   = testCount[26:23];
   assign dispVal[3:0]   = testCount[25:22];




   DisplayInterface disp1 (
				.clk5(clk5),
				.reset(reset),
            .point(point),
				.dispVal(dispVal),
				.digit(digit),
				.segment(segment));

endmodule