data/full_repos/permissive/101862289/btn2_pergesmentesito.v
None: at end of input
data/verilator_xmls/d26d6163-ae96-4895-831b-bb58e958e9e7.xml
module btn2_pergesmentesito(

   input btn,
	 input clk,
	 input en,
    output btn2_en
    );

	 wire rst = ~btn;
	 wire engedelyezes;
	 reg[15:0] Q;


	assign btn2_en=(Q==4);
	 assign engedelyezes=((btn^btn2_en)&en);


	 always@(posedge clk)
	 begin
		if(rst) Q<=16'b0;
		else if(engedelyezes) Q<=Q+1;
	 end

endmodule
module btn2_pergesmentesito(

   input btn,
	 input clk,
	 input en,
    output btn2_en
    );


	 wire rst = ~btn;
	 wire engedelyezes;
	 reg[15:0] Q;


	assign btn2_en=(Q==4);
	 assign engedelyezes=((btn^btn2_en)&en);


	 always@(posedge clk)
	 begin
		if(rst) Q<=16'b0;
		else if(engedelyezes) Q<=Q+1;
	 end

endmodule