data/full_repos/permissive/111393021/CLA.v
1: b"%Error: data/full_repos/permissive/111393021/CLA.v:17: Input/output/inout declaration not found for port: 'clk_ram'\nmodule CLA(clk_ram, clk_core, ram_iobus);\n           ^~~~~~~\n%Error: data/full_repos/permissive/111393021/CLA.v:17: Input/output/inout declaration not found for port: 'clk_core'\nmodule CLA(clk_ram, clk_core, ram_iobus);\n                    ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module CLA(clk_ram, clk_core, ram_iobus);
	input [31:0] ram_iobus;

endmodule
module CLA(clk_ram, clk_core, ram_iobus);

	input [31:0] ram_iobus;

endmodule