data/full_repos/permissive/15761418/src/register24.v
data/verilator_xmls/dcaf4437-6a7d-4bd6-96ac-9d4142f635b0.xml
module register24(
	input wire clk,
	input wire[23:0] data_in,
	output reg[23:0] data_out);
	always @(posedge clk)
		data_out <= data_in;
endmodule
module register24(
	input wire clk,
	input wire[23:0] data_in,
	output reg[23:0] data_out);

	always @(posedge clk)
		data_out <= data_in;
endmodule