data/full_repos/permissive/159555381/mory.v
 line:73: before: "$"
1: b'%Error: data/full_repos/permissive/159555381/mory.v:49: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("Moor.vcd"); \n   ^~~~~~~~~\n%Error: data/full_repos/permissive/159555381/mory.v:50: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0,TB);\n   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:53: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = 1\'b0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #12 reset=1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #8 x=1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10 x=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/mory.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Moore(x, clk, reset, y);
 	input x, clk, reset;
	output reg y;
	parameter A = 0, B = 1, C = 2, D = 3, E = 4;
	reg [2:0] ps, ns;
	always@(posedge clk, posedge reset)
		begin
			if(reset)
				ps <= A;
			else
			ps <= ns;
		end
	always@(ps, x)
		begin
			case(ps)
				A: ns = x ? B : A;
				B: ns = x ? B : C;
				C: ns = x ? D : A;
				D: ns = x ? B : E;
				E: ns = x ? D : A;
			default: ps = A;
		endcase
	end
	always@(ps)
		begin
		case(ps)
			A: y = 0;
			B: y = 0;
			C: y = 0;
			D: y = 0;
			E: y = 1;
		endcase
	end
endmodule
module Moore(x, clk, reset, y);

 	input x, clk, reset;
	output reg y;
	parameter A = 0, B = 1, C = 2, D = 3, E = 4;
	reg [2:0] ps, ns;
	always@(posedge clk, posedge reset)
		begin
			if(reset)
				ps <= A;
			else
			ps <= ns;
		end
	always@(ps, x)
		begin
			case(ps)
				A: ns = x ? B : A;
				B: ns = x ? B : C;
				C: ns = x ? D : A;
				D: ns = x ? B : E;
				E: ns = x ? D : A;
			default: ps = A;
		endcase
	end
	always@(ps)
		begin
		case(ps)
			A: y = 0;
			B: y = 0;
			C: y = 0;
			D: y = 0;
			E: y = 1;
		endcase
	end
endmodule