data/full_repos/permissive/109394014/examples/GameTable.v
1: b'%Warning-WIDTH: data/full_repos/permissive/109394014/examples/GameTable.v:47: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'TABFILE\' generates 96 bits.\n                                                                            : ... In instance GameTable\n   if (TABFILE) $readmemh(TABFILE, mem);\n   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module GameTable (clk, din, write_en, waddr, raddr, dout);
	parameter rows = 30;
	parameter cols = 40;
	parameter addr_width = 11;
	parameter nsprites = 4;
	input [addr_width-1:0] waddr, raddr;
	input [nsprites-1:0] din;
	input write_en, clk;
	output reg [nsprites-1:0] dout;
	reg [nsprites-1:0] mem [(rows*cols)-1:0];
	
	parameter TABFILE="inittab.list";

	initial begin
	  if (TABFILE) $readmemh(TABFILE, mem);
	end

	always @(posedge clk)
	begin
	if (write_en)
		mem[waddr] <= din;
	end
	
	always @(posedge clk)
	begin
		dout <= mem[raddr];
	end
endmodule
module GameTable (clk, din, write_en, waddr, raddr, dout);

	parameter rows = 30;
	parameter cols = 40;
	parameter addr_width = 11;
	parameter nsprites = 4;
	input [addr_width-1:0] waddr, raddr;
	input [nsprites-1:0] din;
	input write_en, clk;
	output reg [nsprites-1:0] dout;
	reg [nsprites-1:0] mem [(rows*cols)-1:0];
	
	parameter TABFILE="inittab.list";

	initial begin
	  if (TABFILE) $readmemh(TABFILE, mem);
	end

	always @(posedge clk)
	begin
	if (write_en)
		mem[waddr] <= din;
	end
	
	always @(posedge clk)
	begin
		dout <= mem[raddr];
	end
endmodule