data/full_repos/permissive/143278/ivltests/pr142.v
 line:51: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr142.v:28: Unsupported: Ignoring delay on this delayed statement.\n         # 50 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr142.v:39: syntax error, unexpected \'@\'\n            @ (posedge clk);\n            ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testit;

   reg clk;
   reg [2:0] cnt;

   always
      begin
         # 50 clk = ~clk;
      end

   task idle;
      input [15:0] waitcnt;

   begin: idletask

      integer i;
      for (i=0; i < waitcnt; i = i + 1)
         begin
            @ (posedge clk);

         end

   end
   endtask

   initial begin
       clk = 0;
       cnt = 0;
       $display ("One");
       cnt = cnt + 1;
       idle(3);
       cnt = cnt + 1;
       $display ("Two");
       if(cnt === 2)
         $display("PASSED");
       else
         $display("FAILED");
       $finish;
   end

endmodule
module testit;


   reg clk;
   reg [2:0] cnt;

   always
      begin
         # 50 clk = ~clk;
      end

   task idle;
      input [15:0] waitcnt;

   begin: idletask

      integer i;
      for (i=0; i < waitcnt; i = i + 1)
         begin
            @ (posedge clk);

         end

   end
   endtask

   initial begin
       clk = 0;
       cnt = 0;
       $display ("One");
       cnt = cnt + 1;
       idle(3);
       cnt = cnt + 1;
       $display ("Two");
       if(cnt === 2)
         $display("PASSED");
       else
         $display("FAILED");
       $finish;
   end

endmodule