data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/SystemClockControl.v
1: b"%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/SystemClockControl.v:102: Cannot find file containing module: 'buff'\nbuff buff_highSpeedClock (.A(clk_ringosc_i), .Q(highSpeedClock_buff));  \n^~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src,data/full_repos/permissive/137416811/buff\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src,data/full_repos/permissive/137416811/buff.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src,data/full_repos/permissive/137416811/buff.sv\n             buff\n             buff.v\n             buff.sv\n             obj_dir/buff\n             obj_dir/buff.v\n             obj_dir/buff.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/SystemClockControl.v:105: Cannot find file containing module: 'buff'\nbuff buff_highSpeedClock_x2 (.A(clk_ringosc_x2_i), .Q(highSpeedClock_x2_buff));  \n^~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/SystemClockControl.v:118: Cannot find file containing module: 'ring_osc_adjust'\nring_osc_adjust ring_osc_adjust_1 (\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module SystemClockControl (
	OperatingClockRef_i,
	Clock32KIn_i,
	SPIClock_i,
	ResetIn_i,
	
	FfeClkSelect_i,
	SmClkSelect_i,
	SmSpeedSelect_i,
	SpiClkSelect_i,
	ClkSourceSelect_i,
	Clk32KhzEnable_i,
	MainClkEnable_i,
	FfeClkEnable_i,
	CM_AutoDrain_Busy,
	
	SmClock_o,
	FfeClock_o,
	FfeClock_x2_o,
	clock_32KHz_o,
	multiplierClk_o,
	ClockGen_State_o,
	CM_FIFO_ReadClk,
	
	clk_ringosc_i,
	clk_ringosc_x2_i,
	enable_i,
	clk_cal_value_o,
	assp_ringosc_en_o
);


input			OperatingClockRef_i;
input			Clock32KIn_i;
input			SPIClock_i;
input			ResetIn_i;
	
input	[2:0]	FfeClkSelect_i;
input	[2:0]	SmClkSelect_i;
input			SmSpeedSelect_i;
input			SpiClkSelect_i;
input			ClkSourceSelect_i;
input			Clk32KhzEnable_i;
input			MainClkEnable_i;
input			FfeClkEnable_i;
input			CM_AutoDrain_Busy;

output			SmClock_o;
output			FfeClock_o;
output			FfeClock_x2_o;
output			clock_32KHz_o;
output			multiplierClk_o;
output	[3:0]	ClockGen_State_o;
output			CM_FIFO_ReadClk;

input			clk_ringosc_i;
input			clk_ringosc_x2_i;
input			enable_i;
output	[15:0]	clk_cal_value_o;
output			assp_ringosc_en_o;

reg				multiplierClk_o;
wire	[3:0]	ClockGen_State_o;
wire			CM_FIFO_ReadClk;
wire			assp_ringosc_en_o;




wire			highSpeedClock, highSpeedClock_buff, highSpeedClock_x2_buff;
reg		[6:0]	ClockDiv;
wire			FfeClock;
reg				SmClock;
wire			RingOscEnable;
wire			ring_osc_clk;
wire			OperatingClockRef;

	




assign	OperatingClockRef = OperatingClockRef_i;



assign CM_FIFO_ReadClk = CM_AutoDrain_Busy ? highSpeedClock_buff : SPIClock_i;






assign	clock_32KHz_o = Clock32KIn_i && Clk32KhzEnable_i;




buff buff_highSpeedClock (.A(clk_ringosc_i), .Q(highSpeedClock_buff));


buff buff_highSpeedClock_x2 (.A(clk_ringosc_x2_i), .Q(highSpeedClock_x2_buff));







assign FfeClock_o = SpiClkSelect_i ? SPIClock_i : highSpeedClock_buff;
assign FfeClock_x2_o = SpiClkSelect_i ? SPIClock_i : highSpeedClock_x2_buff;
assign SmClock_o = SpiClkSelect_i ? SPIClock_i : highSpeedClock_buff;


ring_osc_adjust ring_osc_adjust_1 (
		.reset_i			( ResetIn_i				),
		.clk_ringosc_i		( clk_ringosc_i			),
		.clk_32khz_i		( Clock32KIn_i			),
		.enable_i			( enable_i				),
		.cal_val_o			( clk_cal_value_o		)
	);

assign assp_ringosc_en_o = ClkSourceSelect_i || MainClkEnable_i;
	
endmodule
module SystemClockControl (
	OperatingClockRef_i,
	Clock32KIn_i,
	SPIClock_i,
	ResetIn_i,
	
	FfeClkSelect_i,
	SmClkSelect_i,
	SmSpeedSelect_i,
	SpiClkSelect_i,
	ClkSourceSelect_i,
	Clk32KhzEnable_i,
	MainClkEnable_i,
	FfeClkEnable_i,
	CM_AutoDrain_Busy,
	
	SmClock_o,
	FfeClock_o,
	FfeClock_x2_o,
	clock_32KHz_o,
	multiplierClk_o,
	ClockGen_State_o,
	CM_FIFO_ReadClk,
	
	clk_ringosc_i,
	clk_ringosc_x2_i,
	enable_i,
	clk_cal_value_o,
	assp_ringosc_en_o
);



input			OperatingClockRef_i;
input			Clock32KIn_i;
input			SPIClock_i;
input			ResetIn_i;
	
input	[2:0]	FfeClkSelect_i;
input	[2:0]	SmClkSelect_i;
input			SmSpeedSelect_i;
input			SpiClkSelect_i;
input			ClkSourceSelect_i;
input			Clk32KhzEnable_i;
input			MainClkEnable_i;
input			FfeClkEnable_i;
input			CM_AutoDrain_Busy;

output			SmClock_o;
output			FfeClock_o;
output			FfeClock_x2_o;
output			clock_32KHz_o;
output			multiplierClk_o;
output	[3:0]	ClockGen_State_o;
output			CM_FIFO_ReadClk;

input			clk_ringosc_i;
input			clk_ringosc_x2_i;
input			enable_i;
output	[15:0]	clk_cal_value_o;
output			assp_ringosc_en_o;

reg				multiplierClk_o;
wire	[3:0]	ClockGen_State_o;
wire			CM_FIFO_ReadClk;
wire			assp_ringosc_en_o;




wire			highSpeedClock, highSpeedClock_buff, highSpeedClock_x2_buff;
reg		[6:0]	ClockDiv;
wire			FfeClock;
reg				SmClock;
wire			RingOscEnable;
wire			ring_osc_clk;
wire			OperatingClockRef;

	




assign	OperatingClockRef = OperatingClockRef_i;



assign CM_FIFO_ReadClk = CM_AutoDrain_Busy ? highSpeedClock_buff : SPIClock_i;






assign	clock_32KHz_o = Clock32KIn_i && Clk32KhzEnable_i;




buff buff_highSpeedClock (.A(clk_ringosc_i), .Q(highSpeedClock_buff));


buff buff_highSpeedClock_x2 (.A(clk_ringosc_x2_i), .Q(highSpeedClock_x2_buff));







assign FfeClock_o = SpiClkSelect_i ? SPIClock_i : highSpeedClock_buff;
assign FfeClock_x2_o = SpiClkSelect_i ? SPIClock_i : highSpeedClock_x2_buff;
assign SmClock_o = SpiClkSelect_i ? SPIClock_i : highSpeedClock_buff;


ring_osc_adjust ring_osc_adjust_1 (
		.reset_i			( ResetIn_i				),
		.clk_ringosc_i		( clk_ringosc_i			),
		.clk_32khz_i		( Clock32KIn_i			),
		.enable_i			( enable_i				),
		.cal_val_o			( clk_cal_value_o		)
	);

assign assp_ringosc_en_o = ClkSourceSelect_i || MainClkEnable_i;
	
endmodule