data/full_repos/permissive/160788788/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160788788/test.v:9: Unsupported: Ignoring delay on this delayed statement.\n  #3 reset = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160788788/test.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #3 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/160788788/test.v:13: Unsupported: Ignoring delay on this delayed statement.\n always #10 clock = ~clock;\n        ^\n%Error: data/full_repos/permissive/160788788/test.v:15: Cannot find file containing module: \'mips\'\n mips mips(.clock(clock), .reset(reset));\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/160788788,data/full_repos/permissive/160788788/mips\n             data/full_repos/permissive/160788788,data/full_repos/permissive/160788788/mips.v\n             data/full_repos/permissive/160788788,data/full_repos/permissive/160788788/mips.sv\n             mips\n             mips.v\n             mips.sv\n             obj_dir/mips\n             obj_dir/mips.v\n             obj_dir/mips.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();
	reg clock, reset;


	initial
	begin
		clock = 0;
		reset = 0;
		#3 reset = 1;
        #3 reset = 0;
	end

	always #10 clock = ~clock;

	mips mips(.clock(clock), .reset(reset));

endmodule
module test();

	reg clock, reset;


	initial
	begin
		clock = 0;
		reset = 0;
		#3 reset = 1;
        #3 reset = 0;
	end

	always #10 clock = ~clock;

	mips mips(.clock(clock), .reset(reset));

endmodule