data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/jump_control.v
 line:85: before: "&"
data/verilator_xmls/1ccee266-3aa4-478a-a270-32efee876f15.xml
module jump_control
#(parameter N=3)
(
	input  wire         clk, rst, 
	input  wire         start,
        output wire         out ,
	output wire         tick
);


reg [N-1:0] cnt;
reg [N-1:0] cnt_next;

reg [2-1:0] state, state_next;
wire        tirgger;

localparam  [2-1:0]
        idle     = 2'd0,
        wait1    = 2'd1,
        jump     = 2'd2,
        wait2    = 2'd3;


always @(posedge clk)
	if (rst) begin
                cnt           <=  {N{1'b0}} ;
                state         <=   0 ;
        end
	else begin
		cnt           <=   cnt_next;
                state         <=   state_next ;
        end


always @*
begin
        case (state)
                idle : begin
                    if (start) 
                        state_next <= wait1 ;
                    else
                        state_next  <=    idle ;
                    cnt_next        <=    {N{1'b0}} ;
                end
                wait1 : begin
                    if (&cnt) 
                        state_next <= jump ;
                    else
                        state_next <= wait1 ;
                    cnt_next       <=    cnt + 1 ;
                end
                jump : begin
                    state_next     <= wait2 ;
                    cnt_next       <=    {N{1'b0}} ;
                end
                wait2 : begin
                    if (start) 
                        state_next <= wait2 ;
                    else
                        state_next  <=    idle ;
                    cnt_next        <=    {N{1'b0}} ;
                end
                default : begin 
                    state      <= idle;
                    cnt        <= {N{1'b0}} ;
                end
        endcase
end




assign tick = (state==jump) ;
assign out  = (state==jump)|(state==wait2) ;

endmodule
module jump_control
#(parameter N=3)
(
	input  wire         clk, rst, 
	input  wire         start,
        output wire         out ,
	output wire         tick
);



reg [N-1:0] cnt;
reg [N-1:0] cnt_next;

reg [2-1:0] state, state_next;
wire        tirgger;

localparam  [2-1:0]
        idle     = 2'd0,
        wait1    = 2'd1,
        jump     = 2'd2,
        wait2    = 2'd3;


always @(posedge clk)
	if (rst) begin
                cnt           <=  {N{1'b0}} ;
                state         <=   0 ;
        end
	else begin
		cnt           <=   cnt_next;
                state         <=   state_next ;
        end


always @*
begin
        case (state)
                idle : begin
                    if (start) 
                        state_next <= wait1 ;
                    else
                        state_next  <=    idle ;
                    cnt_next        <=    {N{1'b0}} ;
                end
                wait1 : begin
                    if (&cnt) 
                        state_next <= jump ;
                    else
                        state_next <= wait1 ;
                    cnt_next       <=    cnt + 1 ;
                end
                jump : begin
                    state_next     <= wait2 ;
                    cnt_next       <=    {N{1'b0}} ;
                end
                wait2 : begin
                    if (start) 
                        state_next <= wait2 ;
                    else
                        state_next  <=    idle ;
                    cnt_next        <=    {N{1'b0}} ;
                end
                default : begin 
                    state      <= idle;
                    cnt        <= {N{1'b0}} ;
                end
        endcase
end




assign tick = (state==jump) ;
assign out  = (state==jump)|(state==wait2) ;

endmodule