data/full_repos/permissive/168234415/A1_Factorial_Accelerator/CMPE140_Assignment1.srcs/sources_1/new/Mult.v
data/verilator_xmls/dcb23b99-a0db-404d-834c-d39cccd73531.xml
module MUL #(parameter Data_Width = 32)(
    input [Data_Width - 1:0] x, y,
    output reg [Data_Width - 1:0] z
);

    always @ (x or y)
        begin
            z <= x * y;
        end

endmodule
module MUL #(parameter Data_Width = 32)(
    input [Data_Width - 1:0] x, y,
    output reg [Data_Width - 1:0] z
);


    always @ (x or y)
        begin
            z <= x * y;
        end

endmodule