data/full_repos/permissive/138473269/rtl/mano_dp.v
1: b'%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:5: Cannot find include file: rtl/basic_params.v\n`include "rtl/basic_params.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138473269/rtl,data/full_repos/permissive/138473269/rtl/basic_params.v\n             data/full_repos/permissive/138473269/rtl,data/full_repos/permissive/138473269/rtl/basic_params.v.v\n             data/full_repos/permissive/138473269/rtl,data/full_repos/permissive/138473269/rtl/basic_params.v.sv\n             rtl/basic_params.v\n             rtl/basic_params.v.v\n             rtl/basic_params.v.sv\n             obj_dir/rtl/basic_params.v\n             obj_dir/rtl/basic_params.v.v\n             obj_dir/rtl/basic_params.v.sv\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:47: Define or directive not defined: \'`buswidth\'\n input [`buswidth-1:0] cs_bus_sel;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:48: Define or directive not defined: \'`funcwidth\'\n input [`funcwidth-1:0] cs_alu_func;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:51: Define or directive not defined: \'`datawidth\'\n output [`datawidth-1:0] IR;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:52: Define or directive not defined: \'`datawidth\'\n output [`datawidth-1:0] AC;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:53: Define or directive not defined: \'`datawidth\'\n output [`datawidth-1:0] DR;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:65: Define or directive not defined: \'`datawidth\'\n wire [`datawidth-1:0] alua, alub, aluout;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:66: Define or directive not defined: \'`iowidth\'\n wire [`iowidth-1:0] inprin;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:68: Define or directive not defined: \'`datawidth\'\n wire [`datawidth-1:0] TR;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:69: Define or directive not defined: \'`addrwidth\'\n wire [`addrwidth-1:0] AR, PC;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:70: Define or directive not defined: \'`iowidth\'\n wire [`iowidth-1:0] INPR, OUTR;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:71: Define or directive not defined: \'`datawidth\'\n wire [`datawidth-1:0] memout, cache_cpu_dout, cache_mem_dout;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:72: Define or directive not defined: \'`datawidth\'\n reg [`datawidth-1:0] busout;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:73: Define or directive not defined: \'`addrwidth\'\n wire [`addrwidth-1:0]  cache_mem_addr;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:90: Define or directive not defined: \'`addrwidth\'\n register     #(.width(`addrwidth)) AR_R   (.clk(mclk), .rst(cs_ar_clr_t),   .ld(cs_ar_ld),   .inc(cs_ar_inc),   .d(busout[11:0]),  .q(AR) ); \n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:91: Define or directive not defined: \'`datawidth\'\n register     #(.width(`datawidth)) IR_R   (.clk(mclk), .rst(cs_ir_clr_t),   .ld(cs_ir_ld),   .inc(cs_ir_inc),   .d(cache_cpu_dout),.q(IR) );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:92: Define or directive not defined: \'`addrwidth\'\n register     #(.width(`addrwidth)) PC_R   (.clk(mclk), .rst(cs_pc_clr_t),   .ld(cs_pc_ld),   .inc(cs_pc_inc),   .d(busout[11:0]),  .q(PC) );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:93: Define or directive not defined: \'`datawidth\'\n register     #(.width(`datawidth)) DR_R   (.clk(mclk), .rst(cs_dr_clr_t),   .ld(cs_dr_ld),   .inc(cs_dr_inc),   .d(busout),        .q(DR) );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:94: Define or directive not defined: \'`datawidth\'\n register     #(.width(`datawidth)) AC_R   (.clk(mclk), .rst(cs_ac_clr_t),   .ld(cs_ac_ld),   .inc(cs_ac_inc),   .d(aluout),        .q(AC) );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:95: Define or directive not defined: \'`datawidth\'\n register     #(.width(`datawidth)) TR_R   (.clk(mclk), .rst(cs_tr_clr_t),   .ld(cs_tr_ld),   .inc(cs_tr_inc),   .d(busout),        .q(TR) );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:96: Define or directive not defined: \'`iowidth\'\n register     #(.width(`iowidth))   INPR_R (.clk(mclk), .rst(cs_inpr_clr_t), .ld(cs_inpr_ld), .inc(cs_inpr_inc), .d(inprin),        .q(INPR) );\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:97: Define or directive not defined: \'`iowidth\'\n register     #(.width(`iowidth))   OUTR_R (.clk(mclk), .rst(cs_outr_clr_t), .ld(cs_outr_ld), .inc(cs_outr_inc), .d(busout[7:0]),   .q(OUTR) );\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:135: Define or directive not defined: \'`BUS_MEM\'\n   `BUS_MEM : busout <= memout;                                  \n   ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:135: syntax error, unexpected \':\', expecting endcase\n   `BUS_MEM : busout <= memout;                                  \n            ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:136: Define or directive not defined: \'`BUS_AR\'\n   `BUS_AR  : busout <= AR;                                      \n   ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:137: Define or directive not defined: \'`BUS_PC\'\n   `BUS_PC  : busout <= PC;                                      \n   ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:138: Define or directive not defined: \'`BUS_DR\'\n   `BUS_DR  : busout <= DR;                                      \n   ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:139: Define or directive not defined: \'`BUS_AC\'\n   `BUS_AC  : busout <= AC;                                      \n   ^~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:140: Define or directive not defined: \'`BUS_INP\'\n   `BUS_INP : busout <= INPR;                                    \n   ^~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_dp.v:141: Define or directive not defined: \'`BUS_IR\'\n   `BUS_IR  : busout <= IR;                                      \n   ^~~~~~~\n%Error: Exiting due to 30 error(s)\n'
module datapath (	mrst, mclk, 

					cs_ar_clr, cs_ir_clr, cs_pc_clr, cs_dr_clr, cs_ac_clr, cs_tr_clr, cs_inpr_clr, cs_outr_clr,
					cs_ar_inc, cs_ir_inc, cs_pc_inc, cs_dr_inc, cs_ac_inc, cs_tr_inc, cs_inpr_inc, cs_outr_inc,
					cs_ar_ld, cs_ir_ld,   cs_pc_ld,  cs_dr_ld,  cs_ac_ld,  cs_tr_ld,  cs_inpr_ld,  cs_outr_ld,

					cs_s_ld, cs_s_clr, cs_e_ld, cs_e_clr, cs_i_ld, cs_i_clr, 
					cs_fgi_ld, cs_fgi_clr, cs_fgo_ld, cs_fgo_clr, cs_r_ld, cs_r_clr, cs_ien_ld, cs_ien_clr,

					cs_mem_rd, cs_mem_wr,

					cs_bus_sel, 

					cs_alu_func, cs_alub_sel,

					s_in, ien_in, fgi_in, fgo_in, r_in,

					cache_hit,

					IR,
					AC,
					DR,
					E,
					I,
					FGI,
					FGO,
					S,
					R,
					IEN,
					b_signal
					);
	input mclk, mrst;
	input cs_ar_clr, cs_ir_clr, cs_pc_clr, cs_dr_clr, cs_ac_clr, cs_tr_clr, cs_inpr_clr, cs_outr_clr;
	input cs_ar_inc, cs_ir_inc, cs_pc_inc, cs_dr_inc, cs_ac_inc, cs_tr_inc, cs_inpr_inc, cs_outr_inc;
	input cs_ar_ld,  cs_ir_ld,  cs_pc_ld,  cs_dr_ld,  cs_ac_ld,  cs_tr_ld,  cs_inpr_ld,  cs_outr_ld;
	input cs_s_ld, cs_s_clr, cs_e_ld, cs_e_clr,  cs_i_ld,  cs_i_clr;
	input cs_fgi_ld, cs_fgi_clr,cs_fgo_ld, cs_fgo_clr, cs_r_ld, cs_r_clr, cs_ien_ld, cs_ien_clr;
	input cs_mem_rd, cs_mem_wr;
	input s_in, ien_in, fgi_in, fgo_in, r_in;
	input [`buswidth-1:0] cs_bus_sel;
	input [`funcwidth-1:0] cs_alu_func;
	input cs_alub_sel;
	output cache_hit;
	output [`datawidth-1:0] IR;
	output [`datawidth-1:0] AC;
	output [`datawidth-1:0] DR;
	output E;
	output I;
	output FGI;
	output FGO;
	output S;
	output R;
	output IEN;


	output b_signal;

	wire [`datawidth-1:0] alua, alub, aluout;
	wire [`iowidth-1:0] inprin;

	wire [`datawidth-1:0] TR;
	wire [`addrwidth-1:0] AR, PC;
	wire [`iowidth-1:0] INPR, OUTR;
	wire [`datawidth-1:0] memout, cache_cpu_dout, cache_mem_dout;
	reg [`datawidth-1:0] busout;
	wire [`addrwidth-1:0]  cache_mem_addr;

	assign cs_ar_clr_t   = cs_ar_clr   | mrst;
	assign cs_ir_clr_t   = cs_ir_clr   | mrst;
	assign cs_pc_clr_t   = cs_pc_clr   | mrst;
	assign cs_dr_clr_t   = cs_dr_clr   | mrst;
	assign cs_ac_clr_t   = cs_ac_clr   | mrst;
	assign cs_tr_clr_t   = cs_tr_clr   | mrst;
	assign cs_inpr_clr_t = cs_inpr_clr | mrst;
	assign cs_outr_clr_t = cs_outr_clr | mrst;
	assign cs_e_clr_t    = cs_e_clr    | mrst;
	assign cs_i_clr_t    = cs_i_clr    | mrst;
	assign cs_fgi_clr_t  = cs_fgi_clr  | mrst;
	assign cs_fgo_clr_t  = cs_fgo_clr  | mrst;
	assign cs_s_clr_t    = cs_s_clr    | mrst;
	

	register 	   #(.width(`addrwidth)) AR_R   (.clk(mclk), .rst(cs_ar_clr_t),   .ld(cs_ar_ld),   .inc(cs_ar_inc),   .d(busout[11:0]),  .q(AR) );	
	register 	   #(.width(`datawidth)) IR_R   (.clk(mclk), .rst(cs_ir_clr_t),   .ld(cs_ir_ld),   .inc(cs_ir_inc),   .d(cache_cpu_dout),.q(IR) );
	register 	   #(.width(`addrwidth)) PC_R   (.clk(mclk), .rst(cs_pc_clr_t),   .ld(cs_pc_ld),   .inc(cs_pc_inc),   .d(busout[11:0]),  .q(PC) );
	register 	   #(.width(`datawidth)) DR_R   (.clk(mclk), .rst(cs_dr_clr_t),   .ld(cs_dr_ld),   .inc(cs_dr_inc),   .d(busout),        .q(DR) );
	register 	   #(.width(`datawidth)) AC_R   (.clk(mclk), .rst(cs_ac_clr_t),   .ld(cs_ac_ld),   .inc(cs_ac_inc),   .d(aluout),        .q(AC) );
	register 	   #(.width(`datawidth)) TR_R   (.clk(mclk), .rst(cs_tr_clr_t),   .ld(cs_tr_ld),   .inc(cs_tr_inc),   .d(busout),        .q(TR) );
	register 	   #(.width(`iowidth))   INPR_R (.clk(mclk), .rst(cs_inpr_clr_t), .ld(cs_inpr_ld), .inc(cs_inpr_inc), .d(inprin),        .q(INPR) );
	register 	   #(.width(`iowidth))   OUTR_R (.clk(mclk), .rst(cs_outr_clr_t), .ld(cs_outr_ld), .inc(cs_outr_inc), .d(busout[7:0]),   .q(OUTR) );
	dff E_F   		(.clk(mclk), .rst(cs_e_clr_t),   .ld(cs_e_ld),   .d(alu_e_out), .q(E) );
	dff I_F   		(.clk(mclk), .rst(cs_i_clr_t),   .ld(cs_i_ld),   .d(IR[15]),    .q(I) );
	dff FGI_F 		(.clk(mclk), .rst(cs_fgi_clr_t), .ld(cs_fgi_ld), .d(fgi_in),    .q(FGI) );
	dff FGO_F 		(.clk(mclk), .rst(cs_fgo_clr_t), .ld(cs_fgo_ld), .d(fgo_in),    .q(FGO) );
	dff R_F   		(.clk(mclk), .rst(cs_r_clr_t),   .ld(cs_r_ld),   .d(r_in),      .q(R) );
	dff S_F   		(.clk(mclk), .rst(cs_s_clr_t),   .ld(cs_s_ld),   .d(s_in),      .q(S) );
	dff IEN_F 		(.clk(mclk), .rst(cs_ien_clr_t), .ld(cs_ien_ld), .d(ien_in),    .q(IEN) );
	dmc256x16 CACHE (	.clk(mclk), 
						.clr(mrst), 
						.cpu_addr(AR), 
						.cpu_rd(cs_mem_rd), 
						.cpu_wr(cs_mem_wr), 
						.cpu_din(busout), 
						.cpu_dout(cache_cpu_dout), 
						.cache_hit(cache_hit),
						.ir_ld_b(cs_ir_ld),
						.mem_addr(cache_mem_addr), 
						.mem_rd(cache_mem_rd), 
						.mem_wr(cache_mem_wr), 
						.mem_din(memout), 
						.mem_dout(cache_mem_dout),
						.b(b_signal)
					);

	mem4096x16 MEM  (	.clk(mclk), 
						.addr(cache_mem_addr), 
						.rd(cache_mem_rd), 
						.wr(cache_mem_wr), 
						.din(cache_mem_dout), 
						.dout(memout)
					);
	alu ALU (.a(alua), .b(alub), .e_in(E), .func(cs_alu_func), .e_out(alu_e_out), .z(aluout));
	 
	                                                                      

	always @(cs_bus_sel)                                                  
		case(cs_bus_sel)                                                  
			`BUS_MEM : busout <= memout;                                  
			`BUS_AR  : busout <= AR;                                      
			`BUS_PC  : busout <= PC;                                      
			`BUS_DR  : busout <= DR;                                      
			`BUS_AC  : busout <= AC;                                      
			`BUS_INP : busout <= INPR;                                    
			`BUS_IR  : busout <= IR;                                      
			default  : busout <= TR;                                      
		endcase  
		                                                                  
	assign alua = DR;                                                     
	assign alub = (cs_alub_sel) ? {8'b00000000,INPR} : AC;                
endmodule
module datapath (	mrst, mclk, 

					cs_ar_clr, cs_ir_clr, cs_pc_clr, cs_dr_clr, cs_ac_clr, cs_tr_clr, cs_inpr_clr, cs_outr_clr,
					cs_ar_inc, cs_ir_inc, cs_pc_inc, cs_dr_inc, cs_ac_inc, cs_tr_inc, cs_inpr_inc, cs_outr_inc,
					cs_ar_ld, cs_ir_ld,   cs_pc_ld,  cs_dr_ld,  cs_ac_ld,  cs_tr_ld,  cs_inpr_ld,  cs_outr_ld,

					cs_s_ld, cs_s_clr, cs_e_ld, cs_e_clr, cs_i_ld, cs_i_clr, 
					cs_fgi_ld, cs_fgi_clr, cs_fgo_ld, cs_fgo_clr, cs_r_ld, cs_r_clr, cs_ien_ld, cs_ien_clr,

					cs_mem_rd, cs_mem_wr,

					cs_bus_sel, 

					cs_alu_func, cs_alub_sel,

					s_in, ien_in, fgi_in, fgo_in, r_in,

					cache_hit,

					IR,
					AC,
					DR,
					E,
					I,
					FGI,
					FGO,
					S,
					R,
					IEN,
					b_signal
					);

	input mclk, mrst;
	input cs_ar_clr, cs_ir_clr, cs_pc_clr, cs_dr_clr, cs_ac_clr, cs_tr_clr, cs_inpr_clr, cs_outr_clr;
	input cs_ar_inc, cs_ir_inc, cs_pc_inc, cs_dr_inc, cs_ac_inc, cs_tr_inc, cs_inpr_inc, cs_outr_inc;
	input cs_ar_ld,  cs_ir_ld,  cs_pc_ld,  cs_dr_ld,  cs_ac_ld,  cs_tr_ld,  cs_inpr_ld,  cs_outr_ld;
	input cs_s_ld, cs_s_clr, cs_e_ld, cs_e_clr,  cs_i_ld,  cs_i_clr;
	input cs_fgi_ld, cs_fgi_clr,cs_fgo_ld, cs_fgo_clr, cs_r_ld, cs_r_clr, cs_ien_ld, cs_ien_clr;
	input cs_mem_rd, cs_mem_wr;
	input s_in, ien_in, fgi_in, fgo_in, r_in;
	input [`buswidth-1:0] cs_bus_sel;
	input [`funcwidth-1:0] cs_alu_func;
	input cs_alub_sel;
	output cache_hit;
	output [`datawidth-1:0] IR;
	output [`datawidth-1:0] AC;
	output [`datawidth-1:0] DR;
	output E;
	output I;
	output FGI;
	output FGO;
	output S;
	output R;
	output IEN;


	output b_signal;

	wire [`datawidth-1:0] alua, alub, aluout;
	wire [`iowidth-1:0] inprin;

	wire [`datawidth-1:0] TR;
	wire [`addrwidth-1:0] AR, PC;
	wire [`iowidth-1:0] INPR, OUTR;
	wire [`datawidth-1:0] memout, cache_cpu_dout, cache_mem_dout;
	reg [`datawidth-1:0] busout;
	wire [`addrwidth-1:0]  cache_mem_addr;

	assign cs_ar_clr_t   = cs_ar_clr   | mrst;
	assign cs_ir_clr_t   = cs_ir_clr   | mrst;
	assign cs_pc_clr_t   = cs_pc_clr   | mrst;
	assign cs_dr_clr_t   = cs_dr_clr   | mrst;
	assign cs_ac_clr_t   = cs_ac_clr   | mrst;
	assign cs_tr_clr_t   = cs_tr_clr   | mrst;
	assign cs_inpr_clr_t = cs_inpr_clr | mrst;
	assign cs_outr_clr_t = cs_outr_clr | mrst;
	assign cs_e_clr_t    = cs_e_clr    | mrst;
	assign cs_i_clr_t    = cs_i_clr    | mrst;
	assign cs_fgi_clr_t  = cs_fgi_clr  | mrst;
	assign cs_fgo_clr_t  = cs_fgo_clr  | mrst;
	assign cs_s_clr_t    = cs_s_clr    | mrst;
	

	register 	   #(.width(`addrwidth)) AR_R   (.clk(mclk), .rst(cs_ar_clr_t),   .ld(cs_ar_ld),   .inc(cs_ar_inc),   .d(busout[11:0]),  .q(AR) );	
	register 	   #(.width(`datawidth)) IR_R   (.clk(mclk), .rst(cs_ir_clr_t),   .ld(cs_ir_ld),   .inc(cs_ir_inc),   .d(cache_cpu_dout),.q(IR) );
	register 	   #(.width(`addrwidth)) PC_R   (.clk(mclk), .rst(cs_pc_clr_t),   .ld(cs_pc_ld),   .inc(cs_pc_inc),   .d(busout[11:0]),  .q(PC) );
	register 	   #(.width(`datawidth)) DR_R   (.clk(mclk), .rst(cs_dr_clr_t),   .ld(cs_dr_ld),   .inc(cs_dr_inc),   .d(busout),        .q(DR) );
	register 	   #(.width(`datawidth)) AC_R   (.clk(mclk), .rst(cs_ac_clr_t),   .ld(cs_ac_ld),   .inc(cs_ac_inc),   .d(aluout),        .q(AC) );
	register 	   #(.width(`datawidth)) TR_R   (.clk(mclk), .rst(cs_tr_clr_t),   .ld(cs_tr_ld),   .inc(cs_tr_inc),   .d(busout),        .q(TR) );
	register 	   #(.width(`iowidth))   INPR_R (.clk(mclk), .rst(cs_inpr_clr_t), .ld(cs_inpr_ld), .inc(cs_inpr_inc), .d(inprin),        .q(INPR) );
	register 	   #(.width(`iowidth))   OUTR_R (.clk(mclk), .rst(cs_outr_clr_t), .ld(cs_outr_ld), .inc(cs_outr_inc), .d(busout[7:0]),   .q(OUTR) );
	dff E_F   		(.clk(mclk), .rst(cs_e_clr_t),   .ld(cs_e_ld),   .d(alu_e_out), .q(E) );
	dff I_F   		(.clk(mclk), .rst(cs_i_clr_t),   .ld(cs_i_ld),   .d(IR[15]),    .q(I) );
	dff FGI_F 		(.clk(mclk), .rst(cs_fgi_clr_t), .ld(cs_fgi_ld), .d(fgi_in),    .q(FGI) );
	dff FGO_F 		(.clk(mclk), .rst(cs_fgo_clr_t), .ld(cs_fgo_ld), .d(fgo_in),    .q(FGO) );
	dff R_F   		(.clk(mclk), .rst(cs_r_clr_t),   .ld(cs_r_ld),   .d(r_in),      .q(R) );
	dff S_F   		(.clk(mclk), .rst(cs_s_clr_t),   .ld(cs_s_ld),   .d(s_in),      .q(S) );
	dff IEN_F 		(.clk(mclk), .rst(cs_ien_clr_t), .ld(cs_ien_ld), .d(ien_in),    .q(IEN) );
	dmc256x16 CACHE (	.clk(mclk), 
						.clr(mrst), 
						.cpu_addr(AR), 
						.cpu_rd(cs_mem_rd), 
						.cpu_wr(cs_mem_wr), 
						.cpu_din(busout), 
						.cpu_dout(cache_cpu_dout), 
						.cache_hit(cache_hit),
						.ir_ld_b(cs_ir_ld),
						.mem_addr(cache_mem_addr), 
						.mem_rd(cache_mem_rd), 
						.mem_wr(cache_mem_wr), 
						.mem_din(memout), 
						.mem_dout(cache_mem_dout),
						.b(b_signal)
					);

	mem4096x16 MEM  (	.clk(mclk), 
						.addr(cache_mem_addr), 
						.rd(cache_mem_rd), 
						.wr(cache_mem_wr), 
						.din(cache_mem_dout), 
						.dout(memout)
					);
	alu ALU (.a(alua), .b(alub), .e_in(E), .func(cs_alu_func), .e_out(alu_e_out), .z(aluout));
	 
	                                                                      

	always @(cs_bus_sel)                                                  
		case(cs_bus_sel)                                                  
			`BUS_MEM : busout <= memout;                                  
			`BUS_AR  : busout <= AR;                                      
			`BUS_PC  : busout <= PC;                                      
			`BUS_DR  : busout <= DR;                                      
			`BUS_AC  : busout <= AC;                                      
			`BUS_INP : busout <= INPR;                                    
			`BUS_IR  : busout <= IR;                                      
			default  : busout <= TR;                                      
		endcase  
		                                                                  
	assign alua = DR;                                                     
	assign alub = (cs_alub_sel) ? {8'b00000000,INPR} : AC;                
endmodule