data/full_repos/permissive/205055389/vlib/74xxGateLevel.v
 line:125: before: "11"
1: b"%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:197: syntax error, unexpected (-for-strength, expecting '('\n  not (highz1, strong0) #40 g1(Y1, A1);\n       ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:236: syntax error, unexpected (-for-strength, expecting '('\n  nor (highz1,strong0) #35 g1(Y1, A1, B1);\n       ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:255: syntax error, unexpected (-for-strength, expecting '('\n  nand (highz1, strong0) #35 g1(Y1, A1, B1, C1, D1);\n        ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:367: syntax error, unexpected (-for-strength, expecting '('\n  nand (highz1, strong0) #35 g1(Y1, A1, B1, C1);\n        ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:385: syntax error, unexpected (-for-strength, expecting '('\n  and (highz1, strong0) #21 g1(Y1, A1, B1);\n       ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:421: syntax error, unexpected (-for-strength, expecting '('\n  and (highz1, strong0) #40 g1(Y1, A1, B1, C1);\n       ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:457: syntax error, unexpected (-for-strength, expecting '('\n  nand (highz1,strong0) #35 g1(Y1, A1, B1);\n        ^~~~~~\n%Error: Exiting due to 7 error(s)\n"
module main;
reg w14;
reg w16;
reg w15;
reg w3;
reg w23;
reg w24;
reg w8;
reg w11;
reg w12;
reg w10;
reg w13;
reg w5;
reg w9;
reg w26;
wire w32;
wire w6;
wire w7;
wire w19;
wire w4;
wire [6:0] w0;
wire w34;
wire w21;
wire w31;
wire w28;
wire w36;
wire w20;
wire w1;
wire w25;
wire w35;
wire w18;
wire w30;
wire w22;
wire w17;
wire w2;
wire w27;
wire w33;
wire w29;


  SN7470 g8 (._CLR(w26), .J1(w23), .J2(w11), ._J(w10), .K1(w9), .K2(w8), ._K(w5), ._PRE(w3), .CLK(w24), .Q(w22), ._Q(w21), .J(w25), .K(w2), .CLK_1(w36), .J_1(w35), .K_1(w34), .w1_1(w33), .w1_2(w32), .w2_1(w31), .w2_2(w30), .w3_1(w29), .w3_2(w28), .w4_1(w27), .w4_2(w18));











  assign w0 = {w1, w7, w4, w17, w6, w19, w20};









  SN7449 g0 (._BI(w16), .D(w15), .C(w14), .B(w13), .A(w12), .g(w17), .f(w19), .e(w4), .d(w1), .c(w7), .b(w6), .a(w20));



endmodule
module main;

reg w14;
reg w16;
reg w15;
reg w3;
reg w23;
reg w24;
reg w8;
reg w11;
reg w12;
reg w10;
reg w13;
reg w5;
reg w9;
reg w26;
wire w32;
wire w6;
wire w7;
wire w19;
wire w4;
wire [6:0] w0;
wire w34;
wire w21;
wire w31;
wire w28;
wire w36;
wire w20;
wire w1;
wire w25;
wire w35;
wire w18;
wire w30;
wire w22;
wire w17;
wire w2;
wire w27;
wire w33;
wire w29;


  SN7470 g8 (._CLR(w26), .J1(w23), .J2(w11), ._J(w10), .K1(w9), .K2(w8), ._K(w5), ._PRE(w3), .CLK(w24), .Q(w22), ._Q(w21), .J(w25), .K(w2), .CLK_1(w36), .J_1(w35), .K_1(w34), .w1_1(w33), .w1_2(w32), .w2_1(w31), .w2_2(w30), .w3_1(w29), .w3_2(w28), .w4_1(w27), .w4_2(w18));











  assign w0 = {w1, w7, w4, w17, w6, w19, w20};









  SN7449 g0 (._BI(w16), .D(w15), .C(w14), .B(w13), .A(w12), .g(w17), .f(w19), .e(w4), .d(w1), .c(w7), .b(w6), .a(w20));



endmodule