data/full_repos/permissive/108561032/procesador_segmentado_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/108561032/procesador_segmentado_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108561032/procesador_segmentado_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/108561032/procesador_segmentado_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/108561032/procesador_segmentado_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/108561032/procesador_segmentado_tb.v:27: Cannot find file containing module: \'procesador_segmentado\'\n procesador_segmentado uut(\n ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/108561032,data/full_repos/permissive/108561032/procesador_segmentado\n             data/full_repos/permissive/108561032,data/full_repos/permissive/108561032/procesador_segmentado.v\n             data/full_repos/permissive/108561032,data/full_repos/permissive/108561032/procesador_segmentado.sv\n             procesador_segmentado\n             procesador_segmentado.v\n             procesador_segmentado.sv\n             obj_dir/procesador_segmentado\n             obj_dir/procesador_segmentado.v\n             obj_dir/procesador_segmentado.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module procesador_segmentado_tb();
    reg clk;
    reg reset;

	procesador_segmentado uut(
		.clk(clk),
		.reset(reset)
	);

	always begin
		clk=1'b1; 
		#50;
		clk=1'b0;
		#50;
	end

initial begin
	reset=1'b1;
	#50;
	reset=1'b0;
	#50;
	

end
	
endmodule
module procesador_segmentado_tb();

    reg clk;
    reg reset;

	procesador_segmentado uut(
		.clk(clk),
		.reset(reset)
	);

	always begin
		clk=1'b1; 
		#50;
		clk=1'b0;
		#50;
	end

initial begin
	reset=1'b1;
	#50;
	reset=1'b0;
	#50;
	

end
	
endmodule