data/full_repos/permissive/20289584/ffff.v
 line:23: before: "~"
1: b"%Error: data/full_repos/permissive/20289584/ffff.v:23: syntax error, unexpected '~', expecting TYPE-IDENTIFIER\nalways @(posedge clk or posedge ~rst)\n                                ^\n%Error: data/full_repos/permissive/20289584/ffff.v:37: syntax error, unexpected '=', expecting IDENTIFIER\n     Clkout =0;\n            ^\n%Error: data/full_repos/permissive/20289584/ffff.v:43: syntax error, unexpected '=', expecting IDENTIFIER\n     Clkout =1;\n            ^\n%Error: data/full_repos/permissive/20289584/ffff.v:47: syntax error, unexpected '=', expecting IDENTIFIER\n     Pulse =0;\n           ^\n%Error: data/full_repos/permissive/20289584/ffff.v:50: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n"
module ffff(clk,rst,Pulse,Clkout,counterOut,clk_out);

parameter Divider =6;
parameter Bitwidth = 4;



input clk,rst;
output Pulse,Clkout;
output [3:0] counterOut;
output clk_out;

wire clk,rst;
wire [3:0] counterOut;
reg Pulse,Clkout;
reg [Bitwidth-1:0] Counter;
wire [Bitwidth-1:0] HalfDivider;

assign clk_out = clk;
assign HalfDivider = (Divider >>1);
assign counterOut[3:0] = Counter[3:0];

always @(posedge clk or posedge ~rst)
	begin
		if(rst==0)
		begin
			Pulse =0;
			Counter =0;
			Clkout =0;
		end
		else
		begin
			Counter = Counter+1;
			case (Counter)
				Divider:
				begin
					Clkout =0;
					Counter =0;
					Pulse =1;
				end
				HalfDivider:
				begin
					Clkout =1;
				end
				default:
				begin
					Pulse =0;
				end
			endcase
		end
	end
endmodule
module ffff(clk,rst,Pulse,Clkout,counterOut,clk_out);


parameter Divider =6;
parameter Bitwidth = 4;



input clk,rst;
output Pulse,Clkout;
output [3:0] counterOut;
output clk_out;

wire clk,rst;
wire [3:0] counterOut;
reg Pulse,Clkout;
reg [Bitwidth-1:0] Counter;
wire [Bitwidth-1:0] HalfDivider;

assign clk_out = clk;
assign HalfDivider = (Divider >>1);
assign counterOut[3:0] = Counter[3:0];

always @(posedge clk or posedge ~rst)
	begin
		if(rst==0)
		begin
			Pulse =0;
			Counter =0;
			Clkout =0;
		end
		else
		begin
			Counter = Counter+1;
			case (Counter)
				Divider:
				begin
					Clkout =0;
					Counter =0;
					Pulse =1;
				end
				HalfDivider:
				begin
					Clkout =1;
				end
				default:
				begin
					Pulse =0;
				end
			endcase
		end
	end
endmodule