data/full_repos/permissive/156425967/xilinx_arty_a7/LED_clocked/led_clk.v
data/verilator_xmls/9435e983-35f4-4ae7-9b1f-a9a85e3a347b.xml
module led_clk (
    input board_clk,
    input switch,
    output reg [3:0] led);

    reg [32:0] counter;

    always @ (posedge board_clk) 
    begin
        if (switch == 1'b1)
            begin
                counter <= counter + 1;
                led[0] = counter[26];
            end
    end
endmodule
module led_clk (
    input board_clk,
    input switch,
    output reg [3:0] led);


    reg [32:0] counter;

    always @ (posedge board_clk) 
    begin
        if (switch == 1'b1)
            begin
                counter <= counter + 1;
                led[0] = counter[26];
            end
    end
endmodule