data/full_repos/permissive/104305228/code/ram.v
1: b'%Error: data/full_repos/permissive/104305228/code/ram.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/ram.v:15: Define or directive not defined: \'`ChipEnable\'\n  if (ce == `ChipEnable && re == `ReadEnable) begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ram.v:15: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n  if (ce == `ChipEnable && re == `ReadEnable) begin\n                        ^~\n%Error: data/full_repos/permissive/104305228/code/ram.v:15: Define or directive not defined: \'`ReadEnable\'\n  if (ce == `ChipEnable && re == `ReadEnable) begin\n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ram.v:24: Define or directive not defined: \'`ChipEnable\'\n  if (ce == `ChipEnable && we == `WriteEnable) begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ram.v:24: Define or directive not defined: \'`WriteEnable\'\n  if (ce == `ChipEnable && we == `WriteEnable) begin\n                                 ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module ram(
	input clk,
	input ce,
	input re,
	input we,
	input [31:0] read_addr,
	output reg[31:0] read_instr,
	input [31:0] write_addr,
	input [31:0] write_instr,
	input [3:0] write
);
	reg [31:0] instr_mem[0:1023];
	always @ (*) begin
		if (ce == `ChipEnable && re == `ReadEnable) begin
			read_instr <= instr_mem[read_addr[18:2]];
		end
		else begin
			read_instr <= 32'b0;
		end
	end

	always @ (negedge clk) begin
		if (ce == `ChipEnable && we == `WriteEnable) begin
			if (write[3] == 1'b1) begin
				instr_mem[write_addr[18:2]][31:24] <= write_instr[31:24];
			end
			if (write[2] == 1'b1) begin
				instr_mem[write_addr[18:2]][23:16] <= write_instr[23:16];
			end
			if (write[1] == 1'b1) begin
				instr_mem[write_addr[18:2]][15:8] <= write_instr[15:8];
			end
			if (write[0] == 1'b1) begin
				instr_mem[write_addr[18:2]][7:0] <= write_instr[7:0];
			end
		end
	end
endmodule
module ram(
	input clk,
	input ce,
	input re,
	input we,
	input [31:0] read_addr,
	output reg[31:0] read_instr,
	input [31:0] write_addr,
	input [31:0] write_instr,
	input [3:0] write
);

	reg [31:0] instr_mem[0:1023];
	always @ (*) begin
		if (ce == `ChipEnable && re == `ReadEnable) begin
			read_instr <= instr_mem[read_addr[18:2]];
		end
		else begin
			read_instr <= 32'b0;
		end
	end

	always @ (negedge clk) begin
		if (ce == `ChipEnable && we == `WriteEnable) begin
			if (write[3] == 1'b1) begin
				instr_mem[write_addr[18:2]][31:24] <= write_instr[31:24];
			end
			if (write[2] == 1'b1) begin
				instr_mem[write_addr[18:2]][23:16] <= write_instr[23:16];
			end
			if (write[1] == 1'b1) begin
				instr_mem[write_addr[18:2]][15:8] <= write_instr[15:8];
			end
			if (write[0] == 1'b1) begin
				instr_mem[write_addr[18:2]][7:0] <= write_instr[7:0];
			end
		end
	end
endmodule