data/full_repos/permissive/123304708/src/datapath/rf.v
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data/verilator_xmls/1b2dd20a-b14b-44ed-9418-c76f1c4897aa.xml
module rf(

    input RegWrite,
    
    input [4:0] ReadAddr1,
    input [4:0] ReadAddr2,
    input [4:0] WriteAddr,
    input [31:0] WriteData,

    output [31:0] ReadData1,
    output [31:0] ReadData2

);

    reg[31:0] register[31:0];
    integer i; 

    initial
    begin
        
        for(i = 0; i<32; i=i+1)
            register[i] = 0;
    end

    always @(*) begin
        if (WriteAddr!=0 && RegWrite) 
        begin

            register[WriteAddr] = WriteData;
        end
    end

    assign ReadData1 = register[ReadAddr1] ;
    assign ReadData2 = register[ReadAddr2] ;

endmodule
module rf(

    input RegWrite,
    
    input [4:0] ReadAddr1,
    input [4:0] ReadAddr2,
    input [4:0] WriteAddr,
    input [31:0] WriteData,

    output [31:0] ReadData1,
    output [31:0] ReadData2

);


    reg[31:0] register[31:0];
    integer i; 

    initial
    begin
        
        for(i = 0; i<32; i=i+1)
            register[i] = 0;
    end

    always @(*) begin
        if (WriteAddr!=0 && RegWrite) 
        begin

            register[WriteAddr] = WriteData;
        end
    end

    assign ReadData1 = register[ReadAddr1] ;
    assign ReadData2 = register[ReadAddr2] ;

endmodule