data/full_repos/permissive/143278/ivltests/pr2146620.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2146620.v:11: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                         : ... In instance bug\n      Value = i * 256 + j * 128;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module bug();

integer i;
integer j;

reg [7:0] Value;

initial begin
  for (i = 0; i < 2; i = i + 1) begin
    for (j = 0; j < 2; j = j + 1) begin
      Value = i * 256 + j * 128;
      $display(Value);
    end
  end
end

endmodule
module bug();


integer i;
integer j;

reg [7:0] Value;

initial begin
  for (i = 0; i < 2; i = i + 1) begin
    for (j = 0; j < 2; j = j + 1) begin
      Value = i * 256 + j * 128;
      $display(Value);
    end
  end
end

endmodule