data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v:40: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'inputData1\' generates 32 bits.\n                                                                                                                    : ... In instance arithmeticLogicUnit\n    AND: outputData = inputData1 && inputData2; \n                                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v:40: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'inputData2\' generates 32 bits.\n                                                                                                                    : ... In instance arithmeticLogicUnit\n    AND: outputData = inputData1 && inputData2; \n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v:40: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGAND generates 1 bits.\n                                                                                                                    : ... In instance arithmeticLogicUnit\n    AND: outputData = inputData1 && inputData2; \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v:41: Logical Operator LOGOR expects 1 bit on the LHS, but LHS\'s VARREF \'inputData1\' generates 32 bits.\n                                                                                                                    : ... In instance arithmeticLogicUnit\n    OR: outputData = inputData1 || inputData2; \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v:41: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s VARREF \'inputData2\' generates 32 bits.\n                                                                                                                    : ... In instance arithmeticLogicUnit\n    OR: outputData = inputData1 || inputData2; \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v:41: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGOR generates 1 bits.\n                                                                                                                    : ... In instance arithmeticLogicUnit\n    OR: outputData = inputData1 || inputData2; \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v:42: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'inputData1\' generates 32 bits.\n                                                                                                                    : ... In instance arithmeticLogicUnit\n    NOT: outputData = !inputData1; \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v:42: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGNOT generates 1 bits.\n                                                                                                                    : ... In instance arithmeticLogicUnit\n    NOT: outputData = !inputData1; \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v:43: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                                                                    : ... In instance arithmeticLogicUnit\n    EQ: outputData = $signed(inputData1) == $signed(inputData2); \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v:44: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s NEQ generates 1 bits.\n                                                                                                                    : ... In instance arithmeticLogicUnit\n    NEQ: outputData = $signed(inputData1) != $signed(inputData2); \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v:45: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                                                                    : ... In instance arithmeticLogicUnit\n    LT: outputData = $signed(inputData1) < $signed(inputData2); \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/arithmetic-logic-unit/arithmeticLogicUnit.v:46: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTES generates 1 bits.\n                                                                                                                    : ... In instance arithmeticLogicUnit\n    LTE: outputData = $signed(inputData1) <= $signed(inputData2); \n                    ^\n%Error: Exiting due to 12 warning(s)\n'
module arithmeticLogicUnit(
  opCode,
  inputData1,
  inputData2,
  outputData
);

parameter DATA_WIDTH = 32;
parameter OPCODE_WIDTH = 6;

input [OPCODE_WIDTH-1:0] opCode;
input [DATA_WIDTH-1:0] inputData1;
input [DATA_WIDTH-1:0] inputData2;
output reg [DATA_WIDTH-1:0] outputData;

localparam [OPCODE_WIDTH-1:0] ADD = 6'd0;
localparam [OPCODE_WIDTH-1:0] SUB = 6'd1;
localparam [OPCODE_WIDTH-1:0] MULT = 6'd2;
localparam [OPCODE_WIDTH-1:0] DIV = 6'd3;
localparam [OPCODE_WIDTH-1:0] MOD = 6'd4;
localparam [OPCODE_WIDTH-1:0] LSH = 6'd5;
localparam [OPCODE_WIDTH-1:0] RSH = 6'd6;
localparam [OPCODE_WIDTH-1:0] AND = 6'd7;
localparam [OPCODE_WIDTH-1:0] OR = 6'd8;
localparam [OPCODE_WIDTH-1:0] NOT = 6'd9;
localparam [OPCODE_WIDTH-1:0] EQ = 6'd10;
localparam [OPCODE_WIDTH-1:0] NEQ = 6'd11;
localparam [OPCODE_WIDTH-1:0] LT = 6'd12;
localparam [OPCODE_WIDTH-1:0] LTE = 6'd13;

always @ (opCode or inputData1 or inputData2) begin
  case (opCode)
    ADD: outputData = inputData1 + inputData2; 
    SUB: outputData = inputData1 - inputData2; 
    MULT: outputData = inputData1 * inputData2; 
    DIV: outputData = inputData1 / inputData2; 
    MOD: outputData = inputData1 % inputData2; 
    LSH: outputData = inputData1 << inputData2; 
    RSH: outputData = inputData1 >> inputData2; 
    AND: outputData = inputData1 && inputData2; 
    OR: outputData = inputData1 || inputData2; 
    NOT: outputData = !inputData1; 
    EQ: outputData = $signed(inputData1) == $signed(inputData2); 
    NEQ: outputData = $signed(inputData1) != $signed(inputData2); 
    LT: outputData = $signed(inputData1) < $signed(inputData2); 
    LTE: outputData = $signed(inputData1) <= $signed(inputData2); 
    default: outputData = inputData1 + inputData2;  
  endcase
end

endmodule
module arithmeticLogicUnit(
  opCode,
  inputData1,
  inputData2,
  outputData
);


parameter DATA_WIDTH = 32;
parameter OPCODE_WIDTH = 6;

input [OPCODE_WIDTH-1:0] opCode;
input [DATA_WIDTH-1:0] inputData1;
input [DATA_WIDTH-1:0] inputData2;
output reg [DATA_WIDTH-1:0] outputData;

localparam [OPCODE_WIDTH-1:0] ADD = 6'd0;
localparam [OPCODE_WIDTH-1:0] SUB = 6'd1;
localparam [OPCODE_WIDTH-1:0] MULT = 6'd2;
localparam [OPCODE_WIDTH-1:0] DIV = 6'd3;
localparam [OPCODE_WIDTH-1:0] MOD = 6'd4;
localparam [OPCODE_WIDTH-1:0] LSH = 6'd5;
localparam [OPCODE_WIDTH-1:0] RSH = 6'd6;
localparam [OPCODE_WIDTH-1:0] AND = 6'd7;
localparam [OPCODE_WIDTH-1:0] OR = 6'd8;
localparam [OPCODE_WIDTH-1:0] NOT = 6'd9;
localparam [OPCODE_WIDTH-1:0] EQ = 6'd10;
localparam [OPCODE_WIDTH-1:0] NEQ = 6'd11;
localparam [OPCODE_WIDTH-1:0] LT = 6'd12;
localparam [OPCODE_WIDTH-1:0] LTE = 6'd13;

always @ (opCode or inputData1 or inputData2) begin
  case (opCode)
    ADD: outputData = inputData1 + inputData2; 
    SUB: outputData = inputData1 - inputData2; 
    MULT: outputData = inputData1 * inputData2; 
    DIV: outputData = inputData1 / inputData2; 
    MOD: outputData = inputData1 % inputData2; 
    LSH: outputData = inputData1 << inputData2; 
    RSH: outputData = inputData1 >> inputData2; 
    AND: outputData = inputData1 && inputData2; 
    OR: outputData = inputData1 || inputData2; 
    NOT: outputData = !inputData1; 
    EQ: outputData = $signed(inputData1) == $signed(inputData2); 
    NEQ: outputData = $signed(inputData1) != $signed(inputData2); 
    LT: outputData = $signed(inputData1) < $signed(inputData2); 
    LTE: outputData = $signed(inputData1) <= $signed(inputData2); 
    default: outputData = inputData1 + inputData2;  
  endcase
end

endmodule