data/full_repos/permissive/196676072/rtl/ctrl.v
data/verilator_xmls/8f6fa575-a086-4924-b79a-364a0afc76a8.xml
module ctrl #(
    parameter           PROTOCOL = 8'hFF,
    parameter           REVISION = 8'hFF
) (
    input  wire         CLK,
    input  wire         RST_N,

    output wire         WB_CYC_O,
    output wire         WB_STB_O,
    output reg          WB_WE_O,
    output reg  [7:0]   WB_ADR_O,
    output reg  [7:0]   WB_DAT_O,
    input  wire [7:0]   WB_DAT_I,
    input  wire         WB_ACK_I,

    output reg  [5:0]   DEBUG

);






    `define REQ_READ                 1'b0
    `define REQ_WRITE                1'b1


    `define SPICR0                   8'h54
    `define SPICR1                   8'h55
    `define SPICR2                   8'h56
    `define SPIBR                    8'h57
    `define SPICSR                   8'h58
    `define SPITXDR                  8'h59
    `define SPISR                    8'h5A
    `define SPIRXDR                  8'h5B
    `define SPIIRQ                   8'h5C
    `define SPIIRQEN                 8'h5D


    `define SPICR1_CFG               8'h80
    `define SPICR2_CFG               8'h00
    `define SPITXDR_CFG              8'h00
    `define SPIIRQEN_CFG             8'h00


    `define SPI_CMD_PROTOCOL         8'hF0
    `define SPI_CMD_REVISION         8'hF1


    `define S_INIT                   5'h00
    `define S_SPICR1                 5'h01
    `define S_SPICR2                 5'h02
    `define S_WAIT_FOR_TIPN          5'h03
    `define S_RXDR_DISCARD1          5'h04
    `define S_RXDR_DISCARD2          5'h05
    `define S_T1_TXDR                5'h06
    `define S_WAIT_FOR_TIP           5'h07
    `define S_T2_TRDY                5'h08
    `define S_T2_TXDR                5'h09
    `define S_R1_RRDY                5'h0A
    `define S_R1_RXDR                5'h0B
    `define S_T3_TRDY                5'h0C
    `define S_T3_TXDR                5'h0D
    `define S_RN_RRDY                5'h0E
    `define S_RN_RXDR                5'h0F
    `define S_RN_PROCESS             5'h10
    `define S_TN_TRDY                5'h11
    `define S_TN_TXDR                5'h12


    reg       wb_cyc;


    reg [4:0] sm_state;


    reg [7:0] sm_spi_cmd;
    reg [7:0] sm_spi_count;





    assign #1.000 WB_STB_O = wb_cyc;
    assign #1.000 WB_CYC_O = wb_cyc;


    always @(posedge CLK) begin
        if (RST_N == 1'b0) begin
            sm_state        <= `S_INIT;


            wb_cyc          <= 1'b0;
            WB_WE_O         <= 1'b0;
            WB_ADR_O        <= 8'h00;
            WB_DAT_O        <= 8'h00;


            sm_spi_cmd      <= 8'h00;
            sm_spi_count    <= 8'h00;


            DEBUG           <= 6'h00;
        end
        else begin

            wb_cyc          <= 1'b0;
            WB_WE_O         <= `REQ_READ;


            if      ( (wb_cyc      == 1'b1) && (WB_ADR_O == `SPISR) &&
                      (WB_DAT_I[7] == 1'b1) && (WB_ACK_I == 1'b1) )
                DEBUG[5] <= 1'b1;

            else if ( (wb_cyc      == 1'b1) && (WB_ADR_O == `SPISR) &&
                      (WB_DAT_I[7] == 1'b0) && (WB_ACK_I == 1'b1) )
                DEBUG[5] <= 1'b0;


            DEBUG[4:0] <= sm_state;





            case (sm_state)





                `S_INIT: begin
                    sm_state <= `S_SPICR1;
                end





                `S_SPICR1: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPICR1;
                    WB_DAT_O <= `SPICR1_CFG;
                    WB_WE_O  <= `REQ_WRITE;
                    sm_state <= `S_SPICR1;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_SPICR2;
                    end
                end





                `S_SPICR2: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPICR2;
                    WB_DAT_O <= `SPICR2_CFG;
                    WB_WE_O  <= `REQ_WRITE;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_WAIT_FOR_TIPN;
                    end
                end





                `S_WAIT_FOR_TIPN: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;

                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[7] == 1'b0) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RXDR_DISCARD1;
                    end
                    else if (WB_ACK_I == 1'b1)  begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_WAIT_FOR_TIPN;
                    end
                end







                `S_RXDR_DISCARD1: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPIRXDR;
                    WB_WE_O  <= `REQ_READ;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RXDR_DISCARD2;
                    end
                end







                `S_RXDR_DISCARD2: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPIRXDR;
                    WB_WE_O  <= `REQ_READ;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T1_TXDR;
                    end
                end







                `S_T1_TXDR: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPITXDR;
                    WB_DAT_O <= 8'h00;
                    WB_WE_O  <= `REQ_WRITE;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_WAIT_FOR_TIP;
                    end
                end





                `S_WAIT_FOR_TIP: begin
                    sm_spi_count <= 8'h00;

                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;


                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[7] == 1'b1) &&
                         (WB_DAT_I[4] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T2_TXDR;
                    end

                    else if ( (WB_ACK_I    == 1'b1) &&
                              (WB_DAT_I[7] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T2_TRDY;
                    end

                    else if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_WAIT_FOR_TIP;
                    end
                end





                `S_T2_TRDY: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;

                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[4] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T2_TXDR;
                    end
                    else if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T2_TRDY;
                    end
                end







                `S_T2_TXDR: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPITXDR;
                    WB_DAT_O <= 8'h00;
                    WB_WE_O  <= `REQ_WRITE;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_R1_RRDY;
                    end
                end





                `S_R1_RRDY: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;


                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[7] == 1'b0) &&
                         (WB_DAT_I[3] == 1'b0) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_SPICR2;
                    end

                    else if ( (WB_ACK_I    == 1'b1) &&
                              (WB_DAT_I[3] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_R1_RXDR;
                    end

                    else if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_R1_RRDY;
                    end
                end







                `S_R1_RXDR: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPIRXDR;
                    WB_WE_O  <= `REQ_READ;

                    if (WB_ACK_I == 1'b1) begin
                        sm_spi_cmd <= WB_DAT_I;

                        wb_cyc     <= 1'b0;
                        WB_WE_O    <= `REQ_READ;
                        sm_state   <= `S_T3_TRDY;
                    end
                end





                `S_T3_TRDY: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;


                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[7] == 1'b0) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_SPICR2;
                    end

                    else if ( (WB_ACK_I    == 1'b1) &&
                              (WB_DAT_I[4] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T3_TXDR;
                    end

                    else if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T3_TRDY;
                    end
                end







                `S_T3_TXDR: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPITXDR;
                    WB_WE_O  <= `REQ_WRITE;

                    case (sm_spi_cmd)
                        `SPI_CMD_PROTOCOL: WB_DAT_O <= PROTOCOL;
                        `SPI_CMD_REVISION: WB_DAT_O <= REVISION;
                        default:           WB_DAT_O <= 8'h00;
                    endcase

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RN_RRDY;
                    end
                end





                `S_RN_RRDY: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;


                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[7] == 1'b0) &&
                         (WB_DAT_I[3] == 1'b0) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_SPICR2;
                    end

                    else if ( (WB_ACK_I    == 1'b1) &&
                              (WB_DAT_I[3] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RN_RXDR;
                    end

                    else if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RN_RRDY;
                    end
                end







                `S_RN_RXDR: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPIRXDR;
                    WB_WE_O  <= `REQ_READ;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RN_PROCESS;
                    end
                end





                `S_RN_PROCESS: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;
                    sm_state <= `S_TN_TRDY;

                    sm_spi_count <= sm_spi_count + 8'h01;
                end





                `S_TN_TRDY: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;

                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[7] == 1'b0) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_SPICR2;
                    end
                    else if ( (WB_ACK_I    == 1'b1) &&
                              (WB_DAT_I[4] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_TN_TXDR;
                    end

                    else if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_TN_TRDY;
                    end
                end





                `S_TN_TXDR: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPITXDR;
                    WB_DAT_O <= sm_spi_count;
                    WB_WE_O  <= `REQ_WRITE;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RN_RRDY;
                    end
                end





                default: begin
                    sm_state <= `S_INIT;
                end
            endcase
        end
    end

endmodule
module ctrl #(
    parameter           PROTOCOL = 8'hFF,
    parameter           REVISION = 8'hFF
) (
    input  wire         CLK,
    input  wire         RST_N,

    output wire         WB_CYC_O,
    output wire         WB_STB_O,
    output reg          WB_WE_O,
    output reg  [7:0]   WB_ADR_O,
    output reg  [7:0]   WB_DAT_O,
    input  wire [7:0]   WB_DAT_I,
    input  wire         WB_ACK_I,

    output reg  [5:0]   DEBUG

);







    `define REQ_READ                 1'b0
    `define REQ_WRITE                1'b1


    `define SPICR0                   8'h54
    `define SPICR1                   8'h55
    `define SPICR2                   8'h56
    `define SPIBR                    8'h57
    `define SPICSR                   8'h58
    `define SPITXDR                  8'h59
    `define SPISR                    8'h5A
    `define SPIRXDR                  8'h5B
    `define SPIIRQ                   8'h5C
    `define SPIIRQEN                 8'h5D


    `define SPICR1_CFG               8'h80
    `define SPICR2_CFG               8'h00
    `define SPITXDR_CFG              8'h00
    `define SPIIRQEN_CFG             8'h00


    `define SPI_CMD_PROTOCOL         8'hF0
    `define SPI_CMD_REVISION         8'hF1


    `define S_INIT                   5'h00
    `define S_SPICR1                 5'h01
    `define S_SPICR2                 5'h02
    `define S_WAIT_FOR_TIPN          5'h03
    `define S_RXDR_DISCARD1          5'h04
    `define S_RXDR_DISCARD2          5'h05
    `define S_T1_TXDR                5'h06
    `define S_WAIT_FOR_TIP           5'h07
    `define S_T2_TRDY                5'h08
    `define S_T2_TXDR                5'h09
    `define S_R1_RRDY                5'h0A
    `define S_R1_RXDR                5'h0B
    `define S_T3_TRDY                5'h0C
    `define S_T3_TXDR                5'h0D
    `define S_RN_RRDY                5'h0E
    `define S_RN_RXDR                5'h0F
    `define S_RN_PROCESS             5'h10
    `define S_TN_TRDY                5'h11
    `define S_TN_TXDR                5'h12


    reg       wb_cyc;


    reg [4:0] sm_state;


    reg [7:0] sm_spi_cmd;
    reg [7:0] sm_spi_count;





    assign #1.000 WB_STB_O = wb_cyc;
    assign #1.000 WB_CYC_O = wb_cyc;


    always @(posedge CLK) begin
        if (RST_N == 1'b0) begin
            sm_state        <= `S_INIT;


            wb_cyc          <= 1'b0;
            WB_WE_O         <= 1'b0;
            WB_ADR_O        <= 8'h00;
            WB_DAT_O        <= 8'h00;


            sm_spi_cmd      <= 8'h00;
            sm_spi_count    <= 8'h00;


            DEBUG           <= 6'h00;
        end
        else begin

            wb_cyc          <= 1'b0;
            WB_WE_O         <= `REQ_READ;


            if      ( (wb_cyc      == 1'b1) && (WB_ADR_O == `SPISR) &&
                      (WB_DAT_I[7] == 1'b1) && (WB_ACK_I == 1'b1) )
                DEBUG[5] <= 1'b1;

            else if ( (wb_cyc      == 1'b1) && (WB_ADR_O == `SPISR) &&
                      (WB_DAT_I[7] == 1'b0) && (WB_ACK_I == 1'b1) )
                DEBUG[5] <= 1'b0;


            DEBUG[4:0] <= sm_state;





            case (sm_state)





                `S_INIT: begin
                    sm_state <= `S_SPICR1;
                end





                `S_SPICR1: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPICR1;
                    WB_DAT_O <= `SPICR1_CFG;
                    WB_WE_O  <= `REQ_WRITE;
                    sm_state <= `S_SPICR1;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_SPICR2;
                    end
                end





                `S_SPICR2: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPICR2;
                    WB_DAT_O <= `SPICR2_CFG;
                    WB_WE_O  <= `REQ_WRITE;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_WAIT_FOR_TIPN;
                    end
                end





                `S_WAIT_FOR_TIPN: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;

                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[7] == 1'b0) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RXDR_DISCARD1;
                    end
                    else if (WB_ACK_I == 1'b1)  begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_WAIT_FOR_TIPN;
                    end
                end







                `S_RXDR_DISCARD1: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPIRXDR;
                    WB_WE_O  <= `REQ_READ;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RXDR_DISCARD2;
                    end
                end







                `S_RXDR_DISCARD2: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPIRXDR;
                    WB_WE_O  <= `REQ_READ;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T1_TXDR;
                    end
                end







                `S_T1_TXDR: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPITXDR;
                    WB_DAT_O <= 8'h00;
                    WB_WE_O  <= `REQ_WRITE;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_WAIT_FOR_TIP;
                    end
                end





                `S_WAIT_FOR_TIP: begin
                    sm_spi_count <= 8'h00;

                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;


                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[7] == 1'b1) &&
                         (WB_DAT_I[4] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T2_TXDR;
                    end

                    else if ( (WB_ACK_I    == 1'b1) &&
                              (WB_DAT_I[7] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T2_TRDY;
                    end

                    else if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_WAIT_FOR_TIP;
                    end
                end





                `S_T2_TRDY: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;

                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[4] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T2_TXDR;
                    end
                    else if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T2_TRDY;
                    end
                end







                `S_T2_TXDR: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPITXDR;
                    WB_DAT_O <= 8'h00;
                    WB_WE_O  <= `REQ_WRITE;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_R1_RRDY;
                    end
                end





                `S_R1_RRDY: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;


                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[7] == 1'b0) &&
                         (WB_DAT_I[3] == 1'b0) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_SPICR2;
                    end

                    else if ( (WB_ACK_I    == 1'b1) &&
                              (WB_DAT_I[3] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_R1_RXDR;
                    end

                    else if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_R1_RRDY;
                    end
                end







                `S_R1_RXDR: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPIRXDR;
                    WB_WE_O  <= `REQ_READ;

                    if (WB_ACK_I == 1'b1) begin
                        sm_spi_cmd <= WB_DAT_I;

                        wb_cyc     <= 1'b0;
                        WB_WE_O    <= `REQ_READ;
                        sm_state   <= `S_T3_TRDY;
                    end
                end





                `S_T3_TRDY: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;


                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[7] == 1'b0) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_SPICR2;
                    end

                    else if ( (WB_ACK_I    == 1'b1) &&
                              (WB_DAT_I[4] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T3_TXDR;
                    end

                    else if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_T3_TRDY;
                    end
                end







                `S_T3_TXDR: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPITXDR;
                    WB_WE_O  <= `REQ_WRITE;

                    case (sm_spi_cmd)
                        `SPI_CMD_PROTOCOL: WB_DAT_O <= PROTOCOL;
                        `SPI_CMD_REVISION: WB_DAT_O <= REVISION;
                        default:           WB_DAT_O <= 8'h00;
                    endcase

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RN_RRDY;
                    end
                end





                `S_RN_RRDY: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;


                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[7] == 1'b0) &&
                         (WB_DAT_I[3] == 1'b0) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_SPICR2;
                    end

                    else if ( (WB_ACK_I    == 1'b1) &&
                              (WB_DAT_I[3] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RN_RXDR;
                    end

                    else if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RN_RRDY;
                    end
                end







                `S_RN_RXDR: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPIRXDR;
                    WB_WE_O  <= `REQ_READ;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RN_PROCESS;
                    end
                end





                `S_RN_PROCESS: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;
                    sm_state <= `S_TN_TRDY;

                    sm_spi_count <= sm_spi_count + 8'h01;
                end





                `S_TN_TRDY: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPISR;
                    WB_WE_O  <= `REQ_READ;

                    if ( (WB_ACK_I    == 1'b1) &&
                         (WB_DAT_I[7] == 1'b0) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_SPICR2;
                    end
                    else if ( (WB_ACK_I    == 1'b1) &&
                              (WB_DAT_I[4] == 1'b1) ) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_TN_TXDR;
                    end

                    else if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_TN_TRDY;
                    end
                end





                `S_TN_TXDR: begin
                    wb_cyc   <= 1'b1;
                    WB_ADR_O <= `SPITXDR;
                    WB_DAT_O <= sm_spi_count;
                    WB_WE_O  <= `REQ_WRITE;

                    if (WB_ACK_I == 1'b1) begin
                        wb_cyc   <= 1'b0;
                        WB_WE_O  <= `REQ_READ;
                        sm_state <= `S_RN_RRDY;
                    end
                end





                default: begin
                    sm_state <= `S_INIT;
                end
            endcase
        end
    end

endmodule