data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Reciprocal/Reciprocal_Cascaded_tb.v
 line:70: before: "real"
1: b'%Error: Cannot find file containing module: Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Reciprocal/Reciprocal_Cascaded_tb.v\n%Error: Exiting due to 3 error(s)\n'
module Reciprocal_Cascaded_tb;


	parameter WL = 24;
	parameter LUT_bits = 10;
	parameter LUT_addWidth = 6;
	parameter ITERATION = 1;
	

	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din;


	wire [WL-1:0] dout;



	reg [WL-1:0] Testdata_vec_NR [`Testdata_Depth-1:0];

	reg [WL-1:0] Simu_Result_Matlab [`Testdata_Depth-1:0];
	

	real real_din, real_MATLAB_reuslt, real_Xilinx_result;
	real real_mul_1, real_mul_1_r, real_mul_2, real_mul_2_s;
	real real_out_0, real_mul_3, real_mul_3_r, real_mul_3_s;
	real real_mul_4, real_mul_4_s;


	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction



	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;



	Reciprocal_Cascaded_NR
	#(
		.WL(WL),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth),
		.ITERATION(ITERATION)
    )
	Fang_Reciprocal_cascaded_NR 
	(
		.CLK(CLK),
		.nRST(nRST),
		.CE(CE),
		.din(din),
		.dout(dout)
	 );



	integer count;
	real count_mismatched = 0;
	initial begin
	

		$readmemb("ini_input_binary_rec_NR_720.txt", Testdata_vec_NR);		
	

		$readmemb("LUT_rec_NR_iter1_720.txt", Reciprocal_Cascaded_tb.Fang_Reciprocal_cascaded_NR.LUT);
		$readmemb("result_rec_NR_720.txt", Simu_Result_Matlab);

		nRST = 0; CE = 0;
		@(posedge CLK); nRST = 1; CE = 1;
		
		for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
			din = Testdata_vec_NR[count];
		   $display("MATLAB: %f, Xilinx: %f", unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1), unsigned_fixedToFloat(dout, 1, WL-1));
			if (unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1)==unsigned_fixedToFloat(dout, 1, WL-1))


				$display("MATCHED");
			else begin
				count_mismatched = count_mismatched + 1;
				$display("MISMATCHED HERE <================= !!! ");
				$display("The NO.%d result is not matched, MATLAB: %b, Xilinx: %b ", count, Simu_Result_Matlab[count-1], dout);
			end
			@(posedge CLK);
			if (count==`Testdata_Depth) begin
				$display("Mismatched proporbility: %f", count_mismatched/`Testdata_Depth);
				$finish;
			end
		end

	end



	always @ din real_din = unsigned_fixedToFloat(din, 1, WL-1);
	



	always @ dout real_Xilinx_result = unsigned_fixedToFloat(dout, 1, WL-1);
	always @ Simu_Result_Matlab[count] real_MATLAB_reuslt = unsigned_fixedToFloat(Simu_Result_Matlab[count], 1, WL-1);
	
endmodule
module Reciprocal_Cascaded_tb;



	parameter WL = 24;
	parameter LUT_bits = 10;
	parameter LUT_addWidth = 6;
	parameter ITERATION = 1;
	

	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din;


	wire [WL-1:0] dout;



	reg [WL-1:0] Testdata_vec_NR [`Testdata_Depth-1:0];

	reg [WL-1:0] Simu_Result_Matlab [`Testdata_Depth-1:0];
	

	real real_din, real_MATLAB_reuslt, real_Xilinx_result;
	real real_mul_1, real_mul_1_r, real_mul_2, real_mul_2_s;
	real real_out_0, real_mul_3, real_mul_3_r, real_mul_3_s;
	real real_mul_4, real_mul_4_s;


	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction



	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;



	Reciprocal_Cascaded_NR
	#(
		.WL(WL),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth),
		.ITERATION(ITERATION)
    )
	Fang_Reciprocal_cascaded_NR 
	(
		.CLK(CLK),
		.nRST(nRST),
		.CE(CE),
		.din(din),
		.dout(dout)
	 );



	integer count;
	real count_mismatched = 0;
	initial begin
	

		$readmemb("ini_input_binary_rec_NR_720.txt", Testdata_vec_NR);		
	

		$readmemb("LUT_rec_NR_iter1_720.txt", Reciprocal_Cascaded_tb.Fang_Reciprocal_cascaded_NR.LUT);
		$readmemb("result_rec_NR_720.txt", Simu_Result_Matlab);

		nRST = 0; CE = 0;
		@(posedge CLK); nRST = 1; CE = 1;
		
		for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
			din = Testdata_vec_NR[count];
		   $display("MATLAB: %f, Xilinx: %f", unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1), unsigned_fixedToFloat(dout, 1, WL-1));
			if (unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1)==unsigned_fixedToFloat(dout, 1, WL-1))


				$display("MATCHED");
			else begin
				count_mismatched = count_mismatched + 1;
				$display("MISMATCHED HERE <================= !!! ");
				$display("The NO.%d result is not matched, MATLAB: %b, Xilinx: %b ", count, Simu_Result_Matlab[count-1], dout);
			end
			@(posedge CLK);
			if (count==`Testdata_Depth) begin
				$display("Mismatched proporbility: %f", count_mismatched/`Testdata_Depth);
				$finish;
			end
		end

	end



	always @ din real_din = unsigned_fixedToFloat(din, 1, WL-1);
	



	always @ dout real_Xilinx_result = unsigned_fixedToFloat(dout, 1, WL-1);
	always @ Simu_Result_Matlab[count] real_MATLAB_reuslt = unsigned_fixedToFloat(Simu_Result_Matlab[count], 1, WL-1);
	
endmodule