data/full_repos/permissive/156417892/hdl/InstructionDecode/RegFile/RegFile.v
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data/verilator_xmls/ce087556-972d-4df8-b503-2d7f8eb229ac.xml
module RegFile(rs,
                rt,
                rd,
                writedata,
                A,
                B,
                regwrite,
                clk);
   input [4:0] rs, rt, rd;
   input [31:0] writedata;
   input regwrite;
   input clk;
   
   output reg [31:0] A, B;
   
   reg [31:0] content[31:0];

   integer i;
   
initial begin
  A = 0;
  B = 0;
	for (i = 0; i < 32; i = i + 1)
      content[i] = i;
end

   always @(posedge clk) begin
      if (regwrite) begin
         if (rd != 0)
            content[rd] = writedata;
         A = content[rs];
         B = content[rt];
      end else begin
         A = content[rs];
         B = content[rt];
      end
   end
    
endmodule
module RegFile(rs,
                rt,
                rd,
                writedata,
                A,
                B,
                regwrite,
                clk);

   input [4:0] rs, rt, rd;
   input [31:0] writedata;
   input regwrite;
   input clk;
   
   output reg [31:0] A, B;
   
   reg [31:0] content[31:0];

   integer i;
   
initial begin
  A = 0;
  B = 0;
	for (i = 0; i < 32; i = i + 1)
      content[i] = i;
end

   always @(posedge clk) begin
      if (regwrite) begin
         if (rd != 0)
            content[rd] = writedata;
         A = content[rs];
         B = content[rt];
      end else begin
         A = content[rs];
         B = content[rt];
      end
   end
    
endmodule