data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_AdderTree.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_AdderTree.v:35: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_AdderTree.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #12;\n        ^\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_AdderTree.v:31: Cannot find file containing module: \'AdderTree_R\'\n    AdderTree_R uut( .clk(clk), .count_done(count_done), .result(result), .w1(w1), .w2(w2), .w3(w3), .w4(w4), .w5(w5),\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/AdderTree_R\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/AdderTree_R.v\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/AdderTree_R.sv\n             AdderTree_R\n             AdderTree_R.v\n             AdderTree_R.sv\n             obj_dir/AdderTree_R\n             obj_dir/AdderTree_R.v\n             obj_dir/AdderTree_R.sv\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_AdderTree.v:34: Cannot find file containing module: \'Counter\'\n    Counter counter( .clk(clk), .start(start), .reset(reset),   .done(count_done));\n    ^~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_AdderTree;
    reg signed [7:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16;
    reg clk;
    reg start;
    reg reset;
    wire count_done;
    wire signed [19:0] result;
    
    AdderTree_R uut( .clk(clk), .count_done(count_done), .result(result), .w1(w1), .w2(w2), .w3(w3), .w4(w4), .w5(w5),
    .w6(w6), .w7(w7), .w8(w8), .w9(w9), .w10(w10), .w11(w11), .w12(w12), .w13(w13), .w14(w14), .w15(w15), .w16(w16));
    
    Counter counter( .clk(clk), .start(start), .reset(reset),.done(count_done));
    always #5 clk = ~clk;
    
    initial begin
        clk = 0;
        reset = 1;
        start = 0;
        #12;
        start = 1;
        reset = 0;
        w1 = 1;
        w2 = 1;
        w3 = 1;
        w4 = 1;
        w5 = 1;
        w6 = 1;
        w7 = 1;
        w8 = 1;
        w9 = 1;
        w10 = 1;
        w11 = 1;
        w12 = 1;
        w13 = 1;
        w14 = 1;
        w15 = 1;
        w16 = 1;
    end

endmodule
module TB_AdderTree;

    reg signed [7:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16;
    reg clk;
    reg start;
    reg reset;
    wire count_done;
    wire signed [19:0] result;
    
    AdderTree_R uut( .clk(clk), .count_done(count_done), .result(result), .w1(w1), .w2(w2), .w3(w3), .w4(w4), .w5(w5),
    .w6(w6), .w7(w7), .w8(w8), .w9(w9), .w10(w10), .w11(w11), .w12(w12), .w13(w13), .w14(w14), .w15(w15), .w16(w16));
    
    Counter counter( .clk(clk), .start(start), .reset(reset),.done(count_done));
    always #5 clk = ~clk;
    
    initial begin
        clk = 0;
        reset = 1;
        start = 0;
        #12;
        start = 1;
        reset = 0;
        w1 = 1;
        w2 = 1;
        w3 = 1;
        w4 = 1;
        w5 = 1;
        w6 = 1;
        w7 = 1;
        w8 = 1;
        w9 = 1;
        w10 = 1;
        w11 = 1;
        w12 = 1;
        w13 = 1;
        w14 = 1;
        w15 = 1;
        w16 = 1;
    end

endmodule