data/full_repos/permissive/142505464/modules/wb_leds/rtl/verilog/wb_leds.v
 line:75: before: ";"
1: b"%Error: data/full_repos/permissive/142505464/modules/wb_leds/rtl/verilog/wb_leds.v:58: Cannot find file containing module: 'wb_leds_csr'\nwb_leds_csr wb_leds_csr (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/142505464/modules/wb_leds/rtl/verilog,data/full_repos/permissive/142505464/wb_leds_csr\n             data/full_repos/permissive/142505464/modules/wb_leds/rtl/verilog,data/full_repos/permissive/142505464/wb_leds_csr.v\n             data/full_repos/permissive/142505464/modules/wb_leds/rtl/verilog,data/full_repos/permissive/142505464/wb_leds_csr.sv\n             wb_leds_csr\n             wb_leds_csr.v\n             wb_leds_csr.sv\n             obj_dir/wb_leds_csr\n             obj_dir/wb_leds_csr.v\n             obj_dir/wb_leds_csr.sv\n%Error: Exiting due to 1 error(s)\n"
module wb_leds
(

    input               clk_i,
    input               rst_n_i,


    input  [31:0]       wb_adr_i,
    input  [31:0]       wb_dat_i,
    input  [3:0]        wb_sel_i,
    input               wb_we_i,
    input               wb_cyc_i,
    input               wb_stb_i,
    output [31:0]       wb_dat_o,
    output              wb_ack_o,
    output              wb_err_o,
    output              wb_rty_o,
    output              wb_stall_o,


    output [31:0]       leds_o
);

wb_leds_csr wb_leds_csr (
    .rst_n_i            (rst_n_i),
    .clk_i              (clk_i),
    .wb_dat_i           (wb_dat_i),
    .wb_dat_o           (wb_dat_o),
    .wb_cyc_i           (wb_cyc_i),
    .wb_sel_i           (wb_sel_i),
    .wb_stb_i           (wb_stb_i),
    .wb_we_i            (wb_we_i),
    .wb_ack_o           (wb_ack_o),
    .wb_err_o           (wb_err_o),
    .wb_rty_o           (wb_rty_o),
    .wb_stall_o         (wb_stall_o),
    .leds_o             (leds_o)
);

endmodule
module wb_leds
(

    input               clk_i,
    input               rst_n_i,


    input  [31:0]       wb_adr_i,
    input  [31:0]       wb_dat_i,
    input  [3:0]        wb_sel_i,
    input               wb_we_i,
    input               wb_cyc_i,
    input               wb_stb_i,
    output [31:0]       wb_dat_o,
    output              wb_ack_o,
    output              wb_err_o,
    output              wb_rty_o,
    output              wb_stall_o,


    output [31:0]       leds_o
);


wb_leds_csr wb_leds_csr (
    .rst_n_i            (rst_n_i),
    .clk_i              (clk_i),
    .wb_dat_i           (wb_dat_i),
    .wb_dat_o           (wb_dat_o),
    .wb_cyc_i           (wb_cyc_i),
    .wb_sel_i           (wb_sel_i),
    .wb_stb_i           (wb_stb_i),
    .wb_we_i            (wb_we_i),
    .wb_ack_o           (wb_ack_o),
    .wb_err_o           (wb_err_o),
    .wb_rty_o           (wb_rty_o),
    .wb_stall_o         (wb_stall_o),
    .leds_o             (leds_o)
);

endmodule