data/full_repos/permissive/152986713/ice40/digits10.v
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1: b'%Error: data/full_repos/permissive/152986713/ice40/digits10.v:5: Cannot find include file: hvsync_generator.v\n`include "hvsync_generator.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/152986713/ice40,data/full_repos/permissive/152986713/hvsync_generator.v\n             data/full_repos/permissive/152986713/ice40,data/full_repos/permissive/152986713/hvsync_generator.v.v\n             data/full_repos/permissive/152986713/ice40,data/full_repos/permissive/152986713/hvsync_generator.v.sv\n             hvsync_generator.v\n             hvsync_generator.v.v\n             hvsync_generator.v.sv\n             obj_dir/hvsync_generator.v\n             obj_dir/hvsync_generator.v.v\n             obj_dir/hvsync_generator.v.sv\n%Error: Exiting due to 1 error(s)\n'
module test_numbers_top(clk, reset, hsync, vsync, rgb);
  
  input clk, reset;
  output hsync, vsync;
  output [2:0] rgb;

  wire display_on;
  wire [8:0] hpos;
  wire [8:0] vpos;
  
  hvsync_generator hvsync_gen(
    .clk(clk),
    .reset(reset),
    .hsync(hsync),
    .vsync(vsync),
    .display_on(display_on),
    .hpos(hpos),
    .vpos(vpos)
  );
  
  wire [3:0] digit = hpos[7:4];
  wire [2:0] xofs = hpos[3:1];
  wire [2:0] yofs = vpos[3:1];
  wire [4:0] bits;
  
  digits10_array numbers(
    .digit(digit),
    .yofs(yofs),
    .bits(bits)
  );

  wire r = display_on && 0;
  wire g = display_on && bits[xofs ^ 3'b111];
  wire b = display_on && 0;
  assign rgb = {b,g,r};

endmodule
module test_numbers_top(clk, reset, hsync, vsync, rgb);

  
  input clk, reset;
  output hsync, vsync;
  output [2:0] rgb;

  wire display_on;
  wire [8:0] hpos;
  wire [8:0] vpos;
  
  hvsync_generator hvsync_gen(
    .clk(clk),
    .reset(reset),
    .hsync(hsync),
    .vsync(vsync),
    .display_on(display_on),
    .hpos(hpos),
    .vpos(vpos)
  );
  
  wire [3:0] digit = hpos[7:4];
  wire [2:0] xofs = hpos[3:1];
  wire [2:0] yofs = vpos[3:1];
  wire [4:0] bits;
  
  digits10_array numbers(
    .digit(digit),
    .yofs(yofs),
    .bits(bits)
  );

  wire r = display_on && 0;
  wire g = display_on && bits[xofs ^ 3'b111];
  wire b = display_on && 0;
  assign rgb = {b,g,r};

endmodule