data/full_repos/permissive/119715647/sim/gameFunct/TetrisTestTop_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/gameFunct/TetrisTestTop_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/gameFunct/TetrisTestTop_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/gameFunct/TetrisTestTop_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/gameFunct/TetrisTestTop_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #40;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/gameFunct/TetrisTestTop_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #40;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/gameFunct/TetrisTestTop_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #40;\n    ^\n%Error: data/full_repos/permissive/119715647/sim/gameFunct/TetrisTestTop_tb.v:12: Cannot find file containing module: \'TetrisTestTop\'\n  TetrisTestTop DUT_TTT(start, stacked, clk, rstBtn, stopBtn, rLED, doneLED, outputStream);\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119715647/sim/gameFunct,data/full_repos/permissive/119715647/TetrisTestTop\n             data/full_repos/permissive/119715647/sim/gameFunct,data/full_repos/permissive/119715647/TetrisTestTop.v\n             data/full_repos/permissive/119715647/sim/gameFunct,data/full_repos/permissive/119715647/TetrisTestTop.sv\n             TetrisTestTop\n             TetrisTestTop.v\n             TetrisTestTop.sv\n             obj_dir/TetrisTestTop\n             obj_dir/TetrisTestTop.v\n             obj_dir/TetrisTestTop.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TetrisTestTop_tb();
  reg start;
  reg stacked;
  reg clk, rstBtn;
  reg stopBtn;
  wire rLED;
  wire doneLED;
  wire [63:0] outputStream;

  TetrisTestTop DUT_TTT(start, stacked, clk, rstBtn, stopBtn, rLED, doneLED, outputStream);

  always begin
    clk = 1;
    #10;
    clk = 0;
    #10;
  end

  initial begin
    #5;
    #40;
    rstBtn = 0;
    #40;
    rstBtn = 1;
    #40;
  end


endmodule
module TetrisTestTop_tb();

  reg start;
  reg stacked;
  reg clk, rstBtn;
  reg stopBtn;
  wire rLED;
  wire doneLED;
  wire [63:0] outputStream;

  TetrisTestTop DUT_TTT(start, stacked, clk, rstBtn, stopBtn, rLED, doneLED, outputStream);

  always begin
    clk = 1;
    #10;
    clk = 0;
    #10;
  end

  initial begin
    #5;
    #40;
    rstBtn = 0;
    #40;
    rstBtn = 1;
    #40;
  end


endmodule