data/full_repos/permissive/193669196/hwrot/rtl/hwrot_synth.v
 line:90: before: "["
1: b'%Warning-IMPLICIT: data/full_repos/permissive/193669196/hwrot/rtl/hwrot_synth.v:122: Signal definition not found, creating implicitly: \'uartm_tx\'\n assign core_out = uartm_tx;\n                   ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/193669196/hwrot/rtl/hwrot_synth.v:123: Signal definition not found, creating implicitly: \'uartm_rx\'\n                                                                                   : ... Suggested alternative: \'uartm_tx\'\n assign uartm_rx = core_in[3];\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/193669196/hwrot/rtl/hwrot_synth.v:431: Signal definition not found, creating implicitly: \'wdtimer_irq\'\n                                                                                   : ... Suggested alternative: \'timerA_irq\'\n assign nporeset_sync     = nporeset_sync2 & nporeset_sync1 & nporeset_sync0 & nporeset & ~wdtimer_irq;\n                                                                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193669196/hwrot/rtl/hwrot_synth.v:103: Cannot find file containing module: \'uartm\'\nuartm u_uartm_inst (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/193669196/hwrot/rtl,data/full_repos/permissive/193669196/uartm\n             data/full_repos/permissive/193669196/hwrot/rtl,data/full_repos/permissive/193669196/uartm.v\n             data/full_repos/permissive/193669196/hwrot/rtl,data/full_repos/permissive/193669196/uartm.sv\n             uartm\n             uartm.v\n             uartm.sv\n             obj_dir/uartm\n             obj_dir/uartm.v\n             obj_dir/uartm.sv\n%Error: data/full_repos/permissive/193669196/hwrot/rtl/hwrot_synth.v:132: Cannot find file containing module: \'CORTEXM0DS_wrap\'\n    CORTEXM0DS_wrap u_cortexm0_wrap_inst (\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193669196/hwrot/rtl/hwrot_synth.v:160: Cannot find file containing module: \'ahb_ic_wrap\'\nahb_ic_wrap #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/193669196/hwrot/rtl/hwrot_synth.v:215: Cannot find file containing module: \'pram\'\npram u_pram_inst (  \n^~~~\n%Error: data/full_repos/permissive/193669196/hwrot/rtl/hwrot_synth.v:266: Cannot find file containing module: \'sram_wrap\'\n    sram_wrap #(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/193669196/hwrot/rtl/hwrot_synth.v:284: Cannot find file containing module: \'gpcfg\'\ngpcfg #(\n^~~~~\n%Error: data/full_repos/permissive/193669196/hwrot/rtl/hwrot_synth.v:367: Cannot find file containing module: \'timer\'\ntimer u_timer_inst (\n^~~~~\n%Error: Exiting due to 7 error(s), 3 warning(s)\n'
module hwrot (
  input   wire [3  :0]  core_in,
  output  wire          core_out
);






  localparam NUM_CORES          = 65;
  localparam NUM_MASTERS        = 1 + NUM_CORES;
  localparam NUM_SRAMS          = 5;
  localparam NUM_SLAVES         = NUM_SRAMS + 2;

  localparam NUM_16K_MEM        = 16;

  localparam NUM_APU_POLICY     = 16;
  localparam NUM_DPU_POLICY     = 16;

  localparam PRAM_S_ID          = 0;
  localparam GPCFG_S_ID         = NUM_SLAVES-1;

  localparam PRAM_BASE          = 32'h0000_0000;
  localparam SYSRAM0_BASE       = 32'h2000_0000;
  localparam SYSRAM1_BASE       = 32'h2100_0000;
  localparam SYSRAM2_BASE       = 32'h2200_0000;
  localparam SYSRAM3_BASE       = 32'h2300_0000;
  localparam GPCFG_BASE         = 32'h4002_0000;

  localparam GPCFG_BASE_MASK    = 32'h0000_FFFF;
  localparam SYSRAM0_BASE_MASK  = 32'h0001_FFFF;
  localparam PRAM_BASE_MASK     = 32'h0000_FFFF;

  localparam UARTM_M_ID         = 0;

wire        hclk;
wire        nreset;
wire        nporeset;

wire        nporeset_sync;
wire        nporeset_sync_wdt;
reg         nporeset_sync0;
reg         nporeset_sync1;
reg         nporeset_sync2;

wire        nreset_sync;
reg         nreset_sync0;
reg         nreset_sync1;
reg         nreset_sync2;

wire [1:0]  htrans_m0;
wire [31:0] haddr_m0;
wire [2:0]  hsize_m0;
wire [31:0] hwdata_m0;
wire [31:0] hrdata_m0;
wire [31:0] hrdata_gpcfg;
wire [31:0] hrdata_sram_wrap;

wire [31:0] spaddr[NUM_CORES-1 :0];
wire [31:0] resetaddr[NUM_CORES-1 :0];
wire [31:0] nmiaddr[NUM_CORES-1 :0];
wire [31:0] faultaddr[NUM_CORES-1 :0];
wire [31:0] irqaddr[NUM_CORES-1 :0];
wire [31:0] gpcfg_reg[63:17];
wire [31:0] i_val;

wire [ 1:0] htrans_m[NUM_MASTERS-1 :0];
wire [31:0] haddr_m[NUM_MASTERS-1 :0];
wire [31:0] haddr_m_loc[NUM_MASTERS-1 :0];
wire [ 2:0] hsize_m[NUM_MASTERS-1 :0];
wire [31:0] hmaster_m[NUM_MASTERS-1 :0];
wire [ 3:0] hprot_m[NUM_MASTERS-1 :0];
wire [31:0] hwdata_m[NUM_MASTERS-1 :0];
wire        hwrite_m[NUM_MASTERS-1 :0];
wire [31:0] hrdata_m[NUM_MASTERS-1 :0];
wire        hready_m[NUM_MASTERS-1 :0];
wire        hresp_m[NUM_MASTERS-1 :0];
wire        hsel_s[NUM_SLAVES-1 :0];
wire [31:0] haddr_s[NUM_SLAVES-1 :0];
wire [31:0] hmaster_s[NUM_SLAVES-1 :0];
wire [ 2:0] hsize_s[NUM_SLAVES-1 :0];
wire        hwrite_s[NUM_SLAVES-1 :0];
wire [31:0] hwdata_s[NUM_SLAVES-1 :0];
reg [31:0] hrdata_s[NUM_SLAVES-1 :0];
reg        hready_s[NUM_SLAVES-1 :0];
reg        hresp_s[NUM_SLAVES-1 :0];

`ifndef NOTRANSMON
wire [NUM_APU_POLICY-1 :0][31:0] apumid [NUM_SRAMS :0];
wire [NUM_APU_POLICY-1 :0][31:0] apuaddr[NUM_SRAMS :0];
wire [NUM_APU_POLICY-1 :0][31:0] apumask[NUM_SRAMS :0];
wire [NUM_APU_POLICY-1 :0][31:0] apuperm[NUM_SRAMS :0];
wire [NUM_DPU_POLICY-1 :0][31:0] dpumid [NUM_SRAMS :0];
wire [NUM_DPU_POLICY-1 :0][31:0] dpuaddr[NUM_SRAMS :0];
wire [NUM_DPU_POLICY-1 :0][31:0] dpudata[NUM_SRAMS :0];
wire [NUM_DPU_POLICY-1 :0][31:0] dpumask[NUM_SRAMS :0];
wire [NUM_DPU_POLICY-1 :0][31:0] dpuamask[NUM_SRAMS :0];
`endif


assign hprot_m[UARTM_M_ID] = 4'b0;
uartm u_uartm_inst (
  .hclk        (hclk),
  .hresetn     (nporeset_sync),
  .haddr       (haddr_m[UARTM_M_ID]),
  .hsize       (hsize_m[UARTM_M_ID]),
  .htrans      (htrans_m[UARTM_M_ID]),
  .hwdata      (hwdata_m[UARTM_M_ID]),
  .hwrite      (hwrite_m[UARTM_M_ID]),
  .hrdata      (hrdata_m[UARTM_M_ID]),
  .hready      (hready_m[UARTM_M_ID]),
  .hresp       (hresp_m[UARTM_M_ID]),
  .uartm_baud  (gpcfg_reg[17]),
  .uartm_ctl   (gpcfg_reg[18]),
  .TX          (uartm_tx),
  .RX          (uartm_rx)
);

 assign hmaster_m[0] = 32'h0;

 assign core_out = uartm_tx;
 assign uartm_rx = core_in[3];


wire wdtimer_nmi, timerC_irq, timerB_irq, timerA_irq;

genvar i;

generate
  for (i=1; i<=NUM_CORES; i=i+1) begin
    CORTEXM0DS_wrap u_cortexm0_wrap_inst (
      .HCLK           (hclk),
      .HRESETn        (nreset_sync),
      .HADDR          (haddr_m[i]),
      .HBURST         (),
      .HMASTLOCK      (),
      .HPROT          (hprot_m[i]),
      .HSIZE          (hsize_m[i]),
      .HTRANS         (htrans_m[i]),
      .HWDATA         (hwdata_m[i]),
      .HWRITE         (hwrite_m[i]),
      .HRDATA         (hrdata_m[i][31:0]),
      .HREADY         (hready_m[i]),
      .HRESP          (hresp_m[i]),
      .NMI            (wdtimer_nmi),
      .IRQ            ({7'b0, gpcfg_reg[41][i], gpcfg_reg[40][i], gpcfg_reg[39][i], 2'b0, timerC_irq, timerB_irq, timerA_irq, 1'b0}),
      .TXEV           (),
      .RXEV           (gpcfg_reg[39][10]),
      .LOCKUP         (),
      .SYSRESETREQ    (),
      .SLEEPING       ()
    );
    assign hmaster_m[i] = i;
  end
endgenerate



ahb_ic_wrap #(
  .NUM_APU_POLICY  (NUM_APU_POLICY),
  .NUM_DPU_POLICY  (NUM_DPU_POLICY),
  .NUM_CORES       (NUM_CORES),
  .NUM_SRAMS       (NUM_SRAMS),
  .NUM_SLAVES      (NUM_SLAVES),
  .NUM_MASTERS     (NUM_MASTERS),
  .SLAVE_BASE_MASK ( {GPCFG_BASE_MASK,
                       SYSRAM0_BASE_MASK,
                       PRAM_BASE_MASK}),
  .SLAVE_BASE  ( {GPCFG_BASE,
                  SYSRAM0_BASE,
                  PRAM_BASE})
  ) u_ahb_ic_wrap_inst (  
  .hclk      (hclk),
  .htrans_m  (htrans_m),
  .hmaster_m (hmaster_m),
  .haddr_m   (haddr_m),
  .hsize_m   (hsize_m),
  .hprot_m   (hprot_m),
  .hwdata_m  (hwdata_m),
  .hwrite_m  (hwrite_m),
  .hrdata_m  (hrdata_m),
  .hready_m  (hready_m),
  .hresp_m   (hresp_m),
  .hsel_s    (hsel_s),
  .hmaster_s (hmaster_s),
  .haddr_s   (haddr_s),
  .hsize_s   (hsize_s),
  .hwrite_s  (hwrite_s),
  .hwdata_s  (hwdata_s),
  .hrdata_s  (hrdata_s),
  .hready_s  (hready_s),
  .hresp_s   (hresp_s),
`ifndef NOTRANSMON
  .apumid    (apumid),
  .apuaddr   (apuaddr),
  .apumask   (apumask),
  .apuperm   (apuperm),
  .dpumid    (dpumid),
  .dpuaddr   (dpuaddr),
  .dpudata   (dpudata),
  .dpumask   (dpumask),
  .dpuamask   (dpuamask),
`endif
  .hresetn   (nporeset_sync)

);

wire [31:0] hrdata_pram [NUM_CORES-1 :0];
wire [NUM_CORES-1 :0] hready_pram ;
wire [NUM_CORES-1 :0] hresp_pram;

generate
  for (i=1; i<=NUM_CORES; i=i+1) begin
pram u_pram_inst (  
  .hclk               (hclk),
  .hresetn            (nporeset_sync),
  .hsel               (hsel_s[PRAM_S_ID] && (hmaster_s[PRAM_S_ID] == i)),
  .haddr              (haddr_s[PRAM_S_ID]),
  .hsize              (hsize_s[PRAM_S_ID]),
  .hwrite             (hwrite_s[PRAM_S_ID]),
  .hrdata             (hrdata_pram[i-1]),
  .hready             (hready_pram[i-1]),
  .hresp              (hresp_pram[i-1]),
  .sp_addr            (spaddr[0]),
  .reset_addr         (resetaddr[0]),
  .nmi_addr           (nmiaddr[0]),
  .fault_addr         (faultaddr[0]),
  .irq0_addr          (irqaddr[0]),
  .irq1_addr          (irqaddr[0]),
  .irq2_addr          (irqaddr[0]),
  .irq3_addr          (irqaddr[0]),
  .irq4_addr          (irqaddr[0]),
  .irq5_addr          (irqaddr[0]),
  .irq6_addr          (irqaddr[0]),
  .irq7_addr          (irqaddr[0]),
  .irq8_addr          (irqaddr[0]),
  .irq9_addr          (irqaddr[0]),
  .irq10_addr         (irqaddr[0]),
  .irq11_addr         (irqaddr[0]),
  .irq12_addr         (irqaddr[0]),
  .irq13_addr         (irqaddr[0]),
  .irq14_addr         (irqaddr[0]),
  .irq15_addr         (irqaddr[0])
);

  end
endgenerate

integer k;
 always@* begin
        hrdata_s[PRAM_S_ID]   = 32'b0;
        hresp_s[PRAM_S_ID]    = 1'b0;
        hready_s[PRAM_S_ID]   = 1'b1;
        for (k=0; k<NUM_CORES; k=k+1) begin
          hrdata_s[PRAM_S_ID] = hrdata_pram[k] | hrdata_s[PRAM_S_ID];
          hresp_s[PRAM_S_ID]  = hresp_pram[k]  | hresp_s[PRAM_S_ID];
          hready_s[PRAM_S_ID] = hready_pram[k] & hready_s[PRAM_S_ID];
        end
 end



generate
  for (i=1; i<(NUM_SRAMS+1); i=i+1) begin
    sram_wrap #(
      .NUM_16K_MEM (NUM_16K_MEM)
    ) u_sram_wrap_inst (  
      .hclk       (hclk),
      .hresetn    (nporeset_sync),
      .hsel       (hsel_s[i]),
      .haddr      (haddr_s[i]),
      .hsize      (hsize_s[i]),
      .hwdata     (hwdata_s[i]),
      .hwrite     (hwrite_s[i]),
      .hrdata     (hrdata_s[i]),
      .hready     (hready_s[i]),
      .hresp      (hresp_s[i])
    );
  end
endgenerate


gpcfg #(
  .NUM_SRAMS       (NUM_SRAMS),
  .NUM_CORES       (NUM_CORES),
  .NUM_APU_POLICY  (NUM_APU_POLICY),
  .NUM_DPU_POLICY  (NUM_DPU_POLICY)
) u_gpcfg_inst (
  .hclk           (hclk),
  .hsel           (hsel_s[GPCFG_S_ID]),
  .hmaster        (hmaster_s[GPCFG_S_ID]),
  .haddr          (haddr_s[GPCFG_S_ID]),
  .hsize          (hsize_s[GPCFG_S_ID]),
  .hwdata         (hwdata_s[GPCFG_S_ID]),
  .hwrite         (hwrite_s[GPCFG_S_ID]),
  .hrdata         (hrdata_s[GPCFG_S_ID]),
  .hready         (hready_s[GPCFG_S_ID]),
  .hresp          (hresp_s[GPCFG_S_ID]),
  .spaddr         (spaddr),
  .resetaddr      (resetaddr),
  .nmiaddr        (nmiaddr),
  .faultaddr      (faultaddr),
  .irqaddr        (irqaddr),
  .gpcfg17_reg    (gpcfg_reg[17]),
  .gpcfg18_reg    (gpcfg_reg[18]),
  .gpcfg19_reg    (gpcfg_reg[19]),
  .gpcfg20_reg    (gpcfg_reg[20]),
  .gpcfg21_reg    (gpcfg_reg[21]),
  .gpcfg22_reg    (gpcfg_reg[22]),
  .gpcfg23_reg    (gpcfg_reg[23]),
  .gpcfg24_reg    (gpcfg_reg[24]),
  .gpcfg25_reg    (gpcfg_reg[25]),
  .gpcfg26_reg    (gpcfg_reg[26]),
  .gpcfg27_reg    (gpcfg_reg[27]),
  .gpcfg28_reg    (gpcfg_reg[28]),
  .gpcfg29_reg    (gpcfg_reg[29]),
  .gpcfg30_reg    (gpcfg_reg[30]),
  .gpcfg31_reg    (gpcfg_reg[31]),
  .gpcfg32_reg    (gpcfg_reg[32]),
  .gpcfg33_reg    (gpcfg_reg[33]),
  .gpcfg34_reg    (gpcfg_reg[34]),
  .gpcfg35_reg    (gpcfg_reg[35]),
  .gpcfg36_reg    (gpcfg_reg[36]),
  .uarts_rx_data  (32'b0),
  .gpcfg38_reg    (gpcfg_reg[38]),
  .gpcfg39_reg    (gpcfg_reg[39]),
  .gpcfg40_reg    (gpcfg_reg[40]),
  .gpcfg41_reg    (gpcfg_reg[41]),
  .gpcfg42_reg    (gpcfg_reg[42]),
  .gpcfg43_reg    (gpcfg_reg[43]),
  .gpcfg44_reg    (gpcfg_reg[44]),
  .gpcfg45_reg    (gpcfg_reg[45]),
  .gpcfg46_reg    (gpcfg_reg[46]),
  .gpcfg47_reg    (gpcfg_reg[47]),
  .gpcfg48_reg    (gpcfg_reg[48]),
  .gpcfg49_reg    (gpcfg_reg[49]),
  .gpcfg50_reg    (gpcfg_reg[50]),
  .gpcfg51_reg    (gpcfg_reg[51]),
  .gpcfg52_reg    (gpcfg_reg[52]),
  .gpcfg53_reg    (gpcfg_reg[53]),
  .gpcfg54_reg    (gpcfg_reg[54]),
  .gpcfg55_reg    (gpcfg_reg[55]),
  .gpcfg56_reg    (gpcfg_reg[56]),
  .gpcfg57_reg    (gpcfg_reg[57]),
  .gpcfg58_reg    (gpcfg_reg[58]),
  .gpcfg59_reg    (gpcfg_reg[59]),
  .gpcfg60_reg    (gpcfg_reg[60]),
  .gpcfg61_reg    (gpcfg_reg[61]),
  .gpcfg62_reg    (gpcfg_reg[62]),
  .gpcfg63_reg    (gpcfg_reg[63]),
`ifndef NOTRANSMON
  .apumid         (apumid),
  .apuaddr        (apuaddr),
  .apumask        (apumask),
  .apuperm        (apuperm),
  .dpumid         (dpumid),
  .dpuaddr        (dpuaddr),
  .dpudata        (dpudata),
  .dpumask        (dpumask),
  .dpuamask        (dpuamask),
`endif
  .hresetn        (nporeset_sync)
);


timer u_timer_inst (
  .hclk          (hclk),
  .hresetn       (nporeset_sync),
  .wdt_rstn      (nporeset_sync_wdt),
  .timerA_cfg    (gpcfg_reg[28]),
  .timerB_cfg    (gpcfg_reg[29]),
  .timerC_cfg    (gpcfg_reg[30]),
  .wdtimer_cfg   (gpcfg_reg[32]),
  .wdtimer_cfg2  (gpcfg_reg[33]),
  .timerA_en     (gpcfg_reg[27][0]),
  .timerB_en     (gpcfg_reg[27][8]),
  .timerC_en     (gpcfg_reg[27][16]),
  .wdtimer_en    (gpcfg_reg[31][0]),
  .timerA_rst    (gpcfg_reg[27][1]),
  .timerB_rst    (gpcfg_reg[27][9]),
  .timerC_rst    (gpcfg_reg[27][17]),
  .wdtimer_rst   (gpcfg_reg[31][1]),
  .pwm_val_tim0  (gpcfg_reg[40]),
  .pwm_val_tim1  (gpcfg_reg[41]),
  .timerA_irq    (timerA_irq),
  .timerB_irq    (timerB_irq),
  .timerC_irq    (timerC_irq),
  .wdtimer_irq   (wdtimer_irq),
  .wdtimer_nmi   (wdtimer_nmi),
  .pwm_out       ()
);













    assign nporeset    = core_in[0]; 
    assign nreset      = core_in[1]; 

    `ifdef FPGA_SYNTH
       clock_div u_clk_div4_inst ( 
         .CLK_IN1(core_in[2]),
         .CLK_OUT1(hclk)
       );
    `else
      assign hclk        = core_in[2]; 
    `endif

 always @ (posedge hclk or negedge nporeset) begin
   if (nporeset == 1'b0) begin
     nporeset_sync0 <= 1'b0;
     nporeset_sync1 <= 1'b0;
     nporeset_sync2 <= 1'b0;
   end
   else begin
     nporeset_sync0 <= 1'b1;
     nporeset_sync1 <= nporeset_sync0;
     nporeset_sync2 <= nporeset_sync1;
   end
 end

 assign nporeset_sync     = nporeset_sync2 & nporeset_sync1 & nporeset_sync0 & nporeset & ~wdtimer_irq;
 assign nporeset_sync_wdt = nporeset_sync2 & nporeset_sync1 & nporeset_sync0 & nporeset;

 always @ (posedge hclk or negedge nreset) begin
   if (nreset == 1'b0) begin
     nreset_sync0 <= 1'b0;
     nreset_sync1 <= 1'b0;
     nreset_sync2 <= 1'b0;
   end
   else begin
     nreset_sync0 <= 1'b1;
     nreset_sync1 <= nreset_sync0;
     nreset_sync2 <= nreset_sync1;
   end
 end

 assign nreset_sync = nreset_sync2 & nreset_sync1 & nreset_sync0 & nreset & nporeset_sync;

endmodule
module hwrot (
  input   wire [3  :0]  core_in,
  output  wire          core_out
);







  localparam NUM_CORES          = 65;
  localparam NUM_MASTERS        = 1 + NUM_CORES;
  localparam NUM_SRAMS          = 5;
  localparam NUM_SLAVES         = NUM_SRAMS + 2;

  localparam NUM_16K_MEM        = 16;

  localparam NUM_APU_POLICY     = 16;
  localparam NUM_DPU_POLICY     = 16;

  localparam PRAM_S_ID          = 0;
  localparam GPCFG_S_ID         = NUM_SLAVES-1;

  localparam PRAM_BASE          = 32'h0000_0000;
  localparam SYSRAM0_BASE       = 32'h2000_0000;
  localparam SYSRAM1_BASE       = 32'h2100_0000;
  localparam SYSRAM2_BASE       = 32'h2200_0000;
  localparam SYSRAM3_BASE       = 32'h2300_0000;
  localparam GPCFG_BASE         = 32'h4002_0000;

  localparam GPCFG_BASE_MASK    = 32'h0000_FFFF;
  localparam SYSRAM0_BASE_MASK  = 32'h0001_FFFF;
  localparam PRAM_BASE_MASK     = 32'h0000_FFFF;

  localparam UARTM_M_ID         = 0;

wire        hclk;
wire        nreset;
wire        nporeset;

wire        nporeset_sync;
wire        nporeset_sync_wdt;
reg         nporeset_sync0;
reg         nporeset_sync1;
reg         nporeset_sync2;

wire        nreset_sync;
reg         nreset_sync0;
reg         nreset_sync1;
reg         nreset_sync2;

wire [1:0]  htrans_m0;
wire [31:0] haddr_m0;
wire [2:0]  hsize_m0;
wire [31:0] hwdata_m0;
wire [31:0] hrdata_m0;
wire [31:0] hrdata_gpcfg;
wire [31:0] hrdata_sram_wrap;

wire [31:0] spaddr[NUM_CORES-1 :0];
wire [31:0] resetaddr[NUM_CORES-1 :0];
wire [31:0] nmiaddr[NUM_CORES-1 :0];
wire [31:0] faultaddr[NUM_CORES-1 :0];
wire [31:0] irqaddr[NUM_CORES-1 :0];
wire [31:0] gpcfg_reg[63:17];
wire [31:0] i_val;

wire [ 1:0] htrans_m[NUM_MASTERS-1 :0];
wire [31:0] haddr_m[NUM_MASTERS-1 :0];
wire [31:0] haddr_m_loc[NUM_MASTERS-1 :0];
wire [ 2:0] hsize_m[NUM_MASTERS-1 :0];
wire [31:0] hmaster_m[NUM_MASTERS-1 :0];
wire [ 3:0] hprot_m[NUM_MASTERS-1 :0];
wire [31:0] hwdata_m[NUM_MASTERS-1 :0];
wire        hwrite_m[NUM_MASTERS-1 :0];
wire [31:0] hrdata_m[NUM_MASTERS-1 :0];
wire        hready_m[NUM_MASTERS-1 :0];
wire        hresp_m[NUM_MASTERS-1 :0];
wire        hsel_s[NUM_SLAVES-1 :0];
wire [31:0] haddr_s[NUM_SLAVES-1 :0];
wire [31:0] hmaster_s[NUM_SLAVES-1 :0];
wire [ 2:0] hsize_s[NUM_SLAVES-1 :0];
wire        hwrite_s[NUM_SLAVES-1 :0];
wire [31:0] hwdata_s[NUM_SLAVES-1 :0];
reg [31:0] hrdata_s[NUM_SLAVES-1 :0];
reg        hready_s[NUM_SLAVES-1 :0];
reg        hresp_s[NUM_SLAVES-1 :0];

`ifndef NOTRANSMON
wire [NUM_APU_POLICY-1 :0][31:0] apumid [NUM_SRAMS :0];
wire [NUM_APU_POLICY-1 :0][31:0] apuaddr[NUM_SRAMS :0];
wire [NUM_APU_POLICY-1 :0][31:0] apumask[NUM_SRAMS :0];
wire [NUM_APU_POLICY-1 :0][31:0] apuperm[NUM_SRAMS :0];
wire [NUM_DPU_POLICY-1 :0][31:0] dpumid [NUM_SRAMS :0];
wire [NUM_DPU_POLICY-1 :0][31:0] dpuaddr[NUM_SRAMS :0];
wire [NUM_DPU_POLICY-1 :0][31:0] dpudata[NUM_SRAMS :0];
wire [NUM_DPU_POLICY-1 :0][31:0] dpumask[NUM_SRAMS :0];
wire [NUM_DPU_POLICY-1 :0][31:0] dpuamask[NUM_SRAMS :0];
`endif


assign hprot_m[UARTM_M_ID] = 4'b0;
uartm u_uartm_inst (
  .hclk        (hclk),
  .hresetn     (nporeset_sync),
  .haddr       (haddr_m[UARTM_M_ID]),
  .hsize       (hsize_m[UARTM_M_ID]),
  .htrans      (htrans_m[UARTM_M_ID]),
  .hwdata      (hwdata_m[UARTM_M_ID]),
  .hwrite      (hwrite_m[UARTM_M_ID]),
  .hrdata      (hrdata_m[UARTM_M_ID]),
  .hready      (hready_m[UARTM_M_ID]),
  .hresp       (hresp_m[UARTM_M_ID]),
  .uartm_baud  (gpcfg_reg[17]),
  .uartm_ctl   (gpcfg_reg[18]),
  .TX          (uartm_tx),
  .RX          (uartm_rx)
);

 assign hmaster_m[0] = 32'h0;

 assign core_out = uartm_tx;
 assign uartm_rx = core_in[3];


wire wdtimer_nmi, timerC_irq, timerB_irq, timerA_irq;

genvar i;

generate
  for (i=1; i<=NUM_CORES; i=i+1) begin
    CORTEXM0DS_wrap u_cortexm0_wrap_inst (
      .HCLK           (hclk),
      .HRESETn        (nreset_sync),
      .HADDR          (haddr_m[i]),
      .HBURST         (),
      .HMASTLOCK      (),
      .HPROT          (hprot_m[i]),
      .HSIZE          (hsize_m[i]),
      .HTRANS         (htrans_m[i]),
      .HWDATA         (hwdata_m[i]),
      .HWRITE         (hwrite_m[i]),
      .HRDATA         (hrdata_m[i][31:0]),
      .HREADY         (hready_m[i]),
      .HRESP          (hresp_m[i]),
      .NMI            (wdtimer_nmi),
      .IRQ            ({7'b0, gpcfg_reg[41][i], gpcfg_reg[40][i], gpcfg_reg[39][i], 2'b0, timerC_irq, timerB_irq, timerA_irq, 1'b0}),
      .TXEV           (),
      .RXEV           (gpcfg_reg[39][10]),
      .LOCKUP         (),
      .SYSRESETREQ    (),
      .SLEEPING       ()
    );
    assign hmaster_m[i] = i;
  end
endgenerate



ahb_ic_wrap #(
  .NUM_APU_POLICY  (NUM_APU_POLICY),
  .NUM_DPU_POLICY  (NUM_DPU_POLICY),
  .NUM_CORES       (NUM_CORES),
  .NUM_SRAMS       (NUM_SRAMS),
  .NUM_SLAVES      (NUM_SLAVES),
  .NUM_MASTERS     (NUM_MASTERS),
  .SLAVE_BASE_MASK ( {GPCFG_BASE_MASK,
                       SYSRAM0_BASE_MASK,
                       PRAM_BASE_MASK}),
  .SLAVE_BASE  ( {GPCFG_BASE,
                  SYSRAM0_BASE,
                  PRAM_BASE})
  ) u_ahb_ic_wrap_inst (  
  .hclk      (hclk),
  .htrans_m  (htrans_m),
  .hmaster_m (hmaster_m),
  .haddr_m   (haddr_m),
  .hsize_m   (hsize_m),
  .hprot_m   (hprot_m),
  .hwdata_m  (hwdata_m),
  .hwrite_m  (hwrite_m),
  .hrdata_m  (hrdata_m),
  .hready_m  (hready_m),
  .hresp_m   (hresp_m),
  .hsel_s    (hsel_s),
  .hmaster_s (hmaster_s),
  .haddr_s   (haddr_s),
  .hsize_s   (hsize_s),
  .hwrite_s  (hwrite_s),
  .hwdata_s  (hwdata_s),
  .hrdata_s  (hrdata_s),
  .hready_s  (hready_s),
  .hresp_s   (hresp_s),
`ifndef NOTRANSMON
  .apumid    (apumid),
  .apuaddr   (apuaddr),
  .apumask   (apumask),
  .apuperm   (apuperm),
  .dpumid    (dpumid),
  .dpuaddr   (dpuaddr),
  .dpudata   (dpudata),
  .dpumask   (dpumask),
  .dpuamask   (dpuamask),
`endif
  .hresetn   (nporeset_sync)

);

wire [31:0] hrdata_pram [NUM_CORES-1 :0];
wire [NUM_CORES-1 :0] hready_pram ;
wire [NUM_CORES-1 :0] hresp_pram;

generate
  for (i=1; i<=NUM_CORES; i=i+1) begin
pram u_pram_inst (  
  .hclk               (hclk),
  .hresetn            (nporeset_sync),
  .hsel               (hsel_s[PRAM_S_ID] && (hmaster_s[PRAM_S_ID] == i)),
  .haddr              (haddr_s[PRAM_S_ID]),
  .hsize              (hsize_s[PRAM_S_ID]),
  .hwrite             (hwrite_s[PRAM_S_ID]),
  .hrdata             (hrdata_pram[i-1]),
  .hready             (hready_pram[i-1]),
  .hresp              (hresp_pram[i-1]),
  .sp_addr            (spaddr[0]),
  .reset_addr         (resetaddr[0]),
  .nmi_addr           (nmiaddr[0]),
  .fault_addr         (faultaddr[0]),
  .irq0_addr          (irqaddr[0]),
  .irq1_addr          (irqaddr[0]),
  .irq2_addr          (irqaddr[0]),
  .irq3_addr          (irqaddr[0]),
  .irq4_addr          (irqaddr[0]),
  .irq5_addr          (irqaddr[0]),
  .irq6_addr          (irqaddr[0]),
  .irq7_addr          (irqaddr[0]),
  .irq8_addr          (irqaddr[0]),
  .irq9_addr          (irqaddr[0]),
  .irq10_addr         (irqaddr[0]),
  .irq11_addr         (irqaddr[0]),
  .irq12_addr         (irqaddr[0]),
  .irq13_addr         (irqaddr[0]),
  .irq14_addr         (irqaddr[0]),
  .irq15_addr         (irqaddr[0])
);

  end
endgenerate

integer k;
 always@* begin
        hrdata_s[PRAM_S_ID]   = 32'b0;
        hresp_s[PRAM_S_ID]    = 1'b0;
        hready_s[PRAM_S_ID]   = 1'b1;
        for (k=0; k<NUM_CORES; k=k+1) begin
          hrdata_s[PRAM_S_ID] = hrdata_pram[k] | hrdata_s[PRAM_S_ID];
          hresp_s[PRAM_S_ID]  = hresp_pram[k]  | hresp_s[PRAM_S_ID];
          hready_s[PRAM_S_ID] = hready_pram[k] & hready_s[PRAM_S_ID];
        end
 end



generate
  for (i=1; i<(NUM_SRAMS+1); i=i+1) begin
    sram_wrap #(
      .NUM_16K_MEM (NUM_16K_MEM)
    ) u_sram_wrap_inst (  
      .hclk       (hclk),
      .hresetn    (nporeset_sync),
      .hsel       (hsel_s[i]),
      .haddr      (haddr_s[i]),
      .hsize      (hsize_s[i]),
      .hwdata     (hwdata_s[i]),
      .hwrite     (hwrite_s[i]),
      .hrdata     (hrdata_s[i]),
      .hready     (hready_s[i]),
      .hresp      (hresp_s[i])
    );
  end
endgenerate


gpcfg #(
  .NUM_SRAMS       (NUM_SRAMS),
  .NUM_CORES       (NUM_CORES),
  .NUM_APU_POLICY  (NUM_APU_POLICY),
  .NUM_DPU_POLICY  (NUM_DPU_POLICY)
) u_gpcfg_inst (
  .hclk           (hclk),
  .hsel           (hsel_s[GPCFG_S_ID]),
  .hmaster        (hmaster_s[GPCFG_S_ID]),
  .haddr          (haddr_s[GPCFG_S_ID]),
  .hsize          (hsize_s[GPCFG_S_ID]),
  .hwdata         (hwdata_s[GPCFG_S_ID]),
  .hwrite         (hwrite_s[GPCFG_S_ID]),
  .hrdata         (hrdata_s[GPCFG_S_ID]),
  .hready         (hready_s[GPCFG_S_ID]),
  .hresp          (hresp_s[GPCFG_S_ID]),
  .spaddr         (spaddr),
  .resetaddr      (resetaddr),
  .nmiaddr        (nmiaddr),
  .faultaddr      (faultaddr),
  .irqaddr        (irqaddr),
  .gpcfg17_reg    (gpcfg_reg[17]),
  .gpcfg18_reg    (gpcfg_reg[18]),
  .gpcfg19_reg    (gpcfg_reg[19]),
  .gpcfg20_reg    (gpcfg_reg[20]),
  .gpcfg21_reg    (gpcfg_reg[21]),
  .gpcfg22_reg    (gpcfg_reg[22]),
  .gpcfg23_reg    (gpcfg_reg[23]),
  .gpcfg24_reg    (gpcfg_reg[24]),
  .gpcfg25_reg    (gpcfg_reg[25]),
  .gpcfg26_reg    (gpcfg_reg[26]),
  .gpcfg27_reg    (gpcfg_reg[27]),
  .gpcfg28_reg    (gpcfg_reg[28]),
  .gpcfg29_reg    (gpcfg_reg[29]),
  .gpcfg30_reg    (gpcfg_reg[30]),
  .gpcfg31_reg    (gpcfg_reg[31]),
  .gpcfg32_reg    (gpcfg_reg[32]),
  .gpcfg33_reg    (gpcfg_reg[33]),
  .gpcfg34_reg    (gpcfg_reg[34]),
  .gpcfg35_reg    (gpcfg_reg[35]),
  .gpcfg36_reg    (gpcfg_reg[36]),
  .uarts_rx_data  (32'b0),
  .gpcfg38_reg    (gpcfg_reg[38]),
  .gpcfg39_reg    (gpcfg_reg[39]),
  .gpcfg40_reg    (gpcfg_reg[40]),
  .gpcfg41_reg    (gpcfg_reg[41]),
  .gpcfg42_reg    (gpcfg_reg[42]),
  .gpcfg43_reg    (gpcfg_reg[43]),
  .gpcfg44_reg    (gpcfg_reg[44]),
  .gpcfg45_reg    (gpcfg_reg[45]),
  .gpcfg46_reg    (gpcfg_reg[46]),
  .gpcfg47_reg    (gpcfg_reg[47]),
  .gpcfg48_reg    (gpcfg_reg[48]),
  .gpcfg49_reg    (gpcfg_reg[49]),
  .gpcfg50_reg    (gpcfg_reg[50]),
  .gpcfg51_reg    (gpcfg_reg[51]),
  .gpcfg52_reg    (gpcfg_reg[52]),
  .gpcfg53_reg    (gpcfg_reg[53]),
  .gpcfg54_reg    (gpcfg_reg[54]),
  .gpcfg55_reg    (gpcfg_reg[55]),
  .gpcfg56_reg    (gpcfg_reg[56]),
  .gpcfg57_reg    (gpcfg_reg[57]),
  .gpcfg58_reg    (gpcfg_reg[58]),
  .gpcfg59_reg    (gpcfg_reg[59]),
  .gpcfg60_reg    (gpcfg_reg[60]),
  .gpcfg61_reg    (gpcfg_reg[61]),
  .gpcfg62_reg    (gpcfg_reg[62]),
  .gpcfg63_reg    (gpcfg_reg[63]),
`ifndef NOTRANSMON
  .apumid         (apumid),
  .apuaddr        (apuaddr),
  .apumask        (apumask),
  .apuperm        (apuperm),
  .dpumid         (dpumid),
  .dpuaddr        (dpuaddr),
  .dpudata        (dpudata),
  .dpumask        (dpumask),
  .dpuamask        (dpuamask),
`endif
  .hresetn        (nporeset_sync)
);


timer u_timer_inst (
  .hclk          (hclk),
  .hresetn       (nporeset_sync),
  .wdt_rstn      (nporeset_sync_wdt),
  .timerA_cfg    (gpcfg_reg[28]),
  .timerB_cfg    (gpcfg_reg[29]),
  .timerC_cfg    (gpcfg_reg[30]),
  .wdtimer_cfg   (gpcfg_reg[32]),
  .wdtimer_cfg2  (gpcfg_reg[33]),
  .timerA_en     (gpcfg_reg[27][0]),
  .timerB_en     (gpcfg_reg[27][8]),
  .timerC_en     (gpcfg_reg[27][16]),
  .wdtimer_en    (gpcfg_reg[31][0]),
  .timerA_rst    (gpcfg_reg[27][1]),
  .timerB_rst    (gpcfg_reg[27][9]),
  .timerC_rst    (gpcfg_reg[27][17]),
  .wdtimer_rst   (gpcfg_reg[31][1]),
  .pwm_val_tim0  (gpcfg_reg[40]),
  .pwm_val_tim1  (gpcfg_reg[41]),
  .timerA_irq    (timerA_irq),
  .timerB_irq    (timerB_irq),
  .timerC_irq    (timerC_irq),
  .wdtimer_irq   (wdtimer_irq),
  .wdtimer_nmi   (wdtimer_nmi),
  .pwm_out       ()
);













    assign nporeset    = core_in[0]; 
    assign nreset      = core_in[1]; 

    `ifdef FPGA_SYNTH
       clock_div u_clk_div4_inst ( 
         .CLK_IN1(core_in[2]),
         .CLK_OUT1(hclk)
       );
    `else
      assign hclk        = core_in[2]; 
    `endif

 always @ (posedge hclk or negedge nporeset) begin
   if (nporeset == 1'b0) begin
     nporeset_sync0 <= 1'b0;
     nporeset_sync1 <= 1'b0;
     nporeset_sync2 <= 1'b0;
   end
   else begin
     nporeset_sync0 <= 1'b1;
     nporeset_sync1 <= nporeset_sync0;
     nporeset_sync2 <= nporeset_sync1;
   end
 end

 assign nporeset_sync     = nporeset_sync2 & nporeset_sync1 & nporeset_sync0 & nporeset & ~wdtimer_irq;
 assign nporeset_sync_wdt = nporeset_sync2 & nporeset_sync1 & nporeset_sync0 & nporeset;

 always @ (posedge hclk or negedge nreset) begin
   if (nreset == 1'b0) begin
     nreset_sync0 <= 1'b0;
     nreset_sync1 <= 1'b0;
     nreset_sync2 <= 1'b0;
   end
   else begin
     nreset_sync0 <= 1'b1;
     nreset_sync1 <= nreset_sync0;
     nreset_sync2 <= nreset_sync1;
   end
 end

 assign nreset_sync = nreset_sync2 & nreset_sync1 & nreset_sync0 & nreset & nporeset_sync;

endmodule