data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:2: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/180413071/nonpipelined/sources/tests,data/full_repos/permissive/180413071/constants.vh\n             data/full_repos/permissive/180413071/nonpipelined/sources/tests,data/full_repos/permissive/180413071/constants.vh.v\n             data/full_repos/permissive/180413071/nonpipelined/sources/tests,data/full_repos/permissive/180413071/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:7: Define or directive not defined: \'`INSTR_LEN\'\n    reg  [`INSTR_LEN-1:0] instruction;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:8: Define or directive not defined: \'`WORD\'\n    reg  [`WORD-1:0] write_data;\n          ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:10: Define or directive not defined: \'`WORD\'\n    wire [`WORD-1:0] extended_instruction;\n          ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:12: Define or directive not defined: \'`WORD\'\n    wire [`WORD-1:0] read_data1, read_data2;\n          ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:26: Define or directive not defined: \'`WORD\'\n        write_data <= `WORD\'d20;\n                      ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:27: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:27: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:31: Define or directive not defined: \'`WORD\'\n        write_data <= `WORD\'d30;\n                      ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:32: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:32: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:36: Define or directive not defined: \'`WORD\'\n        write_data <= `WORD\'d0;\n                      ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:37: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:37: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:41: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:41: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:45: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:45: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:49: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:49: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:53: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:53: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:57: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:57: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:61: Define or directive not defined: \'`WORD\'\n        write_data <= `WORD\'d30;\n                      ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:62: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:62: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:66: Define or directive not defined: \'`WORD\'\n        write_data <= `WORD\'d16;\n                      ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:67: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/Decode_tb.sv:67: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: Exiting due to 30 error(s)\n'
module Decode_tb;

    wire read_clk, write_clk;
    reg  [`INSTR_LEN-1:0] instruction;
    reg  [`WORD-1:0] write_data;
    
    wire [`WORD-1:0] extended_instruction;
    wire [10:0] opcode;
    wire [`WORD-1:0] read_data1, read_data2;
    
    wire unconditional_branch, branch, mem_read, mem_to_reg, mem_write, alu_src, reg_write;
    wire [1:0] alu_op;
    
    oscillator clk_gen(read_clk);
    
    delay #(2) write_clk_gen(read_clk, write_clk);
    
    Decode DECODE(.*);
    
    initial begin

        instruction <= 32'hF84402C9;
        write_data <= `WORD'd20;
        #`CYCLE;
        

        instruction <= 32'h8B09026A;
        write_data <= `WORD'd30;
        #`CYCLE;
        

        instruction <= 32'hCB0A028B;
        write_data <= `WORD'd0;
        #`CYCLE;
        

        instruction <= 32'hF80602CB;
        #`CYCLE;
        

        instruction <= 32'hB4FFFF6B;
        #`CYCLE;
        

        instruction <= 32'hB4000109;
        #`CYCLE;
        

        instruction <= 32'h14000040;
        #`CYCLE;
        

        instruction <= 32'h17FFFFC9;
        #`CYCLE;
        

        instruction <= 32'hAA150149;
        write_data <= `WORD'd30;
        #`CYCLE;
        

        instruction <= 32'h8A0A02C9;
        write_data <= `WORD'd16;
        #`CYCLE;
        
        $finish;
    end

endmodule
module Decode_tb;


    wire read_clk, write_clk;
    reg  [`INSTR_LEN-1:0] instruction;
    reg  [`WORD-1:0] write_data;
    
    wire [`WORD-1:0] extended_instruction;
    wire [10:0] opcode;
    wire [`WORD-1:0] read_data1, read_data2;
    
    wire unconditional_branch, branch, mem_read, mem_to_reg, mem_write, alu_src, reg_write;
    wire [1:0] alu_op;
    
    oscillator clk_gen(read_clk);
    
    delay #(2) write_clk_gen(read_clk, write_clk);
    
    Decode DECODE(.*);
    
    initial begin

        instruction <= 32'hF84402C9;
        write_data <= `WORD'd20;
        #`CYCLE;
        

        instruction <= 32'h8B09026A;
        write_data <= `WORD'd30;
        #`CYCLE;
        

        instruction <= 32'hCB0A028B;
        write_data <= `WORD'd0;
        #`CYCLE;
        

        instruction <= 32'hF80602CB;
        #`CYCLE;
        

        instruction <= 32'hB4FFFF6B;
        #`CYCLE;
        

        instruction <= 32'hB4000109;
        #`CYCLE;
        

        instruction <= 32'h14000040;
        #`CYCLE;
        

        instruction <= 32'h17FFFFC9;
        #`CYCLE;
        

        instruction <= 32'hAA150149;
        write_data <= `WORD'd30;
        #`CYCLE;
        

        instruction <= 32'h8A0A02C9;
        write_data <= `WORD'd16;
        #`CYCLE;
        
        $finish;
    end

endmodule