data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v
1: b'%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:51: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v.v\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:53: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:105: Define or directive not defined: \'`OR1200_ICLS\'\nreg [`OR1200_ICLS-1:0]     cnt;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:148: Define or directive not defined: \'`OR1200_RST_EVENT\'\n   always @(posedge clk or `OR1200_RST_EVENT rst) begin\n                           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:149: Define or directive not defined: \'`OR1200_RST_VALUE\'\n      if (rst == `OR1200_RST_VALUE) begin\n                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:149: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (rst == `OR1200_RST_VALUE) begin\n                                  ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:154: Define or directive not defined: \'`OR1200_ICLS\'\n  cnt <=  `OR1200_ICLS\'d0;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:159: syntax error, unexpected else\n      else\n      ^~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:181: syntax error, unexpected \'[\', expecting IDENTIFIER\n        saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];\n                    ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:181: Define or directive not defined: \'`OR1200_ICTAGL\'\n        saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];\n                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:181: Define or directive not defined: \'`OR1200_ICTAGL\'\n        saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];\n                                                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:191: syntax error, unexpected <=, expecting IDENTIFIER\n  state <=  2\'d0;\n        ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:198: syntax error, unexpected <=, expecting IDENTIFIER\n  state <=  2\'d2;\n        ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:199: Define or directive not defined: \'`OR1200_ICLS\'\n  saved_addr_r[`OR1200_ICLS-1:2] \n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:200: Define or directive not defined: \'`OR1200_ICLS\'\n    <= saved_addr_r[`OR1200_ICLS-1:2] + 1;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:202: Define or directive not defined: \'`OR1200_ICLS\'\n  cnt <= ((1 << `OR1200_ICLS) - (2 * 4));\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:209: syntax error, unexpected <=, expecting IDENTIFIER\n  state <=  2\'d0;\n        ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:216: syntax error, unexpected <=, expecting IDENTIFIER\n  saved_addr_r <=  start_addr;\n               ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:220: syntax error, unexpected <=, expecting IDENTIFIER\n        hitmiss_eval <=  1\'b0;\n                     ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:223: syntax error, unexpected <=, expecting IDENTIFIER\n        last_eval_miss <= 1;  \n                       ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:237: Define or directive not defined: \'`OR1200_ICLS\'\n  cnt <=  cnt - `OR1200_ICLS\'d4;\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:238: Define or directive not defined: \'`OR1200_ICLS\'\n  saved_addr_r[`OR1200_ICLS-1:2] \n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_ic_fsm.v:239: Define or directive not defined: \'`OR1200_ICLS\'\n    <= saved_addr_r[`OR1200_ICLS-1:2] + 1;\n                    ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module or1200_ic_fsm(

	clk, rst,


	ic_en, icqmem_cycstb_i, icqmem_ci_i,
	tagcomp_miss, 
	biudata_valid, biudata_error, 
        start_addr, saved_addr,
	icram_we, tag_we,
        biu_read, 
        first_hit_ack, first_miss_ack, first_miss_err,
	burst
);




input				clk;
input				rst;
input				ic_en;
input				icqmem_cycstb_i;
input				icqmem_ci_i;
input				tagcomp_miss;
input				biudata_valid;
input				biudata_error;
input	[31:0]			start_addr;
output	[31:0]			saved_addr;
output	[3:0]			icram_we;
output				biu_read;
output				first_hit_ack;
output				first_miss_ack;
output				first_miss_err;
output				burst;
output				tag_we;




reg	[31:0]			saved_addr_r;
reg	[1:0]			state;
reg [`OR1200_ICLS-1:0]    	cnt;
reg				hitmiss_eval;
reg				load;
reg				cache_inhibit;
reg 				last_eval_miss;
   



   assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
   assign tag_we = biu_read & biudata_valid & !cache_inhibit;




   assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);


   assign saved_addr = saved_addr_r;


   assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & 
			  !tagcomp_miss & !cache_inhibit;




   assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid &
			   ~first_hit_ack;
   


   assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;




   assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & 
		  !cache_inhibit | (state == `OR1200_ICFSM_LREFILL3);




   always @(posedge clk or `OR1200_RST_EVENT rst) begin
      if (rst == `OR1200_RST_VALUE) begin
	 state <=  `OR1200_ICFSM_IDLE;
	 saved_addr_r <=  32'b0;
	 hitmiss_eval <=  1'b0;
	 load <=  1'b0;
	 cnt <=  `OR1200_ICLS'd0;
	 cache_inhibit <=  1'b0;
	 last_eval_miss <= 0;
	 
      end
      else
	case (state)
	  `OR1200_ICFSM_IDLE :
	    if (ic_en & icqmem_cycstb_i) begin
	       state <=  `OR1200_ICFSM_CFETCH;
	       saved_addr_r <=  start_addr;
	       hitmiss_eval <=  1'b1;
	       load <=  1'b1;
	       cache_inhibit <=  icqmem_ci_i;
	       last_eval_miss <= 0;
	    end
	    else begin
	       hitmiss_eval <=  1'b0;
	       load <=  1'b0;
	       cache_inhibit <=  1'b0;
	    end	  
	  `OR1200_ICFSM_CFETCH: begin
	     
	     if (icqmem_cycstb_i & icqmem_ci_i)
	       cache_inhibit <=  1'b1;
	     
	     if (hitmiss_eval)
	       saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];



	     if ((!ic_en) ||

		 (hitmiss_eval & !icqmem_cycstb_i) ||	
		 (biudata_error) ||

		 (cache_inhibit & biudata_valid)) begin	
		state <=  `OR1200_ICFSM_IDLE;
		hitmiss_eval <=  1'b0;
		load <=  1'b0;
		cache_inhibit <=  1'b0;
	     end

	     else if (tagcomp_miss & biudata_valid) begin	
		state <=  `OR1200_ICFSM_LREFILL3;
		saved_addr_r[`OR1200_ICLS-1:2] 
		  <= saved_addr_r[`OR1200_ICLS-1:2] + 1;
		hitmiss_eval <=  1'b0;
		cnt <= ((1 << `OR1200_ICLS) - (2 * 4));
		cache_inhibit <=  1'b0;
	     end

	     else if (!icqmem_cycstb_i
		      & !last_eval_miss
		      ) begin	
		state <=  `OR1200_ICFSM_IDLE;
		hitmiss_eval <=  1'b0;
		load <=  1'b0;
		cache_inhibit <=  1'b0;
	     end

	     else if (!tagcomp_miss & !icqmem_ci_i) begin
		saved_addr_r <=  start_addr;
		cache_inhibit <=  1'b0;
	     end
	     else
	       hitmiss_eval <=  1'b0;

	     if (hitmiss_eval & !tagcomp_miss)
	       last_eval_miss <= 1;
	     
	  end
	  `OR1200_ICFSM_LREFILL3 : begin

             if (!ic_en) begin

		state <=  `OR1200_ICFSM_IDLE;	
                saved_addr_r <=  start_addr;
                hitmiss_eval <=  1'b0;
                load <=  1'b0;
             end

	     else if (biudata_valid && (|cnt)) begin	
		cnt <=  cnt - `OR1200_ICLS'd4;
		saved_addr_r[`OR1200_ICLS-1:2] 
		  <= saved_addr_r[`OR1200_ICLS-1:2] + 1;
	     end

	     else if (biudata_valid) begin
		state <=  `OR1200_ICFSM_IDLE;
		saved_addr_r <=  start_addr;
		hitmiss_eval <=  1'b0;
		load <=  1'b0;
	     end
	  end
	  default:
	    state <=  `OR1200_ICFSM_IDLE;
	endcase
   end

endmodule
module or1200_ic_fsm(

	clk, rst,


	ic_en, icqmem_cycstb_i, icqmem_ci_i,
	tagcomp_miss, 
	biudata_valid, biudata_error, 
        start_addr, saved_addr,
	icram_we, tag_we,
        biu_read, 
        first_hit_ack, first_miss_ack, first_miss_err,
	burst
);





input				clk;
input				rst;
input				ic_en;
input				icqmem_cycstb_i;
input				icqmem_ci_i;
input				tagcomp_miss;
input				biudata_valid;
input				biudata_error;
input	[31:0]			start_addr;
output	[31:0]			saved_addr;
output	[3:0]			icram_we;
output				biu_read;
output				first_hit_ack;
output				first_miss_ack;
output				first_miss_err;
output				burst;
output				tag_we;




reg	[31:0]			saved_addr_r;
reg	[1:0]			state;
reg [`OR1200_ICLS-1:0]    	cnt;
reg				hitmiss_eval;
reg				load;
reg				cache_inhibit;
reg 				last_eval_miss;
   



   assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
   assign tag_we = biu_read & biudata_valid & !cache_inhibit;




   assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);


   assign saved_addr = saved_addr_r;


   assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & 
			  !tagcomp_miss & !cache_inhibit;




   assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid &
			   ~first_hit_ack;
   


   assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;




   assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & 
		  !cache_inhibit | (state == `OR1200_ICFSM_LREFILL3);




   always @(posedge clk or `OR1200_RST_EVENT rst) begin
      if (rst == `OR1200_RST_VALUE) begin
	 state <=  `OR1200_ICFSM_IDLE;
	 saved_addr_r <=  32'b0;
	 hitmiss_eval <=  1'b0;
	 load <=  1'b0;
	 cnt <=  `OR1200_ICLS'd0;
	 cache_inhibit <=  1'b0;
	 last_eval_miss <= 0;
	 
      end
      else
	case (state)
	  `OR1200_ICFSM_IDLE :
	    if (ic_en & icqmem_cycstb_i) begin
	       state <=  `OR1200_ICFSM_CFETCH;
	       saved_addr_r <=  start_addr;
	       hitmiss_eval <=  1'b1;
	       load <=  1'b1;
	       cache_inhibit <=  icqmem_ci_i;
	       last_eval_miss <= 0;
	    end
	    else begin
	       hitmiss_eval <=  1'b0;
	       load <=  1'b0;
	       cache_inhibit <=  1'b0;
	    end	  
	  `OR1200_ICFSM_CFETCH: begin
	     
	     if (icqmem_cycstb_i & icqmem_ci_i)
	       cache_inhibit <=  1'b1;
	     
	     if (hitmiss_eval)
	       saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];



	     if ((!ic_en) ||

		 (hitmiss_eval & !icqmem_cycstb_i) ||	
		 (biudata_error) ||

		 (cache_inhibit & biudata_valid)) begin	
		state <=  `OR1200_ICFSM_IDLE;
		hitmiss_eval <=  1'b0;
		load <=  1'b0;
		cache_inhibit <=  1'b0;
	     end

	     else if (tagcomp_miss & biudata_valid) begin	
		state <=  `OR1200_ICFSM_LREFILL3;
		saved_addr_r[`OR1200_ICLS-1:2] 
		  <= saved_addr_r[`OR1200_ICLS-1:2] + 1;
		hitmiss_eval <=  1'b0;
		cnt <= ((1 << `OR1200_ICLS) - (2 * 4));
		cache_inhibit <=  1'b0;
	     end

	     else if (!icqmem_cycstb_i
		      & !last_eval_miss
		      ) begin	
		state <=  `OR1200_ICFSM_IDLE;
		hitmiss_eval <=  1'b0;
		load <=  1'b0;
		cache_inhibit <=  1'b0;
	     end

	     else if (!tagcomp_miss & !icqmem_ci_i) begin
		saved_addr_r <=  start_addr;
		cache_inhibit <=  1'b0;
	     end
	     else
	       hitmiss_eval <=  1'b0;

	     if (hitmiss_eval & !tagcomp_miss)
	       last_eval_miss <= 1;
	     
	  end
	  `OR1200_ICFSM_LREFILL3 : begin

             if (!ic_en) begin

		state <=  `OR1200_ICFSM_IDLE;	
                saved_addr_r <=  start_addr;
                hitmiss_eval <=  1'b0;
                load <=  1'b0;
             end

	     else if (biudata_valid && (|cnt)) begin	
		cnt <=  cnt - `OR1200_ICLS'd4;
		saved_addr_r[`OR1200_ICLS-1:2] 
		  <= saved_addr_r[`OR1200_ICLS-1:2] + 1;
	     end

	     else if (biudata_valid) begin
		state <=  `OR1200_ICFSM_IDLE;
		saved_addr_r <=  start_addr;
		hitmiss_eval <=  1'b0;
		load <=  1'b0;
	     end
	  end
	  default:
	    state <=  `OR1200_ICFSM_IDLE;
	endcase
   end

endmodule