data/full_repos/permissive/155064391/demo/oled_pattern.v
None: at end of input
1: b'%Error: data/full_repos/permissive/155064391/demo/oled_pattern.v:1: Cannot find include file: components/oled.v\n`include "components/oled.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/155064391/demo,data/full_repos/permissive/155064391/components/oled.v\n             data/full_repos/permissive/155064391/demo,data/full_repos/permissive/155064391/components/oled.v.v\n             data/full_repos/permissive/155064391/demo,data/full_repos/permissive/155064391/components/oled.v.sv\n             components/oled.v\n             components/oled.v.v\n             components/oled.v.sv\n             obj_dir/components/oled.v\n             obj_dir/components/oled.v.v\n             obj_dir/components/oled.v.sv\n%Error: Exiting due to 1 error(s)\n'
module pattern(input wire       clk,
               input wire       read,
               input wire [5:0] row_idx,
               input wire [6:0] column_idx,
               output reg [7:0] data,
               output reg       ack);

  wire page_odd = row_idx & 1;
  wire column_field_odd = ((column_idx >> 3) & 1);
  wire field_black = page_odd ^ column_field_odd;
  wire column_odd = column_idx & 1;

  always @(posedge clk) begin
    ack <= 0;
    if (read) begin
      ack <= 1;
      if (field_black)
        data <= 8'b00000000;
      else if (column_odd)
        data <= 8'b10101010;
      else
        data <= 8'b01010101;
    end
  end
endmodule
module pattern(input wire       clk,
               input wire       read,
               input wire [5:0] row_idx,
               input wire [6:0] column_idx,
               output reg [7:0] data,
               output reg       ack);


  wire page_odd = row_idx & 1;
  wire column_field_odd = ((column_idx >> 3) & 1);
  wire field_black = page_odd ^ column_field_odd;
  wire column_odd = column_idx & 1;

  always @(posedge clk) begin
    ack <= 0;
    if (read) begin
      ack <= 1;
      if (field_black)
        data <= 8'b00000000;
      else if (column_odd)
        data <= 8'b10101010;
      else
        data <= 8'b01010101;
    end
  end
endmodule