data/full_repos/permissive/146399661/src/control_unit/test_cu.v
None: at end of input
1: b'%Error: data/full_repos/permissive/146399661/src/control_unit/test_cu.v:12: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146399661/src/control_unit,data/full_repos/permissive/146399661/constants.vh\n             data/full_repos/permissive/146399661/src/control_unit,data/full_repos/permissive/146399661/constants.vh.v\n             data/full_repos/permissive/146399661/src/control_unit,data/full_repos/permissive/146399661/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/control_unit/test_cu.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/control_unit/test_cu.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/control_unit/test_cu.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/control_unit/test_cu.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/control_unit/test_cu.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/control_unit/test_cu.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module main;
`include "constants.vh"

reg clock,reset,enable;
reg [OPCODE_WIDTH-1:0] opcode;
reg [DATA_WIDTH-1:0] datain,addr;
wire [DATA_WIDTH-1:0] rsa_dataout,mem_dataout,dataout,rsa_datain,rsa_modulusin,rsa_keyin,mem_datain;
wire rsa_en,mem_en,cu_ready;
wire [STATUS_WIDTH-1:0] status;

reg mem_ready,rsa_ready;

cu cu( clock,reset,enable,opcode,datain,addr,
           rsa_dataout,rsa_ready,mem_dataout,mem_ready,
           dataout,status,cu_ready,
           rsa_datain,rsa_modulusin,rsa_keyin,mem_datain,
           rsa_en,mem_en
          );

initial begin

    $display("test >> Resetting Chakravyuh");

    rsa_ready = 1'b1;
    mem_ready = 1'b1;
    reset = 1'b1;
    #10;
    reset = 1'b0;

    if (cu_ready == 1'b0) begin
        $display("test >> All is well, CU is ready!");
    end

    $display("test >> Testing memory read");

    opcode = OPCODE_MEM_READ;
    enable = 1'b1;

    $display("test >> Waiting for ready signal");

    while (cu_ready == 1'b0) begin
        #1;
    end

    $display("test >> Got the ready signal, setting enable to zero");
    enable = 1'b0;

    $display("test >> Waiting for CU to get ready for next operation");
    while (cu_ready != 1'b0) begin
        #1;
    end

    $display("test >> Testing memory write");
    opcode = OPCODE_MEM_WRITE;
    enable = 1'b1;

    $display("test >> Waiting for ready signal");
    while (cu_ready == 1'b0) begin
        #1;
    end

    $display("test >> Got the ready signal, setting enable to zero");
    enable = 1'b0;

end

always begin
    clock = 0;
    #5;
    clock = 1;
    #5;
end

endmodule
module main;

`include "constants.vh"

reg clock,reset,enable;
reg [OPCODE_WIDTH-1:0] opcode;
reg [DATA_WIDTH-1:0] datain,addr;
wire [DATA_WIDTH-1:0] rsa_dataout,mem_dataout,dataout,rsa_datain,rsa_modulusin,rsa_keyin,mem_datain;
wire rsa_en,mem_en,cu_ready;
wire [STATUS_WIDTH-1:0] status;

reg mem_ready,rsa_ready;

cu cu( clock,reset,enable,opcode,datain,addr,
           rsa_dataout,rsa_ready,mem_dataout,mem_ready,
           dataout,status,cu_ready,
           rsa_datain,rsa_modulusin,rsa_keyin,mem_datain,
           rsa_en,mem_en
          );

initial begin

    $display("test >> Resetting Chakravyuh");

    rsa_ready = 1'b1;
    mem_ready = 1'b1;
    reset = 1'b1;
    #10;
    reset = 1'b0;

    if (cu_ready == 1'b0) begin
        $display("test >> All is well, CU is ready!");
    end

    $display("test >> Testing memory read");

    opcode = OPCODE_MEM_READ;
    enable = 1'b1;

    $display("test >> Waiting for ready signal");

    while (cu_ready == 1'b0) begin
        #1;
    end

    $display("test >> Got the ready signal, setting enable to zero");
    enable = 1'b0;

    $display("test >> Waiting for CU to get ready for next operation");
    while (cu_ready != 1'b0) begin
        #1;
    end

    $display("test >> Testing memory write");
    opcode = OPCODE_MEM_WRITE;
    enable = 1'b1;

    $display("test >> Waiting for ready signal");
    while (cu_ready == 1'b0) begin
        #1;
    end

    $display("test >> Got the ready signal, setting enable to zero");
    enable = 1'b0;

end

always begin
    clock = 0;
    #5;
    clock = 1;
    #5;
end

endmodule