data/full_repos/permissive/161526648/SingleCycle.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:300: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                      : ... In instance SingleCycle.alu\n    result = ALUsrc1 < ALUsrc2;  \n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:227: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                      : ... In instance SingleCycle.ImExtend\n assign out = $signed(in);\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module RegFile(readReg1,readReg2,writeReg,writeData,regWrite,readData1,readData2);
	input [4:0]readReg1,readReg2,writeReg;
	input regWrite;
	input [31:0]writeData;
	output reg [31:0]readData1,readData2;
	reg [31:0]regfile[31:0];
	initial begin
		regfile[0]=32'b0;
		regfile[1]=32'b0;
		regfile[2]=32'b0;
		regfile[3]=32'b0;
		regfile[4]=32'b0;
		regfile[5]=32'b0;
		regfile[6]=32'b0;
		regfile[7]=32'b0;
		regfile[8]=32'b0;
		regfile[9]=32'b0;
		regfile[10]=32'b0;
		regfile[11]=32'b0;
		regfile[12]=32'b0;
		regfile[13]=32'b0;
		regfile[14]=32'b0;
		regfile[15]=32'b0;
		regfile[16]=32'b0;
		regfile[17]=32'b0;
		regfile[18]=32'b0;
		regfile[19]=32'b0;
		regfile[20]=32'b0;
		regfile[21]=32'b0;
		regfile[22]=32'b0;
		regfile[23]=32'b0;
		regfile[24]=32'b0;
		regfile[25]=32'b0;
		regfile[26]=32'b0;
		regfile[27]=32'b0;
		regfile[28]=32'b0;
		regfile[29]=32'b0;
		regfile[30]=32'b0;
		regfile[31]=32'b0;
	end
	always @(readReg1 or readReg2 or writeReg or regWrite or writeData) begin
		readData1 = regfile[readReg1];
		readData2 = regfile[readReg2];
		if (regWrite) regfile[writeReg] = writeData;
	end
endmodule
module RegFile(readReg1,readReg2,writeReg,writeData,regWrite,readData1,readData2);

	input [4:0]readReg1,readReg2,writeReg;
	input regWrite;
	input [31:0]writeData;
	output reg [31:0]readData1,readData2;
	reg [31:0]regfile[31:0];
	initial begin
		regfile[0]=32'b0;
		regfile[1]=32'b0;
		regfile[2]=32'b0;
		regfile[3]=32'b0;
		regfile[4]=32'b0;
		regfile[5]=32'b0;
		regfile[6]=32'b0;
		regfile[7]=32'b0;
		regfile[8]=32'b0;
		regfile[9]=32'b0;
		regfile[10]=32'b0;
		regfile[11]=32'b0;
		regfile[12]=32'b0;
		regfile[13]=32'b0;
		regfile[14]=32'b0;
		regfile[15]=32'b0;
		regfile[16]=32'b0;
		regfile[17]=32'b0;
		regfile[18]=32'b0;
		regfile[19]=32'b0;
		regfile[20]=32'b0;
		regfile[21]=32'b0;
		regfile[22]=32'b0;
		regfile[23]=32'b0;
		regfile[24]=32'b0;
		regfile[25]=32'b0;
		regfile[26]=32'b0;
		regfile[27]=32'b0;
		regfile[28]=32'b0;
		regfile[29]=32'b0;
		regfile[30]=32'b0;
		regfile[31]=32'b0;
	end
	always @(readReg1 or readReg2 or writeReg or regWrite or writeData) begin
		readData1 = regfile[readReg1];
		readData2 = regfile[readReg2];
		if (regWrite) regfile[writeReg] = writeData;
	end
endmodule