data/full_repos/permissive/142844950/rtl/b_lut/b_lut.v
data/verilator_xmls/e308bbd7-1adf-4c88-8442-a1b11211d593.xml
module b_lut (

input  wire [31:0] crs1  ,
input  wire [31:0] crs2  ,
input  wire [31:0] crs3  ,

output wire [31:0] result

);


wire [ 3:0] lut_arr [15:0];
wire [63:0] lut_con = {crs1, crs2};

genvar i;
generate for (i = 0; i < 16; i = i + 1) begin

    assign lut_arr[i] = lut_con[4*i+3:4*i];

end endgenerate


genvar j;
generate for (j = 0; j < 8; j = j + 1) begin

    assign result[4*j+3:4*j] = lut_arr[crs3[4*j+3:4*j]];

end endgenerate

endmodule
module b_lut (

input  wire [31:0] crs1  ,
input  wire [31:0] crs2  ,
input  wire [31:0] crs3  ,

output wire [31:0] result

);



wire [ 3:0] lut_arr [15:0];
wire [63:0] lut_con = {crs1, crs2};

genvar i;
generate for (i = 0; i < 16; i = i + 1) begin

    assign lut_arr[i] = lut_con[4*i+3:4*i];

end endgenerate


genvar j;
generate for (j = 0; j < 8; j = j + 1) begin

    assign result[4*j+3:4*j] = lut_arr[crs3[4*j+3:4*j]];

end endgenerate

endmodule