data/full_repos/permissive/143278/ivltests/addsr.v
data/verilator_xmls/1c719de7-1b02-4a56-bbb1-e47e33a51e1c.xml
module main;

   reg [3:0] a;
   reg [4:0] result, b;

   initial begin
      a = 5;
      b = 6;
      result = (a + b) >> 1;
      if (result !== 5) begin
	 $display("FAILED: result === %b", result);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;


   reg [3:0] a;
   reg [4:0] result, b;

   initial begin
      a = 5;
      b = 6;
      result = (a + b) >> 1;
      if (result !== 5) begin
	 $display("FAILED: result === %b", result);
	 $finish;
      end

      $display("PASSED");
   end
endmodule