data/full_repos/permissive/16552133/src/verilog/instruction_register.v
 line:25: before: "("
data/verilator_xmls/3e98d174-822e-4242-8a63-d861cfff719b.xml
module instruction_register(clk,in,out,opcode,ls,enable,clr);
	input clk,clr,ls,enable;
	input [15:0] in;
	output [15:0] out;
	output [3:0] opcode;
	reg [15:0] instr;
	
	initial begin instr = 16'dZ; end
	
	always @(posedge(clk))
	begin
		if(clr) begin
			instr = 16'dZ;
		end
		else if (ls) begin
			instr = in;
		end
		else begin
			instr = instr;
		end
	end
	
	assign opcode = instr[15:12];
	assign out = (enable) ? instr : 16'hZZ;
	



	always @(posedge(ls))
	begin
		instr = 16'dZ;
	end
	
endmodule
module instruction_register(clk,in,out,opcode,ls,enable,clr);

	input clk,clr,ls,enable;
	input [15:0] in;
	output [15:0] out;
	output [3:0] opcode;
	reg [15:0] instr;
	
	initial begin instr = 16'dZ; end
	
	always @(posedge(clk))
	begin
		if(clr) begin
			instr = 16'dZ;
		end
		else if (ls) begin
			instr = in;
		end
		else begin
			instr = instr;
		end
	end
	
	assign opcode = instr[15:12];
	assign out = (enable) ? instr : 16'hZZ;
	



	always @(posedge(ls))
	begin
		instr = 16'dZ;
	end
	
endmodule