data/full_repos/permissive/153414067/SRAM_256kx16.v
'utf-8' codec can't decode byte 0xf3 in position 82: invalid continuation byte
1: b'%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:81: Operator SUB expects 10 bits on the RHS, but RHS\'s CONST \'5\'h14\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n   else if (((ver_cntr > ball_ver-5\'d20) && (ver_cntr <= ball_ver-5\'d16) && (hor_cntr >= ball_hor-1\'d1) && (hor_cntr <= ball_hor+1\'d1)) || \n                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:81: Operator SUB expects 10 bits on the RHS, but RHS\'s CONST \'5\'h10\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n   else if (((ver_cntr > ball_ver-5\'d20) && (ver_cntr <= ball_ver-5\'d16) && (hor_cntr >= ball_hor-1\'d1) && (hor_cntr <= ball_hor+1\'d1)) || \n                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:82: Operator SUB expects 10 bits on the RHS, but RHS\'s CONST \'5\'h10\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver-5\'d16) && (ver_cntr <= ball_ver-4\'d8)  && (hor_cntr >= ball_hor-2\'d3) && (hor_cntr <= ball_hor+2\'d3)) ||\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:82: Operator SUB expects 10 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver-5\'d16) && (ver_cntr <= ball_ver-4\'d8)  && (hor_cntr >= ball_hor-2\'d3) && (hor_cntr <= ball_hor+2\'d3)) ||\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:82: Operator SUB expects 7 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver-5\'d16) && (ver_cntr <= ball_ver-4\'d8)  && (hor_cntr >= ball_hor-2\'d3) && (hor_cntr <= ball_hor+2\'d3)) ||\n                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:82: Operator ADD expects 7 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver-5\'d16) && (ver_cntr <= ball_ver-4\'d8)  && (hor_cntr >= ball_hor-2\'d3) && (hor_cntr <= ball_hor+2\'d3)) ||\n                                                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:83: Operator SUB expects 10 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver-4\'d8)  && (ver_cntr <= ball_ver+4\'d8)  && (hor_cntr >= ball_hor-3\'d4) && (hor_cntr <= ball_hor+3\'d4)) ||\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:83: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver-4\'d8)  && (ver_cntr <= ball_ver+4\'d8)  && (hor_cntr >= ball_hor-3\'d4) && (hor_cntr <= ball_hor+3\'d4)) ||\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:83: Operator SUB expects 7 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver-4\'d8)  && (ver_cntr <= ball_ver+4\'d8)  && (hor_cntr >= ball_hor-3\'d4) && (hor_cntr <= ball_hor+3\'d4)) ||\n                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:83: Operator ADD expects 7 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver-4\'d8)  && (ver_cntr <= ball_ver+4\'d8)  && (hor_cntr >= ball_hor-3\'d4) && (hor_cntr <= ball_hor+3\'d4)) ||\n                                                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:84: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver+4\'d8)  && (ver_cntr <= ball_ver+5\'d16) && (hor_cntr >= ball_hor-2\'d3) && (hor_cntr <= ball_hor+2\'d3)) ||\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:84: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'5\'h10\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver+4\'d8)  && (ver_cntr <= ball_ver+5\'d16) && (hor_cntr >= ball_hor-2\'d3) && (hor_cntr <= ball_hor+2\'d3)) ||\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:84: Operator SUB expects 7 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver+4\'d8)  && (ver_cntr <= ball_ver+5\'d16) && (hor_cntr >= ball_hor-2\'d3) && (hor_cntr <= ball_hor+2\'d3)) ||\n                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:84: Operator ADD expects 7 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver+4\'d8)  && (ver_cntr <= ball_ver+5\'d16) && (hor_cntr >= ball_hor-2\'d3) && (hor_cntr <= ball_hor+2\'d3)) ||\n                                                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:85: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'5\'h10\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver+5\'d16) && (ver_cntr <= ball_ver+5\'d20) && (hor_cntr >= ball_hor-1\'d1) && (hor_cntr <= ball_hor+1\'d1))) \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:85: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'5\'h14\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr > ball_ver+5\'d16) && (ver_cntr <= ball_ver+5\'d20) && (hor_cntr >= ball_hor-1\'d1) && (hor_cntr <= ball_hor+1\'d1))) \n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:74: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'5\'h13\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n   else if (((ver_cntr >= {out_platform_ver, 2\'b00}) && (ver_cntr <= {out_platform_ver, 2\'b00} + 5\'d19) && (hor_cntr >= out_platform_hor - out_platform_width) && (hor_cntr <= out_platform_hor + out_platform_width)) ||\n                                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:75: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'5\'h13\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform0_ver, 2\'b00}) && (ver_cntr <= {platform0_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform0_hor - platform0_width) && (hor_cntr <= platform0_hor + platform0_width)) ||\n                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:76: Operator GTE expects 10 bits on the RHS, but RHS\'s REPLICATE generates 9 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform1_ver, 2\'b00}) && (ver_cntr <= {platform1_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform1_hor - platform1_width) && (hor_cntr <= platform1_hor + platform1_width)) ||\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:76: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'5\'h13\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform1_ver, 2\'b00}) && (ver_cntr <= {platform1_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform1_hor - platform1_width) && (hor_cntr <= platform1_hor + platform1_width)) ||\n                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:76: Operator SUB expects 7 bits on the RHS, but RHS\'s VARREF \'platform1_width\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform1_ver, 2\'b00}) && (ver_cntr <= {platform1_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform1_hor - platform1_width) && (hor_cntr <= platform1_hor + platform1_width)) ||\n                                                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:76: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'platform1_width\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform1_ver, 2\'b00}) && (ver_cntr <= {platform1_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform1_hor - platform1_width) && (hor_cntr <= platform1_hor + platform1_width)) ||\n                                                                                                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:77: Operator GTE expects 10 bits on the RHS, but RHS\'s REPLICATE generates 8 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform2_ver, 2\'b00}) && (ver_cntr <= {platform2_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform2_hor - platform2_width) && (hor_cntr <= platform2_hor + platform2_width)) ||\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:77: Operator ADD expects 10 bits on the LHS, but LHS\'s REPLICATE generates 8 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform2_ver, 2\'b00}) && (ver_cntr <= {platform2_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform2_hor - platform2_width) && (hor_cntr <= platform2_hor + platform2_width)) ||\n                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:77: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'5\'h13\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform2_ver, 2\'b00}) && (ver_cntr <= {platform2_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform2_hor - platform2_width) && (hor_cntr <= platform2_hor + platform2_width)) ||\n                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:77: Operator SUB expects 7 bits on the RHS, but RHS\'s VARREF \'platform2_width\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform2_ver, 2\'b00}) && (ver_cntr <= {platform2_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform2_hor - platform2_width) && (hor_cntr <= platform2_hor + platform2_width)) ||\n                                                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:77: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'platform2_width\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform2_ver, 2\'b00}) && (ver_cntr <= {platform2_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform2_hor - platform2_width) && (hor_cntr <= platform2_hor + platform2_width)) ||\n                                                                                                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:78: Operator GTE expects 10 bits on the RHS, but RHS\'s REPLICATE generates 7 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform3_ver, 2\'b00}) && (ver_cntr <= {platform3_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform3_hor - platform2_width) && (hor_cntr <= platform3_hor + platform3_width)))\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:78: Operator ADD expects 10 bits on the LHS, but LHS\'s REPLICATE generates 7 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform3_ver, 2\'b00}) && (ver_cntr <= {platform3_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform3_hor - platform2_width) && (hor_cntr <= platform3_hor + platform3_width)))\n                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:78: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'5\'h13\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform3_ver, 2\'b00}) && (ver_cntr <= {platform3_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform3_hor - platform2_width) && (hor_cntr <= platform3_hor + platform3_width)))\n                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:78: Operator SUB expects 7 bits on the RHS, but RHS\'s VARREF \'platform2_width\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform3_ver, 2\'b00}) && (ver_cntr <= {platform3_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform3_hor - platform2_width) && (hor_cntr <= platform3_hor + platform3_width)))\n                                                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:78: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'platform3_width\' generates 5 bits.\n                                                                      : ... In instance SRAM_256kx16\n      ((ver_cntr >= {platform3_ver, 2\'b00}) && (ver_cntr <= {platform3_ver, 2\'b00} + 5\'d19) && (hor_cntr >= platform3_hor - platform2_width) && (hor_cntr <= platform3_hor + platform3_width)))\n                                                                                                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:71: Operator GTE expects 10 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                      : ... In instance SRAM_256kx16\n   if ((ver_cntr >= 1\'d0) && (ver_cntr <= 6\'d39) && (hor_cntr >= 3\'d6) && (hor_cntr <= 7\'d96))\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:71: Operator LTE expects 10 bits on the RHS, but RHS\'s CONST \'6\'h27\' generates 6 bits.\n                                                                      : ... In instance SRAM_256kx16\n   if ((ver_cntr >= 1\'d0) && (ver_cntr <= 6\'d39) && (hor_cntr >= 3\'d6) && (hor_cntr <= 7\'d96))\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/153414067/SRAM_256kx16.v:71: Operator GTE expects 7 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n                                                                      : ... In instance SRAM_256kx16\n   if ((ver_cntr >= 1\'d0) && (ver_cntr <= 6\'d39) && (hor_cntr >= 3\'d6) && (hor_cntr <= 7\'d96))\n                                                              ^~\n%Warning-UNSIGNED: data/full_repos/permissive/153414067/SRAM_256kx16.v:71: Comparison is constant due to unsigned arithmetic\n                                                                         : ... In instance SRAM_256kx16\n   if ((ver_cntr >= 1\'d0) && (ver_cntr <= 6\'d39) && (hor_cntr >= 3\'d6) && (hor_cntr <= 7\'d96))\n                 ^~\n%Error: Exiting due to 36 warning(s)\n'
module SRAM_256kx16(
	input clk,
	input rst,
	input write,
	output [5:0] mem_data,
	
	input [6:0] ball_hor,
	input [9:0] ball_ver,
	




	
	input [7:0] platform0_ver,
	input [6:0] platform0_hor,
	input [5:0] platform0_width,
	
	input [6:0] platform1_ver,
	input [6:0] platform1_hor,
	input [4:0] platform1_width,
	
	input [5:0] platform2_ver,
	input [6:0] platform2_hor,
	input [4:0] platform2_width,
	
	input [4:0] platform3_ver,
	input [6:0] platform3_hor,
	input [4:0] platform3_width,
	

	
	input [7:0] out_platform_ver,
	input [6:0] out_platform_hor,
	input [5:0] out_platform_width,
	
	input over
	);
	
	reg [5:0] data;
	
	reg [9:0] ver_cntr = 10'd1;
	reg [6:0] hor_cntr = 7'd1;
	 
	always @ (posedge clk)
	begin
		if (rst || ~(write)) begin
			hor_cntr <= 7'd1;
			if (rst) ver_cntr <= 10'd1;
		end
		else begin
			if (hor_cntr == 7'd101)
				if (ver_cntr != 10'd600) ver_cntr <= ver_cntr + 1'b1;
				else ver_cntr <= 10'd1;
			else
				hor_cntr <= hor_cntr + 1'b1;
		end
	end
	
	always @ (*)
	begin
		if (over) data <= 000001;
		else begin

			if ((ver_cntr >= 1'd0) && (ver_cntr <= 6'd39) && (hor_cntr >= 3'd6) && (hor_cntr <= 7'd96))
				data <= 6'b000000;

			else if (((ver_cntr >= {out_platform_ver, 2'b00}) && (ver_cntr <= {out_platform_ver, 2'b00} + 5'd19) && (hor_cntr >= out_platform_hor - out_platform_width) && (hor_cntr <= out_platform_hor + out_platform_width)) ||
						((ver_cntr >= {platform0_ver, 2'b00}) && (ver_cntr <= {platform0_ver, 2'b00} + 5'd19) && (hor_cntr >= platform0_hor - platform0_width) && (hor_cntr <= platform0_hor + platform0_width)) ||
						((ver_cntr >= {platform1_ver, 2'b00}) && (ver_cntr <= {platform1_ver, 2'b00} + 5'd19) && (hor_cntr >= platform1_hor - platform1_width) && (hor_cntr <= platform1_hor + platform1_width)) ||
						((ver_cntr >= {platform2_ver, 2'b00}) && (ver_cntr <= {platform2_ver, 2'b00} + 5'd19) && (hor_cntr >= platform2_hor - platform2_width) && (hor_cntr <= platform2_hor + platform2_width)) ||
						((ver_cntr >= {platform3_ver, 2'b00}) && (ver_cntr <= {platform3_ver, 2'b00} + 5'd19) && (hor_cntr >= platform3_hor - platform2_width) && (hor_cntr <= platform3_hor + platform3_width)))
				data <= 6'b001100;

			else if (((ver_cntr > ball_ver-5'd20) && (ver_cntr <= ball_ver-5'd16) && (hor_cntr >= ball_hor-1'd1) && (hor_cntr <= ball_hor+1'd1)) || 
						((ver_cntr > ball_ver-5'd16) && (ver_cntr <= ball_ver-4'd8)  && (hor_cntr >= ball_hor-2'd3) && (hor_cntr <= ball_hor+2'd3)) ||
						((ver_cntr > ball_ver-4'd8)  && (ver_cntr <= ball_ver+4'd8)  && (hor_cntr >= ball_hor-3'd4) && (hor_cntr <= ball_hor+3'd4)) ||
						((ver_cntr > ball_ver+4'd8)  && (ver_cntr <= ball_ver+5'd16) && (hor_cntr >= ball_hor-2'd3) && (hor_cntr <= ball_hor+2'd3)) ||
						((ver_cntr > ball_ver+5'd16) && (ver_cntr <= ball_ver+5'd20) && (hor_cntr >= ball_hor-1'd1) && (hor_cntr <= ball_hor+1'd1)))	
				data <= 6'b000011;

			else
				data <= 6'b110100;
		end	
	end
	

	assign mem_data = write ? data : 6'bzzzzzz;

endmodule
module SRAM_256kx16(
	input clk,
	input rst,
	input write,
	output [5:0] mem_data,
	
	input [6:0] ball_hor,
	input [9:0] ball_ver,
	




	
	input [7:0] platform0_ver,
	input [6:0] platform0_hor,
	input [5:0] platform0_width,
	
	input [6:0] platform1_ver,
	input [6:0] platform1_hor,
	input [4:0] platform1_width,
	
	input [5:0] platform2_ver,
	input [6:0] platform2_hor,
	input [4:0] platform2_width,
	
	input [4:0] platform3_ver,
	input [6:0] platform3_hor,
	input [4:0] platform3_width,
	

	
	input [7:0] out_platform_ver,
	input [6:0] out_platform_hor,
	input [5:0] out_platform_width,
	
	input over
	);

	
	reg [5:0] data;
	
	reg [9:0] ver_cntr = 10'd1;
	reg [6:0] hor_cntr = 7'd1;
	 
	always @ (posedge clk)
	begin
		if (rst || ~(write)) begin
			hor_cntr <= 7'd1;
			if (rst) ver_cntr <= 10'd1;
		end
		else begin
			if (hor_cntr == 7'd101)
				if (ver_cntr != 10'd600) ver_cntr <= ver_cntr + 1'b1;
				else ver_cntr <= 10'd1;
			else
				hor_cntr <= hor_cntr + 1'b1;
		end
	end
	
	always @ (*)
	begin
		if (over) data <= 000001;
		else begin

			if ((ver_cntr >= 1'd0) && (ver_cntr <= 6'd39) && (hor_cntr >= 3'd6) && (hor_cntr <= 7'd96))
				data <= 6'b000000;

			else if (((ver_cntr >= {out_platform_ver, 2'b00}) && (ver_cntr <= {out_platform_ver, 2'b00} + 5'd19) && (hor_cntr >= out_platform_hor - out_platform_width) && (hor_cntr <= out_platform_hor + out_platform_width)) ||
						((ver_cntr >= {platform0_ver, 2'b00}) && (ver_cntr <= {platform0_ver, 2'b00} + 5'd19) && (hor_cntr >= platform0_hor - platform0_width) && (hor_cntr <= platform0_hor + platform0_width)) ||
						((ver_cntr >= {platform1_ver, 2'b00}) && (ver_cntr <= {platform1_ver, 2'b00} + 5'd19) && (hor_cntr >= platform1_hor - platform1_width) && (hor_cntr <= platform1_hor + platform1_width)) ||
						((ver_cntr >= {platform2_ver, 2'b00}) && (ver_cntr <= {platform2_ver, 2'b00} + 5'd19) && (hor_cntr >= platform2_hor - platform2_width) && (hor_cntr <= platform2_hor + platform2_width)) ||
						((ver_cntr >= {platform3_ver, 2'b00}) && (ver_cntr <= {platform3_ver, 2'b00} + 5'd19) && (hor_cntr >= platform3_hor - platform2_width) && (hor_cntr <= platform3_hor + platform3_width)))
				data <= 6'b001100;

			else if (((ver_cntr > ball_ver-5'd20) && (ver_cntr <= ball_ver-5'd16) && (hor_cntr >= ball_hor-1'd1) && (hor_cntr <= ball_hor+1'd1)) || 
						((ver_cntr > ball_ver-5'd16) && (ver_cntr <= ball_ver-4'd8)  && (hor_cntr >= ball_hor-2'd3) && (hor_cntr <= ball_hor+2'd3)) ||
						((ver_cntr > ball_ver-4'd8)  && (ver_cntr <= ball_ver+4'd8)  && (hor_cntr >= ball_hor-3'd4) && (hor_cntr <= ball_hor+3'd4)) ||
						((ver_cntr > ball_ver+4'd8)  && (ver_cntr <= ball_ver+5'd16) && (hor_cntr >= ball_hor-2'd3) && (hor_cntr <= ball_hor+2'd3)) ||
						((ver_cntr > ball_ver+5'd16) && (ver_cntr <= ball_ver+5'd20) && (hor_cntr >= ball_hor-1'd1) && (hor_cntr <= ball_hor+1'd1)))	
				data <= 6'b000011;

			else
				data <= 6'b110100;
		end	
	end
	

	assign mem_data = write ? data : 6'bzzzzzz;

endmodule