data/full_repos/permissive/141596082/voice_core/voice_dcm.v
1: b"%Error: data/full_repos/permissive/141596082/voice_core/voice_dcm.v:34: Cannot find file containing module: 'IBUFG'\n  IBUFG clkin_buf (\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/141596082/voice_core,data/full_repos/permissive/141596082/IBUFG\n             data/full_repos/permissive/141596082/voice_core,data/full_repos/permissive/141596082/IBUFG.v\n             data/full_repos/permissive/141596082/voice_core,data/full_repos/permissive/141596082/IBUFG.sv\n             IBUFG\n             IBUFG.v\n             IBUFG.sv\n             obj_dir/IBUFG\n             obj_dir/IBUFG.v\n             obj_dir/IBUFG.sv\n%Error: data/full_repos/permissive/141596082/voice_core/voice_dcm.v:47: Cannot find file containing module: 'DCM_SP'\nDCM_SP\n^~~~~~\n%Error: data/full_repos/permissive/141596082/voice_core/voice_dcm.v:85: Cannot find file containing module: 'BUFG'\n  BUFG clkf_buf\n  ^~~~\n%Error: data/full_repos/permissive/141596082/voice_core/voice_dcm.v:89: Cannot find file containing module: 'BUFG'\n  BUFG clkout1_buf\n  ^~~~\n%Error: data/full_repos/permissive/141596082/voice_core/voice_dcm.v:93: Cannot find file containing module: 'BUFG'\n  BUFG clkout2_buf\n  ^~~~\n%Error: data/full_repos/permissive/141596082/voice_core/voice_dcm.v:97: Cannot find file containing module: 'BUFG'\n  BUFG clkout3_buf\n  ^~~~\n%Error: Exiting due to 6 error(s)\n"
module creator_dcm #(
  parameter CLKFX_DIVIDE   = 1,
  parameter CLKFX_MULTIPLY = 4
  ) (

  input  clkin       ,

  output clk_out_200 ,
  output nclk_out_200,
  output clk_out_25
);

  IBUFG clkin_buf (
    .O(b_clkin),
    .I(clkin  )
  );

  wire       locked_int;
  wire [7:0] status_int;
  wire       clkfb     ;
  wire       clk0      ;
  wire       clkfx     ;
  wire       nclkfx    ;
  wire       clkdv     ;

DCM_SP
#(.CLKDV_DIVIDE          (2.000),
  .CLKFX_DIVIDE          (CLKFX_DIVIDE),
  .CLKFX_MULTIPLY        (CLKFX_MULTIPLY),
  .CLKIN_DIVIDE_BY_2     ("FALSE"),
  .CLKIN_PERIOD          (20.000),
  .CLKOUT_PHASE_SHIFT    ("NONE"),
  .CLK_FEEDBACK          ("1X"),
  .DESKEW_ADJUST         ("SYSTEM_SYNCHRONOUS"),
  .PHASE_SHIFT           (0),
  .STARTUP_WAIT          ("FALSE"))
dcm_sp_inst (
  .CLKIN                 (b_clkin),
  .CLKFB                 (clkfb),

  .CLK0                  (clk0),
  .CLK90                 (),
  .CLK180                (),
  .CLK270                (),
  .CLK2X                 (),
  .CLK2X180              (),
  .CLKFX                 (clkfx),
  .CLKFX180              (nclkfx),
  .CLKDV                 (clkdv),

  .PSCLK                 (1'b0),
  .PSEN                  (1'b0),
  .PSINCDEC              (1'b0),
  .PSDONE                (),

  .LOCKED                (locked_int),
  .STATUS                (status_int),
  .RST                   (1'b0),

  .DSSEN                 (1'b0)
  );


  BUFG clkf_buf
   (.O (clkfb),
  .I (clk0));

  BUFG clkout1_buf
   (.O   (clk_out_200),
  .I   (clkfx));

  BUFG clkout2_buf
   (.O   (nclk_out_200),
  .I   (nclkfx));

  BUFG clkout3_buf
   (.O   (clk_out_25),
  .I   (clkdv));

endmodule
module creator_dcm #(
  parameter CLKFX_DIVIDE   = 1,
  parameter CLKFX_MULTIPLY = 4
  ) (

  input  clkin       ,

  output clk_out_200 ,
  output nclk_out_200,
  output clk_out_25
);


  IBUFG clkin_buf (
    .O(b_clkin),
    .I(clkin  )
  );

  wire       locked_int;
  wire [7:0] status_int;
  wire       clkfb     ;
  wire       clk0      ;
  wire       clkfx     ;
  wire       nclkfx    ;
  wire       clkdv     ;

DCM_SP
#(.CLKDV_DIVIDE          (2.000),
  .CLKFX_DIVIDE          (CLKFX_DIVIDE),
  .CLKFX_MULTIPLY        (CLKFX_MULTIPLY),
  .CLKIN_DIVIDE_BY_2     ("FALSE"),
  .CLKIN_PERIOD          (20.000),
  .CLKOUT_PHASE_SHIFT    ("NONE"),
  .CLK_FEEDBACK          ("1X"),
  .DESKEW_ADJUST         ("SYSTEM_SYNCHRONOUS"),
  .PHASE_SHIFT           (0),
  .STARTUP_WAIT          ("FALSE"))
dcm_sp_inst (
  .CLKIN                 (b_clkin),
  .CLKFB                 (clkfb),

  .CLK0                  (clk0),
  .CLK90                 (),
  .CLK180                (),
  .CLK270                (),
  .CLK2X                 (),
  .CLK2X180              (),
  .CLKFX                 (clkfx),
  .CLKFX180              (nclkfx),
  .CLKDV                 (clkdv),

  .PSCLK                 (1'b0),
  .PSEN                  (1'b0),
  .PSINCDEC              (1'b0),
  .PSDONE                (),

  .LOCKED                (locked_int),
  .STATUS                (status_int),
  .RST                   (1'b0),

  .DSSEN                 (1'b0)
  );


  BUFG clkf_buf
   (.O (clkfb),
  .I (clk0));

  BUFG clkout1_buf
   (.O   (clk_out_200),
  .I   (clkfx));

  BUFG clkout2_buf
   (.O   (nclk_out_200),
  .I   (nclkfx));

  BUFG clkout3_buf
   (.O   (clk_out_25),
  .I   (clkdv));

endmodule