data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_ram/rtl/verilog/wb_ram.v
1: b"%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_ram/rtl/verilog/wb_ram.v:34: Cannot find file containing module: 'wb_next_adr'\n   wb_next_adr #(.aw(aw)) wb_next_adr0(adr_r, wb_cti_i, wb_bte_i, next_adr);\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_ram/rtl/verilog,data/full_repos/permissive/19905110/wb_next_adr\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_ram/rtl/verilog,data/full_repos/permissive/19905110/wb_next_adr.v\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_ram/rtl/verilog,data/full_repos/permissive/19905110/wb_next_adr.sv\n             wb_next_adr\n             wb_next_adr.v\n             wb_next_adr.sv\n             obj_dir/wb_next_adr\n             obj_dir/wb_next_adr.v\n             obj_dir/wb_next_adr.sv\n%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_ram/rtl/verilog/wb_ram.v:55: Cannot find file containing module: 'wb_ram_generic'\n   wb_ram_generic\n   ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module wb_ram
 #(
   parameter dw = 32,

   parameter depth = 256,
   parameter aw    = $clog2(depth),
   parameter memfile = "")
  (input 	   wb_clk_i,
   input 	   wb_rst_i,
   
   input [aw-1:0]  wb_adr_i,
   input [dw-1:0]  wb_dat_i,
   input [3:0] 	   wb_sel_i,
   input 	   wb_we_i,
   input [1:0] 	   wb_bte_i,
   input [2:0] 	   wb_cti_i,
   input 	   wb_cyc_i,
   input 	   wb_stb_i,
   
   output reg 	   wb_ack_o,
   output 	   wb_err_o,
   output [dw-1:0] wb_dat_o);

   reg [aw-1:0] 	   adr_r;

   wire [aw-1:0] 	   next_adr;

   wire 		   valid = wb_cyc_i & wb_stb_i;

   reg 			   valid_r;

   wire 		   new_cycle = valid & !valid_r;

   wb_next_adr #(.aw(aw)) wb_next_adr0(adr_r, wb_cti_i, wb_bte_i, next_adr);

   wire [aw-1:0] 	   adr = new_cycle ? wb_adr_i : next_adr;

   always@(posedge wb_clk_i) begin
      adr_r   <= adr;
      valid_r <= valid;

      wb_ack_o <= valid & (!((wb_cti_i == 3'b000) | (wb_cti_i == 3'b111)) | !wb_ack_o);
      if(wb_rst_i) begin
	 adr_r <= {aw{1'b0}};
	 valid_r <= 1'b0;
	 wb_ack_o <= 1'b0;
      end
   end

   wire ram_we = wb_we_i & valid & wb_ack_o;


   assign wb_err_o =  1'b0;

   wb_ram_generic
     #(.depth(depth/4),
       .memfile (memfile))
   ram0
     (.clk (wb_clk_i),
      .we  ({4{ram_we}} & wb_sel_i),
      .din (wb_dat_i),
      .waddr(adr_r[aw-1:2]),
      .raddr (adr[aw-1:2]),
      .dout (wb_dat_o));

endmodule
module wb_ram
 #(
   parameter dw = 32,

   parameter depth = 256,
   parameter aw    = $clog2(depth),
   parameter memfile = "")
  (input 	   wb_clk_i,
   input 	   wb_rst_i,
   
   input [aw-1:0]  wb_adr_i,
   input [dw-1:0]  wb_dat_i,
   input [3:0] 	   wb_sel_i,
   input 	   wb_we_i,
   input [1:0] 	   wb_bte_i,
   input [2:0] 	   wb_cti_i,
   input 	   wb_cyc_i,
   input 	   wb_stb_i,
   
   output reg 	   wb_ack_o,
   output 	   wb_err_o,
   output [dw-1:0] wb_dat_o);


   reg [aw-1:0] 	   adr_r;

   wire [aw-1:0] 	   next_adr;

   wire 		   valid = wb_cyc_i & wb_stb_i;

   reg 			   valid_r;

   wire 		   new_cycle = valid & !valid_r;

   wb_next_adr #(.aw(aw)) wb_next_adr0(adr_r, wb_cti_i, wb_bte_i, next_adr);

   wire [aw-1:0] 	   adr = new_cycle ? wb_adr_i : next_adr;

   always@(posedge wb_clk_i) begin
      adr_r   <= adr;
      valid_r <= valid;

      wb_ack_o <= valid & (!((wb_cti_i == 3'b000) | (wb_cti_i == 3'b111)) | !wb_ack_o);
      if(wb_rst_i) begin
	 adr_r <= {aw{1'b0}};
	 valid_r <= 1'b0;
	 wb_ack_o <= 1'b0;
      end
   end

   wire ram_we = wb_we_i & valid & wb_ack_o;


   assign wb_err_o =  1'b0;

   wb_ram_generic
     #(.depth(depth/4),
       .memfile (memfile))
   ram0
     (.clk (wb_clk_i),
      .we  ({4{ram_we}} & wb_sel_i),
      .din (wb_dat_i),
      .waddr(adr_r[aw-1:2]),
      .raddr (adr[aw-1:2]),
      .dout (wb_dat_o));

endmodule