data/full_repos/permissive/117880471/HW3/sipo_8bit.v
 line:39: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:11: Unsupported: Ignoring delay on this delayed statement.\n #00 clock = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:12: Unsupported: Ignoring delay on this delayed statement.\n forever #20 clock = ~clock;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:17: Unsupported: Ignoring delay on this delayed statement.\n #00 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:18: Unsupported: Ignoring delay on this delayed statement.\n #50 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10 in_bit = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:24: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:25: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:26: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:27: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:28: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:29: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:30: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:31: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:33: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:34: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:35: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:36: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:37: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:38: Unsupported: Ignoring delay on this delayed statement.\n #20 in_bit = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:39: Unsupported: Ignoring delay on this delayed statement.\n #20 $stop;\n ^\n%Error: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:45: Unsupported or unknown PLI call: $monitor\n $monitor("time=%3d, sum=%8b, in_bit=%b, clock=%b, reset=%b");\n ^~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:49: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("sipo_8bit.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:50: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/sipo_8bit.v:65: syntax error, unexpected \';\'\n  sum << 1;\n          ^\n%Error: Exiting due to 4 error(s), 21 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sipo_8bit();
wire [7:0] sum;
reg in_bit, clock, reset;

sipo_8bit uut(sum, in_bit, clock, reset);

initial
begin
	#00 clock = 1'b0;
	forever #20 clock = ~clock;
end

initial
begin
	#00 reset = 1'b1;
	#50 reset = 1'b0;
end

initial
begin
	#10 in_bit = 1'b0;
	#20 in_bit = 1'b0;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b0;
	#20 in_bit = 1'b0;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b0;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b0;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b1;
	#20 $stop;
end


initial
begin
	$monitor("time=%3d, sum=%8b, in_bit=%b, clock=%b, reset=%b");
end
initial
begin
	$dumpfile("sipo_8bit.vcd");
	$dumpvars;
end

endmodule
module tb_sipo_8bit();

wire [7:0] sum;
reg in_bit, clock, reset;

sipo_8bit uut(sum, in_bit, clock, reset);

initial
begin
	#00 clock = 1'b0;
	forever #20 clock = ~clock;
end

initial
begin
	#00 reset = 1'b1;
	#50 reset = 1'b0;
end

initial
begin
	#10 in_bit = 1'b0;
	#20 in_bit = 1'b0;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b0;
	#20 in_bit = 1'b0;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b0;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b0;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b1;
	#20 in_bit = 1'b1;
	#20 $stop;
end


initial
begin
	$monitor("time=%3d, sum=%8b, in_bit=%b, clock=%b, reset=%b");
end
initial
begin
	$dumpfile("sipo_8bit.vcd");
	$dumpvars;
end

endmodule