data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v
 line:78: before: "("
1: b'%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:46: syntax error, unexpected byte\n .byte(uart_byte_out),\n  ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:67: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, comm_controller);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\nalways #(clk_pulse_width/2) clk = !clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:75: Unsupported or unknown PLI call: $monitor\n $monitor("Time %d", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:78: syntax error, unexpected \'@\'\n repeat (5) @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:91: Unsupported: wait statements\n wait( rst_n );\n ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:92: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:93: Unsupported or unknown PLI call: $monitor\n $monitor("[Time %d]: Started testbench", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:98: Unsupported or unknown PLI call: $monitor\n $monitor("[Time %d]: Testing write weight operation", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:99: syntax error, unexpected \'@\'\n repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);\n                                           ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:102: Unsupported: wait statements\n wait(clear);\n ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:106: syntax error, unexpected \'@\'\n  repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);\n                                            ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:109: Unsupported: wait statements\n  wait(clear);\n  ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:115: Unsupported or unknown PLI call: $monitor\n $monitor("[Time %d]: Testing write input operation", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:116: syntax error, unexpected \'@\'\n repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);\n                                           ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:119: Unsupported: wait statements\n wait(clear);\n ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:123: syntax error, unexpected \'@\'\n  repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);\n                                            ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:126: Unsupported: wait statements\n  wait(clear);\n  ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:133: Unsupported or unknown PLI call: $monitor\n $monitor("[Time %d]: Testing read", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:134: syntax error, unexpected \'@\'\n repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);\n                                           ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:137: Unsupported: wait statements\n wait(clear);\n ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:141: Unsupported: wait statements\n  wait(send_byte);\n  ^~~~\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:143: syntax error, unexpected \'@\'\n  repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);\n                                            ^\n%Error: data/full_repos/permissive/131358616/test/perceptron_comm_controller_tb.v:147: syntax error, unexpected \'@\'\n repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);\n                                           ^\n%Error: Exiting due to 23 error(s), 1 warning(s)\n'
module perceptron_comm_controller_tb;


localparam clock_frequency	= 12000000;
localparam clk_pulse_width = 1000000000/clock_frequency;

localparam uart_baud_rate	= 9600;

localparam integer 
	OP_READ 				= 5,
	OP_WRITE_WEIGHTS		= 50,
	OP_WRITE_INPUTS			= 51,
 	OP_READ_RESPONSE		= 100,
 	OP_WRITE_RESPONSE_OK 	= 101,
	OP_WRITE_RESPONSE_ERR	= 102;

reg clk, rst_n;
integer i;


reg [7:0] uart_byte_out;
reg uart_byte_ready;
reg uart_busy;
reg [15:0] perceptron_weight1, perceptron_weight2, perceptron_result;

wire [7:0] byte_to_send;
wire [15:0] weight1_new, weight2_new, input1_new, input2_new;
wire send_byte, weight_write, input_write, clear;

comm_controller comm_controller(
    .rst_n(rst_n),
    .clk(clk),
	
	.byte(uart_byte_out),
	.byte_ready(uart_byte_ready),
	.uart_busy(uart_busy),
	.weight1(perceptron_weight1),
	.weight2(perceptron_weight2),
	.result(perceptron_result),

	.uart_byte(byte_to_send),
	.weight1_new(weight1_new),
	.weight2_new(weight2_new),
	.data_in1(input1_new),
	.data_in2(input2_new),
	.uart_send(send_byte),
	.uart_clear(clear),
	.weight_write(weight_write),
	.input_write(input_write)
);



initial begin
    $dumpvars(0, comm_controller);
end


always #(clk_pulse_width/2) clk = !clk;


initial begin
	$monitor("Time %d", $time);
	clk = 0;
    rst_n = 0;
	repeat (5) @(negedge clk);
	rst_n = 1;
end


initial begin
	uart_byte_out = 0;
	uart_byte_ready = 0;
	uart_busy = 0;
	perceptron_weight1 = 101;
	perceptron_weight2 = 102;
	perceptron_result =  103;

	wait( rst_n );
	@(negedge clk);
	$monitor("[Time %d]: Started testbench", $time);




	$monitor("[Time %d]: Testing write weight operation", $time);
	repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);
	uart_byte_out = OP_WRITE_WEIGHTS;
	uart_byte_ready = 1;
	wait(clear);
	uart_byte_ready = 0;

	for (i = 0; i < 4; i = i+1) begin
		repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);
		uart_byte_out = 50 + i;
		uart_byte_ready = 1;
		wait(clear);
		uart_byte_ready = 0;
	end



	$monitor("[Time %d]: Testing write input operation", $time);
	repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);
	uart_byte_out = OP_WRITE_INPUTS;
	uart_byte_ready = 1;
	wait(clear);
	uart_byte_ready = 0;

	for (i = 0; i < 4; i = i+1) begin
		repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);
		uart_byte_out = 70 + i;
		uart_byte_ready = 1;
		wait(clear);
		uart_byte_ready = 0;
	end




	$monitor("[Time %d]: Testing read", $time);
	repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);
	uart_byte_out = OP_READ;
	uart_byte_ready = 1;
	wait(clear);
	uart_byte_ready = 0;	

	for (i = 0; i < 6; i = i+1) begin
		wait(send_byte);
		uart_busy = 1;
		repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);
		uart_busy = 0;
	end

	repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);

	$finish;
end

endmodule
module perceptron_comm_controller_tb;



localparam clock_frequency	= 12000000;
localparam clk_pulse_width = 1000000000/clock_frequency;

localparam uart_baud_rate	= 9600;

localparam integer 
	OP_READ 				= 5,
	OP_WRITE_WEIGHTS		= 50,
	OP_WRITE_INPUTS			= 51,
 	OP_READ_RESPONSE		= 100,
 	OP_WRITE_RESPONSE_OK 	= 101,
	OP_WRITE_RESPONSE_ERR	= 102;

reg clk, rst_n;
integer i;


reg [7:0] uart_byte_out;
reg uart_byte_ready;
reg uart_busy;
reg [15:0] perceptron_weight1, perceptron_weight2, perceptron_result;

wire [7:0] byte_to_send;
wire [15:0] weight1_new, weight2_new, input1_new, input2_new;
wire send_byte, weight_write, input_write, clear;

comm_controller comm_controller(
    .rst_n(rst_n),
    .clk(clk),
	
	.byte(uart_byte_out),
	.byte_ready(uart_byte_ready),
	.uart_busy(uart_busy),
	.weight1(perceptron_weight1),
	.weight2(perceptron_weight2),
	.result(perceptron_result),

	.uart_byte(byte_to_send),
	.weight1_new(weight1_new),
	.weight2_new(weight2_new),
	.data_in1(input1_new),
	.data_in2(input2_new),
	.uart_send(send_byte),
	.uart_clear(clear),
	.weight_write(weight_write),
	.input_write(input_write)
);



initial begin
    $dumpvars(0, comm_controller);
end


always #(clk_pulse_width/2) clk = !clk;


initial begin
	$monitor("Time %d", $time);
	clk = 0;
    rst_n = 0;
	repeat (5) @(negedge clk);
	rst_n = 1;
end


initial begin
	uart_byte_out = 0;
	uart_byte_ready = 0;
	uart_busy = 0;
	perceptron_weight1 = 101;
	perceptron_weight2 = 102;
	perceptron_result =  103;

	wait( rst_n );
	@(negedge clk);
	$monitor("[Time %d]: Started testbench", $time);




	$monitor("[Time %d]: Testing write weight operation", $time);
	repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);
	uart_byte_out = OP_WRITE_WEIGHTS;
	uart_byte_ready = 1;
	wait(clear);
	uart_byte_ready = 0;

	for (i = 0; i < 4; i = i+1) begin
		repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);
		uart_byte_out = 50 + i;
		uart_byte_ready = 1;
		wait(clear);
		uart_byte_ready = 0;
	end



	$monitor("[Time %d]: Testing write input operation", $time);
	repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);
	uart_byte_out = OP_WRITE_INPUTS;
	uart_byte_ready = 1;
	wait(clear);
	uart_byte_ready = 0;

	for (i = 0; i < 4; i = i+1) begin
		repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);
		uart_byte_out = 70 + i;
		uart_byte_ready = 1;
		wait(clear);
		uart_byte_ready = 0;
	end




	$monitor("[Time %d]: Testing read", $time);
	repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);
	uart_byte_out = OP_READ;
	uart_byte_ready = 1;
	wait(clear);
	uart_byte_ready = 0;	

	for (i = 0; i < 6; i = i+1) begin
		wait(send_byte);
		uart_busy = 1;
		repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);
		uart_busy = 0;
	end

	repeat (8*clock_frequency/uart_baud_rate) @(negedge clk);

	$finish;
end

endmodule