data/full_repos/permissive/124591763/debounce/sig_deb.v
1: b'%Warning-WIDTH: data/full_repos/permissive/124591763/debounce/sig_deb.v:28: Operator OR expects 2 bits on the RHS, but RHS\'s VARREF \'i_sig\' generates 1 bits.\n                                                                          : ... In instance sig_deb\n        sync <= (sync << 1) | i_sig;\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/124591763/debounce/sig_deb.v:50: Operator OR expects 4 bits on the RHS, but RHS\'s VARREF \'sig_s\' generates 1 bits.\n                                                                          : ... In instance sig_deb\n        else if (tck) shft <= (shft << 1) | sig_s;\n                                          ^\n%Error: Exiting due to 2 warning(s)\n'
module sig_deb #(
    parameter CLKS_PER_SMPL = 16,
    parameter SMPL_CNT      = 4
) (
    input  wire clk,

    input  wire i_sig,

    output wire o_sig
);


    reg  [ 1:0] sync  = 2'b00;
    wire        sig_s = sync[1];


    always @ (posedge clk) begin
        sync <= (sync << 1) | i_sig;
    end


    reg  [CLKS_PER_SMPL - 1:0] cnt = {CLKS_PER_SMPL{1'b0}};
    wire                       tck = &cnt;


    always @ (posedge clk) begin
        if (~sig_s | tck) begin
            cnt <= {CLKS_PER_SMPL{1'b0}};
        end else begin
            cnt <= cnt + 'h1;
        end
    end


    reg  [SMPL_CNT - 1:0] shft  = {SMPL_CNT{1'b0}};


    always @ (posedge clk) begin
        if (~sig_s)   shft <= {SMPL_CNT{1'b0}};
        else if (tck) shft <= (shft << 1) | sig_s;
    end


    assign o_sig = &shft;

endmodule
module sig_deb #(
    parameter CLKS_PER_SMPL = 16,
    parameter SMPL_CNT      = 4
) (
    input  wire clk,

    input  wire i_sig,

    output wire o_sig
);



    reg  [ 1:0] sync  = 2'b00;
    wire        sig_s = sync[1];


    always @ (posedge clk) begin
        sync <= (sync << 1) | i_sig;
    end


    reg  [CLKS_PER_SMPL - 1:0] cnt = {CLKS_PER_SMPL{1'b0}};
    wire                       tck = &cnt;


    always @ (posedge clk) begin
        if (~sig_s | tck) begin
            cnt <= {CLKS_PER_SMPL{1'b0}};
        end else begin
            cnt <= cnt + 'h1;
        end
    end


    reg  [SMPL_CNT - 1:0] shft  = {SMPL_CNT{1'b0}};


    always @ (posedge clk) begin
        if (~sig_s)   shft <= {SMPL_CNT{1'b0}};
        else if (tck) shft <= (shft << 1) | sig_s;
    end


    assign o_sig = &shft;

endmodule