data/full_repos/permissive/129127690/memory.v
 line:1: before: "dir"
1: b'%Warning-WIDTH: data/full_repos/permissive/129127690/memory.v:10: Operator LT expects 64 bits on the LHS, but LHS\'s VARREF \'i\' generates 32 bits.\n                                                                : ... In instance memory\n  for (i = 0; i < bus; i = i + 1) begin\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module  memory #(parameter time dir = 16, parameter time bus = 2**dir) 
	(input [dir-1:0]da,addr_write,input [dir-1:0] write_data,input clk,memwrite,memread,
	output reg [dir-1:0] doa);

	reg [dir-1:0] my_memory [0:bus-1];	
	
	integer i;

	initial begin
		for (i = 0; i < bus; i = i + 1) begin
			my_memory[i] = 0;
		end	
	end
	


	always @(posedge clk) begin

	if (memread == 1'b1) begin
		doa <= my_memory[da];
	end
	end
	
	
	always @(negedge clk) begin
	if (memwrite == 1'b1) begin
		my_memory[addr_write] <= write_data;
	end
	end

endmodule
module  memory #(parameter time dir = 16, parameter time bus = 2**dir) 
	(input [dir-1:0]da,addr_write,input [dir-1:0] write_data,input clk,memwrite,memread,
	output reg [dir-1:0] doa);


	reg [dir-1:0] my_memory [0:bus-1];	
	
	integer i;

	initial begin
		for (i = 0; i < bus; i = i + 1) begin
			my_memory[i] = 0;
		end	
	end
	


	always @(posedge clk) begin

	if (memread == 1'b1) begin
		doa <= my_memory[da];
	end
	end
	
	
	always @(negedge clk) begin
	if (memwrite == 1'b1) begin
		my_memory[addr_write] <= write_data;
	end
	end

endmodule