data/full_repos/permissive/185658197/src/step-4/verilog/testbench.v
 line:53: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/185658197/src/step-4/verilog/testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/185658197/src/step-4/verilog/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #10;  \n      ^\n%Error: data/full_repos/permissive/185658197/src/step-4/verilog/testbench.v:9: Cannot find file containing module: \'Multiplier\'\n  Multiplier multiplier(\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/185658197/src/step-4/verilog,data/full_repos/permissive/185658197/Multiplier\n             data/full_repos/permissive/185658197/src/step-4/verilog,data/full_repos/permissive/185658197/Multiplier.v\n             data/full_repos/permissive/185658197/src/step-4/verilog,data/full_repos/permissive/185658197/Multiplier.sv\n             Multiplier\n             Multiplier.v\n             Multiplier.sv\n             obj_dir/Multiplier\n             obj_dir/Multiplier.v\n             obj_dir/Multiplier.sv\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-4/verilog/testbench.v:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'p\' generates 16 bits.\n                                                                                      : ... In instance Testbench\n        result = p;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-4/verilog/testbench.v:30: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                                      : ... In instance Testbench\n        result = $signed(p); \n               ^\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-4/verilog/testbench.v:51: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                      : ... In instance Testbench\n        a <= i;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-4/verilog/testbench.v:52: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                                      : ... In instance Testbench\n        b <= j;        \n          ^~\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-4/verilog/testbench.v:70: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                      : ... In instance Testbench\n        a <= i;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-4/verilog/testbench.v:71: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                                      : ... In instance Testbench\n        b <= j;\n          ^~\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Testbench;  
  reg [7:0] a;
  reg [7:0] b;
  reg sgnd;
  wire [15:0] p;
  reg clk;
  integer error_count, i, j, prev_i, prev_j;     
  
  Multiplier multiplier(
    .clk(clk),
    .a(a),
    .b(b), 
    .sgnd(sgnd),
    .p(p)
  );
  
  always
    #5 clk = ~clk;

  task test_result;
    integer result; 
    begin

      #10;  
      

      if (sgnd == 1'b0)
        result = p;
      else if (sgnd == 1'b1)
        result = $signed(p); 
      else
        $display("Error: invalid signed input");
        

      if (result != prev_i * prev_j) begin
        error_count = error_count + 1;
        $display("Error: a = %0d, b = %0d, expected = %0d, found = %0d", 
          prev_i, prev_j, prev_i*prev_j, result);    
      end  
    end
  endtask

  initial begin  

    $display("Running unsigned multiplication test...");
    clk <= 0;
    error_count <= 0;    
    sgnd <= 1'b0;
    for (i = 0; i < 256; i = i + 1) begin
      for (j = 0; j < 256; j = j + 1) begin
        a <= i;
        b <= j;        
        test_result;              
        prev_i <= i;
        prev_j <= j;           
      end      
    end  
    test_result;    
    $display("The test is completed with %0d error(s).", error_count);
    

    $display("Running signed multiplication test...");
    clk <= 0;
    error_count <= 0;    
    sgnd <= 1'b1;
    prev_i <= 'hX;
    prev_j <= 'hX;
    for (i = -128; i < 128; i = i + 1) begin
      for (j = -128; j < 128; j = j + 1) begin
        a <= i;
        b <= j;
        test_result;        
        prev_i <= i;
        prev_j <= j;           
      end      
    end  
    test_result;    
    $display("The test is completed with %0d error(s).", error_count);    
    $finish;
  end  
endmodule
module Testbench;
  
  reg [7:0] a;
  reg [7:0] b;
  reg sgnd;
  wire [15:0] p;
  reg clk;
  integer error_count, i, j, prev_i, prev_j;     
  
  Multiplier multiplier(
    .clk(clk),
    .a(a),
    .b(b), 
    .sgnd(sgnd),
    .p(p)
  );
  
  always
    #5 clk = ~clk;

  task test_result;
    integer result; 
    begin

      #10;  
      

      if (sgnd == 1'b0)
        result = p;
      else if (sgnd == 1'b1)
        result = $signed(p); 
      else
        $display("Error: invalid signed input");
        

      if (result != prev_i * prev_j) begin
        error_count = error_count + 1;
        $display("Error: a = %0d, b = %0d, expected = %0d, found = %0d", 
          prev_i, prev_j, prev_i*prev_j, result);    
      end  
    end
  endtask

  initial begin  

    $display("Running unsigned multiplication test...");
    clk <= 0;
    error_count <= 0;    
    sgnd <= 1'b0;
    for (i = 0; i < 256; i = i + 1) begin
      for (j = 0; j < 256; j = j + 1) begin
        a <= i;
        b <= j;        
        test_result;              
        prev_i <= i;
        prev_j <= j;           
      end      
    end  
    test_result;    
    $display("The test is completed with %0d error(s).", error_count);
    

    $display("Running signed multiplication test...");
    clk <= 0;
    error_count <= 0;    
    sgnd <= 1'b1;
    prev_i <= 'hX;
    prev_j <= 'hX;
    for (i = -128; i < 128; i = i + 1) begin
      for (j = -128; j < 128; j = j + 1) begin
        a <= i;
        b <= j;
        test_result;        
        prev_i <= i;
        prev_j <= j;           
      end      
    end  
    test_result;    
    $display("The test is completed with %0d error(s).", error_count);    
    $finish;
  end  
endmodule