data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v
1: b"%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:46: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\a_pad[2]/U0/U0  (.PAD(a[2]), .Y(\\a_pad[2]/U0/NET1 ));\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1,data/full_repos/permissive/165160692/IOPAD_IN\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1,data/full_repos/permissive/165160692/IOPAD_IN.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1,data/full_repos/permissive/165160692/IOPAD_IN.sv\n             IOPAD_IN\n             IOPAD_IN.v\n             IOPAD_IN.sv\n             obj_dir/IOPAD_IN\n             obj_dir/IOPAD_IN.v\n             obj_dir/IOPAD_IN.sv\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:47: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\a_pad[1]/U0/U0  (.PAD(a[1]), .Y(\\a_pad[1]/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:48: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\a_pad[3]/U0/U1  (.YIN(\\a_pad[3]/U0/NET1 ), .Y(\\a_c[3] ));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:49: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\shiftedcarry_pad[4]/U0/U1  (.D(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:53: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\shiftedcarry_pad[3]/U0/U1  (.D(N_38_i_0_c), .E(VCC), \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:56: Cannot find file containing module: 'XOR3'\n    XOR3 \\carry_generation.carrychain_2_1_SUM0_0  (.A(\\b_c[0] ), .B(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:58: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\b_pad[1]/U0/U1  (.YIN(\\b_pad[1]/U0/NET1 ), .Y(\\b_c[1] ));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:59: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\sum_pad[3]/U0/U1  (.D(\\sum_c[3] ), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:61: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\cout_pad/U0/U1  (.D(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:64: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\sum_pad[2]/U0/U0  (.D(\\sum_pad[2]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:66: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\shiftedcarry_pad[4]/U0/U0  (.D(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:69: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\shiftedcarry_pad[3]/U0/U0  (.D(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:72: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\b_pad[3]/U0/U1  (.YIN(\\b_pad[3]/U0/NET1 ), .Y(\\b_c[3] ));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:73: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\cout_pad/U0/U0  (.D(\\cout_pad/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:75: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\a_pad[0]/U0/U1  (.YIN(\\a_pad[0]/U0/NET1 ), .Y(\\a_c[0] ));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:76: Cannot find file containing module: 'MAJ3'\n    MAJ3 \\carry_generation.carrychain_2_1_CO0_i  (.A(\\a_c[0] ), .B(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:78: Cannot find file containing module: 'MAJ3'\n    MAJ3 \\carry_generation.carrychain_3_0_0_ADD_5x5_slow_I0_un1_CO1_i  \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:81: Cannot find file containing module: 'XOR3'\n    XOR3 \\carry_generation.carrychain_3_0_0_ADD_5x5_slow_I4_S_0  (.A(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:83: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\sum_pad[3]/U0/U0  (.D(\\sum_pad[3]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:85: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\b_pad[0]/U0/U0  (.PAD(b[0]), .Y(\\b_pad[0]/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:86: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\cin_pad/U0/U0  (.PAD(cin), .Y(\\cin_pad/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:87: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\a_pad[3]/U0/U0  (.PAD(a[3]), .Y(\\a_pad[3]/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:88: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\b_pad[2]/U0/U1  (.YIN(\\b_pad[2]/U0/NET1 ), .Y(\\b_c[2] ));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:89: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\b_pad[1]/U0/U0  (.PAD(b[1]), .Y(\\b_pad[1]/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:90: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\b_pad[3]/U0/U0  (.PAD(b[3]), .Y(\\b_pad[3]/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:91: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\sum_pad[1]/U0/U1  (.D(\\sum_c[1] ), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:93: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\cin_pad/U0/U1  (.YIN(\\cin_pad/U0/NET1 ), .Y(cin_c_c));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:94: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\a_pad[0]/U0/U0  (.PAD(a[0]), .Y(\\a_pad[0]/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:95: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\a_pad[2]/U0/U1  (.YIN(\\a_pad[2]/U0/NET1 ), .Y(\\a_c[2] ));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:96: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\a_pad[1]/U0/U1  (.YIN(\\a_pad[1]/U0/NET1 ), .Y(\\a_c[1] ));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:97: Cannot find file containing module: 'XOR3'\n    XOR3 \\carry_generation.carrychain_3_0_0_ADD_5x5_slow_I0_S_0  (.A(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:99: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\sum_pad[0]/U0/U1  (.D(\\sum_c[0] ), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:101: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\sum_pad[1]/U0/U0  (.D(\\sum_pad[1]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:103: Cannot find file containing module: 'MAJ3'\n    MAJ3 \\carry_generation.carrychain_3_0_0_ADD_5x5_slow_I4_un1_CO1_i  \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:106: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\shiftedcarry_pad[0]/U0/U1  (.D(cin_c_c), .E(VCC), \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:109: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\shiftedcarry_pad[0]/U0/U0  (.D(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:112: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\shiftedcarry_pad[2]/U0/U1  (.D(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:116: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\b_pad[2]/U0/U0  (.PAD(b[2]), .Y(\\b_pad[2]/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:117: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\shiftedcarry_pad[1]/U0/U1  (.D(N_5), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:120: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\shiftedcarry_pad[2]/U0/U0  (.D(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:123: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\sum_pad[0]/U0/U0  (.D(\\sum_pad[0]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:125: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\shiftedcarry_pad[1]/U0/U0  (.D(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:128: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\sum_pad[2]/U0/U1  (.D(\\sum_c[2] ), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:130: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\b_pad[0]/U0/U1  (.YIN(\\b_pad[0]/U0/NET1 ), .Y(\\b_c[0] ));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:131: Cannot find file containing module: 'MAJ3'\n    MAJ3 \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:135: Cannot find file containing module: 'XOR3'\n    XOR3 \\carry_generation.carrychain_3_0_0_ADD_5x5_slow_I2_S_0  (.A(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:138: Cannot find file containing module: 'GND'\n    GND GND_power_inst1 (.Y(GND_power_net1));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC283/designer/impl1/HC283_ba.v:139: Cannot find file containing module: 'VCC'\n    VCC VCC_power_inst1 (.Y(VCC_power_net1));\n    ^~~\n%Error: Exiting due to 48 error(s)\n"
module HC283(
       sum,
       cout,
       a,
       b,
       cin,
       shiftedcarry
    );
output [3:0] sum;
output cout;
input  [3:0] a;
input  [3:0] b;
input  cin;
output [4:0] shiftedcarry;

    wire ADD_5x5_slow_I0_un1_CO1_i, N_5, 
        \carry_generation.carrychain_3_0_0.N_7 , \sum_c[0] , 
        \sum_c[1] , \sum_c[2] , \sum_c[3] , \a_c[0] , \a_c[1] , 
        \a_c[2] , \a_c[3] , \b_c[0] , \b_c[1] , \b_c[2] , \b_c[3] , 
        cin_c_c, N_38_i_0_c, \shiftedcarry_pad[1]/U0/NET1 , 
        \shiftedcarry_pad[1]/U0/NET2 , \b_pad[3]/U0/NET1 , 
        \b_pad[2]/U0/NET1 , \shiftedcarry_pad[3]/U0/NET1 , 
        \shiftedcarry_pad[3]/U0/NET2 , \sum_pad[1]/U0/NET1 , 
        \sum_pad[1]/U0/NET2 , \a_pad[0]/U0/NET1 , 
        \shiftedcarry_pad[2]/U0/NET1 , \shiftedcarry_pad[2]/U0/NET2 , 
        \sum_pad[3]/U0/NET1 , \sum_pad[3]/U0/NET2 , \b_pad[1]/U0/NET1 , 
        \shiftedcarry_pad[4]/U0/NET1 , \shiftedcarry_pad[4]/U0/NET2 , 
        \sum_pad[2]/U0/NET1 , \sum_pad[2]/U0/NET2 , \a_pad[2]/U0/NET1 , 
        \a_pad[3]/U0/NET1 , \cout_pad/U0/NET1 , \cout_pad/U0/NET2 , 
        \sum_pad[0]/U0/NET1 , \sum_pad[0]/U0/NET2 , \a_pad[1]/U0/NET1 , 
        \shiftedcarry_pad[0]/U0/NET1 , \shiftedcarry_pad[0]/U0/NET2 , 
        VCC, \cin_pad/U0/NET1 , \b_pad[0]/U0/NET1 , GND, AFLSDF_VCC, 
        AFLSDF_GND;
    wire GND_power_net1;
    wire VCC_power_net1;
    assign GND = GND_power_net1;
    assign AFLSDF_GND = GND_power_net1;
    assign VCC = VCC_power_net1;
    assign AFLSDF_VCC = VCC_power_net1;
    
    IOPAD_IN \a_pad[2]/U0/U0  (.PAD(a[2]), .Y(\a_pad[2]/U0/NET1 ));
    IOPAD_IN \a_pad[1]/U0/U0  (.PAD(a[1]), .Y(\a_pad[1]/U0/NET1 ));
    IOIN_IB \a_pad[3]/U0/U1  (.YIN(\a_pad[3]/U0/NET1 ), .Y(\a_c[3] ));
    IOTRI_OB_EB \shiftedcarry_pad[4]/U0/U1  (.D(
        \carry_generation.carrychain_3_0_0.N_7 ), .E(VCC), .DOUT(
        \shiftedcarry_pad[4]/U0/NET1 ), .EOUT(
        \shiftedcarry_pad[4]/U0/NET2 ));
    IOTRI_OB_EB \shiftedcarry_pad[3]/U0/U1  (.D(N_38_i_0_c), .E(VCC), 
        .DOUT(\shiftedcarry_pad[3]/U0/NET1 ), .EOUT(
        \shiftedcarry_pad[3]/U0/NET2 ));
    XOR3 \carry_generation.carrychain_2_1_SUM0_0  (.A(\b_c[0] ), .B(
        \a_c[0] ), .C(cin_c_c), .Y(\sum_c[0] ));
    IOIN_IB \b_pad[1]/U0/U1  (.YIN(\b_pad[1]/U0/NET1 ), .Y(\b_c[1] ));
    IOTRI_OB_EB \sum_pad[3]/U0/U1  (.D(\sum_c[3] ), .E(VCC), .DOUT(
        \sum_pad[3]/U0/NET1 ), .EOUT(\sum_pad[3]/U0/NET2 ));
    IOTRI_OB_EB \cout_pad/U0/U1  (.D(
        \carry_generation.carrychain_3_0_0.N_7 ), .E(VCC), .DOUT(
        \cout_pad/U0/NET1 ), .EOUT(\cout_pad/U0/NET2 ));
    IOPAD_TRI \sum_pad[2]/U0/U0  (.D(\sum_pad[2]/U0/NET1 ), .E(
        \sum_pad[2]/U0/NET2 ), .PAD(sum[2]));
    IOPAD_TRI \shiftedcarry_pad[4]/U0/U0  (.D(
        \shiftedcarry_pad[4]/U0/NET1 ), .E(
        \shiftedcarry_pad[4]/U0/NET2 ), .PAD(shiftedcarry[4]));
    IOPAD_TRI \shiftedcarry_pad[3]/U0/U0  (.D(
        \shiftedcarry_pad[3]/U0/NET1 ), .E(
        \shiftedcarry_pad[3]/U0/NET2 ), .PAD(shiftedcarry[3]));
    IOIN_IB \b_pad[3]/U0/U1  (.YIN(\b_pad[3]/U0/NET1 ), .Y(\b_c[3] ));
    IOPAD_TRI \cout_pad/U0/U0  (.D(\cout_pad/U0/NET1 ), .E(
        \cout_pad/U0/NET2 ), .PAD(cout));
    IOIN_IB \a_pad[0]/U0/U1  (.YIN(\a_pad[0]/U0/NET1 ), .Y(\a_c[0] ));
    MAJ3 \carry_generation.carrychain_2_1_CO0_i  (.A(\a_c[0] ), .B(
        cin_c_c), .C(\b_c[0] ), .Y(N_5));
    MAJ3 \carry_generation.carrychain_3_0_0_ADD_5x5_slow_I0_un1_CO1_i  
        (.A(N_5), .B(\b_c[1] ), .C(\a_c[1] ), .Y(
        ADD_5x5_slow_I0_un1_CO1_i));
    XOR3 \carry_generation.carrychain_3_0_0_ADD_5x5_slow_I4_S_0  (.A(
        \a_c[3] ), .B(N_38_i_0_c), .C(\b_c[3] ), .Y(\sum_c[3] ));
    IOPAD_TRI \sum_pad[3]/U0/U0  (.D(\sum_pad[3]/U0/NET1 ), .E(
        \sum_pad[3]/U0/NET2 ), .PAD(sum[3]));
    IOPAD_IN \b_pad[0]/U0/U0  (.PAD(b[0]), .Y(\b_pad[0]/U0/NET1 ));
    IOPAD_IN \cin_pad/U0/U0  (.PAD(cin), .Y(\cin_pad/U0/NET1 ));
    IOPAD_IN \a_pad[3]/U0/U0  (.PAD(a[3]), .Y(\a_pad[3]/U0/NET1 ));
    IOIN_IB \b_pad[2]/U0/U1  (.YIN(\b_pad[2]/U0/NET1 ), .Y(\b_c[2] ));
    IOPAD_IN \b_pad[1]/U0/U0  (.PAD(b[1]), .Y(\b_pad[1]/U0/NET1 ));
    IOPAD_IN \b_pad[3]/U0/U0  (.PAD(b[3]), .Y(\b_pad[3]/U0/NET1 ));
    IOTRI_OB_EB \sum_pad[1]/U0/U1  (.D(\sum_c[1] ), .E(VCC), .DOUT(
        \sum_pad[1]/U0/NET1 ), .EOUT(\sum_pad[1]/U0/NET2 ));
    IOIN_IB \cin_pad/U0/U1  (.YIN(\cin_pad/U0/NET1 ), .Y(cin_c_c));
    IOPAD_IN \a_pad[0]/U0/U0  (.PAD(a[0]), .Y(\a_pad[0]/U0/NET1 ));
    IOIN_IB \a_pad[2]/U0/U1  (.YIN(\a_pad[2]/U0/NET1 ), .Y(\a_c[2] ));
    IOIN_IB \a_pad[1]/U0/U1  (.YIN(\a_pad[1]/U0/NET1 ), .Y(\a_c[1] ));
    XOR3 \carry_generation.carrychain_3_0_0_ADD_5x5_slow_I0_S_0  (.A(
        \a_c[1] ), .B(N_5), .C(\b_c[1] ), .Y(\sum_c[1] ));
    IOTRI_OB_EB \sum_pad[0]/U0/U1  (.D(\sum_c[0] ), .E(VCC), .DOUT(
        \sum_pad[0]/U0/NET1 ), .EOUT(\sum_pad[0]/U0/NET2 ));
    IOPAD_TRI \sum_pad[1]/U0/U0  (.D(\sum_pad[1]/U0/NET1 ), .E(
        \sum_pad[1]/U0/NET2 ), .PAD(sum[1]));
    MAJ3 \carry_generation.carrychain_3_0_0_ADD_5x5_slow_I4_un1_CO1_i  
        (.A(\a_c[3] ), .B(\b_c[3] ), .C(N_38_i_0_c), .Y(
        \carry_generation.carrychain_3_0_0.N_7 ));
    IOTRI_OB_EB \shiftedcarry_pad[0]/U0/U1  (.D(cin_c_c), .E(VCC), 
        .DOUT(\shiftedcarry_pad[0]/U0/NET1 ), .EOUT(
        \shiftedcarry_pad[0]/U0/NET2 ));
    IOPAD_TRI \shiftedcarry_pad[0]/U0/U0  (.D(
        \shiftedcarry_pad[0]/U0/NET1 ), .E(
        \shiftedcarry_pad[0]/U0/NET2 ), .PAD(shiftedcarry[0]));
    IOTRI_OB_EB \shiftedcarry_pad[2]/U0/U1  (.D(
        ADD_5x5_slow_I0_un1_CO1_i), .E(VCC), .DOUT(
        \shiftedcarry_pad[2]/U0/NET1 ), .EOUT(
        \shiftedcarry_pad[2]/U0/NET2 ));
    IOPAD_IN \b_pad[2]/U0/U0  (.PAD(b[2]), .Y(\b_pad[2]/U0/NET1 ));
    IOTRI_OB_EB \shiftedcarry_pad[1]/U0/U1  (.D(N_5), .E(VCC), .DOUT(
        \shiftedcarry_pad[1]/U0/NET1 ), .EOUT(
        \shiftedcarry_pad[1]/U0/NET2 ));
    IOPAD_TRI \shiftedcarry_pad[2]/U0/U0  (.D(
        \shiftedcarry_pad[2]/U0/NET1 ), .E(
        \shiftedcarry_pad[2]/U0/NET2 ), .PAD(shiftedcarry[2]));
    IOPAD_TRI \sum_pad[0]/U0/U0  (.D(\sum_pad[0]/U0/NET1 ), .E(
        \sum_pad[0]/U0/NET2 ), .PAD(sum[0]));
    IOPAD_TRI \shiftedcarry_pad[1]/U0/U0  (.D(
        \shiftedcarry_pad[1]/U0/NET1 ), .E(
        \shiftedcarry_pad[1]/U0/NET2 ), .PAD(shiftedcarry[1]));
    IOTRI_OB_EB \sum_pad[2]/U0/U1  (.D(\sum_c[2] ), .E(VCC), .DOUT(
        \sum_pad[2]/U0/NET1 ), .EOUT(\sum_pad[2]/U0/NET2 ));
    IOIN_IB \b_pad[0]/U0/U1  (.YIN(\b_pad[0]/U0/NET1 ), .Y(\b_c[0] ));
    MAJ3 
        \carry_generation.carrychain_3_0_0_ADD_5x5_slow_I2_un1_CO1_i_o3  
        (.A(ADD_5x5_slow_I0_un1_CO1_i), .B(\a_c[2] ), .C(\b_c[2] ), .Y(
        N_38_i_0_c));
    XOR3 \carry_generation.carrychain_3_0_0_ADD_5x5_slow_I2_S_0  (.A(
        \a_c[2] ), .B(ADD_5x5_slow_I0_un1_CO1_i), .C(\b_c[2] ), .Y(
        \sum_c[2] ));
    GND GND_power_inst1 (.Y(GND_power_net1));
    VCC VCC_power_inst1 (.Y(VCC_power_net1));
    
endmodule
module HC283(
       sum,
       cout,
       a,
       b,
       cin,
       shiftedcarry
    );

output [3:0] sum;
output cout;
input  [3:0] a;
input  [3:0] b;
input  cin;
output [4:0] shiftedcarry;

    wire ADD_5x5_slow_I0_un1_CO1_i, N_5, 
        \carry_generation.carrychain_3_0_0.N_7 , \sum_c[0] , 
        \sum_c[1] , \sum_c[2] , \sum_c[3] , \a_c[0] , \a_c[1] , 
        \a_c[2] , \a_c[3] , \b_c[0] , \b_c[1] , \b_c[2] , \b_c[3] , 
        cin_c_c, N_38_i_0_c, \shiftedcarry_pad[1]/U0/NET1 , 
        \shiftedcarry_pad[1]/U0/NET2 , \b_pad[3]/U0/NET1 , 
        \b_pad[2]/U0/NET1 , \shiftedcarry_pad[3]/U0/NET1 , 
        \shiftedcarry_pad[3]/U0/NET2 , \sum_pad[1]/U0/NET1 , 
        \sum_pad[1]/U0/NET2 , \a_pad[0]/U0/NET1 , 
        \shiftedcarry_pad[2]/U0/NET1 , \shiftedcarry_pad[2]/U0/NET2 , 
        \sum_pad[3]/U0/NET1 , \sum_pad[3]/U0/NET2 , \b_pad[1]/U0/NET1 , 
        \shiftedcarry_pad[4]/U0/NET1 , \shiftedcarry_pad[4]/U0/NET2 , 
        \sum_pad[2]/U0/NET1 , \sum_pad[2]/U0/NET2 , \a_pad[2]/U0/NET1 , 
        \a_pad[3]/U0/NET1 , \cout_pad/U0/NET1 , \cout_pad/U0/NET2 , 
        \sum_pad[0]/U0/NET1 , \sum_pad[0]/U0/NET2 , \a_pad[1]/U0/NET1 , 
        \shiftedcarry_pad[0]/U0/NET1 , \shiftedcarry_pad[0]/U0/NET2 , 
        VCC, \cin_pad/U0/NET1 , \b_pad[0]/U0/NET1 , GND, AFLSDF_VCC, 
        AFLSDF_GND;
    wire GND_power_net1;
    wire VCC_power_net1;
    assign GND = GND_power_net1;
    assign AFLSDF_GND = GND_power_net1;
    assign VCC = VCC_power_net1;
    assign AFLSDF_VCC = VCC_power_net1;
    
    IOPAD_IN \a_pad[2]/U0/U0  (.PAD(a[2]), .Y(\a_pad[2]/U0/NET1 ));
    IOPAD_IN \a_pad[1]/U0/U0  (.PAD(a[1]), .Y(\a_pad[1]/U0/NET1 ));
    IOIN_IB \a_pad[3]/U0/U1  (.YIN(\a_pad[3]/U0/NET1 ), .Y(\a_c[3] ));
    IOTRI_OB_EB \shiftedcarry_pad[4]/U0/U1  (.D(
        \carry_generation.carrychain_3_0_0.N_7 ), .E(VCC), .DOUT(
        \shiftedcarry_pad[4]/U0/NET1 ), .EOUT(
        \shiftedcarry_pad[4]/U0/NET2 ));
    IOTRI_OB_EB \shiftedcarry_pad[3]/U0/U1  (.D(N_38_i_0_c), .E(VCC), 
        .DOUT(\shiftedcarry_pad[3]/U0/NET1 ), .EOUT(
        \shiftedcarry_pad[3]/U0/NET2 ));
    XOR3 \carry_generation.carrychain_2_1_SUM0_0  (.A(\b_c[0] ), .B(
        \a_c[0] ), .C(cin_c_c), .Y(\sum_c[0] ));
    IOIN_IB \b_pad[1]/U0/U1  (.YIN(\b_pad[1]/U0/NET1 ), .Y(\b_c[1] ));
    IOTRI_OB_EB \sum_pad[3]/U0/U1  (.D(\sum_c[3] ), .E(VCC), .DOUT(
        \sum_pad[3]/U0/NET1 ), .EOUT(\sum_pad[3]/U0/NET2 ));
    IOTRI_OB_EB \cout_pad/U0/U1  (.D(
        \carry_generation.carrychain_3_0_0.N_7 ), .E(VCC), .DOUT(
        \cout_pad/U0/NET1 ), .EOUT(\cout_pad/U0/NET2 ));
    IOPAD_TRI \sum_pad[2]/U0/U0  (.D(\sum_pad[2]/U0/NET1 ), .E(
        \sum_pad[2]/U0/NET2 ), .PAD(sum[2]));
    IOPAD_TRI \shiftedcarry_pad[4]/U0/U0  (.D(
        \shiftedcarry_pad[4]/U0/NET1 ), .E(
        \shiftedcarry_pad[4]/U0/NET2 ), .PAD(shiftedcarry[4]));
    IOPAD_TRI \shiftedcarry_pad[3]/U0/U0  (.D(
        \shiftedcarry_pad[3]/U0/NET1 ), .E(
        \shiftedcarry_pad[3]/U0/NET2 ), .PAD(shiftedcarry[3]));
    IOIN_IB \b_pad[3]/U0/U1  (.YIN(\b_pad[3]/U0/NET1 ), .Y(\b_c[3] ));
    IOPAD_TRI \cout_pad/U0/U0  (.D(\cout_pad/U0/NET1 ), .E(
        \cout_pad/U0/NET2 ), .PAD(cout));
    IOIN_IB \a_pad[0]/U0/U1  (.YIN(\a_pad[0]/U0/NET1 ), .Y(\a_c[0] ));
    MAJ3 \carry_generation.carrychain_2_1_CO0_i  (.A(\a_c[0] ), .B(
        cin_c_c), .C(\b_c[0] ), .Y(N_5));
    MAJ3 \carry_generation.carrychain_3_0_0_ADD_5x5_slow_I0_un1_CO1_i  
        (.A(N_5), .B(\b_c[1] ), .C(\a_c[1] ), .Y(
        ADD_5x5_slow_I0_un1_CO1_i));
    XOR3 \carry_generation.carrychain_3_0_0_ADD_5x5_slow_I4_S_0  (.A(
        \a_c[3] ), .B(N_38_i_0_c), .C(\b_c[3] ), .Y(\sum_c[3] ));
    IOPAD_TRI \sum_pad[3]/U0/U0  (.D(\sum_pad[3]/U0/NET1 ), .E(
        \sum_pad[3]/U0/NET2 ), .PAD(sum[3]));
    IOPAD_IN \b_pad[0]/U0/U0  (.PAD(b[0]), .Y(\b_pad[0]/U0/NET1 ));
    IOPAD_IN \cin_pad/U0/U0  (.PAD(cin), .Y(\cin_pad/U0/NET1 ));
    IOPAD_IN \a_pad[3]/U0/U0  (.PAD(a[3]), .Y(\a_pad[3]/U0/NET1 ));
    IOIN_IB \b_pad[2]/U0/U1  (.YIN(\b_pad[2]/U0/NET1 ), .Y(\b_c[2] ));
    IOPAD_IN \b_pad[1]/U0/U0  (.PAD(b[1]), .Y(\b_pad[1]/U0/NET1 ));
    IOPAD_IN \b_pad[3]/U0/U0  (.PAD(b[3]), .Y(\b_pad[3]/U0/NET1 ));
    IOTRI_OB_EB \sum_pad[1]/U0/U1  (.D(\sum_c[1] ), .E(VCC), .DOUT(
        \sum_pad[1]/U0/NET1 ), .EOUT(\sum_pad[1]/U0/NET2 ));
    IOIN_IB \cin_pad/U0/U1  (.YIN(\cin_pad/U0/NET1 ), .Y(cin_c_c));
    IOPAD_IN \a_pad[0]/U0/U0  (.PAD(a[0]), .Y(\a_pad[0]/U0/NET1 ));
    IOIN_IB \a_pad[2]/U0/U1  (.YIN(\a_pad[2]/U0/NET1 ), .Y(\a_c[2] ));
    IOIN_IB \a_pad[1]/U0/U1  (.YIN(\a_pad[1]/U0/NET1 ), .Y(\a_c[1] ));
    XOR3 \carry_generation.carrychain_3_0_0_ADD_5x5_slow_I0_S_0  (.A(
        \a_c[1] ), .B(N_5), .C(\b_c[1] ), .Y(\sum_c[1] ));
    IOTRI_OB_EB \sum_pad[0]/U0/U1  (.D(\sum_c[0] ), .E(VCC), .DOUT(
        \sum_pad[0]/U0/NET1 ), .EOUT(\sum_pad[0]/U0/NET2 ));
    IOPAD_TRI \sum_pad[1]/U0/U0  (.D(\sum_pad[1]/U0/NET1 ), .E(
        \sum_pad[1]/U0/NET2 ), .PAD(sum[1]));
    MAJ3 \carry_generation.carrychain_3_0_0_ADD_5x5_slow_I4_un1_CO1_i  
        (.A(\a_c[3] ), .B(\b_c[3] ), .C(N_38_i_0_c), .Y(
        \carry_generation.carrychain_3_0_0.N_7 ));
    IOTRI_OB_EB \shiftedcarry_pad[0]/U0/U1  (.D(cin_c_c), .E(VCC), 
        .DOUT(\shiftedcarry_pad[0]/U0/NET1 ), .EOUT(
        \shiftedcarry_pad[0]/U0/NET2 ));
    IOPAD_TRI \shiftedcarry_pad[0]/U0/U0  (.D(
        \shiftedcarry_pad[0]/U0/NET1 ), .E(
        \shiftedcarry_pad[0]/U0/NET2 ), .PAD(shiftedcarry[0]));
    IOTRI_OB_EB \shiftedcarry_pad[2]/U0/U1  (.D(
        ADD_5x5_slow_I0_un1_CO1_i), .E(VCC), .DOUT(
        \shiftedcarry_pad[2]/U0/NET1 ), .EOUT(
        \shiftedcarry_pad[2]/U0/NET2 ));
    IOPAD_IN \b_pad[2]/U0/U0  (.PAD(b[2]), .Y(\b_pad[2]/U0/NET1 ));
    IOTRI_OB_EB \shiftedcarry_pad[1]/U0/U1  (.D(N_5), .E(VCC), .DOUT(
        \shiftedcarry_pad[1]/U0/NET1 ), .EOUT(
        \shiftedcarry_pad[1]/U0/NET2 ));
    IOPAD_TRI \shiftedcarry_pad[2]/U0/U0  (.D(
        \shiftedcarry_pad[2]/U0/NET1 ), .E(
        \shiftedcarry_pad[2]/U0/NET2 ), .PAD(shiftedcarry[2]));
    IOPAD_TRI \sum_pad[0]/U0/U0  (.D(\sum_pad[0]/U0/NET1 ), .E(
        \sum_pad[0]/U0/NET2 ), .PAD(sum[0]));
    IOPAD_TRI \shiftedcarry_pad[1]/U0/U0  (.D(
        \shiftedcarry_pad[1]/U0/NET1 ), .E(
        \shiftedcarry_pad[1]/U0/NET2 ), .PAD(shiftedcarry[1]));
    IOTRI_OB_EB \sum_pad[2]/U0/U1  (.D(\sum_c[2] ), .E(VCC), .DOUT(
        \sum_pad[2]/U0/NET1 ), .EOUT(\sum_pad[2]/U0/NET2 ));
    IOIN_IB \b_pad[0]/U0/U1  (.YIN(\b_pad[0]/U0/NET1 ), .Y(\b_c[0] ));
    MAJ3 
        \carry_generation.carrychain_3_0_0_ADD_5x5_slow_I2_un1_CO1_i_o3  
        (.A(ADD_5x5_slow_I0_un1_CO1_i), .B(\a_c[2] ), .C(\b_c[2] ), .Y(
        N_38_i_0_c));
    XOR3 \carry_generation.carrychain_3_0_0_ADD_5x5_slow_I2_S_0  (.A(
        \a_c[2] ), .B(ADD_5x5_slow_I0_un1_CO1_i), .C(\b_c[2] ), .Y(
        \sum_c[2] ));
    GND GND_power_inst1 (.Y(GND_power_net1));
    VCC VCC_power_inst1 (.Y(VCC_power_net1));
    
endmodule