data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v
 line:85: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:65: Unsupported: Ignoring delay on this delayed statement.\nalways #25  TCK = ~TCK;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #50 TRST = 1\'b0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #20000 TRST = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #1000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:98: Unsupported: Ignoring delay on this delayed statement.\n    #20000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #10000\n  ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:144: syntax error, unexpected \'@\'\n  repeat(2) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:146: syntax error, unexpected \'@\'\n  repeat(2) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:148: syntax error, unexpected \'@\'\n  repeat(2) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:151: syntax error, unexpected \'@\'\n  repeat(1) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:153: syntax error, unexpected \'@\'\n  repeat(1) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:155: syntax error, unexpected \'@\'\n  repeat(1) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:157: syntax error, unexpected \'@\'\n  repeat(1) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:160: syntax error, unexpected \'@\'\n  repeat(3) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:162: syntax error, unexpected \'@\'\n  repeat(2) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:166: syntax error, unexpected \'@\'\n    repeat(1) @(negedge TCK);\n              ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:178: syntax error, unexpected \'@\'\n    repeat(1) @(posedge TCK);\n              ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:185: syntax error, unexpected \'@\'\n  repeat(1) @(posedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:187: syntax error, unexpected \'@\'\n  repeat(3) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:198: syntax error, unexpected \'@\'\n  repeat(2) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:200: syntax error, unexpected \'@\'\n  repeat(2) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:202: syntax error, unexpected \'@\'\n  repeat(2) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:205: syntax error, unexpected \'@\'\n  repeat(1) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:207: syntax error, unexpected \'@\'\n  repeat(1) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:209: syntax error, unexpected \'@\'\n  repeat(1) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:211: syntax error, unexpected \'@\'\n  repeat(1) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:214: syntax error, unexpected \'@\'\n  repeat(3) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:216: syntax error, unexpected \'@\'\n  repeat(2) @(negedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:218: syntax error, unexpected \'@\'\n  repeat(1) @(posedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:222: syntax error, unexpected \'@\'\n    repeat(1) @(posedge TCK);\n              ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:229: syntax error, unexpected \'@\'\n  repeat(1) @(posedge TCK);\n            ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/ejtag_virtual_host.v:231: syntax error, unexpected \'@\'\n  repeat(3) @(negedge TCK);\n            ^\n%Error: Exiting due to 26 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ejtag_virtual_host (
    TCK,
    TMS,
    TDO,
    TDI,
    TRST
);

input   TDO;
output  TCK, TDI, TMS, TRST;
reg [31:0] control;
reg [31:0] impcode;
reg [31:0] idcode;
reg [31:0] data;
reg [31:0] addr;
reg [31:0] pc;
reg     TDI, TCK, TMS, TRST;

reg     pracc;
reg     prnw;
reg [1:0] psz;
reg     rocc;
reg     proben;
reg     probtrap;

reg     dmseg_service;
reg     service_busy;

reg [31:0] memory [{19{1'b1}}:0];
integer j;

always #25  TCK = ~TCK;

initial
begin
  TMS = 0;
  for(j=0; j<128; j=j+1)
    memory[j]=32'h0;
  
  
  dmseg_service = 1'b0;
  service_busy = 1'b0;
  #50 TRST = 1'b0; 
  TRST  = 1'b0;
  TCK   = 1'b0;
  pracc = 1'b0;
  rocc  = 1'b0;
  #20000 TRST = 1'b1;

  $display("ejtag reboot done!");
  #1000
  query_reg32(5'ha, control);
  start_dmseg_service;





end

initial
begin
  #10000
  begin
    #20000
    if(dmseg_service)
    begin
      service_busy = 1'b1;
      query_reg32(5'h01, idcode );
      $display("Idcode:%x Version:%x PartNumber:%x ManufID:%x\n",
                idcode,idcode[31:28],idcode[27:12],idcode[11:1]);

      query_reg32(5'h03, impcode);
      $display("Impcode:%x EJTAGver:%x DINTsup:%x NoDMA:%x MIPS32/64:%x\n",
                impcode,impcode[31:29],impcode[24],impcode[14],impcode[0]);
      service_busy = 1'b0;
    end
    if((!service_busy)&&dmseg_service)
    end_dmseg_service;
  end
end


task start_dmseg_service;
begin
  dmseg_service = 1'b1;
  $display("dmseg service start!");
end
endtask

task end_dmseg_service;
begin
  dmseg_service = 1'b0;
  query_reg32(5'ha, control);
  control[31] = 1'b0;
  control[15] = 1'b0;
  control[14] = 1'b0;
  control[12] = 1'b0;
  write_reg32(5'ha, control);
  $display("dmseg service end!");
end
endtask

task query_reg32;
input [4:0] reg_inst;
output [31:0] reg_data;
reg [31:0] reg_rd_data;
integer i; 
begin
  TMS = 0;
  repeat(2) @(negedge TCK);
  TMS = 1;
  repeat(2) @(negedge TCK);
  TMS = 0;
  repeat(2) @(negedge TCK);

  TDI = reg_inst[0];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[1];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[2];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[3];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[4];
  TMS = 1;
  repeat(3) @(negedge TCK);
  TMS = 0;
  repeat(2) @(negedge TCK);
   
  for(i = 0; i < 32; i = i+1)
  begin
    repeat(1) @(negedge TCK);
    reg_data[i] = TDO;
  end

  if (reg_data[18]==1'b0) 
    reg_rd_data[31:0] = {reg_data[31:19], 1'b1, reg_data[17:0]};
  else 
    reg_rd_data[31:0] = reg_data[31:0];
    
  for(i = 0; i < 32; i = i+1)
  begin
    TDI = reg_rd_data[i];
    repeat(1) @(posedge TCK);
    if(i == 30)
    begin
      TMS = 1;
    end
  end
      
  repeat(1) @(posedge TCK);
  TMS = 0; 
  repeat(3) @(negedge TCK);
end
endtask


task write_reg32;
input [4:0] reg_inst;
input [31:0] reg_data;
integer i; 
begin
  TMS = 0;
  repeat(2) @(negedge TCK);
  TMS = 1;
  repeat(2) @(negedge TCK);
  TMS = 0;
  repeat(2) @(negedge TCK);

  TDI = reg_inst[0];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[1];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[2];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[3];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[4];
  TMS = 1;
  repeat(3) @(negedge TCK);
  TMS = 0;
  repeat(2) @(negedge TCK);

  repeat(1) @(posedge TCK);
  for(i = 0; i < 32; i = i+1)
  begin
    TDI = reg_data[i];
    repeat(1) @(posedge TCK);
    if(i==30)
    begin
      TMS = 1;
    end
  end
      
  repeat(1) @(posedge TCK);
  TMS = 0; 
  repeat(3) @(negedge TCK);
end
endtask

endmodule
module ejtag_virtual_host (
    TCK,
    TMS,
    TDO,
    TDI,
    TRST
);


input   TDO;
output  TCK, TDI, TMS, TRST;
reg [31:0] control;
reg [31:0] impcode;
reg [31:0] idcode;
reg [31:0] data;
reg [31:0] addr;
reg [31:0] pc;
reg     TDI, TCK, TMS, TRST;

reg     pracc;
reg     prnw;
reg [1:0] psz;
reg     rocc;
reg     proben;
reg     probtrap;

reg     dmseg_service;
reg     service_busy;

reg [31:0] memory [{19{1'b1}}:0];
integer j;

always #25  TCK = ~TCK;

initial
begin
  TMS = 0;
  for(j=0; j<128; j=j+1)
    memory[j]=32'h0;
  
  
  dmseg_service = 1'b0;
  service_busy = 1'b0;
  #50 TRST = 1'b0; 
  TRST  = 1'b0;
  TCK   = 1'b0;
  pracc = 1'b0;
  rocc  = 1'b0;
  #20000 TRST = 1'b1;

  $display("ejtag reboot done!");
  #1000
  query_reg32(5'ha, control);
  start_dmseg_service;





end

initial
begin
  #10000
  begin
    #20000
    if(dmseg_service)
    begin
      service_busy = 1'b1;
      query_reg32(5'h01, idcode );
      $display("Idcode:%x Version:%x PartNumber:%x ManufID:%x\n",
                idcode,idcode[31:28],idcode[27:12],idcode[11:1]);

      query_reg32(5'h03, impcode);
      $display("Impcode:%x EJTAGver:%x DINTsup:%x NoDMA:%x MIPS32/64:%x\n",
                impcode,impcode[31:29],impcode[24],impcode[14],impcode[0]);
      service_busy = 1'b0;
    end
    if((!service_busy)&&dmseg_service)
    end_dmseg_service;
  end
end


task start_dmseg_service;
begin
  dmseg_service = 1'b1;
  $display("dmseg service start!");
end
endtask

task end_dmseg_service;
begin
  dmseg_service = 1'b0;
  query_reg32(5'ha, control);
  control[31] = 1'b0;
  control[15] = 1'b0;
  control[14] = 1'b0;
  control[12] = 1'b0;
  write_reg32(5'ha, control);
  $display("dmseg service end!");
end
endtask

task query_reg32;
input [4:0] reg_inst;
output [31:0] reg_data;
reg [31:0] reg_rd_data;
integer i; 
begin
  TMS = 0;
  repeat(2) @(negedge TCK);
  TMS = 1;
  repeat(2) @(negedge TCK);
  TMS = 0;
  repeat(2) @(negedge TCK);

  TDI = reg_inst[0];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[1];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[2];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[3];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[4];
  TMS = 1;
  repeat(3) @(negedge TCK);
  TMS = 0;
  repeat(2) @(negedge TCK);
   
  for(i = 0; i < 32; i = i+1)
  begin
    repeat(1) @(negedge TCK);
    reg_data[i] = TDO;
  end

  if (reg_data[18]==1'b0) 
    reg_rd_data[31:0] = {reg_data[31:19], 1'b1, reg_data[17:0]};
  else 
    reg_rd_data[31:0] = reg_data[31:0];
    
  for(i = 0; i < 32; i = i+1)
  begin
    TDI = reg_rd_data[i];
    repeat(1) @(posedge TCK);
    if(i == 30)
    begin
      TMS = 1;
    end
  end
      
  repeat(1) @(posedge TCK);
  TMS = 0; 
  repeat(3) @(negedge TCK);
end
endtask


task write_reg32;
input [4:0] reg_inst;
input [31:0] reg_data;
integer i; 
begin
  TMS = 0;
  repeat(2) @(negedge TCK);
  TMS = 1;
  repeat(2) @(negedge TCK);
  TMS = 0;
  repeat(2) @(negedge TCK);

  TDI = reg_inst[0];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[1];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[2];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[3];
  repeat(1) @(negedge TCK);
  TDI = reg_inst[4];
  TMS = 1;
  repeat(3) @(negedge TCK);
  TMS = 0;
  repeat(2) @(negedge TCK);

  repeat(1) @(posedge TCK);
  for(i = 0; i < 32; i = i+1)
  begin
    TDI = reg_data[i];
    repeat(1) @(posedge TCK);
    if(i==30)
    begin
      TMS = 1;
    end
  end
      
  repeat(1) @(posedge TCK);
  TMS = 0; 
  repeat(3) @(negedge TCK);
end
endtask

endmodule