data/full_repos/permissive/212981921/rtl/png_dff.v
data/verilator_xmls/4d8ae8ed-0bb2-48a4-9edc-b083517443ba.xml
module png_dff
(
    input wire  clk, d, _clr, _pre,
    output reg  q,
    output wire _q
);

always @(posedge clk or negedge _clr or negedge _pre) begin
    if (_clr == 1'b0) begin
        q <= 1'b0;
    end else if (_pre == 1'b0) begin
        q <= 1'b1;
    end else begin
        q <= d;
    end
end

assign _q = ~q;

endmodule
module png_dff
(
    input wire  clk, d, _clr, _pre,
    output reg  q,
    output wire _q
);


always @(posedge clk or negedge _clr or negedge _pre) begin
    if (_clr == 1'b0) begin
        q <= 1'b0;
    end else if (_pre == 1'b0) begin
        q <= 1'b1;
    end else begin
        q <= d;
    end
end

assign _q = ~q;

endmodule