data/full_repos/permissive/123339956/Labtest_2/bcd_adder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_2/bcd_adder.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #10 a = 8\'b10011001; b = 8\'b10001000;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_2/bcd_adder.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #10 a = 8\'b10010011; b = 8\'b00010010;\n  ^\n%Error: data/full_repos/permissive/123339956/Labtest_2/bcd_adder.v:19: Unsupported or unknown PLI call: $monitor\n initial $monitor("t=%3d, a=%8b, b=%8b, cout=%b, s=%8b",$time,a,b,cout,s); \n         ^~~~~~~~\n%Error: data/full_repos/permissive/123339956/Labtest_2/bcd_adder.v:23: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("bcd_adder.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/123339956/Labtest_2/bcd_adder.v:24: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bcd_adder (cout,s,a,b); 
input [7:0] a, b; 
	output [7:0]s ; 
	output cout ; 
	wire [4:0] y1, y2;
	adder_4bit Add1 (y1, a[3:0], b[3:0]);
	adder_4bit Add2 (y2, a[7:4], b[7:4]);
	bcd_adjustment BAD (cout, s, y2, y1);

endmodule
module bcd_adder (cout,s,a,b);
 
input [7:0] a, b; 
	output [7:0]s ; 
	output cout ; 
	wire [4:0] y1, y2;
	adder_4bit Add1 (y1, a[3:0], b[3:0]);
	adder_4bit Add2 (y2, a[7:4], b[7:4]);
	bcd_adjustment BAD (cout, s, y2, y1);

endmodule