data/full_repos/permissive/188434311/verilog/register_slice/synchronizer/multibit_sync_reg_p.v
1: b"%Error: data/full_repos/permissive/188434311/verilog/register_slice/synchronizer/multibit_sync_reg_p.v:22: Cannot find file containing module: 'sync_reg_p'\n    sync_reg_p sync_reg_p_inst(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188434311/verilog/register_slice/synchronizer,data/full_repos/permissive/188434311/sync_reg_p\n             data/full_repos/permissive/188434311/verilog/register_slice/synchronizer,data/full_repos/permissive/188434311/sync_reg_p.v\n             data/full_repos/permissive/188434311/verilog/register_slice/synchronizer,data/full_repos/permissive/188434311/sync_reg_p.sv\n             sync_reg_p\n             sync_reg_p.v\n             sync_reg_p.sv\n             obj_dir/sync_reg_p\n             obj_dir/sync_reg_p.v\n             obj_dir/sync_reg_p.sv\n%Error: Exiting due to 1 error(s)\n"
module multibit_sync_reg_p #(
    parameter DW = 32
)(
    input  wire  clki,
    input  wire  rstn,
    input  wire [ DW - 1 : 0 ] async_data_i,
    output wire [ DW - 1 : 0 ] sync_data_o 
);

genvar i;
generate
  for( i = 0 ; i < DW ; i = i + 1 ) begin:BIT
    sync_reg_p sync_reg_p_inst(
        .clki(clki),
        .rstn(rstn),
        .async_data_i(async_data_i[i]),
        .sync_data_o(sync_data_o)
    );
  end
endgenerate

endmodule
module multibit_sync_reg_p #(
    parameter DW = 32
)(
    input  wire  clki,
    input  wire  rstn,
    input  wire [ DW - 1 : 0 ] async_data_i,
    output wire [ DW - 1 : 0 ] sync_data_o 
);


genvar i;
generate
  for( i = 0 ; i < DW ; i = i + 1 ) begin:BIT
    sync_reg_p sync_reg_p_inst(
        .clki(clki),
        .rstn(rstn),
        .async_data_i(async_data_i[i]),
        .sync_data_o(sync_data_o)
    );
  end
endgenerate

endmodule