data/full_repos/permissive/151863926/src/cross_domain.v
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data/verilator_xmls/d219c719-1d8d-4b4d-b07c-c62daa27aec6.xml
module cross_domain(
    input clk_dst,
    input in,
    output reg out
    );
    
    reg int1 = 0, int2 = 0;
    always @(posedge clk_dst) begin
        int1 <= in;
        int2 <= int1;
        out <= int2;
    end
    
endmodule
module cross_domain(
    input clk_dst,
    input in,
    output reg out
    );

    
    reg int1 = 0, int2 = 0;
    always @(posedge clk_dst) begin
        int1 <= in;
        int2 <= int1;
        out <= int2;
    end
    
endmodule