data/full_repos/permissive/135820056/rtl/jt89/jt89_tone.v
 line:27: before: "("
1: b"%Error: data/full_repos/permissive/135820056/rtl/jt89/jt89_tone.v:38: Cannot find file containing module: 'jt89_vol'\njt89_vol u_vol(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135820056/rtl/jt89,data/full_repos/permissive/135820056/jt89_vol\n             data/full_repos/permissive/135820056/rtl/jt89,data/full_repos/permissive/135820056/jt89_vol.v\n             data/full_repos/permissive/135820056/rtl/jt89,data/full_repos/permissive/135820056/jt89_vol.sv\n             jt89_vol\n             jt89_vol.v\n             jt89_vol.sv\n             obj_dir/jt89_vol\n             obj_dir/jt89_vol.v\n             obj_dir/jt89_vol.sv\n%Error: Exiting due to 1 error(s)\n"
module jt89_tone(
    input               clk,
(* direct_enable = 1 *) input   clk_en,
    input               rst,
    input         [9:0] tone,
    input         [3:0] vol,
    output        [8:0] snd,
    output reg          out
);

reg [9:0] cnt;
reg last_out;

jt89_vol u_vol(
    .rst    ( rst     ),
    .clk    ( clk     ),
    .clk_en ( clk_en  ),
    .din    ( out     ),
    .vol    ( vol     ),
    .snd    ( snd     )
);

always @(posedge clk) 
    if( rst ) begin
        cnt <= 10'd0;
        out <= 1'b0;
    end else if( clk_en ) begin
        if( tone==10'd0 || tone==10'd1 )
            out <= 1'b1;
        else begin
            if( cnt[9:0]==10'd1 ) begin 
                cnt[9:0] <= (tone==10'd0) ? 10'd1 : tone;
                out <= ~out;
            end
            else cnt <= cnt-10'b1;
        end
    end

endmodule
module jt89_tone(
    input               clk,
(* direct_enable = 1 *) input   clk_en,
    input               rst,
    input         [9:0] tone,
    input         [3:0] vol,
    output        [8:0] snd,
    output reg          out
);


reg [9:0] cnt;
reg last_out;

jt89_vol u_vol(
    .rst    ( rst     ),
    .clk    ( clk     ),
    .clk_en ( clk_en  ),
    .din    ( out     ),
    .vol    ( vol     ),
    .snd    ( snd     )
);

always @(posedge clk) 
    if( rst ) begin
        cnt <= 10'd0;
        out <= 1'b0;
    end else if( clk_en ) begin
        if( tone==10'd0 || tone==10'd1 )
            out <= 1'b1;
        else begin
            if( cnt[9:0]==10'd1 ) begin 
                cnt[9:0] <= (tone==10'd0) ? 10'd1 : tone;
                out <= ~out;
            end
            else cnt <= cnt-10'b1;
        end
    end

endmodule