data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:27: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clock_i <= ~clock_i;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1 send_packet(8\'h55);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #6 assert_data_received(8\'h55);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #2 ack_i = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #2 if (ready_o)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #2 send_packet(8\'hAA);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #6 assert_data_received(8\'hAA);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #2 send_packet(8\'hCC);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #6 assert_data_received(8\'hAA);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #2 ack_i = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #2 if (!ready_o)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #4 clear_ready_flag();\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #4 serial_i <= 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #4 serial_i <= data[0];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #4 serial_i <= data[1];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #4 serial_i <= data[2];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #4 serial_i <= data[3];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #4 serial_i <= data[4];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #4 serial_i <= data[5];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #4 serial_i <= data[6];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #4 serial_i <= data[7];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #4 serial_i <= 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #2 ack_i = 1\'b0;\n    ^\n%Error: data/full_repos/permissive/122777989/test/uart_rx/uart_rx_ack_oneshot_test.v:15: Cannot find file containing module: \'UartRx\'\nUartRx uart_rx (\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122777989/test/uart_rx,data/full_repos/permissive/122777989/UartRx\n             data/full_repos/permissive/122777989/test/uart_rx,data/full_repos/permissive/122777989/UartRx.v\n             data/full_repos/permissive/122777989/test/uart_rx,data/full_repos/permissive/122777989/UartRx.sv\n             UartRx\n             UartRx.v\n             UartRx.sv\n             obj_dir/UartRx\n             obj_dir/UartRx.v\n             obj_dir/UartRx.sv\n%Error: Exiting due to 1 error(s), 23 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UartRxAckOneshotTest ();

reg reset_i = 1'b0;
reg clock_i = 1'b0;
reg ack_i = 1'b0;
reg parity_bit_i = 1'b0;
reg parity_even_i = 1'b0;
reg serial_i = 1'b1;
reg [15:0] clock_divider_i = 2;
wire [7:0] data_o;
wire ready_o;

UartRx uart_rx (
  .reset_i(reset_i),
  .clock_i(clock_i),
  .ack_i(ack_i),
  .parity_bit_i(parity_bit_i),
  .parity_even_i(parity_even_i),
  .serial_i(serial_i),
  .clock_divider_i(clock_divider_i),
  .data_o(data_o),
  .ready_o(ready_o)
);

always #1 clock_i <= ~clock_i;

initial begin
  #1 send_packet(8'h55);
  #6 assert_data_received(8'h55);

  #2 ack_i = 1'b1;
  #2 if (ready_o)
    $display("FAILED - ready_o should be low after ack_i goes high");

  #2 send_packet(8'hAA);
  #6 assert_data_received(8'hAA);
  

  #2 send_packet(8'hCC);
  #6 assert_data_received(8'hAA);

  #2 ack_i = 1'b0;
  #2 if (!ready_o)
    $display("FAILED - ready_o should remain high when ack_i goes low and another packet is available");

  #4 clear_ready_flag();
end

task send_packet;
  input [7:0] data;

  begin
    #4 serial_i <= 1'b0;
    #4 serial_i <= data[0];
    #4 serial_i <= data[1];
    #4 serial_i <= data[2];
    #4 serial_i <= data[3];
    #4 serial_i <= data[4];
    #4 serial_i <= data[5];
    #4 serial_i <= data[6];
    #4 serial_i <= data[7];
    #4 serial_i <= 1'b1;
  end
endtask

task assert_data_received;
  input [7:0] data;

  begin
    if (!ready_o)
    $display("FAILED - ready_o should be high after receiving packet");

    if (data_o != data)
      $display("FAILED - data_o value should be h%x", data);
  end
endtask

task clear_ready_flag;
  begin
    ack_i = 1'b1;

    if (!ready_o)
      $display("FAILED - ready_o should stay high after receiving packet");

    #2 ack_i = 1'b0;

    if (ready_o)
      $display("FAILED - ready_o should be low after ack_i goes high");
  end
endtask

endmodule
module UartRxAckOneshotTest ();


reg reset_i = 1'b0;
reg clock_i = 1'b0;
reg ack_i = 1'b0;
reg parity_bit_i = 1'b0;
reg parity_even_i = 1'b0;
reg serial_i = 1'b1;
reg [15:0] clock_divider_i = 2;
wire [7:0] data_o;
wire ready_o;

UartRx uart_rx (
  .reset_i(reset_i),
  .clock_i(clock_i),
  .ack_i(ack_i),
  .parity_bit_i(parity_bit_i),
  .parity_even_i(parity_even_i),
  .serial_i(serial_i),
  .clock_divider_i(clock_divider_i),
  .data_o(data_o),
  .ready_o(ready_o)
);

always #1 clock_i <= ~clock_i;

initial begin
  #1 send_packet(8'h55);
  #6 assert_data_received(8'h55);

  #2 ack_i = 1'b1;
  #2 if (ready_o)
    $display("FAILED - ready_o should be low after ack_i goes high");

  #2 send_packet(8'hAA);
  #6 assert_data_received(8'hAA);
  

  #2 send_packet(8'hCC);
  #6 assert_data_received(8'hAA);

  #2 ack_i = 1'b0;
  #2 if (!ready_o)
    $display("FAILED - ready_o should remain high when ack_i goes low and another packet is available");

  #4 clear_ready_flag();
end

task send_packet;
  input [7:0] data;

  begin
    #4 serial_i <= 1'b0;
    #4 serial_i <= data[0];
    #4 serial_i <= data[1];
    #4 serial_i <= data[2];
    #4 serial_i <= data[3];
    #4 serial_i <= data[4];
    #4 serial_i <= data[5];
    #4 serial_i <= data[6];
    #4 serial_i <= data[7];
    #4 serial_i <= 1'b1;
  end
endtask

task assert_data_received;
  input [7:0] data;

  begin
    if (!ready_o)
    $display("FAILED - ready_o should be high after receiving packet");

    if (data_o != data)
      $display("FAILED - data_o value should be h%x", data);
  end
endtask

task clear_ready_flag;
  begin
    ack_i = 1'b1;

    if (!ready_o)
      $display("FAILED - ready_o should stay high after receiving packet");

    #2 ack_i = 1'b0;

    if (ready_o)
      $display("FAILED - ready_o should be low after ack_i goes high");
  end
endtask

endmodule