data/full_repos/permissive/19818566/hardware/testcases/DCT4/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog/cut_wrapper.v
1: b"%Error: data/full_repos/permissive/19818566/hardware/testcases/DCT4/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog/cut_wrapper.v:14: Cannot find file containing module: 'dct4_inj'\ndct4_inj toplevel_instance (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19818566/hardware/testcases/DCT4/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog,data/full_repos/permissive/19818566/dct4_inj\n             data/full_repos/permissive/19818566/hardware/testcases/DCT4/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog,data/full_repos/permissive/19818566/dct4_inj.v\n             data/full_repos/permissive/19818566/hardware/testcases/DCT4/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog,data/full_repos/permissive/19818566/dct4_inj.sv\n             dct4_inj\n             dct4_inj.v\n             dct4_inj.sv\n             obj_dir/dct4_inj\n             obj_dir/dct4_inj.v\n             obj_dir/dct4_inj.sv\n%Error: Exiting due to 1 error(s)\n"
module circuit_under_test (
clk,
rst,
testVector,
resultVector,
injectionVector
);
input clk;
input rst;
input[63:0] testVector;
output[22:0] resultVector;
input[12:0] injectionVector;
dct4_inj toplevel_instance (
.CK(clk),
.inp(testVector [63:0]),
.outp(resultVector [19:0]),
.outi(resultVector [22:20]),
.p_desc0_p_O_FD(injectionVector[0]),
.p_desc1_p_O_FD(injectionVector[1]),
.p_desc2_p_O_FD(injectionVector[2]),
.p_i_1_rep1_Z_p_O_FD(injectionVector[3]),
.p_i_1_rep2_Z_p_O_FD(injectionVector[4]),
.p_desc3_p_O_FD(injectionVector[5]),
.p_i_2_rep1_Z_p_O_FD(injectionVector[6]),
.p_desc9_p_O_FD(injectionVector[7]),
.p_desc10_p_O_FD(injectionVector[8]),
.p_desc11_p_O_FD(injectionVector[9]),
.p_desc12_p_O_FD(injectionVector[10]),
.p_desc13_p_O_FD(injectionVector[11]),
.p_i_0_rep1_Z_p_O_FD(injectionVector[12]));
endmodule
module circuit_under_test (
clk,
rst,
testVector,
resultVector,
injectionVector
);

input clk;
input rst;
input[63:0] testVector;
output[22:0] resultVector;
input[12:0] injectionVector;
dct4_inj toplevel_instance (
.CK(clk),
.inp(testVector [63:0]),
.outp(resultVector [19:0]),
.outi(resultVector [22:20]),
.p_desc0_p_O_FD(injectionVector[0]),
.p_desc1_p_O_FD(injectionVector[1]),
.p_desc2_p_O_FD(injectionVector[2]),
.p_i_1_rep1_Z_p_O_FD(injectionVector[3]),
.p_i_1_rep2_Z_p_O_FD(injectionVector[4]),
.p_desc3_p_O_FD(injectionVector[5]),
.p_i_2_rep1_Z_p_O_FD(injectionVector[6]),
.p_desc9_p_O_FD(injectionVector[7]),
.p_desc10_p_O_FD(injectionVector[8]),
.p_desc11_p_O_FD(injectionVector[9]),
.p_desc12_p_O_FD(injectionVector[10]),
.p_desc13_p_O_FD(injectionVector[11]),
.p_i_0_rep1_Z_p_O_FD(injectionVector[12]));
endmodule