data/full_repos/permissive/166008742/src/led_driver_shift_reg.v
1: b'%Error: data/full_repos/permissive/166008742/src/led_driver_shift_reg.v:30: Cannot find include file: globals.vh\n    `include "globals.vh" \n             ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/globals.vh\n             data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/globals.vh.v\n             data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/globals.vh.sv\n             globals.vh\n             globals.vh.v\n             globals.vh.sv\n             obj_dir/globals.vh\n             obj_dir/globals.vh.v\n             obj_dir/globals.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module led_driver_shift_reg #(parameter DATA_WIDTH = 32, parameter SHIFT_WIDTH = 32)
(
    input  clk,
    input  reset,

    input  [DATA_WIDTH-1:0] data_in,
    input  load,
    input  next_bit,
    output bit_val,
    output last_bit
);

    `include "globals.vh"

    localparam SHIFT_WIDTH_NBITS = clogb2(SHIFT_WIDTH) + 1;

    reg [SHIFT_WIDTH_NBITS-1:0] cnt;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            cnt <= 0;
        end
        else begin
            if (load) begin
                cnt <= SHIFT_WIDTH-1;
            end
            else if (next_bit) begin
                cnt <= cnt - 1;
            end
        end
    end 

    assign last_bit = (cnt == 0);

    reg [DATA_WIDTH-1:0] data;
    assign bit_val = data[cnt];

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            data <= 0;
        end
        else begin
            if (load) begin
                data <= data_in;
            end
        end
    end 

endmodule
module led_driver_shift_reg #(parameter DATA_WIDTH = 32, parameter SHIFT_WIDTH = 32)
(
    input  clk,
    input  reset,

    input  [DATA_WIDTH-1:0] data_in,
    input  load,
    input  next_bit,
    output bit_val,
    output last_bit
);


    `include "globals.vh"

    localparam SHIFT_WIDTH_NBITS = clogb2(SHIFT_WIDTH) + 1;

    reg [SHIFT_WIDTH_NBITS-1:0] cnt;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            cnt <= 0;
        end
        else begin
            if (load) begin
                cnt <= SHIFT_WIDTH-1;
            end
            else if (next_bit) begin
                cnt <= cnt - 1;
            end
        end
    end 

    assign last_bit = (cnt == 0);

    reg [DATA_WIDTH-1:0] data;
    assign bit_val = data[cnt];

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            data <= 0;
        end
        else begin
            if (load) begin
                data <= data_in;
            end
        end
    end 

endmodule