data/full_repos/permissive/20430511/hardware/FPGA/wishbone/example/wb_sram.v
 line:33: before: "="
data/verilator_xmls/938b65b3-0234-4d80-ad2a-8b93abf144a8.xml
module wb_sram
  #(parameter WIDTH = 32,
    parameter MSB   = WIDTH-1,
    parameter SBITS = 10,
    parameter SIZE  = 1 << SBITS,
    parameter ASB   = SBITS-1,
    parameter DELAY = 3)
   (

    input              clk_i,
    input              rst_i,
    input              cyc_i,
    input              stb_i,
    input              we_i,
    input              bst_i,
    output reg         ack_o = 0,
    input [ASB:0]      adr_i,
    input [MSB:0]      dat_i,
    output reg [MSB:0] dat_o
    );





   reg [MSB:0]         sram [0:SIZE-1];

   integer             i;
   initial begin : SRAM_INIT
      for (i = 0; i < SIZE; i = i+1)
        sram[i] <= 0;
   end




   always @(posedge clk_i)
     if (rst_i) ack_o <= #DELAY 0;
     else       ack_o <= #DELAY cyc_i && stb_i;


   always @(posedge clk_i)
     if (!rst_i && cyc_i && stb_i) begin
        dat_o <= #DELAY sram[adr_i];
        if (we_i)
          sram[adr_i] <= #DELAY dat_i;
     end


endmodule
module wb_sram
  #(parameter WIDTH = 32,
    parameter MSB   = WIDTH-1,
    parameter SBITS = 10,
    parameter SIZE  = 1 << SBITS,
    parameter ASB   = SBITS-1,
    parameter DELAY = 3)
   (

    input              clk_i,
    input              rst_i,
    input              cyc_i,
    input              stb_i,
    input              we_i,
    input              bst_i,
    output reg         ack_o = 0,
    input [ASB:0]      adr_i,
    input [MSB:0]      dat_i,
    output reg [MSB:0] dat_o
    );






   reg [MSB:0]         sram [0:SIZE-1];

   integer             i;
   initial begin : SRAM_INIT
      for (i = 0; i < SIZE; i = i+1)
        sram[i] <= 0;
   end




   always @(posedge clk_i)
     if (rst_i) ack_o <= #DELAY 0;
     else       ack_o <= #DELAY cyc_i && stb_i;


   always @(posedge clk_i)
     if (!rst_i && cyc_i && stb_i) begin
        dat_o <= #DELAY sram[adr_i];
        if (we_i)
          sram[adr_i] <= #DELAY dat_i;
     end


endmodule