data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #73 rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #40 dataIn = 4\'hF;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #2  vld = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #10 vld = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #40 dataIn = 4\'h7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #2  vld = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #10 vld = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #40 dataIn = 4\'h5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #2  vld = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10 vld = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #40 dataIn = 4\'h6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #2  vld = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #10 vld = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #40 dataIn = 4\'h8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #2  vld = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #10 vld = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #40 $finish;\n ^\n%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/display3/display3_top_tb.v:20: Cannot find file containing module: \'display3_top\'\ndisplay3_top #(SCWIDTH, RCWIDTH, CNTSIZE) uut(.clk(clk), .rst(rst), .vld(vld), .dataIn(dataIn), .ledOut(ledOut), .anode(anode), .sevenSeg(sevenSeg));\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display3,data/full_repos/permissive/214278225/display3_top\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display3,data/full_repos/permissive/214278225/display3_top.v\n             data/full_repos/permissive/214278225/1_7SegmentDisplay/display3,data/full_repos/permissive/214278225/display3_top.sv\n             display3_top\n             display3_top.v\n             display3_top.sv\n             obj_dir/display3_top\n             obj_dir/display3_top.v\n             obj_dir/display3_top.sv\n%Error: Exiting due to 1 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module display3_top_tb;

parameter SCWIDTH = 1;
parameter RCWIDTH = 0;
parameter CNTSIZE = 0;


reg clk;
reg rst;
reg vld;
reg [3:0] dataIn;


wire [3:0] ledOut;
wire [3:0] anode;
wire [7:0] sevenSeg;


display3_top #(SCWIDTH, RCWIDTH, CNTSIZE) uut(.clk(clk), .rst(rst), .vld(vld), .dataIn(dataIn), .ledOut(ledOut), .anode(anode), .sevenSeg(sevenSeg));

initial begin
	clk = 0;
	forever
		#5 clk = ~clk;
end

initial begin
	rst = 1;
	#73 rst = 0;
end

initial begin
	vld = 0;
	dataIn = 0;
	#40 dataIn = 4'hF;
	#2  vld = 1;
	#10 vld = 0;
	#40 dataIn = 4'h7;
	#2  vld = 1;
	#10 vld = 0;
	#40 dataIn = 4'h5;
	#2  vld = 1;
	#10 vld = 0;
	#40 dataIn = 4'h6;
	#2  vld = 1;
	#10 vld = 0;
	#40 dataIn = 4'h8;
	#2  vld = 1;
	#10 vld = 0;
	#40 $finish;
end

endmodule
module display3_top_tb;


parameter SCWIDTH = 1;
parameter RCWIDTH = 0;
parameter CNTSIZE = 0;


reg clk;
reg rst;
reg vld;
reg [3:0] dataIn;


wire [3:0] ledOut;
wire [3:0] anode;
wire [7:0] sevenSeg;


display3_top #(SCWIDTH, RCWIDTH, CNTSIZE) uut(.clk(clk), .rst(rst), .vld(vld), .dataIn(dataIn), .ledOut(ledOut), .anode(anode), .sevenSeg(sevenSeg));

initial begin
	clk = 0;
	forever
		#5 clk = ~clk;
end

initial begin
	rst = 1;
	#73 rst = 0;
end

initial begin
	vld = 0;
	dataIn = 0;
	#40 dataIn = 4'hF;
	#2  vld = 1;
	#10 vld = 0;
	#40 dataIn = 4'h7;
	#2  vld = 1;
	#10 vld = 0;
	#40 dataIn = 4'h5;
	#2  vld = 1;
	#10 vld = 0;
	#40 dataIn = 4'h6;
	#2  vld = 1;
	#10 vld = 0;
	#40 dataIn = 4'h8;
	#2  vld = 1;
	#10 vld = 0;
	#40 $finish;
end

endmodule