data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:11: Cannot find include file: ../../utils/sim/sim.v\n`include "../../utils/sim/sim.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/190755935/src/image/sim,data/full_repos/permissive/190755935/../../utils/sim/sim.v\n             data/full_repos/permissive/190755935/src/image/sim,data/full_repos/permissive/190755935/../../utils/sim/sim.v.v\n             data/full_repos/permissive/190755935/src/image/sim,data/full_repos/permissive/190755935/../../utils/sim/sim.v.sv\n             ../../utils/sim/sim.v\n             ../../utils/sim/sim.v.v\n             ../../utils/sim/sim.v.sv\n             obj_dir/../../utils/sim/sim.v\n             obj_dir/../../utils/sim/sim.v.v\n             obj_dir/../../utils/sim/sim.v.sv\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:13: Cannot find include file: ../../image/rtl/image_defs.v\n`include "../../image/rtl/image_defs.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:18: Define or directive not defined: \'`OutputInfo\'\n    parameter Output=`OutputInfo;\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:18: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    parameter Output=`OutputInfo;\n                                ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:21: Define or directive not defined: \'`IS_w\'\n    localparam [`IS_w-1:0] ImageSpec = `IS_DEFAULT;\n                ^~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:21: Define or directive not defined: \'`IS_DEFAULT\'\n    localparam [`IS_w-1:0] ImageSpec = `IS_DEFAULT;\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:21: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam [`IS_w-1:0] ImageSpec = `IS_DEFAULT;\n                                                  ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:22: Define or directive not defined: \'`I_w\'\n    localparam ImageWidth = `I_w( ImageSpec );\n                            ^~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:23: Define or directive not defined: \'`I_Data_w\'\n    localparam ImageDataWidth = `I_Data_w( ImageSpec );\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:30: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("image_fifo_tb.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:31: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars( 0, image_fifo_tb );\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:35: Define or directive not defined: \'`Realtime\'\n    `Realtime\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:38: Define or directive not defined: \'`Clock10MHz\'\n    `Clock10MHz\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:40: Define or directive not defined: \'`AssertSetup\'\n    `AssertSetup\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:63: Define or directive not defined: \'`I_Start\'\n    assign     `I_Start( ImageSpec, image_in ) = image_in_start;\n               ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:63: syntax error, unexpected \'(\', expecting TYPE-IDENTIFIER\n    assign     `I_Start( ImageSpec, image_in ) = image_in_start;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:64: Define or directive not defined: \'`I_Stop\'\n    assign     `I_Stop( ImageSpec, image_in ) = image_in_stop;\n               ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:65: Define or directive not defined: \'`I_Data\'\n    assign     `I_Data( ImageSpec, image_in ) = image_in_data;\n               ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:66: Define or directive not defined: \'`I_Valid\'\n    assign     `I_Valid( ImageSpec, image_in ) = image_in_valid;\n               ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:67: Define or directive not defined: \'`I_Error\'\n                                                                             : ... Suggested alternative: \'`error\'\n    assign     `I_Error( ImageSpec, image_in ) = image_in_error;\n               ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:68: Define or directive not defined: \'`I_Ready\'\n    assign     image_in_ready   = `I_Ready( ImageSpec, image_in );\n                                  ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:68: syntax error, unexpected \',\'\n    assign     image_in_ready   = `I_Ready( ImageSpec, image_in );\n                                                     ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:69: Define or directive not defined: \'`I_Request\'\n    assign     image_in_request = `I_Request( ImageSpec, image_in );\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:69: syntax error, unexpected \',\'\n    assign     image_in_request = `I_Request( ImageSpec, image_in );\n                                                       ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:70: Define or directive not defined: \'`I_Cancel\'\n    assign     image_in_cancel  = `I_Cancel( ImageSpec, image_in );\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:70: syntax error, unexpected \',\'\n    assign     image_in_cancel  = `I_Cancel( ImageSpec, image_in );\n                                                      ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:81: Define or directive not defined: \'`I_Start\'\n    assign     image_out_start = `I_Start( ImageSpec, image_out ) ;\n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:81: syntax error, unexpected \',\'\n    assign     image_out_start = `I_Start( ImageSpec, image_out ) ;\n                                                    ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:82: Define or directive not defined: \'`I_Stop\'\n    assign     image_out_stop = `I_Stop( ImageSpec, image_out ) ;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:82: syntax error, unexpected \',\'\n    assign     image_out_stop = `I_Stop( ImageSpec, image_out ) ;\n                                                  ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:83: Define or directive not defined: \'`I_Data\'\n    assign     image_out_data = `I_Data( ImageSpec, image_out ) ;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:83: syntax error, unexpected \',\'\n    assign     image_out_data = `I_Data( ImageSpec, image_out ) ;\n                                                  ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:84: Define or directive not defined: \'`I_Valid\'\n    assign     image_out_valid = `I_Valid( ImageSpec, image_out ) ;\n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:84: syntax error, unexpected \',\'\n    assign     image_out_valid = `I_Valid( ImageSpec, image_out ) ;\n                                                    ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:85: Define or directive not defined: \'`I_Error\'\n                                                                             : ... Suggested alternative: \'`error\'\n    assign     image_out_error = `I_Error( ImageSpec, image_out ) ;\n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:85: syntax error, unexpected \',\'\n    assign     image_out_error = `I_Error( ImageSpec, image_out ) ;\n                                                    ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:86: Define or directive not defined: \'`I_Ready\'\n    assign     `I_Ready( ImageSpec, image_out ) = image_out_ready;\n               ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:87: Define or directive not defined: \'`I_Request\'\n    assign     `I_Request( ImageSpec, image_out ) = image_out_request;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:88: Define or directive not defined: \'`I_Cancel\'\n    assign     `I_Cancel( ImageSpec, image_out ) = image_out_cancel;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:107: syntax error, unexpected \'@\'\n            @( posedge clock );\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n            #2\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:108: Define or directive not defined: \'`Debug\'\n            `Debug( "            Clock");\n            ^~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:108: syntax error, unexpected \';\'\n            `Debug( "            Clock");\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n            #2\n            ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:118: Define or directive not defined: \'`Info\'\n            `Info( "    Reset");\n            ^~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:118: syntax error, unexpected \';\'\n            `Info( "    Reset");\n                               ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:131: Define or directive not defined: \'`InfoDo\'\n            `InfoDo $display( "            In:  %0x:%0x:%0x", start_in, stop_in, data_in );\n            ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:153: Define or directive not defined: \'`InfoDo\'\n            `InfoDo $display( "                        Out: %0x:%0x:%0x (%0x)", image_out_start, image_out_stop, image_out_data, image_out_valid );\n            ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:154: Define or directive not defined: \'`AssertEqual\'\n            `AssertEqual( image_out_valid, valid_out, test_name );\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:154: syntax error, unexpected \',\'\n            `AssertEqual( image_out_valid, valid_out, test_name );\n                                         ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:155: Define or directive not defined: \'`AssertEqual\'\n            `AssertEqual( image_out_start, start_out, test_name );\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_fifo_tb.v:155: syntax error, unexpected \',\'\n            `AssertEqual( image_out_start, start_out, test_name );\n                                         ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module image_fifo_tb();


    parameter Output=`OutputInfo;


    localparam [`IS_w-1:0] ImageSpec = `IS_DEFAULT;
    localparam ImageWidth = `I_w( ImageSpec );
    localparam ImageDataWidth = `I_Data_w( ImageSpec );
    localparam MemoryWidth = 3;
    localparam MemorySize = 1 << MemoryWidth;

    reg  reset;

    initial begin
      $dumpfile("image_fifo_tb.vcd");
      $dumpvars( 0, image_fifo_tb );
    end


    `Realtime


    `Clock10MHz

    `AssertSetup

    wire [ImageWidth-1:0] image_in;
    wire [ImageWidth-1:0] image_out;

    image_fifo #( .InIS( ImageSpec ), .OutIS( ImageSpec ), .MemoryWidth( MemoryWidth ) ) i_f (
        .clock( clock ),
        .reset( reset ),

        .image_in( image_in ),
        .image_out( image_out )
    );


    reg                       image_in_start;
    reg                       image_in_stop;
    reg [ImageDataWidth-1:0]  image_in_data;
    reg                       image_in_valid;
    reg                       image_in_error;
    wire                      image_in_ready;
    wire                      image_in_request;
    wire                      image_in_cancel;

    assign     `I_Start( ImageSpec, image_in ) = image_in_start;
    assign     `I_Stop( ImageSpec, image_in ) = image_in_stop;
    assign     `I_Data( ImageSpec, image_in ) = image_in_data;
    assign     `I_Valid( ImageSpec, image_in ) = image_in_valid;
    assign     `I_Error( ImageSpec, image_in ) = image_in_error;
    assign     image_in_ready   = `I_Ready( ImageSpec, image_in );
    assign     image_in_request = `I_Request( ImageSpec, image_in );
    assign     image_in_cancel  = `I_Cancel( ImageSpec, image_in );

    wire                      image_out_start;
    wire                      image_out_stop;
    wire [ImageDataWidth-1:0] image_out_data;
    wire                      image_out_valid;
    wire                      image_out_error;
    reg                       image_out_ready;
    reg                       image_out_request;
    reg                       image_out_cancel;

    assign     image_out_start = `I_Start( ImageSpec, image_out ) ;
    assign     image_out_stop = `I_Stop( ImageSpec, image_out ) ;
    assign     image_out_data = `I_Data( ImageSpec, image_out ) ;
    assign     image_out_valid = `I_Valid( ImageSpec, image_out ) ;
    assign     image_out_error = `I_Error( ImageSpec, image_out ) ;
    assign     `I_Ready( ImageSpec, image_out ) = image_out_ready;
    assign     `I_Request( ImageSpec, image_out ) = image_out_request;
    assign     `I_Cancel( ImageSpec, image_out ) = image_out_cancel;

    task if_init;
        begin
            image_in_start = 0;
            image_in_stop = 0;
            image_in_data = 0;
            image_in_valid = 0;
            image_in_error = 0;

            image_out_ready = 1;
            image_out_request = 0;
            image_out_cancel = 0;
        end
    endtask

    task  if_clock;
        begin
            #2
            @( posedge clock );
            `Debug( "            Clock");
            #2
            ;
        end
    endtask

    task  if_reset;
        begin
            reset = 1;
            if_clock;
            `Info( "    Reset");
            reset = 0;
            if_clock;
        end
    endtask

    task if_in( input reg start_in, input reg stop_in, input reg [ImageDataWidth-1:0] data_in );
        begin
            image_in_start = start_in;
            image_in_stop = stop_in;
            image_in_data = data_in;
            image_in_valid = 1;

            `InfoDo $display( "            In:  %0x:%0x:%0x", start_in, stop_in, data_in );

            if_clock;

            image_in_start = 0;
            image_in_stop = 0;
            image_in_data = 0;
            image_in_valid = 0;
        end
    endtask


    integer i, j, k;

    reg                    start, start0;
    reg                    stop, stop0;
    reg [ImageDataWidth:0] data, data0;

    reg [8*50:1] test_name;

    task if_out( input reg valid_out, input reg start_out, input reg stop_out, input reg [ImageDataWidth-1:0] data_out );
        begin
            `InfoDo $display( "                        Out: %0x:%0x:%0x (%0x)", image_out_start, image_out_stop, image_out_data, image_out_valid );
            `AssertEqual( image_out_valid, valid_out, test_name );
            `AssertEqual( image_out_start, start_out, test_name );
            `AssertEqual( image_out_stop, stop_out, test_name );
            `AssertEqual( image_out_data, data_out, test_name );
        end
    endtask

    task if_check_initial_state;
        begin
            `Info( "Initial State" );
            test_name = "Initial State";

            `Assert( image_in_ready, test_name );

            `Assert( !image_in_valid, test_name );
        end
    endtask

    task if_single_stepping( input  reg pauses );
        begin
            `InfoDo $display( "Single Stepping Pauses = %0x", pauses );

            if_check_initial_state;

            test_name = "Single Stepping";

            image_out_ready = 1;



            for ( i = 0; i < MemorySize * 3; i = i + 1 ) begin
                start = i % 2;
                stop = i % 3;
                data = i + 8'H10;
                if_in( start, stop, data );


                if ( pauses ) begin
                    image_out_ready = 0;
                    for ( j = 0; j < 4; j = j + 1 ) begin
                        `Info( "        Hold" );
                        if_out( 1, start, stop, data );
                        if_clock;
                    end
                    image_out_ready = 1;
                end

                if_out( 1, start, stop, data );
            end

            if_clock;
            if_out( 0, 0, 0, 0 );

        end
    endtask

    task if_partial_load( input  reg pauses );
        begin
            `InfoDo $display( "Partial Load Pauses = %0x", pauses );

            if_check_initial_state;

            test_name = "Partial Load";


            for ( j = 0; j < 3; j = j + 1 ) begin
                `InfoDo $display( "    Filling %0d", j );

                image_out_ready = 0;


                start0 = 0;
                stop0 = 0;
                data0 = 8'H10 * j;
                for ( i = 0; i < 2 * MemorySize / 3; i = i + 1 ) begin
                    start = i % 2;
                    stop = i % 3;
                    data = data0 + i;
                    if_in( start, stop, data );
                    if_out( 1, start0, stop0, data0 );
                    if ( pauses ) begin
                        for ( k = 0; k < 4; k = k + 1 ) begin
                            `Info( "        Pause" );
                            if_out( 1, start0, stop0, data0 );
                            if_clock;
                        end
                    end
                end

                image_out_ready = 1;

                `InfoDo $display( "    Emptying %0d", j );


                for ( i = 0; i < 2 * MemorySize / 3; i = i + 1 ) begin
                    start = i % 2;
                    stop = i % 3;
                    data = data0 + i;
                    if_out( 1, start, stop, data );
                    if ( pauses ) begin
                        image_out_ready = 0;
                        for ( k = 0; k < 4; k = k + 1 ) begin
                            `Info( "        Hold" );
                            if_out( 1, start, stop, data );
                            if_clock;
                        end
                        image_out_ready = 1;
                    end
                    if_clock;



                end

                if_out( 0, 0, 0, 0 );
            end
        end
    endtask

    localparam FillExtra = 10;

    task if_fill( input reg pauses );
        begin
            `InfoDo $display( "Fill Pauses = %0x", pauses );

            if_check_initial_state;

            test_name = "Fill";


            for ( j = 0; j < 3; j = j + 1 ) begin
                `InfoDo $display( "    Fill To Full %0d", j );

                image_out_ready = 0;


                start0 = 0;
                stop0 = 0;
                data0 = 8'H10 * j;
                for ( i = 0; i < MemorySize + FillExtra; i = i + 1 ) begin
                    start = i % 2;
                    stop = i % 3;
                    data = data0 + i;
                    if_in( start, stop, data );
                    if_out( 1, start0, stop0, data0 );
                    if ( i >= MemorySize ) begin
                        `Info( "        FULL" );
                        `Assert( ~image_in_ready, test_name );
                    end
                    if ( pauses ) begin
                        for ( k = 0; k < 4; k = k + 1 ) begin
                            `Info( "        Pause" );
                            if_out( 1, start0, stop0, data0 );
                            if_clock;
                        end
                    end
                end

                image_out_ready = 1;

                `InfoDo $display( "    Emptying %0d", j );


                for ( i = 0; i < MemorySize; i = i + 1 ) begin
                    start = i % 2;
                    stop = i % 3;
                    data = data0 + i;
                    if_out( 1, start, stop, data );

                    if ( pauses ) begin
                        image_out_ready = 0;
                        for ( k = 0; k < 4; k = k + 1 ) begin
                            `Info( "        Hold" );
                            if_out( 1, start, stop, data );
                            if_clock;
                        end
                        image_out_ready = 1;
                    end

                    if_clock;
                end


                if_out( 0, 0, 0, 0 );
            end
        end
    endtask

    task if_check_in_to_out_signals;
        begin
            `Info( "    In to Out Signals" );

            image_in_error = 0;

            if_clock;

            `Assert( ~image_out_error, "Error Idle"  );

            `Info( "        Checking Error Up" );

            image_in_error = 1;

            if_clock;

            `Assert( image_out_error, "Error Not Idle"  );

            `Info( "        Checking Error Down" );

            image_in_error = 0;

            if_clock;

            `Assert( !image_out_error, "Error Idle Again"  );

            if_clock;

        end
    endtask

    task if_check_out_to_in_signals;
        begin

            `Info( "    Out to In Signals" );

            image_out_request = 0;
            image_out_cancel = 0;


            if_clock;

            `Assert( ~image_in_request, "Request Idle"  );
            `Assert( ~image_in_cancel,  "Cancel Idle"  );

            `Info( "        Checking Request Up" );

            image_out_request = 1;

            if_clock;

            `Assert( image_in_request, "Request Not Idle"  );
            `Assert( ~image_in_cancel,  "Cancel Idle Still"  );

            if_clock;

            `Assert( image_in_request, "Request Not Idle"  );
            `Assert( ~image_in_cancel,  "Cancel Idle Still"  );

            if_clock;

            `Info( "        Checking Request Down" );

            image_out_request = 0;

            if_clock;

            `Assert( !image_in_request, "Request Idle Again"  );
            `Assert( ~image_in_cancel,  "Cancel Idle Still"  );

            if_clock;

            `Assert( ~image_in_request, "Request Idle"  );
            `Assert( ~image_in_cancel,  "Cancel Idle"  );

            `Info( "        Checking Request Up" );

            image_out_cancel = 1;

            if_clock;

            `Assert( ~image_in_request, "Request Idle"  );
            `Assert( image_in_cancel,  "Cancel Not Idle"  );

            `Info( "        Checking Request Down" );

            image_out_cancel = 0;

            if_clock;

            `Assert( ~image_in_request, "Request Idle Still"  );
            `Assert( ~image_in_cancel,  "Cancel Idle Again Still"  );

            if_clock;

        end
    endtask

    initial begin
        $display( "\nImage FIFO Test %s", `__FILE__ );

        if_init;
        if_reset;

        if_check_initial_state;

        if_single_stepping( 0 );
        if_single_stepping( 1 );

        if_partial_load( 0 );
        if_partial_load( 1 );

        if_fill( 0 );
        if_fill( 1 );

        if_check_in_to_out_signals;
        if_check_out_to_in_signals;

        `AssertSummary

        $finish;
    end



endmodule
module image_fifo_tb();



    parameter Output=`OutputInfo;


    localparam [`IS_w-1:0] ImageSpec = `IS_DEFAULT;
    localparam ImageWidth = `I_w( ImageSpec );
    localparam ImageDataWidth = `I_Data_w( ImageSpec );
    localparam MemoryWidth = 3;
    localparam MemorySize = 1 << MemoryWidth;

    reg  reset;

    initial begin
      $dumpfile("image_fifo_tb.vcd");
      $dumpvars( 0, image_fifo_tb );
    end


    `Realtime


    `Clock10MHz

    `AssertSetup

    wire [ImageWidth-1:0] image_in;
    wire [ImageWidth-1:0] image_out;

    image_fifo #( .InIS( ImageSpec ), .OutIS( ImageSpec ), .MemoryWidth( MemoryWidth ) ) i_f (
        .clock( clock ),
        .reset( reset ),

        .image_in( image_in ),
        .image_out( image_out )
    );


    reg                       image_in_start;
    reg                       image_in_stop;
    reg [ImageDataWidth-1:0]  image_in_data;
    reg                       image_in_valid;
    reg                       image_in_error;
    wire                      image_in_ready;
    wire                      image_in_request;
    wire                      image_in_cancel;

    assign     `I_Start( ImageSpec, image_in ) = image_in_start;
    assign     `I_Stop( ImageSpec, image_in ) = image_in_stop;
    assign     `I_Data( ImageSpec, image_in ) = image_in_data;
    assign     `I_Valid( ImageSpec, image_in ) = image_in_valid;
    assign     `I_Error( ImageSpec, image_in ) = image_in_error;
    assign     image_in_ready   = `I_Ready( ImageSpec, image_in );
    assign     image_in_request = `I_Request( ImageSpec, image_in );
    assign     image_in_cancel  = `I_Cancel( ImageSpec, image_in );

    wire                      image_out_start;
    wire                      image_out_stop;
    wire [ImageDataWidth-1:0] image_out_data;
    wire                      image_out_valid;
    wire                      image_out_error;
    reg                       image_out_ready;
    reg                       image_out_request;
    reg                       image_out_cancel;

    assign     image_out_start = `I_Start( ImageSpec, image_out ) ;
    assign     image_out_stop = `I_Stop( ImageSpec, image_out ) ;
    assign     image_out_data = `I_Data( ImageSpec, image_out ) ;
    assign     image_out_valid = `I_Valid( ImageSpec, image_out ) ;
    assign     image_out_error = `I_Error( ImageSpec, image_out ) ;
    assign     `I_Ready( ImageSpec, image_out ) = image_out_ready;
    assign     `I_Request( ImageSpec, image_out ) = image_out_request;
    assign     `I_Cancel( ImageSpec, image_out ) = image_out_cancel;

    task if_init;
        begin
            image_in_start = 0;
            image_in_stop = 0;
            image_in_data = 0;
            image_in_valid = 0;
            image_in_error = 0;

            image_out_ready = 1;
            image_out_request = 0;
            image_out_cancel = 0;
        end
    endtask

    task  if_clock;
        begin
            #2
            @( posedge clock );
            `Debug( "            Clock");
            #2
            ;
        end
    endtask

    task  if_reset;
        begin
            reset = 1;
            if_clock;
            `Info( "    Reset");
            reset = 0;
            if_clock;
        end
    endtask

    task if_in( input reg start_in, input reg stop_in, input reg [ImageDataWidth-1:0] data_in );
        begin
            image_in_start = start_in;
            image_in_stop = stop_in;
            image_in_data = data_in;
            image_in_valid = 1;

            `InfoDo $display( "            In:  %0x:%0x:%0x", start_in, stop_in, data_in );

            if_clock;

            image_in_start = 0;
            image_in_stop = 0;
            image_in_data = 0;
            image_in_valid = 0;
        end
    endtask


    integer i, j, k;

    reg                    start, start0;
    reg                    stop, stop0;
    reg [ImageDataWidth:0] data, data0;

    reg [8*50:1] test_name;

    task if_out( input reg valid_out, input reg start_out, input reg stop_out, input reg [ImageDataWidth-1:0] data_out );
        begin
            `InfoDo $display( "                        Out: %0x:%0x:%0x (%0x)", image_out_start, image_out_stop, image_out_data, image_out_valid );
            `AssertEqual( image_out_valid, valid_out, test_name );
            `AssertEqual( image_out_start, start_out, test_name );
            `AssertEqual( image_out_stop, stop_out, test_name );
            `AssertEqual( image_out_data, data_out, test_name );
        end
    endtask

    task if_check_initial_state;
        begin
            `Info( "Initial State" );
            test_name = "Initial State";

            `Assert( image_in_ready, test_name );

            `Assert( !image_in_valid, test_name );
        end
    endtask

    task if_single_stepping( input  reg pauses );
        begin
            `InfoDo $display( "Single Stepping Pauses = %0x", pauses );

            if_check_initial_state;

            test_name = "Single Stepping";

            image_out_ready = 1;



            for ( i = 0; i < MemorySize * 3; i = i + 1 ) begin
                start = i % 2;
                stop = i % 3;
                data = i + 8'H10;
                if_in( start, stop, data );


                if ( pauses ) begin
                    image_out_ready = 0;
                    for ( j = 0; j < 4; j = j + 1 ) begin
                        `Info( "        Hold" );
                        if_out( 1, start, stop, data );
                        if_clock;
                    end
                    image_out_ready = 1;
                end

                if_out( 1, start, stop, data );
            end

            if_clock;
            if_out( 0, 0, 0, 0 );

        end
    endtask

    task if_partial_load( input  reg pauses );
        begin
            `InfoDo $display( "Partial Load Pauses = %0x", pauses );

            if_check_initial_state;

            test_name = "Partial Load";


            for ( j = 0; j < 3; j = j + 1 ) begin
                `InfoDo $display( "    Filling %0d", j );

                image_out_ready = 0;


                start0 = 0;
                stop0 = 0;
                data0 = 8'H10 * j;
                for ( i = 0; i < 2 * MemorySize / 3; i = i + 1 ) begin
                    start = i % 2;
                    stop = i % 3;
                    data = data0 + i;
                    if_in( start, stop, data );
                    if_out( 1, start0, stop0, data0 );
                    if ( pauses ) begin
                        for ( k = 0; k < 4; k = k + 1 ) begin
                            `Info( "        Pause" );
                            if_out( 1, start0, stop0, data0 );
                            if_clock;
                        end
                    end
                end

                image_out_ready = 1;

                `InfoDo $display( "    Emptying %0d", j );


                for ( i = 0; i < 2 * MemorySize / 3; i = i + 1 ) begin
                    start = i % 2;
                    stop = i % 3;
                    data = data0 + i;
                    if_out( 1, start, stop, data );
                    if ( pauses ) begin
                        image_out_ready = 0;
                        for ( k = 0; k < 4; k = k + 1 ) begin
                            `Info( "        Hold" );
                            if_out( 1, start, stop, data );
                            if_clock;
                        end
                        image_out_ready = 1;
                    end
                    if_clock;



                end

                if_out( 0, 0, 0, 0 );
            end
        end
    endtask

    localparam FillExtra = 10;

    task if_fill( input reg pauses );
        begin
            `InfoDo $display( "Fill Pauses = %0x", pauses );

            if_check_initial_state;

            test_name = "Fill";


            for ( j = 0; j < 3; j = j + 1 ) begin
                `InfoDo $display( "    Fill To Full %0d", j );

                image_out_ready = 0;


                start0 = 0;
                stop0 = 0;
                data0 = 8'H10 * j;
                for ( i = 0; i < MemorySize + FillExtra; i = i + 1 ) begin
                    start = i % 2;
                    stop = i % 3;
                    data = data0 + i;
                    if_in( start, stop, data );
                    if_out( 1, start0, stop0, data0 );
                    if ( i >= MemorySize ) begin
                        `Info( "        FULL" );
                        `Assert( ~image_in_ready, test_name );
                    end
                    if ( pauses ) begin
                        for ( k = 0; k < 4; k = k + 1 ) begin
                            `Info( "        Pause" );
                            if_out( 1, start0, stop0, data0 );
                            if_clock;
                        end
                    end
                end

                image_out_ready = 1;

                `InfoDo $display( "    Emptying %0d", j );


                for ( i = 0; i < MemorySize; i = i + 1 ) begin
                    start = i % 2;
                    stop = i % 3;
                    data = data0 + i;
                    if_out( 1, start, stop, data );

                    if ( pauses ) begin
                        image_out_ready = 0;
                        for ( k = 0; k < 4; k = k + 1 ) begin
                            `Info( "        Hold" );
                            if_out( 1, start, stop, data );
                            if_clock;
                        end
                        image_out_ready = 1;
                    end

                    if_clock;
                end


                if_out( 0, 0, 0, 0 );
            end
        end
    endtask

    task if_check_in_to_out_signals;
        begin
            `Info( "    In to Out Signals" );

            image_in_error = 0;

            if_clock;

            `Assert( ~image_out_error, "Error Idle"  );

            `Info( "        Checking Error Up" );

            image_in_error = 1;

            if_clock;

            `Assert( image_out_error, "Error Not Idle"  );

            `Info( "        Checking Error Down" );

            image_in_error = 0;

            if_clock;

            `Assert( !image_out_error, "Error Idle Again"  );

            if_clock;

        end
    endtask

    task if_check_out_to_in_signals;
        begin

            `Info( "    Out to In Signals" );

            image_out_request = 0;
            image_out_cancel = 0;


            if_clock;

            `Assert( ~image_in_request, "Request Idle"  );
            `Assert( ~image_in_cancel,  "Cancel Idle"  );

            `Info( "        Checking Request Up" );

            image_out_request = 1;

            if_clock;

            `Assert( image_in_request, "Request Not Idle"  );
            `Assert( ~image_in_cancel,  "Cancel Idle Still"  );

            if_clock;

            `Assert( image_in_request, "Request Not Idle"  );
            `Assert( ~image_in_cancel,  "Cancel Idle Still"  );

            if_clock;

            `Info( "        Checking Request Down" );

            image_out_request = 0;

            if_clock;

            `Assert( !image_in_request, "Request Idle Again"  );
            `Assert( ~image_in_cancel,  "Cancel Idle Still"  );

            if_clock;

            `Assert( ~image_in_request, "Request Idle"  );
            `Assert( ~image_in_cancel,  "Cancel Idle"  );

            `Info( "        Checking Request Up" );

            image_out_cancel = 1;

            if_clock;

            `Assert( ~image_in_request, "Request Idle"  );
            `Assert( image_in_cancel,  "Cancel Not Idle"  );

            `Info( "        Checking Request Down" );

            image_out_cancel = 0;

            if_clock;

            `Assert( ~image_in_request, "Request Idle Still"  );
            `Assert( ~image_in_cancel,  "Cancel Idle Again Still"  );

            if_clock;

        end
    endtask

    initial begin
        $display( "\nImage FIFO Test %s", `__FILE__ );

        if_init;
        if_reset;

        if_check_initial_state;

        if_single_stepping( 0 );
        if_single_stepping( 1 );

        if_partial_load( 0 );
        if_partial_load( 1 );

        if_fill( 0 );
        if_fill( 1 );

        if_check_in_to_out_signals;
        if_check_out_to_in_signals;

        `AssertSummary

        $finish;
    end



endmodule