data/full_repos/permissive/208325333/Files/RAM_double_addr.v
data/verilator_xmls/9c539429-0624-4293-9fba-7772767645af.xml
module RAM_double_addr #(
         parameter AW = 5,
         parameter DW = 4)

       (
         input clk,
         input wire [AW-1: 0] addr_write,
         input wire [AW-1: 0] addr_read,
         input wire rw,
         input wire [DW-1: 0] data_in,
         output reg [DW-1: 0] data_out);


parameter ROMFILE = "bufferini.list";


localparam NPOS = 2 ** AW;


  reg [DW-1: 0] ram [0: NPOS-1];


  always @(posedge clk) begin
    if (rw == 1) begin
    	 data_out <= ram[addr_read];
   	end
   	
    else if (rw == 0) begin
    	 ram[addr_write] <= data_in;
    	 data_out <= ram[addr_write];
    end
  end



initial begin
  $readmemh(ROMFILE, ram);
end


endmodule
module RAM_double_addr #(
         parameter AW = 5,
         parameter DW = 4)

       (
         input clk,
         input wire [AW-1: 0] addr_write,
         input wire [AW-1: 0] addr_read,
         input wire rw,
         input wire [DW-1: 0] data_in,
         output reg [DW-1: 0] data_out);



parameter ROMFILE = "bufferini.list";


localparam NPOS = 2 ** AW;


  reg [DW-1: 0] ram [0: NPOS-1];


  always @(posedge clk) begin
    if (rw == 1) begin
    	 data_out <= ram[addr_read];
   	end
   	
    else if (rw == 0) begin
    	 ram[addr_write] <= data_in;
    	 data_out <= ram[addr_write];
    end
  end



initial begin
  $readmemh(ROMFILE, ram);
end


endmodule