data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v
None: at end of input
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:50: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/or1200,data/full_repos/permissive/17099167/timescale.v\n             data/full_repos/permissive/17099167/system/hardware/cores/or1200,data/full_repos/permissive/17099167/timescale.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/or1200,data/full_repos/permissive/17099167/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:52: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:88: Define or directive not defined: \'`OR1200_OPERAND_WIDTH\'\n   parameter width = `OR1200_OPERAND_WIDTH;\n                     ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter width = `OR1200_OPERAND_WIDTH;\n                                          ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:114: Define or directive not defined: \'`OR1200_BRANCHOP_WIDTH\'\n   input [`OR1200_BRANCHOP_WIDTH-1:0]  branch_op;  \n          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:117: Define or directive not defined: \'`OR1200_SR_WIDTH\'\n   input [`OR1200_SR_WIDTH-1:0]  esr /*verilator public*/ ;  \n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:125: Define or directive not defined: \'`OR1200_SR_WIDTH\'\n   output [`OR1200_SR_WIDTH-1:0]  to_sr;   \n           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:126: Define or directive not defined: \'`OR1200_SR_WIDTH\'\n   output [`OR1200_SR_WIDTH-1:0]  sr /*verilator public*/ ; \n           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:134: Define or directive not defined: \'`OR1200_FPCSR_WIDTH\'\n   input [`OR1200_FPCSR_WIDTH-1:0]  fpcsr;  \n          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:170: Define or directive not defined: \'`OR1200_SR_WIDTH\'\n   input [`OR1200_SR_WIDTH-1:0]  sp_esr_ghost;  \n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:181: Define or directive not defined: \'`OR1200_SR_WIDTH\'\n   reg [`OR1200_SR_WIDTH-1:0]   sr_reg;   \n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:185: Define or directive not defined: \'`OR1200_SR_WIDTH\'\n   reg [`OR1200_SR_WIDTH-1:0]   sr;    \n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:270: Define or directive not defined: \'`OR1200_SR_SM\'\n   assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & (sr[`OR1200_SR_SM] | (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPR_GROUP_WIDTH\'d07)))}};\n                                                                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:270: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & (sr[`OR1200_SR_SM] | (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPR_GROUP_WIDTH\'d07)))}};\n                                                                                                            ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:270: Define or directive not defined: \'`OR1200_SPR_GROUP_BITS\'\n   assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & (sr[`OR1200_SR_SM] | (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPR_GROUP_WIDTH\'d07)))}};\n                                                                                                                          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:270: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n   assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & (sr[`OR1200_SR_SM] | (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPR_GROUP_WIDTH\'d07)))}};\n                                                                                                                                                     ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:276: Define or directive not defined: \'`OR1200_SPR_GROUP_BITS\'\n     case (spr_addr[`OR1200_SPR_GROUP_BITS])  \n                    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:276: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n     case (spr_addr[`OR1200_SPR_GROUP_BITS])  \n                                          ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:277: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d00: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:279: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d01: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:281: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d02: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:283: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d03: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:285: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d04: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:287: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d05: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:289: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d06: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:291: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d07: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:293: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d08: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:295: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d09: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:297: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d10: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:299: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d11: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:301: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d12: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:303: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d13: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:305: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d14: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:307: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d15: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:309: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d16: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:311: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d17: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:313: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d18: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:315: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d19: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:317: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d20: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:319: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d21: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:321: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d22: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:323: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d23: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:325: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d24: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:327: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d25: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:329: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d26: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:331: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d27: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:333: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d28: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:335: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d29: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:337: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d30: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/or1200/or1200_sprs.v:339: Define or directive not defined: \'`OR1200_SPR_GROUP_WIDTH\'\n       `OR1200_SPR_GROUP_WIDTH\'d31: unqualified_cs \n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module or1200_sprs(

		   clk, rst,


		   flagforw, flag_we, flag, cyforw, cy_we, carry,
		   ovforw, ov_we, dsx,
		   addrbase, addrofs, dat_i, branch_op, ex_spr_read, 
		   ex_spr_write, 
		   epcr, eear, esr, except_started,
		   to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
		   spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, 
		   spr_dat_mac,
		   
		   boot_adr_sel_i,


		   fpcsr, fpcsr_we, spr_dat_fpu,
	

		   spr_dat_pic, spr_dat_tt, spr_dat_pm,
		   spr_dat_dmmu, spr_dat_immu, spr_dat_du,
		   spr_addr, spr_dat_o, spr_cs, spr_we,

		   du_addr, du_dat_du, du_read,
		   du_write, du_dat_cpu

		   , ex_pc, ex_void, except_illegal,
		   sp_epcr_ghost_we, sp_eear_ghost_we, sp_esr_ghost_we,
		   sp_epcr_ghost, sp_eear_ghost, sp_esr_ghost,
		   sp_address, sp_data, sp_strobe
		   , sp_assertions_violated, sp_assertion_violated, sp_attack_enable
		   );

   parameter width = `OR1200_OPERAND_WIDTH;








   input				clk;
   input 				rst;
   input 				flagforw;
   input 				flag_we;
   output 				flag;
   input 				cyforw;
   input 				cy_we;
   output 				carry;
   input 				ovforw;
   input 				ov_we;
   input 				dsx;
   
   input [width-1:0] 			addrbase;
   input [15:0] 			addrofs;
   input [width-1:0] 			dat_i;
   input 				ex_spr_read;
   input 				ex_spr_write;
   input [`OR1200_BRANCHOP_WIDTH-1:0] 	branch_op;
   input [width-1:0] 			epcr;
   input [width-1:0] 			eear;
   input [`OR1200_SR_WIDTH-1:0] 	esr;
   input 				except_started;
   output [width-1:0] 			to_wbmux;
   output				epcr_we;
   output				eear_we;
   output				esr_we;
   output				pc_we;
   output 				sr_we;
   output [`OR1200_SR_WIDTH-1:0] 	to_sr;
   output [`OR1200_SR_WIDTH-1:0] 	sr;
   input [31:0] 			spr_dat_cfgr;
   input [31:0] 			spr_dat_rf;
   input [31:0] 			spr_dat_npc;
   input [31:0] 			spr_dat_ppc;
   input [31:0] 			spr_dat_mac;
   input				boot_adr_sel_i;

   input [`OR1200_FPCSR_WIDTH-1:0] 	fpcsr;
   output 				fpcsr_we;
   input [31:0] 			spr_dat_fpu;
   



   input [31:0] 			spr_dat_pic;
   input [31:0] 			spr_dat_tt;
   input [31:0] 			spr_dat_pm;
   input [31:0] 			spr_dat_dmmu;
   input [31:0] 			spr_dat_immu;
   input [31:0] 			spr_dat_du;
   output [31:0] 			spr_addr;
   output [31:0] 			spr_dat_o;
   output [31:0] 			spr_cs;
   output				spr_we;




   input [width-1:0] 			du_addr;
   input [width-1:0] 			du_dat_du;
   input				du_read;
   input				du_write;
   output [width-1:0] 			du_dat_cpu;
   

   input [31:0]				ex_pc;   
   input ex_void;
   input except_illegal;
   output				sp_epcr_ghost_we;
   output				sp_eear_ghost_we;
   output				sp_esr_ghost_we;
   input [width-1:0] 			sp_epcr_ghost;
   input [width-1:0] 			sp_eear_ghost;
   input [`OR1200_SR_WIDTH-1:0] 	sp_esr_ghost;
   output [31:0] 			sp_address;
   output [31:0] 			sp_data;
   output [31:0] 			sp_strobe;
   input [31:0] 			sp_assertions_violated;
   input        			sp_assertion_violated;
   output [31:0] 			sp_attack_enable;
   



   reg [`OR1200_SR_WIDTH-1:0] 		sr_reg;
   reg 					sr_reg_bit_eph;
   reg 					sr_reg_bit_eph_select;
   wire 				sr_reg_bit_eph_muxed;
   reg [`OR1200_SR_WIDTH-1:0] 		sr;
   reg [width-1:0] 			to_wbmux;
   wire 				cfgr_sel;
   wire 				rf_sel;
   wire 				npc_sel;
   wire 				ppc_sel;
   wire 				sr_sel;
   wire 				epcr_sel;
   wire 				eear_sel;
   wire 				esr_sel;
   wire 				fpcsr_sel;
   wire [31:0] 				sys_data;
   wire 				du_access;
   reg [31:0] 				unqualified_cs;
   wire 				ex_spr_write;



   reg [31:0] 				sp_reg0;
   wire 				sp_reg0_we;
   wire 				sp_reg0_sel;
   reg [31:0] 				sp_reg1;
   wire 				sp_reg1_we;
   wire 				sp_reg1_sel;
   reg [31:0] 				sp_reg2;
   wire 				sp_reg2_we;
   wire 				sp_reg2_sel;
   reg [31:0] 				sp_reg3;
   wire 				sp_reg3_we;
   wire 				sp_reg3_sel;
   reg [31:0] 				sp_reg4;
   wire 				sp_reg4_we;
   wire 				sp_reg4_sel;
   wire 				sp_reg5_sel;
   reg [31:0] 				sp_reg6;
   wire 				sp_reg6_we;
   wire 				sp_reg6_sel;
   reg [31:0] 				sp_reg7;
   wire 				sp_reg7_sel;


   assign sp_address = sp_reg1;
   assign sp_data = sp_reg2;
   assign sp_strobe = sp_reg3;
   assign sp_attack_enable = sp_reg6;
   

   wire 				sp_esr_ghost_sel;
   wire 				sp_epcr_ghost_sel;
   wire 				sp_eearr_ghost_sel;
   



   assign du_access = du_read | du_write;





   assign spr_addr = du_access ? du_addr : (addrbase | {16'h0000, addrofs});




   assign spr_dat_o = du_write ? du_dat_du : dat_i;







   assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;




   assign spr_we = du_write | ( ex_spr_write & !du_access );






   assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & (sr[`OR1200_SR_SM] | (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPR_GROUP_WIDTH'd07)))}};




   always @(spr_addr)
     case (spr_addr[`OR1200_SPR_GROUP_BITS])
       `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs 
	 = 32'b00000000_00000000_00000000_00000001;
       `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs 
	 = 32'b00000000_00000000_00000000_00000010;
       `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs 
	 = 32'b00000000_00000000_00000000_00000100;
       `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs 
	 = 32'b00000000_00000000_00000000_00001000;
       `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs 
	 = 32'b00000000_00000000_00000000_00010000;
       `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs 
	 = 32'b00000000_00000000_00000000_00100000;
       `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs 
	 = 32'b00000000_00000000_00000000_01000000;
       `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs 
	 = 32'b00000000_00000000_00000000_10000000;
       `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs 
	 = 32'b00000000_00000000_00000001_00000000;
       `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs 
	 = 32'b00000000_00000000_00000010_00000000;
       `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs 
	 = 32'b00000000_00000000_00000100_00000000;
       `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs 
	 = 32'b00000000_00000000_00001000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs 
	 = 32'b00000000_00000000_00010000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs 
	 = 32'b00000000_00000000_00100000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs 
	 = 32'b00000000_00000000_01000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs 
	 = 32'b00000000_00000000_10000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs 
	 = 32'b00000000_00000001_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs 
	 = 32'b00000000_00000010_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs 
	 = 32'b00000000_00000100_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs 
	 = 32'b00000000_00001000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs 
	 = 32'b00000000_00010000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs 
	 = 32'b00000000_00100000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs 
	 = 32'b00000000_01000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs 
	 = 32'b00000000_10000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs 
	 = 32'b00000001_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs 
	 = 32'b00000010_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs 
	 = 32'b00000100_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs 
	 = 32'b00001000_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs 
	 = 32'b00010000_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs 
	 = 32'b00100000_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs 
	 = 32'b01000000_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs 
	 = 32'b10000000_00000000_00000000_00000000;
     endcase








   assign to_sr[`OR1200_SR_FO:`OR1200_SR_OVE] 
	    = (except_started) ? {sr[`OR1200_SR_FO:`OR1200_SR_EPH],dsx,1'b0} :
	      (branch_op == `OR1200_BRANCHOP_RFE) ? 
	      (`SP_IIE_ADDR_COMPARE) ? sp_esr_ghost[`OR1200_SR_FO:`OR1200_SR_OVE] : esr[`OR1200_SR_FO:`OR1200_SR_OVE] : (spr_we && sr_sel) ? 
	      {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OVE]} :
	      sr[`OR1200_SR_FO:`OR1200_SR_OVE];
   assign to_sr[`OR1200_SR_TED] 
	    = (except_started) ? 1'b1 :
	      (branch_op == `OR1200_BRANCHOP_RFE) ? 
	      (`SP_IIE_ADDR_COMPARE) ? sp_esr_ghost[`OR1200_SR_TED] : esr[`OR1200_SR_TED] :
	      (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED] :
	      sr[`OR1200_SR_TED];
   assign to_sr[`OR1200_SR_OV] 
	    = (except_started) ? sr[`OR1200_SR_OV] :
	      (branch_op == `OR1200_BRANCHOP_RFE) ? 
	      (`SP_IIE_ADDR_COMPARE) ? sp_esr_ghost[`OR1200_SR_OV] : esr[`OR1200_SR_OV] :
	      ov_we ? ovforw :
	      (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_OV] :
	      sr[`OR1200_SR_OV];
   assign to_sr[`OR1200_SR_CY] 
	    = (except_started) ? sr[`OR1200_SR_CY] :
	      (branch_op == `OR1200_BRANCHOP_RFE) ? 
	      (`SP_IIE_ADDR_COMPARE) ? sp_esr_ghost[`OR1200_SR_CY] : esr[`OR1200_SR_CY] :
	      cy_we ? cyforw :
	      (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
	      sr[`OR1200_SR_CY];
   assign to_sr[`OR1200_SR_F] 
	    = (except_started) ? sr[`OR1200_SR_F] :
	      (branch_op == `OR1200_BRANCHOP_RFE) ? 
	      (`SP_IIE_ADDR_COMPARE) ? sp_esr_ghost[`OR1200_SR_F] : esr[`OR1200_SR_F] :
	      flag_we ? flagforw :
	      (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
	      sr[`OR1200_SR_F];
   
   assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] 
	    = (except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00, 
				  sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
	      (branch_op == `OR1200_BRANCHOP_RFE) ? 
	      (`SP_IIE_ADDR_COMPARE) ? sp_esr_ghost[`OR1200_SR_CE:`OR1200_SR_SM] : esr[`OR1200_SR_CE:`OR1200_SR_SM] : (spr_we && sr_sel) ? 
	      spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM] :
	      sr[`OR1200_SR_CE:`OR1200_SR_SM];




   assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		      (spr_addr[10:4] == `OR1200_SPR_CFGR));
   assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		    (spr_addr[10:5] == `OR1200_SPR_RF));
   assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		     (spr_addr[10:0] == `OR1200_SPR_NPC));
   assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		     (spr_addr[10:0] == `OR1200_SPR_PPC));
   assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		    (spr_addr[10:0] == `OR1200_SPR_SR));
   assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		      (spr_addr[10:0] == `OR1200_SPR_EPCR));
   assign sp_epcr_ghost_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		      (spr_addr[10:0] == (`OR1200_SPR_EPCR + 1)));
   assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		      (spr_addr[10:0] == `OR1200_SPR_EEAR));
   assign sp_eear_ghost_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		      (spr_addr[10:0] == (`OR1200_SPR_EEAR+1)));
   assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		     (spr_addr[10:0] == `OR1200_SPR_ESR));
   assign sp_esr_ghost_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		     (spr_addr[10:0] == (`OR1200_SPR_ESR+1)));
   assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		       (spr_addr[10:0] == `OR1200_SPR_FPCSR));
   assign sp_reg0_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR0));
   assign sp_reg4_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR4));
   assign sp_reg1_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR1));
   assign sp_reg2_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR2));
   assign sp_reg3_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR3));
   assign sp_reg5_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR5));
   assign sp_reg6_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR6));
   assign sp_reg7_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR7));
   



   assign sr_we = (spr_we && sr_sel) | (~except_illegal & ~sp_assertion_violated & ~ex_void & (branch_op == `OR1200_BRANCHOP_RFE)) | flag_we | cy_we | ov_we;
   assign pc_we = (du_write && (npc_sel | ppc_sel));
   assign epcr_we = (spr_we && epcr_sel);
   assign eear_we = (spr_we && eear_sel);
   assign esr_we = (spr_we && esr_sel);
   assign fpcsr_we = (spr_we && fpcsr_sel);
   assign sp_epcr_ghost_we = (spr_we && sp_epcr_ghost_sel);
   assign sp_eear_ghost_we = (spr_we && sp_eear_ghost_sel);
   assign sp_esr_ghost_we = (spr_we && sp_esr_ghost_sel);
   assign sp_reg0_we = spr_we & sp_reg0_sel;
   assign sp_reg4_we = spr_we & sp_reg4_sel;
   assign sp_reg1_we = spr_we & sp_reg1_sel;
   assign sp_reg2_we = spr_we & sp_reg2_sel;
   assign sp_reg3_we = spr_we & sp_reg3_sel;
   assign sp_reg6_we = spr_we & sp_reg6_sel;

   



   assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
		     (sp_esr_ghost & {32{sp_esr_ghost_sel}}) |
		     (sp_epcr_ghost & {32{sp_epcr_ghost_sel}}) |
		     (sp_eear_ghost & {32{sp_eear_ghost_sel}}) |
		     (sp_reg0 & {32{sp_reg0_sel}}) |
		     (sp_reg4 & {32{sp_reg4_sel}}) |
		     (sp_reg1 & {32{sp_reg1_sel}}) |
		     (sp_reg2 & {32{sp_reg2_sel}}) |
		     (sp_reg3 & {32{sp_reg3_sel}}) |
		     (sp_assertions_violated & {32{sp_reg5_sel}}) |
		     (sp_reg6 & {32{sp_reg6_sel}}) |
		     (sp_reg7 & {32{sp_reg7_sel}}) |
		     (spr_dat_rf & {32{rf_sel}}) |
		     (spr_dat_npc & {32{npc_sel}}) |
		     (spr_dat_ppc & {32{ppc_sel}}) |
		     ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
		     (epcr & {32{epcr_sel}}) |
		     (eear & {32{eear_sel}}) |
		     ({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} & 
		      {32{fpcsr_sel}}) |
		     ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});




   assign flag = sr[`OR1200_SR_F];




   assign carry = sr[`OR1200_SR_CY];


   always @(posedge clk or `OR1200_RST_EVENT rst) begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg7 <= 0;
      else if(sp_assertion_violated)
	sp_reg7 <= spr_dat_ppc;
   end


   always @(posedge clk or `OR1200_RST_EVENT rst) begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg0 <= 0;
      else if(sp_reg0_we == 1'b1)
	sp_reg0 <= spr_dat_o;
   end


   always@(posedge clk or `OR1200_RST_EVENT rst)begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg4 <= 0;
      else if(sp_reg4_we == 1'b1)
	sp_reg4 <= spr_dat_o;
   end


   always@(posedge clk or `OR1200_RST_EVENT rst)begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg1 <= 32'd2000;
      else if(sp_reg1_we == 1'b1)
	sp_reg1 <= spr_dat_o;
   end


   always@(posedge clk or `OR1200_RST_EVENT rst)begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg2 <= 0;
      else if(sp_reg2_we == 1'b1)
	sp_reg2 <= spr_dat_o;
   end


   always@(posedge clk or `OR1200_RST_EVENT rst)begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg3 <= 0;
      else if(sp_reg3_we == 1'b1)
	sp_reg3 <= spr_dat_o;   
   end


   always@(posedge clk or `OR1200_RST_EVENT rst)begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg6 <= 0;
      else if(sp_reg6_we == 1'b1)
	sp_reg6 <= spr_dat_o;   
   end
      



   always @(posedge clk or `OR1200_RST_EVENT rst)
     if (rst == `OR1200_RST_VALUE)
       sr_reg <=  {2'b01,
		   `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
     else if (except_started)
       sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
     else if (sr_we)
       sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
   

   always @(posedge clk or `OR1200_RST_EVENT rst)

     if (rst == `OR1200_RST_VALUE) begin
	sr_reg_bit_eph <=  `OR1200_SR_EPH_DEF;

	sr_reg_bit_eph_select <=  1'b1;	
     end


     else if (sr_reg_bit_eph_select) begin

	sr_reg_bit_eph <=  boot_adr_sel_i;
	sr_reg_bit_eph_select <=  1'b0;
     end
     else if (sr_we) begin
	sr_reg_bit_eph <=  to_sr[`OR1200_SR_EPH];
     end


   assign	sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ? 
				       boot_adr_sel_i : sr_reg_bit_eph;


   always @(sr_reg or sr_reg_bit_eph_muxed or sp_reg3)
     sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed,
	   sr_reg[`OR1200_SR_WIDTH-4:0]};

`ifdef verilator




   function [31:0] get_sr;

      get_sr = {{32-`OR1200_SR_WIDTH{1'b0}},sr};
   endfunction

   function [31:0] get_epcr;

      get_epcr = epcr;
   endfunction

   function [31:0] get_eear;

      get_eear = eear;
   endfunction

   function [31:0] get_esr;

      get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
   endfunction

`endif
   



   always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
	    spr_dat_fpu or
	    spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
      casez (spr_addr[`OR1200_SPR_GROUP_BITS])
	`OR1200_SPR_GROUP_PC:
	  to_wbmux = sys_data;
	`OR1200_SPR_GROUP_SYS:
	  to_wbmux = sys_data;
	`OR1200_SPR_GROUP_TT:
	  to_wbmux = spr_dat_tt;
	`OR1200_SPR_GROUP_PIC:
	  to_wbmux = spr_dat_pic;
	`OR1200_SPR_GROUP_PM:
	  to_wbmux = spr_dat_pm;
	`OR1200_SPR_GROUP_DMMU:
	  to_wbmux = spr_dat_dmmu;
	`OR1200_SPR_GROUP_IMMU:
	  to_wbmux = spr_dat_immu;
	`OR1200_SPR_GROUP_MAC:
	  to_wbmux = spr_dat_mac;
	`OR1200_SPR_GROUP_FPU:
	  to_wbmux = spr_dat_fpu;
	default:
	  to_wbmux = spr_dat_du;
      endcase
   end

endmodule
module or1200_sprs(

		   clk, rst,


		   flagforw, flag_we, flag, cyforw, cy_we, carry,
		   ovforw, ov_we, dsx,
		   addrbase, addrofs, dat_i, branch_op, ex_spr_read, 
		   ex_spr_write, 
		   epcr, eear, esr, except_started,
		   to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
		   spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, 
		   spr_dat_mac,
		   
		   boot_adr_sel_i,


		   fpcsr, fpcsr_we, spr_dat_fpu,
	

		   spr_dat_pic, spr_dat_tt, spr_dat_pm,
		   spr_dat_dmmu, spr_dat_immu, spr_dat_du,
		   spr_addr, spr_dat_o, spr_cs, spr_we,

		   du_addr, du_dat_du, du_read,
		   du_write, du_dat_cpu

		   , ex_pc, ex_void, except_illegal,
		   sp_epcr_ghost_we, sp_eear_ghost_we, sp_esr_ghost_we,
		   sp_epcr_ghost, sp_eear_ghost, sp_esr_ghost,
		   sp_address, sp_data, sp_strobe
		   , sp_assertions_violated, sp_assertion_violated, sp_attack_enable
		   );


   parameter width = `OR1200_OPERAND_WIDTH;








   input				clk;
   input 				rst;
   input 				flagforw;
   input 				flag_we;
   output 				flag;
   input 				cyforw;
   input 				cy_we;
   output 				carry;
   input 				ovforw;
   input 				ov_we;
   input 				dsx;
   
   input [width-1:0] 			addrbase;
   input [15:0] 			addrofs;
   input [width-1:0] 			dat_i;
   input 				ex_spr_read;
   input 				ex_spr_write;
   input [`OR1200_BRANCHOP_WIDTH-1:0] 	branch_op;
   input [width-1:0] 			epcr;
   input [width-1:0] 			eear;
   input [`OR1200_SR_WIDTH-1:0] 	esr;
   input 				except_started;
   output [width-1:0] 			to_wbmux;
   output				epcr_we;
   output				eear_we;
   output				esr_we;
   output				pc_we;
   output 				sr_we;
   output [`OR1200_SR_WIDTH-1:0] 	to_sr;
   output [`OR1200_SR_WIDTH-1:0] 	sr;
   input [31:0] 			spr_dat_cfgr;
   input [31:0] 			spr_dat_rf;
   input [31:0] 			spr_dat_npc;
   input [31:0] 			spr_dat_ppc;
   input [31:0] 			spr_dat_mac;
   input				boot_adr_sel_i;

   input [`OR1200_FPCSR_WIDTH-1:0] 	fpcsr;
   output 				fpcsr_we;
   input [31:0] 			spr_dat_fpu;
   



   input [31:0] 			spr_dat_pic;
   input [31:0] 			spr_dat_tt;
   input [31:0] 			spr_dat_pm;
   input [31:0] 			spr_dat_dmmu;
   input [31:0] 			spr_dat_immu;
   input [31:0] 			spr_dat_du;
   output [31:0] 			spr_addr;
   output [31:0] 			spr_dat_o;
   output [31:0] 			spr_cs;
   output				spr_we;




   input [width-1:0] 			du_addr;
   input [width-1:0] 			du_dat_du;
   input				du_read;
   input				du_write;
   output [width-1:0] 			du_dat_cpu;
   

   input [31:0]				ex_pc;   
   input ex_void;
   input except_illegal;
   output				sp_epcr_ghost_we;
   output				sp_eear_ghost_we;
   output				sp_esr_ghost_we;
   input [width-1:0] 			sp_epcr_ghost;
   input [width-1:0] 			sp_eear_ghost;
   input [`OR1200_SR_WIDTH-1:0] 	sp_esr_ghost;
   output [31:0] 			sp_address;
   output [31:0] 			sp_data;
   output [31:0] 			sp_strobe;
   input [31:0] 			sp_assertions_violated;
   input        			sp_assertion_violated;
   output [31:0] 			sp_attack_enable;
   



   reg [`OR1200_SR_WIDTH-1:0] 		sr_reg;
   reg 					sr_reg_bit_eph;
   reg 					sr_reg_bit_eph_select;
   wire 				sr_reg_bit_eph_muxed;
   reg [`OR1200_SR_WIDTH-1:0] 		sr;
   reg [width-1:0] 			to_wbmux;
   wire 				cfgr_sel;
   wire 				rf_sel;
   wire 				npc_sel;
   wire 				ppc_sel;
   wire 				sr_sel;
   wire 				epcr_sel;
   wire 				eear_sel;
   wire 				esr_sel;
   wire 				fpcsr_sel;
   wire [31:0] 				sys_data;
   wire 				du_access;
   reg [31:0] 				unqualified_cs;
   wire 				ex_spr_write;



   reg [31:0] 				sp_reg0;
   wire 				sp_reg0_we;
   wire 				sp_reg0_sel;
   reg [31:0] 				sp_reg1;
   wire 				sp_reg1_we;
   wire 				sp_reg1_sel;
   reg [31:0] 				sp_reg2;
   wire 				sp_reg2_we;
   wire 				sp_reg2_sel;
   reg [31:0] 				sp_reg3;
   wire 				sp_reg3_we;
   wire 				sp_reg3_sel;
   reg [31:0] 				sp_reg4;
   wire 				sp_reg4_we;
   wire 				sp_reg4_sel;
   wire 				sp_reg5_sel;
   reg [31:0] 				sp_reg6;
   wire 				sp_reg6_we;
   wire 				sp_reg6_sel;
   reg [31:0] 				sp_reg7;
   wire 				sp_reg7_sel;


   assign sp_address = sp_reg1;
   assign sp_data = sp_reg2;
   assign sp_strobe = sp_reg3;
   assign sp_attack_enable = sp_reg6;
   

   wire 				sp_esr_ghost_sel;
   wire 				sp_epcr_ghost_sel;
   wire 				sp_eearr_ghost_sel;
   



   assign du_access = du_read | du_write;





   assign spr_addr = du_access ? du_addr : (addrbase | {16'h0000, addrofs});




   assign spr_dat_o = du_write ? du_dat_du : dat_i;







   assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;




   assign spr_we = du_write | ( ex_spr_write & !du_access );






   assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & (sr[`OR1200_SR_SM] | (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPR_GROUP_WIDTH'd07)))}};




   always @(spr_addr)
     case (spr_addr[`OR1200_SPR_GROUP_BITS])
       `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs 
	 = 32'b00000000_00000000_00000000_00000001;
       `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs 
	 = 32'b00000000_00000000_00000000_00000010;
       `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs 
	 = 32'b00000000_00000000_00000000_00000100;
       `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs 
	 = 32'b00000000_00000000_00000000_00001000;
       `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs 
	 = 32'b00000000_00000000_00000000_00010000;
       `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs 
	 = 32'b00000000_00000000_00000000_00100000;
       `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs 
	 = 32'b00000000_00000000_00000000_01000000;
       `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs 
	 = 32'b00000000_00000000_00000000_10000000;
       `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs 
	 = 32'b00000000_00000000_00000001_00000000;
       `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs 
	 = 32'b00000000_00000000_00000010_00000000;
       `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs 
	 = 32'b00000000_00000000_00000100_00000000;
       `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs 
	 = 32'b00000000_00000000_00001000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs 
	 = 32'b00000000_00000000_00010000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs 
	 = 32'b00000000_00000000_00100000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs 
	 = 32'b00000000_00000000_01000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs 
	 = 32'b00000000_00000000_10000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs 
	 = 32'b00000000_00000001_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs 
	 = 32'b00000000_00000010_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs 
	 = 32'b00000000_00000100_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs 
	 = 32'b00000000_00001000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs 
	 = 32'b00000000_00010000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs 
	 = 32'b00000000_00100000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs 
	 = 32'b00000000_01000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs 
	 = 32'b00000000_10000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs 
	 = 32'b00000001_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs 
	 = 32'b00000010_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs 
	 = 32'b00000100_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs 
	 = 32'b00001000_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs 
	 = 32'b00010000_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs 
	 = 32'b00100000_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs 
	 = 32'b01000000_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs 
	 = 32'b10000000_00000000_00000000_00000000;
     endcase








   assign to_sr[`OR1200_SR_FO:`OR1200_SR_OVE] 
	    = (except_started) ? {sr[`OR1200_SR_FO:`OR1200_SR_EPH],dsx,1'b0} :
	      (branch_op == `OR1200_BRANCHOP_RFE) ? 
	      (`SP_IIE_ADDR_COMPARE) ? sp_esr_ghost[`OR1200_SR_FO:`OR1200_SR_OVE] : esr[`OR1200_SR_FO:`OR1200_SR_OVE] : (spr_we && sr_sel) ? 
	      {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OVE]} :
	      sr[`OR1200_SR_FO:`OR1200_SR_OVE];
   assign to_sr[`OR1200_SR_TED] 
	    = (except_started) ? 1'b1 :
	      (branch_op == `OR1200_BRANCHOP_RFE) ? 
	      (`SP_IIE_ADDR_COMPARE) ? sp_esr_ghost[`OR1200_SR_TED] : esr[`OR1200_SR_TED] :
	      (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED] :
	      sr[`OR1200_SR_TED];
   assign to_sr[`OR1200_SR_OV] 
	    = (except_started) ? sr[`OR1200_SR_OV] :
	      (branch_op == `OR1200_BRANCHOP_RFE) ? 
	      (`SP_IIE_ADDR_COMPARE) ? sp_esr_ghost[`OR1200_SR_OV] : esr[`OR1200_SR_OV] :
	      ov_we ? ovforw :
	      (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_OV] :
	      sr[`OR1200_SR_OV];
   assign to_sr[`OR1200_SR_CY] 
	    = (except_started) ? sr[`OR1200_SR_CY] :
	      (branch_op == `OR1200_BRANCHOP_RFE) ? 
	      (`SP_IIE_ADDR_COMPARE) ? sp_esr_ghost[`OR1200_SR_CY] : esr[`OR1200_SR_CY] :
	      cy_we ? cyforw :
	      (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
	      sr[`OR1200_SR_CY];
   assign to_sr[`OR1200_SR_F] 
	    = (except_started) ? sr[`OR1200_SR_F] :
	      (branch_op == `OR1200_BRANCHOP_RFE) ? 
	      (`SP_IIE_ADDR_COMPARE) ? sp_esr_ghost[`OR1200_SR_F] : esr[`OR1200_SR_F] :
	      flag_we ? flagforw :
	      (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
	      sr[`OR1200_SR_F];
   
   assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] 
	    = (except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00, 
				  sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
	      (branch_op == `OR1200_BRANCHOP_RFE) ? 
	      (`SP_IIE_ADDR_COMPARE) ? sp_esr_ghost[`OR1200_SR_CE:`OR1200_SR_SM] : esr[`OR1200_SR_CE:`OR1200_SR_SM] : (spr_we && sr_sel) ? 
	      spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM] :
	      sr[`OR1200_SR_CE:`OR1200_SR_SM];




   assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		      (spr_addr[10:4] == `OR1200_SPR_CFGR));
   assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		    (spr_addr[10:5] == `OR1200_SPR_RF));
   assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		     (spr_addr[10:0] == `OR1200_SPR_NPC));
   assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		     (spr_addr[10:0] == `OR1200_SPR_PPC));
   assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		    (spr_addr[10:0] == `OR1200_SPR_SR));
   assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		      (spr_addr[10:0] == `OR1200_SPR_EPCR));
   assign sp_epcr_ghost_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		      (spr_addr[10:0] == (`OR1200_SPR_EPCR + 1)));
   assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		      (spr_addr[10:0] == `OR1200_SPR_EEAR));
   assign sp_eear_ghost_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		      (spr_addr[10:0] == (`OR1200_SPR_EEAR+1)));
   assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		     (spr_addr[10:0] == `OR1200_SPR_ESR));
   assign sp_esr_ghost_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		     (spr_addr[10:0] == (`OR1200_SPR_ESR+1)));
   assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && 
		       (spr_addr[10:0] == `OR1200_SPR_FPCSR));
   assign sp_reg0_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR0));
   assign sp_reg4_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR4));
   assign sp_reg1_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR1));
   assign sp_reg2_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR2));
   assign sp_reg3_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR3));
   assign sp_reg5_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR5));
   assign sp_reg6_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR6));
   assign sp_reg7_sel = (spr_cs[`OR1200_SPR_GROUP_PC] &&
			   (spr_addr[10:0] == `OR1200_PC_PCCR7));
   



   assign sr_we = (spr_we && sr_sel) | (~except_illegal & ~sp_assertion_violated & ~ex_void & (branch_op == `OR1200_BRANCHOP_RFE)) | flag_we | cy_we | ov_we;
   assign pc_we = (du_write && (npc_sel | ppc_sel));
   assign epcr_we = (spr_we && epcr_sel);
   assign eear_we = (spr_we && eear_sel);
   assign esr_we = (spr_we && esr_sel);
   assign fpcsr_we = (spr_we && fpcsr_sel);
   assign sp_epcr_ghost_we = (spr_we && sp_epcr_ghost_sel);
   assign sp_eear_ghost_we = (spr_we && sp_eear_ghost_sel);
   assign sp_esr_ghost_we = (spr_we && sp_esr_ghost_sel);
   assign sp_reg0_we = spr_we & sp_reg0_sel;
   assign sp_reg4_we = spr_we & sp_reg4_sel;
   assign sp_reg1_we = spr_we & sp_reg1_sel;
   assign sp_reg2_we = spr_we & sp_reg2_sel;
   assign sp_reg3_we = spr_we & sp_reg3_sel;
   assign sp_reg6_we = spr_we & sp_reg6_sel;

   



   assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
		     (sp_esr_ghost & {32{sp_esr_ghost_sel}}) |
		     (sp_epcr_ghost & {32{sp_epcr_ghost_sel}}) |
		     (sp_eear_ghost & {32{sp_eear_ghost_sel}}) |
		     (sp_reg0 & {32{sp_reg0_sel}}) |
		     (sp_reg4 & {32{sp_reg4_sel}}) |
		     (sp_reg1 & {32{sp_reg1_sel}}) |
		     (sp_reg2 & {32{sp_reg2_sel}}) |
		     (sp_reg3 & {32{sp_reg3_sel}}) |
		     (sp_assertions_violated & {32{sp_reg5_sel}}) |
		     (sp_reg6 & {32{sp_reg6_sel}}) |
		     (sp_reg7 & {32{sp_reg7_sel}}) |
		     (spr_dat_rf & {32{rf_sel}}) |
		     (spr_dat_npc & {32{npc_sel}}) |
		     (spr_dat_ppc & {32{ppc_sel}}) |
		     ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
		     (epcr & {32{epcr_sel}}) |
		     (eear & {32{eear_sel}}) |
		     ({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} & 
		      {32{fpcsr_sel}}) |
		     ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});




   assign flag = sr[`OR1200_SR_F];




   assign carry = sr[`OR1200_SR_CY];


   always @(posedge clk or `OR1200_RST_EVENT rst) begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg7 <= 0;
      else if(sp_assertion_violated)
	sp_reg7 <= spr_dat_ppc;
   end


   always @(posedge clk or `OR1200_RST_EVENT rst) begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg0 <= 0;
      else if(sp_reg0_we == 1'b1)
	sp_reg0 <= spr_dat_o;
   end


   always@(posedge clk or `OR1200_RST_EVENT rst)begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg4 <= 0;
      else if(sp_reg4_we == 1'b1)
	sp_reg4 <= spr_dat_o;
   end


   always@(posedge clk or `OR1200_RST_EVENT rst)begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg1 <= 32'd2000;
      else if(sp_reg1_we == 1'b1)
	sp_reg1 <= spr_dat_o;
   end


   always@(posedge clk or `OR1200_RST_EVENT rst)begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg2 <= 0;
      else if(sp_reg2_we == 1'b1)
	sp_reg2 <= spr_dat_o;
   end


   always@(posedge clk or `OR1200_RST_EVENT rst)begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg3 <= 0;
      else if(sp_reg3_we == 1'b1)
	sp_reg3 <= spr_dat_o;   
   end


   always@(posedge clk or `OR1200_RST_EVENT rst)begin
      if(rst == `OR1200_RST_VALUE)
	sp_reg6 <= 0;
      else if(sp_reg6_we == 1'b1)
	sp_reg6 <= spr_dat_o;   
   end
      



   always @(posedge clk or `OR1200_RST_EVENT rst)
     if (rst == `OR1200_RST_VALUE)
       sr_reg <=  {2'b01,
		   `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
     else if (except_started)
       sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
     else if (sr_we)
       sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
   

   always @(posedge clk or `OR1200_RST_EVENT rst)

     if (rst == `OR1200_RST_VALUE) begin
	sr_reg_bit_eph <=  `OR1200_SR_EPH_DEF;

	sr_reg_bit_eph_select <=  1'b1;	
     end


     else if (sr_reg_bit_eph_select) begin

	sr_reg_bit_eph <=  boot_adr_sel_i;
	sr_reg_bit_eph_select <=  1'b0;
     end
     else if (sr_we) begin
	sr_reg_bit_eph <=  to_sr[`OR1200_SR_EPH];
     end


   assign	sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ? 
				       boot_adr_sel_i : sr_reg_bit_eph;


   always @(sr_reg or sr_reg_bit_eph_muxed or sp_reg3)
     sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed,
	   sr_reg[`OR1200_SR_WIDTH-4:0]};

`ifdef verilator




   function [31:0] get_sr;

      get_sr = {{32-`OR1200_SR_WIDTH{1'b0}},sr};
   endfunction

   function [31:0] get_epcr;

      get_epcr = epcr;
   endfunction

   function [31:0] get_eear;

      get_eear = eear;
   endfunction

   function [31:0] get_esr;

      get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
   endfunction

`endif
   



   always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
	    spr_dat_fpu or
	    spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
      casez (spr_addr[`OR1200_SPR_GROUP_BITS])
	`OR1200_SPR_GROUP_PC:
	  to_wbmux = sys_data;
	`OR1200_SPR_GROUP_SYS:
	  to_wbmux = sys_data;
	`OR1200_SPR_GROUP_TT:
	  to_wbmux = spr_dat_tt;
	`OR1200_SPR_GROUP_PIC:
	  to_wbmux = spr_dat_pic;
	`OR1200_SPR_GROUP_PM:
	  to_wbmux = spr_dat_pm;
	`OR1200_SPR_GROUP_DMMU:
	  to_wbmux = spr_dat_dmmu;
	`OR1200_SPR_GROUP_IMMU:
	  to_wbmux = spr_dat_immu;
	`OR1200_SPR_GROUP_MAC:
	  to_wbmux = spr_dat_mac;
	`OR1200_SPR_GROUP_FPU:
	  to_wbmux = spr_dat_fpu;
	default:
	  to_wbmux = spr_dat_du;
      endcase
   end

endmodule