data/full_repos/permissive/219428126/full_adder.v
 line:59 column:2: Illegal character '\x00'
1: b"%Error: data/full_repos/permissive/219428126/full_adder.v:42: Cannot find file containing module: 'half_adder'\nhalf_adder b2v_inst(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219428126,data/full_repos/permissive/219428126/half_adder\n             data/full_repos/permissive/219428126,data/full_repos/permissive/219428126/half_adder.v\n             data/full_repos/permissive/219428126,data/full_repos/permissive/219428126/half_adder.sv\n             half_adder\n             half_adder.v\n             half_adder.sv\n             obj_dir/half_adder\n             obj_dir/half_adder.v\n             obj_dir/half_adder.sv\n%Error: data/full_repos/permissive/219428126/full_adder.v:49: Cannot find file containing module: 'half_adder'\nhalf_adder b2v_inst2(\n^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module full_adder(
	A,
	B,
	X,
	S,
	C
);


input wire	A;
input wire	B;
input wire	X;
output wire	S;
output wire	C;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;





half_adder	b2v_inst(
	.A(A),
	.B(B),
	.S(SYNTHESIZED_WIRE_0),
	.C(SYNTHESIZED_WIRE_2));


half_adder	b2v_inst2(
	.A(SYNTHESIZED_WIRE_0),
	.B(X),
	.S(S),
	.C(SYNTHESIZED_WIRE_1));

assign	C = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;


endmodule
module full_adder(
	A,
	B,
	X,
	S,
	C
);



input wire	A;
input wire	B;
input wire	X;
output wire	S;
output wire	C;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;





half_adder	b2v_inst(
	.A(A),
	.B(B),
	.S(SYNTHESIZED_WIRE_0),
	.C(SYNTHESIZED_WIRE_2));


half_adder	b2v_inst2(
	.A(SYNTHESIZED_WIRE_0),
	.B(X),
	.S(S),
	.C(SYNTHESIZED_WIRE_1));

assign	C = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;


endmodule