data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:2: Cannot find include file: xcfi_macros.sv\n`include "xcfi_macros.sv" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201267735/verif/rvfi/models,data/full_repos/permissive/201267735/xcfi_macros.sv\n             data/full_repos/permissive/201267735/verif/rvfi/models,data/full_repos/permissive/201267735/xcfi_macros.sv.v\n             data/full_repos/permissive/201267735/verif/rvfi/models,data/full_repos/permissive/201267735/xcfi_macros.sv.sv\n             xcfi_macros.sv\n             xcfi_macros.sv.v\n             xcfi_macros.sv.sv\n             obj_dir/xcfi_macros.sv\n             obj_dir/xcfi_macros.sv.v\n             obj_dir/xcfi_macros.sv.sv\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:6: Define or directive not defined: \'`XCFI_TRACE_INPUTS\'\n    `XCFI_TRACE_INPUTS,\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:6: syntax error, unexpected \',\', expecting \'[\'\n    `XCFI_TRACE_INPUTS,\n                      ^\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:8: Define or directive not defined: \'`XCFI_SPEC_OUTPUTS\'\n    `XCFI_SPEC_OUTPUTS\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:12: Define or directive not defined: \'`XCFI_INSN_CHECK_COMMON\'\n`XCFI_INSN_CHECK_COMMON\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:14: Define or directive not defined: \'`RS1\'\nwire [31:0] addr_byte = (`RS1 + (`RS2 << 1));\n                         ^~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:14: Define or directive not defined: \'`RS2\'\nwire [31:0] addr_byte = (`RS1 + (`RS2 << 1));\n                                 ^~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:14: syntax error, unexpected <<, expecting TYPE-IDENTIFIER\nwire [31:0] addr_byte = (`RS1 + (`RS2 << 1));\n                                      ^~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:17: syntax error, unexpected assign\nassign spec_valid       = rvfi_valid && dec_xc_str_h;\n^~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:19: Define or directive not defined: \'`FIELD_RS1_ADDR\'\nassign spec_rs1_addr    = `FIELD_RS1_ADDR;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:20: Define or directive not defined: \'`FIELD_RS2_ADDR\'\nassign spec_rs2_addr    = `FIELD_RS2_ADDR;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:21: Define or directive not defined: \'`FIELD_RS3_ADDR\'\nassign spec_rs3_addr    = `FIELD_RS3_ADDR;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_str_h.v:35: Define or directive not defined: \'`RS3\'\nassign spec_mem_wdata   = `RS3[15:0] << (16*addr_byte[1]);\n                          ^~~~\n%Error: Exiting due to 13 error(s)\n'
module xcfi_insn_spec (

    `XCFI_TRACE_INPUTS,

    `XCFI_SPEC_OUTPUTS

);

`XCFI_INSN_CHECK_COMMON

wire [31:0] addr_byte = (`RS1 + (`RS2 << 1));
wire [31:0] addr_word = addr_byte & 32'hFFFF_FFFC;

assign spec_valid       = rvfi_valid && dec_xc_str_h;
assign spec_trap        = addr_byte[0];
assign spec_rs1_addr    = `FIELD_RS1_ADDR;
assign spec_rs2_addr    = `FIELD_RS2_ADDR;
assign spec_rs3_addr    = `FIELD_RS3_ADDR;
assign spec_rd_addr     = 0;
assign spec_rd_wdata    = 0;
assign spec_rd_wide     = 1'b0;
assign spec_rd_wdatahi  = 32'b0;
assign spec_pc_wdata    = rvfi_pc_rdata + 4;
assign spec_mem_addr    = addr_word;
assign spec_mem_rmask   = 0;

assign spec_mem_wmask   = {
    {2{ addr_byte[1]}},
    {2{!addr_byte[1]}}
};

assign spec_mem_wdata   = `RS3[15:0] << (16*addr_byte[1]);

endmodule
module xcfi_insn_spec (

    `XCFI_TRACE_INPUTS,

    `XCFI_SPEC_OUTPUTS

);


`XCFI_INSN_CHECK_COMMON

wire [31:0] addr_byte = (`RS1 + (`RS2 << 1));
wire [31:0] addr_word = addr_byte & 32'hFFFF_FFFC;

assign spec_valid       = rvfi_valid && dec_xc_str_h;
assign spec_trap        = addr_byte[0];
assign spec_rs1_addr    = `FIELD_RS1_ADDR;
assign spec_rs2_addr    = `FIELD_RS2_ADDR;
assign spec_rs3_addr    = `FIELD_RS3_ADDR;
assign spec_rd_addr     = 0;
assign spec_rd_wdata    = 0;
assign spec_rd_wide     = 1'b0;
assign spec_rd_wdatahi  = 32'b0;
assign spec_pc_wdata    = rvfi_pc_rdata + 4;
assign spec_mem_addr    = addr_word;
assign spec_mem_rmask   = 0;

assign spec_mem_wmask   = {
    {2{ addr_byte[1]}},
    {2{!addr_byte[1]}}
};

assign spec_mem_wdata   = `RS3[15:0] << (16*addr_byte[1]);

endmodule