data/full_repos/permissive/175780824/1_VerilogSourceCode/1_CPUCore_src/NPC_Generator.v
data/verilator_xmls/8292b0f1-724f-4d94-a7b4-0ff892c4f2bc.xml
module NPC_Generator(
    input wire [31:0] PCF,JalrTarget, BranchTarget, JalTarget,
    input wire BranchE,JalD,JalrE,
    output reg [31:0] PC_In
    );
endmodule
module NPC_Generator(
    input wire [31:0] PCF,JalrTarget, BranchTarget, JalTarget,
    input wire BranchE,JalD,JalrE,
    output reg [31:0] PC_In
    );

endmodule