data/full_repos/permissive/133571498/dance/mem.v
data/verilator_xmls/e1dc5bc2-59ef-4610-bb0d-48194b1db330.xml
module mem (
    input clock,
    input [3:0] addr,
    output reg [4:0] num
);

    reg [4:0] memory [0:8];

    initial begin
        $readmemb("prog.hex", memory);
    end

    always @(posedge clock) begin
        num <= memory[addr];
    end

endmodule
module mem (
    input clock,
    input [3:0] addr,
    output reg [4:0] num
);


    reg [4:0] memory [0:8];

    initial begin
        $readmemb("prog.hex", memory);
    end

    always @(posedge clock) begin
        num <= memory[addr];
    end

endmodule