data/full_repos/permissive/185628295/hdl/stream_filter_tb.v
 line:327: before: "signed"
1: b'%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:18: Cannot find include file: stream_filter.v\n`include "stream_filter.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/185628295/hdl,data/full_repos/permissive/185628295/stream_filter.v\n             data/full_repos/permissive/185628295/hdl,data/full_repos/permissive/185628295/stream_filter.v.v\n             data/full_repos/permissive/185628295/hdl,data/full_repos/permissive/185628295/stream_filter.v.sv\n             stream_filter.v\n             stream_filter.v.v\n             stream_filter.v.sv\n             obj_dir/stream_filter.v\n             obj_dir/stream_filter.v.v\n             obj_dir/stream_filter.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:31: Unsupported: event data types\n    event end_trigger;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    initial #1 display_header();\n            ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:207: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:215: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:242: syntax error, unexpected \'@\'\n        repeat(6) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:244: syntax error, unexpected \'@\'\n        repeat(6) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:246: syntax error, unexpected \'@\'\n        repeat(5) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:256: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:261: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:267: syntax error, unexpected \'@\'\n            @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:273: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:280: syntax error, unexpected \'@\'\n        repeat(10) @(negedge clk);\n                   ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:285: syntax error, unexpected \'@\'\n            @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:290: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:294: syntax error, unexpected \'@\'\n        repeat(30) @(negedge clk);\n                   ^\n%Error: data/full_repos/permissive/185628295/hdl/stream_filter_tb.v:300: syntax error, unexpected ->\n        -> end_trigger;\n        ^~\n%Error: Exiting due to 16 error(s), 2 warning(s)\n'
module stream_filter_tb;




    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam
        CFG_WIDTH   = 1,
        CFG_KERNEL  = 2,
        CFG_RESCALE = 3;


    localparam CFG_DWIDTH   = 32;
    localparam CFG_AWIDTH   = 5;

    localparam MEM_AWIDTH   = 8;
    localparam MEM_DEPTH    = 128;

    localparam IMG_WIDTH    = 16;
    localparam KER_WIDTH    = 16;

    localparam IMG_POINT    = 8;
    localparam KER_POINT    = 12;



    function real ker_f2r;
        input signed [KER_WIDTH-1:0] value;

        begin
            ker_f2r = value / ((1<<KER_POINT) * 1.0);
        end
    endfunction


    function signed [KER_WIDTH-1:0] ker_r2f;
        input real value;

        begin
            ker_r2f = value * (1<<KER_POINT);
        end
    endfunction


    function real img_f2r;
        input signed [IMG_WIDTH-1:0] value;

        begin
            img_f2r = value / ((1<<IMG_POINT) * 1.0);
        end
    endfunction


    function signed [IMG_WIDTH-1:0] img_r2f;
        input real value;

        begin
            img_r2f = value * (1<<IMG_POINT);
        end
    endfunction


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'stream_filter'");
    end
`endif



    reg                     rst;

    reg  [7:0]              shift;
    reg  [7:0]              head;

    reg  [CFG_DWIDTH-1:0]   cfg_data;
    reg  [CFG_AWIDTH-1:0]   cfg_addr;
    reg                     cfg_valid;

    reg  [IMG_WIDTH-1:0]    image;
    reg                     image_val;

    wire [IMG_WIDTH-1:0]    result;
    wire                    result_val;




    stream_filter #(
        .CFG_DWIDTH (CFG_DWIDTH),
        .CFG_AWIDTH (CFG_AWIDTH),

        .MEM_AWIDTH (MEM_AWIDTH),
        .MEM_DEPTH  (MEM_DEPTH),

        .IMG_WIDTH  (IMG_WIDTH),
        .KER_WIDTH  (KER_WIDTH))
    uut (
        .clk        (clk),
        .rst        (rst),

        .cfg_data   (cfg_data),
        .cfg_addr   (cfg_addr),
        .cfg_valid  (cfg_valid),

        .image      (image),
        .image_val  (image_val),

        .result     (result),
        .result_val (result_val)
    );




    task display_signals;
        $display(
            "%d %d",
            $time, rst,

            "\tcfg %x %b",
            cfg_data,
            cfg_valid,

            "\timg: %x %12f %b",
            image,
            img_f2r(image),
            image_val,

            "\tres: %12f %b",
            img_f2r(result),
            result_val,






















        );

    endtask

    task display_header;
        $display(
            "\t\ttime\trst",

        );
    endtask




    initial begin

        rst = 0;

        shift       = KER_POINT;
        head        = IMG_WIDTH+KER_POINT-1;

        cfg_data    = 'b0;
        cfg_addr    = 'b0;
        cfg_valid   = 1'b0;

        image       = 'b0;
        image_val   = 1'b0;


`ifdef TB_VERBOSE
    $display("RESET");
`endif

        repeat(6) @(negedge clk);
        rst <= 1'b1;
        repeat(6) @(negedge clk);
        rst <= 1'b0;
        repeat(5) @(negedge clk);

`ifdef TB_VERBOSE
    $display("send config");
`endif


        cfg_data    <= {8'd0, 8'd0, shift, head};
        cfg_addr    <= CFG_RESCALE;
        cfg_valid   <= 1'b1;
        @(negedge clk);

        cfg_data    <= 32'd10;
        cfg_addr    <= CFG_WIDTH;
        cfg_valid   <= 1'b1;
        @(negedge clk);

        repeat(30) begin
            cfg_data    <= ker_r2f(0.5);
            cfg_addr    <= CFG_KERNEL;
            cfg_valid   <= 1'b1;
            @(negedge clk);
        end

        cfg_data    <= 'b0;
        cfg_addr    <= 'b0;
        cfg_valid   <= 1'b0;
        @(negedge clk);


`ifdef TB_VERBOSE
    $display("send data");
`endif

        repeat(10) @(negedge clk);

        repeat(30) begin
            image       <= img_r2f(img_f2r(image) + 16'd1);
            image_val   <= 1'b1;
            @(negedge clk);
        end

        image       <= 'b0;
        image_val   <= 1'b0;
        @(negedge clk);



        repeat(30) @(negedge clk);


`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule
module stream_filter_tb;





    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam
        CFG_WIDTH   = 1,
        CFG_KERNEL  = 2,
        CFG_RESCALE = 3;


    localparam CFG_DWIDTH   = 32;
    localparam CFG_AWIDTH   = 5;

    localparam MEM_AWIDTH   = 8;
    localparam MEM_DEPTH    = 128;

    localparam IMG_WIDTH    = 16;
    localparam KER_WIDTH    = 16;

    localparam IMG_POINT    = 8;
    localparam KER_POINT    = 12;



    function real ker_f2r;
        input signed [KER_WIDTH-1:0] value;

        begin
            ker_f2r = value / ((1<<KER_POINT) * 1.0);
        end
    endfunction


    function signed [KER_WIDTH-1:0] ker_r2f;
        input real value;

        begin
            ker_r2f = value * (1<<KER_POINT);
        end
    endfunction


    function real img_f2r;
        input signed [IMG_WIDTH-1:0] value;

        begin
            img_f2r = value / ((1<<IMG_POINT) * 1.0);
        end
    endfunction


    function signed [IMG_WIDTH-1:0] img_r2f;
        input real value;

        begin
            img_r2f = value * (1<<IMG_POINT);
        end
    endfunction


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'stream_filter'");
    end
`endif



    reg                     rst;

    reg  [7:0]              shift;
    reg  [7:0]              head;

    reg  [CFG_DWIDTH-1:0]   cfg_data;
    reg  [CFG_AWIDTH-1:0]   cfg_addr;
    reg                     cfg_valid;

    reg  [IMG_WIDTH-1:0]    image;
    reg                     image_val;

    wire [IMG_WIDTH-1:0]    result;
    wire                    result_val;




    stream_filter #(
        .CFG_DWIDTH (CFG_DWIDTH),
        .CFG_AWIDTH (CFG_AWIDTH),

        .MEM_AWIDTH (MEM_AWIDTH),
        .MEM_DEPTH  (MEM_DEPTH),

        .IMG_WIDTH  (IMG_WIDTH),
        .KER_WIDTH  (KER_WIDTH))
    uut (
        .clk        (clk),
        .rst        (rst),

        .cfg_data   (cfg_data),
        .cfg_addr   (cfg_addr),
        .cfg_valid  (cfg_valid),

        .image      (image),
        .image_val  (image_val),

        .result     (result),
        .result_val (result_val)
    );




    task display_signals;
        $display(
            "%d %d",
            $time, rst,

            "\tcfg %x %b",
            cfg_data,
            cfg_valid,

            "\timg: %x %12f %b",
            image,
            img_f2r(image),
            image_val,

            "\tres: %12f %b",
            img_f2r(result),
            result_val,






















        );

    endtask

    task display_header;
        $display(
            "\t\ttime\trst",

        );
    endtask




    initial begin

        rst = 0;

        shift       = KER_POINT;
        head        = IMG_WIDTH+KER_POINT-1;

        cfg_data    = 'b0;
        cfg_addr    = 'b0;
        cfg_valid   = 1'b0;

        image       = 'b0;
        image_val   = 1'b0;


`ifdef TB_VERBOSE
    $display("RESET");
`endif

        repeat(6) @(negedge clk);
        rst <= 1'b1;
        repeat(6) @(negedge clk);
        rst <= 1'b0;
        repeat(5) @(negedge clk);

`ifdef TB_VERBOSE
    $display("send config");
`endif


        cfg_data    <= {8'd0, 8'd0, shift, head};
        cfg_addr    <= CFG_RESCALE;
        cfg_valid   <= 1'b1;
        @(negedge clk);

        cfg_data    <= 32'd10;
        cfg_addr    <= CFG_WIDTH;
        cfg_valid   <= 1'b1;
        @(negedge clk);

        repeat(30) begin
            cfg_data    <= ker_r2f(0.5);
            cfg_addr    <= CFG_KERNEL;
            cfg_valid   <= 1'b1;
            @(negedge clk);
        end

        cfg_data    <= 'b0;
        cfg_addr    <= 'b0;
        cfg_valid   <= 1'b0;
        @(negedge clk);


`ifdef TB_VERBOSE
    $display("send data");
`endif

        repeat(10) @(negedge clk);

        repeat(30) begin
            image       <= img_r2f(img_f2r(image) + 16'd1);
            image_val   <= 1'b1;
            @(negedge clk);
        end

        image       <= 'b0;
        image_val   <= 1'b0;
        @(negedge clk);



        repeat(30) @(negedge clk);


`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule