data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v:1: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.sv\n             cmos_cells.v\n             cmos_cells.v.v\n             cmos_cells.v.sv\n             obj_dir/cmos_cells.v\n             obj_dir/cmos_cells.v.v\n             obj_dir/cmos_cells.v.sv\n%Error: Exiting due to 1 error(s)\n'
module p2s_synth(IN_CLK_p2s, IN_LANE3_p2s, IN_LANE2_p2s, IN_LANE1_p2s, IN_LANE0_p2s, IN_CTR_p2s, IN_ENB_p2s, IN_RESET_p2s, IN_VALID_BS, OUT_LANE_p2s);
  input IN_CLK_p2s;
  input [2:0] IN_CTR_p2s;
  input IN_ENB_p2s;
  input [7:0] IN_LANE0_p2s;
  input [7:0] IN_LANE1_p2s;
  input [7:0] IN_LANE2_p2s;
  input [7:0] IN_LANE3_p2s;
  input IN_RESET_p2s;
  input IN_VALID_BS;
  output [3:0] OUT_LANE_p2s;
  wire [7:0] Q0_p2s;
  wire [7:0] Q1_p2s;
  wire [7:0] Q2_p2s;
  wire [7:0] Q3_p2s;
  wire valid_ffd;
  ffd_p2s_synth \ffd_lane0[0]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[0]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[0]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[1]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[1]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[1]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[2]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[2]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[2]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[3]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[3]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[3]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[4]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[4]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[4]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[5]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[5]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[5]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[6]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[6]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[6]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[7]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[7]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[7]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[0]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[0]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[0]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[1]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[1]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[1]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[2]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[2]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[2]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[3]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[3]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[3]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[4]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[4]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[4]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[5]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[5]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[5]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[6]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[6]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[6]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[7]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[7]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[7]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[0]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[0]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[0]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[1]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[1]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[1]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[2]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[2]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[2]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[3]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[3]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[3]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[4]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[4]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[4]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[5]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[5]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[5]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[6]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[6]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[6]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[7]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[7]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[7]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[0]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[0]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[0]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[1]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[1]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[1]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[2]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[2]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[2]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[3]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[3]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[3]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[4]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[4]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[4]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[5]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[5]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[5]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[6]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[6]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[6]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth ffd_valid (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[7]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[7]),
    .valid_in(IN_VALID_BS),
    .valid_out(valid_ffd)
  );
  mux_p2s_synth mux_lane0 (
    .data_in(Q0_p2s),
    .data_out(OUT_LANE_p2s[0]),
    .sel(IN_CTR_p2s)
  );
  mux_p2s_synth mux_lane1 (
    .data_in(Q1_p2s),
    .data_out(OUT_LANE_p2s[1]),
    .sel(IN_CTR_p2s)
  );
  mux_p2s_synth mux_lane2 (
    .data_in(Q2_p2s),
    .data_out(OUT_LANE_p2s[2]),
    .sel(IN_CTR_p2s)
  );
  mux_p2s_synth mux_lane3 (
    .data_in(Q3_p2s),
    .data_out(OUT_LANE_p2s[3]),
    .sel(IN_CTR_p2s)
  );
endmodule
module p2s_synth(IN_CLK_p2s, IN_LANE3_p2s, IN_LANE2_p2s, IN_LANE1_p2s, IN_LANE0_p2s, IN_CTR_p2s, IN_ENB_p2s, IN_RESET_p2s, IN_VALID_BS, OUT_LANE_p2s);

  input IN_CLK_p2s;
  input [2:0] IN_CTR_p2s;
  input IN_ENB_p2s;
  input [7:0] IN_LANE0_p2s;
  input [7:0] IN_LANE1_p2s;
  input [7:0] IN_LANE2_p2s;
  input [7:0] IN_LANE3_p2s;
  input IN_RESET_p2s;
  input IN_VALID_BS;
  output [3:0] OUT_LANE_p2s;
  wire [7:0] Q0_p2s;
  wire [7:0] Q1_p2s;
  wire [7:0] Q2_p2s;
  wire [7:0] Q3_p2s;
  wire valid_ffd;
  ffd_p2s_synth \ffd_lane0[0]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[0]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[0]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[1]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[1]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[1]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[2]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[2]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[2]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[3]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[3]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[3]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[4]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[4]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[4]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[5]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[5]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[5]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[6]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[6]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[6]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane0[7]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE0_p2s[7]),
    .ENB(IN_ENB_p2s),
    .Q(Q0_p2s[7]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[0]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[0]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[0]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[1]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[1]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[1]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[2]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[2]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[2]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[3]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[3]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[3]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[4]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[4]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[4]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[5]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[5]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[5]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[6]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[6]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[6]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane1[7]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE1_p2s[7]),
    .ENB(IN_ENB_p2s),
    .Q(Q1_p2s[7]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[0]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[0]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[0]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[1]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[1]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[1]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[2]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[2]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[2]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[3]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[3]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[3]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[4]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[4]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[4]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[5]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[5]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[5]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[6]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[6]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[6]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane2[7]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE2_p2s[7]),
    .ENB(IN_ENB_p2s),
    .Q(Q2_p2s[7]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[0]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[0]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[0]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[1]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[1]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[1]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[2]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[2]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[2]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[3]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[3]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[3]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[4]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[4]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[4]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[5]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[5]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[5]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth \ffd_lane3[6]  (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[6]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[6]),
    .valid_in(valid_ffd)
  );
  ffd_p2s_synth ffd_valid (
    .CLK(IN_CLK_p2s),
    .D(IN_LANE3_p2s[7]),
    .ENB(IN_ENB_p2s),
    .Q(Q3_p2s[7]),
    .valid_in(IN_VALID_BS),
    .valid_out(valid_ffd)
  );
  mux_p2s_synth mux_lane0 (
    .data_in(Q0_p2s),
    .data_out(OUT_LANE_p2s[0]),
    .sel(IN_CTR_p2s)
  );
  mux_p2s_synth mux_lane1 (
    .data_in(Q1_p2s),
    .data_out(OUT_LANE_p2s[1]),
    .sel(IN_CTR_p2s)
  );
  mux_p2s_synth mux_lane2 (
    .data_in(Q2_p2s),
    .data_out(OUT_LANE_p2s[2]),
    .sel(IN_CTR_p2s)
  );
  mux_p2s_synth mux_lane3 (
    .data_in(Q3_p2s),
    .data_out(OUT_LANE_p2s[3]),
    .sel(IN_CTR_p2s)
  );
endmodule