data/full_repos/permissive/157494568/Part3/clock_1hz.v
data/verilator_xmls/ca57d7f8-3bcf-4e0a-95fc-bc7827367041.xml
module clock_1hz(clk, out);

input clk;
output out;


reg [25:0] count_reg = 0;
reg out_1hz = 0;

always @(posedge clk) begin
    
	 if (count_reg < 25000000) begin
        count_reg <= count_reg + 1;
    end else begin
        count_reg <= 0;
        out_1hz <= ~out_1hz;
    end
end

assign out = out_1hz;

endmodule
module clock_1hz(clk, out);


input clk;
output out;


reg [25:0] count_reg = 0;
reg out_1hz = 0;

always @(posedge clk) begin
    
	 if (count_reg < 25000000) begin
        count_reg <= count_reg + 1;
    end else begin
        count_reg <= 0;
        out_1hz <= ~out_1hz;
    end
end

assign out = out_1hz;

endmodule