data/full_repos/permissive/115837888/source-7400/74283.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/115837888/source-7400/74283.v:18: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'C_in\' generates 1 bits.\n                                                                           : ... In instance ttl_74283\n  {C_computed, Sum_computed} = {1\'b0, A} + {1\'b0, B} + C_in;\n                                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ttl_74283 #(parameter WIDTH = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
  input [WIDTH-1:0] A,
  input [WIDTH-1:0] B,
  input C_in,
  output [WIDTH-1:0] Sum,
  output C_out
);


reg [WIDTH-1:0] Sum_computed;
reg C_computed;

always @(*)
begin
  {C_computed, Sum_computed} = {1'b0, A} + {1'b0, B} + C_in;
end


assign #(DELAY_RISE, DELAY_FALL) Sum = Sum_computed;
assign #(DELAY_RISE, DELAY_FALL) C_out = C_computed;

endmodule
module ttl_74283 #(parameter WIDTH = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
  input [WIDTH-1:0] A,
  input [WIDTH-1:0] B,
  input C_in,
  output [WIDTH-1:0] Sum,
  output C_out
);



reg [WIDTH-1:0] Sum_computed;
reg C_computed;

always @(*)
begin
  {C_computed, Sum_computed} = {1'b0, A} + {1'b0, B} + C_in;
end


assign #(DELAY_RISE, DELAY_FALL) Sum = Sum_computed;
assign #(DELAY_RISE, DELAY_FALL) C_out = C_computed;

endmodule