data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/ALUmodule.v
1: b"%Error: data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/ALUmodule.v:59: Cannot find file containing module: 'ALU'\nALU u_ALU(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/ALU\n             data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/ALU.v\n             data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips,data/full_repos/permissive/115487336/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s)\n"
module ALUmodule(
	input clk,
	input rst_n,
	
	input [31:0] rego1,
	input [31:0] PC,
	input ALUSrcA,
	
	input [31:0] rego2,
	input [15:0] imm,
	input [1:0] ALUSrcB,
	
	input [4:0] alu_op,
	
	input ALURegWe,
	output [31:0] alu_out,
	output reg [31:0] alu_lock_next,
	output flag

);

wire [31:0] alu_a;
assign alu_a= ALUSrcA ? rego1 : PC;

wire [31:0] SignExtend;
assign SignExtend[15:0]=imm;
assign SignExtend[31:16]= imm[15]==1 ? 16'hFFFF : 16'h0;


wire [31:0] alu_b;


assign alu_b= ALUSrcB==2'h0 ? rego2 : (
	ALUSrcB==2'h2 ? SignExtend : (
	ALUSrcB==2'h3 ? SignExtend << 2 : 32'h4
));


ALU u_ALU(
	alu_a,
	alu_b,
	alu_op,
	alu_out,
	flag
);


reg [31:0] alu_lock_now;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		alu_lock_now<=32'hCCCC_CCCC;
	end
	else
	begin
		alu_lock_now<=alu_lock_next;
	end
end

always@(*)
begin
	if(ALURegWe)
		alu_lock_next=alu_out;
	else
		alu_lock_next=alu_lock_now;
end
endmodule
module ALUmodule(
	input clk,
	input rst_n,
	
	input [31:0] rego1,
	input [31:0] PC,
	input ALUSrcA,
	
	input [31:0] rego2,
	input [15:0] imm,
	input [1:0] ALUSrcB,
	
	input [4:0] alu_op,
	
	input ALURegWe,
	output [31:0] alu_out,
	output reg [31:0] alu_lock_next,
	output flag

);


wire [31:0] alu_a;
assign alu_a= ALUSrcA ? rego1 : PC;

wire [31:0] SignExtend;
assign SignExtend[15:0]=imm;
assign SignExtend[31:16]= imm[15]==1 ? 16'hFFFF : 16'h0;


wire [31:0] alu_b;


assign alu_b= ALUSrcB==2'h0 ? rego2 : (
	ALUSrcB==2'h2 ? SignExtend : (
	ALUSrcB==2'h3 ? SignExtend << 2 : 32'h4
));


ALU u_ALU(
	alu_a,
	alu_b,
	alu_op,
	alu_out,
	flag
);


reg [31:0] alu_lock_now;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		alu_lock_now<=32'hCCCC_CCCC;
	end
	else
	begin
		alu_lock_now<=alu_lock_next;
	end
end

always@(*)
begin
	if(ALURegWe)
		alu_lock_next=alu_out;
	else
		alu_lock_next=alu_lock_now;
end
endmodule