data/full_repos/permissive/208556773/src/space_vector_modulator.v
 line:40: before: "real"
1: b'%Warning-REALCVT: data/full_repos/permissive/208556773/src/space_vector_modulator.v:45: Implicit conversion of real to integer\n          phase_table[i] <= $sin(pi*i/(phase_table_end+1))*(2.0**microstep_bits-1);\n                                                          ^\n                  ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/208556773/src/space_vector_modulator.v:90: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 12 bits.\n                                                                                    : ... In instance space_vector_modulator\n      assign pwm_delay[0] = (pwm[0] >= pwm[1]) ? 0 : (pwm[1]-pwm[0])>>1;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/208556773/src/space_vector_modulator.v:91: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 12 bits.\n                                                                                    : ... In instance space_vector_modulator\n      assign pwm_delay[1] = (pwm[1] >= pwm[0]) ? 0 : (pwm[0]-pwm[1])>>1;\n                          ^\n%Error: data/full_repos/permissive/208556773/src/space_vector_modulator.v:102: Cannot find file containing module: \'pwm\'\n    pwm #(.bits(microstep_bits+current_bits),\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/208556773/src,data/full_repos/permissive/208556773/pwm\n             data/full_repos/permissive/208556773/src,data/full_repos/permissive/208556773/pwm.v\n             data/full_repos/permissive/208556773/src,data/full_repos/permissive/208556773/pwm.sv\n             pwm\n             pwm.v\n             pwm.sv\n             obj_dir/pwm\n             obj_dir/pwm.v\n             obj_dir/pwm.sv\n%Warning-SELRANGE: data/full_repos/permissive/208556773/src/space_vector_modulator.v:124: Selection index out of range: 3 outside 1:0\n                                                                                        : ... In instance space_vector_modulator\n        phase[3] <= phase_table[phase_idx];\n             ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module space_vector_modulator #(
   parameter current_bits = 4,
   parameter microstep_bits = 8,
   parameter phase_ct_bits = 8,
   parameter center_aligned = 1,
   parameter phases = 2,
   parameter microsteps = 64
) (
    input clk,
    input resetn,
    input pwm_clk,
    output [phases-1:0] vref_pwm,

    input  [current_bits-1:0] current,
    input [phase_ct_bits-1:0] phase_ct
);


  localparam can_delay = center_aligned && phases > 1;



  localparam integer phase_table_end = microsteps*2-1;


  reg [microstep_bits-1:0] phase_table [0:phase_table_end];


  localparam real pi = 3.1415926535897;
  integer i;

  initial begin
      for (i=0; i <= phase_table_end;  i=i+1) begin
          phase_table[i] <= $sin(pi*i/(phase_table_end+1))*(2.0**microstep_bits-1);
      end
  end


  reg [microstep_bits-1:0] phase [phases-1:0];


  wire [microstep_bits+current_bits-1:0] pwm [phases-1:0];

  genvar ig;
  generate
    for (ig=0; ig<phases; ig=ig+1) begin
      assign pwm[ig] = phase[ig]*current;
    end
  endgenerate












  wire [microstep_bits+current_bits-2:0] pwm_delay [phases-1:0];


  if (can_delay) begin












    if (phases == 2) begin
      assign pwm_delay[0] = (pwm[0] >= pwm[1]) ? 0 : (pwm[1]-pwm[0])>>1;
      assign pwm_delay[1] = (pwm[1] >= pwm[0]) ? 0 : (pwm[0]-pwm[1])>>1;
    end if (phases == 3) begin

      assign pwm_delay[0] = (pwm[0] >= pwm[1]) ? 0 : (pwm[1]-pwm[0])>>1;
      assign pwm_delay[1] = (pwm[1] >= pwm[0]) ? 0 : (pwm[0]-pwm[1])>>1;
    end
  end



  for (ig=0; ig<phases; ig=ig+1) begin
    pwm #(.bits(microstep_bits+current_bits),
          .delayed(can_delay)) mb (.clk(pwm_clk),
            .resetn (resetn),
            .val(pwm[ig]),
            .delay(pwm_delay[ig]),
            .pwm(vref_pwm[ig]));
  end

  localparam idx_end = phase_ct_bits - 2;
  wire [idx_end:0] phase_idx = phase_ct[idx_end:0];

  always @(posedge clk) begin
    if (resetn) begin

      if (phases == 1) begin
        phase[1] <= phase_table[phase_idx];
      end if (phases == 2) begin
        phase[0] <= phase_table[phase_idx];
        phase[1] <= phase_table[phase_idx+microsteps];
      end if (phases == 3) begin
        phase[0] <= phase_table[phase_idx+microsteps/3];
        phase[1] <= phase_table[phase_idx+microsteps*2/3];
        phase[3] <= phase_table[phase_idx];
      end
    end
  end

endmodule
module space_vector_modulator #(
   parameter current_bits = 4,
   parameter microstep_bits = 8,
   parameter phase_ct_bits = 8,
   parameter center_aligned = 1,
   parameter phases = 2,
   parameter microsteps = 64
) (
    input clk,
    input resetn,
    input pwm_clk,
    output [phases-1:0] vref_pwm,

    input  [current_bits-1:0] current,
    input [phase_ct_bits-1:0] phase_ct
);



  localparam can_delay = center_aligned && phases > 1;



  localparam integer phase_table_end = microsteps*2-1;


  reg [microstep_bits-1:0] phase_table [0:phase_table_end];


  localparam real pi = 3.1415926535897;
  integer i;

  initial begin
      for (i=0; i <= phase_table_end;  i=i+1) begin
          phase_table[i] <= $sin(pi*i/(phase_table_end+1))*(2.0**microstep_bits-1);
      end
  end


  reg [microstep_bits-1:0] phase [phases-1:0];


  wire [microstep_bits+current_bits-1:0] pwm [phases-1:0];

  genvar ig;
  generate
    for (ig=0; ig<phases; ig=ig+1) begin
      assign pwm[ig] = phase[ig]*current;
    end
  endgenerate












  wire [microstep_bits+current_bits-2:0] pwm_delay [phases-1:0];


  if (can_delay) begin












    if (phases == 2) begin
      assign pwm_delay[0] = (pwm[0] >= pwm[1]) ? 0 : (pwm[1]-pwm[0])>>1;
      assign pwm_delay[1] = (pwm[1] >= pwm[0]) ? 0 : (pwm[0]-pwm[1])>>1;
    end if (phases == 3) begin

      assign pwm_delay[0] = (pwm[0] >= pwm[1]) ? 0 : (pwm[1]-pwm[0])>>1;
      assign pwm_delay[1] = (pwm[1] >= pwm[0]) ? 0 : (pwm[0]-pwm[1])>>1;
    end
  end



  for (ig=0; ig<phases; ig=ig+1) begin
    pwm #(.bits(microstep_bits+current_bits),
          .delayed(can_delay)) mb (.clk(pwm_clk),
            .resetn (resetn),
            .val(pwm[ig]),
            .delay(pwm_delay[ig]),
            .pwm(vref_pwm[ig]));
  end

  localparam idx_end = phase_ct_bits - 2;
  wire [idx_end:0] phase_idx = phase_ct[idx_end:0];

  always @(posedge clk) begin
    if (resetn) begin

      if (phases == 1) begin
        phase[1] <= phase_table[phase_idx];
      end if (phases == 2) begin
        phase[0] <= phase_table[phase_idx];
        phase[1] <= phase_table[phase_idx+microsteps];
      end if (phases == 3) begin
        phase[0] <= phase_table[phase_idx+microsteps/3];
        phase[1] <= phase_table[phase_idx+microsteps*2/3];
        phase[3] <= phase_table[phase_idx];
      end
    end
  end

endmodule