data/full_repos/permissive/179227721/mid/tdigadder.v
1: b'%Error: data/full_repos/permissive/179227721/mid/tdigadder.v:19: Cannot find file containing module: \'bcdadder\'\n   bcdadder bad1(.num1(x21), .num2(x11), .out(y1), .cin(c0), .carry(c1));\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179227721/mid,data/full_repos/permissive/179227721/bcdadder\n             data/full_repos/permissive/179227721/mid,data/full_repos/permissive/179227721/bcdadder.v\n             data/full_repos/permissive/179227721/mid,data/full_repos/permissive/179227721/bcdadder.sv\n             bcdadder\n             bcdadder.v\n             bcdadder.sv\n             obj_dir/bcdadder\n             obj_dir/bcdadder.v\n             obj_dir/bcdadder.sv\n%Error: data/full_repos/permissive/179227721/mid/tdigadder.v:20: Cannot find file containing module: \'bcdadder\'\n   bcdadder bad2(.num1(x22), .num2(x12), .out(y2), .cin(c1), .carry(cout));\n   ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179227721/mid/tdigadder.v:22: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                       : ... In instance tdigadder\n   assign c0 = 4\'b0000;  \n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module tdigadder(

                 input [7:0]  num1,
                 input [7:0]  num2,
                 output [7:0] out,
                 output       of
                 );

   wire [3:0]           x22;
   wire [3:0]           x21;
   wire [3:0]           x12;
   wire [3:0]           x11;
   wire [3:0]           y2;
   wire [3:0]           y1;
   wire                 c0;
   wire                 c1;
   wire                 cout;

   bcdadder bad1(.num1(x21), .num2(x11), .out(y1), .cin(c0), .carry(c1));
   bcdadder bad2(.num1(x22), .num2(x12), .out(y2), .cin(c1), .carry(cout));

   assign c0 = 4'b0000;
   assign x22[3:0] = num1[7:4];
   assign x21[3:0] = num1[3:0];
   assign x12[3:0] = num2[7:4];
   assign x11[3:0] = num2[3:0];
   assign of = cout;
   assign out = {y2, y1};

`ifdef FORMAL
     assert property (num1[7:4] > 9 ||
                      num1[3:0] > 9 ||
                      num2[7:4] > 9 ||
                      num2[3:0] > 9 ||
                      of ||
                      (num1[7:4] * 10 + num1[3:0])
                      + (num2[7:4] * 10 + num2[3:0])
                      == (out[7:4] * 10 + out[3:0]));
   assert property (num1[7:4] > 9 ||
                    num1[3:0] > 9 ||
                    num2[7:4] > 9 ||
                    num2[3:0] > 9 ||
                    !of ||
                    (num1[7:4] * 10 + num1[3:0])
                    + (num2[7:4] * 10 + num2[3:0])
                    > 99);
`endif

endmodule
module tdigadder(

                 input [7:0]  num1,
                 input [7:0]  num2,
                 output [7:0] out,
                 output       of
                 );


   wire [3:0]           x22;
   wire [3:0]           x21;
   wire [3:0]           x12;
   wire [3:0]           x11;
   wire [3:0]           y2;
   wire [3:0]           y1;
   wire                 c0;
   wire                 c1;
   wire                 cout;

   bcdadder bad1(.num1(x21), .num2(x11), .out(y1), .cin(c0), .carry(c1));
   bcdadder bad2(.num1(x22), .num2(x12), .out(y2), .cin(c1), .carry(cout));

   assign c0 = 4'b0000;
   assign x22[3:0] = num1[7:4];
   assign x21[3:0] = num1[3:0];
   assign x12[3:0] = num2[7:4];
   assign x11[3:0] = num2[3:0];
   assign of = cout;
   assign out = {y2, y1};

`ifdef FORMAL
     assert property (num1[7:4] > 9 ||
                      num1[3:0] > 9 ||
                      num2[7:4] > 9 ||
                      num2[3:0] > 9 ||
                      of ||
                      (num1[7:4] * 10 + num1[3:0])
                      + (num2[7:4] * 10 + num2[3:0])
                      == (out[7:4] * 10 + out[3:0]));
   assert property (num1[7:4] > 9 ||
                    num1[3:0] > 9 ||
                    num2[7:4] > 9 ||
                    num2[3:0] > 9 ||
                    !of ||
                    (num1[7:4] * 10 + num1[3:0])
                    + (num2[7:4] * 10 + num2[3:0])
                    > 99);
`endif

endmodule