data/full_repos/permissive/138961980/powlib_std.v
 line:24: before: "if"
1: b'%Error: data/full_repos/permissive/138961980/powlib_std.v:195: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh.v\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh.sv\n             powlib_std.vh\n             powlib_std.vh.v\n             powlib_std.vh.sv\n             obj_dir/powlib_std.vh\n             obj_dir/powlib_std.vh.v\n             obj_dir/powlib_std.vh.sv\n%Error: data/full_repos/permissive/138961980/powlib_std.v:221: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:252: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:207: Define or directive not defined: \'`POWLIB_DW\'\n            wire [`POWLIB_DW-1:0] d0 = powlib_grayencode(d); \n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:233: Define or directive not defined: \'`POWLIB_DW\'\n            wire [`POWLIB_DW-1:0] d0 = powlib_graydecode(d); \n                  ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module powlib_dpram(wridx,wrdata,wrvld,wrbe,rdidx,rddata,rdrdy,clk,wrclk,rdclk);



`include "powlib_std.vh"

  parameter                    W      = 32;
  parameter                    D      = 128;
  parameter         [W*D-1:0]  INIT   = 0;
  parameter                    WIDX   = powlib_clogb2(D);
  parameter                    EWBE   = 0;
  parameter                    ERDRDY = 0;
  parameter                    ERRD   = 0;
  parameter                    EASYNC = 0;
  parameter                    EDBG   = 0;
  parameter                    ID     = "DPRAM";
  input     wire    [WIDX-1:0] wridx;
  input     wire    [W-1:0]    wrdata;
  input     wire               wrvld;
  input     wire    [W-1:0]    wrbe;
  input     wire    [WIDX-1:0] rdidx;
  output    reg     [W-1:0]    rddata=0;
  input     wire               rdrdy;
  input     wire               clk;
  input     wire               wrclk;
  input     wire               rdclk;
            wire               wrclk0, rdclk0;
            reg     [W-1:0]    mem[D-1:0];
            reg                rdrdy0;
            integer            i; 


  assign wrclk0 = (EASYNC!=0) ? wrclk : clk; 
  assign rdclk0 = (EASYNC!=0) ? rdclk : clk;
              
  always @(*) begin
    rdrdy0 <= rdrdy==1 || ERDRDY==0;
  end    
    
  if (ERRD!=0) begin
    always @(posedge rdclk0) begin
      if (rdrdy0==1) begin
        rddata <= mem[rdidx];
      end
    end
  end else begin
    always @(*) begin
      rddata <= mem[rdidx];
    end
  end
    
  initial begin
    for (i=0; i<D; i=i+1) begin
      mem[i] = INIT[W*i +: W]; 
    end    
  end
  
  always @(posedge wrclk0) begin               
    if (EWBE==0) begin
      if (wrvld==1) begin
        mem[wridx] <= wrdata;
      end
    end else begin
      for (i=0; i<W; i=i+1) begin
        if (wrbe[i]==1) begin
          mem[wridx][i] <= wrdata[i];
        end
      end
    end    
  end

  if (EDBG!=0) begin
    always @(posedge wrclk0) begin      
      for (i=0; i<D; i=i+1) begin
        $display("ID: %s, i: %d, mem[i]: %h", ID, i, mem[i]);        
      end     
    end
  end

endmodule
module powlib_dpram(wridx,wrdata,wrvld,wrbe,rdidx,rddata,rdrdy,clk,wrclk,rdclk);




`include "powlib_std.vh"

  parameter                    W      = 32;
  parameter                    D      = 128;
  parameter         [W*D-1:0]  INIT   = 0;
  parameter                    WIDX   = powlib_clogb2(D);
  parameter                    EWBE   = 0;
  parameter                    ERDRDY = 0;
  parameter                    ERRD   = 0;
  parameter                    EASYNC = 0;
  parameter                    EDBG   = 0;
  parameter                    ID     = "DPRAM";
  input     wire    [WIDX-1:0] wridx;
  input     wire    [W-1:0]    wrdata;
  input     wire               wrvld;
  input     wire    [W-1:0]    wrbe;
  input     wire    [WIDX-1:0] rdidx;
  output    reg     [W-1:0]    rddata=0;
  input     wire               rdrdy;
  input     wire               clk;
  input     wire               wrclk;
  input     wire               rdclk;
            wire               wrclk0, rdclk0;
            reg     [W-1:0]    mem[D-1:0];
            reg                rdrdy0;
            integer            i; 


  assign wrclk0 = (EASYNC!=0) ? wrclk : clk; 
  assign rdclk0 = (EASYNC!=0) ? rdclk : clk;
              
  always @(*) begin
    rdrdy0 <= rdrdy==1 || ERDRDY==0;
  end    
    
  if (ERRD!=0) begin
    always @(posedge rdclk0) begin
      if (rdrdy0==1) begin
        rddata <= mem[rdidx];
      end
    end
  end else begin
    always @(*) begin
      rddata <= mem[rdidx];
    end
  end
    
  initial begin
    for (i=0; i<D; i=i+1) begin
      mem[i] = INIT[W*i +: W]; 
    end    
  end
  
  always @(posedge wrclk0) begin               
    if (EWBE==0) begin
      if (wrvld==1) begin
        mem[wridx] <= wrdata;
      end
    end else begin
      for (i=0; i<W; i=i+1) begin
        if (wrbe[i]==1) begin
          mem[wridx][i] <= wrdata[i];
        end
      end
    end    
  end

  if (EDBG!=0) begin
    always @(posedge wrclk0) begin      
      for (i=0; i<D; i=i+1) begin
        $display("ID: %s, i: %d, mem[i]: %h", ID, i, mem[i]);        
      end     
    end
  end

endmodule