data/full_repos/permissive/200314387/verilog/74574/test.v
 line:29: before: ">"
1: b'%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:3: Cannot find include file: hct74574.v\n`include "hct74574.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/74574,data/full_repos/permissive/200314387/hct74574.v\n             data/full_repos/permissive/200314387/verilog/74574,data/full_repos/permissive/200314387/hct74574.v.v\n             data/full_repos/permissive/200314387/verilog/74574,data/full_repos/permissive/200314387/hct74574.v.sv\n             hct74574.v\n             hct74574.v.v\n             hct74574.v.sv\n             obj_dir/hct74574.v\n             obj_dir/hct74574.v.v\n             obj_dir/hct74574.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:4: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:21: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:22: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,  register);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:44: Define or directive not defined: \'`equals\'\n    `equals(Q , undefined, "initial");\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:44: syntax error, unexpected \',\'\n    `equals(Q , undefined, "initial");\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74574/test.v:43: Unsupported: Ignoring delay on this delayed statement.\n #pdOE \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:48: Define or directive not defined: \'`equals\'\n    `equals(Q , zed, "output disabled");\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:48: syntax error, unexpected \',\'\n    `equals(Q , zed, "output disabled");\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74574/test.v:47: Unsupported: Ignoring delay on this delayed statement.\n #(pdOE+1) \n ^\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:52: Define or directive not defined: \'`equals\'\n    `equals(Q , undefined, "unclocked - D = X");\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:52: syntax error, unexpected \',\'\n    `equals(Q , undefined, "unclocked - D = X");\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74574/test.v:51: Unsupported: Ignoring delay on this delayed statement.\n #(pdOE+1)\n ^\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:57: Define or directive not defined: \'`equals\'\n    `equals(Q , 0, "clocked - but AA not setup prior to serup interval so pickup the earlier 00");\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:57: syntax error, unexpected \',\'\n    `equals(Q , 0, "clocked - but AA not setup prior to serup interval so pickup the earlier 00");\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74574/test.v:56: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74574/test.v:60: Unsupported: Ignoring delay on this delayed statement.\n #pdOE \n ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74574/test.v:63: Unsupported: Ignoring delay on this delayed statement.\n #(setup+1)\n ^\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:67: Define or directive not defined: \'`equals\'\n    `equals(Q , 8\'b1, "transition to high - wth 1");\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:67: syntax error, unexpected \',\'\n    `equals(Q , 8\'b1, "transition to high - wth 1");\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74574/test.v:66: Unsupported: Ignoring delay on this delayed statement.\n #(pdCLK+1)\n ^\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:71: Define or directive not defined: \'`equals\'\n    `equals(Q , 8\'b1, "remain high - wth 1");\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:71: syntax error, unexpected \',\'\n    `equals(Q , 8\'b1, "remain high - wth 1");\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74574/test.v:70: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:75: Define or directive not defined: \'`equals\'\n    `equals(Q , 1, "transition to low - with 255 should still be 1");\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:75: syntax error, unexpected \',\'\n    `equals(Q , 1, "transition to low - with 255 should still be 1");\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74574/test.v:74: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74574/test.v:79: Unsupported: Ignoring delay on this delayed statement.\n #(setup+1)\n ^\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:82: Define or directive not defined: \'`equals\'\n    `equals(Q , zed, "transition to high - should clock in 255 when _OE disabled");\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:82: syntax error, unexpected \',\'\n    `equals(Q , zed, "transition to high - should clock in 255 when _OE disabled");\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74574/test.v:81: Unsupported: Ignoring delay on this delayed statement.\n #pdOE\n ^\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:86: Define or directive not defined: \'`equals\'\n    `equals(Q , 8\'d255, "oe enabled");\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74574/test.v:86: syntax error, unexpected \',\'\n    `equals(Q , 8\'d255, "oe enabled");\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74574/test.v:85: Unsupported: Ignoring delay on this delayed statement.\n #(pdOE+1)\n ^\n%Error: Exiting due to 22 error(s), 12 warning(s)\n'
module icarus_tb();
    
	logic [7:0] D, Q;
	logic CLK, _OE;
    
	hct74574 register( .D, .Q, .CLK, ._OE);
    
    integer pdOE = register.PD_OE_Q;
    integer pdCLK = register.PD_CLK_Q;
    integer setup = register.SETUP_TIME;
    
    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0,  register);
        
        $display ("");
        $display ($time, "   D         Q         CLK  _OE");
`ifndef verilator
        $monitor ($time, "   %8b  %8b  %b   %b", D,   Q,   CLK,  _OE);
`endif
    end

    initial begin
        parameter zero      = 8'b0;
        parameter aa     = 8'b10101010;
        parameter undefined = 8'bx;
        parameter zed       = 8'bz;
        parameter low  = 0;
        parameter high  = 1;
        parameter disabled = 1;
        parameter enabled = 0;

	D=zero;
	CLK=low;
	#pdOE 
    `equals(Q , undefined, "initial");

	_OE=disabled;
	#(pdOE+1) 
    `equals(Q , zed, "output disabled");

	_OE=enabled;
	#(pdOE+1)
    `equals(Q , undefined, "unclocked - D = X");

	D=aa;
	CLK=high;
	#1000
    `equals(Q , 0, "clocked - but AA not setup prior to serup interval so pickup the earlier 00");

	CLK=low;
	#pdOE 

	D=1;
	#(setup+1)

	CLK=high;
	#(pdCLK+1)
    `equals(Q , 8'b1, "transition to high - wth 1");

	D=255;
	#1000
    `equals(Q , 8'b1, "remain high - wth 1");

	CLK=low;
	#1000
    `equals(Q , 1, "transition to low - with 255 should still be 1");

	D=255;
	_OE=disabled;
	#(setup+1)
	CLK=high;
	#pdOE
    `equals(Q , zed, "transition to high - should clock in 255 when _OE disabled");

	_OE=enabled;
	#(pdOE+1)
    `equals(Q , 8'd255, "oe enabled");


    end
endmodule
module icarus_tb();

    
	logic [7:0] D, Q;
	logic CLK, _OE;
    
	hct74574 register( .D, .Q, .CLK, ._OE);
    
    integer pdOE = register.PD_OE_Q;
    integer pdCLK = register.PD_CLK_Q;
    integer setup = register.SETUP_TIME;
    
    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0,  register);
        
        $display ("");
        $display ($time, "   D         Q         CLK  _OE");
`ifndef verilator
        $monitor ($time, "   %8b  %8b  %b   %b", D,   Q,   CLK,  _OE);
`endif
    end

    initial begin
        parameter zero      = 8'b0;
        parameter aa     = 8'b10101010;
        parameter undefined = 8'bx;
        parameter zed       = 8'bz;
        parameter low  = 0;
        parameter high  = 1;
        parameter disabled = 1;
        parameter enabled = 0;

	D=zero;
	CLK=low;
	#pdOE 
    `equals(Q , undefined, "initial");

	_OE=disabled;
	#(pdOE+1) 
    `equals(Q , zed, "output disabled");

	_OE=enabled;
	#(pdOE+1)
    `equals(Q , undefined, "unclocked - D = X");

	D=aa;
	CLK=high;
	#1000
    `equals(Q , 0, "clocked - but AA not setup prior to serup interval so pickup the earlier 00");

	CLK=low;
	#pdOE 

	D=1;
	#(setup+1)

	CLK=high;
	#(pdCLK+1)
    `equals(Q , 8'b1, "transition to high - wth 1");

	D=255;
	#1000
    `equals(Q , 8'b1, "remain high - wth 1");

	CLK=low;
	#1000
    `equals(Q , 1, "transition to low - with 255 should still be 1");

	D=255;
	_OE=disabled;
	#(setup+1)
	CLK=high;
	#pdOE
    `equals(Q , zed, "transition to high - should clock in 255 when _OE disabled");

	_OE=enabled;
	#(pdOE+1)
    `equals(Q , 8'd255, "oe enabled");


    end
endmodule