data/full_repos/permissive/143278/ivltests/wiremod1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wiremod1.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #1 ;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wiremod1.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

reg globvar;

reg [3:0] var1,var2,var3;
wire [3:0] var3a;
reg error;

assign var3a = var1 % var2;

always @( var1 or var2)
  var3 = var1 % var2 ;

initial
begin
for ( var1 = 4'b0; var1 != 4'hf; var1 = var1 + 1)
  for ( var2 = 4'b0; var2 != 4'hf; var2 = var2 + 1)
     begin
        error = 0;
        #1 ;
        if(var3 != var3a)
          begin
           $display("FAILED continuous 1=%h,2=%h,3=%h,3a=%h",
                     var1,var2,var3,var3a);
            error = 1;
          end
        #1;
     end
if(error == 0)
    $display("PASSED");
end
endmodule
module main;


reg globvar;

reg [3:0] var1,var2,var3;
wire [3:0] var3a;
reg error;

assign var3a = var1 % var2;

always @( var1 or var2)
  var3 = var1 % var2 ;

initial
begin
for ( var1 = 4'b0; var1 != 4'hf; var1 = var1 + 1)
  for ( var2 = 4'b0; var2 != 4'hf; var2 = var2 + 1)
     begin
        error = 0;
        #1 ;
        if(var3 != var3a)
          begin
           $display("FAILED continuous 1=%h,2=%h,3=%h,3a=%h",
                     var1,var2,var3,var3a);
            error = 1;
          end
        #1;
     end
if(error == 0)
    $display("PASSED");
end
endmodule