data/full_repos/permissive/143278/ivltests/pr1676071.v
 line:6: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1676071.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gentest;

reg [7:0] a=0, b=0;
wire co;
wire [7:0] result;

adder work(a, b, 1'b0, result, co);

integer cc;
initial begin
	for (cc=0; cc<10; cc=cc+1) begin
		a=a+1;
		#10;
		$display("%d %d %d", a, b, result);
		b=result;
	end
	if (b==55) $display("PASSED");
	else $display("FAIL");
end

endmodule
module gentest;


reg [7:0] a=0, b=0;
wire co;
wire [7:0] result;

adder work(a, b, 1'b0, result, co);

integer cc;
initial begin
	for (cc=0; cc<10; cc=cc+1) begin
		a=a+1;
		#10;
		$display("%d %d %d", a, b, result);
		b=result;
	end
	if (b==55) $display("PASSED");
	else $display("FAIL");
end

endmodule