data/full_repos/permissive/117439233/hdl/src/branch_prediction/branch_prediction.v
1: b"%Error: data/full_repos/permissive/117439233/hdl/src/branch_prediction/branch_prediction.v:6: Duplicate declaration of signal: 'Branch'\n input Branch,\n       ^~~~~~\n        data/full_repos/permissive/117439233/hdl/src/branch_prediction/branch_prediction.v:5: ... Location of original declaration\n input Branch,\n       ^~~~~~\n%Error: data/full_repos/permissive/117439233/hdl/src/branch_prediction/branch_prediction.v:6: Duplicate declaration of port: 'Branch'\n input Branch,\n       ^~~~~~\n        data/full_repos/permissive/117439233/hdl/src/branch_prediction/branch_prediction.v:5: ... Location of original declaration\n input Branch,\n       ^~~~~~\n%Error: data/full_repos/permissive/117439233/hdl/src/branch_prediction/branch_prediction.v:20: Can't find definition of variable: 'Global_History'\n                                                                                             : ... Suggested alternative: 'Global_History_Reg'\n    Global_History <= 2'b0;\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117439233/hdl/src/branch_prediction/branch_prediction.v:22: Can't find definition of variable: 'Branch_Result'\n    Global_History_Reg <= (Global_History_Reg << 1) | Branch_Result;\n                                                      ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module branch_prediction(
	input CLK,
	input RST,
	
	input Branch,
	input Branch,
	input [3:0] Branch_PC,
	output Prediction
	);
	
	reg [1:0] Global_History_Reg;
	reg [3:0] Local_History_Table_0;
        reg [3:0] Local_History_Table_1;
        reg [3:0] Local_History_Table_2;
        reg [3:0] Local_History_Table_3;

	always @ (posedge CLK)
		begin
			if(RST)
				Global_History <= 2'b0;
			else
				Global_History_Reg <= (Global_History_Reg << 1) | Branch_Result;
		end

	
	wire Branch_EN = 4'b0;
	history_table table_00(.CLK(CLK), .RST(RST), .Branch_en(Branch_EN[0]), .Branch(Branch), .Branch_PC(Branch_PC), .Prediction(Prediction_00));
        history_table table_01(.CLK(CLK), .RST(RST), .Branch_en(Branch_EN[1]), .Branch(Branch), .Branch_PC(Branch_PC), .Prediction(Prediction_01));
        history_table table_10(.CLK(CLK), .RST(RST), .Branch_en(Branch_EN[2]), .Branch(Branch), .Branch_PC(Branch_PC), .Prediction(Prediction_10));
        history_table table_11(.CLK(CLK), .RST(RST), .Branch_en(Branch_EN[3]), .Branch(Branch), .Branch_PC(Branch_PC), .Prediction(Prediction_11));

endmodule
module branch_prediction(
	input CLK,
	input RST,
	
	input Branch,
	input Branch,
	input [3:0] Branch_PC,
	output Prediction
	);

	
	reg [1:0] Global_History_Reg;
	reg [3:0] Local_History_Table_0;
        reg [3:0] Local_History_Table_1;
        reg [3:0] Local_History_Table_2;
        reg [3:0] Local_History_Table_3;

	always @ (posedge CLK)
		begin
			if(RST)
				Global_History <= 2'b0;
			else
				Global_History_Reg <= (Global_History_Reg << 1) | Branch_Result;
		end

	
	wire Branch_EN = 4'b0;
	history_table table_00(.CLK(CLK), .RST(RST), .Branch_en(Branch_EN[0]), .Branch(Branch), .Branch_PC(Branch_PC), .Prediction(Prediction_00));
        history_table table_01(.CLK(CLK), .RST(RST), .Branch_en(Branch_EN[1]), .Branch(Branch), .Branch_PC(Branch_PC), .Prediction(Prediction_01));
        history_table table_10(.CLK(CLK), .RST(RST), .Branch_en(Branch_EN[2]), .Branch(Branch), .Branch_PC(Branch_PC), .Prediction(Prediction_10));
        history_table table_11(.CLK(CLK), .RST(RST), .Branch_en(Branch_EN[3]), .Branch(Branch), .Branch_PC(Branch_PC), .Prediction(Prediction_11));

endmodule