data/full_repos/permissive/170402453/SignalRouter8_1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:75: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'OUT5_\' generates 8 bits.\n                                                                         : ... In instance SignalRouter8_1\n  assign OUT5 = OUT5_;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:76: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'OUT6_\' generates 8 bits.\n                                                                         : ... In instance SignalRouter8_1\n  assign OUT6 = OUT6_;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:77: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'OUT7_\' generates 8 bits.\n                                                                         : ... In instance SignalRouter8_1\n  assign OUT7 = OUT7_;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:78: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'OUT8_\' generates 8 bits.\n                                                                         : ... In instance SignalRouter8_1\n  assign OUT8 = OUT8_;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:107: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'IN5\' generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n  RMAP[4][4]  <= (RSel[9:8] == 3) ? IN5 :       \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:109: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'C5\' generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n       (RSel[9:8] == 1) ? PWM5 : C5;  \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:107: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                          : ... In instance SignalRouter8_1\n  RMAP[4][4]  <= (RSel[9:8] == 3) ? IN5 :       \n              ^~\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:111: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'IN6\' generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n  RMAP[4][5]  <= (RSel[11:10] == 3) ? IN6 :      \n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:113: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'C6\' generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n       (RSel[11:10] == 1) ? PWM6 : C6; \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:111: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                          : ... In instance SignalRouter8_1\n  RMAP[4][5]  <= (RSel[11:10] == 3) ? IN6 :      \n              ^~\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:115: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'IN7\' generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n  RMAP[4][6]  <= (RSel[13:12] == 3) ? IN7 :      \n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:117: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'C7\' generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n       (RSel[13:12] == 1) ? PWM7 : C7; \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:115: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                          : ... In instance SignalRouter8_1\n  RMAP[4][6]  <= (RSel[13:12] == 3) ? IN7 :      \n              ^~\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:119: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'IN8\' generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n  RMAP[4][7]  <= (RSel[15:14] == 3) ? IN8 :      \n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:121: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'C8\' generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n       (RSel[15:14] == 1) ? PWM8 : C8; \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:119: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                          : ... In instance SignalRouter8_1\n  RMAP[4][7]  <= (RSel[15:14] == 3) ? IN8 :      \n              ^~\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:122: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n  OUT8_ <= RMAP[4][RLoc[21 +:3]];\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:129: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n  OUT5_ <= RMAP[4][RLoc[12 +:3]];\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:130: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n  OUT6_ <= RMAP[4][RLoc[15 +:3]];\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:131: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n  OUT7_ <= RMAP[4][RLoc[18 +:3]];\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/170402453/SignalRouter8_1.v:132: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance SignalRouter8_1\n  OUT8_ <= RMAP[4][RLoc[21 +:3]];  \n        ^~\n%Error: data/full_repos/permissive/170402453/SignalRouter8_1.v:136: Cannot find file containing module: \'SubClockDyn\'\n SubClockDyn clk5 (.CLK(CLK), .Freq(ClkDiv5), .OUTCLK(CLK5));\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/SubClockDyn\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/SubClockDyn.v\n             data/full_repos/permissive/170402453,data/full_repos/permissive/170402453/SubClockDyn.sv\n             SubClockDyn\n             SubClockDyn.v\n             SubClockDyn.sv\n             obj_dir/SubClockDyn\n             obj_dir/SubClockDyn.v\n             obj_dir/SubClockDyn.sv\n%Error: data/full_repos/permissive/170402453/SignalRouter8_1.v:137: Cannot find file containing module: \'SubClockDyn\'\n SubClockDyn clk6 (.CLK(CLK), .Freq(ClkDiv6), .OUTCLK(CLK6));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/SignalRouter8_1.v:138: Cannot find file containing module: \'SubClockDyn\'\n SubClockDyn clk7 (.CLK(CLK), .Freq(ClkDiv7), .OUTCLK(CLK7));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/SignalRouter8_1.v:139: Cannot find file containing module: \'SubClockDyn\'\n SubClockDyn clk8 (.CLK(CLK), .Freq(ClkDiv8), .OUTCLK(CLK8));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/170402453/SignalRouter8_1.v:141: Cannot find file containing module: \'PWM\'\n PWM pwm5 (CLK5,PWMRate5,PWM5);\n ^~~\n%Error: data/full_repos/permissive/170402453/SignalRouter8_1.v:142: Cannot find file containing module: \'PWM\'\n PWM pwm6 (CLK6,PWMRate6,PWM6);\n ^~~\n%Error: data/full_repos/permissive/170402453/SignalRouter8_1.v:143: Cannot find file containing module: \'PWM\'\n PWM pwm7 (CLK7,PWMRate7,PWM7);\n ^~~\n%Error: data/full_repos/permissive/170402453/SignalRouter8_1.v:144: Cannot find file containing module: \'PWM\'\n PWM pwm8 (CLK8,PWMRate8,PWM8);\n ^~~\n%Error: Exiting due to 8 error(s), 21 warning(s)\n'
module SignalRouter8_1(
	 input CLK,
    input [7:0] IN1,
	 input [7:0] IN2,
	 input [7:0] IN3,
	 input [7:0] IN4,
	 input IN5,
	 input IN6,
	 input IN7,
	 input IN8,
	 input [7:0] C1,
	 input [7:0] C2,
	 input [7:0] C3,
	 input [7:0] C4,
	 input C5,
	 input C6,
	 input C7,
	 input C8,
	 input [25:0] ClkDiv5,
	 input [25:0] ClkDiv6,
	 input [25:0] ClkDiv7,
	 input [25:0] ClkDiv8,
	 input [7:0] PWMRate5,
	 input [7:0] PWMRate6,
	 input [7:0] PWMRate7,
	 input [7:0] PWMRate8,
	 output [7:0] OUT1,
	 output [7:0] OUT2,
	 output [7:0] OUT3,
	 output [7:0] OUT4,
	 output OUT5,
	 output OUT6,
	 output OUT7,
	 output OUT8,
	 input [23:0] RLoc,
	 input [15:0] RSel
    );
	 
	 reg [1:0] R;
	 reg [7:0] OUT1_,OUT2_,OUT3_,OUT4_,OUT5_,OUT6_,OUT7_,OUT8_;
	 reg [7:0] RMAP [7:0];
	 wire [7:0] CLK5,CLK6,CLK7,CLK8;
	 wire [7:0] PWM5,PWM6,PWM7,PWM8;
	 integer incrementer;
	 
	 assign OUT1 = OUT1_;
	 assign OUT2 = OUT2_;
	 assign OUT3 = OUT3_;
	 assign OUT4 = OUT4_;
	 assign OUT5 = OUT5_;
	 assign OUT6 = OUT6_;
	 assign OUT7 = OUT7_;
	 assign OUT8 = OUT8_;
	 
	 initial begin
		OUT1_ = 0;
		OUT2_ = 0;
		OUT3_ = 0;
		OUT4_ = 0;
		OUT5_ = 0;
		OUT6_ = 0;
		OUT7_ = 0;
		OUT8_ = 0;
		RMAP[0] = 0;
		RMAP[1] = 0;
		RMAP[2] = 0;
		RMAP[3] = 0;
		RMAP[4] = 0;
		R=0;
	 end
	 

	 always @(negedge CLK) begin


		RMAP[0] <= (RSel[1:0] == 3) ? IN1 : C1;
		RMAP[1] <= (RSel[3:2] == 3) ? IN2 : C2;
		RMAP[2] <= (RSel[5:4] == 3) ? IN3 : C3;
		RMAP[3] <= (RSel[7:6] == 3) ? IN4 : C4;
		

		RMAP[4][4]  <= (RSel[9:8] == 3) ? IN5 :
							(RSel[9:8] == 2) ? CLK5 :
							(RSel[9:8] == 1) ? PWM5 : C5;
							
		RMAP[4][5]  <= (RSel[11:10] == 3) ? IN6 :
							(RSel[11:10] == 2) ? CLK6 :
							(RSel[11:10] == 1) ? PWM6 : C6;
							
		RMAP[4][6]  <= (RSel[13:12] == 3) ? IN7 :
							(RSel[13:12] == 2) ? CLK7 :
							(RSel[13:12] == 1) ? PWM7 : C7;
							
		RMAP[4][7]  <= (RSel[15:14] == 3) ? IN8 :
							(RSel[15:14] == 2) ? CLK8 :
							(RSel[15:14] == 1) ? PWM8 : C8;
		OUT8_ <= RMAP[4][RLoc[21 +:3]];
	 

		OUT1_ <= RMAP[RLoc[0 +:3]];
		OUT2_ <= RMAP[RLoc[3 +:3]];
		OUT3_ <= RMAP[RLoc[6 +:3]];
		OUT4_ <= RMAP[RLoc[9 +:3]];
		OUT5_ <= RMAP[4][RLoc[12 +:3]];
		OUT6_ <= RMAP[4][RLoc[15 +:3]];
		OUT7_ <= RMAP[4][RLoc[18 +:3]];
		OUT8_ <= RMAP[4][RLoc[21 +:3]];
	 end
	 
	 
	SubClockDyn clk5 (.CLK(CLK), .Freq(ClkDiv5), .OUTCLK(CLK5));
	SubClockDyn clk6 (.CLK(CLK), .Freq(ClkDiv6), .OUTCLK(CLK6));
	SubClockDyn clk7 (.CLK(CLK), .Freq(ClkDiv7), .OUTCLK(CLK7));
	SubClockDyn clk8 (.CLK(CLK), .Freq(ClkDiv8), .OUTCLK(CLK8));
	 
	PWM pwm5 (CLK5,PWMRate5,PWM5);
	PWM pwm6 (CLK6,PWMRate6,PWM6);
	PWM pwm7 (CLK7,PWMRate7,PWM7);
	PWM pwm8 (CLK8,PWMRate8,PWM8);
		 
	

endmodule
module SignalRouter8_1(
	 input CLK,
    input [7:0] IN1,
	 input [7:0] IN2,
	 input [7:0] IN3,
	 input [7:0] IN4,
	 input IN5,
	 input IN6,
	 input IN7,
	 input IN8,
	 input [7:0] C1,
	 input [7:0] C2,
	 input [7:0] C3,
	 input [7:0] C4,
	 input C5,
	 input C6,
	 input C7,
	 input C8,
	 input [25:0] ClkDiv5,
	 input [25:0] ClkDiv6,
	 input [25:0] ClkDiv7,
	 input [25:0] ClkDiv8,
	 input [7:0] PWMRate5,
	 input [7:0] PWMRate6,
	 input [7:0] PWMRate7,
	 input [7:0] PWMRate8,
	 output [7:0] OUT1,
	 output [7:0] OUT2,
	 output [7:0] OUT3,
	 output [7:0] OUT4,
	 output OUT5,
	 output OUT6,
	 output OUT7,
	 output OUT8,
	 input [23:0] RLoc,
	 input [15:0] RSel
    );

	 
	 reg [1:0] R;
	 reg [7:0] OUT1_,OUT2_,OUT3_,OUT4_,OUT5_,OUT6_,OUT7_,OUT8_;
	 reg [7:0] RMAP [7:0];
	 wire [7:0] CLK5,CLK6,CLK7,CLK8;
	 wire [7:0] PWM5,PWM6,PWM7,PWM8;
	 integer incrementer;
	 
	 assign OUT1 = OUT1_;
	 assign OUT2 = OUT2_;
	 assign OUT3 = OUT3_;
	 assign OUT4 = OUT4_;
	 assign OUT5 = OUT5_;
	 assign OUT6 = OUT6_;
	 assign OUT7 = OUT7_;
	 assign OUT8 = OUT8_;
	 
	 initial begin
		OUT1_ = 0;
		OUT2_ = 0;
		OUT3_ = 0;
		OUT4_ = 0;
		OUT5_ = 0;
		OUT6_ = 0;
		OUT7_ = 0;
		OUT8_ = 0;
		RMAP[0] = 0;
		RMAP[1] = 0;
		RMAP[2] = 0;
		RMAP[3] = 0;
		RMAP[4] = 0;
		R=0;
	 end
	 

	 always @(negedge CLK) begin


		RMAP[0] <= (RSel[1:0] == 3) ? IN1 : C1;
		RMAP[1] <= (RSel[3:2] == 3) ? IN2 : C2;
		RMAP[2] <= (RSel[5:4] == 3) ? IN3 : C3;
		RMAP[3] <= (RSel[7:6] == 3) ? IN4 : C4;
		

		RMAP[4][4]  <= (RSel[9:8] == 3) ? IN5 :
							(RSel[9:8] == 2) ? CLK5 :
							(RSel[9:8] == 1) ? PWM5 : C5;
							
		RMAP[4][5]  <= (RSel[11:10] == 3) ? IN6 :
							(RSel[11:10] == 2) ? CLK6 :
							(RSel[11:10] == 1) ? PWM6 : C6;
							
		RMAP[4][6]  <= (RSel[13:12] == 3) ? IN7 :
							(RSel[13:12] == 2) ? CLK7 :
							(RSel[13:12] == 1) ? PWM7 : C7;
							
		RMAP[4][7]  <= (RSel[15:14] == 3) ? IN8 :
							(RSel[15:14] == 2) ? CLK8 :
							(RSel[15:14] == 1) ? PWM8 : C8;
		OUT8_ <= RMAP[4][RLoc[21 +:3]];
	 

		OUT1_ <= RMAP[RLoc[0 +:3]];
		OUT2_ <= RMAP[RLoc[3 +:3]];
		OUT3_ <= RMAP[RLoc[6 +:3]];
		OUT4_ <= RMAP[RLoc[9 +:3]];
		OUT5_ <= RMAP[4][RLoc[12 +:3]];
		OUT6_ <= RMAP[4][RLoc[15 +:3]];
		OUT7_ <= RMAP[4][RLoc[18 +:3]];
		OUT8_ <= RMAP[4][RLoc[21 +:3]];
	 end
	 
	 
	SubClockDyn clk5 (.CLK(CLK), .Freq(ClkDiv5), .OUTCLK(CLK5));
	SubClockDyn clk6 (.CLK(CLK), .Freq(ClkDiv6), .OUTCLK(CLK6));
	SubClockDyn clk7 (.CLK(CLK), .Freq(ClkDiv7), .OUTCLK(CLK7));
	SubClockDyn clk8 (.CLK(CLK), .Freq(ClkDiv8), .OUTCLK(CLK8));
	 
	PWM pwm5 (CLK5,PWMRate5,PWM5);
	PWM pwm6 (CLK6,PWMRate6,PWM6);
	PWM pwm7 (CLK7,PWMRate7,PWM7);
	PWM pwm8 (CLK8,PWMRate8,PWM8);
		 
	

endmodule