data/full_repos/permissive/114642806/dev/main.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/114642806/dev/main.v:151: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                      : ... Top module \'main\'\nmodule main(CLOCK_50, SW, GPIO_0, LEDR);\n       ^~~~\n                                                                      : ... Top module \'counter\'\nmodule counter(CLOCK_50, enable);\n       ^~~~~~~\n                                                                      : ... Top module \'backup_counter\'\nmodule backup_counter(CLOCK_50, enable_next);\n       ^~~~~~~~~~~~~~\n                                                                      : ... Top module \'emergency\'\nmodule emergency(SW, its_an_emergency);\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/114642806/dev/main.v:12: Cannot find file containing module: \'fsm\'\nfsm f0(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/114642806/dev,data/full_repos/permissive/114642806/fsm\n             data/full_repos/permissive/114642806/dev,data/full_repos/permissive/114642806/fsm.v\n             data/full_repos/permissive/114642806/dev,data/full_repos/permissive/114642806/fsm.sv\n             fsm\n             fsm.v\n             fsm.sv\n             obj_dir/fsm\n             obj_dir/fsm.v\n             obj_dir/fsm.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module counter1(clock, enable_next);

input clock;
output enable_next;

reg [25:0] count = 26'b0;
assign enable_next = (count == 26'b10111110101111000010000000) ? 1'b1 : 1'b0;






always @(posedge clock)
	begin
	if (enable_next == 1'b1)
		begin
			count <= 0;
		end
	else
		begin
			count <= count + 1'b1;
		end
	end
endmodule
module counter1(clock, enable_next);


input clock;
output enable_next;

reg [25:0] count = 26'b0;
assign enable_next = (count == 26'b10111110101111000010000000) ? 1'b1 : 1'b0;






always @(posedge clock)
	begin
	if (enable_next == 1'b1)
		begin
			count <= 0;
		end
	else
		begin
			count <= count + 1'b1;
		end
	end
endmodule