data/full_repos/permissive/143278/ivltests/sv_wildcard_import3.v
 line:1: before: "package"
1: b'%Error: data/full_repos/permissive/143278/ivltests/sv_wildcard_import3.v:10: Unsupported: event data types\nevent e;\n^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/sv_wildcard_import3.v:32: Unsupported: event data types\nevent e;\n^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/sv_wildcard_import3.v:37: syntax error, unexpected ->\n  #1 ->my_package::e;\n     ^~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sv_wildcard_import3.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #1 ->my_package::e;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/sv_wildcard_import3.v:41: syntax error, unexpected \'@\'\n  @(my_package::e);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sv_wildcard_import3.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #1 my_v = 8\'bx;\n  ^\n%Error: data/full_repos/permissive/143278/ivltests/sv_wildcard_import3.v:43: syntax error, unexpected ->\n  #1 ->e;\n     ^~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sv_wildcard_import3.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #1 ->e;\n  ^\n%Error: data/full_repos/permissive/143278/ivltests/sv_wildcard_import3.v:50: syntax error, unexpected \'@\'\n  @e v = my_v;\n  ^\n%Error: Exiting due to 6 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

parameter  p1 = 'bx;
localparam p2 = 'bx;

typedef logic [7:0] word;

word v = 8'bx;

event e;

word my_v = 1;

initial begin
  #1 ->my_package::e;
end

initial begin
  @(my_package::e);
  #1 my_v = 8'bx;
  #1 ->e;
end

initial begin:my_block
  import my_package::*;


  @e v = my_v;
  h(f(1));
  if (p1 === 1 && p2 === 2 && $bits(v) === 4 && v === 3)
    $display("PASSED");
  else
    $display("FAILED");
end

function word f(word g);
  f = g + 8'bx;
endfunction

task h(word i);
  v = v + i + 8'bx;
  $display(v);
endtask

endmodule
module test();


parameter  p1 = 'bx;
localparam p2 = 'bx;

typedef logic [7:0] word;

word v = 8'bx;

event e;

word my_v = 1;

initial begin
  #1 ->my_package::e;
end

initial begin
  @(my_package::e);
  #1 my_v = 8'bx;
  #1 ->e;
end

initial begin:my_block
  import my_package::*;


  @e v = my_v;
  h(f(1));
  if (p1 === 1 && p2 === 2 && $bits(v) === 4 && v === 3)
    $display("PASSED");
  else
    $display("FAILED");
end

function word f(word g);
  f = g + 8'bx;
endfunction

task h(word i);
  v = v + i + 8'bx;
  $display(v);
endtask

endmodule