data/full_repos/permissive/164482394/Verilog/MIDI_rx.v
 line:48: before: "begin"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/164482394/Verilog/MIDI_rx.v:23: Signal definition not found, creating implicitly: \'Tstate\'\n                                                                            : ... Suggested alternative: \'State\'\n assign Tstate = State;  \n        ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/164482394/Verilog/MIDI_rx.v:85: Operator LT expects 5 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n                                                                         : ... In instance MIDI_rx\n   if ((counter == 12\'d1600) & (!start_bit) & (Bit < 4\'b1000))  \n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/164482394/Verilog/MIDI_rx.v:94: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n                                                                         : ... In instance MIDI_rx\n    Bit <= 12\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/164482394/Verilog/MIDI_rx.v:96: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                         : ... In instance MIDI_rx\n    counter <= 4\'b0000;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/164482394/Verilog/MIDI_rx.v:92: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n                                                                         : ... In instance MIDI_rx\n   if ((counter == 12\'d1600) & (Bit == 4\'b1000) & (Rx == 1\'b1))   \n                                    ^~\n%Error: Exiting due to 5 warning(s)\n'
module MIDI_rx (Clk, Rst_n, RxData, read_enable, Rx, State);	

	input Clk, Rst_n, Rx;
	
	output read_enable, State;
	output reg [7:0] RxData;

	parameter IDLE = 1'b0; 
	parameter READ = 1'b1;
	reg State;
	reg read_enable = 1'b0;
	reg start_bit = 1'b1;
	reg RxDone = 1'b1;
	reg [4:0] Bit = 5'b0;
	reg [11:0] counter = 12'b0;
	reg [7:0] Read_data = 8'b0;

	assign Tstate = State;


	always @ (posedge Clk)
	begin
		if (Rst_n == 1'b0)
		begin
			State <= IDLE;
		end
		else begin
			case(State)	
				IDLE:	if(Rx == 1'b0)		
				begin
					State <= READ;
				end
				else begin
					State <= IDLE;
				end
				READ:	if(RxDone == 1'b1)
				begin
					State <= IDLE;
				end
				else begin
					State <= READ;
				end
				default begin
					State <= IDLE;
				end
			endcase
		end
	end

	always @ (State)
	begin
		case (State)
			READ: 
			begin
				read_enable = 1'b1;
	      end
	
			IDLE: 
			begin
				read_enable = 1'b0;
	      end
		endcase
	end 


	always @ (posedge Clk)
	begin
		if (read_enable)
		begin
			RxDone <= 1'b0;
			counter <= counter + 1'b1;
	

			if ((counter == 12'd800) & (start_bit))
			begin
				start_bit <= 1'b0;
				counter <= 12'b0;
			end

			if ((counter == 12'd1600) & (!start_bit) & (Bit < 4'b1000))
			begin
				Bit <= Bit + 1'b1;
				Read_data <= {Rx,Read_data[7:1]};
				counter <= 12'b0;
			end
	
			if ((counter == 12'd1600) & (Bit == 4'b1000) & (Rx == 1'b1))
			begin
				Bit <= 12'b0;
				RxDone <= 1'b1;
				counter <= 4'b0000;
				start_bit <= 1'b1;
				RxData[7:0] <= Read_data[7:0];	
			end
		end
	end

endmodule
module MIDI_rx (Clk, Rst_n, RxData, read_enable, Rx, State);
	

	input Clk, Rst_n, Rx;
	
	output read_enable, State;
	output reg [7:0] RxData;

	parameter IDLE = 1'b0; 
	parameter READ = 1'b1;
	reg State;
	reg read_enable = 1'b0;
	reg start_bit = 1'b1;
	reg RxDone = 1'b1;
	reg [4:0] Bit = 5'b0;
	reg [11:0] counter = 12'b0;
	reg [7:0] Read_data = 8'b0;

	assign Tstate = State;


	always @ (posedge Clk)
	begin
		if (Rst_n == 1'b0)
		begin
			State <= IDLE;
		end
		else begin
			case(State)	
				IDLE:	if(Rx == 1'b0)		
				begin
					State <= READ;
				end
				else begin
					State <= IDLE;
				end
				READ:	if(RxDone == 1'b1)
				begin
					State <= IDLE;
				end
				else begin
					State <= READ;
				end
				default begin
					State <= IDLE;
				end
			endcase
		end
	end

	always @ (State)
	begin
		case (State)
			READ: 
			begin
				read_enable = 1'b1;
	      end
	
			IDLE: 
			begin
				read_enable = 1'b0;
	      end
		endcase
	end 


	always @ (posedge Clk)
	begin
		if (read_enable)
		begin
			RxDone <= 1'b0;
			counter <= counter + 1'b1;
	

			if ((counter == 12'd800) & (start_bit))
			begin
				start_bit <= 1'b0;
				counter <= 12'b0;
			end

			if ((counter == 12'd1600) & (!start_bit) & (Bit < 4'b1000))
			begin
				Bit <= Bit + 1'b1;
				Read_data <= {Rx,Read_data[7:1]};
				counter <= 12'b0;
			end
	
			if ((counter == 12'd1600) & (Bit == 4'b1000) & (Rx == 1'b1))
			begin
				Bit <= 12'b0;
				RxDone <= 1'b1;
				counter <= 4'b0000;
				start_bit <= 1'b1;
				RxData[7:0] <= Read_data[7:0];	
			end
		end
	end

endmodule