data/full_repos/permissive/180282590/SimpleGPUonS7.srcs/sources_1/new/staticRam.v
data/verilator_xmls/b5025610-2f07-4de7-aa29-3de34941e8c2.xml
module staticRamDiscretePorts (
            address     ,
            data        ,
            we_,
            clock,
            Q
            );
            parameter ROMFILE = "noFile";
            parameter DATA_WIDTH = 8 ;
            parameter ADDR_WIDTH = 8 ;
            parameter RAM_DEPTH = 1 << ADDR_WIDTH;
            
        

            input [ADDR_WIDTH-1:0] address ;
            input [DATA_WIDTH-1:0]  data;
            input we_;
            input clock;
        

            output reg [DATA_WIDTH-1:0] Q;
            integer i;

            reg [DATA_WIDTH-1:0] mem [RAM_DEPTH-1:0];
            

            initial begin
             $readmemb(ROMFILE, mem);
              for (i = 0; i < RAM_DEPTH; i = i + 1) begin

              end
            end
            
            always @(posedge clock)
            begin
              if (!we_) begin
                mem[address] <= data;
                end
                else begin
               Q <= mem[address];
               end
            end
            
            endmodule
module staticRamDiscretePorts (
            address     ,
            data        ,
            we_,
            clock,
            Q
            );

            parameter ROMFILE = "noFile";
            parameter DATA_WIDTH = 8 ;
            parameter ADDR_WIDTH = 8 ;
            parameter RAM_DEPTH = 1 << ADDR_WIDTH;
            
        

            input [ADDR_WIDTH-1:0] address ;
            input [DATA_WIDTH-1:0]  data;
            input we_;
            input clock;
        

            output reg [DATA_WIDTH-1:0] Q;
            integer i;

            reg [DATA_WIDTH-1:0] mem [RAM_DEPTH-1:0];
            

            initial begin
             $readmemb(ROMFILE, mem);
              for (i = 0; i < RAM_DEPTH; i = i + 1) begin

              end
            end
            
            always @(posedge clock)
            begin
              if (!we_) begin
                mem[address] <= data;
                end
                else begin
               Q <= mem[address];
               end
            end
            
            endmodule