data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_サンプル回路/FPGA/FPGA_stopwatch/time_manager.v
data/verilator_xmls/30b442b7-8049-495f-ac60-cb73fd4cea4e.xml
module time_manager(

		CLK,
		RSTN,

		SEC_SIG
);


input CLK;
input RSTN;


output SEC_SIG;


reg [27:0] SEC_COUNT;
reg SEC_SIG;

	always@( posedge CLK or negedge RSTN) begin
  		if( !RSTN )begin
    		SEC_COUNT <= 28'd0;
		end
		else if( SEC_COUNT >= 28'd20000000 - 28'd1)begin
			SEC_COUNT <= 28'd0;
		end
  		else begin
    		SEC_COUNT <= SEC_COUNT + 28'd1;
		end
	end

	always@( posedge CLK or negedge RSTN) begin
		if( !RSTN )begin
    		SEC_SIG <= 1'b0;
		end
  		else if( SEC_COUNT >= 28'd20000000 - 28'd1 )begin
    		SEC_SIG <= 1'b1;
		end
  		else begin
   	 		SEC_SIG <= 1'b0;
		end
	end

endmodule
module time_manager(

		CLK,
		RSTN,

		SEC_SIG
);



input CLK;
input RSTN;


output SEC_SIG;


reg [27:0] SEC_COUNT;
reg SEC_SIG;

	always@( posedge CLK or negedge RSTN) begin
  		if( !RSTN )begin
    		SEC_COUNT <= 28'd0;
		end
		else if( SEC_COUNT >= 28'd20000000 - 28'd1)begin
			SEC_COUNT <= 28'd0;
		end
  		else begin
    		SEC_COUNT <= SEC_COUNT + 28'd1;
		end
	end

	always@( posedge CLK or negedge RSTN) begin
		if( !RSTN )begin
    		SEC_SIG <= 1'b0;
		end
  		else if( SEC_COUNT >= 28'd20000000 - 28'd1 )begin
    		SEC_SIG <= 1'b1;
		end
  		else begin
   	 		SEC_SIG <= 1'b0;
		end
	end

endmodule