data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv
 line:151: before: ")"
1: b'%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:2: Cannot find include file: ../majority_top.sv\n`include "../majority_top.sv" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219917900/rx_rtl_files/sim,data/full_repos/permissive/219917900/../majority_top.sv\n             data/full_repos/permissive/219917900/rx_rtl_files/sim,data/full_repos/permissive/219917900/../majority_top.sv.v\n             data/full_repos/permissive/219917900/rx_rtl_files/sim,data/full_repos/permissive/219917900/../majority_top.sv.sv\n             ../majority_top.sv\n             ../majority_top.sv.v\n             ../majority_top.sv.sv\n             obj_dir/../majority_top.sv\n             obj_dir/../majority_top.sv.v\n             obj_dir/../majority_top.sv.sv\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:3: Cannot find include file: ../pkt8to256out.sv\n`include "../pkt8to256out.sv" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:4: Cannot find include file: ../sync_fifo.v\n`include "../sync_fifo.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:5: Cannot find include file: ../super_asyncFIFO.v\n`include "../super_asyncFIFO.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:6: Cannot find include file: ../asyncFIFO_glay.v\n`include "../asyncFIFO_glay.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:30: Unsupported: Ignoring delay on this delayed statement.\n    #(dc/4) dclk = !dclk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:31: Unsupported: Ignoring delay on this delayed statement.\n    #(dc/4);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:34: Unsupported: Ignoring delay on this delayed statement.\n    #1 ui_clk = !ui_clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:35: Unsupported: Ignoring delay on this delayed statement.\n    #(uc/2 - 1);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:46: Unsupported: Ignoring delay on this delayed statement.\n        #dc;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:62: Unsupported: Ignoring delay on this delayed statement.\n            #dc;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:65: Unsupported: Ignoring delay on this delayed statement.\n        #(dc);\n        ^\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:88: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("wf_majority_top.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:89: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,tb_majority_top);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:95: Unsupported: Ignoring delay on this delayed statement.\n    #(dc*25);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:100: Unsupported: Ignoring delay on this delayed statement.\n        #(dc*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:105: Unsupported: Ignoring delay on this delayed statement.\n        #(dc*4);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_majority_top.sv:108: Unsupported: Ignoring delay on this delayed statement.\n    #(dc * 2000);\n    ^\n%Error: Exiting due to 7 error(s), 11 warning(s)\n'
module tb_majority_top;



reg RST,dclk,rx_en;
reg [7:0] rx_data;

reg ui_clk;
wire wr_busy,rd_busy,rd_data_valid;
wire  [255:0] rd_data;
wire wr_en,rd_en;
wire [24:0] wr_addr,rd_addr;
wire [255:0] wr_data;

parameter whereis_segnum = 34;
parameter whereis_id = 36;
localparam packetsize = 101;

localparam dc = 8;
localparam uc = 5;

always begin
    #(dc/4) dclk = !dclk;
    #(dc/4);
end
always begin
    #1 ui_clk = !ui_clk;
    #(uc/2 - 1);
end
integer i;
integer j,k,l;
reg [31:0] seed = 32'hdeadbeef;
task onepacket;
    input [3:0] id;
    input [15:0] segnum;
    input [7:0] incr;

    begin
        #dc;
        rx_en = 1'b1;

        for (i = 0; i < packetsize; i=i+1) begin
            if (i==whereis_id)
                rx_data = {4'd0,id};
            else if (i == whereis_segnum)
                rx_data = segnum[15:8];
            else if (i == whereis_segnum + 1'b1)
                rx_data = segnum[7:0];
            else if (i == packetsize - 1) begin
                rx_data = 8'haa;
            end
            else begin 
                rx_data = i+incr;
                end
            #dc;
        end
        rx_en = 1'b0;
        #(dc);
    end
endtask
majority_top uut (
    .RST(RST),
    .rx_data(rx_data),
    .rx_en(rx_en),
    .dclk(dclk),

    .ui_clk(ui_clk),
    .wr_busy(wr_busy),
    .rd_busy(rd_busy),
    .rd_data(rd_data),
    .rd_data_valid(rd_data_valid),
    .wr_en(wr_en),
    .rd_en(rd_en),
    .wr_data(wr_data),
    .wr_addr(wr_addr),
    .rd_addr(rd_addr)

);

initial begin
    $dumpfile("wf_majority_top.vcd");
    $dumpvars(0,tb_majority_top);
    RST = 'h1;
    rx_data = 'h0;
    rx_en = 'h0;
    dclk = 'h0;
    ui_clk = 'h0;
    #(dc*25);
    RST = 'h0;

    for(i=0;i<5; i=i+1) begin
        l = 0;
        #(dc*2);
        for(j=1; j<=5;j=j+1) begin
            l = l + 1;
            onepacket(j,i,l);
        end
        #(dc*4);
    end

    #(dc * 2000);
    $finish;

end


endmodule
module tb_majority_top;




reg RST,dclk,rx_en;
reg [7:0] rx_data;

reg ui_clk;
wire wr_busy,rd_busy,rd_data_valid;
wire  [255:0] rd_data;
wire wr_en,rd_en;
wire [24:0] wr_addr,rd_addr;
wire [255:0] wr_data;

parameter whereis_segnum = 34;
parameter whereis_id = 36;
localparam packetsize = 101;

localparam dc = 8;
localparam uc = 5;

always begin
    #(dc/4) dclk = !dclk;
    #(dc/4);
end
always begin
    #1 ui_clk = !ui_clk;
    #(uc/2 - 1);
end
integer i;
integer j,k,l;
reg [31:0] seed = 32'hdeadbeef;
task onepacket;
    input [3:0] id;
    input [15:0] segnum;
    input [7:0] incr;

    begin
        #dc;
        rx_en = 1'b1;

        for (i = 0; i < packetsize; i=i+1) begin
            if (i==whereis_id)
                rx_data = {4'd0,id};
            else if (i == whereis_segnum)
                rx_data = segnum[15:8];
            else if (i == whereis_segnum + 1'b1)
                rx_data = segnum[7:0];
            else if (i == packetsize - 1) begin
                rx_data = 8'haa;
            end
            else begin 
                rx_data = i+incr;
                end
            #dc;
        end
        rx_en = 1'b0;
        #(dc);
    end
endtask
majority_top uut (
    .RST(RST),
    .rx_data(rx_data),
    .rx_en(rx_en),
    .dclk(dclk),

    .ui_clk(ui_clk),
    .wr_busy(wr_busy),
    .rd_busy(rd_busy),
    .rd_data(rd_data),
    .rd_data_valid(rd_data_valid),
    .wr_en(wr_en),
    .rd_en(rd_en),
    .wr_data(wr_data),
    .wr_addr(wr_addr),
    .rd_addr(rd_addr)

);

initial begin
    $dumpfile("wf_majority_top.vcd");
    $dumpvars(0,tb_majority_top);
    RST = 'h1;
    rx_data = 'h0;
    rx_en = 'h0;
    dclk = 'h0;
    ui_clk = 'h0;
    #(dc*25);
    RST = 'h0;

    for(i=0;i<5; i=i+1) begin
        l = 0;
        #(dc*2);
        for(j=1; j<=5;j=j+1) begin
            l = l + 1;
            onepacket(j,i,l);
        end
        #(dc*4);
    end

    #(dc * 2000);
    $finish;

end


endmodule