data/full_repos/permissive/110151336/lab_08/src/lab8.v
1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:231: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                          : ... In instance lab8\n    assign hex0 = moore_fsm_out ? 8\'b10100011 : 8\'b11111111;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:232: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                          : ... In instance lab8\n    assign hex1 = mealy_fsm_out ? 8\'b10011100 : 8\'b11111111;\n                ^\n%Error: Exiting due to 2 warning(s)\n'
module lab8
(
    input        clock,
    input        reset_n,
    input        key,
    output [9:0] led,
    output [6:0] hex0,
    output [6:0] hex1
);

    wire       button  = ~ key;
    wire       enable;
    wire [9:0] shift_data;
    wire       shift_out;
    wire       moore_fsm_out;
    wire       mealy_fsm_out;

    timer
    # ( .timer_divider ( 24 ))
    timer_i
    (
        .clock_50_mhz ( clock   ),
        .reset_n      ( reset_n ),
        .strobe       ( enable  )
    );

    shift 
    # ( .width ( 10 ))
    shift_i
    (
        .clock        ( clock      ),
        .reset_n      ( reset_n    ),
        .shift_enable ( enable     ),
        .button       ( button     ),
        .shift_reg    ( shift_data ),
        .out          ( shift_out  )
    );


    pattern_fsm_moore fsm_moore
    (
        .clock   ( clock         ),
        .reset_n ( reset_n       ),
        .enable  ( enable        ),
        .a       ( shift_out     ),
        .y       ( moore_fsm_out )
    );

    pattern_fsm_mealy fsm_mealy
    (
        .clock   ( clock         ),
        .reset_n ( reset_n       ),
        .enable  ( enable        ),
        .a       ( shift_out     ),
        .y       ( mealy_fsm_out )
    );

    assign led = shift_data;
    assign hex0 = moore_fsm_out ? 8'b10100011 : 8'b11111111;
    assign hex1 = mealy_fsm_out ? 8'b10011100 : 8'b11111111;

endmodule
module lab8
(
    input        clock,
    input        reset_n,
    input        key,
    output [9:0] led,
    output [6:0] hex0,
    output [6:0] hex1
);


    wire       button  = ~ key;
    wire       enable;
    wire [9:0] shift_data;
    wire       shift_out;
    wire       moore_fsm_out;
    wire       mealy_fsm_out;

    timer
    # ( .timer_divider ( 24 ))
    timer_i
    (
        .clock_50_mhz ( clock   ),
        .reset_n      ( reset_n ),
        .strobe       ( enable  )
    );

    shift 
    # ( .width ( 10 ))
    shift_i
    (
        .clock        ( clock      ),
        .reset_n      ( reset_n    ),
        .shift_enable ( enable     ),
        .button       ( button     ),
        .shift_reg    ( shift_data ),
        .out          ( shift_out  )
    );


    pattern_fsm_moore fsm_moore
    (
        .clock   ( clock         ),
        .reset_n ( reset_n       ),
        .enable  ( enable        ),
        .a       ( shift_out     ),
        .y       ( moore_fsm_out )
    );

    pattern_fsm_mealy fsm_mealy
    (
        .clock   ( clock         ),
        .reset_n ( reset_n       ),
        .enable  ( enable        ),
        .a       ( shift_out     ),
        .y       ( mealy_fsm_out )
    );

    assign led = shift_data;
    assign hex0 = moore_fsm_out ? 8'b10100011 : 8'b11111111;
    assign hex1 = mealy_fsm_out ? 8'b10011100 : 8'b11111111;

endmodule