data/full_repos/permissive/154123726/3rdParty/simd/do_reduce_full.v
1: b'%Error: data/full_repos/permissive/154123726/3rdParty/simd/do_reduce_full.v:29: Cannot find file containing module: \'do_reduce\'\n do_reduce full_do_reduce({{2{ai[14]}},ai},reduce_out);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/do_reduce\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/do_reduce.v\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/do_reduce.sv\n             do_reduce\n             do_reduce.v\n             do_reduce.sv\n             obj_dir/do_reduce\n             obj_dir/do_reduce.v\n             obj_dir/do_reduce.sv\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/do_reduce_full.v:30: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 15 bits.\n                                                                                      : ... In instance do_reduce_full\n assign diff = reduce_out - 257;  \n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/do_reduce_full.v:31: Operator COND expects 15 bits on the Conditional False, but Conditional False\'s VARREF \'diff\' generates 10 bits.\n                                                                                      : ... In instance do_reduce_full\n assign ao = (reduce_out <= 128) ? reduce_out : diff; \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/do_reduce_full.v:31: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s COND generates 15 bits.\n                                                                                      : ... In instance do_reduce_full\n assign ao = (reduce_out <= 128) ? reduce_out : diff; \n           ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module do_reduce_full(ai, 
					            ao
					            );

	input signed [14:0] ai;
	

	output signed [8:0] ao;
	
	
	wire signed [14:0] reduce_out;
	wire signed [9:0] diff;
	do_reduce full_do_reduce({{2{ai[14]}},ai},reduce_out);
	assign diff = reduce_out - 257;		
	assign ao = (reduce_out <= 128) ? reduce_out : diff;	
endmodule
module do_reduce_full(ai, 
					            ao
					            );


	input signed [14:0] ai;
	

	output signed [8:0] ao;
	
	
	wire signed [14:0] reduce_out;
	wire signed [9:0] diff;
	do_reduce full_do_reduce({{2{ai[14]}},ai},reduce_out);
	assign diff = reduce_out - 257;		
	assign ao = (reduce_out <= 128) ? reduce_out : diff;	
endmodule