data/full_repos/permissive/146618947/valid_tarea6/mux_41_estructural.v
 line:38: before: "*"
data/verilator_xmls/4c622534-7f2d-42c7-8056-e8a22983fafa.xml
module mux_estructural(clk, reset_L, data_0, data_1, valid_0, valid_1, valid_out, data_out);
  (* src = "mux.v:35" *)
  wire [3:0] _00_;
  (* src = "mux.v:35" *)
  wire _01_;
  (* src = "mux.v:21" *)
  wire _02_;
  (* src = "mux.v:45" *)
  wire _03_;
  wire [3:0] _04_;
  wire [3:0] _05_;
  wire [3:0] _06_;
  wire [3:0] _07_;
  (* src = "mux.v:3" *)
  input clk;
  (* src = "mux.v:5" *)
  input [3:0] data_0;
  (* src = "mux.v:6" *)
  input [3:0] data_1;
  (* init = 4'h0 *)
  (* src = "mux.v:10" *)
  output [3:0] data_out;
  reg [3:0] data_out = 4'h0;
  (* src = "mux.v:4" *)
  input reset_L;
  (* init = 1'h0 *)
  (* src = "mux.v:13" *)
  reg selector = 1'h0;
  (* src = "mux.v:7" *)
  input valid_0;
  (* src = "mux.v:8" *)
  input valid_1;
  (* src = "mux.v:9" *)
  output valid_out;
  assign _00_[0] = reset_L ? (* src = "mux.v:44" *) _07_[0] : _04_[0];
  assign _00_[1] = reset_L ? (* src = "mux.v:44" *) _07_[1] : _04_[1];
  assign _00_[2] = reset_L ? (* src = "mux.v:44" *) _07_[2] : _04_[2];
  assign _00_[3] = reset_L ? (* src = "mux.v:44" *) _07_[3] : _04_[3];
  assign _02_ = selector ? (* src = "mux.v:25" *) valid_0 : valid_1;
  assign valid_out = reset_L ? (* src = "mux.v:24" *) _02_ : 1'h0;
  assign _01_ = reset_L ? (* src = "mux.v:44" *) _03_ : 1'h0;
  assign _04_[0] = reset_L ? (* src = "mux.v:38" *) data_out[0] : 1'h0;
  assign _04_[1] = reset_L ? (* src = "mux.v:38" *) data_out[1] : 1'h0;
  assign _04_[2] = reset_L ? (* src = "mux.v:38" *) data_out[2] : 1'h0;
  assign _04_[3] = reset_L ? (* src = "mux.v:38" *) data_out[3] : 1'h0;
  assign _05_[0] = valid_1 ? (* src = "mux.v:51" *) data_1[0] : _04_[0];
  assign _05_[1] = valid_1 ? (* src = "mux.v:51" *) data_1[1] : _04_[1];
  assign _05_[2] = valid_1 ? (* src = "mux.v:51" *) data_1[2] : _04_[2];
  assign _05_[3] = valid_1 ? (* src = "mux.v:51" *) data_1[3] : _04_[3];
  assign _06_[0] = valid_0 ? (* src = "mux.v:47" *) data_0[0] : _04_[0];
  assign _06_[1] = valid_0 ? (* src = "mux.v:47" *) data_0[1] : _04_[1];
  assign _06_[2] = valid_0 ? (* src = "mux.v:47" *) data_0[2] : _04_[2];
  assign _06_[3] = valid_0 ? (* src = "mux.v:47" *) data_0[3] : _04_[3];
  assign _07_[0] = selector ? (* src = "mux.v:46" *) _06_[0] : _05_[0];
  assign _07_[1] = selector ? (* src = "mux.v:46" *) _06_[1] : _05_[1];
  assign _07_[2] = selector ? (* src = "mux.v:46" *) _06_[2] : _05_[2];
  assign _07_[3] = selector ? (* src = "mux.v:46" *) _06_[3] : _05_[3];
  assign _03_ = ~(* src = "mux.v:45" *) selector;
  (* src = "mux.v:35" *)
  always @(posedge clk)
      data_out[0] <= _00_[0];
  (* src = "mux.v:35" *)
  always @(posedge clk)
      data_out[1] <= _00_[1];
  (* src = "mux.v:35" *)
  always @(posedge clk)
      data_out[2] <= _00_[2];
  (* src = "mux.v:35" *)
  always @(posedge clk)
      data_out[3] <= _00_[3];
  (* src = "mux.v:35" *)
  always @(posedge clk)
      selector <= _01_;
endmodule
module mux_estructural(clk, reset_L, data_0, data_1, valid_0, valid_1, valid_out, data_out);

  (* src = "mux.v:35" *)
  wire [3:0] _00_;
  (* src = "mux.v:35" *)
  wire _01_;
  (* src = "mux.v:21" *)
  wire _02_;
  (* src = "mux.v:45" *)
  wire _03_;
  wire [3:0] _04_;
  wire [3:0] _05_;
  wire [3:0] _06_;
  wire [3:0] _07_;
  (* src = "mux.v:3" *)
  input clk;
  (* src = "mux.v:5" *)
  input [3:0] data_0;
  (* src = "mux.v:6" *)
  input [3:0] data_1;
  (* init = 4'h0 *)
  (* src = "mux.v:10" *)
  output [3:0] data_out;
  reg [3:0] data_out = 4'h0;
  (* src = "mux.v:4" *)
  input reset_L;
  (* init = 1'h0 *)
  (* src = "mux.v:13" *)
  reg selector = 1'h0;
  (* src = "mux.v:7" *)
  input valid_0;
  (* src = "mux.v:8" *)
  input valid_1;
  (* src = "mux.v:9" *)
  output valid_out;
  assign _00_[0] = reset_L ? (* src = "mux.v:44" *) _07_[0] : _04_[0];
  assign _00_[1] = reset_L ? (* src = "mux.v:44" *) _07_[1] : _04_[1];
  assign _00_[2] = reset_L ? (* src = "mux.v:44" *) _07_[2] : _04_[2];
  assign _00_[3] = reset_L ? (* src = "mux.v:44" *) _07_[3] : _04_[3];
  assign _02_ = selector ? (* src = "mux.v:25" *) valid_0 : valid_1;
  assign valid_out = reset_L ? (* src = "mux.v:24" *) _02_ : 1'h0;
  assign _01_ = reset_L ? (* src = "mux.v:44" *) _03_ : 1'h0;
  assign _04_[0] = reset_L ? (* src = "mux.v:38" *) data_out[0] : 1'h0;
  assign _04_[1] = reset_L ? (* src = "mux.v:38" *) data_out[1] : 1'h0;
  assign _04_[2] = reset_L ? (* src = "mux.v:38" *) data_out[2] : 1'h0;
  assign _04_[3] = reset_L ? (* src = "mux.v:38" *) data_out[3] : 1'h0;
  assign _05_[0] = valid_1 ? (* src = "mux.v:51" *) data_1[0] : _04_[0];
  assign _05_[1] = valid_1 ? (* src = "mux.v:51" *) data_1[1] : _04_[1];
  assign _05_[2] = valid_1 ? (* src = "mux.v:51" *) data_1[2] : _04_[2];
  assign _05_[3] = valid_1 ? (* src = "mux.v:51" *) data_1[3] : _04_[3];
  assign _06_[0] = valid_0 ? (* src = "mux.v:47" *) data_0[0] : _04_[0];
  assign _06_[1] = valid_0 ? (* src = "mux.v:47" *) data_0[1] : _04_[1];
  assign _06_[2] = valid_0 ? (* src = "mux.v:47" *) data_0[2] : _04_[2];
  assign _06_[3] = valid_0 ? (* src = "mux.v:47" *) data_0[3] : _04_[3];
  assign _07_[0] = selector ? (* src = "mux.v:46" *) _06_[0] : _05_[0];
  assign _07_[1] = selector ? (* src = "mux.v:46" *) _06_[1] : _05_[1];
  assign _07_[2] = selector ? (* src = "mux.v:46" *) _06_[2] : _05_[2];
  assign _07_[3] = selector ? (* src = "mux.v:46" *) _06_[3] : _05_[3];
  assign _03_ = ~(* src = "mux.v:45" *) selector;
  (* src = "mux.v:35" *)
  always @(posedge clk)
      data_out[0] <= _00_[0];
  (* src = "mux.v:35" *)
  always @(posedge clk)
      data_out[1] <= _00_[1];
  (* src = "mux.v:35" *)
  always @(posedge clk)
      data_out[2] <= _00_[2];
  (* src = "mux.v:35" *)
  always @(posedge clk)
      data_out[3] <= _00_[3];
  (* src = "mux.v:35" *)
  always @(posedge clk)
      selector <= _01_;
endmodule