data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v
 line:593: before: ","
1: b'%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:616: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:616: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:619: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_left\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n    out[63:32] <= out_left;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:623: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_right\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n    out[31:0] <= out_right;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:625: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:625: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:628: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  {temp[0], temp[31:1]} = out_left & key_left;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:593: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:593: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:596: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_left\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n    out[63:32] <= out_left;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:600: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_right\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n    out[31:0] <= out_right;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:602: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:602: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:604: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  {temp[0], temp[31:1]} = in_left & key_left;\n                                ^\n%Error: Exiting due to 14 warning(s)\n'
module Camellia_sequencer( Krdy, Drdy, RSTn, EN, CLK, state, round );

  input  CLK, RSTn, EN;
  input  Drdy, Krdy;
  output [3:0] state;
  output [4:0] round;


  parameter ST_IDLE                = 4'h0;
  parameter ST_IDLE_READY          = 4'h1;


  parameter ST_KEY_GET             = 4'h3;
  parameter ST_KEY_F_FUNC          = 4'h4;
  parameter ST_KEY_XOR             = 4'h5;


  parameter ST_RANDOMIZE_GET         = 4'h7;
  parameter ST_RANDOMIZE_INITIAL_XOR = 4'h8;
  parameter ST_RANDOMIZE_FINAL_XOR   = 4'h9;
  parameter ST_RANDOMIZE_F_FUNC      = 4'ha;
  parameter ST_RANDOMIZE_FL_1        = 4'hb;
  parameter ST_RANDOMIZE_FL_2        = 4'hc;

  parameter Enc = 1'b0;
  parameter Dec = 1'b1;

  reg [3:0]    state;
  reg [4:0]    round;

  always @(posedge CLK) begin
    if(RSTn == 1'b0) begin
      state <= ST_IDLE;
      round <= 5'd00;
    end
    else if(EN == 1) begin
      case(state)
	ST_IDLE:
	  if(Krdy == 1'b1)
	    state <= ST_KEY_GET;
	
	ST_IDLE_READY:
	  if(Krdy == 1'b1)
	    state <= ST_KEY_GET;
	  else if(Drdy == 1'b1)
	    state <= ST_RANDOMIZE_GET;

	ST_KEY_GET: begin
	  round <= 5'd01;
	  state <= ST_KEY_F_FUNC;
	end

	ST_KEY_F_FUNC:
	  case(round)
	    5'd02:   state <= ST_KEY_XOR;
	    5'd04:   state <= ST_IDLE_READY;
	    default: round <= round + 1;
	  endcase
	
	ST_KEY_XOR: begin
	  round <= round + 1;
	  state <= ST_KEY_F_FUNC;
	end

	ST_RANDOMIZE_GET: begin
	  round <= 5'd01;
	  state <= ST_RANDOMIZE_INITIAL_XOR;
	end

	ST_RANDOMIZE_INITIAL_XOR: state <= ST_RANDOMIZE_F_FUNC;
	
	ST_RANDOMIZE_F_FUNC:
	  case(round)
	    5'd06:   state <= ST_RANDOMIZE_FL_1;
	    5'd12:   state <= ST_RANDOMIZE_FL_2;
	    5'd18:   state <= ST_RANDOMIZE_FINAL_XOR;
	    default: round <= round + 1;
	  endcase

	ST_RANDOMIZE_FL_1, ST_RANDOMIZE_FL_2: begin
	  round <= round + 1;
	  state <= ST_RANDOMIZE_F_FUNC;
	end
	
	ST_RANDOMIZE_FINAL_XOR: state <= ST_IDLE_READY;
      endcase
    end
  end
endmodule
module Camellia_sequencer( Krdy, Drdy, RSTn, EN, CLK, state, round );


  input  CLK, RSTn, EN;
  input  Drdy, Krdy;
  output [3:0] state;
  output [4:0] round;


  parameter ST_IDLE                = 4'h0;
  parameter ST_IDLE_READY          = 4'h1;


  parameter ST_KEY_GET             = 4'h3;
  parameter ST_KEY_F_FUNC          = 4'h4;
  parameter ST_KEY_XOR             = 4'h5;


  parameter ST_RANDOMIZE_GET         = 4'h7;
  parameter ST_RANDOMIZE_INITIAL_XOR = 4'h8;
  parameter ST_RANDOMIZE_FINAL_XOR   = 4'h9;
  parameter ST_RANDOMIZE_F_FUNC      = 4'ha;
  parameter ST_RANDOMIZE_FL_1        = 4'hb;
  parameter ST_RANDOMIZE_FL_2        = 4'hc;

  parameter Enc = 1'b0;
  parameter Dec = 1'b1;

  reg [3:0]    state;
  reg [4:0]    round;

  always @(posedge CLK) begin
    if(RSTn == 1'b0) begin
      state <= ST_IDLE;
      round <= 5'd00;
    end
    else if(EN == 1) begin
      case(state)
	ST_IDLE:
	  if(Krdy == 1'b1)
	    state <= ST_KEY_GET;
	
	ST_IDLE_READY:
	  if(Krdy == 1'b1)
	    state <= ST_KEY_GET;
	  else if(Drdy == 1'b1)
	    state <= ST_RANDOMIZE_GET;

	ST_KEY_GET: begin
	  round <= 5'd01;
	  state <= ST_KEY_F_FUNC;
	end

	ST_KEY_F_FUNC:
	  case(round)
	    5'd02:   state <= ST_KEY_XOR;
	    5'd04:   state <= ST_IDLE_READY;
	    default: round <= round + 1;
	  endcase
	
	ST_KEY_XOR: begin
	  round <= round + 1;
	  state <= ST_KEY_F_FUNC;
	end

	ST_RANDOMIZE_GET: begin
	  round <= 5'd01;
	  state <= ST_RANDOMIZE_INITIAL_XOR;
	end

	ST_RANDOMIZE_INITIAL_XOR: state <= ST_RANDOMIZE_F_FUNC;
	
	ST_RANDOMIZE_F_FUNC:
	  case(round)
	    5'd06:   state <= ST_RANDOMIZE_FL_1;
	    5'd12:   state <= ST_RANDOMIZE_FL_2;
	    5'd18:   state <= ST_RANDOMIZE_FINAL_XOR;
	    default: round <= round + 1;
	  endcase

	ST_RANDOMIZE_FL_1, ST_RANDOMIZE_FL_2: begin
	  round <= round + 1;
	  state <= ST_RANDOMIZE_F_FUNC;
	end
	
	ST_RANDOMIZE_FINAL_XOR: state <= ST_IDLE_READY;
      endcase
    end
  end
endmodule