data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/top.sv
 line:154: before: "*"
data/verilator_xmls/6d4d6c1a-9578-4059-8d92-7bd9bd1e27a3.xml
module top
# (
    parameter width = 8
)
(
    input                    clock,
    input                    reset_n,

    input      [width - 1:0] up_data,
    input                    up_valid,
    output                   up_ready,

    output     [width - 1:0] down_data,
    output                   down_valid,
    input                    down_ready
);

    pipeline_stomach      # (.width (width))
    pipeline_stomach_inst (.*);


endmodule
module top
# (
    parameter width = 8
)
(
    input                    clock,
    input                    reset_n,

    input      [width - 1:0] up_data,
    input                    up_valid,
    output                   up_ready,

    output     [width - 1:0] down_data,
    output                   down_valid,
    input                    down_ready
);


    pipeline_stomach      # (.width (width))
    pipeline_stomach_inst (.*);


endmodule