data/full_repos/permissive/106583614/Final_project_divider/Div_mod_top_level.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/106583614/Final_project_divider/Div_mod_top_level.v:30: Operator COND expects 32 or 17 bits on the Conditional False, but Conditional False\'s VARREF \'mod_res\' generates 16 bits.\n                                                                                                 : ... In instance Div_mod_top_level\n assign final_output = (valid_output) ? ((mode) ? div_res : mod_res) : \'b0;\n                                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106583614/Final_project_divider/Div_mod_top_level.v:32: Cannot find file containing module: \'interconect_cells\'\n interconect_cells connected_cells \n ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106583614/Final_project_divider,data/full_repos/permissive/106583614/interconect_cells\n             data/full_repos/permissive/106583614/Final_project_divider,data/full_repos/permissive/106583614/interconect_cells.v\n             data/full_repos/permissive/106583614/Final_project_divider,data/full_repos/permissive/106583614/interconect_cells.sv\n             interconect_cells\n             interconect_cells.v\n             interconect_cells.sv\n             obj_dir/interconect_cells\n             obj_dir/interconect_cells.v\n             obj_dir/interconect_cells.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module Div_mod_top_level(
	clk,
	reset,
	divisor,
	dividend,
	mode,
	valid_input,
	valid_output,
	final_output
);

	input signed [31:0] dividend;
	input signed [15:0] divisor;

	input clk, reset;
	input valid_input, mode;

	output valid_output;
	output signed [16:0] final_output;

	wire signed [16:0] div_res;
	wire signed [15:0] mod_res;


	assign final_output = (valid_output) ? ((mode) ? div_res : mod_res) : 'b0;

	interconect_cells connected_cells 
	(
		.clk(clk) ,
		.reset(reset) ,
		.in_divisor(divisor),
		.in_dividend(dividend),
		.valid_input(valid_input),
		.valid_output(valid_output),
		.mod_res(mod_res),
		.div_res_tmp(div_res)
	);


endmodule
module Div_mod_top_level(
	clk,
	reset,
	divisor,
	dividend,
	mode,
	valid_input,
	valid_output,
	final_output
);


	input signed [31:0] dividend;
	input signed [15:0] divisor;

	input clk, reset;
	input valid_input, mode;

	output valid_output;
	output signed [16:0] final_output;

	wire signed [16:0] div_res;
	wire signed [15:0] mod_res;


	assign final_output = (valid_output) ? ((mode) ? div_res : mod_res) : 'b0;

	interconect_cells connected_cells 
	(
		.clk(clk) ,
		.reset(reset) ,
		.in_divisor(divisor),
		.in_dividend(dividend),
		.valid_input(valid_input),
		.valid_output(valid_output),
		.mod_res(mod_res),
		.div_res_tmp(div_res)
	);


endmodule