data/full_repos/permissive/189415563/FSM_Controlled.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:37: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance DCT\nreg signed [FACTOR_SIGNED_WIDTH - 1:0] C1 = 4\'d15,\n                                            ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:38: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'he\' generates 4 bits.\n                                                                        : ... In instance DCT\n    C2 = 4\'d14,\n         ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:39: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hd\' generates 4 bits.\n                                                                        : ... In instance DCT\n    C3 = 4\'d13,\n         ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:40: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hb\' generates 4 bits.\n                                                                        : ... In instance DCT\n    C4 = 4\'d11,\n         ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:41: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h9\' generates 4 bits.\n                                                                        : ... In instance DCT\n    C5 = 4\'d9,\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:42: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h6\' generates 4 bits.\n                                                                        : ... In instance DCT\n    C6 = 4\'d6,\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:43: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h3\' generates 4 bits.\n                                                                        : ... In instance DCT\n    C7 = 4\'d3;\n         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:94: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                        : ... In instance DCT\n      data_out0 <= 16\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:95: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                        : ... In instance DCT\n      data_out1 <= 16\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:96: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                        : ... In instance DCT\n      data_out2 <= 16\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:97: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                        : ... In instance DCT\n      data_out3 <= 16\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:98: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                        : ... In instance DCT\n      data_out4 <= 16\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:99: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                        : ... In instance DCT\n      data_out5 <= 16\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:100: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n      data_out6 <= 16\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:101: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n      data_out7 <= 16\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:103: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n     M0 <= 9\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:104: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n     M1 <= 9\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:105: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n     M2 <= 9\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:106: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n     M3 <= 9\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:107: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n     P0 <= 9\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:108: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n     P1 <= 9\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:109: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n     P2 <= 9\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:110: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n     P3 <= 9\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:113: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance DCT\n     M03 <= 10\'b0;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:114: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance DCT\n     M12 <= 10\'b0;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:115: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance DCT\n     P03 <= 10\'b0;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:116: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance DCT\n     P12 <= 10\'b0;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:119: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                         : ... In instance DCT\n     M4 <= 11\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:120: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                         : ... In instance DCT\n     P4 <= 11\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:123: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[0]  <= 16\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:124: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[1]  <= 16\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:125: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[2]  <= 16\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:126: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[3]  <= 16\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:127: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[4]  <= 16\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:128: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[5]  <= 16\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:129: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[6]  <= 16\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:130: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[7]  <= 16\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:131: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[8]  <= 16\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:132: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[9]  <= 16\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:133: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[10]  <= 16\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:134: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[11]  <= 16\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:135: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[12]  <= 16\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:136: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[13]  <= 16\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:137: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[14]  <= 16\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:138: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[15]  <= 16\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:139: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[16]  <= 16\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:140: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[17]  <= 16\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:141: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[18]  <= 16\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:142: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[19]  <= 16\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:143: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[20]  <= 16\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:144: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n     tempMultiply[21]  <= 16\'b0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:152: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out0 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:153: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out1 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:154: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out2 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:155: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out3 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:156: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out4 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:157: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out5 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:158: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out6 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:159: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out7 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:161: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        M0 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:162: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        M1 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:163: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        M2 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:164: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        M3 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:165: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        P0 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:166: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        P1 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:167: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        P2 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:168: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        P3 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:171: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance DCT\n        M03 <= 10\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:172: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance DCT\n        M12 <= 10\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:173: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance DCT\n        P03 <= 10\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:174: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance DCT\n        P12 <= 10\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:178: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                         : ... In instance DCT\n        M4 <= 11\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:179: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                         : ... In instance DCT\n        P4 <= 11\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:182: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[0]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:183: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[1]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:184: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[2]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:185: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[3]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:186: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[4]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:187: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[5]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:188: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[6]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:189: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[7]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:190: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[8]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:191: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[9]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:192: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[10]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:193: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[11]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:194: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[12]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:195: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[13]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:196: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[14]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:197: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[15]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:198: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[16]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:199: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[17]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:200: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[18]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:201: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[19]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:202: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[20]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:203: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[21]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:260: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg0  <= tempMultiply[0];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:261: Operator ADD expects 19 bits on the LHS, but LHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg1  <= tempMultiply[1] + tempMultiply[2] + tempMultiply[3] + tempMultiply[4];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:261: Operator ADD expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg1  <= tempMultiply[1] + tempMultiply[2] + tempMultiply[3] + tempMultiply[4];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:261: Operator ADD expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg1  <= tempMultiply[1] + tempMultiply[2] + tempMultiply[3] + tempMultiply[4];\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:261: Operator ADD expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg1  <= tempMultiply[1] + tempMultiply[2] + tempMultiply[3] + tempMultiply[4];\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:262: Operator ADD expects 19 bits on the LHS, but LHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg2  <= tempMultiply[5] + tempMultiply[6];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:262: Operator ADD expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg2  <= tempMultiply[5] + tempMultiply[6];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:263: Operator SUB expects 19 bits on the LHS, but LHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg3  <= tempMultiply[7] - tempMultiply[8] - tempMultiply[9] - tempMultiply[10];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:263: Operator SUB expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg3  <= tempMultiply[7] - tempMultiply[8] - tempMultiply[9] - tempMultiply[10];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:263: Operator SUB expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg3  <= tempMultiply[7] - tempMultiply[8] - tempMultiply[9] - tempMultiply[10];\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:263: Operator SUB expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg3  <= tempMultiply[7] - tempMultiply[8] - tempMultiply[9] - tempMultiply[10];\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:264: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg4  <= tempMultiply[11];\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:265: Operator SUB expects 19 bits on the LHS, but LHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg5  <= tempMultiply[12] - tempMultiply[13] + tempMultiply[14] + tempMultiply[15];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:265: Operator SUB expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg5  <= tempMultiply[12] - tempMultiply[13] + tempMultiply[14] + tempMultiply[15];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:265: Operator ADD expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg5  <= tempMultiply[12] - tempMultiply[13] + tempMultiply[14] + tempMultiply[15];\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:265: Operator ADD expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg5  <= tempMultiply[12] - tempMultiply[13] + tempMultiply[14] + tempMultiply[15];\n                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:266: Operator SUB expects 19 bits on the LHS, but LHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg6  <= tempMultiply[16] - tempMultiply[17];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:266: Operator SUB expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg6  <= tempMultiply[16] - tempMultiply[17];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:267: Operator SUB expects 19 bits on the LHS, but LHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg7  <= tempMultiply[18] - tempMultiply[19] + tempMultiply[20] - tempMultiply[21];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:267: Operator SUB expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg7  <= tempMultiply[18] - tempMultiply[19] + tempMultiply[20] - tempMultiply[21];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:267: Operator ADD expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg7  <= tempMultiply[18] - tempMultiply[19] + tempMultiply[20] - tempMultiply[21];\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:267: Operator SUB expects 19 bits on the RHS, but RHS\'s ARRAYSEL generates 17 bits.\n                                                                         : ... In instance DCT\n        data_out_reg7  <= tempMultiply[18] - tempMultiply[19] + tempMultiply[20] - tempMultiply[21];\n                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:283: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out0 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:284: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out1 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:285: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out2 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:286: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out3 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:287: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out4 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:288: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out5 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:289: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out6 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:290: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n         data_out7 <= 16\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:292: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        M0 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:293: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        M1 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:294: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        M2 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:295: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        M3 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:296: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        P0 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:297: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        P1 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:298: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        P2 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:299: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DCT\n        P3 <= 9\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:302: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance DCT\n        M03 <= 10\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:303: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance DCT\n        M12 <= 10\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:304: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance DCT\n        P03 <= 10\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:305: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance DCT\n        P12 <= 10\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:309: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                         : ... In instance DCT\n        M4 <= 11\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:310: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                         : ... In instance DCT\n        P4 <= 11\'b0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:313: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[0]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:314: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[1]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:315: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[2]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:316: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[3]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:317: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[4]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:318: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[5]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:319: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[6]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:320: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[7]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:321: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[8]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:322: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[9]  <= 16\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:323: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[10]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:324: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[11]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:325: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[12]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:326: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[13]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:327: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[14]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:328: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[15]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:329: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[16]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:330: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[17]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:331: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[18]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:332: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[19]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:333: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[20]  <= 16\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/189415563/FSM_Controlled.v:334: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                         : ... In instance DCT\n        tempMultiply[21]  <= 16\'b0;\n                          ^~\n%Error: Exiting due to 161 warning(s)\n'
module DCT(clk,rst_n,ena,done,pipe0,pipe1,pipe2,pipe3,
			data_in0,data_in1,data_in2,data_in3,data_in4,data_in5,data_in6,data_in7,
			data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7,
			M0,M1,M2,M3,P0,P1,P2,P3,M03,M12,P03,P12,M4,P4);

parameter DATA_IN_WIDTH = 8;
parameter DATA_IN_SIGNED_WIDTH = DATA_IN_WIDTH + 1'b1;
parameter FACTOR_WIDTH = 4;
parameter FACTOR_SIGNED_WIDTH = FACTOR_WIDTH + 1'b1;
parameter TEMP_MULTIPLY_SIGNED_WIDTH = 17;
parameter DATA_OUT_SIGNED_WIDTH = 19;

input clk,rst_n,ena;
input signed [DATA_IN_SIGNED_WIDTH - 1:0] data_in0,data_in1,data_in2,data_in3,data_in4,data_in5,data_in6,data_in7;
output signed [DATA_OUT_SIGNED_WIDTH - 1:0] data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7;
output done;
output pipe0,pipe1,pipe2,pipe3;

output signed [DATA_IN_SIGNED_WIDTH :0] M0,M1,M2,M3,P0,P1,P2,P3;
output signed [DATA_IN_SIGNED_WIDTH + 1:0] M03,M12,P03,P12;
output signed [DATA_IN_SIGNED_WIDTH + 2:0] M4,P4;

reg signed [DATA_OUT_SIGNED_WIDTH - 1:0] data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7;
reg signed [DATA_OUT_SIGNED_WIDTH - 1:0] data_out_reg0,data_out_reg1,data_out_reg2,data_out_reg3,
			 data_out_reg4,data_out_reg5,data_out_reg6,data_out_reg7;
reg done;

reg signed [DATA_IN_SIGNED_WIDTH :0] M0,M1,M2,M3,P0,P1,P2,P3;
reg signed [DATA_IN_SIGNED_WIDTH + 1:0] M03,M12,P03,P12;
reg signed [DATA_IN_SIGNED_WIDTH + 2:0] M4,P4;
reg signed [TEMP_MULTIPLY_SIGNED_WIDTH - 1:0] tempMultiply[21:0];
reg pipe0;
reg pipe1;
reg pipe2;
reg pipe3;

reg signed [FACTOR_SIGNED_WIDTH - 1:0]	C1 = 4'd15,
				C2 = 4'd14,
				C3 = 4'd13,
				C4 = 4'd11,
				C5 = 4'd9,
				C6 = 4'd6,
				C7 = 4'd3;

	localparam 		IDLE		= 3'b011;
	localparam 		STAGE1 		= 3'b001;
	localparam 		STAGE2		= 3'b010;
	localparam		STAGE3		= 3'b111;
	localparam 		STAGE4 		= 3'b100;
	localparam 		STAGE5 		= 3'b101;
	localparam 		STAGE6 		= 3'b110;
	reg [2:0] current_state = 3'b000;
	reg [2:0] next_state = 3'b000;


	always @(posedge clk or negedge rst_n)
		begin
			if (!rst_n)
				current_state <= IDLE;
			else
				current_state <= next_state;
		end
	
	always @ (rst_n,current_state,ena,data_in0,data_in1,data_in2,data_in3,data_in4,data_in5,data_in6,data_in7)
		begin
			if (!rst_n)
				next_state = IDLE;
			else
				case(current_state)
					IDLE:	
						if (ena)
							next_state = STAGE1;
					STAGE1:
							next_state = STAGE2;
					STAGE2:
							next_state = STAGE3;
					STAGE3:
							next_state = STAGE4;
					STAGE4:
							next_state = STAGE5;
					STAGE5:
							next_state = STAGE6;
					STAGE6:
							next_state = IDLE;
					default:
							next_state = IDLE;
				endcase
		end
		
	always @(posedge clk or negedge rst_n)
		begin
			if (!rst_n)
				begin
				  data_out0 <= 16'b0;
				  data_out1 <= 16'b0;
				  data_out2 <= 16'b0;
				  data_out3 <= 16'b0;
				  data_out4 <= 16'b0;
				  data_out5 <= 16'b0;
				  data_out6 <= 16'b0;
				  data_out7 <= 16'b0;
				  
				 M0 <= 9'b0;
				 M1 <= 9'b0;
				 M2 <= 9'b0;
				 M3 <= 9'b0;
				 P0 <= 9'b0;
				 P1 <= 9'b0;
				 P2 <= 9'b0;
				 P3 <= 9'b0;
				 pipe0 <= 0;
				 
				 M03 <= 10'b0;
				 M12 <= 10'b0;
				 P03 <= 10'b0;
				 P12 <= 10'b0;
				 pipe1 <= 0;

				 M4 <= 11'b0;
				 P4 <= 11'b0;
				 pipe2 <= 0;
				 
				 tempMultiply[0]  <= 16'b0;
				 tempMultiply[1]  <= 16'b0;
				 tempMultiply[2]  <= 16'b0;
				 tempMultiply[3]  <= 16'b0;
				 tempMultiply[4]  <= 16'b0;
				 tempMultiply[5]  <= 16'b0;
				 tempMultiply[6]  <= 16'b0;
				 tempMultiply[7]  <= 16'b0;
				 tempMultiply[8]  <= 16'b0;
				 tempMultiply[9]  <= 16'b0;
				 tempMultiply[10]  <= 16'b0;
				 tempMultiply[11]  <= 16'b0;
				 tempMultiply[12]  <= 16'b0;
				 tempMultiply[13]  <= 16'b0;
				 tempMultiply[14]  <= 16'b0;
				 tempMultiply[15]  <= 16'b0;
				 tempMultiply[16]  <= 16'b0;
				 tempMultiply[17]  <= 16'b0;
				 tempMultiply[18]  <= 16'b0;
				 tempMultiply[19]  <= 16'b0;
				 tempMultiply[20]  <= 16'b0;
				 tempMultiply[21]  <= 16'b0;
				 pipe3 <= 0;
				end
			else
				begin
					case(current_state)
						IDLE:
							begin
							  data_out0 <= 16'b0;
							  data_out1 <= 16'b0;
							  data_out2 <= 16'b0;
							  data_out3 <= 16'b0;
							  data_out4 <= 16'b0;
							  data_out5 <= 16'b0;
							  data_out6 <= 16'b0;
							  data_out7 <= 16'b0;
							  
							 M0 <= 9'b0;
							 M1 <= 9'b0;
							 M2 <= 9'b0;
							 M3 <= 9'b0;
							 P0 <= 9'b0;
							 P1 <= 9'b0;
							 P2 <= 9'b0;
							 P3 <= 9'b0;
							 pipe0 <= 0;
							 
							 M03 <= 10'b0;
							 M12 <= 10'b0;
							 P03 <= 10'b0;
							 P12 <= 10'b0;
							 pipe1 <= 0;
							 
							 
							 M4 <= 11'b0;
							 P4 <= 11'b0;
							 pipe2 <= 0;
							 
							 tempMultiply[0]  <= 16'b0;
							 tempMultiply[1]  <= 16'b0;
							 tempMultiply[2]  <= 16'b0;
							 tempMultiply[3]  <= 16'b0;
							 tempMultiply[4]  <= 16'b0;
							 tempMultiply[5]  <= 16'b0;
							 tempMultiply[6]  <= 16'b0;
							 tempMultiply[7]  <= 16'b0;
							 tempMultiply[8]  <= 16'b0;
							 tempMultiply[9]  <= 16'b0;
							 tempMultiply[10]  <= 16'b0;
							 tempMultiply[11]  <= 16'b0;
							 tempMultiply[12]  <= 16'b0;
							 tempMultiply[13]  <= 16'b0;
							 tempMultiply[14]  <= 16'b0;
							 tempMultiply[15]  <= 16'b0;
							 tempMultiply[16]  <= 16'b0;
							 tempMultiply[17]  <= 16'b0;
							 tempMultiply[18]  <= 16'b0;
							 tempMultiply[19]  <= 16'b0;
							 tempMultiply[20]  <= 16'b0;
							 tempMultiply[21]  <= 16'b0;
							 pipe3 <= 0;
							end
						STAGE1:
							begin
								 M0 <= data_in0 - data_in7;
								 M1 <= data_in1 - data_in6;
								 M2 <= data_in2 - data_in5;
								 M3 <= data_in3 - data_in4;
								 P0 <= data_in0 + data_in7;
								 P1 <= data_in1 + data_in6;
								 P2 <= data_in2 + data_in5;
								 P3 <= data_in3 + data_in4;
								 pipe0 <= 1;
							end
						STAGE2:
							begin
								 M03 <= P0 - P3;
								 M12 <= P1 - P2;
								 P03 <= P0 + P3;
								 P12 <= P1 + P2;
								 pipe1 <= 1;
							end
						STAGE3:
							begin
							  M4 <= P03 - P12;
							  P4 <= P03 + P12;
							  pipe2 <= 1;
							end
						STAGE4:
							begin
							 tempMultiply[0]  <= P4*C4;
							 tempMultiply[1]  <= M0*C1;
							 tempMultiply[2]  <= M1*C3;
							 tempMultiply[3]  <= M2*C5;
							 tempMultiply[4]  <= M3*C7;
							 tempMultiply[5]  <= M03*C2;
							 tempMultiply[6]  <= M12*C6;
							 tempMultiply[7]  <= M0*C3;
							 tempMultiply[8]  <= M1*C7;
							 tempMultiply[9]  <= M2*C1;
							 tempMultiply[10]  <= M3*C5;
							 tempMultiply[11]  <= M4*C4;
							 tempMultiply[12]  <= M0*C5;
							 tempMultiply[13]  <= M1*C1;
							 tempMultiply[14]  <= M2*C7;
							 tempMultiply[15]  <= M3*C3;
							 tempMultiply[16]  <= M03*C6;
							 tempMultiply[17]  <= M12*C2;
							 tempMultiply[18]  <= M0*C7;
							 tempMultiply[19]  <= M1*C5;
							 tempMultiply[20]  <= M2*C3;
							 tempMultiply[21]  <= M3*C1;
							 pipe3 <= 1;
							end
						STAGE5:	
							begin
							 data_out_reg0  <= tempMultiply[0];
							 data_out_reg1  <= tempMultiply[1] + tempMultiply[2] + tempMultiply[3] + tempMultiply[4];
							 data_out_reg2  <= tempMultiply[5] + tempMultiply[6];
							 data_out_reg3  <= tempMultiply[7] - tempMultiply[8] - tempMultiply[9] - tempMultiply[10];
							 data_out_reg4  <= tempMultiply[11];
							 data_out_reg5  <= tempMultiply[12] - tempMultiply[13] + tempMultiply[14] + tempMultiply[15];
							 data_out_reg6  <= tempMultiply[16] - tempMultiply[17];
							 data_out_reg7  <= tempMultiply[18] - tempMultiply[19] + tempMultiply[20] - tempMultiply[21];
							 done <= 1;
							end	
						STAGE6:
							begin
							 data_out0 <= data_out_reg0;
							 data_out1 <= data_out_reg1;
							 data_out2 <= data_out_reg2;
							 data_out3 <= data_out_reg3;
							 data_out4 <= data_out_reg4;
							 data_out5 <= data_out_reg5;
							 data_out6 <= data_out_reg6;
							 data_out7 <= data_out_reg7;
							end
						default:
							begin
							  data_out0 <= 16'b0;
							  data_out1 <= 16'b0;
							  data_out2 <= 16'b0;
							  data_out3 <= 16'b0;
							  data_out4 <= 16'b0;
							  data_out5 <= 16'b0;
							  data_out6 <= 16'b0;
							  data_out7 <= 16'b0;
							  
							 M0 <= 9'b0;
							 M1 <= 9'b0;
							 M2 <= 9'b0;
							 M3 <= 9'b0;
							 P0 <= 9'b0;
							 P1 <= 9'b0;
							 P2 <= 9'b0;
							 P3 <= 9'b0;
							 pipe0 <= 0;
							 
							 M03 <= 10'b0;
							 M12 <= 10'b0;
							 P03 <= 10'b0;
							 P12 <= 10'b0;
							 pipe1 <= 0;
							 
							 
							 M4 <= 11'b0;
							 P4 <= 11'b0;
							 pipe2 <= 0;
							 
							 tempMultiply[0]  <= 16'b0;
							 tempMultiply[1]  <= 16'b0;
							 tempMultiply[2]  <= 16'b0;
							 tempMultiply[3]  <= 16'b0;
							 tempMultiply[4]  <= 16'b0;
							 tempMultiply[5]  <= 16'b0;
							 tempMultiply[6]  <= 16'b0;
							 tempMultiply[7]  <= 16'b0;
							 tempMultiply[8]  <= 16'b0;
							 tempMultiply[9]  <= 16'b0;
							 tempMultiply[10]  <= 16'b0;
							 tempMultiply[11]  <= 16'b0;
							 tempMultiply[12]  <= 16'b0;
							 tempMultiply[13]  <= 16'b0;
							 tempMultiply[14]  <= 16'b0;
							 tempMultiply[15]  <= 16'b0;
							 tempMultiply[16]  <= 16'b0;
							 tempMultiply[17]  <= 16'b0;
							 tempMultiply[18]  <= 16'b0;
							 tempMultiply[19]  <= 16'b0;
							 tempMultiply[20]  <= 16'b0;
							 tempMultiply[21]  <= 16'b0;
							 pipe3 <= 0;
							end
					endcase
				end
		end

endmodule
module DCT(clk,rst_n,ena,done,pipe0,pipe1,pipe2,pipe3,
			data_in0,data_in1,data_in2,data_in3,data_in4,data_in5,data_in6,data_in7,
			data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7,
			M0,M1,M2,M3,P0,P1,P2,P3,M03,M12,P03,P12,M4,P4);


parameter DATA_IN_WIDTH = 8;
parameter DATA_IN_SIGNED_WIDTH = DATA_IN_WIDTH + 1'b1;
parameter FACTOR_WIDTH = 4;
parameter FACTOR_SIGNED_WIDTH = FACTOR_WIDTH + 1'b1;
parameter TEMP_MULTIPLY_SIGNED_WIDTH = 17;
parameter DATA_OUT_SIGNED_WIDTH = 19;

input clk,rst_n,ena;
input signed [DATA_IN_SIGNED_WIDTH - 1:0] data_in0,data_in1,data_in2,data_in3,data_in4,data_in5,data_in6,data_in7;
output signed [DATA_OUT_SIGNED_WIDTH - 1:0] data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7;
output done;
output pipe0,pipe1,pipe2,pipe3;

output signed [DATA_IN_SIGNED_WIDTH :0] M0,M1,M2,M3,P0,P1,P2,P3;
output signed [DATA_IN_SIGNED_WIDTH + 1:0] M03,M12,P03,P12;
output signed [DATA_IN_SIGNED_WIDTH + 2:0] M4,P4;

reg signed [DATA_OUT_SIGNED_WIDTH - 1:0] data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7;
reg signed [DATA_OUT_SIGNED_WIDTH - 1:0] data_out_reg0,data_out_reg1,data_out_reg2,data_out_reg3,
			 data_out_reg4,data_out_reg5,data_out_reg6,data_out_reg7;
reg done;

reg signed [DATA_IN_SIGNED_WIDTH :0] M0,M1,M2,M3,P0,P1,P2,P3;
reg signed [DATA_IN_SIGNED_WIDTH + 1:0] M03,M12,P03,P12;
reg signed [DATA_IN_SIGNED_WIDTH + 2:0] M4,P4;
reg signed [TEMP_MULTIPLY_SIGNED_WIDTH - 1:0] tempMultiply[21:0];
reg pipe0;
reg pipe1;
reg pipe2;
reg pipe3;

reg signed [FACTOR_SIGNED_WIDTH - 1:0]	C1 = 4'd15,
				C2 = 4'd14,
				C3 = 4'd13,
				C4 = 4'd11,
				C5 = 4'd9,
				C6 = 4'd6,
				C7 = 4'd3;

	localparam 		IDLE		= 3'b011;
	localparam 		STAGE1 		= 3'b001;
	localparam 		STAGE2		= 3'b010;
	localparam		STAGE3		= 3'b111;
	localparam 		STAGE4 		= 3'b100;
	localparam 		STAGE5 		= 3'b101;
	localparam 		STAGE6 		= 3'b110;
	reg [2:0] current_state = 3'b000;
	reg [2:0] next_state = 3'b000;


	always @(posedge clk or negedge rst_n)
		begin
			if (!rst_n)
				current_state <= IDLE;
			else
				current_state <= next_state;
		end
	
	always @ (rst_n,current_state,ena,data_in0,data_in1,data_in2,data_in3,data_in4,data_in5,data_in6,data_in7)
		begin
			if (!rst_n)
				next_state = IDLE;
			else
				case(current_state)
					IDLE:	
						if (ena)
							next_state = STAGE1;
					STAGE1:
							next_state = STAGE2;
					STAGE2:
							next_state = STAGE3;
					STAGE3:
							next_state = STAGE4;
					STAGE4:
							next_state = STAGE5;
					STAGE5:
							next_state = STAGE6;
					STAGE6:
							next_state = IDLE;
					default:
							next_state = IDLE;
				endcase
		end
		
	always @(posedge clk or negedge rst_n)
		begin
			if (!rst_n)
				begin
				  data_out0 <= 16'b0;
				  data_out1 <= 16'b0;
				  data_out2 <= 16'b0;
				  data_out3 <= 16'b0;
				  data_out4 <= 16'b0;
				  data_out5 <= 16'b0;
				  data_out6 <= 16'b0;
				  data_out7 <= 16'b0;
				  
				 M0 <= 9'b0;
				 M1 <= 9'b0;
				 M2 <= 9'b0;
				 M3 <= 9'b0;
				 P0 <= 9'b0;
				 P1 <= 9'b0;
				 P2 <= 9'b0;
				 P3 <= 9'b0;
				 pipe0 <= 0;
				 
				 M03 <= 10'b0;
				 M12 <= 10'b0;
				 P03 <= 10'b0;
				 P12 <= 10'b0;
				 pipe1 <= 0;

				 M4 <= 11'b0;
				 P4 <= 11'b0;
				 pipe2 <= 0;
				 
				 tempMultiply[0]  <= 16'b0;
				 tempMultiply[1]  <= 16'b0;
				 tempMultiply[2]  <= 16'b0;
				 tempMultiply[3]  <= 16'b0;
				 tempMultiply[4]  <= 16'b0;
				 tempMultiply[5]  <= 16'b0;
				 tempMultiply[6]  <= 16'b0;
				 tempMultiply[7]  <= 16'b0;
				 tempMultiply[8]  <= 16'b0;
				 tempMultiply[9]  <= 16'b0;
				 tempMultiply[10]  <= 16'b0;
				 tempMultiply[11]  <= 16'b0;
				 tempMultiply[12]  <= 16'b0;
				 tempMultiply[13]  <= 16'b0;
				 tempMultiply[14]  <= 16'b0;
				 tempMultiply[15]  <= 16'b0;
				 tempMultiply[16]  <= 16'b0;
				 tempMultiply[17]  <= 16'b0;
				 tempMultiply[18]  <= 16'b0;
				 tempMultiply[19]  <= 16'b0;
				 tempMultiply[20]  <= 16'b0;
				 tempMultiply[21]  <= 16'b0;
				 pipe3 <= 0;
				end
			else
				begin
					case(current_state)
						IDLE:
							begin
							  data_out0 <= 16'b0;
							  data_out1 <= 16'b0;
							  data_out2 <= 16'b0;
							  data_out3 <= 16'b0;
							  data_out4 <= 16'b0;
							  data_out5 <= 16'b0;
							  data_out6 <= 16'b0;
							  data_out7 <= 16'b0;
							  
							 M0 <= 9'b0;
							 M1 <= 9'b0;
							 M2 <= 9'b0;
							 M3 <= 9'b0;
							 P0 <= 9'b0;
							 P1 <= 9'b0;
							 P2 <= 9'b0;
							 P3 <= 9'b0;
							 pipe0 <= 0;
							 
							 M03 <= 10'b0;
							 M12 <= 10'b0;
							 P03 <= 10'b0;
							 P12 <= 10'b0;
							 pipe1 <= 0;
							 
							 
							 M4 <= 11'b0;
							 P4 <= 11'b0;
							 pipe2 <= 0;
							 
							 tempMultiply[0]  <= 16'b0;
							 tempMultiply[1]  <= 16'b0;
							 tempMultiply[2]  <= 16'b0;
							 tempMultiply[3]  <= 16'b0;
							 tempMultiply[4]  <= 16'b0;
							 tempMultiply[5]  <= 16'b0;
							 tempMultiply[6]  <= 16'b0;
							 tempMultiply[7]  <= 16'b0;
							 tempMultiply[8]  <= 16'b0;
							 tempMultiply[9]  <= 16'b0;
							 tempMultiply[10]  <= 16'b0;
							 tempMultiply[11]  <= 16'b0;
							 tempMultiply[12]  <= 16'b0;
							 tempMultiply[13]  <= 16'b0;
							 tempMultiply[14]  <= 16'b0;
							 tempMultiply[15]  <= 16'b0;
							 tempMultiply[16]  <= 16'b0;
							 tempMultiply[17]  <= 16'b0;
							 tempMultiply[18]  <= 16'b0;
							 tempMultiply[19]  <= 16'b0;
							 tempMultiply[20]  <= 16'b0;
							 tempMultiply[21]  <= 16'b0;
							 pipe3 <= 0;
							end
						STAGE1:
							begin
								 M0 <= data_in0 - data_in7;
								 M1 <= data_in1 - data_in6;
								 M2 <= data_in2 - data_in5;
								 M3 <= data_in3 - data_in4;
								 P0 <= data_in0 + data_in7;
								 P1 <= data_in1 + data_in6;
								 P2 <= data_in2 + data_in5;
								 P3 <= data_in3 + data_in4;
								 pipe0 <= 1;
							end
						STAGE2:
							begin
								 M03 <= P0 - P3;
								 M12 <= P1 - P2;
								 P03 <= P0 + P3;
								 P12 <= P1 + P2;
								 pipe1 <= 1;
							end
						STAGE3:
							begin
							  M4 <= P03 - P12;
							  P4 <= P03 + P12;
							  pipe2 <= 1;
							end
						STAGE4:
							begin
							 tempMultiply[0]  <= P4*C4;
							 tempMultiply[1]  <= M0*C1;
							 tempMultiply[2]  <= M1*C3;
							 tempMultiply[3]  <= M2*C5;
							 tempMultiply[4]  <= M3*C7;
							 tempMultiply[5]  <= M03*C2;
							 tempMultiply[6]  <= M12*C6;
							 tempMultiply[7]  <= M0*C3;
							 tempMultiply[8]  <= M1*C7;
							 tempMultiply[9]  <= M2*C1;
							 tempMultiply[10]  <= M3*C5;
							 tempMultiply[11]  <= M4*C4;
							 tempMultiply[12]  <= M0*C5;
							 tempMultiply[13]  <= M1*C1;
							 tempMultiply[14]  <= M2*C7;
							 tempMultiply[15]  <= M3*C3;
							 tempMultiply[16]  <= M03*C6;
							 tempMultiply[17]  <= M12*C2;
							 tempMultiply[18]  <= M0*C7;
							 tempMultiply[19]  <= M1*C5;
							 tempMultiply[20]  <= M2*C3;
							 tempMultiply[21]  <= M3*C1;
							 pipe3 <= 1;
							end
						STAGE5:	
							begin
							 data_out_reg0  <= tempMultiply[0];
							 data_out_reg1  <= tempMultiply[1] + tempMultiply[2] + tempMultiply[3] + tempMultiply[4];
							 data_out_reg2  <= tempMultiply[5] + tempMultiply[6];
							 data_out_reg3  <= tempMultiply[7] - tempMultiply[8] - tempMultiply[9] - tempMultiply[10];
							 data_out_reg4  <= tempMultiply[11];
							 data_out_reg5  <= tempMultiply[12] - tempMultiply[13] + tempMultiply[14] + tempMultiply[15];
							 data_out_reg6  <= tempMultiply[16] - tempMultiply[17];
							 data_out_reg7  <= tempMultiply[18] - tempMultiply[19] + tempMultiply[20] - tempMultiply[21];
							 done <= 1;
							end	
						STAGE6:
							begin
							 data_out0 <= data_out_reg0;
							 data_out1 <= data_out_reg1;
							 data_out2 <= data_out_reg2;
							 data_out3 <= data_out_reg3;
							 data_out4 <= data_out_reg4;
							 data_out5 <= data_out_reg5;
							 data_out6 <= data_out_reg6;
							 data_out7 <= data_out_reg7;
							end
						default:
							begin
							  data_out0 <= 16'b0;
							  data_out1 <= 16'b0;
							  data_out2 <= 16'b0;
							  data_out3 <= 16'b0;
							  data_out4 <= 16'b0;
							  data_out5 <= 16'b0;
							  data_out6 <= 16'b0;
							  data_out7 <= 16'b0;
							  
							 M0 <= 9'b0;
							 M1 <= 9'b0;
							 M2 <= 9'b0;
							 M3 <= 9'b0;
							 P0 <= 9'b0;
							 P1 <= 9'b0;
							 P2 <= 9'b0;
							 P3 <= 9'b0;
							 pipe0 <= 0;
							 
							 M03 <= 10'b0;
							 M12 <= 10'b0;
							 P03 <= 10'b0;
							 P12 <= 10'b0;
							 pipe1 <= 0;
							 
							 
							 M4 <= 11'b0;
							 P4 <= 11'b0;
							 pipe2 <= 0;
							 
							 tempMultiply[0]  <= 16'b0;
							 tempMultiply[1]  <= 16'b0;
							 tempMultiply[2]  <= 16'b0;
							 tempMultiply[3]  <= 16'b0;
							 tempMultiply[4]  <= 16'b0;
							 tempMultiply[5]  <= 16'b0;
							 tempMultiply[6]  <= 16'b0;
							 tempMultiply[7]  <= 16'b0;
							 tempMultiply[8]  <= 16'b0;
							 tempMultiply[9]  <= 16'b0;
							 tempMultiply[10]  <= 16'b0;
							 tempMultiply[11]  <= 16'b0;
							 tempMultiply[12]  <= 16'b0;
							 tempMultiply[13]  <= 16'b0;
							 tempMultiply[14]  <= 16'b0;
							 tempMultiply[15]  <= 16'b0;
							 tempMultiply[16]  <= 16'b0;
							 tempMultiply[17]  <= 16'b0;
							 tempMultiply[18]  <= 16'b0;
							 tempMultiply[19]  <= 16'b0;
							 tempMultiply[20]  <= 16'b0;
							 tempMultiply[21]  <= 16'b0;
							 pipe3 <= 0;
							end
					endcase
				end
		end

endmodule