data/full_repos/permissive/152883307/Project/Display_on_SEG.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152883307/Project/Display_on_SEG.v:25: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 22 bits.\n                                                                                : ... In instance Display_on_SEG\n Digit1  =  Digit / 409400;               \n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/152883307/Project/Display_on_SEG.v:26: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 22 bits.\n                                                                                : ... In instance Display_on_SEG\n Digit01  = (Digit - (Digit1 * 409400)) / 40940;        \n          ^\n%Warning-WIDTH: data/full_repos/permissive/152883307/Project/Display_on_SEG.v:27: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 22 bits.\n                                                                                : ... In instance Display_on_SEG\n Digit001  = (Digit - (Digit1 * 409400) - (Digit01 * 40940)) / 4094;  \n           ^\n%Error: Exiting due to 3 warning(s)\n'
module Display_on_SEG(
	clock_in,
	reset_n,
	data_from,
	dig1,
	dig01,
	dig001
);

input 						clock_in;
input 						reset_n;
input 			[11:0]	data_from;
output	reg	[6:0]		dig1;
output	reg	[6:0]		dig01;
output	reg	[6:0]		dig001;
reg				[21:0]	Digit;
reg				[3:0]		Digit1;
reg				[3:0]		Digit01;
reg				[3:0]		Digit001;

always@(negedge clock_in or negedge reset_n)
begin
	Digit = data_from * 500;
	
	Digit1		= 	Digit / 409400;
	Digit01		=	(Digit - (Digit1 * 409400)) / 40940;
	Digit001		=	(Digit - (Digit1 * 409400) - (Digit01 * 40940)) / 4094;

	
    case(Digit1)
      0: dig1 <= 7'b1000000;
      1: dig1 <= 7'b1111001;
      2: dig1 <= 7'b0100100;
      3: dig1 <= 7'b0110000;
      4: dig1 <= 7'b0011001;
      5: dig1 <= 7'b0010010;
      6: dig1 <= 7'b0000010;
      7: dig1 <= 7'b1111000;
      8: dig1 <= 7'b0000000;
      9: dig1 <= 7'b0010000;
		default: dig1 <= 7'b0111111;
    endcase
	 case(Digit01)
      0: dig01 <= 7'b1000000;
      1: dig01 <= 7'b1111001;
      2: dig01 <= 7'b0100100;
      3: dig01 <= 7'b0110000;
      4: dig01 <= 7'b0011001;
      5: dig01 <= 7'b0010010;
      6: dig01 <= 7'b0000010;
      7: dig01 <= 7'b1111000;
      8: dig01 <= 7'b0000000;
      9: dig01 <= 7'b0010000;
		default: dig01 <= 7'b0111111;
    endcase
	 case(Digit001)
      0: dig001 <= 7'b1000000;
      1: dig001 <= 7'b1111001;
      2: dig001 <= 7'b0100100;
      3: dig001 <= 7'b0110000;
      4: dig001 <= 7'b0011001;
      5: dig001 <= 7'b0010010;
      6: dig001 <= 7'b0000010;
      7: dig001 <= 7'b1111000;
      8: dig001 <= 7'b0000000;
      9: dig001 <= 7'b0010000;
		default: dig001 <= 7'b0111111;
    endcase
end
endmodule
module Display_on_SEG(
	clock_in,
	reset_n,
	data_from,
	dig1,
	dig01,
	dig001
);


input 						clock_in;
input 						reset_n;
input 			[11:0]	data_from;
output	reg	[6:0]		dig1;
output	reg	[6:0]		dig01;
output	reg	[6:0]		dig001;
reg				[21:0]	Digit;
reg				[3:0]		Digit1;
reg				[3:0]		Digit01;
reg				[3:0]		Digit001;

always@(negedge clock_in or negedge reset_n)
begin
	Digit = data_from * 500;
	
	Digit1		= 	Digit / 409400;
	Digit01		=	(Digit - (Digit1 * 409400)) / 40940;
	Digit001		=	(Digit - (Digit1 * 409400) - (Digit01 * 40940)) / 4094;

	
    case(Digit1)
      0: dig1 <= 7'b1000000;
      1: dig1 <= 7'b1111001;
      2: dig1 <= 7'b0100100;
      3: dig1 <= 7'b0110000;
      4: dig1 <= 7'b0011001;
      5: dig1 <= 7'b0010010;
      6: dig1 <= 7'b0000010;
      7: dig1 <= 7'b1111000;
      8: dig1 <= 7'b0000000;
      9: dig1 <= 7'b0010000;
		default: dig1 <= 7'b0111111;
    endcase
	 case(Digit01)
      0: dig01 <= 7'b1000000;
      1: dig01 <= 7'b1111001;
      2: dig01 <= 7'b0100100;
      3: dig01 <= 7'b0110000;
      4: dig01 <= 7'b0011001;
      5: dig01 <= 7'b0010010;
      6: dig01 <= 7'b0000010;
      7: dig01 <= 7'b1111000;
      8: dig01 <= 7'b0000000;
      9: dig01 <= 7'b0010000;
		default: dig01 <= 7'b0111111;
    endcase
	 case(Digit001)
      0: dig001 <= 7'b1000000;
      1: dig001 <= 7'b1111001;
      2: dig001 <= 7'b0100100;
      3: dig001 <= 7'b0110000;
      4: dig001 <= 7'b0011001;
      5: dig001 <= 7'b0010010;
      6: dig001 <= 7'b0000010;
      7: dig001 <= 7'b1111000;
      8: dig001 <= 7'b0000000;
      9: dig001 <= 7'b0010000;
		default: dig001 <= 7'b0111111;
    endcase
end
endmodule