data/full_repos/permissive/204646149/mdma_1.0/hdl/mdma_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/204646149/mdma_1.0/hdl/mdma_fifo.v:111: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'head\' generates 2 bits.\n                                                                                 : ... In instance mdma_fifo\n            if (head == (DATA_DEPTH - 1)) begin\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/204646149/mdma_1.0/hdl/mdma_fifo.v:119: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'tail\' generates 2 bits.\n                                                                                 : ... In instance mdma_fifo\n            if (tail == (DATA_DEPTH - 1)) begin\n                     ^~\n%Error: Exiting due to 2 warning(s)\n'
module mdma_fifo #(
    parameter DATA_WIDTH = 8,
    parameter DATA_DEPTH = 4
)
(
    input wire aclk,
    input wire aresetn,
	input wire [DATA_WIDTH-1:0]s_axis_tdata,
	input wire s_axis_tvalid,
	output wire s_axis_tready,
	input wire s_axis_tlast,
	output wire [DATA_WIDTH-1:0]m_axis_tdata,
	output wire m_axis_tvalid,
	input wire m_axis_tready,
	output wire m_axis_tlast
);

function integer clogb2;
    input [31:0]value;
    begin
        value = value - 1;
        for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
            value = value >> 1;
        end
    end
endfunction

localparam CWIDTH = clogb2(DATA_DEPTH);

reg [DATA_WIDTH:0]data[DATA_DEPTH-1:0];
reg [CWIDTH:0]count;
reg [CWIDTH-1:0]tail;
reg [CWIDTH-1:0]head;

wire fifo_full;
wire fifo_empty;

wire fifo_wr;
wire fifo_rd;

wire [DATA_WIDTH:0]din;
wire [DATA_WIDTH:0]dout;

integer i;

assign din = {s_axis_tlast, s_axis_tdata};
assign dout = data[tail];

assign s_axis_tready = ~fifo_full;
assign m_axis_tdata = dout[DATA_WIDTH-1:0];
assign m_axis_tvalid = ~fifo_empty;
assign m_axis_tlast = dout[DATA_WIDTH];

assign fifo_full = (count == DATA_DEPTH) ? 1'b1 : 1'b0;
assign fifo_empty = (count == 0) ? 1'b1 : 1'b0;

assign fifo_wr = s_axis_tvalid & s_axis_tready;
assign fifo_rd = m_axis_tvalid & m_axis_tready;

always @(posedge aclk) begin
    if (aresetn == 1'b0) begin
        for (i = 0; i < DATA_DEPTH; i = i + 1) begin
            data[i] <= 0;
        end
        count <= 0;
        tail <= 0;
        head <= 0;
    end else begin
        if (fifo_wr) begin
            data[head] <= din;
            if (head == (DATA_DEPTH - 1)) begin
                head <= 0;
            end else begin
                head <= head + 1;
            end
        end
        
        if (fifo_rd) begin
            if (tail == (DATA_DEPTH - 1)) begin
                tail <= 0;
            end else begin
                tail <= tail + 1;
            end
        end
        
        case ({fifo_wr, fifo_rd})
            2'b01: count <= count - 1;
            2'b10: count <= count + 1;
            default: count <= count;
        endcase
    end
end
endmodule
module mdma_fifo #(
    parameter DATA_WIDTH = 8,
    parameter DATA_DEPTH = 4
)
(
    input wire aclk,
    input wire aresetn,
	input wire [DATA_WIDTH-1:0]s_axis_tdata,
	input wire s_axis_tvalid,
	output wire s_axis_tready,
	input wire s_axis_tlast,
	output wire [DATA_WIDTH-1:0]m_axis_tdata,
	output wire m_axis_tvalid,
	input wire m_axis_tready,
	output wire m_axis_tlast
);


function integer clogb2;
    input [31:0]value;
    begin
        value = value - 1;
        for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
            value = value >> 1;
        end
    end
endfunction

localparam CWIDTH = clogb2(DATA_DEPTH);

reg [DATA_WIDTH:0]data[DATA_DEPTH-1:0];
reg [CWIDTH:0]count;
reg [CWIDTH-1:0]tail;
reg [CWIDTH-1:0]head;

wire fifo_full;
wire fifo_empty;

wire fifo_wr;
wire fifo_rd;

wire [DATA_WIDTH:0]din;
wire [DATA_WIDTH:0]dout;

integer i;

assign din = {s_axis_tlast, s_axis_tdata};
assign dout = data[tail];

assign s_axis_tready = ~fifo_full;
assign m_axis_tdata = dout[DATA_WIDTH-1:0];
assign m_axis_tvalid = ~fifo_empty;
assign m_axis_tlast = dout[DATA_WIDTH];

assign fifo_full = (count == DATA_DEPTH) ? 1'b1 : 1'b0;
assign fifo_empty = (count == 0) ? 1'b1 : 1'b0;

assign fifo_wr = s_axis_tvalid & s_axis_tready;
assign fifo_rd = m_axis_tvalid & m_axis_tready;

always @(posedge aclk) begin
    if (aresetn == 1'b0) begin
        for (i = 0; i < DATA_DEPTH; i = i + 1) begin
            data[i] <= 0;
        end
        count <= 0;
        tail <= 0;
        head <= 0;
    end else begin
        if (fifo_wr) begin
            data[head] <= din;
            if (head == (DATA_DEPTH - 1)) begin
                head <= 0;
            end else begin
                head <= head + 1;
            end
        end
        
        if (fifo_rd) begin
            if (tail == (DATA_DEPTH - 1)) begin
                tail <= 0;
            end else begin
                tail <= tail + 1;
            end
        end
        
        case ({fifo_wr, fifo_rd})
            2'b01: count <= count - 1;
            2'b10: count <= count + 1;
            default: count <= count;
        endcase
    end
end
endmodule