data/full_repos/permissive/113780415/src/Control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:18: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'LOAD_LEFT_WAIT\' generates 5 bits.\n                                                                     : ... In instance control\n   LOAD_LEFT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_LEFT;\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:18: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'LOAD_LEFT\' generates 5 bits.\n                                                                     : ... In instance control\n   LOAD_LEFT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_LEFT;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:19: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'LOAD_LEFT_WAIT\' generates 5 bits.\n                                                                     : ... In instance control\n   LOAD_LEFT_WAIT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_RIGHT;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:19: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'LOAD_RIGHT\' generates 5 bits.\n                                                                     : ... In instance control\n   LOAD_LEFT_WAIT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_RIGHT;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:20: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'LOAD_RIGHT_WAIT\' generates 5 bits.\n                                                                     : ... In instance control\n   LOAD_RIGHT : next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_RIGHT;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:20: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'LOAD_RIGHT\' generates 5 bits.\n                                                                     : ... In instance control\n   LOAD_RIGHT : next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_RIGHT;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:21: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'LOAD_RIGHT_WAIT\' generates 5 bits.\n                                                                     : ... In instance control\n   LOAD_RIGHT_WAIT: next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_USER;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:21: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'LOAD_USER\' generates 5 bits.\n                                                                     : ... In instance control\n   LOAD_RIGHT_WAIT: next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_USER;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:22: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'LOAD_USER_WAIT\' generates 5 bits.\n                                                                     : ... In instance control\n   LOAD_USER: next_state = ~stop_rps? LOAD_USER_WAIT: LOAD_USER;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:22: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'LOAD_USER\' generates 5 bits.\n                                                                     : ... In instance control\n   LOAD_USER: next_state = ~stop_rps? LOAD_USER_WAIT: LOAD_USER;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:24: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'LOAD_LEFT\' generates 5 bits.\n                                                                     : ... In instance control\n   default: next_state = LOAD_LEFT;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:17: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_LEFT\' generates 5 bits.\n                                                                     : ... In instance control\n  case(current_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:17: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_LEFT_WAIT\' generates 5 bits.\n                                                                     : ... In instance control\n  case(current_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:17: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_RIGHT\' generates 5 bits.\n                                                                     : ... In instance control\n  case(current_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:17: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_RIGHT_WAIT\' generates 5 bits.\n                                                                     : ... In instance control\n  case(current_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:17: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_USER\' generates 5 bits.\n                                                                     : ... In instance control\n  case(current_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:34: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_LEFT\' generates 5 bits.\n                                                                     : ... In instance control\n  case (current_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:34: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_RIGHT\' generates 5 bits.\n                                                                     : ... In instance control\n  case (current_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:34: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'LOAD_USER\' generates 5 bits.\n                                                                     : ... In instance control\n  case (current_state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113780415/src/Control.v:52: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'LOAD_LEFT\' generates 5 bits.\n                                                                     : ... In instance control\n      current_state <= LOAD_LEFT;  \n                    ^~\n%Error: Exiting due to 20 warning(s)\n'
module control(clk, resetn, ld_user, ld_left, ld_right, stop_left, stop_right, stop_rps);
	input clk, resetn;
        input stop_left, stop_right, stop_rps;
	output reg ld_user, ld_left, ld_right;
	reg[5:0] current_state, next_state;
	localparam LOAD_LEFT = 5'd0,
		   LOAD_LEFT_WAIT = 5'd1,
		   LOAD_RIGHT = 5'd2,
		   LOAD_RIGHT_WAIT = 5'd3,
		   LOAD_USER = 5'd4,
		   LOAD_USER_WAIT = 5'd5;

	always@(*)
	begin: state_table
		case(current_state)
			LOAD_LEFT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_LEFT;
			LOAD_LEFT_WAIT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_RIGHT;
			LOAD_RIGHT : next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_RIGHT;
			LOAD_RIGHT_WAIT: next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_USER;
			LOAD_USER: next_state = ~stop_rps? LOAD_USER_WAIT: LOAD_USER;

			default: next_state = LOAD_LEFT;
		endcase
	end
	
	always @(*)
	begin: enable_signals
		ld_left = 1'b0;
		ld_right = 1'b0;
		ld_user = 1'b0;
		  
		case (current_state)
		    LOAD_LEFT: begin
			ld_left = 1'b1;
			end
		    LOAD_RIGHT: begin
		    	ld_right = 1'b1;
			end
		    LOAD_USER: begin
			ld_user = 1'b1;
			end

		endcase
        end
    

	always @(posedge clk)
	begin: state_FFs
		if (resetn == 1'b0)
		    current_state <= LOAD_LEFT;
		else
		    current_state <= next_state;
	end
endmodule
module control(clk, resetn, ld_user, ld_left, ld_right, stop_left, stop_right, stop_rps);

	input clk, resetn;
        input stop_left, stop_right, stop_rps;
	output reg ld_user, ld_left, ld_right;
	reg[5:0] current_state, next_state;
	localparam LOAD_LEFT = 5'd0,
		   LOAD_LEFT_WAIT = 5'd1,
		   LOAD_RIGHT = 5'd2,
		   LOAD_RIGHT_WAIT = 5'd3,
		   LOAD_USER = 5'd4,
		   LOAD_USER_WAIT = 5'd5;

	always@(*)
	begin: state_table
		case(current_state)
			LOAD_LEFT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_LEFT;
			LOAD_LEFT_WAIT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_RIGHT;
			LOAD_RIGHT : next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_RIGHT;
			LOAD_RIGHT_WAIT: next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_USER;
			LOAD_USER: next_state = ~stop_rps? LOAD_USER_WAIT: LOAD_USER;

			default: next_state = LOAD_LEFT;
		endcase
	end
	
	always @(*)
	begin: enable_signals
		ld_left = 1'b0;
		ld_right = 1'b0;
		ld_user = 1'b0;
		  
		case (current_state)
		    LOAD_LEFT: begin
			ld_left = 1'b1;
			end
		    LOAD_RIGHT: begin
		    	ld_right = 1'b1;
			end
		    LOAD_USER: begin
			ld_user = 1'b1;
			end

		endcase
        end
    

	always @(posedge clk)
	begin: state_FFs
		if (resetn == 1'b0)
		    current_state <= LOAD_LEFT;
		else
		    current_state <= next_state;
	end
endmodule