data/full_repos/permissive/104305228/code/register.v
1: b'%Error: data/full_repos/permissive/104305228/code/register.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/register.v:18: Define or directive not defined: \'`RstDisable\'\n  if (rst == `RstDisable && re1 == `ReadEnable && read_addr1 != 5\'b0) begin\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/register.v:18: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n  if (rst == `RstDisable && re1 == `ReadEnable && read_addr1 != 5\'b0) begin\n                         ^~\n%Error: data/full_repos/permissive/104305228/code/register.v:18: Define or directive not defined: \'`ReadEnable\'\n  if (rst == `RstDisable && re1 == `ReadEnable && read_addr1 != 5\'b0) begin\n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/register.v:27: Define or directive not defined: \'`RstDisable\'\n  if (rst == `RstDisable && re2 == `ReadEnable && read_addr2 != 5\'b0) begin\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/register.v:27: Define or directive not defined: \'`ReadEnable\'\n  if (rst == `RstDisable && re2 == `ReadEnable && read_addr2 != 5\'b0) begin\n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/register.v:36: Define or directive not defined: \'`RstDisable\'\n  if (rst == `RstDisable && we == `WriteEnable && write_addr != 5\'b0) begin\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/register.v:36: Define or directive not defined: \'`WriteEnable\'\n  if (rst == `RstDisable && we == `WriteEnable && write_addr != 5\'b0) begin\n                                  ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module register(
	input clk,
	input rst,
	input re1,
	input [4:0] read_addr1,
	input re2,
	input [4:0] read_addr2,
	input we,
	input [4:0] write_addr,
	input [31:0] write_instr,
	output reg[31:0] read_instr1,
	output reg[31:0] read_instr2
);

	reg[31:0] instr[31:0];
	always @ (*) begin
		if (rst == `RstDisable && re1 == `ReadEnable && read_addr1 != 5'b0) begin
			read_instr1 <= instr[read_addr1];
		end
		else begin
			read_instr1 <= 32'b0;
		end
	end

	always @ (*) begin
		if (rst == `RstDisable && re2 == `ReadEnable && read_addr2 != 5'b0) begin
			read_instr2 <= instr[read_addr2];
		end
		else begin
			read_instr2 <= 32'b0;
		end
	end
	
	always @ (negedge clk) begin
		if (rst == `RstDisable && we == `WriteEnable && write_addr != 5'b0) begin
			instr[write_addr] <= write_instr;
		end
	end
endmodule
module register(
	input clk,
	input rst,
	input re1,
	input [4:0] read_addr1,
	input re2,
	input [4:0] read_addr2,
	input we,
	input [4:0] write_addr,
	input [31:0] write_instr,
	output reg[31:0] read_instr1,
	output reg[31:0] read_instr2
);


	reg[31:0] instr[31:0];
	always @ (*) begin
		if (rst == `RstDisable && re1 == `ReadEnable && read_addr1 != 5'b0) begin
			read_instr1 <= instr[read_addr1];
		end
		else begin
			read_instr1 <= 32'b0;
		end
	end

	always @ (*) begin
		if (rst == `RstDisable && re2 == `ReadEnable && read_addr2 != 5'b0) begin
			read_instr2 <= instr[read_addr2];
		end
		else begin
			read_instr2 <= 32'b0;
		end
	end
	
	always @ (negedge clk) begin
		if (rst == `RstDisable && we == `WriteEnable && write_addr != 5'b0) begin
			instr[write_addr] <= write_instr;
		end
	end
endmodule