data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_tx_circular_buffer_66.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_tx_circular_buffer_66.sv:97: Cannot find include file: sonic_constants.sv\n`include "sonic_constants.sv" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18477150/lib/shared/circbuf,data/full_repos/permissive/18477150/sonic_constants.sv\n             data/full_repos/permissive/18477150/lib/shared/circbuf,data/full_repos/permissive/18477150/sonic_constants.sv.v\n             data/full_repos/permissive/18477150/lib/shared/circbuf,data/full_repos/permissive/18477150/sonic_constants.sv.sv\n             sonic_constants.sv\n             sonic_constants.sv.v\n             sonic_constants.sv.sv\n             obj_dir/sonic_constants.sv\n             obj_dir/sonic_constants.sv.v\n             obj_dir/sonic_constants.sv.sv\n%Error: data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_tx_circular_buffer_66.sv:107: Define or directive not defined: \'`TX_WRITE_ADDR_WIDTH\'\n   input [`TX_WRITE_ADDR_WIDTH-1:0]  wr_address;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_tx_circular_buffer_66.sv:117: Define or directive not defined: \'`TX_READ_ADDR_WIDTH\'\n   output [`TX_READ_ADDR_WIDTH-1:0] clock_crossed_rd_address;\n           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_tx_circular_buffer_66.sv:122: Define or directive not defined: \'`TX_READ_ADDR_WIDTH\'\n   logic [`TX_READ_ADDR_WIDTH-1:0]  rd_address;\n          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_tx_circular_buffer_66.sv:124: Define or directive not defined: \'`TX_WRITE_ADDR_WIDTH\'\n   logic [`TX_WRITE_ADDR_WIDTH-1:0]  wr_address_data;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_tx_circular_buffer_66.sv:141: Define or directive not defined: \'`TX_WRITE_ADDR_WIDTH\'\n   assign wr_address_sync = {wr_address[`TX_WRITE_ADDR_WIDTH-1:8], wr_address[2:0]}; \n                                        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_tx_circular_buffer_66.sv:204: Define or directive not defined: \'`TX_READ_ADDR_WIDTH\'\n   defparam rdcounter_to_wrclock.WIDTH = `TX_READ_ADDR_WIDTH;\n                                         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_tx_circular_buffer_66.sv:204: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   defparam rdcounter_to_wrclock.WIDTH = `TX_READ_ADDR_WIDTH;\n                                                            ^\n%Error: Exiting due to 8 error(s)\n'
module sonic_tx_circular_buffer_66 (

   data_out, clock_crossed_rd_address,

   data_in, wr_address, wr_clk, rd_clk, reset, wrreq, rdena, rdreq
   ) ;

   input [127:0] data_in;
   input [`TX_WRITE_ADDR_WIDTH-1:0]  wr_address;
   input 	 wr_clk;
   input 	 rd_clk;
   input 	 reset;
   input         wrreq;
   input 	 rdena; 	 
   input 	 rdreq;


   output [65:0] data_out;
   output [`TX_READ_ADDR_WIDTH-1:0] clock_crossed_rd_address;
      
   logic [1:0] 	 dout_sync;
   logic [63:0]  dout_data;

   logic [`TX_READ_ADDR_WIDTH-1:0]  rd_address;
   logic [8:0]   wr_address_sync;
   logic [`TX_WRITE_ADDR_WIDTH-1:0]  wr_address_data;
   logic 	 wren_data;
   logic 	 wren_sync;



   
   assign data_out = {dout_data, dout_sync};

   

   assign wr_address_sync = {wr_address[`TX_WRITE_ADDR_WIDTH-1:8], wr_address[2:0]}; 
   assign wr_address_data = wr_address;
   

   assign wren_data = (wr_address[7] | wr_address[6] | wr_address[5] | wr_address[4] | wr_address[3]) & wrreq;
   assign wren_sync = (~wren_data) & wrreq;


   sonic_calc_address gen_rd_addr (.clk_in(rd_clk),
				   .ena(rdena),
				   .incr(rdreq),
				   .reset(reset),
				   .addr_out(rd_address)
				   );
   

   sonic_data_ring_128_64 data_ring (.data(data_in),
				       .rdaddress(rd_address),
				       .rdclock(rd_clk),
				       .rden(1'b1),
				       .wraddress(wr_address_data),
				       .wrclock(wr_clk),
				       .wren(wren_data),
				       .q(dout_data)
				       );
   

   sonic_sync_ring_128_2 sync_ring(.data_in(data_in),
				   .wren(wren_sync),
				   .rd_clock(rd_clk),
				   .wr_clock(wr_clk),
				   .wr_address(wr_address_sync),
				   .rd_address(rd_address),
				   .data_out(dout_sync)
				   );


   sonic_common_gray_clock_crosser rdcounter_to_wrclock(
							.inclock(rd_clk),
							.outclock(wr_clk),
							.inena(rdena),
							.outena(1'b1),
							.reset(reset),
							.data(rd_address),
							.q(clock_crossed_rd_address)
							);
   defparam rdcounter_to_wrclock.WIDTH = `TX_READ_ADDR_WIDTH;
   
endmodule
module sonic_tx_circular_buffer_66 (

   data_out, clock_crossed_rd_address,

   data_in, wr_address, wr_clk, rd_clk, reset, wrreq, rdena, rdreq
   ) ;


   input [127:0] data_in;
   input [`TX_WRITE_ADDR_WIDTH-1:0]  wr_address;
   input 	 wr_clk;
   input 	 rd_clk;
   input 	 reset;
   input         wrreq;
   input 	 rdena; 	 
   input 	 rdreq;


   output [65:0] data_out;
   output [`TX_READ_ADDR_WIDTH-1:0] clock_crossed_rd_address;
      
   logic [1:0] 	 dout_sync;
   logic [63:0]  dout_data;

   logic [`TX_READ_ADDR_WIDTH-1:0]  rd_address;
   logic [8:0]   wr_address_sync;
   logic [`TX_WRITE_ADDR_WIDTH-1:0]  wr_address_data;
   logic 	 wren_data;
   logic 	 wren_sync;



   
   assign data_out = {dout_data, dout_sync};

   

   assign wr_address_sync = {wr_address[`TX_WRITE_ADDR_WIDTH-1:8], wr_address[2:0]}; 
   assign wr_address_data = wr_address;
   

   assign wren_data = (wr_address[7] | wr_address[6] | wr_address[5] | wr_address[4] | wr_address[3]) & wrreq;
   assign wren_sync = (~wren_data) & wrreq;


   sonic_calc_address gen_rd_addr (.clk_in(rd_clk),
				   .ena(rdena),
				   .incr(rdreq),
				   .reset(reset),
				   .addr_out(rd_address)
				   );
   

   sonic_data_ring_128_64 data_ring (.data(data_in),
				       .rdaddress(rd_address),
				       .rdclock(rd_clk),
				       .rden(1'b1),
				       .wraddress(wr_address_data),
				       .wrclock(wr_clk),
				       .wren(wren_data),
				       .q(dout_data)
				       );
   

   sonic_sync_ring_128_2 sync_ring(.data_in(data_in),
				   .wren(wren_sync),
				   .rd_clock(rd_clk),
				   .wr_clock(wr_clk),
				   .wr_address(wr_address_sync),
				   .rd_address(rd_address),
				   .data_out(dout_sync)
				   );


   sonic_common_gray_clock_crosser rdcounter_to_wrclock(
							.inclock(rd_clk),
							.outclock(wr_clk),
							.inena(rdena),
							.outena(1'b1),
							.reset(reset),
							.data(rd_address),
							.q(clock_crossed_rd_address)
							);
   defparam rdcounter_to_wrclock.WIDTH = `TX_READ_ADDR_WIDTH;
   
endmodule