data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v
1: b'%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:23: Duplicate declaration of module: \'top_module\'\nmodule top_module ( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:2: ... Location of original declaration\nmodule top_module ( input clk, input d, output q );\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:59: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:2: ... Location of original declaration\nmodule top_module ( input clk, input d, output q );\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:84: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:2: ... Location of original declaration\nmodule top_module ( input clk, input d, output q );\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:134: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:2: ... Location of original declaration\nmodule top_module ( input clk, input d, output q );\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:167: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:2: ... Location of original declaration\nmodule top_module ( input clk, input d, output q );\n       ^~~~~~~~~~\n%Warning-MULTITOP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:112: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                            : ... Top module \'top_module\'\nmodule top_module ( input clk, input d, output q );\n       ^~~~~~~~~~\n                                                                                            : ... Top module \'my_add16\'\nmodule my_add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );\n       ^~~~~~~~\n%Error: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:4: Cannot find file containing module: \'my_dff\'\n    my_dff U1(\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/148324174/HDLBits/VerilogLanguage,data/full_repos/permissive/148324174/my_dff\n             data/full_repos/permissive/148324174/HDLBits/VerilogLanguage,data/full_repos/permissive/148324174/my_dff.v\n             data/full_repos/permissive/148324174/HDLBits/VerilogLanguage,data/full_repos/permissive/148324174/my_dff.sv\n             my_dff\n             my_dff.v\n             my_dff.sv\n             obj_dir/my_dff\n             obj_dir/my_dff.v\n             obj_dir/my_dff.sv\n%Error: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:9: Cannot find file containing module: \'my_dff\'\n    my_dff U2(\n    ^~~~~~\n%Error: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Module.v:14: Cannot find file containing module: \'my_dff\'\n    my_dff U3(\n    ^~~~~~\n%Error: Exiting due to 3 error(s), 6 warning(s)\n'
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] result
);
    wire cout_lo;
    wire [15:0] sum_lo, sum_hi;
    wire [31:0] sub_b;

    add16 U1(
        .a(a[15:0]),
        .b(sub_b[15:0]),
        .sum(sum_lo),
        .cin(sub),
        .cout(cout_lo)
        );
    add16 U2(
        .a(a[31:16]),
        .b(sub_b[31:16]),
        .sum(sum_hi),
        .cin(cout_lo)
        );
    assign sub_b = {32{sub}}^b;
    assign result = {sum_hi, sum_lo};
endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] result
);

    wire cout_lo;
    wire [15:0] sum_lo, sum_hi;
    wire [31:0] sub_b;

    add16 U1(
        .a(a[15:0]),
        .b(sub_b[15:0]),
        .sum(sum_lo),
        .cin(sub),
        .cout(cout_lo)
        );
    add16 U2(
        .a(a[31:16]),
        .b(sub_b[31:16]),
        .sum(sum_hi),
        .cin(cout_lo)
        );
    assign sub_b = {32{sub}}^b;
    assign result = {sum_hi, sum_lo};
endmodule