data/full_repos/permissive/214823094/submissions/lab_6/project_1/traffic_lights_1.v
 line:81: before: "begin"
data/verilator_xmls/ee4f87ae-baf2-40c8-8c6e-03264beae870.xml
module clkdiv(
    input inclk,
    output outclk
    );
    reg [35:0]q;
    always@(posedge inclk)
         q<=q+1;
    assign outclk=q[26];
endmodule
module clkdiv(
    input inclk,
    output outclk
    );

    reg [35:0]q;
    always@(posedge inclk)
         q<=q+1;
    assign outclk=q[26];
endmodule