data/full_repos/permissive/210918583/rtl/m6800.v
data/verilator_xmls/aa134f92-c746-4c7a-bbf9-e3ce410fd5d2.xml
module m6800(

           input                CLK7M,
           input                        AS20,
           input [2:0]  FC,
           input                        VPA,
           output               VMA,
           output reg   E,


           output   DSACK1

       );

wire CPUSPACE = &FC;


reg [3:0] Q = 'h4;
reg VMA_SYNC = 1'b1;
reg DSACK1_SYNC = 1'b1;


initial begin

    E = 'b0;

end



always @(posedge CLK7M) begin



    if (Q == 'd9) begin

        Q <= 'd0;

    end else begin

        Q <= Q + 'd1;

        if (Q == 'd4) begin

            E <= 'b1;

        end

        if (Q == 'd8) begin

            E <= 'b0;

        end

    end

end


always @(posedge CLK7M or posedge VPA) begin

    if (VPA == 1'b1) begin

        VMA_SYNC <= 1'b1;

    end else begin

        if (Q == 'd9) begin

            VMA_SYNC <= 1'b1;

        end

        if (Q == 'd2) begin

            VMA_SYNC <= VPA | CPUSPACE;

        end

    end

end

always @(posedge CLK7M or posedge AS20) begin

    if (AS20 == 1'b1) begin

        DSACK1_SYNC <= 1'b1;

    end else begin

        if (Q == 'd9) begin

            DSACK1_SYNC <= 1'b1;

        end

        if (Q == 'd8) begin

            DSACK1_SYNC <= VMA_SYNC;

        end

    end

end

assign VMA = VMA_SYNC;
assign DSACK1 = DSACK1_SYNC;

endmodule
module m6800(

           input                CLK7M,
           input                        AS20,
           input [2:0]  FC,
           input                        VPA,
           output               VMA,
           output reg   E,


           output   DSACK1

       );


wire CPUSPACE = &FC;


reg [3:0] Q = 'h4;
reg VMA_SYNC = 1'b1;
reg DSACK1_SYNC = 1'b1;


initial begin

    E = 'b0;

end



always @(posedge CLK7M) begin



    if (Q == 'd9) begin

        Q <= 'd0;

    end else begin

        Q <= Q + 'd1;

        if (Q == 'd4) begin

            E <= 'b1;

        end

        if (Q == 'd8) begin

            E <= 'b0;

        end

    end

end


always @(posedge CLK7M or posedge VPA) begin

    if (VPA == 1'b1) begin

        VMA_SYNC <= 1'b1;

    end else begin

        if (Q == 'd9) begin

            VMA_SYNC <= 1'b1;

        end

        if (Q == 'd2) begin

            VMA_SYNC <= VPA | CPUSPACE;

        end

    end

end

always @(posedge CLK7M or posedge AS20) begin

    if (AS20 == 1'b1) begin

        DSACK1_SYNC <= 1'b1;

    end else begin

        if (Q == 'd9) begin

            DSACK1_SYNC <= 1'b1;

        end

        if (Q == 'd8) begin

            DSACK1_SYNC <= VMA_SYNC;

        end

    end

end

assign VMA = VMA_SYNC;
assign DSACK1 = DSACK1_SYNC;

endmodule