data/full_repos/permissive/149553056/sources/divider.v
None: at end of input
data/verilator_xmls/b1896dca-abe1-4877-a06f-02bc5b25835c.xml
module divider #(
parameter N = 50000000,
	      WIDTH = 32
)

(
    input clk,
    input rst,
    output reg clk_out
);
 
reg [WIDTH-1:0]counter;
always @(posedge clk or posedge rst) begin
	if (rst) begin

		counter <= 0;
	end
	else if (counter == N-1) begin
		counter <= 0;
	end
	else begin
		counter <= counter + 1;
	end
end
 
always @(posedge clk or posedge rst) begin
	if (rst) begin

		clk_out <= 0;
	end
	else if (counter == N-1) begin
		clk_out <= !clk_out;
	end
end
 
endmodule
module divider #(
parameter N = 50000000,
	      WIDTH = 32
)

(
    input clk,
    input rst,
    output reg clk_out
);

 
reg [WIDTH-1:0]counter;
always @(posedge clk or posedge rst) begin
	if (rst) begin

		counter <= 0;
	end
	else if (counter == N-1) begin
		counter <= 0;
	end
	else begin
		counter <= counter + 1;
	end
end
 
always @(posedge clk or posedge rst) begin
	if (rst) begin

		clk_out <= 0;
	end
	else if (counter == N-1) begin
		clk_out <= !clk_out;
	end
end
 
endmodule