data/full_repos/permissive/123796236/mem32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123796236/mem32.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100 clk <= ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testmem32();

reg mem_WriteCtrl, mem_ReadCtrl, clk, file_ID;
reg [31:0] mem_Address, mem_WriteData;
wire [31:0] mem_OutputData;

mem32 m(mem_OutputData, mem_Address, mem_WriteData, mem_WriteCtrl, mem_ReadCtrl, clk, file_ID);

initial begin
	clk = 0;
	file_ID = 0;
	mem_WriteCtrl = 0;
	mem_ReadCtrl = 1;
	mem_Address = 32'd0;
	mem_WriteData = 32'h00010001;
end
always
	begin
	#100 clk <= ~clk;
	mem_Address <= mem_Address + 1;
	end
endmodule
module testmem32();


reg mem_WriteCtrl, mem_ReadCtrl, clk, file_ID;
reg [31:0] mem_Address, mem_WriteData;
wire [31:0] mem_OutputData;

mem32 m(mem_OutputData, mem_Address, mem_WriteData, mem_WriteCtrl, mem_ReadCtrl, clk, file_ID);

initial begin
	clk = 0;
	file_ID = 0;
	mem_WriteCtrl = 0;
	mem_ReadCtrl = 1;
	mem_Address = 32'd0;
	mem_WriteData = 32'h00010001;
end
always
	begin
	#100 clk <= ~clk;
	mem_Address <= mem_Address + 1;
	end
endmodule