data/full_repos/permissive/201275379/src/cpu/core/Core.v
None: at end of input
data/verilator_xmls/d86dec0d-344e-49c9-b06a-bbacc3e35e6b.xml
module Core(
  input clk,
  input rst,
  input [4:0] intr
);



endmodule
module Core(
  input clk,
  input rst,
  input [4:0] intr
);




endmodule