data/full_repos/permissive/109846502/calkkoTest.v
1: b'%Error: data/full_repos/permissive/109846502/calkkoTest.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:62: Define or directive not defined: \'`S_OBL\'\n  ST = `S_OBL;\n       ^~~~~~\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  ST = `S_OBL;\n             ^\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:75: Define or directive not defined: \'`SL_ADD\'\n  ST_L = `SL_ADD;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  ST_L = `SL_ADD;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/calkkoTest.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:77: Define or directive not defined: \'`SL_SUB\'\n  ST_L = `SL_SUB;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:77: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  ST_L = `SL_SUB;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/calkkoTest.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:79: Define or directive not defined: \'`SL_XOR\'\n  ST_L = `SL_XOR;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  ST_L = `SL_XOR;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/calkkoTest.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:81: Define or directive not defined: \'`SL_OR\'\n  ST_L = `SL_OR;\n         ^~~~~~\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  ST_L = `SL_OR;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/calkkoTest.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:83: Define or directive not defined: \'`SL_AND\'\n  ST_L = `SL_AND;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109846502/calkkoTest.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  ST_L = `SL_AND;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/calkkoTest.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 13 error(s), 5 warning(s)\n'
module calkkoTest;


	reg [3:0] A1;
	reg [3:0] A2;
	reg [3:0] A3;
	reg [3:0] A4;
	reg [3:0] B1;
	reg [3:0] B2;
	reg [3:0] B3;
	reg [3:0] B4;
	reg [1:0] ST;
	reg [2:0] ST_L;
	
	reg [3:0] OUT1, OUT2, OUT3, OUT4;


	wire set;
	wire [15:0] number;


	Calkko uut (
		.A1(A1), 
		.A2(A2), 
		.A3(A3), 
		.A4(A4), 
		.B1(B1), 
		.B2(B2), 
		.B3(B3), 
		.B4(B4), 
		.ST(ST), 
		.ST_L(ST_L), 
		.set(set), 
		.number(number)
	);

	initial begin
		ST = `S_OBL;
		
		A1 = 4'd0;
		A2 = 4'd0;
		A3 = 4'd0;
		A4 = 4'd5;
		
		B1 = 4'd0;
		B2 = 4'd0;
		B3 = 4'd0;
		B4 = 4'd1;
		
		
		ST_L = `SL_ADD;
		#10;
		ST_L = `SL_SUB;
		#10;
		ST_L = `SL_XOR;
		#10;
		ST_L = `SL_OR;
		#10;
		ST_L = `SL_AND;

	end
	
	initial begin
		forever begin
		#1;
		OUT1 <= number[3:0];
		OUT2 <= number[7:4];
		OUT3 <= number[11:8];
		OUT4 <= number[15:12];
		end
	end
      
endmodule
module calkkoTest;



	reg [3:0] A1;
	reg [3:0] A2;
	reg [3:0] A3;
	reg [3:0] A4;
	reg [3:0] B1;
	reg [3:0] B2;
	reg [3:0] B3;
	reg [3:0] B4;
	reg [1:0] ST;
	reg [2:0] ST_L;
	
	reg [3:0] OUT1, OUT2, OUT3, OUT4;


	wire set;
	wire [15:0] number;


	Calkko uut (
		.A1(A1), 
		.A2(A2), 
		.A3(A3), 
		.A4(A4), 
		.B1(B1), 
		.B2(B2), 
		.B3(B3), 
		.B4(B4), 
		.ST(ST), 
		.ST_L(ST_L), 
		.set(set), 
		.number(number)
	);

	initial begin
		ST = `S_OBL;
		
		A1 = 4'd0;
		A2 = 4'd0;
		A3 = 4'd0;
		A4 = 4'd5;
		
		B1 = 4'd0;
		B2 = 4'd0;
		B3 = 4'd0;
		B4 = 4'd1;
		
		
		ST_L = `SL_ADD;
		#10;
		ST_L = `SL_SUB;
		#10;
		ST_L = `SL_XOR;
		#10;
		ST_L = `SL_OR;
		#10;
		ST_L = `SL_AND;

	end
	
	initial begin
		forever begin
		#1;
		OUT1 <= number[3:0];
		OUT2 <= number[7:4];
		OUT3 <= number[11:8];
		OUT4 <= number[15:12];
		end
	end
      
endmodule