data/full_repos/permissive/170013753/test/ram_tb.v
 line:23: before: "+"
1: b'%Error: data/full_repos/permissive/170013753/test/ram_tb.v:2: Cannot find include file: src/ram.v\n`include "src/ram.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170013753/test,data/full_repos/permissive/170013753/src/ram.v\n             data/full_repos/permissive/170013753/test,data/full_repos/permissive/170013753/src/ram.v.v\n             data/full_repos/permissive/170013753/test,data/full_repos/permissive/170013753/src/ram.v.sv\n             src/ram.v\n             src/ram.v.v\n             src/ram.v.sv\n             obj_dir/src/ram.v\n             obj_dir/src/ram.v.v\n             obj_dir/src/ram.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/170013753/test/ram_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    clk = ~clk; #5;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/170013753/test/ram_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("out/ram.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/170013753/test/ram_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, ram_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/170013753/test/ram_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/170013753/test/ram_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/170013753/test/ram_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/170013753/test/ram_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/170013753/test/ram_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/170013753/test/ram_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/170013753/test/ram_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: Exiting due to 3 error(s), 8 warning(s)\n'
module ram_tb;

  reg clk  = 1'b0;
  reg wen  = 1'b0;
  reg ren  = 1'b0;

  reg [15:0] din = 16'b0;
  reg [15:0] addr = 16'b0;

  wire [15:0] dout;

  integer testIndex = 0;

  ram UUT(clk, wen, ren, din, addr, dout);

  always begin
    clk = ~clk; #5;
  end

  initial begin
    $dumpfile("out/ram.vcd");
    $dumpvars(0, ram_tb);
    
    din = 16'b0000000011111111;
    #10;

    wen = 1'b1;
    testIndex++;
    #10;
    
    wen = 1'b0;
    din = 16'b0000000000000001;
    addr++;
    testIndex++;
    #10;

    wen = 1'b1;
    testIndex++;
    #10;

    wen = 1'b0;
    testIndex++;
    #10;

    addr--;
    testIndex++;
    #10;

    addr--;
    testIndex++;
    #10;


    $finish;
    $display("Testbench completed");
  end

endmodule
module ram_tb;


  reg clk  = 1'b0;
  reg wen  = 1'b0;
  reg ren  = 1'b0;

  reg [15:0] din = 16'b0;
  reg [15:0] addr = 16'b0;

  wire [15:0] dout;

  integer testIndex = 0;

  ram UUT(clk, wen, ren, din, addr, dout);

  always begin
    clk = ~clk; #5;
  end

  initial begin
    $dumpfile("out/ram.vcd");
    $dumpvars(0, ram_tb);
    
    din = 16'b0000000011111111;
    #10;

    wen = 1'b1;
    testIndex++;
    #10;
    
    wen = 1'b0;
    din = 16'b0000000000000001;
    addr++;
    testIndex++;
    #10;

    wen = 1'b1;
    testIndex++;
    #10;

    wen = 1'b0;
    testIndex++;
    #10;

    addr--;
    testIndex++;
    #10;

    addr--;
    testIndex++;
    #10;


    $finish;
    $display("Testbench completed");
  end

endmodule