data/full_repos/permissive/126791278/testbenches/tb_instructionRegister.v
 line:71: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_instructionRegister.v:24: Unsupported: Ignoring delay on this delayed statement.\n #00 clk = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_instructionRegister.v:25: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_instructionRegister.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #0 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_instructionRegister.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #17  D_MemData = 16\'b1000_1011_0100_1000; C_IRWrite = 1\'b1; rst = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_instructionRegister.v:49: Unsupported: Ignoring delay on this delayed statement.\n   #17  C_IRWrite = 1\'b0; rst = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_instructionRegister.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #17  C_IRWrite = 1\'b0; rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_instructionRegister.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #17  C_IRWrite = 1\'b1; rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_instructionRegister.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #17  D_MemData = 16\'b0010_1011_11001001; C_IRWrite = 1\'b1; rst = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_instructionRegister.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #17  $stop;\n  ^\n%Error: data/full_repos/permissive/126791278/testbenches/tb_instructionRegister.v:76: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("instructionRegister.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/126791278/testbenches/tb_instructionRegister.v:77: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_instructionRegister();

	wire [3:0] OPCODE, FUNCFIELD;
	wire [3:0] A_ReadReg1RT, A_ReadReg2RT;
	wire [1:0] A_Offset, A_RegSWLW;
	wire [3:0] A_WriteRegRT_BT;

	reg [15:0] D_MemData;
	reg C_IRWrite;
	reg clk, rst;

	instructionRegister uut(	OPCODE, FUNCFIELD,
								A_ReadReg1RT, A_ReadReg2RT,
								A_Offset, A_RegSWLW,
								A_WriteRegRT_BT,
								D_MemData,
								C_IRWrite,
								clk, rst
								);

	initial
	begin
	#00 clk = 1'b0;
	forever #10 clk = ~clk;
	end

	initial
		begin
		#0 rst = 1;
		#17  D_MemData = 16'b1000_1011_0100_1000; C_IRWrite = 1'b1; rst = 0;
#17  C_IRWrite = 1'b0; rst = 0;
		#17  C_IRWrite = 1'b0; rst = 1;
		#17  C_IRWrite = 1'b1; rst = 1;

		#17  D_MemData = 16'b0010_1011_11001001; C_IRWrite = 1'b1; rst = 0;
		#17  $stop;
		end

	initial
		begin
		$dumpfile("instructionRegister.vcd");
		$dumpvars;
		end

endmodule
module tb_instructionRegister();


	wire [3:0] OPCODE, FUNCFIELD;
	wire [3:0] A_ReadReg1RT, A_ReadReg2RT;
	wire [1:0] A_Offset, A_RegSWLW;
	wire [3:0] A_WriteRegRT_BT;

	reg [15:0] D_MemData;
	reg C_IRWrite;
	reg clk, rst;

	instructionRegister uut(	OPCODE, FUNCFIELD,
								A_ReadReg1RT, A_ReadReg2RT,
								A_Offset, A_RegSWLW,
								A_WriteRegRT_BT,
								D_MemData,
								C_IRWrite,
								clk, rst
								);

	initial
	begin
	#00 clk = 1'b0;
	forever #10 clk = ~clk;
	end

	initial
		begin
		#0 rst = 1;
		#17  D_MemData = 16'b1000_1011_0100_1000; C_IRWrite = 1'b1; rst = 0;
#17  C_IRWrite = 1'b0; rst = 0;
		#17  C_IRWrite = 1'b0; rst = 1;
		#17  C_IRWrite = 1'b1; rst = 1;

		#17  D_MemData = 16'b0010_1011_11001001; C_IRWrite = 1'b1; rst = 0;
		#17  $stop;
		end

	initial
		begin
		$dumpfile("instructionRegister.vcd");
		$dumpvars;
		end

endmodule