data/full_repos/permissive/219891072/add.v
data/verilator_xmls/b1e538d5-40dd-47e3-82bf-c771132145cd.xml
module add (
  input  wire a, b, c,
  output wire g, p, s );

  assign s = a ^ b ^ c;
  assign g = a & b;
  assign p = a | b;
endmodule
module add (
  input  wire a, b, c,
  output wire g, p, s );


  assign s = a ^ b ^ c;
  assign g = a & b;
  assign p = a | b;
endmodule