data/full_repos/permissive/106966316/alu32_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#50 clk = 1\'b1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n#50 clk = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #100;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n #100;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n #100;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #100;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n #100;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n #100;  \n ^\n%Error: data/full_repos/permissive/106966316/alu32_tb.v:33: Cannot find file containing module: \'alu32\'\nalu32 uut(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/alu32\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/alu32.v\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/alu32.sv\n             alu32\n             alu32.v\n             alu32.sv\n             obj_dir/alu32\n             obj_dir/alu32.v\n             obj_dir/alu32.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu32_tb();

reg [31:0] data1;
reg [31:0] data2;
reg [2:0] ctrl;
reg clk;
wire oCarry;
wire oZero;
wire [31:0]out;

alu32 uut(
	.data1(data1),
	.data2(data2),
	.ctrl(ctrl),
	.clk(clk),
	.oCarry(oCarry),
	.oZero(oZero),
	.out(out)
	);

always begin

#50 clk = 1'b1;
#50 clk = 1'b0;
end



initial begin

    data1 = 32'b11111111_11111111_11111111_11111111;
    data2 = 32'b11111111_11111111_11111111_11111111;
	ctrl = 3'b000;

	#100; 


	data1 = 32'b11111111_11111111_11111111_11111111;
	data2 = 32'b00000000_00000000_00000000_00000001;
	ctrl = 3'b000;

	#100;
	
	data1 = 32'b11111111_11111111_11111111_11111111;
    data2 = 32'b11111111_11111111_11111111_11111111;
	ctrl = 3'b001;

	#100;


	data1 = 32'b11111111_11111111_11111111_11111111;
	data2 = 32'b00000000_00000000_00000000_00000001;
	ctrl = 3'b001;

	#100;

	data1 = 32'b00000000_00000000_00000000_00000000;
	data2 = 32'b00000000_00000000_00000000_00000000;
	ctrl = 3'b001;

	#100;

	data1 = 32'b11111111_11111111_11111111_11111111;
    data2 = 32'b11111111_11111111_11111111_11111111;
	ctrl = 3'b010;

	#100;


	data1 = 32'b11111111_11111111_11111111_11111111;
	data2 = 32'b00000000_00001000_00000000_00000000;
	ctrl = 3'b010;

	#100;

	data1 = 32'b11111111_11111111_11111111_11111111;
    data2 = 32'b11111111_11111111_11111111_11111111;
	ctrl = 3'b011;

	#100;


	data1 = 32'b11111111_11111111_11111111_11111111;
	data2 = 32'b00000000_00000000_00000000_00000000;
	ctrl = 3'b011;

	#100;

	data1 = 32'b11111111_11111111_11111111_11111111;
    data2 = 32'b11111111_11111111_11111111_11111111;
	ctrl = 3'b100;

	#100;


	data1 = 32'b11111111_11111111_11111111_11111110;
	data2 = 32'b00000000_00000000_00000000_00000000;
	ctrl = 3'b100;

	#100;


end 


endmodule
module alu32_tb();


reg [31:0] data1;
reg [31:0] data2;
reg [2:0] ctrl;
reg clk;
wire oCarry;
wire oZero;
wire [31:0]out;

alu32 uut(
	.data1(data1),
	.data2(data2),
	.ctrl(ctrl),
	.clk(clk),
	.oCarry(oCarry),
	.oZero(oZero),
	.out(out)
	);

always begin

#50 clk = 1'b1;
#50 clk = 1'b0;
end



initial begin

    data1 = 32'b11111111_11111111_11111111_11111111;
    data2 = 32'b11111111_11111111_11111111_11111111;
	ctrl = 3'b000;

	#100; 


	data1 = 32'b11111111_11111111_11111111_11111111;
	data2 = 32'b00000000_00000000_00000000_00000001;
	ctrl = 3'b000;

	#100;
	
	data1 = 32'b11111111_11111111_11111111_11111111;
    data2 = 32'b11111111_11111111_11111111_11111111;
	ctrl = 3'b001;

	#100;


	data1 = 32'b11111111_11111111_11111111_11111111;
	data2 = 32'b00000000_00000000_00000000_00000001;
	ctrl = 3'b001;

	#100;

	data1 = 32'b00000000_00000000_00000000_00000000;
	data2 = 32'b00000000_00000000_00000000_00000000;
	ctrl = 3'b001;

	#100;

	data1 = 32'b11111111_11111111_11111111_11111111;
    data2 = 32'b11111111_11111111_11111111_11111111;
	ctrl = 3'b010;

	#100;


	data1 = 32'b11111111_11111111_11111111_11111111;
	data2 = 32'b00000000_00001000_00000000_00000000;
	ctrl = 3'b010;

	#100;

	data1 = 32'b11111111_11111111_11111111_11111111;
    data2 = 32'b11111111_11111111_11111111_11111111;
	ctrl = 3'b011;

	#100;


	data1 = 32'b11111111_11111111_11111111_11111111;
	data2 = 32'b00000000_00000000_00000000_00000000;
	ctrl = 3'b011;

	#100;

	data1 = 32'b11111111_11111111_11111111_11111111;
    data2 = 32'b11111111_11111111_11111111_11111111;
	ctrl = 3'b100;

	#100;


	data1 = 32'b11111111_11111111_11111111_11111110;
	data2 = 32'b00000000_00000000_00000000_00000000;
	ctrl = 3'b100;

	#100;


end 


endmodule