data/full_repos/permissive/113471686/baseline/src/mtree.v
data/verilator_xmls/114311fa-51f3-493b-ba7c-2d8fc389679a.xml
module MERGE_SORTER_TREE #(parameter                       W_LOG = 2,
                           parameter                       DATW  = 64,
                           parameter                       KEYW  = 32)
                          (input  wire                     CLK,
                           input  wire                     RST,
                           input  wire                     IN_FULL,
                           input  wire [(DATW<<W_LOG)-1:0] DIN,
                           input  wire [(1<<W_LOG)-1:0]    DINEN,
                           output wire [(1<<W_LOG)-1:0]    FULL,
                           output wire [DATW-1:0]          DOT,
                           output wire                     DOTEN);

  genvar i, j;
  generate
    for (i=0; i<W_LOG; i=i+1) begin: level
      wire [(1<<(W_LOG-(i+1)))-1:0]    node_in_full;
      wire [(DATW<<(W_LOG-i))-1:0]     node_din;
      wire [(1<<(W_LOG-i))-1:0]        node_dinen;
      wire [(1<<(W_LOG-i))-1:0]        node_full;
      wire [(DATW<<(W_LOG-(i+1)))-1:0] node_dot;
      wire [(1<<(W_LOG-(i+1)))-1:0]    node_doten;
      for (j=0; j<(1<<(W_LOG-(i+1))); j=j+1) begin: nodes
        TREE_NODE #(DATW, KEYW)
        tree_node(CLK, RST, node_in_full[j], node_din[DATW*(2*j+1)-1:DATW*(2*j)], node_dinen[2*j], node_din[DATW*(2*j+2)-1:DATW*(2*j+1)], node_dinen[2*j+1], 
                  node_full[2*j], node_full[2*j+1], node_dot[DATW*(j+1)-1:DATW*j], node_doten[j]);
      end
    end
  endgenerate

  generate
    for (i=0; i<W_LOG; i=i+1) begin: connection
      if (i == 0) begin
        assign level[0].node_din   = DIN;
        assign level[0].node_dinen = DINEN;
        assign FULL                = level[0].node_full;
      end else begin
        assign level[i].node_din       = level[i-1].node_dot;
        assign level[i].node_dinen     = level[i-1].node_doten;
        assign level[i-1].node_in_full = level[i].node_full;
      end
    end
  endgenerate

  assign level[W_LOG-1].node_in_full = IN_FULL;
  assign DOT                         = level[W_LOG-1].node_dot;
  assign DOTEN                       = level[W_LOG-1].node_doten;
  
endmodule
module MERGE_SORTER_TREE #(parameter                       W_LOG = 2,
                           parameter                       DATW  = 64,
                           parameter                       KEYW  = 32)
                          (input  wire                     CLK,
                           input  wire                     RST,
                           input  wire                     IN_FULL,
                           input  wire [(DATW<<W_LOG)-1:0] DIN,
                           input  wire [(1<<W_LOG)-1:0]    DINEN,
                           output wire [(1<<W_LOG)-1:0]    FULL,
                           output wire [DATW-1:0]          DOT,
                           output wire                     DOTEN);


  genvar i, j;
  generate
    for (i=0; i<W_LOG; i=i+1) begin: level
      wire [(1<<(W_LOG-(i+1)))-1:0]    node_in_full;
      wire [(DATW<<(W_LOG-i))-1:0]     node_din;
      wire [(1<<(W_LOG-i))-1:0]        node_dinen;
      wire [(1<<(W_LOG-i))-1:0]        node_full;
      wire [(DATW<<(W_LOG-(i+1)))-1:0] node_dot;
      wire [(1<<(W_LOG-(i+1)))-1:0]    node_doten;
      for (j=0; j<(1<<(W_LOG-(i+1))); j=j+1) begin: nodes
        TREE_NODE #(DATW, KEYW)
        tree_node(CLK, RST, node_in_full[j], node_din[DATW*(2*j+1)-1:DATW*(2*j)], node_dinen[2*j], node_din[DATW*(2*j+2)-1:DATW*(2*j+1)], node_dinen[2*j+1], 
                  node_full[2*j], node_full[2*j+1], node_dot[DATW*(j+1)-1:DATW*j], node_doten[j]);
      end
    end
  endgenerate

  generate
    for (i=0; i<W_LOG; i=i+1) begin: connection
      if (i == 0) begin
        assign level[0].node_din   = DIN;
        assign level[0].node_dinen = DINEN;
        assign FULL                = level[0].node_full;
      end else begin
        assign level[i].node_din       = level[i-1].node_dot;
        assign level[i].node_dinen     = level[i-1].node_doten;
        assign level[i-1].node_in_full = level[i].node_full;
      end
    end
  endgenerate

  assign level[W_LOG-1].node_in_full = IN_FULL;
  assign DOT                         = level[W_LOG-1].node_dot;
  assign DOTEN                       = level[W_LOG-1].node_doten;
  
endmodule