data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_port.v
1: b'%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_port.v:62: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3c7\' generates 10 bits.\n                                                                                             : ... In instance serial_port\n initial ctrl = 10\'h3C7;  \n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_port.v:72: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h3c7\' generates 10 bits.\n                                                                                             : ... In instance serial_port\n   ctrl <= 10\'h3C7;  \n        ^~\n%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_port.v:200: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'stat\' generates 5 bits.\n                                                                                              : ... In instance serial_port\n                  data = stat;      \n                       ^\n%Error: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_port.v:217: Cannot find file containing module: \'transmitter\'\n transmitter transmitter(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1,data/full_repos/permissive/172396252/transmitter\n             data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1,data/full_repos/permissive/172396252/transmitter.v\n             data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1,data/full_repos/permissive/172396252/transmitter.sv\n             transmitter\n             transmitter.v\n             transmitter.sv\n             obj_dir/transmitter\n             obj_dir/transmitter.v\n             obj_dir/transmitter.sv\n%Error: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_port.v:228: Cannot find file containing module: \'receiver\'\n receiver receiver(\n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module serial_port(
  	input rst_n,
    input clk,

    input read_enable,
    input write_enable,
    inout [31:0] data_bus,
    input [19:0] address_bus,

    output reg serial_irq_n,

    output Tx,
    input Rx
	); 
	

	reg [7:0] TxData, next_TxData;
	reg [7:0] RxData, next_RxData;
	reg [10:0] ctrl, next_ctrl;
	reg [4:0] stat, next_stat;
	reg [2:0] int_ack, next_int_ack;
	
	wire finishedTX, startRX, finishedRX, parityErr, frammingErr;
    wire [7:0] newRxData;

	reg [14:0] baudRate;

	reg [31:0] data;
	assign data_bus = read_enable ? data : 32'hzzzzzzzz;

	reg [1:0] TXstat;
	reg [1:0] RXstat;

	reg startTX, next_startTX;


	initial TxData = 0;
	initial RxData = 0;
	initial ctrl = 10'h3C7;
	initial stat = 2;
	initial int_ack = 0;
	
	
	always @(posedge clk) begin
		if (!rst_n) begin     
			RxData <= 0;
			TxData <= 0;

			ctrl <= 10'h3C7;


			int_ack <= 0;
			stat <= 2;

			TXstat <= 0;
			RXstat <= 0;
			startTX <= 0;

		end 
		else begin
			RxData <= next_RxData;
			TxData <= next_TxData;
			ctrl <= next_ctrl;
			int_ack <= next_int_ack;
			stat <= next_stat;

			TXstat[1:0] <= {TXstat[1],finishedTX};
			RXstat[1:0] <= {RXstat[1],finishedRX};

			startTX <= next_startTX;
		end
	end		
		
		
	always @(*) begin



		case (ctrl[2:0])
		 	3'b000: begin
                 baudRate <= 20833;
            end
            3'b001: begin
                baudRate <= 10417;
            end
            3'b010: begin
                baudRate <= 5208;
            end
            3'b011: begin
                baudRate <= 2604;
            end
            3'b100: begin
                baudRate <= 1302;
            end
            3'b101: begin
                baudRate <= 651;
            end
            3'b110: begin
                baudRate <= 326;
            end
            3'b111: begin
                baudRate <= 163;
            end
		endcase

            
		 next_RxData = RxData;
		 next_TxData = TxData;
		 next_ctrl = ctrl;
		 next_int_ack = int_ack;		 
		 next_stat = stat;
		 next_startTX = 0;

		 if (RXstat == 2'b01) begin
		 	
		 	
		 			 
            next_stat[4] = parityErr;
            next_stat[3] = frammingErr;
		 	next_stat[2] = stat[0];
		 	
		 	next_stat[0] = 1;
		 	next_int_ack[0] = ctrl[8];
		 	next_RxData = newRxData;

			 next_int_ack[2] = ctrl[10] & (parityErr | frammingErr | stat[0]); 
		 end

		 if (TXstat == 2'b01) begin
		 	next_stat[1] = 1;
		 	next_int_ack[1] = ctrl[9];
		 end
		
	
		 data = 32'h00000000;
		 case (address_bus[11:0])
		 	0: begin
		 		if (write_enable) begin
		 			 next_stat[1] = 0;
		             next_TxData = data_bus[7:0];
		             next_startTX = 1;
		         end else begin 
		         	data[7:0] = 0;
		         end
		 	end
			
		 	1: begin
		 		if (read_enable) begin
		            next_stat[0] = 0;
		 			data[7:0] = RxData;		
		         end
		 	end
			
		 	2: begin
		 		if (write_enable) begin
		 			next_ctrl = data_bus[10:0];			
		 		end
		 		else data[10:0] = ctrl;
		 	end
			
		 	3: begin
		 		if (read_enable) begin
                 	data = stat;
		 		end
		 	end
			
		 	4: begin
                 if (write_enable) begin
		 			next_int_ack = data_bus[2:0];
		 			next_stat = stat & 3;		


		 		end
		 		else data[2:0] = int_ack;
		 	end			
		 endcase
		 serial_irq_n = int_ack == 0;
	end
	
	transmitter transmitter(
        .rst_n(rst_n),
        .clk(clk),
        .TxD(TxData),
        .ctrl(ctrl),
        .startTx(startTX),
        .finished(finishedTX),
        .Tx(Tx),
        .baudRate(baudRate)
	);
		
	receiver receiver(
		.rst_n(rst_n),
		.clk(clk),
		.RxD(newRxData),
		.ctrl(ctrl),
		.startRx(startRX),
		.finished(finishedRX),
		.Rx(Rx),
		.parityErr(parityErr), 
		.frammingErr(frammingErr),
		.baudRate(baudRate)
	);
endmodule
module serial_port(
  	input rst_n,
    input clk,

    input read_enable,
    input write_enable,
    inout [31:0] data_bus,
    input [19:0] address_bus,

    output reg serial_irq_n,

    output Tx,
    input Rx
	);
 
	

	reg [7:0] TxData, next_TxData;
	reg [7:0] RxData, next_RxData;
	reg [10:0] ctrl, next_ctrl;
	reg [4:0] stat, next_stat;
	reg [2:0] int_ack, next_int_ack;
	
	wire finishedTX, startRX, finishedRX, parityErr, frammingErr;
    wire [7:0] newRxData;

	reg [14:0] baudRate;

	reg [31:0] data;
	assign data_bus = read_enable ? data : 32'hzzzzzzzz;

	reg [1:0] TXstat;
	reg [1:0] RXstat;

	reg startTX, next_startTX;


	initial TxData = 0;
	initial RxData = 0;
	initial ctrl = 10'h3C7;
	initial stat = 2;
	initial int_ack = 0;
	
	
	always @(posedge clk) begin
		if (!rst_n) begin     
			RxData <= 0;
			TxData <= 0;

			ctrl <= 10'h3C7;


			int_ack <= 0;
			stat <= 2;

			TXstat <= 0;
			RXstat <= 0;
			startTX <= 0;

		end 
		else begin
			RxData <= next_RxData;
			TxData <= next_TxData;
			ctrl <= next_ctrl;
			int_ack <= next_int_ack;
			stat <= next_stat;

			TXstat[1:0] <= {TXstat[1],finishedTX};
			RXstat[1:0] <= {RXstat[1],finishedRX};

			startTX <= next_startTX;
		end
	end		
		
		
	always @(*) begin



		case (ctrl[2:0])
		 	3'b000: begin
                 baudRate <= 20833;
            end
            3'b001: begin
                baudRate <= 10417;
            end
            3'b010: begin
                baudRate <= 5208;
            end
            3'b011: begin
                baudRate <= 2604;
            end
            3'b100: begin
                baudRate <= 1302;
            end
            3'b101: begin
                baudRate <= 651;
            end
            3'b110: begin
                baudRate <= 326;
            end
            3'b111: begin
                baudRate <= 163;
            end
		endcase

            
		 next_RxData = RxData;
		 next_TxData = TxData;
		 next_ctrl = ctrl;
		 next_int_ack = int_ack;		 
		 next_stat = stat;
		 next_startTX = 0;

		 if (RXstat == 2'b01) begin
		 	
		 	
		 			 
            next_stat[4] = parityErr;
            next_stat[3] = frammingErr;
		 	next_stat[2] = stat[0];
		 	
		 	next_stat[0] = 1;
		 	next_int_ack[0] = ctrl[8];
		 	next_RxData = newRxData;

			 next_int_ack[2] = ctrl[10] & (parityErr | frammingErr | stat[0]); 
		 end

		 if (TXstat == 2'b01) begin
		 	next_stat[1] = 1;
		 	next_int_ack[1] = ctrl[9];
		 end
		
	
		 data = 32'h00000000;
		 case (address_bus[11:0])
		 	0: begin
		 		if (write_enable) begin
		 			 next_stat[1] = 0;
		             next_TxData = data_bus[7:0];
		             next_startTX = 1;
		         end else begin 
		         	data[7:0] = 0;
		         end
		 	end
			
		 	1: begin
		 		if (read_enable) begin
		            next_stat[0] = 0;
		 			data[7:0] = RxData;		
		         end
		 	end
			
		 	2: begin
		 		if (write_enable) begin
		 			next_ctrl = data_bus[10:0];			
		 		end
		 		else data[10:0] = ctrl;
		 	end
			
		 	3: begin
		 		if (read_enable) begin
                 	data = stat;
		 		end
		 	end
			
		 	4: begin
                 if (write_enable) begin
		 			next_int_ack = data_bus[2:0];
		 			next_stat = stat & 3;		


		 		end
		 		else data[2:0] = int_ack;
		 	end			
		 endcase
		 serial_irq_n = int_ack == 0;
	end
	
	transmitter transmitter(
        .rst_n(rst_n),
        .clk(clk),
        .TxD(TxData),
        .ctrl(ctrl),
        .startTx(startTX),
        .finished(finishedTX),
        .Tx(Tx),
        .baudRate(baudRate)
	);
		
	receiver receiver(
		.rst_n(rst_n),
		.clk(clk),
		.RxD(newRxData),
		.ctrl(ctrl),
		.startRx(startRX),
		.finished(finishedRX),
		.Rx(Rx),
		.parityErr(parityErr), 
		.frammingErr(frammingErr),
		.baudRate(baudRate)
	);
endmodule