data/full_repos/permissive/204486675/hdl/buspirate.v
1: b'%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:5: Cannot find include file: iobuf.v\n`include "iobuf.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/204486675/hdl,data/full_repos/permissive/204486675/iobuf.v\n             data/full_repos/permissive/204486675/hdl,data/full_repos/permissive/204486675/iobuf.v.v\n             data/full_repos/permissive/204486675/hdl,data/full_repos/permissive/204486675/iobuf.v.sv\n             iobuf.v\n             iobuf.v.v\n             iobuf.v.sv\n             obj_dir/iobuf.v\n             obj_dir/iobuf.v.v\n             obj_dir/iobuf.v.sv\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:6: Cannot find include file: iobufphy.v\n`include "iobufphy.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:7: Cannot find include file: synchronizer.v\n`include "synchronizer.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:8: Cannot find include file: pwm.v\n`include "pwm.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:9: Cannot find include file: pll.v\n`include "pll.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:10: Cannot find include file: registers.v\n`include "registers.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:11: Cannot find include file: spimaster.v\n`include "spimaster.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:12: Cannot find include file: fifo.v\n`include "fifo.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:13: Cannot find include file: adc.v\n`include "adc.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:75: Define or directive not defined: \'`reg_bpio_oe\'\n      .oe(`reg_bpio_oe),  \n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:76: Define or directive not defined: \'`reg_bpio_od\'\n      .od(`reg_bpio_od),  \n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:77: Define or directive not defined: \'`reg_bpio_dir\'\n      .dir(`reg_bpio_dir), \n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:95: Define or directive not defined: \'`reg_pwm_on\'\n    pwm PWM_OUT(pwm_reset, count[0],pwm_out, `reg_pwm_on,`reg_pwm_off);\n                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:95: Define or directive not defined: \'`reg_pwm_off\'\n    pwm PWM_OUT(pwm_reset, count[0],pwm_out, `reg_pwm_on,`reg_pwm_off);\n                                                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:105: Define or directive not defined: \'`reg_adc_en\'\n    assign adc_mux_en=`reg_adc_en;\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    assign adc_mux_en=`reg_adc_en;\n                                 ^\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:106: Define or directive not defined: \'`reg_adc_s\'\n    assign adc_mux_s=`reg_adc_s;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:106: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    assign adc_mux_s=`reg_adc_s;\n                               ^\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:126: Define or directive not defined: \'`reg_la_active\'\n    assign sram_clock_source=(la_start&&`reg_la_active)?clock:(`reg_la_io_quad)?sram_auto_clock:(`reg_la_io_spi)?mcu_clock:1\'b0;\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign sram_clock_source=(la_start&&`reg_la_active)?clock:(`reg_la_io_quad)?sram_auto_clock:(`reg_la_io_spi)?mcu_clock:1\'b0;\n                                                      ^\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:126: Define or directive not defined: \'`reg_la_io_quad\'\n    assign sram_clock_source=(la_start&&`reg_la_active)?clock:(`reg_la_io_quad)?sram_auto_clock:(`reg_la_io_spi)?mcu_clock:1\'b0;\n                                                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:126: Define or directive not defined: \'`reg_la_io_spi\'\n    assign sram_clock_source=(la_start&&`reg_la_active)?clock:(`reg_la_io_quad)?sram_auto_clock:(`reg_la_io_spi)?mcu_clock:1\'b0;\n                                                                                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:128: Define or directive not defined: \'`reg_la_active\'\n    assign sram_cs=(la_start&&`reg_la_active)?2\'b00:{`reg_la_io_cs1,`reg_la_io_cs0};  \n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:128: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign sram_cs=(la_start&&`reg_la_active)?2\'b00:{`reg_la_io_cs1,`reg_la_io_cs0};  \n                                            ^\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:128: Define or directive not defined: \'`reg_la_io_cs1\'\n    assign sram_cs=(la_start&&`reg_la_active)?2\'b00:{`reg_la_io_cs1,`reg_la_io_cs0};  \n                                                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:128: Define or directive not defined: \'`reg_la_io_cs0\'\n    assign sram_cs=(la_start&&`reg_la_active)?2\'b00:{`reg_la_io_cs1,`reg_la_io_cs0};  \n                                                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:129: Define or directive not defined: \'`reg_la_active\'\n    assign sram_sio_tdo[0]=(la_start&&`reg_la_active)?lat[0]:`reg_la_io_quad?`reg_la_write[0]:mcu_mosi;\n                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:129: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign sram_sio_tdo[0]=(la_start&&`reg_la_active)?lat[0]:`reg_la_io_quad?`reg_la_write[0]:mcu_mosi;\n                                                    ^\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:129: Define or directive not defined: \'`reg_la_io_quad\'\n    assign sram_sio_tdo[0]=(la_start&&`reg_la_active)?lat[0]:`reg_la_io_quad?`reg_la_write[0]:mcu_mosi;\n                                                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:129: Define or directive not defined: \'`reg_la_write\'\n    assign sram_sio_tdo[0]=(la_start&&`reg_la_active)?lat[0]:`reg_la_io_quad?`reg_la_write[0]:mcu_mosi;\n                                                                             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:130: Define or directive not defined: \'`reg_la_active\'\n    assign sram_sio_tdo[4]=(la_start&&`reg_la_active)?lat[4]:`reg_la_io_quad?`reg_la_write[4]:mcu_mosi;\n                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:130: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign sram_sio_tdo[4]=(la_start&&`reg_la_active)?lat[4]:`reg_la_io_quad?`reg_la_write[4]:mcu_mosi;\n                                                    ^\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:130: Define or directive not defined: \'`reg_la_io_quad\'\n    assign sram_sio_tdo[4]=(la_start&&`reg_la_active)?lat[4]:`reg_la_io_quad?`reg_la_write[4]:mcu_mosi;\n                                                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:130: Define or directive not defined: \'`reg_la_write\'\n    assign sram_sio_tdo[4]=(la_start&&`reg_la_active)?lat[4]:`reg_la_io_quad?`reg_la_write[4]:mcu_mosi;\n                                                                             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:131: Define or directive not defined: \'`reg_la_active\'\n    assign {sram_sio_tdo[7:5],sram_sio_tdo[3:1]}=(la_start&&`reg_la_active)?{lat[7:5],lat[3:1]}:{`reg_la_write[7:5],`reg_la_write[3:1]};\n                                                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:131: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign {sram_sio_tdo[7:5],sram_sio_tdo[3:1]}=(la_start&&`reg_la_active)?{lat[7:5],lat[3:1]}:{`reg_la_write[7:5],`reg_la_write[3:1]};\n                                                                          ^\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:131: Define or directive not defined: \'`reg_la_write\'\n    assign {sram_sio_tdo[7:5],sram_sio_tdo[3:1]}=(la_start&&`reg_la_active)?{lat[7:5],lat[3:1]}:{`reg_la_write[7:5],`reg_la_write[3:1]};\n                                                                                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:131: Define or directive not defined: \'`reg_la_write\'\n    assign {sram_sio_tdo[7:5],sram_sio_tdo[3:1]}=(la_start&&`reg_la_active)?{lat[7:5],lat[3:1]}:{`reg_la_write[7:5],`reg_la_write[3:1]};\n                                                                                                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:132: Define or directive not defined: \'`reg_la_io_cs0\'\n    assign mcu_miso=!`reg_la_io_cs0?sram_sio_tdi[1]:sram_sio_tdi[5];  \n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:132: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n    assign mcu_miso=!`reg_la_io_cs0?sram_sio_tdi[1]:sram_sio_tdi[5];  \n                                   ^\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:137: Define or directive not defined: \'`reg_la_sample_count\'\n      assign reg_la_sample_count=`reg_la_sample_count;\n                                 ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:137: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      assign reg_la_sample_count=`reg_la_sample_count;\n                                                     ^\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:280: Define or directive not defined: \'`reg_bpsm_reset\'\n      if(`reg_bpsm_reset||reset) begin\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:280: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n      if(`reg_bpsm_reset||reset) begin\n                        ^~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:286: syntax error, unexpected else\n       else\n       ^~~~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:355: syntax error, unexpected <=, expecting IDENTIFIER\n                    bpsm_state <= 8;\n                               ^~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:357: syntax error, unexpected <=, expecting IDENTIFIER\n                    delay_counter <= delay_counter - 1;\n                                  ^~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:365: syntax error, unexpected <=, expecting IDENTIFIER\n                    bpsm_state <= 8;\n                               ^~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:376: syntax error, unexpected <=, expecting IDENTIFIER\n                    bpsm_state <= 8;\n                               ^~\n%Error: data/full_repos/permissive/204486675/hdl/buspirate.v:406: Define or directive not defined: \'`reg_bpsm_reset\'\n              `reg_bpsm_reset<=1\'b1;  \n              ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module top #(
  parameter MC_DATA_WIDTH = 16,
  parameter MC_ADD_WIDTH = 6,
  parameter LA_WIDTH = 8,
  parameter LA_CHIPS = 2,
  parameter BP_PINS = 8,
  parameter FIFO_WIDTH = 16,
  parameter FIFO_DEPTH = 512
) (
  input clock,

  inout wire [BP_PINS-1:0] bpio_buffer_io,
  output wire [BP_PINS-1:0] bpio_buffer_dir, bpio_buffer_od,
  output wire[LA_CHIPS-1:0] sram_clock,
  output wire[LA_CHIPS-1:0] sram_cs,
  inout[LA_WIDTH-1:0] sram_sio,
  output wire lat_oe, lat_dir,
  input wire [LA_WIDTH-1:0] lat,
  input wire mcu_clock,
  input wire mcu_cs,
  input wire mcu_mosi,
  output wire mcu_miso,
  input wire mc_oe, mc_ce, mc_we,
  input wire [MC_ADD_WIDTH-1:0] mc_add,
  inout [MC_DATA_WIDTH-1:0] mc_data,
  output bp_active,
  output bp_fifo_in_full,
  output bp_fifo_out_nempty,
  input bp_fifo_clear,
  output adc_mux_en,
  output [3:0] adc_mux_s,
  output adc_cs, adc_clock,
  input adc_data,
  output pullup_enable
  );


    wire mc_we_sync,mc_oe_sync,mc_ce_sync;
    sync MC_WE_SYNC(clock, mc_we, mc_we_sync);
    sync MC_OE_SYNC(clock, mc_oe, mc_oe_sync);
    sync MC_CE_SYNC(clock, mc_ce, mc_ce_sync);

    reg [MC_DATA_WIDTH-1:0] wreg [32:0];
    reg [MC_DATA_WIDTH-1:0] rreg [32:0];


    wire [BP_PINS-1:0] bpio_toe, bpio_tdo, bpio_tdi;

    wire [BP_PINS-1:0] bpio_oe,bpio_di,bpio_do,bpio_dir;

    reg [BP_PINS-1:0] bpio_dio_tris_d, bpio_dio_port_d;

    reg bp_busy;
    assign bp_active=in_fifo_out_nempty || peripheral_busy || bp_busy;


    iobuf BPIO_BUF[BP_PINS-1:0] (

      .oe(`reg_bpio_oe),
      .od(`reg_bpio_od),
      .dir(`reg_bpio_dir),
      .din(bpio_do),
      .dout(bpio_di),

      .bufdir(bpio_buffer_dir),
      .bufod(bpio_buffer_od),
      .bufdat_tristate_oe(bpio_toe),
      .bufdat_tristate_dout(bpio_tdo),
      .bufdat_tristate_din(bpio_tdi)
      );
      `define BP_PERIPHERAL_PINS 3
      assign bpio_do[BP_PINS-1:`BP_PERIPHERAL_PINS]=bpio_dio_port_d[BP_PINS-1:`BP_PERIPHERAL_PINS];




    wire pwm_out;
    reg pwm_reset;
    pwm PWM_OUT(pwm_reset, count[0],pwm_out, `reg_pwm_on,`reg_pwm_off);



  	wire [MC_DATA_WIDTH-1:0] mc_din;
    reg [MC_DATA_WIDTH-1:0] mc_dout_d;
    wire [MC_DATA_WIDTH-1:0] mc_dout;
    assign mc_dout=mc_dout_d;


    assign adc_mux_en=`reg_adc_en;
    assign adc_mux_s=`reg_adc_s;


    assign lat_oe=1'b0;
    assign lat_dir=1'b0;
    assign pullup_enable=1'b0;

    localparam N = 3;
    reg [N:0] count;
    reg reset;
    reg [2:0] reset_count;

    reg [7:0] la_sample_prescaler;

    wire [LA_WIDTH-1:0] sram_sio_tdi;
    wire [LA_WIDTH-1:0] sram_sio_tdo;

    reg la_start;
    wire sram_clock_source;
    reg sram_auto_clock, sram_auto_clock_delay;
    assign sram_clock_source=(la_start&&`reg_la_active)?clock:(`reg_la_io_quad)?sram_auto_clock:(`reg_la_io_spi)?mcu_clock:1'b0;
    assign sram_clock={sram_clock_source,sram_clock_source};
    assign sram_cs=(la_start&&`reg_la_active)?2'b00:{`reg_la_io_cs1,`reg_la_io_cs0};
    assign sram_sio_tdo[0]=(la_start&&`reg_la_active)?lat[0]:`reg_la_io_quad?`reg_la_write[0]:mcu_mosi;
    assign sram_sio_tdo[4]=(la_start&&`reg_la_active)?lat[4]:`reg_la_io_quad?`reg_la_write[4]:mcu_mosi;
    assign {sram_sio_tdo[7:5],sram_sio_tdo[3:1]}=(la_start&&`reg_la_active)?{lat[7:5],lat[3:1]}:{`reg_la_write[7:5],`reg_la_write[3:1]};
    assign mcu_miso=!`reg_la_io_cs0?sram_sio_tdi[1]:sram_sio_tdi[5];


    `ifdef SIMULATION
      wire [15:0] reg_la_sample_count;
      assign reg_la_sample_count=`reg_la_sample_count;


    `endif


    wire bp_fifo_clear_sync;
    sync FIFO_CLEAR_SYNC(clock, bp_fifo_clear, bp_fifo_clear_sync);

    wire [MC_DATA_WIDTH-1:0] in_fifo_out_data;
    wire in_fifo_in_nempty,in_fifo_out_nempty;
    reg in_fifo_in_shift,in_fifo_out_pop;

    reg [MC_DATA_WIDTH-1:0] out_fifo_in_data_d;
    wire [MC_DATA_WIDTH-1:0] out_fifo_out_data;
    wire out_fifo_in_nempty, out_fifo_in_full;
    reg out_fifo_in_shift,out_fifo_out_pop;

    reg peripheral_trigger;
    wire peripheral_busy;
    wire[7:0] peripheral_data_out;
    reg [15:0] peripheral_data_in_d;

    fifo #(
      .WIDTH(FIFO_WIDTH),
      .DEPTH(FIFO_DEPTH)
    ) FIFO_IN (
      .reset(bp_fifo_clear_sync),
      .in_clock(clock),
      .in_shift(in_fifo_in_shift),
      .in_data(mc_din),
      .in_full(bp_fifo_in_full),
      .in_nempty(in_fifo_in_nempty),
      .out_clock(clock),
      .out_pop(in_fifo_out_pop),
      .out_data(in_fifo_out_data),
      .out_nempty(in_fifo_out_nempty)
    ), FIFO_OUT (
      .reset(bp_fifo_clear_sync),
      .in_clock(clock),
    	.in_shift(out_fifo_in_shift),
    	.in_data(out_fifo_in_data_d),
    	.in_full(out_fifo_in_full),
    	.in_nempty(out_fifo_in_nempty),
      .out_clock(clock),
    	.out_pop(out_fifo_out_pop),
    	.out_data(out_fifo_out_data),
    	.out_nempty(bp_fifo_out_nempty)
    );

    wire adc_busy;
    reg adc_trigger;
    wire [13:0] adc_data_out;
    reg adc_calibrate;

    adc ADC_SI (

      	.rst(reset),
      	.clkin(clock),

      	.go(adc_trigger),
      	.state(adc_busy),
        .calibrate(adc_calibrate),

      	.data_o(adc_data_out),

      	.sclk(adc_clock),
      	.miso(adc_data),
      	.cs(adc_cs)
      );


     spimaster SPI_MASTER(

       .rst(reset),
       .clkin(clock),

       .cpol(1'b1),
       .cpha(1'b0),
       .cspol(1'b1),


       .go(peripheral_trigger),
       .state(peripheral_busy),

       .data_i(peripheral_data_in_d),
       .data_o(peripheral_data_out),

       .mosi(bpio_do[0]),
       .sclk(bpio_do[1]),
       .miso(bpio_di[2])

       );

    reg [7:0] delay_counter;

    `define STATE_IDLE   0
    `define STATE_WAIT    1
    `define STATE_LASTART   2
    `define STATE_LASTOP 3
    `define STATE_DIO_WRITE 4
    `define STATE_DIO_READ 5
    `define STATE_DELAY 6
    `define STATE_PERIPHERAL_WAIT 7
    `define STATE_POP_FIFO 8
    `define STATE_CLEANUP 9
    `define STATE_HALT 10
    `define STATE_ADC_WAIT 11


    `define CMD_PERIPHERAL_WRITE 8'b0???????
    `define CMD_LASTART 8'b11111110
    `define CMD_LASTOP 8'b11111111
    `define CMD_HALT 8'b11111101
    `define CMD_DIO_WRITE 8'b10000001
    `define CMD_DIO_READ 8'b10000010
    `define CMD_DIO_TRIS 8'b10000011
    `define CMD_DELAY 8'b10000100
    `define CMD_ADC 8'b10000101
    `define CMD_ADC_CALIBRATE 8'b10000110

    reg [$clog2(`STATE_HALT):0] bpsm_state;

    always @(posedge clock)
      begin

      rreg[9][$clog2(`STATE_HALT):0]<=bpsm_state;



      if(reset_count<3) begin
        reset_count<=reset_count+1;
        reset<=1'b1;
        rreg[9]<=16'h00;
      end
      else
      begin
        reset<=1'b0;
      end

      count <= count + 1;
      pwm_reset<=1'b0;

      if(`reg_bpsm_reset||reset) begin
           bpsm_state <= `STATE_IDLE;
           peripheral_trigger <= 1'b0;
           out_fifo_in_shift<=1'b0;
           in_fifo_out_pop<=1'b0;
       end
       else
       begin

         case(bpsm_state)
             `STATE_IDLE: begin
                 if(in_fifo_out_nempty&&!out_fifo_in_full) begin
                     bp_busy <= 1'b1;

                     rreg[10]<=in_fifo_out_data;


                     out_fifo_in_data_d<=in_fifo_out_data;
                     out_fifo_in_shift<=1'b1;
                     bpsm_state<=`STATE_POP_FIFO;

                     casez(in_fifo_out_data[15:8])
                       `CMD_PERIPHERAL_WRITE:
                          begin
                          peripheral_data_in_d <= in_fifo_out_data;
                          peripheral_trigger <= 1'b1;
                          bpsm_state<=`STATE_PERIPHERAL_WAIT;
                          end
                       `CMD_ADC:
                          begin
                          adc_calibrate<=1'b0;
                          adc_trigger <= 1'b1;
                          bpsm_state<=`STATE_ADC_WAIT;
                          end
                       `CMD_ADC_CALIBRATE:
                         begin
                         adc_calibrate<=1'b1;
                         adc_trigger <= 1'b1;
                         bpsm_state<=`STATE_ADC_WAIT;
                         end
                       `CMD_LASTART:
                           la_start<=1'b1;
                       `CMD_LASTOP:
                           la_start<=1'b0;
                       `CMD_DIO_WRITE:
                           bpio_dio_port_d<= in_fifo_out_data[BP_PINS-1:0];

                       `CMD_DELAY:
                           begin
                           bpsm_state <= `STATE_DELAY;
                           delay_counter<=in_fifo_out_data[7:0];
                           end
                      `CMD_HALT:
                          bpsm_state <= `STATE_HALT;
                       default: begin




                       end
                   endcase
               end else begin
                   bp_busy <= 0;
              end
           end

           `STATE_DELAY: begin
                out_fifo_in_shift<=1'b0;
                if (delay_counter == 0) begin
                    bpsm_state <= `STATE_POP_FIFO;
                end else begin
                    delay_counter <= delay_counter - 1;
                end
            end

            `STATE_PERIPHERAL_WAIT: begin
                out_fifo_in_shift<=1'b0;
                peripheral_trigger <= 1'b0;
                if (!peripheral_trigger && !peripheral_busy && !out_fifo_in_full) begin
                    bpsm_state <= `STATE_POP_FIFO;
                    out_fifo_in_data_d<={8'hFF,peripheral_data_out};

                    out_fifo_in_shift<=1'b1;
                end
            end

            `STATE_ADC_WAIT: begin
                out_fifo_in_shift<=1'b0;
                adc_trigger <= 1'b0;
                if (!adc_trigger && !adc_busy && !out_fifo_in_full) begin
                    bpsm_state <= `STATE_POP_FIFO;
                    out_fifo_in_data_d<={4'h0,adc_data_out};
                    out_fifo_in_shift<=1'b1;
                end
            end










            `STATE_POP_FIFO: begin
                out_fifo_in_shift<=1'b0;
                in_fifo_out_pop<=1'b1;
                bpsm_state <= `STATE_CLEANUP;
             end

             `STATE_CLEANUP: begin
                 in_fifo_out_pop<=1'b0;
                 bpsm_state <= `STATE_IDLE;
              end

            `STATE_HALT: begin
              `reg_bpsm_reset<=1'b1;
                out_fifo_in_shift<=1'b0;
                in_fifo_out_pop<=1'b1;

             end

          endcase
        end




        if(sram_auto_clock_delay)
        begin
          sram_auto_clock_delay<=1'b0;
          sram_auto_clock<=1'b1;
        end
        else if(sram_auto_clock)
        begin
          sram_auto_clock<=1'b0;
        end



        if(`reg_la_clear_sample_counter)
        begin
          `reg_la_sample_count<=16'h0000;
          `reg_la_clear_sample_counter<=1'b0;
          `reg_la_max_samples_reached<=1'b0;
        end
        else if(la_start)
        begin
          if(`reg_la_sample_count<16'hF424)
          begin
            `reg_la_sample_count<=`reg_la_sample_count+1;
            `reg_la_active<=1'b1;
          end
          else
            begin
              `reg_la_active<=1'b0;
              `reg_la_max_samples_reached<=1'b1;
            end
        end
        else
        begin
          `reg_la_active<=1'b0;
        end


        in_fifo_in_shift<=1'b0;
        out_fifo_out_pop<=1'b0;
        if(!mc_ce)
        begin

          if (mc_we_sync)

          begin
            wreg[mc_add] <= mc_din;
            case(mc_add)
              6'h02:sram_auto_clock_delay<=1'b1;
              6'h06:pwm_reset<=1'b1;
              6'h07:in_fifo_in_shift<=1'b1;
              default: begin end
            endcase
          end

          else if (mc_oe_sync)

          begin

            case(mc_add)
              6'h02:begin
                sram_auto_clock_delay<=1'b1;
                mc_dout_d <= {8'h00,sram_sio_tdi};
              end
              6'h03: mc_dout_d<=`reg_la_config;
              6'h07: begin
                mc_dout_d<=out_fifo_out_data;
                out_fifo_out_pop<=1'b1;
              end
              default:mc_dout_d <= rreg[mc_add];
            endcase
          end

        end
      end




    SB_IO #(
      .PIN_TYPE(6'b1010_01),
      .PULLUP(1'b0)
    ) sram_mosi_sbio[LA_CHIPS-1:0] (
      .PACKAGE_PIN({sram_sio[4],sram_sio[0]}),
      .OUTPUT_ENABLE(`reg_la_io_quad?`reg_la_io_quad_direction:1'b1),
      .D_OUT_0({sram_sio_tdo[4],sram_sio_tdo[0]}),
      .D_IN_0({sram_sio_tdi[4],sram_sio_tdi[0]})
    );

    SB_IO #(
			.PIN_TYPE(6'b1010_01),
			.PULLUP(1'b0)
		) sram_miso_sbio[LA_CHIPS-1:0](
			.PACKAGE_PIN({sram_sio[5],sram_sio[1]}),
			.OUTPUT_ENABLE(`reg_la_io_quad?`reg_la_io_quad_direction:1'b0),
			.D_OUT_0({sram_sio_tdo[5],sram_sio_tdo[1]}),
			.D_IN_0({sram_sio_tdi[5],sram_sio_tdi[1]})
		);

    SB_IO #(
			.PIN_TYPE(6'b1010_01),
			.PULLUP(1'b0)
		) sram_sio_sbio[3:0] (
			.PACKAGE_PIN({sram_sio[7:6],sram_sio[3:2]}),
			.OUTPUT_ENABLE(`reg_la_io_quad&&`reg_la_io_quad_direction),
			.D_OUT_0({sram_sio_tdo[7:6],sram_sio_tdo[3:2]}),
			.D_IN_0({sram_sio_tdi[7:6],sram_sio_tdi[3:2]})
		);

    SB_IO #(
      .PIN_TYPE(6'b1010_01),
      .PULLUP(1'b0)
    ) mc_io [MC_DATA_WIDTH-1:0] (
      .PACKAGE_PIN(mc_data),
      .OUTPUT_ENABLE(!mc_oe),
      .D_OUT_0(mc_dout),
      .D_IN_0(mc_din)
    );

    SB_IO #(
      .PIN_TYPE(6'b1010_01),
      .PULLUP(1'b0)
    ) bpio_tio [BP_PINS-1:0] (
      .PACKAGE_PIN(bpio_buffer_io),
      .OUTPUT_ENABLE(bpio_toe),
      .D_OUT_0(bpio_tdo),
      .D_IN_0(bpio_tdi)
    );

`ifdef SIMULATION
    initial begin

      reset<=1'b0;
      count<=3'b000;
      reset_count<=3'b000;
      bp_busy <= 1'b0;
      la_start<=1'b0;
      rreg[6'b00000] <= 16'b0000000000000000;
      rreg[6'b00001] <= 16'b0000000000000000;
      rreg[6'b00010] <= 16'b0000000000000000;
      rreg[6'b00011] <= 16'b0000000000000000;
      rreg[6'b00100] <= 16'b0000000000000000;
      rreg[6'b00101] <= 16'b0000000000000000;
      rreg[6'b00110] <= 16'b0000000000000000;
      rreg[6'b00111] <= 16'b0000000000000000;
      rreg[6'b01000] <= 16'b0000000000000000;
      rreg[6'b01001] <= 16'b0000000000000000;
      rreg[6'b01010] <= 16'b0000000000000000;
      rreg[6'b01011] <= 16'b0000000000000000;
      rreg[6'b01100] <= 16'b0000000000000000;
      rreg[6'b01101] <= 16'b0000000000000000;
      rreg[6'b01110] <= 16'b0000000000000000;
      rreg[6'b01111] <= 16'b0000000000000000;
      rreg[6'b10000] <= 16'b0000000000000000;
      rreg[6'b10001] <= 16'b0000000000000000;
      rreg[6'b10010] <= 16'b0000000000000000;
      rreg[6'b10011] <= 16'b0000000000000000;
      rreg[6'b10100] <= 16'b0000000000000000;
      rreg[6'b10101] <= 16'b0000000000000000;
      rreg[6'b10110] <= 16'b0000000000000000;
      rreg[6'b10111] <= 16'b0000000000000000;
      rreg[6'b11000] <= 16'b0000000000000000;
      rreg[6'b11001] <= 16'b0000000000000000;
      rreg[6'b11010] <= 16'b0000000000000000;
      rreg[6'b11011] <= 16'b0000000000000000;
      rreg[6'b11100] <= 16'b0000000000000000;
      rreg[6'b11101] <= 16'b0000000000000000;
      rreg[6'b11110] <= 16'b0000000000000000;
      rreg[6'b11111] <= 16'b0000000000000000;

      wreg[6'b00000] <= 16'b0000000000000000;
      wreg[6'b00001] <= 16'b0000000000000000;
      wreg[6'b00010] <= 16'b0000000000000000;
      wreg[6'b00011] <= 16'b0000000000000000;
      wreg[6'b00100] <= 16'b0000000000000000;
      wreg[6'b00101] <= 16'b0000000000000000;
      wreg[6'b00110] <= 16'b0000000000000000;
      wreg[6'b00111] <= 16'b0000000000000000;
      wreg[6'b01000] <= 16'b0000000000000000;
      wreg[6'b01001] <= 16'b0000000000000000;
      wreg[6'b01010] <= 16'b0000000000000000;
      wreg[6'b01011] <= 16'b0000000000000000;
      wreg[6'b01100] <= 16'b0000000000000000;
      wreg[6'b01101] <= 16'b0000000000000000;
      wreg[6'b01110] <= 16'b0000000000000000;
      wreg[6'b01111] <= 16'b0000000000000000;
      wreg[6'b10000] <= 16'b0000000000000000;
      wreg[6'b10001] <= 16'b0000000000000000;
      wreg[6'b10010] <= 16'b0000000000000000;
      wreg[6'b10011] <= 16'b0000000000000000;
      wreg[6'b10100] <= 16'b0000000000000000;
      wreg[6'b10101] <= 16'b0000000000000000;
      wreg[6'b10110] <= 16'b0000000000000000;
      wreg[6'b10111] <= 16'b0000000000000000;
      wreg[6'b11000] <= 16'b0000000000000000;
      wreg[6'b11001] <= 16'b0000000000000000;
      wreg[6'b11010] <= 16'b0000000000000000;
      wreg[6'b11011] <= 16'b0000000000000000;
      wreg[6'b11100] <= 16'b0000000000000000;
      wreg[6'b11101] <= 16'b0000000000000000;
      wreg[6'b11110] <= 16'b0000000000000000;
      wreg[6'b11111] <= 16'b0000000000000000;


    end
  `endif

endmodule
module top #(
  parameter MC_DATA_WIDTH = 16,
  parameter MC_ADD_WIDTH = 6,
  parameter LA_WIDTH = 8,
  parameter LA_CHIPS = 2,
  parameter BP_PINS = 8,
  parameter FIFO_WIDTH = 16,
  parameter FIFO_DEPTH = 512
) (
  input clock,

  inout wire [BP_PINS-1:0] bpio_buffer_io,
  output wire [BP_PINS-1:0] bpio_buffer_dir, bpio_buffer_od,
  output wire[LA_CHIPS-1:0] sram_clock,
  output wire[LA_CHIPS-1:0] sram_cs,
  inout[LA_WIDTH-1:0] sram_sio,
  output wire lat_oe, lat_dir,
  input wire [LA_WIDTH-1:0] lat,
  input wire mcu_clock,
  input wire mcu_cs,
  input wire mcu_mosi,
  output wire mcu_miso,
  input wire mc_oe, mc_ce, mc_we,
  input wire [MC_ADD_WIDTH-1:0] mc_add,
  inout [MC_DATA_WIDTH-1:0] mc_data,
  output bp_active,
  output bp_fifo_in_full,
  output bp_fifo_out_nempty,
  input bp_fifo_clear,
  output adc_mux_en,
  output [3:0] adc_mux_s,
  output adc_cs, adc_clock,
  input adc_data,
  output pullup_enable
  );



    wire mc_we_sync,mc_oe_sync,mc_ce_sync;
    sync MC_WE_SYNC(clock, mc_we, mc_we_sync);
    sync MC_OE_SYNC(clock, mc_oe, mc_oe_sync);
    sync MC_CE_SYNC(clock, mc_ce, mc_ce_sync);

    reg [MC_DATA_WIDTH-1:0] wreg [32:0];
    reg [MC_DATA_WIDTH-1:0] rreg [32:0];


    wire [BP_PINS-1:0] bpio_toe, bpio_tdo, bpio_tdi;

    wire [BP_PINS-1:0] bpio_oe,bpio_di,bpio_do,bpio_dir;

    reg [BP_PINS-1:0] bpio_dio_tris_d, bpio_dio_port_d;

    reg bp_busy;
    assign bp_active=in_fifo_out_nempty || peripheral_busy || bp_busy;


    iobuf BPIO_BUF[BP_PINS-1:0] (

      .oe(`reg_bpio_oe),
      .od(`reg_bpio_od),
      .dir(`reg_bpio_dir),
      .din(bpio_do),
      .dout(bpio_di),

      .bufdir(bpio_buffer_dir),
      .bufod(bpio_buffer_od),
      .bufdat_tristate_oe(bpio_toe),
      .bufdat_tristate_dout(bpio_tdo),
      .bufdat_tristate_din(bpio_tdi)
      );
      `define BP_PERIPHERAL_PINS 3
      assign bpio_do[BP_PINS-1:`BP_PERIPHERAL_PINS]=bpio_dio_port_d[BP_PINS-1:`BP_PERIPHERAL_PINS];




    wire pwm_out;
    reg pwm_reset;
    pwm PWM_OUT(pwm_reset, count[0],pwm_out, `reg_pwm_on,`reg_pwm_off);



  	wire [MC_DATA_WIDTH-1:0] mc_din;
    reg [MC_DATA_WIDTH-1:0] mc_dout_d;
    wire [MC_DATA_WIDTH-1:0] mc_dout;
    assign mc_dout=mc_dout_d;


    assign adc_mux_en=`reg_adc_en;
    assign adc_mux_s=`reg_adc_s;


    assign lat_oe=1'b0;
    assign lat_dir=1'b0;
    assign pullup_enable=1'b0;

    localparam N = 3;
    reg [N:0] count;
    reg reset;
    reg [2:0] reset_count;

    reg [7:0] la_sample_prescaler;

    wire [LA_WIDTH-1:0] sram_sio_tdi;
    wire [LA_WIDTH-1:0] sram_sio_tdo;

    reg la_start;
    wire sram_clock_source;
    reg sram_auto_clock, sram_auto_clock_delay;
    assign sram_clock_source=(la_start&&`reg_la_active)?clock:(`reg_la_io_quad)?sram_auto_clock:(`reg_la_io_spi)?mcu_clock:1'b0;
    assign sram_clock={sram_clock_source,sram_clock_source};
    assign sram_cs=(la_start&&`reg_la_active)?2'b00:{`reg_la_io_cs1,`reg_la_io_cs0};
    assign sram_sio_tdo[0]=(la_start&&`reg_la_active)?lat[0]:`reg_la_io_quad?`reg_la_write[0]:mcu_mosi;
    assign sram_sio_tdo[4]=(la_start&&`reg_la_active)?lat[4]:`reg_la_io_quad?`reg_la_write[4]:mcu_mosi;
    assign {sram_sio_tdo[7:5],sram_sio_tdo[3:1]}=(la_start&&`reg_la_active)?{lat[7:5],lat[3:1]}:{`reg_la_write[7:5],`reg_la_write[3:1]};
    assign mcu_miso=!`reg_la_io_cs0?sram_sio_tdi[1]:sram_sio_tdi[5];


    `ifdef SIMULATION
      wire [15:0] reg_la_sample_count;
      assign reg_la_sample_count=`reg_la_sample_count;


    `endif


    wire bp_fifo_clear_sync;
    sync FIFO_CLEAR_SYNC(clock, bp_fifo_clear, bp_fifo_clear_sync);

    wire [MC_DATA_WIDTH-1:0] in_fifo_out_data;
    wire in_fifo_in_nempty,in_fifo_out_nempty;
    reg in_fifo_in_shift,in_fifo_out_pop;

    reg [MC_DATA_WIDTH-1:0] out_fifo_in_data_d;
    wire [MC_DATA_WIDTH-1:0] out_fifo_out_data;
    wire out_fifo_in_nempty, out_fifo_in_full;
    reg out_fifo_in_shift,out_fifo_out_pop;

    reg peripheral_trigger;
    wire peripheral_busy;
    wire[7:0] peripheral_data_out;
    reg [15:0] peripheral_data_in_d;

    fifo #(
      .WIDTH(FIFO_WIDTH),
      .DEPTH(FIFO_DEPTH)
    ) FIFO_IN (
      .reset(bp_fifo_clear_sync),
      .in_clock(clock),
      .in_shift(in_fifo_in_shift),
      .in_data(mc_din),
      .in_full(bp_fifo_in_full),
      .in_nempty(in_fifo_in_nempty),
      .out_clock(clock),
      .out_pop(in_fifo_out_pop),
      .out_data(in_fifo_out_data),
      .out_nempty(in_fifo_out_nempty)
    ), FIFO_OUT (
      .reset(bp_fifo_clear_sync),
      .in_clock(clock),
    	.in_shift(out_fifo_in_shift),
    	.in_data(out_fifo_in_data_d),
    	.in_full(out_fifo_in_full),
    	.in_nempty(out_fifo_in_nempty),
      .out_clock(clock),
    	.out_pop(out_fifo_out_pop),
    	.out_data(out_fifo_out_data),
    	.out_nempty(bp_fifo_out_nempty)
    );

    wire adc_busy;
    reg adc_trigger;
    wire [13:0] adc_data_out;
    reg adc_calibrate;

    adc ADC_SI (

      	.rst(reset),
      	.clkin(clock),

      	.go(adc_trigger),
      	.state(adc_busy),
        .calibrate(adc_calibrate),

      	.data_o(adc_data_out),

      	.sclk(adc_clock),
      	.miso(adc_data),
      	.cs(adc_cs)
      );


     spimaster SPI_MASTER(

       .rst(reset),
       .clkin(clock),

       .cpol(1'b1),
       .cpha(1'b0),
       .cspol(1'b1),


       .go(peripheral_trigger),
       .state(peripheral_busy),

       .data_i(peripheral_data_in_d),
       .data_o(peripheral_data_out),

       .mosi(bpio_do[0]),
       .sclk(bpio_do[1]),
       .miso(bpio_di[2])

       );

    reg [7:0] delay_counter;

    `define STATE_IDLE   0
    `define STATE_WAIT    1
    `define STATE_LASTART   2
    `define STATE_LASTOP 3
    `define STATE_DIO_WRITE 4
    `define STATE_DIO_READ 5
    `define STATE_DELAY 6
    `define STATE_PERIPHERAL_WAIT 7
    `define STATE_POP_FIFO 8
    `define STATE_CLEANUP 9
    `define STATE_HALT 10
    `define STATE_ADC_WAIT 11


    `define CMD_PERIPHERAL_WRITE 8'b0???????
    `define CMD_LASTART 8'b11111110
    `define CMD_LASTOP 8'b11111111
    `define CMD_HALT 8'b11111101
    `define CMD_DIO_WRITE 8'b10000001
    `define CMD_DIO_READ 8'b10000010
    `define CMD_DIO_TRIS 8'b10000011
    `define CMD_DELAY 8'b10000100
    `define CMD_ADC 8'b10000101
    `define CMD_ADC_CALIBRATE 8'b10000110

    reg [$clog2(`STATE_HALT):0] bpsm_state;

    always @(posedge clock)
      begin

      rreg[9][$clog2(`STATE_HALT):0]<=bpsm_state;



      if(reset_count<3) begin
        reset_count<=reset_count+1;
        reset<=1'b1;
        rreg[9]<=16'h00;
      end
      else
      begin
        reset<=1'b0;
      end

      count <= count + 1;
      pwm_reset<=1'b0;

      if(`reg_bpsm_reset||reset) begin
           bpsm_state <= `STATE_IDLE;
           peripheral_trigger <= 1'b0;
           out_fifo_in_shift<=1'b0;
           in_fifo_out_pop<=1'b0;
       end
       else
       begin

         case(bpsm_state)
             `STATE_IDLE: begin
                 if(in_fifo_out_nempty&&!out_fifo_in_full) begin
                     bp_busy <= 1'b1;

                     rreg[10]<=in_fifo_out_data;


                     out_fifo_in_data_d<=in_fifo_out_data;
                     out_fifo_in_shift<=1'b1;
                     bpsm_state<=`STATE_POP_FIFO;

                     casez(in_fifo_out_data[15:8])
                       `CMD_PERIPHERAL_WRITE:
                          begin
                          peripheral_data_in_d <= in_fifo_out_data;
                          peripheral_trigger <= 1'b1;
                          bpsm_state<=`STATE_PERIPHERAL_WAIT;
                          end
                       `CMD_ADC:
                          begin
                          adc_calibrate<=1'b0;
                          adc_trigger <= 1'b1;
                          bpsm_state<=`STATE_ADC_WAIT;
                          end
                       `CMD_ADC_CALIBRATE:
                         begin
                         adc_calibrate<=1'b1;
                         adc_trigger <= 1'b1;
                         bpsm_state<=`STATE_ADC_WAIT;
                         end
                       `CMD_LASTART:
                           la_start<=1'b1;
                       `CMD_LASTOP:
                           la_start<=1'b0;
                       `CMD_DIO_WRITE:
                           bpio_dio_port_d<= in_fifo_out_data[BP_PINS-1:0];

                       `CMD_DELAY:
                           begin
                           bpsm_state <= `STATE_DELAY;
                           delay_counter<=in_fifo_out_data[7:0];
                           end
                      `CMD_HALT:
                          bpsm_state <= `STATE_HALT;
                       default: begin




                       end
                   endcase
               end else begin
                   bp_busy <= 0;
              end
           end

           `STATE_DELAY: begin
                out_fifo_in_shift<=1'b0;
                if (delay_counter == 0) begin
                    bpsm_state <= `STATE_POP_FIFO;
                end else begin
                    delay_counter <= delay_counter - 1;
                end
            end

            `STATE_PERIPHERAL_WAIT: begin
                out_fifo_in_shift<=1'b0;
                peripheral_trigger <= 1'b0;
                if (!peripheral_trigger && !peripheral_busy && !out_fifo_in_full) begin
                    bpsm_state <= `STATE_POP_FIFO;
                    out_fifo_in_data_d<={8'hFF,peripheral_data_out};

                    out_fifo_in_shift<=1'b1;
                end
            end

            `STATE_ADC_WAIT: begin
                out_fifo_in_shift<=1'b0;
                adc_trigger <= 1'b0;
                if (!adc_trigger && !adc_busy && !out_fifo_in_full) begin
                    bpsm_state <= `STATE_POP_FIFO;
                    out_fifo_in_data_d<={4'h0,adc_data_out};
                    out_fifo_in_shift<=1'b1;
                end
            end










            `STATE_POP_FIFO: begin
                out_fifo_in_shift<=1'b0;
                in_fifo_out_pop<=1'b1;
                bpsm_state <= `STATE_CLEANUP;
             end

             `STATE_CLEANUP: begin
                 in_fifo_out_pop<=1'b0;
                 bpsm_state <= `STATE_IDLE;
              end

            `STATE_HALT: begin
              `reg_bpsm_reset<=1'b1;
                out_fifo_in_shift<=1'b0;
                in_fifo_out_pop<=1'b1;

             end

          endcase
        end




        if(sram_auto_clock_delay)
        begin
          sram_auto_clock_delay<=1'b0;
          sram_auto_clock<=1'b1;
        end
        else if(sram_auto_clock)
        begin
          sram_auto_clock<=1'b0;
        end



        if(`reg_la_clear_sample_counter)
        begin
          `reg_la_sample_count<=16'h0000;
          `reg_la_clear_sample_counter<=1'b0;
          `reg_la_max_samples_reached<=1'b0;
        end
        else if(la_start)
        begin
          if(`reg_la_sample_count<16'hF424)
          begin
            `reg_la_sample_count<=`reg_la_sample_count+1;
            `reg_la_active<=1'b1;
          end
          else
            begin
              `reg_la_active<=1'b0;
              `reg_la_max_samples_reached<=1'b1;
            end
        end
        else
        begin
          `reg_la_active<=1'b0;
        end


        in_fifo_in_shift<=1'b0;
        out_fifo_out_pop<=1'b0;
        if(!mc_ce)
        begin

          if (mc_we_sync)

          begin
            wreg[mc_add] <= mc_din;
            case(mc_add)
              6'h02:sram_auto_clock_delay<=1'b1;
              6'h06:pwm_reset<=1'b1;
              6'h07:in_fifo_in_shift<=1'b1;
              default: begin end
            endcase
          end

          else if (mc_oe_sync)

          begin

            case(mc_add)
              6'h02:begin
                sram_auto_clock_delay<=1'b1;
                mc_dout_d <= {8'h00,sram_sio_tdi};
              end
              6'h03: mc_dout_d<=`reg_la_config;
              6'h07: begin
                mc_dout_d<=out_fifo_out_data;
                out_fifo_out_pop<=1'b1;
              end
              default:mc_dout_d <= rreg[mc_add];
            endcase
          end

        end
      end




    SB_IO #(
      .PIN_TYPE(6'b1010_01),
      .PULLUP(1'b0)
    ) sram_mosi_sbio[LA_CHIPS-1:0] (
      .PACKAGE_PIN({sram_sio[4],sram_sio[0]}),
      .OUTPUT_ENABLE(`reg_la_io_quad?`reg_la_io_quad_direction:1'b1),
      .D_OUT_0({sram_sio_tdo[4],sram_sio_tdo[0]}),
      .D_IN_0({sram_sio_tdi[4],sram_sio_tdi[0]})
    );

    SB_IO #(
			.PIN_TYPE(6'b1010_01),
			.PULLUP(1'b0)
		) sram_miso_sbio[LA_CHIPS-1:0](
			.PACKAGE_PIN({sram_sio[5],sram_sio[1]}),
			.OUTPUT_ENABLE(`reg_la_io_quad?`reg_la_io_quad_direction:1'b0),
			.D_OUT_0({sram_sio_tdo[5],sram_sio_tdo[1]}),
			.D_IN_0({sram_sio_tdi[5],sram_sio_tdi[1]})
		);

    SB_IO #(
			.PIN_TYPE(6'b1010_01),
			.PULLUP(1'b0)
		) sram_sio_sbio[3:0] (
			.PACKAGE_PIN({sram_sio[7:6],sram_sio[3:2]}),
			.OUTPUT_ENABLE(`reg_la_io_quad&&`reg_la_io_quad_direction),
			.D_OUT_0({sram_sio_tdo[7:6],sram_sio_tdo[3:2]}),
			.D_IN_0({sram_sio_tdi[7:6],sram_sio_tdi[3:2]})
		);

    SB_IO #(
      .PIN_TYPE(6'b1010_01),
      .PULLUP(1'b0)
    ) mc_io [MC_DATA_WIDTH-1:0] (
      .PACKAGE_PIN(mc_data),
      .OUTPUT_ENABLE(!mc_oe),
      .D_OUT_0(mc_dout),
      .D_IN_0(mc_din)
    );

    SB_IO #(
      .PIN_TYPE(6'b1010_01),
      .PULLUP(1'b0)
    ) bpio_tio [BP_PINS-1:0] (
      .PACKAGE_PIN(bpio_buffer_io),
      .OUTPUT_ENABLE(bpio_toe),
      .D_OUT_0(bpio_tdo),
      .D_IN_0(bpio_tdi)
    );

`ifdef SIMULATION
    initial begin

      reset<=1'b0;
      count<=3'b000;
      reset_count<=3'b000;
      bp_busy <= 1'b0;
      la_start<=1'b0;
      rreg[6'b00000] <= 16'b0000000000000000;
      rreg[6'b00001] <= 16'b0000000000000000;
      rreg[6'b00010] <= 16'b0000000000000000;
      rreg[6'b00011] <= 16'b0000000000000000;
      rreg[6'b00100] <= 16'b0000000000000000;
      rreg[6'b00101] <= 16'b0000000000000000;
      rreg[6'b00110] <= 16'b0000000000000000;
      rreg[6'b00111] <= 16'b0000000000000000;
      rreg[6'b01000] <= 16'b0000000000000000;
      rreg[6'b01001] <= 16'b0000000000000000;
      rreg[6'b01010] <= 16'b0000000000000000;
      rreg[6'b01011] <= 16'b0000000000000000;
      rreg[6'b01100] <= 16'b0000000000000000;
      rreg[6'b01101] <= 16'b0000000000000000;
      rreg[6'b01110] <= 16'b0000000000000000;
      rreg[6'b01111] <= 16'b0000000000000000;
      rreg[6'b10000] <= 16'b0000000000000000;
      rreg[6'b10001] <= 16'b0000000000000000;
      rreg[6'b10010] <= 16'b0000000000000000;
      rreg[6'b10011] <= 16'b0000000000000000;
      rreg[6'b10100] <= 16'b0000000000000000;
      rreg[6'b10101] <= 16'b0000000000000000;
      rreg[6'b10110] <= 16'b0000000000000000;
      rreg[6'b10111] <= 16'b0000000000000000;
      rreg[6'b11000] <= 16'b0000000000000000;
      rreg[6'b11001] <= 16'b0000000000000000;
      rreg[6'b11010] <= 16'b0000000000000000;
      rreg[6'b11011] <= 16'b0000000000000000;
      rreg[6'b11100] <= 16'b0000000000000000;
      rreg[6'b11101] <= 16'b0000000000000000;
      rreg[6'b11110] <= 16'b0000000000000000;
      rreg[6'b11111] <= 16'b0000000000000000;

      wreg[6'b00000] <= 16'b0000000000000000;
      wreg[6'b00001] <= 16'b0000000000000000;
      wreg[6'b00010] <= 16'b0000000000000000;
      wreg[6'b00011] <= 16'b0000000000000000;
      wreg[6'b00100] <= 16'b0000000000000000;
      wreg[6'b00101] <= 16'b0000000000000000;
      wreg[6'b00110] <= 16'b0000000000000000;
      wreg[6'b00111] <= 16'b0000000000000000;
      wreg[6'b01000] <= 16'b0000000000000000;
      wreg[6'b01001] <= 16'b0000000000000000;
      wreg[6'b01010] <= 16'b0000000000000000;
      wreg[6'b01011] <= 16'b0000000000000000;
      wreg[6'b01100] <= 16'b0000000000000000;
      wreg[6'b01101] <= 16'b0000000000000000;
      wreg[6'b01110] <= 16'b0000000000000000;
      wreg[6'b01111] <= 16'b0000000000000000;
      wreg[6'b10000] <= 16'b0000000000000000;
      wreg[6'b10001] <= 16'b0000000000000000;
      wreg[6'b10010] <= 16'b0000000000000000;
      wreg[6'b10011] <= 16'b0000000000000000;
      wreg[6'b10100] <= 16'b0000000000000000;
      wreg[6'b10101] <= 16'b0000000000000000;
      wreg[6'b10110] <= 16'b0000000000000000;
      wreg[6'b10111] <= 16'b0000000000000000;
      wreg[6'b11000] <= 16'b0000000000000000;
      wreg[6'b11001] <= 16'b0000000000000000;
      wreg[6'b11010] <= 16'b0000000000000000;
      wreg[6'b11011] <= 16'b0000000000000000;
      wreg[6'b11100] <= 16'b0000000000000000;
      wreg[6'b11101] <= 16'b0000000000000000;
      wreg[6'b11110] <= 16'b0000000000000000;
      wreg[6'b11111] <= 16'b0000000000000000;


    end
  `endif

endmodule