data/full_repos/permissive/188434311/verilog/register_slice/testbench/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/188434311/verilog/register_slice/testbench/tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 clk = ~ clk ;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/188434311/verilog/register_slice/testbench/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  forever #20 clk_div2 = ~clk_div2 ;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/188434311/verilog/register_slice/testbench/tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #105;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/188434311/verilog/register_slice/testbench/tb.v:36: Operator ADD expects 8 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance dut\n         txdata <= txdata + 1\'b0 ;\n                          ^\n%Error: data/full_repos/permissive/188434311/verilog/register_slice/testbench/tb.v:42: Cannot find file containing module: \'forward_register_slice\'\nforward_register_slice fwd_reg_inst0(\n^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188434311/verilog/register_slice/testbench,data/full_repos/permissive/188434311/forward_register_slice\n             data/full_repos/permissive/188434311/verilog/register_slice/testbench,data/full_repos/permissive/188434311/forward_register_slice.v\n             data/full_repos/permissive/188434311/verilog/register_slice/testbench,data/full_repos/permissive/188434311/forward_register_slice.sv\n             forward_register_slice\n             forward_register_slice.v\n             forward_register_slice.sv\n             obj_dir/forward_register_slice\n             obj_dir/forward_register_slice.v\n             obj_dir/forward_register_slice.sv\n%Error: data/full_repos/permissive/188434311/verilog/register_slice/testbench/tb.v:55: Cannot find file containing module: \'backward_register_slice\'\nbackward_register_slice bwd_reg_inst0(\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dut();

reg  clk;
reg  clk_div2;
reg  rstn;

initial begin
  clk = 1'b0 ;
  forever #10 clk = ~ clk ;
end

initial begin
  clk_div2 = 1'b0 ;
  forever #20 clk_div2 = ~clk_div2 ;
end

initial begin
  rstn = 1'b0;
  #105;
  rstn = 1'b1;
end

reg txvld;
reg txrdy;
reg rxvld;
reg rxrdy;
reg [7:0] txdata;
reg [7:0] rxdata;

always @(posedge clk or negedge rstn)
  if(~rstn) begin
    txvld <= 1'b0;
    txdata <= 8'b0;
  end
  else if(txrdy) begin
         txdata <= txdata + 1'b0 ;
         txvld <= clk_div2;
       end
        
    

forward_register_slice fwd_reg_inst0(
    .clki(clk),
    .rst_n(rstn),
    .RxVld(txvld),
    .RxData(txdata),
    .RxRdy(),
    .TxVld(),
    .TxRdy(txvld),
    .TxData()
);



backward_register_slice bwd_reg_inst0(
    .clki(clk),
    .rst_n(rstn),
    .RxVld(clk),
    .RxData(8'hf),
    .RxRdy(),
    .TxVld(),
    .TxRdy(clk_div2),
    .TxData()
);


endmodule
module dut();


reg  clk;
reg  clk_div2;
reg  rstn;

initial begin
  clk = 1'b0 ;
  forever #10 clk = ~ clk ;
end

initial begin
  clk_div2 = 1'b0 ;
  forever #20 clk_div2 = ~clk_div2 ;
end

initial begin
  rstn = 1'b0;
  #105;
  rstn = 1'b1;
end

reg txvld;
reg txrdy;
reg rxvld;
reg rxrdy;
reg [7:0] txdata;
reg [7:0] rxdata;

always @(posedge clk or negedge rstn)
  if(~rstn) begin
    txvld <= 1'b0;
    txdata <= 8'b0;
  end
  else if(txrdy) begin
         txdata <= txdata + 1'b0 ;
         txvld <= clk_div2;
       end
        
    

forward_register_slice fwd_reg_inst0(
    .clki(clk),
    .rst_n(rstn),
    .RxVld(txvld),
    .RxData(txdata),
    .RxRdy(),
    .TxVld(),
    .TxRdy(txvld),
    .TxData()
);



backward_register_slice bwd_reg_inst0(
    .clki(clk),
    .rst_n(rstn),
    .RxVld(clk),
    .RxData(8'hf),
    .RxRdy(),
    .TxVld(),
    .TxRdy(clk_div2),
    .TxData()
);


endmodule