data/full_repos/permissive/100975158/ProcessadorQuartus/Controle.v
data/verilator_xmls/316a03c4-fc23-4e70-8d71-5c71a69752da.xml
module Controle(input wire [5:0] opcode,
                input wire [5:0] funct,
                output reg [1:0] c_ALUOp,
                output reg c_fonte_ula,
                output reg [2:0] c_desvio,
                output reg [1:0] c_memoria,
                output reg c_memtoreg,
                output reg c_escrever_reg,
                output reg c_reg_destino,
                output reg c_jal
);


    always @ ( * ) begin
        c_jal <= 1'b0;
        case (opcode)
            6'b000000: begin
                c_ALUOp <= 2'b10;
                c_fonte_ula <= 1'b0;
                c_desvio <= 3'b000;
                c_memoria <= 2'b00;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b1;
                c_reg_destino <= 1'b1;

                if (funct == 6'b001000) begin
                  c_ALUOp <= 2'b01;
                  c_desvio <= 3'b101;
                  c_escrever_reg <= 1'b0;
                end
            end

            6'b011100: begin
              c_ALUOp <= 2'b10;
              c_fonte_ula <= 1'b0;
              c_desvio <= 3'b000;
              c_memoria <= 2'b00;
              c_memtoreg <= 1'b0;
              c_escrever_reg <= 1'b1;
              c_reg_destino <= 1'b1;
            end

            6'b101011: begin
                c_ALUOp <= 2'b00;
                c_fonte_ula <= 1'b1;
                c_desvio <= 3'b000;
                c_memoria <= 2'b10;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b0;
                c_reg_destino <= 1'b0;
            end

            6'b100011: begin
                c_ALUOp <= 2'b00;
                c_fonte_ula <= 1'b1;
                c_desvio <= 3'b000;
                c_memoria <= 2'b01;
                c_memtoreg <= 1'b1;
                c_escrever_reg <= 1'b1;
                c_reg_destino <= 1'b0;
            end

            6'b001000: begin
                c_ALUOp <= 2'b00;
                c_fonte_ula <= 1'b1;
                c_desvio <= 3'b000;
                c_memoria <= 2'b00;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b1;
                c_reg_destino <= 1'b0;
            end

            6'b000100: begin
                c_ALUOp <= 2'b01;
                c_fonte_ula <= 1'b0;
                c_desvio <= 3'b001;
                c_memoria <= 2'b00;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b0;
                c_reg_destino <= 1'b0;
            end

            6'b000101: begin
                c_ALUOp <= 2'b01;
                c_fonte_ula <= 1'b0;
                c_desvio <= 3'b010;
                c_memoria <= 2'b00;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b0;
                c_reg_destino <= 1'b0;
            end

            6'b000010: begin
                c_ALUOp <= 2'b01;
                c_fonte_ula <= 1'b0;
                c_desvio <= 3'b011;
                c_memoria <= 2'b00;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b0;
                c_reg_destino <= 1'b0;
            end

            6'b000011: begin
                c_ALUOp <= 2'b01;
                c_fonte_ula <= 1'b0;
                c_desvio <= 3'b100;
                c_memoria <= 2'b00;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b1;
                c_reg_destino <= 1'b0;
                c_jal <= 1'b1;
            end

        endcase
    end

endmodule
module Controle(input wire [5:0] opcode,
                input wire [5:0] funct,
                output reg [1:0] c_ALUOp,
                output reg c_fonte_ula,
                output reg [2:0] c_desvio,
                output reg [1:0] c_memoria,
                output reg c_memtoreg,
                output reg c_escrever_reg,
                output reg c_reg_destino,
                output reg c_jal
);



    always @ ( * ) begin
        c_jal <= 1'b0;
        case (opcode)
            6'b000000: begin
                c_ALUOp <= 2'b10;
                c_fonte_ula <= 1'b0;
                c_desvio <= 3'b000;
                c_memoria <= 2'b00;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b1;
                c_reg_destino <= 1'b1;

                if (funct == 6'b001000) begin
                  c_ALUOp <= 2'b01;
                  c_desvio <= 3'b101;
                  c_escrever_reg <= 1'b0;
                end
            end

            6'b011100: begin
              c_ALUOp <= 2'b10;
              c_fonte_ula <= 1'b0;
              c_desvio <= 3'b000;
              c_memoria <= 2'b00;
              c_memtoreg <= 1'b0;
              c_escrever_reg <= 1'b1;
              c_reg_destino <= 1'b1;
            end

            6'b101011: begin
                c_ALUOp <= 2'b00;
                c_fonte_ula <= 1'b1;
                c_desvio <= 3'b000;
                c_memoria <= 2'b10;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b0;
                c_reg_destino <= 1'b0;
            end

            6'b100011: begin
                c_ALUOp <= 2'b00;
                c_fonte_ula <= 1'b1;
                c_desvio <= 3'b000;
                c_memoria <= 2'b01;
                c_memtoreg <= 1'b1;
                c_escrever_reg <= 1'b1;
                c_reg_destino <= 1'b0;
            end

            6'b001000: begin
                c_ALUOp <= 2'b00;
                c_fonte_ula <= 1'b1;
                c_desvio <= 3'b000;
                c_memoria <= 2'b00;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b1;
                c_reg_destino <= 1'b0;
            end

            6'b000100: begin
                c_ALUOp <= 2'b01;
                c_fonte_ula <= 1'b0;
                c_desvio <= 3'b001;
                c_memoria <= 2'b00;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b0;
                c_reg_destino <= 1'b0;
            end

            6'b000101: begin
                c_ALUOp <= 2'b01;
                c_fonte_ula <= 1'b0;
                c_desvio <= 3'b010;
                c_memoria <= 2'b00;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b0;
                c_reg_destino <= 1'b0;
            end

            6'b000010: begin
                c_ALUOp <= 2'b01;
                c_fonte_ula <= 1'b0;
                c_desvio <= 3'b011;
                c_memoria <= 2'b00;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b0;
                c_reg_destino <= 1'b0;
            end

            6'b000011: begin
                c_ALUOp <= 2'b01;
                c_fonte_ula <= 1'b0;
                c_desvio <= 3'b100;
                c_memoria <= 2'b00;
                c_memtoreg <= 1'b0;
                c_escrever_reg <= 1'b1;
                c_reg_destino <= 1'b0;
                c_jal <= 1'b1;
            end

        endcase
    end

endmodule