data/full_repos/permissive/101171422/de2-115/vgaram/vgaram.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/101171422/de2-115/vgaram/vgaram.v:43: Unsized numbers/parameters not allowed in replications.\n                                                                                     : ... In instance vgaram\n assign sram_we_n = {key[0] ? 1 : 0};\n                            ^\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101171422/de2-115/vgaram/vgaram.v:54: Cannot find file containing module: \'reset_delay\'\n reset_delay r0(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/101171422/de2-115/vgaram,data/full_repos/permissive/101171422/reset_delay\n             data/full_repos/permissive/101171422/de2-115/vgaram,data/full_repos/permissive/101171422/reset_delay.v\n             data/full_repos/permissive/101171422/de2-115/vgaram,data/full_repos/permissive/101171422/reset_delay.sv\n             reset_delay\n             reset_delay.v\n             reset_delay.sv\n             obj_dir/reset_delay\n             obj_dir/reset_delay.v\n             obj_dir/reset_delay.sv\n%Error: data/full_repos/permissive/101171422/de2-115/vgaram/vgaram.v:64: Cannot find file containing module: \'pll\'\n pll p0(\n ^~~\n%Error: data/full_repos/permissive/101171422/de2-115/vgaram/vgaram.v:72: Cannot find file containing module: \'vga\'\n vga v0(\n ^~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module vgaram
(
	input wire        clk50,

	input wire [3:0]  key,
	input wire [17:0] sw,
	
	inout wire [15:0]  sram_dq,
	output wire [19:0] sram_addr,
	output wire        sram_ub_n,
	output wire        sram_lb_n,
	output wire        sram_we_n,
	output wire        sram_ce_n,
	output wire        sram_oe_n,

	output wire       vga_clk,
	output wire       vga_hs,
	output wire       vga_vs,
	output wire       vga_blank,
	output wire       vga_sync,
	output wire [7:0] vga_r,
	output wire [7:0] vga_g,
	output wire [7:0] vga_b
);	
	wire       rst;
	wire       vga_ctrl_clk;
	wire [7:0] r, g, b;
	wire [9:0] x, y;

	assign sram_addr = {x[9:0], y[9:0]};

	assign sram_ub_n = 0;

	assign sram_lb_n = 0;

	assign sram_ce_n = 0;

	assign sram_oe_n = 0;


	assign sram_we_n = {key[0] ? 1 : 0};
	assign sram_dq = (key[0] ? 16'hzzzz :
    					  (key[1] ? {x[8:5], y[8:5] & ~{4{x[9]}}, y[8:5] & {4{x[9]}}, 4'b0} :
         							sw[15:0]));
	

	assign r = {sram_dq[15:12], 4'b0};
	assign g = {sram_dq[11:8], 4'b0};
	assign b = {sram_dq[7:4], 4'b0};
	

	reset_delay r0(
		.clk(clk50),
		.rst(rst)
	);
	





	pll p0(
		.areset(~rst),
		.inclk0(clk50),
		.c0(vga_ctrl_clk),
		.c1(vga_clk)
	);


	vga v0(
		.clk(vga_ctrl_clk), 
		.rst(rst),
		.r(r),
		.g(g),
		.b(b),
		.x(x),
		.y(y),
		.vga_hs(vga_hs),
		.vga_vs(vga_vs),
		.vga_blank(vga_blank),
		.vga_sync(vga_sync),
		.vga_r(vga_r),
		.vga_g(vga_g),
		.vga_b(vga_b)
	);
endmodule
module vgaram
(
	input wire        clk50,

	input wire [3:0]  key,
	input wire [17:0] sw,
	
	inout wire [15:0]  sram_dq,
	output wire [19:0] sram_addr,
	output wire        sram_ub_n,
	output wire        sram_lb_n,
	output wire        sram_we_n,
	output wire        sram_ce_n,
	output wire        sram_oe_n,

	output wire       vga_clk,
	output wire       vga_hs,
	output wire       vga_vs,
	output wire       vga_blank,
	output wire       vga_sync,
	output wire [7:0] vga_r,
	output wire [7:0] vga_g,
	output wire [7:0] vga_b
);
	
	wire       rst;
	wire       vga_ctrl_clk;
	wire [7:0] r, g, b;
	wire [9:0] x, y;

	assign sram_addr = {x[9:0], y[9:0]};

	assign sram_ub_n = 0;

	assign sram_lb_n = 0;

	assign sram_ce_n = 0;

	assign sram_oe_n = 0;


	assign sram_we_n = {key[0] ? 1 : 0};
	assign sram_dq = (key[0] ? 16'hzzzz :
    					  (key[1] ? {x[8:5], y[8:5] & ~{4{x[9]}}, y[8:5] & {4{x[9]}}, 4'b0} :
         							sw[15:0]));
	

	assign r = {sram_dq[15:12], 4'b0};
	assign g = {sram_dq[11:8], 4'b0};
	assign b = {sram_dq[7:4], 4'b0};
	

	reset_delay r0(
		.clk(clk50),
		.rst(rst)
	);
	





	pll p0(
		.areset(~rst),
		.inclk0(clk50),
		.c0(vga_ctrl_clk),
		.c1(vga_clk)
	);


	vga v0(
		.clk(vga_ctrl_clk), 
		.rst(rst),
		.r(r),
		.g(g),
		.b(b),
		.x(x),
		.y(y),
		.vga_hs(vga_hs),
		.vga_vs(vga_vs),
		.vga_blank(vga_blank),
		.vga_sync(vga_sync),
		.vga_r(vga_r),
		.vga_g(vga_g),
		.vga_b(vga_b)
	);
endmodule