data/full_repos/permissive/137416864/benchmarks/techmapping/tigfet/sclib_tigfet10_hpnw4_tt_0p70v_25c.v
None: at end of input
data/verilator_xmls/66fbbc70-176b-43e7-9514-2e141670a68b.xml
module DFFQN1_HPNW4 (QN, D, CK);
	output QN;
	input D, CK;
	reg notifier;
	wire delayed_D, delayed_CK;


	specify
		(posedge CK => (QN:CK)) = 0;
		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
		$width (posedge CK, 0, 0, notifier);
		$width (negedge CK, 0, 0, notifier);
	endspecify
endmodule
module DFFQN1_HPNW4 (QN, D, CK);

	output QN;
	input D, CK;
	reg notifier;
	wire delayed_D, delayed_CK;


	specify
		(posedge CK => (QN:CK)) = 0;
		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
		$width (posedge CK, 0, 0, notifier);
		$width (negedge CK, 0, 0, notifier);
	endspecify
endmodule