data/full_repos/permissive/101862289/proba1.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/101862289/proba1.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101862289/proba1.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101862289/proba1.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101862289/proba1.v:77: Unsupported: Ignoring delay on this delayed statement.\n      always #1 clk=~clk;\n             ^\n%Error: data/full_repos/permissive/101862289/proba1.v:43: Cannot find file containing module: \'top_level\'\n top_level uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/101862289,data/full_repos/permissive/101862289/top_level\n             data/full_repos/permissive/101862289,data/full_repos/permissive/101862289/top_level.v\n             data/full_repos/permissive/101862289,data/full_repos/permissive/101862289/top_level.sv\n             top_level\n             top_level.v\n             top_level.sv\n             obj_dir/top_level\n             obj_dir/top_level.v\n             obj_dir/top_level.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module proba1;


	reg clk;
	reg rst;
	reg btn1;
	reg btn2;
	reg [7:0] sw;


	wire kimenet;
	wire[10:0] bitgen_dbg;
	wire[3:0] dbgki;
	wire startki;
	wire btn1enki;
	wire btn2enki;


	top_level uut (
		.clk(clk),
		.rst(rst),
		.btn1(btn1),
		.btn2(btn2),
		.sw(sw),
		.kimenet(kimenet),
		.bitgen_dbg(bitgen_dbg),
		.dbgki(dbgki),
		.startki(startki),
		.btn1enki(btn1enki),
		.btn2enki(btn2enki)
	);

	initial begin

		clk = 0;
		rst = 1;
		btn1 = 0;
		btn2 = 0;
		sw = 8'b01010101;


		#10;
			rst=0;
		#2;
			btn2=1;
		#500;
			btn2=0;




	end
      always #1 clk=~clk;
endmodule
module proba1;



	reg clk;
	reg rst;
	reg btn1;
	reg btn2;
	reg [7:0] sw;


	wire kimenet;
	wire[10:0] bitgen_dbg;
	wire[3:0] dbgki;
	wire startki;
	wire btn1enki;
	wire btn2enki;


	top_level uut (
		.clk(clk),
		.rst(rst),
		.btn1(btn1),
		.btn2(btn2),
		.sw(sw),
		.kimenet(kimenet),
		.bitgen_dbg(bitgen_dbg),
		.dbgki(dbgki),
		.startki(startki),
		.btn1enki(btn1enki),
		.btn2enki(btn2enki)
	);

	initial begin

		clk = 0;
		rst = 1;
		btn1 = 0;
		btn2 = 0;
		sw = 8'b01010101;


		#10;
			rst=0;
		#2;
			btn2=1;
		#500;
			btn2=0;




	end
      always #1 clk=~clk;
endmodule