data/full_repos/permissive/120851390/pod-dac-ad9116/hdl/syzygy-dac-top.v
1: b"%Error: data/full_repos/permissive/120851390/pod-dac-ad9116/hdl/syzygy-dac-top.v:66: Cannot find file containing module: 'sync_reset'\nsync_reset dac_reset_sync (\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120851390/pod-dac-ad9116/hdl,data/full_repos/permissive/120851390/sync_reset\n             data/full_repos/permissive/120851390/pod-dac-ad9116/hdl,data/full_repos/permissive/120851390/sync_reset.v\n             data/full_repos/permissive/120851390/pod-dac-ad9116/hdl,data/full_repos/permissive/120851390/sync_reset.sv\n             sync_reset\n             sync_reset.v\n             sync_reset.sv\n             obj_dir/sync_reset\n             obj_dir/sync_reset.v\n             obj_dir/sync_reset.sv\n%Error: data/full_repos/permissive/120851390/pod-dac-ad9116/hdl/syzygy-dac-top.v:72: Cannot find file containing module: 'syzygy_dds_mem'\nsyzygy_dds_mem #(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120851390/pod-dac-ad9116/hdl/syzygy-dac-top.v:85: Cannot find file containing module: 'syzygy_dds'\nsyzygy_dds dds_q (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/120851390/pod-dac-ad9116/hdl/syzygy-dac-top.v:91: Cannot find file containing module: 'syzygy_dac_phy'\nsyzygy_dac_phy dac_phy_impl (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120851390/pod-dac-ad9116/hdl/syzygy-dac-top.v:102: Cannot find file containing module: 'syzygy_dac_spi'\nsyzygy_dac_spi dac_spi (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120851390/pod-dac-ad9116/hdl/syzygy-dac-top.v:119: Cannot find file containing module: 'syzygy_dac_controller'\nsyzygy_dac_controller dac_control (\n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module syzygy_dac_top (
	input  wire        reset_async,
	
	output wire [31:0] dds_addr,
	input  wire [31:0] dds_data,
	input  wire [15:0] dds_rate,
	
	input  wire [15:0] dac_fsadj,

    output wire [11:0] dac_data,
    output wire        dac_clk,
    output wire        dac_reset_pinmd,
    output wire        dac_sclk,
    inout  wire        dac_sdio,
    output wire        dac_cs_n,

	input  wire        clk
	);


wire [11:0] dac_data_i, dac_data_q;
	

wire [5:0] spi_reg;
wire [7:0] spi_data_in, spi_data_out;
wire       spi_send, spi_done, spi_rw;

wire       dac_ready;
wire       reset_sync, reset;

assign reset = reset_sync | ~dac_ready;


sync_reset dac_reset_sync (
	.clk         (clk),
	.async_reset (reset_async),
	.sync_reset  (reset_sync)
);

syzygy_dds_mem #(
	.MEM_SIZE_BITS (12)
) dds_i (
	.clk   (clk),
	.reset (reset),
	
	.rate     (dds_rate),
	.mem_addr (dds_addr),
	.mem_data (dds_data),
	
	.data  (dac_data_i)
);

syzygy_dds dds_q (
	.clk   (clk),
	.reset (reset),
	.data  (dac_data_q)
);

syzygy_dac_phy dac_phy_impl (
	.clk      (clk),
	.reset    (reset_async),

	.data_i   (dac_data_i),
	.data_q   (dac_data_q),
	
	.dac_data (dac_data),
	.dac_clk  (dac_clk)
);

syzygy_dac_spi dac_spi (
	.clk          (clk),
	.reset        (reset_sync),

	.dac_sclk     (dac_sclk),
	.dac_sdio     (dac_sdio),
	.dac_cs_n     (dac_cs_n),
	.dac_reset    (dac_reset_pinmd),

	.spi_reg      (spi_reg),
	.spi_data_in  (spi_data_in),
	.spi_data_out (spi_data_out),
	.spi_send     (spi_send),
	.spi_done     (spi_done),
	.spi_rw       (spi_rw)
);

syzygy_dac_controller dac_control (
	.clk         (clk),
	.reset       (reset_sync),
	
	.dac_fsadj   (dac_fsadj),

	.spi_reg     (spi_reg),
	.spi_data_in (spi_data_in),
	.spi_send    (spi_send),
	.spi_done    (spi_done),
	.spi_rw      (spi_rw),

	.dac_ready   (dac_ready)
);

endmodule
module syzygy_dac_top (
	input  wire        reset_async,
	
	output wire [31:0] dds_addr,
	input  wire [31:0] dds_data,
	input  wire [15:0] dds_rate,
	
	input  wire [15:0] dac_fsadj,

    output wire [11:0] dac_data,
    output wire        dac_clk,
    output wire        dac_reset_pinmd,
    output wire        dac_sclk,
    inout  wire        dac_sdio,
    output wire        dac_cs_n,

	input  wire        clk
	);



wire [11:0] dac_data_i, dac_data_q;
	

wire [5:0] spi_reg;
wire [7:0] spi_data_in, spi_data_out;
wire       spi_send, spi_done, spi_rw;

wire       dac_ready;
wire       reset_sync, reset;

assign reset = reset_sync | ~dac_ready;


sync_reset dac_reset_sync (
	.clk         (clk),
	.async_reset (reset_async),
	.sync_reset  (reset_sync)
);

syzygy_dds_mem #(
	.MEM_SIZE_BITS (12)
) dds_i (
	.clk   (clk),
	.reset (reset),
	
	.rate     (dds_rate),
	.mem_addr (dds_addr),
	.mem_data (dds_data),
	
	.data  (dac_data_i)
);

syzygy_dds dds_q (
	.clk   (clk),
	.reset (reset),
	.data  (dac_data_q)
);

syzygy_dac_phy dac_phy_impl (
	.clk      (clk),
	.reset    (reset_async),

	.data_i   (dac_data_i),
	.data_q   (dac_data_q),
	
	.dac_data (dac_data),
	.dac_clk  (dac_clk)
);

syzygy_dac_spi dac_spi (
	.clk          (clk),
	.reset        (reset_sync),

	.dac_sclk     (dac_sclk),
	.dac_sdio     (dac_sdio),
	.dac_cs_n     (dac_cs_n),
	.dac_reset    (dac_reset_pinmd),

	.spi_reg      (spi_reg),
	.spi_data_in  (spi_data_in),
	.spi_data_out (spi_data_out),
	.spi_send     (spi_send),
	.spi_done     (spi_done),
	.spi_rw       (spi_rw)
);

syzygy_dac_controller dac_control (
	.clk         (clk),
	.reset       (reset_sync),
	
	.dac_fsadj   (dac_fsadj),

	.spi_reg     (spi_reg),
	.spi_data_in (spi_data_in),
	.spi_send    (spi_send),
	.spi_done    (spi_done),
	.spi_rw      (spi_rw),

	.dac_ready   (dac_ready)
);

endmodule