data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_in_v3.v
1: b'%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_in_v3.v:105: Operator GT expects 13 bits on the RHS, but RHS\'s VARREF \'LowColProc\' generates 11 bits.\n                                                                                                                   : ... In instance video_in_v3\n     if( column_counter>LowColProc && column_counter<HighColProc) \n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_in_v3.v:105: Operator LT expects 13 bits on the RHS, but RHS\'s VARREF \'HighColProc\' generates 11 bits.\n                                                                                                                   : ... In instance video_in_v3\n     if( column_counter>LowColProc && column_counter<HighColProc) \n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_in_v3.v:103: Operator GT expects 13 bits on the RHS, but RHS\'s VARREF \'LowLineProc\' generates 11 bits.\n                                                                                                                   : ... In instance video_in_v3\n    if( line_counter>LowLineProc && line_counter<HighLineProc)  \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_in_v3.v:103: Operator LT expects 13 bits on the RHS, but RHS\'s VARREF \'HighLineProc\' generates 11 bits.\n                                                                                                                   : ... In instance video_in_v3\n    if( line_counter>LowLineProc && line_counter<HighLineProc)  \n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_in_v3.v:137: Operator GT expects 13 bits on the RHS, but RHS\'s VARREF \'LowLineProc\' generates 11 bits.\n                                                                                                                   : ... In instance video_in_v3\n    if( line_counter>LowLineProc && line_counter<HighLineProc )\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_in_v3.v:137: Operator LT expects 13 bits on the RHS, but RHS\'s VARREF \'HighLineProc\' generates 11 bits.\n                                                                                                                   : ... In instance video_in_v3\n    if( line_counter>LowLineProc && line_counter<HighLineProc )\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_in_v3.v:187: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'line_counter\' generates 13 bits.\n                                                                                                                   : ... In instance video_in_v3\n      line_max_o  <= line_counter;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/video_in_v3.v:229: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'column_counter\' generates 13 bits.\n                                                                                                                   : ... In instance video_in_v3\n           column_max_o <= column_counter;\n                        ^~\n%Error: Exiting due to 8 warning(s)\n'
module video_in_v3(

	input  pixel_clk_i,rst_i,
	input  hsync_i,vsync_i,
	input  [7:0] red_i,
	input  [7:0] green_i,
	input  [7:0] blue_i,

	output wire clka_bram12_o,
	output reg 	wea_bram12_o,
	output reg 	[6:0] addra_bram12_o,
	output reg [383:0] dina_bram12_o,
	output reg vld_o,
	output wire vld_video_o,
	input wire rdy_i,
	

	input video_ACK_i,
	

	output reg [10:0] column_max_o,
	output reg [10:0] line_max_o );
		

	localparam 	LowLineProc		=	11'd195,
					HighLineProc	=	11'd323,
					LowColProc		=	11'd415,
					HighColProc		=	11'd543;
	

	reg countV_en;
	reg countH_en;
	reg vld_line,vld_column;
	reg [1:0] temp_hsync;
	reg [1:0] temp_vsync;
	reg [12:0] line_counter;
	reg [12:0] column_counter;
	reg [383:0] row2mem; 
	

	wire vld_frame;


	assign vld_video_o	= vld_frame; 
	assign vld_frame		= vld_column & vld_line;	
	assign clka_bram12_o = hsync_i;
	

	always @(posedge pixel_clk_i or posedge rst_i)
	begin
		if(rst_i)
		begin
			row2mem<=0;
		end
		else
		begin
			if(vld_frame && video_ACK_i)
			begin
				if( line_counter>LowLineProc && line_counter<HighLineProc)
				begin
					if( column_counter>LowColProc && column_counter<HighColProc)
					begin
						row2mem[2]		<=	red_i[7];	
						row2mem[1]		<=	green_i[7];	
						row2mem[0]		<=	blue_i[7];		
						row2mem[383:3]	<=	row2mem[380:0];
					end
				end
			end			
		end
	end
	

	always @(negedge hsync_i or posedge rst_i) 
	begin
		if(rst_i)
		begin
			addra_bram12_o<=7'd0;
			wea_bram12_o<=0;
			dina_bram12_o<=0;
			vld_o<=0;
		end
		else
		begin
			if(vld_frame && video_ACK_i)
			begin
				if(~rdy_i) vld_o<=0;
				else
				begin
					if(addra_bram12_o==7'd126) vld_o<=1'b1;
				end	
				
				if( line_counter>LowLineProc && line_counter<HighLineProc )
				begin
					if(addra_bram12_o!=7'd127)
					begin
						addra_bram12_o<=addra_bram12_o+1'b1;
						dina_bram12_o<=row2mem;
						wea_bram12_o<=1'b1;
					end
					else
					begin
							wea_bram12_o<=1'b0;
					end
				end
				else
				begin
					wea_bram12_o<=1'b0;
					if(~vsync_i) addra_bram12_o<=0;
				end
			end
			else
			begin
				wea_bram12_o<=0;
			end
		end
	end
	

	always @(posedge hsync_i or posedge rst_i) 
	begin
		if(rst_i)
		begin
			line_counter	<= 0;
			vld_line			<= 1'b0;
			line_max_o		<= 0;
			temp_vsync		<= 2'b00;
			countV_en		<= 1'b0;
		end
		else
		begin
			if( video_ACK_i)
			begin

				temp_vsync[0]	<= vsync_i;
				temp_vsync[1]	<= temp_vsync[0];
				
				if(temp_vsync==2'b10)
				begin
					countV_en	<= 1'b1;
					if(line_max_o == 0 && countV_en == 1'b1)
					begin
						line_max_o		<= line_counter;
						vld_line		<= 1'b1;
						line_counter	<= 0;
					end
					else line_counter<= 0;
				end
				else line_counter	<= line_counter + 1'b1; 
			end	
		end
	end
	

	always @(posedge pixel_clk_i or posedge rst_i)
	begin
		if(rst_i)
		begin
			column_counter	<= 0;
			vld_column		<= 1'b0;
			column_max_o	<= 0;
			countH_en		<= 1'b0;
			temp_hsync		<= 2'b00;
		end
		else
		begin
			if(video_ACK_i)
			begin
				temp_hsync[0]<=hsync_i;
				temp_hsync[1]<=temp_hsync[0];
				if(vsync_i)
				begin
					if(temp_hsync == 2'b10 && countH_en == 0) countH_en	<= 1'b1; 
					else
					begin
						case(temp_hsync)
						2'b11  : begin

									column_counter	<= column_counter + 1'b1;

									end	
						2'b10  : begin
										if(column_max_o == 0)
										begin
											column_max_o	<= column_counter;
											vld_column		<= 1'b1;
											column_counter	<= 0;
										end
										else column_counter	<= 0;
									end	
						default: column_counter	<= 0;
						endcase
					end	
				end	
			end	
		end
	end
endmodule
module video_in_v3(

	input  pixel_clk_i,rst_i,
	input  hsync_i,vsync_i,
	input  [7:0] red_i,
	input  [7:0] green_i,
	input  [7:0] blue_i,

	output wire clka_bram12_o,
	output reg 	wea_bram12_o,
	output reg 	[6:0] addra_bram12_o,
	output reg [383:0] dina_bram12_o,
	output reg vld_o,
	output wire vld_video_o,
	input wire rdy_i,
	

	input video_ACK_i,
	

	output reg [10:0] column_max_o,
	output reg [10:0] line_max_o );

		

	localparam 	LowLineProc		=	11'd195,
					HighLineProc	=	11'd323,
					LowColProc		=	11'd415,
					HighColProc		=	11'd543;
	

	reg countV_en;
	reg countH_en;
	reg vld_line,vld_column;
	reg [1:0] temp_hsync;
	reg [1:0] temp_vsync;
	reg [12:0] line_counter;
	reg [12:0] column_counter;
	reg [383:0] row2mem; 
	

	wire vld_frame;


	assign vld_video_o	= vld_frame; 
	assign vld_frame		= vld_column & vld_line;	
	assign clka_bram12_o = hsync_i;
	

	always @(posedge pixel_clk_i or posedge rst_i)
	begin
		if(rst_i)
		begin
			row2mem<=0;
		end
		else
		begin
			if(vld_frame && video_ACK_i)
			begin
				if( line_counter>LowLineProc && line_counter<HighLineProc)
				begin
					if( column_counter>LowColProc && column_counter<HighColProc)
					begin
						row2mem[2]		<=	red_i[7];	
						row2mem[1]		<=	green_i[7];	
						row2mem[0]		<=	blue_i[7];		
						row2mem[383:3]	<=	row2mem[380:0];
					end
				end
			end			
		end
	end
	

	always @(negedge hsync_i or posedge rst_i) 
	begin
		if(rst_i)
		begin
			addra_bram12_o<=7'd0;
			wea_bram12_o<=0;
			dina_bram12_o<=0;
			vld_o<=0;
		end
		else
		begin
			if(vld_frame && video_ACK_i)
			begin
				if(~rdy_i) vld_o<=0;
				else
				begin
					if(addra_bram12_o==7'd126) vld_o<=1'b1;
				end	
				
				if( line_counter>LowLineProc && line_counter<HighLineProc )
				begin
					if(addra_bram12_o!=7'd127)
					begin
						addra_bram12_o<=addra_bram12_o+1'b1;
						dina_bram12_o<=row2mem;
						wea_bram12_o<=1'b1;
					end
					else
					begin
							wea_bram12_o<=1'b0;
					end
				end
				else
				begin
					wea_bram12_o<=1'b0;
					if(~vsync_i) addra_bram12_o<=0;
				end
			end
			else
			begin
				wea_bram12_o<=0;
			end
		end
	end
	

	always @(posedge hsync_i or posedge rst_i) 
	begin
		if(rst_i)
		begin
			line_counter	<= 0;
			vld_line			<= 1'b0;
			line_max_o		<= 0;
			temp_vsync		<= 2'b00;
			countV_en		<= 1'b0;
		end
		else
		begin
			if( video_ACK_i)
			begin

				temp_vsync[0]	<= vsync_i;
				temp_vsync[1]	<= temp_vsync[0];
				
				if(temp_vsync==2'b10)
				begin
					countV_en	<= 1'b1;
					if(line_max_o == 0 && countV_en == 1'b1)
					begin
						line_max_o		<= line_counter;
						vld_line		<= 1'b1;
						line_counter	<= 0;
					end
					else line_counter<= 0;
				end
				else line_counter	<= line_counter + 1'b1; 
			end	
		end
	end
	

	always @(posedge pixel_clk_i or posedge rst_i)
	begin
		if(rst_i)
		begin
			column_counter	<= 0;
			vld_column		<= 1'b0;
			column_max_o	<= 0;
			countH_en		<= 1'b0;
			temp_hsync		<= 2'b00;
		end
		else
		begin
			if(video_ACK_i)
			begin
				temp_hsync[0]<=hsync_i;
				temp_hsync[1]<=temp_hsync[0];
				if(vsync_i)
				begin
					if(temp_hsync == 2'b10 && countH_en == 0) countH_en	<= 1'b1; 
					else
					begin
						case(temp_hsync)
						2'b11  : begin

									column_counter	<= column_counter + 1'b1;

									end	
						2'b10  : begin
										if(column_max_o == 0)
										begin
											column_max_o	<= column_counter;
											vld_column		<= 1'b1;
											column_counter	<= 0;
										end
										else column_counter	<= 0;
									end	
						default: column_counter	<= 0;
						endcase
					end	
				end	
			end	
		end
	end
endmodule