data/full_repos/permissive/199399537/sys_ctrl.v
1: b"%Error: data/full_repos/permissive/199399537/sys_ctrl.v:69: Cannot find file containing module: 'PLL'\nPLL   uut_PLL_ctrl(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/PLL\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/PLL.v\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/PLL.sv\n             PLL\n             PLL.v\n             PLL.sv\n             obj_dir/PLL\n             obj_dir/PLL.v\n             obj_dir/PLL.sv\n%Error: Exiting due to 1 error(s)\n"
module sys_ctrl(
				clk,
				rst_n,
				sys_rst_n,
				clk_20m,
				clk_100m,
				sdram_clk
			);

input clk;
input rst_n;

output sys_rst_n;

output clk_20m;
output clk_100m;
output sdram_clk;

wire locked;




wire pll_rst;

reg rst_r1,rst_r2;

always @(posedge clk or negedge rst_n)
	if(!rst_n) 
		rst_r1 <= 1'b1;
	else 
		rst_r1 <= 1'b0;

always @(posedge clk or negedge rst_n)
	if(!rst_n) 
		rst_r2 <= 1'b1;
	else 
		rst_r2 <= rst_r1;

assign pll_rst = rst_r2;




wire sys_rst_n;
wire sysrst_nr0;
reg sysrst_nr1,sysrst_nr2;

assign sysrst_nr0 = rst_n & locked;

always @(posedge clk_100m or negedge sysrst_nr0)
	if(!sysrst_nr0) 
		sysrst_nr1 <= 1'b0;
	else 
		sysrst_nr1 <= 1'b1;

always @(posedge clk_100m or negedge sysrst_nr0)
	if(!sysrst_nr0) 
		sysrst_nr2 <= 1'b0;
	else 
		sysrst_nr2 <= sysrst_nr1;

assign sys_rst_n = sysrst_nr2;



PLL 		uut_PLL_ctrl(
					.areset(pll_rst),	
					.inclk0(clk),		
					.c0(clk_100m),					
					.c1(clk_20m),		
					.c2(sdram_clk),		
					.locked(locked)		
				);
				

endmodule
module sys_ctrl(
				clk,
				rst_n,
				sys_rst_n,
				clk_20m,
				clk_100m,
				sdram_clk
			);


input clk;
input rst_n;

output sys_rst_n;

output clk_20m;
output clk_100m;
output sdram_clk;

wire locked;




wire pll_rst;

reg rst_r1,rst_r2;

always @(posedge clk or negedge rst_n)
	if(!rst_n) 
		rst_r1 <= 1'b1;
	else 
		rst_r1 <= 1'b0;

always @(posedge clk or negedge rst_n)
	if(!rst_n) 
		rst_r2 <= 1'b1;
	else 
		rst_r2 <= rst_r1;

assign pll_rst = rst_r2;




wire sys_rst_n;
wire sysrst_nr0;
reg sysrst_nr1,sysrst_nr2;

assign sysrst_nr0 = rst_n & locked;

always @(posedge clk_100m or negedge sysrst_nr0)
	if(!sysrst_nr0) 
		sysrst_nr1 <= 1'b0;
	else 
		sysrst_nr1 <= 1'b1;

always @(posedge clk_100m or negedge sysrst_nr0)
	if(!sysrst_nr0) 
		sysrst_nr2 <= 1'b0;
	else 
		sysrst_nr2 <= sysrst_nr1;

assign sys_rst_n = sysrst_nr2;



PLL 		uut_PLL_ctrl(
					.areset(pll_rst),	
					.inclk0(clk),		
					.c0(clk_100m),					
					.c1(clk_20m),		
					.c2(sdram_clk),		
					.locked(locked)		
				);
				

endmodule