data/full_repos/permissive/214823094/submissions/lab_4/project_1/ALU.v
data/verilator_xmls/e26a1419-41f2-47e6-a198-f0be3fa3fb27.xml
module xor_(a,b,ans);
    input [3:0] a,b;
    output [3:0] ans;
    
    assign ans[3:0]=a[3:0]^b[3:0];
    
endmodule
module xor_(a,b,ans);

    input [3:0] a,b;
    output [3:0] ans;
    
    assign ans[3:0]=a[3:0]^b[3:0];
    
endmodule