data/full_repos/permissive/208556773/src/dual_hbridge.v
 line:78: before: "if"
1: b"%Error: data/full_repos/permissive/208556773/src/dual_hbridge.v:38: Cannot find file containing module: 'space_vector_modulator'\n  space_vector_modulator #(\n  ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208556773/src,data/full_repos/permissive/208556773/space_vector_modulator\n             data/full_repos/permissive/208556773/src,data/full_repos/permissive/208556773/space_vector_modulator.v\n             data/full_repos/permissive/208556773/src,data/full_repos/permissive/208556773/space_vector_modulator.sv\n             space_vector_modulator\n             space_vector_modulator.v\n             space_vector_modulator.sv\n             obj_dir/space_vector_modulator\n             obj_dir/space_vector_modulator.v\n             obj_dir/space_vector_modulator.sv\n%Error: Exiting due to 1 error(s)\n"
module dual_hbridge #(
   parameter current_bits = 4,
   parameter microstep_bits = 8,
   parameter vref_off_brake = 1,
   parameter microstep_count = 256
) (
    input clk,
    input resetn,
    input pwm_clk,
    output       phase_a1,
    output       phase_a2,
    output       phase_b1,
    output       phase_b2,
    output       vref_a,
    output       vref_b,
    input        enable,
    input        brake,
    input  [current_bits-1:0] current,
    input  [phase_ct_end:0] phase_angle,
    output wire faultn
);



  localparam phase_ct_end = $clog2(microstep_count*4) - 1; 









  space_vector_modulator #(
    .current_bits(current_bits),
    .phase_ct_bits(phase_ct_end+1),
    .microsteps(microstep_count)
  )
    svm0 (.clk(clk),
          .pwm_clk(pwm_clk),
          .resetn(resetn),
          .vref_pwm({vref_b,vref_a}),

          .current(current),
          .phase_ct(phase_angle));








  wire [1:0] phase_polarity;

  assign phase_polarity = (phase_angle[phase_ct_end:phase_ct_end-1] == 2'b00 ) ? 2'b11 :
                          (phase_angle[phase_ct_end:phase_ct_end-1] == 2'b01 ) ? 2'b01 :
                          (phase_angle[phase_ct_end:phase_ct_end-1] == 2'b10 ) ? 2'b00 :
                                                                                 2'b10 ;


  assign phase_a1 = (enable & vref_a) ?  phase_polarity[0] : brake_a;
  assign phase_a2 = (enable & vref_a) ? ~phase_polarity[0] : brake_a;
  assign phase_b1 = (enable & vref_b) ?  phase_polarity[1] : brake_b;
  assign phase_b2 = (enable & vref_b) ? ~phase_polarity[1] : brake_b;







  wire brake_a, brake_b;
  if (vref_off_brake) begin
    assign brake_a = ((!enable & brake) | !vref_a);
    assign brake_b = ((!enable & brake) | !vref_b);
  end else begin
    assign brake_a = brake;
    assign brake_b = brake;
  end

endmodule
module dual_hbridge #(
   parameter current_bits = 4,
   parameter microstep_bits = 8,
   parameter vref_off_brake = 1,
   parameter microstep_count = 256
) (
    input clk,
    input resetn,
    input pwm_clk,
    output       phase_a1,
    output       phase_a2,
    output       phase_b1,
    output       phase_b2,
    output       vref_a,
    output       vref_b,
    input        enable,
    input        brake,
    input  [current_bits-1:0] current,
    input  [phase_ct_end:0] phase_angle,
    output wire faultn
);




  localparam phase_ct_end = $clog2(microstep_count*4) - 1; 









  space_vector_modulator #(
    .current_bits(current_bits),
    .phase_ct_bits(phase_ct_end+1),
    .microsteps(microstep_count)
  )
    svm0 (.clk(clk),
          .pwm_clk(pwm_clk),
          .resetn(resetn),
          .vref_pwm({vref_b,vref_a}),

          .current(current),
          .phase_ct(phase_angle));








  wire [1:0] phase_polarity;

  assign phase_polarity = (phase_angle[phase_ct_end:phase_ct_end-1] == 2'b00 ) ? 2'b11 :
                          (phase_angle[phase_ct_end:phase_ct_end-1] == 2'b01 ) ? 2'b01 :
                          (phase_angle[phase_ct_end:phase_ct_end-1] == 2'b10 ) ? 2'b00 :
                                                                                 2'b10 ;


  assign phase_a1 = (enable & vref_a) ?  phase_polarity[0] : brake_a;
  assign phase_a2 = (enable & vref_a) ? ~phase_polarity[0] : brake_a;
  assign phase_b1 = (enable & vref_b) ?  phase_polarity[1] : brake_b;
  assign phase_b2 = (enable & vref_b) ? ~phase_polarity[1] : brake_b;







  wire brake_a, brake_b;
  if (vref_off_brake) begin
    assign brake_a = ((!enable & brake) | !vref_a);
    assign brake_b = ((!enable & brake) | !vref_b);
  end else begin
    assign brake_a = brake;
    assign brake_b = brake;
  end

endmodule