data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Mux_51.v
data/verilator_xmls/08222d1e-4496-47d1-8075-3ca71a5e6c27.xml
module Mux_51(Y,A0,A1,A2,A3,A4,sel);

output	[7:0]Y;
input	[7:0]A4,A3,A2,A1,A0;
input	[2:0]sel;

reg		[7:0]Y;

always@(*)
	begin
		case(sel)
			0:	Y=A0;
			1:	Y=A1;
			2:	Y=A2;
			3:	Y=A3;
			4:	Y=A4;
			default:Y=8'bx;
		endcase
	end

endmodule
module Mux_51(Y,A0,A1,A2,A3,A4,sel);


output	[7:0]Y;
input	[7:0]A4,A3,A2,A1,A0;
input	[2:0]sel;

reg		[7:0]Y;

always@(*)
	begin
		case(sel)
			0:	Y=A0;
			1:	Y=A1;
			2:	Y=A2;
			3:	Y=A3;
			4:	Y=A4;
			default:Y=8'bx;
		endcase
	end

endmodule