data/full_repos/permissive/174263347/scanconv/hdl/scanconv.v
1: b'%Error: data/full_repos/permissive/174263347/scanconv/hdl/scanconv.v:5: Cannot find include file: vga.v\n`include "vga.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174263347/scanconv/hdl,data/full_repos/permissive/174263347/vga.v\n             data/full_repos/permissive/174263347/scanconv/hdl,data/full_repos/permissive/174263347/vga.v.v\n             data/full_repos/permissive/174263347/scanconv/hdl,data/full_repos/permissive/174263347/vga.v.sv\n             vga.v\n             vga.v.v\n             vga.v.sv\n             obj_dir/vga.v\n             obj_dir/vga.v.v\n             obj_dir/vga.v.sv\n%Error: data/full_repos/permissive/174263347/scanconv/hdl/scanconv.v:6: Cannot find include file: memory.v\n`include "memory.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/hdl/scanconv.v:7: Cannot find include file: cgaega.v\n`include "cgaega.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/174263347/scanconv/hdl/scanconv.v:8: Cannot find include file: syncinv.v\n`include "syncinv.v" \n         ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module scanconv ( clk, nReset, hsync, vsync, ega, iVideo, oVideo, csync, relay, aMem, dMem, nCs, nOe, nWe );


    input   hsync, vsync;
    input   clk,  nReset, iVideo;
    output  csync, relay, oVideo;
    input   ega;

    output  [15:0] aMem;
    inout   [7:0]  dMem;
    output  nCs, nOe, nWe;


    wire    save;
    wire    reset;


    assign  reset = ~nReset;

    wire    [7:0] dVga, dCga;
    wire    [15:0] aVga, aCga;
    wire    wrVga, wrVgaReq;
    wire    dirout;
    wire    [7:0] dMemOut;
    wire    halfclk;
    wire    access;

vga         ivga (  clk,
                    reset,
                    iVideo,
                    vsync,
 				    hsync,
                    dVga,
                    aVga,
                    wrVga,
                    wrVgaReq,
					notVga,
					lines350
                 );

memory      imemory(clk,
                    reset,
                    wrVga,
                    dVga,
                    aVga,
                    dCga,
                    aCga,
                    dMem,
                    dMemOut,
                    aMem,
                    dirout,
                    nCs,
                    nOe,
                    nWe,
                    access,
                    halfclk,
                    wrVgaReq
                   );

cgaega      icgaega(clk,
                    reset,
                    access,
                    halfclk,
                    ega,
                    dCga,
                    aCga,
                    csync,
                    oVideo
					);

assign dMem[7:0] = dirout ? 8'bzzzzzzzz : dMemOut;

assign relay = notVga;

endmodule
module scanconv ( clk, nReset, hsync, vsync, ega, iVideo, oVideo, csync, relay, aMem, dMem, nCs, nOe, nWe );



    input   hsync, vsync;
    input   clk,  nReset, iVideo;
    output  csync, relay, oVideo;
    input   ega;

    output  [15:0] aMem;
    inout   [7:0]  dMem;
    output  nCs, nOe, nWe;


    wire    save;
    wire    reset;


    assign  reset = ~nReset;

    wire    [7:0] dVga, dCga;
    wire    [15:0] aVga, aCga;
    wire    wrVga, wrVgaReq;
    wire    dirout;
    wire    [7:0] dMemOut;
    wire    halfclk;
    wire    access;

vga         ivga (  clk,
                    reset,
                    iVideo,
                    vsync,
 				    hsync,
                    dVga,
                    aVga,
                    wrVga,
                    wrVgaReq,
					notVga,
					lines350
                 );

memory      imemory(clk,
                    reset,
                    wrVga,
                    dVga,
                    aVga,
                    dCga,
                    aCga,
                    dMem,
                    dMemOut,
                    aMem,
                    dirout,
                    nCs,
                    nOe,
                    nWe,
                    access,
                    halfclk,
                    wrVgaReq
                   );

cgaega      icgaega(clk,
                    reset,
                    access,
                    halfclk,
                    ega,
                    dCga,
                    aCga,
                    csync,
                    oVideo
					);

assign dMem[7:0] = dirout ? 8'bzzzzzzzz : dMemOut;

assign relay = notVga;

endmodule