data/full_repos/permissive/208603716/rtl/clampSPositive.v
data/verilator_xmls/72a04a78-73be-4e3a-b38f-7b9a24942fa2.xml
module clampSPositive
#(	parameter INW  = 16,
	parameter OUTW = 8
)
(
	input  signed [ INW-1:0] valueIn,
	output        [OUTW-1:0] valueOut
);

	wire isPos					= !valueIn[INW-1];
	wire [OUTW-1:0] andStage	= {OUTW{isPos}};
	

	wire overF					= |valueIn[INW-2:OUTW];
	
	assign valueOut = ( valueIn[OUTW-1:0] | {OUTW{overF}} ) & andStage;
endmodule
module clampSPositive
#(	parameter INW  = 16,
	parameter OUTW = 8
)
(
	input  signed [ INW-1:0] valueIn,
	output        [OUTW-1:0] valueOut
);


	wire isPos					= !valueIn[INW-1];
	wire [OUTW-1:0] andStage	= {OUTW{isPos}};
	

	wire overF					= |valueIn[INW-2:OUTW];
	
	assign valueOut = ( valueIn[OUTW-1:0] | {OUTW{overF}} ) & andStage;
endmodule