data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v
 line:49: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n always #10 rclk <= ~rclk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n always #5 wclk <= ~wclk;\n        ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v:23: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("mm.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v:24: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #2\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #20  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #10  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #30  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #20  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo_dc_gray_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifo_dc_gray_tb;
	
	reg	rclk	= 1;
	reg	wclk	= 1;
	reg	reset	= 0;
	reg	read	= 0;
	reg	write	= 0;
	
	reg	[17:0]	wr_data	= 0;
	wire	[17:0]	rd_data;
	
	wire	[1:0]	rlev, wlev;
	wire	full, empty;
	
	always	#10	rclk	<= ~rclk;
	always	#5	wclk	<= ~wclk;
	
	
	initial begin : Sim

		$write ("%% ");
		$dumpfile ("mm.vcd");
		$dumpvars;
		
		#2
		reset	= 1;
		
		#20
		reset	= 0;
		
		#30
		write	= 1;
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		write	= 0;
		
		#30
		read	= 1;
		
		#20
		read	= 0;
		
		#30
		$finish;
	end
	
	
	fifo_dc_gray #(18,4,16) FIFO0 (
		.rd_clk		(rclk),
		.wr_clk		(wclk),
		.rst		(1),
		.clr		(reset),
		.din		(wr_data),
		.we		(write),
		
		.dout		(rd_data),
		.re		(read),
		.full		(full),
		.empty		(empty),
		.wr_level	(wlev),
		.rd_level	(rlev)
	);
	
	
endmodule
module fifo_dc_gray_tb;

	
	reg	rclk	= 1;
	reg	wclk	= 1;
	reg	reset	= 0;
	reg	read	= 0;
	reg	write	= 0;
	
	reg	[17:0]	wr_data	= 0;
	wire	[17:0]	rd_data;
	
	wire	[1:0]	rlev, wlev;
	wire	full, empty;
	
	always	#10	rclk	<= ~rclk;
	always	#5	wclk	<= ~wclk;
	
	
	initial begin : Sim

		$write ("%% ");
		$dumpfile ("mm.vcd");
		$dumpvars;
		
		#2
		reset	= 1;
		
		#20
		reset	= 0;
		
		#30
		write	= 1;
		wr_data	= 18'h30F0;
		
		#10
		wr_data	= 18'h0A0A;
		
		#10
		write	= 0;
		
		#30
		read	= 1;
		
		#20
		read	= 0;
		
		#30
		$finish;
	end
	
	
	fifo_dc_gray #(18,4,16) FIFO0 (
		.rd_clk		(rclk),
		.wr_clk		(wclk),
		.rst		(1),
		.clr		(reset),
		.din		(wr_data),
		.we		(write),
		
		.dout		(rd_data),
		.re		(read),
		.full		(full),
		.empty		(empty),
		.wr_level	(wlev),
		.rd_level	(rlev)
	);
	
	
endmodule