data/full_repos/permissive/19340845/test/RegisterTest.v
 line:53: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:12: Unsupported: Ignoring delay on this delayed statement.\n      clock = 0; #(STEP / 2);\n                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:13: Unsupported: Ignoring delay on this delayed statement.\n      clock = 1; #(STEP / 2);\n                 ^\n%Error: data/full_repos/permissive/19340845/test/RegisterTest.v:17: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("registerTest.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19340845/test/RegisterTest.v:18: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, REGISTERTEST);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19340845/test/RegisterTest.v:19: Unsupported or unknown PLI call: $monitor\n      $monitor ("%t: clock = %b, write = %b, reset = %b, address1 = %b, writeAddress = %b, writeData = %b, data1 = %b", $time, clock, write, reset, address1, writeAddress, writeData, data1);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #STEP writeAddress = 3\'b001; writeData = 16\'b0000_0000_0000_0010;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #STEP writeAddress = 3\'b010; writeData = 16\'b0000_0000_0000_0100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #STEP writeAddress = 3\'b011; writeData = 16\'b0000_0000_0000_1000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #STEP writeAddress = 3\'b100; writeData = 16\'b0000_0000_0001_0000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #STEP writeAddress = 3\'b101; writeData = 16\'b0000_0000_0010_0000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #STEP writeAddress = 3\'b110; writeData = 16\'b0000_0000_0100_0000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #STEP writeAddress = 3\'b111; writeData = 16\'b0000_0000_1000_0000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #STEP writeAddress = 3\'b000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b001;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b010;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b011;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b101;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b110;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b111;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b001;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b010;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b011;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:48: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b101;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b110;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b111;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #STEP address1 = 3\'b000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/RegisterTest.v:53: Unsupported: Ignoring delay on this delayed statement.\n      #STEP $finish;\n      ^\n%Error: Exiting due to 3 error(s), 27 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module REGISTERTEST;
   reg clock, write, reset;
   reg [2:0] address1, address2, writeAddress;
   reg [15:0] writeData;
   wire [15:0] data1, data2;

   parameter STEP = 2;
   
   Register r (clock, write, reset, address1, address2, writeAddress, writeData, data1, data2);

   always begin
      clock = 0; #(STEP / 2);
      clock = 1; #(STEP / 2);
   end

   initial begin
      $dumpfile("registerTest.vcd");
      $dumpvars(0, REGISTERTEST);
      $monitor ("%t: clock = %b, write = %b, reset = %b, address1 = %b, writeAddress = %b, writeData = %b, data1 = %b", $time, clock, write, reset, address1, writeAddress, writeData, data1);

      $display(" --- write ---");
      write = 1'b1; writeAddress = 3'b000; writeData = 16'b0000_0000_0000_0001;
      #STEP writeAddress = 3'b001; writeData = 16'b0000_0000_0000_0010;
      #STEP writeAddress = 3'b010; writeData = 16'b0000_0000_0000_0100;
      #STEP writeAddress = 3'b011; writeData = 16'b0000_0000_0000_1000;
      #STEP writeAddress = 3'b100; writeData = 16'b0000_0000_0001_0000;
      #STEP writeAddress = 3'b101; writeData = 16'b0000_0000_0010_0000;
      #STEP writeAddress = 3'b110; writeData = 16'b0000_0000_0100_0000;
      #STEP writeAddress = 3'b111; writeData = 16'b0000_0000_1000_0000;
      #STEP writeAddress = 3'b000;

      $display(" --- load ---");
      write = 1'b0; address1 = 3'b000;
      #STEP address1 = 3'b001;
      #STEP address1 = 3'b010;
      #STEP address1 = 3'b011;
      #STEP address1 = 3'b100;
      #STEP address1 = 3'b101;
      #STEP address1 = 3'b110;
      #STEP address1 = 3'b111;
      #STEP address1 = 3'b000;
      
      $display(" --- reset ---");
      reset = 1'b1; 
      #STEP address1 = 3'b001;
      #STEP address1 = 3'b010;
      #STEP address1 = 3'b011;
      #STEP address1 = 3'b100;
      #STEP address1 = 3'b101;
      #STEP address1 = 3'b110;
      #STEP address1 = 3'b111;
      #STEP address1 = 3'b000;
      #STEP $finish;
      
   end
endmodule
module REGISTERTEST;

   reg clock, write, reset;
   reg [2:0] address1, address2, writeAddress;
   reg [15:0] writeData;
   wire [15:0] data1, data2;

   parameter STEP = 2;
   
   Register r (clock, write, reset, address1, address2, writeAddress, writeData, data1, data2);

   always begin
      clock = 0; #(STEP / 2);
      clock = 1; #(STEP / 2);
   end

   initial begin
      $dumpfile("registerTest.vcd");
      $dumpvars(0, REGISTERTEST);
      $monitor ("%t: clock = %b, write = %b, reset = %b, address1 = %b, writeAddress = %b, writeData = %b, data1 = %b", $time, clock, write, reset, address1, writeAddress, writeData, data1);

      $display(" --- write ---");
      write = 1'b1; writeAddress = 3'b000; writeData = 16'b0000_0000_0000_0001;
      #STEP writeAddress = 3'b001; writeData = 16'b0000_0000_0000_0010;
      #STEP writeAddress = 3'b010; writeData = 16'b0000_0000_0000_0100;
      #STEP writeAddress = 3'b011; writeData = 16'b0000_0000_0000_1000;
      #STEP writeAddress = 3'b100; writeData = 16'b0000_0000_0001_0000;
      #STEP writeAddress = 3'b101; writeData = 16'b0000_0000_0010_0000;
      #STEP writeAddress = 3'b110; writeData = 16'b0000_0000_0100_0000;
      #STEP writeAddress = 3'b111; writeData = 16'b0000_0000_1000_0000;
      #STEP writeAddress = 3'b000;

      $display(" --- load ---");
      write = 1'b0; address1 = 3'b000;
      #STEP address1 = 3'b001;
      #STEP address1 = 3'b010;
      #STEP address1 = 3'b011;
      #STEP address1 = 3'b100;
      #STEP address1 = 3'b101;
      #STEP address1 = 3'b110;
      #STEP address1 = 3'b111;
      #STEP address1 = 3'b000;
      
      $display(" --- reset ---");
      reset = 1'b1; 
      #STEP address1 = 3'b001;
      #STEP address1 = 3'b010;
      #STEP address1 = 3'b011;
      #STEP address1 = 3'b100;
      #STEP address1 = 3'b101;
      #STEP address1 = 3'b110;
      #STEP address1 = 3'b111;
      #STEP address1 = 3'b000;
      #STEP $finish;
      
   end
endmodule