data/full_repos/permissive/123796236/reg32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123796236/reg32.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #100 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reg32 (clk, reset, d_in, d_out);

input clk, reset;
input [31:0] d_in;
output [31:0] d_out;
reg [31:0]	d_out;

always @(posedge clk)
	begin
		if (reset) d_out <= 0;
		else d_out <= d_in;
	end
endmodule
module reg32 (clk, reset, d_in, d_out);


input clk, reset;
input [31:0] d_in;
output [31:0] d_out;
reg [31:0]	d_out;

always @(posedge clk)
	begin
		if (reset) d_out <= 0;
		else d_out <= d_in;
	end
endmodule