data/full_repos/permissive/169382915/rtl/coprocessor/scarv_cop_rng.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/169382915/rtl/coprocessor/scarv_cop_rng.v:39: Cannot find include file: scarv_cop_common.vh\n`include "scarv_cop_common.vh" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169382915/rtl/coprocessor,data/full_repos/permissive/169382915/scarv_cop_common.vh\n             data/full_repos/permissive/169382915/rtl/coprocessor,data/full_repos/permissive/169382915/scarv_cop_common.vh.v\n             data/full_repos/permissive/169382915/rtl/coprocessor,data/full_repos/permissive/169382915/scarv_cop_common.vh.sv\n             scarv_cop_common.vh\n             scarv_cop_common.vh.v\n             scarv_cop_common.vh.sv\n             obj_dir/scarv_cop_common.vh\n             obj_dir/scarv_cop_common.vh.v\n             obj_dir/scarv_cop_common.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module scarv_cop_rng (
input  wire         g_clk            ,
input  wire         g_resetn         ,

input  wire         rng_ivalid       ,
output wire         rng_idone        ,

`ifndef SYNTHESIS

output wire [31:0]  cop_random       ,
output wire         cop_rand_sample  ,
`endif

input  wire [31:0]  rng_rs1          ,

input  wire [31:0]  id_imm           ,
input  wire [15:0]  id_subclass      ,

output wire [ 3:0]  rng_cpr_rd_ben   ,
output wire [31:0]  rng_cpr_rd_wdata
);

`include "scarv_cop_common.vh"




parameter   RNG_TYPE        = SCARV_COP_RNG_TYPE_LFSR32;
parameter   RNG_RESET_VALUE = 32'b0;



wire [31:0] rng_output;

`ifndef SYNTHESIS


assign cop_random       = rng_output;
assign cop_rand_sample  = is_rsamp;

`endif



wire is_rseed   = rng_ivalid && id_subclass[SCARV_COP_SCLASS_RSEED];

wire is_rsamp   = rng_ivalid && id_subclass[SCARV_COP_SCLASS_RSAMP];

wire is_rtest   = rng_ivalid && id_subclass[SCARV_COP_SCLASS_RTEST];



assign rng_cpr_rd_ben   = is_rsamp ? 4'b1111    : 4'b0000;
assign rng_cpr_rd_wdata = is_rsamp ? rng_output :
                          is_rtest ? 32'b1      :
                                     32'b0      ;
assign rng_idone        = is_rseed || is_rsamp || is_rtest;

generate if(RNG_TYPE == SCARV_COP_RNG_TYPE_LFSR32) begin : gen_lfsr32







    reg [31:0] rng_value;
    wire[31:0] n_rng_value;
    wire       n_lsb = rng_value[31] ~^ 
                       rng_value[21] ~^ 
                       rng_value[ 1] ~^
                       rng_value[ 0]  ;

    assign n_rng_value = is_rseed ? rng_rs1
                                  : rng_value << 1 | n_lsb;

    always @(posedge g_clk) if(!g_resetn) begin
        rng_value <= RNG_RESET_VALUE;
    end else begin
        rng_value <= n_rng_value;
    end

    assign rng_output = rng_value;

end else begin

    assign rng_output = 0;

end endgenerate

endmodule
module scarv_cop_rng (
input  wire         g_clk            ,
input  wire         g_resetn         ,

input  wire         rng_ivalid       ,
output wire         rng_idone        ,

`ifndef SYNTHESIS

output wire [31:0]  cop_random       ,
output wire         cop_rand_sample  ,
`endif

input  wire [31:0]  rng_rs1          ,

input  wire [31:0]  id_imm           ,
input  wire [15:0]  id_subclass      ,

output wire [ 3:0]  rng_cpr_rd_ben   ,
output wire [31:0]  rng_cpr_rd_wdata
);


`include "scarv_cop_common.vh"




parameter   RNG_TYPE        = SCARV_COP_RNG_TYPE_LFSR32;
parameter   RNG_RESET_VALUE = 32'b0;



wire [31:0] rng_output;

`ifndef SYNTHESIS


assign cop_random       = rng_output;
assign cop_rand_sample  = is_rsamp;

`endif



wire is_rseed   = rng_ivalid && id_subclass[SCARV_COP_SCLASS_RSEED];

wire is_rsamp   = rng_ivalid && id_subclass[SCARV_COP_SCLASS_RSAMP];

wire is_rtest   = rng_ivalid && id_subclass[SCARV_COP_SCLASS_RTEST];



assign rng_cpr_rd_ben   = is_rsamp ? 4'b1111    : 4'b0000;
assign rng_cpr_rd_wdata = is_rsamp ? rng_output :
                          is_rtest ? 32'b1      :
                                     32'b0      ;
assign rng_idone        = is_rseed || is_rsamp || is_rtest;

generate if(RNG_TYPE == SCARV_COP_RNG_TYPE_LFSR32) begin : gen_lfsr32







    reg [31:0] rng_value;
    wire[31:0] n_rng_value;
    wire       n_lsb = rng_value[31] ~^ 
                       rng_value[21] ~^ 
                       rng_value[ 1] ~^
                       rng_value[ 0]  ;

    assign n_rng_value = is_rseed ? rng_rs1
                                  : rng_value << 1 | n_lsb;

    always @(posedge g_clk) if(!g_resetn) begin
        rng_value <= RNG_RESET_VALUE;
    end else begin
        rng_value <= n_rng_value;
    end

    assign rng_output = rng_value;

end else begin

    assign rng_output = 0;

end endgenerate

endmodule