data/full_repos/permissive/206169433/single cycle/test.v
 line:44: before: "begin"
1: b'%Error: Cannot find file containing module: cycle,data/full_repos/permissive/206169433\n        ... Looked in:\n             data/full_repos/permissive/206169433/single/cycle,data/full_repos/permissive/206169433\n             data/full_repos/permissive/206169433/single/cycle,data/full_repos/permissive/206169433.v\n             data/full_repos/permissive/206169433/single/cycle,data/full_repos/permissive/206169433.sv\n             cycle,data/full_repos/permissive/206169433\n             cycle,data/full_repos/permissive/206169433.v\n             cycle,data/full_repos/permissive/206169433.sv\n             obj_dir/cycle,data/full_repos/permissive/206169433\n             obj_dir/cycle,data/full_repos/permissive/206169433.v\n             obj_dir/cycle,data/full_repos/permissive/206169433.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/206169433/single\n%Error: Cannot find file containing module: cycle/test.v\n%Error: Exiting due to 3 error(s)\n'
module test;

	integer i = -1;


	reg clk;


	single_cycle uut (clk	);

	
	initial begin

            clk = 0;
            $dumpvars(1, uut);
            $display("Texual result of single cycle:");
            $display("==========================================================");
            #500;
            $stop;
        end
	
	always #10 begin
	    
        $display("Time: %d, CLK = %d, PC = 0x%H", i, clk, uut.pc_out);     
		$display("[$s0] = 0x%H, [$s1] = 0x%H, [$s2] = 0x%H", uut.Register.regs[16], uut.Register.regs[17], uut.Register.regs[18]);
        $display("[$s3] = 0x%H, [$s4] = 0x%H, [$s5] = 0x%H", uut.Register.regs[19], uut.Register.regs[20], uut.Register.regs[21]);
        $display("[$s6] = 0x%H, [$s7] = 0x%H, [$t0] = 0x%H", uut.Register.regs[22], uut.Register.regs[23], uut.Register.regs[8]);
        $display("[$t1] = 0x%H, [$t2] = 0x%H, [$t3] = 0x%H", uut.Register.regs[9], uut.Register.regs[10], uut.Register.regs[11]);
	    $display("----------------------------------------------------------");
       clk = ~clk;
       if (clk) i = i + 1;
    end
endmodule
module test;


	integer i = -1;


	reg clk;


	single_cycle uut (clk	);

	
	initial begin

            clk = 0;
            $dumpvars(1, uut);
            $display("Texual result of single cycle:");
            $display("==========================================================");
            #500;
            $stop;
        end
	
	always #10 begin
	    
        $display("Time: %d, CLK = %d, PC = 0x%H", i, clk, uut.pc_out);     
		$display("[$s0] = 0x%H, [$s1] = 0x%H, [$s2] = 0x%H", uut.Register.regs[16], uut.Register.regs[17], uut.Register.regs[18]);
        $display("[$s3] = 0x%H, [$s4] = 0x%H, [$s5] = 0x%H", uut.Register.regs[19], uut.Register.regs[20], uut.Register.regs[21]);
        $display("[$s6] = 0x%H, [$s7] = 0x%H, [$t0] = 0x%H", uut.Register.regs[22], uut.Register.regs[23], uut.Register.regs[8]);
        $display("[$t1] = 0x%H, [$t2] = 0x%H, [$t3] = 0x%H", uut.Register.regs[9], uut.Register.regs[10], uut.Register.regs[11]);
	    $display("----------------------------------------------------------");
       clk = ~clk;
       if (clk) i = i + 1;
    end
endmodule