data/full_repos/permissive/161314640/TP2-Urna-Eletronica-CCF251/urnaeletronica.v
data/verilator_xmls/7c026067-df5a-453b-a05b-170beebf9472.xml
module urnaeletronica(control,digit,tisabella,tclaudio,tfilipe,tguilherme,tnulo,clock,valid,finish,votestatus);
	input wire clock,valid,finish;
	input wire [3:0]digit;
	input wire [2:0]control;
	output reg [7:0]tisabella = 8'b00000000;
	output reg [7:0]tclaudio = 8'b00000000;
	output reg [7:0]tfilipe = 8'b00000000;
	output reg [7:0]tguilherme = 8'b00000000;
	output reg [7:0]tnulo = 8'b00000000;
	output reg votestatus;
	reg [3:0]estado = 4'b0000;
	reg [7:0]isabella = 8'b00000000;
	reg [7:0]claudio = 8'b00000000;
	reg [7:0]filipe = 8'b00000000;
	reg [7:0]guilherme = 8'b00000000;
	reg [7:0]nulo = 8'b00000000;



	always @(posedge clock) begin

	if(finish) begin
		case (control)
			3'b000: begin
				isabella <= 8'b00000000;
				claudio <= 8'b00000000;
				filipe <= 8'b00000000;
				guilherme <= 8'b00000000;
				nulo <= 8'b00000000;
				tisabella <= 8'b00000000;
				tclaudio <= 8'b00000000;
				tfilipe <= 8'b00000000;
				tguilherme <= 8'b00000000;
				tnulo <= 8'b00000000;
			end
			3'b001: begin
				tisabella <= isabella;
			end
			3'b010: begin
				tclaudio <= claudio;
			end
			3'b011: begin
				tfilipe <= filipe;
			end
			3'b100: begin
				tguilherme <= guilherme;
			end
			3'b101: begin
				tnulo <= nulo;
			end
		endcase
	end

		else if(~finish) begin
			case(estado)

				4'b0000: begin
					if((digit == 4'b0011) & (valid)) begin
						estado <= 4'b0001;
					end
					else begin
						estado <= 4'b0101;
					end
				end



				4'b0001: begin
					if((digit == 4'b0100) & (valid)) begin
						estado <= 4'b0010;
					end
					else if((digit == 4'b0101) & (valid)) begin
						estado <= 4'b0010;
					end
					else begin
						estado <= 4'b0110;
					end
				end


				4'b0010: begin
					if((digit == 4'b1001) & (valid)) begin
						estado <= 4'b1000;
					end
					else if((digit == 4'b0111) & (valid)) begin
						estado <= 4'b0011;
					end
					else if((digit == 4'b0000) & (valid)) begin
						estado <= 4'b0011;
					end
					else begin
						estado <= 4'b0100;
					end
				end



				4'b1000: begin
					if((digit == 4'b0010) & (valid)) begin
						claudio <= claudio + 8'b00000001;
						votestatus <= 1;
						estado <= 4'b0000;
					end
					else begin
						nulo <= nulo + 8'b00000001;
						votestatus <= 0;
						estado <= 4'b0000;
					end
				end


				4'b0011: begin
					if((digit == 4'b1001) & (valid)) begin
						guilherme <= guilherme + 8'b00000001;
						votestatus <= 1;
						estado <= 4'b0000;
					end
					else if((digit == 4'b0100) & (valid)) begin
						isabella <= isabella + 8'b00000001;
						votestatus <= 1;
						estado <= 4'b0000;
					end
					else if((digit == 4'b0010) & (valid)) begin
						filipe <= filipe + 8'b00000001;
						votestatus <= 1;
						estado <= 4'b0000;
					end
					else begin
						nulo <= nulo + 8'b00000001;
						votestatus <= 0;
						estado <= 4'b0000;
					end
				end



				4'b0101: begin
					if(valid) begin
						estado <= 4'b0110;
					end
				end



				4'b0110: begin
					if(valid) begin
						estado <= 4'b0100;
					end
				end



				4'b0100: begin
					if(valid) begin
						nulo <= nulo + 8'b00000001;
						votestatus <= 0;
						estado <= 4'b0000;
					end


				end
			endcase
		end

	end
endmodule
module urnaeletronica(control,digit,tisabella,tclaudio,tfilipe,tguilherme,tnulo,clock,valid,finish,votestatus);

	input wire clock,valid,finish;
	input wire [3:0]digit;
	input wire [2:0]control;
	output reg [7:0]tisabella = 8'b00000000;
	output reg [7:0]tclaudio = 8'b00000000;
	output reg [7:0]tfilipe = 8'b00000000;
	output reg [7:0]tguilherme = 8'b00000000;
	output reg [7:0]tnulo = 8'b00000000;
	output reg votestatus;
	reg [3:0]estado = 4'b0000;
	reg [7:0]isabella = 8'b00000000;
	reg [7:0]claudio = 8'b00000000;
	reg [7:0]filipe = 8'b00000000;
	reg [7:0]guilherme = 8'b00000000;
	reg [7:0]nulo = 8'b00000000;



	always @(posedge clock) begin

	if(finish) begin
		case (control)
			3'b000: begin
				isabella <= 8'b00000000;
				claudio <= 8'b00000000;
				filipe <= 8'b00000000;
				guilherme <= 8'b00000000;
				nulo <= 8'b00000000;
				tisabella <= 8'b00000000;
				tclaudio <= 8'b00000000;
				tfilipe <= 8'b00000000;
				tguilherme <= 8'b00000000;
				tnulo <= 8'b00000000;
			end
			3'b001: begin
				tisabella <= isabella;
			end
			3'b010: begin
				tclaudio <= claudio;
			end
			3'b011: begin
				tfilipe <= filipe;
			end
			3'b100: begin
				tguilherme <= guilherme;
			end
			3'b101: begin
				tnulo <= nulo;
			end
		endcase
	end

		else if(~finish) begin
			case(estado)

				4'b0000: begin
					if((digit == 4'b0011) & (valid)) begin
						estado <= 4'b0001;
					end
					else begin
						estado <= 4'b0101;
					end
				end



				4'b0001: begin
					if((digit == 4'b0100) & (valid)) begin
						estado <= 4'b0010;
					end
					else if((digit == 4'b0101) & (valid)) begin
						estado <= 4'b0010;
					end
					else begin
						estado <= 4'b0110;
					end
				end


				4'b0010: begin
					if((digit == 4'b1001) & (valid)) begin
						estado <= 4'b1000;
					end
					else if((digit == 4'b0111) & (valid)) begin
						estado <= 4'b0011;
					end
					else if((digit == 4'b0000) & (valid)) begin
						estado <= 4'b0011;
					end
					else begin
						estado <= 4'b0100;
					end
				end



				4'b1000: begin
					if((digit == 4'b0010) & (valid)) begin
						claudio <= claudio + 8'b00000001;
						votestatus <= 1;
						estado <= 4'b0000;
					end
					else begin
						nulo <= nulo + 8'b00000001;
						votestatus <= 0;
						estado <= 4'b0000;
					end
				end


				4'b0011: begin
					if((digit == 4'b1001) & (valid)) begin
						guilherme <= guilherme + 8'b00000001;
						votestatus <= 1;
						estado <= 4'b0000;
					end
					else if((digit == 4'b0100) & (valid)) begin
						isabella <= isabella + 8'b00000001;
						votestatus <= 1;
						estado <= 4'b0000;
					end
					else if((digit == 4'b0010) & (valid)) begin
						filipe <= filipe + 8'b00000001;
						votestatus <= 1;
						estado <= 4'b0000;
					end
					else begin
						nulo <= nulo + 8'b00000001;
						votestatus <= 0;
						estado <= 4'b0000;
					end
				end



				4'b0101: begin
					if(valid) begin
						estado <= 4'b0110;
					end
				end



				4'b0110: begin
					if(valid) begin
						estado <= 4'b0100;
					end
				end



				4'b0100: begin
					if(valid) begin
						nulo <= nulo + 8'b00000001;
						votestatus <= 0;
						estado <= 4'b0000;
					end


				end
			endcase
		end

	end
endmodule