data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/uart_top.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/uart_top.v:3: Cannot find include file: uart_defines.v\n`include "uart_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes,data/full_repos/permissive/19905110/uart_defines.v\n             data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes,data/full_repos/permissive/19905110/uart_defines.v.v\n             data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes,data/full_repos/permissive/19905110/uart_defines.v.sv\n             uart_defines.v\n             uart_defines.v.v\n             uart_defines.v.sv\n             obj_dir/uart_defines.v\n             obj_dir/uart_defines.v.v\n             obj_dir/uart_defines.v.sv\n%Error: data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/uart_top.v:23: Define or directive not defined: \'`UART_DATA_WIDTH\'\nparameter         uart_data_width = `UART_DATA_WIDTH;\n                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/uart_top.v:23: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter         uart_data_width = `UART_DATA_WIDTH;\n                                                    ^\n%Error: data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/uart_top.v:24: Define or directive not defined: \'`UART_ADDR_WIDTH\'\nparameter         uart_addr_width = `UART_ADDR_WIDTH;\n                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/prj/src/blackboxes/uart_top.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter         uart_addr_width = `UART_ADDR_WIDTH;\n                                                    ^\n%Error: Exiting due to 5 error(s)\n'
module uart_top	(
	wb_clk_i, 
	

	wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
	int_o,



	stx_pad_o, srx_pad_i,


	rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
`ifdef UART_HAS_BAUDRATE_OUTPUT
	, baud_o
`endif
	);

parameter 							 uart_data_width = `UART_DATA_WIDTH;
parameter 							 uart_addr_width = `UART_ADDR_WIDTH;

input 								 wb_clk_i;


input 								 wb_rst_i;
input [uart_addr_width-1:0] 	 wb_adr_i;
input [uart_data_width-1:0] 	 wb_dat_i;
output [uart_data_width-1:0] 	 wb_dat_o;
input 								 wb_we_i;
input 								 wb_stb_i;
input 								 wb_cyc_i;
input [3:0]							 wb_sel_i;
output 								 wb_ack_o;
output 								 int_o;


input 								 srx_pad_i;
output 								 stx_pad_o;
output 								 rts_pad_o;
input 								 cts_pad_i;
output 								 dtr_pad_o;
input 								 dsr_pad_i;
input 								 ri_pad_i;
input 								 dcd_pad_i;


`ifdef UART_HAS_BAUDRATE_OUTPUT
output	baud_o;
`endif


endmodule
module uart_top	(
	wb_clk_i, 
	

	wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
	int_o,



	stx_pad_o, srx_pad_i,


	rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
`ifdef UART_HAS_BAUDRATE_OUTPUT
	, baud_o
`endif
	);


parameter 							 uart_data_width = `UART_DATA_WIDTH;
parameter 							 uart_addr_width = `UART_ADDR_WIDTH;

input 								 wb_clk_i;


input 								 wb_rst_i;
input [uart_addr_width-1:0] 	 wb_adr_i;
input [uart_data_width-1:0] 	 wb_dat_i;
output [uart_data_width-1:0] 	 wb_dat_o;
input 								 wb_we_i;
input 								 wb_stb_i;
input 								 wb_cyc_i;
input [3:0]							 wb_sel_i;
output 								 wb_ack_o;
output 								 int_o;


input 								 srx_pad_i;
output 								 stx_pad_o;
output 								 rts_pad_o;
input 								 cts_pad_i;
output 								 dtr_pad_o;
input 								 dsr_pad_i;
input 								 ri_pad_i;
input 								 dcd_pad_i;


`ifdef UART_HAS_BAUDRATE_OUTPUT
output	baud_o;
`endif


endmodule