data/full_repos/permissive/103842408/rtl/main/rvm_adder.v
1: b'%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:18: Cannot find include file: rvm_constants.v\n`include "rvm_constants.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v\n             data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.v\n             data/full_repos/permissive/103842408/rtl/main,data/full_repos/permissive/103842408/rvm_constants.v.sv\n             rvm_constants.v\n             rvm_constants.v.v\n             rvm_constants.v.sv\n             obj_dir/rvm_constants.v\n             obj_dir/rvm_constants.v.v\n             obj_dir/rvm_constants.v.sv\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:34: Define or directive not defined: \'`RVM_ARITH_NOP\'\nwire [31:0] i_lhs = lhs & {32{op != `RVM_ARITH_NOP}};\n                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:34: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\nwire [31:0] i_lhs = lhs & {32{op != `RVM_ARITH_NOP}};\n                                                  ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:35: Define or directive not defined: \'`RVM_ARITH_NOP\'\nwire [31:0] i_rhs = rhs & {32{op != `RVM_ARITH_NOP}};\n                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:35: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\nwire [31:0] i_rhs = rhs & {32{op != `RVM_ARITH_NOP}};\n                                                  ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:37: Define or directive not defined: \'`RVM_ARITH_NOP\'\nassign valid = op != `RVM_ARITH_NOP;\n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:37: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign valid = op != `RVM_ARITH_NOP;\n                                   ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:39: Define or directive not defined: \'`RVM_ARITH_GE\'\nwire result_ge = op == `RVM_ARITH_GE  && $signed(lhs) >= $signed(rhs);\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:39: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\nwire result_ge = op == `RVM_ARITH_GE  && $signed(lhs) >= $signed(rhs);\n                                      ^~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:40: Define or directive not defined: \'`RVM_ARITH_GEU\'\nwire result_geu= op == `RVM_ARITH_GEU && $unsigned(lhs >= rhs);\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:40: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\nwire result_geu= op == `RVM_ARITH_GEU && $unsigned(lhs >= rhs);\n                                      ^~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:41: Define or directive not defined: \'`RVM_ARITH_LT\'\nwire result_lt = op == `RVM_ARITH_LT  && $signed(lhs) <  $signed(rhs);\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:41: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\nwire result_lt = op == `RVM_ARITH_LT  && $signed(lhs) <  $signed(rhs);\n                                      ^~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:42: Define or directive not defined: \'`RVM_ARITH_LTU\'\nwire result_ltu= op == `RVM_ARITH_LTU && $unsigned(lhs <  rhs);\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:42: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\nwire result_ltu= op == `RVM_ARITH_LTU && $unsigned(lhs <  rhs);\n                                      ^~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:46: Define or directive not defined: \'`RVM_ARITH_ADD\'\nassign {overflow,result} = ({33{op == `RVM_ARITH_ADD}} & (i_lhs + i_rhs)) |\n                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:46: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\nassign {overflow,result} = ({33{op == `RVM_ARITH_ADD}} & (i_lhs + i_rhs)) |\n                                                    ^\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:47: Define or directive not defined: \'`RVM_ARITH_SUB\'\n                           ({33{op == `RVM_ARITH_SUB}} & (i_lhs - i_rhs)) |\n                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:48: Define or directive not defined: \'`RVM_ARITH_GE\'\n                           ({33{op == `RVM_ARITH_GE }} & (result_ge    )) |\n                                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:49: Define or directive not defined: \'`RVM_ARITH_GEU\'\n                           ({33{op == `RVM_ARITH_GEU}} & (result_geu   )) |\n                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:50: Define or directive not defined: \'`RVM_ARITH_LT\'\n                           ({33{op == `RVM_ARITH_LT }} & (result_lt    )) |\n                                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103842408/rtl/main/rvm_adder.v:51: Define or directive not defined: \'`RVM_ARITH_LTU\'\n                           ({33{op == `RVM_ARITH_LTU}} & (result_ltu   )) ;\n                                      ^~~~~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n'
module rvm_adder(

input  wire [31:0] lhs,
input  wire [31:0] rhs,

input  wire [2:0]  op,

output wire        valid,
output wire [31:0] result,
output wire        overflow
);



wire [31:0] i_lhs = lhs & {32{op != `RVM_ARITH_NOP}};
wire [31:0] i_rhs = rhs & {32{op != `RVM_ARITH_NOP}};

assign valid = op != `RVM_ARITH_NOP;

wire result_ge = op == `RVM_ARITH_GE  && $signed(lhs) >= $signed(rhs);
wire result_geu= op == `RVM_ARITH_GEU && $unsigned(lhs >= rhs);
wire result_lt = op == `RVM_ARITH_LT  && $signed(lhs) <  $signed(rhs);
wire result_ltu= op == `RVM_ARITH_LTU && $unsigned(lhs <  rhs);



assign {overflow,result} = ({33{op == `RVM_ARITH_ADD}} & (i_lhs + i_rhs)) |
                           ({33{op == `RVM_ARITH_SUB}} & (i_lhs - i_rhs)) |
                           ({33{op == `RVM_ARITH_GE }} & (result_ge    )) |
                           ({33{op == `RVM_ARITH_GEU}} & (result_geu   )) |
                           ({33{op == `RVM_ARITH_LT }} & (result_lt    )) |
                           ({33{op == `RVM_ARITH_LTU}} & (result_ltu   )) ;


endmodule
module rvm_adder(

input  wire [31:0] lhs,
input  wire [31:0] rhs,

input  wire [2:0]  op,

output wire        valid,
output wire [31:0] result,
output wire        overflow
);




wire [31:0] i_lhs = lhs & {32{op != `RVM_ARITH_NOP}};
wire [31:0] i_rhs = rhs & {32{op != `RVM_ARITH_NOP}};

assign valid = op != `RVM_ARITH_NOP;

wire result_ge = op == `RVM_ARITH_GE  && $signed(lhs) >= $signed(rhs);
wire result_geu= op == `RVM_ARITH_GEU && $unsigned(lhs >= rhs);
wire result_lt = op == `RVM_ARITH_LT  && $signed(lhs) <  $signed(rhs);
wire result_ltu= op == `RVM_ARITH_LTU && $unsigned(lhs <  rhs);



assign {overflow,result} = ({33{op == `RVM_ARITH_ADD}} & (i_lhs + i_rhs)) |
                           ({33{op == `RVM_ARITH_SUB}} & (i_lhs - i_rhs)) |
                           ({33{op == `RVM_ARITH_GE }} & (result_ge    )) |
                           ({33{op == `RVM_ARITH_GEU}} & (result_geu   )) |
                           ({33{op == `RVM_ARITH_LT }} & (result_lt    )) |
                           ({33{op == `RVM_ARITH_LTU}} & (result_ltu   )) ;


endmodule