data/full_repos/permissive/166115772/old_attempt/verilog/instruction_reg.v
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1: b'%Warning-LITENDIAN: data/full_repos/permissive/166115772/old_attempt/verilog/instruction_reg.v:2: Little bit endian vector: MSB < LSB of bit range: 0:25\n    input [0:25] dataIn,\n          ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/old_attempt/verilog/instruction_reg.v:4: Little bit endian vector: MSB < LSB of bit range: 0:25\n    output [0:25] dataOut\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/old_attempt/verilog/instruction_reg.v:6: Little bit endian vector: MSB < LSB of bit range: 0:25\n    reg [0:25] register;\n        ^\n%Error: Exiting due to 3 warning(s)\n'
module instructionReg (
    input [0:25] dataIn,
    input load,
    output [0:25] dataOut
);
    reg [0:25] register;
    assign dataOut = register;

    always @(posedge load)
        register <=dataIn;
endmodule
module instructionReg (
    input [0:25] dataIn,
    input load,
    output [0:25] dataOut
);

    reg [0:25] register;
    assign dataOut = register;

    always @(posedge load)
        register <=dataIn;
endmodule