data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v
 line:23: before: "="
1: b'%Error: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:18: Cannot find file containing module: \'counter_3\'\n  counter_3 slowclock (\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/counter_3\n             data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/counter_3.v\n             data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/counter_3.sv\n             counter_3\n             counter_3.v\n             counter_3.sv\n             obj_dir/counter_3\n             obj_dir/counter_3.v\n             obj_dir/counter_3.sv\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:23: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                              : ... In instance led_matrix_2\n  reg [15:0] M_cSignal_d, M_cSignal_q = 1\'h0;\n                                        ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:24: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                              : ... In instance led_matrix_2\n  reg [15:0] M_aSignal_d, M_aSignal_q = 1\'h0;\n                                        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:35: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                              : ... In instance led_matrix_2\n    case (M_slowclock_value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:35: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                                                                              : ... In instance led_matrix_2\n    case (M_slowclock_value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:35: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                                                                                              : ... In instance led_matrix_2\n    case (M_slowclock_value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:35: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                                                                                              : ... In instance led_matrix_2\n    case (M_slowclock_value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:35: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                                                                                              : ... In instance led_matrix_2\n    case (M_slowclock_value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:35: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                                                                                              : ... In instance led_matrix_2\n    case (M_slowclock_value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:35: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                                                                                              : ... In instance led_matrix_2\n    case (M_slowclock_value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:35: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                                                                                              : ... In instance led_matrix_2\n    case (M_slowclock_value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:107: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                               : ... In instance led_matrix_2\n      M_cSignal_q <= 1\'h0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/led_matrix_2.v:113: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                               : ... In instance led_matrix_2\n      M_aSignal_q <= 1\'h0;\n                  ^~\n%Error: Exiting due to 1 error(s), 12 warning(s)\n'
module led_matrix_2 (
    input clk,
    input rst,
    input [255:0] pattern,
    output reg [15:0] a,
    output reg [15:0] c
  );
  
  
  
  wire [4-1:0] M_slowclock_value;
  counter_3 slowclock (
    .clk(clk),
    .rst(rst),
    .value(M_slowclock_value)
  );
  reg [15:0] M_cSignal_d, M_cSignal_q = 1'h0;
  reg [15:0] M_aSignal_d, M_aSignal_q = 1'h0;
  
  always @* begin
    M_cSignal_d = M_cSignal_q;
    M_aSignal_d = M_aSignal_q;
    
    a = pattern[(M_slowclock_value)*16+15-:16];
    c = 16'hfffe;
    M_aSignal_d = 16'h0000;
    M_cSignal_d = 16'hfffe;
    
    case (M_slowclock_value)
      1'h0: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfffe;
      end
      1'h1: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfffd;
      end
      2'h2: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfffb;
      end
      2'h3: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfff7;
      end
      3'h4: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hffef;
      end
      3'h5: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hffdf;
      end
      3'h6: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hffbf;
      end
      3'h7: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hff7f;
      end
      4'h8: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfeff;
      end
      4'h9: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfdff;
      end
      4'ha: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfbff;
      end
      4'hb: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hf7ff;
      end
      4'hc: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hefff;
      end
      4'hd: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hdfff;
      end
      4'he: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hbfff;
      end
      4'hf: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'h7fff;
      end
    endcase
    a = M_aSignal_q;
    c = M_cSignal_q;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_cSignal_q <= 1'h0;
    end else begin
      M_cSignal_q <= M_cSignal_d;
    end
    
    if (rst == 1'b1) begin
      M_aSignal_q <= 1'h0;
    end else begin
      M_aSignal_q <= M_aSignal_d;
    end
  end
  
endmodule
module led_matrix_2 (
    input clk,
    input rst,
    input [255:0] pattern,
    output reg [15:0] a,
    output reg [15:0] c
  );

  
  
  
  wire [4-1:0] M_slowclock_value;
  counter_3 slowclock (
    .clk(clk),
    .rst(rst),
    .value(M_slowclock_value)
  );
  reg [15:0] M_cSignal_d, M_cSignal_q = 1'h0;
  reg [15:0] M_aSignal_d, M_aSignal_q = 1'h0;
  
  always @* begin
    M_cSignal_d = M_cSignal_q;
    M_aSignal_d = M_aSignal_q;
    
    a = pattern[(M_slowclock_value)*16+15-:16];
    c = 16'hfffe;
    M_aSignal_d = 16'h0000;
    M_cSignal_d = 16'hfffe;
    
    case (M_slowclock_value)
      1'h0: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfffe;
      end
      1'h1: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfffd;
      end
      2'h2: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfffb;
      end
      2'h3: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfff7;
      end
      3'h4: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hffef;
      end
      3'h5: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hffdf;
      end
      3'h6: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hffbf;
      end
      3'h7: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hff7f;
      end
      4'h8: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfeff;
      end
      4'h9: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfdff;
      end
      4'ha: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hfbff;
      end
      4'hb: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hf7ff;
      end
      4'hc: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hefff;
      end
      4'hd: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hdfff;
      end
      4'he: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'hbfff;
      end
      4'hf: begin
        M_aSignal_d = pattern[(M_slowclock_value)*16+15-:16];
        M_cSignal_d = 16'h7fff;
      end
    endcase
    a = M_aSignal_q;
    c = M_cSignal_q;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_cSignal_q <= 1'h0;
    end else begin
      M_cSignal_q <= M_cSignal_d;
    end
    
    if (rst == 1'b1) begin
      M_aSignal_q <= 1'h0;
    end else begin
      M_aSignal_q <= M_aSignal_d;
    end
  end
  
endmodule