data/full_repos/permissive/190755935/src/comms/rtl/uart_in.v
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1: b'%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_in.v:54: Cannot find include file: ../../pipe/rtl/pipe_defs.v\n`include "../../pipe/rtl/pipe_defs.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/190755935/src/comms/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v\n             data/full_repos/permissive/190755935/src/comms/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v.v\n             data/full_repos/permissive/190755935/src/comms/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v.sv\n             ../../pipe/rtl/pipe_defs.v\n             ../../pipe/rtl/pipe_defs.v.v\n             ../../pipe/rtl/pipe_defs.v.sv\n             obj_dir/../../pipe/rtl/pipe_defs.v\n             obj_dir/../../pipe/rtl/pipe_defs.v.v\n             obj_dir/../../pipe/rtl/pipe_defs.v.sv\n%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_in.v:56: Define or directive not defined: \'`PS_DATA\'\nmodule uart_in  #( parameter PipeSpec = `PS_DATA( 8 ), parameter ClockFrequency = 12000000, parameter BaudRate = 9600 ) (\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_in.v:60: Define or directive not defined: \'`P_m\'\n        inout [`P_m(PipeSpec):0] pipe_out,\n               ^~~~\n%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_in.v:65: Define or directive not defined: \'`P_Data_w\'\n    wire [`P_Data_w(PipeSpec)-1:0] out_data;\n          ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module uart_in_np #( parameter ClockFrequency = 12000000, parameter BaudRate = 9600,  parameter Oversampling = 8 )(
        input clock,
        input reset,

        output reg [7:0] in_data = 0,
        output reg       in_valid = 0,
        input            in_ready,




        output uart_idle,
        output reg uart_endofpacket = 0,

        input uart_rx
    );

    reg [7:0] in_data_build;




    generate
        if( ClockFrequency < BaudRate * Oversampling ) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current BaudRate rate and oversampling");
        if( Oversampling < 8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
    endgenerate


    reg [3:0] uart_state = 0;

    `ifdef SIMULATION
        wire uart_bit = uart_rx;
        wire sampleNow = 1'b1;
    `else
        wire OversamplingTick;
        uart_in_baudrate_gen #(ClockFrequency, BaudRate, Oversampling) tickgen(.clock(clock), .enable(1'b1), .tick(OversamplingTick));


        reg [1:0] uart_sync = 2'b11;
        always @(posedge clock)
            if(OversamplingTick)
                uart_sync <= {uart_sync[0], uart_rx};


        reg [1:0] Filter_cnt = 2'b11;
        reg uart_bit = 1'b1;

        always @(posedge clock)
            if(OversamplingTick) begin
                if(uart_sync[1]==1'b1 && Filter_cnt!=2'b11)
                    Filter_cnt <= Filter_cnt + 1'd1;
                else
                    if(uart_sync[1]==1'b0 && Filter_cnt!=2'b00)
                        Filter_cnt <= Filter_cnt - 1'd1;

                if(Filter_cnt==2'b11)
                    uart_bit <= 1'b1;
                else
                    if(Filter_cnt==2'b00)
                        uart_bit <= 1'b0;
            end


        function integer log2(input integer v); begin
            log2=0;
            while(v>>log2) log2=log2+1;
        end endfunction

        localparam l2o = log2(Oversampling);

        reg [l2o-2:0] OversamplingCnt = 0;

        always @(posedge clock)
            if(OversamplingTick)
                OversamplingCnt <= (uart_state==0) ? 1'd0 : OversamplingCnt + 1'd1;

        wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
    `endif


    always @(posedge clock)
        if ( reset ) begin
            uart_state <= 0;
        end else begin
            case(uart_state)
                4'b0000: if(~uart_bit) uart_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif;
                4'b0001: if(sampleNow) uart_state <= 4'b1000;
                4'b1000: if(sampleNow) uart_state <= 4'b1001;
                4'b1001: if(sampleNow) uart_state <= 4'b1010;
                4'b1010: if(sampleNow) uart_state <= 4'b1011;
                4'b1011: if(sampleNow) uart_state <= 4'b1100;
                4'b1100: if(sampleNow) uart_state <= 4'b1101;
                4'b1101: if(sampleNow) uart_state <= 4'b1110;
                4'b1110: if(sampleNow) uart_state <= 4'b1111;
                4'b1111: if(sampleNow) uart_state <= 4'b0010;
                4'b0010: if(sampleNow) uart_state <= 4'b0000;
                default: uart_state <= 4'b0000;
            endcase
        end

    always @(posedge clock)
        if(sampleNow && uart_state[3])
            in_data_build <= {uart_bit, in_data_build[7:1]};


    always @(posedge clock) begin
        if ( sampleNow && uart_state==4'b0010 && uart_bit ) begin
            in_valid <= 1;
            in_data <= in_data_build;
        end else begin
            if ( in_ready ) begin
                in_valid <= 0;
                in_data <= 0;
            end
        end



    end

    `ifdef SIMULATION
        assign uart_idle = 0;
    `else
        reg [l2o+1:0] GapCnt = 0;
        always @(posedge clock)
            if (uart_state!=0)
                GapCnt<=0;
            else
                if(OversamplingTick & ~GapCnt[log2(Oversampling)+1])
                    GapCnt <= GapCnt + 1'h1;
        assign uart_idle = GapCnt[l2o+1];
        always @(posedge clock)
            uart_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
    `endif

endmodule
module uart_in_np #( parameter ClockFrequency = 12000000, parameter BaudRate = 9600,  parameter Oversampling = 8 )(
        input clock,
        input reset,

        output reg [7:0] in_data = 0,
        output reg       in_valid = 0,
        input            in_ready,




        output uart_idle,
        output reg uart_endofpacket = 0,

        input uart_rx
    );


    reg [7:0] in_data_build;




    generate
        if( ClockFrequency < BaudRate * Oversampling ) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current BaudRate rate and oversampling");
        if( Oversampling < 8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
    endgenerate


    reg [3:0] uart_state = 0;

    `ifdef SIMULATION
        wire uart_bit = uart_rx;
        wire sampleNow = 1'b1;
    `else
        wire OversamplingTick;
        uart_in_baudrate_gen #(ClockFrequency, BaudRate, Oversampling) tickgen(.clock(clock), .enable(1'b1), .tick(OversamplingTick));


        reg [1:0] uart_sync = 2'b11;
        always @(posedge clock)
            if(OversamplingTick)
                uart_sync <= {uart_sync[0], uart_rx};


        reg [1:0] Filter_cnt = 2'b11;
        reg uart_bit = 1'b1;

        always @(posedge clock)
            if(OversamplingTick) begin
                if(uart_sync[1]==1'b1 && Filter_cnt!=2'b11)
                    Filter_cnt <= Filter_cnt + 1'd1;
                else
                    if(uart_sync[1]==1'b0 && Filter_cnt!=2'b00)
                        Filter_cnt <= Filter_cnt - 1'd1;

                if(Filter_cnt==2'b11)
                    uart_bit <= 1'b1;
                else
                    if(Filter_cnt==2'b00)
                        uart_bit <= 1'b0;
            end


        function integer log2(input integer v); begin
            log2=0;
            while(v>>log2) log2=log2+1;
        end endfunction

        localparam l2o = log2(Oversampling);

        reg [l2o-2:0] OversamplingCnt = 0;

        always @(posedge clock)
            if(OversamplingTick)
                OversamplingCnt <= (uart_state==0) ? 1'd0 : OversamplingCnt + 1'd1;

        wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
    `endif


    always @(posedge clock)
        if ( reset ) begin
            uart_state <= 0;
        end else begin
            case(uart_state)
                4'b0000: if(~uart_bit) uart_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif;
                4'b0001: if(sampleNow) uart_state <= 4'b1000;
                4'b1000: if(sampleNow) uart_state <= 4'b1001;
                4'b1001: if(sampleNow) uart_state <= 4'b1010;
                4'b1010: if(sampleNow) uart_state <= 4'b1011;
                4'b1011: if(sampleNow) uart_state <= 4'b1100;
                4'b1100: if(sampleNow) uart_state <= 4'b1101;
                4'b1101: if(sampleNow) uart_state <= 4'b1110;
                4'b1110: if(sampleNow) uart_state <= 4'b1111;
                4'b1111: if(sampleNow) uart_state <= 4'b0010;
                4'b0010: if(sampleNow) uart_state <= 4'b0000;
                default: uart_state <= 4'b0000;
            endcase
        end

    always @(posedge clock)
        if(sampleNow && uart_state[3])
            in_data_build <= {uart_bit, in_data_build[7:1]};


    always @(posedge clock) begin
        if ( sampleNow && uart_state==4'b0010 && uart_bit ) begin
            in_valid <= 1;
            in_data <= in_data_build;
        end else begin
            if ( in_ready ) begin
                in_valid <= 0;
                in_data <= 0;
            end
        end



    end

    `ifdef SIMULATION
        assign uart_idle = 0;
    `else
        reg [l2o+1:0] GapCnt = 0;
        always @(posedge clock)
            if (uart_state!=0)
                GapCnt<=0;
            else
                if(OversamplingTick & ~GapCnt[log2(Oversampling)+1])
                    GapCnt <= GapCnt + 1'h1;
        assign uart_idle = GapCnt[l2o+1];
        always @(posedge clock)
            uart_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
    `endif

endmodule