data/full_repos/permissive/143278/ivltests/pr355.v
 line:40: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr355.v:40: Unsupported: Ignoring delay on this delayed statement.\n      # (16*200+15) $display("PASSED");\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr355.v:45: Unsupported: Ignoring delay on this delayed statement.\n   always #100 clock = ~clock;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr355.v:53: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'a_in\' generates 4 bits.\n                                                                     : ... In instance testFunction\n   myint = a_in;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr355.v:73: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 4 bits.\n                                                                     : ... In instance testFunction\n   short_to_int = x;\n                ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testFunction();


   reg				clock;
   reg [`NRBITS-1:0]		a_in;
   integer			a_integer;
   integer			myint;
   reg [`NRBITS:0]		cycle_count;


   initial begin
	  clock = 1;
	  cycle_count = 0;
      # (16*200+15) $display("PASSED");
      $finish;
   end


   always #100 clock = ~clock;


   always @(negedge clock) begin
	  cycle_count = cycle_count + 1;


	  a_in = cycle_count[`NRBITS-1:0];
	  myint = a_in;
	  $display("a_in = %d, myint = %d", a_in, myint);


	  a_integer = short_to_int(a_in);


	  if (myint !== a_integer)
		 begin
			$display("ERROR ! %d !== %d", myint, a_integer);
			$stop;
		 end
   end



   function integer short_to_int;

	  input [`NRBITS-1:0]	x;
	  begin
		 short_to_int = x;
		 $display("\tshort_to_int(%b) = %b", x, short_to_int);
	  end
   endfunction
endmodule
module testFunction();



   reg				clock;
   reg [`NRBITS-1:0]		a_in;
   integer			a_integer;
   integer			myint;
   reg [`NRBITS:0]		cycle_count;


   initial begin
	  clock = 1;
	  cycle_count = 0;
      # (16*200+15) $display("PASSED");
      $finish;
   end


   always #100 clock = ~clock;


   always @(negedge clock) begin
	  cycle_count = cycle_count + 1;


	  a_in = cycle_count[`NRBITS-1:0];
	  myint = a_in;
	  $display("a_in = %d, myint = %d", a_in, myint);


	  a_integer = short_to_int(a_in);


	  if (myint !== a_integer)
		 begin
			$display("ERROR ! %d !== %d", myint, a_integer);
			$stop;
		 end
   end



   function integer short_to_int;

	  input [`NRBITS-1:0]	x;
	  begin
		 short_to_int = x;
		 $display("\tshort_to_int(%b) = %b", x, short_to_int);
	  end
   endfunction
endmodule