data/full_repos/permissive/157490365/stack4.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/157490365/stack4.v:26: Multiple top level modules\n                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                   : ... Top module \'mux2_3\'\nmodule mux2_3(input wire op, input wire [2:0] i0, i1, output wire [2:0] out);\n       ^~~~~~\n                                                                   : ... Top module \'stack\'\nmodule stack(input wire clk, reset, push, pop, input wire [15:0] value_in, output wire [15:0] value_out, output wire full, empty);\n       ^~~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:20: Cannot find file containing module: \'mux4\'\n    mux4 a0({i0[0],i1[0],i2[0],i3[0]},op2,op1,out[0]);\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/157490365,data/full_repos/permissive/157490365/mux4\n             data/full_repos/permissive/157490365,data/full_repos/permissive/157490365/mux4.v\n             data/full_repos/permissive/157490365,data/full_repos/permissive/157490365/mux4.sv\n             mux4\n             mux4.v\n             mux4.sv\n             obj_dir/mux4\n             obj_dir/mux4.v\n             obj_dir/mux4.sv\n%Error: data/full_repos/permissive/157490365/stack4.v:21: Cannot find file containing module: \'mux4\'\n    mux4 a1({i0[1],i1[1],i2[1],i3[1]},op2,op1,out[1]);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:22: Cannot find file containing module: \'mux4\'\n    mux4 a2({i0[2],i1[2],i2[2],i3[2]},op2,op1,out[2]);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:10: Cannot find file containing module: \'dfs\'\n    dfs dl(clk, set, d, q);\n    ^~~\n%Error: data/full_repos/permissive/157490365/stack4.v:6: Cannot find file containing module: \'dfr\'\n    dfr dl(clk, reset, d, q);\n    ^~~\n%Error: data/full_repos/permissive/157490365/stack4.v:2: Cannot find file containing module: \'dfrl\'\n    dfrl dl[2:0](clk, reset, load, d[2:0], q[2:0]);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:31: Cannot find file containing module: \'mux2\'\n    mux2 push_checker(push, 1\'b0, is_7_reg, write_push);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:34: Cannot find file containing module: \'mux2\'\n    mux2 pop_checker(pop, 1\'b0, is_0_reg, write_pop);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:36: Cannot find file containing module: \'or2\'\n    or2 top_reg_writer(write_pop, write_push, top_write_enable);\n    ^~~\n%Error: data/full_repos/permissive/157490365/stack4.v:39: Cannot find file containing module: \'fas3\'\n    fas3 a(top, 3\'b001, 1\'b0, inc, carry_a);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:40: Cannot find file containing module: \'fas3\'\n    fas3 b(top, 3\'b001, 1\'b1, dec, carry_s);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:43: Cannot find file containing module: \'reg_file\'\n    reg_file rf(clk, reset, write_push, top, 3\'bxxx, top, value_in, value_out, d_care);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:44: Cannot find file containing module: \'and3\'\n    and3 full_checker(inc_dec[2], inc_dec[1], inc_dec[0], is_7);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:45: Cannot find file containing module: \'and3\'\n    and3 empty_checker((!inc_dec[2]), (!inc_dec[1]), (!inc_dec[0]), is_0);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:14: Cannot find file containing module: \'mux2\'\n    mux2 a0(i0[0],i1[0],op,out[0]);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:15: Cannot find file containing module: \'mux2\'\n    mux2 a1(i0[1],i1[1],op,out[1]);\n    ^~~~\n%Error: data/full_repos/permissive/157490365/stack4.v:16: Cannot find file containing module: \'mux2\'\n    mux2 a2(i0[2],i1[2],op,out[2]);\n    ^~~~\n%Error: Exiting due to 17 error(s), 1 warning(s)\n'
module mux4_3(input wire op2, op1, input wire [2:0] i0, i1, i2, i3, output wire [2:0] out);
    mux4 a0({i0[0],i1[0],i2[0],i3[0]},op2,op1,out[0]);
    mux4 a1({i0[1],i1[1],i2[1],i3[1]},op2,op1,out[1]);
    mux4 a2({i0[2],i1[2],i2[2],i3[2]},op2,op1,out[2]);
endmodule
module mux4_3(input wire op2, op1, input wire [2:0] i0, i1, i2, i3, output wire [2:0] out);

    mux4 a0({i0[0],i1[0],i2[0],i3[0]},op2,op1,out[0]);
    mux4 a1({i0[1],i1[1],i2[1],i3[1]},op2,op1,out[1]);
    mux4 a2({i0[2],i1[2],i2[2],i3[2]},op2,op1,out[2]);
endmodule