data/full_repos/permissive/106029354/verilog_source/controller.v
1: b'%Error: data/full_repos/permissive/106029354/verilog_source/controller.v:7: Cannot find include file: params_proc.v\n`include "params_proc.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n             params_proc.v\n             params_proc.v.v\n             params_proc.v.sv\n             obj_dir/params_proc.v\n             obj_dir/params_proc.v.v\n             obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n'
module controller(
	opcode,
	ctrl
);


`include "params_proc.v"


input [OPCODE_WIDTH-1:0] opcode;

output reg [CTRL_WIDTH-1:0] ctrl;


always @(opcode) begin

	ctrl <= opcode[CTRL_WIDTH-1:0];
end

endmodule
module controller(
	opcode,
	ctrl
);



`include "params_proc.v"


input [OPCODE_WIDTH-1:0] opcode;

output reg [CTRL_WIDTH-1:0] ctrl;


always @(opcode) begin

	ctrl <= opcode[CTRL_WIDTH-1:0];
end

endmodule