data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v
 line:593: before: ","
1: b'%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:616: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:616: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:619: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_left\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n    out[63:32] <= out_left;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:623: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_right\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n    out[31:0] <= out_right;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:625: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:625: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:628: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_minus\n  assign  {temp[0], temp[31:1]} = out_left & key_left;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:593: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:593: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  in_left = in[63:32],   in_right = in[31:0];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:596: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_left\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n    out[63:32] <= out_left;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:600: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_right\' generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n    out[31:0] <= out_right;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:602: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:602: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  key_left = key[63:32], key_right = key[31:0];\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/181158585/simple_platform.srcs/sources_1/imports/platform/camellia.v:604: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                                                                   : ... In instance camellia.Camellia_randomize.Camellia_fl.Camellia_fl_plus\n  assign  {temp[0], temp[31:1]} = in_left & key_left;\n                                ^\n%Error: Exiting due to 14 warning(s)\n'
module Camellia_p_func(in, out);
  input [63:0] in;
  output reg [63:0] out;
  always @(in)
  begin
    out[63:56] <= in[63:56]             ^ in[47:40] ^ in[39:32]             ^ in[23:16] ^ in[15:8] ^ in[7:0];
    out[55:48] <= in[63:56] ^ in[55:48]             ^ in[39:32] ^ in[31:24]             ^ in[15:8] ^ in[7:0];
    out[47:40] <= in[63:56] ^ in[55:48] ^ in[47:40]             ^ in[31:24] ^ in[23:16]            ^ in[7:0];
    out[39:32] <=             in[55:48] ^ in[47:40] ^ in[39:32] ^ in[31:24] ^ in[23:16] ^ in[15:8]          ;
    out[31:24] <= in[63:56] ^ in[55:48]                                     ^ in[23:16] ^ in[15:8] ^ in[7:0];
    out[23:16] <=             in[55:48] ^ in[47:40]             ^ in[31:24]             ^ in[15:8] ^ in[7:0];
    out[15:8]  <=                         in[47:40] ^ in[39:32] ^ in[31:24] ^ in[23:16]            ^ in[7:0];
    out[7:0]   <= in[63:56]                         ^ in[39:32] ^ in[31:24] ^ in[23:16] ^ in[15:8]          ;
  end
endmodule
module Camellia_p_func(in, out);

  input [63:0] in;
  output reg [63:0] out;
  always @(in)
  begin
    out[63:56] <= in[63:56]             ^ in[47:40] ^ in[39:32]             ^ in[23:16] ^ in[15:8] ^ in[7:0];
    out[55:48] <= in[63:56] ^ in[55:48]             ^ in[39:32] ^ in[31:24]             ^ in[15:8] ^ in[7:0];
    out[47:40] <= in[63:56] ^ in[55:48] ^ in[47:40]             ^ in[31:24] ^ in[23:16]            ^ in[7:0];
    out[39:32] <=             in[55:48] ^ in[47:40] ^ in[39:32] ^ in[31:24] ^ in[23:16] ^ in[15:8]          ;
    out[31:24] <= in[63:56] ^ in[55:48]                                     ^ in[23:16] ^ in[15:8] ^ in[7:0];
    out[23:16] <=             in[55:48] ^ in[47:40]             ^ in[31:24]             ^ in[15:8] ^ in[7:0];
    out[15:8]  <=                         in[47:40] ^ in[39:32] ^ in[31:24] ^ in[23:16]            ^ in[7:0];
    out[7:0]   <= in[63:56]                         ^ in[39:32] ^ in[31:24] ^ in[23:16] ^ in[15:8]          ;
  end
endmodule