data/full_repos/permissive/130536678/Single-Cycle/ARM_CPU.v
 line:98: before: "INSTRUCTION"
1: b"%Error: data/full_repos/permissive/130536678/Single-Cycle/ARM_CPU.v:506: syntax error, unexpected $end, expecting ';'\n    Data[31] = 64   h00000000;\n                 ^\n%Error: Cannot continue\n"
module DataMemMux
(
  input [63:0] readData,
  input [63:0] aluOutput,
  input CONTROL_MEM2REG,
  output reg [63:0] out
);

  always @(readData, aluOutput, CONTROL_MEM2REG, out) begin
    if (CONTROL_MEM2REG == 0) begin
      out = aluOutput;
    end

    else begin
      out = readData;
    end
  end
endmodule
module DataMemMux
(
  input [63:0] readData,
  input [63:0] aluOutput,
  input CONTROL_MEM2REG,
  output reg [63:0] out
);


  always @(readData, aluOutput, CONTROL_MEM2REG, out) begin
    if (CONTROL_MEM2REG == 0) begin
      out = aluOutput;
    end

    else begin
      out = readData;
    end
  end
endmodule