data/full_repos/permissive/164033466/Source/cpu.v
data/verilator_xmls/090e14c5-af61-42e5-b428-2f75bd2f4f56.xml
module fsmCPU (ACK, clk, rst, outDATA,outSEND);	
	output reg outSEND;
  	output reg [31:0] outDATA;

	input ACK;
  	input clk, rst;
	

	reg currentState, nextState;


	always @ (posedge clk)
	begin
		if (rst == 1)
			currentState <= 0;
		else
			currentState <= nextState;
	end


	always @ (*)
	begin
		case ({currentState})
			0, 1:
				if (ACK == 0)
					nextState = 1;
				else
					nextState = 0;
		endcase
	end


	always @ (*)
	begin
		case ({currentState})
			0:
			begin
				outSEND = 0;
			end
			1:
			begin
				outSEND = 1;

				outDATA = $random;
			end
			
		endcase
	end

endmodule
module fsmCPU (ACK, clk, rst, outDATA,outSEND);
	
	output reg outSEND;
  	output reg [31:0] outDATA;

	input ACK;
  	input clk, rst;
	

	reg currentState, nextState;


	always @ (posedge clk)
	begin
		if (rst == 1)
			currentState <= 0;
		else
			currentState <= nextState;
	end


	always @ (*)
	begin
		case ({currentState})
			0, 1:
				if (ACK == 0)
					nextState = 1;
				else
					nextState = 0;
		endcase
	end


	always @ (*)
	begin
		case ({currentState})
			0:
			begin
				outSEND = 0;
			end
			1:
			begin
				outSEND = 1;

				outDATA = $random;
			end
			
		endcase
	end

endmodule