data/full_repos/permissive/194847941/demo/12_game/sources/rtl/uart/uart_tx.v
data/verilator_xmls/595931d4-a2b8-443e-b84e-5544a0c1423c.xml
module uart_tx
#(
	parameter BAUDRATE = 115200,
	parameter CLK_RATE = 50000000
)
(
    input	wire		clk,
	

    output  reg			tx,
	

    input	wire		tx_en,
    input	wire [7:0]	tx_data,
	output	reg			tx_ready
);

reg start;
reg clk_en;
reg [3:0] cnt;
reg [7:0] data;
reg [31:0] clk_cnt;

initial
begin
	start = 0;
end


always@(posedge clk)
begin
	if(!start)
		clk_cnt <= 0;
	else if(clk_cnt == CLK_RATE / BAUDRATE - 1)
		clk_cnt <= 0;
	else
		clk_cnt <= clk_cnt + 1;
end


always@(posedge clk)
begin
	clk_en <= (clk_cnt == CLK_RATE / BAUDRATE - 1);
end


always@(posedge clk)
begin
    if(tx_en)
        start <= 1;
    else if(cnt == 10)
        start <= 0;
end


always@(posedge clk)
begin
	if(tx_en && !start)
		data <= tx_data;
end


always@(posedge clk)
begin
    if(!start)
		cnt <= 0;
	else if(clk_en)
        cnt <= cnt + 1;
end


always@(posedge clk)
begin
    case(cnt)
		0: tx <= 1'b1;
        1: tx <= 1'b0;
        2: tx <= data[0];
        3: tx <= data[1];
        4: tx <= data[2];
        5: tx <= data[3];
        6: tx <= data[4];
        7: tx <= data[5];
        8: tx <= data[6];
        9: tx <= data[7];
        10:tx <= 1'b1;
    endcase
end


always@(posedge clk)
begin
	if(tx_en)
		tx_ready <= 0;
	else
		tx_ready <= !start;
end

endmodule
module uart_tx
#(
	parameter BAUDRATE = 115200,
	parameter CLK_RATE = 50000000
)
(
    input	wire		clk,
	

    output  reg			tx,
	

    input	wire		tx_en,
    input	wire [7:0]	tx_data,
	output	reg			tx_ready
);


reg start;
reg clk_en;
reg [3:0] cnt;
reg [7:0] data;
reg [31:0] clk_cnt;

initial
begin
	start = 0;
end


always@(posedge clk)
begin
	if(!start)
		clk_cnt <= 0;
	else if(clk_cnt == CLK_RATE / BAUDRATE - 1)
		clk_cnt <= 0;
	else
		clk_cnt <= clk_cnt + 1;
end


always@(posedge clk)
begin
	clk_en <= (clk_cnt == CLK_RATE / BAUDRATE - 1);
end


always@(posedge clk)
begin
    if(tx_en)
        start <= 1;
    else if(cnt == 10)
        start <= 0;
end


always@(posedge clk)
begin
	if(tx_en && !start)
		data <= tx_data;
end


always@(posedge clk)
begin
    if(!start)
		cnt <= 0;
	else if(clk_en)
        cnt <= cnt + 1;
end


always@(posedge clk)
begin
    case(cnt)
		0: tx <= 1'b1;
        1: tx <= 1'b0;
        2: tx <= data[0];
        3: tx <= data[1];
        4: tx <= data[2];
        5: tx <= data[3];
        6: tx <= data[4];
        7: tx <= data[5];
        8: tx <= data[6];
        9: tx <= data[7];
        10:tx <= 1'b1;
    endcase
end


always@(posedge clk)
begin
	if(tx_en)
		tx_ready <= 0;
	else
		tx_ready <= !start;
end

endmodule