data/full_repos/permissive/143278/ivltests/negative_genvar.v
 line:7: before: "for"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/negative_genvar.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/negative_genvar.v:8: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hffffffff\' generates 32 bits.\n                                                                              : ... In instance negative_genvar\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/negative_genvar.v:8: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hfffffffe\' generates 32 bits.\n                                                                              : ... In instance negative_genvar\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/negative_genvar.v:8: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hfffffffd\' generates 32 bits.\n                                                                              : ... In instance negative_genvar\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/negative_genvar.v:8: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hfffffffc\' generates 32 bits.\n                                                                              : ... In instance negative_genvar\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/negative_genvar.v:8: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hfffffffb\' generates 32 bits.\n                                                                              : ... In instance negative_genvar\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/negative_genvar.v:8: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hfffffffa\' generates 32 bits.\n                                                                              : ... In instance negative_genvar\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/negative_genvar.v:8: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hfffffff9\' generates 32 bits.\n                                                                              : ... In instance negative_genvar\n  assign value[i] = i;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/negative_genvar.v:19: Operator NEQCASE expects 32 bits on the LHS, but LHS\'s ARRAYSEL generates 4 bits.\n                                                                               : ... In instance negative_genvar\n    if (value[j] !== j) fail = 1;\n                 ^~~\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module negative_genvar;

wire signed [3:0] value[-7:7];

genvar i;

for (i = 7; i >= -7; i = i - 1) begin:genloop
  assign value[i] = i;
end

integer j;

reg fail = 0;

initial begin
  #0;
  for (j = -7; j <= 7; j = j + 1) begin
    $display("%d", value[j]);
    if (value[j] !== j) fail = 1;
  end

  if (fail)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module negative_genvar;


wire signed [3:0] value[-7:7];

genvar i;

for (i = 7; i >= -7; i = i - 1) begin:genloop
  assign value[i] = i;
end

integer j;

reg fail = 0;

initial begin
  #0;
  for (j = -7; j <= 7; j = j + 1) begin
    $display("%d", value[j]);
    if (value[j] !== j) fail = 1;
  end

  if (fail)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule