data/full_repos/permissive/119387855/mips_alu_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b0000; \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b0001;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b0010; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b0100;   \n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b0101;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b0110;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b0111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b1001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b1010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b1011;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b1110;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119387855/mips_alu_testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #10 alu_op = 4\'b1100;\n ^\n%Error: data/full_repos/permissive/119387855/mips_alu_testbench.v:34: Unsupported or unknown PLI call: $monitor\n $monitor(" alu_op: %b, result: %b zero: %b",alu_op, result, zero);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_alu_testbench();

	wire zero;
	wire [31:0] result;

	reg [31:0] first_data;
	reg [31:0] second_data;
	reg [3:0] alu_op;
	reg [4:0] shamt;
	mips_alu test(zero, result, alu_op, first_data, second_data, shamt);
	
	initial first_data = 32'b10000000000000000000000000000000;
	initial second_data = 32'b01111111111111111111111111111111;
	
	initial begin
	#10 alu_op = 4'b0000; 
	#10 alu_op = 4'b0001;  
	#10 alu_op = 4'b0010; 
	#10 alu_op = 4'b0100;  	
	#10 alu_op = 4'b0101;
	#10 alu_op = 4'b0110;
	#10 alu_op = 4'b0111;
	#10 alu_op = 4'b1000;
	#10 alu_op = 4'b1001;
	#10 alu_op = 4'b1010;
	#10 alu_op = 4'b1011;
	#10 alu_op = 4'b1110;
	#10 alu_op = 4'b1111;
	#10 alu_op = 4'b1100;
		
end

initial begin
	$monitor(" alu_op: %b, result: %b zero: %b",alu_op, result, zero);
end

endmodule
module mips_alu_testbench();


	wire zero;
	wire [31:0] result;

	reg [31:0] first_data;
	reg [31:0] second_data;
	reg [3:0] alu_op;
	reg [4:0] shamt;
	mips_alu test(zero, result, alu_op, first_data, second_data, shamt);
	
	initial first_data = 32'b10000000000000000000000000000000;
	initial second_data = 32'b01111111111111111111111111111111;
	
	initial begin
	#10 alu_op = 4'b0000; 
	#10 alu_op = 4'b0001;  
	#10 alu_op = 4'b0010; 
	#10 alu_op = 4'b0100;  	
	#10 alu_op = 4'b0101;
	#10 alu_op = 4'b0110;
	#10 alu_op = 4'b0111;
	#10 alu_op = 4'b1000;
	#10 alu_op = 4'b1001;
	#10 alu_op = 4'b1010;
	#10 alu_op = 4'b1011;
	#10 alu_op = 4'b1110;
	#10 alu_op = 4'b1111;
	#10 alu_op = 4'b1100;
		
end

initial begin
	$monitor(" alu_op: %b, result: %b zero: %b",alu_op, result, zero);
end

endmodule