data/full_repos/permissive/18921956/HardwareLab/Final/Final.v
1: b"%Error: data/full_repos/permissive/18921956/HardwareLab/Final/Final.v:32: Cannot find file containing module: 'CLK_DIV'\nCLK_DIV clk_div(clk_1us, clk);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18921956/HardwareLab/Final,data/full_repos/permissive/18921956/CLK_DIV\n             data/full_repos/permissive/18921956/HardwareLab/Final,data/full_repos/permissive/18921956/CLK_DIV.v\n             data/full_repos/permissive/18921956/HardwareLab/Final,data/full_repos/permissive/18921956/CLK_DIV.sv\n             CLK_DIV\n             CLK_DIV.v\n             CLK_DIV.sv\n             obj_dir/CLK_DIV\n             obj_dir/CLK_DIV.v\n             obj_dir/CLK_DIV.sv\n%Error: data/full_repos/permissive/18921956/HardwareLab/Final/Final.v:33: Cannot find file containing module: 'CAR_CTR'\nCAR_CTR car_ctr(md1, md2, md3, md4, inf1, inf2, clk_1us, reset_n);\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Final(
    output  md1,
    output  md2,
    output  md3,
    output  md4,
    input   inf1,
    input   inf2,
    input   clk,
    input   reset_n
);
wire clk_1us;
CLK_DIV clk_div(clk_1us, clk);
CAR_CTR car_ctr(md1, md2, md3, md4, inf1, inf2, clk_1us, reset_n);

endmodule
module Final(
    output  md1,
    output  md2,
    output  md3,
    output  md4,
    input   inf1,
    input   inf2,
    input   clk,
    input   reset_n
);

wire clk_1us;
CLK_DIV clk_div(clk_1us, clk);
CAR_CTR car_ctr(md1, md2, md3, md4, inf1, inf2, clk_1us, reset_n);

endmodule