data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Basics/Basics/notgate.v
data/verilator_xmls/9faeb360-7f0d-4229-bb7c-4aef5aa007f4.xml
module top_module( input in, output out );
    assign out = !in;
endmodule
module top_module( input in, output out );

    assign out = !in;
endmodule