data/full_repos/permissive/120024308/src/core/ram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/120024308/src/core/ram.v:314: Bit extraction of array[80:0] requires 7 bit index, not 30 bits.\n                                                                       : ... In instance Ram\n           ram[address[ADDR_WIDTH-1:2]] <= data_in;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/120024308/src/core/ram.v:317: Bit extraction of array[80:0] requires 7 bit index, not 30 bits.\n                                                                       : ... In instance Ram\n        temp_read_data <= ram[address[ADDR_WIDTH-1:2]];\n                             ^\n%Error: Exiting due to 2 warning(s)\n'
module Ram # ( parameter DATA_WIDTH= 32, parameter ADDR_WIDTH=32, parameter MEM_SIZE=80 )
   (
    input wire 			 clk,
    input wire 			 write_en,
    input wire 			 read_en,
    input wire [ADDR_WIDTH-1:0]  address,
    input wire [DATA_WIDTH-1:0]  data_in,
    output wire [DATA_WIDTH-1:0] data_out,

    output wire [DATA_WIDTH-1:0] visR1,
    output wire [DATA_WIDTH-1:0] visR2,
    output wire [DATA_WIDTH-1:0] visR3,
    output wire [DATA_WIDTH-1:0] visR4,
    output wire [DATA_WIDTH-1:0] visR5,
    output wire [DATA_WIDTH-1:0] visR6,
    output wire [DATA_WIDTH-1:0] visR7,
    output wire [DATA_WIDTH-1:0] visR8,
    output wire [DATA_WIDTH-1:0] visR9,

    output wire [DATA_WIDTH-1:0] visR10,
    output wire [DATA_WIDTH-1:0] visR11,
    output wire [DATA_WIDTH-1:0] visR12,
    output wire [DATA_WIDTH-1:0] visR13,
    output wire [DATA_WIDTH-1:0] visR14,
    output wire [DATA_WIDTH-1:0] visR15,
    output wire [DATA_WIDTH-1:0] visR16,
    output wire [DATA_WIDTH-1:0] visR17,
    output wire [DATA_WIDTH-1:0] visR18,
    output wire [DATA_WIDTH-1:0] visR19,

    output wire [DATA_WIDTH-1:0] visR20,
    output wire [DATA_WIDTH-1:0] visR21,
    output wire [DATA_WIDTH-1:0] visR22,
    output wire [DATA_WIDTH-1:0] visR23,
    output wire [DATA_WIDTH-1:0] visR24,
    output wire [DATA_WIDTH-1:0] visR25,
    output wire [DATA_WIDTH-1:0] visR26,
    output wire [DATA_WIDTH-1:0] visR27,
    output wire [DATA_WIDTH-1:0] visR28,
    output wire [DATA_WIDTH-1:0] visR29,

    output wire [DATA_WIDTH-1:0] visR30,
    output wire [DATA_WIDTH-1:0] visR31,
    output wire [DATA_WIDTH-1:0] visR32,
    output wire [DATA_WIDTH-1:0] visR33,
    output wire [DATA_WIDTH-1:0] visR34,
    output wire [DATA_WIDTH-1:0] visR35,
    output wire [DATA_WIDTH-1:0] visR36,
    output wire [DATA_WIDTH-1:0] visR37,
    output wire [DATA_WIDTH-1:0] visR38,
    output wire [DATA_WIDTH-1:0] visR39,

    output wire [DATA_WIDTH-1:0] visR40,
    output wire [DATA_WIDTH-1:0] visR41,
    output wire [DATA_WIDTH-1:0] visR42,
    output wire [DATA_WIDTH-1:0] visR43,
    output wire [DATA_WIDTH-1:0] visR44,
    output wire [DATA_WIDTH-1:0] visR45,
    output wire [DATA_WIDTH-1:0] visR46,
    output wire [DATA_WIDTH-1:0] visR47,
    output wire [DATA_WIDTH-1:0] visR48,
    output wire [DATA_WIDTH-1:0] visR49,

    output wire [DATA_WIDTH-1:0] visR50,
    output wire [DATA_WIDTH-1:0] visR51,
    output wire [DATA_WIDTH-1:0] visR52,
    output wire [DATA_WIDTH-1:0] visR53,
    output wire [DATA_WIDTH-1:0] visR54,
    output wire [DATA_WIDTH-1:0] visR55,
    output wire [DATA_WIDTH-1:0] visR56,
    output wire [DATA_WIDTH-1:0] visR57,
    output wire [DATA_WIDTH-1:0] visR58,
    output wire [DATA_WIDTH-1:0] visR59,

    output wire [DATA_WIDTH-1:0] visR60
    );

   reg [DATA_WIDTH-1:0]          ram [MEM_SIZE:0];

   assign visR1 = ram[1];
   assign visR1 = ram[1];
   assign visR2 = ram[2];
   assign visR3 = ram[3];
   assign visR4 = ram[4];
   assign visR5 = ram[5];
   assign visR6 = ram[6];
   assign visR7 = ram[7];
   assign visR8 = ram[8];
   assign visR9 = ram[9];

   assign visR10 = ram[10];
   assign visR11 = ram[11];
   assign visR12 = ram[12];
   assign visR13 = ram[13];
   assign visR14 = ram[14];
   assign visR15 = ram[15];
   assign visR16 = ram[16];
   assign visR17 = ram[17];
   assign visR18 = ram[18];
   assign visR19 = ram[19];

   assign visR20 = ram[20];
   assign visR21 = ram[21];
   assign visR22 = ram[22];
   assign visR23 = ram[23];
   assign visR24 = ram[24];
   assign visR25 = ram[25];
   assign visR26 = ram[26];
   assign visR27 = ram[27];
   assign visR28 = ram[28];
   assign visR29 = ram[29];

   assign visR30 = ram[30];
   assign visR31 = ram[31];
   assign visR32 = ram[32];
   assign visR33 = ram[33];
   assign visR34 = ram[34];
   assign visR35 = ram[35];
   assign visR36 = ram[36];
   assign visR37 = ram[37];
   assign visR38 = ram[38];
   assign visR39 = ram[39];

   assign visR40 = ram[40];
   assign visR41 = ram[41];
   assign visR42 = ram[42];
   assign visR43 = ram[43];
   assign visR44 = ram[44];
   assign visR45 = ram[45];
   assign visR46 = ram[46];
   assign visR47 = ram[47];
   assign visR48 = ram[48];
   assign visR49 = ram[49];

   assign visR50 = ram[50];
   assign visR51 = ram[51];
   assign visR52 = ram[52];
   assign visR53 = ram[53];
   assign visR54 = ram[54];
   assign visR55 = ram[55];
   assign visR56 = ram[56];
   assign visR57 = ram[57];
   assign visR58 = ram[58];
   assign visR59 = ram[59];

   assign visR60 = ram[60];


   reg 				 delayed_read_en, output_en;
   

   reg [DATA_WIDTH-1:0]          temp_read_data;
   assign data_out= (output_en)? temp_read_data: 32'b0;


   always @(posedge clk)
     begin
	delayed_read_en <= read_en;
	output_en <= delayed_read_en;	
        if (write_en) begin
           ram[address[ADDR_WIDTH-1:2]] <= data_in;
        end

        temp_read_data <= ram[address[ADDR_WIDTH-1:2]];
     end
endmodule
module Ram # ( parameter DATA_WIDTH= 32, parameter ADDR_WIDTH=32, parameter MEM_SIZE=80 )
   (
    input wire 			 clk,
    input wire 			 write_en,
    input wire 			 read_en,
    input wire [ADDR_WIDTH-1:0]  address,
    input wire [DATA_WIDTH-1:0]  data_in,
    output wire [DATA_WIDTH-1:0] data_out,

    output wire [DATA_WIDTH-1:0] visR1,
    output wire [DATA_WIDTH-1:0] visR2,
    output wire [DATA_WIDTH-1:0] visR3,
    output wire [DATA_WIDTH-1:0] visR4,
    output wire [DATA_WIDTH-1:0] visR5,
    output wire [DATA_WIDTH-1:0] visR6,
    output wire [DATA_WIDTH-1:0] visR7,
    output wire [DATA_WIDTH-1:0] visR8,
    output wire [DATA_WIDTH-1:0] visR9,

    output wire [DATA_WIDTH-1:0] visR10,
    output wire [DATA_WIDTH-1:0] visR11,
    output wire [DATA_WIDTH-1:0] visR12,
    output wire [DATA_WIDTH-1:0] visR13,
    output wire [DATA_WIDTH-1:0] visR14,
    output wire [DATA_WIDTH-1:0] visR15,
    output wire [DATA_WIDTH-1:0] visR16,
    output wire [DATA_WIDTH-1:0] visR17,
    output wire [DATA_WIDTH-1:0] visR18,
    output wire [DATA_WIDTH-1:0] visR19,

    output wire [DATA_WIDTH-1:0] visR20,
    output wire [DATA_WIDTH-1:0] visR21,
    output wire [DATA_WIDTH-1:0] visR22,
    output wire [DATA_WIDTH-1:0] visR23,
    output wire [DATA_WIDTH-1:0] visR24,
    output wire [DATA_WIDTH-1:0] visR25,
    output wire [DATA_WIDTH-1:0] visR26,
    output wire [DATA_WIDTH-1:0] visR27,
    output wire [DATA_WIDTH-1:0] visR28,
    output wire [DATA_WIDTH-1:0] visR29,

    output wire [DATA_WIDTH-1:0] visR30,
    output wire [DATA_WIDTH-1:0] visR31,
    output wire [DATA_WIDTH-1:0] visR32,
    output wire [DATA_WIDTH-1:0] visR33,
    output wire [DATA_WIDTH-1:0] visR34,
    output wire [DATA_WIDTH-1:0] visR35,
    output wire [DATA_WIDTH-1:0] visR36,
    output wire [DATA_WIDTH-1:0] visR37,
    output wire [DATA_WIDTH-1:0] visR38,
    output wire [DATA_WIDTH-1:0] visR39,

    output wire [DATA_WIDTH-1:0] visR40,
    output wire [DATA_WIDTH-1:0] visR41,
    output wire [DATA_WIDTH-1:0] visR42,
    output wire [DATA_WIDTH-1:0] visR43,
    output wire [DATA_WIDTH-1:0] visR44,
    output wire [DATA_WIDTH-1:0] visR45,
    output wire [DATA_WIDTH-1:0] visR46,
    output wire [DATA_WIDTH-1:0] visR47,
    output wire [DATA_WIDTH-1:0] visR48,
    output wire [DATA_WIDTH-1:0] visR49,

    output wire [DATA_WIDTH-1:0] visR50,
    output wire [DATA_WIDTH-1:0] visR51,
    output wire [DATA_WIDTH-1:0] visR52,
    output wire [DATA_WIDTH-1:0] visR53,
    output wire [DATA_WIDTH-1:0] visR54,
    output wire [DATA_WIDTH-1:0] visR55,
    output wire [DATA_WIDTH-1:0] visR56,
    output wire [DATA_WIDTH-1:0] visR57,
    output wire [DATA_WIDTH-1:0] visR58,
    output wire [DATA_WIDTH-1:0] visR59,

    output wire [DATA_WIDTH-1:0] visR60
    );


   reg [DATA_WIDTH-1:0]          ram [MEM_SIZE:0];

   assign visR1 = ram[1];
   assign visR1 = ram[1];
   assign visR2 = ram[2];
   assign visR3 = ram[3];
   assign visR4 = ram[4];
   assign visR5 = ram[5];
   assign visR6 = ram[6];
   assign visR7 = ram[7];
   assign visR8 = ram[8];
   assign visR9 = ram[9];

   assign visR10 = ram[10];
   assign visR11 = ram[11];
   assign visR12 = ram[12];
   assign visR13 = ram[13];
   assign visR14 = ram[14];
   assign visR15 = ram[15];
   assign visR16 = ram[16];
   assign visR17 = ram[17];
   assign visR18 = ram[18];
   assign visR19 = ram[19];

   assign visR20 = ram[20];
   assign visR21 = ram[21];
   assign visR22 = ram[22];
   assign visR23 = ram[23];
   assign visR24 = ram[24];
   assign visR25 = ram[25];
   assign visR26 = ram[26];
   assign visR27 = ram[27];
   assign visR28 = ram[28];
   assign visR29 = ram[29];

   assign visR30 = ram[30];
   assign visR31 = ram[31];
   assign visR32 = ram[32];
   assign visR33 = ram[33];
   assign visR34 = ram[34];
   assign visR35 = ram[35];
   assign visR36 = ram[36];
   assign visR37 = ram[37];
   assign visR38 = ram[38];
   assign visR39 = ram[39];

   assign visR40 = ram[40];
   assign visR41 = ram[41];
   assign visR42 = ram[42];
   assign visR43 = ram[43];
   assign visR44 = ram[44];
   assign visR45 = ram[45];
   assign visR46 = ram[46];
   assign visR47 = ram[47];
   assign visR48 = ram[48];
   assign visR49 = ram[49];

   assign visR50 = ram[50];
   assign visR51 = ram[51];
   assign visR52 = ram[52];
   assign visR53 = ram[53];
   assign visR54 = ram[54];
   assign visR55 = ram[55];
   assign visR56 = ram[56];
   assign visR57 = ram[57];
   assign visR58 = ram[58];
   assign visR59 = ram[59];

   assign visR60 = ram[60];


   reg 				 delayed_read_en, output_en;
   

   reg [DATA_WIDTH-1:0]          temp_read_data;
   assign data_out= (output_en)? temp_read_data: 32'b0;


   always @(posedge clk)
     begin
	delayed_read_en <= read_en;
	output_en <= delayed_read_en;	
        if (write_en) begin
           ram[address[ADDR_WIDTH-1:2]] <= data_in;
        end

        temp_read_data <= ram[address[ADDR_WIDTH-1:2]];
     end
endmodule