data/full_repos/permissive/115487336/mycode/Mips/MultiCycle-Mips/FSM.v
data/verilator_xmls/c984b046-d243-4a9f-9625-1150230ae6aa.xml
module FSM(
	input clk,
	input rst_n,
	input [31:0] ir,
	
	output reg RegDst,
	output reg MemtoReg,
	
	output reg IorD,
	output reg MemWrite,
	output reg IRWrite,
	output reg pcen,
	output reg Branch,
	output reg PCSrc,
	output reg [4:0] ALUControl,
	output reg [1:0] ALUSrcB,
	output reg ALUSrcA,
	output reg RegWrite,
	
	output reg ALURegWe,
	
	output reg NeedJmp,
	output reg BorJ
);



















reg [7:0] nowstate;
reg [7:0] nextstate;


always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		nowstate<=8'h0;
	end
	else
		nowstate<=nextstate;
end

always@(*)
begin
	case(nowstate)
	8'h0:
		nextstate=8'h1;
	8'h1:
		nextstate=8'h2;
	8'h2:
		begin
			case(ir[31:26])
			6'h0:
				nextstate=8'h10;
			6'h8:
				nextstate=8'h20;
			6'h23:
				nextstate=8'h30;
			6'h2B:
				nextstate=8'h40;
			6'h2:
				nextstate=8'h50;
			6'h7:
				nextstate=8'h60;
			default:
				nextstate=8'h0;
			endcase
		end
	8'h10:
		nextstate=8'h11;
	8'h20:
		nextstate=8'h21;
	8'h30:
		nextstate=8'h31;
	8'h31:
		nextstate=8'h32;
	8'h40:
		nextstate=8'h41;
	8'h50:
		nextstate=8'h51;
	8'h60:
		nextstate=8'h61;
	default:
		nextstate=8'h1;
	endcase
end

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		pcen<=1;
		MemWrite<=0;
		RegWrite<=0;
		IorD<=0;
		IRWrite<=0;
		Branch<=0;
		PCSrc<=0;
		ALUControl<=5'b0;
		ALUSrcB<=2'b0;
		ALUSrcA<=0;
		RegWrite<=0;
		ALURegWe<=0;
		NeedJmp<=0;
		BorJ<=0;
	end
	else
	begin
	case(nextstate)
	8'h1:
	begin

		pcen<=0;
		IRWrite<=1;
	end
	8'h2:
	begin

		IRWrite<=0;
	end
	8'h10:
	begin
		RegDst<=1;
		RegWrite<=1;
		ALUSrcA<=1;
		ALUSrcB<=2'b00;
		ALURegWe<=1;
		ALUControl<=5'h1;
		MemtoReg<=0;
	end
	8'h11:
	begin
		RegDst<=0;
		RegWrite<=0;
		ALUSrcA<=0;
		ALUControl<=5'h0;
		pcen<=1;
		ALURegWe<=0;
	end
	8'h20:
	begin
		RegDst<=0;
		RegWrite<=1;
		ALUSrcA<=1;
		ALUSrcB<=2'b10;
		ALUControl<=5'h1;
		MemtoReg<=0;
		ALURegWe<=1;
	end
	8'h21:
	begin
		RegDst<=0;
		RegWrite<=0;
		ALUSrcA<=0;
		ALUSrcB<=2'b0;
		ALUControl<=5'h0;
		pcen<=1;
		ALURegWe<=0;
	end
	8'h30:
	begin
		ALUSrcA<=1;
		ALUSrcB<=2'b11;
		ALUControl<=5'h1;
		IorD<=1;
		ALURegWe<=1;
	end
	8'h31:
	begin
		ALURegWe<=0;
		IorD<=0;
		ALUControl<=5'h0;
		ALUSrcA<=0;
		ALUSrcB<=2'b0;

		RegDst<=0;
		RegWrite<=1;
	end
	8'h32:
	begin

		RegWrite<=0;
		pcen<=1;
	end
	8'h40:
	begin
		ALUSrcA<=1;
		ALUSrcB<=2'b11;
		ALUControl<=5'h1;
		IorD<=1;
		ALURegWe<=1;
		MemWrite<=1;
	end
	8'h41:
	begin
		MemWrite<=0;
		ALURegWe<=0;
		IorD<=0;
		ALUSrcA<=0;
		ALUSrcB<=2'b0;
		ALUControl<=5'h0;
		pcen<=1;
	end
	8'h50:
	begin
		ALUSrcA<=1;
		ALUControl<=5'h7;
		NeedJmp<=1;
		BorJ<=1;
	end
	8'h51:
	begin
		NeedJmp<=0;
		BorJ<=0;
		pcen<=1;
	end
	8'h60:
	begin
		NeedJmp<=1;
		BorJ<=0;
	end
	8'h61:
	begin
		NeedJmp<=0;
		pcen<=1;
	end
	endcase
	end
end
endmodule
module FSM(
	input clk,
	input rst_n,
	input [31:0] ir,
	
	output reg RegDst,
	output reg MemtoReg,
	
	output reg IorD,
	output reg MemWrite,
	output reg IRWrite,
	output reg pcen,
	output reg Branch,
	output reg PCSrc,
	output reg [4:0] ALUControl,
	output reg [1:0] ALUSrcB,
	output reg ALUSrcA,
	output reg RegWrite,
	
	output reg ALURegWe,
	
	output reg NeedJmp,
	output reg BorJ
);




















reg [7:0] nowstate;
reg [7:0] nextstate;


always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		nowstate<=8'h0;
	end
	else
		nowstate<=nextstate;
end

always@(*)
begin
	case(nowstate)
	8'h0:
		nextstate=8'h1;
	8'h1:
		nextstate=8'h2;
	8'h2:
		begin
			case(ir[31:26])
			6'h0:
				nextstate=8'h10;
			6'h8:
				nextstate=8'h20;
			6'h23:
				nextstate=8'h30;
			6'h2B:
				nextstate=8'h40;
			6'h2:
				nextstate=8'h50;
			6'h7:
				nextstate=8'h60;
			default:
				nextstate=8'h0;
			endcase
		end
	8'h10:
		nextstate=8'h11;
	8'h20:
		nextstate=8'h21;
	8'h30:
		nextstate=8'h31;
	8'h31:
		nextstate=8'h32;
	8'h40:
		nextstate=8'h41;
	8'h50:
		nextstate=8'h51;
	8'h60:
		nextstate=8'h61;
	default:
		nextstate=8'h1;
	endcase
end

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		pcen<=1;
		MemWrite<=0;
		RegWrite<=0;
		IorD<=0;
		IRWrite<=0;
		Branch<=0;
		PCSrc<=0;
		ALUControl<=5'b0;
		ALUSrcB<=2'b0;
		ALUSrcA<=0;
		RegWrite<=0;
		ALURegWe<=0;
		NeedJmp<=0;
		BorJ<=0;
	end
	else
	begin
	case(nextstate)
	8'h1:
	begin

		pcen<=0;
		IRWrite<=1;
	end
	8'h2:
	begin

		IRWrite<=0;
	end
	8'h10:
	begin
		RegDst<=1;
		RegWrite<=1;
		ALUSrcA<=1;
		ALUSrcB<=2'b00;
		ALURegWe<=1;
		ALUControl<=5'h1;
		MemtoReg<=0;
	end
	8'h11:
	begin
		RegDst<=0;
		RegWrite<=0;
		ALUSrcA<=0;
		ALUControl<=5'h0;
		pcen<=1;
		ALURegWe<=0;
	end
	8'h20:
	begin
		RegDst<=0;
		RegWrite<=1;
		ALUSrcA<=1;
		ALUSrcB<=2'b10;
		ALUControl<=5'h1;
		MemtoReg<=0;
		ALURegWe<=1;
	end
	8'h21:
	begin
		RegDst<=0;
		RegWrite<=0;
		ALUSrcA<=0;
		ALUSrcB<=2'b0;
		ALUControl<=5'h0;
		pcen<=1;
		ALURegWe<=0;
	end
	8'h30:
	begin
		ALUSrcA<=1;
		ALUSrcB<=2'b11;
		ALUControl<=5'h1;
		IorD<=1;
		ALURegWe<=1;
	end
	8'h31:
	begin
		ALURegWe<=0;
		IorD<=0;
		ALUControl<=5'h0;
		ALUSrcA<=0;
		ALUSrcB<=2'b0;

		RegDst<=0;
		RegWrite<=1;
	end
	8'h32:
	begin

		RegWrite<=0;
		pcen<=1;
	end
	8'h40:
	begin
		ALUSrcA<=1;
		ALUSrcB<=2'b11;
		ALUControl<=5'h1;
		IorD<=1;
		ALURegWe<=1;
		MemWrite<=1;
	end
	8'h41:
	begin
		MemWrite<=0;
		ALURegWe<=0;
		IorD<=0;
		ALUSrcA<=0;
		ALUSrcB<=2'b0;
		ALUControl<=5'h0;
		pcen<=1;
	end
	8'h50:
	begin
		ALUSrcA<=1;
		ALUControl<=5'h7;
		NeedJmp<=1;
		BorJ<=1;
	end
	8'h51:
	begin
		NeedJmp<=0;
		BorJ<=0;
		pcen<=1;
	end
	8'h60:
	begin
		NeedJmp<=1;
		BorJ<=0;
	end
	8'h61:
	begin
		NeedJmp<=0;
		pcen<=1;
	end
	endcase
	end
end
endmodule