data/full_repos/permissive/127511545/src/Decoder.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Decoder.v:56: Signal definition not found, creating implicitly: \'F1\'\n and #(50) a0(F1, A, B, C, D), a1(G, F1, E);\n              ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Decoder.v:67: Signal definition not found, creating implicitly: \'NotA\'\n not #(50) inv4(NotA, Address[4]);\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Decoder.v:68: Signal definition not found, creating implicitly: \'NotB\'\n                                                                        : ... Suggested alternative: \'NotA\'\n not #(50) inv3(NotB, Address[3]);\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Decoder.v:69: Signal definition not found, creating implicitly: \'NotC\'\n                                                                        : ... Suggested alternative: \'NotA\'\n not #(50) inv2(NotC, Address[2]);\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Decoder.v:70: Signal definition not found, creating implicitly: \'NotD\'\n                                                                        : ... Suggested alternative: \'NotA\'\n not #(50) inv1(NotD, Address[1]);\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/Decoder.v:71: Signal definition not found, creating implicitly: \'NotE\'\n                                                                        : ... Suggested alternative: \'NotA\'\n not #(50) inv0(NotE, Address[0]);\n                ^~~~\n%Error: Exiting due to 6 warning(s)\n'
module Decoder5to32(Output, Address);

	output[31:0] Output;
	input[4:0] Address;

	not #(50) inv4(NotA, Address[4]);
	not #(50) inv3(NotB, Address[3]);
	not #(50) inv2(NotC, Address[2]);
	not #(50) inv1(NotD, Address[1]);
	not #(50) inv0(NotE, Address[0]);

	AndMore am0(Output[0], NotA, NotB, NotC, NotD, NotE);
	AndMore am1(Output[1], NotA, NotB, NotC, NotD, Address[0]);
	AndMore am2(Output[2], NotA, NotB, NotC, Address[1], NotE);
	AndMore am3(Output[3], NotA, NotB, NotC, Address[1], Address[0]);
	AndMore am4(Output[4], NotA, NotB, Address[2], NotD, NotE);
	AndMore am5(Output[5], NotA, NotB, Address[2], NotD, Address[0]);
	AndMore am6(Output[6], NotA, NotB, Address[2], Address[1], NotE);
	AndMore am7(Output[7], NotA, NotB, Address[2], Address[1], Address[0]);
	AndMore am8(Output[8], NotA, Address[3], NotC, NotD, NotE);
	AndMore am9(Output[9], NotA, Address[3], NotC, NotD, Address[0]);
	AndMore am10(Output[10], NotA, Address[3], NotC, Address[1], NotE);
	AndMore am11(Output[11], NotA, Address[3], NotC, Address[1], Address[0]);
	AndMore am12(Output[12], NotA, Address[3], Address[2], NotD, NotE);
	AndMore am13(Output[13], NotA, Address[3], Address[2], NotD, Address[0]);
	AndMore am14(Output[14], NotA, Address[3], Address[2], Address[1], NotE);
	AndMore am15(Output[15], NotA, Address[3], Address[2], Address[1], Address[0]);
	AndMore am16(Output[16], Address[4], NotB, NotC, NotD, NotE);
	AndMore am17(Output[17], Address[4], NotB, NotC, NotD, Address[0]);
	AndMore am18(Output[18], Address[4], NotB, NotC, Address[1], NotE);
	AndMore am19(Output[19], Address[4], NotB, NotC, Address[1], Address[0]);
	AndMore am20(Output[20], Address[4], NotB, Address[2], NotD, NotE);
	AndMore am21(Output[21], Address[4], NotB, Address[2], NotD, Address[0]);
	AndMore am22(Output[22], Address[4], NotB, Address[2], Address[1], NotE);
	AndMore am23(Output[23], Address[4], NotB, Address[2], Address[1], Address[0]);
	AndMore am24(Output[24], Address[4], Address[3], NotC, NotD, NotE);
	AndMore am25(Output[25], Address[4], Address[3], NotC, NotD, Address[0]);
	AndMore am26(Output[26], Address[4], Address[3], NotC, Address[1], NotE);
	AndMore am27(Output[27], Address[4], Address[3], NotC, Address[1], Address[0]);
	AndMore am28(Output[28], Address[4], Address[3], Address[2], NotD, NotE);
	AndMore am29(Output[29], Address[4], Address[3], Address[2], NotD, Address[0]);
	AndMore am30(Output[30], Address[4], Address[3], Address[2], Address[1], NotE);
	AndMore am31(Output[31], Address[4], Address[3], Address[2], Address[1], Address[0]);

endmodule
module Decoder5to32(Output, Address);


	output[31:0] Output;
	input[4:0] Address;

	not #(50) inv4(NotA, Address[4]);
	not #(50) inv3(NotB, Address[3]);
	not #(50) inv2(NotC, Address[2]);
	not #(50) inv1(NotD, Address[1]);
	not #(50) inv0(NotE, Address[0]);

	AndMore am0(Output[0], NotA, NotB, NotC, NotD, NotE);
	AndMore am1(Output[1], NotA, NotB, NotC, NotD, Address[0]);
	AndMore am2(Output[2], NotA, NotB, NotC, Address[1], NotE);
	AndMore am3(Output[3], NotA, NotB, NotC, Address[1], Address[0]);
	AndMore am4(Output[4], NotA, NotB, Address[2], NotD, NotE);
	AndMore am5(Output[5], NotA, NotB, Address[2], NotD, Address[0]);
	AndMore am6(Output[6], NotA, NotB, Address[2], Address[1], NotE);
	AndMore am7(Output[7], NotA, NotB, Address[2], Address[1], Address[0]);
	AndMore am8(Output[8], NotA, Address[3], NotC, NotD, NotE);
	AndMore am9(Output[9], NotA, Address[3], NotC, NotD, Address[0]);
	AndMore am10(Output[10], NotA, Address[3], NotC, Address[1], NotE);
	AndMore am11(Output[11], NotA, Address[3], NotC, Address[1], Address[0]);
	AndMore am12(Output[12], NotA, Address[3], Address[2], NotD, NotE);
	AndMore am13(Output[13], NotA, Address[3], Address[2], NotD, Address[0]);
	AndMore am14(Output[14], NotA, Address[3], Address[2], Address[1], NotE);
	AndMore am15(Output[15], NotA, Address[3], Address[2], Address[1], Address[0]);
	AndMore am16(Output[16], Address[4], NotB, NotC, NotD, NotE);
	AndMore am17(Output[17], Address[4], NotB, NotC, NotD, Address[0]);
	AndMore am18(Output[18], Address[4], NotB, NotC, Address[1], NotE);
	AndMore am19(Output[19], Address[4], NotB, NotC, Address[1], Address[0]);
	AndMore am20(Output[20], Address[4], NotB, Address[2], NotD, NotE);
	AndMore am21(Output[21], Address[4], NotB, Address[2], NotD, Address[0]);
	AndMore am22(Output[22], Address[4], NotB, Address[2], Address[1], NotE);
	AndMore am23(Output[23], Address[4], NotB, Address[2], Address[1], Address[0]);
	AndMore am24(Output[24], Address[4], Address[3], NotC, NotD, NotE);
	AndMore am25(Output[25], Address[4], Address[3], NotC, NotD, Address[0]);
	AndMore am26(Output[26], Address[4], Address[3], NotC, Address[1], NotE);
	AndMore am27(Output[27], Address[4], Address[3], NotC, Address[1], Address[0]);
	AndMore am28(Output[28], Address[4], Address[3], Address[2], NotD, NotE);
	AndMore am29(Output[29], Address[4], Address[3], Address[2], NotD, Address[0]);
	AndMore am30(Output[30], Address[4], Address[3], Address[2], Address[1], NotE);
	AndMore am31(Output[31], Address[4], Address[3], Address[2], Address[1], Address[0]);

endmodule