data/full_repos/permissive/124844461/Lab1/regfile.v
 line:60: before: "/"
1: b'%Warning-WIDTH: data/full_repos/permissive/124844461/Lab1/regfile.v:36: Bit extraction of array[31:0] requires 5 bit index, not 6 bits.\n                                                                      : ... In instance regfile\n   regfile1[i] = {DATA_WIDTH{1\'b0}};\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/124844461/Lab1/regfile.v:45: Bit extraction of array[31:0] requires 5 bit index, not 6 bits.\n                                                                      : ... In instance regfile\n     regfile1[i] = 0;\n             ^\n%Error: Exiting due to 2 warning(s)\n'
module regfile
#(parameter DATA_WIDTH = 32,V0 = 2, A0 = 4)
(
	input clk,
	input rst,
	input we,
	input [4:0] raddrA,
	input [4:0] raddrB,
	input [4:0] waddr,
	input [DATA_WIDTH -1:0] wdata,
	output [DATA_WIDTH -1:0] regA,
	output [DATA_WIDTH -1:0] regB,
	output [DATA_WIDTH -1:0] v0_data,
	output [DATA_WIDTH -1:0] a0_data
);

	reg [5:0] i;
	reg [DATA_WIDTH -1:0] regfile1 [0:31];

	initial begin
		for (i = 0; i < 32; i = i + 1) begin
			regfile1[i] = {DATA_WIDTH{1'b0}};
		end
	end


	always@(posedge clk) begin
		if(rst) begin
			for(i = 0; i < 32;i = i + 1)
				begin
					regfile1[i] = 0;
				end
		end else if(we && waddr != 0) begin
			regfile1[waddr] <= wdata;
		end
	end
	
	
	assign regA = regfile1[raddrA];
	assign regB = regfile1[raddrB];

	assign v0_data = 1;
	assign a0_data = 1;

endmodule
module regfile
#(parameter DATA_WIDTH = 32,V0 = 2, A0 = 4)
(
	input clk,
	input rst,
	input we,
	input [4:0] raddrA,
	input [4:0] raddrB,
	input [4:0] waddr,
	input [DATA_WIDTH -1:0] wdata,
	output [DATA_WIDTH -1:0] regA,
	output [DATA_WIDTH -1:0] regB,
	output [DATA_WIDTH -1:0] v0_data,
	output [DATA_WIDTH -1:0] a0_data
);


	reg [5:0] i;
	reg [DATA_WIDTH -1:0] regfile1 [0:31];

	initial begin
		for (i = 0; i < 32; i = i + 1) begin
			regfile1[i] = {DATA_WIDTH{1'b0}};
		end
	end


	always@(posedge clk) begin
		if(rst) begin
			for(i = 0; i < 32;i = i + 1)
				begin
					regfile1[i] = 0;
				end
		end else if(we && waddr != 0) begin
			regfile1[waddr] <= wdata;
		end
	end
	
	
	assign regA = regfile1[raddrA];
	assign regB = regfile1[raddrB];

	assign v0_data = 1;
	assign a0_data = 1;

endmodule