data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v:11: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] a,\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v:12: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] b,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v:13: Little bit endian vector: MSB < LSB of bit range: 0:31\n output [0:31] out,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v:16: Little bit endian vector: MSB < LSB of bit range: 0:31\n    reg [0:31] out_reg;\n        ^\n%Error: Exiting due to 4 warning(s)\n'
module frac_mult_16x16 (
	input [0:15] a,
	input [0:15] b,
	output [0:31] out,
    input [0:0] mode);

    reg [0:31] out_reg;

    always @(mode, a, b) begin 
       if (1'b1 == mode) begin
         out_reg[0:15] <= a[0:7] * b[0:7];
         out_reg[16:31] <= a[8:15] * b[8:15];
       end else begin
         out_reg <= a * b;
       end
    end

    assign out = out_reg;

endmodule
module frac_mult_16x16 (
	input [0:15] a,
	input [0:15] b,
	output [0:31] out,
    input [0:0] mode);


    reg [0:31] out_reg;

    always @(mode, a, b) begin 
       if (1'b1 == mode) begin
         out_reg[0:15] <= a[0:7] * b[0:7];
         out_reg[16:31] <= a[8:15] * b[8:15];
       end else begin
         out_reg <= a * b;
       end
    end

    assign out = out_reg;

endmodule