data/full_repos/permissive/143278/ivltests/pr1675789.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1675789.v:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'idx\' generates 32 bits.\n                                                                         : ... In instance main\n  array[0][idx*NIBBLE +: 4] = +idx;\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1675789.v:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s NEGATE generates 32 bits.\n                                                                         : ... In instance main\n  array[1][idx*NIBBLE +: 4] = -idx;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1675789.v:33: Operator NEQCASE expects 32 bits on the LHS, but LHS\'s VARREF \'word\' generates 4 bits.\n                                                                         : ... In instance main\n  if (word !== idx) begin\n           ^~~\n%Error: Exiting due to 3 warning(s)\n'
module main;

   parameter NIBBLE = 4;
   reg [NIBBLE*4-1:0] array [1:0];
   reg [3:0]  word;

   integer    idx;
   initial begin
      for (idx = 0 ; idx < 4 ;  idx = idx+1) begin
	 array[0][idx*NIBBLE +: 4] = +idx;
	 array[1][idx*NIBBLE +: 4] = -idx;
      end

      if (array[0] !== 16'h3210) begin
	 $display("FAILED -- array[0] = %h", array[0]);
	 $finish;
      end

      word = array[0][7:4];
      if (word !== 4'h1) begin
	 $display("FAILED == array[0][7:4] = %h", word);
	 $finish;
      end

      word = array[1][7:4];
      if (word !== 4'hf) begin
	 $display("FAILED == array[0][7:4] = %h", word);
	 $finish;
      end

      for (idx = 0 ;  idx < 4 ;  idx = idx+1) begin
	 word = array[0][idx*NIBBLE +: 4];
	 if (word !== idx) begin
	    $display("FAILED == array[0][nibble=%d] = %h", idx, word);
	    $finish;
	 end

	 word = array[1][idx*NIBBLE +: 4];
	 if (word !== - idx[3:0]) begin
	    $display("FAILED == array[1][nibble=%d] = %h", idx, word);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule
module main;


   parameter NIBBLE = 4;
   reg [NIBBLE*4-1:0] array [1:0];
   reg [3:0]  word;

   integer    idx;
   initial begin
      for (idx = 0 ; idx < 4 ;  idx = idx+1) begin
	 array[0][idx*NIBBLE +: 4] = +idx;
	 array[1][idx*NIBBLE +: 4] = -idx;
      end

      if (array[0] !== 16'h3210) begin
	 $display("FAILED -- array[0] = %h", array[0]);
	 $finish;
      end

      word = array[0][7:4];
      if (word !== 4'h1) begin
	 $display("FAILED == array[0][7:4] = %h", word);
	 $finish;
      end

      word = array[1][7:4];
      if (word !== 4'hf) begin
	 $display("FAILED == array[0][7:4] = %h", word);
	 $finish;
      end

      for (idx = 0 ;  idx < 4 ;  idx = idx+1) begin
	 word = array[0][idx*NIBBLE +: 4];
	 if (word !== idx) begin
	    $display("FAILED == array[0][nibble=%d] = %h", idx, word);
	    $finish;
	 end

	 word = array[1][idx*NIBBLE +: 4];
	 if (word !== - idx[3:0]) begin
	    $display("FAILED == array[1][nibble=%d] = %h", idx, word);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule