data/full_repos/permissive/174323821/hdl/sdram/jtframe_rom_sync.v
data/verilator_xmls/da2888b3-9715-4bad-a92b-72a20b376c21.xml
module jtframe_rom_sync(
    input       clk,
    input       rdy_in,
    input       ack_in,
    output      rdy_out,
    output      ack_out
);

reg last_rdy, last_ack;

assign rdy_out = rdy_in & last_rdy;
assign ack_out = ack_in & last_ack;

always @(posedge clk) begin
    last_rdy <= rdy_in;
    last_ack <= ack_in;
end

endmodule
module jtframe_rom_sync(
    input       clk,
    input       rdy_in,
    input       ack_in,
    output      rdy_out,
    output      ack_out
);


reg last_rdy, last_ack;

assign rdy_out = rdy_in & last_rdy;
assign ack_out = ack_in & last_ack;

always @(posedge clk) begin
    last_rdy <= rdy_in;
    last_ack <= ack_in;
end

endmodule