data/full_repos/permissive/193419875/src/ARMLEGvtf.v
 line:55: before: "input"
1: b'%Error: data/full_repos/permissive/193419875/src/ARMLEGvtf.v:3: Cannot find include file: ARMLEG.v\n`include "ARMLEG.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193419875/src,data/full_repos/permissive/193419875/ARMLEG.v\n             data/full_repos/permissive/193419875/src,data/full_repos/permissive/193419875/ARMLEG.v.v\n             data/full_repos/permissive/193419875/src,data/full_repos/permissive/193419875/ARMLEG.v.sv\n             ARMLEG.v\n             ARMLEG.v.v\n             ARMLEG.v.sv\n             obj_dir/ARMLEG.v\n             obj_dir/ARMLEG.v.v\n             obj_dir/ARMLEG.v.sv\n%Error: data/full_repos/permissive/193419875/src/ARMLEGvtf.v:4: Cannot find include file: Clock.v\n`include "Clock.v" \n         ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/193419875/src/ARMLEGvtf.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #0.01;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/193419875/src/ARMLEGvtf.v:21: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("ARMLEGvtf.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/193419875/src/ARMLEGvtf.v:22: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,ARMLEGvtf);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/193419875/src/ARMLEGvtf.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #2.5;\n  ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module ARMLEGvtf;
	wire CLOCK;
	reg RESET;

	Clock clock(CLOCK);

	ARMLEG ARMLEGv8(CLOCK, RESET);

	always @ ( RESET ) begin
		#0.01;
		RESET = ~RESET;
	end

	initial
	begin
		$dumpfile("ARMLEGvtf.vcd");
		$dumpvars(0,ARMLEGvtf);
		#2.5;
		RESET = 1;
	end
endmodule
module ARMLEGvtf;

	wire CLOCK;
	reg RESET;

	Clock clock(CLOCK);

	ARMLEG ARMLEGv8(CLOCK, RESET);

	always @ ( RESET ) begin
		#0.01;
		RESET = ~RESET;
	end

	initial
	begin
		$dumpfile("ARMLEGvtf.vcd");
		$dumpvars(0,ARMLEGvtf);
		#2.5;
		RESET = 1;
	end
endmodule