data/full_repos/permissive/102955443/reflectorEncode.v
1: b'%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:12: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   0 : val = "Y" - 8\'h41;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:13: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   1 : val = "R" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:14: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   2 : val = "U" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:15: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   3 : val = "H" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:16: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   4 : val = "Q" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:17: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   5 : val = "S" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:18: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   6 : val = "L" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:19: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   7 : val = "D" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:20: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   8 : val = "P" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:21: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   9 : val = "X" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:22: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   10: val = "N" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:23: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   11: val = "G" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:24: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   12: val = "O" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:25: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   13: val = "K" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:26: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   14: val = "M" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:27: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   15: val = "I" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:28: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   16: val = "E" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:29: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   17: val = "B" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:30: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   18: val = "F" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:31: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   19: val = "Z" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:32: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   20: val = "C" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:33: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   21: val = "W" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:34: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   22: val = "V" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:35: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   23: val = "J" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:36: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   24: val = "A" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:37: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   25: val = "T" - 8\'h41;  \n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:44: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   0 : val = "F" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:45: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   1 : val = "V" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:46: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   2 : val = "P" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:47: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   3 : val = "J" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:48: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   4 : val = "I" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:49: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   5 : val = "A" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:50: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   6 : val = "O" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:51: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   7 : val = "Y" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:52: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   8 : val = "E" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:53: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   9 : val = "D" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:54: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   10: val = "R" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:55: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   11: val = "Z" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:56: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   12: val = "X" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:57: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   13: val = "W" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:58: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   14: val = "G" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:59: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   15: val = "C" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:60: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   16: val = "T" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:61: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   17: val = "K" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:62: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   18: val = "U" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:63: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   19: val = "Q" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:64: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   20: val = "S" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:65: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   21: val = "B" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:66: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   22: val = "N" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:67: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   23: val = "M" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:68: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   24: val = "H" - 8\'h41;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:69: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                         : ... In instance reflectorEncode\n   25: val = "L" - 8\'h41;  \n           ^\n%Error: Exiting due to 52 warning(s)\n'
module reflectorEncode (code, val, reflector_type);
	input [4:0] code; 
	output reg [4:0] val;
	input reflector_type;

    always @*
    begin
	  if (reflector_type == 1'b0)
	  begin

		  case (code)
			0 : val = "Y" - 8'h41;
			1 : val = "R" - 8'h41;
			2 : val = "U" - 8'h41;
			3 : val = "H" - 8'h41;
			4 : val = "Q" - 8'h41;
			5 : val = "S" - 8'h41;
			6 : val = "L" - 8'h41;
			7 : val = "D" - 8'h41;
			8 : val = "P" - 8'h41;
			9 : val = "X" - 8'h41;
			10: val = "N" - 8'h41;
			11: val = "G" - 8'h41;
			12: val = "O" - 8'h41;
			13: val = "K" - 8'h41;
			14: val = "M" - 8'h41;
			15: val = "I" - 8'h41;
			16: val = "E" - 8'h41;
			17: val = "B" - 8'h41;
			18: val = "F" - 8'h41;
			19: val = "Z" - 8'h41;
			20: val = "C" - 8'h41;
			21: val = "W" - 8'h41;
			22: val = "V" - 8'h41;
			23: val = "J" - 8'h41;
			24: val = "A" - 8'h41;
			25: val = "T" - 8'h41;		
		  endcase
	  end
	  else
	  begin

	  	case (code)
			0 : val = "F" - 8'h41;
			1 : val = "V" - 8'h41;
			2 : val = "P" - 8'h41;
			3 : val = "J" - 8'h41;
			4 : val = "I" - 8'h41;
			5 : val = "A" - 8'h41;
			6 : val = "O" - 8'h41;
			7 : val = "Y" - 8'h41;
			8 : val = "E" - 8'h41;
			9 : val = "D" - 8'h41;
			10: val = "R" - 8'h41;
			11: val = "Z" - 8'h41;
			12: val = "X" - 8'h41;
			13: val = "W" - 8'h41;
			14: val = "G" - 8'h41;
			15: val = "C" - 8'h41;
			16: val = "T" - 8'h41;
			17: val = "K" - 8'h41;
			18: val = "U" - 8'h41;
			19: val = "Q" - 8'h41;
			20: val = "S" - 8'h41;
			21: val = "B" - 8'h41;
			22: val = "N" - 8'h41;
			23: val = "M" - 8'h41;
			24: val = "H" - 8'h41;
			25: val = "L" - 8'h41;		
		  endcase
	  end
    end 
endmodule
module reflectorEncode (code, val, reflector_type);

	input [4:0] code; 
	output reg [4:0] val;
	input reflector_type;

    always @*
    begin
	  if (reflector_type == 1'b0)
	  begin

		  case (code)
			0 : val = "Y" - 8'h41;
			1 : val = "R" - 8'h41;
			2 : val = "U" - 8'h41;
			3 : val = "H" - 8'h41;
			4 : val = "Q" - 8'h41;
			5 : val = "S" - 8'h41;
			6 : val = "L" - 8'h41;
			7 : val = "D" - 8'h41;
			8 : val = "P" - 8'h41;
			9 : val = "X" - 8'h41;
			10: val = "N" - 8'h41;
			11: val = "G" - 8'h41;
			12: val = "O" - 8'h41;
			13: val = "K" - 8'h41;
			14: val = "M" - 8'h41;
			15: val = "I" - 8'h41;
			16: val = "E" - 8'h41;
			17: val = "B" - 8'h41;
			18: val = "F" - 8'h41;
			19: val = "Z" - 8'h41;
			20: val = "C" - 8'h41;
			21: val = "W" - 8'h41;
			22: val = "V" - 8'h41;
			23: val = "J" - 8'h41;
			24: val = "A" - 8'h41;
			25: val = "T" - 8'h41;		
		  endcase
	  end
	  else
	  begin

	  	case (code)
			0 : val = "F" - 8'h41;
			1 : val = "V" - 8'h41;
			2 : val = "P" - 8'h41;
			3 : val = "J" - 8'h41;
			4 : val = "I" - 8'h41;
			5 : val = "A" - 8'h41;
			6 : val = "O" - 8'h41;
			7 : val = "Y" - 8'h41;
			8 : val = "E" - 8'h41;
			9 : val = "D" - 8'h41;
			10: val = "R" - 8'h41;
			11: val = "Z" - 8'h41;
			12: val = "X" - 8'h41;
			13: val = "W" - 8'h41;
			14: val = "G" - 8'h41;
			15: val = "C" - 8'h41;
			16: val = "T" - 8'h41;
			17: val = "K" - 8'h41;
			18: val = "U" - 8'h41;
			19: val = "Q" - 8'h41;
			20: val = "S" - 8'h41;
			21: val = "B" - 8'h41;
			22: val = "N" - 8'h41;
			23: val = "M" - 8'h41;
			24: val = "H" - 8'h41;
			25: val = "L" - 8'h41;		
		  endcase
	  end
    end 
endmodule