data/full_repos/permissive/143344034/hdl/anton_ram_2port_raddreg.v
 line:64: before: "localparam"
1: b'%Error: data/full_repos/permissive/143344034/hdl/anton_ram_2port_raddreg.v:1: Cannot find include file: anton_common.vh\n`include "anton_common.vh" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143344034/hdl,data/full_repos/permissive/143344034/anton_common.vh\n             data/full_repos/permissive/143344034/hdl,data/full_repos/permissive/143344034/anton_common.vh.v\n             data/full_repos/permissive/143344034/hdl,data/full_repos/permissive/143344034/anton_common.vh.sv\n             anton_common.vh\n             anton_common.vh.v\n             anton_common.vh.sv\n             obj_dir/anton_common.vh\n             obj_dir/anton_common.vh.v\n             obj_dir/anton_common.vh.sv\n%Error: data/full_repos/permissive/143344034/hdl/anton_ram_2port_raddreg.v:8: Define or directive not defined: \'`BUFFER_END_DEFAULT\'\n  parameter  BUFFER_END  = `BUFFER_END_DEFAULT,   \n                           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_ram_2port_raddreg.v:8: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  parameter  BUFFER_END  = `BUFFER_END_DEFAULT,   \n                                              ^\n%Error: data/full_repos/permissive/143344034/hdl/anton_ram_2port_raddreg.v:9: Define or directive not defined: \'`CLOG2\'\n  localparam BUFFER_BITS = `CLOG2(BUFFER_END+1)   \n                           ^~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_ram_2port_raddreg.v:10: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/143344034/hdl/anton_ram_2port_raddreg.v:26: syntax error, unexpected always\nalways@ (posedge clk)\n^~~~~~\n%Error: Exiting due to 6 error(s)\n'
module anton_ram_2port_raddreg #(
  parameter  BUFFER_END  = `BUFFER_END_DEFAULT,
  localparam BUFFER_BITS = `CLOG2(BUFFER_END+1)
)(
  input                    clk,

  input  [BUFFER_BITS-1:0] rAddr,
  output [7:0]             dOut,

  input                    wr,
  input  [BUFFER_BITS-1:0] wAddr,
  input  [7:0]             dIn
);

reg [BUFFER_BITS-1:0] raddr_reg;
reg [7:0]             mem [0:BUFFER_END-1];
reg [7:0]             dOut;
reg [7:0]             dOutB;

always@ (posedge clk)
begin
  raddr_reg <= rAddr;
  dOutB <= mem[raddr_reg];
  if (wr)
    mem[wAddr] <= dIn;
end

always@ (posedge clk)
begin
  dOut <= dOutB;
end


endmodule
module anton_ram_2port_raddreg #(
  parameter  BUFFER_END  = `BUFFER_END_DEFAULT,
  localparam BUFFER_BITS = `CLOG2(BUFFER_END+1)
)(
  input                    clk,

  input  [BUFFER_BITS-1:0] rAddr,
  output [7:0]             dOut,

  input                    wr,
  input  [BUFFER_BITS-1:0] wAddr,
  input  [7:0]             dIn
);


reg [BUFFER_BITS-1:0] raddr_reg;
reg [7:0]             mem [0:BUFFER_END-1];
reg [7:0]             dOut;
reg [7:0]             dOutB;

always@ (posedge clk)
begin
  raddr_reg <= rAddr;
  dOutB <= mem[raddr_reg];
  if (wr)
    mem[wAddr] <= dIn;
end

always@ (posedge clk)
begin
  dOut <= dOutB;
end


endmodule