data/full_repos/permissive/180217218/fpga/test.v
 line:50: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/180217218/fpga/test.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #42; forever #42 clk = !clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/180217218/fpga/test.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #42; forever #42 clk = !clk;\n               ^\n%Error: data/full_repos/permissive/180217218/fpga/test.v:55: Unsupported: wait statements\n   wait(cts == 0);\n   ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/180217218/fpga/test.v:57: Unsupported: Ignoring delay on this delayed statement.\n   #baud_delay;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/180217218/fpga/test.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #baud_delay;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/180217218/fpga/test.v:63: Unsupported: Ignoring delay on this delayed statement.\n   #baud_delay;\n   ^\n%Error: data/full_repos/permissive/180217218/fpga/test.v:72: syntax error, unexpected \'@\'\n   @(negedge rx);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/180217218/fpga/test.v:73: Unsupported: Ignoring delay on this delayed statement.\n   #(3*baud_delay/2);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/180217218/fpga/test.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #baud_delay;\n    ^\n%Error: data/full_repos/permissive/180217218/fpga/test.v:85: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.lx2");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/180217218/fpga/test.v:86: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/180217218/fpga/test.v:89: syntax error, unexpected \'@\'\n  repeat(1000) @(posedge clk);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/180217218/fpga/test.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #1000000;\n  ^\n%Error: data/full_repos/permissive/180217218/fpga/test.v:97: syntax error, unexpected \'@\'\n  repeat(10000) @(posedge clk);\n                ^\n%Error: Exiting due to 6 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

	localparam baud_delay = 500;

	reg clk = 0;
	wire [4:0] led;
	
	reg tx = 1;
	wire rx;
	reg rts = 0;
	wire cts;
	

	initial
	begin
		#42; forever #42 clk = !clk;
	end
	

	Top uut (
		.clk(clk),
		.led(led),
		.uart_rx(tx),
		.uart_tx(rx),
		.uart_rts(rts),
		.uart_cts(cts)
	);

	task usart_send (
		input [7:0] data
	);
		integer i;
		begin
			wait(cts == 0);
			tx <= 0;
			#baud_delay;
			for (i = 0; i < 8; i=i+1) begin
				tx <= data[i];
				#baud_delay;
			end
			tx <= 1;
			#baud_delay;
		end
	endtask
	
	task usart_recv (
		output [7:0] data
	);
		integer i;
		begin
			@(negedge rx);
			#(3*baud_delay/2);
			for (i = 0; i < 8; i=i+1) begin
				data[i] <= rx;
				#baud_delay;
			end
		end
	endtask


	integer k;
	initial
	begin
		$dumpfile("dump.lx2");
		$dumpvars;
		$display("start");

		repeat(1000) @(posedge clk);
		for(k = 0; k < 3; k=k+1) begin
			usart_send(k);
		end
		#1000000;
		for(k = 0; k < 3; k=k+1) begin
			usart_send(k);
		end
		repeat(10000) @(posedge clk);

		$display("done");
		$finish;
	end
endmodule
module test;


	localparam baud_delay = 500;

	reg clk = 0;
	wire [4:0] led;
	
	reg tx = 1;
	wire rx;
	reg rts = 0;
	wire cts;
	

	initial
	begin
		#42; forever #42 clk = !clk;
	end
	

	Top uut (
		.clk(clk),
		.led(led),
		.uart_rx(tx),
		.uart_tx(rx),
		.uart_rts(rts),
		.uart_cts(cts)
	);

	task usart_send (
		input [7:0] data
	);
		integer i;
		begin
			wait(cts == 0);
			tx <= 0;
			#baud_delay;
			for (i = 0; i < 8; i=i+1) begin
				tx <= data[i];
				#baud_delay;
			end
			tx <= 1;
			#baud_delay;
		end
	endtask
	
	task usart_recv (
		output [7:0] data
	);
		integer i;
		begin
			@(negedge rx);
			#(3*baud_delay/2);
			for (i = 0; i < 8; i=i+1) begin
				data[i] <= rx;
				#baud_delay;
			end
		end
	endtask


	integer k;
	initial
	begin
		$dumpfile("dump.lx2");
		$dumpvars;
		$display("start");

		repeat(1000) @(posedge clk);
		for(k = 0; k < 3; k=k+1) begin
			usart_send(k);
		end
		#1000000;
		for(k = 0; k < 3; k=k+1) begin
			usart_send(k);
		end
		repeat(10000) @(posedge clk);

		$display("done");
		$finish;
	end
endmodule