data/full_repos/permissive/214823094/lab_2/project_1/project_1.srcs/sources_1/new/BCD_7_segment_display.v
data/verilator_xmls/75cec3d4-1df4-46e5-892f-01512258ee10.xml
module BCD_7_segment_display(
    input [3:0] swt,
    output reg [6:0] C,
    output [7:0] AN
    );
    

    assign AN[0]=0;
    assign AN[1]=1;
    assign AN[2]=1;
    assign AN[3]=1;
    assign AN[4]=1;
    assign AN[5]=1;
    assign AN[6]=1;
    assign AN[7]=1;
    

    always@(swt)
    begin
    case(swt)
    4'b0000:C=7'b0000001;
    4'b0001:C=7'b1001111;
    4'b0010:C=7'b0010010;
    4'b0011:C=7'b0000110;
    4'b0100:C=7'b1001100;
    4'b0101:C=7'b0100100;
    4'b0110:C=7'b0100000;
    4'b0111:C=7'b0001111;
    4'b1000:C=7'b0000000;

    4'b1001:C=7'b0001100;







    default:C=7'b1111111;
    endcase
    end
    
endmodule
module BCD_7_segment_display(
    input [3:0] swt,
    output reg [6:0] C,
    output [7:0] AN
    );

    

    assign AN[0]=0;
    assign AN[1]=1;
    assign AN[2]=1;
    assign AN[3]=1;
    assign AN[4]=1;
    assign AN[5]=1;
    assign AN[6]=1;
    assign AN[7]=1;
    

    always@(swt)
    begin
    case(swt)
    4'b0000:C=7'b0000001;
    4'b0001:C=7'b1001111;
    4'b0010:C=7'b0010010;
    4'b0011:C=7'b0000110;
    4'b0100:C=7'b1001100;
    4'b0101:C=7'b0100100;
    4'b0110:C=7'b0100000;
    4'b0111:C=7'b0001111;
    4'b1000:C=7'b0000000;

    4'b1001:C=7'b0001100;







    default:C=7'b1111111;
    endcase
    end
    
endmodule