data/full_repos/permissive/159902111/PCPU_experiment/RF.v
1: b'%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/RF.v:23: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                            : ... In instance RF\n        for (i = 1\'b0; i < 32; i = i+1)\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_experiment/RF.v:30: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'wa_i\' generates 5 bits.\n                                                                            : ... In instance RF\n            Regfile[wa_i] = (!wa_i)? 32\'h0 : wd_i; \n                             ^\n%Error: Exiting due to 2 warning(s)\n'
module RF(
  input clk,
  input rst,
  input RegWrite_i,
  input [4:0]wa_i,
  input [4:0]ra1_i,
  input [4:0]ra2_i,
  input [31:0]wd_i,
  
  output [31:0]rd1_o,
  output [31:0]rd2_o
  );
  
  reg [31:0] Regfile [31:0];
  reg [31:0] rd1, rd2;
  integer    i;
  
  always@(posedge clk or posedge rst)
  begin
    if (rst)
      begin
        for (i = 1'b0; i < 32; i = i+1)
          Regfile[i] = 32'h0;
      end
    else
      begin
        if (RegWrite_i)
          begin
            Regfile[wa_i] = (!wa_i)? 32'h0 : wd_i;
            $display("R[00-07]=%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X", Regfile[0], Regfile[1], Regfile[2], Regfile[3], Regfile[4], Regfile[5], Regfile[6], Regfile[7]);
            $display("R[08-15]=%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X", Regfile[8], Regfile[9], Regfile[10], Regfile[11], Regfile[12], Regfile[13], Regfile[14], Regfile[15]);
            $display("R[16-23]=%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X", Regfile[16], Regfile[17], Regfile[18], Regfile[19], Regfile[20], Regfile[21], Regfile[22], Regfile[23]);
            $display("R[24-31]=%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X", Regfile[24], Regfile[25], Regfile[26], Regfile[27], Regfile[28], Regfile[29], Regfile[30], Regfile[31]);
          end
      end

  end


  always@(*)
  begin
    if (wa_i == ra1_i && RegWrite_i)
      rd1 = wd_i;
    else rd1 = Regfile[ra1_i];
    if (wa_i == ra2_i && RegWrite_i)
      rd2 = wd_i;
    else rd2 = Regfile[ra2_i];
  end
  assign rd1_o = rd1;
  assign rd2_o = rd2;
endmodule
module RF(
  input clk,
  input rst,
  input RegWrite_i,
  input [4:0]wa_i,
  input [4:0]ra1_i,
  input [4:0]ra2_i,
  input [31:0]wd_i,
  
  output [31:0]rd1_o,
  output [31:0]rd2_o
  );

  
  reg [31:0] Regfile [31:0];
  reg [31:0] rd1, rd2;
  integer    i;
  
  always@(posedge clk or posedge rst)
  begin
    if (rst)
      begin
        for (i = 1'b0; i < 32; i = i+1)
          Regfile[i] = 32'h0;
      end
    else
      begin
        if (RegWrite_i)
          begin
            Regfile[wa_i] = (!wa_i)? 32'h0 : wd_i;
            $display("R[00-07]=%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X", Regfile[0], Regfile[1], Regfile[2], Regfile[3], Regfile[4], Regfile[5], Regfile[6], Regfile[7]);
            $display("R[08-15]=%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X", Regfile[8], Regfile[9], Regfile[10], Regfile[11], Regfile[12], Regfile[13], Regfile[14], Regfile[15]);
            $display("R[16-23]=%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X", Regfile[16], Regfile[17], Regfile[18], Regfile[19], Regfile[20], Regfile[21], Regfile[22], Regfile[23]);
            $display("R[24-31]=%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X", Regfile[24], Regfile[25], Regfile[26], Regfile[27], Regfile[28], Regfile[29], Regfile[30], Regfile[31]);
          end
      end

  end


  always@(*)
  begin
    if (wa_i == ra1_i && RegWrite_i)
      rd1 = wd_i;
    else rd1 = Regfile[ra1_i];
    if (wa_i == ra2_i && RegWrite_i)
      rd2 = wd_i;
    else rd2 = Regfile[ra2_i];
  end
  assign rd1_o = rd1;
  assign rd2_o = rd2;
endmodule