data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v
 line:11: before: ";"
1: b'%Error: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:11: Unsupported: event data types\n    event error;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #100 $stop;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:21: syntax error, unexpected ->\n            ->error;\n            ^~\n%Warning-STMTDLY: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #100; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #100; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #100; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #100; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150642927/VerilogSrc/Simulators/multiply_and_add_simulator.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: Exiting due to 2 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multiply_and_add_simulator();

    event error;
    always @ (error) begin
        $display("ERROR at time %t", $time);
        #100 $stop;
    end

    task check_output(input [`DATA_WIDTH*2-1:0] result, input [`DATA_WIDTH*2-1:0] golden);
    begin
        if (result!==golden) begin
            $display("Output is %0d which should be %0d instead!", result[`DATA_WIDTH*2-1:0], golden[`DATA_WIDTH*2-1:0]);
            ->error;
        end
    end
    endtask
    
    reg [`DATA_WIDTH*2-1:0] add_value;
    reg [`DATA_WIDTH-1:0] input_value;
    reg [7:0] weight_value;
    wire [`DATA_WIDTH*2-1:0] output_value;
    
    multiply_and_add #(
        .DATA_WIDTH(`DATA_WIDTH)
    ) uut (
        .add_value(add_value),
        .input_value(input_value),
        .weight_value(weight_value),
        .output_value(output_value)
    );
    
    initial begin
        add_value = 0;
        input_value = 0;
        weight_value = 0;
    end
    
    initial begin
        #100; 
        check_output(output_value, 16'd0);
        #100; 
        add_value = 16'd1;
        #10;
        check_output(output_value, 16'd1);
        #100; 
        input_value = 8'd2;
        #10;
        check_output(output_value, 16'd1);
        #100; 
        weight_value = 8'd3;
        #10;
        check_output(output_value, 16'd7);
        #100;
        add_value = 16'd10;
        input_value = 8'd5;
        weight_value = 8'd2;
        #10;
        check_output(output_value, 16'd20);
        #100;
        add_value = 16'd10;
        input_value = 8'd255;
        weight_value = 8'd6;
        #10;
        check_output(output_value, 16'd4);
        $display("SUCCESSFUL TEST!"); 
        $stop;
    end

endmodule
module multiply_and_add_simulator();


    event error;
    always @ (error) begin
        $display("ERROR at time %t", $time);
        #100 $stop;
    end

    task check_output(input [`DATA_WIDTH*2-1:0] result, input [`DATA_WIDTH*2-1:0] golden);
    begin
        if (result!==golden) begin
            $display("Output is %0d which should be %0d instead!", result[`DATA_WIDTH*2-1:0], golden[`DATA_WIDTH*2-1:0]);
            ->error;
        end
    end
    endtask
    
    reg [`DATA_WIDTH*2-1:0] add_value;
    reg [`DATA_WIDTH-1:0] input_value;
    reg [7:0] weight_value;
    wire [`DATA_WIDTH*2-1:0] output_value;
    
    multiply_and_add #(
        .DATA_WIDTH(`DATA_WIDTH)
    ) uut (
        .add_value(add_value),
        .input_value(input_value),
        .weight_value(weight_value),
        .output_value(output_value)
    );
    
    initial begin
        add_value = 0;
        input_value = 0;
        weight_value = 0;
    end
    
    initial begin
        #100; 
        check_output(output_value, 16'd0);
        #100; 
        add_value = 16'd1;
        #10;
        check_output(output_value, 16'd1);
        #100; 
        input_value = 8'd2;
        #10;
        check_output(output_value, 16'd1);
        #100; 
        weight_value = 8'd3;
        #10;
        check_output(output_value, 16'd7);
        #100;
        add_value = 16'd10;
        input_value = 8'd5;
        weight_value = 8'd2;
        #10;
        check_output(output_value, 16'd20);
        #100;
        add_value = 16'd10;
        input_value = 8'd255;
        weight_value = 8'd6;
        #10;
        check_output(output_value, 16'd4);
        $display("SUCCESSFUL TEST!"); 
        $stop;
    end

endmodule