data/full_repos/permissive/111433415/verilog/03_combinacionales/03-1_florencio/florencio.v
data/verilator_xmls/132d4b06-1559-4b27-99c9-8cde0894c082.xml
module test ();

    reg a = 0, b = 0, c = 0, d = 0;
    wire f;

    florencio uut(f, a, b, c, d);

    initial begin

        $display("d c b a | f");
        $monitor("%b %b %b %b | %b", d, c, b, a, f);






        #(16 * `BTIME) $finish;
    end

    always
        #(`BTIME) a = ~a;
    always
        #(2 * `BTIME) b = ~b;
    always
        #(4 * `BTIME) c = ~c;
    always
        #(8 * `BTIME) d = ~d;
endmodule
module test ();


    reg a = 0, b = 0, c = 0, d = 0;
    wire f;

    florencio uut(f, a, b, c, d);

    initial begin

        $display("d c b a | f");
        $monitor("%b %b %b %b | %b", d, c, b, a, f);






        #(16 * `BTIME) $finish;
    end

    always
        #(`BTIME) a = ~a;
    always
        #(2 * `BTIME) b = ~b;
    always
        #(4 * `BTIME) c = ~c;
    always
        #(8 * `BTIME) d = ~d;
endmodule