data/full_repos/permissive/121041165/vm1801mini/vm1_alib.v
1: b"%Error: data/full_repos/permissive/121041165/vm1801mini/vm1_alib.v:68: Cannot find file containing module: 'BRAM_TDP_MACRO'\n   BRAM_TDP_MACRO #(\n   ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/121041165/vm1801mini,data/full_repos/permissive/121041165/BRAM_TDP_MACRO\n             data/full_repos/permissive/121041165/vm1801mini,data/full_repos/permissive/121041165/BRAM_TDP_MACRO.v\n             data/full_repos/permissive/121041165/vm1801mini,data/full_repos/permissive/121041165/BRAM_TDP_MACRO.sv\n             BRAM_TDP_MACRO\n             BRAM_TDP_MACRO.v\n             BRAM_TDP_MACRO.sv\n             obj_dir/BRAM_TDP_MACRO\n             obj_dir/BRAM_TDP_MACRO.v\n             obj_dir/BRAM_TDP_MACRO.sv\n%Error: Exiting due to 1 error(s)\n"
module vm1_aram(
	input	[5:0]address_a,
	input	[5:0]address_b,
	input	[1:0]byteena_a,
	input clock,
	input	[15:0]data_a,
	input	[15:0]data_b,
	input wren_a,
	input wren_b,
	output	[15:0]q_a,
	output	[15:0]q_b
);

wire [8:0]addr_a = {3'b000, address_a};
wire [8:0]addr_b = {3'b000, address_b};
wire [1:0]WEA = {2{wren_a}} & byteena_a;
wire [1:0]WEB = {2{wren_b}};













   
















   BRAM_TDP_MACRO #(
      .BRAM_SIZE("9Kb"),
      .DEVICE("SPARTAN6"),
      .DOA_REG(0),
      .DOB_REG(0),
      .INIT_A(36'h0000000),
      .INIT_B(36'h00000000),
      .INIT_FILE ("NONE"),
      .READ_WIDTH_A (16),
      .READ_WIDTH_B (16),
      .SIM_COLLISION_CHECK ("ALL"),

      .SRVAL_A(36'h00000000),
      .SRVAL_B(36'h00000000),
      .WRITE_MODE_A("WRITE_FIRST"),
      .WRITE_MODE_B("WRITE_FIRST"),
      .WRITE_WIDTH_A(16),
      .WRITE_WIDTH_B(16),
      .INIT_00(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
      .INIT_01(256'h0000_0000_0000_001C_E002_0040_0014_00B8_E00A_0018_FFCE_0004_000C_0008_0010_E006),
      .INIT_02(256'h0000_0008_FF00_0000_0010_FFBE_8000_0000_0001_FFFF_FFCE_0000_0002_0000_00E0_0000),
      .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
            

      .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000)
   ) BRAM_TDP_MACRO_inst (
      .DOA(q_a),
      .DOB(q_b),
      .ADDRA(addr_a),
      .ADDRB(addr_b),
      .CLKA(clock),
      .CLKB(clock),
      .DIA(data_a),
      .DIB(data_b),
      .ENA(1'b1),
      .ENB(1'b1),
      .REGCEA(1'b0),
      .REGCEB(1'b0),
      .RSTA(1'b0),
      .RSTB(1'b0),
      .WEA(WEA),
      .WEB(WEB)
   );


endmodule
module vm1_aram(
	input	[5:0]address_a,
	input	[5:0]address_b,
	input	[1:0]byteena_a,
	input clock,
	input	[15:0]data_a,
	input	[15:0]data_b,
	input wren_a,
	input wren_b,
	output	[15:0]q_a,
	output	[15:0]q_b
);


wire [8:0]addr_a = {3'b000, address_a};
wire [8:0]addr_b = {3'b000, address_b};
wire [1:0]WEA = {2{wren_a}} & byteena_a;
wire [1:0]WEB = {2{wren_b}};













   
















   BRAM_TDP_MACRO #(
      .BRAM_SIZE("9Kb"),
      .DEVICE("SPARTAN6"),
      .DOA_REG(0),
      .DOB_REG(0),
      .INIT_A(36'h0000000),
      .INIT_B(36'h00000000),
      .INIT_FILE ("NONE"),
      .READ_WIDTH_A (16),
      .READ_WIDTH_B (16),
      .SIM_COLLISION_CHECK ("ALL"),

      .SRVAL_A(36'h00000000),
      .SRVAL_B(36'h00000000),
      .WRITE_MODE_A("WRITE_FIRST"),
      .WRITE_MODE_B("WRITE_FIRST"),
      .WRITE_WIDTH_A(16),
      .WRITE_WIDTH_B(16),
      .INIT_00(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
      .INIT_01(256'h0000_0000_0000_001C_E002_0040_0014_00B8_E00A_0018_FFCE_0004_000C_0008_0010_E006),
      .INIT_02(256'h0000_0008_FF00_0000_0010_FFBE_8000_0000_0001_FFFF_FFCE_0000_0002_0000_00E0_0000),
      .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
            

      .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000)
   ) BRAM_TDP_MACRO_inst (
      .DOA(q_a),
      .DOB(q_b),
      .ADDRA(addr_a),
      .ADDRB(addr_b),
      .CLKA(clock),
      .CLKB(clock),
      .DIA(data_a),
      .DIB(data_b),
      .ENA(1'b1),
      .ENB(1'b1),
      .REGCEA(1'b0),
      .REGCEB(1'b0),
      .RSTA(1'b0),
      .RSTB(1'b0),
      .WEA(WEA),
      .WEB(WEB)
   );


endmodule