data/full_repos/permissive/158984095/Homework1/Question2/answer1_2_tb.v
1: b'%Error: data/full_repos/permissive/158984095/Homework1/Question2/answer1_2_tb.v:7: Unsupported or unknown PLI call: $monitor\n$monitor($time,"input is %b \\t c0 is %b \\t c1 is %b \\t sum is %b \\n",in[4:0],c0,c1,sum);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/Question2/answer1_2_tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/Question2/answer1_2_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/Question2/answer1_2_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework1/Question2/answer1_2_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module carrysave_4is2_tb;
reg [4:0] in;
wire c0,c1,sum;
carrysave_4is2 carrysave_tb(in[4:0],c0,c1,sum);
initial
begin
$monitor($time,"input is %b \t c0 is %b \t c1 is %b \t sum is %b \n",in[4:0],c0,c1,sum);
#50;
in[4:0] = 10110;
#50
in[4:0] = 00000;
#50;
in[4:0] = 10001;
#50;
in[4:0] = 00101;
end
endmodule
module carrysave_4is2_tb;

reg [4:0] in;
wire c0,c1,sum;
carrysave_4is2 carrysave_tb(in[4:0],c0,c1,sum);
initial
begin
$monitor($time,"input is %b \t c0 is %b \t c1 is %b \t sum is %b \n",in[4:0],c0,c1,sum);
#50;
in[4:0] = 10110;
#50
in[4:0] = 00000;
#50;
in[4:0] = 10001;
#50;
in[4:0] = 00101;
end
endmodule