data/full_repos/permissive/161275071/video/lspc2_a2.v
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1: b'%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:132: Signal definition not found, creating implicitly: \'LSPC_3M\'\n                                                                            : ... Suggested alternative: \'LSPC_4M\'\n assign S1H1 = LSPC_3M;\n               ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:133: Signal definition not found, creating implicitly: \'LSPC_1_5M\'\n                                                                            : ... Suggested alternative: \'LSPC_3M\'\n assign S2H1 = LSPC_1_5M;\n               ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:146: Signal definition not found, creating implicitly: \'T160A_OUT\'\n  PCK1 <= T160A_OUT;\n          ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:149: Signal definition not found, creating implicitly: \'T160B_OUT\'\n                                                                            : ... Suggested alternative: \'T160A_OUT\'\n  PCK2 <= T160B_OUT;\n          ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:152: Signal definition not found, creating implicitly: \'SPR_TILE_HFLIP\'\n                                                                            : ... Suggested alternative: \'SPR_TILEMAP\'\n   T172_Q <= SPR_TILE_HFLIP;\n             ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:161: Signal definition not found, creating implicitly: \'nEVEN_ODD\'\n assign U105A_OUT = ~&{nHSHRINK_OUT_A, nHSHRINK_OUT_B, nEVEN_ODD};\n                                                       ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:161: Signal definition not found, creating implicitly: \'U105A_OUT\'\n                                                                            : ... Suggested alternative: \'T160A_OUT\'\n assign U105A_OUT = ~&{nHSHRINK_OUT_A, nHSHRINK_OUT_B, nEVEN_ODD};\n        ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:162: Signal definition not found, creating implicitly: \'EVEN_nODD\'\n                                                                            : ... Suggested alternative: \'nEVEN_ODD\'\n assign U107_OUT = ~&{nHSHRINK_OUT_A, EVEN_nODD, HSHRINK_OUT_B};\n                                      ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:162: Signal definition not found, creating implicitly: \'HSHRINK_OUT_B\'\n                                                                            : ... Suggested alternative: \'nHSHRINK_OUT_B\'\n assign U107_OUT = ~&{nHSHRINK_OUT_A, EVEN_nODD, HSHRINK_OUT_B};\n                                                 ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:162: Signal definition not found, creating implicitly: \'U107_OUT\'\n                                                                            : ... Suggested alternative: \'U105A_OUT\'\n assign U107_OUT = ~&{nHSHRINK_OUT_A, EVEN_nODD, HSHRINK_OUT_B};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:163: Signal definition not found, creating implicitly: \'HSHRINK_OUT_A\'\n                                                                            : ... Suggested alternative: \'HSHRINK_OUT_B\'\n assign U109_OUT = ~&{HSHRINK_OUT_A, nEVEN_ODD};\n                      ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:163: Signal definition not found, creating implicitly: \'U109_OUT\'\n                                                                            : ... Suggested alternative: \'U107_OUT\'\n assign U109_OUT = ~&{HSHRINK_OUT_A, nEVEN_ODD};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:164: Signal definition not found, creating implicitly: \'U112_OUT\'\n                                                                            : ... Suggested alternative: \'U107_OUT\'\n assign U112_OUT = ~&{U105A_OUT, U107_OUT, U109_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:169: Signal definition not found, creating implicitly: \'nCHAINED\'\n assign nPARITY_INIT = ~&{nCHAINED, S53A_OUT};  \n                          ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:169: Signal definition not found, creating implicitly: \'S53A_OUT\'\n assign nPARITY_INIT = ~&{nCHAINED, S53A_OUT};  \n                                    ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:169: Signal definition not found, creating implicitly: \'nPARITY_INIT\'\n assign nPARITY_INIT = ~&{nCHAINED, S53A_OUT};  \n        ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:170: Signal definition not found, creating implicitly: \'nXPOS_ZERO\'\n assign nXPOS_ZERO = ~PIPE_C[0];\n        ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:171: Signal definition not found, creating implicitly: \'S58A_OUT\'\n                                                                            : ... Suggested alternative: \'S53A_OUT\'\n assign S58A_OUT = ~|{nXPOS_ZERO, nPARITY_INIT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:172: Signal definition not found, creating implicitly: \'ONE_PIXEL\'\n assign ONE_PIXEL = HSHRINK_OUT_A ^ HSHRINK_OUT_B;  \n        ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:173: Signal definition not found, creating implicitly: \'U72_OUT\'\n                                                                            : ... Suggested alternative: \'U112_OUT\'\n assign U72_OUT = ONE_PIXEL ^ nEVEN_ODD;\n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:174: Signal definition not found, creating implicitly: \'U57B_OUT\'\n                                                                            : ... Suggested alternative: \'U72_OUT\'\n assign U57B_OUT = nPARITY_INIT & U72_OUT;\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:175: Signal definition not found, creating implicitly: \'U56A_OUT\'\n                                                                            : ... Suggested alternative: \'S53A_OUT\'\n assign U56A_OUT = ~|{S58A_OUT, U57B_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:184: Signal definition not found, creating implicitly: \'WR_VRAM_RW\'\n assign C22A_OUT = ~&{WR_VRAM_RW, WR_VRAM_ADDR};\n                      ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:184: Signal definition not found, creating implicitly: \'WR_VRAM_ADDR\'\n                                                                            : ... Suggested alternative: \'FVRAM_ADDR\'\n assign C22A_OUT = ~&{WR_VRAM_RW, WR_VRAM_ADDR};\n                                  ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:184: Signal definition not found, creating implicitly: \'C22A_OUT\'\n assign C22A_OUT = ~&{WR_VRAM_RW, WR_VRAM_ADDR};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:196: Signal definition not found, creating implicitly: \'VRAM_ADDR_UPD_TYPE\'\n assign VRAM_ADDR_MUX = VRAM_ADDR_UPD_TYPE ? VRAM_ADDR_AUTOINC : REG_VRAMADDR;\n                        ^~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:202: Signal definition not found, creating implicitly: \'D112B_OUT\'\n                                                                            : ... Suggested alternative: \'U112_OUT\'\n  D112B_OUT_DELAY <= D112B_OUT;\n                     ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:212: Signal definition not found, creating implicitly: \'nCPU_WR_HIGH\'\n assign O108B_OUT = ~&{nCPU_WR_HIGH, nCPU_WR_LOW};\n                       ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:212: Signal definition not found, creating implicitly: \'nCPU_WR_LOW\'\n                                                                            : ... Suggested alternative: \'nCPU_WR_HIGH\'\n assign O108B_OUT = ~&{nCPU_WR_HIGH, nCPU_WR_LOW};\n                                     ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:212: Signal definition not found, creating implicitly: \'O108B_OUT\'\n                                                                            : ... Suggested alternative: \'D112B_OUT\'\n assign O108B_OUT = ~&{nCPU_WR_HIGH, nCPU_WR_LOW};\n        ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:223: Signal definition not found, creating implicitly: \'LSPOE_SEQA\'\n assign B71_OUT = ~&{~LSPOE, LSPOE_SEQA};\n                             ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:223: Signal definition not found, creating implicitly: \'B71_OUT\'\n                                                                            : ... Suggested alternative: \'U72_OUT\'\n assign B71_OUT = ~&{~LSPOE, LSPOE_SEQA};\n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:225: Signal definition not found, creating implicitly: \'LSPOE_SEQB\'\n                                                                            : ... Suggested alternative: \'LSPOE_SEQA\'\n assign B75A_OUT = ~&{~LSPOE, LSPOE_SEQB};\n                              ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:225: Signal definition not found, creating implicitly: \'B75A_OUT\'\n                                                                            : ... Suggested alternative: \'B71_OUT\'\n assign B75A_OUT = ~&{~LSPOE, LSPOE_SEQB};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:227: Signal definition not found, creating implicitly: \'LSPOE_SEQC\'\n                                                                            : ... Suggested alternative: \'LSPOE_SEQA\'\n assign B74_OUT = ~&{~LSPOE, LSPOE_SEQC};\n                             ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:227: Signal definition not found, creating implicitly: \'B74_OUT\'\n                                                                            : ... Suggested alternative: \'B71_OUT\'\n assign B74_OUT = ~&{~LSPOE, LSPOE_SEQC};\n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:233: Signal definition not found, creating implicitly: \'SPR_AA_3\'\n assign AUTOANIM3_EN = SPR_AA_3 & ~AA_DISABLE;\n                       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:233: Signal definition not found, creating implicitly: \'AA_DISABLE\'\n assign AUTOANIM3_EN = SPR_AA_3 & ~AA_DISABLE;\n                                   ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:233: Signal definition not found, creating implicitly: \'AUTOANIM3_EN\'\n assign AUTOANIM3_EN = SPR_AA_3 & ~AA_DISABLE;\n        ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:234: Signal definition not found, creating implicitly: \'SPR_AA_2\'\n                                                                            : ... Suggested alternative: \'SPR_AA_3\'\n assign C186A_OUT = SPR_AA_2 & ~AA_DISABLE;\n                    ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:234: Signal definition not found, creating implicitly: \'C186A_OUT\'\n                                                                            : ... Suggested alternative: \'C22A_OUT\'\n assign C186A_OUT = SPR_AA_2 & ~AA_DISABLE;\n        ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:236: Signal definition not found, creating implicitly: \'AUTOANIM2_EN\'\n                                                                            : ... Suggested alternative: \'AUTOANIM3_EN\'\n assign AUTOANIM2_EN = AUTOANIM3_EN | C186A_OUT;\n        ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:241: Signal definition not found, creating implicitly: \'LSPC_6M\'\n                                                                            : ... Suggested alternative: \'LSPC_3M\'\n assign T56A_OUT = ~&{LSPC_6M, LSPC_3M};\n                      ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:241: Signal definition not found, creating implicitly: \'T56A_OUT\'\n                                                                            : ... Suggested alternative: \'U56A_OUT\'\n assign T56A_OUT = ~&{LSPC_6M, LSPC_3M};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:242: Signal definition not found, creating implicitly: \'T58A_OUT\'\n                                                                            : ... Suggested alternative: \'S58A_OUT\'\n assign T58A_OUT = ~&{LSPC_6M, LSPC_3M};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:245: Signal definition not found, creating implicitly: \'U53_Q\'\n assign nPBUS_OUT_EN = U53_Q & T53_Q;\n                       ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:245: Signal definition not found, creating implicitly: \'T53_Q\'\n                                                                            : ... Suggested alternative: \'U53_Q\'\n assign nPBUS_OUT_EN = U53_Q & T53_Q;\n                               ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:249: Signal definition not found, creating implicitly: \'CLK_24MB\'\n                                                                            : ... Suggested alternative: \'CLK_24M\'\n always @(posedge CLK_24MB or negedge nRESETP)\n                  ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:258: Signal definition not found, creating implicitly: \'LSPC_12M\'\n                                                                            : ... Suggested alternative: \'LSPC_1_5M\'\n   if (!LSPC_12M)\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:263: Signal definition not found, creating implicitly: \'T73A_OUT\'\n                                                                            : ... Suggested alternative: \'B75A_OUT\'\n assign T73A_OUT = LSPC_3M | T69_nQ;\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:291: Signal definition not found, creating implicitly: \'T125A_OUT\'\n                                                                            : ... Suggested alternative: \'T160A_OUT\'\n assign T125A_OUT = ~U129A_Q | T140_Q;\n        ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:294: Signal definition not found, creating implicitly: \'O159_QB\'\n assign P219A_OUT = ~|{O159_QB, ~P201_Q[0]};\n                       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:294: Signal definition not found, creating implicitly: \'P219A_OUT\'\n                                                                            : ... Suggested alternative: \'C22A_OUT\'\n assign P219A_OUT = ~|{O159_QB, ~P201_Q[0]};\n        ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:295: Signal definition not found, creating implicitly: \'P222A_OUT\'\n                                                                            : ... Suggested alternative: \'C22A_OUT\'\n assign P222A_OUT = ~&{P219A_OUT, ~P201_Q[1]};\n        ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:296: Signal definition not found, creating implicitly: \'CLK_SPR_TILE\'\n                                                                            : ... Suggested alternative: \'SPR_TILE\'\n assign CLK_SPR_TILE = P201_Q[1];\n        ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:297: Signal definition not found, creating implicitly: \'R91_Q\'\n assign R94A_OUT = ~&{P201_Q[2], R91_Q};\n                                 ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:297: Signal definition not found, creating implicitly: \'R94A_OUT\'\n assign R94A_OUT = ~&{P201_Q[2], R91_Q};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:298: Signal definition not found, creating implicitly: \'D208B_OUT\'\n                                                                            : ... Suggested alternative: \'O108B_OUT\'\n assign D208B_OUT = ~P201_Q[3];\n        ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:309: Signal definition not found, creating implicitly: \'WE1\'\n                                                                            : ... Suggested alternative: \'WE\'\n assign WE1 = ~&{T31_P[0], LSPC_12M};\n        ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:310: Signal definition not found, creating implicitly: \'WE2\'\n                                                                            : ... Suggested alternative: \'WE\'\n assign WE2 = ~&{T31_P[1], LSPC_12M};\n        ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:311: Signal definition not found, creating implicitly: \'CK1\'\n                                                                            : ... Suggested alternative: \'CK\'\n assign CK1 = ~&{T31_P[2], LSPC_12M};\n        ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:312: Signal definition not found, creating implicitly: \'CK2\'\n                                                                            : ... Suggested alternative: \'CK\'\n assign CK2 = ~&{T31_P[3], LSPC_12M};\n        ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:314: Signal definition not found, creating implicitly: \'WE3\'\n                                                                            : ... Suggested alternative: \'WE\'\n assign WE3 = ~&{U24_P[2], LSPC_12M};\n        ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:315: Signal definition not found, creating implicitly: \'WE4\'\n                                                                            : ... Suggested alternative: \'WE\'\n assign WE4 = ~&{U24_P[3], LSPC_12M};\n        ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:316: Signal definition not found, creating implicitly: \'CK3\'\n                                                                            : ... Suggested alternative: \'CK\'\n assign CK3 = ~&{U24_P[0], LSPC_12M};\n        ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:317: Signal definition not found, creating implicitly: \'CK4\'\n                                                                            : ... Suggested alternative: \'CA4\'\n assign CK4 = ~&{U24_P[1], LSPC_12M};\n        ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:326: Signal definition not found, creating implicitly: \'T50B_OUT\'\n                                                                            : ... Suggested alternative: \'T160B_OUT\'\n assign T22A_OUT = ~&{T50B_OUT, SS1};\n                      ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:326: Signal definition not found, creating implicitly: \'T22A_OUT\'\n                                                                            : ... Suggested alternative: \'C22A_OUT\'\n assign T22A_OUT = ~&{T50B_OUT, SS1};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:327: Signal definition not found, creating implicitly: \'T48A_OUT\'\n                                                                            : ... Suggested alternative: \'T58A_OUT\'\n assign T40B_OUT = ~&{T48A_OUT, SS1};\n                      ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:327: Signal definition not found, creating implicitly: \'T40B_OUT\'\n                                                                            : ... Suggested alternative: \'T50B_OUT\'\n assign T40B_OUT = ~&{T48A_OUT, SS1};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:329: Signal definition not found, creating implicitly: \'WRITEPX_A\'\n assign T50A_OUT = ~&{WRITEPX_A, CHG_D};\n                      ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:329: Signal definition not found, creating implicitly: \'CHG_D\'\n                                                                            : ... Suggested alternative: \'CHG\'\n assign T50A_OUT = ~&{WRITEPX_A, CHG_D};\n                                 ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:329: Signal definition not found, creating implicitly: \'T50A_OUT\'\n                                                                            : ... Suggested alternative: \'T50B_OUT\'\n assign T50A_OUT = ~&{WRITEPX_A, CHG_D};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:330: Signal definition not found, creating implicitly: \'WRITEPX_B\'\n                                                                            : ... Suggested alternative: \'WRITEPX_A\'\n assign T40A_OUT = ~&{WRITEPX_B, CHG_D};\n                      ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:330: Signal definition not found, creating implicitly: \'T40A_OUT\'\n                                                                            : ... Suggested alternative: \'T40B_OUT\'\n assign T40A_OUT = ~&{WRITEPX_B, CHG_D};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:332: Signal definition not found, creating implicitly: \'T17A_OUT\'\n                                                                            : ... Suggested alternative: \'T125A_OUT\'\n assign T17A_OUT = ~&{DOTA, ~T50A_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:333: Signal definition not found, creating implicitly: \'T22B_OUT\'\n                                                                            : ... Suggested alternative: \'T22A_OUT\'\n assign T22B_OUT = ~&{DOTB, ~T40A_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:335: Signal definition not found, creating implicitly: \'T20B_OUT\'\n                                                                            : ... Suggested alternative: \'T22B_OUT\'\n assign T20B_OUT = ~&{T22A_OUT, T17A_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:336: Signal definition not found, creating implicitly: \'T29A_OUT\'\n                                                                            : ... Suggested alternative: \'T22A_OUT\'\n assign T29A_OUT = ~&{T40B_OUT, T22B_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:338: Signal definition not found, creating implicitly: \'LD1_D\'\n                                                                            : ... Suggested alternative: \'LD1\'\n assign T28_OUT = ~&{T22A_OUT, LD1_D, T50A_OUT};\n                               ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:338: Signal definition not found, creating implicitly: \'T28_OUT\'\n                                                                            : ... Suggested alternative: \'T20B_OUT\'\n assign T28_OUT = ~&{T22A_OUT, LD1_D, T50A_OUT};\n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:339: Signal definition not found, creating implicitly: \'T38A_OUT\'\n                                                                            : ... Suggested alternative: \'T48A_OUT\'\n assign T38A_OUT = ~&{T40B_OUT, T40A_OUT, LD1_D};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:343: Signal definition not found, creating implicitly: \'U33B_OUT\'\n                                                                            : ... Suggested alternative: \'U57B_OUT\'\n assign U33B_OUT = ~&{T48A_OUT, SS2};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:344: Signal definition not found, creating implicitly: \'T20A_OUT\'\n                                                                            : ... Suggested alternative: \'T20B_OUT\'\n assign T20A_OUT = ~&{T50B_OUT, SS2};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:346: Signal definition not found, creating implicitly: \'nCHG_D\'\n                                                                            : ... Suggested alternative: \'CHG_D\'\n assign U51B_OUT = ~&{WRITEPX_A, nCHG_D};\n                                 ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:346: Signal definition not found, creating implicitly: \'U51B_OUT\'\n                                                                            : ... Suggested alternative: \'U57B_OUT\'\n assign U51B_OUT = ~&{WRITEPX_A, nCHG_D};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:347: Signal definition not found, creating implicitly: \'U39B_OUT\'\n                                                                            : ... Suggested alternative: \'U33B_OUT\'\n assign U39B_OUT = ~&{WRITEPX_B, nCHG_D};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:349: Signal definition not found, creating implicitly: \'U18A_OUT\'\n                                                                            : ... Suggested alternative: \'C186A_OUT\'\n assign U18A_OUT = ~&{DOTA, ~U51B_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:350: Signal definition not found, creating implicitly: \'U38A_OUT\'\n                                                                            : ... Suggested alternative: \'T38A_OUT\'\n assign U38A_OUT = ~&{DOTB, ~U39B_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:352: Signal definition not found, creating implicitly: \'U21B_OUT\'\n                                                                            : ... Suggested alternative: \'U51B_OUT\'\n assign U21B_OUT = ~&{T20A_OUT, U18A_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:353: Signal definition not found, creating implicitly: \'U37B_OUT\'\n                                                                            : ... Suggested alternative: \'U33B_OUT\'\n assign U37B_OUT = ~&{U33B_OUT, U38A_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:355: Signal definition not found, creating implicitly: \'LD2_D\'\n                                                                            : ... Suggested alternative: \'LD1_D\'\n assign U35A_OUT = ~&{LD2_D, U33B_OUT, U39B_OUT};\n                      ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:355: Signal definition not found, creating implicitly: \'U35A_OUT\'\n                                                                            : ... Suggested alternative: \'U38A_OUT\'\n assign U35A_OUT = ~&{LD2_D, U33B_OUT, U39B_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:356: Signal definition not found, creating implicitly: \'U31A_OUT\'\n                                                                            : ... Suggested alternative: \'U35A_OUT\'\n assign U31A_OUT = ~&{LD2_D, T20A_OUT, U51B_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:365: Signal definition not found, creating implicitly: \'U89A_OUT\'\n                                                                            : ... Suggested alternative: \'T29A_OUT\'\n assign U89A_OUT = ~&{nHSHRINK_OUT_B, nEVEN_ODD, HSHRINK_OUT_A};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:366: Signal definition not found, creating implicitly: \'U92A_OUT\'\n                                                                            : ... Suggested alternative: \'C22A_OUT\'\n assign U92A_OUT = ~&{nHSHRINK_OUT_A, nEVEN_ODD, HSHRINK_OUT_B};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:367: Signal definition not found, creating implicitly: \'U91_OUT\'\n                                                                            : ... Suggested alternative: \'B71_OUT\'\n assign U91_OUT = ~&{nHSHRINK_OUT_B, EVEN_nODD, HSHRINK_OUT_A};\n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:368: Signal definition not found, creating implicitly: \'U94_OUT\'\n                                                                            : ... Suggested alternative: \'U91_OUT\'\n assign U94_OUT = ~&{nHSHRINK_OUT_A, EVEN_nODD, HSHRINK_OUT_B};\n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:370: Signal definition not found, creating implicitly: \'U88B_OUT\'\n                                                                            : ... Suggested alternative: \'U18A_OUT\'\n assign U88B_OUT = HSHRINK_OUT_A | HSHRINK_OUT_B;\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:371: Signal definition not found, creating implicitly: \'U85_OUT\'\n                                                                            : ... Suggested alternative: \'U18A_OUT\'\n assign U85_OUT = &{U89A_OUT, U92A_OUT, U88B_OUT};\n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:372: Signal definition not found, creating implicitly: \'U86A_OUT\'\n                                                                            : ... Suggested alternative: \'U56A_OUT\'\n assign U86A_OUT = &{U88B_OUT, U94_OUT, U91_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:385: Signal definition not found, creating implicitly: \'S55_Q\'\n assign S53A_OUT = S55_Q & LSPC_6M;\n                   ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:391: Signal definition not found, creating implicitly: \'R69_nQ\'\n                                                                            : ... Suggested alternative: \'T69_nQ\'\n assign nCHAINED = ~|{PIPE_C[13], R69_nQ};\n                                  ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:393: Signal definition not found, creating implicitly: \'R50_nQ\'\n                                                                            : ... Suggested alternative: \'R69_nQ\'\n assign R44B_OUT = ~&{R50_nQ, R53_Q};\n                      ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:393: Signal definition not found, creating implicitly: \'R53_Q\'\n                                                                            : ... Suggested alternative: \'T53_Q\'\n assign R44B_OUT = ~&{R50_nQ, R53_Q};\n                              ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:393: Signal definition not found, creating implicitly: \'R44B_OUT\'\n                                                                            : ... Suggested alternative: \'R94A_OUT\'\n assign R44B_OUT = ~&{R50_nQ, R53_Q};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:395: Signal definition not found, creating implicitly: \'R50_Q\'\n                                                                            : ... Suggested alternative: \'R50_nQ\'\n assign R48B_OUT = ~&{nCHAINED, R50_Q};\n                                ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:395: Signal definition not found, creating implicitly: \'R48B_OUT\'\n                                                                            : ... Suggested alternative: \'R44B_OUT\'\n assign R48B_OUT = ~&{nCHAINED, R50_Q};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:397: Signal definition not found, creating implicitly: \'R42B_OUT\'\n                                                                            : ... Suggested alternative: \'R44B_OUT\'\n assign R42B_OUT = ~&{R44B_OUT, R48B_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:404: Signal definition not found, creating implicitly: \'R44A_OUT\'\n                                                                            : ... Suggested alternative: \'R44B_OUT\'\n assign R44A_OUT = ~&{R53_Q, R50_Q};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:406: Signal definition not found, creating implicitly: \'R46A_OUT\'\n                                                                            : ... Suggested alternative: \'R44A_OUT\'\n assign R46A_OUT = ~&{R50_nQ, nCHAINED};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:408: Signal definition not found, creating implicitly: \'R46B_OUT\'\n                                                                            : ... Suggested alternative: \'R42B_OUT\'\n assign R46B_OUT = ~&{R44A_OUT, R46A_OUT};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:421: Signal definition not found, creating implicitly: \'R74_nQ\'\n                                                                            : ... Suggested alternative: \'R50_nQ\'\n assign R67A_OUT = R74_nQ & P74_Q;\n                   ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:421: Signal definition not found, creating implicitly: \'P74_Q\'\n                                                                            : ... Suggested alternative: \'R74_nQ\'\n assign R67A_OUT = R74_nQ & P74_Q;\n                            ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:421: Signal definition not found, creating implicitly: \'R67A_OUT\'\n                                                                            : ... Suggested alternative: \'R44A_OUT\'\n assign R67A_OUT = R74_nQ & P74_Q;\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:426: Signal definition not found, creating implicitly: \'R69_Q\'\n                                                                            : ... Suggested alternative: \'R69_nQ\'\n assign R48A_OUT = ~&{S53A_OUT, R69_Q};\n                                ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:426: Signal definition not found, creating implicitly: \'R48A_OUT\'\n                                                                            : ... Suggested alternative: \'R44A_OUT\'\n assign R48A_OUT = ~&{S53A_OUT, R69_Q};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:438: Signal definition not found, creating implicitly: \'S48_nQ\'\n assign SS1 = ~|{S48_nQ, CHG_D};\n                 ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:444: Signal definition not found, creating implicitly: \'J20A_OUT\'\n                                                                            : ... Suggested alternative: \'T20A_OUT\'\n assign J20A_OUT = ~&{PIXELC[8:7]};\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:452: Signal definition not found, creating implicitly: \'P235_OUT\'\n                                                                            : ... Suggested alternative: \'P219A_OUT\'\n assign S186_OUT = ~(~P235_OUT ^ R179_Q);\n                      ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:452: Signal definition not found, creating implicitly: \'R179_Q\'\n                                                                            : ... Suggested alternative: \'R69_Q\'\n assign S186_OUT = ~(~P235_OUT ^ R179_Q);\n                                 ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:452: Signal definition not found, creating implicitly: \'S186_OUT\'\n                                                                            : ... Suggested alternative: \'C186A_OUT\'\n assign S186_OUT = ~(~P235_OUT ^ R179_Q);\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:453: Signal definition not found, creating implicitly: \'SPRITEMAP_ADDR_MSB\'\n assign SPRITEMAP_ADDR_MSB = ~S186_OUT;\n        ^~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:454: Signal definition not found, creating implicitly: \'S166_OUT\'\n                                                                            : ... Suggested alternative: \'S186_OUT\'\n assign S166_OUT = VSHRINK_LINE[3] ^ ~S186_OUT;\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:455: Signal definition not found, creating implicitly: \'S164_OUT\'\n                                                                            : ... Suggested alternative: \'S166_OUT\'\n assign S164_OUT = VSHRINK_LINE[2] ^ ~S186_OUT;\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:456: Signal definition not found, creating implicitly: \'S162_OUT\'\n                                                                            : ... Suggested alternative: \'S164_OUT\'\n assign S162_OUT = VSHRINK_LINE[1] ^ ~S186_OUT;\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:457: Signal definition not found, creating implicitly: \'S168_OUT\'\n                                                                            : ... Suggested alternative: \'S162_OUT\'\n assign S168_OUT = VSHRINK_LINE[0] ^ ~S186_OUT;\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:460: Signal definition not found, creating implicitly: \'SPR_TILE_VFLIP\'\n                                                                            : ... Suggested alternative: \'SPR_TILE_HFLIP\'\n assign SPR_LINE[0] = SPR_TILE_VFLIP ^ G233_Q[0];\n                      ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:464: Signal definition not found, creating implicitly: \'Q184_OUT\'\n                                                                            : ... Suggested alternative: \'S164_OUT\'\n assign Q184_OUT = VSHRINK_INDEX[3] ^ ~S186_OUT;\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:465: Signal definition not found, creating implicitly: \'Q182_OUT\'\n                                                                            : ... Suggested alternative: \'Q184_OUT\'\n assign Q182_OUT = VSHRINK_INDEX[2] ^ ~S186_OUT;\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:466: Signal definition not found, creating implicitly: \'Q186_OUT\'\n                                                                            : ... Suggested alternative: \'Q182_OUT\'\n assign Q186_OUT = VSHRINK_INDEX[1] ^ ~S186_OUT;\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:467: Signal definition not found, creating implicitly: \'Q172_OUT\'\n                                                                            : ... Suggested alternative: \'Q182_OUT\'\n assign Q172_OUT = VSHRINK_INDEX[0] ^ ~S186_OUT;\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:477: Signal definition not found, creating implicitly: \'R88_nQ\'\n                                                                            : ... Suggested alternative: \'R50_nQ\'\n assign VCS = ~R88_nQ;\n               ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:480: Signal definition not found, creating implicitly: \'T185B_OUT\'\n                                                                            : ... Suggested alternative: \'T125A_OUT\'\n assign T185B_OUT = PCK1 | PCK2;\n        ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:496: Signal definition not found, creating implicitly: \'R88_Q\'\n                                                                            : ... Suggested alternative: \'R88_nQ\'\n assign P_MUX_HIGH = R88_Q ? XPOS[8:1] : YSHRINK;\n                     ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:500: Signal definition not found, creating implicitly: \'SPR_CONTINUOUS\'\n assign LO_LINE_MUX = SPR_CONTINUOUS ? ~LO_LINE_B : LO_LINE_A;   \n                      ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:510: Signal definition not found, creating implicitly: \'S183_Q_DELAYED\'\n assign P_OUT_MUX[23:16] = ~S183_Q_DELAYED ? \n                            ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:511: Signal definition not found, creating implicitly: \'S171_nQ\'\n          ~S171_nQ ? \n           ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:532: Signal definition not found, creating implicitly: \'FLIP\'\n           {PIXELC[2], RASTERC[2:1], FLIP, FIX_TILE[11:8], FIX_TILE[7:0]}\n                                     ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:556: Signal definition not found, creating implicitly: \'SPR_SIZE0\'\n                                                                            : ... Suggested alternative: \'SPR_LINE\'\n assign SPR_CONTINUOUS = &{SPR_SIZE0, SPR_SIZE5, SPR_Y_SHRINK[8]};\n                           ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/161275071/video/lspc2_a2.v:556: Signal definition not found, creating implicitly: \'SPR_SIZE5\'\n                                                                            : ... Suggested alternative: \'SPR_SIZE0\'\n assign SPR_CONTINUOUS = &{SPR_SIZE0, SPR_SIZE5, SPR_Y_SHRINK[8]};\n                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:176: Cannot find file containing module: \'FD2\'\n FD2 U68A(CLK_24MB, ~LSPC_12M, CK_HSHRINK_REG, U68A_nQ);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/161275071/video,data/full_repos/permissive/161275071/FD2\n             data/full_repos/permissive/161275071/video,data/full_repos/permissive/161275071/FD2.v\n             data/full_repos/permissive/161275071/video,data/full_repos/permissive/161275071/FD2.sv\n             FD2\n             FD2.v\n             FD2.sv\n             obj_dir/FD2\n             obj_dir/FD2.v\n             obj_dir/FD2.sv\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:177: Cannot find file containing module: \'FD2\'\n FD2 U74A(~U68A_nQ, U56A_OUT, EVEN_nODD, nEVEN_ODD);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:185: Cannot find file containing module: \'FDM\'\n FDM B18(C22A_OUT, M68K_ADDR[1], VRAM_ADDR_UPD_TYPE);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:203: Cannot find file containing module: \'FDS16bit\'\n FDS16bit F14(D112B_OUT_DELAY, VRAM_ADDR_MUX, VRAM_ADDR);\n ^~~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:207: Cannot find file containing module: \'FDS16bit\'\n FDS16bit E196(O108B_OUT, REG_VRAMRW, VRAM_WRITE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:218: Cannot find file containing module: \'FDM\'\n FDM C71(CLK_24M, LSPOE, C71_Q, LSPOE_SEQA);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:219: Cannot find file containing module: \'FDM\'\n FDM C68(CLK_24MB, C71_Q, C68_Q, LSPOE_SEQB);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:220: Cannot find file containing module: \'FDM\'\n FDM C75(CLK_24M, C68_Q, , LSPOE_SEQC);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:243: Cannot find file containing module: \'FDM\'\n FDM T53(LSPC_12M, T56A_OUT, T53_Q);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:244: Cannot find file containing module: \'FDM\'\n FDM U53(CLK_24M, T53_Q, U53_Q);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:292: Cannot find file containing module: \'BD3\'\n BD3 P198A(Q174B_OUT, P198A_OUT);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:293: Cannot find file containing module: \'FS1\'\n FS1 P201(LSPC_12M, P198A_OUT, P201_Q);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:304: Cannot find file containing module: \'LT4\'\n LT4 T31(LSPC_12M, {T38A_OUT, T28_OUT, T29A_OUT, T20B_OUT}, T31_P);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:306: Cannot find file containing module: \'LT4\'\n LT4 U24(LSPC_12M, {U37B_OUT, U21B_OUT, U35A_OUT, U31A_OUT}, U24_P);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:374: Cannot find file containing module: \'FD2\'\n FD2 T82A(CLK_24M, U85_OUT, WRITEPX_A);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:375: Cannot find file containing module: \'FD2\'\n FD2 T86(CLK_24M, U86A_OUT, WRITEPX_B);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:380: Cannot find file containing module: \'FDM\'\n FDM R50(LSPC_3M, FLIP_nQ, R50_Q, R50_nQ);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:383: Cannot find file containing module: \'FDM\'\n FDM R69(LSPC_3M, LSPC_1_5M, R69_Q, R69_nQ);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:384: Cannot find file containing module: \'FDM\'\n FDM S55(LSPC_12M, LSPC_3M, S55_Q);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:387: Cannot find file containing module: \'FD2\'\n FD2 R35A(CLK_24MB, S53A_OUT, LOAD);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:400: Cannot find file containing module: \'FD2\'\n FD2 R32(CLK_24MB, LD1_D, LD1);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:411: Cannot find file containing module: \'FD2\'\n FD2 R28A(CLK_24MB, LD2_D, LD2);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:416: Cannot find file containing module: \'FDPCell\'\n FDPCell O62(PIXELC[3], PIXELC[8], 1\'b1, nRESETP, O62_Q);\n ^~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:418: Cannot find file containing module: \'FDPCell\'\n FDPCell P74(PIXELC[2], O62_Q, 1\'b1, nRESETP, P74_Q);\n ^~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:420: Cannot find file containing module: \'FDM\'\n FDM R53(LSPC_3M, R67A_OUT, R53_Q);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:422: Cannot find file containing module: \'FDPCell\'\n FDPCell R74(LSPC_1_5M, P74_Q, 1\'b1, nRESETP, , R74_nQ);\n ^~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:427: Cannot find file containing module: \'FD2\'\n FD2 R56A(CLK_24MB, R48A_OUT, LD_HSHRINK_REG);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:431: Cannot find file containing module: \'FDPCell\'\n FDPCell S137(LSPC_1_5M, CHG_D, 1\'b1, nRESETP, CHG);\n ^~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:434: Cannot find file containing module: \'FDPCell\'\n FDPCell O69(CLK_24MB, nFLIP, nRESETP, 1\'b1, , FLIP_nQ);\n ^~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:435: Cannot find file containing module: \'FDPCell\'\n FDPCell R63(PIXELC[2], FLIP_nQ, 1\'b1, nRESETP, CHG_D, nCHG_D);\n ^~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:436: Cannot find file containing module: \'FDM\'\n FDM S48(LSPC_3M, R15_QD, , S48_nQ);\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/161275071/video/lspc2_a2.v:446: Operator ADD expects 5 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance lspc2_a2\n assign PIXEL_HPLUS = 5\'d15 + {~J20A_OUT, PIXELC[6:4]} + PIXELC[3];\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/161275071/video/lspc2_a2.v:446: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 5 bits.\n                                                                         : ... In instance lspc2_a2\n assign PIXEL_HPLUS = 5\'d15 + {~J20A_OUT, PIXELC[6:4]} + PIXELC[3];\n                    ^\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:450: Cannot find file containing module: \'FDM\'\n FDM R179(VCS, SPR_CONTINUOUS, R179_Q);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:458: Cannot find file containing module: \'FDSCell\'\n FDSCell O227(P222A_OUT, {S166_OUT, S164_OUT, S162_OUT, S168_OUT}, O227_Q);\n ^~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:459: Cannot find file containing module: \'FDSCell\'\n FDSCell G233(~P201_Q[1], O227_Q, G233_Q);\n ^~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:468: Cannot find file containing module: \'FDSCell\'\n FDSCell O175(P222A_OUT, {Q184_OUT, Q182_OUT, Q186_OUT, Q172_OUT}, SPR_TILEMAP);\n ^~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:473: Cannot find file containing module: \'FDSCell\'\n FDSCell Q87(VCS, PBUS_IO[23:20], VSHRINK_INDEX);\n ^~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:474: Cannot find file containing module: \'FDSCell\'\n FDSCell S141(VCS, PBUS_IO[19:16], VSHRINK_LINE);\n ^~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:476: Cannot find file containing module: \'FDM\'\n FDM R88(CLK_24M, R94A_OUT, R88_Q, R88_nQ);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:482: Cannot find file containing module: \'FDM\'\n FDM S183(T185B_OUT, S171_Q, S183_Q);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:483: Cannot find file containing module: \'BD3\'\n BD3 P196(S183_Q, S183_Q_DELAYED);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:484: Cannot find file containing module: \'FDM\'\n FDM S171(U53_Q, LSPC_1_5M, S171_Q, S171_nQ);\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/161275071/video/lspc2_a2.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance lspc2_a2\n assign XPOS_ROUND_UP = XPOS[8:1] + XPOS[0];\n                                  ^\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:558: Cannot find file containing module: \'lspc_regs\'\n lspc_regs REGS(RESET, nRESETP, M68K_ADDR, M68K_DATA, LSPOE, LSPWE, VMODE, RASTERC, AA_COUNT, VRAM_LOW_READ,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:563: Cannot find file containing module: \'lspc_timer\'\n lspc_timer TIMER(LSPC_6M, nRESETP, M68K_DATA, WR_TIMER_HIGH, WR_TIMER_LOW, VMODE, TIMER_MODE, TIMER_STOP,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:566: Cannot find file containing module: \'resetp\'\n resetp RSTP(CLK_24MB, RESET, nRESETP);\n ^~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:568: Cannot find file containing module: \'irq\'\n irq IRQ(WR_IRQ_ACK, M68K_DATA[2:0], RESET, D46A_OUT, BNK, LSPC_6M, IPL0, IPL1);\n ^~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:570: Cannot find file containing module: \'videosync\'\n videosync VS(CLK_24MB, LSPC_3M, LSPC_1_5M, Q53_CO, nRESETP, VMODE, PIXELC, RASTERC, HSYNC, VSYNC, BNK,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:573: Cannot find file containing module: \'lspc2_clk\'\n lspc2_clk LSPCCLK(CLK_24M, nRESETP, CLK_24MB, LSPC_12M, LSPC_8M, LSPC_6M, LSPC_4M, LSPC_3M, LSPC_1_5M,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:576: Cannot find file containing module: \'slow_cycle\'\n slow_cycle SCY(CLK_24M, CLK_24MB, LSPC_12M, LSPC_6M, LSPC_3M, LSPC_1_5M, nRESETP, VRAM_ADDR[14:0], VRAM_WRITE,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:584: Cannot find file containing module: \'fast_cycle\'\n fast_cycle FCY(CLK_24M, LSPC_12M, LSPC_6M, LSPC_3M, LSPC_1_5M, nRESETP, nVRAM_WRITE_REQ,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/161275071/video/lspc2_a2.v:591: Cannot find file containing module: \'autoanim\'\n autoanim AA(RASTERC[8], nRESETP, AA_SPEED, AA_COUNT);\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module lspc2_a2(
	input CLK_24M,
	input RESET,
	output [15:0] PBUS_OUT,
	inout [23:16] PBUS_IO,
	input [3:1] M68K_ADDR,
	inout [15:0] M68K_DATA,
	input LSPOE, LSPWE,
	input DOTA, DOTB,
	output CA4,
	output S2H1,
	output S1H1,
	output LOAD,
	output reg H,
	output EVEN1,
	output reg EVEN2,
	output IPL0, IPL1,
	output CHG,
	output LD1, LD2,
	output reg PCK1, PCK2,
	output [3:0] WE,
	output [3:0] CK,
	output SS1, SS2,
	output nRESETP,
	output HSYNC,
	output VSYNC,
	output CHBL,
	output BNKB,
	output VCS,
	output LSPC_8M,
	output LSPC_4M,
	
	output [14:0] SVRAM_ADDR,
	input [15:0] SVRAM_DATA_IN,
	output [15:0] SVRAM_DATA_OUT,
	output BOE, BWE,
	
	output [10:0] FVRAM_ADDR,
	input [15:0] FVRAM_DATA_IN,
	output [15:0] FVRAM_DATA_OUT,
	output CWE,
	
	output nPBUS_OUT_EN,
	
	input VMODE,
	
	output [14:0] FIXMAP_ADDR
);

	wire [8:0] PIXELC;
	wire [3:0] PIXEL_HPLUS;
	wire [8:0] RASTERC;
	
	wire [7:0] AA_SPEED;
	wire [2:0] AA_COUNT;
	
	wire [15:0] CPU_DATA_OUT;
	
	wire [15:0] VRAM_LOW_READ;
	wire [15:0] VRAM_HIGH_READ;
	wire [15:0] REG_VRAMADDR;
	wire [15:0] VRAM_ADDR;
	wire [15:0] VRAM_ADDR_MUX;
	wire [15:0] VRAM_ADDR_AUTOINC;
	wire [15:0] REG_VRAMRW;
	wire [15:0] VRAM_WRITE;
	
	wire [15:0] REG_VRAMMOD;
	wire [15:0] REG_LSPCMODE;
	
	wire [2:0] TIMER_MODE;
	
	wire [3:0] T31_P;
	wire [3:0] U24_P;
	wire [3:0] O227_Q;
	
	wire [7:0] P_MUX_HIGH;
	wire [7:0] P_MUX_LOW;
	wire [23:0] P_OUT_MUX;
	
	wire [3:0] VSHRINK_INDEX;
	wire [3:0] VSHRINK_LINE;
	wire [8:0] XPOS;
	wire [7:0] XPOS_ROUND_UP;
	wire [2:0] SPR_TILE_AA;
	wire [3:0] G233_Q;
	wire [7:0] SPR_Y_LOOKAHEAD;
	wire [8:0] SPR_Y_ADD;
	wire [7:0] LO_LINE_A;
	wire [7:0] LO_LINE_B;
	wire [8:0] SPR_Y_SHRINK;
	wire [3:0] SPR_LINE;
	wire [7:0] LO_LINE_MUX;
	wire [19:0] SPR_TILE;
	wire [7:0] YSHRINK;
	wire [8:0] SPR_Y;
	wire [7:0] SPR_PAL;
	wire [3:0] FIX_PAL;
	wire [11:0] FIX_TILE;
	wire [3:0] HSHRINK;
	wire [13:0] PIPE_C;
	wire [3:0] SPR_TILEMAP;
	wire [7:0] ACTIVE_RD;
	wire [3:0] P201_Q;
	
	reg D112B_OUT_DELAY;
	

	
	assign S1H1 = LSPC_3M;
	assign S2H1 = LSPC_1_5M;
	




	

	reg T172_Q;

	always @(negedge CLK_24M)
	begin

		PCK1 <= T160A_OUT;


		PCK2 <= T160B_OUT;

		if (PCK1 & ~T160A_OUT)
			T172_Q <= SPR_TILE_HFLIP;

		if (~PCK2 & T160B_OUT)
			H <= T172_Q;
	end
	
	assign CA4 = T172_Q ^ LSPC_1_5M;
	

	assign U105A_OUT = ~&{nHSHRINK_OUT_A, nHSHRINK_OUT_B, nEVEN_ODD};
	assign U107_OUT = ~&{nHSHRINK_OUT_A, EVEN_nODD, HSHRINK_OUT_B};
	assign U109_OUT = ~&{HSHRINK_OUT_A, nEVEN_ODD};
	assign U112_OUT = ~&{U105A_OUT, U107_OUT, U109_OUT};

	assign EVEN1 = U112_OUT;
	

	assign nPARITY_INIT = ~&{nCHAINED, S53A_OUT};
	assign nXPOS_ZERO = ~PIPE_C[0];
	assign S58A_OUT = ~|{nXPOS_ZERO, nPARITY_INIT};
	assign ONE_PIXEL = HSHRINK_OUT_A ^ HSHRINK_OUT_B;
	assign U72_OUT = ONE_PIXEL ^ nEVEN_ODD;
	assign U57B_OUT = nPARITY_INIT & U72_OUT;
	assign U56A_OUT = ~|{S58A_OUT, U57B_OUT};
	FD2 U68A(CLK_24MB, ~LSPC_12M, CK_HSHRINK_REG, U68A_nQ);
	FD2 U74A(~U68A_nQ, U56A_OUT, EVEN_nODD, nEVEN_ODD);


	



	assign C22A_OUT = ~&{WR_VRAM_RW, WR_VRAM_ADDR};
	FDM B18(C22A_OUT, M68K_ADDR[1], VRAM_ADDR_UPD_TYPE);
	


	assign VRAM_ADDR_AUTOINC = REG_VRAMMOD + VRAM_ADDR;
	





	assign VRAM_ADDR_MUX = VRAM_ADDR_UPD_TYPE ? VRAM_ADDR_AUTOINC : REG_VRAMADDR;
	



	always @(negedge CLK_24M)
		D112B_OUT_DELAY <= D112B_OUT;
	FDS16bit F14(D112B_OUT_DELAY, VRAM_ADDR_MUX, VRAM_ADDR);
	


	FDS16bit E196(O108B_OUT, REG_VRAMRW, VRAM_WRITE);
	



	assign O108B_OUT = ~&{nCPU_WR_HIGH, nCPU_WR_LOW};
	assign D112B_OUT = ~|{~WR_VRAM_ADDR, O108B_OUT};
	



	FDM C71(CLK_24M, LSPOE, C71_Q, LSPOE_SEQA);
	FDM C68(CLK_24MB, C71_Q, C68_Q, LSPOE_SEQB);
	FDM C75(CLK_24M, C68_Q, , LSPOE_SEQC);
	
	assign M68K_DATA[1:0] = LSPOE ? 2'bzz : CPU_DATA_OUT[1:0];
	assign B71_OUT = ~&{~LSPOE, LSPOE_SEQA};
	assign M68K_DATA[7:2] = B71_OUT ? 6'bzzzzzz : CPU_DATA_OUT[7:2];
	assign B75A_OUT = ~&{~LSPOE, LSPOE_SEQB};
	assign M68K_DATA[9:8] = B75A_OUT ? 2'bzz : CPU_DATA_OUT[9:8];
	assign B74_OUT = ~&{~LSPOE, LSPOE_SEQC};
	assign M68K_DATA[15:10] = B74_OUT ? 6'bzzzzzz : CPU_DATA_OUT[15:10];
	
	


	assign AUTOANIM3_EN = SPR_AA_3 & ~AA_DISABLE;
	assign C186A_OUT = SPR_AA_2 & ~AA_DISABLE;

	assign AUTOANIM2_EN = AUTOANIM3_EN | C186A_OUT;
	
	


	assign T56A_OUT = ~&{LSPC_6M, LSPC_3M};
	assign T58A_OUT = ~&{LSPC_6M, LSPC_3M};
	FDM T53(LSPC_12M, T56A_OUT, T53_Q);
	FDM U53(CLK_24M, T53_Q, U53_Q);
	assign nPBUS_OUT_EN = U53_Q & T53_Q;
	
	reg T69_nQ;
	
	always @(posedge CLK_24MB or negedge nRESETP)
	begin

		if (!nRESETP)
		begin
			T69_nQ <= 1'b0;
		end
		else
		begin
			if (!LSPC_12M)
				T69_nQ <= ~LSPC_3M;
		end
	end
	
	assign T73A_OUT = LSPC_3M | T69_nQ;
	
	reg T140_Q, T134_Q;
	always @(posedge CLK_24M or negedge T73A_OUT)
	begin
		if (!T73A_OUT)
		begin
			T140_Q <= 1'b0;
			T134_Q <= 1'b0;
		end
		else
		begin

			T140_Q <= (~T134_Q) ? ~T140_Q : 1'b0;

			T134_Q <= (T140_Q) ? ~T134_Q : 1'b0;
		end
	end
	
	reg U129A_Q;
	always @(negedge CLK_24M)
	begin

		U129A_Q <= ~T134_Q;

		EVEN2 <= U112_OUT;
	end
	
	assign T125A_OUT = ~U129A_Q | T140_Q;
	BD3 P198A(Q174B_OUT, P198A_OUT);
	FS1 P201(LSPC_12M, P198A_OUT, P201_Q);
	assign P219A_OUT = ~|{O159_QB, ~P201_Q[0]};
	assign P222A_OUT = ~&{P219A_OUT, ~P201_Q[1]};
	assign CLK_SPR_TILE = P201_Q[1];
	assign R94A_OUT = ~&{P201_Q[2], R91_Q};
	assign D208B_OUT = ~P201_Q[3];
	
	

	

	LT4 T31(LSPC_12M, {T38A_OUT, T28_OUT, T29A_OUT, T20B_OUT}, T31_P);

	LT4 U24(LSPC_12M, {U37B_OUT, U21B_OUT, U35A_OUT, U31A_OUT}, U24_P);
	

	assign WE1 = ~&{T31_P[0], LSPC_12M};
	assign WE2 = ~&{T31_P[1], LSPC_12M};
	assign CK1 = ~&{T31_P[2], LSPC_12M};
	assign CK2 = ~&{T31_P[3], LSPC_12M};
	
	assign WE3 = ~&{U24_P[2], LSPC_12M};
	assign WE4 = ~&{U24_P[3], LSPC_12M};
	assign CK3 = ~&{U24_P[0], LSPC_12M};
	assign CK4 = ~&{U24_P[1], LSPC_12M};
	
	assign WE = {WE4, WE3, WE2, WE1};
	assign CK = {CK4, CK3, CK2, CK1};
	

	


	assign T22A_OUT = ~&{T50B_OUT, SS1};
	assign T40B_OUT = ~&{T48A_OUT, SS1};

	assign T50A_OUT = ~&{WRITEPX_A, CHG_D};
	assign T40A_OUT = ~&{WRITEPX_B, CHG_D};

	assign T17A_OUT = ~&{DOTA, ~T50A_OUT};
	assign T22B_OUT = ~&{DOTB, ~T40A_OUT};

	assign T20B_OUT = ~&{T22A_OUT, T17A_OUT};
	assign T29A_OUT = ~&{T40B_OUT, T22B_OUT};

	assign T28_OUT = ~&{T22A_OUT, LD1_D, T50A_OUT};
	assign T38A_OUT = ~&{T40B_OUT, T40A_OUT, LD1_D};
	


	assign U33B_OUT = ~&{T48A_OUT, SS2};
	assign T20A_OUT = ~&{T50B_OUT, SS2};

	assign U51B_OUT = ~&{WRITEPX_A, nCHG_D};
	assign U39B_OUT = ~&{WRITEPX_B, nCHG_D};

	assign U18A_OUT = ~&{DOTA, ~U51B_OUT};
	assign U38A_OUT = ~&{DOTB, ~U39B_OUT};

	assign U21B_OUT = ~&{T20A_OUT, U18A_OUT};
	assign U37B_OUT = ~&{U33B_OUT, U38A_OUT};

	assign U35A_OUT = ~&{LD2_D, U33B_OUT, U39B_OUT};
	assign U31A_OUT = ~&{LD2_D, T20A_OUT, U51B_OUT};
	
	

	assign T50B_OUT = LSPC_3M & LSPC_6M;
	assign T48A_OUT = ~LSPC_3M & LSPC_6M;
	
	

	assign U89A_OUT = ~&{nHSHRINK_OUT_B, nEVEN_ODD, HSHRINK_OUT_A};
	assign U92A_OUT = ~&{nHSHRINK_OUT_A, nEVEN_ODD, HSHRINK_OUT_B};
	assign U91_OUT = ~&{nHSHRINK_OUT_B, EVEN_nODD, HSHRINK_OUT_A};
	assign U94_OUT = ~&{nHSHRINK_OUT_A, EVEN_nODD, HSHRINK_OUT_B};

	assign U88B_OUT = HSHRINK_OUT_A | HSHRINK_OUT_B;
	assign U85_OUT = &{U89A_OUT, U92A_OUT, U88B_OUT};
	assign U86A_OUT = &{U88B_OUT, U94_OUT, U91_OUT};

	FD2 T82A(CLK_24M, U85_OUT, WRITEPX_A);
	FD2 T86(CLK_24M, U86A_OUT, WRITEPX_B);
	
	


	FDM R50(LSPC_3M, FLIP_nQ, R50_Q, R50_nQ);
	

	FDM R69(LSPC_3M, LSPC_1_5M, R69_Q, R69_nQ);
	FDM S55(LSPC_12M, LSPC_3M, S55_Q);
	assign S53A_OUT = S55_Q & LSPC_6M;

	FD2 R35A(CLK_24MB, S53A_OUT, LOAD);
	


	assign nCHAINED = ~|{PIPE_C[13], R69_nQ};

	assign R44B_OUT = ~&{R50_nQ, R53_Q};

	assign R48B_OUT = ~&{nCHAINED, R50_Q};

	assign R42B_OUT = ~&{R44B_OUT, R48B_OUT};

	assign LD1_D = ~&{R42B_OUT, S53A_OUT};
	FD2 R32(CLK_24MB, LD1_D, LD1);
	


	assign R44A_OUT = ~&{R53_Q, R50_Q};

	assign R46A_OUT = ~&{R50_nQ, nCHAINED};

	assign R46B_OUT = ~&{R44A_OUT, R46A_OUT};

	assign LD2_D = ~&{R46B_OUT, S53A_OUT};
	FD2 R28A(CLK_24MB, LD2_D, LD2);
	



	FDPCell O62(PIXELC[3], PIXELC[8], 1'b1, nRESETP, O62_Q);

	FDPCell P74(PIXELC[2], O62_Q, 1'b1, nRESETP, P74_Q);

	FDM R53(LSPC_3M, R67A_OUT, R53_Q);
	assign R67A_OUT = R74_nQ & P74_Q;
	FDPCell R74(LSPC_1_5M, P74_Q, 1'b1, nRESETP, , R74_nQ);
	


	assign R48A_OUT = ~&{S53A_OUT, R69_Q};
	FD2 R56A(CLK_24MB, R48A_OUT, LD_HSHRINK_REG);
	
	

	FDPCell S137(LSPC_1_5M, CHG_D, 1'b1, nRESETP, CHG);
	

	FDPCell O69(CLK_24MB, nFLIP, nRESETP, 1'b1, , FLIP_nQ);
	FDPCell R63(PIXELC[2], FLIP_nQ, 1'b1, nRESETP, CHG_D, nCHG_D);
	FDM S48(LSPC_3M, R15_QD, , S48_nQ);

	assign SS1 = ~|{S48_nQ, CHG_D};

	assign SS2 = ~|{nCHG_D, S48_nQ};
	
	

	assign J20A_OUT = ~&{PIXELC[8:7]};

	assign PIXEL_HPLUS = 5'd15 + {~J20A_OUT, PIXELC[6:4]} + PIXELC[3];
	
	

	FDM R179(VCS, SPR_CONTINUOUS, R179_Q);

	assign S186_OUT = ~(~P235_OUT ^ R179_Q);
	assign SPRITEMAP_ADDR_MSB = ~S186_OUT;
	assign S166_OUT = VSHRINK_LINE[3] ^ ~S186_OUT;
	assign S164_OUT = VSHRINK_LINE[2] ^ ~S186_OUT;
	assign S162_OUT = VSHRINK_LINE[1] ^ ~S186_OUT;
	assign S168_OUT = VSHRINK_LINE[0] ^ ~S186_OUT;
	FDSCell O227(P222A_OUT, {S166_OUT, S164_OUT, S162_OUT, S168_OUT}, O227_Q);
	FDSCell G233(~P201_Q[1], O227_Q, G233_Q);
	assign SPR_LINE[0] = SPR_TILE_VFLIP ^ G233_Q[0];
	assign SPR_LINE[1] = SPR_TILE_VFLIP ^ G233_Q[1];
	assign SPR_LINE[2] = SPR_TILE_VFLIP ^ G233_Q[2];
	assign SPR_LINE[3] = SPR_TILE_VFLIP ^ G233_Q[3];
	assign Q184_OUT = VSHRINK_INDEX[3] ^ ~S186_OUT;
	assign Q182_OUT = VSHRINK_INDEX[2] ^ ~S186_OUT;
	assign Q186_OUT = VSHRINK_INDEX[1] ^ ~S186_OUT;
	assign Q172_OUT = VSHRINK_INDEX[0] ^ ~S186_OUT;
	FDSCell O175(P222A_OUT, {Q184_OUT, Q182_OUT, Q186_OUT, Q172_OUT}, SPR_TILEMAP);
	
	


	FDSCell Q87(VCS, PBUS_IO[23:20], VSHRINK_INDEX);
	FDSCell S141(VCS, PBUS_IO[19:16], VSHRINK_LINE);
	
	FDM R88(CLK_24M, R94A_OUT, R88_Q, R88_nQ);
	assign VCS = ~R88_nQ;
	
	
	assign T185B_OUT = PCK1 | PCK2;

	FDM S183(T185B_OUT, S171_Q, S183_Q);
	BD3 P196(S183_Q, S183_Q_DELAYED);
	FDM S171(U53_Q, LSPC_1_5M, S171_Q, S171_nQ);
	
	assign XPOS = PIPE_C[8:0];
	
	assign SPR_TILE_AA[2] = AUTOANIM3_EN ? AA_COUNT[2] : SPR_TILE[2];
	assign SPR_TILE_AA[1:0] = AUTOANIM2_EN ? AA_COUNT[1:0] : SPR_TILE[1:0];
	

	assign XPOS_ROUND_UP = XPOS[8:1] + XPOS[0];
	


	assign P_MUX_HIGH = R88_Q ? XPOS[8:1] : YSHRINK;
	


	assign LO_LINE_MUX = SPR_CONTINUOUS ? ~LO_LINE_B : LO_LINE_A;
	


	assign P_MUX_LOW = R88_Q ? XPOS_ROUND_UP : LO_LINE_MUX;
	
	



	assign P_OUT_MUX[23:16] = ~S183_Q_DELAYED ? 
										~S171_nQ ? 
											{SPR_PAL}
											:
											{SPR_TILE[19:16], SPR_LINE}
										:
										~S171_nQ ?
											{8'b00000000}
											:
											{4'b0000, FIX_PAL};
	




	assign P_OUT_MUX[15:0] = ~S183_Q_DELAYED ?
										~S171_nQ ?
											{P_MUX_HIGH, P_MUX_LOW}
											:
											{SPR_TILE[15:8], SPR_TILE[7:3], SPR_TILE_AA}
										:
										~S171_nQ ?
											{PIXELC[2], RASTERC[2:1], FLIP, FIX_TILE[11:8], FIX_TILE[7:0]}
											:
											{8'b00000000, 8'b00000000};
	
	assign PBUS_IO = nPBUS_OUT_EN ? 8'bzzzzzzzz : P_OUT_MUX[23:16];
	assign PBUS_OUT = P_OUT_MUX[15:0];
	
	


	assign SPR_Y_LOOKAHEAD = {RASTERC[7:1], FLIP} + 1'b1;

	assign SPR_Y_ADD = SPR_Y_LOOKAHEAD + SPR_Y[7:0];


	assign LO_LINE_A = SPR_Y_ADD[7:0] ^ {8{~P235_OUT}};
	assign P235_OUT = ~(SPR_Y[8] ^ SPR_Y_ADD[8]);

	assign SPR_Y_SHRINK = LO_LINE_A + {1'b0, ~YSHRINK};

	assign LO_LINE_B = LO_LINE_A + {~YSHRINK[6:0], 1'b0};
	


	assign SPR_CONTINUOUS = &{SPR_SIZE0, SPR_SIZE5, SPR_Y_SHRINK[8]};
	
	lspc_regs REGS(RESET, nRESETP, M68K_ADDR, M68K_DATA, LSPOE, LSPWE, VMODE, RASTERC, AA_COUNT, VRAM_LOW_READ,
					VRAM_HIGH_READ, WR_VRAM_ADDR, WR_VRAM_RW, WR_TIMER_HIGH, WR_TIMER_LOW, WR_IRQ_ACK, REG_VRAMADDR,
					REG_VRAMMOD, REG_VRAMRW, REG_LSPCMODE, CPU_DATA_OUT, AA_SPEED,	TIMER_MODE,	TIMER_IRQ_EN,
					AA_DISABLE, TIMER_STOP, nVRAM_WRITE_REQ, D112B_OUT);
	
	lspc_timer TIMER(LSPC_6M, nRESETP, M68K_DATA, WR_TIMER_HIGH, WR_TIMER_LOW, VMODE, TIMER_MODE, TIMER_STOP,
						RASTERC, TIMER_IRQ_EN, R74_nQ, BNKB, D46A_OUT);
	
	resetp RSTP(CLK_24MB, RESET, nRESETP);
	
	irq IRQ(WR_IRQ_ACK, M68K_DATA[2:0], RESET, D46A_OUT, BNK, LSPC_6M, IPL0, IPL1);
	
	videosync VS(CLK_24MB, LSPC_3M, LSPC_1_5M, Q53_CO, nRESETP, VMODE, PIXELC, RASTERC, HSYNC, VSYNC, BNK,
						BNKB, CHBL, R15_QD, FLIP, nFLIP, P50_CO);

	lspc2_clk LSPCCLK(CLK_24M, nRESETP, CLK_24MB, LSPC_12M, LSPC_8M, LSPC_6M, LSPC_4M, LSPC_3M, LSPC_1_5M,
							Q53_CO);
	
	slow_cycle SCY(CLK_24M, CLK_24MB, LSPC_12M, LSPC_6M, LSPC_3M, LSPC_1_5M, nRESETP, VRAM_ADDR[14:0], VRAM_WRITE,
							REG_VRAMADDR[15], PIXELC[3], PIXELC[8], RASTERC[7:3], PIXEL_HPLUS, ACTIVE_RD,
							nVRAM_WRITE_REQ, SPR_TILEMAP, SPR_TILE_VFLIP, SPR_TILE_HFLIP, SPR_AA_3, SPR_AA_2,
							FIX_TILE, FIX_PAL, SPR_TILE, SPR_PAL, VRAM_LOW_READ, nCPU_WR_LOW, R91_nQ,
							CLK_CPU_READ_LOW, T160A_OUT, T160B_OUT, CLK_ACTIVE_RD, ACTIVE_RD_PRE8, Q174B_OUT,
							D208B_OUT, SPRITEMAP_ADDR_MSB, CLK_SPR_TILE, P222A_OUT, ~P201_Q[1],
							SVRAM_ADDR, SVRAM_DATA_IN, SVRAM_DATA_OUT, BOE, BWE, FIXMAP_ADDR);
	
	fast_cycle FCY(CLK_24M, LSPC_12M, LSPC_6M, LSPC_3M, LSPC_1_5M, nRESETP, nVRAM_WRITE_REQ,
							VRAM_ADDR, VRAM_WRITE, REG_VRAMADDR[15], FLIP, nFLIP,
							PIXELC, RASTERC, P50_CO, nCPU_WR_HIGH, HSHRINK, PIPE_C, VRAM_HIGH_READ,
							ACTIVE_RD, R91_Q, R91_nQ, T140_Q, T58A_OUT, T73A_OUT, U129A_Q, T125A_OUT,
							CLK_ACTIVE_RD, ACTIVE_RD_PRE8, SPR_Y, YSHRINK, SPR_SIZE0, SPR_SIZE5, O159_QB,
							FVRAM_ADDR, FVRAM_DATA_IN, FVRAM_DATA_OUT, CWE);
	
	autoanim AA(RASTERC[8], nRESETP, AA_SPEED, AA_COUNT);
	
	hshrink HSH(HSHRINK, CK_HSHRINK_REG, LD_HSHRINK_REG, HSHRINK_OUT_A, HSHRINK_OUT_B);
	wire nHSHRINK_OUT_A = ~HSHRINK_OUT_A;
	wire nHSHRINK_OUT_B = ~HSHRINK_OUT_B;
	
endmodule
module lspc2_a2(
	input CLK_24M,
	input RESET,
	output [15:0] PBUS_OUT,
	inout [23:16] PBUS_IO,
	input [3:1] M68K_ADDR,
	inout [15:0] M68K_DATA,
	input LSPOE, LSPWE,
	input DOTA, DOTB,
	output CA4,
	output S2H1,
	output S1H1,
	output LOAD,
	output reg H,
	output EVEN1,
	output reg EVEN2,
	output IPL0, IPL1,
	output CHG,
	output LD1, LD2,
	output reg PCK1, PCK2,
	output [3:0] WE,
	output [3:0] CK,
	output SS1, SS2,
	output nRESETP,
	output HSYNC,
	output VSYNC,
	output CHBL,
	output BNKB,
	output VCS,
	output LSPC_8M,
	output LSPC_4M,
	
	output [14:0] SVRAM_ADDR,
	input [15:0] SVRAM_DATA_IN,
	output [15:0] SVRAM_DATA_OUT,
	output BOE, BWE,
	
	output [10:0] FVRAM_ADDR,
	input [15:0] FVRAM_DATA_IN,
	output [15:0] FVRAM_DATA_OUT,
	output CWE,
	
	output nPBUS_OUT_EN,
	
	input VMODE,
	
	output [14:0] FIXMAP_ADDR
);


	wire [8:0] PIXELC;
	wire [3:0] PIXEL_HPLUS;
	wire [8:0] RASTERC;
	
	wire [7:0] AA_SPEED;
	wire [2:0] AA_COUNT;
	
	wire [15:0] CPU_DATA_OUT;
	
	wire [15:0] VRAM_LOW_READ;
	wire [15:0] VRAM_HIGH_READ;
	wire [15:0] REG_VRAMADDR;
	wire [15:0] VRAM_ADDR;
	wire [15:0] VRAM_ADDR_MUX;
	wire [15:0] VRAM_ADDR_AUTOINC;
	wire [15:0] REG_VRAMRW;
	wire [15:0] VRAM_WRITE;
	
	wire [15:0] REG_VRAMMOD;
	wire [15:0] REG_LSPCMODE;
	
	wire [2:0] TIMER_MODE;
	
	wire [3:0] T31_P;
	wire [3:0] U24_P;
	wire [3:0] O227_Q;
	
	wire [7:0] P_MUX_HIGH;
	wire [7:0] P_MUX_LOW;
	wire [23:0] P_OUT_MUX;
	
	wire [3:0] VSHRINK_INDEX;
	wire [3:0] VSHRINK_LINE;
	wire [8:0] XPOS;
	wire [7:0] XPOS_ROUND_UP;
	wire [2:0] SPR_TILE_AA;
	wire [3:0] G233_Q;
	wire [7:0] SPR_Y_LOOKAHEAD;
	wire [8:0] SPR_Y_ADD;
	wire [7:0] LO_LINE_A;
	wire [7:0] LO_LINE_B;
	wire [8:0] SPR_Y_SHRINK;
	wire [3:0] SPR_LINE;
	wire [7:0] LO_LINE_MUX;
	wire [19:0] SPR_TILE;
	wire [7:0] YSHRINK;
	wire [8:0] SPR_Y;
	wire [7:0] SPR_PAL;
	wire [3:0] FIX_PAL;
	wire [11:0] FIX_TILE;
	wire [3:0] HSHRINK;
	wire [13:0] PIPE_C;
	wire [3:0] SPR_TILEMAP;
	wire [7:0] ACTIVE_RD;
	wire [3:0] P201_Q;
	
	reg D112B_OUT_DELAY;
	

	
	assign S1H1 = LSPC_3M;
	assign S2H1 = LSPC_1_5M;
	




	

	reg T172_Q;

	always @(negedge CLK_24M)
	begin

		PCK1 <= T160A_OUT;


		PCK2 <= T160B_OUT;

		if (PCK1 & ~T160A_OUT)
			T172_Q <= SPR_TILE_HFLIP;

		if (~PCK2 & T160B_OUT)
			H <= T172_Q;
	end
	
	assign CA4 = T172_Q ^ LSPC_1_5M;
	

	assign U105A_OUT = ~&{nHSHRINK_OUT_A, nHSHRINK_OUT_B, nEVEN_ODD};
	assign U107_OUT = ~&{nHSHRINK_OUT_A, EVEN_nODD, HSHRINK_OUT_B};
	assign U109_OUT = ~&{HSHRINK_OUT_A, nEVEN_ODD};
	assign U112_OUT = ~&{U105A_OUT, U107_OUT, U109_OUT};

	assign EVEN1 = U112_OUT;
	

	assign nPARITY_INIT = ~&{nCHAINED, S53A_OUT};
	assign nXPOS_ZERO = ~PIPE_C[0];
	assign S58A_OUT = ~|{nXPOS_ZERO, nPARITY_INIT};
	assign ONE_PIXEL = HSHRINK_OUT_A ^ HSHRINK_OUT_B;
	assign U72_OUT = ONE_PIXEL ^ nEVEN_ODD;
	assign U57B_OUT = nPARITY_INIT & U72_OUT;
	assign U56A_OUT = ~|{S58A_OUT, U57B_OUT};
	FD2 U68A(CLK_24MB, ~LSPC_12M, CK_HSHRINK_REG, U68A_nQ);
	FD2 U74A(~U68A_nQ, U56A_OUT, EVEN_nODD, nEVEN_ODD);


	



	assign C22A_OUT = ~&{WR_VRAM_RW, WR_VRAM_ADDR};
	FDM B18(C22A_OUT, M68K_ADDR[1], VRAM_ADDR_UPD_TYPE);
	


	assign VRAM_ADDR_AUTOINC = REG_VRAMMOD + VRAM_ADDR;
	





	assign VRAM_ADDR_MUX = VRAM_ADDR_UPD_TYPE ? VRAM_ADDR_AUTOINC : REG_VRAMADDR;
	



	always @(negedge CLK_24M)
		D112B_OUT_DELAY <= D112B_OUT;
	FDS16bit F14(D112B_OUT_DELAY, VRAM_ADDR_MUX, VRAM_ADDR);
	


	FDS16bit E196(O108B_OUT, REG_VRAMRW, VRAM_WRITE);
	



	assign O108B_OUT = ~&{nCPU_WR_HIGH, nCPU_WR_LOW};
	assign D112B_OUT = ~|{~WR_VRAM_ADDR, O108B_OUT};
	



	FDM C71(CLK_24M, LSPOE, C71_Q, LSPOE_SEQA);
	FDM C68(CLK_24MB, C71_Q, C68_Q, LSPOE_SEQB);
	FDM C75(CLK_24M, C68_Q, , LSPOE_SEQC);
	
	assign M68K_DATA[1:0] = LSPOE ? 2'bzz : CPU_DATA_OUT[1:0];
	assign B71_OUT = ~&{~LSPOE, LSPOE_SEQA};
	assign M68K_DATA[7:2] = B71_OUT ? 6'bzzzzzz : CPU_DATA_OUT[7:2];
	assign B75A_OUT = ~&{~LSPOE, LSPOE_SEQB};
	assign M68K_DATA[9:8] = B75A_OUT ? 2'bzz : CPU_DATA_OUT[9:8];
	assign B74_OUT = ~&{~LSPOE, LSPOE_SEQC};
	assign M68K_DATA[15:10] = B74_OUT ? 6'bzzzzzz : CPU_DATA_OUT[15:10];
	
	


	assign AUTOANIM3_EN = SPR_AA_3 & ~AA_DISABLE;
	assign C186A_OUT = SPR_AA_2 & ~AA_DISABLE;

	assign AUTOANIM2_EN = AUTOANIM3_EN | C186A_OUT;
	
	


	assign T56A_OUT = ~&{LSPC_6M, LSPC_3M};
	assign T58A_OUT = ~&{LSPC_6M, LSPC_3M};
	FDM T53(LSPC_12M, T56A_OUT, T53_Q);
	FDM U53(CLK_24M, T53_Q, U53_Q);
	assign nPBUS_OUT_EN = U53_Q & T53_Q;
	
	reg T69_nQ;
	
	always @(posedge CLK_24MB or negedge nRESETP)
	begin

		if (!nRESETP)
		begin
			T69_nQ <= 1'b0;
		end
		else
		begin
			if (!LSPC_12M)
				T69_nQ <= ~LSPC_3M;
		end
	end
	
	assign T73A_OUT = LSPC_3M | T69_nQ;
	
	reg T140_Q, T134_Q;
	always @(posedge CLK_24M or negedge T73A_OUT)
	begin
		if (!T73A_OUT)
		begin
			T140_Q <= 1'b0;
			T134_Q <= 1'b0;
		end
		else
		begin

			T140_Q <= (~T134_Q) ? ~T140_Q : 1'b0;

			T134_Q <= (T140_Q) ? ~T134_Q : 1'b0;
		end
	end
	
	reg U129A_Q;
	always @(negedge CLK_24M)
	begin

		U129A_Q <= ~T134_Q;

		EVEN2 <= U112_OUT;
	end
	
	assign T125A_OUT = ~U129A_Q | T140_Q;
	BD3 P198A(Q174B_OUT, P198A_OUT);
	FS1 P201(LSPC_12M, P198A_OUT, P201_Q);
	assign P219A_OUT = ~|{O159_QB, ~P201_Q[0]};
	assign P222A_OUT = ~&{P219A_OUT, ~P201_Q[1]};
	assign CLK_SPR_TILE = P201_Q[1];
	assign R94A_OUT = ~&{P201_Q[2], R91_Q};
	assign D208B_OUT = ~P201_Q[3];
	
	

	

	LT4 T31(LSPC_12M, {T38A_OUT, T28_OUT, T29A_OUT, T20B_OUT}, T31_P);

	LT4 U24(LSPC_12M, {U37B_OUT, U21B_OUT, U35A_OUT, U31A_OUT}, U24_P);
	

	assign WE1 = ~&{T31_P[0], LSPC_12M};
	assign WE2 = ~&{T31_P[1], LSPC_12M};
	assign CK1 = ~&{T31_P[2], LSPC_12M};
	assign CK2 = ~&{T31_P[3], LSPC_12M};
	
	assign WE3 = ~&{U24_P[2], LSPC_12M};
	assign WE4 = ~&{U24_P[3], LSPC_12M};
	assign CK3 = ~&{U24_P[0], LSPC_12M};
	assign CK4 = ~&{U24_P[1], LSPC_12M};
	
	assign WE = {WE4, WE3, WE2, WE1};
	assign CK = {CK4, CK3, CK2, CK1};
	

	


	assign T22A_OUT = ~&{T50B_OUT, SS1};
	assign T40B_OUT = ~&{T48A_OUT, SS1};

	assign T50A_OUT = ~&{WRITEPX_A, CHG_D};
	assign T40A_OUT = ~&{WRITEPX_B, CHG_D};

	assign T17A_OUT = ~&{DOTA, ~T50A_OUT};
	assign T22B_OUT = ~&{DOTB, ~T40A_OUT};

	assign T20B_OUT = ~&{T22A_OUT, T17A_OUT};
	assign T29A_OUT = ~&{T40B_OUT, T22B_OUT};

	assign T28_OUT = ~&{T22A_OUT, LD1_D, T50A_OUT};
	assign T38A_OUT = ~&{T40B_OUT, T40A_OUT, LD1_D};
	


	assign U33B_OUT = ~&{T48A_OUT, SS2};
	assign T20A_OUT = ~&{T50B_OUT, SS2};

	assign U51B_OUT = ~&{WRITEPX_A, nCHG_D};
	assign U39B_OUT = ~&{WRITEPX_B, nCHG_D};

	assign U18A_OUT = ~&{DOTA, ~U51B_OUT};
	assign U38A_OUT = ~&{DOTB, ~U39B_OUT};

	assign U21B_OUT = ~&{T20A_OUT, U18A_OUT};
	assign U37B_OUT = ~&{U33B_OUT, U38A_OUT};

	assign U35A_OUT = ~&{LD2_D, U33B_OUT, U39B_OUT};
	assign U31A_OUT = ~&{LD2_D, T20A_OUT, U51B_OUT};
	
	

	assign T50B_OUT = LSPC_3M & LSPC_6M;
	assign T48A_OUT = ~LSPC_3M & LSPC_6M;
	
	

	assign U89A_OUT = ~&{nHSHRINK_OUT_B, nEVEN_ODD, HSHRINK_OUT_A};
	assign U92A_OUT = ~&{nHSHRINK_OUT_A, nEVEN_ODD, HSHRINK_OUT_B};
	assign U91_OUT = ~&{nHSHRINK_OUT_B, EVEN_nODD, HSHRINK_OUT_A};
	assign U94_OUT = ~&{nHSHRINK_OUT_A, EVEN_nODD, HSHRINK_OUT_B};

	assign U88B_OUT = HSHRINK_OUT_A | HSHRINK_OUT_B;
	assign U85_OUT = &{U89A_OUT, U92A_OUT, U88B_OUT};
	assign U86A_OUT = &{U88B_OUT, U94_OUT, U91_OUT};

	FD2 T82A(CLK_24M, U85_OUT, WRITEPX_A);
	FD2 T86(CLK_24M, U86A_OUT, WRITEPX_B);
	
	


	FDM R50(LSPC_3M, FLIP_nQ, R50_Q, R50_nQ);
	

	FDM R69(LSPC_3M, LSPC_1_5M, R69_Q, R69_nQ);
	FDM S55(LSPC_12M, LSPC_3M, S55_Q);
	assign S53A_OUT = S55_Q & LSPC_6M;

	FD2 R35A(CLK_24MB, S53A_OUT, LOAD);
	


	assign nCHAINED = ~|{PIPE_C[13], R69_nQ};

	assign R44B_OUT = ~&{R50_nQ, R53_Q};

	assign R48B_OUT = ~&{nCHAINED, R50_Q};

	assign R42B_OUT = ~&{R44B_OUT, R48B_OUT};

	assign LD1_D = ~&{R42B_OUT, S53A_OUT};
	FD2 R32(CLK_24MB, LD1_D, LD1);
	


	assign R44A_OUT = ~&{R53_Q, R50_Q};

	assign R46A_OUT = ~&{R50_nQ, nCHAINED};

	assign R46B_OUT = ~&{R44A_OUT, R46A_OUT};

	assign LD2_D = ~&{R46B_OUT, S53A_OUT};
	FD2 R28A(CLK_24MB, LD2_D, LD2);
	



	FDPCell O62(PIXELC[3], PIXELC[8], 1'b1, nRESETP, O62_Q);

	FDPCell P74(PIXELC[2], O62_Q, 1'b1, nRESETP, P74_Q);

	FDM R53(LSPC_3M, R67A_OUT, R53_Q);
	assign R67A_OUT = R74_nQ & P74_Q;
	FDPCell R74(LSPC_1_5M, P74_Q, 1'b1, nRESETP, , R74_nQ);
	


	assign R48A_OUT = ~&{S53A_OUT, R69_Q};
	FD2 R56A(CLK_24MB, R48A_OUT, LD_HSHRINK_REG);
	
	

	FDPCell S137(LSPC_1_5M, CHG_D, 1'b1, nRESETP, CHG);
	

	FDPCell O69(CLK_24MB, nFLIP, nRESETP, 1'b1, , FLIP_nQ);
	FDPCell R63(PIXELC[2], FLIP_nQ, 1'b1, nRESETP, CHG_D, nCHG_D);
	FDM S48(LSPC_3M, R15_QD, , S48_nQ);

	assign SS1 = ~|{S48_nQ, CHG_D};

	assign SS2 = ~|{nCHG_D, S48_nQ};
	
	

	assign J20A_OUT = ~&{PIXELC[8:7]};

	assign PIXEL_HPLUS = 5'd15 + {~J20A_OUT, PIXELC[6:4]} + PIXELC[3];
	
	

	FDM R179(VCS, SPR_CONTINUOUS, R179_Q);

	assign S186_OUT = ~(~P235_OUT ^ R179_Q);
	assign SPRITEMAP_ADDR_MSB = ~S186_OUT;
	assign S166_OUT = VSHRINK_LINE[3] ^ ~S186_OUT;
	assign S164_OUT = VSHRINK_LINE[2] ^ ~S186_OUT;
	assign S162_OUT = VSHRINK_LINE[1] ^ ~S186_OUT;
	assign S168_OUT = VSHRINK_LINE[0] ^ ~S186_OUT;
	FDSCell O227(P222A_OUT, {S166_OUT, S164_OUT, S162_OUT, S168_OUT}, O227_Q);
	FDSCell G233(~P201_Q[1], O227_Q, G233_Q);
	assign SPR_LINE[0] = SPR_TILE_VFLIP ^ G233_Q[0];
	assign SPR_LINE[1] = SPR_TILE_VFLIP ^ G233_Q[1];
	assign SPR_LINE[2] = SPR_TILE_VFLIP ^ G233_Q[2];
	assign SPR_LINE[3] = SPR_TILE_VFLIP ^ G233_Q[3];
	assign Q184_OUT = VSHRINK_INDEX[3] ^ ~S186_OUT;
	assign Q182_OUT = VSHRINK_INDEX[2] ^ ~S186_OUT;
	assign Q186_OUT = VSHRINK_INDEX[1] ^ ~S186_OUT;
	assign Q172_OUT = VSHRINK_INDEX[0] ^ ~S186_OUT;
	FDSCell O175(P222A_OUT, {Q184_OUT, Q182_OUT, Q186_OUT, Q172_OUT}, SPR_TILEMAP);
	
	


	FDSCell Q87(VCS, PBUS_IO[23:20], VSHRINK_INDEX);
	FDSCell S141(VCS, PBUS_IO[19:16], VSHRINK_LINE);
	
	FDM R88(CLK_24M, R94A_OUT, R88_Q, R88_nQ);
	assign VCS = ~R88_nQ;
	
	
	assign T185B_OUT = PCK1 | PCK2;

	FDM S183(T185B_OUT, S171_Q, S183_Q);
	BD3 P196(S183_Q, S183_Q_DELAYED);
	FDM S171(U53_Q, LSPC_1_5M, S171_Q, S171_nQ);
	
	assign XPOS = PIPE_C[8:0];
	
	assign SPR_TILE_AA[2] = AUTOANIM3_EN ? AA_COUNT[2] : SPR_TILE[2];
	assign SPR_TILE_AA[1:0] = AUTOANIM2_EN ? AA_COUNT[1:0] : SPR_TILE[1:0];
	

	assign XPOS_ROUND_UP = XPOS[8:1] + XPOS[0];
	


	assign P_MUX_HIGH = R88_Q ? XPOS[8:1] : YSHRINK;
	


	assign LO_LINE_MUX = SPR_CONTINUOUS ? ~LO_LINE_B : LO_LINE_A;
	


	assign P_MUX_LOW = R88_Q ? XPOS_ROUND_UP : LO_LINE_MUX;
	
	



	assign P_OUT_MUX[23:16] = ~S183_Q_DELAYED ? 
										~S171_nQ ? 
											{SPR_PAL}
											:
											{SPR_TILE[19:16], SPR_LINE}
										:
										~S171_nQ ?
											{8'b00000000}
											:
											{4'b0000, FIX_PAL};
	




	assign P_OUT_MUX[15:0] = ~S183_Q_DELAYED ?
										~S171_nQ ?
											{P_MUX_HIGH, P_MUX_LOW}
											:
											{SPR_TILE[15:8], SPR_TILE[7:3], SPR_TILE_AA}
										:
										~S171_nQ ?
											{PIXELC[2], RASTERC[2:1], FLIP, FIX_TILE[11:8], FIX_TILE[7:0]}
											:
											{8'b00000000, 8'b00000000};
	
	assign PBUS_IO = nPBUS_OUT_EN ? 8'bzzzzzzzz : P_OUT_MUX[23:16];
	assign PBUS_OUT = P_OUT_MUX[15:0];
	
	


	assign SPR_Y_LOOKAHEAD = {RASTERC[7:1], FLIP} + 1'b1;

	assign SPR_Y_ADD = SPR_Y_LOOKAHEAD + SPR_Y[7:0];


	assign LO_LINE_A = SPR_Y_ADD[7:0] ^ {8{~P235_OUT}};
	assign P235_OUT = ~(SPR_Y[8] ^ SPR_Y_ADD[8]);

	assign SPR_Y_SHRINK = LO_LINE_A + {1'b0, ~YSHRINK};

	assign LO_LINE_B = LO_LINE_A + {~YSHRINK[6:0], 1'b0};
	


	assign SPR_CONTINUOUS = &{SPR_SIZE0, SPR_SIZE5, SPR_Y_SHRINK[8]};
	
	lspc_regs REGS(RESET, nRESETP, M68K_ADDR, M68K_DATA, LSPOE, LSPWE, VMODE, RASTERC, AA_COUNT, VRAM_LOW_READ,
					VRAM_HIGH_READ, WR_VRAM_ADDR, WR_VRAM_RW, WR_TIMER_HIGH, WR_TIMER_LOW, WR_IRQ_ACK, REG_VRAMADDR,
					REG_VRAMMOD, REG_VRAMRW, REG_LSPCMODE, CPU_DATA_OUT, AA_SPEED,	TIMER_MODE,	TIMER_IRQ_EN,
					AA_DISABLE, TIMER_STOP, nVRAM_WRITE_REQ, D112B_OUT);
	
	lspc_timer TIMER(LSPC_6M, nRESETP, M68K_DATA, WR_TIMER_HIGH, WR_TIMER_LOW, VMODE, TIMER_MODE, TIMER_STOP,
						RASTERC, TIMER_IRQ_EN, R74_nQ, BNKB, D46A_OUT);
	
	resetp RSTP(CLK_24MB, RESET, nRESETP);
	
	irq IRQ(WR_IRQ_ACK, M68K_DATA[2:0], RESET, D46A_OUT, BNK, LSPC_6M, IPL0, IPL1);
	
	videosync VS(CLK_24MB, LSPC_3M, LSPC_1_5M, Q53_CO, nRESETP, VMODE, PIXELC, RASTERC, HSYNC, VSYNC, BNK,
						BNKB, CHBL, R15_QD, FLIP, nFLIP, P50_CO);

	lspc2_clk LSPCCLK(CLK_24M, nRESETP, CLK_24MB, LSPC_12M, LSPC_8M, LSPC_6M, LSPC_4M, LSPC_3M, LSPC_1_5M,
							Q53_CO);
	
	slow_cycle SCY(CLK_24M, CLK_24MB, LSPC_12M, LSPC_6M, LSPC_3M, LSPC_1_5M, nRESETP, VRAM_ADDR[14:0], VRAM_WRITE,
							REG_VRAMADDR[15], PIXELC[3], PIXELC[8], RASTERC[7:3], PIXEL_HPLUS, ACTIVE_RD,
							nVRAM_WRITE_REQ, SPR_TILEMAP, SPR_TILE_VFLIP, SPR_TILE_HFLIP, SPR_AA_3, SPR_AA_2,
							FIX_TILE, FIX_PAL, SPR_TILE, SPR_PAL, VRAM_LOW_READ, nCPU_WR_LOW, R91_nQ,
							CLK_CPU_READ_LOW, T160A_OUT, T160B_OUT, CLK_ACTIVE_RD, ACTIVE_RD_PRE8, Q174B_OUT,
							D208B_OUT, SPRITEMAP_ADDR_MSB, CLK_SPR_TILE, P222A_OUT, ~P201_Q[1],
							SVRAM_ADDR, SVRAM_DATA_IN, SVRAM_DATA_OUT, BOE, BWE, FIXMAP_ADDR);
	
	fast_cycle FCY(CLK_24M, LSPC_12M, LSPC_6M, LSPC_3M, LSPC_1_5M, nRESETP, nVRAM_WRITE_REQ,
							VRAM_ADDR, VRAM_WRITE, REG_VRAMADDR[15], FLIP, nFLIP,
							PIXELC, RASTERC, P50_CO, nCPU_WR_HIGH, HSHRINK, PIPE_C, VRAM_HIGH_READ,
							ACTIVE_RD, R91_Q, R91_nQ, T140_Q, T58A_OUT, T73A_OUT, U129A_Q, T125A_OUT,
							CLK_ACTIVE_RD, ACTIVE_RD_PRE8, SPR_Y, YSHRINK, SPR_SIZE0, SPR_SIZE5, O159_QB,
							FVRAM_ADDR, FVRAM_DATA_IN, FVRAM_DATA_OUT, CWE);
	
	autoanim AA(RASTERC[8], nRESETP, AA_SPEED, AA_COUNT);
	
	hshrink HSH(HSHRINK, CK_HSHRINK_REG, LD_HSHRINK_REG, HSHRINK_OUT_A, HSHRINK_OUT_B);
	wire nHSHRINK_OUT_A = ~HSHRINK_OUT_A;
	wire nHSHRINK_OUT_B = ~HSHRINK_OUT_B;
	
endmodule