data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/MAXPOOL2.v
'utf-8' codec can't decode byte 0xe7 in position 525: invalid continuation byte
1: b'%Warning-WIDTH: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/MAXPOOL2.v:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                      : ... In instance MAXPOOL2\n output reg [3:0]  mx2_count =1\'b0,  \n                              ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/MAXPOOL2.v:17: Operator ASSIGN expects 36 bits on the Assign RHS, but Assign RHS\'s CONST \'35\'h0\' generates 35 bits.\n                                                                                                      : ... In instance MAXPOOL2\n    reg [35:0] temp1 = 35\'d0, temp2 = 35\'d0;\n                       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/MAXPOOL2.v:17: Operator ASSIGN expects 36 bits on the Assign RHS, but Assign RHS\'s CONST \'35\'h0\' generates 35 bits.\n                                                                                                      : ... In instance MAXPOOL2\n    reg [35:0] temp1 = 35\'d0, temp2 = 35\'d0;\n                                      ^~~~~\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/MAXPOOL2.v:22: Cannot find file containing module: \'counter_8\'\n    counter_8 counter8 (  \n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/counter_8\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/counter_8.v\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/counter_8.sv\n             counter_8\n             counter_8.v\n             counter_8.sv\n             obj_dir/counter_8\n             obj_dir/counter_8.v\n             obj_dir/counter_8.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module MAXPOOL2(
    input  [35:0] mx2_input,
    input  clk,
    input  enable,
    input  reset,
    input  read_strobe,
	output reg [1:0]  mx2_done,
	output reg [3:0]  mx2_count =1'b0,
    output reg [35:0] mx2_output
    );
    
	wire [35:0] mx2_input_reg;
    wire [3:0] count1, count2;
    wire done;
    reg [35:0] temp1 = 35'd0, temp2 = 35'd0;

	 
	assign mx2_input_reg = mx2_input;
	 
    counter_8 counter8 (
        .clk(clk), 
        .start(enable), 
        .reset(reset), 
        .count1(count1), 
        .count2(count2), 
        .done(done)
        );
        



    always @(posedge clk)
    begin
    if(reset)
        mx2_count <= 0;
    else if (done)
        mx2_count <= mx2_count + 1;
    else if((mx2_count % 4) == 0 )
        mx2_count <= 0;
    end    
      
    always @(posedge clk)
    begin 
        if(enable && (( count2 == 3 )|( count2 == 7 )))
			begin
			if(count1 == 4)
				begin mx2_output <= temp1; mx2_done <= 1; end
			else if(count1 == 8)
				begin mx2_output <= temp2; mx2_done <= 2; end
			else 
				begin mx2_output <= -1;    mx2_done <= 0; end
			end
		else  mx2_done <= 0;
    end  
    
    always @ (posedge clk)
    begin
		 if(reset || (mx2_done == 2))
		 begin 

            temp1 <= 0; temp2 <= 0;  
		 end
		 else if(read_strobe && enable) begin
           if(count1 <  4 && temp1 < mx2_input_reg)
                temp1 <= mx2_input_reg;
           if(count1 >= 4 && count1  < 8 && temp2 < mx2_input_reg)
                temp2 <= mx2_input_reg;
		 end
    end     
        
endmodule
module MAXPOOL2(
    input  [35:0] mx2_input,
    input  clk,
    input  enable,
    input  reset,
    input  read_strobe,
	output reg [1:0]  mx2_done,
	output reg [3:0]  mx2_count =1'b0,
    output reg [35:0] mx2_output
    );

    
	wire [35:0] mx2_input_reg;
    wire [3:0] count1, count2;
    wire done;
    reg [35:0] temp1 = 35'd0, temp2 = 35'd0;

	 
	assign mx2_input_reg = mx2_input;
	 
    counter_8 counter8 (
        .clk(clk), 
        .start(enable), 
        .reset(reset), 
        .count1(count1), 
        .count2(count2), 
        .done(done)
        );
        



    always @(posedge clk)
    begin
    if(reset)
        mx2_count <= 0;
    else if (done)
        mx2_count <= mx2_count + 1;
    else if((mx2_count % 4) == 0 )
        mx2_count <= 0;
    end    
      
    always @(posedge clk)
    begin 
        if(enable && (( count2 == 3 )|( count2 == 7 )))
			begin
			if(count1 == 4)
				begin mx2_output <= temp1; mx2_done <= 1; end
			else if(count1 == 8)
				begin mx2_output <= temp2; mx2_done <= 2; end
			else 
				begin mx2_output <= -1;    mx2_done <= 0; end
			end
		else  mx2_done <= 0;
    end  
    
    always @ (posedge clk)
    begin
		 if(reset || (mx2_done == 2))
		 begin 

            temp1 <= 0; temp2 <= 0;  
		 end
		 else if(read_strobe && enable) begin
           if(count1 <  4 && temp1 < mx2_input_reg)
                temp1 <= mx2_input_reg;
           if(count1 >= 4 && count1  < 8 && temp2 < mx2_input_reg)
                temp2 <= mx2_input_reg;
		 end
    end     
        
endmodule