data/full_repos/permissive/143278/ivltests/pr3306516.v
 line:37: before: "ta"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3306516.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (y !== 1\'bx && y !== 1\'bz) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3306516.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (y !== 1\'b0) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3306516.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (y !== 1\'b0) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3306516.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #2 if (y !== 1\'b1) begin\n    ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module my_and(output wire y, input wire a, b);
  specify
    specparam ta = 1;
    specparam tb = 2;
  endspecify




  assign #(ta+tb) y = a & b;
endmodule
module my_and(output wire y, input wire a, b);

  specify
    specparam ta = 1;
    specparam tb = 2;
  endspecify




  assign #(ta+tb) y = a & b;
endmodule