data/full_repos/permissive/143278/ivltests/pr1868792.v
 line:5: before: "["
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1868792.v:26: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'pass\' generates 32 bits.\n                                                                         : ... In instance top\n    if (pass) $display("PASSED");\n    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top;
  parameter amax = 9;
  reg [31:0] mem [amax:0];
  integer i, tmp;
  integer fail [amax:0];
  integer pass;

  initial begin
    pass = 1;
    for (i=0; i<amax; i=i+1) begin
      fail[i] = i;
      mem[i] = i;
    end
    for (i=0; i<(amax-1); i=i+1) begin
      mem[fail[i]] = mem[fail[i]] + 1;


    end
    for (i=0; i<(amax-1); i=i+1) begin
      if (mem[i] != i+1) begin
        pass = 0;
        $display("Failed location %d, value was %d, expected %d",
                 i, mem[i], i+1);
      end
    end
    if (pass) $display("PASSED");
  end
endmodule
module top;

  parameter amax = 9;
  reg [31:0] mem [amax:0];
  integer i, tmp;
  integer fail [amax:0];
  integer pass;

  initial begin
    pass = 1;
    for (i=0; i<amax; i=i+1) begin
      fail[i] = i;
      mem[i] = i;
    end
    for (i=0; i<(amax-1); i=i+1) begin
      mem[fail[i]] = mem[fail[i]] + 1;


    end
    for (i=0; i<(amax-1); i=i+1) begin
      if (mem[i] != i+1) begin
        pass = 0;
        $display("Failed location %d, value was %d, expected %d",
                 i, mem[i], i+1);
      end
    end
    if (pass) $display("PASSED");
  end
endmodule