data/full_repos/permissive/184431263/BUF/INV.v
data/verilator_xmls/ca5fec68-846b-47c8-bbe1-9ac39bdc1cf6.xml
module INV(Y, A, VDD, VSS );
  input A;
  output Y;
  inout VDD, VSS;

  assign Y = A ? VSS : VDD ;
endmodule
module INV(Y, A, VDD, VSS );

  input A;
  output Y;
  inout VDD, VSS;

  assign Y = A ? VSS : VDD ;
endmodule