data/full_repos/permissive/105948944/sources/sensorIR.v
1: b'%Error: data/full_repos/permissive/105948944/sources/sensorIR.v:33: Cannot find file containing module: \'signalSync\'\n    signalSync sync_IR0(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync\n             data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync.v\n             data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/signalSync.sv\n             signalSync\n             signalSync.v\n             signalSync.sv\n             obj_dir/signalSync\n             obj_dir/signalSync.v\n             obj_dir/signalSync.sv\n%Error: data/full_repos/permissive/105948944/sources/sensorIR.v:40: Cannot find file containing module: \'signalSync\'\n     signalSync sync_IR1(\n     ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/105948944/sources/sensorIR.v:61: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'rebuiltSignal_reg\' generates 2 bits.\n                                                                          : ... In instance sensorIR\n        if ( rebuiltSignal_reg )\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module sensorIR(
    input clock,
    input [1:0] IR_sensors,
    output reg IR_sensed
    );
    
    reg [1:0] rebuiltSignal_reg;
    wire [1:0] rising_edge_wire;
    wire [1:0] falling_edge_wire;
    
    signalSync sync_IR0(
            .clock(clock),
            .asynchronous_signal(~IR_sensors[0]),
            .rising_edge(rising_edge_wire[0]),
            .falling_edge(falling_edge_wire[0])
        );
        
     signalSync sync_IR1(
            .clock(clock),
            .asynchronous_signal(~IR_sensors[1]),
            .rising_edge(rising_edge_wire[1]),
            .falling_edge(falling_edge_wire[1])
        );
    always@(posedge clock) begin
            if (rising_edge_wire[0])
                rebuiltSignal_reg[0] <= 1;
            else if (falling_edge_wire[0])
                rebuiltSignal_reg[0] <= 0;
    end
    
    always@(posedge clock) begin
            if (rising_edge_wire[1])
                rebuiltSignal_reg[1] <= 1;
            else if (falling_edge_wire[1])
                rebuiltSignal_reg[1] <= 0;
    end
       
    always@(negedge clock) begin
        if ( rebuiltSignal_reg )
            IR_sensed <= 1;
        else
            IR_sensed <= 0;
    end 
        
endmodule
module sensorIR(
    input clock,
    input [1:0] IR_sensors,
    output reg IR_sensed
    );

    
    reg [1:0] rebuiltSignal_reg;
    wire [1:0] rising_edge_wire;
    wire [1:0] falling_edge_wire;
    
    signalSync sync_IR0(
            .clock(clock),
            .asynchronous_signal(~IR_sensors[0]),
            .rising_edge(rising_edge_wire[0]),
            .falling_edge(falling_edge_wire[0])
        );
        
     signalSync sync_IR1(
            .clock(clock),
            .asynchronous_signal(~IR_sensors[1]),
            .rising_edge(rising_edge_wire[1]),
            .falling_edge(falling_edge_wire[1])
        );
    always@(posedge clock) begin
            if (rising_edge_wire[0])
                rebuiltSignal_reg[0] <= 1;
            else if (falling_edge_wire[0])
                rebuiltSignal_reg[0] <= 0;
    end
    
    always@(posedge clock) begin
            if (rising_edge_wire[1])
                rebuiltSignal_reg[1] <= 1;
            else if (falling_edge_wire[1])
                rebuiltSignal_reg[1] <= 0;
    end
       
    always@(negedge clock) begin
        if ( rebuiltSignal_reg )
            IR_sensed <= 1;
        else
            IR_sensed <= 0;
    end 
        
endmodule