data/full_repos/permissive/136510272/icarus/main.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/136510272/icarus/main.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk         = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136510272/icarus/main.v:10: Unsupported: Ignoring delay on this delayed statement.\ninitial begin clk = 1; #2000 $finish; end\n                       ^\n%Error: data/full_repos/permissive/136510272/icarus/main.v:11: Unsupported or unknown PLI call: $dumpfile\ninitial begin $dumpfile("main.vcd"); $dumpvars(0, main); end\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/icarus/main.v:11: Unsupported or unknown PLI call: $dumpvars\ninitial begin $dumpfile("main.vcd"); $dumpvars(0, main); end\n                                     ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;



reg         clk;
always #0.5 clk         = ~clk;

initial begin clk = 1; #2000 $finish; end
initial begin $dumpfile("main.vcd"); $dumpvars(0, main); end



endmodule
module main;




reg         clk;
always #0.5 clk         = ~clk;

initial begin clk = 1; #2000 $finish; end
initial begin $dumpfile("main.vcd"); $dumpvars(0, main); end



endmodule