data/full_repos/permissive/10379745/hw_de0/hard/hp_display/hp_display.sv
 line:58 column:26: Illegal character "'"
1: b'%Error: data/full_repos/permissive/10379745/hw_de0/hard/hp_display/hp_display.sv:74: Cannot find include file: log2.inc\n`include "log2.inc" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc\n             data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc.v\n             data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc.sv\n             log2.inc\n             log2.inc.v\n             log2.inc.sv\n             obj_dir/log2.inc\n             obj_dir/log2.inc.v\n             obj_dir/log2.inc.sv\n%Error: Exiting due to 1 error(s)\n'
module hp_display ( input         CLK,
                    input         RESET,

                    input         WE,
                    input   [3:0] A,
                    input  [31:0] WD,
                    output [31:0] RD,

                    output        HP_CE,
                    output        HP_RS,
                    output        HP_RESET,
                    output        HP_BLANK,
                    output        HP_DO,
                    output        HP_CLK );

logic [4:0] bits_q;
logic       shift, shifting, done, dot_sel, ctrl_sel;

assign dot_sel  = (A == 4'd0);
assign ctrl_sel = (A == 4'd1); 

ffd #(5) bits_fd(CLK, RESET, WE & ctrl_sel, WD[4:0], bits_q);

rsd en_reg(CLK, RESET | (shift & done), WE & (A == 4'd0), shifting);

so_reg_left #(8) sreg( .CLK    ( CLK          ),
                       .UPDATE ( WE & dot_sel ),
                       .SHIFT  ( shift        ),
                       .DATA   ( WD[7:0]      ),
                       .OUT    ( HP_DO        ),
                       .EMPTY  ( done         ) );

hp_clk_div hp_clk_div( .CLK    ( CLK          ), 
                       .RESET  ( WE & dot_sel ),
                       .EN     ( shifting     ),
                       .SHIFT  ( shift        ),
                       .HP_CLK ( HP_CLK       ) );

assign HP_RESET  = ~bits_q[4];

assign HP_BLANK  =  bits_q[2];
assign HP_RS     =  bits_q[1];
assign HP_CE     = ~bits_q[0];

assign RD = {31'd0, shifting};

endmodule
module hp_display ( input         CLK,
                    input         RESET,

                    input         WE,
                    input   [3:0] A,
                    input  [31:0] WD,
                    output [31:0] RD,

                    output        HP_CE,
                    output        HP_RS,
                    output        HP_RESET,
                    output        HP_BLANK,
                    output        HP_DO,
                    output        HP_CLK );


logic [4:0] bits_q;
logic       shift, shifting, done, dot_sel, ctrl_sel;

assign dot_sel  = (A == 4'd0);
assign ctrl_sel = (A == 4'd1); 

ffd #(5) bits_fd(CLK, RESET, WE & ctrl_sel, WD[4:0], bits_q);

rsd en_reg(CLK, RESET | (shift & done), WE & (A == 4'd0), shifting);

so_reg_left #(8) sreg( .CLK    ( CLK          ),
                       .UPDATE ( WE & dot_sel ),
                       .SHIFT  ( shift        ),
                       .DATA   ( WD[7:0]      ),
                       .OUT    ( HP_DO        ),
                       .EMPTY  ( done         ) );

hp_clk_div hp_clk_div( .CLK    ( CLK          ), 
                       .RESET  ( WE & dot_sel ),
                       .EN     ( shifting     ),
                       .SHIFT  ( shift        ),
                       .HP_CLK ( HP_CLK       ) );

assign HP_RESET  = ~bits_q[4];

assign HP_BLANK  =  bits_q[2];
assign HP_RS     =  bits_q[1];
assign HP_CE     = ~bits_q[0];

assign RD = {31'd0, shifting};

endmodule