data/full_repos/permissive/212394344/DependencyCheckBlock_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/212394344/DependencyCheckBlock_TB.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212394344/DependencyCheckBlock_TB.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #400;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/DependencyCheckBlock_TB.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #800;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/DependencyCheckBlock_TB.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/DependencyCheckBlock_TB.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/DependencyCheckBlock_TB.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/DependencyCheckBlock_TB.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #500 clk = ~clk;\n  ^\n%Error: data/full_repos/permissive/212394344/DependencyCheckBlock_TB.v:44: Cannot find file containing module: \'DependencyCheckBlock\'\n DependencyCheckBlock uut (\n ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/DependencyCheckBlock\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/DependencyCheckBlock.v\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/DependencyCheckBlock.sv\n             DependencyCheckBlock\n             DependencyCheckBlock.v\n             DependencyCheckBlock.sv\n             obj_dir/DependencyCheckBlock\n             obj_dir/DependencyCheckBlock.v\n             obj_dir/DependencyCheckBlock.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DependencyCheckBlock_TB;


	reg [23:0] ins;
	reg clk;
	reg reset;


	wire [7:0] imm;
	wire [4:0] RW_dm;
	wire [4:0] op_dec;
	wire [1:0] mux_sel_A;
	wire [1:0] mux_sel_B;
	wire imm_sel;
	wire mem_en_ex;
	wire mem_rw_ex;
	wire mem_mux_sel_dm;


	DependencyCheckBlock uut (
		.imm(imm), 
		.RW_dm(RW_dm), 
		.op_dec(op_dec), 
		.mux_sel_A(mux_sel_A), 
		.mux_sel_B(mux_sel_B), 
		.imm_sel(imm_sel), 
		.mem_en_ex(mem_en_ex), 
		.mem_rw_ex(mem_rw_ex), 
		.mem_mux_sel_dm(mem_mux_sel_dm), 
		.ins(ins), 
		.clk(clk), 
		.reset(reset)
	);

	initial begin

		reset = 1'b1;
		clk = 1'b0;

	
		#200;
		reset = 1'b0;
		
		#400;
		reset = 1'b1;
		
		#800;
		ins = 24'b00000_00001_00010_00011_0000;
		
		#1000;
		ins = 24'b10100_00100_00001_00000_0000;
		
		#2000;
		ins = 24'b00100_00101_00001_00100_0000;
		
		#1000;
		ins = 24'b01101_00110_00001_00000_1010;

	end
	
	
		always
		#500 clk = ~clk;
      
endmodule
module DependencyCheckBlock_TB;



	reg [23:0] ins;
	reg clk;
	reg reset;


	wire [7:0] imm;
	wire [4:0] RW_dm;
	wire [4:0] op_dec;
	wire [1:0] mux_sel_A;
	wire [1:0] mux_sel_B;
	wire imm_sel;
	wire mem_en_ex;
	wire mem_rw_ex;
	wire mem_mux_sel_dm;


	DependencyCheckBlock uut (
		.imm(imm), 
		.RW_dm(RW_dm), 
		.op_dec(op_dec), 
		.mux_sel_A(mux_sel_A), 
		.mux_sel_B(mux_sel_B), 
		.imm_sel(imm_sel), 
		.mem_en_ex(mem_en_ex), 
		.mem_rw_ex(mem_rw_ex), 
		.mem_mux_sel_dm(mem_mux_sel_dm), 
		.ins(ins), 
		.clk(clk), 
		.reset(reset)
	);

	initial begin

		reset = 1'b1;
		clk = 1'b0;

	
		#200;
		reset = 1'b0;
		
		#400;
		reset = 1'b1;
		
		#800;
		ins = 24'b00000_00001_00010_00011_0000;
		
		#1000;
		ins = 24'b10100_00100_00001_00000_0000;
		
		#2000;
		ins = 24'b00100_00101_00001_00100_0000;
		
		#1000;
		ins = 24'b01101_00110_00001_00000_1010;

	end
	
	
		always
		#500 clk = ~clk;
      
endmodule