data/full_repos/permissive/117026779/sim/Test_PWMCapture.v
 line:55: before: "("
1: b'%Error: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:34: syntax error, unexpected \';\', expecting IDENTIFIER or do or final\nwire int;\n        ^\n%Error: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:46: syntax error, unexpected int\n    .int(int),    \n     ^~~\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:53: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:56: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:65: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:71: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Error: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:80: syntax error, unexpected !=, expecting "\'{"\n if(int != bit_value)\n        ^~\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:79: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Error: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:83: syntax error, unexpected \',\', expecting "\'{"\n  $display("!!ERROR!! @ %d INTERRUPT FLAG %d !== %d", $time, int, bit_value);\n                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Error: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:87: syntax error, unexpected end\nend\n^~~\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:111: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:113: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:115: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:148: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_PWMCapture.v:149: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: Exiting due to 5 error(s), 13 warning(s)\n'
module Test_PWMCapture;

reg success_flag;

reg clk, rst;
reg oe, clr;
reg ext_pwm;
reg trigger;
reg int_clr;
wire [31:0] data;
wire int;

integer i;

PWMCapture U0 (
    .clk(clk),
    .rst(rst),
    .oe(oe),
    .clr(clr),
    .trigger(trigger),
    .ext_pwm(ext_pwm),
    .int_clr(int_clr),
    .int(int),
    .data(data)
);

task STROBE_TRIGGER;
begin
	trigger = 0;
	#1000
	trigger = 1;
    CLOCK(1);
	#1000
	trigger = 0;
end
endtask

task CHECK_OUTPUT;
	input [31:0] value;
begin
	oe = 1;
	#1000
	if(data != value)
	begin
		success_flag = 0;
		$display("!!ERROR!! @ %d 0x%X !== 0x%X", $time, data, value);
	end
	#1
	oe = 0;
end
endtask;

task CHECK_INTERRUPT;
	input bit_value;
begin
	#1
	if(int != bit_value)
	begin
		success_flag = 0;
		$display("!!ERROR!! @ %d INTERRUPT FLAG %d !== %d", $time, int, bit_value);
	end
	#1
	oe = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
	end
end
endtask

initial
begin
	success_flag = 1;
    rst = 0;
    clk = 0;
    oe = 0;
    trigger = 0;
    #5
    rst = 1;
    #5
    rst = 0;
	#5

	ext_pwm = 0;
	STROBE_TRIGGER;
	ext_pwm = 1;
	CLOCK(1000);
	ext_pwm = 0;
	CLOCK(1);
    CHECK_OUTPUT(1000);
	CHECK_INTERRUPT(1);

	CLOCK(1000);

	ext_pwm = 0;
	STROBE_TRIGGER;
	CHECK_INTERRUPT(0);
	ext_pwm = 1;
	CLOCK(2000);
	CHECK_INTERRUPT(0);
	CLOCK(5000);
	ext_pwm = 0;
	CLOCK(1);
	CHECK_OUTPUT(7000);
	CHECK_INTERRUPT(1);


	if (success_flag == 0) begin
		$display("*FAILED* TEST!");
	end
	else begin
		$display("**PASSED** TEST!");
	end

    #10 $stop;
    #5 $finish;
end

endmodule
module Test_PWMCapture;


reg success_flag;

reg clk, rst;
reg oe, clr;
reg ext_pwm;
reg trigger;
reg int_clr;
wire [31:0] data;
wire int;

integer i;

PWMCapture U0 (
    .clk(clk),
    .rst(rst),
    .oe(oe),
    .clr(clr),
    .trigger(trigger),
    .ext_pwm(ext_pwm),
    .int_clr(int_clr),
    .int(int),
    .data(data)
);

task STROBE_TRIGGER;
begin
	trigger = 0;
	#1000
	trigger = 1;
    CLOCK(1);
	#1000
	trigger = 0;
end
endtask

task CHECK_OUTPUT;
	input [31:0] value;
begin
	oe = 1;
	#1000
	if(data != value)
	begin
		success_flag = 0;
		$display("!!ERROR!! @ %d 0x%X !== 0x%X", $time, data, value);
	end
	#1
	oe = 0;
end
endtask;

task CHECK_INTERRUPT;
	input bit_value;
begin
	#1
	if(int != bit_value)
	begin
		success_flag = 0;
		$display("!!ERROR!! @ %d INTERRUPT FLAG %d !== %d", $time, int, bit_value);
	end
	#1
	oe = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
	end
end
endtask

initial
begin
	success_flag = 1;
    rst = 0;
    clk = 0;
    oe = 0;
    trigger = 0;
    #5
    rst = 1;
    #5
    rst = 0;
	#5

	ext_pwm = 0;
	STROBE_TRIGGER;
	ext_pwm = 1;
	CLOCK(1000);
	ext_pwm = 0;
	CLOCK(1);
    CHECK_OUTPUT(1000);
	CHECK_INTERRUPT(1);

	CLOCK(1000);

	ext_pwm = 0;
	STROBE_TRIGGER;
	CHECK_INTERRUPT(0);
	ext_pwm = 1;
	CLOCK(2000);
	CHECK_INTERRUPT(0);
	CLOCK(5000);
	ext_pwm = 0;
	CLOCK(1);
	CHECK_OUTPUT(7000);
	CHECK_INTERRUPT(1);


	if (success_flag == 0) begin
		$display("*FAILED* TEST!");
	end
	else begin
		$display("**PASSED** TEST!");
	end

    #10 $stop;
    #5 $finish;
end

endmodule