data/full_repos/permissive/143278/ivltests/sv_end_label.v
 line:4: before: ":"
1: b'%Error: data/full_repos/permissive/143278/ivltests/sv_end_label.v:6: Unsupported: fork statements\n  initial fork:fj_label\n          ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/sv_end_label.v:9: Unsupported: fork statements\n  initial fork:fja_label\n          ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/sv_end_label.v:12: Unsupported: fork statements\n  initial fork:fjn_label\n          ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/sv_end_label.v:46: Unsupported: classes\n  class foo;\n  ^~~~~\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module extra;
  parameter add_inv = 1;
  reg a;
  wire y, yb;
  pbuf dut(y, a);

  if (add_inv) begin: g_label
    pinv dut2(yb, y);
  end: g_label

endmodule
module extra;

  parameter add_inv = 1;
  reg a;
  wire y, yb;
  pbuf dut(y, a);

  if (add_inv) begin: g_label
    pinv dut2(yb, y);
  end: g_label

endmodule