data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v
 line:44: before: "integer"
1: b'%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v:78: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'r_row\' generates 5 bits.\n                                                                                                         : ... In instance oled_performance_counters\n  assign offset = r_page * C_ROWS + r_row;\n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v:92: Operator GTE expects 32 or 7 bits on the LHS, but LHS\'s ARRAYSEL generates 6 bits.\n                                                                                                         : ... In instance oled_performance_counters\n     offset + 0 >= C_COUNTER_N ? 1\'b0 : (r_pc[offset + 0] >= r_col + \'d1),\n                                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v:93: Operator GTE expects 32 or 7 bits on the LHS, but LHS\'s ARRAYSEL generates 6 bits.\n                                                                                                         : ... In instance oled_performance_counters\n     offset + 1 >= C_COUNTER_N ? 1\'b0 : (r_pc[offset + 1] >= r_col + \'d1),\n                                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v:94: Operator GTE expects 32 or 7 bits on the LHS, but LHS\'s ARRAYSEL generates 6 bits.\n                                                                                                         : ... In instance oled_performance_counters\n     offset + 2 >= C_COUNTER_N ? 1\'b0 : (r_pc[offset + 2] >= r_col + \'d1),\n                                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v:95: Operator GTE expects 32 or 7 bits on the LHS, but LHS\'s ARRAYSEL generates 6 bits.\n                                                                                                         : ... In instance oled_performance_counters\n     offset + 3 >= C_COUNTER_N ? 1\'b0 : (r_pc[offset + 3] >= r_col + \'d1),\n                                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v:96: Operator GTE expects 32 or 7 bits on the LHS, but LHS\'s ARRAYSEL generates 6 bits.\n                                                                                                         : ... In instance oled_performance_counters\n     offset + 4 >= C_COUNTER_N ? 1\'b0 : (r_pc[offset + 4] >= r_col + \'d1),\n                                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v:97: Operator GTE expects 32 or 7 bits on the LHS, but LHS\'s ARRAYSEL generates 6 bits.\n                                                                                                         : ... In instance oled_performance_counters\n     offset + 5 >= C_COUNTER_N ? 1\'b0 : (r_pc[offset + 5] >= r_col + \'d1),\n                                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v:98: Operator GTE expects 32 or 7 bits on the LHS, but LHS\'s ARRAYSEL generates 6 bits.\n                                                                                                         : ... In instance oled_performance_counters\n     offset + 6 >= C_COUNTER_N ? 1\'b0 : (r_pc[offset + 6] >= r_col + \'d1),\n                                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v:99: Operator GTE expects 32 or 7 bits on the LHS, but LHS\'s ARRAYSEL generates 6 bits.\n                                                                                                         : ... In instance oled_performance_counters\n     offset + 7 >= C_COUNTER_N ? 1\'b0 : (r_pc[offset + 7] >= r_col + \'d1)\n                                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v:119: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'r_col\' generates 7 bits.\n                                                                                                          : ... In instance oled_performance_counters\n        r_col <= r_col == C_COLS - 1 ? \'b0 : r_col + 1;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v:121: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'r_col\' generates 7 bits.\n                                                                                                          : ... In instance oled_performance_counters\n          if (r_col == C_COLS - 1) r_page <= r_page + \'d1;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/135295301/common/ip/oled_pc/src/oled_performance_counters.v:118: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'r_row\' generates 5 bits.\n                                                                                                          : ... In instance oled_performance_counters\n      if (r_row == C_ROWS - 1) begin\n                ^~\n%Error: Exiting due to 12 warning(s)\n'
module oled_performance_counters #(
    parameter C_COUNTER_N = 64,
    parameter C_COUNTER_W = 6,
    parameter C_COLS = 128,
    parameter C_ROWS = 32
  ) (
    input wire clk,
    input wire rst_n,
    input wire [C_COUNTER_N - 1 : 0] intr,
    input wire ready,
    output reg oled_sclk,
    output wire oled_dc,
    output wire oled_sdin
  );


  function integer log2;
    input integer n;
    begin
      n = n - 1;
      for (log2 = 0; n > 0; log2 = log2 + 1)
        n = n >> 1;
    end
  endfunction

  function integer max;
    input integer n1, n2;
    begin
      max = n2 > n1 ? n2 : n1;
    end
  endfunction

  reg [log2(C_COLS) - 1 : 0] r_col;
  reg [log2(C_ROWS) - 1 : 0] r_row;
  reg [max(log2(C_COUNTER_N / C_ROWS), 1) - 1 : 0] r_page;

  reg [C_COUNTER_W - 1 : 0] r_pc [C_COUNTER_N - 1 : 0];
  reg [C_COUNTER_N - 1 : 0] r_intr;


  assign oled_dc = 1'b1;


  always @(posedge clk) begin
    if (rst_n == 1'b1 && ready) oled_sclk <= ~oled_sclk;
    else                        oled_sclk <= 1'b1;
  end

  reg [7:0] r_word;
  reg [2:0] r_cnt;
  wire [31:0] offset;
  assign offset = r_page * C_ROWS + r_row;
  assign oled_sdin = r_word[0];


  always @(negedge oled_sclk, negedge rst_n) begin
    if (rst_n == 1'b0) begin
      r_word    <= 'd0;
      r_cnt     <= 'd7;
    end else begin
      if (r_cnt == 'd7) begin
        if ((r_col >= (1 << C_COUNTER_W)) || (offset >= C_COUNTER_N)) begin
	  r_word <= 8'd0;
	end else begin
	  r_word <= {
	    offset + 0 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 0] >= r_col + 'd1),
	    offset + 1 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 1] >= r_col + 'd1),
	    offset + 2 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 2] >= r_col + 'd1),
	    offset + 3 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 3] >= r_col + 'd1),
	    offset + 4 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 4] >= r_col + 'd1),
	    offset + 5 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 5] >= r_col + 'd1),
	    offset + 6 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 6] >= r_col + 'd1),
	    offset + 7 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 7] >= r_col + 'd1)
	  };
	end
      end else begin
	r_word <= r_word >> 1;
      end
      r_cnt <= r_cnt - 'd1;
    end
  end



  always @(negedge oled_sclk, negedge rst_n) begin
    if (rst_n == 1'b0 || ready == 1'b0) begin
      r_col  <= 'd0;
      r_row  <= 'd0;
      r_page <= 'd0;
    end else begin
      r_row <= r_row + 1;
      if (r_row == C_ROWS - 1) begin
        r_col <= r_col == C_COLS - 1 ? 'b0 : r_col + 1;
	if (C_COUNTER_N > C_ROWS) begin
          if (r_col == C_COLS - 1) r_page <= r_page + 'd1;
	end
      end
    end
  end


  genvar i;
  generate
  for (i = 0; i < C_COUNTER_N; i = i + 1) begin
    always @(posedge clk) begin
      if (rst_n == 1'b0) begin
        r_intr[i] <= 1'b0;
        r_pc[i] <= 'd0;
      end else begin
        r_intr[i] <= intr[i];
        if (intr[i] == 1'b1 && r_intr[i] == 1'b0)
          r_pc[i] <= r_pc[i] + 1;
      end
    end
  end
  endgenerate

endmodule
module oled_performance_counters #(
    parameter C_COUNTER_N = 64,
    parameter C_COUNTER_W = 6,
    parameter C_COLS = 128,
    parameter C_ROWS = 32
  ) (
    input wire clk,
    input wire rst_n,
    input wire [C_COUNTER_N - 1 : 0] intr,
    input wire ready,
    output reg oled_sclk,
    output wire oled_dc,
    output wire oled_sdin
  );



  function integer log2;
    input integer n;
    begin
      n = n - 1;
      for (log2 = 0; n > 0; log2 = log2 + 1)
        n = n >> 1;
    end
  endfunction

  function integer max;
    input integer n1, n2;
    begin
      max = n2 > n1 ? n2 : n1;
    end
  endfunction

  reg [log2(C_COLS) - 1 : 0] r_col;
  reg [log2(C_ROWS) - 1 : 0] r_row;
  reg [max(log2(C_COUNTER_N / C_ROWS), 1) - 1 : 0] r_page;

  reg [C_COUNTER_W - 1 : 0] r_pc [C_COUNTER_N - 1 : 0];
  reg [C_COUNTER_N - 1 : 0] r_intr;


  assign oled_dc = 1'b1;


  always @(posedge clk) begin
    if (rst_n == 1'b1 && ready) oled_sclk <= ~oled_sclk;
    else                        oled_sclk <= 1'b1;
  end

  reg [7:0] r_word;
  reg [2:0] r_cnt;
  wire [31:0] offset;
  assign offset = r_page * C_ROWS + r_row;
  assign oled_sdin = r_word[0];


  always @(negedge oled_sclk, negedge rst_n) begin
    if (rst_n == 1'b0) begin
      r_word    <= 'd0;
      r_cnt     <= 'd7;
    end else begin
      if (r_cnt == 'd7) begin
        if ((r_col >= (1 << C_COUNTER_W)) || (offset >= C_COUNTER_N)) begin
	  r_word <= 8'd0;
	end else begin
	  r_word <= {
	    offset + 0 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 0] >= r_col + 'd1),
	    offset + 1 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 1] >= r_col + 'd1),
	    offset + 2 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 2] >= r_col + 'd1),
	    offset + 3 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 3] >= r_col + 'd1),
	    offset + 4 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 4] >= r_col + 'd1),
	    offset + 5 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 5] >= r_col + 'd1),
	    offset + 6 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 6] >= r_col + 'd1),
	    offset + 7 >= C_COUNTER_N ? 1'b0 : (r_pc[offset + 7] >= r_col + 'd1)
	  };
	end
      end else begin
	r_word <= r_word >> 1;
      end
      r_cnt <= r_cnt - 'd1;
    end
  end



  always @(negedge oled_sclk, negedge rst_n) begin
    if (rst_n == 1'b0 || ready == 1'b0) begin
      r_col  <= 'd0;
      r_row  <= 'd0;
      r_page <= 'd0;
    end else begin
      r_row <= r_row + 1;
      if (r_row == C_ROWS - 1) begin
        r_col <= r_col == C_COLS - 1 ? 'b0 : r_col + 1;
	if (C_COUNTER_N > C_ROWS) begin
          if (r_col == C_COLS - 1) r_page <= r_page + 'd1;
	end
      end
    end
  end


  genvar i;
  generate
  for (i = 0; i < C_COUNTER_N; i = i + 1) begin
    always @(posedge clk) begin
      if (rst_n == 1'b0) begin
        r_intr[i] <= 1'b0;
        r_pc[i] <= 'd0;
      end else begin
        r_intr[i] <= intr[i];
        if (intr[i] == 1'b1 && r_intr[i] == 1'b0)
          r_pc[i] <= r_pc[i] + 1;
      end
    end
  end
  endgenerate

endmodule