data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v
1: b'%Error: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:1: Cannot find include file: ../cpu/MBScore_const.v\n`include "../cpu/MBScore_const.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v\n             data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.v\n             data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.sv\n             ../cpu/MBScore_const.v\n             ../cpu/MBScore_const.v.v\n             ../cpu/MBScore_const.v.sv\n             obj_dir/../cpu/MBScore_const.v\n             obj_dir/../cpu/MBScore_const.v.v\n             obj_dir/../cpu/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:5: Define or directive not defined: \'`DATA_WIDTH\'\n    reg [`DATA_WIDTH-1:0] inst;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:6: Define or directive not defined: \'`DATA_WIDTH\'\n    wire [`DATA_WIDTH-1:0] alu_result;\n          ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:19: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:21: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:34: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clk = ~clk;  \n                ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module MBScore_cpu_top_vlg_tst();
    reg clk,rst_n;
    reg [`DATA_WIDTH-1:0] inst;
    wire [`DATA_WIDTH-1:0] alu_result;

    MBScore_cpu_top i1(
        .clk(clk),
        .rst_n(rst_n),
        .inst(inst),
        .alu_result(alu_result)
    );

    initial                                                
    begin                                                                     
        rst_n = 1'b1;
        clk = 1'b0;
        #1
        rst_n = 1'b0;
        #5
        rst_n = 1'b1;                                                                                                 
        $display("Running testbench");                       
    end

    always
    begin
        #10
        inst = 32'b00000000001000010000100000100000;
    end

    always
    begin
        forever #10 clk = ~clk;  
    end

endmodule
module MBScore_cpu_top_vlg_tst();

    reg clk,rst_n;
    reg [`DATA_WIDTH-1:0] inst;
    wire [`DATA_WIDTH-1:0] alu_result;

    MBScore_cpu_top i1(
        .clk(clk),
        .rst_n(rst_n),
        .inst(inst),
        .alu_result(alu_result)
    );

    initial                                                
    begin                                                                     
        rst_n = 1'b1;
        clk = 1'b0;
        #1
        rst_n = 1'b0;
        #5
        rst_n = 1'b1;                                                                                                 
        $display("Running testbench");                       
    end

    always
    begin
        #10
        inst = 32'b00000000001000010000100000100000;
    end

    always
    begin
        forever #10 clk = ~clk;  
    end

endmodule