data/full_repos/permissive/153960117/hdl/image_write_tb.v
 line:444: before: ";"
1: b'%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:18: Cannot find include file: image_write.v\n`include "image_write.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/153960117/hdl,data/full_repos/permissive/153960117/image_write.v\n             data/full_repos/permissive/153960117/hdl,data/full_repos/permissive/153960117/image_write.v.v\n             data/full_repos/permissive/153960117/hdl,data/full_repos/permissive/153960117/image_write.v.sv\n             image_write.v\n             image_write.v.v\n             image_write.v.sv\n             obj_dir/image_write.v\n             obj_dir/image_write.v.v\n             obj_dir/image_write.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/153960117/hdl/image_write_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:31: Unsupported: event data types\n    event end_trigger;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/153960117/hdl/image_write_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    initial #1 display_header();\n            ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:165: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:173: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:199: syntax error, unexpected \'@\'\n        repeat(6) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:201: syntax error, unexpected \'@\'\n        repeat(6) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:203: syntax error, unexpected \'@\'\n        repeat(5) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:213: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:218: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:223: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:228: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:231: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:233: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:239: syntax error, unexpected \'@\'\n        repeat(5) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:247: syntax error, unexpected \'@\'\n        repeat(350) @(negedge clk);\n                    ^\n%Error: data/full_repos/permissive/153960117/hdl/image_write_tb.v:252: syntax error, unexpected ->\n        -> end_trigger;\n        ^~\n%Error: Exiting due to 16 error(s), 2 warning(s)\n'
module image_write_tb;




    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam CFG_DWIDTH   = 32;
    localparam CFG_AWIDTH   = 5;

    localparam DEPTH_NB     = 16;
    localparam IMG_WIDTH    = 16;

    localparam MEM_AWIDTH   = 16;


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'image_write'");
    end
`endif



    reg                             rst;

    reg  [CFG_DWIDTH-1:0]           cfg_data;
    reg  [CFG_AWIDTH-1:0]           cfg_addr;
    reg                             cfg_valid;

    reg                             next;
    wire                            next_rdy;

    reg  [IMG_WIDTH*DEPTH_NB-1:0]   str_img_bus;
    reg                             str_img_val;
    wire                            str_img_rdy;

    wire                            wr_val;
    wire [MEM_AWIDTH-1:0]           wr_addr;
    wire [IMG_WIDTH*DEPTH_NB-1:0]   wr_data;




    image_write #(
        .CFG_DWIDTH (CFG_DWIDTH),
        .CFG_AWIDTH (CFG_AWIDTH),

        .DEPTH_NB   (DEPTH_NB),
        .IMG_WIDTH  (IMG_WIDTH),

        .MEM_AWIDTH (MEM_AWIDTH))
    uut (
        .clk            (clk),
        .rst            (rst),

        .cfg_data       (cfg_data),
        .cfg_addr       (cfg_addr),
        .cfg_valid      (cfg_valid),

        .next           (next),
        .next_rdy       (next_rdy),

        .str_img_bus    (str_img_bus),
        .str_img_val    (str_img_val),
        .str_img_rdy    (str_img_rdy),

        .wr_val         (wr_val),
        .wr_addr        (wr_addr),
        .wr_data        (wr_data)
    );


    always @(posedge clk)
        if (str_img_val & str_img_rdy) begin
            str_img_bus <= str_img_bus + 'd1;
        end


`ifndef TB_VERBOSE
    always @(posedge clk)
        if (wr_val) begin
            $display("   %d ", wr_addr);
        end
`endif





    task display_signals;
        $display(
            "%d %d",
            $time, rst,

            "\t<nx %b %b>",
            next,
            next_rdy,

            "\t<str>: d %d, v %b, r: %b",
            str_img_bus[0 +: IMG_WIDTH],
            str_img_val,
            str_img_rdy,

            "\t<wr>: v %b, a %d, d: %d",
            wr_val,
            wr_addr,
            wr_data[0 +: IMG_WIDTH],





        );

    endtask

    task display_header;
        $display(
            "\t\ttime rst",

        );
    endtask




    initial begin

        rst = 0;

        cfg_addr    = 'b0;
        cfg_data    = 'b0;
        cfg_valid   = 1'b0;

        next        = 1'b0;

        str_img_bus = 'd1;
        str_img_val = 1'b0;


`ifdef TB_VERBOSE
    $display("RESET");
`endif

        repeat(6) @(negedge clk);
        rst         <= 1'b1;
        repeat(6) @(negedge clk);
        rst         <= 1'b0;
        repeat(5) @(negedge clk);


`ifdef TB_VERBOSE
    $display("configure");
`endif

        cfg_addr    <= uut.CFG_IW_IMG_W;
        cfg_data    <= 32'd9;
        cfg_valid   <= 1'b1;
        @(negedge clk);

        cfg_addr    <= uut.CFG_IW_START;
        cfg_data    <= {16'd0, 16'd4};
        cfg_valid   <= 1'b1;
        @(negedge clk);

        cfg_addr    <= uut.CFG_IW_STEP;
        cfg_data    <= {16'd3, 16'd9};
        cfg_valid   <= 1'b1;
        @(negedge clk);

        cfg_addr    <= 'b0;
        cfg_data    <= 'b0;
        cfg_valid   <= 1'b0;
        @(negedge clk);

        next <= 1'b1;
        @(negedge clk);
        next <= 1'b0;
        @(negedge clk);


`ifdef TB_VERBOSE
    $display("stream in data");
`endif
        repeat(5) @(negedge clk);
        str_img_val <= 1'b1;






        repeat(350) @(negedge clk);

`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule
module image_write_tb;





    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam CFG_DWIDTH   = 32;
    localparam CFG_AWIDTH   = 5;

    localparam DEPTH_NB     = 16;
    localparam IMG_WIDTH    = 16;

    localparam MEM_AWIDTH   = 16;


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'image_write'");
    end
`endif



    reg                             rst;

    reg  [CFG_DWIDTH-1:0]           cfg_data;
    reg  [CFG_AWIDTH-1:0]           cfg_addr;
    reg                             cfg_valid;

    reg                             next;
    wire                            next_rdy;

    reg  [IMG_WIDTH*DEPTH_NB-1:0]   str_img_bus;
    reg                             str_img_val;
    wire                            str_img_rdy;

    wire                            wr_val;
    wire [MEM_AWIDTH-1:0]           wr_addr;
    wire [IMG_WIDTH*DEPTH_NB-1:0]   wr_data;




    image_write #(
        .CFG_DWIDTH (CFG_DWIDTH),
        .CFG_AWIDTH (CFG_AWIDTH),

        .DEPTH_NB   (DEPTH_NB),
        .IMG_WIDTH  (IMG_WIDTH),

        .MEM_AWIDTH (MEM_AWIDTH))
    uut (
        .clk            (clk),
        .rst            (rst),

        .cfg_data       (cfg_data),
        .cfg_addr       (cfg_addr),
        .cfg_valid      (cfg_valid),

        .next           (next),
        .next_rdy       (next_rdy),

        .str_img_bus    (str_img_bus),
        .str_img_val    (str_img_val),
        .str_img_rdy    (str_img_rdy),

        .wr_val         (wr_val),
        .wr_addr        (wr_addr),
        .wr_data        (wr_data)
    );


    always @(posedge clk)
        if (str_img_val & str_img_rdy) begin
            str_img_bus <= str_img_bus + 'd1;
        end


`ifndef TB_VERBOSE
    always @(posedge clk)
        if (wr_val) begin
            $display("   %d ", wr_addr);
        end
`endif





    task display_signals;
        $display(
            "%d %d",
            $time, rst,

            "\t<nx %b %b>",
            next,
            next_rdy,

            "\t<str>: d %d, v %b, r: %b",
            str_img_bus[0 +: IMG_WIDTH],
            str_img_val,
            str_img_rdy,

            "\t<wr>: v %b, a %d, d: %d",
            wr_val,
            wr_addr,
            wr_data[0 +: IMG_WIDTH],





        );

    endtask

    task display_header;
        $display(
            "\t\ttime rst",

        );
    endtask




    initial begin

        rst = 0;

        cfg_addr    = 'b0;
        cfg_data    = 'b0;
        cfg_valid   = 1'b0;

        next        = 1'b0;

        str_img_bus = 'd1;
        str_img_val = 1'b0;


`ifdef TB_VERBOSE
    $display("RESET");
`endif

        repeat(6) @(negedge clk);
        rst         <= 1'b1;
        repeat(6) @(negedge clk);
        rst         <= 1'b0;
        repeat(5) @(negedge clk);


`ifdef TB_VERBOSE
    $display("configure");
`endif

        cfg_addr    <= uut.CFG_IW_IMG_W;
        cfg_data    <= 32'd9;
        cfg_valid   <= 1'b1;
        @(negedge clk);

        cfg_addr    <= uut.CFG_IW_START;
        cfg_data    <= {16'd0, 16'd4};
        cfg_valid   <= 1'b1;
        @(negedge clk);

        cfg_addr    <= uut.CFG_IW_STEP;
        cfg_data    <= {16'd3, 16'd9};
        cfg_valid   <= 1'b1;
        @(negedge clk);

        cfg_addr    <= 'b0;
        cfg_data    <= 'b0;
        cfg_valid   <= 1'b0;
        @(negedge clk);

        next <= 1'b1;
        @(negedge clk);
        next <= 1'b0;
        @(negedge clk);


`ifdef TB_VERBOSE
    $display("stream in data");
`endif
        repeat(5) @(negedge clk);
        str_img_val <= 1'b1;






        repeat(350) @(negedge clk);

`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule