data/full_repos/permissive/14193640/fpga/usb_controller_testbench.v
 line:62: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/usb_controller_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/usb_controller_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/usb_controller_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/usb_controller_testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/usb_controller_testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #110;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/usb_controller_testbench.v:55: Unsupported: Ignoring delay on this delayed statement.\n      #70;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/usb_controller_testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n      #110;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/usb_controller_testbench.v:59: Unsupported: Ignoring delay on this delayed statement.\n      #200\n      ^\n%Error: data/full_repos/permissive/14193640/fpga/usb_controller_testbench.v:22: Cannot find file containing module: \'usb_controller\'\n   usb_controller uut\n   ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/14193640/fpga,data/full_repos/permissive/14193640/usb_controller\n             data/full_repos/permissive/14193640/fpga,data/full_repos/permissive/14193640/usb_controller.v\n             data/full_repos/permissive/14193640/fpga,data/full_repos/permissive/14193640/usb_controller.sv\n             usb_controller\n             usb_controller.v\n             usb_controller.sv\n             obj_dir/usb_controller\n             obj_dir/usb_controller.v\n             obj_dir/usb_controller.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module usb_controller_testbench;

   reg         clk;
   reg         reset_n;
   reg [15:0]  panel_switches_raw;
   reg         rxf_n_raw;
   reg         txe_n_raw;
   reg [7:0]   data_bus_in_raw;
   wire [7:0]  data_bus_out;
   wire        rd_n;
   wire        wr_n;
   wire        data_out_enable;
   wire [31:0] chunk_data;
   wire [3:0]  chunk_addr;
   wire        chunk_write_enable;
   wire [3:0]  row_addr;
   wire [1:0]  panel_addr;
   wire [4:0]  state_out;

   usb_controller uut
     (.clk(clk), .reset_n(reset_n), .panel_switches_raw(panel_switches_raw),
      .rxf_n_raw(rxf_n_raw), .txe_n_raw(txe_n_raw), 
      .data_bus_in_raw(data_bus_in_raw), .data_bus_out(data_bus_out), 
      .rd_n(rd_n), .wr_n(wr_n), .data_out_enable(data_out_enable),
      .chunk_data(chunk_data), .chunk_addr(chunk_addr), 
      .chunk_write_enable(chunk_write_enable), .row_addr(row_addr),
      .panel_addr(panel_addr), .state_out(state_out));

   always begin
      clk = 1'b1;
      #10;
      clk = 1'b0;
      #10;
   end

   initial begin

      reset_n = 0;
      panel_switches_raw = 16'hfdec;
      rxf_n_raw = 1;
      txe_n_raw = 0;
      data_bus_in_raw = 8'h00;
      #100;

      reset_n = 1;
      data_bus_in_raw = 8'h23;
      #100;

      rxf_n_raw = 0;
      #110;
      rxf_n_raw = 1;
      data_bus_in_raw = 8'h40;
      #70;
      rxf_n_raw = 0;
      #110;
      rxf_n_raw = 1;
      #200
      
      
      $stop;
   end


endmodule
module usb_controller_testbench;


   reg         clk;
   reg         reset_n;
   reg [15:0]  panel_switches_raw;
   reg         rxf_n_raw;
   reg         txe_n_raw;
   reg [7:0]   data_bus_in_raw;
   wire [7:0]  data_bus_out;
   wire        rd_n;
   wire        wr_n;
   wire        data_out_enable;
   wire [31:0] chunk_data;
   wire [3:0]  chunk_addr;
   wire        chunk_write_enable;
   wire [3:0]  row_addr;
   wire [1:0]  panel_addr;
   wire [4:0]  state_out;

   usb_controller uut
     (.clk(clk), .reset_n(reset_n), .panel_switches_raw(panel_switches_raw),
      .rxf_n_raw(rxf_n_raw), .txe_n_raw(txe_n_raw), 
      .data_bus_in_raw(data_bus_in_raw), .data_bus_out(data_bus_out), 
      .rd_n(rd_n), .wr_n(wr_n), .data_out_enable(data_out_enable),
      .chunk_data(chunk_data), .chunk_addr(chunk_addr), 
      .chunk_write_enable(chunk_write_enable), .row_addr(row_addr),
      .panel_addr(panel_addr), .state_out(state_out));

   always begin
      clk = 1'b1;
      #10;
      clk = 1'b0;
      #10;
   end

   initial begin

      reset_n = 0;
      panel_switches_raw = 16'hfdec;
      rxf_n_raw = 1;
      txe_n_raw = 0;
      data_bus_in_raw = 8'h00;
      #100;

      reset_n = 1;
      data_bus_in_raw = 8'h23;
      #100;

      rxf_n_raw = 0;
      #110;
      rxf_n_raw = 1;
      data_bus_in_raw = 8'h40;
      #70;
      rxf_n_raw = 0;
      #110;
      rxf_n_raw = 1;
      #200
      
      
      $stop;
   end


endmodule