data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi/axis_packet_flush.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi/axis_packet_flush.v:66: Operator EQ expects 40 bits on the LHS, but LHS\'s VARREF \'PIPELINE\' generates 32 bits.\n                                                                                                                                  : ... In instance axis_packet_flush\n    if (PIPELINE == "IN" || PIPELINE == "INOUT") begin\n                                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi/axis_packet_flush.v:78: Operator EQ expects 40 bits on the LHS, but LHS\'s VARREF \'PIPELINE\' generates 32 bits.\n                                                                                                                                  : ... In instance axis_packet_flush\n    if (PIPELINE == "OUT" || PIPELINE == "INOUT") begin\n                                      ^~\n%Error: Exiting due to 2 warning(s)\n'
module axis_packet_flush #(
  parameter WIDTH               = 64,
  parameter TIMEOUT_W           = 32,
  parameter FLUSH_PARTIAL_PKTS  = 0,
  parameter PIPELINE            = "NONE"
)(

  input  wire                 clk,
  input  wire                 reset,

  input  wire                 enable,
  input  wire [TIMEOUT_W-1:0] timeout,
  output wire                 flushing,
  output reg                  done = 1'b0,

  input  wire [WIDTH-1:0]     s_axis_tdata,
  input  wire                 s_axis_tlast,
  input  wire                 s_axis_tvalid,
  output wire                 s_axis_tready,

  output wire [WIDTH-1:0]     m_axis_tdata,
  output wire                 m_axis_tlast,
  output wire                 m_axis_tvalid,
  input  wire                 m_axis_tready
);





  wire [WIDTH-1:0] i_pipe_tdata,  o_pipe_tdata;
  wire             i_pipe_tlast,  o_pipe_tlast;
  wire             i_pipe_tvalid, o_pipe_tvalid;
  wire             i_pipe_tready, o_pipe_tready;

  generate
    if (PIPELINE == "IN" || PIPELINE == "INOUT") begin
      axi_fifo_flop2 #(.WIDTH(WIDTH+1)) in_pipe_i (
        .clk(clk), .reset(reset), .clear(1'b0),
        .i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready),
        .o_tdata({i_pipe_tlast, i_pipe_tdata}), .o_tvalid(i_pipe_tvalid), .o_tready(i_pipe_tready),
        .space(), .occupied()
      );
    end else begin
      assign {i_pipe_tlast, i_pipe_tdata, i_pipe_tvalid} = {s_axis_tlast, s_axis_tdata, s_axis_tvalid}; 
      assign s_axis_tready = i_pipe_tready;
    end

    if (PIPELINE == "OUT" || PIPELINE == "INOUT") begin
      axi_fifo_flop2 #(.WIDTH(WIDTH+1)) out_pipe_i (
        .clk(clk), .reset(reset), .clear(1'b0),
        .i_tdata({o_pipe_tlast, o_pipe_tdata}), .i_tvalid(o_pipe_tvalid), .i_tready(o_pipe_tready),
        .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready),
        .space(), .occupied()
      );
    end else begin
      assign {m_axis_tlast, m_axis_tdata, m_axis_tvalid} = {o_pipe_tlast, o_pipe_tdata, o_pipe_tvalid};
      assign o_pipe_tready = m_axis_tready;
    end
  endgenerate






  wire xfer_stb = i_pipe_tvalid & i_pipe_tready;
  wire pkt_stb  = xfer_stb & i_pipe_tlast;


  reg mid_pkt = 1'b0;
  always @(posedge clk) begin
    if (reset) begin
      mid_pkt <= 1'b0;
    end else if (xfer_stb) begin
      mid_pkt <= ~pkt_stb;
    end
  end


  reg active  = 1'b0;
  always @(posedge clk) begin
    if (reset) begin
      active <= 1'b0;
    end else begin
      if (enable & (pkt_stb | (~mid_pkt & ~xfer_stb))) begin
        active <= 1'b1;
      end else if (~enable) begin
        active <= 1'b0;
      end
    end
  end
  assign flushing = (FLUSH_PARTIAL_PKTS == 0) ? active : enable;


  reg [TIMEOUT_W-1:0] cyc_to_go = {TIMEOUT_W{1'b1}};
  wire done_tmp = (cyc_to_go == {TIMEOUT_W{1'b0}});
  always @(posedge clk) begin
    if (reset | ~enable) begin
      cyc_to_go <= {TIMEOUT_W{1'b1}};
      done <= 1'b0;
    end else if (enable & ~active) begin
      cyc_to_go <= timeout;
    end else begin
      if (~done_tmp) begin
        cyc_to_go <= xfer_stb ? timeout : (cyc_to_go - 1'b1);
      end
      done <= done_tmp;
    end
  end



  assign o_pipe_tdata  = i_pipe_tdata;
  assign o_pipe_tlast  = i_pipe_tlast;
  assign o_pipe_tvalid = flushing ? 1'b0 : i_pipe_tvalid;
  assign i_pipe_tready = flushing ? 1'b1 : o_pipe_tready;

endmodule
module axis_packet_flush #(
  parameter WIDTH               = 64,
  parameter TIMEOUT_W           = 32,
  parameter FLUSH_PARTIAL_PKTS  = 0,
  parameter PIPELINE            = "NONE"
)(

  input  wire                 clk,
  input  wire                 reset,

  input  wire                 enable,
  input  wire [TIMEOUT_W-1:0] timeout,
  output wire                 flushing,
  output reg                  done = 1'b0,

  input  wire [WIDTH-1:0]     s_axis_tdata,
  input  wire                 s_axis_tlast,
  input  wire                 s_axis_tvalid,
  output wire                 s_axis_tready,

  output wire [WIDTH-1:0]     m_axis_tdata,
  output wire                 m_axis_tlast,
  output wire                 m_axis_tvalid,
  input  wire                 m_axis_tready
);






  wire [WIDTH-1:0] i_pipe_tdata,  o_pipe_tdata;
  wire             i_pipe_tlast,  o_pipe_tlast;
  wire             i_pipe_tvalid, o_pipe_tvalid;
  wire             i_pipe_tready, o_pipe_tready;

  generate
    if (PIPELINE == "IN" || PIPELINE == "INOUT") begin
      axi_fifo_flop2 #(.WIDTH(WIDTH+1)) in_pipe_i (
        .clk(clk), .reset(reset), .clear(1'b0),
        .i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready),
        .o_tdata({i_pipe_tlast, i_pipe_tdata}), .o_tvalid(i_pipe_tvalid), .o_tready(i_pipe_tready),
        .space(), .occupied()
      );
    end else begin
      assign {i_pipe_tlast, i_pipe_tdata, i_pipe_tvalid} = {s_axis_tlast, s_axis_tdata, s_axis_tvalid}; 
      assign s_axis_tready = i_pipe_tready;
    end

    if (PIPELINE == "OUT" || PIPELINE == "INOUT") begin
      axi_fifo_flop2 #(.WIDTH(WIDTH+1)) out_pipe_i (
        .clk(clk), .reset(reset), .clear(1'b0),
        .i_tdata({o_pipe_tlast, o_pipe_tdata}), .i_tvalid(o_pipe_tvalid), .i_tready(o_pipe_tready),
        .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready),
        .space(), .occupied()
      );
    end else begin
      assign {m_axis_tlast, m_axis_tdata, m_axis_tvalid} = {o_pipe_tlast, o_pipe_tdata, o_pipe_tvalid};
      assign o_pipe_tready = m_axis_tready;
    end
  endgenerate






  wire xfer_stb = i_pipe_tvalid & i_pipe_tready;
  wire pkt_stb  = xfer_stb & i_pipe_tlast;


  reg mid_pkt = 1'b0;
  always @(posedge clk) begin
    if (reset) begin
      mid_pkt <= 1'b0;
    end else if (xfer_stb) begin
      mid_pkt <= ~pkt_stb;
    end
  end


  reg active  = 1'b0;
  always @(posedge clk) begin
    if (reset) begin
      active <= 1'b0;
    end else begin
      if (enable & (pkt_stb | (~mid_pkt & ~xfer_stb))) begin
        active <= 1'b1;
      end else if (~enable) begin
        active <= 1'b0;
      end
    end
  end
  assign flushing = (FLUSH_PARTIAL_PKTS == 0) ? active : enable;


  reg [TIMEOUT_W-1:0] cyc_to_go = {TIMEOUT_W{1'b1}};
  wire done_tmp = (cyc_to_go == {TIMEOUT_W{1'b0}});
  always @(posedge clk) begin
    if (reset | ~enable) begin
      cyc_to_go <= {TIMEOUT_W{1'b1}};
      done <= 1'b0;
    end else if (enable & ~active) begin
      cyc_to_go <= timeout;
    end else begin
      if (~done_tmp) begin
        cyc_to_go <= xfer_stb ? timeout : (cyc_to_go - 1'b1);
      end
      done <= done_tmp;
    end
  end



  assign o_pipe_tdata  = i_pipe_tdata;
  assign o_pipe_tlast  = i_pipe_tlast;
  assign o_pipe_tvalid = flushing ? 1'b0 : i_pipe_tvalid;
  assign i_pipe_tready = flushing ? 1'b1 : o_pipe_tready;

endmodule