data/full_repos/permissive/162251494/GuitarHero.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/162251494/GuitarHero.v:187: Value too large for 6 bit number: 101000\n  else if(x_counter >= 6\'d101000 & y_counter < 7\'b1111000) begin\n                       ^~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/162251494/GuitarHero.v:453: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'state\' generates 4 bits.\n                                                                     : ... In instance GuitarHero.pFSM0\n  else if(state == 16) begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/162251494/GuitarHero.v:278: Operator LTE expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'counter\' generates 1 bits.\n                                                                     : ... In instance GuitarHero.gsm0\n  else if (counter <= 9 & ~loss) begin\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/162251494/GuitarHero.v:317: Bit extraction of var[9:0] requires 4 bit index, not 1 bits.\n                                                                     : ... In instance GuitarHero.gsm0\n   c1Draw <= {c1Curr[28:0], c1Pattern[counter]};\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/162251494/GuitarHero.v:318: Bit extraction of var[9:0] requires 4 bit index, not 1 bits.\n                                                                     : ... In instance GuitarHero.gsm0\n   c2Draw <= {c2Curr[28:0], c2Pattern[counter]};\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/162251494/GuitarHero.v:319: Bit extraction of var[9:0] requires 4 bit index, not 1 bits.\n                                                                     : ... In instance GuitarHero.gsm0\n   c3Draw <= {c3Curr[28:0], c3Pattern[counter]};\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/162251494/GuitarHero.v:320: Bit extraction of var[9:0] requires 4 bit index, not 1 bits.\n                                                                     : ... In instance GuitarHero.gsm0\n   c4Draw <= {c4Curr[28:0], c4Pattern[counter]};\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/162251494/GuitarHero.v:315: Operator LTE expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'counter\' generates 1 bits.\n                                                                     : ... In instance GuitarHero.gsm0\n  else if (counter <= 9 & ~loss) begin\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/162251494/GuitarHero.v:349: Operator GT expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'counter\' generates 1 bits.\n                                                                     : ... In instance GuitarHero.gsm0\n  if (counter > 9) begin\n              ^\n%Warning-WIDTH: data/full_repos/permissive/162251494/GuitarHero.v:170: Operator ADD expects 8 bits on the LHS, but LHS\'s SEL generates 6 bits.\n                                                                     : ... In instance GuitarHero.p0\n assign X_out[7:0] = x_counter[5:0] + column[1:0]*6\'b101000;\n                                    ^\n%Error: data/full_repos/permissive/162251494/GuitarHero.v:79: Cannot find file containing module: \'keyboard\'\n keyboard kb(.keyboard_clk(PS2_CLK), .keyboard_data(PS2_DAT), .clock50(CLOCK_50), .reset(0), .read(read), .scan_ready(scan_ready), .scan_code(scan_code));\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162251494,data/full_repos/permissive/162251494/keyboard\n             data/full_repos/permissive/162251494,data/full_repos/permissive/162251494/keyboard.v\n             data/full_repos/permissive/162251494,data/full_repos/permissive/162251494/keyboard.sv\n             keyboard\n             keyboard.v\n             keyboard.sv\n             obj_dir/keyboard\n             obj_dir/keyboard.v\n             obj_dir/keyboard.sv\n%Error: data/full_repos/permissive/162251494/GuitarHero.v:80: Cannot find file containing module: \'oneshot\'\n oneshot pulse(.pulse_out(read), .trigger_in(scan_ready), .clk(CLOCK_50));\n ^~~~~~~\n%Error: data/full_repos/permissive/162251494/GuitarHero.v:133: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 10 warning(s)\n'
module GameStateManager (input p1_key1, input p1_key2, input p2_key1, input p2_key2, 
							input [29:0] c1Curr, input [29:0] c2Curr, input [29:0] c3Curr, input [29:0] c4Curr,
							input [9:0] c1Pattern, input [9:0] c2Pattern, input [9:0] c3Pattern, input [9:0] c4Pattern,
							input clock, input reset,
							output reg [3:0] score_p1, output reg [3:0] score_p2, 
							output reg [29:0] c1Draw, output reg [29:0] c2Draw, output reg [29:0] c3Draw, output reg [29:0] c4Draw);
		

	reg p1k1Reg, p1k2Reg, p2k1Reg, p2k2Reg;
	reg resetKeysReg;
	reg resetKeysRegCheck;
	reg counter = 0; 
	always @ (*) begin 
		if (p1_key1)
			p1k1Reg <= 1;
		
		if (p1_key2)
			p1k2Reg <= 1;
			
		if (p2_key1)
			p2k1Reg <= 1;
		
		if (p2_key2)
			p2k2Reg <= 1;
		
		if (resetKeysReg) begin
			p1k1Reg <= 0;
			p1k2Reg <= 0;
			p2k1Reg <= 0;
			p2k2Reg <= 0;
			
		end
	end
	

	reg loss;
	always @(negedge clock) begin
		if (reset) begin
			loss <= 0;
			resetKeysReg <= 1;
		end
		else if ((p1k1Reg != c1Curr[29]) || (p1k2Reg != c2Curr[29]) || (p2k1Reg != c3Curr[29]) || (p2k2Reg != c4Curr[29])) begin
			loss <= 1;
		end
		
		if(resetKeysRegCheck & !reset) begin
			resetKeysReg <= 0;
		end
		else if (counter <= 9 & ~loss) begin
			resetKeysReg <= 1;
		end

	end
	

	wire increment_score_p1_1;
	wire increment_score_p1_2;
	wire increment_score_p2_1;
	wire increment_score_p2_2;
	
	assign increment_score_p1_1 = ~loss && (p1k1Reg == c1Curr[29] && c1Curr[29]);
	assign increment_score_p1_2 = ~loss && (p1k2Reg == c2Curr[29] && c2Curr[29]);
	assign increment_score_p2_1 = ~loss && (p2k1Reg == c3Curr[29] && c3Curr[29]); 
	assign increment_score_p2_2 = ~loss && (p2k2Reg == c4Curr[29] && c4Curr[29]);


	always @(posedge clock) begin
		if (resetKeysReg) begin
			resetKeysRegCheck <= 1;
		end
		else if(resetKeysRegCheck & !resetKeysReg) begin
			resetKeysRegCheck <= 0;
		end
		
		if (reset) begin
			c1Draw <= 30'b111111111111111111111111111111;
			c2Draw <= 30'b111111111111111111111111111111;
			c3Draw <= 30'b111111111111111111111111111111;
			c4Draw <= 30'b111111111111111111111111111111;
			
			counter <= 0;
			score_p1 <= 0;
			score_p2 <= 0;
			
		end
		else if (counter <= 9 & ~loss) begin
			
			c1Draw <= {c1Curr[28:0], c1Pattern[counter]};
			c2Draw <= {c2Curr[28:0], c2Pattern[counter]};
			c3Draw <= {c3Curr[28:0], c3Pattern[counter]};
			c4Draw <= {c4Curr[28:0], c4Pattern[counter]};
			
		end
		else if (loss) begin
			c1Draw <= 0;
			c2Draw <= 0;
			c3Draw <= 0;
			c4Draw <= 0;
			
		end
		
		counter <= counter + 1;
		
		if (increment_score_p1_1& ~reset) begin
			score_p1 <= score_p1 + 1;
		end
		
		if (increment_score_p2_1& ~reset) begin
			score_p2 <= score_p2 + 1;
		end
		
		if (increment_score_p1_2& ~reset) begin
			score_p2 <= score_p2 + 1;
		end
		
		if (increment_score_p2_2& ~reset) begin
			score_p2 <= score_p2 + 1;
		end
		
		if (counter > 9) begin
			counter <= 0;
		end
	end
	
endmodule
module GameStateManager (input p1_key1, input p1_key2, input p2_key1, input p2_key2, 
							input [29:0] c1Curr, input [29:0] c2Curr, input [29:0] c3Curr, input [29:0] c4Curr,
							input [9:0] c1Pattern, input [9:0] c2Pattern, input [9:0] c3Pattern, input [9:0] c4Pattern,
							input clock, input reset,
							output reg [3:0] score_p1, output reg [3:0] score_p2, 
							output reg [29:0] c1Draw, output reg [29:0] c2Draw, output reg [29:0] c3Draw, output reg [29:0] c4Draw);

		

	reg p1k1Reg, p1k2Reg, p2k1Reg, p2k2Reg;
	reg resetKeysReg;
	reg resetKeysRegCheck;
	reg counter = 0; 
	always @ (*) begin 
		if (p1_key1)
			p1k1Reg <= 1;
		
		if (p1_key2)
			p1k2Reg <= 1;
			
		if (p2_key1)
			p2k1Reg <= 1;
		
		if (p2_key2)
			p2k2Reg <= 1;
		
		if (resetKeysReg) begin
			p1k1Reg <= 0;
			p1k2Reg <= 0;
			p2k1Reg <= 0;
			p2k2Reg <= 0;
			
		end
	end
	

	reg loss;
	always @(negedge clock) begin
		if (reset) begin
			loss <= 0;
			resetKeysReg <= 1;
		end
		else if ((p1k1Reg != c1Curr[29]) || (p1k2Reg != c2Curr[29]) || (p2k1Reg != c3Curr[29]) || (p2k2Reg != c4Curr[29])) begin
			loss <= 1;
		end
		
		if(resetKeysRegCheck & !reset) begin
			resetKeysReg <= 0;
		end
		else if (counter <= 9 & ~loss) begin
			resetKeysReg <= 1;
		end

	end
	

	wire increment_score_p1_1;
	wire increment_score_p1_2;
	wire increment_score_p2_1;
	wire increment_score_p2_2;
	
	assign increment_score_p1_1 = ~loss && (p1k1Reg == c1Curr[29] && c1Curr[29]);
	assign increment_score_p1_2 = ~loss && (p1k2Reg == c2Curr[29] && c2Curr[29]);
	assign increment_score_p2_1 = ~loss && (p2k1Reg == c3Curr[29] && c3Curr[29]); 
	assign increment_score_p2_2 = ~loss && (p2k2Reg == c4Curr[29] && c4Curr[29]);


	always @(posedge clock) begin
		if (resetKeysReg) begin
			resetKeysRegCheck <= 1;
		end
		else if(resetKeysRegCheck & !resetKeysReg) begin
			resetKeysRegCheck <= 0;
		end
		
		if (reset) begin
			c1Draw <= 30'b111111111111111111111111111111;
			c2Draw <= 30'b111111111111111111111111111111;
			c3Draw <= 30'b111111111111111111111111111111;
			c4Draw <= 30'b111111111111111111111111111111;
			
			counter <= 0;
			score_p1 <= 0;
			score_p2 <= 0;
			
		end
		else if (counter <= 9 & ~loss) begin
			
			c1Draw <= {c1Curr[28:0], c1Pattern[counter]};
			c2Draw <= {c2Curr[28:0], c2Pattern[counter]};
			c3Draw <= {c3Curr[28:0], c3Pattern[counter]};
			c4Draw <= {c4Curr[28:0], c4Pattern[counter]};
			
		end
		else if (loss) begin
			c1Draw <= 0;
			c2Draw <= 0;
			c3Draw <= 0;
			c4Draw <= 0;
			
		end
		
		counter <= counter + 1;
		
		if (increment_score_p1_1& ~reset) begin
			score_p1 <= score_p1 + 1;
		end
		
		if (increment_score_p2_1& ~reset) begin
			score_p2 <= score_p2 + 1;
		end
		
		if (increment_score_p1_2& ~reset) begin
			score_p2 <= score_p2 + 1;
		end
		
		if (increment_score_p2_2& ~reset) begin
			score_p2 <= score_p2 + 1;
		end
		
		if (counter > 9) begin
			counter <= 0;
		end
	end
	
endmodule