data/full_repos/permissive/179884651/examples/WF_joystick_board_demo.v
 line:72: before: "."
1: b'%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_joystick_board_demo.v:76: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_joystick_board_demo.v:78: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_joystick_board_demo.v:84: Signal definition not found, creating implicitly: \'two_ms\'\n           .timer_pulse(two_ms));\n                        ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_joystick_board_demo.v:314: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h1f\' generates 5 bits.\n                                                                                          : ... In instance fpga_top.joystick_inst\n         if (dataout_index == 5\'d31)  \n                           ^~\n%Error: data/full_repos/permissive/179884651/examples/WF_joystick_board_demo.v:66: Cannot find file containing module: \'SB_HFOSC\'\n  SB_HFOSC OSC_i (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.v\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.sv\n             SB_HFOSC\n             SB_HFOSC.v\n             SB_HFOSC.sv\n             obj_dir/SB_HFOSC\n             obj_dir/SB_HFOSC.v\n             obj_dir/SB_HFOSC.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module WF_timer (
       input  wire clk,
       input  wire enable,
       output reg  timer_pulse
   );

   parameter [9:0] COUNT = 499;
   parameter       EVERY_CLK = 1'b0;

    reg [9:0] counter;

    always @ (posedge clk)
        if (enable)
          begin
            if (counter == COUNT)
              begin
                timer_pulse <= 1'b1;
                counter     <= 'b0;
              end
           else
             begin
              counter     <= counter + 'b1;
              if (EVERY_CLK)
               timer_pulse <= 1'b0;
             end

          end
        else
            timer_pulse <= 1'b0;

   endmodule
module WF_timer (
       input  wire clk,
       input  wire enable,
       output reg  timer_pulse
   );


   parameter [9:0] COUNT = 499;
   parameter       EVERY_CLK = 1'b0;

    reg [9:0] counter;

    always @ (posedge clk)
        if (enable)
          begin
            if (counter == COUNT)
              begin
                timer_pulse <= 1'b1;
                counter     <= 'b0;
              end
           else
             begin
              counter     <= counter + 'b1;
              if (EVERY_CLK)
               timer_pulse <= 1'b0;
             end

          end
        else
            timer_pulse <= 1'b0;

   endmodule