data/full_repos/permissive/203526788/IceStick/UART_String/test.v
 line:74: before: "="
1: b'%Error: data/full_repos/permissive/203526788/IceStick/UART_String/test.v:3: Cannot find include file: top.v\n`include "top.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203526788/IceStick/UART_String,data/full_repos/permissive/203526788/top.v\n             data/full_repos/permissive/203526788/IceStick/UART_String,data/full_repos/permissive/203526788/top.v.v\n             data/full_repos/permissive/203526788/IceStick/UART_String,data/full_repos/permissive/203526788/top.v.sv\n             top.v\n             top.v.v\n             top.v.sv\n             obj_dir/top.v\n             obj_dir/top.v.v\n             obj_dir/top.v.sv\n%Error: data/full_repos/permissive/203526788/IceStick/UART_String/test.v:16: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/203526788/IceStick/UART_String/test.v:17: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/203526788/IceStick/UART_String/test.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10_000_000 $finish;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/203526788/IceStick/UART_String/test.v:23: Unsupported: Ignoring delay on this delayed statement.\nalways #(1000000000/ClkFrequency/2-1) \n       ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module test;

parameter ClkFrequency = 12000000;

reg clk;


initial 
begin
	$dumpfile("test.vcd");
	$dumpvars(0, test);
	
	clk = 0;
	#10_000_000 $finish;
end

always #(1000000000/ClkFrequency/2-1) 
begin
	clk = ~clk;
end

top main (clk);

endmodule
module test;


parameter ClkFrequency = 12000000;

reg clk;


initial 
begin
	$dumpfile("test.vcd");
	$dumpvars(0, test);
	
	clk = 0;
	#10_000_000 $finish;
end

always #(1000000000/ClkFrequency/2-1) 
begin
	clk = ~clk;
end

top main (clk);

endmodule