data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv
 line:19: before: "*"
1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:26: Unsupported: Ignoring delay on this delayed statement.\n            # (clock_period / 2) clock = ~ clock;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:48: syntax error, unexpected \'@\'\n        repeat (5) @ (posedge clock);\n                   ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:52: syntax error, unexpected \'@\'\n        repeat (5) @ (posedge clock);\n                   ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:58: syntax error, unexpected \'@\'\n        repeat (5) @ (posedge clock);\n                   ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:62: Unsupported: for loop initialization after the first comma\n        for (i = 0, n = 0; i < 10; i ++)\n                  ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:69: syntax error, unexpected \'@\'\n            @ (posedge clock);\n            ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:79: syntax error, unexpected \'@\'\n        repeat (5) @ (posedge clock);\n                   ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:83: Unsupported: for loop initialization after the first comma\n        for (i = 0, n = 0; i < 10; i ++)\n                  ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:90: syntax error, unexpected \'@\'\n            @ (posedge clock);\n            ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:100: syntax error, unexpected \'@\'\n        repeat (5) @ (posedge clock);\n                   ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:104: Unsupported: for loop initialization after the first comma\n        for (i = 0, n = 0; i < 10; i ++)\n                  ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:111: syntax error, unexpected \'@\'\n            @ (posedge clock);\n            ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:121: syntax error, unexpected \'@\'\n        repeat (5) @ (posedge clock);\n                   ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:125: Unsupported: for loop initialization after the first comma\n        for (i = 0, n = 0; i < 10; i ++)\n                  ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:132: syntax error, unexpected \'@\'\n            @ (posedge clock);\n            ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:142: syntax error, unexpected \'@\'\n        repeat (5) @ (posedge clock);\n                   ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:146: Unsupported: for loop initialization after the first comma\n        for (i = 0, n = 0; i < 10; i ++)\n                  ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:153: syntax error, unexpected \'@\'\n            @ (posedge clock);\n            ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:163: syntax error, unexpected \'@\'\n        repeat (5) @ (posedge clock);\n                   ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:167: Unsupported: for loop initialization after the first comma\n        for (i = 0, n = 0; i < 10; i ++)\n                  ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:169: Unsupported or unknown PLI call: $urandom_range\n            up_valid   <= $urandom_range (1);\n                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:170: Unsupported or unknown PLI call: $urandom_range\n            down_ready <= $urandom_range (1);\n                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:174: syntax error, unexpected \'@\'\n            @ (posedge clock);\n            ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_3_pipeline_stomach/old_yuri_panchul_example/tb.sv:184: syntax error, unexpected \'@\'\n        repeat (5) @ (posedge clock);\n                   ^\n%Error: Exiting due to 23 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;

    localparam width        = 8,
               clock_period = 100;

    reg                clock;
    reg                reset_n;

    reg  [width - 1:0] up_data;
    reg                up_valid;
    wire               up_ready;

    wire [width - 1:0] down_data;
    wire               down_valid;
    reg                down_ready;

    top
    #(.width (width))
    top_inst (.*);

    initial
    begin
        clock = 1'b1;

        forever
            # (clock_period / 2) clock = ~ clock;
    end

    wire [width - 1:0] up_data_x
        = up_valid & up_ready ? up_data : 8'hx;

    wire [width - 1:0] down_data_x
        = down_valid & down_ready ? down_data : 8'hx;

    int i, n;

    initial
    begin


        up_valid   <= 1'b0;
        down_ready <= 1'b0;



        reset_n <= 1'b0;

        repeat (5) @ (posedge clock);

        reset_n <= 1'b1;

        repeat (5) @ (posedge clock);

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);



        for (i = 0, n = 0; i < 10; i ++)
        begin
            up_valid   <= 1'b1;
            down_ready <= 1'b1;

            up_data    <= n;

            @ (posedge clock);

            if (up_valid & up_ready)
                n ++;
        end

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);



        for (i = 0, n = 0; i < 10; i ++)
        begin
            up_valid   <= 1'b1;
            down_ready <= i & 1;

            up_data    <= n;

            @ (posedge clock);

            if (up_valid & up_ready)
                n ++;
        end

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);



        for (i = 0, n = 0; i < 10; i ++)
        begin
            up_valid   <= i & 1;
            down_ready <= 1'b1;

            up_data    <= n;

            @ (posedge clock);

            if (up_valid & up_ready)
                n ++;
        end

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);



        for (i = 0, n = 0; i < 10; i ++)
        begin
            up_valid   <= i & 1;
            down_ready <= i & 1;

            up_data    <= n;

            @ (posedge clock);

            if (up_valid & up_ready)
                n ++;
        end

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);



        for (i = 0, n = 0; i < 10; i ++)
        begin
            up_valid   <=    i & 1;
            down_ready <= ! (i & 1);

            up_data    <= n;

            @ (posedge clock);

            if (up_valid & up_ready)
                n ++;
        end

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);



        for (i = 0, n = 0; i < 10; i ++)
        begin
            up_valid   <= $urandom_range (1);
            down_ready <= $urandom_range (1);

            up_data    <= n;

            @ (posedge clock);

            if (up_valid & up_ready)
                n ++;
        end

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);

        $finish;
    end

endmodule
module tb;


    localparam width        = 8,
               clock_period = 100;

    reg                clock;
    reg                reset_n;

    reg  [width - 1:0] up_data;
    reg                up_valid;
    wire               up_ready;

    wire [width - 1:0] down_data;
    wire               down_valid;
    reg                down_ready;

    top
    #(.width (width))
    top_inst (.*);

    initial
    begin
        clock = 1'b1;

        forever
            # (clock_period / 2) clock = ~ clock;
    end

    wire [width - 1:0] up_data_x
        = up_valid & up_ready ? up_data : 8'hx;

    wire [width - 1:0] down_data_x
        = down_valid & down_ready ? down_data : 8'hx;

    int i, n;

    initial
    begin


        up_valid   <= 1'b0;
        down_ready <= 1'b0;



        reset_n <= 1'b0;

        repeat (5) @ (posedge clock);

        reset_n <= 1'b1;

        repeat (5) @ (posedge clock);

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);



        for (i = 0, n = 0; i < 10; i ++)
        begin
            up_valid   <= 1'b1;
            down_ready <= 1'b1;

            up_data    <= n;

            @ (posedge clock);

            if (up_valid & up_ready)
                n ++;
        end

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);



        for (i = 0, n = 0; i < 10; i ++)
        begin
            up_valid   <= 1'b1;
            down_ready <= i & 1;

            up_data    <= n;

            @ (posedge clock);

            if (up_valid & up_ready)
                n ++;
        end

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);



        for (i = 0, n = 0; i < 10; i ++)
        begin
            up_valid   <= i & 1;
            down_ready <= 1'b1;

            up_data    <= n;

            @ (posedge clock);

            if (up_valid & up_ready)
                n ++;
        end

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);



        for (i = 0, n = 0; i < 10; i ++)
        begin
            up_valid   <= i & 1;
            down_ready <= i & 1;

            up_data    <= n;

            @ (posedge clock);

            if (up_valid & up_ready)
                n ++;
        end

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);



        for (i = 0, n = 0; i < 10; i ++)
        begin
            up_valid   <=    i & 1;
            down_ready <= ! (i & 1);

            up_data    <= n;

            @ (posedge clock);

            if (up_valid & up_ready)
                n ++;
        end

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);



        for (i = 0, n = 0; i < 10; i ++)
        begin
            up_valid   <= $urandom_range (1);
            down_ready <= $urandom_range (1);

            up_data    <= n;

            @ (posedge clock);

            if (up_valid & up_ready)
                n ++;
        end

        up_data    <= 8'b0;
        up_valid   <= 1'b0;
        down_ready <= 1'b1;

        repeat (5) @ (posedge clock);

        $finish;
    end

endmodule