data/full_repos/permissive/212763527/others/sources/comp.v
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data/verilator_xmls/5cdc44a7-2851-48a3-a2ad-c2630717d1b0.xml
module comp(
    input CLK, RST,
    input A,B,
    output reg GT, LT, EQ
);
    always @(posedge CLK, negedge RST) begin
        if (RST) 
            {GT, LT, EQ} <= 3'b0;
            
        else
            if (A>B) 
                {GT, LT, EQ} <= 3'b100;
            else if (A==B)
                {GT, LT, EQ} <= 3'b001;
            else
                {GT, LT, EQ} <= 3'b010;
        
    end
endmodule
module comp(
    input CLK, RST,
    input A,B,
    output reg GT, LT, EQ
);

    always @(posedge CLK, negedge RST) begin
        if (RST) 
            {GT, LT, EQ} <= 3'b0;
            
        else
            if (A>B) 
                {GT, LT, EQ} <= 3'b100;
            else if (A==B)
                {GT, LT, EQ} <= 3'b001;
            else
                {GT, LT, EQ} <= 3'b010;
        
    end
endmodule