data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX V1.00/UART_TX/FINAL UI.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: V1.00/UART_TX,data/full_repos/permissive/216654561\n        ... Looked in:\n             data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX/V1.00/UART_TX,data/full_repos/permissive/216654561\n             data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX/V1.00/UART_TX,data/full_repos/permissive/216654561.v\n             data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX/V1.00/UART_TX,data/full_repos/permissive/216654561.sv\n             V1.00/UART_TX,data/full_repos/permissive/216654561\n             V1.00/UART_TX,data/full_repos/permissive/216654561.v\n             V1.00/UART_TX,data/full_repos/permissive/216654561.sv\n             obj_dir/V1.00/UART_TX,data/full_repos/permissive/216654561\n             obj_dir/V1.00/UART_TX,data/full_repos/permissive/216654561.v\n             obj_dir/V1.00/UART_TX,data/full_repos/permissive/216654561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/216654561/HW/Pcores/UART/UART_TX\n%Error: Cannot find file containing module: V1.00/UART_TX/FINAL\n%Error: Cannot find file containing module: UI.v\n%Error: Exiting due to 4 error(s)\n'
module UART_User_interface(
input [7:0]data_in,
input [2:0]addr,
input wr_en,
input rd_en,
input rst,
input clk,
input fifo_full,

output reg [7:0]AXI_data_out,
output reg [7:0]data_fifo,
output reg fifo_wr_en,
output     [7:0]reg_array0,
output     [7:0]reg_array1,
output     [7:0]reg_array3,
output     [7:0]reg_array4
    );
 reg [7:0] mem [0:7];
 
assign reg_array0=mem[0];
assign reg_array1=mem[1];
assign reg_array3=mem[3];
assign reg_array4=mem[4];

always @ (posedge clk) begin
 if (!rst) begin
   
   mem[0] <= 8'b0;
   mem[1] <= 8'b0;
   mem[2] <= 8'b0;
   mem[3] <= 8'b0;
   mem[4] <= 8'b0;
   mem[5] <= 8'b0;
   mem[6] <= 8'b0;
   mem[7] <= 8'b0;
    end
 else begin
   if (wr_en) 
      begin
       mem[addr] <= data_in;
       AXI_data_out <= 0;
         if (addr== 3'b000&& !fifo_full && reg_array3[7] == 0)
         begin
            fifo_wr_en <= 1'b1;
            data_fifo <= data_in;
            mem[5] <= 8'b11111101;
         end 
         else 
         begin
            mem[5]<= 8'b11111111;
            fifo_wr_en <= 1'b0;
            data_fifo <= 8'b0;
         end  
   end	  
   else if (rd_en) begin
	       AXI_data_out <= mem[addr];
   end
   else begin
	      AXI_data_out <= 0;
	      fifo_wr_en <= 1'b0;
	      mem[5]<= 8'b11111111;
   end	 
 end
end
endmodule
module UART_User_interface(
input [7:0]data_in,
input [2:0]addr,
input wr_en,
input rd_en,
input rst,
input clk,
input fifo_full,

output reg [7:0]AXI_data_out,
output reg [7:0]data_fifo,
output reg fifo_wr_en,
output     [7:0]reg_array0,
output     [7:0]reg_array1,
output     [7:0]reg_array3,
output     [7:0]reg_array4
    );

 reg [7:0] mem [0:7];
 
assign reg_array0=mem[0];
assign reg_array1=mem[1];
assign reg_array3=mem[3];
assign reg_array4=mem[4];

always @ (posedge clk) begin
 if (!rst) begin
   
   mem[0] <= 8'b0;
   mem[1] <= 8'b0;
   mem[2] <= 8'b0;
   mem[3] <= 8'b0;
   mem[4] <= 8'b0;
   mem[5] <= 8'b0;
   mem[6] <= 8'b0;
   mem[7] <= 8'b0;
    end
 else begin
   if (wr_en) 
      begin
       mem[addr] <= data_in;
       AXI_data_out <= 0;
         if (addr== 3'b000&& !fifo_full && reg_array3[7] == 0)
         begin
            fifo_wr_en <= 1'b1;
            data_fifo <= data_in;
            mem[5] <= 8'b11111101;
         end 
         else 
         begin
            mem[5]<= 8'b11111111;
            fifo_wr_en <= 1'b0;
            data_fifo <= 8'b0;
         end  
   end	  
   else if (rd_en) begin
	       AXI_data_out <= mem[addr];
   end
   else begin
	      AXI_data_out <= 0;
	      fifo_wr_en <= 1'b0;
	      mem[5]<= 8'b11111111;
   end	 
 end
end
endmodule