data/full_repos/permissive/116563702/fsm/counter/mod3counter_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/116563702/fsm/counter/mod3counter_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n #50 reset = 1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116563702/fsm/counter/mod3counter_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116563702/fsm/counter/mod3counter_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/116563702/fsm/counter/mod3counter_testbench.v:22: Cannot find file containing module: \'mod3counter\'\n   mod3counter uut(clk, reset, y);\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/116563702/fsm/counter,data/full_repos/permissive/116563702/mod3counter\n             data/full_repos/permissive/116563702/fsm/counter,data/full_repos/permissive/116563702/mod3counter.v\n             data/full_repos/permissive/116563702/fsm/counter,data/full_repos/permissive/116563702/mod3counter.sv\n             mod3counter\n             mod3counter.v\n             mod3counter.sv\n             obj_dir/mod3counter\n             obj_dir/mod3counter.v\n             obj_dir/mod3counter.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
   reg clk, reset;
   wire y;

   reg [1:0] state, nextstate;

   initial
     begin
	reset =  0;
	clk = 0;
	#50 reset = 1;
	#20 reset = 0;
     end

   always
     begin
	#5 clk = ~clk;
     end

   mod3counter uut(clk, reset, y);

endmodule
module testbench;

   reg clk, reset;
   wire y;

   reg [1:0] state, nextstate;

   initial
     begin
	reset =  0;
	clk = 0;
	#50 reset = 1;
	#20 reset = 0;
     end

   always
     begin
	#5 clk = ~clk;
     end

   mod3counter uut(clk, reset, y);

endmodule