data/full_repos/permissive/170365068/Single verilog file/mipsFull.v
1: b'%Error: Cannot find file containing module: verilog\n        ... Looked in:\n             data/full_repos/permissive/170365068/Single/verilog\n             data/full_repos/permissive/170365068/Single/verilog.v\n             data/full_repos/permissive/170365068/Single/verilog.sv\n             verilog\n             verilog.v\n             verilog.sv\n             obj_dir/verilog\n             obj_dir/verilog.v\n             obj_dir/verilog.sv\n%Error: Cannot find file containing module: file,data/full_repos/permissive/170365068\n%Error: Cannot find file containing module: data/full_repos/permissive/170365068/Single\n%Error: Cannot find file containing module: file/mipsFull.v\n%Error: Exiting due to 4 error(s)\n'
module control(reset,instruction5,RegDst,Branch,Jump,MemRead,MemtoReg,
				ALUOp,MemWrite,ALUSrc,RegWrite,BranchTest);
	input reset;
	input [5:0] instruction5;
	
	output reg RegDst,Branch,BranchTest,MemRead,Jump,MemtoReg,MemWrite,ALUSrc,RegWrite;
	output reg [1:0] ALUOp;
	
	always@(*)
	begin
		if(reset)
		  begin  
				RegDst=0;
				Branch=0;
				Jump=0;
				BranchTest=0;
				MemRead=0;
				MemtoReg=0;
				ALUOp=0;
				MemWrite=0;
				ALUSrc=0;
				RegWrite=0;	 
		  end  
		  else begin  
			  case(instruction5)
				6'b000000:begin
					RegDst=1;
					Branch=0;
					Jump=0;
					BranchTest=0;
					MemRead=0;
					MemtoReg=0;
					ALUOp=2'b10;
					MemWrite=0;
					ALUSrc=0;
					RegWrite=1;
				end
				6'b100011:begin
					RegDst=0;
					Branch=0;
					Jump=0;
					BranchTest=0;
					MemRead=1;
					MemtoReg=1;
					ALUOp=2'b00;
					MemWrite=0;
					ALUSrc=1;
					RegWrite=1;
				end
				6'b101011:begin
					RegDst=0;
					Branch=0;
					Jump=0;
					BranchTest=0;
					MemRead=0;
					MemtoReg=0;
					ALUOp=2'b00;
					MemWrite=1;
					ALUSrc=1;
					RegWrite=0;	
				end
				6'b101000:begin
					RegDst=0;
					Branch=0;
					Jump=0;
					BranchTest=0;
					MemRead=0;
					MemtoReg=0;
					ALUOp=2'b00;
					MemWrite=0;
					ALUSrc=1;
					RegWrite=1;	
				end
				6'b100110:begin
					RegDst=0;
					Branch=0;
					Jump=1;
					BranchTest=0;
					MemRead=0;
					MemtoReg=0;
					ALUOp=0;
					MemWrite=0;
					ALUSrc=0;
					RegWrite=0;	
				end
				6'b000100:begin
					RegDst=0;
					Branch=1;
					Jump=0;
					BranchTest=0;
					MemRead=0;
					MemtoReg=0;
					ALUOp=2'b01;
					MemWrite=0;
					ALUSrc=0;
					RegWrite=0;	
				end
				6'b000110:begin
					RegDst=0;
					Branch=1;
					Jump=0;
					BranchTest=1;
					MemRead=0;
					MemtoReg=0;
					ALUOp=2'b01;
					MemWrite=0;
					ALUSrc=0;
					RegWrite=0;	
				end
				default :begin
					RegDst=0;
					Branch=0;
					Jump=0;
					MemRead=0;
					MemtoReg=0;
					ALUOp=0;
					MemWrite=0;
					ALUSrc=0;
					RegWrite=0;
				end
			endcase
		end
	end
endmodule
module control(reset,instruction5,RegDst,Branch,Jump,MemRead,MemtoReg,
				ALUOp,MemWrite,ALUSrc,RegWrite,BranchTest);

	input reset;
	input [5:0] instruction5;
	
	output reg RegDst,Branch,BranchTest,MemRead,Jump,MemtoReg,MemWrite,ALUSrc,RegWrite;
	output reg [1:0] ALUOp;
	
	always@(*)
	begin
		if(reset)
		  begin  
				RegDst=0;
				Branch=0;
				Jump=0;
				BranchTest=0;
				MemRead=0;
				MemtoReg=0;
				ALUOp=0;
				MemWrite=0;
				ALUSrc=0;
				RegWrite=0;	 
		  end  
		  else begin  
			  case(instruction5)
				6'b000000:begin
					RegDst=1;
					Branch=0;
					Jump=0;
					BranchTest=0;
					MemRead=0;
					MemtoReg=0;
					ALUOp=2'b10;
					MemWrite=0;
					ALUSrc=0;
					RegWrite=1;
				end
				6'b100011:begin
					RegDst=0;
					Branch=0;
					Jump=0;
					BranchTest=0;
					MemRead=1;
					MemtoReg=1;
					ALUOp=2'b00;
					MemWrite=0;
					ALUSrc=1;
					RegWrite=1;
				end
				6'b101011:begin
					RegDst=0;
					Branch=0;
					Jump=0;
					BranchTest=0;
					MemRead=0;
					MemtoReg=0;
					ALUOp=2'b00;
					MemWrite=1;
					ALUSrc=1;
					RegWrite=0;	
				end
				6'b101000:begin
					RegDst=0;
					Branch=0;
					Jump=0;
					BranchTest=0;
					MemRead=0;
					MemtoReg=0;
					ALUOp=2'b00;
					MemWrite=0;
					ALUSrc=1;
					RegWrite=1;	
				end
				6'b100110:begin
					RegDst=0;
					Branch=0;
					Jump=1;
					BranchTest=0;
					MemRead=0;
					MemtoReg=0;
					ALUOp=0;
					MemWrite=0;
					ALUSrc=0;
					RegWrite=0;	
				end
				6'b000100:begin
					RegDst=0;
					Branch=1;
					Jump=0;
					BranchTest=0;
					MemRead=0;
					MemtoReg=0;
					ALUOp=2'b01;
					MemWrite=0;
					ALUSrc=0;
					RegWrite=0;	
				end
				6'b000110:begin
					RegDst=0;
					Branch=1;
					Jump=0;
					BranchTest=1;
					MemRead=0;
					MemtoReg=0;
					ALUOp=2'b01;
					MemWrite=0;
					ALUSrc=0;
					RegWrite=0;	
				end
				default :begin
					RegDst=0;
					Branch=0;
					Jump=0;
					MemRead=0;
					MemtoReg=0;
					ALUOp=0;
					MemWrite=0;
					ALUSrc=0;
					RegWrite=0;
				end
			endcase
		end
	end
endmodule