data/full_repos/permissive/212897440/sync_fifo.v
1: b"%Error: data/full_repos/permissive/212897440/sync_fifo.v:99: Cannot find file containing module: 'rams_tdp_rf_rf'\nrams_tdp_rf_rf #( \n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/rams_tdp_rf_rf\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/rams_tdp_rf_rf.v\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/rams_tdp_rf_rf.sv\n             rams_tdp_rf_rf\n             rams_tdp_rf_rf.v\n             rams_tdp_rf_rf.sv\n             obj_dir/rams_tdp_rf_rf\n             obj_dir/rams_tdp_rf_rf.v\n             obj_dir/rams_tdp_rf_rf.sv\n%Error: Exiting due to 1 error(s)\n"
module sync_fifo #( parameter

   data_width       = 4,
   address_width    = 4,
   ram_depth        = 16
)(

   output reg signed [data_width-1:0]  data_out,
   output                        full,
   output                        empty,
   output  [address_width-1:0]     data_fill,
   input signed  [data_width-1:0]  data_in,
   input                         w_clk,
   input                         r_clk,
   input                         reset,
   input                         wr_en,
   input                         rd_en);
 


reg      [address_width-1:0]     wr_pointer = 0;
reg      [address_width-1:0]     rd_pointer = 0;

wire  signed   [data_width-1:0]        data_ram ;























 

   always @ (posedge w_clk,posedge reset)
   begin
      if(reset)
         wr_pointer = 0;
      else if(wr_en)
         wr_pointer = wr_pointer+1;

   end

   always @ (posedge r_clk,posedge reset)
   begin
      if(reset)
         rd_pointer = 0;
      else if(rd_en)
         rd_pointer = rd_pointer + 1;

   end

   always @ (posedge r_clk,posedge reset)
   begin
      if(reset)
         data_out=0;
      else if(rd_en)
         data_out=data_ram;
   end

















assign full = (wr_pointer - rd_pointer  == ram_depth) ? 1'b1 : 1'b0 ;
assign empty = (wr_pointer - rd_pointer == 0) ? 1'b1 : 1'b0 ;
assign data_fill = wr_pointer - rd_pointer ;
 
rams_tdp_rf_rf #( 
   .DEPTH(ram_depth),
   .ADDR_WIDTH(address_width),
   .DATA_WIDTH(data_width)
) memory1 (
   .addra(wr_pointer),
   .addrb(rd_pointer),
   .dia(data_in),
   .dib(),
   .doa(),
   .dob(data_ram),
   .wea(wr_en),
   .web(1'b0),
   .ena(1'b1),
   .enb(rd_en),
   .clka(w_clk),
   .clkb(r_clk)
);

endmodule
module sync_fifo #( parameter

   data_width       = 4,
   address_width    = 4,
   ram_depth        = 16
)(

   output reg signed [data_width-1:0]  data_out,
   output                        full,
   output                        empty,
   output  [address_width-1:0]     data_fill,
   input signed  [data_width-1:0]  data_in,
   input                         w_clk,
   input                         r_clk,
   input                         reset,
   input                         wr_en,
   input                         rd_en);

 


reg      [address_width-1:0]     wr_pointer = 0;
reg      [address_width-1:0]     rd_pointer = 0;

wire  signed   [data_width-1:0]        data_ram ;























 

   always @ (posedge w_clk,posedge reset)
   begin
      if(reset)
         wr_pointer = 0;
      else if(wr_en)
         wr_pointer = wr_pointer+1;

   end

   always @ (posedge r_clk,posedge reset)
   begin
      if(reset)
         rd_pointer = 0;
      else if(rd_en)
         rd_pointer = rd_pointer + 1;

   end

   always @ (posedge r_clk,posedge reset)
   begin
      if(reset)
         data_out=0;
      else if(rd_en)
         data_out=data_ram;
   end

















assign full = (wr_pointer - rd_pointer  == ram_depth) ? 1'b1 : 1'b0 ;
assign empty = (wr_pointer - rd_pointer == 0) ? 1'b1 : 1'b0 ;
assign data_fill = wr_pointer - rd_pointer ;
 
rams_tdp_rf_rf #( 
   .DEPTH(ram_depth),
   .ADDR_WIDTH(address_width),
   .DATA_WIDTH(data_width)
) memory1 (
   .addra(wr_pointer),
   .addrb(rd_pointer),
   .dia(data_in),
   .dib(),
   .doa(),
   .dob(data_ram),
   .wea(wr_en),
   .web(1'b0),
   .ena(1'b1),
   .enb(rd_en),
   .clka(w_clk),
   .clkb(r_clk)
);

endmodule