data/full_repos/permissive/205055389/test/verga/adder3.v
1: b'%Error: data/full_repos/permissive/205055389/test/verga/adder3.v:11: Unsupported or unknown PLI call: $monitor\n $monitor("%d: %h = %h + %h + %h",$time,{co,s},a,b,ci);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/adder3.v:13: Unsupported: Ignoring delay on this delayed statement.\n #2 a = 4\'b0; b = 4\'b0; ci = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/adder3.v:14: Unsupported: Ignoring delay on this delayed statement.\n #2 a = 4\'h2; b = 4\'h7; ci = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/adder3.v:15: Unsupported: Ignoring delay on this delayed statement.\n #2 a = 4\'h2; b = 4\'h7; ci = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/adder3.v:16: Unsupported: Ignoring delay on this delayed statement.\n #2 a = 4\'h9; b = 4\'h3; ci = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/adder3.v:17: Unsupported: Ignoring delay on this delayed statement.\n #2 a = 4\'hf; b = 4\'h3; ci = 1\'b0;\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  wire [3:0] s;
  wire co;
  reg [3:0] a,b;
  reg ci;

  adder a1 (s, co, a, b, ci);

  initial
    begin
	$monitor("%d: %h = %h + %h + %h",$time,{co,s},a,b,ci);

	#2 a = 4'b0; b = 4'b0; ci = 1'b0;
	#2 a = 4'h2; b = 4'h7; ci = 1'b0;
	#2 a = 4'h2; b = 4'h7; ci = 1'b1;
	#2 a = 4'h9; b = 4'h3; ci = 1'b1;
	#2 a = 4'hf; b = 4'h3; ci = 1'b0;
    end

endmodule
module top;

  wire [3:0] s;
  wire co;
  reg [3:0] a,b;
  reg ci;

  adder a1 (s, co, a, b, ci);

  initial
    begin
	$monitor("%d: %h = %h + %h + %h",$time,{co,s},a,b,ci);

	#2 a = 4'b0; b = 4'b0; ci = 1'b0;
	#2 a = 4'h2; b = 4'h7; ci = 1'b0;
	#2 a = 4'h2; b = 4'h7; ci = 1'b1;
	#2 a = 4'h9; b = 4'h3; ci = 1'b1;
	#2 a = 4'hf; b = 4'h3; ci = 1'b0;
    end

endmodule