data/full_repos/permissive/102388603/timer32.v
data/verilator_xmls/7b114562-b96f-45cc-81bf-9f8aabbb289b.xml
module timer32(
	input clk,
	input rst,
	input [31:0]period,
	output reg out);
	
	reg [31:0]counter;
	
	always @(posedge clk, posedge rst)
	if(rst)
		begin

		counter <= 0;
		end
	else

		if(counter == 0)
			begin
				counter <= period - 1;
				out <= 1;
			end
		else

			begin
				counter <= counter - 1;
				out <= 0;
			end

endmodule
module timer32(
	input clk,
	input rst,
	input [31:0]period,
	output reg out);

	
	reg [31:0]counter;
	
	always @(posedge clk, posedge rst)
	if(rst)
		begin

		counter <= 0;
		end
	else

		if(counter == 0)
			begin
				counter <= period - 1;
				out <= 1;
			end
		else

			begin
				counter <= counter - 1;
				out <= 0;
			end

endmodule