data/full_repos/permissive/174369527/SPI/spi_slave_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:3: Cannot find include file: spi_master.v\n`include "spi_master.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174369527/SPI,data/full_repos/permissive/174369527/spi_master.v\n             data/full_repos/permissive/174369527/SPI,data/full_repos/permissive/174369527/spi_master.v.v\n             data/full_repos/permissive/174369527/SPI,data/full_repos/permissive/174369527/spi_master.v.sv\n             spi_master.v\n             spi_master.v.v\n             spi_master.v.sv\n             obj_dir/spi_master.v\n             obj_dir/spi_master.v.v\n             obj_dir/spi_master.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #(c_CLOCK_PERIOD_NS/2) r_clock <= !r_clock;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:20: syntax error, unexpected wire, expecting \',\' or \';\'\n  wire [c_SPI_SIZE-1:0] w_rx_data = 0;\n  ^~~~\n%Error: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:26: syntax error, unexpected wire, expecting \'[\'\n    input wire [c_SPI_SIZE-1:0] i_tx_data;\n          ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #(c_delay);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #(c_SPI_HALF_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #(c_SPI_HALF_PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #(c_SPI_HALF_PERIOD);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #(c_SPI_HALF_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #(c_SPI_HALF_PERIOD);  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n      #(200);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n      #(200);\n      ^\n%Error: data/full_repos/permissive/174369527/SPI/spi_slave_tb.v:79: syntax error, unexpected \'@\'\n      @(posedge r_clock);\n      ^\n%Error: Exiting due to 4 error(s), 9 warning(s)\n'
module spi_master_tb ();

  reg r_rst = 1;
 
  parameter c_CLOCK_PERIOD_NS = 20;
  reg r_clock = 0;
  always
    #(c_CLOCK_PERIOD_NS/2) r_clock <= !r_clock;

  wire w_spi_miso;
  reg r_spi_ss = 1'b1;
  reg r_spi_mosi = 1'b0;
  reg r_spi_clk = 1'b0;
  reg [c_SPI_SIZE-1:0] r_miso_data = 0;
  reg [c_SPI_SIZE-1:0] r_tx_data = 0
  wire [c_SPI_SIZE-1:0] w_rx_data = 0;

  parameter c_SPI_HALF_PERIOD = 1000;
  parameter c_delay = 7;
  parameter c_SPI_SIZE = 8;
  task SPI_WRITE_BYTE;
    input wire [c_SPI_SIZE-1:0] i_tx_data;
    integer     ii;



    begin
      #(c_delay);
      r_spi_clk <= 1'b0;
      r_spi_mosi <= 1'b0;
      r_spi_ss <= 1'b0;
      #(c_SPI_HALF_PERIOD);


      for (ii=0; ii<c_SPI_SIZE; ii=ii+1)
      begin
        r_spi_mosi <= i_tx_data[ii];
        #(c_SPI_HALF_PERIOD);
        r_spi_clk <= 1'b1;
        r_miso_data[ii] <= w_spi_miso;
        #(c_SPI_HALF_PERIOD);
        r_spi_clk <= 1'b0;
      end

      #(c_SPI_HALF_PERIOD);
      r_spi_ss <= 1'b1;
      $display("%0t SPI WRITE done W:0x%0h R:0x%0h", $time, i_tx_data, r_miso_data);
      #(c_SPI_HALF_PERIOD);
     end
  endtask
   
   
  spi_slave #(.c_SPI_SIZE(c_SPI_SIZE)) SPI_SLAVE_INST
    (.i_clock(r_clock),
     .i_rst(r_rst),
     .i_spi_clk(r_spi_clk),
     .i_spi_ss(r_spi_ss),
     .i_spi_mosi(r_spi_mosi),
     .i_tx_data(r_tx_data),
     .o_spi_miso(w_spi_miso),
     .o_rx_data(w_rx_data)
     );

  initial
    begin
      r_rst = 1;

      #(200);
      r_rst = 0;
      r_tx_data = 8'h64;
      #(200);

      SPI_WRITE_BYTE(8'h3F);

      @(posedge r_clock);
      if (w_rx_data == 8'h3F)
        $display("RX Passed - Correct Byte Received");
      else
        $display("RX Failed - Incorrect Byte Received");
      if (r_tx_data == r_miso_data)
        $display("TX Passed - Correct Byte Received");
      else
        $display("TX Failed - Incorrect Byte Received");
      
      $finish;
    end
   
endmodule
module spi_master_tb ();


  reg r_rst = 1;
 
  parameter c_CLOCK_PERIOD_NS = 20;
  reg r_clock = 0;
  always
    #(c_CLOCK_PERIOD_NS/2) r_clock <= !r_clock;

  wire w_spi_miso;
  reg r_spi_ss = 1'b1;
  reg r_spi_mosi = 1'b0;
  reg r_spi_clk = 1'b0;
  reg [c_SPI_SIZE-1:0] r_miso_data = 0;
  reg [c_SPI_SIZE-1:0] r_tx_data = 0
  wire [c_SPI_SIZE-1:0] w_rx_data = 0;

  parameter c_SPI_HALF_PERIOD = 1000;
  parameter c_delay = 7;
  parameter c_SPI_SIZE = 8;
  task SPI_WRITE_BYTE;
    input wire [c_SPI_SIZE-1:0] i_tx_data;
    integer     ii;



    begin
      #(c_delay);
      r_spi_clk <= 1'b0;
      r_spi_mosi <= 1'b0;
      r_spi_ss <= 1'b0;
      #(c_SPI_HALF_PERIOD);


      for (ii=0; ii<c_SPI_SIZE; ii=ii+1)
      begin
        r_spi_mosi <= i_tx_data[ii];
        #(c_SPI_HALF_PERIOD);
        r_spi_clk <= 1'b1;
        r_miso_data[ii] <= w_spi_miso;
        #(c_SPI_HALF_PERIOD);
        r_spi_clk <= 1'b0;
      end

      #(c_SPI_HALF_PERIOD);
      r_spi_ss <= 1'b1;
      $display("%0t SPI WRITE done W:0x%0h R:0x%0h", $time, i_tx_data, r_miso_data);
      #(c_SPI_HALF_PERIOD);
     end
  endtask
   
   
  spi_slave #(.c_SPI_SIZE(c_SPI_SIZE)) SPI_SLAVE_INST
    (.i_clock(r_clock),
     .i_rst(r_rst),
     .i_spi_clk(r_spi_clk),
     .i_spi_ss(r_spi_ss),
     .i_spi_mosi(r_spi_mosi),
     .i_tx_data(r_tx_data),
     .o_spi_miso(w_spi_miso),
     .o_rx_data(w_rx_data)
     );

  initial
    begin
      r_rst = 1;

      #(200);
      r_rst = 0;
      r_tx_data = 8'h64;
      #(200);

      SPI_WRITE_BYTE(8'h3F);

      @(posedge r_clock);
      if (w_rx_data == 8'h3F)
        $display("RX Passed - Correct Byte Received");
      else
        $display("RX Failed - Incorrect Byte Received");
      if (r_tx_data == r_miso_data)
        $display("TX Passed - Correct Byte Received");
      else
        $display("TX Failed - Incorrect Byte Received");
      
      $finish;
    end
   
endmodule