data/full_repos/permissive/114421971/rom/top.v
1: b"%Error: data/full_repos/permissive/114421971/rom/top.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n                                      ^~\n%Error: data/full_repos/permissive/114421971/rom/top.v:27: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n        ^~\n%Error: Exiting due to 2 error(s)\n"
module rom_ROM128X1 (input clk, input [7:0] din, output [7:0] dout);
    parameter LOC="SLICE_FIXME";


    ROM128X1 #(.INIT(128'b0))
            rom(
            .O(dout[0]),
            .A0(din[0]),
            .A1(din[1]),
            .A2(din[2]),
            .A3(din[3]),
            .A4(din[4]),
            .A5(din[5]),
            .A6(din[6]));
endmodule
module rom_ROM128X1 (input clk, input [7:0] din, output [7:0] dout);

    parameter LOC="SLICE_FIXME";


    ROM128X1 #(.INIT(128'b0))
            rom(
            .O(dout[0]),
            .A0(din[0]),
            .A1(din[1]),
            .A2(din[2]),
            .A3(din[3]),
            .A4(din[4]),
            .A5(din[5]),
            .A6(din[6]));
endmodule