data/full_repos/permissive/143278/ivltests/port-test7.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test7.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #(2*1) clk <= 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test7.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #(2*1) if (q !== d) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test7.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #(1 + 1) if (q !== 8\'h00) begin\n      ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ansireg(input clk, reset, input [7:0] d, output reg [7:0] q );
always @(posedge clk or posedge reset)
   if(reset)
     q <= #(`REG_DELAY) 8'h00;
   else
     q <= #(`REG_DELAY) d;

endmodule
module ansireg(input clk, reset, input [7:0] d, output reg [7:0] q );

always @(posedge clk or posedge reset)
   if(reset)
     q <= #(`REG_DELAY) 8'h00;
   else
     q <= #(`REG_DELAY) d;

endmodule