data/full_repos/permissive/157101210/branchTest.t.v
1: b'%Error: data/full_repos/permissive/157101210/branchTest.t.v:1: Cannot find include file: branchTest.v\n`include "branchTest.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/branchTest.v\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/branchTest.v.v\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/branchTest.v.sv\n             branchTest.v\n             branchTest.v.v\n             branchTest.v.sv\n             obj_dir/branchTest.v\n             obj_dir/branchTest.v.v\n             obj_dir/branchTest.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/157101210/branchTest.t.v:16: Unsupported: Ignoring delay on this delayed statement.\n  opcode=6\'b000101; Da=32\'d1; Db=32\'d3; #100\n                                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157101210/branchTest.t.v:20: Unsupported: Ignoring delay on this delayed statement.\n  opcode=6\'b000101; Da=32\'d3; Db=32\'d3; #100\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/branchTest.t.v:24: Unsupported: Ignoring delay on this delayed statement.\n  opcode=6\'b000100; Da=32\'d3; Db=32\'d3; #100\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/branchTest.t.v:28: Unsupported: Ignoring delay on this delayed statement.\n  opcode=6\'b000100; Da=32\'d1; Db=32\'d3; #100\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/branchTest.t.v:32: Unsupported: Ignoring delay on this delayed statement.\n  opcode=6\'b000000; Da=32\'d1; Db=32\'d3; #100\n                                        ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module branchTestTest ();
	reg[5:0] opcode;
	reg[31:0] Da, Db, initialBranchAddress;
	wire[31:0] branchAddress;

	branchTest branchTest(opcode, Da, Db, initialBranchAddress, branchAddress);

	initial begin
		$display("Starting branch test test");
		initialBranchAddress = 32'b11111111111111110000000000000000;


		opcode=6'b000101; Da=32'd1; Db=32'd3; #100
		if (branchAddress !== initialBranchAddress) $display("Test 1 failed - %b", branchAddress);


		opcode=6'b000101; Da=32'd3; Db=32'd3; #100
		if (branchAddress !== 32'b0) $display("Test 2 failed - %b", branchAddress);


		opcode=6'b000100; Da=32'd3; Db=32'd3; #100
		if (branchAddress !== initialBranchAddress) $display("Test 3 failed - %b", branchAddress);


		opcode=6'b000100; Da=32'd1; Db=32'd3; #100
		if (branchAddress !== 32'b0) $display("Test 4 failed - %b", branchAddress);


		opcode=6'b000000; Da=32'd1; Db=32'd3; #100
		if (branchAddress !== 32'b0) $display("Test 5 failed - %b", branchAddress);

		$display("Finished branch test test");
	end

endmodule
module branchTestTest ();

	reg[5:0] opcode;
	reg[31:0] Da, Db, initialBranchAddress;
	wire[31:0] branchAddress;

	branchTest branchTest(opcode, Da, Db, initialBranchAddress, branchAddress);

	initial begin
		$display("Starting branch test test");
		initialBranchAddress = 32'b11111111111111110000000000000000;


		opcode=6'b000101; Da=32'd1; Db=32'd3; #100
		if (branchAddress !== initialBranchAddress) $display("Test 1 failed - %b", branchAddress);


		opcode=6'b000101; Da=32'd3; Db=32'd3; #100
		if (branchAddress !== 32'b0) $display("Test 2 failed - %b", branchAddress);


		opcode=6'b000100; Da=32'd3; Db=32'd3; #100
		if (branchAddress !== initialBranchAddress) $display("Test 3 failed - %b", branchAddress);


		opcode=6'b000100; Da=32'd1; Db=32'd3; #100
		if (branchAddress !== 32'b0) $display("Test 4 failed - %b", branchAddress);


		opcode=6'b000000; Da=32'd1; Db=32'd3; #100
		if (branchAddress !== 32'b0) $display("Test 5 failed - %b", branchAddress);

		$display("Finished branch test test");
	end

endmodule