data/full_repos/permissive/148324174/CombLogic/TestBench.v
 line:27: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/TestBench.v:20: Unsupported: Ignoring delay on this delayed statement.\n #1 Astim = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/TestBench.v:21: Unsupported: Ignoring delay on this delayed statement.\n #1 Bstim = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/TestBench.v:22: Unsupported: Ignoring delay on this delayed statement.\n #1 Cstim = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/TestBench.v:23: Unsupported: Ignoring delay on this delayed statement.\n #50 Dstim = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/TestBench.v:24: Unsupported: Ignoring delay on this delayed statement.\n #50 Astim = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/TestBench.v:25: Unsupported: Ignoring delay on this delayed statement.\n #50 Cstim = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/TestBench.v:26: Unsupported: Ignoring delay on this delayed statement.\n #50 Dstim = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/TestBench.v:27: Unsupported: Ignoring delay on this delayed statement.\n #50 $finish;\n ^\n%Error: data/full_repos/permissive/148324174/CombLogic/TestBench.v:8: Cannot find file containing module: \'Intro_Top\'\nIntro_Top Top1(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/148324174/CombLogic,data/full_repos/permissive/148324174/Intro_Top\n             data/full_repos/permissive/148324174/CombLogic,data/full_repos/permissive/148324174/Intro_Top.v\n             data/full_repos/permissive/148324174/CombLogic,data/full_repos/permissive/148324174/Intro_Top.sv\n             Intro_Top\n             Intro_Top.v\n             Intro_Top.sv\n             obj_dir/Intro_Top\n             obj_dir/Intro_Top.v\n             obj_dir/Intro_Top.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestBench;

reg Astim, Bstim, Cstim, Dstim;
wire Xwatch, Ywatch, Zwatch;

Intro_Top Top1(
	.X(Xwatch),
	.Y(Ywatch),
	.Z(Zwatch),
	.A(Astim),
	.B(Bstim),
	.C(Cstim),
	.D(Dstim)
	);

initial
begin
	#1 Astim = 1'b0;
	#1 Bstim = 1'b0;
	#1 Cstim = 1'b0;
	#50 Dstim = 1'b1;
	#50 Astim = 1'b0;
	#50 Cstim = 1'b0;
	#50 Dstim = 1'b0;
	#50 $finish;
end


endmodule
module TestBench;


reg Astim, Bstim, Cstim, Dstim;
wire Xwatch, Ywatch, Zwatch;

Intro_Top Top1(
	.X(Xwatch),
	.Y(Ywatch),
	.Z(Zwatch),
	.A(Astim),
	.B(Bstim),
	.C(Cstim),
	.D(Dstim)
	);

initial
begin
	#1 Astim = 1'b0;
	#1 Bstim = 1'b0;
	#1 Cstim = 1'b0;
	#50 Dstim = 1'b1;
	#50 Astim = 1'b0;
	#50 Cstim = 1'b0;
	#50 Dstim = 1'b0;
	#50 $finish;
end


endmodule