data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v
 line:45: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #100000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #100000;\n ^\n%Error: data/full_repos/permissive/106583614/Lab2/UARTTransmeter_tb.v:14: Cannot find file containing module: \'UARTTransmeter\'\n UARTTransmeter uart_transmitter_0(\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTTransmeter\n             data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTTransmeter.v\n             data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTTransmeter.sv\n             UARTTransmeter\n             UARTTransmeter.v\n             UARTTransmeter.sv\n             obj_dir/UARTTransmeter\n             obj_dir/UARTTransmeter.v\n             obj_dir/UARTTransmeter.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UARTTransmeter_tb;
reg clk;
reg rst_n;

reg [2:0] baud_in;

reg [7:0] Tx_DATA;
reg Tx_EN, Tx_WR;

wire Tx_BUSY, Tx_D;

 UARTTransmeter uart_transmitter_0(
	.clk(clk) ,
	.reset(rst_n) ,
	.Tx_DATA(Tx_DATA) ,
	.baud_select(baud_in) ,
	.Tx_WR(Tx_WR) ,
	.Tx_EN(Tx_EN) ,
	.Tx_D(Tx_D) ,
	.Tx_BUSY(Tx_BUSY)
);

localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;

initial 
begin
	clk = 1;
	Tx_EN = 0;
	baud_in = 3'b111;
	Tx_WR = 0;
	rst_n = 1;
	#10;
	rst_n = 0;
	Tx_DATA = 8'b00001111;
	Tx_WR = 1;
	
	#10;
	Tx_WR = 0;
	Tx_EN = 1;
	#10
	
	#100000
	Tx_WR = 1;
	Tx_DATA = 8'b11101010;
	#10;
	Tx_WR = 0;
	#100;



	#100000;

	Tx_WR = 0;

	$finish;
end

endmodule
module UARTTransmeter_tb;

reg clk;
reg rst_n;

reg [2:0] baud_in;

reg [7:0] Tx_DATA;
reg Tx_EN, Tx_WR;

wire Tx_BUSY, Tx_D;

 UARTTransmeter uart_transmitter_0(
	.clk(clk) ,
	.reset(rst_n) ,
	.Tx_DATA(Tx_DATA) ,
	.baud_select(baud_in) ,
	.Tx_WR(Tx_WR) ,
	.Tx_EN(Tx_EN) ,
	.Tx_D(Tx_D) ,
	.Tx_BUSY(Tx_BUSY)
);

localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;

initial 
begin
	clk = 1;
	Tx_EN = 0;
	baud_in = 3'b111;
	Tx_WR = 0;
	rst_n = 1;
	#10;
	rst_n = 0;
	Tx_DATA = 8'b00001111;
	Tx_WR = 1;
	
	#10;
	Tx_WR = 0;
	Tx_EN = 1;
	#10
	
	#100000
	Tx_WR = 1;
	Tx_DATA = 8'b11101010;
	#10;
	Tx_WR = 0;
	#100;



	#100000;

	Tx_WR = 0;

	$finish;
end

endmodule