data/full_repos/permissive/169574047/basic_grammar/basic_grammar.srcs/sources_1/new/basic.v
'utf-8' codec can't decode byte 0xca in position 502: invalid continuation byte
1: b'%Error: data/full_repos/permissive/169574047/basic_grammar/basic_grammar.srcs/sources_1/new/basic.v:203: Cannot find include file: header.v\n    `include "header.v" \n             ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169574047/basic_grammar/basic_grammar.srcs/sources_1/new,data/full_repos/permissive/169574047/header.v\n             data/full_repos/permissive/169574047/basic_grammar/basic_grammar.srcs/sources_1/new,data/full_repos/permissive/169574047/header.v.v\n             data/full_repos/permissive/169574047/basic_grammar/basic_grammar.srcs/sources_1/new,data/full_repos/permissive/169574047/header.v.sv\n             header.v\n             header.v.v\n             header.v.sv\n             obj_dir/header.v\n             obj_dir/header.v.v\n             obj_dir/header.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/169574047/basic_grammar/basic_grammar.srcs/sources_1/new/basic.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #100 reset = 1\'b0;   \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/169574047/basic_grammar/basic_grammar.srcs/sources_1/new/basic.v:193: Unsupported or unknown PLI call: $monitor\n        $monitor($time,"value:%b,reset=%b",clock,reset);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/169574047/basic_grammar/basic_grammar.srcs/sources_1/new/basic.v:195: Unsupported: Ignoring delay on this delayed statement.\n        #100 $stop;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/basic_grammar/basic_grammar.srcs/sources_1/new/basic.v:196: Unsupported: Ignoring delay on this delayed statement.\n        #900 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module basic(
clk
    );



    

    reg a = 4'b1111;
    reg b = 12'habc;
    reg c = 16'd255;
    
    reg d = 23456;
    reg e = 'hc3;
    reg f = 'o21;
    
    reg g = 12'h13x;
    reg h = 6'hx;
    reg i = 32'bz;
    
    reg j = -6'd3;
    reg k = -6'sd3;
    
    reg l = 12'b1111_0000_1111;
    reg m = 4'b10??;
    
    reg n = "Hello world";
    reg o = "a / b";
    

    reg value;
    input clk;
    

    





    









    

    wire wa;
    wire wb,wc;
    wire wd = 1'b0;
    

    reg reset;
    initial
    begin
        reset = 1'b1;
        #100 reset = 1'b0;
    end
    
    reg signed [63:0] rm;
    integer ii;
    

    wire va;
    wire[7:0] vbus;
    wire[31:0] vbusA,vbusB,vbusC;
    reg vclock;
    reg[0:40] vvitural_addr;
    



    
    reg [255:0] vdata1;
    reg [0:255] vdata2;
    reg [7:0] vbyte;
    integer byteNum=1;
    
    initial
    begin
        vbyte=vdata1[31-:8];
        vbyte=vdata1[24+:8];
        vbyte=vdata2[31-:8];
        vbyte=vdata2[24+:8];
    
        for(j=0;j<31;j=j+1)
            vbyte=vdata1[(j*8)+:8];
    

        vdata1[(byteNum*8)+:8]=8'b0;
    end
    

    integer counter;
    initial
        counter=-1;
        

    real delta;
    initial
    begin
        delta=4e10;
        delta=2.13;
    end
    integer inti;
    initial
        inti=delta;


    time save_sim_time;
    initial
        save_sim_time= $time;
    

    integer count[0:7];
    reg bool[31:0];
    time chk_point[1:100];
    reg[4:0] port_id[0:7];
    integer matrix[4:0][0:255];
    reg[63:0] array_4d[15:0][7:0][7:0][255:0];
    wire[7:0] w_array2[5:0];
    wire w_array1[7:0][5:0];
    
    initial
    begin
        count[5]=0;
        chk_point[100]=0;
        port_id[3]=0;
        
        matrix[1][0]=35559;
        array_4d[0][0][0][0][15:0]=0;
        



    end
    

    reg mem1bit[0:1023];
    reg[7:0] membyte[0:1023];
    initial
        membyte[511]=0;
    

    parameter paraport_id=5;
    parameter cache_line_width=256;
    parameter signed [15:0] WIDTH=0;

    localparam  state1=4'b0001,
                state2=4'b0010,
                state3=4'b0100,
                state4=4'b1000;

    reg [8*18:1] string_value;
    initial
        string_value="Hello Verilog World";
    
    initial
    begin
        $display("Hello Verilog World");
        $display($time);
        $display("time:%d,value:%h",$time,virtual_addr);
        $display("ID:%b",port_id);
        $display("This string is displayed from %m level of hierarchy");
        $display("This is a\n multiline string with a %% sign");
        $monitor($time,"value:%b,reset=%b",clock,reset);
        
        #100 $stop;
        #900 $finish;
    end
    
    `define WORD_SIZE 32
    `define S $stop
    `define WORD_REG reg [31:0]
    
    `include "header.v"
    
endmodule
module basic(
clk
    );




    

    reg a = 4'b1111;
    reg b = 12'habc;
    reg c = 16'd255;
    
    reg d = 23456;
    reg e = 'hc3;
    reg f = 'o21;
    
    reg g = 12'h13x;
    reg h = 6'hx;
    reg i = 32'bz;
    
    reg j = -6'd3;
    reg k = -6'sd3;
    
    reg l = 12'b1111_0000_1111;
    reg m = 4'b10??;
    
    reg n = "Hello world";
    reg o = "a / b";
    

    reg value;
    input clk;
    

    





    









    

    wire wa;
    wire wb,wc;
    wire wd = 1'b0;
    

    reg reset;
    initial
    begin
        reset = 1'b1;
        #100 reset = 1'b0;
    end
    
    reg signed [63:0] rm;
    integer ii;
    

    wire va;
    wire[7:0] vbus;
    wire[31:0] vbusA,vbusB,vbusC;
    reg vclock;
    reg[0:40] vvitural_addr;
    



    
    reg [255:0] vdata1;
    reg [0:255] vdata2;
    reg [7:0] vbyte;
    integer byteNum=1;
    
    initial
    begin
        vbyte=vdata1[31-:8];
        vbyte=vdata1[24+:8];
        vbyte=vdata2[31-:8];
        vbyte=vdata2[24+:8];
    
        for(j=0;j<31;j=j+1)
            vbyte=vdata1[(j*8)+:8];
    

        vdata1[(byteNum*8)+:8]=8'b0;
    end
    

    integer counter;
    initial
        counter=-1;
        

    real delta;
    initial
    begin
        delta=4e10;
        delta=2.13;
    end
    integer inti;
    initial
        inti=delta;


    time save_sim_time;
    initial
        save_sim_time= $time;
    

    integer count[0:7];
    reg bool[31:0];
    time chk_point[1:100];
    reg[4:0] port_id[0:7];
    integer matrix[4:0][0:255];
    reg[63:0] array_4d[15:0][7:0][7:0][255:0];
    wire[7:0] w_array2[5:0];
    wire w_array1[7:0][5:0];
    
    initial
    begin
        count[5]=0;
        chk_point[100]=0;
        port_id[3]=0;
        
        matrix[1][0]=35559;
        array_4d[0][0][0][0][15:0]=0;
        



    end
    

    reg mem1bit[0:1023];
    reg[7:0] membyte[0:1023];
    initial
        membyte[511]=0;
    

    parameter paraport_id=5;
    parameter cache_line_width=256;
    parameter signed [15:0] WIDTH=0;

    localparam  state1=4'b0001,
                state2=4'b0010,
                state3=4'b0100,
                state4=4'b1000;

    reg [8*18:1] string_value;
    initial
        string_value="Hello Verilog World";
    
    initial
    begin
        $display("Hello Verilog World");
        $display($time);
        $display("time:%d,value:%h",$time,virtual_addr);
        $display("ID:%b",port_id);
        $display("This string is displayed from %m level of hierarchy");
        $display("This is a\n multiline string with a %% sign");
        $monitor($time,"value:%b,reset=%b",clock,reset);
        
        #100 $stop;
        #900 $finish;
    end
    
    `define WORD_SIZE 32
    `define S $stop
    `define WORD_REG reg [31:0]
    
    `include "header.v"
    
endmodule