data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v
 line:27: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = (clk === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:27: Unsupported: event data types\n event ser_sample;\n ^~~~~\n%Error: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:30: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("testbench.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:31: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, testbench);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:34: syntax error, unexpected \'@\'\n   repeat (50000) @(posedge clk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b", leds);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #10 rst <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #10000 rst <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst <= 1\'b0;\n  ^\n%Error: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:108: syntax error, unexpected \'@\'\n  @(negedge ser_tx);\n  ^\n%Error: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:110: syntax error, unexpected \'@\'\n  repeat (ser_half_period) @(posedge clk);\n                           ^\n%Error: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:114: syntax error, unexpected \'@\'\n   repeat (ser_half_period) @(posedge clk);\n                            ^\n%Error: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:115: syntax error, unexpected \'@\'\n   repeat (ser_half_period) @(posedge clk);\n                            ^\n%Error: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:117: syntax error, unexpected ->\n   -> ser_sample;  \n   ^~\n%Error: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:120: syntax error, unexpected \'@\'\n  repeat (ser_half_period) @(posedge clk);\n                           ^\n%Error: data/full_repos/permissive/160073872/fpga/sw/tb/testbench.v:121: syntax error, unexpected \'@\'\n  repeat (ser_half_period) @(posedge clk);\n                           ^\n%Error: Exiting due to 11 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
	reg clk;
	always #5 clk = (clk === 1'b0);

	localparam ser_half_period = 53;
	event ser_sample;

	initial begin
		$dumpfile("testbench.vcd");
		$dumpvars(0, testbench);

		repeat (6) begin
			repeat (50000) @(posedge clk);
			$display("+50000 cycles");
		end
		$finish;
	end

	integer cycle_cnt = 0;

	always @(posedge clk) begin
		cycle_cnt <= cycle_cnt + 1;
	end

	wire [7:0] leds;

	wire ser_rx;
	wire ser_tx;

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;
	wire flash_io2;
	wire flash_io3;

	always @(leds) begin
		#1 $display("%b", leds);
	end


	reg rst = 1'b1;
	initial begin
		#10 rst <= 1'b0;
		#10000 rst <= 1'b1;
		#25 rst <= 1'b0;
	end
	
	main_wrapper inst(
		.SYS_CLK_I(clk),
		.PB_RST(rst),

		.USB_UART_RXD(ser_rx),
		.USB_UART_TXD(ser_tx),


		.NetR32_1(flash_clk),
		.QSPI_CSn(flash_csb),
		
		.QSPI_DQ0(flash_io0),
		.QSPI_DQ1(flash_io1),
		.QSPI_DQ2(flash_io2),
		.QSPI_DQ3(flash_io3),

		.USER_LED1(leds[0]),
		.USER_LED2(leds[1]),
		.USER_LED3(leds[2]),
		.USER_LED4(leds[3]),
		.USER_LED5(leds[4]),
		.USER_LED6(leds[5]),
		.USER_LED7(leds[6]),
		.USER_LED8(leds[7])
	);

	spiflash spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(flash_io2),
		.io3(flash_io3)
	);

	reg [7:0] buffer;

	always begin
		@(negedge ser_tx);

		repeat (ser_half_period) @(posedge clk);
		-> ser_sample;

		repeat (8) begin
			repeat (ser_half_period) @(posedge clk);
			repeat (ser_half_period) @(posedge clk);
			buffer = {ser_tx, buffer[7:1]};
			-> ser_sample;
		end

		repeat (ser_half_period) @(posedge clk);
		repeat (ser_half_period) @(posedge clk);
		-> ser_sample;

		if (buffer < 32 || buffer >= 127)
			$display("Serial data: %d", buffer);
		else
			$display("Serial data: '%c'", buffer);
	end
endmodule
module testbench;

	reg clk;
	always #5 clk = (clk === 1'b0);

	localparam ser_half_period = 53;
	event ser_sample;

	initial begin
		$dumpfile("testbench.vcd");
		$dumpvars(0, testbench);

		repeat (6) begin
			repeat (50000) @(posedge clk);
			$display("+50000 cycles");
		end
		$finish;
	end

	integer cycle_cnt = 0;

	always @(posedge clk) begin
		cycle_cnt <= cycle_cnt + 1;
	end

	wire [7:0] leds;

	wire ser_rx;
	wire ser_tx;

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;
	wire flash_io2;
	wire flash_io3;

	always @(leds) begin
		#1 $display("%b", leds);
	end


	reg rst = 1'b1;
	initial begin
		#10 rst <= 1'b0;
		#10000 rst <= 1'b1;
		#25 rst <= 1'b0;
	end
	
	main_wrapper inst(
		.SYS_CLK_I(clk),
		.PB_RST(rst),

		.USB_UART_RXD(ser_rx),
		.USB_UART_TXD(ser_tx),


		.NetR32_1(flash_clk),
		.QSPI_CSn(flash_csb),
		
		.QSPI_DQ0(flash_io0),
		.QSPI_DQ1(flash_io1),
		.QSPI_DQ2(flash_io2),
		.QSPI_DQ3(flash_io3),

		.USER_LED1(leds[0]),
		.USER_LED2(leds[1]),
		.USER_LED3(leds[2]),
		.USER_LED4(leds[3]),
		.USER_LED5(leds[4]),
		.USER_LED6(leds[5]),
		.USER_LED7(leds[6]),
		.USER_LED8(leds[7])
	);

	spiflash spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(flash_io2),
		.io3(flash_io3)
	);

	reg [7:0] buffer;

	always begin
		@(negedge ser_tx);

		repeat (ser_half_period) @(posedge clk);
		-> ser_sample;

		repeat (8) begin
			repeat (ser_half_period) @(posedge clk);
			repeat (ser_half_period) @(posedge clk);
			buffer = {ser_tx, buffer[7:1]};
			-> ser_sample;
		end

		repeat (ser_half_period) @(posedge clk);
		repeat (ser_half_period) @(posedge clk);
		-> ser_sample;

		if (buffer < 32 || buffer >= 127)
			$display("Serial data: %d", buffer);
		else
			$display("Serial data: '%c'", buffer);
	end
endmodule