data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v
1: b"%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:38: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Sl_pad[1]/U0/U1  (.D(Disp_dat11), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1,data/full_repos/permissive/165160692/IOTRI_OB_EB\n             data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1,data/full_repos/permissive/165160692/IOTRI_OB_EB.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1,data/full_repos/permissive/165160692/IOTRI_OB_EB.sv\n             IOTRI_OB_EB\n             IOTRI_OB_EB.v\n             IOTRI_OB_EB.sv\n             obj_dir/IOTRI_OB_EB\n             obj_dir/IOTRI_OB_EB.v\n             obj_dir/IOTRI_OB_EB.sv\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:40: Cannot find file containing module: 'DFN1C1'\n    DFN1C1 \\count[1]  (.D(SUM1_0), .CLK(Clk_c), .CLR(Reset_c), .Q(\n    ^~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:42: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Sl_pad[3]/U0/U1  (.D(Disp_dat13), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:44: Cannot find file containing module: 'DFN1C1'\n    DFN1C1 \\count[0]  (.D(\\count_i[0] ), .CLK(Clk_c), .CLR(Reset_c), \n    ^~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:46: Cannot find file containing module: 'INV'\n    INV \\Sl_pad_RNO[0]  (.A(Disp_dat10), .Y(Disp_dat10_i));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:47: Cannot find file containing module: 'XOR2'\n    XOR2 un3_count_1_SUM1_0 (.A(\\count[1]_net_1 ), .B(\\count[0]_net_1 )\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:49: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Seg_pad[5]/U0/U1  (.D(Disp_dat10), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:51: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Seg_pad[1]/U0/U0  (.D(\\Seg_pad[1]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:53: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Sl_pad[0]/U0/U1  (.D(Disp_dat10_i), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:55: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Seg_pad[6]/U0/U1  (.D(\\count_i[1] ), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:57: Cannot find file containing module: 'OR2A'\n    OR2A \\count_RNIV63F_0[0]  (.A(\\count[1]_net_1 ), .B(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:59: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Seg_pad[4]/U0/U1  (.D(\\count_i[1] ), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:61: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Seg_pad[5]/U0/U0  (.D(\\Seg_pad[5]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:63: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Seg_pad[2]/U0/U1  (.D(Disp_dat11), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:65: Cannot find file containing module: 'INV'\n    INV \\count_RNIGLH7[1]  (.A(\\count[1]_net_1 ), .Y(\\count_i[1] ));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:66: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Seg_pad[6]/U0/U0  (.D(\\Seg_pad[6]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:68: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Sl_pad[2]/U0/U0  (.D(\\Sl_pad[2]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:70: Cannot find file containing module: 'CLKIO'\n    CLKIO \\Clk_pad/U0/U1  (.A(\\Clk_pad/U0/NET1 ), .Y(Clk_c));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:71: Cannot find file containing module: 'OR2B'\n    OR2B \\Sl_pad_RNO[3]  (.A(\\count[1]_net_1 ), .B(\\count[0]_net_1 ), \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:73: Cannot find file containing module: 'IOIN_IB'\n    IOIN_IB \\Reset_pad/U0/U1  (.YIN(\\Reset_pad/U0/NET1 ), .Y(Reset_c));\n    ^~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:74: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Seg_pad[4]/U0/U0  (.D(\\Seg_pad[4]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:76: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Seg_pad[3]/U0/U1  (.D(\\count_i[1] ), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:78: Cannot find file containing module: 'INV'\n    INV \\count_RNO[0]  (.A(\\count[0]_net_1 ), .Y(\\count_i[0] ));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:79: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Seg_pad[2]/U0/U0  (.D(\\Seg_pad[2]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:81: Cannot find file containing module: 'OR2A'\n    OR2A \\count_RNIV63F[0]  (.A(\\count[0]_net_1 ), .B(\\count[1]_net_1 )\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:83: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\Reset_pad/U0/U0  (.PAD(Reset), .Y(\\Reset_pad/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:84: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Sl_pad[1]/U0/U0  (.D(\\Sl_pad[1]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:86: Cannot find file containing module: 'IOPAD_IN'\n    IOPAD_IN \\Clk_pad/U0/U0  (.PAD(Clk), .Y(\\Clk_pad/U0/NET1 ));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:87: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Sl_pad[3]/U0/U0  (.D(\\Sl_pad[3]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:89: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Seg_pad[3]/U0/U0  (.D(\\Seg_pad[3]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:91: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Seg_pad[0]/U0/U1  (.D(Disp_dat12), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:93: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Seg_pad[7]/U0/U1  (.D(GND), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:95: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Sl_pad[2]/U0/U1  (.D(Disp_dat12), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:97: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Sl_pad[0]/U0/U0  (.D(\\Sl_pad[0]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:99: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Seg_pad[0]/U0/U0  (.D(\\Seg_pad[0]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:101: Cannot find file containing module: 'NOR2'\n    NOR2 \\count_RNIV63F_1[0]  (.A(\\count[1]_net_1 ), .B(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:103: Cannot find file containing module: 'IOPAD_TRI'\n    IOPAD_TRI \\Seg_pad[7]/U0/U0  (.D(\\Seg_pad[7]/U0/NET1 ), .E(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:105: Cannot find file containing module: 'IOTRI_OB_EB'\n    IOTRI_OB_EB \\Seg_pad[1]/U0/U1  (.D(VCC), .E(VCC), .DOUT(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:107: Cannot find file containing module: 'GND'\n    GND GND_power_inst1 (.Y(GND_power_net1));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_digi_disp/designer/impl1/dymamic_led_ba.v:108: Cannot find file containing module: 'VCC'\n    VCC VCC_power_inst1 (.Y(VCC_power_net1));\n    ^~~\n%Error: Exiting due to 40 error(s)\n"
module dymamic_led(
       Seg,
       Sl,
       Clk,
       Reset
    );
output [7:0] Seg;
output [3:0] Sl;
input  Clk;
input  Reset;

    wire \count[0]_net_1 , Disp_dat13, Disp_dat10, Disp_dat11, 
        Disp_dat12, SUM1_0, Clk_c, Reset_c, \count[1]_net_1 , 
        \count_i[1] , Disp_dat10_i, \count_i[0] , \Clk_pad/U0/NET1 , 
        \Sl_pad[0]/U0/NET1 , \Sl_pad[0]/U0/NET2 , \Seg_pad[5]/U0/NET1 , 
        \Seg_pad[5]/U0/NET2 , \Sl_pad[1]/U0/NET1 , \Sl_pad[1]/U0/NET2 , 
        \Seg_pad[2]/U0/NET1 , \Seg_pad[2]/U0/NET2 , 
        \Seg_pad[4]/U0/NET1 , \Seg_pad[4]/U0/NET2 , 
        \Seg_pad[3]/U0/NET1 , \Seg_pad[3]/U0/NET2 , 
        \Seg_pad[6]/U0/NET1 , \Seg_pad[6]/U0/NET2 , 
        \Reset_pad/U0/NET1 , \Sl_pad[3]/U0/NET1 , \Sl_pad[3]/U0/NET2 , 
        \Sl_pad[2]/U0/NET1 , \Sl_pad[2]/U0/NET2 , \Seg_pad[1]/U0/NET1 , 
        \Seg_pad[1]/U0/NET2 , \Seg_pad[7]/U0/NET1 , 
        \Seg_pad[7]/U0/NET2 , \Seg_pad[0]/U0/NET1 , 
        \Seg_pad[0]/U0/NET2 , VCC, GND, AFLSDF_VCC, AFLSDF_GND;
    wire GND_power_net1;
    wire VCC_power_net1;
    assign GND = GND_power_net1;
    assign AFLSDF_GND = GND_power_net1;
    assign VCC = VCC_power_net1;
    assign AFLSDF_VCC = VCC_power_net1;
    
    IOTRI_OB_EB \Sl_pad[1]/U0/U1  (.D(Disp_dat11), .E(VCC), .DOUT(
        \Sl_pad[1]/U0/NET1 ), .EOUT(\Sl_pad[1]/U0/NET2 ));
    DFN1C1 \count[1]  (.D(SUM1_0), .CLK(Clk_c), .CLR(Reset_c), .Q(
        \count[1]_net_1 ));
    IOTRI_OB_EB \Sl_pad[3]/U0/U1  (.D(Disp_dat13), .E(VCC), .DOUT(
        \Sl_pad[3]/U0/NET1 ), .EOUT(\Sl_pad[3]/U0/NET2 ));
    DFN1C1 \count[0]  (.D(\count_i[0] ), .CLK(Clk_c), .CLR(Reset_c), 
        .Q(\count[0]_net_1 ));
    INV \Sl_pad_RNO[0]  (.A(Disp_dat10), .Y(Disp_dat10_i));
    XOR2 un3_count_1_SUM1_0 (.A(\count[1]_net_1 ), .B(\count[0]_net_1 )
        , .Y(SUM1_0));
    IOTRI_OB_EB \Seg_pad[5]/U0/U1  (.D(Disp_dat10), .E(VCC), .DOUT(
        \Seg_pad[5]/U0/NET1 ), .EOUT(\Seg_pad[5]/U0/NET2 ));
    IOPAD_TRI \Seg_pad[1]/U0/U0  (.D(\Seg_pad[1]/U0/NET1 ), .E(
        \Seg_pad[1]/U0/NET2 ), .PAD(Seg[1]));
    IOTRI_OB_EB \Sl_pad[0]/U0/U1  (.D(Disp_dat10_i), .E(VCC), .DOUT(
        \Sl_pad[0]/U0/NET1 ), .EOUT(\Sl_pad[0]/U0/NET2 ));
    IOTRI_OB_EB \Seg_pad[6]/U0/U1  (.D(\count_i[1] ), .E(VCC), .DOUT(
        \Seg_pad[6]/U0/NET1 ), .EOUT(\Seg_pad[6]/U0/NET2 ));
    OR2A \count_RNIV63F_0[0]  (.A(\count[1]_net_1 ), .B(
        \count[0]_net_1 ), .Y(Disp_dat12));
    IOTRI_OB_EB \Seg_pad[4]/U0/U1  (.D(\count_i[1] ), .E(VCC), .DOUT(
        \Seg_pad[4]/U0/NET1 ), .EOUT(\Seg_pad[4]/U0/NET2 ));
    IOPAD_TRI \Seg_pad[5]/U0/U0  (.D(\Seg_pad[5]/U0/NET1 ), .E(
        \Seg_pad[5]/U0/NET2 ), .PAD(Seg[5]));
    IOTRI_OB_EB \Seg_pad[2]/U0/U1  (.D(Disp_dat11), .E(VCC), .DOUT(
        \Seg_pad[2]/U0/NET1 ), .EOUT(\Seg_pad[2]/U0/NET2 ));
    INV \count_RNIGLH7[1]  (.A(\count[1]_net_1 ), .Y(\count_i[1] ));
    IOPAD_TRI \Seg_pad[6]/U0/U0  (.D(\Seg_pad[6]/U0/NET1 ), .E(
        \Seg_pad[6]/U0/NET2 ), .PAD(Seg[6]));
    IOPAD_TRI \Sl_pad[2]/U0/U0  (.D(\Sl_pad[2]/U0/NET1 ), .E(
        \Sl_pad[2]/U0/NET2 ), .PAD(Sl[2]));
    CLKIO \Clk_pad/U0/U1  (.A(\Clk_pad/U0/NET1 ), .Y(Clk_c));
    OR2B \Sl_pad_RNO[3]  (.A(\count[1]_net_1 ), .B(\count[0]_net_1 ), 
        .Y(Disp_dat13));
    IOIN_IB \Reset_pad/U0/U1  (.YIN(\Reset_pad/U0/NET1 ), .Y(Reset_c));
    IOPAD_TRI \Seg_pad[4]/U0/U0  (.D(\Seg_pad[4]/U0/NET1 ), .E(
        \Seg_pad[4]/U0/NET2 ), .PAD(Seg[4]));
    IOTRI_OB_EB \Seg_pad[3]/U0/U1  (.D(\count_i[1] ), .E(VCC), .DOUT(
        \Seg_pad[3]/U0/NET1 ), .EOUT(\Seg_pad[3]/U0/NET2 ));
    INV \count_RNO[0]  (.A(\count[0]_net_1 ), .Y(\count_i[0] ));
    IOPAD_TRI \Seg_pad[2]/U0/U0  (.D(\Seg_pad[2]/U0/NET1 ), .E(
        \Seg_pad[2]/U0/NET2 ), .PAD(Seg[2]));
    OR2A \count_RNIV63F[0]  (.A(\count[0]_net_1 ), .B(\count[1]_net_1 )
        , .Y(Disp_dat11));
    IOPAD_IN \Reset_pad/U0/U0  (.PAD(Reset), .Y(\Reset_pad/U0/NET1 ));
    IOPAD_TRI \Sl_pad[1]/U0/U0  (.D(\Sl_pad[1]/U0/NET1 ), .E(
        \Sl_pad[1]/U0/NET2 ), .PAD(Sl[1]));
    IOPAD_IN \Clk_pad/U0/U0  (.PAD(Clk), .Y(\Clk_pad/U0/NET1 ));
    IOPAD_TRI \Sl_pad[3]/U0/U0  (.D(\Sl_pad[3]/U0/NET1 ), .E(
        \Sl_pad[3]/U0/NET2 ), .PAD(Sl[3]));
    IOPAD_TRI \Seg_pad[3]/U0/U0  (.D(\Seg_pad[3]/U0/NET1 ), .E(
        \Seg_pad[3]/U0/NET2 ), .PAD(Seg[3]));
    IOTRI_OB_EB \Seg_pad[0]/U0/U1  (.D(Disp_dat12), .E(VCC), .DOUT(
        \Seg_pad[0]/U0/NET1 ), .EOUT(\Seg_pad[0]/U0/NET2 ));
    IOTRI_OB_EB \Seg_pad[7]/U0/U1  (.D(GND), .E(VCC), .DOUT(
        \Seg_pad[7]/U0/NET1 ), .EOUT(\Seg_pad[7]/U0/NET2 ));
    IOTRI_OB_EB \Sl_pad[2]/U0/U1  (.D(Disp_dat12), .E(VCC), .DOUT(
        \Sl_pad[2]/U0/NET1 ), .EOUT(\Sl_pad[2]/U0/NET2 ));
    IOPAD_TRI \Sl_pad[0]/U0/U0  (.D(\Sl_pad[0]/U0/NET1 ), .E(
        \Sl_pad[0]/U0/NET2 ), .PAD(Sl[0]));
    IOPAD_TRI \Seg_pad[0]/U0/U0  (.D(\Seg_pad[0]/U0/NET1 ), .E(
        \Seg_pad[0]/U0/NET2 ), .PAD(Seg[0]));
    NOR2 \count_RNIV63F_1[0]  (.A(\count[1]_net_1 ), .B(
        \count[0]_net_1 ), .Y(Disp_dat10));
    IOPAD_TRI \Seg_pad[7]/U0/U0  (.D(\Seg_pad[7]/U0/NET1 ), .E(
        \Seg_pad[7]/U0/NET2 ), .PAD(Seg[7]));
    IOTRI_OB_EB \Seg_pad[1]/U0/U1  (.D(VCC), .E(VCC), .DOUT(
        \Seg_pad[1]/U0/NET1 ), .EOUT(\Seg_pad[1]/U0/NET2 ));
    GND GND_power_inst1 (.Y(GND_power_net1));
    VCC VCC_power_inst1 (.Y(VCC_power_net1));
    
endmodule
module dymamic_led(
       Seg,
       Sl,
       Clk,
       Reset
    );

output [7:0] Seg;
output [3:0] Sl;
input  Clk;
input  Reset;

    wire \count[0]_net_1 , Disp_dat13, Disp_dat10, Disp_dat11, 
        Disp_dat12, SUM1_0, Clk_c, Reset_c, \count[1]_net_1 , 
        \count_i[1] , Disp_dat10_i, \count_i[0] , \Clk_pad/U0/NET1 , 
        \Sl_pad[0]/U0/NET1 , \Sl_pad[0]/U0/NET2 , \Seg_pad[5]/U0/NET1 , 
        \Seg_pad[5]/U0/NET2 , \Sl_pad[1]/U0/NET1 , \Sl_pad[1]/U0/NET2 , 
        \Seg_pad[2]/U0/NET1 , \Seg_pad[2]/U0/NET2 , 
        \Seg_pad[4]/U0/NET1 , \Seg_pad[4]/U0/NET2 , 
        \Seg_pad[3]/U0/NET1 , \Seg_pad[3]/U0/NET2 , 
        \Seg_pad[6]/U0/NET1 , \Seg_pad[6]/U0/NET2 , 
        \Reset_pad/U0/NET1 , \Sl_pad[3]/U0/NET1 , \Sl_pad[3]/U0/NET2 , 
        \Sl_pad[2]/U0/NET1 , \Sl_pad[2]/U0/NET2 , \Seg_pad[1]/U0/NET1 , 
        \Seg_pad[1]/U0/NET2 , \Seg_pad[7]/U0/NET1 , 
        \Seg_pad[7]/U0/NET2 , \Seg_pad[0]/U0/NET1 , 
        \Seg_pad[0]/U0/NET2 , VCC, GND, AFLSDF_VCC, AFLSDF_GND;
    wire GND_power_net1;
    wire VCC_power_net1;
    assign GND = GND_power_net1;
    assign AFLSDF_GND = GND_power_net1;
    assign VCC = VCC_power_net1;
    assign AFLSDF_VCC = VCC_power_net1;
    
    IOTRI_OB_EB \Sl_pad[1]/U0/U1  (.D(Disp_dat11), .E(VCC), .DOUT(
        \Sl_pad[1]/U0/NET1 ), .EOUT(\Sl_pad[1]/U0/NET2 ));
    DFN1C1 \count[1]  (.D(SUM1_0), .CLK(Clk_c), .CLR(Reset_c), .Q(
        \count[1]_net_1 ));
    IOTRI_OB_EB \Sl_pad[3]/U0/U1  (.D(Disp_dat13), .E(VCC), .DOUT(
        \Sl_pad[3]/U0/NET1 ), .EOUT(\Sl_pad[3]/U0/NET2 ));
    DFN1C1 \count[0]  (.D(\count_i[0] ), .CLK(Clk_c), .CLR(Reset_c), 
        .Q(\count[0]_net_1 ));
    INV \Sl_pad_RNO[0]  (.A(Disp_dat10), .Y(Disp_dat10_i));
    XOR2 un3_count_1_SUM1_0 (.A(\count[1]_net_1 ), .B(\count[0]_net_1 )
        , .Y(SUM1_0));
    IOTRI_OB_EB \Seg_pad[5]/U0/U1  (.D(Disp_dat10), .E(VCC), .DOUT(
        \Seg_pad[5]/U0/NET1 ), .EOUT(\Seg_pad[5]/U0/NET2 ));
    IOPAD_TRI \Seg_pad[1]/U0/U0  (.D(\Seg_pad[1]/U0/NET1 ), .E(
        \Seg_pad[1]/U0/NET2 ), .PAD(Seg[1]));
    IOTRI_OB_EB \Sl_pad[0]/U0/U1  (.D(Disp_dat10_i), .E(VCC), .DOUT(
        \Sl_pad[0]/U0/NET1 ), .EOUT(\Sl_pad[0]/U0/NET2 ));
    IOTRI_OB_EB \Seg_pad[6]/U0/U1  (.D(\count_i[1] ), .E(VCC), .DOUT(
        \Seg_pad[6]/U0/NET1 ), .EOUT(\Seg_pad[6]/U0/NET2 ));
    OR2A \count_RNIV63F_0[0]  (.A(\count[1]_net_1 ), .B(
        \count[0]_net_1 ), .Y(Disp_dat12));
    IOTRI_OB_EB \Seg_pad[4]/U0/U1  (.D(\count_i[1] ), .E(VCC), .DOUT(
        \Seg_pad[4]/U0/NET1 ), .EOUT(\Seg_pad[4]/U0/NET2 ));
    IOPAD_TRI \Seg_pad[5]/U0/U0  (.D(\Seg_pad[5]/U0/NET1 ), .E(
        \Seg_pad[5]/U0/NET2 ), .PAD(Seg[5]));
    IOTRI_OB_EB \Seg_pad[2]/U0/U1  (.D(Disp_dat11), .E(VCC), .DOUT(
        \Seg_pad[2]/U0/NET1 ), .EOUT(\Seg_pad[2]/U0/NET2 ));
    INV \count_RNIGLH7[1]  (.A(\count[1]_net_1 ), .Y(\count_i[1] ));
    IOPAD_TRI \Seg_pad[6]/U0/U0  (.D(\Seg_pad[6]/U0/NET1 ), .E(
        \Seg_pad[6]/U0/NET2 ), .PAD(Seg[6]));
    IOPAD_TRI \Sl_pad[2]/U0/U0  (.D(\Sl_pad[2]/U0/NET1 ), .E(
        \Sl_pad[2]/U0/NET2 ), .PAD(Sl[2]));
    CLKIO \Clk_pad/U0/U1  (.A(\Clk_pad/U0/NET1 ), .Y(Clk_c));
    OR2B \Sl_pad_RNO[3]  (.A(\count[1]_net_1 ), .B(\count[0]_net_1 ), 
        .Y(Disp_dat13));
    IOIN_IB \Reset_pad/U0/U1  (.YIN(\Reset_pad/U0/NET1 ), .Y(Reset_c));
    IOPAD_TRI \Seg_pad[4]/U0/U0  (.D(\Seg_pad[4]/U0/NET1 ), .E(
        \Seg_pad[4]/U0/NET2 ), .PAD(Seg[4]));
    IOTRI_OB_EB \Seg_pad[3]/U0/U1  (.D(\count_i[1] ), .E(VCC), .DOUT(
        \Seg_pad[3]/U0/NET1 ), .EOUT(\Seg_pad[3]/U0/NET2 ));
    INV \count_RNO[0]  (.A(\count[0]_net_1 ), .Y(\count_i[0] ));
    IOPAD_TRI \Seg_pad[2]/U0/U0  (.D(\Seg_pad[2]/U0/NET1 ), .E(
        \Seg_pad[2]/U0/NET2 ), .PAD(Seg[2]));
    OR2A \count_RNIV63F[0]  (.A(\count[0]_net_1 ), .B(\count[1]_net_1 )
        , .Y(Disp_dat11));
    IOPAD_IN \Reset_pad/U0/U0  (.PAD(Reset), .Y(\Reset_pad/U0/NET1 ));
    IOPAD_TRI \Sl_pad[1]/U0/U0  (.D(\Sl_pad[1]/U0/NET1 ), .E(
        \Sl_pad[1]/U0/NET2 ), .PAD(Sl[1]));
    IOPAD_IN \Clk_pad/U0/U0  (.PAD(Clk), .Y(\Clk_pad/U0/NET1 ));
    IOPAD_TRI \Sl_pad[3]/U0/U0  (.D(\Sl_pad[3]/U0/NET1 ), .E(
        \Sl_pad[3]/U0/NET2 ), .PAD(Sl[3]));
    IOPAD_TRI \Seg_pad[3]/U0/U0  (.D(\Seg_pad[3]/U0/NET1 ), .E(
        \Seg_pad[3]/U0/NET2 ), .PAD(Seg[3]));
    IOTRI_OB_EB \Seg_pad[0]/U0/U1  (.D(Disp_dat12), .E(VCC), .DOUT(
        \Seg_pad[0]/U0/NET1 ), .EOUT(\Seg_pad[0]/U0/NET2 ));
    IOTRI_OB_EB \Seg_pad[7]/U0/U1  (.D(GND), .E(VCC), .DOUT(
        \Seg_pad[7]/U0/NET1 ), .EOUT(\Seg_pad[7]/U0/NET2 ));
    IOTRI_OB_EB \Sl_pad[2]/U0/U1  (.D(Disp_dat12), .E(VCC), .DOUT(
        \Sl_pad[2]/U0/NET1 ), .EOUT(\Sl_pad[2]/U0/NET2 ));
    IOPAD_TRI \Sl_pad[0]/U0/U0  (.D(\Sl_pad[0]/U0/NET1 ), .E(
        \Sl_pad[0]/U0/NET2 ), .PAD(Sl[0]));
    IOPAD_TRI \Seg_pad[0]/U0/U0  (.D(\Seg_pad[0]/U0/NET1 ), .E(
        \Seg_pad[0]/U0/NET2 ), .PAD(Seg[0]));
    NOR2 \count_RNIV63F_1[0]  (.A(\count[1]_net_1 ), .B(
        \count[0]_net_1 ), .Y(Disp_dat10));
    IOPAD_TRI \Seg_pad[7]/U0/U0  (.D(\Seg_pad[7]/U0/NET1 ), .E(
        \Seg_pad[7]/U0/NET2 ), .PAD(Seg[7]));
    IOTRI_OB_EB \Seg_pad[1]/U0/U1  (.D(VCC), .E(VCC), .DOUT(
        \Seg_pad[1]/U0/NET1 ), .EOUT(\Seg_pad[1]/U0/NET2 ));
    GND GND_power_inst1 (.Y(GND_power_net1));
    VCC VCC_power_inst1 (.Y(VCC_power_net1));
    
endmodule