data/full_repos/permissive/214823094/lab_5/project_4/project_4.srcs/sources_1/new/Shift_register.v
1: b"%Error: data/full_repos/permissive/214823094/lab_5/project_4/project_4.srcs/sources_1/new/Shift_register.v:32: Cannot find file containing module: 'clkdiv'\n    clkdiv c1(clk,myclk);\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214823094/lab_5/project_4/project_4.srcs/sources_1/new,data/full_repos/permissive/214823094/clkdiv\n             data/full_repos/permissive/214823094/lab_5/project_4/project_4.srcs/sources_1/new,data/full_repos/permissive/214823094/clkdiv.v\n             data/full_repos/permissive/214823094/lab_5/project_4/project_4.srcs/sources_1/new,data/full_repos/permissive/214823094/clkdiv.sv\n             clkdiv\n             clkdiv.v\n             clkdiv.sv\n             obj_dir/clkdiv\n             obj_dir/clkdiv.v\n             obj_dir/clkdiv.sv\n%Error: Exiting due to 1 error(s)\n"
module Shift_register(
    input clk,
    input reset,
    input [1:0] d,
    input [1:0] a,
    input [3:0] data,
    output reg [3:0] q
    );
    wire myclk;
    clkdiv c1(clk,myclk);
    always@(posedge myclk,posedge reset)
    begin
        if(~reset)
            q[3:0]=4'b0000;
        else
            case(a)
            2'b00:q[3:0]=q[3:0];
            2'b01:q[3:0]={d[1],q[3:1]};
            2'b10:q[3:0]={q[2:0],d[0]};
            2'b11:q[3:0]=data[3:0];
            endcase
    end
    
endmodule
module Shift_register(
    input clk,
    input reset,
    input [1:0] d,
    input [1:0] a,
    input [3:0] data,
    output reg [3:0] q
    );

    wire myclk;
    clkdiv c1(clk,myclk);
    always@(posedge myclk,posedge reset)
    begin
        if(~reset)
            q[3:0]=4'b0000;
        else
            case(a)
            2'b00:q[3:0]=q[3:0];
            2'b01:q[3:0]={d[1],q[3:1]};
            2'b10:q[3:0]={q[2:0],d[0]};
            2'b11:q[3:0]=data[3:0];
            endcase
    end
    
endmodule