data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/008_pipelined/isqrt.v
1: b'%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/008_pipelined/isqrt.v:38: Cannot find file containing module: \'isqrt_slice_reg\'\n                isqrt_slice_reg #(.m (m >> i * 2)) inst\n                ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/008_pipelined,data/full_repos/permissive/110151336/isqrt_slice_reg\n             data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/008_pipelined,data/full_repos/permissive/110151336/isqrt_slice_reg.v\n             data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/008_pipelined,data/full_repos/permissive/110151336/isqrt_slice_reg.sv\n             isqrt_slice_reg\n             isqrt_slice_reg.v\n             isqrt_slice_reg.sv\n             obj_dir/isqrt_slice_reg\n             obj_dir/isqrt_slice_reg.v\n             obj_dir/isqrt_slice_reg.sv\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/008_pipelined/isqrt.v:62: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                                                                                : ... In instance isqrt\n    assign y = oy [15];\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module isqrt
(
    input         clock,
    input         reset_n,
    input  [31:0] x,
    output [15:0] y
);

    parameter n_pipe_stages = 16;

    localparam n_slices           = 16;
    localparam n_slices_per_stage = n_slices / n_pipe_stages;

    localparam [31:0] m = 32'h4000_0000;

    wire [31:0] ix [0:15], iy [0:15];
    wire [31:0] ox [0:15], oy [0:15];

    generate
        genvar i;

        for (i = 0; i < 16; i = i + 1)
        begin : u
            if (i % n_slices_per_stage != n_slices_per_stage - 1)
            begin
                isqrt_slice_comb #(.m (m >> i * 2)) inst
                (
                    .ix      ( ix [i]  ),
                    .iy      ( iy [i]  ),
                    .ox      ( ox [i]  ),
                    .oy      ( oy [i]  )
                );
            end
            else
            begin
                isqrt_slice_reg #(.m (m >> i * 2)) inst
                (
                    .clock   ( clock   ),
                    .reset_n ( reset_n ),
                    .ix      ( ix [i]  ),
                    .iy      ( iy [i]  ),
                    .ox      ( ox [i]  ),
                    .oy      ( oy [i]  )
                );
            end
        end

        for (i = 1; i < 16; i = i + 1)
        begin : v
            assign ix [i] = ox [i - 1];
            assign iy [i] = oy [i - 1];
        end

    endgenerate


    assign ix [0] = x;
    assign iy [0] = 0;

    assign y = oy [15];

endmodule
module isqrt
(
    input         clock,
    input         reset_n,
    input  [31:0] x,
    output [15:0] y
);


    parameter n_pipe_stages = 16;

    localparam n_slices           = 16;
    localparam n_slices_per_stage = n_slices / n_pipe_stages;

    localparam [31:0] m = 32'h4000_0000;

    wire [31:0] ix [0:15], iy [0:15];
    wire [31:0] ox [0:15], oy [0:15];

    generate
        genvar i;

        for (i = 0; i < 16; i = i + 1)
        begin : u
            if (i % n_slices_per_stage != n_slices_per_stage - 1)
            begin
                isqrt_slice_comb #(.m (m >> i * 2)) inst
                (
                    .ix      ( ix [i]  ),
                    .iy      ( iy [i]  ),
                    .ox      ( ox [i]  ),
                    .oy      ( oy [i]  )
                );
            end
            else
            begin
                isqrt_slice_reg #(.m (m >> i * 2)) inst
                (
                    .clock   ( clock   ),
                    .reset_n ( reset_n ),
                    .ix      ( ix [i]  ),
                    .iy      ( iy [i]  ),
                    .ox      ( ox [i]  ),
                    .oy      ( oy [i]  )
                );
            end
        end

        for (i = 1; i < 16; i = i + 1)
        begin : v
            assign ix [i] = ox [i - 1];
            assign iy [i] = oy [i - 1];
        end

    endgenerate


    assign ix [0] = x;
    assign iy [0] = 0;

    assign y = oy [15];

endmodule