data/full_repos/permissive/144785545/dataselector.v
data/verilator_xmls/91523d48-af54-49d2-90aa-2df8f45d30cc.xml
module DATASELECTOR(
		input CLK,
		input [3:0] C0,
		input [3:0] C1,
		input [3:0] C2,
		output reg [3:0] OUT,
		input SELA,
		input SELB
);

wire [1:0] select;
assign select = {SELA,SELB};


always @( posedge CLK ) begin
		case ( select )
			2'h0:		OUT <= C0;
			2'h1:		OUT <= C1;
			2'h2:		OUT <= C2;
			2'h3:		OUT <= 4'h0;
		endcase
end

endmodule
module DATASELECTOR(
		input CLK,
		input [3:0] C0,
		input [3:0] C1,
		input [3:0] C2,
		output reg [3:0] OUT,
		input SELA,
		input SELB
);


wire [1:0] select;
assign select = {SELA,SELB};


always @( posedge CLK ) begin
		case ( select )
			2'h0:		OUT <= C0;
			2'h1:		OUT <= C1;
			2'h2:		OUT <= C2;
			2'h3:		OUT <= 4'h0;
		endcase
end

endmodule