data/full_repos/permissive/108410192/src/RAM.v
 line:17: before: ":"
1: b"%Error: data/full_repos/permissive/108410192/src/RAM.v:18: syntax error, unexpected if\n        if (cs && we)\n        ^~\n%Error: data/full_repos/permissive/108410192/src/RAM.v:69: syntax error, unexpected ';', expecting ')' or ','\n        input clk;\n                 ^\n%Error: data/full_repos/permissive/108410192/src/RAM.v:79: syntax error, unexpected always\n    always @(posedge clk) begin : MEM_WRITE\n    ^~~~~~\n%Error: data/full_repos/permissive/108410192/src/RAM.v:89: syntax error, unexpected assign\n    assign dout0 = (cs0 && oe0 && ~we) ? data0 : 8'bz;\n    ^~~~~~\n%Error: Exiting due to 4 error(s)\n"
module RAM_sync #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 8)
       (output [DATA_WIDTH-1:0] data_out,
        input [ADDR_WIDTH-1:0] address,
        input [DATA_WIDTH-1:0] data_in,
        input clk, cs, we, oe);


    parameter RAM_DEPTH = 1 << ADDR_WIDTH;

    reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
    reg [DATA_WIDTH-1:0] data;
    

    assign data_out = (cs && ~we && oe) ? data : 8'bz;
    

    always @(posedge clk) bgein : MEM_WRITE
        if (cs && we)
            mem[address] <= data_in;
    end
    

    always @(posedge clk) bgein : MEM_READ
        if (cs && ~we && oe)
            data <= mem[address];
    end

endmodule
module RAM_sync #(parameter DATA_WIDTH = 8, ADDR_WIDTH = 8)
       (output [DATA_WIDTH-1:0] data_out,
        input [ADDR_WIDTH-1:0] address,
        input [DATA_WIDTH-1:0] data_in,
        input clk, cs, we, oe);



    parameter RAM_DEPTH = 1 << ADDR_WIDTH;

    reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
    reg [DATA_WIDTH-1:0] data;
    

    assign data_out = (cs && ~we && oe) ? data : 8'bz;
    

    always @(posedge clk) bgein : MEM_WRITE
        if (cs && we)
            mem[address] <= data_in;
    end
    

    always @(posedge clk) bgein : MEM_READ
        if (cs && ~we && oe)
            data <= mem[address];
    end

endmodule