data/full_repos/permissive/143278/ivltests/deposit.v
 line:111: before: "1"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/deposit.v:69: Unsupported: Ignoring delay on this delayed statement.\n #5 ck <= 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/deposit.v:70: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/deposit.v:74: Unsupported: Ignoring delay on this delayed statement.\n #1 ck <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/deposit.v:81: Unsupported: Ignoring delay on this delayed statement.\n #22;\n ^\n%Error: data/full_repos/permissive/143278/ivltests/deposit.v:85: Unsupported or unknown PLI call: $deposit\n $deposit(C0.Q, 1\'b0);\n ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/deposit.v:86: Unsupported or unknown PLI call: $deposit\n $deposit(C1.Q, 1\'b1);\n ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/deposit.v:87: Unsupported or unknown PLI call: $deposit\n $deposit(C2.Q, 1\'b0);\n ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/deposit.v:88: Unsupported or unknown PLI call: $deposit\n $deposit(C3.Q, 1\'b1);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/deposit.v:90: Unsupported: Ignoring delay on this delayed statement.\n #1 if (cnt !== 4\'b1010)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/deposit.v:92: Unsupported: Ignoring delay on this delayed statement.\n #99;\n ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module deposit_test;

   reg ck;

   reg start;
   initial start = 0;

`ifdef RTL

   reg [3:0] cnt;
   wire      cnt_tc = &cnt;

   always @(posedge ck)
     if (start | ~cnt_tc)
       cnt <= cnt + 1;

`else

   wire [3:0] cnt;
   wire [3:0] cnt_1;
   wire [3:0] cnt_c;
   wire       cnt_tc;
   wire       ne, e;

   and (cnt_tc, cnt[0], cnt[1], cnt[2], cnt[3]);
   not (ne, cnt_tc);
   or (e, ne, start);

   had A0 (cnt[0],     1'b1,  cnt_c[0], cnt_1[0]);
   had A1 (cnt[1], cnt_c[0],  cnt_c[1], cnt_1[1]);
   had A2 (cnt[2], cnt_c[1],  cnt_c[2], cnt_1[2]);
   had A3 (cnt[3], cnt_c[2],  cnt_c[3], cnt_1[3]);

   dffe C0 (ck, e, cnt_1[0], cnt[0]);
   dffe C1 (ck, e, cnt_1[1], cnt[1]);
   dffe C2 (ck, e, cnt_1[2], cnt[2]);
   dffe C3 (ck, e, cnt_1[3], cnt[3]);

`endif

   integer    r0; initial r0 = 0;
   integer    r1; initial r1 = 0;

   always
     begin
	#5 ck <= 0;
	#4;
	$display("%b %b %d %d", cnt, cnt_tc, r0, r1);
	if (cnt_tc === 1'b0) r0 = r0 + 1;
	if (cnt_tc === 1'b1) r1 = r1 + 1;
	#1 ck <= 1;
     end

   initial
     begin


	#22;
`ifdef RTL
	cnt <= 4'b 1010;
`else
	$deposit(C0.Q, 1'b0);
	$deposit(C1.Q, 1'b1);
	$deposit(C2.Q, 1'b0);
	$deposit(C3.Q, 1'b1);
`endif
	#1 if (cnt !== 4'b1010)
	  $display("FAILED");
	#99;
	$display("%d/%d", r0, r1);
	if (r0===5 && r1===5)
	  $display("PASSED");
	else
	  $display("FAILED");
	$finish;
     end

endmodule
module deposit_test;


   reg ck;

   reg start;
   initial start = 0;

`ifdef RTL

   reg [3:0] cnt;
   wire      cnt_tc = &cnt;

   always @(posedge ck)
     if (start | ~cnt_tc)
       cnt <= cnt + 1;

`else

   wire [3:0] cnt;
   wire [3:0] cnt_1;
   wire [3:0] cnt_c;
   wire       cnt_tc;
   wire       ne, e;

   and (cnt_tc, cnt[0], cnt[1], cnt[2], cnt[3]);
   not (ne, cnt_tc);
   or (e, ne, start);

   had A0 (cnt[0],     1'b1,  cnt_c[0], cnt_1[0]);
   had A1 (cnt[1], cnt_c[0],  cnt_c[1], cnt_1[1]);
   had A2 (cnt[2], cnt_c[1],  cnt_c[2], cnt_1[2]);
   had A3 (cnt[3], cnt_c[2],  cnt_c[3], cnt_1[3]);

   dffe C0 (ck, e, cnt_1[0], cnt[0]);
   dffe C1 (ck, e, cnt_1[1], cnt[1]);
   dffe C2 (ck, e, cnt_1[2], cnt[2]);
   dffe C3 (ck, e, cnt_1[3], cnt[3]);

`endif

   integer    r0; initial r0 = 0;
   integer    r1; initial r1 = 0;

   always
     begin
	#5 ck <= 0;
	#4;
	$display("%b %b %d %d", cnt, cnt_tc, r0, r1);
	if (cnt_tc === 1'b0) r0 = r0 + 1;
	if (cnt_tc === 1'b1) r1 = r1 + 1;
	#1 ck <= 1;
     end

   initial
     begin


	#22;
`ifdef RTL
	cnt <= 4'b 1010;
`else
	$deposit(C0.Q, 1'b0);
	$deposit(C1.Q, 1'b1);
	$deposit(C2.Q, 1'b0);
	$deposit(C3.Q, 1'b1);
`endif
	#1 if (cnt !== 4'b1010)
	  $display("FAILED");
	#99;
	$display("%d/%d", r0, r1);
	if (r0===5 && r1===5)
	  $display("PASSED");
	else
	  $display("FAILED");
	$finish;
     end

endmodule