data/full_repos/permissive/143278/ivltests/schedule.v
 line:33: before: "wait"
1: b'%Error: data/full_repos/permissive/143278/ivltests/schedule.v:33: Unsupported: wait statements\n   always #1 wait (test) begin\n             ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/schedule.v:33: Unsupported: Ignoring delay on this delayed statement.\n   always #1 wait (test) begin\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/schedule.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/schedule.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #10 a = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/schedule.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #10 $display("PASSED");\n      ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg a;

   wire test = a == 1'b1;

   always #1 wait (test) begin
      if (a !== 1'b1) begin
	 $display("FAILED -- a == %b, test == %b", a, test);
	 $finish;
      end

      a = 1'b0;
   end

   initial begin
      a = 0;

      #10 a = 1;
      #10 a = 0;
      #10 $display("PASSED");
   end
endmodule
module main;


   reg a;

   wire test = a == 1'b1;

   always #1 wait (test) begin
      if (a !== 1'b1) begin
	 $display("FAILED -- a == %b, test == %b", a, test);
	 $finish;
      end

      a = 1'b0;
   end

   initial begin
      a = 0;

      #10 a = 1;
      #10 a = 0;
      #10 $display("PASSED");
   end
endmodule