data/full_repos/permissive/158922207/Verilog Design/modules/PipeCPU.v
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/PipeCPU.v\n%Error: Exiting due to 3 error(s)\n'
module PipeCPU (clock,reset,pcOut,aluResult,inst,r8,r9,r10,r11,r12,r13,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,r25);
input clock, reset;
output [31:0] pcOut, aluResult, inst;
output [31:0] r8,r9,r10,r11,r12,r13,r14,r15,r16,r17,
r18,r19,r20,r21,r22,r23,r24,r25;

wire [31:0] pc, ID_pc4, ID_instr, EX_pc4,WB_pc4, EX_rs, EX_rt, EX_immExt, EX_instr,MEM_pc4,
FBout, MEM_ALUResult, MEM_FBout, WB_ALUResult,WB_DMOut, Instr,RSout,RTout,WB_RDdata, SEOut,SL2Out,ALUResult, ALU_B, ALU_A, MEM_DMOut, MEM_FAout,jumpAddress,jShift;
wire signed[31:0] pcNext, pc4,BranchAddr;
wire EX_RegWrite,IF_ID_flush, PCWrite,IF_ID_WriteEn, WB_RegWrite,RegWrite, Jump, BranchType,
Branch, MemRead, MemWrite, ALUSrc, PCorBranch, Zero, jr, EX_MemWrite, EX_MemRead,EX_ALUSrc, MEM_RegWrite, MEM_MemWrite, MEM_MemRead,btypeOut,
stall_flush, Muxed_Jump,Muxed_BranchType, Muxed_Branch, Muxed_MemRead,  Muxed_MemWrite, Muxed_ALUSrc, Muxed_RegWrite,Muxed_jr;
wire [4:0] WB_WriteRegister,MEM_WriteRegister, RSin, RTin, EX_WriteRegister;
wire [3:0] ALUIn, EX_ALUIn;
wire [1:0] ALUOp, EX_ALUOp, ForwardA_EX, ForwardB_EX,  ForwardA_ID,ForwardB_ID, Muxed_ALUOp, RegDest,EX_RegDest,Muxed_RegDest,MemtoReg,
EX_MemtoReg,MEM_MemtoReg,Muxed_MemtoReg,WB_MemtoReg;
wire [31:0] dummy31,ZeroTestB,ZeroTestA,MEM_RDdata,RSFlushedOut,RTFlushedOut;
wire dummy1,ID_flush,Flush;



simplereg PCReg (pc, pcNext, PCWrite, reset, clock);


assign pc4 = pc + 32'd4;


IM instructionMemory (Instr, pc);



assign IF_ID_flush = (Muxed_jr || PCorBranch || Muxed_Jump);
assign Flush = ID_flush || reset;

simplereg IF_ID_pc4(ID_pc4, pc4, IF_ID_WriteEn, Flush, clock);
simplereg IF_ID_Instr(ID_instr, Instr, IF_ID_WriteEn, Flush, clock);
simplereg #(1) IF_ID_flushReg(ID_flush, IF_ID_flush, IF_ID_WriteEn, Flush, clock);



ShiftLeft SL1 (jShift, {{6{ID_instr[25]}},ID_instr[25:0]});


assign jumpAddress = {ID_pc4[31:28],jShift};


Control ControlUnit (RegDest, Jump,BranchType, Branch, MemRead,MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, ID_instr[31:26], reset);


ForwardingUnit_ID FU_ID(ForwardA_ID, ForwardB_ID, Branch, MEM_RegWrite, RSin, RTin, MEM_WriteRegister,EX_WriteRegister, EX_RegWrite);


Mux3_1  BranchCompSrcA (ForwardA_ID, RSout, ALUResult ,MEM_RDdata, ZeroTestA);
Mux3_1  BranchCompSrcB (ForwardB_ID, RTout, ALUResult ,MEM_RDdata, ZeroTestB);


assign RSin = ID_instr[25:21];
assign RTin = ID_instr[20:16];


Register Rfile(RSout,RTout, WB_RDdata, RSin, RTin, WB_WriteRegister, WB_RegWrite, clock,reset,
  r8,r9,r10,r11,r12,r13,r14,r15,r16,r17,
r18,r19,r20,r21,r22,r23,r24,r25);


SignExt SE (SEOut, ID_instr[15:0]);


ALU ZeroTest (dummy31, Zero, ALUIn, ZeroTestA, ZeroTestB);


JRControl jrControl (jr, ALUOp, ID_instr[5:0]);


ALUControl ALUCUnit (ALUIn,ALUOp, ID_instr[5:0]);


Mux2_1 #(14) Nop_Control (stall_flush, {RegDest, Jump,BranchType, Branch, MemRead,MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite,jr}, 14'd0,
{Muxed_RegDest, Muxed_Jump,Muxed_BranchType,
Muxed_Branch, Muxed_MemRead,Muxed_MemtoReg,Muxed_ALUOp , Muxed_MemWrite, Muxed_ALUSrc, Muxed_RegWrite,Muxed_jr});


simplereg ID_EX_pc4(EX_pc4, ID_pc4, 1'b1, reset, clock);
simplereg ID_EX_rs(EX_rs, RSFlushedOut, 1'b1, reset, clock);
simplereg ID_EX_rt(EX_rt, RTFlushedOut, 1'b1, reset, clock);
simplereg #(4)ID_EX_ALUIn(EX_ALUIn, ALUIn, 1'b1, reset, clock);
simplereg ID_EX_immExt(EX_immExt, SEOut, 1'b1, reset, clock);
simplereg ID_EX_instr(EX_instr, ID_instr, 1'b1, reset, clock);
WBControlReg ID_EX_wb (EX_MemtoReg, EX_RegWrite, Muxed_MemtoReg, Muxed_RegWrite, 1'b1, reset, clock);
MEMControlReg ID_EX_mem (EX_MemWrite, EX_MemRead, Muxed_MemWrite, Muxed_MemRead, 1'b1, reset, clock);
EXControlReg ID_EX_ex (EX_ALUSrc, EX_RegDest, EX_ALUOp, Muxed_ALUSrc, Muxed_RegDest, Muxed_ALUOp, 1'b1, reset, clock);




Mux3_1 #(5) Rdest (EX_RegDest,EX_instr[20:16],EX_instr[15:11],5'd31,EX_WriteRegister);


ForwardingUnit_EX FU_EX (ForwardA_EX, ForwardB_EX,EX_instr[25:21], EX_instr[20:16], MEM_WriteRegister, WB_WriteRegister, MEM_RegWrite, WB_RegWrite);


Mux3_1 ALUsrcA (ForwardA_EX,EX_rs,WB_RDdata, MEM_ALUResult, ALU_A);
Mux3_1 FBSource (ForwardB_EX,EX_rt,WB_RDdata, MEM_ALUResult, FBout);


Mux2_1 ALUSrcB (EX_ALUSrc,FBout,EX_immExt,ALU_B);

ALU MainALU (ALUResult, dummy1, EX_ALUIn, ALU_A, ALU_B);


ShiftLeft SL2 (SL2Out, SEOut);


assign BranchAddr = ID_pc4 + SL2Out;




simplereg EX_MEM_pc4(MEM_pc4, EX_pc4, 1'b1, reset, clock);
simplereg EX_MEM_ALUResult(MEM_ALUResult, ALUResult, 1'b1, reset, clock);
simplereg EX_MEM_ALUb(MEM_FBout, FBout, 1'b1, reset, clock);
simplereg EX_MEM_ALUa(MEM_FAout, ALU_A, 1'b1, reset, clock);
simplereg #(5) EX_MEM_WriteRegister(MEM_WriteRegister, EX_WriteRegister, 1'b1, reset, clock);
WBControlReg EX_MEM_wb (MEM_MemtoReg, MEM_RegWrite, EX_MemtoReg, EX_RegWrite, 1'b1, reset, clock);
MEMControlReg EX_MEM_mem (MEM_MemWrite, MEM_MemRead,EX_MemWrite, EX_MemRead, 1'b1, reset, clock);





Memory DM(MEM_DMOut, MEM_FBout, MEM_ALUResult, MEM_MemWrite, MEM_MemRead,clock, reset);



simplereg MEM_WB_ALUResult(WB_ALUResult, MEM_ALUResult, 1'b1, reset, clock);
simplereg MEM_WB_pc4(WB_pc4, MEM_pc4, 1'b1, reset, clock);
simplereg MEM_WB_DMOut(WB_DMOut, MEM_DMOut, 1'b1, reset, clock);
simplereg #(5) MEM_WB_WriteRegister(WB_WriteRegister, MEM_WriteRegister, 1'b1, reset, clock);
WBControlReg MEM_WB_wb (WB_MemtoReg, WB_RegWrite, MEM_MemtoReg, MEM_RegWrite, 1'b1, reset, clock);






Mux3_1 WBMtoR (WB_MemtoReg,WB_ALUResult,WB_DMOut,WB_pc4,WB_RDdata);
Mux3_1 MEMMtoR (MEM_MemtoReg,MEM_ALUResult,MEM_DMOut,MEM_pc4,MEM_RDdata);





HazardDetUnit1 HDU1 (PCWrite, IF_ID_WriteEn, stall_flush, ID_instr, EX_MemRead, EX_instr[20:16]);


HazardDetUnit2 HDU2 (WB_RegWrite, RSin, RTin, WB_WriteRegister, RSout,RTout, WB_RDdata, RSFlushedOut,RTFlushedOut);

Mux2_1 #(1) BeqOrBne (Muxed_BranchType, Zero, ~Zero, btypeOut);


and (PCorBranch, Muxed_Branch, btypeOut);



PCSrc_Mux PCSrc (pcNext, pc4,BranchAddr,jumpAddress, RSout,PCorBranch,Jump,jr);

assign pcOut = pc ;
assign aluResult = MEM_ALUResult;

assign inst = Instr;
endmodule
module PipeCPU (clock,reset,pcOut,aluResult,inst,r8,r9,r10,r11,r12,r13,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,r25);

input clock, reset;
output [31:0] pcOut, aluResult, inst;
output [31:0] r8,r9,r10,r11,r12,r13,r14,r15,r16,r17,
r18,r19,r20,r21,r22,r23,r24,r25;

wire [31:0] pc, ID_pc4, ID_instr, EX_pc4,WB_pc4, EX_rs, EX_rt, EX_immExt, EX_instr,MEM_pc4,
FBout, MEM_ALUResult, MEM_FBout, WB_ALUResult,WB_DMOut, Instr,RSout,RTout,WB_RDdata, SEOut,SL2Out,ALUResult, ALU_B, ALU_A, MEM_DMOut, MEM_FAout,jumpAddress,jShift;
wire signed[31:0] pcNext, pc4,BranchAddr;
wire EX_RegWrite,IF_ID_flush, PCWrite,IF_ID_WriteEn, WB_RegWrite,RegWrite, Jump, BranchType,
Branch, MemRead, MemWrite, ALUSrc, PCorBranch, Zero, jr, EX_MemWrite, EX_MemRead,EX_ALUSrc, MEM_RegWrite, MEM_MemWrite, MEM_MemRead,btypeOut,
stall_flush, Muxed_Jump,Muxed_BranchType, Muxed_Branch, Muxed_MemRead,  Muxed_MemWrite, Muxed_ALUSrc, Muxed_RegWrite,Muxed_jr;
wire [4:0] WB_WriteRegister,MEM_WriteRegister, RSin, RTin, EX_WriteRegister;
wire [3:0] ALUIn, EX_ALUIn;
wire [1:0] ALUOp, EX_ALUOp, ForwardA_EX, ForwardB_EX,  ForwardA_ID,ForwardB_ID, Muxed_ALUOp, RegDest,EX_RegDest,Muxed_RegDest,MemtoReg,
EX_MemtoReg,MEM_MemtoReg,Muxed_MemtoReg,WB_MemtoReg;
wire [31:0] dummy31,ZeroTestB,ZeroTestA,MEM_RDdata,RSFlushedOut,RTFlushedOut;
wire dummy1,ID_flush,Flush;



simplereg PCReg (pc, pcNext, PCWrite, reset, clock);


assign pc4 = pc + 32'd4;


IM instructionMemory (Instr, pc);



assign IF_ID_flush = (Muxed_jr || PCorBranch || Muxed_Jump);
assign Flush = ID_flush || reset;

simplereg IF_ID_pc4(ID_pc4, pc4, IF_ID_WriteEn, Flush, clock);
simplereg IF_ID_Instr(ID_instr, Instr, IF_ID_WriteEn, Flush, clock);
simplereg #(1) IF_ID_flushReg(ID_flush, IF_ID_flush, IF_ID_WriteEn, Flush, clock);



ShiftLeft SL1 (jShift, {{6{ID_instr[25]}},ID_instr[25:0]});


assign jumpAddress = {ID_pc4[31:28],jShift};


Control ControlUnit (RegDest, Jump,BranchType, Branch, MemRead,MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, ID_instr[31:26], reset);


ForwardingUnit_ID FU_ID(ForwardA_ID, ForwardB_ID, Branch, MEM_RegWrite, RSin, RTin, MEM_WriteRegister,EX_WriteRegister, EX_RegWrite);


Mux3_1  BranchCompSrcA (ForwardA_ID, RSout, ALUResult ,MEM_RDdata, ZeroTestA);
Mux3_1  BranchCompSrcB (ForwardB_ID, RTout, ALUResult ,MEM_RDdata, ZeroTestB);


assign RSin = ID_instr[25:21];
assign RTin = ID_instr[20:16];


Register Rfile(RSout,RTout, WB_RDdata, RSin, RTin, WB_WriteRegister, WB_RegWrite, clock,reset,
  r8,r9,r10,r11,r12,r13,r14,r15,r16,r17,
r18,r19,r20,r21,r22,r23,r24,r25);


SignExt SE (SEOut, ID_instr[15:0]);


ALU ZeroTest (dummy31, Zero, ALUIn, ZeroTestA, ZeroTestB);


JRControl jrControl (jr, ALUOp, ID_instr[5:0]);


ALUControl ALUCUnit (ALUIn,ALUOp, ID_instr[5:0]);


Mux2_1 #(14) Nop_Control (stall_flush, {RegDest, Jump,BranchType, Branch, MemRead,MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite,jr}, 14'd0,
{Muxed_RegDest, Muxed_Jump,Muxed_BranchType,
Muxed_Branch, Muxed_MemRead,Muxed_MemtoReg,Muxed_ALUOp , Muxed_MemWrite, Muxed_ALUSrc, Muxed_RegWrite,Muxed_jr});


simplereg ID_EX_pc4(EX_pc4, ID_pc4, 1'b1, reset, clock);
simplereg ID_EX_rs(EX_rs, RSFlushedOut, 1'b1, reset, clock);
simplereg ID_EX_rt(EX_rt, RTFlushedOut, 1'b1, reset, clock);
simplereg #(4)ID_EX_ALUIn(EX_ALUIn, ALUIn, 1'b1, reset, clock);
simplereg ID_EX_immExt(EX_immExt, SEOut, 1'b1, reset, clock);
simplereg ID_EX_instr(EX_instr, ID_instr, 1'b1, reset, clock);
WBControlReg ID_EX_wb (EX_MemtoReg, EX_RegWrite, Muxed_MemtoReg, Muxed_RegWrite, 1'b1, reset, clock);
MEMControlReg ID_EX_mem (EX_MemWrite, EX_MemRead, Muxed_MemWrite, Muxed_MemRead, 1'b1, reset, clock);
EXControlReg ID_EX_ex (EX_ALUSrc, EX_RegDest, EX_ALUOp, Muxed_ALUSrc, Muxed_RegDest, Muxed_ALUOp, 1'b1, reset, clock);




Mux3_1 #(5) Rdest (EX_RegDest,EX_instr[20:16],EX_instr[15:11],5'd31,EX_WriteRegister);


ForwardingUnit_EX FU_EX (ForwardA_EX, ForwardB_EX,EX_instr[25:21], EX_instr[20:16], MEM_WriteRegister, WB_WriteRegister, MEM_RegWrite, WB_RegWrite);


Mux3_1 ALUsrcA (ForwardA_EX,EX_rs,WB_RDdata, MEM_ALUResult, ALU_A);
Mux3_1 FBSource (ForwardB_EX,EX_rt,WB_RDdata, MEM_ALUResult, FBout);


Mux2_1 ALUSrcB (EX_ALUSrc,FBout,EX_immExt,ALU_B);

ALU MainALU (ALUResult, dummy1, EX_ALUIn, ALU_A, ALU_B);


ShiftLeft SL2 (SL2Out, SEOut);


assign BranchAddr = ID_pc4 + SL2Out;




simplereg EX_MEM_pc4(MEM_pc4, EX_pc4, 1'b1, reset, clock);
simplereg EX_MEM_ALUResult(MEM_ALUResult, ALUResult, 1'b1, reset, clock);
simplereg EX_MEM_ALUb(MEM_FBout, FBout, 1'b1, reset, clock);
simplereg EX_MEM_ALUa(MEM_FAout, ALU_A, 1'b1, reset, clock);
simplereg #(5) EX_MEM_WriteRegister(MEM_WriteRegister, EX_WriteRegister, 1'b1, reset, clock);
WBControlReg EX_MEM_wb (MEM_MemtoReg, MEM_RegWrite, EX_MemtoReg, EX_RegWrite, 1'b1, reset, clock);
MEMControlReg EX_MEM_mem (MEM_MemWrite, MEM_MemRead,EX_MemWrite, EX_MemRead, 1'b1, reset, clock);





Memory DM(MEM_DMOut, MEM_FBout, MEM_ALUResult, MEM_MemWrite, MEM_MemRead,clock, reset);



simplereg MEM_WB_ALUResult(WB_ALUResult, MEM_ALUResult, 1'b1, reset, clock);
simplereg MEM_WB_pc4(WB_pc4, MEM_pc4, 1'b1, reset, clock);
simplereg MEM_WB_DMOut(WB_DMOut, MEM_DMOut, 1'b1, reset, clock);
simplereg #(5) MEM_WB_WriteRegister(WB_WriteRegister, MEM_WriteRegister, 1'b1, reset, clock);
WBControlReg MEM_WB_wb (WB_MemtoReg, WB_RegWrite, MEM_MemtoReg, MEM_RegWrite, 1'b1, reset, clock);






Mux3_1 WBMtoR (WB_MemtoReg,WB_ALUResult,WB_DMOut,WB_pc4,WB_RDdata);
Mux3_1 MEMMtoR (MEM_MemtoReg,MEM_ALUResult,MEM_DMOut,MEM_pc4,MEM_RDdata);





HazardDetUnit1 HDU1 (PCWrite, IF_ID_WriteEn, stall_flush, ID_instr, EX_MemRead, EX_instr[20:16]);


HazardDetUnit2 HDU2 (WB_RegWrite, RSin, RTin, WB_WriteRegister, RSout,RTout, WB_RDdata, RSFlushedOut,RTFlushedOut);

Mux2_1 #(1) BeqOrBne (Muxed_BranchType, Zero, ~Zero, btypeOut);


and (PCorBranch, Muxed_Branch, btypeOut);



PCSrc_Mux PCSrc (pcNext, pc4,BranchAddr,jumpAddress, RSout,PCorBranch,Jump,jr);

assign pcOut = pc ;
assign aluResult = MEM_ALUResult;

assign inst = Instr;
endmodule