data/full_repos/permissive/117026779/sim/Test_ShiftLoadRegister.v
 line:56: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_ShiftLoadRegister.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_ShiftLoadRegister.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #25\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_ShiftLoadRegister.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_ShiftLoadRegister.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #80\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_ShiftLoadRegister.v:59: Unsupported: Ignoring delay on this delayed statement.\n    always #5 sck = !sck;\n           ^\n%Error: data/full_repos/permissive/117026779/sim/Test_ShiftLoadRegister.v:31: Cannot find file containing module: \'SHIFTLOADREG\'\n    SHIFTLOADREG #(8) buff  (   .rst(i_rst),\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/SHIFTLOADREG\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/SHIFTLOADREG.v\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/SHIFTLOADREG.sv\n             SHIFTLOADREG\n             SHIFTLOADREG.v\n             SHIFTLOADREG.sv\n             obj_dir/SHIFTLOADREG\n             obj_dir/SHIFTLOADREG.v\n             obj_dir/SHIFTLOADREG.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_ShiftLoadRegister(

    );
    
    reg i_rst, sck, load, i_we, miso;
    reg [7:0] tx_packet;
    wire [7:0] rx_packet;
    
    SHIFTLOADREG #(8) buff  (   .rst(i_rst),
                                .clk(sck),
                                .load(load),
                                .en(i_we),
                                .in(miso),
                                .D(tx_packet),
                                .Q(rx_packet)
                            );
                            
    initial
    begin
        i_rst = 1;
        sck = 0;
        load = 0;
        i_we = 0;
        miso = 0;
        tx_packet = 8'h01;
        #5
        i_rst = 0;
        #25
        load = 1;
        #10
        load = 0;
        i_we = 1;
        #80
        $stop;
    end
    
    always #5 sck = !sck;
    
endmodule
module Test_ShiftLoadRegister(

    );

    
    reg i_rst, sck, load, i_we, miso;
    reg [7:0] tx_packet;
    wire [7:0] rx_packet;
    
    SHIFTLOADREG #(8) buff  (   .rst(i_rst),
                                .clk(sck),
                                .load(load),
                                .en(i_we),
                                .in(miso),
                                .D(tx_packet),
                                .Q(rx_packet)
                            );
                            
    initial
    begin
        i_rst = 1;
        sck = 0;
        load = 0;
        i_we = 0;
        miso = 0;
        tx_packet = 8'h01;
        #5
        i_rst = 0;
        #25
        load = 1;
        #10
        load = 0;
        i_we = 1;
        #80
        $stop;
    end
    
    always #5 sck = !sck;
    
endmodule