data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/multiplier.v
1: b'%Warning-WIDTH: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/multiplier.v:28: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                                    : ... In instance mul\n    assign result = C + S + cin;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module booth_mul(
    input  wire [65:0] x,
    input  wire [ 2:0] y,
    output wire [65:0] p,
    output wire        c
);
    wire [65:0] nx;
    wire [65:0] dx;
    wire [65:0] ndx;
    wire        m_1x;
    wire        p_1x;
    wire        m_2x;
    wire        p_2x;
    assign nx   = ~x;
    assign dx   = {x[64:0], 1'b0};
    assign ndx  = ~dx;
    assign m_1x = ( y[2] &  y[1] & ~y[0]) | ( y[2] & ~y[1] &  y[0]);
    assign p_1x = (~y[2] &  y[1] & ~y[0]) | (~y[2] & ~y[1] &  y[0]);
    assign m_2x =   y[2] & ~y[1] & ~y[0];
    assign p_2x =  ~y[2] &  y[1] &  y[0];
    assign {c,p} = ({67{m_1x}} & {1'b1, nx }) |
                   ({67{p_1x}} & {1'b0, x  }) |
                   ({67{m_2x}} & {1'b1, ndx}) |
                   ({67{p_2x}} & {1'b0, dx }) ;
endmodule
module booth_mul(
    input  wire [65:0] x,
    input  wire [ 2:0] y,
    output wire [65:0] p,
    output wire        c
);

    wire [65:0] nx;
    wire [65:0] dx;
    wire [65:0] ndx;
    wire        m_1x;
    wire        p_1x;
    wire        m_2x;
    wire        p_2x;
    assign nx   = ~x;
    assign dx   = {x[64:0], 1'b0};
    assign ndx  = ~dx;
    assign m_1x = ( y[2] &  y[1] & ~y[0]) | ( y[2] & ~y[1] &  y[0]);
    assign p_1x = (~y[2] &  y[1] & ~y[0]) | (~y[2] & ~y[1] &  y[0]);
    assign m_2x =   y[2] & ~y[1] & ~y[0];
    assign p_2x =  ~y[2] &  y[1] &  y[0];
    assign {c,p} = ({67{m_1x}} & {1'b1, nx }) |
                   ({67{p_1x}} & {1'b0, x  }) |
                   ({67{m_2x}} & {1'b1, ndx}) |
                   ({67{p_2x}} & {1'b0, dx }) ;
endmodule