data/full_repos/permissive/157005262/verilog/oled_play.v
None: at end of input
1: b'%Error: data/full_repos/permissive/157005262/verilog/oled_play.v:1: Cannot find include file: fpga-tools/components/uart.v\n`include "fpga-tools/components/uart.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/fpga-tools/components/uart.v\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/fpga-tools/components/uart.v.v\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/fpga-tools/components/uart.v.sv\n             fpga-tools/components/uart.v\n             fpga-tools/components/uart.v.v\n             fpga-tools/components/uart.v.sv\n             obj_dir/fpga-tools/components/uart.v\n             obj_dir/fpga-tools/components/uart.v.v\n             obj_dir/fpga-tools/components/uart.v.sv\n%Error: data/full_repos/permissive/157005262/verilog/oled_play.v:2: Cannot find include file: fpga-tools/components/oled.v\n`include "fpga-tools/components/oled.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module uart_display(input wire       clk,
                    input wire       d_read,


                    output reg [7:0] d_data,
                    output reg       d_ack,
                    input wire       uart_received,
                    input wire [7:0] uart_rx_byte);

  localparam DISPLAY_SIZE = 128*8;

  reg [7:0] data[0:DISPLAY_SIZE-1];
  reg [9:0] data_write_idx = 0;
  reg [9:0] data_read_idx = 0;

  reg byte_num = 0;
  reg [7:0] data_count = 0;
  reg [7:0] data_byte;

  always @(posedge clk) begin
    if (uart_received) begin
      if (byte_num == 0) begin
        data_count <= uart_rx_byte;
        byte_num <= 1;
      end else begin
        data_byte <= uart_rx_byte;
        data[data_write_idx] <= uart_rx_byte;
        data_write_idx <= (data_write_idx + 1) % DISPLAY_SIZE;
        byte_num <= 0;
      end
    end

    if (byte_num == 0 && data_count > 0) begin
      data[data_write_idx] <= data_byte;
      data_write_idx <= (data_write_idx + 1) % DISPLAY_SIZE;
      data_count <= data_count - 1;
    end

    if (d_read) begin
      d_data <= data[data_read_idx];
      d_ack <= 1;
      data_read_idx <= (data_read_idx + 1) % DISPLAY_SIZE;
    end else begin
      d_ack <= 0;
    end
  end
endmodule
module uart_display(input wire       clk,
                    input wire       d_read,


                    output reg [7:0] d_data,
                    output reg       d_ack,
                    input wire       uart_received,
                    input wire [7:0] uart_rx_byte);


  localparam DISPLAY_SIZE = 128*8;

  reg [7:0] data[0:DISPLAY_SIZE-1];
  reg [9:0] data_write_idx = 0;
  reg [9:0] data_read_idx = 0;

  reg byte_num = 0;
  reg [7:0] data_count = 0;
  reg [7:0] data_byte;

  always @(posedge clk) begin
    if (uart_received) begin
      if (byte_num == 0) begin
        data_count <= uart_rx_byte;
        byte_num <= 1;
      end else begin
        data_byte <= uart_rx_byte;
        data[data_write_idx] <= uart_rx_byte;
        data_write_idx <= (data_write_idx + 1) % DISPLAY_SIZE;
        byte_num <= 0;
      end
    end

    if (byte_num == 0 && data_count > 0) begin
      data[data_write_idx] <= data_byte;
      data_write_idx <= (data_write_idx + 1) % DISPLAY_SIZE;
      data_count <= data_count - 1;
    end

    if (d_read) begin
      d_data <= data[data_read_idx];
      d_ack <= 1;
      data_read_idx <= (data_read_idx + 1) % DISPLAY_SIZE;
    end else begin
      d_ack <= 0;
    end
  end
endmodule