data/full_repos/permissive/179451217/fifo_sync.v
1: b'%Warning-WIDTH: data/full_repos/permissive/179451217/fifo_sync.v:65: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 11 bits.\n                                                                   : ... In instance fifo_sync\nwire [AddrWidth-1:0] next_write_addr = (write_addr + 1) % DataDepth;\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/179451217/fifo_sync.v:66: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 11 bits.\n                                                                   : ... In instance fifo_sync\nwire [AddrWidth-1:0] next_read_addr = (read_addr + 1) % DataDepth;\n                                    ^\n%Error: data/full_repos/permissive/179451217/fifo_sync.v:71: Cannot find file containing module: \'ram_dp\'\nram_dp #(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179451217,data/full_repos/permissive/179451217/ram_dp\n             data/full_repos/permissive/179451217,data/full_repos/permissive/179451217/ram_dp.v\n             data/full_repos/permissive/179451217,data/full_repos/permissive/179451217/ram_dp.sv\n             ram_dp\n             ram_dp.v\n             ram_dp.sv\n             obj_dir/ram_dp\n             obj_dir/ram_dp.v\n             obj_dir/ram_dp.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module fifo_sync #(
    parameter DataWidth = 16,
    parameter DataDepth = 1024,
    parameter AddrWidth = 10,
    parameter InitFile = "",
    parameter InitCount = 0,
    parameter VendorImpl = ""
)(
    input wire clk,
    input wire reset,

    input wire write_en,
    input wire [DataWidth-1:0] write_data,
    output reg fifo_full,

    input wire read_en,
    output wire [DataWidth-1:0] read_data,
    output reg fifo_empty
);


reg [AddrWidth-1:0] write_addr, write_addr_D;
reg [AddrWidth-1:0] read_addr, read_addr_D;
reg first_write, first_write_D;
reg do_write, fifo_full_D, fifo_empty_D;

wire [AddrWidth-1:0] next_write_addr = (write_addr + 1) % DataDepth;
wire [AddrWidth-1:0] next_read_addr = (read_addr + 1) % DataDepth;
wire do_read = (read_en & ~fifo_empty) | (~first_write & fifo_empty);



ram_dp #(
    .DataWidth(DataWidth),
    .DataDepth(DataDepth),
    .AddrWidth(AddrWidth),
    .InitFile(InitFile),
    .InitValue(0),
    .InitCount(InitCount),
    .VendorImpl(VendorImpl)
) mem (
    .write_clk(clk),
    .write_en(do_write),
    .write_addr(write_addr),
    .write_data(write_data),
    .read_clk(clk),
    .read_en(do_read),
    .read_addr(read_addr_D),
    .read_data(read_data)
);


generate
if(InitCount > 0) initial begin
    write_addr = InitCount % DataDepth;
    read_addr  = 0;
    fifo_full  = (InitCount == DataDepth);
    fifo_empty = 0;
end
endgenerate


always @* begin
    write_addr_D = write_addr;
    read_addr_D = read_addr;
    fifo_full_D = fifo_full;
    fifo_empty_D = fifo_empty;
    first_write_D = first_write;
    if(first_write == 1'b0) fifo_empty_D = 1'b0;
    do_write = 1'b0;
    if(write_en == 1'b1 && read_en == 1'b1) begin

        do_write = 1'b1;
        write_addr_D = next_write_addr;
        if(fifo_empty == 1'b1) begin
            fifo_full_D = (next_write_addr == read_addr);
            first_write_D = 1'b0;
        end else begin
            read_addr_D = next_read_addr;

        end
    end else if(write_en == 1'b1) begin
        if(fifo_full == 1'b0) begin

            do_write = 1'b1;
            write_addr_D = next_write_addr;
            fifo_full_D = (next_write_addr == read_addr);
            if(fifo_empty) first_write_D = 1'b0;
        end
    end else if(read_en == 1'b1) begin
        if(fifo_empty == 1'b0) begin

            fifo_full_D = 1'b0;
            read_addr_D = next_read_addr;
            fifo_empty_D = (next_read_addr == write_addr);
            first_write_D = fifo_empty_D;
        end
    end
end


always @(posedge clk) begin
    if(reset) begin
        write_addr <= 0;
        read_addr <= 0;
        fifo_full <= 1'b0;
        fifo_empty <= 1'b1;
        first_write <= 1'b1;
    end else begin 
        write_addr <= write_addr_D;
        read_addr <= read_addr_D;
        fifo_full <= fifo_full_D;
        fifo_empty <= fifo_empty_D;
        first_write <= first_write_D;
    end
end

endmodule
module fifo_sync #(
    parameter DataWidth = 16,
    parameter DataDepth = 1024,
    parameter AddrWidth = 10,
    parameter InitFile = "",
    parameter InitCount = 0,
    parameter VendorImpl = ""
)(
    input wire clk,
    input wire reset,

    input wire write_en,
    input wire [DataWidth-1:0] write_data,
    output reg fifo_full,

    input wire read_en,
    output wire [DataWidth-1:0] read_data,
    output reg fifo_empty
);



reg [AddrWidth-1:0] write_addr, write_addr_D;
reg [AddrWidth-1:0] read_addr, read_addr_D;
reg first_write, first_write_D;
reg do_write, fifo_full_D, fifo_empty_D;

wire [AddrWidth-1:0] next_write_addr = (write_addr + 1) % DataDepth;
wire [AddrWidth-1:0] next_read_addr = (read_addr + 1) % DataDepth;
wire do_read = (read_en & ~fifo_empty) | (~first_write & fifo_empty);



ram_dp #(
    .DataWidth(DataWidth),
    .DataDepth(DataDepth),
    .AddrWidth(AddrWidth),
    .InitFile(InitFile),
    .InitValue(0),
    .InitCount(InitCount),
    .VendorImpl(VendorImpl)
) mem (
    .write_clk(clk),
    .write_en(do_write),
    .write_addr(write_addr),
    .write_data(write_data),
    .read_clk(clk),
    .read_en(do_read),
    .read_addr(read_addr_D),
    .read_data(read_data)
);


generate
if(InitCount > 0) initial begin
    write_addr = InitCount % DataDepth;
    read_addr  = 0;
    fifo_full  = (InitCount == DataDepth);
    fifo_empty = 0;
end
endgenerate


always @* begin
    write_addr_D = write_addr;
    read_addr_D = read_addr;
    fifo_full_D = fifo_full;
    fifo_empty_D = fifo_empty;
    first_write_D = first_write;
    if(first_write == 1'b0) fifo_empty_D = 1'b0;
    do_write = 1'b0;
    if(write_en == 1'b1 && read_en == 1'b1) begin

        do_write = 1'b1;
        write_addr_D = next_write_addr;
        if(fifo_empty == 1'b1) begin
            fifo_full_D = (next_write_addr == read_addr);
            first_write_D = 1'b0;
        end else begin
            read_addr_D = next_read_addr;

        end
    end else if(write_en == 1'b1) begin
        if(fifo_full == 1'b0) begin

            do_write = 1'b1;
            write_addr_D = next_write_addr;
            fifo_full_D = (next_write_addr == read_addr);
            if(fifo_empty) first_write_D = 1'b0;
        end
    end else if(read_en == 1'b1) begin
        if(fifo_empty == 1'b0) begin

            fifo_full_D = 1'b0;
            read_addr_D = next_read_addr;
            fifo_empty_D = (next_read_addr == write_addr);
            first_write_D = fifo_empty_D;
        end
    end
end


always @(posedge clk) begin
    if(reset) begin
        write_addr <= 0;
        read_addr <= 0;
        fifo_full <= 1'b0;
        fifo_empty <= 1'b1;
        first_write <= 1'b1;
    end else begin 
        write_addr <= write_addr_D;
        read_addr <= read_addr_D;
        fifo_full <= fifo_full_D;
        fifo_empty <= fifo_empty_D;
        first_write <= first_write_D;
    end
end

endmodule