data/full_repos/permissive/171756809/synchronous_reset_timer_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/171756809/synchronous_reset_timer_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = clk+1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/171756809/synchronous_reset_timer_tb.v:50: syntax error, unexpected \'@\'\n   @(negedge clk);\n   ^\n%Error: data/full_repos/permissive/171756809/synchronous_reset_timer_tb.v:59: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Error: data/full_repos/permissive/171756809/synchronous_reset_timer_tb.v:68: syntax error, unexpected \'@\'\n   @(negedge clk);\n   ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module synchronous_reset_timer_tb();

	generate
		genvar i;
		for(i=3; i<33; i=i+1) begin: reset_tests
			single_synchronous_reset_timer_tb #(.LENGTH(i)) dut();
		end
	endgenerate

endmodule
module synchronous_reset_timer_tb();


	generate
		genvar i;
		for(i=3; i<33; i=i+1) begin: reset_tests
			single_synchronous_reset_timer_tb #(.LENGTH(i)) dut();
		end
	endgenerate

endmodule