data/full_repos/permissive/159016511/src/rtl/common/en_cnt.v
data/verilator_xmls/d13f4fd2-eed8-4755-9db6-0a814b6378b4.xml
module en_cnt (
input wire clk,
input wire rstn,
input wire en,
output reg [31:0] cnt
);

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		cnt <= 0;
	end
	else
	begin 
		if(en)
		begin
			cnt <= cnt + 1;
		end
	end
end

endmodule
module en_cnt (
input wire clk,
input wire rstn,
input wire en,
output reg [31:0] cnt
);


always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		cnt <= 0;
	end
	else
	begin 
		if(en)
		begin
			cnt <= cnt + 1;
		end
	end
end

endmodule