data/full_repos/permissive/198548420/nexys4ddr/ch09_vga_basic/vga.v
data/verilator_xmls/b2bb0dd9-b4e6-4a44-add5-d696bac3754d.xml
module vga(
    input CLK,
    output HS, VS, HS_probe, VS_probe,
    output [9:0] x,
    output reg [9:0] y,
    output blank
    );
reg [1:0] prescaler;
reg [9:0] xc;
 


assign blank = ((xc < 192) | (xc > 832) | (y > 479));
assign HS = ~ ((xc > 23) & (xc < 65));
assign VS = ~ ((y > 489) & (y < 493));
assign HS_probe = HS;
assign VS_probe = VS;
assign x = ((xc < 192)?0:(xc - 192));

always @(posedge CLK)
  
begin
  prescaler = prescaler + 1;
  if (prescaler == 0 )
  begin
  if (xc == 832)
  begin
    xc <= 0;
    y <= y + 1;
  end
  else begin
    xc <= xc + 1;
  end
  if (y == 520)
  begin
    y <= 0; 
  end
  end
end

endmodule
module vga(
    input CLK,
    output HS, VS, HS_probe, VS_probe,
    output [9:0] x,
    output reg [9:0] y,
    output blank
    );

reg [1:0] prescaler;
reg [9:0] xc;
 


assign blank = ((xc < 192) | (xc > 832) | (y > 479));
assign HS = ~ ((xc > 23) & (xc < 65));
assign VS = ~ ((y > 489) & (y < 493));
assign HS_probe = HS;
assign VS_probe = VS;
assign x = ((xc < 192)?0:(xc - 192));

always @(posedge CLK)
  
begin
  prescaler = prescaler + 1;
  if (prescaler == 0 )
  begin
  if (xc == 832)
  begin
    xc <= 0;
    y <= y + 1;
  end
  else begin
    xc <= xc + 1;
  end
  if (y == 520)
  begin
    y <= 0; 
  end
  end
end

endmodule