data/full_repos/permissive/187705377/Camera Reduced/V_D8M/ON_CHIP_FRAM.v
1: b'%Error: Cannot find file containing module: Reduced/V_D8M,data/full_repos/permissive/187705377\n        ... Looked in:\n             data/full_repos/permissive/187705377/Camera/Reduced/V_D8M,data/full_repos/permissive/187705377\n             data/full_repos/permissive/187705377/Camera/Reduced/V_D8M,data/full_repos/permissive/187705377.v\n             data/full_repos/permissive/187705377/Camera/Reduced/V_D8M,data/full_repos/permissive/187705377.sv\n             Reduced/V_D8M,data/full_repos/permissive/187705377\n             Reduced/V_D8M,data/full_repos/permissive/187705377.v\n             Reduced/V_D8M,data/full_repos/permissive/187705377.sv\n             obj_dir/Reduced/V_D8M,data/full_repos/permissive/187705377\n             obj_dir/Reduced/V_D8M,data/full_repos/permissive/187705377.v\n             obj_dir/Reduced/V_D8M,data/full_repos/permissive/187705377.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/187705377/Camera\n%Error: Cannot find file containing module: Reduced/V_D8M/ON_CHIP_FRAM.v\n%Error: Exiting due to 3 error(s)\n'
module ON_CHIP_FRAM  ( 
    input         W_CLK ,  
    input         R_CLK ,  
    input         W_DE   ,  
    input  [9:0]  W_DATA , 
    output [9:0]  R_DATA , 
    input         W_CLR , 
    input         R_CLR ,  
    input         R_DE,
    output [19:0]WR_ADDR,
    output [19:0]RD_ADDR

 ); 



 

FRM_COUNTER wrw(.CLOCK( W_CLK),.CLR( W_CLR ),.DE( W_DE ),.ADDR( WR_ADDR)  );
FRM_COUNTER rrr(.CLOCK( R_CLK),.CLR( R_CLR ),.DE( R_DE ),.ADDR( RD_ADDR)  );














	
	
FRAM_BUFF GG(
	.wraddress(WR_ADDR[19:0]),
	.rdaddress(RD_ADDR[19:0]),
	.data     (W_DATA [9:0]),
	.wrclock  (W_CLK),
	.rdclock  (R_CLK),
	.wren     (W_DE),
	.q        (R_DATA[9:0] )
	);
	

endmodule
module ON_CHIP_FRAM  ( 
    input         W_CLK ,  
    input         R_CLK ,  
    input         W_DE   ,  
    input  [9:0]  W_DATA , 
    output [9:0]  R_DATA , 
    input         W_CLR , 
    input         R_CLR ,  
    input         R_DE,
    output [19:0]WR_ADDR,
    output [19:0]RD_ADDR

 );
 



 

FRM_COUNTER wrw(.CLOCK( W_CLK),.CLR( W_CLR ),.DE( W_DE ),.ADDR( WR_ADDR)  );
FRM_COUNTER rrr(.CLOCK( R_CLK),.CLR( R_CLR ),.DE( R_DE ),.ADDR( RD_ADDR)  );














	
	
FRAM_BUFF GG(
	.wraddress(WR_ADDR[19:0]),
	.rdaddress(RD_ADDR[19:0]),
	.data     (W_DATA [9:0]),
	.wrclock  (W_CLK),
	.rdclock  (R_CLK),
	.wren     (W_DE),
	.q        (R_DATA[9:0] )
	);
	

endmodule