data/full_repos/permissive/123796236/alucontrol.v
 line:31: before: ","
1: b'%Error: data/full_repos/permissive/123796236/alucontrol.v:31: Unsupported or unknown PLI call: $monitor\n$monitor($time,,,"%b %b %b",ALUOp,funct,ALUOpInput);\n^~~~~~~~\n%Error: data/full_repos/permissive/123796236/alucontrol.v:31: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n$monitor($time,,,"%b %b %b",ALUOp,funct,ALUOpInput);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alucontrol.v:33: Unsupported: Ignoring delay on this delayed statement.\n#5 ALUOp=2\'b00;funct=6\'b111111;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alucontrol.v:34: Unsupported: Ignoring delay on this delayed statement.\n#5 ALUOp=2\'b00;funct=6\'b111111;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alucontrol.v:35: Unsupported: Ignoring delay on this delayed statement.\n#5 ALUOp=2\'b10;funct=6\'b100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alucontrol.v:36: Unsupported: Ignoring delay on this delayed statement.\n#5 ALUOp=2\'b10;funct=6\'b100010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alucontrol.v:37: Unsupported: Ignoring delay on this delayed statement.\n#5 ALUOp=2\'b10;funct=6\'b100101;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alucontrol.v:38: Unsupported: Ignoring delay on this delayed statement.\n#5 ALUOp=2\'b10;funct=6\'b101010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alucontrol.v:39: Unsupported: Ignoring delay on this delayed statement.\n#5 ALUOp=2\'b01;funct=6\'b100001;\n^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALUcontrol(funct,ALUOp,ALUOpInput);
input [5:0] funct;
input [1:0] ALUOp;
output reg [3:0] ALUOpInput;
wire [7:0] ALUOpfunct;

assign ALUOpfunct={ALUOp,funct};

always@(ALUOpfunct)
begin
casex(ALUOpfunct)
8'b00xxxxxx:ALUOpInput=4'b0010;
8'b01xxxxxx:ALUOpInput=4'b0110;
8'b10100000:ALUOpInput=4'b0010;
8'b10100010:ALUOpInput=4'b0110;
8'b10100100:ALUOpInput=4'b0000;
8'b10100101:ALUOpInput=4'b0001;
8'b10101010:ALUOpInput=4'b0111;
endcase
end
endmodule
module ALUcontrol(funct,ALUOp,ALUOpInput);

input [5:0] funct;
input [1:0] ALUOp;
output reg [3:0] ALUOpInput;
wire [7:0] ALUOpfunct;

assign ALUOpfunct={ALUOp,funct};

always@(ALUOpfunct)
begin
casex(ALUOpfunct)
8'b00xxxxxx:ALUOpInput=4'b0010;
8'b01xxxxxx:ALUOpInput=4'b0110;
8'b10100000:ALUOpInput=4'b0010;
8'b10100010:ALUOpInput=4'b0110;
8'b10100100:ALUOpInput=4'b0000;
8'b10100101:ALUOpInput=4'b0001;
8'b10101010:ALUOpInput=4'b0111;
endcase
end
endmodule