data/full_repos/permissive/143278/ivltests/ga_mod.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod.v:52: Unsupported: Ignoring delay on this delayed statement.\n    # 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ga_mod.v:57: Unsupported: Ignoring delay on this delayed statement.\n            #1 ;\n            ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

reg globvar;

wire [15:0] out;
reg [15:0] a,b, rslt;
reg error;



my_and foo [0:3] (out,a,b);

always @(a or b)
  rslt = a & b;

initial
  begin
    error = 0;
    # 1;
    for(a = 16'h1; a != 16'hffff; a = (a << 1) | 1)
      begin
        for(b = 16'hffff; b !== 16'h0; b = b >> 1)
          begin
            #1 ;
            if(out !== rslt)
              begin
                 $display("FAILED - GA And a=%h,b=%h,expct=%h - rcvd=%h",
                           a,b,rslt,out);
                 error = 1;
              end
          end
      end
    if( error == 0)
      $display("PASSED");
  end
endmodule
module main;


reg globvar;

wire [15:0] out;
reg [15:0] a,b, rslt;
reg error;



my_and foo [0:3] (out,a,b);

always @(a or b)
  rslt = a & b;

initial
  begin
    error = 0;
    # 1;
    for(a = 16'h1; a != 16'hffff; a = (a << 1) | 1)
      begin
        for(b = 16'hffff; b !== 16'h0; b = b >> 1)
          begin
            #1 ;
            if(out !== rslt)
              begin
                 $display("FAILED - GA And a=%h,b=%h,expct=%h - rcvd=%h",
                           a,b,rslt,out);
                 error = 1;
              end
          end
      end
    if( error == 0)
      $display("PASSED");
  end
endmodule