data/full_repos/permissive/160035208/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160035208/top.v:16: Operator GT expects 17 bits on the RHS, but RHS\'s CONST \'16\'hc\' generates 16 bits.\n                                                             : ... In instance top\n        if (clkdiv > 16\'d12)\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/160035208/top.v:27: Cannot find file containing module: \'hd44780\'\n   hd44780 hd44780_ctrl (.clk(clk_1mhz),\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160035208,data/full_repos/permissive/160035208/hd44780\n             data/full_repos/permissive/160035208,data/full_repos/permissive/160035208/hd44780.v\n             data/full_repos/permissive/160035208,data/full_repos/permissive/160035208/hd44780.sv\n             hd44780\n             hd44780.v\n             hd44780.sv\n             obj_dir/hd44780\n             obj_dir/hd44780.v\n             obj_dir/hd44780.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module top(
           input clk,
           input rst_n,
           output [7:0] led,
           output lcd_rs,
           output lcd_rw,
           output lcd_clk,
           output [7:0] lcd_data
           );

   reg [16:0]    clkdiv;
   reg           clk_1mhz;

   always @ (negedge clk)
     begin
        if (clkdiv > 16'd12)
          begin
             clk_1mhz <= ~clk_1mhz;
             clkdiv <= 0;
          end
        else
          begin
             clkdiv <= clkdiv + 1;
          end
     end

   hd44780 hd44780_ctrl (.clk(clk_1mhz),
                         .rst_n(rst_n),
                         .lcd_rs(lcd_rs),
                         .lcd_rw(lcd_rw),
                         .lcd_clk(lcd_clk),
                         .lcd_data(lcd_data));

   assign led = ~lcd_data;
endmodule
module top(
           input clk,
           input rst_n,
           output [7:0] led,
           output lcd_rs,
           output lcd_rw,
           output lcd_clk,
           output [7:0] lcd_data
           );


   reg [16:0]    clkdiv;
   reg           clk_1mhz;

   always @ (negedge clk)
     begin
        if (clkdiv > 16'd12)
          begin
             clk_1mhz <= ~clk_1mhz;
             clkdiv <= 0;
          end
        else
          begin
             clkdiv <= clkdiv + 1;
          end
     end

   hd44780 hd44780_ctrl (.clk(clk_1mhz),
                         .rst_n(rst_n),
                         .lcd_rs(lcd_rs),
                         .lcd_rw(lcd_rw),
                         .lcd_clk(lcd_clk),
                         .lcd_data(lcd_data));

   assign led = ~lcd_data;
endmodule