data/full_repos/permissive/211316121/lab8_2_nexys4/Display.v
data/verilator_xmls/6768e043-c1d4-4bd6-ae9b-77158dc57bba.xml
module BCD_7Seg(
    input [3:0] addr,
    input [3:0] value,
    input clr,
    input [2:0] clkcount,
    output [6:0] a2g,
    output reg [7:0] an
    );
    
    reg [3:0] digit;
    parameter aen = 8'b01111110;
    
    always @ (*)
    case(clkcount)
        3'b000:  digit = value;
        3'b001:  digit = 4'b0000;
        3'b010:  digit = 4'b0000;
        3'b011:  digit = 4'b0000;
        3'b100:  digit = 4'b0000;
        3'b101:  digit = 4'b0000;
        3'b110:  digit = 4'b0000;
        3'b111:  digit = addr;
    endcase
    
    always @ (*)
    begin
        an = 8'b11111111;
        if(~clr)
            an[clkcount] = aen[clkcount];
    end
    
    seven_segment seg0(digit, a2g);
endmodule
module BCD_7Seg(
    input [3:0] addr,
    input [3:0] value,
    input clr,
    input [2:0] clkcount,
    output [6:0] a2g,
    output reg [7:0] an
    );

    
    reg [3:0] digit;
    parameter aen = 8'b01111110;
    
    always @ (*)
    case(clkcount)
        3'b000:  digit = value;
        3'b001:  digit = 4'b0000;
        3'b010:  digit = 4'b0000;
        3'b011:  digit = 4'b0000;
        3'b100:  digit = 4'b0000;
        3'b101:  digit = 4'b0000;
        3'b110:  digit = 4'b0000;
        3'b111:  digit = addr;
    endcase
    
    always @ (*)
    begin
        an = 8'b11111111;
        if(~clr)
            an[clkcount] = aen[clkcount];
    end
    
    seven_segment seg0(digit, a2g);
endmodule