data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv
 line:24: before: "class"
1: b"%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:24: Unsupported: classes\nclass tlx_afu_monitor extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:24: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass tlx_afu_monitor extends uvm_monitor;\n                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:28: Unsupported: virtual interface\n    virtual interface tlx_afu_interface                   tlx_afu_vif;\n    ^~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:29: Unsupported: virtual interface\n    virtual interface intrp_interface                     intrp_vif;\n    ^~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:30: syntax error, unexpected IDENTIFIER\n    uvm_analysis_port #(tlx_afu_transaction)              tlx_afu_tran_port;\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:51: syntax error, unexpected IDENTIFIER\n    afu_tlx_transaction      afu_tlx_cmd_trans_q[$];\n    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:61: Unsupported: SystemVerilog 2005 reserved word not implemented: 'covergroup'\n    covergroup c_tlx_afu_resp_packet;\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:63: Unsupported: SystemVerilog 2005 reserved word not implemented: 'coverpoint'\n        packet_type: coverpoint tlx_afu_resp_trans_q[0].tlx_afu_type {\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:64: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins read_response        = {tlx_afu_transaction::READ_RESPONSE};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:65: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins read_failed          = {tlx_afu_transaction::READ_FAILED};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:66: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins write_response       = {tlx_afu_transaction::WRITE_RESPONSE};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:67: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins write_failed         = {tlx_afu_transaction::WRITE_FAILED};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:68: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins xlate_done           = {tlx_afu_transaction::XLATE_DONE};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:69: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins intrp_resp           = {tlx_afu_transaction::INTRP_RESP};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:70: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins intrp_rdy            = {tlx_afu_transaction::INTRP_RDY};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:72: Unsupported: SystemVerilog 2005 reserved word not implemented: 'coverpoint'\n        pre_packet_type: coverpoint pre_tlx_afu_resp_trans.tlx_afu_type {\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:74: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins read_response        = {tlx_afu_transaction::READ_RESPONSE};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:75: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins read_failed          = {tlx_afu_transaction::READ_FAILED};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:76: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins write_response       = {tlx_afu_transaction::WRITE_RESPONSE};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:77: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins write_failed         = {tlx_afu_transaction::WRITE_FAILED};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:78: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins xlate_done           = {tlx_afu_transaction::XLATE_DONE};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:79: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins intrp_resp           = {tlx_afu_transaction::INTRP_RESP};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins intrp_rdy            = {tlx_afu_transaction::INTRP_RDY};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:82: Unsupported: SystemVerilog 2005 reserved word not implemented: 'coverpoint'\n        resp_code: coverpoint tlx_afu_resp_trans_q[0].tlx_afu_resp_code {\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:84: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins resp_code_0          ={4'h0};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:85: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins resp_code_2          ={4'h2};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins resp_code_4          ={4'h4};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:88: Unsupported: SystemVerilog 2005 reserved word not implemented: 'coverpoint'\n        data_length: coverpoint tlx_afu_resp_trans_q[0].tlx_afu_dl {\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:90: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins data_length_64       ={2'h1};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:91: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins data_length_128      ={2'h2};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:93: Unsupported: SystemVerilog 2005 reserved word not implemented: 'coverpoint'\n        data_part: coverpoint tlx_afu_resp_trans_q[0].tlx_afu_dp {\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:95: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins data_part_0          ={2'h0};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:96: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins data_part_1          ={2'h1};\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:98: Unsupported: SystemVerilog 2005 reserved word not implemented: 'cross'\n        tlx_afu_two_packet_type: cross packet_type, pre_packet_type;\n                                 ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:99: Unsupported: SystemVerilog 2005 reserved word not implemented: 'cross'\n        read_resp_packet: cross packet_type, data_length, data_part {\n                          ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:100: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins rd_resp_dlength64_dpart0=binsof(packet_type.read_response) && binsof(data_length.data_length_64) && binsof(data_part.data_part_0);\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:100: Unsupported: SystemVerilog 2005 reserved word not implemented: 'binsof'\n            bins rd_resp_dlength64_dpart0=binsof(packet_type.read_response) && binsof(data_length.data_length_64) && binsof(data_part.data_part_0);\n                                          ^~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:100: Unsupported: SystemVerilog 2005 reserved word not implemented: 'binsof'\n            bins rd_resp_dlength64_dpart0=binsof(packet_type.read_response) && binsof(data_length.data_length_64) && binsof(data_part.data_part_0);\n                                                                               ^~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:100: Unsupported: SystemVerilog 2005 reserved word not implemented: 'binsof'\n            bins rd_resp_dlength64_dpart0=binsof(packet_type.read_response) && binsof(data_length.data_length_64) && binsof(data_part.data_part_0);\n                                                                                                                     ^~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:101: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins rd_resp_dlength64_dpart1=binsof(packet_type.read_response) && binsof(data_length.data_length_64) && binsof(data_part.data_part_1);\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:101: Unsupported: SystemVerilog 2005 reserved word not implemented: 'binsof'\n            bins rd_resp_dlength64_dpart1=binsof(packet_type.read_response) && binsof(data_length.data_length_64) && binsof(data_part.data_part_1);\n                                          ^~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:101: Unsupported: SystemVerilog 2005 reserved word not implemented: 'binsof'\n            bins rd_resp_dlength64_dpart1=binsof(packet_type.read_response) && binsof(data_length.data_length_64) && binsof(data_part.data_part_1);\n                                                                               ^~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:101: Unsupported: SystemVerilog 2005 reserved word not implemented: 'binsof'\n            bins rd_resp_dlength64_dpart1=binsof(packet_type.read_response) && binsof(data_length.data_length_64) && binsof(data_part.data_part_1);\n                                                                                                                     ^~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:102: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins rd_resp_dlength128_dpart0=binsof(packet_type.read_response) && binsof(data_length.data_length_128) && binsof(data_part.data_part_0);\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:102: Unsupported: SystemVerilog 2005 reserved word not implemented: 'binsof'\n            bins rd_resp_dlength128_dpart0=binsof(packet_type.read_response) && binsof(data_length.data_length_128) && binsof(data_part.data_part_0);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:102: Unsupported: SystemVerilog 2005 reserved word not implemented: 'binsof'\n            bins rd_resp_dlength128_dpart0=binsof(packet_type.read_response) && binsof(data_length.data_length_128) && binsof(data_part.data_part_0);\n                                                                                ^~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:102: Unsupported: SystemVerilog 2005 reserved word not implemented: 'binsof'\n            bins rd_resp_dlength128_dpart0=binsof(packet_type.read_response) && binsof(data_length.data_length_128) && binsof(data_part.data_part_0);\n                                                                                                                       ^~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:104: Unsupported: SystemVerilog 2005 reserved word not implemented: 'cross'\n        write_resp_packet: cross packet_type, data_length, data_part {\n                           ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:105: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n            bins wr_resp_dlength64_dpart0=binsof(packet_type.write_response) && binsof(data_length.data_length_64) && binsof(data_part.data_part_0);\n            ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/mon/tlx_afu_monitor.sv:105: Unsupported: SystemVerilog 2005 reserved word not implemented: 'binsof'\n            bins wr_resp_dlength64_dpart0=binsof(packet_type.write_response) && binsof(data_length.data_length_64) && binsof(data_part.data_part_0);\n                                          ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n"
function void tlx_afu_monitor::pack_afu_tlx_cmd();
    if(afu_tlx_cmd_trans_q[0].afu_tlx_type == afu_tlx_transaction::DMA_W || afu_tlx_cmd_trans_q[0].afu_tlx_type == afu_tlx_transaction::DMA_W_N) begin
        if(afu_tlx_cmd_data_q.size >= dl2dl_num(afu_tlx_cmd_trans_q[0].afu_tlx_dl)) begin
            for(int i=0; i<dl2dl_num(afu_tlx_cmd_trans_q[0].afu_tlx_dl); i++) begin
                afu_tlx_cmd_trans_q[0].afu_tlx_data_bus[i] = afu_tlx_cmd_data_q[0][511:0];
                afu_tlx_cmd_trans_q[0].afu_tlx_data_bdi[i] = afu_tlx_cmd_data_q[0][512];
                afu_tlx_cmd_data_q.pop_front();
            end
            `uvm_info(tID, $sformatf("Collect an afu-tlx command and data.\n%s", afu_tlx_cmd_trans_q[0].sprint()), UVM_MEDIUM);
            c_afu_tlx_cmd_packet.sample();
            $cast(pre_afu_tlx_cmd_trans, afu_tlx_cmd_trans_q[0].clone()); 
            afu_tlx_tran_port.write(afu_tlx_cmd_trans_q.pop_front());
        end
    end
    else if(afu_tlx_cmd_trans_q[0].afu_tlx_type == afu_tlx_transaction::DMA_W_BE || afu_tlx_cmd_trans_q[0].afu_tlx_type == afu_tlx_transaction::DMA_W_BE_N ||
            afu_tlx_cmd_trans_q[0].afu_tlx_type == afu_tlx_transaction::DMA_PR_W || afu_tlx_cmd_trans_q[0].afu_tlx_type == afu_tlx_transaction::DMA_PR_W) begin
        if(afu_tlx_cmd_data_q.size > 0) begin
            afu_tlx_cmd_trans_q[0].afu_tlx_data_bus[0] = afu_tlx_cmd_data_q[0][511:0];
            afu_tlx_cmd_trans_q[0].afu_tlx_data_bdi[0] = afu_tlx_cmd_data_q[0][512];
            afu_tlx_cmd_data_q.pop_front();                        
            c_afu_tlx_cmd_packet.sample();
            $cast(pre_afu_tlx_cmd_trans, afu_tlx_cmd_trans_q[0].clone());
            `uvm_info(tID, $sformatf("Collect an afu-tlx command and data.\n%s", afu_tlx_cmd_trans_q[0].sprint()), UVM_MEDIUM);
            afu_tlx_tran_port.write(afu_tlx_cmd_trans_q.pop_front());
        end
    end
    else begin
        c_afu_tlx_cmd_packet.sample();
        $cast(pre_afu_tlx_cmd_trans, afu_tlx_cmd_trans_q[0].clone()); 
        `uvm_info(tID, $sformatf("Collect an afu-tlx command.\n%s", afu_tlx_cmd_trans_q[0].sprint()), UVM_MEDIUM);
        afu_tlx_tran_port.write(afu_tlx_cmd_trans_q.pop_front());
    end
endfunction
function void tlx_afu_monitor::pack_afu_tlx_cmd();

    if(afu_tlx_cmd_trans_q[0].afu_tlx_type == afu_tlx_transaction::DMA_W || afu_tlx_cmd_trans_q[0].afu_tlx_type == afu_tlx_transaction::DMA_W_N) begin
        if(afu_tlx_cmd_data_q.size >= dl2dl_num(afu_tlx_cmd_trans_q[0].afu_tlx_dl)) begin
            for(int i=0; i<dl2dl_num(afu_tlx_cmd_trans_q[0].afu_tlx_dl); i++) begin
                afu_tlx_cmd_trans_q[0].afu_tlx_data_bus[i] = afu_tlx_cmd_data_q[0][511:0];
                afu_tlx_cmd_trans_q[0].afu_tlx_data_bdi[i] = afu_tlx_cmd_data_q[0][512];
                afu_tlx_cmd_data_q.pop_front();
            end
            `uvm_info(tID, $sformatf("Collect an afu-tlx command and data.\n%s", afu_tlx_cmd_trans_q[0].sprint()), UVM_MEDIUM);
            c_afu_tlx_cmd_packet.sample();
            $cast(pre_afu_tlx_cmd_trans, afu_tlx_cmd_trans_q[0].clone()); 
            afu_tlx_tran_port.write(afu_tlx_cmd_trans_q.pop_front());
        end
    end
    else if(afu_tlx_cmd_trans_q[0].afu_tlx_type == afu_tlx_transaction::DMA_W_BE || afu_tlx_cmd_trans_q[0].afu_tlx_type == afu_tlx_transaction::DMA_W_BE_N ||
            afu_tlx_cmd_trans_q[0].afu_tlx_type == afu_tlx_transaction::DMA_PR_W || afu_tlx_cmd_trans_q[0].afu_tlx_type == afu_tlx_transaction::DMA_PR_W) begin
        if(afu_tlx_cmd_data_q.size > 0) begin
            afu_tlx_cmd_trans_q[0].afu_tlx_data_bus[0] = afu_tlx_cmd_data_q[0][511:0];
            afu_tlx_cmd_trans_q[0].afu_tlx_data_bdi[0] = afu_tlx_cmd_data_q[0][512];
            afu_tlx_cmd_data_q.pop_front();                        
            c_afu_tlx_cmd_packet.sample();
            $cast(pre_afu_tlx_cmd_trans, afu_tlx_cmd_trans_q[0].clone());
            `uvm_info(tID, $sformatf("Collect an afu-tlx command and data.\n%s", afu_tlx_cmd_trans_q[0].sprint()), UVM_MEDIUM);
            afu_tlx_tran_port.write(afu_tlx_cmd_trans_q.pop_front());
        end
    end
    else begin
        c_afu_tlx_cmd_packet.sample();
        $cast(pre_afu_tlx_cmd_trans, afu_tlx_cmd_trans_q[0].clone()); 
        `uvm_info(tID, $sformatf("Collect an afu-tlx command.\n%s", afu_tlx_cmd_trans_q[0].sprint()), UVM_MEDIUM);
        afu_tlx_tran_port.write(afu_tlx_cmd_trans_q.pop_front());
    end
endfunction