data/full_repos/permissive/187199324/stannel/UartRx.v
1: b'%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:4: Define or directive not defined: \'`ICE_STICK_CLOCK_RATE\'\n    parameter clockRate = `ICE_STICK_CLOCK_RATE,\n                          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:4: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter clockRate = `ICE_STICK_CLOCK_RATE,\n                                               ^\n%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:6: syntax error, unexpected \')\', expecting \';\'\n  ) (\n  ^\n%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:8: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire reset,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire rx,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:10: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg rcv,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:11: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[7:0] data\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:12: syntax error, unexpected \')\', expecting \',\' or \';\'\n  );\n  ^\n%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:24: syntax error, unexpected always\n  always @(posedge clk)\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:34: syntax error, unexpected always\n  always @(posedge clk)\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:43: syntax error, unexpected always\n  always @(posedge clk)\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/UartRx.v:61: syntax error, unexpected always\n  always @(posedge clk)\n  ^~~~~~\n%Error: Exiting due to 13 error(s)\n'
module UartRx #(
    parameter clockRate = `ICE_STICK_CLOCK_RATE,
    parameter baudRate = 115200
  ) (
    input wire clk,
    input wire reset,
    input wire rx,
    output reg rcv,
    output reg[7:0] data
  );

  localparam BAUD = clockRate / baudRate;
  wire clk_baud;
  reg rx_r;

  reg baud_enabled;
  reg clear;
  reg load;



  always @(posedge clk)
    rx_r <= rx;

  CounterSignal #(.Total(BAUD), .SignalValue(BAUD >> 1)) baud0 (
    .clk(clk),
    .enabled(baud_enabled),
    .signal(clk_baud)
  );

  reg [3:0] counter;
  always @(posedge clk)
    if (clear)
      counter <= 0;
    else if (clk_baud == 1)
      counter <= counter + 1;



  reg[9:0] raw_data;
  always @(posedge clk)
    if (clk_baud == 1)
      raw_data <= { rx_r, raw_data[9:1] };


  always @(posedge clk)
    if (reset == 0)
      data <= 0;
    else if (load)
      data <= raw_data[8:1];


  localparam IDLE = 2'd0;
  localparam RECV = 2'd1;
  localparam LOAD = 2'd2;
  localparam DONE = 2'd3;
  reg[1:0] state;

  always @(posedge clk)
    if (reset == 0)
      state <= IDLE;
    else
      case (state)
        IDLE:
          state <= rx_r == 0 ? RECV : IDLE;
        RECV:
          state <= counter == 10 ? LOAD : RECV;
        LOAD:
          state <= DONE;
        DONE:
          state <= IDLE;
        default:
          state <= IDLE;
      endcase
  always @ *
    begin
      baud_enabled = state == RECV ? 1 : 0;
      clear        = state == IDLE ? 1 : 0;
      load         = state == LOAD ? 1 : 0;
      rcv          = state == DONE ? 1 : 0;
    end
endmodule
module UartRx #(
    parameter clockRate = `ICE_STICK_CLOCK_RATE,
    parameter baudRate = 115200
  ) (
    input wire clk,
    input wire reset,
    input wire rx,
    output reg rcv,
    output reg[7:0] data
  );


  localparam BAUD = clockRate / baudRate;
  wire clk_baud;
  reg rx_r;

  reg baud_enabled;
  reg clear;
  reg load;



  always @(posedge clk)
    rx_r <= rx;

  CounterSignal #(.Total(BAUD), .SignalValue(BAUD >> 1)) baud0 (
    .clk(clk),
    .enabled(baud_enabled),
    .signal(clk_baud)
  );

  reg [3:0] counter;
  always @(posedge clk)
    if (clear)
      counter <= 0;
    else if (clk_baud == 1)
      counter <= counter + 1;



  reg[9:0] raw_data;
  always @(posedge clk)
    if (clk_baud == 1)
      raw_data <= { rx_r, raw_data[9:1] };


  always @(posedge clk)
    if (reset == 0)
      data <= 0;
    else if (load)
      data <= raw_data[8:1];


  localparam IDLE = 2'd0;
  localparam RECV = 2'd1;
  localparam LOAD = 2'd2;
  localparam DONE = 2'd3;
  reg[1:0] state;

  always @(posedge clk)
    if (reset == 0)
      state <= IDLE;
    else
      case (state)
        IDLE:
          state <= rx_r == 0 ? RECV : IDLE;
        RECV:
          state <= counter == 10 ? LOAD : RECV;
        LOAD:
          state <= DONE;
        DONE:
          state <= IDLE;
        default:
          state <= IDLE;
      endcase
  always @ *
    begin
      baud_enabled = state == RECV ? 1 : 0;
      clear        = state == IDLE ? 1 : 0;
      load         = state == LOAD ? 1 : 0;
      rcv          = state == DONE ? 1 : 0;
    end
endmodule