data/full_repos/permissive/19478345/cross_bar/cross_bar_tb.v
 line:28: before: "for"
1: b'%Warning-STMTDLY: data/full_repos/permissive/19478345/cross_bar/cross_bar_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19478345/cross_bar/cross_bar_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #31 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/cross_bar/cross_bar_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n            #10 ;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/cross_bar/cross_bar_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10 for(i = 0; i < 1; i = i + 1) begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/cross_bar/cross_bar_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #200 $finish;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/19478345/cross_bar/cross_bar_tb.v:3: Little bit endian vector: MSB < LSB of bit range: 0:7\n    reg [0:7] wr_en;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/19478345/cross_bar/cross_bar_tb.v:5: Little bit endian vector: MSB < LSB of bit range: 0:7\n    wire [0:7] full;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/19478345/cross_bar/cross_bar_tb.v:6: Little bit endian vector: MSB < LSB of bit range: 0:7\n    wire [0:7] valid;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/19478345/cross_bar/cross_bar_tb.v:8: Little bit endian vector: MSB < LSB of bit range: 0:7\n    reg [0:7] stall;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/19478345/cross_bar/cross_bar_tb.v:9: Little bit endian vector: MSB < LSB of bit range: 0:7\n    wire [0:7] almost_full;\n         ^\n%Error: data/full_repos/permissive/19478345/cross_bar/cross_bar_tb.v:10: Cannot find file containing module: \'cross_bar\'\n    cross_bar #(8, 8)dut(rst, clk, wr_en, d, full, valid, q, stall, almost_full);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19478345/cross_bar,data/full_repos/permissive/19478345/cross_bar\n             data/full_repos/permissive/19478345/cross_bar,data/full_repos/permissive/19478345/cross_bar.v\n             data/full_repos/permissive/19478345/cross_bar,data/full_repos/permissive/19478345/cross_bar.sv\n             cross_bar\n             cross_bar.v\n             cross_bar.sv\n             obj_dir/cross_bar\n             obj_dir/cross_bar.v\n             obj_dir/cross_bar.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cross_bar_tb;
    reg rst, clk;
    reg [0:7] wr_en;
    reg [63:0] d;
    wire [0:7] full;
    wire [0:7] valid;
    wire [63:0] q;
    reg [0:7] stall;
    wire [0:7] almost_full;
    cross_bar #(8, 8)dut(rst, clk, wr_en, d, full, valid, q, stall, almost_full);

    wire [7:0] internal_q [0:7];

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end
    integer i, j, tmp;
    integer i2;


    initial begin
        rst = 1;
        wr_en = 0;
        d = 0;
        stall = 0;
        #31 rst = 0;
        #10 for(i = 0; i < 1; i = i + 1) begin
            wr_en = 0;
            d = d + 1;
            for(j = 0; j < 1; j = j + 1) begin
                if(!full[j])
                    wr_en[j] = 1;
            end
            #10 ;
        end
        wr_en = 0;
        d = 0;
        stall = 0;

        #200 $finish;
    end

    always @(posedge clk) begin
        for(i2 = 0; i2 < 8; i2 = i2 + 1) begin
            if(valid[i2])
                $display("valid: port:%d, time:%d, data:%b", i2, $time, q);
        end
    end
endmodule
module cross_bar_tb;

    reg rst, clk;
    reg [0:7] wr_en;
    reg [63:0] d;
    wire [0:7] full;
    wire [0:7] valid;
    wire [63:0] q;
    reg [0:7] stall;
    wire [0:7] almost_full;
    cross_bar #(8, 8)dut(rst, clk, wr_en, d, full, valid, q, stall, almost_full);

    wire [7:0] internal_q [0:7];

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end
    integer i, j, tmp;
    integer i2;


    initial begin
        rst = 1;
        wr_en = 0;
        d = 0;
        stall = 0;
        #31 rst = 0;
        #10 for(i = 0; i < 1; i = i + 1) begin
            wr_en = 0;
            d = d + 1;
            for(j = 0; j < 1; j = j + 1) begin
                if(!full[j])
                    wr_en[j] = 1;
            end
            #10 ;
        end
        wr_en = 0;
        d = 0;
        stall = 0;

        #200 $finish;
    end

    always @(posedge clk) begin
        for(i2 = 0; i2 < 8; i2 = i2 + 1) begin
            if(valid[i2])
                $display("valid: port:%d, time:%d, data:%b", i2, $time, q);
        end
    end
endmodule