data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v
1: b'%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:2: Cannot find include file: def.v\n`include "def.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.v\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.sv\n             def.v\n             def.v.v\n             def.v.sv\n             obj_dir/def.v\n             obj_dir/def.v.v\n             obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:67: Define or directive not defined: \'`True\'\n  if (rst == `True) begin\n             ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:67: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if (rst == `True) begin\n                  ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:70: Define or directive not defined: \'`False\'\n                                                                             : ... Suggested alternative: \'`else\'\n   wrIs_o    <= `False;\n                ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:70: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   wrIs_o    <= `False;\n                      ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:82: Define or directive not defined: \'`False\'\n                                                                             : ... Suggested alternative: \'`else\'\n   lk_o      <= `False;\n                ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:82: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   lk_o      <= `False;\n                      ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:83: Define or directive not defined: \'`True\'\n  end else if (stall != `True) begin\n                        ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:94: Define or directive not defined: \'`LUI\'\n   `LUI: begin\n   ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:94: syntax error, unexpected \':\', expecting endcase\n   `LUI: begin\n       ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:98: Define or directive not defined: \'`False\'\n                                                                             : ... Suggested alternative: \'`else\'\n    clear     <= `False;\n                 ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:100: Define or directive not defined: \'`AUIPC\'\n   `AUIPC: begin\n   ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:104: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n    clear     <= `False;\n                 ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:106: Define or directive not defined: \'`JAL\'\n   `JAL: begin\n   ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:108: Define or directive not defined: \'`True\'\n    wPcIs_o   <= `True;\n                 ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:110: Define or directive not defined: \'`True\'\n    clear     <= `True;\n                 ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:112: Define or directive not defined: \'`JALR\'\n   `JALR: begin\n   ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:114: Define or directive not defined: \'`True\'\n    wPcIs_o   <= `True;\n                 ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:116: Define or directive not defined: \'`True\'\n    clear     <= `True;\n                 ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:118: Define or directive not defined: \'`BRANCH\'\n   `BRANCH: begin\n   ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:120: Define or directive not defined: \'`BEQ\'\n    `BEQ:\n    ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:122: Define or directive not defined: \'`BNE\'\n    `BNE:\n    ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:124: Define or directive not defined: \'`BLT\'\n    `BLT:\n    ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:126: Define or directive not defined: \'`BGE\'\n    `BGE:\n    ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:128: Define or directive not defined: \'`BLTU\'\n    `BLTU:\n    ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:130: Define or directive not defined: \'`BGEU\'\n    `BGEU:\n    ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:135: Define or directive not defined: \'`DEBUG\'\n    if(`DEBUG == 1\'b1) $display("select jump? %d %d", rd0, rd1);\n       ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:137: syntax error, unexpected <=, expecting IDENTIFIER\n     wPcIs_o   <= `True;\n               ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:137: Define or directive not defined: \'`True\'\n     wPcIs_o   <= `True;\n                  ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:139: Define or directive not defined: \'`True\'\n     clear     <= `True;\n                  ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:141: Define or directive not defined: \'`DEBUG\'\n     if(`DEBUG == 1\'b1) $display("no jump!");\n        ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:141: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\n     if(`DEBUG == 1\'b1) $display("no jump!");\n               ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:142: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n     wPcIs_o   <= `False;\n                  ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:144: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n     clear     <= `False;\n                  ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:148: Define or directive not defined: \'`LOAD\'\n   `LOAD: begin\n   ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:151: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n    clear     <= `False;\n                 ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:153: Define or directive not defined: \'`DEBUG\'\n    if(`DEBUG == 1\'b1) $display("[MEM]LOAD Addr:%d %d", rd0, imm);\n       ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:153: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\n    if(`DEBUG == 1\'b1) $display("[MEM]LOAD Addr:%d %d", rd0, imm);\n              ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:155: Define or directive not defined: \'`STORE\'\n   `STORE: begin\n   ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:158: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n    clear     <= `False;\n                 ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:161: Define or directive not defined: \'`OP_IMM\'\n   `OP_IMM: begin\n   ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:164: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n    clear     <= `False;\n                 ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:166: Define or directive not defined: \'`ADDI\'\n    `ADDI: begin\n    ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:166: syntax error, unexpected \':\', expecting endcase\n    `ADDI: begin\n         ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:169: Define or directive not defined: \'`SLTI\'\n    `SLTI: begin\n    ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:172: Define or directive not defined: \'`SLTIU\'\n    `SLTIU: begin \n    ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:175: Define or directive not defined: \'`XORI\'\n    `XORI: begin\n    ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:178: Define or directive not defined: \'`ORI\'\n    `ORI: begin\n    ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:181: Define or directive not defined: \'`ANDI\'\n    `ANDI: begin\n    ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:184: Define or directive not defined: \'`SLLI\'\n    `SLLI: begin\n    ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module CPU_EX(
	clk, rst, state, stall,

	i_id, i_id_o,

	wrIs, wr,
	opCode, opType,
	rd0, rd1, imm,

	wrIs_o, wr_o, wrData_o,
	wPcIs_o, wPcData_o,
	opCode_o, opType_o,
	rd0_o, rd1_o, imm_o,

	clear,
	lk_o

	);
	input wire clk, rst, state, stall;

	input wire [31 : 0] i_id;
	output reg [31 : 0] i_id_o;

	input wire 			wrIs;
	input wire [ 4 : 0] wr;
	input wire [ 6 : 0] opCode;
	input wire [ 2 : 0] opType;
	input wire [31 : 0] rd0, rd1, imm;

	output reg          wrIs_o;
	output reg [ 4 : 0] wr_o;
	output reg [31 : 0] wrData_o;
	output reg 			wPcIs_o;
	output reg [31 : 0]	wPcData_o;
	output reg [ 6 : 0] opCode_o;
	output reg [ 2 : 0] opType_o;
	output reg [31 : 0] rd0_o, rd1_o, imm_o;

	output reg clear, lk_o;

	reg tmp0, tmp1, tmpOut, jumpFlag;



	always @( * ) begin
		if (rst == `True) begin
			i_id_o    <= 5'b0;

			wrIs_o    <= `False;
			wr_o      <= 4'b0;
			wrData_o  <= 32'b0;
			opCode_o  <= 7'b0;
			opType_o  <= 3'b0;
			rd0_o     <= 32'b0;
			rd1_o     <= 32'b0;
			imm_o     <= 32'b0;
			wPcIs_o   <= 1'b0;
			wPcData_o <= 32'b0;

			clear     <= 1'b0;
			lk_o      <= `False;
		end	else if (stall != `True) begin
			i_id_o   <= i_id;
			opCode_o <= opCode;
			opType_o <= opType;
			wrIs_o   <= wrIs;
			wr_o     <= wr;
			rd0_o    <= rd0;
			rd1_o    <= rd1;
			imm_o    <= imm;

			case (opCode)
			`LUI: begin
				wrData_o  <= imm;
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear     <= `False;
			end
			`AUIPC: begin
				wrData_o  <= i_id + imm;
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear     <= `False;
			end
			`JAL: begin
				wrData_o  <= i_id + 4;
				wPcIs_o   <= `True;
				wPcData_o <= imm + i_id;
				clear     <= `True;
			end
			`JALR: begin
				wrData_o  <= i_id + 4;
				wPcIs_o   <= `True;
				wPcData_o <= (rd0 + imm) & (-1 ^ 1);
				clear     <= `True;
			end
			`BRANCH: begin
				case (opType)
				`BEQ:
					jumpFlag = (rd0 == rd1) ? 1'b1 : 1'b0;
				`BNE:
					jumpFlag = (rd0 != rd1) ? 1'b1 : 1'b0;
				`BLT:
					jumpFlag = ($signed(rd0) < $signed(rd1)) ? 1'b1 : 1'b0;
				`BGE:
					jumpFlag = ($signed(rd0) >= $signed(rd1)) ? 1'b1 : 1'b0;
				`BLTU:
					jumpFlag = ($unsigned(rd0) < $unsigned(rd1)) ? 1'b1 : 1'b0;
				`BGEU:
					jumpFlag = ($unsigned(rd0) >= $unsigned(rd1)) ? 1'b1 : 1'b0;
				default:
					jumpFlag = 1'b0;
				endcase
				if(`DEBUG == 1'b1)	$display("select jump? %d %d", rd0, rd1);
				if (jumpFlag == 1'b1) begin
					wPcIs_o   <= `True;
					wPcData_o <= i_id + imm;
					clear     <= `True;
				end else begin
					if(`DEBUG == 1'b1)	$display("no jump!");
					wPcIs_o   <= `False;
					wPcData_o <= i_id + 4;
					clear     <= `False;
				end
			end

			`LOAD: begin
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear     <= `False;
				wrData_o  <= rd0 + imm;
				if(`DEBUG == 1'b1)	$display("[MEM]LOAD Addr:%d %d", rd0, imm);
			end
			`STORE: begin
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear     <= `False;
				wrData_o  <= rd0 + imm;
			end
			`OP_IMM: begin
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear     <= `False;
				case (opType)
				`ADDI: begin
					wrData_o <= rd0 + rd1;
				end
				`SLTI: begin
					wrData_o <= $signed(rd0) < $signed(rd1) ? 32'b1 : 32'b0;
				end
				`SLTIU: begin
					wrData_o <= $unsigned(rd0) < $unsigned(rd1) ? 32'b1 : 32'b0;
				end
				`XORI: begin
					wrData_o <= rd0 ^ rd1;
				end
				`ORI: begin
					wrData_o <= rd0 | rd1;
				end
				`ANDI: begin
					wrData_o <= rd0 & rd1;
				end
				`SLLI: begin
					wrData_o <= rd0 << rd1[4:0];
				end
				`SRLI: begin
					if (imm[10] == 0)

						wrData_o <= rd0 >> rd1[4:0];
					else

						wrData_o <= (rd0 >> rd1[4:0]) | ({32{rd0[31]}} << (6'd32 - {1'b0, rd1[4:0]}));
				end
				default: ;
				endcase
			end
			`OP: begin
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear <= `False;
				case (opType)
				`ADD: begin
					if (imm[5] == 0)

						wrData_o <= rd0 + rd1;
					else

						wrData_o <= rd0 - rd1;
				end
				`SLT: begin
					wrData_o <= $signed(rd0) < $signed(rd1) ? 32'b1 : 32'b0;
				end
				`SLTU: begin
					wrData_o <= $unsigned(rd0) < $unsigned(rd1) ? 32'b1 : 32'b0;
				end
				`XOR: begin
					wrData_o <= rd0 ^ rd1;
				end
				`SLL: begin
					wrData_o <= rd0 << rd1[4:0];
				end
				`SRL: begin
					if (imm[5] == 0)

						wrData_o <= rd0 >> rd1[4:0];
					else

						wrData_o <= (rd0 >> rd1[4:0]) | ({32{rd0[31]}} << (6'd32 - {1'b0, rd1[4:0]}));
				end
				`OR: begin
					wrData_o <= rd0 | rd1;
				end
				`AND: begin
					wrData_o <= rd0 & rd1;
				end
				default: ;
				endcase
			end
			`MISC_MEM: begin
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear <= `False;

			end
			default: ;
			endcase
			if (opCode != `LOAD)
				lk_o = `False;
			else
				lk_o = `True;
		end
	end

endmodule
module CPU_EX(
	clk, rst, state, stall,

	i_id, i_id_o,

	wrIs, wr,
	opCode, opType,
	rd0, rd1, imm,

	wrIs_o, wr_o, wrData_o,
	wPcIs_o, wPcData_o,
	opCode_o, opType_o,
	rd0_o, rd1_o, imm_o,

	clear,
	lk_o

	);

	input wire clk, rst, state, stall;

	input wire [31 : 0] i_id;
	output reg [31 : 0] i_id_o;

	input wire 			wrIs;
	input wire [ 4 : 0] wr;
	input wire [ 6 : 0] opCode;
	input wire [ 2 : 0] opType;
	input wire [31 : 0] rd0, rd1, imm;

	output reg          wrIs_o;
	output reg [ 4 : 0] wr_o;
	output reg [31 : 0] wrData_o;
	output reg 			wPcIs_o;
	output reg [31 : 0]	wPcData_o;
	output reg [ 6 : 0] opCode_o;
	output reg [ 2 : 0] opType_o;
	output reg [31 : 0] rd0_o, rd1_o, imm_o;

	output reg clear, lk_o;

	reg tmp0, tmp1, tmpOut, jumpFlag;



	always @( * ) begin
		if (rst == `True) begin
			i_id_o    <= 5'b0;

			wrIs_o    <= `False;
			wr_o      <= 4'b0;
			wrData_o  <= 32'b0;
			opCode_o  <= 7'b0;
			opType_o  <= 3'b0;
			rd0_o     <= 32'b0;
			rd1_o     <= 32'b0;
			imm_o     <= 32'b0;
			wPcIs_o   <= 1'b0;
			wPcData_o <= 32'b0;

			clear     <= 1'b0;
			lk_o      <= `False;
		end	else if (stall != `True) begin
			i_id_o   <= i_id;
			opCode_o <= opCode;
			opType_o <= opType;
			wrIs_o   <= wrIs;
			wr_o     <= wr;
			rd0_o    <= rd0;
			rd1_o    <= rd1;
			imm_o    <= imm;

			case (opCode)
			`LUI: begin
				wrData_o  <= imm;
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear     <= `False;
			end
			`AUIPC: begin
				wrData_o  <= i_id + imm;
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear     <= `False;
			end
			`JAL: begin
				wrData_o  <= i_id + 4;
				wPcIs_o   <= `True;
				wPcData_o <= imm + i_id;
				clear     <= `True;
			end
			`JALR: begin
				wrData_o  <= i_id + 4;
				wPcIs_o   <= `True;
				wPcData_o <= (rd0 + imm) & (-1 ^ 1);
				clear     <= `True;
			end
			`BRANCH: begin
				case (opType)
				`BEQ:
					jumpFlag = (rd0 == rd1) ? 1'b1 : 1'b0;
				`BNE:
					jumpFlag = (rd0 != rd1) ? 1'b1 : 1'b0;
				`BLT:
					jumpFlag = ($signed(rd0) < $signed(rd1)) ? 1'b1 : 1'b0;
				`BGE:
					jumpFlag = ($signed(rd0) >= $signed(rd1)) ? 1'b1 : 1'b0;
				`BLTU:
					jumpFlag = ($unsigned(rd0) < $unsigned(rd1)) ? 1'b1 : 1'b0;
				`BGEU:
					jumpFlag = ($unsigned(rd0) >= $unsigned(rd1)) ? 1'b1 : 1'b0;
				default:
					jumpFlag = 1'b0;
				endcase
				if(`DEBUG == 1'b1)	$display("select jump? %d %d", rd0, rd1);
				if (jumpFlag == 1'b1) begin
					wPcIs_o   <= `True;
					wPcData_o <= i_id + imm;
					clear     <= `True;
				end else begin
					if(`DEBUG == 1'b1)	$display("no jump!");
					wPcIs_o   <= `False;
					wPcData_o <= i_id + 4;
					clear     <= `False;
				end
			end

			`LOAD: begin
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear     <= `False;
				wrData_o  <= rd0 + imm;
				if(`DEBUG == 1'b1)	$display("[MEM]LOAD Addr:%d %d", rd0, imm);
			end
			`STORE: begin
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear     <= `False;
				wrData_o  <= rd0 + imm;
			end
			`OP_IMM: begin
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear     <= `False;
				case (opType)
				`ADDI: begin
					wrData_o <= rd0 + rd1;
				end
				`SLTI: begin
					wrData_o <= $signed(rd0) < $signed(rd1) ? 32'b1 : 32'b0;
				end
				`SLTIU: begin
					wrData_o <= $unsigned(rd0) < $unsigned(rd1) ? 32'b1 : 32'b0;
				end
				`XORI: begin
					wrData_o <= rd0 ^ rd1;
				end
				`ORI: begin
					wrData_o <= rd0 | rd1;
				end
				`ANDI: begin
					wrData_o <= rd0 & rd1;
				end
				`SLLI: begin
					wrData_o <= rd0 << rd1[4:0];
				end
				`SRLI: begin
					if (imm[10] == 0)

						wrData_o <= rd0 >> rd1[4:0];
					else

						wrData_o <= (rd0 >> rd1[4:0]) | ({32{rd0[31]}} << (6'd32 - {1'b0, rd1[4:0]}));
				end
				default: ;
				endcase
			end
			`OP: begin
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear <= `False;
				case (opType)
				`ADD: begin
					if (imm[5] == 0)

						wrData_o <= rd0 + rd1;
					else

						wrData_o <= rd0 - rd1;
				end
				`SLT: begin
					wrData_o <= $signed(rd0) < $signed(rd1) ? 32'b1 : 32'b0;
				end
				`SLTU: begin
					wrData_o <= $unsigned(rd0) < $unsigned(rd1) ? 32'b1 : 32'b0;
				end
				`XOR: begin
					wrData_o <= rd0 ^ rd1;
				end
				`SLL: begin
					wrData_o <= rd0 << rd1[4:0];
				end
				`SRL: begin
					if (imm[5] == 0)

						wrData_o <= rd0 >> rd1[4:0];
					else

						wrData_o <= (rd0 >> rd1[4:0]) | ({32{rd0[31]}} << (6'd32 - {1'b0, rd1[4:0]}));
				end
				`OR: begin
					wrData_o <= rd0 | rd1;
				end
				`AND: begin
					wrData_o <= rd0 & rd1;
				end
				default: ;
				endcase
			end
			`MISC_MEM: begin
				wPcIs_o   <= 1'b0;
				wPcData_o <= 32'b0;
				clear <= `False;

			end
			default: ;
			endcase
			if (opCode != `LOAD)
				lk_o = `False;
			else
				lk_o = `True;
		end
	end

endmodule