data/full_repos/permissive/189158922/verilog_src/lj92_pipeline_fifo.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/lj92_pipeline_fifo.v:351: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance top.fifo.unbuffered\n  assign \\$10  = produce == (* src = "nmigen/lib/fifo.py:102" *) 1\'h0;\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/lj92_pipeline_fifo.v:371: Operator NEQ expects 7 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance top.fifo.unbuffered\n  assign \\$4  = level != (* src = "nmigen/lib/fifo.py:145" *) 1\'h0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/lj92_pipeline_fifo.v:67: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'readable\' generates 1 bits.\n                                                                                        : ... In instance top.fifo\n  assign \\$7  = unbuffered_level + (* src = "nmigen/lib/fifo.py:263" *) readable;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/lj92_pipeline_fifo.v:192: Operator GTE expects 8 bits on the RHS, but RHS\'s CONST \'7\'h76\' generates 7 bits.\n                                                                                         : ... In instance top\n  assign \\$1  = fifo_level >= (* src = "lj92_pipeline_fifo.py:99" *) 7\'h76;\n                           ^~\n%Error: Exiting due to 4 warning(s)\n'
module top(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, enc_out, enc_out_ctr, out_end, valid_out, close_full, valid_in);
  wire \$1 ;
  (* src = "lj92_pipeline_fifo.py:67" *)
  reg \$next\close_full ;
  (* src = "lj92_pipeline_fifo.py:60" *)
  reg [61:0] \$next\enc_out ;
  (* src = "lj92_pipeline_fifo.py:61" *)
  reg [5:0] \$next\enc_out_ctr ;
  (* src = "nmigen/lib/fifo.py:65" *)
  reg [68:0] \$next\fifo_din ;
  (* src = "nmigen/lib/fifo.py:71" *)
  reg \$next\fifo_re ;
  (* src = "nmigen/lib/fifo.py:67" *)
  reg \$next\fifo_we ;
  (* src = "lj92_pipeline_fifo.py:62" *)
  reg \$next\out_end ;
  (* src = "lj92_pipeline_fifo.py:63" *)
  reg \$next\valid_out ;
  (* src = "nmigen/hdl/mem.py:97" *)
  input clk;
  (* init = 1'h0 *)
  (* src = "lj92_pipeline_fifo.py:67" *)
  output close_full;
  reg close_full = 1'h0;
  (* src = "lj92_pipeline_fifo.py:54" *)
  input [61:0] enc_in;
  (* src = "lj92_pipeline_fifo.py:55" *)
  input [5:0] enc_in_ctr;
  (* src = "lj92_pipeline_fifo.py:60" *)
  output [61:0] enc_out;
  (* src = "lj92_pipeline_fifo.py:61" *)
  output [5:0] enc_out_ctr;
  (* src = "nmigen/lib/fifo.py:65" *)
  wire [68:0] fifo_din;
  (* src = "nmigen/lib/fifo.py:69" *)
  wire [68:0] fifo_dout;
  (* src = "nmigen/lib/fifo.py:238" *)
  wire [7:0] fifo_level;
  (* src = "nmigen/lib/fifo.py:71" *)
  wire fifo_re;
  (* src = "nmigen/lib/fifo.py:70" *)
  wire fifo_readable;
  (* src = "nmigen/lib/fifo.py:67" *)
  wire fifo_we;
  (* src = "lj92_pipeline_fifo.py:56" *)
  input in_end;
  (* src = "lj92_pipeline_fifo.py:59" *)
  input latch_output;
  (* src = "lj92_pipeline_fifo.py:62" *)
  output out_end;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "lj92_pipeline_fifo.py:57" *)
  input valid_in;
  (* src = "lj92_pipeline_fifo.py:63" *)
  output valid_out;
  assign \$1  = fifo_level >= (* src = "lj92_pipeline_fifo.py:99" *) 7'h76;
  always @(posedge clk)
      close_full <= \$next\close_full ;
  fifo fifo (
    .clk(clk),
    .din(fifo_din),
    .dout(fifo_dout),
    .level(fifo_level),
    .re(fifo_re),
    .readable(fifo_readable),
    .rst(rst),
    .we(fifo_we)
  );
  always @* begin
    \$next\fifo_we  = 1'h0;
    \$next\fifo_we  = valid_in;
  end
  always @* begin
    \$next\fifo_din  = 69'h000000000000000000;
    \$next\fifo_din  = { in_end, enc_in_ctr, enc_in };
  end
  always @* begin
    \$next\valid_out  = 1'h0;
    \$next\valid_out  = fifo_readable;
  end
  always @* begin
    \$next\enc_out  = 62'h0000000000000000;
    \$next\enc_out  = fifo_dout[61:0];
  end
  always @* begin
    \$next\enc_out_ctr  = 6'h00;
    \$next\enc_out_ctr  = fifo_dout[67:62];
  end
  always @* begin
    \$next\out_end  = 1'h0;
    \$next\out_end  = fifo_dout[68];
  end
  always @* begin
    \$next\fifo_re  = 1'h0;
    \$next\fifo_re  = latch_output;
  end
  always @* begin
    \$next\close_full  = close_full;
    \$next\close_full  = \$1 ;
    casez (rst)
      1'h1:
          \$next\close_full  = 1'h0;
    endcase
  end
  assign fifo_re = \$next\fifo_re ;
  assign out_end = \$next\out_end ;
  assign enc_out_ctr = \$next\enc_out_ctr ;
  assign enc_out = \$next\enc_out ;
  assign valid_out = \$next\valid_out ;
  assign fifo_din = \$next\fifo_din ;
  assign fifo_we = \$next\fifo_we ;
endmodule
module top(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, enc_out, enc_out_ctr, out_end, valid_out, close_full, valid_in);

  wire \$1 ;
  (* src = "lj92_pipeline_fifo.py:67" *)
  reg \$next\close_full ;
  (* src = "lj92_pipeline_fifo.py:60" *)
  reg [61:0] \$next\enc_out ;
  (* src = "lj92_pipeline_fifo.py:61" *)
  reg [5:0] \$next\enc_out_ctr ;
  (* src = "nmigen/lib/fifo.py:65" *)
  reg [68:0] \$next\fifo_din ;
  (* src = "nmigen/lib/fifo.py:71" *)
  reg \$next\fifo_re ;
  (* src = "nmigen/lib/fifo.py:67" *)
  reg \$next\fifo_we ;
  (* src = "lj92_pipeline_fifo.py:62" *)
  reg \$next\out_end ;
  (* src = "lj92_pipeline_fifo.py:63" *)
  reg \$next\valid_out ;
  (* src = "nmigen/hdl/mem.py:97" *)
  input clk;
  (* init = 1'h0 *)
  (* src = "lj92_pipeline_fifo.py:67" *)
  output close_full;
  reg close_full = 1'h0;
  (* src = "lj92_pipeline_fifo.py:54" *)
  input [61:0] enc_in;
  (* src = "lj92_pipeline_fifo.py:55" *)
  input [5:0] enc_in_ctr;
  (* src = "lj92_pipeline_fifo.py:60" *)
  output [61:0] enc_out;
  (* src = "lj92_pipeline_fifo.py:61" *)
  output [5:0] enc_out_ctr;
  (* src = "nmigen/lib/fifo.py:65" *)
  wire [68:0] fifo_din;
  (* src = "nmigen/lib/fifo.py:69" *)
  wire [68:0] fifo_dout;
  (* src = "nmigen/lib/fifo.py:238" *)
  wire [7:0] fifo_level;
  (* src = "nmigen/lib/fifo.py:71" *)
  wire fifo_re;
  (* src = "nmigen/lib/fifo.py:70" *)
  wire fifo_readable;
  (* src = "nmigen/lib/fifo.py:67" *)
  wire fifo_we;
  (* src = "lj92_pipeline_fifo.py:56" *)
  input in_end;
  (* src = "lj92_pipeline_fifo.py:59" *)
  input latch_output;
  (* src = "lj92_pipeline_fifo.py:62" *)
  output out_end;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "lj92_pipeline_fifo.py:57" *)
  input valid_in;
  (* src = "lj92_pipeline_fifo.py:63" *)
  output valid_out;
  assign \$1  = fifo_level >= (* src = "lj92_pipeline_fifo.py:99" *) 7'h76;
  always @(posedge clk)
      close_full <= \$next\close_full ;
  fifo fifo (
    .clk(clk),
    .din(fifo_din),
    .dout(fifo_dout),
    .level(fifo_level),
    .re(fifo_re),
    .readable(fifo_readable),
    .rst(rst),
    .we(fifo_we)
  );
  always @* begin
    \$next\fifo_we  = 1'h0;
    \$next\fifo_we  = valid_in;
  end
  always @* begin
    \$next\fifo_din  = 69'h000000000000000000;
    \$next\fifo_din  = { in_end, enc_in_ctr, enc_in };
  end
  always @* begin
    \$next\valid_out  = 1'h0;
    \$next\valid_out  = fifo_readable;
  end
  always @* begin
    \$next\enc_out  = 62'h0000000000000000;
    \$next\enc_out  = fifo_dout[61:0];
  end
  always @* begin
    \$next\enc_out_ctr  = 6'h00;
    \$next\enc_out_ctr  = fifo_dout[67:62];
  end
  always @* begin
    \$next\out_end  = 1'h0;
    \$next\out_end  = fifo_dout[68];
  end
  always @* begin
    \$next\fifo_re  = 1'h0;
    \$next\fifo_re  = latch_output;
  end
  always @* begin
    \$next\close_full  = close_full;
    \$next\close_full  = \$1 ;
    casez (rst)
      1'h1:
          \$next\close_full  = 1'h0;
    endcase
  end
  assign fifo_re = \$next\fifo_re ;
  assign out_end = \$next\out_end ;
  assign enc_out_ctr = \$next\enc_out_ctr ;
  assign enc_out = \$next\enc_out ;
  assign valid_out = \$next\valid_out ;
  assign fifo_din = \$next\fifo_din ;
  assign fifo_we = \$next\fifo_we ;
endmodule