data/full_repos/permissive/168753118/rtl/misc/MUX_A.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_A.v:34: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_A\n    1'b0: data_wire = a_data_src_in;\n          ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/misc/MUX_A.v:35: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_wire'\n                                                                            : ... In instance MUX_A\n    1'b1: data_wire = b_data_src_in;\n          ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module MUX_A
  #(parameter DATA_WIDTH = 32) (

    input data_sel_in,


    input [DATA_WIDTH-1:0] a_data_src_in,
    input [DATA_WIDTH-1:0] b_data_src_in,


    output [DATA_WIDTH-1:0] data_out
  );

wire [DATA_WIDTH-1:0] data_wire;

always @ (*) begin
  case(data_sel_in)
    1'b0: data_wire = a_data_src_in;
    1'b1: data_wire = b_data_src_in;
  endcase
end

assign data_out = data_wire;

endmodule
module MUX_A
  #(parameter DATA_WIDTH = 32) (

    input data_sel_in,


    input [DATA_WIDTH-1:0] a_data_src_in,
    input [DATA_WIDTH-1:0] b_data_src_in,


    output [DATA_WIDTH-1:0] data_out
  );


wire [DATA_WIDTH-1:0] data_wire;

always @ (*) begin
  case(data_sel_in)
    1'b0: data_wire = a_data_src_in;
    1'b1: data_wire = b_data_src_in;
  endcase
end

assign data_out = data_wire;

endmodule