data/full_repos/permissive/189158922/verilog_src/predictor_p1_c4_px4.v
data/verilator_xmls/e065ef44-c502-470f-ba95-f2526020e3f6.xml
module top(pixel_in, \pixel_in$1 , \pixel_in$2 , \pixel_in$3 , new_row, end_in, rst, clk, predic_out, \predic_out$4 , \predic_out$5 , \predic_out$6 , pixel_out, \pixel_out$7 , \pixel_out$8 , \pixel_out$9 , valid_out, end_out, valid_in);
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \$next\buff ;
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \$next\buff$11 ;
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \$next\buff$13 ;
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \$next\buff$15 ;
  (* src = "predictor_p1_c4_px4.py:80" *)
  reg \$next\end_out ;
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \$next\lbuff ;
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \$next\lbuff$10 ;
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \$next\lbuff$12 ;
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \$next\lbuff$14 ;
  (* src = "predictor_p1_c4_px4.py:69" *)
  reg [15:0] \$next\pixel_out ;
  (* src = "predictor_p1_c4_px4.py:69" *)
  reg [15:0] \$next\pixel_out$7 ;
  (* src = "predictor_p1_c4_px4.py:69" *)
  reg [15:0] \$next\pixel_out$8 ;
  (* src = "predictor_p1_c4_px4.py:69" *)
  reg [15:0] \$next\pixel_out$9 ;
  (* src = "predictor_p1_c4_px4.py:72" *)
  reg [15:0] \$next\predic_out ;
  (* src = "predictor_p1_c4_px4.py:72" *)
  reg [15:0] \$next\predic_out$4 ;
  (* src = "predictor_p1_c4_px4.py:72" *)
  reg [15:0] \$next\predic_out$5 ;
  (* src = "predictor_p1_c4_px4.py:72" *)
  reg [15:0] \$next\predic_out$6 ;
  (* src = "predictor_p1_c4_px4.py:76" *)
  reg \$next\valid_out ;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] buff = 16'h8000;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \buff$11  = 16'h8000;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \buff$13  = 16'h8000;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \buff$15  = 16'h8000;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* src = "predictor_p1_c4_px4.py:79" *)
  input end_in;
  (* init = 1'h0 *)
  (* src = "predictor_p1_c4_px4.py:80" *)
  output end_out;
  reg end_out = 1'h0;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] lbuff = 16'h8000;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \lbuff$10  = 16'h8000;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \lbuff$12  = 16'h8000;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \lbuff$14  = 16'h8000;
  (* src = "predictor_p1_c4_px4.py:66" *)
  input new_row;
  (* src = "predictor_p1_c4_px4.py:63" *)
  input [15:0] pixel_in;
  (* src = "predictor_p1_c4_px4.py:63" *)
  input [15:0] \pixel_in$1 ;
  (* src = "predictor_p1_c4_px4.py:63" *)
  input [15:0] \pixel_in$2 ;
  (* src = "predictor_p1_c4_px4.py:63" *)
  input [15:0] \pixel_in$3 ;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:69" *)
  output [15:0] pixel_out;
  reg [15:0] pixel_out = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:69" *)
  output [15:0] \pixel_out$7 ;
  reg [15:0] \pixel_out$7  = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:69" *)
  output [15:0] \pixel_out$8 ;
  reg [15:0] \pixel_out$8  = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:69" *)
  output [15:0] \pixel_out$9 ;
  reg [15:0] \pixel_out$9  = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:72" *)
  output [15:0] predic_out;
  reg [15:0] predic_out = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:72" *)
  output [15:0] \predic_out$4 ;
  reg [15:0] \predic_out$4  = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:72" *)
  output [15:0] \predic_out$5 ;
  reg [15:0] \predic_out$5  = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:72" *)
  output [15:0] \predic_out$6 ;
  reg [15:0] \predic_out$6  = 16'h0000;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "predictor_p1_c4_px4.py:75" *)
  input valid_in;
  (* init = 1'h0 *)
  (* src = "predictor_p1_c4_px4.py:76" *)
  output valid_out;
  reg valid_out = 1'h0;
  always @(posedge clk)
      end_out <= \$next\end_out ;
  always @(posedge clk)
      lbuff <= \$next\lbuff ;
  always @(posedge clk)
      \predic_out$6  <= \$next\predic_out$6 ;
  always @(posedge clk)
      \predic_out$5  <= \$next\predic_out$5 ;
  always @(posedge clk)
      \predic_out$4  <= \$next\predic_out$4 ;
  always @(posedge clk)
      predic_out <= \$next\predic_out ;
  always @(posedge clk)
      \pixel_out$9  <= \$next\pixel_out$9 ;
  always @(posedge clk)
      \pixel_out$8  <= \$next\pixel_out$8 ;
  always @(posedge clk)
      \pixel_out$7  <= \$next\pixel_out$7 ;
  always @(posedge clk)
      pixel_out <= \$next\pixel_out ;
  always @(posedge clk)
      valid_out <= \$next\valid_out ;
  always @(posedge clk)
      \buff$15  <= \$next\buff$15 ;
  always @(posedge clk)
      \buff$13  <= \$next\buff$13 ;
  always @(posedge clk)
      \buff$11  <= \$next\buff$11 ;
  always @(posedge clk)
      buff <= \$next\buff ;
  always @(posedge clk)
      \lbuff$14  <= \$next\lbuff$14 ;
  always @(posedge clk)
      \lbuff$12  <= \$next\lbuff$12 ;
  always @(posedge clk)
      \lbuff$10  <= \$next\lbuff$10 ;
  always @* begin
    \$next\pixel_out  = pixel_out;
    casez (valid_in)
      1'h1:
          \$next\pixel_out  = pixel_in;
    endcase
    casez (rst)
      1'h1:
          \$next\pixel_out  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\pixel_out$7  = \pixel_out$7 ;
    casez (valid_in)
      1'h1:
          \$next\pixel_out$7  = \pixel_in$1 ;
    endcase
    casez (rst)
      1'h1:
          \$next\pixel_out$7  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\lbuff$12  = \lbuff$12 ;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\lbuff$12  = \pixel_in$2 ;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\lbuff$12  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\lbuff$14  = \lbuff$14 ;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\lbuff$14  = \pixel_in$3 ;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\lbuff$14  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\buff  = buff;
    casez (valid_in)
      1'h1:
          \$next\buff  = pixel_in;
    endcase
    casez (rst)
      1'h1:
          \$next\buff  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\buff$11  = \buff$11 ;
    casez (valid_in)
      1'h1:
          \$next\buff$11  = \pixel_in$1 ;
    endcase
    casez (rst)
      1'h1:
          \$next\buff$11  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\buff$13  = \buff$13 ;
    casez (valid_in)
      1'h1:
          \$next\buff$13  = \pixel_in$2 ;
    endcase
    casez (rst)
      1'h1:
          \$next\buff$13  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\buff$15  = \buff$15 ;
    casez (valid_in)
      1'h1:
          \$next\buff$15  = \pixel_in$3 ;
    endcase
    casez (rst)
      1'h1:
          \$next\buff$15  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\valid_out  = valid_out;
    \$next\valid_out  = valid_in;
    casez (rst)
      1'h1:
          \$next\valid_out  = 1'h0;
    endcase
  end
  always @* begin
    \$next\end_out  = end_out;
    \$next\end_out  = end_in;
    casez (rst)
      1'h1:
          \$next\end_out  = 1'h0;
    endcase
  end
  always @* begin
    \$next\pixel_out$8  = \pixel_out$8 ;
    casez (valid_in)
      1'h1:
          \$next\pixel_out$8  = \pixel_in$2 ;
    endcase
    casez (rst)
      1'h1:
          \$next\pixel_out$8  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\pixel_out$9  = \pixel_out$9 ;
    casez (valid_in)
      1'h1:
          \$next\pixel_out$9  = \pixel_in$3 ;
    endcase
    casez (rst)
      1'h1:
          \$next\pixel_out$9  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\predic_out  = predic_out;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\predic_out  = lbuff;
            1'hz:
                \$next\predic_out  = buff;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\predic_out  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\predic_out$4  = \predic_out$4 ;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\predic_out$4  = \lbuff$10 ;
            1'hz:
                \$next\predic_out$4  = \buff$11 ;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\predic_out$4  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\predic_out$5  = \predic_out$5 ;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\predic_out$5  = \lbuff$12 ;
            1'hz:
                \$next\predic_out$5  = \buff$13 ;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\predic_out$5  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\predic_out$6  = \predic_out$6 ;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\predic_out$6  = \lbuff$14 ;
            1'hz:
                \$next\predic_out$6  = \buff$15 ;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\predic_out$6  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\lbuff  = lbuff;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\lbuff  = pixel_in;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\lbuff  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\lbuff$10  = \lbuff$10 ;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\lbuff$10  = \pixel_in$1 ;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\lbuff$10  = 16'h8000;
    endcase
  end
endmodule
module top(pixel_in, \pixel_in$1 , \pixel_in$2 , \pixel_in$3 , new_row, end_in, rst, clk, predic_out, \predic_out$4 , \predic_out$5 , \predic_out$6 , pixel_out, \pixel_out$7 , \pixel_out$8 , \pixel_out$9 , valid_out, end_out, valid_in);

  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \$next\buff ;
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \$next\buff$11 ;
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \$next\buff$13 ;
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \$next\buff$15 ;
  (* src = "predictor_p1_c4_px4.py:80" *)
  reg \$next\end_out ;
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \$next\lbuff ;
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \$next\lbuff$10 ;
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \$next\lbuff$12 ;
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \$next\lbuff$14 ;
  (* src = "predictor_p1_c4_px4.py:69" *)
  reg [15:0] \$next\pixel_out ;
  (* src = "predictor_p1_c4_px4.py:69" *)
  reg [15:0] \$next\pixel_out$7 ;
  (* src = "predictor_p1_c4_px4.py:69" *)
  reg [15:0] \$next\pixel_out$8 ;
  (* src = "predictor_p1_c4_px4.py:69" *)
  reg [15:0] \$next\pixel_out$9 ;
  (* src = "predictor_p1_c4_px4.py:72" *)
  reg [15:0] \$next\predic_out ;
  (* src = "predictor_p1_c4_px4.py:72" *)
  reg [15:0] \$next\predic_out$4 ;
  (* src = "predictor_p1_c4_px4.py:72" *)
  reg [15:0] \$next\predic_out$5 ;
  (* src = "predictor_p1_c4_px4.py:72" *)
  reg [15:0] \$next\predic_out$6 ;
  (* src = "predictor_p1_c4_px4.py:76" *)
  reg \$next\valid_out ;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] buff = 16'h8000;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \buff$11  = 16'h8000;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \buff$13  = 16'h8000;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:96" *)
  reg [15:0] \buff$15  = 16'h8000;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* src = "predictor_p1_c4_px4.py:79" *)
  input end_in;
  (* init = 1'h0 *)
  (* src = "predictor_p1_c4_px4.py:80" *)
  output end_out;
  reg end_out = 1'h0;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] lbuff = 16'h8000;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \lbuff$10  = 16'h8000;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \lbuff$12  = 16'h8000;
  (* init = 16'h8000 *)
  (* src = "predictor_p1_c4_px4.py:102" *)
  reg [15:0] \lbuff$14  = 16'h8000;
  (* src = "predictor_p1_c4_px4.py:66" *)
  input new_row;
  (* src = "predictor_p1_c4_px4.py:63" *)
  input [15:0] pixel_in;
  (* src = "predictor_p1_c4_px4.py:63" *)
  input [15:0] \pixel_in$1 ;
  (* src = "predictor_p1_c4_px4.py:63" *)
  input [15:0] \pixel_in$2 ;
  (* src = "predictor_p1_c4_px4.py:63" *)
  input [15:0] \pixel_in$3 ;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:69" *)
  output [15:0] pixel_out;
  reg [15:0] pixel_out = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:69" *)
  output [15:0] \pixel_out$7 ;
  reg [15:0] \pixel_out$7  = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:69" *)
  output [15:0] \pixel_out$8 ;
  reg [15:0] \pixel_out$8  = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:69" *)
  output [15:0] \pixel_out$9 ;
  reg [15:0] \pixel_out$9  = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:72" *)
  output [15:0] predic_out;
  reg [15:0] predic_out = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:72" *)
  output [15:0] \predic_out$4 ;
  reg [15:0] \predic_out$4  = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:72" *)
  output [15:0] \predic_out$5 ;
  reg [15:0] \predic_out$5  = 16'h0000;
  (* init = 16'h0000 *)
  (* src = "predictor_p1_c4_px4.py:72" *)
  output [15:0] \predic_out$6 ;
  reg [15:0] \predic_out$6  = 16'h0000;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "predictor_p1_c4_px4.py:75" *)
  input valid_in;
  (* init = 1'h0 *)
  (* src = "predictor_p1_c4_px4.py:76" *)
  output valid_out;
  reg valid_out = 1'h0;
  always @(posedge clk)
      end_out <= \$next\end_out ;
  always @(posedge clk)
      lbuff <= \$next\lbuff ;
  always @(posedge clk)
      \predic_out$6  <= \$next\predic_out$6 ;
  always @(posedge clk)
      \predic_out$5  <= \$next\predic_out$5 ;
  always @(posedge clk)
      \predic_out$4  <= \$next\predic_out$4 ;
  always @(posedge clk)
      predic_out <= \$next\predic_out ;
  always @(posedge clk)
      \pixel_out$9  <= \$next\pixel_out$9 ;
  always @(posedge clk)
      \pixel_out$8  <= \$next\pixel_out$8 ;
  always @(posedge clk)
      \pixel_out$7  <= \$next\pixel_out$7 ;
  always @(posedge clk)
      pixel_out <= \$next\pixel_out ;
  always @(posedge clk)
      valid_out <= \$next\valid_out ;
  always @(posedge clk)
      \buff$15  <= \$next\buff$15 ;
  always @(posedge clk)
      \buff$13  <= \$next\buff$13 ;
  always @(posedge clk)
      \buff$11  <= \$next\buff$11 ;
  always @(posedge clk)
      buff <= \$next\buff ;
  always @(posedge clk)
      \lbuff$14  <= \$next\lbuff$14 ;
  always @(posedge clk)
      \lbuff$12  <= \$next\lbuff$12 ;
  always @(posedge clk)
      \lbuff$10  <= \$next\lbuff$10 ;
  always @* begin
    \$next\pixel_out  = pixel_out;
    casez (valid_in)
      1'h1:
          \$next\pixel_out  = pixel_in;
    endcase
    casez (rst)
      1'h1:
          \$next\pixel_out  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\pixel_out$7  = \pixel_out$7 ;
    casez (valid_in)
      1'h1:
          \$next\pixel_out$7  = \pixel_in$1 ;
    endcase
    casez (rst)
      1'h1:
          \$next\pixel_out$7  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\lbuff$12  = \lbuff$12 ;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\lbuff$12  = \pixel_in$2 ;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\lbuff$12  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\lbuff$14  = \lbuff$14 ;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\lbuff$14  = \pixel_in$3 ;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\lbuff$14  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\buff  = buff;
    casez (valid_in)
      1'h1:
          \$next\buff  = pixel_in;
    endcase
    casez (rst)
      1'h1:
          \$next\buff  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\buff$11  = \buff$11 ;
    casez (valid_in)
      1'h1:
          \$next\buff$11  = \pixel_in$1 ;
    endcase
    casez (rst)
      1'h1:
          \$next\buff$11  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\buff$13  = \buff$13 ;
    casez (valid_in)
      1'h1:
          \$next\buff$13  = \pixel_in$2 ;
    endcase
    casez (rst)
      1'h1:
          \$next\buff$13  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\buff$15  = \buff$15 ;
    casez (valid_in)
      1'h1:
          \$next\buff$15  = \pixel_in$3 ;
    endcase
    casez (rst)
      1'h1:
          \$next\buff$15  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\valid_out  = valid_out;
    \$next\valid_out  = valid_in;
    casez (rst)
      1'h1:
          \$next\valid_out  = 1'h0;
    endcase
  end
  always @* begin
    \$next\end_out  = end_out;
    \$next\end_out  = end_in;
    casez (rst)
      1'h1:
          \$next\end_out  = 1'h0;
    endcase
  end
  always @* begin
    \$next\pixel_out$8  = \pixel_out$8 ;
    casez (valid_in)
      1'h1:
          \$next\pixel_out$8  = \pixel_in$2 ;
    endcase
    casez (rst)
      1'h1:
          \$next\pixel_out$8  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\pixel_out$9  = \pixel_out$9 ;
    casez (valid_in)
      1'h1:
          \$next\pixel_out$9  = \pixel_in$3 ;
    endcase
    casez (rst)
      1'h1:
          \$next\pixel_out$9  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\predic_out  = predic_out;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\predic_out  = lbuff;
            1'hz:
                \$next\predic_out  = buff;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\predic_out  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\predic_out$4  = \predic_out$4 ;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\predic_out$4  = \lbuff$10 ;
            1'hz:
                \$next\predic_out$4  = \buff$11 ;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\predic_out$4  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\predic_out$5  = \predic_out$5 ;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\predic_out$5  = \lbuff$12 ;
            1'hz:
                \$next\predic_out$5  = \buff$13 ;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\predic_out$5  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\predic_out$6  = \predic_out$6 ;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\predic_out$6  = \lbuff$14 ;
            1'hz:
                \$next\predic_out$6  = \buff$15 ;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\predic_out$6  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\lbuff  = lbuff;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\lbuff  = pixel_in;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\lbuff  = 16'h8000;
    endcase
  end
  always @* begin
    \$next\lbuff$10  = \lbuff$10 ;
    casez (valid_in)
      1'h1:
          casez (new_row)
            1'h1:
                \$next\lbuff$10  = \pixel_in$1 ;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\lbuff$10  = 16'h8000;
    endcase
  end
endmodule