data/full_repos/permissive/134057391/2018_cpu/code/rtl/pc.v
data/verilator_xmls/4510b604-fb55-4629-ba91-7f7de278e389.xml
module pc (
    input                  clk,
    input                  reset,
    output reg [3:0]       pc
    );

    always @(posedge clk)
        if (reset)
            pc <= 0;
        else
            pc <= pc + 1;
 
endmodule
module pc (
    input                  clk,
    input                  reset,
    output reg [3:0]       pc
    );


    always @(posedge clk)
        if (reset)
            pc <= 0;
        else
            pc <= pc + 1;
 
endmodule