data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sources_1/new/Multiplexer_Packet_Former.v
1: b"%Error: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sources_1/new/Multiplexer_Packet_Former.v:59: Cannot find file containing module: 'async_fifo'\n    async_fifo#(.DATADEPTH(256),.addresswidth(8)) camera1FIFO( .reset(reset),\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sources_1/new,data/full_repos/permissive/123043192/async_fifo\n             data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sources_1/new,data/full_repos/permissive/123043192/async_fifo.v\n             data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sources_1/new,data/full_repos/permissive/123043192/async_fifo.sv\n             async_fifo\n             async_fifo.v\n             async_fifo.sv\n             obj_dir/async_fifo\n             obj_dir/async_fifo.v\n             obj_dir/async_fifo.sv\n%Error: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sources_1/new/Multiplexer_Packet_Former.v:74: Cannot find file containing module: 'async_fifo'\n    async_fifo#(.DATADEPTH(256),.addresswidth(8)) camera2FIFO( .reset(reset),\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sources_1/new/Multiplexer_Packet_Former.v:89: Cannot find file containing module: 'async_fifo'\n    async_fifo#(.DATADEPTH(256),.addresswidth(8)) camera3FIFO( .reset(reset),\n    ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module Multiplexer_Packet_Former(

    output [7:0] packetData,
    output packetDataGood,
    output packetDataClk,
    input readData,
    

    input [7:0] camera1PixelData,
    input camera1PixelDataGood,
    input camera1PixelDataClk,
    

    input [7:0] camera2PixelData,
    input camera2PixelDataGood,
    input camera2PixelDataClk,
    

    input [7:0] camera3PixelData,
    input camera3PixelDataGood,
    input camera3PixelDataClk,
    
    input sys_clk,
    input reset
    );
    
    wire fifoReadClock;
    
    assign fifoReadClock = sys_clk;
    assign packetDataClk = fifoReadClock;
    

    reg camera1ReadData;
    wire [7:0] camera1Data;
    wire camera1FIFOFull;
    wire camera1FIFOEmpty;
    async_fifo#(.DATADEPTH(256),.addresswidth(8)) camera1FIFO( .reset(reset),
                            .write_clk(camera1PixelDataClk),
                            .write_en(camera1PixelDataGood),
                            .inputData(camera1PixelData),
                            .read_clk(fifoReadClock),
                            .read_en(camera1ReadData),
                            .outputData(camera1Data),
                            .full(camera1FIFOFull),
                            .empty(camera1FIFOEmpty));
    

    reg camera2ReadData;
    wire [7:0] camera2Data;
    wire camera2FIFOFull;
    wire camera2FIFOEmpty;
    async_fifo#(.DATADEPTH(256),.addresswidth(8)) camera2FIFO( .reset(reset),
                            .write_clk(camera2PixelDataClk),
                            .write_en(camera2PixelDataGood),
                            .inputData(camera2PixelData),
                            .read_clk(fifoReadClock),
                            .read_en(camera2ReadData),
                            .outputData(camera2Data),
                            .full(camera2FIFOFull),
                            .empty(camera2FIFOEmpty));
                            

    reg camera3ReadData;
    wire [7:0] camera3Data;
    wire camera3FIFOFull;
    wire camera3FIFOEmpty;
    async_fifo#(.DATADEPTH(256),.addresswidth(8)) camera3FIFO( .reset(reset),
                            .write_clk(camera3PixelDataClk),
                            .write_en(camera3PixelDataGood),
                            .inputData(camera3PixelData),
                            .read_clk(fifoReadClock),
                            .read_en(camera3ReadData),
                            .outputData(camera3Data),
                            .full(camera3FIFOFull),
                            .empty(camera3FIFOEmpty));      
                            
                            

    reg outputPacketWriteData;
    reg outputPacketReadData;
    reg [7:0] outputPacketData;
    wire outputPacketFIFOFull;
    reg outputPacketGood;
    

    assign packetDataGood = outputPacketGood;
    assign packetData = outputPacketData;                                                              
                                    
    reg[3:0] state;
    reg[3:0] nextState; 
    parameter IDLE = 0, READ_CAMERA_1 = 1, READ_CAMERA_2 = 2, READ_CAMERA_3 = 3, WAIT_CAMERA_1 = 4, WAIT_CAMERA_2 = 5, WAIT_CAMERA_3 = 6;
    
    always @(state) begin
        case(state)
            IDLE: begin
                outputPacketWriteData <= 0;
                outputPacketData <= 8'hAA;
            end
            
            READ_CAMERA_1: begin
                outputPacketWriteData <= 1;
                camera1ReadData <= 1;
                camera2ReadData <= 0;
                camera3ReadData <= 0;
                outputPacketData <= camera1Data;
                outputPacketGood <= 1;
            end
            
            READ_CAMERA_2: begin
                outputPacketWriteData <= 1;
                camera1ReadData <= 0;
                camera2ReadData <= 1;
                camera3ReadData <= 0;
                outputPacketData <= camera2Data;
                outputPacketGood <= 1;
            end
            
            READ_CAMERA_3: begin
                outputPacketWriteData <= 1;
                camera1ReadData <= 0;
                camera2ReadData <= 0;
                camera3ReadData <= 1;
                outputPacketData <= camera3Data;
                outputPacketGood <= 1;
            end
            
            WAIT_CAMERA_1: begin
                outputPacketWriteData <= 0;
                camera1ReadData <= 0;
                camera2ReadData <= 0;
                camera3ReadData <= 0;
                outputPacketData <= 8'h11;
                outputPacketGood <= 0;
            end
            
            WAIT_CAMERA_2: begin
                outputPacketWriteData <= 0;
                camera1ReadData <= 0;
                camera2ReadData <= 0;
                camera3ReadData <= 0;
                outputPacketData <= 8'h22;
                outputPacketGood <= 0;
            end 
            
            WAIT_CAMERA_3: begin
                outputPacketWriteData <= 0;
                camera1ReadData <= 0;
                camera2ReadData <= 0;
                camera3ReadData <= 0;
                outputPacketData <= 8'h33;
                outputPacketGood <= 0;
            end                                                               
        endcase
    end
    
    
    always@(posedge sys_clk) begin
        if(reset)
            state <= IDLE;
        if(readData) begin
            case(state)
                IDLE: begin
                    if(~camera1FIFOEmpty) begin
                        state <= READ_CAMERA_1;
                    end else begin
                        state <= IDLE;
                    end
                end
                
                READ_CAMERA_1: begin
                    if(~camera2FIFOEmpty) begin
                        state <= READ_CAMERA_2;
                    end else begin
                        state <= WAIT_CAMERA_2;
                    end
                end
                
                WAIT_CAMERA_2: begin
                    if(~camera2FIFOEmpty) begin
                        state <= READ_CAMERA_2;
                    end else begin
                        state <= WAIT_CAMERA_2;
                    end
                end
    
                READ_CAMERA_2: begin
                    if(~camera3FIFOEmpty) begin
                        state <= READ_CAMERA_3;
                    end else begin
                        state <= WAIT_CAMERA_3;
                    end
                end
                
                WAIT_CAMERA_3: begin
                    if(~camera3FIFOEmpty) begin
                        state <= READ_CAMERA_3;
                    end else begin
                        state <= WAIT_CAMERA_3;
                    end
                end
    
                READ_CAMERA_3: begin
                    if(~camera1FIFOEmpty) begin
                        state <= READ_CAMERA_1;
                    end else begin
                        state <= WAIT_CAMERA_1;
                    end
                end
                
                WAIT_CAMERA_1: begin
                    if(~camera1FIFOEmpty) begin
                        state <= READ_CAMERA_1;
                    end else begin
                        state <= WAIT_CAMERA_1;
                    end
                end
                
                default: begin
                    state <= IDLE;
                end
            endcase
        end
       
    end                                                                                                                       
    
    
    
    
endmodule
module Multiplexer_Packet_Former(

    output [7:0] packetData,
    output packetDataGood,
    output packetDataClk,
    input readData,
    

    input [7:0] camera1PixelData,
    input camera1PixelDataGood,
    input camera1PixelDataClk,
    

    input [7:0] camera2PixelData,
    input camera2PixelDataGood,
    input camera2PixelDataClk,
    

    input [7:0] camera3PixelData,
    input camera3PixelDataGood,
    input camera3PixelDataClk,
    
    input sys_clk,
    input reset
    );

    
    wire fifoReadClock;
    
    assign fifoReadClock = sys_clk;
    assign packetDataClk = fifoReadClock;
    

    reg camera1ReadData;
    wire [7:0] camera1Data;
    wire camera1FIFOFull;
    wire camera1FIFOEmpty;
    async_fifo#(.DATADEPTH(256),.addresswidth(8)) camera1FIFO( .reset(reset),
                            .write_clk(camera1PixelDataClk),
                            .write_en(camera1PixelDataGood),
                            .inputData(camera1PixelData),
                            .read_clk(fifoReadClock),
                            .read_en(camera1ReadData),
                            .outputData(camera1Data),
                            .full(camera1FIFOFull),
                            .empty(camera1FIFOEmpty));
    

    reg camera2ReadData;
    wire [7:0] camera2Data;
    wire camera2FIFOFull;
    wire camera2FIFOEmpty;
    async_fifo#(.DATADEPTH(256),.addresswidth(8)) camera2FIFO( .reset(reset),
                            .write_clk(camera2PixelDataClk),
                            .write_en(camera2PixelDataGood),
                            .inputData(camera2PixelData),
                            .read_clk(fifoReadClock),
                            .read_en(camera2ReadData),
                            .outputData(camera2Data),
                            .full(camera2FIFOFull),
                            .empty(camera2FIFOEmpty));
                            

    reg camera3ReadData;
    wire [7:0] camera3Data;
    wire camera3FIFOFull;
    wire camera3FIFOEmpty;
    async_fifo#(.DATADEPTH(256),.addresswidth(8)) camera3FIFO( .reset(reset),
                            .write_clk(camera3PixelDataClk),
                            .write_en(camera3PixelDataGood),
                            .inputData(camera3PixelData),
                            .read_clk(fifoReadClock),
                            .read_en(camera3ReadData),
                            .outputData(camera3Data),
                            .full(camera3FIFOFull),
                            .empty(camera3FIFOEmpty));      
                            
                            

    reg outputPacketWriteData;
    reg outputPacketReadData;
    reg [7:0] outputPacketData;
    wire outputPacketFIFOFull;
    reg outputPacketGood;
    

    assign packetDataGood = outputPacketGood;
    assign packetData = outputPacketData;                                                              
                                    
    reg[3:0] state;
    reg[3:0] nextState; 
    parameter IDLE = 0, READ_CAMERA_1 = 1, READ_CAMERA_2 = 2, READ_CAMERA_3 = 3, WAIT_CAMERA_1 = 4, WAIT_CAMERA_2 = 5, WAIT_CAMERA_3 = 6;
    
    always @(state) begin
        case(state)
            IDLE: begin
                outputPacketWriteData <= 0;
                outputPacketData <= 8'hAA;
            end
            
            READ_CAMERA_1: begin
                outputPacketWriteData <= 1;
                camera1ReadData <= 1;
                camera2ReadData <= 0;
                camera3ReadData <= 0;
                outputPacketData <= camera1Data;
                outputPacketGood <= 1;
            end
            
            READ_CAMERA_2: begin
                outputPacketWriteData <= 1;
                camera1ReadData <= 0;
                camera2ReadData <= 1;
                camera3ReadData <= 0;
                outputPacketData <= camera2Data;
                outputPacketGood <= 1;
            end
            
            READ_CAMERA_3: begin
                outputPacketWriteData <= 1;
                camera1ReadData <= 0;
                camera2ReadData <= 0;
                camera3ReadData <= 1;
                outputPacketData <= camera3Data;
                outputPacketGood <= 1;
            end
            
            WAIT_CAMERA_1: begin
                outputPacketWriteData <= 0;
                camera1ReadData <= 0;
                camera2ReadData <= 0;
                camera3ReadData <= 0;
                outputPacketData <= 8'h11;
                outputPacketGood <= 0;
            end
            
            WAIT_CAMERA_2: begin
                outputPacketWriteData <= 0;
                camera1ReadData <= 0;
                camera2ReadData <= 0;
                camera3ReadData <= 0;
                outputPacketData <= 8'h22;
                outputPacketGood <= 0;
            end 
            
            WAIT_CAMERA_3: begin
                outputPacketWriteData <= 0;
                camera1ReadData <= 0;
                camera2ReadData <= 0;
                camera3ReadData <= 0;
                outputPacketData <= 8'h33;
                outputPacketGood <= 0;
            end                                                               
        endcase
    end
    
    
    always@(posedge sys_clk) begin
        if(reset)
            state <= IDLE;
        if(readData) begin
            case(state)
                IDLE: begin
                    if(~camera1FIFOEmpty) begin
                        state <= READ_CAMERA_1;
                    end else begin
                        state <= IDLE;
                    end
                end
                
                READ_CAMERA_1: begin
                    if(~camera2FIFOEmpty) begin
                        state <= READ_CAMERA_2;
                    end else begin
                        state <= WAIT_CAMERA_2;
                    end
                end
                
                WAIT_CAMERA_2: begin
                    if(~camera2FIFOEmpty) begin
                        state <= READ_CAMERA_2;
                    end else begin
                        state <= WAIT_CAMERA_2;
                    end
                end
    
                READ_CAMERA_2: begin
                    if(~camera3FIFOEmpty) begin
                        state <= READ_CAMERA_3;
                    end else begin
                        state <= WAIT_CAMERA_3;
                    end
                end
                
                WAIT_CAMERA_3: begin
                    if(~camera3FIFOEmpty) begin
                        state <= READ_CAMERA_3;
                    end else begin
                        state <= WAIT_CAMERA_3;
                    end
                end
    
                READ_CAMERA_3: begin
                    if(~camera1FIFOEmpty) begin
                        state <= READ_CAMERA_1;
                    end else begin
                        state <= WAIT_CAMERA_1;
                    end
                end
                
                WAIT_CAMERA_1: begin
                    if(~camera1FIFOEmpty) begin
                        state <= READ_CAMERA_1;
                    end else begin
                        state <= WAIT_CAMERA_1;
                    end
                end
                
                default: begin
                    state <= IDLE;
                end
            endcase
        end
       
    end                                                                                                                       
    
    
    
    
endmodule