data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/axi_master/wburst_counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/axi_master/wburst_counter.v:22: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'write_count\' generates 16 bits.\n                                                                                                                         : ... In instance wburst_counter\n  assign burst_ready = ((write_count >= MAX_BURST_LEN));\n                                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/axi_master/wburst_counter.v:23: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'write_count\' generates 16 bits.\n                                                                                                                         : ... In instance wburst_counter\n  assign wburst_len = write_count >= MAX_BURST_LEN ? MAX_BURST_LEN - 1 :\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/axi_master/wburst_counter.v:24: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'write_count\' generates 16 bits.\n                                                                                                                         : ... In instance wburst_counter\n                      write_count != 0 ? write_count - 1 : 0;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/axi_master/wburst_counter.v:23: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                         : ... In instance wburst_counter\n  assign wburst_len = write_count >= MAX_BURST_LEN ? MAX_BURST_LEN - 1 :\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/axi_master/wburst_counter.v:33: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'wburst_issued_len\' generates 4 bits.\n                                                                                                                         : ... In instance wburst_counter\n        write_count <= write_count - wburst_issued_len;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/axi_master/wburst_counter.v:38: Operator SUB expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'wburst_issued_len\' generates 4 bits.\n                                                                                                                         : ... In instance wburst_counter\n        write_count <= write_count - wburst_issued_len - 1;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/axi_master/wburst_counter.v:57: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'READY\' generates 32 bits.\n                                                                                                                         : ... In instance wburst_counter\n        next_state = READY;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/axi_master/wburst_counter.v:61: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 32 bits.\n                                                                                                                         : ... In instance wburst_counter\n        next_state = IDLE;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/axi_master/wburst_counter.v:54: Operator CASE expects 32 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 1 bits.\n                                                                                                                         : ... In instance wburst_counter\n  case(state)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/axi_master/wburst_counter.v:72: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'state\' generates 1 bits.\n                                                                                                                         : ... In instance wburst_counter\nassign wburst_ready = (state == READY);\n                             ^~\n%Error: Exiting due to 10 warning(s)\n'
module wburst_counter #(
  parameter integer WBURST_COUNTER_LEN    = 16,
  parameter integer WBURST_LEN            = 4,
  parameter integer MAX_BURST_LEN         = 16
)(
  input  wire                             clk,
  input  wire                             resetn,
  input  wire                             write_valid,
  input  wire                             write_flush,

  output wire [WBURST_LEN-1:0]            wburst_len,
  output wire                             wburst_ready,

  input  wire                             wburst_issued,
  input  wire [WBURST_LEN-1:0]            wburst_issued_len
);


  reg  [WBURST_COUNTER_LEN-1:0] write_count;
  wire burst_ready;

  assign burst_ready = ((write_count >= MAX_BURST_LEN));
  assign wburst_len = write_count >= MAX_BURST_LEN ? MAX_BURST_LEN - 1 :
                      write_count != 0 ? write_count - 1 : 0;

  always @(posedge clk)
  begin
    if (!resetn)
      write_count <= 0;
    else if (write_valid)
    begin
      if (wburst_issued)
        write_count <= write_count - wburst_issued_len;
      else
        write_count <= write_count + 1;
    end else begin
      if (wburst_issued)
        write_count <= write_count - wburst_issued_len - 1;
      else
        write_count <= write_count + 0;
    end
  end



reg state;
reg next_state;

localparam integer IDLE=0, READY=1;

always @(*)
begin
  next_state = state;
  case(state)
    IDLE: begin
      if (burst_ready)
        next_state = READY;
    end
    READY: begin
      if (wburst_issued)
        next_state = IDLE;
    end
  endcase
end

always @(posedge clk)
  if (resetn)
    state <= next_state;
  else
    state <= 1'b0;

assign wburst_ready = (state == READY);

endmodule
module wburst_counter #(
  parameter integer WBURST_COUNTER_LEN    = 16,
  parameter integer WBURST_LEN            = 4,
  parameter integer MAX_BURST_LEN         = 16
)(
  input  wire                             clk,
  input  wire                             resetn,
  input  wire                             write_valid,
  input  wire                             write_flush,

  output wire [WBURST_LEN-1:0]            wburst_len,
  output wire                             wburst_ready,

  input  wire                             wburst_issued,
  input  wire [WBURST_LEN-1:0]            wburst_issued_len
);



  reg  [WBURST_COUNTER_LEN-1:0] write_count;
  wire burst_ready;

  assign burst_ready = ((write_count >= MAX_BURST_LEN));
  assign wburst_len = write_count >= MAX_BURST_LEN ? MAX_BURST_LEN - 1 :
                      write_count != 0 ? write_count - 1 : 0;

  always @(posedge clk)
  begin
    if (!resetn)
      write_count <= 0;
    else if (write_valid)
    begin
      if (wburst_issued)
        write_count <= write_count - wburst_issued_len;
      else
        write_count <= write_count + 1;
    end else begin
      if (wburst_issued)
        write_count <= write_count - wburst_issued_len - 1;
      else
        write_count <= write_count + 0;
    end
  end



reg state;
reg next_state;

localparam integer IDLE=0, READY=1;

always @(*)
begin
  next_state = state;
  case(state)
    IDLE: begin
      if (burst_ready)
        next_state = READY;
    end
    READY: begin
      if (wburst_issued)
        next_state = IDLE;
    end
  endcase
end

always @(posedge clk)
  if (resetn)
    state <= next_state;
  else
    state <= 1'b0;

assign wburst_ready = (state == READY);

endmodule