data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Finete_State_Machines/ece241_2014_q5b.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Finete_State_Machines/ece241_2014_q5b.v:17: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z'\n                                                                                                                                     : ... In instance top_module\n                z = x;\n                ^\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Finete_State_Machines/ece241_2014_q5b.v:23: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z'\n                                                                                                                                     : ... In instance top_module\n                z = ~x;\n                ^\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Finete_State_Machines/ece241_2014_q5b.v:29: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z'\n                                                                                                                                     : ... In instance top_module\n                z = 1'b0;\n                ^\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    localparam S0 = 0, S1 = 1;
    reg [1:0] state;
    reg [1:0] next_state;
    
    always @(*)	begin
        next_state = 2'b0;
        case(1'b1)
            state[S0] : begin
                next_state[S1] = x ? 1'b1 : 1'b0;
                next_state[S0] = x ? 1'b0 : 1'b1;
                z = x;
            end
            
            state[S1] : begin
                next_state[S1] = 1'b1;
                next_state[S0] = 1'b0;
                z = ~x;
            end
            
            default : begin
                next_state[S0] = 1'b1;
                next_state[S1] = 1'b0;
                z = 1'b0;
            end
        endcase
    end
    
    always @(posedge clk or posedge areset)	begin
        if(areset)	begin
            state <= 2'b0;
            state[S0] <= 1'b1;
        end
        else
            state <= next_state;
    end
   
endmodule
module top_module (
    input clk,
    input areset,
    input x,
    output z
);
 
    localparam S0 = 0, S1 = 1;
    reg [1:0] state;
    reg [1:0] next_state;
    
    always @(*)	begin
        next_state = 2'b0;
        case(1'b1)
            state[S0] : begin
                next_state[S1] = x ? 1'b1 : 1'b0;
                next_state[S0] = x ? 1'b0 : 1'b1;
                z = x;
            end
            
            state[S1] : begin
                next_state[S1] = 1'b1;
                next_state[S0] = 1'b0;
                z = ~x;
            end
            
            default : begin
                next_state[S0] = 1'b1;
                next_state[S1] = 1'b0;
                z = 1'b0;
            end
        endcase
    end
    
    always @(posedge clk or posedge areset)	begin
        if(areset)	begin
            state <= 2'b0;
            state[S0] <= 1'b1;
        end
        else
            state <= next_state;
    end
   
endmodule