data/full_repos/permissive/122492732/Master.v
 line:1: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/122492732/Master.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 alpha = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/122492732/Master.v:42: Unsupported: Ignoring delay on this delayed statement.\n #1 forever #2 scl2 <= !scl2;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/122492732/Master.v:42: Unsupported: Ignoring delay on this delayed statement.\n #1 forever #2 scl2 <= !scl2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/122492732/Master.v:98: Unsupported: Ignoring delay on this delayed statement.\n #2 alpha <= 1;\n ^\n%Error: data/full_repos/permissive/122492732/Master.v:112: Cannot find file containing module: \'Slave\'\nSlave Sl1(sda,scl);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/122492732,data/full_repos/permissive/122492732/Slave\n             data/full_repos/permissive/122492732,data/full_repos/permissive/122492732/Slave.v\n             data/full_repos/permissive/122492732,data/full_repos/permissive/122492732/Slave.sv\n             Slave\n             Slave.v\n             Slave.sv\n             obj_dir/Slave\n             obj_dir/Slave.v\n             obj_dir/Slave.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Master(sda,scl,clk);
inout sda;
input clk;
output reg scl;
reg scl2;
reg ack;
reg direction;
reg alpha;
reg [6:0] address;
reg [7:0] temp;
reg [7:0] temp_reserved;
reg rw;
reg[6:0] register;
reg a;
initial begin
	a = 0;
	rw = 0;
	scl = 1'b1;
	scl2 = 1'b1;
	direction = 1;
	address = 7'b1101001;
	register = 7'b1001010;
	temp = {address,rw};
	temp_reserved = {address,rw};
	alpha = 1;
	#5 alpha = 0;
end
always @(posedge clk)begin
	if(a==0)
		scl <= 1;
	else if(a==1)
		scl <= !scl;
end

always @(negedge sda)
	a <= 1;
always @(negedge scl)begin
	#1 forever #2 scl2 <= !scl2;
end
always @(sda)begin
	if(scl==1'b1) begin
		scl <= 1'b1;
	end
end

integer left_bits = 1;

always @(negedge scl2)begin

if(left_bits <= 8) begin
	alpha <= temp[7];
	temp <= temp<<1;
   left_bits <= left_bits + 1;
end
else if(left_bits == 9)begin
	direction <= 0;
	ack <= sda;
	left_bits <= left_bits + 1;
	end
else if(left_bits == 10)begin 

	if(sda == 0)begin
		left_bits <= 1;
		direction <= 1;
		temp <= temp_reserved;
	end
	else begin
		direction <= 1;
		alpha <= 0;
		left_bits <= left_bits + 1;
		end
end
else if(left_bits >=11 && left_bits <=17)begin

		alpha <= register[6];
		register <= register<<1;

	left_bits <= left_bits + 1;
	end
else if (left_bits >= 18 && left_bits <= 28)begin
	direction <=0;
	left_bits <= left_bits + 1;
	end
else if(left_bits == 29)begin
	direction <= 1;
	alpha <= 1;
	left_bits <= left_bits + 1;
	end
else if(left_bits == 30)begin
	alpha <= 0;
	left_bits <= left_bits + 1;
	end
else if(left_bits == 31)begin
	#2 alpha <= 1;

	left_bits <= left_bits + 1;
	end
else if(left_bits == 32)
	a <= 0;
	


end


assign sda = direction?alpha:1'bZ;

Slave Sl1(sda,scl);



endmodule
module Master(sda,scl,clk);

inout sda;
input clk;
output reg scl;
reg scl2;
reg ack;
reg direction;
reg alpha;
reg [6:0] address;
reg [7:0] temp;
reg [7:0] temp_reserved;
reg rw;
reg[6:0] register;
reg a;
initial begin
	a = 0;
	rw = 0;
	scl = 1'b1;
	scl2 = 1'b1;
	direction = 1;
	address = 7'b1101001;
	register = 7'b1001010;
	temp = {address,rw};
	temp_reserved = {address,rw};
	alpha = 1;
	#5 alpha = 0;
end
always @(posedge clk)begin
	if(a==0)
		scl <= 1;
	else if(a==1)
		scl <= !scl;
end

always @(negedge sda)
	a <= 1;
always @(negedge scl)begin
	#1 forever #2 scl2 <= !scl2;
end
always @(sda)begin
	if(scl==1'b1) begin
		scl <= 1'b1;
	end
end

integer left_bits = 1;

always @(negedge scl2)begin

if(left_bits <= 8) begin
	alpha <= temp[7];
	temp <= temp<<1;
   left_bits <= left_bits + 1;
end
else if(left_bits == 9)begin
	direction <= 0;
	ack <= sda;
	left_bits <= left_bits + 1;
	end
else if(left_bits == 10)begin 

	if(sda == 0)begin
		left_bits <= 1;
		direction <= 1;
		temp <= temp_reserved;
	end
	else begin
		direction <= 1;
		alpha <= 0;
		left_bits <= left_bits + 1;
		end
end
else if(left_bits >=11 && left_bits <=17)begin

		alpha <= register[6];
		register <= register<<1;

	left_bits <= left_bits + 1;
	end
else if (left_bits >= 18 && left_bits <= 28)begin
	direction <=0;
	left_bits <= left_bits + 1;
	end
else if(left_bits == 29)begin
	direction <= 1;
	alpha <= 1;
	left_bits <= left_bits + 1;
	end
else if(left_bits == 30)begin
	alpha <= 0;
	left_bits <= left_bits + 1;
	end
else if(left_bits == 31)begin
	#2 alpha <= 1;

	left_bits <= left_bits + 1;
	end
else if(left_bits == 32)
	a <= 0;
	


end


assign sda = direction?alpha:1'bZ;

Slave Sl1(sda,scl);



endmodule