data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:1: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Data/Control/Control.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Data/Control/Control.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Data/Control/Control.v.sv\n             Data/Control/Control.v\n             Data/Control/Control.v.v\n             Data/Control/Control.v.sv\n             obj_dir/Data/Control/Control.v\n             obj_dir/Data/Control/Control.v.v\n             obj_dir/Data/Control/Control.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:3: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:4: Cannot find include file: Mips/Type/RegAddr.v\n`include "Mips/Type/RegAddr.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:5: Cannot find include file: Mips/Type/RegPorts.v\n`include "Mips/Type/RegPorts.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:6: Cannot find include file: Mips/Instruction/Format/RFormat.v\n`include "Mips/Instruction/Format/RFormat.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:8: Cannot find include file: Mips/Control/Control.v\n`include "Mips/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:9: Cannot find include file: Mips/Control/Signal/Register/Control.v\n`include "Mips/Control/Signal/Register/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:11: Cannot find include file: Mips/Datapath/Register/ports.v\n`include "Mips/Datapath/Register/ports.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:12: Cannot find include file: Mips/Datapath/Register/wrData.v\n`include "Mips/Datapath/Register/wrData.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:13: Cannot find include file: Mips/Datapath/Register/register.v\n`include "Mips/Datapath/Register/register.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:18: Define or directive not defined: \'`Data_Control_Control_T\'\n ( `Data_Control_Control_T (input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:18: syntax error, unexpected \'(\', expecting \'[\'\n ( `Data_Control_Control_T (input) ctrl\n                            ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:19: Define or directive not defined: \'`Mips_Control_Control_T\'\n , `Mips_Control_Control_T (input) control\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:20: Define or directive not defined: \'`Mips_Type_RegPorts_T\'\n , `Mips_Type_RegPorts_T (input)  portsIn\n   ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:21: Define or directive not defined: \'`Mips_Type_RegPorts_T\'\n , `Mips_Type_RegPorts_T (output) portsOut\n   ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:22: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (input) instruction\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:23: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (input) pcAddr\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:24: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (input) memOut\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:25: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (input) aluResult\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:26: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (output) writeData\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:27: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (output) port1\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:28: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (output) port2\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:32: Define or directive not defined: \'`Mips_Type_Bool_T\'\n`Mips_Type_Bool_T (wire) portIn_WriteEn;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:33: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n`Mips_Type_RegAddr_T (wire) portIn_WriteAddr;\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:34: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteDataSource_T\'\n`Mips_Control_Signal_Register_Signal_WriteDataSource_T (wire) portIn_WriteData;\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:50: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n`Mips_Type_RegAddr_T (wire) portOut_Read1Addr;\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:51: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n`Mips_Type_RegAddr_T (wire) portOut_Read2Addr;\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/datapath.v:61: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) wrData;\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 28 error(s)\n'
module Mips_Datapath_Register_datapath #
	( parameter PASSTHROUGH = 0
	)
	( `Data_Control_Control_T (input) ctrl
	, `Mips_Control_Control_T (input) control
	, `Mips_Type_RegPorts_T (input)  portsIn
	, `Mips_Type_RegPorts_T (output) portsOut
	, `Mips_Type_Word_T (input) instruction
	, `Mips_Type_Word_T (input) pcAddr
	, `Mips_Type_Word_T (input) memOut
	, `Mips_Type_Word_T (input) aluResult
	, `Mips_Type_Word_T (output) writeData
	, `Mips_Type_Word_T (output) port1
	, `Mips_Type_Word_T (output) port2
	, output portEq
	);

`Mips_Type_Bool_T (wire) portIn_WriteEn;
`Mips_Type_RegAddr_T (wire) portIn_WriteAddr;
`Mips_Control_Signal_Register_Signal_WriteDataSource_T (wire) portIn_WriteData;
Mips_Type_RegPorts_unpack PORTIN
	( .in (portsIn)
	, .read1Addr ()
	, .read2Addr ()
	, .writeAddr (portIn_WriteAddr)
	, .writeData (portIn_WriteData)
	, .writeEn (portIn_WriteEn)
	);

Mips_Datapath_Register_ports PORTS
	( .ports (portsOut)
	, .control (control)
	, .instruction (instruction)
	);

`Mips_Type_RegAddr_T (wire) portOut_Read1Addr;
`Mips_Type_RegAddr_T (wire) portOut_Read2Addr;
Mips_Type_RegPorts_unpack PORTOUT
	( .in (portsOut)
	, .read1Addr (portOut_Read1Addr)
	, .read2Addr (portOut_Read2Addr)
	, .writeAddr ()
	, .writeData ()
	, .writeEn ()
	);

`Mips_Type_Word_T (wire) wrData;
Mips_Datapath_Register_wrData WRD
	( .source    (portIn_WriteData)
	, .memOut    (memOut)
	, .pcAddr    (pcAddr)
	, .aluResult (aluResult)
	, .wrData    (wrData)
	);

Mips_Datapath_Register_register #
	( .PASSTHROUGH (PASSTHROUGH)
	) REG
	( .ctrl    (ctrl)
	, .rd1Addr (portOut_Read1Addr)
	, .rd2Addr (portOut_Read2Addr)
	, .wrData   (wrData)
	, .wrAddr   (portIn_WriteAddr)
	, .wrEnable (portIn_WriteEn)
	, .rd1Data (port1)
	, .rd2Data (port2)
	);

assign portEq = port1 == port2;
assign writeData = wrData;

endmodule
module Mips_Datapath_Register_datapath #
	( parameter PASSTHROUGH = 0
	)
	( `Data_Control_Control_T (input) ctrl
	, `Mips_Control_Control_T (input) control
	, `Mips_Type_RegPorts_T (input)  portsIn
	, `Mips_Type_RegPorts_T (output) portsOut
	, `Mips_Type_Word_T (input) instruction
	, `Mips_Type_Word_T (input) pcAddr
	, `Mips_Type_Word_T (input) memOut
	, `Mips_Type_Word_T (input) aluResult
	, `Mips_Type_Word_T (output) writeData
	, `Mips_Type_Word_T (output) port1
	, `Mips_Type_Word_T (output) port2
	, output portEq
	);


`Mips_Type_Bool_T (wire) portIn_WriteEn;
`Mips_Type_RegAddr_T (wire) portIn_WriteAddr;
`Mips_Control_Signal_Register_Signal_WriteDataSource_T (wire) portIn_WriteData;
Mips_Type_RegPorts_unpack PORTIN
	( .in (portsIn)
	, .read1Addr ()
	, .read2Addr ()
	, .writeAddr (portIn_WriteAddr)
	, .writeData (portIn_WriteData)
	, .writeEn (portIn_WriteEn)
	);

Mips_Datapath_Register_ports PORTS
	( .ports (portsOut)
	, .control (control)
	, .instruction (instruction)
	);

`Mips_Type_RegAddr_T (wire) portOut_Read1Addr;
`Mips_Type_RegAddr_T (wire) portOut_Read2Addr;
Mips_Type_RegPorts_unpack PORTOUT
	( .in (portsOut)
	, .read1Addr (portOut_Read1Addr)
	, .read2Addr (portOut_Read2Addr)
	, .writeAddr ()
	, .writeData ()
	, .writeEn ()
	);

`Mips_Type_Word_T (wire) wrData;
Mips_Datapath_Register_wrData WRD
	( .source    (portIn_WriteData)
	, .memOut    (memOut)
	, .pcAddr    (pcAddr)
	, .aluResult (aluResult)
	, .wrData    (wrData)
	);

Mips_Datapath_Register_register #
	( .PASSTHROUGH (PASSTHROUGH)
	) REG
	( .ctrl    (ctrl)
	, .rd1Addr (portOut_Read1Addr)
	, .rd2Addr (portOut_Read2Addr)
	, .wrData   (wrData)
	, .wrAddr   (portIn_WriteAddr)
	, .wrEnable (portIn_WriteEn)
	, .rd1Data (port1)
	, .rd2Data (port2)
	);

assign portEq = port1 == port2;
assign writeData = wrData;

endmodule