data/full_repos/permissive/212897440/effect_mixer.v
 line:23: before: ","
1: b'%Warning-WIDTH: data/full_repos/permissive/212897440/effect_mixer.v:81: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_data_sw0\' generates 16 bits.\n                                                                      : ... In instance effect_mixer\n                                        r_data_add <= r_data_sw0;    \n                                                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212897440/effect_mixer.v:84: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_data_sw1\' generates 16 bits.\n                                                                      : ... In instance effect_mixer\n                                        r_data_add <= r_data_sw1;\n                                                   ^~\n%Error: Exiting due to 2 warning(s)\n'
module effect_mixer #( parameter
    data_width = 16
)(
    input                                       clk,
    input   [1:0]                               sw,
    input                                       reset,
    input                                       i_fifo_full,
    output  signed      [data_width-1: 0]       o_data,
    output                                      o_read_done,
    output                                      o_read_ready,
    output                                      o_data_valid,
    input                                       i_dv_from_eff,
    input  signed      [data_width-1: 0]    i_data_from_eff_sw0,
    input  signed      [data_width-1: 0]    i_data_from_eff_sw1 
);


localparam [2:0]        IDLE         = 'd0,
                        ADD          = 'd1,
                        NORM         = 'd2,
                        OUTPUT       = 'd3;

reg [2:0] r_state=IDLE, r_next=IDLE;

reg   signed      [data_width-1: 0]     r_data_sw0 = 'b0;
reg   signed      [data_width-1: 0]     r_data_sw1 = 'b0;

reg   signed      [data_width: 0]       r_data_add = 'b0;

reg   signed      [data_width-1: 0]     r_data_norm = 'b0;

reg     r_read_done = 0;
reg     r_read_ready = 0;
reg     r_data_valid = 0;

assign o_read_done = r_read_done;
assign o_data_valid = r_data_valid;
assign o_data = r_data_norm;
assign o_read_ready = r_read_ready;



always @(posedge clk ) begin
    if (reset == 1) begin

        r_state <= IDLE;
        r_next <= IDLE;
    end
    else begin
        r_state <= r_next;
    end 
end



always @(posedge clk ) begin
    
    case(r_state)
        IDLE    :   begin
                        if (i_dv_from_eff == 1) begin
                            r_next <= ADD;
                            r_data_sw0 <= i_data_from_eff_sw0;
                            r_data_sw1 <= i_data_from_eff_sw1;
                            r_data_norm <= 'b0;
                            r_read_done <= 1;
                            r_read_ready <= 0;
                            r_data_valid <= 0;
                        end
                        else begin
                            r_next <= IDLE;
                            r_read_ready <= 1;
                            r_data_valid <= 0;
                        end                         
                    end
        ADD     :   begin
                        case ( sw ) 
                            0   :   begin
                                        r_data_add <= 0;    
                                    end
                            1   :   begin
                                        r_data_add <= r_data_sw0;    
                                    end
                            2   :   begin
                                        r_data_add <= r_data_sw1;
                                    end
                            3   :   begin
                                        r_data_add <= r_data_sw0 + r_data_sw1;
                                    end                
                        endcase
                        r_next <= NORM;
                        r_read_done <= 0; 
                    end
        NORM    :   begin
                        case ( sw ) 
                            0   :   begin
                                        r_data_norm <= 0;    
                                    end
                            1   :   begin
                                        r_data_norm <= r_data_add[data_width-1: 0];    
                                    end
                            2   :   begin
                                        r_data_norm <= r_data_add[data_width-1: 0];
                                    end
                            3   :   begin
                                        r_data_norm <= r_data_add[data_width  : 1] ;
                                    end                
                        endcase
                        r_next <= OUTPUT;
                    end
        OUTPUT  :   begin
                        if ((i_fifo_full == 1) & (i_dv_from_eff == 1)) begin
                            r_next          <= OUTPUT;
                            r_read_done     <= 0;
                            r_read_ready    <= 0;
                            r_data_valid    <= 0;
                        end
                        else begin
                            r_next          <= IDLE;
                            r_read_ready    <= 0;
                            r_data_valid    <= 1;
                        end  
                    end
        default: r_next <= IDLE;
    endcase 
end




endmodule
module effect_mixer #( parameter
    data_width = 16
)(
    input                                       clk,
    input   [1:0]                               sw,
    input                                       reset,
    input                                       i_fifo_full,
    output  signed      [data_width-1: 0]       o_data,
    output                                      o_read_done,
    output                                      o_read_ready,
    output                                      o_data_valid,
    input                                       i_dv_from_eff,
    input  signed      [data_width-1: 0]    i_data_from_eff_sw0,
    input  signed      [data_width-1: 0]    i_data_from_eff_sw1 
);



localparam [2:0]        IDLE         = 'd0,
                        ADD          = 'd1,
                        NORM         = 'd2,
                        OUTPUT       = 'd3;

reg [2:0] r_state=IDLE, r_next=IDLE;

reg   signed      [data_width-1: 0]     r_data_sw0 = 'b0;
reg   signed      [data_width-1: 0]     r_data_sw1 = 'b0;

reg   signed      [data_width: 0]       r_data_add = 'b0;

reg   signed      [data_width-1: 0]     r_data_norm = 'b0;

reg     r_read_done = 0;
reg     r_read_ready = 0;
reg     r_data_valid = 0;

assign o_read_done = r_read_done;
assign o_data_valid = r_data_valid;
assign o_data = r_data_norm;
assign o_read_ready = r_read_ready;



always @(posedge clk ) begin
    if (reset == 1) begin

        r_state <= IDLE;
        r_next <= IDLE;
    end
    else begin
        r_state <= r_next;
    end 
end



always @(posedge clk ) begin
    
    case(r_state)
        IDLE    :   begin
                        if (i_dv_from_eff == 1) begin
                            r_next <= ADD;
                            r_data_sw0 <= i_data_from_eff_sw0;
                            r_data_sw1 <= i_data_from_eff_sw1;
                            r_data_norm <= 'b0;
                            r_read_done <= 1;
                            r_read_ready <= 0;
                            r_data_valid <= 0;
                        end
                        else begin
                            r_next <= IDLE;
                            r_read_ready <= 1;
                            r_data_valid <= 0;
                        end                         
                    end
        ADD     :   begin
                        case ( sw ) 
                            0   :   begin
                                        r_data_add <= 0;    
                                    end
                            1   :   begin
                                        r_data_add <= r_data_sw0;    
                                    end
                            2   :   begin
                                        r_data_add <= r_data_sw1;
                                    end
                            3   :   begin
                                        r_data_add <= r_data_sw0 + r_data_sw1;
                                    end                
                        endcase
                        r_next <= NORM;
                        r_read_done <= 0; 
                    end
        NORM    :   begin
                        case ( sw ) 
                            0   :   begin
                                        r_data_norm <= 0;    
                                    end
                            1   :   begin
                                        r_data_norm <= r_data_add[data_width-1: 0];    
                                    end
                            2   :   begin
                                        r_data_norm <= r_data_add[data_width-1: 0];
                                    end
                            3   :   begin
                                        r_data_norm <= r_data_add[data_width  : 1] ;
                                    end                
                        endcase
                        r_next <= OUTPUT;
                    end
        OUTPUT  :   begin
                        if ((i_fifo_full == 1) & (i_dv_from_eff == 1)) begin
                            r_next          <= OUTPUT;
                            r_read_done     <= 0;
                            r_read_ready    <= 0;
                            r_data_valid    <= 0;
                        end
                        else begin
                            r_next          <= IDLE;
                            r_read_ready    <= 0;
                            r_data_valid    <= 1;
                        end  
                    end
        default: r_next <= IDLE;
    endcase 
end




endmodule