data/full_repos/permissive/123304708/src/control/forwarding.v
1: b'%Warning-WIDTH: data/full_repos/permissive/123304708/src/control/forwarding.v:25: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'rs_ex\' generates 5 bits.\n                                                                                : ... In instance forwarding\n    else if((RegWrite_wb && rf_wa_wb != 0) && (rf_wa_wb == rs_ex)\n                                                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/123304708/src/control/forwarding.v:26: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'rs_ex\' generates 5 bits.\n                                                                                : ... In instance forwarding\n            && !((RegWrite_mem && rf_wa_mem != 0) && (rf_wa_mem == rs_ex))) \n                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/123304708/src/control/forwarding.v:22: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'rs_ex\' generates 5 bits.\n                                                                                : ... In instance forwarding\n    if((RegWrite_mem && rf_wa_mem != 0) && (rf_wa_mem == rs_ex))\n                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/123304708/src/control/forwarding.v:35: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'rt_ex\' generates 5 bits.\n                                                                                : ... In instance forwarding\n    else if((RegWrite_wb && rf_wa_wb != 0) && (rf_wa_wb == rt_ex)\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/123304708/src/control/forwarding.v:36: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'rt_ex\' generates 5 bits.\n                                                                                : ... In instance forwarding\n            && !((RegWrite_mem && rf_wa_mem != 0) && (rf_wa_mem == rt_ex))) \n                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/123304708/src/control/forwarding.v:32: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'rt_ex\' generates 5 bits.\n                                                                                : ... In instance forwarding\n    if((RegWrite_mem && rf_wa_mem != 0) && (rf_wa_mem == rt_ex))\n                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/123304708/src/control/forwarding.v:42: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'rt\' generates 5 bits.\n                                                                                : ... In instance forwarding\n    if(RegWrite_mem && Jump == 2\'b10 && (rf_wa == rt || rf_wa == rs)) \n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/123304708/src/control/forwarding.v:42: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'rs\' generates 5 bits.\n                                                                                : ... In instance forwarding\n    if(RegWrite_mem && Jump == 2\'b10 && (rf_wa == rt || rf_wa == rs)) \n                                                              ^~\n%Error: Exiting due to 8 warning(s)\n'
module forwarding(
  input [4:0] rs,
  input [4:0] rt,
  input [4:0] rs_ex,
  input [4:0] rt_ex,
  input [31:0] rf_wa,
  input [31:0] rf_wa_mem,
  input [31:0] rf_wa_wb,
  input [1:0] Jump,
  input MemRead_mem,
  input RegWrite_mem,
  input RegWrite_wb,
  
  output reg[1:0] forwardA,
  output reg[1:0] forwardB,
  output reg[1:0] JRegDst
  );

  always@(*)
  begin

    if((RegWrite_mem && rf_wa_mem != 0) && (rf_wa_mem == rs_ex))
      forwardA = 2'b10;

    else if((RegWrite_wb && rf_wa_wb != 0) && (rf_wa_wb == rs_ex)
            && !((RegWrite_mem && rf_wa_mem != 0) && (rf_wa_mem == rs_ex))) 
      forwardA = 2'b01;
    else
      forwardA = 2'b00;
      

    if((RegWrite_mem && rf_wa_mem != 0) && (rf_wa_mem == rt_ex))
      forwardB = 2'b10;

    else if((RegWrite_wb && rf_wa_wb != 0) && (rf_wa_wb == rt_ex)
            && !((RegWrite_mem && rf_wa_mem != 0) && (rf_wa_mem == rt_ex))) 
      forwardB = 2'b01;
    else
      forwardB = 2'b00;
      

    if(RegWrite_mem && Jump == 2'b10 && (rf_wa == rt || rf_wa == rs)) 
    begin
      if(MemRead_mem)
        JRegDst = 2'b10;
      else
        JRegDst = 2'b01;
    end
    else
      JRegDst = 2'b00;
  end
  
endmodule
module forwarding(
  input [4:0] rs,
  input [4:0] rt,
  input [4:0] rs_ex,
  input [4:0] rt_ex,
  input [31:0] rf_wa,
  input [31:0] rf_wa_mem,
  input [31:0] rf_wa_wb,
  input [1:0] Jump,
  input MemRead_mem,
  input RegWrite_mem,
  input RegWrite_wb,
  
  output reg[1:0] forwardA,
  output reg[1:0] forwardB,
  output reg[1:0] JRegDst
  );


  always@(*)
  begin

    if((RegWrite_mem && rf_wa_mem != 0) && (rf_wa_mem == rs_ex))
      forwardA = 2'b10;

    else if((RegWrite_wb && rf_wa_wb != 0) && (rf_wa_wb == rs_ex)
            && !((RegWrite_mem && rf_wa_mem != 0) && (rf_wa_mem == rs_ex))) 
      forwardA = 2'b01;
    else
      forwardA = 2'b00;
      

    if((RegWrite_mem && rf_wa_mem != 0) && (rf_wa_mem == rt_ex))
      forwardB = 2'b10;

    else if((RegWrite_wb && rf_wa_wb != 0) && (rf_wa_wb == rt_ex)
            && !((RegWrite_mem && rf_wa_mem != 0) && (rf_wa_mem == rt_ex))) 
      forwardB = 2'b01;
    else
      forwardB = 2'b00;
      

    if(RegWrite_mem && Jump == 2'b10 && (rf_wa == rt || rf_wa == rs)) 
    begin
      if(MemRead_mem)
        JRegDst = 2'b10;
      else
        JRegDst = 2'b01;
    end
    else
      JRegDst = 2'b00;
  end
  
endmodule