data/full_repos/permissive/135852214/Verilog/mexor_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/mexor_sim.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/mexor_sim.v:46: Unsupported: Ignoring delay on this delayed statement.\n   #10 in = i;\n   ^\n%Error: data/full_repos/permissive/135852214/Verilog/mexor_sim.v:34: Cannot find file containing module: \'mexor\'\n mexor uut (\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/mexor\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/mexor.v\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/mexor.sv\n             mexor\n             mexor.v\n             mexor.sv\n             obj_dir/mexor\n             obj_dir/mexor.v\n             obj_dir/mexor.sv\n%Warning-WIDTH: data/full_repos/permissive/135852214/Verilog/mexor_sim.v:46: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                           : ... In instance mexor_sim\n   #10 in = i;\n          ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mexor_sim;


	reg [4:0] in;
	integer i;

	wire [4:0] out;


	mexor uut (
		.in(in), 
		.out(out)
	);

	initial begin

		in = 0;


		#100;
		for (i = 0; i < 32; i = i+1)
			#10 in = i;
        


	end
      
endmodule
module mexor_sim;



	reg [4:0] in;
	integer i;

	wire [4:0] out;


	mexor uut (
		.in(in), 
		.out(out)
	);

	initial begin

		in = 0;


		#100;
		for (i = 0; i < 32; i = i+1)
			#10 in = i;
        


	end
      
endmodule