data/full_repos/permissive/106966316/alu32tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n#100; \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/alu32tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Error: data/full_repos/permissive/106966316/alu32tb.v:32: Cannot find file containing module: \'alu32\'\nalu32 uut(.iA(iA),.iB(iB),.ctrl(ctrl),.out(out),.oCarry(oCarry));\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/alu32\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/alu32.v\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/alu32.sv\n             alu32\n             alu32.v\n             alu32.sv\n             obj_dir/alu32\n             obj_dir/alu32.v\n             obj_dir/alu32.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu32tb();

reg [31:0] iA;
reg [31:0] iB;
reg [2:0] ctrl;

wire [31:0]out;
wire oCarry;

alu32 uut(.iA(iA),.iB(iB),.ctrl(ctrl),.out(out),.oCarry(oCarry));

initial begin

    iA = 32'b1;
    iB = 32'b1;

ctrl = 3'b000;

#100; 

iA = 32'b1;
iB = 32'b0;

ctrl = 3'b000;

#100;
$finish;
end 


endmodule
module alu32tb();


reg [31:0] iA;
reg [31:0] iB;
reg [2:0] ctrl;

wire [31:0]out;
wire oCarry;

alu32 uut(.iA(iA),.iB(iB),.ctrl(ctrl),.out(out),.oCarry(oCarry));

initial begin

    iA = 32'b1;
    iB = 32'b1;

ctrl = 3'b000;

#100; 

iA = 32'b1;
iB = 32'b0;

ctrl = 3'b000;

#100;
$finish;
end 


endmodule