data/full_repos/permissive/133651929/late_1_rx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:47: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n  next_state = 4\'b0000;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:53: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'START\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n      next_state = START;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:61: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_0\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n      next_state = DATA_0;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:66: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_1\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n      next_state = DATA_1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:71: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_2\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n      next_state = DATA_2;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:76: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_3\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n      next_state = DATA_3;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:81: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_4\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n      next_state = DATA_4;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:86: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_5\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n      next_state = DATA_5;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:91: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_6\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n      next_state = DATA_6;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:96: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_7\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n      next_state = DATA_7;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:101: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'STOP\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n      next_state = STOP;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:106: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n      next_state = IDLE;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:109: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n      next_state = IDLE;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:49: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'IDLE\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:49: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'START\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:49: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_0\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:49: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_1\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:49: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_2\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:49: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_3\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:49: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_4\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:49: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_5\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:49: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_6\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:49: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_7\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:49: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'STOP\' generates 4 bits.\n                                                                   : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:137: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:137: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:144: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:144: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:151: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:151: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:158: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:158: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:165: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:165: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:172: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:172: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:179: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:179: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:186: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:186: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                    : ... In instance late_1_rx\n      rx_data[count] <= rx_reg[count];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:192: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n      state  <= IDLE;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:198: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n      state <= IDLE;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:120: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'IDLE\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:120: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'START\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:120: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_0\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:120: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_1\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:120: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_2\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:120: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_3\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:120: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_4\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:120: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_5\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:120: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_6\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:120: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'DATA_7\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133651929/late_1_rx.v:120: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'STOP\' generates 4 bits.\n                                                                    : ... In instance late_1_rx\n    case(state)\n    ^~~~\n%Error: Exiting due to 53 warning(s)\n'
module late_1_rx(clk,rst,wr_en,enable,rx,rx_data);
	input 		clk,rst,wr_en,enable;
	input 		rx;
	output reg  [7:0] rx_data;
	reg			[7:0] rx_reg;
	reg			[4:0] state;
	reg			[4:0] next_state;
	wire    	rx,clk,rst,wr_en,enable;
	reg			[4:0] count;
	
	parameter	IDLE   = 4'b0000,
				START  = 4'b0001,
				DATA_0 = 4'b0010,
				DATA_1 = 4'b0011,
				DATA_2 = 4'b0100,
				DATA_3 = 4'b0101,
				DATA_4 = 4'b0110,
				DATA_5 = 4'b0111,
				DATA_6 = 4'b1000,
				DATA_7 = 4'b1001,
				STOP   = 4'b1010;
				
	always@(posedge clk)
		
		begin:RX_REGISTER
		rx_reg <= 0;
			if(rst == 1)begin
			rx_data <= 8'b0;
			end
		    else if(wr_en == 1 && enable == 1) begin
			rx_reg[7:0] <= {rx_reg[6:0],rx};

			count  <= count + 1;
			end
			






		end
		
		
	always@(state or wr_en or enable)
		begin:COMB_LOGIC
		next_state = 4'b0000;
				
				case(state)
				
				 IDLE  :
						begin
						next_state = START;
						end



				 START :  if(wr_en == 1'b1 && enable == 1'b1)
						begin

						next_state = DATA_0;
						end
				 DATA_0: if(count == 0)
						begin

						next_state = DATA_1;
						end
				 DATA_1:if(count == 1)
						begin

						next_state = DATA_2;
						end
				 DATA_2:if(count == 2)
						begin

						next_state = DATA_3;
						end
				 DATA_3:if(count == 3)
						begin

						next_state = DATA_4;
						end
				 DATA_4:if(count == 4)
						begin

						next_state = DATA_5;
						end
				 DATA_5:if(count == 5)
						begin

						next_state = DATA_6;
						end
				 DATA_6: if(count == 6)
						begin

						next_state = DATA_7;
						end
				 DATA_7: if(count == 7)
						begin

						next_state = STOP;
						end
				 STOP  : if(count == 8)
						begin

						next_state = IDLE;
						end
				 default:begin
						next_state = IDLE;
					    end
				endcase
		end
		
		
	always@(posedge clk)
		begin:SEQ_LOGIC
			
			  begin
				state <= next_state;
				case(state)
				
				 IDLE  :
						begin
						rx_data <= 0;
						end
						
				 START :
						begin


						count   <= 0;
						end
				 
				 DATA_0:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 DATA_1:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 DATA_2:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 DATA_3:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 DATA_4:
						begin

						rx_data[count] <= rx_reg[count];
						count   <= count + 1;
						end
						
				 DATA_5:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 DATA_6:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 DATA_7:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 STOP  :
						begin
						state  <= IDLE;
						rx_reg <= 8'b00000000;
						count  <= 0;
						end
						
				 default:begin
						state <= IDLE;
					    end
				endcase
			end
		end
endmodule
module late_1_rx(clk,rst,wr_en,enable,rx,rx_data);

	input 		clk,rst,wr_en,enable;
	input 		rx;
	output reg  [7:0] rx_data;
	reg			[7:0] rx_reg;
	reg			[4:0] state;
	reg			[4:0] next_state;
	wire    	rx,clk,rst,wr_en,enable;
	reg			[4:0] count;
	
	parameter	IDLE   = 4'b0000,
				START  = 4'b0001,
				DATA_0 = 4'b0010,
				DATA_1 = 4'b0011,
				DATA_2 = 4'b0100,
				DATA_3 = 4'b0101,
				DATA_4 = 4'b0110,
				DATA_5 = 4'b0111,
				DATA_6 = 4'b1000,
				DATA_7 = 4'b1001,
				STOP   = 4'b1010;
				
	always@(posedge clk)
		
		begin:RX_REGISTER
		rx_reg <= 0;
			if(rst == 1)begin
			rx_data <= 8'b0;
			end
		    else if(wr_en == 1 && enable == 1) begin
			rx_reg[7:0] <= {rx_reg[6:0],rx};

			count  <= count + 1;
			end
			






		end
		
		
	always@(state or wr_en or enable)
		begin:COMB_LOGIC
		next_state = 4'b0000;
				
				case(state)
				
				 IDLE  :
						begin
						next_state = START;
						end



				 START :  if(wr_en == 1'b1 && enable == 1'b1)
						begin

						next_state = DATA_0;
						end
				 DATA_0: if(count == 0)
						begin

						next_state = DATA_1;
						end
				 DATA_1:if(count == 1)
						begin

						next_state = DATA_2;
						end
				 DATA_2:if(count == 2)
						begin

						next_state = DATA_3;
						end
				 DATA_3:if(count == 3)
						begin

						next_state = DATA_4;
						end
				 DATA_4:if(count == 4)
						begin

						next_state = DATA_5;
						end
				 DATA_5:if(count == 5)
						begin

						next_state = DATA_6;
						end
				 DATA_6: if(count == 6)
						begin

						next_state = DATA_7;
						end
				 DATA_7: if(count == 7)
						begin

						next_state = STOP;
						end
				 STOP  : if(count == 8)
						begin

						next_state = IDLE;
						end
				 default:begin
						next_state = IDLE;
					    end
				endcase
		end
		
		
	always@(posedge clk)
		begin:SEQ_LOGIC
			
			  begin
				state <= next_state;
				case(state)
				
				 IDLE  :
						begin
						rx_data <= 0;
						end
						
				 START :
						begin


						count   <= 0;
						end
				 
				 DATA_0:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 DATA_1:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 DATA_2:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 DATA_3:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 DATA_4:
						begin

						rx_data[count] <= rx_reg[count];
						count   <= count + 1;
						end
						
				 DATA_5:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 DATA_6:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 DATA_7:
						begin

						rx_data[count] <= rx_reg[count];

						end
						
				 STOP  :
						begin
						state  <= IDLE;
						rx_reg <= 8'b00000000;
						count  <= 0;
						end
						
				 default:begin
						state <= IDLE;
					    end
				endcase
			end
		end
endmodule