data/full_repos/permissive/129127690/concat.v
data/verilator_xmls/64b16751-e5fa-4b28-9cfd-e86d60c32646.xml
module concat #(parameter bus_size = 32, bus_size_a = 16, bus_size_b = 16) (
	input [bus_size_a-1:0] a,
	input [bus_size_b-1:0] b,
	output [bus_size-1:0] out);
	
	assign out[bus_size-1:0] = {a, b};

endmodule
module concat #(parameter bus_size = 32, bus_size_a = 16, bus_size_b = 16) (
	input [bus_size_a-1:0] a,
	input [bus_size_b-1:0] b,
	output [bus_size-1:0] out);

	
	assign out[bus_size-1:0] = {a, b};

endmodule