data/full_repos/permissive/138254793/transmition.v
 line:321: before: "."
1: b'%Warning-WIDTH: data/full_repos/permissive/138254793/transmition.v:83: Operator ASSIGNDLY expects 139 bits on the Assign RHS, but Assign RHS\'s CONST \'138\'h0\' generates 138 bits.\n                                                                     : ... In instance transmition\n  metadata_out <= 138\'b0;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/138254793/transmition.v:223: Operator EQ expects 9 bits on the RHS, but RHS\'s CONST \'8\'h10\' generates 8 bits.\n                                                                      : ... In instance transmition\n    if(payload[96:88] == 8\'d16)\n                      ^~\n%Error: data/full_repos/permissive/138254793/transmition.v:309: Cannot find file containing module: \'fifo\'\nfifo packet_buffer(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/138254793,data/full_repos/permissive/138254793/fifo\n             data/full_repos/permissive/138254793,data/full_repos/permissive/138254793/fifo.v\n             data/full_repos/permissive/138254793,data/full_repos/permissive/138254793/fifo.sv\n             fifo\n             fifo.v\n             fifo.sv\n             obj_dir/fifo\n             obj_dir/fifo.v\n             obj_dir/fifo.sv\n%Error: data/full_repos/permissive/138254793/transmition.v:325: Cannot find file containing module: \'ram\'\nram packet_ram(\n^~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module transmition(
	clk,
	reset,
	metadata_in_valid,
	metadata_in,
	metadata_out_valid,
	metadata_out,
	um2cdp_rule_wrreq,
	um2cdp_rule,
	cdp2um_rule_usedw,
	cdp2um_tx_enable
);

input				clk;
input				reset;
input				metadata_in_valid;
input		[133:0]	metadata_in;
output	reg			metadata_out_valid;
output	reg	[138:0]	metadata_out;
output	reg			um2cdp_rule_wrreq;
output	reg	[29:0]	um2cdp_rule;
input		[4:0]	cdp2um_rule_usedw;
input				cdp2um_tx_enable;




reg				rdreq_pktBuffer;
wire			empty_pktBuffer;
wire	[133:0]	ctx_pktBuffer;


reg		[7:0]	idx_pkt;
reg				rden_pkt,wren_pkt;
reg		[133:0]	data_pkt;
wire	[133:0]	ctx_pkt;


reg	[7:0]	outPort;
reg	[47:0]	dstMac,srcMac;
reg	[15:0]	ethType,ipHead_tag;
reg	[79:0]	ipDefault;
reg	[31:0]	srcIP,dstIP;
reg	[127:0]	payload;
reg	[7:0]	protocol;
reg			forward_temp;


reg	[4:0]	state_trans;
parameter	IDLE_S				= 5'd0,
			READ_FIFO_S			= 5'd1,
			READ_META_2_S		= 5'd2,
			WRITE_RULE_S		= 5'd3,
			WAIT_SEND_PKT_S		= 5'd4,
			WAIT_SEND_PKT_C_S	= 5'd5,
			WAIT_PKT_TAIL_S		= 5'd6,
			SEND_PKT_ETH_S		= 5'd7,
			SEND_PKT_IP_S		= 5'd8,
			SEND_PKT_PAYLOAD_S	= 5'd9,
			SEND_PKT_TAIL_S		= 5'd10,
			SEND_PKT_HEAD_S		= 5'd11,
			DISCARD_S			= 5'd12,
			TRANS_RAM_PKT_S		= 5'd13,
			WAIT_TRANS_RAM_PKT_S= 5'd14,
			WAIT_RAM_1_S		= 5'd15,
			WAIT_RAM_2_S		= 5'd16,
			READ_RAM_S			= 5'd17;


always @(posedge clk or negedge reset) begin
	if (!reset) begin
		metadata_out_valid <= 1'b0;
		metadata_out <= 138'b0;
		um2cdp_rule_wrreq <= 1'b0;
		um2cdp_rule <= 30'b0;

		outPort <= 8'd0;
		protocol <= 8'b0;
		rdreq_pktBuffer <= 1'b0;
		rden_pkt <= 1'b0;
		wren_pkt <= 1'b0;
		data_pkt <= 134'b0;
		idx_pkt <= 8'b0;
		
		dstMac <= 48'h0000_1111_1111;
		srcMac <= 48'h0000_2222_2222;
		ethType <= 16'h0800;
		ipHead_tag <= 16'h4500;
		ipDefault <= {16'h0032,16'h706b,16'h4000,8'h7f,8'd252,16'h0};
		srcIP <= 32'h0000_2222;
		dstIP <= 32'h0000_1111;
		payload <= 128'b0;
		forward_temp <= 1'b0;

		state_trans <= IDLE_S;
	end
	else begin
		case(state_trans)
			IDLE_S: begin
				metadata_out_valid <= 1'b0;
				wren_pkt <= 1'b0;
				um2cdp_rule_wrreq <= 1'b0;
				outPort <= 8'd0;
				forward_temp <= 1'b0;
				if((cdp2um_rule_usedw <= 5'd28) &&
					(empty_pktBuffer == 1'b0)) 
				begin
					rdreq_pktBuffer <= 1'b1;
					state_trans <= READ_FIFO_S;
				end
				else begin
					state_trans <= IDLE_S;
				end
			end
			READ_FIFO_S: begin

				if(ctx_pktBuffer[123:120] == 4'd0) 		outPort <= 8'd2;
				else if(ctx_pktBuffer[123:120]==4'd1)	outPort <= 8'd1;
				else outPort <= 8'd0;
				protocol <= ctx_pktBuffer[119:112];
				state_trans <= READ_META_2_S;
			end
			READ_META_2_S: begin
				rdreq_pktBuffer <= 1'b0;
				

				if(ctx_pktBuffer[81] == 1'b1) begin

					forward_temp <= ctx_pktBuffer[80];
					payload <= ctx_pktBuffer[127:0];
					um2cdp_rule_wrreq <= 1'b1;
					um2cdp_rule <= {29'b0,1'b1};
					state_trans <= WAIT_SEND_PKT_C_S;
				end
				else begin
					forward_temp <= 1'b0;
					if(protocol == 8'd6) begin
						if(ctx_pktBuffer[80] == 1'b0) begin
							state_trans <= DISCARD_S;
							rdreq_pktBuffer <= 1'b1;
						end
						else begin
							um2cdp_rule_wrreq <= 1'b1;
							um2cdp_rule <= {22'b0,outPort};
							state_trans <= WAIT_SEND_PKT_S;
						end
					end
					else begin
						um2cdp_rule_wrreq <= 1'b1;
						um2cdp_rule <= {22'b0,outPort};
						state_trans <= WAIT_SEND_PKT_S;
					end
				end
			end
			WRITE_RULE_S: begin
				metadata_out_valid <= 1'b0;
				um2cdp_rule_wrreq <= 1'b1;
				um2cdp_rule <= {22'b0,outPort};
				state_trans <= WAIT_SEND_PKT_S;
			end
			WAIT_SEND_PKT_S: begin
				um2cdp_rule_wrreq <= 1'b0;
				if(cdp2um_tx_enable == 1'b1) begin
					forward_temp <= 1'b0;
					rdreq_pktBuffer <= 1'b1;
					state_trans <= WAIT_PKT_TAIL_S;
				end
			end
			WAIT_PKT_TAIL_S: begin
				idx_pkt <= idx_pkt + 8'd1;
				data_pkt <= ctx_pktBuffer;
			
				metadata_out_valid <= 1'b1;

				metadata_out[127:0] <= ctx_pktBuffer[127:0];
				metadata_out[131:128] <= 4'b0;
				metadata_out[135:132] <= ctx_pktBuffer[131:128];
				case(ctx_pktBuffer[133:132])
					2'b01: metadata_out[138:136] <= 3'b101;
					2'b11: metadata_out[138:136] <= 3'b100;
					2'b10: metadata_out[138:136] <= 3'b110;
					default: metadata_out[138:136] <= 3'b100;
				endcase

				if(ctx_pktBuffer[133:132] == 2'b10) begin
					rdreq_pktBuffer <= 1'b0;
					if(forward_temp == 1'b1) begin
						forward_temp <= 1'b0;
						state_trans <= TRANS_RAM_PKT_S;
					end
					else
						state_trans <=IDLE_S;
				end
				else state_trans <= WAIT_PKT_TAIL_S;
			end
			WAIT_SEND_PKT_C_S: begin
				um2cdp_rule_wrreq <= 1'b0;
				if(cdp2um_tx_enable == 1'b1) begin
					state_trans <= SEND_PKT_ETH_S;
				end
			end
			SEND_PKT_ETH_S: begin
				metadata_out_valid <= 1'b1;
				metadata_out <= {3'b101,4'hf,4'b0,dstMac,srcMac,ethType,ipHead_tag};
				state_trans <= SEND_PKT_IP_S;
			end
			SEND_PKT_IP_S: begin
				metadata_out <= {3'b100,4'hf,4'b0,ipDefault,srcIP,dstIP[31:16]};
				state_trans <= SEND_PKT_PAYLOAD_S;
			end
			SEND_PKT_PAYLOAD_S: begin
				metadata_out <= {3'b100,4'hf,4'b0,dstIP[15:0],payload[127:16]};
				if(payload[96:88] == 8'd16)

					state_trans <= SEND_PKT_TAIL_S;
				else begin
					rdreq_pktBuffer <= 1'b1;
					state_trans <= SEND_PKT_HEAD_S;
				end
			end
			SEND_PKT_TAIL_S: begin
				metadata_out <= {3'b110,4'hf,4'b0,128'b0};
				state_trans <= IDLE_S;
			end
			SEND_PKT_HEAD_S: begin
				idx_pkt <= 8'b0;
				data_pkt <= ctx_pktBuffer;
				wren_pkt <= 1'b1;
			
				metadata_out_valid <= 1'b1;
				metadata_out <= {3'b100,4'hf,4'd0,ctx_pktBuffer[127:0]};
				state_trans <= WAIT_PKT_TAIL_S;
			end
			DISCARD_S: begin
				if(ctx_pktBuffer[133:132] == 2'b10) begin
					rdreq_pktBuffer <= 1'b0;
					state_trans <= IDLE_S;
				end
				else begin
					state_trans <= DISCARD_S;
				end
			end
			TRANS_RAM_PKT_S: begin
				metadata_out_valid <= 1'b0;
				wren_pkt <= 1'b0;
				if(outPort!=8'b0) begin
					um2cdp_rule_wrreq <= 1'b1;
					um2cdp_rule <= {22'b0,outPort};
					state_trans <= WAIT_TRANS_RAM_PKT_S;
				end
				else
					state_trans <= IDLE_S;
			end
			WAIT_TRANS_RAM_PKT_S: begin
				um2cdp_rule_wrreq <= 1'b0;
				if(cdp2um_tx_enable == 1'b1) begin
					state_trans <= WAIT_RAM_1_S;
					
					idx_pkt <= 8'd0;
					rden_pkt <= 1'b1;
				end
				else
					state_trans <= WAIT_TRANS_RAM_PKT_S;
			end
			WAIT_RAM_1_S: begin
				idx_pkt <= idx_pkt + 8'd1;
				state_trans <= WAIT_RAM_2_S;
			end
			WAIT_RAM_2_S: begin
				idx_pkt <= idx_pkt + 8'd1;
				state_trans <= READ_RAM_S;
			end
			READ_RAM_S: begin
				idx_pkt <= idx_pkt + 8'd1;
				metadata_out_valid <= 1'b1;

				metadata_out[127:0] <= ctx_pkt[127:0];
				metadata_out[131:128] <= 4'b0;
				metadata_out[135:132] <= ctx_pkt[131:128];
				case(ctx_pkt[133:132])
					2'b01: metadata_out[138:136] <= 3'b101;
					2'b11: metadata_out[138:136] <= 3'b100;
					2'b10: metadata_out[138:136] <= 3'b110;
					default: metadata_out[138:136] <= 3'b100;
				endcase
				if(ctx_pkt[133:132] == 2'b10) begin
					rden_pkt <= 1'b0;
					state_trans <= IDLE_S;
				end
				else
					state_trans <= READ_RAM_S;
			end
			default: state_trans <= IDLE_S;
		endcase
	end
end


fifo packet_buffer(
.aclr(!reset),
.clock(clk),
.data(metadata_in),
.rdreq(rdreq_pktBuffer),
.wrreq(metadata_in_valid),
.empty(empty_pktBuffer),
.full(),
.q(ctx_pktBuffer),
.usedw()
);
defparam
	packet_buffer.width = 134,
	packet_buffer.depth = 8,
	packet_buffer.words = 256;

ram packet_ram(
.address_a(idx_pkt),
.address_b(8'b0),
.clock(clk),
.data_a(data_pkt),
.data_b(134'b0),
.rden_a(rden_pkt),
.rden_b(1'b0),
.wren_a(wren_pkt),
.wren_b(1'b0),
.q_a(ctx_pkt),
.q_b()
);
defparam
	packet_ram.width = 134,
	packet_ram.depth = 8,
	packet_ram.words = 256;
	
	

endmodule
module transmition(
	clk,
	reset,
	metadata_in_valid,
	metadata_in,
	metadata_out_valid,
	metadata_out,
	um2cdp_rule_wrreq,
	um2cdp_rule,
	cdp2um_rule_usedw,
	cdp2um_tx_enable
);


input				clk;
input				reset;
input				metadata_in_valid;
input		[133:0]	metadata_in;
output	reg			metadata_out_valid;
output	reg	[138:0]	metadata_out;
output	reg			um2cdp_rule_wrreq;
output	reg	[29:0]	um2cdp_rule;
input		[4:0]	cdp2um_rule_usedw;
input				cdp2um_tx_enable;




reg				rdreq_pktBuffer;
wire			empty_pktBuffer;
wire	[133:0]	ctx_pktBuffer;


reg		[7:0]	idx_pkt;
reg				rden_pkt,wren_pkt;
reg		[133:0]	data_pkt;
wire	[133:0]	ctx_pkt;


reg	[7:0]	outPort;
reg	[47:0]	dstMac,srcMac;
reg	[15:0]	ethType,ipHead_tag;
reg	[79:0]	ipDefault;
reg	[31:0]	srcIP,dstIP;
reg	[127:0]	payload;
reg	[7:0]	protocol;
reg			forward_temp;


reg	[4:0]	state_trans;
parameter	IDLE_S				= 5'd0,
			READ_FIFO_S			= 5'd1,
			READ_META_2_S		= 5'd2,
			WRITE_RULE_S		= 5'd3,
			WAIT_SEND_PKT_S		= 5'd4,
			WAIT_SEND_PKT_C_S	= 5'd5,
			WAIT_PKT_TAIL_S		= 5'd6,
			SEND_PKT_ETH_S		= 5'd7,
			SEND_PKT_IP_S		= 5'd8,
			SEND_PKT_PAYLOAD_S	= 5'd9,
			SEND_PKT_TAIL_S		= 5'd10,
			SEND_PKT_HEAD_S		= 5'd11,
			DISCARD_S			= 5'd12,
			TRANS_RAM_PKT_S		= 5'd13,
			WAIT_TRANS_RAM_PKT_S= 5'd14,
			WAIT_RAM_1_S		= 5'd15,
			WAIT_RAM_2_S		= 5'd16,
			READ_RAM_S			= 5'd17;


always @(posedge clk or negedge reset) begin
	if (!reset) begin
		metadata_out_valid <= 1'b0;
		metadata_out <= 138'b0;
		um2cdp_rule_wrreq <= 1'b0;
		um2cdp_rule <= 30'b0;

		outPort <= 8'd0;
		protocol <= 8'b0;
		rdreq_pktBuffer <= 1'b0;
		rden_pkt <= 1'b0;
		wren_pkt <= 1'b0;
		data_pkt <= 134'b0;
		idx_pkt <= 8'b0;
		
		dstMac <= 48'h0000_1111_1111;
		srcMac <= 48'h0000_2222_2222;
		ethType <= 16'h0800;
		ipHead_tag <= 16'h4500;
		ipDefault <= {16'h0032,16'h706b,16'h4000,8'h7f,8'd252,16'h0};
		srcIP <= 32'h0000_2222;
		dstIP <= 32'h0000_1111;
		payload <= 128'b0;
		forward_temp <= 1'b0;

		state_trans <= IDLE_S;
	end
	else begin
		case(state_trans)
			IDLE_S: begin
				metadata_out_valid <= 1'b0;
				wren_pkt <= 1'b0;
				um2cdp_rule_wrreq <= 1'b0;
				outPort <= 8'd0;
				forward_temp <= 1'b0;
				if((cdp2um_rule_usedw <= 5'd28) &&
					(empty_pktBuffer == 1'b0)) 
				begin
					rdreq_pktBuffer <= 1'b1;
					state_trans <= READ_FIFO_S;
				end
				else begin
					state_trans <= IDLE_S;
				end
			end
			READ_FIFO_S: begin

				if(ctx_pktBuffer[123:120] == 4'd0) 		outPort <= 8'd2;
				else if(ctx_pktBuffer[123:120]==4'd1)	outPort <= 8'd1;
				else outPort <= 8'd0;
				protocol <= ctx_pktBuffer[119:112];
				state_trans <= READ_META_2_S;
			end
			READ_META_2_S: begin
				rdreq_pktBuffer <= 1'b0;
				

				if(ctx_pktBuffer[81] == 1'b1) begin

					forward_temp <= ctx_pktBuffer[80];
					payload <= ctx_pktBuffer[127:0];
					um2cdp_rule_wrreq <= 1'b1;
					um2cdp_rule <= {29'b0,1'b1};
					state_trans <= WAIT_SEND_PKT_C_S;
				end
				else begin
					forward_temp <= 1'b0;
					if(protocol == 8'd6) begin
						if(ctx_pktBuffer[80] == 1'b0) begin
							state_trans <= DISCARD_S;
							rdreq_pktBuffer <= 1'b1;
						end
						else begin
							um2cdp_rule_wrreq <= 1'b1;
							um2cdp_rule <= {22'b0,outPort};
							state_trans <= WAIT_SEND_PKT_S;
						end
					end
					else begin
						um2cdp_rule_wrreq <= 1'b1;
						um2cdp_rule <= {22'b0,outPort};
						state_trans <= WAIT_SEND_PKT_S;
					end
				end
			end
			WRITE_RULE_S: begin
				metadata_out_valid <= 1'b0;
				um2cdp_rule_wrreq <= 1'b1;
				um2cdp_rule <= {22'b0,outPort};
				state_trans <= WAIT_SEND_PKT_S;
			end
			WAIT_SEND_PKT_S: begin
				um2cdp_rule_wrreq <= 1'b0;
				if(cdp2um_tx_enable == 1'b1) begin
					forward_temp <= 1'b0;
					rdreq_pktBuffer <= 1'b1;
					state_trans <= WAIT_PKT_TAIL_S;
				end
			end
			WAIT_PKT_TAIL_S: begin
				idx_pkt <= idx_pkt + 8'd1;
				data_pkt <= ctx_pktBuffer;
			
				metadata_out_valid <= 1'b1;

				metadata_out[127:0] <= ctx_pktBuffer[127:0];
				metadata_out[131:128] <= 4'b0;
				metadata_out[135:132] <= ctx_pktBuffer[131:128];
				case(ctx_pktBuffer[133:132])
					2'b01: metadata_out[138:136] <= 3'b101;
					2'b11: metadata_out[138:136] <= 3'b100;
					2'b10: metadata_out[138:136] <= 3'b110;
					default: metadata_out[138:136] <= 3'b100;
				endcase

				if(ctx_pktBuffer[133:132] == 2'b10) begin
					rdreq_pktBuffer <= 1'b0;
					if(forward_temp == 1'b1) begin
						forward_temp <= 1'b0;
						state_trans <= TRANS_RAM_PKT_S;
					end
					else
						state_trans <=IDLE_S;
				end
				else state_trans <= WAIT_PKT_TAIL_S;
			end
			WAIT_SEND_PKT_C_S: begin
				um2cdp_rule_wrreq <= 1'b0;
				if(cdp2um_tx_enable == 1'b1) begin
					state_trans <= SEND_PKT_ETH_S;
				end
			end
			SEND_PKT_ETH_S: begin
				metadata_out_valid <= 1'b1;
				metadata_out <= {3'b101,4'hf,4'b0,dstMac,srcMac,ethType,ipHead_tag};
				state_trans <= SEND_PKT_IP_S;
			end
			SEND_PKT_IP_S: begin
				metadata_out <= {3'b100,4'hf,4'b0,ipDefault,srcIP,dstIP[31:16]};
				state_trans <= SEND_PKT_PAYLOAD_S;
			end
			SEND_PKT_PAYLOAD_S: begin
				metadata_out <= {3'b100,4'hf,4'b0,dstIP[15:0],payload[127:16]};
				if(payload[96:88] == 8'd16)

					state_trans <= SEND_PKT_TAIL_S;
				else begin
					rdreq_pktBuffer <= 1'b1;
					state_trans <= SEND_PKT_HEAD_S;
				end
			end
			SEND_PKT_TAIL_S: begin
				metadata_out <= {3'b110,4'hf,4'b0,128'b0};
				state_trans <= IDLE_S;
			end
			SEND_PKT_HEAD_S: begin
				idx_pkt <= 8'b0;
				data_pkt <= ctx_pktBuffer;
				wren_pkt <= 1'b1;
			
				metadata_out_valid <= 1'b1;
				metadata_out <= {3'b100,4'hf,4'd0,ctx_pktBuffer[127:0]};
				state_trans <= WAIT_PKT_TAIL_S;
			end
			DISCARD_S: begin
				if(ctx_pktBuffer[133:132] == 2'b10) begin
					rdreq_pktBuffer <= 1'b0;
					state_trans <= IDLE_S;
				end
				else begin
					state_trans <= DISCARD_S;
				end
			end
			TRANS_RAM_PKT_S: begin
				metadata_out_valid <= 1'b0;
				wren_pkt <= 1'b0;
				if(outPort!=8'b0) begin
					um2cdp_rule_wrreq <= 1'b1;
					um2cdp_rule <= {22'b0,outPort};
					state_trans <= WAIT_TRANS_RAM_PKT_S;
				end
				else
					state_trans <= IDLE_S;
			end
			WAIT_TRANS_RAM_PKT_S: begin
				um2cdp_rule_wrreq <= 1'b0;
				if(cdp2um_tx_enable == 1'b1) begin
					state_trans <= WAIT_RAM_1_S;
					
					idx_pkt <= 8'd0;
					rden_pkt <= 1'b1;
				end
				else
					state_trans <= WAIT_TRANS_RAM_PKT_S;
			end
			WAIT_RAM_1_S: begin
				idx_pkt <= idx_pkt + 8'd1;
				state_trans <= WAIT_RAM_2_S;
			end
			WAIT_RAM_2_S: begin
				idx_pkt <= idx_pkt + 8'd1;
				state_trans <= READ_RAM_S;
			end
			READ_RAM_S: begin
				idx_pkt <= idx_pkt + 8'd1;
				metadata_out_valid <= 1'b1;

				metadata_out[127:0] <= ctx_pkt[127:0];
				metadata_out[131:128] <= 4'b0;
				metadata_out[135:132] <= ctx_pkt[131:128];
				case(ctx_pkt[133:132])
					2'b01: metadata_out[138:136] <= 3'b101;
					2'b11: metadata_out[138:136] <= 3'b100;
					2'b10: metadata_out[138:136] <= 3'b110;
					default: metadata_out[138:136] <= 3'b100;
				endcase
				if(ctx_pkt[133:132] == 2'b10) begin
					rden_pkt <= 1'b0;
					state_trans <= IDLE_S;
				end
				else
					state_trans <= READ_RAM_S;
			end
			default: state_trans <= IDLE_S;
		endcase
	end
end


fifo packet_buffer(
.aclr(!reset),
.clock(clk),
.data(metadata_in),
.rdreq(rdreq_pktBuffer),
.wrreq(metadata_in_valid),
.empty(empty_pktBuffer),
.full(),
.q(ctx_pktBuffer),
.usedw()
);
defparam
	packet_buffer.width = 134,
	packet_buffer.depth = 8,
	packet_buffer.words = 256;

ram packet_ram(
.address_a(idx_pkt),
.address_b(8'b0),
.clock(clk),
.data_a(data_pkt),
.data_b(134'b0),
.rden_a(rden_pkt),
.rden_b(1'b0),
.wren_a(wren_pkt),
.wren_b(1'b0),
.q_a(ctx_pkt),
.q_b()
);
defparam
	packet_ram.width = 134,
	packet_ram.depth = 8,
	packet_ram.words = 256;
	
	

endmodule