data/full_repos/permissive/20401628/i2c.v
1: b"%Error: data/full_repos/permissive/20401628/i2c.v:30: syntax error, unexpected byte, expecting IDENTIFIER or do or final\nwire [7:0] byte;\n           ^~~~\n%Error: data/full_repos/permissive/20401628/i2c.v:44: syntax error, unexpected byte, expecting TYPE-IDENTIFIER\nassign byte = inst[7:0];\n       ^~~~\n%Error: data/full_repos/permissive/20401628/i2c.v:270: syntax error, unexpected byte\n .byte(byte),\n  ^~~~\n%Error: data/full_repos/permissive/20401628/i2c.v:506: syntax error, unexpected byte, expecting IDENTIFIER or '[' or do or final\n input [7:0] byte,\n             ^~~~\n%Error: data/full_repos/permissive/20401628/i2c.v:508: syntax error, unexpected inout, expecting IDENTIFIER or '=' or do or final\n inout i2c_sda,\n ^~~~~\n%Error: data/full_repos/permissive/20401628/i2c.v:515: syntax error, unexpected assign\nassign i2c_sda = sda_oe ? sda_out : 1'bz;\n^~~~~~\n%Error: data/full_repos/permissive/20401628/i2c.v:528: syntax error, unexpected always\nalways @(posedge ioclk)\n^~~~~~\n%Error: Exiting due to 7 error(s)\n"
function [11:0] instmem;
input [7:0] pc;
input [7:0] data;
case (pc)

	8'h0: instmem = START;
	8'h1: instmem = {4'h8, LCD_ADDR};
	8'h2: instmem = TRANSMIT;
	8'h3: instmem = {4'h8, 8'h80};
	8'h4: instmem = TRANSMIT;
	8'h5: instmem = {4'h8, 8'h38};
	8'h6: instmem = TRANSMIT;
	8'h7: instmem = END;

	8'h8: instmem = START;
	8'h9: instmem = {4'h8, LCD_ADDR};
	8'ha: instmem = TRANSMIT;
	8'hb: instmem = {4'h8, 8'h80};
	8'hc: instmem = TRANSMIT;
	8'hd: instmem = {4'h8, 8'h39};
	8'he: instmem = TRANSMIT;
	8'hf: instmem = END;

	8'h10: instmem = START;
	8'h11: instmem = {4'h8, LCD_ADDR};
	8'h12: instmem = TRANSMIT;
	8'h13: instmem = {4'h8, 8'h80};
	8'h14: instmem = TRANSMIT;
	8'h15: instmem = {4'h8, 8'h14};
	8'h16: instmem = TRANSMIT;
	8'h17: instmem = END;

	8'h18: instmem = START;
	8'h19: instmem = {4'h8, LCD_ADDR};
	8'h1a: instmem = TRANSMIT;
	8'h1b: instmem = {4'h8, 8'h80};
	8'h1c: instmem = TRANSMIT;
	8'h1d: instmem = {4'h8, 8'h74};
	8'h1e: instmem = TRANSMIT;
	8'h1f: instmem = END;

	8'h20: instmem = START;
	8'h21: instmem = {4'h8, LCD_ADDR};
	8'h22: instmem = TRANSMIT;
	8'h23: instmem = {4'h8, 8'h80};
	8'h24: instmem = TRANSMIT;
	8'h25: instmem = {4'h8, 8'h56};
	8'h26: instmem = TRANSMIT;
	8'h27: instmem = END;

	8'h28: instmem = START;
	8'h29: instmem = {4'h8, LCD_ADDR};
	8'h2a: instmem = TRANSMIT;
	8'h2b: instmem = {4'h8, 8'h80};
	8'h2c: instmem = TRANSMIT;
	8'h2d: instmem = {4'h8, 8'h6c};
	8'h2e: instmem = TRANSMIT;
	8'h2f: instmem = END;



	8'h30: instmem = START;
	8'h31: instmem = {4'h8, LCD_ADDR};
	8'h32: instmem = TRANSMIT;
	8'h33: instmem = {4'h8, 8'h80};
	8'h34: instmem = TRANSMIT;
	8'h35: instmem = {4'h8, 8'h38};
	8'h36: instmem = TRANSMIT;
	8'h37: instmem = END;

	8'h38: instmem = START;
	8'h39: instmem = {4'h8, LCD_ADDR};
	8'h3a: instmem = TRANSMIT;
	8'h3b: instmem = {4'h8, 8'h80};
	8'h3c: instmem = TRANSMIT;
	8'h3d: instmem = {4'h8, 8'h0c};
	8'h3e: instmem = TRANSMIT;
	8'h3f: instmem = END;

	8'h40: instmem = START;
	8'h41: instmem = {4'h8, LCD_ADDR};
	8'h42: instmem = TRANSMIT;
	8'h43: instmem = {4'h8, 8'h80};
	8'h44: instmem = TRANSMIT;
	8'h45: instmem = {4'h8, 8'h01};
	8'h46: instmem = TRANSMIT;
	8'h47: instmem = END;

	8'h48: instmem = START;
	8'h49: instmem = {4'h8, LCD_ADDR};
	8'h4a: instmem = TRANSMIT;
	8'h4b: instmem = {4'h8, 8'hc0};
	8'h4c: instmem = TRANSMIT;
	8'h4d: instmem = {4'h8, data};
	8'h4e: instmem = TRANSMIT;
	8'h53: instmem = END;
	8'h54: instmem = 0;

	8'h60: instmem = START;
	8'h61: instmem = {4'h8, LCD_ADDR};
	8'h62: instmem = TRANSMIT;
	8'h63: instmem = {4'h8, 8'h80};
	8'h64: instmem = TRANSMIT;
	8'h65: instmem = {4'h8, 8'h01};
	8'h66: instmem = TRANSMIT;
	8'h67: instmem = END;                            
	8'h68: instmem = 0;


	default:
		instmem = 0;
endcase
endfunction
function [11:0] instmem;

input [7:0] pc;
input [7:0] data;
case (pc)

	8'h0: instmem = START;
	8'h1: instmem = {4'h8, LCD_ADDR};
	8'h2: instmem = TRANSMIT;
	8'h3: instmem = {4'h8, 8'h80};
	8'h4: instmem = TRANSMIT;
	8'h5: instmem = {4'h8, 8'h38};
	8'h6: instmem = TRANSMIT;
	8'h7: instmem = END;

	8'h8: instmem = START;
	8'h9: instmem = {4'h8, LCD_ADDR};
	8'ha: instmem = TRANSMIT;
	8'hb: instmem = {4'h8, 8'h80};
	8'hc: instmem = TRANSMIT;
	8'hd: instmem = {4'h8, 8'h39};
	8'he: instmem = TRANSMIT;
	8'hf: instmem = END;

	8'h10: instmem = START;
	8'h11: instmem = {4'h8, LCD_ADDR};
	8'h12: instmem = TRANSMIT;
	8'h13: instmem = {4'h8, 8'h80};
	8'h14: instmem = TRANSMIT;
	8'h15: instmem = {4'h8, 8'h14};
	8'h16: instmem = TRANSMIT;
	8'h17: instmem = END;

	8'h18: instmem = START;
	8'h19: instmem = {4'h8, LCD_ADDR};
	8'h1a: instmem = TRANSMIT;
	8'h1b: instmem = {4'h8, 8'h80};
	8'h1c: instmem = TRANSMIT;
	8'h1d: instmem = {4'h8, 8'h74};
	8'h1e: instmem = TRANSMIT;
	8'h1f: instmem = END;

	8'h20: instmem = START;
	8'h21: instmem = {4'h8, LCD_ADDR};
	8'h22: instmem = TRANSMIT;
	8'h23: instmem = {4'h8, 8'h80};
	8'h24: instmem = TRANSMIT;
	8'h25: instmem = {4'h8, 8'h56};
	8'h26: instmem = TRANSMIT;
	8'h27: instmem = END;

	8'h28: instmem = START;
	8'h29: instmem = {4'h8, LCD_ADDR};
	8'h2a: instmem = TRANSMIT;
	8'h2b: instmem = {4'h8, 8'h80};
	8'h2c: instmem = TRANSMIT;
	8'h2d: instmem = {4'h8, 8'h6c};
	8'h2e: instmem = TRANSMIT;
	8'h2f: instmem = END;



	8'h30: instmem = START;
	8'h31: instmem = {4'h8, LCD_ADDR};
	8'h32: instmem = TRANSMIT;
	8'h33: instmem = {4'h8, 8'h80};
	8'h34: instmem = TRANSMIT;
	8'h35: instmem = {4'h8, 8'h38};
	8'h36: instmem = TRANSMIT;
	8'h37: instmem = END;

	8'h38: instmem = START;
	8'h39: instmem = {4'h8, LCD_ADDR};
	8'h3a: instmem = TRANSMIT;
	8'h3b: instmem = {4'h8, 8'h80};
	8'h3c: instmem = TRANSMIT;
	8'h3d: instmem = {4'h8, 8'h0c};
	8'h3e: instmem = TRANSMIT;
	8'h3f: instmem = END;

	8'h40: instmem = START;
	8'h41: instmem = {4'h8, LCD_ADDR};
	8'h42: instmem = TRANSMIT;
	8'h43: instmem = {4'h8, 8'h80};
	8'h44: instmem = TRANSMIT;
	8'h45: instmem = {4'h8, 8'h01};
	8'h46: instmem = TRANSMIT;
	8'h47: instmem = END;

	8'h48: instmem = START;
	8'h49: instmem = {4'h8, LCD_ADDR};
	8'h4a: instmem = TRANSMIT;
	8'h4b: instmem = {4'h8, 8'hc0};
	8'h4c: instmem = TRANSMIT;
	8'h4d: instmem = {4'h8, data};
	8'h4e: instmem = TRANSMIT;
	8'h53: instmem = END;
	8'h54: instmem = 0;

	8'h60: instmem = START;
	8'h61: instmem = {4'h8, LCD_ADDR};
	8'h62: instmem = TRANSMIT;
	8'h63: instmem = {4'h8, 8'h80};
	8'h64: instmem = TRANSMIT;
	8'h65: instmem = {4'h8, 8'h01};
	8'h66: instmem = TRANSMIT;
	8'h67: instmem = END;                            
	8'h68: instmem = 0;


	default:
		instmem = 0;
endcase
endfunction