data/full_repos/permissive/174642777/Experiments/Lab X6/2. TC_Mealy/TC_Mealy.v
1: b'%Error: Cannot find file containing module: X6/2.\n        ... Looked in:\n             data/full_repos/permissive/174642777/Experiments/Lab/X6/2.\n             data/full_repos/permissive/174642777/Experiments/Lab/X6/2..v\n             data/full_repos/permissive/174642777/Experiments/Lab/X6/2..sv\n             X6/2.\n             X6/2..v\n             X6/2..sv\n             obj_dir/X6/2.\n             obj_dir/X6/2..v\n             obj_dir/X6/2..sv\n%Error: Cannot find file containing module: TC_Mealy,data/full_repos/permissive/174642777\n%Error: Cannot find file containing module: data/full_repos/permissive/174642777/Experiments/Lab\n%Error: Cannot find file containing module: TC_Mealy/TC_Mealy.v\n%Error: Exiting due to 4 error(s)\n'
module TC_Mealy(
  input wire CLK,
  input wire R,
  input wire T_A, T_B,
  output reg[2:0] L_A,
  output reg[2:0] L_B
);

  reg[1:0] state;
  

  initial begin

    state <= 2'b00;
    

    L_A = 3'b100;
    L_B = 3'b001;
  end
  

  always@(posedge CLK, posedge R) begin
    if(R) begin
      state = 2'b00;
      L_A = 3'b100;
      L_B = 3'b001;
    end
    else begin
      case(state)

        2'b00: begin
          if(!T_A) begin
            state = 2'b01;
            L_A = 3'b010;
            L_B = 3'b001;
          end
        end
        

        2'b01: begin
          state = 2'b10;
          L_A = 3'b001;
          L_B = 3'b100;
        end
        

        2'b10: begin
          if(!T_B) begin
            state = 2'b11;
            L_A = 3'b001;
            L_B = 3'b010;
          end
        end
        

        2'b11: begin
          state = 2'b00;
          L_A = 3'b100;
          L_B = 3'b001;
        end
      endcase
    end
  end

endmodule
module TC_Mealy(
  input wire CLK,
  input wire R,
  input wire T_A, T_B,
  output reg[2:0] L_A,
  output reg[2:0] L_B
);


  reg[1:0] state;
  

  initial begin

    state <= 2'b00;
    

    L_A = 3'b100;
    L_B = 3'b001;
  end
  

  always@(posedge CLK, posedge R) begin
    if(R) begin
      state = 2'b00;
      L_A = 3'b100;
      L_B = 3'b001;
    end
    else begin
      case(state)

        2'b00: begin
          if(!T_A) begin
            state = 2'b01;
            L_A = 3'b010;
            L_B = 3'b001;
          end
        end
        

        2'b01: begin
          state = 2'b10;
          L_A = 3'b001;
          L_B = 3'b100;
        end
        

        2'b10: begin
          if(!T_B) begin
            state = 2'b11;
            L_A = 3'b001;
            L_B = 3'b010;
          end
        end
        

        2'b11: begin
          state = 2'b00;
          L_A = 3'b100;
          L_B = 3'b001;
        end
      endcase
    end
  end

endmodule