data/full_repos/permissive/157667710/benchmark/AES-T1200/AES-T1200/src/TjIn/Trojan_Trigger.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/157667710/benchmark/AES-T1200/AES-T1200/src/TjIn/Trojan_Trigger.v:27: Duplicate declaration of signal: 'Tj_Trig'\n                                                                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg Tj_Trig;\n     ^~~~~~~\n        data/full_repos/permissive/157667710/benchmark/AES-T1200/AES-T1200/src/TjIn/Trojan_Trigger.v:24: ... Location of original declaration\n    output Tj_Trig\n           ^~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module Trojan_Trigger(
    input rst,
    input [127:0] out,
    output Tj_Trig
    );

	reg Tj_Trig;
	reg [127:0] Counter;
	
	always @(rst, out)
	begin
		if (rst == 1) begin
			Counter <= 0;
		end else begin
			Counter <= Counter + 1;
		end
	end

	always @(rst, Counter)
	begin
		if (rst == 1) begin
			Tj_Trig <= 0;
		end else if (Counter == 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff) begin
			Tj_Trig <= 1;
		end else begin
			Tj_Trig <= 0;		
		end
	end

endmodule
module Trojan_Trigger(
    input rst,
    input [127:0] out,
    output Tj_Trig
    );


	reg Tj_Trig;
	reg [127:0] Counter;
	
	always @(rst, out)
	begin
		if (rst == 1) begin
			Counter <= 0;
		end else begin
			Counter <= Counter + 1;
		end
	end

	always @(rst, Counter)
	begin
		if (rst == 1) begin
			Tj_Trig <= 0;
		end else if (Counter == 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff) begin
			Tj_Trig <= 1;
		end else begin
			Tj_Trig <= 0;		
		end
	end

endmodule