data/full_repos/permissive/162646941/src/counter.v
data/verilator_xmls/dcbb6350-357e-4bb4-b6d1-a95a350dd23e.xml
module counter(clk,clr,q);
  parameter width=16;
  input clk,clr; 
  output reg [width-1:0] q;

  always @ (posedge clk)
  begin
    if(clr)
      q <= 0;
    else
      q <= q + 1;
  end
endmodule
module counter(clk,clr,q);

  parameter width=16;
  input clk,clr; 
  output reg [width-1:0] q;

  always @ (posedge clk)
  begin
    if(clr)
      q <= 0;
    else
      q <= q + 1;
  end
endmodule