data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag/jtag_dmi_dsif.v
data/verilator_xmls/7eefb110-2932-4550-ad8b-6bdf1c427798.xml
module jtag_dmi_dsif#(
    parameter DMI_ADDR_WIDTH = 7,
    parameter DMI_DATA_WIDTH = 32,
    parameter DMI_OP_WIDTH = 2,
    parameter JTAG_DATA_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH),
    parameter TX_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH),
    parameter RX_WIDTH = (DMI_DATA_WIDTH+DMI_OP_WIDTH)
)(
    input jclk,
    

    input jcapture,
    input jreset,
    input jshift,
    input jupdate,
    output jtdo, 
    input jtdi,
    input jtms,
    input jsel,
    

    output reg jreq_vld,
    output [TX_WIDTH-1:0] jreq_data,
    input jreq_rdy,
    input jresp_vld,
    input [RX_WIDTH-1:0] jresp_data,
    output reg jresp_rdy,
    
    input dev_rst
);

reg [JTAG_DATA_WIDTH-1:0] jreq_buf;
reg [JTAG_DATA_WIDTH-1:0] jresp_buf;

reg req_avl;
reg req_done;
reg resp_avl;
reg [RX_WIDTH-1:0] resp_data;
reg [DMI_ADDR_WIDTH-1:0] resp_addr;

reg jreq_update;

assign jtdo = jresp_buf[0];
assign jreq_data = jreq_buf;

always@(posedge jclk or posedge dev_rst) begin
    if(dev_rst|jreset) begin
        jreq_vld <= 1'b0;
        jresp_rdy <= 1'b0;
    
        jreq_buf <= {JTAG_DATA_WIDTH{1'b0}};
        jresp_buf <= {JTAG_DATA_WIDTH{1'b0}};
        req_avl <= 1'b0;
        req_done <= 1'b0;
        resp_avl <= 1'b0;
        resp_data <= {RX_WIDTH{1'b0}};
        resp_addr <= {DMI_ADDR_WIDTH{1'b0}};
        
        jreq_update <= 1'b0;
    end
    else begin
        if(jsel) begin

            if(jcapture) begin
                if(resp_avl&(!req_done)) begin
                    jresp_buf[RX_WIDTH+:DMI_ADDR_WIDTH] <= resp_addr;
                    jresp_buf[0+:RX_WIDTH] <= resp_data;
                    req_done <= 1'b1;
                end
            end
            

            if(jshift&(~jreq_update)) begin
                jreq_buf <= {jtdi, jreq_buf[JTAG_DATA_WIDTH-1:1]};
                jresp_buf <= {jresp_buf[0], jresp_buf[JTAG_DATA_WIDTH-1:1]};
                if(jtms) begin
                    jreq_update <= 1'b1;
                end
            end
            


            
            if(jupdate) begin
                jreq_update <= 1'b0;
                jreq_vld <= 1'b0;
            end
            else if(jreq_update) begin
                jreq_update <= 1'b0;
                if(req_avl) begin
                    if(req_done) begin
                        req_avl <= 1'b0;
                        resp_avl <= 1'b0;
                        req_done <= 1'b0;
                        jresp_buf <= {JTAG_DATA_WIDTH{1'b0}};
                        resp_data <= {RX_WIDTH{1'b0}};
                        resp_addr <= {DMI_ADDR_WIDTH{1'b0}};
                    end
                end
                else begin
                    if(jreq_rdy) begin
                        if(jreq_buf[DMI_OP_WIDTH-1:0] == 2'b01) begin
                            jreq_vld <= 1'b1;
                            req_avl <= 1'b1;
                            resp_addr <= jreq_buf[(DMI_DATA_WIDTH+DMI_OP_WIDTH)+:DMI_ADDR_WIDTH];
                            jresp_buf[DMI_OP_WIDTH+:(DMI_ADDR_WIDTH+DMI_DATA_WIDTH)] <= {jreq_buf[(DMI_DATA_WIDTH+DMI_OP_WIDTH)+:DMI_ADDR_WIDTH], {DMI_DATA_WIDTH{1'b0}}};
                            jresp_buf[DMI_OP_WIDTH-1:0] <= 2'h3;
                        end
                        else if(jreq_buf[DMI_OP_WIDTH-1:0] == 2'b10) begin
                            jreq_vld <= 1'b1;
                            req_avl <= 1'b1;
                            resp_addr <= jreq_buf[(DMI_DATA_WIDTH+DMI_OP_WIDTH)+:DMI_ADDR_WIDTH];
                            jresp_buf[DMI_OP_WIDTH+:(DMI_ADDR_WIDTH+DMI_DATA_WIDTH)] <= {jreq_buf[(DMI_DATA_WIDTH+DMI_OP_WIDTH)+:DMI_ADDR_WIDTH], {DMI_DATA_WIDTH{1'b0}}};
                            jresp_buf[DMI_OP_WIDTH-1:0] <= 2'h3;
                        end
                    end
                end
            end
            
        end

        jresp_rdy <= 1'b1;
        if(jresp_vld&(req_avl)) begin
            resp_avl <= 1'b1;
            resp_data <= jresp_data;
        end
        
    end
end

endmodule
module jtag_dmi_dsif#(
    parameter DMI_ADDR_WIDTH = 7,
    parameter DMI_DATA_WIDTH = 32,
    parameter DMI_OP_WIDTH = 2,
    parameter JTAG_DATA_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH),
    parameter TX_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH),
    parameter RX_WIDTH = (DMI_DATA_WIDTH+DMI_OP_WIDTH)
)(
    input jclk,
    

    input jcapture,
    input jreset,
    input jshift,
    input jupdate,
    output jtdo, 
    input jtdi,
    input jtms,
    input jsel,
    

    output reg jreq_vld,
    output [TX_WIDTH-1:0] jreq_data,
    input jreq_rdy,
    input jresp_vld,
    input [RX_WIDTH-1:0] jresp_data,
    output reg jresp_rdy,
    
    input dev_rst
);


reg [JTAG_DATA_WIDTH-1:0] jreq_buf;
reg [JTAG_DATA_WIDTH-1:0] jresp_buf;

reg req_avl;
reg req_done;
reg resp_avl;
reg [RX_WIDTH-1:0] resp_data;
reg [DMI_ADDR_WIDTH-1:0] resp_addr;

reg jreq_update;

assign jtdo = jresp_buf[0];
assign jreq_data = jreq_buf;

always@(posedge jclk or posedge dev_rst) begin
    if(dev_rst|jreset) begin
        jreq_vld <= 1'b0;
        jresp_rdy <= 1'b0;
    
        jreq_buf <= {JTAG_DATA_WIDTH{1'b0}};
        jresp_buf <= {JTAG_DATA_WIDTH{1'b0}};
        req_avl <= 1'b0;
        req_done <= 1'b0;
        resp_avl <= 1'b0;
        resp_data <= {RX_WIDTH{1'b0}};
        resp_addr <= {DMI_ADDR_WIDTH{1'b0}};
        
        jreq_update <= 1'b0;
    end
    else begin
        if(jsel) begin

            if(jcapture) begin
                if(resp_avl&(!req_done)) begin
                    jresp_buf[RX_WIDTH+:DMI_ADDR_WIDTH] <= resp_addr;
                    jresp_buf[0+:RX_WIDTH] <= resp_data;
                    req_done <= 1'b1;
                end
            end
            

            if(jshift&(~jreq_update)) begin
                jreq_buf <= {jtdi, jreq_buf[JTAG_DATA_WIDTH-1:1]};
                jresp_buf <= {jresp_buf[0], jresp_buf[JTAG_DATA_WIDTH-1:1]};
                if(jtms) begin
                    jreq_update <= 1'b1;
                end
            end
            


            
            if(jupdate) begin
                jreq_update <= 1'b0;
                jreq_vld <= 1'b0;
            end
            else if(jreq_update) begin
                jreq_update <= 1'b0;
                if(req_avl) begin
                    if(req_done) begin
                        req_avl <= 1'b0;
                        resp_avl <= 1'b0;
                        req_done <= 1'b0;
                        jresp_buf <= {JTAG_DATA_WIDTH{1'b0}};
                        resp_data <= {RX_WIDTH{1'b0}};
                        resp_addr <= {DMI_ADDR_WIDTH{1'b0}};
                    end
                end
                else begin
                    if(jreq_rdy) begin
                        if(jreq_buf[DMI_OP_WIDTH-1:0] == 2'b01) begin
                            jreq_vld <= 1'b1;
                            req_avl <= 1'b1;
                            resp_addr <= jreq_buf[(DMI_DATA_WIDTH+DMI_OP_WIDTH)+:DMI_ADDR_WIDTH];
                            jresp_buf[DMI_OP_WIDTH+:(DMI_ADDR_WIDTH+DMI_DATA_WIDTH)] <= {jreq_buf[(DMI_DATA_WIDTH+DMI_OP_WIDTH)+:DMI_ADDR_WIDTH], {DMI_DATA_WIDTH{1'b0}}};
                            jresp_buf[DMI_OP_WIDTH-1:0] <= 2'h3;
                        end
                        else if(jreq_buf[DMI_OP_WIDTH-1:0] == 2'b10) begin
                            jreq_vld <= 1'b1;
                            req_avl <= 1'b1;
                            resp_addr <= jreq_buf[(DMI_DATA_WIDTH+DMI_OP_WIDTH)+:DMI_ADDR_WIDTH];
                            jresp_buf[DMI_OP_WIDTH+:(DMI_ADDR_WIDTH+DMI_DATA_WIDTH)] <= {jreq_buf[(DMI_DATA_WIDTH+DMI_OP_WIDTH)+:DMI_ADDR_WIDTH], {DMI_DATA_WIDTH{1'b0}}};
                            jresp_buf[DMI_OP_WIDTH-1:0] <= 2'h3;
                        end
                    end
                end
            end
            
        end

        jresp_rdy <= 1'b1;
        if(jresp_vld&(req_avl)) begin
            resp_avl <= 1'b1;
            resp_data <= jresp_data;
        end
        
    end
end

endmodule