data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top.v:51: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'PC\' generates 16 bits.\n                                                                                            : ... In instance top\nassign operand_A = (op_A_sel==1)?PC:(op_A_sel==0)?read_data1:PC+4;\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top.v:51: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'PC\' generates 16 bits.\n                                                                                            : ... In instance top\nassign operand_A = (op_A_sel==1)?PC:(op_A_sel==0)?read_data1:PC+4;\n                                                               ^\n%Error: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top.v:54: Cannot find file containing module: \'fetch\'\nfetch #(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/fetch\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/fetch.v\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/fetch.sv\n             fetch\n             fetch.v\n             fetch.sv\n             obj_dir/fetch\n             obj_dir/fetch.v\n             obj_dir/fetch.sv\n%Error: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top.v:64: Cannot find file containing module: \'decode\'\ndecode #(\n^~~~~~\n%Error: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top.v:102: Cannot find file containing module: \'regFile\'\nregFile regFile_inst (\n^~~~~~~\n%Error: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top.v:116: Cannot find file containing module: \'ALU\'\nALU alu_inst(\n^~~\n%Error: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top.v:126: Cannot find file containing module: \'ram\'\nram #(\n^~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module top #(
  parameter ADDRESS_BITS = 16
) (
  input clock,
  input reset,

  output [31:0] wb_data
);





wire [ADDRESS_BITS-1:0] PC;

wire next_PC_select;
wire [ADDRESS_BITS-1:0] target_PC;
wire [4:0] read_sel1;
wire [4:0] read_sel2;
wire [4:0] write_sel;
wire wEn;
wire branch_op;
wire [31:0] imm32;
wire [1:0] op_A_sel;
wire op_B_sel;
wire [5:0] ALU_Control;
wire mem_wEn;
wire wb_sel;


wire [31:0] read_data1;
wire [31:0] read_data2;

wire branch;
wire [31:0] JALR = imm32 + read_data1;
wire [ADDRESS_BITS-1:0] JALR_target;
assign JALR_target = {JALR[15:1],{1'b0}};
wire [31:0] ALU_result;

wire [31:0] instruction;
wire [31:0] d_read_data;

assign wb_data = (wb_sel==0)?ALU_result:d_read_data;
wire [31:0] operand_A;
assign operand_A = (op_A_sel==1)?PC:(op_A_sel==0)?read_data1:PC+4;
wire [31:0] operand_B;
assign operand_B = (op_B_sel==0)?read_data2:imm32;
fetch #(
  .ADDRESS_BITS(ADDRESS_BITS)
) fetch_inst (
  .clock(clock),
  .reset(reset),
  .next_PC_select(next_PC_select),
  .target_PC(target_PC),
  .PC(PC)
);

decode #(
  .ADDRESS_BITS(ADDRESS_BITS)
) decode_unit (


  .PC(PC),
  .instruction(instruction),


  .JALR_target(JALR_target),
  .branch(branch),


  .next_PC_select(next_PC_select),
  .target_PC(target_PC),


  .read_sel1(read_sel1),
  .read_sel2(read_sel2),
  .write_sel(write_sel),
  .wEn(wEn),


  .branch_op(branch_op),
  .imm32(imm32),
  .op_A_sel(op_A_sel),
  .op_B_sel(op_B_sel),
  .ALU_Control(ALU_Control),


  .mem_wEn(mem_wEn),


  .wb_sel(wb_sel)

);


regFile regFile_inst (
  .clock(clock),
  .reset(reset),
  .wEn(wEn),
  .write_data(wb_data),
  .read_sel1(read_sel1),
  .read_sel2(read_sel2),
  .write_sel(write_sel),
  .read_data1(read_data1),
  .read_data2(read_data2)
);



ALU alu_inst(
  .branch_op(branch_op),
  .ALU_Control(ALU_Control),
  .operand_A(operand_A),
  .operand_B(operand_B),
  .ALU_result(ALU_result),
  .branch(branch)
);


ram #(
  .ADDR_WIDTH(ADDRESS_BITS)
) main_memory (
  .clock(clock),


  .i_address(PC),
  .i_read_data(instruction),


  .wEn(mem_wEn),
  .d_address(ALU_result[15:0]),
  .d_write_data(read_data2),
  .d_read_data(d_read_data)
);

endmodule
module top #(
  parameter ADDRESS_BITS = 16
) (
  input clock,
  input reset,

  output [31:0] wb_data
);






wire [ADDRESS_BITS-1:0] PC;

wire next_PC_select;
wire [ADDRESS_BITS-1:0] target_PC;
wire [4:0] read_sel1;
wire [4:0] read_sel2;
wire [4:0] write_sel;
wire wEn;
wire branch_op;
wire [31:0] imm32;
wire [1:0] op_A_sel;
wire op_B_sel;
wire [5:0] ALU_Control;
wire mem_wEn;
wire wb_sel;


wire [31:0] read_data1;
wire [31:0] read_data2;

wire branch;
wire [31:0] JALR = imm32 + read_data1;
wire [ADDRESS_BITS-1:0] JALR_target;
assign JALR_target = {JALR[15:1],{1'b0}};
wire [31:0] ALU_result;

wire [31:0] instruction;
wire [31:0] d_read_data;

assign wb_data = (wb_sel==0)?ALU_result:d_read_data;
wire [31:0] operand_A;
assign operand_A = (op_A_sel==1)?PC:(op_A_sel==0)?read_data1:PC+4;
wire [31:0] operand_B;
assign operand_B = (op_B_sel==0)?read_data2:imm32;
fetch #(
  .ADDRESS_BITS(ADDRESS_BITS)
) fetch_inst (
  .clock(clock),
  .reset(reset),
  .next_PC_select(next_PC_select),
  .target_PC(target_PC),
  .PC(PC)
);

decode #(
  .ADDRESS_BITS(ADDRESS_BITS)
) decode_unit (


  .PC(PC),
  .instruction(instruction),


  .JALR_target(JALR_target),
  .branch(branch),


  .next_PC_select(next_PC_select),
  .target_PC(target_PC),


  .read_sel1(read_sel1),
  .read_sel2(read_sel2),
  .write_sel(write_sel),
  .wEn(wEn),


  .branch_op(branch_op),
  .imm32(imm32),
  .op_A_sel(op_A_sel),
  .op_B_sel(op_B_sel),
  .ALU_Control(ALU_Control),


  .mem_wEn(mem_wEn),


  .wb_sel(wb_sel)

);


regFile regFile_inst (
  .clock(clock),
  .reset(reset),
  .wEn(wEn),
  .write_data(wb_data),
  .read_sel1(read_sel1),
  .read_sel2(read_sel2),
  .write_sel(write_sel),
  .read_data1(read_data1),
  .read_data2(read_data2)
);



ALU alu_inst(
  .branch_op(branch_op),
  .ALU_Control(ALU_Control),
  .operand_A(operand_A),
  .operand_B(operand_B),
  .ALU_result(ALU_result),
  .branch(branch)
);


ram #(
  .ADDR_WIDTH(ADDRESS_BITS)
) main_memory (
  .clock(clock),


  .i_address(PC),
  .i_read_data(instruction),


  .wEn(mem_wEn),
  .d_address(ALU_result[15:0]),
  .d_write_data(read_data2),
  .d_read_data(d_read_data)
);

endmodule