data/full_repos/permissive/206783267/SPI/CNTLR/W25Q32JV_fastread_tb.v
 line:25: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206783267/SPI/CNTLR/W25Q32JV_fastread_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n forever #(CLK_CYCLE/2) clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/206783267/SPI/CNTLR/W25Q32JV_fastread_tb.v:24: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: data/full_repos/permissive/206783267/SPI/CNTLR/W25Q32JV_fastread_tb.v:32: syntax error, unexpected \'@\'\n @(posedge arstn)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/SPI/CNTLR/W25Q32JV_fastread_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE) fastread_start <= 1\'b0;\n  ^\n%Error: data/full_repos/permissive/206783267/SPI/CNTLR/W25Q32JV_fastread_tb.v:35: syntax error, unexpected \'@\'\n @(negedge fastread_done)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/SPI/CNTLR/W25Q32JV_fastread_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE) fastread_start <= 1\'b0;\n  ^\n%Error: data/full_repos/permissive/206783267/SPI/CNTLR/W25Q32JV_fastread_tb.v:45: syntax error, unexpected \'@\'\n @(posedge fastread_start)\n ^\n%Error: data/full_repos/permissive/206783267/SPI/CNTLR/W25Q32JV_fastread_tb.v:63: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Error: Exiting due to 5 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module W25Q32JV_fastread_tb();

parameter CLK_CYCLE = 20;

reg	clk, arstn;
reg	fastread_start;
reg	[23:0]	addr;
wire	sclk, csn, mosi;
reg		miso;
wire	fastread_done;
wire	[7:0]	data_out_1, data_out_2;


initial begin
	clk = 0;
	forever	#(CLK_CYCLE/2)	clk = ~clk;
end


initial begin
	arstn = 1'b0;
	@(posedge clk)
		#(CLK_CYCLE)	arstn = 1'b1;
end


task gen_fastread_start;
begin
	fastread_start = 1'b0;
	@(posedge arstn)
		#(CLK_CYCLE*100)	fastread_start <= 1'b1;
		#(CLK_CYCLE)	fastread_start <= 1'b0;
	@(negedge fastread_done)
		#(CLK_CYCLE*100)	fastread_start <= 1'b1;
		#(CLK_CYCLE)	fastread_start <= 1'b0;
end
endtask


task gen_fastread_addr;
begin
	addr = 'd0;
	@(posedge fastread_start)
		addr = 24'haaccee;
	@(posedge fastread_start)
		addr = 24'hbbddff;
	@(negedge fastread_done)
		#(CLK_CYCLE*100)	$finish;
end
endtask


initial begin
	miso = 1'b0;
end

always@(negedge sclk) begin
	miso = $random;
end

initial fork
	gen_fastread_start;
	gen_fastread_addr;
join

W25Q32JV_fastread DUT(
	.clk(clk),
	.arstn(arstn),
	.fastread_start(fastread_start),
	.addr(addr),
	.sclk(sclk),
	.csn(csn),
	.mosi(mosi),
	.miso(miso),
	.fastread_done(fastread_done),
	.data_out_1(data_out_1),
	.data_out_2(data_out_2)
	);

endmodule
module W25Q32JV_fastread_tb();


parameter CLK_CYCLE = 20;

reg	clk, arstn;
reg	fastread_start;
reg	[23:0]	addr;
wire	sclk, csn, mosi;
reg		miso;
wire	fastread_done;
wire	[7:0]	data_out_1, data_out_2;


initial begin
	clk = 0;
	forever	#(CLK_CYCLE/2)	clk = ~clk;
end


initial begin
	arstn = 1'b0;
	@(posedge clk)
		#(CLK_CYCLE)	arstn = 1'b1;
end


task gen_fastread_start;
begin
	fastread_start = 1'b0;
	@(posedge arstn)
		#(CLK_CYCLE*100)	fastread_start <= 1'b1;
		#(CLK_CYCLE)	fastread_start <= 1'b0;
	@(negedge fastread_done)
		#(CLK_CYCLE*100)	fastread_start <= 1'b1;
		#(CLK_CYCLE)	fastread_start <= 1'b0;
end
endtask


task gen_fastread_addr;
begin
	addr = 'd0;
	@(posedge fastread_start)
		addr = 24'haaccee;
	@(posedge fastread_start)
		addr = 24'hbbddff;
	@(negedge fastread_done)
		#(CLK_CYCLE*100)	$finish;
end
endtask


initial begin
	miso = 1'b0;
end

always@(negedge sclk) begin
	miso = $random;
end

initial fork
	gen_fastread_start;
	gen_fastread_addr;
join

W25Q32JV_fastread DUT(
	.clk(clk),
	.arstn(arstn),
	.fastread_start(fastread_start),
	.addr(addr),
	.sclk(sclk),
	.csn(csn),
	.mosi(mosi),
	.miso(miso),
	.fastread_done(fastread_done),
	.data_out_1(data_out_1),
	.data_out_2(data_out_2)
	);

endmodule