data/full_repos/permissive/114553631/src/data_mem.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/114553631/src/data_mem.v:4: Cannot find include file: ../src/def.v\n`include "../src/def.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v\n             data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v.v\n             data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v.sv\n             ../src/def.v\n             ../src/def.v.v\n             ../src/def.v.sv\n             obj_dir/../src/def.v\n             obj_dir/../src/def.v.v\n             obj_dir/../src/def.v.sv\n%Error: data/full_repos/permissive/114553631/src/data_mem.v:21: Define or directive not defined: \'`ILW\'\n        if (M_op==`ILW) begin\n                  ^~~~\n%Error: data/full_repos/permissive/114553631/src/data_mem.v:21: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (M_op==`ILW) begin\n                      ^\n%Error: data/full_repos/permissive/114553631/src/data_mem.v:23: Define or directive not defined: \'`ISW\'\n        end else if (M_op==`ISW) begin\n                           ^~~~\n%Error: Cannot continue\n'
module data_mem(
    output reg [31:0] m_valM,
    input [5:0] M_op,
    input [31:0] M_valE,
    input [31:0] M_valA
);
    parameter DM_DATA="../data/data_memory.txt";
    
    reg[31:0] data[0:63];

    initial begin
		$readmemh(DM_DATA, data, 0, 63);
	end

    always @(*) begin
        if (M_op==`ILW) begin
            m_valM <= data[M_valE[5:0]];
        end else if (M_op==`ISW) begin
            data[M_valE[5:0]] <= M_valA;
        end
    end
endmodule
module data_mem(
    output reg [31:0] m_valM,
    input [5:0] M_op,
    input [31:0] M_valE,
    input [31:0] M_valA
);

    parameter DM_DATA="../data/data_memory.txt";
    
    reg[31:0] data[0:63];

    initial begin
		$readmemh(DM_DATA, data, 0, 63);
	end

    always @(*) begin
        if (M_op==`ILW) begin
            m_valM <= data[M_valE[5:0]];
        end else if (M_op==`ISW) begin
            data[M_valE[5:0]] <= M_valA;
        end
    end
endmodule