data/full_repos/permissive/185824253/rtl/myCPU/div.v
1: b'%Warning-WIDTH: data/full_repos/permissive/185824253/rtl/myCPU/div.v:28: Operator XOR expects 33 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                       : ... In instance div\n assign abs_a  = ({32{a_sign}} ^ x) + a_sign;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/185824253/rtl/myCPU/div.v:28: Operator XOR expects 33 bits on the RHS, but RHS\'s VARREF \'x\' generates 32 bits.\n                                                                       : ... In instance div\n assign abs_a  = ({32{a_sign}} ^ x) + a_sign;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/185824253/rtl/myCPU/div.v:28: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'a_sign\' generates 1 bits.\n                                                                       : ... In instance div\n assign abs_a  = ({32{a_sign}} ^ x) + a_sign;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/185824253/rtl/myCPU/div.v:29: Operator XOR expects 33 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                       : ... In instance div\n assign abs_b  = ({32{b_sign}} ^ y) + b_sign;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/185824253/rtl/myCPU/div.v:29: Operator XOR expects 33 bits on the RHS, but RHS\'s VARREF \'y\' generates 32 bits.\n                                                                       : ... In instance div\n assign abs_b  = ({32{b_sign}} ^ y) + b_sign;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/185824253/rtl/myCPU/div.v:29: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'b_sign\' generates 1 bits.\n                                                                       : ... In instance div\n assign abs_b  = ({32{b_sign}} ^ y) + b_sign;\n                                    ^\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/div.v:40: Cannot find file containing module: \'cla_32\'\n cla_32 sub(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/185824253/rtl/myCPU,data/full_repos/permissive/185824253/cla_32\n             data/full_repos/permissive/185824253/rtl/myCPU,data/full_repos/permissive/185824253/cla_32.v\n             data/full_repos/permissive/185824253/rtl/myCPU,data/full_repos/permissive/185824253/cla_32.sv\n             cla_32\n             cla_32.v\n             cla_32.sv\n             obj_dir/cla_32\n             obj_dir/cla_32.v\n             obj_dir/cla_32.sv\n%Warning-WIDTH: data/full_repos/permissive/185824253/rtl/myCPU/div.v:89: Operator ASSIGNDLY expects 66 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h0\' generates 64 bits.\n                                                                       : ... In instance div\n   shift_A <= 64\'d0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/185824253/rtl/myCPU/div.v:98: Operator ASSIGNDLY expects 66 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                       : ... In instance div\n    shift_A <= {{32{1\'b0}}, x};\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/185824253/rtl/myCPU/div.v:120: Operator NOT expects 34 bits on the LHS, but LHS\'s VARREF \'B\' generates 33 bits.\n                                                                        : ... In instance div\n assign neg_r = A[65] ? (A[65:33] + ~B) : A[65:33];\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/185824253/rtl/myCPU/div.v:120: Operator COND expects 34 bits on the Conditional False, but Conditional False\'s SEL generates 33 bits.\n                                                                        : ... In instance div\n assign neg_r = A[65] ? (A[65:33] + ~B) : A[65:33];\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/185824253/rtl/myCPU/div.v:122: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'s_sign\' generates 1 bits.\n                                                                        : ... In instance div\n assign s = {32{complete}} & (({32{s_sign}}^A[31:0]) + s_sign);\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/185824253/rtl/myCPU/div.v:123: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'r_sign\' generates 1 bits.\n                                                                        : ... In instance div\n assign r = {32{complete}} & (({32{r_sign}}^neg_r[31:0]) + r_sign);\n                                                         ^\n%Error: Exiting due to 1 error(s), 12 warning(s)\n'
module div (
	input         div_clk,
	input         resetn,
	input         div,
	input         div_signed,
	input  [31:0] x,
	input  [31:0] y,
	output [31:0] s,
	output [31:0] r,
	output        complete
);

	reg  [65:0] A;
	reg  [65:0] shift_A;
	reg  [32:0] B;
	reg  [ 5:0] cnt; 
	wire [32:0] abs_a;
	wire [32:0] abs_b;
	wire        a_sign;
	wire        b_sign;

	assign a_sign = x[31] & div_signed;
	assign b_sign = y[31] & div_signed;
	assign abs_a  = ({32{a_sign}} ^ x) + a_sign;
	assign abs_b  = ({32{b_sign}} ^ y) + b_sign;



	wire [32:0] sub_result;
	wire        cin;
	wire        cout;

	assign cin = 1'b0;
	assign sub_result[32] = shift_A[65] ^ B[32] ^ cout;

	cla_32 sub(
		.A(shift_A[64:33]),
		.B(B[31:0]),
		.cin(cin),
		.result(sub_result[31:0]),
		.cout(cout)
	);

	wire [32:0] result;

	assign result = sub_result[32] ? shift_A[65:33] : sub_result;


	reg c_state, n_state;

	always @(posedge div_clk) 
	begin
		if (!resetn) 
			c_state <= 1'b0;
		else 
			c_state <= n_state;
	end

	always @(*) 
	begin
		if (!resetn) 
		  n_state <= 1'b0;
		else begin
			case(c_state)
				1'b0: 
				begin
					if (div) n_state <= 1'b1;
					else n_state <= 1'b0;
				end
				1'b1: 
				begin
					if (complete) n_state <= 1'b0;
					else n_state <= 1'b1;
				end
				default:
                    n_state <= 1'b0;
			endcase
		end
	end

	reg s_sign, r_sign;

	always @(posedge div_clk) begin
		if (!resetn) begin
			shift_A <= 64'd0;
			B <= 33'd0;
			cnt <= 6'd0;
			A <= 66'd0;
			s_sign <= 1'b0;
			r_sign <= 1'b0;
		end
		else begin
			if (c_state == 1'b0) begin
				shift_A <= {{32{1'b0}}, x};
				B <= ~abs_b + 1'b1;
				cnt <= 6'd1;
				A <= {33'd0, abs_a};
				s_sign <= div_signed & (x[31] ^ y[31]);
				r_sign <= div_signed & x[31];
			end

			else begin
				A <= {result[32:0], A[31:0], !sub_result[32]};

				shift_A <= {result[31:0], A[31:0], !sub_result[32], 1'b0};
				B <= B;
				cnt <= cnt + 1;
				s_sign <= s_sign;
				r_sign <= r_sign;
			end
		end
	end

	wire [33:0] neg_r;

	assign neg_r = A[65] ? (A[65:33] + ~B) : A[65:33];

	assign s = {32{complete}} & (({32{s_sign}}^A[31:0]) + s_sign);
	assign r = {32{complete}} & (({32{r_sign}}^neg_r[31:0]) + r_sign);
	assign complete = (cnt == 6'd34);


endmodule
module div (
	input         div_clk,
	input         resetn,
	input         div,
	input         div_signed,
	input  [31:0] x,
	input  [31:0] y,
	output [31:0] s,
	output [31:0] r,
	output        complete
);


	reg  [65:0] A;
	reg  [65:0] shift_A;
	reg  [32:0] B;
	reg  [ 5:0] cnt; 
	wire [32:0] abs_a;
	wire [32:0] abs_b;
	wire        a_sign;
	wire        b_sign;

	assign a_sign = x[31] & div_signed;
	assign b_sign = y[31] & div_signed;
	assign abs_a  = ({32{a_sign}} ^ x) + a_sign;
	assign abs_b  = ({32{b_sign}} ^ y) + b_sign;



	wire [32:0] sub_result;
	wire        cin;
	wire        cout;

	assign cin = 1'b0;
	assign sub_result[32] = shift_A[65] ^ B[32] ^ cout;

	cla_32 sub(
		.A(shift_A[64:33]),
		.B(B[31:0]),
		.cin(cin),
		.result(sub_result[31:0]),
		.cout(cout)
	);

	wire [32:0] result;

	assign result = sub_result[32] ? shift_A[65:33] : sub_result;


	reg c_state, n_state;

	always @(posedge div_clk) 
	begin
		if (!resetn) 
			c_state <= 1'b0;
		else 
			c_state <= n_state;
	end

	always @(*) 
	begin
		if (!resetn) 
		  n_state <= 1'b0;
		else begin
			case(c_state)
				1'b0: 
				begin
					if (div) n_state <= 1'b1;
					else n_state <= 1'b0;
				end
				1'b1: 
				begin
					if (complete) n_state <= 1'b0;
					else n_state <= 1'b1;
				end
				default:
                    n_state <= 1'b0;
			endcase
		end
	end

	reg s_sign, r_sign;

	always @(posedge div_clk) begin
		if (!resetn) begin
			shift_A <= 64'd0;
			B <= 33'd0;
			cnt <= 6'd0;
			A <= 66'd0;
			s_sign <= 1'b0;
			r_sign <= 1'b0;
		end
		else begin
			if (c_state == 1'b0) begin
				shift_A <= {{32{1'b0}}, x};
				B <= ~abs_b + 1'b1;
				cnt <= 6'd1;
				A <= {33'd0, abs_a};
				s_sign <= div_signed & (x[31] ^ y[31]);
				r_sign <= div_signed & x[31];
			end

			else begin
				A <= {result[32:0], A[31:0], !sub_result[32]};

				shift_A <= {result[31:0], A[31:0], !sub_result[32], 1'b0};
				B <= B;
				cnt <= cnt + 1;
				s_sign <= s_sign;
				r_sign <= r_sign;
			end
		end
	end

	wire [33:0] neg_r;

	assign neg_r = A[65] ? (A[65:33] + ~B) : A[65:33];

	assign s = {32{complete}} & (({32{s_sign}}^A[31:0]) + s_sign);
	assign r = {32{complete}} & (({32{r_sign}}^neg_r[31:0]) + r_sign);
	assign complete = (cnt == 6'd34);


endmodule