data/full_repos/permissive/173232294/hdcp_engine.srcs/sources_1/imports/srcs-origin/hdcp_lfsr.v
1: b"%Error: data/full_repos/permissive/173232294/hdcp_engine.srcs/sources_1/imports/srcs-origin/hdcp_lfsr.v:154: Cannot find file containing module: 'shuffle_network'\n   shuffle_network sh0 ( .clk(clk), .reset(reset),\n   ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173232294/hdcp_engine.srcs/sources_1/imports/srcs-origin,data/full_repos/permissive/173232294/shuffle_network\n             data/full_repos/permissive/173232294/hdcp_engine.srcs/sources_1/imports/srcs-origin,data/full_repos/permissive/173232294/shuffle_network.v\n             data/full_repos/permissive/173232294/hdcp_engine.srcs/sources_1/imports/srcs-origin,data/full_repos/permissive/173232294/shuffle_network.sv\n             shuffle_network\n             shuffle_network.v\n             shuffle_network.sv\n             obj_dir/shuffle_network\n             obj_dir/shuffle_network.v\n             obj_dir/shuffle_network.sv\n%Error: data/full_repos/permissive/173232294/hdcp_engine.srcs/sources_1/imports/srcs-origin/hdcp_lfsr.v:162: Cannot find file containing module: 'shuffle_network'\n   shuffle_network sh1 ( .clk(clk), .reset(reset),\n   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173232294/hdcp_engine.srcs/sources_1/imports/srcs-origin/hdcp_lfsr.v:170: Cannot find file containing module: 'shuffle_network'\n   shuffle_network sh2 ( .clk(clk), .reset(reset),\n   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173232294/hdcp_engine.srcs/sources_1/imports/srcs-origin/hdcp_lfsr.v:178: Cannot find file containing module: 'shuffle_network'\n   shuffle_network sh3 ( .clk(clk), .reset(reset),\n   ^~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module hdcp_lfsr(
		   input wire    clk,
		   input wire    reset,
		   
		   input wire [55:0]  iv,

		   input  wire   init_iv,
		   input  wire   advance,
		   output wire   onebit
		   );

   reg [12:0] 			 lfsr0;
   reg [13:0] 			 lfsr1;
   reg [15:0] 			 lfsr2;
   reg [16:0] 			 lfsr3;

   wire [3:0] 			 comb_tap0;
   wire [3:0] 			 comb_tap1;
   wire [3:0] 			 comb_tap2;
   
   always @(posedge clk) begin
      if( reset == 1 ) begin
	 lfsr0 <= 13'b0;
	 lfsr1 <= 14'b0;
	 lfsr2 <= 16'b0;
	 lfsr3 <= 17'b0;
      end else begin
	 if( init_iv ) begin

	    lfsr0[12:0] <= {~iv[6],iv[11:0]};
	    lfsr1[13:0] <= {~iv[18],iv[24:12]};
	    lfsr2[15:0] <= {~iv[32],iv[39:25]};
	    lfsr3[16:0] <= {~iv[47],iv[55:40]};
	 end else if( advance ) begin


	    lfsr0[0 ] <= lfsr0[4] ^ lfsr0[8] ^ lfsr0[10] ^ lfsr0[12];
	    lfsr0[1 ] <= lfsr0[0 ];
	    lfsr0[2 ] <= lfsr0[1 ];
	    lfsr0[3 ] <= lfsr0[2 ];
	    lfsr0[4 ] <= lfsr0[3 ];
	    lfsr0[5 ] <= lfsr0[4 ];
	    lfsr0[6 ] <= lfsr0[5 ];
	    lfsr0[7 ] <= lfsr0[6 ];
	    lfsr0[8 ] <= lfsr0[7 ];
	    lfsr0[9 ] <= lfsr0[8 ];
	    lfsr0[10] <= lfsr0[9 ];
	    lfsr0[11] <= lfsr0[10];
	    lfsr0[12] <= lfsr0[11];



	    lfsr1[0 ] <= lfsr1[3] ^ lfsr1[5] ^ lfsr1[6] ^ lfsr1[9] ^ lfsr1[10] ^ lfsr1[13];
	    lfsr1[1 ] <= lfsr1[0 ];
	    lfsr1[2 ] <= lfsr1[1 ];
	    lfsr1[3 ] <= lfsr1[2 ];
	    lfsr1[4 ] <= lfsr1[3 ];
	    lfsr1[5 ] <= lfsr1[4 ];
	    lfsr1[6 ] <= lfsr1[5 ];
	    lfsr1[7 ] <= lfsr1[6 ];
	    lfsr1[8 ] <= lfsr1[7 ];
	    lfsr1[9 ] <= lfsr1[8 ];
	    lfsr1[10] <= lfsr1[9 ];
	    lfsr1[11] <= lfsr1[10];
	    lfsr1[12] <= lfsr1[11];
	    lfsr1[13] <= lfsr1[12];



	    lfsr2[0 ] <= lfsr2[4] ^ lfsr2[6] ^ lfsr2[7] ^ lfsr2[11] ^ lfsr2[14] ^ lfsr2[15];
	    lfsr2[1 ] <= lfsr2[0 ];
	    lfsr2[2 ] <= lfsr2[1 ];
	    lfsr2[3 ] <= lfsr2[2 ];
	    lfsr2[4 ] <= lfsr2[3 ];
	    lfsr2[5 ] <= lfsr2[4 ];
	    lfsr2[6 ] <= lfsr2[5 ];
	    lfsr2[7 ] <= lfsr2[6 ];
	    lfsr2[8 ] <= lfsr2[7 ];
	    lfsr2[9 ] <= lfsr2[8 ];
	    lfsr2[10] <= lfsr2[9 ];
	    lfsr2[11] <= lfsr2[10];
	    lfsr2[12] <= lfsr2[11];
	    lfsr2[13] <= lfsr2[12];
	    lfsr2[14] <= lfsr2[13];
	    lfsr2[15] <= lfsr2[14];



	    lfsr3[0 ] <= lfsr3[4] ^ lfsr3[10] ^ lfsr3[14] ^ lfsr3[16];
	    lfsr3[1 ] <= lfsr3[0 ];
	    lfsr3[2 ] <= lfsr3[1 ];
	    lfsr3[3 ] <= lfsr3[2 ];
	    lfsr3[4 ] <= lfsr3[3 ];
	    lfsr3[5 ] <= lfsr3[4 ];
	    lfsr3[6 ] <= lfsr3[5 ];
	    lfsr3[7 ] <= lfsr3[6 ];
	    lfsr3[8 ] <= lfsr3[7 ];
	    lfsr3[9 ] <= lfsr3[8 ];
	    lfsr3[10] <= lfsr3[9 ];
	    lfsr3[11] <= lfsr3[10];
	    lfsr3[12] <= lfsr3[11];
	    lfsr3[13] <= lfsr3[12];
	    lfsr3[14] <= lfsr3[13];
	    lfsr3[15] <= lfsr3[14];
	    lfsr3[16] <= lfsr3[15];
	 end else begin

	    lfsr0 <= lfsr0;
	    lfsr1 <= lfsr1;
	    lfsr2 <= lfsr2;
	    lfsr3 <= lfsr3;
	 end
      end
   end

   assign comb_tap0[0] = lfsr0[3];
   assign comb_tap0[1] = lfsr1[4];
   assign comb_tap0[2] = lfsr2[5];
   assign comb_tap0[3] = lfsr3[5];
   
   assign comb_tap1[0] = lfsr0[7];
   assign comb_tap1[1] = lfsr1[8];
   assign comb_tap1[2] = lfsr2[9];
   assign comb_tap1[3] = lfsr3[11];
   
   assign comb_tap2[0] = lfsr0[12];
   assign comb_tap2[1] = lfsr1[13];
   assign comb_tap2[2] = lfsr2[15];
   assign comb_tap2[3] = lfsr3[16];

   wire [3:0] sh_dout;
   shuffle_network sh0 ( .clk(clk), .reset(reset),
			 .din(comb_tap0[0] ^ comb_tap0[1] ^ comb_tap0[2] ^ comb_tap0[3]),
			 .sel(comb_tap1[0]),
			 .advance(advance),
			 .init_iv(init_iv),
			 .dout(sh_dout[0])
			 );
   
   shuffle_network sh1 ( .clk(clk), .reset(reset),
			 .din(sh_dout[0]),
			 .sel(comb_tap1[1]),
			 .advance(advance),
			 .init_iv(init_iv),
			 .dout(sh_dout[1])
			 );
   
   shuffle_network sh2 ( .clk(clk), .reset(reset),
			 .din(sh_dout[1]),
			 .sel(comb_tap1[2]),
			 .advance(advance),
			 .init_iv(init_iv),
			 .dout(sh_dout[2])
			 );

   shuffle_network sh3 ( .clk(clk), .reset(reset),
			 .din(sh_dout[2]),
			 .sel(comb_tap1[3]),
			 .advance(advance),
			 .init_iv(init_iv),
			 .dout(sh_dout[3])
			 );
   
   assign onebit = sh_dout[3] ^ comb_tap2[0] ^ comb_tap2[1] ^ comb_tap2[2] ^ comb_tap2[3];
   
endmodule
module hdcp_lfsr(
		   input wire    clk,
		   input wire    reset,
		   
		   input wire [55:0]  iv,

		   input  wire   init_iv,
		   input  wire   advance,
		   output wire   onebit
		   );


   reg [12:0] 			 lfsr0;
   reg [13:0] 			 lfsr1;
   reg [15:0] 			 lfsr2;
   reg [16:0] 			 lfsr3;

   wire [3:0] 			 comb_tap0;
   wire [3:0] 			 comb_tap1;
   wire [3:0] 			 comb_tap2;
   
   always @(posedge clk) begin
      if( reset == 1 ) begin
	 lfsr0 <= 13'b0;
	 lfsr1 <= 14'b0;
	 lfsr2 <= 16'b0;
	 lfsr3 <= 17'b0;
      end else begin
	 if( init_iv ) begin

	    lfsr0[12:0] <= {~iv[6],iv[11:0]};
	    lfsr1[13:0] <= {~iv[18],iv[24:12]};
	    lfsr2[15:0] <= {~iv[32],iv[39:25]};
	    lfsr3[16:0] <= {~iv[47],iv[55:40]};
	 end else if( advance ) begin


	    lfsr0[0 ] <= lfsr0[4] ^ lfsr0[8] ^ lfsr0[10] ^ lfsr0[12];
	    lfsr0[1 ] <= lfsr0[0 ];
	    lfsr0[2 ] <= lfsr0[1 ];
	    lfsr0[3 ] <= lfsr0[2 ];
	    lfsr0[4 ] <= lfsr0[3 ];
	    lfsr0[5 ] <= lfsr0[4 ];
	    lfsr0[6 ] <= lfsr0[5 ];
	    lfsr0[7 ] <= lfsr0[6 ];
	    lfsr0[8 ] <= lfsr0[7 ];
	    lfsr0[9 ] <= lfsr0[8 ];
	    lfsr0[10] <= lfsr0[9 ];
	    lfsr0[11] <= lfsr0[10];
	    lfsr0[12] <= lfsr0[11];



	    lfsr1[0 ] <= lfsr1[3] ^ lfsr1[5] ^ lfsr1[6] ^ lfsr1[9] ^ lfsr1[10] ^ lfsr1[13];
	    lfsr1[1 ] <= lfsr1[0 ];
	    lfsr1[2 ] <= lfsr1[1 ];
	    lfsr1[3 ] <= lfsr1[2 ];
	    lfsr1[4 ] <= lfsr1[3 ];
	    lfsr1[5 ] <= lfsr1[4 ];
	    lfsr1[6 ] <= lfsr1[5 ];
	    lfsr1[7 ] <= lfsr1[6 ];
	    lfsr1[8 ] <= lfsr1[7 ];
	    lfsr1[9 ] <= lfsr1[8 ];
	    lfsr1[10] <= lfsr1[9 ];
	    lfsr1[11] <= lfsr1[10];
	    lfsr1[12] <= lfsr1[11];
	    lfsr1[13] <= lfsr1[12];



	    lfsr2[0 ] <= lfsr2[4] ^ lfsr2[6] ^ lfsr2[7] ^ lfsr2[11] ^ lfsr2[14] ^ lfsr2[15];
	    lfsr2[1 ] <= lfsr2[0 ];
	    lfsr2[2 ] <= lfsr2[1 ];
	    lfsr2[3 ] <= lfsr2[2 ];
	    lfsr2[4 ] <= lfsr2[3 ];
	    lfsr2[5 ] <= lfsr2[4 ];
	    lfsr2[6 ] <= lfsr2[5 ];
	    lfsr2[7 ] <= lfsr2[6 ];
	    lfsr2[8 ] <= lfsr2[7 ];
	    lfsr2[9 ] <= lfsr2[8 ];
	    lfsr2[10] <= lfsr2[9 ];
	    lfsr2[11] <= lfsr2[10];
	    lfsr2[12] <= lfsr2[11];
	    lfsr2[13] <= lfsr2[12];
	    lfsr2[14] <= lfsr2[13];
	    lfsr2[15] <= lfsr2[14];



	    lfsr3[0 ] <= lfsr3[4] ^ lfsr3[10] ^ lfsr3[14] ^ lfsr3[16];
	    lfsr3[1 ] <= lfsr3[0 ];
	    lfsr3[2 ] <= lfsr3[1 ];
	    lfsr3[3 ] <= lfsr3[2 ];
	    lfsr3[4 ] <= lfsr3[3 ];
	    lfsr3[5 ] <= lfsr3[4 ];
	    lfsr3[6 ] <= lfsr3[5 ];
	    lfsr3[7 ] <= lfsr3[6 ];
	    lfsr3[8 ] <= lfsr3[7 ];
	    lfsr3[9 ] <= lfsr3[8 ];
	    lfsr3[10] <= lfsr3[9 ];
	    lfsr3[11] <= lfsr3[10];
	    lfsr3[12] <= lfsr3[11];
	    lfsr3[13] <= lfsr3[12];
	    lfsr3[14] <= lfsr3[13];
	    lfsr3[15] <= lfsr3[14];
	    lfsr3[16] <= lfsr3[15];
	 end else begin

	    lfsr0 <= lfsr0;
	    lfsr1 <= lfsr1;
	    lfsr2 <= lfsr2;
	    lfsr3 <= lfsr3;
	 end
      end
   end

   assign comb_tap0[0] = lfsr0[3];
   assign comb_tap0[1] = lfsr1[4];
   assign comb_tap0[2] = lfsr2[5];
   assign comb_tap0[3] = lfsr3[5];
   
   assign comb_tap1[0] = lfsr0[7];
   assign comb_tap1[1] = lfsr1[8];
   assign comb_tap1[2] = lfsr2[9];
   assign comb_tap1[3] = lfsr3[11];
   
   assign comb_tap2[0] = lfsr0[12];
   assign comb_tap2[1] = lfsr1[13];
   assign comb_tap2[2] = lfsr2[15];
   assign comb_tap2[3] = lfsr3[16];

   wire [3:0] sh_dout;
   shuffle_network sh0 ( .clk(clk), .reset(reset),
			 .din(comb_tap0[0] ^ comb_tap0[1] ^ comb_tap0[2] ^ comb_tap0[3]),
			 .sel(comb_tap1[0]),
			 .advance(advance),
			 .init_iv(init_iv),
			 .dout(sh_dout[0])
			 );
   
   shuffle_network sh1 ( .clk(clk), .reset(reset),
			 .din(sh_dout[0]),
			 .sel(comb_tap1[1]),
			 .advance(advance),
			 .init_iv(init_iv),
			 .dout(sh_dout[1])
			 );
   
   shuffle_network sh2 ( .clk(clk), .reset(reset),
			 .din(sh_dout[1]),
			 .sel(comb_tap1[2]),
			 .advance(advance),
			 .init_iv(init_iv),
			 .dout(sh_dout[2])
			 );

   shuffle_network sh3 ( .clk(clk), .reset(reset),
			 .din(sh_dout[2]),
			 .sel(comb_tap1[3]),
			 .advance(advance),
			 .init_iv(init_iv),
			 .dout(sh_dout[3])
			 );
   
   assign onebit = sh_dout[3] ^ comb_tap2[0] ^ comb_tap2[1] ^ comb_tap2[2] ^ comb_tap2[3];
   
endmodule