data/full_repos/permissive/19591557/modules/link_speed_interface/spio_link_speed_halver.v
data/verilator_xmls/ec8bb199-0877-4d6c-867f-4c5ad9d89cde.xml
module spio_link_speed_halver #( parameter PKT_BITS = 72 )
                               (
                                 input wire RESET_IN

                               , input wire SCLK_IN


                               , input wire FCLK_IN

                               , input  wire [PKT_BITS-1:0] DATA_IN
                               , input  wire                VLD_IN
                               , output reg                 RDY_OUT

                               , output reg  [PKT_BITS-1:0] DATA_OUT
                               , output reg                 VLD_OUT
                               , input  wire                RDY_IN
                               );








reg sclk_i;

reg sclk_toggler_i;
reg sclk_started_i;
always @ (posedge SCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			sclk_toggler_i <= 1'b0;
			sclk_started_i <= 1'b0;
		end
	else
		begin
			sclk_toggler_i <= ~sclk_toggler_i;
			sclk_started_i <= 1'b1;
		end

reg last_sclk_toggler_i;
always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		last_sclk_toggler_i <= 1'b0;
	else
		last_sclk_toggler_i <= sclk_toggler_i;



always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		sclk_i <= 1'b0;
	else
		sclk_i <= sclk_started_i && (last_sclk_toggler_i == sclk_toggler_i);







wire rdy_in_i;
reg last_rdy_in_i;
always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN) last_rdy_in_i <= 1'b0;
	else          last_rdy_in_i <= RDY_IN;
assign rdy_in_i = sclk_i ? last_rdy_in_i : RDY_IN;






























wire wait_i = VLD_OUT && (!rdy_in_i);



wire park_i = VLD_IN && RDY_OUT && wait_i;



reg [PKT_BITS-1:0] parked_data_i;
always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		parked_data_i <= {PKT_BITS{1'bX}};
	else if (park_i)
		parked_data_i <= DATA_IN;














reg parked_i;
always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		parked_i <= 1'b0;
	else
		if (park_i)
			parked_i <= 1'b1;
		else if (!sclk_i && !wait_i)
			parked_i <= 1'b0;



wire [PKT_BITS-1:0] data_i = (parked_i ? parked_data_i : DATA_IN);
wire                vld_i  = (parked_i ?          1'b1 : VLD_IN);









always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		RDY_OUT <= 1'b0;
	else
		if ((VLD_IN && RDY_OUT) || parked_i)
			RDY_OUT <= 1'b0;
		else if (sclk_i && rdy_in_i)
			RDY_OUT <= 1'b1;








always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		DATA_OUT <= {PKT_BITS{1'bX}};
	else
		if ((vld_i && RDY_OUT && !wait_i) || (parked_i && rdy_in_i))
			DATA_OUT <= data_i;









reg delayed_transfer_i;
always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		delayed_transfer_i <= 1'b0;
	else
		delayed_transfer_i <= (vld_i && RDY_OUT && sclk_i);







always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		VLD_OUT <= 1'b0;
	else 
		if (!sclk_i)
			VLD_OUT <= parked_i || wait_i || (vld_i && RDY_OUT) || delayed_transfer_i;


endmodule
module spio_link_speed_halver #( parameter PKT_BITS = 72 )
                               (
                                 input wire RESET_IN

                               , input wire SCLK_IN


                               , input wire FCLK_IN

                               , input  wire [PKT_BITS-1:0] DATA_IN
                               , input  wire                VLD_IN
                               , output reg                 RDY_OUT

                               , output reg  [PKT_BITS-1:0] DATA_OUT
                               , output reg                 VLD_OUT
                               , input  wire                RDY_IN
                               );









reg sclk_i;

reg sclk_toggler_i;
reg sclk_started_i;
always @ (posedge SCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			sclk_toggler_i <= 1'b0;
			sclk_started_i <= 1'b0;
		end
	else
		begin
			sclk_toggler_i <= ~sclk_toggler_i;
			sclk_started_i <= 1'b1;
		end

reg last_sclk_toggler_i;
always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		last_sclk_toggler_i <= 1'b0;
	else
		last_sclk_toggler_i <= sclk_toggler_i;



always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		sclk_i <= 1'b0;
	else
		sclk_i <= sclk_started_i && (last_sclk_toggler_i == sclk_toggler_i);







wire rdy_in_i;
reg last_rdy_in_i;
always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN) last_rdy_in_i <= 1'b0;
	else          last_rdy_in_i <= RDY_IN;
assign rdy_in_i = sclk_i ? last_rdy_in_i : RDY_IN;






























wire wait_i = VLD_OUT && (!rdy_in_i);



wire park_i = VLD_IN && RDY_OUT && wait_i;



reg [PKT_BITS-1:0] parked_data_i;
always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		parked_data_i <= {PKT_BITS{1'bX}};
	else if (park_i)
		parked_data_i <= DATA_IN;














reg parked_i;
always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		parked_i <= 1'b0;
	else
		if (park_i)
			parked_i <= 1'b1;
		else if (!sclk_i && !wait_i)
			parked_i <= 1'b0;



wire [PKT_BITS-1:0] data_i = (parked_i ? parked_data_i : DATA_IN);
wire                vld_i  = (parked_i ?          1'b1 : VLD_IN);









always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		RDY_OUT <= 1'b0;
	else
		if ((VLD_IN && RDY_OUT) || parked_i)
			RDY_OUT <= 1'b0;
		else if (sclk_i && rdy_in_i)
			RDY_OUT <= 1'b1;








always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		DATA_OUT <= {PKT_BITS{1'bX}};
	else
		if ((vld_i && RDY_OUT && !wait_i) || (parked_i && rdy_in_i))
			DATA_OUT <= data_i;









reg delayed_transfer_i;
always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		delayed_transfer_i <= 1'b0;
	else
		delayed_transfer_i <= (vld_i && RDY_OUT && sclk_i);







always @ (posedge FCLK_IN, posedge RESET_IN)
	if (RESET_IN)
		VLD_OUT <= 1'b0;
	else 
		if (!sclk_i)
			VLD_OUT <= parked_i || wait_i || (vld_i && RDY_OUT) || delayed_transfer_i;


endmodule