data/full_repos/permissive/196412397/7segment_tb.v
 line:23: before: ","
1: b'%Error: data/full_repos/permissive/196412397/7segment_tb.v:1: Cannot find include file: 7segment.v\n`include "7segment.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/7segment.v\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/7segment.v.v\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/7segment.v.sv\n             7segment.v\n             7segment.v.v\n             7segment.v.sv\n             obj_dir/7segment.v\n             obj_dir/7segment.v.v\n             obj_dir/7segment.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/196412397/7segment_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk <= ~clk; \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/196412397/7segment_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nalways #40 sw <= sw + 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/196412397/7segment_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Error: data/full_repos/permissive/196412397/7segment_tb.v:26: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("wave.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/196412397/7segment_tb.v:27: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0);\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module bin_7segment_tb();

reg clk = 1'b0;
reg [15:0]  sw = 'b0;
wire [6:0]   seg;
wire [3:0]   an;
wire dp;

always #1 clk <= ~clk; 

always #40 sw <= sw + 1;

  initial
  begin
    #1000;
    $finish();
  end
    
  initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
    $display("----------------------------------------------");
    $display(" ");
  end

bin_7segment test_unit1(
    .clk(clk),
    .sw(sw),
    .seg(seg),
    .an(an),
    .dp(dp)
);



endmodule
module bin_7segment_tb();


reg clk = 1'b0;
reg [15:0]  sw = 'b0;
wire [6:0]   seg;
wire [3:0]   an;
wire dp;

always #1 clk <= ~clk; 

always #40 sw <= sw + 1;

  initial
  begin
    #1000;
    $finish();
  end
    
  initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
    $display("----------------------------------------------");
    $display(" ");
  end

bin_7segment test_unit1(
    .clk(clk),
    .sw(sw),
    .seg(seg),
    .an(an),
    .dp(dp)
);



endmodule