data/full_repos/permissive/197614203/code/A500 FastRAM Verilog.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/197614203/code/A500\n        ... Looked in:\n             data/full_repos/permissive/197614203/code,data/full_repos/permissive/197614203/data/full_repos/permissive/197614203/code/A500\n             data/full_repos/permissive/197614203/code,data/full_repos/permissive/197614203/data/full_repos/permissive/197614203/code/A500.v\n             data/full_repos/permissive/197614203/code,data/full_repos/permissive/197614203/data/full_repos/permissive/197614203/code/A500.sv\n             data/full_repos/permissive/197614203/code/A500\n             data/full_repos/permissive/197614203/code/A500.v\n             data/full_repos/permissive/197614203/code/A500.sv\n             obj_dir/data/full_repos/permissive/197614203/code/A500\n             obj_dir/data/full_repos/permissive/197614203/code/A500.v\n             obj_dir/data/full_repos/permissive/197614203/code/A500.sv\n%Error: Cannot find file containing module: FastRAM\n%Error: Cannot find file containing module: Verilog.v\n%Error: Exiting due to 3 error(s)\n'
module a500_8mb( cpu_a21,cpu_a22,cpu_a23,
                 cpu_a1, cpu_a2, cpu_a3, cpu_a4, cpu_a5, cpu_a6,
                 cpu_a16,cpu_a17,cpu_a18,cpu_a19,cpu_a20,
                 cpu_d12,cpu_d13,cpu_d14,cpu_d15,
                 cpu_as,cpu_lds,cpu_uds,cpu_clk,
                 cpu_reset,
                 dram_ras0,dram_ras1,dram_ras2,dram_ras3, dram_lcas,dram_ucas,
                 dram_ma0,dram_ma1,
                 mux_switch
               );

	input cpu_a21,cpu_a22,cpu_a23;

	input cpu_a1, cpu_a2, cpu_a3, cpu_a4, cpu_a5, cpu_a6;
	input cpu_a16,cpu_a17,cpu_a18,cpu_a19,cpu_a20;

	inout cpu_d12,cpu_d13,cpu_d14,cpu_d15;
	reg   cpu_d12,cpu_d13,cpu_d14,cpu_d15;

	input cpu_as,cpu_lds,cpu_uds;
	input cpu_clk;

	input cpu_reset;

	output dram_ras0,dram_ras1,dram_ras2,dram_ras3;
	reg    dram_ras0,dram_ras1,dram_ras2,dram_ras3;

	output dram_lcas,dram_ucas;
	reg    dram_lcas,dram_ucas;

	output dram_ma0,dram_ma1;
	reg    dram_ma0,dram_ma1;

	output mux_switch;
	reg    mux_switch;


	reg  [3:0] datout;

	wire [7:0] high_addr;
	wire [5:0] low_addr;

	reg which_ras[0:3];
	reg mem_selected;

	reg rfsh_ras,rfsh_cas;

	reg access_ras,access_cas;

	reg read_cycle;
	reg write_cycle;
	reg autoconf_on;
	reg cpu_as_z;

	reg [1:0] rfsh_select;


	assign high_addr = {cpu_a23,cpu_a22,cpu_a21,cpu_a20,cpu_a19,cpu_a18,cpu_a17,cpu_a16};
	assign low_addr  = {cpu_a6,cpu_a5,cpu_a4,cpu_a3,cpu_a2,cpu_a1};


	always @*
	begin
		casex( high_addr )
		8'b001xxxxx:
		begin
			{which_ras[0],which_ras[1],which_ras[2],which_ras[3]} <= 4'b1000;
			mem_selected <= 1'b1;
		end

		8'b010xxxxx:
		begin
			{which_ras[0],which_ras[1],which_ras[2],which_ras[3]} <= 4'b0100;
			mem_selected <= 1'b1;
		end


		8'b011xxxxx:
		begin
			{which_ras[0],which_ras[1],which_ras[2],which_ras[3]} <= 4'b0010;
			mem_selected <= 1'b1;
		end

		8'b100xxxxx:
		begin
			{which_ras[0],which_ras[1],which_ras[2],which_ras[3]} <= 4'b0001;
			mem_selected <= 1'b1;
		end

		default:
		begin
			{which_ras[0],which_ras[1],which_ras[2],which_ras[3]} <= 4'b0000;
			mem_selected <= 1'b0;
		end

		endcase
	end



	always @(posedge cpu_clk,posedge cpu_as)
	begin
		if( cpu_as==1 )
		begin
			access_ras <= 0;
			access_cas <= 0;
		end
		else
		begin
			access_ras <= 1;
			access_cas <= access_ras;
		end
	end


	always @(negedge cpu_clk,negedge access_ras)
	begin
		if( access_ras==0 )
		begin
			mux_switch <= 0;
		end
		else
		begin
			mux_switch <= 1;
		end
	end





	always @(negedge cpu_clk)
	begin
		if( cpu_as==1 )
		begin
			rfsh_cas <= ~rfsh_cas;
		end
		else
		begin
			rfsh_cas <= 0;
		end

		if( (rfsh_cas == 1'b0) && (cpu_as==1) )
		begin
			rfsh_select <= rfsh_select + 2'b01;
		end
	end

	always @*
	begin
		rfsh_ras <= rfsh_cas & cpu_clk;
	end




	always @*
	begin
		dram_ras0 <= ~( ( which_ras[0] & access_ras ) | ((rfsh_select==2'b00)?rfsh_ras:1'b0) );
		dram_ras1 <= ~( ( which_ras[1] & access_ras ) | ((rfsh_select==2'b01)?rfsh_ras:1'b0) );
		dram_ras2 <= ~( ( which_ras[2] & access_ras ) | ((rfsh_select==2'b10)?rfsh_ras:1'b0) );
		dram_ras3 <= ~( ( which_ras[3] & access_ras ) | ((rfsh_select==2'b11)?rfsh_ras:1'b0) );

		dram_lcas <= ~( ( ~cpu_lds & access_cas & mem_selected ) | rfsh_cas );
		dram_ucas <= ~( ( ~cpu_uds & access_cas & mem_selected ) | rfsh_cas );
	end






	always @*
	begin
		if( mux_switch==0 )
			{ dram_ma0,dram_ma1 } <= { cpu_a1,cpu_a2 };
		else
			{ dram_ma0,dram_ma1 } <= { cpu_a20,cpu_a19 };
	end



	always @(posedge cpu_clk)
	begin
		cpu_as_z <= cpu_as;
	end


	always @(posedge cpu_clk, posedge cpu_as)
	begin
		if( cpu_as==1 )
		begin
			read_cycle  <= 0;
			write_cycle <= 0;
		end
		else
		begin
			if( cpu_as==0 && cpu_as_z==1 )
			begin
				if( (cpu_lds&cpu_uds)==0 )
					read_cycle <= 1;
				else
					write_cycle <= 1;
			end
		end
	end


	always @*
	begin
		case( low_addr )
		6'b000000:
			datout <= 4'b1110;
		6'b000001:
			datout <= 4'b0000;

		6'b000010:
			datout <= 4'hE;
		6'b000011:
			datout <= 4'hE;

		6'b000100:
			datout <= 4'h3;
		6'b000101:
			datout <= 4'hF;

		6'b001000:
			datout <= 4'hE;
		6'b001001:
			datout <= 4'hE;

		6'b001010:
			datout <= 4'hE;
		6'b001011:
			datout <= 4'hE;

		6'b100000:
			datout <= 4'b0000;
		6'b100001:
			datout <= 4'b0000;

		default:
			datout <= 4'b1111;
		endcase
	end


	always @*
	begin
		if( read_cycle==1 && high_addr==8'hE8 && autoconf_on==1 )
			{cpu_d15,cpu_d14,cpu_d13,cpu_d12} <= datout;
		else
			{cpu_d15,cpu_d14,cpu_d13,cpu_d12} <= 4'bZZZZ;
	end


	always @(posedge write_cycle,negedge cpu_reset)
	begin
		if( cpu_reset==0 )
			autoconf_on <= 1;
		else
		begin
			if( high_addr==8'hE8 && low_addr[5:2]==4'b1001 )
				autoconf_on <= 0;
		end
	end



endmodule
module a500_8mb( cpu_a21,cpu_a22,cpu_a23,
                 cpu_a1, cpu_a2, cpu_a3, cpu_a4, cpu_a5, cpu_a6,
                 cpu_a16,cpu_a17,cpu_a18,cpu_a19,cpu_a20,
                 cpu_d12,cpu_d13,cpu_d14,cpu_d15,
                 cpu_as,cpu_lds,cpu_uds,cpu_clk,
                 cpu_reset,
                 dram_ras0,dram_ras1,dram_ras2,dram_ras3, dram_lcas,dram_ucas,
                 dram_ma0,dram_ma1,
                 mux_switch
               );


	input cpu_a21,cpu_a22,cpu_a23;

	input cpu_a1, cpu_a2, cpu_a3, cpu_a4, cpu_a5, cpu_a6;
	input cpu_a16,cpu_a17,cpu_a18,cpu_a19,cpu_a20;

	inout cpu_d12,cpu_d13,cpu_d14,cpu_d15;
	reg   cpu_d12,cpu_d13,cpu_d14,cpu_d15;

	input cpu_as,cpu_lds,cpu_uds;
	input cpu_clk;

	input cpu_reset;

	output dram_ras0,dram_ras1,dram_ras2,dram_ras3;
	reg    dram_ras0,dram_ras1,dram_ras2,dram_ras3;

	output dram_lcas,dram_ucas;
	reg    dram_lcas,dram_ucas;

	output dram_ma0,dram_ma1;
	reg    dram_ma0,dram_ma1;

	output mux_switch;
	reg    mux_switch;


	reg  [3:0] datout;

	wire [7:0] high_addr;
	wire [5:0] low_addr;

	reg which_ras[0:3];
	reg mem_selected;

	reg rfsh_ras,rfsh_cas;

	reg access_ras,access_cas;

	reg read_cycle;
	reg write_cycle;
	reg autoconf_on;
	reg cpu_as_z;

	reg [1:0] rfsh_select;


	assign high_addr = {cpu_a23,cpu_a22,cpu_a21,cpu_a20,cpu_a19,cpu_a18,cpu_a17,cpu_a16};
	assign low_addr  = {cpu_a6,cpu_a5,cpu_a4,cpu_a3,cpu_a2,cpu_a1};


	always @*
	begin
		casex( high_addr )
		8'b001xxxxx:
		begin
			{which_ras[0],which_ras[1],which_ras[2],which_ras[3]} <= 4'b1000;
			mem_selected <= 1'b1;
		end

		8'b010xxxxx:
		begin
			{which_ras[0],which_ras[1],which_ras[2],which_ras[3]} <= 4'b0100;
			mem_selected <= 1'b1;
		end


		8'b011xxxxx:
		begin
			{which_ras[0],which_ras[1],which_ras[2],which_ras[3]} <= 4'b0010;
			mem_selected <= 1'b1;
		end

		8'b100xxxxx:
		begin
			{which_ras[0],which_ras[1],which_ras[2],which_ras[3]} <= 4'b0001;
			mem_selected <= 1'b1;
		end

		default:
		begin
			{which_ras[0],which_ras[1],which_ras[2],which_ras[3]} <= 4'b0000;
			mem_selected <= 1'b0;
		end

		endcase
	end



	always @(posedge cpu_clk,posedge cpu_as)
	begin
		if( cpu_as==1 )
		begin
			access_ras <= 0;
			access_cas <= 0;
		end
		else
		begin
			access_ras <= 1;
			access_cas <= access_ras;
		end
	end


	always @(negedge cpu_clk,negedge access_ras)
	begin
		if( access_ras==0 )
		begin
			mux_switch <= 0;
		end
		else
		begin
			mux_switch <= 1;
		end
	end





	always @(negedge cpu_clk)
	begin
		if( cpu_as==1 )
		begin
			rfsh_cas <= ~rfsh_cas;
		end
		else
		begin
			rfsh_cas <= 0;
		end

		if( (rfsh_cas == 1'b0) && (cpu_as==1) )
		begin
			rfsh_select <= rfsh_select + 2'b01;
		end
	end

	always @*
	begin
		rfsh_ras <= rfsh_cas & cpu_clk;
	end




	always @*
	begin
		dram_ras0 <= ~( ( which_ras[0] & access_ras ) | ((rfsh_select==2'b00)?rfsh_ras:1'b0) );
		dram_ras1 <= ~( ( which_ras[1] & access_ras ) | ((rfsh_select==2'b01)?rfsh_ras:1'b0) );
		dram_ras2 <= ~( ( which_ras[2] & access_ras ) | ((rfsh_select==2'b10)?rfsh_ras:1'b0) );
		dram_ras3 <= ~( ( which_ras[3] & access_ras ) | ((rfsh_select==2'b11)?rfsh_ras:1'b0) );

		dram_lcas <= ~( ( ~cpu_lds & access_cas & mem_selected ) | rfsh_cas );
		dram_ucas <= ~( ( ~cpu_uds & access_cas & mem_selected ) | rfsh_cas );
	end






	always @*
	begin
		if( mux_switch==0 )
			{ dram_ma0,dram_ma1 } <= { cpu_a1,cpu_a2 };
		else
			{ dram_ma0,dram_ma1 } <= { cpu_a20,cpu_a19 };
	end



	always @(posedge cpu_clk)
	begin
		cpu_as_z <= cpu_as;
	end


	always @(posedge cpu_clk, posedge cpu_as)
	begin
		if( cpu_as==1 )
		begin
			read_cycle  <= 0;
			write_cycle <= 0;
		end
		else
		begin
			if( cpu_as==0 && cpu_as_z==1 )
			begin
				if( (cpu_lds&cpu_uds)==0 )
					read_cycle <= 1;
				else
					write_cycle <= 1;
			end
		end
	end


	always @*
	begin
		case( low_addr )
		6'b000000:
			datout <= 4'b1110;
		6'b000001:
			datout <= 4'b0000;

		6'b000010:
			datout <= 4'hE;
		6'b000011:
			datout <= 4'hE;

		6'b000100:
			datout <= 4'h3;
		6'b000101:
			datout <= 4'hF;

		6'b001000:
			datout <= 4'hE;
		6'b001001:
			datout <= 4'hE;

		6'b001010:
			datout <= 4'hE;
		6'b001011:
			datout <= 4'hE;

		6'b100000:
			datout <= 4'b0000;
		6'b100001:
			datout <= 4'b0000;

		default:
			datout <= 4'b1111;
		endcase
	end


	always @*
	begin
		if( read_cycle==1 && high_addr==8'hE8 && autoconf_on==1 )
			{cpu_d15,cpu_d14,cpu_d13,cpu_d12} <= datout;
		else
			{cpu_d15,cpu_d14,cpu_d13,cpu_d12} <= 4'bZZZZ;
	end


	always @(posedge write_cycle,negedge cpu_reset)
	begin
		if( cpu_reset==0 )
			autoconf_on <= 1;
		else
		begin
			if( high_addr==8'hE8 && low_addr[5:2]==4'b1001 )
				autoconf_on <= 0;
		end
	end



endmodule