data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v
1: b'%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:121: Cannot find file containing module: \'hitcheck\'\n    hitcheck #(3) h0(tag,cache2[set][0][130:128], \n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/hitcheck\n             data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/hitcheck.v\n             data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/hitcheck.sv\n             hitcheck\n             hitcheck.v\n             hitcheck.sv\n             obj_dir/hitcheck\n             obj_dir/hitcheck.v\n             obj_dir/hitcheck.sv\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:124: Cannot find file containing module: \'hitcheck\'\n    hitcheck #(3) h1(tag,cache2[set][1][130:128],\n    ^~~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:127: Cannot find file containing module: \'hitcheck\'\n    hitcheck #(3) h2(tag,cache2[set][2][130:128],\n    ^~~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:130: Cannot find file containing module: \'hitcheck\'\n    hitcheck #(3) h3(tag,cache2[set][3][130:128],\n    ^~~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:136: Cannot find file containing module: \'mux4\'\n    mux4 #(32) trdmux4(cache2[set][hway][31:0],\n    ^~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:150: Cannot find file containing module: \'nextU\'\n    nextU nextu(U[set],hway,tU);\n    ^~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:166: Cannot find file containing module: \'imem\'\n    imem imem(clk,reset,\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:182: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                                                                                 : ... In instance icache2\n        t<={3\'b0,cache2[SW[6:5]][SW[4:3]][131],\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:198: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'iready\' generates 1 bits.\n                                                                                                                                                 : ... In instance icache2\n        7\'b11:begin t<=iready;disop<=ONE; end\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:199: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'state\' generates 2 bits.\n                                                                                                                                                 : ... In instance icache2\n        7\'b100:begin t<=state;disop<=ONE; end\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:200: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'nextstate\' generates 2 bits.\n                                                                                                                                                 : ... In instance icache2\n        7\'b101:begin t<=nextstate;disop<=ONE; end\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:202: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'controls\' generates 3 bits.\n                                                                                                                                                 : ... In instance icache2\n        7\'b111:begin t<=controls;disop<=ONE; end\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:203: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'ready\' generates 1 bits.\n                                                                                                                                                 : ... In instance icache2\n        7\'b1000:begin t<=ready;disop<=ONE; end\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/icache2.v:204: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'hit\' generates 1 bits.\n                                                                                                                                                 : ... In instance icache2\n        7\'b1001:begin t<=hit;disop<=ONE; end\n                       ^~\n%Error: Exiting due to 7 error(s), 7 warning(s)\n'
module icache2(
    input clk,reset,
    input [31:0] addr,
    output reg [31:0] readdata,
    output ready,
    input [9:0] SW,
    output reg [31:0] t,
    output reg [7:0] disop
    );
    


    
    reg [131:0] cache2[3:0][3:0];




    reg [5:0] U[3:0];
    initial
    begin 
    U[0]<=6'b0;U[1]<=6'b0;
    U[2]<=6'b0;U[3]<=6'b0; 
    end
    wire [5:0] tU;

    

    wire [127:0] rd;
    wire iready;
        

    wire hit0,hit1,hit2,hit3,hit;
    wire [31:0] trd;


    parameter READY=2'b00;
    parameter LOAD=2'b01;
    parameter REPLACE=2'b10;
    reg [1:0] state,nextstate;




    wire [1:0] hway,rway,way;
    wire [2:0] tag;
    wire [1:0] set,blockoffset;
    
    wire [31:0] memt;
    
    reg [31:0] total,hitcount,replacecount;
    initial begin total=0;hitcount=0;replacecount=0; end
    
    wire read,replace;
    reg [2:0] controls;
    assign {read,replace,ready}=controls;
    
    assign {tag,set,blockoffset}=addr[8:2];
    

    always@(posedge hit) total<=total+1;
    always@(*) hitcount<=total-replacecount;
    always@(posedge replace) replacecount<=replacecount+1;
    

    always@(posedge clk)
    if(reset)
        state<=READY;
    else
        state<=nextstate;
        

    always@(*)
    case(state)
    READY:
        if(hit) nextstate<=READY; 
        else nextstate<=LOAD;
    LOAD:
        if(iready) nextstate<=REPLACE;
        else nextstate<=LOAD;
    REPLACE:
        nextstate<=READY;
    default:
        nextstate<=2'bxx;
    endcase
       

    always@(*)
    case(state)
    READY:
        if(hit) controls<=3'b101; 
        else    controls<=3'b000;        
    LOAD:       controls<=3'b000;
    REPLACE:    controls<=3'b010;
    default:    controls<=3'bxxx;
    endcase
    

    hitcheck #(3) h0(tag,cache2[set][0][130:128],
                     cache2[set][0][131],
                     hit0);
    hitcheck #(3) h1(tag,cache2[set][1][130:128],
                     cache2[set][1][131],
                     hit1);
    hitcheck #(3) h2(tag,cache2[set][2][130:128],
                     cache2[set][2][131],
                     hit2);
    hitcheck #(3) h3(tag,cache2[set][3][130:128],
                     cache2[set][3][131],
                     hit3);
    assign hit=hit0|hit1|hit2|hit3;

    assign hway={hit3|hit2,hit3|hit1};
    mux4 #(32) trdmux4(cache2[set][hway][31:0],
                       cache2[set][hway][63:32],
                       cache2[set][hway][95:64],
                       cache2[set][hway][127:96],
                       blockoffset,trd);
    

    assign rway=(U[set][5:3]==3'b000)?2'b00:(
                ({U[set][5],U[set][2:1]}==3'b100)?2'b01:(
                ({U[set][4],U[set][2],U[set][0]}==3'b110)?2'b10:(
                ({U[set][3],U[set][1:0]}==3'b111)?2'b11:
                2'bxx)));
    

    nextU nextu(U[set],hway,tU);

   


    always@(*)
    if(read) readdata<=trd;

    always@(posedge clk)
    if(reset) U[set]<=6'b0; else
    if(read) U[set]<=tU;
 
    always@(posedge clk)
    if(replace) cache2[set][rway][131:0]<={1'b1,tag,rd};
    

    imem imem(clk,reset,
              {23'b0,tag,set,4'b0},
              rd,iready,
              SW[6:0],memt);
    

    parameter ZERO=8'b0;
    parameter ONE=8'b1;
    parameter TWO=8'b11;
    parameter EIGHT=8'b11111111;
    always@(*)
    case(SW[9:7])
    3'b010:begin t<=memt;disop<=EIGHT; end
    3'b110:
        if(SW[2])
        begin 
        t<={3'b0,cache2[SW[6:5]][SW[4:3]][131],
            1'b0,cache2[SW[6:5]][SW[4:3]][130:128]};
        disop<=TWO;
        end
        else
        case(SW[1:0])
        2'b00:begin t<=cache2[SW[6:5]][SW[4:3]][31:0];disop<=EIGHT;end
        2'b01:begin t<=cache2[SW[6:5]][SW[4:3]][63:32];disop<=EIGHT;end
        2'b10:begin t<=cache2[SW[6:5]][SW[4:3]][95:64];disop<=EIGHT;end
        2'b11:begin t<=cache2[SW[6:5]][SW[4:3]][127:96];disop<=EIGHT;end
        endcase
    3'b111:
        case(SW[6:0])
        7'b0:begin t<=total;disop<=EIGHT; end
        7'b1:begin t<=hitcount;disop<=EIGHT; end
        7'b10:begin t<=replacecount;disop<=EIGHT; end
        7'b11:begin t<=iready;disop<=ONE; end
        7'b100:begin t<=state;disop<=ONE; end
        7'b101:begin t<=nextstate;disop<=ONE; end
        7'b110:begin t<=readdata;disop<=EIGHT; end
        7'b111:begin t<=controls;disop<=ONE; end
        7'b1000:begin t<=ready;disop<=ONE; end
        7'b1001:begin t<=hit;disop<=ONE; end
        default:begin t<=32'b0;disop<=ZERO;end
        endcase
    default:begin t<=32'b0;disop<=ZERO;end
    endcase    
    
endmodule
module icache2(
    input clk,reset,
    input [31:0] addr,
    output reg [31:0] readdata,
    output ready,
    input [9:0] SW,
    output reg [31:0] t,
    output reg [7:0] disop
    );

    


    
    reg [131:0] cache2[3:0][3:0];




    reg [5:0] U[3:0];
    initial
    begin 
    U[0]<=6'b0;U[1]<=6'b0;
    U[2]<=6'b0;U[3]<=6'b0; 
    end
    wire [5:0] tU;

    

    wire [127:0] rd;
    wire iready;
        

    wire hit0,hit1,hit2,hit3,hit;
    wire [31:0] trd;


    parameter READY=2'b00;
    parameter LOAD=2'b01;
    parameter REPLACE=2'b10;
    reg [1:0] state,nextstate;




    wire [1:0] hway,rway,way;
    wire [2:0] tag;
    wire [1:0] set,blockoffset;
    
    wire [31:0] memt;
    
    reg [31:0] total,hitcount,replacecount;
    initial begin total=0;hitcount=0;replacecount=0; end
    
    wire read,replace;
    reg [2:0] controls;
    assign {read,replace,ready}=controls;
    
    assign {tag,set,blockoffset}=addr[8:2];
    

    always@(posedge hit) total<=total+1;
    always@(*) hitcount<=total-replacecount;
    always@(posedge replace) replacecount<=replacecount+1;
    

    always@(posedge clk)
    if(reset)
        state<=READY;
    else
        state<=nextstate;
        

    always@(*)
    case(state)
    READY:
        if(hit) nextstate<=READY; 
        else nextstate<=LOAD;
    LOAD:
        if(iready) nextstate<=REPLACE;
        else nextstate<=LOAD;
    REPLACE:
        nextstate<=READY;
    default:
        nextstate<=2'bxx;
    endcase
       

    always@(*)
    case(state)
    READY:
        if(hit) controls<=3'b101; 
        else    controls<=3'b000;        
    LOAD:       controls<=3'b000;
    REPLACE:    controls<=3'b010;
    default:    controls<=3'bxxx;
    endcase
    

    hitcheck #(3) h0(tag,cache2[set][0][130:128],
                     cache2[set][0][131],
                     hit0);
    hitcheck #(3) h1(tag,cache2[set][1][130:128],
                     cache2[set][1][131],
                     hit1);
    hitcheck #(3) h2(tag,cache2[set][2][130:128],
                     cache2[set][2][131],
                     hit2);
    hitcheck #(3) h3(tag,cache2[set][3][130:128],
                     cache2[set][3][131],
                     hit3);
    assign hit=hit0|hit1|hit2|hit3;

    assign hway={hit3|hit2,hit3|hit1};
    mux4 #(32) trdmux4(cache2[set][hway][31:0],
                       cache2[set][hway][63:32],
                       cache2[set][hway][95:64],
                       cache2[set][hway][127:96],
                       blockoffset,trd);
    

    assign rway=(U[set][5:3]==3'b000)?2'b00:(
                ({U[set][5],U[set][2:1]}==3'b100)?2'b01:(
                ({U[set][4],U[set][2],U[set][0]}==3'b110)?2'b10:(
                ({U[set][3],U[set][1:0]}==3'b111)?2'b11:
                2'bxx)));
    

    nextU nextu(U[set],hway,tU);

   


    always@(*)
    if(read) readdata<=trd;

    always@(posedge clk)
    if(reset) U[set]<=6'b0; else
    if(read) U[set]<=tU;
 
    always@(posedge clk)
    if(replace) cache2[set][rway][131:0]<={1'b1,tag,rd};
    

    imem imem(clk,reset,
              {23'b0,tag,set,4'b0},
              rd,iready,
              SW[6:0],memt);
    

    parameter ZERO=8'b0;
    parameter ONE=8'b1;
    parameter TWO=8'b11;
    parameter EIGHT=8'b11111111;
    always@(*)
    case(SW[9:7])
    3'b010:begin t<=memt;disop<=EIGHT; end
    3'b110:
        if(SW[2])
        begin 
        t<={3'b0,cache2[SW[6:5]][SW[4:3]][131],
            1'b0,cache2[SW[6:5]][SW[4:3]][130:128]};
        disop<=TWO;
        end
        else
        case(SW[1:0])
        2'b00:begin t<=cache2[SW[6:5]][SW[4:3]][31:0];disop<=EIGHT;end
        2'b01:begin t<=cache2[SW[6:5]][SW[4:3]][63:32];disop<=EIGHT;end
        2'b10:begin t<=cache2[SW[6:5]][SW[4:3]][95:64];disop<=EIGHT;end
        2'b11:begin t<=cache2[SW[6:5]][SW[4:3]][127:96];disop<=EIGHT;end
        endcase
    3'b111:
        case(SW[6:0])
        7'b0:begin t<=total;disop<=EIGHT; end
        7'b1:begin t<=hitcount;disop<=EIGHT; end
        7'b10:begin t<=replacecount;disop<=EIGHT; end
        7'b11:begin t<=iready;disop<=ONE; end
        7'b100:begin t<=state;disop<=ONE; end
        7'b101:begin t<=nextstate;disop<=ONE; end
        7'b110:begin t<=readdata;disop<=EIGHT; end
        7'b111:begin t<=controls;disop<=ONE; end
        7'b1000:begin t<=ready;disop<=ONE; end
        7'b1001:begin t<=hit;disop<=ONE; end
        default:begin t<=32'b0;disop<=ZERO;end
        endcase
    default:begin t<=32'b0;disop<=ZERO;end
    endcase    
    
endmodule