data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v
1: b'%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:1: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:5: Define or directive not defined: \'`RS_ENT_SEL\'\n   input wire [`RS_ENT_SEL-1:0] rsent_1,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:6: Define or directive not defined: \'`RS_ENT_SEL\'\n   input wire [`RS_ENT_SEL-1:0] rsent_2,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:21: Define or directive not defined: \'`RS_ENT_ALU\'\n   assign req1_alu = (rsent_1 == `RS_ENT_ALU) ? 1\'b1 : 1\'b0;\n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:21: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign req1_alu = (rsent_1 == `RS_ENT_ALU) ? 1\'b1 : 1\'b0;\n                                            ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:22: Define or directive not defined: \'`RS_ENT_ALU\'\n   assign req2_alu = (rsent_2 == `RS_ENT_ALU) ? 1\'b1 : 1\'b0;\n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:22: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign req2_alu = (rsent_2 == `RS_ENT_ALU) ? 1\'b1 : 1\'b0;\n                                            ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:25: Define or directive not defined: \'`RS_ENT_BRANCH\'\n   assign req1_branch = (rsent_1 == `RS_ENT_BRANCH) ? 1\'b1 : 1\'b0;\n                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:25: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign req1_branch = (rsent_1 == `RS_ENT_BRANCH) ? 1\'b1 : 1\'b0;\n                                                  ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:26: Define or directive not defined: \'`RS_ENT_BRANCH\'\n   assign req2_branch = (rsent_2 == `RS_ENT_BRANCH) ? 1\'b1 : 1\'b0;\n                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:26: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign req2_branch = (rsent_2 == `RS_ENT_BRANCH) ? 1\'b1 : 1\'b0;\n                                                  ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:29: Define or directive not defined: \'`RS_ENT_MUL\'\n   assign req1_mul = (rsent_1 == `RS_ENT_MUL) ? 1\'b1 : 1\'b0;\n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:29: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign req1_mul = (rsent_1 == `RS_ENT_MUL) ? 1\'b1 : 1\'b0;\n                                            ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:30: Define or directive not defined: \'`RS_ENT_MUL\'\n   assign req2_mul = (rsent_2 == `RS_ENT_MUL) ? 1\'b1 : 1\'b0;\n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:30: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign req2_mul = (rsent_2 == `RS_ENT_MUL) ? 1\'b1 : 1\'b0;\n                                            ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:33: Define or directive not defined: \'`RS_ENT_LDST\'\n   assign req1_ldst = (rsent_1 == `RS_ENT_LDST) ? 1\'b1 : 1\'b0;\n                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:33: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign req1_ldst = (rsent_1 == `RS_ENT_LDST) ? 1\'b1 : 1\'b0;\n                                              ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:34: Define or directive not defined: \'`RS_ENT_LDST\'\n   assign req2_ldst = (rsent_2 == `RS_ENT_LDST) ? 1\'b1 : 1\'b0;\n                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/rs_reqgen.v:34: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign req2_ldst = (rsent_2 == `RS_ENT_LDST) ? 1\'b1 : 1\'b0;\n                                              ^\n%Error: Exiting due to 19 error(s)\n'
module rs_requestgenerator
  (
   input wire [`RS_ENT_SEL-1:0] rsent_1,
   input wire [`RS_ENT_SEL-1:0] rsent_2,
   output wire 			req1_alu,
   output wire 			req2_alu,
   output wire [1:0] 		req_alunum,
   output wire 			req1_branch,
   output wire 			req2_branch,
   output wire [1:0] 		req_branchnum,
   output wire 			req1_mul,
   output wire 			req2_mul,
   output wire [1:0] 		req_mulnum,
   output wire 			req1_ldst,
   output wire 			req2_ldst,
   output wire [1:0] 		req_ldstnum
   );

   assign req1_alu = (rsent_1 == `RS_ENT_ALU) ? 1'b1 : 1'b0;
   assign req2_alu = (rsent_2 == `RS_ENT_ALU) ? 1'b1 : 1'b0;
   assign req_alunum = {1'b0, req1_alu} + {1'b0, req2_alu};

   assign req1_branch = (rsent_1 == `RS_ENT_BRANCH) ? 1'b1 : 1'b0;
   assign req2_branch = (rsent_2 == `RS_ENT_BRANCH) ? 1'b1 : 1'b0;
   assign req_branchnum = {1'b0, req1_branch} + {1'b0, req2_branch};

   assign req1_mul = (rsent_1 == `RS_ENT_MUL) ? 1'b1 : 1'b0;
   assign req2_mul = (rsent_2 == `RS_ENT_MUL) ? 1'b1 : 1'b0;
   assign req_mulnum = {1'b0, req1_mul} + {1'b0, req2_mul};

   assign req1_ldst = (rsent_1 == `RS_ENT_LDST) ? 1'b1 : 1'b0;
   assign req2_ldst = (rsent_2 == `RS_ENT_LDST) ? 1'b1 : 1'b0;
   assign req_ldstnum = {1'b0, req1_ldst} + {1'b0, req2_ldst};
   
endmodule
module rs_requestgenerator
  (
   input wire [`RS_ENT_SEL-1:0] rsent_1,
   input wire [`RS_ENT_SEL-1:0] rsent_2,
   output wire 			req1_alu,
   output wire 			req2_alu,
   output wire [1:0] 		req_alunum,
   output wire 			req1_branch,
   output wire 			req2_branch,
   output wire [1:0] 		req_branchnum,
   output wire 			req1_mul,
   output wire 			req2_mul,
   output wire [1:0] 		req_mulnum,
   output wire 			req1_ldst,
   output wire 			req2_ldst,
   output wire [1:0] 		req_ldstnum
   );


   assign req1_alu = (rsent_1 == `RS_ENT_ALU) ? 1'b1 : 1'b0;
   assign req2_alu = (rsent_2 == `RS_ENT_ALU) ? 1'b1 : 1'b0;
   assign req_alunum = {1'b0, req1_alu} + {1'b0, req2_alu};

   assign req1_branch = (rsent_1 == `RS_ENT_BRANCH) ? 1'b1 : 1'b0;
   assign req2_branch = (rsent_2 == `RS_ENT_BRANCH) ? 1'b1 : 1'b0;
   assign req_branchnum = {1'b0, req1_branch} + {1'b0, req2_branch};

   assign req1_mul = (rsent_1 == `RS_ENT_MUL) ? 1'b1 : 1'b0;
   assign req2_mul = (rsent_2 == `RS_ENT_MUL) ? 1'b1 : 1'b0;
   assign req_mulnum = {1'b0, req1_mul} + {1'b0, req2_mul};

   assign req1_ldst = (rsent_1 == `RS_ENT_LDST) ? 1'b1 : 1'b0;
   assign req2_ldst = (rsent_2 == `RS_ENT_LDST) ? 1'b1 : 1'b0;
   assign req_ldstnum = {1'b0, req1_ldst} + {1'b0, req2_ldst};
   
endmodule