data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_lut.svp
 line:8: before: "parameter"
1: b"%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_lut.svp:7: Define or directive not defined: '`mname'\nmodule  `mname`  #(\n        ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_lut.svp:7: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule  `mname`  #(\n              ^\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_lut.svp:9: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_lut.svp:20: Unsupported or unknown PLI call: $c_in_decl\n  input  `$c_in_decl`        op_c_in,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_lut.svp:24: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_lut.svp:30: Unsupported or unknown PLI call: $lut_inps\n    logic [`$lut_inps-1`:0] lut;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/unused/pe/rtl/test_lut.svp:36: Unsupported or unknown PLI call: $lut_inps\n        lut   <= cfg_d[`$lut_inps-1`: 0];\n                        ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module  `mname`  #(
  parameter DataWidth = 16
) (
  input                  cfg_clk,
  input                  cfg_rst_n,
  input           [15:0] cfg_d,
  input           [7:0]  cfg_a,
  input                  cfg_en,

  input  [DataWidth-1:0] op_a_in,
  input  [DataWidth-1:0] op_b_in,


  input  `$c_in_decl`        op_c_in,


  output logic [DataWidth-1:0] res
);

genvar ggg;
generate
  for (ggg = 0; ggg < DataWidth; ggg = ggg +1) begin : GEN_LUT

    logic [`$lut_inps-1`:0] lut;

    always_ff @(posedge cfg_clk or negedge cfg_rst_n) begin
      if(~cfg_rst_n) begin
        lut   <= 4'h0;
      end else if(cfg_en && (cfg_a == (ggg/4))) begin
        lut   <= cfg_d[`$lut_inps-1`: 0];
      end
    end

    assign res[ggg] = lut[{op_a_in[ggg], op_b_in[ggg]}];
  end
endgenerate



endmodule
module  `mname`  #(
  parameter DataWidth = 16
) (
  input                  cfg_clk,
  input                  cfg_rst_n,
  input           [15:0] cfg_d,
  input           [7:0]  cfg_a,
  input                  cfg_en,

  input  [DataWidth-1:0] op_a_in,
  input  [DataWidth-1:0] op_b_in,


  input  `$c_in_decl`        op_c_in,


  output logic [DataWidth-1:0] res
);


genvar ggg;
generate
  for (ggg = 0; ggg < DataWidth; ggg = ggg +1) begin : GEN_LUT

    logic [`$lut_inps-1`:0] lut;

    always_ff @(posedge cfg_clk or negedge cfg_rst_n) begin
      if(~cfg_rst_n) begin
        lut   <= 4'h0;
      end else if(cfg_en && (cfg_a == (ggg/4))) begin
        lut   <= cfg_d[`$lut_inps-1`: 0];
      end
    end

    assign res[ggg] = lut[{op_a_in[ggg], op_b_in[ggg]}];
  end
endgenerate



endmodule