data/full_repos/permissive/19340845/src/SpeicalPurposeRegister.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/19340845/src/SpeicalPurposeRegister.v:28: Multiple top level modules\n                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                      : ... Top module \'ZeroRegister\'\nmodule ZeroRegister (\n       ^~~~~~~~~~~~\n                                                                                      : ... Top module \'AddressRegister\'\nmodule AddressRegister (\n       ^~~~~~~~~~~~~~~\n                                                                                      : ... Top module \'BaseRegister\'\nmodule BaseRegister(\n       ^~~~~~~~~~~~\n                                                                                      : ... Top module \'IndexRegister\'\nmodule IndexRegister(\n       ^~~~~~~~~~~~~\n                                                                                      : ... Top module \'StackPointerRegister\'\nmodule StackPointerRegister (\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                      : ... Top module \'BasePointerRegister\'\nmodule BasePointerRegister (\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                      : ... Top module \'InputRegister\'\nmodule InputRegister (\n       ^~~~~~~~~~~~~\n                                                                                      : ... Top module \'OutputRegister\'\nmodule OutputRegister (\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module AddressRegister (
   input        clock, write, reset,
   input [3:0]  address,
   input [15:0] writeData,
   output [15:0] data);

   reg [15:0]    out = 16'b0;

   always @ (posedge clock) begin
      if (reset)
        out = 16'b0;
      else if (write)
        out = writeData;
   end

   assign data = out;
endmodule
module AddressRegister (
   input        clock, write, reset,
   input [3:0]  address,
   input [15:0] writeData,
   output [15:0] data);


   reg [15:0]    out = 16'b0;

   always @ (posedge clock) begin
      if (reset)
        out = 16'b0;
      else if (write)
        out = writeData;
   end

   assign data = out;
endmodule