data/full_repos/permissive/132173046/src/tests/btc_four_zeroes/rtl/top_test.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/132173046/src/tests/btc_four_zeroes/rtl/top_test.v:35: Cannot find file containing module: 'SB_PLL40_CORE'\n    SB_PLL40_CORE #(\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132173046/src/tests/btc_four_zeroes/rtl,data/full_repos/permissive/132173046/SB_PLL40_CORE\n             data/full_repos/permissive/132173046/src/tests/btc_four_zeroes/rtl,data/full_repos/permissive/132173046/SB_PLL40_CORE.v\n             data/full_repos/permissive/132173046/src/tests/btc_four_zeroes/rtl,data/full_repos/permissive/132173046/SB_PLL40_CORE.sv\n             SB_PLL40_CORE\n             SB_PLL40_CORE.v\n             SB_PLL40_CORE.sv\n             obj_dir/SB_PLL40_CORE\n             obj_dir/SB_PLL40_CORE.v\n             obj_dir/SB_PLL40_CORE.sv\n%Error: data/full_repos/permissive/132173046/src/tests/btc_four_zeroes/rtl/top_test.v:70: Cannot find file containing module: 'top'\n    top #(\n    ^~~\n%Error: Exiting due to 2 error(s)\n"
module top_test
(
  clk_in,
  reset_n_in,

  sck0_in,
  sdi0_in,
  cs0_n_in,

  sck1_in,
  sdi1_in,
  sdo1_out,
  cs1_n_in,

  ready_n_od_out,

  status_led_n_out
);


    `define SHAPOOL_NO_NONCE_OFFSET

    parameter POOL_SIZE       = 1;
    parameter POOL_SIZE_LOG2  = 0;
    parameter BASE_TARGET     = 4;


    parameter PLL_DIVR = 4'b0000;
    parameter PLL_DIVF = 7'b1001111;
    parameter PLL_DIVQ = 3'b101;


    wire g_clk;

    SB_PLL40_CORE #(
        .FEEDBACK_PATH("SIMPLE"),
        .DIVR(PLL_DIVR),
        .DIVF(PLL_DIVF),
        .DIVQ(PLL_DIVQ),
        .FILTER_RANGE(3'b001)
    )
    pll (
        .LOCK(pll_locked),
        .RESETB(1'b1),
        .BYPASS(1'b0),
        .REFERENCECLK(clk_in),

        .PLLOUTGLOBAL(g_clk)
    );



    input wire clk_in;

    input wire reset_n_in;

    input wire sck0_in;
    input wire sdi0_in;
    input wire cs0_n_in;

    input wire sck1_in;
    input wire sdi1_in;
    output wire sdo1_out;
    input wire cs1_n_in;

    output wire ready_n_od_out;

    output wire status_led_n_out;

    top #(
      .POOL_SIZE(POOL_SIZE),
      .POOL_SIZE_LOG2(POOL_SIZE_LOG2),
      .BASE_TARGET(BASE_TARGET)
    )
    u (
      g_clk,
      reset_n_in,

      sck0_in,
      sdi0_in,
      cs0_n_in,

      sck1_in,
      sdi1_in,
      sdo1_out,
      cs1_n_in,

      ready_n_od_out,

      status_led_n_out
    );

endmodule
module top_test
(
  clk_in,
  reset_n_in,

  sck0_in,
  sdi0_in,
  cs0_n_in,

  sck1_in,
  sdi1_in,
  sdo1_out,
  cs1_n_in,

  ready_n_od_out,

  status_led_n_out
);



    `define SHAPOOL_NO_NONCE_OFFSET

    parameter POOL_SIZE       = 1;
    parameter POOL_SIZE_LOG2  = 0;
    parameter BASE_TARGET     = 4;


    parameter PLL_DIVR = 4'b0000;
    parameter PLL_DIVF = 7'b1001111;
    parameter PLL_DIVQ = 3'b101;


    wire g_clk;

    SB_PLL40_CORE #(
        .FEEDBACK_PATH("SIMPLE"),
        .DIVR(PLL_DIVR),
        .DIVF(PLL_DIVF),
        .DIVQ(PLL_DIVQ),
        .FILTER_RANGE(3'b001)
    )
    pll (
        .LOCK(pll_locked),
        .RESETB(1'b1),
        .BYPASS(1'b0),
        .REFERENCECLK(clk_in),

        .PLLOUTGLOBAL(g_clk)
    );



    input wire clk_in;

    input wire reset_n_in;

    input wire sck0_in;
    input wire sdi0_in;
    input wire cs0_n_in;

    input wire sck1_in;
    input wire sdi1_in;
    output wire sdo1_out;
    input wire cs1_n_in;

    output wire ready_n_od_out;

    output wire status_led_n_out;

    top #(
      .POOL_SIZE(POOL_SIZE),
      .POOL_SIZE_LOG2(POOL_SIZE_LOG2),
      .BASE_TARGET(BASE_TARGET)
    )
    u (
      g_clk,
      reset_n_in,

      sck0_in,
      sdi0_in,
      cs0_n_in,

      sck1_in,
      sdi1_in,
      sdo1_out,
      cs1_n_in,

      ready_n_od_out,

      status_led_n_out
    );

endmodule