data/full_repos/permissive/143278/ivltests/pr1983762.v
 line:11: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1983762.v:10: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1983762.v:11: Unsupported: Ignoring delay on this delayed statement.\n      #1 $finish;\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module print (input wire clk);

   parameter message = "";
   parameter number = 0;

   always @(posedge clk) begin
      if (number !== 100) begin
	 $display("FAILED -- number=%d\n", number);
	 $finish;
      end
     $display("%s", message);
   end

endmodule
module print (input wire clk);


   parameter message = "";
   parameter number = 0;

   always @(posedge clk) begin
      if (number !== 100) begin
	 $display("FAILED -- number=%d\n", number);
	 $finish;
      end
     $display("%s", message);
   end

endmodule