data/full_repos/permissive/130234582/src/rst_gen.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/130234582/src/rst_gen.v:8: Unsupported: Ignoring delay on this delayed statement.\n    #(ASSERT_PS)\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/130234582/src/rst_gen.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #(RELEASE_PS-ASSERT_PS)\n    ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rst_gen
#(  parameter RELEASE_PS=10000,
    parameter ASSERT_PS=1000    )
(   output reg rst_n            );
initial begin
    rst_n = 1;
    #(ASSERT_PS)
    rst_n = 0;
    #(RELEASE_PS-ASSERT_PS)
     rst_n = 1;
end
endmodule
module rst_gen
#(  parameter RELEASE_PS=10000,
    parameter ASSERT_PS=1000    )
(   output reg rst_n            );

initial begin
    rst_n = 1;
    #(ASSERT_PS)
    rst_n = 0;
    #(RELEASE_PS-ASSERT_PS)
     rst_n = 1;
end
endmodule