data/full_repos/permissive/105948944/sources/signalSync.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/105948944/sources/signalSync.v:30: Little bit endian vector: MSB < LSB of bit range: 1:3\n  reg [1:3] resync;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module signalSync(
    input clock,
    input asynchronous_signal,
    output rising_edge,
    output falling_edge
);

  reg [1:3] resync;
  reg fall, rise;
    
  initial 
  begin
    fall <= 0;
    rise <= 0;
    resync <= 0;
  end
  


  
  always @(posedge clock)
  begin


    fall <= resync[3] & !resync[2];
    rise <= resync[2] & !resync[3];

    resync <= {asynchronous_signal , resync[1:2]};
  end
  
  
  assign rising_edge = rise;
  assign falling_edge = fall;
endmodule
module signalSync(
    input clock,
    input asynchronous_signal,
    output rising_edge,
    output falling_edge
);


  reg [1:3] resync;
  reg fall, rise;
    
  initial 
  begin
    fall <= 0;
    rise <= 0;
    resync <= 0;
  end
  


  
  always @(posedge clock)
  begin


    fall <= resync[3] & !resync[2];
    rise <= resync[2] & !resync[3];

    resync <= {asynchronous_signal , resync[1:2]};
  end
  
  
  assign rising_edge = rise;
  assign falling_edge = fall;
endmodule