data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v
 line:100: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n             ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n            ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n                ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n                                                                                              : ... In instance multicpu.alu\n   zero = ALUResult ? 0 : 1;\n                    ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ControlUnit(
   input clk,zero,rst,
	input [5:0] op,
	output reg WrRegData, ExtSel, RegWre, ALUSrcB, ALUSrcA, InsMemRW, IRWre, RD, WR, ALUM2Reg, PCWre,
	output reg[2:0] ALUOp,
	output reg[1:0] RegDst, PCSrc
    );
	
	parameter[2:0] If=3'b000, id=3'b001,
		exe1=3'b110,
		exe2=3'b101,
		exe3=3'b010,
		wb1=3'b111,
		wb2=3'b100,
		mem=3'b011;
	
	parameter[5:0] addu=6'b000000, subu=6'b000001, addiu=6'b000010,
		Or=6'b010000, And=6'b010001, ori=6'b010010, sll=6'b011000,
		sltu=6'b100110, slt=6'b100111, sw=6'b110000, lw=6'b110001,
		beq=6'b110100, j=6'b111000, jr=6'b111001, jal=6'b111010, halt=6'b111111;
	
	reg [2:0] state,nextstate;
	
	initial
		begin
			PCWre=1;
			ALUSrcA=0;
			ALUSrcB=0;
			ALUM2Reg=0;
			RegWre=0;
			WrRegData=0;
			InsMemRW=0;
			RD=0;
			WR=0;
			IRWre=1;
			ExtSel=1;
			PCSrc=2'b00;
			RegDst=2'b01;
			ALUOp=3'b000;
			state=If;
			nextstate=state;
		end
	
	always@(posedge clk)
		begin
			if(rst==0)
				state<=If;
			else
				state<=nextstate;
		end
		
	always@(state or op)
		begin
			case(state)
				If:nextstate=id;
				id:begin
						case(op)
							beq:nextstate=exe2;
							sw:nextstate=exe3;
							lw:nextstate=exe3;
							j:nextstate=If;
							jal:nextstate=wb1;
							jr:nextstate=If;
							halt:nextstate=If;
							addu:nextstate=exe1;
							subu:nextstate=exe1;
							addiu:nextstate=exe1;
							Or:nextstate=exe1;
							And:nextstate=exe1;
							ori:nextstate=exe1;
							sll:nextstate=exe1;
							sltu:nextstate=exe1;
							slt:nextstate=exe1;
						endcase
					end
				exe1:nextstate=wb1;
				exe2:nextstate=If;
				exe3:nextstate=mem;
				mem:if(op==lw) nextstate=wb2;
					 else if(op==sw) nextstate=If;
				wb1:nextstate=If;
				wb2:nextstate=If;
			endcase
		end
		
		always@(state)


			begin
				if(state==If && op != halt) PCWre=1;
				else PCWre=0;
				
				if(op==sll) ALUSrcA=1;
				else ALUSrcA=0;
				
				if(op==addiu||op==ori||op==lw||op==sw) ALUSrcB=1;
				else ALUSrcB=0;
				
				if(op==lw) ALUM2Reg=1;
				else ALUM2Reg=0;
				
				if(state==wb1||state==wb2||op==jal) RegWre=1;
				else RegWre=0;
				
				if(op==jal) WrRegData=0;
				else WrRegData=1;
				
				InsMemRW=1;
				
				if(state==mem && op==sw)
					begin
						WR=1;
						RD=0;
					end
				else
					begin
						WR=0;
						RD=1;
					end
				
				if(op !=halt) IRWre=1;
				else IRWre=0;
				
				if(op==ori) ExtSel=0;
				else ExtSel=1;
				
				case(op)
					j:PCSrc=2'b11;
					jal:PCSrc=2'b11;
					jr:PCSrc=2'b10;
					beq:if(zero) PCSrc=2'b01;
						 else PCSrc=2'b00;
					default:PCSrc=2'b00;
				endcase
				
				if(op==jal) RegDst=2'b00;
				else if(op==addiu||op==ori||op==lw) RegDst=2'b01;
				else if(op==addu||op==subu||op==Or||op==And||op==sltu||op==sll||op==slt) RegDst=2'b10;
			
				case(op)
					subu:ALUOp=3'b001;
					Or:ALUOp=3'b101;
					And:ALUOp=3'b110;
					ori:ALUOp=3'b101;
					sll:ALUOp=3'b100;
					sltu:ALUOp=3'b010;
					beq:ALUOp=3'b001;
					slt:ALUOp = 3'b011;
					default: ALUOp=3'b000;
				endcase
				
				if(state==If)
					begin
						RegWre=0;
						WR=0;
					end
			end
endmodule
module ControlUnit(
   input clk,zero,rst,
	input [5:0] op,
	output reg WrRegData, ExtSel, RegWre, ALUSrcB, ALUSrcA, InsMemRW, IRWre, RD, WR, ALUM2Reg, PCWre,
	output reg[2:0] ALUOp,
	output reg[1:0] RegDst, PCSrc
    );

	
	parameter[2:0] If=3'b000, id=3'b001,
		exe1=3'b110,
		exe2=3'b101,
		exe3=3'b010,
		wb1=3'b111,
		wb2=3'b100,
		mem=3'b011;
	
	parameter[5:0] addu=6'b000000, subu=6'b000001, addiu=6'b000010,
		Or=6'b010000, And=6'b010001, ori=6'b010010, sll=6'b011000,
		sltu=6'b100110, slt=6'b100111, sw=6'b110000, lw=6'b110001,
		beq=6'b110100, j=6'b111000, jr=6'b111001, jal=6'b111010, halt=6'b111111;
	
	reg [2:0] state,nextstate;
	
	initial
		begin
			PCWre=1;
			ALUSrcA=0;
			ALUSrcB=0;
			ALUM2Reg=0;
			RegWre=0;
			WrRegData=0;
			InsMemRW=0;
			RD=0;
			WR=0;
			IRWre=1;
			ExtSel=1;
			PCSrc=2'b00;
			RegDst=2'b01;
			ALUOp=3'b000;
			state=If;
			nextstate=state;
		end
	
	always@(posedge clk)
		begin
			if(rst==0)
				state<=If;
			else
				state<=nextstate;
		end
		
	always@(state or op)
		begin
			case(state)
				If:nextstate=id;
				id:begin
						case(op)
							beq:nextstate=exe2;
							sw:nextstate=exe3;
							lw:nextstate=exe3;
							j:nextstate=If;
							jal:nextstate=wb1;
							jr:nextstate=If;
							halt:nextstate=If;
							addu:nextstate=exe1;
							subu:nextstate=exe1;
							addiu:nextstate=exe1;
							Or:nextstate=exe1;
							And:nextstate=exe1;
							ori:nextstate=exe1;
							sll:nextstate=exe1;
							sltu:nextstate=exe1;
							slt:nextstate=exe1;
						endcase
					end
				exe1:nextstate=wb1;
				exe2:nextstate=If;
				exe3:nextstate=mem;
				mem:if(op==lw) nextstate=wb2;
					 else if(op==sw) nextstate=If;
				wb1:nextstate=If;
				wb2:nextstate=If;
			endcase
		end
		
		always@(state)


			begin
				if(state==If && op != halt) PCWre=1;
				else PCWre=0;
				
				if(op==sll) ALUSrcA=1;
				else ALUSrcA=0;
				
				if(op==addiu||op==ori||op==lw||op==sw) ALUSrcB=1;
				else ALUSrcB=0;
				
				if(op==lw) ALUM2Reg=1;
				else ALUM2Reg=0;
				
				if(state==wb1||state==wb2||op==jal) RegWre=1;
				else RegWre=0;
				
				if(op==jal) WrRegData=0;
				else WrRegData=1;
				
				InsMemRW=1;
				
				if(state==mem && op==sw)
					begin
						WR=1;
						RD=0;
					end
				else
					begin
						WR=0;
						RD=1;
					end
				
				if(op !=halt) IRWre=1;
				else IRWre=0;
				
				if(op==ori) ExtSel=0;
				else ExtSel=1;
				
				case(op)
					j:PCSrc=2'b11;
					jal:PCSrc=2'b11;
					jr:PCSrc=2'b10;
					beq:if(zero) PCSrc=2'b01;
						 else PCSrc=2'b00;
					default:PCSrc=2'b00;
				endcase
				
				if(op==jal) RegDst=2'b00;
				else if(op==addiu||op==ori||op==lw) RegDst=2'b01;
				else if(op==addu||op==subu||op==Or||op==And||op==sltu||op==sll||op==slt) RegDst=2'b10;
			
				case(op)
					subu:ALUOp=3'b001;
					Or:ALUOp=3'b101;
					And:ALUOp=3'b110;
					ori:ALUOp=3'b101;
					sll:ALUOp=3'b100;
					sltu:ALUOp=3'b010;
					beq:ALUOp=3'b001;
					slt:ALUOp = 3'b011;
					default: ALUOp=3'b000;
				endcase
				
				if(state==If)
					begin
						RegWre=0;
						WR=0;
					end
			end
endmodule