data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v
1: b"%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:170: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n  output [DATA_WIDTH_R-1:0] do,\n                            ^~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:206: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  output [DATA_WIDTH_R-1:0] do,\n                            ^~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:225: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  output [3:0]do\n              ^~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:759: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  input [3:0] do,\n              ^~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:893: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  output [7:0] do,\n               ^~\n%Error: Exiting due to 5 error(s)\n"
module EG_PHY_PAD(
  input ipad,
  output opad,
  inout bpad,
  input rst,
  input ce,
  input isclk,
  input ipclk,
  input osclk,
  input opclk,
  input ts,
  input [3:0] do,
  output di,
  output [3:0] diq
);
  parameter DEDCLK = "DISABLE";
  parameter GSR = "ENABLE";
  parameter SRMODE = "SYNC";
  parameter TSMUX = "1";
  parameter INSCLKMUX = "0";
  parameter INPCLKMUX = "CLK";
  parameter INCEMUX = "CE";
  parameter INRSTMUX = "0";
  parameter IN_REGSET = "RESET";
  parameter IN_DFFMODE = "NONE";
  parameter IDDRMODE = "OFF";
  parameter IDDRPIPEMODE = "NONE";
  parameter INDELMUX = "NODEL";
  parameter INDEL = 0;
  parameter OUTSCLKMUX = "0";
  parameter OUTPCLKMUX = "CLK";
  parameter OUTCEMUX = "CE";
  parameter OUTRSTMUX = "0";
  parameter DO_REGSET = "RESET";
  parameter DO_DFFMODE = "NONE";
  parameter ODDRMODE = "OFF";
  parameter OUTDELMUX = "NODEL";
  parameter OUTDEL = 0;
  parameter TO_REGSET = "RESET";
  parameter TO_DFFMODE = "NONE";
  parameter MODE = "IN";
  parameter DRIVE = "NONE";
  parameter IOTYPE = "LVCMOS25";
endmodule
module EG_PHY_PAD(
  input ipad,
  output opad,
  inout bpad,
  input rst,
  input ce,
  input isclk,
  input ipclk,
  input osclk,
  input opclk,
  input ts,
  input [3:0] do,
  output di,
  output [3:0] diq
);

  parameter DEDCLK = "DISABLE";
  parameter GSR = "ENABLE";
  parameter SRMODE = "SYNC";
  parameter TSMUX = "1";
  parameter INSCLKMUX = "0";
  parameter INPCLKMUX = "CLK";
  parameter INCEMUX = "CE";
  parameter INRSTMUX = "0";
  parameter IN_REGSET = "RESET";
  parameter IN_DFFMODE = "NONE";
  parameter IDDRMODE = "OFF";
  parameter IDDRPIPEMODE = "NONE";
  parameter INDELMUX = "NODEL";
  parameter INDEL = 0;
  parameter OUTSCLKMUX = "0";
  parameter OUTPCLKMUX = "CLK";
  parameter OUTCEMUX = "CE";
  parameter OUTRSTMUX = "0";
  parameter DO_REGSET = "RESET";
  parameter DO_DFFMODE = "NONE";
  parameter ODDRMODE = "OFF";
  parameter OUTDELMUX = "NODEL";
  parameter OUTDEL = 0;
  parameter TO_REGSET = "RESET";
  parameter TO_DFFMODE = "NONE";
  parameter MODE = "IN";
  parameter DRIVE = "NONE";
  parameter IOTYPE = "LVCMOS25";
endmodule