data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v
'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte
1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n             const_defination.v\n             const_defination.v.v\n             const_defination.v.sv\n             obj_dir/const_defination.v\n             obj_dir/const_defination.v.v\n             obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:27: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] M,E,   \n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`digitsBus] M,E,   \n                         ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:29: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[63:0] d_rvalA,d_rvalB   \n    ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:30: syntax error, unexpected \')\', expecting \',\' or \';\'\n    );\n    ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:35: syntax error, unexpected always\n    always@(posedge clk)\n    ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:37: Define or directive not defined: \'`NONE\'\n  if(dstM!=`NONE)\n           ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:46: Define or directive not defined: \'`NONE\'\n  if(dstE!=`NONE)\n           ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:55: Define or directive not defined: \'`NONE\'\n  if(srcA!=`NONE)\n           ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/regFile.v:64: Define or directive not defined: \'`NONE\'\n  if(srcB!=`NONE)\n           ^~~~~\n%Error: Exiting due to 10 error(s)\n'
module regFile(
    input wire clk,
    input wire[3:0] dstE,dstM,
    input wire[`digitsBus] M,E,
    input wire[3:0] srcA,srcB,
    output reg[63:0] d_rvalA,d_rvalB
    );
    
    reg[63:0] regs[0:15];
    

    always@(posedge clk)
    begin
		if(dstM!=`NONE)
		begin
			regs[dstM]=M;
		end
    end
    

    always@(posedge clk)
    begin
		if(dstE!=`NONE)
		begin
			regs[dstE]=E;
		end
    end   
    

    always@(*)
    begin
		if(srcA!=`NONE)
		begin
			d_rvalA<=regs[srcA];
		end
    end
    
    
    always@(*)
    begin
		if(srcB!=`NONE)
		begin
			d_rvalB<=regs[srcB];
		end
    end    
endmodule
module regFile(
    input wire clk,
    input wire[3:0] dstE,dstM,
    input wire[`digitsBus] M,E,
    input wire[3:0] srcA,srcB,
    output reg[63:0] d_rvalA,d_rvalB
    );

    
    reg[63:0] regs[0:15];
    

    always@(posedge clk)
    begin
		if(dstM!=`NONE)
		begin
			regs[dstM]=M;
		end
    end
    

    always@(posedge clk)
    begin
		if(dstE!=`NONE)
		begin
			regs[dstE]=E;
		end
    end   
    

    always@(*)
    begin
		if(srcA!=`NONE)
		begin
			d_rvalA<=regs[srcA];
		end
    end
    
    
    always@(*)
    begin
		if(srcB!=`NONE)
		begin
			d_rvalB<=regs[srcB];
		end
    end    
endmodule