data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v
 line:40: before: "."
1: b'%Warning-MULTITOP: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:464: Multiple top level modules\n                                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                 : ... Top module \'fpga_top\'\nmodule fpga_top(\n       ^~~~~~~~\n                                                                                                 : ... Top module \'WF_neo_fading_rom\'\nmodule WF_neo_fading_rom ( rd_data, rd_addr,clk);\n       ^~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:44: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:46: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:52: Signal definition not found, creating implicitly: \'five_ms\'\n           .timer_pulse(five_ms));\n                        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:60: Signal definition not found, creating implicitly: \'switch_pushed\'\n      .switch_pushed(switch_pushed),     \n                     ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:349: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                              : ... In instance fpga_top.neopixel_inst\n                   pixel_bit_cnt <= 1\'b0;\n                                 ^~\n%Error: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:478: Cannot find file containing module: \'SB_RAM256x16\'\n                 SB_RAM256x16  ram ( .WDATA(16\'b0),\n                 ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_RAM256x16\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_RAM256x16.v\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_RAM256x16.sv\n             SB_RAM256x16\n             SB_RAM256x16.v\n             SB_RAM256x16.sv\n             obj_dir/SB_RAM256x16\n             obj_dir/SB_RAM256x16.v\n             obj_dir/SB_RAM256x16.sv\n%Error: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:34: Cannot find file containing module: \'SB_HFOSC\'\n  SB_HFOSC OSC_i (\n  ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h1\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h2\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h3\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Error: Exiting due to 2 error(s), 14 warning(s)\n'
module fpga_top(
    output wire DOUT,
    input  wire WF_CPU1,
    input  wire WF_BUTTON
);


   wire      clk_en = 1'b1;

   reg  [23:0] pixel0;  
   reg  [23:0] pixel1;
   reg  [23:0] pixel2;
   reg  [23:0] pixel3;
   reg  [23:0] pixel4;
   reg  [23:0] pixel5;
   reg  [23:0] pixel6;
   reg  [23:0] pixel7;	
   reg  [23:0] np_pixels;
   wire [ 7:0] ram_rd_addr;


   reg       cpu_in_d;
   wire      cpu_toggled;







  SB_HFOSC OSC_i (
	    .CLKHFEN(clk_en),
	    .CLKHFPU(clk_en),
	    .CLKHF(clk));


   defparam OSC_i.CLKHF_DIV = "0b10";


     WF_timer #(.COUNT(119), .EVERY_CLK(1'b1)) ten_usec(
           .clk(clk),
           .enable(1'b1),
           .timer_pulse(ten_us));


     WF_timer #(.COUNT(499)) five_msec(
           .clk(clk),
           .enable(ten_us),
           .timer_pulse(five_ms));


    WF_switch_debounce switch_deb1 (
      .clk(clk),
      .sample_en(five_ms),
      .switch_in(WF_BUTTON),
      .switch_out(),
      .switch_pushed(switch_pushed),
      .switch_released()
     );


    WF_neopixel_if #(
	   .NUM_OF_PIXELS(8))
    neopixel_inst(
           .clk(clk),
           .ten_us(ten_us),
           .ram_rd_addr(ram_rd_addr),
           .ram_rd_data(np_pixels),
           .DOUT(DOUT));


















  reg [1:0] cnt;
  reg [6:0] cnt2;
  reg [2:0] cnt3;
  reg       updn;
  reg       updn_d;
  reg [2:0] ph;


  wire [6:0] cnt2_G = {cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};
  wire [6:0] cnt2_R = {cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};
  wire [6:0] cnt2_B = {cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};


   always @(posedge clk)
     begin
       if (five_ms)
         begin
           cnt <= cnt + 'h01;
           if (cnt == 0)
             begin
               if (cnt2 ==  127)
	         begin
                   cnt2 <= 126;
                   updn <= ~updn;
	           if (ph==5) ph <= 0; else ph <= ph + 1;
	         end
	       else if (cnt2 == 1 && updn ==1)
	         begin
                   cnt2 <= 1;
                   updn <= ~updn;
	           if (ph==5) ph <= 0; else ph <= ph + 1;
	         end
	       else if (updn==0)
                 cnt2 <= cnt2 + 7'b1;
	       else
                 cnt2 <= cnt2 - 7'b1;
	   end
         end




         pixel0[23:0] <= {8'b0,8'b0,cnt2_G,1'b0};
         pixel1[23:0] <= {8'b0,cnt2_R,1'b0,8'b0};
         pixel2[23:0] <= {cnt2_B,1'b0,8'b0,8'b0};

         pixel3[0]  <= ~cnt3[0];
         pixel3[8]  <= ~cnt3[1];
         pixel3[16] <= ~cnt3[2];

         pixel4[23:0] <= {cnt2_B,1'b0, ~cnt2_R,1'b0,8'b0};
         pixel5[23:0] <= {8'b0, ~cnt2_R,1'b0,cnt2_G,1'b0};

	 if (ph==0)
           pixel6[23:0] <= {8'h80,        ~cnt2_R,1'b0,   cnt2_G,1'b0};
         if (ph==1)
           pixel6[23:0] <= {~cnt2_B, 1'b0, 8'h80,         cnt2_G,1'b0};
         if (ph==2)
           pixel6[23:0] <= {~cnt2_B, 1'b0,  cnt2_R,1'b0,   8'h80};
         if (ph==3)
           pixel6[23:0] <= {8'h80,         cnt2_R,1'b0,   ~cnt2_G,1'b0};
         if (ph==4)
           pixel6[23:0] <= {cnt2_B,1'b0,   8'h80,         ~cnt2_G,1'b0};
         if (ph==5)
           pixel6[23:0] <= {cnt2_B,1'b0,  ~cnt2_R,1'b0,    8'h80};
         pixel7[23:0] <= 
		    {~pixel6[23:17],1'b0,~pixel6[15:9],1'b0,~pixel6[7:1],1'b0};
   
         updn_d <= updn; 
     end




   always @(*)
      case (ram_rd_addr)
        3'h0 : np_pixels = pixel0;
        3'h1 : np_pixels = pixel1;
        3'h2 : np_pixels = pixel2;
        3'h3 : np_pixels = pixel3;
        3'h4 : np_pixels = pixel4;
        3'h5 : np_pixels = pixel5;
        3'h6 : np_pixels = pixel6;
        3'h7 : np_pixels = pixel7;
     endcase



   always @ (posedge clk)
       cpu_in_d <= WF_CPU1;

    assign cpu_toggled = (cpu_in_d && ~WF_CPU1) || (~cpu_in_d && WF_CPU1);

     always @(posedge clk)
       if (cpu_toggled || switch_pushed)  
          cnt3 <= cnt3 + 3'b1;

endmodule
module fpga_top(
    output wire DOUT,
    input  wire WF_CPU1,
    input  wire WF_BUTTON
);



   wire      clk_en = 1'b1;

   reg  [23:0] pixel0;  
   reg  [23:0] pixel1;
   reg  [23:0] pixel2;
   reg  [23:0] pixel3;
   reg  [23:0] pixel4;
   reg  [23:0] pixel5;
   reg  [23:0] pixel6;
   reg  [23:0] pixel7;	
   reg  [23:0] np_pixels;
   wire [ 7:0] ram_rd_addr;


   reg       cpu_in_d;
   wire      cpu_toggled;







  SB_HFOSC OSC_i (
	    .CLKHFEN(clk_en),
	    .CLKHFPU(clk_en),
	    .CLKHF(clk));


   defparam OSC_i.CLKHF_DIV = "0b10";


     WF_timer #(.COUNT(119), .EVERY_CLK(1'b1)) ten_usec(
           .clk(clk),
           .enable(1'b1),
           .timer_pulse(ten_us));


     WF_timer #(.COUNT(499)) five_msec(
           .clk(clk),
           .enable(ten_us),
           .timer_pulse(five_ms));


    WF_switch_debounce switch_deb1 (
      .clk(clk),
      .sample_en(five_ms),
      .switch_in(WF_BUTTON),
      .switch_out(),
      .switch_pushed(switch_pushed),
      .switch_released()
     );


    WF_neopixel_if #(
	   .NUM_OF_PIXELS(8))
    neopixel_inst(
           .clk(clk),
           .ten_us(ten_us),
           .ram_rd_addr(ram_rd_addr),
           .ram_rd_data(np_pixels),
           .DOUT(DOUT));


















  reg [1:0] cnt;
  reg [6:0] cnt2;
  reg [2:0] cnt3;
  reg       updn;
  reg       updn_d;
  reg [2:0] ph;


  wire [6:0] cnt2_G = {cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};
  wire [6:0] cnt2_R = {cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};
  wire [6:0] cnt2_B = {cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};


   always @(posedge clk)
     begin
       if (five_ms)
         begin
           cnt <= cnt + 'h01;
           if (cnt == 0)
             begin
               if (cnt2 ==  127)
	         begin
                   cnt2 <= 126;
                   updn <= ~updn;
	           if (ph==5) ph <= 0; else ph <= ph + 1;
	         end
	       else if (cnt2 == 1 && updn ==1)
	         begin
                   cnt2 <= 1;
                   updn <= ~updn;
	           if (ph==5) ph <= 0; else ph <= ph + 1;
	         end
	       else if (updn==0)
                 cnt2 <= cnt2 + 7'b1;
	       else
                 cnt2 <= cnt2 - 7'b1;
	   end
         end




         pixel0[23:0] <= {8'b0,8'b0,cnt2_G,1'b0};
         pixel1[23:0] <= {8'b0,cnt2_R,1'b0,8'b0};
         pixel2[23:0] <= {cnt2_B,1'b0,8'b0,8'b0};

         pixel3[0]  <= ~cnt3[0];
         pixel3[8]  <= ~cnt3[1];
         pixel3[16] <= ~cnt3[2];

         pixel4[23:0] <= {cnt2_B,1'b0, ~cnt2_R,1'b0,8'b0};
         pixel5[23:0] <= {8'b0, ~cnt2_R,1'b0,cnt2_G,1'b0};

	 if (ph==0)
           pixel6[23:0] <= {8'h80,        ~cnt2_R,1'b0,   cnt2_G,1'b0};
         if (ph==1)
           pixel6[23:0] <= {~cnt2_B, 1'b0, 8'h80,         cnt2_G,1'b0};
         if (ph==2)
           pixel6[23:0] <= {~cnt2_B, 1'b0,  cnt2_R,1'b0,   8'h80};
         if (ph==3)
           pixel6[23:0] <= {8'h80,         cnt2_R,1'b0,   ~cnt2_G,1'b0};
         if (ph==4)
           pixel6[23:0] <= {cnt2_B,1'b0,   8'h80,         ~cnt2_G,1'b0};
         if (ph==5)
           pixel6[23:0] <= {cnt2_B,1'b0,  ~cnt2_R,1'b0,    8'h80};
         pixel7[23:0] <= 
		    {~pixel6[23:17],1'b0,~pixel6[15:9],1'b0,~pixel6[7:1],1'b0};
   
         updn_d <= updn; 
     end




   always @(*)
      case (ram_rd_addr)
        3'h0 : np_pixels = pixel0;
        3'h1 : np_pixels = pixel1;
        3'h2 : np_pixels = pixel2;
        3'h3 : np_pixels = pixel3;
        3'h4 : np_pixels = pixel4;
        3'h5 : np_pixels = pixel5;
        3'h6 : np_pixels = pixel6;
        3'h7 : np_pixels = pixel7;
     endcase



   always @ (posedge clk)
       cpu_in_d <= WF_CPU1;

    assign cpu_toggled = (cpu_in_d && ~WF_CPU1) || (~cpu_in_d && WF_CPU1);

     always @(posedge clk)
       if (cpu_toggled || switch_pushed)  
          cnt3 <= cnt3 + 3'b1;

endmodule