data/full_repos/permissive/122693972/hdlsrc/dut.v
data/verilator_xmls/c217bdb6-e477-47b9-b4ff-44ad0fda257d.xml
module u_add_1(
  IN  ,
  OUT );

parameter WL  = 8       ;

input  [WL -1:0] IN ;
output [WL -1:0] OUT;

reg    [WL-1:0] W_add;

always @ (IN) begin
  W_add = IN + 1;
end

assign OUT = W_add;

endmodule
module u_add_1(
  IN  ,
  OUT );


parameter WL  = 8       ;

input  [WL -1:0] IN ;
output [WL -1:0] OUT;

reg    [WL-1:0] W_add;

always @ (IN) begin
  W_add = IN + 1;
end

assign OUT = W_add;

endmodule