data/full_repos/permissive/191241380/common/vgatext.v
1: b"%Error: data/full_repos/permissive/191241380/common/vgatext.v:38: Cannot find file containing module: 'videosyncs'\n  videosyncs sincronismos (   \n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191241380/common,data/full_repos/permissive/191241380/videosyncs\n             data/full_repos/permissive/191241380/common,data/full_repos/permissive/191241380/videosyncs.v\n             data/full_repos/permissive/191241380/common,data/full_repos/permissive/191241380/videosyncs.sv\n             videosyncs\n             videosyncs.v\n             videosyncs.sv\n             obj_dir/videosyncs\n             obj_dir/videosyncs.v\n             obj_dir/videosyncs.sv\n%Error: Exiting due to 1 error(s)\n"
module vram (
  input wire clk,


  input wire [11:0] addr_sys,
  input wire [7:0] din_sys,
  input wire we_sys,
  output wire [7:0] dout_sys,


  input wire [10:0] addr_video,
  output reg [7:0] char_video,
  output reg [7:0] attr_video,

  input wire [11:0] bmaddr,
  output reg [7:0] bitmap
  );


  reg [7:0] dout_char, dout_attr;
  assign dout_sys = (addr_sys[11] == 1'b0)? dout_char : dout_attr;
  
  (* ram_style = "block" *) reg [7:0] chram[0:2047];
  (* ram_style = "block" *) reg [7:0] colram[0:2047];
  (* ram_style = "block" *) reg [7:0] bmram[0:4095];
  
  integer i;

  initial begin
    for (i=0;i<2048;i=i+1) begin
      chram[i]  = i[7:0];
      colram[i] = {1'b0,i[5:3],1'b0,i[2:0]};
    end
    $readmemh ("../resources/ibm_vga_8x16.hex", bmram);
  end

  always @(posedge clk) begin
    char_video <= chram[addr_video];
    attr_video <= colram[addr_video];
    bitmap <= bmram[bmaddr];

    dout_char <= chram[addr_sys[10:0]];
    dout_attr <= colram[addr_sys[10:0]];

    if (we_sys == 1'b1) begin
      if (addr_sys[11] == 1'b0)
        chram[addr_sys[10:0]] <= din_sys;
      else
        colram[addr_sys[10:0]] <= din_sys;
    end
  end
endmodule
module vram (
  input wire clk,


  input wire [11:0] addr_sys,
  input wire [7:0] din_sys,
  input wire we_sys,
  output wire [7:0] dout_sys,


  input wire [10:0] addr_video,
  output reg [7:0] char_video,
  output reg [7:0] attr_video,

  input wire [11:0] bmaddr,
  output reg [7:0] bitmap
  );



  reg [7:0] dout_char, dout_attr;
  assign dout_sys = (addr_sys[11] == 1'b0)? dout_char : dout_attr;
  
  (* ram_style = "block" *) reg [7:0] chram[0:2047];
  (* ram_style = "block" *) reg [7:0] colram[0:2047];
  (* ram_style = "block" *) reg [7:0] bmram[0:4095];
  
  integer i;

  initial begin
    for (i=0;i<2048;i=i+1) begin
      chram[i]  = i[7:0];
      colram[i] = {1'b0,i[5:3],1'b0,i[2:0]};
    end
    $readmemh ("../resources/ibm_vga_8x16.hex", bmram);
  end

  always @(posedge clk) begin
    char_video <= chram[addr_video];
    attr_video <= colram[addr_video];
    bitmap <= bmram[bmaddr];

    dout_char <= chram[addr_sys[10:0]];
    dout_attr <= colram[addr_sys[10:0]];

    if (we_sys == 1'b1) begin
      if (addr_sys[11] == 1'b0)
        chram[addr_sys[10:0]] <= din_sys;
      else
        colram[addr_sys[10:0]] <= din_sys;
    end
  end
endmodule