data/full_repos/permissive/207111076/jt51/deprecated/jt51_sh2.v
data/verilator_xmls/dc8f9b34-6e4f-4c1f-8c23-6fbcb2e00dd8.xml
module jt51_sh1 #(parameter stages=32)
(
	input 	clk,
	input	en,
	input	ld,
	input	din,
   	output	drop
);

reg	[stages-1:0] shift;
assign drop = shift[0];
wire next = ld ? din : drop;

always @(posedge clk ) 
	if( en )
		shift <= {next, shift[stages-1:1]};

endmodule
module jt51_sh1 #(parameter stages=32)
(
	input 	clk,
	input	en,
	input	ld,
	input	din,
   	output	drop
);


reg	[stages-1:0] shift;
assign drop = shift[0];
wire next = ld ? din : drop;

always @(posedge clk ) 
	if( en )
		shift <= {next, shift[stages-1:1]};

endmodule