data/full_repos/permissive/146975244/Instructions.v
1: b'%Warning-WIDTH: data/full_repos/permissive/146975244/Instructions.v:40: Bit extraction of array[31:0] requires 5 bit index, not 11 bits.\n                                                                      : ... In instance Instructions\nassign Inst = ramInstrucoes[PC];\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module  Instructions (PC,Inst, clock);

input clock;
output   [31:0] Inst;
input 	[10:0] PC;
reg 		[31:0] ramInstrucoes [31:0];

initial begin






	






	



	ramInstrucoes[0] = {{6'b001110},{5'b00000},{5'b00100},{5'b00000},{5'b00000},{6'b000000}};

	ramInstrucoes[1] = {{6'b011000},{5'b00000},{5'b00001},{5'b00000},{5'b00000},{6'b000000}};
	ramInstrucoes[2] = {{6'b011000},{5'b00000},{5'b00010},{5'b00000},{5'b00000},{6'b000001}};
	ramInstrucoes[3] = {{6'b011000},{5'b00000},{5'b00101},{5'b00000},{5'b00000},{6'b000001}};
	ramInstrucoes[4] = {{6'b000000},{5'b00010},{5'b00001},{5'b00011},{5'b00000},{6'b000000}};
	ramInstrucoes[5] = {{6'b001000},{5'b00010},{5'b00001},{5'b00000},{5'b00000},{6'b000000}};
	ramInstrucoes[6] = {{6'b001001},{5'b00011},{5'b00010},{5'b00000},{5'b00000},{6'b000000}};
	ramInstrucoes[7] = {{6'b001000},{5'b00101},{5'b00101},{5'b00000},{5'b00000},{6'b000001}};
	ramInstrucoes[8] = {{6'b001010},{5'b00101},{5'b00100},{5'b00000},{5'b00000},{6'b000010}};
	ramInstrucoes[9] = {{6'b001011},{5'b00101},{5'b00100},{16'b1111111111111011}};
	ramInstrucoes[10] = {{6'b001111},{5'b00000},{5'b00011},{5'b00000},{5'b00000},{6'b000000}};
	ramInstrucoes[11] = {{6'b111001},{5'b00001},{5'b00010},{5'b00011},{5'b00000},{6'b001010}};
end
assign Inst = ramInstrucoes[PC];

endmodule
module  Instructions (PC,Inst, clock);


input clock;
output   [31:0] Inst;
input 	[10:0] PC;
reg 		[31:0] ramInstrucoes [31:0];

initial begin






	






	



	ramInstrucoes[0] = {{6'b001110},{5'b00000},{5'b00100},{5'b00000},{5'b00000},{6'b000000}};

	ramInstrucoes[1] = {{6'b011000},{5'b00000},{5'b00001},{5'b00000},{5'b00000},{6'b000000}};
	ramInstrucoes[2] = {{6'b011000},{5'b00000},{5'b00010},{5'b00000},{5'b00000},{6'b000001}};
	ramInstrucoes[3] = {{6'b011000},{5'b00000},{5'b00101},{5'b00000},{5'b00000},{6'b000001}};
	ramInstrucoes[4] = {{6'b000000},{5'b00010},{5'b00001},{5'b00011},{5'b00000},{6'b000000}};
	ramInstrucoes[5] = {{6'b001000},{5'b00010},{5'b00001},{5'b00000},{5'b00000},{6'b000000}};
	ramInstrucoes[6] = {{6'b001001},{5'b00011},{5'b00010},{5'b00000},{5'b00000},{6'b000000}};
	ramInstrucoes[7] = {{6'b001000},{5'b00101},{5'b00101},{5'b00000},{5'b00000},{6'b000001}};
	ramInstrucoes[8] = {{6'b001010},{5'b00101},{5'b00100},{5'b00000},{5'b00000},{6'b000010}};
	ramInstrucoes[9] = {{6'b001011},{5'b00101},{5'b00100},{16'b1111111111111011}};
	ramInstrucoes[10] = {{6'b001111},{5'b00000},{5'b00011},{5'b00000},{5'b00000},{6'b000000}};
	ramInstrucoes[11] = {{6'b111001},{5'b00001},{5'b00010},{5'b00011},{5'b00000},{6'b001010}};
end
assign Inst = ramInstrucoes[PC];

endmodule