data/full_repos/permissive/126791278/testbenches/tb_alu.v
 line:22: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_alu.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #20  op=3\'d0; a=16\'d54; b=16\'d5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_alu.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #20  op=3\'d1; a=16\'d54; b=16\'d5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_alu.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #20  op=3\'d2; a=16\'d54; b=16\'d5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_alu.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #20  op=3\'d3; a=16\'d54; b=16\'d5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_alu.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #20  op=3\'d4; a=16\'d54; b=16\'d5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_alu.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #20  op=3\'d5; a=16\'d54; b=16\'d5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_alu.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #20  op=3\'d6; a=16\'d54; b=16\'d5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_alu.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #20  op=3\'d7; a=16\'d54; b=16\'d5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_alu.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #20  $stop;\n  ^\n%Error: data/full_repos/permissive/126791278/testbenches/tb_alu.v:27: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("alu.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/126791278/testbenches/tb_alu.v:28: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_alu();

	wire [15:0] out;
	wire z;
	reg [15:0] a,b;
	reg [2:0] op;

	alu uut(out,z,a,b,op);

	initial
	begin
		#20  op=3'd0; a=16'd54; b=16'd5;
		#20  op=3'd1; a=16'd54; b=16'd5;
		#20  op=3'd2; a=16'd54; b=16'd5;
		#20  op=3'd3; a=16'd54; b=16'd5;
		#20  op=3'd4; a=16'd54; b=16'd5;
		#20  op=3'd5; a=16'd54; b=16'd5;
		#20  op=3'd6; a=16'd54; b=16'd5;
		#20  op=3'd7; a=16'd54; b=16'd5;
		#20  $stop;
	end

	initial
	begin
		$dumpfile("alu.vcd");
		$dumpvars;
	end

endmodule
module tb_alu();


	wire [15:0] out;
	wire z;
	reg [15:0] a,b;
	reg [2:0] op;

	alu uut(out,z,a,b,op);

	initial
	begin
		#20  op=3'd0; a=16'd54; b=16'd5;
		#20  op=3'd1; a=16'd54; b=16'd5;
		#20  op=3'd2; a=16'd54; b=16'd5;
		#20  op=3'd3; a=16'd54; b=16'd5;
		#20  op=3'd4; a=16'd54; b=16'd5;
		#20  op=3'd5; a=16'd54; b=16'd5;
		#20  op=3'd6; a=16'd54; b=16'd5;
		#20  op=3'd7; a=16'd54; b=16'd5;
		#20  $stop;
	end

	initial
	begin
		$dumpfile("alu.vcd");
		$dumpvars;
	end

endmodule