data/full_repos/permissive/156417892/hdl/Execute/MuxRegDest/MuxRegDest.v
data/verilator_xmls/7ffc4dfc-058b-40a6-88e7-97ab308fc674.xml
module MuxRegDest(clk,
                  rt,
                  rd,
                  RegDest,
                  rw);
                  
    input [4:0] rt, rd;
    input RegDest;
    output reg [4:0] rw;
    input clk;

    always @(posedge clk) begin
      rw = (RegDest) ? rd:rt;
    end
endmodule
module MuxRegDest(clk,
                  rt,
                  rd,
                  RegDest,
                  rw);

                  
    input [4:0] rt, rd;
    input RegDest;
    output reg [4:0] rw;
    input clk;

    always @(posedge clk) begin
      rw = (RegDest) ? rd:rt;
    end
endmodule