data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v
1: b"%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:373: Cannot find file containing module: 'SB_LUT4'\n         SB_LUT4 #(.LUT_INIT(16'haea2)) cmb_dinx1( .O(dinx[1]), .I3(INSTR[30]), .I2(INSTR[6]), .I1(INSTR[5]), .I0(INSTR[3]));\n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/195227969/work/cold_store,data/full_repos/permissive/195227969/SB_LUT4\n             data/full_repos/permissive/195227969/work/cold_store,data/full_repos/permissive/195227969/SB_LUT4.v\n             data/full_repos/permissive/195227969/work/cold_store,data/full_repos/permissive/195227969/SB_LUT4.sv\n             SB_LUT4\n             SB_LUT4.v\n             SB_LUT4.sv\n             obj_dir/SB_LUT4\n             obj_dir/SB_LUT4.v\n             obj_dir/SB_LUT4.sv\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:376: Cannot find file containing module: 'SB_LUT4'\n         SB_LUT4 #(.LUT_INIT(16'hdf00)) cmb_dinx7( .O(dinx[7]), .I3(INSTR[14]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));\n         ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:395: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hf020)) checkfunct7h_cmb( .O(checkfunct7h), .I3(opcode[5]), .I2(opcode[4]), .I1(funct3[1]), .I0(funct3[0]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:397: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'h1010)) checkfunct7_cmb( .O(checkfunct7), .I3(1'b0), .I2(checkfunct7h), .I1(opcode[3]), .I0(opcode[2]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:402: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'h2121)) funct3_is_101_or_000_cmb( .O(funct3_is_101_or_000), .I3(1'b0), .I2(funct3[2]), .I1(funct3[1]), .I0(funct3[0]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:404: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'h4000)) funct7_5_dontcare_a_cmb( .O(funct7_5_dontcare_a), .I3(funct3_is_101_or_000), .I2(opcode[5]), .I1(opcode[4]), .I0(opcode[3]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:407: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'h0400)) funct7_5_dontcare_b_cmb( .O(funct7_5_dontcare_b), .I3(funct3_is_101_or_000), .I2(opcode[5]), .I1(opcode[4]), .I0(opcode[3]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:410: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hf8f8)) funct7_5_dontcare_cmb( .O(funct7_5_dontcare), .I3(1'b0), .I2(funct7_5_dontcare_a), .I1(funct7_5_dontcare_b), .I0(funct3[0]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:413: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfefe)) funct7h_cmb( .O(funct7h), .I3(1'b0), .I2(funct7[2]), .I1(funct7[1]), .I0(funct7[0]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:414: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfffe)) mostof_funct7_ne0_cmb( .O(mostof_funct7_ne0), .I3(funct7h), .I2(funct7[6]), .I1(funct7[4]), .I0(funct7[3]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:418: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'h1000)) check_rs1_rd_cmb( .O(check_rs1_rd), .I3(opcode[5]), .I2(opcode[4]), .I1(funct3[1]), .I0(funct3[0]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:426: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfffe)) rs1_ne_x0000_cmb( .O(rs1_ne_x0000), .I3(INSTR[18]), .I2(INSTR[17]), .I1(INSTR[16]), .I0(INSTR[15]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:427: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfffe)) rd_ne_x0000_cmb(  .O(rd_ne_x0000),  .I3(INSTR[10]), .I2(INSTR[9]),  .I1(INSTR[8]),  .I0(INSTR[7]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:428: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'heeee)) instr_11_or_instr_19_cmb( .O(instr_11_or_instr_19), .I3(1'b0), .I2(1'b0), .I1(INSTR[11]), .I0(INSTR[19]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:429: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfe00)) illegal_rs1_rd_cmb( .O(illegal_rs1_rd), .I3(check_rs1_rd), .I2(instr_11_or_instr_19), .I1(rs1_ne_x0000), .I0(rd_ne_x0000));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:433: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hf200)) illegal_funct7_cmb( .O(illegal_funct7), .I3(checkfunct7), .I2(mostof_funct7_ne0), .I1(funct7_5_dontcare), .I0(funct7[5]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:435: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hcec2)) illegal_a_cmb( .O(illegal_a), .I3(INSTR[5]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:436: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'he4ff)) illegal_b_cmb( .O(illegal_b), .I3(INSTR[5]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:438: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfff7)) illegal_c_cmb( .O(illegal_c), .I3(illegal_rs1_rd), .I2(illegal_funct7), .I1(INSTR[1]), .I0(INSTR[0]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:439: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hffca)) illegal_cmb(.O(illegal), .I3(illegal_c), .I2(INSTR[6]), .I1(illegal_b), .I0(illegal_a));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:442: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfe00)) cmb_bbb(.O(illegal_or_qualint_or_RST_I_AND_corerunning), .I3(corerunning), .I2(qualint), .I1(illegal), .I0(RST_I));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:445: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'h4444)) l_sa32_nsa15(.O(sa32_nsa15), .I3(1'b0), .I2(1'b0), .I1(sa32), .I0(sa15));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:446: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_a_cmb( .O(takebranch_a), .I3(Adr0Mustbe0), .I2(B[0]), .I1(Adr1Mustbe0), .I0(B[1]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:447: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_b_cmb( .O(takebranch_b), .I3(use_brcond), .I2(is_brcond), .I1(sa32_nsa15), .I0(B[31]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:450: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfdfd)) usedinx_or_RST_I_cmb( .O(usedinx_or_RST_I), .I3(1'b0), .I2(RST_I), .I1(sa28), .I0(corerunning));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:451: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfffe)) maybranch_cmb( .O(maybranch), .I3(Adr0Mustbe0), .I2(Adr1Mustbe0), .I1(use_brcond), .I0(sa32_nsa15));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:454: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'h0f00)) dinx0_and_legal_cmb( .O(dinx0_and_legal), .I3(dinx[0]), .I2(illegal), .I1(1'b0), .I0(1'b0));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:455: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0b_cmb( .O(minx0b), .I3(maybranch), .I2(takebranch_a), .I1(takebranch_b), .I0(rinx[0]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:456: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0a_cmb( .O(minx0a), .I3(usedinx_or_RST_I), .I2(qualint), .I1(dinx0_and_legal), .I0(minx0b));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:457: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfe00)) minx_cmb0( .O(minx[0]), .I3(corerunning), .I2(RST_I), .I1(buserror), .I0(minx0a));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:461: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'h0e00)) minx_cmb1h(.O(minx1h), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(dinx1_and_corerunning));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:462: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hccca)) minx_cmb1(.O(minx[1]), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(minx1h), .I0(rinx[1]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:465: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb2( .O(minx[2]), .I3(usedinx_or_RST_I), .I2(dinx[2]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[2]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:466: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb3( .O(minx[3]), .I3(usedinx_or_RST_I), .I2(dinx[3]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[3]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:467: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb4( .O(minx[4]), .I3(usedinx_or_RST_I), .I2(dinx[4]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[4]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:468: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb5( .O(minx[5]), .I3(usedinx_or_RST_I), .I2(dinx[5]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[5]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:469: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb6( .O(minx[6]), .I3(usedinx_or_RST_I), .I2(dinx[6]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[6]));\n            ^~~~~~~\n%Error: data/full_repos/permissive/195227969/work/cold_store/m_ucodepc_attempt.v:470: Cannot find file containing module: 'SB_LUT4'\n            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb7( .O(minx[7]), .I3(usedinx_or_RST_I), .I2(dinx[7]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[7]));\n            ^~~~~~~\n%Error: Exiting due to 38 error(s)\n"
module m_ucodepc
  # ( parameter HIGHLEVEL = 0, LAZY_DECODE = 0 )
  (
   input        corerunning,
   input [7:0]  rinx,
   input        sa28,sa29,sa30,sa37,
   input        sa32,sa15,
   input        qualint,
   input        is_brcond,
   input [31:0] INSTR,
   input [31:0] B,
   input        RST_I,
   input        buserror,
   output [7:0] minx,
   output       ucodepc_killwarnings
   );
   wire [7:0]   dinx;
   wire         usedinx, maybranch, takebranch;
   wire         Adr0Mustbe0 = sa29;
   wire         Adr1Mustbe0 = sa30;
   wire         use_brcond  = sa37;

   wire         illegal;

                
`ifdef verilator
   function [1:0] get_branchvariables;

      get_branchvariables = {is_brcond,use_brcond};
   endfunction
   function [0:0] get_usedinx;

      get_usedinx = usedinx;
   endfunction
   function [5:0] get_ucodepcinfo;

      get_ucodepcinfo = {buserror,usedinx,qualint,illegal,maybranch,takebranch};
   endfunction
   function [7:0] get_dinx;

      get_dinx = dinx;
   endfunction
`endif

   generate
      if ( HIGHLEVEL ) begin 
         

         
         assign usedinx   = sa28 | !corerunning;
         assign maybranch = Adr0Mustbe0 | Adr1Mustbe0 | use_brcond | (sa32 & ~sa15);
                  

         assign dinx[0]   = INSTR[2];
         assign dinx[1]   = ((~INSTR[6]&INSTR[5])&INSTR[30]) | ((~(~INSTR[6]&INSTR[5]))&INSTR[3]);
         assign dinx[4:2] = INSTR[6:4];


         assign dinx[6:5] = INSTR[13:12];

         assign dinx[7]   = INSTR[14] & (INSTR[4:2] != 3'b101);



         if ( LAZY_DECODE == 0 ) begin





            wire       illegal_funct7_or_illegal_rs1_rd;


            
            wire [6:0] funct7 = INSTR[31:25];
            wire [2:0] funct3 = INSTR[14:12];

            wire [6:0] opcode = INSTR[6:0];


            wire       checkfunct7 = 
                       (opcode[6:2] == 5'b01100) ||
                       (opcode[6:2] == 5'b00100 && funct3[1:0] == 2'b01 );
            wire       funct7_5_dontcare =
                       (opcode[6:2] == 5'b00100 && funct3 == 3'b101) ||
                       (opcode[6:2] == 5'b01100 && (funct3 == 3'b101 || funct3 == 3'b000));






            wire       mostof_funct7_ne0 = {funct7[6],funct7[4:0]} != 6'h0;



            wire       check_rs1_rd = (opcode[6:2] == 5'b11100) && (funct3[1:0] == 2'b00);

            wire       rs1_ne_zero = INSTR[19:15] != 5'h0;
            wire       rd_ne_zero  = INSTR[11:7] != 5'h0;
            wire       illegal_rs1_rd = check_rs1_rd & (rs1_ne_zero | rd_ne_zero);
            
            assign illegal_funct7_or_illegal_rs1_rd
              = (checkfunct7 & mostof_funct7_ne0) |
                (checkfunct7 & ~funct7_5_dontcare & funct7[5]) |
                illegal_rs1_rd;
            


            reg        illegal_a, illegal_b;
            always @(INSTR)
              case ( INSTR[5:2] )
                4'b0000 : {illegal_b,illegal_a} = 2'b10;
                4'b0001 : {illegal_b,illegal_a} = 2'b11;
                4'b0010 : {illegal_b,illegal_a} = 2'b10;
                4'b0011 : {illegal_b,illegal_a} = 2'b10;
                4'b0100 : {illegal_b,illegal_a} = 2'b10;
                4'b0101 : {illegal_b,illegal_a} = 2'b10;
                4'b0110 : {illegal_b,illegal_a} = 2'b11;
                4'b0111 : {illegal_b,illegal_a} = 2'b11;
                4'b1000 : {illegal_b,illegal_a} = 2'b00;
                4'b1001 : {illegal_b,illegal_a} = 2'b01;
                4'b1010 : {illegal_b,illegal_a} = 2'b11;
                4'b1011 : {illegal_b,illegal_a} = 2'b01;
                4'b1100 : {illegal_b,illegal_a} = 2'b00;
                4'b1101 : {illegal_b,illegal_a} = 2'b10;
                4'b1110 : {illegal_b,illegal_a} = 2'b11;
                4'b1111 : {illegal_b,illegal_a} = 2'b11;
              endcase
            assign illegal = (~INSTR[6] & illegal_a) | 
                             (INSTR[6] & illegal_b ) | 
                             ~INSTR[1] |
                             ~INSTR[0] |
                             illegal_funct7_or_illegal_rs1_rd;
         
            

            wire       qualint_or_RST_I = qualint | RST_I;
            wire       illegal_or_qualint = (illegal | qualint) & corerunning;
            wire       illegal_or_qualint_or_RST_I = (illegal | qualint | RST_I) & corerunning;
            assign takebranch = 
                                (Adr0Mustbe0 & B[0]) |
                                (Adr1Mustbe0 & B[1]) |                
                                (use_brcond & is_brcond) |
                                (sa32 & ~sa15 & B[31] );
            wire       usedinx_or_RST_I = usedinx | RST_I;
            assign minx[7:2] = {6{corerunning}} & (usedinx_or_RST_I ? (dinx[7:2] | {6{illegal_or_qualint_or_RST_I}}) : rinx[7:2]);
            assign minx[1]   = corerunning & (usedinx_or_RST_I ? ( (dinx[1] | illegal_or_qualint) & ~RST_I)     : rinx[1]);
            assign minx[0]   = corerunning & (buserror | (usedinx_or_RST_I ? (illegal_or_qualint_or_RST_I ? qualint_or_RST_I : dinx[0]) : (maybranch ? takebranch : rinx[0])));
            
            assign ucodepc_killwarnings = INSTR[31] | &INSTR[29:15] | &INSTR[11:7] |  &B;
            
            
         end else if ( LAZY_DECODE == 1 ) begin




            

            reg          illegal_a, illegal_b;
            always @(INSTR)
              case ( INSTR[5:2] )
                4'b0000 : {illegal_b,illegal_a} = 2'b10;
                4'b0001 : {illegal_b,illegal_a} = 2'b11;
                4'b0010 : {illegal_b,illegal_a} = 2'b10;
                4'b0011 : {illegal_b,illegal_a} = 2'b10;
                4'b0100 : {illegal_b,illegal_a} = 2'b10;
                4'b0101 : {illegal_b,illegal_a} = 2'b10;
                4'b0110 : {illegal_b,illegal_a} = 2'b11;
                4'b0111 : {illegal_b,illegal_a} = 2'b11;
                4'b1000 : {illegal_b,illegal_a} = 2'b00;
                4'b1001 : {illegal_b,illegal_a} = 2'b01;
                4'b1010 : {illegal_b,illegal_a} = 2'b11;
                4'b1011 : {illegal_b,illegal_a} = 2'b01;
                4'b1100 : {illegal_b,illegal_a} = 2'b00;
                4'b1101 : {illegal_b,illegal_a} = 2'b10;
                4'b1110 : {illegal_b,illegal_a} = 2'b11;
                4'b1111 : {illegal_b,illegal_a} = 2'b11;
              endcase
            assign illegal = (~INSTR[6] & illegal_a) | 
                         (INSTR[6] & illegal_b ) | 
                         ~INSTR[1] |
                         ~INSTR[0];
            
            wire         qualint_or_RST_I = qualint | RST_I;
            wire         illegal_or_qualint_AND_corerunning = (illegal | qualint) & corerunning;
            wire         illegal_or_qualint_or_RST_I_AND_corerunning = (illegal | qualint | RST_I) & corerunning;
            assign takebranch = 
                                (Adr0Mustbe0 & B[0]) |
                                (Adr1Mustbe0 & B[1]) |                
                                (use_brcond & is_brcond) |
                                (sa32 & ~sa15 & B[31] );
            wire         usedinx_or_RST_I = usedinx | RST_I;
            assign minx[7:2] = usedinx_or_RST_I ? (dinx[7:2] | {6{illegal_or_qualint_or_RST_I_AND_corerunning}}) : rinx[7:2];
            assign minx[1]   = corerunning & (usedinx_or_RST_I ? ( (dinx[1] | illegal_or_qualint_AND_corerunning) & ~RST_I)     : rinx[1]);
            assign minx[0]   = corerunning & (buserror | (usedinx_or_RST_I ? (illegal_or_qualint_or_RST_I_AND_corerunning ? qualint_or_RST_I : dinx[0]) : (maybranch ? takebranch : rinx[0])));
            
            assign ucodepc_killwarnings = INSTR[31] | &INSTR[29:15] | &INSTR[11:7] | &B;
            
         end else begin










            
            wire qualint_or_RST_I = qualint | RST_I;
            wire illegal_or_qualint = qualint & corerunning;
            wire illegal_or_qualint_or_RST_I = (qualint | RST_I) & corerunning;
            assign takebranch = (Adr0Mustbe0 & B[0]) |(Adr1Mustbe0 & B[1]) |(use_brcond & is_brcond) | (sa32 & ~sa15 & B[31] );
            wire usedinx_or_RST_I = usedinx | RST_I;
            assign minx[7:2] = usedinx_or_RST_I ? (dinx[7:2] | {6{illegal_or_qualint_or_RST_I}}) : rinx[7:2];
            assign minx[1]   = usedinx_or_RST_I ? ( (dinx[1] | illegal_or_qualint) & ~RST_I)     : rinx[1];
            assign minx[0]   = buserror | (usedinx_or_RST_I ? (illegal_or_qualint_or_RST_I ? qualint_or_RST_I : dinx[0]) : (maybranch ? takebranch : rinx[0]));
            
            assign ucodepc_killwarnings = INSTR[31] | &INSTR[29:15] | &INSTR[11:7] | &INSTR[1:0] | &B;
            assign illegal = 1'b0;
         end                 
         
      end else begin


         

         wire illegal_a, illegal_b;


         

         assign dinx[0]   = INSTR[2];
         SB_LUT4 #(.LUT_INIT(16'haea2)) cmb_dinx1( .O(dinx[1]), .I3(INSTR[30]), .I2(INSTR[6]), .I1(INSTR[5]), .I0(INSTR[3]));
         assign dinx[4:2] = INSTR[6:4];
         assign dinx[6:5] = INSTR[13:12];
         SB_LUT4 #(.LUT_INIT(16'hdf00)) cmb_dinx7( .O(dinx[7]), .I3(INSTR[14]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));
           
                  
         if ( LAZY_DECODE == 0 ) begin
            





            wire       illegal_funct7;
            wire [6:0] funct7 = INSTR[31:25];
            wire [2:0] funct3 = INSTR[14:12];

            wire [6:0] opcode = INSTR[6:0];



            wire       checkfunct7h, checkfunct7;
            SB_LUT4 #(.LUT_INIT(16'hf020)) checkfunct7h_cmb( .O(checkfunct7h), .I3(opcode[5]), .I2(opcode[4]), .I1(funct3[1]), .I0(funct3[0]));

            SB_LUT4 #(.LUT_INIT(16'h1010)) checkfunct7_cmb( .O(checkfunct7), .I3(1'b0), .I2(checkfunct7h), .I1(opcode[3]), .I0(opcode[2]));


            wire       funct3_is_101_or_000,funct7_5_dontcare_a;

            SB_LUT4 #(.LUT_INIT(16'h2121)) funct3_is_101_or_000_cmb( .O(funct3_is_101_or_000), .I3(1'b0), .I2(funct3[2]), .I1(funct3[1]), .I0(funct3[0]));

            SB_LUT4 #(.LUT_INIT(16'h4000)) funct7_5_dontcare_a_cmb( .O(funct7_5_dontcare_a), .I3(funct3_is_101_or_000), .I2(opcode[5]), .I1(opcode[4]), .I0(opcode[3]));
            wire       funct7_5_dontcare_b;

            SB_LUT4 #(.LUT_INIT(16'h0400)) funct7_5_dontcare_b_cmb( .O(funct7_5_dontcare_b), .I3(funct3_is_101_or_000), .I2(opcode[5]), .I1(opcode[4]), .I0(opcode[3]));

            wire       funct7_5_dontcare;
            SB_LUT4 #(.LUT_INIT(16'hf8f8)) funct7_5_dontcare_cmb( .O(funct7_5_dontcare), .I3(1'b0), .I2(funct7_5_dontcare_a), .I1(funct7_5_dontcare_b), .I0(funct3[0]));

            wire       mostof_funct7_ne0,funct7h;
            SB_LUT4 #(.LUT_INIT(16'hfefe)) funct7h_cmb( .O(funct7h), .I3(1'b0), .I2(funct7[2]), .I1(funct7[1]), .I0(funct7[0]));
            SB_LUT4 #(.LUT_INIT(16'hfffe)) mostof_funct7_ne0_cmb( .O(mostof_funct7_ne0), .I3(funct7h), .I2(funct7[6]), .I1(funct7[4]), .I0(funct7[3]));
            

            wire       check_rs1_rd;
            SB_LUT4 #(.LUT_INIT(16'h1000)) check_rs1_rd_cmb( .O(check_rs1_rd), .I3(opcode[5]), .I2(opcode[4]), .I1(funct3[1]), .I0(funct3[0]));




            wire       rs1_ne_x0000, rd_ne_x0000, illegal_rs1_rd;
            wire       instr_11_or_instr_19;
            
            SB_LUT4 #(.LUT_INIT(16'hfffe)) rs1_ne_x0000_cmb( .O(rs1_ne_x0000), .I3(INSTR[18]), .I2(INSTR[17]), .I1(INSTR[16]), .I0(INSTR[15]));
            SB_LUT4 #(.LUT_INIT(16'hfffe)) rd_ne_x0000_cmb(  .O(rd_ne_x0000),  .I3(INSTR[10]), .I2(INSTR[9]),  .I1(INSTR[8]),  .I0(INSTR[7]));
            SB_LUT4 #(.LUT_INIT(16'heeee)) instr_11_or_instr_19_cmb( .O(instr_11_or_instr_19), .I3(1'b0), .I2(1'b0), .I1(INSTR[11]), .I0(INSTR[19]));
            SB_LUT4 #(.LUT_INIT(16'hfe00)) illegal_rs1_rd_cmb( .O(illegal_rs1_rd), .I3(check_rs1_rd), .I2(instr_11_or_instr_19), .I1(rs1_ne_x0000), .I0(rd_ne_x0000));
           
            

            SB_LUT4 #(.LUT_INIT(16'hf200)) illegal_funct7_cmb( .O(illegal_funct7), .I3(checkfunct7), .I2(mostof_funct7_ne0), .I1(funct7_5_dontcare), .I0(funct7[5]));
            
            SB_LUT4 #(.LUT_INIT(16'hcec2)) illegal_a_cmb( .O(illegal_a), .I3(INSTR[5]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));
            SB_LUT4 #(.LUT_INIT(16'he4ff)) illegal_b_cmb( .O(illegal_b), .I3(INSTR[5]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));
            wire illegal_c;
            SB_LUT4 #(.LUT_INIT(16'hfff7)) illegal_c_cmb( .O(illegal_c), .I3(illegal_rs1_rd), .I2(illegal_funct7), .I1(INSTR[1]), .I0(INSTR[0]));
            SB_LUT4 #(.LUT_INIT(16'hffca)) illegal_cmb(.O(illegal), .I3(illegal_c), .I2(INSTR[6]), .I1(illegal_b), .I0(illegal_a));

            wire         illegal_or_qualint_or_RST_I_AND_corerunning;
            SB_LUT4 #(.LUT_INIT(16'hfe00)) cmb_bbb(.O(illegal_or_qualint_or_RST_I_AND_corerunning), .I3(corerunning), .I2(qualint), .I1(illegal), .I0(RST_I));
            wire         sa32_nsa15;
            wire         takebranch_a, takebranch_b;
            SB_LUT4 #(.LUT_INIT(16'h4444)) l_sa32_nsa15(.O(sa32_nsa15), .I3(1'b0), .I2(1'b0), .I1(sa32), .I0(sa15));
            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_a_cmb( .O(takebranch_a), .I3(Adr0Mustbe0), .I2(B[0]), .I1(Adr1Mustbe0), .I0(B[1]));
            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_b_cmb( .O(takebranch_b), .I3(use_brcond), .I2(is_brcond), .I1(sa32_nsa15), .I0(B[31]));

            wire         usedinx_or_RST_I;
            SB_LUT4 #(.LUT_INIT(16'hfdfd)) usedinx_or_RST_I_cmb( .O(usedinx_or_RST_I), .I3(1'b0), .I2(RST_I), .I1(sa28), .I0(corerunning));
            SB_LUT4 #(.LUT_INIT(16'hfffe)) maybranch_cmb( .O(maybranch), .I3(Adr0Mustbe0), .I2(Adr1Mustbe0), .I1(use_brcond), .I0(sa32_nsa15));
            wire         minx0a, minx0b;
            wire         dinx0_and_legal;
            SB_LUT4 #(.LUT_INIT(16'h0f00)) dinx0_and_legal_cmb( .O(dinx0_and_legal), .I3(dinx[0]), .I2(illegal), .I1(1'b0), .I0(1'b0));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0b_cmb( .O(minx0b), .I3(maybranch), .I2(takebranch_a), .I1(takebranch_b), .I0(rinx[0]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0a_cmb( .O(minx0a), .I3(usedinx_or_RST_I), .I2(qualint), .I1(dinx0_and_legal), .I0(minx0b));
            SB_LUT4 #(.LUT_INIT(16'hfe00)) minx_cmb0( .O(minx[0]), .I3(corerunning), .I2(RST_I), .I1(buserror), .I0(minx0a));

            wire         minx1h;
            wire         dinx1_and_corerunning = dinx[1] & corerunning;
            SB_LUT4 #(.LUT_INIT(16'h0e00)) minx_cmb1h(.O(minx1h), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(dinx1_and_corerunning));
            SB_LUT4 #(.LUT_INIT(16'hccca)) minx_cmb1(.O(minx[1]), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(minx1h), .I0(rinx[1]));


            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb2( .O(minx[2]), .I3(usedinx_or_RST_I), .I2(dinx[2]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[2]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb3( .O(minx[3]), .I3(usedinx_or_RST_I), .I2(dinx[3]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[3]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb4( .O(minx[4]), .I3(usedinx_or_RST_I), .I2(dinx[4]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[4]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb5( .O(minx[5]), .I3(usedinx_or_RST_I), .I2(dinx[5]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[5]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb6( .O(minx[6]), .I3(usedinx_or_RST_I), .I2(dinx[6]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[6]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb7( .O(minx[7]), .I3(usedinx_or_RST_I), .I2(dinx[7]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[7]));
                        
            assign ucodepc_killwarnings = INSTR[31] | &INSTR[29:15] | &INSTR[11:7] | &B | &INSTR;

         end else if ( LAZY_DECODE == 1 ) begin




            

            SB_LUT4 #(.LUT_INIT(16'hcec2)) illegal_a_cmb( .O(illegal_a), .I3(INSTR[5]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));
            SB_LUT4 #(.LUT_INIT(16'he4ff)) illegal_b_cmb( .O(illegal_b), .I3(INSTR[5]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));
            wire illegal_c;
            SB_LUT4 #(.LUT_INIT(16'h7777)) illegal_c_cmb( .O(illegal_c), .I3(1'b0), .I2(1'b0), .I1(INSTR[1]), .I0(INSTR[0]));
            SB_LUT4 #(.LUT_INIT(16'hffca)) illegal_cmb(.O(illegal), .I3(illegal_c), .I2(INSTR[6]), .I1(illegal_b), .I0(illegal_a));

            wire         illegal_or_qualint_or_RST_I_AND_corerunning;
            SB_LUT4 #(.LUT_INIT(16'hfe00)) cmb_bbb(.O(illegal_or_qualint_or_RST_I_AND_corerunning), .I3(corerunning), .I2(qualint), .I1(illegal), .I0(RST_I));

         
         


            wire         sa32_nsa15;
            wire         takebranch_a, takebranch_b;
            SB_LUT4 #(.LUT_INIT(16'h4444)) l_sa32_nsa15(.O(sa32_nsa15), .I3(1'b0), .I2(1'b0), .I1(sa32), .I0(sa15));
            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_a_cmb( .O(takebranch_a), .I3(Adr0Mustbe0), .I2(B[0]), .I1(Adr1Mustbe0), .I0(B[1]));
            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_b_cmb( .O(takebranch_b), .I3(use_brcond), .I2(is_brcond), .I1(sa32_nsa15), .I0(B[31]));

            wire         usedinx_or_RST_I;
            SB_LUT4 #(.LUT_INIT(16'hfdfd)) usedinx_or_RST_I_cmb( .O(usedinx_or_RST_I), .I3(1'b0), .I2(RST_I), .I1(sa28), .I0(corerunning));
            SB_LUT4 #(.LUT_INIT(16'hfffe)) maybranch_cmb( .O(maybranch), .I3(Adr0Mustbe0), .I2(Adr1Mustbe0), .I1(use_brcond), .I0(sa32_nsa15));


            wire         minx0a, minx0b;
            wire         dinx0_and_legal;
            SB_LUT4 #(.LUT_INIT(16'h0f00)) dinx0_and_legal_cmb( .O(dinx0_and_legal), .I3(dinx[0]), .I2(illegal), .I1(1'b0), .I0(1'b0));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0b_cmb( .O(minx0b), .I3(maybranch), .I2(takebranch_a), .I1(takebranch_b), .I0(rinx[0]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0a_cmb( .O(minx0a), .I3(usedinx_or_RST_I), .I2(qualint), .I1(dinx0_and_legal), .I0(minx0b));
            SB_LUT4 #(.LUT_INIT(16'hfe00)) minx_cmb0( .O(minx[0]), .I3(corerunning), .I2(RST_I), .I1(buserror), .I0(minx0a));


            wire         minx1h;
            wire         dinx1_and_corerunning = dinx[1] & corerunning;
            SB_LUT4 #(.LUT_INIT(16'h0e00)) minx_cmb1h(.O(minx1h), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(dinx1_and_corerunning));
            SB_LUT4 #(.LUT_INIT(16'hccca)) minx_cmb1(.O(minx[1]), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(minx1h), .I0(rinx[1]));


            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb2( .O(minx[2]), .I3(usedinx_or_RST_I), .I2(dinx[2]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[2]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb3( .O(minx[3]), .I3(usedinx_or_RST_I), .I2(dinx[3]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[3]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb4( .O(minx[4]), .I3(usedinx_or_RST_I), .I2(dinx[4]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[4]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb5( .O(minx[5]), .I3(usedinx_or_RST_I), .I2(dinx[5]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[5]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb6( .O(minx[6]), .I3(usedinx_or_RST_I), .I2(dinx[6]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[6]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb7( .O(minx[7]), .I3(usedinx_or_RST_I), .I2(dinx[7]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[7]));
                        
            assign ucodepc_killwarnings = INSTR[31] | &INSTR[29:15] | &INSTR[11:7] | &B | &INSTR;
            
         end else begin
            




            wire         illegal_or_qualint_or_RST_I_AND_corerunning;

            SB_LUT4 #(.LUT_INIT(16'hfe00)) cmb_bbb(.O(illegal_or_qualint_or_RST_I_AND_corerunning), .I3(corerunning), .I2(qualint), .I1(1'b0), .I0(RST_I));

            wire         sa32_nsa15;
            wire         takebranch_a, takebranch_b;
            SB_LUT4 #(.LUT_INIT(16'h4444)) l_sa32_nsa15(.O(sa32_nsa15), .I3(1'b0), .I2(1'b0), .I1(sa32), .I0(sa15));
            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_a_cmb( .O(takebranch_a), .I3(Adr0Mustbe0), .I2(B[0]), .I1(Adr1Mustbe0), .I0(B[1]));
            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_b_cmb( .O(takebranch_b), .I3(use_brcond), .I2(is_brcond), .I1(sa32_nsa15), .I0(B[31]));

            wire         usedinx_or_RST_I;
            SB_LUT4 #(.LUT_INIT(16'hfdfd)) usedinx_or_RST_I_cmb( .O(usedinx_or_RST_I), .I3(1'b0), .I2(RST_I), .I1(sa28), .I0(corerunning));
            SB_LUT4 #(.LUT_INIT(16'hfffe)) maybranch_cmb( .O(maybranch), .I3(Adr0Mustbe0), .I2(Adr1Mustbe0), .I1(use_brcond), .I0(sa32_nsa15));


            wire         minx0a, minx0b;
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0b_cmb( .O(minx0b), .I3(maybranch), .I2(takebranch_a), .I1(takebranch_b), .I0(rinx[0]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0a_cmb( .O(minx0a), .I3(usedinx_or_RST_I), .I2(qualint), .I1(dinx[0]), .I0(minx0b));
            SB_LUT4 #(.LUT_INIT(16'hfe00)) minx_cmb0( .O(minx[0]), .I3(corerunning), .I2(RST_I), .I1(buserror), .I0(minx0a));


            wire         minx1h;
            wire         dinx1_and_corerunning = dinx[1] & corerunning;
            SB_LUT4 #(.LUT_INIT(16'h0e00)) minx_cmb1h(.O(minx1h), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(dinx1_and_corerunning));
            SB_LUT4 #(.LUT_INIT(16'hccca)) minx_cmb1(.O(minx[1]), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(minx1h), .I0(rinx[1]));


            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb2( .O(minx[2]), .I3(usedinx_or_RST_I), .I2(dinx[2]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[2]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb3( .O(minx[3]), .I3(usedinx_or_RST_I), .I2(dinx[3]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[3]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb4( .O(minx[4]), .I3(usedinx_or_RST_I), .I2(dinx[4]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[4]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb5( .O(minx[5]), .I3(usedinx_or_RST_I), .I2(dinx[5]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[5]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb6( .O(minx[6]), .I3(usedinx_or_RST_I), .I2(dinx[6]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[6]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb7( .O(minx[7]), .I3(usedinx_or_RST_I), .I2(dinx[7]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[7]));
                        
            assign ucodepc_killwarnings = INSTR[31] | &INSTR[29:15] | &INSTR[11:7] | &B | &INSTR;
            assign illegal = 1'b0;          
            
         end


         assign usedinx   = sa28 | !corerunning;
         assign takebranch = (Adr0Mustbe0 & B[0]) | (Adr1Mustbe0 & B[1]) | (use_brcond & is_brcond) | ((sa32 & ~sa15) & B[31] ); 
      end
         
   endgenerate
endmodule
module m_ucodepc
  # ( parameter HIGHLEVEL = 0, LAZY_DECODE = 0 )
  (
   input        corerunning,
   input [7:0]  rinx,
   input        sa28,sa29,sa30,sa37,
   input        sa32,sa15,
   input        qualint,
   input        is_brcond,
   input [31:0] INSTR,
   input [31:0] B,
   input        RST_I,
   input        buserror,
   output [7:0] minx,
   output       ucodepc_killwarnings
   );

   wire [7:0]   dinx;
   wire         usedinx, maybranch, takebranch;
   wire         Adr0Mustbe0 = sa29;
   wire         Adr1Mustbe0 = sa30;
   wire         use_brcond  = sa37;

   wire         illegal;

                
`ifdef verilator
   function [1:0] get_branchvariables;

      get_branchvariables = {is_brcond,use_brcond};
   endfunction
   function [0:0] get_usedinx;

      get_usedinx = usedinx;
   endfunction
   function [5:0] get_ucodepcinfo;

      get_ucodepcinfo = {buserror,usedinx,qualint,illegal,maybranch,takebranch};
   endfunction
   function [7:0] get_dinx;

      get_dinx = dinx;
   endfunction
`endif

   generate
      if ( HIGHLEVEL ) begin 
         

         
         assign usedinx   = sa28 | !corerunning;
         assign maybranch = Adr0Mustbe0 | Adr1Mustbe0 | use_brcond | (sa32 & ~sa15);
                  

         assign dinx[0]   = INSTR[2];
         assign dinx[1]   = ((~INSTR[6]&INSTR[5])&INSTR[30]) | ((~(~INSTR[6]&INSTR[5]))&INSTR[3]);
         assign dinx[4:2] = INSTR[6:4];


         assign dinx[6:5] = INSTR[13:12];

         assign dinx[7]   = INSTR[14] & (INSTR[4:2] != 3'b101);



         if ( LAZY_DECODE == 0 ) begin





            wire       illegal_funct7_or_illegal_rs1_rd;


            
            wire [6:0] funct7 = INSTR[31:25];
            wire [2:0] funct3 = INSTR[14:12];

            wire [6:0] opcode = INSTR[6:0];


            wire       checkfunct7 = 
                       (opcode[6:2] == 5'b01100) ||
                       (opcode[6:2] == 5'b00100 && funct3[1:0] == 2'b01 );
            wire       funct7_5_dontcare =
                       (opcode[6:2] == 5'b00100 && funct3 == 3'b101) ||
                       (opcode[6:2] == 5'b01100 && (funct3 == 3'b101 || funct3 == 3'b000));






            wire       mostof_funct7_ne0 = {funct7[6],funct7[4:0]} != 6'h0;



            wire       check_rs1_rd = (opcode[6:2] == 5'b11100) && (funct3[1:0] == 2'b00);

            wire       rs1_ne_zero = INSTR[19:15] != 5'h0;
            wire       rd_ne_zero  = INSTR[11:7] != 5'h0;
            wire       illegal_rs1_rd = check_rs1_rd & (rs1_ne_zero | rd_ne_zero);
            
            assign illegal_funct7_or_illegal_rs1_rd
              = (checkfunct7 & mostof_funct7_ne0) |
                (checkfunct7 & ~funct7_5_dontcare & funct7[5]) |
                illegal_rs1_rd;
            


            reg        illegal_a, illegal_b;
            always @(INSTR)
              case ( INSTR[5:2] )
                4'b0000 : {illegal_b,illegal_a} = 2'b10;
                4'b0001 : {illegal_b,illegal_a} = 2'b11;
                4'b0010 : {illegal_b,illegal_a} = 2'b10;
                4'b0011 : {illegal_b,illegal_a} = 2'b10;
                4'b0100 : {illegal_b,illegal_a} = 2'b10;
                4'b0101 : {illegal_b,illegal_a} = 2'b10;
                4'b0110 : {illegal_b,illegal_a} = 2'b11;
                4'b0111 : {illegal_b,illegal_a} = 2'b11;
                4'b1000 : {illegal_b,illegal_a} = 2'b00;
                4'b1001 : {illegal_b,illegal_a} = 2'b01;
                4'b1010 : {illegal_b,illegal_a} = 2'b11;
                4'b1011 : {illegal_b,illegal_a} = 2'b01;
                4'b1100 : {illegal_b,illegal_a} = 2'b00;
                4'b1101 : {illegal_b,illegal_a} = 2'b10;
                4'b1110 : {illegal_b,illegal_a} = 2'b11;
                4'b1111 : {illegal_b,illegal_a} = 2'b11;
              endcase
            assign illegal = (~INSTR[6] & illegal_a) | 
                             (INSTR[6] & illegal_b ) | 
                             ~INSTR[1] |
                             ~INSTR[0] |
                             illegal_funct7_or_illegal_rs1_rd;
         
            

            wire       qualint_or_RST_I = qualint | RST_I;
            wire       illegal_or_qualint = (illegal | qualint) & corerunning;
            wire       illegal_or_qualint_or_RST_I = (illegal | qualint | RST_I) & corerunning;
            assign takebranch = 
                                (Adr0Mustbe0 & B[0]) |
                                (Adr1Mustbe0 & B[1]) |                
                                (use_brcond & is_brcond) |
                                (sa32 & ~sa15 & B[31] );
            wire       usedinx_or_RST_I = usedinx | RST_I;
            assign minx[7:2] = {6{corerunning}} & (usedinx_or_RST_I ? (dinx[7:2] | {6{illegal_or_qualint_or_RST_I}}) : rinx[7:2]);
            assign minx[1]   = corerunning & (usedinx_or_RST_I ? ( (dinx[1] | illegal_or_qualint) & ~RST_I)     : rinx[1]);
            assign minx[0]   = corerunning & (buserror | (usedinx_or_RST_I ? (illegal_or_qualint_or_RST_I ? qualint_or_RST_I : dinx[0]) : (maybranch ? takebranch : rinx[0])));
            
            assign ucodepc_killwarnings = INSTR[31] | &INSTR[29:15] | &INSTR[11:7] |  &B;
            
            
         end else if ( LAZY_DECODE == 1 ) begin




            

            reg          illegal_a, illegal_b;
            always @(INSTR)
              case ( INSTR[5:2] )
                4'b0000 : {illegal_b,illegal_a} = 2'b10;
                4'b0001 : {illegal_b,illegal_a} = 2'b11;
                4'b0010 : {illegal_b,illegal_a} = 2'b10;
                4'b0011 : {illegal_b,illegal_a} = 2'b10;
                4'b0100 : {illegal_b,illegal_a} = 2'b10;
                4'b0101 : {illegal_b,illegal_a} = 2'b10;
                4'b0110 : {illegal_b,illegal_a} = 2'b11;
                4'b0111 : {illegal_b,illegal_a} = 2'b11;
                4'b1000 : {illegal_b,illegal_a} = 2'b00;
                4'b1001 : {illegal_b,illegal_a} = 2'b01;
                4'b1010 : {illegal_b,illegal_a} = 2'b11;
                4'b1011 : {illegal_b,illegal_a} = 2'b01;
                4'b1100 : {illegal_b,illegal_a} = 2'b00;
                4'b1101 : {illegal_b,illegal_a} = 2'b10;
                4'b1110 : {illegal_b,illegal_a} = 2'b11;
                4'b1111 : {illegal_b,illegal_a} = 2'b11;
              endcase
            assign illegal = (~INSTR[6] & illegal_a) | 
                         (INSTR[6] & illegal_b ) | 
                         ~INSTR[1] |
                         ~INSTR[0];
            
            wire         qualint_or_RST_I = qualint | RST_I;
            wire         illegal_or_qualint_AND_corerunning = (illegal | qualint) & corerunning;
            wire         illegal_or_qualint_or_RST_I_AND_corerunning = (illegal | qualint | RST_I) & corerunning;
            assign takebranch = 
                                (Adr0Mustbe0 & B[0]) |
                                (Adr1Mustbe0 & B[1]) |                
                                (use_brcond & is_brcond) |
                                (sa32 & ~sa15 & B[31] );
            wire         usedinx_or_RST_I = usedinx | RST_I;
            assign minx[7:2] = usedinx_or_RST_I ? (dinx[7:2] | {6{illegal_or_qualint_or_RST_I_AND_corerunning}}) : rinx[7:2];
            assign minx[1]   = corerunning & (usedinx_or_RST_I ? ( (dinx[1] | illegal_or_qualint_AND_corerunning) & ~RST_I)     : rinx[1]);
            assign minx[0]   = corerunning & (buserror | (usedinx_or_RST_I ? (illegal_or_qualint_or_RST_I_AND_corerunning ? qualint_or_RST_I : dinx[0]) : (maybranch ? takebranch : rinx[0])));
            
            assign ucodepc_killwarnings = INSTR[31] | &INSTR[29:15] | &INSTR[11:7] | &B;
            
         end else begin










            
            wire qualint_or_RST_I = qualint | RST_I;
            wire illegal_or_qualint = qualint & corerunning;
            wire illegal_or_qualint_or_RST_I = (qualint | RST_I) & corerunning;
            assign takebranch = (Adr0Mustbe0 & B[0]) |(Adr1Mustbe0 & B[1]) |(use_brcond & is_brcond) | (sa32 & ~sa15 & B[31] );
            wire usedinx_or_RST_I = usedinx | RST_I;
            assign minx[7:2] = usedinx_or_RST_I ? (dinx[7:2] | {6{illegal_or_qualint_or_RST_I}}) : rinx[7:2];
            assign minx[1]   = usedinx_or_RST_I ? ( (dinx[1] | illegal_or_qualint) & ~RST_I)     : rinx[1];
            assign minx[0]   = buserror | (usedinx_or_RST_I ? (illegal_or_qualint_or_RST_I ? qualint_or_RST_I : dinx[0]) : (maybranch ? takebranch : rinx[0]));
            
            assign ucodepc_killwarnings = INSTR[31] | &INSTR[29:15] | &INSTR[11:7] | &INSTR[1:0] | &B;
            assign illegal = 1'b0;
         end                 
         
      end else begin


         

         wire illegal_a, illegal_b;


         

         assign dinx[0]   = INSTR[2];
         SB_LUT4 #(.LUT_INIT(16'haea2)) cmb_dinx1( .O(dinx[1]), .I3(INSTR[30]), .I2(INSTR[6]), .I1(INSTR[5]), .I0(INSTR[3]));
         assign dinx[4:2] = INSTR[6:4];
         assign dinx[6:5] = INSTR[13:12];
         SB_LUT4 #(.LUT_INIT(16'hdf00)) cmb_dinx7( .O(dinx[7]), .I3(INSTR[14]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));
           
                  
         if ( LAZY_DECODE == 0 ) begin
            





            wire       illegal_funct7;
            wire [6:0] funct7 = INSTR[31:25];
            wire [2:0] funct3 = INSTR[14:12];

            wire [6:0] opcode = INSTR[6:0];



            wire       checkfunct7h, checkfunct7;
            SB_LUT4 #(.LUT_INIT(16'hf020)) checkfunct7h_cmb( .O(checkfunct7h), .I3(opcode[5]), .I2(opcode[4]), .I1(funct3[1]), .I0(funct3[0]));

            SB_LUT4 #(.LUT_INIT(16'h1010)) checkfunct7_cmb( .O(checkfunct7), .I3(1'b0), .I2(checkfunct7h), .I1(opcode[3]), .I0(opcode[2]));


            wire       funct3_is_101_or_000,funct7_5_dontcare_a;

            SB_LUT4 #(.LUT_INIT(16'h2121)) funct3_is_101_or_000_cmb( .O(funct3_is_101_or_000), .I3(1'b0), .I2(funct3[2]), .I1(funct3[1]), .I0(funct3[0]));

            SB_LUT4 #(.LUT_INIT(16'h4000)) funct7_5_dontcare_a_cmb( .O(funct7_5_dontcare_a), .I3(funct3_is_101_or_000), .I2(opcode[5]), .I1(opcode[4]), .I0(opcode[3]));
            wire       funct7_5_dontcare_b;

            SB_LUT4 #(.LUT_INIT(16'h0400)) funct7_5_dontcare_b_cmb( .O(funct7_5_dontcare_b), .I3(funct3_is_101_or_000), .I2(opcode[5]), .I1(opcode[4]), .I0(opcode[3]));

            wire       funct7_5_dontcare;
            SB_LUT4 #(.LUT_INIT(16'hf8f8)) funct7_5_dontcare_cmb( .O(funct7_5_dontcare), .I3(1'b0), .I2(funct7_5_dontcare_a), .I1(funct7_5_dontcare_b), .I0(funct3[0]));

            wire       mostof_funct7_ne0,funct7h;
            SB_LUT4 #(.LUT_INIT(16'hfefe)) funct7h_cmb( .O(funct7h), .I3(1'b0), .I2(funct7[2]), .I1(funct7[1]), .I0(funct7[0]));
            SB_LUT4 #(.LUT_INIT(16'hfffe)) mostof_funct7_ne0_cmb( .O(mostof_funct7_ne0), .I3(funct7h), .I2(funct7[6]), .I1(funct7[4]), .I0(funct7[3]));
            

            wire       check_rs1_rd;
            SB_LUT4 #(.LUT_INIT(16'h1000)) check_rs1_rd_cmb( .O(check_rs1_rd), .I3(opcode[5]), .I2(opcode[4]), .I1(funct3[1]), .I0(funct3[0]));




            wire       rs1_ne_x0000, rd_ne_x0000, illegal_rs1_rd;
            wire       instr_11_or_instr_19;
            
            SB_LUT4 #(.LUT_INIT(16'hfffe)) rs1_ne_x0000_cmb( .O(rs1_ne_x0000), .I3(INSTR[18]), .I2(INSTR[17]), .I1(INSTR[16]), .I0(INSTR[15]));
            SB_LUT4 #(.LUT_INIT(16'hfffe)) rd_ne_x0000_cmb(  .O(rd_ne_x0000),  .I3(INSTR[10]), .I2(INSTR[9]),  .I1(INSTR[8]),  .I0(INSTR[7]));
            SB_LUT4 #(.LUT_INIT(16'heeee)) instr_11_or_instr_19_cmb( .O(instr_11_or_instr_19), .I3(1'b0), .I2(1'b0), .I1(INSTR[11]), .I0(INSTR[19]));
            SB_LUT4 #(.LUT_INIT(16'hfe00)) illegal_rs1_rd_cmb( .O(illegal_rs1_rd), .I3(check_rs1_rd), .I2(instr_11_or_instr_19), .I1(rs1_ne_x0000), .I0(rd_ne_x0000));
           
            

            SB_LUT4 #(.LUT_INIT(16'hf200)) illegal_funct7_cmb( .O(illegal_funct7), .I3(checkfunct7), .I2(mostof_funct7_ne0), .I1(funct7_5_dontcare), .I0(funct7[5]));
            
            SB_LUT4 #(.LUT_INIT(16'hcec2)) illegal_a_cmb( .O(illegal_a), .I3(INSTR[5]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));
            SB_LUT4 #(.LUT_INIT(16'he4ff)) illegal_b_cmb( .O(illegal_b), .I3(INSTR[5]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));
            wire illegal_c;
            SB_LUT4 #(.LUT_INIT(16'hfff7)) illegal_c_cmb( .O(illegal_c), .I3(illegal_rs1_rd), .I2(illegal_funct7), .I1(INSTR[1]), .I0(INSTR[0]));
            SB_LUT4 #(.LUT_INIT(16'hffca)) illegal_cmb(.O(illegal), .I3(illegal_c), .I2(INSTR[6]), .I1(illegal_b), .I0(illegal_a));

            wire         illegal_or_qualint_or_RST_I_AND_corerunning;
            SB_LUT4 #(.LUT_INIT(16'hfe00)) cmb_bbb(.O(illegal_or_qualint_or_RST_I_AND_corerunning), .I3(corerunning), .I2(qualint), .I1(illegal), .I0(RST_I));
            wire         sa32_nsa15;
            wire         takebranch_a, takebranch_b;
            SB_LUT4 #(.LUT_INIT(16'h4444)) l_sa32_nsa15(.O(sa32_nsa15), .I3(1'b0), .I2(1'b0), .I1(sa32), .I0(sa15));
            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_a_cmb( .O(takebranch_a), .I3(Adr0Mustbe0), .I2(B[0]), .I1(Adr1Mustbe0), .I0(B[1]));
            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_b_cmb( .O(takebranch_b), .I3(use_brcond), .I2(is_brcond), .I1(sa32_nsa15), .I0(B[31]));

            wire         usedinx_or_RST_I;
            SB_LUT4 #(.LUT_INIT(16'hfdfd)) usedinx_or_RST_I_cmb( .O(usedinx_or_RST_I), .I3(1'b0), .I2(RST_I), .I1(sa28), .I0(corerunning));
            SB_LUT4 #(.LUT_INIT(16'hfffe)) maybranch_cmb( .O(maybranch), .I3(Adr0Mustbe0), .I2(Adr1Mustbe0), .I1(use_brcond), .I0(sa32_nsa15));
            wire         minx0a, minx0b;
            wire         dinx0_and_legal;
            SB_LUT4 #(.LUT_INIT(16'h0f00)) dinx0_and_legal_cmb( .O(dinx0_and_legal), .I3(dinx[0]), .I2(illegal), .I1(1'b0), .I0(1'b0));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0b_cmb( .O(minx0b), .I3(maybranch), .I2(takebranch_a), .I1(takebranch_b), .I0(rinx[0]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0a_cmb( .O(minx0a), .I3(usedinx_or_RST_I), .I2(qualint), .I1(dinx0_and_legal), .I0(minx0b));
            SB_LUT4 #(.LUT_INIT(16'hfe00)) minx_cmb0( .O(minx[0]), .I3(corerunning), .I2(RST_I), .I1(buserror), .I0(minx0a));

            wire         minx1h;
            wire         dinx1_and_corerunning = dinx[1] & corerunning;
            SB_LUT4 #(.LUT_INIT(16'h0e00)) minx_cmb1h(.O(minx1h), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(dinx1_and_corerunning));
            SB_LUT4 #(.LUT_INIT(16'hccca)) minx_cmb1(.O(minx[1]), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(minx1h), .I0(rinx[1]));


            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb2( .O(minx[2]), .I3(usedinx_or_RST_I), .I2(dinx[2]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[2]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb3( .O(minx[3]), .I3(usedinx_or_RST_I), .I2(dinx[3]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[3]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb4( .O(minx[4]), .I3(usedinx_or_RST_I), .I2(dinx[4]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[4]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb5( .O(minx[5]), .I3(usedinx_or_RST_I), .I2(dinx[5]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[5]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb6( .O(minx[6]), .I3(usedinx_or_RST_I), .I2(dinx[6]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[6]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb7( .O(minx[7]), .I3(usedinx_or_RST_I), .I2(dinx[7]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[7]));
                        
            assign ucodepc_killwarnings = INSTR[31] | &INSTR[29:15] | &INSTR[11:7] | &B | &INSTR;

         end else if ( LAZY_DECODE == 1 ) begin




            

            SB_LUT4 #(.LUT_INIT(16'hcec2)) illegal_a_cmb( .O(illegal_a), .I3(INSTR[5]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));
            SB_LUT4 #(.LUT_INIT(16'he4ff)) illegal_b_cmb( .O(illegal_b), .I3(INSTR[5]), .I2(INSTR[4]), .I1(INSTR[3]), .I0(INSTR[2]));
            wire illegal_c;
            SB_LUT4 #(.LUT_INIT(16'h7777)) illegal_c_cmb( .O(illegal_c), .I3(1'b0), .I2(1'b0), .I1(INSTR[1]), .I0(INSTR[0]));
            SB_LUT4 #(.LUT_INIT(16'hffca)) illegal_cmb(.O(illegal), .I3(illegal_c), .I2(INSTR[6]), .I1(illegal_b), .I0(illegal_a));

            wire         illegal_or_qualint_or_RST_I_AND_corerunning;
            SB_LUT4 #(.LUT_INIT(16'hfe00)) cmb_bbb(.O(illegal_or_qualint_or_RST_I_AND_corerunning), .I3(corerunning), .I2(qualint), .I1(illegal), .I0(RST_I));

         
         


            wire         sa32_nsa15;
            wire         takebranch_a, takebranch_b;
            SB_LUT4 #(.LUT_INIT(16'h4444)) l_sa32_nsa15(.O(sa32_nsa15), .I3(1'b0), .I2(1'b0), .I1(sa32), .I0(sa15));
            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_a_cmb( .O(takebranch_a), .I3(Adr0Mustbe0), .I2(B[0]), .I1(Adr1Mustbe0), .I0(B[1]));
            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_b_cmb( .O(takebranch_b), .I3(use_brcond), .I2(is_brcond), .I1(sa32_nsa15), .I0(B[31]));

            wire         usedinx_or_RST_I;
            SB_LUT4 #(.LUT_INIT(16'hfdfd)) usedinx_or_RST_I_cmb( .O(usedinx_or_RST_I), .I3(1'b0), .I2(RST_I), .I1(sa28), .I0(corerunning));
            SB_LUT4 #(.LUT_INIT(16'hfffe)) maybranch_cmb( .O(maybranch), .I3(Adr0Mustbe0), .I2(Adr1Mustbe0), .I1(use_brcond), .I0(sa32_nsa15));


            wire         minx0a, minx0b;
            wire         dinx0_and_legal;
            SB_LUT4 #(.LUT_INIT(16'h0f00)) dinx0_and_legal_cmb( .O(dinx0_and_legal), .I3(dinx[0]), .I2(illegal), .I1(1'b0), .I0(1'b0));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0b_cmb( .O(minx0b), .I3(maybranch), .I2(takebranch_a), .I1(takebranch_b), .I0(rinx[0]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0a_cmb( .O(minx0a), .I3(usedinx_or_RST_I), .I2(qualint), .I1(dinx0_and_legal), .I0(minx0b));
            SB_LUT4 #(.LUT_INIT(16'hfe00)) minx_cmb0( .O(minx[0]), .I3(corerunning), .I2(RST_I), .I1(buserror), .I0(minx0a));


            wire         minx1h;
            wire         dinx1_and_corerunning = dinx[1] & corerunning;
            SB_LUT4 #(.LUT_INIT(16'h0e00)) minx_cmb1h(.O(minx1h), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(dinx1_and_corerunning));
            SB_LUT4 #(.LUT_INIT(16'hccca)) minx_cmb1(.O(minx[1]), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(minx1h), .I0(rinx[1]));


            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb2( .O(minx[2]), .I3(usedinx_or_RST_I), .I2(dinx[2]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[2]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb3( .O(minx[3]), .I3(usedinx_or_RST_I), .I2(dinx[3]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[3]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb4( .O(minx[4]), .I3(usedinx_or_RST_I), .I2(dinx[4]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[4]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb5( .O(minx[5]), .I3(usedinx_or_RST_I), .I2(dinx[5]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[5]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb6( .O(minx[6]), .I3(usedinx_or_RST_I), .I2(dinx[6]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[6]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb7( .O(minx[7]), .I3(usedinx_or_RST_I), .I2(dinx[7]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[7]));
                        
            assign ucodepc_killwarnings = INSTR[31] | &INSTR[29:15] | &INSTR[11:7] | &B | &INSTR;
            
         end else begin
            




            wire         illegal_or_qualint_or_RST_I_AND_corerunning;

            SB_LUT4 #(.LUT_INIT(16'hfe00)) cmb_bbb(.O(illegal_or_qualint_or_RST_I_AND_corerunning), .I3(corerunning), .I2(qualint), .I1(1'b0), .I0(RST_I));

            wire         sa32_nsa15;
            wire         takebranch_a, takebranch_b;
            SB_LUT4 #(.LUT_INIT(16'h4444)) l_sa32_nsa15(.O(sa32_nsa15), .I3(1'b0), .I2(1'b0), .I1(sa32), .I0(sa15));
            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_a_cmb( .O(takebranch_a), .I3(Adr0Mustbe0), .I2(B[0]), .I1(Adr1Mustbe0), .I0(B[1]));
            SB_LUT4 #(.LUT_INIT(16'hf888)) takebranch_b_cmb( .O(takebranch_b), .I3(use_brcond), .I2(is_brcond), .I1(sa32_nsa15), .I0(B[31]));

            wire         usedinx_or_RST_I;
            SB_LUT4 #(.LUT_INIT(16'hfdfd)) usedinx_or_RST_I_cmb( .O(usedinx_or_RST_I), .I3(1'b0), .I2(RST_I), .I1(sa28), .I0(corerunning));
            SB_LUT4 #(.LUT_INIT(16'hfffe)) maybranch_cmb( .O(maybranch), .I3(Adr0Mustbe0), .I2(Adr1Mustbe0), .I1(use_brcond), .I0(sa32_nsa15));


            wire         minx0a, minx0b;
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0b_cmb( .O(minx0b), .I3(maybranch), .I2(takebranch_a), .I1(takebranch_b), .I0(rinx[0]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx0a_cmb( .O(minx0a), .I3(usedinx_or_RST_I), .I2(qualint), .I1(dinx[0]), .I0(minx0b));
            SB_LUT4 #(.LUT_INIT(16'hfe00)) minx_cmb0( .O(minx[0]), .I3(corerunning), .I2(RST_I), .I1(buserror), .I0(minx0a));


            wire         minx1h;
            wire         dinx1_and_corerunning = dinx[1] & corerunning;
            SB_LUT4 #(.LUT_INIT(16'h0e00)) minx_cmb1h(.O(minx1h), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(dinx1_and_corerunning));
            SB_LUT4 #(.LUT_INIT(16'hccca)) minx_cmb1(.O(minx[1]), .I3(usedinx_or_RST_I), .I2(RST_I), .I1(minx1h), .I0(rinx[1]));


            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb2( .O(minx[2]), .I3(usedinx_or_RST_I), .I2(dinx[2]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[2]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb3( .O(minx[3]), .I3(usedinx_or_RST_I), .I2(dinx[3]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[3]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb4( .O(minx[4]), .I3(usedinx_or_RST_I), .I2(dinx[4]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[4]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb5( .O(minx[5]), .I3(usedinx_or_RST_I), .I2(dinx[5]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[5]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb6( .O(minx[6]), .I3(usedinx_or_RST_I), .I2(dinx[6]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[6]));
            SB_LUT4 #(.LUT_INIT(16'hfcaa)) minx_cmb7( .O(minx[7]), .I3(usedinx_or_RST_I), .I2(dinx[7]), .I1(illegal_or_qualint_or_RST_I_AND_corerunning), .I0(rinx[7]));
                        
            assign ucodepc_killwarnings = INSTR[31] | &INSTR[29:15] | &INSTR[11:7] | &B | &INSTR;
            assign illegal = 1'b0;          
            
         end


         assign usedinx   = sa28 | !corerunning;
         assign takebranch = (Adr0Mustbe0 & B[0]) | (Adr1Mustbe0 & B[1]) | (use_brcond & is_brcond) | ((sa32 & ~sa15) & B[31] ); 
      end
         
   endgenerate
endmodule