data/full_repos/permissive/174783592/Adder_PL/sum24bitTB.sv
 line:46: before: "$"
1: b'%Error: data/full_repos/permissive/174783592/Adder_PL/sum24bitTB.sv:43: Unsupported or unknown PLI call: $monitor\n  $monitor ("a=%b\\nb=%b \\n kpgIn=%b sum=%b",a,b,s1.kpgIn[24],sum);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174783592/Adder_PL/sum24bitTB.sv:46: Unsupported: Ignoring delay on this delayed statement.\n #20 $display ("kpgIn[%d]=%b",i,s1.wl1[i]);\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sum24bitTB();
	reg [23:0] a;
	reg    [23:0] b;
	reg [1:0] kIn;
       	integer i;
	wire [24:0] sum ;

	
	sum24bit s1(a,b,kIn,  sum);
	initial
	begin
		a <= {{4{5'b10001}},4'b0101};
		b <= {{4{5'b01011}},4'b1011};
		kIn <= 2'b00;

	end
	initial begin
		$monitor ("a=%b\nb=%b \n kpgIn=%b sum=%b",a,b,s1.kpgIn[24],sum);
	for(i=0;i<23;i=i+1) 
		begin
	#20	$display ("kpgIn[%d]=%b",i,s1.wl1[i]);

		end
	end	

endmodule
module sum24bitTB();

	reg [23:0] a;
	reg    [23:0] b;
	reg [1:0] kIn;
       	integer i;
	wire [24:0] sum ;

	
	sum24bit s1(a,b,kIn,  sum);
	initial
	begin
		a <= {{4{5'b10001}},4'b0101};
		b <= {{4{5'b01011}},4'b1011};
		kIn <= 2'b00;

	end
	initial begin
		$monitor ("a=%b\nb=%b \n kpgIn=%b sum=%b",a,b,s1.kpgIn[24],sum);
	for(i=0;i<23;i=i+1) 
		begin
	#20	$display ("kpgIn[%d]=%b",i,s1.wl1[i]);

		end
	end	

endmodule