data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/2014_q4a.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/2014_q4a.v:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out1'\n                                                                                                                           : ... In instance top_module\n                out1 = Q;\n                ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/2014_q4a.v:13: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out1'\n                                                                                                                           : ... In instance top_module\n                out1 = w;\n                ^~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/2014_q4a.v:18: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q'\n                                                                                                                           : ... In instance top_module\n                Q = out1;\n                ^\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/2014_q4a.v:21: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q'\n                                                                                                                           : ... In instance top_module\n                Q = R;\n                ^\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    wire out1,out2;
    always @(posedge clk) begin
        case (E)
            1'b0: begin
                out1 = Q;
            end
            1'b1: begin
                out1 = w;
            end
        endcase
        case (L)
            1'b0: begin
                Q = out1;
            end
            1'b1: begin
                Q = R;
            end
        endcase
    end
endmodule
module top_module (
    input clk,
    input w, R, E, L,
    output Q
);

    wire out1,out2;
    always @(posedge clk) begin
        case (E)
            1'b0: begin
                out1 = Q;
            end
            1'b1: begin
                out1 = w;
            end
        endcase
        case (L)
            1'b0: begin
                Q = out1;
            end
            1'b1: begin
                Q = R;
            end
        endcase
    end
endmodule