data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sources_1/new/blink.v
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data/verilator_xmls/bc39ccd1-2481-49f6-927b-16785f42ef59.xml
module blink#(parameter DVSR = 10000_0000 - 1)
    (
    input clk,reset,
    input en,
    output blink
    );
    
    reg [29:0] ms_reg;
    wire [29:0] ms_next;
    reg blink_reg;
    reg blink_next;
    

    always@(posedge clk) begin
        ms_reg <= ms_next;
        blink_reg <= blink_next;
    end
    

    assign ms_next = (reset||(ms_reg == DVSR && en)) ? 0 :
                                                (en) ? ms_reg + 1 :
                                                       ms_reg;
    

    always@(*) begin
        if(reset||~en) begin
            blink_next = 1'b0;
        end else if(en && (ms_reg == DVSR)) begin
            blink_next = ~blink_reg;
        end
    end
    
    assign blink = blink_reg;
endmodule
module blink#(parameter DVSR = 10000_0000 - 1)
    (
    input clk,reset,
    input en,
    output blink
    );

    
    reg [29:0] ms_reg;
    wire [29:0] ms_next;
    reg blink_reg;
    reg blink_next;
    

    always@(posedge clk) begin
        ms_reg <= ms_next;
        blink_reg <= blink_next;
    end
    

    assign ms_next = (reset||(ms_reg == DVSR && en)) ? 0 :
                                                (en) ? ms_reg + 1 :
                                                       ms_reg;
    

    always@(*) begin
        if(reset||~en) begin
            blink_next = 1'b0;
        end else if(en && (ms_reg == DVSR)) begin
            blink_next = ~blink_reg;
        end
    end
    
    assign blink = blink_reg;
endmodule