data/full_repos/permissive/220281533/control_unit.v
data/verilator_xmls/99721ac4-e3c6-4669-a01a-ed78d1df9e80.xml
module control_unit(
	output reg RegRead,
				  RegWrite,
				  MemRead,
				  MemWrite,
				  RegDst,
				  Branch,
	input [5:0] opcode, funct
);
	
	always @(opcode, funct) begin
	

		MemRead  = 1'b0;
		MemWrite = 1'b0;
		RegWrite = 1'b0;
		RegRead  = 1'b0;
		RegDst   = 1'b0;
		Branch   = 1'b0;
		

		if(opcode == 6'h0) begin
			RegDst = 1'b1;
			RegRead = 1'b1;

			if(funct != 6'h08) begin
				RegWrite = 1'b1;
			end
		end

		if(opcode != 6'b010101) begin
			RegRead = 1'b1;
		end


		if(opcode != 6'h0 & opcode != 6'h4 & opcode != 6'h5 & opcode != 6'h28 & opcode != 6'h29 & opcode != 6'h2b) begin
			RegWrite = 1'b1;
			RegDst   = 1'b0;
		end

		if(opcode == 6'h4 | opcode == 6'h5) begin
			Branch   = 1'b1;
		end


		if(opcode != 6'h0 & (opcode == 6'h28 | opcode == 6'h29 | opcode == 6'h2b)) begin
			MemWrite = 1'b1;
			RegRead  = 1'b1;
		end


		if(opcode != 6'h0 & (opcode == 6'h23))begin
			MemRead = 1'b1;
		end



	end
	
	
	
endmodule
module control_unit(
	output reg RegRead,
				  RegWrite,
				  MemRead,
				  MemWrite,
				  RegDst,
				  Branch,
	input [5:0] opcode, funct
);

	
	always @(opcode, funct) begin
	

		MemRead  = 1'b0;
		MemWrite = 1'b0;
		RegWrite = 1'b0;
		RegRead  = 1'b0;
		RegDst   = 1'b0;
		Branch   = 1'b0;
		

		if(opcode == 6'h0) begin
			RegDst = 1'b1;
			RegRead = 1'b1;

			if(funct != 6'h08) begin
				RegWrite = 1'b1;
			end
		end

		if(opcode != 6'b010101) begin
			RegRead = 1'b1;
		end


		if(opcode != 6'h0 & opcode != 6'h4 & opcode != 6'h5 & opcode != 6'h28 & opcode != 6'h29 & opcode != 6'h2b) begin
			RegWrite = 1'b1;
			RegDst   = 1'b0;
		end

		if(opcode == 6'h4 | opcode == 6'h5) begin
			Branch   = 1'b1;
		end


		if(opcode != 6'h0 & (opcode == 6'h28 | opcode == 6'h29 | opcode == 6'h2b)) begin
			MemWrite = 1'b1;
			RegRead  = 1'b1;
		end


		if(opcode != 6'h0 & (opcode == 6'h23))begin
			MemRead = 1'b1;
		end



	end
	
	
	
endmodule