data/full_repos/permissive/109209652/verilog/ov7670.v
1: b'%Warning-WIDTH: data/full_repos/permissive/109209652/verilog/ov7670.v:80: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                        : ... In instance ov7670\n   row_buf_addr <= 10\'d0;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ov7670(
	input				clk_50,
	input				reset,


	output	reg			xclk,
	input 				pclk,

	input				vsync,
	input				href,

	input		[7:0]	data,

	output	reg			cam_rst,
	output	reg			cam_pwdn,


	output	reg	[7:0]	value,
	output	reg	[9:0]	x_addr,
	output	reg	[9:0]	y_addr,

	output	reg	[18:0]	mem_addr,
	output	reg			is_val
);
	reg		[7:0]		pixel_temp;

	reg		[7:0]		row_buf[319:0];
	reg		[8:0]		row_buf_addr;


	always@ (posedge clk_50) begin
		if (reset == 1'b1) begin
			xclk <= 1'b0;
		end
		else begin
			xclk <= ~xclk;
		end
	end


	always@ (posedge clk_50) begin
		if (reset == 1'b1) begin
			cam_rst <= 1'b0;
			cam_pwdn <= 1'b1;
		end
		else begin
			cam_rst <= 1'b1;
			cam_pwdn <= 1'b0;
		end
	end
	
	reg last_href;
	reg	is_y;
	reg	is_wr_row;
	reg	pixel_num;


	always@ (posedge pclk) begin

		if (vsync == 1'b1 && href == 1'b0 && last_href == 1'b0) begin
			x_addr <= 10'b0;
			y_addr <= 10'b0;
			mem_addr <= 19'b0;

			value <= 8'b0;
			is_val <= 1'b0;
			is_y <= 1'b0;
			
			is_wr_row <= 0;
			pixel_num <= 0;
			pixel_temp <= 0;
			row_buf_addr <= 10'd0;
		end
		

		else begin

			if (href == 1'b1) begin

				if (is_y) begin
					pixel_num <= ~pixel_num;
					if (pixel_num) begin
						if (is_wr_row) begin


							value <= (data >> 4) + (pixel_temp >> 4) + row_buf[row_buf_addr];
							row_buf_addr <= row_buf_addr + 1;
							is_val <= 1'b1;
							
							mem_addr <= mem_addr + 1;
							x_addr <= x_addr + 10'b1;
							y_addr <= y_addr;
						end
						else begin





							row_buf[row_buf_addr] <= (data >> 2) + (pixel_temp >> 2);
							row_buf_addr <= row_buf_addr + 1;
							is_val <= 1'b0;
						end
					end
					else begin
						pixel_temp <= data;
						is_val <= 1'b0;
					end
				end
				else begin
					x_addr <= x_addr;
					y_addr <= y_addr;
					mem_addr <= mem_addr;

					value <= 8'b0;
					is_val <= 1'b0;
				end

				is_y <= ~is_y;
			end

			else begin
				value <= 8'b0;
				is_val <= 1'b0;
				is_y <= 1'b0;

				if (last_href == 1'b1) begin
					x_addr <= 10'b0;
					mem_addr <= mem_addr;
					is_wr_row <= ~is_wr_row;
					pixel_num <= 0;
					row_buf_addr <= 0;
					y_addr <= y_addr + 10'b1;
				end
				else begin
					x_addr <= x_addr;
					y_addr <= y_addr;
					mem_addr <= mem_addr;
				end
			end
		end

		last_href <= href;
	end

endmodule
module ov7670(
	input				clk_50,
	input				reset,


	output	reg			xclk,
	input 				pclk,

	input				vsync,
	input				href,

	input		[7:0]	data,

	output	reg			cam_rst,
	output	reg			cam_pwdn,


	output	reg	[7:0]	value,
	output	reg	[9:0]	x_addr,
	output	reg	[9:0]	y_addr,

	output	reg	[18:0]	mem_addr,
	output	reg			is_val
);

	reg		[7:0]		pixel_temp;

	reg		[7:0]		row_buf[319:0];
	reg		[8:0]		row_buf_addr;


	always@ (posedge clk_50) begin
		if (reset == 1'b1) begin
			xclk <= 1'b0;
		end
		else begin
			xclk <= ~xclk;
		end
	end


	always@ (posedge clk_50) begin
		if (reset == 1'b1) begin
			cam_rst <= 1'b0;
			cam_pwdn <= 1'b1;
		end
		else begin
			cam_rst <= 1'b1;
			cam_pwdn <= 1'b0;
		end
	end
	
	reg last_href;
	reg	is_y;
	reg	is_wr_row;
	reg	pixel_num;


	always@ (posedge pclk) begin

		if (vsync == 1'b1 && href == 1'b0 && last_href == 1'b0) begin
			x_addr <= 10'b0;
			y_addr <= 10'b0;
			mem_addr <= 19'b0;

			value <= 8'b0;
			is_val <= 1'b0;
			is_y <= 1'b0;
			
			is_wr_row <= 0;
			pixel_num <= 0;
			pixel_temp <= 0;
			row_buf_addr <= 10'd0;
		end
		

		else begin

			if (href == 1'b1) begin

				if (is_y) begin
					pixel_num <= ~pixel_num;
					if (pixel_num) begin
						if (is_wr_row) begin


							value <= (data >> 4) + (pixel_temp >> 4) + row_buf[row_buf_addr];
							row_buf_addr <= row_buf_addr + 1;
							is_val <= 1'b1;
							
							mem_addr <= mem_addr + 1;
							x_addr <= x_addr + 10'b1;
							y_addr <= y_addr;
						end
						else begin





							row_buf[row_buf_addr] <= (data >> 2) + (pixel_temp >> 2);
							row_buf_addr <= row_buf_addr + 1;
							is_val <= 1'b0;
						end
					end
					else begin
						pixel_temp <= data;
						is_val <= 1'b0;
					end
				end
				else begin
					x_addr <= x_addr;
					y_addr <= y_addr;
					mem_addr <= mem_addr;

					value <= 8'b0;
					is_val <= 1'b0;
				end

				is_y <= ~is_y;
			end

			else begin
				value <= 8'b0;
				is_val <= 1'b0;
				is_y <= 1'b0;

				if (last_href == 1'b1) begin
					x_addr <= 10'b0;
					mem_addr <= mem_addr;
					is_wr_row <= ~is_wr_row;
					pixel_num <= 0;
					row_buf_addr <= 0;
					y_addr <= y_addr + 10'b1;
				end
				else begin
					x_addr <= x_addr;
					y_addr <= y_addr;
					mem_addr <= mem_addr;
				end
			end
		end

		last_href <= href;
	end

endmodule