data/full_repos/permissive/189193559/03/pwm_modulator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/189193559/03/pwm_modulator.v:25: Operator GTE expects 65 bits on the LHS, but LHS\'s VARREF \'cnt_clock\' generates 32 bits.\n                                                                          : ... In instance pwm_modulator\n            if(cnt_clock >= C_FREQ / 100000 - 1) cnt_clock <= 0;\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189193559/03/pwm_modulator.v:29: Operator EQ expects 65 bits on the LHS, but LHS\'s VARREF \'cnt_clock\' generates 32 bits.\n                                                                          : ... In instance pwm_modulator\n    assign is_clk_max = (cnt_clock == C_FREQ / 100000 - 1);\n                                   ^~\n%Error: Exiting due to 2 warning(s)\n'
module pwm_modulator(CLK, RST, VAL, MOUT, C_FREQ);
    input CLK, RST;

    input [7:0] VAL;

   input [64:0] C_FREQ;

    output MOUT;


    reg out_buf;

    reg [7:0] cnt_time;

    reg [31:0] cnt_clock;
    wire is_clk_max;

    assign MOUT = out_buf;

    always @(posedge CLK) begin
        if(RST == 1) cnt_clock <= 0;
        else begin

            if(cnt_clock >= C_FREQ / 100000 - 1) cnt_clock <= 0;
            else cnt_clock <= cnt_clock + 1;
        end
    end
    assign is_clk_max = (cnt_clock == C_FREQ / 100000 - 1);

    always @(posedge CLK) begin
        if(RST == 1) begin
            out_buf <= 0;
            cnt_time <= 8'b0;
        end
        else begin
            if(is_clk_max) cnt_time <= cnt_time + 1;

            if(cnt_time >= VAL) out_buf <= 0;
            else out_buf <= 1;
        end
    end
endmodule
module pwm_modulator(CLK, RST, VAL, MOUT, C_FREQ);

    input CLK, RST;

    input [7:0] VAL;

   input [64:0] C_FREQ;

    output MOUT;


    reg out_buf;

    reg [7:0] cnt_time;

    reg [31:0] cnt_clock;
    wire is_clk_max;

    assign MOUT = out_buf;

    always @(posedge CLK) begin
        if(RST == 1) cnt_clock <= 0;
        else begin

            if(cnt_clock >= C_FREQ / 100000 - 1) cnt_clock <= 0;
            else cnt_clock <= cnt_clock + 1;
        end
    end
    assign is_clk_max = (cnt_clock == C_FREQ / 100000 - 1);

    always @(posedge CLK) begin
        if(RST == 1) begin
            out_buf <= 0;
            cnt_time <= 8'b0;
        end
        else begin
            if(is_clk_max) cnt_time <= cnt_time + 1;

            if(cnt_time >= VAL) out_buf <= 0;
            else out_buf <= 1;
        end
    end
endmodule