data/full_repos/permissive/143278/ivltests/l_equiv_ca.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:97: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:103: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:115: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:123: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:130: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:137: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:151: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:10: Logical Operator LOGEQ expects 1 bit on the LHS, but LHS\'s VARREF \'wval1\' generates 4 bits.\n                                                                          : ... In instance top\n  assign lew = wval1 <-> wval2;\n                     ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:10: Logical Operator LOGEQ expects 1 bit on the RHS, but RHS\'s VARREF \'wval2\' generates 4 bits.\n                                                                          : ... In instance top\n  assign lew = wval1 <-> wval2;\n                     ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:10: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s LOGEQ generates 1 bits.\n                                                                          : ... In instance top\n  assign lew = wval1 <-> wval2;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:11: Logical Operator LOGEQ expects 1 bit on the LHS, but LHS\'s VARREF \'wval1\' generates 4 bits.\n                                                                          : ... In instance top\n  assign lews = $signed(wval1 <-> wval2);\n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:11: Logical Operator LOGEQ expects 1 bit on the RHS, but RHS\'s VARREF \'wval2\' generates 4 bits.\n                                                                          : ... In instance top\n  assign lews = $signed(wval1 <-> wval2);\n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/l_equiv_ca.v:11: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 1 bits.\n                                                                          : ... In instance top\n  assign lews = $signed(wval1 <-> wval2);\n              ^\n%Error: Exiting due to 27 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  wire res, ler0, ler1, ler2, ler3;
  wire [1:0] lew, lews;
  real rval1, rval2;
  reg val1, val2;
  reg [3:0] wval1, wval2;
  reg pass;

  assign res = val1 <-> val2;
  assign lew = wval1 <-> wval2;
  assign lews = $signed(wval1 <-> wval2);
  assign ler0 = rval1 <-> val2;
  assign ler1 = val1 <-> rval2;
  assign ler2 = rval1 <-> val2;
  assign ler3 = rval1 <-> rval2;

  initial begin
    pass = 1'b1;

    val1 = 1'b0;
    val2 = 1'b0;
    #1;
    if (res !== 1'b1) begin
      $display("FAILED: 1'b0 <-> 1'b0 returned %b not 1'b1", res);
      pass = 1'b0;
    end
    val2 = 1'b1;
    #1;
    if (res !== 1'b0) begin
      $display("FAILED: 1'b0 <-> 1'b1 returned %b not 1'b0", res);
      pass = 1'b0;
    end
    val2 = 1'bx;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'b0 <-> 1'bx returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'bz;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'b0 <-> 1'bz returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val1 = 1'b1;
    val2 = 1'b0;
    #1;
    if (res !== 1'b0) begin
      $display("FAILED: 1'b1 <-> 1'b0 returned %b not 1'b0", res);
      pass = 1'b0;
    end
    val2 = 1'b1;
    #1;
    if (res !== 1'b1) begin
      $display("FAILED: 1'b1 <-> 1'b1 returned %b not 1'b1", res);
      pass = 1'b0;
    end
    val2 = 1'bx;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'b1 <-> 1'bx returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'bz;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'b1 <-> 1'bz returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val1 = 1'bx;
    val2 = 1'b0;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bx <-> 1'b0 returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'b1;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bx <-> 1'b1 returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'bx;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bx <-> 1'bx returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'bz;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bx <-> 1'bz returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val1 = 1'bz;
    val2 = 1'b0;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bz <-> 1'b0 returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'b1;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bz <-> 1'b1 returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'bx;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bz <-> 1'bx returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'bz;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bz <-> 1'bz returned %b not 1'bx", res);
      pass = 1'b0;
    end

    rval1 = 0.0;
    val2 = 1'b0;
    #1;
    if (ler0 !== 1'b1) begin
      $display("FAILED: 0.0 <-> 1'b0 returned %b not 1'b1", ler0);
      pass = 1'b0;
    end
    val1 = 1'b0;
    rval2 = 2.0;
    #1;
    if (ler1 !== 1'b0) begin
      $display("FAILED: 1'b0 <-> 2.0 returned %b not 1'b0", ler1);
      pass = 1'b0;
    end
    rval1 = 2.0;
    val2 = 1'bx;
    #1;
    if (ler2 !== 1'bx) begin
      $display("FAILED: 2.0 <-> 1'bx returned %b not 1'bx", ler2);
      pass = 1'b0;
    end
    rval1 = -5.0;
    rval2 = 2.0;
    #1;
    if (ler3 !== 1'b1) begin
      $display("FAILED: -5.0 <-> -2.0 returned %b not 1'b1", ler3);
      pass = 1'b0;
    end
    wval1 = 4'b0110;
    wval2 = 4'b1001;
    #1;
    if (lew !== 2'b01) begin
      $display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b01", lew);
      pass = 1'b0;
    end
    if (lews !== 2'b11) begin
      $display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b11", lews);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  wire res, ler0, ler1, ler2, ler3;
  wire [1:0] lew, lews;
  real rval1, rval2;
  reg val1, val2;
  reg [3:0] wval1, wval2;
  reg pass;

  assign res = val1 <-> val2;
  assign lew = wval1 <-> wval2;
  assign lews = $signed(wval1 <-> wval2);
  assign ler0 = rval1 <-> val2;
  assign ler1 = val1 <-> rval2;
  assign ler2 = rval1 <-> val2;
  assign ler3 = rval1 <-> rval2;

  initial begin
    pass = 1'b1;

    val1 = 1'b0;
    val2 = 1'b0;
    #1;
    if (res !== 1'b1) begin
      $display("FAILED: 1'b0 <-> 1'b0 returned %b not 1'b1", res);
      pass = 1'b0;
    end
    val2 = 1'b1;
    #1;
    if (res !== 1'b0) begin
      $display("FAILED: 1'b0 <-> 1'b1 returned %b not 1'b0", res);
      pass = 1'b0;
    end
    val2 = 1'bx;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'b0 <-> 1'bx returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'bz;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'b0 <-> 1'bz returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val1 = 1'b1;
    val2 = 1'b0;
    #1;
    if (res !== 1'b0) begin
      $display("FAILED: 1'b1 <-> 1'b0 returned %b not 1'b0", res);
      pass = 1'b0;
    end
    val2 = 1'b1;
    #1;
    if (res !== 1'b1) begin
      $display("FAILED: 1'b1 <-> 1'b1 returned %b not 1'b1", res);
      pass = 1'b0;
    end
    val2 = 1'bx;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'b1 <-> 1'bx returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'bz;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'b1 <-> 1'bz returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val1 = 1'bx;
    val2 = 1'b0;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bx <-> 1'b0 returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'b1;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bx <-> 1'b1 returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'bx;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bx <-> 1'bx returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'bz;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bx <-> 1'bz returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val1 = 1'bz;
    val2 = 1'b0;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bz <-> 1'b0 returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'b1;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bz <-> 1'b1 returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'bx;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bz <-> 1'bx returned %b not 1'bx", res);
      pass = 1'b0;
    end
    val2 = 1'bz;
    #1;
    if (res !== 1'bx) begin
      $display("FAILED: 1'bz <-> 1'bz returned %b not 1'bx", res);
      pass = 1'b0;
    end

    rval1 = 0.0;
    val2 = 1'b0;
    #1;
    if (ler0 !== 1'b1) begin
      $display("FAILED: 0.0 <-> 1'b0 returned %b not 1'b1", ler0);
      pass = 1'b0;
    end
    val1 = 1'b0;
    rval2 = 2.0;
    #1;
    if (ler1 !== 1'b0) begin
      $display("FAILED: 1'b0 <-> 2.0 returned %b not 1'b0", ler1);
      pass = 1'b0;
    end
    rval1 = 2.0;
    val2 = 1'bx;
    #1;
    if (ler2 !== 1'bx) begin
      $display("FAILED: 2.0 <-> 1'bx returned %b not 1'bx", ler2);
      pass = 1'b0;
    end
    rval1 = -5.0;
    rval2 = 2.0;
    #1;
    if (ler3 !== 1'b1) begin
      $display("FAILED: -5.0 <-> -2.0 returned %b not 1'b1", ler3);
      pass = 1'b0;
    end
    wval1 = 4'b0110;
    wval2 = 4'b1001;
    #1;
    if (lew !== 2'b01) begin
      $display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b01", lew);
      pass = 1'b0;
    end
    if (lews !== 2'b11) begin
      $display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b11", lews);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule