data/full_repos/permissive/12298861/ver/uut_32_top.v
 line:48: before: "function"
1: b'%Error: data/full_repos/permissive/12298861/ver/uut_32_top.v:21: Cannot find include file: fcs32_32.v\n`include "fcs32_32.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/12298861/ver,data/full_repos/permissive/12298861/fcs32_32.v\n             data/full_repos/permissive/12298861/ver,data/full_repos/permissive/12298861/fcs32_32.v.v\n             data/full_repos/permissive/12298861/ver,data/full_repos/permissive/12298861/fcs32_32.v.sv\n             fcs32_32.v\n             fcs32_32.v.v\n             fcs32_32.v.sv\n             obj_dir/fcs32_32.v\n             obj_dir/fcs32_32.v.v\n             obj_dir/fcs32_32.v.sv\n%Error: data/full_repos/permissive/12298861/ver/uut_32_top.v:22: Cannot find include file: fcs32_brev.v\n`include "fcs32_brev.v" \n         ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module uut_32_top
(
    output wire [31:0] res_o,
    output wire [31:0] exp_o,
    output wire [31:0] obs_o,
    output wire        val_o,

    input  wire [31:0] data_i,
    input  wire        sof_i,
    input  wire        eof_i,

    input  wire        pclk_i
);

    localparam         LO                = 1'b0;
    localparam         HI                = 1'b1;
    localparam [31:0]  ZEROS             = {32{LO}};
    localparam [31:0]  ONES              = {32{HI}};


    reg  [31:0]  data_z1;
    reg          sof_z1;

    reg  [31:0]  exp_z2;
    reg  [31:0]  fcs_z2;
    reg          val_z2;

    reg          val_z3;
    reg  [31:0]  exp_z3;
    reg  [31:0]  fcs_z3;




    always @ (posedge pclk_i) begin
        data_z1[31:0] <= data_i[31:0];
        sof_z1        <= sof_i;

        val_z2        <= eof_i;

        if (eof_i == HI) begin
            exp_z2[31:0] <= data_i[31:0];
        end

        if (sof_z1 == HI) begin
            fcs_z2[31:0] <= fcs32_32(data_z1[31:0], ONES[31:0]);
        end else begin
            fcs_z2[31:0] <= fcs32_32(data_z1[31:0], fcs_z2[31:0]);
        end

        val_z3       <= val_z2;
        exp_z3[31:0] <= exp_z2[31:0];
        fcs_z3[31:0] <= fcs32_brev(fcs_z2[31:0]);
    end


    always @ (*) begin
        val_o       = val_z3;
        res_o[31:0] = fcs_z2[31:0];
        exp_o[31:0] = exp_z3[31:0];
        obs_o[31:0] = fcs_z3[31:0];
    end
endmodule
module uut_32_top
(
    output wire [31:0] res_o,
    output wire [31:0] exp_o,
    output wire [31:0] obs_o,
    output wire        val_o,

    input  wire [31:0] data_i,
    input  wire        sof_i,
    input  wire        eof_i,

    input  wire        pclk_i
);


    localparam         LO                = 1'b0;
    localparam         HI                = 1'b1;
    localparam [31:0]  ZEROS             = {32{LO}};
    localparam [31:0]  ONES              = {32{HI}};


    reg  [31:0]  data_z1;
    reg          sof_z1;

    reg  [31:0]  exp_z2;
    reg  [31:0]  fcs_z2;
    reg          val_z2;

    reg          val_z3;
    reg  [31:0]  exp_z3;
    reg  [31:0]  fcs_z3;




    always @ (posedge pclk_i) begin
        data_z1[31:0] <= data_i[31:0];
        sof_z1        <= sof_i;

        val_z2        <= eof_i;

        if (eof_i == HI) begin
            exp_z2[31:0] <= data_i[31:0];
        end

        if (sof_z1 == HI) begin
            fcs_z2[31:0] <= fcs32_32(data_z1[31:0], ONES[31:0]);
        end else begin
            fcs_z2[31:0] <= fcs32_32(data_z1[31:0], fcs_z2[31:0]);
        end

        val_z3       <= val_z2;
        exp_z3[31:0] <= exp_z2[31:0];
        fcs_z3[31:0] <= fcs32_brev(fcs_z2[31:0]);
    end


    always @ (*) begin
        val_o       = val_z3;
        res_o[31:0] = fcs_z2[31:0];
        exp_o[31:0] = exp_z3[31:0];
        obs_o[31:0] = fcs_z3[31:0];
    end
endmodule