data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v
1: b'%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:2: Cannot find include file: ../../utils/test.v\n`include "../../utils/test.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165846232/components/SignAddSub,data/full_repos/permissive/165846232/../../utils/test.v\n             data/full_repos/permissive/165846232/components/SignAddSub,data/full_repos/permissive/165846232/../../utils/test.v.v\n             data/full_repos/permissive/165846232/components/SignAddSub,data/full_repos/permissive/165846232/../../utils/test.v.sv\n             ../../utils/test.v\n             ../../utils/test.v.v\n             ../../utils/test.v.sv\n             obj_dir/../../utils/test.v\n             obj_dir/../../utils/test.v.v\n             obj_dir/../../utils/test.v.sv\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:3: Cannot find include file: ./SignAddSub.v\n`include "./SignAddSub.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:39: Define or directive not defined: \'`defClock\'\n    `defClock(Clk, 2);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:39: syntax error, unexpected \'(\'\n    `defClock(Clk, 2);\n              ^~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:56: Define or directive not defined: \'`startTest\'\n `startTest("SignAddSub");\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:56: syntax error, unexpected \'(\'\n `startTest("SignAddSub");\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:64: Define or directive not defined: \'`describe\'\n        `describe("Test 20 +/- 8");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:65: Define or directive not defined: \'`assert\'\n        `assert(Result, 20+8);; \n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:65: syntax error, unexpected \'=\', expecting IDENTIFIER\n        AddSubMode = 0; \n                   ^\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:65: Define or directive not defined: \'`assert\'\n        `assert(Result, 20-8);;;\n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:67: Define or directive not defined: \'`describe\'\n        `describe("Test 100 +/- 100");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:67: syntax error, unexpected \'(\'\n        `describe("Test 100 +/- 100");\n                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:68: Define or directive not defined: \'`assert\'\n        `assert(Result, 100+100);; \n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:68: syntax error, unexpected \'=\', expecting IDENTIFIER\n        AddSubMode = 0; \n                   ^\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:68: Define or directive not defined: \'`assert\'\n        `assert(Result, 100-100);;;\n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:70: Define or directive not defined: \'`describe\'\n        `describe("Test 0 +/- 0");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:70: syntax error, unexpected \'(\'\n        `describe("Test 0 +/- 0");\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:71: Define or directive not defined: \'`assert\'\n        `assert(Result, 0+0);; \n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:71: syntax error, unexpected \'=\', expecting IDENTIFIER\n        AddSubMode = 0; \n                   ^\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:71: Define or directive not defined: \'`assert\'\n        `assert(Result, 0-0);;;\n        ^~~~~~~\n%Error: data/full_repos/permissive/165846232/components/SignAddSub/TestSignAddSub.v:73: Define or directive not defined: \'`endTest\'\n `endTest\n ^~~~~~~~\n%Error: Exiting due to 21 error(s)\n'
module TestSignAddSub
#(
	parameter INPUT_BIT_WIDTH = 8
);


    `defClock(Clk, 2);
	reg signed [INPUT_BIT_WIDTH-1:0] InputA;
	reg signed [INPUT_BIT_WIDTH-1:0] InputB;
	reg AddSubMode;


	wire [INPUT_BIT_WIDTH-1:0] Result;


	SignAddSub uut (
		.AddSubMode(AddSubMode),
		.InputA(InputA),
		.InputB(InputB),
		.Clk(Clk),
        .Result(Result)
	);

	`startTest("SignAddSub");

		AddSubMode = 0;
        InputA = 0;
        InputB = 0;
		Clk = 0;
		#100;
        
        `describe("Test 20 +/- 8");
            `do_add_sub(20, 8);
            
        `describe("Test 100 +/- 100");
            `do_add_sub(100, 100);
            
        `describe("Test 0 +/- 0");
            `do_add_sub(0, 0);

	`endTest

      
endmodule
module TestSignAddSub
#(
	parameter INPUT_BIT_WIDTH = 8
);



    `defClock(Clk, 2);
	reg signed [INPUT_BIT_WIDTH-1:0] InputA;
	reg signed [INPUT_BIT_WIDTH-1:0] InputB;
	reg AddSubMode;


	wire [INPUT_BIT_WIDTH-1:0] Result;


	SignAddSub uut (
		.AddSubMode(AddSubMode),
		.InputA(InputA),
		.InputB(InputB),
		.Clk(Clk),
        .Result(Result)
	);

	`startTest("SignAddSub");

		AddSubMode = 0;
        InputA = 0;
        InputB = 0;
		Clk = 0;
		#100;
        
        `describe("Test 20 +/- 8");
            `do_add_sub(20, 8);
            
        `describe("Test 100 +/- 100");
            `do_add_sub(100, 100);
            
        `describe("Test 0 +/- 0");
            `do_add_sub(0, 0);

	`endTest

      
endmodule