data/full_repos/permissive/211316121/lab5_1/FlipFlop.v
data/verilator_xmls/d8ef6967-f9c6-4ff4-9a6d-83398a96c8b5.xml
module CLKDIV(
    input clkstd,
    output clk
);
reg [28:0] q;

always@(posedge clkstd)
    q<=q+1;

assign clk=q[26];

endmodule
module CLKDIV(
    input clkstd,
    output clk
);

reg [28:0] q;

always@(posedge clkstd)
    q<=q+1;

assign clk=q[26];

endmodule