data/full_repos/permissive/152183157/IC_CDesign8.v
 line:279: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/152183157/IC_CDesign8.v:269: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk=~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/152183157/IC_CDesign8.v:279: Unsupported: Ignoring delay on this delayed statement.\n #500 $stop;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/152183157/IC_CDesign8.v:132: Multiple top level modules\n                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                         : ... Top module \'oreg\'\nmodule oreg(output reg [8:0]oregout,\n       ^~~~\n                                                                         : ... Top module \'remreg\'\nmodule remreg();\n       ^~~~~~\n                                                                         : ... Top module \'complement\'\nmodule complement(output reg [8:0]comout,\n       ^~~~~~~~~~\n                                                                         : ... Top module \'IC\'\nmodule IC;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/152183157/IC_CDesign8.v:85: Operator ADD expects 9 bits on the RHS, but RHS\'s ARRAYSEL generates 1 bits.\n                                                                     : ... In instance IC.icw\nassign resulttmp[9]=resulttmp[8]+resone[9];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/152183157/IC_CDesign8.v:92: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 10 bits.\n                                                                     : ... In instance IC.icw\n  remainder=remaindertmp[8];\n           ^\n%Warning-WIDTH: data/full_repos/permissive/152183157/IC_CDesign8.v:94: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 10 bits.\n                                                                     : ... In instance IC.icw\n  remainder=remaindertmp[9];\n           ^\n%Warning-WIDTH: data/full_repos/permissive/152183157/IC_CDesign8.v:173: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'comtmp\' generates 8 bits.\n                                                                      : ... In instance complement\n comout=comtmp;\n       ^\n%Warning-INFINITELOOP: data/full_repos/permissive/152183157/IC_CDesign8.v:269: Infinite loop (condition always true)\n                                                                             : ... In instance IC\n forever #10 clk=~clk;\n ^~~~~~~\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module IC_CDesign(output [1:0]sign,
						output reg [8:0]remainder,
						output reg [8:0]result,
						input [8:0]dividend,
						input [8:0]divisor,
						input clk);

wire [9:0]dividendtmp;
wire [9:0]divisortmp[8:0];
wire [9:0]remaindertmp[9:0];
wire [9:0]remaindershitmp[7:0];
wire [8:0]resulttmp[9:0];
assign resulttmp[0]=9'b0_0000_0000;
wire resone[9:0];
assign resone[0]=1'b1;

ireg irA0(sign,dividendtmp,dividend,clk);
chose choB1(divisortmp[0],divisor,resone[0],clk);
adder addA1(remaindertmp[0],resone[1],dividendtmp,divisortmp[0],clk);
shift shiA1(remaindershitmp[0],resulttmp[1],remaindertmp[0],resulttmp[0],resone[1],clk);

chose choB2(divisortmp[1],divisor,resone[1],clk);
adder addA2(remaindertmp[1],resone[2],remaindershitmp[0],divisortmp[1],clk);
shift shiA2(remaindershitmp[1],resulttmp[2],remaindertmp[1],resulttmp[1],resone[2],clk);

chose choB3(divisortmp[2],divisor,resone[2],clk);
adder addA3(remaindertmp[2],resone[3],remaindershitmp[1],divisortmp[2],clk);
shift shiA3(remaindershitmp[2],resulttmp[3],remaindertmp[2],resulttmp[2],resone[3],clk);

chose choB4(divisortmp[3],divisor,resone[3],clk);
adder addA4(remaindertmp[3],resone[4],remaindershitmp[2],divisortmp[3],clk);
shift shiA4(remaindershitmp[3],resulttmp[4],remaindertmp[3],resulttmp[3],resone[4],clk);

chose choB5(divisortmp[4],divisor,resone[4],clk);
adder addA5(remaindertmp[4],resone[5],remaindershitmp[3],divisortmp[4],clk);
shift shiA5(remaindershitmp[4],resulttmp[5],remaindertmp[4],resulttmp[4],resone[5],clk);

chose choB6(divisortmp[5],divisor,resone[5],clk);
adder addA6(remaindertmp[5],resone[6],remaindershitmp[4],divisortmp[5],clk);
shift shiA6(remaindershitmp[5],resulttmp[6],remaindertmp[5],resulttmp[5],resone[6],clk);

chose choB7(divisortmp[6],divisor,resone[6],clk);
adder addA7(remaindertmp[6],resone[7],remaindershitmp[5],divisortmp[6],clk);
shift shiA7(remaindershitmp[6],resulttmp[7],remaindertmp[6],resulttmp[6],resone[7],clk);

chose choB8(divisortmp[7],divisor,resone[7],clk);
adder addA8(remaindertmp[7],resone[8],remaindershitmp[6],divisortmp[7],clk);
shift shiA8(remaindershitmp[7],resulttmp[8],remaindertmp[7],resulttmp[7],resone[8],clk);

chose choB9(divisortmp[8],divisor,resone[8],clk);
adder addA9(remaindertmp[8],resone[9],remaindershitmp[7],divisortmp[8],clk);
assign resulttmp[9]=resulttmp[8]+resone[9];
remrec rr(remaindertmp[9],remaindertmp[8],divisortmp[8],resone[9],clk);

always @(posedge clk)
begin
	result=resulttmp[9];
	if(resone[9])
		remainder=remaindertmp[8];
	else if(!resone[9])
		remainder=remaindertmp[9];
end
endmodule
module IC_CDesign(output [1:0]sign,
						output reg [8:0]remainder,
						output reg [8:0]result,
						input [8:0]dividend,
						input [8:0]divisor,
						input clk);


wire [9:0]dividendtmp;
wire [9:0]divisortmp[8:0];
wire [9:0]remaindertmp[9:0];
wire [9:0]remaindershitmp[7:0];
wire [8:0]resulttmp[9:0];
assign resulttmp[0]=9'b0_0000_0000;
wire resone[9:0];
assign resone[0]=1'b1;

ireg irA0(sign,dividendtmp,dividend,clk);
chose choB1(divisortmp[0],divisor,resone[0],clk);
adder addA1(remaindertmp[0],resone[1],dividendtmp,divisortmp[0],clk);
shift shiA1(remaindershitmp[0],resulttmp[1],remaindertmp[0],resulttmp[0],resone[1],clk);

chose choB2(divisortmp[1],divisor,resone[1],clk);
adder addA2(remaindertmp[1],resone[2],remaindershitmp[0],divisortmp[1],clk);
shift shiA2(remaindershitmp[1],resulttmp[2],remaindertmp[1],resulttmp[1],resone[2],clk);

chose choB3(divisortmp[2],divisor,resone[2],clk);
adder addA3(remaindertmp[2],resone[3],remaindershitmp[1],divisortmp[2],clk);
shift shiA3(remaindershitmp[2],resulttmp[3],remaindertmp[2],resulttmp[2],resone[3],clk);

chose choB4(divisortmp[3],divisor,resone[3],clk);
adder addA4(remaindertmp[3],resone[4],remaindershitmp[2],divisortmp[3],clk);
shift shiA4(remaindershitmp[3],resulttmp[4],remaindertmp[3],resulttmp[3],resone[4],clk);

chose choB5(divisortmp[4],divisor,resone[4],clk);
adder addA5(remaindertmp[4],resone[5],remaindershitmp[3],divisortmp[4],clk);
shift shiA5(remaindershitmp[4],resulttmp[5],remaindertmp[4],resulttmp[4],resone[5],clk);

chose choB6(divisortmp[5],divisor,resone[5],clk);
adder addA6(remaindertmp[5],resone[6],remaindershitmp[4],divisortmp[5],clk);
shift shiA6(remaindershitmp[5],resulttmp[6],remaindertmp[5],resulttmp[5],resone[6],clk);

chose choB7(divisortmp[6],divisor,resone[6],clk);
adder addA7(remaindertmp[6],resone[7],remaindershitmp[5],divisortmp[6],clk);
shift shiA7(remaindershitmp[6],resulttmp[7],remaindertmp[6],resulttmp[6],resone[7],clk);

chose choB8(divisortmp[7],divisor,resone[7],clk);
adder addA8(remaindertmp[7],resone[8],remaindershitmp[6],divisortmp[7],clk);
shift shiA8(remaindershitmp[7],resulttmp[8],remaindertmp[7],resulttmp[7],resone[8],clk);

chose choB9(divisortmp[8],divisor,resone[8],clk);
adder addA9(remaindertmp[8],resone[9],remaindershitmp[7],divisortmp[8],clk);
assign resulttmp[9]=resulttmp[8]+resone[9];
remrec rr(remaindertmp[9],remaindertmp[8],divisortmp[8],resone[9],clk);

always @(posedge clk)
begin
	result=resulttmp[9];
	if(resone[9])
		remainder=remaindertmp[8];
	else if(!resone[9])
		remainder=remaindertmp[9];
end
endmodule