data/full_repos/permissive/130390123/upcount.v
data/verilator_xmls/cf9f6327-b3de-41fd-9228-0b34cc41dbc5.xml
module upcount(
	Clear,
	Clock, 
	Q
	);
	input Clear, Clock;
	output reg [1:0] Q = 2'b00;
	always @(posedge Clock)
	if (Clear)
	Q <= 2'b0;
	else
	Q <= Q + 1'b1;
endmodule
module upcount(
	Clear,
	Clock, 
	Q
	);

	input Clear, Clock;
	output reg [1:0] Q = 2'b00;
	always @(posedge Clock)
	if (Clear)
	Q <= 2'b0;
	else
	Q <= Q + 1'b1;
endmodule