data/full_repos/permissive/168395472/labs/04_devboard/top.v
data/verilator_xmls/ab1deee1-c819-4e11-a1f0-ca0279198227.xml
module blink_gen(
    input clk,

    output clk2
);

reg [25:0]cnt = 0;

assign clk2 = cnt[25];

always @(posedge clk) begin
    cnt <= cnt + 26'b1;
end

endmodule
module blink_gen(
    input clk,

    output clk2
);


reg [25:0]cnt = 0;

assign clk2 = cnt[25];

always @(posedge clk) begin
    cnt <= cnt + 26'b1;
end

endmodule