data/full_repos/permissive/143278/ivltests/real4.v
 line:28: before: "_8979323846_2643383279"
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/real4.v:89: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'err\' generates 32 bits.\n                                                                     : ... In instance test\n if (err)\n ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module test;

    integer	err, i;
    real	r;
    reg [63:0]	b;

    parameter PI = 3.1415926535_8979323846_2643383279;

    initial begin
	err = 0;




	i = $rtoi(0.1);
	if (i != 0) begin
	    err = 1;
	    $display("$rtoi(0.1): %0d != 0", i);
	end
	i = $rtoi(9.6);
	if (i != 9) begin
	    err = 1;
	    $display("$rtoi(9.6): %0d != 9", i);
	end




	b = $realtobits(PI);
	if (b != 64'h400921FB54442D18) begin
	    err = 1;
	    $display("$realtobits(PI): 'h%x != 'h400921FB54442D18", b);
	end
	b = $realtobits(1.1);
	if (b != 64'h3ff199999999999a) begin
	    err = 1;
	    $display("$realtobits(1.1): 'h%x != 'h400921FB54442D18", b);
	end




	r = $bitstoreal(64'h400921FB54442D18);
	if (r != PI) begin
	    err = 1;
	    $display("$realtobits(PI): %20.17f != %20.17f", r, PI);
	end
	r = $bitstoreal(64'h3FF4CCCCCCCCCCCD);
	if (r != 1.3) begin
	    err = 1;
	    $display("$realtobits(1.3): %20.17f != 1.3", r);
	end




	r = $itor(1);
	if (r != 1.0) begin
	    err = 1;
	    $display("$itor(1): %20.1f != 1.0", r);
	end
	r = $itor(123456789);
	if (r != 123456789.0) begin
	    err = 1;
	    $display("$itor(123456789): %20.1f != 123456789.0", r);
	end

	if (err)
	    $display("FAILED");
	else
	    $display("PASSED");

	$finish;
    end

endmodule
module test;


    integer	err, i;
    real	r;
    reg [63:0]	b;

    parameter PI = 3.1415926535_8979323846_2643383279;

    initial begin
	err = 0;




	i = $rtoi(0.1);
	if (i != 0) begin
	    err = 1;
	    $display("$rtoi(0.1): %0d != 0", i);
	end
	i = $rtoi(9.6);
	if (i != 9) begin
	    err = 1;
	    $display("$rtoi(9.6): %0d != 9", i);
	end




	b = $realtobits(PI);
	if (b != 64'h400921FB54442D18) begin
	    err = 1;
	    $display("$realtobits(PI): 'h%x != 'h400921FB54442D18", b);
	end
	b = $realtobits(1.1);
	if (b != 64'h3ff199999999999a) begin
	    err = 1;
	    $display("$realtobits(1.1): 'h%x != 'h400921FB54442D18", b);
	end




	r = $bitstoreal(64'h400921FB54442D18);
	if (r != PI) begin
	    err = 1;
	    $display("$realtobits(PI): %20.17f != %20.17f", r, PI);
	end
	r = $bitstoreal(64'h3FF4CCCCCCCCCCCD);
	if (r != 1.3) begin
	    err = 1;
	    $display("$realtobits(1.3): %20.17f != 1.3", r);
	end




	r = $itor(1);
	if (r != 1.0) begin
	    err = 1;
	    $display("$itor(1): %20.1f != 1.0", r);
	end
	r = $itor(123456789);
	if (r != 123456789.0) begin
	    err = 1;
	    $display("$itor(123456789): %20.1f != 123456789.0", r);
	end

	if (err)
	    $display("FAILED");
	else
	    $display("PASSED");

	$finish;
    end

endmodule