data/full_repos/permissive/167856740/cpu/mux_privilege.v
data/verilator_xmls/c145e9e9-0125-4d84-9d83-b1d606eaafa8.xml
module mux_privilege(
        input wire I_exception,
		input wire I_privsel,
		input wire [31:0] I_mevect,
		input wire [31:0] I_data1,
		input wire [31:0] I_data2,
		output wire [31:0] O_data
	  );

    assign O_data = (I_exception == 1'b1) ? I_mevect : ((I_privsel == 1'b0) ? I_data1 : I_data2);

endmodule
module mux_privilege(
        input wire I_exception,
		input wire I_privsel,
		input wire [31:0] I_mevect,
		input wire [31:0] I_data1,
		input wire [31:0] I_data2,
		output wire [31:0] O_data
	  );


    assign O_data = (I_exception == 1'b1) ? I_mevect : ((I_privsel == 1'b0) ? I_data1 : I_data2);

endmodule