data/full_repos/permissive/120043621/statemachine.sv
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data/verilator_xmls/d069c4e9-e636-4e1a-b8c7-c7bbbba40874.xml
module statemachine (

    input logic clk,
    input logic rst,
    input logic start,


    input logic n_equals_iterations,
    input logic n_lt_iterations,
    input logic donei,
    input logic donej,
    input logic dist_gt_max_dist,


    output logic enx,
    output logic eny,
    output logic ena,
    output logic enb,
    output logic enn,
    output logic eni,
    output logic enj,

    output logic initx,
    output logic inity,
    output logic inita,
    output logic initb,
    output logic initn,
    output logic initi,
    output logic initj,


    output logic plot,
    output logic done
);

    enum {
        IDLE,
        INIT,
        JLOOP,
        ILOOP,
        ITERLOOP,
        PLOT,
        ENDLOOP,
        DONE
    } current, next;


    always_comb begin
        case (current)
            IDLE: next = start ? INIT : IDLE;
            INIT: next = JLOOP;
            JLOOP: next = ILOOP;
            ILOOP: next = ITERLOOP;
            ITERLOOP: next = (dist_gt_max_dist | ~n_lt_iterations) ? PLOT : ITERLOOP;
            PLOT: next = donei ? ENDLOOP : ILOOP;
            ENDLOOP: next = donej ? DONE : JLOOP;
            DONE: next = DONE;
        endcase
    end


    always_ff @(posedge clk, negedge rst) begin
        current <= rst == 0 ? IDLE : next;
    end


    always_comb begin

        {enx, eny, ena, enb, enn, eni, enj} = 7'b0;
        {initx, inity, inita, initb, initn, initi, initj} = 7'b0;
        {plot, done} = 2'b0;


        case (current)
            INIT: begin
                {inity, eny} = 2'b11;
                {initj, enj} = 2'b11;
            end
            JLOOP: begin
                {initx, enx} = 2'b11;
                {initi, eni} = 2'b11;
            end
            ILOOP: begin
                {inita, ena} = 2'b11;
                {initb, enb} = 2'b11;
                {initn, enn} = 2'b11;
            end
            ITERLOOP: {ena, enb, enn} = {2'b11, ~dist_gt_max_dist};
            PLOT: {enx, eni, plot} = 3'b111;
            ENDLOOP: {eny, enj} = 2'b11;
            DONE: done = 1'b1;
            default: done = 1'b0;
        endcase
    end
endmodule
module statemachine (

    input logic clk,
    input logic rst,
    input logic start,


    input logic n_equals_iterations,
    input logic n_lt_iterations,
    input logic donei,
    input logic donej,
    input logic dist_gt_max_dist,


    output logic enx,
    output logic eny,
    output logic ena,
    output logic enb,
    output logic enn,
    output logic eni,
    output logic enj,

    output logic initx,
    output logic inity,
    output logic inita,
    output logic initb,
    output logic initn,
    output logic initi,
    output logic initj,


    output logic plot,
    output logic done
);


    enum {
        IDLE,
        INIT,
        JLOOP,
        ILOOP,
        ITERLOOP,
        PLOT,
        ENDLOOP,
        DONE
    } current, next;


    always_comb begin
        case (current)
            IDLE: next = start ? INIT : IDLE;
            INIT: next = JLOOP;
            JLOOP: next = ILOOP;
            ILOOP: next = ITERLOOP;
            ITERLOOP: next = (dist_gt_max_dist | ~n_lt_iterations) ? PLOT : ITERLOOP;
            PLOT: next = donei ? ENDLOOP : ILOOP;
            ENDLOOP: next = donej ? DONE : JLOOP;
            DONE: next = DONE;
        endcase
    end


    always_ff @(posedge clk, negedge rst) begin
        current <= rst == 0 ? IDLE : next;
    end


    always_comb begin

        {enx, eny, ena, enb, enn, eni, enj} = 7'b0;
        {initx, inity, inita, initb, initn, initi, initj} = 7'b0;
        {plot, done} = 2'b0;


        case (current)
            INIT: begin
                {inity, eny} = 2'b11;
                {initj, enj} = 2'b11;
            end
            JLOOP: begin
                {initx, enx} = 2'b11;
                {initi, eni} = 2'b11;
            end
            ILOOP: begin
                {inita, ena} = 2'b11;
                {initb, enb} = 2'b11;
                {initn, enn} = 2'b11;
            end
            ITERLOOP: {ena, enb, enn} = {2'b11, ~dist_gt_max_dist};
            PLOT: {enx, eni, plot} = 3'b111;
            ENDLOOP: {eny, enj} = 2'b11;
            DONE: done = 1'b1;
            default: done = 1'b0;
        endcase
    end
endmodule