data/full_repos/permissive/119397495/washing_tb.v
 line:10: before: "("
1: b'%Error: data/full_repos/permissive/119397495/washing_tb.v:7: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("washing.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/119397495/washing_tb.v:8: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0,washing_tb);\n   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/119397495/washing_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n    # 10 start = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119397495/washing_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n      # 10 td = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119397495/washing_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n      # 10 tf = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119397495/washing_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n      # 10 tr = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119397495/washing_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n      # 10 ts = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119397495/washing_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n      # 10 tw = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119397495/washing_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #10 tw = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/119397495/washing_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  # 1 start = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119397495/washing_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n   # 200 $stop;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/119397495/washing_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #160 door = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/119397495/washing_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10 door = 0;\n  ^\n%Error: data/full_repos/permissive/119397495/washing_tb.v:42: Unsupported or unknown PLI call: $monitor\n $monitor("At time %t, value = %h (%0d)",\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module washing_tb;

  reg start = 0;
  reg door = 0;
  reg td, tf, tr, ts, tw;
  initial begin
	  $dumpfile("washing.vcd");
	  $dumpvars(0,washing_tb);
    # 10 start = 1;
    repeat (8) begin
      # 10 td = 1;
      # 10 tf = 1;
      td = 0;
      # 10 tr = 1;
      tf = 0;
      # 10 ts = 1;
      tr = 0;
      # 10 tw = 1;
      ts = 0;
      #10 tw = 0;
		# 1 start = 0;
    end
	 
	  # 200 $stop;
  end
  
  initial  begin
		#160 door = 1;
		#10 door = 0;
	end


  wire  agitator, motor, pump, speed, water_fill, reset;

  washing_machine_control w1 (td, tf, tr, ts, tw,
                              door, start, agitator,
                              motor, pump, speed,
                              water_fill, reset);


  initial
	$monitor("At time %t, value = %h (%0d)",
			  $time, agitator, agitator);


endmodule
module washing_tb;


  reg start = 0;
  reg door = 0;
  reg td, tf, tr, ts, tw;
  initial begin
	  $dumpfile("washing.vcd");
	  $dumpvars(0,washing_tb);
    # 10 start = 1;
    repeat (8) begin
      # 10 td = 1;
      # 10 tf = 1;
      td = 0;
      # 10 tr = 1;
      tf = 0;
      # 10 ts = 1;
      tr = 0;
      # 10 tw = 1;
      ts = 0;
      #10 tw = 0;
		# 1 start = 0;
    end
	 
	  # 200 $stop;
  end
  
  initial  begin
		#160 door = 1;
		#10 door = 0;
	end


  wire  agitator, motor, pump, speed, water_fill, reset;

  washing_machine_control w1 (td, tf, tr, ts, tw,
                              door, start, agitator,
                              motor, pump, speed,
                              water_fill, reset);


  initial
	$monitor("At time %t, value = %h (%0d)",
			  $time, agitator, agitator);


endmodule