data/full_repos/permissive/104269513/pipeline_dualCF.v
 line:168: before: "integer"
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline_dualCF.v:691: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline_dualCF.v:696: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 0;\n ^\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:177: Cannot find file containing module: \'datapath\'\ndatapath dp  (   \n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.v\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.sv\n             datapath\n             datapath.v\n             datapath.sv\n             obj_dir/datapath\n             obj_dir/datapath.v\n             obj_dir/datapath.sv\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:223: Cannot find file containing module: \'ALU_ctrl\'\nALU_ctrl EX_ALU (\n^~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:231: Cannot find file containing module: \'control\'\ncontrol ctrl (\n^~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:294: Cannot find file containing module: \'convert_fifo\'\nconvert_fifo fifo_dm  ( \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:674: Cannot find file containing module: \'regfile\'\nregfile op_reg(\n^~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pipeline_dualCF #(
				parameter MAX_DEPTH = 256,
				parameter ADDR_WIDTH = 8,
				parameter DATA_WIDTH = 64,
				parameter CTRL_WIDTH = DATA_WIDTH/8,
				parameter Number_of_FIFO = 2
				)
				(

				input 	[DATA_WIDTH-1:0]			in_data,
				input 	[CTRL_WIDTH-1:0]			in_ctrl,
				output 	reg [DATA_WIDTH-1:0]		out_data,
				output 	reg [CTRL_WIDTH-1:0]		out_ctrl,


				input 								out_rdy,
				input 								in_wr,
				output reg							in_rdy,
				output reg							out_wr,
				

				input								IorD,
				input	[8:0]						Addr_in,
				input [DATA_WIDTH-1:0]				Data_In,
				

				output	[8:0]						Addr_DM,
				output	[8:0]						Addr_IM,		
				output	[31:0]						Data_out_IM,
				output	[DATA_WIDTH-1:0]			Data_out_DM,
				output 	reg							full,
				output 	reg							nearly_full,
				output 	reg							nearly_empty,
				output 	reg							empty,			
				output	reg							fifo_busy,			
				output 	reg [1:0]					packet_count,			
				output 	reg [ADDR_WIDTH-1:0]		FIFO_RD_addr,
				output 	reg [ADDR_WIDTH-1:0]		FIFO_WR_addr,
				output	reg [1:0]					fifo_state,
				output	reg [ADDR_WIDTH:0]			DEPTH,
				output	reg							PL_EN,
				output	reg							SW_CTRL,
				output	reg	[Number_of_FIFO-1:0]	fifo_rd_en,
				output	reg	[Number_of_FIFO-1:0]	fifo_wr_en,
				

				output reg 	[Number_of_FIFO-1:0]	Master_reg,
				

				input clk,
				input rst
				);

				




reg PL_EN_next;
reg SW_CTRL_next;
reg R_W_EN,R_W_EN_next;
reg [15:0] counter,counter_next;


wire DM_wea;
wire [DATA_WIDTH-1:0] PL_Data_mem_dina;
reg [DATA_WIDTH-1:0] PL_MEM_dout;
wire [ADDR_WIDTH-1:0] PL_Addr_DM;		
reg PL_done_next;
wire PL_done_raw;
reg PL_done;



wire [DATA_WIDTH-1:0] EX_ALU_in1,EX_ALU_in2;


wire [DATA_WIDTH-1:0] EX_ALU_out;



wire [3:0] ALUop,EX_ALUop;
wire RegWrite,MemWrite, MemtoReg, Jump, ble, PL_done_ctrl, FW_ld;
reg [log2(Number_of_FIFO)-1:0] fifo_mem_sel;
reg [log2(Number_of_FIFO)-1:0] fifo_sel, fifo_sel_next;
wire [log2(Number_of_FIFO)-1:0] mem_sel;




reg [Number_of_FIFO-1:0] fifo_rd_en_next;
reg [Number_of_FIFO-1:0] fifo_wr_en_next;


reg [ADDR_WIDTH-1:0] first_word; 
	

wire [Number_of_FIFO-1:0] pckt_rd_wr_next;
reg [Number_of_FIFO-1:0] pckt_rd_wr;



wire [DATA_WIDTH-1:0] cf_out_data [Number_of_FIFO-1:0];
wire [CTRL_WIDTH-1:0] cf_out_ctrl [Number_of_FIFO-1:0];
reg [Number_of_FIFO-1:0] cf_out_rdy;
reg [Number_of_FIFO-1:0] cf_in_wr;
wire [Number_of_FIFO-1:0] cf_in_rdy;
wire [Number_of_FIFO-1:0] cf_out_wr;

wire [Number_of_FIFO-1:0] cf_full;
wire [Number_of_FIFO-1:0] cf_nearly_full;	
wire [Number_of_FIFO-1:0] cf_nearly_empty;	
wire [Number_of_FIFO-1:0] cf_empty;			
wire [Number_of_FIFO-1:0] cf_fifo_busy;			
wire [1:0] cf_packet_count [Number_of_FIFO-1:0];			
wire [ADDR_WIDTH-1:0] cf_FIFO_RD_addr [Number_of_FIFO-1:0];
wire [ADDR_WIDTH-1:0] cf_FIFO_WR_addr [Number_of_FIFO-1:0];
wire [1:0] cf_fifo_state [Number_of_FIFO-1:0];
wire [ADDR_WIDTH:0] cf_DEPTH [Number_of_FIFO-1:0];
wire [ADDR_WIDTH-1:0] cf_first_word [Number_of_FIFO-1:0]; 

reg [Number_of_FIFO-1:0] cf_DM_wea;
wire [DATA_WIDTH-1:0] cf_PL_MEM_dout [Number_of_FIFO-1:0];


  function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction
		
datapath dp		(
				 .clk(clk),
				 .rst(rst),


				 .pipeline_en(PL_EN),
				 .sw_ctrl(SW_CTRL),
				 .IorD(IorD),
				 .WorR(R_W_EN),
				 .MEM_PL_done(PL_done_raw),
				 

				 .Addr_in(Addr_in),
				 .Data_in(Data_In),
				 .IM_Addr_out(Addr_IM),
				 .DM_Addr_out(Addr_DM),
				 .IM_Data_out(Data_out_IM),
				 .DM_Data_out(Data_out_DM),
				 

				 .Data_mem_wea (DM_wea),
				 .Data_mem_dina (PL_Data_mem_dina),
				 .Data_mem_addr (PL_Addr_DM), 
				 .MEM_Dout(PL_MEM_dout),
				 .first_word(first_word),

				 

				 .EX_ALU_in1(EX_ALU_in1),
				 .EX_ALU_in2(EX_ALU_in2),
				 .EX_ALU_out(EX_ALU_out),
				 .EX_ALUop(EX_ALUop),
				 

				 .RegWrite(RegWrite),
				 .ALUSrc(ALUSrc),
				 .MemWrite(MemWrite),
				 .MemtoReg(MemtoReg),	
				 .Jump(Jump),	
				 .ble(ble),	
				 .imme(imme),
				 .ALUop(ALUop),
				 .PL_done(PL_done_ctrl),
				 .FW_ld (FW_ld)
				);

ALU_ctrl EX_ALU (
				.A(EX_ALU_in1),
				.B(EX_ALU_in2),
				.cmd(EX_ALUop),					
				.psw(),
				.Data_out(EX_ALU_out)
				);
				
control ctrl	(
				.instruction(Data_out_IM),
				.RegWrite(RegWrite),
				.ALUSrc(ALUSrc),
				.MemWrite(MemWrite),
				.MemtoReg(MemtoReg),	
				.Jump(Jump),	
				.ble(ble),	
				.imme(imme), 
				.PL_done(PL_done_ctrl),
				.FW_ld (FW_ld),
				.ALUop(ALUop),
				.Master_reg(),
				.mem_sel(mem_sel)
				);
				

genvar i;
generate
	for (i=0 ; i<Number_of_FIFO ; i = i+1)
	begin: CF
convert_fifo fifo_dm  (
				.fifo_rd_en(fifo_rd_en[i]), 
				.fifo_wr_en(fifo_wr_en[i]),
				.out_rdy(cf_out_rdy[i]), 
				.in_wr(cf_in_wr[i]),
				.out_wr(cf_out_wr[i]),
				.pckt_rd_wr(pckt_rd_wr_next[i]),
				

				.in_rdy(cf_in_rdy[i]),
				.full(cf_full[i]),
				.empty(cf_empty[i]), 
				.nearly_full(cf_nearly_full[i]), 
				.nearly_empty(cf_nearly_empty[i]),
				.packet_count(cf_packet_count[i]),
				.first_word(cf_first_word[i]),
				.last_word(),
				.fifo_busy(cf_fifo_busy[i]),
				


				.fifo_data_in(in_data),
				.fifo_data_out(cf_out_data[i]),
				.fifo_ctrl_in(in_ctrl),
				.fifo_ctrl_out(cf_out_ctrl[i]),
				

				.PL_A_DM(PL_Addr_DM),
				.PL_Data_mem_dina(PL_Data_mem_dina),
				.DM_wea(cf_DM_wea[i]),
				.PL_MEM_dout(cf_PL_MEM_dout[i]),
				

				.addrb(cf_FIFO_RD_addr[i]),
				.addra(cf_FIFO_WR_addr[i]),
				.state (cf_fifo_state[i]),
				.DEPTH (cf_DEPTH[i]),
								

				.clk(clk),
				.rst(rst)
				);
	end
endgenerate

always @ *
begin
			cf_out_rdy[0] = 'b0;
			cf_in_wr[0] = 'b0;
			cf_DM_wea[0] = 'b0;		
			cf_out_rdy[1] = 'b0;
			cf_in_wr[1] = 'b0;
			cf_DM_wea[1] = 'b0;	
			
			out_wr = cf_out_wr[0]; 
			
	case(fifo_mem_sel)
	'h0:begin


			cf_out_rdy[0] = out_rdy;
			cf_in_wr[0] = in_wr;
			in_rdy = cf_in_rdy[0];


			full = cf_full[0];			
			nearly_full = cf_nearly_full[0];
			nearly_empty = cf_nearly_empty[0];	
			empty = cf_empty[0];			
			fifo_busy = cf_fifo_busy[0];			







			cf_DM_wea[0] = DM_wea;

	end

	'h1:begin


			cf_out_rdy[1] = out_rdy;
			cf_in_wr[1] = in_wr;
			in_rdy = cf_in_rdy[1];


			full = cf_full[1];			
			nearly_full = cf_nearly_full[1];
			nearly_empty = cf_nearly_empty[1];	
			empty = cf_empty[1];			
			fifo_busy = cf_fifo_busy[1];			







			cf_DM_wea[1] = DM_wea;

	end
	
	default:begin


				cf_out_rdy[0] = out_rdy;
				cf_in_wr[0] = in_wr;
				in_rdy = cf_in_rdy[0];
				out_wr = cf_out_wr[0];

				full = cf_full[0];			
				nearly_full = cf_nearly_full[0];
				nearly_empty = cf_nearly_empty[0];	
				empty = cf_empty[0];			
				fifo_busy = cf_fifo_busy[0];			







				cf_DM_wea[0] = DM_wea;

		end
	endcase
end

always @ (fifo_mem_sel,cf_out_data [0], cf_out_ctrl [0], cf_packet_count[0], cf_FIFO_RD_addr[0], cf_FIFO_WR_addr[0],cf_fifo_state[0], cf_DEPTH[0],cf_first_word [0], cf_PL_MEM_dout [0],cf_out_data [1], cf_out_ctrl [1], cf_packet_count[1], cf_FIFO_RD_addr[1], cf_FIFO_WR_addr[1],cf_fifo_state[1], cf_DEPTH[1],cf_first_word [1], cf_PL_MEM_dout [1])
begin

	out_data = cf_out_data [0];
	out_ctrl = cf_out_ctrl [0];

	case(fifo_mem_sel)
	'h0:begin


			
			packet_count = cf_packet_count[0];			
			FIFO_RD_addr = cf_FIFO_RD_addr[0];
			FIFO_WR_addr = cf_FIFO_WR_addr[0];
			fifo_state = cf_fifo_state[0];
			DEPTH = cf_DEPTH[0];
			
			first_word = cf_first_word [0]; 
			PL_MEM_dout = cf_PL_MEM_dout [0];			
	end

	'h1:begin


			
			packet_count = cf_packet_count[1];			
			FIFO_RD_addr = cf_FIFO_RD_addr[1];
			FIFO_WR_addr = cf_FIFO_WR_addr[1];
			fifo_state = cf_fifo_state[1];
			DEPTH = cf_DEPTH[1];
			
			first_word = cf_first_word [1]; 
			PL_MEM_dout = cf_PL_MEM_dout [1];			

		end
	
	default:begin
			out_data = cf_out_data [0];
			out_ctrl = cf_out_ctrl [0];
			
			packet_count = cf_packet_count[0];			
			FIFO_RD_addr = cf_FIFO_RD_addr[0];
			FIFO_WR_addr = cf_FIFO_WR_addr[0];
			fifo_state = cf_fifo_state[0];
			DEPTH = cf_DEPTH[0];
			
			first_word = cf_first_word [0]; 
			PL_MEM_dout = cf_PL_MEM_dout [0];			
		end
	endcase


end

				
always @ * 
	begin

		PL_EN_next = 'b0;
		SW_CTRL_next = 'b0;
		R_W_EN_next = 'b1;
		fifo_rd_en_next[0] = 'b0;	
		fifo_rd_en_next[1] = 'b0;	
		fifo_wr_en_next[0] = 'b0;
		fifo_wr_en_next[1] = 'b0;
		PL_done_next = PL_done;
		fifo_sel_next = 'h0;
		counter_next = counter + 1;
									




		
		if(counter < 'h4000)
			begin
				if (PL_done & pckt_rd_wr[0] & pckt_rd_wr[1])
					begin	
						fifo_wr_en_next[0] = 'b1;
						fifo_sel_next = 'h0;
					end

				if (PL_done & !pckt_rd_wr[0] & pckt_rd_wr[1])
					begin
						fifo_wr_en_next[1] = 'b1;
						PL_done_next = pckt_rd_wr_next[1];
						fifo_sel_next = 'h1;
					end
			
					
				if (!PL_done & !pckt_rd_wr[0] & !pckt_rd_wr[1])
					begin
						PL_EN_next = 'b1;				
						PL_done_next = PL_done_raw;
					end
					
				if (PL_done & !pckt_rd_wr[0] & !pckt_rd_wr[1])
					begin	
						fifo_rd_en_next[0] = 'b1;
						fifo_sel_next = 'h0;
					end

				if (PL_done & pckt_rd_wr[0] & !pckt_rd_wr[1])
					begin
						fifo_rd_en_next[1] = 'b1;							
						fifo_sel_next = 'h1;
						counter_next = 'h0;
					end
			end
			
		else
			begin
				if (!pckt_rd_wr[0])
					begin
						fifo_rd_en_next[0] = 'b1;
						fifo_sel_next = 'h0;					
					end
				else if (!pckt_rd_wr[1])
					begin
						fifo_rd_en_next[1] = 'b1;							
						fifo_sel_next = 'h1;					
					end	
				else	counter_next = 'h0;
			end
				
		if (PL_EN)
			fifo_mem_sel = mem_sel;
		else
			fifo_mem_sel = fifo_sel;
	end

always @ (posedge clk, posedge rst)
	begin
		if (rst)
			begin
				counter <= 'h0;
				PL_EN <= 0;
				SW_CTRL <= 0;
				R_W_EN <= 1;
				fifo_rd_en[0] <= 0;
				fifo_rd_en[1] <= 0;
				fifo_wr_en[0] <= 0;
				fifo_wr_en[1] <= 0;
				PL_done <= 'h1;
				pckt_rd_wr[0] <= 'h1;
				pckt_rd_wr[1] <= 'h1;
				fifo_sel <= 'h0;
			end

		else
			begin
				counter <= counter_next;
				PL_EN <= PL_EN_next;
				SW_CTRL <= SW_CTRL_next;
				R_W_EN <= R_W_EN_next;
				fifo_rd_en[0] <= fifo_rd_en_next[0];
				fifo_rd_en[1] <= fifo_rd_en_next[1];
				fifo_wr_en[0] <= fifo_wr_en_next[0];	
				fifo_wr_en[1] <= fifo_wr_en_next[1];
				PL_done <= PL_done_next;
				pckt_rd_wr[0] <= pckt_rd_wr_next[0];
				pckt_rd_wr[1] <= pckt_rd_wr_next[1];
				fifo_sel <= fifo_sel_next;
			end

	end

endmodule
module pipeline_dualCF #(
				parameter MAX_DEPTH = 256,
				parameter ADDR_WIDTH = 8,
				parameter DATA_WIDTH = 64,
				parameter CTRL_WIDTH = DATA_WIDTH/8,
				parameter Number_of_FIFO = 2
				)
				(

				input 	[DATA_WIDTH-1:0]			in_data,
				input 	[CTRL_WIDTH-1:0]			in_ctrl,
				output 	reg [DATA_WIDTH-1:0]		out_data,
				output 	reg [CTRL_WIDTH-1:0]		out_ctrl,


				input 								out_rdy,
				input 								in_wr,
				output reg							in_rdy,
				output reg							out_wr,
				

				input								IorD,
				input	[8:0]						Addr_in,
				input [DATA_WIDTH-1:0]				Data_In,
				

				output	[8:0]						Addr_DM,
				output	[8:0]						Addr_IM,		
				output	[31:0]						Data_out_IM,
				output	[DATA_WIDTH-1:0]			Data_out_DM,
				output 	reg							full,
				output 	reg							nearly_full,
				output 	reg							nearly_empty,
				output 	reg							empty,			
				output	reg							fifo_busy,			
				output 	reg [1:0]					packet_count,			
				output 	reg [ADDR_WIDTH-1:0]		FIFO_RD_addr,
				output 	reg [ADDR_WIDTH-1:0]		FIFO_WR_addr,
				output	reg [1:0]					fifo_state,
				output	reg [ADDR_WIDTH:0]			DEPTH,
				output	reg							PL_EN,
				output	reg							SW_CTRL,
				output	reg	[Number_of_FIFO-1:0]	fifo_rd_en,
				output	reg	[Number_of_FIFO-1:0]	fifo_wr_en,
				

				output reg 	[Number_of_FIFO-1:0]	Master_reg,
				

				input clk,
				input rst
				);


				




reg PL_EN_next;
reg SW_CTRL_next;
reg R_W_EN,R_W_EN_next;
reg [15:0] counter,counter_next;


wire DM_wea;
wire [DATA_WIDTH-1:0] PL_Data_mem_dina;
reg [DATA_WIDTH-1:0] PL_MEM_dout;
wire [ADDR_WIDTH-1:0] PL_Addr_DM;		
reg PL_done_next;
wire PL_done_raw;
reg PL_done;



wire [DATA_WIDTH-1:0] EX_ALU_in1,EX_ALU_in2;


wire [DATA_WIDTH-1:0] EX_ALU_out;



wire [3:0] ALUop,EX_ALUop;
wire RegWrite,MemWrite, MemtoReg, Jump, ble, PL_done_ctrl, FW_ld;
reg [log2(Number_of_FIFO)-1:0] fifo_mem_sel;
reg [log2(Number_of_FIFO)-1:0] fifo_sel, fifo_sel_next;
wire [log2(Number_of_FIFO)-1:0] mem_sel;




reg [Number_of_FIFO-1:0] fifo_rd_en_next;
reg [Number_of_FIFO-1:0] fifo_wr_en_next;


reg [ADDR_WIDTH-1:0] first_word; 
	

wire [Number_of_FIFO-1:0] pckt_rd_wr_next;
reg [Number_of_FIFO-1:0] pckt_rd_wr;



wire [DATA_WIDTH-1:0] cf_out_data [Number_of_FIFO-1:0];
wire [CTRL_WIDTH-1:0] cf_out_ctrl [Number_of_FIFO-1:0];
reg [Number_of_FIFO-1:0] cf_out_rdy;
reg [Number_of_FIFO-1:0] cf_in_wr;
wire [Number_of_FIFO-1:0] cf_in_rdy;
wire [Number_of_FIFO-1:0] cf_out_wr;

wire [Number_of_FIFO-1:0] cf_full;
wire [Number_of_FIFO-1:0] cf_nearly_full;	
wire [Number_of_FIFO-1:0] cf_nearly_empty;	
wire [Number_of_FIFO-1:0] cf_empty;			
wire [Number_of_FIFO-1:0] cf_fifo_busy;			
wire [1:0] cf_packet_count [Number_of_FIFO-1:0];			
wire [ADDR_WIDTH-1:0] cf_FIFO_RD_addr [Number_of_FIFO-1:0];
wire [ADDR_WIDTH-1:0] cf_FIFO_WR_addr [Number_of_FIFO-1:0];
wire [1:0] cf_fifo_state [Number_of_FIFO-1:0];
wire [ADDR_WIDTH:0] cf_DEPTH [Number_of_FIFO-1:0];
wire [ADDR_WIDTH-1:0] cf_first_word [Number_of_FIFO-1:0]; 

reg [Number_of_FIFO-1:0] cf_DM_wea;
wire [DATA_WIDTH-1:0] cf_PL_MEM_dout [Number_of_FIFO-1:0];


  function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction
		
datapath dp		(
				 .clk(clk),
				 .rst(rst),


				 .pipeline_en(PL_EN),
				 .sw_ctrl(SW_CTRL),
				 .IorD(IorD),
				 .WorR(R_W_EN),
				 .MEM_PL_done(PL_done_raw),
				 

				 .Addr_in(Addr_in),
				 .Data_in(Data_In),
				 .IM_Addr_out(Addr_IM),
				 .DM_Addr_out(Addr_DM),
				 .IM_Data_out(Data_out_IM),
				 .DM_Data_out(Data_out_DM),
				 

				 .Data_mem_wea (DM_wea),
				 .Data_mem_dina (PL_Data_mem_dina),
				 .Data_mem_addr (PL_Addr_DM), 
				 .MEM_Dout(PL_MEM_dout),
				 .first_word(first_word),

				 

				 .EX_ALU_in1(EX_ALU_in1),
				 .EX_ALU_in2(EX_ALU_in2),
				 .EX_ALU_out(EX_ALU_out),
				 .EX_ALUop(EX_ALUop),
				 

				 .RegWrite(RegWrite),
				 .ALUSrc(ALUSrc),
				 .MemWrite(MemWrite),
				 .MemtoReg(MemtoReg),	
				 .Jump(Jump),	
				 .ble(ble),	
				 .imme(imme),
				 .ALUop(ALUop),
				 .PL_done(PL_done_ctrl),
				 .FW_ld (FW_ld)
				);

ALU_ctrl EX_ALU (
				.A(EX_ALU_in1),
				.B(EX_ALU_in2),
				.cmd(EX_ALUop),					
				.psw(),
				.Data_out(EX_ALU_out)
				);
				
control ctrl	(
				.instruction(Data_out_IM),
				.RegWrite(RegWrite),
				.ALUSrc(ALUSrc),
				.MemWrite(MemWrite),
				.MemtoReg(MemtoReg),	
				.Jump(Jump),	
				.ble(ble),	
				.imme(imme), 
				.PL_done(PL_done_ctrl),
				.FW_ld (FW_ld),
				.ALUop(ALUop),
				.Master_reg(),
				.mem_sel(mem_sel)
				);
				

genvar i;
generate
	for (i=0 ; i<Number_of_FIFO ; i = i+1)
	begin: CF
convert_fifo fifo_dm  (
				.fifo_rd_en(fifo_rd_en[i]), 
				.fifo_wr_en(fifo_wr_en[i]),
				.out_rdy(cf_out_rdy[i]), 
				.in_wr(cf_in_wr[i]),
				.out_wr(cf_out_wr[i]),
				.pckt_rd_wr(pckt_rd_wr_next[i]),
				

				.in_rdy(cf_in_rdy[i]),
				.full(cf_full[i]),
				.empty(cf_empty[i]), 
				.nearly_full(cf_nearly_full[i]), 
				.nearly_empty(cf_nearly_empty[i]),
				.packet_count(cf_packet_count[i]),
				.first_word(cf_first_word[i]),
				.last_word(),
				.fifo_busy(cf_fifo_busy[i]),
				


				.fifo_data_in(in_data),
				.fifo_data_out(cf_out_data[i]),
				.fifo_ctrl_in(in_ctrl),
				.fifo_ctrl_out(cf_out_ctrl[i]),
				

				.PL_A_DM(PL_Addr_DM),
				.PL_Data_mem_dina(PL_Data_mem_dina),
				.DM_wea(cf_DM_wea[i]),
				.PL_MEM_dout(cf_PL_MEM_dout[i]),
				

				.addrb(cf_FIFO_RD_addr[i]),
				.addra(cf_FIFO_WR_addr[i]),
				.state (cf_fifo_state[i]),
				.DEPTH (cf_DEPTH[i]),
								

				.clk(clk),
				.rst(rst)
				);
	end
endgenerate

always @ *
begin
			cf_out_rdy[0] = 'b0;
			cf_in_wr[0] = 'b0;
			cf_DM_wea[0] = 'b0;		
			cf_out_rdy[1] = 'b0;
			cf_in_wr[1] = 'b0;
			cf_DM_wea[1] = 'b0;	
			
			out_wr = cf_out_wr[0]; 
			
	case(fifo_mem_sel)
	'h0:begin


			cf_out_rdy[0] = out_rdy;
			cf_in_wr[0] = in_wr;
			in_rdy = cf_in_rdy[0];


			full = cf_full[0];			
			nearly_full = cf_nearly_full[0];
			nearly_empty = cf_nearly_empty[0];	
			empty = cf_empty[0];			
			fifo_busy = cf_fifo_busy[0];			







			cf_DM_wea[0] = DM_wea;

	end

	'h1:begin


			cf_out_rdy[1] = out_rdy;
			cf_in_wr[1] = in_wr;
			in_rdy = cf_in_rdy[1];


			full = cf_full[1];			
			nearly_full = cf_nearly_full[1];
			nearly_empty = cf_nearly_empty[1];	
			empty = cf_empty[1];			
			fifo_busy = cf_fifo_busy[1];			







			cf_DM_wea[1] = DM_wea;

	end
	
	default:begin


				cf_out_rdy[0] = out_rdy;
				cf_in_wr[0] = in_wr;
				in_rdy = cf_in_rdy[0];
				out_wr = cf_out_wr[0];

				full = cf_full[0];			
				nearly_full = cf_nearly_full[0];
				nearly_empty = cf_nearly_empty[0];	
				empty = cf_empty[0];			
				fifo_busy = cf_fifo_busy[0];			







				cf_DM_wea[0] = DM_wea;

		end
	endcase
end

always @ (fifo_mem_sel,cf_out_data [0], cf_out_ctrl [0], cf_packet_count[0], cf_FIFO_RD_addr[0], cf_FIFO_WR_addr[0],cf_fifo_state[0], cf_DEPTH[0],cf_first_word [0], cf_PL_MEM_dout [0],cf_out_data [1], cf_out_ctrl [1], cf_packet_count[1], cf_FIFO_RD_addr[1], cf_FIFO_WR_addr[1],cf_fifo_state[1], cf_DEPTH[1],cf_first_word [1], cf_PL_MEM_dout [1])
begin

	out_data = cf_out_data [0];
	out_ctrl = cf_out_ctrl [0];

	case(fifo_mem_sel)
	'h0:begin


			
			packet_count = cf_packet_count[0];			
			FIFO_RD_addr = cf_FIFO_RD_addr[0];
			FIFO_WR_addr = cf_FIFO_WR_addr[0];
			fifo_state = cf_fifo_state[0];
			DEPTH = cf_DEPTH[0];
			
			first_word = cf_first_word [0]; 
			PL_MEM_dout = cf_PL_MEM_dout [0];			
	end

	'h1:begin


			
			packet_count = cf_packet_count[1];			
			FIFO_RD_addr = cf_FIFO_RD_addr[1];
			FIFO_WR_addr = cf_FIFO_WR_addr[1];
			fifo_state = cf_fifo_state[1];
			DEPTH = cf_DEPTH[1];
			
			first_word = cf_first_word [1]; 
			PL_MEM_dout = cf_PL_MEM_dout [1];			

		end
	
	default:begin
			out_data = cf_out_data [0];
			out_ctrl = cf_out_ctrl [0];
			
			packet_count = cf_packet_count[0];			
			FIFO_RD_addr = cf_FIFO_RD_addr[0];
			FIFO_WR_addr = cf_FIFO_WR_addr[0];
			fifo_state = cf_fifo_state[0];
			DEPTH = cf_DEPTH[0];
			
			first_word = cf_first_word [0]; 
			PL_MEM_dout = cf_PL_MEM_dout [0];			
		end
	endcase


end

				
always @ * 
	begin

		PL_EN_next = 'b0;
		SW_CTRL_next = 'b0;
		R_W_EN_next = 'b1;
		fifo_rd_en_next[0] = 'b0;	
		fifo_rd_en_next[1] = 'b0;	
		fifo_wr_en_next[0] = 'b0;
		fifo_wr_en_next[1] = 'b0;
		PL_done_next = PL_done;
		fifo_sel_next = 'h0;
		counter_next = counter + 1;
									




		
		if(counter < 'h4000)
			begin
				if (PL_done & pckt_rd_wr[0] & pckt_rd_wr[1])
					begin	
						fifo_wr_en_next[0] = 'b1;
						fifo_sel_next = 'h0;
					end

				if (PL_done & !pckt_rd_wr[0] & pckt_rd_wr[1])
					begin
						fifo_wr_en_next[1] = 'b1;
						PL_done_next = pckt_rd_wr_next[1];
						fifo_sel_next = 'h1;
					end
			
					
				if (!PL_done & !pckt_rd_wr[0] & !pckt_rd_wr[1])
					begin
						PL_EN_next = 'b1;				
						PL_done_next = PL_done_raw;
					end
					
				if (PL_done & !pckt_rd_wr[0] & !pckt_rd_wr[1])
					begin	
						fifo_rd_en_next[0] = 'b1;
						fifo_sel_next = 'h0;
					end

				if (PL_done & pckt_rd_wr[0] & !pckt_rd_wr[1])
					begin
						fifo_rd_en_next[1] = 'b1;							
						fifo_sel_next = 'h1;
						counter_next = 'h0;
					end
			end
			
		else
			begin
				if (!pckt_rd_wr[0])
					begin
						fifo_rd_en_next[0] = 'b1;
						fifo_sel_next = 'h0;					
					end
				else if (!pckt_rd_wr[1])
					begin
						fifo_rd_en_next[1] = 'b1;							
						fifo_sel_next = 'h1;					
					end	
				else	counter_next = 'h0;
			end
				
		if (PL_EN)
			fifo_mem_sel = mem_sel;
		else
			fifo_mem_sel = fifo_sel;
	end

always @ (posedge clk, posedge rst)
	begin
		if (rst)
			begin
				counter <= 'h0;
				PL_EN <= 0;
				SW_CTRL <= 0;
				R_W_EN <= 1;
				fifo_rd_en[0] <= 0;
				fifo_rd_en[1] <= 0;
				fifo_wr_en[0] <= 0;
				fifo_wr_en[1] <= 0;
				PL_done <= 'h1;
				pckt_rd_wr[0] <= 'h1;
				pckt_rd_wr[1] <= 'h1;
				fifo_sel <= 'h0;
			end

		else
			begin
				counter <= counter_next;
				PL_EN <= PL_EN_next;
				SW_CTRL <= SW_CTRL_next;
				R_W_EN <= R_W_EN_next;
				fifo_rd_en[0] <= fifo_rd_en_next[0];
				fifo_rd_en[1] <= fifo_rd_en_next[1];
				fifo_wr_en[0] <= fifo_wr_en_next[0];	
				fifo_wr_en[1] <= fifo_wr_en_next[1];
				PL_done <= PL_done_next;
				pckt_rd_wr[0] <= pckt_rd_wr_next[0];
				pckt_rd_wr[1] <= pckt_rd_wr_next[1];
				fifo_sel <= fifo_sel_next;
			end

	end

endmodule