data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/16f29252-be16-4001-836e-3f017940db91.xml
module or2(
  a,
  b,
  c);

input wire a;
input wire b;
output wire c;

assign c = a | b;

endmodule
module or2(
  a,
  b,
  c);


input wire a;
input wire b;
output wire c;

assign c = a | b;

endmodule