data/full_repos/permissive/178917770/design.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/178917770/design.v:237: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'flopenr\'\nmodule flopenr #(parameter WIDTH = 4)\n       ^~~~~~~\n                                                                    : ... Top module \'processor\'\nmodule processor(input clk, reset,\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/178917770/design.v:250: Duplicate declaration of signal: \'MemWrite\'\n                                                         : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire MemToReg, MemWrite, RegWrite, ALUSrc, J, initRd;\n                   ^~~~~~~~\n        data/full_repos/permissive/178917770/design.v:240: ... Location of original declaration\n                 output MemWrite,BeqFlag,\n                        ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module processor(input clk, reset,
                 output [7:0] PC,
                 input [10:0] Instr,
                 output MemWrite,BeqFlag,
                 output [3:0] ALUResult,WriteData,
                 input [3:0] ReadData,
                 output [1:0] ALUControl,
                 output  [1:0] AdrRd,
                 output [1:0] AdrRa,
                 output  [1:0] AdrRb,
                output Beq);
  

    wire MemToReg, MemWrite, RegWrite, ALUSrc, J, initRd;



  wire  [3:0] imm;
  wire [6:0] Adr;

  
  controlUnit cu(.Instr(Instr), .BeqFlag(BeqFlag),.AdrRd(AdrRd),.AdrRa(AdrRa), .AdrRb(AdrRb),.imm(imm),.Adr(Adr),.ALUControl(ALUControl),.MemToReg(MemToReg), .MemWrite(MemWrite), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .J(J), .Beq(Beq), .initRd(initRd) );
    
  datapath dp( .clk(clk),.reset(reset),.BeqFlag(BeqFlag),.AdrRd(AdrRd), .AdrRa(AdrRa), .AdrRb(AdrRb), .imm(imm), .Adr(Adr), .ALUControl(ALUControl), .MemToReg(MemToReg), .MemWrite(MemWrite), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .J(J), .Beq(Beq), .PC(PC), .ALUResult(ALUResult), .WriteData(WriteData), .ReadData(ReadData) ,.initRd(initRd));
    
  endmodule
module processor(input clk, reset,
                 output [7:0] PC,
                 input [10:0] Instr,
                 output MemWrite,BeqFlag,
                 output [3:0] ALUResult,WriteData,
                 input [3:0] ReadData,
                 output [1:0] ALUControl,
                 output  [1:0] AdrRd,
                 output [1:0] AdrRa,
                 output  [1:0] AdrRb,
                output Beq);

  

    wire MemToReg, MemWrite, RegWrite, ALUSrc, J, initRd;



  wire  [3:0] imm;
  wire [6:0] Adr;

  
  controlUnit cu(.Instr(Instr), .BeqFlag(BeqFlag),.AdrRd(AdrRd),.AdrRa(AdrRa), .AdrRb(AdrRb),.imm(imm),.Adr(Adr),.ALUControl(ALUControl),.MemToReg(MemToReg), .MemWrite(MemWrite), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .J(J), .Beq(Beq), .initRd(initRd) );
    
  datapath dp( .clk(clk),.reset(reset),.BeqFlag(BeqFlag),.AdrRd(AdrRd), .AdrRa(AdrRa), .AdrRb(AdrRb), .imm(imm), .Adr(Adr), .ALUControl(ALUControl), .MemToReg(MemToReg), .MemWrite(MemWrite), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .J(J), .Beq(Beq), .PC(PC), .ALUResult(ALUResult), .WriteData(WriteData), .ReadData(ReadData) ,.initRd(initRd));
    
  endmodule