data/full_repos/permissive/200104480/Processor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:440: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'singleBit\' generates 1 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.A.ze\n assign dataOut = 32\'b0 + singleBit;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:361: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'dataIn\' generates 16 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.ZE\n assign dataOut = 32\'b0 + dataIn;\n                        ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegFile(input CLK,
			input WE3,
			input [4:0] A1,
			input [4:0] A2,
			input [4:0] A3,
			input [31:0] WD3,
			output reg [31:0] RD1,
			output reg [31:0] RD2);
			
	reg [31:0] gpreg [0:31];
	reg [31:0] i;
	
	initial
	begin
		for (i=0; i<32; i=i+1)
		begin
			gpreg[i] <= 32'b0;
		end
	end
	
	always @(*)
	begin
		RD1 <= gpreg[A1];
		RD2 <= gpreg[A2];
	end
	
	always @(negedge CLK)
	begin
		if (WE3 == 1'b1)
		begin
				gpreg[A3] <= WD3;
		end
	end
endmodule
module RegFile(input CLK,
			input WE3,
			input [4:0] A1,
			input [4:0] A2,
			input [4:0] A3,
			input [31:0] WD3,
			output reg [31:0] RD1,
			output reg [31:0] RD2);

			
	reg [31:0] gpreg [0:31];
	reg [31:0] i;
	
	initial
	begin
		for (i=0; i<32; i=i+1)
		begin
			gpreg[i] <= 32'b0;
		end
	end
	
	always @(*)
	begin
		RD1 <= gpreg[A1];
		RD2 <= gpreg[A2];
	end
	
	always @(negedge CLK)
	begin
		if (WE3 == 1'b1)
		begin
				gpreg[A3] <= WD3;
		end
	end
endmodule