data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test.v
 line:56: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test.v:56: Unsupported: Ignoring delay on this delayed statement.\n    always #5 begin\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sim_1/new/test.v:66: syntax error, unexpected \'@\'\n                @(posedge clk)\n                ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();
    reg clk, rst;

	reg [10:0] aux;
	reg [4:0] r1_index;
	reg [4:0] r2_index;
	reg [4:0] w_index;
	wire [31:0] r1_data;
	wire [31:0] r2_data;
	reg [31:0] w_data;
	wire [31:0] result;

	register r(
		.clk(clk), .rst(rst),
		.r1_index(r1_index), .r1_data(r1_data),
		.r2_index(r2_index), .r2_data(r2_data),
		.w_index(w_index), .w_data(w_data));
	alu al(
		.clk(clk), .aux(aux),
		.ra(r1_data),
		.rb(r2_data),
		.rc(result));

    initial begin
		clk <= 0;
		rst <= 0;
		aux <= 0;
        r1_index <= 0;
        r2_index <= 0;
        w_index <= 0;
        w_data <= 0;
    end

    always #5 begin
        clk <= ~clk;
    end

    task wait_posedge_clk;
        input   n;
        integer n;

        begin
            for(n=n; n>0; n=n-1) begin
                @(posedge clk)
                    ;
            end
        end
    endtask

	initial begin
		wait_posedge_clk(1);
		rst <= 1;
		wait_posedge_clk(1);
		rst <= 0;
		wait_posedge_clk(4);
		w_index <= 3;
		w_data <= 14;
		wait_posedge_clk(1);
		w_index <= 4;
		w_data <= 11;
		wait_posedge_clk(4);
		w_index <= 0;
		w_data <= 0;
		r1_index <= 3;
		r2_index <= 4;
		wait_posedge_clk(4);
        aux <= 2;
		wait_posedge_clk(4);

		$finish;
	end

endmodule
module test();

    reg clk, rst;

	reg [10:0] aux;
	reg [4:0] r1_index;
	reg [4:0] r2_index;
	reg [4:0] w_index;
	wire [31:0] r1_data;
	wire [31:0] r2_data;
	reg [31:0] w_data;
	wire [31:0] result;

	register r(
		.clk(clk), .rst(rst),
		.r1_index(r1_index), .r1_data(r1_data),
		.r2_index(r2_index), .r2_data(r2_data),
		.w_index(w_index), .w_data(w_data));
	alu al(
		.clk(clk), .aux(aux),
		.ra(r1_data),
		.rb(r2_data),
		.rc(result));

    initial begin
		clk <= 0;
		rst <= 0;
		aux <= 0;
        r1_index <= 0;
        r2_index <= 0;
        w_index <= 0;
        w_data <= 0;
    end

    always #5 begin
        clk <= ~clk;
    end

    task wait_posedge_clk;
        input   n;
        integer n;

        begin
            for(n=n; n>0; n=n-1) begin
                @(posedge clk)
                    ;
            end
        end
    endtask

	initial begin
		wait_posedge_clk(1);
		rst <= 1;
		wait_posedge_clk(1);
		rst <= 0;
		wait_posedge_clk(4);
		w_index <= 3;
		w_data <= 14;
		wait_posedge_clk(1);
		w_index <= 4;
		w_data <= 11;
		wait_posedge_clk(4);
		w_index <= 0;
		w_data <= 0;
		r1_index <= 3;
		r2_index <= 4;
		wait_posedge_clk(4);
        aux <= 2;
		wait_posedge_clk(4);

		$finish;
	end

endmodule