data/full_repos/permissive/123690745/EXMEM.v
 line:29: before: "="
data/verilator_xmls/4ca37705-b5c4-49e7-8987-c9edf82104a2.xml
module EXMEM(
	 input InterruptRequest,
	 input clk, input reset,
	 input [4:0] RdE,
    input [31:0] ALUOutE,
    input [31:0] WriteDataE,
    input [4:0] WriteRegE,
	 output reg [4:0] RdM, 
    output reg [31:0] ALUOutM = 0,
    output reg [31:0] WriteDataM = 0,
    output reg [4:0] WriteRegM = 0,
	 input [31:0] InstrE,
	 output reg [31:0] InstrM = 0
    );
	always @(posedge clk) begin
		if (reset || InterruptRequest) begin
			ALUOutM <= 0;
			WriteDataM <= 0;
			WriteRegM <= 0;
			InstrM <= 0;
			RdM <= 0;
		end
		else begin
			ALUOutM <= ALUOutE;
			WriteDataM <= WriteDataE;
			WriteRegM <= WriteRegE;
			InstrM <= InstrE;
			RdM <= RdE;
		end
	end

endmodule
module EXMEM(
	 input InterruptRequest,
	 input clk, input reset,
	 input [4:0] RdE,
    input [31:0] ALUOutE,
    input [31:0] WriteDataE,
    input [4:0] WriteRegE,
	 output reg [4:0] RdM, 
    output reg [31:0] ALUOutM = 0,
    output reg [31:0] WriteDataM = 0,
    output reg [4:0] WriteRegM = 0,
	 input [31:0] InstrE,
	 output reg [31:0] InstrM = 0
    );

	always @(posedge clk) begin
		if (reset || InterruptRequest) begin
			ALUOutM <= 0;
			WriteDataM <= 0;
			WriteRegM <= 0;
			InstrM <= 0;
			RdM <= 0;
		end
		else begin
			ALUOutM <= ALUOutE;
			WriteDataM <= WriteDataE;
			WriteRegM <= WriteRegE;
			InstrM <= InstrE;
			RdM <= RdE;
		end
	end

endmodule