data/full_repos/permissive/169258653/components/sl2/sl2.srcs/sources_1/new/sl2.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/169258653/components/sl2/sl2.srcs/sources_1/new/sl2.v:29: Signal definition not found, creating implicitly: \'y\'\n    assign y={in[29:0], 2\'b00};\n           ^\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169258653/components/sl2/sl2.srcs/sources_1/new/sl2.v:29: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                   : ... In instance sl2\n    assign y={in[29:0], 2\'b00};\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module sl2(
    input [31:0] in,
    output [31:0] out
    );
    

    assign y={in[29:0], 2'b00};
    
endmodule
module sl2(
    input [31:0] in,
    output [31:0] out
    );

    

    assign y={in[29:0], 2'b00};
    
endmodule