data/full_repos/permissive/162672365/Adder.v
data/verilator_xmls/fbe7f381-9c5d-417b-8dbc-a02327e27a4f.xml
module eightBitFullAdder(sum, carry, in1, in2, cin);
	input [7:0] in1, in2;
	input cin;
	output [7:0] sum;
	output carry;
	wire caux;
	
	fourBitFullAdder fbfa1(sum[3:0], caux, in1[3:0], in2[3:0], cin);
	fourBitFullAdder fbfa2(sum[7:4], carry, in1[7:4], in2[7:4], caux);
	
endmodule
module eightBitFullAdder(sum, carry, in1, in2, cin);

	input [7:0] in1, in2;
	input cin;
	output [7:0] sum;
	output carry;
	wire caux;
	
	fourBitFullAdder fbfa1(sum[3:0], caux, in1[3:0], in2[3:0], cin);
	fourBitFullAdder fbfa2(sum[7:4], carry, in1[7:4], in2[7:4], caux);
	
endmodule