data/full_repos/permissive/125520060/problem-1004-mux2_4/tb_top.v
 line:20: before: "$"
1: b'%Error: data/full_repos/permissive/125520060/problem-1004-mux2_4/tb_top.v:10: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("wave.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/125520060/problem-1004-mux2_4/tb_top.v:11: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, u_mux2_4);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/125520060/problem-1004-mux2_4/tb_top.v:13: Unsupported or unknown PLI call: $monitor\n    $monitor("Time = %3d, a = %b, b = %b, sel = %b, q = %b",\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125520060/problem-1004-mux2_4/tb_top.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #10 a = 4\'b1110; b = 4\'b0001;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125520060/problem-1004-mux2_4/tb_top.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10 a = 4\'b1101; b = 4\'b0010; sel = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/125520060/problem-1004-mux2_4/tb_top.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10 a = 4\'b1100; b = 4\'b0011;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/125520060/problem-1004-mux2_4/tb_top.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mux2_4();

reg     [3:0]   a, b;
reg             sel;
wire    [3:0]   q;

mux2_4 u_mux2_4(a, b, sel, q);

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(1, u_mux2_4);

    $monitor("Time = %3d, a = %b, b = %b, sel = %b, q = %b",
             $time, a, b, sel, q);

        a = 4'b1111; b = 4'b0000; sel = 1;
    #10 a = 4'b1110; b = 4'b0001;
    #10 a = 4'b1101; b = 4'b0010; sel = 0;
    #10 a = 4'b1100; b = 4'b0011;
    #10 $finish;
end

endmodule
module tb_mux2_4();


reg     [3:0]   a, b;
reg             sel;
wire    [3:0]   q;

mux2_4 u_mux2_4(a, b, sel, q);

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(1, u_mux2_4);

    $monitor("Time = %3d, a = %b, b = %b, sel = %b, q = %b",
             $time, a, b, sel, q);

        a = 4'b1111; b = 4'b0000; sel = 1;
    #10 a = 4'b1110; b = 4'b0001;
    #10 a = 4'b1101; b = 4'b0010; sel = 0;
    #10 a = 4'b1100; b = 4'b0011;
    #10 $finish;
end

endmodule