data/full_repos/permissive/122924576/stack.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/122924576/stack.v:21: Bit extraction of array[63:0] requires 6 bit index, not 7 bits.\n                                                               : ... In instance stack\n   mem[sp] = d_in;\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module stack(reset, d_in, push, pop, clk, d_out, of, uf, empty);	
	parameter depth=21;
	parameter stack_depth=6;
	
	input[depth:0] d_in;
	input reset, push, pop, clk;
	output [depth:0] d_out;
	output reg of=0 ,uf=0;
	output empty;
	
	reg [stack_depth:0]sp;
	reg [depth:0] mem [(1<<stack_depth)-1:0];
	assign d_out[depth:0]  = mem [sp-1];
	assign empty = (sp==0);
	
	always @(posedge clk) begin
		if(reset) begin
			sp = 0;
		end
		else if(push) begin
			mem[sp] = d_in;
			if(sp==((1<<stack_depth)-1))
			  of = 1;
			else begin	
			  sp = sp + 1;
			  uf = 0;
			end
		end
		else if(pop) begin
		  if(sp==0)
		    uf = 1;
		  else begin
		    sp = sp - 1;
		    of = 0;
		  end
		end
	end
endmodule
module stack(reset, d_in, push, pop, clk, d_out, of, uf, empty);
	
	parameter depth=21;
	parameter stack_depth=6;
	
	input[depth:0] d_in;
	input reset, push, pop, clk;
	output [depth:0] d_out;
	output reg of=0 ,uf=0;
	output empty;
	
	reg [stack_depth:0]sp;
	reg [depth:0] mem [(1<<stack_depth)-1:0];
	assign d_out[depth:0]  = mem [sp-1];
	assign empty = (sp==0);
	
	always @(posedge clk) begin
		if(reset) begin
			sp = 0;
		end
		else if(push) begin
			mem[sp] = d_in;
			if(sp==((1<<stack_depth)-1))
			  of = 1;
			else begin	
			  sp = sp + 1;
			  uf = 0;
			end
		end
		else if(pop) begin
		  if(sp==0)
		    uf = 1;
		  else begin
		    sp = sp - 1;
		    of = 0;
		  end
		end
	end
endmodule