data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-3_alu/alu_tb.v
1: b'%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-3_alu/alu_tb.v:54: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("alu_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-3_alu/alu_tb.v:55: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-3_alu/alu_tb.v:72: Unsupported or unknown PLI call: $monitor\n        $monitor("%b (%d)  %b (%d)   %b (%d)  %b",\n        ^~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-3_alu/alu_tb.v:84: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n        a = $random(seed);\n            ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-3_alu/alu_tb.v:84: ../V3Ast.cpp:358: Null item passed to setOp1p\n        a = $random(seed);\n          ^\n                        ... See the manual and https://verilator.org for more assistance.\n'
module test ();

    reg signed [7:0] a;
    reg signed [7:0] b;
    reg [2:0] op = `OP;
    wire signed [7:0] f;
    wire ov;
    integer np;
    integer seed = `SEED;



    alu #(.WIDTH(8)) uut(.a(a), .b(b), .op(op), .f(f), .ov(ov));

    initial begin

        np = `NP;


        $dumpfile("alu_tb.vcd");
        $dumpvars(0, test);


        $write("Operacion: %d ", op);
        case (op)
        0:       $display("SUMA");
        1:       $display("RESTA");
        2:       $display("INCREMENTO");
        3:       $display("DECREMENTO");
        4:       $display("AND");
        5:       $display("OR");
        6:       $display("XOR");
        default: $display("NOT");
        endcase

        $display("       A                B",
                 "                 F         ov");
        $monitor("%b (%d)  %b (%d)   %b (%d)  %b",
                   a, a, b, b, f, f, ov);
    end



    always begin
        #20
        a = $random(seed);
        b = $random(seed);
        np = np - 1;
        if (np == 0)
            $finish;
    end
endmodule
module test ();


    reg signed [7:0] a;
    reg signed [7:0] b;
    reg [2:0] op = `OP;
    wire signed [7:0] f;
    wire ov;
    integer np;
    integer seed = `SEED;



    alu #(.WIDTH(8)) uut(.a(a), .b(b), .op(op), .f(f), .ov(ov));

    initial begin

        np = `NP;


        $dumpfile("alu_tb.vcd");
        $dumpvars(0, test);


        $write("Operacion: %d ", op);
        case (op)
        0:       $display("SUMA");
        1:       $display("RESTA");
        2:       $display("INCREMENTO");
        3:       $display("DECREMENTO");
        4:       $display("AND");
        5:       $display("OR");
        6:       $display("XOR");
        default: $display("NOT");
        endcase

        $display("       A                B",
                 "                 F         ov");
        $monitor("%b (%d)  %b (%d)   %b (%d)  %b",
                   a, a, b, b, f, f, ov);
    end



    always begin
        #20
        a = $random(seed);
        b = $random(seed);
        np = np - 1;
        if (np == 0)
            $finish;
    end
endmodule