data/full_repos/permissive/128659832/verilog/mem_wrapper.v
 line:42: before: "."
1: b"%Error: data/full_repos/permissive/128659832/verilog/mem_wrapper.v:33: Cannot find file containing module: 'ram'\n    ram #( .addr_width( 8 ), .data_width( 8 ) ) ram0 (\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/128659832/verilog,data/full_repos/permissive/128659832/ram\n             data/full_repos/permissive/128659832/verilog,data/full_repos/permissive/128659832/ram.v\n             data/full_repos/permissive/128659832/verilog,data/full_repos/permissive/128659832/ram.sv\n             ram\n             ram.v\n             ram.sv\n             obj_dir/ram\n             obj_dir/ram.v\n             obj_dir/ram.sv\n%Error: data/full_repos/permissive/128659832/verilog/mem_wrapper.v:50: Cannot find file containing module: 'XALU'\n    XALU #( .BASE_ADDR( 8'h00 ), .data_width( 8 ) ) xalu0 (\n    ^~~~\n%Error: data/full_repos/permissive/128659832/verilog/mem_wrapper.v:65: Cannot find file containing module: 'LEDS'\n    LEDS #( .BASE_ADDR( 8'h10 ), .data_width( 8 ) ) leds0 (\n    ^~~~\n%Error: data/full_repos/permissive/128659832/verilog/mem_wrapper.v:79: Cannot find file containing module: 'RAND'\n    RAND rand0 (\n    ^~~~\n%Error: Exiting due to 4 error(s)\n"
module mem_wrapper #(
        parameter data_width = 8,
        parameter addr_width=8
    ) (
        input  wire                  clk,
        input  wire [addr_width-1:0] addr,
        input  wire [data_width-1:0] din,
        input  wire                  write_en,
        input  wire                  mmio,
        input  wire                  rst,
        output reg  [data_width-1:0] dout,
        output reg  [7:0]            o_leds
    );

`ifdef MMIO_SUPPORT
    wire cs_RAM0 = ~mmio;
    wire cs_XALU =  mmio & ( addr[7:4] == 4'h0 );
    wire cs_LEDS =  mmio & ( addr == 8'h10 );
    wire cs_RAND =  mmio & ( addr == 8'h11 );
`else
    wire cs_RAM0 = 1'b 1;
`endif




    parameter ROMFILE = "";

    wire [data_width-1:0] ram0_dout;
    ram #( .addr_width( 8 ), .data_width( 8 ) ) ram0 (

        .clk( clk ),
        .addr( addr ),
        .dout( ram0_dout ),

        .write_en( write_en & cs_RAM0 ),
        .din( din )
    );
    defparam ram0.ROMFILE = ROMFILE;


`ifdef MMIO_SUPPORT



    wire [data_width-1:0] xalu_dout;
    XALU #( .BASE_ADDR( 8'h00 ), .data_width( 8 ) ) xalu0 (
        .clk( clk ),
        .addr( addr ),
        .dout( xalu_dout ),
        .write_en( write_en & cs_XALU ),
        .din( din ),
        .rst( rst )
    );






    wire [data_width-1:0] leds_dout;
    LEDS #( .BASE_ADDR( 8'h10 ), .data_width( 8 ) ) leds0 (
        .clk( clk ),
        .addr( addr ),
        .dout( leds_dout ),
        .write_en( write_en & cs_LEDS ),
        .din( din ),
        .rst( rst )
    );





    wire [data_width-1:0] rand_dout;
    RAND rand0 (
        .clk( clk ),
        .addr( addr ),
        .dout( rand_dout ),
        .write_en( write_en & cs_RAND ),
        .din( din ),
        .rst( rst )
    );

`endif



    always @*
    begin
        case (1'b1)
            cs_RAM0: dout = ram0_dout;
`ifdef MMIO_SUPPORT
            cs_XALU: dout = xalu_dout;
            cs_LEDS: dout = leds_dout;
            cs_RAND: dout = rand_dout;
`endif

            default: dout = {(data_width){1'b 0}};
        endcase

`ifdef MMIO_SUPPORT
        o_leds = leds_dout;
`else
        o_leds = 8'b 0;
`endif
    end


endmodule
module mem_wrapper #(
        parameter data_width = 8,
        parameter addr_width=8
    ) (
        input  wire                  clk,
        input  wire [addr_width-1:0] addr,
        input  wire [data_width-1:0] din,
        input  wire                  write_en,
        input  wire                  mmio,
        input  wire                  rst,
        output reg  [data_width-1:0] dout,
        output reg  [7:0]            o_leds
    );


`ifdef MMIO_SUPPORT
    wire cs_RAM0 = ~mmio;
    wire cs_XALU =  mmio & ( addr[7:4] == 4'h0 );
    wire cs_LEDS =  mmio & ( addr == 8'h10 );
    wire cs_RAND =  mmio & ( addr == 8'h11 );
`else
    wire cs_RAM0 = 1'b 1;
`endif




    parameter ROMFILE = "";

    wire [data_width-1:0] ram0_dout;
    ram #( .addr_width( 8 ), .data_width( 8 ) ) ram0 (

        .clk( clk ),
        .addr( addr ),
        .dout( ram0_dout ),

        .write_en( write_en & cs_RAM0 ),
        .din( din )
    );
    defparam ram0.ROMFILE = ROMFILE;


`ifdef MMIO_SUPPORT



    wire [data_width-1:0] xalu_dout;
    XALU #( .BASE_ADDR( 8'h00 ), .data_width( 8 ) ) xalu0 (
        .clk( clk ),
        .addr( addr ),
        .dout( xalu_dout ),
        .write_en( write_en & cs_XALU ),
        .din( din ),
        .rst( rst )
    );






    wire [data_width-1:0] leds_dout;
    LEDS #( .BASE_ADDR( 8'h10 ), .data_width( 8 ) ) leds0 (
        .clk( clk ),
        .addr( addr ),
        .dout( leds_dout ),
        .write_en( write_en & cs_LEDS ),
        .din( din ),
        .rst( rst )
    );





    wire [data_width-1:0] rand_dout;
    RAND rand0 (
        .clk( clk ),
        .addr( addr ),
        .dout( rand_dout ),
        .write_en( write_en & cs_RAND ),
        .din( din ),
        .rst( rst )
    );

`endif



    always @*
    begin
        case (1'b1)
            cs_RAM0: dout = ram0_dout;
`ifdef MMIO_SUPPORT
            cs_XALU: dout = xalu_dout;
            cs_LEDS: dout = leds_dout;
            cs_RAND: dout = rand_dout;
`endif

            default: dout = {(data_width){1'b 0}};
        endcase

`ifdef MMIO_SUPPORT
        o_leds = leds_dout;
`else
        o_leds = 8'b 0;
`endif
    end


endmodule