data/full_repos/permissive/123364505/risc_rom.v
None: at end of input
1: b'%Error: data/full_repos/permissive/123364505/risc_rom.v:41: Cannot find include file: d:\\xilinx\\designs\\risc32\\opcodes.vh\n `include "d:\\xilinx\\designs\\risc32\\opcodes.vh" \n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123364505,data/full_repos/permissive/123364505/d:\\xilinx\\designs\\risc32\\opcodes.vh\n             data/full_repos/permissive/123364505,data/full_repos/permissive/123364505/d:\\xilinx\\designs\\risc32\\opcodes.vh.v\n             data/full_repos/permissive/123364505,data/full_repos/permissive/123364505/d:\\xilinx\\designs\\risc32\\opcodes.vh.sv\n             d:\\xilinx\\designs\\risc32\\opcodes.vh\n             d:\\xilinx\\designs\\risc32\\opcodes.vh.v\n             d:\\xilinx\\designs\\risc32\\opcodes.vh.sv\n             obj_dir/d:\\xilinx\\designs\\risc32\\opcodes.vh\n             obj_dir/d:\\xilinx\\designs\\risc32\\opcodes.vh.v\n             obj_dir/d:\\xilinx\\designs\\risc32\\opcodes.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module risc_rom
	(

		input wire [ 31 : 0 ] address,
		output reg [ 31 : 0 ] data
    );


	`include "d:\xilinx\designs\risc32\opcodes.vh"
	


	







		
	always @*
		case (address)
			8'h00000000: data = {OP_LDI, R0, R3, 16'b1111111111111111 };
			8'h00000004: data = {OP_LDI, R0, R1, 16'b0000000000000010 };
			8'h00000008: data = {OP_LDI, R0, R2, 16'b0000000000000011 };
			8'h0000000C: data = {OP_ADD, R1, R2, R3, 11'b0};
			8'h00000010: data = {OP_SUB, R2, R1, R3, 11'b0};
			8'h00000014: data = {OP_GOTO, 26'b11111111111111111111111010};
			default: data = 32'b0;
		endcase
endmodule
module risc_rom
	(

		input wire [ 31 : 0 ] address,
		output reg [ 31 : 0 ] data
    );



	`include "d:\xilinx\designs\risc32\opcodes.vh"
	


	







		
	always @*
		case (address)
			8'h00000000: data = {OP_LDI, R0, R3, 16'b1111111111111111 };
			8'h00000004: data = {OP_LDI, R0, R1, 16'b0000000000000010 };
			8'h00000008: data = {OP_LDI, R0, R2, 16'b0000000000000011 };
			8'h0000000C: data = {OP_ADD, R1, R2, R3, 11'b0};
			8'h00000010: data = {OP_SUB, R2, R1, R3, 11'b0};
			8'h00000014: data = {OP_GOTO, 26'b11111111111111111111111010};
			default: data = 32'b0;
		endcase
endmodule