data/full_repos/permissive/169574047/bahavior/bahavior.srcs/sources_1/new/case_demultiplexer1_to_4.v
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data/verilator_xmls/07296f25-5041-47fe-852a-8456f36dd63b.xml
module case_demultiplexer1_to_4(output reg out0,out1,out2,out3, input in, s1,s0);

always @(s1 or s0 or in)
    case ({s1, s0})
        2'b00 : begin out0 = in; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz; end
        2'b01 : begin out0 = 1'bz; out1 = in; out2 = 1'bz; out3 = 1'bz; end
        2'b10 : begin out0 = 1'bz; out1 = 1'bz; out2 = in; out3 = 1'bz; end
        2'b11 : begin out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = in; end

        2'bx0, 2'bx1, 2'bxz, 2'bxx, 2'b0x, 2'b1x, 2'bzx :
            begin
                out0 = 1'bx; out1 = 1'bx; out2 = 1'bx; out3 = 1'bx;
            end
        2'bz0, 2'bz1, 2'bzz, 2'b0z, 2'b1z :
            begin
                out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz;
            end
        default : $display("Unspecified control signals");
    endcase

endmodule
module case_demultiplexer1_to_4(output reg out0,out1,out2,out3, input in, s1,s0);


always @(s1 or s0 or in)
    case ({s1, s0})
        2'b00 : begin out0 = in; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz; end
        2'b01 : begin out0 = 1'bz; out1 = in; out2 = 1'bz; out3 = 1'bz; end
        2'b10 : begin out0 = 1'bz; out1 = 1'bz; out2 = in; out3 = 1'bz; end
        2'b11 : begin out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = in; end

        2'bx0, 2'bx1, 2'bxz, 2'bxx, 2'b0x, 2'b1x, 2'bzx :
            begin
                out0 = 1'bx; out1 = 1'bx; out2 = 1'bx; out3 = 1'bx;
            end
        2'bz0, 2'bz1, 2'bzz, 2'b0z, 2'b1z :
            begin
                out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz;
            end
        default : $display("Unspecified control signals");
    endcase

endmodule