data/full_repos/permissive/109846502/bcd2binTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/bcd2binTest.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/bcd2binTest.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/bcd2binTest.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/bcd2binTest.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/109846502/bcd2binTest.v:37: Cannot find file containing module: \'bcd2bin\'\n bcd2bin uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/bcd2bin\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/bcd2bin.v\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/bcd2bin.sv\n             bcd2bin\n             bcd2bin.v\n             bcd2bin.sv\n             obj_dir/bcd2bin\n             obj_dir/bcd2bin.v\n             obj_dir/bcd2bin.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bcd2binTest;


	reg [3:0] N1;
	reg [3:0] N2;
	reg [3:0] N3;
	reg [3:0] N4;


	wire [13:0] out;


	bcd2bin uut (
		.N1(N1), 
		.N2(N2), 
		.N3(N3), 
		.N4(N4), 
		.out(out)
	);

	initial begin
		N1 = 4'd0;
		N2 = 4'd0;
		N3 = 4'd1;
		N4 = 4'd2;

		
		
		#10;
		N1 = 4'd5;
		N2 = 4'd4;
		N3 = 4'd3;
		N4 = 4'd2;
		
		#10;
		N1 = 4'd9;
		N2 = 4'd9;
		N3 = 4'd9;
		N4 = 4'd9;
		
		#10;
		N1 = 4'd3;
		N2 = 4'd5;
		N3 = 4'd7;
		N4 = 4'd9;
		
		#10;
		N1 = 4'd1;
		N2 = 4'd0;
		N3 = 4'd4;
		N4 = 4'd0;
		
		
		
	end
      
endmodule
module bcd2binTest;



	reg [3:0] N1;
	reg [3:0] N2;
	reg [3:0] N3;
	reg [3:0] N4;


	wire [13:0] out;


	bcd2bin uut (
		.N1(N1), 
		.N2(N2), 
		.N3(N3), 
		.N4(N4), 
		.out(out)
	);

	initial begin
		N1 = 4'd0;
		N2 = 4'd0;
		N3 = 4'd1;
		N4 = 4'd2;

		
		
		#10;
		N1 = 4'd5;
		N2 = 4'd4;
		N3 = 4'd3;
		N4 = 4'd2;
		
		#10;
		N1 = 4'd9;
		N2 = 4'd9;
		N3 = 4'd9;
		N4 = 4'd9;
		
		#10;
		N1 = 4'd3;
		N2 = 4'd5;
		N3 = 4'd7;
		N4 = 4'd9;
		
		#10;
		N1 = 4'd1;
		N2 = 4'd0;
		N3 = 4'd4;
		N4 = 4'd0;
		
		
		
	end
      
endmodule