data/full_repos/permissive/191067740/src/vga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/191067740/src/vga.v:270: Operator ADD expects 32 or 13 bits on the RHS, but RHS\'s VARREF \'haddr\' generates 7 bits.\n                                                                  : ... In instance vga\n  char_addr <= vaddr*100 + haddr;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/191067740/src/vga.v:309: Cannot find file containing module: \'vram_32kb\'\n vram_32kb uram(\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191067740/src,data/full_repos/permissive/191067740/vram_32kb\n             data/full_repos/permissive/191067740/src,data/full_repos/permissive/191067740/vram_32kb.v\n             data/full_repos/permissive/191067740/src,data/full_repos/permissive/191067740/vram_32kb.sv\n             vram_32kb\n             vram_32kb.v\n             vram_32kb.sv\n             obj_dir/vram_32kb\n             obj_dir/vram_32kb.v\n             obj_dir/vram_32kb.sv\n%Error: data/full_repos/permissive/191067740/src/vga.v:328: Cannot find file containing module: \'rom_cg_2kB\'\n rom_cg_2kB ucgr(\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module vga(
	input clk,
	input clk_4x,
	input reset,
	input sel_ram,
	input sel_ctl,
	input we,
	input [12:0] addr,
	input [7:0] din,
	output reg [7:0] ram_dout,
	output reg [7:0] ctl_dout,
	output reg [1:0]	vga_r,
						vga_g,
						vga_b,
	output reg 			vga_vs,
						vga_hs
);

	localparam MAX_H = 1055;
	localparam HFP_WID = 40;
	localparam HS_WID = 128;
	localparam HBP_WID = 88;
	localparam HA_WID = 800;
	localparam MAX_V = 627;
	localparam VFP_WID = 1;
	localparam VS_WID = 4;
	localparam VBP_WID = 23;
	localparam VA_WID = 600;
	

	reg [5:0] color_lut[15:0];
	reg [7:0] ctrl, hires;

	always @(posedge clk)
		if(reset)
		begin

			ctrl <= 8'h00;
			

			hires <= 8'hF3;
			

			color_lut[0]  <= 6'b00_00_00;
			color_lut[1]  <= 6'b11_00_00;
			color_lut[2]  <= 6'b00_11_00;
			color_lut[3]  <= 6'b00_00_11;
			color_lut[4]  <= 6'b00_11_11;
			color_lut[5]  <= 6'b11_00_11;
			color_lut[6]  <= 6'b11_11_00;
			color_lut[7]  <= 6'b01_01_01;
			color_lut[8]  <= 6'b10_10_10;
			color_lut[9]  <= 6'b11_10_11;
			color_lut[10] <= 6'b11_10_00;
			color_lut[11] <= 6'b11_11_10;
			color_lut[12] <= 6'b00_11_10;
			color_lut[13] <= 6'b00_10_11;
			color_lut[14] <= 6'b11_01_11;
			color_lut[15] <= 6'b11_11_11;
		end
		else if((we == 1'b1) && (sel_ctl == 1'b1))
		begin
			if(addr[4]==1'b0)
				case(addr[3:0])
					4'h0: ctrl <= din;
					4'h1: hires <= din;
				endcase
			else
				color_lut[addr[3:0]] <= din[5:0];
		end
		

	always @(posedge clk)
		if((we == 1'b0) && (sel_ctl == 1'b1))
			if(addr[4]==1'b0)
				case(addr[3:0])
					4'h0: ctl_dout <= ctrl;
					4'h1: ctl_dout <= hires;
					default: ctl_dout <= 8'h00;
				endcase
			else
				ctl_dout <= {2'b00,color_lut[addr[3:0]]};


	wire gc = ctrl[0];
	wire bank = ctrl[1];
	wire [1:0] mode = ctrl[3:2];
	

	reg [10:0] hcnt;
	reg [9:0] vcnt;
	reg hs, vs, ha, va;
	always @(posedge clk_4x)
	begin
		if(reset)
		begin
			hcnt <= 11'd0;
			vcnt <= 10'd0;
			hs <= 1'b0;
			vs <= 1'b0;
			ha <= 1'b0;
			va <= 1'b0;
		end
		else
		begin

			if(hcnt == MAX_H)
			begin

				hcnt <= 11'd0;
				if(vcnt == MAX_V)
					vcnt <= 10'd0;
				else
					vcnt <= vcnt + 10'd1;
				

				if(vcnt == VFP_WID)
					vs <= 1'b1;
				else if(vcnt == (VFP_WID + VS_WID))
					vs <= 1'b0;
				

				if(vcnt >= (VFP_WID + VS_WID + VBP_WID))
					va <= 1'b1;
				else
					va <= 1'b0;
			end
			else
				hcnt <= hcnt + 1;


			if(hcnt == HFP_WID)
				hs <= 1'b1;
			else if(hcnt == (HFP_WID + HS_WID))
				hs <= 1'b0;
			

			if(hcnt >= (HFP_WID + HS_WID + HBP_WID))
				ha <= 1'b1;
			else
				ha <= 1'b0;
		end
	end
	

	localparam ASTART = HFP_WID + HS_WID + HBP_WID;
	localparam BK_TOP = VFP_WID + VS_WID + VBP_WID;
	

	reg active;
	reg [2:0] pcnt;
	reg vload;
	reg hrena;
	reg mrena;
	reg [6:0] haddr;
	reg [2:0] cline;
	reg [6:0] vaddr;
	always @(posedge clk_4x)
	begin
		if(reset)
		begin
			active <= 1'b0;
			pcnt <= 3'b000;
			vload <= 1'b0;
			hrena <= 1'b0;
			mrena <= 1'b0;
			haddr <= 7'd0;
			cline <= 3'b000;
			vaddr <= 7'd0;
		end
		else
		begin

			if(active == 1'b0)
			begin
				if((hcnt == ASTART) && (vcnt >= BK_TOP))
				begin

					active <= 1'b1;
					pcnt <= 3'b000;
					vload <= 1'b1;
					hrena <= 1'b1;
					mrena <= 1'b1;
					haddr <= 7'd0;
				end
				

				if(vcnt == 0)
				begin
					cline <= 3'b000;
					vaddr <= 7'd0;
				end
			end
			else
			begin
				if(pcnt == 3'b111)
				begin

					vload <= 1'b1;
					

					if(haddr == 7'd99)
					begin

						active <= 1'b0;
						vload <= 1'b0;
						

						if(cline == 3'b111)
							vaddr <= vaddr + 7'd1;
						

						cline <= cline + 3'b001;
					end
					

					haddr <= haddr + 7'd1;
				end
				else
					vload <= 1'b0;
				

				pcnt <= pcnt + 3'b001;
				

				hrena <= pcnt[0];
				

				mrena <= &pcnt[1:0];
			end
		end
	end
	

	reg [2:0] vload_pipe;
	reg [2:0] hrena_pipe;
	reg [2:0] mrena_pipe;
	reg [4:0] active_pipe, hs_pipe, vs_pipe;
	reg [2:0] cline_dly0, cline_dly1;
	always @(posedge clk_4x)
	begin
		vload_pipe <= {vload_pipe[1:0],vload};
		hrena_pipe <= {hrena_pipe[1:0],hrena};
		mrena_pipe <= {mrena_pipe[1:0],mrena};
		active_pipe <= {active_pipe[3:0],active};
		hs_pipe <= {hs_pipe[3:0],hs};
		vs_pipe <= {vs_pipe[3:0],vs};
		cline_dly0 <= cline;
		cline_dly1 <= cline_dly0;
	end
	wire vload_dly = vload_pipe[2];
	wire hrena_dly = hrena_pipe[2];
	wire mrena_dly = mrena_pipe[2];
	wire active_dly = active_pipe[4];
	wire hs_dly = hs_pipe[4];
	wire vs_dly = vs_pipe[4];
	wire [2:0] cline_dly = cline_dly1;
	



	reg [12:0] char_addr;
	always @(posedge clk_4x)
		char_addr <= vaddr*100 + haddr;
	

	wire [13:0] vid_addr = {char_addr, 1'b0};
	

	reg [1:0] scnt;
	reg cpu_mux, cpu_mux_d1;
	always @(posedge clk_4x)
		if(reset)
		begin
			scnt <= 2'b10;
			cpu_mux <= 1'b0;
			cpu_mux_d1 <= 1'b0;
		end
		else
		begin
			if(vload)
				scnt <= 2'b00;
			else
				scnt <= scnt + 2'b01;
			

			cpu_mux <= (scnt == 2'b00) ? 1'b1 : 1'b0;
			cpu_mux_d1 <= cpu_mux;
		end
	

	wire [13:0] cpu_addr = {~addr[12],addr[11:0],gc};
		

	wire [13:0] mem_addr = cpu_mux ? cpu_addr: vid_addr;
		

	wire mem_we = sel_ram & we & cpu_mux;
	

	wire [7:0] raw_ram_dout;
	wire [15:0] raw_ram_word;
	vram_32kb uram(
		.clk(clk_4x),
		.we(mem_we),
		.addr({bank,mem_addr}),
		.din(din),
		.dout_byte(raw_ram_dout),
		.dout_word(raw_ram_word)
	);


	always @(posedge clk_4x)
		if(cpu_mux_d1)
			ram_dout <= raw_ram_dout;
		

	

	wire [10:0] cg_addr = {raw_ram_word[7:0],cline_dly};
	wire [7:0] cg_dout;
	rom_cg_2kB ucgr(
		.clk(clk_4x),
		.addr(cg_addr),
		.dout(cg_dout)
	);
	

	reg [7:0] color_idx;
	always @(posedge clk_4x)
		color_idx <= raw_ram_word[15:8];
	

	reg [3:0] hr_dout;
	always @(posedge clk_4x)
		case(cline_dly[2:1])
			2'b00: hr_dout <= raw_ram_word[3:0];
			2'b01: hr_dout <= raw_ram_word[7:4];
			2'b10: hr_dout <= raw_ram_word[11:8];
			2'b11: hr_dout <= raw_ram_word[15:12];
		endcase
	

	reg [7:0] mr_dout;
	always @(posedge clk_4x)
		mr_dout <= cline_dly[2] ? raw_ram_word[15:8] : raw_ram_word[7:0];
	

		

	reg [7:0] vid_shf_reg;
	reg [3:0] fore, back;
	always @(posedge clk_4x)
		if(vload_dly)
		begin
			vid_shf_reg <= cg_dout;
			fore <= color_idx[7:4];
			back <= color_idx[3:0];
		end
		else 
			vid_shf_reg <= {vid_shf_reg[6:0],1'b0};
		

	reg [3:0] hr_shf_reg;
	always @(posedge clk_4x)
		if(hrena_dly)
		begin
			if(vload_dly)
				hr_shf_reg <= hr_dout;
			else 
				hr_shf_reg <= {hr_shf_reg[2:0],1'b0};
		end
	

	reg [3:0] mr_sel_reg;
	always @(posedge clk_4x)
		if(mrena_dly)
			if(vload_dly)
				mr_sel_reg <= mr_dout[3:0];
			else
				mr_sel_reg <= mr_dout[7:4];
	

		

	reg [3:0] color_addr;
	always @(*)
		case(mode)
			2'b00: color_addr = vid_shf_reg[7] ? fore : back;
			2'b01: color_addr = hr_shf_reg[3] ? hires[7:4] : hires[3:0];
			2'b10: color_addr = mr_sel_reg;
			2'b11: color_addr = mr_sel_reg;
		endcase
		

	reg [1:0] r, g, b;
	always @(posedge clk_4x)
		{r, g, b} <= color_lut[color_addr];
		

	always @(posedge clk_4x)
	begin
		vga_r <= active_dly ? r : 2'd0;
		vga_g <= active_dly ? g : 2'd0;
		vga_b <= active_dly ? b : 2'd0;
		vga_hs <= hs_dly;
		vga_vs <= vs_dly;
	end
endmodule
module vga(
	input clk,
	input clk_4x,
	input reset,
	input sel_ram,
	input sel_ctl,
	input we,
	input [12:0] addr,
	input [7:0] din,
	output reg [7:0] ram_dout,
	output reg [7:0] ctl_dout,
	output reg [1:0]	vga_r,
						vga_g,
						vga_b,
	output reg 			vga_vs,
						vga_hs
);


	localparam MAX_H = 1055;
	localparam HFP_WID = 40;
	localparam HS_WID = 128;
	localparam HBP_WID = 88;
	localparam HA_WID = 800;
	localparam MAX_V = 627;
	localparam VFP_WID = 1;
	localparam VS_WID = 4;
	localparam VBP_WID = 23;
	localparam VA_WID = 600;
	

	reg [5:0] color_lut[15:0];
	reg [7:0] ctrl, hires;

	always @(posedge clk)
		if(reset)
		begin

			ctrl <= 8'h00;
			

			hires <= 8'hF3;
			

			color_lut[0]  <= 6'b00_00_00;
			color_lut[1]  <= 6'b11_00_00;
			color_lut[2]  <= 6'b00_11_00;
			color_lut[3]  <= 6'b00_00_11;
			color_lut[4]  <= 6'b00_11_11;
			color_lut[5]  <= 6'b11_00_11;
			color_lut[6]  <= 6'b11_11_00;
			color_lut[7]  <= 6'b01_01_01;
			color_lut[8]  <= 6'b10_10_10;
			color_lut[9]  <= 6'b11_10_11;
			color_lut[10] <= 6'b11_10_00;
			color_lut[11] <= 6'b11_11_10;
			color_lut[12] <= 6'b00_11_10;
			color_lut[13] <= 6'b00_10_11;
			color_lut[14] <= 6'b11_01_11;
			color_lut[15] <= 6'b11_11_11;
		end
		else if((we == 1'b1) && (sel_ctl == 1'b1))
		begin
			if(addr[4]==1'b0)
				case(addr[3:0])
					4'h0: ctrl <= din;
					4'h1: hires <= din;
				endcase
			else
				color_lut[addr[3:0]] <= din[5:0];
		end
		

	always @(posedge clk)
		if((we == 1'b0) && (sel_ctl == 1'b1))
			if(addr[4]==1'b0)
				case(addr[3:0])
					4'h0: ctl_dout <= ctrl;
					4'h1: ctl_dout <= hires;
					default: ctl_dout <= 8'h00;
				endcase
			else
				ctl_dout <= {2'b00,color_lut[addr[3:0]]};


	wire gc = ctrl[0];
	wire bank = ctrl[1];
	wire [1:0] mode = ctrl[3:2];
	

	reg [10:0] hcnt;
	reg [9:0] vcnt;
	reg hs, vs, ha, va;
	always @(posedge clk_4x)
	begin
		if(reset)
		begin
			hcnt <= 11'd0;
			vcnt <= 10'd0;
			hs <= 1'b0;
			vs <= 1'b0;
			ha <= 1'b0;
			va <= 1'b0;
		end
		else
		begin

			if(hcnt == MAX_H)
			begin

				hcnt <= 11'd0;
				if(vcnt == MAX_V)
					vcnt <= 10'd0;
				else
					vcnt <= vcnt + 10'd1;
				

				if(vcnt == VFP_WID)
					vs <= 1'b1;
				else if(vcnt == (VFP_WID + VS_WID))
					vs <= 1'b0;
				

				if(vcnt >= (VFP_WID + VS_WID + VBP_WID))
					va <= 1'b1;
				else
					va <= 1'b0;
			end
			else
				hcnt <= hcnt + 1;


			if(hcnt == HFP_WID)
				hs <= 1'b1;
			else if(hcnt == (HFP_WID + HS_WID))
				hs <= 1'b0;
			

			if(hcnt >= (HFP_WID + HS_WID + HBP_WID))
				ha <= 1'b1;
			else
				ha <= 1'b0;
		end
	end
	

	localparam ASTART = HFP_WID + HS_WID + HBP_WID;
	localparam BK_TOP = VFP_WID + VS_WID + VBP_WID;
	

	reg active;
	reg [2:0] pcnt;
	reg vload;
	reg hrena;
	reg mrena;
	reg [6:0] haddr;
	reg [2:0] cline;
	reg [6:0] vaddr;
	always @(posedge clk_4x)
	begin
		if(reset)
		begin
			active <= 1'b0;
			pcnt <= 3'b000;
			vload <= 1'b0;
			hrena <= 1'b0;
			mrena <= 1'b0;
			haddr <= 7'd0;
			cline <= 3'b000;
			vaddr <= 7'd0;
		end
		else
		begin

			if(active == 1'b0)
			begin
				if((hcnt == ASTART) && (vcnt >= BK_TOP))
				begin

					active <= 1'b1;
					pcnt <= 3'b000;
					vload <= 1'b1;
					hrena <= 1'b1;
					mrena <= 1'b1;
					haddr <= 7'd0;
				end
				

				if(vcnt == 0)
				begin
					cline <= 3'b000;
					vaddr <= 7'd0;
				end
			end
			else
			begin
				if(pcnt == 3'b111)
				begin

					vload <= 1'b1;
					

					if(haddr == 7'd99)
					begin

						active <= 1'b0;
						vload <= 1'b0;
						

						if(cline == 3'b111)
							vaddr <= vaddr + 7'd1;
						

						cline <= cline + 3'b001;
					end
					

					haddr <= haddr + 7'd1;
				end
				else
					vload <= 1'b0;
				

				pcnt <= pcnt + 3'b001;
				

				hrena <= pcnt[0];
				

				mrena <= &pcnt[1:0];
			end
		end
	end
	

	reg [2:0] vload_pipe;
	reg [2:0] hrena_pipe;
	reg [2:0] mrena_pipe;
	reg [4:0] active_pipe, hs_pipe, vs_pipe;
	reg [2:0] cline_dly0, cline_dly1;
	always @(posedge clk_4x)
	begin
		vload_pipe <= {vload_pipe[1:0],vload};
		hrena_pipe <= {hrena_pipe[1:0],hrena};
		mrena_pipe <= {mrena_pipe[1:0],mrena};
		active_pipe <= {active_pipe[3:0],active};
		hs_pipe <= {hs_pipe[3:0],hs};
		vs_pipe <= {vs_pipe[3:0],vs};
		cline_dly0 <= cline;
		cline_dly1 <= cline_dly0;
	end
	wire vload_dly = vload_pipe[2];
	wire hrena_dly = hrena_pipe[2];
	wire mrena_dly = mrena_pipe[2];
	wire active_dly = active_pipe[4];
	wire hs_dly = hs_pipe[4];
	wire vs_dly = vs_pipe[4];
	wire [2:0] cline_dly = cline_dly1;
	



	reg [12:0] char_addr;
	always @(posedge clk_4x)
		char_addr <= vaddr*100 + haddr;
	

	wire [13:0] vid_addr = {char_addr, 1'b0};
	

	reg [1:0] scnt;
	reg cpu_mux, cpu_mux_d1;
	always @(posedge clk_4x)
		if(reset)
		begin
			scnt <= 2'b10;
			cpu_mux <= 1'b0;
			cpu_mux_d1 <= 1'b0;
		end
		else
		begin
			if(vload)
				scnt <= 2'b00;
			else
				scnt <= scnt + 2'b01;
			

			cpu_mux <= (scnt == 2'b00) ? 1'b1 : 1'b0;
			cpu_mux_d1 <= cpu_mux;
		end
	

	wire [13:0] cpu_addr = {~addr[12],addr[11:0],gc};
		

	wire [13:0] mem_addr = cpu_mux ? cpu_addr: vid_addr;
		

	wire mem_we = sel_ram & we & cpu_mux;
	

	wire [7:0] raw_ram_dout;
	wire [15:0] raw_ram_word;
	vram_32kb uram(
		.clk(clk_4x),
		.we(mem_we),
		.addr({bank,mem_addr}),
		.din(din),
		.dout_byte(raw_ram_dout),
		.dout_word(raw_ram_word)
	);


	always @(posedge clk_4x)
		if(cpu_mux_d1)
			ram_dout <= raw_ram_dout;
		

	

	wire [10:0] cg_addr = {raw_ram_word[7:0],cline_dly};
	wire [7:0] cg_dout;
	rom_cg_2kB ucgr(
		.clk(clk_4x),
		.addr(cg_addr),
		.dout(cg_dout)
	);
	

	reg [7:0] color_idx;
	always @(posedge clk_4x)
		color_idx <= raw_ram_word[15:8];
	

	reg [3:0] hr_dout;
	always @(posedge clk_4x)
		case(cline_dly[2:1])
			2'b00: hr_dout <= raw_ram_word[3:0];
			2'b01: hr_dout <= raw_ram_word[7:4];
			2'b10: hr_dout <= raw_ram_word[11:8];
			2'b11: hr_dout <= raw_ram_word[15:12];
		endcase
	

	reg [7:0] mr_dout;
	always @(posedge clk_4x)
		mr_dout <= cline_dly[2] ? raw_ram_word[15:8] : raw_ram_word[7:0];
	

		

	reg [7:0] vid_shf_reg;
	reg [3:0] fore, back;
	always @(posedge clk_4x)
		if(vload_dly)
		begin
			vid_shf_reg <= cg_dout;
			fore <= color_idx[7:4];
			back <= color_idx[3:0];
		end
		else 
			vid_shf_reg <= {vid_shf_reg[6:0],1'b0};
		

	reg [3:0] hr_shf_reg;
	always @(posedge clk_4x)
		if(hrena_dly)
		begin
			if(vload_dly)
				hr_shf_reg <= hr_dout;
			else 
				hr_shf_reg <= {hr_shf_reg[2:0],1'b0};
		end
	

	reg [3:0] mr_sel_reg;
	always @(posedge clk_4x)
		if(mrena_dly)
			if(vload_dly)
				mr_sel_reg <= mr_dout[3:0];
			else
				mr_sel_reg <= mr_dout[7:4];
	

		

	reg [3:0] color_addr;
	always @(*)
		case(mode)
			2'b00: color_addr = vid_shf_reg[7] ? fore : back;
			2'b01: color_addr = hr_shf_reg[3] ? hires[7:4] : hires[3:0];
			2'b10: color_addr = mr_sel_reg;
			2'b11: color_addr = mr_sel_reg;
		endcase
		

	reg [1:0] r, g, b;
	always @(posedge clk_4x)
		{r, g, b} <= color_lut[color_addr];
		

	always @(posedge clk_4x)
	begin
		vga_r <= active_dly ? r : 2'd0;
		vga_g <= active_dly ? g : 2'd0;
		vga_b <= active_dly ? b : 2'd0;
		vga_hs <= hs_dly;
		vga_vs <= vs_dly;
	end
endmodule