data/full_repos/permissive/16142629/rtl/v1_3_1/zet_othop.v
None: at end of input
1: b'%Error: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_othop.v:34: Cannot find file containing module: \'zet_mux8_16\'\n  zet_mux8_16 mux8_16 (func, dcmp[15:0], dcmp2[15:0], deff, outf, clcm, setf, \n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/16142629/rtl/v1_3_1,data/full_repos/permissive/16142629/zet_mux8_16\n             data/full_repos/permissive/16142629/rtl/v1_3_1,data/full_repos/permissive/16142629/zet_mux8_16.v\n             data/full_repos/permissive/16142629/rtl/v1_3_1,data/full_repos/permissive/16142629/zet_mux8_16.sv\n             zet_mux8_16\n             zet_mux8_16.v\n             zet_mux8_16.sv\n             obj_dir/zet_mux8_16\n             obj_dir/zet_mux8_16.v\n             obj_dir/zet_mux8_16.sv\n%Warning-WIDTH: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_othop.v:36: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'func\' generates 3 bits.\n                                                                             : ... In instance zet_othop\n  assign out[19:16] = func ? dcmp2[19:16] : dcmp[19:16];\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_othop.v:39: Operator SHIFTL expects 20 bits on the LHS, but LHS\'s VARREF \'seg\' generates 16 bits.\n                                                                             : ... In instance zet_othop\n  assign dcmp  = (seg << 4) + deff;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_othop.v:39: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'deff\' generates 16 bits.\n                                                                             : ... In instance zet_othop\n  assign dcmp  = (seg << 4) + deff;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_othop.v:40: Operator SHIFTL expects 20 bits on the LHS, but LHS\'s VARREF \'seg\' generates 16 bits.\n                                                                             : ... In instance zet_othop\n  assign dcmp2 = (seg << 4) + deff2;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/16142629/rtl/v1_3_1/zet_othop.v:40: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'deff2\' generates 16 bits.\n                                                                             : ... In instance zet_othop\n  assign dcmp2 = (seg << 4) + deff2;\n                            ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module zet_othop (x, y, seg, off, iflags, func, word_op, out, oflags);

  input [15:0] x, y, off, seg, iflags;
  input [2:0] func;
  input word_op;
  output [19:0] out;
  output [8:0] oflags;


  wire [15:0] deff, deff2, outf, clcm, setf, intf, strf;
  wire [19:0] dcmp, dcmp2; 
  wire dfi;


  zet_mux8_16 mux8_16 (func, dcmp[15:0], dcmp2[15:0], deff, outf, clcm, setf, 
                       intf, strf, out[15:0]);
  assign out[19:16] = func ? dcmp2[19:16] : dcmp[19:16];


  assign dcmp  = (seg << 4) + deff;
  assign dcmp2 = (seg << 4) + deff2;
  assign deff  = x + y + off;
  assign deff2 = x + y + off + 16'd2;
  assign outf  = y;
  assign clcm  = y[2] ? (y[1] ?{iflags[15:1], 1'b0} 
                         :{iflags[15:11], 1'b0, iflags[9:0]})
                     : (y[1] ?{iflags[15:10], 1'b0, iflags[8:0]}
                       :{iflags[15:1], ~iflags[0]});
  assign setf  = y[2] ? (y[1] ?{iflags[15:1], 1'b1} 
                         :{iflags[15:11], 1'b1, iflags[9:0]})
                     : (y[1] ?{iflags[15:10], 1'b1, iflags[8:0]}
                       :iflags);

  assign intf = {iflags[15:10], 2'b0, iflags[7:0]};
  assign dfi  = iflags[10];
  assign strf = dfi ? (x - y) : (x + y);

  assign oflags = word_op ? { out[11:6], out[4], out[2], out[0] }
                           : { iflags[11:8], out[7:6], out[4], out[2], out[0] };
endmodule
module zet_othop (x, y, seg, off, iflags, func, word_op, out, oflags);


  input [15:0] x, y, off, seg, iflags;
  input [2:0] func;
  input word_op;
  output [19:0] out;
  output [8:0] oflags;


  wire [15:0] deff, deff2, outf, clcm, setf, intf, strf;
  wire [19:0] dcmp, dcmp2; 
  wire dfi;


  zet_mux8_16 mux8_16 (func, dcmp[15:0], dcmp2[15:0], deff, outf, clcm, setf, 
                       intf, strf, out[15:0]);
  assign out[19:16] = func ? dcmp2[19:16] : dcmp[19:16];


  assign dcmp  = (seg << 4) + deff;
  assign dcmp2 = (seg << 4) + deff2;
  assign deff  = x + y + off;
  assign deff2 = x + y + off + 16'd2;
  assign outf  = y;
  assign clcm  = y[2] ? (y[1] ?{iflags[15:1], 1'b0} 
                         :{iflags[15:11], 1'b0, iflags[9:0]})
                     : (y[1] ?{iflags[15:10], 1'b0, iflags[8:0]}
                       :{iflags[15:1], ~iflags[0]});
  assign setf  = y[2] ? (y[1] ?{iflags[15:1], 1'b1} 
                         :{iflags[15:11], 1'b1, iflags[9:0]})
                     : (y[1] ?{iflags[15:10], 1'b1, iflags[8:0]}
                       :iflags);

  assign intf = {iflags[15:10], 2'b0, iflags[7:0]};
  assign dfi  = iflags[10];
  assign strf = dfi ? (x - y) : (x + y);

  assign oflags = word_op ? { out[11:6], out[4], out[2], out[0] }
                           : { iflags[11:8], out[7:6], out[4], out[2], out[0] };
endmodule