data/full_repos/permissive/166008742/src/dp_ram.v
data/verilator_xmls/85841562-7759-4536-a6cb-40c705d9a056.xml
module dp_ram (
    clk    ,
    wr     ,
    wr_addr,
    wr_data,
    rd     ,
    rd_addr,
    rd_data
); 

parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;



input clk;
input wr;
input [ADDR_WIDTH-1:0] wr_addr;
input [DATA_WIDTH-1:0] wr_data;
input rd;
input [ADDR_WIDTH-1:0] rd_addr;
output [DATA_WIDTH-1:0] rd_data;



reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];




always @ (posedge clk) begin
    if (wr) begin
        mem[wr_addr] <= wr_data;
    end
end


assign rd_data = mem[rd_addr]; 

endmodule
module dp_ram (
    clk    ,
    wr     ,
    wr_addr,
    wr_data,
    rd     ,
    rd_addr,
    rd_data
);
 

parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;



input clk;
input wr;
input [ADDR_WIDTH-1:0] wr_addr;
input [DATA_WIDTH-1:0] wr_data;
input rd;
input [ADDR_WIDTH-1:0] rd_addr;
output [DATA_WIDTH-1:0] rd_data;



reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];




always @ (posedge clk) begin
    if (wr) begin
        mem[wr_addr] <= wr_data;
    end
end


assign rd_data = mem[rd_addr]; 

endmodule