data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:57: Cell has missing pin: \'clk1_out\'\n  pll_test u_pll_test (\n           ^~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:57: Cell has missing pin: \'clk2_out\'\n  pll_test u_pll_test (\n           ^~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:225: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg0 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:231: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:237: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg2 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:439: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg0 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:445: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:569: Cell has missing pin: \'en\'\n  reg_ar_as_w13 reg0 (\n                ^~~~\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:601: Cannot find file containing module: \'EG_LOGIC_BUFG\'\n  EG_LOGIC_BUFG bufg_feedback (\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG.v\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG.sv\n             EG_LOGIC_BUFG\n             EG_LOGIC_BUFG.v\n             EG_LOGIC_BUFG.sv\n             obj_dir/EG_LOGIC_BUFG\n             obj_dir/EG_LOGIC_BUFG.v\n             obj_dir/EG_LOGIC_BUFG.sv\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:604: Cannot find file containing module: \'EG_PHY_PLL\'\n  EG_PHY_PLL #(\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module my_uart_rx
  (
  clk,
  clk_bps,
  rst_n,
  uart_rx,
  bps_start,
  rx_data,
  rx_int
  );

  input clk;
  input clk_bps;
  input rst_n;
  input uart_rx;
  output bps_start;
  output [7:0] rx_data;
  output rx_int;

  wire [3:0] n18;
  wire [7:0] n28;
  wire [3:0] n30;
  wire [7:0] n31;
  wire [3:0] n32;
  wire [7:0] n33;
  wire [7:0] n34;
  wire [3:0] n35;
  wire [7:0] n36;
  wire [7:0] n37;
  wire [3:0] num;
  wire [7:0] rx_data_r;
  wire [7:0] rx_temp_data;
  wire bps_start_r;
  wire n0;
  wire n1;
  wire n10;
  wire n11;
  wire n12;
  wire n13;
  wire n14;
  wire n15;
  wire n16;
  wire n17;
  wire n19;
  wire n2;
  wire n20;
  wire n21;
  wire n22;
  wire n23;
  wire n24;
  wire n25;
  wire n26;
  wire n27;
  wire n29;
  wire n3;
  wire n38;
  wire n4;
  wire n5;
  wire n6;
  wire n7;
  wire n8;
  wire n9;
  wire neg_uart_rx;
  wire uart_rx0;
  wire uart_rx1;
  wire uart_rx2;
  wire uart_rx3;

  add_pu4_pu4_o4 add0 (
    .i0(num),
    .i1(4'b0001),
    .o(n18));
  AL_DFF bps_start_r_reg (
    .clk(clk),
    .d(n15),
    .reset(n17),
    .set(1'b0),
    .q(n10));
  eq_w4 eq0 (
    .i0(num),
    .i1(4'b1001),
    .o(n6));
  eq_w4 eq1 (
    .i0(num),
    .i1(4'b0001),
    .o(n19));
  eq_w4 eq2 (
    .i0(num),
    .i1(4'b0010),
    .o(n20));
  eq_w4 eq3 (
    .i0(num),
    .i1(4'b0011),
    .o(n21));
  eq_w4 eq4 (
    .i0(num),
    .i1(4'b0100),
    .o(n22));
  eq_w4 eq5 (
    .i0(num),
    .i1(4'b0101),
    .o(n23));
  eq_w4 eq6 (
    .i0(num),
    .i1(4'b0110),
    .o(n24));
  eq_w4 eq7 (
    .i0(num),
    .i1(4'b0111),
    .o(n25));
  eq_w4 eq8 (
    .i0(num),
    .i1(4'b1000),
    .o(n26));
  AL_DFF i30 (
    .clk(clk),
    .d(n16),
    .reset(n17),
    .set(1'b0),
    .q(n14));
  binary_mux_s1_w4 mux0 (
    .i0(num),
    .i1(4'b0000),
    .sel(n6),
    .o(n30));
  binary_mux_s1_w8 mux1 (
    .i0(rx_data_r),
    .i1(rx_temp_data),
    .sel(n6),
    .o(n31));
  binary_mux_s1_w4 mux2 (
    .i0(n30),
    .i1(n18),
    .sel(clk_bps),
    .o(n32));
  binary_mux_s1_w8 mux3 (
    .i0(rx_temp_data),
    .i1(n28),
    .sel(clk_bps),
    .o(n33));
  binary_mux_s1_w8 mux4 (
    .i0(n31),
    .i1(rx_data_r),
    .sel(clk_bps),
    .o(n34));
  binary_mux_s1_w4 mux5 (
    .i0(num),
    .i1(n32),
    .sel(rx_int),
    .o(n35));
  binary_mux_s1_w8 mux6 (
    .i0(rx_temp_data),
    .i1(n33),
    .sel(rx_int),
    .o(n36));
  binary_mux_s1_w8 mux7 (
    .i0(rx_data_r),
    .i1(n34),
    .sel(rx_int),
    .o(n37));
  reg_ar_as_w8 reg0 (
    .clk(clk),
    .d(n36),
    .reset({n17,n17,n17,n17,n17,n17,n17,n17}),
    .set(8'b00000000),
    .q(rx_temp_data));
  reg_ar_as_w4 reg1 (
    .clk(clk),
    .d(n35),
    .reset({n17,n17,n17,n17}),
    .set(4'b0000),
    .q(num));
  reg_ar_as_w8 reg2 (
    .clk(clk),
    .d(n37),
    .reset({n17,n17,n17,n17,n17,n17,n17,n17}),
    .set(8'b00000000),
    .q(rx_data_r));
  AL_DFF rx_int_reg (
    .clk(clk),
    .d(n9),
    .reset(n17),
    .set(1'b0),
    .q(rx_int));
  onehot_mux_s9_w8 sel0 (
    .i0(rx_temp_data),
    .i1({uart_rx,rx_temp_data[6:0]}),
    .i2({rx_temp_data[7],uart_rx,rx_temp_data[5:0]}),
    .i3({rx_temp_data[7:6],uart_rx,rx_temp_data[4:0]}),
    .i4({rx_temp_data[7:5],uart_rx,rx_temp_data[3:0]}),
    .i5({rx_temp_data[7:4],uart_rx,rx_temp_data[2:0]}),
    .i6({rx_temp_data[7:3],uart_rx,rx_temp_data[1:0]}),
    .i7({rx_temp_data[7:2],uart_rx,rx_temp_data[0]}),
    .i8({rx_temp_data[7:1],uart_rx}),
    .sel({n19,n20,n21,n22,n23,n24,n25,n26,n27}),
    .o(n28));
  and u10 (neg_uart_rx, n3, n4);
  or u11 (n38, n12, n5);
  buf u12 (rx_data[4], rx_data_r[4]);
  or u13 (n5, n20, n19);
  AL_MUX u14 (
    .i0(rx_int),
    .i1(1'b0),
    .sel(n6),
    .o(n7));
  buf u15 (rx_data[6], rx_data_r[6]);
  AL_MUX u16 (
    .i0(n7),
    .i1(1'b1),
    .sel(neg_uart_rx),
    .o(n9));
  or u17 (n12, n22, n21);
  or u18 (n13, n29, n0);
  or u19 (n11, neg_uart_rx, n6);
  not u2 (n27, n8);
  buf u20 (rx_data[3], rx_data_r[3]);
  or u21 (n0, n24, n23);
  buf u22 (rx_data[2], rx_data_r[2]);
  AL_MUX u23 (
    .i0(n10),
    .i1(neg_uart_rx),
    .sel(n11),
    .o(n15));
  AL_MUX u24 (
    .i0(n14),
    .i1(1'b1),
    .sel(n11),
    .o(n16));
  bufif1 u25 (bps_start_r, n10, n14);
  buf u26 (bps_start, bps_start_r);
  buf u27 (rx_data[7], rx_data_r[7]);
  buf u28 (rx_data[1], rx_data_r[1]);
  buf u29 (rx_data[0], rx_data_r[0]);
  or u3 (n8, n13, n38);
  or u30 (n29, n26, n25);
  not u4 (n17, rst_n);
  buf u5 (rx_data[5], rx_data_r[5]);
  and u6 (n1, uart_rx3, uart_rx2);
  not u7 (n2, uart_rx1);
  and u8 (n3, n1, n2);
  not u9 (n4, uart_rx0);
  AL_DFF uart_rx0_reg (
    .clk(clk),
    .d(uart_rx),
    .reset(n17),
    .set(1'b0),
    .q(uart_rx0));
  AL_DFF uart_rx1_reg (
    .clk(clk),
    .d(uart_rx0),
    .reset(n17),
    .set(1'b0),
    .q(uart_rx1));
  AL_DFF uart_rx2_reg (
    .clk(clk),
    .d(uart_rx1),
    .reset(n17),
    .set(1'b0),
    .q(uart_rx2));
  AL_DFF uart_rx3_reg (
    .clk(clk),
    .d(uart_rx2),
    .reset(n17),
    .set(1'b0),
    .q(uart_rx3));

endmodule
module my_uart_rx
  (
  clk,
  clk_bps,
  rst_n,
  uart_rx,
  bps_start,
  rx_data,
  rx_int
  );


  input clk;
  input clk_bps;
  input rst_n;
  input uart_rx;
  output bps_start;
  output [7:0] rx_data;
  output rx_int;

  wire [3:0] n18;
  wire [7:0] n28;
  wire [3:0] n30;
  wire [7:0] n31;
  wire [3:0] n32;
  wire [7:0] n33;
  wire [7:0] n34;
  wire [3:0] n35;
  wire [7:0] n36;
  wire [7:0] n37;
  wire [3:0] num;
  wire [7:0] rx_data_r;
  wire [7:0] rx_temp_data;
  wire bps_start_r;
  wire n0;
  wire n1;
  wire n10;
  wire n11;
  wire n12;
  wire n13;
  wire n14;
  wire n15;
  wire n16;
  wire n17;
  wire n19;
  wire n2;
  wire n20;
  wire n21;
  wire n22;
  wire n23;
  wire n24;
  wire n25;
  wire n26;
  wire n27;
  wire n29;
  wire n3;
  wire n38;
  wire n4;
  wire n5;
  wire n6;
  wire n7;
  wire n8;
  wire n9;
  wire neg_uart_rx;
  wire uart_rx0;
  wire uart_rx1;
  wire uart_rx2;
  wire uart_rx3;

  add_pu4_pu4_o4 add0 (
    .i0(num),
    .i1(4'b0001),
    .o(n18));
  AL_DFF bps_start_r_reg (
    .clk(clk),
    .d(n15),
    .reset(n17),
    .set(1'b0),
    .q(n10));
  eq_w4 eq0 (
    .i0(num),
    .i1(4'b1001),
    .o(n6));
  eq_w4 eq1 (
    .i0(num),
    .i1(4'b0001),
    .o(n19));
  eq_w4 eq2 (
    .i0(num),
    .i1(4'b0010),
    .o(n20));
  eq_w4 eq3 (
    .i0(num),
    .i1(4'b0011),
    .o(n21));
  eq_w4 eq4 (
    .i0(num),
    .i1(4'b0100),
    .o(n22));
  eq_w4 eq5 (
    .i0(num),
    .i1(4'b0101),
    .o(n23));
  eq_w4 eq6 (
    .i0(num),
    .i1(4'b0110),
    .o(n24));
  eq_w4 eq7 (
    .i0(num),
    .i1(4'b0111),
    .o(n25));
  eq_w4 eq8 (
    .i0(num),
    .i1(4'b1000),
    .o(n26));
  AL_DFF i30 (
    .clk(clk),
    .d(n16),
    .reset(n17),
    .set(1'b0),
    .q(n14));
  binary_mux_s1_w4 mux0 (
    .i0(num),
    .i1(4'b0000),
    .sel(n6),
    .o(n30));
  binary_mux_s1_w8 mux1 (
    .i0(rx_data_r),
    .i1(rx_temp_data),
    .sel(n6),
    .o(n31));
  binary_mux_s1_w4 mux2 (
    .i0(n30),
    .i1(n18),
    .sel(clk_bps),
    .o(n32));
  binary_mux_s1_w8 mux3 (
    .i0(rx_temp_data),
    .i1(n28),
    .sel(clk_bps),
    .o(n33));
  binary_mux_s1_w8 mux4 (
    .i0(n31),
    .i1(rx_data_r),
    .sel(clk_bps),
    .o(n34));
  binary_mux_s1_w4 mux5 (
    .i0(num),
    .i1(n32),
    .sel(rx_int),
    .o(n35));
  binary_mux_s1_w8 mux6 (
    .i0(rx_temp_data),
    .i1(n33),
    .sel(rx_int),
    .o(n36));
  binary_mux_s1_w8 mux7 (
    .i0(rx_data_r),
    .i1(n34),
    .sel(rx_int),
    .o(n37));
  reg_ar_as_w8 reg0 (
    .clk(clk),
    .d(n36),
    .reset({n17,n17,n17,n17,n17,n17,n17,n17}),
    .set(8'b00000000),
    .q(rx_temp_data));
  reg_ar_as_w4 reg1 (
    .clk(clk),
    .d(n35),
    .reset({n17,n17,n17,n17}),
    .set(4'b0000),
    .q(num));
  reg_ar_as_w8 reg2 (
    .clk(clk),
    .d(n37),
    .reset({n17,n17,n17,n17,n17,n17,n17,n17}),
    .set(8'b00000000),
    .q(rx_data_r));
  AL_DFF rx_int_reg (
    .clk(clk),
    .d(n9),
    .reset(n17),
    .set(1'b0),
    .q(rx_int));
  onehot_mux_s9_w8 sel0 (
    .i0(rx_temp_data),
    .i1({uart_rx,rx_temp_data[6:0]}),
    .i2({rx_temp_data[7],uart_rx,rx_temp_data[5:0]}),
    .i3({rx_temp_data[7:6],uart_rx,rx_temp_data[4:0]}),
    .i4({rx_temp_data[7:5],uart_rx,rx_temp_data[3:0]}),
    .i5({rx_temp_data[7:4],uart_rx,rx_temp_data[2:0]}),
    .i6({rx_temp_data[7:3],uart_rx,rx_temp_data[1:0]}),
    .i7({rx_temp_data[7:2],uart_rx,rx_temp_data[0]}),
    .i8({rx_temp_data[7:1],uart_rx}),
    .sel({n19,n20,n21,n22,n23,n24,n25,n26,n27}),
    .o(n28));
  and u10 (neg_uart_rx, n3, n4);
  or u11 (n38, n12, n5);
  buf u12 (rx_data[4], rx_data_r[4]);
  or u13 (n5, n20, n19);
  AL_MUX u14 (
    .i0(rx_int),
    .i1(1'b0),
    .sel(n6),
    .o(n7));
  buf u15 (rx_data[6], rx_data_r[6]);
  AL_MUX u16 (
    .i0(n7),
    .i1(1'b1),
    .sel(neg_uart_rx),
    .o(n9));
  or u17 (n12, n22, n21);
  or u18 (n13, n29, n0);
  or u19 (n11, neg_uart_rx, n6);
  not u2 (n27, n8);
  buf u20 (rx_data[3], rx_data_r[3]);
  or u21 (n0, n24, n23);
  buf u22 (rx_data[2], rx_data_r[2]);
  AL_MUX u23 (
    .i0(n10),
    .i1(neg_uart_rx),
    .sel(n11),
    .o(n15));
  AL_MUX u24 (
    .i0(n14),
    .i1(1'b1),
    .sel(n11),
    .o(n16));
  bufif1 u25 (bps_start_r, n10, n14);
  buf u26 (bps_start, bps_start_r);
  buf u27 (rx_data[7], rx_data_r[7]);
  buf u28 (rx_data[1], rx_data_r[1]);
  buf u29 (rx_data[0], rx_data_r[0]);
  or u3 (n8, n13, n38);
  or u30 (n29, n26, n25);
  not u4 (n17, rst_n);
  buf u5 (rx_data[5], rx_data_r[5]);
  and u6 (n1, uart_rx3, uart_rx2);
  not u7 (n2, uart_rx1);
  and u8 (n3, n1, n2);
  not u9 (n4, uart_rx0);
  AL_DFF uart_rx0_reg (
    .clk(clk),
    .d(uart_rx),
    .reset(n17),
    .set(1'b0),
    .q(uart_rx0));
  AL_DFF uart_rx1_reg (
    .clk(clk),
    .d(uart_rx0),
    .reset(n17),
    .set(1'b0),
    .q(uart_rx1));
  AL_DFF uart_rx2_reg (
    .clk(clk),
    .d(uart_rx1),
    .reset(n17),
    .set(1'b0),
    .q(uart_rx2));
  AL_DFF uart_rx3_reg (
    .clk(clk),
    .d(uart_rx2),
    .reset(n17),
    .set(1'b0),
    .q(uart_rx3));

endmodule