data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new/ALUCtr_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new/ALUCtr_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new/ALUCtr_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new/ALUCtr_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new/ALUCtr_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new/ALUCtr_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new/ALUCtr_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new/ALUCtr_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new/ALUCtr_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new/ALUCtr_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new/ALUCtr_tb.v:30: Cannot find file containing module: \'ctr\'\nctr u0(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new,data/full_repos/permissive/194376374/ctr\n             data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new,data/full_repos/permissive/194376374/ctr.v\n             data/full_repos/permissive/194376374/0521_LJX_lab3/0521_LJX_lab0302/lab030201.srcs/sim_1/new,data/full_repos/permissive/194376374/ctr.sv\n             ctr\n             ctr.v\n             ctr.sv\n             obj_dir/ctr\n             obj_dir/ctr.v\n             obj_dir/ctr.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALUCtr_tb(
    );
    
reg [5:0] Funct;
reg [1:0] ALUOp;
wire [3:0] ALUCtrOut;

ctr u0(
    .Funct(Funct),
    .ALUOp(ALUOp),
    .ALUCtrOut(ALUCtrOut)
);

    initial begin
    

    Funct=6'b000000;
    

    #100;
    
    #100;

    ALUOp=2'b10;

    Funct=6'b100000;
    #100;

    Funct=6'b100010;
    #100;

    Funct=6'b100100;
    #100;

    Funct=6'b100101;
    #100;

    Funct=6'b101010;
    #100;
    

    ALUOp=2'b00;
    #100;

    ALUOp=2'b01;
    #100;

    end

endmodule
module ALUCtr_tb(
    );

    
reg [5:0] Funct;
reg [1:0] ALUOp;
wire [3:0] ALUCtrOut;

ctr u0(
    .Funct(Funct),
    .ALUOp(ALUOp),
    .ALUCtrOut(ALUCtrOut)
);

    initial begin
    

    Funct=6'b000000;
    

    #100;
    
    #100;

    ALUOp=2'b10;

    Funct=6'b100000;
    #100;

    Funct=6'b100010;
    #100;

    Funct=6'b100100;
    #100;

    Funct=6'b100101;
    #100;

    Funct=6'b101010;
    #100;
    

    ALUOp=2'b00;
    #100;

    ALUOp=2'b01;
    #100;

    end

endmodule