data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/eim_debug.v
1: b"%Error: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/eim_debug.v:47: Cannot find file containing module: 'eim_pretrigger'\n   eim_pretrigger eim_pre (\n   ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports,data/full_repos/permissive/17242406/eim_pretrigger\n             data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports,data/full_repos/permissive/17242406/eim_pretrigger.v\n             data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports,data/full_repos/permissive/17242406/eim_pretrigger.sv\n             eim_pretrigger\n             eim_pretrigger.v\n             eim_pretrigger.sv\n             obj_dir/eim_pretrigger\n             obj_dir/eim_pretrigger.v\n             obj_dir/eim_pretrigger.sv\n%Error: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/eim_debug.v:105: Cannot find file containing module: 'eim_monitor'\n   eim_monitor eim_mon (\n   ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module eim_debug(
		 input wire bclk_i,
		 input wire bclk_dll,
		 input wire adv_in,
		 input wire rw_in,
		 input wire cs1_in,
		 input wire [2:0] a_in,
		 input wire [15:0] din_in,
		 input wire oe_in,

		 input wire eim_trig_ena,
		 input wire eim_mon_reset,
		 input wire eim_mon_adv,

		 output wire mon_empty,
		 output wire mon_full,

		 output wire [23:0] mon_data,
		 
		 input wire bclk_reset
		 );

   wire pretrig_full;
   wire pretrig_almost_full;
   wire [23:0] pretrig_d;
   
   eim_pretrigger eim_pre (
			   .wr_clk(bclk_i),
			   .rd_clk(bclk_dll),
			   .din({1'b0,oe_in,adv_in,rw_in,cs1_in,a_in[2:0],din_in[15:0]}),
			   .wr_en(1'b1),
			   .rd_en(pretrig_full | pretrig_almost_full),
			   .dout(pretrig_d[23:0]),
			   .full(pretrig_full),
			   .almost_full(pretrig_almost_full),



			   .rst(bclk_reset)
			   );

   wire        mon_trig;
   reg         mon_wren;
   reg         mon_oneshot;
   
   assign mon_trig = eim_trig_ena & !cs1_in;


   always @(posedge bclk_dll) begin
      if(eim_mon_reset) begin
	 mon_oneshot <= 1'b0;
	 mon_wren <= 1'b0;
      end else begin
	 if(mon_trig && !mon_wren && !mon_oneshot) begin
	    mon_wren <= 1'b1;
	    mon_oneshot <= 1'b1;
	 end else if( mon_oneshot && mon_wren ) begin
	    mon_oneshot <= 1'b1;
	    if(mon_full) begin
	       mon_wren <= 1'b0;
	    end else begin
	       mon_wren <= 1'b1;
	    end
	 end else if( mon_oneshot && !mon_wren ) begin
	    mon_oneshot <= 1'b1;
	    mon_wren <= 1'b0;
	 end else begin
	    mon_oneshot <= 1'b0;
	    mon_wren <= 1'b0;
	 end
      end
   end

   reg eim_mon_pulse;
   reg [1:0] eim_mon_adv_d;

   always @(posedge bclk_dll) begin
      eim_mon_adv_d[0] <= eim_mon_adv;
      eim_mon_adv_d[1] <= eim_mon_adv_d[0];

      eim_mon_pulse <= !eim_mon_adv_d[1] & eim_mon_adv_d[0];
   end


   eim_monitor eim_mon (
				   .wr_clk(bclk_dll),
				   .rd_clk(bclk_dll),
				   .din(pretrig_d[23:0]),
				   .wr_en(mon_wren),
				   .rd_en(eim_mon_pulse),
				   .dout(mon_data[23:0]),
				   .almost_full(mon_full),

				   .empty(mon_empty),

				   .rst(bclk_reset | eim_mon_reset)
				   );

endmodule
module eim_debug(
		 input wire bclk_i,
		 input wire bclk_dll,
		 input wire adv_in,
		 input wire rw_in,
		 input wire cs1_in,
		 input wire [2:0] a_in,
		 input wire [15:0] din_in,
		 input wire oe_in,

		 input wire eim_trig_ena,
		 input wire eim_mon_reset,
		 input wire eim_mon_adv,

		 output wire mon_empty,
		 output wire mon_full,

		 output wire [23:0] mon_data,
		 
		 input wire bclk_reset
		 );


   wire pretrig_full;
   wire pretrig_almost_full;
   wire [23:0] pretrig_d;
   
   eim_pretrigger eim_pre (
			   .wr_clk(bclk_i),
			   .rd_clk(bclk_dll),
			   .din({1'b0,oe_in,adv_in,rw_in,cs1_in,a_in[2:0],din_in[15:0]}),
			   .wr_en(1'b1),
			   .rd_en(pretrig_full | pretrig_almost_full),
			   .dout(pretrig_d[23:0]),
			   .full(pretrig_full),
			   .almost_full(pretrig_almost_full),



			   .rst(bclk_reset)
			   );

   wire        mon_trig;
   reg         mon_wren;
   reg         mon_oneshot;
   
   assign mon_trig = eim_trig_ena & !cs1_in;


   always @(posedge bclk_dll) begin
      if(eim_mon_reset) begin
	 mon_oneshot <= 1'b0;
	 mon_wren <= 1'b0;
      end else begin
	 if(mon_trig && !mon_wren && !mon_oneshot) begin
	    mon_wren <= 1'b1;
	    mon_oneshot <= 1'b1;
	 end else if( mon_oneshot && mon_wren ) begin
	    mon_oneshot <= 1'b1;
	    if(mon_full) begin
	       mon_wren <= 1'b0;
	    end else begin
	       mon_wren <= 1'b1;
	    end
	 end else if( mon_oneshot && !mon_wren ) begin
	    mon_oneshot <= 1'b1;
	    mon_wren <= 1'b0;
	 end else begin
	    mon_oneshot <= 1'b0;
	    mon_wren <= 1'b0;
	 end
      end
   end

   reg eim_mon_pulse;
   reg [1:0] eim_mon_adv_d;

   always @(posedge bclk_dll) begin
      eim_mon_adv_d[0] <= eim_mon_adv;
      eim_mon_adv_d[1] <= eim_mon_adv_d[0];

      eim_mon_pulse <= !eim_mon_adv_d[1] & eim_mon_adv_d[0];
   end


   eim_monitor eim_mon (
				   .wr_clk(bclk_dll),
				   .rd_clk(bclk_dll),
				   .din(pretrig_d[23:0]),
				   .wr_en(mon_wren),
				   .rd_en(eim_mon_pulse),
				   .dout(mon_data[23:0]),
				   .almost_full(mon_full),

				   .empty(mon_empty),

				   .rst(bclk_reset | eim_mon_reset)
				   );

endmodule