data/full_repos/permissive/113780415/src/top_test.v
 line:1736: before: "&&"
1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(posedge clk && enable == 1'b1)\n                                   ^~\n%Error: Cannot continue\n"
module SevenSegment(HEXleft, HEXright, num);



	output reg [6:0] HEXleft, HEXright;

	input [4:0] num;

 

	always @(num) begin

		case (num)


    	5'b00000: begin

    	HEXleft = 7'b100_0000;

    	HEXright = 7'b100_0000;

      	end


      	5'b00001: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b111_1001;

      	end


      	5'b00010: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b010_0100;

      	end


      	5'b00011: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b011_0000;

      	end


      	5'b0100: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b001_1001;

      	end


      	5'b00101: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b001_0010;

      	end


      	5'b00110: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b000_0010;

      	end


      	5'b00111: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b111_1000;

      	end


      	5'b01000: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b000_0000;

      	end


      	5'b01001: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b001_1000;

      	end


      	5'b01010: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b100_0000;

      	end


      	5'b01011: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b111_1001;

      	end


      	5'b01100: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b010_0100;

      	end


      	5'b01101: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b011_0000;

      	end


      	5'b01110: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b001_1001;

      	end


      	5'b01111: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b001_0010;

      	end


      	5'b10000: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b000_0010;

      	end


      	5'b10001: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b111_1000;

      	end


      	5'b10010: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b000_0000;

      	end


      	5'b10011: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b001_1000;

      	end


      	5'b10100: begin

      	HEXleft = 7'b010_0100;

      	HEXright = 7'b100_0000;

      	end



		default: begin

		HEXleft = 7'b0000000;

		HEXright = 7'b0000000;

		end

	endcase

end

endmodule
module SevenSegment(HEXleft, HEXright, num);




	output reg [6:0] HEXleft, HEXright;

	input [4:0] num;

 

	always @(num) begin

		case (num)


    	5'b00000: begin

    	HEXleft = 7'b100_0000;

    	HEXright = 7'b100_0000;

      	end


      	5'b00001: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b111_1001;

      	end


      	5'b00010: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b010_0100;

      	end


      	5'b00011: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b011_0000;

      	end


      	5'b0100: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b001_1001;

      	end


      	5'b00101: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b001_0010;

      	end


      	5'b00110: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b000_0010;

      	end


      	5'b00111: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b111_1000;

      	end


      	5'b01000: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b000_0000;

      	end


      	5'b01001: begin

      	HEXleft = 7'b100_0000;

      	HEXright = 7'b001_1000;

      	end


      	5'b01010: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b100_0000;

      	end


      	5'b01011: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b111_1001;

      	end


      	5'b01100: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b010_0100;

      	end


      	5'b01101: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b011_0000;

      	end


      	5'b01110: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b001_1001;

      	end


      	5'b01111: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b001_0010;

      	end


      	5'b10000: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b000_0010;

      	end


      	5'b10001: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b111_1000;

      	end


      	5'b10010: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b000_0000;

      	end


      	5'b10011: begin

      	HEXleft = 7'b111_1001;

      	HEXright = 7'b001_1000;

      	end


      	5'b10100: begin

      	HEXleft = 7'b010_0100;

      	HEXright = 7'b100_0000;

      	end



		default: begin

		HEXleft = 7'b0000000;

		HEXright = 7'b0000000;

		end

	endcase

end

endmodule