data/full_repos/permissive/143278/ivltests/pr1695309.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1695309.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== (A|B)) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   genvar i;
   parameter MSB = 7;

   wire [MSB:0] Z;
   reg [MSB:0]	A, B;
   generate
      for (i = 0; i <= MSB; i = i+1)
	begin: or2
	   OR2 uor2 (.A(A[i]), .B(B[i]), .Z(Z[i]));
	end
   endgenerate

   initial begin
      for (A = 0 ;  A < 'hff ;  A = A+1)
	for (B = 0 ;  B < 'hff ;  B = B+1)
	   #1 if (Z !== (A|B)) begin
	      $display("FAILED -- A=%h, B=%h, Z=%h", A, B, Z);
	      $finish;
	   end

      $display("PASSED");
   end

endmodule
module main;


   genvar i;
   parameter MSB = 7;

   wire [MSB:0] Z;
   reg [MSB:0]	A, B;
   generate
      for (i = 0; i <= MSB; i = i+1)
	begin: or2
	   OR2 uor2 (.A(A[i]), .B(B[i]), .Z(Z[i]));
	end
   endgenerate

   initial begin
      for (A = 0 ;  A < 'hff ;  A = A+1)
	for (B = 0 ;  B < 'hff ;  B = B+1)
	   #1 if (Z !== (A|B)) begin
	      $display("FAILED -- A=%h, B=%h, Z=%h", A, B, Z);
	      $finish;
	   end

      $display("PASSED");
   end

endmodule