data/full_repos/permissive/115074071/src/main/Datapath/SignExt.v
1: b'%Error: data/full_repos/permissive/115074071/src/main/Datapath/SignExt.v:1: Cannot find include file: src/main/Define/signal_def.v\n`include "src/main/Define/signal_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115074071/src/main/Datapath,data/full_repos/permissive/115074071/src/main/Define/signal_def.v\n             data/full_repos/permissive/115074071/src/main/Datapath,data/full_repos/permissive/115074071/src/main/Define/signal_def.v.v\n             data/full_repos/permissive/115074071/src/main/Datapath,data/full_repos/permissive/115074071/src/main/Define/signal_def.v.sv\n             src/main/Define/signal_def.v\n             src/main/Define/signal_def.v.v\n             src/main/Define/signal_def.v.sv\n             obj_dir/src/main/Define/signal_def.v\n             obj_dir/src/main/Define/signal_def.v.v\n             obj_dir/src/main/Define/signal_def.v.sv\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/SignExt.v:15: Define or directive not defined: \'`EXTOP_UNSIGNED\'\n            `EXTOP_UNSIGNED: Immediate32 = {{16\'b0}, Immediate16[15:0]};\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/SignExt.v:15: syntax error, unexpected \':\', expecting endcase\n            `EXTOP_UNSIGNED: Immediate32 = {{16\'b0}, Immediate16[15:0]};\n                           ^\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/SignExt.v:16: Define or directive not defined: \'`EXTOP_SIGNED\'\n            `EXTOP_SIGNED: Immediate32 = {{16{Immediate16[15]}}, Immediate16[15:0]};\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115074071/src/main/Datapath/SignExt.v:17: Define or directive not defined: \'`EXTOP_INST\'\n            `EXTOP_INST: Immediate32 = 32\'b0;\n            ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module EXT(
    input               clk,
    input   [15:0]      Immediate16,
    input   [1:0]       EXTOp,
    output  reg[31:0]   Immediate32
);

    initial begin
        Immediate32 = 32'b00;
    end

    always @(negedge clk) begin
        case(EXTOp)
            `EXTOP_UNSIGNED: Immediate32 = {{16'b0}, Immediate16[15:0]};
            `EXTOP_SIGNED: Immediate32 = {{16{Immediate16[15]}}, Immediate16[15:0]};
            `EXTOP_INST: Immediate32 = 32'b0;
            default: Immediate32 = {{16'b0}, Immediate16[15:0]};
        endcase
        $display("EXTOp: %b, EXT in: %x, out: %x", EXTOp, Immediate16, Immediate32);
    end
endmodule
module EXT(
    input               clk,
    input   [15:0]      Immediate16,
    input   [1:0]       EXTOp,
    output  reg[31:0]   Immediate32
);


    initial begin
        Immediate32 = 32'b00;
    end

    always @(negedge clk) begin
        case(EXTOp)
            `EXTOP_UNSIGNED: Immediate32 = {{16'b0}, Immediate16[15:0]};
            `EXTOP_SIGNED: Immediate32 = {{16{Immediate16[15]}}, Immediate16[15:0]};
            `EXTOP_INST: Immediate32 = 32'b0;
            default: Immediate32 = {{16'b0}, Immediate16[15:0]};
        endcase
        $display("EXTOp: %b, EXT in: %x, out: %x", EXTOp, Immediate16, Immediate32);
    end
endmodule