data/full_repos/permissive/17027731/src/mojo_top.v
data/verilator_xmls/21ccad76-e320-4f45-8bfe-564845315316.xml
module mojo_top(

    input clk,

    input rst_n,

    input cclk,

    output[7:0]led,

    output spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,

    output [3:0] spi_channel,

    input avr_tx,
    output avr_rx,
    input avr_rx_busy
    );

wire rst = ~rst_n;


assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;

assign led = 8'b0;

endmodule
module mojo_top(

    input clk,

    input rst_n,

    input cclk,

    output[7:0]led,

    output spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,

    output [3:0] spi_channel,

    input avr_tx,
    output avr_rx,
    input avr_rx_busy
    );


wire rst = ~rst_n;


assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;

assign led = 8'b0;

endmodule