data/full_repos/permissive/199632300/HDLBits/Circuits/Combiantional_Logic/Basic_Gates/truthtable1.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Combiantional_Logic/Basic_Gates/truthtable1.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'f'\n                                                                                                                         : ... In instance top_module\n            f = 1'b1;\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Combiantional_Logic/Basic_Gates/truthtable1.v:13: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'f'\n                                                                                                                          : ... In instance top_module\n                f = 1'b1;\n                ^\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Combiantional_Logic/Basic_Gates/truthtable1.v:16: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'f'\n                                                                                                                          : ... In instance top_module\n                f = 1'b0;\n                ^\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Combiantional_Logic/Basic_Gates/truthtable1.v:20: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'f'\n                                                                                                                          : ... In instance top_module\n            f = 1'b0;\n            ^\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module( 
    input x3,
    input x2,
    input x1,
    output f
);
    always @(*) begin
        if(x1 == 0 && x2 == 1 && x3 == 0) begin
            f = 1'b1;
        end
        else if(x1 == 1) begin
            if((x2|x3) == 1) begin
                f = 1'b1;
            end
            else begin
                f = 1'b0;
            end
        end
        else begin 
            f = 1'b0;
        end
    end
endmodule
module top_module( 
    input x3,
    input x2,
    input x1,
    output f
);

    always @(*) begin
        if(x1 == 0 && x2 == 1 && x3 == 0) begin
            f = 1'b1;
        end
        else if(x1 == 1) begin
            if((x2|x3) == 1) begin
                f = 1'b1;
            end
            else begin
                f = 1'b0;
            end
        end
        else begin 
            f = 1'b0;
        end
    end
endmodule