data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ctrl.v
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ctrl.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module ctrl(
		input wire		rst,


		input wire		id_req,
		input wire		mem_busy,


		output reg[5:0] stall
	);

	always @ (*)
	begin
		if (rst) begin
			stall <= 6'b000000;
		end else begin
			if (mem_busy) begin
				stall <= 6'b111111;
			end else if (id_req) begin
				stall <= 6'b000011;
			end else begin
				stall <= 6'b000000;
			end
		end
	end

endmodule
module ctrl(
		input wire		rst,


		input wire		id_req,
		input wire		mem_busy,


		output reg[5:0] stall
	);


	always @ (*)
	begin
		if (rst) begin
			stall <= 6'b000000;
		end else begin
			if (mem_busy) begin
				stall <= 6'b111111;
			end else if (id_req) begin
				stall <= 6'b000011;
			end else begin
				stall <= 6'b000000;
			end
		end
	end

endmodule