data/full_repos/permissive/160310921/vedic_2.v
data/verilator_xmls/71c627d3-1cda-481c-ba19-bd2eeb966817.xml
module vedic_2(a,b,c);
input [1:0]a,b;
output [3:0]c;

assign c[0] =  a[0]&b[0];
assign c[1] = (a[1]&b[0])^(a[0]&b[1]);
assign c[2] = ((a[0]&b[1])&(a[1]&b[0]))^(a[1]&b[1]);
assign c[3] = (a[1]&b[1])&((a[0]&b[1])&(a[1]&b[0]));
endmodule
module vedic_2(a,b,c);

input [1:0]a,b;
output [3:0]c;

assign c[0] =  a[0]&b[0];
assign c[1] = (a[1]&b[0])^(a[0]&b[1]);
assign c[2] = ((a[0]&b[1])&(a[1]&b[0]))^(a[1]&b[1]);
assign c[3] = (a[1]&b[1])&((a[0]&b[1])&(a[1]&b[0]));
endmodule