data/full_repos/permissive/185287750/vrased/hw-mod/dma_AC.v
 line:9: before: ")"
1: b"%Error: data/full_repos/permissive/185287750/vrased/hw-mod/dma_AC.v:9: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/185287750/vrased/hw-mod/dma_AC.v:36: syntax error, unexpected initial\ninitial\n^~~~~~~\n%Error: data/full_repos/permissive/185287750/vrased/hw-mod/dma_AC.v:44: syntax error, unexpected always\nalways @(posedge clk)\n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module  dma_AC (
    clk,
    pc,
    dma_addr,
    dma_en,

    reset,
);

input           clk;
input   [15:0]  pc;
input   [15:0]  dma_addr;
input           dma_en;
output          reset;





parameter KMEM_BASE = 16'hFEFE;
parameter KMEM_SIZE = 16'h0040;






parameter RESET_HANDLER = 16'h0000;
parameter RUN  = 1'b0, KILL = 1'b1;

reg             state;
reg             key_res;


initial
    begin
        state = KILL;
        key_res = 1'b1;
    end

wire invalid_access_key = (dma_addr >= KMEM_BASE && dma_addr < KMEM_BASE + KMEM_SIZE) && dma_en;

always @(posedge clk)
if( state == RUN && invalid_access_key) 
    state <= KILL;
else if (state == KILL && pc == RESET_HANDLER && !invalid_access_key)
    state <= RUN;
else state <= state;

always @(posedge clk)
if (state == RUN && invalid_access_key)
    key_res <= 1'b1;
else if (state == KILL && pc == RESET_HANDLER && !invalid_access_key)
    key_res <= 1'b0;
else if (state == KILL)
    key_res <= 1'b1;
else if (state == RUN)
    key_res <= 1'b0;
else key_res <= 1'b0;

assign reset = key_res;

endmodule
module  dma_AC (
    clk,
    pc,
    dma_addr,
    dma_en,

    reset,
);


input           clk;
input   [15:0]  pc;
input   [15:0]  dma_addr;
input           dma_en;
output          reset;





parameter KMEM_BASE = 16'hFEFE;
parameter KMEM_SIZE = 16'h0040;






parameter RESET_HANDLER = 16'h0000;
parameter RUN  = 1'b0, KILL = 1'b1;

reg             state;
reg             key_res;


initial
    begin
        state = KILL;
        key_res = 1'b1;
    end

wire invalid_access_key = (dma_addr >= KMEM_BASE && dma_addr < KMEM_BASE + KMEM_SIZE) && dma_en;

always @(posedge clk)
if( state == RUN && invalid_access_key) 
    state <= KILL;
else if (state == KILL && pc == RESET_HANDLER && !invalid_access_key)
    state <= RUN;
else state <= state;

always @(posedge clk)
if (state == RUN && invalid_access_key)
    key_res <= 1'b1;
else if (state == KILL && pc == RESET_HANDLER && !invalid_access_key)
    key_res <= 1'b0;
else if (state == KILL)
    key_res <= 1'b1;
else if (state == RUN)
    key_res <= 1'b0;
else key_res <= 1'b0;

assign reset = key_res;

endmodule