data/full_repos/permissive/101427397/v/MUX4T1_5.v
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data/verilator_xmls/e4d917fd-edf7-468c-bd3c-ad81f9ab5e66.xml
module   MUX4T1_5(input [1:0]s,
						 input [4:0]I0,
						 input [4:0]I1,
						 input [4:0]I2,
						 input [4:0]I3,						
						 output reg[4:0]o
						 );

		always @ *
			case(s)
				2'd0: o <= I0;
				2'd1: o <= I1;
				2'd2: o <= I2;
				2'd3: o <= I3;
			endcase	
endmodule
module   MUX4T1_5(input [1:0]s,
						 input [4:0]I0,
						 input [4:0]I1,
						 input [4:0]I2,
						 input [4:0]I3,						
						 output reg[4:0]o
						 );


		always @ *
			case(s)
				2'd0: o <= I0;
				2'd1: o <= I1;
				2'd2: o <= I2;
				2'd3: o <= I3;
			endcase	
endmodule