data/full_repos/permissive/149769583/sram.v
data/verilator_xmls/53d0a0bb-862e-4f7c-a761-7678c06c600a.xml
module sram #(parameter ADDR_WIDTH = 3, DATA_WIDTH = 34, DEPTH = 8) (

	input [DATA_WIDTH-1:0] data_a,
	input [ADDR_WIDTH-1:0] addr_a, addr_b,
	input we_a,
	output reg [DATA_WIDTH-1:0] q_b
);


	reg [DATA_WIDTH-1:0] ram [0:DEPTH-1];
	reg [DATA_WIDTH-1:0] q_a;

	always @ (addr_a) begin
		if (we_a) begin
			ram[addr_a] <= data_a;
			q_a <= data_a;
		end else begin
			q_a <= ram[addr_a];
		end
	end


	always @ (addr_b) begin







		q_b <= ram[addr_b];

	end

endmodule
module sram #(parameter ADDR_WIDTH = 3, DATA_WIDTH = 34, DEPTH = 8) (

	input [DATA_WIDTH-1:0] data_a,
	input [ADDR_WIDTH-1:0] addr_a, addr_b,
	input we_a,
	output reg [DATA_WIDTH-1:0] q_b
);



	reg [DATA_WIDTH-1:0] ram [0:DEPTH-1];
	reg [DATA_WIDTH-1:0] q_a;

	always @ (addr_a) begin
		if (we_a) begin
			ram[addr_a] <= data_a;
			q_a <= data_a;
		end else begin
			q_a <= ram[addr_a];
		end
	end


	always @ (addr_b) begin







		q_b <= ram[addr_b];

	end

endmodule