data/full_repos/permissive/146246005/RISC-y Processor/RISCY_CPU.sv
 line:3: before: "package"
1: b'%Error: Cannot find file containing module: Processor,data/full_repos/permissive/146246005\n        ... Looked in:\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.v\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.sv\n             Processor,data/full_repos/permissive/146246005\n             Processor,data/full_repos/permissive/146246005.v\n             Processor,data/full_repos/permissive/146246005.sv\n             obj_dir/Processor,data/full_repos/permissive/146246005\n             obj_dir/Processor,data/full_repos/permissive/146246005.v\n             obj_dir/Processor,data/full_repos/permissive/146246005.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/RISC-y\n%Error: Cannot find file containing module: Processor/RISCY_CPU.sv\n%Error: Exiting due to 3 error(s)\n'
module PORT_DIR_REG(REG_OUT,DATA_IN,PDR_EN,CLOCK,RESET);
	output reg REG_OUT;
	input reg DATA_IN;
	input CLOCK,RESET,PDR_EN;
  always @ (posedge CLOCK or negedge RESET) begin
	if(PDR_EN)
		REG_OUT <= DATA_IN;
	else if (!RESET)
		REG_OUT <= 0;
	else
		REG_OUT <= REG_OUT;
  end
endmodule
module PORT_DIR_REG(REG_OUT,DATA_IN,PDR_EN,CLOCK,RESET);

	output reg REG_OUT;
	input reg DATA_IN;
	input CLOCK,RESET,PDR_EN;
  always @ (posedge CLOCK or negedge RESET) begin
	if(PDR_EN)
		REG_OUT <= DATA_IN;
	else if (!RESET)
		REG_OUT <= 0;
	else
		REG_OUT <= REG_OUT;
  end
endmodule