data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sim.v
 line:227: before: "$"
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sim.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sim.v:15: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sim.v:20: Unsupported: Ignoring delay on this delayed statement.\n  forever #5 clk = !clk;  \n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sim.v:26: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sim.v:27: Unsupported: Ignoring delay on this delayed statement.\n#700000 $finish;\n^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module sim();

	reg clk;
	reg rst;
	wire Tx;
	wire Rx;

	cpu cpu0(clk,rst,Tx,Rx);
	memory_sim memory_sim0(clk,rst,Rx,Tx);

	initial begin
		$dumpvars(0);
	end

	initial begin
		clk = 0;
		forever #5 clk = !clk;
	end

	initial begin
		rst = 0;
		rst = 1;
#100	rst = 0;
#700000 $finish;
	end

endmodule
module sim();


	reg clk;
	reg rst;
	wire Tx;
	wire Rx;

	cpu cpu0(clk,rst,Tx,Rx);
	memory_sim memory_sim0(clk,rst,Rx,Tx);

	initial begin
		$dumpvars(0);
	end

	initial begin
		clk = 0;
		forever #5 clk = !clk;
	end

	initial begin
		rst = 0;
		rst = 1;
#100	rst = 0;
#700000 $finish;
	end

endmodule