data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v
 line:55: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n   #10 $finish;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n   #10 $finish;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n   #10 $finish;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n   #10 $finish;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #1 check_last <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n   #10 $finish;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #1 check_last <= 0;\n  ^\n%Error: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:92: syntax error, unexpected \'@\'\n   @(negedge clk);\n   ^\n%Error: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:94: syntax error, unexpected \'@\'\n   @(posedge clk)\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n    #1 check_last = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n%Error: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:103: syntax error, unexpected end\nend\n^~~\n%Error: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:116: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n    #1 check_last = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n%Error: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:132: Unsupported or unknown PLI call: $vcdpluson\n  $vcdpluson;\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:133: Unsupported or unknown PLI call: $vcdplusmemon\n  $vcdplusmemon;\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:134: Unsupported or unknown PLI call: $vcdplusdeltacycleon\n  $vcdplusdeltacycleon;\n  ^~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n      #10 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n      #10 clk = 0;\n      ^\n%Error: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:149: syntax error, unexpected \'@\'\n@(posedge clk) ;\n^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:231: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n   #50;\n   ^\n%Error: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:239: Unsupported: fork statements\n   fork\n   ^~~~\n%Error: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:243: syntax error, unexpected \'@\'\n            @(negedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:246: Unsupported: Ignoring delay on this delayed statement.\n               #5;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:253: Unsupported: Ignoring delay on this delayed statement.\n            #(50 + ($random % 50));\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:256: Unsupported: Ignoring delay on this delayed statement.\n         #200 $finish;\n         ^\n%Error: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:262: syntax error, unexpected \'@\'\n            @(negedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:270: Unsupported: Ignoring delay on this delayed statement.\n            #(50 + ($random % 50));\n            ^\n%Error: data/full_repos/permissive/148324174/FIFO/sync_fifo_tb.v:278: Unsupported or unknown PLI call: $timeformat\n   $timeformat(-9,3," ps",5);\n   ^~~~~~~~~~~\n%Error: Exiting due to 12 error(s), 21 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_fifo;

reg		clk;
reg		rstp;
reg [7:0]	src_in;
reg [7:0]	dst_in;
reg [31:0]	data_in;
reg		readp;
reg		writep;
wire [7:0]	src_out;
wire [7:0]	dst_out;
wire [31:0]	data_out;
wire		emptyp;
wire		fullp;
reg [3:0] count_checker;
reg check_last;

parameter    depth = 2;

sync_fifo #(depth+1) U1 (
   .clk		(clk),
   .rstp	(rstp),
   .src_in	(src_in),
   .dst_in	(dst_in),
   .data_in	(data_in),
   .readp	(readp),
   .writep	(writep),
   .src_out	(src_out),
   .dst_out	(dst_out),
   .data_out	(data_out),
   .emptyp	(emptyp),
   .fullp	(fullp)
);



always @(posedge clk) begin
   if (rstp) begin
   count_checker = 4'b0000;
   check_last = 0;
   end
   end




always @(negedge clk)
    begin
		if (test_fifo.U1.count != count_checker && count_checker == 4'h8 && writep) begin
		    $display("FAILURE: Overflow Detected at time %t!  Exiting test.", $realtime);
			#10 $finish;
		end
		if (test_fifo.U1.count != count_checker && count_checker == 4'h0 && readp) begin
		    $display("FAILURE: Underflow Detected at time %t!  Exiting test.", $realtime);
			#10 $finish;
		end
		if (test_fifo.U1.count != count_checker) begin
		    $display("FAILURE: Counter mismatch at time %t!  Exiting test.", $realtime);
			#10 $finish;
		end
	end	


always @(posedge check_last)
	begin
		if (count_checker == 4'h0 && !emptyp) begin
		    $display("FAILURE: Empty flag missed at time %t.  Exiting test.", $realtime - 1);
			#10 $finish;
		end
		#1 check_last <= 0;
	end	


always @(posedge check_last)
	begin
		if (count_checker == 4'h8 && !fullp) begin
		    $display("FAILURE: Full flag missed at time %t.  Exiting test.", $realtime - 1);
			#10 $finish;
		end
		#1 check_last <= 0;
	end	




task read_word;
begin
   @(negedge clk);
   readp = 1;
   @(posedge clk)

   if (count_checker > 4'h0 && !writep) begin
       count_checker <= count_checker - 1;
	   #1 check_last = 1;
   end		 
   $display ("Read %0h from FIFO", data_out);
   #5;
   readp = 0;
end
endtask
   
task write_word;
input [7:0]	src;
input [7:0]	dst;
input [31:0]	data;
begin
   @(negedge clk);
   src_in = src;
   dst_in = dst;
   data_in = data;
   writep = 1;
   @(posedge clk);

   if (count_checker < 4'h8 && !readp) begin
       count_checker <= count_checker + 1;
	   #1 check_last = 1;
   end	   
   $display ("Write %0h to FIFO", data_in);
   #5;
   src_in = 8'bz;
   dst_in = 8'bz;
   data_in = 32'bz;
   writep = 0;
end
endtask

initial begin
  $vcdpluson;
  $vcdplusmemon;
  $vcdplusdeltacycleon;
end

initial begin
   clk = 0;
   forever begin
      #10 clk = 1;
      #10 clk = 0;
   end
end

initial begin
   test1;
   test2;
   
@(posedge clk) ;
   $finish;
end






task test1;
begin
   src_in = 8'bz;
   dst_in = 8'bz;
   data_in = 32'bz;
   writep = 0;
   readp = 0;


   rstp = 1;
   #50;
   rstp = 0;
   #50;
   

   write_word (0,1,16'h1111);
   write_word (1,2,16'h2222);
   write_word (3,4,16'h3333);
   

   read_word;
   read_word;
   

   write_word (5,6,16'h4444);
   

   repeat (6) begin
      read_word;
   end
   

   write_word (0,1,16'h0001);
   write_word (0,1,16'h0002);
   write_word (0,1,16'h0003);
   write_word (0,1,16'h0004);
   write_word (0,1,16'h0005);
   write_word (0,1,16'h0006);
   write_word (0,1,16'h0007);
   write_word (0,1,16'h0008);
   write_word (0,1,16'h0009);


    repeat (8) begin
      read_word;
    end
   
   $display ("Done TEST1.");
end
endtask











task test2;
reg [15:0] writer_counter;
begin
   src_in = 8'bz;
   dst_in = 8'bz;
   data_in = 32'bz;
   writer_counter = 16'h0001;
   writep = 0;
   readp = 0;


   rstp = 1;
   #50;
   rstp = 0;
   #50;
  




   fork

      begin
         repeat (500) begin
            @(negedge clk);
            if (fullp == 1'b0) begin
               write_word ($random,$random,$random);
               #5;
               writer_counter = writer_counter + 1;
            end
            else begin
               $display ("WRITER is waiting..");
            end

            #(50 + ($random % 50));
         end
         $display ("Done with WRITER fork..");
         #200 $finish;
      end
      

      begin
         forever begin
            @(negedge clk);
            if (emptyp == 1'b0) begin
               read_word;
            end  
            else begin
               $display ("READER is waiting..");
            end

            #(50 + ($random % 50));
         end
      end
   join
end
endtask

always @(clk) begin
   $timeformat(-9,3," ps",5);
   $display ("time = %t", $realtime);
end

always @(fullp)
   $display ("fullp = %0b", fullp);
   
always @(emptyp)
   $display ("emptyp = %0b", emptyp);

always @(U1.head)
   $display ("head = %0h", U1.head);

always @(U1.tail)
   $display ("tail = %0h", U1.tail);

endmodule
module test_fifo;


reg		clk;
reg		rstp;
reg [7:0]	src_in;
reg [7:0]	dst_in;
reg [31:0]	data_in;
reg		readp;
reg		writep;
wire [7:0]	src_out;
wire [7:0]	dst_out;
wire [31:0]	data_out;
wire		emptyp;
wire		fullp;
reg [3:0] count_checker;
reg check_last;

parameter    depth = 2;

sync_fifo #(depth+1) U1 (
   .clk		(clk),
   .rstp	(rstp),
   .src_in	(src_in),
   .dst_in	(dst_in),
   .data_in	(data_in),
   .readp	(readp),
   .writep	(writep),
   .src_out	(src_out),
   .dst_out	(dst_out),
   .data_out	(data_out),
   .emptyp	(emptyp),
   .fullp	(fullp)
);



always @(posedge clk) begin
   if (rstp) begin
   count_checker = 4'b0000;
   check_last = 0;
   end
   end




always @(negedge clk)
    begin
		if (test_fifo.U1.count != count_checker && count_checker == 4'h8 && writep) begin
		    $display("FAILURE: Overflow Detected at time %t!  Exiting test.", $realtime);
			#10 $finish;
		end
		if (test_fifo.U1.count != count_checker && count_checker == 4'h0 && readp) begin
		    $display("FAILURE: Underflow Detected at time %t!  Exiting test.", $realtime);
			#10 $finish;
		end
		if (test_fifo.U1.count != count_checker) begin
		    $display("FAILURE: Counter mismatch at time %t!  Exiting test.", $realtime);
			#10 $finish;
		end
	end	


always @(posedge check_last)
	begin
		if (count_checker == 4'h0 && !emptyp) begin
		    $display("FAILURE: Empty flag missed at time %t.  Exiting test.", $realtime - 1);
			#10 $finish;
		end
		#1 check_last <= 0;
	end	


always @(posedge check_last)
	begin
		if (count_checker == 4'h8 && !fullp) begin
		    $display("FAILURE: Full flag missed at time %t.  Exiting test.", $realtime - 1);
			#10 $finish;
		end
		#1 check_last <= 0;
	end	




task read_word;
begin
   @(negedge clk);
   readp = 1;
   @(posedge clk)

   if (count_checker > 4'h0 && !writep) begin
       count_checker <= count_checker - 1;
	   #1 check_last = 1;
   end		 
   $display ("Read %0h from FIFO", data_out);
   #5;
   readp = 0;
end
endtask
   
task write_word;
input [7:0]	src;
input [7:0]	dst;
input [31:0]	data;
begin
   @(negedge clk);
   src_in = src;
   dst_in = dst;
   data_in = data;
   writep = 1;
   @(posedge clk);

   if (count_checker < 4'h8 && !readp) begin
       count_checker <= count_checker + 1;
	   #1 check_last = 1;
   end	   
   $display ("Write %0h to FIFO", data_in);
   #5;
   src_in = 8'bz;
   dst_in = 8'bz;
   data_in = 32'bz;
   writep = 0;
end
endtask

initial begin
  $vcdpluson;
  $vcdplusmemon;
  $vcdplusdeltacycleon;
end

initial begin
   clk = 0;
   forever begin
      #10 clk = 1;
      #10 clk = 0;
   end
end

initial begin
   test1;
   test2;
   
@(posedge clk) ;
   $finish;
end






task test1;
begin
   src_in = 8'bz;
   dst_in = 8'bz;
   data_in = 32'bz;
   writep = 0;
   readp = 0;


   rstp = 1;
   #50;
   rstp = 0;
   #50;
   

   write_word (0,1,16'h1111);
   write_word (1,2,16'h2222);
   write_word (3,4,16'h3333);
   

   read_word;
   read_word;
   

   write_word (5,6,16'h4444);
   

   repeat (6) begin
      read_word;
   end
   

   write_word (0,1,16'h0001);
   write_word (0,1,16'h0002);
   write_word (0,1,16'h0003);
   write_word (0,1,16'h0004);
   write_word (0,1,16'h0005);
   write_word (0,1,16'h0006);
   write_word (0,1,16'h0007);
   write_word (0,1,16'h0008);
   write_word (0,1,16'h0009);


    repeat (8) begin
      read_word;
    end
   
   $display ("Done TEST1.");
end
endtask











task test2;
reg [15:0] writer_counter;
begin
   src_in = 8'bz;
   dst_in = 8'bz;
   data_in = 32'bz;
   writer_counter = 16'h0001;
   writep = 0;
   readp = 0;


   rstp = 1;
   #50;
   rstp = 0;
   #50;
  




   fork

      begin
         repeat (500) begin
            @(negedge clk);
            if (fullp == 1'b0) begin
               write_word ($random,$random,$random);
               #5;
               writer_counter = writer_counter + 1;
            end
            else begin
               $display ("WRITER is waiting..");
            end

            #(50 + ($random % 50));
         end
         $display ("Done with WRITER fork..");
         #200 $finish;
      end
      

      begin
         forever begin
            @(negedge clk);
            if (emptyp == 1'b0) begin
               read_word;
            end  
            else begin
               $display ("READER is waiting..");
            end

            #(50 + ($random % 50));
         end
      end
   join
end
endtask

always @(clk) begin
   $timeformat(-9,3," ps",5);
   $display ("time = %t", $realtime);
end

always @(fullp)
   $display ("fullp = %0b", fullp);
   
always @(emptyp)
   $display ("emptyp = %0b", emptyp);

always @(U1.head)
   $display ("head = %0h", U1.head);

always @(U1.tail)
   $display ("tail = %0h", U1.tail);

endmodule