data/full_repos/permissive/179227721/mid/bcdsub.v
1: b"%Error: data/full_repos/permissive/179227721/mid/bcdsub.v:34: Cannot find file containing module: 'Cla'\n   Cla add12(.num1(x12), .num2(x22), .cin(1'b0), .out(htmp), .car(hc));\n   ^~~\n        ... Looked in:\n             data/full_repos/permissive/179227721/mid,data/full_repos/permissive/179227721/Cla\n             data/full_repos/permissive/179227721/mid,data/full_repos/permissive/179227721/Cla.v\n             data/full_repos/permissive/179227721/mid,data/full_repos/permissive/179227721/Cla.sv\n             Cla\n             Cla.v\n             Cla.sv\n             obj_dir/Cla\n             obj_dir/Cla.v\n             obj_dir/Cla.sv\n%Error: data/full_repos/permissive/179227721/mid/bcdsub.v:35: Cannot find file containing module: 'Cla'\n   Cla add11(.num1(x11), .num2(x21), .cin(1'b0), .out(ltmp), .car(lc));\n   ^~~\n%Error: data/full_repos/permissive/179227721/mid/bcdsub.v:38: Cannot find file containing module: 'Cla'\n   Cla add22(.num1(htmp), .num2(4'b0000), .cin(lc), .out(y2), .car());\n   ^~~\n%Error: data/full_repos/permissive/179227721/mid/bcdsub.v:39: Cannot find file containing module: 'Cla'\n   Cla add21(.num1(ltmp), .num2(comp), .cin(hc), .out(y1), .car());\n   ^~~\n%Error: Exiting due to 4 error(s)\n"
module bcdsub(

 input [7:0]  num1,
 input [7:0]  num2,
 output [7:0] out,
 output       uf  );

   wire [3:0] x12;
   wire [3:0] x11;
   wire [3:0] x22;
   wire [3:0] x21;
   wire [3:0] y2;
   wire [3:0] y1;
   wire       lc;
   wire       hc;


   wire [3:0] htmp;
   wire [3:0] ltmp;





   wire [3:0] comp;



   assign x12[3:0] = num1[7:4];
   assign x11[3:0] = num1[3:0];
   assign x22[3:0] = ~(num2[7:4]);
   assign x21[3:0] = ~(num2[3:0]);

   Cla add12(.num1(x12), .num2(x22), .cin(1'b0), .out(htmp), .car(hc));
   Cla add11(.num1(x11), .num2(x21), .cin(1'b0), .out(ltmp), .car(lc));

   assign comp[3:0] = {!lc, 1'b0, !lc, 1'b0};
   Cla add22(.num1(htmp), .num2(4'b0000), .cin(lc), .out(y2), .car());
   Cla add21(.num1(ltmp), .num2(comp), .cin(hc), .out(y1), .car());

   assign out[7:0] = {y2,y1};
   assign uf = !hc;
`ifdef FORMAL
   assert property (num1[7:4] > 9 ||
                    num1[3:0] > 9 ||
                    num2[7:4] > 9 ||
                    num2[3:0] > 9 ||
                    uf ||
                    ((num1[7:4] * 10) + num1[3:0]) - ((num2[7:4] * 10) + num2[3:0]) == ((out[7:4] * 10) + out[3:0]));
`endif

endmodule
module bcdsub(

 input [7:0]  num1,
 input [7:0]  num2,
 output [7:0] out,
 output       uf  );


   wire [3:0] x12;
   wire [3:0] x11;
   wire [3:0] x22;
   wire [3:0] x21;
   wire [3:0] y2;
   wire [3:0] y1;
   wire       lc;
   wire       hc;


   wire [3:0] htmp;
   wire [3:0] ltmp;





   wire [3:0] comp;



   assign x12[3:0] = num1[7:4];
   assign x11[3:0] = num1[3:0];
   assign x22[3:0] = ~(num2[7:4]);
   assign x21[3:0] = ~(num2[3:0]);

   Cla add12(.num1(x12), .num2(x22), .cin(1'b0), .out(htmp), .car(hc));
   Cla add11(.num1(x11), .num2(x21), .cin(1'b0), .out(ltmp), .car(lc));

   assign comp[3:0] = {!lc, 1'b0, !lc, 1'b0};
   Cla add22(.num1(htmp), .num2(4'b0000), .cin(lc), .out(y2), .car());
   Cla add21(.num1(ltmp), .num2(comp), .cin(hc), .out(y1), .car());

   assign out[7:0] = {y2,y1};
   assign uf = !hc;
`ifdef FORMAL
   assert property (num1[7:4] > 9 ||
                    num1[3:0] > 9 ||
                    num2[7:4] > 9 ||
                    num2[3:0] > 9 ||
                    uf ||
                    ((num1[7:4] * 10) + num1[3:0]) - ((num2[7:4] * 10) + num2[3:0]) == ((out[7:4] * 10) + out[3:0]));
`endif

endmodule