data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:12: Define or directive not defined: \'`RegAddrWidth\'\n        input wire[`RegAddrWidth-1:0] waddr,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:13: Define or directive not defined: \'`RegDataWidth\'\n        input wire[`RegDataWidth-1:0] wdata,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:17: Define or directive not defined: \'`RegAddrWidth\'\n        input wire[`RegAddrWidth-1:0] raddr1,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:18: Define or directive not defined: \'`RegDataWidth\'\n        output reg[`RegDataWidth-1:0] rdata1,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:22: Define or directive not defined: \'`RegAddrWidth\'\n        input wire[`RegAddrWidth-1:0] raddr2,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:23: Define or directive not defined: \'`RegDataWidth\'\n        output reg[`RegDataWidth-1:0] rdata2\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:26: Define or directive not defined: \'`RegDataWidth\'\n    reg[`RegDataWidth-1:0] regs[0:`RegNum-1];\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:26: Define or directive not defined: \'`RegNum\'\n    reg[`RegDataWidth-1:0] regs[0:`RegNum-1];\n                                  ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:30: Define or directive not defined: \'`RegNum\'\n  for(i = 0; i < `RegNum; i=i+1) begin\n                 ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  for(i = 0; i < `RegNum; i=i+1) begin\n                        ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:30: syntax error, unexpected \')\', expecting \';\'\n  for(i = 0; i < `RegNum; i=i+1) begin\n                               ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:31: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0, regs[i]);\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:38: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:41: Define or directive not defined: \'`WriteEnable\'\n            if (we == `WriteEnable && waddr != `ZeroRegAddr) begin\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:41: Define or directive not defined: \'`ZeroRegAddr\'\n            if (we == `WriteEnable && waddr != `ZeroRegAddr) begin\n                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:50: Define or directive not defined: \'`RstEnable\'\n        if (rst == `RstEnable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:51: Define or directive not defined: \'`ZeroWord\'\n            rdata1 <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:52: Define or directive not defined: \'`ReadDisable\'\n        end else if (re1 == `ReadDisable) begin\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:53: Define or directive not defined: \'`ZeroWord\'\n            rdata1 <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:54: Define or directive not defined: \'`ZeroRegAddr\'\n        end else if (raddr1 == `ZeroRegAddr) begin\n                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:55: Define or directive not defined: \'`ZeroWord\'\n            rdata1 <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:56: Define or directive not defined: \'`WriteEnable\'\n        end else if (raddr1 == waddr && we == `WriteEnable) begin\n                                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:66: Define or directive not defined: \'`RstEnable\'\n        if (rst == `RstEnable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:67: Define or directive not defined: \'`ZeroWord\'\n            rdata2 <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:68: Define or directive not defined: \'`ReadDisable\'\n        end else if (re2 == `ReadDisable) begin\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:69: Define or directive not defined: \'`ZeroWord\'\n            rdata2 <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:70: Define or directive not defined: \'`ZeroRegAddr\'\n        end else if (raddr2 == `ZeroRegAddr) begin\n                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:71: Define or directive not defined: \'`ZeroWord\'\n            rdata2 <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:72: Define or directive not defined: \'`WriteEnable\'\n        end else if (raddr2 == waddr && we == `WriteEnable) begin\n                                              ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module regfile(
        input wire clk,
        input wire rst,
		input wire[5:0] stall,
        

        input wire we,
        input wire[`RegAddrWidth-1:0] waddr,
        input wire[`RegDataWidth-1:0] wdata,
        

        input wire re1,
        input wire[`RegAddrWidth-1:0] raddr1,
        output reg[`RegDataWidth-1:0] rdata1,
        

        input wire re2,
        input wire[`RegAddrWidth-1:0] raddr2,
        output reg[`RegDataWidth-1:0] rdata2
    );
    
    reg[`RegDataWidth-1:0] regs[0:`RegNum-1];

	integer i;
	initial begin
		for(i = 0; i < `RegNum; i=i+1) begin
			$dumpvars(0, regs[i]);
		end
	end
    

    always @ (posedge clk) 
    begin
		if (rst == `RstEnable) begin

		end else if(!stall[5]) begin
            if (we == `WriteEnable && waddr != `ZeroRegAddr) begin
                regs[waddr] <= wdata;
            end
		end 
    end
    

    always @(*) 
    begin
        if (rst == `RstEnable) begin
            rdata1 <= `ZeroWord;
        end else if (re1 == `ReadDisable) begin
            rdata1 <= `ZeroWord;
        end else if (raddr1 == `ZeroRegAddr) begin
            rdata1 <= `ZeroWord;
        end else if (raddr1 == waddr && we == `WriteEnable) begin
            rdata1 <= wdata;
        end else begin
            rdata1 <= regs[raddr1];
        end
    end
    

    always @(*) 
    begin
        if (rst == `RstEnable) begin
            rdata2 <= `ZeroWord;
        end else if (re2 == `ReadDisable) begin
            rdata2 <= `ZeroWord;
        end else if (raddr2 == `ZeroRegAddr) begin
            rdata2 <= `ZeroWord;
        end else if (raddr2 == waddr && we == `WriteEnable) begin
            rdata2 <= wdata;
        end else begin
            rdata2 <= regs[raddr2];
        end
    end
endmodule
module regfile(
        input wire clk,
        input wire rst,
		input wire[5:0] stall,
        

        input wire we,
        input wire[`RegAddrWidth-1:0] waddr,
        input wire[`RegDataWidth-1:0] wdata,
        

        input wire re1,
        input wire[`RegAddrWidth-1:0] raddr1,
        output reg[`RegDataWidth-1:0] rdata1,
        

        input wire re2,
        input wire[`RegAddrWidth-1:0] raddr2,
        output reg[`RegDataWidth-1:0] rdata2
    );

    
    reg[`RegDataWidth-1:0] regs[0:`RegNum-1];

	integer i;
	initial begin
		for(i = 0; i < `RegNum; i=i+1) begin
			$dumpvars(0, regs[i]);
		end
	end
    

    always @ (posedge clk) 
    begin
		if (rst == `RstEnable) begin

		end else if(!stall[5]) begin
            if (we == `WriteEnable && waddr != `ZeroRegAddr) begin
                regs[waddr] <= wdata;
            end
		end 
    end
    

    always @(*) 
    begin
        if (rst == `RstEnable) begin
            rdata1 <= `ZeroWord;
        end else if (re1 == `ReadDisable) begin
            rdata1 <= `ZeroWord;
        end else if (raddr1 == `ZeroRegAddr) begin
            rdata1 <= `ZeroWord;
        end else if (raddr1 == waddr && we == `WriteEnable) begin
            rdata1 <= wdata;
        end else begin
            rdata1 <= regs[raddr1];
        end
    end
    

    always @(*) 
    begin
        if (rst == `RstEnable) begin
            rdata2 <= `ZeroWord;
        end else if (re2 == `ReadDisable) begin
            rdata2 <= `ZeroWord;
        end else if (raddr2 == `ZeroRegAddr) begin
            rdata2 <= `ZeroWord;
        end else if (raddr2 == waddr && we == `WriteEnable) begin
            rdata2 <= wdata;
        end else begin
            rdata2 <= regs[raddr2];
        end
    end
endmodule