data/full_repos/permissive/188595972/src/lib.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/188595972/src/lib.v:31: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'InputToASCII\'\nmodule InputToASCII(keyboard,ascii,e);\n       ^~~~~~~~~~~~\n                                                                    : ... Top module \'EightSegDisplayment\'\nmodule EightSegDisplayment(segmentSelect,bitSelect_m,data,clk,rst_n);\n       ^~~~~~~~~~~~~~~~~~~\n                                                                    : ... Top module \'KeyboardScaner\'\nmodule KeyboardScaner(Yin,clk,rst_n,Xout,data);\n       ^~~~~~~~~~~~~~\n                                                                    : ... Top module \'SerialClockModule\'\nmodule SerialClockModule(e,clk,rst_n,out,half);\n       ^~~~~~~~~~~~~~~~~\n                                                                    : ... Top module \'AShiftReg\'\nmodule AShiftReg(Di,D,e,set,clk,rst_n,Q);\n       ^~~~~~~~~\n                                                                    : ... Top module \'NegedgeDetector\'\nmodule NegedgeDetector(i,clk,rst_n,neg);\n       ^~~~~~~~~~~~~~~\n                                                                    : ... Top module \'JK_FF\'\nmodule JK_FF(J,K,clk,rst_n,Q);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/188595972/src/lib.v:182: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                  : ... In instance NegedgeDetector\n        if(!rst_n) negCache<=2\'d0;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/188595972/src/lib.v:187: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                  : ... In instance NegedgeDetector\n        Y={negCache[0],|antiVibrationQ};\n         ^\n%Warning-WIDTH: data/full_repos/permissive/188595972/src/lib.v:47: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'num\' generates 2 bits.\n                                                                 : ... In instance EightSegDisplayment\n        case(num)\n        ^~~~\n%Error: Exiting due to 4 warning(s)\n'
module InputToASCII(keyboard,ascii,e);
    input [15:0]keyboard;
    output reg [7:0]ascii;
    output e;
    wire [3:0]num;
    wire [15:0]keyboard_n;
    
    assign keyboard_n=~keyboard;
    PriorityEncoder pe(keyboard_n,num,e);
    always@(num)
      case(num)
        4'hf:ascii=8'd55;
        4'he:ascii=8'd52;
        4'hd:ascii=8'd49;
        4'hc:ascii=8'd0;
        4'hb:ascii=8'd56;
        4'ha:ascii=8'd53;
        4'h9:ascii=8'd50;
        4'h8:ascii=8'd48;
        4'h7:ascii=8'd57;
        4'h6:ascii=8'd54;
        4'h5:ascii=8'd51;
        4'h4:ascii=8'd61;
        4'h3:ascii=8'd43;
        4'h2:ascii=8'd45;
        4'h1:ascii=8'd42;
        4'h0:ascii=8'd47;
      endcase
    endmodule
module InputToASCII(keyboard,ascii,e);

    input [15:0]keyboard;
    output reg [7:0]ascii;
    output e;
    wire [3:0]num;
    wire [15:0]keyboard_n;
    
    assign keyboard_n=~keyboard;
    PriorityEncoder pe(keyboard_n,num,e);
    always@(num)
      case(num)
        4'hf:ascii=8'd55;
        4'he:ascii=8'd52;
        4'hd:ascii=8'd49;
        4'hc:ascii=8'd0;
        4'hb:ascii=8'd56;
        4'ha:ascii=8'd53;
        4'h9:ascii=8'd50;
        4'h8:ascii=8'd48;
        4'h7:ascii=8'd57;
        4'h6:ascii=8'd54;
        4'h5:ascii=8'd51;
        4'h4:ascii=8'd61;
        4'h3:ascii=8'd43;
        4'h2:ascii=8'd45;
        4'h1:ascii=8'd42;
        4'h0:ascii=8'd47;
      endcase
    endmodule