data/full_repos/permissive/196851857/datapath/datapath.v
None: at end of input
1: b'%Error: data/full_repos/permissive/196851857/datapath/datapath.v:1: Cannot find include file: ..\\\\control\\\\ctrl_signals_def.v\n`include "..\\\\control\\\\ctrl_signals_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/196851857/datapath,data/full_repos/permissive/196851857/..\\\\control\\\\ctrl_signals_def.v\n             data/full_repos/permissive/196851857/datapath,data/full_repos/permissive/196851857/..\\\\control\\\\ctrl_signals_def.v.v\n             data/full_repos/permissive/196851857/datapath,data/full_repos/permissive/196851857/..\\\\control\\\\ctrl_signals_def.v.sv\n             ..\\\\control\\\\ctrl_signals_def.v\n             ..\\\\control\\\\ctrl_signals_def.v.v\n             ..\\\\control\\\\ctrl_signals_def.v.sv\n             obj_dir/..\\\\control\\\\ctrl_signals_def.v\n             obj_dir/..\\\\control\\\\ctrl_signals_def.v.v\n             obj_dir/..\\\\control\\\\ctrl_signals_def.v.sv\n%Error: data/full_repos/permissive/196851857/datapath/datapath.v:50: Define or directive not defined: \'`RwIdSrc_ra\'\n  assign rw = (RwIdSrc == `RwIdSrc_ra) ? `ra : \n                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/datapath.v:50: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  assign rw = (RwIdSrc == `RwIdSrc_ra) ? `ra : \n                                     ^\n%Error: data/full_repos/permissive/196851857/datapath/datapath.v:50: Define or directive not defined: \'`ra\'\n  assign rw = (RwIdSrc == `RwIdSrc_ra) ? `ra : \n                                         ^~~\n%Error: data/full_repos/permissive/196851857/datapath/datapath.v:51: Define or directive not defined: \'`RwIdSrc_rd\'\n              ((RwIdSrc == `RwIdSrc_rd) ? rd : rt);\n                           ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module datapath(
  input clk, rst,
  
  input RegWrite,
  input [1:0] RwIdSrc, RwDataSrc,

  input MemRead, MemWrite, MemOpType,

  input [2:0] BranchType,
  input [1:0] JumpType,

  input [4:0] AluCtr,
  input [1:0] AluBSrc,
  
  input ExtType, MemDataExtType,
  
  output [5:0] opcode, funct,
  output bit16
);
  wire [31:0] PC, NPC, NormalNPC;


  pc pc(.NPC(NPC), .PC(PC), .rst(rst), .clk(clk));

  wire [31:0] Instruction;

  im_4k im(.addr(PC[11:2]), .dout(Instruction));
  
  wire [4:0] rs, rt, rd;
  wire [4:0] shamt;
  wire [15:0] imm16_or_offset;
  wire [25:0] PseudoAddr;


  instruction instruction(
    Instruction,
    opcode,
    rs, rt, rd, 
    shamt,
    funct,
    imm16_or_offset, 
    PseudoAddr,
    bit16
  );


  wire [4:0]rw;
  wire [31:0]rsVal, rtVal, regWriteData;
  assign rw = (RwIdSrc == `RwIdSrc_ra) ? `ra : 
              ((RwIdSrc == `RwIdSrc_rd) ? rd : rt);
  regfiles regfiles(
    .writeEn(RegWrite), .rw(rw), .busW(regWriteData),
    .ra(rs), .rb(rt), .busA(rsVal), .busB(rtVal),
    .clk(clk)
  );
  
  wire [31:0] imm32_or_offset, lui_imm;
  wire [31:0] AluB;
  
  ext imm_ext(
    .in(imm16_or_offset),
    .out(imm32_or_offset),
    .ExtType(ExtType)
   );
  assign lui_imm = { imm16_or_offset, 16'b0 };
  

  mux4 alub_mux(
    .i00(rtVal),
    .i01(imm32_or_offset),
    .i10(32'd0),
    .i11(lui_imm),
    .sel(AluBSrc),
    .out(AluB)
  );
  

  wire zero, pos, neg;
  wire [31:0] alu_res;
  alu alu(
    .A(rsVal), .B(AluB),
    .ALUctr(AluCtr), 
    .result(alu_res),

    .zero(zero), .pos(pos), .neg(neg),
    .shamt(shamt)
  );
  
  wire [31:0] dm_read_data;
  dm_4k dm(
    .addr(alu_res[11:2]), .ByteOff(alu_res[1:0]),
    .wr_en(MemWrite), .d_in(rtVal),
    .d_out(dm_read_data),
    .MemOpType(MemOpType), .MemDataExtType(MemDataExtType),
    .clk(clk)
  );
  

  mux4 sel_regWriteData(
    .i00(alu_res),
    .i01(dm_read_data),
    .i10(NormalNPC),
    .i11(32'hxxxx_xxxx),
    .sel(RwDataSrc),
    .out(regWriteData)
  );
  

  npc npc(
    .PC(PC),
    .PseudoAddr(PseudoAddr),
    .offset(imm16_or_offset), 
    .RegTypeNPC(rsVal),
    .BranchType(BranchType),
    .JumpType(JumpType),

    .zero(zero), .pos(pos), .neg(neg),
    .NPC(NPC),
    .NormalNPC(NormalNPC)
  );
endmodule
module datapath(
  input clk, rst,
  
  input RegWrite,
  input [1:0] RwIdSrc, RwDataSrc,

  input MemRead, MemWrite, MemOpType,

  input [2:0] BranchType,
  input [1:0] JumpType,

  input [4:0] AluCtr,
  input [1:0] AluBSrc,
  
  input ExtType, MemDataExtType,
  
  output [5:0] opcode, funct,
  output bit16
);

  wire [31:0] PC, NPC, NormalNPC;


  pc pc(.NPC(NPC), .PC(PC), .rst(rst), .clk(clk));

  wire [31:0] Instruction;

  im_4k im(.addr(PC[11:2]), .dout(Instruction));
  
  wire [4:0] rs, rt, rd;
  wire [4:0] shamt;
  wire [15:0] imm16_or_offset;
  wire [25:0] PseudoAddr;


  instruction instruction(
    Instruction,
    opcode,
    rs, rt, rd, 
    shamt,
    funct,
    imm16_or_offset, 
    PseudoAddr,
    bit16
  );


  wire [4:0]rw;
  wire [31:0]rsVal, rtVal, regWriteData;
  assign rw = (RwIdSrc == `RwIdSrc_ra) ? `ra : 
              ((RwIdSrc == `RwIdSrc_rd) ? rd : rt);
  regfiles regfiles(
    .writeEn(RegWrite), .rw(rw), .busW(regWriteData),
    .ra(rs), .rb(rt), .busA(rsVal), .busB(rtVal),
    .clk(clk)
  );
  
  wire [31:0] imm32_or_offset, lui_imm;
  wire [31:0] AluB;
  
  ext imm_ext(
    .in(imm16_or_offset),
    .out(imm32_or_offset),
    .ExtType(ExtType)
   );
  assign lui_imm = { imm16_or_offset, 16'b0 };
  

  mux4 alub_mux(
    .i00(rtVal),
    .i01(imm32_or_offset),
    .i10(32'd0),
    .i11(lui_imm),
    .sel(AluBSrc),
    .out(AluB)
  );
  

  wire zero, pos, neg;
  wire [31:0] alu_res;
  alu alu(
    .A(rsVal), .B(AluB),
    .ALUctr(AluCtr), 
    .result(alu_res),

    .zero(zero), .pos(pos), .neg(neg),
    .shamt(shamt)
  );
  
  wire [31:0] dm_read_data;
  dm_4k dm(
    .addr(alu_res[11:2]), .ByteOff(alu_res[1:0]),
    .wr_en(MemWrite), .d_in(rtVal),
    .d_out(dm_read_data),
    .MemOpType(MemOpType), .MemDataExtType(MemDataExtType),
    .clk(clk)
  );
  

  mux4 sel_regWriteData(
    .i00(alu_res),
    .i01(dm_read_data),
    .i10(NormalNPC),
    .i11(32'hxxxx_xxxx),
    .sel(RwDataSrc),
    .out(regWriteData)
  );
  

  npc npc(
    .PC(PC),
    .PseudoAddr(PseudoAddr),
    .offset(imm16_or_offset), 
    .RegTypeNPC(rsVal),
    .BranchType(BranchType),
    .JumpType(JumpType),

    .zero(zero), .pos(pos), .neg(neg),
    .NPC(NPC),
    .NormalNPC(NormalNPC)
  );
endmodule