data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/generator_top_3.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/generator_top_3.v:16: Operator ASSIGN expects 224 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                        : ... In instance generator_top_3\n  reg [223:0] M_leftedcols_d, M_leftedcols_q = 1\'h0;\n                                               ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/generator_top_3.v:17: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                        : ... In instance generator_top_3\n  reg [29:0] M_counter_d, M_counter_q = 1\'h0;\n                                        ^~~~\n%Error: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/generator_top_3.v:19: Cannot find file containing module: \'randomNumGen_20\'\n  randomNumGen_20 rng (\n  ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/randomNumGen_20\n             data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/randomNumGen_20.v\n             data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/randomNumGen_20.sv\n             randomNumGen_20\n             randomNumGen_20.v\n             randomNumGen_20.sv\n             obj_dir/randomNumGen_20\n             obj_dir/randomNumGen_20.v\n             obj_dir/randomNumGen_20.sv\n%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/generator_top_3.v:33: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                        : ... In instance generator_top_3\n    for (i = 1\'h0; i < 5\'h10; i = i + 1) begin\n           ^\n%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/generator_top_3.v:36: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                        : ... In instance generator_top_3\n    for (i = 1\'h0; i < 5\'h10; i = i + 1) begin\n           ^\n%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/generator_top_3.v:43: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                        : ... In instance generator_top_3\n    M_counter_d = 1\'h0;\n                ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module generator_top_3 (
    input clk,
    input rst,
    input [223:0] cols,
    output reg [223:0] colsout
  );
  
  
  
  reg [223:0] M_leftedcols_d, M_leftedcols_q = 1'h0;
  reg [29:0] M_counter_d, M_counter_q = 1'h0;
  wire [4-1:0] M_rng_out;
  randomNumGen_20 rng (
    .clk(clk),
    .rst(rst),
    .out(M_rng_out)
  );
  
  integer i;
  
  reg [3:0] random;
  
  always @* begin
    M_leftedcols_d = M_leftedcols_q;
    M_counter_d = M_counter_q;
    
    for (i = 1'h0; i < 5'h10; i = i + 1) begin
      colsout[(i)*14+13-:14] = 14'h0000;
    end
    for (i = 1'h0; i < 5'h10; i = i + 1) begin
      M_leftedcols_d[(i)*14+13-:14] = cols[(i)*14+13-:14] << 1'h1;
    end
    M_counter_d = M_counter_q + 1'h1;
    random = M_rng_out[0+3-:4];
    M_leftedcols_d[(random)*14+13-:14] = M_leftedcols_q[(random)*14+13-:14] + 14'h0001;
    colsout = M_leftedcols_q;
    M_counter_d = 1'h0;
  end
  
  always @(posedge clk) begin
    M_leftedcols_q <= M_leftedcols_d;
    M_counter_q <= M_counter_d;
  end
  
endmodule
module generator_top_3 (
    input clk,
    input rst,
    input [223:0] cols,
    output reg [223:0] colsout
  );

  
  
  
  reg [223:0] M_leftedcols_d, M_leftedcols_q = 1'h0;
  reg [29:0] M_counter_d, M_counter_q = 1'h0;
  wire [4-1:0] M_rng_out;
  randomNumGen_20 rng (
    .clk(clk),
    .rst(rst),
    .out(M_rng_out)
  );
  
  integer i;
  
  reg [3:0] random;
  
  always @* begin
    M_leftedcols_d = M_leftedcols_q;
    M_counter_d = M_counter_q;
    
    for (i = 1'h0; i < 5'h10; i = i + 1) begin
      colsout[(i)*14+13-:14] = 14'h0000;
    end
    for (i = 1'h0; i < 5'h10; i = i + 1) begin
      M_leftedcols_d[(i)*14+13-:14] = cols[(i)*14+13-:14] << 1'h1;
    end
    M_counter_d = M_counter_q + 1'h1;
    random = M_rng_out[0+3-:4];
    M_leftedcols_d[(random)*14+13-:14] = M_leftedcols_q[(random)*14+13-:14] + 14'h0001;
    colsout = M_leftedcols_q;
    M_counter_d = 1'h0;
  end
  
  always @(posedge clk) begin
    M_leftedcols_q <= M_leftedcols_d;
    M_counter_q <= M_counter_d;
  end
  
endmodule