data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v
 line:54: before: ";"
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v:60: syntax error, unexpected \'@\'\n    @(uart_tx); \n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v:63: syntax error, unexpected \'@\'\n           @(uart_tx);\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #(uart_baudrate_period_ns+(uart_baudrate_period_ns/2));\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #uart_baudrate_period_ns;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #uart_baudrate_period_ns;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #uart_baudrate_period_ns;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #uart_baudrate_period_ns;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #uart_baudrate_period_ns;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #uart_baudrate_period_ns;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #uart_baudrate_period_ns;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #uart_baudrate_period_ns;\n  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/bench/uart_decoder.v:86: syntax error, unexpected \'@\'\n  @(uart_tx);\n  ^\n%Error: Exiting due to 3 error(s), 9 warning(s)\n'
module uart_decoder(clk, uart_tx);

   input clk;   
   input uart_tx;


   parameter uart_baudrate_period_ns = 8680; 


   always @(posedge clk)
     uart_decoder;
   
   task uart_decoder;
      reg [7:0] tx_byte;
      begin
	 while (uart_tx !== 1'b1)
	   @(uart_tx); 

	 while (uart_tx !== 1'b0)
           @(uart_tx);
	 #(uart_baudrate_period_ns+(uart_baudrate_period_ns/2));
	 tx_byte[0] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[1] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[2] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[3] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[4] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[5] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[6] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[7] = uart_tx;
	 #uart_baudrate_period_ns;

	 if (uart_tx !== 1'b1)
	   begin

	      while (uart_tx !== 1'b1)
		@(uart_tx);
	   end

	 $write("%c", tx_byte);
      end
   endtask

endmodule
module uart_decoder(clk, uart_tx);


   input clk;   
   input uart_tx;


   parameter uart_baudrate_period_ns = 8680; 


   always @(posedge clk)
     uart_decoder;
   
   task uart_decoder;
      reg [7:0] tx_byte;
      begin
	 while (uart_tx !== 1'b1)
	   @(uart_tx); 

	 while (uart_tx !== 1'b0)
           @(uart_tx);
	 #(uart_baudrate_period_ns+(uart_baudrate_period_ns/2));
	 tx_byte[0] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[1] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[2] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[3] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[4] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[5] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[6] = uart_tx;
	 #uart_baudrate_period_ns;
	 tx_byte[7] = uart_tx;
	 #uart_baudrate_period_ns;

	 if (uart_tx !== 1'b1)
	   begin

	      while (uart_tx !== 1'b1)
		@(uart_tx);
	   end

	 $write("%c", tx_byte);
      end
   endtask

endmodule