data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/controller.v
 line:507: before: ","
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/controller.v:542: Cannot find file containing module: 'counter'\n counter COUNTtRAS (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/counter\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/counter.v\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/controller.v:582: Cannot find file containing module: 'counter'\n counter COUNTtRFC (\n ^~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/controller.v:592: Cannot find file containing module: 'counter'\n counter COUNT200 (\n ^~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/controller.v:603: Cannot find file containing module: 'genrefresh'\n genrefresh GRFC0 (\n ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module controller (
		clock_i,
		reset_i,
		
		ddr_cke_o,
		
		ddr_cs_no,
		ddr_ras_no,
		ddr_cas_no,
		ddr_we_no,
		
		ddr_ba_o,
		ddr_a_o,
		
		init_done_o,
		
		cmd_start_i,
		cmd_read_i,
		cmd_last_i,
		cmd_active_o,
		cmd_exec_o,
		cmd_bank_i,
		cmd_row_i,
		cmd_col_i,
		
		data_read_o,
		data_write_o,
		
		rfc_req_o,
		rfc_start_i,
		rfc_done_o
	);
	
	parameter	RFC_TICKS	= 1040;
	
	input	clock_i;
	input	reset_i;
	

	output	ddr_cke_o;
	

	output	ddr_cs_no;
	output	ddr_ras_no;
	output	ddr_cas_no;
	output	ddr_we_no;
	

	output	[1:0]	ddr_ba_o;
	output	[12:0]	ddr_a_o;
	

	output	init_done_o;
	

	input	cmd_start_i;
	input	cmd_read_i;
	input	cmd_last_i;
	output	cmd_active_o;
	output	cmd_exec_o;
	input	[1:0]	cmd_bank_i;
	input	[12:0]	cmd_row_i;
	input	[7:0]	cmd_col_i;
	
	output	data_read_o;
	output	data_write_o;
	

	output	rfc_req_o;
	input	rfc_start_i;
	output	rfc_done_o;
	
	
	


`define	DDRST_INIT	4'b1111
`define	DDRST_IDLE	4'b0111
`define	DDRST_NOP	4'b0111
`define	DDRST_LOADMODE	4'b0000
`define	DDRST_MODEWAIT	4'b1000
`define	DDRST_RFCSTART	4'b0001
`define	DDRST_RFCWAIT	4'b1001
`define	DDRST_ACTIVE	4'b0011
`define	DDRST_READ	4'b0101
`define	DDRST_WRITE	4'b0100
`define	DDRST_PRECHARGE	4'b0010
`define	DDRST_PREWAIT	4'b1010
	
	



	

	wire	ddr_cke_o;
	wire	ddr_cs_no;
	

	


	reg	ddr_ras_n	= 1;
	reg	ddr_cas_n	= 1;
	reg	ddr_we_n	= 1;
	
	reg	[1:0]	ddr_ba	= 0;
	reg	[12:0]	ddr_a	= 0;
	




	reg	[3:0]	state		= `DDRST_INIT;
	reg	[3:0]	next_state	= `DDRST_INIT;
	

	reg	[3:0]	init_state	= 0;
	wire	init_done	= (init_state == 4'd9);
	

	reg	[1:0]	mrd_addr	= 0;
	
	wire	count200_start	= (state == `DDRST_INIT) & (init_state == 4'h4);
	wire	count200_done;
	

	reg	refresh_en	= 0;
	wire	refresh_start;
	wire	refresh_ack	= (state == `DDRST_RFCSTART);
	
	reg	[8:0]	col_addr	= 0;
	
	wire	tRAS_done;
	wire	tRC_done;
	wire	tREFI;
	
	
	













	always @(posedge clock_i)
	begin
		if (reset_i)
		begin
			state		<= `DDRST_INIT;
			next_state	<= `DDRST_INIT;
			init_state	<= 0;
		end
		else
		begin
			case (state)
			


			`DDRST_INIT:
			begin
				case (init_state)
				

				4'h0:	init_state	<= init_state + 1;
				

				4'h1:
				begin
					state	<= `DDRST_PRECHARGE;
					init_state	<= init_state + 1;
				end
				

				4'h2:
				begin
					state	<= `DDRST_LOADMODE;
					init_state	<= init_state + 1;
				end
				

				4'h3:
				begin
					state	<= `DDRST_LOADMODE;
					init_state	<= init_state + 1;
				end
				

				4'h4:	init_state	<= init_state + 1;
				

				4'h5:
				if (count200_done)
				begin
					init_state	<= init_state + 1;
					state		<= `DDRST_PRECHARGE;
				end
				

				4'h6:
				begin
					init_state	<= init_state + 1;
					state		<= `DDRST_RFCSTART;
				end
				

				4'h7:
				begin
					init_state	<= init_state + 1;
					state		<= `DDRST_RFCSTART;
				end
				

				4'h8:
				begin
					init_state	<= init_state + 1;
					state		<= `DDRST_LOADMODE;
				end
				

				default:
				begin
					state		<= `DDRST_IDLE;
					next_state	<= `DDRST_IDLE;
				end
				
				endcase
			end
			

			`DDRST_IDLE:
			begin
				if (rfc_start_i)
					state	<= `DDRST_RFCSTART;
				else if (state != next_state)
					state	<= next_state;
				else if (cmd_start_i && tRC_done)
				begin


					state		<= `DDRST_ACTIVE;

					if (cmd_read_i)
						next_state	<= `DDRST_READ;
					else
						next_state	<= `DDRST_WRITE;
				end
				else
					state	<= state;
			end
			



			`DDRST_LOADMODE:
			begin
				state		<= `DDRST_NOP;
				next_state	<= `DDRST_INIT;
			end
			

			`DDRST_RFCSTART:
				state	<= `DDRST_RFCWAIT;
			

			`DDRST_RFCWAIT:
			begin
				if (rfc_done_o)
					state	<= `DDRST_IDLE;
				else
					state	<= state;
			end
			


			`DDRST_PRECHARGE:
			begin
				state		<= `DDRST_NOP;

			end
			



			`DDRST_ACTIVE:
				state	<= `DDRST_NOP;
			

			`DDRST_READ:
			begin
				if (cmd_last_i)
				begin
					state		<= `DDRST_IDLE;
					next_state	<= `DDRST_IDLE;
				end
			end
			

			`DDRST_WRITE:
			begin
				if (cmd_last_i)
				begin
					state		<= `DDRST_IDLE;
					next_state	<= `DDRST_IDLE;
				end
			end
			
			default:;
			
			endcase
		end
	end
	
	
	



	


	always @(posedge clock_i)
	begin
		if (reset_i)
		begin
			ddr_ras_n	<= 1;
			ddr_cas_n	<= 1;
			ddr_we_n	<= 1;
		end
		else
		begin
			if (state [3] == 0)
			begin
				ddr_ras_n	<= state [2];
				ddr_cas_n	<= state [1];
				ddr_we_n	<= state [0];
			end
			else
			begin
				ddr_ras_n	<= 1;
				ddr_cas_n	<= 1;
				ddr_we_n	<= 1;
			end
		end
	end
	
	










	always @(posedge clock_i)
	begin
		if (reset_i)
			mrd_addr	<= 0;
		else
		begin
			if (state == `DDRST_LOADMODE)
			begin
				case (mrd_addr)
				

				2'b00:
					{ddr_ba, ddr_a}	<= 15'b01_00000_0000_0010;
				

				2'b01:
					{ddr_ba, ddr_a}	<= 15'b00_000010_010_0_001;
				

				default:
					{ddr_ba, ddr_a}	<= 15'b00_000000_010_0_001;
				
				endcase
				
				mrd_addr	<= mrd_addr + 1;
			end
			else
			begin
				ddr_ba	<= cmd_bank_i;
				
				if (state == `DDRST_READ || state == `DDRST_WRITE)
					ddr_a	<= {2'b00, cmd_last_i, 1'b0, cmd_col_i, 1'b0};
				else if (state == `DDRST_PRECHARGE)
					ddr_a	<= 13'b0_0100_0000_0000;
				else
					ddr_a	<= cmd_row_i;
			end
		end
	end
	
	

	
	assign	ddr_ras_no	= ddr_ras_n;
	assign	ddr_cas_no	= ddr_cas_n;
	assign	ddr_we_no	= ddr_we_n;
	
	assign	ddr_ba_o	= ddr_ba;
	assign	ddr_a_o		= ddr_a;
	
	




	reg	init_done0	= 0, init_done1	= 0, init_done2	= 0;
	always @(posedge clock_i)
	begin
		init_done0	<= init_done;
		init_done1	<= init_done0;
		init_done2	<= init_done1;
	end
	
	
	assign	init_done_o	= init_done2;
	
	assign	ddr_cke_o	= ~reset_i;
	assign	ddr_cs_no	= reset_i;
	


	assign	cmd_exec_o	= (state == `DDRST_READ) | (state == `DDRST_WRITE);
	assign	cmd_active_o	= (state == `DDRST_ACTIVE);
	

	assign	data_read_o	= (state == `DDRST_READ);
	assign	data_write_o	= (state == `DDRST_WRITE);
	

	assign	rfc_req_o	= tREFI & tRC_done;
	
	
	



	

	defparam	COUNTtRAS.COUNT	= `tRAS_COUNT;
	defparam	COUNTtRAS.BITS	= `tRAS_BITS;
	counter COUNTtRAS (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		.start_i	(state == `DDRST_ACTIVE),
		.done_o		(tRAS_done)
	);
	
	

	reg	[`tRC_BITS-1:0]	tRC_count	= 0;
	always @(posedge clock_i)
	begin
		if (reset_i)
			tRC_count	<= 0;
		else
		begin
			if (state == `DDRST_ACTIVE)
				tRC_count	<= `tRC_COUNT - 1;
			else if (tRC_count != 0)
				tRC_count	<= tRC_count - 1;
			else
				tRC_count	<= tRC_count - 1;
		end
	end
	
	assign	tRC_done	= (tRC_count == 0);

	

	defparam	COUNTtRFC.COUNT	= `tRFC_COUNT;
	defparam	COUNTtRFC.BITS	= `tRFC_BITS;
	counter COUNTtRFC (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		.start_i	(state == `DDRST_RFCSTART),
		.done_o		(rfc_done_o)
	);
	

	defparam	COUNT200.COUNT	= 200;
	defparam	COUNT200.BITS	= 8;
	counter COUNT200 (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		.start_i	(count200_start),
		.done_o		(count200_done)
	);
	
	

	defparam	GRFC0.TICKS	= RFC_TICKS;
	defparam	GRFC0.BITS	= 11;
	genrefresh GRFC0 (
		.clock_i	(clock_i),
		.reset_ni	(init_done_o),
		.refresh_o	(tREFI),
		.ack_i		(state == `DDRST_RFCSTART)
	);
	
endmodule
module controller (
		clock_i,
		reset_i,
		
		ddr_cke_o,
		
		ddr_cs_no,
		ddr_ras_no,
		ddr_cas_no,
		ddr_we_no,
		
		ddr_ba_o,
		ddr_a_o,
		
		init_done_o,
		
		cmd_start_i,
		cmd_read_i,
		cmd_last_i,
		cmd_active_o,
		cmd_exec_o,
		cmd_bank_i,
		cmd_row_i,
		cmd_col_i,
		
		data_read_o,
		data_write_o,
		
		rfc_req_o,
		rfc_start_i,
		rfc_done_o
	);

	
	parameter	RFC_TICKS	= 1040;
	
	input	clock_i;
	input	reset_i;
	

	output	ddr_cke_o;
	

	output	ddr_cs_no;
	output	ddr_ras_no;
	output	ddr_cas_no;
	output	ddr_we_no;
	

	output	[1:0]	ddr_ba_o;
	output	[12:0]	ddr_a_o;
	

	output	init_done_o;
	

	input	cmd_start_i;
	input	cmd_read_i;
	input	cmd_last_i;
	output	cmd_active_o;
	output	cmd_exec_o;
	input	[1:0]	cmd_bank_i;
	input	[12:0]	cmd_row_i;
	input	[7:0]	cmd_col_i;
	
	output	data_read_o;
	output	data_write_o;
	

	output	rfc_req_o;
	input	rfc_start_i;
	output	rfc_done_o;
	
	
	


`define	DDRST_INIT	4'b1111
`define	DDRST_IDLE	4'b0111
`define	DDRST_NOP	4'b0111
`define	DDRST_LOADMODE	4'b0000
`define	DDRST_MODEWAIT	4'b1000
`define	DDRST_RFCSTART	4'b0001
`define	DDRST_RFCWAIT	4'b1001
`define	DDRST_ACTIVE	4'b0011
`define	DDRST_READ	4'b0101
`define	DDRST_WRITE	4'b0100
`define	DDRST_PRECHARGE	4'b0010
`define	DDRST_PREWAIT	4'b1010
	
	



	

	wire	ddr_cke_o;
	wire	ddr_cs_no;
	

	


	reg	ddr_ras_n	= 1;
	reg	ddr_cas_n	= 1;
	reg	ddr_we_n	= 1;
	
	reg	[1:0]	ddr_ba	= 0;
	reg	[12:0]	ddr_a	= 0;
	




	reg	[3:0]	state		= `DDRST_INIT;
	reg	[3:0]	next_state	= `DDRST_INIT;
	

	reg	[3:0]	init_state	= 0;
	wire	init_done	= (init_state == 4'd9);
	

	reg	[1:0]	mrd_addr	= 0;
	
	wire	count200_start	= (state == `DDRST_INIT) & (init_state == 4'h4);
	wire	count200_done;
	

	reg	refresh_en	= 0;
	wire	refresh_start;
	wire	refresh_ack	= (state == `DDRST_RFCSTART);
	
	reg	[8:0]	col_addr	= 0;
	
	wire	tRAS_done;
	wire	tRC_done;
	wire	tREFI;
	
	
	













	always @(posedge clock_i)
	begin
		if (reset_i)
		begin
			state		<= `DDRST_INIT;
			next_state	<= `DDRST_INIT;
			init_state	<= 0;
		end
		else
		begin
			case (state)
			


			`DDRST_INIT:
			begin
				case (init_state)
				

				4'h0:	init_state	<= init_state + 1;
				

				4'h1:
				begin
					state	<= `DDRST_PRECHARGE;
					init_state	<= init_state + 1;
				end
				

				4'h2:
				begin
					state	<= `DDRST_LOADMODE;
					init_state	<= init_state + 1;
				end
				

				4'h3:
				begin
					state	<= `DDRST_LOADMODE;
					init_state	<= init_state + 1;
				end
				

				4'h4:	init_state	<= init_state + 1;
				

				4'h5:
				if (count200_done)
				begin
					init_state	<= init_state + 1;
					state		<= `DDRST_PRECHARGE;
				end
				

				4'h6:
				begin
					init_state	<= init_state + 1;
					state		<= `DDRST_RFCSTART;
				end
				

				4'h7:
				begin
					init_state	<= init_state + 1;
					state		<= `DDRST_RFCSTART;
				end
				

				4'h8:
				begin
					init_state	<= init_state + 1;
					state		<= `DDRST_LOADMODE;
				end
				

				default:
				begin
					state		<= `DDRST_IDLE;
					next_state	<= `DDRST_IDLE;
				end
				
				endcase
			end
			

			`DDRST_IDLE:
			begin
				if (rfc_start_i)
					state	<= `DDRST_RFCSTART;
				else if (state != next_state)
					state	<= next_state;
				else if (cmd_start_i && tRC_done)
				begin


					state		<= `DDRST_ACTIVE;

					if (cmd_read_i)
						next_state	<= `DDRST_READ;
					else
						next_state	<= `DDRST_WRITE;
				end
				else
					state	<= state;
			end
			



			`DDRST_LOADMODE:
			begin
				state		<= `DDRST_NOP;
				next_state	<= `DDRST_INIT;
			end
			

			`DDRST_RFCSTART:
				state	<= `DDRST_RFCWAIT;
			

			`DDRST_RFCWAIT:
			begin
				if (rfc_done_o)
					state	<= `DDRST_IDLE;
				else
					state	<= state;
			end
			


			`DDRST_PRECHARGE:
			begin
				state		<= `DDRST_NOP;

			end
			



			`DDRST_ACTIVE:
				state	<= `DDRST_NOP;
			

			`DDRST_READ:
			begin
				if (cmd_last_i)
				begin
					state		<= `DDRST_IDLE;
					next_state	<= `DDRST_IDLE;
				end
			end
			

			`DDRST_WRITE:
			begin
				if (cmd_last_i)
				begin
					state		<= `DDRST_IDLE;
					next_state	<= `DDRST_IDLE;
				end
			end
			
			default:;
			
			endcase
		end
	end
	
	
	



	


	always @(posedge clock_i)
	begin
		if (reset_i)
		begin
			ddr_ras_n	<= 1;
			ddr_cas_n	<= 1;
			ddr_we_n	<= 1;
		end
		else
		begin
			if (state [3] == 0)
			begin
				ddr_ras_n	<= state [2];
				ddr_cas_n	<= state [1];
				ddr_we_n	<= state [0];
			end
			else
			begin
				ddr_ras_n	<= 1;
				ddr_cas_n	<= 1;
				ddr_we_n	<= 1;
			end
		end
	end
	
	










	always @(posedge clock_i)
	begin
		if (reset_i)
			mrd_addr	<= 0;
		else
		begin
			if (state == `DDRST_LOADMODE)
			begin
				case (mrd_addr)
				

				2'b00:
					{ddr_ba, ddr_a}	<= 15'b01_00000_0000_0010;
				

				2'b01:
					{ddr_ba, ddr_a}	<= 15'b00_000010_010_0_001;
				

				default:
					{ddr_ba, ddr_a}	<= 15'b00_000000_010_0_001;
				
				endcase
				
				mrd_addr	<= mrd_addr + 1;
			end
			else
			begin
				ddr_ba	<= cmd_bank_i;
				
				if (state == `DDRST_READ || state == `DDRST_WRITE)
					ddr_a	<= {2'b00, cmd_last_i, 1'b0, cmd_col_i, 1'b0};
				else if (state == `DDRST_PRECHARGE)
					ddr_a	<= 13'b0_0100_0000_0000;
				else
					ddr_a	<= cmd_row_i;
			end
		end
	end
	
	

	
	assign	ddr_ras_no	= ddr_ras_n;
	assign	ddr_cas_no	= ddr_cas_n;
	assign	ddr_we_no	= ddr_we_n;
	
	assign	ddr_ba_o	= ddr_ba;
	assign	ddr_a_o		= ddr_a;
	
	




	reg	init_done0	= 0, init_done1	= 0, init_done2	= 0;
	always @(posedge clock_i)
	begin
		init_done0	<= init_done;
		init_done1	<= init_done0;
		init_done2	<= init_done1;
	end
	
	
	assign	init_done_o	= init_done2;
	
	assign	ddr_cke_o	= ~reset_i;
	assign	ddr_cs_no	= reset_i;
	


	assign	cmd_exec_o	= (state == `DDRST_READ) | (state == `DDRST_WRITE);
	assign	cmd_active_o	= (state == `DDRST_ACTIVE);
	

	assign	data_read_o	= (state == `DDRST_READ);
	assign	data_write_o	= (state == `DDRST_WRITE);
	

	assign	rfc_req_o	= tREFI & tRC_done;
	
	
	



	

	defparam	COUNTtRAS.COUNT	= `tRAS_COUNT;
	defparam	COUNTtRAS.BITS	= `tRAS_BITS;
	counter COUNTtRAS (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		.start_i	(state == `DDRST_ACTIVE),
		.done_o		(tRAS_done)
	);
	
	

	reg	[`tRC_BITS-1:0]	tRC_count	= 0;
	always @(posedge clock_i)
	begin
		if (reset_i)
			tRC_count	<= 0;
		else
		begin
			if (state == `DDRST_ACTIVE)
				tRC_count	<= `tRC_COUNT - 1;
			else if (tRC_count != 0)
				tRC_count	<= tRC_count - 1;
			else
				tRC_count	<= tRC_count - 1;
		end
	end
	
	assign	tRC_done	= (tRC_count == 0);

	

	defparam	COUNTtRFC.COUNT	= `tRFC_COUNT;
	defparam	COUNTtRFC.BITS	= `tRFC_BITS;
	counter COUNTtRFC (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		.start_i	(state == `DDRST_RFCSTART),
		.done_o		(rfc_done_o)
	);
	

	defparam	COUNT200.COUNT	= 200;
	defparam	COUNT200.BITS	= 8;
	counter COUNT200 (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		.start_i	(count200_start),
		.done_o		(count200_done)
	);
	
	

	defparam	GRFC0.TICKS	= RFC_TICKS;
	defparam	GRFC0.BITS	= 11;
	genrefresh GRFC0 (
		.clock_i	(clock_i),
		.reset_ni	(init_done_o),
		.refresh_o	(tREFI),
		.ack_i		(state == `DDRST_RFCSTART)
	);
	
endmodule