data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/ece241_2014_q4.v
 line:230: before: "/"
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/ece241_2014_q4.v:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z'\n                                                                                                                                : ... In instance top_module\n    initial z = 1;\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Latches_Flip_Flops/ece241_2014_q4.v:12: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'z'\n                                                                                                                                 : ... In instance top_module\n        z = ~(out1 | out2 | out3);\n        ^\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input x,
    output z
); 
    reg out1=0, out2, out3;
    initial z = 1;
    always @(posedge clk) begin
        out1 = x ^ out1;
        out2 = x & ~out2;
        out3 = x | ~out3;
        z = ~(out1 | out2 | out3);
    end
endmodule
module top_module (
    input clk,
    input x,
    output z
);
 
    reg out1=0, out2, out3;
    initial z = 1;
    always @(posedge clk) begin
        out1 = x ^ out1;
        out2 = x & ~out2;
        out3 = x | ~out3;
        z = ~(out1 | out2 | out3);
    end
endmodule