data/full_repos/permissive/179844171/simulator/verilator/verilog/top.v
 line:40: before: "32'h8000_0000"
1: b"%Error: data/full_repos/permissive/179844171/simulator/verilator/verilog/top.v:51: Cannot find file containing module: 'mirfak_core'\n    mirfak_core #( \n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179844171/simulator/verilator/verilog,data/full_repos/permissive/179844171/mirfak_core\n             data/full_repos/permissive/179844171/simulator/verilator/verilog,data/full_repos/permissive/179844171/mirfak_core.v\n             data/full_repos/permissive/179844171/simulator/verilator/verilog,data/full_repos/permissive/179844171/mirfak_core.sv\n             mirfak_core\n             mirfak_core.v\n             mirfak_core.sv\n             obj_dir/mirfak_core\n             obj_dir/mirfak_core.v\n             obj_dir/mirfak_core.sv\n%Error: data/full_repos/permissive/179844171/simulator/verilator/verilog/top.v:89: Cannot find file containing module: 'ram'\n    ram #( \n    ^~~\n%Error: Exiting due to 2 error(s)\n"
module top #(
             parameter [31:0] HART_ID         = 0,
             parameter [31:0] RESET_ADDR      = 32'h8000_0000,
             parameter [0:0]  ENABLE_COUNTERS = 1,
             parameter [0:0]  ENABLE_M_ISA    = 1,
             parameter [31:0] MEM_SIZE        = 32'h0100_0000
             )(
               input wire clk_i,
               input wire rst_i,
               input wire xint_meip_i,
               input wire xint_mtip_i,
               input wire xint_msip_i
               );

    localparam ADDR_WIDTH = $clog2(MEM_SIZE);
    localparam BASE_ADDR  = RESET_ADDR;


    wire                dwbm_ack_i;
    wire [31:0]         dwbm_addr_o;
    wire                dwbm_cyc_o;
    wire [31:0]         dwbm_dat_i;
    wire [31:0]         dwbm_dat_o;
    wire [3:0]          dwbm_sel_o;
    wire                dwbm_stb_o;
    wire                dwbm_we_o;
    wire                iwbm_ack_i;
    wire [31:0]         iwbm_addr_o;
    wire                iwbm_cyc_o;
    wire [31:0]         iwbm_dat_i;
    wire                iwbm_stb_o;



    mirfak_core #(

                  .HART_ID              (HART_ID[31:0]),
                  .RESET_ADDR           (RESET_ADDR[31:0]),
                  .ENABLE_COUNTERS      (ENABLE_COUNTERS[0:0]),
                  .ENABLE_M_ISA         (ENABLE_M_ISA[0:0])
                  ) cpu (

                         .iwbm_addr_o           (iwbm_addr_o[31:0]),
                         .iwbm_cyc_o            (iwbm_cyc_o),
                         .iwbm_stb_o            (iwbm_stb_o),
                         .dwbm_addr_o           (dwbm_addr_o[31:0]),
                         .dwbm_dat_o            (dwbm_dat_o[31:0]),
                         .dwbm_sel_o            (dwbm_sel_o[3:0]),
                         .dwbm_cyc_o            (dwbm_cyc_o),
                         .dwbm_stb_o            (dwbm_stb_o),
                         .dwbm_we_o             (dwbm_we_o),

                         .clk_i                 (clk_i),
                         .rst_i                 (rst_i),
                         .iwbm_dat_i            (iwbm_dat_i[31:0]),
                         .iwbm_ack_i            (iwbm_ack_i),
                         .iwbm_err_i            (0),
                         .dwbm_dat_i            (dwbm_dat_i[31:0]),
                         .dwbm_ack_i            (dwbm_ack_i),
                         .dwbm_err_i            (0),
                         .xint_meip_i           (xint_meip_i),
                         .xint_mtip_i           (xint_mtip_i),
                         .xint_msip_i           (xint_msip_i));


    ram #(

          .ADDR_WIDTH (ADDR_WIDTH),
          .BASE_ADDR  (BASE_ADDR)
          ) memory (

                    .iwbs_dat_o        (iwbm_dat_i[31:0]),
                    .iwbs_ack_o        (iwbm_ack_i),
                    .dwbs_dat_o        (dwbm_dat_i[31:0]),
                    .dwbs_ack_o        (dwbm_ack_i),

                    .iwbs_addr_i       (iwbm_addr_o[31:0]),
                    .iwbs_cyc_i        (iwbm_cyc_o),
                    .iwbs_stb_i        (iwbm_stb_o),
                    .dwbs_addr_i       (dwbm_addr_o[31:0]),
                    .dwbs_dat_i        (dwbm_dat_o[31:0]),
                    .dwbs_sel_i        (dwbm_sel_o[3:0]),
                    .dwbs_cyc_i        (dwbm_cyc_o),
                    .dwbs_stb_i        (dwbm_stb_o),
                    .dwbs_we_i         (dwbm_we_o));

endmodule
module top #(
             parameter [31:0] HART_ID         = 0,
             parameter [31:0] RESET_ADDR      = 32'h8000_0000,
             parameter [0:0]  ENABLE_COUNTERS = 1,
             parameter [0:0]  ENABLE_M_ISA    = 1,
             parameter [31:0] MEM_SIZE        = 32'h0100_0000
             )(
               input wire clk_i,
               input wire rst_i,
               input wire xint_meip_i,
               input wire xint_mtip_i,
               input wire xint_msip_i
               );


    localparam ADDR_WIDTH = $clog2(MEM_SIZE);
    localparam BASE_ADDR  = RESET_ADDR;


    wire                dwbm_ack_i;
    wire [31:0]         dwbm_addr_o;
    wire                dwbm_cyc_o;
    wire [31:0]         dwbm_dat_i;
    wire [31:0]         dwbm_dat_o;
    wire [3:0]          dwbm_sel_o;
    wire                dwbm_stb_o;
    wire                dwbm_we_o;
    wire                iwbm_ack_i;
    wire [31:0]         iwbm_addr_o;
    wire                iwbm_cyc_o;
    wire [31:0]         iwbm_dat_i;
    wire                iwbm_stb_o;



    mirfak_core #(

                  .HART_ID              (HART_ID[31:0]),
                  .RESET_ADDR           (RESET_ADDR[31:0]),
                  .ENABLE_COUNTERS      (ENABLE_COUNTERS[0:0]),
                  .ENABLE_M_ISA         (ENABLE_M_ISA[0:0])
                  ) cpu (

                         .iwbm_addr_o           (iwbm_addr_o[31:0]),
                         .iwbm_cyc_o            (iwbm_cyc_o),
                         .iwbm_stb_o            (iwbm_stb_o),
                         .dwbm_addr_o           (dwbm_addr_o[31:0]),
                         .dwbm_dat_o            (dwbm_dat_o[31:0]),
                         .dwbm_sel_o            (dwbm_sel_o[3:0]),
                         .dwbm_cyc_o            (dwbm_cyc_o),
                         .dwbm_stb_o            (dwbm_stb_o),
                         .dwbm_we_o             (dwbm_we_o),

                         .clk_i                 (clk_i),
                         .rst_i                 (rst_i),
                         .iwbm_dat_i            (iwbm_dat_i[31:0]),
                         .iwbm_ack_i            (iwbm_ack_i),
                         .iwbm_err_i            (0),
                         .dwbm_dat_i            (dwbm_dat_i[31:0]),
                         .dwbm_ack_i            (dwbm_ack_i),
                         .dwbm_err_i            (0),
                         .xint_meip_i           (xint_meip_i),
                         .xint_mtip_i           (xint_mtip_i),
                         .xint_msip_i           (xint_msip_i));


    ram #(

          .ADDR_WIDTH (ADDR_WIDTH),
          .BASE_ADDR  (BASE_ADDR)
          ) memory (

                    .iwbs_dat_o        (iwbm_dat_i[31:0]),
                    .iwbs_ack_o        (iwbm_ack_i),
                    .dwbs_dat_o        (dwbm_dat_i[31:0]),
                    .dwbs_ack_o        (dwbm_ack_i),

                    .iwbs_addr_i       (iwbm_addr_o[31:0]),
                    .iwbs_cyc_i        (iwbm_cyc_o),
                    .iwbs_stb_i        (iwbm_stb_o),
                    .dwbs_addr_i       (dwbm_addr_o[31:0]),
                    .dwbs_dat_i        (dwbm_dat_o[31:0]),
                    .dwbs_sel_i        (dwbm_sel_o[3:0]),
                    .dwbs_cyc_i        (dwbm_cyc_o),
                    .dwbs_stb_i        (dwbm_stb_o),
                    .dwbs_we_i         (dwbm_we_o));

endmodule