data/full_repos/permissive/101171422/sim/edge_wait.v
 line:12: before: "("
1: b'%Error: data/full_repos/permissive/101171422/sim/edge_wait.v:13: syntax error, unexpected \'@\'\n   @ (posedge G.clock);\n   ^\n%Error: data/full_repos/permissive/101171422/sim/edge_wait.v:24: Unsupported or unknown PLI call: $monitor\n  $monitor("TIME : %d CLK : %b ENABLE : %b TRIGGER : %b",\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #5  G.enable = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #10 G.enable = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #15 G.enable = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #20 G.enable = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #25 G.enable = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #30 G.enable = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #35 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/edge_wait.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #1 G.clock = ~G.clock;\n  ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module G();
	reg enable, clock;
endmodule
module G();

	reg enable, clock;
endmodule