data/full_repos/permissive/169266176/mos8501.v
1: b"%Error: data/full_repos/permissive/169266176/mos8501.v:71: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n  .do(core_data_out), \n   ^~\n%Error: data/full_repos/permissive/169266176/mos8501.v:71: syntax error, unexpected '(', expecting ')'\n  .do(core_data_out), \n      ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mos8501(
    input clk,
    input reset,
    input enable,
    input irq_n,
    input [7:0] data_in,
	 output wire [7:0] data_out,
	 output [15:0] address,
	 input gate_in,
    output rw,
	 input [7:0] port_in,
	 output [7:0] port_out,
	 input rdy,
	 input aec
    );

wire we,enable_cpu;
wire [15:0] core_address;
wire [7:0] core_data_out;
wire port_access;
reg  [7:0] data_out_reg,core_data_in,port_io;
reg [7:0] port_dir=8'b0;
reg [7:0] port_data=8'b0;
reg rw_reg,aec_reg;



	cpu65xx #(.pipelineOpcode(0),.pipelineAluMux(0),.pipelineAluOut(0)) 
		cpu_core(
		.clk(clk), 
		.reset(reset), 
		.enable(enable_cpu), 
		.nmi_n(1'b1), 
		.irq_n(irq_n), 
		.di(core_data_in), 
		.do(core_data_out), 
		.addr(core_address), 
		.we(we),
		.so_n(1'b1),
		.debugOpcode(),
		.debugPc(),
		.debugA(),
		.debugX(),
		.debugY(),
		.debugS()
	);

assign address=(aec)?core_address:16'hffff;

always @(posedge clk)		
	begin
	if(gate_in)				
		begin							
		if(port_access==1'b1 && we==1'b1)
			if(address[0]==1'b0)
				data_out_reg<=8'h00;
			else
				data_out_reg<=8'h01;
		else
			data_out_reg<=core_data_out;
		end
	else
		begin
		data_out_reg<=data_out_reg;
		end
	end

always @(posedge clk)
	begin
	if(gate_in)
		rw_reg<=~we;		
	end

always @(posedge clk)
	begin
	aec_reg<=aec;
	end

assign rw=(~aec_reg)?1'b1:rw_reg;

assign data_out=(~aec_reg | gate_in | rw)?8'hff:data_out_reg;
assign port_access=(address[15:1]==0)?1'b1:1'b0;


	
always @(posedge clk)
	begin
	if(reset)
		begin
		port_dir<=0;
		port_data<=0;
		end
	else if (enable)
			if(port_access & we)
				if(address[0]==0)
					port_dir<=core_data_out;
				else
					port_data<=core_data_out;
	end
	
always @*
	begin
	core_data_in=data_in;
	if (port_access & ~we)
		if(address[0]==0)
			core_data_in=port_dir;
		else
			core_data_in=port_io;
	end
	



always @*
	begin
		if(port_dir[0]==1'b0)
				port_io[0]=port_in[0];				
			else
				port_io[0]=port_data[0];			
		if(port_dir[1]==1'b0)
				port_io[1]=port_in[1];				
			else
				port_io[1]=port_data[1];
		if(port_dir[2]==1'b0)
				port_io[2]=port_in[2];				
			else
				port_io[2]=port_data[2];
		if(port_dir[3]==1'b0)
				port_io[3]=port_in[3];				
			else
				port_io[3]=port_data[3];
		if(port_dir[4]==1'b0)
				port_io[4]=port_in[4];				
			else
				port_io[4]=port_data[4];
		if(port_dir[5]==1'b0)
				port_io[5]=port_in[5];				
			else
				port_io[5]=port_data[5];
		if(port_dir[6]==1'b0)
				port_io[6]=port_in[6];				
			else
				port_io[6]=port_data[6];
		if(port_dir[7]==1'b0)
				port_io[7]=port_in[7];				
			else
				port_io[7]=port_data[7];
	end
	
assign port_out=port_data;
assign enable_cpu=(~rdy & ~we)?1'b0:enable;
					 
endmodule
module mos8501(
    input clk,
    input reset,
    input enable,
    input irq_n,
    input [7:0] data_in,
	 output wire [7:0] data_out,
	 output [15:0] address,
	 input gate_in,
    output rw,
	 input [7:0] port_in,
	 output [7:0] port_out,
	 input rdy,
	 input aec
    );


wire we,enable_cpu;
wire [15:0] core_address;
wire [7:0] core_data_out;
wire port_access;
reg  [7:0] data_out_reg,core_data_in,port_io;
reg [7:0] port_dir=8'b0;
reg [7:0] port_data=8'b0;
reg rw_reg,aec_reg;



	cpu65xx #(.pipelineOpcode(0),.pipelineAluMux(0),.pipelineAluOut(0)) 
		cpu_core(
		.clk(clk), 
		.reset(reset), 
		.enable(enable_cpu), 
		.nmi_n(1'b1), 
		.irq_n(irq_n), 
		.di(core_data_in), 
		.do(core_data_out), 
		.addr(core_address), 
		.we(we),
		.so_n(1'b1),
		.debugOpcode(),
		.debugPc(),
		.debugA(),
		.debugX(),
		.debugY(),
		.debugS()
	);

assign address=(aec)?core_address:16'hffff;

always @(posedge clk)		
	begin
	if(gate_in)				
		begin							
		if(port_access==1'b1 && we==1'b1)
			if(address[0]==1'b0)
				data_out_reg<=8'h00;
			else
				data_out_reg<=8'h01;
		else
			data_out_reg<=core_data_out;
		end
	else
		begin
		data_out_reg<=data_out_reg;
		end
	end

always @(posedge clk)
	begin
	if(gate_in)
		rw_reg<=~we;		
	end

always @(posedge clk)
	begin
	aec_reg<=aec;
	end

assign rw=(~aec_reg)?1'b1:rw_reg;

assign data_out=(~aec_reg | gate_in | rw)?8'hff:data_out_reg;
assign port_access=(address[15:1]==0)?1'b1:1'b0;


	
always @(posedge clk)
	begin
	if(reset)
		begin
		port_dir<=0;
		port_data<=0;
		end
	else if (enable)
			if(port_access & we)
				if(address[0]==0)
					port_dir<=core_data_out;
				else
					port_data<=core_data_out;
	end
	
always @*
	begin
	core_data_in=data_in;
	if (port_access & ~we)
		if(address[0]==0)
			core_data_in=port_dir;
		else
			core_data_in=port_io;
	end
	



always @*
	begin
		if(port_dir[0]==1'b0)
				port_io[0]=port_in[0];				
			else
				port_io[0]=port_data[0];			
		if(port_dir[1]==1'b0)
				port_io[1]=port_in[1];				
			else
				port_io[1]=port_data[1];
		if(port_dir[2]==1'b0)
				port_io[2]=port_in[2];				
			else
				port_io[2]=port_data[2];
		if(port_dir[3]==1'b0)
				port_io[3]=port_in[3];				
			else
				port_io[3]=port_data[3];
		if(port_dir[4]==1'b0)
				port_io[4]=port_in[4];				
			else
				port_io[4]=port_data[4];
		if(port_dir[5]==1'b0)
				port_io[5]=port_in[5];				
			else
				port_io[5]=port_data[5];
		if(port_dir[6]==1'b0)
				port_io[6]=port_in[6];				
			else
				port_io[6]=port_data[6];
		if(port_dir[7]==1'b0)
				port_io[7]=port_in[7];				
			else
				port_io[7]=port_data[7];
	end
	
assign port_out=port_data;
assign enable_cpu=(~rdy & ~we)?1'b0:enable;
					 
endmodule