data/full_repos/permissive/209644662/verilator/example/counter.v
data/verilator_xmls/cce75b52-226e-4351-add7-7d172de104d6.xml
module counter #(
  parameter WIDTH = 8
)(

  input  wire             clk,
  input  wire             rst,

  input  wire             cen,
  input  wire             wen,
  input  wire [WIDTH-1:0] dat,
  output reg  [WIDTH-1:0] o_p,
  output reg  [WIDTH-1:0] o_n
);


always @ (posedge clk, posedge rst)
if (rst) o_p <= {WIDTH{1'b0}};
else     o_p <= wen ? dat : o_p + {{WIDTH-1{1'b0}}, cen};


always @ (negedge clk, posedge rst)
if (rst) o_n <= {WIDTH{1'b0}};
else     o_n <= wen ? dat : o_n + {{WIDTH-1{1'b0}}, cen};


endmodule
module counter #(
  parameter WIDTH = 8
)(

  input  wire             clk,
  input  wire             rst,

  input  wire             cen,
  input  wire             wen,
  input  wire [WIDTH-1:0] dat,
  output reg  [WIDTH-1:0] o_p,
  output reg  [WIDTH-1:0] o_n
);



always @ (posedge clk, posedge rst)
if (rst) o_p <= {WIDTH{1'b0}};
else     o_p <= wen ? dat : o_p + {{WIDTH-1{1'b0}}, cen};


always @ (negedge clk, posedge rst)
if (rst) o_n <= {WIDTH{1'b0}};
else     o_n <= wen ? dat : o_n + {{WIDTH-1{1'b0}}, cen};


endmodule