data/full_repos/permissive/216192770/ALU.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:14: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'ar\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar + br; \n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:14: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'br\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar + br; \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:15: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                             : ... In instance ALU\n                dataAcc <= result[15:0]; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:19: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ar\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar - br; \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:19: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'br\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar - br; \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:20: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                             : ... In instance ALU\n                dataAcc <= result[15:0]; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:29: Operator DIV expects 32 bits on the LHS, but LHS\'s VARREF \'ar\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar / br; \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:29: Operator DIV expects 32 bits on the RHS, but RHS\'s VARREF \'br\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar / br; \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:34: Operator AND expects 32 bits on the LHS, but LHS\'s VARREF \'ar\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar & br; \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:34: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'br\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar & br; \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:35: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                             : ... In instance ALU\n                dataAcc <= result[15:0]; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:39: Operator OR expects 32 bits on the LHS, but LHS\'s VARREF \'ar\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar | br; \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:39: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'br\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar | br; \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:40: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                             : ... In instance ALU\n                dataAcc <= result[15:0]; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:44: Operator NOT expects 32 bits on the LHS, but LHS\'s VARREF \'ar\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ~ar; \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:45: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                             : ... In instance ALU\n                dataAcc <= result[15:0]; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:49: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'ar\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar << br; \n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:50: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                             : ... In instance ALU\n                dataAcc <= result[15:0]; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:54: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'ar\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar >> br; \n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:55: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                             : ... In instance ALU\n                dataAcc <= result[15:0]; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:59: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'ar\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar + 1\'b1;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:60: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                             : ... In instance ALU\n                dataAcc <= result[15:0];\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:64: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'ar\' generates 16 bits.\n                                                             : ... In instance ALU\n                result <= ar - 1\'b1;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/216192770/ALU.v:65: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                             : ... In instance ALU\n                dataAcc <= result[15:0];\n                        ^~\n%Error: Exiting due to 24 warning(s)\n'
module ALU(funcSelect, ar, br, dataAcc, carry);
    
    input[3:0] funcSelect;
    input[15:0] ar;
    input[15:0] br;
    output reg[31:0] dataAcc;
    output reg carry;

    reg[31:0] result;
    
    always@(*) begin
        case (funcSelect)
            4'b0001: begin 
                result <= ar + br; 
                dataAcc <= result[15:0]; 
                carry <= result[16]; 
            end
            4'b0010: begin 
                result <= ar - br; 
                dataAcc <= result[15:0]; 
                carry <= result[16]; 
            end
            4'b0011: begin 
                result <= ar * br; 
                dataAcc <= result; 
                carry <= 0; 
            end
            4'b0100: begin 
                result <= ar / br; 
                dataAcc <= result; 
                carry <= 0; 
            end
            4'b0101: begin 
                result <= ar & br; 
                dataAcc <= result[15:0]; 
                carry <= 0; 
            end
            4'b0110: begin 
                result <= ar | br; 
                dataAcc <= result[15:0]; 
                carry <= 0; 
            end
            4'b0111: begin 
                result <= ~ar; 
                dataAcc <= result[15:0]; 
                carry <= 0; 
            end
            4'b1000: begin 
                result <= ar << br; 
                dataAcc <= result[15:0]; 
                carry <= 0; 
            end
            4'b1001: begin 
                result <= ar >> br; 
                dataAcc <= result[15:0]; 
                carry <= 0; 
            end 
            4'b1010:begin
                result <= ar + 1'b1;
                dataAcc <= result[15:0];
                carry <= result[16];
            end
            4'b1011:begin
                result <= ar - 1'b1;
                dataAcc <= result[15:0];
                carry <= result[16];
            end

            default: begin result <= 0; carry <= 0; end
        endcase
    end


endmodule
module ALU(funcSelect, ar, br, dataAcc, carry);

    
    input[3:0] funcSelect;
    input[15:0] ar;
    input[15:0] br;
    output reg[31:0] dataAcc;
    output reg carry;

    reg[31:0] result;
    
    always@(*) begin
        case (funcSelect)
            4'b0001: begin 
                result <= ar + br; 
                dataAcc <= result[15:0]; 
                carry <= result[16]; 
            end
            4'b0010: begin 
                result <= ar - br; 
                dataAcc <= result[15:0]; 
                carry <= result[16]; 
            end
            4'b0011: begin 
                result <= ar * br; 
                dataAcc <= result; 
                carry <= 0; 
            end
            4'b0100: begin 
                result <= ar / br; 
                dataAcc <= result; 
                carry <= 0; 
            end
            4'b0101: begin 
                result <= ar & br; 
                dataAcc <= result[15:0]; 
                carry <= 0; 
            end
            4'b0110: begin 
                result <= ar | br; 
                dataAcc <= result[15:0]; 
                carry <= 0; 
            end
            4'b0111: begin 
                result <= ~ar; 
                dataAcc <= result[15:0]; 
                carry <= 0; 
            end
            4'b1000: begin 
                result <= ar << br; 
                dataAcc <= result[15:0]; 
                carry <= 0; 
            end
            4'b1001: begin 
                result <= ar >> br; 
                dataAcc <= result[15:0]; 
                carry <= 0; 
            end 
            4'b1010:begin
                result <= ar + 1'b1;
                dataAcc <= result[15:0];
                carry <= result[16];
            end
            4'b1011:begin
                result <= ar - 1'b1;
                dataAcc <= result[15:0];
                carry <= result[16];
            end

            default: begin result <= 0; carry <= 0; end
        endcase
    end


endmodule