data/full_repos/permissive/197806087/matrix_multiplication/rtl/thread.v
data/verilator_xmls/76a8fc61-5d4a-4538-80a5-5100dd6beab2.xml
module thread #(
    parameter DATA_WIDTH = 8
) (
    input wire clk,
    input wire rst,
    input wire [DATA_WIDTH-1:0] a,
    input wire [DATA_WIDTH-1:0] b,
    output reg [DATA_WIDTH-1:0] res
);

always @(posedge clk or negedge rst) begin
    if (~rst) begin
        res <= 0;
    end
    else begin

        res <= res + (a * b);
        $display("Adding a * b (%d) to res (%d)", a * b, res);
    end
end

endmodule
module thread #(
    parameter DATA_WIDTH = 8
) (
    input wire clk,
    input wire rst,
    input wire [DATA_WIDTH-1:0] a,
    input wire [DATA_WIDTH-1:0] b,
    output reg [DATA_WIDTH-1:0] res
);


always @(posedge clk or negedge rst) begin
    if (~rst) begin
        res <= 0;
    end
    else begin

        res <= res + (a * b);
        $display("Adding a * b (%d) to res (%d)", a * b, res);
    end
end

endmodule