data/full_repos/permissive/143278/ivltests/dffsynth2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth2.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #2 clk = 0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth2.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #2 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth2.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #2 if (Q !== 0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth2.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #2 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth2.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #2 if (Q !== 1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth2.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #2 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth2.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #2 if (Q !== 1) begin\n      ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg clk;

   reg Q, D;
   (* ivl_synthesys_on *)
   always @(negedge clk)
     Q <= D;

   (* ivl_synthesys_off *)
   initial begin
      clk = 1;
      D = 0;
      #2 clk = 0;
      #2 clk = 1;
      #2 if (Q !== 0) begin
	 $display("FAILED -- initial setup D=%b, Q=%b", D, Q);
	 $finish;
      end

      D = 1;
      #2 clk = 0;

      #2 if (Q !== 1) begin
	 $display("FAILED -- negedge clk failed D=%b, Q=%b", D, Q);
	 $finish;
      end

      D = 0;
      #2 clk = 1;
      #2 if (Q !== 1) begin
	 $display("FAILED -- posedge clk tripped FF. D=%b, Q=%b", D, Q);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   reg clk;

   reg Q, D;
   (* ivl_synthesys_on *)
   always @(negedge clk)
     Q <= D;

   (* ivl_synthesys_off *)
   initial begin
      clk = 1;
      D = 0;
      #2 clk = 0;
      #2 clk = 1;
      #2 if (Q !== 0) begin
	 $display("FAILED -- initial setup D=%b, Q=%b", D, Q);
	 $finish;
      end

      D = 1;
      #2 clk = 0;

      #2 if (Q !== 1) begin
	 $display("FAILED -- negedge clk failed D=%b, Q=%b", D, Q);
	 $finish;
      end

      D = 0;
      #2 clk = 1;
      #2 if (Q !== 1) begin
	 $display("FAILED -- posedge clk tripped FF. D=%b, Q=%b", D, Q);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule