data/full_repos/permissive/106029354/verilog_source/pipeline4.v
1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline4.v:15: Cannot find include file: params_proc.v\n`include "params_proc.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n             params_proc.v\n             params_proc.v.v\n             params_proc.v.sv\n             obj_dir/params_proc.v\n             obj_dir/params_proc.v.v\n             obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n'
module pipeline4(
    clk_in,
    RST,
    ctrl_in,
    we,
    data,
    addr,
    reg_addr_in,
    reg_data_out,
    reg_addr_out,
    ctrl_out
);


`include "params_proc.v"

input clk_in, RST;
input [CTRL_WIDTH-1:0] ctrl_in;
input we;
input signed [DATA_WIDTH-1:0] data;
input [MEM_WIDTH-1:0] addr;
input [REG_ADDR_WIDTH-1:0] reg_addr_in;

output wire signed [DATA_WIDTH-1:0] reg_data_out;
output reg [REG_ADDR_WIDTH-1:0] reg_addr_out;
output reg [CTRL_WIDTH-1:0] ctrl_out;


mem_data rom0(.clk(clk_in), .we(we), .addr(addr), .data_in(data), .data_out(reg_data_out));


always @(posedge clk_in) begin
  reg_addr_out <= reg_addr_in;
end


always @(posedge clk_in) begin
    if (!RST) begin

      ctrl_out    <= NOP;
    end else begin
      ctrl_out    <= ctrl_in;
    end
end

endmodule
module pipeline4(
    clk_in,
    RST,
    ctrl_in,
    we,
    data,
    addr,
    reg_addr_in,
    reg_data_out,
    reg_addr_out,
    ctrl_out
);



`include "params_proc.v"

input clk_in, RST;
input [CTRL_WIDTH-1:0] ctrl_in;
input we;
input signed [DATA_WIDTH-1:0] data;
input [MEM_WIDTH-1:0] addr;
input [REG_ADDR_WIDTH-1:0] reg_addr_in;

output wire signed [DATA_WIDTH-1:0] reg_data_out;
output reg [REG_ADDR_WIDTH-1:0] reg_addr_out;
output reg [CTRL_WIDTH-1:0] ctrl_out;


mem_data rom0(.clk(clk_in), .we(we), .addr(addr), .data_in(data), .data_out(reg_data_out));


always @(posedge clk_in) begin
  reg_addr_out <= reg_addr_in;
end


always @(posedge clk_in) begin
    if (!RST) begin

      ctrl_out    <= NOP;
    end else begin
      ctrl_out    <= ctrl_in;
    end
end

endmodule