data/full_repos/permissive/143278/ivltests/always_ff_warn.v
 line:5: before: ";"
1: b'%Error: data/full_repos/permissive/143278/ivltests/always_ff_warn.v:5: Unsupported: event data types\n  event foo;\n  ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/always_ff_warn.v:15: Unsupported: event data types\n    event tevt;\n    ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/always_ff_warn.v:21: Unsupported: event data types\n    event int1, int2;\n    ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/always_ff_warn.v:24: syntax error, unexpected ->\n    -> foo;\n    ^~\n%Error: data/full_repos/permissive/143278/ivltests/always_ff_warn.v:27: Unsupported: Dynamic array new\n    ar = new [2];\n         ^~~\n%Error: data/full_repos/permissive/143278/ivltests/always_ff_warn.v:31: syntax error, unexpected \'{\', expecting \')\'\n    for (int idx = 0; idx; {done, idx} = done + 1) $display("Should never run!");\n                           ^\n%Error: data/full_repos/permissive/143278/ivltests/always_ff_warn.v:39: Unsupported: Verilog 1995 deassign\n    deassign a;\n    ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/always_ff_warn.v:42: Unsupported: Verilog 1995 force\n    force a = 1\'b1;\n    ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/always_ff_warn.v:43: Unsupported: Verilog 1995 release\n    release a;\n    ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always_ff_warn.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = 1\'b1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always_ff_warn.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #0 $display("Expect compile warnings!\\nPASSED");\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always_ff_warn.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #2 $display("FAILED");\n    ^\n%Error: Exiting due to 9 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg a;
  reg q, d;
  reg clk;
  event foo;
  real rl;
  int ar [];
  int start = 0;
  int stop = 1;
  int step = 1;
  int done = 0;

  task a_task;
    real trl;
    event tevt;
    reg tvr;
    $display("user task");
  endtask

  always_ff @(posedge clk)  begin: blk_name
    event int1, int2;
    real intrl;
    q = d;
    -> foo;
    rl = 0.0;
    rl <= 1.0;
    ar = new [2];
    for (int idx = start; idx < stop; idx += step) $display("For: %0d", idx);
    for (int idx = 0; done; idx = done + 1) $display("Should never run!");
    for (int idx = 0; idx; done = done + 1) $display("Should never run!");
    for (int idx = 0; idx; {done, idx} = done + 1) $display("Should never run!");
    for (int idx = 0; idx; idx <<= 1) $display("Should never run!");
    for (int idx = 0; idx; idx = idx << 1) $display("Should never run!");
    $display("array size: %0d", ar.size());
    ar.delete();
    $display("array size: %0d", ar.size());
    a_task;
    assign a = 1'b0;
    deassign a;
    do $display("do/while");
    while (a);
    force a = 1'b1;
    release a;
    while(a) begin
      $display("while");
      a = 1'b0;
    end
    repeat(2) $display("repeat");
    disable out_name;
    forever begin
      $display("forever");
      disable blk_name;
    end
  end

  initial begin
    #1 clk = 1'b1;
    #0 $display("Expect compile warnings!\nPASSED");
  end

  initial begin: out_name
    #2 $display("FAILED");
  end

endmodule
module top;

  reg a;
  reg q, d;
  reg clk;
  event foo;
  real rl;
  int ar [];
  int start = 0;
  int stop = 1;
  int step = 1;
  int done = 0;

  task a_task;
    real trl;
    event tevt;
    reg tvr;
    $display("user task");
  endtask

  always_ff @(posedge clk)  begin: blk_name
    event int1, int2;
    real intrl;
    q = d;
    -> foo;
    rl = 0.0;
    rl <= 1.0;
    ar = new [2];
    for (int idx = start; idx < stop; idx += step) $display("For: %0d", idx);
    for (int idx = 0; done; idx = done + 1) $display("Should never run!");
    for (int idx = 0; idx; done = done + 1) $display("Should never run!");
    for (int idx = 0; idx; {done, idx} = done + 1) $display("Should never run!");
    for (int idx = 0; idx; idx <<= 1) $display("Should never run!");
    for (int idx = 0; idx; idx = idx << 1) $display("Should never run!");
    $display("array size: %0d", ar.size());
    ar.delete();
    $display("array size: %0d", ar.size());
    a_task;
    assign a = 1'b0;
    deassign a;
    do $display("do/while");
    while (a);
    force a = 1'b1;
    release a;
    while(a) begin
      $display("while");
      a = 1'b0;
    end
    repeat(2) $display("repeat");
    disable out_name;
    forever begin
      $display("forever");
      disable blk_name;
    end
  end

  initial begin
    #1 clk = 1'b1;
    #0 $display("Expect compile warnings!\nPASSED");
  end

  initial begin: out_name
    #2 $display("FAILED");
  end

endmodule