data/full_repos/permissive/143278/blif/blif01e.v
data/verilator_xmls/f3f3b4f1-5816-4b9f-9ae7-3cb5cac3fd9f.xml
module cmpN
  #(parameter WID = 4)
   (input wire [WID-1:0] A,
    input wire [WID-1:0] B,
    output wire QE, QN, QGT, QGE
);

   assign QE = A == B;
   assign QN = A != B;
   assign QGT = A > B;
   assign QGE = A >= B;

endmodule
module cmpN
  #(parameter WID = 4)
   (input wire [WID-1:0] A,
    input wire [WID-1:0] B,
    output wire QE, QN, QGT, QGE
);


   assign QE = A == B;
   assign QN = A != B;
   assign QGT = A > B;
   assign QGE = A >= B;

endmodule