data/full_repos/permissive/169522605/hw3_1/nand3.v
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data/verilator_xmls/63015f2a-f2d4-428c-95ef-7de80c2ac52c.xml
module nand3 (in1,in2,in3,out);
    input in1,in2,in3;
    output out;
    assign out = ~(in1 & in2 & in3);
endmodule
module nand3 (in1,in2,in3,out);

    input in1,in2,in3;
    output out;
    assign out = ~(in1 & in2 & in3);
endmodule