data/full_repos/permissive/138254793/test_bench.v
 line:57: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #5 reset = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #1 reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #1 reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:39: Unsupported: Ignoring delay on this delayed statement.\n    forever #1 clk = ~clk;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:57: Unsupported: Ignoring delay on this delayed statement.\n #301 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:61: Unsupported: Ignoring delay on this delayed statement.\n #2 pkt_in = data[1];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:62: Unsupported: Ignoring delay on this delayed statement.\n #2 pkt_in = data[2];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:63: Unsupported: Ignoring delay on this delayed statement.\n #2 pkt_in = data[4];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:64: Unsupported: Ignoring delay on this delayed statement.\n #2 pkt_in = data[5];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:65: Unsupported: Ignoring delay on this delayed statement.\n #2 pkt_in_valid = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:92: Unsupported: Ignoring delay on this delayed statement.\n #21 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:97: Unsupported: Ignoring delay on this delayed statement.\n #2 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:100: Unsupported: Ignoring delay on this delayed statement.\n #20 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:105: Unsupported: Ignoring delay on this delayed statement.\n #2 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:108: Unsupported: Ignoring delay on this delayed statement.\n #20 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:113: Unsupported: Ignoring delay on this delayed statement.\n #2 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:116: Unsupported: Ignoring delay on this delayed statement.\n #20 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:121: Unsupported: Ignoring delay on this delayed statement.\n #2 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:124: Unsupported: Ignoring delay on this delayed statement.\n #20 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:130: Unsupported: Ignoring delay on this delayed statement.\n #2 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:133: Unsupported: Ignoring delay on this delayed statement.\n #20 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:139: Unsupported: Ignoring delay on this delayed statement.\n #2 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:153: Unsupported: Ignoring delay on this delayed statement.\n #20 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:159: Unsupported: Ignoring delay on this delayed statement.\n #2 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:162: Unsupported: Ignoring delay on this delayed statement.\n #20 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/138254793/test_bench.v:167: Unsupported: Ignoring delay on this delayed statement.\n #2 begin\n ^\n%Error: data/full_repos/permissive/138254793/test_bench.v:19: Cannot find file containing module: \'unimon_top\'\nunimon_top unimon(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138254793,data/full_repos/permissive/138254793/unimon_top\n             data/full_repos/permissive/138254793,data/full_repos/permissive/138254793/unimon_top.v\n             data/full_repos/permissive/138254793,data/full_repos/permissive/138254793/unimon_top.sv\n             unimon_top\n             unimon_top.v\n             unimon_top.sv\n             obj_dir/unimon_top\n             obj_dir/unimon_top.v\n             obj_dir/unimon_top.sv\n%Warning-WIDTH: data/full_repos/permissive/138254793/test_bench.v:46: Operator ASSIGNDLY expects 134 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance test\n pkt_in <= 1\'b0;\n        ^~\n%Error: Exiting due to 1 error(s), 27 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test(
);


reg 		clk;
reg 		reset;
reg		pkt_in_valid;
reg		[133:0]	pkt_in;
wire	pkt_out_valid;
wire	[133:0] pkt_out;
reg		ctrl_in_valid;
reg		[1:0]	ctrl_opt;
reg		[31:0]	ctrl_addr;
reg		[31:0]	ctrl_data_in;
wire	ctrl_out_valid;
wire	[31:0]	ctrl_data_out;

unimon_top unimon(
.clk(clk),
.reset(reset),
.pkt_in_valid(pkt_in_valid),
.pkt_in(pkt_in),
.pkt_out_valid(pkt_out_valid),
.pkt_out(pkt_out),
.ctrl_in_valid(ctrl_in_valid),
.ctrl_opt(ctrl_opt),
.ctrl_addr(ctrl_addr),
.ctrl_data_in(ctrl_data_in),
.ctrl_out_valid(ctrl_out_valid),
.ctrl_data_out(ctrl_data_out)
);

initial begin
    clk = 0;
    #5 reset = 1;
    #1 reset = 0;
    #1 reset = 1;
    forever #1 clk = ~clk;
end

reg	[133:0]	data[5:0];

initial begin
    pkt_in_valid <= 1'b0;
	pkt_in <= 1'b0;


	data[0] = {2'b01,4'd0,32'd2,32'd1,16'd4,16'd3,6'h12,26'b0};

	data[1] = {2'b11,4'd0,128'd1};
	data[2] = {2'b11,4'd0,128'd2};
	data[3] = {2'b11,4'd0,128'd3};
	data[4] = {2'b11,4'd0,128'd4};
	data[5] = {2'b10,4'd0,128'd5};

	#301 begin
		pkt_in_valid = 1'b1;
		pkt_in = data[0];
	end
	#2 pkt_in = data[1];
	#2 pkt_in = data[2];
	#2 pkt_in = data[4];
	#2 pkt_in = data[5];
	#2 pkt_in_valid = 1'b0;
	
end


reg	[31:0]	entry[4:0];



initial begin
	ctrl_addr = 32'b0;
	ctrl_opt = 2'd1;
	ctrl_addr = 32'b0;
	ctrl_data_in = 32'b0;
	ctrl_in_valid = 1'b0; 
	
	{entry[4],entry[3],entry[2],entry[1],entry[0]} = {24'b0,
		32'd2,32'd1,16'd4,16'd3,
		3'b0,1'b1,2'd1,2'd0,
		8'hff,
		4'b1,4'b0,
		16'h4};


	
	

	#21 begin
		ctrl_addr = {8'd0,4'd0,16'd3,4'd0};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = entry[0];
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end
	#20 begin
		ctrl_addr = {8'd0,4'd0,16'd3,4'd1};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = entry[1];
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end
	#20 begin
		ctrl_addr = {8'd0,4'd0,16'd3,4'd2};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = entry[2];
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end
	#20 begin
		ctrl_addr = {8'd0,4'd0,16'd3,4'd3};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = entry[3];
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end
	#20 begin
		ctrl_addr = {8'd0,4'd0,16'd3,4'd4};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = entry[4];
	end

	#2 begin
		ctrl_in_valid = 1'b0;
	end
	#20 begin
		ctrl_opt = 2'd0;
		ctrl_addr = {8'd0,4'd0,16'd3,4'd0};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = entry[4];
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end


	#20 begin
		ctrl_opt = 2'd1;
		ctrl_addr = {8'd0,4'd1,16'd6,4'd0};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = {16'h3,16'd2};
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end
	#20 begin
		ctrl_addr = {8'd0,4'd2,16'd2,4'd0};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = {16'h4,16'd3};
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end

end


endmodule
module test(
);



reg 		clk;
reg 		reset;
reg		pkt_in_valid;
reg		[133:0]	pkt_in;
wire	pkt_out_valid;
wire	[133:0] pkt_out;
reg		ctrl_in_valid;
reg		[1:0]	ctrl_opt;
reg		[31:0]	ctrl_addr;
reg		[31:0]	ctrl_data_in;
wire	ctrl_out_valid;
wire	[31:0]	ctrl_data_out;

unimon_top unimon(
.clk(clk),
.reset(reset),
.pkt_in_valid(pkt_in_valid),
.pkt_in(pkt_in),
.pkt_out_valid(pkt_out_valid),
.pkt_out(pkt_out),
.ctrl_in_valid(ctrl_in_valid),
.ctrl_opt(ctrl_opt),
.ctrl_addr(ctrl_addr),
.ctrl_data_in(ctrl_data_in),
.ctrl_out_valid(ctrl_out_valid),
.ctrl_data_out(ctrl_data_out)
);

initial begin
    clk = 0;
    #5 reset = 1;
    #1 reset = 0;
    #1 reset = 1;
    forever #1 clk = ~clk;
end

reg	[133:0]	data[5:0];

initial begin
    pkt_in_valid <= 1'b0;
	pkt_in <= 1'b0;


	data[0] = {2'b01,4'd0,32'd2,32'd1,16'd4,16'd3,6'h12,26'b0};

	data[1] = {2'b11,4'd0,128'd1};
	data[2] = {2'b11,4'd0,128'd2};
	data[3] = {2'b11,4'd0,128'd3};
	data[4] = {2'b11,4'd0,128'd4};
	data[5] = {2'b10,4'd0,128'd5};

	#301 begin
		pkt_in_valid = 1'b1;
		pkt_in = data[0];
	end
	#2 pkt_in = data[1];
	#2 pkt_in = data[2];
	#2 pkt_in = data[4];
	#2 pkt_in = data[5];
	#2 pkt_in_valid = 1'b0;
	
end


reg	[31:0]	entry[4:0];



initial begin
	ctrl_addr = 32'b0;
	ctrl_opt = 2'd1;
	ctrl_addr = 32'b0;
	ctrl_data_in = 32'b0;
	ctrl_in_valid = 1'b0; 
	
	{entry[4],entry[3],entry[2],entry[1],entry[0]} = {24'b0,
		32'd2,32'd1,16'd4,16'd3,
		3'b0,1'b1,2'd1,2'd0,
		8'hff,
		4'b1,4'b0,
		16'h4};


	
	

	#21 begin
		ctrl_addr = {8'd0,4'd0,16'd3,4'd0};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = entry[0];
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end
	#20 begin
		ctrl_addr = {8'd0,4'd0,16'd3,4'd1};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = entry[1];
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end
	#20 begin
		ctrl_addr = {8'd0,4'd0,16'd3,4'd2};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = entry[2];
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end
	#20 begin
		ctrl_addr = {8'd0,4'd0,16'd3,4'd3};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = entry[3];
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end
	#20 begin
		ctrl_addr = {8'd0,4'd0,16'd3,4'd4};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = entry[4];
	end

	#2 begin
		ctrl_in_valid = 1'b0;
	end
	#20 begin
		ctrl_opt = 2'd0;
		ctrl_addr = {8'd0,4'd0,16'd3,4'd0};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = entry[4];
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end


	#20 begin
		ctrl_opt = 2'd1;
		ctrl_addr = {8'd0,4'd1,16'd6,4'd0};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = {16'h3,16'd2};
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end
	#20 begin
		ctrl_addr = {8'd0,4'd2,16'd2,4'd0};
		ctrl_in_valid = 1'b1;
		ctrl_data_in = {16'h4,16'd3};
	end
	#2 begin
		ctrl_in_valid = 1'b0;
	end

end


endmodule