data/full_repos/permissive/205055389/test/verga/supply2.v
1: b'%Error: data/full_repos/permissive/205055389/test/verga/supply2.v:11: Unsupported or unknown PLI call: $monitor\n $monitor("%d: z=%b a=%b",$time,z,a);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/supply2.v:12: Unsupported: Ignoring delay on this delayed statement.\n #2 a = 1\'b1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  supply0 gnd;
  wire vdd = !gnd;
  reg a;
  wire z;

  AND2 g1(z, a, vdd);

  initial
    begin
	$monitor("%d: z=%b a=%b",$time,z,a);
	#2 a = 1'b1;
    end

endmodule
module top;

  supply0 gnd;
  wire vdd = !gnd;
  reg a;
  wire z;

  AND2 g1(z, a, vdd);

  initial
    begin
	$monitor("%d: z=%b a=%b",$time,z,a);
	#2 a = 1'b1;
    end

endmodule