data/full_repos/permissive/177289247/ALU.v
1: b'%Error: data/full_repos/permissive/177289247/ALU.v:1: Cannot find include file: signal_def.v\n`include "signal_def.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/177289247,data/full_repos/permissive/177289247/signal_def.v\n             data/full_repos/permissive/177289247,data/full_repos/permissive/177289247/signal_def.v.v\n             data/full_repos/permissive/177289247,data/full_repos/permissive/177289247/signal_def.v.sv\n             signal_def.v\n             signal_def.v.v\n             signal_def.v.sv\n             obj_dir/signal_def.v\n             obj_dir/signal_def.v.v\n             obj_dir/signal_def.v.sv\n%Error: data/full_repos/permissive/177289247/ALU.v:22: Define or directive not defined: \'`ALUOp_ADD\'\n        `ALUOp_ADD:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:22: syntax error, unexpected \':\', expecting endcase\n        `ALUOp_ADD:\n                  ^\n%Error: data/full_repos/permissive/177289247/ALU.v:24: Define or directive not defined: \'`ALUOp_SUB\'\n        `ALUOp_SUB, `ALUOp_BNE:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:24: Define or directive not defined: \'`ALUOp_BNE\'\n        `ALUOp_SUB, `ALUOp_BNE:\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:26: Define or directive not defined: \'`ALUOp_MUL\'\n        `ALUOp_MUL:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:28: Define or directive not defined: \'`ALUOp_DIV\'\n        `ALUOp_DIV:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:30: Define or directive not defined: \'`ALUOp_SLL\'\n        `ALUOp_SLL:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:32: Define or directive not defined: \'`ALUOp_SRL\'\n        `ALUOp_SRL:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:34: Define or directive not defined: \'`ALUOp_SLR\'\n        `ALUOp_SLR:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:35: syntax error, unexpected \';\'\n        for (i = 0; i < 31; i=i+1) begin\n                          ^\n%Error: data/full_repos/permissive/177289247/ALU.v:35: syntax error, unexpected \')\', expecting \';\'\n        for (i = 0; i < 31; i=i+1) begin\n                                 ^\n%Error: data/full_repos/permissive/177289247/ALU.v:38: Define or directive not defined: \'`ALUOp_SRR\'\n        `ALUOp_SRR:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:39: syntax error, unexpected for, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n        for (i = 0; i < 31; i=i+1) begin\n        ^~~\n%Error: data/full_repos/permissive/177289247/ALU.v:39: syntax error, unexpected \';\'\n        for (i = 0; i < 31; i=i+1) begin\n                          ^\n%Error: data/full_repos/permissive/177289247/ALU.v:39: syntax error, unexpected \')\', expecting \';\'\n        for (i = 0; i < 31; i=i+1) begin\n                                 ^\n%Error: data/full_repos/permissive/177289247/ALU.v:42: Define or directive not defined: \'`ALUOp_AND\'\n        `ALUOp_AND:\n        ^~~~~~~~~~\n%Warning-ENDLABEL: data/full_repos/permissive/177289247/ALU.v:43: End label \'ALURes\' does not match begin label \'\'\n        ALURes = DataIn1 & DataIn2;\n        ^~~~~~\n                   ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/177289247/ALU.v:43: syntax error, unexpected \'=\'\n        ALURes = DataIn1 & DataIn2;\n               ^\n%Error: data/full_repos/permissive/177289247/ALU.v:44: Define or directive not defined: \'`ALUOp_OR\'\n        `ALUOp_OR:\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:46: Define or directive not defined: \'`ALUOp_XOR\'\n        `ALUOp_XOR:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:48: Define or directive not defined: \'`ALUOp_NOR\'\n        `ALUOp_NOR:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:50: Define or directive not defined: \'`ALUOp_NAND\'\n        `ALUOp_NAND:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:52: Define or directive not defined: \'`ALUOp_XNOR\'\n        `ALUOp_XNOR:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:54: Define or directive not defined: \'`ALUOp_SLT\'\n        `ALUOp_SLT: begin\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:67: Define or directive not defined: \'`ALUOp_LUI\'\n        `ALUOp_LUI: begin\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/177289247/ALU.v:74: Define or directive not defined: \'`ALUOp_BNE\'\n        `ALUOp_BNE:\n        ^~~~~~~~~~\n%Error: Cannot continue\n'
module ALU (
    output  reg[31:0]   ALURes,
    output  reg         Zero,
    input   [31:0]      DataIn1,
    input   [31:0]      DataIn2,
    input   [4:0]       shamt,
    input   [4:0]       ALUOp
);

integer i;

initial begin
    Zero   = 0;
    ALURes = 0;
end

always@(DataIn1 or DataIn2 or ALUOp or shamt) begin

    case(ALUOp)
        `ALUOp_ADD:
        ALURes = DataIn1 + DataIn2;
        `ALUOp_SUB, `ALUOp_BNE:
        ALURes = DataIn1 - DataIn2;
        `ALUOp_MUL:
        ALURes = DataIn1 * DataIn2;
        `ALUOp_DIV:
        ALURes = DataIn1 / DataIn2;
        `ALUOp_SLL:
        ALURes = DataIn2 << shamt;
        `ALUOp_SRL:
        ALURes = DataIn2 >> shamt;
        `ALUOp_SLR:
        for (i = 0; i < 31; i=i+1) begin
            ALURes[i] = DataIn1[(i+DataIn2)%32];
        end
        `ALUOp_SRR:
        for (i = 0; i < 31; i=i+1) begin
            ALURes[i] = DataIn1[(i-DataIn2+32)%32];
        end
        `ALUOp_AND:
        ALURes = DataIn1 & DataIn2;
        `ALUOp_OR:
        ALURes = DataIn1 | DataIn2;
        `ALUOp_XOR:
        ALURes = DataIn1 ^ DataIn2;
        `ALUOp_NOR:
        ALURes = ~(DataIn1 | DataIn2);
        `ALUOp_NAND:
        ALURes = ~(DataIn1 & DataIn2);
        `ALUOp_XNOR:
        ALURes = ~(DataIn1 ^ DataIn2);
        `ALUOp_SLT: begin
            if (DataIn1[31] != DataIn2[31]) begin
                if (DataIn1[31] > DataIn2[31])
                    ALURes = 1;
                else
                    ALURes = 0;
            end else begin
                if (DataIn1 < DataIn2)
                    ALURes = 1;
                else
                    ALURes = 0;
            end
        end
        `ALUOp_LUI: begin
            ALURes[15:0]  = 0;
            ALURes[31:16] = DataIn2[15:0];
        end
    endcase

    case (ALUOp)
        `ALUOp_BNE:
            Zero = (ALURes)?1:0;
        default:
            Zero = (ALURes)?0:1;
    endcase

end

endmodule
module ALU (
    output  reg[31:0]   ALURes,
    output  reg         Zero,
    input   [31:0]      DataIn1,
    input   [31:0]      DataIn2,
    input   [4:0]       shamt,
    input   [4:0]       ALUOp
);


integer i;

initial begin
    Zero   = 0;
    ALURes = 0;
end

always@(DataIn1 or DataIn2 or ALUOp or shamt) begin

    case(ALUOp)
        `ALUOp_ADD:
        ALURes = DataIn1 + DataIn2;
        `ALUOp_SUB, `ALUOp_BNE:
        ALURes = DataIn1 - DataIn2;
        `ALUOp_MUL:
        ALURes = DataIn1 * DataIn2;
        `ALUOp_DIV:
        ALURes = DataIn1 / DataIn2;
        `ALUOp_SLL:
        ALURes = DataIn2 << shamt;
        `ALUOp_SRL:
        ALURes = DataIn2 >> shamt;
        `ALUOp_SLR:
        for (i = 0; i < 31; i=i+1) begin
            ALURes[i] = DataIn1[(i+DataIn2)%32];
        end
        `ALUOp_SRR:
        for (i = 0; i < 31; i=i+1) begin
            ALURes[i] = DataIn1[(i-DataIn2+32)%32];
        end
        `ALUOp_AND:
        ALURes = DataIn1 & DataIn2;
        `ALUOp_OR:
        ALURes = DataIn1 | DataIn2;
        `ALUOp_XOR:
        ALURes = DataIn1 ^ DataIn2;
        `ALUOp_NOR:
        ALURes = ~(DataIn1 | DataIn2);
        `ALUOp_NAND:
        ALURes = ~(DataIn1 & DataIn2);
        `ALUOp_XNOR:
        ALURes = ~(DataIn1 ^ DataIn2);
        `ALUOp_SLT: begin
            if (DataIn1[31] != DataIn2[31]) begin
                if (DataIn1[31] > DataIn2[31])
                    ALURes = 1;
                else
                    ALURes = 0;
            end else begin
                if (DataIn1 < DataIn2)
                    ALURes = 1;
                else
                    ALURes = 0;
            end
        end
        `ALUOp_LUI: begin
            ALURes[15:0]  = 0;
            ALURes[31:16] = DataIn2[15:0];
        end
    endcase

    case (ALUOp)
        `ALUOp_BNE:
            Zero = (ALURes)?1:0;
        default:
            Zero = (ALURes)?0:1;
    endcase

end

endmodule