data/full_repos/permissive/150329835/src/Logic.v
data/verilator_xmls/3acdeef9-c225-4a37-87dc-bdd5b6b007ea.xml
module MY_NOT(A,F);
	input [7:0] A;
	output [9:0] F;
	
	assign F[0] = ~A[0];
	assign F[1] = ~A[1];
	assign F[2] = ~A[2];
	assign F[3] = ~A[3];
	assign F[4] = ~A[4];
	assign F[5] = ~A[5];
	assign F[6] = ~A[6];
	assign F[7] = ~A[7];
	assign F[8] = 0;
	assign F[9] = 0;
endmodule
module MY_NOT(A,F);

	input [7:0] A;
	output [9:0] F;
	
	assign F[0] = ~A[0];
	assign F[1] = ~A[1];
	assign F[2] = ~A[2];
	assign F[3] = ~A[3];
	assign F[4] = ~A[4];
	assign F[5] = ~A[5];
	assign F[6] = ~A[6];
	assign F[7] = ~A[7];
	assign F[8] = 0;
	assign F[9] = 0;
endmodule