data/full_repos/permissive/201488448/2_circuits/1_combinational/01_wire.v
data/verilator_xmls/1fed84af-047e-4a92-8620-7772559e1806.xml
module top_module (
    input in,
    output out);

    assign	out = in;
    
endmodule
module top_module (
    input in,
    output out);


    assign	out = in;
    
endmodule