data/full_repos/permissive/19384863/sixbitadd_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/19384863/sixbitadd_tb.v:2: Cannot find include file: sixbitadd.v\n`include "sixbitadd.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19384863,data/full_repos/permissive/19384863/sixbitadd.v\n             data/full_repos/permissive/19384863,data/full_repos/permissive/19384863/sixbitadd.v.v\n             data/full_repos/permissive/19384863,data/full_repos/permissive/19384863/sixbitadd.v.sv\n             sixbitadd.v\n             sixbitadd.v.v\n             sixbitadd.v.sv\n             obj_dir/sixbitadd.v\n             obj_dir/sixbitadd.v.v\n             obj_dir/sixbitadd.v.sv\n%Error: data/full_repos/permissive/19384863/sixbitadd_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("sixbitadd_wave.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/19384863/sixbitadd_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, testbench);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19384863/sixbitadd_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #250;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module testbench;
	reg[5:0] ain;
	reg[5:0] bin;
	wire[5:0] sum;
	wire cout;

	integer i, j;

	sixbitadd ad1 (ain, bin, sum, cout);

	initial begin

		$dumpfile("sixbitadd_wave.vcd");
		$dumpvars(0, testbench);
	
		for(i = 0; i < 64; i = i + 1)
		begin
			ain = i;
			for(j = 0; j < 64; j = j + 1)
			begin
				bin = j;
				#250;
			end
		end
	end
endmodule
module testbench;

	reg[5:0] ain;
	reg[5:0] bin;
	wire[5:0] sum;
	wire cout;

	integer i, j;

	sixbitadd ad1 (ain, bin, sum, cout);

	initial begin

		$dumpfile("sixbitadd_wave.vcd");
		$dumpvars(0, testbench);
	
		for(i = 0; i < 64; i = i + 1)
		begin
			ain = i;
			for(j = 0; j < 64; j = j + 1)
			begin
				bin = j;
				#250;
			end
		end
	end
endmodule