data/full_repos/permissive/220281533/read_registers.v
1: b'%Error: data/full_repos/permissive/220281533/read_registers.v:64: Unsupported or unknown PLI call: $writememb\n   $writememb("registers.mem",registers);\n   ^~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module read_registers(
	output reg [31:0] read_data_1, read_data_2,
	input [31:0] write_data,
	input [4:0] read_reg_1, read_reg_2, write_reg, 
	input [5:0] opcode,
	input signal_regRead, signal_regWrite, signal_regDst, clk
);

	reg [31:0] registers [31:0];
	
	initial begin
		$readmemb("registers.mem", registers);
	end
	
	always @(write_data) begin

		if(signal_regWrite) begin

			if(signal_regDst) begin
				if(opcode == 6'h24)begin
					registers[write_reg][7:0] = write_data[7:0];
				end
				if(opcode == 6'h25)begin
					registers[write_reg][15:0] = write_data[15:0];
				end
				else begin
					registers[write_reg] = write_data;
				end
			end
			else begin
				if(opcode == 6'h24)begin
					registers[read_reg_2][7:0] = write_data[7:0];
				end
				if(opcode == 6'h25)begin
					registers[read_reg_2][15:0] = write_data[15:0];
				end
				else begin
					registers[read_reg_2] = write_data;
				end
			end

			$writememb("registers.mem",registers);
		end
	end
	
	always @(read_reg_1, read_reg_2) begin

		if(signal_regRead) begin
			read_data_1 = registers[read_reg_1];
			read_data_2 = registers[read_reg_2];
		end
	end
	
	
	
	




endmodule
module read_registers(
	output reg [31:0] read_data_1, read_data_2,
	input [31:0] write_data,
	input [4:0] read_reg_1, read_reg_2, write_reg, 
	input [5:0] opcode,
	input signal_regRead, signal_regWrite, signal_regDst, clk
);


	reg [31:0] registers [31:0];
	
	initial begin
		$readmemb("registers.mem", registers);
	end
	
	always @(write_data) begin

		if(signal_regWrite) begin

			if(signal_regDst) begin
				if(opcode == 6'h24)begin
					registers[write_reg][7:0] = write_data[7:0];
				end
				if(opcode == 6'h25)begin
					registers[write_reg][15:0] = write_data[15:0];
				end
				else begin
					registers[write_reg] = write_data;
				end
			end
			else begin
				if(opcode == 6'h24)begin
					registers[read_reg_2][7:0] = write_data[7:0];
				end
				if(opcode == 6'h25)begin
					registers[read_reg_2][15:0] = write_data[15:0];
				end
				else begin
					registers[read_reg_2] = write_data;
				end
			end

			$writememb("registers.mem",registers);
		end
	end
	
	always @(read_reg_1, read_reg_2) begin

		if(signal_regRead) begin
			read_data_1 = registers[read_reg_1];
			read_data_2 = registers[read_reg_2];
		end
	end
	
	
	
	




endmodule