data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ASSIGN1.v
data/verilator_xmls/5f228a04-38cf-4924-989a-1bd3cb82310c.xml
module ASSIGN1(IN, OUT);
   output OUT;
   input IN;
   assign OUT = IN;
endmodule
module ASSIGN1(IN, OUT);

   output OUT;
   input IN;
   assign OUT = IN;
endmodule