data/full_repos/permissive/123075301/BCD_to_HEX.v
1: b'%Warning-WIDTH: data/full_repos/permissive/123075301/BCD_to_HEX.v:28: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                    : ... In instance BCD_to_HEX\nreg[3:0] count = 3\'b0;\n                 ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module BCD_to_HEX(reset,ip,op);

input reset;
input [11:0] ip;
output [11:0] op;

reg [23:0] temp = 24'b0;
reg[3:0] count = 3'b0;
assign op = temp[11:0];

always @ (ip)
begin
if(reset == 1'b1)
	begin
		count = 4'b0;
		temp = 24'b0;
	end
else
	begin
		if(count == 4'b0)
			temp[23:0] = {ip[11:0],12'b0};

		for(count = 4'b0; count<4'd11; count= count+1'b1)
		begin
			temp = temp >> 1;
			if(temp[23:20] >= 4'b1000 )
				temp[23:20] = temp[23:20] - 4'b0011;
			if(temp[19:16] >= 4'b1000 )
				temp[19:16] = temp[19:16] - 4'b0011;
			if(temp[15:12] >= 4'b1000 )
				temp[15:12] = temp[15:12] - 4'b0011;
		end
		
		if(count == 4'b1011)
			begin
				temp = temp>>1;
				count = 4'b0;
			end
		else ;
	end
end
endmodule
module BCD_to_HEX(reset,ip,op);


input reset;
input [11:0] ip;
output [11:0] op;

reg [23:0] temp = 24'b0;
reg[3:0] count = 3'b0;
assign op = temp[11:0];

always @ (ip)
begin
if(reset == 1'b1)
	begin
		count = 4'b0;
		temp = 24'b0;
	end
else
	begin
		if(count == 4'b0)
			temp[23:0] = {ip[11:0],12'b0};

		for(count = 4'b0; count<4'd11; count= count+1'b1)
		begin
			temp = temp >> 1;
			if(temp[23:20] >= 4'b1000 )
				temp[23:20] = temp[23:20] - 4'b0011;
			if(temp[19:16] >= 4'b1000 )
				temp[19:16] = temp[19:16] - 4'b0011;
			if(temp[15:12] >= 4'b1000 )
				temp[15:12] = temp[15:12] - 4'b0011;
		end
		
		if(count == 4'b1011)
			begin
				temp = temp>>1;
				count = 4'b0;
			end
		else ;
	end
end
endmodule