data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v
 line:44: before: "="
1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n             lib/spi.v\n             lib/spi.v.v\n             lib/spi.v.sv\n             obj_dir/lib/spi.v\n             obj_dir/lib/spi.v.v\n             obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n   #300;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n'
module RAM_inferred #(
	parameter addr_width = 9,
	parameter data_width = 8
) (
	input reset,
	input [addr_width-1:0] waddr, raddr,
	input [data_width-1:0] din,
	input write_en, wclk, rclk,
	output reg [data_width-1:0] dout = 0
);
	reg [data_width-1:0] mem [(1<<addr_width)-1:0];
	always @(posedge wclk) begin
		if (reset) begin

		end else begin
			if (write_en) begin
				mem[waddr] <= din;
			end
		end
	end
	always @(posedge rclk) begin
		if (~reset) begin
			dout <= mem[raddr];
		end
	end
endmodule
module RAM_inferred #(
	parameter addr_width = 9,
	parameter data_width = 8
) (
	input reset,
	input [addr_width-1:0] waddr, raddr,
	input [data_width-1:0] din,
	input write_en, wclk, rclk,
	output reg [data_width-1:0] dout = 0
);

	reg [data_width-1:0] mem [(1<<addr_width)-1:0];
	always @(posedge wclk) begin
		if (reset) begin

		end else begin
			if (write_en) begin
				mem[waddr] <= din;
			end
		end
	end
	always @(posedge rclk) begin
		if (~reset) begin
			dout <= mem[raddr];
		end
	end
endmodule