data/full_repos/permissive/133241844/fulladder_zerogate.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/133241844/fulladder_zerogate.v:28: Unsupported or unknown PLI call: $monitor\n  $monitor($time, "a = %b, b = %b, c = %b, s = %b, cout = %b", a, b, c, s, cout);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/133241844/fulladder_zerogate.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #0 a = 0; b = 0; c = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133241844/fulladder_zerogate.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #5 a = 1; b = 0; c = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133241844/fulladder_zerogate.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #5 a = 0; b = 1; c = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133241844/fulladder_zerogate.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #5 a = 0; b = 0; c = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133241844/fulladder_zerogate.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #5 a = 1; b = 1; c = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133241844/fulladder_zerogate.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #5 a = 0; b = 1; c = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133241844/fulladder_zerogate.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #5 a = 1; b = 0; c = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133241844/fulladder_zerogate.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #5 a = 1; b = 1; c = 1;\n  ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module project2();
	wire s;	
	wire cout;	
	wire w, x, y, z;
	reg a, b, c;

	xor (w, a, b);
	xor (s, w, c);


	and (x, a, c);
	and (y, b, c);
	and (z, a, b);


	or (cout, x, y, z);

	initial begin
		$monitor($time, "a = %b, b = %b, c = %b, s = %b, cout = %b", a, b, c, s, cout);
		#0 a = 0; b = 0; c = 0;
		#5 a = 1; b = 0; c = 0;
		#5 a = 0; b = 1; c = 0;
		#5 a = 0; b = 0; c = 1;
		#5 a = 1; b = 1; c = 0;
		#5 a = 0; b = 1; c = 1;
		#5 a = 1; b = 0; c = 1;
		#5 a = 1; b = 1; c = 1;
		$display($time, "a = %b, b = %b, c = %b, s = %b, cout = %b", a, b, c, s, cout);
	end
endmodule
module project2();

	wire s;	
	wire cout;	
	wire w, x, y, z;
	reg a, b, c;

	xor (w, a, b);
	xor (s, w, c);


	and (x, a, c);
	and (y, b, c);
	and (z, a, b);


	or (cout, x, y, z);

	initial begin
		$monitor($time, "a = %b, b = %b, c = %b, s = %b, cout = %b", a, b, c, s, cout);
		#0 a = 0; b = 0; c = 0;
		#5 a = 1; b = 0; c = 0;
		#5 a = 0; b = 1; c = 0;
		#5 a = 0; b = 0; c = 1;
		#5 a = 1; b = 1; c = 0;
		#5 a = 0; b = 1; c = 1;
		#5 a = 1; b = 0; c = 1;
		#5 a = 1; b = 1; c = 1;
		$display($time, "a = %b, b = %b, c = %b, s = %b, cout = %b", a, b, c, s, cout);
	end
endmodule