data/full_repos/permissive/146479393/TB/TB_SPI_Temp_Master2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/146479393/TB/TB_SPI_Temp_Master2.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/146479393/TB/TB_SPI_Temp_Master2.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #10; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/146479393/TB/TB_SPI_Temp_Master2.v:69: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk_i = ~clk_i;\n         ^\n%Error: data/full_repos/permissive/146479393/TB/TB_SPI_Temp_Master2.v:37: Cannot find file containing module: \'SPI_Temp_Master2\'\n SPI_Temp_Master2 uut (\n ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146479393/TB,data/full_repos/permissive/146479393/SPI_Temp_Master2\n             data/full_repos/permissive/146479393/TB,data/full_repos/permissive/146479393/SPI_Temp_Master2.v\n             data/full_repos/permissive/146479393/TB,data/full_repos/permissive/146479393/SPI_Temp_Master2.sv\n             SPI_Temp_Master2\n             SPI_Temp_Master2.v\n             SPI_Temp_Master2.sv\n             obj_dir/SPI_Temp_Master2\n             obj_dir/SPI_Temp_Master2.v\n             obj_dir/SPI_Temp_Master2.sv\n%Warning-WIDTH: data/full_repos/permissive/146479393/TB/TB_SPI_Temp_Master2.v:52: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'40\'h9442212007\' generates 40 bits.\n                                                                                : ... In instance TB_SPI_Temp_Master2\n  data = 40\'b1001010001000010001000010010000000000111;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/146479393/TB/TB_SPI_Temp_Master2.v:65: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                : ... In instance TB_SPI_Temp_Master2\n  SPI_Data_In = data >> i;\n              ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_SPI_Temp_Master2;


	reg clk_i;
	reg SPI_Data_In;


	wire SPI_clk;
	wire SPI_cs;
	wire [31:0] SPI_Data_Out;


	SPI_Temp_Master2 uut (
		.clk_i(clk_i), 
		.SPI_clk(SPI_clk), 
		.SPI_cs(SPI_cs), 
		.SPI_Data_In(SPI_Data_In), 
		.SPI_Data_Out(SPI_Data_Out)
	);

reg [31:0] data;
integer i;

	initial begin

		clk_i = 0;
		SPI_Data_In = 0;
		data = 40'b1001010001000010001000010010000000000111;
		i=-1;



		#100;
        


	end
      
			always@(posedge clk_i)begin
		#10; 
		SPI_Data_In = data >> i;
		i = i + 1;
	end
      
		always #5 clk_i = ~clk_i;
		
		
		
		
		
		
		

		

		
endmodule
module TB_SPI_Temp_Master2;



	reg clk_i;
	reg SPI_Data_In;


	wire SPI_clk;
	wire SPI_cs;
	wire [31:0] SPI_Data_Out;


	SPI_Temp_Master2 uut (
		.clk_i(clk_i), 
		.SPI_clk(SPI_clk), 
		.SPI_cs(SPI_cs), 
		.SPI_Data_In(SPI_Data_In), 
		.SPI_Data_Out(SPI_Data_Out)
	);

reg [31:0] data;
integer i;

	initial begin

		clk_i = 0;
		SPI_Data_In = 0;
		data = 40'b1001010001000010001000010010000000000111;
		i=-1;



		#100;
        


	end
      
			always@(posedge clk_i)begin
		#10; 
		SPI_Data_In = data >> i;
		i = i + 1;
	end
      
		always #5 clk_i = ~clk_i;
		
		
		
		
		
		
		

		

		
endmodule