data/full_repos/permissive/174263347/scanconv/hdl/syncinv.v
data/verilator_xmls/7acd0ade-7488-4556-a5e4-6e1cff52f47c.xml
module syncinv(clk, ena, reset, ih, iv, oh, ov, htick);

    input   clk;
    input   ena;
    input   reset;
    input   ih, iv;
    output  oh, ov;
	output	htick;

    reg     [3:0] hscnt;
    reg     [2:0] vscnt;
    reg     hspol, vspol;





reg		[1:0] hfee;
reg		rhtick;

always @ (posedge clk)
begin
	hfee  <= { hfee[0], oh };
	rhtick <= (~hfee[0] & hfee[1]);
end

assign htick = rhtick;





always @ ( posedge clk or posedge reset) 
begin
	if (reset)
	begin
		hscnt <= 4'b1000;
		hspol <= 1;
	end
	else if (ena)
		if (ih)
			if ( hscnt == 4'b1111 )
				hspol <= 1;
			else
				hscnt <= hscnt + 1;
		else
    		if ( hscnt == 4'b0000 )
				hspol <= 0;
    		else
    			hscnt <= hscnt - 1;
end

assign oh = (hspol ^ ih);





always @ ( posedge clk or posedge reset) 
begin
	if (reset)
	begin
		vscnt <= 3'b100;
		vspol <= 1;
	end
	else if(htick)
		if (iv)
			if ( vscnt == 3'b111 )
				vspol <= 1;
			else
				vscnt <= vscnt + 1;
		else
			if ( vscnt == 3'b000 )
				vspol <= 0;
			else
				vscnt <= vscnt - 1;
end

assign ov = (vspol ^ iv);				

endmodule
module syncinv(clk, ena, reset, ih, iv, oh, ov, htick);


    input   clk;
    input   ena;
    input   reset;
    input   ih, iv;
    output  oh, ov;
	output	htick;

    reg     [3:0] hscnt;
    reg     [2:0] vscnt;
    reg     hspol, vspol;





reg		[1:0] hfee;
reg		rhtick;

always @ (posedge clk)
begin
	hfee  <= { hfee[0], oh };
	rhtick <= (~hfee[0] & hfee[1]);
end

assign htick = rhtick;





always @ ( posedge clk or posedge reset) 
begin
	if (reset)
	begin
		hscnt <= 4'b1000;
		hspol <= 1;
	end
	else if (ena)
		if (ih)
			if ( hscnt == 4'b1111 )
				hspol <= 1;
			else
				hscnt <= hscnt + 1;
		else
    		if ( hscnt == 4'b0000 )
				hspol <= 0;
    		else
    			hscnt <= hscnt - 1;
end

assign oh = (hspol ^ ih);





always @ ( posedge clk or posedge reset) 
begin
	if (reset)
	begin
		vscnt <= 3'b100;
		vspol <= 1;
	end
	else if(htick)
		if (iv)
			if ( vscnt == 3'b111 )
				vspol <= 1;
			else
				vscnt <= vscnt + 1;
		else
			if ( vscnt == 3'b000 )
				vspol <= 0;
			else
				vscnt <= vscnt - 1;
end

assign ov = (vspol ^ iv);				

endmodule