data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v
1: b'%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:56: Operator FUNCREF \'grayInc\' expects 3 bits on the Function Argument, but Function Argument\'s VARREF \'wrPtrA\' generates 2 bits.\n                                                                                         : ... In instance crossclock\n      wrPtrA <= grayInc(wrPtrA);\n                ^~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:56: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'grayInc\' generates 3 bits.\n                                                                                         : ... In instance crossclock\n      wrPtrA <= grayInc(wrPtrA);\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:62: Operator FUNCREF \'grayInc\' expects 3 bits on the Function Argument, but Function Argument\'s VARREF \'rdPtrB\' generates 2 bits.\n                                                                                         : ... In instance crossclock\n      rdPtrB <= grayInc(rdPtrB);\n                ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:62: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'grayInc\' generates 3 bits.\n                                                                                         : ... In instance crossclock\n      rdPtrB <= grayInc(rdPtrB);\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:66: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'rdPtrAQQ\' generates 1 bits.\n                                                                                         : ... In instance crossclock\n      GRAY0: full = (rdPtrAQQ == GRAY1);\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:67: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'rdPtrAQQ\' generates 1 bits.\n                                                                                         : ... In instance crossclock\n      GRAY1: full = (rdPtrAQQ == GRAY2);\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:68: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'rdPtrAQQ\' generates 1 bits.\n                                                                                         : ... In instance crossclock\n      GRAY2: full = (rdPtrAQQ == GRAY3);\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:69: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'rdPtrAQQ\' generates 1 bits.\n                                                                                         : ... In instance crossclock\n      GRAY3: full = (rdPtrAQQ == GRAY4);\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:70: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'rdPtrAQQ\' generates 1 bits.\n                                                                                         : ... In instance crossclock\n      GRAY4: full = (rdPtrAQQ == GRAY5);\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:71: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'rdPtrAQQ\' generates 1 bits.\n                                                                                         : ... In instance crossclock\n      GRAY5: full = (rdPtrAQQ == GRAY6);\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:72: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'rdPtrAQQ\' generates 1 bits.\n                                                                                         : ... In instance crossclock\n      GRAY6: full = (rdPtrAQQ == GRAY7);\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:73: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'rdPtrAQQ\' generates 1 bits.\n                                                                                         : ... In instance crossclock\n      GRAY7: full = (rdPtrAQQ == GRAY0);\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:65: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'wrPtrA\' generates 2 bits.\n                                                                                         : ... In instance crossclock\n    case (wrPtrA)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:80: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'rdPtrB\' generates 2 bits.\n                                                                                         : ... In instance crossclock\n    rdPtrAQ <= rdPtrB;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:85: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'wrPtrA\' generates 2 bits.\n                                                                                         : ... In instance crossclock\n    wrPtrBQ <= wrPtrA;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:113: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                          : ... In instance crossclock\n      wrPtrBQ <= {ad_length{1\'b0}};\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:114: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                          : ... In instance crossclock\n      wrPtrBQQ <= {ad_length{1\'b0}};\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:118: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                          : ... In instance crossclock\n      rdPtrAQ <= {ad_length{1\'b0}};\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:119: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                          : ... In instance crossclock\n      rdPtrAQQ <= {ad_length{1\'b0}};\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/20270692/labs/lab11/crossclock/crossclock.v:124: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'wrPtrBQQ\' generates 1 bits.\n                                                                                          : ... In instance crossclock\n  assign empty = wrPtrBQQ == wrPtrA;\n                          ^~\n%Error: Exiting due to 20 warning(s)\n'
function [2:0] grayInc;
    input [2:0] greyInput;
    begin
      case (greyInput)
        GRAY0 : grayInc=GRAY1;
        GRAY1 : grayInc=GRAY2;
        GRAY2 : grayInc=GRAY3;
        GRAY3 : grayInc=GRAY4;
        GRAY4 : grayInc=GRAY5;
        GRAY5 : grayInc=GRAY6;
        GRAY6 : grayInc=GRAY7;
        GRAY7 : grayInc=GRAY0;
      endcase
    end
  endfunction
function [2:0] grayInc;

    input [2:0] greyInput;
    begin
      case (greyInput)
        GRAY0 : grayInc=GRAY1;
        GRAY1 : grayInc=GRAY2;
        GRAY2 : grayInc=GRAY3;
        GRAY3 : grayInc=GRAY4;
        GRAY4 : grayInc=GRAY5;
        GRAY5 : grayInc=GRAY6;
        GRAY6 : grayInc=GRAY7;
        GRAY7 : grayInc=GRAY0;
      endcase
    end
  endfunction