data/full_repos/permissive/151207731/rv32i/rtl/merlin_fifo.v
None: at end of input
1: b'%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_fifo.v:9: Cannot find include file: riscv_defs.v\n`include "riscv_defs.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v.v\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v.sv\n             riscv_defs.v\n             riscv_defs.v.v\n             riscv_defs.v.sv\n             obj_dir/riscv_defs.v\n             obj_dir/riscv_defs.v.v\n             obj_dir/riscv_defs.v.sv\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_fifo.v:79: Define or directive not defined: \'`RV_SYNC_LOGIC_CLOCK_RESET\'\n    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin\n             ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_fifo.v:102: Define or directive not defined: \'`RV_SYNC_LOGIC_CLOCK\'\n    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin\n             ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module merlin_fifo
    #(
        parameter C_FIFO_PASSTHROUGH = 0,
        parameter C_FIFO_WIDTH       = 1,
        parameter C_FIFO_DEPTH_X     = 1,

        parameter C_FIFO_DEPTH       = 2**C_FIFO_DEPTH_X
    )
    (

        input  wire                     clk_i,
        input  wire                     reset_i,

        input  wire                     flush_i,
        output wire                     empty_o,
        output reg                      full_o,

        input  wire                     wr_i,
        input  wire  [C_FIFO_WIDTH-1:0] din_i,

        input  wire                     rd_i,
        output wire  [C_FIFO_WIDTH-1:0] dout_o
    );





    reg                    empty_int;

    reg [C_FIFO_DEPTH_X:0] rd_ptr_q;
    reg [C_FIFO_DEPTH_X:0] wr_ptr_q;

    reg [C_FIFO_WIDTH-1:0] mem[C_FIFO_DEPTH-1:0];






    generate if (C_FIFO_PASSTHROUGH) begin
        assign empty_o = (empty_int == 1'b1 ? ~wr_i : empty_int);
        assign dout_o  = (empty_int == 1'b1 ? din_i : mem[rd_ptr_q[C_FIFO_DEPTH_X-1:0]]);
    end else begin
        assign empty_o = empty_int;
        assign dout_o  = mem[rd_ptr_q[C_FIFO_DEPTH_X-1:0]];
    end endgenerate





    always @ (*) begin
        empty_int = 1'b0;
        full_o    = 1'b0;
        if (rd_ptr_q[C_FIFO_DEPTH_X-1:0] == wr_ptr_q[C_FIFO_DEPTH_X-1:0]) begin
            if (rd_ptr_q[C_FIFO_DEPTH_X] == wr_ptr_q[C_FIFO_DEPTH_X]) begin
                empty_int = 1'b1;
            end else begin
                full_o = 1'b1;
            end
        end
    end





    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
        if (reset_i) begin
            rd_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
            wr_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
        end else begin
            if (flush_i) begin
                rd_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
                wr_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
            end else begin
                if (rd_i) begin
                    rd_ptr_q <= rd_ptr_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
                end
                if (wr_i) begin
                    wr_ptr_q <= wr_ptr_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
                end
            end
        end
    end





    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
        if (wr_i) begin
            mem[wr_ptr_q[C_FIFO_DEPTH_X-1:0]] <= din_i;
        end
    end





`ifdef RV_ASSERTS_ON
    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
        `RV_ASSERT(((full_o & wr_i) == 1'b0), "FIFO written when full!")
        `RV_ASSERT(((empty_o & rd_i) == 1'b0), "FIFO read when empty!")
    end
`endif
endmodule
module merlin_fifo
    #(
        parameter C_FIFO_PASSTHROUGH = 0,
        parameter C_FIFO_WIDTH       = 1,
        parameter C_FIFO_DEPTH_X     = 1,

        parameter C_FIFO_DEPTH       = 2**C_FIFO_DEPTH_X
    )
    (

        input  wire                     clk_i,
        input  wire                     reset_i,

        input  wire                     flush_i,
        output wire                     empty_o,
        output reg                      full_o,

        input  wire                     wr_i,
        input  wire  [C_FIFO_WIDTH-1:0] din_i,

        input  wire                     rd_i,
        output wire  [C_FIFO_WIDTH-1:0] dout_o
    );






    reg                    empty_int;

    reg [C_FIFO_DEPTH_X:0] rd_ptr_q;
    reg [C_FIFO_DEPTH_X:0] wr_ptr_q;

    reg [C_FIFO_WIDTH-1:0] mem[C_FIFO_DEPTH-1:0];






    generate if (C_FIFO_PASSTHROUGH) begin
        assign empty_o = (empty_int == 1'b1 ? ~wr_i : empty_int);
        assign dout_o  = (empty_int == 1'b1 ? din_i : mem[rd_ptr_q[C_FIFO_DEPTH_X-1:0]]);
    end else begin
        assign empty_o = empty_int;
        assign dout_o  = mem[rd_ptr_q[C_FIFO_DEPTH_X-1:0]];
    end endgenerate





    always @ (*) begin
        empty_int = 1'b0;
        full_o    = 1'b0;
        if (rd_ptr_q[C_FIFO_DEPTH_X-1:0] == wr_ptr_q[C_FIFO_DEPTH_X-1:0]) begin
            if (rd_ptr_q[C_FIFO_DEPTH_X] == wr_ptr_q[C_FIFO_DEPTH_X]) begin
                empty_int = 1'b1;
            end else begin
                full_o = 1'b1;
            end
        end
    end





    always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
        if (reset_i) begin
            rd_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
            wr_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
        end else begin
            if (flush_i) begin
                rd_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
                wr_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
            end else begin
                if (rd_i) begin
                    rd_ptr_q <= rd_ptr_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
                end
                if (wr_i) begin
                    wr_ptr_q <= wr_ptr_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
                end
            end
        end
    end





    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
        if (wr_i) begin
            mem[wr_ptr_q[C_FIFO_DEPTH_X-1:0]] <= din_i;
        end
    end





`ifdef RV_ASSERTS_ON
    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
        `RV_ASSERT(((full_o & wr_i) == 1'b0), "FIFO written when full!")
        `RV_ASSERT(((empty_o & rd_i) == 1'b0), "FIFO read when empty!")
    end
`endif
endmodule