data/full_repos/permissive/197356760/GCD/gcd_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/197356760/GCD/gcd_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #13 rst_tb = 1; #6 start_tb = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/197356760/GCD/gcd_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #13 rst_tb = 1; #6 start_tb = 1;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/GCD/gcd_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #25 start_tb = 0; #200 start_tb = 1; #30 start_tb = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/GCD/gcd_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #25 start_tb = 0; #200 start_tb = 1; #30 start_tb = 0;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/GCD/gcd_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #25 start_tb = 0; #200 start_tb = 1; #30 start_tb = 0;\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/GCD/gcd_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n always #35 a_tb = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/GCD/gcd_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n always #35 b_tb = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/GCD/gcd_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk_tb = ~clk_tb;\n        ^\n%Error: data/full_repos/permissive/197356760/GCD/gcd_tb.v:17: Cannot find file containing module: \'gcd\'\n gcd DUT (a_tb, b_tb, clk_tb, start_tb, rst_tb, ready_tb, result_tb);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/197356760/GCD,data/full_repos/permissive/197356760/gcd\n             data/full_repos/permissive/197356760/GCD,data/full_repos/permissive/197356760/gcd.v\n             data/full_repos/permissive/197356760/GCD,data/full_repos/permissive/197356760/gcd.sv\n             gcd\n             gcd.v\n             gcd.sv\n             obj_dir/gcd\n             obj_dir/gcd.v\n             obj_dir/gcd.sv\n%Warning-WIDTH: data/full_repos/permissive/197356760/GCD/gcd_tb.v:25: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                    : ... In instance gcd_tb\n always #35 a_tb = $random;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/197356760/GCD/gcd_tb.v:26: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                    : ... In instance gcd_tb\n always #35 b_tb = $random;\n                 ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gcd_tb ();
	parameter width = 8;				 
	reg [width-1:0] a_tb, b_tb;
	reg clk_tb, start_tb, rst_tb;
	wire ready_tb;
	wire [width-1:0] result_tb;
	
	gcd DUT (a_tb, b_tb, clk_tb, start_tb, rst_tb, ready_tb, result_tb);
	
	initial begin
		clk_tb = 0; rst_tb = 0; start_tb = 0;
		#13 rst_tb = 1; #6 start_tb = 1;
		#25 start_tb = 0; #200 start_tb = 1; #30 start_tb = 0;
	end

	always #35 a_tb = $random;
	always #35 b_tb = $random;

	always #5 clk_tb = ~clk_tb;
	 
	
endmodule
module gcd_tb ();

	parameter width = 8;				 
	reg [width-1:0] a_tb, b_tb;
	reg clk_tb, start_tb, rst_tb;
	wire ready_tb;
	wire [width-1:0] result_tb;
	
	gcd DUT (a_tb, b_tb, clk_tb, start_tb, rst_tb, ready_tb, result_tb);
	
	initial begin
		clk_tb = 0; rst_tb = 0; start_tb = 0;
		#13 rst_tb = 1; #6 start_tb = 1;
		#25 start_tb = 0; #200 start_tb = 1; #30 start_tb = 0;
	end

	always #35 a_tb = $random;
	always #35 b_tb = $random;

	always #5 clk_tb = ~clk_tb;
	 
	
endmodule