data/full_repos/permissive/174323821/hdl/video/jtframe_linebuf.v
1: b"%Error: data/full_repos/permissive/174323821/hdl/video/jtframe_linebuf.v:54: Cannot find file containing module: 'jtframe_dual_ram'\njtframe_dual_ram #(.aw(AW+1),.dw(DW)) u_line(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174323821/hdl/video,data/full_repos/permissive/174323821/jtframe_dual_ram\n             data/full_repos/permissive/174323821/hdl/video,data/full_repos/permissive/174323821/jtframe_dual_ram.v\n             data/full_repos/permissive/174323821/hdl/video,data/full_repos/permissive/174323821/jtframe_dual_ram.sv\n             jtframe_dual_ram\n             jtframe_dual_ram.v\n             jtframe_dual_ram.sv\n             obj_dir/jtframe_dual_ram\n             obj_dir/jtframe_dual_ram.v\n             obj_dir/jtframe_dual_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module jtframe_linebuf #(parameter
    DW=8,
    AW=9
)(
    input            clk,
    input            LHBL,


    input   [AW-1:0] wr_addr,
    input   [DW-1:0] wr_data,
    input            we,

    input   [AW-1:0] rd_addr,
    output  [DW-1:0] rd_data,
    output  [DW-1:0] rd_gated
);

reg     line, last_LHBL;

wire [DW-1:0]       dump_data;

`ifdef SIMULATION
initial begin
    line = 0;
end
`endif

always @(posedge clk) begin
    last_LHBL <= LHBL;
    if( !LHBL && last_LHBL )
        line <= ~line;
end

assign rd_gated = LHBL ? rd_data : {DW{1'b0}};

jtframe_dual_ram #(.aw(AW+1),.dw(DW)) u_line(
    .clk0   ( clk           ),
    .clk1   ( clk           ),

    .data0  ( wr_data       ),
    .addr0  ( {line,wr_addr}),
    .we0    ( we            ),
    .q0     (               ),

    .data1  (               ),
    .addr1  ({~line,rd_addr}),
    .we1    ( 1'b0          ),
    .q1     ( rd_data       )
);

endmodule
module jtframe_linebuf #(parameter
    DW=8,
    AW=9
)(
    input            clk,
    input            LHBL,


    input   [AW-1:0] wr_addr,
    input   [DW-1:0] wr_data,
    input            we,

    input   [AW-1:0] rd_addr,
    output  [DW-1:0] rd_data,
    output  [DW-1:0] rd_gated
);


reg     line, last_LHBL;

wire [DW-1:0]       dump_data;

`ifdef SIMULATION
initial begin
    line = 0;
end
`endif

always @(posedge clk) begin
    last_LHBL <= LHBL;
    if( !LHBL && last_LHBL )
        line <= ~line;
end

assign rd_gated = LHBL ? rd_data : {DW{1'b0}};

jtframe_dual_ram #(.aw(AW+1),.dw(DW)) u_line(
    .clk0   ( clk           ),
    .clk1   ( clk           ),

    .data0  ( wr_data       ),
    .addr0  ( {line,wr_addr}),
    .we0    ( we            ),
    .q0     (               ),

    .data1  (               ),
    .addr1  ({~line,rd_addr}),
    .we1    ( 1'b0          ),
    .q1     ( rd_data       )
);

endmodule