data/full_repos/permissive/161029703/testbench/gpu_test/test_gpu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/161029703/testbench/gpu_test/test_gpu.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #5 rst_n = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/161029703/testbench/gpu_test/test_gpu.v:38: syntax error, unexpected \'@\'\n    @(negedge clk_bus);\n    ^\n%Error: data/full_repos/permissive/161029703/testbench/gpu_test/test_gpu.v:44: syntax error, unexpected \'@\'\n    @(negedge clk_bus);\n    ^\n%Error: data/full_repos/permissive/161029703/testbench/gpu_test/test_gpu.v:47: syntax error, unexpected \'@\'\n    @(negedge clk_bus);\n    ^\n%Error: data/full_repos/permissive/161029703/testbench/gpu_test/test_gpu.v:50: syntax error, unexpected \'@\'\n    @(negedge clk_bus);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/testbench/gpu_test/test_gpu.v:54: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk_pixel = ~clk_pixel;  \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/testbench/gpu_test/test_gpu.v:55: Unsupported: Ignoring delay on this delayed statement.\nalways #50 clk_bus = ~clk_bus;  \n       ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_gpu ();

reg clk_bus;
reg clk_pixel;
reg rst_n;
wire de;
wire vsync;
wire hsync;
wire[8:0] pxlData;

reg bus_write;
reg[23:0] bus_address;
reg[31:0] bus_data_i;

gpu dut( 
    .clk_bus  (clk_bus),
    .clk_pixel(clk_pixel),
    .rst_n    (rst_n),
    .bus_read (1'b0),
    .bus_write(bus_write),
    .bus_address(bus_address),
    .bus_data_i(bus_data_i),
    .bus_stall(),
    .bus_data_o(),
    .de       (de),
    .vsync    (vsync),
    .hsync    (hsync),
    .pxlData  (pxlData)
);

initial begin 
    bus_write = 0;
    clk_bus = 0;
    clk_pixel = 0;
    rst_n = 0;
    #5 rst_n = 1;
    @(negedge clk_bus);
    @(negedge clk_bus);
    @(negedge clk_bus);
    bus_write = 1;
    bus_address = 24'h50000;
    bus_data_i = 800*2/32;
    @(negedge clk_bus);
    bus_address = 0;
    bus_data_i = 32'haaaaaaaa;
    @(negedge clk_bus);
    bus_address = (800*600/32-1)*4;
    bus_data_i = 32'h55555555;
    @(negedge clk_bus);
    bus_write = 0;
end

always #10 clk_pixel = ~clk_pixel;
always #50 clk_bus = ~clk_bus;

endmodule
module test_gpu ();


reg clk_bus;
reg clk_pixel;
reg rst_n;
wire de;
wire vsync;
wire hsync;
wire[8:0] pxlData;

reg bus_write;
reg[23:0] bus_address;
reg[31:0] bus_data_i;

gpu dut( 
    .clk_bus  (clk_bus),
    .clk_pixel(clk_pixel),
    .rst_n    (rst_n),
    .bus_read (1'b0),
    .bus_write(bus_write),
    .bus_address(bus_address),
    .bus_data_i(bus_data_i),
    .bus_stall(),
    .bus_data_o(),
    .de       (de),
    .vsync    (vsync),
    .hsync    (hsync),
    .pxlData  (pxlData)
);

initial begin 
    bus_write = 0;
    clk_bus = 0;
    clk_pixel = 0;
    rst_n = 0;
    #5 rst_n = 1;
    @(negedge clk_bus);
    @(negedge clk_bus);
    @(negedge clk_bus);
    bus_write = 1;
    bus_address = 24'h50000;
    bus_data_i = 800*2/32;
    @(negedge clk_bus);
    bus_address = 0;
    bus_data_i = 32'haaaaaaaa;
    @(negedge clk_bus);
    bus_address = (800*600/32-1)*4;
    bus_data_i = 32'h55555555;
    @(negedge clk_bus);
    bus_write = 0;
end

always #10 clk_pixel = ~clk_pixel;
always #50 clk_bus = ~clk_bus;

endmodule