data/full_repos/permissive/211891954/Finite States Machine/Maquina de Mealy/Exemplo 2/mealy.v
 line:12: before: "rst"
1: b'%Error: Cannot find file containing module: States\n        ... Looked in:\n             data/full_repos/permissive/211891954/Finite/States\n             data/full_repos/permissive/211891954/Finite/States.v\n             data/full_repos/permissive/211891954/Finite/States.sv\n             States\n             States.v\n             States.sv\n             obj_dir/States\n             obj_dir/States.v\n             obj_dir/States.sv\n%Error: Cannot find file containing module: Machine/Maquina\n%Error: Cannot find file containing module: de\n%Error: Cannot find file containing module: Mealy/Exemplo\n%Error: Cannot find file containing module: 2,data/full_repos/permissive/211891954\n%Error: Cannot find file containing module: data/full_repos/permissive/211891954/Finite\n%Error: Cannot find file containing module: 2/mealy.v\n%Error: Exiting due to 7 error(s)\n'
module zero_zero_one_zero(clk,rst,in);
    input wire clk,rst,in;

    reg[2:0] state;
    reg[2:0] next_state;
    parameter  S0 = 3'b000,
               S1 = 3'b001,
               S2 = 3'b010,
               S3 = 3'b011,
               S4 = 3'b100;

    always @(posedge clk or rst or in) begin
        if(rst)begin
            state = S0;
        end
        else begin
            case(state)
                S0:begin
                    if(in == 1'b0)
                        next_state = S1;
                    else
                        next_state = S2;  
                end

                S1:begin
                    if(in == 1'b0)
                        next_state = S2;
                    else
                        next_state = S1; 
                end

                S2:begin
                    if(in == 1'b1)
                        next_state = S3;
                    else
                        next_state = S4; 
                end

                S3:begin
                    if(in == 1'b0)
                        next_state = S1;
                    else
                        next_state = S0; 
                end

                S4:begin
                    if(in == 1'b0)
                        next_state = S4;
                    else
                        next_state = S0; 
                end
            endcase
        end
    end
endmodule
module zero_zero_one_zero(clk,rst,in);

    input wire clk,rst,in;

    reg[2:0] state;
    reg[2:0] next_state;
    parameter  S0 = 3'b000,
               S1 = 3'b001,
               S2 = 3'b010,
               S3 = 3'b011,
               S4 = 3'b100;

    always @(posedge clk or rst or in) begin
        if(rst)begin
            state = S0;
        end
        else begin
            case(state)
                S0:begin
                    if(in == 1'b0)
                        next_state = S1;
                    else
                        next_state = S2;  
                end

                S1:begin
                    if(in == 1'b0)
                        next_state = S2;
                    else
                        next_state = S1; 
                end

                S2:begin
                    if(in == 1'b1)
                        next_state = S3;
                    else
                        next_state = S4; 
                end

                S3:begin
                    if(in == 1'b0)
                        next_state = S1;
                    else
                        next_state = S0; 
                end

                S4:begin
                    if(in == 1'b0)
                        next_state = S4;
                    else
                        next_state = S0; 
                end
            endcase
        end
    end
endmodule