data/full_repos/permissive/103463431/axi_test.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/103463431/axi_test.v:1: Cannot find include file: Macros.v\n`include "Macros.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/103463431,data/full_repos/permissive/103463431/Macros.v\n             data/full_repos/permissive/103463431,data/full_repos/permissive/103463431/Macros.v.v\n             data/full_repos/permissive/103463431,data/full_repos/permissive/103463431/Macros.v.sv\n             Macros.v\n             Macros.v.v\n             Macros.v.sv\n             obj_dir/Macros.v\n             obj_dir/Macros.v.v\n             obj_dir/Macros.v.sv\n%Error: data/full_repos/permissive/103463431/axi_test.v:2: Cannot find include file: axi4dummy.v\n`include "axi4dummy.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103463431/axi_test.v:199: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("axi_tester.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/103463431/axi_test.v:200: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0,axi_tester);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:209: Unsupported: Ignoring delay on this delayed statement.\n      forever #1 clock_axi = !clock_axi;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:218: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:220: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/103463431/axi_test.v:237: syntax error, unexpected \'@\'\n        @(posedge clock_axi) begin\n        ^\n%Error: data/full_repos/permissive/103463431/axi_test.v:247: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/103463431/axi_test.v:281: Unsupported: fork statements\n        fork  \n        ^~~~\n%Error: data/full_repos/permissive/103463431/axi_test.v:287: syntax error, unexpected \'@\'\n                @(clock_axi);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:290: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Error: data/full_repos/permissive/103463431/axi_test.v:298: syntax error, unexpected \'@\'\n                @(clock_axi);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:301: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Error: data/full_repos/permissive/103463431/axi_test.v:309: syntax error, unexpected \'@\'\n              @(clock_axi);\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:315: Unsupported: Ignoring delay on this delayed statement.\n       #1\n       ^\n%Error: data/full_repos/permissive/103463431/axi_test.v:340: Unsupported: fork statements\n        fork  \n        ^~~~\n%Error: data/full_repos/permissive/103463431/axi_test.v:346: syntax error, unexpected \'@\'\n                @(clock_axi);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:349: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:352: Unsupported: Ignoring delay on this delayed statement.\n             #1\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:358: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Error: Exiting due to 12 error(s), 9 warning(s)\n'
module axi_tester ();

  parameter
    AWIDTH = 64,
    DWIDTH = 64,
    IDWIDTH = 4,
    UWIDTH =  0,
    NUM_WORDS = 24;

  localparam

    DBYTES = (DWIDTH/8),

    AWID = IDWIDTH,
    AWADDR = AWIDTH,
    AWLEN = 8,
    AWSIZE =  3,
    AWBURST = 2,
    AWCACHE = 4,
    AWPROT = 3,
    AWQOS = 4,
    AWREGION = 4,
    AWUSER = UWIDTH,
    WDATA = DWIDTH,
    WSTRB = DBYTES,
    WUSER = UWIDTH,
    BID = IDWIDTH,
    BRESP = 2,
    BUSER = UWIDTH,
    ARID = IDWIDTH,
    ARADDR = AWIDTH,
    ARLEN = 8,
    ARSIZE = 3,
    ARBURST = 2,
    ARCACHE = 4,
    ARPROT = 3,
    ARQOS = 4,
    ARREGION = 4,
    ARUSER = UWIDTH,
    RID = IDWIDTH,
    RDATA = DWIDTH,
    RRESP = 2,
    RUSER = UWIDTH,

    DEBUG = 0;

  reg [AWADDR-1:0]              store_m_axi_awaddr;
  reg [AWID-1:0]                store_m_axi_awid;
  reg [AWLEN-1:0]               store_m_axi_awlen;
  reg [AWSIZE-1:0]              store_m_axi_awsize;
  reg [AWBURST-1:0]             store_m_axi_awburst;
  reg                           store_m_axi_awlock;
  reg [AWCACHE-1:0]             store_m_axi_awcache;
  reg [AWPROT-1:0]              store_m_axi_awprot;
  reg [AWQOS-1:0]               store_m_axi_awqos;
  reg [AWREGION-1:0]            store_m_axi_awregion;
  reg [AWUSER-1:0]              store_m_axi_awuser;
  reg                           store_m_axi_awvalid;
  wire                          store_s_axi_awready;

  reg [WDATA-1:0]               store_m_axi_wdata;
  reg [WSTRB-1:0]               store_m_axi_wstrb;
  reg                           store_m_axi_wlast;
  reg [WUSER-1:0]               store_m_axi_wuser;
  reg                           store_m_axi_wvalid;
  wire                          store_s_axi_wready;

  wire [BID-1:0]                store_s_axi_bid;
  wire [BRESP-1:0]              store_s_axi_bresp;
  wire [BUSER-1:0]              store_s_axi_buser;
  wire                          store_s_axi_bvalid;
  reg                           store_m_axi_bready;

  reg [ARADDR-1:0]              load_m_axi_araddr;
  reg [ARID-1:0]                load_m_axi_arid;
  reg [ARLEN-1:0]               load_m_axi_arlen;
  reg [ARSIZE-1:0]              load_m_axi_arsize;
  reg [ARBURST-1:0]             load_m_axi_arburst;
  reg                           load_m_axi_arlock;
  reg [ARCACHE-1:0]             load_m_axi_arcache;
  reg [ARPROT-1:0]              load_m_axi_arprot;
  reg [ARQOS-1:0]               load_m_axi_arqos;
  reg [ARREGION-1:0]            load_m_axi_arregion;
  reg [ARUSER-1:0]              load_m_axi_aruser;
  reg                           load_m_axi_arvalid;
  wire                          load_s_axi_arready;

  wire [RID-1:0]                load_s_axi_rid;
  reg [RID-1:0] read_id;
  wire [RDATA-1:0]              load_s_axi_rdata;
  reg [RDATA-1:0] read_data;
  wire [RRESP-1:0]              load_s_axi_rresp;
  wire                          load_s_axi_rlast;
  wire [RUSER-1:0]              load_s_axi_ruser;
  wire                          load_s_axi_rvalid;
  reg                           load_m_axi_rready;

  reg [0:0]  clock_axi;
  reg [0:0]  reset_axi_n;



    axi4dummy #(
      .NUM_WORDS(             NUM_WORDS),
      .AWIDTH(                AWIDTH),
      .DWIDTH(                DWIDTH),
      .IDWIDTH(               IDWIDTH),
      .INITIAL_VALUE(         {(NUM_WORDS*DWIDTH){1'b0}})
    ) DUT (
      .clock_axi(             clock_axi),
      .reset_axi_n(           reset_axi_n),

      .s_axi_awaddr(          store_m_axi_awaddr),
      .s_axi_awid(            store_m_axi_awid),
      .s_axi_awlen(           store_m_axi_awlen),
      .s_axi_awsize(          store_m_axi_awsize),
      .s_axi_awburst(         store_m_axi_awburst),
      .s_axi_awlock(          store_m_axi_awlock),
      .s_axi_awcache(         store_m_axi_awcache),
      .s_axi_awprot(          store_m_axi_awprot),
      .s_axi_awqos(           store_m_axi_awqos),
      .s_axi_awregion(        store_m_axi_awregion),
      .s_axi_awvalid(         store_m_axi_awvalid),
      .s_axi_awready(         store_s_axi_awready),
      .s_axi_awuser(          store_m_axi_awuser),

      .s_axi_wdata(           store_m_axi_wdata),
      .s_axi_wstrb(           store_m_axi_wstrb),
      .s_axi_wlast(           store_m_axi_wlast),
      .s_axi_wuser(           store_m_axi_wuser),
      .s_axi_wvalid(          store_m_axi_wvalid),
      .s_axi_wready(          store_s_axi_wready),

      .s_axi_bid(             store_s_axi_bid),
      .s_axi_bresp(           store_s_axi_bresp),
      .s_axi_buser(           store_s_axi_buser),
      .s_axi_bvalid(          store_s_axi_bvalid),
      .s_axi_bready(          store_m_axi_bready),

      .s_axi_araddr(          load_m_axi_araddr),
      .s_axi_arid(            load_m_axi_arid),
      .s_axi_arlen(           load_m_axi_arlen),
      .s_axi_arsize(          load_m_axi_arsize),
      .s_axi_arburst(         load_m_axi_arburst),
      .s_axi_arlock(          load_m_axi_arlock),
      .s_axi_arcache(         load_m_axi_arcache),
      .s_axi_arprot(          load_m_axi_arprot),
      .s_axi_arqos(           load_m_axi_arqos),
      .s_axi_arregion(        load_m_axi_arregion),
      .s_axi_arvalid(         load_m_axi_arvalid),
      .s_axi_arready(         load_s_axi_arready),

      .s_axi_rid(             load_s_axi_rid),
      .s_axi_rdata(           load_s_axi_rdata),
      .s_axi_rresp(           load_s_axi_rresp),
      .s_axi_rlast(           load_s_axi_rlast),
      .s_axi_ruser(           load_s_axi_ruser),
      .s_axi_rvalid(          load_s_axi_rvalid),
      .s_axi_rready(          load_m_axi_rready)
      );


  initial
   begin
      $dumpfile("axi_tester.vcd");
      $dumpvars(0,axi_tester);
   end


   initial
    begin
      clock_axi = 0;
      store_m_axi_wlast = 0;
      store_m_axi_bready = 1;
      forever #1 clock_axi = !clock_axi;
    end


  initial begin
    reset(2);

    store(4'b0000,8'b00,3'b011, 2'b00, 64'h0000_0000_0000_0000, 64'hDEAD_BEEF_DEAD_BEEF);

    #10
    load(4'b0000,8'b00,3'b011, 2'b00, 64'h0000_0000_0000_0000);
    #10
    $finish;
  end





  task reset;
    input [31:0] reset_cycles;

    begin
      reset_axi_n = 0;
      repeat (reset_cycles)
        @(posedge clock_axi) begin
          load_m_axi_arvalid <= 0;
          store_m_axi_awvalid <= 0;
          store_m_axi_wvalid <= 0;
          load_m_axi_rready <= 0;
        end
      reset_axi_n = 1;
      $display ("");
      $display("==== Reset complete, Time = %0d units", $time);
      $display ("");
    end

  endtask



  task automatic store;
    input [AWID-1:0]                awid;
    input [AWLEN-1:0]               awlen;
    input [AWSIZE-1:0]              awsize;
    input [AWBURST-1:0]             awburst;
    input [AWADDR-1:0]              awaddr;
    input [WDATA-1:0]               wdata;

    begin
      store_m_axi_awid = awid;
      store_m_axi_awlen = awlen;
      store_m_axi_awsize = awsize;
      store_m_axi_awburst = awburst;


        store_m_axi_bready <= 1;
        store_m_axi_awvalid <= 1;
        store_m_axi_awaddr <= awaddr;


        store_m_axi_wdata <= wdata;
        store_m_axi_wstrb <= 8'hFF;
        store_m_axi_wlast <= 1'b1;
        store_m_axi_wvalid <= 1'b1;


        fork


          begin
            while (store_s_axi_awready != 1)
              begin
                @(clock_axi);
              end
            if (DEBUG == 1) $display ("AWREADY = %0d @ Time = %0d units", store_s_axi_awready, $time);
            #1
           store_m_axi_awvalid <= 0;
          end


          begin
            while (store_s_axi_wready != 1)
              begin
                @(clock_axi);
            end
            if (DEBUG == 1) $display ("WREADY = %0d @ Time = %0d units", store_s_axi_wready, $time);
            #1
            store_m_axi_wlast <= 0;
            store_m_axi_wvalid <= 0;
          end


          begin
            while (store_s_axi_bvalid !=1)
              @(clock_axi);
            if (DEBUG == 1) if (store_s_axi_bresp === 2'b00) $display ("BRESP = %0d (OK) @ Time = %0d units", store_s_axi_bresp, $time);
          end

       join

       #1
       $display ("==== Store data = 0x%h, Address = 0x%h", wdata, awaddr);
       $display ("");
    end

   endtask


  task load;
    input  [ARID-1:0]               arid;
    input  [ARLEN-1:0]              arlen;
    input  [ARSIZE-1:0]             arsize;
    input  [ARBURST-1:0]            arburst;
    input  [ARADDR-1:0]             araddr;

    begin
      load_m_axi_arid = arid;
      load_m_axi_arlen = arlen;
      load_m_axi_arsize = arsize;
      load_m_axi_arburst = arburst;


        load_m_axi_arvalid <= 1;
        load_m_axi_araddr <= araddr;

        fork


          begin
            while (load_s_axi_arready != 1)
              begin
                @(clock_axi);
              end
            if (DEBUG == 1) $display ("ARREADY = %0d @ Time = %0d units", load_s_axi_arready, $time);
            #1
            load_m_axi_arvalid <= 0;
            load_m_axi_rready <= 1;
             #1
            if (DEBUG == 1) begin
              if (load_s_axi_rresp === 2'b00) $display ("RRESP = %0d (OK) @ Time = %0d units", load_s_axi_rresp, $time);
            end
            $display ("==== Loaded data = 0x%h, Address = 0x%h", load_s_axi_rdata, araddr);
            $display ("");
            #1
            load_m_axi_rready <= 0;
          end
       join
     end

  endtask

endmodule
module axi_tester ();


  parameter
    AWIDTH = 64,
    DWIDTH = 64,
    IDWIDTH = 4,
    UWIDTH =  0,
    NUM_WORDS = 24;

  localparam

    DBYTES = (DWIDTH/8),

    AWID = IDWIDTH,
    AWADDR = AWIDTH,
    AWLEN = 8,
    AWSIZE =  3,
    AWBURST = 2,
    AWCACHE = 4,
    AWPROT = 3,
    AWQOS = 4,
    AWREGION = 4,
    AWUSER = UWIDTH,
    WDATA = DWIDTH,
    WSTRB = DBYTES,
    WUSER = UWIDTH,
    BID = IDWIDTH,
    BRESP = 2,
    BUSER = UWIDTH,
    ARID = IDWIDTH,
    ARADDR = AWIDTH,
    ARLEN = 8,
    ARSIZE = 3,
    ARBURST = 2,
    ARCACHE = 4,
    ARPROT = 3,
    ARQOS = 4,
    ARREGION = 4,
    ARUSER = UWIDTH,
    RID = IDWIDTH,
    RDATA = DWIDTH,
    RRESP = 2,
    RUSER = UWIDTH,

    DEBUG = 0;

  reg [AWADDR-1:0]              store_m_axi_awaddr;
  reg [AWID-1:0]                store_m_axi_awid;
  reg [AWLEN-1:0]               store_m_axi_awlen;
  reg [AWSIZE-1:0]              store_m_axi_awsize;
  reg [AWBURST-1:0]             store_m_axi_awburst;
  reg                           store_m_axi_awlock;
  reg [AWCACHE-1:0]             store_m_axi_awcache;
  reg [AWPROT-1:0]              store_m_axi_awprot;
  reg [AWQOS-1:0]               store_m_axi_awqos;
  reg [AWREGION-1:0]            store_m_axi_awregion;
  reg [AWUSER-1:0]              store_m_axi_awuser;
  reg                           store_m_axi_awvalid;
  wire                          store_s_axi_awready;

  reg [WDATA-1:0]               store_m_axi_wdata;
  reg [WSTRB-1:0]               store_m_axi_wstrb;
  reg                           store_m_axi_wlast;
  reg [WUSER-1:0]               store_m_axi_wuser;
  reg                           store_m_axi_wvalid;
  wire                          store_s_axi_wready;

  wire [BID-1:0]                store_s_axi_bid;
  wire [BRESP-1:0]              store_s_axi_bresp;
  wire [BUSER-1:0]              store_s_axi_buser;
  wire                          store_s_axi_bvalid;
  reg                           store_m_axi_bready;

  reg [ARADDR-1:0]              load_m_axi_araddr;
  reg [ARID-1:0]                load_m_axi_arid;
  reg [ARLEN-1:0]               load_m_axi_arlen;
  reg [ARSIZE-1:0]              load_m_axi_arsize;
  reg [ARBURST-1:0]             load_m_axi_arburst;
  reg                           load_m_axi_arlock;
  reg [ARCACHE-1:0]             load_m_axi_arcache;
  reg [ARPROT-1:0]              load_m_axi_arprot;
  reg [ARQOS-1:0]               load_m_axi_arqos;
  reg [ARREGION-1:0]            load_m_axi_arregion;
  reg [ARUSER-1:0]              load_m_axi_aruser;
  reg                           load_m_axi_arvalid;
  wire                          load_s_axi_arready;

  wire [RID-1:0]                load_s_axi_rid;
  reg [RID-1:0] read_id;
  wire [RDATA-1:0]              load_s_axi_rdata;
  reg [RDATA-1:0] read_data;
  wire [RRESP-1:0]              load_s_axi_rresp;
  wire                          load_s_axi_rlast;
  wire [RUSER-1:0]              load_s_axi_ruser;
  wire                          load_s_axi_rvalid;
  reg                           load_m_axi_rready;

  reg [0:0]  clock_axi;
  reg [0:0]  reset_axi_n;



    axi4dummy #(
      .NUM_WORDS(             NUM_WORDS),
      .AWIDTH(                AWIDTH),
      .DWIDTH(                DWIDTH),
      .IDWIDTH(               IDWIDTH),
      .INITIAL_VALUE(         {(NUM_WORDS*DWIDTH){1'b0}})
    ) DUT (
      .clock_axi(             clock_axi),
      .reset_axi_n(           reset_axi_n),

      .s_axi_awaddr(          store_m_axi_awaddr),
      .s_axi_awid(            store_m_axi_awid),
      .s_axi_awlen(           store_m_axi_awlen),
      .s_axi_awsize(          store_m_axi_awsize),
      .s_axi_awburst(         store_m_axi_awburst),
      .s_axi_awlock(          store_m_axi_awlock),
      .s_axi_awcache(         store_m_axi_awcache),
      .s_axi_awprot(          store_m_axi_awprot),
      .s_axi_awqos(           store_m_axi_awqos),
      .s_axi_awregion(        store_m_axi_awregion),
      .s_axi_awvalid(         store_m_axi_awvalid),
      .s_axi_awready(         store_s_axi_awready),
      .s_axi_awuser(          store_m_axi_awuser),

      .s_axi_wdata(           store_m_axi_wdata),
      .s_axi_wstrb(           store_m_axi_wstrb),
      .s_axi_wlast(           store_m_axi_wlast),
      .s_axi_wuser(           store_m_axi_wuser),
      .s_axi_wvalid(          store_m_axi_wvalid),
      .s_axi_wready(          store_s_axi_wready),

      .s_axi_bid(             store_s_axi_bid),
      .s_axi_bresp(           store_s_axi_bresp),
      .s_axi_buser(           store_s_axi_buser),
      .s_axi_bvalid(          store_s_axi_bvalid),
      .s_axi_bready(          store_m_axi_bready),

      .s_axi_araddr(          load_m_axi_araddr),
      .s_axi_arid(            load_m_axi_arid),
      .s_axi_arlen(           load_m_axi_arlen),
      .s_axi_arsize(          load_m_axi_arsize),
      .s_axi_arburst(         load_m_axi_arburst),
      .s_axi_arlock(          load_m_axi_arlock),
      .s_axi_arcache(         load_m_axi_arcache),
      .s_axi_arprot(          load_m_axi_arprot),
      .s_axi_arqos(           load_m_axi_arqos),
      .s_axi_arregion(        load_m_axi_arregion),
      .s_axi_arvalid(         load_m_axi_arvalid),
      .s_axi_arready(         load_s_axi_arready),

      .s_axi_rid(             load_s_axi_rid),
      .s_axi_rdata(           load_s_axi_rdata),
      .s_axi_rresp(           load_s_axi_rresp),
      .s_axi_rlast(           load_s_axi_rlast),
      .s_axi_ruser(           load_s_axi_ruser),
      .s_axi_rvalid(          load_s_axi_rvalid),
      .s_axi_rready(          load_m_axi_rready)
      );


  initial
   begin
      $dumpfile("axi_tester.vcd");
      $dumpvars(0,axi_tester);
   end


   initial
    begin
      clock_axi = 0;
      store_m_axi_wlast = 0;
      store_m_axi_bready = 1;
      forever #1 clock_axi = !clock_axi;
    end


  initial begin
    reset(2);

    store(4'b0000,8'b00,3'b011, 2'b00, 64'h0000_0000_0000_0000, 64'hDEAD_BEEF_DEAD_BEEF);

    #10
    load(4'b0000,8'b00,3'b011, 2'b00, 64'h0000_0000_0000_0000);
    #10
    $finish;
  end





  task reset;
    input [31:0] reset_cycles;

    begin
      reset_axi_n = 0;
      repeat (reset_cycles)
        @(posedge clock_axi) begin
          load_m_axi_arvalid <= 0;
          store_m_axi_awvalid <= 0;
          store_m_axi_wvalid <= 0;
          load_m_axi_rready <= 0;
        end
      reset_axi_n = 1;
      $display ("");
      $display("==== Reset complete, Time = %0d units", $time);
      $display ("");
    end

  endtask



  task automatic store;
    input [AWID-1:0]                awid;
    input [AWLEN-1:0]               awlen;
    input [AWSIZE-1:0]              awsize;
    input [AWBURST-1:0]             awburst;
    input [AWADDR-1:0]              awaddr;
    input [WDATA-1:0]               wdata;

    begin
      store_m_axi_awid = awid;
      store_m_axi_awlen = awlen;
      store_m_axi_awsize = awsize;
      store_m_axi_awburst = awburst;


        store_m_axi_bready <= 1;
        store_m_axi_awvalid <= 1;
        store_m_axi_awaddr <= awaddr;


        store_m_axi_wdata <= wdata;
        store_m_axi_wstrb <= 8'hFF;
        store_m_axi_wlast <= 1'b1;
        store_m_axi_wvalid <= 1'b1;


        fork


          begin
            while (store_s_axi_awready != 1)
              begin
                @(clock_axi);
              end
            if (DEBUG == 1) $display ("AWREADY = %0d @ Time = %0d units", store_s_axi_awready, $time);
            #1
           store_m_axi_awvalid <= 0;
          end


          begin
            while (store_s_axi_wready != 1)
              begin
                @(clock_axi);
            end
            if (DEBUG == 1) $display ("WREADY = %0d @ Time = %0d units", store_s_axi_wready, $time);
            #1
            store_m_axi_wlast <= 0;
            store_m_axi_wvalid <= 0;
          end


          begin
            while (store_s_axi_bvalid !=1)
              @(clock_axi);
            if (DEBUG == 1) if (store_s_axi_bresp === 2'b00) $display ("BRESP = %0d (OK) @ Time = %0d units", store_s_axi_bresp, $time);
          end

       join

       #1
       $display ("==== Store data = 0x%h, Address = 0x%h", wdata, awaddr);
       $display ("");
    end

   endtask


  task load;
    input  [ARID-1:0]               arid;
    input  [ARLEN-1:0]              arlen;
    input  [ARSIZE-1:0]             arsize;
    input  [ARBURST-1:0]            arburst;
    input  [ARADDR-1:0]             araddr;

    begin
      load_m_axi_arid = arid;
      load_m_axi_arlen = arlen;
      load_m_axi_arsize = arsize;
      load_m_axi_arburst = arburst;


        load_m_axi_arvalid <= 1;
        load_m_axi_araddr <= araddr;

        fork


          begin
            while (load_s_axi_arready != 1)
              begin
                @(clock_axi);
              end
            if (DEBUG == 1) $display ("ARREADY = %0d @ Time = %0d units", load_s_axi_arready, $time);
            #1
            load_m_axi_arvalid <= 0;
            load_m_axi_rready <= 1;
             #1
            if (DEBUG == 1) begin
              if (load_s_axi_rresp === 2'b00) $display ("RRESP = %0d (OK) @ Time = %0d units", load_s_axi_rresp, $time);
            end
            $display ("==== Loaded data = 0x%h, Address = 0x%h", load_s_axi_rdata, araddr);
            $display ("");
            #1
            load_m_axi_rready <= 0;
          end
       join
     end

  endtask

endmodule