data/full_repos/permissive/154352170/EX_MEM.v
None: at end of input
data/verilator_xmls/c9eb9908-d5a0-41a6-a202-53881898e910.xml
module EX_MEM(
    input clk,
    input reset,
	 input EX_MEM_En,
	 input [31:0] IR_In,
	 input [31:0] RD2_In,
	 input [31:0] PC_Out_In,
	 input [31:0] ALU_Out_In,
	 output [31:0] IR_Out,
	 output [31:0] RD2_Out,
	 output [31:0] PC_Out_Out,
	 output [31:0] ALU_Out_Out
    );
	 
	 reg [31:0] IR;
	 reg [31:0] RD2;
	 reg [31:0] PC;
	 reg [31:0] ALU_Out;
	 
	 assign IR_Out = IR;
	 assign RD2_Out = RD2;
	 assign PC_Out_Out = PC;
	 assign ALU_Out_Out = ALU_Out;
    
	 initial begin
	    IR = 32'h00000000;
		 RD2 = 32'h00000000;
		 PC = 32'h00000000;
		 ALU_Out = 32'h00000000;
	 end
	 
	 always @ (posedge clk) begin
	    
		 if (reset) begin
		    IR <= 0;
			 RD2 <= 0;
			 PC <= 0;
			 ALU_Out <= 0;
		 end
		 
		 else begin
		    IR <= IR_In;
			 RD2 <= RD2_In;
			 PC <= PC_Out_In;
			 ALU_Out <= ALU_Out_In;
		 end
		 
	 end

endmodule
module EX_MEM(
    input clk,
    input reset,
	 input EX_MEM_En,
	 input [31:0] IR_In,
	 input [31:0] RD2_In,
	 input [31:0] PC_Out_In,
	 input [31:0] ALU_Out_In,
	 output [31:0] IR_Out,
	 output [31:0] RD2_Out,
	 output [31:0] PC_Out_Out,
	 output [31:0] ALU_Out_Out
    );

	 
	 reg [31:0] IR;
	 reg [31:0] RD2;
	 reg [31:0] PC;
	 reg [31:0] ALU_Out;
	 
	 assign IR_Out = IR;
	 assign RD2_Out = RD2;
	 assign PC_Out_Out = PC;
	 assign ALU_Out_Out = ALU_Out;
    
	 initial begin
	    IR = 32'h00000000;
		 RD2 = 32'h00000000;
		 PC = 32'h00000000;
		 ALU_Out = 32'h00000000;
	 end
	 
	 always @ (posedge clk) begin
	    
		 if (reset) begin
		    IR <= 0;
			 RD2 <= 0;
			 PC <= 0;
			 ALU_Out <= 0;
		 end
		 
		 else begin
		    IR <= IR_In;
			 RD2 <= RD2_In;
			 PC <= PC_Out_In;
			 ALU_Out <= ALU_Out_In;
		 end
		 
	 end

endmodule