data/full_repos/permissive/110056451/plotfour_top.v
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1: b'%Warning-IMPLICIT: data/full_repos/permissive/110056451/plotfour_top.v:531: Signal definition not found, creating implicitly: \'enable_1\'\n                                                                          : ... Suggested alternative: \'enable\'\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n        ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:347: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n            x1 <= 8\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:348: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n            y1 <= 7\'b0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:353: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh64\' generates 32 or 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    c1 <= 100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:359: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:360: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:363: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00011000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:364: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:367: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00101110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:368: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:371: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01000100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:372: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:375: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01011010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:376: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:379: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01110000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:380: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:383: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b10000110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:384: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:387: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:388: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h16\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:391: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00011000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:392: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:395: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00101110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:396: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:399: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01000100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:400: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:403: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01011010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:404: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:407: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01110000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:408: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:411: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b10000110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:412: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h15\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0010101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:415: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:416: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h2a\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:419: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00011000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:420: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:423: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00101110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:424: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:427: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01000100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:428: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:431: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01011010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:432: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:435: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01110000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:436: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:439: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b10000110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:440: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h28\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0101000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:443: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:444: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:447: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00011000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:448: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111011;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:451: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00101110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:452: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111011;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:455: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01000100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:456: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111011;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:459: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01011010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:460: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111011;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:463: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01110000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:464: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111011;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:467: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b10000110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h3b\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b0111011;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:471: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:472: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h51\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1010001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:475: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00011000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:476: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1001110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:479: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00101110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:480: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1001110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:483: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01000100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:484: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1001110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:487: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01011010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:488: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1001110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:491: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01110000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:492: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1001110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:495: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b10000110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:496: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1001110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:499: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00000010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:500: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h65\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100101;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:503: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h18\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00011000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:504: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:507: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2e\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b00101110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:508: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:511: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01000100;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:512: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:515: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01011010;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:516: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:519: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h70\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b01110000;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:520: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:523: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h86\' generates 8 bits.\n                                                                       : ... In instance plotfour_top.d0\n    x1 <= 8\'b10000110;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:524: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                       : ... In instance plotfour_top.d0\n    y1 <= 7\'b1100001;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:531: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                       : ... In instance plotfour_top.d0\n assign enable_1 = (controlB == 2\'b00) ? 1 : 0;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:534: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'controlA\' generates 4 bits.\n                                                                       : ... In instance plotfour_top.d0\n assign X = x1 + controlA;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:535: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'controlC\' generates 4 bits.\n                                                                       : ... In instance plotfour_top.d0\n assign Y = y1 + controlC;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:170: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   blue   <= 1\'b0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:171: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   red    <= 1\'b0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:286: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:288: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:290: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:292: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:294: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_one_win <= 1\'b1; p_one_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:296: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_one_win <= 1\'b0; p_one_score <= 1\'b0; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:310: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:312: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:314: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:316: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:318: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_two_win <= 1\'b1; p_two_score <= 1\'b1; end\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:320: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                       : ... In instance plotfour_top.fsm\n   begin p_two_win <= 1\'b0; p_two_score <= 1\'b1; end\n                                        ^~\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:23: Little bit endian vector: MSB < LSB of bit range: 0:3\n input  [0:3]  KEY;      \n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/110056451/plotfour_top.v:31: Little bit endian vector: MSB < LSB of bit range: 0:4\n output  [0:4]  LEDR;      \n         ^\n%Error: data/full_repos/permissive/110056451/plotfour_top.v:59: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter\n             data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.v\n             data/full_repos/permissive/110056451,data/full_repos/permissive/110056451/vga_adapter.sv\n             vga_adapter\n             vga_adapter.v\n             vga_adapter.sv\n             obj_dir/vga_adapter\n             obj_dir/vga_adapter.v\n             obj_dir/vga_adapter.sv\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'X\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'x\' generates 8 bits.\n                                                                      : ... In instance plotfour_top\n    datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:80: Output port connection \'Y\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'y\' generates 7 bits.\n                                                                      : ... In instance plotfour_top\n    datapath d0(SW[5:0], CLOCK_50, KEY[0], KEY[1], KEY[2], enable, x, y, colour);\n                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:146: Output port connection \'p_one_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n                                                                       : ... In instance plotfour_top\n  .p_one_score(p_one_score),\n   ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:147: Output port connection \'p_two_score\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_two_score\' generates 1 bits.\n                                                                       : ... In instance plotfour_top\n  .p_two_score(p_two_score)\n   ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/110056451/plotfour_top.v:151: Input port connection \'hex_digit\' expects 4 bits on the pin connection, but pin connection\'s VARREF \'p_one_score\' generates 1 bits.\n                                                                       : ... In instance plotfour_top\n  .hex_digit(p_one_score),\n   ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 112 warning(s)\n'
module control (go_p1, go_p2, reset_n, clock, enable, plot);
	input go_p1, go_p2, reset_n, clock;
	output reg enable, plot;

	always@(*) begin

		enable = 1'b0;
		plot = 1'b0;

		if (go_p1 || go_p2) begin
			plot = 1'b1;
			enable = 1'b1;
		end
	end
endmodule
module control (go_p1, go_p2, reset_n, clock, enable, plot);

	input go_p1, go_p2, reset_n, clock;
	output reg enable, plot;

	always@(*) begin

		enable = 1'b0;
		plot = 1'b0;

		if (go_p1 || go_p2) begin
			plot = 1'b1;
			enable = 1'b1;
		end
	end
endmodule