data/full_repos/permissive/140157152/hdl/timer_1.v
data/verilator_xmls/ff24de93-e6a4-417a-83c9-931580cf1285.xml
module timer_1 (
	input clock,
	input start,
	output running);

parameter SIZE = 32;
parameter RESET_VALUE = -40000000;

reg [SIZE-1:0] counter = 0;

assign running = |counter;

always @(posedge clock) begin
	if (start)
		counter <= RESET_VALUE;
	else if (running)
		counter <= counter + 1'b1;
end
	
endmodule
module timer_1 (
	input clock,
	input start,
	output running);


parameter SIZE = 32;
parameter RESET_VALUE = -40000000;

reg [SIZE-1:0] counter = 0;

assign running = |counter;

always @(posedge clock) begin
	if (start)
		counter <= RESET_VALUE;
	else if (running)
		counter <= counter + 1'b1;
end
	
endmodule