data/full_repos/permissive/204486675/components/freqcnt/freqcount.v
 line:19: before: ")"
1: b"%Error: data/full_repos/permissive/204486675/components/freqcnt/freqcount.v:19: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/204486675/components/freqcnt/freqcount.v:31: syntax error, unexpected always\nalways @(posedge clkin or posedge rst)\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module freqcount (
rst,
clkin,

signaledge,

signal,
count,
);

input rst;
input clkin;
input signaledge;
input signal;
output reg [15:0] count;
reg [15:0] internalcount;
reg [15:0] clockcount;

reg signal_last;

always @(posedge clkin or posedge rst)
if (rst)
begin
	signal_last <= 1'b0;
	internalcount <= 16'b0;
	clockcount <= 16'b0;
	count <= 16'b0;
end
else
begin
	if (signaledge == 1'b0)
	begin
		if((signal_last == 1'b1)&&(signal == 1'b0))
		begin
			internalcount <= internalcount + 1;
		end
	end
	else
	begin
		if((signal_last == 1'b0)&&(signal == 1'b1))
		begin
			internalcount <= internalcount + 1;
		end
	end
	
	signal_last <= signal;

	clockcount <= clockcount + 1;

	if (clockcount == 16'b0)
	begin
		count <= internalcount;
		internalcount <= 0;
	end
end

endmodule
module freqcount (
rst,
clkin,

signaledge,

signal,
count,
);


input rst;
input clkin;
input signaledge;
input signal;
output reg [15:0] count;
reg [15:0] internalcount;
reg [15:0] clockcount;

reg signal_last;

always @(posedge clkin or posedge rst)
if (rst)
begin
	signal_last <= 1'b0;
	internalcount <= 16'b0;
	clockcount <= 16'b0;
	count <= 16'b0;
end
else
begin
	if (signaledge == 1'b0)
	begin
		if((signal_last == 1'b1)&&(signal == 1'b0))
		begin
			internalcount <= internalcount + 1;
		end
	end
	else
	begin
		if((signal_last == 1'b0)&&(signal == 1'b1))
		begin
			internalcount <= internalcount + 1;
		end
	end
	
	signal_last <= signal;

	clockcount <= clockcount + 1;

	if (clockcount == 16'b0)
	begin
		count <= internalcount;
		internalcount <= 0;
	end
end

endmodule