data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/PC.v
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data/verilator_xmls/dafb17ac-b6a1-4d54-b6fc-f5dccaf2cd24.xml
module PC(
PCWre, NextAddress, CLK, RST, CurrentAddress
);
    
    input  PCWre;
    input wire [31:0]NextAddress;
    input  CLK;
    input  RST;
    output reg [31:0] CurrentAddress;
    

       always@(posedge CLK)begin
           if(RST == 0)begin
               CurrentAddress = 0;
           end
           else if(!PCWre)begin
               CurrentAddress = CurrentAddress;
           end
           else if(PCWre)begin
               CurrentAddress = NextAddress;
           end
       end
endmodule
module PC(
PCWre, NextAddress, CLK, RST, CurrentAddress
);

    
    input  PCWre;
    input wire [31:0]NextAddress;
    input  CLK;
    input  RST;
    output reg [31:0] CurrentAddress;
    

       always@(posedge CLK)begin
           if(RST == 0)begin
               CurrentAddress = 0;
           end
           else if(!PCWre)begin
               CurrentAddress = CurrentAddress;
           end
           else if(PCWre)begin
               CurrentAddress = NextAddress;
           end
       end
endmodule