data/full_repos/permissive/143278/ivltests/pr602.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr602.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (x !== 2\'b00) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr602.v:58: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (x !== 2\'b01) begin\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [1:0] a [3:0], x;

   integer   i;
   initial begin
      a[0] = 0;
      a[1] = 1;
      a[2] = 2;
      a[3] = 3;



      $display("a[(1-1)+0] = %b", a[(1-1)+0]);
      $display("a[(2-1)+0] = %b", a[(2-1)+0]);
      x =  a[(1-1)+0];
      if (x !== 2'b00) begin
	 $display("FAILED -- x == %b", x);
	 $finish;
      end

      x =  a[(2-1)+0];
      if (x !== 2'b01) begin
	 $display("FAILED -- x == %b", x);
	 $finish;
      end

      x <=  a[(1-1)+0];
      #1 if (x !== 2'b00) begin
	 $display("FAILED -- x == %b", x);
	 $finish;
      end

      x <=  a[(2-1)+0];
      #1 if (x !== 2'b01) begin
	 $display("FAILED -- x == %b", x);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;


   reg [1:0] a [3:0], x;

   integer   i;
   initial begin
      a[0] = 0;
      a[1] = 1;
      a[2] = 2;
      a[3] = 3;



      $display("a[(1-1)+0] = %b", a[(1-1)+0]);
      $display("a[(2-1)+0] = %b", a[(2-1)+0]);
      x =  a[(1-1)+0];
      if (x !== 2'b00) begin
	 $display("FAILED -- x == %b", x);
	 $finish;
      end

      x =  a[(2-1)+0];
      if (x !== 2'b01) begin
	 $display("FAILED -- x == %b", x);
	 $finish;
      end

      x <=  a[(1-1)+0];
      #1 if (x !== 2'b00) begin
	 $display("FAILED -- x == %b", x);
	 $finish;
      end

      x <=  a[(2-1)+0];
      #1 if (x !== 2'b01) begin
	 $display("FAILED -- x == %b", x);
	 $finish;
      end

      $display("PASSED");
   end
endmodule