data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v
 line:27: before: ";"
1: b'%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:52: Cannot find include file: clogb2.vh\n`include "clogb2.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue,data/full_repos/permissive/197252258/clogb2.vh\n             data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue,data/full_repos/permissive/197252258/clogb2.vh.v\n             data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue,data/full_repos/permissive/197252258/clogb2.vh.sv\n             clogb2.vh\n             clogb2.vh.v\n             clogb2.vh.sv\n             obj_dir/clogb2.vh\n             obj_dir/clogb2.vh.v\n             obj_dir/clogb2.vh.sv\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:6: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]       enq_seq,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:7: Define or directive not defined: \'`TX_CNT_W\'\n    input   [`TX_CNT_W-1:0]             enq_seq_tx_id,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:10: Define or directive not defined: \'`MAX_QUEUE_BITS\'\n    input   [`MAX_QUEUE_BITS-1:0]       pkt_queue_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:11: Define or directive not defined: \'`MAX_TX_ID_BITS\'\n    input   [`MAX_TX_ID_BITS-1:0]       tx_id_queue_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:12: Define or directive not defined: \'`PKT_QUEUE_IND_W\'\n    input   [`PKT_QUEUE_IND_W-1:0]      pkt_queue_tail_in,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:13: Define or directive not defined: \'`PKT_QUEUE_IND_W\'\n    input   [`PKT_QUEUE_IND_W-1:0]      pkt_queue_size_in,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:16: Define or directive not defined: \'`MAX_QUEUE_BITS\'\n    output  [`MAX_QUEUE_BITS-1:0]       pkt_queue_out,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:17: Define or directive not defined: \'`MAX_TX_ID_BITS\'\n    output  [`MAX_TX_ID_BITS-1:0]       tx_id_queue_out,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:18: Define or directive not defined: \'`PKT_QUEUE_IND_W\'\n    output  [`PKT_QUEUE_IND_W-1:0]      pkt_queue_tail_out,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:19: Define or directive not defined: \'`PKT_QUEUE_IND_W\'\n    output  [`PKT_QUEUE_IND_W-1:0]      pkt_queue_size_out\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:27: Define or directive not defined: \'`MAX_PKT_QUEUE_SIZE\'\nfor (i = 0; i < `MAX_PKT_QUEUE_SIZE; i = i + 1) begin: gen_pkt_queue\n                ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nfor (i = 0; i < `MAX_PKT_QUEUE_SIZE; i = i + 1) begin: gen_pkt_queue\n                                   ^\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:28: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    assign pkt_queue_out[(i + 1) * `FLOW_SEQ_NUM_W - 1 -: `FLOW_SEQ_NUM_W] = (i == pkt_queue_tail_in) ? enq_seq : \n                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:28: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    assign pkt_queue_out[(i + 1) * `FLOW_SEQ_NUM_W - 1 -: `FLOW_SEQ_NUM_W] = (i == pkt_queue_tail_in) ? enq_seq : \n                                                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:29: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n                                                                             pkt_queue_in[(i + 1) * `FLOW_SEQ_NUM_W - 1 -: `FLOW_SEQ_NUM_W];    \n                                                                                                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:29: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n                                                                             pkt_queue_in[(i + 1) * `FLOW_SEQ_NUM_W - 1 -: `FLOW_SEQ_NUM_W];    \n                                                                                                                           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:35: Define or directive not defined: \'`MAX_PKT_QUEUE_SIZE\'\nfor (i = 0; i < `MAX_PKT_QUEUE_SIZE; i = i + 1) begin: gen_tx_id_queue\n                ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:36: Define or directive not defined: \'`TX_CNT_W\'\n    assign tx_id_queue_out[(i + 1) * `TX_CNT_W - 1 -: `TX_CNT_W] = (i == pkt_queue_tail_in) ? enq_seq_tx_id : \n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:36: Define or directive not defined: \'`TX_CNT_W\'\n    assign tx_id_queue_out[(i + 1) * `TX_CNT_W - 1 -: `TX_CNT_W] = (i == pkt_queue_tail_in) ? enq_seq_tx_id : \n                                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:37: Define or directive not defined: \'`TX_CNT_W\'\n                                                                   tx_id_queue_in[(i + 1) * `TX_CNT_W - 1 -: `TX_CNT_W];    \n                                                                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:37: Define or directive not defined: \'`TX_CNT_W\'\n                                                                   tx_id_queue_in[(i + 1) * `TX_CNT_W - 1 -: `TX_CNT_W];    \n                                                                                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:43: Define or directive not defined: \'`PKT_QUEUE_IND_W\'\nwire    [`PKT_QUEUE_IND_W:0]    next_tail;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:44: Define or directive not defined: \'`PKT_QUEUE_IND_W\'\nassign  next_tail = pkt_queue_tail_in + {{(`PKT_QUEUE_IND_W-1){1\'b0}}, 1\'b1};\n                                           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:46: Define or directive not defined: \'`FLOW_SEQ_NONE\'\nassign pkt_queue_tail_out = (enq_seq == `FLOW_SEQ_NONE) ? pkt_queue_tail_in : next_tail[`PKT_QUEUE_IND_W-1:0];\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign pkt_queue_tail_out = (enq_seq == `FLOW_SEQ_NONE) ? pkt_queue_tail_in : next_tail[`PKT_QUEUE_IND_W-1:0];\n                                                      ^\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:46: Define or directive not defined: \'`PKT_QUEUE_IND_W\'\nassign pkt_queue_tail_out = (enq_seq == `FLOW_SEQ_NONE) ? pkt_queue_tail_in : next_tail[`PKT_QUEUE_IND_W-1:0];\n                                                                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:49: Define or directive not defined: \'`FLOW_SEQ_NONE\'\nassign pkt_queue_size_out = (enq_seq == `FLOW_SEQ_NONE) ? pkt_queue_size_in : (pkt_queue_size_in + {{(`PKT_QUEUE_IND_W-1){1\'b0}}, 1\'b1});\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign pkt_queue_size_out = (enq_seq == `FLOW_SEQ_NONE) ? pkt_queue_size_in : (pkt_queue_size_in + {{(`PKT_QUEUE_IND_W-1){1\'b0}}, 1\'b1});\n                                                      ^\n%Error: data/full_repos/permissive/197252258/src/cr_engine/common/event_processors/cr_enqueue/cr_enqueue.v:49: Define or directive not defined: \'`PKT_QUEUE_IND_W\'\nassign pkt_queue_size_out = (enq_seq == `FLOW_SEQ_NONE) ? pkt_queue_size_in : (pkt_queue_size_in + {{(`PKT_QUEUE_IND_W-1){1\'b0}}, 1\'b1});\n                                                                                                      ^~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module cr_enqueue (

            
    input   [`FLOW_SEQ_NUM_W-1:0]       enq_seq,
    input   [`TX_CNT_W-1:0]             enq_seq_tx_id,


    input   [`MAX_QUEUE_BITS-1:0]       pkt_queue_in,
    input   [`MAX_TX_ID_BITS-1:0]       tx_id_queue_in,
    input   [`PKT_QUEUE_IND_W-1:0]      pkt_queue_tail_in,
    input   [`PKT_QUEUE_IND_W-1:0]      pkt_queue_size_in,


    output  [`MAX_QUEUE_BITS-1:0]       pkt_queue_out,
    output  [`MAX_TX_ID_BITS-1:0]       tx_id_queue_out,
    output  [`PKT_QUEUE_IND_W-1:0]      pkt_queue_tail_out,
    output  [`PKT_QUEUE_IND_W-1:0]      pkt_queue_size_out
);



genvar i;

generate
for (i = 0; i < `MAX_PKT_QUEUE_SIZE; i = i + 1) begin: gen_pkt_queue
    assign pkt_queue_out[(i + 1) * `FLOW_SEQ_NUM_W - 1 -: `FLOW_SEQ_NUM_W] = (i == pkt_queue_tail_in) ? enq_seq : 
                                                                             pkt_queue_in[(i + 1) * `FLOW_SEQ_NUM_W - 1 -: `FLOW_SEQ_NUM_W];    
end
endgenerate


generate
for (i = 0; i < `MAX_PKT_QUEUE_SIZE; i = i + 1) begin: gen_tx_id_queue
    assign tx_id_queue_out[(i + 1) * `TX_CNT_W - 1 -: `TX_CNT_W] = (i == pkt_queue_tail_in) ? enq_seq_tx_id : 
                                                                   tx_id_queue_in[(i + 1) * `TX_CNT_W - 1 -: `TX_CNT_W];    
end
endgenerate



wire    [`PKT_QUEUE_IND_W:0]    next_tail;
assign  next_tail = pkt_queue_tail_in + {{(`PKT_QUEUE_IND_W-1){1'b0}}, 1'b1};

assign pkt_queue_tail_out = (enq_seq == `FLOW_SEQ_NONE) ? pkt_queue_tail_in : next_tail[`PKT_QUEUE_IND_W-1:0];


assign pkt_queue_size_out = (enq_seq == `FLOW_SEQ_NONE) ? pkt_queue_size_in : (pkt_queue_size_in + {{(`PKT_QUEUE_IND_W-1){1'b0}}, 1'b1});


`include "clogb2.vh"
endmodule
module cr_enqueue (

            
    input   [`FLOW_SEQ_NUM_W-1:0]       enq_seq,
    input   [`TX_CNT_W-1:0]             enq_seq_tx_id,


    input   [`MAX_QUEUE_BITS-1:0]       pkt_queue_in,
    input   [`MAX_TX_ID_BITS-1:0]       tx_id_queue_in,
    input   [`PKT_QUEUE_IND_W-1:0]      pkt_queue_tail_in,
    input   [`PKT_QUEUE_IND_W-1:0]      pkt_queue_size_in,


    output  [`MAX_QUEUE_BITS-1:0]       pkt_queue_out,
    output  [`MAX_TX_ID_BITS-1:0]       tx_id_queue_out,
    output  [`PKT_QUEUE_IND_W-1:0]      pkt_queue_tail_out,
    output  [`PKT_QUEUE_IND_W-1:0]      pkt_queue_size_out
);




genvar i;

generate
for (i = 0; i < `MAX_PKT_QUEUE_SIZE; i = i + 1) begin: gen_pkt_queue
    assign pkt_queue_out[(i + 1) * `FLOW_SEQ_NUM_W - 1 -: `FLOW_SEQ_NUM_W] = (i == pkt_queue_tail_in) ? enq_seq : 
                                                                             pkt_queue_in[(i + 1) * `FLOW_SEQ_NUM_W - 1 -: `FLOW_SEQ_NUM_W];    
end
endgenerate


generate
for (i = 0; i < `MAX_PKT_QUEUE_SIZE; i = i + 1) begin: gen_tx_id_queue
    assign tx_id_queue_out[(i + 1) * `TX_CNT_W - 1 -: `TX_CNT_W] = (i == pkt_queue_tail_in) ? enq_seq_tx_id : 
                                                                   tx_id_queue_in[(i + 1) * `TX_CNT_W - 1 -: `TX_CNT_W];    
end
endgenerate



wire    [`PKT_QUEUE_IND_W:0]    next_tail;
assign  next_tail = pkt_queue_tail_in + {{(`PKT_QUEUE_IND_W-1){1'b0}}, 1'b1};

assign pkt_queue_tail_out = (enq_seq == `FLOW_SEQ_NONE) ? pkt_queue_tail_in : next_tail[`PKT_QUEUE_IND_W-1:0];


assign pkt_queue_size_out = (enq_seq == `FLOW_SEQ_NONE) ? pkt_queue_size_in : (pkt_queue_size_in + {{(`PKT_QUEUE_IND_W-1){1'b0}}, 1'b1});


`include "clogb2.vh"
endmodule