data/full_repos/permissive/143278/ivltests/br_gh307.v
 line:2: before: "typedef"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh307.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 ;  \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   two_bits src;
   wire two_bits dst;

   simple copy(src, dst);
   assign dst.b2.b = src.b2.b;

   initial begin
      src.b1.b = 1'b1;
      src.b2.b = 1'b0;
      #1 ;
      $display("src=%b (s.b. 10), dst=%b (s.b. 10)", src, dst);
      if (src !== 2'b10 || dst !== 2'b10) begin
	 $display("FAILED");
	 $finish;
      end
      $display("PASSED");
      $finish;
   end

endmodule
module main;


   two_bits src;
   wire two_bits dst;

   simple copy(src, dst);
   assign dst.b2.b = src.b2.b;

   initial begin
      src.b1.b = 1'b1;
      src.b2.b = 1'b0;
      #1 ;
      $display("src=%b (s.b. 10), dst=%b (s.b. 10)", src, dst);
      if (src !== 2'b10 || dst !== 2'b10) begin
	 $display("FAILED");
	 $finish;
      end
      $display("PASSED");
      $finish;
   end

endmodule