data/full_repos/permissive/143278/ivltests/posedge.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/posedge.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #1  flag1 = 0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/posedge.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #1  event_1 = 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/posedge.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/posedge.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ();

   reg flag1;
   reg event_1;

   always @ (posedge event_1)  flag1 = ~flag1;

   initial begin
      event_1 = 1'b0;
      #1  flag1 = 0;

      #1  event_1 = 1'b1;

      #1
	if (flag1 !== 1'b1) begin
	   $display("FAILED -- 0->1 didn't trigger flag1");
	   $finish;
	end

      event_1 = 1'b0;

      #1
	if (flag1 !== 1'b1) begin
	   $display("FAILED -- 1->0 DID trigger flag1");
	   $finish;
	end

      $display("PASSED");
   end

endmodule
module main ();


   reg flag1;
   reg event_1;

   always @ (posedge event_1)  flag1 = ~flag1;

   initial begin
      event_1 = 1'b0;
      #1  flag1 = 0;

      #1  event_1 = 1'b1;

      #1
	if (flag1 !== 1'b1) begin
	   $display("FAILED -- 0->1 didn't trigger flag1");
	   $finish;
	end

      event_1 = 1'b0;

      #1
	if (flag1 !== 1'b1) begin
	   $display("FAILED -- 1->0 DID trigger flag1");
	   $finish;
	end

      $display("PASSED");
   end

endmodule