data/full_repos/permissive/162786998/testbench/lcd_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/162786998/testbench/lcd_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #(time_cycle*2) rstn = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/162786998/testbench/lcd_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #(time_cycle*2) rstn = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/162786998/testbench/lcd_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #(time_cycle/2) clk = ~clk;\n    ^\n%Error: data/full_repos/permissive/162786998/testbench/lcd_tb.v:76: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("lcd_wv.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/162786998/testbench/lcd_tb.v:77: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, dut);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/162786998/testbench/lcd_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #(time_cycle*5);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/162786998/testbench/lcd_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #time_cycle;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/162786998/testbench/lcd_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n    #(time_cycle*1800);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/162786998/testbench/lcd_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n    #time_cycle;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/162786998/testbench/lcd_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n    #(time_cycle*3000000);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/162786998/testbench/lcd_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n    #(time_cycle*100);\n    ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lcd_tb();


parameter time_cycle = 10;


reg clk, rstn;
reg [2:0] command;
reg valid_in;
reg [7:0] fifo_rd_data;
reg fifo_empty;

wire busy;
wire error;
wire fifo_rd_en;

wire rst_lcd;
wire scl_lcd;
wire sda_lcd;
wire cs_lcd;
wire rs_lcd;
wire led_lcd;


lcd_ctrl dut(
    .clk(clk),
    .rstn(rstn),
    .command(command),
    .valid_in(valid_in),
    .busy(busy),
    .error(error),
    .fifo_rd_en(fifo_rd_en),
    .fifo_rd_data(fifo_rd_data),
    .fifo_empty(fifo_empty),
    .rst_lcd(rst_lcd),
    .scl_lcd(scl_lcd),
    .sda_lcd(sda_lcd),
    .cs_lcd(cd__lcd),
    .rs_lcd(rs_lcd),
    .led_lcd(led_lcd)
);


initial begin
    clk = 1;
    rstn = 1;
    #(time_cycle*2) rstn = 0;
    #(time_cycle*2) rstn = 1;
end

always begin
    #(time_cycle/2) clk = ~clk;
end


initial begin
    $dumpfile("lcd_wv.vcd");
    $dumpvars(0, dut);
end


initial begin
    

    command = 3'd0;
    valid_in = 1'b0;
    fifo_rd_data = 8'haa;
    fifo_empty = 1'b0;
    #(time_cycle*5);

    command = 3'd1;
    valid_in = 1'b1;
    #time_cycle;
    command = 3'd1;
    valid_in = 1'b0;
    fifo_rd_data = 8'haa;
    fifo_empty = 1'b0;
    #(time_cycle*1800);


























    command = 3'd5;
    valid_in = 1'b1;
    fifo_rd_data = 8'h9a;
    fifo_empty = 1'b1;
    #time_cycle;
    command = 3'd5;
    valid_in = 1'b0;
    fifo_rd_data = 8'h9a;
    fifo_empty = 1'b1;
    #(time_cycle*3000000);



















    #(time_cycle*100);
    $finish;
end

endmodule
module lcd_tb();



parameter time_cycle = 10;


reg clk, rstn;
reg [2:0] command;
reg valid_in;
reg [7:0] fifo_rd_data;
reg fifo_empty;

wire busy;
wire error;
wire fifo_rd_en;

wire rst_lcd;
wire scl_lcd;
wire sda_lcd;
wire cs_lcd;
wire rs_lcd;
wire led_lcd;


lcd_ctrl dut(
    .clk(clk),
    .rstn(rstn),
    .command(command),
    .valid_in(valid_in),
    .busy(busy),
    .error(error),
    .fifo_rd_en(fifo_rd_en),
    .fifo_rd_data(fifo_rd_data),
    .fifo_empty(fifo_empty),
    .rst_lcd(rst_lcd),
    .scl_lcd(scl_lcd),
    .sda_lcd(sda_lcd),
    .cs_lcd(cd__lcd),
    .rs_lcd(rs_lcd),
    .led_lcd(led_lcd)
);


initial begin
    clk = 1;
    rstn = 1;
    #(time_cycle*2) rstn = 0;
    #(time_cycle*2) rstn = 1;
end

always begin
    #(time_cycle/2) clk = ~clk;
end


initial begin
    $dumpfile("lcd_wv.vcd");
    $dumpvars(0, dut);
end


initial begin
    

    command = 3'd0;
    valid_in = 1'b0;
    fifo_rd_data = 8'haa;
    fifo_empty = 1'b0;
    #(time_cycle*5);

    command = 3'd1;
    valid_in = 1'b1;
    #time_cycle;
    command = 3'd1;
    valid_in = 1'b0;
    fifo_rd_data = 8'haa;
    fifo_empty = 1'b0;
    #(time_cycle*1800);


























    command = 3'd5;
    valid_in = 1'b1;
    fifo_rd_data = 8'h9a;
    fifo_empty = 1'b1;
    #time_cycle;
    command = 3'd5;
    valid_in = 1'b0;
    fifo_rd_data = 8'h9a;
    fifo_empty = 1'b1;
    #(time_cycle*3000000);



















    #(time_cycle*100);
    $finish;
end

endmodule