data/full_repos/permissive/166008742/src/tb_ctrl_logic.v
 line:95: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_ctrl_logic.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/166008742/src/tb_ctrl_logic.v:95: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_ctrl_logic.v:98: syntax error, unexpected \'@\'\n        repeat (200) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_ctrl_logic.v:100: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_ctrl_logic();
    parameter ADDR_WIDTH = 32;
    parameter DATA_WIDTH = 32;
    parameter NBUFS = 13;

    reg reset;
    reg clk;

    wire [ADDR_WIDTH-1:0] wb_address;
    wire [DATA_WIDTH-1:0] wb_writedata;
    wire [DATA_WIDTH-1:0] wb_readdata;
    wire wb_strobe;
    wire wb_cycle;
    wire wb_write;
    wire wb_ack;


    wire [DATA_WIDTH-1:0] update_buf_id;
    wire update_buf;
    reg  buf_updated;


    wire [DATA_WIDTH-1:0] led_tx_buf_id;
    wire led_tx;
    reg  led_tx_done;



    buf_manager #(ADDR_WIDTH, DATA_WIDTH, NBUFS) buf_man
    (
        .reset(reset),
        .clk(clk),


        .wbs_address(wb_address),
        .wbs_writedata(wb_writedata),
        .wbs_readdata(wb_readdata),
        .wbs_strobe(wb_strobe),
        .wbs_cycle(wb_cycle),
        .wbs_write(wb_write),
        .wbs_ack(wb_ack)
    );

    ctrl_logic #(ADDR_WIDTH, DATA_WIDTH) dut
    (
        .reset(reset),
        .clk(clk),

        .wbm_address(wb_address),
        .wbm_writedata(wb_writedata),
        .wbm_readdata(wb_readdata),
        .wbm_strobe(wb_strobe),
        .wbm_cycle(wb_cycle),
        .wbm_write(wb_write),
        .wbm_ack(wb_ack),
        
        .update_buf_id(update_buf_id),
        .update_buf(update_buf),
        .buf_updated(buf_updated),

        .led_tx_buf_id(led_tx_buf_id),
        .led_tx(led_tx),
        .led_tx_done(led_tx_done)
    );


    always begin
        #1;
        clk <= ~clk;
    end

    initial begin
            clk <= 0;
            reset <= 1;
            buf_updated <= 0;
            led_tx_done <= 0;

        repeat (100) @(posedge clk);
            reset <= 0;

        repeat (200) @(posedge clk);
            buf_updated <= 1;
        @(posedge clk);
            buf_updated <= 0;
    end

endmodule
module tb_ctrl_logic();

    parameter ADDR_WIDTH = 32;
    parameter DATA_WIDTH = 32;
    parameter NBUFS = 13;

    reg reset;
    reg clk;

    wire [ADDR_WIDTH-1:0] wb_address;
    wire [DATA_WIDTH-1:0] wb_writedata;
    wire [DATA_WIDTH-1:0] wb_readdata;
    wire wb_strobe;
    wire wb_cycle;
    wire wb_write;
    wire wb_ack;


    wire [DATA_WIDTH-1:0] update_buf_id;
    wire update_buf;
    reg  buf_updated;


    wire [DATA_WIDTH-1:0] led_tx_buf_id;
    wire led_tx;
    reg  led_tx_done;



    buf_manager #(ADDR_WIDTH, DATA_WIDTH, NBUFS) buf_man
    (
        .reset(reset),
        .clk(clk),


        .wbs_address(wb_address),
        .wbs_writedata(wb_writedata),
        .wbs_readdata(wb_readdata),
        .wbs_strobe(wb_strobe),
        .wbs_cycle(wb_cycle),
        .wbs_write(wb_write),
        .wbs_ack(wb_ack)
    );

    ctrl_logic #(ADDR_WIDTH, DATA_WIDTH) dut
    (
        .reset(reset),
        .clk(clk),

        .wbm_address(wb_address),
        .wbm_writedata(wb_writedata),
        .wbm_readdata(wb_readdata),
        .wbm_strobe(wb_strobe),
        .wbm_cycle(wb_cycle),
        .wbm_write(wb_write),
        .wbm_ack(wb_ack),
        
        .update_buf_id(update_buf_id),
        .update_buf(update_buf),
        .buf_updated(buf_updated),

        .led_tx_buf_id(led_tx_buf_id),
        .led_tx(led_tx),
        .led_tx_done(led_tx_done)
    );


    always begin
        #1;
        clk <= ~clk;
    end

    initial begin
            clk <= 0;
            reset <= 1;
            buf_updated <= 0;
            led_tx_done <= 0;

        repeat (100) @(posedge clk);
            reset <= 0;

        repeat (200) @(posedge clk);
            buf_updated <= 1;
        @(posedge clk);
            buf_updated <= 0;
    end

endmodule