data/full_repos/permissive/143278/ivltests/pr3296466b.v
 line:24: before: "$"
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr3296466b.v:3: Unsupported: Verilog 1995 gate primitive: tran\ntran(c[0], c[1]);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3296466b.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b", a);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3296466b.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b", a);\n  ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module connect(inout [1:0] c);

tran(c[0], c[1]);

endmodule
module connect(inout [1:0] c);


tran(c[0], c[1]);

endmodule