data/full_repos/permissive/100100285/rtl/cpram_sclk_2w1r.v
1: b"%Error: data/full_repos/permissive/100100285/rtl/cpram_sclk_2w1r.v:69: Cannot find file containing module: 'dpram_sclk'\ndpram_sclk\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100100285/rtl,data/full_repos/permissive/100100285/dpram_sclk\n             data/full_repos/permissive/100100285/rtl,data/full_repos/permissive/100100285/dpram_sclk.v\n             data/full_repos/permissive/100100285/rtl,data/full_repos/permissive/100100285/dpram_sclk.sv\n             dpram_sclk\n             dpram_sclk.v\n             dpram_sclk.sv\n             obj_dir/dpram_sclk\n             obj_dir/dpram_sclk.v\n             obj_dir/dpram_sclk.sv\n%Error: data/full_repos/permissive/100100285/rtl/cpram_sclk_2w1r.v:88: Cannot find file containing module: 'dpram_sclk'\ndpram_sclk\n^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module cpram_sclk_2w1r
#(
    parameter ADDR_WIDTH = 5,
    parameter DATA_WIDTH = 32,
    parameter CLEAR_ON_INIT = 1,
    parameter ENABLE_BYPASS = 1
)
(
    clk,
    rst,
    we1,
    waddr1,
    wdata1,
    we2,
    waddr2,
    wdata2,
    re,
    raddr,
    rdata
);


input                           clk;
input                           rst;
input                           we1;
input [ADDR_WIDTH-1:0]          waddr1;
input [DATA_WIDTH-1:0]          wdata1;
input                           we2;
input [ADDR_WIDTH-1:0]          waddr2;
input [DATA_WIDTH-1:0]          wdata2;
input                           re;
input [ADDR_WIDTH-1:0]          raddr;
output [DATA_WIDTH-1:0]         rdata;


wire [DATA_WIDTH-1:0]           dout;
wire [DATA_WIDTH-1:0]           dout0;
wire [DATA_WIDTH-1:0]           dout1;
wire [DATA_WIDTH-1:0]           dout2;
wire [DATA_WIDTH-1:0]           dout3;
reg                             sel_map[(1<<ADDR_WIDTH)-1:0];


dpram_sclk
    #(
      .ADDR_WIDTH       (ADDR_WIDTH),
      .DATA_WIDTH       (DATA_WIDTH),
      .CLEAR_ON_INIT    (CLEAR_ON_INIT),
      .ENABLE_BYPASS    (ENABLE_BYPASS)
    )
   mem0
    (
      .clk          (clk),
      .rst          (rst),
      .dout         (dout0),
      .raddr        (raddr),
      .re           (re),
      .waddr        (waddr1),
      .we           (we1),
      .din          (wdata1)
    );

dpram_sclk
    #(
      .ADDR_WIDTH       (ADDR_WIDTH),
      .DATA_WIDTH       (DATA_WIDTH),
      .CLEAR_ON_INIT    (CLEAR_ON_INIT),
      .ENABLE_BYPASS    (ENABLE_BYPASS)
    )
   mem1
    (
      .clk          (clk),
      .rst          (rst),
      .dout         (dout2),
      .raddr        (raddr),
      .re           (re),
      .waddr        (waddr2),
      .we           (we2),
      .din          (wdata2)
    );
    

assign dout = sel_map[raddr]==1'b0 ? dout0 : dout1;
    

generate
    if (ENABLE_BYPASS) begin : bypass_gen
assign rdata =
        (we2 && (raddr==waddr1)) ? wdata1 :
        (we1 && (raddr==waddr2)) ? wdata2 :
        dout;
    end else begin
assign rdata = dout;
    end
endgenerate
    

    always @(posedge clk)
        if (we1 && we2 && waddr1==waddr2)
            sel_map[waddr1] <= 1'b1;
        else if (we1 && we2) begin
            sel_map[waddr1] <= 1'b0;
            sel_map[waddr2] <= 1'b1;
        end
        else if (we1)
            sel_map[waddr1] <= 1'b0;
        else if (we2)
            sel_map[waddr2] <= 1'b1;
    
endmodule
module cpram_sclk_2w1r
#(
    parameter ADDR_WIDTH = 5,
    parameter DATA_WIDTH = 32,
    parameter CLEAR_ON_INIT = 1,
    parameter ENABLE_BYPASS = 1
)
(
    clk,
    rst,
    we1,
    waddr1,
    wdata1,
    we2,
    waddr2,
    wdata2,
    re,
    raddr,
    rdata
);



input                           clk;
input                           rst;
input                           we1;
input [ADDR_WIDTH-1:0]          waddr1;
input [DATA_WIDTH-1:0]          wdata1;
input                           we2;
input [ADDR_WIDTH-1:0]          waddr2;
input [DATA_WIDTH-1:0]          wdata2;
input                           re;
input [ADDR_WIDTH-1:0]          raddr;
output [DATA_WIDTH-1:0]         rdata;


wire [DATA_WIDTH-1:0]           dout;
wire [DATA_WIDTH-1:0]           dout0;
wire [DATA_WIDTH-1:0]           dout1;
wire [DATA_WIDTH-1:0]           dout2;
wire [DATA_WIDTH-1:0]           dout3;
reg                             sel_map[(1<<ADDR_WIDTH)-1:0];


dpram_sclk
    #(
      .ADDR_WIDTH       (ADDR_WIDTH),
      .DATA_WIDTH       (DATA_WIDTH),
      .CLEAR_ON_INIT    (CLEAR_ON_INIT),
      .ENABLE_BYPASS    (ENABLE_BYPASS)
    )
   mem0
    (
      .clk          (clk),
      .rst          (rst),
      .dout         (dout0),
      .raddr        (raddr),
      .re           (re),
      .waddr        (waddr1),
      .we           (we1),
      .din          (wdata1)
    );

dpram_sclk
    #(
      .ADDR_WIDTH       (ADDR_WIDTH),
      .DATA_WIDTH       (DATA_WIDTH),
      .CLEAR_ON_INIT    (CLEAR_ON_INIT),
      .ENABLE_BYPASS    (ENABLE_BYPASS)
    )
   mem1
    (
      .clk          (clk),
      .rst          (rst),
      .dout         (dout2),
      .raddr        (raddr),
      .re           (re),
      .waddr        (waddr2),
      .we           (we2),
      .din          (wdata2)
    );
    

assign dout = sel_map[raddr]==1'b0 ? dout0 : dout1;
    

generate
    if (ENABLE_BYPASS) begin : bypass_gen
assign rdata =
        (we2 && (raddr==waddr1)) ? wdata1 :
        (we1 && (raddr==waddr2)) ? wdata2 :
        dout;
    end else begin
assign rdata = dout;
    end
endgenerate
    

    always @(posedge clk)
        if (we1 && we2 && waddr1==waddr2)
            sel_map[waddr1] <= 1'b1;
        else if (we1 && we2) begin
            sel_map[waddr1] <= 1'b0;
            sel_map[waddr2] <= 1'b1;
        end
        else if (we1)
            sel_map[waddr1] <= 1'b0;
        else if (we2)
            sel_map[waddr2] <= 1'b1;
    
endmodule