data/full_repos/permissive/156129873/verilog/ex.v
1: b'%Error: data/full_repos/permissive/156129873/verilog/ex.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:50: Define or directive not defined: \'`Disable\'\n  pc_vmem_pause = `Disable;\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:50: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pc_vmem_pause = `Disable;\n                          ^\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:51: Define or directive not defined: \'`Disable\'\n  ifid_vmem_pause = `Disable;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:51: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  ifid_vmem_pause = `Disable;\n                            ^\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:53: Define or directive not defined: \'`MEM_WRITE_OP\'\n   `MEM_WRITE_OP, `MEM_READ_OP: begin\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:53: syntax error, unexpected \',\', expecting endcase\n   `MEM_WRITE_OP, `MEM_READ_OP: begin\n                ^\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:53: Define or directive not defined: \'`MEM_READ_OP\'\n   `MEM_WRITE_OP, `MEM_READ_OP: begin\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:54: Define or directive not defined: \'`Enable\'\n    pc_vmem_pause = `Enable;\n                    ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:55: Define or directive not defined: \'`Enable\'\n    ifid_vmem_pause = `Enable;\n                      ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:55: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    ifid_vmem_pause = `Enable;\n                             ^\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:57: syntax error, unexpected \':\', expecting clocking\n   default: begin\n          ^\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:75: Define or directive not defined: \'`ALU_AND_OP\'\n         `ALU_AND_OP, `ALU_OR_OP: begin\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:75: syntax error, unexpected \',\', expecting endcase\n         `ALU_AND_OP, `ALU_OR_OP: begin\n                    ^\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:75: Define or directive not defined: \'`ALU_OR_OP\'\n         `ALU_AND_OP, `ALU_OR_OP: begin\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:78: Define or directive not defined: \'`ALU_SLL_OP\'\n         `ALU_SLL_OP, `ALU_SRA_OP: begin\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:78: Define or directive not defined: \'`ALU_SRA_OP\'\n         `ALU_SLL_OP, `ALU_SRA_OP: begin\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:81: Define or directive not defined: \'`ALU_ADDU_OP\'\n         `ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP, `ALU_SUBU_OP, `ALU_SLTU_OP, `ALU_CMP_OP: begin\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:81: Define or directive not defined: \'`ALU_ADDIU_OP\'\n         `ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP, `ALU_SUBU_OP, `ALU_SLTU_OP, `ALU_CMP_OP: begin\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:81: Define or directive not defined: \'`ALU_ADDIU3_OP\'\n         `ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP, `ALU_SUBU_OP, `ALU_SLTU_OP, `ALU_CMP_OP: begin\n                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:81: Define or directive not defined: \'`ALU_ADDSP_OP\'\n         `ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP, `ALU_SUBU_OP, `ALU_SLTU_OP, `ALU_CMP_OP: begin\n                                                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:81: Define or directive not defined: \'`ALU_SUBU_OP\'\n         `ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP, `ALU_SUBU_OP, `ALU_SLTU_OP, `ALU_CMP_OP: begin\n                                                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:81: Define or directive not defined: \'`ALU_SLTU_OP\'\n         `ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP, `ALU_SUBU_OP, `ALU_SLTU_OP, `ALU_CMP_OP: begin\n                                                                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:81: Define or directive not defined: \'`ALU_CMP_OP\'\n         `ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP, `ALU_SUBU_OP, `ALU_SLTU_OP, `ALU_CMP_OP: begin\n                                                                                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:84: Define or directive not defined: \'`ALU_LI_OP\'\n   `ALU_LI_OP, `ALU_MFIH_OP, `ALU_MTIH_OP, `ALU_MTSP_OP, `ALU_MFPC_OP, `ALU_JALR_OP: begin\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:84: Define or directive not defined: \'`ALU_MFIH_OP\'\n   `ALU_LI_OP, `ALU_MFIH_OP, `ALU_MTIH_OP, `ALU_MTSP_OP, `ALU_MFPC_OP, `ALU_JALR_OP: begin\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:84: Define or directive not defined: \'`ALU_MTIH_OP\'\n   `ALU_LI_OP, `ALU_MFIH_OP, `ALU_MTIH_OP, `ALU_MTSP_OP, `ALU_MFPC_OP, `ALU_JALR_OP: begin\n                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:84: Define or directive not defined: \'`ALU_MTSP_OP\'\n   `ALU_LI_OP, `ALU_MFIH_OP, `ALU_MTIH_OP, `ALU_MTSP_OP, `ALU_MFPC_OP, `ALU_JALR_OP: begin\n                                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:84: Define or directive not defined: \'`ALU_MFPC_OP\'\n   `ALU_LI_OP, `ALU_MFIH_OP, `ALU_MTIH_OP, `ALU_MTSP_OP, `ALU_MFPC_OP, `ALU_JALR_OP: begin\n                                                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:84: Define or directive not defined: \'`ALU_JALR_OP\'\n   `ALU_LI_OP, `ALU_MFIH_OP, `ALU_MTIH_OP, `ALU_MTSP_OP, `ALU_MFPC_OP, `ALU_JALR_OP: begin\n                                                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:87: Define or directive not defined: \'`ALU_LW_OP\'\n   `ALU_LW_OP, `ALU_LWSP_OP: begin\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:87: Define or directive not defined: \'`ALU_LWSP_OP\'\n   `ALU_LW_OP, `ALU_LWSP_OP: begin\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:89: Define or directive not defined: \'`ZERO\'\n    writeData_o = `ZERO;\n                  ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:91: Define or directive not defined: \'`ALU_SW_OP\'\n   `ALU_SW_OP, `ALU_SWRS_OP, `ALU_SWSP_OP: begin\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:91: Define or directive not defined: \'`ALU_SWRS_OP\'\n   `ALU_SW_OP, `ALU_SWRS_OP, `ALU_SWSP_OP: begin\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:91: Define or directive not defined: \'`ALU_SWSP_OP\'\n   `ALU_SW_OP, `ALU_SWRS_OP, `ALU_SWSP_OP: begin\n                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:95: Define or directive not defined: \'`ZERO\'\n          writeData_o = `ZERO;\n                        ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:104: Define or directive not defined: \'`ALU_AND_OP\'\n    `ALU_AND_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:107: Define or directive not defined: \'`ALU_OR_OP\'\n    `ALU_OR_OP: begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:111: Define or directive not defined: \'`ZERO\'\n     logicout = `ZERO;\n                ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:119: Define or directive not defined: \'`ALU_SLL_OP\'\n    `ALU_SLL_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:126: Define or directive not defined: \'`ALU_SRA_OP\'\n    `ALU_SRA_OP: begin\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:134: Define or directive not defined: \'`ZERO\'\n     shiftout = `ZERO;\n                ^~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:140: Define or directive not defined: \'`ALU_SUBU_OP\'\n assign op2_i_mux = ((aluOp_i == `ALU_SUBU_OP) ||\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:141: Define or directive not defined: \'`ALU_SLTU_OP\'\n       (aluOp_i == `ALU_SLTU_OP)) ?\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:149: Define or directive not defined: \'`ALU_SLTU_OP\'\n assign op1_lt_op2 = (aluOp_i == `ALU_SLTU_OP) ?\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:149: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign op1_lt_op2 = (aluOp_i == `ALU_SLTU_OP) ?\n                                             ^\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:160: Define or directive not defined: \'`ALU_ADDU_OP\'\n    `ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP: begin\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:160: syntax error, unexpected \',\', expecting endcase\n    `ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP: begin\n                ^\n%Error: data/full_repos/permissive/156129873/verilog/ex.v:160: Define or directive not defined: \'`ALU_ADDIU_OP\'\n    `ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP: begin\n                  ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ex(


    

    input wire[15:0] operand1_i,
    input wire[15:0] operand2_i,
    input wire[4:0] aluOp_i,


    input wire[1:0] memOp_i,


    input wire writeReg_i,
    input wire[3:0] writeRegAddr_i,



	output reg[15:0] writeData_o,
	

    output reg[1:0] memOp_o,
    output reg[15:0] memAddr_o,
	

	output reg[3:0] writeRegAddr_o,
	output reg writeReg_o,


	output reg pc_vmem_pause,
	output reg ifid_vmem_pause
    );


	reg[15:0]		logicout;
	reg[15:0] 		shiftout;
	reg[15:0]		mathout;
	

	wire 			op1_lt_op2;
	wire 			op1_eq_op2;
	wire[15:0]		op2_i_mux;

	wire[15:0]		result_sum;


	always @(*) begin
		pc_vmem_pause = `Disable;
		ifid_vmem_pause = `Disable;
		case(memOp_i)
			`MEM_WRITE_OP, `MEM_READ_OP: begin
				pc_vmem_pause = `Enable;
				ifid_vmem_pause = `Enable;
			end
			default: begin
				
			end
		endcase
	end



	always @(*) begin

        memOp_o = memOp_i;
        memAddr_o = operand1_i;
    

        writeReg_o = writeReg_i;
        writeRegAddr_o = writeRegAddr_i;

        case (aluOp_i) 
        	`ALU_AND_OP, `ALU_OR_OP: begin
        		writeData_o = logicout;
        	end
        	`ALU_SLL_OP, `ALU_SRA_OP: begin
        		writeData_o = shiftout;
        	end
        	`ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP, `ALU_SUBU_OP, `ALU_SLTU_OP, `ALU_CMP_OP: begin
        		writeData_o = mathout;
        	end
			`ALU_LI_OP, `ALU_MFIH_OP, `ALU_MTIH_OP, `ALU_MTSP_OP, `ALU_MFPC_OP, `ALU_JALR_OP: begin
				writeData_o = operand1_i;
			end
			`ALU_LW_OP, `ALU_LWSP_OP: begin
				memAddr_o = operand1_i + operand2_i;
				writeData_o = `ZERO;
			end
			`ALU_SW_OP, `ALU_SWRS_OP, `ALU_SWSP_OP: begin
				writeData_o = operand2_i;
			end
        	default: begin
        		writeData_o = `ZERO;
        	end
        endcase
	end



	always @(*) begin
			case (aluOp_i)
				`ALU_AND_OP: begin
					logicout = operand1_i & operand2_i;
				end
				`ALU_OR_OP: begin
					logicout = operand1_i | operand2_i;
				end
				default: begin
					logicout = `ZERO;
				end
			endcase
	end


	always @(*) begin
			case (aluOp_i) 
				`ALU_SLL_OP: begin
					if (operand2_i[2:0] == 3'b000) begin
						shiftout = operand1_i << 4'd8;
					end else begin
						shiftout = operand1_i << operand2_i[2:0];
					end
				end
				`ALU_SRA_OP: begin
					if (operand2_i[2:0] == 3'b000) begin
						shiftout = (operand1_i >> 4'd8) | ({16{operand1_i[15]}}) << 4'd8;
					end else begin
						shiftout = (operand1_i >> operand2_i[2:0]) | ({16{operand1_i[15]}} << (5'd16 - {2'b00, operand2_i[2:0]}));
					end
				end
				default: begin
					shiftout = `ZERO;
				end
			endcase
	end


	assign op2_i_mux = ((aluOp_i == `ALU_SUBU_OP) ||
						 (aluOp_i == `ALU_SLTU_OP)) ?
						 (~operand2_i) + 1 : operand2_i;

	assign result_sum = operand1_i + op2_i_mux;




	assign op1_lt_op2 = (aluOp_i == `ALU_SLTU_OP) ?
						  ((operand1_i[15] && ~operand2_i[15]) || 
						  	(~operand1_i[15] && ~operand2_i[15] && result_sum[15])|| 
						  	(operand1_i[15] && operand2_i[15] && result_sum[15])) : (operand1_i < operand2_i);

	assign op1_neq_op2 = ~(operand1_i == operand2_i);



	always @(*) begin
			case (aluOp_i)
				`ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP: begin
					mathout = result_sum;
				end
				`ALU_SUBU_OP: begin
					mathout = result_sum;
				end
				`ALU_SLTU_OP: begin
					mathout = op1_lt_op2;
				end
				`ALU_CMP_OP: begin
					mathout = op1_neq_op2;
				end
				default: begin
					mathout = `ZERO;
				end
			endcase
	end

endmodule
module ex(


    

    input wire[15:0] operand1_i,
    input wire[15:0] operand2_i,
    input wire[4:0] aluOp_i,


    input wire[1:0] memOp_i,


    input wire writeReg_i,
    input wire[3:0] writeRegAddr_i,



	output reg[15:0] writeData_o,
	

    output reg[1:0] memOp_o,
    output reg[15:0] memAddr_o,
	

	output reg[3:0] writeRegAddr_o,
	output reg writeReg_o,


	output reg pc_vmem_pause,
	output reg ifid_vmem_pause
    );



	reg[15:0]		logicout;
	reg[15:0] 		shiftout;
	reg[15:0]		mathout;
	

	wire 			op1_lt_op2;
	wire 			op1_eq_op2;
	wire[15:0]		op2_i_mux;

	wire[15:0]		result_sum;


	always @(*) begin
		pc_vmem_pause = `Disable;
		ifid_vmem_pause = `Disable;
		case(memOp_i)
			`MEM_WRITE_OP, `MEM_READ_OP: begin
				pc_vmem_pause = `Enable;
				ifid_vmem_pause = `Enable;
			end
			default: begin
				
			end
		endcase
	end



	always @(*) begin

        memOp_o = memOp_i;
        memAddr_o = operand1_i;
    

        writeReg_o = writeReg_i;
        writeRegAddr_o = writeRegAddr_i;

        case (aluOp_i) 
        	`ALU_AND_OP, `ALU_OR_OP: begin
        		writeData_o = logicout;
        	end
        	`ALU_SLL_OP, `ALU_SRA_OP: begin
        		writeData_o = shiftout;
        	end
        	`ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP, `ALU_SUBU_OP, `ALU_SLTU_OP, `ALU_CMP_OP: begin
        		writeData_o = mathout;
        	end
			`ALU_LI_OP, `ALU_MFIH_OP, `ALU_MTIH_OP, `ALU_MTSP_OP, `ALU_MFPC_OP, `ALU_JALR_OP: begin
				writeData_o = operand1_i;
			end
			`ALU_LW_OP, `ALU_LWSP_OP: begin
				memAddr_o = operand1_i + operand2_i;
				writeData_o = `ZERO;
			end
			`ALU_SW_OP, `ALU_SWRS_OP, `ALU_SWSP_OP: begin
				writeData_o = operand2_i;
			end
        	default: begin
        		writeData_o = `ZERO;
        	end
        endcase
	end



	always @(*) begin
			case (aluOp_i)
				`ALU_AND_OP: begin
					logicout = operand1_i & operand2_i;
				end
				`ALU_OR_OP: begin
					logicout = operand1_i | operand2_i;
				end
				default: begin
					logicout = `ZERO;
				end
			endcase
	end


	always @(*) begin
			case (aluOp_i) 
				`ALU_SLL_OP: begin
					if (operand2_i[2:0] == 3'b000) begin
						shiftout = operand1_i << 4'd8;
					end else begin
						shiftout = operand1_i << operand2_i[2:0];
					end
				end
				`ALU_SRA_OP: begin
					if (operand2_i[2:0] == 3'b000) begin
						shiftout = (operand1_i >> 4'd8) | ({16{operand1_i[15]}}) << 4'd8;
					end else begin
						shiftout = (operand1_i >> operand2_i[2:0]) | ({16{operand1_i[15]}} << (5'd16 - {2'b00, operand2_i[2:0]}));
					end
				end
				default: begin
					shiftout = `ZERO;
				end
			endcase
	end


	assign op2_i_mux = ((aluOp_i == `ALU_SUBU_OP) ||
						 (aluOp_i == `ALU_SLTU_OP)) ?
						 (~operand2_i) + 1 : operand2_i;

	assign result_sum = operand1_i + op2_i_mux;




	assign op1_lt_op2 = (aluOp_i == `ALU_SLTU_OP) ?
						  ((operand1_i[15] && ~operand2_i[15]) || 
						  	(~operand1_i[15] && ~operand2_i[15] && result_sum[15])|| 
						  	(operand1_i[15] && operand2_i[15] && result_sum[15])) : (operand1_i < operand2_i);

	assign op1_neq_op2 = ~(operand1_i == operand2_i);



	always @(*) begin
			case (aluOp_i)
				`ALU_ADDU_OP, `ALU_ADDIU_OP, `ALU_ADDIU3_OP, `ALU_ADDSP_OP: begin
					mathout = result_sum;
				end
				`ALU_SUBU_OP: begin
					mathout = result_sum;
				end
				`ALU_SLTU_OP: begin
					mathout = op1_lt_op2;
				end
				`ALU_CMP_OP: begin
					mathout = op1_neq_op2;
				end
				default: begin
					mathout = `ZERO;
				end
			endcase
	end

endmodule