data/full_repos/permissive/138443719/04-arrays/src/main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/138443719/04-arrays/src/main.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hello_world;


  reg [3:0] in1, in2;
  wire [3:0] out1;

  assign out1 = in1 ^ in2;

  initial begin

    in1 = 'b1001;
    in2 = 'b1010;
    $display("Input values are: %b %b", in1, in2);
    #1;
    $display("Output value is: %b", out1);
    $finish;

  end

endmodule
module hello_world;



  reg [3:0] in1, in2;
  wire [3:0] out1;

  assign out1 = in1 ^ in2;

  initial begin

    in1 = 'b1001;
    in2 = 'b1010;
    $display("Input values are: %b %b", in1, in2);
    #1;
    $display("Output value is: %b", out1);
    $finish;

  end

endmodule