data/full_repos/permissive/174242803/datapath/src/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/174242803/datapath/src/alu.v:13: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance alu\n   assign sum = a + b2 + alucont[2] ;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/174242803/datapath/src/alu.v:15: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance alu\n   assign slt = sum[7] ;\n              ^\n%Error: Exiting due to 2 warning(s)\n'
module alu (result, a, b, alucont) ;

   input  [7:0] a, b ;
   input  [2:0] alucont ;
   output [7:0] result ;

   reg    [7:0] result ;
   wire   [7:0] b2, sum, slt ;

   assign b2 = alucont[2] ? ~b:b ; 
   assign sum = a + b2 + alucont[2] ;

   assign slt = sum[7] ;

   always@(a or b or alucont or sum or slt)
      case(alucont[1:0])
         2'b00: result <= a & b ;
         2'b01: result <= a | b ;
         2'b10: result <= sum ;
         2'b11: result <= slt ;
      endcase

endmodule
module alu (result, a, b, alucont) ;


   input  [7:0] a, b ;
   input  [2:0] alucont ;
   output [7:0] result ;

   reg    [7:0] result ;
   wire   [7:0] b2, sum, slt ;

   assign b2 = alucont[2] ? ~b:b ; 
   assign sum = a + b2 + alucont[2] ;

   assign slt = sum[7] ;

   always@(a or b or alucont or sum or slt)
      case(alucont[1:0])
         2'b00: result <= a & b ;
         2'b01: result <= a | b ;
         2'b10: result <= sum ;
         2'b11: result <= slt ;
      endcase

endmodule