data/full_repos/permissive/172912857/project_alu_basys3/alu_basys3.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/172912857/project_alu_basys3/alu_basys3.v:31: Signal definition not found, creating implicitly: \'zr\'\n            .zr(zr),\n                ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/172912857/project_alu_basys3/alu_basys3.v:32: Signal definition not found, creating implicitly: \'ng\'\n            .ng(ng)\n                ^~\n%Warning-LITENDIAN: data/full_repos/permissive/172912857/project_alu_basys3/alu_basys3.v:87: Little bit endian vector: MSB < LSB of bit range: 1:6\n    input [1:6] c,\n          ^\n%Error: Exiting due to 3 warning(s)\n'
module top_data_alu(
    input [15:0] data,

    input reset,
    input [2:0] load,
    output [15:0] alu_out


    );

wire [5:0] opcode;    
wire [15:0] x, y;

data my_data(
        .data(data),

        .reset(reset),
        .load(load),
        .x(x), 
        .y(y),
        .opcode(opcode)
        );
        
ALU_case ALU(
            .c(opcode),
            .x(x),
            .y(y),
            .out(alu_out),
            .zr(zr),
            .ng(ng)
            );

endmodule
module top_data_alu(
    input [15:0] data,

    input reset,
    input [2:0] load,
    output [15:0] alu_out


    );


wire [5:0] opcode;    
wire [15:0] x, y;

data my_data(
        .data(data),

        .reset(reset),
        .load(load),
        .x(x), 
        .y(y),
        .opcode(opcode)
        );
        
ALU_case ALU(
            .c(opcode),
            .x(x),
            .y(y),
            .out(alu_out),
            .zr(zr),
            .ng(ng)
            );

endmodule