data/full_repos/permissive/143278/ivltests/pr1787423.v
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1: b'%Error: data/full_repos/permissive/143278/ivltests/pr1787423.v:6: Unsupported or unknown PLI call: $monitor\n    $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1787423.v:6: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in);\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1787423.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #1 in = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1787423.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #1 in = 0;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1787423.v:13: syntax error, unexpected \',\', expecting \')\'\n  buf (bf1, bf2, in);\n               ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1787423.v:14: syntax error, unexpected \',\', expecting \')\'\n  not (nt1, nt2, in);\n               ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1787423.v:15: syntax error, unexpected \',\', expecting \')\'\n  pulldown (pd1, pd2);\n               ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1787423.v:16: syntax error, unexpected \',\', expecting \')\'\n  pullup (pu1, pu2);\n             ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg in;
  wire bf1, bf2, nt1, nt2, pd1, pd2, pu1, pu2;

  initial begin
    $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in);
    in = 0;

    #1 in = 1;
    #1 in = 0;
  end

  buf (bf1, bf2, in);
  not (nt1, nt2, in);
  pulldown (pd1, pd2);
  pullup (pu1, pu2);
endmodule
module top;

  reg in;
  wire bf1, bf2, nt1, nt2, pd1, pd2, pu1, pu2;

  initial begin
    $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in);
    in = 0;

    #1 in = 1;
    #1 in = 0;
  end

  buf (bf1, bf2, in);
  not (nt1, nt2, in);
  pulldown (pd1, pd2);
  pullup (pu1, pu2);
endmodule