data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Reciprocal/flot_Rec_Hung_tb.v
 line:50: before: "real"
1: b'%Error: Cannot find file containing module: Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Reciprocal/flot_Rec_Hung_tb.v\n%Error: Exiting due to 3 error(s)\n'
module flot_Rec_Hung_tb;









	

	parameter WIDTH = 32;
	parameter WIDTH_exp = 8;
	parameter WIDTH_mat = 23;
	parameter LUT_addWidth = 12;
	parameter LUT_bits = 24;





	reg CLK;
	reg nRST;
	reg [WIDTH-1:0] OP;
	reg CE;
	reg exce_in;


	wire [WIDTH-1:0] result;
	wire exce_out;




function real floatToReal;
	input [2047:0] in;
	input integer WE;
	input integer WM;
	integer	idx;
	integer idx2;
	real retVal;
	real exVal;
	begin
		retVal = 0;
		exVal  = 0;

		for(idx = 0; idx < WM; idx = idx + 1) begin
			if(in[idx]==1'b1) begin
				retVal = retVal + (2.0**(idx-WM));
			end
		end
		retVal = retVal + 1;

		for(idx2 = 0; idx2 < WE; idx2 = idx2 + 1) begin
			if(in[idx2+WM]==1'b1) begin
				exVal = exVal + (2.0**idx2);
			end
		end

		if (in == 0)
			floatToReal = 0;
		else if (in[WE+WM]==1'b1) 
			floatToReal = -retVal*(2.0**(exVal-((2.0**(WE-1))-1)));
		else 
			floatToReal = retVal*(2.0**(exVal-((2.0**(WE-1))-1)));
	end
endfunction




	parameter ClockPeriod = 10;
	initial 	 CLK = 1;
	always # (ClockPeriod/2) CLK = ~CLK;





	flot_Rec_Hung
	  #(
		.WIDTH(WIDTH),	
		.WIDTH_exp(WIDTH_exp),
		.WIDTH_mat(WIDTH_mat),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth)
		)
	Fang_flo_Rec_Hung 
		(
		.CLK(CLK), 
		.nRST(nRST), 
		.OP(OP), 
		.CE(CE),
		.exce_in(exce_in),
		.result(result),
		.exce_out(exce_out)
		);


	flot_Rec_pipe
	  #(
		.WIDTH(WIDTH),	
		.WIDTH_exp(WIDTH_exp),
		.WIDTH_mat(WIDTH_mat),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth)
		)
	Fang_flo_Rec_pipe
		(
		.CLK(CLK), 
		.nRST(nRST), 
		.OP(OP), 
		.CE(CE),
		.exce_in(exce_in),
		.result(result),
		.exce_out(exce_out)
		);

	initial begin
		

		$readmemb("LUT_rec_Hung_24bit.txt", flot_Rec_Hung_tb.Fang_flo_Rec_Hung.Fang_Reciprocal_Hung.LUT); 






		

		CLK = 0;
		nRST = 0;
		OP = 0; @(posedge CLK);
		nRST = 1; CE = 1; exce_in = 0;







		

		OP = 32'b0_01111111_11000000000000000000000; @(posedge CLK);
		OP = 32'b0_01111110_11000000000000000000000; @(posedge CLK);
		OP = 32'b0_01111110_11100000000000000000000; @(posedge CLK);
		OP = 32'b0_10000011_11000000000000000000000; @(posedge CLK);
		OP = 32'b0_10000011_11001110000000000000000; @(posedge CLK);
		OP = 32'b0_10001011_11000011100001111000000; @(posedge CLK);
		OP = 32'b0_10000111_11000000000000000000000; @(posedge CLK);
		OP = 32'b1_10000111_11000000000000000000000; @(posedge CLK);
		OP = 32'b1_10001111_11000011111110000000000; @(posedge CLK);
		OP = 32'b1_01110000_11000011111110000000000; @(posedge CLK);
		OP = 32'b0_00111001_11000011111110000000000; @(posedge CLK);

		
		@(posedge CLK); $finish;

	end





	real real_OP;
	real real_result; 




	always @ OP real_OP = floatToReal(OP, WIDTH_exp, WIDTH_mat);  
	always @ result real_result = floatToReal(result, WIDTH_exp, WIDTH_mat);      

		
endmodule
module flot_Rec_Hung_tb;










	

	parameter WIDTH = 32;
	parameter WIDTH_exp = 8;
	parameter WIDTH_mat = 23;
	parameter LUT_addWidth = 12;
	parameter LUT_bits = 24;





	reg CLK;
	reg nRST;
	reg [WIDTH-1:0] OP;
	reg CE;
	reg exce_in;


	wire [WIDTH-1:0] result;
	wire exce_out;




function real floatToReal;
	input [2047:0] in;
	input integer WE;
	input integer WM;
	integer	idx;
	integer idx2;
	real retVal;
	real exVal;
	begin
		retVal = 0;
		exVal  = 0;

		for(idx = 0; idx < WM; idx = idx + 1) begin
			if(in[idx]==1'b1) begin
				retVal = retVal + (2.0**(idx-WM));
			end
		end
		retVal = retVal + 1;

		for(idx2 = 0; idx2 < WE; idx2 = idx2 + 1) begin
			if(in[idx2+WM]==1'b1) begin
				exVal = exVal + (2.0**idx2);
			end
		end

		if (in == 0)
			floatToReal = 0;
		else if (in[WE+WM]==1'b1) 
			floatToReal = -retVal*(2.0**(exVal-((2.0**(WE-1))-1)));
		else 
			floatToReal = retVal*(2.0**(exVal-((2.0**(WE-1))-1)));
	end
endfunction




	parameter ClockPeriod = 10;
	initial 	 CLK = 1;
	always # (ClockPeriod/2) CLK = ~CLK;





	flot_Rec_Hung
	  #(
		.WIDTH(WIDTH),	
		.WIDTH_exp(WIDTH_exp),
		.WIDTH_mat(WIDTH_mat),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth)
		)
	Fang_flo_Rec_Hung 
		(
		.CLK(CLK), 
		.nRST(nRST), 
		.OP(OP), 
		.CE(CE),
		.exce_in(exce_in),
		.result(result),
		.exce_out(exce_out)
		);


	flot_Rec_pipe
	  #(
		.WIDTH(WIDTH),	
		.WIDTH_exp(WIDTH_exp),
		.WIDTH_mat(WIDTH_mat),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth)
		)
	Fang_flo_Rec_pipe
		(
		.CLK(CLK), 
		.nRST(nRST), 
		.OP(OP), 
		.CE(CE),
		.exce_in(exce_in),
		.result(result),
		.exce_out(exce_out)
		);

	initial begin
		

		$readmemb("LUT_rec_Hung_24bit.txt", flot_Rec_Hung_tb.Fang_flo_Rec_Hung.Fang_Reciprocal_Hung.LUT); 






		

		CLK = 0;
		nRST = 0;
		OP = 0; @(posedge CLK);
		nRST = 1; CE = 1; exce_in = 0;







		

		OP = 32'b0_01111111_11000000000000000000000; @(posedge CLK);
		OP = 32'b0_01111110_11000000000000000000000; @(posedge CLK);
		OP = 32'b0_01111110_11100000000000000000000; @(posedge CLK);
		OP = 32'b0_10000011_11000000000000000000000; @(posedge CLK);
		OP = 32'b0_10000011_11001110000000000000000; @(posedge CLK);
		OP = 32'b0_10001011_11000011100001111000000; @(posedge CLK);
		OP = 32'b0_10000111_11000000000000000000000; @(posedge CLK);
		OP = 32'b1_10000111_11000000000000000000000; @(posedge CLK);
		OP = 32'b1_10001111_11000011111110000000000; @(posedge CLK);
		OP = 32'b1_01110000_11000011111110000000000; @(posedge CLK);
		OP = 32'b0_00111001_11000011111110000000000; @(posedge CLK);

		
		@(posedge CLK); $finish;

	end





	real real_OP;
	real real_result; 




	always @ OP real_OP = floatToReal(OP, WIDTH_exp, WIDTH_mat);  
	always @ result real_result = floatToReal(result, WIDTH_exp, WIDTH_mat);      

		
endmodule