data/full_repos/permissive/20951436/Code/fpga code/PWM_8bit.v
1: b'%Error: Cannot find file containing module: code,data/full_repos/permissive/20951436\n        ... Looked in:\n             data/full_repos/permissive/20951436/Code/fpga/code,data/full_repos/permissive/20951436\n             data/full_repos/permissive/20951436/Code/fpga/code,data/full_repos/permissive/20951436.v\n             data/full_repos/permissive/20951436/Code/fpga/code,data/full_repos/permissive/20951436.sv\n             code,data/full_repos/permissive/20951436\n             code,data/full_repos/permissive/20951436.v\n             code,data/full_repos/permissive/20951436.sv\n             obj_dir/code,data/full_repos/permissive/20951436\n             obj_dir/code,data/full_repos/permissive/20951436.v\n             obj_dir/code,data/full_repos/permissive/20951436.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/20951436/Code/fpga\n%Error: Cannot find file containing module: code/PWM_8bit.v\n%Error: Exiting due to 3 error(s)\n'
module PWM_timer(input clk, input [8:0] speed, input en, output out, output dirp, dirn);

	reg [8:0] speed_copy; initial speed_copy<=0;

	reg outlogic; initial outlogic<=0;
	assign out = (en ? outlogic : 0);
	
	reg [7:0] count; initial count<=0;

	always @(negedge count[7]) speed_copy <= (speed[8] ? ~speed[7:0]+1 : speed[7:0]);

	always @(negedge clk) begin
		count<=count+1;
		if (count==0 && speed_copy[7:0]!=0) begin
			outlogic<=1;
		end else if (count==speed_copy[7:0]) begin
			outlogic<=0;
		end
	end
	
	assign dirp = (~speed_copy[8]);
	assign dirn = (speed_copy[8]);

endmodule
module PWM_timer(input clk, input [8:0] speed, input en, output out, output dirp, dirn);


	reg [8:0] speed_copy; initial speed_copy<=0;

	reg outlogic; initial outlogic<=0;
	assign out = (en ? outlogic : 0);
	
	reg [7:0] count; initial count<=0;

	always @(negedge count[7]) speed_copy <= (speed[8] ? ~speed[7:0]+1 : speed[7:0]);

	always @(negedge clk) begin
		count<=count+1;
		if (count==0 && speed_copy[7:0]!=0) begin
			outlogic<=1;
		end else if (count==speed_copy[7:0]) begin
			outlogic<=0;
		end
	end
	
	assign dirp = (~speed_copy[8]);
	assign dirn = (speed_copy[8]);

endmodule