data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #50 clk = ~ clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new/gated_T_tb.v:31: Cannot find file containing module: \'gated_T\'\n    gated_T T_latch(T,clk,restn,enable,Q);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new,data/full_repos/permissive/165901145/gated_T\n             data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new,data/full_repos/permissive/165901145/gated_T.v\n             data/full_repos/permissive/165901145/seq_detector.srcs/sim_1/new,data/full_repos/permissive/165901145/gated_T.sv\n             gated_T\n             gated_T.v\n             gated_T.sv\n             obj_dir/gated_T\n             obj_dir/gated_T.v\n             obj_dir/gated_T.sv\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gated_T_tb(

    );
    reg T;
    reg clk;
    reg restn;
    reg enable;
    wire Q;
    gated_T T_latch(T,clk,restn,enable,Q);
    
    always
    begin
    clk =0;
    #10
    clk=1;
    forever 
    #50 clk = ~ clk;
    end
    
    initial begin
      T=0;
      restn = 1;
      enable =0; 
      #10
      restn =0;
      T =1;
      #10
      enable = 1;
      restn = 1;
      T=1;
      #10
      enable = 1;
      #100
      
      T=0;
      #100
      T=1;
      #100
      T=0;
      #100
      T=1;
      #100
      T=0;
      #100
      T=1;
      #100
      T=0;
      #100
      T=1;
      #100
      T=0;
      #100
      T=1;
      #100
      T=0;
    end
endmodule
module gated_T_tb(

    );

    reg T;
    reg clk;
    reg restn;
    reg enable;
    wire Q;
    gated_T T_latch(T,clk,restn,enable,Q);
    
    always
    begin
    clk =0;
    #10
    clk=1;
    forever 
    #50 clk = ~ clk;
    end
    
    initial begin
      T=0;
      restn = 1;
      enable =0; 
      #10
      restn =0;
      T =1;
      #10
      enable = 1;
      restn = 1;
      T=1;
      #10
      enable = 1;
      #100
      
      T=0;
      #100
      T=1;
      #100
      T=0;
      #100
      T=1;
      #100
      T=0;
      #100
      T=1;
      #100
      T=0;
      #100
      T=1;
      #100
      T=0;
      #100
      T=1;
      #100
      T=0;
    end
endmodule