data/full_repos/permissive/174369527/verilator_test/03-Blink/blink.v
data/verilator_xmls/bb0062e2-774c-4622-9932-9a2489f846fd.xml
module blink(i_clk, o_led);
	input wire i_clk;
	output wire o_led;

	parameter WIDTH = 27;
	reg [WIDTH-1:0] r_counter = 0;

	always @(posedge i_clk)
		r_counter <= r_counter + 1'b1;

	assign o_led = r_counter[WIDTH-1];
endmodule
module blink(i_clk, o_led);

	input wire i_clk;
	output wire o_led;

	parameter WIDTH = 27;
	reg [WIDTH-1:0] r_counter = 0;

	always @(posedge i_clk)
		r_counter <= r_counter + 1'b1;

	assign o_led = r_counter[WIDTH-1];
endmodule