data/full_repos/permissive/146618947/generate_tarea7/word_operation_cond.v
data/verilator_xmls/a850c1bd-a6bb-4454-95af-62175f5bc14b.xml
module word_operation_cond #(
                              parameter BUS_SIZE = 32,
                              parameter WORD_SIZE = 4,
                              parameter WORD_NUM = BUS_SIZE / WORD_SIZE
                              )
   (input clk,
    input                      reset,
    input [WORD_SIZE-1:0]      word_in,
    output reg [WORD_SIZE-1:0] word_out,
    output reg                 word_control_out);

   always @ (posedge clk) begin
      if (reset) begin
         word_control_out <= | word_in;
         word_out <= word_in;
      end else begin
         word_control_out <= 0;
         word_out <= 0;
      end
   end

endmodule
module word_operation_cond #(
                              parameter BUS_SIZE = 32,
                              parameter WORD_SIZE = 4,
                              parameter WORD_NUM = BUS_SIZE / WORD_SIZE
                              )
   (input clk,
    input                      reset,
    input [WORD_SIZE-1:0]      word_in,
    output reg [WORD_SIZE-1:0] word_out,
    output reg                 word_control_out);


   always @ (posedge clk) begin
      if (reset) begin
         word_control_out <= | word_in;
         word_out <= word_in;
      end else begin
         word_control_out <= 0;
         word_out <= 0;
      end
   end

endmodule