data/full_repos/permissive/114459345/srcCache/id.v
1: b'%Error: data/full_repos/permissive/114459345/srcCache/id.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:9: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] pc_i,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] pc_i,\n                        ^\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:10: Define or directive not defined: \'`InstBus\'\n input wire[`InstBus] inst_i,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] reg1_data_i,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg1_data_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] reg2_data_i,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:16: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg2_data_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:20: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg reg2_read_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:21: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] reg1_addr_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:21: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] reg1_addr_o,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:22: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] reg2_addr_o,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:25: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus] pc_o,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:26: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus] aluop_o,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:27: Define or directive not defined: \'`AluFunct3Bus\'\n output reg[`AluFunct3Bus] alufunct3_o,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:28: Define or directive not defined: \'`AluFunct7Bus\'\n output reg[`AluFunct7Bus] alufunct7_o,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:29: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] reg1_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:30: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] reg2_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:31: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] imm_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] wd_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:33: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_o,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:39: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg jump_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`InstAddrBus] jpc_o\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:40: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus] jpc_o\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:47: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] imm;\n     ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] imm;\n            ^\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:53: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:54: Define or directive not defined: \'`IType\'\n   inst_type <= `IType;   \n                ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:57: Define or directive not defined: \'`IType\'\n   inst_type <= `IType;\n                ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:59: Define or directive not defined: \'`LUI\'\n    `LUI : inst_type <= `UType;\n    ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:59: Define or directive not defined: \'`UType\'\n    `LUI : inst_type <= `UType;\n                        ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:60: Define or directive not defined: \'`AUIPC\'\n    `AUIPC : inst_type <= `UType;\n    ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:60: Define or directive not defined: \'`UType\'\n    `AUIPC : inst_type <= `UType;\n                          ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:61: Define or directive not defined: \'`JAL\'\n    `JAL : inst_type <= `JType;\n    ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:61: Define or directive not defined: \'`JType\'\n    `JAL : inst_type <= `JType;\n                        ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:62: Define or directive not defined: \'`JALR\'\n    `JALR : inst_type <= `IType;\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:62: Define or directive not defined: \'`IType\'\n    `JALR : inst_type <= `IType;\n                         ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:63: Define or directive not defined: \'`BRANCH\'\n    `BRANCH : inst_type <= `BType;\n    ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:63: Define or directive not defined: \'`BType\'\n    `BRANCH : inst_type <= `BType;\n                           ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:64: Define or directive not defined: \'`LOAD\'\n    `LOAD : inst_type <= `IType;\n    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:64: Define or directive not defined: \'`IType\'\n    `LOAD : inst_type <= `IType;\n                         ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:65: Define or directive not defined: \'`STORE\'\n    `STORE : inst_type <= `SType;\n    ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:65: Define or directive not defined: \'`SType\'\n    `STORE : inst_type <= `SType;\n                          ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:66: Define or directive not defined: \'`EXE_IMM\'\n    `EXE_IMM : inst_type <= `IType;\n    ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:66: Define or directive not defined: \'`IType\'\n    `EXE_IMM : inst_type <= `IType;\n                            ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:67: Define or directive not defined: \'`EXE\'\n    `EXE : inst_type <= `RType;\n    ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:67: Define or directive not defined: \'`RType\'\n    `EXE : inst_type <= `RType;\n                        ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:76: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:77: Define or directive not defined: \'`NopInst\'\n   pc_o <= `NopInst;\n           ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:78: Define or directive not defined: \'`NOP\'\n   aluop_o <= `NOP;\n              ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module id(

	input wire rst,


	input wire[`InstAddrBus] pc_i,
	input wire[`InstBus] inst_i,
	

	input wire reg1_suc,
	input wire[`RegBus] reg1_data_i,
	input wire reg2_suc,
	input wire[`RegBus] reg2_data_i,
	

	output reg reg1_read_o,
	output reg reg2_read_o,
	output reg[`RegAddrBus] reg1_addr_o,
	output reg[`RegAddrBus] reg2_addr_o,
	

	output reg[`InstAddrBus] pc_o,
	output reg[`AluOpBus] aluop_o,
	output reg[`AluFunct3Bus] alufunct3_o,
	output reg[`AluFunct7Bus] alufunct7_o,
	output reg[`RegBus] reg1_o,
	output reg[`RegBus] reg2_o,
	output reg[`RegBus] imm_o,
	output reg wreg_o,
	output reg[`RegAddrBus] wd_o,
	

	output reg stall_req,
	

	output reg jump_o,
	output reg[`InstAddrBus] jpc_o

);
	
	wire[6:0] op = inst_i[6:0];
	
	reg[2:0] inst_type;
	reg[`RegBus] imm;
	

	

	always @ (*) begin
		if(rst == `RstEnable) begin
			inst_type <= `IType;
		end
		else begin
			inst_type <= `IType;
			case(op)
				`LUI : inst_type <= `UType;
				`AUIPC : inst_type <= `UType;
				`JAL : inst_type <= `JType;
				`JALR : inst_type <= `IType;
				`BRANCH : inst_type <= `BType;
				`LOAD : inst_type <= `IType;
				`STORE : inst_type <= `SType;
				`EXE_IMM : inst_type <= `IType;
				`EXE : inst_type <= `RType;


			endcase
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			pc_o <= `NopInst;
			aluop_o <= `NOP;
			alufunct3_o <= `NOP_FUNCT3;
			alufunct7_o <= `NOP_FUNCT7;
			imm <= `ZeroWord;
			wreg_o <= `WriteDisable;
			wd_o <= `NopRegAddr;

		end
		else begin
			pc_o <= pc_i;

			aluop_o <= op;
			alufunct3_o <= `NOP_FUNCT3;			
			alufunct7_o <= `NOP_FUNCT7;
			imm <= `ZeroWord;
			wreg_o <= `WriteDisable;			
			wd_o <= `NopRegAddr;

		
			case(inst_type)
				`RType : begin
					wreg_o <= `WriteEnable;
					alufunct3_o <= inst_i[14:12];
					alufunct7_o <= inst_i[31:25];
					wd_o <= inst_i[11:7];	

				end
				`IType : begin
					imm <= {{21{inst_i[31]}}, inst_i[30:20]};
					wreg_o <= `WriteEnable;
					alufunct3_o <= inst_i[14:12];
					alufunct7_o <= inst_i[31:25];
					wd_o <= inst_i[11:7];	

				end
				`SType : begin
					imm <= {{21{inst_i[31]}}, inst_i[30:25], inst_i[11:8], inst_i[7]};
					wreg_o <= `WriteDisable;
					alufunct3_o <= inst_i[14:12];

				end
				`BType : begin
					imm <= {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
					wreg_o <= `WriteDisable;
					alufunct3_o <= inst_i[14:12];

				end
				`UType : begin
					imm <= {inst_i[31:12], {12{1'b0}}};
					wreg_o <= `WriteEnable;
					wd_o <= inst_i[11:7];	

				end
				`JType : begin
					imm <= {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:25], inst_i[24:21], 1'b0};
					wreg_o <= `WriteEnable;
					wd_o <= inst_i[11:7];	

				end
				default : begin

				end
			endcase
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			reg1_read_o <= `ReadDisable;
			reg2_read_o <= `ReadDisable;
			reg1_addr_o <= `NopRegAddr;
			reg2_addr_o <= `NopRegAddr;		
		end
		else begin
			reg1_read_o <= `ReadDisable;
			reg2_read_o <= `ReadDisable;
			reg1_addr_o <= `NopRegAddr;
			reg2_addr_o <= `NopRegAddr;
			
			case(inst_type)
				`RType : begin
					reg1_read_o <= `ReadEnable;
					reg2_read_o <= `ReadEnable;
					reg1_addr_o <= inst_i[19:15];
					reg2_addr_o <= inst_i[24:20];
				end
				`IType : begin
					reg1_read_o <= `ReadEnable;
					reg2_read_o <= `ReadDisable;
					reg1_addr_o <= inst_i[19:15];
				end
				`SType : begin
					reg1_read_o <= `ReadEnable;
					reg2_read_o <= `ReadEnable;
					reg1_addr_o <= inst_i[19:15];
					reg2_addr_o <= inst_i[24:20];
				end
				`BType : begin
					reg1_read_o <= `ReadEnable;
					reg2_read_o <= `ReadEnable;
					reg1_addr_o <= inst_i[19:15];
					reg2_addr_o <= inst_i[24:20];
				end
				`UType : begin
					reg1_read_o <= `ReadDisable;
					reg2_read_o <= `ReadDisable;
				end
				`JType : begin
					reg1_read_o <= `ReadDisable;
					reg2_read_o <= `ReadDisable;
				end
			endcase
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			reg1_o <= `ZeroWord;
		end
		else if(reg1_read_o == `ReadEnable) begin
			reg1_o <= reg1_data_i;
		end
		else if(reg1_read_o == `ReadDisable) begin
			reg1_o <= imm;
		end
		else begin
			reg1_o <= `ZeroWord;
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			reg2_o <= `ZeroWord;
		end
		else if(reg2_read_o == `ReadEnable) begin
			reg2_o <= reg2_data_i;
		end
		else if(reg2_read_o == `ReadDisable) begin
			reg2_o <= imm;
		end
		else begin
			reg2_o <= `ZeroWord;
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			imm_o <= `ZeroWord;
		end
		else begin
			imm_o <= imm;
		end
	end
	
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			stall_req <= `Continue;
		end
		else begin
			stall_req <= `Continue;
			case(inst_type)
				`RType : stall_req <= !(reg1_suc & reg2_suc);
				`IType : stall_req <= !reg1_suc;
				`SType : stall_req <= !(reg1_suc & reg2_suc);
				`BType : stall_req <= !(reg1_suc & reg2_suc);
				`UType : stall_req <= `Continue;
				`JType : stall_req <= `Continue;
			endcase
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			jump_o <= `Stay;
			jpc_o <= `NopInst;		
		end
		else begin
			jump_o <= `Stay;			
			jpc_o <= `NopInst;		

			
			case (op)




				`JAL : begin
					jump_o <= `Jump;
					jpc_o <= reg1_o + pc_i;
				end
				`JALR : begin
					jump_o <= `Jump;
					jpc_o <= {reg1_o[31:1] + reg2_o[31:1] + {{30{1'b0}}, reg1_o[0] & reg2_o[0]}, 1'b0};
				end
				`BRANCH : begin
					case(alufunct3_o)
						`BEQ : begin
							if(reg1_o == reg2_o) begin
								jump_o <= `Jump;
								jpc_o <= imm_o + pc_i;
							end
							else begin
								jpc_o <= pc_i + 4;
							end
						end
						`BNE : begin
							if(reg1_o != reg2_o) begin
								jump_o <= `Jump;
								jpc_o <= imm_o + pc_i;
							end
						end
						`BLT : begin
							if($signed(reg1_o) < $signed(reg2_o)) begin
								jump_o <= `Jump;
								jpc_o <= imm_o + pc_i;
							end
							else begin
								jpc_o <= pc_i + 4;
							end
						end
						`BGE : begin
							if($signed(reg1_o) >= $signed(reg2_o)) begin
								jump_o <= `Jump;
								jpc_o <= imm_o + pc_i;
							end	
							else begin
								jpc_o <= pc_i + 4;
							end							
						end
						`BLTU : begin
							if(reg1_o < reg2_o) begin
								jump_o <= `Jump;
								jpc_o <= imm_o + pc_i;
							end		
							else begin
								jpc_o <= pc_i + 4;
							end							
						end
						`BGEU : begin
							if(reg1_o >= reg2_o) begin
								jump_o <= `Jump;
								jpc_o <= imm_o + pc_i;
							end		
							else begin
								jpc_o <= pc_i + 4;
							end							
						end
					endcase
				end	
			endcase
		end
	end

endmodule
module id(

	input wire rst,


	input wire[`InstAddrBus] pc_i,
	input wire[`InstBus] inst_i,
	

	input wire reg1_suc,
	input wire[`RegBus] reg1_data_i,
	input wire reg2_suc,
	input wire[`RegBus] reg2_data_i,
	

	output reg reg1_read_o,
	output reg reg2_read_o,
	output reg[`RegAddrBus] reg1_addr_o,
	output reg[`RegAddrBus] reg2_addr_o,
	

	output reg[`InstAddrBus] pc_o,
	output reg[`AluOpBus] aluop_o,
	output reg[`AluFunct3Bus] alufunct3_o,
	output reg[`AluFunct7Bus] alufunct7_o,
	output reg[`RegBus] reg1_o,
	output reg[`RegBus] reg2_o,
	output reg[`RegBus] imm_o,
	output reg wreg_o,
	output reg[`RegAddrBus] wd_o,
	

	output reg stall_req,
	

	output reg jump_o,
	output reg[`InstAddrBus] jpc_o

);

	
	wire[6:0] op = inst_i[6:0];
	
	reg[2:0] inst_type;
	reg[`RegBus] imm;
	

	

	always @ (*) begin
		if(rst == `RstEnable) begin
			inst_type <= `IType;
		end
		else begin
			inst_type <= `IType;
			case(op)
				`LUI : inst_type <= `UType;
				`AUIPC : inst_type <= `UType;
				`JAL : inst_type <= `JType;
				`JALR : inst_type <= `IType;
				`BRANCH : inst_type <= `BType;
				`LOAD : inst_type <= `IType;
				`STORE : inst_type <= `SType;
				`EXE_IMM : inst_type <= `IType;
				`EXE : inst_type <= `RType;


			endcase
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			pc_o <= `NopInst;
			aluop_o <= `NOP;
			alufunct3_o <= `NOP_FUNCT3;
			alufunct7_o <= `NOP_FUNCT7;
			imm <= `ZeroWord;
			wreg_o <= `WriteDisable;
			wd_o <= `NopRegAddr;

		end
		else begin
			pc_o <= pc_i;

			aluop_o <= op;
			alufunct3_o <= `NOP_FUNCT3;			
			alufunct7_o <= `NOP_FUNCT7;
			imm <= `ZeroWord;
			wreg_o <= `WriteDisable;			
			wd_o <= `NopRegAddr;

		
			case(inst_type)
				`RType : begin
					wreg_o <= `WriteEnable;
					alufunct3_o <= inst_i[14:12];
					alufunct7_o <= inst_i[31:25];
					wd_o <= inst_i[11:7];	

				end
				`IType : begin
					imm <= {{21{inst_i[31]}}, inst_i[30:20]};
					wreg_o <= `WriteEnable;
					alufunct3_o <= inst_i[14:12];
					alufunct7_o <= inst_i[31:25];
					wd_o <= inst_i[11:7];	

				end
				`SType : begin
					imm <= {{21{inst_i[31]}}, inst_i[30:25], inst_i[11:8], inst_i[7]};
					wreg_o <= `WriteDisable;
					alufunct3_o <= inst_i[14:12];

				end
				`BType : begin
					imm <= {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
					wreg_o <= `WriteDisable;
					alufunct3_o <= inst_i[14:12];

				end
				`UType : begin
					imm <= {inst_i[31:12], {12{1'b0}}};
					wreg_o <= `WriteEnable;
					wd_o <= inst_i[11:7];	

				end
				`JType : begin
					imm <= {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:25], inst_i[24:21], 1'b0};
					wreg_o <= `WriteEnable;
					wd_o <= inst_i[11:7];	

				end
				default : begin

				end
			endcase
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			reg1_read_o <= `ReadDisable;
			reg2_read_o <= `ReadDisable;
			reg1_addr_o <= `NopRegAddr;
			reg2_addr_o <= `NopRegAddr;		
		end
		else begin
			reg1_read_o <= `ReadDisable;
			reg2_read_o <= `ReadDisable;
			reg1_addr_o <= `NopRegAddr;
			reg2_addr_o <= `NopRegAddr;
			
			case(inst_type)
				`RType : begin
					reg1_read_o <= `ReadEnable;
					reg2_read_o <= `ReadEnable;
					reg1_addr_o <= inst_i[19:15];
					reg2_addr_o <= inst_i[24:20];
				end
				`IType : begin
					reg1_read_o <= `ReadEnable;
					reg2_read_o <= `ReadDisable;
					reg1_addr_o <= inst_i[19:15];
				end
				`SType : begin
					reg1_read_o <= `ReadEnable;
					reg2_read_o <= `ReadEnable;
					reg1_addr_o <= inst_i[19:15];
					reg2_addr_o <= inst_i[24:20];
				end
				`BType : begin
					reg1_read_o <= `ReadEnable;
					reg2_read_o <= `ReadEnable;
					reg1_addr_o <= inst_i[19:15];
					reg2_addr_o <= inst_i[24:20];
				end
				`UType : begin
					reg1_read_o <= `ReadDisable;
					reg2_read_o <= `ReadDisable;
				end
				`JType : begin
					reg1_read_o <= `ReadDisable;
					reg2_read_o <= `ReadDisable;
				end
			endcase
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			reg1_o <= `ZeroWord;
		end
		else if(reg1_read_o == `ReadEnable) begin
			reg1_o <= reg1_data_i;
		end
		else if(reg1_read_o == `ReadDisable) begin
			reg1_o <= imm;
		end
		else begin
			reg1_o <= `ZeroWord;
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			reg2_o <= `ZeroWord;
		end
		else if(reg2_read_o == `ReadEnable) begin
			reg2_o <= reg2_data_i;
		end
		else if(reg2_read_o == `ReadDisable) begin
			reg2_o <= imm;
		end
		else begin
			reg2_o <= `ZeroWord;
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			imm_o <= `ZeroWord;
		end
		else begin
			imm_o <= imm;
		end
	end
	
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			stall_req <= `Continue;
		end
		else begin
			stall_req <= `Continue;
			case(inst_type)
				`RType : stall_req <= !(reg1_suc & reg2_suc);
				`IType : stall_req <= !reg1_suc;
				`SType : stall_req <= !(reg1_suc & reg2_suc);
				`BType : stall_req <= !(reg1_suc & reg2_suc);
				`UType : stall_req <= `Continue;
				`JType : stall_req <= `Continue;
			endcase
		end
	end
	

	always @ (*) begin
		if(rst == `RstEnable) begin
			jump_o <= `Stay;
			jpc_o <= `NopInst;		
		end
		else begin
			jump_o <= `Stay;			
			jpc_o <= `NopInst;		

			
			case (op)




				`JAL : begin
					jump_o <= `Jump;
					jpc_o <= reg1_o + pc_i;
				end
				`JALR : begin
					jump_o <= `Jump;
					jpc_o <= {reg1_o[31:1] + reg2_o[31:1] + {{30{1'b0}}, reg1_o[0] & reg2_o[0]}, 1'b0};
				end
				`BRANCH : begin
					case(alufunct3_o)
						`BEQ : begin
							if(reg1_o == reg2_o) begin
								jump_o <= `Jump;
								jpc_o <= imm_o + pc_i;
							end
							else begin
								jpc_o <= pc_i + 4;
							end
						end
						`BNE : begin
							if(reg1_o != reg2_o) begin
								jump_o <= `Jump;
								jpc_o <= imm_o + pc_i;
							end
						end
						`BLT : begin
							if($signed(reg1_o) < $signed(reg2_o)) begin
								jump_o <= `Jump;
								jpc_o <= imm_o + pc_i;
							end
							else begin
								jpc_o <= pc_i + 4;
							end
						end
						`BGE : begin
							if($signed(reg1_o) >= $signed(reg2_o)) begin
								jump_o <= `Jump;
								jpc_o <= imm_o + pc_i;
							end	
							else begin
								jpc_o <= pc_i + 4;
							end							
						end
						`BLTU : begin
							if(reg1_o < reg2_o) begin
								jump_o <= `Jump;
								jpc_o <= imm_o + pc_i;
							end		
							else begin
								jpc_o <= pc_i + 4;
							end							
						end
						`BGEU : begin
							if(reg1_o >= reg2_o) begin
								jump_o <= `Jump;
								jpc_o <= imm_o + pc_i;
							end		
							else begin
								jpc_o <= pc_i + 4;
							end							
						end
					endcase
				end	
			endcase
		end
	end

endmodule