data/full_repos/permissive/106330868/verilog/speech256_top/speech256_top.v
1: b"%Error: data/full_repos/permissive/106330868/verilog/speech256_top/speech256_top.v:65: Cannot find file containing module: 'SOURCE'\n    SOURCE u_source (\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106330868/verilog/speech256_top,data/full_repos/permissive/106330868/SOURCE\n             data/full_repos/permissive/106330868/verilog/speech256_top,data/full_repos/permissive/106330868/SOURCE.v\n             data/full_repos/permissive/106330868/verilog/speech256_top,data/full_repos/permissive/106330868/SOURCE.sv\n             SOURCE\n             SOURCE.v\n             SOURCE.sv\n             obj_dir/SOURCE\n             obj_dir/SOURCE.v\n             obj_dir/SOURCE.sv\n%Error: data/full_repos/permissive/106330868/verilog/speech256_top/speech256_top.v:77: Cannot find file containing module: 'FILTER'\n    FILTER u_filter (\n    ^~~~~~\n%Error: data/full_repos/permissive/106330868/verilog/speech256_top/speech256_top.v:101: Cannot find file containing module: 'PWMDAC'\n    PWMDAC u_pwmdac (\n    ^~~~~~\n%Error: data/full_repos/permissive/106330868/verilog/speech256_top/speech256_top.v:110: Cannot find file containing module: 'CONTROLLER'\n    CONTROLLER u_controller (\n    ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module SPEECH256_TOP (
        clk,
        rst_an,     
        ldq,
        data_in,
        data_stb,
        pwm_out,
        sample_out,
        sample_stb
    );


	input clk;


    input rst_an;


	output pwm_out;
    output ldq;
    output signed [15:0] sample_out;
    output sample_stb;


    input [5:0] data_in;
    input       data_stb;



    wire pwmdac_ack, src_strobe;    
    wire signed [15:0] sig_source;
    wire signed [15:0] sig_filter;
    wire period_done;
    wire clear_states;

    wire [7:0]  period;
    wire [7:0]  dur;
    wire [15:0] amp;
    
    wire signed  [9:0]  coef_bus;
    wire                coef_load;
    
    wire done;

    SOURCE u_source (
        .clk        (clk),
        .rst_an     (rst_an),


        .period     (period[7:0]),
        .amplitude  (amp[14:0]),
        .strobe     (src_strobe),
        .period_done (period_done),
        .source_out  (sig_source)
    );

    FILTER u_filter (
        .clk        (clk),
        .rst_an     (rst_an),
        .coef_in    (coef_bus),
        .coef_load  (coef_load),
        .clear_states (clear_states),
        .sig_in     (sig_source),
        .sig_out    (sig_filter),
        .start      (pwmdac_ack),
        .done       (src_strobe)
    );




    `ifdef USE_SDDAC
    SD2DAC u_sd2dac (
        .clk        (clk),
        .rst_an     (rst_an),
        .din        ($signed({sig_filter[11:0],4'h0})),
        .din_ack    (pwmdac_ack),
        .dacout     (pwm_out)
    );
    `else
    PWMDAC u_pwmdac (
        .clk        (clk),
        .rst_an     (rst_an),
        .din        (sig_filter[10:3]),
        .din_ack    (pwmdac_ack),
        .dacout     (pwm_out)
    );    
    `endif

    CONTROLLER u_controller (
        .clk        (clk),
        .rst_an     (rst_an),
        .ldq        (ldq),
        .data_in    (data_in),
        .data_stb   (data_stb),
        .period_out (period),
        .amp_out    (amp),
        .coeff_out  (coef_bus),
        .coeff_stb  (coef_load),
        .clear_states (clear_states),
        .period_done_in (period_done)
    );

    assign sample_out = sig_filter[15:0];
    assign sample_stb = src_strobe;

    always @(posedge clk, negedge rst_an)
    begin
        if (rst_an == 0)
        begin

        end
        else
        begin

        end
    end

endmodule
module SPEECH256_TOP (
        clk,
        rst_an,     
        ldq,
        data_in,
        data_stb,
        pwm_out,
        sample_out,
        sample_stb
    );



	input clk;


    input rst_an;


	output pwm_out;
    output ldq;
    output signed [15:0] sample_out;
    output sample_stb;


    input [5:0] data_in;
    input       data_stb;



    wire pwmdac_ack, src_strobe;    
    wire signed [15:0] sig_source;
    wire signed [15:0] sig_filter;
    wire period_done;
    wire clear_states;

    wire [7:0]  period;
    wire [7:0]  dur;
    wire [15:0] amp;
    
    wire signed  [9:0]  coef_bus;
    wire                coef_load;
    
    wire done;

    SOURCE u_source (
        .clk        (clk),
        .rst_an     (rst_an),


        .period     (period[7:0]),
        .amplitude  (amp[14:0]),
        .strobe     (src_strobe),
        .period_done (period_done),
        .source_out  (sig_source)
    );

    FILTER u_filter (
        .clk        (clk),
        .rst_an     (rst_an),
        .coef_in    (coef_bus),
        .coef_load  (coef_load),
        .clear_states (clear_states),
        .sig_in     (sig_source),
        .sig_out    (sig_filter),
        .start      (pwmdac_ack),
        .done       (src_strobe)
    );




    `ifdef USE_SDDAC
    SD2DAC u_sd2dac (
        .clk        (clk),
        .rst_an     (rst_an),
        .din        ($signed({sig_filter[11:0],4'h0})),
        .din_ack    (pwmdac_ack),
        .dacout     (pwm_out)
    );
    `else
    PWMDAC u_pwmdac (
        .clk        (clk),
        .rst_an     (rst_an),
        .din        (sig_filter[10:3]),
        .din_ack    (pwmdac_ack),
        .dacout     (pwm_out)
    );    
    `endif

    CONTROLLER u_controller (
        .clk        (clk),
        .rst_an     (rst_an),
        .ldq        (ldq),
        .data_in    (data_in),
        .data_stb   (data_stb),
        .period_out (period),
        .amp_out    (amp),
        .coeff_out  (coef_bus),
        .coeff_stb  (coef_load),
        .clear_states (clear_states),
        .period_done_in (period_done)
    );

    assign sample_out = sig_filter[15:0];
    assign sample_stb = src_strobe;

    always @(posedge clk, negedge rst_an)
    begin
        if (rst_an == 0)
        begin

        end
        else
        begin

        end
    end

endmodule