data/full_repos/permissive/208113388/afu/afp/afp3_eng_fsm_intrpt.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/208113388/afu/afp/afp3_eng_fsm_intrpt.v:234: Signal definition not found, creating implicitly: \'intrpt_seq_done_int\'\n                                                                                         : ... Suggested alternative: \'intrpt_seq_done\'\n  assign  intrpt_seq_done_int =  intrpt_seq[3];\n          ^~~~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/208113388/afu/afp/afp3_eng_fsm_intrpt.v:191: Cannot find file containing module: \'mcp3_ohc03\'\n  mcp3_ohc03  intrpt_seq_err (\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208113388/afu/afp,data/full_repos/permissive/208113388/mcp3_ohc03\n             data/full_repos/permissive/208113388/afu/afp,data/full_repos/permissive/208113388/mcp3_ohc03.v\n             data/full_repos/permissive/208113388/afu/afp,data/full_repos/permissive/208113388/mcp3_ohc03.sv\n             mcp3_ohc03\n             mcp3_ohc03.v\n             mcp3_ohc03.sv\n             obj_dir/mcp3_ohc03\n             obj_dir/mcp3_ohc03.v\n             obj_dir/mcp3_ohc03.sv\n%Error: data/full_repos/permissive/208113388/afu/afp/afp3_eng_fsm_intrpt.v:267: Cannot find file containing module: \'mcp3_ohc04\'\n  mcp3_ohc04  intrpt_rtry_seq_err (\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module afp3_eng_fsm_intrpt 
  (

    input                 clock                                           
  , input                 reset


  , input                 rtry_backoff_timer_disable_q
  , input                 main_seq_done



  , input           [1:0] cmd_intrpt_type_q

  , input          [31:0] cmd_intrpt_data_q

  , input          [31:0] we_cmd_dest_ea_q
  , input                 we_cmd_is_intrpt_q
  , input                 we_cmd_is_wkhstthrd_q
  , input           [4:4] we_cmd_extra_q
  , input          [63:0] mmio_eng_obj_handle

  , input           [5:0] eng_num
  , input          [11:0] eng_actag
  , input           [7:0] cfg_afu_bdf_bus 
  , input           [4:0] cfg_afu_bdf_device
  , input           [2:0] cfg_afu_bdf_function






  , input                 start_intrpt_seq
  , input                 rspi_intrpt_resp_val_q

  , output                intrpt_req
  , output reg            intrpt_req_w_data
  , input                 arb_eng_misc_gnt


  , output                intrpt_seq_done
  , output                intrpt_seq_error

  , output          [2:0] intrpt_state
  , output                intrpt_idle_st
  , output                intrpt_wt4gnt_st
  , output                intrpt_wt4rsp_st


  , input                 start_intrpt_rtry_seq
  , input                 rtry_decode_is_immediate
  , input                 rtry_decode_is_backoff
  , input                 rtry_decode_is_abort
  , input                 intrpt_rtry_backoff_done
  , input                 intrpt_rtry_backoff_done_q

  , output                intrpt_rtry_req
  , output reg            intrpt_rtry_req_w_data
  , input                 arb_eng_rtry_misc_gnt
  , input                 arb_rtry_misc_gnt_q


  , output                intrpt_rtry_seq_error

  , output          [3:0] intrpt_rtry_state
  , output                intrpt_rtry_idle_st
  , output                intrpt_rtry_wt4bckoff_st
  , output                intrpt_rtry_wt4gnt_st
  , output                intrpt_rtry_abort_st


  , output reg            intrpt_valid
  , output reg      [7:0] intrpt_opcode
  , output reg     [11:0] intrpt_actag
  , output reg      [3:0] intrpt_stream_id 
  , output reg     [67:0] intrpt_ea_or_obj
  , output reg     [15:0] intrpt_afutag
  , output reg      [1:0] intrpt_dl
  , output reg      [2:0] intrpt_pl
  , output reg            intrpt_os
  , output reg     [63:0] intrpt_be
  , output reg      [3:0] intrpt_flag
  , output reg            intrpt_endian
  , output reg     [15:0] intrpt_bdf

  , output reg      [5:0] intrpt_pg_size


  , output                intrpt_data_valid
  , output        [511:0] intrpt_data


  , output reg            intrpt_sent_q

  );






  wire      [5:0] intrpt_seq_sel;
  reg       [4:0] intrpt_seq;
  wire            intrpt_seq_err_int;
  wire            intrpt_req_int;

  wire            intrpt_idle_state;
  wire            intrpt_wt4gnt_state;
  wire            intrpt_wt4rsp_state;


  wire     [10:0] intrpt_rtry_seq_sel;
  reg       [4:0] intrpt_rtry_seq;
  wire            intrpt_rtry_seq_err_int;
  wire            intrpt_rtry_req_int;

  wire            intrpt_rtry_idle_state;
  wire            intrpt_rtry_wt4bckoff_state;
  wire            intrpt_rtry_wt4gnt_state;
  wire            intrpt_rtry_abort_state;

  wire            intrpt_cmd_data_valid;
  wire            intrpt_err_data_valid;







  wire      [2:0] intrpt_seq_d;
  reg       [2:0] intrpt_seq_q;

  wire      [3:0] intrpt_rtry_seq_d;
  reg       [3:0] intrpt_rtry_seq_q;

  wire            intrpt_data_valid_d;
  reg             intrpt_data_valid_q;

  wire            intrpt_data_en;
  reg      [31:0] intrpt_data_d;
  reg      [31:0] intrpt_data_q;

  wire            intrpt_sent_en;
  wire            intrpt_sent_d;







  localparam    [4:0] INTRPT_WHT_AFUTAG_ENCODE                 = 5'b00111;
  localparam    [4:0] INTRPT_ERR_AFUTAG_ENCODE                 = 5'b01101;
  localparam    [4:0] INTRPT_CMD_AFUTAG_ENCODE                 = 5'b01110;


  localparam    [7:0] AFU_TLX_CMD_ENCODE_INTRP_REQ             = 8'b01011000;
  localparam    [7:0] AFU_TLX_CMD_ENCODE_INTRP_REQ_S           = 8'b01011001;
  localparam    [7:0] AFU_TLX_CMD_ENCODE_INTRP_REQ_D           = 8'b01011010;
  localparam    [7:0] AFU_TLX_CMD_ENCODE_INTRP_REQ_D_S         = 8'b01011011;






  mcp3_ohc03  intrpt_seq_err (
    .one_hot_vector   ( intrpt_seq_q[2:0] ),
    .one_hot_error    ( intrpt_seq_err_int )
  );


  assign  intrpt_idle_state   =  intrpt_seq_q[0];
  assign  intrpt_wt4gnt_state =  intrpt_seq_q[1];
  assign  intrpt_wt4rsp_state =  intrpt_seq_q[2];


  assign  intrpt_seq_sel[5:0] = { start_intrpt_seq, arb_eng_misc_gnt, rspi_intrpt_resp_val_q, intrpt_seq_q[2:0] };


  always @*
    begin
      casez ( intrpt_seq_sel[5:0] )










            6'b0??_001 :  intrpt_seq[4:0] =  5'b00_001 ;
            6'b1??_001 :  intrpt_seq[4:0] =  5'b10_010 ;

            6'b?0?_010 :  intrpt_seq[4:0] =  5'b00_010 ;
            6'b?1?_010 :  intrpt_seq[4:0] =  5'b00_100 ;

            6'b??0_100 :  intrpt_seq[4:0] =  5'b00_100 ;
            6'b??1_100 :  intrpt_seq[4:0] =  5'b01_001 ;

            default    :  intrpt_seq[4:0] =  5'b01_001 ;

      endcase
    end


  assign  intrpt_req_int      =  intrpt_seq[4];
  assign  intrpt_seq_done_int =  intrpt_seq[3];


  assign  intrpt_req      =  intrpt_req_int;
  assign  intrpt_seq_done =  intrpt_seq_done_int;


  assign  intrpt_state[2:0] =  intrpt_seq_q[2:0];  
  assign  intrpt_idle_st    =  intrpt_idle_state;
  assign  intrpt_wt4gnt_st  =  intrpt_wt4gnt_state;
  assign  intrpt_wt4rsp_st  =  intrpt_wt4rsp_state;


  assign  intrpt_seq_error =  intrpt_seq_err_int;


  assign  intrpt_seq_d[2:0] = ( reset || intrpt_seq_err_int ) ? 3'b1 :  intrpt_seq[2:0];


  always @*
    begin
      if ( we_cmd_is_intrpt_q || we_cmd_is_wkhstthrd_q )
        intrpt_req_w_data =  intrpt_req_int && we_cmd_extra_q[4];
      else
        intrpt_req_w_data =  intrpt_req_int && cmd_intrpt_type_q[1];
    end







  mcp3_ohc04  intrpt_rtry_seq_err (
    .one_hot_vector   ( intrpt_rtry_seq_q[3:0] ),
    .one_hot_error    ( intrpt_rtry_seq_err_int )
  );


  assign  intrpt_rtry_idle_state      =  intrpt_rtry_seq_q[0];
  assign  intrpt_rtry_wt4bckoff_state =  intrpt_rtry_seq_q[1];
  assign  intrpt_rtry_wt4gnt_state    =  intrpt_rtry_seq_q[2];
  assign  intrpt_rtry_abort_state     =  intrpt_rtry_seq_q[3];


  assign  intrpt_rtry_seq_sel[10:0] = { start_intrpt_rtry_seq, ( rtry_decode_is_immediate || rtry_backoff_timer_disable_q ), rtry_decode_is_backoff, rtry_decode_is_abort,
                                        intrpt_rtry_backoff_done_q, intrpt_rtry_backoff_done, arb_eng_rtry_misc_gnt, intrpt_rtry_seq_q[3:0] };

  always @*
    begin
      casez ( intrpt_rtry_seq_sel[10:0] )














           11'b0??????_0001 :  intrpt_rtry_seq[4:0] =  5'b0_0001 ;
           11'b11?????_0001 :  intrpt_rtry_seq[4:0] =  5'b1_0100 ;
           11'b101?00?_0001 :  intrpt_rtry_seq[4:0] =  5'b0_0010 ;
           11'b101?1??_0001 :  intrpt_rtry_seq[4:0] =  5'b1_0100 ;
           11'b101?01?_0001 :  intrpt_rtry_seq[4:0] =  5'b1_0100 ;
           11'b1001???_0001 :  intrpt_rtry_seq[4:0] =  5'b0_1000 ;

           11'b?????0?_0010 :  intrpt_rtry_seq[4:0] =  5'b0_0010 ;
           11'b?????1?_0010 :  intrpt_rtry_seq[4:0] =  5'b1_0100 ;

           11'b??????0_0100 :  intrpt_rtry_seq[4:0] =  5'b0_0100 ;
           11'b??????1_0100 :  intrpt_rtry_seq[4:0] =  5'b0_0001 ;

           11'b???????_1000 :  intrpt_rtry_seq[4:0] =  5'b0_0001 ;

            default         :  intrpt_rtry_seq[4:0] =  5'b0_0001 ;

      endcase
    end


  assign  intrpt_rtry_req_int      =  intrpt_rtry_seq[4];


  assign  intrpt_rtry_req          =  intrpt_rtry_req_int;


  assign  intrpt_rtry_state[3:0]   =  intrpt_rtry_seq_q[3:0];  
  assign  intrpt_rtry_idle_st      =  intrpt_rtry_idle_state;
  assign  intrpt_rtry_wt4bckoff_st =  intrpt_rtry_wt4bckoff_state;
  assign  intrpt_rtry_wt4gnt_st    =  intrpt_rtry_wt4gnt_state;
  assign  intrpt_rtry_abort_st     =  intrpt_rtry_abort_state;


  assign  intrpt_rtry_seq_error  =  intrpt_rtry_seq_err_int;


  assign  intrpt_rtry_seq_d[3:0] = ( reset || intrpt_rtry_seq_err_int ) ? 4'b1 : intrpt_rtry_seq[3:0];



  always @*
    begin
      if ( we_cmd_is_intrpt_q || we_cmd_is_wkhstthrd_q )
        intrpt_rtry_req_w_data =  intrpt_rtry_req_int && we_cmd_extra_q[4];
      else
        intrpt_rtry_req_w_data =  intrpt_rtry_req_int && cmd_intrpt_type_q[1];
    end







  always @*
    begin

      if ( intrpt_wt4gnt_state || intrpt_rtry_wt4gnt_state )
        begin
          intrpt_valid           =  (( intrpt_wt4gnt_state && arb_eng_misc_gnt ) || ( intrpt_rtry_wt4gnt_state && arb_eng_rtry_misc_gnt ));
          if (( we_cmd_is_intrpt_q || we_cmd_is_wkhstthrd_q ) && ~we_cmd_extra_q[4] )
            intrpt_opcode[7:0]   =     AFU_TLX_CMD_ENCODE_INTRP_REQ[7:0];
          else if (( we_cmd_is_intrpt_q || we_cmd_is_wkhstthrd_q ) && we_cmd_extra_q[4] )
            intrpt_opcode[7:0]   =     AFU_TLX_CMD_ENCODE_INTRP_REQ_D[7:0];
          else
            begin
              case ( cmd_intrpt_type_q[1:0] )
                2'b00 :  intrpt_opcode[7:0] =  AFU_TLX_CMD_ENCODE_INTRP_REQ[7:0];
                2'b01 :  intrpt_opcode[7:0] =  AFU_TLX_CMD_ENCODE_INTRP_REQ_S[7:0];
                2'b10 :  intrpt_opcode[7:0] =  AFU_TLX_CMD_ENCODE_INTRP_REQ_D[7:0];
                2'b11 :  intrpt_opcode[7:0] =  AFU_TLX_CMD_ENCODE_INTRP_REQ_D_S[7:0];
              endcase
            end
          intrpt_actag[11:0]     =     eng_actag[11:0];
          intrpt_stream_id[3:0]  =     4'b0;
          if ( we_cmd_is_intrpt_q || we_cmd_is_wkhstthrd_q)

            intrpt_ea_or_obj[67:0] =  {  4'b0, mmio_eng_obj_handle[63:0] };
          else

            intrpt_ea_or_obj[67:0] =  {  4'b0, mmio_eng_obj_handle[63:0] };

          if ( we_cmd_is_wkhstthrd_q )
            begin
              if ( we_cmd_extra_q[4] || cmd_intrpt_type_q[1] )
                begin
                  intrpt_afutag[15:0] =  {  2'b00, 3'b011, eng_num[5:0], INTRPT_WHT_AFUTAG_ENCODE[4:0] };
                  intrpt_pl[2:0]      =     3'b010;
                end
              else
                begin
                  intrpt_afutag[15:0] =  {  2'b00, 3'b001, eng_num[5:0], INTRPT_WHT_AFUTAG_ENCODE[4:0] };
                  intrpt_pl[2:0]      =     3'b000;
                end
            end
          else if ( we_cmd_is_intrpt_q )
            begin
              if ( we_cmd_extra_q[4] || cmd_intrpt_type_q[1] )
                begin
                  intrpt_afutag[15:0] =  {  2'b00, 3'b011, eng_num[5:0], INTRPT_CMD_AFUTAG_ENCODE[4:0] };
                  intrpt_pl[2:0]      =     3'b010;
                end
              else
                begin
                  intrpt_afutag[15:0] =  {  2'b00, 3'b001, eng_num[5:0], INTRPT_CMD_AFUTAG_ENCODE[4:0] };
                  intrpt_pl[2:0]      =     3'b000;
                end
            end
          else
            begin
              if ( we_cmd_extra_q[4] || cmd_intrpt_type_q[1] )
                begin
                  intrpt_afutag[15:0] =  {  2'b00, 3'b011, eng_num[5:0], INTRPT_ERR_AFUTAG_ENCODE[4:0] };
                  intrpt_pl[2:0]      =     3'b010;
                end
              else
                begin
                  intrpt_afutag[15:0] =  {  2'b00, 3'b001, eng_num[5:0], INTRPT_ERR_AFUTAG_ENCODE[4:0] };
                  intrpt_pl[2:0]      =     3'b000;
                end
            end

          intrpt_dl[1:0]         =     2'b00;
          intrpt_os              =     1'b0;
          intrpt_be[63:0]        =    64'b0;
          intrpt_flag[3:0]       =     4'b0;
          intrpt_endian          =     1'b0;
          intrpt_bdf[15:0]       =  { cfg_afu_bdf_bus[7:0], cfg_afu_bdf_device[4:0], cfg_afu_bdf_function[2:0] };

          intrpt_pg_size[5:0]    =     6'b0;
        end
      else
        begin
          intrpt_valid           =    1'b0;
          intrpt_opcode[7:0]     =    8'b0;
          intrpt_actag[11:0]     =   12'b0;
          intrpt_stream_id[3:0]  =    4'b0;
          intrpt_ea_or_obj[67:0] =   68'b0;
          intrpt_afutag[15:0]    =   16'b0;
          intrpt_dl[1:0]         =    2'b0;
          intrpt_pl[2:0]         =    3'b0;
          intrpt_os              =    1'b0;
          intrpt_be[63:0]        =   64'b0;
          intrpt_flag[3:0]       =    4'b0;
          intrpt_endian          =    1'b0;
          intrpt_bdf[15:0]       =   16'b0;

          intrpt_pg_size[5:0]    =    6'b0;
        end
    end






  assign  intrpt_cmd_data_valid = ((( intrpt_wt4gnt_state  && arb_eng_misc_gnt ) || ( intrpt_rtry_wt4gnt_state && arb_eng_rtry_misc_gnt )) &&
                                   (( we_cmd_is_intrpt_q || we_cmd_is_wkhstthrd_q ) && we_cmd_extra_q[4] )); 

  assign  intrpt_err_data_valid = ((( intrpt_wt4gnt_state  && arb_eng_misc_gnt ) || ( intrpt_rtry_wt4gnt_state && arb_eng_rtry_misc_gnt )) &&
                                   ( ~we_cmd_is_intrpt_q && ~we_cmd_is_wkhstthrd_q && cmd_intrpt_type_q[1] )); 

  assign  intrpt_data_valid_d   =  ( intrpt_cmd_data_valid || intrpt_err_data_valid );


  assign  intrpt_data_en =  ( reset || intrpt_cmd_data_valid || intrpt_err_data_valid || intrpt_data_valid_q );

  always @*
    begin
      if ( intrpt_cmd_data_valid )
        intrpt_data_d[31:0] =  we_cmd_dest_ea_q[31:0];
      else if ( intrpt_err_data_valid )
        intrpt_data_d[31:0] =  cmd_intrpt_data_q[31:0];
      else
        intrpt_data_d[31:0] =  32'b0;
     end

  assign  intrpt_data_valid  =  intrpt_data_valid_d;
  assign  intrpt_data[511:0] =  { 480'b0, intrpt_data_q[31:0] };







  assign  intrpt_sent_en =  ( intrpt_wt4rsp_state && rspi_intrpt_resp_val_q ) || main_seq_done || reset;
  assign  intrpt_sent_d  =  ( intrpt_wt4rsp_state && rspi_intrpt_resp_val_q );






  always @ ( posedge clock )
    begin

      intrpt_seq_q[2:0]                            <= intrpt_seq_d[2:0];        
      intrpt_rtry_seq_q[3:0]                       <= intrpt_rtry_seq_d[3:0];        

      intrpt_data_valid_q                          <= intrpt_data_valid_d;
      if ( intrpt_data_en )
        intrpt_data_q[31:0]                        <= intrpt_data_d[31:0];

      if (intrpt_sent_en )
        intrpt_sent_q                              <= intrpt_sent_d;

    end

endmodule
module afp3_eng_fsm_intrpt 
  (

    input                 clock                                           
  , input                 reset


  , input                 rtry_backoff_timer_disable_q
  , input                 main_seq_done



  , input           [1:0] cmd_intrpt_type_q

  , input          [31:0] cmd_intrpt_data_q

  , input          [31:0] we_cmd_dest_ea_q
  , input                 we_cmd_is_intrpt_q
  , input                 we_cmd_is_wkhstthrd_q
  , input           [4:4] we_cmd_extra_q
  , input          [63:0] mmio_eng_obj_handle

  , input           [5:0] eng_num
  , input          [11:0] eng_actag
  , input           [7:0] cfg_afu_bdf_bus 
  , input           [4:0] cfg_afu_bdf_device
  , input           [2:0] cfg_afu_bdf_function






  , input                 start_intrpt_seq
  , input                 rspi_intrpt_resp_val_q

  , output                intrpt_req
  , output reg            intrpt_req_w_data
  , input                 arb_eng_misc_gnt


  , output                intrpt_seq_done
  , output                intrpt_seq_error

  , output          [2:0] intrpt_state
  , output                intrpt_idle_st
  , output                intrpt_wt4gnt_st
  , output                intrpt_wt4rsp_st


  , input                 start_intrpt_rtry_seq
  , input                 rtry_decode_is_immediate
  , input                 rtry_decode_is_backoff
  , input                 rtry_decode_is_abort
  , input                 intrpt_rtry_backoff_done
  , input                 intrpt_rtry_backoff_done_q

  , output                intrpt_rtry_req
  , output reg            intrpt_rtry_req_w_data
  , input                 arb_eng_rtry_misc_gnt
  , input                 arb_rtry_misc_gnt_q


  , output                intrpt_rtry_seq_error

  , output          [3:0] intrpt_rtry_state
  , output                intrpt_rtry_idle_st
  , output                intrpt_rtry_wt4bckoff_st
  , output                intrpt_rtry_wt4gnt_st
  , output                intrpt_rtry_abort_st


  , output reg            intrpt_valid
  , output reg      [7:0] intrpt_opcode
  , output reg     [11:0] intrpt_actag
  , output reg      [3:0] intrpt_stream_id 
  , output reg     [67:0] intrpt_ea_or_obj
  , output reg     [15:0] intrpt_afutag
  , output reg      [1:0] intrpt_dl
  , output reg      [2:0] intrpt_pl
  , output reg            intrpt_os
  , output reg     [63:0] intrpt_be
  , output reg      [3:0] intrpt_flag
  , output reg            intrpt_endian
  , output reg     [15:0] intrpt_bdf

  , output reg      [5:0] intrpt_pg_size


  , output                intrpt_data_valid
  , output        [511:0] intrpt_data


  , output reg            intrpt_sent_q

  );







  wire      [5:0] intrpt_seq_sel;
  reg       [4:0] intrpt_seq;
  wire            intrpt_seq_err_int;
  wire            intrpt_req_int;

  wire            intrpt_idle_state;
  wire            intrpt_wt4gnt_state;
  wire            intrpt_wt4rsp_state;


  wire     [10:0] intrpt_rtry_seq_sel;
  reg       [4:0] intrpt_rtry_seq;
  wire            intrpt_rtry_seq_err_int;
  wire            intrpt_rtry_req_int;

  wire            intrpt_rtry_idle_state;
  wire            intrpt_rtry_wt4bckoff_state;
  wire            intrpt_rtry_wt4gnt_state;
  wire            intrpt_rtry_abort_state;

  wire            intrpt_cmd_data_valid;
  wire            intrpt_err_data_valid;







  wire      [2:0] intrpt_seq_d;
  reg       [2:0] intrpt_seq_q;

  wire      [3:0] intrpt_rtry_seq_d;
  reg       [3:0] intrpt_rtry_seq_q;

  wire            intrpt_data_valid_d;
  reg             intrpt_data_valid_q;

  wire            intrpt_data_en;
  reg      [31:0] intrpt_data_d;
  reg      [31:0] intrpt_data_q;

  wire            intrpt_sent_en;
  wire            intrpt_sent_d;







  localparam    [4:0] INTRPT_WHT_AFUTAG_ENCODE                 = 5'b00111;
  localparam    [4:0] INTRPT_ERR_AFUTAG_ENCODE                 = 5'b01101;
  localparam    [4:0] INTRPT_CMD_AFUTAG_ENCODE                 = 5'b01110;


  localparam    [7:0] AFU_TLX_CMD_ENCODE_INTRP_REQ             = 8'b01011000;
  localparam    [7:0] AFU_TLX_CMD_ENCODE_INTRP_REQ_S           = 8'b01011001;
  localparam    [7:0] AFU_TLX_CMD_ENCODE_INTRP_REQ_D           = 8'b01011010;
  localparam    [7:0] AFU_TLX_CMD_ENCODE_INTRP_REQ_D_S         = 8'b01011011;






  mcp3_ohc03  intrpt_seq_err (
    .one_hot_vector   ( intrpt_seq_q[2:0] ),
    .one_hot_error    ( intrpt_seq_err_int )
  );


  assign  intrpt_idle_state   =  intrpt_seq_q[0];
  assign  intrpt_wt4gnt_state =  intrpt_seq_q[1];
  assign  intrpt_wt4rsp_state =  intrpt_seq_q[2];


  assign  intrpt_seq_sel[5:0] = { start_intrpt_seq, arb_eng_misc_gnt, rspi_intrpt_resp_val_q, intrpt_seq_q[2:0] };


  always @*
    begin
      casez ( intrpt_seq_sel[5:0] )










            6'b0??_001 :  intrpt_seq[4:0] =  5'b00_001 ;
            6'b1??_001 :  intrpt_seq[4:0] =  5'b10_010 ;

            6'b?0?_010 :  intrpt_seq[4:0] =  5'b00_010 ;
            6'b?1?_010 :  intrpt_seq[4:0] =  5'b00_100 ;

            6'b??0_100 :  intrpt_seq[4:0] =  5'b00_100 ;
            6'b??1_100 :  intrpt_seq[4:0] =  5'b01_001 ;

            default    :  intrpt_seq[4:0] =  5'b01_001 ;

      endcase
    end


  assign  intrpt_req_int      =  intrpt_seq[4];
  assign  intrpt_seq_done_int =  intrpt_seq[3];


  assign  intrpt_req      =  intrpt_req_int;
  assign  intrpt_seq_done =  intrpt_seq_done_int;


  assign  intrpt_state[2:0] =  intrpt_seq_q[2:0];  
  assign  intrpt_idle_st    =  intrpt_idle_state;
  assign  intrpt_wt4gnt_st  =  intrpt_wt4gnt_state;
  assign  intrpt_wt4rsp_st  =  intrpt_wt4rsp_state;


  assign  intrpt_seq_error =  intrpt_seq_err_int;


  assign  intrpt_seq_d[2:0] = ( reset || intrpt_seq_err_int ) ? 3'b1 :  intrpt_seq[2:0];


  always @*
    begin
      if ( we_cmd_is_intrpt_q || we_cmd_is_wkhstthrd_q )
        intrpt_req_w_data =  intrpt_req_int && we_cmd_extra_q[4];
      else
        intrpt_req_w_data =  intrpt_req_int && cmd_intrpt_type_q[1];
    end







  mcp3_ohc04  intrpt_rtry_seq_err (
    .one_hot_vector   ( intrpt_rtry_seq_q[3:0] ),
    .one_hot_error    ( intrpt_rtry_seq_err_int )
  );


  assign  intrpt_rtry_idle_state      =  intrpt_rtry_seq_q[0];
  assign  intrpt_rtry_wt4bckoff_state =  intrpt_rtry_seq_q[1];
  assign  intrpt_rtry_wt4gnt_state    =  intrpt_rtry_seq_q[2];
  assign  intrpt_rtry_abort_state     =  intrpt_rtry_seq_q[3];


  assign  intrpt_rtry_seq_sel[10:0] = { start_intrpt_rtry_seq, ( rtry_decode_is_immediate || rtry_backoff_timer_disable_q ), rtry_decode_is_backoff, rtry_decode_is_abort,
                                        intrpt_rtry_backoff_done_q, intrpt_rtry_backoff_done, arb_eng_rtry_misc_gnt, intrpt_rtry_seq_q[3:0] };

  always @*
    begin
      casez ( intrpt_rtry_seq_sel[10:0] )














           11'b0??????_0001 :  intrpt_rtry_seq[4:0] =  5'b0_0001 ;
           11'b11?????_0001 :  intrpt_rtry_seq[4:0] =  5'b1_0100 ;
           11'b101?00?_0001 :  intrpt_rtry_seq[4:0] =  5'b0_0010 ;
           11'b101?1??_0001 :  intrpt_rtry_seq[4:0] =  5'b1_0100 ;
           11'b101?01?_0001 :  intrpt_rtry_seq[4:0] =  5'b1_0100 ;
           11'b1001???_0001 :  intrpt_rtry_seq[4:0] =  5'b0_1000 ;

           11'b?????0?_0010 :  intrpt_rtry_seq[4:0] =  5'b0_0010 ;
           11'b?????1?_0010 :  intrpt_rtry_seq[4:0] =  5'b1_0100 ;

           11'b??????0_0100 :  intrpt_rtry_seq[4:0] =  5'b0_0100 ;
           11'b??????1_0100 :  intrpt_rtry_seq[4:0] =  5'b0_0001 ;

           11'b???????_1000 :  intrpt_rtry_seq[4:0] =  5'b0_0001 ;

            default         :  intrpt_rtry_seq[4:0] =  5'b0_0001 ;

      endcase
    end


  assign  intrpt_rtry_req_int      =  intrpt_rtry_seq[4];


  assign  intrpt_rtry_req          =  intrpt_rtry_req_int;


  assign  intrpt_rtry_state[3:0]   =  intrpt_rtry_seq_q[3:0];  
  assign  intrpt_rtry_idle_st      =  intrpt_rtry_idle_state;
  assign  intrpt_rtry_wt4bckoff_st =  intrpt_rtry_wt4bckoff_state;
  assign  intrpt_rtry_wt4gnt_st    =  intrpt_rtry_wt4gnt_state;
  assign  intrpt_rtry_abort_st     =  intrpt_rtry_abort_state;


  assign  intrpt_rtry_seq_error  =  intrpt_rtry_seq_err_int;


  assign  intrpt_rtry_seq_d[3:0] = ( reset || intrpt_rtry_seq_err_int ) ? 4'b1 : intrpt_rtry_seq[3:0];



  always @*
    begin
      if ( we_cmd_is_intrpt_q || we_cmd_is_wkhstthrd_q )
        intrpt_rtry_req_w_data =  intrpt_rtry_req_int && we_cmd_extra_q[4];
      else
        intrpt_rtry_req_w_data =  intrpt_rtry_req_int && cmd_intrpt_type_q[1];
    end







  always @*
    begin

      if ( intrpt_wt4gnt_state || intrpt_rtry_wt4gnt_state )
        begin
          intrpt_valid           =  (( intrpt_wt4gnt_state && arb_eng_misc_gnt ) || ( intrpt_rtry_wt4gnt_state && arb_eng_rtry_misc_gnt ));
          if (( we_cmd_is_intrpt_q || we_cmd_is_wkhstthrd_q ) && ~we_cmd_extra_q[4] )
            intrpt_opcode[7:0]   =     AFU_TLX_CMD_ENCODE_INTRP_REQ[7:0];
          else if (( we_cmd_is_intrpt_q || we_cmd_is_wkhstthrd_q ) && we_cmd_extra_q[4] )
            intrpt_opcode[7:0]   =     AFU_TLX_CMD_ENCODE_INTRP_REQ_D[7:0];
          else
            begin
              case ( cmd_intrpt_type_q[1:0] )
                2'b00 :  intrpt_opcode[7:0] =  AFU_TLX_CMD_ENCODE_INTRP_REQ[7:0];
                2'b01 :  intrpt_opcode[7:0] =  AFU_TLX_CMD_ENCODE_INTRP_REQ_S[7:0];
                2'b10 :  intrpt_opcode[7:0] =  AFU_TLX_CMD_ENCODE_INTRP_REQ_D[7:0];
                2'b11 :  intrpt_opcode[7:0] =  AFU_TLX_CMD_ENCODE_INTRP_REQ_D_S[7:0];
              endcase
            end
          intrpt_actag[11:0]     =     eng_actag[11:0];
          intrpt_stream_id[3:0]  =     4'b0;
          if ( we_cmd_is_intrpt_q || we_cmd_is_wkhstthrd_q)

            intrpt_ea_or_obj[67:0] =  {  4'b0, mmio_eng_obj_handle[63:0] };
          else

            intrpt_ea_or_obj[67:0] =  {  4'b0, mmio_eng_obj_handle[63:0] };

          if ( we_cmd_is_wkhstthrd_q )
            begin
              if ( we_cmd_extra_q[4] || cmd_intrpt_type_q[1] )
                begin
                  intrpt_afutag[15:0] =  {  2'b00, 3'b011, eng_num[5:0], INTRPT_WHT_AFUTAG_ENCODE[4:0] };
                  intrpt_pl[2:0]      =     3'b010;
                end
              else
                begin
                  intrpt_afutag[15:0] =  {  2'b00, 3'b001, eng_num[5:0], INTRPT_WHT_AFUTAG_ENCODE[4:0] };
                  intrpt_pl[2:0]      =     3'b000;
                end
            end
          else if ( we_cmd_is_intrpt_q )
            begin
              if ( we_cmd_extra_q[4] || cmd_intrpt_type_q[1] )
                begin
                  intrpt_afutag[15:0] =  {  2'b00, 3'b011, eng_num[5:0], INTRPT_CMD_AFUTAG_ENCODE[4:0] };
                  intrpt_pl[2:0]      =     3'b010;
                end
              else
                begin
                  intrpt_afutag[15:0] =  {  2'b00, 3'b001, eng_num[5:0], INTRPT_CMD_AFUTAG_ENCODE[4:0] };
                  intrpt_pl[2:0]      =     3'b000;
                end
            end
          else
            begin
              if ( we_cmd_extra_q[4] || cmd_intrpt_type_q[1] )
                begin
                  intrpt_afutag[15:0] =  {  2'b00, 3'b011, eng_num[5:0], INTRPT_ERR_AFUTAG_ENCODE[4:0] };
                  intrpt_pl[2:0]      =     3'b010;
                end
              else
                begin
                  intrpt_afutag[15:0] =  {  2'b00, 3'b001, eng_num[5:0], INTRPT_ERR_AFUTAG_ENCODE[4:0] };
                  intrpt_pl[2:0]      =     3'b000;
                end
            end

          intrpt_dl[1:0]         =     2'b00;
          intrpt_os              =     1'b0;
          intrpt_be[63:0]        =    64'b0;
          intrpt_flag[3:0]       =     4'b0;
          intrpt_endian          =     1'b0;
          intrpt_bdf[15:0]       =  { cfg_afu_bdf_bus[7:0], cfg_afu_bdf_device[4:0], cfg_afu_bdf_function[2:0] };

          intrpt_pg_size[5:0]    =     6'b0;
        end
      else
        begin
          intrpt_valid           =    1'b0;
          intrpt_opcode[7:0]     =    8'b0;
          intrpt_actag[11:0]     =   12'b0;
          intrpt_stream_id[3:0]  =    4'b0;
          intrpt_ea_or_obj[67:0] =   68'b0;
          intrpt_afutag[15:0]    =   16'b0;
          intrpt_dl[1:0]         =    2'b0;
          intrpt_pl[2:0]         =    3'b0;
          intrpt_os              =    1'b0;
          intrpt_be[63:0]        =   64'b0;
          intrpt_flag[3:0]       =    4'b0;
          intrpt_endian          =    1'b0;
          intrpt_bdf[15:0]       =   16'b0;

          intrpt_pg_size[5:0]    =    6'b0;
        end
    end






  assign  intrpt_cmd_data_valid = ((( intrpt_wt4gnt_state  && arb_eng_misc_gnt ) || ( intrpt_rtry_wt4gnt_state && arb_eng_rtry_misc_gnt )) &&
                                   (( we_cmd_is_intrpt_q || we_cmd_is_wkhstthrd_q ) && we_cmd_extra_q[4] )); 

  assign  intrpt_err_data_valid = ((( intrpt_wt4gnt_state  && arb_eng_misc_gnt ) || ( intrpt_rtry_wt4gnt_state && arb_eng_rtry_misc_gnt )) &&
                                   ( ~we_cmd_is_intrpt_q && ~we_cmd_is_wkhstthrd_q && cmd_intrpt_type_q[1] )); 

  assign  intrpt_data_valid_d   =  ( intrpt_cmd_data_valid || intrpt_err_data_valid );


  assign  intrpt_data_en =  ( reset || intrpt_cmd_data_valid || intrpt_err_data_valid || intrpt_data_valid_q );

  always @*
    begin
      if ( intrpt_cmd_data_valid )
        intrpt_data_d[31:0] =  we_cmd_dest_ea_q[31:0];
      else if ( intrpt_err_data_valid )
        intrpt_data_d[31:0] =  cmd_intrpt_data_q[31:0];
      else
        intrpt_data_d[31:0] =  32'b0;
     end

  assign  intrpt_data_valid  =  intrpt_data_valid_d;
  assign  intrpt_data[511:0] =  { 480'b0, intrpt_data_q[31:0] };







  assign  intrpt_sent_en =  ( intrpt_wt4rsp_state && rspi_intrpt_resp_val_q ) || main_seq_done || reset;
  assign  intrpt_sent_d  =  ( intrpt_wt4rsp_state && rspi_intrpt_resp_val_q );






  always @ ( posedge clock )
    begin

      intrpt_seq_q[2:0]                            <= intrpt_seq_d[2:0];        
      intrpt_rtry_seq_q[3:0]                       <= intrpt_rtry_seq_d[3:0];        

      intrpt_data_valid_q                          <= intrpt_data_valid_d;
      if ( intrpt_data_en )
        intrpt_data_q[31:0]                        <= intrpt_data_d[31:0];

      if (intrpt_sent_en )
        intrpt_sent_q                              <= intrpt_sent_d;

    end

endmodule