data/full_repos/permissive/211316121/lab6_3/BCD_7Seg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/211316121/lab6_3/BCD_7Seg.v:46: Bit extraction of var[7:0] requires 3 bit index, not 2 bits.\n                                                                         : ... In instance BCD_7Seg\n        an[clkcount] = aen[clkcount];\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/211316121/lab6_3/BCD_7Seg.v:46: Bit extraction of var[7:0] requires 3 bit index, not 2 bits.\n                                                                         : ... In instance BCD_7Seg\n        an[clkcount] = aen[clkcount];\n                          ^\n%Error: data/full_repos/permissive/211316121/lab6_3/BCD_7Seg.v:49: Cannot find file containing module: \'seven_segment\'\n    seven_segment seg0(digit, a2g);\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/lab6_3,data/full_repos/permissive/211316121/seven_segment\n             data/full_repos/permissive/211316121/lab6_3,data/full_repos/permissive/211316121/seven_segment.v\n             data/full_repos/permissive/211316121/lab6_3,data/full_repos/permissive/211316121/seven_segment.sv\n             seven_segment\n             seven_segment.v\n             seven_segment.sv\n             obj_dir/seven_segment\n             obj_dir/seven_segment.v\n             obj_dir/seven_segment.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module BCD_7Seg(
    input [15:0] bcd,
    input [1:0] clkcount,

    output [6:0] a2g,
    output reg [7:0] an
    );
    
    reg [3:0] digit;
    parameter aen = 8'b11110000;
    
    always @ (*)
    case(clkcount)
        2'b00:  digit = bcd[3:0];
        2'b01:  digit = bcd[7:4];
        2'b10:  digit = bcd[11:8];
        2'b11:  digit = bcd[15:12];
        default: digit = bcd[3:0];
    endcase
    
    always @ (*)
    begin
        an = 8'b11111111;
        an[clkcount] = aen[clkcount];
    end
    
    seven_segment seg0(digit, a2g);
endmodule
module BCD_7Seg(
    input [15:0] bcd,
    input [1:0] clkcount,

    output [6:0] a2g,
    output reg [7:0] an
    );

    
    reg [3:0] digit;
    parameter aen = 8'b11110000;
    
    always @ (*)
    case(clkcount)
        2'b00:  digit = bcd[3:0];
        2'b01:  digit = bcd[7:4];
        2'b10:  digit = bcd[11:8];
        2'b11:  digit = bcd[15:12];
        default: digit = bcd[3:0];
    endcase
    
    always @ (*)
    begin
        an = 8'b11111111;
        an[clkcount] = aen[clkcount];
    end
    
    seven_segment seg0(digit, a2g);
endmodule