data/full_repos/permissive/183092987/LedMatrix.v
 line:131: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:119: Unsupported: Ignoring delay on this delayed statement.\nalways #90.909 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:131: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:130: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:134: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:133: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:137: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:136: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:140: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:142: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:148: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:150: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:152: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:154: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:156: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:158: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:160: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:162: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:164: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:166: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:168: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:170: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:172: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:174: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:176: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:178: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:180: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:182: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:184: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:186: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:188: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:190: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:192: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:194: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:196: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:198: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:200: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:202: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:204: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:206: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:211: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:210: Unsupported: Ignoring delay on this delayed statement.\n    #(clk_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:215: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:217: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:219: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:221: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:223: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:225: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:227: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:229: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:231: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:233: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:235: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:237: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:239: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:241: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:243: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:245: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:247: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:249: Unsupported: Ignoring delay on this delayed statement.\n    #25\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:251: Unsupported: Ignoring delay on this delayed statement.\n    #25\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:253: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:256: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:258: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:260: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:262: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:264: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:266: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:268: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:270: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:272: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:274: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:276: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:278: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:280: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:282: Unsupported: Ignoring delay on this delayed statement.\n    #(sclk_half_period)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:284: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183092987/LedMatrix.v:288: Unsupported: Ignoring delay on this delayed statement.\n    #10000000;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/183092987/LedMatrix.v:51: Bit extraction of var[103:0] requires 7 bit index, not 8 bits.\n                                                                   : ... In instance LedMatrix_Test.DUT\n    pixels[row_idx][column_idx +: 8] = ~data;\n                   ^\n%Error: Exiting due to 80 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module LedMatrix_Test;
reg          clk;
reg          cs;
reg          sclk;
reg          mosi;
wire [103:0] columns;
wire [15:0]  rows;


always #90.909 clk = ~clk;
parameter clk_period = 181.818;
parameter sclk_half_period = 500;

LedMatrix DUT (.clk(clk), .cs(cs), .sclk(sclk), .mosi(mosi), .columns(columns), .rows(rows));

initial begin
    clk  = 1'b0;
    cs   = 1'b1;
    sclk = 1'b0;
    mosi = 1'b0;
    #(clk_period)
    #(clk_period)
    cs = 1'b0;
    #(clk_period)
    #(clk_period)
    cs = 1'b1;
    #(clk_period)
    #(clk_period)

    cs = 1'b0;
    #20
    mosi = 1'b1;
    #20
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #20
    mosi = 1'b0;
    cs   = 1'b1;

    #(clk_period)
    #(clk_period)


    cs = 1'b0;
    #20
    mosi = 1'b0;
    #20
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #25
    mosi = 1'b1;
    #25
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    mosi = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #20
    mosi = 1'b0;
    cs   = 1'b1;

    #10000000;
end

endmodule
module LedMatrix_Test;

reg          clk;
reg          cs;
reg          sclk;
reg          mosi;
wire [103:0] columns;
wire [15:0]  rows;


always #90.909 clk = ~clk;
parameter clk_period = 181.818;
parameter sclk_half_period = 500;

LedMatrix DUT (.clk(clk), .cs(cs), .sclk(sclk), .mosi(mosi), .columns(columns), .rows(rows));

initial begin
    clk  = 1'b0;
    cs   = 1'b1;
    sclk = 1'b0;
    mosi = 1'b0;
    #(clk_period)
    #(clk_period)
    cs = 1'b0;
    #(clk_period)
    #(clk_period)
    cs = 1'b1;
    #(clk_period)
    #(clk_period)

    cs = 1'b0;
    #20
    mosi = 1'b1;
    #20
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #20
    mosi = 1'b0;
    cs   = 1'b1;

    #(clk_period)
    #(clk_period)


    cs = 1'b0;
    #20
    mosi = 1'b0;
    #20
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #25
    mosi = 1'b1;
    #25
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    mosi = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #(sclk_half_period)
    sclk = 1'b1;
    #(sclk_half_period)
    sclk = 1'b0;
    #20
    mosi = 1'b0;
    cs   = 1'b1;

    #10000000;
end

endmodule