data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #5 rd_clk = !rd_clk & !full;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #2 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #2 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #30 full = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10 full = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #110 full = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10  full = 0;\n        ^\n%Error: data/full_repos/permissive/108891607/src/sim/rd_valid_gen_testbench.v:19: Cannot find file containing module: \'rd_valid_gen\'\n    rd_valid_gen #(\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/108891607/src/sim,data/full_repos/permissive/108891607/rd_valid_gen\n             data/full_repos/permissive/108891607/src/sim,data/full_repos/permissive/108891607/rd_valid_gen.v\n             data/full_repos/permissive/108891607/src/sim,data/full_repos/permissive/108891607/rd_valid_gen.sv\n             rd_valid_gen\n             rd_valid_gen.v\n             rd_valid_gen.sv\n             obj_dir/rd_valid_gen\n             obj_dir/rd_valid_gen.v\n             obj_dir/rd_valid_gen.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rd_valid_gen_testbench ( );


    
    parameter FIFO_DEPTH = 8;
    parameter COUNTER_WIDTH = 3;
    

    
    reg full = 0;
    reg rd_clk = 0;
    reg reset = 0;
    
    wire rd_valid;
    

    

    rd_valid_gen #(
        .FIFO_DEPTH(FIFO_DEPTH),
        .COUNTER_WIDTH(COUNTER_WIDTH)
    ) rd_valid_gen_inst (
        .full(full),
        .rd_clk(rd_clk),
        .reset(reset),
        .rd_valid(rd_valid)
    );
    

    always
        #5 rd_clk = !rd_clk & !full;
        

    initial begin
        #2 reset = 1;
        #2 reset = 0;
        
        #30 full = 1;
        #10 full = 0;
        
        #110 full = 1;
        #10  full = 0;
    end

endmodule
module rd_valid_gen_testbench ( );



    
    parameter FIFO_DEPTH = 8;
    parameter COUNTER_WIDTH = 3;
    

    
    reg full = 0;
    reg rd_clk = 0;
    reg reset = 0;
    
    wire rd_valid;
    

    

    rd_valid_gen #(
        .FIFO_DEPTH(FIFO_DEPTH),
        .COUNTER_WIDTH(COUNTER_WIDTH)
    ) rd_valid_gen_inst (
        .full(full),
        .rd_clk(rd_clk),
        .reset(reset),
        .rd_valid(rd_valid)
    );
    

    always
        #5 rd_clk = !rd_clk & !full;
        

    initial begin
        #2 reset = 1;
        #2 reset = 0;
        
        #30 full = 1;
        #10 full = 0;
        
        #110 full = 1;
        #10  full = 0;
    end

endmodule