data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array.v
data/verilator_xmls/6963c2f9-0e6a-474d-b24a-26ae3c40ee51.xml
module simple_memory_using_1d_array(
    input  clk,
    input  write,
    input  [3:0] addr,
    input  [7:0] wdata,
    output [7:0] rdata
);


reg [7:0] mem [0:15];

assign rdata = mem[addr];

always @ (posedge clk) begin
    if (write) begin

        mem[addr] <= wdata;
    end
end

endmodule
module simple_memory_using_1d_array(
    input  clk,
    input  write,
    input  [3:0] addr,
    input  [7:0] wdata,
    output [7:0] rdata
);



reg [7:0] mem [0:15];

assign rdata = mem[addr];

always @ (posedge clk) begin
    if (write) begin

        mem[addr] <= wdata;
    end
end

endmodule