data/full_repos/permissive/190426879/extension/source/regfile.v
None: at end of input
data/verilator_xmls/8255f043-adb2-4c51-b74e-4878023b29da.xml
module regfile (rna,rnb,d,wn,we,clk,clrn,qa,qb);
   input [4:0] rna,rnb,wn;
   input [31:0] d;
   input we,clk,clrn;
   
   output [31:0] qa,qb;
   
   reg [31:0] register [1:31];
   
   assign qa = (rna == 0)? 0 : register[rna];
   assign qb = (rnb == 0)? 0 : register[rnb];

   always @(posedge clk or negedge clrn) begin
      if (clrn == 0) begin: myblock
         integer i;
         for (i=1; i<32; i=i+1)
            register[i] <= 0;
      end else begin
         if ((wn != 0) && (we == 1))
            register[wn] <= d;
      end
   end
endmodule
module regfile (rna,rnb,d,wn,we,clk,clrn,qa,qb);

   input [4:0] rna,rnb,wn;
   input [31:0] d;
   input we,clk,clrn;
   
   output [31:0] qa,qb;
   
   reg [31:0] register [1:31];
   
   assign qa = (rna == 0)? 0 : register[rna];
   assign qb = (rnb == 0)? 0 : register[rnb];

   always @(posedge clk or negedge clrn) begin
      if (clrn == 0) begin: myblock
         integer i;
         for (i=1; i<32; i=i+1)
            register[i] <= 0;
      end else begin
         if ((wn != 0) && (we == 1))
            register[wn] <= d;
      end
   end
endmodule