data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v
 line:431: before: "signed"
1: b'%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:76: Cannot find file containing module: \'FFT_8\'\n FFT_8 FFT8_1(.i0(FFT8_N1[0]),\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/FFT_8\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/FFT_8.v\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/FFT_8.sv\n             FFT_8\n             FFT_8.v\n             FFT_8.sv\n             obj_dir/FFT_8\n             obj_dir/FFT_8.v\n             obj_dir/FFT_8.sv\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:93: Cannot find file containing module: \'FFT_8\'\n FFT_8 FFT8_2(.i0(FFT8_N2[0]),\n ^~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:110: Cannot find file containing module: \'FFT_8\'\n FFT_8 FFT8_3(.i0(FFT8_N3[0]),\n ^~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:127: Cannot find file containing module: \'FFT_8\'\n FFT_8 FFT8_4(.i0(FFT8_N4[0]),\n ^~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:144: Cannot find file containing module: \'FFT_8\'\n FFT_8 FFT8_5(.i0(FFT8_N5[0]),\n ^~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:161: Cannot find file containing module: \'FFT_8\'\n FFT_8 FFT8_6(.i0(FFT8_N6[0]),\n ^~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:178: Cannot find file containing module: \'FFT_8\'\n FFT_8 FFT8_7(.i0(FFT8_N7[0]),\n ^~~~~\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:195: Cannot find file containing module: \'FFT_8\'\n FFT_8 FFT8_8(.i0(FFT8_N8[0]),\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:434: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL002 = 0 + (op<<1) ;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:441: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL004 = 0 + (op<<2) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:448: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL008 = 0 + (op<<3) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:455: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL016 = 0 + (op<<4) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:462: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL032 = 0 + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:469: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL064 = 0 + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:476: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL128 = 0 + (op<<7) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:483: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL060 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:483: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL060 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:483: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL060 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:483: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL060 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<5) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:492: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL120 = 0 + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:492: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL120 = 0 + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:492: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL120 = 0 + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:492: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL120 = 0 + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:501: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL017 = 0 + op     + (op<<4) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:501: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL017 = 0 + op     + (op<<4) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:510: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL034 = 0 + (op<<1)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:510: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL034 = 0 + (op<<1)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:520: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL068 = 0 + (op<<2)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:520: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL068 = 0 + (op<<2)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:529: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL030 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:529: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL030 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:529: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL030 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:529: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL030 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<4) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:540: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL046 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:540: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL046 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:540: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL046 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:540: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL046 = 0 + (op<<1)  + (op<<2)  + (op<<3)  + (op<<5) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:548: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL067 = 0 + op     + (op<<1)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:548: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL067 = 0 + op     + (op<<1)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:548: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL067 = 0 + op     + (op<<1)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:557: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL092 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:557: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL092 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:557: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL092 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:557: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL092 = 0 + (op<<2)  + (op<<3)  + (op<<4)  + (op<<6) ;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:566: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL123 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:566: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL123 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:566: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL123 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:566: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL123 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:566: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL123 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:566: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL123 = 0 + op     + (op<<1)  + (op<<3)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:577: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL022 = 0 + (op<<1)  + (op<<2)  + (op<<4) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:577: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL022 = 0 + (op<<1)  + (op<<2)  + (op<<4) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:577: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL022 = 0 + (op<<1)  + (op<<2)  + (op<<4) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:586: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL117 = 0 + op     + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:586: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL117 = 0 + op     + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:586: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL117 = 0 + op     + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:586: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL117 = 0 + op     + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:586: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL117 = 0 + op     + (op<<2)  + (op<<4)  + (op<<5)  + (op<<6) ;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:599: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL073 = 0 + op     + (op<<3)  + (op<<6) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:599: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL073 = 0 + op     + (op<<3)  + (op<<6) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:599: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL073 = 0 + op     + (op<<3)  + (op<<6) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:611: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL070 = 0 + (op<<1)  + (op<<2)  + (op<<6) ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:611: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL070 = 0 + (op<<1)  + (op<<2)  + (op<<6) ;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:611: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL070 = 0 + (op<<1)  + (op<<2)  + (op<<6) ;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:621: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL035 = 0 + op     + (op<<1)  + (op<<5) ;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:621: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL035 = 0 + op     + (op<<1)  + (op<<5) ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:621: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'op\' generates 9 bits.\n                                                                               : ... In instance FFT_64\n  MUL035 = 0 + op     + (op<<1)  + (op<<5) ;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:271: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 15 bits.\n                                                                               : ... In instance FFT_64\n  assign yo[(i+1)*10-1:10*i] = yo_array[i];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:278: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n  assign yo_array[i] = FFT8_O1[i];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:279: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n  assign yo_array[i+8] = FFT8_O2[i];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:280: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n  assign yo_array[i+16] = FFT8_O3[i];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:281: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n  assign yo_array[i+24] = FFT8_O4[i];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:282: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n  assign yo_array[i+32] = FFT8_O5[i];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:283: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n  assign yo_array[i+40] = FFT8_O6[i];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:284: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n  assign yo_array[i+48] = FFT8_O7[i];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:285: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n  assign yo_array[i+56] = FFT8_O8[i];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:342: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N1[0] <= FFT8_O1[0];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:343: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N1[1] <= FFT8_O2[0];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:344: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N1[2] <= FFT8_O3[0];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:345: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N1[3] <= FFT8_O4[0];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:346: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N1[4] <= FFT8_O5[0];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:347: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N1[5] <= FFT8_O6[0];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:348: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N1[6] <= FFT8_O7[0];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:349: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N1[7] <= FFT8_O8[0];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:351: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N2[0] <= FFT8_O1[1];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:360: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N3[0] <= FFT8_O1[2];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:369: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N4[0] <= FFT8_O1[3];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:378: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N5[0] <= FFT8_O1[4];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:387: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N6[0] <= FFT8_O1[5];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:396: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N7[0] <= FFT8_O1[6];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/FFT_64.v:405: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                               : ... In instance FFT_64\n    FFT8_N8[0] <= FFT8_O1[7];\n               ^~\n%Error: Exiting due to 8 error(s), 83 warning(s)\n'
function signed  [15:0] MUL067;
	  input signed [8:0] op;
	  begin
		MUL067 = 0 + op     + (op<<1)  + (op<<6) ;
	  end
	endfunction
function signed  [15:0] MUL067;

	  input signed [8:0] op;
	  begin
		MUL067 = 0 + op     + (op<<1)  + (op<<6) ;
	  end
	endfunction