data/full_repos/permissive/104443190/chen_div.v
 line:13: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:14: Unsupported: Ignoring delay on this delayed statement.\n initial #30 rst=1;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:15: Unsupported: Ignoring delay on this delayed statement.\n always#10 clk=~clk;\n       ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module chen_div_tb;  
  
	reg clk=0,rst=0;
	initial #30 rst=1;
	always#10 clk=~clk;


	reg divide_en=0;
	reg [31:0] dividend=0,divisor=0;

	integer i=0;
	always@(posedge clk)
	begin
		i <= i + 1;
		if(i==7)
			begin
				divide_en=1; dividend={16'd10,16'd0};divisor={16'd0,16'd3};
			end
		else if(i==8)
			begin
				divide_en=1; dividend=10;divisor=2;
			end
		else 
			begin
				divide_en=0; dividend=0;divisor=0;
			end
	end

    wire divide_error;
    wire divide_done;
    wire [31:0] quotient;
    wire [31:0] remainde;

	chen_unsigned_div chen_unsigned_div( 
		.clk(clk),
		.rst_n(rst),
		.divide_en(divide_en),
		.dividend(dividend),
		.divisor(divisor),
		.divide_error(divide_error),
		.divide_done(divide_done),
		.quotient(quotient),
		.remainde(remainde) 
		); 



	reg divide_en_signed=0;
	reg [15:0] dividend_signed=0,divisor_signed=0;

	integer j=0;
	always@(posedge clk)
	begin
		j <= j + 1;
		if(j==7)
			begin
				divide_en_signed=1; dividend_signed=-16'sd10;divisor_signed=16'sd3;
			end
		else if(j==8)
			begin
				divide_en_signed=1; dividend_signed=-16'sd10;divisor_signed=16'sd0;
			end
		else 
			begin
				divide_en_signed=0; dividend_signed=0;divisor_signed=0;
			end
	end

	wire divide_error_signed;
    wire divide_done_signed;
    wire [31:0] quotient_signed;

	chen_signed_div chen_signed_div( 
		.clk(clk),
		.rst_n(rst),
		.divide_en(divide_en_signed),
		.dividend(dividend_signed),
		.divisor(divisor_signed),
		.divide_error(divide_error_signed),
		.divide_done(divide_done_signed),
		.quotient(quotient_signed) 
		);
  
endmodule
module chen_div_tb;
  
  
	reg clk=0,rst=0;
	initial #30 rst=1;
	always#10 clk=~clk;


	reg divide_en=0;
	reg [31:0] dividend=0,divisor=0;

	integer i=0;
	always@(posedge clk)
	begin
		i <= i + 1;
		if(i==7)
			begin
				divide_en=1; dividend={16'd10,16'd0};divisor={16'd0,16'd3};
			end
		else if(i==8)
			begin
				divide_en=1; dividend=10;divisor=2;
			end
		else 
			begin
				divide_en=0; dividend=0;divisor=0;
			end
	end

    wire divide_error;
    wire divide_done;
    wire [31:0] quotient;
    wire [31:0] remainde;

	chen_unsigned_div chen_unsigned_div( 
		.clk(clk),
		.rst_n(rst),
		.divide_en(divide_en),
		.dividend(dividend),
		.divisor(divisor),
		.divide_error(divide_error),
		.divide_done(divide_done),
		.quotient(quotient),
		.remainde(remainde) 
		); 



	reg divide_en_signed=0;
	reg [15:0] dividend_signed=0,divisor_signed=0;

	integer j=0;
	always@(posedge clk)
	begin
		j <= j + 1;
		if(j==7)
			begin
				divide_en_signed=1; dividend_signed=-16'sd10;divisor_signed=16'sd3;
			end
		else if(j==8)
			begin
				divide_en_signed=1; dividend_signed=-16'sd10;divisor_signed=16'sd0;
			end
		else 
			begin
				divide_en_signed=0; dividend_signed=0;divisor_signed=0;
			end
	end

	wire divide_error_signed;
    wire divide_done_signed;
    wire [31:0] quotient_signed;

	chen_signed_div chen_signed_div( 
		.clk(clk),
		.rst_n(rst),
		.divide_en(divide_en_signed),
		.dividend(dividend_signed),
		.divisor(divisor_signed),
		.divide_error(divide_error_signed),
		.divide_done(divide_done_signed),
		.quotient(quotient_signed) 
		);
  
endmodule