data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v
 line:69: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst= 1\'b1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #160 rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #160 rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #160 rx = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #160 rx = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #160 rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #160 rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #160 rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #160 rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #160 rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #160 rx = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #160 rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:58: Unsupported: Ignoring delay on this delayed statement.\n     #160 rx = 1\'b1;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:59: Unsupported: Ignoring delay on this delayed statement.\n     #160 rx = 1\'b0;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:60: Unsupported: Ignoring delay on this delayed statement.\n     #160 rx = 1\'b0;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:61: Unsupported: Ignoring delay on this delayed statement.\n     #160 rx = 1\'b0;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:62: Unsupported: Ignoring delay on this delayed statement.\n     #160 rx = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:63: Unsupported: Ignoring delay on this delayed statement.\n     #160 rx = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:64: Unsupported: Ignoring delay on this delayed statement.\n     #160 rx = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:65: Unsupported: Ignoring delay on this delayed statement.\n     #160 rx = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:67: Unsupported: Ignoring delay on this delayed statement.\n     #160 rx = 1\'b1;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #500000000 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:71: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 clk=~clk;   \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:72: Unsupported: Ignoring delay on this delayed statement.\nalways #5 rate=~rate;        \n       ^\n%Error: data/full_repos/permissive/205673649/UART/Simulacion/tb_rx.v:75: Cannot find file containing module: \'rx\'\nrx #(.NB_DATA(NB_DBIT_01), .SB_TICK(NB_TICK_01))\n^~\n        ... Looked in:\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/rx\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/rx.v\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/rx.sv\n             rx\n             rx.v\n             rx.sv\n             obj_dir/rx\n             obj_dir/rx.v\n             obj_dir/rx.sv\n%Error: Exiting due to 1 error(s), 24 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_rx();


localparam  NB_DBIT_01    =  8;
localparam NB_TICK_01 = 16;
reg  clk;
reg  rst;
reg  rx;
reg rate;
wire [NB_DBIT_01-1:0] data;
wire done_data_interfaz;



initial	
begin
    clk = 1'b0;
    rate = 1'b0;
    rst = 1'b0;
    rx= 1'b1;
    
    #10 rst= 1'b1;
    #160 rx = 1'b0;
            
    #160 rx = 1'b0;
    #160 rx = 1'b1;
    #160 rx = 1'b1;
    #160 rx = 1'b0;
    #160 rx = 1'b0;
    #160 rx = 1'b0;
    #160 rx = 1'b0;
    #160 rx = 1'b0;
    
    #160 rx = 1'b1;
    
    #160 rx = 1'b0;
             
     #160 rx = 1'b1;
     #160 rx = 1'b0;
     #160 rx = 1'b0;
     #160 rx = 1'b0;
     #160 rx = 1'b0;
     #160 rx = 1'b0;
     #160 rx = 1'b0;
     #160 rx = 1'b0;
     
     #160 rx = 1'b1;
    
    #500000000 $finish;
end
always #2.5 clk=~clk;
always #5 rate=~rate;


rx #(.NB_DATA(NB_DBIT_01), .SB_TICK(NB_TICK_01))
u_a
(
    .i_clk(clk),
    .i_rst(rst),
    .i_bit(rx),                  
    .i_tick(rate),
    .o_done_data(done_data_interfaz),  
    .o_data(data)      
);


endmodule
module tb_rx();



localparam  NB_DBIT_01    =  8;
localparam NB_TICK_01 = 16;
reg  clk;
reg  rst;
reg  rx;
reg rate;
wire [NB_DBIT_01-1:0] data;
wire done_data_interfaz;



initial	
begin
    clk = 1'b0;
    rate = 1'b0;
    rst = 1'b0;
    rx= 1'b1;
    
    #10 rst= 1'b1;
    #160 rx = 1'b0;
            
    #160 rx = 1'b0;
    #160 rx = 1'b1;
    #160 rx = 1'b1;
    #160 rx = 1'b0;
    #160 rx = 1'b0;
    #160 rx = 1'b0;
    #160 rx = 1'b0;
    #160 rx = 1'b0;
    
    #160 rx = 1'b1;
    
    #160 rx = 1'b0;
             
     #160 rx = 1'b1;
     #160 rx = 1'b0;
     #160 rx = 1'b0;
     #160 rx = 1'b0;
     #160 rx = 1'b0;
     #160 rx = 1'b0;
     #160 rx = 1'b0;
     #160 rx = 1'b0;
     
     #160 rx = 1'b1;
    
    #500000000 $finish;
end
always #2.5 clk=~clk;
always #5 rate=~rate;


rx #(.NB_DATA(NB_DBIT_01), .SB_TICK(NB_TICK_01))
u_a
(
    .i_clk(clk),
    .i_rst(rst),
    .i_bit(rx),                  
    .i_tick(rate),
    .o_done_data(done_data_interfaz),  
    .o_data(data)      
);


endmodule