data/full_repos/permissive/143278/ivltests/br_gh99a.v
 line:11: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh99a.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #2 $display("%b %b", value, pass);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

wire [7:0] value;
wire       pass;

assign value[3:0] = 4'd2;

assign pass = (value === 8'bzzzz0010);

initial begin
  #2 $display("%b %b", value, pass);
  if (pass === 1)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module test();


wire [7:0] value;
wire       pass;

assign value[3:0] = 4'd2;

assign pass = (value === 8'bzzzz0010);

initial begin
  #2 $display("%b %b", value, pass);
  if (pass === 1)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule