data/full_repos/permissive/168753118/rtl/modules/PC_CALC.v
data/verilator_xmls/48b5bbfb-682d-43d9-bfc4-fca0b6822862.xml
module PC_CALC #(
  parameter XLEN = 32
)(

  input pc_calc_correction_en_in,
  input pc_calc_prediction_en_in,


  input [XLEN-1:0] pc_calc_current_in,


  input [XLEN-1:0] pc_calc_correction_in,
  input [XLEN-1:0] pc_calc_prediction_in,


  output reg pc_calc_pred_out,
  output reg [XLEN-1:0] pc_calc_addr_out
);


always @ ( * ) begin
  case ({pc_calc_correction_en_in, pc_calc_prediction_en_in})
    2'b00: pc_calc_addr_out = pc_calc_current_in + 4;
    2'b01: pc_calc_addr_out = pc_calc_prediction_in;
    2'b10: pc_calc_addr_out = pc_calc_correction_in;
    2'b11: pc_calc_addr_out = pc_calc_correction_in;
  endcase

  pc_calc_pred_out = pc_calc_prediction_en_in & !pc_calc_correction_en_in;

end

endmodule
module PC_CALC #(
  parameter XLEN = 32
)(

  input pc_calc_correction_en_in,
  input pc_calc_prediction_en_in,


  input [XLEN-1:0] pc_calc_current_in,


  input [XLEN-1:0] pc_calc_correction_in,
  input [XLEN-1:0] pc_calc_prediction_in,


  output reg pc_calc_pred_out,
  output reg [XLEN-1:0] pc_calc_addr_out
);



always @ ( * ) begin
  case ({pc_calc_correction_en_in, pc_calc_prediction_en_in})
    2'b00: pc_calc_addr_out = pc_calc_current_in + 4;
    2'b01: pc_calc_addr_out = pc_calc_prediction_in;
    2'b10: pc_calc_addr_out = pc_calc_correction_in;
    2'b11: pc_calc_addr_out = pc_calc_correction_in;
  endcase

  pc_calc_pred_out = pc_calc_prediction_en_in & !pc_calc_correction_en_in;

end

endmodule