data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/syncCorrector.v
1: b'%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/syncCorrector.v:85: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                 : ... In instance syncCorrector.vdect\n    lowCount <= 24\'d0;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/syncCorrector.v:86: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                 : ... In instance syncCorrector.vdect\n    highCount <= 24\'d0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/syncCorrector.v:92: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                 : ... In instance syncCorrector.vdect\n        lowCount <= 24\'d0;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/syncCorrector.v:93: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                 : ... In instance syncCorrector.vdect\n        highCount <= 24\'d0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/overlay_logic/syncCorrector.v:99: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                                                 : ... In instance syncCorrector.vdect\n        lowCount <= 24\'d0;\n                 ^~\n%Error: Exiting due to 5 warning(s)\n'
module syncPolDecter(
  input wire pxlClk,
  input wire rst,
  
  input wire sync,
  
  output reg normalSync

);

reg [24:0] lowCount;
reg [24:0] highCount;
reg sync_d1;

always @(posedge pxlClk or negedge rst) begin
  if(!rst) begin
    sync_d1 <= 1'b0;
  end else begin
    sync_d1 <= sync;
  end
end


always @(posedge pxlClk or negedge rst) begin

  if(!rst) begin
    lowCount <= 24'd0;
    highCount <= 24'd0;
    normalSync <= 1'b1;
  end else begin
    if(sync) begin
      if(!sync_d1) begin
        normalSync <= highCount > lowCount;
        lowCount <= 24'd0;
        highCount <= 24'd0;
      end else begin 
        highCount <= highCount + 1;
      end
    end else begin 
      if(sync_d1) begin
        lowCount <= 24'd0;
      end else begin
        lowCount <= lowCount + 1;
      end
    end
  end

end


endmodule
module syncPolDecter(
  input wire pxlClk,
  input wire rst,
  
  input wire sync,
  
  output reg normalSync

);


reg [24:0] lowCount;
reg [24:0] highCount;
reg sync_d1;

always @(posedge pxlClk or negedge rst) begin
  if(!rst) begin
    sync_d1 <= 1'b0;
  end else begin
    sync_d1 <= sync;
  end
end


always @(posedge pxlClk or negedge rst) begin

  if(!rst) begin
    lowCount <= 24'd0;
    highCount <= 24'd0;
    normalSync <= 1'b1;
  end else begin
    if(sync) begin
      if(!sync_d1) begin
        normalSync <= highCount > lowCount;
        lowCount <= 24'd0;
        highCount <= 24'd0;
      end else begin 
        highCount <= highCount + 1;
      end
    end else begin 
      if(sync_d1) begin
        lowCount <= 24'd0;
      end else begin
        lowCount <= lowCount + 1;
      end
    end
  end

end


endmodule