data/full_repos/permissive/200650987/src/verilog/discarded/demo-cache/icache/icache_tag.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/200650987/src/verilog/discarded/demo-cache/icache/icache_tag.v:20: Cannot find file containing module: 'icache_tag_ram'\nicache_tag_ram icache_tag_ram_u\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200650987/src/verilog/discarded/demo-cache/icache,data/full_repos/permissive/200650987/icache_tag_ram\n             data/full_repos/permissive/200650987/src/verilog/discarded/demo-cache/icache,data/full_repos/permissive/200650987/icache_tag_ram.v\n             data/full_repos/permissive/200650987/src/verilog/discarded/demo-cache/icache,data/full_repos/permissive/200650987/icache_tag_ram.sv\n             icache_tag_ram\n             icache_tag_ram.v\n             icache_tag_ram.sv\n             obj_dir/icache_tag_ram\n             obj_dir/icache_tag_ram.v\n             obj_dir/icache_tag_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module icache_tag
(
    input         clk,
    input         rst,
    input    [3:0] wen,
    input         en,
    input   [20:0] wdata,
    output  [20:0] rdata,

    input   [31:0] addr,
    output         hit,
    output         valid
);

assign hit = (rdata[19:0] == addr[31:12]) ? 1'b1 : 1'b0;
assign valid = rdata[20];


icache_tag_ram icache_tag_ram_u
(
    .clka  (clk            ),   

    .ena   (en        ),
    .wea   (wen       ),
    .addra (addr[11:5]),
    .dina  (wdata     ),
    .douta (rdata     )
);


endmodule
module icache_tag
(
    input         clk,
    input         rst,
    input    [3:0] wen,
    input         en,
    input   [20:0] wdata,
    output  [20:0] rdata,

    input   [31:0] addr,
    output         hit,
    output         valid
);


assign hit = (rdata[19:0] == addr[31:12]) ? 1'b1 : 1'b0;
assign valid = rdata[20];


icache_tag_ram icache_tag_ram_u
(
    .clka  (clk            ),   

    .ena   (en        ),
    .wea   (wen       ),
    .addra (addr[11:5]),
    .dina  (wdata     ),
    .douta (rdata     )
);


endmodule