data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/sim/fifo_1clk_tb.v
 line:1 column:1: Illegal character '\x00'
1: b"%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/sim/fifo_1clk_tb.v:26: Cannot find file containing module: 'clock_gen'\n  clock_gen clkgen(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/sim,data/full_repos/permissive/181738725/clock_gen\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/sim,data/full_repos/permissive/181738725/clock_gen.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/sim,data/full_repos/permissive/181738725/clock_gen.sv\n             clock_gen\n             clock_gen.v\n             clock_gen.sv\n             obj_dir/clock_gen\n             obj_dir/clock_gen.v\n             obj_dir/clock_gen.sv\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/sim/fifo_1clk_tb.v:35: Cannot find file containing module: 'stream_source'\n  stream_source #(\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/sim/fifo_1clk_tb.v:52: Cannot find file containing module: 'stream_fifo_1clk'\n  stream_fifo_1clk #(\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/sim/fifo_1clk_tb.v:73: Cannot find file containing module: 'stream_sink'\n  stream_sink #(\n  ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module fifo_1clk_tb;




  wire clk, rst;
  clock_gen clkgen(
    .clk (clk),
    .rst (rst));




  wire       din_valid, din_ready;
  wire [7:0] din_data;
  stream_source #(
    .Filename    ("in.dat"),
    .NumSymbols (1),
    .SymbolBits ({32'd8}))
  src (
    .clk       (clk),
    .rst       (rst),
    .dout_ready(din_ready),
    .dout_valid(din_valid),
    .dout_data (din_data));




  wire        dout_valid, dout_ready;
  wire [7:0]  dout_data;

  stream_fifo_1clk #(
    .Width    (8),
    .Depth    (100))
  fifo(
    .clk       (clk),
    .rst       (rst),

    .din_valid (din_valid),
    .din_ready (din_ready),
    .din_data  (din_data),

    .dout_valid(dout_valid),
    .dout_ready(dout_ready),
    .dout_data (dout_data),

    .used ( ));




  wire       done, err;
  stream_sink #(
    .FilenameDump ("out.dat"),
    .FilenameRef  ("ref.dat"),
    .CheckData    (1),
    .NumSymbols   (1),
    .SymbolBits   ({32'd8}))
  snk (
    .clk       (clk),
    .rst       (rst),
    .din_ready (dout_ready),
    .din_valid (dout_valid),
    .din_data  (dout_data),
    .done      (done),
    .err       (err));




  reg        finished;
  always @(posedge clk) begin
    if (!finished) begin
      if (done) begin
        if (err)
          $display("***SIMULATION FAILED***");
        else
          $display("***SIMULATION PASSED***");

        finished = 1;
      end
    end
    if (rst)
      finished = 0;
  end


endmodule
module fifo_1clk_tb;





  wire clk, rst;
  clock_gen clkgen(
    .clk (clk),
    .rst (rst));




  wire       din_valid, din_ready;
  wire [7:0] din_data;
  stream_source #(
    .Filename    ("in.dat"),
    .NumSymbols (1),
    .SymbolBits ({32'd8}))
  src (
    .clk       (clk),
    .rst       (rst),
    .dout_ready(din_ready),
    .dout_valid(din_valid),
    .dout_data (din_data));




  wire        dout_valid, dout_ready;
  wire [7:0]  dout_data;

  stream_fifo_1clk #(
    .Width    (8),
    .Depth    (100))
  fifo(
    .clk       (clk),
    .rst       (rst),

    .din_valid (din_valid),
    .din_ready (din_ready),
    .din_data  (din_data),

    .dout_valid(dout_valid),
    .dout_ready(dout_ready),
    .dout_data (dout_data),

    .used ( ));




  wire       done, err;
  stream_sink #(
    .FilenameDump ("out.dat"),
    .FilenameRef  ("ref.dat"),
    .CheckData    (1),
    .NumSymbols   (1),
    .SymbolBits   ({32'd8}))
  snk (
    .clk       (clk),
    .rst       (rst),
    .din_ready (dout_ready),
    .din_valid (dout_valid),
    .din_data  (dout_data),
    .done      (done),
    .err       (err));




  reg        finished;
  always @(posedge clk) begin
    if (!finished) begin
      if (done) begin
        if (err)
          $display("***SIMULATION FAILED***");
        else
          $display("***SIMULATION PASSED***");

        finished = 1;
      end
    end
    if (rst)
      finished = 0;
  end


endmodule