data/full_repos/permissive/114091260/material/CPU设计代码/第二步/内存实现/initial初始化/memory.v
data/verilator_xmls/8442b39e-f01a-4555-a925-fa6bc95bc31b.xml
module memory(
    input clk,
    input [7:0] addr,
    input we,
    input [15:0] datain,
    output [15:0] dataout
    );

	reg [15:0] RAM[255:0];
	
	assign dataout = RAM[addr];
	always @(posedge clk)
		if (we)
			RAM[addr] <= datain;

endmodule
module memory(
    input clk,
    input [7:0] addr,
    input we,
    input [15:0] datain,
    output [15:0] dataout
    );


	reg [15:0] RAM[255:0];
	
	assign dataout = RAM[addr];
	always @(posedge clk)
		if (we)
			RAM[addr] <= datain;

endmodule