data/full_repos/permissive/208113388/config_subsystem/cfg_respfifo.v
 line:97: before: "("
data/verilator_xmls/c5f02203-70c0-45f3-b82b-5216e9109648.xml
module cfg_respfifo (
    input         clock
  , input         reset


  , input   [7:0] cfg_rff_resp_opcode
  , input   [3:0] cfg_rff_resp_code


  , input  [15:0] cfg_rff_resp_capptag
  , input   [3:0] cfg_rff_rdata_offset
  , input         cfg_rff_rdata_bdi
  , input  [31:0] cfg_rff_rdata_bus
  , input         cfg_rff_resp_in_valid
  , output  [3:0] resp_buffers_available


  , output  [7:0] cfg_tlx_resp_opcode

  , output [15:0] cfg_tlx_resp_capptag

  , output  [3:0] cfg_tlx_resp_code
  , output  [3:0] cfg_tlx_rdata_offset
  , output [31:0] cfg_tlx_rdata_bus
  , output        cfg_tlx_rdata_bdi


  , `ifdef MARK_DEBUG_ACTIVE (* mark_debug = "TRUE" *) `endif
    output        cfg_tlx_resp_valid
  , `ifdef MARK_DEBUG_ACTIVE (* mark_debug = "TRUE" *) `endif
    input         tlx_cfg_resp_ack


  , output        fifo_overflow
) ;






parameter integer WIDTH = 68;


reg  [WIDTH-1:0] respfifo [7:0];
wire [WIDTH-1:0] resp_in, resp_out;

reg  [2:0] wrptr;
reg  [2:0] rdptr;
reg  [7:0] respfifo_val;
reg        resp_sent;

wire       resp_in_valid;
assign resp_in_valid = cfg_rff_resp_in_valid;


always @(posedge(clock))
  begin
    if (reset == 1'b1) 
      wrptr <= 3'b000;
    else if (resp_in_valid == 1'b1 && wrptr != 3'b111)   
      wrptr <= wrptr + 3'b001;
    else if (resp_in_valid == 1'b1 && wrptr == 3'b111)   
      wrptr <= 3'b000;
    else
      wrptr <= wrptr;
  end


always @(posedge(clock))
  begin
    if (reset == 1'b1)
      rdptr <= 3'b000;
    else if (resp_sent == 1'b1 && rdptr != 3'b111)
      rdptr <= rdptr + 3'b001;
    else if (resp_sent == 1'b1 && rdptr == 3'b111)
      rdptr <= 3'b000;
    else
      rdptr <= rdptr;
  end


always @(posedge(clock))
  begin 
    if (reset == 1'b1)  
      respfifo_val <= 8'h00;
    else if (resp_in_valid == 1'b1 && resp_sent == 1'b0)  
      respfifo_val <= respfifo_val | (8'h01 << wrptr);
    else if (resp_in_valid == 1'b0 && resp_sent == 1'b1)
      respfifo_val <= respfifo_val & ~(8'h01 << rdptr);
    else if (resp_in_valid == 1'b1 && resp_sent == 1'b1)
      respfifo_val <= (respfifo_val | (8'h01 << wrptr)) & ~(8'h01 << rdptr);
    else
      respfifo_val <= respfifo_val;
  end


assign resp_in = {            
    cfg_rff_resp_opcode
  , cfg_rff_resp_code


  , cfg_rff_resp_capptag
  , cfg_rff_rdata_offset
  , 3'b000
  , cfg_rff_rdata_bdi
  , cfg_rff_rdata_bus
};



always @(posedge(clock)) begin
  if (resp_in_valid) respfifo[wrptr] <= resp_in;
end





assign resp_out = (respfifo_val[rdptr] == 1'b1) ? respfifo[rdptr] : {WIDTH{1'b0}};  


wire  [2:0] pad;
assign {
    cfg_tlx_resp_opcode
  , cfg_tlx_resp_code


  , cfg_tlx_resp_capptag
  , cfg_tlx_rdata_offset
  , pad
  , cfg_tlx_rdata_bdi
  , cfg_tlx_rdata_bus
} = resp_out;


wire   resp_out_valid;
assign resp_out_valid = respfifo_val[rdptr];  


assign fifo_overflow   = (resp_in_valid == 1'b1 && respfifo_val == 8'hFF) ? 1'b1 : 1'b0;




reg [3:0] resp_buffers_used;
always @(*)
  if (respfifo_val == 8'h00)
    resp_buffers_used = 4'b0000; 
  else if (wrptr > rdptr)
    resp_buffers_used = {1'b0,wrptr} - {1'b0,rdptr};
  else if (wrptr < rdptr)
    resp_buffers_used = (4'b1000 + {1'b0,wrptr}) - {1'b0,rdptr};   
  else
    resp_buffers_used = 4'b1000; 
assign resp_buffers_available = 4'b1000 - resp_buffers_used;







reg [1:0] SM_CFG_RFF;
parameter SM_CFG_RFF_IDLE           = 2'b00;
parameter SM_CFG_RFF_WAIT_FOR_ACK_1 = 2'b01;
parameter SM_CFG_RFF_WAIT_FOR_ACK_0 = 2'b10;
parameter SM_CFG_RFF_ERROR          = 2'b11;

reg    resp_valid;
assign cfg_tlx_resp_valid = resp_valid;


always @(posedge(clock))
  case (SM_CFG_RFF)

    SM_CFG_RFF_IDLE:            
      if (resp_out_valid == 1'b1)
        begin
          resp_valid <= 1'b1;
          resp_sent  <= 1'b0;
        end
      else
        begin
          resp_valid <= 1'b0;
          resp_sent  <= 1'b0;
        end

    SM_CFG_RFF_WAIT_FOR_ACK_1:
      if (tlx_cfg_resp_ack == 1'b1)
        begin
          resp_valid <= 1'b0;
          resp_sent  <= 1'b1;
        end
      else
        begin
          resp_valid <= resp_valid;
          resp_sent  <= resp_sent;
        end

    SM_CFG_RFF_WAIT_FOR_ACK_0:
      if (tlx_cfg_resp_ack == 1'b0)
        begin
          resp_valid <= 1'b0;
          resp_sent  <= 1'b0;
        end
      else
        begin
          resp_valid <= resp_valid;
          resp_sent  <= 1'b0;
        end

    SM_CFG_RFF_ERROR:
      begin
        resp_valid <= 1'b0;
        resp_sent  <= 1'b0;
      end
  endcase


always @(posedge(clock))
  if (reset == 1'b1)                             SM_CFG_RFF <= SM_CFG_RFF_IDLE;   
  else 
    case (SM_CFG_RFF)
      SM_CFG_RFF_IDLE:            
          if (resp_out_valid == 1'b1)            SM_CFG_RFF <= SM_CFG_RFF_WAIT_FOR_ACK_1;
          else                                   SM_CFG_RFF <= SM_CFG_RFF_IDLE;
      SM_CFG_RFF_WAIT_FOR_ACK_1:
          if (tlx_cfg_resp_ack == 1'b1)          SM_CFG_RFF <= SM_CFG_RFF_WAIT_FOR_ACK_0;
          else                                   SM_CFG_RFF <= SM_CFG_RFF_WAIT_FOR_ACK_1;
      SM_CFG_RFF_WAIT_FOR_ACK_0:
          if (tlx_cfg_resp_ack == 1'b0)          SM_CFG_RFF <= SM_CFG_RFF_IDLE;
          else                                   SM_CFG_RFF <= SM_CFG_RFF_WAIT_FOR_ACK_0;
      SM_CFG_RFF_ERROR:
                                                 SM_CFG_RFF <= SM_CFG_RFF_ERROR;
      default:
                                                 SM_CFG_RFF <= SM_CFG_RFF_ERROR;
    endcase

endmodule
module cfg_respfifo (
    input         clock
  , input         reset


  , input   [7:0] cfg_rff_resp_opcode
  , input   [3:0] cfg_rff_resp_code


  , input  [15:0] cfg_rff_resp_capptag
  , input   [3:0] cfg_rff_rdata_offset
  , input         cfg_rff_rdata_bdi
  , input  [31:0] cfg_rff_rdata_bus
  , input         cfg_rff_resp_in_valid
  , output  [3:0] resp_buffers_available


  , output  [7:0] cfg_tlx_resp_opcode

  , output [15:0] cfg_tlx_resp_capptag

  , output  [3:0] cfg_tlx_resp_code
  , output  [3:0] cfg_tlx_rdata_offset
  , output [31:0] cfg_tlx_rdata_bus
  , output        cfg_tlx_rdata_bdi


  , `ifdef MARK_DEBUG_ACTIVE (* mark_debug = "TRUE" *) `endif
    output        cfg_tlx_resp_valid
  , `ifdef MARK_DEBUG_ACTIVE (* mark_debug = "TRUE" *) `endif
    input         tlx_cfg_resp_ack


  , output        fifo_overflow
) ;







parameter integer WIDTH = 68;


reg  [WIDTH-1:0] respfifo [7:0];
wire [WIDTH-1:0] resp_in, resp_out;

reg  [2:0] wrptr;
reg  [2:0] rdptr;
reg  [7:0] respfifo_val;
reg        resp_sent;

wire       resp_in_valid;
assign resp_in_valid = cfg_rff_resp_in_valid;


always @(posedge(clock))
  begin
    if (reset == 1'b1) 
      wrptr <= 3'b000;
    else if (resp_in_valid == 1'b1 && wrptr != 3'b111)   
      wrptr <= wrptr + 3'b001;
    else if (resp_in_valid == 1'b1 && wrptr == 3'b111)   
      wrptr <= 3'b000;
    else
      wrptr <= wrptr;
  end


always @(posedge(clock))
  begin
    if (reset == 1'b1)
      rdptr <= 3'b000;
    else if (resp_sent == 1'b1 && rdptr != 3'b111)
      rdptr <= rdptr + 3'b001;
    else if (resp_sent == 1'b1 && rdptr == 3'b111)
      rdptr <= 3'b000;
    else
      rdptr <= rdptr;
  end


always @(posedge(clock))
  begin 
    if (reset == 1'b1)  
      respfifo_val <= 8'h00;
    else if (resp_in_valid == 1'b1 && resp_sent == 1'b0)  
      respfifo_val <= respfifo_val | (8'h01 << wrptr);
    else if (resp_in_valid == 1'b0 && resp_sent == 1'b1)
      respfifo_val <= respfifo_val & ~(8'h01 << rdptr);
    else if (resp_in_valid == 1'b1 && resp_sent == 1'b1)
      respfifo_val <= (respfifo_val | (8'h01 << wrptr)) & ~(8'h01 << rdptr);
    else
      respfifo_val <= respfifo_val;
  end


assign resp_in = {            
    cfg_rff_resp_opcode
  , cfg_rff_resp_code


  , cfg_rff_resp_capptag
  , cfg_rff_rdata_offset
  , 3'b000
  , cfg_rff_rdata_bdi
  , cfg_rff_rdata_bus
};



always @(posedge(clock)) begin
  if (resp_in_valid) respfifo[wrptr] <= resp_in;
end





assign resp_out = (respfifo_val[rdptr] == 1'b1) ? respfifo[rdptr] : {WIDTH{1'b0}};  


wire  [2:0] pad;
assign {
    cfg_tlx_resp_opcode
  , cfg_tlx_resp_code


  , cfg_tlx_resp_capptag
  , cfg_tlx_rdata_offset
  , pad
  , cfg_tlx_rdata_bdi
  , cfg_tlx_rdata_bus
} = resp_out;


wire   resp_out_valid;
assign resp_out_valid = respfifo_val[rdptr];  


assign fifo_overflow   = (resp_in_valid == 1'b1 && respfifo_val == 8'hFF) ? 1'b1 : 1'b0;




reg [3:0] resp_buffers_used;
always @(*)
  if (respfifo_val == 8'h00)
    resp_buffers_used = 4'b0000; 
  else if (wrptr > rdptr)
    resp_buffers_used = {1'b0,wrptr} - {1'b0,rdptr};
  else if (wrptr < rdptr)
    resp_buffers_used = (4'b1000 + {1'b0,wrptr}) - {1'b0,rdptr};   
  else
    resp_buffers_used = 4'b1000; 
assign resp_buffers_available = 4'b1000 - resp_buffers_used;







reg [1:0] SM_CFG_RFF;
parameter SM_CFG_RFF_IDLE           = 2'b00;
parameter SM_CFG_RFF_WAIT_FOR_ACK_1 = 2'b01;
parameter SM_CFG_RFF_WAIT_FOR_ACK_0 = 2'b10;
parameter SM_CFG_RFF_ERROR          = 2'b11;

reg    resp_valid;
assign cfg_tlx_resp_valid = resp_valid;


always @(posedge(clock))
  case (SM_CFG_RFF)

    SM_CFG_RFF_IDLE:            
      if (resp_out_valid == 1'b1)
        begin
          resp_valid <= 1'b1;
          resp_sent  <= 1'b0;
        end
      else
        begin
          resp_valid <= 1'b0;
          resp_sent  <= 1'b0;
        end

    SM_CFG_RFF_WAIT_FOR_ACK_1:
      if (tlx_cfg_resp_ack == 1'b1)
        begin
          resp_valid <= 1'b0;
          resp_sent  <= 1'b1;
        end
      else
        begin
          resp_valid <= resp_valid;
          resp_sent  <= resp_sent;
        end

    SM_CFG_RFF_WAIT_FOR_ACK_0:
      if (tlx_cfg_resp_ack == 1'b0)
        begin
          resp_valid <= 1'b0;
          resp_sent  <= 1'b0;
        end
      else
        begin
          resp_valid <= resp_valid;
          resp_sent  <= 1'b0;
        end

    SM_CFG_RFF_ERROR:
      begin
        resp_valid <= 1'b0;
        resp_sent  <= 1'b0;
      end
  endcase


always @(posedge(clock))
  if (reset == 1'b1)                             SM_CFG_RFF <= SM_CFG_RFF_IDLE;   
  else 
    case (SM_CFG_RFF)
      SM_CFG_RFF_IDLE:            
          if (resp_out_valid == 1'b1)            SM_CFG_RFF <= SM_CFG_RFF_WAIT_FOR_ACK_1;
          else                                   SM_CFG_RFF <= SM_CFG_RFF_IDLE;
      SM_CFG_RFF_WAIT_FOR_ACK_1:
          if (tlx_cfg_resp_ack == 1'b1)          SM_CFG_RFF <= SM_CFG_RFF_WAIT_FOR_ACK_0;
          else                                   SM_CFG_RFF <= SM_CFG_RFF_WAIT_FOR_ACK_1;
      SM_CFG_RFF_WAIT_FOR_ACK_0:
          if (tlx_cfg_resp_ack == 1'b0)          SM_CFG_RFF <= SM_CFG_RFF_IDLE;
          else                                   SM_CFG_RFF <= SM_CFG_RFF_WAIT_FOR_ACK_0;
      SM_CFG_RFF_ERROR:
                                                 SM_CFG_RFF <= SM_CFG_RFF_ERROR;
      default:
                                                 SM_CFG_RFF <= SM_CFG_RFF_ERROR;
    endcase

endmodule