data/full_repos/permissive/219219909/Radix-5/src/buf_inout.v
data/verilator_xmls/9fc592c9-567a-4143-9ed4-9809e1524994.xml
module buf_inout(
    input [31:0] a_re,
    input [31:0] a_img,
    input [31:0] b_re,
    input [31:0] b_img,
    input [31:0] c_re,
    input [31:0] c_img,
    input [31:0] d_re,
    input [31:0] d_img,
    input [31:0] e_re,
    input [31:0] e_img,
    input clk,
    output reg [31:0] a1_re,
    output reg [31:0] a1_img,
    output reg [31:0] b1_re,
    output reg [31:0] b1_img,
    output reg [31:0] c1_re,
    output reg [31:0] c1_img,
    output reg [31:0] d1_re,
    output reg [31:0] d1_img,
    output reg [31:0] e1_re,
    output reg [31:0] e1_img
    );
always @(posedge clk) begin
a1_re<=a_re;
a1_img<=a_img;
b1_re<=b_re;
b1_img<=b_img;
c1_re<=c_re;
c1_img<=c_img;
d1_re<=d_re;
d1_img<=d_img;
e1_re<=e_re;
e1_img<=e_img;
end
endmodule
module buf_inout(
    input [31:0] a_re,
    input [31:0] a_img,
    input [31:0] b_re,
    input [31:0] b_img,
    input [31:0] c_re,
    input [31:0] c_img,
    input [31:0] d_re,
    input [31:0] d_img,
    input [31:0] e_re,
    input [31:0] e_img,
    input clk,
    output reg [31:0] a1_re,
    output reg [31:0] a1_img,
    output reg [31:0] b1_re,
    output reg [31:0] b1_img,
    output reg [31:0] c1_re,
    output reg [31:0] c1_img,
    output reg [31:0] d1_re,
    output reg [31:0] d1_img,
    output reg [31:0] e1_re,
    output reg [31:0] e1_img
    );

always @(posedge clk) begin
a1_re<=a_re;
a1_img<=a_img;
b1_re<=b_re;
b1_img<=b_img;
c1_re<=c_re;
c1_img<=c_img;
d1_re<=d_re;
d1_img<=d_img;
e1_re<=e_re;
e1_img<=e_img;
end
endmodule