data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v
'utf-8' codec can't decode byte 0xca in position 627: invalid continuation byte
1: b'%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:113: Operator ADD expects 32 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                                   : ... In instance g_ipsend\n        check_buffer<=ip_header[0][15:0]+ip_header[0][31:16]+ip_header[1][15:0]+ip_header[1][31:16]+ip_header[2][15:0]+\n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:113: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                   : ... In instance g_ipsend\n        check_buffer<=ip_header[0][15:0]+ip_header[0][31:16]+ip_header[1][15:0]+ip_header[1][31:16]+ip_header[2][15:0]+\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:113: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                   : ... In instance g_ipsend\n        check_buffer<=ip_header[0][15:0]+ip_header[0][31:16]+ip_header[1][15:0]+ip_header[1][31:16]+ip_header[2][15:0]+\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:113: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                   : ... In instance g_ipsend\n        check_buffer<=ip_header[0][15:0]+ip_header[0][31:16]+ip_header[1][15:0]+ip_header[1][31:16]+ip_header[2][15:0]+\n                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:113: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                   : ... In instance g_ipsend\n        check_buffer<=ip_header[0][15:0]+ip_header[0][31:16]+ip_header[1][15:0]+ip_header[1][31:16]+ip_header[2][15:0]+\n                                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:113: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                   : ... In instance g_ipsend\n        check_buffer<=ip_header[0][15:0]+ip_header[0][31:16]+ip_header[1][15:0]+ip_header[1][31:16]+ip_header[2][15:0]+\n                                                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:114: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                   : ... In instance g_ipsend\n           ip_header[2][31:16]+ip_header[3][15:0]+ip_header[3][31:16]+ip_header[4][15:0]+ip_header[4][31:16];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:114: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                   : ... In instance g_ipsend\n           ip_header[2][31:16]+ip_header[3][15:0]+ip_header[3][31:16]+ip_header[4][15:0]+ip_header[4][31:16];\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:114: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                   : ... In instance g_ipsend\n           ip_header[2][31:16]+ip_header[3][15:0]+ip_header[3][31:16]+ip_header[4][15:0]+ip_header[4][31:16];\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:114: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                   : ... In instance g_ipsend\n           ip_header[2][31:16]+ip_header[3][15:0]+ip_header[3][31:16]+ip_header[4][15:0]+ip_header[4][31:16];\n                                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:131: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n                                                                                   : ... In instance g_ipsend\n      dataout[7:0]<=preamble[i][7:0];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:136: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n                                                                                   : ... In instance g_ipsend\n       dataout[7:0]<=preamble[i][7:0];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:144: Bit extraction of array[13:0] requires 4 bit index, not 5 bits.\n                                                                                   : ... In instance g_ipsend\n      dataout[7:0]<=mac_addr[i][7:0];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:149: Bit extraction of array[13:0] requires 4 bit index, not 5 bits.\n                                                                                   : ... In instance g_ipsend\n       dataout[7:0]<=mac_addr[i][7:0];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:156: Bit extraction of array[6:0] requires 3 bit index, not 5 bits.\n                                                                                   : ... In instance g_ipsend\n        dataout[7:0]<=ip_header[j][31:24];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:160: Bit extraction of array[6:0] requires 3 bit index, not 5 bits.\n                                                                                   : ... In instance g_ipsend\n        dataout[7:0]<=ip_header[j][23:16];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:164: Bit extraction of array[6:0] requires 3 bit index, not 5 bits.\n                                                                                   : ... In instance g_ipsend\n        dataout[7:0]<=ip_header[j][15:8];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:168: Bit extraction of array[6:0] requires 3 bit index, not 5 bits.\n                                                                                   : ... In instance g_ipsend\n        dataout[7:0]<=ip_header[j][7:0];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:178: Bit extraction of array[6:0] requires 3 bit index, not 5 bits.\n                                                                                   : ... In instance g_ipsend\n        dataout[7:0]<=ip_header[j][31:24];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:182: Bit extraction of array[6:0] requires 3 bit index, not 5 bits.\n                                                                                   : ... In instance g_ipsend\n        dataout[7:0]<=ip_header[j][23:16];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:186: Bit extraction of array[6:0] requires 3 bit index, not 5 bits.\n                                                                                   : ... In instance g_ipsend\n        dataout[7:0]<=ip_header[j][15:8];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/ethernet/1G/g_ipsend.v:190: Bit extraction of array[6:0] requires 3 bit index, not 5 bits.\n                                                                                   : ... In instance g_ipsend\n        dataout[7:0]<=ip_header[j][7:0];\n                               ^\n%Error: Exiting due to 22 warning(s)\n'
module g_ipsend(
				  input              clk,
				  output reg         txen,
				  output reg         txer,
				  output reg [7:0]   dataout,
				  input              reset_n,  				  
				  input      [31:0]  crc,
				  input      [31:0]  datain,
				  output reg         crcen,
				  output reg         crcre,
				  output reg         crc_valid,
				  output reg [3:0]   tx_state,
				  output reg [31:0]  datain_reg,
				  input      [15:0]  tx_data_length,
				  input      [15:0]  tx_total_length,
				  output reg [8:0]   ram_rd_addr
				  
	  );


	  
reg [31:0] ip_header [6:0];

reg [7:0] preamble [7:0];
reg [7:0] mac_addr [13:0];
reg [4:0] i,j;

reg [31:0] check_buffer;
reg [31:0] time_counter;
reg [15:0] tx_data_counter;

parameter idle=4'b0000,start=4'b0001,make=4'b0010,send55=4'b0011,sendmac=4'b0100,sendheader=4'b0101,
          senddata=4'b0110,sendcrc=4'b0111;



initial
  begin


	 preamble[0]<=8'h55;
	 preamble[1]<=8'h55;
	 preamble[2]<=8'h55;
	 preamble[3]<=8'h55;
	 preamble[4]<=8'h55;
	 preamble[5]<=8'h55;
	 preamble[6]<=8'h55;
	 preamble[7]<=8'hD5;
	 mac_addr[0]<=8'hFF;
	 mac_addr[1]<=8'hFF;
	 mac_addr[2]<=8'hFF;
	 mac_addr[3]<=8'hFF;
	 mac_addr[4]<=8'hFF;
	 mac_addr[5]<=8'hFF;
	 mac_addr[6]<=8'h00;
	 mac_addr[7]<=8'h0A;
	 mac_addr[8]<=8'h35;
	 mac_addr[9]<=8'h01;
	 mac_addr[10]<=8'hFE;
	 mac_addr[11]<=8'hC0;
	 mac_addr[12]<=8'h08;
	 mac_addr[13]<=8'h00;
	 i<=0;
 end

	 
always@(negedge clk)
begin		
		if(reset_n==1'b0) begin
		  tx_state<=idle;
		  time_counter<=0;
		  crc_valid<=1'b0;
		  txer<=1'b0;
		  txen<=1'b0;
		  crcen<=1'b0;
		  crcre<=1;
		  j<=0;
		  ram_rd_addr<=1;
		  tx_data_counter<=0;
      end		  
		else begin
			case(tx_state)
			  idle:begin
					 crc_valid<=1'b0;
					 txer<=1'b0;
					 txen<=1'b0;
					 crcen<=1'b0;
					 crcre<=1;
					 j<=0;
					 ram_rd_addr<=1;
					 tx_data_counter<=0;
					 if (time_counter==32'h08000000) begin
						  tx_state<=start;  
						  time_counter<=0;
					 end
					 else
						  time_counter<=time_counter+1'b1;				
				end
				start:begin
						ip_header[0]<={16'h4500,tx_total_length};
						ip_header[1][31:16]<=ip_header[1][31:16]+1'b1;
						ip_header[1][15:0]<=16'h4000;
						ip_header[2]<=32'h80110000;
						ip_header[3]<=32'hc0a80002;
						ip_header[4]<=32'hc0a80003;
						ip_header[5]<=32'h1f901f90;
						ip_header[6]<={tx_data_length,16'h0000};
						tx_state<=make;
				end	
				make:begin
					 if(i==0) begin
						  check_buffer<=ip_header[0][15:0]+ip_header[0][31:16]+ip_header[1][15:0]+ip_header[1][31:16]+ip_header[2][15:0]+
											ip_header[2][31:16]+ip_header[3][15:0]+ip_header[3][31:16]+ip_header[4][15:0]+ip_header[4][31:16];
						  i<=i+1'b1;
						end
					 else if(i==1) begin
							check_buffer[15:0]<=check_buffer[31:16]+check_buffer[15:0];
							i<=i+1'b1;
					 end
					 else	begin
							ip_header[2][15:0]<=~check_buffer[15:0];
							i<=0;
							tx_state<=send55;
						end
				end
				send55: begin
					 txen<=1'b1;
					 crcre<=1'b1;
					 if(i==7) begin
						dataout[7:0]<=preamble[i][7:0];
						i<=0;
						tx_state<=sendmac;
					 end
					 else begin                        
						 dataout[7:0]<=preamble[i][7:0];
						 i<=i+1;
					 end
				end	
				sendmac: begin
					 crcen<=1'b1;
					 crcre<=1'b0;                            			
					 if(i==13) begin
						dataout[7:0]<=mac_addr[i][7:0];
						i<=0;
						tx_state<=sendheader;
					 end
					 else begin                        
						 dataout[7:0]<=mac_addr[i][7:0];
						 i<=i+1'b1;
					 end
				end
				sendheader: begin
					if(j==6) begin                             
						  if(i==0) begin
							 dataout[7:0]<=ip_header[j][31:24];
							 i<=i+1'b1;
						  end
						  else if(i==1) begin
							 dataout[7:0]<=ip_header[j][23:16];
							 i<=i+1'b1;
						  end
						  else if(i==2) begin
							 dataout[7:0]<=ip_header[j][15:8];
							 i<=i+1'b1;
						  end
						  else if(i==3) begin
							 dataout[7:0]<=ip_header[j][7:0];
							 i<=0;
							 j<=0;
							 tx_state<=senddata;			 
						  end
						  else
							 txer<=1'b1;
					end		 
					else begin
						  if(i==0) begin
							 dataout[7:0]<=ip_header[j][31:24];
							 i<=i+1'b1;
						  end
						  else if(i==1) begin
							 dataout[7:0]<=ip_header[j][23:16];
							 i<=i+1'b1;
						  end
						  else if(i==2) begin
							 dataout[7:0]<=ip_header[j][15:8];
							 i<=i+1'b1;
						  end
						  else if(i==3) begin
							 dataout[7:0]<=ip_header[j][7:0];
							 i<=0;
							 j<=j+1'b1;
						  end					
						  else
							 txer<=1'b1;
					end
				 end
				 senddata:begin
					if(tx_data_counter==tx_data_length-9) begin
						tx_state<=sendcrc;	
						if(i==0) begin    
						  dataout[7:0]<=datain[31:24];
						  i<=0;
						end
						else if(i==1) begin
						  dataout[7:0]<=datain[23:16];
						  i<=0;
						end
						else if(i==2) begin
						  dataout[7:0]<=datain[15:8];
						  i<=0;
						end
						else if(i==3) begin
						  dataout[7:0]<=datain[7:0];
						  i<=0;
						end
					end
					else begin
						tx_data_counter<=tx_data_counter+1'b1;			
						if(i==0) begin    
						  dataout[7:0]<=datain[31:24];
						  i<=i+1'b1;
						end
						else if(i==1) begin
						  dataout[7:0]<=datain[23:16];
						  i<=i+1'b1;
						end
						else if(i==2) begin
						  dataout[7:0]<=datain[15:8];
						  i<=i+1'b1;
						end
						else if(i==3) begin
						  dataout[7:0]<=datain[7:0];
						  i<=0; 
						  ram_rd_addr<=ram_rd_addr+1'b1;						  
						end
					end
				end	
				sendcrc: begin
					crcen<=1'b0;
					crc_valid<=1'b1;
					if(i==0)	begin
						  dataout[7:0] <= {~crc[24], ~crc[25], ~crc[26], ~crc[27], ~crc[28], ~crc[29], ~crc[30], ~crc[31]};
						  i<=i+1'b1;
						end
					else begin
					  if(i==1) begin
							dataout[7:0]<={~crc[16], ~crc[17], ~crc[18], ~crc[19], ~crc[20], ~crc[21], ~crc[22], ~crc[23]};
							i<=i+1'b1;
					  end
					  else if(i==2) begin
							dataout[7:0]<={~crc[8], ~crc[9], ~crc[10], ~crc[11], ~crc[12], ~crc[13], ~crc[14], ~crc[15]};
							i<=i+1'b1;
					  end
					  else if(i==3) begin
							dataout[7:0]<={~crc[0], ~crc[1], ~crc[2], ~crc[3], ~crc[4], ~crc[5], ~crc[6], ~crc[7]};
							i<=0;
							tx_state<=idle;
							crc_valid<=1'b0;
					  end
					  else begin
							txer<=1'b1;
					  end
					end
				end					
				default:tx_state<=idle;		
			 endcase	 
     end			 
 end
endmodule
module g_ipsend(
				  input              clk,
				  output reg         txen,
				  output reg         txer,
				  output reg [7:0]   dataout,
				  input              reset_n,  				  
				  input      [31:0]  crc,
				  input      [31:0]  datain,
				  output reg         crcen,
				  output reg         crcre,
				  output reg         crc_valid,
				  output reg [3:0]   tx_state,
				  output reg [31:0]  datain_reg,
				  input      [15:0]  tx_data_length,
				  input      [15:0]  tx_total_length,
				  output reg [8:0]   ram_rd_addr
				  
	  );



	  
reg [31:0] ip_header [6:0];

reg [7:0] preamble [7:0];
reg [7:0] mac_addr [13:0];
reg [4:0] i,j;

reg [31:0] check_buffer;
reg [31:0] time_counter;
reg [15:0] tx_data_counter;

parameter idle=4'b0000,start=4'b0001,make=4'b0010,send55=4'b0011,sendmac=4'b0100,sendheader=4'b0101,
          senddata=4'b0110,sendcrc=4'b0111;



initial
  begin


	 preamble[0]<=8'h55;
	 preamble[1]<=8'h55;
	 preamble[2]<=8'h55;
	 preamble[3]<=8'h55;
	 preamble[4]<=8'h55;
	 preamble[5]<=8'h55;
	 preamble[6]<=8'h55;
	 preamble[7]<=8'hD5;
	 mac_addr[0]<=8'hFF;
	 mac_addr[1]<=8'hFF;
	 mac_addr[2]<=8'hFF;
	 mac_addr[3]<=8'hFF;
	 mac_addr[4]<=8'hFF;
	 mac_addr[5]<=8'hFF;
	 mac_addr[6]<=8'h00;
	 mac_addr[7]<=8'h0A;
	 mac_addr[8]<=8'h35;
	 mac_addr[9]<=8'h01;
	 mac_addr[10]<=8'hFE;
	 mac_addr[11]<=8'hC0;
	 mac_addr[12]<=8'h08;
	 mac_addr[13]<=8'h00;
	 i<=0;
 end

	 
always@(negedge clk)
begin		
		if(reset_n==1'b0) begin
		  tx_state<=idle;
		  time_counter<=0;
		  crc_valid<=1'b0;
		  txer<=1'b0;
		  txen<=1'b0;
		  crcen<=1'b0;
		  crcre<=1;
		  j<=0;
		  ram_rd_addr<=1;
		  tx_data_counter<=0;
      end		  
		else begin
			case(tx_state)
			  idle:begin
					 crc_valid<=1'b0;
					 txer<=1'b0;
					 txen<=1'b0;
					 crcen<=1'b0;
					 crcre<=1;
					 j<=0;
					 ram_rd_addr<=1;
					 tx_data_counter<=0;
					 if (time_counter==32'h08000000) begin
						  tx_state<=start;  
						  time_counter<=0;
					 end
					 else
						  time_counter<=time_counter+1'b1;				
				end
				start:begin
						ip_header[0]<={16'h4500,tx_total_length};
						ip_header[1][31:16]<=ip_header[1][31:16]+1'b1;
						ip_header[1][15:0]<=16'h4000;
						ip_header[2]<=32'h80110000;
						ip_header[3]<=32'hc0a80002;
						ip_header[4]<=32'hc0a80003;
						ip_header[5]<=32'h1f901f90;
						ip_header[6]<={tx_data_length,16'h0000};
						tx_state<=make;
				end	
				make:begin
					 if(i==0) begin
						  check_buffer<=ip_header[0][15:0]+ip_header[0][31:16]+ip_header[1][15:0]+ip_header[1][31:16]+ip_header[2][15:0]+
											ip_header[2][31:16]+ip_header[3][15:0]+ip_header[3][31:16]+ip_header[4][15:0]+ip_header[4][31:16];
						  i<=i+1'b1;
						end
					 else if(i==1) begin
							check_buffer[15:0]<=check_buffer[31:16]+check_buffer[15:0];
							i<=i+1'b1;
					 end
					 else	begin
							ip_header[2][15:0]<=~check_buffer[15:0];
							i<=0;
							tx_state<=send55;
						end
				end
				send55: begin
					 txen<=1'b1;
					 crcre<=1'b1;
					 if(i==7) begin
						dataout[7:0]<=preamble[i][7:0];
						i<=0;
						tx_state<=sendmac;
					 end
					 else begin                        
						 dataout[7:0]<=preamble[i][7:0];
						 i<=i+1;
					 end
				end	
				sendmac: begin
					 crcen<=1'b1;
					 crcre<=1'b0;                            			
					 if(i==13) begin
						dataout[7:0]<=mac_addr[i][7:0];
						i<=0;
						tx_state<=sendheader;
					 end
					 else begin                        
						 dataout[7:0]<=mac_addr[i][7:0];
						 i<=i+1'b1;
					 end
				end
				sendheader: begin
					if(j==6) begin                             
						  if(i==0) begin
							 dataout[7:0]<=ip_header[j][31:24];
							 i<=i+1'b1;
						  end
						  else if(i==1) begin
							 dataout[7:0]<=ip_header[j][23:16];
							 i<=i+1'b1;
						  end
						  else if(i==2) begin
							 dataout[7:0]<=ip_header[j][15:8];
							 i<=i+1'b1;
						  end
						  else if(i==3) begin
							 dataout[7:0]<=ip_header[j][7:0];
							 i<=0;
							 j<=0;
							 tx_state<=senddata;			 
						  end
						  else
							 txer<=1'b1;
					end		 
					else begin
						  if(i==0) begin
							 dataout[7:0]<=ip_header[j][31:24];
							 i<=i+1'b1;
						  end
						  else if(i==1) begin
							 dataout[7:0]<=ip_header[j][23:16];
							 i<=i+1'b1;
						  end
						  else if(i==2) begin
							 dataout[7:0]<=ip_header[j][15:8];
							 i<=i+1'b1;
						  end
						  else if(i==3) begin
							 dataout[7:0]<=ip_header[j][7:0];
							 i<=0;
							 j<=j+1'b1;
						  end					
						  else
							 txer<=1'b1;
					end
				 end
				 senddata:begin
					if(tx_data_counter==tx_data_length-9) begin
						tx_state<=sendcrc;	
						if(i==0) begin    
						  dataout[7:0]<=datain[31:24];
						  i<=0;
						end
						else if(i==1) begin
						  dataout[7:0]<=datain[23:16];
						  i<=0;
						end
						else if(i==2) begin
						  dataout[7:0]<=datain[15:8];
						  i<=0;
						end
						else if(i==3) begin
						  dataout[7:0]<=datain[7:0];
						  i<=0;
						end
					end
					else begin
						tx_data_counter<=tx_data_counter+1'b1;			
						if(i==0) begin    
						  dataout[7:0]<=datain[31:24];
						  i<=i+1'b1;
						end
						else if(i==1) begin
						  dataout[7:0]<=datain[23:16];
						  i<=i+1'b1;
						end
						else if(i==2) begin
						  dataout[7:0]<=datain[15:8];
						  i<=i+1'b1;
						end
						else if(i==3) begin
						  dataout[7:0]<=datain[7:0];
						  i<=0; 
						  ram_rd_addr<=ram_rd_addr+1'b1;						  
						end
					end
				end	
				sendcrc: begin
					crcen<=1'b0;
					crc_valid<=1'b1;
					if(i==0)	begin
						  dataout[7:0] <= {~crc[24], ~crc[25], ~crc[26], ~crc[27], ~crc[28], ~crc[29], ~crc[30], ~crc[31]};
						  i<=i+1'b1;
						end
					else begin
					  if(i==1) begin
							dataout[7:0]<={~crc[16], ~crc[17], ~crc[18], ~crc[19], ~crc[20], ~crc[21], ~crc[22], ~crc[23]};
							i<=i+1'b1;
					  end
					  else if(i==2) begin
							dataout[7:0]<={~crc[8], ~crc[9], ~crc[10], ~crc[11], ~crc[12], ~crc[13], ~crc[14], ~crc[15]};
							i<=i+1'b1;
					  end
					  else if(i==3) begin
							dataout[7:0]<={~crc[0], ~crc[1], ~crc[2], ~crc[3], ~crc[4], ~crc[5], ~crc[6], ~crc[7]};
							i<=0;
							tx_state<=idle;
							crc_valid<=1'b0;
					  end
					  else begin
							txer<=1'b1;
					  end
					end
				end					
				default:tx_state<=idle;		
			 endcase	 
     end			 
 end
endmodule