data/full_repos/permissive/197356760/CachCoherency/processor.v
 line:32: before: "("
1: b'%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:8: Cannot find include file: parameter.v\n`include "parameter.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197356760/CachCoherency,data/full_repos/permissive/197356760/parameter.v\n             data/full_repos/permissive/197356760/CachCoherency,data/full_repos/permissive/197356760/parameter.v.v\n             data/full_repos/permissive/197356760/CachCoherency,data/full_repos/permissive/197356760/parameter.v.sv\n             parameter.v\n             parameter.v.v\n             parameter.v.sv\n             obj_dir/parameter.v\n             obj_dir/parameter.v.v\n             obj_dir/parameter.v.sv\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:51: Cannot find include file: parameter.v\n`include "parameter.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:101: Cannot find include file: parameter.v\n`include "parameter.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:137: Cannot find include file: parameter.v\n`include "parameter.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:11: Define or directive not defined: \'`address_rang\'\n output [`address_rang-1:0] address; \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:12: Define or directive not defined: \'`data_siz\'\n input  wire[`data_siz-1:0] data_in;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:15: Define or directive not defined: \'`data_siz\'\n output [`data_siz-1:0] data_out;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:18: Define or directive not defined: \'`address_rang\'\n reg [`address_rang-1:0] temp_address;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:19: Define or directive not defined: \'`data_siz\'\n reg [`data_siz-1:0] temp_data = 1\'b0;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:21: Unsupported: Ignoring delay on this delayed statement.\n initial repeat (1000) #150 temp_read = ~temp_read;\n                       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:22: Unsupported: Ignoring delay on this delayed statement.\n initial repeat (1000) #160 temp_write = ~temp_write;\n                       ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:23: Define or directive not defined: \'`cach_size\'\n initial repeat (1000) #100 temp_address = $random % (`cach_size-1);\n                                                      ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:23: Unsupported: Ignoring delay on this delayed statement.\n initial repeat (1000) #100 temp_address = $random % (`cach_size-1);\n                       ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:24: Define or directive not defined: \'`data_siz\'\n initial repeat (1000) #100 temp_data = $random % (`data_siz-1-1);\n                                                   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:24: Unsupported: Ignoring delay on this delayed statement.\n initial repeat (1000) #100 temp_data = $random % (`data_siz-1-1);\n                       ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:54: Define or directive not defined: \'`address_rang\'\n output [`address_rang-1:0] address; \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:55: Define or directive not defined: \'`data_siz\'\n input  wire[`data_siz-1:0] data_in;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:58: Define or directive not defined: \'`data_siz\'\n output [`data_siz-1:0] data_out;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:63: Define or directive not defined: \'`address_rang\'\n reg [`address_rang-1:0] temp_address1;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:64: Define or directive not defined: \'`data_siz\'\n reg [`data_siz-1:0] temp_data1 = 1\'b0;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:66: Unsupported: Ignoring delay on this delayed statement.\n initial repeat (1000) #500 temp_read1 = ~temp_read1;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:67: Unsupported: Ignoring delay on this delayed statement.\n initial repeat (1000) #510 temp_write1 = ~temp_write1;\n                       ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:68: Define or directive not defined: \'`cach_size\'\n initial repeat (1000) #100 temp_address1 = $random % (`cach_size-1);\n                                                       ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:68: Unsupported: Ignoring delay on this delayed statement.\n initial repeat (1000) #100 temp_address1 = $random % (`cach_size-1);\n                       ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:69: Define or directive not defined: \'`data_siz\'\n initial repeat (1000) #100 temp_data1 = $random % (`data_siz-1-1);\n                                                    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:69: Unsupported: Ignoring delay on this delayed statement.\n initial repeat (1000) #100 temp_data1 = $random % (`data_siz-1-1);\n                       ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:104: Define or directive not defined: \'`address_rang\'\n output reg[`address_rang-1:0] address; \n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:105: Define or directive not defined: \'`data_siz\'\n input  wire[`data_siz-1:0] data_in;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:108: Define or directive not defined: \'`data_siz\'\n output reg[`data_siz-1:0] data_out;\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #750;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #12;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #150;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #12;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #150;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #12;\n  ^\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:140: Define or directive not defined: \'`address_rang\'\n output reg[`address_rang-1:0] address; \n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:141: Define or directive not defined: \'`data_siz\'\n input  wire[`data_siz-1:0] data_in;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197356760/CachCoherency/processor.v:144: Define or directive not defined: \'`data_siz\'\n output reg[`data_siz-1:0] data_out;\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:149: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:152: Unsupported: Ignoring delay on this delayed statement.\n  #12;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:154: Unsupported: Ignoring delay on this delayed statement.\n  #150;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:157: Unsupported: Ignoring delay on this delayed statement.\n  #12;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:159: Unsupported: Ignoring delay on this delayed statement.\n  #150;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197356760/CachCoherency/processor.v:163: Unsupported: Ignoring delay on this delayed statement.\n  #12;\n  ^\n%Error: Exiting due to 24 error(s), 20 warning(s)\n'
module processor2(data_out,data_in,address,write,read,clk);
`include "parameter.v"

	
	output reg[`address_rang-1:0] address; 
	input  wire[`data_siz-1:0] data_in;
	input  clk ;
	output  reg read,write ;
	output reg[`data_siz-1:0] data_out;

	
	initial 
	begin
		read = 1'b0;

		#750;
		read = 1'b1;
		address = 4'b0110;
		#12;
		read = 1'b0;	
		#150;
		read = 1'b1;
		address = 4'b0111;
		#12;
		read = 1'b0;
		#150;		
		address = 4'b1001;
		data_out= 8'b01111000;
		write = 1'b1;
		#12;
		write = 1'b0;
	end
endmodule
module processor2(data_out,data_in,address,write,read,clk);

`include "parameter.v"

	
	output reg[`address_rang-1:0] address; 
	input  wire[`data_siz-1:0] data_in;
	input  clk ;
	output  reg read,write ;
	output reg[`data_siz-1:0] data_out;

	
	initial 
	begin
		read = 1'b0;

		#750;
		read = 1'b1;
		address = 4'b0110;
		#12;
		read = 1'b0;	
		#150;
		read = 1'b1;
		address = 4'b0111;
		#12;
		read = 1'b0;
		#150;		
		address = 4'b1001;
		data_out= 8'b01111000;
		write = 1'b1;
		#12;
		write = 1'b0;
	end
endmodule