data/full_repos/permissive/146246005/RISC-y Processor/RISCY_CPU.sv
 line:3: before: "package"
1: b'%Error: Cannot find file containing module: Processor,data/full_repos/permissive/146246005\n        ... Looked in:\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.v\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.sv\n             Processor,data/full_repos/permissive/146246005\n             Processor,data/full_repos/permissive/146246005.v\n             Processor,data/full_repos/permissive/146246005.sv\n             obj_dir/Processor,data/full_repos/permissive/146246005\n             obj_dir/Processor,data/full_repos/permissive/146246005.v\n             obj_dir/Processor,data/full_repos/permissive/146246005.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/RISC-y\n%Error: Cannot find file containing module: Processor/RISCY_CPU.sv\n%Error: Exiting due to 3 error(s)\n'
module ALU(CLK, EN, OE, OPCODE, A, B, ALU_OUT, CF, OF, SF, ZF);
  parameter WIDTH = 8;
  output reg [ WIDTH-1 : 0] ALU_OUT;
  output reg CF, OF, SF, ZF;
  input [3:0] OPCODE;
  input [ WIDTH-1 : 0] A, B;
  input reg CLK, EN, OE;
  reg [ WIDTH-1 : 0] temp;
  localparam ADDalu = 4'b0010,
             SUBalu = 4'b0011,
             ANDalu = 4'b0100,
             ORalu  = 4'b0101,
             XORalu = 4'b0110,
             NOTalu = 4'b0111;
always @(OE, temp) ALU_OUT = (OE) ? temp : 8'bz;
always @(posedge CLK) begin
  if(EN) begin
    case (OPCODE)
      ADDalu: begin
       temp = A + B;

        if (A+B> 2**WIDTH -1) CF=1;
        else CF=0;

        if (temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;

        if(A>0 && B>0 && temp<0) OF=1;
        else if (A<0 && B<0 && temp>0) OF=1;
        else OF=0;
      end
      SUBalu: begin
       temp = A - B;

        if (A<B) CF=1;
        else CF=0;

        if (temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;

        if(A>0 && B>0 && temp<0) OF=1;
        else if (A<0 && B<0 && temp>0) OF=1;
        else OF=0;
      end
      ANDalu: begin
       temp = A&B;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      ORalu: begin
       temp = A|B;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      XORalu: begin
       temp = A^B;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      NOTalu: begin
       temp = ~A;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      default: temp = 1'bx;
    endcase
  end
end
endmodule
module ALU(CLK, EN, OE, OPCODE, A, B, ALU_OUT, CF, OF, SF, ZF);

  parameter WIDTH = 8;
  output reg [ WIDTH-1 : 0] ALU_OUT;
  output reg CF, OF, SF, ZF;
  input [3:0] OPCODE;
  input [ WIDTH-1 : 0] A, B;
  input reg CLK, EN, OE;
  reg [ WIDTH-1 : 0] temp;
  localparam ADDalu = 4'b0010,
             SUBalu = 4'b0011,
             ANDalu = 4'b0100,
             ORalu  = 4'b0101,
             XORalu = 4'b0110,
             NOTalu = 4'b0111;
always @(OE, temp) ALU_OUT = (OE) ? temp : 8'bz;
always @(posedge CLK) begin
  if(EN) begin
    case (OPCODE)
      ADDalu: begin
       temp = A + B;

        if (A+B> 2**WIDTH -1) CF=1;
        else CF=0;

        if (temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;

        if(A>0 && B>0 && temp<0) OF=1;
        else if (A<0 && B<0 && temp>0) OF=1;
        else OF=0;
      end
      SUBalu: begin
       temp = A - B;

        if (A<B) CF=1;
        else CF=0;

        if (temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;

        if(A>0 && B>0 && temp<0) OF=1;
        else if (A<0 && B<0 && temp>0) OF=1;
        else OF=0;
      end
      ANDalu: begin
       temp = A&B;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      ORalu: begin
       temp = A|B;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      XORalu: begin
       temp = A^B;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      NOTalu: begin
       temp = ~A;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      default: temp = 1'bx;
    endcase
  end
end
endmodule