data/full_repos/permissive/165217789/FusionAccel/deprecated/pool_3x3_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/165217789/FusionAccel/deprecated/pool_3x3_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165217789/FusionAccel/deprecated/pool_3x3_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/165217789/FusionAccel/deprecated/pool_3x3_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #100 pool_ready = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/165217789/FusionAccel/deprecated/pool_3x3_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #310 pool_ready = 0;\n    ^\n%Error: data/full_repos/permissive/165217789/FusionAccel/deprecated/pool_3x3_tb.v:12: Cannot find file containing module: \'pool_3x3\'\npool_3x3 pool_3x3_i(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165217789/FusionAccel/deprecated,data/full_repos/permissive/165217789/pool_3x3\n             data/full_repos/permissive/165217789/FusionAccel/deprecated,data/full_repos/permissive/165217789/pool_3x3.v\n             data/full_repos/permissive/165217789/FusionAccel/deprecated,data/full_repos/permissive/165217789/pool_3x3.sv\n             pool_3x3\n             pool_3x3.v\n             pool_3x3.sv\n             obj_dir/pool_3x3\n             obj_dir/pool_3x3.v\n             obj_dir/pool_3x3.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pool_3x3_tb();

reg [144 - 1:0] im;
reg clk;
reg rst_n;
wire [15:0] om;
reg pool_ready;
wire pool_valid;

pool_3x3 pool_3x3_i(
    .im(im),
    .clk(clk),
    .rst_n(rst_n),
    .om(om),
    .pool_ready(pool_ready),
    .pool_valid(pool_valid)
);
always #5 clk = ~clk;

initial begin
    rst_n = 0;
    clk = 0;
    pool_ready = 0;
    

    im = {16'h4880, 16'h4400, 16'h4600, 16'h4880, 16'h4200, 16'h4700, 16'h3c00, 16'h4000, 16'h4500};
    #10 rst_n = 1;
    #100 pool_ready = 1;
    #310 pool_ready = 0;
end

endmodule
module pool_3x3_tb();


reg [144 - 1:0] im;
reg clk;
reg rst_n;
wire [15:0] om;
reg pool_ready;
wire pool_valid;

pool_3x3 pool_3x3_i(
    .im(im),
    .clk(clk),
    .rst_n(rst_n),
    .om(om),
    .pool_ready(pool_ready),
    .pool_valid(pool_valid)
);
always #5 clk = ~clk;

initial begin
    rst_n = 0;
    clk = 0;
    pool_ready = 0;
    

    im = {16'h4880, 16'h4400, 16'h4600, 16'h4880, 16'h4200, 16'h4700, 16'h3c00, 16'h4000, 16'h4500};
    #10 rst_n = 1;
    #100 pool_ready = 1;
    #310 pool_ready = 0;
end

endmodule