data/full_repos/permissive/174783592/FloatAdd/Adder/kpgGen.v
data/verilator_xmls/7c995723-9a17-4b93-a6e0-a4d8c3227532.xml
module kpgGen(a, b, out);
    input a;
    input b;
	 wire w1, w2;
	 output [1:0] out;
	 
	 xor(w1,a,b);
	 and(w2,a,b);
	 














	assign out[1] = w1;
	assign out[0] = ~w1 & w2;
	 endmodule
module kpgGen(a, b, out);

    input a;
    input b;
	 wire w1, w2;
	 output [1:0] out;
	 
	 xor(w1,a,b);
	 and(w2,a,b);
	 














	assign out[1] = w1;
	assign out[0] = ~w1 & w2;
	 endmodule