data/full_repos/permissive/214823094/submissions/lab_6/project_1/traffic_lights_1.v
 line:81: before: "begin"
data/verilator_xmls/ee4f87ae-baf2-40c8-8c6e-03264beae870.xml
module traffic_lights_1(
    input clk,
    input reset,
    output reg [2:0] N,
    output reg [2:0] S,
    output reg [2:0] E,
    output reg [2:0] W
    );
    
    wire myclk;
    reg [5:0] counter;
    clkdiv c1(clk,myclk);
    
    always@(posedge myclk, posedge reset)
    begin
    if(reset)
    begin
    N<=3'b001;
    S<=3'b001;
    E<=3'b100;
    W<=3'b100;
    end
    else
    begin
        case(counter)
        6'b001001:
            begin
            N<=3'b010;
            S<=3'b010;
            E<=3'b100;
            W<=3'b100;
            counter<=counter+1;
            end
        6'b001100:
            begin
            N<=3'b100;
            S<=3'b100;
            E<=3'b001;
            W<=3'b001;
            counter<=counter+1;
            end
         6'b011101:
            begin
            N<=3'b100;
            S<=3'b100;
            E<=3'b010;
            W<=3'b010;
            counter<=counter+1;
            end
         6'b100000:
            begin
            N<=3'b001;
            S<=3'b001;
            E<=3'b100;
            W<=3'b100;
            counter<=6'b000000;
            end
        default
            begin
            N<=N;
            S<=S;
            E<=E;
            W<=W;
            counter<=counter+1;
            end
        endcase
    end
    end
    
endmodule
module traffic_lights_1(
    input clk,
    input reset,
    output reg [2:0] N,
    output reg [2:0] S,
    output reg [2:0] E,
    output reg [2:0] W
    );

    
    wire myclk;
    reg [5:0] counter;
    clkdiv c1(clk,myclk);
    
    always@(posedge myclk, posedge reset)
    begin
    if(reset)
    begin
    N<=3'b001;
    S<=3'b001;
    E<=3'b100;
    W<=3'b100;
    end
    else
    begin
        case(counter)
        6'b001001:
            begin
            N<=3'b010;
            S<=3'b010;
            E<=3'b100;
            W<=3'b100;
            counter<=counter+1;
            end
        6'b001100:
            begin
            N<=3'b100;
            S<=3'b100;
            E<=3'b001;
            W<=3'b001;
            counter<=counter+1;
            end
         6'b011101:
            begin
            N<=3'b100;
            S<=3'b100;
            E<=3'b010;
            W<=3'b010;
            counter<=counter+1;
            end
         6'b100000:
            begin
            N<=3'b001;
            S<=3'b001;
            E<=3'b100;
            W<=3'b100;
            counter<=6'b000000;
            end
        default
            begin
            N<=N;
            S<=S;
            E<=E;
            W<=W;
            counter<=counter+1;
            end
        endcase
    end
    end
    
endmodule