data/full_repos/permissive/106330868/verilog/pwmdac/pwmdac.v
1: b'%Warning-WIDTH: data/full_repos/permissive/106330868/verilog/pwmdac/pwmdac.v:61: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'data\' generates 8 bits.\n                                                                               : ... In instance PWMDAC\n    assign sum1 = $signed({data[7] ,{data, 2\'b00}}) + data   - $signed({last_data, 2\'b00});\n                                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/106330868/verilog/pwmdac/pwmdac.v:69: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                               : ... In instance PWMDAC\n            quantdata = sum1[10] ?  8\'h80 : 8\'h7F;\n                      ^\n%Error: Exiting due to 2 warning(s)\n'
module PWMDAC (
        clk, 
        rst_an, 
        din,
        din_ack,
        dacout
    );


	input clk;


    input rst_an;


	output reg dacout;


	input signed [7:0] din;
    output reg din_ack;


    reg signed [7:0] counter;
    reg signed [7:0] data;


    reg signed [7:0]   last_data;
    wire signed [10:0] sum1;




    reg signed [6:0]  quantdata;

    assign sum1 = $signed({data[7] ,{data, 2'b00}}) + data   - $signed({last_data, 2'b00});


    always @(*)
    begin        
        if (sum1[10] ^ sum1[9] != 0)
        begin

            quantdata = sum1[10] ?  8'h80 : 8'h7F;
        end
        else 
            quantdata = sum1[9:3];
    end

    always @(posedge clk, negedge rst_an)
    begin
        if (rst_an == 0)
        begin

            counter <= 0;
            dacout  <= 0;
            din_ack <= 0;
            data    <= 0;
        end
        else
        begin

            counter <= counter + 8'b00000001;








            `ifdef USE_PREFILTER
                if (quantdata > $signed(counter[6:0]))
                    dacout <= 1;
                else
                    dacout <= 0;
            `else
                if ($signed(data[7:1]) > $signed(counter[6:0]))
                    dacout <= 1;
                else
                    dacout <= 0;            
            `endif



            if (counter == 8'h7F)
            begin
                last_data <= data;
                data <= din;
                din_ack <= 1;        
            end
            else
                din_ack <= 0;            
        end
    end
endmodule
module PWMDAC (
        clk, 
        rst_an, 
        din,
        din_ack,
        dacout
    );



	input clk;


    input rst_an;


	output reg dacout;


	input signed [7:0] din;
    output reg din_ack;


    reg signed [7:0] counter;
    reg signed [7:0] data;


    reg signed [7:0]   last_data;
    wire signed [10:0] sum1;




    reg signed [6:0]  quantdata;

    assign sum1 = $signed({data[7] ,{data, 2'b00}}) + data   - $signed({last_data, 2'b00});


    always @(*)
    begin        
        if (sum1[10] ^ sum1[9] != 0)
        begin

            quantdata = sum1[10] ?  8'h80 : 8'h7F;
        end
        else 
            quantdata = sum1[9:3];
    end

    always @(posedge clk, negedge rst_an)
    begin
        if (rst_an == 0)
        begin

            counter <= 0;
            dacout  <= 0;
            din_ack <= 0;
            data    <= 0;
        end
        else
        begin

            counter <= counter + 8'b00000001;








            `ifdef USE_PREFILTER
                if (quantdata > $signed(counter[6:0]))
                    dacout <= 1;
                else
                    dacout <= 0;
            `else
                if ($signed(data[7:1]) > $signed(counter[6:0]))
                    dacout <= 1;
                else
                    dacout <= 0;            
            `endif



            if (counter == 8'h7F)
            begin
                last_data <= data;
                data <= din;
                din_ack <= 1;        
            end
            else
                din_ack <= 0;            
        end
    end
endmodule