data/full_repos/permissive/157135695/lab4iram1G.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/8ef3b40c-e3dd-4ebb-8a77-8d9bc532e0d8.xml
module lab4iram1G(CLK, RESET, ADDR, Q);
  input         CLK;
  input         RESET;
  input  [7:0]  ADDR;
  output [15:0] Q;

  reg    [15:0] mem[0:127];

  wire   [6:0]  saddr;
  integer       i;


  assign saddr = ADDR[7:1];
  assign Q = mem[saddr];

  always @(posedge CLK) begin
    if(RESET) begin
      mem[0]   <= 16'b1111010010010001;
      mem[1]   <= 16'b1111001001001001;
      mem[2]   <= 16'b0101010010111111;
      mem[3]   <= 16'b0100010001000000;
      mem[4]   <= 16'b0101001001000001;
      mem[5]   <= 16'b0100010001000000;
      mem[6]   <= 16'b0101001001000001;
      mem[7]   <= 16'b0100010001000000;
      mem[8]   <= 16'b0101001001000001;
      mem[9]   <= 16'b0100010001000000;
      mem[10]  <= 16'b0101001001000001;
      mem[11]  <= 16'b0100010001000000;
      mem[12]  <= 16'b0101001001000001;
      mem[13]  <= 16'b0100010001000000;
      mem[14]  <= 16'b1111011011011001;
      mem[15]  <= 16'b0101011011000001;
      mem[16]  <= 16'b1111001011001000;
      mem[17]  <= 16'b0100010001000000;
      mem[18]  <= 16'b1111011001001110;
      mem[19]  <= 16'b0100010001000000;
      mem[20]  <= 16'b0101011001000000;
      mem[21]  <= 16'b1111001000001100;
      mem[22]  <= 16'b1111001000001100;
      mem[23]  <= 16'b1111001000001100;
      mem[24]  <= 16'b0100010001000000;
      mem[25]  <= 16'b0111001001000001;
      mem[26]  <= 16'b0100010001000000;
      mem[27]  <= 16'b0100011001000000;
      mem[28]  <= 16'b1111011011011001;
      mem[29]  <= 16'b0010011011000001;
      mem[30]  <= 16'b0101011001000001;
      mem[31]  <= 16'b0100010001000000;
      mem[32]  <= 16'b1111001000001100;
      mem[33]  <= 16'b1111001000001100;
      mem[34]  <= 16'b0101001001101110;
      mem[35]  <= 16'b1111001000001011;
      mem[36]  <= 16'b0100010001000000;
      mem[37]  <= 16'b0000000000000000;
      mem[38]  <= 16'b0000000000000000;
      mem[39]  <= 16'b0101001001000001;
      mem[40]  <= 16'b1111010000010010;
      mem[41]  <= 16'b0100010001000000;
      mem[42]  <= 16'b0110010100011010;
      mem[43]  <= 16'b1111100000100010;
      mem[44]  <= 16'b0100010100000000;
      mem[45]  <= 16'b0101011111111110;
      mem[46]  <= 16'b1111111010000101;
      mem[47]  <= 16'b1111000000101000;
      mem[48]  <= 16'b0100010101000000;

      for(i = 49; i < 128; i = i + 1) begin
        mem[i] <= 16'b0000000000000000;
      end
    end
  end

endmodule
module lab4iram1G(CLK, RESET, ADDR, Q);

  input         CLK;
  input         RESET;
  input  [7:0]  ADDR;
  output [15:0] Q;

  reg    [15:0] mem[0:127];

  wire   [6:0]  saddr;
  integer       i;


  assign saddr = ADDR[7:1];
  assign Q = mem[saddr];

  always @(posedge CLK) begin
    if(RESET) begin
      mem[0]   <= 16'b1111010010010001;
      mem[1]   <= 16'b1111001001001001;
      mem[2]   <= 16'b0101010010111111;
      mem[3]   <= 16'b0100010001000000;
      mem[4]   <= 16'b0101001001000001;
      mem[5]   <= 16'b0100010001000000;
      mem[6]   <= 16'b0101001001000001;
      mem[7]   <= 16'b0100010001000000;
      mem[8]   <= 16'b0101001001000001;
      mem[9]   <= 16'b0100010001000000;
      mem[10]  <= 16'b0101001001000001;
      mem[11]  <= 16'b0100010001000000;
      mem[12]  <= 16'b0101001001000001;
      mem[13]  <= 16'b0100010001000000;
      mem[14]  <= 16'b1111011011011001;
      mem[15]  <= 16'b0101011011000001;
      mem[16]  <= 16'b1111001011001000;
      mem[17]  <= 16'b0100010001000000;
      mem[18]  <= 16'b1111011001001110;
      mem[19]  <= 16'b0100010001000000;
      mem[20]  <= 16'b0101011001000000;
      mem[21]  <= 16'b1111001000001100;
      mem[22]  <= 16'b1111001000001100;
      mem[23]  <= 16'b1111001000001100;
      mem[24]  <= 16'b0100010001000000;
      mem[25]  <= 16'b0111001001000001;
      mem[26]  <= 16'b0100010001000000;
      mem[27]  <= 16'b0100011001000000;
      mem[28]  <= 16'b1111011011011001;
      mem[29]  <= 16'b0010011011000001;
      mem[30]  <= 16'b0101011001000001;
      mem[31]  <= 16'b0100010001000000;
      mem[32]  <= 16'b1111001000001100;
      mem[33]  <= 16'b1111001000001100;
      mem[34]  <= 16'b0101001001101110;
      mem[35]  <= 16'b1111001000001011;
      mem[36]  <= 16'b0100010001000000;
      mem[37]  <= 16'b0000000000000000;
      mem[38]  <= 16'b0000000000000000;
      mem[39]  <= 16'b0101001001000001;
      mem[40]  <= 16'b1111010000010010;
      mem[41]  <= 16'b0100010001000000;
      mem[42]  <= 16'b0110010100011010;
      mem[43]  <= 16'b1111100000100010;
      mem[44]  <= 16'b0100010100000000;
      mem[45]  <= 16'b0101011111111110;
      mem[46]  <= 16'b1111111010000101;
      mem[47]  <= 16'b1111000000101000;
      mem[48]  <= 16'b0100010101000000;

      for(i = 49; i < 128; i = i + 1) begin
        mem[i] <= 16'b0000000000000000;
      end
    end
  end

endmodule