data/full_repos/permissive/114642806/main/fsm.v
data/verilator_xmls/8216b74a-c713-42da-893a-45763aa7c526.xml
module counter01(clock, enable_next);

input clock;
output enable_next;

reg [25:0] count = 26'b0;
assign enable_next = (count == 26'd50000000) ? 1'b1 : 1'b0;






always @(posedge clock)
	begin
	if (enable_next == 1'b1)
		begin
			count <= 0;
		end
	else
		begin
			count <= count + 1'b1;
		end
	end
endmodule
module counter01(clock, enable_next);


input clock;
output enable_next;

reg [25:0] count = 26'b0;
assign enable_next = (count == 26'd50000000) ? 1'b1 : 1'b0;






always @(posedge clock)
	begin
	if (enable_next == 1'b1)
		begin
			count <= 0;
		end
	else
		begin
			count <= count + 1'b1;
		end
	end
endmodule