data/full_repos/permissive/208113388/tlx/dram_syn_test.v
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data/verilator_xmls/97680577-10b4-4a5e-9e7d-b5723570c633.xml
module dram_syn_test(a, dpra, clk, din, we, qdpo_ce, qdpo, reset_n);

	parameter ADDRESSWIDTH = 6;
	parameter BITWIDTH     = 1;
	parameter DEPTH       = 34;

	input clk, we, qdpo_ce;
	input reset_n;
	input [BITWIDTH-1:0] din;
	input [ADDRESSWIDTH-1:0] a, dpra;

	output [BITWIDTH-1:0] qdpo;

	(* ram_style = "distributed", ARRAY_UPDATE="RW"*)
	reg [BITWIDTH-1:0] ram [DEPTH-1:0];
	reg [BITWIDTH-1:0] qdpo_reg;

	always @(posedge clk) begin
		if      (we)           begin    ram [a] <= din;    end

		if      (!reset_n)     begin    qdpo_reg <= {BITWIDTH{1'b0}};  end
		else if (qdpo_ce)      begin    qdpo_reg <= ram[dpra];         end
	end

	assign qdpo = qdpo_reg;

endmodule
module dram_syn_test(a, dpra, clk, din, we, qdpo_ce, qdpo, reset_n);


	parameter ADDRESSWIDTH = 6;
	parameter BITWIDTH     = 1;
	parameter DEPTH       = 34;

	input clk, we, qdpo_ce;
	input reset_n;
	input [BITWIDTH-1:0] din;
	input [ADDRESSWIDTH-1:0] a, dpra;

	output [BITWIDTH-1:0] qdpo;

	(* ram_style = "distributed", ARRAY_UPDATE="RW"*)
	reg [BITWIDTH-1:0] ram [DEPTH-1:0];
	reg [BITWIDTH-1:0] qdpo_reg;

	always @(posedge clk) begin
		if      (we)           begin    ram [a] <= din;    end

		if      (!reset_n)     begin    qdpo_reg <= {BITWIDTH{1'b0}};  end
		else if (qdpo_ce)      begin    qdpo_reg <= ram[dpra];         end
	end

	assign qdpo = qdpo_reg;

endmodule