data/full_repos/permissive/120142431/step.v
data/verilator_xmls/5e499ae5-16e9-4a26-9523-b1e498c0205a.xml
module step(clk, step, rst);

input clk;

input rst;

output reg [1:0] step;

always @ (posedge clk)
begin
	if(rst)
		begin
			step <= 0;
		end
	else
		begin
			step <= #1 step + 1;
		end
end

endmodule
module step(clk, step, rst);


input clk;

input rst;

output reg [1:0] step;

always @ (posedge clk)
begin
	if(rst)
		begin
			step <= 0;
		end
	else
		begin
			step <= #1 step + 1;
		end
end

endmodule