data/full_repos/permissive/143278/ivltests/pr1455873.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1455873.v:8: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (foo !== 32\'h00_00_00_7f) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [6:0] bar;
   wire [31:0] foo = {{25{1'b0}}, bar};

   initial begin
      bar = 7'b1111111;
      #1 if (foo !== 32'h00_00_00_7f) begin
	 $display("FAILED -- foo=%h", foo);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg [6:0] bar;
   wire [31:0] foo = {{25{1'b0}}, bar};

   initial begin
      bar = 7'b1111111;
      #1 if (foo !== 32'h00_00_00_7f) begin
	 $display("FAILED -- foo=%h", foo);
	 $finish;
      end

      $display("PASSED");
   end

endmodule