data/full_repos/permissive/220281533/ALU32bit.v
1: b'%Error: data/full_repos/permissive/220281533/ALU32bit.v:200: Unsupported or unknown PLI call: $monitor\n  $monitor("opcode: %6b, Rs content: %32b, rt content: %32b, signExtendImm = %32b, result: %32b\\n",\n  ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU32bit(ALU_result, sig_branch, opcode, rs_content, rt_content, shamt, ALU_control, immediate);
	
	input [5:0] ALU_control, opcode;
	input [4:0] shamt;
	input [15:0] immediate;
	input [31:0] rs_content, rt_content;
	
	output reg sig_branch;
	output reg [31:0] ALU_result;
	
	integer i;

	reg signed [31:0] temp, signed_rs, signed_rt; 
	reg [31:0] signExtend, zeroExtend;

	always @ (ALU_control, rs_content, rt_content, shamt, immediate) begin
		
		

		signed_rs = rs_content;
		signed_rt = rt_content;
			
			

		if(opcode == 6'h0) begin
			
			case(ALU_control)
			
				6'h20 :
					ALU_result = signed_rs + signed_rt;
				
				6'h21 :
					ALU_result = rs_content + rt_content;
					
				6'h22 :
					ALU_result = signed_rs - signed_rt;
					
				6'h23 :
					ALU_result = rs_content - rt_content;
					
				6'h24 :
					ALU_result = rs_content & rt_content;
					
				6'h25 :
					ALU_result = rs_content | rt_content;
					
				6'h27 :
					ALU_result = ~(rs_content | rt_content);
					
				6'h03 :
					begin
						temp = rt_content;
						for(i = 0; i < shamt; i = i + 1) begin
							temp = {temp[31],temp[31:1]};
						end
					
					ALU_result = temp;
					end
					
				6'h02 :
					ALU_result = (rt_content >> shamt);
			
				6'h00 :
					ALU_result = (rt_content << shamt);
				
				6'h2b :
					begin
						if(rs_content < rt_content) begin
							ALU_result = 1;
						end else begin
							ALU_result = 0;
						end
					end
					
				6'h2a :
					begin
						if(signed_rs < signed_rt) begin
							ALU_result = 1;
						end else begin
							ALU_result = 0;
						end
					end
			
			endcase
			
		end
		
		
		

		else begin
			
			signExtend = {{16{immediate[15]}}, immediate};
			zeroExtend = {{16{1'b0}}, immediate};
			
			case(opcode)
		
				6'h8 :
					ALU_result = signed_rs + signExtend;
					
				6'h9 :
					ALU_result = rs_content + signExtend;
					
				6'b010010 :
					ALU_result = rs_content & zeroExtend;
					
				6'h4 :
					begin

						ALU_result = signed_rs - signed_rt;
						if(ALU_result == 0) begin
							sig_branch = 1'b1;
						end
						else begin
							sig_branch = 1'b0;
						end
					end
				
				6'h5 :
					begin

						ALU_result = signed_rs - signed_rt;
						if(ALU_result != 0) begin
							sig_branch = 1'b1;
							ALU_result = 1'b0;
						end
						else begin
							sig_branch = 1'b0;
						end
					end
				
				6'b010101 :
					ALU_result = {immediate, {16{1'b0}}};
				
				6'b010011 :
					ALU_result = rs_content | zeroExtend;
				
				6'b001010 :
					begin
						if(signed_rs < $signed(signExtend)) begin
							ALU_result = 1;
						end else begin
							ALU_result = 0;
						end
					end
				
				6'b001011 :
					begin
						if(rs_content < signExtend) begin
							ALU_result = 1;
						end else begin
							ALU_result = 0;
						end
					end
				6'h28 :
					ALU_result = signed_rs + signExtend;
				6'h29 :
					ALU_result = signed_rs + signExtend;
				6'h2b :
					ALU_result = signed_rs + signExtend;
				6'h23 :
					ALU_result = signed_rs + signExtend;
				6'h24 :
					ALU_result = signed_rs + signExtend;
				6'h25 :
					ALU_result = signed_rs + signExtend;
				6'h30 :
					ALU_result = signed_rs + signExtend;
				
			endcase
		
		end
	$write("ALU output in ALU is = %d",ALU_result);	
	end
	
	
	initial begin
		$monitor("opcode: %6b, Rs content: %32b, rt content: %32b, signExtendImm = %32b, result: %32b\n",
		opcode, rs_content, rt_content, signExtend, ALU_result);
	end
	
endmodule
module ALU32bit(ALU_result, sig_branch, opcode, rs_content, rt_content, shamt, ALU_control, immediate);

	
	input [5:0] ALU_control, opcode;
	input [4:0] shamt;
	input [15:0] immediate;
	input [31:0] rs_content, rt_content;
	
	output reg sig_branch;
	output reg [31:0] ALU_result;
	
	integer i;

	reg signed [31:0] temp, signed_rs, signed_rt; 
	reg [31:0] signExtend, zeroExtend;

	always @ (ALU_control, rs_content, rt_content, shamt, immediate) begin
		
		

		signed_rs = rs_content;
		signed_rt = rt_content;
			
			

		if(opcode == 6'h0) begin
			
			case(ALU_control)
			
				6'h20 :
					ALU_result = signed_rs + signed_rt;
				
				6'h21 :
					ALU_result = rs_content + rt_content;
					
				6'h22 :
					ALU_result = signed_rs - signed_rt;
					
				6'h23 :
					ALU_result = rs_content - rt_content;
					
				6'h24 :
					ALU_result = rs_content & rt_content;
					
				6'h25 :
					ALU_result = rs_content | rt_content;
					
				6'h27 :
					ALU_result = ~(rs_content | rt_content);
					
				6'h03 :
					begin
						temp = rt_content;
						for(i = 0; i < shamt; i = i + 1) begin
							temp = {temp[31],temp[31:1]};
						end
					
					ALU_result = temp;
					end
					
				6'h02 :
					ALU_result = (rt_content >> shamt);
			
				6'h00 :
					ALU_result = (rt_content << shamt);
				
				6'h2b :
					begin
						if(rs_content < rt_content) begin
							ALU_result = 1;
						end else begin
							ALU_result = 0;
						end
					end
					
				6'h2a :
					begin
						if(signed_rs < signed_rt) begin
							ALU_result = 1;
						end else begin
							ALU_result = 0;
						end
					end
			
			endcase
			
		end
		
		
		

		else begin
			
			signExtend = {{16{immediate[15]}}, immediate};
			zeroExtend = {{16{1'b0}}, immediate};
			
			case(opcode)
		
				6'h8 :
					ALU_result = signed_rs + signExtend;
					
				6'h9 :
					ALU_result = rs_content + signExtend;
					
				6'b010010 :
					ALU_result = rs_content & zeroExtend;
					
				6'h4 :
					begin

						ALU_result = signed_rs - signed_rt;
						if(ALU_result == 0) begin
							sig_branch = 1'b1;
						end
						else begin
							sig_branch = 1'b0;
						end
					end
				
				6'h5 :
					begin

						ALU_result = signed_rs - signed_rt;
						if(ALU_result != 0) begin
							sig_branch = 1'b1;
							ALU_result = 1'b0;
						end
						else begin
							sig_branch = 1'b0;
						end
					end
				
				6'b010101 :
					ALU_result = {immediate, {16{1'b0}}};
				
				6'b010011 :
					ALU_result = rs_content | zeroExtend;
				
				6'b001010 :
					begin
						if(signed_rs < $signed(signExtend)) begin
							ALU_result = 1;
						end else begin
							ALU_result = 0;
						end
					end
				
				6'b001011 :
					begin
						if(rs_content < signExtend) begin
							ALU_result = 1;
						end else begin
							ALU_result = 0;
						end
					end
				6'h28 :
					ALU_result = signed_rs + signExtend;
				6'h29 :
					ALU_result = signed_rs + signExtend;
				6'h2b :
					ALU_result = signed_rs + signExtend;
				6'h23 :
					ALU_result = signed_rs + signExtend;
				6'h24 :
					ALU_result = signed_rs + signExtend;
				6'h25 :
					ALU_result = signed_rs + signExtend;
				6'h30 :
					ALU_result = signed_rs + signExtend;
				
			endcase
		
		end
	$write("ALU output in ALU is = %d",ALU_result);	
	end
	
	
	initial begin
		$monitor("opcode: %6b, Rs content: %32b, rt content: %32b, signExtendImm = %32b, result: %32b\n",
		opcode, rs_content, rt_content, signExtend, ALU_result);
	end
	
endmodule