data/full_repos/permissive/195227969/work/hwtst/div/m_digilent.v
 line:55 column:25: Illegal character "'"
1: b'%Error: data/full_repos/permissive/195227969/work/hwtst/div/m_digilent.v:55: Cannot find file containing module: \'SB_IO\'\n   SB_IO #( .PIN_TYPE(6\'b 0000_01)) the_nDATASTB( .PACKAGE_PIN( padnDATASTB ),.D_IN_0(nDATASTB) );\n   ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/195227969/work/hwtst/div,data/full_repos/permissive/195227969/SB_IO\n             data/full_repos/permissive/195227969/work/hwtst/div,data/full_repos/permissive/195227969/SB_IO.v\n             data/full_repos/permissive/195227969/work/hwtst/div,data/full_repos/permissive/195227969/SB_IO.sv\n             SB_IO\n             SB_IO.v\n             SB_IO.sv\n             obj_dir/SB_IO\n             obj_dir/SB_IO.v\n             obj_dir/SB_IO.sv\n%Error: data/full_repos/permissive/195227969/work/hwtst/div/m_digilent.v:56: Cannot find file containing module: \'SB_IO\'\n   SB_IO #( .PIN_TYPE(6\'b 0000_01)) the_nADDRSTB( .PACKAGE_PIN( padnADDRSTB ),.D_IN_0(nADDRSTB) );\n   ^~~~~\n%Error: data/full_repos/permissive/195227969/work/hwtst/div/m_digilent.v:76: Cannot find file containing module: \'SB_IO\'\n   SB_IO #( .PIN_TYPE( 6\'b 1010_01), .NEG_TRIGGER(1\'b1))\n   ^~~~~\n%Error: data/full_repos/permissive/195227969/work/hwtst/div/m_digilent.v:93: Cannot find file containing module: \'SB_IO\'\n   SB_IO #( .PIN_TYPE( 6\'b 0110_00), .NEG_TRIGGER(1\'b1))\n   ^~~~~\n%Error: data/full_repos/permissive/195227969/work/hwtst/div/m_digilent.v:95: Cannot find file containing module: \'SB_IO\'\n   SB_IO #( .PIN_TYPE( 6\'b 0000_01), .NEG_TRIGGER(1\'b1))\n   ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/195227969/work/hwtst/div/m_digilent.v:143: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s REPLICATE generates 7 bits.\n                                                                                    : ... In instance m_digilent\n   assign DAT_O = ADR_I[0] ? {data[7:3], rxbuff_full,txbuff_full} : data;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module m_digilent
  (
   input        CLK_I,
   input [7:0]  DAT_I,
   input [0:0]  ADR_I,
   input        STB_I,
   input        WE_I,
   output [7:0] DAT_O,
   output       ACK_O,
   
   input        padnADDRSTB,
   input        padnDATASTB,
   input        padnWRITE,
   inout [7:0]  padDB,
   output       padnWAIT
   );



   wire         nDATASTB,nADDRSTB;
   SB_IO #( .PIN_TYPE(6'b 0000_01)) the_nDATASTB( .PACKAGE_PIN( padnDATASTB ),.D_IN_0(nDATASTB) );
   SB_IO #( .PIN_TYPE(6'b 0000_01)) the_nADDRSTB( .PACKAGE_PIN( padnADDRSTB ),.D_IN_0(nADDRSTB) );
   

  

   wire [7:0]   data;
   wire [7:0]   theout;
   wire [7:0]   in;
   reg [0:0]    adr;
   wire         nWRITEsig;
   wire         sampledata = nADDRSTB & ~nWRITEsig;

   SB_IO #( .PIN_TYPE( 6'b 1010_01), .NEG_TRIGGER(1'b1))
   theio [7:0] ( .PACKAGE_PIN(       padDB        ),
                 .INPUT_CLK(         nDATASTB     ),
                 .CLOCK_ENABLE(      sampledata   ),
                 .D_OUT_0(           theout       ),
                 .D_IN_0(            in           ),
                 .D_IN_1(            data         ),
                 .OUTPUT_ENABLE(     nWRITEsig    )
                 );


   wire         cmb_nWAIT = !(nADDRSTB & nDATASTB);
   SB_IO #( .PIN_TYPE( 6'b 0110_00), .NEG_TRIGGER(1'b1))
   the_nWAIT ( .PACKAGE_PIN( padnWAIT ),.D_OUT_0( cmb_nWAIT ));
   SB_IO #( .PIN_TYPE( 6'b 0000_01), .NEG_TRIGGER(1'b1))
   the_nWRITE( .PACKAGE_PIN( padnWRITE),.D_IN_0( nWRITEsig ));
  
   always @(posedge nADDRSTB)
     if ( ~nWRITEsig )
       adr[0] <= in[0];


   reg          nrPCdatawritten,nrPCdataread;
   always @(posedge nDATASTB)
     if ( sampledata )
       nrPCdatawritten <= ~nrPCdatawritten;
     else if ( adr[0] == 1'b0 )
       nrPCdataread <= ~nrPCdataread;

   assign theout = adr[0] ? {txreg[7:2],rxbuff_full,txbuff_full} : txreg;


   wire         rxbuff_full = nrPCdatawritten ^ nrFPGAdataread;
   wire         txbuff_full = nrFPGAdatawritten ^ nrPCdataread;
   

   reg          nrFPGAdatawritten,nrFPGAdataread;
   reg [7:0]    txreg;
   
   always @(posedge CLK_I ) 
     if ( STB_I & WE_I & ~ADR_I[0] ) begin
        txreg <= DAT_I;
        nrFPGAdatawritten <= ~nrFPGAdatawritten;
     end
   
   always @(posedge CLK_I ) begin
      if ( STB_I & ~WE_I & ~ADR_I[0] )
        nrFPGAdataread <= ~nrFPGAdataread;
   end
   
   assign DAT_O = ADR_I[0] ? {data[7:3], rxbuff_full,txbuff_full} : data;
   assign ACK_O = STB_I;
   
endmodule
module m_digilent
  (
   input        CLK_I,
   input [7:0]  DAT_I,
   input [0:0]  ADR_I,
   input        STB_I,
   input        WE_I,
   output [7:0] DAT_O,
   output       ACK_O,
   
   input        padnADDRSTB,
   input        padnDATASTB,
   input        padnWRITE,
   inout [7:0]  padDB,
   output       padnWAIT
   );




   wire         nDATASTB,nADDRSTB;
   SB_IO #( .PIN_TYPE(6'b 0000_01)) the_nDATASTB( .PACKAGE_PIN( padnDATASTB ),.D_IN_0(nDATASTB) );
   SB_IO #( .PIN_TYPE(6'b 0000_01)) the_nADDRSTB( .PACKAGE_PIN( padnADDRSTB ),.D_IN_0(nADDRSTB) );
   

  

   wire [7:0]   data;
   wire [7:0]   theout;
   wire [7:0]   in;
   reg [0:0]    adr;
   wire         nWRITEsig;
   wire         sampledata = nADDRSTB & ~nWRITEsig;

   SB_IO #( .PIN_TYPE( 6'b 1010_01), .NEG_TRIGGER(1'b1))
   theio [7:0] ( .PACKAGE_PIN(       padDB        ),
                 .INPUT_CLK(         nDATASTB     ),
                 .CLOCK_ENABLE(      sampledata   ),
                 .D_OUT_0(           theout       ),
                 .D_IN_0(            in           ),
                 .D_IN_1(            data         ),
                 .OUTPUT_ENABLE(     nWRITEsig    )
                 );


   wire         cmb_nWAIT = !(nADDRSTB & nDATASTB);
   SB_IO #( .PIN_TYPE( 6'b 0110_00), .NEG_TRIGGER(1'b1))
   the_nWAIT ( .PACKAGE_PIN( padnWAIT ),.D_OUT_0( cmb_nWAIT ));
   SB_IO #( .PIN_TYPE( 6'b 0000_01), .NEG_TRIGGER(1'b1))
   the_nWRITE( .PACKAGE_PIN( padnWRITE),.D_IN_0( nWRITEsig ));
  
   always @(posedge nADDRSTB)
     if ( ~nWRITEsig )
       adr[0] <= in[0];


   reg          nrPCdatawritten,nrPCdataread;
   always @(posedge nDATASTB)
     if ( sampledata )
       nrPCdatawritten <= ~nrPCdatawritten;
     else if ( adr[0] == 1'b0 )
       nrPCdataread <= ~nrPCdataread;

   assign theout = adr[0] ? {txreg[7:2],rxbuff_full,txbuff_full} : txreg;


   wire         rxbuff_full = nrPCdatawritten ^ nrFPGAdataread;
   wire         txbuff_full = nrFPGAdatawritten ^ nrPCdataread;
   

   reg          nrFPGAdatawritten,nrFPGAdataread;
   reg [7:0]    txreg;
   
   always @(posedge CLK_I ) 
     if ( STB_I & WE_I & ~ADR_I[0] ) begin
        txreg <= DAT_I;
        nrFPGAdatawritten <= ~nrFPGAdatawritten;
     end
   
   always @(posedge CLK_I ) begin
      if ( STB_I & ~WE_I & ~ADR_I[0] )
        nrFPGAdataread <= ~nrFPGAdataread;
   end
   
   assign DAT_O = ADR_I[0] ? {data[7:3], rxbuff_full,txbuff_full} : data;
   assign ACK_O = STB_I;
   
endmodule