data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/aib.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/aib.v:11: Little bit endian vector: MSB < LSB of bit range: 0:79\n inout[0:79] PAD,\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/aib.v:12: Little bit endian vector: MSB < LSB of bit range: 0:79\n input[0:79] TX_DATA,\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/aib.v:13: Little bit endian vector: MSB < LSB of bit range: 0:79\n output[0:79] RX_DATA);\n       ^\n%Error: Exiting due to 3 warning(s)\n'
module AIB (
	input TX_CLK,
	input RX_CLK,
	inout[0:79] PAD,
	input[0:79] TX_DATA,
	output[0:79] RX_DATA);





endmodule
module AIB (
	input TX_CLK,
	input RX_CLK,
	inout[0:79] PAD,
	input[0:79] TX_DATA,
	output[0:79] RX_DATA);






endmodule