data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_wb_master.v
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_wb_master.v:95: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl,data/full_repos/permissive/137416811/timescale.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl,data/full_repos/permissive/137416811/timescale.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl,data/full_repos/permissive/137416811/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n'
module vga_wb_master (clk_i, rst_i, nrst_i,
	cyc_o, stb_o, cti_o, bte_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,
	ctrl_ven, ctrl_cd, ctrl_vbl, ctrl_vbsw, busy,
	VBAa, VBAb, Thgate, Tvgate,
	stat_avmp, vmem_switch, ImDoneFifoQ,
	cursor_adr, cursor0_ba, cursor1_ba, cursor0_ld, cursor1_ld,
	fb_data_fifo_rreq, fb_data_fifo_q, fb_data_fifo_empty);




	input         clk_i;
	input         rst_i;
	input         nrst_i;
	output        cyc_o;
	reg cyc_o;
	output        stb_o;
	reg stb_o;
	output [ 2:0] cti_o;
	reg [2:0] cti_o;
	output [ 1:0] bte_o;
	reg [1:0] bte_o;
	output        we_o;
	reg we_o;
	output [31:0] adr_o;
	output [ 3:0] sel_o;
	reg [3:0] sel_o;
	input         ack_i;
	input         err_i;
	input [31:0]  dat_i;

	output        sint;


	input       ctrl_ven;
	input [1:0] ctrl_cd;
	input [1:0] ctrl_vbl;
	input       ctrl_vbsw;
	output      busy;


	input [31: 2] VBAa;
	input [31: 2] VBAb;

	input [15:0] Thgate;
	input [15:0] Tvgate;

	output stat_avmp;
	output vmem_switch;
	output ImDoneFifoQ;

	output [ 8: 0] cursor_adr;
	input  [31:11] cursor0_ba;
	input  [31:11] cursor1_ba;
	input          cursor0_ld;
	input          cursor1_ld;

	input          fb_data_fifo_rreq;
	output [31: 0] fb_data_fifo_q;
	output         fb_data_fifo_empty;






	reg vmem_acc;
	wire vmem_req, vmem_ack;

	wire ImDone;
	reg  dImDone;
	wire ImDoneStrb;
	reg  dImDoneStrb;

	reg sclr;


	reg [31:11] cursor_ba;
	reg [ 8: 0] cursor_adr;
	wire        cursor0_we, cursor1_we;
	reg         ld_cursor0, ld_cursor1;
	reg         cur_acc;
	reg         cur_acc_sel;
	wire        cur_ack;
	wire        cur_done;






	always @(posedge clk_i)
	  sclr <= #1 ~ctrl_ven;




	reg  [ 2:0] burst_cnt;
	wire        burst_done;
	reg         sel_VBA;
	reg  [31:2] vmemA;


	always @(posedge clk_i)
	  if (sclr)
	    vmem_acc <= #1 1'b0;
	  else
	    vmem_acc <= #1 (vmem_req | (vmem_acc & !(burst_done & vmem_ack)) ) & !ImDone & !cur_acc;

	always @(posedge clk_i)
	  if (sclr)
	    cur_acc <= #1 1'b0;
	  else
	    cur_acc <= #1 (cur_acc | ImDone & (ld_cursor0 | ld_cursor1)) & !cur_done;
	    
	assign busy = vmem_acc | cur_acc;

	assign vmem_ack = ack_i & stb_o & vmem_acc;
	assign cur_ack  = ack_i & stb_o & cur_acc;
	assign sint = err_i;



	assign vmem_switch = ImDoneStrb;

	always @(posedge clk_i)
	  if (sclr)
	    sel_VBA <= #1 1'b0;
	  else if (ctrl_vbsw)
	    sel_VBA <= #1 sel_VBA ^ vmem_switch;

	assign stat_avmp = sel_VBA;



	vga_fifo #(4, 1) clut_sw_fifo (
		.clk    ( clk_i             ),
		.aclr   ( 1'b1              ),
		.sclr   ( sclr              ),
		.d      ( ImDone            ),
		.wreq   ( vmem_ack          ),
		.q      ( ImDoneFifoQ       ),
		.rreq   ( fb_data_fifo_rreq ),
		.nword  ( ),
		.empty  ( ),
		.full   ( ),
		.aempty ( ),
		.afull  ( )
	);




	wire [3:0] burst_cnt_val;
	assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;
	assign burst_done = burst_cnt_val[3];

	always @(posedge clk_i)
	  if ( (burst_done & vmem_ack) | !vmem_acc)
	    case (ctrl_vbl)
	      2'b00: burst_cnt <= #1 3'b000;
	      2'b01: burst_cnt <= #1 3'b001;
	      2'b10: burst_cnt <= #1 3'b011;
	      2'b11: burst_cnt <= #1 3'b111;
	    endcase
	  else if(vmem_ack)
	    burst_cnt <= #1 burst_cnt_val[2:0];






	reg  [15:0] hgate_cnt;
	reg  [16:0] hgate_cnt_val;
	reg  [1:0]  hgate_div_cnt;
	reg  [2:0]  hgate_div_val;

	wire hdone = hgate_cnt_val[16] & vmem_ack;

	always @(hgate_cnt or hgate_div_cnt or ctrl_cd)
	  begin
	      hgate_div_val = {1'b0, hgate_div_cnt} - 3'h1;

	      if (ctrl_cd != 2'b10)
	        hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
	      else if ( hgate_div_val[2] )
	        hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
	      else
	        hgate_cnt_val = {1'b0, hgate_cnt};
	  end

	always @(posedge clk_i)
	  if (sclr)
	    begin
	        case(ctrl_cd)
	          2'b00: hgate_cnt <= #1 Thgate >> 2;
	          2'b01: hgate_cnt <= #1 Thgate >> 1;
	          2'b10: hgate_cnt <= #1 Thgate >> 2;
	          2'b11: hgate_cnt <= #1 Thgate;
	        endcase

	        hgate_div_cnt <= 2'b10;
	    end
	  else if (vmem_ack)
	    if (hdone)
	      begin
	          case(ctrl_cd)
	            2'b00: hgate_cnt <= #1 Thgate >> 2;
	            2'b01: hgate_cnt <= #1 Thgate >> 1;
	            2'b10: hgate_cnt <= #1 Thgate >> 2;
	            2'b11: hgate_cnt <= #1 Thgate;
	          endcase

	          hgate_div_cnt <= 2'b10;
	      end
	    else
	      begin
	          hgate_cnt <= #1 hgate_cnt_val[15:0];

	          if ( hgate_div_val[2] )
	            hgate_div_cnt <= #1 2'b10;
	          else
	            hgate_div_cnt <= #1 hgate_div_val[1:0];
	      end


	reg  [15:0] vgate_cnt;
	wire [16:0] vgate_cnt_val;
	wire        vdone;

	assign vgate_cnt_val = {1'b0, vgate_cnt} - 17'h1;
	assign vdone = vgate_cnt_val[16];

	always @(posedge clk_i)
	  if (sclr | ImDoneStrb)
	    vgate_cnt <= #1 Tvgate;
	  else if (hdone)
	    vgate_cnt <= #1 vgate_cnt_val[15:0];

	assign ImDone = hdone & vdone;

	assign ImDoneStrb = ImDone & !dImDone;

	always @(posedge clk_i)
	  begin
	      dImDone <= #1 ImDone;
	      dImDoneStrb <= #1 ImDoneStrb;
	  end






	always @(posedge clk_i)
	  if (sclr | dImDoneStrb)
	    if (!sel_VBA)
	      vmemA <= #1 VBAa;
	    else
	      vmemA <= #1 VBAb;
	  else if (vmem_ack)
	    vmemA <= #1 vmemA +30'h1;





	always @(posedge clk_i)
	  if (ImDone)
	    cur_acc_sel <= #1 ld_cursor0;

	always @(posedge clk_i)
	if (sclr)
	  begin
	      ld_cursor0 <= #1 1'b0;
	      ld_cursor1 <= #1 1'b0;
	  end
	else
	  begin
	      ld_cursor0 <= #1 cursor0_ld | (ld_cursor0 & !(cur_done &  cur_acc_sel));
	      ld_cursor1 <= #1 cursor1_ld | (ld_cursor1 & !(cur_done & !cur_acc_sel));
	  end


	always @(posedge clk_i)
	  if (!cur_acc)
	    cursor_ba <= #1 ld_cursor0 ? cursor0_ba : cursor1_ba;


	wire [9:0] next_cursor_adr = {1'b0, cursor_adr} + 10'h1;
	assign cur_done = next_cursor_adr[9] & cur_ack;

	always @(posedge clk_i)
	  if (!cur_acc)
	    cursor_adr <= #1 9'h0;
	  else if (cur_ack)
	    cursor_adr <= #1 next_cursor_adr;


	assign cursor1_we = cur_ack & !cur_acc_sel;
	assign cursor0_we = cur_ack &  cur_acc_sel;





	assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00};
	wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & !vmem_req) & !ImDone ||
	                cur_acc & !cur_done;

	always @(posedge clk_i or negedge nrst_i)
	  if (!nrst_i)
	    begin
	        cyc_o <= #1 1'b0;
	        stb_o <= #1 1'b0;
	        sel_o <= #1 4'b1111;
	        cti_o <= #1 3'b000;
	        bte_o <= #1 2'b00;
	        we_o  <= #1 1'b0;
	    end
	  else
	    if (rst_i)
	      begin
	          cyc_o <= #1 1'b0;
	          stb_o <= #1 1'b0;
	          sel_o <= #1 4'b1111;
	          cti_o <= #1 3'b000;
	          bte_o <= #1 2'b00;
	          we_o  <= #1 1'b0;
	      end
	    else
	      begin
	          cyc_o <= #1 wb_cycle;
	          stb_o <= #1 wb_cycle;
	          sel_o <= #1 4'b1111;

	          if (wb_cycle) begin
	            if (cur_acc)
	              cti_o <= #1 &next_cursor_adr[8:0] ? 3'b111 : 3'b010;
	            else if (ctrl_vbl == 2'b00)
	              cti_o <= #1 3'b000;
	            else if (vmem_ack)
	              cti_o <= #1 (burst_cnt == 3'h1) ? 3'b111 : 3'b010;
	          end else
	            cti_o <= #1 (ctrl_vbl == 2'b00) ? 3'b000 : 3'b010;

	          bte_o <= #1 2'b00;
	          we_o  <= #1 1'b0;
	      end



	wire [4:0] fb_data_fifo_nword;


	vga_fifo #(4, 32) data_fifo (
		.clk    ( clk_i              ),
		.aclr   ( 1'b1               ),
		.sclr   ( sclr               ),
		.d      ( dat_i              ),
		.wreq   ( vmem_ack           ),
		.q      ( fb_data_fifo_q     ),
		.rreq   ( fb_data_fifo_rreq  ),
		.nword  ( fb_data_fifo_nword ),
		.empty  ( fb_data_fifo_empty ),
		.full   ( ),
		.aempty ( ),
		.afull  ( )
	);

	assign vmem_req = ~fb_data_fifo_nword[4] & ~fb_data_fifo_nword[3];

endmodule
module vga_wb_master (clk_i, rst_i, nrst_i,
	cyc_o, stb_o, cti_o, bte_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,
	ctrl_ven, ctrl_cd, ctrl_vbl, ctrl_vbsw, busy,
	VBAa, VBAb, Thgate, Tvgate,
	stat_avmp, vmem_switch, ImDoneFifoQ,
	cursor_adr, cursor0_ba, cursor1_ba, cursor0_ld, cursor1_ld,
	fb_data_fifo_rreq, fb_data_fifo_q, fb_data_fifo_empty);





	input         clk_i;
	input         rst_i;
	input         nrst_i;
	output        cyc_o;
	reg cyc_o;
	output        stb_o;
	reg stb_o;
	output [ 2:0] cti_o;
	reg [2:0] cti_o;
	output [ 1:0] bte_o;
	reg [1:0] bte_o;
	output        we_o;
	reg we_o;
	output [31:0] adr_o;
	output [ 3:0] sel_o;
	reg [3:0] sel_o;
	input         ack_i;
	input         err_i;
	input [31:0]  dat_i;

	output        sint;


	input       ctrl_ven;
	input [1:0] ctrl_cd;
	input [1:0] ctrl_vbl;
	input       ctrl_vbsw;
	output      busy;


	input [31: 2] VBAa;
	input [31: 2] VBAb;

	input [15:0] Thgate;
	input [15:0] Tvgate;

	output stat_avmp;
	output vmem_switch;
	output ImDoneFifoQ;

	output [ 8: 0] cursor_adr;
	input  [31:11] cursor0_ba;
	input  [31:11] cursor1_ba;
	input          cursor0_ld;
	input          cursor1_ld;

	input          fb_data_fifo_rreq;
	output [31: 0] fb_data_fifo_q;
	output         fb_data_fifo_empty;






	reg vmem_acc;
	wire vmem_req, vmem_ack;

	wire ImDone;
	reg  dImDone;
	wire ImDoneStrb;
	reg  dImDoneStrb;

	reg sclr;


	reg [31:11] cursor_ba;
	reg [ 8: 0] cursor_adr;
	wire        cursor0_we, cursor1_we;
	reg         ld_cursor0, ld_cursor1;
	reg         cur_acc;
	reg         cur_acc_sel;
	wire        cur_ack;
	wire        cur_done;






	always @(posedge clk_i)
	  sclr <= #1 ~ctrl_ven;




	reg  [ 2:0] burst_cnt;
	wire        burst_done;
	reg         sel_VBA;
	reg  [31:2] vmemA;


	always @(posedge clk_i)
	  if (sclr)
	    vmem_acc <= #1 1'b0;
	  else
	    vmem_acc <= #1 (vmem_req | (vmem_acc & !(burst_done & vmem_ack)) ) & !ImDone & !cur_acc;

	always @(posedge clk_i)
	  if (sclr)
	    cur_acc <= #1 1'b0;
	  else
	    cur_acc <= #1 (cur_acc | ImDone & (ld_cursor0 | ld_cursor1)) & !cur_done;
	    
	assign busy = vmem_acc | cur_acc;

	assign vmem_ack = ack_i & stb_o & vmem_acc;
	assign cur_ack  = ack_i & stb_o & cur_acc;
	assign sint = err_i;



	assign vmem_switch = ImDoneStrb;

	always @(posedge clk_i)
	  if (sclr)
	    sel_VBA <= #1 1'b0;
	  else if (ctrl_vbsw)
	    sel_VBA <= #1 sel_VBA ^ vmem_switch;

	assign stat_avmp = sel_VBA;



	vga_fifo #(4, 1) clut_sw_fifo (
		.clk    ( clk_i             ),
		.aclr   ( 1'b1              ),
		.sclr   ( sclr              ),
		.d      ( ImDone            ),
		.wreq   ( vmem_ack          ),
		.q      ( ImDoneFifoQ       ),
		.rreq   ( fb_data_fifo_rreq ),
		.nword  ( ),
		.empty  ( ),
		.full   ( ),
		.aempty ( ),
		.afull  ( )
	);




	wire [3:0] burst_cnt_val;
	assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;
	assign burst_done = burst_cnt_val[3];

	always @(posedge clk_i)
	  if ( (burst_done & vmem_ack) | !vmem_acc)
	    case (ctrl_vbl)
	      2'b00: burst_cnt <= #1 3'b000;
	      2'b01: burst_cnt <= #1 3'b001;
	      2'b10: burst_cnt <= #1 3'b011;
	      2'b11: burst_cnt <= #1 3'b111;
	    endcase
	  else if(vmem_ack)
	    burst_cnt <= #1 burst_cnt_val[2:0];






	reg  [15:0] hgate_cnt;
	reg  [16:0] hgate_cnt_val;
	reg  [1:0]  hgate_div_cnt;
	reg  [2:0]  hgate_div_val;

	wire hdone = hgate_cnt_val[16] & vmem_ack;

	always @(hgate_cnt or hgate_div_cnt or ctrl_cd)
	  begin
	      hgate_div_val = {1'b0, hgate_div_cnt} - 3'h1;

	      if (ctrl_cd != 2'b10)
	        hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
	      else if ( hgate_div_val[2] )
	        hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
	      else
	        hgate_cnt_val = {1'b0, hgate_cnt};
	  end

	always @(posedge clk_i)
	  if (sclr)
	    begin
	        case(ctrl_cd)
	          2'b00: hgate_cnt <= #1 Thgate >> 2;
	          2'b01: hgate_cnt <= #1 Thgate >> 1;
	          2'b10: hgate_cnt <= #1 Thgate >> 2;
	          2'b11: hgate_cnt <= #1 Thgate;
	        endcase

	        hgate_div_cnt <= 2'b10;
	    end
	  else if (vmem_ack)
	    if (hdone)
	      begin
	          case(ctrl_cd)
	            2'b00: hgate_cnt <= #1 Thgate >> 2;
	            2'b01: hgate_cnt <= #1 Thgate >> 1;
	            2'b10: hgate_cnt <= #1 Thgate >> 2;
	            2'b11: hgate_cnt <= #1 Thgate;
	          endcase

	          hgate_div_cnt <= 2'b10;
	      end
	    else
	      begin
	          hgate_cnt <= #1 hgate_cnt_val[15:0];

	          if ( hgate_div_val[2] )
	            hgate_div_cnt <= #1 2'b10;
	          else
	            hgate_div_cnt <= #1 hgate_div_val[1:0];
	      end


	reg  [15:0] vgate_cnt;
	wire [16:0] vgate_cnt_val;
	wire        vdone;

	assign vgate_cnt_val = {1'b0, vgate_cnt} - 17'h1;
	assign vdone = vgate_cnt_val[16];

	always @(posedge clk_i)
	  if (sclr | ImDoneStrb)
	    vgate_cnt <= #1 Tvgate;
	  else if (hdone)
	    vgate_cnt <= #1 vgate_cnt_val[15:0];

	assign ImDone = hdone & vdone;

	assign ImDoneStrb = ImDone & !dImDone;

	always @(posedge clk_i)
	  begin
	      dImDone <= #1 ImDone;
	      dImDoneStrb <= #1 ImDoneStrb;
	  end






	always @(posedge clk_i)
	  if (sclr | dImDoneStrb)
	    if (!sel_VBA)
	      vmemA <= #1 VBAa;
	    else
	      vmemA <= #1 VBAb;
	  else if (vmem_ack)
	    vmemA <= #1 vmemA +30'h1;





	always @(posedge clk_i)
	  if (ImDone)
	    cur_acc_sel <= #1 ld_cursor0;

	always @(posedge clk_i)
	if (sclr)
	  begin
	      ld_cursor0 <= #1 1'b0;
	      ld_cursor1 <= #1 1'b0;
	  end
	else
	  begin
	      ld_cursor0 <= #1 cursor0_ld | (ld_cursor0 & !(cur_done &  cur_acc_sel));
	      ld_cursor1 <= #1 cursor1_ld | (ld_cursor1 & !(cur_done & !cur_acc_sel));
	  end


	always @(posedge clk_i)
	  if (!cur_acc)
	    cursor_ba <= #1 ld_cursor0 ? cursor0_ba : cursor1_ba;


	wire [9:0] next_cursor_adr = {1'b0, cursor_adr} + 10'h1;
	assign cur_done = next_cursor_adr[9] & cur_ack;

	always @(posedge clk_i)
	  if (!cur_acc)
	    cursor_adr <= #1 9'h0;
	  else if (cur_ack)
	    cursor_adr <= #1 next_cursor_adr;


	assign cursor1_we = cur_ack & !cur_acc_sel;
	assign cursor0_we = cur_ack &  cur_acc_sel;





	assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00};
	wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & !vmem_req) & !ImDone ||
	                cur_acc & !cur_done;

	always @(posedge clk_i or negedge nrst_i)
	  if (!nrst_i)
	    begin
	        cyc_o <= #1 1'b0;
	        stb_o <= #1 1'b0;
	        sel_o <= #1 4'b1111;
	        cti_o <= #1 3'b000;
	        bte_o <= #1 2'b00;
	        we_o  <= #1 1'b0;
	    end
	  else
	    if (rst_i)
	      begin
	          cyc_o <= #1 1'b0;
	          stb_o <= #1 1'b0;
	          sel_o <= #1 4'b1111;
	          cti_o <= #1 3'b000;
	          bte_o <= #1 2'b00;
	          we_o  <= #1 1'b0;
	      end
	    else
	      begin
	          cyc_o <= #1 wb_cycle;
	          stb_o <= #1 wb_cycle;
	          sel_o <= #1 4'b1111;

	          if (wb_cycle) begin
	            if (cur_acc)
	              cti_o <= #1 &next_cursor_adr[8:0] ? 3'b111 : 3'b010;
	            else if (ctrl_vbl == 2'b00)
	              cti_o <= #1 3'b000;
	            else if (vmem_ack)
	              cti_o <= #1 (burst_cnt == 3'h1) ? 3'b111 : 3'b010;
	          end else
	            cti_o <= #1 (ctrl_vbl == 2'b00) ? 3'b000 : 3'b010;

	          bte_o <= #1 2'b00;
	          we_o  <= #1 1'b0;
	      end



	wire [4:0] fb_data_fifo_nword;


	vga_fifo #(4, 32) data_fifo (
		.clk    ( clk_i              ),
		.aclr   ( 1'b1               ),
		.sclr   ( sclr               ),
		.d      ( dat_i              ),
		.wreq   ( vmem_ack           ),
		.q      ( fb_data_fifo_q     ),
		.rreq   ( fb_data_fifo_rreq  ),
		.nword  ( fb_data_fifo_nword ),
		.empty  ( fb_data_fifo_empty ),
		.full   ( ),
		.aempty ( ),
		.afull  ( )
	);

	assign vmem_req = ~fb_data_fifo_nword[4] & ~fb_data_fifo_nword[3];

endmodule