data/full_repos/permissive/16507090/vga/VerilogSandbox.v
None: at end of input
1: b'%Error: data/full_repos/permissive/16507090/vga/VerilogSandbox.v:1: Cannot find include file: fifo.v\n`include "fifo.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/16507090/vga,data/full_repos/permissive/16507090/fifo.v\n             data/full_repos/permissive/16507090/vga,data/full_repos/permissive/16507090/fifo.v.v\n             data/full_repos/permissive/16507090/vga,data/full_repos/permissive/16507090/fifo.v.sv\n             fifo.v\n             fifo.v.v\n             fifo.v.sv\n             obj_dir/fifo.v\n             obj_dir/fifo.v.v\n             obj_dir/fifo.v.sv\n%Error: data/full_repos/permissive/16507090/vga/VerilogSandbox.v:229: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign bus_data_lines=voice ?   : \'bz;\n                                 ^\n%Error: Exiting due to 2 error(s)\n'
module SRAMInterface
#(

	parameter bus_period_ns=7,
	parameter access_time_ns=20,
	parameter ready_timer_bits=8,
	parameter word_length=16,
	parameter address_width=18,	

	parameter bus_width=32,
	parameter bus_max_devices=16,
	parameter bus_buffer_size=32,
	parameter device_id=1
)
(

	input clk,
	inout [bus_width-1:0] bus_data,
	inout [bus_max_devices-1:0] bus_receiver,
	inout [bus_max_devices-1:0] bus_write_request,
	inout [bus_max_devices-1:0] bus_buffer_full,
	input [bus_max_devices-1:0] bus_voice,

	output reg [address_width-1:0] chip_address_lines,
	inout [word_length-1:0] chip_data_lines,
	output reg chip_disable,
	output reg write_disable,
	output reg byte_low_disable,
	output reg byte_high_disable,
	output reg output_disable
);
	specparam tick_access_time=access_time_ns/bus_period_ns;

	wire [bus_width-1:0]		bus_in;
	wire [bus_max_devices-1:0]	bus_source;
	wire [bus_width-1:0]		bus_out;
	reg [bus_max_devices-1:0]	bus_target;
	wire bus_next;
	wire bus_send;
	wire bus_input_empty;
	wire bus_input_full;
	wire bus_output_empty;
	wire bus_output_full;

	BusClient
	#(
		.bus_width(bus_width),
		.bus_max_devices(bus_max_devices),
		.bus_buffer_size(bus_buffer_size),
		.device_id(device_id)
	) bus_client
	(
		clk,
		bus_data,
		bus_receiver,
		bus_write_request,
		bus_buffer_full,
		bus_voice,
		bus_in,
		bus_source,
		bus_out,
		bus_target,
		bus_next,
		bus_send,
		bus_input_empty,
		bus_input_full,
		bus_output_empty,
		bus_output_full
	);









	wire [1:0] action=bus_in[0+:2];
	wire [address_width-1:0] address=bus_in[2+:address_width];
	wire [7:0] data=bus_in[address_width+2+:8];

	assign bus_out[0+:word_length]=chip_data_lines;
	assign bus_out[word_length+:address_width]=chip_address_lines;

	reg [ready_timer_bits-1:0] ready_timer=0;
	SRAMState state=ready;

	always @(negedge clk) begin
		if (state==ready) begin
			bus_send<=0;
			bus_next<=0;
			if (~bus_input_empty) begin
				state<=busy;
				bus_target<=bus_source;
				case (SRAMMode'(action))
					read: begin
						chip_address_lines<=address;
							chip_read;
						ready_timer<=tick_access_time;
					end
					write: begin
						chip_address_lines<=address;
						chip_data_lines<=data;
						chip_write;
							ready_timer<=tick_access_time;
					end
					highz: chip_highz;
				endcase
			end
		end
		else if (state==busy) begin
			if (~ready_timer) begin
				bus_send<=1;
				bus_next<=1;
				state<=ready;
			end
			else begin
				ready_timer<=ready_timer-1;
			end
		end
	end

	task chip_highz;
		chip_disable<=1;
		write_disable<=1;
		byte_low_disable<=1;
		byte_high_disable<=1;
		output_disable<=1;
	endtask

	task chip_read;
		chip_disable<=0;
		write_disable<=1;
		byte_low_disable<=0;
		byte_high_disable<=0;
		output_disable<=0;
	endtask

	task chip_write;
		chip_disable<=0;
		write_disable<=0;
		byte_low_disable<=0;
		byte_high_disable<=0;


	endtask
endmodule
module SRAMInterface
#(

	parameter bus_period_ns=7,
	parameter access_time_ns=20,
	parameter ready_timer_bits=8,
	parameter word_length=16,
	parameter address_width=18,	

	parameter bus_width=32,
	parameter bus_max_devices=16,
	parameter bus_buffer_size=32,
	parameter device_id=1
)
(

	input clk,
	inout [bus_width-1:0] bus_data,
	inout [bus_max_devices-1:0] bus_receiver,
	inout [bus_max_devices-1:0] bus_write_request,
	inout [bus_max_devices-1:0] bus_buffer_full,
	input [bus_max_devices-1:0] bus_voice,

	output reg [address_width-1:0] chip_address_lines,
	inout [word_length-1:0] chip_data_lines,
	output reg chip_disable,
	output reg write_disable,
	output reg byte_low_disable,
	output reg byte_high_disable,
	output reg output_disable
);

	specparam tick_access_time=access_time_ns/bus_period_ns;

	wire [bus_width-1:0]		bus_in;
	wire [bus_max_devices-1:0]	bus_source;
	wire [bus_width-1:0]		bus_out;
	reg [bus_max_devices-1:0]	bus_target;
	wire bus_next;
	wire bus_send;
	wire bus_input_empty;
	wire bus_input_full;
	wire bus_output_empty;
	wire bus_output_full;

	BusClient
	#(
		.bus_width(bus_width),
		.bus_max_devices(bus_max_devices),
		.bus_buffer_size(bus_buffer_size),
		.device_id(device_id)
	) bus_client
	(
		clk,
		bus_data,
		bus_receiver,
		bus_write_request,
		bus_buffer_full,
		bus_voice,
		bus_in,
		bus_source,
		bus_out,
		bus_target,
		bus_next,
		bus_send,
		bus_input_empty,
		bus_input_full,
		bus_output_empty,
		bus_output_full
	);









	wire [1:0] action=bus_in[0+:2];
	wire [address_width-1:0] address=bus_in[2+:address_width];
	wire [7:0] data=bus_in[address_width+2+:8];

	assign bus_out[0+:word_length]=chip_data_lines;
	assign bus_out[word_length+:address_width]=chip_address_lines;

	reg [ready_timer_bits-1:0] ready_timer=0;
	SRAMState state=ready;

	always @(negedge clk) begin
		if (state==ready) begin
			bus_send<=0;
			bus_next<=0;
			if (~bus_input_empty) begin
				state<=busy;
				bus_target<=bus_source;
				case (SRAMMode'(action))
					read: begin
						chip_address_lines<=address;
							chip_read;
						ready_timer<=tick_access_time;
					end
					write: begin
						chip_address_lines<=address;
						chip_data_lines<=data;
						chip_write;
							ready_timer<=tick_access_time;
					end
					highz: chip_highz;
				endcase
			end
		end
		else if (state==busy) begin
			if (~ready_timer) begin
				bus_send<=1;
				bus_next<=1;
				state<=ready;
			end
			else begin
				ready_timer<=ready_timer-1;
			end
		end
	end

	task chip_highz;
		chip_disable<=1;
		write_disable<=1;
		byte_low_disable<=1;
		byte_high_disable<=1;
		output_disable<=1;
	endtask

	task chip_read;
		chip_disable<=0;
		write_disable<=1;
		byte_low_disable<=0;
		byte_high_disable<=0;
		output_disable<=0;
	endtask

	task chip_write;
		chip_disable<=0;
		write_disable<=0;
		byte_low_disable<=0;
		byte_high_disable<=0;


	endtask
endmodule