data/full_repos/permissive/129127690/deco_1_2.v
data/verilator_xmls/c78ece54-65de-45b0-a4c8-b7af7e795305.xml
module deco_1_2 #(parameter bus_size = 8)(
	input  select,
	input  [bus_size-1:0] in,
	output  [bus_size-1:0] outa,
	output [bus_size-1:0] outb);
		
	genvar i;
	generate 
	for (i = 0; i < bus_size; i = i+1) begin:forloop
		assign outa[i] = ~select & in[i];
		assign outb[i] =  select & in[i];
	end
	endgenerate
		
endmodule
module deco_1_2 #(parameter bus_size = 8)(
	input  select,
	input  [bus_size-1:0] in,
	output  [bus_size-1:0] outa,
	output [bus_size-1:0] outb);

		
	genvar i;
	generate 
	for (i = 0; i < bus_size; i = i+1) begin:forloop
		assign outa[i] = ~select & in[i];
		assign outb[i] =  select & in[i];
	end
	endgenerate
		
endmodule