data/full_repos/permissive/169738435/System/upd4990.v
data/verilator_xmls/baf5b4f7-c82e-485c-bfbc-b65fdd70a9c9.xml
module upd4990(
	input XTAL,
	input CS, OE,
	input CLK,
	input DATA_IN,
	input STROBE,
	output reg TP,
	output DATA_OUT
);


	
	parameter TIME_REG = 48'h892424113000;
	
	reg [3:0] COMMAND_SR;
	
	wire [51:0] TIME_SR;
	wire CLKG, STROBEG;

	assign TIME_SR = { COMMAND_SR, TIME_REG };
	assign DATA_OUT = 1'b0;
	assign CLKG = CS & CLK;
	assign STROBEG = CS & STROBE;

	always @(posedge CLKG)
	begin
		if (CS)
		begin
			COMMAND_SR[2:0] <= COMMAND_SR[3:1];
			COMMAND_SR[3] <= DATA_IN;
		end
	end
	


	
endmodule
module upd4990(
	input XTAL,
	input CS, OE,
	input CLK,
	input DATA_IN,
	input STROBE,
	output reg TP,
	output DATA_OUT
);



	
	parameter TIME_REG = 48'h892424113000;
	
	reg [3:0] COMMAND_SR;
	
	wire [51:0] TIME_SR;
	wire CLKG, STROBEG;

	assign TIME_SR = { COMMAND_SR, TIME_REG };
	assign DATA_OUT = 1'b0;
	assign CLKG = CS & CLK;
	assign STROBEG = CS & STROBE;

	always @(posedge CLKG)
	begin
		if (CS)
		begin
			COMMAND_SR[2:0] <= COMMAND_SR[3:1];
			COMMAND_SR[3] <= DATA_IN;
		end
	end
	


	
endmodule