data/full_repos/permissive/119126104/myCPU/regfile_2r1w.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/119126104/myCPU/regfile_2r1w.v:28: Multiple top level modules\n                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                               : ... Top module \'regfile_2r1w\'\nmodule regfile_2r1w(\n       ^~~~~~~~~~~~\n                                                                               : ... Top module \'reg_HILO\'\nmodule reg_HILO(\n       ^~~~~~~~\n                                                                               : ... Top module \'reg_CP0\'\nmodule reg_CP0(\n       ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module reg_HILO(
    input  wire        clk,

    output wire [31:0] rd_HI,
    output wire [31:0] rd_LO,

    input  wire        we_HI,
    input  wire [31:0] wd_HI,
    input  wire        we_LO,
    input  wire [31:0] wd_LO
);

reg  [31:0] HI;
reg  [31:0] LO;

assign rd_HI = HI;
assign rd_LO = LO;

always @(posedge clk) begin
    if (we_HI)
        HI <= wd_HI;
    if (we_LO)
        LO <= wd_LO;
end

endmodule
module reg_HILO(
    input  wire        clk,

    output wire [31:0] rd_HI,
    output wire [31:0] rd_LO,

    input  wire        we_HI,
    input  wire [31:0] wd_HI,
    input  wire        we_LO,
    input  wire [31:0] wd_LO
);


reg  [31:0] HI;
reg  [31:0] LO;

assign rd_HI = HI;
assign rd_LO = LO;

always @(posedge clk) begin
    if (we_HI)
        HI <= wd_HI;
    if (we_LO)
        LO <= wd_LO;
end

endmodule