data/full_repos/permissive/143278/fpga_tests/timer_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/timer_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/timer_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk = 0;\n      ^\n%Error: data/full_repos/permissive/143278/fpga_tests/timer_tb.v:37: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, main);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/timer_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #7 reset = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/timer_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (rdy !== 0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/timer_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #6 reset = 0;\n      ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire rdy;
   reg	reset, clk;

   timer dut(.rdy(rdy), .clk(clk), .reset(reset));

   always begin
      #5 clk = 1;
      #5 clk = 0;
   end

   initial begin
      $dumpvars(0, main);
      #7 reset = 1;
      #1 if (rdy !== 0) begin
	 $display("FAILED: reset did not clear rdy. rdy=%b", rdy);
	 $finish;
      end
      #6 reset = 0;
   end

   always @(posedge clk)
     if (rdy === 1) begin
	$display("rdy=%b at time=%0d", rdy,  $time);
	if ($time != 175) begin
	   $display("FAILED: timer ran out incorrectly.");
	   $finish;
	end

	$display("PASSED");
	$finish;
     end

endmodule
module main;


   wire rdy;
   reg	reset, clk;

   timer dut(.rdy(rdy), .clk(clk), .reset(reset));

   always begin
      #5 clk = 1;
      #5 clk = 0;
   end

   initial begin
      $dumpvars(0, main);
      #7 reset = 1;
      #1 if (rdy !== 0) begin
	 $display("FAILED: reset did not clear rdy. rdy=%b", rdy);
	 $finish;
      end
      #6 reset = 0;
   end

   always @(posedge clk)
     if (rdy === 1) begin
	$display("rdy=%b at time=%0d", rdy,  $time);
	if ($time != 175) begin
	   $display("FAILED: timer ran out incorrectly.");
	   $finish;
	end

	$display("PASSED");
	$finish;
     end

endmodule