data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/CKLNQD12PO4.v
None: at end of input
data/verilator_xmls/ae7b6ce5-5721-4fb5-a932-c33784103d63.xml
module CKLNQD12PO4 (
  TE
 ,E
 ,CP
 ,Q
 );
input TE ;
input E ;
input CP ;
output Q ;
reg qd;
always @(negedge CP)
    qd <= TE | E;
assign Q = CP & qd;
endmodule
module CKLNQD12PO4 (
  TE
 ,E
 ,CP
 ,Q
 );

input TE ;
input E ;
input CP ;
output Q ;
reg qd;
always @(negedge CP)
    qd <= TE | E;
assign Q = CP & qd;
endmodule