data/full_repos/permissive/216344104/sincos.v
data/verilator_xmls/39f14954-b1c9-495b-be31-1e6ec62b0dd1.xml
module isin(
  input signed [15:0] x,
  output signed [15:0] s);

  wire signed [15:0] z, y, sums, sumc, sum1, cc;

  wire [2:0] n = x[15:13] + 3'd1;
  assign y = {x[13:0], 2'b00};

  hmadd _h0(.a(y), .b(y), .c(0), .p(z));
  hmadd _hc(.a(z), .b(16'sh0fbd), .c(-16'sh4ee9), .p(sumc));
  hmadd _hs(.a(z), .b(16'sh04f8), .c(-16'sh2953), .p(sums));
  hmadd _h2(.a(z), .b(sums), .c(16'sh6487), .p(sum1));

  reg signed [15:0] t0, t1, sa;
  always @*
    if (n[1]) begin
      t0 = z;
      t1 = sumc;
      sa = cc + 16'sh7fff;
    end else begin
      t0 = y;
      t1 = sum1;
      sa = cc;
    end
  wire [31:0] cc32 = t0 * t1;
  assign cc = cc32[30:15];

  assign s = n[2] ? -sa : sa;
endmodule
module isin(
  input signed [15:0] x,
  output signed [15:0] s);


  wire signed [15:0] z, y, sums, sumc, sum1, cc;

  wire [2:0] n = x[15:13] + 3'd1;
  assign y = {x[13:0], 2'b00};

  hmadd _h0(.a(y), .b(y), .c(0), .p(z));
  hmadd _hc(.a(z), .b(16'sh0fbd), .c(-16'sh4ee9), .p(sumc));
  hmadd _hs(.a(z), .b(16'sh04f8), .c(-16'sh2953), .p(sums));
  hmadd _h2(.a(z), .b(sums), .c(16'sh6487), .p(sum1));

  reg signed [15:0] t0, t1, sa;
  always @*
    if (n[1]) begin
      t0 = z;
      t1 = sumc;
      sa = cc + 16'sh7fff;
    end else begin
      t0 = y;
      t1 = sum1;
      sa = cc;
    end
  wire [31:0] cc32 = t0 * t1;
  assign cc = cc32[30:15];

  assign s = n[2] ? -sa : sa;
endmodule