data/full_repos/permissive/151116236/src/mojo_top.v
1: b'%Error: data/full_repos/permissive/151116236/src/mojo_top.v:75: Cannot find file containing module: \'spi_slave\'\nspi_slave com1(clk, rst, my_spi_ss, my_spi_mosi, my_spi_miso, my_spi_sck, done, din, dout);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151116236/src,data/full_repos/permissive/151116236/spi_slave\n             data/full_repos/permissive/151116236/src,data/full_repos/permissive/151116236/spi_slave.v\n             data/full_repos/permissive/151116236/src,data/full_repos/permissive/151116236/spi_slave.sv\n             spi_slave\n             spi_slave.v\n             spi_slave.sv\n             obj_dir/spi_slave\n             obj_dir/spi_slave.v\n             obj_dir/spi_slave.sv\n%Warning-WIDTH: data/full_repos/permissive/151116236/src/mojo_top.v:78: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 9 bits.\n                                                                      : ... In instance mojo_top\n      din <= decoder[15:7];\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module mojo_top(

    input clk,

    input rst_n,

    input cclk,

    output[7:0]led,

    output spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,

    output [3:0] spi_channel,

    input avr_tx,
    output avr_rx,
    input avr_rx_busy,
    

    output my_spi_miso,
    input my_spi_ss,
    input my_spi_mosi,
    input my_spi_sck
    );

wire rst = ~rst_n;


assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;





reg data1 = 1'b1;
reg [32:0] counter;
reg [32:0] decoder;
reg state;


assign led[0] = state;
assign led[1] = data1;

assign led[7] = rst;
assign led[6] = my_spi_ss;



always @ (posedge clk) begin
    if (rst)
      counter <= 0;
     else
      counter <= counter + 1;
    state <= counter[26];

    qout[0] <= counter[20] ^ counter[21];
    qout[1] <= counter[21];
    qin <= qout;
    
end


reg [1:0] pqin;


wire done;
reg [7:0] din;
wire [7:0] dout;

spi_slave com1(clk, rst, my_spi_ss, my_spi_mosi, my_spi_miso, my_spi_sck, done, din, dout);
always @ (posedge clk) begin
    if(spi_ss)
      din <= decoder[15:7];
end 

always @ (posedge clk) begin
  if (rst)
      decoder <= 0;
  if(pqin[1] ^ qin[0])
    decoder <= decoder + 1;
  if(pqin[0] ^ qin[1])
    decoder <= decoder - 1;  

  pqin <= qin;
  
end




reg [1:0] qout;
reg [1:0] qin;



assign led[3:2] = qout;
assign led[5:4] = decoder[6:5];



endmodule
module mojo_top(

    input clk,

    input rst_n,

    input cclk,

    output[7:0]led,

    output spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,

    output [3:0] spi_channel,

    input avr_tx,
    output avr_rx,
    input avr_rx_busy,
    

    output my_spi_miso,
    input my_spi_ss,
    input my_spi_mosi,
    input my_spi_sck
    );


wire rst = ~rst_n;


assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;





reg data1 = 1'b1;
reg [32:0] counter;
reg [32:0] decoder;
reg state;


assign led[0] = state;
assign led[1] = data1;

assign led[7] = rst;
assign led[6] = my_spi_ss;



always @ (posedge clk) begin
    if (rst)
      counter <= 0;
     else
      counter <= counter + 1;
    state <= counter[26];

    qout[0] <= counter[20] ^ counter[21];
    qout[1] <= counter[21];
    qin <= qout;
    
end


reg [1:0] pqin;


wire done;
reg [7:0] din;
wire [7:0] dout;

spi_slave com1(clk, rst, my_spi_ss, my_spi_mosi, my_spi_miso, my_spi_sck, done, din, dout);
always @ (posedge clk) begin
    if(spi_ss)
      din <= decoder[15:7];
end 

always @ (posedge clk) begin
  if (rst)
      decoder <= 0;
  if(pqin[1] ^ qin[0])
    decoder <= decoder + 1;
  if(pqin[0] ^ qin[1])
    decoder <= decoder - 1;  

  pqin <= qin;
  
end




reg [1:0] qout;
reg [1:0] qin;



assign led[3:2] = qout;
assign led[5:4] = decoder[6:5];



endmodule