data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v
 line:39: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n forever #(CLK_CYCLE/2) clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_CYCLE*75) arstn = 1\'b1;\n ^\n%Error: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:38: syntax error, unexpected \'@\'\n @(posedge arstn)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE) bytewrite_start = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:47: syntax error, unexpected \'@\'\n @(posedge bytewrite_start)\n ^\n%Error: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:51: syntax error, unexpected \'@\'\n @(negedge bytewrite_done)\n ^\n%Error: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:58: syntax error, unexpected \'@\'\n @(posedge bytewrite_start)\n ^\n%Error: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:66: syntax error, unexpected \'@\'\n @(negedge bytewrite_start)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV*8)  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV*8)  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV)\n  ^\n%Error: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite_tb.v:85: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Error: Exiting due to 6 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PCA24S08A_bytewrite_tb();

parameter	CLK_FREQ = 50_000_000,
			I2C_FREQ = 500_000,
			CLK_CYCLE = 20,
			DIV = CLK_FREQ / I2C_FREQ;

reg	clk, arstn;
reg	bytewrite_start;
reg	[2:0]	block_num, page_num;
reg	[3:0]	byte_addr;
reg	[7:0]	data_write;
wire	bytewrite_done;

wire	sda, scl;

reg	sda_in, sda_in_en;

assign sda = sda_in_en ? sda_in : 1'bz;


initial begin
	clk = 0;
	forever	#(CLK_CYCLE/2)	clk = ~clk;
end


initial begin
	arstn = 1'b0;
	#(CLK_CYCLE*75)	arstn = 1'b1;
end

task gen_bytewrite_start;
begin
	bytewrite_start = 1'b0;
	@(posedge arstn)
	@(posedge clk)
		#(CLK_CYCLE*10)	bytewrite_start = 1'b1;
		#(CLK_CYCLE)	bytewrite_start = 1'b0;
end
endtask

task gen_bytewrite_addr;
begin
	@(posedge bytewrite_start)
		block_num = 3'b110;
		page_num = 3'b010;
		byte_addr = 4'b1111;
	@(negedge bytewrite_done)
		#(CLK_CYCLE*75)	$finish;
end
endtask

task gen_bytewrite_data;
begin
	@(posedge bytewrite_start)
		data_write = 8'b11001001;
end
endtask

task gen_bytewrite_ack;
begin
	sda_in_en = 1'b0;
	@(negedge bytewrite_start)
		#(CLK_CYCLE*DIV*10)
			sda_in_en = 1'b1;
			sda_in = 1'b0;
		#(CLK_CYCLE*DIV)
			sda_in_en = 1'b0;
		#(CLK_CYCLE*DIV*8)
			sda_in_en = 1'b1;
			sda_in = 1'b0;
		#(CLK_CYCLE*DIV)
			sda_in_en = 1'b0;
		#(CLK_CYCLE*DIV*8)
			sda_in_en = 1'b1;
			sda_in = 1'b0;
		#(CLK_CYCLE*DIV)
			sda_in_en = 1'b0;
end
endtask

initial fork
	gen_bytewrite_start;
	gen_bytewrite_addr;
	gen_bytewrite_data;
	gen_bytewrite_ack;
join

PCA24S08A_bytewrite
#(
	.CLK_FREQ(CLK_FREQ),
	.I2C_FREQ(I2C_FREQ)
)
DUT(
	.clk(clk),
	.arstn(arstn),
	.bytewrite_start(bytewrite_start),
	.block_num(block_num),
	.page_num(page_num),
	.byte_addr(byte_addr),
	.data_write(data_write),
	.bytewrite_done(bytewrite_done),
	.sda(sda),
	.scl(scl)
);

endmodule
module PCA24S08A_bytewrite_tb();


parameter	CLK_FREQ = 50_000_000,
			I2C_FREQ = 500_000,
			CLK_CYCLE = 20,
			DIV = CLK_FREQ / I2C_FREQ;

reg	clk, arstn;
reg	bytewrite_start;
reg	[2:0]	block_num, page_num;
reg	[3:0]	byte_addr;
reg	[7:0]	data_write;
wire	bytewrite_done;

wire	sda, scl;

reg	sda_in, sda_in_en;

assign sda = sda_in_en ? sda_in : 1'bz;


initial begin
	clk = 0;
	forever	#(CLK_CYCLE/2)	clk = ~clk;
end


initial begin
	arstn = 1'b0;
	#(CLK_CYCLE*75)	arstn = 1'b1;
end

task gen_bytewrite_start;
begin
	bytewrite_start = 1'b0;
	@(posedge arstn)
	@(posedge clk)
		#(CLK_CYCLE*10)	bytewrite_start = 1'b1;
		#(CLK_CYCLE)	bytewrite_start = 1'b0;
end
endtask

task gen_bytewrite_addr;
begin
	@(posedge bytewrite_start)
		block_num = 3'b110;
		page_num = 3'b010;
		byte_addr = 4'b1111;
	@(negedge bytewrite_done)
		#(CLK_CYCLE*75)	$finish;
end
endtask

task gen_bytewrite_data;
begin
	@(posedge bytewrite_start)
		data_write = 8'b11001001;
end
endtask

task gen_bytewrite_ack;
begin
	sda_in_en = 1'b0;
	@(negedge bytewrite_start)
		#(CLK_CYCLE*DIV*10)
			sda_in_en = 1'b1;
			sda_in = 1'b0;
		#(CLK_CYCLE*DIV)
			sda_in_en = 1'b0;
		#(CLK_CYCLE*DIV*8)
			sda_in_en = 1'b1;
			sda_in = 1'b0;
		#(CLK_CYCLE*DIV)
			sda_in_en = 1'b0;
		#(CLK_CYCLE*DIV*8)
			sda_in_en = 1'b1;
			sda_in = 1'b0;
		#(CLK_CYCLE*DIV)
			sda_in_en = 1'b0;
end
endtask

initial fork
	gen_bytewrite_start;
	gen_bytewrite_addr;
	gen_bytewrite_data;
	gen_bytewrite_ack;
join

PCA24S08A_bytewrite
#(
	.CLK_FREQ(CLK_FREQ),
	.I2C_FREQ(I2C_FREQ)
)
DUT(
	.clk(clk),
	.arstn(arstn),
	.bytewrite_start(bytewrite_start),
	.block_num(block_num),
	.page_num(page_num),
	.byte_addr(byte_addr),
	.data_write(data_write),
	.bytewrite_done(bytewrite_done),
	.sda(sda),
	.scl(scl)
);

endmodule