data/full_repos/permissive/10136357/hardware/src/decode.v
1: b'%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n             consts.vh\n             consts.vh.v\n             consts.vh.sv\n             obj_dir/consts.vh\n             obj_dir/consts.vh.v\n             obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:48: Define or directive not defined: \'`OPCODE_JAL\'\n assign wd = (opcode == `OPCODE_JAL) ? 5\'d1 : inst[31:27];\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:48: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign wd = (opcode == `OPCODE_JAL) ? 5\'d1 : inst[31:27];\n                                   ^\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:50: Define or directive not defined: \'`OPCODE_OP\'\n assign rf_wr_en = (opcode == `OPCODE_OP ||\n                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:50: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign rf_wr_en = (opcode == `OPCODE_OP ||\n                                         ^~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:51: Define or directive not defined: \'`OPCODE_OP_IMM\'\n                    opcode == `OPCODE_OP_IMM ||\n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:52: Define or directive not defined: \'`OPCODE_LUI\'\n                    opcode == `OPCODE_LUI ||\n                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:53: Define or directive not defined: \'`OPCODE_LOAD\'\n                    opcode == `OPCODE_LOAD ||\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:54: Define or directive not defined: \'`OPCODE_JAL\'\n                    opcode == `OPCODE_JAL ||\n                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:55: Define or directive not defined: \'`OPCODE_JALR\'\n                    opcode == `OPCODE_JALR ||\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:56: Define or directive not defined: \'`OPCODE_PCR\'\n      opcode == `OPCODE_PCR);\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:58: Define or directive not defined: \'`OPCODE_LOAD\'\n assign memory_request = (opcode == `OPCODE_LOAD || \n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:58: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign memory_request = (opcode == `OPCODE_LOAD || \n                                                 ^~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:59: Define or directive not defined: \'`OPCODE_STORE\'\n                          opcode == `OPCODE_STORE);\n                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:61: Define or directive not defined: \'`OPCODE_STORE\'\n assign memory_request_type = (opcode == `OPCODE_STORE) ? \n                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:61: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign memory_request_type = (opcode == `OPCODE_STORE) ? \n                                                      ^\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:62: Define or directive not defined: \'`MEM_REQ_WRITE\'\n                              `MEM_REQ_WRITE : `MEM_REQ_READ;\n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:62: Define or directive not defined: \'`MEM_REQ_READ\'\n                              `MEM_REQ_WRITE : `MEM_REQ_READ;\n                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:66: Define or directive not defined: \'`OPCODE_OP\'\n   `OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:66: syntax error, unexpected \',\', expecting endcase\n   `OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:\n             ^\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:66: Define or directive not defined: \'`OPCODE_OP_IMM\'\n   `OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:\n               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:66: Define or directive not defined: \'`OPCODE_LUI\'\n   `OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:67: Define or directive not defined: \'`WB_ALU\'\n    wb_sel = `WB_ALU;\n             ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:68: Define or directive not defined: \'`OPCODE_LOAD\'\n   `OPCODE_LOAD:\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:69: Define or directive not defined: \'`WB_MEM\'\n    wb_sel = `WB_MEM;\n             ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:70: Define or directive not defined: \'`OPCODE_JAL\'\n   `OPCODE_JAL, `OPCODE_JALR:\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:70: Define or directive not defined: \'`OPCODE_JALR\'\n   `OPCODE_JAL, `OPCODE_JALR:\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:71: Define or directive not defined: \'`WB_PC4\'\n    wb_sel = `WB_PC4;\n             ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:72: Define or directive not defined: \'`OPCODE_PCR\'\n   `OPCODE_PCR:\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:73: Define or directive not defined: \'`WB_PCR\'\n    wb_sel = `WB_PCR;\n             ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:80: Define or directive not defined: \'`OPCODE_PCR\'\n  if (opcode == `OPCODE_PCR) begin\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/decode.v:84: syntax error, unexpected else\n  end else begin\n      ^~~~\n%Error: Cannot continue\n'
module decode (
	input [31:0] inst,

	output [4:0] rs1,
	output [4:0] rs2,
	output [4:0] wd,

	output reg [2:0] wb_sel,

	output rf_wr_en,

	output memory_request,
	output memory_request_type,

	output reg pcr_enable,
	output reg [1:0] pcr_cmd
);
	wire [6:0] opcode = inst[6:0];
	assign rs1 = inst[26:22];
	assign rs2 = inst[21:17];
	assign wd = (opcode == `OPCODE_JAL) ? 5'd1 : inst[31:27];
	
	assign rf_wr_en = (opcode == `OPCODE_OP ||
	                   opcode == `OPCODE_OP_IMM ||
	                   opcode == `OPCODE_LUI ||
	                   opcode == `OPCODE_LOAD ||
	                   opcode == `OPCODE_JAL ||
	                   opcode == `OPCODE_JALR ||
			   opcode == `OPCODE_PCR);

	assign memory_request = (opcode == `OPCODE_LOAD || 
	                         opcode == `OPCODE_STORE);
	
	assign memory_request_type = (opcode == `OPCODE_STORE) ? 
	                             `MEM_REQ_WRITE : `MEM_REQ_READ;

	always @ (*) begin
		case (opcode)
			`OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:
				wb_sel = `WB_ALU;
			`OPCODE_LOAD:
				wb_sel = `WB_MEM;
			`OPCODE_JAL, `OPCODE_JALR:
				wb_sel = `WB_PC4;
			`OPCODE_PCR:
				wb_sel = `WB_PCR;
			default:
				wb_sel = 0;
		endcase
	end

	always @ (*) begin
		if (opcode == `OPCODE_PCR) begin
			pcr_enable = 1;

			pcr_cmd = inst[8:7];
		end else begin
			pcr_enable = 0;
			pcr_cmd = 2'b00;
		end
	end

endmodule
module decode (
	input [31:0] inst,

	output [4:0] rs1,
	output [4:0] rs2,
	output [4:0] wd,

	output reg [2:0] wb_sel,

	output rf_wr_en,

	output memory_request,
	output memory_request_type,

	output reg pcr_enable,
	output reg [1:0] pcr_cmd
);

	wire [6:0] opcode = inst[6:0];
	assign rs1 = inst[26:22];
	assign rs2 = inst[21:17];
	assign wd = (opcode == `OPCODE_JAL) ? 5'd1 : inst[31:27];
	
	assign rf_wr_en = (opcode == `OPCODE_OP ||
	                   opcode == `OPCODE_OP_IMM ||
	                   opcode == `OPCODE_LUI ||
	                   opcode == `OPCODE_LOAD ||
	                   opcode == `OPCODE_JAL ||
	                   opcode == `OPCODE_JALR ||
			   opcode == `OPCODE_PCR);

	assign memory_request = (opcode == `OPCODE_LOAD || 
	                         opcode == `OPCODE_STORE);
	
	assign memory_request_type = (opcode == `OPCODE_STORE) ? 
	                             `MEM_REQ_WRITE : `MEM_REQ_READ;

	always @ (*) begin
		case (opcode)
			`OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:
				wb_sel = `WB_ALU;
			`OPCODE_LOAD:
				wb_sel = `WB_MEM;
			`OPCODE_JAL, `OPCODE_JALR:
				wb_sel = `WB_PC4;
			`OPCODE_PCR:
				wb_sel = `WB_PCR;
			default:
				wb_sel = 0;
		endcase
	end

	always @ (*) begin
		if (opcode == `OPCODE_PCR) begin
			pcr_enable = 1;

			pcr_cmd = inst[8:7];
		end else begin
			pcr_enable = 0;
			pcr_cmd = 2'b00;
		end
	end

endmodule