data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/vga_core.v
1: b'%Warning-WIDTH: data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/vga_core.v:151: Value too large for 8 bit number: 400\n    ball_x_pos <= {8\'d0, 8\'d400, 8\'d0 };        \n                         ^~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/vga_core.v:152: Value too large for 8 bit number: 300\n    ball_y_pos <= {8\'d0, 8\'d300, 8\'d0 };\n                         ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/vga_core.v:154: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                                              : ... In instance vga_core\n    ball_x_dir <= { 2\'b01, random_num[11:2]  }; \n               ^~\n%Warning-WIDTH: data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/vga_core.v:155: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                                              : ... In instance vga_core\n    ball_y_dir <= { 2\'b01, random_num[23:14] }; \n               ^~\n%Warning-WIDTH: data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/vga_core.v:166: Operator NOT expects 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                              : ... In instance vga_core\n        ball_x_dir    <= ~ ball_x_dir[11:0];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/vga_core.v:169: Operator NOT expects 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                              : ... In instance vga_core\n        ball_x_dir    <= ~ ball_x_dir[11:0];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/vga_core.v:173: Operator NOT expects 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                              : ... In instance vga_core\n        ball_y_dir    <= ~ ball_y_dir[11:0];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/vga_core.v:176: Operator NOT expects 16 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                              : ... In instance vga_core\n        ball_y_dir    <= ~ ball_y_dir[11:0];\n                         ^\n%Error: data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/vga_core.v:255: Cannot find file containing module: \'vga_timing\'\nvga_timing u0_vga_timing\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410,data/full_repos/permissive/166492247/vga_timing\n             data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410,data/full_repos/permissive/166492247/vga_timing.v\n             data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410,data/full_repos/permissive/166492247/vga_timing.sv\n             vga_timing\n             vga_timing.v\n             vga_timing.sv\n             obj_dir/vga_timing\n             obj_dir/vga_timing.v\n             obj_dir/vga_timing.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n'
module vga_core
(
  input  wire         reset,
  input  wire         color_3b,
  input  wire         mode_bit,
  input  wire         clk_dot,
  input  wire  [31:0] random_num,
  output wire  [23:0] vga_pixel_rgb,
  output wire         vga_active,
  output wire         vga_hsync,
  output wire         vga_vsync
);

  reg  [15:0]   u0_pel_x;
  reg  [15:0]   u0_pel_y;
  reg  [23:0]   vga_rgb_tp;
  reg  [23:0]   vga_rgb_ball;
  reg  [23:0]   vga_rgb_line;
  reg  [23:0]   vga_rgb;
  wire [7:0]    ramp;
  reg  [15:0]   ball_x_dir;
  reg  [15:0]   ball_y_dir;
  reg  [23:0]   ball_x_pos;
  reg  [23:0]   ball_y_pos;
  reg  [3:0]    dir_chg_sr;
  reg  [23:0]   ball_rgb;
  reg  [3:0]    demo_mode;
  reg           mode_bit_p1;
  reg  [15:0]   line_x_pos;
  reg  [15:0]   line_y_pos;
  reg  [23:0]   line_rgb;


  wire          u0_vid_new_frame;
  wire          u0_vid_new_line;
  wire          u0_vid_active;
  wire          u0_vga_hsync;
  wire          u0_vga_vsync;

  assign vga_active    = u0_vid_active;
  assign vga_hsync     = u0_vga_hsync;
  assign vga_vsync     = u0_vga_vsync;
  assign vga_pixel_rgb = vga_rgb[23:0];
  assign ramp          = { u0_pel_x[6:0], 1'b0 };





always @ ( posedge clk_dot ) begin : proc_out_mux 
 begin
  mode_bit_p1 <= mode_bit;
  if ( color_3b == 0 ) begin
    if ( mode_bit == 0 ) begin
      vga_rgb <= vga_rgb_tp[23:0];
    end else begin
      if ( mode_bit_p1 == 0 ) begin
        demo_mode <= ~demo_mode[3:0];
      end
        if ( demo_mode[0] == 0 ) begin
        vga_rgb <= vga_rgb_ball[23:0];
      end else begin
        vga_rgb <= vga_rgb_line[23:0];
      end 
    end 
  end else begin
    if ( mode_bit == 0 ) begin
      vga_rgb[23:16] <= ( vga_rgb_tp[23:16] >= 8'd128 ) ? 8'hFF : 8'h00;
      vga_rgb[15:8 ] <= ( vga_rgb_tp[15:8 ] >= 8'd128 ) ? 8'hFF : 8'h00;
      vga_rgb[7:0  ] <= ( vga_rgb_tp[7:0  ] >= 8'd128 ) ? 8'hFF : 8'h00;
    end else begin
      if ( mode_bit_p1 == 0 ) begin
        demo_mode <= ~demo_mode[3:0];
      end
        if ( demo_mode[0] == 0 ) begin
        vga_rgb[23:16] <= ( vga_rgb_ball[23:16] >= 8'd128 ) ? 8'hFF : 8'h00;
        vga_rgb[15:8 ] <= ( vga_rgb_ball[15:8 ] >= 8'd128 ) ? 8'hFF : 8'h00;
        vga_rgb[7:0  ] <= ( vga_rgb_ball[7:0  ] >= 8'd128 ) ? 8'hFF : 8'h00;
      end else begin
        vga_rgb[23:16] <= ( vga_rgb_line[23:16] >= 8'd128 ) ? 8'hFF : 8'h00;
        vga_rgb[15:8 ] <= ( vga_rgb_line[15:8 ] >= 8'd128 ) ? 8'hFF : 8'h00;
        vga_rgb[7:0  ] <= ( vga_rgb_line[7:0  ] >= 8'd128 ) ? 8'hFF : 8'h00;
      end 
    end 
  end
 end
end





always @ ( posedge clk_dot ) begin : proc_line
 begin
  if ( mode_bit == 0 ) begin
    line_x_pos <= 16'd400;
    line_y_pos <= 16'd300;
    line_rgb   <= random_num[23:0];
  end else begin
    if ( u0_vid_new_frame == 1 ) begin
      line_x_pos <= line_x_pos - 1;
      line_y_pos <= line_y_pos - 1;
      if ( line_x_pos == 16'd0 || line_y_pos == 16'd0 ) begin
        line_x_pos <= 16'd400;
        line_y_pos <= 16'd300;
        line_rgb   <= random_num[23:0];
      end
    end
    vga_rgb_line[23:0] <= { 8'd0, 8'd0, 8'd0 };
    if ( u0_pel_x == 16'd400 - line_x_pos[15:0] ||
         u0_pel_x == 16'd400 + line_x_pos[15:0] ||
         u0_pel_y == 16'd300 - line_y_pos[15:0] ||
         u0_pel_y == 16'd300 + line_y_pos[15:0]    ) begin
      vga_rgb_line[23:0] <= { 1'b1, line_rgb[22:0] };
    end
  end
 end
end





always @ ( posedge clk_dot ) begin : proc_ball
 begin
  if ( mode_bit == 0 ) begin
    ball_x_pos <= {8'd0, 8'd400, 8'd0 };
    ball_y_pos <= {8'd0, 8'd300, 8'd0 };
    ball_rgb   <= random_num[23:0];
    ball_x_dir <= { 2'b01, random_num[11:2]  };
    ball_y_dir <= { 2'b01, random_num[23:14] };
  end else begin



    if ( u0_vid_new_frame == 1 ) begin
      dir_chg_sr <= { dir_chg_sr[2:0], 1'b0 };
      ball_x_pos <= ball_x_pos + { {12{ball_x_dir[11]}}, ball_x_dir[11:0] };
      ball_y_pos <= ball_y_pos + { {12{ball_y_dir[11]}}, ball_y_dir[11:0] };
      
      if          ( ball_x_pos[23:8] <  32 && dir_chg_sr == 4'd0 ) begin
        ball_x_dir    <= ~ ball_x_dir[11:0];
        dir_chg_sr[0] <= 1;
      end else if ( ball_x_pos[23:8] > 768 && dir_chg_sr == 4'd0 ) begin
        ball_x_dir    <= ~ ball_x_dir[11:0];
        dir_chg_sr[0] <= 1;
      end
      if          ( ball_y_pos[23:8] <  32 && dir_chg_sr == 4'd0 ) begin
        ball_y_dir    <= ~ ball_y_dir[11:0];
        dir_chg_sr[0] <= 1;
      end else if ( ball_y_pos[23:8] > 550 && dir_chg_sr == 4'd0 ) begin
        ball_y_dir    <= ~ ball_y_dir[11:0];
        dir_chg_sr[0] <= 1;
      end
      if ( dir_chg_sr[0] == 1 ) begin
        ball_rgb   <= random_num[23:0];
      end
    end

    vga_rgb_ball[23:0] <= { 8'h00, 8'h00, 8'h00 };

    if ( u0_pel_x > ball_x_pos[23:8] - 16'd8  &&
         u0_pel_x < ball_x_pos[23:8] + 16'd8  &&
         u0_pel_y > ball_y_pos[23:8] - 16'd8  &&
         u0_pel_y < ball_y_pos[23:8] + 16'd8     ) begin
      vga_rgb_ball[23:0] <= { 1'b1, ball_rgb[22:0] };
    end
  end
 end
end





always @ ( posedge clk_dot ) begin : proc_test_pattern 
 begin

  if          ( u0_pel_x[9:7] == 3'd6 ) begin
    vga_rgb_tp <= { ramp, ramp, ramp };
  end else if ( u0_pel_x[9:7] == 3'd5 ) begin
    vga_rgb_tp <= { ramp, ramp, 8'd0 };
  end else if ( u0_pel_x[9:7] == 3'd4 ) begin
    vga_rgb_tp <= { 8'd0, ramp, ramp };
  end else if ( u0_pel_x[9:7] == 3'd3 ) begin
    vga_rgb_tp <= { 8'd0, ramp, 8'd0 };
  end else if ( u0_pel_x[9:7] == 3'd2 ) begin
    vga_rgb_tp <= { ramp, 8'd0, ramp };
  end else if ( u0_pel_x[9:7] == 3'd1 ) begin
    vga_rgb_tp <= { ramp, 8'd0, 8'd0 };
  end else if ( u0_pel_x[9:7] == 3'd0 ) begin
    vga_rgb_tp <= { 8'd0, 8'd0, ramp };
  end

 end
end





always @ ( posedge clk_dot ) begin : proc_u0_raster_cnt
 begin
  if ( u0_vid_new_frame == 1 ) begin
    u0_pel_y <= 16'd0;
  end else if ( u0_vid_new_line == 1 ) begin
    if ( u0_pel_y == 16'hFFFF ) begin
      u0_pel_y <= 16'hFFFF;
    end else begin
      u0_pel_y <= u0_pel_y + 1;
    end
  end

  if ( u0_vid_new_line == 1 ) begin
    u0_pel_x <= 16'd0;
  end else begin
    if ( u0_pel_x == 16'hFFFF ) begin
      u0_pel_x <= 16'hFFFF;
    end else begin
      u0_pel_x <= u0_pel_x + 1;
    end
  end

 end
end





vga_timing u0_vga_timing
(
  .reset                           ( reset             ),
  .clk_dot                         ( clk_dot           ),
  .vid_new_frame                   ( u0_vid_new_frame  ),
  .vid_new_line                    ( u0_vid_new_line   ),
  .vid_active                      ( u0_vid_active     ),
  .vga_hsync                       ( u0_vga_hsync      ),
  .vga_vsync                       ( u0_vga_vsync      )
);


endmodule
module vga_core
(
  input  wire         reset,
  input  wire         color_3b,
  input  wire         mode_bit,
  input  wire         clk_dot,
  input  wire  [31:0] random_num,
  output wire  [23:0] vga_pixel_rgb,
  output wire         vga_active,
  output wire         vga_hsync,
  output wire         vga_vsync
);


  reg  [15:0]   u0_pel_x;
  reg  [15:0]   u0_pel_y;
  reg  [23:0]   vga_rgb_tp;
  reg  [23:0]   vga_rgb_ball;
  reg  [23:0]   vga_rgb_line;
  reg  [23:0]   vga_rgb;
  wire [7:0]    ramp;
  reg  [15:0]   ball_x_dir;
  reg  [15:0]   ball_y_dir;
  reg  [23:0]   ball_x_pos;
  reg  [23:0]   ball_y_pos;
  reg  [3:0]    dir_chg_sr;
  reg  [23:0]   ball_rgb;
  reg  [3:0]    demo_mode;
  reg           mode_bit_p1;
  reg  [15:0]   line_x_pos;
  reg  [15:0]   line_y_pos;
  reg  [23:0]   line_rgb;


  wire          u0_vid_new_frame;
  wire          u0_vid_new_line;
  wire          u0_vid_active;
  wire          u0_vga_hsync;
  wire          u0_vga_vsync;

  assign vga_active    = u0_vid_active;
  assign vga_hsync     = u0_vga_hsync;
  assign vga_vsync     = u0_vga_vsync;
  assign vga_pixel_rgb = vga_rgb[23:0];
  assign ramp          = { u0_pel_x[6:0], 1'b0 };





always @ ( posedge clk_dot ) begin : proc_out_mux 
 begin
  mode_bit_p1 <= mode_bit;
  if ( color_3b == 0 ) begin
    if ( mode_bit == 0 ) begin
      vga_rgb <= vga_rgb_tp[23:0];
    end else begin
      if ( mode_bit_p1 == 0 ) begin
        demo_mode <= ~demo_mode[3:0];
      end
        if ( demo_mode[0] == 0 ) begin
        vga_rgb <= vga_rgb_ball[23:0];
      end else begin
        vga_rgb <= vga_rgb_line[23:0];
      end 
    end 
  end else begin
    if ( mode_bit == 0 ) begin
      vga_rgb[23:16] <= ( vga_rgb_tp[23:16] >= 8'd128 ) ? 8'hFF : 8'h00;
      vga_rgb[15:8 ] <= ( vga_rgb_tp[15:8 ] >= 8'd128 ) ? 8'hFF : 8'h00;
      vga_rgb[7:0  ] <= ( vga_rgb_tp[7:0  ] >= 8'd128 ) ? 8'hFF : 8'h00;
    end else begin
      if ( mode_bit_p1 == 0 ) begin
        demo_mode <= ~demo_mode[3:0];
      end
        if ( demo_mode[0] == 0 ) begin
        vga_rgb[23:16] <= ( vga_rgb_ball[23:16] >= 8'd128 ) ? 8'hFF : 8'h00;
        vga_rgb[15:8 ] <= ( vga_rgb_ball[15:8 ] >= 8'd128 ) ? 8'hFF : 8'h00;
        vga_rgb[7:0  ] <= ( vga_rgb_ball[7:0  ] >= 8'd128 ) ? 8'hFF : 8'h00;
      end else begin
        vga_rgb[23:16] <= ( vga_rgb_line[23:16] >= 8'd128 ) ? 8'hFF : 8'h00;
        vga_rgb[15:8 ] <= ( vga_rgb_line[15:8 ] >= 8'd128 ) ? 8'hFF : 8'h00;
        vga_rgb[7:0  ] <= ( vga_rgb_line[7:0  ] >= 8'd128 ) ? 8'hFF : 8'h00;
      end 
    end 
  end
 end
end





always @ ( posedge clk_dot ) begin : proc_line
 begin
  if ( mode_bit == 0 ) begin
    line_x_pos <= 16'd400;
    line_y_pos <= 16'd300;
    line_rgb   <= random_num[23:0];
  end else begin
    if ( u0_vid_new_frame == 1 ) begin
      line_x_pos <= line_x_pos - 1;
      line_y_pos <= line_y_pos - 1;
      if ( line_x_pos == 16'd0 || line_y_pos == 16'd0 ) begin
        line_x_pos <= 16'd400;
        line_y_pos <= 16'd300;
        line_rgb   <= random_num[23:0];
      end
    end
    vga_rgb_line[23:0] <= { 8'd0, 8'd0, 8'd0 };
    if ( u0_pel_x == 16'd400 - line_x_pos[15:0] ||
         u0_pel_x == 16'd400 + line_x_pos[15:0] ||
         u0_pel_y == 16'd300 - line_y_pos[15:0] ||
         u0_pel_y == 16'd300 + line_y_pos[15:0]    ) begin
      vga_rgb_line[23:0] <= { 1'b1, line_rgb[22:0] };
    end
  end
 end
end





always @ ( posedge clk_dot ) begin : proc_ball
 begin
  if ( mode_bit == 0 ) begin
    ball_x_pos <= {8'd0, 8'd400, 8'd0 };
    ball_y_pos <= {8'd0, 8'd300, 8'd0 };
    ball_rgb   <= random_num[23:0];
    ball_x_dir <= { 2'b01, random_num[11:2]  };
    ball_y_dir <= { 2'b01, random_num[23:14] };
  end else begin



    if ( u0_vid_new_frame == 1 ) begin
      dir_chg_sr <= { dir_chg_sr[2:0], 1'b0 };
      ball_x_pos <= ball_x_pos + { {12{ball_x_dir[11]}}, ball_x_dir[11:0] };
      ball_y_pos <= ball_y_pos + { {12{ball_y_dir[11]}}, ball_y_dir[11:0] };
      
      if          ( ball_x_pos[23:8] <  32 && dir_chg_sr == 4'd0 ) begin
        ball_x_dir    <= ~ ball_x_dir[11:0];
        dir_chg_sr[0] <= 1;
      end else if ( ball_x_pos[23:8] > 768 && dir_chg_sr == 4'd0 ) begin
        ball_x_dir    <= ~ ball_x_dir[11:0];
        dir_chg_sr[0] <= 1;
      end
      if          ( ball_y_pos[23:8] <  32 && dir_chg_sr == 4'd0 ) begin
        ball_y_dir    <= ~ ball_y_dir[11:0];
        dir_chg_sr[0] <= 1;
      end else if ( ball_y_pos[23:8] > 550 && dir_chg_sr == 4'd0 ) begin
        ball_y_dir    <= ~ ball_y_dir[11:0];
        dir_chg_sr[0] <= 1;
      end
      if ( dir_chg_sr[0] == 1 ) begin
        ball_rgb   <= random_num[23:0];
      end
    end

    vga_rgb_ball[23:0] <= { 8'h00, 8'h00, 8'h00 };

    if ( u0_pel_x > ball_x_pos[23:8] - 16'd8  &&
         u0_pel_x < ball_x_pos[23:8] + 16'd8  &&
         u0_pel_y > ball_y_pos[23:8] - 16'd8  &&
         u0_pel_y < ball_y_pos[23:8] + 16'd8     ) begin
      vga_rgb_ball[23:0] <= { 1'b1, ball_rgb[22:0] };
    end
  end
 end
end





always @ ( posedge clk_dot ) begin : proc_test_pattern 
 begin

  if          ( u0_pel_x[9:7] == 3'd6 ) begin
    vga_rgb_tp <= { ramp, ramp, ramp };
  end else if ( u0_pel_x[9:7] == 3'd5 ) begin
    vga_rgb_tp <= { ramp, ramp, 8'd0 };
  end else if ( u0_pel_x[9:7] == 3'd4 ) begin
    vga_rgb_tp <= { 8'd0, ramp, ramp };
  end else if ( u0_pel_x[9:7] == 3'd3 ) begin
    vga_rgb_tp <= { 8'd0, ramp, 8'd0 };
  end else if ( u0_pel_x[9:7] == 3'd2 ) begin
    vga_rgb_tp <= { ramp, 8'd0, ramp };
  end else if ( u0_pel_x[9:7] == 3'd1 ) begin
    vga_rgb_tp <= { ramp, 8'd0, 8'd0 };
  end else if ( u0_pel_x[9:7] == 3'd0 ) begin
    vga_rgb_tp <= { 8'd0, 8'd0, ramp };
  end

 end
end





always @ ( posedge clk_dot ) begin : proc_u0_raster_cnt
 begin
  if ( u0_vid_new_frame == 1 ) begin
    u0_pel_y <= 16'd0;
  end else if ( u0_vid_new_line == 1 ) begin
    if ( u0_pel_y == 16'hFFFF ) begin
      u0_pel_y <= 16'hFFFF;
    end else begin
      u0_pel_y <= u0_pel_y + 1;
    end
  end

  if ( u0_vid_new_line == 1 ) begin
    u0_pel_x <= 16'd0;
  end else begin
    if ( u0_pel_x == 16'hFFFF ) begin
      u0_pel_x <= 16'hFFFF;
    end else begin
      u0_pel_x <= u0_pel_x + 1;
    end
  end

 end
end





vga_timing u0_vga_timing
(
  .reset                           ( reset             ),
  .clk_dot                         ( clk_dot           ),
  .vid_new_frame                   ( u0_vid_new_frame  ),
  .vid_new_line                    ( u0_vid_new_line   ),
  .vid_active                      ( u0_vid_active     ),
  .vga_hsync                       ( u0_vga_hsync      ),
  .vga_vsync                       ( u0_vga_vsync      )
);


endmodule