data/full_repos/permissive/143278/ivltests/vhdl_test2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_test2.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #1 if (out !== out_ref) begin\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_test2.v:7: Cannot find file containing module: \'mask\'\n   mask dut (.\\output (out), .\\input (in[15:0]), .mask(mask));\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/mask\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/mask.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/mask.sv\n             mask\n             mask.v\n             mask.sv\n             obj_dir/mask\n             obj_dir/mask.v\n             obj_dir/mask.sv\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_test2.v:12: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                          : ... In instance main\n  mask = $random;\n       ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire [15:0] out;
   reg [16:0]  in;
   reg [15:0]  mask;

   mask dut (.\output (out), .\input (in[15:0]), .mask(mask));

   wire [15:0] out_ref = in[15:0] & mask;
   initial begin
      for (in = 0 ; in[16] == 0 ; in = in+1) begin
	 mask = $random;
	 #1 if (out !== out_ref) begin
	    $display("FAILED: in=%b, out=%b, mask=%b, out_ref=%b", in, out, mask, out_ref);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule
module main;


   wire [15:0] out;
   reg [16:0]  in;
   reg [15:0]  mask;

   mask dut (.\output (out), .\input (in[15:0]), .mask(mask));

   wire [15:0] out_ref = in[15:0] & mask;
   initial begin
      for (in = 0 ; in[16] == 0 ; in = in+1) begin
	 mask = $random;
	 #1 if (out !== out_ref) begin
	    $display("FAILED: in=%b, out=%b, mask=%b, out_ref=%b", in, out, mask, out_ref);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule