data/full_repos/permissive/187199324/stannel/FetchInstruction.v
1: b'%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:3: Define or directive not defined: \'`ADDRESS_BITS\'\nmodule FetchInstruction #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:3: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nmodule FetchInstruction #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                            ^\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:3: Define or directive not defined: \'`DATA_BITS\'\nmodule FetchInstruction #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:3: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule FetchInstruction #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                                                             ^\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:6: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                reset,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:7: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                useInternalProgramCounter,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:8: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [addrBits-1:0] programAddress,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [dataBits-1:0] programDataOut,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:10: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                finished,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [8:0]          programCounter,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [7:0]          instruction,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [8:0]          nextProgramCounter\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:15: syntax error, unexpected \')\', expecting \',\' or \';\'\n  );\n  ^\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:19: syntax error, unexpected assign\n  assign instruction = rInstruction;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:22: syntax error, unexpected assign\n  assign programAddress = wProgramAddress;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:25: syntax error, unexpected assign\n  assign nextProgramCounter = rInternalProgramCounter;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:35: syntax error, unexpected assign\n  assign finished = rState == STATE_DONE;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchInstruction.v:43: syntax error, unexpected always\n  always @(posedge clk)\n  ^~~~~~\n%Error: Exiting due to 19 error(s)\n'
module FetchInstruction #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    input  wire                useInternalProgramCounter,
    output wire [addrBits-1:0] programAddress,
    input  wire [dataBits-1:0] programDataOut,
    output wire                finished,

    input  wire [8:0]          programCounter,
    output wire [7:0]          instruction,
    output wire [8:0]          nextProgramCounter
  );


  reg [7:0] rInstruction;
  assign instruction = rInstruction;

  reg [addrBits-1:0] wProgramAddress;
  assign programAddress = wProgramAddress;

  reg [8:0] rInternalProgramCounter;
  assign nextProgramCounter = rInternalProgramCounter;

  reg [8:0] wActualProgramCounter;
  wire [7:0] instructionFromRamOut = wActualProgramCounter[0] ? programDataOut[7:0] : programDataOut[15:8];



  localparam STATE_PREPARE = 0;
  localparam STATE_DONE    = 1;

  assign finished = rState == STATE_DONE;

  reg rState;

  reg wNextState;
  reg wUpdateInstruction;
  reg wIncrementInternalProgramCounter;

  always @(posedge clk)
    begin
      if (wUpdateInstruction)
        rInstruction <= instructionFromRamOut;

      if (wIncrementInternalProgramCounter)
        rInternalProgramCounter <= rInternalProgramCounter + 1;
      else if (~useInternalProgramCounter)
        rInternalProgramCounter <= programCounter;

      if (!reset)
        rState <= 0;
      else
        rState <= wNextState;
    end

  always @(*)
  begin
    wActualProgramCounter = useInternalProgramCounter ? rInternalProgramCounter : programCounter;
    wProgramAddress = wActualProgramCounter[8:1];
    wNextState = rState + 1;
    wIncrementInternalProgramCounter = rState == STATE_DONE;
    wUpdateInstruction = rState == STATE_DONE;
  end

endmodule
module FetchInstruction #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    input  wire                useInternalProgramCounter,
    output wire [addrBits-1:0] programAddress,
    input  wire [dataBits-1:0] programDataOut,
    output wire                finished,

    input  wire [8:0]          programCounter,
    output wire [7:0]          instruction,
    output wire [8:0]          nextProgramCounter
  );



  reg [7:0] rInstruction;
  assign instruction = rInstruction;

  reg [addrBits-1:0] wProgramAddress;
  assign programAddress = wProgramAddress;

  reg [8:0] rInternalProgramCounter;
  assign nextProgramCounter = rInternalProgramCounter;

  reg [8:0] wActualProgramCounter;
  wire [7:0] instructionFromRamOut = wActualProgramCounter[0] ? programDataOut[7:0] : programDataOut[15:8];



  localparam STATE_PREPARE = 0;
  localparam STATE_DONE    = 1;

  assign finished = rState == STATE_DONE;

  reg rState;

  reg wNextState;
  reg wUpdateInstruction;
  reg wIncrementInternalProgramCounter;

  always @(posedge clk)
    begin
      if (wUpdateInstruction)
        rInstruction <= instructionFromRamOut;

      if (wIncrementInternalProgramCounter)
        rInternalProgramCounter <= rInternalProgramCounter + 1;
      else if (~useInternalProgramCounter)
        rInternalProgramCounter <= programCounter;

      if (!reset)
        rState <= 0;
      else
        rState <= wNextState;
    end

  always @(*)
  begin
    wActualProgramCounter = useInternalProgramCounter ? rInternalProgramCounter : programCounter;
    wProgramAddress = wActualProgramCounter[8:1];
    wNextState = rState + 1;
    wIncrementInternalProgramCounter = rState == STATE_DONE;
    wUpdateInstruction = rState == STATE_DONE;
  end

endmodule