data/full_repos/permissive/136610640/soc_system/submodules/altera_jtag_streaming.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/136610640/soc_system/submodules/altera_jtag_streaming.v:184: Operator ASSIGNW expects 19 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 18 bits.\n                                                                                                      : ... In instance altera_jtag_streaming\n    assign decoded_scan_length =  { scan_length, {8{1\'b1}} };\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/136610640/soc_system/submodules/altera_jtag_streaming.v:219: Cannot find file containing module: \'altera_std_synchronizer\'\n    altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_sensor_synchronizer (\n    ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136610640/soc_system/submodules,data/full_repos/permissive/136610640/altera_std_synchronizer\n             data/full_repos/permissive/136610640/soc_system/submodules,data/full_repos/permissive/136610640/altera_std_synchronizer.v\n             data/full_repos/permissive/136610640/soc_system/submodules,data/full_repos/permissive/136610640/altera_std_synchronizer.sv\n             altera_std_synchronizer\n             altera_std_synchronizer.v\n             altera_std_synchronizer.sv\n             obj_dir/altera_std_synchronizer\n             obj_dir/altera_std_synchronizer.v\n             obj_dir/altera_std_synchronizer.sv\n%Error: data/full_repos/permissive/136610640/soc_system/submodules/altera_jtag_streaming.v:225: Cannot find file containing module: \'altera_std_synchronizer\'\n    altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) reset_to_sample_synchronizer (\n    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136610640/soc_system/submodules/altera_jtag_streaming.v:231: Cannot find file containing module: \'altera_std_synchronizer\'\n    altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_to_sample_div2_synchronizer (\n    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136610640/soc_system/submodules/altera_jtag_streaming.v:237: Cannot find file containing module: \'altera_std_synchronizer\'\n    altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) clock_sense_reset_n_synchronizer (\n    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136610640/soc_system/submodules/altera_jtag_streaming.v:543: Cannot find file containing module: \'altera_jtag_sld_node\'\n    altera_jtag_sld_node node (\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136610640/soc_system/submodules/altera_jtag_streaming.v:560: Cannot find file containing module: \'altera_avalon_st_idle_remover\'\n    altera_avalon_st_idle_remover idle_remover (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136610640/soc_system/submodules/altera_jtag_streaming.v:577: Cannot find file containing module: \'altera_avalon_st_idle_inserter\'\n    altera_avalon_st_idle_inserter idle_inserter (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n'
function integer flog2;
      input [31:0] Depth;
      integer i;
      begin
        i = Depth;
        if ( i <= 0 ) flog2 = 0;
        else begin
          for(flog2 = -1; i > 0; flog2 = flog2 + 1)
          i = i >> 1;
        end
      end    
    endfunction
function integer flog2;

      input [31:0] Depth;
      integer i;
      begin
        i = Depth;
        if ( i <= 0 ) flog2 = 0;
        else begin
          for(flog2 = -1; i > 0; flog2 = flog2 + 1)
          i = i >> 1;
        end
      end    
    endfunction