data/full_repos/permissive/143278/ivltests/vhdl_inout.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_inout.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_inout.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_inout.v:24: Cannot find file containing module: \'vhdl_inout\'\nvhdl_inout dut(a, b, c);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_inout\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_inout.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_inout.sv\n             vhdl_inout\n             vhdl_inout.v\n             vhdl_inout.sv\n             obj_dir/vhdl_inout\n             obj_dir/vhdl_inout.v\n             obj_dir/vhdl_inout.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vhdl_inout_test;
logic a, b, c;
vhdl_inout dut(a, b, c);

initial begin
    b <= 1'b0;
    #1;
    if(a !== 1'b1 || c !== 1'b0) begin
        $display("FAILED 1");
        $finish();
    end

    b <= 1'b1;
    #1;
    if(a !== 1'b0 || c !== 1'b1) begin
        $display("FAILED 2");
        $finish();
    end

    $display("PASSED");
end
endmodule
module vhdl_inout_test;

logic a, b, c;
vhdl_inout dut(a, b, c);

initial begin
    b <= 1'b0;
    #1;
    if(a !== 1'b1 || c !== 1'b0) begin
        $display("FAILED 1");
        $finish();
    end

    b <= 1'b1;
    #1;
    if(a !== 1'b0 || c !== 1'b1) begin
        $display("FAILED 2");
        $finish();
    end

    $display("PASSED");
end
endmodule