data/full_repos/permissive/131069375/uv-risc/verilog/regfile.v
data/verilator_xmls/3d168395-51c3-45dd-a7fe-40242f4d5086.xml
module regfile
  (
 input 		   reset, clk,
 input 		   flags_we, reg_we, hi_we,
 input [2:0] 	   wr_sel, rd1_sel, rd2_sel,
 input [3:0] 	   flags_in,
 input [15:0] 	   data_in, hi_in,
 output reg [15:0] data1, data2,
 output reg [3:0]  flags
);
   
endmodule
module regfile
  (
 input 		   reset, clk,
 input 		   flags_we, reg_we, hi_we,
 input [2:0] 	   wr_sel, rd1_sel, rd2_sel,
 input [3:0] 	   flags_in,
 input [15:0] 	   data_in, hi_in,
 output reg [15:0] data1, data2,
 output reg [3:0]  flags
);

   
endmodule