data/full_repos/permissive/14636651/DataMemory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/14636651/DataMemory.v:16: Bit extraction of array[63:0] requires 6 bit index, not 16 bits.\n                                                                   : ... In instance DataMemory\n   mem[abus] = dbus_in;\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/14636651/DataMemory.v:20: Bit extraction of array[63:0] requires 6 bit index, not 16 bits.\n                                                                   : ... In instance DataMemory\n assign dbus_out = (read)? mem[abus] : 16\'bz;\n                              ^\n%Error: Exiting due to 2 warning(s)\n'
module DataMemory(input clk, read, write, input [15:0] abus, dbus_in, input rst, output [15:0] dbus_out);
	reg [15:0] mem [0:63];
	integer i;

	always@(posedge clk)
	begin
		if(rst)
		begin
			for(i = 0; i < 64; i=i+1 )
			begin
				mem[i] = 0;
			end
		end
		else if(write)
		begin
			mem[abus] = dbus_in;
		end
	end
	
	assign dbus_out = (read)? mem[abus] : 16'bz;
endmodule
module DataMemory(input clk, read, write, input [15:0] abus, dbus_in, input rst, output [15:0] dbus_out);

	reg [15:0] mem [0:63];
	integer i;

	always@(posedge clk)
	begin
		if(rst)
		begin
			for(i = 0; i < 64; i=i+1 )
			begin
				mem[i] = 0;
			end
		end
		else if(write)
		begin
			mem[abus] = dbus_in;
		end
	end
	
	assign dbus_out = (read)? mem[abus] : 16'bz;
endmodule