data/full_repos/permissive/220187565/wishbone_cyc10/wishbone_uart_lite.v
1: b'%Error: data/full_repos/permissive/220187565/wishbone_cyc10/wishbone_uart_lite.v:19: Cannot find include file: cpu/defines.v\n`include "cpu/defines.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220187565/wishbone_cyc10,data/full_repos/permissive/220187565/cpu/defines.v\n             data/full_repos/permissive/220187565/wishbone_cyc10,data/full_repos/permissive/220187565/cpu/defines.v.v\n             data/full_repos/permissive/220187565/wishbone_cyc10,data/full_repos/permissive/220187565/cpu/defines.v.sv\n             cpu/defines.v\n             cpu/defines.v.v\n             cpu/defines.v.sv\n             obj_dir/cpu/defines.v\n             obj_dir/cpu/defines.v.v\n             obj_dir/cpu/defines.v.sv\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/wishbone_uart_lite.v:30: Define or directive not defined: \'`WishboneDataBus\'\n input  [`WishboneDataBus]   wishbone_addr_i,\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/wishbone_uart_lite.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input  [`WishboneDataBus]   wishbone_addr_i,\n                         ^\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/wishbone_uart_lite.v:31: Define or directive not defined: \'`WishboneDataBus\'\n input  [`WishboneDataBus]    wishbone_data_i,\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/wishbone_uart_lite.v:33: Define or directive not defined: \'`WishboneSelBus\'\n input  [`WishboneSelBus]   wishbone_sel_i,\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/wishbone_uart_lite.v:36: Define or directive not defined: \'`WishboneDataBus\'\n output [`WishboneDataBus]    wishbone_data_o,\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/wishbone_uart_lite.v:52: syntax error, unexpected assign\n assign wishbone_ack_o = state == StateOk ? 1\'b1 : 1\'b0;\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/wishbone_uart_lite.v:57: Define or directive not defined: \'`RstEnable\'\n  if(resetn == `RstEnable) begin\n               ^~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module wishbone_uart_lite #(
	parameter ClkFreq   = 25000000,
	parameter BoundRate = 115200
)(
	input clk,
	input resetn,

	output ser_tx,
	input  ser_rx,

	input  [`WishboneDataBus]	  wishbone_addr_i,
	input  [`WishboneDataBus]    wishbone_data_i,
	input								  wishbone_we_i,
	input  [`WishboneSelBus]	  wishbone_sel_i,
	input 							  wishbone_stb_i,
	input								  wishbone_cyc_i,
	output [`WishboneDataBus]    wishbone_data_o,
	output							  wishbone_ack_o

);
	localparam CfgDivder = ClkFreq/BoundRate;
	localparam StateIdle = 2'b00;
	localparam StateReq  = 2'b01;
	localparam StateWait = 2'b10;
	localparam StateOk	= 2'b11;
	
	reg [9:0] send_pattern;
	reg [3:0] send_bitcnt;
	reg [9:0] send_divcnt;
	reg [1:0] state;
	
	wire req = wishbone_cyc_i && wishbone_stb_i && wishbone_we_i;
	assign wishbone_ack_o = state == StateOk ? 1'b1 : 1'b0;
	assign wishbone_data_o = 32'b0;
	assign ser_tx = send_pattern[0];
	
	always @(posedge clk) begin
		if(resetn == `RstEnable) begin
			state <= StateIdle;
			send_pattern[0] = 1'b1;
		end else begin
		case(state)
			StateIdle: begin
				if(req) begin
					state <= StateReq;
					send_pattern <= {1'b1, wishbone_data_i[7:0], 1'b0};
					send_bitcnt <= 10;
					send_divcnt <= 0;
				end else begin
					send_pattern <= ~0;
					send_bitcnt <= 0;
					send_divcnt <= 0;
				end
			end
			StateReq: begin
				if(send_bitcnt == 0) begin
					state <= StateOk;
				end else if(send_divcnt >= CfgDivder) begin
					send_pattern <= {1'b1, send_pattern[9:1]};
					send_bitcnt <= send_bitcnt - 1;
					send_divcnt <= 0;
				end else begin
					send_divcnt = send_divcnt + 1;
				end
			end
			StateOk: begin
				state <= StateIdle;
				send_pattern[0] = 1'b1;
			end
		endcase
		end
	end
		

endmodule
module wishbone_uart_lite #(
	parameter ClkFreq   = 25000000,
	parameter BoundRate = 115200
)(
	input clk,
	input resetn,

	output ser_tx,
	input  ser_rx,

	input  [`WishboneDataBus]	  wishbone_addr_i,
	input  [`WishboneDataBus]    wishbone_data_i,
	input								  wishbone_we_i,
	input  [`WishboneSelBus]	  wishbone_sel_i,
	input 							  wishbone_stb_i,
	input								  wishbone_cyc_i,
	output [`WishboneDataBus]    wishbone_data_o,
	output							  wishbone_ack_o

);

	localparam CfgDivder = ClkFreq/BoundRate;
	localparam StateIdle = 2'b00;
	localparam StateReq  = 2'b01;
	localparam StateWait = 2'b10;
	localparam StateOk	= 2'b11;
	
	reg [9:0] send_pattern;
	reg [3:0] send_bitcnt;
	reg [9:0] send_divcnt;
	reg [1:0] state;
	
	wire req = wishbone_cyc_i && wishbone_stb_i && wishbone_we_i;
	assign wishbone_ack_o = state == StateOk ? 1'b1 : 1'b0;
	assign wishbone_data_o = 32'b0;
	assign ser_tx = send_pattern[0];
	
	always @(posedge clk) begin
		if(resetn == `RstEnable) begin
			state <= StateIdle;
			send_pattern[0] = 1'b1;
		end else begin
		case(state)
			StateIdle: begin
				if(req) begin
					state <= StateReq;
					send_pattern <= {1'b1, wishbone_data_i[7:0], 1'b0};
					send_bitcnt <= 10;
					send_divcnt <= 0;
				end else begin
					send_pattern <= ~0;
					send_bitcnt <= 0;
					send_divcnt <= 0;
				end
			end
			StateReq: begin
				if(send_bitcnt == 0) begin
					state <= StateOk;
				end else if(send_divcnt >= CfgDivder) begin
					send_pattern <= {1'b1, send_pattern[9:1]};
					send_bitcnt <= send_bitcnt - 1;
					send_divcnt <= 0;
				end else begin
					send_divcnt = send_divcnt + 1;
				end
			end
			StateOk: begin
				state <= StateIdle;
				send_pattern[0] = 1'b1;
			end
		endcase
		end
	end
		

endmodule