data/full_repos/permissive/150482260/reg_file_32x32.v
 line:95: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #10 clear = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:57: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clock = ~clock;\n                ^\n%Error: data/full_repos/permissive/150482260/reg_file_32x32.v:61: Unsupported or unknown PLI call: $monitor\n        $monitor({\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #10 read_index1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #10 read_index1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #10 read_index1 = 7;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #10 read_index1 = 4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reg_file_32x32 (
    input clear,
    input clock,
    input [4:0] read_index1,
    input write1,
    input [4:0] write_index1,
    input [31:0] write_data1,
    input write2,
    input [4:0] write_index2,
    input [31:0] write_data2,
    output [31:0] read_value
);

    reg [31:0] data[0:31];
    integer i;

    assign read_value = data[read_index1];

    always @(negedge clock, posedge clear)
        if (clear)
            for (i = 0; i < 32; i = i + 1)
                data[i] = 0;
        else begin
            if (write2)
                data[write_index2] = write_data2;
            if (write1)
                data[write_index1] = write_data1;
        end
endmodule
module reg_file_32x32 (
    input clear,
    input clock,
    input [4:0] read_index1,
    input write1,
    input [4:0] write_index1,
    input [31:0] write_data1,
    input write2,
    input [4:0] write_index2,
    input [31:0] write_data2,
    output [31:0] read_value
);


    reg [31:0] data[0:31];
    integer i;

    assign read_value = data[read_index1];

    always @(negedge clock, posedge clear)
        if (clear)
            for (i = 0; i < 32; i = i + 1)
                data[i] = 0;
        else begin
            if (write2)
                data[write_index2] = write_data2;
            if (write1)
                data[write_index1] = write_data1;
        end
endmodule