data/full_repos/permissive/115035459/verilog/src/lib/histogram.v
 line:313: before: "if"
1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:7: Cannot find include file: RAM8.v\n`include "RAM8.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/RAM8.v\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/RAM8.v.v\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/RAM8.v.sv\n             RAM8.v\n             RAM8.v.v\n             RAM8.v.sv\n             obj_dir/RAM8.v\n             obj_dir/RAM8.v.v\n             obj_dir/RAM8.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:8: Cannot find include file: fifo.v\n`include "fifo.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:9: Cannot find include file: generic.v\n`include "generic.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:22: Define or directive not defined: \'`LOG2_OF_BASE_BLOCK_MEMORY_SIZE\'\n parameter PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + $clog2(DATA_WIDTH) - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE,\n                                                                                                                                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:22: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n parameter PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + $clog2(DATA_WIDTH) - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE,\n                                                                                                                                                                         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:24: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST = LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE - LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:25: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter USE_BLOCK_MEMORY = 1\n ^~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:26: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg partial_count_reached = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:41: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg max_count_reached = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:42: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg adding_finished = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:43: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg result_valid = 0,\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:44: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output [31:0] error_count\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:77: syntax error, unexpected assign\n assign ram_read_address   = { {RAM_ADDRESS_DEPTH-DATA_WIDTH{1\'b0}}, adding_not_comparing ? data_out_from_fifo : j };\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:92: syntax error, unexpected always\n  always @(posedge clock) begin\n  ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:414: Unsupported: Ignoring delay on this delayed statement.\n  #100; reset <= 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:415: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:415: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:415: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:416: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:416: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:416: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:417: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:417: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:417: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:418: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:418: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:418: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:419: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:419: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:419: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:420: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:420: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:420: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:421: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:421: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:421: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:422: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:422: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:422: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:423: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:423: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:423: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:424: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:424: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:424: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:425: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:425: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:425: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:426: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:426: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:426: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:427: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:427: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:427: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:428: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:428: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:428: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:429: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:429: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:429: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h15; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:430: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h22; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:430: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h22; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:430: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h22; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:431: Unsupported: Ignoring delay on this delayed statement.\n  #80; @(negedge partial_count_reached); #80;\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:431: syntax error, unexpected \'@\'\n  #80; @(negedge partial_count_reached); #80;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:431: Unsupported: Ignoring delay on this delayed statement.\n  #80; @(negedge partial_count_reached); #80;\n                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:432: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:432: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:432: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:433: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:433: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:433: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:434: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:434: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:434: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:435: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:435: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:435: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:436: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:436: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:436: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:437: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:437: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:437: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:438: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:438: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:438: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:439: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:439: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:439: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:440: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:440: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:440: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:441: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:441: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:441: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h10; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:442: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:442: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:442: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:443: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:443: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:443: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:444: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:444: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:444: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:445: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:445: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:445: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:446: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:446: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:446: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:447: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:447: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:447: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h06; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:448: Unsupported: Ignoring delay on this delayed statement.\n  #80; @(negedge partial_count_reached); #80;\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:448: syntax error, unexpected \'@\'\n  #80; @(negedge partial_count_reached); #80;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:448: Unsupported: Ignoring delay on this delayed statement.\n  #80; @(negedge partial_count_reached); #80;\n                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:451: Unsupported: Ignoring delay on this delayed statement.\n  #(4*13);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:453: Unsupported: Ignoring delay on this delayed statement.\n  #(4*3);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:455: Unsupported: Ignoring delay on this delayed statement.\n  #80; @(negedge partial_count_reached); #80;\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:455: syntax error, unexpected \'@\'\n  #80; @(negedge partial_count_reached); #80;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:455: Unsupported: Ignoring delay on this delayed statement.\n  #80; @(negedge partial_count_reached); #80;\n                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:456: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:456: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:456: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:457: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:457: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:457: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:458: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:458: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:458: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:459: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:459: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:459: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:460: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:460: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:460: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:461: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:461: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:461: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:462: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:462: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:462: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:463: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:463: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:463: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:464: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:464: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:464: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:465: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:465: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:465: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:466: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:466: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:466: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:467: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:467: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:467: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:468: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:468: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:468: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:469: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:469: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:469: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:470: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:470: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:470: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:471: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:471: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:471: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h55; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:472: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:472: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:472: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'haa; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:473: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:473: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:473: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:474: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:474: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:474: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h44; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:475: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:475: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:475: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h11; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:476: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:476: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:476: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h99; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:477: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:477: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:477: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h51; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:478: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:478: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:478: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h38; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:479: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:479: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:479: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h83; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:480: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:481: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d23; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:481: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d23; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:481: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d23; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:482: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d29; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:482: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d29; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:482: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d29; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:483: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d31; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:483: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d31; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:483: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d31; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:484: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d37; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:484: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d37; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:484: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d37; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:485: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d41; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:485: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d41; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:485: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d41; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:486: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d43; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:486: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d43; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:486: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d43; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:487: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d47; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:487: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d47; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:487: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d47; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:488: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d53; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:488: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d53; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:488: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d53; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:489: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d59; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:489: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d59; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:489: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d59; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:490: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d61; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:490: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d61; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:490: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d61; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:491: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d67; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:491: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d67; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:491: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d67; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:492: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d71; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:492: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d71; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:492: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d71; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:493: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d73; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:493: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d73; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:493: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d73; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:494: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d79; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:494: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d79; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:494: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d79; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:495: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d83; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:495: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d83; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:495: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d83; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:496: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d89; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:496: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d89; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:496: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d89; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:497: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d97; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:497: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d97; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:497: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'d97; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:498: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:499: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h84; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:499: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h84; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:499: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h84; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:500: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h85; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:500: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h85; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:500: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h85; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:501: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h86; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:501: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h86; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:501: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h86; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:502: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h87; #4; sample <= 1; #4; sample <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:502: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h87; #4; sample <= 1; #4; sample <= 0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:502: Unsupported: Ignoring delay on this delayed statement.\n  #20; data_in <= 8\'h87; #4; sample <= 1; #4; sample <= 0;\n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:503: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:504: Unsupported: Ignoring delay on this delayed statement.\n  #20; @(posedge result_valid);\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:504: syntax error, unexpected \'@\'\n  #20; @(posedge result_valid);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:505: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:506: Unsupported: Ignoring delay on this delayed statement.\n  #1000; clear_results <= 1; #4; clear_results <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:506: Unsupported: Ignoring delay on this delayed statement.\n  #1000; clear_results <= 1; #4; clear_results <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:507: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/histogram.v:508: Unsupported: Ignoring delay on this delayed statement.\n  #100; $finish;\n  ^\n%Error: Exiting due to 19 error(s), 249 warning(s)\n'
module histogram #(
	parameter DATA_WIDTH = 4,
	parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE = 4,
	parameter TESTBENCH = 0,
	parameter PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + $clog2(DATA_WIDTH) - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE,
	parameter LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO < 0 ? 0 : PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO,
	parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST = LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE - LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO,
	parameter USE_BLOCK_MEMORY = 1
) (
	input reset, clock,
	input sample,
	input clear_results,
	input [DATA_WIDTH-1:0] data_in,
	output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count00,
	output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count01,
	output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count02,
	output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count03,
	output [DATA_WIDTH-1:0] result00,
	output [DATA_WIDTH-1:0] result01,
	output [DATA_WIDTH-1:0] result02,
	output [DATA_WIDTH-1:0] result03,
	output reg [LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO-1:0] capture_completion = 0,
	output reg partial_count_reached = 0,
	output reg max_count_reached = 0,
	output reg adding_finished = 0,
	output reg result_valid = 0,
	output [31:0] error_count
);
	localparam MAX_INDEX = (1<<DATA_WIDTH) - 1;
	localparam MAXIMUM_SAMPLE_NUMBER = (1<<LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST) - 1;
	localparam LOG2_OF_NUMBER_OF_RESULTS = 2;
	localparam LAST_RESULT = (1<<LOG2_OF_NUMBER_OF_RESULTS) - 1;

	localparam RAM_DATA_WIDTH = USE_BLOCK_MEMORY ? 32 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE;
	localparam RAM_ADDRESS_DEPTH = USE_BLOCK_MEMORY ? 9 : DATA_WIDTH;
	localparam LAST_FIFO_FILL_NUMBER = (1<<LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO) - 1;
	reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count_copy [LAST_RESULT:0];
	reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST-1:0] sample_counter = 0;
	reg [LAST_RESULT:0] i = 0;
	reg [RAM_DATA_WIDTH-1:0] max_so_far = 0;
	reg [DATA_WIDTH-1:0] j = 0;
	reg [DATA_WIDTH-1:0] index [LAST_RESULT:0];
	reg fifo_read_enable = 0;
	reg [DATA_WIDTH-1:0] previous_data_out_from_fifo = 0;
	wire [DATA_WIDTH-1:0] data_out_from_fifo;
	wire [RAM_ADDRESS_DEPTH-1:0] ram_read_address;
	wire [RAM_ADDRESS_DEPTH-1:0] ram_write_address;
	reg adding_ram_write_enable = 0;
	reg comparing_ram_write_enable = 0;
	wire ram_write_enable;
	wire fifo_full;
	wire should_keep_sampling = sample && (~partial_count_reached);
	wire [RAM_DATA_WIDTH-1:0] ram_data_in;
	wire [RAM_DATA_WIDTH-1:0] data_out_from_ram;
	reg [2:0] adding_state = 0;
	reg [2:0] comparing_state = 0;
	reg [RAM_DATA_WIDTH-1:0] count = 0;
	reg adding_not_comparing = 0;
	reg comparing_write_enable = 0;
	assign ram_read_address   = { {RAM_ADDRESS_DEPTH-DATA_WIDTH{1'b0}}, adding_not_comparing ? data_out_from_fifo : j };
	assign ram_write_address  = { {RAM_ADDRESS_DEPTH-DATA_WIDTH{1'b0}}, adding_not_comparing ? previous_data_out_from_fifo : j };
	assign ram_write_enable = adding_not_comparing ? adding_ram_write_enable : comparing_write_enable;

	assign ram_data_in      = adding_not_comparing ? count : {RAM_DATA_WIDTH{1'b0}} ;
	fifo_single_clock_using_single_bram #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_DEPTH(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST)) fsc (
		.clock(clock), .reset(reset), .error_count(error_count),
		.data_in(data_in), .write_enable(should_keep_sampling), .full(), .almost_full(), .full_or_almost_full(fifo_full),
		.data_out(data_out_from_fifo), .read_enable(fifo_read_enable), .empty(), .almost_empty(), .empty_or_almost_empty());
	if (USE_BLOCK_MEMORY) begin
		RAM_s6_primitive #(.DATA_WIDTH_A(RAM_DATA_WIDTH), .DATA_WIDTH_B(RAM_DATA_WIDTH)) mem (.reset(reset),
			.write_clock(clock), .write_address(ram_write_address), .data_in(ram_data_in), .write_enable(ram_write_enable),
			.read_clock(clock), .read_address(ram_read_address), .read_enable(1'b1), .data_out(data_out_from_ram));
	end else begin
		reg [RAM_ADDRESS_DEPTH-1:0] mem [(1<<RAM_ADDRESS_DEPTH)-1:0];
		always @(posedge clock) begin
			if (reset || clear_results) begin
			end else begin
				if (ram_write_enable) begin
					mem[ram_write_address] <= ram_data_in;
				end
			end
		end
		assign data_out_from_ram = mem[ram_read_address];
	end
	always @(posedge clock) begin
		if (reset || clear_results) begin
			fifo_read_enable <= 0;
			sample_counter <= 0;
			adding_ram_write_enable <= 0;
			adding_state <= 3'd0;
			count <= 0;
			max_count_reached <= 0;
			previous_data_out_from_fifo <= 0;
			adding_finished <= 0;
			partial_count_reached <= 0;
			capture_completion <= 0;
		end else begin
			if (~result_valid) begin
				if (~adding_finished) begin
					if (partial_count_reached) begin
						case (adding_state)
							3'd0    : begin
								if (adding_not_comparing) begin
									adding_state <= 3'd1;
								end
							end
							3'd1    : begin
								fifo_read_enable <= 1;
								adding_state <= 3'd2;
							end
							3'd2    : begin

								fifo_read_enable <= 0;
								count <= data_out_from_ram;
								previous_data_out_from_fifo <= data_out_from_fifo;
								adding_state <= 3'd3;
							end
							3'd3    : begin
								count <= count + 3'd1;
								adding_ram_write_enable <= 1;
								adding_state <= 3'd4;
							end
							3'd4    : begin
								adding_ram_write_enable <= 0;
								adding_state <= 3'd5;
							end
							default : begin
								if (sample_counter!=MAXIMUM_SAMPLE_NUMBER) begin
									sample_counter <= sample_counter + 1'd1;
								end else begin
									if (max_count_reached) begin
										adding_finished <= 1;
									end else begin
										partial_count_reached <= 0;
										sample_counter <= 0;
									end
									fifo_read_enable <= 0;
								end
								adding_state <= 3'd1;
							end
						endcase
					end
					if (fifo_full && ~partial_count_reached) begin
						partial_count_reached <= 1;
						if (capture_completion!=LAST_FIFO_FILL_NUMBER) begin
							capture_completion <= capture_completion + 1'd1;
						end else begin
							max_count_reached <= 1;
						end
					end
				end
			end
		end
	end
	always @(posedge clock) begin
		if (reset || clear_results) begin
			i <= 0;
			j <= 0;
			max_so_far <= 0;
			index[0] <= 0;
			index[1] <= 0;
			index[2] <= 0;
			index[3] <= 0;
			count_copy[0] <= 0;
			count_copy[1] <= 0;
			count_copy[2] <= 0;
			count_copy[3] <= 0;
			result_valid <= 0;
			comparing_state <= 0;
			comparing_write_enable <= 0;
			adding_not_comparing <= 0;
		end else begin
			if (~result_valid) begin
				if ((~adding_not_comparing) && adding_state==3'd0) begin
					comparing_write_enable <= 1;
					if (j!=MAX_INDEX) begin
						j <= j + 1'd1;
					end else begin
						j <= 0;
						comparing_write_enable <= 0;
						adding_not_comparing <= 1;
					end
				end
				if (max_count_reached && adding_finished) begin
					adding_not_comparing <= 0;
					case (comparing_state)
						3'd0    : begin
							comparing_write_enable <= 0;
							comparing_state <= 3'd1;
						end
						3'd1    : begin
							j <= 1'd1;
							comparing_state <= 3'd2;
						end
						3'd2    : begin
							max_so_far <= data_out_from_ram;
							comparing_state <= 3'd3;
						end
						3'd3    : begin
							comparing_state <= 3'd4;
						end
						3'd4    : begin
							if (max_so_far<data_out_from_ram) begin
								index[i] <= j;
								max_so_far <= data_out_from_ram;
							end
							if (j!=MAX_INDEX) begin
								j <= j + 1'd1;
								comparing_state <= 3'd3;
							end else begin
								j <= index[i];
								comparing_state <= 3'd5;
							end
						end
						3'd5    : begin
							count_copy[i] <= max_so_far[LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
							comparing_write_enable <= 1;
							comparing_state <= 3'd6;
						end
						default : begin
							comparing_write_enable <= 0;
							if (i!=LAST_RESULT) begin
								i <= i + 1'd1;
								j <= 0;
							end else begin
								result_valid <= 1;
							end
							comparing_state <= 3'd1;
						end
					endcase
				end
			end
		end
	end
	assign result00 = index[0];
	assign result01 = index[1];
	assign result02 = index[2];
	assign result03 = index[3];
	assign count00 = count_copy[0][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
	assign count01 = count_copy[1][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
	assign count02 = count_copy[2][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
	assign count03 = count_copy[3][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
endmodule
module histogram #(
	parameter DATA_WIDTH = 4,
	parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE = 4,
	parameter TESTBENCH = 0,
	parameter PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = TESTBENCH ? 2 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE + $clog2(DATA_WIDTH) - `LOG2_OF_BASE_BLOCK_MEMORY_SIZE,
	parameter LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO = PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO < 0 ? 0 : PRELIMINARY_LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO,
	parameter LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST = LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE - LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO,
	parameter USE_BLOCK_MEMORY = 1
) (
	input reset, clock,
	input sample,
	input clear_results,
	input [DATA_WIDTH-1:0] data_in,
	output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count00,
	output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count01,
	output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count02,
	output [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count03,
	output [DATA_WIDTH-1:0] result00,
	output [DATA_WIDTH-1:0] result01,
	output [DATA_WIDTH-1:0] result02,
	output [DATA_WIDTH-1:0] result03,
	output reg [LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO-1:0] capture_completion = 0,
	output reg partial_count_reached = 0,
	output reg max_count_reached = 0,
	output reg adding_finished = 0,
	output reg result_valid = 0,
	output [31:0] error_count
);

	localparam MAX_INDEX = (1<<DATA_WIDTH) - 1;
	localparam MAXIMUM_SAMPLE_NUMBER = (1<<LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST) - 1;
	localparam LOG2_OF_NUMBER_OF_RESULTS = 2;
	localparam LAST_RESULT = (1<<LOG2_OF_NUMBER_OF_RESULTS) - 1;

	localparam RAM_DATA_WIDTH = USE_BLOCK_MEMORY ? 32 : LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE;
	localparam RAM_ADDRESS_DEPTH = USE_BLOCK_MEMORY ? 9 : DATA_WIDTH;
	localparam LAST_FIFO_FILL_NUMBER = (1<<LOG2_OF_NUMBER_OF_TIMES_TO_FILL_FIFO) - 1;
	reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0] count_copy [LAST_RESULT:0];
	reg [LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST-1:0] sample_counter = 0;
	reg [LAST_RESULT:0] i = 0;
	reg [RAM_DATA_WIDTH-1:0] max_so_far = 0;
	reg [DATA_WIDTH-1:0] j = 0;
	reg [DATA_WIDTH-1:0] index [LAST_RESULT:0];
	reg fifo_read_enable = 0;
	reg [DATA_WIDTH-1:0] previous_data_out_from_fifo = 0;
	wire [DATA_WIDTH-1:0] data_out_from_fifo;
	wire [RAM_ADDRESS_DEPTH-1:0] ram_read_address;
	wire [RAM_ADDRESS_DEPTH-1:0] ram_write_address;
	reg adding_ram_write_enable = 0;
	reg comparing_ram_write_enable = 0;
	wire ram_write_enable;
	wire fifo_full;
	wire should_keep_sampling = sample && (~partial_count_reached);
	wire [RAM_DATA_WIDTH-1:0] ram_data_in;
	wire [RAM_DATA_WIDTH-1:0] data_out_from_ram;
	reg [2:0] adding_state = 0;
	reg [2:0] comparing_state = 0;
	reg [RAM_DATA_WIDTH-1:0] count = 0;
	reg adding_not_comparing = 0;
	reg comparing_write_enable = 0;
	assign ram_read_address   = { {RAM_ADDRESS_DEPTH-DATA_WIDTH{1'b0}}, adding_not_comparing ? data_out_from_fifo : j };
	assign ram_write_address  = { {RAM_ADDRESS_DEPTH-DATA_WIDTH{1'b0}}, adding_not_comparing ? previous_data_out_from_fifo : j };
	assign ram_write_enable = adding_not_comparing ? adding_ram_write_enable : comparing_write_enable;

	assign ram_data_in      = adding_not_comparing ? count : {RAM_DATA_WIDTH{1'b0}} ;
	fifo_single_clock_using_single_bram #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_DEPTH(LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE_IN_ONE_BURST)) fsc (
		.clock(clock), .reset(reset), .error_count(error_count),
		.data_in(data_in), .write_enable(should_keep_sampling), .full(), .almost_full(), .full_or_almost_full(fifo_full),
		.data_out(data_out_from_fifo), .read_enable(fifo_read_enable), .empty(), .almost_empty(), .empty_or_almost_empty());
	if (USE_BLOCK_MEMORY) begin
		RAM_s6_primitive #(.DATA_WIDTH_A(RAM_DATA_WIDTH), .DATA_WIDTH_B(RAM_DATA_WIDTH)) mem (.reset(reset),
			.write_clock(clock), .write_address(ram_write_address), .data_in(ram_data_in), .write_enable(ram_write_enable),
			.read_clock(clock), .read_address(ram_read_address), .read_enable(1'b1), .data_out(data_out_from_ram));
	end else begin
		reg [RAM_ADDRESS_DEPTH-1:0] mem [(1<<RAM_ADDRESS_DEPTH)-1:0];
		always @(posedge clock) begin
			if (reset || clear_results) begin
			end else begin
				if (ram_write_enable) begin
					mem[ram_write_address] <= ram_data_in;
				end
			end
		end
		assign data_out_from_ram = mem[ram_read_address];
	end
	always @(posedge clock) begin
		if (reset || clear_results) begin
			fifo_read_enable <= 0;
			sample_counter <= 0;
			adding_ram_write_enable <= 0;
			adding_state <= 3'd0;
			count <= 0;
			max_count_reached <= 0;
			previous_data_out_from_fifo <= 0;
			adding_finished <= 0;
			partial_count_reached <= 0;
			capture_completion <= 0;
		end else begin
			if (~result_valid) begin
				if (~adding_finished) begin
					if (partial_count_reached) begin
						case (adding_state)
							3'd0    : begin
								if (adding_not_comparing) begin
									adding_state <= 3'd1;
								end
							end
							3'd1    : begin
								fifo_read_enable <= 1;
								adding_state <= 3'd2;
							end
							3'd2    : begin

								fifo_read_enable <= 0;
								count <= data_out_from_ram;
								previous_data_out_from_fifo <= data_out_from_fifo;
								adding_state <= 3'd3;
							end
							3'd3    : begin
								count <= count + 3'd1;
								adding_ram_write_enable <= 1;
								adding_state <= 3'd4;
							end
							3'd4    : begin
								adding_ram_write_enable <= 0;
								adding_state <= 3'd5;
							end
							default : begin
								if (sample_counter!=MAXIMUM_SAMPLE_NUMBER) begin
									sample_counter <= sample_counter + 1'd1;
								end else begin
									if (max_count_reached) begin
										adding_finished <= 1;
									end else begin
										partial_count_reached <= 0;
										sample_counter <= 0;
									end
									fifo_read_enable <= 0;
								end
								adding_state <= 3'd1;
							end
						endcase
					end
					if (fifo_full && ~partial_count_reached) begin
						partial_count_reached <= 1;
						if (capture_completion!=LAST_FIFO_FILL_NUMBER) begin
							capture_completion <= capture_completion + 1'd1;
						end else begin
							max_count_reached <= 1;
						end
					end
				end
			end
		end
	end
	always @(posedge clock) begin
		if (reset || clear_results) begin
			i <= 0;
			j <= 0;
			max_so_far <= 0;
			index[0] <= 0;
			index[1] <= 0;
			index[2] <= 0;
			index[3] <= 0;
			count_copy[0] <= 0;
			count_copy[1] <= 0;
			count_copy[2] <= 0;
			count_copy[3] <= 0;
			result_valid <= 0;
			comparing_state <= 0;
			comparing_write_enable <= 0;
			adding_not_comparing <= 0;
		end else begin
			if (~result_valid) begin
				if ((~adding_not_comparing) && adding_state==3'd0) begin
					comparing_write_enable <= 1;
					if (j!=MAX_INDEX) begin
						j <= j + 1'd1;
					end else begin
						j <= 0;
						comparing_write_enable <= 0;
						adding_not_comparing <= 1;
					end
				end
				if (max_count_reached && adding_finished) begin
					adding_not_comparing <= 0;
					case (comparing_state)
						3'd0    : begin
							comparing_write_enable <= 0;
							comparing_state <= 3'd1;
						end
						3'd1    : begin
							j <= 1'd1;
							comparing_state <= 3'd2;
						end
						3'd2    : begin
							max_so_far <= data_out_from_ram;
							comparing_state <= 3'd3;
						end
						3'd3    : begin
							comparing_state <= 3'd4;
						end
						3'd4    : begin
							if (max_so_far<data_out_from_ram) begin
								index[i] <= j;
								max_so_far <= data_out_from_ram;
							end
							if (j!=MAX_INDEX) begin
								j <= j + 1'd1;
								comparing_state <= 3'd3;
							end else begin
								j <= index[i];
								comparing_state <= 3'd5;
							end
						end
						3'd5    : begin
							count_copy[i] <= max_so_far[LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
							comparing_write_enable <= 1;
							comparing_state <= 3'd6;
						end
						default : begin
							comparing_write_enable <= 0;
							if (i!=LAST_RESULT) begin
								i <= i + 1'd1;
								j <= 0;
							end else begin
								result_valid <= 1;
							end
							comparing_state <= 3'd1;
						end
					endcase
				end
			end
		end
	end
	assign result00 = index[0];
	assign result01 = index[1];
	assign result02 = index[2];
	assign result03 = index[3];
	assign count00 = count_copy[0][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
	assign count01 = count_copy[1][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
	assign count02 = count_copy[2][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
	assign count03 = count_copy[3][LOG2_OF_NUMBER_OF_SAMPLES_TO_ACQUIRE-1:0];
endmodule