data/full_repos/permissive/169496369/alu_small.v
data/verilator_xmls/be9c2b8f-2b2c-4214-832d-a49571db54fb.xml
module alu_small(e1, e2, d, diff);
    input [7:0]e1, e2;
    output logic d;
    output logic [7:0]diff;
    
    always_comb
        begin
        d = 0;
        diff = 8'd0;
        if(e1 >= e2)
        begin
            d = 0;
            diff = e1 - e2;
        end
        else if (e1 < e2)
        begin
            d = 1;
            diff = e2 - e1;
        end
    end
endmodule
module alu_small(e1, e2, d, diff);

    input [7:0]e1, e2;
    output logic d;
    output logic [7:0]diff;
    
    always_comb
        begin
        d = 0;
        diff = 8'd0;
        if(e1 >= e2)
        begin
            d = 0;
            diff = e1 - e2;
        end
        else if (e1 < e2)
        begin
            d = 1;
            diff = e2 - e1;
        end
    end
endmodule