data/full_repos/permissive/154371523/Code/rtl/xtop.v
1: b'%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:3: Cannot find include file: xdefs.vh\n`include "xdefs.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh.v\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh.sv\n             xdefs.vh\n             xdefs.vh.v\n             xdefs.vh.sv\n             obj_dir/xdefs.vh\n             obj_dir/xdefs.vh.v\n             obj_dir/xdefs.vh.sv\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:4: Cannot find include file: xctrldefs.vh\n`include "xctrldefs.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:5: Cannot find include file: xprogdefs.vh\n`include "xprogdefs.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:6: Cannot find include file: xregfdefs.vh\n`include "xregfdefs.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:36: Define or directive not defined: \'`INSTR_W\'\n   wire [`INSTR_W-1:0]     instruction;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:37: Define or directive not defined: \'`PROG_ADDR_W\'\n   wire [`PROG_ADDR_W-1:0]    pc;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:42: Define or directive not defined: \'`ADDR_W\'\n   wire [`ADDR_W-1:0]     data_addr;\n         ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:43: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W-1:0]     data_to_rd;\n        ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:44: Define or directive not defined: \'`DATA_W\'\n   wire [`DATA_W-1:0]     data_to_wr;\n         ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:48: Define or directive not defined: \'`DATA_W\'\n   wire [`DATA_W-1:0]     prog_data_to_rd;\n         ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:51: Define or directive not defined: \'`DATA_W\'\n   wire [`DATA_W-1:0]     regf_data_to_rd;\n         ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:98: Define or directive not defined: \'`PROG_RAM_ADDR_W\'\n        .data_addr(data_addr[`PROG_RAM_ADDR_W-1:0]),\n                             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:131: Define or directive not defined: \'`DATA_W\'\n        data_to_rd = `DATA_W\'d0;\n                     ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:133: Define or directive not defined: \'`REGF_BASE\'\n        if (`REGF_BASE == (data_addr & ({`ADDR_W{1\'b1}}<<`REGF_ADDR_W))) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:133: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\n        if (`REGF_BASE == (data_addr & ({`ADDR_W{1\'b1}}<<`REGF_ADDR_W))) begin\n                       ^~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:133: Define or directive not defined: \'`ADDR_W\'\n        if (`REGF_BASE == (data_addr & ({`ADDR_W{1\'b1}}<<`REGF_ADDR_W))) begin\n                                         ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:133: Define or directive not defined: \'`REGF_ADDR_W\'\n        if (`REGF_BASE == (data_addr & ({`ADDR_W{1\'b1}}<<`REGF_ADDR_W))) begin\n                                                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:143: syntax error, unexpected else\n        else if (`PROG_BASE == (data_addr & ({`ADDR_W{1\'b1}}<<`PROG_ADDR_W))) begin\n        ^~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:143: Define or directive not defined: \'`PROG_BASE\'\n        else if (`PROG_BASE == (data_addr & ({`ADDR_W{1\'b1}}<<`PROG_ADDR_W))) begin\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:143: Define or directive not defined: \'`ADDR_W\'\n        else if (`PROG_BASE == (data_addr & ({`ADDR_W{1\'b1}}<<`PROG_ADDR_W))) begin\n                                              ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:143: Define or directive not defined: \'`PROG_ADDR_W\'\n        else if (`PROG_BASE == (data_addr & ({`ADDR_W{1\'b1}}<<`PROG_ADDR_W))) begin\n                                                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:148: Define or directive not defined: \'`PS2_BASE\'\n     else if(`PS2_BASE == data_addr) begin\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:153: Define or directive not defined: \'`DISP_BASE\'\n   else if(`DISP_BASE == data_addr)\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:157: Define or directive not defined: \'`OPER_BASE\'\n else if (`OPER_BASE == data_addr) \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:159: Define or directive not defined: \'`OP_BASE\'\n else if (`OP_BASE == data_addr) begin\n          ^~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop.v:190: Define or directive not defined: \'`REGF_ADDR_W\'\n        .int_addr(data_addr[`REGF_ADDR_W-1:0]),\n                            ^~~~~~~~~~~~\n%Error: Exiting due to 26 error(s)\n'
module xtop (
	    

	     input 		      clk,
	     input 		      rst,
		  

		  input				ps2_data,
		  input				ps2_clk,
		  

		  

		  output	[11:0]	disp_ctrl,
          

          output [7:0]	      overflow_led
		  
	     );






   

   wire [`INSTR_W-1:0] 		  instruction;
   wire [`PROG_ADDR_W-1:0] 	  pc;


   wire 			  data_sel;
   wire 			  data_we;
   wire [`ADDR_W-1:0] 		  data_addr;
   reg [`DATA_W-1:0] 		  data_to_rd;
   wire [`DATA_W-1:0] 		  data_to_wr;


   reg 				  prog_sel;
   wire [`DATA_W-1:0] 		  prog_data_to_rd;
   
   reg 				  regf_sel;
   wire [`DATA_W-1:0] 		  regf_data_to_rd;

`ifdef DEBUG
   reg 				  cprt_sel;
`endif

	reg					ps2_sel;

	wire [8:0]			ps2_data_to_rd;
  	reg					disp_sel;
   
	reg 					oper_sel;
	wire [10:0]			oper_data_to_rd;







   



   xctrl controller (
		     .clk(clk), 
		     .rst(rst),
		     

		     .pc(pc),
		     .instruction(instruction),
		     

		     .data_sel(data_sel),
		     .data_we (data_we), 
		     .data_addr(data_addr),
		     .data_to_rd(data_to_rd), 
		     .data_to_wr(data_to_wr)
		     );


   xprog prog (
	       .clk(clk),


	       .data_sel(prog_sel),
	       .data_we(data_we),
	       .data_addr(data_addr[`PROG_RAM_ADDR_W-1:0]),
	       .data_in(data_to_wr),
	       .data_out(prog_data_to_rd),


`ifdef DMA_USE
	       .dma_req(dma_prog_req),	       
	       .dma_rnw(dma_rnw),
	       .dma_addr(dma_addr[`PROG_ADDR_W-1:0]),
	       .dma_data_in(dma_data_from),
	       .dma_data_out(dma_data_from_prog),
`endif	       


	       .pc(pc),
       	       .instruction(instruction)      
	       );



   always @ * begin
      prog_sel = 1'b0;
      regf_sel = 1'b0;
		ps2_sel = 1'b0;
     
		disp_sel =1'b0;
 
		oper_sel =1'b0;
	
		
`ifdef DEBUG
        cprt_sel = 1'b0;
`endif
        data_to_rd = `DATA_W'd0;
      
        if (`REGF_BASE == (data_addr & ({`ADDR_W{1'b1}}<<`REGF_ADDR_W))) begin
				regf_sel = data_sel;
            data_to_rd = regf_data_to_rd;
        end

`ifdef DEBUG
        else if (`CPRT_BASE == data_addr)
	        cprt_sel = data_sel;
 `endif

        else if (`PROG_BASE == (data_addr & ({`ADDR_W{1'b1}}<<`PROG_ADDR_W))) begin
            prog_sel = 1'b1;
            data_to_rd = prog_data_to_rd;	    
        end

	    else if(`PS2_BASE == data_addr) begin
	        ps2_sel =1'b1;
			  data_to_rd = ps2_data_to_rd;
			
		 end
	  else if(`DISP_BASE == data_addr)
	      disp_sel =1'b1;
			  
       
	else if (`OPER_BASE == data_addr) 
		oper_sel =1'b1;
	else if (`OP_BASE == data_addr) begin
		data_to_rd=oper_data_to_rd;
	
	end

			
`ifdef DEBUG	
        else if(data_sel === 1'b1)
            $display("Warning: unmapped controller issued data address %x at time %f", data_addr, $time);
`endif
    end






   

   xregf regf (
	       .clk(clk),
	       

	       .ext_we(1'b0),
	       .ext_addr(4'b0),
	       .ext_data_in(32'b1),
	       .ext_data_out(),
			

	       .int_sel(regf_sel),
	       .int_we(data_we),
	       .int_addr(data_addr[`REGF_ADDR_W-1:0]),
	       .int_data_in(data_to_wr),
	       .int_data_out(regf_data_to_rd)
	       );

`ifdef DEBUG
   xcprint cprint (
		   .clk(clk),
		   .sel(cprt_sel),
		   .data_in(data_to_wr[7:0])
		   );
`endif

   xps2 ps2 (
			.clk(clk),
			.sel(ps2_sel),
			.rst(rst),
			.ps2_clk(ps2_clk),
			.ps2_data(ps2_data),
			.data_out(ps2_data_to_rd)
			);
			
			
	xdisp disp (
			.clk(clk),
			.sel(disp_sel),
			.rst(rst),
			.data_in(data_to_wr[10:0]),
			.data_out(disp_ctrl)
			);

 

xoper oper (
	    .clk(clk),
       .sel(oper_sel),
	    .rst(rst),
	    .data_in(data_to_wr[10:0]),
	    .data_out(oper_data_to_rd),
		 .led(overflow_led)
	    );
	
			
endmodule
module xtop (
	    

	     input 		      clk,
	     input 		      rst,
		  

		  input				ps2_data,
		  input				ps2_clk,
		  

		  

		  output	[11:0]	disp_ctrl,
          

          output [7:0]	      overflow_led
		  
	     );







   

   wire [`INSTR_W-1:0] 		  instruction;
   wire [`PROG_ADDR_W-1:0] 	  pc;


   wire 			  data_sel;
   wire 			  data_we;
   wire [`ADDR_W-1:0] 		  data_addr;
   reg [`DATA_W-1:0] 		  data_to_rd;
   wire [`DATA_W-1:0] 		  data_to_wr;


   reg 				  prog_sel;
   wire [`DATA_W-1:0] 		  prog_data_to_rd;
   
   reg 				  regf_sel;
   wire [`DATA_W-1:0] 		  regf_data_to_rd;

`ifdef DEBUG
   reg 				  cprt_sel;
`endif

	reg					ps2_sel;

	wire [8:0]			ps2_data_to_rd;
  	reg					disp_sel;
   
	reg 					oper_sel;
	wire [10:0]			oper_data_to_rd;







   



   xctrl controller (
		     .clk(clk), 
		     .rst(rst),
		     

		     .pc(pc),
		     .instruction(instruction),
		     

		     .data_sel(data_sel),
		     .data_we (data_we), 
		     .data_addr(data_addr),
		     .data_to_rd(data_to_rd), 
		     .data_to_wr(data_to_wr)
		     );


   xprog prog (
	       .clk(clk),


	       .data_sel(prog_sel),
	       .data_we(data_we),
	       .data_addr(data_addr[`PROG_RAM_ADDR_W-1:0]),
	       .data_in(data_to_wr),
	       .data_out(prog_data_to_rd),


`ifdef DMA_USE
	       .dma_req(dma_prog_req),	       
	       .dma_rnw(dma_rnw),
	       .dma_addr(dma_addr[`PROG_ADDR_W-1:0]),
	       .dma_data_in(dma_data_from),
	       .dma_data_out(dma_data_from_prog),
`endif	       


	       .pc(pc),
       	       .instruction(instruction)      
	       );



   always @ * begin
      prog_sel = 1'b0;
      regf_sel = 1'b0;
		ps2_sel = 1'b0;
     
		disp_sel =1'b0;
 
		oper_sel =1'b0;
	
		
`ifdef DEBUG
        cprt_sel = 1'b0;
`endif
        data_to_rd = `DATA_W'd0;
      
        if (`REGF_BASE == (data_addr & ({`ADDR_W{1'b1}}<<`REGF_ADDR_W))) begin
				regf_sel = data_sel;
            data_to_rd = regf_data_to_rd;
        end

`ifdef DEBUG
        else if (`CPRT_BASE == data_addr)
	        cprt_sel = data_sel;
 `endif

        else if (`PROG_BASE == (data_addr & ({`ADDR_W{1'b1}}<<`PROG_ADDR_W))) begin
            prog_sel = 1'b1;
            data_to_rd = prog_data_to_rd;	    
        end

	    else if(`PS2_BASE == data_addr) begin
	        ps2_sel =1'b1;
			  data_to_rd = ps2_data_to_rd;
			
		 end
	  else if(`DISP_BASE == data_addr)
	      disp_sel =1'b1;
			  
       
	else if (`OPER_BASE == data_addr) 
		oper_sel =1'b1;
	else if (`OP_BASE == data_addr) begin
		data_to_rd=oper_data_to_rd;
	
	end

			
`ifdef DEBUG	
        else if(data_sel === 1'b1)
            $display("Warning: unmapped controller issued data address %x at time %f", data_addr, $time);
`endif
    end






   

   xregf regf (
	       .clk(clk),
	       

	       .ext_we(1'b0),
	       .ext_addr(4'b0),
	       .ext_data_in(32'b1),
	       .ext_data_out(),
			

	       .int_sel(regf_sel),
	       .int_we(data_we),
	       .int_addr(data_addr[`REGF_ADDR_W-1:0]),
	       .int_data_in(data_to_wr),
	       .int_data_out(regf_data_to_rd)
	       );

`ifdef DEBUG
   xcprint cprint (
		   .clk(clk),
		   .sel(cprt_sel),
		   .data_in(data_to_wr[7:0])
		   );
`endif

   xps2 ps2 (
			.clk(clk),
			.sel(ps2_sel),
			.rst(rst),
			.ps2_clk(ps2_clk),
			.ps2_data(ps2_data),
			.data_out(ps2_data_to_rd)
			);
			
			
	xdisp disp (
			.clk(clk),
			.sel(disp_sel),
			.rst(rst),
			.data_in(data_to_wr[10:0]),
			.data_out(disp_ctrl)
			);

 

xoper oper (
	    .clk(clk),
       .sel(oper_sel),
	    .rst(rst),
	    .data_in(data_to_wr[10:0]),
	    .data_out(oper_data_to_rd),
		 .led(overflow_led)
	    );
	
			
endmodule