data/full_repos/permissive/204736068/SoM/RTL/vision/synth/source/impl_1/dpram512x8/rtl/dpram512x8_bb.v
data/verilator_xmls/e39f2b3c-e6c7-4fec-bcda-ff62010752ed.xml
module dpram512x8 (wr_clk_i, rd_clk_i, rst_i, wr_clk_en_i, rd_en_i,
    rd_clk_en_i, wr_en_i, wr_data_i, wr_addr_i, rd_addr_i, rd_data_o);
    input  wr_clk_i;
    input  rd_clk_i;
    input  rst_i;
    input  wr_clk_en_i;
    input  rd_en_i;
    input  rd_clk_en_i;
    input  wr_en_i;
    input  [35:0]  wr_data_i;
    input  [8:0]  wr_addr_i;
    input  [8:0]  rd_addr_i;
    output  [35:0]  rd_data_o;
endmodule
module dpram512x8 (wr_clk_i, rd_clk_i, rst_i, wr_clk_en_i, rd_en_i,
    rd_clk_en_i, wr_en_i, wr_data_i, wr_addr_i, rd_addr_i, rd_data_o);

    input  wr_clk_i;
    input  rd_clk_i;
    input  rst_i;
    input  wr_clk_en_i;
    input  rd_en_i;
    input  rd_clk_en_i;
    input  wr_en_i;
    input  [35:0]  wr_data_i;
    input  [8:0]  wr_addr_i;
    input  [8:0]  rd_addr_i;
    output  [35:0]  rd_data_o;
endmodule