data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_dfilt1_tb.sv
 line:29: before: "realtime"
1: b'%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_dfilt1_tb.sv:29: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  realtime  TP = 8.0ns   \n                 ^~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_dfilt1_tb.sv:40: syntax error, unexpected initial\ninitial        clk = 1\'b0;\n^~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_dfilt1_tb.sv:69: syntax error, unexpected initial\ninitial begin\n^~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_dfilt1_tb.sv:127: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("red_pitaya_dfilt1_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/red_pitaya_dfilt1_tb.sv:128: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, red_pitaya_dfilt1_tb);\n  ^~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module red_pitaya_dfilt1_tb #(

  realtime  TP = 8.0ns
);





logic              clk ;
logic              rstn;


initial        clk = 1'b0;
always #(TP/2) clk = ~clk;


initial begin
  rstn = 1'b0;
  repeat(4) @(posedge clk);
  rstn = 1'b1;
end

logic [ 14-1: 0] adc_read    ;
logic [ 14-1: 0] adc_in      ;
logic [ 14-1: 0] adc_out     ;
logic            adc_clk     ;
logic            adc_rstn    ;

logic [ 18-1: 0] cfg_aa      ;
logic [ 25-1: 0] cfg_bb      ;
logic [ 25-1: 0] cfg_kk      ;
logic [ 25-1: 0] cfg_pp      ;






integer fp1,fp2;
integer dummy;

initial begin

   fp1 = $fopen("../../../../code/bench/dfilt1_sim_values.txt", "r");
   fp2 = $fopen("../../../../code/bench/dfilt1_sim_output.txt", "w");
   adc_read <= 14'h0 ;
   adc_in   <= 14'h0 ;

   cfg_aa <= 18'd40724 ;
   cfg_bb <= 25'd341536 ;
   cfg_kk <= 25'd14260634 ;
   cfg_pp <= 25'd9830 ;

   wait (adc_rstn)
   repeat(2) @(posedge adc_clk);


   while ( !$feof(fp1) ) begin
      @(posedge adc_clk);
      dummy = $fscanf(fp1,"%d \n", adc_read);
   end

   repeat(2) @(posedge adc_clk);
   $fclose(fp1);
end


always @(posedge adc_clk) begin
   adc_in <= adc_read ;

   if(adc_rstn == 1'b1) begin
      $fwrite(fp2, "%d %d %d %d %d %d %d \n", $signed(i_filt1.r01_reg), $signed(i_filt1.r02_reg), 
                                              $signed(i_filt1.r1_reg), $signed(i_filt1.r2_reg), 
                                              $signed(i_filt1.r3_reg), $signed(i_filt1.r4_reg), $signed(i_filt1.r5_reg) ) ;
   end
end





red_pitaya_dfilt1 i_filt1 (

  .adc_clk_i   ( adc_clk    ),
  .adc_rstn_i  ( adc_rstn   ),
  .adc_dat_i   ( adc_in     ),
  .adc_dat_o   ( adc_out    ),

  .cfg_aa_i    ( cfg_aa     ),
  .cfg_bb_i    ( cfg_bb     ),
  .cfg_kk_i    ( cfg_kk     ),
  .cfg_pp_i    ( cfg_pp     ) 
);





initial begin
  $dumpfile("red_pitaya_dfilt1_tb.vcd");
  $dumpvars(0, red_pitaya_dfilt1_tb);
end

endmodule
module red_pitaya_dfilt1_tb #(

  realtime  TP = 8.0ns
);






logic              clk ;
logic              rstn;


initial        clk = 1'b0;
always #(TP/2) clk = ~clk;


initial begin
  rstn = 1'b0;
  repeat(4) @(posedge clk);
  rstn = 1'b1;
end

logic [ 14-1: 0] adc_read    ;
logic [ 14-1: 0] adc_in      ;
logic [ 14-1: 0] adc_out     ;
logic            adc_clk     ;
logic            adc_rstn    ;

logic [ 18-1: 0] cfg_aa      ;
logic [ 25-1: 0] cfg_bb      ;
logic [ 25-1: 0] cfg_kk      ;
logic [ 25-1: 0] cfg_pp      ;






integer fp1,fp2;
integer dummy;

initial begin

   fp1 = $fopen("../../../../code/bench/dfilt1_sim_values.txt", "r");
   fp2 = $fopen("../../../../code/bench/dfilt1_sim_output.txt", "w");
   adc_read <= 14'h0 ;
   adc_in   <= 14'h0 ;

   cfg_aa <= 18'd40724 ;
   cfg_bb <= 25'd341536 ;
   cfg_kk <= 25'd14260634 ;
   cfg_pp <= 25'd9830 ;

   wait (adc_rstn)
   repeat(2) @(posedge adc_clk);


   while ( !$feof(fp1) ) begin
      @(posedge adc_clk);
      dummy = $fscanf(fp1,"%d \n", adc_read);
   end

   repeat(2) @(posedge adc_clk);
   $fclose(fp1);
end


always @(posedge adc_clk) begin
   adc_in <= adc_read ;

   if(adc_rstn == 1'b1) begin
      $fwrite(fp2, "%d %d %d %d %d %d %d \n", $signed(i_filt1.r01_reg), $signed(i_filt1.r02_reg), 
                                              $signed(i_filt1.r1_reg), $signed(i_filt1.r2_reg), 
                                              $signed(i_filt1.r3_reg), $signed(i_filt1.r4_reg), $signed(i_filt1.r5_reg) ) ;
   end
end





red_pitaya_dfilt1 i_filt1 (

  .adc_clk_i   ( adc_clk    ),
  .adc_rstn_i  ( adc_rstn   ),
  .adc_dat_i   ( adc_in     ),
  .adc_dat_o   ( adc_out    ),

  .cfg_aa_i    ( cfg_aa     ),
  .cfg_bb_i    ( cfg_bb     ),
  .cfg_kk_i    ( cfg_kk     ),
  .cfg_pp_i    ( cfg_pp     ) 
);





initial begin
  $dumpfile("red_pitaya_dfilt1_tb.vcd");
  $dumpvars(0, red_pitaya_dfilt1_tb);
end

endmodule