data/full_repos/permissive/117436613/mmix/fetch_unit.sv
 line:45: before: "parameter"
1: b'%Error: data/full_repos/permissive/117436613/mmix/fetch_unit.sv:23: Cannot find include file: mmix_defs.sv\n`include "mmix_defs.sv" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117436613/mmix,data/full_repos/permissive/117436613/mmix_defs.sv\n             data/full_repos/permissive/117436613/mmix,data/full_repos/permissive/117436613/mmix_defs.sv.v\n             data/full_repos/permissive/117436613/mmix,data/full_repos/permissive/117436613/mmix_defs.sv.sv\n             mmix_defs.sv\n             mmix_defs.sv.v\n             mmix_defs.sv.sv\n             obj_dir/mmix_defs.sv\n             obj_dir/mmix_defs.sv.v\n             obj_dir/mmix_defs.sv.sv\n%Error: Exiting due to 1 error(s)\n'
module fetch_unit(
	input  logic			clk,
	input  logic			reset_n,
	input  logic			enable,
	input  logic[63:0]	inst_ptr,
	output logic			fetch_done,
	output fetch			head,
	
	output logic [63:0]	mem_address,
	output logic [1:0]	mem_datasize,
	output logic			mem_read,
	input  logic [63:0]	mem_readdata,
	input  logic			mem_done
);

	logic[31:0]	inst;
	logic px_bit, f_bit;
	
	assign head.loc = inst_ptr;
	assign head.inst = head.interrupt[F_BIT] ? {SWYM, 24'b0} : inst;
	assign head.resuming = 0;
	
	always_comb begin
		head.interrupt = 0;
		head.interrupt[PX_BIT] = px_bit;
		head.interrupt[F_BIT] = f_bit;
	end
	
	logic [3:0]		state;
	
	assign mem_datasize = 2'b10;
	assign mem_address = { 1'b0, inst_ptr[62:0] };
	
	always_ff @(posedge clk, negedge reset_n) begin
		if (reset_n == 0) begin
			inst <= 0;
		end else begin
			if ((state == 1) && mem_done)
				inst <= mem_readdata[31:0];
		end
	end

	always_ff @(posedge clk, negedge reset_n) begin
		if (reset_n == 0) begin
			mem_read <= 0;
			fetch_done <= 0;
			px_bit <= 0;
			f_bit <= 0;
			state <= 0;
		end else begin
			case (state)
			0: begin
					if (enable) begin
						if (inst_ptr[63]) begin
							if (inst_ptr[62:48]) begin
								px_bit <= 1;
								fetch_done <= 1;
								state <= 15;
							end else begin
								mem_read <= 1;
								state <= 1;
							end
						end else begin

							f_bit <= 1;
							fetch_done <= 1;
							state <= 15;
						end
					end
				end
			1: begin
					if (mem_done) begin
						mem_read <= 0;
						fetch_done <= 1;
						state <= 15;
					end
				end
			15: begin
					fetch_done <= 0;
					px_bit <= 0;
					f_bit <= 0;
					state <= 0;
				end
			endcase
		end
	end

endmodule
module fetch_unit(
	input  logic			clk,
	input  logic			reset_n,
	input  logic			enable,
	input  logic[63:0]	inst_ptr,
	output logic			fetch_done,
	output fetch			head,
	
	output logic [63:0]	mem_address,
	output logic [1:0]	mem_datasize,
	output logic			mem_read,
	input  logic [63:0]	mem_readdata,
	input  logic			mem_done
);


	logic[31:0]	inst;
	logic px_bit, f_bit;
	
	assign head.loc = inst_ptr;
	assign head.inst = head.interrupt[F_BIT] ? {SWYM, 24'b0} : inst;
	assign head.resuming = 0;
	
	always_comb begin
		head.interrupt = 0;
		head.interrupt[PX_BIT] = px_bit;
		head.interrupt[F_BIT] = f_bit;
	end
	
	logic [3:0]		state;
	
	assign mem_datasize = 2'b10;
	assign mem_address = { 1'b0, inst_ptr[62:0] };
	
	always_ff @(posedge clk, negedge reset_n) begin
		if (reset_n == 0) begin
			inst <= 0;
		end else begin
			if ((state == 1) && mem_done)
				inst <= mem_readdata[31:0];
		end
	end

	always_ff @(posedge clk, negedge reset_n) begin
		if (reset_n == 0) begin
			mem_read <= 0;
			fetch_done <= 0;
			px_bit <= 0;
			f_bit <= 0;
			state <= 0;
		end else begin
			case (state)
			0: begin
					if (enable) begin
						if (inst_ptr[63]) begin
							if (inst_ptr[62:48]) begin
								px_bit <= 1;
								fetch_done <= 1;
								state <= 15;
							end else begin
								mem_read <= 1;
								state <= 1;
							end
						end else begin

							f_bit <= 1;
							fetch_done <= 1;
							state <= 15;
						end
					end
				end
			1: begin
					if (mem_done) begin
						mem_read <= 0;
						fetch_done <= 1;
						state <= 15;
					end
				end
			15: begin
					fetch_done <= 0;
					px_bit <= 0;
					f_bit <= 0;
					state <= 0;
				end
			endcase
		end
	end

endmodule