data/full_repos/permissive/143278/ivltests/pr1755593.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1755593.v:14: Unsupported: Ignoring delay on this delayed statement.\n     #1 if (out !== data[sel]) begin\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test (Z, D0, D1, D2, D3, E0, E1);

   output Z;
   input D0;
   input D1;
   input D2;
   input D3;
   input E0;
   input E1;

   u_test I48 (Z, D0, D1, D2, D3, E0, E1);

endmodule
module test (Z, D0, D1, D2, D3, E0, E1);


   output Z;
   input D0;
   input D1;
   input D2;
   input D3;
   input E0;
   input E1;

   u_test I48 (Z, D0, D1, D2, D3, E0, E1);

endmodule