data/full_repos/permissive/126689099/chirp.v
 line:24: before: "reg"
1: b'%Warning-WIDTH: data/full_repos/permissive/126689099/chirp.v:34: Operator ASSIGNW expects 14 bits on the Assign RHS, but Assign RHS\'s VARREF \'douta\' generates 16 bits.\n                                                               : ... In instance chirp\nassign chirp_out = douta;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/126689099/chirp.v:39: Cannot find file containing module: \'ip_chirp_data_rom\'\nip_chirp_data_rom uut (\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/126689099,data/full_repos/permissive/126689099/ip_chirp_data_rom\n             data/full_repos/permissive/126689099,data/full_repos/permissive/126689099/ip_chirp_data_rom.v\n             data/full_repos/permissive/126689099,data/full_repos/permissive/126689099/ip_chirp_data_rom.sv\n             ip_chirp_data_rom\n             ip_chirp_data_rom.v\n             ip_chirp_data_rom.sv\n             obj_dir/ip_chirp_data_rom\n             obj_dir/ip_chirp_data_rom.v\n             obj_dir/ip_chirp_data_rom.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module chirp(
	input clk,
	input rst_n,
	output[13:0] chirp_out
    );

reg[13:0] reg_chirp_out;

assign chirp_out = douta;

reg [8:0] addra;
wire [15:0] douta;

ip_chirp_data_rom uut (
	.clka(clk), 
	.addra(addra), 
	.douta(douta)
);

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		index <= 0;
		reg_chirp_out <= 14'b00_0000_0000_0000;
		addra <= 0;
	end
	else
	begin
		addra <= addra + 1'b1;
		if(addra == 450)
			addra <= 0;
	end
end

endmodule
module chirp(
	input clk,
	input rst_n,
	output[13:0] chirp_out
    );


reg[13:0] reg_chirp_out;

assign chirp_out = douta;

reg [8:0] addra;
wire [15:0] douta;

ip_chirp_data_rom uut (
	.clka(clk), 
	.addra(addra), 
	.douta(douta)
);

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		index <= 0;
		reg_chirp_out <= 14'b00_0000_0000_0000;
		addra <= 0;
	end
	else
	begin
		addra <= addra + 1'b1;
		if(addra == 450)
			addra <= 0;
	end
end

endmodule