data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v
 line:100: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n             ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n            ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n                ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n                                                                                              : ... In instance multicpu.alu\n   zero = ALUResult ? 0 : 1;\n                    ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DataMemory(
   input [31:0] DAddr,DataIn,
	input RD,WR,
	output reg [31:0] DataOut
    );
	 
	reg [7:0] memory[0:127];
	integer i;
	
	initial
		begin
			DataOut=0;
			for(i=0;i<128;i=i+1) memory[i] <= 0;
		end
		
	always@(RD or WR or DAddr or DataIn)
		begin
			if(RD)
				begin
					DataOut[31:24]=memory[DAddr];
					DataOut[23:16]=memory[DAddr + 1];
					DataOut[15:8]=memory[DAddr + 2];
					DataOut[7:0]=memory[DAddr + 3];
				end
			else 
					if(WR)
						begin
							memory[DAddr]=DataIn[31:24];
							memory[DAddr + 1]=DataIn[23:16];
							memory[DAddr + 2]=DataIn[15:8];
							memory[DAddr + 3]=DataIn[7:0];
						end
		end

endmodule
module DataMemory(
   input [31:0] DAddr,DataIn,
	input RD,WR,
	output reg [31:0] DataOut
    );

	 
	reg [7:0] memory[0:127];
	integer i;
	
	initial
		begin
			DataOut=0;
			for(i=0;i<128;i=i+1) memory[i] <= 0;
		end
		
	always@(RD or WR or DAddr or DataIn)
		begin
			if(RD)
				begin
					DataOut[31:24]=memory[DAddr];
					DataOut[23:16]=memory[DAddr + 1];
					DataOut[15:8]=memory[DAddr + 2];
					DataOut[7:0]=memory[DAddr + 3];
				end
			else 
					if(WR)
						begin
							memory[DAddr]=DataIn[31:24];
							memory[DAddr + 1]=DataIn[23:16];
							memory[DAddr + 2]=DataIn[15:8];
							memory[DAddr + 3]=DataIn[7:0];
						end
		end

endmodule