data/full_repos/permissive/199399537/sdram_ctrl.v
'utf-8' codec can't decode byte 0xcc in position 2093: invalid continuation byte
1: b'%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:53: Cannot find include file: sdr_para.v\n`include "sdr_para.v"  //             SDRAM                                 \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/sdr_para.v\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/sdr_para.v.v\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/sdr_para.v.sv\n             sdr_para.v\n             sdr_para.v.v\n             sdr_para.v.sv\n             obj_dir/sdr_para.v\n             obj_dir/sdr_para.v.v\n             obj_dir/sdr_para.v.sv\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:105: Define or directive not defined: \'`I_NOP\'\n  init_state_r <= `I_NOP;\n                  ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  init_state_r <= `I_NOP;\n                        ^\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:110: Define or directive not defined: \'`I_NOP\'\n    `I_NOP:  \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:110: syntax error, unexpected \':\', expecting endcase\n    `I_NOP:  \n          ^\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:111: Define or directive not defined: \'`I_PRE\'\n     init_state_r <= done_200us ? `I_PRE:`I_NOP;  \n                                  ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:111: Define or directive not defined: \'`I_NOP\'\n     init_state_r <= done_200us ? `I_PRE:`I_NOP;  \n                                         ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:113: Define or directive not defined: \'`I_PRE\'\n    `I_PRE:  \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:114: Define or directive not defined: \'`I_AR1\'\n     init_state_r <= (TRP_CLK == 0) ? `I_AR1:`I_TRP; \n                                      ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:114: Define or directive not defined: \'`I_TRP\'\n     init_state_r <= (TRP_CLK == 0) ? `I_AR1:`I_TRP; \n                                             ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:116: Define or directive not defined: \'`I_TRP\'\n    `I_TRP:  \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:117: Define or directive not defined: \'`I_AR1\'\n     init_state_r <= (cnt_clk_r == TRP_CLK) ? `I_AR1:`I_TRP;   \n                                              ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:117: Define or directive not defined: \'`I_TRP\'\n     init_state_r <= (cnt_clk_r == TRP_CLK) ? `I_AR1:`I_TRP;   \n                                                     ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:120: Define or directive not defined: \'`I_AR1\'\n    `I_AR1:  \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:121: Define or directive not defined: \'`I_AR2\'\n     init_state_r <= (TRFC_CLK == 0) ? `I_AR2:`I_TRF1; \n                                       ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:121: Define or directive not defined: \'`I_TRF1\'\n     init_state_r <= (TRFC_CLK == 0) ? `I_AR2:`I_TRF1; \n                                              ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:123: Define or directive not defined: \'`I_TRF1\'\n    `I_TRF1: \n    ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:124: Define or directive not defined: \'`I_AR2\'\n     init_state_r <= (cnt_clk_r == TRFC_CLK) ? `I_AR2:`I_TRF1; \n                                               ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:124: Define or directive not defined: \'`I_TRF1\'\n     init_state_r <= (cnt_clk_r == TRFC_CLK) ? `I_AR2:`I_TRF1; \n                                                      ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:127: Define or directive not defined: \'`I_AR2\'\n    `I_AR2:  \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:128: Define or directive not defined: \'`I_AR3\'\n     init_state_r <= (TRFC_CLK == 0) ? `I_AR3:`I_TRF2; \n                                       ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:128: Define or directive not defined: \'`I_TRF2\'\n     init_state_r <= (TRFC_CLK == 0) ? `I_AR3:`I_TRF2; \n                                              ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:130: Define or directive not defined: \'`I_TRF2\'\n    `I_TRF2: \n    ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:131: Define or directive not defined: \'`I_AR3\'\n     init_state_r <= (cnt_clk_r == TRFC_CLK) ? `I_AR3:`I_TRF2;   \n                                               ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:131: Define or directive not defined: \'`I_TRF2\'\n     init_state_r <= (cnt_clk_r == TRFC_CLK) ? `I_AR3:`I_TRF2;   \n                                                      ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:134: Define or directive not defined: \'`I_AR3\'\n    `I_AR3:  init_state_r <= (TRFC_CLK == 0) ? `I_AR4:`I_TRF3; \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:134: Define or directive not defined: \'`I_AR4\'\n    `I_AR3:  init_state_r <= (TRFC_CLK == 0) ? `I_AR4:`I_TRF3; \n                                               ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:134: Define or directive not defined: \'`I_TRF3\'\n    `I_AR3:  init_state_r <= (TRFC_CLK == 0) ? `I_AR4:`I_TRF3; \n                                                      ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:136: Define or directive not defined: \'`I_TRF3\'\n    `I_TRF3: init_state_r <= (cnt_clk_r == TRFC_CLK) ? `I_AR4:`I_TRF3; \n    ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:136: Define or directive not defined: \'`I_AR4\'\n    `I_TRF3: init_state_r <= (cnt_clk_r == TRFC_CLK) ? `I_AR4:`I_TRF3; \n                                                       ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:136: Define or directive not defined: \'`I_TRF3\'\n    `I_TRF3: init_state_r <= (cnt_clk_r == TRFC_CLK) ? `I_AR4:`I_TRF3; \n                                                              ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:139: Define or directive not defined: \'`I_AR4\'\n    `I_AR4:  init_state_r <= (TRFC_CLK == 0) ? `I_AR5:`I_TRF4; \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:139: Define or directive not defined: \'`I_AR5\'\n    `I_AR4:  init_state_r <= (TRFC_CLK == 0) ? `I_AR5:`I_TRF4; \n                                               ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:139: Define or directive not defined: \'`I_TRF4\'\n    `I_AR4:  init_state_r <= (TRFC_CLK == 0) ? `I_AR5:`I_TRF4; \n                                                      ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:140: Define or directive not defined: \'`I_TRF4\'\n    `I_TRF4: init_state_r <= (cnt_clk_r == TRFC_CLK) ? `I_AR5:`I_TRF4;  \n    ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:140: Define or directive not defined: \'`I_AR5\'\n    `I_TRF4: init_state_r <= (cnt_clk_r == TRFC_CLK) ? `I_AR5:`I_TRF4;  \n                                                       ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:140: Define or directive not defined: \'`I_TRF4\'\n    `I_TRF4: init_state_r <= (cnt_clk_r == TRFC_CLK) ? `I_AR5:`I_TRF4;  \n                                                              ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:143: Define or directive not defined: \'`I_AR5\'\n    `I_AR5:  init_state_r <= (TRFC_CLK == 0) ? `I_AR6:`I_TRF5; \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:143: Define or directive not defined: \'`I_AR6\'\n    `I_AR5:  init_state_r <= (TRFC_CLK == 0) ? `I_AR6:`I_TRF5; \n                                               ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:143: Define or directive not defined: \'`I_TRF5\'\n    `I_AR5:  init_state_r <= (TRFC_CLK == 0) ? `I_AR6:`I_TRF5; \n                                                      ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:144: Define or directive not defined: \'`I_TRF5\'\n    `I_TRF5: init_state_r <= (`end_trfc) ? `I_AR6:`I_TRF5;   \n    ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:144: Define or directive not defined: \'`end_trfc\'\n    `I_TRF5: init_state_r <= (`end_trfc) ? `I_AR6:`I_TRF5;   \n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:144: Define or directive not defined: \'`I_AR6\'\n    `I_TRF5: init_state_r <= (`end_trfc) ? `I_AR6:`I_TRF5;   \n                                           ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:144: Define or directive not defined: \'`I_TRF5\'\n    `I_TRF5: init_state_r <= (`end_trfc) ? `I_AR6:`I_TRF5;   \n                                                  ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:147: Define or directive not defined: \'`I_AR6\'\n    `I_AR6:  init_state_r <= (TRFC_CLK == 0) ? `I_AR7:`I_TRF6; \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:147: Define or directive not defined: \'`I_AR7\'\n    `I_AR6:  init_state_r <= (TRFC_CLK == 0) ? `I_AR7:`I_TRF6; \n                                               ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:147: Define or directive not defined: \'`I_TRF6\'\n    `I_AR6:  init_state_r <= (TRFC_CLK == 0) ? `I_AR7:`I_TRF6; \n                                                      ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:148: Define or directive not defined: \'`I_TRF6\'\n    `I_TRF6: init_state_r <= (`end_trfc) ? `I_AR7:`I_TRF6;   \n    ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:148: Define or directive not defined: \'`end_trfc\'\n    `I_TRF6: init_state_r <= (`end_trfc) ? `I_AR7:`I_TRF6;   \n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_ctrl.v:148: Define or directive not defined: \'`I_AR7\'\n    `I_TRF6: init_state_r <= (`end_trfc) ? `I_AR7:`I_TRF6;   \n                                           ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module sdram_ctrl(
				clk,
				rst_n,
				sdram_wr_req,
				sdram_rd_req,
				sdram_wr_ack,
				sdram_rd_ack,
				init_state,
				work_state,
				cnt_clk
			);
			

input clk;
input rst_n;



input sdram_wr_req;
input sdram_rd_req;

output sdram_wr_ack;
output sdram_rd_ack;







output[4:0] init_state;
output[3:0] work_state;
output[8:0] cnt_clk;



wire sdram_init_done;
wire sdram_busy;
reg sdram_ref_req;
wire sdram_ref_ack;

`include "sdr_para.v"



parameter	TRP_CLK		= 9'd4,
					TRFC_CLK		= 9'd6,
					TMRD_CLK		= 9'd6,
					TRCD_CLK		= 9'd2,
					TCL_CLK			= 9'd2,
					TREAD_CLK	= 9'd8,
					TWRITE_CLK	= 9'd8,
					TDAL_CLK		= 9'd3;





wire done_200us;
reg[14:0] cnt_200us; 

always @ (posedge clk or negedge rst_n) 
	if(!rst_n) 
			cnt_200us <= 15'd0;
	else if(cnt_200us < 15'd20_000) 
			cnt_200us <= cnt_200us+1'b1;	

assign done_200us = (cnt_200us == 15'd20_000);





reg[8:0] cnt_clk_r;
reg 		cnt_rst_n;

always @ (posedge clk or negedge rst_n) 
	if(!rst_n) 
		cnt_clk_r <= 9'd0;
	else if(!cnt_rst_n) 
		cnt_clk_r <= 9'd0;
	else 
		cnt_clk_r <= cnt_clk_r+1'b1;
	
assign cnt_clk = cnt_clk_r;




reg[4:0] init_state_r;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
		init_state_r <= `I_NOP;
	else 
		case (init_state_r)
		

				`I_NOP: 	
					init_state_r <= done_200us ? `I_PRE:`I_NOP;		

				`I_PRE: 	
					init_state_r <= (TRP_CLK == 0) ? `I_AR1:`I_TRP;	

				`I_TRP: 	
					init_state_r <= (cnt_clk_r	== TRP_CLK) ? `I_AR1:`I_TRP;			
				

				`I_AR1: 	
					init_state_r <= (TRFC_CLK == 0) ? `I_AR2:`I_TRF1;	

				`I_TRF1:	
					init_state_r <= (cnt_clk_r	== TRFC_CLK) ? `I_AR2:`I_TRF1;	
				

				`I_AR2: 	
					init_state_r <= (TRFC_CLK == 0) ? `I_AR3:`I_TRF2; 

				`I_TRF2:	
					init_state_r <= (cnt_clk_r	== TRFC_CLK) ? `I_AR3:`I_TRF2; 		
				

				`I_AR3: 	init_state_r <= (TRFC_CLK == 0) ? `I_AR4:`I_TRF3; 

				`I_TRF3:	init_state_r <= (cnt_clk_r	== TRFC_CLK) ? `I_AR4:`I_TRF3;	
				

				`I_AR4: 	init_state_r <= (TRFC_CLK == 0) ? `I_AR5:`I_TRF4; 
				`I_TRF4:	init_state_r <= (cnt_clk_r	== TRFC_CLK) ? `I_AR5:`I_TRF4; 	
				

				`I_AR5: 	init_state_r <= (TRFC_CLK == 0) ? `I_AR6:`I_TRF5; 
				`I_TRF5:	init_state_r <= (`end_trfc) ? `I_AR6:`I_TRF5;			
				

				`I_AR6: 	init_state_r <= (TRFC_CLK == 0) ? `I_AR7:`I_TRF6; 
				`I_TRF6:	init_state_r <= (`end_trfc) ? `I_AR7:`I_TRF6;			
				

				`I_AR7: 	init_state_r <= (TRFC_CLK == 0) ? `I_AR8:`I_TRF7; 
				`I_TRF7: 	init_state_r <= (`end_trfc) ? `I_AR8:`I_TRF7;		
				

				`I_AR8: 	init_state_r <= (TRFC_CLK == 0) ? `I_MRS:`I_TRF8;	
				`I_TRF8:	init_state_r <= (cnt_clk_r	== TRFC_CLK) ? `I_MRS:`I_TRF8;			
				

				`I_MRS:		init_state_r <= (TMRD_CLK == 0) ? `I_DONE:`I_TMRD;
				

				`I_TMRD:	init_state_r <= (cnt_clk_r	== TRFC_CLK) ? `I_DONE:`I_TMRD;		
				

				`I_DONE:	init_state_r <= `I_DONE;		
				default: init_state_r <= `I_NOP;
		endcase


assign init_state = init_state_r;
assign sdram_init_done = (init_state_r == `I_DONE);







reg[10:0] cnt_15us;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
		cnt_15us <= 11'd0;
	else if(cnt_15us < 11'd1499) 
		cnt_15us <= cnt_15us+1'b1;
	else 
		cnt_15us <= 11'd0;	

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
		sdram_ref_req <= 1'b0;
	else if(cnt_15us == 11'd1498) 
		sdram_ref_req <= 1'b1;
	else if(sdram_ref_ack) 
		sdram_ref_req <= 1'b0;

		
		



reg[3:0] work_state_r;
reg 			sys_r_wn;

always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) 
		work_state_r <= `W_IDLE;
	else 
		case (work_state_r)

 			`W_IDLE:	

						if(sdram_ref_req & sdram_init_done) 
							begin
								work_state_r <= `W_AR;
								sys_r_wn <= 1'b1;
							end 
						

						else if(sdram_wr_req & sdram_init_done)
							begin
								work_state_r <= `W_ACTIVE;
								sys_r_wn <= 1'b0;	
							end		

						else if(sdram_rd_req && sdram_init_done)
							begin
								work_state_r <= `W_ACTIVE;
								sys_r_wn <= 1'b1;	
							end

						else 
							begin 
								work_state_r <= `W_IDLE;
								sys_r_wn <= 1'b1;
							end	
						
						

			`W_ACTIVE: 	
						if(TRCD_CLK == 0)
							if(sys_r_wn) 
									work_state_r <= `W_READ;
							else 
									work_state_r <= `W_WRITE;
						else 
							work_state_r <= `W_TRCD;


			`W_TRCD:	 if(cnt_clk_r	== TRCD_CLK-1)
						 	 if(sys_r_wn) 
									work_state_r <= `W_READ;
						 	 else 
									work_state_r <= `W_WRITE;
						else 
							work_state_r <= `W_TRCD;
							

			`W_READ:	work_state_r <= `W_CL;
			

			`W_CL:		work_state_r <= (cnt_clk_r== TCL_CLK-1) ? `W_RD:`W_CL;	
			

			`W_RD:		work_state_r <= (cnt_clk_r	== TREAD_CLK+2) ? `W_RWAIT:`W_RD;
			

			`W_RWAIT:	work_state_r <= (cnt_clk_r	== TRP_CLK) ? `W_IDLE:`W_RWAIT;
			

			`W_WRITE:	work_state_r <= `W_WD;
			

			`W_WD:		work_state_r <= (cnt_clk_r	== TWRITE_CLK-2) ? `W_TDAL:`W_WD;
			

			`W_TDAL:		work_state_r <= (`end_tdal) ? `W_IDLE:`W_TDAL;
			
			

			`W_AR:		
					work_state_r <= (TRFC_CLK == 0) ? `W_IDLE:`W_TRFC; 
					

			`W_TRFC:	
					work_state_r <= (cnt_clk_r	== TRFC_CLK) ? `W_IDLE:`W_TRFC;
					
			default: 	
					work_state_r <= `W_IDLE;
					
		endcase
end


assign work_state = work_state_r;	
	




assign sdram_ref_ack = (work_state_r == `W_AR);		





assign sdram_wr_ack = ((work_state == `W_TRCD) & ~sys_r_wn) | (work_state == `W_WRITE) 
						| ((work_state == `W_WD) & (cnt_clk_r < 9'd6));		





assign sdram_rd_ack = (work_state_r == `W_RD) & (cnt_clk_r >=9'd0) & (cnt_clk_r < 9'd8);













always @ (init_state_r or work_state_r or cnt_clk_r) 
	begin
		case (init_state_r)

	    	`I_NOP:	
				cnt_rst_n <= 1'b0;

	   	`I_PRE:	cnt_rst_n <= (TRP_CLK != 0);	

	   	`I_TRP:	cnt_rst_n <= (cnt_clk_r	== TRP_CLK) ? 1'b0:1'b1;	
			

	    	`I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:
	         		cnt_rst_n <= (TRFC_CLK != 0);
						

	    	`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8:
	         		cnt_rst_n <= (`end_trfc) ? 1'b0:1'b1;	
						
			`I_MRS:	cnt_rst_n <= (TMRD_CLK != 0);
			`I_TMRD:	cnt_rst_n <= (cnt_clk_r	== TMRD_CLK) ? 1'b0:1'b1;
			
		   `I_DONE:
						case (work_state_r)

								`W_IDLE:	cnt_rst_n <= 1'b0;
								

								`W_ACTIVE: 	cnt_rst_n <= (TRCD_CLK == 0) ? 1'b0:1'b1;
								

								`W_TRCD:	cnt_rst_n <= (cnt_clk_r	== TRCD_CLK-1) ? 1'b0:1'b1;
								

								`W_CL:		cnt_rst_n <= (cnt_clk_r   == TCL_CLK-1) ? 1'b0:1'b1;
								

								`W_RD:		cnt_rst_n <= (cnt_clk_r	== TREAD_CLK+2) ? 1'b0:1'b1;
								

								`W_RWAIT:	cnt_rst_n <= (`end_trwait) ? 1'b0:1'b1;
								

								`W_WD:		cnt_rst_n <= (`end_twrite) ? 1'b0:1'b1;
								

								`W_TDAL:	cnt_rst_n <= (`end_tdal) ? 1'b0:1'b1;
								

								`W_TRFC:	
										cnt_rst_n <= (`end_trfc) ? 1'b0:1'b1;
										
								default: cnt_rst_n <= 1'b0;
		         	endcase
		default: 
				cnt_rst_n <= 1'b0;
		endcase
	end

endmodule
module sdram_ctrl(
				clk,
				rst_n,
				sdram_wr_req,
				sdram_rd_req,
				sdram_wr_ack,
				sdram_rd_ack,
				init_state,
				work_state,
				cnt_clk
			);

			

input clk;
input rst_n;



input sdram_wr_req;
input sdram_rd_req;

output sdram_wr_ack;
output sdram_rd_ack;







output[4:0] init_state;
output[3:0] work_state;
output[8:0] cnt_clk;



wire sdram_init_done;
wire sdram_busy;
reg sdram_ref_req;
wire sdram_ref_ack;

`include "sdr_para.v"



parameter	TRP_CLK		= 9'd4,
					TRFC_CLK		= 9'd6,
					TMRD_CLK		= 9'd6,
					TRCD_CLK		= 9'd2,
					TCL_CLK			= 9'd2,
					TREAD_CLK	= 9'd8,
					TWRITE_CLK	= 9'd8,
					TDAL_CLK		= 9'd3;





wire done_200us;
reg[14:0] cnt_200us; 

always @ (posedge clk or negedge rst_n) 
	if(!rst_n) 
			cnt_200us <= 15'd0;
	else if(cnt_200us < 15'd20_000) 
			cnt_200us <= cnt_200us+1'b1;	

assign done_200us = (cnt_200us == 15'd20_000);





reg[8:0] cnt_clk_r;
reg 		cnt_rst_n;

always @ (posedge clk or negedge rst_n) 
	if(!rst_n) 
		cnt_clk_r <= 9'd0;
	else if(!cnt_rst_n) 
		cnt_clk_r <= 9'd0;
	else 
		cnt_clk_r <= cnt_clk_r+1'b1;
	
assign cnt_clk = cnt_clk_r;




reg[4:0] init_state_r;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
		init_state_r <= `I_NOP;
	else 
		case (init_state_r)
		

				`I_NOP: 	
					init_state_r <= done_200us ? `I_PRE:`I_NOP;		

				`I_PRE: 	
					init_state_r <= (TRP_CLK == 0) ? `I_AR1:`I_TRP;	

				`I_TRP: 	
					init_state_r <= (cnt_clk_r	== TRP_CLK) ? `I_AR1:`I_TRP;			
				

				`I_AR1: 	
					init_state_r <= (TRFC_CLK == 0) ? `I_AR2:`I_TRF1;	

				`I_TRF1:	
					init_state_r <= (cnt_clk_r	== TRFC_CLK) ? `I_AR2:`I_TRF1;	
				

				`I_AR2: 	
					init_state_r <= (TRFC_CLK == 0) ? `I_AR3:`I_TRF2; 

				`I_TRF2:	
					init_state_r <= (cnt_clk_r	== TRFC_CLK) ? `I_AR3:`I_TRF2; 		
				

				`I_AR3: 	init_state_r <= (TRFC_CLK == 0) ? `I_AR4:`I_TRF3; 

				`I_TRF3:	init_state_r <= (cnt_clk_r	== TRFC_CLK) ? `I_AR4:`I_TRF3;	
				

				`I_AR4: 	init_state_r <= (TRFC_CLK == 0) ? `I_AR5:`I_TRF4; 
				`I_TRF4:	init_state_r <= (cnt_clk_r	== TRFC_CLK) ? `I_AR5:`I_TRF4; 	
				

				`I_AR5: 	init_state_r <= (TRFC_CLK == 0) ? `I_AR6:`I_TRF5; 
				`I_TRF5:	init_state_r <= (`end_trfc) ? `I_AR6:`I_TRF5;			
				

				`I_AR6: 	init_state_r <= (TRFC_CLK == 0) ? `I_AR7:`I_TRF6; 
				`I_TRF6:	init_state_r <= (`end_trfc) ? `I_AR7:`I_TRF6;			
				

				`I_AR7: 	init_state_r <= (TRFC_CLK == 0) ? `I_AR8:`I_TRF7; 
				`I_TRF7: 	init_state_r <= (`end_trfc) ? `I_AR8:`I_TRF7;		
				

				`I_AR8: 	init_state_r <= (TRFC_CLK == 0) ? `I_MRS:`I_TRF8;	
				`I_TRF8:	init_state_r <= (cnt_clk_r	== TRFC_CLK) ? `I_MRS:`I_TRF8;			
				

				`I_MRS:		init_state_r <= (TMRD_CLK == 0) ? `I_DONE:`I_TMRD;
				

				`I_TMRD:	init_state_r <= (cnt_clk_r	== TRFC_CLK) ? `I_DONE:`I_TMRD;		
				

				`I_DONE:	init_state_r <= `I_DONE;		
				default: init_state_r <= `I_NOP;
		endcase


assign init_state = init_state_r;
assign sdram_init_done = (init_state_r == `I_DONE);







reg[10:0] cnt_15us;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
		cnt_15us <= 11'd0;
	else if(cnt_15us < 11'd1499) 
		cnt_15us <= cnt_15us+1'b1;
	else 
		cnt_15us <= 11'd0;	

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
		sdram_ref_req <= 1'b0;
	else if(cnt_15us == 11'd1498) 
		sdram_ref_req <= 1'b1;
	else if(sdram_ref_ack) 
		sdram_ref_req <= 1'b0;

		
		



reg[3:0] work_state_r;
reg 			sys_r_wn;

always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) 
		work_state_r <= `W_IDLE;
	else 
		case (work_state_r)

 			`W_IDLE:	

						if(sdram_ref_req & sdram_init_done) 
							begin
								work_state_r <= `W_AR;
								sys_r_wn <= 1'b1;
							end 
						

						else if(sdram_wr_req & sdram_init_done)
							begin
								work_state_r <= `W_ACTIVE;
								sys_r_wn <= 1'b0;	
							end		

						else if(sdram_rd_req && sdram_init_done)
							begin
								work_state_r <= `W_ACTIVE;
								sys_r_wn <= 1'b1;	
							end

						else 
							begin 
								work_state_r <= `W_IDLE;
								sys_r_wn <= 1'b1;
							end	
						
						

			`W_ACTIVE: 	
						if(TRCD_CLK == 0)
							if(sys_r_wn) 
									work_state_r <= `W_READ;
							else 
									work_state_r <= `W_WRITE;
						else 
							work_state_r <= `W_TRCD;


			`W_TRCD:	 if(cnt_clk_r	== TRCD_CLK-1)
						 	 if(sys_r_wn) 
									work_state_r <= `W_READ;
						 	 else 
									work_state_r <= `W_WRITE;
						else 
							work_state_r <= `W_TRCD;
							

			`W_READ:	work_state_r <= `W_CL;
			

			`W_CL:		work_state_r <= (cnt_clk_r== TCL_CLK-1) ? `W_RD:`W_CL;	
			

			`W_RD:		work_state_r <= (cnt_clk_r	== TREAD_CLK+2) ? `W_RWAIT:`W_RD;
			

			`W_RWAIT:	work_state_r <= (cnt_clk_r	== TRP_CLK) ? `W_IDLE:`W_RWAIT;
			

			`W_WRITE:	work_state_r <= `W_WD;
			

			`W_WD:		work_state_r <= (cnt_clk_r	== TWRITE_CLK-2) ? `W_TDAL:`W_WD;
			

			`W_TDAL:		work_state_r <= (`end_tdal) ? `W_IDLE:`W_TDAL;
			
			

			`W_AR:		
					work_state_r <= (TRFC_CLK == 0) ? `W_IDLE:`W_TRFC; 
					

			`W_TRFC:	
					work_state_r <= (cnt_clk_r	== TRFC_CLK) ? `W_IDLE:`W_TRFC;
					
			default: 	
					work_state_r <= `W_IDLE;
					
		endcase
end


assign work_state = work_state_r;	
	




assign sdram_ref_ack = (work_state_r == `W_AR);		





assign sdram_wr_ack = ((work_state == `W_TRCD) & ~sys_r_wn) | (work_state == `W_WRITE) 
						| ((work_state == `W_WD) & (cnt_clk_r < 9'd6));		





assign sdram_rd_ack = (work_state_r == `W_RD) & (cnt_clk_r >=9'd0) & (cnt_clk_r < 9'd8);













always @ (init_state_r or work_state_r or cnt_clk_r) 
	begin
		case (init_state_r)

	    	`I_NOP:	
				cnt_rst_n <= 1'b0;

	   	`I_PRE:	cnt_rst_n <= (TRP_CLK != 0);	

	   	`I_TRP:	cnt_rst_n <= (cnt_clk_r	== TRP_CLK) ? 1'b0:1'b1;	
			

	    	`I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:
	         		cnt_rst_n <= (TRFC_CLK != 0);
						

	    	`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8:
	         		cnt_rst_n <= (`end_trfc) ? 1'b0:1'b1;	
						
			`I_MRS:	cnt_rst_n <= (TMRD_CLK != 0);
			`I_TMRD:	cnt_rst_n <= (cnt_clk_r	== TMRD_CLK) ? 1'b0:1'b1;
			
		   `I_DONE:
						case (work_state_r)

								`W_IDLE:	cnt_rst_n <= 1'b0;
								

								`W_ACTIVE: 	cnt_rst_n <= (TRCD_CLK == 0) ? 1'b0:1'b1;
								

								`W_TRCD:	cnt_rst_n <= (cnt_clk_r	== TRCD_CLK-1) ? 1'b0:1'b1;
								

								`W_CL:		cnt_rst_n <= (cnt_clk_r   == TCL_CLK-1) ? 1'b0:1'b1;
								

								`W_RD:		cnt_rst_n <= (cnt_clk_r	== TREAD_CLK+2) ? 1'b0:1'b1;
								

								`W_RWAIT:	cnt_rst_n <= (`end_trwait) ? 1'b0:1'b1;
								

								`W_WD:		cnt_rst_n <= (`end_twrite) ? 1'b0:1'b1;
								

								`W_TDAL:	cnt_rst_n <= (`end_tdal) ? 1'b0:1'b1;
								

								`W_TRFC:	
										cnt_rst_n <= (`end_trfc) ? 1'b0:1'b1;
										
								default: cnt_rst_n <= 1'b0;
		         	endcase
		default: 
				cnt_rst_n <= 1'b0;
		endcase
	end

endmodule