data/full_repos/permissive/119715647/sim/gameFunct/SpeedyLevels_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/gameFunct/SpeedyLevels_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/gameFunct/SpeedyLevels_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/gameFunct/SpeedyLevels_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/gameFunct/SpeedyLevels_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: data/full_repos/permissive/119715647/sim/gameFunct/SpeedyLevels_tb.v:8: Cannot find file containing module: \'SpeedyLevels\'\n  SpeedyLevels DUT_SL(clk, stacked, shorterTime);\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119715647/sim/gameFunct,data/full_repos/permissive/119715647/SpeedyLevels\n             data/full_repos/permissive/119715647/sim/gameFunct,data/full_repos/permissive/119715647/SpeedyLevels.v\n             data/full_repos/permissive/119715647/sim/gameFunct,data/full_repos/permissive/119715647/SpeedyLevels.sv\n             SpeedyLevels\n             SpeedyLevels.v\n             SpeedyLevels.sv\n             obj_dir/SpeedyLevels\n             obj_dir/SpeedyLevels.v\n             obj_dir/SpeedyLevels.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SpeedyLevels_tb ();
  reg clk;
  reg stacked;
  wire [7:0] shorterTime;

  SpeedyLevels DUT_SL(clk, stacked, shorterTime);

  always begin
    clk = 0;
    #2;
    clk = 1;
    #2;
  end

  always begin
    stacked = 0;
    #5;
    stacked = 1;
    #5;
  end

endmodule
module SpeedyLevels_tb ();

  reg clk;
  reg stacked;
  wire [7:0] shorterTime;

  SpeedyLevels DUT_SL(clk, stacked, shorterTime);

  always begin
    clk = 0;
    #2;
    clk = 1;
    #2;
  end

  always begin
    stacked = 0;
    #5;
    stacked = 1;
    #5;
  end

endmodule