data/full_repos/permissive/150152921/apps/sha1/step3/rtl/sha1_w_mem.v
 line:2: before: "?"
data/verilator_xmls/6f0ffbd4-1f7d-4e43-93e2-a0226334dfe1.xml
module sha1_w_mem(
                  input wire           clk,
                  input wire           reset_n,

                  input wire [511 : 0] block,

                  input wire           init,
                  input wire           next,

                  output wire [31 : 0] w_mem00,
                  output wire [31 : 0] w_mem01,
                  output wire [31 : 0] w_mem02,
                  output wire [31 : 0] w_mem03,
                  output wire [31 : 0] w_mem04,
                  output wire [31 : 0] w_mem05,
                  output wire [31 : 0] w_mem06,
                  output wire [31 : 0] w_mem07,
                  output wire [31 : 0] w_mem08,
                  output wire [31 : 0] w_mem09,
                  output wire [31 : 0] w_mem10,
                  output wire [31 : 0] w_mem11,
                  output wire [31 : 0] w_mem12,
                  output wire [31 : 0] w_mem13,
                  output wire [31 : 0] w_mem14,
                  output wire [31 : 0] w_mem15,
                  output wire [31 : 0] w_mem16,
                  output wire [31 : 0] w_mem16_dup1,
                  output wire [31 : 0] w_mem16_dup2,
                  output wire [31 : 0] w_mem16_dup3,
                  output wire [31 : 0] w
                 );





  parameter SHA1_ROUNDS = 79;

  parameter CTRL_IDLE   = 1'b0;
  parameter CTRL_UPDATE = 1'b1;





  reg [31 : 0] w_mem [0 : 15];
  reg [31 : 0] w_mem00_new;
  reg [31 : 0] w_mem01_new;
  reg [31 : 0] w_mem02_new;
  reg [31 : 0] w_mem03_new;
  reg [31 : 0] w_mem04_new;
  reg [31 : 0] w_mem05_new;
  reg [31 : 0] w_mem06_new;
  reg [31 : 0] w_mem07_new;
  reg [31 : 0] w_mem08_new;
  reg [31 : 0] w_mem09_new;
  reg [31 : 0] w_mem10_new;
  reg [31 : 0] w_mem11_new;
  reg [31 : 0] w_mem12_new;
  reg [31 : 0] w_mem13_new;
  reg [31 : 0] w_mem14_new;
  reg [31 : 0] w_mem15_new;
  reg          w_mem_we;

  reg [6 : 0] w_ctr_reg;
  reg [6 : 0] w_ctr_new;
  reg         w_ctr_we;
  reg         w_ctr_inc;
  reg         w_ctr_rst;

  reg         sha1_w_mem_ctrl_reg;
  reg         sha1_w_mem_ctrl_new;
  reg         sha1_w_mem_ctrl_we;





  reg [31 : 0] w_tmp;
  reg [31 : 0] w_new;





  assign w = w_tmp;

  assign w_mem00 = w_mem[0];
  assign w_mem01 = w_mem[1];
  assign w_mem02 = w_mem[2];
  assign w_mem03 = w_mem[3];
  assign w_mem04 = w_mem[4];
  assign w_mem05 = w_mem[5];
  assign w_mem06 = w_mem[6];
  assign w_mem07 = w_mem[7];
  assign w_mem08 = w_mem[8];
  assign w_mem09 = w_mem[9];
  assign w_mem10 = w_mem[10];
  assign w_mem11 = w_mem[11];
  assign w_mem12 = w_mem[12];
  assign w_mem13 = w_mem[13];
  assign w_mem14 = w_mem[14];
  assign w_mem15 = w_mem[15];


reg [31:0] w_new_0q;
reg [31:0] w_new_0q_dup1;
reg [31:0] w_new_0q_dup2;
reg [31:0] w_new_0q_dup3;
reg [31:0] w_mem_new_precalc;
reg [31:0] w_mem_new_precalc_rot;



  always@* begin
    w_mem_new_precalc = (w_mem[14] ^ w_mem[9] ^ w_mem[3] ^ w_mem[1]);
    w_mem_new_precalc_rot = {w_mem_new_precalc[30:0], w_mem_new_precalc[31]}; 
  end 

  always@(posedge clk) begin
    if(w_ctr_reg > 15) begin
      w_new_0q      <= w_mem_new_precalc_rot;
      w_new_0q_dup1 <= w_mem_new_precalc_rot;
      w_new_0q_dup2 <= w_mem_new_precalc_rot;
      w_new_0q_dup3 <= w_mem_new_precalc_rot;
    end 
    else begin
      w_new_0q      <= w_new;
      w_new_0q_dup1 <= w_new;
      w_new_0q_dup2 <= w_new;
      w_new_0q_dup3 <= w_new;
    end 
  end 

assign w_mem16      = w_new_0q; 
assign w_mem16_dup1 = w_new_0q_dup1; 
assign w_mem16_dup2 = w_new_0q_dup2; 
assign w_mem16_dup3 = w_new_0q_dup3; 








  always @ (posedge clk)
    begin : reg_update
      if (!reset_n)
        begin
          w_mem[00]           <= 32'h0;
          w_mem[01]           <= 32'h0;
          w_mem[02]           <= 32'h0;
          w_mem[03]           <= 32'h0;
          w_mem[04]           <= 32'h0;
          w_mem[05]           <= 32'h0;
          w_mem[06]           <= 32'h0;
          w_mem[07]           <= 32'h0;
          w_mem[08]           <= 32'h0;
          w_mem[09]           <= 32'h0;
          w_mem[10]           <= 32'h0;
          w_mem[11]           <= 32'h0;
          w_mem[12]           <= 32'h0;
          w_mem[13]           <= 32'h0;
          w_mem[14]           <= 32'h0;
          w_mem[15]           <= 32'h0;
          w_ctr_reg           <= 7'h0;
          sha1_w_mem_ctrl_reg <= CTRL_IDLE;
        end
      else
        begin
          if (w_mem_we)
            begin
              w_mem[00] <= w_mem00_new;
              w_mem[01] <= w_mem01_new;
              w_mem[02] <= w_mem02_new;
              w_mem[03] <= w_mem03_new;
              w_mem[04] <= w_mem04_new;
              w_mem[05] <= w_mem05_new;
              w_mem[06] <= w_mem06_new;
              w_mem[07] <= w_mem07_new;
              w_mem[08] <= w_mem08_new;
              w_mem[09] <= w_mem09_new;
              w_mem[10] <= w_mem10_new;
              w_mem[11] <= w_mem11_new;
              w_mem[12] <= w_mem12_new;
              w_mem[13] <= w_mem13_new;
              w_mem[14] <= w_mem14_new;
              w_mem[15] <= w_mem15_new;
            end

          if (w_ctr_we)
            w_ctr_reg <= w_ctr_new;

          if (sha1_w_mem_ctrl_we)
            sha1_w_mem_ctrl_reg <= sha1_w_mem_ctrl_new;
        end
    end








  always @*
    begin : select_w
      if (w_ctr_reg < 16)
        begin
          w_tmp = w_mem[w_ctr_reg[3 : 0]];
        end
      else
        begin
          w_tmp = w_new;
        end
    end








  always @*
    begin : w_mem_update_logic
      reg [31 : 0] w_0;
      reg [31 : 0] w_2;
      reg [31 : 0] w_8;
      reg [31 : 0] w_13;
      reg [31 : 0] w_16;

      w_mem00_new = 32'h0;
      w_mem01_new = 32'h0;
      w_mem02_new = 32'h0;
      w_mem03_new = 32'h0;
      w_mem04_new = 32'h0;
      w_mem05_new = 32'h0;
      w_mem06_new = 32'h0;
      w_mem07_new = 32'h0;
      w_mem08_new = 32'h0;
      w_mem09_new = 32'h0;
      w_mem10_new = 32'h0;
      w_mem11_new = 32'h0;
      w_mem12_new = 32'h0;
      w_mem13_new = 32'h0;
      w_mem14_new = 32'h0;
      w_mem15_new = 32'h0;
      w_mem_we    = 0;

      w_0   = w_mem[0];
      w_2   = w_mem[2];
      w_8   = w_mem[8];
      w_13  = w_mem[13];
      w_16  = w_13 ^ w_8 ^ w_2 ^ w_0;
      w_new = {w_16[30 : 0], w_16[31]};

      if (init)
        begin
          w_mem00_new = block[511 : 480];
          w_mem01_new = block[479 : 448];
          w_mem02_new = block[447 : 416];
          w_mem03_new = block[415 : 384];
          w_mem04_new = block[383 : 352];
          w_mem05_new = block[351 : 320];
          w_mem06_new = block[319 : 288];
          w_mem07_new = block[287 : 256];
          w_mem08_new = block[255 : 224];
          w_mem09_new = block[223 : 192];
          w_mem10_new = block[191 : 160];
          w_mem11_new = block[159 : 128];
          w_mem12_new = block[127 :  96];
          w_mem13_new = block[95  :  64];
          w_mem14_new = block[63  :  32];
          w_mem15_new = block[31  :   0];
          w_mem_we    = 1;
        end

      else if (w_ctr_reg > 15)
        begin
          w_mem00_new = w_mem[01];
          w_mem01_new = w_mem[02];
          w_mem02_new = w_mem[03];
          w_mem03_new = w_mem[04];
          w_mem04_new = w_mem[05];
          w_mem05_new = w_mem[06];
          w_mem06_new = w_mem[07];
          w_mem07_new = w_mem[08];
          w_mem08_new = w_mem[09];
          w_mem09_new = w_mem[10];
          w_mem10_new = w_mem[11];
          w_mem11_new = w_mem[12];
          w_mem12_new = w_mem[13];
          w_mem13_new = w_mem[14];
          w_mem14_new = w_mem[15];
          w_mem15_new = w_new;
          if(next) 
            w_mem_we    = 1;
        end
    end








  always @*
    begin : w_ctr
      w_ctr_new = 7'h0;
      w_ctr_we  = 0;

      if (w_ctr_rst)
        begin
          w_ctr_new = 7'h0;
          w_ctr_we  = 1;
        end

      if (w_ctr_inc)
        begin
          w_ctr_new = w_ctr_reg + 7'h01;
          w_ctr_we  = 1;
        end
    end







  always @*
    begin : sha1_w_mem_fsm
      w_ctr_rst           = 0;
      w_ctr_inc           = 0;
      sha1_w_mem_ctrl_new = CTRL_IDLE;
      sha1_w_mem_ctrl_we  = 0;

      case (sha1_w_mem_ctrl_reg)
        CTRL_IDLE:
          begin
            if (init)
              begin
                w_ctr_rst           = 1;
                sha1_w_mem_ctrl_new = CTRL_UPDATE;
                sha1_w_mem_ctrl_we  = 1;
              end
          end

        CTRL_UPDATE:
          begin
            if (next)
              begin
                w_ctr_inc = 1;
              end

            if (w_ctr_reg == SHA1_ROUNDS)
              begin
                sha1_w_mem_ctrl_new = CTRL_IDLE;
                sha1_w_mem_ctrl_we  = 1;
              end
          end
      endcase
    end
endmodule
module sha1_w_mem(
                  input wire           clk,
                  input wire           reset_n,

                  input wire [511 : 0] block,

                  input wire           init,
                  input wire           next,

                  output wire [31 : 0] w_mem00,
                  output wire [31 : 0] w_mem01,
                  output wire [31 : 0] w_mem02,
                  output wire [31 : 0] w_mem03,
                  output wire [31 : 0] w_mem04,
                  output wire [31 : 0] w_mem05,
                  output wire [31 : 0] w_mem06,
                  output wire [31 : 0] w_mem07,
                  output wire [31 : 0] w_mem08,
                  output wire [31 : 0] w_mem09,
                  output wire [31 : 0] w_mem10,
                  output wire [31 : 0] w_mem11,
                  output wire [31 : 0] w_mem12,
                  output wire [31 : 0] w_mem13,
                  output wire [31 : 0] w_mem14,
                  output wire [31 : 0] w_mem15,
                  output wire [31 : 0] w_mem16,
                  output wire [31 : 0] w_mem16_dup1,
                  output wire [31 : 0] w_mem16_dup2,
                  output wire [31 : 0] w_mem16_dup3,
                  output wire [31 : 0] w
                 );






  parameter SHA1_ROUNDS = 79;

  parameter CTRL_IDLE   = 1'b0;
  parameter CTRL_UPDATE = 1'b1;





  reg [31 : 0] w_mem [0 : 15];
  reg [31 : 0] w_mem00_new;
  reg [31 : 0] w_mem01_new;
  reg [31 : 0] w_mem02_new;
  reg [31 : 0] w_mem03_new;
  reg [31 : 0] w_mem04_new;
  reg [31 : 0] w_mem05_new;
  reg [31 : 0] w_mem06_new;
  reg [31 : 0] w_mem07_new;
  reg [31 : 0] w_mem08_new;
  reg [31 : 0] w_mem09_new;
  reg [31 : 0] w_mem10_new;
  reg [31 : 0] w_mem11_new;
  reg [31 : 0] w_mem12_new;
  reg [31 : 0] w_mem13_new;
  reg [31 : 0] w_mem14_new;
  reg [31 : 0] w_mem15_new;
  reg          w_mem_we;

  reg [6 : 0] w_ctr_reg;
  reg [6 : 0] w_ctr_new;
  reg         w_ctr_we;
  reg         w_ctr_inc;
  reg         w_ctr_rst;

  reg         sha1_w_mem_ctrl_reg;
  reg         sha1_w_mem_ctrl_new;
  reg         sha1_w_mem_ctrl_we;





  reg [31 : 0] w_tmp;
  reg [31 : 0] w_new;





  assign w = w_tmp;

  assign w_mem00 = w_mem[0];
  assign w_mem01 = w_mem[1];
  assign w_mem02 = w_mem[2];
  assign w_mem03 = w_mem[3];
  assign w_mem04 = w_mem[4];
  assign w_mem05 = w_mem[5];
  assign w_mem06 = w_mem[6];
  assign w_mem07 = w_mem[7];
  assign w_mem08 = w_mem[8];
  assign w_mem09 = w_mem[9];
  assign w_mem10 = w_mem[10];
  assign w_mem11 = w_mem[11];
  assign w_mem12 = w_mem[12];
  assign w_mem13 = w_mem[13];
  assign w_mem14 = w_mem[14];
  assign w_mem15 = w_mem[15];


reg [31:0] w_new_0q;
reg [31:0] w_new_0q_dup1;
reg [31:0] w_new_0q_dup2;
reg [31:0] w_new_0q_dup3;
reg [31:0] w_mem_new_precalc;
reg [31:0] w_mem_new_precalc_rot;



  always@* begin
    w_mem_new_precalc = (w_mem[14] ^ w_mem[9] ^ w_mem[3] ^ w_mem[1]);
    w_mem_new_precalc_rot = {w_mem_new_precalc[30:0], w_mem_new_precalc[31]}; 
  end 

  always@(posedge clk) begin
    if(w_ctr_reg > 15) begin
      w_new_0q      <= w_mem_new_precalc_rot;
      w_new_0q_dup1 <= w_mem_new_precalc_rot;
      w_new_0q_dup2 <= w_mem_new_precalc_rot;
      w_new_0q_dup3 <= w_mem_new_precalc_rot;
    end 
    else begin
      w_new_0q      <= w_new;
      w_new_0q_dup1 <= w_new;
      w_new_0q_dup2 <= w_new;
      w_new_0q_dup3 <= w_new;
    end 
  end 

assign w_mem16      = w_new_0q; 
assign w_mem16_dup1 = w_new_0q_dup1; 
assign w_mem16_dup2 = w_new_0q_dup2; 
assign w_mem16_dup3 = w_new_0q_dup3; 








  always @ (posedge clk)
    begin : reg_update
      if (!reset_n)
        begin
          w_mem[00]           <= 32'h0;
          w_mem[01]           <= 32'h0;
          w_mem[02]           <= 32'h0;
          w_mem[03]           <= 32'h0;
          w_mem[04]           <= 32'h0;
          w_mem[05]           <= 32'h0;
          w_mem[06]           <= 32'h0;
          w_mem[07]           <= 32'h0;
          w_mem[08]           <= 32'h0;
          w_mem[09]           <= 32'h0;
          w_mem[10]           <= 32'h0;
          w_mem[11]           <= 32'h0;
          w_mem[12]           <= 32'h0;
          w_mem[13]           <= 32'h0;
          w_mem[14]           <= 32'h0;
          w_mem[15]           <= 32'h0;
          w_ctr_reg           <= 7'h0;
          sha1_w_mem_ctrl_reg <= CTRL_IDLE;
        end
      else
        begin
          if (w_mem_we)
            begin
              w_mem[00] <= w_mem00_new;
              w_mem[01] <= w_mem01_new;
              w_mem[02] <= w_mem02_new;
              w_mem[03] <= w_mem03_new;
              w_mem[04] <= w_mem04_new;
              w_mem[05] <= w_mem05_new;
              w_mem[06] <= w_mem06_new;
              w_mem[07] <= w_mem07_new;
              w_mem[08] <= w_mem08_new;
              w_mem[09] <= w_mem09_new;
              w_mem[10] <= w_mem10_new;
              w_mem[11] <= w_mem11_new;
              w_mem[12] <= w_mem12_new;
              w_mem[13] <= w_mem13_new;
              w_mem[14] <= w_mem14_new;
              w_mem[15] <= w_mem15_new;
            end

          if (w_ctr_we)
            w_ctr_reg <= w_ctr_new;

          if (sha1_w_mem_ctrl_we)
            sha1_w_mem_ctrl_reg <= sha1_w_mem_ctrl_new;
        end
    end








  always @*
    begin : select_w
      if (w_ctr_reg < 16)
        begin
          w_tmp = w_mem[w_ctr_reg[3 : 0]];
        end
      else
        begin
          w_tmp = w_new;
        end
    end








  always @*
    begin : w_mem_update_logic
      reg [31 : 0] w_0;
      reg [31 : 0] w_2;
      reg [31 : 0] w_8;
      reg [31 : 0] w_13;
      reg [31 : 0] w_16;

      w_mem00_new = 32'h0;
      w_mem01_new = 32'h0;
      w_mem02_new = 32'h0;
      w_mem03_new = 32'h0;
      w_mem04_new = 32'h0;
      w_mem05_new = 32'h0;
      w_mem06_new = 32'h0;
      w_mem07_new = 32'h0;
      w_mem08_new = 32'h0;
      w_mem09_new = 32'h0;
      w_mem10_new = 32'h0;
      w_mem11_new = 32'h0;
      w_mem12_new = 32'h0;
      w_mem13_new = 32'h0;
      w_mem14_new = 32'h0;
      w_mem15_new = 32'h0;
      w_mem_we    = 0;

      w_0   = w_mem[0];
      w_2   = w_mem[2];
      w_8   = w_mem[8];
      w_13  = w_mem[13];
      w_16  = w_13 ^ w_8 ^ w_2 ^ w_0;
      w_new = {w_16[30 : 0], w_16[31]};

      if (init)
        begin
          w_mem00_new = block[511 : 480];
          w_mem01_new = block[479 : 448];
          w_mem02_new = block[447 : 416];
          w_mem03_new = block[415 : 384];
          w_mem04_new = block[383 : 352];
          w_mem05_new = block[351 : 320];
          w_mem06_new = block[319 : 288];
          w_mem07_new = block[287 : 256];
          w_mem08_new = block[255 : 224];
          w_mem09_new = block[223 : 192];
          w_mem10_new = block[191 : 160];
          w_mem11_new = block[159 : 128];
          w_mem12_new = block[127 :  96];
          w_mem13_new = block[95  :  64];
          w_mem14_new = block[63  :  32];
          w_mem15_new = block[31  :   0];
          w_mem_we    = 1;
        end

      else if (w_ctr_reg > 15)
        begin
          w_mem00_new = w_mem[01];
          w_mem01_new = w_mem[02];
          w_mem02_new = w_mem[03];
          w_mem03_new = w_mem[04];
          w_mem04_new = w_mem[05];
          w_mem05_new = w_mem[06];
          w_mem06_new = w_mem[07];
          w_mem07_new = w_mem[08];
          w_mem08_new = w_mem[09];
          w_mem09_new = w_mem[10];
          w_mem10_new = w_mem[11];
          w_mem11_new = w_mem[12];
          w_mem12_new = w_mem[13];
          w_mem13_new = w_mem[14];
          w_mem14_new = w_mem[15];
          w_mem15_new = w_new;
          if(next) 
            w_mem_we    = 1;
        end
    end








  always @*
    begin : w_ctr
      w_ctr_new = 7'h0;
      w_ctr_we  = 0;

      if (w_ctr_rst)
        begin
          w_ctr_new = 7'h0;
          w_ctr_we  = 1;
        end

      if (w_ctr_inc)
        begin
          w_ctr_new = w_ctr_reg + 7'h01;
          w_ctr_we  = 1;
        end
    end







  always @*
    begin : sha1_w_mem_fsm
      w_ctr_rst           = 0;
      w_ctr_inc           = 0;
      sha1_w_mem_ctrl_new = CTRL_IDLE;
      sha1_w_mem_ctrl_we  = 0;

      case (sha1_w_mem_ctrl_reg)
        CTRL_IDLE:
          begin
            if (init)
              begin
                w_ctr_rst           = 1;
                sha1_w_mem_ctrl_new = CTRL_UPDATE;
                sha1_w_mem_ctrl_we  = 1;
              end
          end

        CTRL_UPDATE:
          begin
            if (next)
              begin
                w_ctr_inc = 1;
              end

            if (w_ctr_reg == SHA1_ROUNDS)
              begin
                sha1_w_mem_ctrl_new = CTRL_IDLE;
                sha1_w_mem_ctrl_we  = 1;
              end
          end
      endcase
    end
endmodule