data/full_repos/permissive/172705897/verilog/branch_decide.v
data/verilator_xmls/c83662d2-af4c-4dfa-95dc-fc8f88dab5e7.xml
module branch_decision (Branch, Predicted, Branch_Enable, Jump, Mispredict, Decision, Branch_Jump_Trigger);
	input	Branch;
	input	Predicted;
	input	Branch_Enable;
	input	Jump;
	output	Mispredict;
	output	Decision;
	output	Branch_Jump_Trigger;

	assign	Branch_Jump_Trigger	= ((!Predicted) & (Branch & Branch_Enable)) | Jump;
	assign	Decision		= (Branch & Branch_Enable);
	assign	Mispredict		= (Predicted & (!(Branch & Branch_Enable)));
endmodule
module branch_decision (Branch, Predicted, Branch_Enable, Jump, Mispredict, Decision, Branch_Jump_Trigger);

	input	Branch;
	input	Predicted;
	input	Branch_Enable;
	input	Jump;
	output	Mispredict;
	output	Decision;
	output	Branch_Jump_Trigger;

	assign	Branch_Jump_Trigger	= ((!Predicted) & (Branch & Branch_Enable)) | Jump;
	assign	Decision		= (Branch & Branch_Enable);
	assign	Mispredict		= (Predicted & (!(Branch & Branch_Enable)));
endmodule