data/full_repos/permissive/211866113/Accumulator.v
1: b'%Error: data/full_repos/permissive/211866113/Accumulator.v:1: Cannot find include file: RippleCarryAdder.v\n`include "RippleCarryAdder.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/RippleCarryAdder.v\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/RippleCarryAdder.v.v\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/RippleCarryAdder.v.sv\n             RippleCarryAdder.v\n             RippleCarryAdder.v.v\n             RippleCarryAdder.v.sv\n             obj_dir/RippleCarryAdder.v\n             obj_dir/RippleCarryAdder.v.v\n             obj_dir/RippleCarryAdder.v.sv\n%Error: data/full_repos/permissive/211866113/Accumulator.v:2: Cannot find include file: Register.v\n`include "Register.v" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module accumulator (
            input wire clk,
            input wire reset,
		    input wire [2:0] content,
		    output [2:0]     acc
		    );

    wire [2:0] forward;
    reg carry_in;
    wire carry_out;

    initial begin
        carry_in = 1'b0;
    end

    rippe_carry_adder my_adder(content, acc, carry_in, forward, carry_out);
    three_bit_reg my_reg(clk, reset, forward, acc);

    always @ ( posedge clk or posedge reset) begin
        if (reset) begin
            carry_in <= 1'b0;
        end else begin
            carry_in <= carry_out;
        end
    end

endmodule
module accumulator (
            input wire clk,
            input wire reset,
		    input wire [2:0] content,
		    output [2:0]     acc
		    );


    wire [2:0] forward;
    reg carry_in;
    wire carry_out;

    initial begin
        carry_in = 1'b0;
    end

    rippe_carry_adder my_adder(content, acc, carry_in, forward, carry_out);
    three_bit_reg my_reg(clk, reset, forward, acc);

    always @ ( posedge clk or posedge reset) begin
        if (reset) begin
            carry_in <= 1'b0;
        end else begin
            carry_in <= carry_out;
        end
    end

endmodule