data/full_repos/permissive/167274925/ADD.v
data/verilator_xmls/856e70e8-a518-4f75-a23e-ccc46525d4d0.xml
module ADD(A,B,C);
input [31:0]A,B;
output reg [31:0]C;
always@(*)begin 
C<=A+B;
end 
endmodule
module ADD(A,B,C);

input [31:0]A,B;
output reg [31:0]C;
always@(*)begin 
C<=A+B;
end 
endmodule