data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/stream_fifo_1clk.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/stream_fifo_1clk.v:23: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module stream_fifo_1clk (clk, rst, din_valid, din_ready, din_data,
                         dout_valid, dout_ready, dout_data, used);
`include "util.vh"
  parameter                   Width = 8;
  parameter                   Depth = 128;

  input                       clk;
  input                       rst;

  input                       din_valid;
  output                      din_ready;
  input [Width-1:0]           din_data;

  output                      dout_valid;
  input                       dout_ready;
  output [Width-1:0]          dout_data;

  output [clog2(Depth+1)-1:0] used;


  wire full, empty, rd_en, wr_en;

  assign wr_en     = ~full & din_valid;
  assign din_ready = ~full;

  assign rd_en      = ~empty & dout_ready;
  assign dout_valid = ~empty;

  fifo_1clk #(
    .Width (Width),
    .Depth (Depth))
  fifo(
    .clk     (clk),
    .rst     (rst),
    .wr_en   (wr_en),
    .wr_data (din_data),
    .full    (full),
    .rd_en   (rd_en),
    .rd_data (dout_data),
    .empty   (empty),
    .used    (used));

endmodule
module stream_fifo_1clk (clk, rst, din_valid, din_ready, din_data,
                         dout_valid, dout_ready, dout_data, used);

`include "util.vh"
  parameter                   Width = 8;
  parameter                   Depth = 128;

  input                       clk;
  input                       rst;

  input                       din_valid;
  output                      din_ready;
  input [Width-1:0]           din_data;

  output                      dout_valid;
  input                       dout_ready;
  output [Width-1:0]          dout_data;

  output [clog2(Depth+1)-1:0] used;


  wire full, empty, rd_en, wr_en;

  assign wr_en     = ~full & din_valid;
  assign din_ready = ~full;

  assign rd_en      = ~empty & dout_ready;
  assign dout_valid = ~empty;

  fifo_1clk #(
    .Width (Width),
    .Depth (Depth))
  fifo(
    .clk     (clk),
    .rst     (rst),
    .wr_en   (wr_en),
    .wr_data (din_data),
    .full    (full),
    .rd_en   (rd_en),
    .rd_data (dout_data),
    .empty   (empty),
    .used    (used));

endmodule