data/full_repos/permissive/133043770/DACTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/133043770/DACTest.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #5 IN_CLOCK = ~IN_CLOCK;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133043770/DACTest.v:46: Unsupported: Ignoring delay on this delayed statement.\n   #5 IN_SAMPLE_READY = 0;\n   ^\n%Error: data/full_repos/permissive/133043770/DACTest.v:19: Cannot find file containing module: \'DAC\'\n DAC uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/133043770,data/full_repos/permissive/133043770/DAC\n             data/full_repos/permissive/133043770,data/full_repos/permissive/133043770/DAC.v\n             data/full_repos/permissive/133043770,data/full_repos/permissive/133043770/DAC.sv\n             DAC\n             DAC.v\n             DAC.sv\n             obj_dir/DAC\n             obj_dir/DAC.v\n             obj_dir/DAC.sv\n%Warning-WIDTH: data/full_repos/permissive/133043770/DACTest.v:38: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                 : ... In instance DACTest\n  IN_BITS = 4\'b1111;\n          ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DACTest;


	reg IN_CLOCK;
	reg IN_RESET;
	reg [11:0]IN_BITS;
	reg IN_SAMPLE_READY;
	

	wire OUT_SPI_MOSI;
	wire OUT_SPI_SCK;
	wire OUT_DAC_CS;
	wire OUT_DAC_CLR;
	wire [4:0]OUT_STATE;
	wire [31:0]OUT_WRITE_BIT;

	DAC uut (
		.IN_CLOCK(IN_CLOCK),
		.IN_RESET(IN_RESET),
		.IN_BITS(IN_BITS),
		.IN_SAMPLE_READY(IN_SAMPLE_READY),

		.OUT_SPI_SCK(OUT_SPI_SCK),
		.OUT_SPI_MOSI(OUT_SPI_MOSI),
		
		.OUT_DAC_CS(OUT_DAC_CS), 
		.OUT_DAC_CLR(OUT_DAC_CLR),
	
		.OUT_STATE(OUT_STATE),
		.OUT_WRITE_BIT(OUT_WRITE_BIT)
	);

	initial begin
		IN_RESET = 0;
		IN_CLOCK = 0;
		IN_BITS = 4'b1111;
		IN_SAMPLE_READY = 1;
	end
      
	always begin		
		#5 IN_CLOCK = ~IN_CLOCK;
		
		if (IN_SAMPLE_READY == 1) begin
			#5 IN_SAMPLE_READY = 0;
		end
	end
endmodule
module DACTest;



	reg IN_CLOCK;
	reg IN_RESET;
	reg [11:0]IN_BITS;
	reg IN_SAMPLE_READY;
	

	wire OUT_SPI_MOSI;
	wire OUT_SPI_SCK;
	wire OUT_DAC_CS;
	wire OUT_DAC_CLR;
	wire [4:0]OUT_STATE;
	wire [31:0]OUT_WRITE_BIT;

	DAC uut (
		.IN_CLOCK(IN_CLOCK),
		.IN_RESET(IN_RESET),
		.IN_BITS(IN_BITS),
		.IN_SAMPLE_READY(IN_SAMPLE_READY),

		.OUT_SPI_SCK(OUT_SPI_SCK),
		.OUT_SPI_MOSI(OUT_SPI_MOSI),
		
		.OUT_DAC_CS(OUT_DAC_CS), 
		.OUT_DAC_CLR(OUT_DAC_CLR),
	
		.OUT_STATE(OUT_STATE),
		.OUT_WRITE_BIT(OUT_WRITE_BIT)
	);

	initial begin
		IN_RESET = 0;
		IN_CLOCK = 0;
		IN_BITS = 4'b1111;
		IN_SAMPLE_READY = 1;
	end
      
	always begin		
		#5 IN_CLOCK = ~IN_CLOCK;
		
		if (IN_SAMPLE_READY == 1) begin
			#5 IN_SAMPLE_READY = 0;
		end
	end
endmodule