data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v
 line:101: before: "@"
1: b'%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:91: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("SBox_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:92: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_ch_lt_s, r_ch_rt_n, w_ch_up_n, w_ch_dn_s, w_ch_lt_n, w_ch_rt_s);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:101: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:105: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:109: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:112: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:115: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:118: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:121: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:124: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:127: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:130: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:134: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:141: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:150: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:159: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:168: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:177: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:185: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:189: syntax error, unexpected \'@\'\n  #50@(posedge r_clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n  #50@(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:193: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:200: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:209: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:218: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:218: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:227: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:236: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:242: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n  #50 r_clk <= ~r_clk;\n  ^\n%Error: Exiting due to 27 error(s), 26 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SBox_tb;

	reg r_clk;
	reg r_mode;
	reg [8:0] r_c_bus;
	reg r_c_dimension;
	reg [1:0] r_ch_up_s;
	reg [1:0] r_ch_dn_n;
	reg [1:0] r_ch_lt_s;
	reg [1:0] r_ch_rt_n;
	wire [1:0] w_ch_up_n;
	wire [1:0] w_ch_dn_s;
	wire [1:0] w_ch_lt_n;
	wire [1:0] w_ch_rt_s;

	SBox#(0, 2, 2, 2, 16, 1, 2) inst(
		.mode(r_mode),
		.c_clk(r_clk),
		.c_bus(r_c_bus),
		.c_dimension(r_c_dimension),

		.ch_up_n(w_ch_up_n),
		.ch_up_s(r_ch_up_s),
		.ch_dn_n(r_ch_dn_n),
		.ch_dn_s(w_ch_dn_s),

		.ch_lt_n(w_ch_lt_n),
		.ch_lt_s(r_ch_lt_s),
		.ch_rt_n(r_ch_rt_n),
		.ch_rt_s(w_ch_rt_s)
	);

































	initial begin
		$dumpfile("SBox_tb.vcd");
		$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_ch_lt_s, r_ch_rt_n, w_ch_up_n, w_ch_dn_s, w_ch_lt_n, w_ch_rt_s);
		r_clk <= 'b1;
		r_mode <= 'b0;
		r_c_bus <= 'h0;
		r_c_dimension <= 'b0;
		r_ch_up_s <= 'h3;
		r_ch_dn_n <= 'h3;
		r_ch_lt_s <= 'h3;
		r_ch_rt_n <= 'h3;
		#100 @(posedge r_clk);


		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_bus <= {3'h0, 6'b100110};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h1, 6'b100101};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h2, 6'b100101};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h3, 6'b100001};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h4, 6'b100110};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h5, 6'b100011};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h6, 6'b100010};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h7, 6'b100010};
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_ch_dn_n <= 'h0;
		r_ch_rt_n <= 'h0;
		r_ch_up_s <= 'h0;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h2;
		r_ch_rt_n <= 'h1;
		r_ch_up_s <= 'h0;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h2;
		r_ch_rt_n <= 'h3;
		r_ch_up_s <= 'h0;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h2;
		r_ch_rt_n <= 'h3;
		r_ch_up_s <= 'h2;
		r_ch_lt_s <= 'h3;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h1;
		r_ch_rt_n <= 'h0;
		r_ch_up_s <= 'h1;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);






		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h1;
		#50@(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_ch_dn_n <= 'h0;
		r_ch_rt_n <= 'h0;
		r_ch_up_s <= 'h0;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h2;
		r_ch_rt_n <= 'h1;
		r_ch_up_s <= 'h0;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h2;
		r_ch_rt_n <= 'h3;
		r_ch_up_s <= 'h0;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h2;
		r_ch_rt_n <= 'h3;
		r_ch_up_s <= 'h2;
		r_ch_lt_s <= 'h3;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h1;
		r_ch_rt_n <= 'h0;
		r_ch_up_s <= 'h1;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);





		#50 @(posedge r_clk);

		$finish;
	end

	always begin
		#50 r_clk <= ~r_clk;
	end

endmodule
module SBox_tb;


	reg r_clk;
	reg r_mode;
	reg [8:0] r_c_bus;
	reg r_c_dimension;
	reg [1:0] r_ch_up_s;
	reg [1:0] r_ch_dn_n;
	reg [1:0] r_ch_lt_s;
	reg [1:0] r_ch_rt_n;
	wire [1:0] w_ch_up_n;
	wire [1:0] w_ch_dn_s;
	wire [1:0] w_ch_lt_n;
	wire [1:0] w_ch_rt_s;

	SBox#(0, 2, 2, 2, 16, 1, 2) inst(
		.mode(r_mode),
		.c_clk(r_clk),
		.c_bus(r_c_bus),
		.c_dimension(r_c_dimension),

		.ch_up_n(w_ch_up_n),
		.ch_up_s(r_ch_up_s),
		.ch_dn_n(r_ch_dn_n),
		.ch_dn_s(w_ch_dn_s),

		.ch_lt_n(w_ch_lt_n),
		.ch_lt_s(r_ch_lt_s),
		.ch_rt_n(r_ch_rt_n),
		.ch_rt_s(w_ch_rt_s)
	);

































	initial begin
		$dumpfile("SBox_tb.vcd");
		$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_ch_lt_s, r_ch_rt_n, w_ch_up_n, w_ch_dn_s, w_ch_lt_n, w_ch_rt_s);
		r_clk <= 'b1;
		r_mode <= 'b0;
		r_c_bus <= 'h0;
		r_c_dimension <= 'b0;
		r_ch_up_s <= 'h3;
		r_ch_dn_n <= 'h3;
		r_ch_lt_s <= 'h3;
		r_ch_rt_n <= 'h3;
		#100 @(posedge r_clk);


		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_bus <= {3'h0, 6'b100110};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h1, 6'b100101};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h2, 6'b100101};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h3, 6'b100001};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h4, 6'b100110};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h5, 6'b100011};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h6, 6'b100010};
		#50 @(posedge r_clk);

		r_c_bus <= {3'h7, 6'b100010};
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_ch_dn_n <= 'h0;
		r_ch_rt_n <= 'h0;
		r_ch_up_s <= 'h0;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h2;
		r_ch_rt_n <= 'h1;
		r_ch_up_s <= 'h0;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h2;
		r_ch_rt_n <= 'h3;
		r_ch_up_s <= 'h0;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h2;
		r_ch_rt_n <= 'h3;
		r_ch_up_s <= 'h2;
		r_ch_lt_s <= 'h3;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h1;
		r_ch_rt_n <= 'h0;
		r_ch_up_s <= 'h1;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);






		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h1;
		#50@(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_ch_dn_n <= 'h0;
		r_ch_rt_n <= 'h0;
		r_ch_up_s <= 'h0;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h2;
		r_ch_rt_n <= 'h1;
		r_ch_up_s <= 'h0;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h2;
		r_ch_rt_n <= 'h3;
		r_ch_up_s <= 'h0;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h2;
		r_ch_rt_n <= 'h3;
		r_ch_up_s <= 'h2;
		r_ch_lt_s <= 'h3;
		#50 @(posedge r_clk);




		r_ch_dn_n <= 'h1;
		r_ch_rt_n <= 'h0;
		r_ch_up_s <= 'h1;
		r_ch_lt_s <= 'h0;
		#50 @(posedge r_clk);





		#50 @(posedge r_clk);

		$finish;
	end

	always begin
		#50 r_clk <= ~r_clk;
	end

endmodule