data/full_repos/permissive/143278/ivltests/test_work14.v
 line:2: before: ":"
1: b'%Error: data/full_repos/permissive/143278/ivltests/test_work14.v:2: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport work14_pkg::*;\n       ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_work14.v:9: Unsupported: Ignoring delay on this delayed statement.\ninitial begin : clkgen forever #10 clk = ~clk; end\n                               ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/test_work14.v:16: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_work14.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/143278/ivltests/test_work14.v:19: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_work14.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_work14.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module test14;
import work14_pkg::*;
bit clk = 0;

parameter longint maxvalue = 2**29 + 17;
logic [29:0] mvalue;
logic [29:0] lvalue;

initial begin : clkgen forever #10 clk = ~clk; end

assign lvalue = maxvalue;

work14_comp #(.max_out_val(maxvalue)) duv (.clk_i(clk), .val(mvalue));

initial begin
  @(posedge clk);
  #1;
  if (lvalue !== mvalue) $display ("ERROR due to mismatch between lvalue=%d and mvalue=%d", lvalue, mvalue);
  @(posedge clk);
  #1;
  if (lvalue !== mvalue) $display ("ERROR due to mismatch between lvalue=%d and mvalue=%d", lvalue, mvalue);
  #5;
  $display ("PASSED");
  $finish;
end


endmodule
module test14;

import work14_pkg::*;
bit clk = 0;

parameter longint maxvalue = 2**29 + 17;
logic [29:0] mvalue;
logic [29:0] lvalue;

initial begin : clkgen forever #10 clk = ~clk; end

assign lvalue = maxvalue;

work14_comp #(.max_out_val(maxvalue)) duv (.clk_i(clk), .val(mvalue));

initial begin
  @(posedge clk);
  #1;
  if (lvalue !== mvalue) $display ("ERROR due to mismatch between lvalue=%d and mvalue=%d", lvalue, mvalue);
  @(posedge clk);
  #1;
  if (lvalue !== mvalue) $display ("ERROR due to mismatch between lvalue=%d and mvalue=%d", lvalue, mvalue);
  #5;
  $display ("PASSED");
  $finish;
end


endmodule