data/full_repos/permissive/146246005/ALU/ALU.sv
Syntax Error
1: b'%Warning-WIDTH: data/full_repos/permissive/146246005/ALU/ALU.sv:109: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                   : ... In instance ALU\n      default: temp = 1\'bx;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-UNSIGNED: data/full_repos/permissive/146246005/ALU/ALU.sv:48: Comparison is constant due to unsigned arithmetic\n                                                                     : ... In instance ALU\n        if(A>0 && B>0 && temp<0) OF=1;\n                             ^\n%Warning-UNSIGNED: data/full_repos/permissive/146246005/ALU/ALU.sv:49: Comparison is constant due to unsigned arithmetic\n                                                                     : ... In instance ALU\n        else if (A<0 && B<0 && temp>0) OF=1;\n                  ^\n%Warning-UNSIGNED: data/full_repos/permissive/146246005/ALU/ALU.sv:65: Comparison is constant due to unsigned arithmetic\n                                                                     : ... In instance ALU\n        if(A>0 && B>0 && temp<0) OF=1;\n                             ^\n%Warning-UNSIGNED: data/full_repos/permissive/146246005/ALU/ALU.sv:66: Comparison is constant due to unsigned arithmetic\n                                                                     : ... In instance ALU\n        else if (A<0 && B<0 && temp>0) OF=1;\n                  ^\n%Error: Exiting due to 5 warning(s)\n'
module ALU(CLK, EN, OE, OPCODE, A, B, ALU_OUT, CF, OF, SF, ZF);
  parameter WIDTH = 8;
  output reg [ WIDTH-1 : 0] ALU_OUT;
  output reg CF, OF, SF, ZF;
  input [3:0] OPCODE;
  input [ WIDTH-1 : 0] A, B;
  input reg CLK, EN, OE;
  reg [ WIDTH-1 : 0] temp;
  localparam ADDalu = 4'b0010,
             SUBalu = 4'b0011,
             ANDalu = 4'b0100,
             ORalu  = 4'b0101,
             XORalu = 4'b0110,
             NOTalu = 4'b0111;

always @(OE, temp) ALU_OUT = (OE) ? temp : 8'bz;
always @(posedge CLK) begin
  
  if(EN) begin
    case (OPCODE)
      
      ADDalu: begin
       temp = A + B;

        if (A+B> 2**WIDTH -1) CF=1;
        else CF=0;

        if (temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;

        if(A>0 && B>0 && temp<0) OF=1;
        else if (A<0 && B<0 && temp>0) OF=1;
        else OF=0;
      end
      
      SUBalu: begin
       temp = A - B;

        if (A<B) CF=1;
        else CF=0;

        if (temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;

        if(A>0 && B>0 && temp<0) OF=1;
        else if (A<0 && B<0 && temp>0) OF=1;
        else OF=0;
      end
      
      ANDalu: begin
       temp = A&B;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      
      ORalu: begin
       temp = A|B;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      
      XORalu: begin
       temp = A^B;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      
      NOTalu: begin
       temp = ~A;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      default: temp = 1'bx;
    endcase
  end
 
end

endmodule
module ALU(CLK, EN, OE, OPCODE, A, B, ALU_OUT, CF, OF, SF, ZF);

  parameter WIDTH = 8;
  output reg [ WIDTH-1 : 0] ALU_OUT;
  output reg CF, OF, SF, ZF;
  input [3:0] OPCODE;
  input [ WIDTH-1 : 0] A, B;
  input reg CLK, EN, OE;
  reg [ WIDTH-1 : 0] temp;
  localparam ADDalu = 4'b0010,
             SUBalu = 4'b0011,
             ANDalu = 4'b0100,
             ORalu  = 4'b0101,
             XORalu = 4'b0110,
             NOTalu = 4'b0111;

always @(OE, temp) ALU_OUT = (OE) ? temp : 8'bz;
always @(posedge CLK) begin
  
  if(EN) begin
    case (OPCODE)
      
      ADDalu: begin
       temp = A + B;

        if (A+B> 2**WIDTH -1) CF=1;
        else CF=0;

        if (temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;

        if(A>0 && B>0 && temp<0) OF=1;
        else if (A<0 && B<0 && temp>0) OF=1;
        else OF=0;
      end
      
      SUBalu: begin
       temp = A - B;

        if (A<B) CF=1;
        else CF=0;

        if (temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;

        if(A>0 && B>0 && temp<0) OF=1;
        else if (A<0 && B<0 && temp>0) OF=1;
        else OF=0;
      end
      
      ANDalu: begin
       temp = A&B;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      
      ORalu: begin
       temp = A|B;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      
      XORalu: begin
       temp = A^B;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      
      NOTalu: begin
       temp = ~A;

        if(temp[WIDTH-1]==1) SF=1;
        else SF=0;

        if(temp==0) ZF=1;
        else ZF=0;
      end
      default: temp = 1'bx;
    endcase
  end
 
end

endmodule