data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp
 line:229: before: "parameter"
1: b"%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:228: Define or directive not defined: '`mname'\nmodule   `mname`  #(\n         ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:228: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule   `mname`  #(\n               ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:230: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:256: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [3:0]                 res_p_out\n  ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:257: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:276: syntax error, unexpected assign\nassign nc_mult_res = mult_res;\n^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:282: syntax error, unexpected always_ff\nalways_ff @(posedge clk or negedge rst_n) begin\n^~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:291: syntax error, unexpected assign\nassign       nc_op_code = op_code;\n^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:297: syntax error, unexpected $undefined\n`$inp_l->mname()` #(.DataWidth(DataWidth)) `$inp_l->iname()`\n^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:297: Unsupported or unknown PLI call: $inp_l\n`$inp_l->mname()` #(.DataWidth(DataWidth)) `$inp_l->iname()`\n ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:297: Unsupported or unknown PLI call: $inp_l\n`$inp_l->mname()` #(.DataWidth(DataWidth)) `$inp_l->iname()`\n                                            ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:309: Unsupported or unknown PLI call: $inp_h\n`$inp_h->mname()` #(.DataWidth(DataWidth)) `$inp_h->iname()`\n ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:309: Unsupported or unknown PLI call: $inp_h\n`$inp_h->mname()` #(.DataWidth(DataWidth)) `$inp_h->iname()`\n                                            ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:330: syntax error, unexpected assign\nassign en_mult32    = (op_code[8:7] == 2'b00);\n^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:374: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\nlogic [1:0][`$use_add -1`:0] carry_chain;\n            ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:374: Unsupported or unknown PLI call: $use_add\nlogic [1:0][`$use_add -1`:0] carry_chain;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:383: syntax error, unexpected assign\nassign nc_div_lsb_msb[0] = div_lsb[0][DataWidth-1];\n^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:403: Unsupported or unknown PLI call: $PE\n`$PE->mname()` #(.DataWidth(DataWidth)) `$PE->iname()`\n ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:403: Unsupported or unknown PLI call: $PE\n`$PE->mname()` #(.DataWidth(DataWidth)) `$PE->iname()`\n                                         ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:412: Unsupported or unknown PLI call: $i\n  .clk_en    (clk_en[`$i`]),\n                      ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:416: Number is missing value digits: 3'h\n  .cfg_en    (cfg_en & (cfg_a[10:8]==3'h`$i`)),  \n                                     ^~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:416: Unsupported or unknown PLI call: $i\n  .cfg_en    (cfg_en & (cfg_a[10:8]==3'h`$i`)),  \n                                         ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:418: Unsupported or unknown PLI call: $i\n  .data0   (pe_a_in[`$i`]),\n                     ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:420: Unsupported or unknown PLI call: $i\n  .op_a_shift (pe_a_in[`$i+1`]),\n                        ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:422: Unsupported or unknown PLI call: $i\n  .op_a_shift (pe_a_in[`$i-1`]),\n                        ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:424: Unsupported or unknown PLI call: $i\n  .data1   (pe_b_in[`$i`]),\n                     ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:426: Unsupported or unknown PLI call: $i\n  .data2   (pe_c_in[`$i`]),\n                     ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:430: Unsupported or unknown PLI call: $i\n  .res_p_msb   (res_p[`$i+1`]),\n                       ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:431: Unsupported or unknown PLI call: $chain_i\n  .carry_out   (carry_chain[`$chain_i`]),\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:432: Unsupported or unknown PLI call: $chain_i\n  .cmpr_eq_out (cmpr_eq_chain[`$chain_i`]),\n                               ^~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:434: Unsupported or unknown PLI call: $chain_i\n  .carry_in   (carry_chain[`$chain_i`]),\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:435: Unsupported or unknown PLI call: $chain_i\n  .cmpr_eq_in (cmpr_eq_chain[`$chain_i`]),\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:442: Unsupported or unknown PLI call: $chain_i\n  .div_oper    (div_oper_msb[`$chain_i`]),\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:445: Unsupported or unknown PLI call: $i\n  .res_p_msb   (res_p[`$i+1`]),\n                       ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:448: Unsupported or unknown PLI call: $chain_i\n  .div_oper  (div_oper_lsb[`$chain_i`]),\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:449: Unsupported or unknown PLI call: $chain_i\n  .div_co    (div_lsb[`$chain_i`]),\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:455: Unsupported or unknown PLI call: $i\n  .bit0 (op_d_p[`$i`]),\n                 ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:456: Unsupported or unknown PLI call: $i\n  .bit1 (op_e_p[`$i`]),\n                 ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:457: Unsupported or unknown PLI call: $i\n  .bit2 (op_f_p[`$i`]),\n                 ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:459: Unsupported or unknown PLI call: $i\n  .res       (pe_res[`$i`]),\n                      ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:461: Unsupported or unknown PLI call: $i\n  .mult_res  (mult_res[`$i`]),\n                        ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:463: Unsupported or unknown PLI call: $i\n  .res_p     (res_p[`$i`])\n                     ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:474: syntax error, unexpected genvar\ngenvar g_i;\n^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:501: Unsupported or unknown PLI call: $dut_red\n`$dut_red->mname()` #(.DataWidth(2*DataWidth)) `$dut_red->iname()`\n ^~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/pe_new/clust/rtl/test_clust.svp:501: Unsupported or unknown PLI call: $dut_red\n`$dut_red->mname()` #(.DataWidth(2*DataWidth)) `$dut_red->iname()`\n                                                ^~~~~~~~\n%Error: Exiting due to 45 error(s)\n"
module   `mname`  #(
  parameter DataWidth = 16
) (
  input                         clk,
  input                         rst_n,
  input         [3:0]           clk_en,

  input         [31:0]          cfg_d,
  input         [10:0]          cfg_a,
  input                         cfg_en,


  input  [3:0][DataWidth-1:0]   op_a,
  input  [3:0][DataWidth-1:0]   op_b,

  input  [3:0][DataWidth-1:0]   op_c,


  input  [2*DataWidth-1:0]        reduce_extra_inp_in,



  input  [3:0]                  op_d_p,
  input  [3:0]                  op_e_p,
  input  [3:0]                  op_f_p,


  output logic [3:0][DataWidth-1:0]  res_out  ,
  output logic [3:0]                 res_p_out
);

logic [3:0][DataWidth-1:0]  res  ;
logic [3:0]                 res_p;

logic [3:0][DataWidth-1:0]        pe_a_in;
logic [3:0][DataWidth-1:0]        pe_b_in;

logic [3:0][DataWidth-1:0]        pe_c_in;



logic [3:0][DataWidth-1:0]  pe_res;

logic [3:0][2*DataWidth-1:0] mult_res;



logic [3:0][2*DataWidth-1:0] nc_mult_res;
assign nc_mult_res = mult_res;


logic en_chain_inp;

logic [15:0] op_code;
always_ff @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    op_code <= 'h0;
  end else if(cfg_en && (&cfg_a)) begin
    op_code <= cfg_d[15:0];
  end
end

logic [15:0] nc_op_code;
assign       nc_op_code = op_code;


  logic [2*DataWidth-1:0]  reduce_extra_inp;


`$inp_l->mname()` #(.DataWidth(DataWidth)) `$inp_l->iname()`
(
  .clk        (clk),
  .clk_en     (clk_en[0]),
  .rst_n      (rst_n),
  .load       (cfg_en && (cfg_a == 8'hF0)),
  .val        (cfg_d[DataWidth-1:0]),
  .mode       (op_code[15:14]),
  .data_in    (reduce_extra_inp_in[DataWidth-1:0]),
  .res        (reduce_extra_inp[DataWidth-1:0])
);

`$inp_h->mname()` #(.DataWidth(DataWidth)) `$inp_h->iname()`
(
  .clk        (clk),
  .clk_en     (clk_en[0]),
  .rst_n      (rst_n),
  .load       (cfg_en && (cfg_a == 8'hF1)),
  .val        (cfg_d[DataWidth-1:0]),
  .mode       (op_code[15:14]),
  .data_in    (reduce_extra_inp_in[2*DataWidth-1:DataWidth]),
  .res        (reduce_extra_inp[2*DataWidth-1:DataWidth])
);



assign en_chain_inp = (op_code[8:7] == 2'b11);


logic reduce_en;
logic en_mult32;


assign en_mult32    = (op_code[8:7] == 2'b00);


assign reduce_en = |op_code[6:0];


always_comb begin
  pe_a_in = op_a;
  pe_b_in = op_b;

  pe_c_in = op_c;


  if (en_mult32) begin
    pe_a_in[1] = pe_a_in[0];
    pe_b_in[2] = pe_b_in[0];
    pe_a_in[3] = pe_a_in[2];
    pe_b_in[3] = pe_b_in[1];
  end else if (en_chain_inp) begin
    pe_b_in[1] = pe_res[0];
    pe_b_in[3] = pe_res[2];
  end
end





always_comb begin
  pe_a_in = op_a;
  pe_b_in = op_b;

  pe_c_in = op_c;


  if (en_chain_inp) begin
    pe_b_in[1] = pe_res[0];
    pe_b_in[3] = pe_res[2];
  end
end




logic [1:0][`$use_add -1`:0] carry_chain;
logic [1:0]      cmpr_eq_chain;


logic [1:0][DataWidth-1:0] div_lsb;
logic [1:0]                nc_div_lsb_msb;
logic [1:0][DataWidth-1:0] div_oper_msb;
logic [1:0][DataWidth-1:0] div_oper_lsb;

assign nc_div_lsb_msb[0] = div_lsb[0][DataWidth-1];
assign nc_div_lsb_msb[1] = div_lsb[1][DataWidth-1];

assign div_oper_lsb[0] =  {pe_a_in[1][DataWidth-2:0], pe_a_in[0][DataWidth-1]};
assign div_oper_msb[0] =  {div_lsb[0][DataWidth-2:0], pe_a_in[0][DataWidth-2]};

assign div_oper_lsb[1] =  {pe_a_in[3][DataWidth-2:0], pe_a_in[2][DataWidth-1]};
assign div_oper_msb[1] =  {div_lsb[1][DataWidth-2:0], pe_a_in[2][DataWidth-2]};












`$PE->mname()` #(.DataWidth(DataWidth)) `$PE->iname()`
(





  .clk       (clk),
  .rst_n     (rst_n),
  .clk_en    (clk_en[`$i`]),

  .cfg_d     (cfg_d),
  .cfg_a     (cfg_a[7:0]),
  .cfg_en    (cfg_en & (cfg_a[10:8]==3'h`$i`)),

  .data0   (pe_a_in[`$i`]),

  .op_a_shift (pe_a_in[`$i+1`]),

  .op_a_shift (pe_a_in[`$i-1`]),

  .data1   (pe_b_in[`$i`]),

  .data2   (pe_c_in[`$i`]),



  .res_p_msb   (res_p[`$i+1`]),
  .carry_out   (carry_chain[`$chain_i`]),
  .cmpr_eq_out (cmpr_eq_chain[`$chain_i`]),

  .carry_in   (carry_chain[`$chain_i`]),
  .cmpr_eq_in (cmpr_eq_chain[`$chain_i`]),






  .div_oper    (div_oper_msb[`$chain_i`]),


  .res_p_msb   (res_p[`$i+1`]),


  .div_oper  (div_oper_lsb[`$chain_i`]),
  .div_co    (div_lsb[`$chain_i`]),





  .bit0 (op_d_p[`$i`]),
  .bit1 (op_e_p[`$i`]),
  .bit2 (op_f_p[`$i`]),

  .res       (pe_res[`$i`]),

  .mult_res  (mult_res[`$i`]),

  .res_p     (res_p[`$i`])
);







logic [4*DataWidth - 1:0] reduce_res;
logic [2*DataWidth - 1:0] reduce_inp [3:0];
genvar g_i;
generate
  for (g_i = 0; g_i < 4; g_i = g_i + 1) begin : GEN_RED_IN

    always_ff @(posedge clk or negedge rst_n) begin
      if(~rst_n) begin
        reduce_inp[g_i] <= 'h0;
      end else begin

        reduce_inp[g_i] <= en_mult32 ? mult_res[g_i] : { {DataWidth{1'b0}},pe_res[g_i]};

        reduce_inp[g_i] <= { {DataWidth{1'b0}},pe_res[g_i]};

      end
    end

      assign reduce_inp[g_i] = en_mult32 ? mult_res[g_i] : { {DataWidth{1'b0}},pe_res[g_i]};

      assign reduce_inp[g_i] = { {DataWidth{1'b0}},pe_res[g_i]};

  end
endgenerate





`$dut_red->mname()` #(.DataWidth(2*DataWidth)) `$dut_red->iname()`
(

  .clk       (clk),
  .rst_n     (rst_n),

  .op_code (op_code[6:0]),

  .op_a (reduce_inp[0]),
  .op_b (reduce_inp[1]),
  .op_c (reduce_inp[2]),
  .op_d (reduce_inp[3]),

  .op_e (reduce_extra_inp),


  .res  (reduce_res)
);



assign res[0] = reduce_en ? reduce_res[3*DataWidth-1:2*DataWidth] : pe_res[0];
assign res[2] = reduce_en ? reduce_res[4*DataWidth-1:3*DataWidth] : pe_res[2];

assign res[1] = reduce_en ? reduce_res[DataWidth-1:0] : pe_res[1];
assign res[3] = reduce_en ? reduce_res[2*DataWidth-1:DataWidth] : pe_res[3];


assign res = pe_res;



  assign res_p_out = res_p;
  assign res_out   = res;


endmodule
module   `mname`  #(
  parameter DataWidth = 16
) (
  input                         clk,
  input                         rst_n,
  input         [3:0]           clk_en,

  input         [31:0]          cfg_d,
  input         [10:0]          cfg_a,
  input                         cfg_en,


  input  [3:0][DataWidth-1:0]   op_a,
  input  [3:0][DataWidth-1:0]   op_b,

  input  [3:0][DataWidth-1:0]   op_c,


  input  [2*DataWidth-1:0]        reduce_extra_inp_in,



  input  [3:0]                  op_d_p,
  input  [3:0]                  op_e_p,
  input  [3:0]                  op_f_p,


  output logic [3:0][DataWidth-1:0]  res_out  ,
  output logic [3:0]                 res_p_out
);


logic [3:0][DataWidth-1:0]  res  ;
logic [3:0]                 res_p;

logic [3:0][DataWidth-1:0]        pe_a_in;
logic [3:0][DataWidth-1:0]        pe_b_in;

logic [3:0][DataWidth-1:0]        pe_c_in;



logic [3:0][DataWidth-1:0]  pe_res;

logic [3:0][2*DataWidth-1:0] mult_res;



logic [3:0][2*DataWidth-1:0] nc_mult_res;
assign nc_mult_res = mult_res;


logic en_chain_inp;

logic [15:0] op_code;
always_ff @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    op_code <= 'h0;
  end else if(cfg_en && (&cfg_a)) begin
    op_code <= cfg_d[15:0];
  end
end

logic [15:0] nc_op_code;
assign       nc_op_code = op_code;


  logic [2*DataWidth-1:0]  reduce_extra_inp;


`$inp_l->mname()` #(.DataWidth(DataWidth)) `$inp_l->iname()`
(
  .clk        (clk),
  .clk_en     (clk_en[0]),
  .rst_n      (rst_n),
  .load       (cfg_en && (cfg_a == 8'hF0)),
  .val        (cfg_d[DataWidth-1:0]),
  .mode       (op_code[15:14]),
  .data_in    (reduce_extra_inp_in[DataWidth-1:0]),
  .res        (reduce_extra_inp[DataWidth-1:0])
);

`$inp_h->mname()` #(.DataWidth(DataWidth)) `$inp_h->iname()`
(
  .clk        (clk),
  .clk_en     (clk_en[0]),
  .rst_n      (rst_n),
  .load       (cfg_en && (cfg_a == 8'hF1)),
  .val        (cfg_d[DataWidth-1:0]),
  .mode       (op_code[15:14]),
  .data_in    (reduce_extra_inp_in[2*DataWidth-1:DataWidth]),
  .res        (reduce_extra_inp[2*DataWidth-1:DataWidth])
);



assign en_chain_inp = (op_code[8:7] == 2'b11);


logic reduce_en;
logic en_mult32;


assign en_mult32    = (op_code[8:7] == 2'b00);


assign reduce_en = |op_code[6:0];


always_comb begin
  pe_a_in = op_a;
  pe_b_in = op_b;

  pe_c_in = op_c;


  if (en_mult32) begin
    pe_a_in[1] = pe_a_in[0];
    pe_b_in[2] = pe_b_in[0];
    pe_a_in[3] = pe_a_in[2];
    pe_b_in[3] = pe_b_in[1];
  end else if (en_chain_inp) begin
    pe_b_in[1] = pe_res[0];
    pe_b_in[3] = pe_res[2];
  end
end





always_comb begin
  pe_a_in = op_a;
  pe_b_in = op_b;

  pe_c_in = op_c;


  if (en_chain_inp) begin
    pe_b_in[1] = pe_res[0];
    pe_b_in[3] = pe_res[2];
  end
end




logic [1:0][`$use_add -1`:0] carry_chain;
logic [1:0]      cmpr_eq_chain;


logic [1:0][DataWidth-1:0] div_lsb;
logic [1:0]                nc_div_lsb_msb;
logic [1:0][DataWidth-1:0] div_oper_msb;
logic [1:0][DataWidth-1:0] div_oper_lsb;

assign nc_div_lsb_msb[0] = div_lsb[0][DataWidth-1];
assign nc_div_lsb_msb[1] = div_lsb[1][DataWidth-1];

assign div_oper_lsb[0] =  {pe_a_in[1][DataWidth-2:0], pe_a_in[0][DataWidth-1]};
assign div_oper_msb[0] =  {div_lsb[0][DataWidth-2:0], pe_a_in[0][DataWidth-2]};

assign div_oper_lsb[1] =  {pe_a_in[3][DataWidth-2:0], pe_a_in[2][DataWidth-1]};
assign div_oper_msb[1] =  {div_lsb[1][DataWidth-2:0], pe_a_in[2][DataWidth-2]};












`$PE->mname()` #(.DataWidth(DataWidth)) `$PE->iname()`
(





  .clk       (clk),
  .rst_n     (rst_n),
  .clk_en    (clk_en[`$i`]),

  .cfg_d     (cfg_d),
  .cfg_a     (cfg_a[7:0]),
  .cfg_en    (cfg_en & (cfg_a[10:8]==3'h`$i`)),

  .data0   (pe_a_in[`$i`]),

  .op_a_shift (pe_a_in[`$i+1`]),

  .op_a_shift (pe_a_in[`$i-1`]),

  .data1   (pe_b_in[`$i`]),

  .data2   (pe_c_in[`$i`]),



  .res_p_msb   (res_p[`$i+1`]),
  .carry_out   (carry_chain[`$chain_i`]),
  .cmpr_eq_out (cmpr_eq_chain[`$chain_i`]),

  .carry_in   (carry_chain[`$chain_i`]),
  .cmpr_eq_in (cmpr_eq_chain[`$chain_i`]),






  .div_oper    (div_oper_msb[`$chain_i`]),


  .res_p_msb   (res_p[`$i+1`]),


  .div_oper  (div_oper_lsb[`$chain_i`]),
  .div_co    (div_lsb[`$chain_i`]),





  .bit0 (op_d_p[`$i`]),
  .bit1 (op_e_p[`$i`]),
  .bit2 (op_f_p[`$i`]),

  .res       (pe_res[`$i`]),

  .mult_res  (mult_res[`$i`]),

  .res_p     (res_p[`$i`])
);







logic [4*DataWidth - 1:0] reduce_res;
logic [2*DataWidth - 1:0] reduce_inp [3:0];
genvar g_i;
generate
  for (g_i = 0; g_i < 4; g_i = g_i + 1) begin : GEN_RED_IN

    always_ff @(posedge clk or negedge rst_n) begin
      if(~rst_n) begin
        reduce_inp[g_i] <= 'h0;
      end else begin

        reduce_inp[g_i] <= en_mult32 ? mult_res[g_i] : { {DataWidth{1'b0}},pe_res[g_i]};

        reduce_inp[g_i] <= { {DataWidth{1'b0}},pe_res[g_i]};

      end
    end

      assign reduce_inp[g_i] = en_mult32 ? mult_res[g_i] : { {DataWidth{1'b0}},pe_res[g_i]};

      assign reduce_inp[g_i] = { {DataWidth{1'b0}},pe_res[g_i]};

  end
endgenerate





`$dut_red->mname()` #(.DataWidth(2*DataWidth)) `$dut_red->iname()`
(

  .clk       (clk),
  .rst_n     (rst_n),

  .op_code (op_code[6:0]),

  .op_a (reduce_inp[0]),
  .op_b (reduce_inp[1]),
  .op_c (reduce_inp[2]),
  .op_d (reduce_inp[3]),

  .op_e (reduce_extra_inp),


  .res  (reduce_res)
);



assign res[0] = reduce_en ? reduce_res[3*DataWidth-1:2*DataWidth] : pe_res[0];
assign res[2] = reduce_en ? reduce_res[4*DataWidth-1:3*DataWidth] : pe_res[2];

assign res[1] = reduce_en ? reduce_res[DataWidth-1:0] : pe_res[1];
assign res[3] = reduce_en ? reduce_res[2*DataWidth-1:DataWidth] : pe_res[3];


assign res = pe_res;



  assign res_p_out = res_p;
  assign res_out   = res;


endmodule