data/full_repos/permissive/123339956/Homework_Assignment_3/priority_encoder42.v
 line:14: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/123339956/Homework_Assignment_3/priority_encoder42.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #0 I0 = 1\'b1; I1 = 1\'b0; I2 = 1\'b0; I3 = 1\'b0;  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Homework_Assignment_3/priority_encoder42.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #10 I1 = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Homework_Assignment_3/priority_encoder42.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #20 I3 = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Homework_Assignment_3/priority_encoder42.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #20 I3 = 1\'b0; I2 = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Homework_Assignment_3/priority_encoder42.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #100 $finish;\n  ^\n%Error: data/full_repos/permissive/123339956/Homework_Assignment_3/priority_encoder42.v:18: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("priority_encoder42.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/123339956/Homework_Assignment_3/priority_encoder42.v:19: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_priority_encoder42();
	
	wire [1:0] Y;
	wire V;
	reg I0, I1, I2, I3;

	priority_encoder42 uut (Y, V, I0, I1, I2, I3);

	initial begin
		#0 I0 = 1'b1; I1 = 1'b0; I2 = 1'b0; I3 = 1'b0;  
		#10 I1 = 1'b1;
		#20 I3 = 1'b1;
		#20 I3 = 1'b0; I2 = 1'b1;
		#100 $finish;
	end

	initial begin
		$dumpfile("priority_encoder42.vcd");
		$dumpvars;
	end
endmodule
module tb_priority_encoder42();

	
	wire [1:0] Y;
	wire V;
	reg I0, I1, I2, I3;

	priority_encoder42 uut (Y, V, I0, I1, I2, I3);

	initial begin
		#0 I0 = 1'b1; I1 = 1'b0; I2 = 1'b0; I3 = 1'b0;  
		#10 I1 = 1'b1;
		#20 I3 = 1'b1;
		#20 I3 = 1'b0; I2 = 1'b1;
		#100 $finish;
	end

	initial begin
		$dumpfile("priority_encoder42.vcd");
		$dumpvars;
	end
endmodule