data/full_repos/permissive/143278/ivltests/packed_dims_invalid_module.v
 line:4: before: "typedef"
1: b"%Error: data/full_repos/permissive/143278/ivltests/packed_dims_invalid_module.v:4: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\ntypedef logic [] T1;\n               ^\n%Error: data/full_repos/permissive/143278/ivltests/packed_dims_invalid_module.v:5: syntax error, unexpected ']', expecting ':'\ntypedef logic [0] T2;\n                ^\n%Error: data/full_repos/permissive/143278/ivltests/packed_dims_invalid_module.v:6: syntax error, unexpected ']', expecting ':'\ntypedef logic [-1] T3;\n                 ^\n%Error: data/full_repos/permissive/143278/ivltests/packed_dims_invalid_module.v:7: syntax error, unexpected ']', expecting ':'\ntypedef logic [$] T4;\n                ^\n%Error: data/full_repos/permissive/143278/ivltests/packed_dims_invalid_module.v:10: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n  input [] port_a,\n         ^\n%Error: data/full_repos/permissive/143278/ivltests/packed_dims_invalid_module.v:15: syntax error, unexpected ']', expecting ':'\n logic [$] a;\n         ^\n%Error: data/full_repos/permissive/143278/ivltests/packed_dims_invalid_module.v:19: syntax error, unexpected ']', expecting ':'\n logic [0] d;\n         ^\n%Error: data/full_repos/permissive/143278/ivltests/packed_dims_invalid_module.v:23: syntax error, unexpected ']', expecting ':'\n logic [-1] g;\n          ^\n%Error: data/full_repos/permissive/143278/ivltests/packed_dims_invalid_module.v:27: syntax error, unexpected ']', expecting ':'\n logic [$] j;\n         ^\n%Error: Exiting due to 9 error(s)\n"
module test (
  input [] port_a,
  input [0] port_b,
  output [-1] port_c,
  output [$] port_d
);
	logic [$] a;
	T1 b;
	T1 [$] c;

	logic [0] d;
	T2 e;
	T2 [0] f;

	logic [-1] g;
	T3 h;
	T3 [-1] i;

	logic [$] j;
	T4 k;
	T4 [$] l;
endmodule
module test (
  input [] port_a,
  input [0] port_b,
  output [-1] port_c,
  output [$] port_d
);

	logic [$] a;
	T1 b;
	T1 [$] c;

	logic [0] d;
	T2 e;
	T2 [0] f;

	logic [-1] g;
	T3 h;
	T3 [-1] i;

	logic [$] j;
	T4 k;
	T4 [$] l;
endmodule