data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:5: Cannot find include file: lib/generic.v\n`include "lib/generic.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.v\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/lib/generic.v.sv\n             lib/generic.v\n             lib/generic.v.v\n             lib/generic.v.sv\n             obj_dir/lib/generic.v\n             obj_dir/lib/generic.v.v\n             obj_dir/lib/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:6: Cannot find include file: lib/DebugInfoWarningError.sv\n`include "lib/DebugInfoWarningError.sv" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:341: Expecting `error string. Found: TEXT\n   `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:344: Expecting `error string. Found: TEXT\n   `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:738: Expecting `error string. Found: TEXT\n   `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:741: Expecting `error string. Found: TEXT\n   `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:905: Expecting `error string. Found: TEXT\n   `error("%b (%s) is not supported as the axi::burst_t for awburst", axi.awburst, axi.awburst.name); \n         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:908: Expecting `error string. Found: TEXT\n   `error("%b (%s) is not supported as the axi::burst_t for arburst", axi.arburst, axi.arburst.name); \n         ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:7: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport DebugInfoWarningError::*;\n       ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:99: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n      ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:105: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n                  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:106: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n                  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:107: syntax error, unexpected \'.\', expecting ::\n wire  wbeat =  axi.wready &  axi.wvalid;\n                   ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:108: syntax error, unexpected \'.\', expecting ::\n wire  rbeat =  axi.rready &  axi.rvalid;\n                   ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:109: syntax error, unexpected \'.\', expecting ::\n wire  bbeat =  axi.bready &  axi.bvalid;\n                   ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:112: syntax error, unexpected \'.\', expecting ::\n always @(posedge  wbeat) begin $display("%t,  wbeat %08x", $time, axi.wdata); end\n                                                                      ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:113: syntax error, unexpected \'.\', expecting ::\n always @(posedge  rbeat) begin $display("%t,  rbeat %08x", $time, axi.rdata); end\n                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:118: Unsupported: Ignoring delay on this delayed statement.\n   #DELAY_BETWEEN_TRANSACTIONS;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:121: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD_OF_CLOCK_NS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:128: Unsupported: Ignoring delay on this delayed statement.\n   #DELAY_BETWEEN_TRANSACTIONS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:131: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD_OF_CLOCK_NS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:135: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD_OF_CLOCK_NS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:142: Unsupported: Ignoring delay on this delayed statement.\n  #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:143: Unsupported: Dynamic array new\n  data = new[1];\n         ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:148: Unsupported: Ignoring delay on this delayed statement.\n  #LONG_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:153: Unsupported: Ignoring delay on this delayed statement.\n  #LONG_DELAY; $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:157: Unsupported: Ignoring delay on this delayed statement.\n  #DELAY;\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:190: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n                 ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:208: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:347: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n                 ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:348: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n                           ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:376: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER\n axi4 axi(clock, reset);\n      ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:386: syntax error, unexpected \'.\', expecting ::\n wire awbeat = axi.awready & axi.awvalid;\n                  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:387: syntax error, unexpected \'.\', expecting ::\n wire arbeat = axi.arready & axi.arvalid;\n                  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:388: syntax error, unexpected \'.\', expecting ::\n wire  wbeat =  axi.wready &  axi.wvalid;\n                   ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:389: syntax error, unexpected \'.\', expecting ::\n wire  rbeat =  axi.rready &  axi.rvalid;\n                   ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:390: syntax error, unexpected \'.\', expecting ::\n wire  bbeat =  axi.bready &  axi.bvalid;\n                   ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:393: syntax error, unexpected \'.\', expecting ::\n always @(posedge  wbeat) begin $display("%t,  wbeat %08x", $time, axi.wdata); end\n                                                                      ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:394: syntax error, unexpected \'.\', expecting ::\n always @(posedge  rbeat) begin $display("%t,  rbeat %08x", $time, axi.rdata); end\n                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:399: Unsupported: Ignoring delay on this delayed statement.\n   #DELAY_BETWEEN_TRANSACTIONS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:403: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD_OF_CLOCK_NS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:407: Unsupported: Ignoring delay on this delayed statement.\n    #PERIOD_OF_CLOCK_NS;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:410: Unsupported: Ignoring delay on this delayed statement.\n     #DELAY_BETWEEN_READ_BEATS;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:418: Unsupported: Ignoring delay on this delayed statement.\n   #DELAY_BETWEEN_TRANSACTIONS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:422: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD_OF_CLOCK_NS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:428: Unsupported: Ignoring delay on this delayed statement.\n    #PERIOD_OF_CLOCK_NS;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:436: Unsupported: Ignoring delay on this delayed statement.\n   #DELAY_BETWEEN_TRANSACTIONS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:440: Unsupported: Ignoring delay on this delayed statement.\n   #PERIOD_OF_CLOCK_NS;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:446: Unsupported: Ignoring delay on this delayed statement.\n    #PERIOD_OF_CLOCK_NS;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:449: Unsupported: Ignoring delay on this delayed statement.\n     #DELAY_BETWEEN_WRITE_BEATS;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:453: Unsupported: Ignoring delay on this delayed statement.\n     #DELAY_BETWEEN_WRITE_BEATS;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:454: Unsupported: Ignoring delay on this delayed statement.\n     #DELAY_BETWEEN_WRITE_BEATS;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:455: Unsupported: Ignoring delay on this delayed statement.\n     #DELAY_BETWEEN_WRITE_BEATS;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:456: Unsupported: Ignoring delay on this delayed statement.\n     #DELAY_BETWEEN_WRITE_BEATS;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:465: Unsupported: Ignoring delay on this delayed statement.\n  #DELAY_BETWEEN_TRANSACTIONS; reset <= 0;\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:466: Unsupported: Dynamic array new\n  data = new[2**LEN_WIDTH];\n         ^~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:490: Unsupported: Ignoring delay on this delayed statement.\n  #LONG_DELAY;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:502: Unsupported: Ignoring delay on this delayed statement.\n  #LONG_DELAY; $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:506: Unsupported: Ignoring delay on this delayed statement.\n  #DELAY;\n  ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:546: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.controller axi\n                 ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:566: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:744: syntax error, unexpected \'.\', expecting ::\n wire rbeat = axi.rready & axi.rvalid;\n                 ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:745: syntax error, unexpected \'.\', expecting ::\n wire rlast_mismatch = (axi.rlast ^ our_rlast) & rbeat;\n                           ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:753: syntax error, unexpected PACKAGE-IDENTIFIER, expecting IDENTIFIER or do or final\n axi4.peripheral axi\n                 ^~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:766: syntax error, unexpected IDENTIFIER\n axi4 modified_copy(clock, reset);\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/axi4.sv:768: syntax error, unexpected always\n always @(posedge axi.clock) begin\n ^~~~~~\n%Error: Exiting due to 38 error(s), 28 warning(s)\n'
module parallel_peripheral_axi4_controller__pollable_memory_axi4_peripheral__tb;
	localparam ADDRESS_WIDTH = 4;
	localparam DATA_WIDTH = 32;
	localparam LEN_WIDTH = 5;
	localparam FREQUENCY_OF_CLOCK_HZ = 10000000;
	localparam PERIOD_OF_CLOCK_NS = 1000000000.0/FREQUENCY_OF_CLOCK_HZ;
	localparam DELAY_BETWEEN_TRANSACTIONS = 4*PERIOD_OF_CLOCK_NS;
	localparam DELAY_BETWEEN_WRITE_BEATS = 1*PERIOD_OF_CLOCK_NS;
	localparam DELAY_BETWEEN_READ_BEATS = 1*PERIOD_OF_CLOCK_NS;
	localparam LONG_DELAY = 8*PERIOD_OF_CLOCK_NS;
	wire clock;
	clock #(.FREQUENCY_OF_CLOCK_HZ(FREQUENCY_OF_CLOCK_HZ)) clockmod (.clock(clock));
	reg reset = 1;
	reg [ADDRESS_WIDTH-1:0] pre_parallel_write_address = 0;
	reg [ADDRESS_WIDTH-1:0] parallel_write_address = 0;
	reg pre_parallel_write_address_valid = 0;
	reg parallel_write_address_valid = 0;
	reg [DATA_WIDTH-1:0] pre_parallel_write_data = 0;
	reg [DATA_WIDTH-1:0] parallel_write_data = 0;
	reg [ADDRESS_WIDTH-1:0] pre_parallel_read_address = 0;
	reg [ADDRESS_WIDTH-1:0] parallel_read_address = 0;
	reg pre_parallel_read_address_valid = 0;
	reg parallel_read_address_valid = 0;
	wire [DATA_WIDTH-1:0] parallel_read_data;
	axi4 axi(clock, reset);
	reg pre_parallel_write_data_valid = 0;
	reg parallel_write_data_valid = 0;
	wire parallel_read_data_valid;
	parallel_peripheral__axi4_controller  #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) spac (.*);
	pollable_memory__axi4_peripheral #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH), .LEN_WIDTH(LEN_WIDTH)) pmap (.*);
	wire awbeat = axi.awready & axi.awvalid;
	wire arbeat = axi.arready & axi.arvalid;
	wire  wbeat =  axi.wready &  axi.wvalid;
	wire  rbeat =  axi.rready &  axi.rvalid;
	wire  bbeat =  axi.bready &  axi.bvalid;
	always @(posedge awbeat) begin $display("%t, awbeat %08x", $time, parallel_write_address); end
	always @(posedge arbeat) begin $display("%t, arbeat %08x", $time, parallel_read_address); end
	always @(posedge  wbeat) begin $display("%t,  wbeat %08x", $time, axi.wdata); end
	always @(posedge  rbeat) begin $display("%t,  rbeat %08x", $time, axi.rdata); end
	always @(posedge  bbeat) begin $display("%t,  bbeat", $time); end
	task automatic controller_read_transaction(input [ADDRESS_WIDTH-1:0] address);
		reg [ADDRESS_WIDTH:0] i;
		begin
			#DELAY_BETWEEN_TRANSACTIONS;
			pre_parallel_read_address <= address;
			pre_parallel_read_address_valid <= 1;
			#PERIOD_OF_CLOCK_NS;
			pre_parallel_read_address_valid <= 0;
		end
	endtask
	task automatic controller_write_transaction(input [ADDRESS_WIDTH-1:0] address, input [DATA_WIDTH-1:0] data []);
		reg [ADDRESS_WIDTH:0] i;
		begin
			#DELAY_BETWEEN_TRANSACTIONS;
			pre_parallel_write_address <= address;
			pre_parallel_write_address_valid <= 1;
			#PERIOD_OF_CLOCK_NS;
			pre_parallel_write_address_valid <= 0;
			pre_parallel_write_data <= data[0];
			pre_parallel_write_data_valid <= 1;
			#PERIOD_OF_CLOCK_NS;
			pre_parallel_write_data_valid <= 0;
		end
	endtask
	reg [DATA_WIDTH-1:0] data [];
	reg [31:0] i = 0;
	initial begin
		#DELAY_BETWEEN_TRANSACTIONS; reset <= 0;
		data = new[1];
		data[0] = 32'd0; controller_write_transaction(4'h0, data); controller_read_transaction(4'h0);
		data[0] = 32'd1; controller_write_transaction(4'h1, data); controller_read_transaction(4'h1);
		data[0] = 32'd2; controller_write_transaction(4'h2, data); controller_read_transaction(4'h2);
		data[0] = 32'd3; controller_write_transaction(4'h3, data); controller_read_transaction(4'h3);
		#LONG_DELAY;
		data[0] = 32'd8; controller_write_transaction(4'h7, data); controller_read_transaction(4'h7);
		data[0] = 32'd7; controller_write_transaction(4'h6, data); controller_read_transaction(4'h6);
		data[0] = 32'd6; controller_write_transaction(4'h5, data); controller_read_transaction(4'h5);
		data[0] = 32'd5; controller_write_transaction(4'h4, data); controller_read_transaction(4'h4);
		#LONG_DELAY; $finish;
	end
	localparam DELAY = 0;
	always @(posedge clock) begin
		#DELAY;
		if (reset) begin
			parallel_write_address       <= 0;
			parallel_write_address_valid <= 0;
			parallel_write_data          <= 0;
			parallel_write_data_valid    <= 0;
			parallel_read_address       <= 0;
			parallel_read_address_valid <= 0;
		end else begin
			parallel_write_address       <= pre_parallel_write_address;
			parallel_write_address_valid <= pre_parallel_write_address_valid;
			parallel_write_data          <= pre_parallel_write_data;
			parallel_write_data_valid    <= pre_parallel_write_data_valid;
			parallel_read_address       <= pre_parallel_read_address;
			parallel_read_address_valid <= pre_parallel_read_address_valid;
		end
	end
endmodule
module parallel_peripheral_axi4_controller__pollable_memory_axi4_peripheral__tb;

	localparam ADDRESS_WIDTH = 4;
	localparam DATA_WIDTH = 32;
	localparam LEN_WIDTH = 5;
	localparam FREQUENCY_OF_CLOCK_HZ = 10000000;
	localparam PERIOD_OF_CLOCK_NS = 1000000000.0/FREQUENCY_OF_CLOCK_HZ;
	localparam DELAY_BETWEEN_TRANSACTIONS = 4*PERIOD_OF_CLOCK_NS;
	localparam DELAY_BETWEEN_WRITE_BEATS = 1*PERIOD_OF_CLOCK_NS;
	localparam DELAY_BETWEEN_READ_BEATS = 1*PERIOD_OF_CLOCK_NS;
	localparam LONG_DELAY = 8*PERIOD_OF_CLOCK_NS;
	wire clock;
	clock #(.FREQUENCY_OF_CLOCK_HZ(FREQUENCY_OF_CLOCK_HZ)) clockmod (.clock(clock));
	reg reset = 1;
	reg [ADDRESS_WIDTH-1:0] pre_parallel_write_address = 0;
	reg [ADDRESS_WIDTH-1:0] parallel_write_address = 0;
	reg pre_parallel_write_address_valid = 0;
	reg parallel_write_address_valid = 0;
	reg [DATA_WIDTH-1:0] pre_parallel_write_data = 0;
	reg [DATA_WIDTH-1:0] parallel_write_data = 0;
	reg [ADDRESS_WIDTH-1:0] pre_parallel_read_address = 0;
	reg [ADDRESS_WIDTH-1:0] parallel_read_address = 0;
	reg pre_parallel_read_address_valid = 0;
	reg parallel_read_address_valid = 0;
	wire [DATA_WIDTH-1:0] parallel_read_data;
	axi4 axi(clock, reset);
	reg pre_parallel_write_data_valid = 0;
	reg parallel_write_data_valid = 0;
	wire parallel_read_data_valid;
	parallel_peripheral__axi4_controller  #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) spac (.*);
	pollable_memory__axi4_peripheral #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH), .LEN_WIDTH(LEN_WIDTH)) pmap (.*);
	wire awbeat = axi.awready & axi.awvalid;
	wire arbeat = axi.arready & axi.arvalid;
	wire  wbeat =  axi.wready &  axi.wvalid;
	wire  rbeat =  axi.rready &  axi.rvalid;
	wire  bbeat =  axi.bready &  axi.bvalid;
	always @(posedge awbeat) begin $display("%t, awbeat %08x", $time, parallel_write_address); end
	always @(posedge arbeat) begin $display("%t, arbeat %08x", $time, parallel_read_address); end
	always @(posedge  wbeat) begin $display("%t,  wbeat %08x", $time, axi.wdata); end
	always @(posedge  rbeat) begin $display("%t,  rbeat %08x", $time, axi.rdata); end
	always @(posedge  bbeat) begin $display("%t,  bbeat", $time); end
	task automatic controller_read_transaction(input [ADDRESS_WIDTH-1:0] address);
		reg [ADDRESS_WIDTH:0] i;
		begin
			#DELAY_BETWEEN_TRANSACTIONS;
			pre_parallel_read_address <= address;
			pre_parallel_read_address_valid <= 1;
			#PERIOD_OF_CLOCK_NS;
			pre_parallel_read_address_valid <= 0;
		end
	endtask
	task automatic controller_write_transaction(input [ADDRESS_WIDTH-1:0] address, input [DATA_WIDTH-1:0] data []);
		reg [ADDRESS_WIDTH:0] i;
		begin
			#DELAY_BETWEEN_TRANSACTIONS;
			pre_parallel_write_address <= address;
			pre_parallel_write_address_valid <= 1;
			#PERIOD_OF_CLOCK_NS;
			pre_parallel_write_address_valid <= 0;
			pre_parallel_write_data <= data[0];
			pre_parallel_write_data_valid <= 1;
			#PERIOD_OF_CLOCK_NS;
			pre_parallel_write_data_valid <= 0;
		end
	endtask
	reg [DATA_WIDTH-1:0] data [];
	reg [31:0] i = 0;
	initial begin
		#DELAY_BETWEEN_TRANSACTIONS; reset <= 0;
		data = new[1];
		data[0] = 32'd0; controller_write_transaction(4'h0, data); controller_read_transaction(4'h0);
		data[0] = 32'd1; controller_write_transaction(4'h1, data); controller_read_transaction(4'h1);
		data[0] = 32'd2; controller_write_transaction(4'h2, data); controller_read_transaction(4'h2);
		data[0] = 32'd3; controller_write_transaction(4'h3, data); controller_read_transaction(4'h3);
		#LONG_DELAY;
		data[0] = 32'd8; controller_write_transaction(4'h7, data); controller_read_transaction(4'h7);
		data[0] = 32'd7; controller_write_transaction(4'h6, data); controller_read_transaction(4'h6);
		data[0] = 32'd6; controller_write_transaction(4'h5, data); controller_read_transaction(4'h5);
		data[0] = 32'd5; controller_write_transaction(4'h4, data); controller_read_transaction(4'h4);
		#LONG_DELAY; $finish;
	end
	localparam DELAY = 0;
	always @(posedge clock) begin
		#DELAY;
		if (reset) begin
			parallel_write_address       <= 0;
			parallel_write_address_valid <= 0;
			parallel_write_data          <= 0;
			parallel_write_data_valid    <= 0;
			parallel_read_address       <= 0;
			parallel_read_address_valid <= 0;
		end else begin
			parallel_write_address       <= pre_parallel_write_address;
			parallel_write_address_valid <= pre_parallel_write_address_valid;
			parallel_write_data          <= pre_parallel_write_data;
			parallel_write_data_valid    <= pre_parallel_write_data_valid;
			parallel_read_address       <= pre_parallel_read_address;
			parallel_read_address_valid <= pre_parallel_read_address_valid;
		end
	end
endmodule