data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg0 <= \'d0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg1 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg2 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg3 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg4 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg5 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg6 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg7 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg8 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg9 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg10 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg11 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg12 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg13 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg14 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:138: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg15 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg16 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:140: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg17 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:141: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg18 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:142: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg19 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:143: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg20 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg21 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg22 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:146: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg23 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:147: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg24 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg25 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:149: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg26 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg27 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:151: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg28 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:152: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg29 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:153: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg30 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:154: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_reg31 <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:157: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_rsp_valid_reg <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #1 icb_rsp_rdata_reg <= \'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:163: Unsupported: Ignoring delay on this delayed statement.\n    5\'d0: begin   #1 icb_reg0 <= i_icb_cmd_wdata;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:164: Unsupported: Ignoring delay on this delayed statement.\n    5\'d1: begin   #1 icb_reg1 <= i_icb_cmd_wdata;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:165: Unsupported: Ignoring delay on this delayed statement.\n    5\'d2: begin   #1 icb_reg2 <= i_icb_cmd_wdata;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:166: Unsupported: Ignoring delay on this delayed statement.\n    5\'d3: begin   #1 icb_reg3 <= i_icb_cmd_wdata;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:167: Unsupported: Ignoring delay on this delayed statement.\n    5\'d4: begin   #1 icb_reg4 <= i_icb_cmd_wdata;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:168: Unsupported: Ignoring delay on this delayed statement.\n    5\'d5: begin   #1 icb_reg5 <= i_icb_cmd_wdata;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:169: Unsupported: Ignoring delay on this delayed statement.\n    5\'d6: begin   #1 icb_reg6 <= i_icb_cmd_wdata;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:170: Unsupported: Ignoring delay on this delayed statement.\n    5\'d7: begin   #1 icb_reg7 <= i_icb_cmd_wdata;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:171: Unsupported: Ignoring delay on this delayed statement.\n    5\'d8: begin   #1 icb_reg8 <= i_icb_cmd_wdata;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:172: Unsupported: Ignoring delay on this delayed statement.\n    5\'d9: begin   #1 icb_reg9 <= i_icb_cmd_wdata;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:173: Unsupported: Ignoring delay on this delayed statement.\n    5\'d10:begin  #1  icb_reg10 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:174: Unsupported: Ignoring delay on this delayed statement.\n    5\'d11:begin  #1  icb_reg11 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:175: Unsupported: Ignoring delay on this delayed statement.\n    5\'d12:begin  #1  icb_reg12 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:176: Unsupported: Ignoring delay on this delayed statement.\n    5\'d13:begin  #1  icb_reg13 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:177: Unsupported: Ignoring delay on this delayed statement.\n    5\'d14:begin  #1  icb_reg14 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:178: Unsupported: Ignoring delay on this delayed statement.\n    5\'d15:begin  #1  icb_reg15 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:179: Unsupported: Ignoring delay on this delayed statement.\n    5\'d16:begin  #1  icb_reg16 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:180: Unsupported: Ignoring delay on this delayed statement.\n    5\'d17:begin  #1  icb_reg17 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:181: Unsupported: Ignoring delay on this delayed statement.\n    5\'d18:begin  #1  icb_reg18 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:182: Unsupported: Ignoring delay on this delayed statement.\n    5\'d19:begin  #1  icb_reg19 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:183: Unsupported: Ignoring delay on this delayed statement.\n    5\'d20:begin  #1  icb_reg20 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:184: Unsupported: Ignoring delay on this delayed statement.\n    5\'d21:begin  #1  icb_reg21 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:185: Unsupported: Ignoring delay on this delayed statement.\n    5\'d22:begin  #1  icb_reg22 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:186: Unsupported: Ignoring delay on this delayed statement.\n    5\'d23:begin  #1  icb_reg23 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:187: Unsupported: Ignoring delay on this delayed statement.\n    5\'d24:begin  #1  icb_reg24 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:188: Unsupported: Ignoring delay on this delayed statement.\n    5\'d25:begin  #1  icb_reg25 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:189: Unsupported: Ignoring delay on this delayed statement.\n    5\'d26:begin  #1  icb_reg26 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:190: Unsupported: Ignoring delay on this delayed statement.\n    5\'d27:begin  #1  icb_reg27 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:191: Unsupported: Ignoring delay on this delayed statement.\n    5\'d28:begin  #1  icb_reg28 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:192: Unsupported: Ignoring delay on this delayed statement.\n    5\'d29:begin  #1  icb_reg29 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:193: Unsupported: Ignoring delay on this delayed statement.\n    5\'d30:begin  #1  icb_reg30 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:194: Unsupported: Ignoring delay on this delayed statement.\n    5\'d31:begin  #1  icb_reg31 <= i_icb_cmd_wdata;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:203: Unsupported: Ignoring delay on this delayed statement.\n   #1 icb_rsp_valid_reg <= 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:204: Unsupported: Ignoring delay on this delayed statement.\n   #1 icb_rsp_rdata_reg <= \'d0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:208: Unsupported: Ignoring delay on this delayed statement.\n   #1 icb_rsp_valid_reg <= 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:211: Unsupported: Ignoring delay on this delayed statement.\n    5\'d0:  begin  #1 icb_rsp_rdata_reg <= icb_reg0;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:212: Unsupported: Ignoring delay on this delayed statement.\n    5\'d1:  begin  #1 icb_rsp_rdata_reg <= icb_reg1;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:213: Unsupported: Ignoring delay on this delayed statement.\n    5\'d2:  begin  #1 icb_rsp_rdata_reg <= icb_reg2;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:214: Unsupported: Ignoring delay on this delayed statement.\n    5\'d3:  begin  #1 icb_rsp_rdata_reg <= icb_reg3;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:215: Unsupported: Ignoring delay on this delayed statement.\n    5\'d4:  begin  #1 icb_rsp_rdata_reg <= icb_reg4;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:216: Unsupported: Ignoring delay on this delayed statement.\n    5\'d5:  begin  #1 icb_rsp_rdata_reg <= icb_reg5;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:217: Unsupported: Ignoring delay on this delayed statement.\n    5\'d6:  begin  #1 icb_rsp_rdata_reg <= icb_reg6;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:218: Unsupported: Ignoring delay on this delayed statement.\n    5\'d7:  begin  #1 icb_rsp_rdata_reg <= icb_reg7;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:219: Unsupported: Ignoring delay on this delayed statement.\n    5\'d8:  begin  #1 icb_rsp_rdata_reg <= icb_reg8;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:220: Unsupported: Ignoring delay on this delayed statement.\n    5\'d9:  begin  #1 icb_rsp_rdata_reg <= icb_reg9;end\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:221: Unsupported: Ignoring delay on this delayed statement.\n    5\'d10: begin #1  icb_rsp_rdata_reg <= icb_reg10;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:222: Unsupported: Ignoring delay on this delayed statement.\n    5\'d11: begin #1  icb_rsp_rdata_reg <= icb_reg11;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:223: Unsupported: Ignoring delay on this delayed statement.\n    5\'d12: begin #1  icb_rsp_rdata_reg <= stepperPosition[31:0]; end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:224: Unsupported: Ignoring delay on this delayed statement.\n    5\'d13: begin #1  icb_rsp_rdata_reg <= stepperPosition[63:32]; end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:225: Unsupported: Ignoring delay on this delayed statement.\n    5\'d14: begin #1  icb_rsp_rdata_reg <= stepperPosition[95:64]; end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:226: Unsupported: Ignoring delay on this delayed statement.\n    5\'d15: begin #1  icb_rsp_rdata_reg <= stepperPosition[127:96]; end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:227: Unsupported: Ignoring delay on this delayed statement.\n    5\'d16: begin #1  icb_rsp_rdata_reg <= stepperPosition[159:128]; end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:228: Unsupported: Ignoring delay on this delayed statement.\n    5\'d17: begin #1  icb_rsp_rdata_reg <= stepperPosition[191:160]; end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:229: Unsupported: Ignoring delay on this delayed statement.\n    5\'d18: begin #1  icb_rsp_rdata_reg <= stepperPosition[223:192]; end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:230: Unsupported: Ignoring delay on this delayed statement.\n    5\'d19: begin #1  icb_rsp_rdata_reg <= stepperPosition[255:224]; end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:231: Unsupported: Ignoring delay on this delayed statement.\n    5\'d20: begin #1  icb_rsp_rdata_reg <= stepperPosition[287:256]; end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:232: Unsupported: Ignoring delay on this delayed statement.\n    5\'d21: begin #1  icb_rsp_rdata_reg <= stepperPosition[319:288]; end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:233: Unsupported: Ignoring delay on this delayed statement.\n    5\'d22: begin #1  icb_rsp_rdata_reg <= stepperPosition[351:320]; end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:234: Unsupported: Ignoring delay on this delayed statement.\n    5\'d23: begin #1  icb_rsp_rdata_reg <= stepperPosition[383:352]; end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:235: Unsupported: Ignoring delay on this delayed statement.\n    5\'d24: begin #1  icb_rsp_rdata_reg <= icb_reg24;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:236: Unsupported: Ignoring delay on this delayed statement.\n    5\'d25: begin #1  icb_rsp_rdata_reg <= icb_reg25;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:237: Unsupported: Ignoring delay on this delayed statement.\n    5\'d26: begin #1  icb_rsp_rdata_reg <= icb_reg26;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:238: Unsupported: Ignoring delay on this delayed statement.\n    5\'d27: begin #1  icb_rsp_rdata_reg <= icb_reg27;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:239: Unsupported: Ignoring delay on this delayed statement.\n    5\'d28: begin #1  icb_rsp_rdata_reg <= icb_reg28;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:240: Unsupported: Ignoring delay on this delayed statement.\n    5\'d29: begin #1  icb_rsp_rdata_reg <= icb_reg29;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:241: Unsupported: Ignoring delay on this delayed statement.\n    5\'d30: begin #1  icb_rsp_rdata_reg <= icb_reg30;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:242: Unsupported: Ignoring delay on this delayed statement.\n    5\'d31: begin #1  icb_rsp_rdata_reg <= icb_reg31;end\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:243: Unsupported: Ignoring delay on this delayed statement.\n   default: #1 icb_rsp_rdata_reg <= \'d66;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:253: Unsupported: Ignoring delay on this delayed statement.\n   #1 icb_rsp_valid_reg <= 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:254: Unsupported: Ignoring delay on this delayed statement.\n   #1 icb_rsp_rdata_reg <= \'d0;\n   ^\n%Error: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:294: Cannot find file containing module: \'stepper_package\'\nstepper_package i_stepper_package0 \n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm,data/full_repos/permissive/160924877/stepper_package\n             data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm,data/full_repos/permissive/160924877/stepper_package.v\n             data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm,data/full_repos/permissive/160924877/stepper_package.sv\n             stepper_package\n             stepper_package.v\n             stepper_package.sv\n             obj_dir/stepper_package\n             obj_dir/stepper_package.v\n             obj_dir/stepper_package.sv\n%Error: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:313: Cannot find file containing module: \'stepper_package\'\nstepper_package i_stepper_package1\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/icb_RA_PL.v:334: Cannot find file containing module: \'teleStop\'\nteleStop i_teleStop\n^~~~~~~~\n%Error: Exiting due to 3 error(s), 104 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PRM_RA_PL (

	output [5:0] powerENA,
	output [5:0] thrusterDirectA,
	output [5:0] powerENB,
	output [5:0] thrusterDirectB,

	input [3:0] petectIO,
	output [5:0]  safetyPluseA,
	output [5:0]  safetyPluseB,

    output redLed,
    output greenLed,

    output BZ,
    input CLK100MHZ,





	input			i_icb_cmd_valid,
	output			i_icb_cmd_ready,
	input [31:0]	i_icb_cmd_addr, 
	input			i_icb_cmd_read, 
	input [31:0]	i_icb_cmd_wdata,
	
	output			i_icb_rsp_valid,
	input			i_icb_rsp_ready,
	output [31:0]	i_icb_rsp_rdata,

	input	clk,
	input	rst_n
);




wire [383:0] stepperPosition;

wire [383:0] stepCnt;
wire currentLoopPowerOnA;
wire currentLoopEnableA;

wire currentLoopPowerOnB;
wire currentLoopEnableB;

wire stepperRST;

















reg [31:0] icb_reg0;
reg [31:0] icb_reg1;
reg [31:0] icb_reg2;
reg [31:0] icb_reg3;
reg [31:0] icb_reg4;
reg [31:0] icb_reg5;
reg [31:0] icb_reg6;
reg [31:0] icb_reg7;
reg [31:0] icb_reg8;
reg [31:0] icb_reg9;
reg [31:0] icb_reg10;
reg [31:0] icb_reg11;
reg [31:0] icb_reg12;
reg [31:0] icb_reg13;
reg [31:0] icb_reg14;
reg [31:0] icb_reg15;
reg [31:0] icb_reg16;
reg [31:0] icb_reg17;
reg [31:0] icb_reg18;
reg [31:0] icb_reg19;
reg [31:0] icb_reg20;
reg [31:0] icb_reg21;
reg [31:0] icb_reg22;
reg [31:0] icb_reg23;
reg [31:0] icb_reg24;
reg [31:0] icb_reg25;
reg [31:0] icb_reg26;
reg [31:0] icb_reg27;
reg [31:0] icb_reg28;
reg [31:0] icb_reg29;
reg [31:0] icb_reg30;
reg [31:0] icb_reg31;



reg icb_rsp_valid_reg;

reg [31:0] icb_rsp_rdata_reg;

assign i_icb_cmd_ready = i_icb_cmd_valid;
assign i_icb_rsp_valid = ( (~i_icb_cmd_read) & i_icb_cmd_valid ) 
						| icb_rsp_valid_reg;
assign i_icb_rsp_rdata = icb_rsp_rdata_reg;

wire [4:0] reg_mux = i_icb_cmd_addr[6:2];






always @ ( posedge clk or negedge rst_n ) begin
	if ( !rst_n ) begin
		#1 icb_reg0 <= 'd0;
		#1 icb_reg1 <= 'd0;
		#1 icb_reg2 <= 'd0;
		#1 icb_reg3 <= 'd0;
		#1 icb_reg4 <= 'd0;
		#1 icb_reg5 <= 'd0;
		#1 icb_reg6 <= 'd0;
		#1 icb_reg7 <= 'd0;
		#1 icb_reg8 <= 'd0;
		#1 icb_reg9 <= 'd0;
		#1 icb_reg10 <= 'd0;
		#1 icb_reg11 <= 'd0;
		#1 icb_reg12 <= 'd0;
		#1 icb_reg13 <= 'd0;
		#1 icb_reg14 <= 'd0;
		#1 icb_reg15 <= 'd0;
		#1 icb_reg16 <= 'd0;
		#1 icb_reg17 <= 'd0;
		#1 icb_reg18 <= 'd0;
		#1 icb_reg19 <= 'd0;
		#1 icb_reg20 <= 'd0;
		#1 icb_reg21 <= 'd0;
		#1 icb_reg22 <= 'd0;
		#1 icb_reg23 <= 'd0;
		#1 icb_reg24 <= 'd0;
		#1 icb_reg25 <= 'd0;
		#1 icb_reg26 <= 'd0;
		#1 icb_reg27 <= 'd0;
		#1 icb_reg28 <= 'd0;
		#1 icb_reg29 <= 'd0;
		#1 icb_reg30 <= 'd0;
		#1 icb_reg31 <= 'd0;


		#1 icb_rsp_valid_reg <= 1'b0;
		#1 icb_rsp_rdata_reg <= 'd0;
	end
	else begin
		if ( ~i_icb_cmd_read & i_icb_cmd_valid ) begin
			case(reg_mux)
				5'd0: begin   #1 icb_reg0 <= i_icb_cmd_wdata;end
				5'd1: begin   #1 icb_reg1 <= i_icb_cmd_wdata;end
				5'd2: begin   #1 icb_reg2 <= i_icb_cmd_wdata;end
				5'd3: begin   #1 icb_reg3 <= i_icb_cmd_wdata;end
				5'd4: begin   #1 icb_reg4 <= i_icb_cmd_wdata;end
				5'd5: begin   #1 icb_reg5 <= i_icb_cmd_wdata;end
				5'd6: begin   #1 icb_reg6 <= i_icb_cmd_wdata;end
				5'd7: begin   #1 icb_reg7 <= i_icb_cmd_wdata;end
				5'd8: begin   #1 icb_reg8 <= i_icb_cmd_wdata;end
				5'd9: begin   #1 icb_reg9 <= i_icb_cmd_wdata;end
				5'd10:begin  #1  icb_reg10 <= i_icb_cmd_wdata;end
				5'd11:begin  #1  icb_reg11 <= i_icb_cmd_wdata;end
				5'd12:begin  #1  icb_reg12 <= i_icb_cmd_wdata;end
				5'd13:begin  #1  icb_reg13 <= i_icb_cmd_wdata;end
				5'd14:begin  #1  icb_reg14 <= i_icb_cmd_wdata;end
				5'd15:begin  #1  icb_reg15 <= i_icb_cmd_wdata;end
				5'd16:begin  #1  icb_reg16 <= i_icb_cmd_wdata;end
				5'd17:begin  #1  icb_reg17 <= i_icb_cmd_wdata;end
				5'd18:begin  #1  icb_reg18 <= i_icb_cmd_wdata;end
				5'd19:begin  #1  icb_reg19 <= i_icb_cmd_wdata;end
				5'd20:begin  #1  icb_reg20 <= i_icb_cmd_wdata;end
				5'd21:begin  #1  icb_reg21 <= i_icb_cmd_wdata;end
				5'd22:begin  #1  icb_reg22 <= i_icb_cmd_wdata;end
				5'd23:begin  #1  icb_reg23 <= i_icb_cmd_wdata;end
				5'd24:begin  #1  icb_reg24 <= i_icb_cmd_wdata;end
				5'd25:begin  #1  icb_reg25 <= i_icb_cmd_wdata;end
				5'd26:begin  #1  icb_reg26 <= i_icb_cmd_wdata;end
				5'd27:begin  #1  icb_reg27 <= i_icb_cmd_wdata;end
				5'd28:begin  #1  icb_reg28 <= i_icb_cmd_wdata;end
				5'd29:begin  #1  icb_reg29 <= i_icb_cmd_wdata;end
				5'd30:begin  #1  icb_reg30 <= i_icb_cmd_wdata;end
				5'd31:begin  #1  icb_reg31 <= i_icb_cmd_wdata;end
				default: begin end 





			endcase

			#1 icb_rsp_valid_reg <= 1'b0;
			#1 icb_rsp_rdata_reg <= 'd0;
		end

		else if ( i_icb_cmd_read & i_icb_cmd_valid ) begin
			#1 icb_rsp_valid_reg <= 1'b1;

			case(reg_mux)
				5'd0:  begin  #1 icb_rsp_rdata_reg <= icb_reg0;end
				5'd1:  begin  #1 icb_rsp_rdata_reg <= icb_reg1;end
				5'd2:  begin  #1 icb_rsp_rdata_reg <= icb_reg2;end
				5'd3:  begin  #1 icb_rsp_rdata_reg <= icb_reg3;end
				5'd4:  begin  #1 icb_rsp_rdata_reg <= icb_reg4;end
				5'd5:  begin  #1 icb_rsp_rdata_reg <= icb_reg5;end
				5'd6:  begin  #1 icb_rsp_rdata_reg <= icb_reg6;end
				5'd7:  begin  #1 icb_rsp_rdata_reg <= icb_reg7;end
				5'd8:  begin  #1 icb_rsp_rdata_reg <= icb_reg8;end
				5'd9:  begin  #1 icb_rsp_rdata_reg <= icb_reg9;end
				5'd10: begin #1  icb_rsp_rdata_reg <= icb_reg10;end
				5'd11: begin #1  icb_rsp_rdata_reg <= icb_reg11;end
				5'd12: begin #1  icb_rsp_rdata_reg <= stepperPosition[31:0]; end
				5'd13: begin #1  icb_rsp_rdata_reg <= stepperPosition[63:32]; end
				5'd14: begin #1  icb_rsp_rdata_reg <= stepperPosition[95:64]; end
				5'd15: begin #1  icb_rsp_rdata_reg <= stepperPosition[127:96]; end
				5'd16: begin #1  icb_rsp_rdata_reg <= stepperPosition[159:128]; end
				5'd17: begin #1  icb_rsp_rdata_reg <= stepperPosition[191:160]; end
				5'd18: begin #1  icb_rsp_rdata_reg <= stepperPosition[223:192]; end
				5'd19: begin #1  icb_rsp_rdata_reg <= stepperPosition[255:224]; end
				5'd20: begin #1  icb_rsp_rdata_reg <= stepperPosition[287:256]; end
				5'd21: begin #1  icb_rsp_rdata_reg <= stepperPosition[319:288]; end
				5'd22: begin #1  icb_rsp_rdata_reg <= stepperPosition[351:320]; end
				5'd23: begin #1  icb_rsp_rdata_reg <= stepperPosition[383:352]; end
				5'd24: begin #1  icb_rsp_rdata_reg <= icb_reg24;end
				5'd25: begin #1  icb_rsp_rdata_reg <= icb_reg25;end
				5'd26: begin #1  icb_rsp_rdata_reg <= icb_reg26;end
				5'd27: begin #1  icb_rsp_rdata_reg <= icb_reg27;end
				5'd28: begin #1  icb_rsp_rdata_reg <= icb_reg28;end
				5'd29: begin #1  icb_rsp_rdata_reg <= icb_reg29;end
				5'd30: begin #1  icb_rsp_rdata_reg <= icb_reg30;end
				5'd31: begin #1  icb_rsp_rdata_reg <= icb_reg31;end
			default: #1 icb_rsp_rdata_reg <= 'd66;



			endcase


		end

		else if ( i_icb_rsp_ready == 1'b1 ) begin
			#1 icb_rsp_valid_reg <= 1'b0;
			#1 icb_rsp_rdata_reg <= 'd0;
		end

		else begin


		end



	end


end




assign stepCnt = {icb_reg11,icb_reg10,icb_reg9,icb_reg8,icb_reg7,icb_reg6,icb_reg5,icb_reg4,icb_reg3,icb_reg2,icb_reg1,icb_reg0};

assign currentLoopPowerOnA = icb_reg25[0];
assign currentLoopEnableA = icb_reg24[0];

assign currentLoopPowerOnB = icb_reg27[0];
assign currentLoopEnableB = icb_reg26[0];

assign stepperRST = icb_reg28[0];







wire [ 5 : 0 ] thrusterPluseA;
wire [ 5 : 0 ] thrusterPluseB;




stepper_package i_stepper_package0 
(
	.CLK(CLK100MHZ),
	.RST_n(stepperRST),
	
	.stepCnt(stepCnt[191:0]),
	.currentLoopPowerOn(currentLoopPowerOnA),
	.currentLoopEnable(currentLoopEnableA),

	.stepperPosition(stepperPosition[191:0]),

	.powerEN(powerENA),
	.thrusterPluse(thrusterPluseA),
	.thrusterDirect(thrusterDirectA)
);




stepper_package i_stepper_package1
(
	.CLK(CLK100MHZ),
	.RST_n(stepperRST),
	
	.stepCnt(stepCnt[383:192]),
	.currentLoopPowerOn(currentLoopPowerOnB),
	.currentLoopEnable(currentLoopEnableB),

	.stepperPosition(stepperPosition[383:192]),

	.powerEN(powerENB),
	.thrusterPluse(thrusterPluseB),
	.thrusterDirect(thrusterDirectB)
);






teleStop i_teleStop
(
	.CLK(CLK100MHZ),
	.RST_n(stepperRST),

	.petectIO(petectIO),

	.thrusterPluseA(thrusterPluseA),
	.safetyPluseA(safetyPluseA),
   
	.thrusterPluseB(thrusterPluseB),
	.safetyPluseB(safetyPluseB),

    .redLed(redLed),
    .greenLed(greenLed),
    .BZ(BZ)
);










endmodule
module PRM_RA_PL (

	output [5:0] powerENA,
	output [5:0] thrusterDirectA,
	output [5:0] powerENB,
	output [5:0] thrusterDirectB,

	input [3:0] petectIO,
	output [5:0]  safetyPluseA,
	output [5:0]  safetyPluseB,

    output redLed,
    output greenLed,

    output BZ,
    input CLK100MHZ,





	input			i_icb_cmd_valid,
	output			i_icb_cmd_ready,
	input [31:0]	i_icb_cmd_addr, 
	input			i_icb_cmd_read, 
	input [31:0]	i_icb_cmd_wdata,
	
	output			i_icb_rsp_valid,
	input			i_icb_rsp_ready,
	output [31:0]	i_icb_rsp_rdata,

	input	clk,
	input	rst_n
);





wire [383:0] stepperPosition;

wire [383:0] stepCnt;
wire currentLoopPowerOnA;
wire currentLoopEnableA;

wire currentLoopPowerOnB;
wire currentLoopEnableB;

wire stepperRST;

















reg [31:0] icb_reg0;
reg [31:0] icb_reg1;
reg [31:0] icb_reg2;
reg [31:0] icb_reg3;
reg [31:0] icb_reg4;
reg [31:0] icb_reg5;
reg [31:0] icb_reg6;
reg [31:0] icb_reg7;
reg [31:0] icb_reg8;
reg [31:0] icb_reg9;
reg [31:0] icb_reg10;
reg [31:0] icb_reg11;
reg [31:0] icb_reg12;
reg [31:0] icb_reg13;
reg [31:0] icb_reg14;
reg [31:0] icb_reg15;
reg [31:0] icb_reg16;
reg [31:0] icb_reg17;
reg [31:0] icb_reg18;
reg [31:0] icb_reg19;
reg [31:0] icb_reg20;
reg [31:0] icb_reg21;
reg [31:0] icb_reg22;
reg [31:0] icb_reg23;
reg [31:0] icb_reg24;
reg [31:0] icb_reg25;
reg [31:0] icb_reg26;
reg [31:0] icb_reg27;
reg [31:0] icb_reg28;
reg [31:0] icb_reg29;
reg [31:0] icb_reg30;
reg [31:0] icb_reg31;



reg icb_rsp_valid_reg;

reg [31:0] icb_rsp_rdata_reg;

assign i_icb_cmd_ready = i_icb_cmd_valid;
assign i_icb_rsp_valid = ( (~i_icb_cmd_read) & i_icb_cmd_valid ) 
						| icb_rsp_valid_reg;
assign i_icb_rsp_rdata = icb_rsp_rdata_reg;

wire [4:0] reg_mux = i_icb_cmd_addr[6:2];






always @ ( posedge clk or negedge rst_n ) begin
	if ( !rst_n ) begin
		#1 icb_reg0 <= 'd0;
		#1 icb_reg1 <= 'd0;
		#1 icb_reg2 <= 'd0;
		#1 icb_reg3 <= 'd0;
		#1 icb_reg4 <= 'd0;
		#1 icb_reg5 <= 'd0;
		#1 icb_reg6 <= 'd0;
		#1 icb_reg7 <= 'd0;
		#1 icb_reg8 <= 'd0;
		#1 icb_reg9 <= 'd0;
		#1 icb_reg10 <= 'd0;
		#1 icb_reg11 <= 'd0;
		#1 icb_reg12 <= 'd0;
		#1 icb_reg13 <= 'd0;
		#1 icb_reg14 <= 'd0;
		#1 icb_reg15 <= 'd0;
		#1 icb_reg16 <= 'd0;
		#1 icb_reg17 <= 'd0;
		#1 icb_reg18 <= 'd0;
		#1 icb_reg19 <= 'd0;
		#1 icb_reg20 <= 'd0;
		#1 icb_reg21 <= 'd0;
		#1 icb_reg22 <= 'd0;
		#1 icb_reg23 <= 'd0;
		#1 icb_reg24 <= 'd0;
		#1 icb_reg25 <= 'd0;
		#1 icb_reg26 <= 'd0;
		#1 icb_reg27 <= 'd0;
		#1 icb_reg28 <= 'd0;
		#1 icb_reg29 <= 'd0;
		#1 icb_reg30 <= 'd0;
		#1 icb_reg31 <= 'd0;


		#1 icb_rsp_valid_reg <= 1'b0;
		#1 icb_rsp_rdata_reg <= 'd0;
	end
	else begin
		if ( ~i_icb_cmd_read & i_icb_cmd_valid ) begin
			case(reg_mux)
				5'd0: begin   #1 icb_reg0 <= i_icb_cmd_wdata;end
				5'd1: begin   #1 icb_reg1 <= i_icb_cmd_wdata;end
				5'd2: begin   #1 icb_reg2 <= i_icb_cmd_wdata;end
				5'd3: begin   #1 icb_reg3 <= i_icb_cmd_wdata;end
				5'd4: begin   #1 icb_reg4 <= i_icb_cmd_wdata;end
				5'd5: begin   #1 icb_reg5 <= i_icb_cmd_wdata;end
				5'd6: begin   #1 icb_reg6 <= i_icb_cmd_wdata;end
				5'd7: begin   #1 icb_reg7 <= i_icb_cmd_wdata;end
				5'd8: begin   #1 icb_reg8 <= i_icb_cmd_wdata;end
				5'd9: begin   #1 icb_reg9 <= i_icb_cmd_wdata;end
				5'd10:begin  #1  icb_reg10 <= i_icb_cmd_wdata;end
				5'd11:begin  #1  icb_reg11 <= i_icb_cmd_wdata;end
				5'd12:begin  #1  icb_reg12 <= i_icb_cmd_wdata;end
				5'd13:begin  #1  icb_reg13 <= i_icb_cmd_wdata;end
				5'd14:begin  #1  icb_reg14 <= i_icb_cmd_wdata;end
				5'd15:begin  #1  icb_reg15 <= i_icb_cmd_wdata;end
				5'd16:begin  #1  icb_reg16 <= i_icb_cmd_wdata;end
				5'd17:begin  #1  icb_reg17 <= i_icb_cmd_wdata;end
				5'd18:begin  #1  icb_reg18 <= i_icb_cmd_wdata;end
				5'd19:begin  #1  icb_reg19 <= i_icb_cmd_wdata;end
				5'd20:begin  #1  icb_reg20 <= i_icb_cmd_wdata;end
				5'd21:begin  #1  icb_reg21 <= i_icb_cmd_wdata;end
				5'd22:begin  #1  icb_reg22 <= i_icb_cmd_wdata;end
				5'd23:begin  #1  icb_reg23 <= i_icb_cmd_wdata;end
				5'd24:begin  #1  icb_reg24 <= i_icb_cmd_wdata;end
				5'd25:begin  #1  icb_reg25 <= i_icb_cmd_wdata;end
				5'd26:begin  #1  icb_reg26 <= i_icb_cmd_wdata;end
				5'd27:begin  #1  icb_reg27 <= i_icb_cmd_wdata;end
				5'd28:begin  #1  icb_reg28 <= i_icb_cmd_wdata;end
				5'd29:begin  #1  icb_reg29 <= i_icb_cmd_wdata;end
				5'd30:begin  #1  icb_reg30 <= i_icb_cmd_wdata;end
				5'd31:begin  #1  icb_reg31 <= i_icb_cmd_wdata;end
				default: begin end 





			endcase

			#1 icb_rsp_valid_reg <= 1'b0;
			#1 icb_rsp_rdata_reg <= 'd0;
		end

		else if ( i_icb_cmd_read & i_icb_cmd_valid ) begin
			#1 icb_rsp_valid_reg <= 1'b1;

			case(reg_mux)
				5'd0:  begin  #1 icb_rsp_rdata_reg <= icb_reg0;end
				5'd1:  begin  #1 icb_rsp_rdata_reg <= icb_reg1;end
				5'd2:  begin  #1 icb_rsp_rdata_reg <= icb_reg2;end
				5'd3:  begin  #1 icb_rsp_rdata_reg <= icb_reg3;end
				5'd4:  begin  #1 icb_rsp_rdata_reg <= icb_reg4;end
				5'd5:  begin  #1 icb_rsp_rdata_reg <= icb_reg5;end
				5'd6:  begin  #1 icb_rsp_rdata_reg <= icb_reg6;end
				5'd7:  begin  #1 icb_rsp_rdata_reg <= icb_reg7;end
				5'd8:  begin  #1 icb_rsp_rdata_reg <= icb_reg8;end
				5'd9:  begin  #1 icb_rsp_rdata_reg <= icb_reg9;end
				5'd10: begin #1  icb_rsp_rdata_reg <= icb_reg10;end
				5'd11: begin #1  icb_rsp_rdata_reg <= icb_reg11;end
				5'd12: begin #1  icb_rsp_rdata_reg <= stepperPosition[31:0]; end
				5'd13: begin #1  icb_rsp_rdata_reg <= stepperPosition[63:32]; end
				5'd14: begin #1  icb_rsp_rdata_reg <= stepperPosition[95:64]; end
				5'd15: begin #1  icb_rsp_rdata_reg <= stepperPosition[127:96]; end
				5'd16: begin #1  icb_rsp_rdata_reg <= stepperPosition[159:128]; end
				5'd17: begin #1  icb_rsp_rdata_reg <= stepperPosition[191:160]; end
				5'd18: begin #1  icb_rsp_rdata_reg <= stepperPosition[223:192]; end
				5'd19: begin #1  icb_rsp_rdata_reg <= stepperPosition[255:224]; end
				5'd20: begin #1  icb_rsp_rdata_reg <= stepperPosition[287:256]; end
				5'd21: begin #1  icb_rsp_rdata_reg <= stepperPosition[319:288]; end
				5'd22: begin #1  icb_rsp_rdata_reg <= stepperPosition[351:320]; end
				5'd23: begin #1  icb_rsp_rdata_reg <= stepperPosition[383:352]; end
				5'd24: begin #1  icb_rsp_rdata_reg <= icb_reg24;end
				5'd25: begin #1  icb_rsp_rdata_reg <= icb_reg25;end
				5'd26: begin #1  icb_rsp_rdata_reg <= icb_reg26;end
				5'd27: begin #1  icb_rsp_rdata_reg <= icb_reg27;end
				5'd28: begin #1  icb_rsp_rdata_reg <= icb_reg28;end
				5'd29: begin #1  icb_rsp_rdata_reg <= icb_reg29;end
				5'd30: begin #1  icb_rsp_rdata_reg <= icb_reg30;end
				5'd31: begin #1  icb_rsp_rdata_reg <= icb_reg31;end
			default: #1 icb_rsp_rdata_reg <= 'd66;



			endcase


		end

		else if ( i_icb_rsp_ready == 1'b1 ) begin
			#1 icb_rsp_valid_reg <= 1'b0;
			#1 icb_rsp_rdata_reg <= 'd0;
		end

		else begin


		end



	end


end




assign stepCnt = {icb_reg11,icb_reg10,icb_reg9,icb_reg8,icb_reg7,icb_reg6,icb_reg5,icb_reg4,icb_reg3,icb_reg2,icb_reg1,icb_reg0};

assign currentLoopPowerOnA = icb_reg25[0];
assign currentLoopEnableA = icb_reg24[0];

assign currentLoopPowerOnB = icb_reg27[0];
assign currentLoopEnableB = icb_reg26[0];

assign stepperRST = icb_reg28[0];







wire [ 5 : 0 ] thrusterPluseA;
wire [ 5 : 0 ] thrusterPluseB;




stepper_package i_stepper_package0 
(
	.CLK(CLK100MHZ),
	.RST_n(stepperRST),
	
	.stepCnt(stepCnt[191:0]),
	.currentLoopPowerOn(currentLoopPowerOnA),
	.currentLoopEnable(currentLoopEnableA),

	.stepperPosition(stepperPosition[191:0]),

	.powerEN(powerENA),
	.thrusterPluse(thrusterPluseA),
	.thrusterDirect(thrusterDirectA)
);




stepper_package i_stepper_package1
(
	.CLK(CLK100MHZ),
	.RST_n(stepperRST),
	
	.stepCnt(stepCnt[383:192]),
	.currentLoopPowerOn(currentLoopPowerOnB),
	.currentLoopEnable(currentLoopEnableB),

	.stepperPosition(stepperPosition[383:192]),

	.powerEN(powerENB),
	.thrusterPluse(thrusterPluseB),
	.thrusterDirect(thrusterDirectB)
);






teleStop i_teleStop
(
	.CLK(CLK100MHZ),
	.RST_n(stepperRST),

	.petectIO(petectIO),

	.thrusterPluseA(thrusterPluseA),
	.safetyPluseA(safetyPluseA),
   
	.thrusterPluseB(thrusterPluseB),
	.safetyPluseB(safetyPluseB),

    .redLed(redLed),
    .greenLed(greenLed),
    .BZ(BZ)
);










endmodule