data/full_repos/permissive/150947952/scratch/cyclone10/ip/DVI_OUT/TMDS_ENCODE.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/150947952/scratch/cyclone10/ip/DVI_OUT/TMDS_ENCODE.v:124: Operator ADD expects 5 bits on the RHS, but RHS\'s REPLICATE generates 2 bits.\n                                                                                                   : ... In instance TMDS_ENCODE\n      rBIAS<=rBIAS+{rDATA_WORD[8],1\'b0}+rD9_ZERO_COUNT-rD9_ONE_COUNT;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/150947952/scratch/cyclone10/ip/DVI_OUT/TMDS_ENCODE.v:127: Operator SUB expects 5 bits on the RHS, but RHS\'s REPLICATE generates 2 bits.\n                                                                                                   : ... In instance TMDS_ENCODE\n      rBIAS<=rBIAS-{~rDATA_WORD[8], 1\'b0}+rD9_ONE_COUNT-rD9_ZERO_COUNT;\n                  ^\n%Error: Exiting due to 2 warning(s)\n'
module TMDS_ENCODE
(
  input            iCLK,
  input      [1:0] iCTL,
  input            iBLANK,
  input      [7:0] iDATA,
  output reg [9:0] oDATA
);

wire [8:0] wXORED_DATA;
wire [8:0] wXNORED_DATA;
reg  [8:0] rDATA_WORD;
wire [3:0] wONE_COUNT;
wire [3:0] wZERO_COUNT;
reg  [3:0] rD9_ONE_COUNT,rD9_ZERO_COUNT;
reg  [4:0] rBIAS;
reg  [1:0] rCTL;
reg        rBLANK;

assign  wXORED_DATA  = {1'b1,(iDATA ^ {wXORED_DATA[6:0],1'b0})};
assign  wXNORED_DATA = {1'b0,(iDATA ^~ {wXNORED_DATA[6:0],1'b0})};
assign  wONE_COUNT  = {3'b0,iDATA[0]}+
                      {3'b0,iDATA[1]}+
                      {3'b0,iDATA[2]}+
                      {3'b0,iDATA[3]}+
                      {3'b0,iDATA[4]}+
                      {3'b0,iDATA[5]}+
                      {3'b0,iDATA[6]}+
                      {3'b0,iDATA[7]};


always @(posedge iCLK)
begin

  rCTL <= iCTL;
  rBLANK <= iBLANK;
  
  if ((wONE_COUNT>4) || ((wONE_COUNT==4) && (iDATA[0]==0)))
  begin
    rDATA_WORD <= wXNORED_DATA;
    rD9_ONE_COUNT <= 
                 {3'b0,wXNORED_DATA[0]}+
                 {3'b0,wXNORED_DATA[1]}+
                 {3'b0,wXNORED_DATA[2]}+
                 {3'b0,wXNORED_DATA[3]}+
                 {3'b0,wXNORED_DATA[4]}+
                 {3'b0,wXNORED_DATA[5]}+
                 {3'b0,wXNORED_DATA[6]}+
                 {3'b0,wXNORED_DATA[7]};
    rD9_ZERO_COUNT <= 8-
                 {3'b0,wXNORED_DATA[0]}-
                 {3'b0,wXNORED_DATA[1]}-
                 {3'b0,wXNORED_DATA[2]}-
                 {3'b0,wXNORED_DATA[3]}-
                 {3'b0,wXNORED_DATA[4]}-
                 {3'b0,wXNORED_DATA[5]}-
                 {3'b0,wXNORED_DATA[6]}-
                 {3'b0,wXNORED_DATA[7]};

  end else begin
    rDATA_WORD <= wXORED_DATA;
    rD9_ONE_COUNT <= 
                 {3'b0,wXORED_DATA[0]}+
                 {3'b0,wXORED_DATA[1]}+
                 {3'b0,wXORED_DATA[2]}+
                 {3'b0,wXORED_DATA[3]}+
                 {3'b0,wXORED_DATA[4]}+
                 {3'b0,wXORED_DATA[5]}+
                 {3'b0,wXORED_DATA[6]}+
                 {3'b0,wXORED_DATA[7]};
    rD9_ZERO_COUNT <= 8-
                 {3'b0,wXORED_DATA[0]}-
                 {3'b0,wXORED_DATA[1]}-
                 {3'b0,wXORED_DATA[2]}-
                 {3'b0,wXORED_DATA[3]}-
                 {3'b0,wXORED_DATA[4]}-
                 {3'b0,wXORED_DATA[5]}-
                 {3'b0,wXORED_DATA[6]}-
                 {3'b0,wXORED_DATA[7]};
  end

  if (rBLANK)
  begin
    case (rCTL)
      0: oDATA <= 10'b1101010100;
      1: oDATA <= 10'b0010101011;
      2: oDATA <= 10'b0101010100;
      3: oDATA <= 10'b1010101011;
    endcase
    rBIAS <=5'd0;
  end else begin
    if ((rBIAS==0) || (rD9_ONE_COUNT==rD9_ZERO_COUNT))
    begin
      if (rDATA_WORD[8]) begin
        oDATA<= {2'b01,rDATA_WORD[7:0]};
        rBIAS<=rBIAS+rD9_ONE_COUNT-rD9_ZERO_COUNT;
      end else begin
        oDATA<= {2'b10,~rDATA_WORD[7:0]};
        rBIAS<=rBIAS-rD9_ONE_COUNT+rD9_ZERO_COUNT;
      end
    end else if (!rBIAS[4] && (rD9_ONE_COUNT>rD9_ZERO_COUNT) || 
                  rBIAS[4] && (rD9_ONE_COUNT<rD9_ZERO_COUNT)  ) begin
      oDATA<= {1'b1,rDATA_WORD[8],~rDATA_WORD[7:0]};
      rBIAS<=rBIAS+{rDATA_WORD[8],1'b0}+rD9_ZERO_COUNT-rD9_ONE_COUNT;
    end else begin
      oDATA<= {1'b0,rDATA_WORD};
      rBIAS<=rBIAS-{~rDATA_WORD[8], 1'b0}+rD9_ONE_COUNT-rD9_ZERO_COUNT;
    end
  end
  
end

endmodule
module TMDS_ENCODE
(
  input            iCLK,
  input      [1:0] iCTL,
  input            iBLANK,
  input      [7:0] iDATA,
  output reg [9:0] oDATA
);


wire [8:0] wXORED_DATA;
wire [8:0] wXNORED_DATA;
reg  [8:0] rDATA_WORD;
wire [3:0] wONE_COUNT;
wire [3:0] wZERO_COUNT;
reg  [3:0] rD9_ONE_COUNT,rD9_ZERO_COUNT;
reg  [4:0] rBIAS;
reg  [1:0] rCTL;
reg        rBLANK;

assign  wXORED_DATA  = {1'b1,(iDATA ^ {wXORED_DATA[6:0],1'b0})};
assign  wXNORED_DATA = {1'b0,(iDATA ^~ {wXNORED_DATA[6:0],1'b0})};
assign  wONE_COUNT  = {3'b0,iDATA[0]}+
                      {3'b0,iDATA[1]}+
                      {3'b0,iDATA[2]}+
                      {3'b0,iDATA[3]}+
                      {3'b0,iDATA[4]}+
                      {3'b0,iDATA[5]}+
                      {3'b0,iDATA[6]}+
                      {3'b0,iDATA[7]};


always @(posedge iCLK)
begin

  rCTL <= iCTL;
  rBLANK <= iBLANK;
  
  if ((wONE_COUNT>4) || ((wONE_COUNT==4) && (iDATA[0]==0)))
  begin
    rDATA_WORD <= wXNORED_DATA;
    rD9_ONE_COUNT <= 
                 {3'b0,wXNORED_DATA[0]}+
                 {3'b0,wXNORED_DATA[1]}+
                 {3'b0,wXNORED_DATA[2]}+
                 {3'b0,wXNORED_DATA[3]}+
                 {3'b0,wXNORED_DATA[4]}+
                 {3'b0,wXNORED_DATA[5]}+
                 {3'b0,wXNORED_DATA[6]}+
                 {3'b0,wXNORED_DATA[7]};
    rD9_ZERO_COUNT <= 8-
                 {3'b0,wXNORED_DATA[0]}-
                 {3'b0,wXNORED_DATA[1]}-
                 {3'b0,wXNORED_DATA[2]}-
                 {3'b0,wXNORED_DATA[3]}-
                 {3'b0,wXNORED_DATA[4]}-
                 {3'b0,wXNORED_DATA[5]}-
                 {3'b0,wXNORED_DATA[6]}-
                 {3'b0,wXNORED_DATA[7]};

  end else begin
    rDATA_WORD <= wXORED_DATA;
    rD9_ONE_COUNT <= 
                 {3'b0,wXORED_DATA[0]}+
                 {3'b0,wXORED_DATA[1]}+
                 {3'b0,wXORED_DATA[2]}+
                 {3'b0,wXORED_DATA[3]}+
                 {3'b0,wXORED_DATA[4]}+
                 {3'b0,wXORED_DATA[5]}+
                 {3'b0,wXORED_DATA[6]}+
                 {3'b0,wXORED_DATA[7]};
    rD9_ZERO_COUNT <= 8-
                 {3'b0,wXORED_DATA[0]}-
                 {3'b0,wXORED_DATA[1]}-
                 {3'b0,wXORED_DATA[2]}-
                 {3'b0,wXORED_DATA[3]}-
                 {3'b0,wXORED_DATA[4]}-
                 {3'b0,wXORED_DATA[5]}-
                 {3'b0,wXORED_DATA[6]}-
                 {3'b0,wXORED_DATA[7]};
  end

  if (rBLANK)
  begin
    case (rCTL)
      0: oDATA <= 10'b1101010100;
      1: oDATA <= 10'b0010101011;
      2: oDATA <= 10'b0101010100;
      3: oDATA <= 10'b1010101011;
    endcase
    rBIAS <=5'd0;
  end else begin
    if ((rBIAS==0) || (rD9_ONE_COUNT==rD9_ZERO_COUNT))
    begin
      if (rDATA_WORD[8]) begin
        oDATA<= {2'b01,rDATA_WORD[7:0]};
        rBIAS<=rBIAS+rD9_ONE_COUNT-rD9_ZERO_COUNT;
      end else begin
        oDATA<= {2'b10,~rDATA_WORD[7:0]};
        rBIAS<=rBIAS-rD9_ONE_COUNT+rD9_ZERO_COUNT;
      end
    end else if (!rBIAS[4] && (rD9_ONE_COUNT>rD9_ZERO_COUNT) || 
                  rBIAS[4] && (rD9_ONE_COUNT<rD9_ZERO_COUNT)  ) begin
      oDATA<= {1'b1,rDATA_WORD[8],~rDATA_WORD[7:0]};
      rBIAS<=rBIAS+{rDATA_WORD[8],1'b0}+rD9_ZERO_COUNT-rD9_ONE_COUNT;
    end else begin
      oDATA<= {1'b0,rDATA_WORD};
      rBIAS<=rBIAS-{~rDATA_WORD[8], 1'b0}+rD9_ONE_COUNT-rD9_ZERO_COUNT;
    end
  end
  
end

endmodule