data/full_repos/permissive/181013988/src/main_mem.v
data/verilator_xmls/c92f2f90-a641-49ce-8fdd-69b210c2d55b.xml
module main_mem(
    input clk,
    input [31:0] addr,
    input rd_enbl,
    input wrt_enbl,
    input [31:0] dat_in,
    output reg [31:0] dat_out
);

    reg [31:0] mem [1024*1024*1024*4-1:0];

    always @(addr) begin
        dat_out = mem[addr];
    end

    always @(dat_in) begin
        if(wrt_enbl & !rd_enbl)
            mem[addr] = dat_in;
    end

endmodule
module main_mem(
    input clk,
    input [31:0] addr,
    input rd_enbl,
    input wrt_enbl,
    input [31:0] dat_in,
    output reg [31:0] dat_out
);


    reg [31:0] mem [1024*1024*1024*4-1:0];

    always @(addr) begin
        dat_out = mem[addr];
    end

    always @(dat_in) begin
        if(wrt_enbl & !rd_enbl)
            mem[addr] = dat_in;
    end

endmodule