data/full_repos/permissive/122560566/FPU.srcs/sim_1/new/regfile_unittest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/122560566/FPU.srcs/sim_1/new/regfile_unittest.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #7; \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/122560566/FPU.srcs/sim_1/new/regfile_unittest.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/122560566/FPU.srcs/sim_1/new/regfile_unittest.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/122560566/FPU.srcs/sim_1/new/regfile_unittest.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/122560566/FPU.srcs/sim_1/new/regfile_unittest.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/122560566/FPU.srcs/sim_1/new/regfile_unittest.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/122560566/FPU.srcs/sim_1/new/regfile_unittest.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #10; I_we = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/122560566/FPU.srcs/sim_1/new/regfile_unittest.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/122560566/FPU.srcs/sim_1/new/regfile_unittest.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #5; I_clk = ~I_clk;\n        ^\n%Error: data/full_repos/permissive/122560566/FPU.srcs/sim_1/new/regfile_unittest.v:38: Cannot find file containing module: \'reg_file\'\n    reg_file unittest (I_selA, I_selB, I_selD, I_dataD, I_clk, I_en, I_we, O_dataA, O_dataB);\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122560566/FPU.srcs/sim_1/new,data/full_repos/permissive/122560566/reg_file\n             data/full_repos/permissive/122560566/FPU.srcs/sim_1/new,data/full_repos/permissive/122560566/reg_file.v\n             data/full_repos/permissive/122560566/FPU.srcs/sim_1/new,data/full_repos/permissive/122560566/reg_file.sv\n             reg_file\n             reg_file.v\n             reg_file.sv\n             obj_dir/reg_file\n             obj_dir/reg_file.v\n             obj_dir/reg_file.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module regfile_unittest(

    );
    
    reg [2:0] I_selA;
    reg [2:0] I_selB;
    reg [2:0] I_selD;
    reg [15:0] I_dataD;
    reg I_clk;
    reg I_en;
    reg I_we;
    wire [15:0] O_dataA;
    wire [15:0] O_dataB;
    

    reg_file unittest (I_selA, I_selB, I_selD, I_dataD, I_clk, I_en, I_we, O_dataA, O_dataB);
    

  
    initial begin

        I_clk = 1'b0;
        I_en = 1'b0;
        I_we = 1'b0;
        
        I_selA = 0;
        I_selB = 0;
        I_selD = 0;
        I_dataD = 0;
        

        #7; 
        I_en = 1'b1;
        
        I_selA = 3'b000;
        I_selB = 3'b001;
        I_selD = 3'b000;
        
        I_dataD = 16'hFFFF;
        I_we = 1'b1; 
        
        #10;
        I_we = 1'b0;
        I_selD = 3'b010;
        I_dataD = 16'h2222;
        
        #10;
        I_we = 1'b1;
        
        #10;
        I_dataD = 16'h3333;
        
        #10
        I_we = 1'b0;
        I_selD = 3'b000;
        I_dataD = 16'hFEED;
        
        #10;
        I_selD = 3'b100;
        I_dataD = 16'h4444;
        
        #10; I_we = 1'b1;
        
        #50;
        I_selA = 3'b100;
        I_selB = 3'b100;
    end
    

    always begin
        #5; I_clk = ~I_clk;
    end
endmodule
module regfile_unittest(

    );

    
    reg [2:0] I_selA;
    reg [2:0] I_selB;
    reg [2:0] I_selD;
    reg [15:0] I_dataD;
    reg I_clk;
    reg I_en;
    reg I_we;
    wire [15:0] O_dataA;
    wire [15:0] O_dataB;
    

    reg_file unittest (I_selA, I_selB, I_selD, I_dataD, I_clk, I_en, I_we, O_dataA, O_dataB);
    

  
    initial begin

        I_clk = 1'b0;
        I_en = 1'b0;
        I_we = 1'b0;
        
        I_selA = 0;
        I_selB = 0;
        I_selD = 0;
        I_dataD = 0;
        

        #7; 
        I_en = 1'b1;
        
        I_selA = 3'b000;
        I_selB = 3'b001;
        I_selD = 3'b000;
        
        I_dataD = 16'hFFFF;
        I_we = 1'b1; 
        
        #10;
        I_we = 1'b0;
        I_selD = 3'b010;
        I_dataD = 16'h2222;
        
        #10;
        I_we = 1'b1;
        
        #10;
        I_dataD = 16'h3333;
        
        #10
        I_we = 1'b0;
        I_selD = 3'b000;
        I_dataD = 16'hFEED;
        
        #10;
        I_selD = 3'b100;
        I_dataD = 16'h4444;
        
        #10; I_we = 1'b1;
        
        #50;
        I_selA = 3'b100;
        I_selB = 3'b100;
    end
    

    always begin
        #5; I_clk = ~I_clk;
    end
endmodule