data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/PISO/piso.v
data/verilator_xmls/0e9aee61-b695-418c-ab0f-a2f27a4d2ebd.xml
module piso
#(
    parameter integer DATA_IN_WIDTH  = 64,
    parameter integer DATA_OUT_WIDTH = 16
)(
    input  wire                         CLK,
    input  wire                         RESET,
    input  wire                         LOAD,
    input  wire                         SHIFT,
    input  wire [DATA_IN_WIDTH -1 : 0]  DATA_IN,
    output wire [DATA_OUT_WIDTH -1 : 0] DATA_OUT
);




    localparam integer NUM_SHIFTS = DATA_IN_WIDTH / DATA_OUT_WIDTH;





    reg [DATA_IN_WIDTH -1 : 0]  serial;


assign DATA_OUT = serial [DATA_OUT_WIDTH-1:0];

always @(posedge CLK)
begin: DATA_SHIFT
    if (RESET)
        serial <= 0;
    else begin
        if (LOAD)
            serial <= DATA_IN;
        else if (SHIFT)

            serial <= serial >> DATA_OUT_WIDTH;
    end
end

endmodule
module piso
#(
    parameter integer DATA_IN_WIDTH  = 64,
    parameter integer DATA_OUT_WIDTH = 16
)(
    input  wire                         CLK,
    input  wire                         RESET,
    input  wire                         LOAD,
    input  wire                         SHIFT,
    input  wire [DATA_IN_WIDTH -1 : 0]  DATA_IN,
    output wire [DATA_OUT_WIDTH -1 : 0] DATA_OUT
);





    localparam integer NUM_SHIFTS = DATA_IN_WIDTH / DATA_OUT_WIDTH;





    reg [DATA_IN_WIDTH -1 : 0]  serial;


assign DATA_OUT = serial [DATA_OUT_WIDTH-1:0];

always @(posedge CLK)
begin: DATA_SHIFT
    if (RESET)
        serial <= 0;
    else begin
        if (LOAD)
            serial <= DATA_IN;
        else if (SHIFT)

            serial <= serial >> DATA_OUT_WIDTH;
    end
end

endmodule