data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:1: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Forward/Mem,data/full_repos/permissive/131921633/Data/Control/Control.v\n             data/full_repos/permissive/131921633/tv/Mips/Forward/Mem,data/full_repos/permissive/131921633/Data/Control/Control.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Forward/Mem,data/full_repos/permissive/131921633/Data/Control/Control.v.sv\n             Data/Control/Control.v\n             Data/Control/Control.v.v\n             Data/Control/Control.v.sv\n             obj_dir/Data/Control/Control.v\n             obj_dir/Data/Control/Control.v.v\n             obj_dir/Data/Control/Control.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:2: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:3: Cannot find include file: Mips/Type/RegAddr.v\n`include "Mips/Type/RegAddr.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:4: Cannot find include file: Mips/Control/Signal/Register/Signal/WriteDataSource.v\n`include "Mips/Control/Signal/Register/Signal/WriteDataSource.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:9: Define or directive not defined: \'`Mips_Type_Word_T\'\n ( `Mips_Type_Word_T (output) memData\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:9: syntax error, unexpected \'(\', expecting \'[\'\n ( `Mips_Type_Word_T (output) memData\n                      ^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:10: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (input) pipeMem_MemAddr\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:11: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (input) pipeReg_MemAddr\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:12: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (input) pipeMem_MemData\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:13: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (input) pipeReg_MemData\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:14: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteDataSource_T\'\n , `Mips_Control_Signal_Register_Signal_WriteDataSource_T (input) pipeReg_WriteDataSource\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:15: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n , `Mips_Type_RegAddr_T (input) pipeMem_Read1Addr\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:16: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n , `Mips_Type_RegAddr_T (input) pipeMem_Read2Addr\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Forward/Mem/forward.v:17: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n , `Mips_Type_RegAddr_T (input) pipeReg_WriteAddr\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module Mips_Forward_Mem_forward #
	( parameter DIRECT = 1
	)
	( `Mips_Type_Word_T (output) memData
	, `Mips_Type_Word_T (input) pipeMem_MemAddr
	, `Mips_Type_Word_T (input) pipeReg_MemAddr
	, `Mips_Type_Word_T (input) pipeMem_MemData
	, `Mips_Type_Word_T (input) pipeReg_MemData
	, `Mips_Control_Signal_Register_Signal_WriteDataSource_T (input) pipeReg_WriteDataSource
	, `Mips_Type_RegAddr_T (input) pipeMem_Read1Addr
	, `Mips_Type_RegAddr_T (input) pipeMem_Read2Addr
	, `Mips_Type_RegAddr_T (input) pipeReg_WriteAddr
	);

Mips_Forward_Ex_port1 #
	( .DIRECT (DIRECT)
	) PORT1
	( .port (regPort1)
	, .pipeEx_RegPorts   (pipeEx_RegPorts)
	, .pipeMem_RegPorts  (pipeMem_RegPorts)
	, .pipeReg_RegPorts  (pipeReg_RegPorts)
	, .pipeMem_AluResult (pipeMem_AluResult)
	, .pipeMem_PcAddr    (pipeMem_PcAddr)
	, .pipeReg_WriteData (pipeReg_WriteData)
	, .pipeEx_RegPort1   (pipeEx_RegPort1)
	);

Mips_Forward_Ex_port2 #
	( .DIRECT (DIRECT)
	) PORT2
	( .port (regPort2)
	, .pipeEx_RegPorts   (pipeEx_RegPorts)
	, .pipeMem_RegPorts  (pipeMem_RegPorts)
	, .pipeReg_RegPorts  (pipeReg_RegPorts)
	, .pipeMem_AluResult (pipeMem_AluResult)
	, .pipeMem_PcAddr    (pipeMem_PcAddr)
	, .pipeReg_WriteData (pipeReg_WriteData)
	, .pipeEx_RegPort2   (pipeEx_RegPort2)
	);

endmodule
module Mips_Forward_Mem_forward #
	( parameter DIRECT = 1
	)
	( `Mips_Type_Word_T (output) memData
	, `Mips_Type_Word_T (input) pipeMem_MemAddr
	, `Mips_Type_Word_T (input) pipeReg_MemAddr
	, `Mips_Type_Word_T (input) pipeMem_MemData
	, `Mips_Type_Word_T (input) pipeReg_MemData
	, `Mips_Control_Signal_Register_Signal_WriteDataSource_T (input) pipeReg_WriteDataSource
	, `Mips_Type_RegAddr_T (input) pipeMem_Read1Addr
	, `Mips_Type_RegAddr_T (input) pipeMem_Read2Addr
	, `Mips_Type_RegAddr_T (input) pipeReg_WriteAddr
	);


Mips_Forward_Ex_port1 #
	( .DIRECT (DIRECT)
	) PORT1
	( .port (regPort1)
	, .pipeEx_RegPorts   (pipeEx_RegPorts)
	, .pipeMem_RegPorts  (pipeMem_RegPorts)
	, .pipeReg_RegPorts  (pipeReg_RegPorts)
	, .pipeMem_AluResult (pipeMem_AluResult)
	, .pipeMem_PcAddr    (pipeMem_PcAddr)
	, .pipeReg_WriteData (pipeReg_WriteData)
	, .pipeEx_RegPort1   (pipeEx_RegPort1)
	);

Mips_Forward_Ex_port2 #
	( .DIRECT (DIRECT)
	) PORT2
	( .port (regPort2)
	, .pipeEx_RegPorts   (pipeEx_RegPorts)
	, .pipeMem_RegPorts  (pipeMem_RegPorts)
	, .pipeReg_RegPorts  (pipeReg_RegPorts)
	, .pipeMem_AluResult (pipeMem_AluResult)
	, .pipeMem_PcAddr    (pipeMem_PcAddr)
	, .pipeReg_WriteData (pipeReg_WriteData)
	, .pipeEx_RegPort2   (pipeEx_RegPort2)
	);

endmodule