data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:126: Multiple top level modules\n                                                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                          : ... Top module \'okHost\'\nmodule okHost\n       ^~~~~~\n                                                                                                                          : ... Top module \'okWireIn\'\nmodule okWireIn(ok1, ep_addr, ep_dataout);\n       ^~~~~~~~\n                                                                                                                          : ... Top module \'okWireOut\'\nmodule okWireOut(ok1, ok2, ep_addr, ep_datain);\n       ^~~~~~~~~\n                                                                                                                          : ... Top module \'okTriggerIn\'\nmodule okTriggerIn(ok1, ep_addr, ep_clk, ep_trigger);\n       ^~~~~~~~~~~\n                                                                                                                          : ... Top module \'okTriggerOut\'\nmodule okTriggerOut(ok1, ok2, ep_addr, ep_clk, ep_trigger);\n       ^~~~~~~~~~~~\n                                                                                                                          : ... Top module \'okPipeIn\'\nmodule okPipeIn(ok1, ok2, ep_addr, ep_write, ep_dataout);\n       ^~~~~~~~\n                                                                                                                          : ... Top module \'okPipeOut\'\nmodule okPipeOut(ok1, ok2, ep_addr, ep_read, ep_datain);\n       ^~~~~~~~~\n                                                                                                                          : ... Top module \'okBTPipeIn\'\nmodule okBTPipeIn(ok1, ok2, ep_addr, ep_write, ep_blockstrobe, ep_dataout, ep_ready);\n       ^~~~~~~~~~\n                                                                                                                          : ... Top module \'okBTPipeOut\'\nmodule okBTPipeOut(ok1, ok2, ep_addr, ep_read, ep_blockstrobe, ep_datain, ep_ready);\n       ^~~~~~~~~~~\n                                                                                                                          : ... Top module \'okWireOR\'\nmodule okWireOR # (parameter N = 1) (\n       ^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:40: Cannot find file containing module: \'DCM_SP\'\n DCM_SP hi_dcm (.CLKIN     (hi_in[0]),\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150,data/full_repos/permissive/120539939/DCM_SP\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150,data/full_repos/permissive/120539939/DCM_SP.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150,data/full_repos/permissive/120539939/DCM_SP.sv\n             DCM_SP\n             DCM_SP.v\n             DCM_SP.sv\n             obj_dir/DCM_SP\n             obj_dir/DCM_SP.v\n             obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:48: Cannot find file containing module: \'BUFG\'\n BUFG clkout1_buf (.I(dcm_clk0), .O(ti_clk));\n ^~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:49: Cannot find file containing module: \'FDS\'\n FDS flop1(.D(1\'b0), .C(hi_in[0]), .Q(rst1), .S(1\'b0));\n ^~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:50: Cannot find file containing module: \'FD\'\n FD flop2(.D(rst1), .C(hi_in[0]), .Q(rst2));\n ^~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:51: Cannot find file containing module: \'FD\'\n FD flop3(.D(rst2), .C(hi_in[0]), .Q(rst3));\n ^~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:52: Cannot find file containing module: \'FD\'\n FD flop4(.D(rst3), .C(hi_in[0]), .Q(rst4));\n ^~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:60: Cannot find file containing module: \'IOBUF\'\n   IOBUF iobf0 (\n   ^~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:68: Cannot find file containing module: \'IODELAY2\'\n   IODELAY2 #(\n   ^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:79: Cannot find file containing module: \'FDRE\'\n   FDRE fdrein0 (\n   ^~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:89: Cannot find file containing module: \'FDRE\'\n   FDRE fdreout0 (\n   ^~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:98: Cannot find file containing module: \'FDRE\'\n   FDRE fdreout1 (\n   ^~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:109: Cannot find file containing module: \'OBUF\'\n OBUF obuf0(.I(okCH[0]), .O(hi_out[0]));\n ^~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:110: Cannot find file containing module: \'OBUF\'\n OBUF obuf1(.I(okCH[1]), .O(hi_out[1]));\n ^~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/FrontPanelHDL/XEM6010-LX150/okLibrary.v:111: Cannot find file containing module: \'IOBUF\'\n IOBUF tbuf(.I(okCH[19]), .O(okHC[24]), .T(okCH[20]), .IO(hi_aa));\n ^~~~~\n%Error: Exiting due to 14 error(s), 1 warning(s)\n'
module okHost
	(
	input  wire [7:0]  hi_in,
	output wire [1:0]  hi_out,
	inout  wire [15:0] hi_inout,
	inout  wire        hi_aa,
	output wire        ti_clk,
	output wire [30:0] ok1,
	input  wire [16:0] ok2
	);

	wire [24:0] okHC;
	wire [20:0] okCH;
		
	wire [15:0] iobf0_hi_datain;
	wire [15:0] iodly0_datain;
	wire [15:0] hi_datain;
	
	wire [15:0] fdreout0_hi_dataout;
	wire [15:0] fdreout1_hi_drive; 
	
	assign okHC[0]     = ti_clk;
	assign okHC[7:1]   = hi_in[7:1];
	assign okHC[23:8]  = hi_datain;


	wire dcm_clk0, rstin, rst1, rst2, rst3, rst4; 

	DCM_SP hi_dcm (.CLKIN     (hi_in[0]),
	               .CLKFB     (ti_clk),
	               .CLK0      (dcm_clk0),
	               .PSCLK     (1'b0),
	               .PSEN      (1'b0),
	               .PSINCDEC  (1'b0),
	               .RST       (rstin),
	               .DSSEN     (1'b0));
	BUFG clkout1_buf (.I(dcm_clk0), .O(ti_clk));
	FDS flop1(.D(1'b0), .C(hi_in[0]), .Q(rst1), .S(1'b0));
	FD flop2(.D(rst1), .C(hi_in[0]), .Q(rst2));
	FD flop3(.D(rst2), .C(hi_in[0]), .Q(rst3));
	FD flop4(.D(rst3), .C(hi_in[0]), .Q(rst4));
	assign rstin = (rst2 | rst3 | rst4);
	

	genvar i;
	generate
		for (i=0; i<16; i=i+1) begin : delays
			
			IOBUF iobf0 (
				.IO(hi_inout[i]),
				.I(fdreout0_hi_dataout[i]), 
				.O(iobf0_hi_datain[i]), 
				.T(fdreout1_hi_drive[i]) 
			);


			IODELAY2 #(
				.IDELAY_TYPE("FIXED"),
				.IDELAY_VALUE(100),
				.DELAY_SRC("IDATAIN")
			) iodelay_inst (
				.IDATAIN(iobf0_hi_datain[i]),
				.DATAOUT(iodly0_datain[i]),
				.T(1'b1)
			);
  
			(* IOB = "true" *)
			FDRE fdrein0 (
				.D              (iodly0_datain[i]),
				.C              (ti_clk),
				.CE             (1'b1),
				.R              (1'b0),
				.Q              (hi_datain[i])
			);


			(* IOB = "true" *)
			FDRE fdreout0 (
				.D              (okCH[i+3]),
				.C              (ti_clk),
				.CE             (1'b1),
				.R              (1'b0),
				.Q              (fdreout0_hi_dataout[i])
			);

			(* IOB = "true" *)
			FDRE fdreout1 (
				.D              (~okCH[2]),
				.C              (ti_clk),
				.CE             (1'b1),
				.R              (1'b0),
				.Q              (fdreout1_hi_drive[i])
			);

		end
	endgenerate
	
	OBUF obuf0(.I(okCH[0]), .O(hi_out[0]));
	OBUF obuf1(.I(okCH[1]), .O(hi_out[1]));
	IOBUF tbuf(.I(okCH[19]), .O(okHC[24]), .T(okCH[20]), .IO(hi_aa));

	okCoreHarness core0(.okHC(okHC), .okCH(okCH), .ok1(ok1), .ok2(ok2));
endmodule
module okHost
	(
	input  wire [7:0]  hi_in,
	output wire [1:0]  hi_out,
	inout  wire [15:0] hi_inout,
	inout  wire        hi_aa,
	output wire        ti_clk,
	output wire [30:0] ok1,
	input  wire [16:0] ok2
	);


	wire [24:0] okHC;
	wire [20:0] okCH;
		
	wire [15:0] iobf0_hi_datain;
	wire [15:0] iodly0_datain;
	wire [15:0] hi_datain;
	
	wire [15:0] fdreout0_hi_dataout;
	wire [15:0] fdreout1_hi_drive; 
	
	assign okHC[0]     = ti_clk;
	assign okHC[7:1]   = hi_in[7:1];
	assign okHC[23:8]  = hi_datain;


	wire dcm_clk0, rstin, rst1, rst2, rst3, rst4; 

	DCM_SP hi_dcm (.CLKIN     (hi_in[0]),
	               .CLKFB     (ti_clk),
	               .CLK0      (dcm_clk0),
	               .PSCLK     (1'b0),
	               .PSEN      (1'b0),
	               .PSINCDEC  (1'b0),
	               .RST       (rstin),
	               .DSSEN     (1'b0));
	BUFG clkout1_buf (.I(dcm_clk0), .O(ti_clk));
	FDS flop1(.D(1'b0), .C(hi_in[0]), .Q(rst1), .S(1'b0));
	FD flop2(.D(rst1), .C(hi_in[0]), .Q(rst2));
	FD flop3(.D(rst2), .C(hi_in[0]), .Q(rst3));
	FD flop4(.D(rst3), .C(hi_in[0]), .Q(rst4));
	assign rstin = (rst2 | rst3 | rst4);
	

	genvar i;
	generate
		for (i=0; i<16; i=i+1) begin : delays
			
			IOBUF iobf0 (
				.IO(hi_inout[i]),
				.I(fdreout0_hi_dataout[i]), 
				.O(iobf0_hi_datain[i]), 
				.T(fdreout1_hi_drive[i]) 
			);


			IODELAY2 #(
				.IDELAY_TYPE("FIXED"),
				.IDELAY_VALUE(100),
				.DELAY_SRC("IDATAIN")
			) iodelay_inst (
				.IDATAIN(iobf0_hi_datain[i]),
				.DATAOUT(iodly0_datain[i]),
				.T(1'b1)
			);
  
			(* IOB = "true" *)
			FDRE fdrein0 (
				.D              (iodly0_datain[i]),
				.C              (ti_clk),
				.CE             (1'b1),
				.R              (1'b0),
				.Q              (hi_datain[i])
			);


			(* IOB = "true" *)
			FDRE fdreout0 (
				.D              (okCH[i+3]),
				.C              (ti_clk),
				.CE             (1'b1),
				.R              (1'b0),
				.Q              (fdreout0_hi_dataout[i])
			);

			(* IOB = "true" *)
			FDRE fdreout1 (
				.D              (~okCH[2]),
				.C              (ti_clk),
				.CE             (1'b1),
				.R              (1'b0),
				.Q              (fdreout1_hi_drive[i])
			);

		end
	endgenerate
	
	OBUF obuf0(.I(okCH[0]), .O(hi_out[0]));
	OBUF obuf1(.I(okCH[1]), .O(hi_out[1]));
	IOBUF tbuf(.I(okCH[19]), .O(okHC[24]), .T(okCH[20]), .IO(hi_aa));

	okCoreHarness core0(.okHC(okHC), .okCH(okCH), .ok1(ok1), .ok2(ok2));
endmodule