data/full_repos/permissive/115920613/rtl/cpu/arlet_6502.v
1: b"%Error: data/full_repos/permissive/115920613/rtl/cpu/arlet_6502.v:43: Cannot find file containing module: 'cpu'\n    cpu arlet_cpu(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/115920613/rtl/cpu,data/full_repos/permissive/115920613/cpu\n             data/full_repos/permissive/115920613/rtl/cpu,data/full_repos/permissive/115920613/cpu.v\n             data/full_repos/permissive/115920613/rtl/cpu,data/full_repos/permissive/115920613/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s)\n"
module arlet_6502(
    input clk,
    input enable,
    input rst,
    output reg [15:0] ab,
    input [7:0] dbi,
    output reg [7:0] dbo,
    output reg we,
    input irq_n,
    input nmi_n,
    input ready,
    output [15:0] pc_monitor
);

    wire [7:0] dbo_c;
    wire [15:0] ab_c;
    wire we_c;

    cpu arlet_cpu(
        .clk(clk),
        .reset(rst),
        .AB(ab_c),
        .DI(dbi),
        .DO(dbo_c),
        .WE(we_c),
        .IRQ(~irq_n),
        .NMI(~nmi_n),
        .RDY(ready),
        .PC_MONITOR(pc_monitor)
    );

    always @(posedge clk or posedge rst)
    begin
        if (rst)
        begin
            ab <= 16'd0;
            dbo <= 8'd0;
            we <= 1'b0;
        end
        else
            if (enable)
            begin
                ab <= ab_c;
                dbo <= dbo_c;
                we <= we_c;
            end
    end
endmodule
module arlet_6502(
    input clk,
    input enable,
    input rst,
    output reg [15:0] ab,
    input [7:0] dbi,
    output reg [7:0] dbo,
    output reg we,
    input irq_n,
    input nmi_n,
    input ready,
    output [15:0] pc_monitor
);


    wire [7:0] dbo_c;
    wire [15:0] ab_c;
    wire we_c;

    cpu arlet_cpu(
        .clk(clk),
        .reset(rst),
        .AB(ab_c),
        .DI(dbi),
        .DO(dbo_c),
        .WE(we_c),
        .IRQ(~irq_n),
        .NMI(~nmi_n),
        .RDY(ready),
        .PC_MONITOR(pc_monitor)
    );

    always @(posedge clk or posedge rst)
    begin
        if (rst)
        begin
            ab <= 16'd0;
            dbo <= 8'd0;
            we <= 1'b0;
        end
        else
            if (enable)
            begin
                ab <= ab_c;
                dbo <= dbo_c;
                we <= we_c;
            end
    end
endmodule