data/full_repos/permissive/16552133/src/verilog/program_counter.v
data/verilator_xmls/a0edb080-c635-445a-a540-70b686de9f19.xml
module program_counter(clk,in,out,ctrl,clr);
	input clk,clr;
	input [1:0] ctrl;
	input [5:0] in;
	output reg [5:0]out;
	
	initial begin
		out <= 0;
	end
	
	always @(posedge clk)
	begin
		if(clr)
			out <= 0;
		else begin
			case(ctrl)
			0 : out <= out;
			1 : out <= (out + 1);
			2 : out <= in;
			default: out <= out;
			endcase
		end
	end
endmodule
module program_counter(clk,in,out,ctrl,clr);

	input clk,clr;
	input [1:0] ctrl;
	input [5:0] in;
	output reg [5:0]out;
	
	initial begin
		out <= 0;
	end
	
	always @(posedge clk)
	begin
		if(clr)
			out <= 0;
		else begin
			case(ctrl)
			0 : out <= out;
			1 : out <= (out + 1);
			2 : out <= in;
			default: out <= out;
			endcase
		end
	end
endmodule