data/full_repos/permissive/110143902/projects/reg_async_reset/src/design/reg.v
 line:22: before: "reg"
1: b"%Error: data/full_repos/permissive/110143902/projects/reg_async_reset/src/design/reg.v:36: Cannot find file containing module: 'd_trig'\n            d_trig #(\n            ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110143902/projects/reg_async_reset/src/design,data/full_repos/permissive/110143902/d_trig\n             data/full_repos/permissive/110143902/projects/reg_async_reset/src/design,data/full_repos/permissive/110143902/d_trig.v\n             data/full_repos/permissive/110143902/projects/reg_async_reset/src/design,data/full_repos/permissive/110143902/d_trig.sv\n             d_trig\n             d_trig.v\n             d_trig.sv\n             obj_dir/d_trig\n             obj_dir/d_trig.v\n             obj_dir/d_trig.sv\n%Error: Exiting due to 1 error(s)\n"
module register (
    D, C, CLR,
    Q
    );


    parameter                          DATA_WIDTH = 4;
    parameter reg [DATA_WIDTH - 1 : 0] INIT_VAL   = 0;
    parameter                          CLEAR_VAL  = 1;


    input wire [DATA_WIDTH - 1 : 0] D;
    input wire C, CLR;
    output wire [DATA_WIDTH - 1 : 0] Q;


    genvar i;


    generate
        for(i = 0; i < DATA_WIDTH; i = i + 1) begin
            d_trig #(
                .INIT_VAL(INIT_VAL[i]),
                .CLEAR_VAL(CLEAR_VAL)
            ) d_trig_i (
                .D(D[i]),
                .C(C),
                .CLR(CLR),
                .Q(Q[i]),
                .notQ()
            );
        end
    endgenerate

endmodule
module register (
    D, C, CLR,
    Q
    );



    parameter                          DATA_WIDTH = 4;
    parameter reg [DATA_WIDTH - 1 : 0] INIT_VAL   = 0;
    parameter                          CLEAR_VAL  = 1;


    input wire [DATA_WIDTH - 1 : 0] D;
    input wire C, CLR;
    output wire [DATA_WIDTH - 1 : 0] Q;


    genvar i;


    generate
        for(i = 0; i < DATA_WIDTH; i = i + 1) begin
            d_trig #(
                .INIT_VAL(INIT_VAL[i]),
                .CLEAR_VAL(CLEAR_VAL)
            ) d_trig_i (
                .D(D[i]),
                .C(C),
                .CLR(CLR),
                .Q(Q[i]),
                .notQ()
            );
        end
    endgenerate

endmodule