data/full_repos/permissive/159001439/src/axi_mux.v
 line:191: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/159001439/src/axi_mux.v:206: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'current\' generates 1 bits.\n                                                                      : ... In instance axi_mux\n  j=current+i;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/axi_mux.v:210: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                      : ... In instance axi_mux\n   select=j;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/axi_mux.v:230: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'s_awvalid\' generates 2 bits.\n                                                                      : ... In instance axi_mux\n else if(!write_busy && s_awvalid) begin\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/axi_mux.v:323: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'wi\' generates 1 bits.\n                                                                      : ... In instance axi_mux\n  s_awready[i] = write_busy & (wi==i) & m_awready & !write_disable;\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/axi_mux.v:324: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'wi\' generates 1 bits.\n                                                                      : ... In instance axi_mux\n  s_wready[i] = write_busy & (wi==i) & m_wready & wdata_enable;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/axi_mux.v:325: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'wi\' generates 1 bits.\n                                                                      : ... In instance axi_mux\n  s_bvalid[i] = write_busy & (wi==i) & m_bvalid & bresp_enable;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/axi_mux.v:338: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'s_arvalid\' generates 2 bits.\n                                                                      : ... In instance axi_mux\n else if(!read_busy && s_arvalid) begin\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/axi_mux.v:391: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'ri\' generates 1 bits.\n                                                                      : ... In instance axi_mux\n  s_arready[i] = read_busy & (ri==i) & m_arready & !read_disable;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/axi_mux.v:392: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'ri\' generates 1 bits.\n                                                                      : ... In instance axi_mux\n  s_rvalid[i] = read_busy & (ri==i) & m_rvalid;\n                               ^~\n%Error: Exiting due to 9 warning(s)\n'
function integer clogb2 (input integer size);
begin
	size = size - 1;
	for (clogb2=1; size>1; clogb2=clogb2+1)
		size = size >> 1;
end
endfunction
function integer clogb2 (input integer size);

begin
	size = size - 1;
	for (clogb2=1; size>1; clogb2=clogb2+1)
		size = size >> 1;
end
endfunction