data/full_repos/permissive/167274925/Mux32Bit3To1.v
data/verilator_xmls/e1259970-aaa2-4e42-aee2-e82d5fb8a6c1.xml
module Mux32Bit3To1(out, inA, inB,inC, sel);

    output reg [31:0] out;
   
    input [31:0] inA;
    input [31:0] inB;
    input [31:0] inC;
    input [1:0]sel;
 
   always@(inA,inB,sel)begin 
      case(sel)
      2'd0:out<=inA;
      2'd1:out<=inB;
      2'd2:out<=inC;
      endcase 
   end 
endmodule
module Mux32Bit3To1(out, inA, inB,inC, sel);


    output reg [31:0] out;
   
    input [31:0] inA;
    input [31:0] inB;
    input [31:0] inC;
    input [1:0]sel;
 
   always@(inA,inB,sel)begin 
      case(sel)
      2'd0:out<=inA;
      2'd1:out<=inB;
      2'd2:out<=inC;
      endcase 
   end 
endmodule