data/full_repos/permissive/169266176/mos6529.v
data/verilator_xmls/f9605ea6-968a-4cdd-8902-0b063efb7f7c.xml
module mos6529(
	 input clk,
    input [7:0] data_in,
    output wire [7:0] data_out,
    input [7:0] port_in,
    output wire [7:0] port_out,
    input rw,
    input cs
    );

reg [7:0] iodata=0;

assign port_out=iodata;
assign data_out=(cs & rw)?iodata:8'hff;

always @(posedge clk)
	begin
	if(cs)
		if(rw)
			iodata<=port_in;
		else
			iodata<=data_in;
	end
endmodule
module mos6529(
	 input clk,
    input [7:0] data_in,
    output wire [7:0] data_out,
    input [7:0] port_in,
    output wire [7:0] port_out,
    input rw,
    input cs
    );


reg [7:0] iodata=0;

assign port_out=iodata;
assign data_out=(cs & rw)?iodata:8'hff;

always @(posedge clk)
	begin
	if(cs)
		if(rw)
			iodata<=port_in;
		else
			iodata<=data_in;
	end
endmodule