data/full_repos/permissive/125592111/verilog/ID_EX.v
1: b"%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:56: Duplicate declaration of signal: 'RegWrite_out'\n                                                               : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg RegWrite_out;\n     ^~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:45: ... Location of original declaration\n output RegWrite_out, \n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:57: Duplicate declaration of signal: 'Branch_out'\n reg Branch_out, MemRead_out, MemWrite_out, Jump_out;\n     ^~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:46: ... Location of original declaration\n output Branch_out, MemRead_out, MemWrite_out, Jump_out,\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:57: Duplicate declaration of signal: 'MemRead_out'\n reg Branch_out, MemRead_out, MemWrite_out, Jump_out;\n                 ^~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:46: ... Location of original declaration\n output Branch_out, MemRead_out, MemWrite_out, Jump_out,\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:57: Duplicate declaration of signal: 'MemWrite_out'\n reg Branch_out, MemRead_out, MemWrite_out, Jump_out;\n                              ^~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:46: ... Location of original declaration\n output Branch_out, MemRead_out, MemWrite_out, Jump_out,\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:57: Duplicate declaration of signal: 'Jump_out'\n reg Branch_out, MemRead_out, MemWrite_out, Jump_out;\n                                            ^~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:46: ... Location of original declaration\n output Branch_out, MemRead_out, MemWrite_out, Jump_out,\n                                               ^~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:58: Duplicate declaration of signal: 'ALUSrc_out'\n reg ALUSrc_out;\n     ^~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:47: ... Location of original declaration\n output ALUSrc_out,\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:59: Duplicate declaration of signal: 'ALUOp_out'\n reg [2:0] ALUOp_out;\n           ^~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:49: ... Location of original declaration\n output [2:0] ALUOp_out,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:60: Duplicate declaration of signal: 'RegDst_out'\n reg [1:0] RegDst_out, MemtoReg_out;\n           ^~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:48: ... Location of original declaration\n output [1:0] RegDst_out, MemtoReg_out,\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:60: Duplicate declaration of signal: 'MemtoReg_out'\n reg [1:0] RegDst_out, MemtoReg_out;\n                       ^~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:48: ... Location of original declaration\n output [1:0] RegDst_out, MemtoReg_out,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:61: Duplicate declaration of signal: 'jump_addr_out'\n reg [31:0] jump_addr_out, PC_plus4_out, branch_addr_out;\n            ^~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:50: ... Location of original declaration\n output [31:0] jump_addr_out, PC_plus4_out, branch_addr_out,\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:61: Duplicate declaration of signal: 'PC_plus4_out'\n reg [31:0] jump_addr_out, PC_plus4_out, branch_addr_out;\n                           ^~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:50: ... Location of original declaration\n output [31:0] jump_addr_out, PC_plus4_out, branch_addr_out,\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:61: Duplicate declaration of signal: 'branch_addr_out'\n reg [31:0] jump_addr_out, PC_plus4_out, branch_addr_out;\n                                         ^~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:50: ... Location of original declaration\n output [31:0] jump_addr_out, PC_plus4_out, branch_addr_out,\n                                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:62: Duplicate declaration of signal: 'reg_read_data_1_out'\n reg [31:0] reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out;\n            ^~~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:51: ... Location of original declaration\n output [31:0] reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out,\n               ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:62: Duplicate declaration of signal: 'reg_read_data_2_out'\n reg [31:0] reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out;\n                                 ^~~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:51: ... Location of original declaration\n output [31:0] reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out,\n                                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:62: Duplicate declaration of signal: 'immi_sign_extended_out'\n reg [31:0] reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out;\n                                                      ^~~~~~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:51: ... Location of original declaration\n output [31:0] reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out,\n                                                         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:63: Duplicate declaration of signal: 'ID_EX_RegisterRs_out'\n reg [4:0] ID_EX_RegisterRs_out, ID_EX_RegisterRt_out, ID_EX_RegisterRd_out;\n           ^~~~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:52: ... Location of original declaration\n output [4:0] ID_EX_RegisterRs_out, ID_EX_RegisterRt_out, ID_EX_RegisterRd_out,\n              ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:63: Duplicate declaration of signal: 'ID_EX_RegisterRt_out'\n reg [4:0] ID_EX_RegisterRs_out, ID_EX_RegisterRt_out, ID_EX_RegisterRd_out;\n                                 ^~~~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:52: ... Location of original declaration\n output [4:0] ID_EX_RegisterRs_out, ID_EX_RegisterRt_out, ID_EX_RegisterRd_out,\n                                    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:63: Duplicate declaration of signal: 'ID_EX_RegisterRd_out'\n reg [4:0] ID_EX_RegisterRs_out, ID_EX_RegisterRt_out, ID_EX_RegisterRd_out;\n                                                       ^~~~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:52: ... Location of original declaration\n output [4:0] ID_EX_RegisterRs_out, ID_EX_RegisterRt_out, ID_EX_RegisterRd_out,\n                                                          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/ID_EX.v:64: Duplicate declaration of signal: 'ID_EX_funct_out'\n reg [5:0] ID_EX_funct_out;\n           ^~~~~~~~~~~~~~~\n        data/full_repos/permissive/125592111/verilog/ID_EX.v:53: ... Location of original declaration\n output [5:0] ID_EX_funct_out\n              ^~~~~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n"
module ID_EX (
	input ID_Hazard_lwstall, ID_Hazard_Branch,
	input Branch_in, MemRead_in, MemWrite_in, Jump_in,
	input RegWrite_in, 
	input ALUSrc_in,
	input [1:0] RegDst_in, MemtoReg_in,
	input [2:0] ALUOp_in,
	input [31:0] jump_addr_in, PC_plus4_in, branch_addr_in,
	input [31:0] reg_read_data_1_in, reg_read_data_2_in, immi_sign_extended_in,
	input [4:0] IF_ID_RegisterRs_in, IF_ID_RegisterRt_in, IF_ID_RegisterRd_in,
	input [5:0] IF_ID_funct_in,
	input clk, rst,
	
	output RegWrite_out, 
	output Branch_out, MemRead_out, MemWrite_out, Jump_out,
	output ALUSrc_out,
	output [1:0] RegDst_out, MemtoReg_out,
	output [2:0] ALUOp_out,
	output [31:0] jump_addr_out, PC_plus4_out, branch_addr_out,
	output [31:0] reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out,
	output [4:0] ID_EX_RegisterRs_out, ID_EX_RegisterRt_out, ID_EX_RegisterRd_out,
	output [5:0] ID_EX_funct_out
);

	reg RegWrite_out;
	reg Branch_out, MemRead_out, MemWrite_out, Jump_out;
	reg ALUSrc_out;
	reg [2:0] ALUOp_out;
	reg [1:0] RegDst_out, MemtoReg_out;
	reg [31:0] jump_addr_out, PC_plus4_out, branch_addr_out;
	reg [31:0] reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out;
	reg [4:0] ID_EX_RegisterRs_out, ID_EX_RegisterRt_out, ID_EX_RegisterRd_out;
	reg [5:0] ID_EX_funct_out;

	
	always @(negedge clk) begin
		
		if (rst == 1'b1) begin
			RegWrite_out <= 1'b0;
			MemtoReg_out <= 2'b00;
			Branch_out <= 1'b0;
			MemRead_out <= 1'b0;
			MemWrite_out <= 1'b0;
			Jump_out <= 1'b0;
			RegDst_out <= 2'b00;
			ALUSrc_out <= 1'b0;
			ALUOp_out <= 2'b0;
			jump_addr_out <= 32'b0;
			branch_addr_out <= 32'b0;
			PC_plus4_out <= 32'b0;
			reg_read_data_1_out <= 32'b0;
			reg_read_data_2_out <= 32'b0;
			immi_sign_extended_out <= 32'b0;
			ID_EX_RegisterRs_out <= 5'b0;
			ID_EX_RegisterRt_out <= 5'b0;
			ID_EX_RegisterRd_out <= 5'b0;
			ID_EX_funct_out <= 6'b0;			
		end

		else begin

			RegWrite_out <= RegWrite_in;
			MemtoReg_out <= MemtoReg_in;
			Branch_out <= Branch_in;
			MemRead_out <= MemRead_in;
			MemWrite_out <= MemWrite_in;
			Jump_out <= Jump_in;
			RegDst_out <= RegDst_in;
			ALUSrc_out <= ALUSrc_in;
			ALUOp_out <= ALUOp_in;
			jump_addr_out <= jump_addr_in;
			branch_addr_out <= branch_addr_in;
			PC_plus4_out <= PC_plus4_in;
			reg_read_data_1_out <= reg_read_data_1_in;
			reg_read_data_2_out <= reg_read_data_2_in;
			immi_sign_extended_out <= immi_sign_extended_in;
			ID_EX_RegisterRs_out <= IF_ID_RegisterRs_in;
			ID_EX_RegisterRt_out <= IF_ID_RegisterRt_in;
			ID_EX_RegisterRd_out <= IF_ID_RegisterRd_in;
			ID_EX_funct_out <= IF_ID_funct_in;

			if (ID_Hazard_lwstall == 1'b1 || ID_Hazard_Branch == 1'b1) begin

				RegWrite_out <= 1'b0;
				MemtoReg_out <= 2'b00;
				Branch_out <= 1'b0;
				MemRead_out <= 1'b0;
				MemWrite_out <= 1'b0;
				Jump_out <= 1'b0;
				RegDst_out <= 2'b00;
				ALUSrc_out <= 1'b0;
				ALUOp_out <= 2'b0;

			end

		end	
		
	end	
	
endmodule
module ID_EX (
	input ID_Hazard_lwstall, ID_Hazard_Branch,
	input Branch_in, MemRead_in, MemWrite_in, Jump_in,
	input RegWrite_in, 
	input ALUSrc_in,
	input [1:0] RegDst_in, MemtoReg_in,
	input [2:0] ALUOp_in,
	input [31:0] jump_addr_in, PC_plus4_in, branch_addr_in,
	input [31:0] reg_read_data_1_in, reg_read_data_2_in, immi_sign_extended_in,
	input [4:0] IF_ID_RegisterRs_in, IF_ID_RegisterRt_in, IF_ID_RegisterRd_in,
	input [5:0] IF_ID_funct_in,
	input clk, rst,
	
	output RegWrite_out, 
	output Branch_out, MemRead_out, MemWrite_out, Jump_out,
	output ALUSrc_out,
	output [1:0] RegDst_out, MemtoReg_out,
	output [2:0] ALUOp_out,
	output [31:0] jump_addr_out, PC_plus4_out, branch_addr_out,
	output [31:0] reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out,
	output [4:0] ID_EX_RegisterRs_out, ID_EX_RegisterRt_out, ID_EX_RegisterRd_out,
	output [5:0] ID_EX_funct_out
);


	reg RegWrite_out;
	reg Branch_out, MemRead_out, MemWrite_out, Jump_out;
	reg ALUSrc_out;
	reg [2:0] ALUOp_out;
	reg [1:0] RegDst_out, MemtoReg_out;
	reg [31:0] jump_addr_out, PC_plus4_out, branch_addr_out;
	reg [31:0] reg_read_data_1_out, reg_read_data_2_out, immi_sign_extended_out;
	reg [4:0] ID_EX_RegisterRs_out, ID_EX_RegisterRt_out, ID_EX_RegisterRd_out;
	reg [5:0] ID_EX_funct_out;

	
	always @(negedge clk) begin
		
		if (rst == 1'b1) begin
			RegWrite_out <= 1'b0;
			MemtoReg_out <= 2'b00;
			Branch_out <= 1'b0;
			MemRead_out <= 1'b0;
			MemWrite_out <= 1'b0;
			Jump_out <= 1'b0;
			RegDst_out <= 2'b00;
			ALUSrc_out <= 1'b0;
			ALUOp_out <= 2'b0;
			jump_addr_out <= 32'b0;
			branch_addr_out <= 32'b0;
			PC_plus4_out <= 32'b0;
			reg_read_data_1_out <= 32'b0;
			reg_read_data_2_out <= 32'b0;
			immi_sign_extended_out <= 32'b0;
			ID_EX_RegisterRs_out <= 5'b0;
			ID_EX_RegisterRt_out <= 5'b0;
			ID_EX_RegisterRd_out <= 5'b0;
			ID_EX_funct_out <= 6'b0;			
		end

		else begin

			RegWrite_out <= RegWrite_in;
			MemtoReg_out <= MemtoReg_in;
			Branch_out <= Branch_in;
			MemRead_out <= MemRead_in;
			MemWrite_out <= MemWrite_in;
			Jump_out <= Jump_in;
			RegDst_out <= RegDst_in;
			ALUSrc_out <= ALUSrc_in;
			ALUOp_out <= ALUOp_in;
			jump_addr_out <= jump_addr_in;
			branch_addr_out <= branch_addr_in;
			PC_plus4_out <= PC_plus4_in;
			reg_read_data_1_out <= reg_read_data_1_in;
			reg_read_data_2_out <= reg_read_data_2_in;
			immi_sign_extended_out <= immi_sign_extended_in;
			ID_EX_RegisterRs_out <= IF_ID_RegisterRs_in;
			ID_EX_RegisterRt_out <= IF_ID_RegisterRt_in;
			ID_EX_RegisterRd_out <= IF_ID_RegisterRd_in;
			ID_EX_funct_out <= IF_ID_funct_in;

			if (ID_Hazard_lwstall == 1'b1 || ID_Hazard_Branch == 1'b1) begin

				RegWrite_out <= 1'b0;
				MemtoReg_out <= 2'b00;
				Branch_out <= 1'b0;
				MemRead_out <= 1'b0;
				MemWrite_out <= 1'b0;
				Jump_out <= 1'b0;
				RegDst_out <= 2'b00;
				ALUSrc_out <= 1'b0;
				ALUOp_out <= 2'b0;

			end

		end	
		
	end	
	
endmodule