data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter.v
data/verilator_xmls/d1da7fd7-7dc9-4636-a57a-c97396b3f19b.xml
module counter #(


    parameter W = 8
    )(
    input wire ck,
    input wire cl,
    input wire en,
    input wire ud,
    output wire [W-1:0] q,
    output reg c
    );


    reg [W-1:0] count;


    always @(posedge ck) begin
        if (cl)
            count <= 0;
        else if (en)
            if (ud == 0)
                count = count + 1;
            else
                count = count - 1;
    end



    always @* begin
        if (ud == 0)
            c = &count;
        else
            c = ~(|count);
    end


    assign q = count;

endmodule
module counter #(


    parameter W = 8
    )(
    input wire ck,
    input wire cl,
    input wire en,
    input wire ud,
    output wire [W-1:0] q,
    output reg c
    );



    reg [W-1:0] count;


    always @(posedge ck) begin
        if (cl)
            count <= 0;
        else if (en)
            if (ud == 0)
                count = count + 1;
            else
                count = count - 1;
    end



    always @* begin
        if (ud == 0)
            c = &count;
        else
            c = ~(|count);
    end


    assign q = count;

endmodule