data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/ddrtop.v
 line:260: before: "."
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/ddrtop.v:189: Cannot find file containing module: 'user_fifos'\n user_fifos UFIFO0 (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/user_fifos\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/user_fifos.v\n             data/full_repos/permissive/20430511/hardware/FPGA/ddrmem,data/full_repos/permissive/20430511/user_fifos.sv\n             user_fifos\n             user_fifos.v\n             user_fifos.sv\n             obj_dir/user_fifos\n             obj_dir/user_fifos.v\n             obj_dir/user_fifos.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/ddrtop.v:224: Cannot find file containing module: 'scheduler'\n scheduler SHED0 (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/ddrtop.v:261: Cannot find file containing module: 'controller'\n controller CNTRL0 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/ddrtop.v:297: Cannot find file containing module: 'datapath'\n datapath DP0 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/ddrtop.v:322: Cannot find file containing module: 'iobs'\n iobs IOBS0 (\n ^~~~\n%Error: Exiting due to 5 error(s)\n"
module ddrtop (
		clock_i,
		clock_270i,
		reset_i,
		

		ddr_clk_po,
		ddr_clk_no,
		ddr_cke_o,
		
		ddr_cs_no,
		ddr_ras_no,
		ddr_cas_no,
		ddr_we_no,
		
		ddr_ba_o,
		ddr_a_o,
		
		ddr_dm_o,
		ddr_dq_io,
		ddr_dqs_io,
		

		rd_req_i,
		rd_block_i,
		rd_owner_i,
		rd_busy_o,
		rd_addr_i,
		rd_owner_o,
		rd_data_o,
		rd_ready_o,
		
		wr_req_i,
		wr_block_i,
		wr_busy_o,
		wr_bes_ni,
		wr_addr_i,
		wr_data_i
	);
	
	parameter	DWIDTH		= 16;
	parameter	DRADDR		= 13;
	parameter	DCADDR		= 9;
	parameter	STROBES		= 2;
	
	parameter	UWIDTH		= 32;
	parameter	UBYTES		= 4;
	parameter	UADDR		= 23;
	parameter	OWNERS		= 2;
	
	parameter	REFRESH_TIMER	= 585;
	parameter	CAS_LATENCY	= 2;
	parameter	BURST_LENGTH	= 2;
	

	input	clock_i;
	input	clock_270i;
	input	reset_i;
	

	output	ddr_clk_po;
	output	ddr_clk_no;
	output	ddr_cke_o;
	
	output	ddr_cs_no;
	output	ddr_ras_no;
	output	ddr_cas_no;
	output	ddr_we_no;
	
	output	[1:0]		ddr_ba_o;
	output	[DRADDR-1:0]	ddr_a_o;
	
	output	[STROBES-1:0]	ddr_dm_o;
	inout	[STROBES-1:0]	ddr_dqs_io;
	inout	[DWIDTH-1:0]	ddr_dq_io;
	

	input	rd_req_i;
	input	rd_block_i;
	output	rd_busy_o;
	input	[OWNERS-1:0]	rd_owner_i;
	output	[OWNERS-1:0]	rd_owner_o;
	input	[UADDR-1:0]	rd_addr_i;
	output	[UWIDTH-1:0]	rd_data_o;
	output	rd_ready_o;
	
	input	wr_req_i;
	input	wr_block_i;
	output	wr_busy_o;
	input	[UADDR-1:0]	wr_addr_i;
	input	[UBYTES-1:0]	wr_bes_ni;
	input	[UWIDTH-1:0]	wr_data_i;
	
	

	wire	raf_read;
	wire	raf_block;
	wire	raf_empty_n;
	wire	raf_one;
	wire	[OWNERS-1:0]	raf_owner;
	wire	[UADDR-1:0]	raf_addr;
	
	wire	waf_read;
	wire	waf_empty_n;
	wire	[UADDR-1:0]	waf_addr;
	wire	[UBYTES-1:0]	wdf_bes_n;
	wire	[UWIDTH-1:0]	wdf_data;
	

	wire	cntrl_cke;
	wire	cntrl_cs_n;
	wire	cntrl_ras_n;
	wire	cntrl_cas_n;
	wire	cntrl_we_n;
	wire	[1:0]		cntrl_ba;
	wire	[DRADDR-1:0]	cntrl_a;
	

	wire	ctl_start;
	wire	ctl_read;
	wire	ctl_last;
	wire	[1:0]		ctl_bank;
	wire	[DRADDR-1:0]	ctl_row;
	wire	[DCADDR-2:0]	ctl_col;
	
	wire	ctl_exec;
	wire	ctl_active;
	

	wire	dp_read;
	wire	dp_write;
	wire	dp_suspend;
	

	wire	dp_send;
	wire	[UBYTES-1:0]	dp_bes_n;
	wire	dp_dqs;
	wire	[UWIDTH-1:0]	dp_data_to;
	wire	[UWIDTH-1:0]	dp_data_from;
	


	reg	wdf_read	= 0;
	


	reg	wdf_read0, wdf_read1;
	always @(posedge clock_i)
	begin
		if (reset_i)
			wdf_read0	<= 0;
		else
		begin
			wdf_read0	<= dp_write;
			wdf_read1	<= wdf_read0;
			wdf_read	<= wdf_read1;
		end
	end
	
	


	user_fifos UFIFO0 (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		

		.rd_req_i	(rd_req_i),
		.rd_block_i	(rd_block_i),
		.rd_busy_o	(rd_busy_o),
		.rd_owner_i	(rd_owner_i),
		.rd_addr_i	(rd_addr_i),
		
		.wr_req_i	(wr_req_i),
		.wr_busy_o	(wr_busy_o),
		.wr_addr_i	(wr_addr_i),
		.wr_bytes_i	(wr_bes_ni),
		.wr_data_i	(wr_data_i),
		

		.raf_read_i	(raf_read),
		.raf_block_o	(raf_block),
		.raf_one_o	(raf_one),
		.raf_empty_no	(raf_empty_n),
		.raf_owner_o	(raf_owner),
		.raf_addr_o	(raf_addr),
		
		.waf_read_i	(waf_read),
		.waf_empty_no	(waf_empty_n),
		.waf_addr_o	(waf_addr),
		
		.wdf_read_i	(wdf_read),
		.wdf_bytes_o	(wdf_bes_n),
		.wdf_data_o	(wdf_data)
	);
	
	
	scheduler SHED0 (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		.enable_i	(init_done),
		
		.raf_empty_ni	(raf_empty_n),
		.raf_one_i	(raf_one),
		.raf_block_i	(raf_block),
		.raf_read_o	(raf_read),
		.raf_addr_i	(raf_addr),
		
		.waf_empty_ni	(waf_empty_n),
		.waf_read_o	(waf_read),
		.waf_addr_i	(waf_addr),
		

		.cmd_start_o	(ctl_start),
		.cmd_read_o	(ctl_read),
		.cmd_last_o	(ctl_last),
		.cmd_susp_o	(dp_suspend),
		.cmd_bank_o	(ctl_bank),
		.cmd_row_o	(ctl_row),
		.cmd_col_o	(ctl_col),
		

		.ctl_read_i	(dp_read),
		.ctl_write_i	(dp_write),
		.ctl_active_i	(ctl_active),
		
		.rfc_req_i	(rfc_req),
		.rfc_ack_o	(rfc_start),
		.rfc_end_i	(rfc_done)
	);
	
	

	defparam	CNTRL0.RFC_TICKS	= REFRESH_TIMER;
	controller CNTRL0 (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		
		.ddr_cke_o	(cntrl_cke),
		
		.ddr_cs_no	(cntrl_cs_n),
		.ddr_ras_no	(cntrl_ras_n),
		.ddr_cas_no	(cntrl_cas_n),
		.ddr_we_no	(cntrl_we_n),
		
		.ddr_ba_o	(cntrl_ba),
		.ddr_a_o	(cntrl_a),
		
		.init_done_o	(init_done),
		
		.cmd_start_i	(ctl_start),
		.cmd_read_i	(ctl_read),
		.cmd_last_i	(ctl_last),
		.cmd_exec_o	(ctl_exec),
		.cmd_active_o	(ctl_active),
		.cmd_bank_i	(ctl_bank),
		.cmd_row_i	(ctl_row),
		.cmd_col_i	(ctl_col),
		
		.data_read_o	(dp_read),
		.data_write_o	(dp_write),
		
		.rfc_req_o	(rfc_req),
		.rfc_start_i	(rfc_start),
		.rfc_done_o	(rfc_done)
	);
	
	


	datapath DP0 (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		
		.usr_data_i	(wdf_data),
		.usr_bes_ni	(wdf_bes_n),
		.usr_owner_i	(raf_owner),
		.usr_data_o	(rd_data_o),
		.usr_owner_o	(rd_owner_o),
		.usr_ready_o	(rd_ready_o),
		
		.ctl_start_i	(ctl_start),
		.ctl_block_i	(block),
		.ctl_suspend_i	(dp_suspend),
		.ctl_read_i	(dp_read),
		.ctl_write_i	(dp_write),
		
		.ddr_send_o	(dp_send),
		.ddr_bes_no	(dp_bes_n),
		.ddr_dqs_o	(dp_dqs),
		.ddr_data_o	(dp_data_to),
		.ddr_data_i	(dp_data_from)
	);
	
	
	iobs IOBS0 (
		.clock_i	(clock_i),
		.clock_270i	(clock_270i),
		.reset_i	(reset_i),
		

		.cntrl_cke_i	(cntrl_cke),
		
		.cntrl_cs_ni	(cntrl_cs_n),
		.cntrl_ras_ni	(cntrl_ras_n),
		.cntrl_cas_ni	(cntrl_cas_n),
		.cntrl_we_ni	(cntrl_we_n),
		
		.cntrl_ba_i	(cntrl_ba),
		.cntrl_a_i	(cntrl_a),
		
		.cntrl_dm_i	(dp_bes_n),
		.cntrl_data_i	(dp_data_to),
		.cntrl_dqs_i	(dp_dqs),
		.cntrl_send_i	(dp_send),
		.cntrl_data_o	(dp_data_from),
		

		.ddr_ck_o	(ddr_clk_po),
		.ddr_ck_no	(ddr_clk_no),
		.ddr_cke_o	(ddr_cke_o),
		
		.ddr_cs_no	(ddr_cs_no),
		.ddr_ras_no	(ddr_ras_no),
		.ddr_cas_no	(ddr_cas_no),
		.ddr_we_no	(ddr_we_no),
		
		.ddr_ba_o	(ddr_ba_o),
		.ddr_a_o	(ddr_a_o),
		
		.ddr_dm_o	(ddr_dm_o),
		.ddr_dq_io	(ddr_dq_io),
		.ddr_dqs_io	(ddr_dqs_io)
	);
	
endmodule
module ddrtop (
		clock_i,
		clock_270i,
		reset_i,
		

		ddr_clk_po,
		ddr_clk_no,
		ddr_cke_o,
		
		ddr_cs_no,
		ddr_ras_no,
		ddr_cas_no,
		ddr_we_no,
		
		ddr_ba_o,
		ddr_a_o,
		
		ddr_dm_o,
		ddr_dq_io,
		ddr_dqs_io,
		

		rd_req_i,
		rd_block_i,
		rd_owner_i,
		rd_busy_o,
		rd_addr_i,
		rd_owner_o,
		rd_data_o,
		rd_ready_o,
		
		wr_req_i,
		wr_block_i,
		wr_busy_o,
		wr_bes_ni,
		wr_addr_i,
		wr_data_i
	);

	
	parameter	DWIDTH		= 16;
	parameter	DRADDR		= 13;
	parameter	DCADDR		= 9;
	parameter	STROBES		= 2;
	
	parameter	UWIDTH		= 32;
	parameter	UBYTES		= 4;
	parameter	UADDR		= 23;
	parameter	OWNERS		= 2;
	
	parameter	REFRESH_TIMER	= 585;
	parameter	CAS_LATENCY	= 2;
	parameter	BURST_LENGTH	= 2;
	

	input	clock_i;
	input	clock_270i;
	input	reset_i;
	

	output	ddr_clk_po;
	output	ddr_clk_no;
	output	ddr_cke_o;
	
	output	ddr_cs_no;
	output	ddr_ras_no;
	output	ddr_cas_no;
	output	ddr_we_no;
	
	output	[1:0]		ddr_ba_o;
	output	[DRADDR-1:0]	ddr_a_o;
	
	output	[STROBES-1:0]	ddr_dm_o;
	inout	[STROBES-1:0]	ddr_dqs_io;
	inout	[DWIDTH-1:0]	ddr_dq_io;
	

	input	rd_req_i;
	input	rd_block_i;
	output	rd_busy_o;
	input	[OWNERS-1:0]	rd_owner_i;
	output	[OWNERS-1:0]	rd_owner_o;
	input	[UADDR-1:0]	rd_addr_i;
	output	[UWIDTH-1:0]	rd_data_o;
	output	rd_ready_o;
	
	input	wr_req_i;
	input	wr_block_i;
	output	wr_busy_o;
	input	[UADDR-1:0]	wr_addr_i;
	input	[UBYTES-1:0]	wr_bes_ni;
	input	[UWIDTH-1:0]	wr_data_i;
	
	

	wire	raf_read;
	wire	raf_block;
	wire	raf_empty_n;
	wire	raf_one;
	wire	[OWNERS-1:0]	raf_owner;
	wire	[UADDR-1:0]	raf_addr;
	
	wire	waf_read;
	wire	waf_empty_n;
	wire	[UADDR-1:0]	waf_addr;
	wire	[UBYTES-1:0]	wdf_bes_n;
	wire	[UWIDTH-1:0]	wdf_data;
	

	wire	cntrl_cke;
	wire	cntrl_cs_n;
	wire	cntrl_ras_n;
	wire	cntrl_cas_n;
	wire	cntrl_we_n;
	wire	[1:0]		cntrl_ba;
	wire	[DRADDR-1:0]	cntrl_a;
	

	wire	ctl_start;
	wire	ctl_read;
	wire	ctl_last;
	wire	[1:0]		ctl_bank;
	wire	[DRADDR-1:0]	ctl_row;
	wire	[DCADDR-2:0]	ctl_col;
	
	wire	ctl_exec;
	wire	ctl_active;
	

	wire	dp_read;
	wire	dp_write;
	wire	dp_suspend;
	

	wire	dp_send;
	wire	[UBYTES-1:0]	dp_bes_n;
	wire	dp_dqs;
	wire	[UWIDTH-1:0]	dp_data_to;
	wire	[UWIDTH-1:0]	dp_data_from;
	


	reg	wdf_read	= 0;
	


	reg	wdf_read0, wdf_read1;
	always @(posedge clock_i)
	begin
		if (reset_i)
			wdf_read0	<= 0;
		else
		begin
			wdf_read0	<= dp_write;
			wdf_read1	<= wdf_read0;
			wdf_read	<= wdf_read1;
		end
	end
	
	


	user_fifos UFIFO0 (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		

		.rd_req_i	(rd_req_i),
		.rd_block_i	(rd_block_i),
		.rd_busy_o	(rd_busy_o),
		.rd_owner_i	(rd_owner_i),
		.rd_addr_i	(rd_addr_i),
		
		.wr_req_i	(wr_req_i),
		.wr_busy_o	(wr_busy_o),
		.wr_addr_i	(wr_addr_i),
		.wr_bytes_i	(wr_bes_ni),
		.wr_data_i	(wr_data_i),
		

		.raf_read_i	(raf_read),
		.raf_block_o	(raf_block),
		.raf_one_o	(raf_one),
		.raf_empty_no	(raf_empty_n),
		.raf_owner_o	(raf_owner),
		.raf_addr_o	(raf_addr),
		
		.waf_read_i	(waf_read),
		.waf_empty_no	(waf_empty_n),
		.waf_addr_o	(waf_addr),
		
		.wdf_read_i	(wdf_read),
		.wdf_bytes_o	(wdf_bes_n),
		.wdf_data_o	(wdf_data)
	);
	
	
	scheduler SHED0 (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		.enable_i	(init_done),
		
		.raf_empty_ni	(raf_empty_n),
		.raf_one_i	(raf_one),
		.raf_block_i	(raf_block),
		.raf_read_o	(raf_read),
		.raf_addr_i	(raf_addr),
		
		.waf_empty_ni	(waf_empty_n),
		.waf_read_o	(waf_read),
		.waf_addr_i	(waf_addr),
		

		.cmd_start_o	(ctl_start),
		.cmd_read_o	(ctl_read),
		.cmd_last_o	(ctl_last),
		.cmd_susp_o	(dp_suspend),
		.cmd_bank_o	(ctl_bank),
		.cmd_row_o	(ctl_row),
		.cmd_col_o	(ctl_col),
		

		.ctl_read_i	(dp_read),
		.ctl_write_i	(dp_write),
		.ctl_active_i	(ctl_active),
		
		.rfc_req_i	(rfc_req),
		.rfc_ack_o	(rfc_start),
		.rfc_end_i	(rfc_done)
	);
	
	

	defparam	CNTRL0.RFC_TICKS	= REFRESH_TIMER;
	controller CNTRL0 (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		
		.ddr_cke_o	(cntrl_cke),
		
		.ddr_cs_no	(cntrl_cs_n),
		.ddr_ras_no	(cntrl_ras_n),
		.ddr_cas_no	(cntrl_cas_n),
		.ddr_we_no	(cntrl_we_n),
		
		.ddr_ba_o	(cntrl_ba),
		.ddr_a_o	(cntrl_a),
		
		.init_done_o	(init_done),
		
		.cmd_start_i	(ctl_start),
		.cmd_read_i	(ctl_read),
		.cmd_last_i	(ctl_last),
		.cmd_exec_o	(ctl_exec),
		.cmd_active_o	(ctl_active),
		.cmd_bank_i	(ctl_bank),
		.cmd_row_i	(ctl_row),
		.cmd_col_i	(ctl_col),
		
		.data_read_o	(dp_read),
		.data_write_o	(dp_write),
		
		.rfc_req_o	(rfc_req),
		.rfc_start_i	(rfc_start),
		.rfc_done_o	(rfc_done)
	);
	
	


	datapath DP0 (
		.clock_i	(clock_i),
		.reset_i	(reset_i),
		
		.usr_data_i	(wdf_data),
		.usr_bes_ni	(wdf_bes_n),
		.usr_owner_i	(raf_owner),
		.usr_data_o	(rd_data_o),
		.usr_owner_o	(rd_owner_o),
		.usr_ready_o	(rd_ready_o),
		
		.ctl_start_i	(ctl_start),
		.ctl_block_i	(block),
		.ctl_suspend_i	(dp_suspend),
		.ctl_read_i	(dp_read),
		.ctl_write_i	(dp_write),
		
		.ddr_send_o	(dp_send),
		.ddr_bes_no	(dp_bes_n),
		.ddr_dqs_o	(dp_dqs),
		.ddr_data_o	(dp_data_to),
		.ddr_data_i	(dp_data_from)
	);
	
	
	iobs IOBS0 (
		.clock_i	(clock_i),
		.clock_270i	(clock_270i),
		.reset_i	(reset_i),
		

		.cntrl_cke_i	(cntrl_cke),
		
		.cntrl_cs_ni	(cntrl_cs_n),
		.cntrl_ras_ni	(cntrl_ras_n),
		.cntrl_cas_ni	(cntrl_cas_n),
		.cntrl_we_ni	(cntrl_we_n),
		
		.cntrl_ba_i	(cntrl_ba),
		.cntrl_a_i	(cntrl_a),
		
		.cntrl_dm_i	(dp_bes_n),
		.cntrl_data_i	(dp_data_to),
		.cntrl_dqs_i	(dp_dqs),
		.cntrl_send_i	(dp_send),
		.cntrl_data_o	(dp_data_from),
		

		.ddr_ck_o	(ddr_clk_po),
		.ddr_ck_no	(ddr_clk_no),
		.ddr_cke_o	(ddr_cke_o),
		
		.ddr_cs_no	(ddr_cs_no),
		.ddr_ras_no	(ddr_ras_no),
		.ddr_cas_no	(ddr_cas_no),
		.ddr_we_no	(ddr_we_no),
		
		.ddr_ba_o	(ddr_ba_o),
		.ddr_a_o	(ddr_a_o),
		
		.ddr_dm_o	(ddr_dm_o),
		.ddr_dq_io	(ddr_dq_io),
		.ddr_dqs_io	(ddr_dqs_io)
	);
	
endmodule