data/full_repos/permissive/143278/ivltests/casesynth9.v
 line:38: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/casesynth9.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #1 $display("%d : %b", sel, out);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/casesynth9.v:40: Operator NEQCASE expects 3 bits on the RHS, but RHS\'s VARREF \'sel\' generates 2 bits.\n                                                                          : ... In instance test\n    if (out !== sel) failed = 1;\n            ^~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux(

input wire [1:0] sel,
input wire [2:0] i0,
input wire [2:0] i1,
input wire [2:0] i2,
input wire [2:0] i3,
input wire [2:0] i4,
output reg [2:0] o

);

always @* begin
  case (sel)
    0 : o = i0;
    1 : o = i1;
    2 : o = i2;
    3 : o = i3;
    2 : o = i4;
  endcase
end

endmodule
module mux(

input wire [1:0] sel,
input wire [2:0] i0,
input wire [2:0] i1,
input wire [2:0] i2,
input wire [2:0] i3,
input wire [2:0] i4,
output reg [2:0] o

);


always @* begin
  case (sel)
    0 : o = i0;
    1 : o = i1;
    2 : o = i2;
    3 : o = i3;
    2 : o = i4;
  endcase
end

endmodule