data/full_repos/permissive/190698744/5 - More Verilog Features/4 - combinational for loop - vector reversal.v
1: b'%Error: Invalid Option: -\n'
module top_module( 
    input [99:0] in,
    output [99:0] out
);
    integer i;
    always @ (in) begin 
        for (i=0;i<100; i=i+1) begin
            out[99-i] = in[i];
        end        
    end
endmodule
module top_module( 
    input [99:0] in,
    output [99:0] out
);

    integer i;
    always @ (in) begin 
        for (i=0;i<100; i=i+1) begin
            out[99-i] = in[i];
        end        
    end
endmodule