data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/testbench.v
 line:644: before: "("
1: b'%Error: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/testbench.v:11: Cannot find include file: sumador.v\n`include "sumador.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline,data/full_repos/permissive/178052224/sumador.v\n             data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline,data/full_repos/permissive/178052224/sumador.v.v\n             data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline,data/full_repos/permissive/178052224/sumador.v.sv\n             sumador.v\n             sumador.v.v\n             sumador.v.sv\n             obj_dir/sumador.v\n             obj_dir/sumador.v.v\n             obj_dir/sumador.v.sv\n%Error: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/testbench.v:12: Cannot find include file: sumador_Synth.v\n`include "sumador_Synth.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/testbench.v:13: Cannot find include file: probador.v\n`include "probador.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/testbench.v:14: Cannot find include file: CMOS/cmos_cells.v\n`include "CMOS/cmos_cells.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module testbench();


	wire		clk;
	wire [3:0]	dataA;
	wire [3:0]	dataB;
	wire [3:0]	idx;
	wire [3:0]	idx_dd_cond;
	wire [3:0]	idx_dd_estruc;
	wire		reset_L;
	wire [3:0]	sum30_dd_cond;
	wire [3:0]	sum30_dd_estruc;


	

    sumador sumador_con(

			.sum30_dd	(sum30_dd_cond[3:0]),
			.idx_dd		(idx_dd_cond[3:0]),

			.clk		(clk),
			.reset_L	(reset_L),
			.idx		(idx[3:0]),
			.dataA		(dataA[3:0]),
			.dataB		(dataB[3:0]));

	sumador_Synth sumador_est(

				  .idx_dd		(idx_dd_estruc[3:0]),
				  .sum30_dd		(sum30_dd_estruc[3:0]),

				  .clk			(clk),
				  .dataA		(dataA[3:0]),
				  .dataB		(dataB[3:0]),
				  .idx			(idx[3:0]),
				  .reset_L		(reset_L));
	
    probador test0(

		   .clk			(clk),
		   .reset_L		(reset_L),
		   .idx			(idx[3:0]),
		   .dataA		(dataA[3:0]),
		   .dataB		(dataB[3:0]),

		   .idx_dd_cond		(idx_dd_cond[3:0]),
		   .idx_dd_estruc	(idx_dd_estruc[3:0]),
		   .sum30_dd_cond	(sum30_dd_cond[3:0]),
		   .sum30_dd_estruc	(sum30_dd_estruc[3:0]));

endmodule
module testbench();



	wire		clk;
	wire [3:0]	dataA;
	wire [3:0]	dataB;
	wire [3:0]	idx;
	wire [3:0]	idx_dd_cond;
	wire [3:0]	idx_dd_estruc;
	wire		reset_L;
	wire [3:0]	sum30_dd_cond;
	wire [3:0]	sum30_dd_estruc;


	

    sumador sumador_con(

			.sum30_dd	(sum30_dd_cond[3:0]),
			.idx_dd		(idx_dd_cond[3:0]),

			.clk		(clk),
			.reset_L	(reset_L),
			.idx		(idx[3:0]),
			.dataA		(dataA[3:0]),
			.dataB		(dataB[3:0]));

	sumador_Synth sumador_est(

				  .idx_dd		(idx_dd_estruc[3:0]),
				  .sum30_dd		(sum30_dd_estruc[3:0]),

				  .clk			(clk),
				  .dataA		(dataA[3:0]),
				  .dataB		(dataB[3:0]),
				  .idx			(idx[3:0]),
				  .reset_L		(reset_L));
	
    probador test0(

		   .clk			(clk),
		   .reset_L		(reset_L),
		   .idx			(idx[3:0]),
		   .dataA		(dataA[3:0]),
		   .dataB		(dataB[3:0]),

		   .idx_dd_cond		(idx_dd_cond[3:0]),
		   .idx_dd_estruc	(idx_dd_estruc[3:0]),
		   .sum30_dd_cond	(sum30_dd_cond[3:0]),
		   .sum30_dd_estruc	(sum30_dd_estruc[3:0]));

endmodule