data/full_repos/permissive/102388603/rmii_rx_byte.v
data/verilator_xmls/33c905a7-bc2d-4d49-b9a7-c12e97671a6b.xml
module rmii_rx_byte
(
	input rst,
	input clk,
	input rmii_clk,
	input fast_eth,
	input [1:0]rm_rx_data,
	input rm_crs_dv,
	output reg [7:0]data,
	output reg rdy,
	output reg busy
);


reg [1:0]s_rm_rx_data;
reg s_rm_crs_dv;
reg s_rmii_clk;

always @(posedge rst, posedge clk)
	if(rst)
		{s_rm_rx_data, s_rm_crs_dv, s_rmii_clk} <= 0;
	else
		{s_rm_rx_data, s_rm_crs_dv, s_rmii_clk} <= {rm_rx_data, rm_crs_dv, rmii_clk};

reg [4:0]wait_cnt;
reg [7:0]rx_data;

reg [1:0]stop;


always @(posedge rst, posedge clk)
    begin
	if(rst)
		begin
			data <= 0;
			rx_data <= 0;
			wait_cnt <= 0;
			rdy <= 0;
			busy <= 0;
			stop <= 0;
		end	
	else
        begin
            if(rdy)
                rdy <= 0;
            if(wait_cnt == 0)
                begin
                    if(!busy)
                    begin
                        stop <= 0;
                            if(s_rm_crs_dv)
                            begin
                                if(s_rmii_clk)
                                begin
                                    if(rx_data == 8'hD5)
                                        begin
                                            busy <= 1;
                                            rx_data <= {s_rm_rx_data, 6'b11_0000};
                                        end
                                    else
                                        rx_data <= {s_rm_rx_data, rx_data[7:2]};
                                    if(!fast_eth)
                                        wait_cnt <= 18;
                                end
                            end
                            else
                                rx_data <= 0;
                    end							
                    else
                        begin
                            if((s_rm_crs_dv) | (stop == 2'b01))
                                begin
                                    if(s_rmii_clk)
                                        begin
                                            if(rx_data[1:0] == 2'b11)
                                                begin
                                                    data <= {s_rm_rx_data, rx_data[7:2]};
                                                    rx_data <= 8'b11_00_0000;
                                                    if(stop==2'b01)
                                                        stop <= 2'b10;
                                                    rdy <= 1;
                                                end
                                                    else
                                                        rx_data <= {s_rm_rx_data, rx_data[7:2]};
                                                    if(!fast_eth)
                                                        wait_cnt <= 18;
                                        end
                                end
                            else
                                begin
                                    if((fast_eth )|(stop == 2'b10))
                                        begin
                                            stop <= 0;			
                                            busy <= 0;
                                            rx_data <= 0;
                                        end 
                                    else
                                        stop <= 2'b01;
                                end
                        end							
                end
    
				else
					wait_cnt <= wait_cnt - 1;
			end
		end	
endmodule
module rmii_rx_byte
(
	input rst,
	input clk,
	input rmii_clk,
	input fast_eth,
	input [1:0]rm_rx_data,
	input rm_crs_dv,
	output reg [7:0]data,
	output reg rdy,
	output reg busy
);



reg [1:0]s_rm_rx_data;
reg s_rm_crs_dv;
reg s_rmii_clk;

always @(posedge rst, posedge clk)
	if(rst)
		{s_rm_rx_data, s_rm_crs_dv, s_rmii_clk} <= 0;
	else
		{s_rm_rx_data, s_rm_crs_dv, s_rmii_clk} <= {rm_rx_data, rm_crs_dv, rmii_clk};

reg [4:0]wait_cnt;
reg [7:0]rx_data;

reg [1:0]stop;


always @(posedge rst, posedge clk)
    begin
	if(rst)
		begin
			data <= 0;
			rx_data <= 0;
			wait_cnt <= 0;
			rdy <= 0;
			busy <= 0;
			stop <= 0;
		end	
	else
        begin
            if(rdy)
                rdy <= 0;
            if(wait_cnt == 0)
                begin
                    if(!busy)
                    begin
                        stop <= 0;
                            if(s_rm_crs_dv)
                            begin
                                if(s_rmii_clk)
                                begin
                                    if(rx_data == 8'hD5)
                                        begin
                                            busy <= 1;
                                            rx_data <= {s_rm_rx_data, 6'b11_0000};
                                        end
                                    else
                                        rx_data <= {s_rm_rx_data, rx_data[7:2]};
                                    if(!fast_eth)
                                        wait_cnt <= 18;
                                end
                            end
                            else
                                rx_data <= 0;
                    end							
                    else
                        begin
                            if((s_rm_crs_dv) | (stop == 2'b01))
                                begin
                                    if(s_rmii_clk)
                                        begin
                                            if(rx_data[1:0] == 2'b11)
                                                begin
                                                    data <= {s_rm_rx_data, rx_data[7:2]};
                                                    rx_data <= 8'b11_00_0000;
                                                    if(stop==2'b01)
                                                        stop <= 2'b10;
                                                    rdy <= 1;
                                                end
                                                    else
                                                        rx_data <= {s_rm_rx_data, rx_data[7:2]};
                                                    if(!fast_eth)
                                                        wait_cnt <= 18;
                                        end
                                end
                            else
                                begin
                                    if((fast_eth )|(stop == 2'b10))
                                        begin
                                            stop <= 0;			
                                            busy <= 0;
                                            rx_data <= 0;
                                        end 
                                    else
                                        stop <= 2'b01;
                                end
                        end							
                end
    
				else
					wait_cnt <= wait_cnt - 1;
			end
		end	
endmodule