data/full_repos/permissive/12880408/addsub.v
data/verilator_xmls/131295c0-e8af-4acd-a64d-3be9c9eda9bc.xml
module addsub(Sub, A, B, Out);
	input [8:0] A, B;
	input Sub;
	output [8:0] Out;
	
	assign Out = Sub ? A - B : A + B;
	
endmodule
module addsub(Sub, A, B, Out);

	input [8:0] A, B;
	input Sub;
	output [8:0] Out;
	
	assign Out = Sub ? A - B : A + B;
	
endmodule