data/full_repos/permissive/200478172/source/pcreg.v
data/verilator_xmls/2e5b4efd-3a25-446a-af25-798d51ff5423.xml
module pcreg(
    input clk,
    input ctr,
    input ena,
    input rst,
    input [31:0] data_in,
    
    output reg [31:0] data_out 
    );
    wire[31:0]temp;
    assign temp=(ctr)?data_in:temp;
    always @(negedge clk or posedge ena or posedge rst)
    begin
        if(rst) data_out = 32'h0040_0000;
        else if(ena) data_out = temp;
        else data_out = data_out;
    end
endmodule
module pcreg(
    input clk,
    input ctr,
    input ena,
    input rst,
    input [31:0] data_in,
    
    output reg [31:0] data_out 
    );

    wire[31:0]temp;
    assign temp=(ctr)?data_in:temp;
    always @(negedge clk or posedge ena or posedge rst)
    begin
        if(rst) data_out = 32'h0040_0000;
        else if(ena) data_out = temp;
        else data_out = data_out;
    end
endmodule