data/full_repos/permissive/139213403/FPGA/blastit_demo_daylight.v
data/verilator_xmls/efe6e510-f4b2-4089-a28b-7284e2d8af41.xml
module blastit_demo_daylight
(



	input wire CLOCK_50,




	input wire DAYLIGHT,
	



	input wire UART_RX,
	



	output wire[7:0] C_SSEG,
	



	output wire[15:0] C,
	



	output wire[9:0] D,
	



	output wire[9:0] G,
	



	output wire UART_TX,
	



	output wire[3:0] LED,
	



	output wire WARN
);

	assign WARN = DAYLIGHT;
	
	assign LED = { DAYLIGHT, ~DAYLIGHT, DAYLIGHT, ~DAYLIGHT };

endmodule
module blastit_demo_daylight
(



	input wire CLOCK_50,




	input wire DAYLIGHT,
	



	input wire UART_RX,
	



	output wire[7:0] C_SSEG,
	



	output wire[15:0] C,
	



	output wire[9:0] D,
	



	output wire[9:0] G,
	



	output wire UART_TX,
	



	output wire[3:0] LED,
	



	output wire WARN
);


	assign WARN = DAYLIGHT;
	
	assign LED = { DAYLIGHT, ~DAYLIGHT, DAYLIGHT, ~DAYLIGHT };

endmodule