data/full_repos/permissive/100975158/ProcessadorQuartus/RegPipeline.v
data/verilator_xmls/802da568-1d9f-4a0b-a804-a5a06a38a7bd.xml
module RegPipeline(
	input clock, parada, limpar,
	input wire [TAM-1:0] in,
	output reg [TAM-1:0] out
	);
			

	parameter TAM = 32; 
	
	always @ ( posedge clock ) begin

		if (limpar)
			out <= {TAM{1'b0}};

		else if (parada)
			out <= out;

		else
			out <= in;
	end
						 
endmodule
module RegPipeline(
	input clock, parada, limpar,
	input wire [TAM-1:0] in,
	output reg [TAM-1:0] out
	);

			

	parameter TAM = 32; 
	
	always @ ( posedge clock ) begin

		if (limpar)
			out <= {TAM{1'b0}};

		else if (parada)
			out <= out;

		else
			out <= in;
	end
						 
endmodule