data/full_repos/permissive/173670949/gtkwave/test.v
 line:17: before: "$"
1: b'%Error: data/full_repos/permissive/173670949/gtkwave/test.v:9: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/173670949/gtkwave/test.v:10: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/173670949/gtkwave/test.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #0 reset = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173670949/gtkwave/test.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #1 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173670949/gtkwave/test.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #1 level = 100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173670949/gtkwave/test.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #22 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173670949/gtkwave/test.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #15 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173670949/gtkwave/test.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #10000 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173670949/gtkwave/test.v:22: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = !clk;\n           ^\n%Error: data/full_repos/permissive/173670949/gtkwave/test.v:32: Unsupported or unknown PLI call: $monitor\n        $monitor("Time %t value = %d", $time, value);\n        ^~~~~~~~\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

    reg reset = 0;
    reg [7:0] level = 0;

    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0, test);

        #0 reset = 1;
        #1 reset = 0;
        #1 level = 100;
        #22 reset = 1;
        #15 reset = 0;
        #10000 $finish;
    end


    reg clk = 0;
    always #1 clk = !clk;

    wire [7:0] value;
    wire pwm_out;
    counter c (clk, value, reset);
    PWM pwm(clk, level, pwm_out);

    UART_RX #(.CLKS_PER_BIT(213)) uart();

    initial begin
        $monitor("Time %t value = %d", $time, value);
    end

endmodule
module test;


    reg reset = 0;
    reg [7:0] level = 0;

    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0, test);

        #0 reset = 1;
        #1 reset = 0;
        #1 level = 100;
        #22 reset = 1;
        #15 reset = 0;
        #10000 $finish;
    end


    reg clk = 0;
    always #1 clk = !clk;

    wire [7:0] value;
    wire pwm_out;
    counter c (clk, value, reset);
    PWM pwm(clk, level, pwm_out);

    UART_RX #(.CLKS_PER_BIT(213)) uart();

    initial begin
        $monitor("Time %t value = %d", $time, value);
    end

endmodule