data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/mux_tb.v
 line:75: before: ";"
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/mux_tb.v:40: syntax error, unexpected \'@\'\n    @(posedge op_clock);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/mux_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #op_clk_period op_clock_reg = ~op_clock_reg; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog_testbench/mux_tb.v:72: Unsupported: wait statements\nalways wait (config_done)  \n       ^~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module cmos_mux2level_tb;

parameter SIZE_OF_MUX = 50;
parameter SIZE_OF_SRAM = 16;
parameter op_clk_period = 1;
parameter operating_period =  SIZE_OF_MUX * 2 * op_clk_period;


wire [0:SIZE_OF_MUX-1] in;
wire out;
wire [0:SIZE_OF_SRAM-1] sram;
wire [0:SIZE_OF_SRAM-1] sram_inv; 

wire op_clock;

reg op_clock_reg;
reg [0:SIZE_OF_MUX-1] in_reg;
reg [0:SIZE_OF_SRAM-1] sram_reg;
reg [0:SIZE_OF_SRAM-1] sram_inv_reg;

reg config_done;

reg temp;


mux_2level_size50 U0 (in, out, sram, sram_inv);


task op_mux_input;
  begin
    @(posedge op_clock);
    temp = in_reg[SIZE_OF_MUX-1];
    in_reg[1:SIZE_OF_MUX-1] = in_reg[0:SIZE_OF_MUX-2];
    in_reg[0] = temp;
  end 
endtask


initial
begin
  config_done = 1'b1;
end


initial 
begin
  op_clock_reg = 1'b0;
end
always
begin
  #op_clk_period op_clock_reg = ~op_clock_reg; 
end


assign op_clock = op_clock_reg & config_done;


initial
begin
  in_reg = {SIZE_OF_MUX {1'b0}}; 
  in_reg[0] = 1'b1;
end
always wait (config_done)
begin

  op_mux_input;
end


assign in = in_reg;
assign sram[0:7] = 8'b00010000;
assign sram[8:15] = 8'b00010000;
assign sram_inv = ~sram;

endmodule
module cmos_mux2level_tb;


parameter SIZE_OF_MUX = 50;
parameter SIZE_OF_SRAM = 16;
parameter op_clk_period = 1;
parameter operating_period =  SIZE_OF_MUX * 2 * op_clk_period;


wire [0:SIZE_OF_MUX-1] in;
wire out;
wire [0:SIZE_OF_SRAM-1] sram;
wire [0:SIZE_OF_SRAM-1] sram_inv; 

wire op_clock;

reg op_clock_reg;
reg [0:SIZE_OF_MUX-1] in_reg;
reg [0:SIZE_OF_SRAM-1] sram_reg;
reg [0:SIZE_OF_SRAM-1] sram_inv_reg;

reg config_done;

reg temp;


mux_2level_size50 U0 (in, out, sram, sram_inv);


task op_mux_input;
  begin
    @(posedge op_clock);
    temp = in_reg[SIZE_OF_MUX-1];
    in_reg[1:SIZE_OF_MUX-1] = in_reg[0:SIZE_OF_MUX-2];
    in_reg[0] = temp;
  end 
endtask


initial
begin
  config_done = 1'b1;
end


initial 
begin
  op_clock_reg = 1'b0;
end
always
begin
  #op_clk_period op_clock_reg = ~op_clock_reg; 
end


assign op_clock = op_clock_reg & config_done;


initial
begin
  in_reg = {SIZE_OF_MUX {1'b0}}; 
  in_reg[0] = 1'b1;
end
always wait (config_done)
begin

  op_mux_input;
end


assign in = in_reg;
assign sram[0:7] = 8'b00010000;
assign sram[8:15] = 8'b00010000;
assign sram_inv = ~sram;

endmodule