data/full_repos/permissive/2084115/rtl/library/jelly2_data_shift_register_lut.sv
 line:16: before: "SEL_WIDTH"
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/library/jelly2_data_shift_register_lut.sv:38: Operator EQ expects 64 bits on the LHS, but LHS\'s VARREF \'DEVICE\' generates 24 bits.\n                                                                                                   : ... In instance jelly2_data_shift_register_lut\n            && (DEVICE == "SPARTAN6"\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/library/jelly2_data_shift_register_lut.sv:39: Operator EQ expects 56 bits on the LHS, but LHS\'s VARREF \'DEVICE\' generates 24 bits.\n                                                                                                   : ... In instance jelly2_data_shift_register_lut\n             || DEVICE == "VIRTEX6"\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/library/jelly2_data_shift_register_lut.sv:40: Operator EQ expects 56 bits on the LHS, but LHS\'s VARREF \'DEVICE\' generates 24 bits.\n                                                                                                   : ... In instance jelly2_data_shift_register_lut\n             || DEVICE == "7SERIES"\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/library/jelly2_data_shift_register_lut.sv:41: Operator EQ expects 80 bits on the LHS, but LHS\'s VARREF \'DEVICE\' generates 24 bits.\n                                                                                                   : ... In instance jelly2_data_shift_register_lut\n             || DEVICE == "ULTRASCALE"\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/library/jelly2_data_shift_register_lut.sv:42: Operator EQ expects 152 bits on the LHS, but LHS\'s VARREF \'DEVICE\' generates 24 bits.\n                                                                                                   : ... In instance jelly2_data_shift_register_lut\n             || DEVICE == "ULTRASCALE_PLUS_ES1"\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/library/jelly2_data_shift_register_lut.sv:43: Operator EQ expects 152 bits on the LHS, but LHS\'s VARREF \'DEVICE\' generates 24 bits.\n                                                                                                   : ... In instance jelly2_data_shift_register_lut\n             || DEVICE == "ULTRASCALE_PLUS_ES2") ) begin : xilinx_srlc32e\n                       ^~\n%Error: Exiting due to 6 warning(s)\n'
module jelly2_data_shift_register_lut
        #(
            parameter   int     SEL_WIDTH  = 5,
            parameter   int     NUM        = (1 << SEL_WIDTH),
            parameter   int     DATA_WIDTH = 8,
            parameter           DEVICE     = "RTL"
        )
        (
            input   logic                       clk,
            input   logic                       cke,
            
            input   logic   [SEL_WIDTH-1:0]     sel,
            input   logic   [DATA_WIDTH-1:0]    in_data,
            output  logic   [DATA_WIDTH-1:0]    out_data
        );
    
`ifndef VERILATOR
    localparam bit  VERILATOR = 1'b1;
`else
    localparam bit  VERILATOR = 1'b0;
`endif
    
    generate
    if ( !VERILATOR && SEL_WIDTH <= 5
            && (DEVICE == "SPARTAN6"
             || DEVICE == "VIRTEX6"
             || DEVICE == "7SERIES"
             || DEVICE == "ULTRASCALE"
             || DEVICE == "ULTRASCALE_PLUS_ES1"
             || DEVICE == "ULTRASCALE_PLUS_ES2") ) begin : xilinx_srlc32e
        
        for ( genvar i = 0; i < DATA_WIDTH; i = i+1 ) begin : loop_shift

            wire    [4:0]   a = sel;
            SRLC32E
                    #(
                        .INIT   (32'h00000000)
                    )
                i_srlc32e
                    (
                        .Q      (out_data[i]),
                        .Q31    (),
                        .A      (a),
                        .CE     (cke),
                        .CLK    (clk),
                        .D      (in_data[i])
                    );
        end
    end
    else begin : blk_rtl

        logic   [NUM*DATA_WIDTH-1:0]    reg_data;
        always_ff @(posedge clk) begin
            if ( cke ) begin
                reg_data <= (NUM*DATA_WIDTH)'({reg_data, in_data});
            end
        end
        
        assign out_data = reg_data[sel*DATA_WIDTH +: DATA_WIDTH];
    end
    endgenerate
    
    
endmodule
module jelly2_data_shift_register_lut
        #(
            parameter   int     SEL_WIDTH  = 5,
            parameter   int     NUM        = (1 << SEL_WIDTH),
            parameter   int     DATA_WIDTH = 8,
            parameter           DEVICE     = "RTL"
        )
        (
            input   logic                       clk,
            input   logic                       cke,
            
            input   logic   [SEL_WIDTH-1:0]     sel,
            input   logic   [DATA_WIDTH-1:0]    in_data,
            output  logic   [DATA_WIDTH-1:0]    out_data
        );

    
`ifndef VERILATOR
    localparam bit  VERILATOR = 1'b1;
`else
    localparam bit  VERILATOR = 1'b0;
`endif
    
    generate
    if ( !VERILATOR && SEL_WIDTH <= 5
            && (DEVICE == "SPARTAN6"
             || DEVICE == "VIRTEX6"
             || DEVICE == "7SERIES"
             || DEVICE == "ULTRASCALE"
             || DEVICE == "ULTRASCALE_PLUS_ES1"
             || DEVICE == "ULTRASCALE_PLUS_ES2") ) begin : xilinx_srlc32e
        
        for ( genvar i = 0; i < DATA_WIDTH; i = i+1 ) begin : loop_shift

            wire    [4:0]   a = sel;
            SRLC32E
                    #(
                        .INIT   (32'h00000000)
                    )
                i_srlc32e
                    (
                        .Q      (out_data[i]),
                        .Q31    (),
                        .A      (a),
                        .CE     (cke),
                        .CLK    (clk),
                        .D      (in_data[i])
                    );
        end
    end
    else begin : blk_rtl

        logic   [NUM*DATA_WIDTH-1:0]    reg_data;
        always_ff @(posedge clk) begin
            if ( cke ) begin
                reg_data <= (NUM*DATA_WIDTH)'({reg_data, in_data});
            end
        end
        
        assign out_data = reg_data[sel*DATA_WIDTH +: DATA_WIDTH];
    end
    endgenerate
    
    
endmodule