data/full_repos/permissive/155085421/uart.v
1: b'%Warning-WIDTH: data/full_repos/permissive/155085421/uart.v:47: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                              : ... In instance uart\n            rx_data[bit_counter] <= rx;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module uart(
    input reset,
    input clock,


    input rx,
    input rts,
    output reg cts,
    input dtr,

    output reg receiving,
    output reg[7:0] rx_data,
    output reg rx_data_ready
    );





reg[3:0] bit_counter;
reg[2:0] pause_counter;
wire pause_is_over = pause_counter[0];

always @(posedge clock or posedge reset)
begin
    if (reset)
    begin
        bit_counter <= 0;
        pause_counter <= 3'b1;
        rx_data <= 0;
        rx_data_ready <= 0;
        receiving <= 0;
        cts <= 0;
    end
    else begin
        if (receiving)
        begin

            rx_data[bit_counter] <= rx;

            pause_counter <= 0;

            if (bit_counter == 7)
            begin

                receiving <= 0;
                rx_data_ready <= 1;
            end
            else begin

                bit_counter <= bit_counter + 1;
            end
        end
        else begin

            rx_data_ready <= 0;
            bit_counter <= 0;








            if (~rx)
            begin

                receiving <= 1;
                cts <= 1;
            end
        end
    end
end

endmodule
module uart(
    input reset,
    input clock,


    input rx,
    input rts,
    output reg cts,
    input dtr,

    output reg receiving,
    output reg[7:0] rx_data,
    output reg rx_data_ready
    );






reg[3:0] bit_counter;
reg[2:0] pause_counter;
wire pause_is_over = pause_counter[0];

always @(posedge clock or posedge reset)
begin
    if (reset)
    begin
        bit_counter <= 0;
        pause_counter <= 3'b1;
        rx_data <= 0;
        rx_data_ready <= 0;
        receiving <= 0;
        cts <= 0;
    end
    else begin
        if (receiving)
        begin

            rx_data[bit_counter] <= rx;

            pause_counter <= 0;

            if (bit_counter == 7)
            begin

                receiving <= 0;
                rx_data_ready <= 1;
            end
            else begin

                bit_counter <= bit_counter + 1;
            end
        end
        else begin

            rx_data_ready <= 0;
            bit_counter <= 0;








            if (~rx)
            begin

                receiving <= 1;
                cts <= 1;
            end
        end
    end
end

endmodule