data/full_repos/permissive/136702298/3.Código/codigo.v
 line:106: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/136702298/3.C\xc3\xb3digo/codigo.v:94: Unsupported: Ignoring delay on this delayed statement.\n    always #10 C=~C;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/136702298/3.C\xc3\xb3digo/codigo.v:99: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("cronograma.dmp"); \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/136702298/3.C\xc3\xb3digo/codigo.v:100: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1,CONT);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/136702298/3.C\xc3\xb3digo/codigo.v:101: Unsupported or unknown PLI call: $dumpon\n    $dumpon;\n    ^~~~~~~\n%Error: data/full_repos/permissive/136702298/3.C\xc3\xb3digo/codigo.v:104: Unsupported or unknown PLI call: $monitor\n    $monitor($time, " C=%b | Q=%d| Q=%b%b%b%b \\n",C,Q,Q[3],Q[2],Q[1],Q[0]);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/136702298/3.C\xc3\xb3digo/codigo.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #160 $finish; \n  ^\n%Error: data/full_repos/permissive/136702298/3.C\xc3\xb3digo/codigo.v:108: Unsupported or unknown PLI call: $dumpoff\n  $dumpoff; \n  ^~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module contador (inout wire [3:0] Q, input wire C);

    wire [3:0] QNEG;
    wire [3:0] J;
    wire [3:0] K;



            wire wireAND1J3, wireAND2J3;

            wire wireAND1K3, wireAND2K3;

            wire wireAND1J2,wireAND2J2,wireAND3J2;

            wire wireANDK2;


            wire wireAND1J0, wireAND2J0, wireAND3J0;




            and and1J3 (wireAND1J3,QNEG[0],QNEG[1],Q[2]);
            and and2J3 (wireAND2J3,Q[0],Q[1],QNEG[2]);
            or orJ3 (J[3],wireAND1J3,wireAND2J3);

            and and1K3 (wireAND1K3,Q[0],QNEG[1],Q[2]);
            and and2K3 (wireAND2K3,QNEG[0],Q[1],Q[2]);
            or orK3 (K[3],wireAND1K3,wireAND2K3);

            and and1J2 (wireAND1J2,Q[0],Q[1]);
            and and2J2 (wireAND2J2,QNEG[0],QNEG[1]);
            and and3J2 (wireAND3J2,QNEG[1],Q[3]);
            or orJ2 (J[2],wireAND1J2,wireAND2J2,wireAND3J2);

            and and1K2 (wireAND1K2,QNEG[0],Q[1],QNEG[3]);
            or orK2 (K[2],wireAND3J2,wireAND1K2);

            and andJ1 (J[1],QNEG[0],Q[2]);

            and andK1 (K[1],Q[0],QNEG[2]);

            and and1J0 (wireAND1J0,QNEG[1],Q[2],Q[3]);
            and and2J0 (wireAND2J0,Q[1],QNEG[2]);
            and and3J0 (wireAND3J0,Q[1],QNEG[3]);
            or orJ0 (J[0],wireAND1J0, wireAND2J0, wireAND3J0);

            or orK0 (K[0],Q[2],QNEG[3]);


    biestableJK JK3 (Q[3],QNEG[3],J[3],K[3],C);
    biestableJK JK2 (Q[2],QNEG[2],J[2],K[2],C);
    biestableJK JK1 (Q[1],QNEG[1],J[1],K[1],C);
    biestableJK JK0 (Q[0],QNEG[0],J[0],K[0],C);
	initial
	   begin
	   end
endmodule
module contador (inout wire [3:0] Q, input wire C);


    wire [3:0] QNEG;
    wire [3:0] J;
    wire [3:0] K;



            wire wireAND1J3, wireAND2J3;

            wire wireAND1K3, wireAND2K3;

            wire wireAND1J2,wireAND2J2,wireAND3J2;

            wire wireANDK2;


            wire wireAND1J0, wireAND2J0, wireAND3J0;




            and and1J3 (wireAND1J3,QNEG[0],QNEG[1],Q[2]);
            and and2J3 (wireAND2J3,Q[0],Q[1],QNEG[2]);
            or orJ3 (J[3],wireAND1J3,wireAND2J3);

            and and1K3 (wireAND1K3,Q[0],QNEG[1],Q[2]);
            and and2K3 (wireAND2K3,QNEG[0],Q[1],Q[2]);
            or orK3 (K[3],wireAND1K3,wireAND2K3);

            and and1J2 (wireAND1J2,Q[0],Q[1]);
            and and2J2 (wireAND2J2,QNEG[0],QNEG[1]);
            and and3J2 (wireAND3J2,QNEG[1],Q[3]);
            or orJ2 (J[2],wireAND1J2,wireAND2J2,wireAND3J2);

            and and1K2 (wireAND1K2,QNEG[0],Q[1],QNEG[3]);
            or orK2 (K[2],wireAND3J2,wireAND1K2);

            and andJ1 (J[1],QNEG[0],Q[2]);

            and andK1 (K[1],Q[0],QNEG[2]);

            and and1J0 (wireAND1J0,QNEG[1],Q[2],Q[3]);
            and and2J0 (wireAND2J0,Q[1],QNEG[2]);
            and and3J0 (wireAND3J0,Q[1],QNEG[3]);
            or orJ0 (J[0],wireAND1J0, wireAND2J0, wireAND3J0);

            or orK0 (K[0],Q[2],QNEG[3]);


    biestableJK JK3 (Q[3],QNEG[3],J[3],K[3],C);
    biestableJK JK2 (Q[2],QNEG[2],J[2],K[2],C);
    biestableJK JK1 (Q[1],QNEG[1],J[1],K[1],C);
    biestableJK JK0 (Q[0],QNEG[0],J[0],K[0],C);
	initial
	   begin
	   end
endmodule