data/full_repos/permissive/20759093/test_t.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/20759093/test_t.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_t.v:57: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk_in = ~clk_in;\n          ^\n%Error: data/full_repos/permissive/20759093/test_t.v:37: Cannot find file containing module: \'Single_Cycle_CPU\'\n Single_Cycle_CPU uut (\n ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/Single_Cycle_CPU\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/Single_Cycle_CPU.v\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/Single_Cycle_CPU.sv\n             Single_Cycle_CPU\n             Single_Cycle_CPU.v\n             Single_Cycle_CPU.sv\n             obj_dir/Single_Cycle_CPU\n             obj_dir/Single_Cycle_CPU.v\n             obj_dir/Single_Cycle_CPU.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_t;


	reg clk_in;
	reg btn_t;
	reg [5:0] sw;


	wire [6:0] seg;
	wire [3:0] an;


	Single_Cycle_CPU uut (
		.clk_in(clk_in), 
		.btn_t(btn_t), 
		.sw(sw), 
		.seg(seg), 
		.an(an)
	);

	initial begin

		clk_in = 0;
		btn_t = 0;
		sw = 0;


		#100;
        


	end
   always #10 clk_in = ~clk_in;
endmodule
module test_t;



	reg clk_in;
	reg btn_t;
	reg [5:0] sw;


	wire [6:0] seg;
	wire [3:0] an;


	Single_Cycle_CPU uut (
		.clk_in(clk_in), 
		.btn_t(btn_t), 
		.sw(sw), 
		.seg(seg), 
		.an(an)
	);

	initial begin

		clk_in = 0;
		btn_t = 0;
		sw = 0;


		#100;
        


	end
   always #10 clk_in = ~clk_in;
endmodule