data/full_repos/permissive/165873996/src/modified/eggs.v
1: b'%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/eggs.v:89: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'waiting\' generates 1 bits.\n                                                                           : ... In instance eggs\n            state_reg <= waiting;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/eggs.v:129: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'respawn\' generates 1 bits.\n                                                                            : ... In instance eggs\n      state_next = respawn;  \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/eggs.v:137: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'respawn\' generates 1 bits.\n                                                                            : ... In instance eggs\n      state_next = respawn;  \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/eggs.v:147: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'A_reg\' generates 8 bits.\n                                                                            : ... In instance eggs\n                    egg_x_next    = A_reg;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/eggs.v:165: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'D_reg\' generates 9 bits.\n                                                                            : ... In instance eggs\n                    egg_x_next    = D_reg;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/eggs.v:187: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'waiting\' generates 1 bits.\n                                                                            : ... In instance eggs\n                state_next = waiting;  \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/eggs.v:120: Operator CASE expects 2 bits on the Case Item, but Case Item\'s VARREF \'waiting\' generates 1 bits.\n                                                                            : ... In instance eggs\n        case(state_reg)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/eggs.v:120: Operator CASE expects 2 bits on the Case Item, but Case Item\'s VARREF \'respawn\' generates 1 bits.\n                                                                            : ... In instance eggs\n        case(state_reg)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/eggs.v:229: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 10 bits.\n                                                                            : ... In instance eggs\n    assign col = x - egg_x_reg;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/eggs.v:231: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'egg_type_offset\' generates 7 bits.\n                                                                            : ... In instance eggs\n    assign row = y + egg_type_offset - egg_y_reg;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/165873996/src/modified/eggs.v:231: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 10 bits.\n                                                                            : ... In instance eggs\n    assign row = y + egg_type_offset - egg_y_reg;\n               ^\n%Error: data/full_repos/permissive/165873996/src/modified/eggs.v:236: Cannot find file containing module: \'MK9_eggs_rom\'\n  MK9_eggs_rom eggs_rom_unit(.clock(clk), .address({row,col}), .q(rgb_out));\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165873996/src/modified,data/full_repos/permissive/165873996/MK9_eggs_rom\n             data/full_repos/permissive/165873996/src/modified,data/full_repos/permissive/165873996/MK9_eggs_rom.v\n             data/full_repos/permissive/165873996/src/modified,data/full_repos/permissive/165873996/MK9_eggs_rom.sv\n             MK9_eggs_rom\n             MK9_eggs_rom.v\n             MK9_eggs_rom.sv\n             obj_dir/MK9_eggs_rom\n             obj_dir/MK9_eggs_rom.v\n             obj_dir/MK9_eggs_rom.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n'
module eggs
    (
        input wire clk, reset,
        input wire [9:0] y_x, y_y,
        input direction,
        input wire [9:0] x, y,
        output eggs_on,
        output wire [11:0] rgb_out,
        output wire [13:0] score,
	output wire new_score
    );
   

    localparam LEFT = 0;
    localparam RIGHT = 1;
   

    reg [2:0] platform_select_reg;
    wire [2:0] platform_select_next;
	

    always @(posedge clk, posedge reset)
        if(reset)
            platform_select_reg <= 5;
        else
            platform_select_reg <= platform_select_next;
	
	assign  platform_select_next = platform_select_reg + 1;
   

    reg [9:0] egg_x_reg, egg_x_next, egg_y_reg, egg_y_next;
    reg [5:0] egg_type_reg, egg_type_next;
   

    always @(posedge clk, posedge reset)
        if(reset)
            begin
            egg_x_reg    <= 296;
            egg_y_reg    <= 364;
            egg_type_reg <= 0;
            end
        else
            begin
            egg_x_reg    <= egg_x_next;
            egg_y_reg    <= egg_y_next;
            egg_type_reg <= egg_type_next;
            end
           



    reg[7:0] A_reg;
    reg[9:0] B_reg;
    reg[9:0] C_reg;
    reg[8:0] D_reg;
    reg[9:0] E_reg;
    reg[9:0] F_reg;
    reg[9:0] G_reg;
   

    always @(posedge clk, posedge reset)
        if(reset)
            begin
            A_reg <=  16;
            B_reg <= 480;
            C_reg <=  80;
            D_reg <=  16;
            E_reg <= 384;
            F_reg <= 296;
            G_reg <=  16;
            end
        else
            begin
            A_reg <= (A_reg <= 144)? A_reg + 1 :  16;
            B_reg <= (B_reg <= 608)? B_reg + 1 : 480;
            C_reg <= (C_reg <= 545)? C_reg + 1 :  80;
            D_reg <= (D_reg <= 240)? D_reg + 1 :  16;
            E_reg <= (E_reg <= 608)? E_reg + 1 : 384;
            F_reg <= (F_reg <= 513)? F_reg + 1 : 112;
            G_reg <= (G_reg <= 608)? G_reg + 1 :  16;
            end
 

    reg [1:0] state_reg, state_next;
    

    always @(posedge clk, posedge reset)
        if(reset)
            state_reg <= waiting;
        else
            state_reg <= state_next;
			

    reg new_score_reg, new_score_next; 
	

    always @(posedge clk, posedge reset)
    if(reset)
	    new_score_reg <= 0;
    else
            new_score_reg <= new_score_next;
	

    assign new_score = new_score_reg;
   

    localparam  waiting    = 1'b0,
                respawn    = 1'b1;
    

    always @*
        begin

        state_next = state_reg;
        egg_x_next = egg_x_reg;
        egg_y_next = egg_y_reg;
        egg_type_next = egg_type_reg;
	new_score_next = 0;
       
        case(state_reg)
           
            waiting:
                begin

                if(direction == LEFT && (egg_x_reg + 13 > y_x && egg_x_reg < y_x + 13 && egg_y_reg + 13 > y_y && egg_y_reg < y_y + 13) ||
                  (egg_x_reg + 13 > y_x + 9 && egg_x_reg < y_x + 16 && egg_y_reg + 13 > y_y + 13 && egg_y_reg < y_y + 18))
                    begin
		    new_score_next = 1;
		    state_next = respawn;
		    end
                

                else if(direction == RIGHT && (egg_x_reg + 13 > y_x + 9 && egg_x_reg < y_x + 16 && egg_y_reg + 13 > y_y && egg_y_reg < y_y + 13) ||
                       (egg_x_reg + 13 > y_x && egg_x_reg < y_x + 13 && egg_y_reg + 13 > y_y + 13 && egg_y_reg < y_y + 18))
                    begin
		    new_score_next = 1;
		    state_next = respawn;
		    end
                end

            respawn:

                begin
                if(platform_select_reg == 0)
                    begin
                    egg_y_next    = 116;
                    egg_x_next    = A_reg;
                    egg_type_next = A_reg[5:0];
                    end
                else if(platform_select_reg == 1)
                    begin
                    egg_y_next    = 116;
                    egg_x_next    = B_reg;
                    egg_type_next = B_reg[5:0];
                    end
                else if(platform_select_reg == 2)
                    begin
                    egg_y_next    = 199;
                    egg_x_next    = C_reg;
                    egg_type_next = C_reg[5:0];
                    end
                else if(platform_select_reg == 3)
                    begin
                    egg_y_next    = 282;
                    egg_x_next    = D_reg;
                    egg_type_next = D_reg[5:0];
                    end
                else if(platform_select_reg == 4)
                    begin
                    egg_y_next    = 282;
                    egg_x_next    = E_reg;
                    egg_type_next = E_reg[5:0];
                    end
                else if(platform_select_reg == 5)
                    begin
                    egg_y_next    = 365;
                    egg_x_next    = F_reg;
                    egg_type_next = F_reg[5:0];
                    end
                else
                    begin
                    egg_y_next    = 448;
                    egg_x_next    = G_reg;
                    egg_type_next = G_reg[5:0];
                    end
               
                state_next = waiting;
                end
        endcase
        end
   


    wire [6:0] egg_type_offset;
    assign egg_type_offset = (egg_type_reg <= 29) ? 0 :
                             (egg_type_reg > 29  && egg_type_reg <= 44) ? 16 :
                             (egg_type_reg > 44  && egg_type_reg <= 54) ? 32 :
                             (egg_type_reg > 54  && egg_type_reg <= 62) ? 48 : 64;
    

    reg [13:0] score_reg;
    wire [13:0] score_next;
	

    always @(posedge clk, posedge reset)
    if(reset)
	    score_reg <= 0;
    else
            score_reg <= score_next;
	

    assign score_next = (reset || new_score_next && score_reg == 9999) ? 0 : 
			new_score_next && egg_type_offset ==  0 ? score_reg +   20:
			new_score_next && egg_type_offset == 16 ? score_reg +   40:
			new_score_next && egg_type_offset == 32 ? score_reg +   60:
			new_score_next && egg_type_offset == 48 ? score_reg +  200:
			new_score_next && egg_type_offset == 64 ? score_reg +  500:
			score_reg;
	

    assign score = score_reg;
   


    wire [3:0] col;
    wire [6:0] row;
   

    assign col = x - egg_x_reg;

    assign row = y + egg_type_offset - egg_y_reg;
   


`ifndef ICARUS_SIMULATOR
	 MK9_eggs_rom eggs_rom_unit(.clock(clk), .address({row,col}), .q(rgb_out));
`endif
   

    assign eggs_on = (x >= egg_x_reg && x < egg_x_reg + 16 && y >= egg_y_reg && y < egg_y_reg + 16)
                     && (rgb_out != 12'b011011011110) ? 1 : 0;                    
endmodule
module eggs
    (
        input wire clk, reset,
        input wire [9:0] y_x, y_y,
        input direction,
        input wire [9:0] x, y,
        output eggs_on,
        output wire [11:0] rgb_out,
        output wire [13:0] score,
	output wire new_score
    );

   

    localparam LEFT = 0;
    localparam RIGHT = 1;
   

    reg [2:0] platform_select_reg;
    wire [2:0] platform_select_next;
	

    always @(posedge clk, posedge reset)
        if(reset)
            platform_select_reg <= 5;
        else
            platform_select_reg <= platform_select_next;
	
	assign  platform_select_next = platform_select_reg + 1;
   

    reg [9:0] egg_x_reg, egg_x_next, egg_y_reg, egg_y_next;
    reg [5:0] egg_type_reg, egg_type_next;
   

    always @(posedge clk, posedge reset)
        if(reset)
            begin
            egg_x_reg    <= 296;
            egg_y_reg    <= 364;
            egg_type_reg <= 0;
            end
        else
            begin
            egg_x_reg    <= egg_x_next;
            egg_y_reg    <= egg_y_next;
            egg_type_reg <= egg_type_next;
            end
           



    reg[7:0] A_reg;
    reg[9:0] B_reg;
    reg[9:0] C_reg;
    reg[8:0] D_reg;
    reg[9:0] E_reg;
    reg[9:0] F_reg;
    reg[9:0] G_reg;
   

    always @(posedge clk, posedge reset)
        if(reset)
            begin
            A_reg <=  16;
            B_reg <= 480;
            C_reg <=  80;
            D_reg <=  16;
            E_reg <= 384;
            F_reg <= 296;
            G_reg <=  16;
            end
        else
            begin
            A_reg <= (A_reg <= 144)? A_reg + 1 :  16;
            B_reg <= (B_reg <= 608)? B_reg + 1 : 480;
            C_reg <= (C_reg <= 545)? C_reg + 1 :  80;
            D_reg <= (D_reg <= 240)? D_reg + 1 :  16;
            E_reg <= (E_reg <= 608)? E_reg + 1 : 384;
            F_reg <= (F_reg <= 513)? F_reg + 1 : 112;
            G_reg <= (G_reg <= 608)? G_reg + 1 :  16;
            end
 

    reg [1:0] state_reg, state_next;
    

    always @(posedge clk, posedge reset)
        if(reset)
            state_reg <= waiting;
        else
            state_reg <= state_next;
			

    reg new_score_reg, new_score_next; 
	

    always @(posedge clk, posedge reset)
    if(reset)
	    new_score_reg <= 0;
    else
            new_score_reg <= new_score_next;
	

    assign new_score = new_score_reg;
   

    localparam  waiting    = 1'b0,
                respawn    = 1'b1;
    

    always @*
        begin

        state_next = state_reg;
        egg_x_next = egg_x_reg;
        egg_y_next = egg_y_reg;
        egg_type_next = egg_type_reg;
	new_score_next = 0;
       
        case(state_reg)
           
            waiting:
                begin

                if(direction == LEFT && (egg_x_reg + 13 > y_x && egg_x_reg < y_x + 13 && egg_y_reg + 13 > y_y && egg_y_reg < y_y + 13) ||
                  (egg_x_reg + 13 > y_x + 9 && egg_x_reg < y_x + 16 && egg_y_reg + 13 > y_y + 13 && egg_y_reg < y_y + 18))
                    begin
		    new_score_next = 1;
		    state_next = respawn;
		    end
                

                else if(direction == RIGHT && (egg_x_reg + 13 > y_x + 9 && egg_x_reg < y_x + 16 && egg_y_reg + 13 > y_y && egg_y_reg < y_y + 13) ||
                       (egg_x_reg + 13 > y_x && egg_x_reg < y_x + 13 && egg_y_reg + 13 > y_y + 13 && egg_y_reg < y_y + 18))
                    begin
		    new_score_next = 1;
		    state_next = respawn;
		    end
                end

            respawn:

                begin
                if(platform_select_reg == 0)
                    begin
                    egg_y_next    = 116;
                    egg_x_next    = A_reg;
                    egg_type_next = A_reg[5:0];
                    end
                else if(platform_select_reg == 1)
                    begin
                    egg_y_next    = 116;
                    egg_x_next    = B_reg;
                    egg_type_next = B_reg[5:0];
                    end
                else if(platform_select_reg == 2)
                    begin
                    egg_y_next    = 199;
                    egg_x_next    = C_reg;
                    egg_type_next = C_reg[5:0];
                    end
                else if(platform_select_reg == 3)
                    begin
                    egg_y_next    = 282;
                    egg_x_next    = D_reg;
                    egg_type_next = D_reg[5:0];
                    end
                else if(platform_select_reg == 4)
                    begin
                    egg_y_next    = 282;
                    egg_x_next    = E_reg;
                    egg_type_next = E_reg[5:0];
                    end
                else if(platform_select_reg == 5)
                    begin
                    egg_y_next    = 365;
                    egg_x_next    = F_reg;
                    egg_type_next = F_reg[5:0];
                    end
                else
                    begin
                    egg_y_next    = 448;
                    egg_x_next    = G_reg;
                    egg_type_next = G_reg[5:0];
                    end
               
                state_next = waiting;
                end
        endcase
        end
   


    wire [6:0] egg_type_offset;
    assign egg_type_offset = (egg_type_reg <= 29) ? 0 :
                             (egg_type_reg > 29  && egg_type_reg <= 44) ? 16 :
                             (egg_type_reg > 44  && egg_type_reg <= 54) ? 32 :
                             (egg_type_reg > 54  && egg_type_reg <= 62) ? 48 : 64;
    

    reg [13:0] score_reg;
    wire [13:0] score_next;
	

    always @(posedge clk, posedge reset)
    if(reset)
	    score_reg <= 0;
    else
            score_reg <= score_next;
	

    assign score_next = (reset || new_score_next && score_reg == 9999) ? 0 : 
			new_score_next && egg_type_offset ==  0 ? score_reg +   20:
			new_score_next && egg_type_offset == 16 ? score_reg +   40:
			new_score_next && egg_type_offset == 32 ? score_reg +   60:
			new_score_next && egg_type_offset == 48 ? score_reg +  200:
			new_score_next && egg_type_offset == 64 ? score_reg +  500:
			score_reg;
	

    assign score = score_reg;
   


    wire [3:0] col;
    wire [6:0] row;
   

    assign col = x - egg_x_reg;

    assign row = y + egg_type_offset - egg_y_reg;
   


`ifndef ICARUS_SIMULATOR
	 MK9_eggs_rom eggs_rom_unit(.clock(clk), .address({row,col}), .q(rgb_out));
`endif
   

    assign eggs_on = (x >= egg_x_reg && x < egg_x_reg + 16 && y >= egg_y_reg && y < egg_y_reg + 16)
                     && (rgb_out != 12'b011011011110) ? 1 : 0;                    
endmodule