data/full_repos/permissive/143278/ivltests/pr585.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr585.v:11: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 8 bits.\n                                                                     : ... In instance main\n      mem = (ram_temp & 8\'h08) >> 3;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module main();

  reg [7:0] ram_temp;
  reg mem;

   initial begin
      ram_temp = 8'h08;
      mem = (ram_temp & 8'h08) >> 3;
      $write("Calculated: %b\nActually in mem: %b\n",((ram_temp & 8'h08) >> 3),
mem);
      if (mem !== 1'b1) begin
	 $display("FAILED == mem = %b", mem);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main();


  reg [7:0] ram_temp;
  reg mem;

   initial begin
      ram_temp = 8'h08;
      mem = (ram_temp & 8'h08) >> 3;
      $write("Calculated: %b\nActually in mem: %b\n",((ram_temp & 8'h08) >> 3),
mem);
      if (mem !== 1'b1) begin
	 $display("FAILED == mem = %b", mem);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule