data/full_repos/permissive/214823094/lab_5/project_1_1/project_1_1.srcs/sources_1/new/D_flip_flop.v
1: b"%Error: data/full_repos/permissive/214823094/lab_5/project_1_1/project_1_1.srcs/sources_1/new/D_flip_flop.v:32: Cannot find file containing module: 'clkdiv'\n    clkdiv c1(clk, myclk);\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214823094/lab_5/project_1_1/project_1_1.srcs/sources_1/new,data/full_repos/permissive/214823094/clkdiv\n             data/full_repos/permissive/214823094/lab_5/project_1_1/project_1_1.srcs/sources_1/new,data/full_repos/permissive/214823094/clkdiv.v\n             data/full_repos/permissive/214823094/lab_5/project_1_1/project_1_1.srcs/sources_1/new,data/full_repos/permissive/214823094/clkdiv.sv\n             clkdiv\n             clkdiv.v\n             clkdiv.sv\n             obj_dir/clkdiv\n             obj_dir/clkdiv.v\n             obj_dir/clkdiv.sv\n%Error: Exiting due to 1 error(s)\n"
module D_flip_flop(
    input clk,
    input d,
    input myset,
    input reset,
    output reg q
    );
    
    wire myclk;
    clkdiv c1(clk, myclk);
    
    always@(posedge myclk,posedge myset,posedge reset)
    begin
        if(myset&~reset)
            q<=1;
        else
            if(reset&~myset)
                q<=0;
            else
                q<=d;





    end
    
endmodule
module D_flip_flop(
    input clk,
    input d,
    input myset,
    input reset,
    output reg q
    );

    
    wire myclk;
    clkdiv c1(clk, myclk);
    
    always@(posedge myclk,posedge myset,posedge reset)
    begin
        if(myset&~reset)
            q<=1;
        else
            if(reset&~myset)
                q<=0;
            else
                q<=d;





    end
    
endmodule