data/full_repos/permissive/102515926/Modules/CIRCUIT2.v
1: b"%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:18: Cannot find file containing module: 'ADD'\n    ADD #(32) ADD_1(a, b, d);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.v\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.sv\n             ADD\n             ADD.v\n             ADD.sv\n             obj_dir/ADD\n             obj_dir/ADD.v\n             obj_dir/ADD.sv\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:19: Cannot find file containing module: 'ADD'\n    ADD #(32) ADD_2(a, c, e);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:20: Cannot find file containing module: 'SUB'\n    SUB #(32) SUB_1(a, b, f);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:21: Cannot find file containing module: 'COMP'\n    COMP #(32) COMP_1(d, e, dGTe, dLTe, dEQe);\n    ^~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:22: Cannot find file containing module: 'MUX2x1'\n    MUX2x1 #(32) MUX2x1_1(e, d, dLTe, g);\n    ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:23: Cannot find file containing module: 'MUX2x1'\n    MUX2x1 #(32) MUX2x1_2(f, g, dEQe, h);\n    ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:24: Cannot find file containing module: 'SHL'\n    SHL #(32) SHL_1(g, dLTe, xwire);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:25: Cannot find file containing module: 'SHR'\n    SHR #(32) SHR_1(h, dEQe, zwire);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:26: Cannot find file containing module: 'REG'\n    REG #(32) REG_1(xwire, Clk, Rst, x);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT2.v:27: Cannot find file containing module: 'REG'\n    REG #(32) REG_2(zwire, Clk, Rst, z);\n    ^~~\n%Error: Exiting due to 10 error(s)\n"
module CIRCUIT2(a, b, c, x, z, Clk, Rst);
    input [31:0] a, b, c;
    input Clk, Rst;
    output [31:0] x, z;
    
    wire [31:0] d, e, f, g, h;
    wire dLTe, dEQe, dGTe;
    wire [31:0] xwire, zwire;
    
    ADD #(32) ADD_1(a, b, d);
    ADD #(32) ADD_2(a, c, e);
    SUB #(32) SUB_1(a, b, f);
    COMP #(32) COMP_1(d, e, dGTe, dLTe, dEQe);
    MUX2x1 #(32) MUX2x1_1(e, d, dLTe, g);
    MUX2x1 #(32) MUX2x1_2(f, g, dEQe, h);
    SHL #(32) SHL_1(g, dLTe, xwire);
    SHR #(32) SHR_1(h, dEQe, zwire);
    REG #(32) REG_1(xwire, Clk, Rst, x);
    REG #(32) REG_2(zwire, Clk, Rst, z);
endmodule
module CIRCUIT2(a, b, c, x, z, Clk, Rst);

    input [31:0] a, b, c;
    input Clk, Rst;
    output [31:0] x, z;
    
    wire [31:0] d, e, f, g, h;
    wire dLTe, dEQe, dGTe;
    wire [31:0] xwire, zwire;
    
    ADD #(32) ADD_1(a, b, d);
    ADD #(32) ADD_2(a, c, e);
    SUB #(32) SUB_1(a, b, f);
    COMP #(32) COMP_1(d, e, dGTe, dLTe, dEQe);
    MUX2x1 #(32) MUX2x1_1(e, d, dLTe, g);
    MUX2x1 #(32) MUX2x1_2(f, g, dEQe, h);
    SHL #(32) SHL_1(g, dLTe, xwire);
    SHR #(32) SHR_1(h, dEQe, zwire);
    REG #(32) REG_1(xwire, Clk, Rst, x);
    REG #(32) REG_2(zwire, Clk, Rst, z);
endmodule