data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v
 line:94: before: "@"
1: b'%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:85: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("CBox_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:86: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_clb_out, w_ch_up_n, w_ch_dn_s, w_clb_in, inst);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:94: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:98: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:104: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:110: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:116: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:122: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:126: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:130: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:135: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:140: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:145: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:152: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:156: syntax error, unexpected \'@\'\n  #50@(posedge r_clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #50@(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:160: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:164: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:169: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:174: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:179: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:186: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:190: syntax error, unexpected \'@\'\n  #50@(posedge r_clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n  #50@(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:194: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:198: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:198: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:203: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:208: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:213: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:220: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:224: syntax error, unexpected \'@\'\n  #50@(posedge r_clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n  #50@(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:228: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:228: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:232: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:237: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:237: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:242: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:247: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:247: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:252: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:252: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n  #50 r_clk <= ~r_clk;\n  ^\n%Error: Exiting due to 35 error(s), 34 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CBox_tb;

	reg r_clk;
	reg r_mode;
	reg [17:0] r_c_bus;
	reg [1:0] r_c_dimension;
	reg [1:0] r_ch_up_s;
	reg [1:0] r_ch_dn_n;
	reg [1:0] r_clb_out;
	wire [1:0] w_ch_up_n;
	wire [1:0] w_ch_dn_s;
	wire [1:0] w_clb_in;

	CBox#(0, 4, 2, 2, 2, 2, 2, 16, 2) inst(
		.mode(r_mode),
		.c_clk(r_clk),
		.c_bus(r_c_bus),
		.c_dimension(r_c_dimension),

		.ch_up_n(w_ch_up_n),
		.ch_up_s(r_ch_up_s),
		.ch_dn_n(r_ch_dn_n),
		.ch_dn_s(w_ch_dn_s),

		.clb_in(w_clb_in),
		.clb_out(r_clb_out)
	);































	initial begin
		$dumpfile("CBox_tb.vcd");
		$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_clb_out, w_ch_up_n, w_ch_dn_s, w_clb_in, inst);
		r_clk <= 'b1;
		r_mode <= 'b0;
		r_c_bus <= 'h0;
		r_c_dimension <= 'h0;
		r_ch_up_s <= 'h3;
		r_ch_dn_n <= 'h3;
		r_clb_out <= 'h0;
		#100 @(posedge r_clk);


		r_mode <= 'b1;
		#100 @(posedge r_clk);




		r_c_bus <= {2'h0, 16'h0330};
		#50 @(posedge r_clk);




		r_c_bus <= {2'h1, 16'h0200};
		#50 @(posedge r_clk);




		r_c_bus <= {2'h2, 8'b00100000, 8'b00001000};
		#50 @(posedge r_clk);




		r_c_bus <= {2'h3, 8'b00000011, 8'b00000111};
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_clb_out <= 'h0;
		#50 @(posedge r_clk);



		r_clb_out <= 'h1;
		#50 @(posedge r_clk);



		r_clb_out <= 'h2;
		#50 @(posedge r_clk);



		r_clb_out <= 'h3;
		#50 @(posedge r_clk);





		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h1;
		#50@(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_clb_out <= 'h0;
		#50 @(posedge r_clk);



		r_clb_out <= 'h1;
		#50 @(posedge r_clk);



		r_clb_out <= 'h2;
		#50 @(posedge r_clk);



		r_clb_out <= 'h3;
		#50 @(posedge r_clk);





		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h2;
		#50@(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_clb_out <= 'h0;
		#50 @(posedge r_clk);



		r_clb_out <= 'h1;
		#50 @(posedge r_clk);



		r_clb_out <= 'h2;
		#50 @(posedge r_clk);



		r_clb_out <= 'h3;
		#50 @(posedge r_clk);





		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h3;
		#50@(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_clb_out <= 'h0;
		#50 @(posedge r_clk);



		r_clb_out <= 'h1;
		#50 @(posedge r_clk);



		r_clb_out <= 'h2;
		#50 @(posedge r_clk);



		r_clb_out <= 'h3;
		#50 @(posedge r_clk);




		#50 @(posedge r_clk);

		$finish;
	end

	always begin
		#50 r_clk <= ~r_clk;
	end

endmodule
module CBox_tb;


	reg r_clk;
	reg r_mode;
	reg [17:0] r_c_bus;
	reg [1:0] r_c_dimension;
	reg [1:0] r_ch_up_s;
	reg [1:0] r_ch_dn_n;
	reg [1:0] r_clb_out;
	wire [1:0] w_ch_up_n;
	wire [1:0] w_ch_dn_s;
	wire [1:0] w_clb_in;

	CBox#(0, 4, 2, 2, 2, 2, 2, 16, 2) inst(
		.mode(r_mode),
		.c_clk(r_clk),
		.c_bus(r_c_bus),
		.c_dimension(r_c_dimension),

		.ch_up_n(w_ch_up_n),
		.ch_up_s(r_ch_up_s),
		.ch_dn_n(r_ch_dn_n),
		.ch_dn_s(w_ch_dn_s),

		.clb_in(w_clb_in),
		.clb_out(r_clb_out)
	);































	initial begin
		$dumpfile("CBox_tb.vcd");
		$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_clb_out, w_ch_up_n, w_ch_dn_s, w_clb_in, inst);
		r_clk <= 'b1;
		r_mode <= 'b0;
		r_c_bus <= 'h0;
		r_c_dimension <= 'h0;
		r_ch_up_s <= 'h3;
		r_ch_dn_n <= 'h3;
		r_clb_out <= 'h0;
		#100 @(posedge r_clk);


		r_mode <= 'b1;
		#100 @(posedge r_clk);




		r_c_bus <= {2'h0, 16'h0330};
		#50 @(posedge r_clk);




		r_c_bus <= {2'h1, 16'h0200};
		#50 @(posedge r_clk);




		r_c_bus <= {2'h2, 8'b00100000, 8'b00001000};
		#50 @(posedge r_clk);




		r_c_bus <= {2'h3, 8'b00000011, 8'b00000111};
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_clb_out <= 'h0;
		#50 @(posedge r_clk);



		r_clb_out <= 'h1;
		#50 @(posedge r_clk);



		r_clb_out <= 'h2;
		#50 @(posedge r_clk);



		r_clb_out <= 'h3;
		#50 @(posedge r_clk);





		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h1;
		#50@(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_clb_out <= 'h0;
		#50 @(posedge r_clk);



		r_clb_out <= 'h1;
		#50 @(posedge r_clk);



		r_clb_out <= 'h2;
		#50 @(posedge r_clk);



		r_clb_out <= 'h3;
		#50 @(posedge r_clk);





		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h2;
		#50@(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_clb_out <= 'h0;
		#50 @(posedge r_clk);



		r_clb_out <= 'h1;
		#50 @(posedge r_clk);



		r_clb_out <= 'h2;
		#50 @(posedge r_clk);



		r_clb_out <= 'h3;
		#50 @(posedge r_clk);





		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h3;
		#50@(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_clb_out <= 'h0;
		#50 @(posedge r_clk);



		r_clb_out <= 'h1;
		#50 @(posedge r_clk);



		r_clb_out <= 'h2;
		#50 @(posedge r_clk);



		r_clb_out <= 'h3;
		#50 @(posedge r_clk);




		#50 @(posedge r_clk);

		$finish;
	end

	always begin
		#50 r_clk <= ~r_clk;
	end

endmodule