data/full_repos/permissive/150266237/parte1.v
 line:157: before: "$"
1: b'%Error: data/full_repos/permissive/150266237/parte1.v:138: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile ("out.vcd"); \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/150266237/parte1.v:139: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars; \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/150266237/parte1.v:145: Unsupported or unknown PLI call: $monitor\n     $monitor($time," c %b res %b a %b s %d smem %d sporta %d",c,res,a,saida,saida1,saida2);\n     ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:146: Unsupported: Ignoring delay on this delayed statement.\n      #1 res=0; a=2\'b10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:147: Unsupported: Ignoring delay on this delayed statement.\n      #1 res=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:148: Unsupported: Ignoring delay on this delayed statement.\n      #1 a=2\'b10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:149: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b11;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:150: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b01;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:151: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b00;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:152: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b11;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:153: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b00;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:154: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b00;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:155: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b01;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:156: Unsupported: Ignoring delay on this delayed statement.\n      #4\n      ^\n%Error: Exiting due to 3 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stateCase(input clk,input reset,input [1:0] a,output [2:0] saida);
reg [2:0] estado;

parameter zero = 3'b000 , um = 3'b001, dois = 3'b010, tres = 3'b011, quatro = 3'b100, cinco = 3'b101, seis = 3'b110, tres2 = 3'b111 ;

assign saida =  (estado == tres2) ? tres : estado;

    always @(posedge clk or  negedge reset) 
    begin
        if(reset == 0) estado = zero;
        else 
            case (estado)
                zero : estado = (a == 2'd0 || a == 2'd2) ? um : 
                                (a == 2'd1) ? dois : cinco;
                um : estado = (a == 2'd1 || a == 2'd0) ? dois : tres;
                dois : estado = (a == 2'd0) ? zero : (a == 2'd1) ? quatro : (a == 2'd2) ? tres2 : tres;
                tres : estado = (a == 2'd3) ? cinco : dois;
                quatro : estado = (a == 2'd0) ? zero : tres;
                cinco : estado = (a == 2'd0) ? zero : (a == 2'd3) ? seis : tres;
                seis : estado = (a == 2'd0) ? zero : tres;
                tres2 : estado = (a == 2'd2) ? um : (a == 2'd3) ? tres : dois;
            endcase
    end
endmodule
module stateCase(input clk,input reset,input [1:0] a,output [2:0] saida);

reg [2:0] estado;

parameter zero = 3'b000 , um = 3'b001, dois = 3'b010, tres = 3'b011, quatro = 3'b100, cinco = 3'b101, seis = 3'b110, tres2 = 3'b111 ;

assign saida =  (estado == tres2) ? tres : estado;

    always @(posedge clk or  negedge reset) 
    begin
        if(reset == 0) estado = zero;
        else 
            case (estado)
                zero : estado = (a == 2'd0 || a == 2'd2) ? um : 
                                (a == 2'd1) ? dois : cinco;
                um : estado = (a == 2'd1 || a == 2'd0) ? dois : tres;
                dois : estado = (a == 2'd0) ? zero : (a == 2'd1) ? quatro : (a == 2'd2) ? tres2 : tres;
                tres : estado = (a == 2'd3) ? cinco : dois;
                quatro : estado = (a == 2'd0) ? zero : tres;
                cinco : estado = (a == 2'd0) ? zero : (a == 2'd3) ? seis : tres;
                seis : estado = (a == 2'd0) ? zero : tres;
                tres2 : estado = (a == 2'd2) ? um : (a == 2'd3) ? tres : dois;
            endcase
    end
endmodule