data/full_repos/permissive/137301388/source/misc/clock_div.v
data/verilator_xmls/7b2a2cfd-0b3f-4626-9091-4abd0aba5707.xml
module clock_div(
clk_sys_i,
rst_n_i,

clk_16hz_o,
clk_8hz_o,
clk_1hz_o,
clk_128hz_o
);


parameter FREQ_SYSCLK = 12_000_000;


input clk_sys_i, rst_n_i;
output clk_16hz_o, clk_8hz_o, clk_1hz_o, clk_128hz_o;

reg[24:0] clk_cnt;



always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		clk_cnt <= 0;
	end
	else begin




			clk_cnt <= clk_cnt + 1'b1;
	end
end





wire clk_16hz_o = clk_cnt[19];
wire clk_8hz_o = clk_cnt[20];
wire clk_1hz_o = clk_cnt[23];
wire clk_128hz_o = clk_cnt[11];

endmodule
module clock_div(
clk_sys_i,
rst_n_i,

clk_16hz_o,
clk_8hz_o,
clk_1hz_o,
clk_128hz_o
);



parameter FREQ_SYSCLK = 12_000_000;


input clk_sys_i, rst_n_i;
output clk_16hz_o, clk_8hz_o, clk_1hz_o, clk_128hz_o;

reg[24:0] clk_cnt;



always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		clk_cnt <= 0;
	end
	else begin




			clk_cnt <= clk_cnt + 1'b1;
	end
end





wire clk_16hz_o = clk_cnt[19];
wire clk_8hz_o = clk_cnt[20];
wire clk_1hz_o = clk_cnt[23];
wire clk_128hz_o = clk_cnt[11];

endmodule