data/full_repos/permissive/160437780/Source/getFreq.v
 line:7: before: "="
data/verilator_xmls/b7a9ed29-4e08-4082-8bbf-8b69a00a9ef1.xml
module getFreq(
input CLK100MHZ,
input signal,
output reg [19:0] frequency = 0
);
parameter countTo = 100000000;
parameter scalar = 1000;


reg [26:0] clockCounter = 0; 
reg [19:0] pulses = 0; 

reg pastSigState = 0;
reg done = 0;





    always@(posedge CLK100MHZ) begin
        if (done) begin
            pulses <= 0;
            clockCounter <=0;
            done <= 0;
        end     

        else if(clockCounter < countTo) begin  

            clockCounter <= clockCounter +1; 
         
            if(signal && ~pastSigState) begin
                pulses <= pulses + 1; 
                pastSigState <= 1; 
            end
            else if(~signal) begin 
                pastSigState <= 0; 
            end        
        end
        else begin
            clockCounter <= 0;        
            frequency <= (pulses*scalar);
            done <= 1;
        end
    end
endmodule
module getFreq(
input CLK100MHZ,
input signal,
output reg [19:0] frequency = 0
);

parameter countTo = 100000000;
parameter scalar = 1000;


reg [26:0] clockCounter = 0; 
reg [19:0] pulses = 0; 

reg pastSigState = 0;
reg done = 0;





    always@(posedge CLK100MHZ) begin
        if (done) begin
            pulses <= 0;
            clockCounter <=0;
            done <= 0;
        end     

        else if(clockCounter < countTo) begin  

            clockCounter <= clockCounter +1; 
         
            if(signal && ~pastSigState) begin
                pulses <= pulses + 1; 
                pastSigState <= 1; 
            end
            else if(~signal) begin 
                pastSigState <= 0; 
            end        
        end
        else begin
            clockCounter <= 0;        
            frequency <= (pulses*scalar);
            done <= 1;
        end
    end
endmodule