data/full_repos/permissive/124591763/led/sevseg/sseg_drv_tb.v
 line:35: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/124591763/led/sevseg/sseg_drv_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk <= ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/124591763/led/sevseg/sseg_drv_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("sseg_drv_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/124591763/led/sevseg/sseg_drv_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/124591763/led/sevseg/sseg_drv_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #50  dat <= 32\'h12345678;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/led/sevseg/sseg_drv_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #50   en <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/led/sevseg/sseg_drv_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #100 mod <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/led/sevseg/sseg_drv_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #100 mod <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/led/sevseg/sseg_drv_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #100  en <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/led/sevseg/sseg_drv_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sseg_drv_tb;

	reg         clk = 1'b0;
	reg         en  = 1'b0;
	reg         mod = 1'b0;
	reg  [31:0] dat = 32'h0;
	wire [ 7:0] an;
	wire [ 7:0] seg;

	sseg_drv uut (
		.clk (clk),
		.en  (en ),
		.mod (mod),
		.dat (dat),
		.an  (an ),
		.seg (seg)
	);

	always #5 clk <= ~clk;

	initial begin
		$dumpfile("sseg_drv_tb.vcd");
		$dumpvars;

		#50  dat <= 32'h12345678;

		#50   en <= 1'b1;
		#100 mod <= 1'b1;
		#100 mod <= 1'b0;
		#100  en <= 1'b0;
		#50

		$display("simulation done");
		$finish;
	end

endmodule
module sseg_drv_tb;


	reg         clk = 1'b0;
	reg         en  = 1'b0;
	reg         mod = 1'b0;
	reg  [31:0] dat = 32'h0;
	wire [ 7:0] an;
	wire [ 7:0] seg;

	sseg_drv uut (
		.clk (clk),
		.en  (en ),
		.mod (mod),
		.dat (dat),
		.an  (an ),
		.seg (seg)
	);

	always #5 clk <= ~clk;

	initial begin
		$dumpfile("sseg_drv_tb.vcd");
		$dumpvars;

		#50  dat <= 32'h12345678;

		#50   en <= 1'b1;
		#100 mod <= 1'b1;
		#100 mod <= 1'b0;
		#100  en <= 1'b0;
		#50

		$display("simulation done");
		$finish;
	end

endmodule