data/full_repos/permissive/210844779/lab1/1.5/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.5/tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.5/tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab1/1.5/tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Error: data/full_repos/permissive/210844779/lab1/1.5/tb.v:6: Cannot find file containing module: \'freq_devide\'\nfreq_devide u0(.clk(clk),.Pre(Pre),.Rst(Rst),.Q(Q));\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab1/1.5,data/full_repos/permissive/210844779/freq_devide\n             data/full_repos/permissive/210844779/lab1/1.5,data/full_repos/permissive/210844779/freq_devide.v\n             data/full_repos/permissive/210844779/lab1/1.5,data/full_repos/permissive/210844779/freq_devide.sv\n             freq_devide\n             freq_devide.v\n             freq_devide.sv\n             obj_dir/freq_devide\n             obj_dir/freq_devide.v\n             obj_dir/freq_devide.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

reg clk,Pre,Rst;
wire Q;

freq_devide u0(.clk(clk),.Pre(Pre),.Rst(Rst),.Q(Q));

always
begin
  clk=1'b0; 
  #5
  clk=1'b1; 
  #5;
end
initial
begin
Rst=1'b1;
Pre=1'b0;
#10;
end

endmodule
module tb();


reg clk,Pre,Rst;
wire Q;

freq_devide u0(.clk(clk),.Pre(Pre),.Rst(Rst),.Q(Q));

always
begin
  clk=1'b0; 
  #5
  clk=1'b1; 
  #5;
end
initial
begin
Rst=1'b1;
Pre=1'b0;
#10;
end

endmodule