data/full_repos/permissive/143278/ivltests/mult2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult2.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk <= 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult2.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult2.v:55: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult2.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult2.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult2.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk <= 0;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/mult2.v:64: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance main\n  a <= $random;\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/mult2.v:65: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance main\n  b <= $random;\n    ^~\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire [35:0] p;
   reg [17:0]  a, b;
   reg	       clk, ce, reset;

   parameter   MAX_TRIALS = 1000;
   integer     idx;

   MULT18X18S dut (p, a, b, clk, ce, reset);

   initial begin
      clk   <= 0;
      ce    <= 1;
      reset <= 1;
      a     <= 0;
      b     <= 0;
      #5 clk <= 1;
      #5 clk <= 0;

      if (p !== 36'h0) begin
	 $display("FAILED -- reset p=%h", p);
	 $finish;
      end

      reset <= 0;


      a <= 18'h3ff82;
      b <= 18'h04000;

      #5 clk <= 1;
      #5 clk <= 0;

      if (p !== 36'hfffe08000) begin
	 $display("FAILED -- %h * %h --> %h", a, b, p);
	 $finish;
      end

      for (idx = 0 ;  idx < MAX_TRIALS ;  idx = idx + 1) begin
	 a <= $random;
	 b <= $random;

	 #5 clk <= 1;
	 #5 clk <= 0;

	 if ($signed(p) !== ($signed(a) * $signed(b))) begin
	    $display("FAILED == %h * %h --> %h", a, b, p);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule
module main;


   wire [35:0] p;
   reg [17:0]  a, b;
   reg	       clk, ce, reset;

   parameter   MAX_TRIALS = 1000;
   integer     idx;

   MULT18X18S dut (p, a, b, clk, ce, reset);

   initial begin
      clk   <= 0;
      ce    <= 1;
      reset <= 1;
      a     <= 0;
      b     <= 0;
      #5 clk <= 1;
      #5 clk <= 0;

      if (p !== 36'h0) begin
	 $display("FAILED -- reset p=%h", p);
	 $finish;
      end

      reset <= 0;


      a <= 18'h3ff82;
      b <= 18'h04000;

      #5 clk <= 1;
      #5 clk <= 0;

      if (p !== 36'hfffe08000) begin
	 $display("FAILED -- %h * %h --> %h", a, b, p);
	 $finish;
      end

      for (idx = 0 ;  idx < MAX_TRIALS ;  idx = idx + 1) begin
	 a <= $random;
	 b <= $random;

	 #5 clk <= 1;
	 #5 clk <= 0;

	 if ($signed(p) !== ($signed(a) * $signed(b))) begin
	    $display("FAILED == %h * %h --> %h", a, b, p);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule