data/full_repos/permissive/205055389/vlib/74xxGateLevel.v
 line:125: before: "11"
1: b"%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:197: syntax error, unexpected (-for-strength, expecting '('\n  not (highz1, strong0) #40 g1(Y1, A1);\n       ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:236: syntax error, unexpected (-for-strength, expecting '('\n  nor (highz1,strong0) #35 g1(Y1, A1, B1);\n       ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:255: syntax error, unexpected (-for-strength, expecting '('\n  nand (highz1, strong0) #35 g1(Y1, A1, B1, C1, D1);\n        ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:367: syntax error, unexpected (-for-strength, expecting '('\n  nand (highz1, strong0) #35 g1(Y1, A1, B1, C1);\n        ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:385: syntax error, unexpected (-for-strength, expecting '('\n  and (highz1, strong0) #21 g1(Y1, A1, B1);\n       ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:421: syntax error, unexpected (-for-strength, expecting '('\n  and (highz1, strong0) #40 g1(Y1, A1, B1, C1);\n       ^~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/74xxGateLevel.v:457: syntax error, unexpected (-for-strength, expecting '('\n  nand (highz1,strong0) #35 g1(Y1, A1, B1);\n        ^~~~~~\n%Error: Exiting due to 7 error(s)\n"
module SN7470(J1, J2, K1, K2, _K, _J, _PRE, _CLR, CLK, Q, _Q, J, K, w1_1, w1_2, K_1, CLK_1, J_1, w2_1, w2_2, w3_1, w3_2, w4_1, w4_2 );
  
  input J1, J2, K1, K2, _J, _K, _PRE, _CLR, CLK;
  output Q, _Q, J, K;
  
  output w1_1, w1_2, K_1, CLK_1, J_1, w2_1, w2_2, w3_1, w3_2, w4_1, w4_2;
  
  buf (K_1, ~_K);
  buf (J_1, ~_J);
  buf (CLK_1, ~CLK);

  nand (w1_1, K1, K2, K_1,_PRE, w3_1, Q);
  nand (w1_2, J1, J2, J_1,_CLR, w3_2,_Q);
  
  and (w2_1, w1_1, w3_2, w4_1);
  and (w2_2, w1_2, w3_1, w4_2);
  
  assign w3_1 = (w2_1==1'bx) ? CLK_1 : 1'bz;
  assign w3_2 = (w2_2==1'bx) ? CLK_1 : 1'bz;
  
  nand (w4_1, w3_1,_PRE, w4_2);
  nand (w4_2, w3_2,_CLR, w4_1);
  
  buf (_Q, ~w4_1);
  buf ( Q, ~w4_2);

endmodule
module SN7470(J1, J2, K1, K2, _K, _J, _PRE, _CLR, CLK, Q, _Q, J, K, w1_1, w1_2, K_1, CLK_1, J_1, w2_1, w2_2, w3_1, w3_2, w4_1, w4_2 );

  
  input J1, J2, K1, K2, _J, _K, _PRE, _CLR, CLK;
  output Q, _Q, J, K;
  
  output w1_1, w1_2, K_1, CLK_1, J_1, w2_1, w2_2, w3_1, w3_2, w4_1, w4_2;
  
  buf (K_1, ~_K);
  buf (J_1, ~_J);
  buf (CLK_1, ~CLK);

  nand (w1_1, K1, K2, K_1,_PRE, w3_1, Q);
  nand (w1_2, J1, J2, J_1,_CLR, w3_2,_Q);
  
  and (w2_1, w1_1, w3_2, w4_1);
  and (w2_2, w1_2, w3_1, w4_2);
  
  assign w3_1 = (w2_1==1'bx) ? CLK_1 : 1'bz;
  assign w3_2 = (w2_2==1'bx) ? CLK_1 : 1'bz;
  
  nand (w4_1, w3_1,_PRE, w4_2);
  nand (w4_2, w3_2,_CLR, w4_1);
  
  buf (_Q, ~w4_1);
  buf ( Q, ~w4_2);

endmodule