data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:3: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/src/cpu/core/storage,data/full_repos/permissive/201275379/bus.v\n             data/full_repos/permissive/201275379/src/cpu/core/storage,data/full_repos/permissive/201275379/bus.v.v\n             data/full_repos/permissive/201275379/src/cpu/core/storage,data/full_repos/permissive/201275379/bus.v.sv\n             bus.v\n             bus.v.v\n             bus.v.sv\n             obj_dir/bus.v\n             obj_dir/bus.v.v\n             obj_dir/bus.v.sv\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:4: Cannot find include file: rob.v\n`include "rob.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:11: Define or directive not defined: \'`REG_ADDR_BUS\'\n  input   [`REG_ADDR_BUS] write_addr,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  input   [`REG_ADDR_BUS] write_addr,\n                        ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:12: Define or directive not defined: \'`ROB_ADDR_BUS\'\n  input   [`ROB_ADDR_BUS] write_ref_id,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:16: Define or directive not defined: \'`REG_ADDR_BUS\'\n  input   [`REG_ADDR_BUS] commit_addr,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:17: Define or directive not defined: \'`DATA_BUS\'\n  input   [`DATA_BUS]     commit_data,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:21: Define or directive not defined: \'`REG_ADDR_BUS\'\n  input   [`REG_ADDR_BUS] read_addr_1,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:22: Define or directive not defined: \'`REG_ADDR_BUS\'\n  input   [`REG_ADDR_BUS] read_addr_2,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:25: Define or directive not defined: \'`DATA_BUS\'\n  output  [`DATA_BUS]     read_data_1,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:26: Define or directive not defined: \'`DATA_BUS\'\n  output  [`DATA_BUS]     read_data_2\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:32: Define or directive not defined: \'`DATA_BUS\'\n  reg[`DATA_BUS] reg_val[31:0];\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`DATA_BUS] reg_val[31:0];\n               ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:34: Define or directive not defined: \'`ROB_ADDR_BUS\'\n  reg[`ROB_ADDR_BUS] ref_id[31:0];\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`ROB_ADDR_BUS] ref_id[31:0];\n                   ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:40: syntax error, unexpected for\n      for (i = 0; i < 32; i = i + 1) begin\n      ^~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:58: syntax error, unexpected for\n      for (i = 0; i < 32; i = i + 1) begin\n      ^~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:71: syntax error, unexpected for\n      for (i = 0; i < 32; i = i + 1) begin\n      ^~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:82: Define or directive not defined: \'`DATA_BUS\'\n  reg[`DATA_BUS] read_data_1;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:82: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`DATA_BUS] read_data_1;\n               ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:99: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n          {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1\'b0}},\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:99: Define or directive not defined: \'`ROB_ADDR_WIDTH\'\n          {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1\'b0}},\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:112: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n            {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1\'b0}},\n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:112: Define or directive not defined: \'`ROB_ADDR_WIDTH\'\n            {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1\'b0}},\n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:129: Define or directive not defined: \'`DATA_BUS\'\n  reg[`DATA_BUS] read_data_2;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:129: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`DATA_BUS] read_data_2;\n               ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:146: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n          {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1\'b0}},\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:146: Define or directive not defined: \'`ROB_ADDR_WIDTH\'\n          {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1\'b0}},\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:159: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n            {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1\'b0}},\n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/RegFile.v:159: Define or directive not defined: \'`ROB_ADDR_WIDTH\'\n            {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1\'b0}},\n                                ^~~~~~~~~~~~~~~\n%Error: Exiting due to 30 error(s)\n'
module RegFile(
  input                   clk,
  input                   rst,

  input                   write_en,
  input   [`REG_ADDR_BUS] write_addr,
  input   [`ROB_ADDR_BUS] write_ref_id,

  input                   commit_en,
  input                   commit_restore,
  input   [`REG_ADDR_BUS] commit_addr,
  input   [`DATA_BUS]     commit_data,

  input                   read_en_1,
  input                   read_en_2,
  input   [`REG_ADDR_BUS] read_addr_1,
  input   [`REG_ADDR_BUS] read_addr_2,
  output                  read_is_ref_1,
  output                  read_is_ref_2,
  output  [`DATA_BUS]     read_data_1,
  output  [`DATA_BUS]     read_data_2
);


  reg is_ref[31:0];

  reg[`DATA_BUS] reg_val[31:0];

  reg[`ROB_ADDR_BUS] ref_id[31:0];


  always @(posedge clk) begin
    if (!rst || commit_restore) begin
      integer i;
      for (i = 0; i < 32; i = i + 1) begin
        is_ref[i] <= 0;
      end
    end
    else begin
      if (write_en) begin
        is_ref[write_addr] <= 1;
      end
      if (commit_en && !(write_en && commit_addr == write_addr)) begin
        is_ref[commit_addr] <= 0;
      end
    end
  end


  always @(posedge clk) begin
    if (!rst) begin
      integer i;
      for (i = 0; i < 32; i = i + 1) begin
        reg_val[i] <= 0;
      end
    end
    else if (commit_en && |commit_addr) begin
      reg_val[commit_addr] <= commit_data;
    end
  end


  always @(posedge clk) begin
    if (!rst) begin
      integer i;
      for (i = 0; i < 32; i = i + 1) begin
        ref_id[i] <= 0;
      end
    end
    else if (write_en && |write_addr) begin
      ref_id[write_addr] <= write_ref_id;
    end
  end


  reg read_is_ref_1;
  reg[`DATA_BUS] read_data_1;

  always @(*) begin
    if (!rst) begin
      read_is_ref_1 <= 0;
      read_data_1 <= 0;
    end
    else if (read_en_1) begin
      if (commit_restore) begin

        read_is_ref_1 <= 0;
        read_data_1 <= reg_val[read_addr_1];
      end
      else if (write_en && read_addr_1 == write_addr) begin

        read_is_ref_1 <= 1;
        read_data_1 <= {
          {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1'b0}},
          write_ref_id
        };
      end
      else if (commit_en && read_addr_1 == commit_addr) begin

        read_is_ref_2 <= 0;
        read_data_2 <= commit_data;
      end
      else begin
        read_is_ref_1 <= is_ref[read_addr_1];
        if (is_ref[read_addr_1]) begin
          read_data_1 <= {
            {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1'b0}},
            ref_id[read_addr_1]
          };
        end
        else begin
          read_data_1 <= reg_val[read_addr_1];
        end
      end
    end
    else begin
      read_is_ref_1 <= 0;
      read_data_1 <= 0;
    end
  end


  reg read_is_ref_2;
  reg[`DATA_BUS] read_data_2;

  always @(*) begin
    if (!rst) begin
      read_is_ref_2 <= 0;
      read_data_2 <= 0;
    end
    else if (read_en_2) begin
      if (commit_restore) begin

        read_is_ref_2 <= 0;
        read_data_2 <= reg_val[read_addr_2];
      end
      else if (write_en && read_addr_2 == write_addr) begin

        read_is_ref_2 <= 1;
        read_data_2 <= {
          {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1'b0}},
          write_ref_id
        };
      end
      else if (commit_en && read_addr_2 == commit_addr) begin

        read_is_ref_2 <= 0;
        read_data_2 <= commit_data;
      end
      else begin
        read_is_ref_2 <= is_ref[read_addr_2];
        if (is_ref[read_addr_2]) begin
          read_data_2 <= {
            {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1'b0}},
            ref_id[read_addr_2]
          };
        end
        else begin
          read_data_2 <= reg_val[read_addr_2];
        end
      end
    end
    else begin
      read_is_ref_2 <= 0;
      read_data_2 <= 0;
    end
  end

endmodule
module RegFile(
  input                   clk,
  input                   rst,

  input                   write_en,
  input   [`REG_ADDR_BUS] write_addr,
  input   [`ROB_ADDR_BUS] write_ref_id,

  input                   commit_en,
  input                   commit_restore,
  input   [`REG_ADDR_BUS] commit_addr,
  input   [`DATA_BUS]     commit_data,

  input                   read_en_1,
  input                   read_en_2,
  input   [`REG_ADDR_BUS] read_addr_1,
  input   [`REG_ADDR_BUS] read_addr_2,
  output                  read_is_ref_1,
  output                  read_is_ref_2,
  output  [`DATA_BUS]     read_data_1,
  output  [`DATA_BUS]     read_data_2
);



  reg is_ref[31:0];

  reg[`DATA_BUS] reg_val[31:0];

  reg[`ROB_ADDR_BUS] ref_id[31:0];


  always @(posedge clk) begin
    if (!rst || commit_restore) begin
      integer i;
      for (i = 0; i < 32; i = i + 1) begin
        is_ref[i] <= 0;
      end
    end
    else begin
      if (write_en) begin
        is_ref[write_addr] <= 1;
      end
      if (commit_en && !(write_en && commit_addr == write_addr)) begin
        is_ref[commit_addr] <= 0;
      end
    end
  end


  always @(posedge clk) begin
    if (!rst) begin
      integer i;
      for (i = 0; i < 32; i = i + 1) begin
        reg_val[i] <= 0;
      end
    end
    else if (commit_en && |commit_addr) begin
      reg_val[commit_addr] <= commit_data;
    end
  end


  always @(posedge clk) begin
    if (!rst) begin
      integer i;
      for (i = 0; i < 32; i = i + 1) begin
        ref_id[i] <= 0;
      end
    end
    else if (write_en && |write_addr) begin
      ref_id[write_addr] <= write_ref_id;
    end
  end


  reg read_is_ref_1;
  reg[`DATA_BUS] read_data_1;

  always @(*) begin
    if (!rst) begin
      read_is_ref_1 <= 0;
      read_data_1 <= 0;
    end
    else if (read_en_1) begin
      if (commit_restore) begin

        read_is_ref_1 <= 0;
        read_data_1 <= reg_val[read_addr_1];
      end
      else if (write_en && read_addr_1 == write_addr) begin

        read_is_ref_1 <= 1;
        read_data_1 <= {
          {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1'b0}},
          write_ref_id
        };
      end
      else if (commit_en && read_addr_1 == commit_addr) begin

        read_is_ref_2 <= 0;
        read_data_2 <= commit_data;
      end
      else begin
        read_is_ref_1 <= is_ref[read_addr_1];
        if (is_ref[read_addr_1]) begin
          read_data_1 <= {
            {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1'b0}},
            ref_id[read_addr_1]
          };
        end
        else begin
          read_data_1 <= reg_val[read_addr_1];
        end
      end
    end
    else begin
      read_is_ref_1 <= 0;
      read_data_1 <= 0;
    end
  end


  reg read_is_ref_2;
  reg[`DATA_BUS] read_data_2;

  always @(*) begin
    if (!rst) begin
      read_is_ref_2 <= 0;
      read_data_2 <= 0;
    end
    else if (read_en_2) begin
      if (commit_restore) begin

        read_is_ref_2 <= 0;
        read_data_2 <= reg_val[read_addr_2];
      end
      else if (write_en && read_addr_2 == write_addr) begin

        read_is_ref_2 <= 1;
        read_data_2 <= {
          {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1'b0}},
          write_ref_id
        };
      end
      else if (commit_en && read_addr_2 == commit_addr) begin

        read_is_ref_2 <= 0;
        read_data_2 <= commit_data;
      end
      else begin
        read_is_ref_2 <= is_ref[read_addr_2];
        if (is_ref[read_addr_2]) begin
          read_data_2 <= {
            {(`DATA_BUS_WIDTH - `ROB_ADDR_WIDTH){1'b0}},
            ref_id[read_addr_2]
          };
        end
        else begin
          read_data_2 <= reg_val[read_addr_2];
        end
      end
    end
    else begin
      read_is_ref_2 <= 0;
      read_data_2 <= 0;
    end
  end

endmodule