data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:22: Cannot find include file: mm_to_lite_v1_0_tb_include.vh\n`include "mm_to_lite_v1_0_tb_include.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design,data/full_repos/permissive/135295301/mm_to_lite_v1_0_tb_include.vh\n             data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design,data/full_repos/permissive/135295301/mm_to_lite_v1_0_tb_include.vh.v\n             data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design,data/full_repos/permissive/135295301/mm_to_lite_v1_0_tb_include.vh.sv\n             mm_to_lite_v1_0_tb_include.vh\n             mm_to_lite_v1_0_tb_include.vh.v\n             mm_to_lite_v1_0_tb_include.vh.sv\n             obj_dir/mm_to_lite_v1_0_tb_include.vh\n             obj_dir/mm_to_lite_v1_0_tb_include.vh.v\n             obj_dir/mm_to_lite_v1_0_tb_include.vh.sv\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:51: Define or directive not defined: \'`BD_WRAPPER\'\n `BD_WRAPPER dut (.ACLK(tb_ACLK),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:51: syntax error, unexpected \'(\', expecting IDENTIFIER\n `BD_WRAPPER dut (.ACLK(tb_ACLK),\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n   #500;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:85: syntax error, unexpected \'@\'\n  @(posedge tb_ACLK);\n  ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:87: syntax error, unexpected \'@\'\n  @(posedge tb_ACLK);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n always #10 tb_ACLK = !tb_ACLK;\n        ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:166: Define or directive not defined: \'`S_AXI_SLAVE_ADDRESS\'\n   S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS;\n                        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:166: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS;\n                                            ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:176: Define or directive not defined: \'`BD_INST_NAME\'\n   dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.WRITE_BURST_CONCURRENT(S_AXI_mtestID,\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:176: syntax error, unexpected \'.\'\n   dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.WRITE_BURST_CONCURRENT(S_AXI_mtestID,\n                    ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:195: Define or directive not defined: \'`BD_INST_NAME\'\n   dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.READ_BURST(S_AXI_mtestID,\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:195: syntax error, unexpected \'.\'\n   dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.READ_BURST(S_AXI_mtestID,\n                    ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:237: Define or directive not defined: \'`S_AXI_SLAVE_ADDRESS\'\n   S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS + addr;\n                        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:248: Define or directive not defined: \'`BD_INST_NAME\'\n   dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.SEND_WRITE_ADDRESS(\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:248: syntax error, unexpected \'.\'\n   dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.SEND_WRITE_ADDRESS(\n                    ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:261: Define or directive not defined: \'`BD_INST_NAME\'\n   dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.SEND_WRITE_DATA(\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:261: syntax error, unexpected \'.\'\n   dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.SEND_WRITE_DATA(\n                    ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:267: Define or directive not defined: \'`BD_INST_NAME\'\n   dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.RECEIVE_WRITE_RESPONSE(\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:267: syntax error, unexpected \'.\'\n   dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.RECEIVE_WRITE_RESPONSE(\n                    ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:282: Define or directive not defined: \'`S_AXI_SLAVE_ADDRESS\'\n   S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS + addr;\n                        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:293: Define or directive not defined: \'`BD_INST_NAME\'\n   dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.READ_BURST(\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:293: syntax error, unexpected \'.\'\n   dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.READ_BURST(\n                    ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:316: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:316: Unsupported: wait statements\n  wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:317: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:317: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:318: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:318: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:319: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:319: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:320: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);  \n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:320: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);  \n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:322: Define or directive not defined: \'`BD_INST_NAME\'\n  dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.set_channel_level_info(1);\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:322: syntax error, unexpected \'.\'\n  dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.set_channel_level_info(1);\n                   ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:335: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:335: Unsupported: wait statements\n  wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:336: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:336: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:337: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:337: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:338: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:338: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:339: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:339: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:341: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:343: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:350: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:352: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:356: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:358: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/mm_to_lite_1.0/example_designs/bfm_design/mm_to_lite_v1_0_tb.v:360: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Error: Exiting due to 43 error(s), 9 warning(s)\n'
module mm_to_lite_v1_0_tb;
	reg tb_ACLK;
	reg tb_ARESETn;


	`BD_WRAPPER dut (.ACLK(tb_ACLK),
				.ARESETN(tb_ARESETn));




	reg [(`S_AXI_DATA_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1)/16)-1:0] S_AXI_rd_data;
	reg [(`S_AXI_DATA_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1)/16)-1:0] S_AXI_test_data [2:0];
	reg [(`RESP_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1))-1:0] S_AXI_vresponse;
	reg [`S_AXI_ADDRESS_BUS_WIDTH-1:0] S_AXI_mtestAddress;
	reg [(`S_AXI_RUSER_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1))-1:0] S_AXI_v_ruser;
	reg [(`S_AXI_WUSER_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1))-1:0] S_AXI_v_wuser;
	reg [`RESP_BUS_WIDTH-1:0] S_AXI_response;
	integer  S_AXI_mtestID;
	integer  S_AXI_mtestBurstLength;
	integer  S_AXI_mtestvector;
	integer  S_AXI_mtestdatasize;
	integer  S_AXI_mtestCacheType = 0;
	integer  S_AXI_mtestProtectionType = 0;
	integer  S_AXI_mtestRegion = 0;
	integer  S_AXI_mtestQOS = 0;
	integer  S_AXI_mtestAWUSER = 0;
	integer  S_AXI_mtestARUSER = 0;
	integer  S_AXI_mtestBUSER = 0;
	integer result_slave_full;

	reg [`S_AXI_DATA_BUS_WIDTH-1:0] test_data;
	reg [`S_AXI_DATA_BUS_WIDTH-1:0] s_axi_read_data;


	initial begin
		tb_ARESETn = 1'b0;
	  #500;

		@(posedge tb_ACLK);
	  tb_ARESETn = 1'b1;
		@(posedge tb_ACLK);
	end


	initial tb_ACLK = 1'b0;
	always #10 tb_ACLK = !tb_ACLK;








	task automatic CHECK_RESPONSE_OKAY;
		input [`RESP_BUS_WIDTH-1:0] response;
		begin
		  if (response !== `RESPONSE_OKAY) begin
			  $display("TESTBENCH ERROR! lite_response is not OKAY",
				         "\n expected = 0x%h",`RESPONSE_OKAY,
				         "\n actual   = 0x%h",response);
		    $stop;
		  end
		end
	endtask











	task automatic COMPARE_DATA;
		input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
		input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
		begin
			if (expected === 'hx || actual === 'hx) begin
				$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
		    result_slave_full = 0;
		    $stop;
		  end

			if (actual != expected) begin
				$display("TESTBENCH ERROR! Data expected is not equal to actual.",
				         "\n expected = 0x%h",expected,
				         "\n actual   = 0x%h",actual);
		    result_slave_full = 0;
		    $stop;
		  end
			else 
			begin
			   $display("TESTBENCH Passed! Data expected is equal to actual.",
			            "\n expected = 0x%h",expected,
			            "\n actual   = 0x%h",actual);
			end
		end
	endtask

	task automatic S_AXI_TEST;
		begin







			$display("---------------------------------------------------------");
			$display("EXAMPLE TEST S_AXI:");
			$display("Simple sequential write and read burst transfers example");
			$display("---------------------------------------------------------");
			
			S_AXI_mtestID = 1;
			S_AXI_mtestvector = 0;
			S_AXI_mtestBurstLength = 15;
			S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS;
			S_AXI_mtestCacheType = 0;
			S_AXI_mtestProtectionType = 0;
			S_AXI_mtestdatasize = `S_AXI_MAX_DATA_SIZE;
			S_AXI_mtestRegion = 0;
			S_AXI_mtestQOS = 0;
			S_AXI_mtestAWUSER = 0;
			S_AXI_mtestARUSER = 0;
			 result_slave_full = 1;
			
			dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.WRITE_BURST_CONCURRENT(S_AXI_mtestID,
			                        S_AXI_mtestAddress,
			                        S_AXI_mtestBurstLength,
			                        `BURST_SIZE_4_BYTES,
			                        `BURST_TYPE_INCR,
			                        `LOCK_TYPE_NORMAL,
			                        S_AXI_mtestCacheType,
			                        S_AXI_mtestProtectionType,
			                        S_AXI_test_data[S_AXI_mtestvector],
			                        S_AXI_mtestdatasize,
			                        S_AXI_mtestRegion,
			                        S_AXI_mtestQOS,
			                        S_AXI_mtestAWUSER,
			                        S_AXI_v_wuser,
			                        S_AXI_response,
			                        S_AXI_mtestBUSER);
			$display("EXAMPLE TEST 1 : DATA = 0x%h, response = 0x%h",S_AXI_test_data[S_AXI_mtestvector],S_AXI_response);
			CHECK_RESPONSE_OKAY(S_AXI_response);
			S_AXI_mtestID = S_AXI_mtestID+1;
			dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.READ_BURST(S_AXI_mtestID,
			                       S_AXI_mtestAddress,
			                       S_AXI_mtestBurstLength,
			                       `BURST_SIZE_4_BYTES,
			                       `BURST_TYPE_WRAP,
			                       `LOCK_TYPE_NORMAL,
			                       S_AXI_mtestCacheType,
			                       S_AXI_mtestProtectionType,
			                       S_AXI_mtestRegion,
			                       S_AXI_mtestQOS,
			                       S_AXI_mtestARUSER,
			                       S_AXI_rd_data,
			                       S_AXI_vresponse,
			                       S_AXI_v_ruser);
			$display("EXAMPLE TEST 1 : DATA = 0x%h, vresponse = 0x%h",S_AXI_rd_data,S_AXI_vresponse);
			CHECK_RESPONSE_OKAY(S_AXI_vresponse);


			COMPARE_DATA(S_AXI_test_data[S_AXI_mtestvector],S_AXI_rd_data);

			$display("EXAMPLE TEST 1 : Sequential write and read FIXED burst transfers complete from the master side.");
			$display("---------------------------------------------------------");
			$display("EXAMPLE TEST S_AXI: PTGEN_TEST_FINISHED!");
				if ( result_slave_full ) begin				   
					$display("PTGEN_TEST: PASSED!");                 
				end	else begin                                         
					$display("PTGEN_TEST: FAILED!");                 
				end							   
			$display("---------------------------------------------------------");
		end
	endtask 




	task automatic WRITE_STROBE;
		input [`S_AXI_ADDRESS_BUS_WIDTH-1:0] addr;
		input [`S_AXI_DATA_BUS_WIDTH-1:0] data;
		input [(`S_AXI_DATA_BUS_WIDTH/8)-1:0] strb;
		begin
			
			S_AXI_mtestBurstLength = 0;
			S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS + addr;

			S_AXI_mtestID = 1;
			S_AXI_mtestCacheType = 0;
			S_AXI_mtestProtectionType = 0;
			S_AXI_mtestRegion = 0;
			S_AXI_mtestQOS = 0;
			S_AXI_mtestAWUSER = 0;
			S_AXI_mtestARUSER = 0;


			dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.SEND_WRITE_ADDRESS(
					S_AXI_mtestID,
					S_AXI_mtestAddress,
					S_AXI_mtestBurstLength,
					3'b010,
					`BURST_TYPE_INCR,
					`LOCK_TYPE_NORMAL,
					S_AXI_mtestCacheType,
					S_AXI_mtestProtectionType,
					S_AXI_mtestRegion,
					S_AXI_mtestQOS,
					S_AXI_mtestAWUSER);   
		                                            
			dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.SEND_WRITE_DATA(
					strb,
					data,
					1'b1,
					S_AXI_v_wuser);   
		                                                                                                                 
			dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.RECEIVE_WRITE_RESPONSE(
					S_AXI_mtestID,
					S_AXI_response,
					S_AXI_mtestBUSER);
			$display("EXAMPLE TEST STRB : DATA = 0x%h, response = 0x%h",data,S_AXI_response);
		end
	endtask




	task automatic READ_OUT;
		input [`S_AXI_ADDRESS_BUS_WIDTH-1:0] addr;
		begin
			S_AXI_mtestBurstLength = 0;
			S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS + addr;

			S_AXI_mtestID = 1;
			S_AXI_mtestCacheType = 0;
			S_AXI_mtestProtectionType = 0;
			S_AXI_mtestRegion = 0;
			S_AXI_mtestQOS = 0;
			S_AXI_mtestARUSER = 0;

			s_axi_read_data = 0;

			dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.READ_BURST(
					S_AXI_mtestID,
					S_AXI_mtestAddress,
					S_AXI_mtestBurstLength,
					3'b010,
					`BURST_TYPE_INCR,
					`LOCK_TYPE_NORMAL,
					S_AXI_mtestCacheType,
					S_AXI_mtestProtectionType,
					S_AXI_mtestRegion,
					S_AXI_mtestQOS,
					S_AXI_mtestARUSER,
					s_axi_read_data,
					S_AXI_vresponse,
					S_AXI_v_ruser);          

			$display("EXAMPLE TEST READ : DATA = 0x%h, vresponse = 0x%h", s_axi_read_data, S_AXI_vresponse);
		end
	endtask


	initial begin

		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);  

		dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.set_channel_level_info(1);


		S_AXI_test_data[1] = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
		S_AXI_test_data[0] = 512'h00abcdef111111112222222233333333444444445555555566666666777777778888888899999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEEFFFFFFFF;
		S_AXI_test_data[2] = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
		S_AXI_v_ruser = 0;
		S_AXI_v_wuser = 0;
	end


	initial begin

		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     

		#100
		$display("EXAMPLE TEST M_AXI_LITE:");
		#100
		test_data[255:0] = 0;



		test_data[255:0] = 256'h12345678ABCDEFAB;
		WRITE_STROBE(32'h44A00000, test_data, 32'hF);
		#20;
		READ_OUT(32'h44A00000);
		#20;

		test_data[255:0] = 256'hC0C0C0C0A0A0A0A0;
		WRITE_STROBE(32'h44A00004, test_data, 32'hF0);
		#20;
		READ_OUT(32'h44A00004);
		#20;

		#100
		$display("M_AXI_LITE: PTGEN_TEST_FINISHED!");
		if ( 1'b0 ) begin
		  $display("PTGEN_TEST: FAILED!");
		end else begin
		  $display("PTGEN_TEST: PASSED!");
		end

	end

endmodule
module mm_to_lite_v1_0_tb;

	reg tb_ACLK;
	reg tb_ARESETn;


	`BD_WRAPPER dut (.ACLK(tb_ACLK),
				.ARESETN(tb_ARESETn));




	reg [(`S_AXI_DATA_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1)/16)-1:0] S_AXI_rd_data;
	reg [(`S_AXI_DATA_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1)/16)-1:0] S_AXI_test_data [2:0];
	reg [(`RESP_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1))-1:0] S_AXI_vresponse;
	reg [`S_AXI_ADDRESS_BUS_WIDTH-1:0] S_AXI_mtestAddress;
	reg [(`S_AXI_RUSER_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1))-1:0] S_AXI_v_ruser;
	reg [(`S_AXI_WUSER_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1))-1:0] S_AXI_v_wuser;
	reg [`RESP_BUS_WIDTH-1:0] S_AXI_response;
	integer  S_AXI_mtestID;
	integer  S_AXI_mtestBurstLength;
	integer  S_AXI_mtestvector;
	integer  S_AXI_mtestdatasize;
	integer  S_AXI_mtestCacheType = 0;
	integer  S_AXI_mtestProtectionType = 0;
	integer  S_AXI_mtestRegion = 0;
	integer  S_AXI_mtestQOS = 0;
	integer  S_AXI_mtestAWUSER = 0;
	integer  S_AXI_mtestARUSER = 0;
	integer  S_AXI_mtestBUSER = 0;
	integer result_slave_full;

	reg [`S_AXI_DATA_BUS_WIDTH-1:0] test_data;
	reg [`S_AXI_DATA_BUS_WIDTH-1:0] s_axi_read_data;


	initial begin
		tb_ARESETn = 1'b0;
	  #500;

		@(posedge tb_ACLK);
	  tb_ARESETn = 1'b1;
		@(posedge tb_ACLK);
	end


	initial tb_ACLK = 1'b0;
	always #10 tb_ACLK = !tb_ACLK;








	task automatic CHECK_RESPONSE_OKAY;
		input [`RESP_BUS_WIDTH-1:0] response;
		begin
		  if (response !== `RESPONSE_OKAY) begin
			  $display("TESTBENCH ERROR! lite_response is not OKAY",
				         "\n expected = 0x%h",`RESPONSE_OKAY,
				         "\n actual   = 0x%h",response);
		    $stop;
		  end
		end
	endtask











	task automatic COMPARE_DATA;
		input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
		input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
		begin
			if (expected === 'hx || actual === 'hx) begin
				$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
		    result_slave_full = 0;
		    $stop;
		  end

			if (actual != expected) begin
				$display("TESTBENCH ERROR! Data expected is not equal to actual.",
				         "\n expected = 0x%h",expected,
				         "\n actual   = 0x%h",actual);
		    result_slave_full = 0;
		    $stop;
		  end
			else 
			begin
			   $display("TESTBENCH Passed! Data expected is equal to actual.",
			            "\n expected = 0x%h",expected,
			            "\n actual   = 0x%h",actual);
			end
		end
	endtask

	task automatic S_AXI_TEST;
		begin







			$display("---------------------------------------------------------");
			$display("EXAMPLE TEST S_AXI:");
			$display("Simple sequential write and read burst transfers example");
			$display("---------------------------------------------------------");
			
			S_AXI_mtestID = 1;
			S_AXI_mtestvector = 0;
			S_AXI_mtestBurstLength = 15;
			S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS;
			S_AXI_mtestCacheType = 0;
			S_AXI_mtestProtectionType = 0;
			S_AXI_mtestdatasize = `S_AXI_MAX_DATA_SIZE;
			S_AXI_mtestRegion = 0;
			S_AXI_mtestQOS = 0;
			S_AXI_mtestAWUSER = 0;
			S_AXI_mtestARUSER = 0;
			 result_slave_full = 1;
			
			dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.WRITE_BURST_CONCURRENT(S_AXI_mtestID,
			                        S_AXI_mtestAddress,
			                        S_AXI_mtestBurstLength,
			                        `BURST_SIZE_4_BYTES,
			                        `BURST_TYPE_INCR,
			                        `LOCK_TYPE_NORMAL,
			                        S_AXI_mtestCacheType,
			                        S_AXI_mtestProtectionType,
			                        S_AXI_test_data[S_AXI_mtestvector],
			                        S_AXI_mtestdatasize,
			                        S_AXI_mtestRegion,
			                        S_AXI_mtestQOS,
			                        S_AXI_mtestAWUSER,
			                        S_AXI_v_wuser,
			                        S_AXI_response,
			                        S_AXI_mtestBUSER);
			$display("EXAMPLE TEST 1 : DATA = 0x%h, response = 0x%h",S_AXI_test_data[S_AXI_mtestvector],S_AXI_response);
			CHECK_RESPONSE_OKAY(S_AXI_response);
			S_AXI_mtestID = S_AXI_mtestID+1;
			dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.READ_BURST(S_AXI_mtestID,
			                       S_AXI_mtestAddress,
			                       S_AXI_mtestBurstLength,
			                       `BURST_SIZE_4_BYTES,
			                       `BURST_TYPE_WRAP,
			                       `LOCK_TYPE_NORMAL,
			                       S_AXI_mtestCacheType,
			                       S_AXI_mtestProtectionType,
			                       S_AXI_mtestRegion,
			                       S_AXI_mtestQOS,
			                       S_AXI_mtestARUSER,
			                       S_AXI_rd_data,
			                       S_AXI_vresponse,
			                       S_AXI_v_ruser);
			$display("EXAMPLE TEST 1 : DATA = 0x%h, vresponse = 0x%h",S_AXI_rd_data,S_AXI_vresponse);
			CHECK_RESPONSE_OKAY(S_AXI_vresponse);


			COMPARE_DATA(S_AXI_test_data[S_AXI_mtestvector],S_AXI_rd_data);

			$display("EXAMPLE TEST 1 : Sequential write and read FIXED burst transfers complete from the master side.");
			$display("---------------------------------------------------------");
			$display("EXAMPLE TEST S_AXI: PTGEN_TEST_FINISHED!");
				if ( result_slave_full ) begin				   
					$display("PTGEN_TEST: PASSED!");                 
				end	else begin                                         
					$display("PTGEN_TEST: FAILED!");                 
				end							   
			$display("---------------------------------------------------------");
		end
	endtask 




	task automatic WRITE_STROBE;
		input [`S_AXI_ADDRESS_BUS_WIDTH-1:0] addr;
		input [`S_AXI_DATA_BUS_WIDTH-1:0] data;
		input [(`S_AXI_DATA_BUS_WIDTH/8)-1:0] strb;
		begin
			
			S_AXI_mtestBurstLength = 0;
			S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS + addr;

			S_AXI_mtestID = 1;
			S_AXI_mtestCacheType = 0;
			S_AXI_mtestProtectionType = 0;
			S_AXI_mtestRegion = 0;
			S_AXI_mtestQOS = 0;
			S_AXI_mtestAWUSER = 0;
			S_AXI_mtestARUSER = 0;


			dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.SEND_WRITE_ADDRESS(
					S_AXI_mtestID,
					S_AXI_mtestAddress,
					S_AXI_mtestBurstLength,
					3'b010,
					`BURST_TYPE_INCR,
					`LOCK_TYPE_NORMAL,
					S_AXI_mtestCacheType,
					S_AXI_mtestProtectionType,
					S_AXI_mtestRegion,
					S_AXI_mtestQOS,
					S_AXI_mtestAWUSER);   
		                                            
			dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.SEND_WRITE_DATA(
					strb,
					data,
					1'b1,
					S_AXI_v_wuser);   
		                                                                                                                 
			dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.RECEIVE_WRITE_RESPONSE(
					S_AXI_mtestID,
					S_AXI_response,
					S_AXI_mtestBUSER);
			$display("EXAMPLE TEST STRB : DATA = 0x%h, response = 0x%h",data,S_AXI_response);
		end
	endtask




	task automatic READ_OUT;
		input [`S_AXI_ADDRESS_BUS_WIDTH-1:0] addr;
		begin
			S_AXI_mtestBurstLength = 0;
			S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS + addr;

			S_AXI_mtestID = 1;
			S_AXI_mtestCacheType = 0;
			S_AXI_mtestProtectionType = 0;
			S_AXI_mtestRegion = 0;
			S_AXI_mtestQOS = 0;
			S_AXI_mtestARUSER = 0;

			s_axi_read_data = 0;

			dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.READ_BURST(
					S_AXI_mtestID,
					S_AXI_mtestAddress,
					S_AXI_mtestBurstLength,
					3'b010,
					`BURST_TYPE_INCR,
					`LOCK_TYPE_NORMAL,
					S_AXI_mtestCacheType,
					S_AXI_mtestProtectionType,
					S_AXI_mtestRegion,
					S_AXI_mtestQOS,
					S_AXI_mtestARUSER,
					s_axi_read_data,
					S_AXI_vresponse,
					S_AXI_v_ruser);          

			$display("EXAMPLE TEST READ : DATA = 0x%h, vresponse = 0x%h", s_axi_read_data, S_AXI_vresponse);
		end
	endtask


	initial begin

		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);  

		dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.set_channel_level_info(1);


		S_AXI_test_data[1] = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
		S_AXI_test_data[0] = 512'h00abcdef111111112222222233333333444444445555555566666666777777778888888899999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEEFFFFFFFF;
		S_AXI_test_data[2] = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
		S_AXI_v_ruser = 0;
		S_AXI_v_wuser = 0;
	end


	initial begin

		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     

		#100
		$display("EXAMPLE TEST M_AXI_LITE:");
		#100
		test_data[255:0] = 0;



		test_data[255:0] = 256'h12345678ABCDEFAB;
		WRITE_STROBE(32'h44A00000, test_data, 32'hF);
		#20;
		READ_OUT(32'h44A00000);
		#20;

		test_data[255:0] = 256'hC0C0C0C0A0A0A0A0;
		WRITE_STROBE(32'h44A00004, test_data, 32'hF0);
		#20;
		READ_OUT(32'h44A00004);
		#20;

		#100
		$display("M_AXI_LITE: PTGEN_TEST_FINISHED!");
		if ( 1'b0 ) begin
		  $display("PTGEN_TEST: FAILED!");
		end else begin
		  $display("PTGEN_TEST: PASSED!");
		end

	end

endmodule