data/full_repos/permissive/188270170/verilog/peripherals/test/src/ssdctrl.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/188270170/verilog/peripherals/test/src/ssdctrl.v:82: Cannot find file containing module: 'Format_Data'\n  Format_Data FDATA(\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188270170/verilog/peripherals/test/src,data/full_repos/permissive/188270170/Format_Data\n             data/full_repos/permissive/188270170/verilog/peripherals/test/src,data/full_repos/permissive/188270170/Format_Data.v\n             data/full_repos/permissive/188270170/verilog/peripherals/test/src,data/full_repos/permissive/188270170/Format_Data.sv\n             Format_Data\n             Format_Data.v\n             Format_Data.sv\n             obj_dir/Format_Data\n             obj_dir/Format_Data.v\n             obj_dir/Format_Data.sv\n%Error: Exiting due to 1 error(s)\n"
module ssdCtrl(
		CLK,
		RST,
		DIN,
		AN,
		SEG,
		DOT
);




   input            CLK;
   input            RST;
   input [9:0]      DIN;
   output [3:0]     AN;
   reg [3:0]        AN;
   output [6:0]     SEG;
   reg [6:0]        SEG;
   output           DOT;
   
   



   

   parameter [15:0] cntEndVal = 16'hC350;
   reg [15:0]       clkCount;
   reg              DCLK;
   

   reg [1:0]        CNT;
   

   wire [15:0]      bcdData;
   

   reg [3:0]        muxData;
   



   

		assign bcdData[15:12] = (DIN[9] == 1'b0) ? (4'hA) : (4'hF);
		

		assign DOT = (CNT == 2'b11) ? 1'b0 : 1'b1;
		



		Format_Data FDATA(
				.CLK(CLK),
				.DCLK(DCLK),
				.RST(RST),
				.DIN(DIN[8:0]),
				.BCDOUT(bcdData[11:0])
		);
		




		always @(CNT[1] or CNT[0] or bcdData or RST)
			if (RST == 1'b1)
				muxData <= 4'b0000;
			else
				case (CNT)
					2'b00 : muxData <= bcdData[3:0];
					2'b01 : muxData <= bcdData[7:4];
					2'b10 : muxData <= bcdData[11:8];
					2'b11 : muxData <= bcdData[15:12];
					default : muxData <= 4'b0000;
				endcase
		





		always @(posedge DCLK or posedge RST)
			if (RST == 1'b1)
				SEG <= 7'b1000000;
			else 
				case (muxData)
					4'h0 : SEG <= 7'b1000000;
					4'h1 : SEG <= 7'b1111001;
					4'h2 : SEG <= 7'b0100100;
					4'h3 : SEG <= 7'b0110000;
					4'h4 : SEG <= 7'b0011001;
					4'h5 : SEG <= 7'b0010010;
					4'h6 : SEG <= 7'b0000010;
					4'h7 : SEG <= 7'b1111000;
					4'h8 : SEG <= 7'b0000000;
					4'h9 : SEG <= 7'b0010000;
					4'hA : SEG <= 7'b0111111;
					4'hF : SEG <= 7'b1111111;
					default : SEG <= 7'b1111111;
				endcase
		





		always @(posedge DCLK or posedge RST)
			if (RST == 1'b1)
				AN <= 4'b1111;
			else 
				case (CNT)
					2'b00 : AN <= 4'b1110;
					2'b01 : AN <= 4'b1101;
					2'b10 : AN <= 4'b1011;
					2'b11 : AN <= 4'b0111;
					default : AN <= 4'b1111;
				endcase
		






		always @(posedge DCLK) begin
				CNT <= CNT + 1'b1;
		end
		





		always @(posedge CLK) begin
				if (clkCount == cntEndVal) begin
					DCLK <= 1'b1;
					clkCount <= 16'h0000;
				end
				else begin
					DCLK <= 1'b0;
					clkCount <= clkCount + 1'b1;
				end
		end
   
endmodule
module ssdCtrl(
		CLK,
		RST,
		DIN,
		AN,
		SEG,
		DOT
);





   input            CLK;
   input            RST;
   input [9:0]      DIN;
   output [3:0]     AN;
   reg [3:0]        AN;
   output [6:0]     SEG;
   reg [6:0]        SEG;
   output           DOT;
   
   



   

   parameter [15:0] cntEndVal = 16'hC350;
   reg [15:0]       clkCount;
   reg              DCLK;
   

   reg [1:0]        CNT;
   

   wire [15:0]      bcdData;
   

   reg [3:0]        muxData;
   



   

		assign bcdData[15:12] = (DIN[9] == 1'b0) ? (4'hA) : (4'hF);
		

		assign DOT = (CNT == 2'b11) ? 1'b0 : 1'b1;
		



		Format_Data FDATA(
				.CLK(CLK),
				.DCLK(DCLK),
				.RST(RST),
				.DIN(DIN[8:0]),
				.BCDOUT(bcdData[11:0])
		);
		




		always @(CNT[1] or CNT[0] or bcdData or RST)
			if (RST == 1'b1)
				muxData <= 4'b0000;
			else
				case (CNT)
					2'b00 : muxData <= bcdData[3:0];
					2'b01 : muxData <= bcdData[7:4];
					2'b10 : muxData <= bcdData[11:8];
					2'b11 : muxData <= bcdData[15:12];
					default : muxData <= 4'b0000;
				endcase
		





		always @(posedge DCLK or posedge RST)
			if (RST == 1'b1)
				SEG <= 7'b1000000;
			else 
				case (muxData)
					4'h0 : SEG <= 7'b1000000;
					4'h1 : SEG <= 7'b1111001;
					4'h2 : SEG <= 7'b0100100;
					4'h3 : SEG <= 7'b0110000;
					4'h4 : SEG <= 7'b0011001;
					4'h5 : SEG <= 7'b0010010;
					4'h6 : SEG <= 7'b0000010;
					4'h7 : SEG <= 7'b1111000;
					4'h8 : SEG <= 7'b0000000;
					4'h9 : SEG <= 7'b0010000;
					4'hA : SEG <= 7'b0111111;
					4'hF : SEG <= 7'b1111111;
					default : SEG <= 7'b1111111;
				endcase
		





		always @(posedge DCLK or posedge RST)
			if (RST == 1'b1)
				AN <= 4'b1111;
			else 
				case (CNT)
					2'b00 : AN <= 4'b1110;
					2'b01 : AN <= 4'b1101;
					2'b10 : AN <= 4'b1011;
					2'b11 : AN <= 4'b0111;
					default : AN <= 4'b1111;
				endcase
		






		always @(posedge DCLK) begin
				CNT <= CNT + 1'b1;
		end
		





		always @(posedge CLK) begin
				if (clkCount == cntEndVal) begin
					DCLK <= 1'b1;
					clkCount <= 16'h0000;
				end
				else begin
					DCLK <= 1'b0;
					clkCount <= clkCount + 1'b1;
				end
		end
   
endmodule