data/full_repos/permissive/13111265/verilog/src/primitives/iob.v
data/verilator_xmls/d2ff925c-f26f-4ab1-b466-2edb559200c5.xml
module iob #(
    parameter ARCH = "GENERIC"
)
(
    input  wire i,
    input  wire t,
    output wire o,
    inout  wire pad
);

generate

if (ARCH == "GENERIC") begin
    assign o = pad;
    assign pad = t ? o : 1'bz;
end
else if ((ARCH == "XIL_SPARTAN6") || (ARCH == "XIL_VIRTEX6") || (ARCH == "XIL_7SERIES")) begin
    IOBUF io_buffer (
        .I(i),
        .T(t),
        .O(o),
        .IO(pad)
    );
end
else begin
    initial begin
        $display("IOB Module %m does not support ARCH = \"%s\".", ARCH);
        $finish();
    end
end

endgenerate

endmodule
module iob #(
    parameter ARCH = "GENERIC"
)
(
    input  wire i,
    input  wire t,
    output wire o,
    inout  wire pad
);


generate

if (ARCH == "GENERIC") begin
    assign o = pad;
    assign pad = t ? o : 1'bz;
end
else if ((ARCH == "XIL_SPARTAN6") || (ARCH == "XIL_VIRTEX6") || (ARCH == "XIL_7SERIES")) begin
    IOBUF io_buffer (
        .I(i),
        .T(t),
        .O(o),
        .IO(pad)
    );
end
else begin
    initial begin
        $display("IOB Module %m does not support ARCH = \"%s\".", ARCH);
        $finish();
    end
end

endgenerate

endmodule