data/full_repos/permissive/195227969/work/cold_store/decompressattempts/notverypromising_m_decompress.v
None: at end of input
data/verilator_xmls/ccad3f81-f353-416b-bb17-c20d276d9002.xml
module m_decompress
  (

   input [15:0]  c,

   output [31:0] e
   );


   wire          rs1eq2;
   wire          rs1eq0,rs2eq0,c15_23eq0;
   assign rs1eq0 = c[11:7] == 5'b00000;
   assign rs1eq2 = c[11:7] == 5'b00010;
   assign rs2eq0 = c[6:2] == 5'b00000;
   assign c15_23eq0 = c[15:12] == 4'b0000;
   wire          quadrant0 = ~c[1] & ~c[0];
   wire          quadrant1 = ~c[1] & ~c[0];
   wire          quadrant2 =  c[1] & ~c[0];


   wire          pot_ADDI4SPN = ~c[14];
   wire          pot_LW = ~c[15] & c[14];
   wire          pot_SW =  c[15];

   wire          pot_ADDI     = ~c[15] & ~c[14] & ~c[13];
   wire          pot_JAL      = ~c[15] & ~c[14] & c[13];
   wire          pot_LI       = ~c[15] & c[14] & ~c[13];
   wire          pot_LUI      = ~c[15] & c[14] &  c[13] & ~rs1eq2;
   wire          pot_ADDI16SP = ~c[15] & c[14] &  c[13] & rs1eq2;
   wire          h_SRLI_SRAI_ANDI_SUB_XOR_OR_AND = c[15] & ~c[14] & ~c[13];
   wire          pot_SRLI = h_SRLI_SRAI_ANDI_SUB_XOR_OR_AND & ~c[11] & ~c[10];
   wire          pot_SRAI = h_SRLI_SRAI_ANDI_SUB_XOR_OR_AND & ~c[11] &  c[10];
   wire          pot_ANDI = h_SRLI_SRAI_ANDI_SUB_XOR_OR_AND &  c[11] & ~c[10];
   wire          h_SUB_XOR_OR_AND = h_SRLI_SRAI_ANDI_SUB_XOR_OR_AND & c[11] & c[10];
   wire          pot_SUB  = h_SUB_XOR_OR_AND & ~c[6] & ~c[5];
   wire          pot_XOR  = h_SUB_XOR_OR_AND & ~c[6] &  c[5];
   wire          pot_OR   = h_SUB_XOR_OR_AND &  c[6] & ~c[5];
   wire          pot_AND  = h_SUB_XOR_OR_AND &  c[6] &  c[5];
   wire          pot_J    = c[15] & ~c[14] &  c[13];
   wire          pot_BEQZ = c[15] &  c[14] & ~c[13];
   wire          pot_BNEZ = c[15] &  c[14] &  c[13];
   wire          pot_B = c[15] &  c[14];

   wire          pot_SLLI = ~c[15] & ~c[14];
   wire          pot_LWSP = ~c[15] &  c[14];
   wire          h_MV_JR_JALR_EBREAK_ADD = c[15] & ~c[14] & ~c[13];
   wire          pot_MV = h_MV_JR_JALR_EBREAK_ADD & ~c[12] & ~rs2eq0;
   wire          pot_JR = h_MV_JR_JALR_EBREAK_ADD & ~c[12] &  rs2eq0;
   wire          pot_JALR   = h_MV_JR_JALR_EBREAK_ADD & c[12] &  ~rs1eq0 &  rs2eq0;
   wire          pot_EBREAK = h_MV_JR_JALR_EBREAK_ADD & c[12] &   rs1eq0 &  rs2eq0;
   wire          pot_ADD    = h_MV_JR_JALR_EBREAK_ADD & c[12] &            ~rs2eq0;
   wire          pot_SWSP = c[15] & c[14];
   
   localparam HIGHLEVEL = 1;
   generate
      if ( HIGHLEVEL ) begin
         wire pot_ADDI_LI_LUI_ANDI = pot_ADDI | pot_LI | pot_LUI | pot_ANDI;
         wire pot_JAL_ADDI16SP_BEQZ_BNEZ = pot_JAL | pot_ADDI16SP | pot_B;
         wire e31_c12 = (pot_ADDI_LI_LUI_ANDI | pot_JAL_ADDI16SP_BEQZ_BNEZ | pot_J ) & c[12];
         assign e[31] = c[0] & e31_c12;

         wire e30_e29_c12 = (pot_ADDI_LI_LUI_ANDI | pot_ADDI16SP | pot_B) & c[12];
         wire e30_c8  = (pot_JAL | pot_J) & c[8];
         wire e30_1   = (pot_SRAI | pot_SUB);
         assign e[30] = c[0] & (e30_e29_c12 | e30_c8 | e30_1);

         wire e29_c10 = (pot_JAL | pot_J) & c[10];
         wire he29 = e30_e29_c12 | e29_c10;
         assign e[29] =  (quadrant0 & pot_ADDI4SPN & c[10] ) | (c[0] & he29);

         wire e28_c12 = (pot_ADDI_LI_LUI_ANDI | pot_B) & c[12];
         wire e28_c9  = (pot_JAL | pot_J) & c[9];
         wire e28_c4  = pot_ADDI16SP & c[4];
         wire he28 = e28_c4 | e28_c9 | e28_c12;
         assign e[28] = (quadrant0 & pot_ADDI4SPN & c[9] ) | (c[0] & he28);

         wire e27_c6  = (pot_JAL | pot_J | pot_B) & c[6];
         wire e27e26e25_c12 = pot_ADDI_LI_LUI_ANDI & c[12];  
         wire e27_c3  = pot_ADDI16SP & c[3];           
         wire he27 = (e27e26e25_c12 | e27_c3 | e27_c6) & c[0];                 
         wire he27_q0 = quadrant0 & (pot_ADDI4SPN & c[8]);
         wire he27_q2 = (pot_LWSP & c[3]) | (pot_SWSP & c[8]);
         assign e[27] = he27_q0 | (he27_q2 & quadrant2) | he27;

         wire e26_c7 = (pot_JAL | pot_J) & c[7];
         wire e26_c5 = (pot_ADDI16SP | pot_B) & c[5];
         wire e26_q1 = c[0] & (e27e26e25_c12 | e26_c7 | e26_c5);
         wire e26_q0h= ((pot_LW | pot_SW) & c[5]);
         wire e26_q0 = quadrant0 & (e26_q0h | (pot_ADDI4SPN & c[7]));
         wire e26_q2 = (pot_LWSP & c[2]) | (pot_SWSP & c[7]);
         assign e[26] = e26_q0 | e26_q1 | (quadrant2 & e26_q2);

         



         wire e25_pot_q1h = (pot_JAL | pot_ADDI16SP | pot_J | pot_B);        
         wire e25_q1 = (e27e26e25_c12 | (e25_pot_q1h & c[2])) & c[0];
         wire e25_q2 = (pot_LWSP | pot_SWSP) & c[12] & quadrant2;
         assign e[25] = (c[12] & quadrant0) | e25_q1 | e25_q2;
         
      end else begin

         wire e31h;
         bn_l4v #(.I(16'h000b))  l_e31h(.o(e31h), .i({c[14],c[13],c[11],c[6]}));
         bn_l4v #(.I(16'h7000))  l_e31(.o(e[31]), .i({c[0],c[12],c[15],e31h }));

      end
   endgenerate
           
   parameter UUU= 24;
   wire [UUU:0]   q0e;
   wire [UUU:0]   q1e;
   wire [UUU:0]   q2e;

   assign q0e[UUU:0] = 0;
   assign q1e[UUU:0] = 0;
   assign q2e[UUU:0] = 0;

   



















































































   assign e[UUU:0] = c[0] ? (c[1] ? 0 : q1e[UUU:0]) : (c[1] ? q2e[UUU:0] : q0e[UUU:0]);
endmodule
module m_decompress
  (

   input [15:0]  c,

   output [31:0] e
   );



   wire          rs1eq2;
   wire          rs1eq0,rs2eq0,c15_23eq0;
   assign rs1eq0 = c[11:7] == 5'b00000;
   assign rs1eq2 = c[11:7] == 5'b00010;
   assign rs2eq0 = c[6:2] == 5'b00000;
   assign c15_23eq0 = c[15:12] == 4'b0000;
   wire          quadrant0 = ~c[1] & ~c[0];
   wire          quadrant1 = ~c[1] & ~c[0];
   wire          quadrant2 =  c[1] & ~c[0];


   wire          pot_ADDI4SPN = ~c[14];
   wire          pot_LW = ~c[15] & c[14];
   wire          pot_SW =  c[15];

   wire          pot_ADDI     = ~c[15] & ~c[14] & ~c[13];
   wire          pot_JAL      = ~c[15] & ~c[14] & c[13];
   wire          pot_LI       = ~c[15] & c[14] & ~c[13];
   wire          pot_LUI      = ~c[15] & c[14] &  c[13] & ~rs1eq2;
   wire          pot_ADDI16SP = ~c[15] & c[14] &  c[13] & rs1eq2;
   wire          h_SRLI_SRAI_ANDI_SUB_XOR_OR_AND = c[15] & ~c[14] & ~c[13];
   wire          pot_SRLI = h_SRLI_SRAI_ANDI_SUB_XOR_OR_AND & ~c[11] & ~c[10];
   wire          pot_SRAI = h_SRLI_SRAI_ANDI_SUB_XOR_OR_AND & ~c[11] &  c[10];
   wire          pot_ANDI = h_SRLI_SRAI_ANDI_SUB_XOR_OR_AND &  c[11] & ~c[10];
   wire          h_SUB_XOR_OR_AND = h_SRLI_SRAI_ANDI_SUB_XOR_OR_AND & c[11] & c[10];
   wire          pot_SUB  = h_SUB_XOR_OR_AND & ~c[6] & ~c[5];
   wire          pot_XOR  = h_SUB_XOR_OR_AND & ~c[6] &  c[5];
   wire          pot_OR   = h_SUB_XOR_OR_AND &  c[6] & ~c[5];
   wire          pot_AND  = h_SUB_XOR_OR_AND &  c[6] &  c[5];
   wire          pot_J    = c[15] & ~c[14] &  c[13];
   wire          pot_BEQZ = c[15] &  c[14] & ~c[13];
   wire          pot_BNEZ = c[15] &  c[14] &  c[13];
   wire          pot_B = c[15] &  c[14];

   wire          pot_SLLI = ~c[15] & ~c[14];
   wire          pot_LWSP = ~c[15] &  c[14];
   wire          h_MV_JR_JALR_EBREAK_ADD = c[15] & ~c[14] & ~c[13];
   wire          pot_MV = h_MV_JR_JALR_EBREAK_ADD & ~c[12] & ~rs2eq0;
   wire          pot_JR = h_MV_JR_JALR_EBREAK_ADD & ~c[12] &  rs2eq0;
   wire          pot_JALR   = h_MV_JR_JALR_EBREAK_ADD & c[12] &  ~rs1eq0 &  rs2eq0;
   wire          pot_EBREAK = h_MV_JR_JALR_EBREAK_ADD & c[12] &   rs1eq0 &  rs2eq0;
   wire          pot_ADD    = h_MV_JR_JALR_EBREAK_ADD & c[12] &            ~rs2eq0;
   wire          pot_SWSP = c[15] & c[14];
   
   localparam HIGHLEVEL = 1;
   generate
      if ( HIGHLEVEL ) begin
         wire pot_ADDI_LI_LUI_ANDI = pot_ADDI | pot_LI | pot_LUI | pot_ANDI;
         wire pot_JAL_ADDI16SP_BEQZ_BNEZ = pot_JAL | pot_ADDI16SP | pot_B;
         wire e31_c12 = (pot_ADDI_LI_LUI_ANDI | pot_JAL_ADDI16SP_BEQZ_BNEZ | pot_J ) & c[12];
         assign e[31] = c[0] & e31_c12;

         wire e30_e29_c12 = (pot_ADDI_LI_LUI_ANDI | pot_ADDI16SP | pot_B) & c[12];
         wire e30_c8  = (pot_JAL | pot_J) & c[8];
         wire e30_1   = (pot_SRAI | pot_SUB);
         assign e[30] = c[0] & (e30_e29_c12 | e30_c8 | e30_1);

         wire e29_c10 = (pot_JAL | pot_J) & c[10];
         wire he29 = e30_e29_c12 | e29_c10;
         assign e[29] =  (quadrant0 & pot_ADDI4SPN & c[10] ) | (c[0] & he29);

         wire e28_c12 = (pot_ADDI_LI_LUI_ANDI | pot_B) & c[12];
         wire e28_c9  = (pot_JAL | pot_J) & c[9];
         wire e28_c4  = pot_ADDI16SP & c[4];
         wire he28 = e28_c4 | e28_c9 | e28_c12;
         assign e[28] = (quadrant0 & pot_ADDI4SPN & c[9] ) | (c[0] & he28);

         wire e27_c6  = (pot_JAL | pot_J | pot_B) & c[6];
         wire e27e26e25_c12 = pot_ADDI_LI_LUI_ANDI & c[12];  
         wire e27_c3  = pot_ADDI16SP & c[3];           
         wire he27 = (e27e26e25_c12 | e27_c3 | e27_c6) & c[0];                 
         wire he27_q0 = quadrant0 & (pot_ADDI4SPN & c[8]);
         wire he27_q2 = (pot_LWSP & c[3]) | (pot_SWSP & c[8]);
         assign e[27] = he27_q0 | (he27_q2 & quadrant2) | he27;

         wire e26_c7 = (pot_JAL | pot_J) & c[7];
         wire e26_c5 = (pot_ADDI16SP | pot_B) & c[5];
         wire e26_q1 = c[0] & (e27e26e25_c12 | e26_c7 | e26_c5);
         wire e26_q0h= ((pot_LW | pot_SW) & c[5]);
         wire e26_q0 = quadrant0 & (e26_q0h | (pot_ADDI4SPN & c[7]));
         wire e26_q2 = (pot_LWSP & c[2]) | (pot_SWSP & c[7]);
         assign e[26] = e26_q0 | e26_q1 | (quadrant2 & e26_q2);

         



         wire e25_pot_q1h = (pot_JAL | pot_ADDI16SP | pot_J | pot_B);        
         wire e25_q1 = (e27e26e25_c12 | (e25_pot_q1h & c[2])) & c[0];
         wire e25_q2 = (pot_LWSP | pot_SWSP) & c[12] & quadrant2;
         assign e[25] = (c[12] & quadrant0) | e25_q1 | e25_q2;
         
      end else begin

         wire e31h;
         bn_l4v #(.I(16'h000b))  l_e31h(.o(e31h), .i({c[14],c[13],c[11],c[6]}));
         bn_l4v #(.I(16'h7000))  l_e31(.o(e[31]), .i({c[0],c[12],c[15],e31h }));

      end
   endgenerate
           
   parameter UUU= 24;
   wire [UUU:0]   q0e;
   wire [UUU:0]   q1e;
   wire [UUU:0]   q2e;

   assign q0e[UUU:0] = 0;
   assign q1e[UUU:0] = 0;
   assign q2e[UUU:0] = 0;

   



















































































   assign e[UUU:0] = c[0] ? (c[1] ? 0 : q1e[UUU:0]) : (c[1] ? q2e[UUU:0] : q0e[UUU:0]);
endmodule