data/full_repos/permissive/131921633/tv/Data/Memory/rom.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Data/Memory/rom.v:1: Cannot find include file: Altera/Mf.v\n`include "Altera/Mf.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Data/Memory,data/full_repos/permissive/131921633/Altera/Mf.v\n             data/full_repos/permissive/131921633/tv/Data/Memory,data/full_repos/permissive/131921633/Altera/Mf.v.v\n             data/full_repos/permissive/131921633/tv/Data/Memory,data/full_repos/permissive/131921633/Altera/Mf.v.sv\n             Altera/Mf.v\n             Altera/Mf.v.v\n             Altera/Mf.v.sv\n             obj_dir/Altera/Mf.v\n             obj_dir/Altera/Mf.v.v\n             obj_dir/Altera/Mf.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/rom.v:2: Cannot find include file: Util/Math.v\n`include "Util/Math.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/rom.v:3: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/rom.v:16: Define or directive not defined: \'`Data_Control_Control_T\'\n , `Data_Control_Control_T(input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/rom.v:16: syntax error, unexpected \'(\', expecting \'[\'\n , `Data_Control_Control_T(input) ctrl\n                           ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/rom.v:20: Define or directive not defined: \'`Util_Math_log2_expr\'\n`Util_Math_log2_expr\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/rom.v:31: syntax error, unexpected assign\nassign out = sub_wire0;\n^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Memory/rom.v:36: Define or directive not defined: \'`Data_Control_Control_Clock\'\n , .clock0         (`Data_Control_Control_Clock(ctrl))\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module Data_Memory_rom #
	( parameter FILE = "asm/test0.mif"
	, parameter ADDR_L = 64
	, parameter ADDR_W = Util_Math_log2(ADDR_L)
	, parameter DATA_W = 32
	)
	( input [ADDR_W-1:0]  addr
	, `Data_Control_Control_T(input) ctrl
	, output [DATA_W-1:0] out
	);

`Util_Math_log2_expr

`ifndef ALTERA_RESERVED_QIS

`endif

`ifndef ALTERA_RESERVED_QIS

`endif

wire [DATA_W-1:0] sub_wire0;
assign out = sub_wire0;


altsyncram altsyncram_component
	( .address_a      (addr)
	, .clock0         (`Data_Control_Control_Clock(ctrl))
	, .q_a            (sub_wire0)
	, .aclr0          (1'b0)
	, .aclr1          (1'b0)
	, .address_b      (1'b1)
	, .addressstall_a (1'b0)
	, .addressstall_b (1'b0)
	, .byteena_a      (1'b1)
	, .byteena_b      (1'b1)
	, .clock1         (1'b1)
	, .clocken0       (1'b1)
	, .clocken1       (1'b1)
	, .clocken2       (1'b1)
	, .clocken3       (1'b1)
	, .data_a         ({32{1'b1}})
	, .data_b         (1'b1)
	, .eccstatus      ()
	, .q_b            ()
	, .rden_a         (1'b1)
	, .rden_b         (1'b1)
	, .wren_a         (1'b0)
	, .wren_b         (1'b0)
	);
defparam
	altsyncram_component.address_aclr_a         = "NONE",
	altsyncram_component.clock_enable_input_a   = "BYPASS",
	altsyncram_component.clock_enable_output_a  = "BYPASS",
	altsyncram_component.init_file              = FILE,
	altsyncram_component.intended_device_family = "MAX 10",
	altsyncram_component.lpm_hint               = "ENABLE_RUNTIME_MOD = NO",
	altsyncram_component.lpm_type               = "altsyncram",
	altsyncram_component.numwords_a             = ADDR_L,
	altsyncram_component.operation_mode         = "ROM",
	altsyncram_component.outdata_aclr_a         = "NONE",
	altsyncram_component.outdata_reg_a          = "UNREGISTERED",
	altsyncram_component.ram_block_type         = "M9K",
	altsyncram_component.widthad_a              = ADDR_W,
	altsyncram_component.width_a                = DATA_W,
	altsyncram_component.width_byteena_a        = 1;

endmodule
module Data_Memory_rom #
	( parameter FILE = "asm/test0.mif"
	, parameter ADDR_L = 64
	, parameter ADDR_W = Util_Math_log2(ADDR_L)
	, parameter DATA_W = 32
	)
	( input [ADDR_W-1:0]  addr
	, `Data_Control_Control_T(input) ctrl
	, output [DATA_W-1:0] out
	);


`Util_Math_log2_expr

`ifndef ALTERA_RESERVED_QIS

`endif

`ifndef ALTERA_RESERVED_QIS

`endif

wire [DATA_W-1:0] sub_wire0;
assign out = sub_wire0;


altsyncram altsyncram_component
	( .address_a      (addr)
	, .clock0         (`Data_Control_Control_Clock(ctrl))
	, .q_a            (sub_wire0)
	, .aclr0          (1'b0)
	, .aclr1          (1'b0)
	, .address_b      (1'b1)
	, .addressstall_a (1'b0)
	, .addressstall_b (1'b0)
	, .byteena_a      (1'b1)
	, .byteena_b      (1'b1)
	, .clock1         (1'b1)
	, .clocken0       (1'b1)
	, .clocken1       (1'b1)
	, .clocken2       (1'b1)
	, .clocken3       (1'b1)
	, .data_a         ({32{1'b1}})
	, .data_b         (1'b1)
	, .eccstatus      ()
	, .q_b            ()
	, .rden_a         (1'b1)
	, .rden_b         (1'b1)
	, .wren_a         (1'b0)
	, .wren_b         (1'b0)
	);
defparam
	altsyncram_component.address_aclr_a         = "NONE",
	altsyncram_component.clock_enable_input_a   = "BYPASS",
	altsyncram_component.clock_enable_output_a  = "BYPASS",
	altsyncram_component.init_file              = FILE,
	altsyncram_component.intended_device_family = "MAX 10",
	altsyncram_component.lpm_hint               = "ENABLE_RUNTIME_MOD = NO",
	altsyncram_component.lpm_type               = "altsyncram",
	altsyncram_component.numwords_a             = ADDR_L,
	altsyncram_component.operation_mode         = "ROM",
	altsyncram_component.outdata_aclr_a         = "NONE",
	altsyncram_component.outdata_reg_a          = "UNREGISTERED",
	altsyncram_component.ram_block_type         = "M9K",
	altsyncram_component.widthad_a              = ADDR_W,
	altsyncram_component.width_a                = DATA_W,
	altsyncram_component.width_byteena_a        = 1;

endmodule