data/full_repos/permissive/134719388/alu32/alu32_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/134719388/alu32/alu32_testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n always #5 CLK=~CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/134719388/alu32/alu32_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n #1280;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/134719388/alu32/alu32_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n #1280;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/134719388/alu32/alu32_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1280;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/134719388/alu32/alu32_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #1280;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/134719388/alu32/alu32_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n #1280;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/134719388/alu32/alu32_testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n #1280;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/134719388/alu32/alu32_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n #1280;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/134719388/alu32/alu32_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n #1280;\n ^\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu32_testbench;
	reg [2:0]  ALUop;
	reg [31:0] inp1;
	reg [31:0] inp2;
	wire [31:0] out;
	reg CLK;
	
	initial CLK=0;
	always #5 CLK=~CLK;



	
	initial
	begin
	
	inp1 = 32'h00000005;
	inp2 = 32'h00000009;
	ALUop= 3'b000;
	#1280;
	inp1 = 32'h00000005;
	inp2 = 32'h00000009;
	ALUop= 3'b010;
	#1280;
	inp1 = 32'h00000008;
	inp2 = 32'h0000000C;
	ALUop= 3'b000;
	#1280;
	inp1 = 32'h00000008;
	inp2 = 32'h0000000C;
	ALUop= 3'b010;
	#1280;
	inp1 = 32'h00000003;
	inp2 = 32'h00000007;
	ALUop= 3'b010;
	#1280;
	ALUop= 3'b011;
	#1280;
	ALUop= 3'b100;
	#1280;
	ALUop= 3'b011;
	#1280;
	
	end
	

endmodule
module alu32_testbench;

	reg [2:0]  ALUop;
	reg [31:0] inp1;
	reg [31:0] inp2;
	wire [31:0] out;
	reg CLK;
	
	initial CLK=0;
	always #5 CLK=~CLK;



	
	initial
	begin
	
	inp1 = 32'h00000005;
	inp2 = 32'h00000009;
	ALUop= 3'b000;
	#1280;
	inp1 = 32'h00000005;
	inp2 = 32'h00000009;
	ALUop= 3'b010;
	#1280;
	inp1 = 32'h00000008;
	inp2 = 32'h0000000C;
	ALUop= 3'b000;
	#1280;
	inp1 = 32'h00000008;
	inp2 = 32'h0000000C;
	ALUop= 3'b010;
	#1280;
	inp1 = 32'h00000003;
	inp2 = 32'h00000007;
	ALUop= 3'b010;
	#1280;
	ALUop= 3'b011;
	#1280;
	ALUop= 3'b100;
	#1280;
	ALUop= 3'b011;
	#1280;
	
	end
	

endmodule