data/full_repos/permissive/128100618/SV/FPU_27bit.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/128100618/SV/FPU_27bit.v:26: Cannot find file containing module: 'FpMul'\n    FpMul s1_mult ( .iA(y_1), .iB(y_1), .oProd(y_1_out) );\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/128100618/SV,data/full_repos/permissive/128100618/FpMul\n             data/full_repos/permissive/128100618/SV,data/full_repos/permissive/128100618/FpMul.v\n             data/full_repos/permissive/128100618/SV,data/full_repos/permissive/128100618/FpMul.sv\n             FpMul\n             FpMul.v\n             FpMul.sv\n             obj_dir/FpMul\n             obj_dir/FpMul.v\n             obj_dir/FpMul.sv\n%Error: data/full_repos/permissive/128100618/SV/FPU_27bit.v:30: Cannot find file containing module: 'FpMul'\n    FpMul s2_mult ( .iA(half_iA_2), .iB(mult_2_in), .oProd(y_2_out) );\n    ^~~~~\n%Error: data/full_repos/permissive/128100618/SV/FPU_27bit.v:34: Cannot find file containing module: 'FpAdd'\n    FpAdd s3_add ( .iCLK(iCLK), .iA({~add_3_in[26],add_3_in[25:0]}), .iB(27'd33423360), .oSum(y_3_out) );\n    ^~~~~\n%Error: data/full_repos/permissive/128100618/SV/FPU_27bit.v:39: Cannot find file containing module: 'FpMul'\n    FpMul s5_mult ( .iA(y_5), .iB(mult_5_in), .oProd(oInvSqrt) );\n    ^~~~~\n%Error: Exiting due to 4 error(s)\n"
module FpInvSqrt (
    input             iCLK,
    input      [26:0] iA,
    output     [26:0] oInvSqrt
);


    wire        A_s;
    wire [7:0]  A_e;
    wire [17:0] A_f;
    assign A_s = iA[26];
    assign A_e = iA[25:18];
    assign A_f = iA[17:0];


    wire [26:0] y_1, y_1_out, half_iA_1;
    assign y_1 = 27'd49920718 - (iA>>1);
    assign half_iA_1 = {A_s, A_e-8'd1,A_f};
    FpMul s1_mult ( .iA(y_1), .iB(y_1), .oProd(y_1_out) );

    reg [26:0] y_2, mult_2_in, half_iA_2;
    wire [26:0] y_2_out;
    FpMul s2_mult ( .iA(half_iA_2), .iB(mult_2_in), .oProd(y_2_out) );

    reg [26:0] y_3, add_3_in;
    wire [26:0] y_3_out;
    FpAdd s3_add ( .iCLK(iCLK), .iA({~add_3_in[26],add_3_in[25:0]}), .iB(27'd33423360), .oSum(y_3_out) );

    reg [26:0] y_4;

    reg [26:0] y_5, mult_5_in;
    FpMul s5_mult ( .iA(y_5), .iB(mult_5_in), .oProd(oInvSqrt) );

    always @(posedge iCLK) begin

    y_2 <= y_1;
    mult_2_in <= y_1_out;
    half_iA_2 <= half_iA_1;

    y_3 <= y_2;
    add_3_in <= y_2_out;

    y_4 <= y_3;

    y_5 <= y_4;
    mult_5_in <= y_3_out;
    end


endmodule
module FpInvSqrt (
    input             iCLK,
    input      [26:0] iA,
    output     [26:0] oInvSqrt
);



    wire        A_s;
    wire [7:0]  A_e;
    wire [17:0] A_f;
    assign A_s = iA[26];
    assign A_e = iA[25:18];
    assign A_f = iA[17:0];


    wire [26:0] y_1, y_1_out, half_iA_1;
    assign y_1 = 27'd49920718 - (iA>>1);
    assign half_iA_1 = {A_s, A_e-8'd1,A_f};
    FpMul s1_mult ( .iA(y_1), .iB(y_1), .oProd(y_1_out) );

    reg [26:0] y_2, mult_2_in, half_iA_2;
    wire [26:0] y_2_out;
    FpMul s2_mult ( .iA(half_iA_2), .iB(mult_2_in), .oProd(y_2_out) );

    reg [26:0] y_3, add_3_in;
    wire [26:0] y_3_out;
    FpAdd s3_add ( .iCLK(iCLK), .iA({~add_3_in[26],add_3_in[25:0]}), .iB(27'd33423360), .oSum(y_3_out) );

    reg [26:0] y_4;

    reg [26:0] y_5, mult_5_in;
    FpMul s5_mult ( .iA(y_5), .iB(mult_5_in), .oProd(oInvSqrt) );

    always @(posedge iCLK) begin

    y_2 <= y_1;
    mult_2_in <= y_1_out;
    half_iA_2 <= half_iA_1;

    y_3 <= y_2;
    add_3_in <= y_2_out;

    y_4 <= y_3;

    y_5 <= y_4;
    mult_5_in <= y_3_out;
    end


endmodule