data/full_repos/permissive/133653839/i2c_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:29: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n   wr_state  <= idle;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:30: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle_1\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n   rd_state  <= idle_1;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:34: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'start\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n   wr_state <= start;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:35: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'start_1\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n   rd_state <= start_1;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:44: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'start\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n     wr_state <= start;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:48: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'wr_data\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n      wr_state <= wr_data;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:52: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'wr_data\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n       wr_state <= wr_data;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:54: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n     else wr_state <= idle;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:57: Bit extraction of var[14:0] requires 4 bit index, not 15 bits.\n                                                                  : ... In instance i2c_fifo\n     fifo_bank[count] <= addr_data;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:59: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'stop\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n       wr_state <= stop;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:65: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n     wr_state    <= idle;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:41: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'idle\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n   case (wr_state)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:41: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'start\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n   case (wr_state)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:41: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'wr_data\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n   case (wr_state)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:41: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'stop\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n   case (wr_state)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:75: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'start_1\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n     rd_state <= start_1;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:79: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'rd_data_1\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n      rd_state <= rd_data_1;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:83: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'rd_data_1\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n       rd_state <= rd_data_1;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:85: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle_1\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n     else rd_state <= idle_1;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:88: Bit extraction of var[14:0] requires 4 bit index, not 15 bits.\n                                                                  : ... In instance i2c_fifo\n     data_out <= fifo_bank[count];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:90: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'stop_1\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n       rd_state <= stop_1;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:96: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle_1\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n     rd_state <= idle_1;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:72: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'idle_1\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n   case (rd_state)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:72: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'start_1\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n   case (rd_state)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:72: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'rd_data_1\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n   case (rd_state)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/133653839/i2c_fifo.v:72: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'stop_1\' generates 2 bits.\n                                                                  : ... In instance i2c_fifo\n   case (rd_state)\n   ^~~~\n%Error: Exiting due to 26 warning(s)\n'
module i2c_fifo(clk,rst,addr_data,data_out,empty,full,wr_en,rd_en);
	input	wire 	clk,rst,wr_en,rd_en;
	input	wire 	addr_data;
	output	reg		data_out;
	output	reg		empty,full;
	
	
	reg     [14:0]	fifo_bank;
	reg		[2:0]	wr_state;
	reg		[2:0]	rd_state;
	reg		[14:0]	count;
	
	parameter 	idle      = 2'b00,
				start     = 2'b01,
				wr_data   = 2'b10,
				stop      = 2'b11;
	
	parameter 	idle_1    = 2'b00,
				start_1   = 2'b01,
				rd_data_1 = 2'b10,
				stop_1    = 2'b11;
					
	
	
	always@(posedge clk)
		begin
			if(rst == 1)begin
			fifo_bank <= 0;
			wr_state  <= idle;
			rd_state  <= idle_1;
			end
			
			else begin
			wr_state <= start;
			rd_state <= start_1;
			end
		end
	
	always@(posedge clk)
		begin:WRITE
			case (wr_state)
			
			idle:begin
					wr_state <= start;
				end
			start:begin
					if(wr_en == 1)begin
						wr_state <= wr_data;
						count <= 14;
					end
					else if((wr_en == 1) && (rd_en == 1))begin
							wr_state <= wr_data;
							end
					else wr_state <= idle;
				end
			wr_data:begin
					fifo_bank[count] <= addr_data;
						if(count == 0)
							wr_state <= stop;
						else
						count <= count - 1;
					end
				stop:begin
					data_out <= 0;
					wr_state    <= idle;
					end
			endcase	
		end	
					
		always@(posedge clk)
		begin:READ
			case (rd_state)
		
			idle_1:begin
					rd_state <= start_1;
				end
			start_1:begin
					if(rd_en == 1)begin
						rd_state <= rd_data_1;
						count <= 14;
					end
					else if((wr_en == 1) && (rd_en == 1))begin
							rd_state <= rd_data_1;
							end
					else rd_state <= idle_1;
				end
			rd_data_1:begin
					data_out <= fifo_bank[count];
						if(count == 0)
							rd_state <= stop_1;
						else
						count <= count - 1;
					end
			stop_1:begin
					data_out <= 0;
					rd_state <= idle_1;
				end
			endcase
		end
			
endmodule
module i2c_fifo(clk,rst,addr_data,data_out,empty,full,wr_en,rd_en);

	input	wire 	clk,rst,wr_en,rd_en;
	input	wire 	addr_data;
	output	reg		data_out;
	output	reg		empty,full;
	
	
	reg     [14:0]	fifo_bank;
	reg		[2:0]	wr_state;
	reg		[2:0]	rd_state;
	reg		[14:0]	count;
	
	parameter 	idle      = 2'b00,
				start     = 2'b01,
				wr_data   = 2'b10,
				stop      = 2'b11;
	
	parameter 	idle_1    = 2'b00,
				start_1   = 2'b01,
				rd_data_1 = 2'b10,
				stop_1    = 2'b11;
					
	
	
	always@(posedge clk)
		begin
			if(rst == 1)begin
			fifo_bank <= 0;
			wr_state  <= idle;
			rd_state  <= idle_1;
			end
			
			else begin
			wr_state <= start;
			rd_state <= start_1;
			end
		end
	
	always@(posedge clk)
		begin:WRITE
			case (wr_state)
			
			idle:begin
					wr_state <= start;
				end
			start:begin
					if(wr_en == 1)begin
						wr_state <= wr_data;
						count <= 14;
					end
					else if((wr_en == 1) && (rd_en == 1))begin
							wr_state <= wr_data;
							end
					else wr_state <= idle;
				end
			wr_data:begin
					fifo_bank[count] <= addr_data;
						if(count == 0)
							wr_state <= stop;
						else
						count <= count - 1;
					end
				stop:begin
					data_out <= 0;
					wr_state    <= idle;
					end
			endcase	
		end	
					
		always@(posedge clk)
		begin:READ
			case (rd_state)
		
			idle_1:begin
					rd_state <= start_1;
				end
			start_1:begin
					if(rd_en == 1)begin
						rd_state <= rd_data_1;
						count <= 14;
					end
					else if((wr_en == 1) && (rd_en == 1))begin
							rd_state <= rd_data_1;
							end
					else rd_state <= idle_1;
				end
			rd_data_1:begin
					data_out <= fifo_bank[count];
						if(count == 0)
							rd_state <= stop_1;
						else
						count <= count - 1;
					end
			stop_1:begin
					data_out <= 0;
					rd_state <= idle_1;
				end
			endcase
		end
			
endmodule