data/full_repos/permissive/168189509/hdl/i2s_rx.v
data/verilator_xmls/aa561289-cd9f-4b44-8745-6ac901c81f99.xml
module i2s_rx #(
    parameter WIDTH = 32
) (
    input wire lrck,
    input wire sclk,

    input wire sdin,

    output reg [WIDTH - 1 : 0] pldout,
    output reg [WIDTH - 1 : 0] prdout
);

    reg lrck_d1;

    reg lrck_d2;

    always @(posedge sclk) begin
        lrck_d1 <= lrck;
        lrck_d2 <= lrck_d1;
    end


    wire lrck_p;

    assign lrck_p = lrck_d1 ^ lrck_d2;


    reg [5 : 0] cnt;

    always @(negedge sclk) begin
        if (lrck_p) begin
            cnt <= 6'b0;
        end else begin
            cnt <= cnt + 6'b1;
        end
    end


    reg [WIDTH - 1 : 0] pdata;

    always @(posedge sclk) begin
        if (lrck_p) begin
            pdata <= {WIDTH {1'b0}};
        end else if (cnt < WIDTH) begin
            pdata[(WIDTH - 1) - cnt] <= sdin;
        end
    end


    always @(negedge sclk) begin
        if (lrck_p) begin
            if (lrck_d1) begin
                prdout <= pdata;
            end else begin
                pldout <= pdata;
            end
        end
    end

endmodule
module i2s_rx #(
    parameter WIDTH = 32
) (
    input wire lrck,
    input wire sclk,

    input wire sdin,

    output reg [WIDTH - 1 : 0] pldout,
    output reg [WIDTH - 1 : 0] prdout
);


    reg lrck_d1;

    reg lrck_d2;

    always @(posedge sclk) begin
        lrck_d1 <= lrck;
        lrck_d2 <= lrck_d1;
    end


    wire lrck_p;

    assign lrck_p = lrck_d1 ^ lrck_d2;


    reg [5 : 0] cnt;

    always @(negedge sclk) begin
        if (lrck_p) begin
            cnt <= 6'b0;
        end else begin
            cnt <= cnt + 6'b1;
        end
    end


    reg [WIDTH - 1 : 0] pdata;

    always @(posedge sclk) begin
        if (lrck_p) begin
            pdata <= {WIDTH {1'b0}};
        end else if (cnt < WIDTH) begin
            pdata[(WIDTH - 1) - cnt] <= sdin;
        end
    end


    always @(negedge sclk) begin
        if (lrck_p) begin
            if (lrck_d1) begin
                prdout <= pdata;
            end else begin
                pldout <= pdata;
            end
        end
    end

endmodule