data/full_repos/permissive/20270692/labs/lab10/shift_register_4_beh_tb.v
 line:74: before: "$"
1: b'%Error: data/full_repos/permissive/20270692/labs/lab10/shift_register_4_beh_tb.v:6: Cannot find include file: shift_register_4_beh.v\n`include "shift_register_4_beh.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab10,data/full_repos/permissive/20270692/shift_register_4_beh.v\n             data/full_repos/permissive/20270692/labs/lab10,data/full_repos/permissive/20270692/shift_register_4_beh.v.v\n             data/full_repos/permissive/20270692/labs/lab10,data/full_repos/permissive/20270692/shift_register_4_beh.v.sv\n             shift_register_4_beh.v\n             shift_register_4_beh.v.v\n             shift_register_4_beh.v.sv\n             obj_dir/shift_register_4_beh.v\n             obj_dir/shift_register_4_beh.v.v\n             obj_dir/shift_register_4_beh.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab10/shift_register_4_beh_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  initial #20000 $finish;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab10/shift_register_4_beh_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n      forever #5 t_clock=~t_clock;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab10/shift_register_4_beh_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n      forever  #100 s1=~s1;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab10/shift_register_4_beh_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n      forever  #200 s0=~s0;\n               ^\n%Error: data/full_repos/permissive/20270692/labs/lab10/shift_register_4_beh_tb.v:84: Unsupported or unknown PLI call: $monitor\n      $monitor("time=%05d",$time,,"| CurState:%04b Input:%b|%04b|%b S:%b%b Clear:%b", a_par, msb_in, i_par, lsb_in, s1, s0, clear);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/20270692/labs/lab10/shift_register_4_beh_tb.v:84: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      $monitor("time=%05d",$time,,"| CurState:%04b Input:%b|%04b|%b S:%b%b Clear:%b", a_par, msb_in, i_par, lsb_in, s1, s0, clear);\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab10/shift_register_4_beh_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n      #20000\n      ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module shift_register_4_beh_tb (clear);

  input clear ;
  wire clear ;

  wire [3:0] a_par;
  reg [3:0] i_par;
  reg msb_in;
  reg lsb_in;
  reg [0:0] t_i_par_0[10000:0];
  reg [0:0] t_i_par_1[10000:0];
  reg [0:0] t_i_par_2[10000:0];
  reg [0:0] t_i_par_3[10000:0];
  reg [0:0] t_msb_in[10000:0];
  reg [0:0] t_lsb_in[10000:0];
  reg t_clock,s0,s1;
  reg [31:0] vectornum;





  initial #20000 $finish;

  initial
    begin
      t_clock=0;
      forever #5 t_clock=~t_clock;
    end

  initial
    begin
      s1=0;
      forever  #100 s1=~s1;
    end

  initial
    begin
      s0=0;
      forever  #200 s0=~s0;
    end

  initial
    begin

      $readmemb("bit_str_i_par_0.txt",t_i_par_0);
      $readmemb("bit_str_i_par_1.txt",t_i_par_1);
      $readmemb("bit_str_i_par_2.txt",t_i_par_2);
      $readmemb("bit_str_i_par_3.txt",t_i_par_3);
      $readmemb("bit_str_msb_in.txt",t_msb_in);
      $readmemb("bit_str_lsb_in.txt",t_lsb_in);

      vectornum=0;
    end

  always @(negedge t_clock)
    begin
      i_par[0]<=t_i_par_0[vectornum];
      i_par[1]<=t_i_par_1[vectornum];
      i_par[2]<=t_i_par_2[vectornum];
      i_par[3]<=t_i_par_3[vectornum];

      msb_in<=t_msb_in[vectornum];
      lsb_in<=t_lsb_in[vectornum];

      vectornum<=vectornum+1;
    end

  shift_register_4_beh M0 (a_par, i_par, s1, s0, msb_in, lsb_in, t_clock, clear);

  initial
    begin
      $monitor("time=%05d",$time,,"| CurState:%04b Input:%b|%04b|%b S:%b%b Clear:%b", a_par, msb_in, i_par, lsb_in, s1, s0, clear);
      #20000
      $finish;
    end

endmodule
module shift_register_4_beh_tb (clear);


  input clear ;
  wire clear ;

  wire [3:0] a_par;
  reg [3:0] i_par;
  reg msb_in;
  reg lsb_in;
  reg [0:0] t_i_par_0[10000:0];
  reg [0:0] t_i_par_1[10000:0];
  reg [0:0] t_i_par_2[10000:0];
  reg [0:0] t_i_par_3[10000:0];
  reg [0:0] t_msb_in[10000:0];
  reg [0:0] t_lsb_in[10000:0];
  reg t_clock,s0,s1;
  reg [31:0] vectornum;





  initial #20000 $finish;

  initial
    begin
      t_clock=0;
      forever #5 t_clock=~t_clock;
    end

  initial
    begin
      s1=0;
      forever  #100 s1=~s1;
    end

  initial
    begin
      s0=0;
      forever  #200 s0=~s0;
    end

  initial
    begin

      $readmemb("bit_str_i_par_0.txt",t_i_par_0);
      $readmemb("bit_str_i_par_1.txt",t_i_par_1);
      $readmemb("bit_str_i_par_2.txt",t_i_par_2);
      $readmemb("bit_str_i_par_3.txt",t_i_par_3);
      $readmemb("bit_str_msb_in.txt",t_msb_in);
      $readmemb("bit_str_lsb_in.txt",t_lsb_in);

      vectornum=0;
    end

  always @(negedge t_clock)
    begin
      i_par[0]<=t_i_par_0[vectornum];
      i_par[1]<=t_i_par_1[vectornum];
      i_par[2]<=t_i_par_2[vectornum];
      i_par[3]<=t_i_par_3[vectornum];

      msb_in<=t_msb_in[vectornum];
      lsb_in<=t_lsb_in[vectornum];

      vectornum<=vectornum+1;
    end

  shift_register_4_beh M0 (a_par, i_par, s1, s0, msb_in, lsb_in, t_clock, clear);

  initial
    begin
      $monitor("time=%05d",$time,,"| CurState:%04b Input:%b|%04b|%b S:%b%b Clear:%b", a_par, msb_in, i_par, lsb_in, s1, s0, clear);
      #20000
      $finish;
    end

endmodule