data/full_repos/permissive/166008742/src/tb_buf_manager.v
 line:69: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_buf_manager.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/166008742/src/tb_buf_manager.v:69: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_buf_manager.v:72: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_buf_manager.v:76: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/166008742/src/tb_buf_manager.v:83: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/166008742/src/tb_buf_manager.v:89: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/166008742/src/tb_buf_manager.v:97: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_buf_manager.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_buf_manager();
    parameter ADDR_WIDTH = 16;
    parameter DATA_WIDTH = 32;
    parameter NBUFS = 13;

    reg reset;
    reg clk;


    reg [ADDR_WIDTH-1:0] wbs_address;
    reg [DATA_WIDTH-1:0] wbs_writedata;
    reg wbs_strobe;
    reg wbs_cycle;
    reg wbs_write;


    wire wbs_ack;
    wire [DATA_WIDTH-1:0] wbs_readdata;


    reg [DATA_WIDTH-1:0] buf_id;


    buf_manager #(ADDR_WIDTH, DATA_WIDTH, NBUFS) dut(
        .reset(reset),
        .clk(clk),


        .wbs_address(wbs_address),
        .wbs_writedata(wbs_writedata),
        .wbs_readdata(wbs_readdata),
        .wbs_strobe(wbs_strobe),
        .wbs_cycle(wbs_cycle),
        .wbs_write(wbs_write),
        .wbs_ack(wbs_ack)
    );

    always begin
        #1;
        clk <= ~clk;
    end

    initial begin
            clk <= 0;
            reset <= 1;
            wbs_address <= 0;
            wbs_writedata <= 0;
            wbs_strobe <= 0;
            wbs_cycle <= 0;
            wbs_write <= 0;

        repeat (100) @(posedge clk);
            reset <= 0;

        repeat (100) @(posedge clk);

        repeat (2) begin
            repeat (NBUFS) begin
                @(posedge clk);
                wbs_address <= 0;
                wbs_writedata <= 0;
                wbs_write <= 0;
                wbs_strobe <= 1;
                wbs_cycle <= 1;

                @(posedge clk);
                wbs_strobe <= 0;
                wbs_cycle <= 0;
            end

            for (buf_id=0; buf_id < NBUFS; buf_id = buf_id+1) begin
                @(posedge clk);
                wbs_address <= 0;
                wbs_writedata <= buf_id;
                wbs_write <= 1;

                wbs_strobe <= 1;
                wbs_cycle <= 1;

                @(posedge clk);
                wbs_strobe <= 0;
                wbs_cycle <= 0;
            end
        end

        #100;
    end

endmodule
module tb_buf_manager();

    parameter ADDR_WIDTH = 16;
    parameter DATA_WIDTH = 32;
    parameter NBUFS = 13;

    reg reset;
    reg clk;


    reg [ADDR_WIDTH-1:0] wbs_address;
    reg [DATA_WIDTH-1:0] wbs_writedata;
    reg wbs_strobe;
    reg wbs_cycle;
    reg wbs_write;


    wire wbs_ack;
    wire [DATA_WIDTH-1:0] wbs_readdata;


    reg [DATA_WIDTH-1:0] buf_id;


    buf_manager #(ADDR_WIDTH, DATA_WIDTH, NBUFS) dut(
        .reset(reset),
        .clk(clk),


        .wbs_address(wbs_address),
        .wbs_writedata(wbs_writedata),
        .wbs_readdata(wbs_readdata),
        .wbs_strobe(wbs_strobe),
        .wbs_cycle(wbs_cycle),
        .wbs_write(wbs_write),
        .wbs_ack(wbs_ack)
    );

    always begin
        #1;
        clk <= ~clk;
    end

    initial begin
            clk <= 0;
            reset <= 1;
            wbs_address <= 0;
            wbs_writedata <= 0;
            wbs_strobe <= 0;
            wbs_cycle <= 0;
            wbs_write <= 0;

        repeat (100) @(posedge clk);
            reset <= 0;

        repeat (100) @(posedge clk);

        repeat (2) begin
            repeat (NBUFS) begin
                @(posedge clk);
                wbs_address <= 0;
                wbs_writedata <= 0;
                wbs_write <= 0;
                wbs_strobe <= 1;
                wbs_cycle <= 1;

                @(posedge clk);
                wbs_strobe <= 0;
                wbs_cycle <= 0;
            end

            for (buf_id=0; buf_id < NBUFS; buf_id = buf_id+1) begin
                @(posedge clk);
                wbs_address <= 0;
                wbs_writedata <= buf_id;
                wbs_write <= 1;

                wbs_strobe <= 1;
                wbs_cycle <= 1;

                @(posedge clk);
                wbs_strobe <= 0;
                wbs_cycle <= 0;
            end
        end

        #100;
    end

endmodule