data/full_repos/permissive/190698744/5 - More Verilog Features/2 - reduction operators.v
1: b'%Error: Invalid Option: -\n'
module top_module (
    input [7:0] in,
    output parity); 

    
    assign parity = ^in;

endmodule
module top_module (
    input [7:0] in,
    output parity);
 

    
    assign parity = ^in;

endmodule