data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v
'utf-8' codec can't decode byte 0xc1 in position 38121: invalid start byte
1: b'%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcOrigin,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcOrigin,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcOrigin,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:3: Cannot find include file: riscv.v\n`include "riscv.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:4: Cannot find include file: rom_ram.v\n`include "rom_ram.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:15: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus] inst_addr;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] inst_addr;\n                  ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:16: Define or directive not defined: \'`InstBus\'\n wire[`InstBus] inst;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:16: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstBus] inst;\n              ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:22: Define or directive not defined: \'`ValidBitBus\'\n wire[`ValidBitBus] rvalid_bit;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`ValidBitBus] rvalid_bit;\n                  ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:23: Define or directive not defined: \'`DataAddrBus\'\n wire[`DataAddrBus] raddr;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`DataAddrBus] raddr;\n                  ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:24: Define or directive not defined: \'`DataBus\'\n wire[`DataBus] rdata;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`DataBus] rdata;\n              ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:26: Define or directive not defined: \'`ValidBitBus\'\n wire[`ValidBitBus] wvalid_bit;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:26: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`ValidBitBus] wvalid_bit;\n                  ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:27: Define or directive not defined: \'`DataAddrBus\'\n wire[`DataAddrBus] waddr;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`DataAddrBus] waddr;\n                  ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:28: Define or directive not defined: \'`DataBus\'\n wire[`DataBus] wdata;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`DataBus] wdata;\n              ^\n%Error: Exiting due to 19 error(s)\n'
module riscv_min_sopc(
	input wire clk,
	input wire rst
	
);


	wire[`InstAddrBus] inst_addr;
	wire[`InstBus] inst;
	wire rom_ce;
	wire req_if;
	

	wire re;
	wire[`ValidBitBus] rvalid_bit;
	wire[`DataAddrBus] raddr;
	wire[`DataBus] rdata;
	wire we;
	wire[`ValidBitBus] wvalid_bit;
	wire[`DataAddrBus] waddr;
	wire[`DataBus] wdata;
	wire ram_ce;
	
	
	riscv riscv0(
		.clk(clk),.rst(rst),
	
		.rom_addr_o(inst_addr), .rom_data_i(inst), .rom_ce_o(rom_ce), .req_if(req_if),
		
		.ram_ce_o(ram_ce),
		.ram_re_m(re), .ram_rvalid_bit(rvalid_bit), .ram_raddr_m(raddr), .ram_rdata_m(rdata),
		.ram_we_m(we), .ram_wvalid_bit(wvalid_bit), .ram_waddr_m(waddr), .ram_wdata_m(wdata)
	);
	
	rom_ram rom_ram0(
		.rom_ce(rom_ce),		
		.addr(inst_addr),
		.inst(inst),
		
		.stall_req(req_if),
	
		.ram_ce(ram_ce),
		
		.we(we), .wvalid_bit(wvalid_bit), .waddr(waddr), .data_i(wdata),
		.re(re), .rvalid_bit(rvalid_bit), .raddr(raddr), .data_o(rdata)	
	
	);





	


		




endmodule
module riscv_min_sopc(
	input wire clk,
	input wire rst
	
);



	wire[`InstAddrBus] inst_addr;
	wire[`InstBus] inst;
	wire rom_ce;
	wire req_if;
	

	wire re;
	wire[`ValidBitBus] rvalid_bit;
	wire[`DataAddrBus] raddr;
	wire[`DataBus] rdata;
	wire we;
	wire[`ValidBitBus] wvalid_bit;
	wire[`DataAddrBus] waddr;
	wire[`DataBus] wdata;
	wire ram_ce;
	
	
	riscv riscv0(
		.clk(clk),.rst(rst),
	
		.rom_addr_o(inst_addr), .rom_data_i(inst), .rom_ce_o(rom_ce), .req_if(req_if),
		
		.ram_ce_o(ram_ce),
		.ram_re_m(re), .ram_rvalid_bit(rvalid_bit), .ram_raddr_m(raddr), .ram_rdata_m(rdata),
		.ram_we_m(we), .ram_wvalid_bit(wvalid_bit), .ram_waddr_m(waddr), .ram_wdata_m(wdata)
	);
	
	rom_ram rom_ram0(
		.rom_ce(rom_ce),		
		.addr(inst_addr),
		.inst(inst),
		
		.stall_req(req_if),
	
		.ram_ce(ram_ce),
		
		.we(we), .wvalid_bit(wvalid_bit), .waddr(waddr), .data_i(wdata),
		.re(re), .rvalid_bit(rvalid_bit), .raddr(raddr), .data_o(rdata)	
	
	);





	


		




endmodule