data/full_repos/permissive/154371523/Code/rtl/xtop_tb.v
 line:207: before: "$"
1: b'%Error: data/full_repos/permissive/154371523/Code/rtl/xtop_tb.v:3: Cannot find include file: xdefs.vh\n`include "xdefs.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh.v\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh.sv\n             xdefs.vh\n             xdefs.vh.v\n             xdefs.vh.sv\n             obj_dir/xdefs.vh\n             obj_dir/xdefs.vh.v\n             obj_dir/xdefs.vh.sv\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop_tb.v:4: Cannot find include file: xregfdefs.vh\n`include "xregfdefs.vh"\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop_tb.v:35: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W-1:0] data [2**`REGF_ADDR_W-1:0];\n        ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop_tb.v:35: Define or directive not defined: \'`REGF_ADDR_W\'\n   reg [`DATA_W-1:0] data [2**`REGF_ADDR_W-1:0];\n                              ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/154371523/Code/rtl/xtop_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n      #(clk_period+1)\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/154371523/Code/rtl/xtop_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n      #clk_period\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/154371523/Code/rtl/xtop_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n      while(1\'b1) #clk_period;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/154371523/Code/rtl/xtop_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n      #clk_period $finish;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/154371523/Code/rtl/xtop_tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n     #(clk_period/2) clk = ~clk;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/154371523/Code/rtl/xtop_tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n   #(ps2_clk_period/2) ps2_clk = ~ps2_clk;\n   ^\n%Error: data/full_repos/permissive/154371523/Code/rtl/xtop_tb.v:183: Define or directive not defined: \'`DATA_W\'\n   wire [`DATA_W-1:0] r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;\n         ^~~~~~~\n%Error: Exiting due to 5 error(s), 6 warning(s)\n'
module xtop_tb;
   

   parameter clk_period = 20;
	parameter ps2_clk_period = 50000;




   reg clk;
   reg rst;



   reg ps2_data;
   reg ps2_clk;

   wire push_AC;
   wire push_C;

   wire[11:0]  disp_ctrl;
	
	wire [7:0]   gpo_out;
   


   integer 		   k, start_time;


   reg [`DATA_W-1:0] data [2**`REGF_ADDR_W-1:0];
	

	reg [10:0] ps2_input_data [29:0];
	reg [3:0] ps2_bit_index;
	reg [4:0] ps2_byte_index;
   

   xtop uut (
	      .clk(clk),
         .rst(rst),
	      

         
          .ps2_data(ps2_data),
          .ps2_clk(ps2_clk),
          .disp_ctrl(disp_ctrl)
    
	      );
   
   initial begin
      
`ifdef DEBUG
      $dumpfile("xtop.vcd");
      $dumpvars();
`endif
        

      clk = 1;
      rst = 0;
		ps2_clk = 1;
		ps2_data = 1;
		
		ps2_byte_index = 0;
		ps2_bit_index = 0;
		
		for (k = 0; k < 30; k=k+1) begin
	   ps2_input_data[k][0] = 0;
		ps2_input_data[k][9] = 1;
		ps2_input_data[k][10] = 1;
		end
		

		ps2_input_data[0][8:1] = 8'h79;
		ps2_input_data[1][8:1] = 8'hF0;
		ps2_input_data[2][8:1] = 8'h79;
		

		ps2_input_data[3][8:1] = 8'h7A;
		ps2_input_data[4][8:1] = 8'hF0;
		ps2_input_data[5][8:1] = 8'h7A;
		

		ps2_input_data[6][8:1] = 8'h69;
		ps2_input_data[7][8:1] = 8'hF0;
		ps2_input_data[8][8:1] = 8'h69;
		
		

		ps2_input_data[9][8:1] = 8'h69;
		ps2_input_data[10][8:1] = 8'hF0;
		ps2_input_data[11][8:1] = 8'h69;
		

		ps2_input_data[12][8:1] = 8'h5A;
		ps2_input_data[13][8:1] = 8'hF0;
		ps2_input_data[14][8:1] = 8'h5A;
		

		ps2_input_data[15][8:1] = 8'h7C;
		ps2_input_data[16][8:1] = 8'hF0;
		ps2_input_data[17][8:1] = 8'h7C;
		

		ps2_input_data[18][8:1] = 8'h5A;
		ps2_input_data[19][8:1] = 8'hF0;
		ps2_input_data[20][8:1] = 8'h5A;
		

		ps2_input_data[21][8:1] = 8'h79;
		ps2_input_data[22][8:1] = 8'hF0;
		ps2_input_data[23][8:1] = 8'h79;
		

		ps2_input_data[24][8:1] = 8'h7A;
		ps2_input_data[25][8:1] = 8'hF0;
		ps2_input_data[26][8:1] = 8'h7A;
		


		ps2_input_data[27][8:1] = 8'h5A;
		ps2_input_data[28][8:1] = 8'hF0;
		ps2_input_data[29][8:1] = 8'h5A;		
		


      #(clk_period+1)
      rst = 1;
      #clk_period
      rst = 0;

		
      




      start_time = $time;
		
      while(1'b1) #clk_period;

      $display("Execution time in clock cycles: %0d",($time-start_time)/clk_period);




  





      #clk_period $finish;


   end

   
   always
     #(clk_period/2) clk = ~clk;
	  
	always
	  #(ps2_clk_period/2) ps2_clk = ~ps2_clk;
	  
	always @(posedge(ps2_clk))
		begin
		if (ps2_byte_index < 30)
			ps2_data = ps2_input_data[ps2_byte_index][ps2_bit_index];
		else ps2_data = 1;
		
		if (ps2_bit_index == 10) begin
			ps2_bit_index <= 0;
			ps2_byte_index <= ps2_byte_index + 1;
		end
		else ps2_bit_index <= ps2_bit_index + 1;
	end


   wire [`DATA_W-1:0] r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;

   assign r0 = uut.regf.reg_1[0];
   assign r1 = uut.regf.reg_1[1];
   assign r2 = uut.regf.reg_1[2];
   assign r3 = uut.regf.reg_1[3];
   assign r4 = uut.regf.reg_1[4];
   assign r5 = uut.regf.reg_1[5];
   assign r6 = uut.regf.reg_1[6];
   assign r7 = uut.regf.reg_1[7];
   assign r8 = uut.regf.reg_1[8];
   assign r9 = uut.regf.reg_1[9];
   assign r10 = uut.regf.reg_1[10];
   assign r11 = uut.regf.reg_1[11];
   assign r12 = uut.regf.reg_1[12];
   assign r13 = uut.regf.reg_1[13];
   assign r14 = uut.regf.reg_1[14];
   assign r15 = uut.regf.reg_1[15];  

endmodule
module xtop_tb;

   

   parameter clk_period = 20;
	parameter ps2_clk_period = 50000;




   reg clk;
   reg rst;



   reg ps2_data;
   reg ps2_clk;

   wire push_AC;
   wire push_C;

   wire[11:0]  disp_ctrl;
	
	wire [7:0]   gpo_out;
   


   integer 		   k, start_time;


   reg [`DATA_W-1:0] data [2**`REGF_ADDR_W-1:0];
	

	reg [10:0] ps2_input_data [29:0];
	reg [3:0] ps2_bit_index;
	reg [4:0] ps2_byte_index;
   

   xtop uut (
	      .clk(clk),
         .rst(rst),
	      

         
          .ps2_data(ps2_data),
          .ps2_clk(ps2_clk),
          .disp_ctrl(disp_ctrl)
    
	      );
   
   initial begin
      
`ifdef DEBUG
      $dumpfile("xtop.vcd");
      $dumpvars();
`endif
        

      clk = 1;
      rst = 0;
		ps2_clk = 1;
		ps2_data = 1;
		
		ps2_byte_index = 0;
		ps2_bit_index = 0;
		
		for (k = 0; k < 30; k=k+1) begin
	   ps2_input_data[k][0] = 0;
		ps2_input_data[k][9] = 1;
		ps2_input_data[k][10] = 1;
		end
		

		ps2_input_data[0][8:1] = 8'h79;
		ps2_input_data[1][8:1] = 8'hF0;
		ps2_input_data[2][8:1] = 8'h79;
		

		ps2_input_data[3][8:1] = 8'h7A;
		ps2_input_data[4][8:1] = 8'hF0;
		ps2_input_data[5][8:1] = 8'h7A;
		

		ps2_input_data[6][8:1] = 8'h69;
		ps2_input_data[7][8:1] = 8'hF0;
		ps2_input_data[8][8:1] = 8'h69;
		
		

		ps2_input_data[9][8:1] = 8'h69;
		ps2_input_data[10][8:1] = 8'hF0;
		ps2_input_data[11][8:1] = 8'h69;
		

		ps2_input_data[12][8:1] = 8'h5A;
		ps2_input_data[13][8:1] = 8'hF0;
		ps2_input_data[14][8:1] = 8'h5A;
		

		ps2_input_data[15][8:1] = 8'h7C;
		ps2_input_data[16][8:1] = 8'hF0;
		ps2_input_data[17][8:1] = 8'h7C;
		

		ps2_input_data[18][8:1] = 8'h5A;
		ps2_input_data[19][8:1] = 8'hF0;
		ps2_input_data[20][8:1] = 8'h5A;
		

		ps2_input_data[21][8:1] = 8'h79;
		ps2_input_data[22][8:1] = 8'hF0;
		ps2_input_data[23][8:1] = 8'h79;
		

		ps2_input_data[24][8:1] = 8'h7A;
		ps2_input_data[25][8:1] = 8'hF0;
		ps2_input_data[26][8:1] = 8'h7A;
		


		ps2_input_data[27][8:1] = 8'h5A;
		ps2_input_data[28][8:1] = 8'hF0;
		ps2_input_data[29][8:1] = 8'h5A;		
		


      #(clk_period+1)
      rst = 1;
      #clk_period
      rst = 0;

		
      




      start_time = $time;
		
      while(1'b1) #clk_period;

      $display("Execution time in clock cycles: %0d",($time-start_time)/clk_period);




  





      #clk_period $finish;


   end

   
   always
     #(clk_period/2) clk = ~clk;
	  
	always
	  #(ps2_clk_period/2) ps2_clk = ~ps2_clk;
	  
	always @(posedge(ps2_clk))
		begin
		if (ps2_byte_index < 30)
			ps2_data = ps2_input_data[ps2_byte_index][ps2_bit_index];
		else ps2_data = 1;
		
		if (ps2_bit_index == 10) begin
			ps2_bit_index <= 0;
			ps2_byte_index <= ps2_byte_index + 1;
		end
		else ps2_bit_index <= ps2_bit_index + 1;
	end


   wire [`DATA_W-1:0] r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;

   assign r0 = uut.regf.reg_1[0];
   assign r1 = uut.regf.reg_1[1];
   assign r2 = uut.regf.reg_1[2];
   assign r3 = uut.regf.reg_1[3];
   assign r4 = uut.regf.reg_1[4];
   assign r5 = uut.regf.reg_1[5];
   assign r6 = uut.regf.reg_1[6];
   assign r7 = uut.regf.reg_1[7];
   assign r8 = uut.regf.reg_1[8];
   assign r9 = uut.regf.reg_1[9];
   assign r10 = uut.regf.reg_1[10];
   assign r11 = uut.regf.reg_1[11];
   assign r12 = uut.regf.reg_1[12];
   assign r13 = uut.regf.reg_1[13];
   assign r14 = uut.regf.reg_1[14];
   assign r15 = uut.regf.reg_1[15];  

endmodule