data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/fifo_m.v
data/verilator_xmls/8d32a364-2b66-470c-ba8e-8b2140da7790.xml
module sync_fifo
   #(
      parameter DATA_WIDTH = 37,
      parameter LOG2_DEPTH = 5
   )
   (
      input [DATA_WIDTH-1:0]  din,
      input wr_en,
      input rd_en,
      output reg [DATA_WIDTH-1:0] dout,
      output full,
      output empty,
      input clk,
      input reset

   );

   parameter MAX_COUNT = 2**LOG2_DEPTH;
   reg   [LOG2_DEPTH-1 : 0]   rd_ptr;
   reg   [LOG2_DEPTH-1 : 0]   wr_ptr;
   reg   [DATA_WIDTH-1 : 0]   mem[MAX_COUNT-1 : 0];
   reg   [LOG2_DEPTH-1 : 0]     depth_cnt;
   

   always @(posedge clk) begin
      if(reset) begin
         wr_ptr <= 'h0;
         rd_ptr <= 'h0;
      end
      else begin
         if(wr_en)begin
            wr_ptr <= wr_ptr+1;
         end
         if(rd_en)
            rd_ptr <= rd_ptr+1;
      end
   end

   assign empty= (depth_cnt=='h0);
   assign full = (depth_cnt==MAX_COUNT-1);





   always @(posedge clk) begin
      if (wr_en)
         mem[wr_ptr] <= din;
   end


   always @(posedge clk) begin
      if (reset)
         dout <= 'h0;
      else if (rd_en)
         dout <= mem[rd_ptr];
   end

   always @(posedge clk) begin
      if (reset)
         depth_cnt <= 'h0;
      else begin
         case({rd_en,wr_en})
            2'b10    :  depth_cnt <= depth_cnt-1;
            2'b01    :  depth_cnt <= depth_cnt+1;
         endcase
      end
   end

endmodule
module sync_fifo
   #(
      parameter DATA_WIDTH = 37,
      parameter LOG2_DEPTH = 5
   )
   (
      input [DATA_WIDTH-1:0]  din,
      input wr_en,
      input rd_en,
      output reg [DATA_WIDTH-1:0] dout,
      output full,
      output empty,
      input clk,
      input reset

   );


   parameter MAX_COUNT = 2**LOG2_DEPTH;
   reg   [LOG2_DEPTH-1 : 0]   rd_ptr;
   reg   [LOG2_DEPTH-1 : 0]   wr_ptr;
   reg   [DATA_WIDTH-1 : 0]   mem[MAX_COUNT-1 : 0];
   reg   [LOG2_DEPTH-1 : 0]     depth_cnt;
   

   always @(posedge clk) begin
      if(reset) begin
         wr_ptr <= 'h0;
         rd_ptr <= 'h0;
      end
      else begin
         if(wr_en)begin
            wr_ptr <= wr_ptr+1;
         end
         if(rd_en)
            rd_ptr <= rd_ptr+1;
      end
   end

   assign empty= (depth_cnt=='h0);
   assign full = (depth_cnt==MAX_COUNT-1);





   always @(posedge clk) begin
      if (wr_en)
         mem[wr_ptr] <= din;
   end


   always @(posedge clk) begin
      if (reset)
         dout <= 'h0;
      else if (rd_en)
         dout <= mem[rd_ptr];
   end

   always @(posedge clk) begin
      if (reset)
         depth_cnt <= 'h0;
      else begin
         case({rd_en,wr_en})
            2'b10    :  depth_cnt <= depth_cnt-1;
            2'b01    :  depth_cnt <= depth_cnt+1;
         endcase
      end
   end

endmodule