data/full_repos/permissive/172582716/challenges/week1/verilog/challenge.v
data/verilator_xmls/b7db3bed-8a74-4f4f-b310-b4d92d254be3.xml
module challenge(input clk, input reset, input enable, output reg [3:0] count);
always @ (posedge clk)
begin
    if (reset == 1'b1)
    begin
        count <= 0;
    end
    else if (enable == 1'b1)
    begin
        count <= count + 1;
    end
end
endmodule
module challenge(input clk, input reset, input enable, output reg [3:0] count);

always @ (posedge clk)
begin
    if (reset == 1'b1)
    begin
        count <= 0;
    end
    else if (enable == 1'b1)
    begin
        count <= count + 1;
    end
end
endmodule