data/full_repos/permissive/143278/ivltests/pr1869781.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1869781.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #20 if (foo_bit[1] !== 1\'b0) begin\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dummy;

integer         i;
integer         foo_value;
reg     [1:0]   foo_bit;

initial
begin
        i = 1;
        foo_value = 10;
        foo_bit[i] <= #foo_value  1'b0;



        #20 if (foo_bit[1] !== 1'b0) begin
	   $display("FAILED -- foo_bit[1] = %b", foo_bit[1]);
	   $finish;
	end
        $display("PASSED");
end

endmodule
module dummy;


integer         i;
integer         foo_value;
reg     [1:0]   foo_bit;

initial
begin
        i = 1;
        foo_value = 10;
        foo_bit[i] <= #foo_value  1'b0;



        #20 if (foo_bit[1] !== 1'b0) begin
	   $display("FAILED -- foo_bit[1] = %b", foo_bit[1]);
	   $finish;
	end
        $display("PASSED");
end

endmodule