data/full_repos/permissive/202237519/verilog/digitalsystem5/CTLtb.v
 line:172: before: ";"
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem5/CTLtb.v:1: Cannot find include file: CTL.v\n`include "CTL.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem5,data/full_repos/permissive/202237519/CTL.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem5,data/full_repos/permissive/202237519/CTL.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem5,data/full_repos/permissive/202237519/CTL.v.sv\n             CTL.v\n             CTL.v.v\n             CTL.v.sv\n             obj_dir/CTL.v\n             obj_dir/CTL.v.v\n             obj_dir/CTL.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem5/CTLtb.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem5/CTLtb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    N_Reset <= 1\'b1; #10;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem5/CTLtb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    N_Reset <= 1\'b0; #10;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem5/CTLtb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    I3<= 1\'b1; I2<= 1\'b0; I1<= 1\'b0; I0<=1\'b0; #100;\n                                               ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module CTLtb;

reg clk; 
reg I3,I2,I1,I0,N_Reset;
wire [7:0] SEG_COM, SEG_DATA;

always #5 clk = ~clk;

Control CTL(clk, I3, I2, I1, I0, N_Reset, SEG_COM, SEG_DATA);

always@(posedge clk) begin
    N_Reset <= 1'b1; #10;
    N_Reset <= 1'b0; #10;
    I3<= 1'b1; I2<= 1'b0; I1<= 1'b0; I0<=1'b0; #100;




end
endmodule
module CTLtb;


reg clk; 
reg I3,I2,I1,I0,N_Reset;
wire [7:0] SEG_COM, SEG_DATA;

always #5 clk = ~clk;

Control CTL(clk, I3, I2, I1, I0, N_Reset, SEG_COM, SEG_DATA);

always@(posedge clk) begin
    N_Reset <= 1'b1; #10;
    N_Reset <= 1'b0; #10;
    I3<= 1'b1; I2<= 1'b0; I1<= 1'b0; I0<=1'b0; #100;




end
endmodule