data/full_repos/permissive/21438680/DAQ_Firmware/src/ok/okLibrary.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/21438680/DAQ_Firmware/src/ok/okLibrary.v:94: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'okHost\'\nmodule okHost(\n       ^~~~~~\n                                                                                         : ... Top module \'okWireOR\'\nmodule okWireOR # (parameter N = 1) (\n       ^~~~~~~~\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ok/okLibrary.v:35: Cannot find file containing module: \'ok_altpll\'\n ok_altpll ok_altpll0 (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21438680/DAQ_Firmware/src/ok,data/full_repos/permissive/21438680/ok_altpll\n             data/full_repos/permissive/21438680/DAQ_Firmware/src/ok,data/full_repos/permissive/21438680/ok_altpll.v\n             data/full_repos/permissive/21438680/DAQ_Firmware/src/ok,data/full_repos/permissive/21438680/ok_altpll.sv\n             ok_altpll\n             ok_altpll.v\n             ok_altpll.sv\n             obj_dir/ok_altpll\n             obj_dir/ok_altpll.v\n             obj_dir/ok_altpll.sv\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ok/okLibrary.v:90: Cannot find file containing module: \'okCoreHarness\'\n okCoreHarness core0(.okHC(okHC), .okCH(okCH), .okHE(okHE), .okEH(okEH));\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module okHost(
	input  wire [4:0]   okUH,
	output reg  [2:0]   okHU,
	inout  wire [31:0]  okUHU,
	inout  wire         okAA,
	output wire         okClk,
	output wire [112:0] okHE,
	input  wire [64:0]  okEH
);
	
	wire [38:0] okHC;
	wire [37:0] okCH;
	
	wire       pll_locked;
	
	
	assign okHC[38]   = ~pll_locked;
	assign okHC[37]   = okAA;
	assign okHC[36:5] = data_in;
	assign okHC[4:1]  = ctrl_in;
	assign okClk      =  okHC[0];
	
	

	ok_altpll ok_altpll0 (
		.inclk0 ( okUH[0] ),
		.c0 ( okHC[0] ),
		.locked ( pll_locked )
		);
	



	reg        data_valid;
	reg [31:0] data_out;
	reg [31:0] data_in;
	reg [4:1]  ctrl_in;
	

	assign okUHU = (data_valid) ? 32'bZ : data_out;
	

	always @ (posedge okHC[0]) begin
		data_in <= okUHU;
	end
	

	always @ (posedge okHC[0]) begin
		data_out <= okCH[34:3];
	end
	

	always @ (posedge okHC[0]) begin
		data_valid <= ~okCH[36];
	end
	
	assign okAA = (okCH[37]) ? 1'bZ : okCH[35];
	
	



	always @ (posedge okHC[0]) begin
		okHU[2] <= okCH[2];
		okHU[0] <= okCH[0];
		okHU[1] <= okCH[1];
	end
	
	





	always @ (posedge okHC[0]) begin
		ctrl_in[1]   <= okUH[1];
		ctrl_in[4:2] <= okUH[4:2];
	end
	
	okCoreHarness core0(.okHC(okHC), .okCH(okCH), .okHE(okHE), .okEH(okEH));
	
endmodule
module okHost(
	input  wire [4:0]   okUH,
	output reg  [2:0]   okHU,
	inout  wire [31:0]  okUHU,
	inout  wire         okAA,
	output wire         okClk,
	output wire [112:0] okHE,
	input  wire [64:0]  okEH
);

	
	wire [38:0] okHC;
	wire [37:0] okCH;
	
	wire       pll_locked;
	
	
	assign okHC[38]   = ~pll_locked;
	assign okHC[37]   = okAA;
	assign okHC[36:5] = data_in;
	assign okHC[4:1]  = ctrl_in;
	assign okClk      =  okHC[0];
	
	

	ok_altpll ok_altpll0 (
		.inclk0 ( okUH[0] ),
		.c0 ( okHC[0] ),
		.locked ( pll_locked )
		);
	



	reg        data_valid;
	reg [31:0] data_out;
	reg [31:0] data_in;
	reg [4:1]  ctrl_in;
	

	assign okUHU = (data_valid) ? 32'bZ : data_out;
	

	always @ (posedge okHC[0]) begin
		data_in <= okUHU;
	end
	

	always @ (posedge okHC[0]) begin
		data_out <= okCH[34:3];
	end
	

	always @ (posedge okHC[0]) begin
		data_valid <= ~okCH[36];
	end
	
	assign okAA = (okCH[37]) ? 1'bZ : okCH[35];
	
	



	always @ (posedge okHC[0]) begin
		okHU[2] <= okCH[2];
		okHU[0] <= okCH[0];
		okHU[1] <= okCH[1];
	end
	
	





	always @ (posedge okHC[0]) begin
		ctrl_in[1]   <= okUH[1];
		ctrl_in[4:2] <= okUH[4:2];
	end
	
	okCoreHarness core0(.okHC(okHC), .okCH(okCH), .okHE(okHE), .okEH(okEH));
	
endmodule