data/full_repos/permissive/157101210/adder.v
data/verilator_xmls/e7c95d2e-5b90-4fdb-b3e3-16c92e499139.xml
module FullAdder1
(
    output res, 
    output carryout,
    input a, 
    input b,
    input carryin
);
    wire xAorB;
    wire AandB;
    wire xAorBandCin;
    xor  xorgate(xAorB, a, b);
    xor  xorgate(res, xAorB, carryin);
    and  andgate(AandB, a, b);
    and  andgate(xAorBandCin, xAorB, carryin);
    or   orgate(carryout, AandB, xAorBandCin);
endmodule
module FullAdder1
(
    output res, 
    output carryout,
    input a, 
    input b,
    input carryin
);

    wire xAorB;
    wire AandB;
    wire xAorBandCin;
    xor  xorgate(xAorB, a, b);
    xor  xorgate(res, xAorB, carryin);
    and  andgate(AandB, a, b);
    and  andgate(xAorBandCin, xAorB, carryin);
    or   orgate(carryout, AandB, xAorBandCin);
endmodule