data/full_repos/permissive/1835228/TSPCtop.v
1: b"%Error: data/full_repos/permissive/1835228/TSPCtop.v:98: Cannot find file containing module: 'IBUFGDS'\nIBUFGDS ClkBuf ( .O  ( clockIn ),\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/1835228,data/full_repos/permissive/1835228/IBUFGDS\n             data/full_repos/permissive/1835228,data/full_repos/permissive/1835228/IBUFGDS.v\n             data/full_repos/permissive/1835228,data/full_repos/permissive/1835228/IBUFGDS.sv\n             IBUFGDS\n             IBUFGDS.v\n             IBUFGDS.sv\n             obj_dir/IBUFGDS\n             obj_dir/IBUFGDS.v\n             obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/1835228/TSPCtop.v:104: Cannot find file containing module: 'etherCtrl'\netherCtrl ethcon( .clk(clock),\n^~~~~~~~~\n%Error: data/full_repos/permissive/1835228/TSPCtop.v:164: Cannot find file containing module: 'hashGen'\nhashGen u_hash( .clk           ( clock          ),\n^~~~~~~\n%Error: data/full_repos/permissive/1835228/TSPCtop.v:180: Cannot find file containing module: 'treeCacheCtrl'\ntreeCacheCtrl tcc( .clk           ( clock          ),\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/1835228/TSPCtop.v:213: Cannot find file containing module: 'PLL_BASE'\nPLL_BASE #(\n^~~~~~~~\n%Error: data/full_repos/permissive/1835228/TSPCtop.v:242: Cannot find file containing module: 'BUFG'\nBUFG bufC   (.O(clock),      .I(clockx)     );\n^~~~\n%Error: data/full_repos/permissive/1835228/TSPCtop.v:243: Cannot find file containing module: 'BUFG'\nBUFG bufM   (.O(MCLK),       .I(MCLKx)      );\n^~~~\n%Error: data/full_repos/permissive/1835228/TSPCtop.v:244: Cannot find file containing module: 'BUFG'\nBUFG CKbuf  (.O(ethTXclock), .I(ethTXclockx));\n^~~~\n%Error: data/full_repos/permissive/1835228/TSPCtop.v:248: Cannot find file containing module: 'IDELAYCTRL'\nIDELAYCTRL idelayctrl0 ( .RDY(ctrlLock),\n^~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module TSPCtop( CLKBN,
                CLKBP,
                FPGAreset,

                GMII_TXD_0,
                GMII_TX_EN_0,
                GMII_TX_ER_0,
                GMII_TX_CLK_0,
                GMII_RXD_0,
                GMII_RX_DV_0,
                GMII_RX_CLK_0,
                GMII_RESET_B,
                LED,
                LED_ERR
              );

  input         CLKBN;
  input         CLKBP;
  input         FPGAreset;
  output [7:0]  LED;
  output [1:0]  LED_ERR;
  

  output [7:0]  GMII_TXD_0;
  output        GMII_TX_EN_0;
  output        GMII_TX_ER_0;
  output        GMII_TX_CLK_0;
  input  [7:0]  GMII_RXD_0;
  input         GMII_RX_DV_0;
  input         GMII_RX_CLK_0;
  output        GMII_RESET_B; 
  

  wire clockIn;
  wire MCLK; 
  wire MCLKx;
  wire clock;
  wire clockx;
  wire ethTXclock;
  wire ethTXclockx;
  wire PLLBfb;
  wire pllLock;
  wire ctrlLock;
  wire reset;


  wire          isFailed;

  assign reset   = ~FPGAreset  | ~pllLock | ~ctrlLock;
  assign LED     = { 6'd0, !isFailed, !isFailed };
  assign LED_ERR = { isFailed, isFailed };


  wire          firstFrame;
  wire          lastFrame;
  

  wire   [7:0]  txFifoIn;  
  wire          txWrEn;    
  wire          txFifoFull;
  

  wire   [7:0]  tcFifoIn;  
  wire          tcWrEn;    
  wire          tcFifoFull;
  

  reg   [11:0]  tfFifoIn_w,    tfFifoIn_r;
  reg           tfWrEn_w,      tfWrEn_r;
  reg           is_both_out_w, is_both_out_r;
  wire          tfFifoFull; 
  wire          txStart_db;
  wire          txStart_tc;
  wire  [10:0]  txByteTotal_db;
  wire  [10:0]  txByteTotal_tc;


  wire  [31:0]  dataFifoOut;
  wire          dataFifoEmpty;
  wire          dataFifoValid;
  wire          dataRdEn;  
  

  wire  [31:0]  instFifoOut;
  wire          instFifoEmpty;
  wire          instFifoValid;
  wire          instRdEn;  


  wire  [ 7:0]  itpFifoOut;
  wire          itpFifoEmpty;
  wire          itpRdEn;  
  

(* DIFF_TERM = "TRUE" *) 
IBUFGDS ClkBuf ( .O  ( clockIn ),
                 .I  ( CLKBP   ),
                 .IB ( CLKBN   )
               );


etherCtrl ethcon( .clk(clock),
                  .reset(reset),
                  .ethTXclock(ethTXclock),

                  .GMII_TXD_0(GMII_TXD_0),
                  .GMII_TX_EN_0(GMII_TX_EN_0),
                  .GMII_TX_ER_0(GMII_TX_ER_0),
                  .GMII_TX_CLK_0(GMII_TX_CLK_0),
                  .GMII_RXD_0(GMII_RXD_0),
                  .GMII_RX_DV_0(GMII_RX_DV_0),
                  .GMII_RX_CLK_0(GMII_RX_CLK_0),
                  .GMII_RESET_B(GMII_RESET_B),
                  .txFifoIn(txFifoIn),
                  .txWrEn(txWrEn),
                  .txFifoFull(txFifoFull),
                  .tcFifoIn(tcFifoIn),
                  .tcWrEn(tcWrEn),
                  .tcFifoFull(tcFifoFull),
                  .tfFifoIn(tfFifoIn_r),
                  .tfWrEn(tfWrEn_r),
                  .tfFifoFull(tfFifoFull),
                  .dataFifoOut(dataFifoOut),
                  .dataFifoEmpty(dataFifoEmpty),
                  .dataFifoValid(dataFifoValid),
                  .dataRdEn(dataRdEn),
                  .instFifoOut(instFifoOut),
                  .instFifoEmpty(instFifoEmpty),
                  .instFifoValid(instFifoValid),
                  .instRdEn(instRdEn),
                  .itpFifoOut(itpFifoOut),
                  .itpFifoEmpty(itpFifoEmpty),
                  .itpRdEn(itpRdEn),
                  .firstFrame(firstFrame),
                  .lastFrame(lastFrame)
                );



always @ (*)
 begin
   tfFifoIn_w    = tfFifoIn_r;
   tfWrEn_w      = 1'b0;
   is_both_out_w = 1'b0;
   if( txStart_db )
    begin
      tfWrEn_w    = 1'b1;
      tfFifoIn_w  = { 1'b1, txByteTotal_db };
      if( txStart_tc )
       begin
         is_both_out_w = 1'b1;
       end
    end
   else if( txStart_tc | is_both_out_r )
    begin
      tfWrEn_w    = 1'b1;
      tfFifoIn_w  = { 1'b0, txByteTotal_tc };
    end
 end


hashGen u_hash( .clk           ( clock          ),
                .reset         ( reset          ),
                .firstFrame    ( firstFrame     ),
                .lastFrame     ( lastFrame      ),
                .dataIn        ( dataFifoOut    ),
                .dataFifoEmpty ( dataFifoEmpty  ),
                .dataFifoValid ( dataFifoValid  ), 
                .dataRdEn      ( dataRdEn       ),
                .hashValueOut  ( txFifoIn       ),
                .hashWrEn      ( txWrEn         ),
                .hashFifoFull  ( txFifoFull     ),
                .txStart       ( txStart_db     ),
                .txByteTotal   ( txByteTotal_db )
              );


treeCacheCtrl tcc( .clk           ( clock          ),
                   .reset         ( reset          ),
                   .instIn        ( instFifoOut    ),
                   .instFifoEmpty ( instFifoEmpty  ),
                   .instFifoValid ( instFifoValid  ),
                   .instRdEn      ( instRdEn       ),
                   .itpIn         ( itpFifoOut     ),
                   .itpFifoEmpty  ( itpFifoEmpty   ),
                   .itpRdEn       ( itpRdEn        ),
                   .hashValueOut  ( tcFifoIn       ),
                   .hashWrEn      ( tcWrEn         ),
                   .txStart       ( txStart_tc     ),
                   .txByteTotal   ( txByteTotal_tc ),
                   .clear         ( isFailed       )
                 );

always @( posedge clock or posedge reset )
 begin
   if( reset)
    begin
      tfFifoIn_r    <= 12'd0;
      tfWrEn_r      <= 1'b0;
      is_both_out_r <= 1'b0;
    end
   else
    begin
      tfFifoIn_r    <= tfFifoIn_w;
      tfWrEn_r      <= tfWrEn_w;
      is_both_out_r <= is_both_out_w;
    end
 end
 

PLL_BASE #(
            .BANDWIDTH("OPTIMIZED"),
            .CLKFBOUT_MULT(20),
            .CLKFBOUT_PHASE(0.0), 
            .CLKIN_PERIOD(5.0), 
            .CLKOUT0_DIVIDE(5),
            .CLKOUT0_DUTY_CYCLE(0.5),
            .CLKOUT0_PHASE(0.0),
            .CLKOUT1_DIVIDE(10),
            .CLKOUT1_DUTY_CYCLE(0.5), 
            .CLKOUT1_PHASE(0.0), 
            .CLKOUT2_DIVIDE(8),
            .CLKOUT2_DUTY_CYCLE(0.5),
            .CLKOUT2_PHASE(0.0),
            .COMPENSATION("SYSTEM_SYNCHRONOUS"),
            .DIVCLK_DIVIDE(4),
            .REF_JITTER(0.100)
          ) 
clkBPLL (
          .CLKFBOUT(PLLBfb),
          .CLKOUT0(MCLKx), 
          .CLKOUT1(clockx),
          .CLKOUT2(ethTXclockx),     
          .LOCKED (pllLock),
          .CLKFBIN(PLLBfb),
          .CLKIN(clockIn),
          .RST(1'b0)
        );

BUFG bufC   (.O(clock),      .I(clockx)     );
BUFG bufM   (.O(MCLK),       .I(MCLKx)      );
BUFG CKbuf  (.O(ethTXclock), .I(ethTXclockx));



IDELAYCTRL idelayctrl0 ( .RDY(ctrlLock),
                         .REFCLK(MCLK), 
                         .RST(~pllLock)
                       );

endmodule
module TSPCtop( CLKBN,
                CLKBP,
                FPGAreset,

                GMII_TXD_0,
                GMII_TX_EN_0,
                GMII_TX_ER_0,
                GMII_TX_CLK_0,
                GMII_RXD_0,
                GMII_RX_DV_0,
                GMII_RX_CLK_0,
                GMII_RESET_B,
                LED,
                LED_ERR
              );


  input         CLKBN;
  input         CLKBP;
  input         FPGAreset;
  output [7:0]  LED;
  output [1:0]  LED_ERR;
  

  output [7:0]  GMII_TXD_0;
  output        GMII_TX_EN_0;
  output        GMII_TX_ER_0;
  output        GMII_TX_CLK_0;
  input  [7:0]  GMII_RXD_0;
  input         GMII_RX_DV_0;
  input         GMII_RX_CLK_0;
  output        GMII_RESET_B; 
  

  wire clockIn;
  wire MCLK; 
  wire MCLKx;
  wire clock;
  wire clockx;
  wire ethTXclock;
  wire ethTXclockx;
  wire PLLBfb;
  wire pllLock;
  wire ctrlLock;
  wire reset;


  wire          isFailed;

  assign reset   = ~FPGAreset  | ~pllLock | ~ctrlLock;
  assign LED     = { 6'd0, !isFailed, !isFailed };
  assign LED_ERR = { isFailed, isFailed };


  wire          firstFrame;
  wire          lastFrame;
  

  wire   [7:0]  txFifoIn;  
  wire          txWrEn;    
  wire          txFifoFull;
  

  wire   [7:0]  tcFifoIn;  
  wire          tcWrEn;    
  wire          tcFifoFull;
  

  reg   [11:0]  tfFifoIn_w,    tfFifoIn_r;
  reg           tfWrEn_w,      tfWrEn_r;
  reg           is_both_out_w, is_both_out_r;
  wire          tfFifoFull; 
  wire          txStart_db;
  wire          txStart_tc;
  wire  [10:0]  txByteTotal_db;
  wire  [10:0]  txByteTotal_tc;


  wire  [31:0]  dataFifoOut;
  wire          dataFifoEmpty;
  wire          dataFifoValid;
  wire          dataRdEn;  
  

  wire  [31:0]  instFifoOut;
  wire          instFifoEmpty;
  wire          instFifoValid;
  wire          instRdEn;  


  wire  [ 7:0]  itpFifoOut;
  wire          itpFifoEmpty;
  wire          itpRdEn;  
  

(* DIFF_TERM = "TRUE" *) 
IBUFGDS ClkBuf ( .O  ( clockIn ),
                 .I  ( CLKBP   ),
                 .IB ( CLKBN   )
               );


etherCtrl ethcon( .clk(clock),
                  .reset(reset),
                  .ethTXclock(ethTXclock),

                  .GMII_TXD_0(GMII_TXD_0),
                  .GMII_TX_EN_0(GMII_TX_EN_0),
                  .GMII_TX_ER_0(GMII_TX_ER_0),
                  .GMII_TX_CLK_0(GMII_TX_CLK_0),
                  .GMII_RXD_0(GMII_RXD_0),
                  .GMII_RX_DV_0(GMII_RX_DV_0),
                  .GMII_RX_CLK_0(GMII_RX_CLK_0),
                  .GMII_RESET_B(GMII_RESET_B),
                  .txFifoIn(txFifoIn),
                  .txWrEn(txWrEn),
                  .txFifoFull(txFifoFull),
                  .tcFifoIn(tcFifoIn),
                  .tcWrEn(tcWrEn),
                  .tcFifoFull(tcFifoFull),
                  .tfFifoIn(tfFifoIn_r),
                  .tfWrEn(tfWrEn_r),
                  .tfFifoFull(tfFifoFull),
                  .dataFifoOut(dataFifoOut),
                  .dataFifoEmpty(dataFifoEmpty),
                  .dataFifoValid(dataFifoValid),
                  .dataRdEn(dataRdEn),
                  .instFifoOut(instFifoOut),
                  .instFifoEmpty(instFifoEmpty),
                  .instFifoValid(instFifoValid),
                  .instRdEn(instRdEn),
                  .itpFifoOut(itpFifoOut),
                  .itpFifoEmpty(itpFifoEmpty),
                  .itpRdEn(itpRdEn),
                  .firstFrame(firstFrame),
                  .lastFrame(lastFrame)
                );



always @ (*)
 begin
   tfFifoIn_w    = tfFifoIn_r;
   tfWrEn_w      = 1'b0;
   is_both_out_w = 1'b0;
   if( txStart_db )
    begin
      tfWrEn_w    = 1'b1;
      tfFifoIn_w  = { 1'b1, txByteTotal_db };
      if( txStart_tc )
       begin
         is_both_out_w = 1'b1;
       end
    end
   else if( txStart_tc | is_both_out_r )
    begin
      tfWrEn_w    = 1'b1;
      tfFifoIn_w  = { 1'b0, txByteTotal_tc };
    end
 end


hashGen u_hash( .clk           ( clock          ),
                .reset         ( reset          ),
                .firstFrame    ( firstFrame     ),
                .lastFrame     ( lastFrame      ),
                .dataIn        ( dataFifoOut    ),
                .dataFifoEmpty ( dataFifoEmpty  ),
                .dataFifoValid ( dataFifoValid  ), 
                .dataRdEn      ( dataRdEn       ),
                .hashValueOut  ( txFifoIn       ),
                .hashWrEn      ( txWrEn         ),
                .hashFifoFull  ( txFifoFull     ),
                .txStart       ( txStart_db     ),
                .txByteTotal   ( txByteTotal_db )
              );


treeCacheCtrl tcc( .clk           ( clock          ),
                   .reset         ( reset          ),
                   .instIn        ( instFifoOut    ),
                   .instFifoEmpty ( instFifoEmpty  ),
                   .instFifoValid ( instFifoValid  ),
                   .instRdEn      ( instRdEn       ),
                   .itpIn         ( itpFifoOut     ),
                   .itpFifoEmpty  ( itpFifoEmpty   ),
                   .itpRdEn       ( itpRdEn        ),
                   .hashValueOut  ( tcFifoIn       ),
                   .hashWrEn      ( tcWrEn         ),
                   .txStart       ( txStart_tc     ),
                   .txByteTotal   ( txByteTotal_tc ),
                   .clear         ( isFailed       )
                 );

always @( posedge clock or posedge reset )
 begin
   if( reset)
    begin
      tfFifoIn_r    <= 12'd0;
      tfWrEn_r      <= 1'b0;
      is_both_out_r <= 1'b0;
    end
   else
    begin
      tfFifoIn_r    <= tfFifoIn_w;
      tfWrEn_r      <= tfWrEn_w;
      is_both_out_r <= is_both_out_w;
    end
 end
 

PLL_BASE #(
            .BANDWIDTH("OPTIMIZED"),
            .CLKFBOUT_MULT(20),
            .CLKFBOUT_PHASE(0.0), 
            .CLKIN_PERIOD(5.0), 
            .CLKOUT0_DIVIDE(5),
            .CLKOUT0_DUTY_CYCLE(0.5),
            .CLKOUT0_PHASE(0.0),
            .CLKOUT1_DIVIDE(10),
            .CLKOUT1_DUTY_CYCLE(0.5), 
            .CLKOUT1_PHASE(0.0), 
            .CLKOUT2_DIVIDE(8),
            .CLKOUT2_DUTY_CYCLE(0.5),
            .CLKOUT2_PHASE(0.0),
            .COMPENSATION("SYSTEM_SYNCHRONOUS"),
            .DIVCLK_DIVIDE(4),
            .REF_JITTER(0.100)
          ) 
clkBPLL (
          .CLKFBOUT(PLLBfb),
          .CLKOUT0(MCLKx), 
          .CLKOUT1(clockx),
          .CLKOUT2(ethTXclockx),     
          .LOCKED (pllLock),
          .CLKFBIN(PLLBfb),
          .CLKIN(clockIn),
          .RST(1'b0)
        );

BUFG bufC   (.O(clock),      .I(clockx)     );
BUFG bufM   (.O(MCLK),       .I(MCLKx)      );
BUFG CKbuf  (.O(ethTXclock), .I(ethTXclockx));



IDELAYCTRL idelayctrl0 ( .RDY(ctrlLock),
                         .REFCLK(MCLK), 
                         .RST(~pllLock)
                       );

endmodule