data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv
 line:40 column:21: Illegal character '"'
1: b'%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:41: Unterminated string\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:42: Unterminated string\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:18: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:18: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:40: syntax error, unexpected \'%\', expecting \')\'\n          $display(          S %h (%h expected)          errors = errors + 1;\n                                   ^\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:63: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_1, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:64: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_1, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:65: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_1, coutb, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:66: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(gnd, net_11, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:67: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, coutb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:68: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, net_23, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:69: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_23, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:70: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_7(gnd, net_23, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:71: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_8(net_23, sb, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:72: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_9(gnd, net_33, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:73: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_10(net_33, net_32, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:74: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_11(net_32, sb, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:75: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_12(gnd, cout, coutb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:76: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_13(gnd, s, sb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:77: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(sb, net_92, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:78: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(net_92, net_90, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:79: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_90, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:80: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(sb, net_94, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:81: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(net_94, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:82: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_6(net_94, vdd, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:83: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_7(net_94, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:84: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_8(cout, vdd, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:85: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_9(net_95, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:86: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_10(coutb, net_95, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:87: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_11(net_111, vdd, a);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:88: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_12(net_111, vdd, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:89: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_13(coutb, net_111, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:90: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_14(s, vdd, sb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:99: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, y, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:100: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:112: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_5, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:113: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_5, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:114: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:115: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:127: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_0, net_1, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:128: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_0, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:129: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, Y, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:130: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(net_11, Y, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:131: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_11, net_1);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:132: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_1, vdd, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:133: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_1, vdd, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:134: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(Y, vdd, net_1);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:135: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_28, vdd, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTC.sv:136: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(Y, net_28, A);\n          ^~~~~~\n%Error: Exiting due to 47 error(s), 2 warning(s)\n'
module muddlib07__inv_1x(a, y);
  input a;
  output y;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(gnd, y, a);
  tranif0 pmos_0(y, vdd, a);
endmodule
module muddlib07__inv_1x(a, y);

  input a;
  output y;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(gnd, y, a);
  tranif0 pmos_0(y, vdd, a);
endmodule