data/full_repos/permissive/126791278/MUXpreALU.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/126791278/MUXpreALU.v:66: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                      : ... Top module \'MUXpreALU\'\nmodule MUXpreALU( ALU_1_IN, ALU_2_IN,\n       ^~~~~~~~~\n                                                                      : ... Top module \'sign_extend_12bto16b\'\nmodule sign_extend_12bto16b(JUMP_SE_Out, instr11to0);\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                      : ... Top module \'sign_extend_8bto16b\'\nmodule sign_extend_8bto16b(SE_Out, instr7to0);\n       ^~~~~~~~~~~~~~~~~~~\n                                                                      : ... Top module \'unsign_extend_8bto16b\'\nmodule unsign_extend_8bto16b(USE_Out, instr7to0);\n       ^~~~~~~~~~~~~~~~~~~~~\n                                                                      : ... Top module \'left_1b_shift\'\nmodule left_1b_shift(L1S_Out, SE_Out);\n       ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/126791278/MUXpreALU.v:55: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                   : ... In instance MUXpreALU\n 3\'b001  :  ALU_2_IN <= 2\'b01;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/126791278/MUXpreALU.v:59: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                   : ... In instance MUXpreALU\n 3\'b101  :  ALU_2_IN <= D_JUMP_SE_Out[7:4];\n                     ^~\n%Error: Exiting due to 3 warning(s)\n'
module left_1b_shift(L1S_Out, SE_Out);
output wire [15:0] L1S_Out;
input wire [15:0] SE_Out;
assign L1S_Out = SE_Out << 1'b1;
endmodule
module left_1b_shift(L1S_Out, SE_Out);

output wire [15:0] L1S_Out;
input wire [15:0] SE_Out;
assign L1S_Out = SE_Out << 1'b1;
endmodule