data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:2: Cannot find include file: helpers.vh\n`include "helpers.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/180413071/nonpipelined/sources/tests,data/full_repos/permissive/180413071/helpers.vh\n             data/full_repos/permissive/180413071/nonpipelined/sources/tests,data/full_repos/permissive/180413071/helpers.vh.v\n             data/full_repos/permissive/180413071/nonpipelined/sources/tests,data/full_repos/permissive/180413071/helpers.vh.sv\n             helpers.vh\n             helpers.vh.v\n             helpers.vh.sv\n             obj_dir/helpers.vh\n             obj_dir/helpers.vh.v\n             obj_dir/helpers.vh.sv\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:3: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:7: Define or directive not defined: \'`INSTR_LEN\'\n    reg  [`INSTR_LEN-1:0] instruction;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:15: Define or directive not defined: \'`TB_BEGIN\'\n        `TB_BEGIN\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:18: Define or directive not defined: \'`INSTR_LEN\'\n        instruction = `INSTR_LEN\'b11111000010011110000000101001001;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:19: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:19: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:22: Define or directive not defined: \'`INSTR_LEN\'\n        instruction = `INSTR_LEN\'b10001011000010010000001010101010;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:23: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:23: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:26: Define or directive not defined: \'`INSTR_LEN\'\n        instruction = `INSTR_LEN\'b11111000000011110000000101001001;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:27: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:27: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/instr_parse_tb.sv:29: Define or directive not defined: \'`TB_END\'\n        `TB_END\n        ^~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module instr_parse_tb;

    reg  [`INSTR_LEN-1:0] instruction;
    wire [4:0] rm, rn, rd;
    wire [8:0] address;
    wire [10:0] opcode;
    
    instr_parse UUT(.*);
    
    initial begin
        `TB_BEGIN
        

        instruction = `INSTR_LEN'b11111000010011110000000101001001;
        #`CYCLE;
        

        instruction = `INSTR_LEN'b10001011000010010000001010101010;
        #`CYCLE;
        

        instruction = `INSTR_LEN'b11111000000011110000000101001001;
        #`CYCLE;
        
        `TB_END
    end

endmodule
module instr_parse_tb;


    reg  [`INSTR_LEN-1:0] instruction;
    wire [4:0] rm, rn, rd;
    wire [8:0] address;
    wire [10:0] opcode;
    
    instr_parse UUT(.*);
    
    initial begin
        `TB_BEGIN
        

        instruction = `INSTR_LEN'b11111000010011110000000101001001;
        #`CYCLE;
        

        instruction = `INSTR_LEN'b10001011000010010000001010101010;
        #`CYCLE;
        

        instruction = `INSTR_LEN'b11111000000011110000000101001001;
        #`CYCLE;
        
        `TB_END
    end

endmodule