data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:12: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'BUF\'\nmodule BUF(A, Y);\n       ^~~\n                                                                                         : ... Top module \'NOT\'\nmodule NOT(A, Y);\n       ^~~\n                                                                                         : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n       ^~~~\n                                                                                         : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n       ^~~\n                                                                                         : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n       ^~~\n                                                                                         : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R);\n       ^~~~~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:38: Can\'t find definition of scope/variable: \'letest\'\n  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;\n                            ^~~~~~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:38: Can\'t find definition of scope/variable: \'m1\'\n  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;\n                                   ^~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:38: Can\'t find definition of scope/variable: \'letest\'\n  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;\n  ^~~~~~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:38: Can\'t find definition of scope/variable: \'m1\'\n  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;\n         ^~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:28: Can\'t find definition of scope/variable: \'letest\'\n  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;\n                            ^~~~~~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:28: Can\'t find definition of scope/variable: \'m1\'\n  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;\n                                   ^~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:28: Can\'t find definition of scope/variable: \'letest\'\n  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;\n  ^~~~~~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:28: Can\'t find definition of scope/variable: \'m1\'\n  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;\n         ^~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:18: Can\'t find definition of scope/variable: \'letest\'\n  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;\n                            ^~~~~~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:18: Can\'t find definition of scope/variable: \'m1\'\n  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;\n                                   ^~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:18: Can\'t find definition of scope/variable: \'letest\'\n  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;\n  ^~~~~~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/cmos_cells.v:18: Can\'t find definition of scope/variable: \'m1\'\n  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;\n         ^~\n%Error: Exiting due to 12 error(s), 1 warning(s)\n'
module NAND(A, B, Y);
input A, B;
output Y;
assign Y = ~(A & B);
parameter PwrC = 3;
always @(posedge Y or negedge Y) begin
  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;
end
endmodule
module NAND(A, B, Y);

input A, B;
output Y;
assign Y = ~(A & B);
parameter PwrC = 3;
always @(posedge Y or negedge Y) begin
  letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;
end
endmodule