data/full_repos/permissive/135852214/Verilog/RFA.v
 line:1 column:1: Illegal character '\x00'
1: b"%Error: data/full_repos/permissive/135852214/Verilog/RFA.v:27: Cannot find file containing module: 'mexor'\nmexor g0({in[6],in[5],in[4],in[1],in[0]},{w0[6],w0[5],w0[4],w0[1],w0[0]});\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/mexor\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/mexor.v\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/mexor.sv\n             mexor\n             mexor.v\n             mexor.sv\n             obj_dir/mexor\n             obj_dir/mexor.v\n             obj_dir/mexor.sv\n%Error: data/full_repos/permissive/135852214/Verilog/RFA.v:30: Cannot find file containing module: 'tcnot'\ntcnot g1({w0[5],w0[3],w0[1],w0[0]},{w1[5],w1[3],w1[1],w1[0]});\n^~~~~\n%Error: data/full_repos/permissive/135852214/Verilog/RFA.v:33: Cannot find file containing module: 'mexor'\nmexor g2({w1[6],w1[5],w1[4],w1[2],w1[1]},{w2[6],w2[5],w2[4],w2[2],w2[1]});\n^~~~~\n%Error: data/full_repos/permissive/135852214/Verilog/RFA.v:35: Cannot find file containing module: 'tcnot'\ntcnot g3({w2[6],w2[3],w2[2],w2[1]},{out[6],out[3],out[2],out[1]});\n^~~~~\n%Error: Exiting due to 4 error(s)\n"
module RFA(
    input [6:0] in,
    output [6:0] out
    );
wire [6:0] w0;
assign {w0[2],w0[3]} = {in[2],in[3]};
mexor g0({in[6],in[5],in[4],in[1],in[0]},{w0[6],w0[5],w0[4],w0[1],w0[0]});
wire [6:0] w1;
assign {w1[2],w1[4],w1[6]} = {w0[2],w0[4],w0[6]};
tcnot g1({w0[5],w0[3],w0[1],w0[0]},{w1[5],w1[3],w1[1],w1[0]});
wire [6:0] w2;
assign {w2[0],w2[3]} = {w1[0],w1[3]};
mexor g2({w1[6],w1[5],w1[4],w1[2],w1[1]},{w2[6],w2[5],w2[4],w2[2],w2[1]});
assign {out[0],out[4],out[5]} = {w2[0],w2[4],w2[5]};
tcnot g3({w2[6],w2[3],w2[2],w2[1]},{out[6],out[3],out[2],out[1]});
endmodule
module RFA(
    input [6:0] in,
    output [6:0] out
    );

wire [6:0] w0;
assign {w0[2],w0[3]} = {in[2],in[3]};
mexor g0({in[6],in[5],in[4],in[1],in[0]},{w0[6],w0[5],w0[4],w0[1],w0[0]});
wire [6:0] w1;
assign {w1[2],w1[4],w1[6]} = {w0[2],w0[4],w0[6]};
tcnot g1({w0[5],w0[3],w0[1],w0[0]},{w1[5],w1[3],w1[1],w1[0]});
wire [6:0] w2;
assign {w2[0],w2[3]} = {w1[0],w1[3]};
mexor g2({w1[6],w1[5],w1[4],w1[2],w1[1]},{w2[6],w2[5],w2[4],w2[2],w2[1]});
assign {out[0],out[4],out[5]} = {w2[0],w2[4],w2[5]};
tcnot g3({w2[6],w2[3],w2[2],w2[1]},{out[6],out[3],out[2],out[1]});
endmodule