data/full_repos/permissive/100331186/tarea5/con-retrasos/src/sreg1.v
data/verilator_xmls/9402ee39-4820-466c-b16c-7f170a1edf2f.xml
module rdesplazante1(CLK, ENB,DIR,S_IN,MODE,D,Q,S_OUT);
input [3 : 0] D;
input [1:0] MODE;
input ENB,S_IN,CLK,DIR;
output reg [3:0] Q;
output reg S_OUT;

always@(posedge CLK)
	if(ENB) begin
		if(MODE === 2'b00) begin
			S_OUT = 1;	
			if(!DIR) begin
			       	Q[3:0] <= {Q[2:0],S_IN};
				S_OUT <= Q[3];
			end
			else begin
			       	Q[3:0] <= {S_IN,Q[3:1]};
				S_OUT <= Q[0];
			end

		end
		if(MODE === 2'b01) begin
			if(!DIR) begin
				Q[3:1] <= Q[2:0];
				Q[0] <= Q[3];
				end
				else begin
					Q[3] <= Q[0];
					Q[2:0] <= Q[3:1];
				end
		end
		if(MODE === 2'b10) begin
			Q <= D;
		end
end

endmodule
module rdesplazante1(CLK, ENB,DIR,S_IN,MODE,D,Q,S_OUT);

input [3 : 0] D;
input [1:0] MODE;
input ENB,S_IN,CLK,DIR;
output reg [3:0] Q;
output reg S_OUT;

always@(posedge CLK)
	if(ENB) begin
		if(MODE === 2'b00) begin
			S_OUT = 1;	
			if(!DIR) begin
			       	Q[3:0] <= {Q[2:0],S_IN};
				S_OUT <= Q[3];
			end
			else begin
			       	Q[3:0] <= {S_IN,Q[3:1]};
				S_OUT <= Q[0];
			end

		end
		if(MODE === 2'b01) begin
			if(!DIR) begin
				Q[3:1] <= Q[2:0];
				Q[0] <= Q[3];
				end
				else begin
					Q[3] <= Q[0];
					Q[2:0] <= Q[3:1];
				end
		end
		if(MODE === 2'b10) begin
			Q <= D;
		end
end

endmodule