data/full_repos/permissive/143278/ivltests/mem2port.v
 line:25: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mem2port.v:17: Unsupported: Ignoring delay on this delayed statement.\n                #10     x[0] = 0;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mem2port.v:20: Unsupported: Ignoring delay on this delayed statement.\n                #100    x[0] = 1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mem2port.v:21: Unsupported: Ignoring delay on this delayed statement.\n                #100    x[0] = 0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mem2port.v:23: Unsupported: Ignoring delay on this delayed statement.\n                #100    x[1] = 0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mem2port.v:25: Unsupported: Ignoring delay on this delayed statement.\n                #100    $finish;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mem2port.v:31: Unsupported: Ignoring delay on this delayed statement.\n        always #100\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mem2port.v:38: Unsupported: Ignoring delay on this delayed statement.\n #100 if (x1 !== 7\'b0 || x2 !== 7\'b0 || x3 !== 7\'b0)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mem2port.v:40: Unsupported: Ignoring delay on this delayed statement.\n #100 if (x1 !== 7\'b1 || x2 !== 7\'b0 || x3 !== 7\'b0)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mem2port.v:42: Unsupported: Ignoring delay on this delayed statement.\n #100 if (x1 !== 7\'b0 || x2 !== 7\'b1 || x3 !== 7\'b0)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mem2port.v:44: Unsupported: Ignoring delay on this delayed statement.\n #100 if (x1 !== 7\'b0 || x2 !== 7\'b0 || x3 !== 7\'b1)\n ^\n%Error: Exiting due to 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module speak(x1, x2, x3);
        input [6:0] x1, x2, x3;
        always #100
                $display ("%d: x1=%d, x2=%d, x3=%d", $time, x1, x2, x3);

   integer	    errors;
   initial
     begin
	errors = 0;
	#100 if (x1 !== 7'b0 || x2 !== 7'b0 || x3 !== 7'b0)
	  begin errors = errors + 1; $display("FAILED"); end
	#100 if (x1 !== 7'b1 || x2 !== 7'b0 || x3 !== 7'b0)
	  begin errors = errors + 1; $display("FAILED"); end
	#100 if (x1 !== 7'b0 || x2 !== 7'b1 || x3 !== 7'b0)
	  begin errors = errors + 1; $display("FAILED"); end
	#100 if (x1 !== 7'b0 || x2 !== 7'b0 || x3 !== 7'b1)
	  begin errors = errors + 1; $display("FAILED"); end
	if (errors === 0)
	  $display("PASSED");
     end

endmodule
module speak(x1, x2, x3);

        input [6:0] x1, x2, x3;
        always #100
                $display ("%d: x1=%d, x2=%d, x3=%d", $time, x1, x2, x3);

   integer	    errors;
   initial
     begin
	errors = 0;
	#100 if (x1 !== 7'b0 || x2 !== 7'b0 || x3 !== 7'b0)
	  begin errors = errors + 1; $display("FAILED"); end
	#100 if (x1 !== 7'b1 || x2 !== 7'b0 || x3 !== 7'b0)
	  begin errors = errors + 1; $display("FAILED"); end
	#100 if (x1 !== 7'b0 || x2 !== 7'b1 || x3 !== 7'b0)
	  begin errors = errors + 1; $display("FAILED"); end
	#100 if (x1 !== 7'b0 || x2 !== 7'b0 || x3 !== 7'b1)
	  begin errors = errors + 1; $display("FAILED"); end
	if (errors === 0)
	  $display("PASSED");
     end

endmodule