data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:75: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 48 bits.\n                                                                                                                    : ... In instance stepper_motor_control_calc\n            st3_d     <= {X_WIDTH{1\'bx}};\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:85: Operator NEGATE expects 50 bits on the LHS, but LHS\'s VARREF \'st0_d\' generates 49 bits.\n                                                                                                                    : ... In instance stepper_motor_control_calc\n                st1_d    <= -st0_d;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:90: Operator ASSIGNDLY expects 50 bits on the Assign RHS, but Assign RHS\'s VARREF \'st0_d\' generates 49 bits.\n                                                                                                                    : ... In instance stepper_motor_control_calc\n                st1_d    <= st0_d;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:97: Operator LTE expects 50 bits on the RHS, but RHS\'s VARREF \'max_a\' generates 16 bits.\n                                                                                                                    : ... In instance stepper_motor_control_calc\n            st2_near  <= (st1_d <= max_a);\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:98: Operator SHIFTL expects 53 bits on the LHS, but LHS\'s VARREF \'st1_d\' generates 50 bits.\n                                                                                                                    : ... In instance stepper_motor_control_calc\n            st2_d     <= (st1_d << 3) + max_a;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:98: Operator ADD expects 53 bits on the RHS, but RHS\'s VARREF \'max_a\' generates 16 bits.\n                                                                                                                    : ... In instance stepper_motor_control_calc\n            st2_d     <= (st1_d << 3) + max_a;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:102: Operator GT expects 53 bits on the RHS, but RHS\'s VARREF \'max_d\' generates 32 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            st3_d     <= (st2_d > max_d) ? max_d : st2_d;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:102: Operator COND expects 53 bits on the Conditional True, but Conditional True\'s VARREF \'max_d\' generates 32 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            st3_d     <= (st2_d > max_d) ? max_d : st2_d;\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:102: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 53 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            st3_d     <= (st2_d > max_d) ? max_d : st2_d;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:109: Operator ASSIGNW expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'st1_d\' generates 50 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n    wire    signed  [X_WIDTH:0]     d_dir  = st1_d;           \n                                           ^\n%Error: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:116: Cannot find file containing module: \'jelly_unsigned_multiply_multicycle\'\n    jelly_unsigned_multiply_multicycle\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl,data/full_repos/permissive/2084115/jelly_unsigned_multiply_multicycle\n             data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl,data/full_repos/permissive/2084115/jelly_unsigned_multiply_multicycle.v\n             data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl,data/full_repos/permissive/2084115/jelly_unsigned_multiply_multicycle.sv\n             jelly_unsigned_multiply_multicycle\n             jelly_unsigned_multiply_multicycle.v\n             jelly_unsigned_multiply_multicycle.sv\n             obj_dir/jelly_unsigned_multiply_multicycle\n             obj_dir/jelly_unsigned_multiply_multicycle.v\n             obj_dir/jelly_unsigned_multiply_multicycle.sv\n%Error: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:141: Cannot find file containing module: \'jelly_unsigned_sqrt_multicycle\'\n    jelly_unsigned_sqrt_multicycle\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:186: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            st9_a      <= {(1+A_WIDTH){1\'bx}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:193: Operator SUB expects 24 bits on the RHS, but RHS\'s VARREF \'max_a\' generates 16 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            st6_lim_v <= (st5_lim_v - max_a) >> 1;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:197: Operator COND expects 49 bits on the Conditional False, but Conditional False\'s REPLICATE generates 25 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            st7_lim_v <= d_near ? d_dir : {1\'b0, st6_lim_v};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:197: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s COND generates 49 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            st7_lim_v <= d_near ? d_dir : {1\'b0, st6_lim_v};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:201: Operator SUB expects 25 bits on the RHS, but RHS\'s VARREF \'v_dir\' generates 17 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            st8_a     <= st7_lim_v - v_dir;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:202: Operator COND expects 25 bits on the Conditional True, but Conditional True\'s VARREF \'max_a_near\' generates 16 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            st8_max_a <= d_near ? max_a_near : max_a;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:202: Operator COND expects 25 bits on the Conditional False, but Conditional False\'s VARREF \'max_a\' generates 16 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            st8_max_a <= d_near ? max_a_near : max_a;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:206: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'st8_a\' generates 25 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            st9_a <= st8_a;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:207: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'st8_max_a\' generates 25 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            if ( st8_a > st8_max_a ) begin st9_a <= st8_max_a; end\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:208: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'st8_min_a\' generates 25 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n            if ( st8_a < st8_min_a ) begin st9_a <= st8_min_a; end\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:213: Operator NEGATE expects 17 bits on the LHS, but LHS\'s VARREF \'st9_a\' generates 16 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n                st10_a <= d_sign ? -st9_a : +st9_a;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/kv260_stepper_motor/rtl/stepper_motor_control_calc.sv:213: Operator COND expects 17 bits on the Conditional False, but Conditional False\'s VARREF \'st9_a\' generates 16 bits.\n                                                                                                                     : ... In instance stepper_motor_control_calc\n                st10_a <= d_sign ? -st9_a : +st9_a;\n                                 ^\n%Error: Exiting due to 2 error(s), 22 warning(s)\n'
module stepper_motor_control_calc
        #(
            parameter   X_WIDTH = 48,
            parameter   V_WIDTH = 16,
            parameter   A_WIDTH = 16
        )
        (
            input   wire                            reset,
            input   wire                            clk,
            input   wire                            cke,
            
            input   wire                            start,
            
            input   wire    signed  [X_WIDTH-1:0]   target_x,
            input   wire    signed  [X_WIDTH-1:0]   cur_x,
            input   wire    signed  [V_WIDTH:0]     cur_v,
            input   wire            [A_WIDTH-1:0]   max_a,
            input   wire            [A_WIDTH-1:0]   max_a_near,
            
            output  wire    signed  [A_WIDTH:0]     out_a,
            output  wire                            out_valid
        );
    

    
    localparam  D_WIDTH = 2*V_WIDTH;
    localparam  L_WIDTH = (D_WIDTH+A_WIDTH+1)/2;
    
    
    wire            [D_WIDTH-1:0]   max_d = {D_WIDTH{1'b1}};
    
    reg     signed  [X_WIDTH:0]     st0_d;
    reg                             st0_valid;
    
    reg     signed  [X_WIDTH+1:0]   st1_d;
    reg     signed  [V_WIDTH:0]     st1_v;
    reg                             st1_sign;
    reg                             st1_valid;
    
    reg             [X_WIDTH+4:0]   st2_d;
    reg                             st2_near;
    reg                             st2_valid;
    
    reg             [D_WIDTH-1:0]   st3_d;
    reg                             st3_valid;
    
    always @(posedge clk) begin
        if ( reset ) begin
            st0_d     <= {(1+X_WIDTH){1'bx}};
            st0_valid <= 1'b0;
            
            st1_d     <= {(2+X_WIDTH){1'bx}};
            st1_v     <= {(1+V_WIDTH){1'bx}};
            st1_sign  <= 1'bx;
            st1_valid <= 1'b0;
            
            st2_d     <= {(X_WIDTH+5){1'bx}};
            st2_near  <= 1'bx;
            st2_valid <= 1'b0;
            
            st3_d     <= {X_WIDTH{1'bx}};
            st3_valid <= 1'b0;
        end
        else begin

            st0_d     <= target_x - cur_x;
            st0_valid <= start;
            

            if ( st0_d < 0 ) begin
                st1_d    <= -st0_d;
                st1_v    <= -cur_v;
                st1_sign <= 1'b1;
            end
            else begin
                st1_d    <= st0_d;
                st1_v    <= cur_v;
                st1_sign <= 1'b0;
            end
            st1_valid <= st0_valid;
            

            st2_near  <= (st1_d <= max_a);
            st2_d     <= (st1_d << 3) + max_a;
            st2_valid <= st1_valid;
            

            st3_d     <= (st2_d > max_d) ? max_d : st2_d;
            st3_valid <= st2_valid;
        end
    end
    
    wire                            d_sign = st1_sign;
    wire                            d_near = st2_near;
    wire    signed  [X_WIDTH:0]     d_dir  = st1_d;
    wire    signed  [V_WIDTH:0]     v_dir  = st1_v;
    
    

    wire    [D_WIDTH+A_WIDTH-1:0]   st4_p;
    wire                            st4_valid;
    jelly_unsigned_multiply_multicycle
            #(
                .DATA_WIDTH0    (D_WIDTH),
                .DATA_WIDTH1    (A_WIDTH)
            )
        i_unsigned_multiply_multicycle
            (
                .reset          (reset),
                .clk            (clk),
                .cke            (cke),
                
                .s_data0        (st3_d),
                .s_data1        (max_a),
                .s_valid        (st3_valid),
                .s_ready        (),
                
                .m_data         (st4_p),
                .m_valid        (st4_valid),
                .m_ready        (1'b1)
            );
    
    

    wire    [L_WIDTH-1:0]       st5_lim_v;
    wire                        st5_valid;
    jelly_unsigned_sqrt_multicycle
            #(
                .DATA_WIDTH     (L_WIDTH)
            )
        i_unsigned_sqrt_multicycle
            (
                .reset          (reset),
                .clk            (clk),
                .cke            (cke),
                
                .s_data         (st4_p),
                .s_valid        (st4_valid),
                .s_ready        (),
                
                .m_data         (st5_lim_v),
                .m_valid        (st5_valid),
                .m_ready        (1'b1)
            );
    
    
    reg             [L_WIDTH-1:0]   st6_lim_v;
    reg                             st6_valid;
    
    reg     signed  [L_WIDTH:0]     st7_lim_v;
    reg                             st7_valid;
    
    reg     signed  [L_WIDTH:0]     st8_a;
    reg     signed  [L_WIDTH:0]     st8_max_a;
    wire    signed  [L_WIDTH:0]     st8_min_a = -st8_max_a;
    reg                             st8_valid;
    
    reg     signed  [A_WIDTH-1:0]   st9_a;
    reg                             st9_valid;
    
    reg     signed  [A_WIDTH:0]     st10_a;
    reg                             st10_valid;
    always @(posedge clk) begin
        if ( reset ) begin
            st6_lim_v  <= {L_WIDTH{1'bx}};
            st6_valid  <= 1'b0;
            st7_lim_v  <= {(1+L_WIDTH){1'bx}};
            st7_valid  <= 1'b0;
            st8_a      <= {(1+L_WIDTH){1'bx}};
            st8_max_a  <= {(1+L_WIDTH){1'bx}};
            st8_valid  <= 1'b0;
            st9_a      <= {(1+A_WIDTH){1'bx}};
            st9_valid  <= 1'b0;
            st10_a     <= {(1+A_WIDTH){1'b0}};
            st10_valid <= 1'b0;
        end
        else begin

            st6_lim_v <= (st5_lim_v - max_a) >> 1;
            st6_valid <= st5_valid;
            

            st7_lim_v <= d_near ? d_dir : {1'b0, st6_lim_v};
            st7_valid <= st6_valid;
            

            st8_a     <= st7_lim_v - v_dir;
            st8_max_a <= d_near ? max_a_near : max_a;
            st8_valid <= st7_valid;
            

            st9_a <= st8_a;
            if ( st8_a > st8_max_a ) begin st9_a <= st8_max_a; end
            if ( st8_a < st8_min_a ) begin st9_a <= st8_min_a; end
            st9_valid <= st8_valid;
            

            if ( st9_valid ) begin
                st10_a <= d_sign ? -st9_a : +st9_a;
            end
            st10_valid <= st9_valid;
        end
    end
    
    assign out_a     = st10_a;
    assign out_valid = st10_valid;
    
endmodule
module stepper_motor_control_calc
        #(
            parameter   X_WIDTH = 48,
            parameter   V_WIDTH = 16,
            parameter   A_WIDTH = 16
        )
        (
            input   wire                            reset,
            input   wire                            clk,
            input   wire                            cke,
            
            input   wire                            start,
            
            input   wire    signed  [X_WIDTH-1:0]   target_x,
            input   wire    signed  [X_WIDTH-1:0]   cur_x,
            input   wire    signed  [V_WIDTH:0]     cur_v,
            input   wire            [A_WIDTH-1:0]   max_a,
            input   wire            [A_WIDTH-1:0]   max_a_near,
            
            output  wire    signed  [A_WIDTH:0]     out_a,
            output  wire                            out_valid
        );

    

    
    localparam  D_WIDTH = 2*V_WIDTH;
    localparam  L_WIDTH = (D_WIDTH+A_WIDTH+1)/2;
    
    
    wire            [D_WIDTH-1:0]   max_d = {D_WIDTH{1'b1}};
    
    reg     signed  [X_WIDTH:0]     st0_d;
    reg                             st0_valid;
    
    reg     signed  [X_WIDTH+1:0]   st1_d;
    reg     signed  [V_WIDTH:0]     st1_v;
    reg                             st1_sign;
    reg                             st1_valid;
    
    reg             [X_WIDTH+4:0]   st2_d;
    reg                             st2_near;
    reg                             st2_valid;
    
    reg             [D_WIDTH-1:0]   st3_d;
    reg                             st3_valid;
    
    always @(posedge clk) begin
        if ( reset ) begin
            st0_d     <= {(1+X_WIDTH){1'bx}};
            st0_valid <= 1'b0;
            
            st1_d     <= {(2+X_WIDTH){1'bx}};
            st1_v     <= {(1+V_WIDTH){1'bx}};
            st1_sign  <= 1'bx;
            st1_valid <= 1'b0;
            
            st2_d     <= {(X_WIDTH+5){1'bx}};
            st2_near  <= 1'bx;
            st2_valid <= 1'b0;
            
            st3_d     <= {X_WIDTH{1'bx}};
            st3_valid <= 1'b0;
        end
        else begin

            st0_d     <= target_x - cur_x;
            st0_valid <= start;
            

            if ( st0_d < 0 ) begin
                st1_d    <= -st0_d;
                st1_v    <= -cur_v;
                st1_sign <= 1'b1;
            end
            else begin
                st1_d    <= st0_d;
                st1_v    <= cur_v;
                st1_sign <= 1'b0;
            end
            st1_valid <= st0_valid;
            

            st2_near  <= (st1_d <= max_a);
            st2_d     <= (st1_d << 3) + max_a;
            st2_valid <= st1_valid;
            

            st3_d     <= (st2_d > max_d) ? max_d : st2_d;
            st3_valid <= st2_valid;
        end
    end
    
    wire                            d_sign = st1_sign;
    wire                            d_near = st2_near;
    wire    signed  [X_WIDTH:0]     d_dir  = st1_d;
    wire    signed  [V_WIDTH:0]     v_dir  = st1_v;
    
    

    wire    [D_WIDTH+A_WIDTH-1:0]   st4_p;
    wire                            st4_valid;
    jelly_unsigned_multiply_multicycle
            #(
                .DATA_WIDTH0    (D_WIDTH),
                .DATA_WIDTH1    (A_WIDTH)
            )
        i_unsigned_multiply_multicycle
            (
                .reset          (reset),
                .clk            (clk),
                .cke            (cke),
                
                .s_data0        (st3_d),
                .s_data1        (max_a),
                .s_valid        (st3_valid),
                .s_ready        (),
                
                .m_data         (st4_p),
                .m_valid        (st4_valid),
                .m_ready        (1'b1)
            );
    
    

    wire    [L_WIDTH-1:0]       st5_lim_v;
    wire                        st5_valid;
    jelly_unsigned_sqrt_multicycle
            #(
                .DATA_WIDTH     (L_WIDTH)
            )
        i_unsigned_sqrt_multicycle
            (
                .reset          (reset),
                .clk            (clk),
                .cke            (cke),
                
                .s_data         (st4_p),
                .s_valid        (st4_valid),
                .s_ready        (),
                
                .m_data         (st5_lim_v),
                .m_valid        (st5_valid),
                .m_ready        (1'b1)
            );
    
    
    reg             [L_WIDTH-1:0]   st6_lim_v;
    reg                             st6_valid;
    
    reg     signed  [L_WIDTH:0]     st7_lim_v;
    reg                             st7_valid;
    
    reg     signed  [L_WIDTH:0]     st8_a;
    reg     signed  [L_WIDTH:0]     st8_max_a;
    wire    signed  [L_WIDTH:0]     st8_min_a = -st8_max_a;
    reg                             st8_valid;
    
    reg     signed  [A_WIDTH-1:0]   st9_a;
    reg                             st9_valid;
    
    reg     signed  [A_WIDTH:0]     st10_a;
    reg                             st10_valid;
    always @(posedge clk) begin
        if ( reset ) begin
            st6_lim_v  <= {L_WIDTH{1'bx}};
            st6_valid  <= 1'b0;
            st7_lim_v  <= {(1+L_WIDTH){1'bx}};
            st7_valid  <= 1'b0;
            st8_a      <= {(1+L_WIDTH){1'bx}};
            st8_max_a  <= {(1+L_WIDTH){1'bx}};
            st8_valid  <= 1'b0;
            st9_a      <= {(1+A_WIDTH){1'bx}};
            st9_valid  <= 1'b0;
            st10_a     <= {(1+A_WIDTH){1'b0}};
            st10_valid <= 1'b0;
        end
        else begin

            st6_lim_v <= (st5_lim_v - max_a) >> 1;
            st6_valid <= st5_valid;
            

            st7_lim_v <= d_near ? d_dir : {1'b0, st6_lim_v};
            st7_valid <= st6_valid;
            

            st8_a     <= st7_lim_v - v_dir;
            st8_max_a <= d_near ? max_a_near : max_a;
            st8_valid <= st7_valid;
            

            st9_a <= st8_a;
            if ( st8_a > st8_max_a ) begin st9_a <= st8_max_a; end
            if ( st8_a < st8_min_a ) begin st9_a <= st8_min_a; end
            st9_valid <= st8_valid;
            

            if ( st9_valid ) begin
                st10_a <= d_sign ? -st9_a : +st9_a;
            end
            st10_valid <= st9_valid;
        end
    end
    
    assign out_a     = st10_a;
    assign out_valid = st10_valid;
    
endmodule