data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ClockGen.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ClockGen.v:49: Unsupported: Ignoring delay on this delayed statement.\n         #0 ;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ClockGen.v:51: Unsupported: Ignoring delay on this delayed statement.\n         # initDelay ;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ClockGen.v:55: Unsupported: Ignoring delay on this delayed statement.\n               # v1Width ;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ClockGen.v:57: Unsupported: Ignoring delay on this delayed statement.\n               # v2Width ;\n               ^\n%Warning-INFINITELOOP: data/full_repos/permissive/135350124/src_SSITH_P1/xilinx_ip/hdl/ClockGen.v:52: Infinite loop (condition always true)\n                                                                                                    : ... In instance ClockGen\n         forever\n         ^~~~~~~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testClockGen1() ;

   wire clkout ;

   ClockGen#(8,24,16,1'b1,1'b0)  u1( clkout );

   initial
     begin
        $dumpfile("ClockGen.dump");
        $dumpvars(5) ;
        $dumpon ;
        #10000 $finish ;
     end

endmodule
module testClockGen1() ;


   wire clkout ;

   ClockGen#(8,24,16,1'b1,1'b0)  u1( clkout );

   initial
     begin
        $dumpfile("ClockGen.dump");
        $dumpvars(5) ;
        $dumpon ;
        #10000 $finish ;
     end

endmodule