data/full_repos/permissive/168395472/labs/00_test/lab00_test.v
data/verilator_xmls/4c2ad83f-7c46-4033-9b9f-f2b196f84898.xml
module lab00_test(
    input wire clk,

    output wire clk1
);

assign clk1 = clk;

endmodule
module lab00_test(
    input wire clk,

    output wire clk1
);


assign clk1 = clk;

endmodule