data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v
1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:7: Define or directive not defined: \'`STAT_BUS\'\n    input wire [`STAT_BUS] m_stat_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`STAT_BUS] m_stat_i,\n                         ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:8: Define or directive not defined: \'`ICODE_BUS\'\n    input wire [`ICODE_BUS] M_icode_i,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:9: Define or directive not defined: \'`DATA_BUS\'\n    input wire [`DATA_BUS] M_valE_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:10: Define or directive not defined: \'`DATA_BUS\'\n    input wire [`DATA_BUS] m_valM_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:11: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input wire [`REG_ADDR_BUS] M_dstE_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:12: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input wire [`REG_ADDR_BUS] M_dstM_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:14: Define or directive not defined: \'`STAT_BUS\'\n    output reg [`STAT_BUS] W_stat_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:15: Define or directive not defined: \'`ICODE_BUS\'\n    output reg [`ICODE_BUS] W_icode_o,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:16: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] W_valE_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:17: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] W_valM_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:18: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output reg [`REG_ADDR_BUS] W_dstE_o,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:19: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output reg [`REG_ADDR_BUS] W_dstM_o\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:24: Define or directive not defined: \'`SAOK\'\n             W_stat_o <= `SAOK;\n                         ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:25: Define or directive not defined: \'`NOP\'\n            W_icode_o <= `NOP;\n                         ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:26: Define or directive not defined: \'`DATA_ZERO\'\n            W_valE_o <= `DATA_ZERO;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:27: Define or directive not defined: \'`DATA_ZERO\'\n            W_valM_o <= `DATA_ZERO;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:28: Define or directive not defined: \'`NREG\'\n            W_dstE_o <= `NREG;\n                        ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:29: Define or directive not defined: \'`NREG\'\n            W_dstM_o <= `NREG;\n                        ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:34: Define or directive not defined: \'`RST_EN\'\n            if(rst == `RST_EN)\n                      ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:36: Define or directive not defined: \'`SAOK\'\n                W_stat_o <= `SAOK;\n                            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:37: Define or directive not defined: \'`NOP\'\n                W_icode_o <= `NOP;\n                             ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:38: Define or directive not defined: \'`DATA_ZERO\'\n                W_valE_o <= `DATA_ZERO;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:39: Define or directive not defined: \'`DATA_ZERO\'\n                W_valM_o <= `DATA_ZERO;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:40: Define or directive not defined: \'`NREG\'\n                W_dstE_o <= `NREG;\n                            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:41: Define or directive not defined: \'`NREG\'\n                W_dstM_o <= `NREG;\n                            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/write_reg.v:43: Define or directive not defined: \'`TRUE\'\n            else if(W_stall_i == `TRUE)\n                                 ^~~~~\n%Error: Exiting due to 28 error(s)\n'
module write_reg(
    input wire clk,
    input wire rst,
    input wire W_stall_i,
    input wire [`STAT_BUS] m_stat_i,
    input wire [`ICODE_BUS] M_icode_i,
    input wire [`DATA_BUS] M_valE_i,
    input wire [`DATA_BUS] m_valM_i,
    input wire [`REG_ADDR_BUS] M_dstE_i,
    input wire [`REG_ADDR_BUS] M_dstM_i,
    
    output reg [`STAT_BUS] W_stat_o,
    output reg [`ICODE_BUS] W_icode_o,
    output reg [`DATA_BUS] W_valE_o,
    output reg [`DATA_BUS] W_valM_o,
    output reg [`REG_ADDR_BUS] W_dstE_o,
    output reg [`REG_ADDR_BUS] W_dstM_o
    );

    initial
        begin   
             W_stat_o <= `SAOK;
            W_icode_o <= `NOP;
            W_valE_o <= `DATA_ZERO;
            W_valM_o <= `DATA_ZERO;
            W_dstE_o <= `NREG;
            W_dstM_o <= `NREG;
        end
    
    always @(posedge clk)
        begin
            if(rst == `RST_EN)
            begin
                W_stat_o <= `SAOK;
                W_icode_o <= `NOP;
                W_valE_o <= `DATA_ZERO;
                W_valM_o <= `DATA_ZERO;
                W_dstE_o <= `NREG;
                W_dstM_o <= `NREG;
            end
            else if(W_stall_i == `TRUE)
            begin
                W_stat_o <= W_stat_o;
                W_icode_o <= W_icode_o;
                W_valE_o <= W_valE_o;
                W_valM_o <= W_valM_o;
                W_dstE_o <= W_dstE_o;
                W_dstM_o <= W_dstM_o;
            end
            else
            begin
                W_stat_o <= m_stat_i;
                W_icode_o <= M_icode_i;
                W_valE_o <= M_valE_i;
                W_valM_o <= m_valM_i;
                W_dstE_o <= M_dstE_i;
                W_dstM_o <= M_dstM_i;
            end
        end
    
endmodule
module write_reg(
    input wire clk,
    input wire rst,
    input wire W_stall_i,
    input wire [`STAT_BUS] m_stat_i,
    input wire [`ICODE_BUS] M_icode_i,
    input wire [`DATA_BUS] M_valE_i,
    input wire [`DATA_BUS] m_valM_i,
    input wire [`REG_ADDR_BUS] M_dstE_i,
    input wire [`REG_ADDR_BUS] M_dstM_i,
    
    output reg [`STAT_BUS] W_stat_o,
    output reg [`ICODE_BUS] W_icode_o,
    output reg [`DATA_BUS] W_valE_o,
    output reg [`DATA_BUS] W_valM_o,
    output reg [`REG_ADDR_BUS] W_dstE_o,
    output reg [`REG_ADDR_BUS] W_dstM_o
    );


    initial
        begin   
             W_stat_o <= `SAOK;
            W_icode_o <= `NOP;
            W_valE_o <= `DATA_ZERO;
            W_valM_o <= `DATA_ZERO;
            W_dstE_o <= `NREG;
            W_dstM_o <= `NREG;
        end
    
    always @(posedge clk)
        begin
            if(rst == `RST_EN)
            begin
                W_stat_o <= `SAOK;
                W_icode_o <= `NOP;
                W_valE_o <= `DATA_ZERO;
                W_valM_o <= `DATA_ZERO;
                W_dstE_o <= `NREG;
                W_dstM_o <= `NREG;
            end
            else if(W_stall_i == `TRUE)
            begin
                W_stat_o <= W_stat_o;
                W_icode_o <= W_icode_o;
                W_valE_o <= W_valE_o;
                W_valM_o <= W_valM_o;
                W_dstE_o <= W_dstE_o;
                W_dstM_o <= W_dstM_o;
            end
            else
            begin
                W_stat_o <= m_stat_i;
                W_icode_o <= M_icode_i;
                W_valE_o <= M_valE_i;
                W_valM_o <= m_valM_i;
                W_dstE_o <= M_dstE_i;
                W_dstM_o <= M_dstM_i;
            end
        end
    
endmodule