data/full_repos/permissive/148201731/sim/ver/tosco_tb/tosco_tb_v2.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/tosco_tb/tosco_tb_v2.sv:290: Unsupported: Ignoring delay on this delayed statement.\n   #10  clk = ~clk;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/tosco_tb/tosco_tb_v2.sv:295: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/tosco_tb/tosco_tb_v2.sv:297: Unsupported: Ignoring delay on this delayed statement.\n#30;\n^\n%Error: data/full_repos/permissive/148201731/sim/ver/tosco_tb/tosco_tb_v2.sv:298: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Warning-STMTDLY: data/full_repos/permissive/148201731/sim/ver/tosco_tb/tosco_tb_v2.sv:299: Unsupported: Ignoring delay on this delayed statement.\n#1\n^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tosco_tb_v2;


reg clk, rst_n;


localparam DATA_WIDTH = 32;
localparam INST_ADDR_WIDTH = 20;
localparam ADDR_WIDTH = 20;
localparam DATA_ADDR_WIDTH = 32;
localparam SRAM_ADDR_WIDTH = 20;
localparam SRAM_DATA_WIDTH = 16;
localparam SDRAM_DATA_WIDTH = 32;
localparam SDRAM_ADDR_WIDTH = 20;
localparam SDRAM_DQM_WIDTH = 4;
localparam SDRAM_BA_WIDTH = 2;

wire data_rd_en;
wire data_wr_en;
wire [DATA_WIDTH-1:0] data_read;
wire [DATA_WIDTH-1:0] data_write;

wire instr_rd_en;
wire [INST_ADDR_WIDTH-1:0] instr_addr;
wire [DATA_WIDTH-1:0] instruction;

wire boot_mem_rd_en;
wire inst_mem_wr_en;

wire [ADDR_WIDTH-1:0] data_addr;
wire [DATA_WIDTH-1:0] data_out;
wire [DATA_WIDTH-1:0] data_in;

wire  [SDRAM_DATA_WIDTH-1:0]  dram_dq;
wire  [SDRAM_DATA_WIDTH-1:0]  dram_dq_in;
wire  [SDRAM_DATA_WIDTH-1:0]  dram_dq_out;
wire [SDRAM_ADDR_WIDTH-1:0]  dram_addr;
wire [SDRAM_DQM_WIDTH-1:0]   dram_dqm;
wire         dram_we_n;
wire         dram_cas_n;
wire         dram_ras_n;
wire         dram_cs_n;
wire [SDRAM_BA_WIDTH-1:0]   dram_ba;
wire         dram_clk;
wire         dram_cke;


wire boot_mode;
wire boot_mem_wr_en;
wire [ADDR_WIDTH-1:0] boot_mem_addr;
wire [DATA_WIDTH-1:0] boot_mem_rd_data;
wire [DATA_WIDTH-1:0] boot_mem_wr_data;

wire inst_mem_rd_en;
wire [DATA_WIDTH-1:0] inst_mem_wr_data;
wire [DATA_WIDTH-1:0] inst_mem_rd_data;
wire [ADDR_WIDTH-1:0] inst_mem_addr;

wire sram_mem_wr_en;
wire sram_mem_rd_en;
wire [DATA_WIDTH-1:0] sram_mem_wr_data;
wire [DATA_WIDTH-1:0] sram_mem_rd_data;
wire [ADDR_WIDTH-1:0] sram_mem_addr;

wire inst_mem_rd_en_proc;
wire [19:0] inst_mem_addr_proc;
wire [31:0] inst_mem_rd_data_proc;
wire data_rd_en_proc;
wire data_wr_en_proc;
wire [19:0] data_addr_proc;
wire [31:0] data_read_proc;
wire [31:0] data_write_proc;

clk_rst_mngr
clk_rst_mngr_u0
   (
   .clk_in(clk),
   .rst_async_n(rst_n),
   .en_clk_div8(!boot_mode),
   .rst_sync_n(rst_sync_n),
   .clk_out(clk_out),
   .clk_div2(clk_div2),
   .clk_div4(clk_div4),
   .clk_div8(clk_div8),
   .clk_div8_proc(clk_div8_proc)
  );




dlx_processor
#(
   .DATA_WIDTH(DATA_WIDTH),
   .INST_ADDR_WIDTH(INST_ADDR_WIDTH),
   .DATA_ADDR_WIDTH(DATA_ADDR_WIDTH)
)
dlx_processor_u0
(
   .clk(clk_div8_proc),
   .rst_n(rst_sync_n),

   .instr_rd_en(inst_mem_rd_en_proc),
   .instr_addr(inst_mem_addr_proc),
   .instruction(inst_mem_rd_data_proc),

   .data_rd_en(data_rd_en_proc),
   .data_wr_en(data_wr_en_proc),
   .data_addr(data_addr_proc),
   .data_read(data_read_proc),
   .data_write(data_write_proc)
);

data_memory_controll
  #(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(ADDR_WIDTH),
   .SDRAM_DATA_WIDTH(SDRAM_DATA_WIDTH),
   .SDRAM_ADDR_WIDTH(SDRAM_ADDR_WIDTH)

  )
  memory_controll
  (
   .clk(clk_out),
   .rst_n(rst_sync_n),
   .data_rd_en(data_rd_en_proc),
   .data_wr_en(data_wr_en_proc),
   .data_addr(data_addr_proc),
   .data_out(data_read_proc),
   .data_in(data_write_proc),

   .dram_dq_in(dram_dq_in),
   .dram_dq_out(dram_dq_out),
   .dram_addr(dram_addr),
   .dram_dqm(dram_dqm),
   .dram_we_n(dram_we_n),
   .dram_cas_n(dram_cas_n),
   .dram_ras_n(dram_ras_n),
   .dram_cs_n(dram_cs_n),
   .dram_ba(dram_ba),
   .dram_clk(dram_clk),
   .dram_cke(dram_cke)
  );


assign dram_dq = &dram_dqm ?  {SDRAM_DATA_WIDTH {1'bZ}} : dram_dq_out;
assign dram_dq_in = dram_dq;

bootloader
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
)
boot_loader_u0
(
.clk(clk_div8),
.rst_n(rst_sync_n),
.boot_mode(boot_mode),
.boot_mem_rd_en(boot_mem_rd_en),
.boot_mem_addr(boot_mem_addr),
.boot_mem_rd_data(boot_mem_rd_data),

.inst_mem_wr_en(inst_mem_wr_en),
.inst_mem_wr_data(inst_mem_wr_data),
.inst_mem_addr(inst_mem_addr)
);

mux_sram
#(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(ADDR_WIDTH)
)
   mux_sram_u0
(

   .boot_mode(boot_mode),
   .boot_mem_wr_en(inst_mem_wr_en),
   .boot_mem_addr(inst_mem_addr),
   .boot_mem_rd_data(inst_mem_wr_data),

   .inst_mem_wr_en(1'b0),
   .inst_mem_rd_en(inst_mem_rd_en_proc),
   .inst_mem_wr_data(32'd0),
   .inst_mem_rd_data(inst_mem_rd_data_proc),
   .inst_mem_addr(inst_mem_addr_proc),

   .sram_mem_wr_en(sram_mem_wr_en),
   .sram_mem_rd_en(sram_mem_rd_en),
   .sram_mem_wr_data(sram_mem_wr_data),
   .sram_mem_rd_data(sram_mem_rd_data),
   .sram_mem_addr(sram_mem_addr)
);

wire [19:0] sram_addr;
wire [31:0] sram_wr_data;
wire [31:0] sram_rd_data;

sram_fsm sram_fsm_u0(

    .clk(clk_div4),
    .rst_n(rst_sync_n),

    .wr_en(sram_mem_wr_en),
    .rd_en(sram_mem_rd_en),
    .wr_data(sram_mem_wr_data),
    .addr(sram_mem_addr),
    .rd_data(sram_mem_rd_data),

    .sram_ub_n(sram_ub_n),
    .sram_lb_n(sram_lb_n),
    .sram_ce_n(sram_ce_n),
    .sram_we_n(sram_we_n),
    .sram_oe_n(sram_oe_n),
    .sram_addr(sram_addr),
    .sram_wr_data(sram_wr_data),
    .sram_rd_data(sram_rd_data)
  );

sp_ram
#(
   .DATA_WIDTH(16),
   .ADDR_WIDTH(10)
)
sp_ram_u0
(
   .clk(clk_div4),
   .rd_ena(!sram_ce_n&sram_we_n),
   .wr_ena(!sram_ce_n&!sram_we_n),
   .address(sram_addr),
   .wr_data(sram_wr_data),
   .rd_data(sram_rd_data)
);

mt48lc8m16a2
  #(
    .data_bits(16),
    .addr_bits(SDRAM_ADDR_WIDTH)
  )
  sdram_memory_2
  (
    .Dq(dram_dq[31:16]),
    .Addr(dram_addr),
    .Ba(dram_ba),
    .Clk(clk_out),
    .Cke(dram_cke),
    .Cs_n(dram_cs_n),
    .Ras_n(dram_ras_n),
    .Cas_n(dram_cas_n),
    .We_n(dram_we_n),
    .Dqm(dram_dqm)
  );

mt48lc8m16a2
  #(
    .data_bits(16),
    .addr_bits(SDRAM_ADDR_WIDTH)
  )
  sdram_memory_1
  (
    .Dq(dram_dq[15:0]),
    .Addr(dram_addr),
    .Ba(dram_ba),
    .Clk(dram_clk),
    .Cke(dram_cke),
    .Cs_n(dram_cs_n),
    .Ras_n(dram_ras_n),
    .Cas_n(dram_cas_n),
    .We_n(dram_we_n),
    .Dqm(dram_dqm)
  );

rom
#(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(10)
)
rom_u0
(
   .clk(clk_div8),
   .rst_n(rst_sync_n),
   .rd_ena(boot_mem_rd_en),
   .address(boot_mem_addr),
   .data(boot_mem_rd_data)
);

initial begin
 clk = 0;
end

always begin
   #10  clk = ~clk;
end

initial begin
rst_n = 1;
#10;
rst_n = 0;
#30;
@(posedge clk);
#1
rst_n = 1;
end

endmodule
module tosco_tb_v2;



reg clk, rst_n;


localparam DATA_WIDTH = 32;
localparam INST_ADDR_WIDTH = 20;
localparam ADDR_WIDTH = 20;
localparam DATA_ADDR_WIDTH = 32;
localparam SRAM_ADDR_WIDTH = 20;
localparam SRAM_DATA_WIDTH = 16;
localparam SDRAM_DATA_WIDTH = 32;
localparam SDRAM_ADDR_WIDTH = 20;
localparam SDRAM_DQM_WIDTH = 4;
localparam SDRAM_BA_WIDTH = 2;

wire data_rd_en;
wire data_wr_en;
wire [DATA_WIDTH-1:0] data_read;
wire [DATA_WIDTH-1:0] data_write;

wire instr_rd_en;
wire [INST_ADDR_WIDTH-1:0] instr_addr;
wire [DATA_WIDTH-1:0] instruction;

wire boot_mem_rd_en;
wire inst_mem_wr_en;

wire [ADDR_WIDTH-1:0] data_addr;
wire [DATA_WIDTH-1:0] data_out;
wire [DATA_WIDTH-1:0] data_in;

wire  [SDRAM_DATA_WIDTH-1:0]  dram_dq;
wire  [SDRAM_DATA_WIDTH-1:0]  dram_dq_in;
wire  [SDRAM_DATA_WIDTH-1:0]  dram_dq_out;
wire [SDRAM_ADDR_WIDTH-1:0]  dram_addr;
wire [SDRAM_DQM_WIDTH-1:0]   dram_dqm;
wire         dram_we_n;
wire         dram_cas_n;
wire         dram_ras_n;
wire         dram_cs_n;
wire [SDRAM_BA_WIDTH-1:0]   dram_ba;
wire         dram_clk;
wire         dram_cke;


wire boot_mode;
wire boot_mem_wr_en;
wire [ADDR_WIDTH-1:0] boot_mem_addr;
wire [DATA_WIDTH-1:0] boot_mem_rd_data;
wire [DATA_WIDTH-1:0] boot_mem_wr_data;

wire inst_mem_rd_en;
wire [DATA_WIDTH-1:0] inst_mem_wr_data;
wire [DATA_WIDTH-1:0] inst_mem_rd_data;
wire [ADDR_WIDTH-1:0] inst_mem_addr;

wire sram_mem_wr_en;
wire sram_mem_rd_en;
wire [DATA_WIDTH-1:0] sram_mem_wr_data;
wire [DATA_WIDTH-1:0] sram_mem_rd_data;
wire [ADDR_WIDTH-1:0] sram_mem_addr;

wire inst_mem_rd_en_proc;
wire [19:0] inst_mem_addr_proc;
wire [31:0] inst_mem_rd_data_proc;
wire data_rd_en_proc;
wire data_wr_en_proc;
wire [19:0] data_addr_proc;
wire [31:0] data_read_proc;
wire [31:0] data_write_proc;

clk_rst_mngr
clk_rst_mngr_u0
   (
   .clk_in(clk),
   .rst_async_n(rst_n),
   .en_clk_div8(!boot_mode),
   .rst_sync_n(rst_sync_n),
   .clk_out(clk_out),
   .clk_div2(clk_div2),
   .clk_div4(clk_div4),
   .clk_div8(clk_div8),
   .clk_div8_proc(clk_div8_proc)
  );




dlx_processor
#(
   .DATA_WIDTH(DATA_WIDTH),
   .INST_ADDR_WIDTH(INST_ADDR_WIDTH),
   .DATA_ADDR_WIDTH(DATA_ADDR_WIDTH)
)
dlx_processor_u0
(
   .clk(clk_div8_proc),
   .rst_n(rst_sync_n),

   .instr_rd_en(inst_mem_rd_en_proc),
   .instr_addr(inst_mem_addr_proc),
   .instruction(inst_mem_rd_data_proc),

   .data_rd_en(data_rd_en_proc),
   .data_wr_en(data_wr_en_proc),
   .data_addr(data_addr_proc),
   .data_read(data_read_proc),
   .data_write(data_write_proc)
);

data_memory_controll
  #(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(ADDR_WIDTH),
   .SDRAM_DATA_WIDTH(SDRAM_DATA_WIDTH),
   .SDRAM_ADDR_WIDTH(SDRAM_ADDR_WIDTH)

  )
  memory_controll
  (
   .clk(clk_out),
   .rst_n(rst_sync_n),
   .data_rd_en(data_rd_en_proc),
   .data_wr_en(data_wr_en_proc),
   .data_addr(data_addr_proc),
   .data_out(data_read_proc),
   .data_in(data_write_proc),

   .dram_dq_in(dram_dq_in),
   .dram_dq_out(dram_dq_out),
   .dram_addr(dram_addr),
   .dram_dqm(dram_dqm),
   .dram_we_n(dram_we_n),
   .dram_cas_n(dram_cas_n),
   .dram_ras_n(dram_ras_n),
   .dram_cs_n(dram_cs_n),
   .dram_ba(dram_ba),
   .dram_clk(dram_clk),
   .dram_cke(dram_cke)
  );


assign dram_dq = &dram_dqm ?  {SDRAM_DATA_WIDTH {1'bZ}} : dram_dq_out;
assign dram_dq_in = dram_dq;

bootloader
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
)
boot_loader_u0
(
.clk(clk_div8),
.rst_n(rst_sync_n),
.boot_mode(boot_mode),
.boot_mem_rd_en(boot_mem_rd_en),
.boot_mem_addr(boot_mem_addr),
.boot_mem_rd_data(boot_mem_rd_data),

.inst_mem_wr_en(inst_mem_wr_en),
.inst_mem_wr_data(inst_mem_wr_data),
.inst_mem_addr(inst_mem_addr)
);

mux_sram
#(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(ADDR_WIDTH)
)
   mux_sram_u0
(

   .boot_mode(boot_mode),
   .boot_mem_wr_en(inst_mem_wr_en),
   .boot_mem_addr(inst_mem_addr),
   .boot_mem_rd_data(inst_mem_wr_data),

   .inst_mem_wr_en(1'b0),
   .inst_mem_rd_en(inst_mem_rd_en_proc),
   .inst_mem_wr_data(32'd0),
   .inst_mem_rd_data(inst_mem_rd_data_proc),
   .inst_mem_addr(inst_mem_addr_proc),

   .sram_mem_wr_en(sram_mem_wr_en),
   .sram_mem_rd_en(sram_mem_rd_en),
   .sram_mem_wr_data(sram_mem_wr_data),
   .sram_mem_rd_data(sram_mem_rd_data),
   .sram_mem_addr(sram_mem_addr)
);

wire [19:0] sram_addr;
wire [31:0] sram_wr_data;
wire [31:0] sram_rd_data;

sram_fsm sram_fsm_u0(

    .clk(clk_div4),
    .rst_n(rst_sync_n),

    .wr_en(sram_mem_wr_en),
    .rd_en(sram_mem_rd_en),
    .wr_data(sram_mem_wr_data),
    .addr(sram_mem_addr),
    .rd_data(sram_mem_rd_data),

    .sram_ub_n(sram_ub_n),
    .sram_lb_n(sram_lb_n),
    .sram_ce_n(sram_ce_n),
    .sram_we_n(sram_we_n),
    .sram_oe_n(sram_oe_n),
    .sram_addr(sram_addr),
    .sram_wr_data(sram_wr_data),
    .sram_rd_data(sram_rd_data)
  );

sp_ram
#(
   .DATA_WIDTH(16),
   .ADDR_WIDTH(10)
)
sp_ram_u0
(
   .clk(clk_div4),
   .rd_ena(!sram_ce_n&sram_we_n),
   .wr_ena(!sram_ce_n&!sram_we_n),
   .address(sram_addr),
   .wr_data(sram_wr_data),
   .rd_data(sram_rd_data)
);

mt48lc8m16a2
  #(
    .data_bits(16),
    .addr_bits(SDRAM_ADDR_WIDTH)
  )
  sdram_memory_2
  (
    .Dq(dram_dq[31:16]),
    .Addr(dram_addr),
    .Ba(dram_ba),
    .Clk(clk_out),
    .Cke(dram_cke),
    .Cs_n(dram_cs_n),
    .Ras_n(dram_ras_n),
    .Cas_n(dram_cas_n),
    .We_n(dram_we_n),
    .Dqm(dram_dqm)
  );

mt48lc8m16a2
  #(
    .data_bits(16),
    .addr_bits(SDRAM_ADDR_WIDTH)
  )
  sdram_memory_1
  (
    .Dq(dram_dq[15:0]),
    .Addr(dram_addr),
    .Ba(dram_ba),
    .Clk(dram_clk),
    .Cke(dram_cke),
    .Cs_n(dram_cs_n),
    .Ras_n(dram_ras_n),
    .Cas_n(dram_cas_n),
    .We_n(dram_we_n),
    .Dqm(dram_dqm)
  );

rom
#(
   .DATA_WIDTH(DATA_WIDTH),
   .ADDR_WIDTH(10)
)
rom_u0
(
   .clk(clk_div8),
   .rst_n(rst_sync_n),
   .rd_ena(boot_mem_rd_en),
   .address(boot_mem_addr),
   .data(boot_mem_rd_data)
);

initial begin
 clk = 0;
end

always begin
   #10  clk = ~clk;
end

initial begin
rst_n = 1;
#10;
rst_n = 0;
#30;
@(posedge clk);
#1
rst_n = 1;
end

endmodule