data/full_repos/permissive/136510272/projects/version.1.zx80/port.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/port.v:22: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'vga_border\' generates 3 bits.\n                                                                                      : ... In instance port\n    (addr == 16\'h00FE) ? vga_border : 1\'b0;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/port.v:22: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance port\n    (addr == 16\'h00FE) ? vga_border : 1\'b0;\n                       ^\n%Error: Exiting due to 2 warning(s)\n'
module port(

    input  wire        clock,
    input  wire [15:0] addr,
    input  wire [7:0]  data_in,
    output wire [7:0]  data_out,
    
    output reg [2:0]   vga_border
    
);

initial begin

    vga_border = 3'b111;

end


assign data_out = 


    (addr == 16'h00FE) ? vga_border : 1'b0;



always @(negedge clock) begin

    case (addr)


        16'h00FE: vga_border[2:0] <= data_in[2:0];

    endcase

end

endmodule
module port(

    input  wire        clock,
    input  wire [15:0] addr,
    input  wire [7:0]  data_in,
    output wire [7:0]  data_out,
    
    output reg [2:0]   vga_border
    
);


initial begin

    vga_border = 3'b111;

end


assign data_out = 


    (addr == 16'h00FE) ? vga_border : 1'b0;



always @(negedge clock) begin

    case (addr)


        16'h00FE: vga_border[2:0] <= data_in[2:0];

    endcase

end

endmodule