data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/mult_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/mult_sim.v:28: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                       : ... Top module \'qlal4s3_mult_32x32_cell\'\nmodule qlal4s3_mult_32x32_cell (\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                                       : ... Top module \'qlal4s3_mult_16x16_cell\'\nmodule qlal4s3_mult_16x16_cell (\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                                       : ... Top module \'qlal4s3_mult_cell_macro\'\nmodule qlal4s3_mult_cell_macro (\n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/220229160/ql-qlf-plugin/pp3/mult_sim.v:58: Signal definition not found, creating implicitly: \'valid_int\'\n  assign valid_int = Valid;\n         ^~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n'
module signed_mult (
    A,
    B,
    Valid,
    C
);

  parameter WIDTH = 32;
  parameter CWIDTH = 2 * WIDTH;

  input [WIDTH-1:0] A, B;
  input Valid;
  output [CWIDTH-1:0] C;

  reg signed [WIDTH-1:0] A_q, B_q;
  wire signed [CWIDTH-1:0] C_int;

  assign C_int = A_q * B_q;
  assign valid_int = Valid;
  assign C = C_int;

  always @(*) if (valid_int == 1'b1) A_q <= A;

  always @(*) if (valid_int == 1'b1) B_q <= B;

endmodule
module signed_mult (
    A,
    B,
    Valid,
    C
);


  parameter WIDTH = 32;
  parameter CWIDTH = 2 * WIDTH;

  input [WIDTH-1:0] A, B;
  input Valid;
  output [CWIDTH-1:0] C;

  reg signed [WIDTH-1:0] A_q, B_q;
  wire signed [CWIDTH-1:0] C_int;

  assign C_int = A_q * B_q;
  assign valid_int = Valid;
  assign C = C_int;

  always @(*) if (valid_int == 1'b1) A_q <= A;

  always @(*) if (valid_int == 1'b1) B_q <= B;

endmodule