data/full_repos/permissive/18921956/HardwareLab/Lab6/clock_divisor.v
data/verilator_xmls/add61e3b-0340-493c-80a7-118a7296b389.xml
module clock_divisor(clk15, clk);
	input clk;
	output clk15;

	reg [14:0] num;
	wire [14:0] next_num;

	always @(posedge clk) begin
		num <= next_num;
	end

	assign next_num = num + 1;
	assign clk15 = num[14];
endmodule
module clock_divisor(clk15, clk);

	input clk;
	output clk15;

	reg [14:0] num;
	wire [14:0] next_num;

	always @(posedge clk) begin
		num <= next_num;
	end

	assign next_num = num + 1;
	assign clk15 = num[14];
endmodule