data/full_repos/permissive/125592111/verilog/IF_ID_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/125592111/verilog/IF_ID_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n always #(tck/2) clk <= ~clk;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/125592111/verilog/IF_ID_tb.v:27: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("ifid_ah.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/IF_ID_tb.v:28: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(-1, dut);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/IF_ID_tb.v:29: Unsupported or unknown PLI call: $monitor\n  $monitor("%b", InsOut);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/IF_ID_tb.v:44: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n  PC_In <= $random(seed) ;\n           ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/125592111/verilog/IF_ID_tb.v:44: ../V3Ast.cpp:358: Null item passed to setOp1p\n  PC_In <= $random(seed) ;\n        ^~\n                        ... See the manual and https://verilator.org for more assistance.\n'
module IF_ID_tb();

	parameter tck = 10;

	reg [31:0] InsIn, PC_In;
	reg clk, reset, IFID_write, IF_flush;
	wire [31:0] InsOut, PC_out;

	IF_ID dut(	
				.InsIn(InsIn),
				.PC_In(PC_In),
				.InsOut(InsOut),
				.PC_out(PC_out),
				.IFID_write(IFID_write),
				.IF_flush(IF_flush),
				.clk(clk),
				.reset(reset)
			);
			
	integer num_iter = 0 ;
	integer seed = 1 ;
	always #(tck/2) clk <= ~clk;

	initial begin
		$dumpfile("ifid_ah.vcd");
		$dumpvars(-1, dut);
		$monitor("%b", InsOut);
	end
							


	initial begin
		clk = 0 ; 
		reset = 0 ;
		InsIn = 0 ;
		PC_In = 0 ;
		IFID_write = 1 ;
		IF_flush = 0 ;
	end
	
	always @(negedge clk) begin
		PC_In <= $random(seed) ;
		InsIn <= $random(seed) ;
		num_iter = num_iter+1 ;

		if(num_iter == 10) IF_flush <= 1;
		if(num_iter == 11) IF_flush <= 0;
		if(num_iter == 5) IFID_write <= 0;
		if(num_iter == 6) IFID_write <= 1;

		if (num_iter > 999) $finish;
	end

endmodule
module IF_ID_tb();


	parameter tck = 10;

	reg [31:0] InsIn, PC_In;
	reg clk, reset, IFID_write, IF_flush;
	wire [31:0] InsOut, PC_out;

	IF_ID dut(	
				.InsIn(InsIn),
				.PC_In(PC_In),
				.InsOut(InsOut),
				.PC_out(PC_out),
				.IFID_write(IFID_write),
				.IF_flush(IF_flush),
				.clk(clk),
				.reset(reset)
			);
			
	integer num_iter = 0 ;
	integer seed = 1 ;
	always #(tck/2) clk <= ~clk;

	initial begin
		$dumpfile("ifid_ah.vcd");
		$dumpvars(-1, dut);
		$monitor("%b", InsOut);
	end
							


	initial begin
		clk = 0 ; 
		reset = 0 ;
		InsIn = 0 ;
		PC_In = 0 ;
		IFID_write = 1 ;
		IF_flush = 0 ;
	end
	
	always @(negedge clk) begin
		PC_In <= $random(seed) ;
		InsIn <= $random(seed) ;
		num_iter = num_iter+1 ;

		if(num_iter == 10) IF_flush <= 1;
		if(num_iter == 11) IF_flush <= 0;
		if(num_iter == 5) IFID_write <= 0;
		if(num_iter == 6) IFID_write <= 1;

		if (num_iter > 999) $finish;
	end

endmodule