data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/002_combinational_unstructured/isqrt.v
 line:17: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/002_combinational_unstructured/isqrt.v:13: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h40000000\' generates 31 bits.\n                                                                                                                                                 : ... In instance isqrt\n        m  = 31\'h4000_0000;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module isqrt
(
    input      [31:0] x,
    output reg [15:0] y
);

    reg [31:0] m, tx, ty, b;

    always @*
    begin
        m  = 31'h4000_0000;
        tx = x;
        ty = 0;
    
        repeat (16)
        begin
            b  = ty |  m;
            ty = ty >> 1;
            
            if (tx >= b)
            begin
                tx = tx - b;
                ty = ty | m;
            end
            
            m = m >> 2;
        end

        y = ty [15:0];
    end

endmodule
module isqrt
(
    input      [31:0] x,
    output reg [15:0] y
);


    reg [31:0] m, tx, ty, b;

    always @*
    begin
        m  = 31'h4000_0000;
        tx = x;
        ty = 0;
    
        repeat (16)
        begin
            b  = ty |  m;
            ty = ty >> 1;
            
            if (tx >= b)
            begin
                tx = tx - b;
                ty = ty | m;
            end
            
            m = m >> 2;
        end

        y = ty [15:0];
    end

endmodule