data/full_repos/permissive/143278/ivltests/sdf6.v
 line:17: before: "if"
1: b'%Error: data/full_repos/permissive/143278/ivltests/sdf6.v:30: Unsupported or unknown PLI call: $monitor\n    $monitor($time,, "d=%b, clk=%b, set=%b, clr=%b, q=%b",\n    ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/sdf6.v:30: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    $monitor($time,, "d=%b, clk=%b, set=%b, clr=%b, q=%b",\n                   ^\n%Error: data/full_repos/permissive/143278/ivltests/sdf6.v:32: Unsupported or unknown PLI call: $sdf_annotate\n    $sdf_annotate("ivltests/sdf6.sdf");\n    ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdf6.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 d = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdf6.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10 set = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdf6.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10 set = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdf6.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10 clr = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdf6.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 clr = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdf6.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdf6.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 d = 0;\n    ^\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  reg d, clk, set, clr;

  dff dut(q, d, clk, ~set, ~clr);

  initial begin
    d=0; clk=0; set=0; clr=0;
    $monitor($time,, "d=%b, clk=%b, set=%b, clr=%b, q=%b",
             d, clk, set, clr, q);
    $sdf_annotate("ivltests/sdf6.sdf");
    #10 d = 1;
    #10 set = 1;
    #10 set = 0;
    #10 clr = 1;
    #10 clr = 0;
    #10 clk = 1;
    #10 d = 0;
  end
endmodule
module test;

  reg d, clk, set, clr;

  dff dut(q, d, clk, ~set, ~clr);

  initial begin
    d=0; clk=0; set=0; clr=0;
    $monitor($time,, "d=%b, clk=%b, set=%b, clr=%b, q=%b",
             d, clk, set, clr, q);
    $sdf_annotate("ivltests/sdf6.sdf");
    #10 d = 1;
    #10 set = 1;
    #10 set = 0;
    #10 clr = 1;
    #10 clr = 0;
    #10 clk = 1;
    #10 d = 0;
  end
endmodule