data/full_repos/permissive/110151336/lab_05/src/09_full_adder/common/full_adder.v
data/verilator_xmls/173ca92a-53dd-45b9-9b88-1cb8d10fbca4.xml
module full_adder
(
    input wire  x, y, carry_in,
	output wire z, carry_out
);
    assign {carry_out, z} = x + y + carry_in;
endmodule
module full_adder
(
    input wire  x, y, carry_in,
	output wire z, carry_out
);

    assign {carry_out, z} = x + y + carry_in;
endmodule