data/full_repos/permissive/15946916/Lab6/lab6_5dec.v
 line:76: before: "$"
1: b'%Error: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:58: Unsupported or unknown PLI call: $monitor\n        $monitor ($time,"\\ta=%b\\tb=%b\\tcin=%b\\tsum=%b\\tcarry=%b",a,b,cin, S, Cout);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #1 \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #1 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #1 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_5dec.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module full_adder_test();
    reg    a, b, cin;
    wire   S, Cout;

    full_adder_dec test(S,Cout,a,b,cin);

    initial begin
        $monitor ($time,"\ta=%b\tb=%b\tcin=%b\tsum=%b\tcarry=%b",a,b,cin, S, Cout);
		
        a = 0; b = 0; cin=0;
        #1 
         a = 0; b = 0; cin=1;
        #1
         a = 0; b = 1; cin=0;
        #1
         a = 0; b = 1; cin=1;
        #1 
		 a = 1; b = 0; cin=0;
        #1 
         a = 1; b = 0; cin=1;
        #1
         a = 1; b = 1; cin=0;
        #1
         a = 1; b = 1; cin=1;
		#1
        $finish;
    end
endmodule
module full_adder_test();

    reg    a, b, cin;
    wire   S, Cout;

    full_adder_dec test(S,Cout,a,b,cin);

    initial begin
        $monitor ($time,"\ta=%b\tb=%b\tcin=%b\tsum=%b\tcarry=%b",a,b,cin, S, Cout);
		
        a = 0; b = 0; cin=0;
        #1 
         a = 0; b = 0; cin=1;
        #1
         a = 0; b = 1; cin=0;
        #1
         a = 0; b = 1; cin=1;
        #1 
		 a = 1; b = 0; cin=0;
        #1 
         a = 1; b = 0; cin=1;
        #1
         a = 1; b = 1; cin=0;
        #1
         a = 1; b = 1; cin=1;
		#1
        $finish;
    end
endmodule