data/full_repos/permissive/108216748/system/sha2.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/108216748/system/sha2.v:29: Multiple top level modules\n                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                        : ... Top module \'sha2_round\'\nmodule sha2_round #(\n       ^~~~~~~~~~\n                                                                        : ... Top module \'Ch\'\nmodule Ch #(parameter WORDSIZE=0) (\n       ^~\n                                                                        : ... Top module \'Maj\'\nmodule Maj #(parameter WORDSIZE=0) (\n       ^~~\n                                                                        : ... Top module \'W_machine\'\nmodule W_machine #(parameter WORDSIZE=1) (\n       ^~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:41: Little bit endian vector: MSB < LSB of bit range: -1:0\n    input wire [WORDSIZE-1:0] x, y, z,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:42: Little bit endian vector: MSB < LSB of bit range: -1:0\n    output wire [WORDSIZE-1:0] Maj\n                ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:30: Little bit endian vector: MSB < LSB of bit range: -1:0\n    input wire [WORDSIZE-1:0] x, y, z,\n               ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:31: Little bit endian vector: MSB < LSB of bit range: -1:0\n    output wire [WORDSIZE-1:0] Ch\n                ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:7: Little bit endian vector: MSB < LSB of bit range: -1:0\n    input [WORDSIZE-1:0] Kj, Wj,\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:8: Little bit endian vector: MSB < LSB of bit range: -1:0\n    input [WORDSIZE-1:0] a_in, b_in, c_in, d_in, e_in, f_in, g_in, h_in,\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:9: Little bit endian vector: MSB < LSB of bit range: -1:0\n    input [WORDSIZE-1:0] Ch_e_f_g, Maj_a_b_c, S0_a, S1_e,\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:10: Little bit endian vector: MSB < LSB of bit range: -1:0\n    output [WORDSIZE-1:0] a_out, b_out, c_out, d_out, e_out, f_out, g_out, h_out\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:13: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [WORDSIZE-1:0] T1 = h_in + S1_e + Ch_e_f_g + Kj + Wj;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/108216748/system/sha2.v:14: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [WORDSIZE-1:0] T2 = S0_a + Maj_a_b_c;\n     ^\n%Error: Exiting due to 11 warning(s)\n'
module Maj #(parameter WORDSIZE=0) (
    input wire [WORDSIZE-1:0] x, y, z,
    output wire [WORDSIZE-1:0] Maj
    );

assign Maj = (x & y) ^ (x & z) ^ (y & z);

endmodule
module Maj #(parameter WORDSIZE=0) (
    input wire [WORDSIZE-1:0] x, y, z,
    output wire [WORDSIZE-1:0] Maj
    );


assign Maj = (x & y) ^ (x & z) ^ (y & z);

endmodule