data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10 a=\'b00010000;b=\'b00011100;c0=\'b0;s0=\'b0;s1=\'b1;m=\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10 a=\'b00010000;b=\'b00011100;c0=\'b0;s0=\'b1;s1=\'b0;m=\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10 a=\'b00010000;b=\'b00011100;c0=\'b0;s0=\'b1;s1=\'b1;m=\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10 a=\'b00010000;b=\'b00011100;c0=\'b0;s0=\'b0;s1=\'b0;m=\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 a=\'b00010000;b=\'b00011100;c0=\'b0;s0=\'b0;s1=\'b1;m=\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10 a=\'b00010000;b=\'b00011100;c0=\'b0;s0=\'b1;s1=\'b0;m=\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10 a=\'b00010000;b=\'b00011100;c0=\'b0;s0=\'b1;s1=\'b1;m=\'b1;    \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #10 a=\'b00010000;b=\'b00011100;c0=\'b1;s0=\'b0;s1=\'b0;m=\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10 a=\'b00010000;b=\'b00011100;c0=\'b1;s0=\'b0;s1=\'b1;m=\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #10 a=\'b00010000;b=\'b00011100;c0=\'b1;s0=\'b1;s1=\'b0;m=\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #10 a=\'b00010000;b=\'b00011100;c0=\'b1;s0=\'b1;s1=\'b1;m=\'b1;\n        ^\n%Error: data/full_repos/permissive/211316121/lab4/sim_1/new/sim_ALU.v:35: Cannot find file containing module: \'ALU\'\n    ALU sim(a,b,c0,s0,s1,m,s,c8);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/lab4/sim_1/new,data/full_repos/permissive/211316121/ALU\n             data/full_repos/permissive/211316121/lab4/sim_1/new,data/full_repos/permissive/211316121/ALU.v\n             data/full_repos/permissive/211316121/lab4/sim_1/new,data/full_repos/permissive/211316121/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_ALU(

    );
    reg [7:0]a;
    reg [7:0]b;
    reg c0;
    reg s0;
    reg s1;
    reg m;
    wire [7:0] s;
    wire c8;
    
    ALU sim(a,b,c0,s0,s1,m,s,c8);
    
    initial
        begin
            a='b00010000;b='b00011100;c0='b0;s0='b0;s1='b0;m='b0;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b0;s1='b1;m='b0;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b1;s1='b0;m='b0;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b1;s1='b1;m='b0;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b0;s1='b0;m='b1;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b0;s1='b1;m='b1;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b1;s1='b0;m='b1;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b1;s1='b1;m='b1;    
        #10 a='b00010000;b='b00011100;c0='b1;s0='b0;s1='b0;m='b1;
        #10 a='b00010000;b='b00011100;c0='b1;s0='b0;s1='b1;m='b1;
        #10 a='b00010000;b='b00011100;c0='b1;s0='b1;s1='b0;m='b1;
        #10 a='b00010000;b='b00011100;c0='b1;s0='b1;s1='b1;m='b1;
        end 
    
endmodule
module sim_ALU(

    );

    reg [7:0]a;
    reg [7:0]b;
    reg c0;
    reg s0;
    reg s1;
    reg m;
    wire [7:0] s;
    wire c8;
    
    ALU sim(a,b,c0,s0,s1,m,s,c8);
    
    initial
        begin
            a='b00010000;b='b00011100;c0='b0;s0='b0;s1='b0;m='b0;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b0;s1='b1;m='b0;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b1;s1='b0;m='b0;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b1;s1='b1;m='b0;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b0;s1='b0;m='b1;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b0;s1='b1;m='b1;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b1;s1='b0;m='b1;
        #10 a='b00010000;b='b00011100;c0='b0;s0='b1;s1='b1;m='b1;    
        #10 a='b00010000;b='b00011100;c0='b1;s0='b0;s1='b0;m='b1;
        #10 a='b00010000;b='b00011100;c0='b1;s0='b0;s1='b1;m='b1;
        #10 a='b00010000;b='b00011100;c0='b1;s0='b1;s1='b0;m='b1;
        #10 a='b00010000;b='b00011100;c0='b1;s0='b1;s1='b1;m='b1;
        end 
    
endmodule