data/full_repos/permissive/18477150/testsuite/mg_sim/lib/sonic_hard_ip_custom.sv
data/verilator_xmls/e995f9d3-8279-40b6-b0a4-4ded30c71d03.xml
module sonic_hard_ip_custom (

   tx_st_data_r, tx_st_sop_r, tx_st_eop_r, tx_st_valid_r, tx_st_err_r,
   tx_st_empty_r, tx_st_be, tx_st_bardec,

   clk_in, rstn, tx_st_data, tx_st_sop, tx_st_eop, tx_st_valid,
   tx_st_err, tx_st_empty
   ) ;

   input         clk_in;   
   input         rstn;
   input [127:0] tx_st_data;
   input 	 tx_st_sop;
   input 	 tx_st_eop;
   input 	 tx_st_valid;
   input 	 tx_st_err;
   input 	 tx_st_empty;
   
   output [127:0] tx_st_data_r;
   output 	  tx_st_sop_r;
   output 	  tx_st_eop_r;
   output 	  tx_st_valid_r;
   output 	  tx_st_err_r;
   output 	  tx_st_empty_r;
   output [15:0]  tx_st_be;
   output [7:0]   tx_st_bardec;

   reg [15:0] 	  tx_st_be;
   reg [127:0] 	  tx_st_data_r;
   reg 		  tx_st_sop_r;
   reg 		  tx_st_eop_r;
   reg 		  tx_st_valid_r;
   reg 		  tx_st_err_r;
   reg 		  tx_st_empty_r;
   reg [7:0] 	  tx_st_bardec;
   reg 		  tx_st_sop_p0;
   reg 		  tx_st_sop_p1;
   reg 		  tx_st_eop_p0;
   reg 		  tx_st_eop_p1;
      
   wire 	 ctrltx_3dw;
   wire [9:0] 	 ctrltx_length;
   wire 	 ctrltx_payload;
   reg [9:0] 	 ctrltx_count_length_dword;
   wire 	 ctrltx_single_cycle;
   reg [9:0] 	 ctrltx_length_reg;
   reg 		 ctrltx_single_cycle_reg;
   reg 		 ctrltx_payload_reg;
   reg 		 ctrltx_3dw_reg;
   reg 		 ctrltx_dw_addroffset_reg;
   reg [15:0] 	 data_tail_be_mask;
      
   assign ctrltx_single_cycle   =  (tx_st_sop==1'b1) ? ((tx_st_eop==1'b1) ? 1'b1 :1'b0) : ctrltx_single_cycle_reg;

   assign ctrltx_payload        = ((tx_st_sop==1'b1)&&(tx_st_data[30]==1'b1)) ? 1'b1  : ctrltx_payload_reg;

   assign ctrltx_3dw            = ((tx_st_sop==1'b1)&&(tx_st_data[29]==1'b0))?1'b1:ctrltx_3dw_reg;

   assign ctrltx_length[9:0]    = (tx_st_sop==1'b1) ?  ((tx_st_data[30]==1'b1) ? tx_st_data[9:0]: 10'h0) : ctrltx_length_reg[9:0];

   always @ (posedge clk_in) begin

      if ((tx_st_sop_p0==1'b1) & (ctrltx_3dw==1'b1)) begin
	 if (ctrltx_single_cycle == 1'b1)
	   tx_st_be <= 16'hffff;
	 else
	   tx_st_be <= 16'hfff;
      end
      else if (ctrltx_3dw==1'b1) begin
	 tx_st_be <= data_tail_be_mask;
      end
      else if ((tx_st_sop_p0==1'b1) & (ctrltx_3dw==1'b0))  begin
	 tx_st_be <= 16'hffff;
      end
      else if (ctrltx_3dw==1'b0)  begin
	 tx_st_be <= data_tail_be_mask;
      end
   end

   always @ (posedge clk_in) begin


      if (tx_st_data[95:64] >= 32'h0024_0000 && tx_st_sop == 1'b1) begin
	 tx_st_bardec <= 8'b0000_1000;
      end

      else if (tx_st_data[95:64] >= 32'h0020_0000 && tx_st_sop == 1'b1) begin
	 tx_st_bardec <= 8'b0000_0100;
      end
   end
   
   always @(posedge clk_in) begin
      if (rstn == 1'b0) begin
         ctrltx_count_length_dword  <= 0;
      end
      else begin

         if (tx_st_sop_p0==1'b1) begin
            if (ctrltx_payload==1'b1) begin
	       ctrltx_count_length_dword <= ctrltx_length;
            end
            else begin
               ctrltx_count_length_dword <= 0;
            end
         end
         else if ((ctrltx_count_length_dword>3))
           ctrltx_count_length_dword <= ctrltx_count_length_dword - 4;
      end
   end

   always @(posedge clk_in) begin
      if (rstn == 1'b0) begin
         ctrltx_single_cycle_reg   <= 1'b0;
         ctrltx_payload_reg        <= 1'b0;
         ctrltx_3dw_reg            <= 1'b0;
         ctrltx_length_reg         <= 0;
      end
      else begin
         ctrltx_single_cycle_reg   <= ctrltx_single_cycle;
         ctrltx_length_reg         <= ctrltx_length;

          if (tx_st_sop_p0==1'b1) begin
              ctrltx_3dw_reg           <= (tx_st_data[29]==1'b0) ? 1'b1 : 1'b0;
              ctrltx_payload_reg       <= (tx_st_data[30]==1'b1) ? 1'b1 : 1'b0;
           end
          else if (((ctrltx_single_cycle==1'b1))||
                    ((ctrltx_single_cycle==1'b0)&&(tx_st_eop_p0==1'b1))) begin
              ctrltx_3dw_reg           <=1'b0;
              ctrltx_payload_reg       <=1'b0;
          end

      end
   end
   
   assign tx_st_sop_p0 = (tx_st_sop==1'b1) ? 1'b1 : 1'b0;
   assign tx_st_eop_p0 = (tx_st_eop==1'b1) ? 1'b1 : 1'b0;

   always @ (posedge clk_in) begin
      tx_st_sop_p1 <= tx_st_sop_p0;
      tx_st_eop_p1 <= tx_st_eop_p0;

      tx_st_valid_r <= tx_st_valid;
      tx_st_err_r <= tx_st_err;
      tx_st_sop_r <= tx_st_sop;
      tx_st_eop_r <= tx_st_eop;
      tx_st_data_r <= tx_st_data;
      tx_st_empty_r <= tx_st_empty;
   end
   
   always @ (*) begin

      if (ctrltx_count_length_dword[9:2] > 0) begin
         data_tail_be_mask = 16'hffff;
      end
      else begin
         case (ctrltx_count_length_dword[1:0])
           2'b00: data_tail_be_mask = 16'h0000;
           2'b01: data_tail_be_mask = 16'h000f;
           2'b10: data_tail_be_mask = 16'h00ff;
           2'b11: data_tail_be_mask = 16'h0fff;
         endcase
      end
   end
endmodule
module sonic_hard_ip_custom (

   tx_st_data_r, tx_st_sop_r, tx_st_eop_r, tx_st_valid_r, tx_st_err_r,
   tx_st_empty_r, tx_st_be, tx_st_bardec,

   clk_in, rstn, tx_st_data, tx_st_sop, tx_st_eop, tx_st_valid,
   tx_st_err, tx_st_empty
   ) ;


   input         clk_in;   
   input         rstn;
   input [127:0] tx_st_data;
   input 	 tx_st_sop;
   input 	 tx_st_eop;
   input 	 tx_st_valid;
   input 	 tx_st_err;
   input 	 tx_st_empty;
   
   output [127:0] tx_st_data_r;
   output 	  tx_st_sop_r;
   output 	  tx_st_eop_r;
   output 	  tx_st_valid_r;
   output 	  tx_st_err_r;
   output 	  tx_st_empty_r;
   output [15:0]  tx_st_be;
   output [7:0]   tx_st_bardec;

   reg [15:0] 	  tx_st_be;
   reg [127:0] 	  tx_st_data_r;
   reg 		  tx_st_sop_r;
   reg 		  tx_st_eop_r;
   reg 		  tx_st_valid_r;
   reg 		  tx_st_err_r;
   reg 		  tx_st_empty_r;
   reg [7:0] 	  tx_st_bardec;
   reg 		  tx_st_sop_p0;
   reg 		  tx_st_sop_p1;
   reg 		  tx_st_eop_p0;
   reg 		  tx_st_eop_p1;
      
   wire 	 ctrltx_3dw;
   wire [9:0] 	 ctrltx_length;
   wire 	 ctrltx_payload;
   reg [9:0] 	 ctrltx_count_length_dword;
   wire 	 ctrltx_single_cycle;
   reg [9:0] 	 ctrltx_length_reg;
   reg 		 ctrltx_single_cycle_reg;
   reg 		 ctrltx_payload_reg;
   reg 		 ctrltx_3dw_reg;
   reg 		 ctrltx_dw_addroffset_reg;
   reg [15:0] 	 data_tail_be_mask;
      
   assign ctrltx_single_cycle   =  (tx_st_sop==1'b1) ? ((tx_st_eop==1'b1) ? 1'b1 :1'b0) : ctrltx_single_cycle_reg;

   assign ctrltx_payload        = ((tx_st_sop==1'b1)&&(tx_st_data[30]==1'b1)) ? 1'b1  : ctrltx_payload_reg;

   assign ctrltx_3dw            = ((tx_st_sop==1'b1)&&(tx_st_data[29]==1'b0))?1'b1:ctrltx_3dw_reg;

   assign ctrltx_length[9:0]    = (tx_st_sop==1'b1) ?  ((tx_st_data[30]==1'b1) ? tx_st_data[9:0]: 10'h0) : ctrltx_length_reg[9:0];

   always @ (posedge clk_in) begin

      if ((tx_st_sop_p0==1'b1) & (ctrltx_3dw==1'b1)) begin
	 if (ctrltx_single_cycle == 1'b1)
	   tx_st_be <= 16'hffff;
	 else
	   tx_st_be <= 16'hfff;
      end
      else if (ctrltx_3dw==1'b1) begin
	 tx_st_be <= data_tail_be_mask;
      end
      else if ((tx_st_sop_p0==1'b1) & (ctrltx_3dw==1'b0))  begin
	 tx_st_be <= 16'hffff;
      end
      else if (ctrltx_3dw==1'b0)  begin
	 tx_st_be <= data_tail_be_mask;
      end
   end

   always @ (posedge clk_in) begin


      if (tx_st_data[95:64] >= 32'h0024_0000 && tx_st_sop == 1'b1) begin
	 tx_st_bardec <= 8'b0000_1000;
      end

      else if (tx_st_data[95:64] >= 32'h0020_0000 && tx_st_sop == 1'b1) begin
	 tx_st_bardec <= 8'b0000_0100;
      end
   end
   
   always @(posedge clk_in) begin
      if (rstn == 1'b0) begin
         ctrltx_count_length_dword  <= 0;
      end
      else begin

         if (tx_st_sop_p0==1'b1) begin
            if (ctrltx_payload==1'b1) begin
	       ctrltx_count_length_dword <= ctrltx_length;
            end
            else begin
               ctrltx_count_length_dword <= 0;
            end
         end
         else if ((ctrltx_count_length_dword>3))
           ctrltx_count_length_dword <= ctrltx_count_length_dword - 4;
      end
   end

   always @(posedge clk_in) begin
      if (rstn == 1'b0) begin
         ctrltx_single_cycle_reg   <= 1'b0;
         ctrltx_payload_reg        <= 1'b0;
         ctrltx_3dw_reg            <= 1'b0;
         ctrltx_length_reg         <= 0;
      end
      else begin
         ctrltx_single_cycle_reg   <= ctrltx_single_cycle;
         ctrltx_length_reg         <= ctrltx_length;

          if (tx_st_sop_p0==1'b1) begin
              ctrltx_3dw_reg           <= (tx_st_data[29]==1'b0) ? 1'b1 : 1'b0;
              ctrltx_payload_reg       <= (tx_st_data[30]==1'b1) ? 1'b1 : 1'b0;
           end
          else if (((ctrltx_single_cycle==1'b1))||
                    ((ctrltx_single_cycle==1'b0)&&(tx_st_eop_p0==1'b1))) begin
              ctrltx_3dw_reg           <=1'b0;
              ctrltx_payload_reg       <=1'b0;
          end

      end
   end
   
   assign tx_st_sop_p0 = (tx_st_sop==1'b1) ? 1'b1 : 1'b0;
   assign tx_st_eop_p0 = (tx_st_eop==1'b1) ? 1'b1 : 1'b0;

   always @ (posedge clk_in) begin
      tx_st_sop_p1 <= tx_st_sop_p0;
      tx_st_eop_p1 <= tx_st_eop_p0;

      tx_st_valid_r <= tx_st_valid;
      tx_st_err_r <= tx_st_err;
      tx_st_sop_r <= tx_st_sop;
      tx_st_eop_r <= tx_st_eop;
      tx_st_data_r <= tx_st_data;
      tx_st_empty_r <= tx_st_empty;
   end
   
   always @ (*) begin

      if (ctrltx_count_length_dword[9:2] > 0) begin
         data_tail_be_mask = 16'hffff;
      end
      else begin
         case (ctrltx_count_length_dword[1:0])
           2'b00: data_tail_be_mask = 16'h0000;
           2'b01: data_tail_be_mask = 16'h000f;
           2'b10: data_tail_be_mask = 16'h00ff;
           2'b11: data_tail_be_mask = 16'h0fff;
         endcase
      end
   end
endmodule