data/full_repos/permissive/143278/ivltests/mult16.v
 line:129: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult16.v:105: Unsupported: Ignoring delay on this delayed statement.\n      #10 clk = ~clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult16.v:111: Unsupported: Ignoring delay on this delayed statement.\n   #30 resetb = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult16.v:126: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult16.v:140: Unsupported: Ignoring delay on this delayed statement.\n   #800;\n   ^\n%Error: data/full_repos/permissive/143278/ivltests/mult16.v:155: syntax error, unexpected \'@\'\n         @(negedge clk);\n         ^\n%Error: data/full_repos/permissive/143278/ivltests/mult16.v:159: syntax error, unexpected \'@\'\n         @(negedge clk) start = 0;\n         ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mult16 (clk, resetb, start, done, ain, bin, yout);
parameter N = 16;
input			clk;
input			resetb;
input			start;



input [15:0]		ain;
input [15:0]		bin;
output [31:0]	yout;

output			done;




reg [31:0]		a;
reg [15:0]		b;
reg [31:0]		yout;

reg		done;

always @(posedge clk or negedge resetb) begin
   if (~resetb) begin
      a <= 0;
      b <= 0;
      yout <= 0;
      done <= 1'b1;
   end
   else begin

      if (start) begin
         a    <= ain;
         b    <= bin;
         yout <= 0;
         done <= 0;
      end
      else begin

         if (~done) begin
            if (b != 0) begin

               if (b[0]) begin
                  yout <= yout + a;
               end
               b <= b >> 1;
               a <= a << 1;
               $display ("a = %h, b = %h, yout = %h", a,b,yout);
            end
            else begin
               done <= 1'b1;
            end
         end
      end
   end
end
endmodule
module mult16 (clk, resetb, start, done, ain, bin, yout);

parameter N = 16;
input			clk;
input			resetb;
input			start;



input [15:0]		ain;
input [15:0]		bin;
output [31:0]	yout;

output			done;




reg [31:0]		a;
reg [15:0]		b;
reg [31:0]		yout;

reg		done;

always @(posedge clk or negedge resetb) begin
   if (~resetb) begin
      a <= 0;
      b <= 0;
      yout <= 0;
      done <= 1'b1;
   end
   else begin

      if (start) begin
         a    <= ain;
         b    <= bin;
         yout <= 0;
         done <= 0;
      end
      else begin

         if (~done) begin
            if (b != 0) begin

               if (b[0]) begin
                  yout <= yout + a;
               end
               b <= b >> 1;
               a <= a << 1;
               $display ("a = %h, b = %h, yout = %h", a,b,yout);
            end
            else begin
               done <= 1'b1;
            end
         end
      end
   end
end
endmodule