data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:9: Define or directive not defined: \'`RegDataWidth\'\n        input wire[`RegDataWidth-1:0] wdata_i,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:10: Define or directive not defined: \'`RegAddrWidth\'\n        input wire[`RegAddrWidth-1:0] wd_i,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:12: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] exmem_addr,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:17: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] read_data_value,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:22: Define or directive not defined: \'`MemAddrWidth\'\n  output reg[`MemAddrWidth-1:0] data_addr,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:23: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] write_data_value,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:24: Define or directive not defined: \'`RegDataBytes\'\n  output reg[`RegDataBytes-1:0] write_data_mask,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:25: Define or directive not defined: \'`RegDataWidth\'\n        output reg[`RegDataWidth-1:0] wdata_o,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:26: Define or directive not defined: \'`RegAddrWidth\'\n        output reg[`RegAddrWidth-1:0] wd_o,\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:32: Define or directive not defined: \'`RstEnable\'\n        if (rst == `RstEnable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:32: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (rst == `RstEnable) begin\n                             ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:33: Define or directive not defined: \'`ChipDisable\'\n   data_ce <= `ChipDisable;\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:35: Define or directive not defined: \'`ZeroWord\'\n   data_addr <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:35: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   data_addr <= `ZeroWord;\n                         ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:36: Define or directive not defined: \'`ZeroWord\'\n   write_data_value <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   write_data_value <= `ZeroWord;\n                                ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:38: Define or directive not defined: \'`ZeroWord\'\n            wdata_o <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:38: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            wdata_o <= `ZeroWord;\n                                ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:39: Define or directive not defined: \'`ZeroRegAddr\'\n            wd_o <= `ZeroRegAddr;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:39: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            wd_o <= `ZeroRegAddr;\n                                ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:40: Define or directive not defined: \'`WriteDisable\'\n            wreg_o <= `WriteDisable;\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            wreg_o <= `WriteDisable;\n                                   ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:42: Define or directive not defined: \'`ChipDisable\'\n   data_ce <= `ChipDisable;\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:44: Define or directive not defined: \'`ZeroWord\'\n   data_addr <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:45: Define or directive not defined: \'`ZeroWord\'\n   write_data_value <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:51: Define or directive not defined: \'`MEM_LOAD\'\n    `MEM_LOAD: begin\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:51: syntax error, unexpected \':\', expecting endcase\n    `MEM_LOAD: begin\n             ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:52: Define or directive not defined: \'`ChipEnable\'\n     data_ce <= `ChipEnable;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:53: Define or directive not defined: \'`MemRead\'\n     data_optype <= `MemRead;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:56: Define or directive not defined: \'`FUNCT3_LBU\'\n      `FUNCT3_LBU: begin\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:56: syntax error, unexpected \':\', expecting endcase\n      `FUNCT3_LBU: begin\n                 ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:64: Define or directive not defined: \'`FUNCT3_LB\'\n      `FUNCT3_LB: begin\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:72: Define or directive not defined: \'`FUNCT3_LHU\'\n      `FUNCT3_LHU: begin\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:78: Define or directive not defined: \'`FUNCT3_LH\'\n      `FUNCT3_LH: begin\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:84: Define or directive not defined: \'`FUNCT3_LW\'\n      `FUNCT3_LW: begin\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:89: Define or directive not defined: \'`MEM_STORE\'\n    `MEM_STORE: begin\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:90: Define or directive not defined: \'`ChipEnable\'\n     data_ce <= `ChipEnable;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:91: Define or directive not defined: \'`MemWrite\'\n     data_optype <= `MemWrite;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:94: Define or directive not defined: \'`FUNCT3_SB\'\n      `FUNCT3_SB: begin\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:94: syntax error, unexpected \':\', expecting endcase\n      `FUNCT3_SB: begin\n                ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:114: Define or directive not defined: \'`FUNCT3_SH\'\n      `FUNCT3_SH: begin\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:126: Define or directive not defined: \'`FUNCT3_SW\'\n      `FUNCT3_SW: begin\n      ^~~~~~~~~~\n%Error: Cannot continue\n'
module mem(
        input wire rst,


        input wire[`RegDataWidth-1:0] wdata_i,
        input wire[`RegAddrWidth-1:0] wd_i,
        input wire wreg_i,
		input wire[`RegDataWidth-1:0] exmem_addr,
		input wire[1:0] memop_i,
		input wire[2:0] memfunct_i,


		input wire[`RegDataWidth-1:0] read_data_value,


		output reg data_ce,
		output reg data_optype,
		output reg[`MemAddrWidth-1:0] data_addr,
		output reg[`RegDataWidth-1:0] write_data_value,
		output reg[`RegDataBytes-1:0] write_data_mask,
        output reg[`RegDataWidth-1:0] wdata_o,
        output reg[`RegAddrWidth-1:0] wd_o,
        output reg wreg_o
    );

    always @ (*)
    begin
        if (rst == `RstEnable) begin
			data_ce <= `ChipDisable;
			data_optype <= 1'b0;
			data_addr <= `ZeroWord;
			write_data_value <= `ZeroWord;
			write_data_mask <= 4'b0000;
            wdata_o <= `ZeroWord;
            wd_o <= `ZeroRegAddr;
            wreg_o <= `WriteDisable;
        end else begin
			data_ce <= `ChipDisable;
			data_optype <= 1'b0;
			data_addr <= `ZeroWord;
			write_data_value <= `ZeroWord;
			write_data_mask <= 0;
            wdata_o <= wdata_i;
            wd_o <= wd_i;
            wreg_o <= wreg_i;
			case (memop_i) 
				`MEM_LOAD: begin
					data_ce <= `ChipEnable;
					data_optype <= `MemRead;
					data_addr <= {exmem_addr[31:2],2'b00};
					case (memfunct_i) 
						`FUNCT3_LBU: begin
							case (exmem_addr[1:0])
								2'b00: wdata_o <= {{24{1'b0}},read_data_value[7:0]};
								2'b01: wdata_o <= {{24{1'b0}},read_data_value[15:8]};
								2'b10: wdata_o <= {{24{1'b0}},read_data_value[23:16]};
								2'b11: wdata_o <= {{24{1'b0}},read_data_value[31:24]};
							endcase
						end
						`FUNCT3_LB: begin
							case (exmem_addr[1:0])
								2'b00: wdata_o <= {{24{read_data_value[7]}},read_data_value[7:0]};
								2'b01: wdata_o <= {{24{read_data_value[15]}},read_data_value[15:8]};
								2'b10: wdata_o <= {{24{read_data_value[23]}},read_data_value[23:16]};
								2'b11: wdata_o <= {{24{read_data_value[31]}},read_data_value[31:24]};
							endcase
						end
						`FUNCT3_LHU: begin
							case (exmem_addr[1])
								1'b0: wdata_o <= {{16{1'b0}},read_data_value[15:0]};
								1'b1: wdata_o <= {{16{1'b0}},read_data_value[31:16]};
							endcase
						end
						`FUNCT3_LH: begin
							case (exmem_addr[0])
								1'b0: wdata_o <= {{16{read_data_value[15]}},read_data_value[15:0]};
								1'b1: wdata_o <= {{16{read_data_value[31]}},read_data_value[31:16]};
							endcase
						end
						`FUNCT3_LW: begin
							wdata_o <= read_data_value;
						end
					endcase
				end
				`MEM_STORE: begin
					data_ce <= `ChipEnable;
					data_optype <= `MemWrite;
					data_addr <= {exmem_addr[31:2],2'b00};
					case (memfunct_i) 
						`FUNCT3_SB: begin
							case (exmem_addr[1:0]) 
								2'b00: begin
									write_data_mask <= 4'b0001;
									write_data_value <= wdata_i;
								end
								2'b01: begin
									write_data_mask <= 4'b0010;
									write_data_value <= wdata_i << 8;
								end
								2'b10: begin
									write_data_mask <= 4'b0100;
									write_data_value <= wdata_i << 16;
								end
								2'b11: begin
									write_data_mask <= 4'b1000;
									write_data_value <= wdata_i << 24;
								end
							endcase
						end
						`FUNCT3_SH: begin
							case (exmem_addr[1]) 
								1'b0: begin
									write_data_mask <= 4'b0011;
									write_data_value <= wdata_i;
								end
								1'b1: begin
									write_data_mask <= 4'b1100;
									write_data_value <= wdata_i << 16;
								end
							endcase
						end
						`FUNCT3_SW: begin
							write_data_mask <= 4'b1111;
							write_data_value <= wdata_i;
						end
					endcase
				end
			endcase
        end
    end
endmodule
module mem(
        input wire rst,


        input wire[`RegDataWidth-1:0] wdata_i,
        input wire[`RegAddrWidth-1:0] wd_i,
        input wire wreg_i,
		input wire[`RegDataWidth-1:0] exmem_addr,
		input wire[1:0] memop_i,
		input wire[2:0] memfunct_i,


		input wire[`RegDataWidth-1:0] read_data_value,


		output reg data_ce,
		output reg data_optype,
		output reg[`MemAddrWidth-1:0] data_addr,
		output reg[`RegDataWidth-1:0] write_data_value,
		output reg[`RegDataBytes-1:0] write_data_mask,
        output reg[`RegDataWidth-1:0] wdata_o,
        output reg[`RegAddrWidth-1:0] wd_o,
        output reg wreg_o
    );


    always @ (*)
    begin
        if (rst == `RstEnable) begin
			data_ce <= `ChipDisable;
			data_optype <= 1'b0;
			data_addr <= `ZeroWord;
			write_data_value <= `ZeroWord;
			write_data_mask <= 4'b0000;
            wdata_o <= `ZeroWord;
            wd_o <= `ZeroRegAddr;
            wreg_o <= `WriteDisable;
        end else begin
			data_ce <= `ChipDisable;
			data_optype <= 1'b0;
			data_addr <= `ZeroWord;
			write_data_value <= `ZeroWord;
			write_data_mask <= 0;
            wdata_o <= wdata_i;
            wd_o <= wd_i;
            wreg_o <= wreg_i;
			case (memop_i) 
				`MEM_LOAD: begin
					data_ce <= `ChipEnable;
					data_optype <= `MemRead;
					data_addr <= {exmem_addr[31:2],2'b00};
					case (memfunct_i) 
						`FUNCT3_LBU: begin
							case (exmem_addr[1:0])
								2'b00: wdata_o <= {{24{1'b0}},read_data_value[7:0]};
								2'b01: wdata_o <= {{24{1'b0}},read_data_value[15:8]};
								2'b10: wdata_o <= {{24{1'b0}},read_data_value[23:16]};
								2'b11: wdata_o <= {{24{1'b0}},read_data_value[31:24]};
							endcase
						end
						`FUNCT3_LB: begin
							case (exmem_addr[1:0])
								2'b00: wdata_o <= {{24{read_data_value[7]}},read_data_value[7:0]};
								2'b01: wdata_o <= {{24{read_data_value[15]}},read_data_value[15:8]};
								2'b10: wdata_o <= {{24{read_data_value[23]}},read_data_value[23:16]};
								2'b11: wdata_o <= {{24{read_data_value[31]}},read_data_value[31:24]};
							endcase
						end
						`FUNCT3_LHU: begin
							case (exmem_addr[1])
								1'b0: wdata_o <= {{16{1'b0}},read_data_value[15:0]};
								1'b1: wdata_o <= {{16{1'b0}},read_data_value[31:16]};
							endcase
						end
						`FUNCT3_LH: begin
							case (exmem_addr[0])
								1'b0: wdata_o <= {{16{read_data_value[15]}},read_data_value[15:0]};
								1'b1: wdata_o <= {{16{read_data_value[31]}},read_data_value[31:16]};
							endcase
						end
						`FUNCT3_LW: begin
							wdata_o <= read_data_value;
						end
					endcase
				end
				`MEM_STORE: begin
					data_ce <= `ChipEnable;
					data_optype <= `MemWrite;
					data_addr <= {exmem_addr[31:2],2'b00};
					case (memfunct_i) 
						`FUNCT3_SB: begin
							case (exmem_addr[1:0]) 
								2'b00: begin
									write_data_mask <= 4'b0001;
									write_data_value <= wdata_i;
								end
								2'b01: begin
									write_data_mask <= 4'b0010;
									write_data_value <= wdata_i << 8;
								end
								2'b10: begin
									write_data_mask <= 4'b0100;
									write_data_value <= wdata_i << 16;
								end
								2'b11: begin
									write_data_mask <= 4'b1000;
									write_data_value <= wdata_i << 24;
								end
							endcase
						end
						`FUNCT3_SH: begin
							case (exmem_addr[1]) 
								1'b0: begin
									write_data_mask <= 4'b0011;
									write_data_value <= wdata_i;
								end
								1'b1: begin
									write_data_mask <= 4'b1100;
									write_data_value <= wdata_i << 16;
								end
							endcase
						end
						`FUNCT3_SW: begin
							write_data_mask <= 4'b1111;
							write_data_value <= wdata_i;
						end
					endcase
				end
			endcase
        end
    end
endmodule