data/full_repos/permissive/149848590/src/dev/ddr3/ResetGen.v
data/verilator_xmls/a725aab9-22d5-4415-a380-21ab8d069d22.xml
module ResetGenerator(
    input ddr_ui_clk,
    input ddr_ui_clk_rst,
    input ddr_calib_done,
    output reg ddr_interconn_rst
);

    always @(posedge ddr_ui_clk) begin
        ddr_interconn_rst <= ~ddr_ui_clk_rst && ddr_calib_done;
    end

endmodule
module ResetGenerator(
    input ddr_ui_clk,
    input ddr_ui_clk_rst,
    input ddr_calib_done,
    output reg ddr_interconn_rst
);


    always @(posedge ddr_ui_clk) begin
        ddr_interconn_rst <= ~ddr_ui_clk_rst && ddr_calib_done;
    end

endmodule