data/full_repos/permissive/153414067/Accelo.v
None: at end of input
data/verilator_xmls/947d47a2-9bd1-4c6a-86db-5a9449be4c98.xml
module Accelo(
	input clk,
	input rst,
	
	output [2:0] bo,
	input bi,
	
	output right,
	output left,
	output middle
    );
	 
	 reg MOSI, SCLK, nCS;
	 
	 reg [17:0] cntr;
	 reg [7:0] out;
	 reg [4:0] sclk_cntr;
	 reg sclk_en;
	 reg read = 1'b0;
	 
	 reg measure = 1'b1;
	 reg range = 1'b0;
	 reg [5:0] act_address = 6'h2D;
	 reg [1:0] act_data_cntr = 2'b0;
	 
	 always @ (posedge clk)
	 begin
		if (rst) begin
			cntr <= 18'b0;
			SCLK <= 1'b0;
			sclk_cntr <= 5'b0;
			sclk_en <= 1'b1;
			act_data_cntr <= 2'b0;
			measure = 1'b1;
			range = 1'b0;
			act_address <= 6'h2D;
			read <= 1'b0;
		end
		else if (cntr == 18'd249999) begin
			cntr <= 18'b0;
			if (SCLK) begin
				if (sclk_cntr == 5'd19) begin
					if (act_data_cntr == 2'b00) begin
						measure = 1'b0;
						range = 1'b1;
						act_address <= 6'h31;
						act_data_cntr <= act_data_cntr + 1'b1;
						end
					else if (act_data_cntr == 2'b01) begin
						measure = 1'b0;
						range = 1'b0;
						act_address <= 6'h34;
						act_data_cntr <= act_data_cntr + 1'b1;
						read <= 1'b1;
					end
					sclk_cntr <= 5'b0;
				end
				else
					sclk_cntr <= sclk_cntr + 1'b1;
					
				case(sclk_cntr)
					5'd0: nCS <= 1'b1;
					5'd1: nCS <= 1'b0;
					5'd2: begin
								MOSI <= read;
								sclk_en <= 1'b0;
							end
					5'd3: MOSI <= 1'b0;
		
					5'd4: MOSI <= act_address[5];
					5'd5: MOSI <= act_address[4];
					5'd6: MOSI <= act_address[3];
					5'd7: MOSI <= act_address[2];
					5'd8: MOSI <= act_address[1];
					5'd9: MOSI <= act_address[0];
					
					5'd10: MOSI <= 1'b0;
					5'd11: MOSI <= 1'b0;
					5'd12: MOSI <= 1'b0;
					5'd13: MOSI <= 1'b0;
					5'd14: MOSI <= measure;
					5'd15: MOSI <= 1'b0;
					5'd16: MOSI <= 1'b0;
					5'd17: MOSI <= range;
					
					5'd19: begin
								nCS <= 1'b1;
								sclk_en <= 1'b1;
							 end
					default: begin
									nCS <= 1'b0;
									sclk_en <= 1'b0;
								end
				endcase
			end
			else
				case (sclk_cntr)
					5'd11: out[7] <= bi && read;
					5'd12: out[6] <= bi && read;
					5'd13: out[5] <= bi && read;
					5'd14: out[4] <= bi && read;
					5'd15: out[3] <= bi && read;
					5'd16: out[2] <= bi && read;
					5'd17: out[1] <= bi && read;
					5'd18: out[0] <= bi && read;
				endcase
			SCLK <= ~SCLK;
		end
		else cntr <= cntr + 1'b1;
	 end
	 

	 
	 assign bo[0] = nCS;
	 assign bo[1] = MOSI;
	 assign bo[2] = sclk_en || SCLK;
	 
	 assign left = out[7] && (out[6:0] <= 7'd96);
	 assign right = ~out[7] && (out[6:0] >= 7'd32);
	 assign middle = ~(left && right);
 	 
endmodule
module Accelo(
	input clk,
	input rst,
	
	output [2:0] bo,
	input bi,
	
	output right,
	output left,
	output middle
    );

	 
	 reg MOSI, SCLK, nCS;
	 
	 reg [17:0] cntr;
	 reg [7:0] out;
	 reg [4:0] sclk_cntr;
	 reg sclk_en;
	 reg read = 1'b0;
	 
	 reg measure = 1'b1;
	 reg range = 1'b0;
	 reg [5:0] act_address = 6'h2D;
	 reg [1:0] act_data_cntr = 2'b0;
	 
	 always @ (posedge clk)
	 begin
		if (rst) begin
			cntr <= 18'b0;
			SCLK <= 1'b0;
			sclk_cntr <= 5'b0;
			sclk_en <= 1'b1;
			act_data_cntr <= 2'b0;
			measure = 1'b1;
			range = 1'b0;
			act_address <= 6'h2D;
			read <= 1'b0;
		end
		else if (cntr == 18'd249999) begin
			cntr <= 18'b0;
			if (SCLK) begin
				if (sclk_cntr == 5'd19) begin
					if (act_data_cntr == 2'b00) begin
						measure = 1'b0;
						range = 1'b1;
						act_address <= 6'h31;
						act_data_cntr <= act_data_cntr + 1'b1;
						end
					else if (act_data_cntr == 2'b01) begin
						measure = 1'b0;
						range = 1'b0;
						act_address <= 6'h34;
						act_data_cntr <= act_data_cntr + 1'b1;
						read <= 1'b1;
					end
					sclk_cntr <= 5'b0;
				end
				else
					sclk_cntr <= sclk_cntr + 1'b1;
					
				case(sclk_cntr)
					5'd0: nCS <= 1'b1;
					5'd1: nCS <= 1'b0;
					5'd2: begin
								MOSI <= read;
								sclk_en <= 1'b0;
							end
					5'd3: MOSI <= 1'b0;
		
					5'd4: MOSI <= act_address[5];
					5'd5: MOSI <= act_address[4];
					5'd6: MOSI <= act_address[3];
					5'd7: MOSI <= act_address[2];
					5'd8: MOSI <= act_address[1];
					5'd9: MOSI <= act_address[0];
					
					5'd10: MOSI <= 1'b0;
					5'd11: MOSI <= 1'b0;
					5'd12: MOSI <= 1'b0;
					5'd13: MOSI <= 1'b0;
					5'd14: MOSI <= measure;
					5'd15: MOSI <= 1'b0;
					5'd16: MOSI <= 1'b0;
					5'd17: MOSI <= range;
					
					5'd19: begin
								nCS <= 1'b1;
								sclk_en <= 1'b1;
							 end
					default: begin
									nCS <= 1'b0;
									sclk_en <= 1'b0;
								end
				endcase
			end
			else
				case (sclk_cntr)
					5'd11: out[7] <= bi && read;
					5'd12: out[6] <= bi && read;
					5'd13: out[5] <= bi && read;
					5'd14: out[4] <= bi && read;
					5'd15: out[3] <= bi && read;
					5'd16: out[2] <= bi && read;
					5'd17: out[1] <= bi && read;
					5'd18: out[0] <= bi && read;
				endcase
			SCLK <= ~SCLK;
		end
		else cntr <= cntr + 1'b1;
	 end
	 

	 
	 assign bo[0] = nCS;
	 assign bo[1] = MOSI;
	 assign bo[2] = sclk_en || SCLK;
	 
	 assign left = out[7] && (out[6:0] <= 7'd96);
	 assign right = ~out[7] && (out[6:0] >= 7'd32);
	 assign middle = ~(left && right);
 	 
endmodule