data/full_repos/permissive/219219909/Radix-5/src/buf_1.v
data/verilator_xmls/dba9394e-ba03-4b0b-80eb-94f592ac6692.xml
module buf_1(
    input [31:0] a_re,
    input [31:0] a_img,
    input clk,
    output reg [31:0] a1_re,
    output reg [31:0] a1_img
    );

always @(posedge clk) begin
a1_re<=a_re;
a1_img<=a_img;
end

endmodule
module buf_1(
    input [31:0] a_re,
    input [31:0] a_img,
    input clk,
    output reg [31:0] a1_re,
    output reg [31:0] a1_img
    );


always @(posedge clk) begin
a1_re<=a_re;
a1_img<=a_img;
end

endmodule