data/full_repos/permissive/106029354/verilog_source/pipeline2.v
1: b'%Error: data/full_repos/permissive/106029354/verilog_source/pipeline2.v:19: Cannot find include file: params_proc.v\n`include "params_proc.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n             params_proc.v\n             params_proc.v.v\n             params_proc.v.sv\n             obj_dir/params_proc.v\n             obj_dir/params_proc.v.v\n             obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n'
module pipeline2(
	clk_in,
	RST,
	pc_in,
	instr,
	reg_addr,
	reg_data,
	reg_en,
    A_addr,
    B_addr,
    A,
    B,
    imm,
	pc_out,
    ctrl
);


`include "params_proc.v"


input clk_in, RST;
input [PC_WIDTH-1:0] pc_in;
input [INSTR_WIDTH-1:0] instr;
input [REG_ADDR_WIDTH-1:0] reg_addr;
input [DATA_WIDTH-1:0] reg_data;
input reg_en;

output reg signed [DATA_WIDTH-1:0] imm;
output reg [PC_WIDTH-1:0] pc_out;
output reg [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
output signed [DATA_WIDTH-1:0] A, B;
output [CTRL_WIDTH-1:0] ctrl;


reg [OPCODE_WIDTH-1:0] opcode;
wire clk_neg;


controller ctrl0(.opcode(opcode), .ctrl(ctrl));
regs regs0(.clk(clk_neg),
         .en_write(reg_en), .addr_write(reg_addr), .data_write(reg_data),
         .addr_read1(A_addr), .addr_read2(B_addr),
         .data_read1(A), .data_read2(B));

assign clk_neg = ~clk_in;
		 


always @(posedge clk_in) begin
	if (!RST) begin

		opcode      <= NOP;
		A_addr      <= 0;
		B_addr      <= 0;
		imm         <= 0;

		pc_out      <= PC_INITIAL + 1;
	end	else begin
		opcode      <= instr[OPCODE_WIDTH-1:0];
		A_addr      <= instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH];
		B_addr      <= instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH];
		imm         <= instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2];

		if (instr[OPCODE_WIDTH-1:0] == RET) begin
			A_addr      <= REG_FUNC_RET;
		end

		pc_out      <= pc_in;
	end
end

endmodule
module pipeline2(
	clk_in,
	RST,
	pc_in,
	instr,
	reg_addr,
	reg_data,
	reg_en,
    A_addr,
    B_addr,
    A,
    B,
    imm,
	pc_out,
    ctrl
);



`include "params_proc.v"


input clk_in, RST;
input [PC_WIDTH-1:0] pc_in;
input [INSTR_WIDTH-1:0] instr;
input [REG_ADDR_WIDTH-1:0] reg_addr;
input [DATA_WIDTH-1:0] reg_data;
input reg_en;

output reg signed [DATA_WIDTH-1:0] imm;
output reg [PC_WIDTH-1:0] pc_out;
output reg [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
output signed [DATA_WIDTH-1:0] A, B;
output [CTRL_WIDTH-1:0] ctrl;


reg [OPCODE_WIDTH-1:0] opcode;
wire clk_neg;


controller ctrl0(.opcode(opcode), .ctrl(ctrl));
regs regs0(.clk(clk_neg),
         .en_write(reg_en), .addr_write(reg_addr), .data_write(reg_data),
         .addr_read1(A_addr), .addr_read2(B_addr),
         .data_read1(A), .data_read2(B));

assign clk_neg = ~clk_in;
		 


always @(posedge clk_in) begin
	if (!RST) begin

		opcode      <= NOP;
		A_addr      <= 0;
		B_addr      <= 0;
		imm         <= 0;

		pc_out      <= PC_INITIAL + 1;
	end	else begin
		opcode      <= instr[OPCODE_WIDTH-1:0];
		A_addr      <= instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH];
		B_addr      <= instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH];
		imm         <= instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2];

		if (instr[OPCODE_WIDTH-1:0] == RET) begin
			A_addr      <= REG_FUNC_RET;
		end

		pc_out      <= pc_in;
	end
end

endmodule