data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/genrefresh.v
 line:67: before: "ou"
data/verilator_xmls/8d9034a7-0ded-45c3-9785-e26900b27190.xml
module genrefresh (
		clock_i,
		reset_ni,
		refresh_o,
		ack_i
	);
	
	parameter	TICKS	= 20000;
	parameter	BITS	= 15;
	
	input	clock_i;
	input	reset_ni;
	output	refresh_o;
	input	ack_i;
	
	reg	[BITS-1:0]	counter;
	reg	refresh_o	= 0;
	always @(posedge clock_i)
	begin
		if (~reset_ni)
		begin
			counter		<= 0;
			refresh_o	<= 0;
		end
		else
		begin
			if (counter == TICKS)
			begin
				counter		<= 0;
				refresh_o	<= 1;
			end
			else
			begin
				if (ack_i)
					refresh_o	<= 0;
				counter	<= counter + 1;
			end
		end
	end
	
endmodule
module genrefresh (
		clock_i,
		reset_ni,
		refresh_o,
		ack_i
	);

	
	parameter	TICKS	= 20000;
	parameter	BITS	= 15;
	
	input	clock_i;
	input	reset_ni;
	output	refresh_o;
	input	ack_i;
	
	reg	[BITS-1:0]	counter;
	reg	refresh_o	= 0;
	always @(posedge clock_i)
	begin
		if (~reset_ni)
		begin
			counter		<= 0;
			refresh_o	<= 0;
		end
		else
		begin
			if (counter == TICKS)
			begin
				counter		<= 0;
				refresh_o	<= 1;
			end
			else
			begin
				if (ack_i)
					refresh_o	<= 0;
				counter	<= counter + 1;
			end
		end
	end
	
endmodule