data/full_repos/permissive/187705377/Camera Reduced/single_frame_trigger.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: Reduced,data/full_repos/permissive/187705377\n        ... Looked in:\n             data/full_repos/permissive/187705377/Camera/Reduced,data/full_repos/permissive/187705377\n             data/full_repos/permissive/187705377/Camera/Reduced,data/full_repos/permissive/187705377.v\n             data/full_repos/permissive/187705377/Camera/Reduced,data/full_repos/permissive/187705377.sv\n             Reduced,data/full_repos/permissive/187705377\n             Reduced,data/full_repos/permissive/187705377.v\n             Reduced,data/full_repos/permissive/187705377.sv\n             obj_dir/Reduced,data/full_repos/permissive/187705377\n             obj_dir/Reduced,data/full_repos/permissive/187705377.v\n             obj_dir/Reduced,data/full_repos/permissive/187705377.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/187705377/Camera\n%Error: Cannot find file containing module: Reduced/single_frame_trigger.sv\n%Error: Exiting due to 3 error(s)\n'
module single_frame_trigger_testbench();
    logic clk, reset, trigger, VS, HS, capture;
    single_frame_trigger dut(clk, reset, trigger, VS, HS, capture);
    
    parameter PERIOD = 100;
	initial begin
        clk <= 0;
		forever #(PERIOD/2) clk = ~clk;
	end
    
    integer i;
	initial begin

		{reset, trigger, VS, HS} <= '0; @(posedge clk);
		reset <= 1; @(posedge clk);
		reset <= 0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        HS <= ~HS; trigger <= 1'b1; @(posedge clk);
        HS <= ~HS; trigger <= 1'b0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        VS <= 1'b1; HS <= ~HS; @(posedge clk);
		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
        for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        

        {reset, trigger, HS} <= '0; VS <= 1'b1; @(posedge clk);
		reset <= 1; @(posedge clk);
		reset <= 0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        HS <= ~HS; trigger <= 1'b1; @(posedge clk);
        HS <= ~HS; trigger <= 1'b0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; VS <= 1'b0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        VS <= 1'b1; HS <= ~HS; @(posedge clk);
		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
        for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        

        VS <= 1'b1; HS <= ~HS; @(posedge clk);
        for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
        for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        

		{reset, trigger, VS, HS} <= '0; @(posedge clk);
		reset <= 1; @(posedge clk);
		reset <= 0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        HS <= ~HS; trigger <= 1'b1; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        VS <= 1'b1; HS <= ~HS; @(posedge clk);
		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        HS <= ~HS; trigger <= 1'b0; @(posedge clk);
		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
        for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        

		{reset, trigger, VS, HS} <= '0; @(posedge clk);
		reset <= 1; @(posedge clk);
		reset <= 0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        HS <= ~HS; trigger <= 1'b1; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        VS <= 1'b1; HS <= ~HS; @(posedge clk);
		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end

 		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b1; HS <= ~HS; @(posedge clk);        
 		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
 		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b1; HS <= ~HS; @(posedge clk);        
 		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
        
        HS <= ~HS; trigger <= 1'b0; @(posedge clk);
		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
        for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        
		$stop;
	end
    
endmodule
module single_frame_trigger_testbench();

    logic clk, reset, trigger, VS, HS, capture;
    single_frame_trigger dut(clk, reset, trigger, VS, HS, capture);
    
    parameter PERIOD = 100;
	initial begin
        clk <= 0;
		forever #(PERIOD/2) clk = ~clk;
	end
    
    integer i;
	initial begin

		{reset, trigger, VS, HS} <= '0; @(posedge clk);
		reset <= 1; @(posedge clk);
		reset <= 0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        HS <= ~HS; trigger <= 1'b1; @(posedge clk);
        HS <= ~HS; trigger <= 1'b0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        VS <= 1'b1; HS <= ~HS; @(posedge clk);
		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
        for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        

        {reset, trigger, HS} <= '0; VS <= 1'b1; @(posedge clk);
		reset <= 1; @(posedge clk);
		reset <= 0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        HS <= ~HS; trigger <= 1'b1; @(posedge clk);
        HS <= ~HS; trigger <= 1'b0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; VS <= 1'b0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        VS <= 1'b1; HS <= ~HS; @(posedge clk);
		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
        for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        

        VS <= 1'b1; HS <= ~HS; @(posedge clk);
        for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
        for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        

		{reset, trigger, VS, HS} <= '0; @(posedge clk);
		reset <= 1; @(posedge clk);
		reset <= 0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        HS <= ~HS; trigger <= 1'b1; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        VS <= 1'b1; HS <= ~HS; @(posedge clk);
		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        HS <= ~HS; trigger <= 1'b0; @(posedge clk);
		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
        for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        

		{reset, trigger, VS, HS} <= '0; @(posedge clk);
		reset <= 1; @(posedge clk);
		reset <= 0; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        HS <= ~HS; trigger <= 1'b1; @(posedge clk);
		HS <= ~HS; @(posedge clk);
		HS <= ~HS; @(posedge clk);
        VS <= 1'b1; HS <= ~HS; @(posedge clk);
		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end

 		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b1; HS <= ~HS; @(posedge clk);        
 		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
 		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b1; HS <= ~HS; @(posedge clk);        
 		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
        
        HS <= ~HS; trigger <= 1'b0; @(posedge clk);
		for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        VS <= 1'b0; HS <= ~HS; @(posedge clk);
        for(i=0; i<10; i+=1) begin
			HS <= ~HS; @(posedge clk);
		end
        
		$stop;
	end
    
endmodule