data/full_repos/permissive/182885969/test/im_slow_tb.v
1: b'%Error: data/full_repos/permissive/182885969/test/im_slow_tb.v:12: Cannot find include file: im_slow.v\n`include "im_slow.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/182885969/test,data/full_repos/permissive/182885969/im_slow.v\n             data/full_repos/permissive/182885969/test,data/full_repos/permissive/182885969/im_slow.v.v\n             data/full_repos/permissive/182885969/test,data/full_repos/permissive/182885969/im_slow.v.sv\n             im_slow.v\n             im_slow.v.v\n             im_slow.v.sv\n             obj_dir/im_slow.v\n             obj_dir/im_slow.v.v\n             obj_dir/im_slow.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/182885969/test/im_slow_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/182885969/test/im_slow_tb.v:33: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("im_slow_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/182885969/test/im_slow_tb.v:34: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, im_slow_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/182885969/test/im_slow_tb.v:43: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/182885969/test/im_slow_tb.v:47: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/182885969/test/im_slow_tb.v:52: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module im_slow_tb;

	integer i;

	reg clk;

	reg [31:0]	addr;
	wire		rdy;
	wire [31:0]	data;

	im_slow #(.IM_DATA("im_slow_tb.hex"), .NMEM(14), .ND(3))
		im1(.clk(clk), .addr(addr), .rdy(rdy), .data(data));

	always begin
		clk <= ~clk;
		#5;
	end

	initial begin
		$dumpfile("im_slow_tb.vcd");
		$dumpvars(0, im_slow_tb);




		clk <= 1'b0;
		addr <= 32'd0;

		for (i = 0; i < 5; i = i + 1) begin
			@(posedge clk);
		end

		addr <= 32'd4;
		@(posedge clk);
		@(posedge clk);

		addr <= 32'd8;

		@(posedge clk);
		@(posedge clk);
		@(posedge clk);
		@(posedge clk);

		$finish;
	end

endmodule
module im_slow_tb;


	integer i;

	reg clk;

	reg [31:0]	addr;
	wire		rdy;
	wire [31:0]	data;

	im_slow #(.IM_DATA("im_slow_tb.hex"), .NMEM(14), .ND(3))
		im1(.clk(clk), .addr(addr), .rdy(rdy), .data(data));

	always begin
		clk <= ~clk;
		#5;
	end

	initial begin
		$dumpfile("im_slow_tb.vcd");
		$dumpvars(0, im_slow_tb);




		clk <= 1'b0;
		addr <= 32'd0;

		for (i = 0; i < 5; i = i + 1) begin
			@(posedge clk);
		end

		addr <= 32'd4;
		@(posedge clk);
		@(posedge clk);

		addr <= 32'd8;

		@(posedge clk);
		@(posedge clk);
		@(posedge clk);
		@(posedge clk);

		$finish;
	end

endmodule