data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/01710d08-7445-4e8f-911e-2f2deeec6d8f.xml
module FromChannelBusToCLBJunction#(

		parameter DIMENSION = 4,

		parameter CH_WIDTH = 4,

		parameter DIMENSION_WIDTH = 2
	) (

		mode,
		c_clk,
		c_bus,
		c_dimension,


		ch,


		clb_in
	);


	parameter CONFIG_WORD_WIDTH = DIMENSION*CH_WIDTH;


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [DIMENSION_WIDTH-1:0] c_dimension;


	input [CH_WIDTH-1:0] ch;


	output clb_in;


	reg [CONFIG_WORD_WIDTH-1:0] configReg;


	always @(posedge c_clk) begin
		if(mode) begin
			`CONFIGREG_CLB_JUNCTION = `C_BUS_CLB_JUNCTION;
		end
	end


	assign clb_in = ch[(`CONFIGREG_CLB_JUNCTION >> (c_dimension * CH_WIDTH)) & (CH_WIDTH - 1)];

endmodule
module FromChannelBusToCLBJunction#(

		parameter DIMENSION = 4,

		parameter CH_WIDTH = 4,

		parameter DIMENSION_WIDTH = 2
	) (

		mode,
		c_clk,
		c_bus,
		c_dimension,


		ch,


		clb_in
	);



	parameter CONFIG_WORD_WIDTH = DIMENSION*CH_WIDTH;


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [DIMENSION_WIDTH-1:0] c_dimension;


	input [CH_WIDTH-1:0] ch;


	output clb_in;


	reg [CONFIG_WORD_WIDTH-1:0] configReg;


	always @(posedge c_clk) begin
		if(mode) begin
			`CONFIGREG_CLB_JUNCTION = `C_BUS_CLB_JUNCTION;
		end
	end


	assign clb_in = ch[(`CONFIGREG_CLB_JUNCTION >> (c_dimension * CH_WIDTH)) & (CH_WIDTH - 1)];

endmodule