data/full_repos/permissive/184431263/AOI/AOI32.v
data/verilator_xmls/ead710f7-3821-4416-bcca-be761f00dab6.xml
module AOI32(Y, A0, A1, A2, B0, B1, B2, VDD, VSS );
  input A0, A1, A2, B0, B1, B2;
  output Y;
  inout VDD, VSS;

  assign Y=~((A0 && A1 && A2) || (B0 && B1 && B2));
endmodule
module AOI32(Y, A0, A1, A2, B0, B1, B2, VDD, VSS );

  input A0, A1, A2, B0, B1, B2;
  output Y;
  inout VDD, VSS;

  assign Y=~((A0 && A1 && A2) || (B0 && B1 && B2));
endmodule