data/full_repos/permissive/202032771/vmod/cnnip_fifo.sv
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1: b'%Warning-WIDTH: data/full_repos/permissive/202032771/vmod/cnnip_fifo.sv:62: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'out_ptr\' generates 2 bits.\n                                                                          : ... In instance cnnip_fifo\n                        (out_ptr == DEPTH-1) ? {(addr_width){1\'b0}} :\n                                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/202032771/vmod/cnnip_fifo.sv:66: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'in_ptr\' generates 2 bits.\n                                                                          : ... In instance cnnip_fifo\n                       (in_ptr == DEPTH-1) ? {(addr_width){1\'b0}} :\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/202032771/vmod/cnnip_fifo.sv:77: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'out_ptr\' generates 2 bits.\n                                                                          : ... In instance cnnip_fifo\n  assign out_ptr_reset = ((out_ptr == DEPTH-1) & pop_a);\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/202032771/vmod/cnnip_fifo.sv:78: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'in_ptr\' generates 2 bits.\n                                                                          : ... In instance cnnip_fifo\n  assign in_ptr_reset  = ((in_ptr == DEPTH-1) & push_a);\n                                  ^~\n%Error: Exiting due to 4 warning(s)\n'
module cnnip_fifo #(
  parameter WIDTH = 32,
  parameter DEPTH = 4
) (
  input  wire             clk_a,
  input  wire             arstz_aq,
  input  wire             push_a,
  input  wire             pop_a,
  input  wire [WIDTH-1:0] din_a,
  output wire             empty_a,
  output wire             full_a,
  output wire [WIDTH-1:0] dout_a
);

  localparam addr_width = $clog2(DEPTH);


  reg  [WIDTH-1:0]      mem[DEPTH-1:0];
  reg  [addr_width-1:0] in_ptr;
  reg  [addr_width-1:0] out_ptr;
  wire [addr_width-1:0] in_ptr_next;
  wire [addr_width-1:0] out_ptr_next;
  wire                  out_ptr_reset;
  wire                  in_ptr_reset;
  reg                   not_empty;
  reg                   not_empty_next;
  reg                   full_aq;
  reg                   empty_aq;
  wire                  full_next;
  wire                  empty_next;




  assign empty_a = empty_aq;
  assign full_a  = full_aq;

  assign empty_next = (in_ptr_next == out_ptr_next) && !not_empty_next;
  assign full_next  = (in_ptr_next == out_ptr_next) && not_empty_next;

  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) empty_aq <= 1'b1;
    else empty_aq <= empty_next;

  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) full_aq <= 1'b0;
    else full_aq <= full_next;




  assign out_ptr_next = (pop_a   == 1'b0)    ? out_ptr :
                        (out_ptr == DEPTH-1) ? {(addr_width){1'b0}} :
                                               out_ptr + 1'b1;

  assign in_ptr_next = (push_a == 1'b0)    ? in_ptr :
                       (in_ptr == DEPTH-1) ? {(addr_width){1'b0}} :
                                             in_ptr + 1'b1;

  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) out_ptr <= {(addr_width){1'b0}};
    else out_ptr <= out_ptr_next;

  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) in_ptr <= {(addr_width){1'b0}};
    else in_ptr <= in_ptr_next;

  assign out_ptr_reset = ((out_ptr == DEPTH-1) & pop_a);
  assign in_ptr_reset  = ((in_ptr == DEPTH-1) & push_a);

  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) not_empty <= 1'b0;
    else not_empty <= not_empty_next;

  always @(*)
    if (out_ptr_reset & in_ptr_reset)      not_empty_next =  not_empty;
    else if (out_ptr_reset | in_ptr_reset) not_empty_next = ~not_empty;
    else                                   not_empty_next = not_empty;

  always @(posedge clk_a)
    if (push_a) mem[in_ptr] <= din_a;

  assign dout_a = mem[out_ptr];

endmodule
module cnnip_fifo #(
  parameter WIDTH = 32,
  parameter DEPTH = 4
) (
  input  wire             clk_a,
  input  wire             arstz_aq,
  input  wire             push_a,
  input  wire             pop_a,
  input  wire [WIDTH-1:0] din_a,
  output wire             empty_a,
  output wire             full_a,
  output wire [WIDTH-1:0] dout_a
);


  localparam addr_width = $clog2(DEPTH);


  reg  [WIDTH-1:0]      mem[DEPTH-1:0];
  reg  [addr_width-1:0] in_ptr;
  reg  [addr_width-1:0] out_ptr;
  wire [addr_width-1:0] in_ptr_next;
  wire [addr_width-1:0] out_ptr_next;
  wire                  out_ptr_reset;
  wire                  in_ptr_reset;
  reg                   not_empty;
  reg                   not_empty_next;
  reg                   full_aq;
  reg                   empty_aq;
  wire                  full_next;
  wire                  empty_next;




  assign empty_a = empty_aq;
  assign full_a  = full_aq;

  assign empty_next = (in_ptr_next == out_ptr_next) && !not_empty_next;
  assign full_next  = (in_ptr_next == out_ptr_next) && not_empty_next;

  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) empty_aq <= 1'b1;
    else empty_aq <= empty_next;

  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) full_aq <= 1'b0;
    else full_aq <= full_next;




  assign out_ptr_next = (pop_a   == 1'b0)    ? out_ptr :
                        (out_ptr == DEPTH-1) ? {(addr_width){1'b0}} :
                                               out_ptr + 1'b1;

  assign in_ptr_next = (push_a == 1'b0)    ? in_ptr :
                       (in_ptr == DEPTH-1) ? {(addr_width){1'b0}} :
                                             in_ptr + 1'b1;

  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) out_ptr <= {(addr_width){1'b0}};
    else out_ptr <= out_ptr_next;

  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) in_ptr <= {(addr_width){1'b0}};
    else in_ptr <= in_ptr_next;

  assign out_ptr_reset = ((out_ptr == DEPTH-1) & pop_a);
  assign in_ptr_reset  = ((in_ptr == DEPTH-1) & push_a);

  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) not_empty <= 1'b0;
    else not_empty <= not_empty_next;

  always @(*)
    if (out_ptr_reset & in_ptr_reset)      not_empty_next =  not_empty;
    else if (out_ptr_reset | in_ptr_reset) not_empty_next = ~not_empty;
    else                                   not_empty_next = not_empty;

  always @(posedge clk_a)
    if (push_a) mem[in_ptr] <= din_a;

  assign dout_a = mem[out_ptr];

endmodule