data/full_repos/permissive/205055389/vlib/tty.v
1: b'%Error: data/full_repos/permissive/205055389/vlib/tty.v:151: Unsupported or unknown PLI call: $tkg$post\n  initial $tkg$post("TTY","%m");\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/205055389/vlib/tty.v:156: syntax error, unexpected \'@\'\n      @(posedge DSR);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/vlib/tty.v:157: Unsupported: Ignoring delay on this delayed statement.\n      # 10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/205055389/vlib/tty.v:160: Unsupported or unknown PLI call: $tkg$send\n      $tkg$send("%m.RD",RD);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/vlib/tty.v:161: Unsupported: Ignoring delay on this delayed statement.\n      # 10;\n      ^\n%Error: data/full_repos/permissive/205055389/vlib/tty.v:162: syntax error, unexpected \'@\'\n      @(negedge DSR);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/vlib/tty.v:163: Unsupported: Ignoring delay on this delayed statement.\n      # 10;\n      ^\n%Error: data/full_repos/permissive/205055389/vlib/tty.v:168: syntax error, unexpected \'@\'\n      @ (negedge CTS);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/vlib/tty.v:169: Unsupported: Ignoring delay on this delayed statement.\n      # 10;\n      ^\n%Error: data/full_repos/permissive/205055389/vlib/tty.v:170: Unsupported or unknown PLI call: $tkg$recv\n      data = $tkg$recv("%m.TD");\n             ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/vlib/tty.v:171: Unsupported: Ignoring delay on this delayed statement.\n      # 10;\n      ^\n%Error: data/full_repos/permissive/205055389/vlib/tty.v:173: syntax error, unexpected \'@\'\n      @ (posedge CTS);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/vlib/tty.v:174: Unsupported: Ignoring delay on this delayed statement.\n      # 10;\n      ^\n%Error: Exiting due to 7 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TTY(TD, RD, RTS, CTS, DSR, DTR);
input CTS, DSR;
input [7:0] RD;
output [7:0] TD;
output RTS, DTR;
reg _RTS, _DTR;
reg [7:0] data;

  initial
    begin
      _RTS = 0;
      data = 0;
      _DTR = 0;
    end

  initial $tkg$post("TTY","%m");

  always
    begin
      _DTR = 1'b0;
      @(posedge DSR);
      # 10;
      _DTR = 1'b1;

      $tkg$send("%m.RD",RD);
      # 10;
      @(negedge DSR);
      # 10;
    end

  always
    begin
      @ (negedge CTS);
      # 10;
      data = $tkg$recv("%m.TD");
      # 10;
      _RTS = 1'b1;
      @ (posedge CTS);
      # 10;
      _RTS = 1'b0;
    end

  assign TD =  data;
  assign RTS = _RTS;
  assign DTR = _DTR;

endmodule
module TTY(TD, RD, RTS, CTS, DSR, DTR);

input CTS, DSR;
input [7:0] RD;
output [7:0] TD;
output RTS, DTR;
reg _RTS, _DTR;
reg [7:0] data;

  initial
    begin
      _RTS = 0;
      data = 0;
      _DTR = 0;
    end

  initial $tkg$post("TTY","%m");

  always
    begin
      _DTR = 1'b0;
      @(posedge DSR);
      # 10;
      _DTR = 1'b1;

      $tkg$send("%m.RD",RD);
      # 10;
      @(negedge DSR);
      # 10;
    end

  always
    begin
      @ (negedge CTS);
      # 10;
      data = $tkg$recv("%m.TD");
      # 10;
      _RTS = 1'b1;
      @ (posedge CTS);
      # 10;
      _RTS = 1'b0;
    end

  assign TD =  data;
  assign RTS = _RTS;
  assign DTR = _DTR;

endmodule