data/full_repos/permissive/114459345/srcCache/if_id.v
1: b'%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:10: Define or directive not defined: \'`CtrlWidth\'\n input wire[`CtrlWidth]   stall,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`CtrlWidth]   stall,\n                      ^\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`InstAddrBus] if_pc,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:16: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] if_pc,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:17: Define or directive not defined: \'`InstBus\'\n input wire[`InstBus]  if_inst,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:20: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus] id_pc,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:21: Define or directive not defined: \'`InstBus\'\n output reg[`InstBus]  id_inst\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:27: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:28: Define or directive not defined: \'`ZeroWord\'\n   id_pc <= `ZeroWord;    \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:29: Define or directive not defined: \'`ZeroWord\'\n   id_inst <= `ZeroWord;   \n              ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:31: Define or directive not defined: \'`Jump\'\n  else if(jumpout == `Jump) begin\n                     ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:32: Define or directive not defined: \'`ZeroWord\'\n   id_pc <= `ZeroWord;   \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:33: Define or directive not defined: \'`ZeroWord\'\n   id_inst <= `ZeroWord;   \n              ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:35: Define or directive not defined: \'`ID_BIT\'\n  else if(stall[`ID_BIT] == `Stop) begin\n                ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:35: Define or directive not defined: \'`Stop\'\n  else if(stall[`ID_BIT] == `Stop) begin\n                            ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:36: Define or directive not defined: \'`EX_BIT\'\n   if(stall[`EX_BIT] == `Continue) begin\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:36: Define or directive not defined: \'`Continue\'\n   if(stall[`EX_BIT] == `Continue) begin\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:37: Define or directive not defined: \'`ZeroWord\'\n    id_pc <= `ZeroWord;   \n             ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:38: Define or directive not defined: \'`ZeroWord\'\n    id_inst <= `ZeroWord;   \n               ^~~~~~~~~\n%Error: Exiting due to 20 error(s)\n'
module if_id(

	input wire clk,
	input wire rst,
	

	input wire[`CtrlWidth] 		stall,
	

	input wire jumpout,
	

	input wire[`InstAddrBus]	if_pc,
	input wire[`InstBus]		if_inst,
	

	output reg[`InstAddrBus]	id_pc,
	output reg[`InstBus]		id_inst
	
);
	

	always @ (posedge clk) begin
		if(rst == `RstEnable) begin
			id_pc <= `ZeroWord;
			id_inst <= `ZeroWord;
		end
		else if(jumpout == `Jump) begin
			id_pc <= `ZeroWord;			
			id_inst <= `ZeroWord;
		end
		else if(stall[`ID_BIT] == `Stop) begin
			if(stall[`EX_BIT] == `Continue) begin
				id_pc <= `ZeroWord;			
				id_inst <= `ZeroWord;
			end
			else begin

			end
		end
		else begin
			id_pc <= if_pc;
			id_inst <= if_inst;
		end
	end
	
endmodule
module if_id(

	input wire clk,
	input wire rst,
	

	input wire[`CtrlWidth] 		stall,
	

	input wire jumpout,
	

	input wire[`InstAddrBus]	if_pc,
	input wire[`InstBus]		if_inst,
	

	output reg[`InstAddrBus]	id_pc,
	output reg[`InstBus]		id_inst
	
);

	

	always @ (posedge clk) begin
		if(rst == `RstEnable) begin
			id_pc <= `ZeroWord;
			id_inst <= `ZeroWord;
		end
		else if(jumpout == `Jump) begin
			id_pc <= `ZeroWord;			
			id_inst <= `ZeroWord;
		end
		else if(stall[`ID_BIT] == `Stop) begin
			if(stall[`EX_BIT] == `Continue) begin
				id_pc <= `ZeroWord;			
				id_inst <= `ZeroWord;
			end
			else begin

			end
		end
		else begin
			id_pc <= if_pc;
			id_inst <= if_inst;
		end
	end
	
endmodule