data/full_repos/permissive/14657119/ms_clock.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/14657119/ms_clock.v:6: Little bit endian vector: MSB < LSB of bit range: 0:17\n reg [0:17] count;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ms_clock(clock, ms_clock);

	input clock;
	output ms_clock;
	reg ms_clock;
	reg [0:17] count;
	

	always @ (posedge clock)
		begin
			count <= count + 1;
			if (count == 250000)
				begin
					ms_clock <= ~ms_clock;
					count <= 0;
				end
		end
endmodule
module ms_clock(clock, ms_clock);


	input clock;
	output ms_clock;
	reg ms_clock;
	reg [0:17] count;
	

	always @ (posedge clock)
		begin
			count <= count + 1;
			if (count == 250000)
				begin
					ms_clock <= ~ms_clock;
					count <= 0;
				end
		end
endmodule