data/full_repos/permissive/143278/ivltests/dffsynth6.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #1 rst <= 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q0 !== 1\'b0 || q1 !== 1\'b0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #1 rst <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q0 !== 1\'b0 || q1 !== 1\'b0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:48: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/dffsynth6.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (q0 !== d0 || q1 !== d1) begin\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/dffsynth6.v:37: Operator NEQCASE expects 2 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance main\n      #1 if (q0 !== 1\'b0 || q1 !== 1\'b0) begin\n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/dffsynth6.v:43: Operator NEQCASE expects 2 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance main\n      #1 if (q0 !== 1\'b0 || q1 !== 1\'b0) begin\n                               ^~~\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DFF
  (output reg Q0,
   output reg [1:0] Q1,
   input wire D0,
   input wire [1:0] D1,
   input wire CLK,
   input wire RST
);

   always @(posedge CLK or posedge RST)
     if (RST) begin
	Q0 <= 0;
	Q1 <= 0;
     end else begin
	Q0 <= D0;
	Q1 <= D1;
     end

endmodule
module DFF
  (output reg Q0,
   output reg [1:0] Q1,
   input wire D0,
   input wire [1:0] D1,
   input wire CLK,
   input wire RST
);


   always @(posedge CLK or posedge RST)
     if (RST) begin
	Q0 <= 0;
	Q1 <= 0;
     end else begin
	Q0 <= D0;
	Q1 <= D1;
     end

endmodule