data/full_repos/permissive/165846232/components/Synchronizer/Synchronizer.v
data/verilator_xmls/95c1c464-ef90-4d83-a54d-8643328bb861.xml
module Synchronizer
#(
  parameter NUM_STAGES = 2
) (
  output Output,
  input  Input,
  input  Clk
);
 
  reg [NUM_STAGES:1] SyncReg;
 
  always @(posedge Clk)
  begin
    SyncReg <= { SyncReg[NUM_STAGES-1:1], Input };
  end
 
  assign Output = SyncReg[NUM_STAGES];
 
endmodule
module Synchronizer
#(
  parameter NUM_STAGES = 2
) (
  output Output,
  input  Input,
  input  Clk
);

 
  reg [NUM_STAGES:1] SyncReg;
 
  always @(posedge Clk)
  begin
    SyncReg <= { SyncReg[NUM_STAGES-1:1], Input };
  end
 
  assign Output = SyncReg[NUM_STAGES];
 
endmodule