data/full_repos/permissive/205919221/src/ocram_sp.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/ea54adfb-5c8d-46de-be67-8efb85ab7c81.xml
module ocram_sp #(
  parameter DWIDTH = 32,
  parameter AWIDTH = 14
) (
  input  wire              clk_i,

  input  wire              ce_i,
  input  wire              we_i,
  input  wire [AWIDTH-1:0] addr_i,
  input  wire [DWIDTH-1:0] d_i,
  output reg  [DWIDTH-1:0] q_o
);

reg [DWIDTH-1:0] ram [2**AWIDTH-1:0];

always @ (posedge clk_i)
begin


  if (ce_i == 1'b1) begin
    if (we_i == 1'b1) begin
      ram[addr_i] <= d_i;
    end else begin
      q_o <= ram[addr_i];
    end
  end
end

endmodule
module ocram_sp #(
  parameter DWIDTH = 32,
  parameter AWIDTH = 14
) (
  input  wire              clk_i,

  input  wire              ce_i,
  input  wire              we_i,
  input  wire [AWIDTH-1:0] addr_i,
  input  wire [DWIDTH-1:0] d_i,
  output reg  [DWIDTH-1:0] q_o
);


reg [DWIDTH-1:0] ram [2**AWIDTH-1:0];

always @ (posedge clk_i)
begin


  if (ce_i == 1'b1) begin
    if (we_i == 1'b1) begin
      ram[addr_i] <= d_i;
    end else begin
      q_o <= ram[addr_i];
    end
  end
end

endmodule