data/full_repos/permissive/162571337/adders/8_unsigned/pareto_pwr_wce/add8u_04A.v
data/verilator_xmls/def130d0-741f-459f-b255-4dcb586afa72.xml
module add8u_04A(A, B, O);
  input [7:0] A, B;
  output [8:0] O;
  assign O[3] = 1'b1;
  assign O[2] = 1'b1;
  assign O[6] = 1'b0;
  assign O[0] = A[7];
  assign O[1] = A[0];
  assign O[4] = A[5];
  assign O[5] = A[3];
  assign O[7] = B[7];
  assign O[8] = O[0];
endmodule
module add8u_04A(A, B, O);

  input [7:0] A, B;
  output [8:0] O;
  assign O[3] = 1'b1;
  assign O[2] = 1'b1;
  assign O[6] = 1'b0;
  assign O[0] = A[7];
  assign O[1] = A[0];
  assign O[4] = A[5];
  assign O[5] = A[3];
  assign O[7] = B[7];
  assign O[8] = O[0];
endmodule