data/full_repos/permissive/105948944/simulations/PWM_testBench.v
 line:29: before: "."
1: b'%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #5000\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #5000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #5000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #5000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #5000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #5000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #5000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #1 clock = ~clock;  \n    ^\n%Error: data/full_repos/permissive/105948944/simulations/PWM_testBench.v:31: Cannot find file containing module: \'PWM_v3\'\n    PWM_v3 UUT\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/PWM_v3\n             data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/PWM_v3.v\n             data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/PWM_v3.sv\n             PWM_v3\n             PWM_v3.v\n             PWM_v3.sv\n             obj_dir/PWM_v3\n             obj_dir/PWM_v3.v\n             obj_dir/PWM_v3.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PWM_testBench(         
);
    reg clock = 0;
    reg [2:0] speed;

    wire PWM_pulse;
    wire [27:0] debugCustomClkCounter_wire;
    
    defparam UUT.PERIOD = 28'd2500; 
    
    PWM_v3 UUT
    (
        .clock(clock),


        .dutyCycle(speed),

        .PWM_pulse(PWM_pulse),
        .debugCounter(debugCustomClkCounter_wire)
    );
    
    initial 
    begin

        speed <= 3'd1;
        #5000
        
        speed <= 3'd2;
        #5000
        
        speed <= 3'd3;
        #5000
        
        speed <= 3'd4;
        #5000
        
        speed <= 3'd5; 
        #5000
        
        speed <= 3'd6;
        #5000
        
        speed <= 3'd7; 
        #5000
        
        speed <= 3'd0;
    end
    
    always begin
    #1 clock = ~clock;
    end

endmodule
module PWM_testBench(         
);

    reg clock = 0;
    reg [2:0] speed;

    wire PWM_pulse;
    wire [27:0] debugCustomClkCounter_wire;
    
    defparam UUT.PERIOD = 28'd2500; 
    
    PWM_v3 UUT
    (
        .clock(clock),


        .dutyCycle(speed),

        .PWM_pulse(PWM_pulse),
        .debugCounter(debugCustomClkCounter_wire)
    );
    
    initial 
    begin

        speed <= 3'd1;
        #5000
        
        speed <= 3'd2;
        #5000
        
        speed <= 3'd3;
        #5000
        
        speed <= 3'd4;
        #5000
        
        speed <= 3'd5; 
        #5000
        
        speed <= 3'd6;
        #5000
        
        speed <= 3'd7; 
        #5000
        
        speed <= 3'd0;
    end
    
    always begin
    #1 clock = ~clock;
    end

endmodule