data/full_repos/permissive/214620165/rtl/e203_clkgate.v
None: at end of input
1: b'%Error: data/full_repos/permissive/214620165/rtl/e203_clkgate.v:34: Cannot find include file: ../../rtl/e203_defines.v\n`include "../../rtl/e203_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214620165/rtl,data/full_repos/permissive/214620165/../../rtl/e203_defines.v\n             data/full_repos/permissive/214620165/rtl,data/full_repos/permissive/214620165/../../rtl/e203_defines.v.v\n             data/full_repos/permissive/214620165/rtl,data/full_repos/permissive/214620165/../../rtl/e203_defines.v.sv\n             ../../rtl/e203_defines.v\n             ../../rtl/e203_defines.v.v\n             ../../rtl/e203_defines.v.sv\n             obj_dir/../../rtl/e203_defines.v\n             obj_dir/../../rtl/e203_defines.v.v\n             obj_dir/../../rtl/e203_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module e203_clkgate (
  input   clk_in,
  input   test_mode,
  input   clock_en,
  output  clk_out
);

`ifdef FPGA_SOURCE

    assign clk_out = clk_in;
`endif

`ifndef FPGA_SOURCE

reg enb;

always@(*)
  if (!clk_in)
    enb = (clock_en | test_mode);

assign clk_out = enb & clk_in;

`endif

endmodule
module e203_clkgate (
  input   clk_in,
  input   test_mode,
  input   clock_en,
  output  clk_out
);


`ifdef FPGA_SOURCE

    assign clk_out = clk_in;
`endif

`ifndef FPGA_SOURCE

reg enb;

always@(*)
  if (!clk_in)
    enb = (clock_en | test_mode);

assign clk_out = enb & clk_in;

`endif

endmodule