data/full_repos/permissive/181665138/verilog/capitolo_iii/SR_Latch_Reset.v
data/verilator_xmls/d38d17a2-5c59-4c12-aa93-d2b4bb09ed21.xml
module SR_Latch_Reset(q, qN, s, r, preset_, preclear_);
    input s, r, preset_, preclear_;
    output q, qN;

    assign #1 q = ~((preset_ & r) | qN | ~preclear_);
    assign #1 qN = ~(~preset_ | (s & preclear_) | q);
endmodule
module SR_Latch_Reset(q, qN, s, r, preset_, preclear_);

    input s, r, preset_, preclear_;
    output q, qN;

    assign #1 q = ~((preset_ & r) | qN | ~preclear_);
    assign #1 qN = ~(~preset_ | (s & preclear_) | q);
endmodule