data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/or_gate.v
data/verilator_xmls/e078fd73-c1d1-4b31-9016-b7914cf54894.xml
module or_gate(input wire x, input wire y, output wire z);




assign z = x | y;

endmodule
module or_gate(input wire x, input wire y, output wire z);





assign z = x | y;

endmodule