data/full_repos/permissive/17894630/Single-Cycle/Core.v
1: b'%Error: data/full_repos/permissive/17894630/Single-Cycle/Core.v:111: Cannot find file containing module: \'regfile\'\n regfile registers(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17894630/Single-Cycle,data/full_repos/permissive/17894630/regfile\n             data/full_repos/permissive/17894630/Single-Cycle,data/full_repos/permissive/17894630/regfile.v\n             data/full_repos/permissive/17894630/Single-Cycle,data/full_repos/permissive/17894630/regfile.sv\n             regfile\n             regfile.v\n             regfile.sv\n             obj_dir/regfile\n             obj_dir/regfile.v\n             obj_dir/regfile.sv\n%Error: data/full_repos/permissive/17894630/Single-Cycle/Core.v:132: Cannot find file containing module: \'IMem\'\n IMem imem (\n ^~~~\n%Error: data/full_repos/permissive/17894630/Single-Cycle/Core.v:139: Cannot find file containing module: \'DMem\'\n DMem dmem_0 (\n ^~~~\n%Error: data/full_repos/permissive/17894630/Single-Cycle/Core.v:146: Cannot find file containing module: \'DMem\'\n DMem dmem_1 (\n ^~~~\n%Error: data/full_repos/permissive/17894630/Single-Cycle/Core.v:153: Cannot find file containing module: \'DMem\'\n DMem dmem_2 (\n ^~~~\n%Error: data/full_repos/permissive/17894630/Single-Cycle/Core.v:160: Cannot find file containing module: \'DMem\'\n DMem dmem_3 (\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/17894630/Single-Cycle/Core.v:294: Operator CASE expects 32 or 17 bits on the Case expression, but Case expression\'s SEL generates 11 bits.\n                                                                           : ... In instance Core\n    case (instr[10:0])\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/17894630/Single-Cycle/Core.v:294: Operator CASE expects 32 or 17 bits on the Case Item, but Case Item\'s CONST \'11\'h20\' generates 11 bits.\n                                                                           : ... In instance Core\n    case (instr[10:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/17894630/Single-Cycle/Core.v:294: Operator CASE expects 32 or 17 bits on the Case Item, but Case Item\'s CONST \'11\'h21\' generates 11 bits.\n                                                                           : ... In instance Core\n    case (instr[10:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/17894630/Single-Cycle/Core.v:294: Operator CASE expects 32 or 17 bits on the Case Item, but Case Item\'s CONST \'11\'h22\' generates 11 bits.\n                                                                           : ... In instance Core\n    case (instr[10:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/17894630/Single-Cycle/Core.v:294: Operator CASE expects 32 or 17 bits on the Case Item, but Case Item\'s CONST \'11\'h24\' generates 11 bits.\n                                                                           : ... In instance Core\n    case (instr[10:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/17894630/Single-Cycle/Core.v:294: Operator CASE expects 32 or 17 bits on the Case Item, but Case Item\'s CONST \'11\'h25\' generates 11 bits.\n                                                                           : ... In instance Core\n    case (instr[10:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/17894630/Single-Cycle/Core.v:294: Operator CASE expects 32 or 17 bits on the Case Item, but Case Item\'s CONST \'11\'h26\' generates 11 bits.\n                                                                           : ... In instance Core\n    case (instr[10:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/17894630/Single-Cycle/Core.v:294: Operator CASE expects 32 or 17 bits on the Case Item, but Case Item\'s CONST \'11\'h0\' generates 11 bits.\n                                                                           : ... In instance Core\n    case (instr[10:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/17894630/Single-Cycle/Core.v:294: Operator CASE expects 32 or 17 bits on the Case Item, but Case Item\'s CONST \'11\'h8\' generates 11 bits.\n                                                                           : ... In instance Core\n    case (instr[10:0])\n    ^~~~\n%Error: Exiting due to 6 error(s), 9 warning(s)\n'
module Core(
    input clk,
    input nrst,
	 input [2:0] R1,
	 output wire[7:0] R2

	 );

	 reg[31:0] ALUOut;
	 wire[31:0] instr;
    reg[5:0] daddr;
    wire[31:0] dout;
    reg[3:0] wr;
	 reg[31:0] pc; 
	 wire[31:0] reg_din;
	 wire[4:0] reg_raddr1;
	 wire[31:0] reg_dout1;
	 wire[4:0] reg_raddr2;
	 wire[31:0] reg_dout2;
	 reg wr_reg;
	 wire[4:0] reg_wr_addr;
	 reg[3:0] ALUOp;
	 reg ALUSrc;
	 wire[31:0] ALUIn2;
	 reg MemToReg;
	 reg RegDst;
	 wire PCSrc;
	 wire Zero;
	 reg Branch;
	 reg Jump;
	 













	wire[31:0] next_pc;


	reg[4:0] shamt;

	wire nclk;
	assign nclk = !(clk);
	regfile registers(
					nclk,
					reg_raddr1,
					reg_dout1,
					reg_raddr2,
					reg_dout2,
					wr_reg,
					reg_wr_addr,
					reg_din,
					R1,
					R2,
					nrst

					);
	
	



	IMem imem (
				  nclk,
				  1'b0,
				  pc[7:2],
				  32'b0,
				  instr
					);
	DMem dmem_0 (
					  nclk,
					  wr[0],
					  daddr[5:0],
					  reg_dout2[7:0],
					  dout[7:0]
					);
	DMem dmem_1 (
					  nclk,
					  wr[1],
					  daddr[5:0],
					  reg_dout2[15:8],
					  dout[15:8]
					);
	DMem dmem_2 (
					  nclk,
					  wr[2],
					  daddr[5:0],
					  reg_dout2[23:16],
					  dout[23:16]
					);
	DMem dmem_3 (
					  nclk,
					  wr[3],
					  daddr[5:0],
					  reg_dout2[31:24],
					  dout[31:24]
					);	
	wire[31:0] JDest;
	reg JR;


		assign JDest = JR ? (reg_dout1 << 2) : {4'b0000, instr[25:0], 2'b00};


		assign PCSrc = Branch & Zero;
		assign next_pc = PCSrc ? ((({{16{instr[15]}}, instr[15:0]}) << 2) + (pc + 32'b100)) : (Jump ? JDest : (pc + 32'b100));

		assign reg_wr_addr = RegDst ? instr[15:11] : instr[20:16];
		assign reg_raddr1 = instr[25:21];
		assign reg_raddr2 = instr[20:16];

		assign ALUIn2 = ALUSrc ? {{16{instr[15]}}, instr[15:0]} : reg_dout2;

		assign reg_din = MemToReg ? dout : ALUOut;				
		
		assign Zero = (ALUOut == 32'b0) ? 1 : 0;

	always @(posedge clk or negedge nrst)
	begin
		if (~nrst)
		begin
			pc = 32'b0;

		end
		else
		begin
			pc = next_pc;
		end
	end
	

	always @(posedge clk)
	begin
		if (instr[31:26] == 6'b001000)
			ALUOp = 4'b0000;
		case (instr[31:26])
		6'b000000 :
		begin

			case (instr[10:0])
				11'b00000100000 :
				begin
					ALUOp = 4'b0000;
				end
				11'b00000100100 :
				begin
					ALUOp = 4'b0001;
				end
				11'b00000100101:
					begin
						ALUOp = 4'b0010;
					end
				11'b00000100110:
					begin
						ALUOp = 4'b0111;
					end
				11'b00000011010, 11'b00000011011 :
				begin
					ALUOp = 4'b0101;
				end
				11'b00000011000, 11'b00000011001 :
				begin
					ALUOp = 4'b0110;
				end
				default :
				begin
					case(instr[5:0])
							6'b000000 :
							begin
								ALUOp = 4'b0011;
							end
					endcase
				end
			endcase
		end
		6'b001101 :
			ALUOp = 4'b0010;
		6'b001110 :
			ALUOp = 4'b0111;
		6'b001100 :
			ALUOp = 4'b0001;
		6'b001000 , 6'b001001 :
			ALUOp = 4'b0000;
		6'b00100, 6'b000001, 6'b000111, 6'b000110, 6'b000001, 6'b000101 :
			ALUOp = 4'b0100;
		6'b100000 :
			ALUOp = 4'b0000;
		6'b001111 :
			ALUOp = 4'b0000;
		6'b100011 :
			ALUOp = 4'b0000;
		6'b101000 :
			ALUOp = 4'b0000;
		6'b101011 :
			ALUOp = 4'b0000;

		default :


			;
		endcase
	end

	always @(posedge clk)
	begin
		if (instr == 32'b0)
		begin
			wr_reg <= 0;
			wr <= 4'b0000;
			Branch <= 0;
			Jump <= 0;
			Branch <= 0;
		end
		else
		begin
			case (instr[31:26])
			6'b000000 :
			begin

				case (instr[10:0])
					11'b00000100000, 11'b00000100001, 11'b00000100010, 00000100011, 11'b00000100100, 11'b00000100101, 11'b00000100110 :

					begin
						RegDst <= 1;
						ALUSrc <= 0;



						wr_reg <= 1;
						MemToReg <= 0;
						Branch <= 0;
						Jump <= 0;
					end
					11'b00000000000 :
					case(instr[5:0])
						6'b000000 :
						begin
							RegDst <= 1;
							ALUSrc <= 0;


							wr_reg <= 1;
							MemToReg <= 0;
							Branch <= 0;
							Jump <= 0;
							shamt <= instr[10:6];
						end
					endcase
					11'b00000001000 :
						if (instr[20:0] == 21'b1000)
						begin

							wr_reg <= 0;
							wr <= 4'b0000;
							Branch <= 0;
							Jump <= 1;
							JR <= 1;
						end
					default:
						;
				endcase
			end
			6'b001000, 6'b001001, 6'b001100, 6'b001101, 6'b001101 :
			begin
				RegDst <= 0;
				ALUSrc <= 1;

				wr_reg <= 1;
				MemToReg <= 0;
				Branch <= 0;
				Jump <= 0;
			end

			6'b100000 :
				begin
					RegDst <= 0;
					ALUSrc <= 1;
					wr[0] <= 0;
					wr[1] <= 0;
					wr[2] <= 0;
					wr[3] <= 0;
					daddr[5:0] <= ALUOut[5:0];

					wr_reg <= 1;
					MemToReg <= 1;
					Branch <= 0;
					Jump <= 0;
				end
			6'b100011 :
				begin
					RegDst <= 0;
					ALUSrc <= 1;
					wr[0] <= 0;
					wr[1] <= 0;
					wr[2] <= 0;
					wr[3] <= 0;
					daddr[5:0] <= ALUOut[5:0];

					wr_reg <= 1;
					MemToReg <= 1;
					Branch <= 0;
					Jump <= 0;
				end
			6'b101000 :
				begin
					ALUSrc <= 1;
					wr[0] <= 1;
					wr[1] <= 0;
					wr[2] <= 0;
					wr[3] <= 0;

					daddr[5:0] <= ALUOut[5:0];
					wr_reg <= 0;
					MemToReg <= 0;
					Branch <= 0;
					Jump <= 0;
				end
			6'b101011 :
				begin
					ALUSrc <= 1;
					wr[0] <= 1;
					wr[1] <= 1;
					wr[2] <= 1;
					wr[3] <= 1;

					daddr[5:0] <= ALUOut[5:0];
					wr_reg <= 0;
					MemToReg <= 0;
					Branch <= 0;
					Jump <= 0;
				end
			6'b000010 :
			begin
				wr_reg <= 0;
				wr <= 4'b0000;
				Branch <= 0;
				Jump <= 1;
				JR <= 0;
			end

			default :
				;
			endcase
		end
	end


	always @(ALUOp, reg_dout1, ALUIn2, shamt)
	begin

		case (ALUOp)
		4'b0000 :
		begin
			ALUOut <= ALUIn2 + reg_dout1;




		end
		4'b0001 :
		begin
			ALUOut <= reg_dout1 & ALUIn2;
		end
		4'b0010 :
		begin
			ALUOut <= reg_dout1 | ALUIn2;
		end
		4'b0011 :
		begin
			ALUOut <= ALUIn2 << shamt;
		end
		4'b0100 :
		begin
			ALUOut <= reg_dout1 - ALUIn2;
		end


		4'b0111 :
		begin
			ALUOut <= reg_dout1 ^ ALUIn2;
		end
		default :
			;
		endcase
	end

endmodule
module Core(
    input clk,
    input nrst,
	 input [2:0] R1,
	 output wire[7:0] R2

	 );


	 reg[31:0] ALUOut;
	 wire[31:0] instr;
    reg[5:0] daddr;
    wire[31:0] dout;
    reg[3:0] wr;
	 reg[31:0] pc; 
	 wire[31:0] reg_din;
	 wire[4:0] reg_raddr1;
	 wire[31:0] reg_dout1;
	 wire[4:0] reg_raddr2;
	 wire[31:0] reg_dout2;
	 reg wr_reg;
	 wire[4:0] reg_wr_addr;
	 reg[3:0] ALUOp;
	 reg ALUSrc;
	 wire[31:0] ALUIn2;
	 reg MemToReg;
	 reg RegDst;
	 wire PCSrc;
	 wire Zero;
	 reg Branch;
	 reg Jump;
	 













	wire[31:0] next_pc;


	reg[4:0] shamt;

	wire nclk;
	assign nclk = !(clk);
	regfile registers(
					nclk,
					reg_raddr1,
					reg_dout1,
					reg_raddr2,
					reg_dout2,
					wr_reg,
					reg_wr_addr,
					reg_din,
					R1,
					R2,
					nrst

					);
	
	



	IMem imem (
				  nclk,
				  1'b0,
				  pc[7:2],
				  32'b0,
				  instr
					);
	DMem dmem_0 (
					  nclk,
					  wr[0],
					  daddr[5:0],
					  reg_dout2[7:0],
					  dout[7:0]
					);
	DMem dmem_1 (
					  nclk,
					  wr[1],
					  daddr[5:0],
					  reg_dout2[15:8],
					  dout[15:8]
					);
	DMem dmem_2 (
					  nclk,
					  wr[2],
					  daddr[5:0],
					  reg_dout2[23:16],
					  dout[23:16]
					);
	DMem dmem_3 (
					  nclk,
					  wr[3],
					  daddr[5:0],
					  reg_dout2[31:24],
					  dout[31:24]
					);	
	wire[31:0] JDest;
	reg JR;


		assign JDest = JR ? (reg_dout1 << 2) : {4'b0000, instr[25:0], 2'b00};


		assign PCSrc = Branch & Zero;
		assign next_pc = PCSrc ? ((({{16{instr[15]}}, instr[15:0]}) << 2) + (pc + 32'b100)) : (Jump ? JDest : (pc + 32'b100));

		assign reg_wr_addr = RegDst ? instr[15:11] : instr[20:16];
		assign reg_raddr1 = instr[25:21];
		assign reg_raddr2 = instr[20:16];

		assign ALUIn2 = ALUSrc ? {{16{instr[15]}}, instr[15:0]} : reg_dout2;

		assign reg_din = MemToReg ? dout : ALUOut;				
		
		assign Zero = (ALUOut == 32'b0) ? 1 : 0;

	always @(posedge clk or negedge nrst)
	begin
		if (~nrst)
		begin
			pc = 32'b0;

		end
		else
		begin
			pc = next_pc;
		end
	end
	

	always @(posedge clk)
	begin
		if (instr[31:26] == 6'b001000)
			ALUOp = 4'b0000;
		case (instr[31:26])
		6'b000000 :
		begin

			case (instr[10:0])
				11'b00000100000 :
				begin
					ALUOp = 4'b0000;
				end
				11'b00000100100 :
				begin
					ALUOp = 4'b0001;
				end
				11'b00000100101:
					begin
						ALUOp = 4'b0010;
					end
				11'b00000100110:
					begin
						ALUOp = 4'b0111;
					end
				11'b00000011010, 11'b00000011011 :
				begin
					ALUOp = 4'b0101;
				end
				11'b00000011000, 11'b00000011001 :
				begin
					ALUOp = 4'b0110;
				end
				default :
				begin
					case(instr[5:0])
							6'b000000 :
							begin
								ALUOp = 4'b0011;
							end
					endcase
				end
			endcase
		end
		6'b001101 :
			ALUOp = 4'b0010;
		6'b001110 :
			ALUOp = 4'b0111;
		6'b001100 :
			ALUOp = 4'b0001;
		6'b001000 , 6'b001001 :
			ALUOp = 4'b0000;
		6'b00100, 6'b000001, 6'b000111, 6'b000110, 6'b000001, 6'b000101 :
			ALUOp = 4'b0100;
		6'b100000 :
			ALUOp = 4'b0000;
		6'b001111 :
			ALUOp = 4'b0000;
		6'b100011 :
			ALUOp = 4'b0000;
		6'b101000 :
			ALUOp = 4'b0000;
		6'b101011 :
			ALUOp = 4'b0000;

		default :


			;
		endcase
	end

	always @(posedge clk)
	begin
		if (instr == 32'b0)
		begin
			wr_reg <= 0;
			wr <= 4'b0000;
			Branch <= 0;
			Jump <= 0;
			Branch <= 0;
		end
		else
		begin
			case (instr[31:26])
			6'b000000 :
			begin

				case (instr[10:0])
					11'b00000100000, 11'b00000100001, 11'b00000100010, 00000100011, 11'b00000100100, 11'b00000100101, 11'b00000100110 :

					begin
						RegDst <= 1;
						ALUSrc <= 0;



						wr_reg <= 1;
						MemToReg <= 0;
						Branch <= 0;
						Jump <= 0;
					end
					11'b00000000000 :
					case(instr[5:0])
						6'b000000 :
						begin
							RegDst <= 1;
							ALUSrc <= 0;


							wr_reg <= 1;
							MemToReg <= 0;
							Branch <= 0;
							Jump <= 0;
							shamt <= instr[10:6];
						end
					endcase
					11'b00000001000 :
						if (instr[20:0] == 21'b1000)
						begin

							wr_reg <= 0;
							wr <= 4'b0000;
							Branch <= 0;
							Jump <= 1;
							JR <= 1;
						end
					default:
						;
				endcase
			end
			6'b001000, 6'b001001, 6'b001100, 6'b001101, 6'b001101 :
			begin
				RegDst <= 0;
				ALUSrc <= 1;

				wr_reg <= 1;
				MemToReg <= 0;
				Branch <= 0;
				Jump <= 0;
			end

			6'b100000 :
				begin
					RegDst <= 0;
					ALUSrc <= 1;
					wr[0] <= 0;
					wr[1] <= 0;
					wr[2] <= 0;
					wr[3] <= 0;
					daddr[5:0] <= ALUOut[5:0];

					wr_reg <= 1;
					MemToReg <= 1;
					Branch <= 0;
					Jump <= 0;
				end
			6'b100011 :
				begin
					RegDst <= 0;
					ALUSrc <= 1;
					wr[0] <= 0;
					wr[1] <= 0;
					wr[2] <= 0;
					wr[3] <= 0;
					daddr[5:0] <= ALUOut[5:0];

					wr_reg <= 1;
					MemToReg <= 1;
					Branch <= 0;
					Jump <= 0;
				end
			6'b101000 :
				begin
					ALUSrc <= 1;
					wr[0] <= 1;
					wr[1] <= 0;
					wr[2] <= 0;
					wr[3] <= 0;

					daddr[5:0] <= ALUOut[5:0];
					wr_reg <= 0;
					MemToReg <= 0;
					Branch <= 0;
					Jump <= 0;
				end
			6'b101011 :
				begin
					ALUSrc <= 1;
					wr[0] <= 1;
					wr[1] <= 1;
					wr[2] <= 1;
					wr[3] <= 1;

					daddr[5:0] <= ALUOut[5:0];
					wr_reg <= 0;
					MemToReg <= 0;
					Branch <= 0;
					Jump <= 0;
				end
			6'b000010 :
			begin
				wr_reg <= 0;
				wr <= 4'b0000;
				Branch <= 0;
				Jump <= 1;
				JR <= 0;
			end

			default :
				;
			endcase
		end
	end


	always @(ALUOp, reg_dout1, ALUIn2, shamt)
	begin

		case (ALUOp)
		4'b0000 :
		begin
			ALUOut <= ALUIn2 + reg_dout1;




		end
		4'b0001 :
		begin
			ALUOut <= reg_dout1 & ALUIn2;
		end
		4'b0010 :
		begin
			ALUOut <= reg_dout1 | ALUIn2;
		end
		4'b0011 :
		begin
			ALUOut <= ALUIn2 << shamt;
		end
		4'b0100 :
		begin
			ALUOut <= reg_dout1 - ALUIn2;
		end


		4'b0111 :
		begin
			ALUOut <= reg_dout1 ^ ALUIn2;
		end
		default :
			;
		endcase
	end

endmodule