data/full_repos/permissive/202237519/verilog/ripple_carry_adder/Mux_tb.v
 line:36: before: "$"
1: b'%Error: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/Mux_tb.v:1: Cannot find include file: Mux.v\n`include "Mux.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/ripple_carry_adder,data/full_repos/permissive/202237519/Mux.v\n             data/full_repos/permissive/202237519/verilog/ripple_carry_adder,data/full_repos/permissive/202237519/Mux.v.v\n             data/full_repos/permissive/202237519/verilog/ripple_carry_adder,data/full_repos/permissive/202237519/Mux.v.sv\n             Mux.v\n             Mux.v.v\n             Mux.v.sv\n             obj_dir/Mux.v\n             obj_dir/Mux.v.v\n             obj_dir/Mux.v.sv\n%Error: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/Mux_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("Mux_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/Mux_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,Mux_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/Mux_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/ripple_carry_adder/Mux_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #500\n    ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module Mux_tb;

reg [3:0] In;
reg [1:0] Sel;
wire Out;
integer i;

Mux mux0 (In,Sel,Out);

initial begin
    $dumpfile("Mux_tb.vcd");
    $dumpvars(0,Mux_tb);
    for(i = 0; i < 4; i = i+1) 
    begin
        In <= 4'b1001;
        Sel <= i;
        #500;
    end
    #500
    $finish;
end

endmodule
module Mux_tb;


reg [3:0] In;
reg [1:0] Sel;
wire Out;
integer i;

Mux mux0 (In,Sel,Out);

initial begin
    $dumpfile("Mux_tb.vcd");
    $dumpvars(0,Mux_tb);
    for(i = 0; i < 4; i = i+1) 
    begin
        In <= 4'b1001;
        Sel <= i;
        #500;
    end
    #500
    $finish;
end

endmodule