data/full_repos/permissive/143278/ivltests/always3.1.1A.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.1A.v:27: Unsupported: Ignoring delay on this delayed statement.\n         #0; #0; #0;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.1A.v:27: Unsupported: Ignoring delay on this delayed statement.\n         #0; #0; #0;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.1A.v:27: Unsupported: Ignoring delay on this delayed statement.\n         #0; #0; #0;\n                 ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ;

reg [3:0] value1 ;

always begin
         #0; #0; #0;
       end

always value1 = 4'h5 ;

initial
    if(value1 != 4'h5)
	$display("FAILED - 3.1.1A always reg_lvalue = constant\n");
    else
	begin
           $display("PASSED\n");
	   $finish;
        end


endmodule
module main ;


reg [3:0] value1 ;

always begin
         #0; #0; #0;
       end

always value1 = 4'h5 ;

initial
    if(value1 != 4'h5)
	$display("FAILED - 3.1.1A always reg_lvalue = constant\n");
    else
	begin
           $display("PASSED\n");
	   $finish;
        end


endmodule