data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v
 line:43: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #8\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:49: Unsupported or unknown PLI call: $urandom_range\n            x     = $urandom_range(0, 2 ** WIDTH - 1);\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:50: Unsupported or unknown PLI call: $urandom_range\n            shamt = $urandom_range(0, 2 ** SHIFT - 1);\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:56: Unsupported or unknown PLI call: $monitor\n        $monitor("Time:\\t%g, x: %b, shamt: %b, lr_out: %b, rr_out: %b",\n        ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:67: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_05/src/05_rotators/simulation/testbench.v:68: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1);   \n        ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    parameter WIDTH = 8;
    parameter SHIFT = 3;

    reg  [WIDTH - 1:0] x;
    reg  [SHIFT - 1:0] shamt;
    wire [WIDTH - 1:0] lr_out;
    wire [WIDTH - 1:0] rr_out;
 

    left_rotator
    #(
        .WIDTH(WIDTH),
        .SHIFT(SHIFT)
    )
    left_rotator_dut
    (
        .x    (x     ),
        .shamt(shamt ),
        .z    (lr_out)
    );
    
    right_rotator
    #(
        .WIDTH(WIDTH),
        .SHIFT(SHIFT)
    )
    right_rotator_dut
    (
        .x    (x     ),
        .shamt(shamt ),
        .z    (rr_out)
    );
    

    initial begin
        x     = 0;
        shamt = 0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            x     = $urandom_range(0, 2 ** WIDTH - 1);
            shamt = $urandom_range(0, 2 ** SHIFT - 1);
        end
            


    initial 
        $monitor("Time:\t%g, x: %b, shamt: %b, lr_out: %b, rr_out: %b",
                $time,
                x,
                shamt,
                lr_out,
                rr_out
            );
            


    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);
    end
    
endmodule
module testbench;

    parameter WIDTH = 8;
    parameter SHIFT = 3;

    reg  [WIDTH - 1:0] x;
    reg  [SHIFT - 1:0] shamt;
    wire [WIDTH - 1:0] lr_out;
    wire [WIDTH - 1:0] rr_out;
 

    left_rotator
    #(
        .WIDTH(WIDTH),
        .SHIFT(SHIFT)
    )
    left_rotator_dut
    (
        .x    (x     ),
        .shamt(shamt ),
        .z    (lr_out)
    );
    
    right_rotator
    #(
        .WIDTH(WIDTH),
        .SHIFT(SHIFT)
    )
    right_rotator_dut
    (
        .x    (x     ),
        .shamt(shamt ),
        .z    (rr_out)
    );
    

    initial begin
        x     = 0;
        shamt = 0;
        #8
        $stop;
    end
    
    initial
        forever begin
            #1;
            x     = $urandom_range(0, 2 ** WIDTH - 1);
            shamt = $urandom_range(0, 2 ** SHIFT - 1);
        end
            


    initial 
        $monitor("Time:\t%g, x: %b, shamt: %b, lr_out: %b, rr_out: %b",
                $time,
                x,
                shamt,
                lr_out,
                rr_out
            );
            


    initial begin 
        $dumpfile("dump.vcd");
        $dumpvars(1);
    end
    
endmodule