data/full_repos/permissive/201488448/2_circuits/2_sequential/24_counter1000.v
1: b"%Error: data/full_repos/permissive/201488448/2_circuits/2_sequential/24_counter1000.v:12: Cannot find file containing module: 'bcdcount'\n    bcdcount counter0 (clk, reset, c_enable[0], q0);\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201488448/2_circuits/2_sequential,data/full_repos/permissive/201488448/bcdcount\n             data/full_repos/permissive/201488448/2_circuits/2_sequential,data/full_repos/permissive/201488448/bcdcount.v\n             data/full_repos/permissive/201488448/2_circuits/2_sequential,data/full_repos/permissive/201488448/bcdcount.sv\n             bcdcount\n             bcdcount.v\n             bcdcount.sv\n             obj_dir/bcdcount\n             obj_dir/bcdcount.v\n             obj_dir/bcdcount.sv\n%Error: data/full_repos/permissive/201488448/2_circuits/2_sequential/24_counter1000.v:13: Cannot find file containing module: 'bcdcount'\n    bcdcount counter1 (clk, reset, c_enable[1], q1);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201488448/2_circuits/2_sequential/24_counter1000.v:14: Cannot find file containing module: 'bcdcount'\n    bcdcount counter2 (clk, reset, c_enable[2], q2);\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
);
    
    wire [3:0] q0, q1, q2;
    
    assign c_enable = {q1 == 4'd9 && q0 == 4'd9, q0 == 4'd9, 1'b1};

    bcdcount counter0 (clk, reset, c_enable[0], q0);
    bcdcount counter1 (clk, reset, c_enable[1], q1);
    bcdcount counter2 (clk, reset, c_enable[2], q2);
    
    assign OneHertz = {q2 == 4'd9 && q1 == 4'd9 && q0 == 4'd9};

endmodule
module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
);

    
    wire [3:0] q0, q1, q2;
    
    assign c_enable = {q1 == 4'd9 && q0 == 4'd9, q0 == 4'd9, 1'b1};

    bcdcount counter0 (clk, reset, c_enable[0], q0);
    bcdcount counter1 (clk, reset, c_enable[1], q1);
    bcdcount counter2 (clk, reset, c_enable[2], q2);
    
    assign OneHertz = {q2 == 4'd9 && q1 == 4'd9 && q0 == 4'd9};

endmodule