data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/pipeline.v
1: b'%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/pipeline.v:24: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/pipeline.v:34: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] exec_branch_target,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/pipeline.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`DATA_BUS] exec_branch_target,\n                    ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/pipeline.v:38: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`DATA_BUS] fetch_branch_target\n    ^~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/pipeline.v:38: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] fetch_branch_target\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/pipeline.v:41: Define or directive not defined: \'`TRUE\'\n    wire fetch_done = `TRUE;\n                      ^~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/pipeline.v:41: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    wire fetch_done = `TRUE;\n                           ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/pipeline.v:43: Define or directive not defined: \'`DATA_BUS\'\n    reg [`DATA_BUS] fetch_addr;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/pipeline.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`DATA_BUS] fetch_addr;\n                  ^\n%Error: Exiting due to 9 error(s)\n'
module pipeline#(parameter DATA_WIDTH = 32)(
    input clk,
    input rst_n,


    input exec_mem_enable,
    input exec_wb_reg,
    input exec_take_branch,
    input [`DATA_BUS] exec_branch_target,


    output reg fetch_branch,
    output reg [`DATA_BUS] fetch_branch_target
    );
    
    wire fetch_done = `TRUE;

    reg [`DATA_BUS] fetch_addr;





    always @*
    begin
        fetch_branch <= exec_take_branch;
        if (exec_take_branch)
            fetch_branch_target <= exec_branch_target;
        else
            fetch_branch_target <= fetch_addr;
    end

endmodule
module pipeline#(parameter DATA_WIDTH = 32)(
    input clk,
    input rst_n,


    input exec_mem_enable,
    input exec_wb_reg,
    input exec_take_branch,
    input [`DATA_BUS] exec_branch_target,


    output reg fetch_branch,
    output reg [`DATA_BUS] fetch_branch_target
    );

    
    wire fetch_done = `TRUE;

    reg [`DATA_BUS] fetch_addr;





    always @*
    begin
        fetch_branch <= exec_take_branch;
        if (exec_take_branch)
            fetch_branch_target <= exec_branch_target;
        else
            fetch_branch_target <= fetch_addr;
    end

endmodule