data/full_repos/permissive/18477150/lib/shared/sonic_common_gray_clock_crosser.sv
 line:54: before: ";"
1: b'%Warning-WIDTH: data/full_repos/permissive/18477150/lib/shared/sonic_common_gray_clock_crosser.sv:71: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                                    : ... In instance sonic_common_gray_clock_crosser\n logic zeros = {WIDTH{1\'b0}};\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sonic_common_gray_clock_crosser # (
	parameter WIDTH = 8
	) (

	input logic inclock,
	input logic outclock,
	input logic inena,
	input logic outena,
	input logic reset,

	input logic [WIDTH-1:0] data,
	output logic [WIDTH-1:0] q
	);
	

	logic [WIDTH-1:0] gray_data;	
	

	localparam SHIFT_REGISTER_LENGTH = 3;
	
	(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *)
	(* preserve *) reg [WIDTH-1:0] shift_register [0:SHIFT_REGISTER_LENGTH-1];
	
	logic [WIDTH-1:0] q_reg;


	always @ (posedge reset or posedge inclock) begin
		if (reset == 1'b1) begin
			gray_data <= 0;
		end
		else if (inena == 1'b1) begin
			gray_data <= data ^ {1'b0,data[WIDTH-1:1]};
		end
	end
	
	int i_shift;

	always @ (posedge reset or posedge outclock) begin
		if (reset == 1'b1) begin
			for (int i = 0; i < SHIFT_REGISTER_LENGTH; i++) 
				shift_register[i] <= {WIDTH{1'b0}};
		end
		else begin
			for (i_shift = 0; i_shift <= SHIFT_REGISTER_LENGTH-2; i_shift=i_shift+1) begin
				shift_register[i_shift] <= shift_register[i_shift+1];
			end

			shift_register[SHIFT_REGISTER_LENGTH-1] <= gray_data;
		end
	end

	logic [WIDTH-1:0] partial_xor;
	logic zeros = {WIDTH{1'b0}};

	int i_out;

	always @ (posedge reset or posedge outclock) begin
		if (reset == 1'b1) begin
			q_reg <= 0;
			end
		else if (outena == 1'b1) begin
			partial_xor = shift_register[0];
	
			for (i_out = 1; i_out < WIDTH; i_out++) begin
				partial_xor = partial_xor ^ (shift_register[0] >> i_out);
			end
			
			q_reg <= partial_xor;
		end
	end
	

	assign q = q_reg;

endmodule
module sonic_common_gray_clock_crosser # (
	parameter WIDTH = 8
	) (

	input logic inclock,
	input logic outclock,
	input logic inena,
	input logic outena,
	input logic reset,

	input logic [WIDTH-1:0] data,
	output logic [WIDTH-1:0] q
	);

	

	logic [WIDTH-1:0] gray_data;	
	

	localparam SHIFT_REGISTER_LENGTH = 3;
	
	(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS" *)
	(* preserve *) reg [WIDTH-1:0] shift_register [0:SHIFT_REGISTER_LENGTH-1];
	
	logic [WIDTH-1:0] q_reg;


	always @ (posedge reset or posedge inclock) begin
		if (reset == 1'b1) begin
			gray_data <= 0;
		end
		else if (inena == 1'b1) begin
			gray_data <= data ^ {1'b0,data[WIDTH-1:1]};
		end
	end
	
	int i_shift;

	always @ (posedge reset or posedge outclock) begin
		if (reset == 1'b1) begin
			for (int i = 0; i < SHIFT_REGISTER_LENGTH; i++) 
				shift_register[i] <= {WIDTH{1'b0}};
		end
		else begin
			for (i_shift = 0; i_shift <= SHIFT_REGISTER_LENGTH-2; i_shift=i_shift+1) begin
				shift_register[i_shift] <= shift_register[i_shift+1];
			end

			shift_register[SHIFT_REGISTER_LENGTH-1] <= gray_data;
		end
	end

	logic [WIDTH-1:0] partial_xor;
	logic zeros = {WIDTH{1'b0}};

	int i_out;

	always @ (posedge reset or posedge outclock) begin
		if (reset == 1'b1) begin
			q_reg <= 0;
			end
		else if (outena == 1'b1) begin
			partial_xor = shift_register[0];
	
			for (i_out = 1; i_out < WIDTH; i_out++) begin
				partial_xor = partial_xor ^ (shift_register[0] >> i_out);
			end
			
			q_reg <= partial_xor;
		end
	end
	

	assign q = q_reg;

endmodule