data/full_repos/permissive/201275379/test/utility/FIFO_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:3: Cannot find include file: tb.v\n`include "tb.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/test/utility,data/full_repos/permissive/201275379/tb.v\n             data/full_repos/permissive/201275379/test/utility,data/full_repos/permissive/201275379/tb.v.v\n             data/full_repos/permissive/201275379/test/utility,data/full_repos/permissive/201275379/tb.v.sv\n             tb.v\n             tb.v.v\n             tb.v.sv\n             obj_dir/tb.v\n             obj_dir/tb.v.v\n             obj_dir/tb.v.sv\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:10: Define or directive not defined: \'`GEN_TICK\'\n  `GEN_TICK(clk, rst);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:10: syntax error, unexpected \'(\'\n  `GEN_TICK(clk, rst);\n            ^~~\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:39: Define or directive not defined: \'`TICK\'\n      case (`TICK)\n            ^~~~~\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:39: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      case (`TICK)\n                 ^\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:45: syntax error, unexpected \':\'\n        5: begin\n         ^\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:50: syntax error, unexpected INTEGER NUMBER\n        6, 7, 8, 9, 10, 11, 12: begin\n        ^\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:53: Define or directive not defined: \'`TICK\'\n          write_data <= `TICK;\n                        ^~~~~\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:63: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("read_data   ", read_data);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:64: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("is_full     ", is_full);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:65: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("is_empty    ", is_empty);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:66: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("write_en    ", write_en);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:67: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("read_en     ", read_en);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:68: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("read_ptr    ", fifo.read_ptr);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:69: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("write_ptr   ", fifo.write_ptr);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/utility/FIFO_tb.v:71: Define or directive not defined: \'`END_AT_TICK\'\n    `END_AT_TICK(20);\n    ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module FIFO_tb(
  input clk,
  input rst
);

  `GEN_TICK(clk, rst);

  reg write_en, read_en;
  reg[31:0] write_data;
  wire[31:0] read_data;
  wire is_full, is_empty;

  FIFO #(
    .kWidth       (32),
    .kAddrWidth   (4)
  ) fifo(
    .clk          (clk),
    .rst          (rst),
    .flush        (0),
    .write_en     (write_en),
    .write_data   (write_data),
    .read_en      (read_en),
    .read_data    (read_data),
    .is_full      (is_full),
    .is_empty     (is_empty)
  );

  always @(posedge clk) begin
    if (!rst) begin
      write_en <= 0;
      read_en <= 0;
      write_data <= 0;
    end
    else begin
      case (`TICK)
        4: begin
          write_en <= 1;
          read_en <= 0;
          write_data <= 32'h12345678;
        end
        5: begin
          write_en <= 0;
          read_en <= 1;
          write_data <= 0;
        end
        6, 7, 8, 9, 10, 11, 12: begin
          write_en <= 1;
          read_en <= 0;
          write_data <= `TICK;
        end
        13, 14, 15, 16: begin
          write_en <= 0;
          read_en <= 1;
          write_data <= 0;
        end
      endcase
    end

    `DISPLAY("read_data   ", read_data);
    `DISPLAY("is_full     ", is_full);
    `DISPLAY("is_empty    ", is_empty);
    `DISPLAY("write_en    ", write_en);
    `DISPLAY("read_en     ", read_en);
    `DISPLAY("read_ptr    ", fifo.read_ptr);
    `DISPLAY("write_ptr   ", fifo.write_ptr);
    $display("");
    `END_AT_TICK(20);
  end

endmodule
module FIFO_tb(
  input clk,
  input rst
);


  `GEN_TICK(clk, rst);

  reg write_en, read_en;
  reg[31:0] write_data;
  wire[31:0] read_data;
  wire is_full, is_empty;

  FIFO #(
    .kWidth       (32),
    .kAddrWidth   (4)
  ) fifo(
    .clk          (clk),
    .rst          (rst),
    .flush        (0),
    .write_en     (write_en),
    .write_data   (write_data),
    .read_en      (read_en),
    .read_data    (read_data),
    .is_full      (is_full),
    .is_empty     (is_empty)
  );

  always @(posedge clk) begin
    if (!rst) begin
      write_en <= 0;
      read_en <= 0;
      write_data <= 0;
    end
    else begin
      case (`TICK)
        4: begin
          write_en <= 1;
          read_en <= 0;
          write_data <= 32'h12345678;
        end
        5: begin
          write_en <= 0;
          read_en <= 1;
          write_data <= 0;
        end
        6, 7, 8, 9, 10, 11, 12: begin
          write_en <= 1;
          read_en <= 0;
          write_data <= `TICK;
        end
        13, 14, 15, 16: begin
          write_en <= 0;
          read_en <= 1;
          write_data <= 0;
        end
      endcase
    end

    `DISPLAY("read_data   ", read_data);
    `DISPLAY("is_full     ", is_full);
    `DISPLAY("is_empty    ", is_empty);
    `DISPLAY("write_en    ", write_en);
    `DISPLAY("read_en     ", read_en);
    `DISPLAY("read_ptr    ", fifo.read_ptr);
    `DISPLAY("write_ptr   ", fifo.write_ptr);
    $display("");
    `END_AT_TICK(20);
  end

endmodule