data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v
1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:4: Define or directive not defined: \'`DATA_BUS\'\n    input wire [`DATA_BUS] aluA_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:4: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`DATA_BUS] aluA_i,\n                         ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:5: Define or directive not defined: \'`DATA_BUS\'\n    input wire [`DATA_BUS] aluB_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:6: Define or directive not defined: \'`IFUN_BUS\'\n    input wire [`IFUN_BUS] fun_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:8: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] e_valE_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:10: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg SF_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:11: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg OF_o\n    ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:17: Define or directive not defined: \'`ADDQ\'\n            `ADDQ:\n            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:21: Define or directive not defined: \'`DATA_WIDTH\'\n                    SF_o = e_valE_o[`DATA_WIDTH-1];\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:22: Define or directive not defined: \'`DATA_WIDTH\'\n                    OF_o = (aluA_i[`DATA_WIDTH-1] == aluB_i[`DATA_WIDTH-1]) &&\n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:22: Define or directive not defined: \'`DATA_WIDTH\'\n                    OF_o = (aluA_i[`DATA_WIDTH-1] == aluB_i[`DATA_WIDTH-1]) &&\n                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:23: Define or directive not defined: \'`DATA_WIDTH\'\n                           (aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);\n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:23: Define or directive not defined: \'`DATA_WIDTH\'\n                           (aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);\n                                                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:25: Define or directive not defined: \'`SUBQ\'\n            `SUBQ:\n            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:29: Define or directive not defined: \'`DATA_WIDTH\'\n                    SF_o = e_valE_o[`DATA_WIDTH-1];\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:30: Define or directive not defined: \'`DATA_WIDTH\'\n                    OF_o = (aluA_i[`DATA_WIDTH-1] != aluB_i[`DATA_WIDTH-1]) &&\n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:30: Define or directive not defined: \'`DATA_WIDTH\'\n                    OF_o = (aluA_i[`DATA_WIDTH-1] != aluB_i[`DATA_WIDTH-1]) &&\n                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:31: Define or directive not defined: \'`DATA_WIDTH\'\n                           (aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);\n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:31: Define or directive not defined: \'`DATA_WIDTH\'\n                           (aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);\n                                                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:33: Define or directive not defined: \'`ANDQ\'\n            `ANDQ:\n            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:37: Define or directive not defined: \'`DATA_WIDTH\'\n                    SF_o = e_valE_o[`DATA_WIDTH-1];\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:38: Define or directive not defined: \'`FALSE\'\n                    OF_o = `FALSE;\n                           ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:40: Define or directive not defined: \'`XORQ\'\n            `XORQ:\n            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:44: Define or directive not defined: \'`DATA_WIDTH\'\n                    SF_o = e_valE_o[`DATA_WIDTH-1];\n                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:45: Define or directive not defined: \'`FALSE\'\n                    OF_o = `FALSE;\n                           ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:49: Define or directive not defined: \'`DATA_ZERO\'\n                    e_valE_o = `DATA_ZERO;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:50: Define or directive not defined: \'`FALSE\'\n                    ZF_o = `FALSE;\n                           ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:51: Define or directive not defined: \'`FALSE\'\n                    SF_o = `FALSE;\n                           ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/alu.v:52: Define or directive not defined: \'`FALSE\'\n                    OF_o = `FALSE;\n                           ^~~~~~\n%Error: Exiting due to 30 error(s)\n'
module alu(
    input wire [`DATA_BUS] aluA_i,
    input wire [`DATA_BUS] aluB_i,
    input wire [`IFUN_BUS] fun_i,
    
    output reg [`DATA_BUS] e_valE_o,
    output reg ZF_o,
    output reg SF_o,
    output reg OF_o
    );
    
    always @(*)
    begin
        case(fun_i)
            `ADDQ:
                begin
                    e_valE_o = aluA_i + aluB_i;
                    ZF_o = e_valE_o == 0;
                    SF_o = e_valE_o[`DATA_WIDTH-1];
                    OF_o = (aluA_i[`DATA_WIDTH-1] == aluB_i[`DATA_WIDTH-1]) &&
                           (aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);
                end
            `SUBQ:
                begin
                    e_valE_o = aluA_i - aluB_i;
                    ZF_o = e_valE_o == 0;
                    SF_o = e_valE_o[`DATA_WIDTH-1];
                    OF_o = (aluA_i[`DATA_WIDTH-1] != aluB_i[`DATA_WIDTH-1]) &&
                           (aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);
                end
            `ANDQ:
                begin
                    e_valE_o = aluA_i & aluB_i;
                    ZF_o = e_valE_o == 0;
                    SF_o = e_valE_o[`DATA_WIDTH-1];
                    OF_o = `FALSE;
                end
            `XORQ:
                begin
                    e_valE_o = aluA_i ^ aluB_i;
                    ZF_o = e_valE_o == 0;
                    SF_o = e_valE_o[`DATA_WIDTH-1];
                    OF_o = `FALSE;
                end
            default:
                begin
                    e_valE_o = `DATA_ZERO;
                    ZF_o = `FALSE;
                    SF_o = `FALSE;
                    OF_o = `FALSE;
                end
        endcase
    end
    
endmodule
module alu(
    input wire [`DATA_BUS] aluA_i,
    input wire [`DATA_BUS] aluB_i,
    input wire [`IFUN_BUS] fun_i,
    
    output reg [`DATA_BUS] e_valE_o,
    output reg ZF_o,
    output reg SF_o,
    output reg OF_o
    );

    
    always @(*)
    begin
        case(fun_i)
            `ADDQ:
                begin
                    e_valE_o = aluA_i + aluB_i;
                    ZF_o = e_valE_o == 0;
                    SF_o = e_valE_o[`DATA_WIDTH-1];
                    OF_o = (aluA_i[`DATA_WIDTH-1] == aluB_i[`DATA_WIDTH-1]) &&
                           (aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);
                end
            `SUBQ:
                begin
                    e_valE_o = aluA_i - aluB_i;
                    ZF_o = e_valE_o == 0;
                    SF_o = e_valE_o[`DATA_WIDTH-1];
                    OF_o = (aluA_i[`DATA_WIDTH-1] != aluB_i[`DATA_WIDTH-1]) &&
                           (aluA_i[`DATA_WIDTH-1] != e_valE_o[`DATA_WIDTH-1]);
                end
            `ANDQ:
                begin
                    e_valE_o = aluA_i & aluB_i;
                    ZF_o = e_valE_o == 0;
                    SF_o = e_valE_o[`DATA_WIDTH-1];
                    OF_o = `FALSE;
                end
            `XORQ:
                begin
                    e_valE_o = aluA_i ^ aluB_i;
                    ZF_o = e_valE_o == 0;
                    SF_o = e_valE_o[`DATA_WIDTH-1];
                    OF_o = `FALSE;
                end
            default:
                begin
                    e_valE_o = `DATA_ZERO;
                    ZF_o = `FALSE;
                    SF_o = `FALSE;
                    OF_o = `FALSE;
                end
        endcase
    end
    
endmodule