data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/LNQD1PO4.v
data/verilator_xmls/4a9e3eb0-fbb7-458e-a969-3935a64a84ae.xml
module LNQD1PO4 (
  D
 ,EN
 ,Q
 );
input D ;
input EN ;
output Q ;
reg Q;
always @(negedge EN)
    Q <= D;
endmodule
module LNQD1PO4 (
  D
 ,EN
 ,Q
 );

input D ;
input EN ;
output Q ;
reg Q;
always @(negedge EN)
    Q <= D;
endmodule