data/full_repos/permissive/143278/ivltests/pr1823732.v
data/verilator_xmls/240235e8-50c0-4aec-ad73-9e2b0860f377.xml
module test;
   reg one = 1;
   reg i, k, kr;
   reg [2:0] j, jr;
   initial
     begin
	i = ($signed(3'b111) === 3'b111);
	j = $signed(3'b110) >>> 1;
	jr = $signed(3'b110) >>> one;
	k = (($signed(3'b110) >>> 1) === 3'b111);
	kr = (($signed(3'b110) >>> one) === 3'b111);
	$display("i is '%b'; j is '%b'; k is '%b'", i, j, k);
	$display("runtime ; j is '%b'; k is '%b'", jr, kr);
     end
endmodule
module test;

   reg one = 1;
   reg i, k, kr;
   reg [2:0] j, jr;
   initial
     begin
	i = ($signed(3'b111) === 3'b111);
	j = $signed(3'b110) >>> 1;
	jr = $signed(3'b110) >>> one;
	k = (($signed(3'b110) >>> 1) === 3'b111);
	kr = (($signed(3'b110) >>> one) === 3'b111);
	$display("i is '%b'; j is '%b'; k is '%b'", i, j, k);
	$display("runtime ; j is '%b'; k is '%b'", jr, kr);
     end
endmodule