data/full_repos/permissive/18426314/verilog/xilinx/bb.v
data/verilator_xmls/7734e09d-b458-4cf0-9a18-7020dd7ff9b1.xml
module BB(
	input I,
	input T,
	output wire O,
	output wire B
);
assign  B = T ? 1'bz : I;
assign  O = B;
endmodule
module BB(
	input I,
	input T,
	output wire O,
	output wire B
);

assign  B = T ? 1'bz : I;
assign  O = B;
endmodule