data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Square_root/Square_root_Reciprocal_Cascaded_tb.v
 line:58: before: "real"
1: b'%Error: Cannot find file containing module: Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Square_root/Square_root_Reciprocal_Cascaded_tb.v\n%Error: Exiting due to 3 error(s)\n'
module Square_root_Reciprocal_Cascaded_tb;


	parameter WL = 24;
	parameter LUT_bits = 13;
	parameter LUT_addWidth = 6;
	parameter ITERATION = 1;


	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din;


	wire [WL-1:0] dout;



	reg [WL-1:0] Testdata_vec_NR [`Testdata_Depth-1:0];

	reg [WL-1:0] Simu_Result_Matlab [`Testdata_Depth-1:0];


	real real_din, real_MATLAB_reuslt, real_Xilinx_result;
	real real_mul_1, real_mul_2, real_mul_2_s;
	real real_out_0, real_out_1, real_mul_3, real_mul_3_s;
	real real_mul_4, real_mul_5, real_mul_5_s, real_mul_6, real_mul_6_s;
	real real_fpThree, real_fpThree_2;
	real real_sub_1, real_sub_2;



	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction



	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;




	Square_root_Reciprocal_NR_DirectImplementation
	#(
		.WL(WL),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth),
		.ITERATION(ITERATION)
    )
	Fang_Square_Root_Reciprocal_cascaded_NR 
	(
		.CLK(CLK),
		.nRST(nRST),
		.CE(CE),
		.din(din),
		.dout(dout)
	 );



	integer count;
	real count_mismatched = 0;
	initial begin
	

		$readmemb("ini_input_binary_isqt_NR.txt", Testdata_vec_NR);		
	

		$readmemb("LUT_isqt_NR_iter1.txt", Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.LUT);
		$readmemb("result_binary_isqt_NR.txt", Simu_Result_Matlab);
		nRST = 0; CE = 0;
		@(posedge CLK); nRST = 1; CE = 1;
		
		for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
			din = Testdata_vec_NR[count];
		   $display("MATLAB: %f, Xilinx: %f", unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1), unsigned_fixedToFloat(dout, 1, WL-1));
			if (unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1)==unsigned_fixedToFloat(dout, 1, WL-1))


				$display("MATCHED");
			else begin
				count_mismatched = count_mismatched + 1;
				$display("MISMATCHED HERE <================= !!! ");
				$display("The NO.%d result is not matched, MATLAB: %b, Xilinx: %b ", count, Simu_Result_Matlab[count-1], dout);
			end
			@(posedge CLK);
			if (count==`Testdata_Depth) begin
				$display("Mismatched proporbility: %f", count_mismatched/`Testdata_Depth);
				$finish;
			end
		end
	end
	 


	always @ din real_din = unsigned_fixedToFloat(din, 1, WL-1);
	



	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_1 
			   real_mul_1 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_1, 2, LUT_bits*2-2);

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_2 
				real_mul_2 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_2, 3, WL+LUT_bits*2-3);

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_2_s 
				real_mul_2_s = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_2_s, 2, WL+LUT_bits*2-3);		

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.sub_1 
				real_sub_1 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.sub_1, 2, WL+LUT_bits*2-3);		

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.fpThree 
				real_fpThree = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.fpThree, 2, WL+LUT_bits*2-3);		

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_3 
				real_mul_3 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_3, 3, WL+LUT_bits*3-4);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_3_s
				real_mul_3_s = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_3_s, 1, WL+LUT_bits*3-3);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.out_0 
				real_out_0 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.out_0, 1, WL-1);		


	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_4 
				real_mul_4 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_4, 2, WL*2+LUT_bits*6-6);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_5
				real_mul_5 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_5, 3, WL*3+LUT_bits*6-7);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_5_s
				real_mul_5_s = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_5_s, 2, WL*3+LUT_bits*6-7);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.fpThree_2 
				real_fpThree_2 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.fpThree_2, 2, WL*3+LUT_bits*6-7);		

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.sub_2
				real_sub_2 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.sub_2, 2, WL*3+LUT_bits*6-7);		

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_6
				real_mul_6 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_6, 3, WL*4+LUT_bits*9-10);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_6_s
				real_mul_6_s = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_6_s, 1, WL*4+LUT_bits*9-9);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.out_1 
				real_out_1 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.out_1, 1, WL-1);		


	always @ dout real_Xilinx_result = unsigned_fixedToFloat(dout, 1, WL-1);
	always @ Simu_Result_Matlab[count] real_MATLAB_reuslt = unsigned_fixedToFloat(Simu_Result_Matlab[count], 1, WL-1);
	 
endmodule
module Square_root_Reciprocal_Cascaded_tb;



	parameter WL = 24;
	parameter LUT_bits = 13;
	parameter LUT_addWidth = 6;
	parameter ITERATION = 1;


	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din;


	wire [WL-1:0] dout;



	reg [WL-1:0] Testdata_vec_NR [`Testdata_Depth-1:0];

	reg [WL-1:0] Simu_Result_Matlab [`Testdata_Depth-1:0];


	real real_din, real_MATLAB_reuslt, real_Xilinx_result;
	real real_mul_1, real_mul_2, real_mul_2_s;
	real real_out_0, real_out_1, real_mul_3, real_mul_3_s;
	real real_mul_4, real_mul_5, real_mul_5_s, real_mul_6, real_mul_6_s;
	real real_fpThree, real_fpThree_2;
	real real_sub_1, real_sub_2;



	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction



	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;




	Square_root_Reciprocal_NR_DirectImplementation
	#(
		.WL(WL),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth),
		.ITERATION(ITERATION)
    )
	Fang_Square_Root_Reciprocal_cascaded_NR 
	(
		.CLK(CLK),
		.nRST(nRST),
		.CE(CE),
		.din(din),
		.dout(dout)
	 );



	integer count;
	real count_mismatched = 0;
	initial begin
	

		$readmemb("ini_input_binary_isqt_NR.txt", Testdata_vec_NR);		
	

		$readmemb("LUT_isqt_NR_iter1.txt", Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.LUT);
		$readmemb("result_binary_isqt_NR.txt", Simu_Result_Matlab);
		nRST = 0; CE = 0;
		@(posedge CLK); nRST = 1; CE = 1;
		
		for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
			din = Testdata_vec_NR[count];
		   $display("MATLAB: %f, Xilinx: %f", unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1), unsigned_fixedToFloat(dout, 1, WL-1));
			if (unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1)==unsigned_fixedToFloat(dout, 1, WL-1))


				$display("MATCHED");
			else begin
				count_mismatched = count_mismatched + 1;
				$display("MISMATCHED HERE <================= !!! ");
				$display("The NO.%d result is not matched, MATLAB: %b, Xilinx: %b ", count, Simu_Result_Matlab[count-1], dout);
			end
			@(posedge CLK);
			if (count==`Testdata_Depth) begin
				$display("Mismatched proporbility: %f", count_mismatched/`Testdata_Depth);
				$finish;
			end
		end
	end
	 


	always @ din real_din = unsigned_fixedToFloat(din, 1, WL-1);
	



	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_1 
			   real_mul_1 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_1, 2, LUT_bits*2-2);

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_2 
				real_mul_2 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_2, 3, WL+LUT_bits*2-3);

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_2_s 
				real_mul_2_s = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_2_s, 2, WL+LUT_bits*2-3);		

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.sub_1 
				real_sub_1 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.sub_1, 2, WL+LUT_bits*2-3);		

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.fpThree 
				real_fpThree = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.fpThree, 2, WL+LUT_bits*2-3);		

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_3 
				real_mul_3 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_3, 3, WL+LUT_bits*3-4);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_3_s
				real_mul_3_s = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_3_s, 1, WL+LUT_bits*3-3);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.out_0 
				real_out_0 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.out_0, 1, WL-1);		


	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_4 
				real_mul_4 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_4, 2, WL*2+LUT_bits*6-6);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_5
				real_mul_5 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_5, 3, WL*3+LUT_bits*6-7);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_5_s
				real_mul_5_s = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_5_s, 2, WL*3+LUT_bits*6-7);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.fpThree_2 
				real_fpThree_2 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.fpThree_2, 2, WL*3+LUT_bits*6-7);		

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.sub_2
				real_sub_2 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.sub_2, 2, WL*3+LUT_bits*6-7);		

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_6
				real_mul_6 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_6, 3, WL*4+LUT_bits*9-10);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_6_s
				real_mul_6_s = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.mul_6_s, 1, WL*4+LUT_bits*9-9);			

	always @ Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.out_1 
				real_out_1 = unsigned_fixedToFloat(Square_root_Reciprocal_Cascaded_tb.Fang_Square_Root_Reciprocal_cascaded_NR.out_1, 1, WL-1);		


	always @ dout real_Xilinx_result = unsigned_fixedToFloat(dout, 1, WL-1);
	always @ Simu_Result_Matlab[count] real_MATLAB_reuslt = unsigned_fixedToFloat(Simu_Result_Matlab[count], 1, WL-1);
	 
endmodule