data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v
 line:153: before: "begin"
1: b'%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:88: syntax error, unexpected \'@\'\n      while(rx !== 1\'b1) @(rx);\n                         ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:91: syntax error, unexpected \'@\'\n        while(rx != 1\'b0) @(rx);\n                          ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:92: syntax error, unexpected \'@\'\n        repeat(8) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:94: syntax error, unexpected \'@\'\n           repeat(16) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:97: syntax error, unexpected \'@\'\n        repeat(16) @(posedge clk);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:112: Unsupported: Ignoring delay on this delayed statement.\n   initial #100\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:169: Unsupported: Ignoring delay on this delayed statement.\n         #1000000;\n         ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:171: Unsupported: wait statements\n         wait(gpio);\n         ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:172: Unsupported: Ignoring delay on this delayed statement.\n         if (uart_number == 1) #200000;\n                               ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:213: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:215: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:217: syntax error, unexpected \'@\'\n      repeat (3) @(posedge clk);\n                 ^\n%Error: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/uart_dev.v:219: syntax error, unexpected \'@\'\n        @uart_tx_state;\n        ^\n%Error: Exiting due to 10 error(s), 3 warning(s)\n'
module uart_dev
(
    input  wire        clk,
    input  wire        rst_n,
    input  wire        rx,
    output wire        tx
);
parameter     uart_number=0;
parameter     STRLEN = 80;

    wire [7:0]  data;
    wire        hwrite;
    wire        hready;
    wire [1:0]  htrans;
    wire [31:0] haddr;
    wire        hclk;
    wire        apb_clk;
    wire        gpio;

    assign data    = 8'h0;
    assign hwrite  = 1'b0;
    assign hready  = 1'b0;
    assign htrans  = 2'b0;
    assign haddr   = 32'h0;
    assign hclk    = clk;
    assign apb_clk = clk;
    assign gpio    = 1'b1;

   wire   uart_beh_reset;

   reg [7:0]     buffer[STRLEN:0];
   wire [8*STRLEN-1:0] outbuf;

   reg [7:0]     byte_in;
   reg [7:0]     ptr;
   integer       i;
   wire tx_mid;
   assign #1 tx= tx_mid;
   assign uart_beh_reset = !rst_n;
   initial
   begin
      while(rx !== 1'b1) @(rx);
      forever begin
        byte_in = 8'h20;
        while(rx != 1'b0) @(rx);
        repeat(8) @(posedge clk);
        for ( i=0; i<8; i=i+1 ) begin
           repeat(16) @(posedge clk);
           byte_in[i] = rx;
        end
        repeat(16) @(posedge clk);
        push(byte_in);
      end
   end

   reg [31:0] haddr_d1;
   reg        hwrite_d1;
   always @(posedge hclk) begin
      haddr_d1 <= haddr;
      hwrite_d1<= hwrite && hready && htrans[1];
      if (haddr_d1 == 32'h1f00_03f8 && hwrite_d1) begin
        push(data);
      end
   end

   initial #100
     begin:init_buffer
        for (ptr = 8'h00; ptr < STRLEN; ptr = ptr + 1)
          begin
             buffer[ptr] = 8'h20;
          end
        ptr = 8'h00;
     end

   assign outbuf[639:0] = { buffer[0], buffer[1], buffer[2], buffer[3], buffer[4], buffer[5], buffer[6], buffer[7],
                            buffer[8], buffer[9], buffer[10],buffer[11],buffer[12],buffer[13],buffer[14],buffer[15],
                            buffer[16],buffer[17],buffer[18],buffer[19],buffer[20],buffer[21],buffer[22],buffer[23],
                            buffer[24],buffer[25],buffer[26],buffer[27],buffer[28],buffer[29],buffer[30],buffer[31],
                            buffer[32],buffer[33],buffer[34],buffer[35],buffer[36],buffer[37],buffer[38],buffer[39],
                            buffer[40],buffer[41],buffer[42],buffer[43],buffer[44],buffer[45],buffer[46],buffer[47],
                            buffer[48],buffer[49],buffer[50],buffer[51],buffer[52],buffer[53],buffer[54],buffer[55],
                            buffer[56],buffer[57],buffer[58],buffer[59],buffer[60],buffer[61],buffer[62],buffer[63],
                            buffer[64],buffer[65],buffer[66],buffer[67],buffer[68],buffer[69],buffer[70],buffer[71],
                            buffer[72],buffer[73],buffer[74],buffer[75],buffer[76],buffer[77],buffer[78],buffer[79]};

         
   task push;
      input [7:0] data;
      begin
      buffer[ptr] = (data[7:0]==8'h0D)? 8'h0A : data[7:0];
      ptr = ptr + 1;
      if (data[7:0] == 8'h0A || data[7:0] == 8'h0D)
        begin
           print;
           ptr = 8'h00;
        end
      else if (ptr == STRLEN)
        begin
           print;
           ptr = 8'h00;
        end
      end
   endtask

   task print;
      begin
         $display("[%t]:[uart%1x]: %s", $time, uart_number,outbuf);
         if (outbuf[639:576] == "GouSheng") $finish;
         for (ptr =  8'h00; ptr < STRLEN; ptr = ptr + 1)
           begin
              buffer[ptr] = 8'h20;
           end
      end
   endtask
   
   reg         uart_push;
   reg [7:0]   uart_tx_data;
   wire [2:0]  uart_tx_state;

   initial
     begin
         begin
         #1000000;

         wait(gpio);
         if (uart_number == 1) #200000;

         uart_send_multiple("d4a000000010 ", 32'd13);

         end
     end

   uart_transmitter_v ut( .clk    (apb_clk       ),
                      .wb_rst_i   (uart_beh_reset),
                      .lcr        (8'h3          ),
                      .tf_push    (uart_push     ),
                      .wb_dat_i   (uart_tx_data  ),
                      .enable     (1'b1          ),
                      .stx_pad_o  (tx_mid        ),
                      .tstate     (uart_tx_state ),
                      .tf_count   (              ),
                      .tx_reset   (uart_beh_reset),
                      .lsr_mask   (1'b0          )
                      );
                      
   task uart_send_multiple;
     input [8*80-1: 0] uart_string;
     input [31:0]  len;
     integer send_multi_i;
     begin
        for (send_multi_i=len-1; send_multi_i >=0; send_multi_i = send_multi_i-1) begin
            uart_send({uart_string[send_multi_i*8 + 7],
                       uart_string[send_multi_i*8 + 6],
                       uart_string[send_multi_i*8 + 5],
                       uart_string[send_multi_i*8 + 4],
                       uart_string[send_multi_i*8 + 3],
                       uart_string[send_multi_i*8 + 2],
                       uart_string[send_multi_i*8 + 1],
                       uart_string[send_multi_i*8 + 0]});
        end
     end
   endtask
   task uart_send;
     input [7:0] data;
     begin
      uart_tx_data = data;
      @(posedge clk);
      uart_push = 1'b1;
      @(posedge clk);
      uart_push = 1'b0;
      repeat (3) @(posedge clk);
      while(uart_tx_state != 3'b001)
        @uart_tx_state;
     end
   endtask


endmodule
module uart_dev
(
    input  wire        clk,
    input  wire        rst_n,
    input  wire        rx,
    output wire        tx
);

parameter     uart_number=0;
parameter     STRLEN = 80;

    wire [7:0]  data;
    wire        hwrite;
    wire        hready;
    wire [1:0]  htrans;
    wire [31:0] haddr;
    wire        hclk;
    wire        apb_clk;
    wire        gpio;

    assign data    = 8'h0;
    assign hwrite  = 1'b0;
    assign hready  = 1'b0;
    assign htrans  = 2'b0;
    assign haddr   = 32'h0;
    assign hclk    = clk;
    assign apb_clk = clk;
    assign gpio    = 1'b1;

   wire   uart_beh_reset;

   reg [7:0]     buffer[STRLEN:0];
   wire [8*STRLEN-1:0] outbuf;

   reg [7:0]     byte_in;
   reg [7:0]     ptr;
   integer       i;
   wire tx_mid;
   assign #1 tx= tx_mid;
   assign uart_beh_reset = !rst_n;
   initial
   begin
      while(rx !== 1'b1) @(rx);
      forever begin
        byte_in = 8'h20;
        while(rx != 1'b0) @(rx);
        repeat(8) @(posedge clk);
        for ( i=0; i<8; i=i+1 ) begin
           repeat(16) @(posedge clk);
           byte_in[i] = rx;
        end
        repeat(16) @(posedge clk);
        push(byte_in);
      end
   end

   reg [31:0] haddr_d1;
   reg        hwrite_d1;
   always @(posedge hclk) begin
      haddr_d1 <= haddr;
      hwrite_d1<= hwrite && hready && htrans[1];
      if (haddr_d1 == 32'h1f00_03f8 && hwrite_d1) begin
        push(data);
      end
   end

   initial #100
     begin:init_buffer
        for (ptr = 8'h00; ptr < STRLEN; ptr = ptr + 1)
          begin
             buffer[ptr] = 8'h20;
          end
        ptr = 8'h00;
     end

   assign outbuf[639:0] = { buffer[0], buffer[1], buffer[2], buffer[3], buffer[4], buffer[5], buffer[6], buffer[7],
                            buffer[8], buffer[9], buffer[10],buffer[11],buffer[12],buffer[13],buffer[14],buffer[15],
                            buffer[16],buffer[17],buffer[18],buffer[19],buffer[20],buffer[21],buffer[22],buffer[23],
                            buffer[24],buffer[25],buffer[26],buffer[27],buffer[28],buffer[29],buffer[30],buffer[31],
                            buffer[32],buffer[33],buffer[34],buffer[35],buffer[36],buffer[37],buffer[38],buffer[39],
                            buffer[40],buffer[41],buffer[42],buffer[43],buffer[44],buffer[45],buffer[46],buffer[47],
                            buffer[48],buffer[49],buffer[50],buffer[51],buffer[52],buffer[53],buffer[54],buffer[55],
                            buffer[56],buffer[57],buffer[58],buffer[59],buffer[60],buffer[61],buffer[62],buffer[63],
                            buffer[64],buffer[65],buffer[66],buffer[67],buffer[68],buffer[69],buffer[70],buffer[71],
                            buffer[72],buffer[73],buffer[74],buffer[75],buffer[76],buffer[77],buffer[78],buffer[79]};

         
   task push;
      input [7:0] data;
      begin
      buffer[ptr] = (data[7:0]==8'h0D)? 8'h0A : data[7:0];
      ptr = ptr + 1;
      if (data[7:0] == 8'h0A || data[7:0] == 8'h0D)
        begin
           print;
           ptr = 8'h00;
        end
      else if (ptr == STRLEN)
        begin
           print;
           ptr = 8'h00;
        end
      end
   endtask

   task print;
      begin
         $display("[%t]:[uart%1x]: %s", $time, uart_number,outbuf);
         if (outbuf[639:576] == "GouSheng") $finish;
         for (ptr =  8'h00; ptr < STRLEN; ptr = ptr + 1)
           begin
              buffer[ptr] = 8'h20;
           end
      end
   endtask
   
   reg         uart_push;
   reg [7:0]   uart_tx_data;
   wire [2:0]  uart_tx_state;

   initial
     begin
         begin
         #1000000;

         wait(gpio);
         if (uart_number == 1) #200000;

         uart_send_multiple("d4a000000010 ", 32'd13);

         end
     end

   uart_transmitter_v ut( .clk    (apb_clk       ),
                      .wb_rst_i   (uart_beh_reset),
                      .lcr        (8'h3          ),
                      .tf_push    (uart_push     ),
                      .wb_dat_i   (uart_tx_data  ),
                      .enable     (1'b1          ),
                      .stx_pad_o  (tx_mid        ),
                      .tstate     (uart_tx_state ),
                      .tf_count   (              ),
                      .tx_reset   (uart_beh_reset),
                      .lsr_mask   (1'b0          )
                      );
                      
   task uart_send_multiple;
     input [8*80-1: 0] uart_string;
     input [31:0]  len;
     integer send_multi_i;
     begin
        for (send_multi_i=len-1; send_multi_i >=0; send_multi_i = send_multi_i-1) begin
            uart_send({uart_string[send_multi_i*8 + 7],
                       uart_string[send_multi_i*8 + 6],
                       uart_string[send_multi_i*8 + 5],
                       uart_string[send_multi_i*8 + 4],
                       uart_string[send_multi_i*8 + 3],
                       uart_string[send_multi_i*8 + 2],
                       uart_string[send_multi_i*8 + 1],
                       uart_string[send_multi_i*8 + 0]});
        end
     end
   endtask
   task uart_send;
     input [7:0] data;
     begin
      uart_tx_data = data;
      @(posedge clk);
      uart_push = 1'b1;
      @(posedge clk);
      uart_push = 1'b0;
      repeat (3) @(posedge clk);
      while(uart_tx_state != 3'b001)
        @uart_tx_state;
     end
   endtask


endmodule