data/full_repos/permissive/162400762/timeOut_inspector.v
1: b'%Warning-WIDTH: data/full_repos/permissive/162400762/timeOut_inspector.v:113: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'idx_agingTb\' generates 3 bits.\n                                                                            : ... In instance connection_outTime_inspector\n      agingInfo <= idx_agingTb;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module connection_outTime_inspector(
reset,
clk,
idx_agingTb,
data_agingTb,
rdValid_agingTb,
wrValid_agingTb,
ctx_agingTb,
agingInfo_valid,
agingInfo,
cur_timestamp
);


parameter 	w_agingInfo = 16,
			w_agingTb = 17,
			d_agingTb = 3,
			w_timestamp = 16,

			b_valid_agingTb = 16,
			b_ts_agingTb = 0,
			

			INCREASE_IDX_AGINGTB = 3'd1,
			INTERVAL_AGING = 16'd100;

input							clk;
input							reset;
output	reg	[d_agingTb-1:0]	idx_agingTb;
output	reg	[w_agingTb-1:0]	data_agingTb;
output	reg						rdValid_agingTb;
output	reg						wrValid_agingTb;
input		[w_agingTb-1:0]	ctx_agingTb;
output	reg						agingInfo_valid;
output	reg	[w_agingInfo-1:0]	agingInfo;
input		[w_timestamp-1:0]	cur_timestamp;






reg	[3:0]	state_aging;	
parameter	IDLE_S				= 4'd0,
			WAIT_RAM_1_S		= 4'd1,
			WAIT_RAM_2_S		= 4'd2,
			READ_AGINGTB_S	= 4'd3;



always @(posedge clk or negedge reset) begin
	if (!reset) begin
		idx_agingTb <= {d_agingTb{1'b0}};
		rdValid_agingTb <= 1'b0;
		wrValid_agingTb <= 1'b0;
		data_agingTb <= {w_agingTb{1'b0}};
		agingInfo_valid <= 1'b0;
		agingInfo <= {w_agingInfo{1'b0}};
		
		state_aging <= IDLE_S;
	end
	else begin
		case(state_aging)
			IDLE_S: begin
				wrValid_agingTb <= 1'b0;
				agingInfo_valid <= 1'b0;

				if(idx_agingTb == {d_agingTb{1'b1}})
					idx_agingTb <= INCREASE_IDX_AGINGTB;
				else
					idx_agingTb <= idx_agingTb + INCREASE_IDX_AGINGTB;
				rdValid_agingTb <= 1'b1;
				state_aging <= WAIT_RAM_1_S;
			end
			WAIT_RAM_1_S: begin
				rdValid_agingTb <= 1'b0;
				state_aging <= WAIT_RAM_2_S;
			end
			WAIT_RAM_2_S: begin
				state_aging <= READ_AGINGTB_S;
			end
			READ_AGINGTB_S: begin
				if(ctx_agingTb[b_valid_agingTb] == 1'b1) begin
					if((ctx_agingTb[w_timestamp-1:0] + INTERVAL_AGING ) == 
						cur_timestamp) 
					begin

						wrValid_agingTb <= 1'b1;
						data_agingTb <= {w_agingTb{1'b0}};
						agingInfo_valid <= 1'b1;
						agingInfo <= idx_agingTb;
					end
					else begin
						wrValid_agingTb <= 1'b0;
						agingInfo_valid <= 1'b0;
					end
				end
				state_aging <= IDLE_S;
			end
			default: begin
				state_aging <= IDLE_S;
			end
		endcase
	end
end






endmodule
module connection_outTime_inspector(
reset,
clk,
idx_agingTb,
data_agingTb,
rdValid_agingTb,
wrValid_agingTb,
ctx_agingTb,
agingInfo_valid,
agingInfo,
cur_timestamp
);



parameter 	w_agingInfo = 16,
			w_agingTb = 17,
			d_agingTb = 3,
			w_timestamp = 16,

			b_valid_agingTb = 16,
			b_ts_agingTb = 0,
			

			INCREASE_IDX_AGINGTB = 3'd1,
			INTERVAL_AGING = 16'd100;

input							clk;
input							reset;
output	reg	[d_agingTb-1:0]	idx_agingTb;
output	reg	[w_agingTb-1:0]	data_agingTb;
output	reg						rdValid_agingTb;
output	reg						wrValid_agingTb;
input		[w_agingTb-1:0]	ctx_agingTb;
output	reg						agingInfo_valid;
output	reg	[w_agingInfo-1:0]	agingInfo;
input		[w_timestamp-1:0]	cur_timestamp;






reg	[3:0]	state_aging;	
parameter	IDLE_S				= 4'd0,
			WAIT_RAM_1_S		= 4'd1,
			WAIT_RAM_2_S		= 4'd2,
			READ_AGINGTB_S	= 4'd3;



always @(posedge clk or negedge reset) begin
	if (!reset) begin
		idx_agingTb <= {d_agingTb{1'b0}};
		rdValid_agingTb <= 1'b0;
		wrValid_agingTb <= 1'b0;
		data_agingTb <= {w_agingTb{1'b0}};
		agingInfo_valid <= 1'b0;
		agingInfo <= {w_agingInfo{1'b0}};
		
		state_aging <= IDLE_S;
	end
	else begin
		case(state_aging)
			IDLE_S: begin
				wrValid_agingTb <= 1'b0;
				agingInfo_valid <= 1'b0;

				if(idx_agingTb == {d_agingTb{1'b1}})
					idx_agingTb <= INCREASE_IDX_AGINGTB;
				else
					idx_agingTb <= idx_agingTb + INCREASE_IDX_AGINGTB;
				rdValid_agingTb <= 1'b1;
				state_aging <= WAIT_RAM_1_S;
			end
			WAIT_RAM_1_S: begin
				rdValid_agingTb <= 1'b0;
				state_aging <= WAIT_RAM_2_S;
			end
			WAIT_RAM_2_S: begin
				state_aging <= READ_AGINGTB_S;
			end
			READ_AGINGTB_S: begin
				if(ctx_agingTb[b_valid_agingTb] == 1'b1) begin
					if((ctx_agingTb[w_timestamp-1:0] + INTERVAL_AGING ) == 
						cur_timestamp) 
					begin

						wrValid_agingTb <= 1'b1;
						data_agingTb <= {w_agingTb{1'b0}};
						agingInfo_valid <= 1'b1;
						agingInfo <= idx_agingTb;
					end
					else begin
						wrValid_agingTb <= 1'b0;
						agingInfo_valid <= 1'b0;
					end
				end
				state_aging <= IDLE_S;
			end
			default: begin
				state_aging <= IDLE_S;
			end
		endcase
	end
end






endmodule