data/full_repos/permissive/128426084/src/sources_1/new/MouseCtlVeri.v
1: b'%Error: data/full_repos/permissive/128426084/src/sources_1/new/MouseCtlVeri.v:22: Cannot find include file: verilog_macro_bus.vh\n`include "verilog_macro_bus.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.v\n             data/full_repos/permissive/128426084/src/sources_1/new,data/full_repos/permissive/128426084/verilog_macro_bus.vh.sv\n             verilog_macro_bus.vh\n             verilog_macro_bus.vh.v\n             verilog_macro_bus.vh.sv\n             obj_dir/verilog_macro_bus.vh\n             obj_dir/verilog_macro_bus.vh.v\n             obj_dir/verilog_macro_bus.vh.sv\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/MouseCtlVeri.v:27: Define or directive not defined: \'`MOUSE_BUS_SIZE\'\n    output [`MOUSE_BUS_SIZE-1:0] mouse_out,\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/MouseCtlVeri.v:32: Define or directive not defined: \'`MOUSE_OUT_WIRE\'\n    `MOUSE_OUT_WIRE\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/MouseCtlVeri.v:33: Define or directive not defined: \'`MOUSE_MERGE_AT_OUTPUT\'\n    `MOUSE_MERGE_AT_OUTPUT(mouse_out)\n    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/128426084/src/sources_1/new/MouseCtlVeri.v:33: syntax error, unexpected \'(\'\n    `MOUSE_MERGE_AT_OUTPUT(mouse_out)\n                           ^~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module MouseCtlVeri(
    inout ps2_clk,
    inout ps2_data,
    output [`MOUSE_BUS_SIZE-1:0] mouse_out,
    input rst,
    input clk
    );
    
    `MOUSE_OUT_WIRE
    `MOUSE_MERGE_AT_OUTPUT(mouse_out)
    
    
      MouseCtl myMouse(
      .clk(clk),
      .ps2_clk(ps2_clk),
      .ps2_data(ps2_data),
      .xpos(xpos_out),
      .ypos(ypos_out),
      .left(left_out)
    );
    
endmodule
module MouseCtlVeri(
    inout ps2_clk,
    inout ps2_data,
    output [`MOUSE_BUS_SIZE-1:0] mouse_out,
    input rst,
    input clk
    );

    
    `MOUSE_OUT_WIRE
    `MOUSE_MERGE_AT_OUTPUT(mouse_out)
    
    
      MouseCtl myMouse(
      .clk(clk),
      .ps2_clk(ps2_clk),
      .ps2_data(ps2_data),
      .xpos(xpos_out),
      .ypos(ypos_out),
      .left(left_out)
    );
    
endmodule