data/full_repos/permissive/117851934/ddr_layout_V5/ip/spi_master/hdl/spi_master.v
 line:194: before: "("
1: b"%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/spi_master/hdl/spi_master.v:194: syntax error, unexpected '^', expecting ')'\n  always @ (posedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_woread_send) begin\n                          ^\n%Error: Exiting due to 1 error(s)\n"
module spi_master (
  									clk,
  									reset_n,
  									chipselect,
  									address,
  									read,
  									write,
  									readdata,
  									writedata,
  									interrupt,
  									miso,
  									mosi,
  									sclk,
  									ss
  									);
  									

  parameter numberOfSlaves=1;
  parameter clk_pol=0;
  parameter clk_pha=0;
  

  input clk;
  input reset_n;
  input chipselect;
  input [2:0] address;
  input read;
  input write;
  input [31:0] writedata;
  output [31:0] readdata;
  output interrupt;

  input miso;
  output mosi;
  output sclk;
  output [numberOfSlaves-1:0] ss;
  
  reg [31:0] readdata;
  reg interrupt;
  reg [7:0] shift_register;
  reg [7:0] txdata;
  reg [7:0] rxdata;
  reg [15:0] control;
  wire [15:0] status;
  reg [7:0] divide_num;
  reg [3:0] count;
  reg status_clear;
  reg sclk;
  reg slave_chipselect;
  reg mosi;
  reg spi_woread_send;
  reg [numberOfSlaves-1:0]ss_reg;
  reg [7:0] divide_pre;
  reg spi_clk_gen;
  reg status_toe,status_roe,status_tmt,status_trdy,status_rrdy;
  wire status_e;
  reg read_rx;
  reg CPOL;          
  reg CPHA;
  wire [numberOfSlaves-1:0]ss; 


  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin

      control <= 0;
      txdata <= 0;
      divide_pre <= 1;
      ss_reg <= 1;
  	end else begin
      if (chipselect & read) begin
        case (address) 
        	`addr_rx			: readdata <= {24'b0,rxdata};
          `addr_status 	: readdata <= {16'b0,status};
          `addr_control	: readdata <= {16'b0,control};
        endcase
      end else if(chipselect & write) begin
      	case (address) 
        	`addr_tx 			: txdata <= writedata[7:0];
          `addr_control	: control <= writedata[15:0];
        	`addr_divide	: divide_pre <= writedata[7:0];
        	`addr_chipsel	:	ss_reg <= writedata[numberOfSlaves-1:0];
        endcase 	
      end
    end
  end


  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin
  		spi_woread_send <=0;
  	end else begin
      if (chipselect & write & (address == `addr_tx)) begin
          spi_woread_send <=1;
          if(count!=0) status_toe <= 1;
          else status_toe <= 0;
          if(status_rrdy==1) status_roe <= 1;
          else 	status_roe <= 0;
      end else begin
          spi_woread_send <=0;
      end
    end
  end
  

  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin
  		CPOL <= clk_pol[0];
  		CPHA <= clk_pha[0];
  	end else begin
      if (chipselect & write & (address == `addr_control)) begin
          CPOL <= control[0];	
          CPHA <= control[1];
      end
    end
  end
  

  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin
  		status_clear <=0;
  	end else begin
      if (chipselect & write & (address == `addr_status)) begin
          status_clear <=1;
      end else begin
          status_clear <=0;
      end
    end
  end
  

  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin
  		read_rx <=0;
  	end else begin
      if (chipselect & read & (address == `addr_rx)) begin
          read_rx <=1;
      end else begin
          read_rx <=0;
      end
    end
  end
  

  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin
  		slave_chipselect <= 1;
  	end else begin
      if (spi_woread_send) begin
          slave_chipselect <= 0;
      end else if ((count == 8) & ~(sclk ^ CPOL)) begin
          slave_chipselect <= 1;
      end 
    end   
  end
  

  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin
  		divide_num <= 0;
  	end else begin
      divide_num <= divide_num + 8'h1; 
      if( divide_num>= divide_pre) begin
      	divide_num <= 0 ;  
      	spi_clk_gen <= ~spi_clk_gen;
      end
    end
  end


  always @ (posedge spi_clk_gen) begin
      if (~slave_chipselect) begin
          sclk <= ~sclk;
      end else if (~CPOL) begin
          sclk <= 0;
      end else begin
          sclk <= 1;
      end
  end
  

  always @ (posedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_woread_send) begin
      if (spi_woread_send) begin
          shift_register[7:0] = txdata;
      end else begin 
          shift_register = shift_register << 1;
          shift_register[0] = miso;
      end
  end
  

  always @ (negedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_woread_send) begin
      if (spi_woread_send) begin
          mosi = txdata[7];
      end else begin 
          mosi = shift_register[7];
      end
  end


  always @ (posedge slave_chipselect or negedge reset_n) begin
  	if (!reset_n) begin
  		status_tmt <= 1;
  		status_trdy <= 1;
  	end else if(slave_chipselect) begin
  		rxdata <= shift_register;
  		status_tmt <= 1;
  		status_trdy <= 1;
  	end else begin
  		status_tmt <= 0;
  		status_trdy <= 0;
  	end
  end









  

  always @ (posedge sclk or posedge slave_chipselect or posedge read_rx or negedge reset_n) begin
  	if (!reset_n) begin
  		status_rrdy <= 0;
  	end else if(slave_chipselect==1) begin
  		if(read_rx==0) status_rrdy <= 1;
  		else status_rrdy <= 0;
  	end else if (read_rx) begin
  		status_rrdy <= 0;
  	end else begin
  		status_rrdy <= status_rrdy;	
  	end
  end 
  

  always @ (posedge sclk or posedge slave_chipselect or negedge reset_n) begin
  	if (!reset_n) begin
  		count = 0;
  	end else begin
      if (slave_chipselect) begin
          count <= 0;
      end else begin   
          count <= count + 4'h1;
      end
    end
  end
  














  

  assign status_e = status_toe | status_roe;
  assign ss = ((control & 16'h400) | (~slave_chipselect)) ?  ~ss_reg : {numberOfSlaves{1'b1}}; 
  assign status = {7'h0,status_e,status_rrdy,status_trdy,status_tmt,status_toe,status_roe,3'h0}; 
  endmodule
module spi_master (
  									clk,
  									reset_n,
  									chipselect,
  									address,
  									read,
  									write,
  									readdata,
  									writedata,
  									interrupt,
  									miso,
  									mosi,
  									sclk,
  									ss
  									);

  									

  parameter numberOfSlaves=1;
  parameter clk_pol=0;
  parameter clk_pha=0;
  

  input clk;
  input reset_n;
  input chipselect;
  input [2:0] address;
  input read;
  input write;
  input [31:0] writedata;
  output [31:0] readdata;
  output interrupt;

  input miso;
  output mosi;
  output sclk;
  output [numberOfSlaves-1:0] ss;
  
  reg [31:0] readdata;
  reg interrupt;
  reg [7:0] shift_register;
  reg [7:0] txdata;
  reg [7:0] rxdata;
  reg [15:0] control;
  wire [15:0] status;
  reg [7:0] divide_num;
  reg [3:0] count;
  reg status_clear;
  reg sclk;
  reg slave_chipselect;
  reg mosi;
  reg spi_woread_send;
  reg [numberOfSlaves-1:0]ss_reg;
  reg [7:0] divide_pre;
  reg spi_clk_gen;
  reg status_toe,status_roe,status_tmt,status_trdy,status_rrdy;
  wire status_e;
  reg read_rx;
  reg CPOL;          
  reg CPHA;
  wire [numberOfSlaves-1:0]ss; 


  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin

      control <= 0;
      txdata <= 0;
      divide_pre <= 1;
      ss_reg <= 1;
  	end else begin
      if (chipselect & read) begin
        case (address) 
        	`addr_rx			: readdata <= {24'b0,rxdata};
          `addr_status 	: readdata <= {16'b0,status};
          `addr_control	: readdata <= {16'b0,control};
        endcase
      end else if(chipselect & write) begin
      	case (address) 
        	`addr_tx 			: txdata <= writedata[7:0];
          `addr_control	: control <= writedata[15:0];
        	`addr_divide	: divide_pre <= writedata[7:0];
        	`addr_chipsel	:	ss_reg <= writedata[numberOfSlaves-1:0];
        endcase 	
      end
    end
  end


  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin
  		spi_woread_send <=0;
  	end else begin
      if (chipselect & write & (address == `addr_tx)) begin
          spi_woread_send <=1;
          if(count!=0) status_toe <= 1;
          else status_toe <= 0;
          if(status_rrdy==1) status_roe <= 1;
          else 	status_roe <= 0;
      end else begin
          spi_woread_send <=0;
      end
    end
  end
  

  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin
  		CPOL <= clk_pol[0];
  		CPHA <= clk_pha[0];
  	end else begin
      if (chipselect & write & (address == `addr_control)) begin
          CPOL <= control[0];	
          CPHA <= control[1];
      end
    end
  end
  

  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin
  		status_clear <=0;
  	end else begin
      if (chipselect & write & (address == `addr_status)) begin
          status_clear <=1;
      end else begin
          status_clear <=0;
      end
    end
  end
  

  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin
  		read_rx <=0;
  	end else begin
      if (chipselect & read & (address == `addr_rx)) begin
          read_rx <=1;
      end else begin
          read_rx <=0;
      end
    end
  end
  

  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin
  		slave_chipselect <= 1;
  	end else begin
      if (spi_woread_send) begin
          slave_chipselect <= 0;
      end else if ((count == 8) & ~(sclk ^ CPOL)) begin
          slave_chipselect <= 1;
      end 
    end   
  end
  

  always @ (posedge clk or negedge reset_n) begin
  	if (!reset_n) begin
  		divide_num <= 0;
  	end else begin
      divide_num <= divide_num + 8'h1; 
      if( divide_num>= divide_pre) begin
      	divide_num <= 0 ;  
      	spi_clk_gen <= ~spi_clk_gen;
      end
    end
  end


  always @ (posedge spi_clk_gen) begin
      if (~slave_chipselect) begin
          sclk <= ~sclk;
      end else if (~CPOL) begin
          sclk <= 0;
      end else begin
          sclk <= 1;
      end
  end
  

  always @ (posedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_woread_send) begin
      if (spi_woread_send) begin
          shift_register[7:0] = txdata;
      end else begin 
          shift_register = shift_register << 1;
          shift_register[0] = miso;
      end
  end
  

  always @ (negedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_woread_send) begin
      if (spi_woread_send) begin
          mosi = txdata[7];
      end else begin 
          mosi = shift_register[7];
      end
  end


  always @ (posedge slave_chipselect or negedge reset_n) begin
  	if (!reset_n) begin
  		status_tmt <= 1;
  		status_trdy <= 1;
  	end else if(slave_chipselect) begin
  		rxdata <= shift_register;
  		status_tmt <= 1;
  		status_trdy <= 1;
  	end else begin
  		status_tmt <= 0;
  		status_trdy <= 0;
  	end
  end









  

  always @ (posedge sclk or posedge slave_chipselect or posedge read_rx or negedge reset_n) begin
  	if (!reset_n) begin
  		status_rrdy <= 0;
  	end else if(slave_chipselect==1) begin
  		if(read_rx==0) status_rrdy <= 1;
  		else status_rrdy <= 0;
  	end else if (read_rx) begin
  		status_rrdy <= 0;
  	end else begin
  		status_rrdy <= status_rrdy;	
  	end
  end 
  

  always @ (posedge sclk or posedge slave_chipselect or negedge reset_n) begin
  	if (!reset_n) begin
  		count = 0;
  	end else begin
      if (slave_chipselect) begin
          count <= 0;
      end else begin   
          count <= count + 4'h1;
      end
    end
  end
  














  

  assign status_e = status_toe | status_roe;
  assign ss = ((control & 16'h400) | (~slave_chipselect)) ?  ~ss_reg : {numberOfSlaves{1'b1}}; 
  assign status = {7'h0,status_e,status_rrdy,status_trdy,status_tmt,status_toe,status_roe,3'h0}; 
  endmodule