data/full_repos/permissive/136684942/src/mytest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/136684942/src/mytest.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #10;clk = 1;reset = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136684942/src/mytest.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #10;clk = 0;reset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136684942/src/mytest.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #10;clk = 1;reset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136684942/src/mytest.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #10;clk = 0;reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136684942/src/mytest.v:67: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/136684942/src/mytest.v:43: Cannot find file containing module: \'Top\'\n Top uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/136684942/src,data/full_repos/permissive/136684942/Top\n             data/full_repos/permissive/136684942/src,data/full_repos/permissive/136684942/Top.v\n             data/full_repos/permissive/136684942/src,data/full_repos/permissive/136684942/Top.sv\n             Top\n             Top.v\n             Top.sv\n             obj_dir/Top\n             obj_dir/Top.v\n             obj_dir/Top.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mytest;


	reg clk;
	reg reset;


	wire [2:0] JumpFlag;
	wire [31:0] Instruction_id;
	wire [31:0] ALU_A;
	wire [31:0] ALU_B;
	wire [31:0] ALUResult;
	wire [31:0] PC;
	wire [31:0] MemDout_wb;
	wire Stall;
	wire [31:0] ALUResult_mem;


	Top uut (
		.clk(clk), 
		.reset(reset), 
		.JumpFlag(JumpFlag), 
		.Instruction_id(Instruction_id), 
		.ALU_A(ALU_A), 
		.ALU_B(ALU_B), 
		.ALUResult(ALUResult), 
		.PC(PC), 
		.MemDout_wb(MemDout_wb), 
		.Stall(Stall), 
		.ALUResult_mem(ALUResult_mem)
	);

	initial begin

		clk = 0;
		reset = 0;


		#10;clk = 1;reset = 1;
		#10;clk = 0;reset = 1;
		#10;clk = 1;reset = 1;
		#10;clk = 0;reset = 0;
		forever #10 clk = ~clk;
        


	end
      
endmodule
module mytest;



	reg clk;
	reg reset;


	wire [2:0] JumpFlag;
	wire [31:0] Instruction_id;
	wire [31:0] ALU_A;
	wire [31:0] ALU_B;
	wire [31:0] ALUResult;
	wire [31:0] PC;
	wire [31:0] MemDout_wb;
	wire Stall;
	wire [31:0] ALUResult_mem;


	Top uut (
		.clk(clk), 
		.reset(reset), 
		.JumpFlag(JumpFlag), 
		.Instruction_id(Instruction_id), 
		.ALU_A(ALU_A), 
		.ALU_B(ALU_B), 
		.ALUResult(ALUResult), 
		.PC(PC), 
		.MemDout_wb(MemDout_wb), 
		.Stall(Stall), 
		.ALUResult_mem(ALUResult_mem)
	);

	initial begin

		clk = 0;
		reset = 0;


		#10;clk = 1;reset = 1;
		#10;clk = 0;reset = 1;
		#10;clk = 1;reset = 1;
		#10;clk = 0;reset = 0;
		forever #10 clk = ~clk;
        


	end
      
endmodule