data/full_repos/permissive/174263347/crtv10/hdl/crt_cpu.v
 line:1 column:1: Illegal character '\x00'
1: b'%Error: data/full_repos/permissive/174263347/crtv10/hdl/crt_cpu.v:145: Cannot find file containing module: \'quad_tmr\'\n    quad_tmr qtmrA( clk, reset, onemks, a[0], b[0], qA);\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174263347/crtv10/hdl,data/full_repos/permissive/174263347/quad_tmr\n             data/full_repos/permissive/174263347/crtv10/hdl,data/full_repos/permissive/174263347/quad_tmr.v\n             data/full_repos/permissive/174263347/crtv10/hdl,data/full_repos/permissive/174263347/quad_tmr.sv\n             quad_tmr\n             quad_tmr.v\n             quad_tmr.sv\n             obj_dir/quad_tmr\n             obj_dir/quad_tmr.v\n             obj_dir/quad_tmr.sv\n%Error: data/full_repos/permissive/174263347/crtv10/hdl/crt_cpu.v:146: Cannot find file containing module: \'quad_tmr\'\n    quad_tmr qtmrB( clk, reset, onemks, a[1], b[1], qB);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/174263347/crtv10/hdl/crt_cpu.v:147: Cannot find file containing module: \'quad_tmr\'\n    quad_tmr qtmrC( clk, reset, onemks, a[2], b[2], qC);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/174263347/crtv10/hdl/crt_cpu.v:148: Cannot find file containing module: \'quad_tmr\'\n    quad_tmr qtmrD( clk, reset, onemks, a[3], b[3], qD);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/174263347/crtv10/hdl/crt_cpu.v:159: Cannot find file containing module: \'crt_cookie\'\n    crt_cookie      obj_crt_cookie(clk, reset, next_cookie, extnoice, test);\n    ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/174263347/crtv10/hdl/crt_cpu.v:172: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                             : ... In instance crt_cpu\n    4\'b10 : dboreg <=  { mem_hold, measure_mode, measure,  test, 3\'b00, test_freq[9:8]};\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/174263347/crtv10/hdl/crt_cpu.v:169: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'reg_select\' generates 2 bits.\n                                                                             : ... In instance crt_cpu\n   case (reg_select)\n   ^~~~\n%Error: data/full_repos/permissive/174263347/crtv10/hdl/crt_cpu.v:179: Cannot find file containing module: \'crt_measure\'\n    crt_measure crt_measure_obj ( clk, reset, start_measure, measure_mode, testh, testv, measure, test_freq);\n    ^~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n'
module crt_cpu (clk, reset, db, as, ds, wr, dbi, dbo, da, mem_hold, page, onemks, a, b, testh, testv, extnoice);



    input   clk, reset;              



    inout   [7:0]   db;
    input           as, ds, wr;



    output  [7:0]   dbo;
    input   [7:0]   dbi;
    output  [19:0]  da;
    output          mem_hold;
	output	[6:0]	page;
    input           onemks;
  	input	[3:0]	a, b;
    input           testh, testv;
    input           extnoice;
    


    reg     [21:0]  addr_reg;
    reg     [1:0]   reg_select;
    reg     [1:0]   ase, dse;
    wire            as_ena, ds_ena, as_enaw, as_end;
    wire            inc, addr_ena;
    reg     [6:0]   page_reg;
    wire            measure_mode;
    wire            measure;





    always @ (posedge reset or posedge clk)
        if (reset)
            begin
                ase <= 2'b00;
                dse <= 2'b00;
            end
        else 
            begin
                ase <= {ase[0], as};
                dse <= {dse[0], ds};
            end                
    
    assign  as_ena = ase[0] & ~ase[1];
    assign  as_enaw= as_ena & wr;
    assign  ds_ena = dse[0] & ~dse[1];
    assign  inc    = dse[1] & ~dse[0];
    assign  as_end = ase[1] & ~ase[0];
    assign  addr_ena = inc | as_ena;





    
    always @ (posedge reset or posedge clk)
        if (reset)
            reg_select <= 2'b00;
        else
        begin
        if (as_end)
            reg_select <= reg_select + 1;
        else if (ds_ena)
            reg_select <= 2'b00;
        end







    always @ (posedge reset or posedge clk)
        if (reset)
            addr_reg <= 22'b00_0000_0000_0000_0000_0000;
        else if (addr_ena)
            if (inc)
                addr_reg[7:0] <= addr_reg[7:0] + 1;    
            else 
            begin
                case (reg_select)
                    2'b00:  addr_reg[7:0]   <= db;
                    2'b01:  addr_reg[15:8]  <= db;
                    2'b10:  addr_reg[21:16] <= {db[7:6], db[3:0]};
                endcase
            end
    
    assign  da= addr_reg[19:0];
    assign  mem_hold     = addr_reg[21];
    assign  measure_mode = addr_reg[20];







    always @ (posedge reset or posedge clk)
        if (reset)
            page_reg <= 7'b000_0000;
        else if (addr_ena)
            case (reg_select)
                2'b11:  page_reg  <= db[6:0];
            endcase         
    
	assign page         = page_reg;



    wire    [3:0]   qA,qB,qC,qD;

    quad_tmr qtmrA( clk, reset, onemks, a[0], b[0], qA);
    quad_tmr qtmrB( clk, reset, onemks, a[1], b[1], qB);
    quad_tmr qtmrC( clk, reset, onemks, a[2], b[2], qC);
    quad_tmr qtmrD( clk, reset, onemks, a[3], b[3], qD);



    reg     [7:0]   dboreg;
    wire            db_dir_out;
    wire    [9:0]   test_freq;
    wire            test;
    wire            next_cookie;
    assign          next_cookie = ~wr & as_ena & (reg_select == 2'b10);

    crt_cookie      obj_crt_cookie(clk, reset, next_cookie, extnoice, test);

    assign  db_dir_out = (as | ds) & ~wr;
    assign  db  = db_dir_out ? dboreg : 8'bzzzz_zzzz;
    assign  dbo = db;

    always @ (ds or reg_select or qA or qB or qC or qD or dbi or test_freq or measure or mem_hold or measure_mode or test)
		if(ds)
			dboreg <= dbi;
		else 
			case (reg_select)
				4'b00 :	dboreg <=  {qB, qA};        
				4'b01 :	dboreg <=  {qD, qC};
				4'b10 :	dboreg <=  { mem_hold, measure_mode, measure,  test, 3'b00, test_freq[9:8]};
				4'b11 :	dboreg <=  test_freq[7:0];
			endcase


    wire    start_measure;
    assign start_measure = as_enaw & (reg_select == 2'b10) & db[5];
    crt_measure crt_measure_obj ( clk, reset, start_measure, measure_mode, testh, testv, measure, test_freq);

endmodule
module crt_cpu (clk, reset, db, as, ds, wr, dbi, dbo, da, mem_hold, page, onemks, a, b, testh, testv, extnoice);




    input   clk, reset;              



    inout   [7:0]   db;
    input           as, ds, wr;



    output  [7:0]   dbo;
    input   [7:0]   dbi;
    output  [19:0]  da;
    output          mem_hold;
	output	[6:0]	page;
    input           onemks;
  	input	[3:0]	a, b;
    input           testh, testv;
    input           extnoice;
    


    reg     [21:0]  addr_reg;
    reg     [1:0]   reg_select;
    reg     [1:0]   ase, dse;
    wire            as_ena, ds_ena, as_enaw, as_end;
    wire            inc, addr_ena;
    reg     [6:0]   page_reg;
    wire            measure_mode;
    wire            measure;





    always @ (posedge reset or posedge clk)
        if (reset)
            begin
                ase <= 2'b00;
                dse <= 2'b00;
            end
        else 
            begin
                ase <= {ase[0], as};
                dse <= {dse[0], ds};
            end                
    
    assign  as_ena = ase[0] & ~ase[1];
    assign  as_enaw= as_ena & wr;
    assign  ds_ena = dse[0] & ~dse[1];
    assign  inc    = dse[1] & ~dse[0];
    assign  as_end = ase[1] & ~ase[0];
    assign  addr_ena = inc | as_ena;





    
    always @ (posedge reset or posedge clk)
        if (reset)
            reg_select <= 2'b00;
        else
        begin
        if (as_end)
            reg_select <= reg_select + 1;
        else if (ds_ena)
            reg_select <= 2'b00;
        end







    always @ (posedge reset or posedge clk)
        if (reset)
            addr_reg <= 22'b00_0000_0000_0000_0000_0000;
        else if (addr_ena)
            if (inc)
                addr_reg[7:0] <= addr_reg[7:0] + 1;    
            else 
            begin
                case (reg_select)
                    2'b00:  addr_reg[7:0]   <= db;
                    2'b01:  addr_reg[15:8]  <= db;
                    2'b10:  addr_reg[21:16] <= {db[7:6], db[3:0]};
                endcase
            end
    
    assign  da= addr_reg[19:0];
    assign  mem_hold     = addr_reg[21];
    assign  measure_mode = addr_reg[20];







    always @ (posedge reset or posedge clk)
        if (reset)
            page_reg <= 7'b000_0000;
        else if (addr_ena)
            case (reg_select)
                2'b11:  page_reg  <= db[6:0];
            endcase         
    
	assign page         = page_reg;



    wire    [3:0]   qA,qB,qC,qD;

    quad_tmr qtmrA( clk, reset, onemks, a[0], b[0], qA);
    quad_tmr qtmrB( clk, reset, onemks, a[1], b[1], qB);
    quad_tmr qtmrC( clk, reset, onemks, a[2], b[2], qC);
    quad_tmr qtmrD( clk, reset, onemks, a[3], b[3], qD);



    reg     [7:0]   dboreg;
    wire            db_dir_out;
    wire    [9:0]   test_freq;
    wire            test;
    wire            next_cookie;
    assign          next_cookie = ~wr & as_ena & (reg_select == 2'b10);

    crt_cookie      obj_crt_cookie(clk, reset, next_cookie, extnoice, test);

    assign  db_dir_out = (as | ds) & ~wr;
    assign  db  = db_dir_out ? dboreg : 8'bzzzz_zzzz;
    assign  dbo = db;

    always @ (ds or reg_select or qA or qB or qC or qD or dbi or test_freq or measure or mem_hold or measure_mode or test)
		if(ds)
			dboreg <= dbi;
		else 
			case (reg_select)
				4'b00 :	dboreg <=  {qB, qA};        
				4'b01 :	dboreg <=  {qD, qC};
				4'b10 :	dboreg <=  { mem_hold, measure_mode, measure,  test, 3'b00, test_freq[9:8]};
				4'b11 :	dboreg <=  test_freq[7:0];
			endcase


    wire    start_measure;
    assign start_measure = as_enaw & (reg_select == 2'b10) & db[5];
    crt_measure crt_measure_obj ( clk, reset, start_measure, measure_mode, testh, testv, measure, test_freq);

endmodule