data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:1: Cannot find include file: Util/Math.v\n`include "Util/Math.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Util/Math.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Util/Math.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Util/Math.v.sv\n             Util/Math.v\n             Util/Math.v.v\n             Util/Math.v.sv\n             obj_dir/Util/Math.v\n             obj_dir/Util/Math.v.v\n             obj_dir/Util/Math.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:2: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:3: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:4: Cannot find include file: Mips/Type/RegAddr.v\n`include "Mips/Type/RegAddr.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:7: Define or directive not defined: \'`Mips_Type_Word_W\'\n ( parameter RESET = `Mips_Type_Word_W\'(0)\n                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:7: syntax error, unexpected "\'", expecting TYPE-IDENTIFIER\n ( parameter RESET = `Mips_Type_Word_W\'(0)\n                                      ^\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:9: syntax error, unexpected \')\', expecting \';\'\n )\n ^\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:10: Define or directive not defined: \'`Data_Control_Control_T\'\n ( `Data_Control_Control_T (input ) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:11: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n , `Mips_Type_RegAddr_T    (input ) rd1Addr\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:12: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T       (output) rd1Data\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:13: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n , `Mips_Type_RegAddr_T    (input ) rd2Addr\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:14: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T       (output) rd2Data\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:15: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n , `Mips_Type_RegAddr_T    (input ) wrAddr\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:16: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T       (input ) wrData\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:20: Define or directive not defined: \'`Util_Math_log2_expr\'\n`Util_Math_log2_expr\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:22: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T(reg) regs [0:31];\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:52: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways @(posedge `Data_Control_Control_Clock(ctrl))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:53: Define or directive not defined: \'`Data_Control_Control_Reset\'\n if(`Data_Control_Control_Reset(ctrl)) begin : wtf\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/register.v:55: syntax error, unexpected for\n  for(i = 0; i < 32; i = i + 1)\n  ^~~\n%Error: Exiting due to 19 error(s)\n'
module Mips_Datapath_Register_register #
	( parameter RESET = `Mips_Type_Word_W'(0)
	, parameter PASSTHROUGH = 0
	)
	( `Data_Control_Control_T (input ) ctrl
	, `Mips_Type_RegAddr_T    (input ) rd1Addr
	, `Mips_Type_Word_T       (output) rd1Data
	, `Mips_Type_RegAddr_T    (input ) rd2Addr
	, `Mips_Type_Word_T       (output) rd2Data
	, `Mips_Type_RegAddr_T    (input ) wrAddr
	, `Mips_Type_Word_T       (input ) wrData
	, input                            wrEnable
	);

`Util_Math_log2_expr

`Mips_Type_Word_T(reg) regs [0:31];

generate
	if(PASSTHROUGH)
		assign rd1Data
			= (
				(|wrAddr) &&
				wrEnable &&
				rd1Addr == wrAddr
			)? wrData
			: regs[rd1Addr]
			;
	else
		assign rd1Data = regs[rd1Addr];
endgenerate

generate
	if(PASSTHROUGH)
		assign rd2Data
			= (
				(|wrAddr) &&
				wrEnable &&
				rd2Addr == wrAddr
			)? wrData
			: regs[rd2Addr]
			;
	else
		assign rd1Data = regs[rd1Addr];
endgenerate

always @(posedge `Data_Control_Control_Clock(ctrl))
	if(`Data_Control_Control_Reset(ctrl)) begin : wtf
		integer i;
		for(i = 0; i < 32; i = i + 1)
			begin regs[i] <= RESET; end
	end else if((|wrAddr) && wrEnable)
		regs[wrAddr] <= wrData;

endmodule
module Mips_Datapath_Register_register #
	( parameter RESET = `Mips_Type_Word_W'(0)
	, parameter PASSTHROUGH = 0
	)
	( `Data_Control_Control_T (input ) ctrl
	, `Mips_Type_RegAddr_T    (input ) rd1Addr
	, `Mips_Type_Word_T       (output) rd1Data
	, `Mips_Type_RegAddr_T    (input ) rd2Addr
	, `Mips_Type_Word_T       (output) rd2Data
	, `Mips_Type_RegAddr_T    (input ) wrAddr
	, `Mips_Type_Word_T       (input ) wrData
	, input                            wrEnable
	);


`Util_Math_log2_expr

`Mips_Type_Word_T(reg) regs [0:31];

generate
	if(PASSTHROUGH)
		assign rd1Data
			= (
				(|wrAddr) &&
				wrEnable &&
				rd1Addr == wrAddr
			)? wrData
			: regs[rd1Addr]
			;
	else
		assign rd1Data = regs[rd1Addr];
endgenerate

generate
	if(PASSTHROUGH)
		assign rd2Data
			= (
				(|wrAddr) &&
				wrEnable &&
				rd2Addr == wrAddr
			)? wrData
			: regs[rd2Addr]
			;
	else
		assign rd1Data = regs[rd1Addr];
endgenerate

always @(posedge `Data_Control_Control_Clock(ctrl))
	if(`Data_Control_Control_Reset(ctrl)) begin : wtf
		integer i;
		for(i = 0; i < 32; i = i + 1)
			begin regs[i] <= RESET; end
	end else if((|wrAddr) && wrEnable)
		regs[wrAddr] <= wrData;

endmodule