data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v
1: b"%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v:105: Cannot find file containing module: 'alt_pll_ip_core'\n alt_pll_ip_core  alt_pll_ip_core_inst(\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic,data/full_repos/permissive/143584361/alt_pll_ip_core\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic,data/full_repos/permissive/143584361/alt_pll_ip_core.v\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic,data/full_repos/permissive/143584361/alt_pll_ip_core.sv\n             alt_pll_ip_core\n             alt_pll_ip_core.v\n             alt_pll_ip_core.sv\n             obj_dir/alt_pll_ip_core\n             obj_dir/alt_pll_ip_core.v\n             obj_dir/alt_pll_ip_core.sv\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v:145: Cannot find file containing module: 'cmd_parser'\n cmd_parser   cmd_parser_inst(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v:179: Cannot find file containing module: 'uart_wr'\n uart_wr    uart_wr_inst(\n ^~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v:223: Cannot find file containing module: 'npu_inst_fsm'\n npu_inst_fsm    npu_inst_fsm_inst(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v:258: Cannot find file containing module: 'npu_inst_ram'\n    npu_inst_ram            npu_inst_ram_inst(\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v:268: Cannot find file containing module: 'npu_inst_ram_bak'\n    npu_inst_ram_bak        npu_inst_ram_bak_inst(\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v:277: Cannot find file containing module: 'npu_inst_join'\n npu_inst_join   npu_inst_join_inst(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v:299: Cannot find file containing module: 'npu_paras_rom'\n npu_paras_rom   npu_paras_rom_inst(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v:305: Cannot find file containing module: 'npu_paras_config'\n npu_paras_config  npu_paras_config_inst(\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v:357: Cannot find file containing module: 'sram_controller'\n sram_controller  sram_controller_inst(\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v:379: Cannot find file containing module: 'mux_ddr_access'\n mux_ddr_access  mux_ddr_access_local_inst(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/top.v:442: Cannot find file containing module: 'mux_ddr_access'\n mux_ddr_access  mux_ddr_access_attach_inst(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n"
module top(

	CLOCK_50,
	CLOCK2_50,
	CLOCK3_50,
	ENETCLK_25,


	LEDG,
	LEDR,


	KEY,


	SW,


	UART_RXD,
	UART_TXD,

	

	SRAM_ADDR,
	SRAM_CE_N,
	SRAM_DQ,
	SRAM_LB_N,
	SRAM_OE_N,
	SRAM_UB_N,
	SRAM_WE_N
);








	input		          		CLOCK_50;
	input		          		CLOCK2_50;
	input		          		CLOCK3_50;
	input		          		ENETCLK_25;


	output		     [8:0]		LEDG;
	output		    [17:0]		LEDR;


	input		     [3:0]		KEY;


	input		    [17:0]		SW;


	input		          		UART_RXD;
	output		          		UART_TXD;


	output		    [19:0]		SRAM_ADDR;
	output		          		SRAM_CE_N;
	inout		    [15:0]		SRAM_DQ;
	output		          		SRAM_LB_N;
	output		          		SRAM_OE_N;
	output		          		SRAM_UB_N;
	output		          		SRAM_WE_N;









	wire 		TEST_MODE = (SW[5:1]==5'B10100);
	wire		SAMP_MODE = (SW[5:1]==5'B00011);
	wire		RUN_MODE = (SW[5:1]==5'B01001);
	wire		SIMU_MODE = (SW[5:1]==5'B01000);


	wire		RESET_N = KEY[0];

	wire		CLOCK50, CLOCK60, CLOCK40, CLOCK10, CLOCK12p28;

	alt_pll_ip_core		alt_pll_ip_core_inst(
							.inclk0(CLOCK_50),
							.c0(CLOCK50),
							.c1(CLOCK60),
							.c2(CLOCK40),
							.c3(CLOCK10),
							.c4(CLOCK12p28)
						);


	wire		sys_clk = CLOCK60;
	wire		sys_rst_n = RESET_N;



	wire		[31:0]					sys_uart_write_data;
	wire								sys_uart_write_data_valid;
	wire								sys_uart_write_data_permitted;
	wire		[15:0]					sys_uart_read_data;
	wire								sys_uart_read_data_req;
	wire								sys_uart_read_data_permitted;

	wire		[31:0]					sys_ddr_write_addr;
	wire		[31:0]					sys_ddr_write_data;
	wire								sys_ddr_write_data_valid;
	wire								sys_ddr_write_burst_begin;
	wire								sys_ddr_write_data_permitted;
	wire		[31:0]					sys_ddr_read_addr;
	wire		[31:0]					sys_ddr_read_data;
	wire								sys_ddr_read_data_valid;
	wire								sys_ddr_read_burst_begin;
	wire								sys_ddr_read_data_req;
	wire								sys_ddr_read_data_permitted;
	wire								logic_receive_valid_cmd;


	wire		[31:0]					npu_inst_part;
	wire								npu_inst_part_en;

	cmd_parser			cmd_parser_inst(
							.sys_clk(sys_clk),
							.sys_rst_n(sys_rst_n),
							.sys_uart_write_data(sys_uart_write_data),
							.sys_uart_write_data_valid(sys_uart_write_data_valid),
							.sys_uart_write_data_permitted(sys_uart_write_data_permitted),
							.sys_uart_read_data(sys_uart_read_data),
							.sys_uart_read_data_req(sys_uart_read_data_req),
							.sys_uart_read_data_permitted(sys_uart_read_data_permitted),
							.sys_ddr_write_addr(sys_ddr_write_addr),
							.sys_ddr_write_data(sys_ddr_write_data),
							.sys_ddr_write_data_valid(sys_ddr_write_data_valid),
							.sys_ddr_write_burst_begin(sys_ddr_write_burst_begin),
							.sys_ddr_write_data_permitted(sys_ddr_write_data_permitted),
							.sys_ddr_read_addr(sys_ddr_read_addr),
							.sys_ddr_read_data(sys_ddr_read_data),
							.sys_ddr_read_data_valid(sys_ddr_read_data_valid),
							.sys_ddr_read_data_req(sys_ddr_read_data_req),
							.sys_ddr_read_burst_begin(sys_ddr_read_burst_begin),
							.sys_ddr_read_data_permitted(sys_ddr_read_data_permitted),
							.receive_valid_cmd(logic_receive_valid_cmd),
							.sys_key_fn(8'HFF),

							.adc_ddr_write_addr(),
							.adc_ddr_write_addr_mask(),

							.audio_sample_en(audio_sample_en),

							.npu_inst_part(npu_inst_part),
							.npu_inst_part_en(npu_inst_part_en)
						);



	uart_wr				uart_wr_inst(
							.sys_clk(sys_clk),
							.sys_rst_n(sys_rst_n),
							.uart_rxd(UART_RXD),
							.uart_txd(UART_TXD),
							.uart_sys_clk(CLOCK50),
							.uart_sys_rst_n(RESET_N),
							.sys_write_data(sys_uart_write_data),
							.sys_write_data_valid(sys_uart_write_data_valid),
							.sys_write_data_permitted(sys_uart_write_data_permitted),
							.sys_read_data(sys_uart_read_data),
							.sys_read_data_req(sys_uart_read_data_req),
							.sys_read_data_permitted(sys_uart_read_data_permitted)
						);	




	wire	[127:0]				npu_inst;
	wire						npu_inst_en;
	wire						npu_inst_ready;

	wire	[31:0]				npu_inst_time;
	wire						NPU_DDR_WRITE_CLK;
	wire	[31:0]				NPU_DDR_WRITE_ADDR;
	wire	[31:0]				NPU_DDR_WRITE_DATA;
	wire						NPU_DDR_WRITE_REQ;
	wire						NPU_DDR_WRITE_READY;
	wire						NPU_DDR_READ_CLK;
	wire	[31:0]				NPU_DDR_READ_ADDR;
	wire						NPU_DDR_READ_REQ;
	wire						NPU_DDR_READ_READY;
	wire	[31:0]				NPU_DDR_READ_DATA;
	wire						NPU_DDR_READ_DATA_VALID;
	wire						npu_inst_clk = CLOCK60;
	wire						npu_inst_rst_n = RESET_N;
    wire    [31:0]              npu_inst_addr;
    wire    [127:0]             npu_inst_q;
	wire						npu_inst_start_vad;


	wire						KEY3_DOWN;
    wire                        npu_inst_start = TEST_MODE? ((npu_inst_en && npu_inst==128'D2)|KEY3_DOWN) : (RUN_MODE||SIMU_MODE)? npu_inst_start_vad : 0;	
	npu_inst_fsm				npu_inst_fsm_inst(
									.clk(npu_inst_clk),
									.rst_n(npu_inst_rst_n),
									.npu_inst_addr(npu_inst_addr),
									.npu_inst_q(npu_inst_q),
									.npu_inst_start(npu_inst_start),
									.npu_inst_ready(npu_inst_ready),
									.npu_inst_time(npu_inst_time),

									.DDR_WRITE_CLK(NPU_DDR_WRITE_CLK),
									.DDR_WRITE_ADDR(NPU_DDR_WRITE_ADDR),
									.DDR_WRITE_DATA(NPU_DDR_WRITE_DATA),
									.DDR_WRITE_REQ(NPU_DDR_WRITE_REQ),
									.DDR_WRITE_READY(NPU_DDR_WRITE_READY),
									.DDR_READ_CLK(NPU_DDR_READ_CLK),
									.DDR_READ_ADDR(NPU_DDR_READ_ADDR),
									.DDR_READ_REQ(NPU_DDR_READ_REQ),
									.DDR_READ_READY(NPU_DDR_READ_READY),
									.DDR_READ_DATA(NPU_DDR_READ_DATA),
									.DDR_READ_DATA_VALID(NPU_DDR_READ_DATA_VALID)
								);

	reg		[1:0]				KEY3;
	always @(posedge npu_inst_clk)
		KEY3 <= {KEY3[0], KEY[3]};
	assign						KEY3_DOWN = (KEY3==2'B10);
                                

    reg     [31:0]      npu_inst_wraddr;
    always @(posedge npu_inst_clk)
        if(npu_inst_en && npu_inst==128'D1)
            npu_inst_wraddr <= 0;
        else if(npu_inst_en && npu_inst!=128'D1 && npu_inst!=128'D2)
            npu_inst_wraddr <= npu_inst_wraddr  +1;

    npu_inst_ram            npu_inst_ram_inst(
                                .data(npu_inst),
                                .wren(npu_inst_en && npu_inst!=128'D1 && npu_inst!=128'D2),
                                .wraddress(npu_inst_wraddr),
                                .wrclock(npu_inst_clk),
                                .rdclock(npu_inst_clk),
                                .rdaddress(npu_inst_addr),
                                .q(npu_inst_q)
                            );   

    npu_inst_ram_bak        npu_inst_ram_bak_inst(
                                .data(npu_inst),
                                .wren(npu_inst_en && npu_inst!=128'D1 && npu_inst!=128'D2),
                                .address(npu_inst_wraddr),
                                .clock(npu_inst_clk)
                            );   
							


	npu_inst_join			npu_inst_join_inst(
								.npu_inst_clk(npu_inst_clk),
								.npu_inst_rst_n(npu_inst_rst_n),
								.npu_inst_part(npu_inst_part),
								.npu_inst_part_en(npu_inst_part_en),
								.npu_inst(npu_inst),
								.npu_inst_en(npu_inst_en)
							);



	wire					cnn_paras_ready;
	wire					cnn_paras_en = !KEY[2];
	wire	[31:0]			cnn_paras_q;
	wire	[31:0]			cnn_paras_addr;

	wire					CNN_DDR_WRITE_CLK;
	wire	[31:0]			CNN_DDR_WRITE_ADDR;
	wire	[31:0]			CNN_DDR_WRITE_DATA;
	wire					CNN_DDR_WRITE_REQ;
	wire					CNN_DDR_WRITE_READY;

	npu_paras_rom			npu_paras_rom_inst(
								.clock(CLOCK60),
								.address(cnn_paras_addr),
								.q(cnn_paras_q)
							);
	
	npu_paras_config		npu_paras_config_inst(
								.clk(CLOCK60),
								.rst_n(RESET_N),
								.npu_paras_ready(cnn_paras_ready),
								.npu_paras_en(cnn_paras_en),
								.npu_paras_addr(cnn_paras_addr),
								.npu_paras_q(cnn_paras_q),

								.DDR_WRITE_CLK(CNN_DDR_WRITE_CLK),
								.DDR_WRITE_ADDR(CNN_DDR_WRITE_ADDR),
								.DDR_WRITE_DATA(CNN_DDR_WRITE_DATA),
								.DDR_WRITE_REQ(CNN_DDR_WRITE_REQ),
								.DDR_WRITE_READY(CNN_DDR_WRITE_READY)
							);




	wire		afi_phy_clk;
	wire		afi_phy_rst_n;



	wire        local_ready;
	wire        local_burstbegin;
	wire [31:0] local_addr;
	wire        local_rdata_valid;
	wire [31:0] local_rdata;
	wire [31:0] local_wdata;
	wire [3:0]  local_be;
	wire        local_read_req;
	wire        local_write_req;
	wire [2:0]  local_size;
	wire		local_waitrequest;

	wire        attach_ready;
	wire        attach_burstbegin;
	wire [31:0] attach_addr;
	wire        attach_rdata_valid;
	wire [31:0] attach_rdata;
	wire [31:0] attach_wdata;
	wire [3:0]  attach_be;
	wire        attach_read_req;
	wire        attach_write_req;
	wire [2:0]  attach_size;
	wire		attach_ready_w, attach_ready_r;
	assign		attach_ready = 	attach_write_req? attach_ready_w : 
								attach_read_req? attach_ready_r : 
								attach_ready_w && attach_ready_r;



	sram_controller		sram_controller_inst(
							.CLOCK(CLOCK40),
							.RESET_N(RESET_N),
							.sram_avalon_clock(afi_phy_clk),
							.sram_avalon_reset_n(afi_phy_rst_n),
							.sram_avalon_address(local_addr),
							.sram_avalon_writedata(local_wdata),
							.sram_avalon_write_n(!local_write_req),
							.sram_avalon_read_n(!local_read_req),
							.sram_avalon_readdata(local_rdata),
							.sram_avalon_readdatavalid(local_rdata_valid),
							.sram_avalon_waitrequest(local_waitrequest),

							.sram_pins_addr(SRAM_ADDR),
							.sram_pins_dq(SRAM_DQ),
							.sram_pins_ce_n(SRAM_CE_N),
							.sram_pins_oe_n(SRAM_OE_N),
							.sram_pins_we_n(SRAM_WE_N),
							.sram_pins_lb_n(SRAM_LB_N),
							.sram_pins_ub_n(SRAM_UB_N)
						);

	mux_ddr_access		mux_ddr_access_local_inst(
							.afi_phy_clk(afi_phy_clk),
							.afi_phy_rst_n(afi_phy_rst_n),

							.local_address(local_addr),
							.local_write_req(local_write_req),
							.local_read_req(local_read_req),
							.local_burstbegin(local_burstbegin),
							.local_wdata(local_wdata),
							.local_be(local_be),
							.local_size(local_size),
							.local_ready(!local_waitrequest),
							.local_rdata(local_rdata),
							.local_rdata_valid(local_rdata_valid),

							.local_init_done(RESET_N),


							.wport_clock_6(afi_phy_clk),
							.wport_addr_6(attach_addr),
							.wport_data_6(attach_wdata),
							.wport_req_6(attach_write_req),
							.wport_ready_6(attach_ready_w),
							.rport_clock_7(afi_phy_clk),
							.rport_addr_7(attach_addr),
							.rport_data_7(attach_rdata),
							.rport_data_valid_7(attach_rdata_valid),
							.rport_req_7(attach_read_req),
							.rport_ready_7(attach_ready_r),

							.wport_clock_4(),
							.wport_addr_4(),
							.wport_data_4(),
							.wport_req_4(),
							.wport_ready_4(),

							.rport_clock_3(),
							.rport_addr_3(),
							.rport_data_3(),
							.rport_data_valid_3(),
							.rport_req_3(),
							.rport_ready_3(),

							.wport_clock_2(CNN_DDR_WRITE_CLK),
							.wport_addr_2(CNN_DDR_WRITE_ADDR),
							.wport_data_2(CNN_DDR_WRITE_DATA),
							.wport_req_2(CNN_DDR_WRITE_REQ && (RUN_MODE||TEST_MODE||SIMU_MODE)),
							.wport_ready_2(CNN_DDR_WRITE_READY),

							.wport_clock_0(NPU_DDR_WRITE_CLK),
							.wport_addr_0(NPU_DDR_WRITE_ADDR),
							.wport_data_0(NPU_DDR_WRITE_DATA),
							.wport_req_0(NPU_DDR_WRITE_REQ && (RUN_MODE||TEST_MODE||SIMU_MODE)),
							.wport_ready_0(NPU_DDR_WRITE_READY),

							.rport_clock_1(NPU_DDR_READ_CLK),
							.rport_addr_1(NPU_DDR_READ_ADDR),
							.rport_data_1(NPU_DDR_READ_DATA),
							.rport_data_valid_1(NPU_DDR_READ_DATA_VALID),
							.rport_req_1(NPU_DDR_READ_REQ && (RUN_MODE||TEST_MODE||SIMU_MODE)),
							.rport_ready_1(NPU_DDR_READ_READY)
						);

	mux_ddr_access		mux_ddr_access_attach_inst(
							.afi_phy_clk(afi_phy_clk),
							.afi_phy_rst_n(afi_phy_rst_n),

							.local_address(attach_addr),
							.local_write_req(attach_write_req),
							.local_read_req(attach_read_req),
							.local_burstbegin(attach_burstbegin),
							.local_wdata(attach_wdata),
							.local_be(attach_be),
							.local_size(attach_size),
							.local_ready(attach_ready),
							.local_rdata(attach_rdata),
							.local_rdata_valid(attach_rdata_valid),

							.local_init_done(RESET_N),


							.wport_clock_4(sys_clk),
							.wport_addr_4(sys_ddr_write_addr),
							.wport_data_4(sys_ddr_write_data),
							.wport_req_4(sys_ddr_write_data_valid),
							.wport_ready_4(sys_ddr_write_data_permitted),

							.rport_clock_5(sys_clk),
							.rport_addr_5(sys_ddr_read_addr),
							.rport_data_5(sys_ddr_read_data),
							.rport_data_valid_5(sys_ddr_read_data_valid),
							.rport_req_5(sys_ddr_read_data_req),
							.rport_ready_5(sys_ddr_read_data_permitted),

							.wport_clock_0(),
							.wport_addr_0(),
							.wport_data_0(),
							.wport_req_0(),
							.wport_ready_0(),

							.wport_clock_2(),
							.wport_addr_2(),
							.wport_data_2(),
							.wport_req_2(),
							.wport_ready_2()
							
						);
	


endmodule
module top(

	CLOCK_50,
	CLOCK2_50,
	CLOCK3_50,
	ENETCLK_25,


	LEDG,
	LEDR,


	KEY,


	SW,


	UART_RXD,
	UART_TXD,

	

	SRAM_ADDR,
	SRAM_CE_N,
	SRAM_DQ,
	SRAM_LB_N,
	SRAM_OE_N,
	SRAM_UB_N,
	SRAM_WE_N
);









	input		          		CLOCK_50;
	input		          		CLOCK2_50;
	input		          		CLOCK3_50;
	input		          		ENETCLK_25;


	output		     [8:0]		LEDG;
	output		    [17:0]		LEDR;


	input		     [3:0]		KEY;


	input		    [17:0]		SW;


	input		          		UART_RXD;
	output		          		UART_TXD;


	output		    [19:0]		SRAM_ADDR;
	output		          		SRAM_CE_N;
	inout		    [15:0]		SRAM_DQ;
	output		          		SRAM_LB_N;
	output		          		SRAM_OE_N;
	output		          		SRAM_UB_N;
	output		          		SRAM_WE_N;









	wire 		TEST_MODE = (SW[5:1]==5'B10100);
	wire		SAMP_MODE = (SW[5:1]==5'B00011);
	wire		RUN_MODE = (SW[5:1]==5'B01001);
	wire		SIMU_MODE = (SW[5:1]==5'B01000);


	wire		RESET_N = KEY[0];

	wire		CLOCK50, CLOCK60, CLOCK40, CLOCK10, CLOCK12p28;

	alt_pll_ip_core		alt_pll_ip_core_inst(
							.inclk0(CLOCK_50),
							.c0(CLOCK50),
							.c1(CLOCK60),
							.c2(CLOCK40),
							.c3(CLOCK10),
							.c4(CLOCK12p28)
						);


	wire		sys_clk = CLOCK60;
	wire		sys_rst_n = RESET_N;



	wire		[31:0]					sys_uart_write_data;
	wire								sys_uart_write_data_valid;
	wire								sys_uart_write_data_permitted;
	wire		[15:0]					sys_uart_read_data;
	wire								sys_uart_read_data_req;
	wire								sys_uart_read_data_permitted;

	wire		[31:0]					sys_ddr_write_addr;
	wire		[31:0]					sys_ddr_write_data;
	wire								sys_ddr_write_data_valid;
	wire								sys_ddr_write_burst_begin;
	wire								sys_ddr_write_data_permitted;
	wire		[31:0]					sys_ddr_read_addr;
	wire		[31:0]					sys_ddr_read_data;
	wire								sys_ddr_read_data_valid;
	wire								sys_ddr_read_burst_begin;
	wire								sys_ddr_read_data_req;
	wire								sys_ddr_read_data_permitted;
	wire								logic_receive_valid_cmd;


	wire		[31:0]					npu_inst_part;
	wire								npu_inst_part_en;

	cmd_parser			cmd_parser_inst(
							.sys_clk(sys_clk),
							.sys_rst_n(sys_rst_n),
							.sys_uart_write_data(sys_uart_write_data),
							.sys_uart_write_data_valid(sys_uart_write_data_valid),
							.sys_uart_write_data_permitted(sys_uart_write_data_permitted),
							.sys_uart_read_data(sys_uart_read_data),
							.sys_uart_read_data_req(sys_uart_read_data_req),
							.sys_uart_read_data_permitted(sys_uart_read_data_permitted),
							.sys_ddr_write_addr(sys_ddr_write_addr),
							.sys_ddr_write_data(sys_ddr_write_data),
							.sys_ddr_write_data_valid(sys_ddr_write_data_valid),
							.sys_ddr_write_burst_begin(sys_ddr_write_burst_begin),
							.sys_ddr_write_data_permitted(sys_ddr_write_data_permitted),
							.sys_ddr_read_addr(sys_ddr_read_addr),
							.sys_ddr_read_data(sys_ddr_read_data),
							.sys_ddr_read_data_valid(sys_ddr_read_data_valid),
							.sys_ddr_read_data_req(sys_ddr_read_data_req),
							.sys_ddr_read_burst_begin(sys_ddr_read_burst_begin),
							.sys_ddr_read_data_permitted(sys_ddr_read_data_permitted),
							.receive_valid_cmd(logic_receive_valid_cmd),
							.sys_key_fn(8'HFF),

							.adc_ddr_write_addr(),
							.adc_ddr_write_addr_mask(),

							.audio_sample_en(audio_sample_en),

							.npu_inst_part(npu_inst_part),
							.npu_inst_part_en(npu_inst_part_en)
						);



	uart_wr				uart_wr_inst(
							.sys_clk(sys_clk),
							.sys_rst_n(sys_rst_n),
							.uart_rxd(UART_RXD),
							.uart_txd(UART_TXD),
							.uart_sys_clk(CLOCK50),
							.uart_sys_rst_n(RESET_N),
							.sys_write_data(sys_uart_write_data),
							.sys_write_data_valid(sys_uart_write_data_valid),
							.sys_write_data_permitted(sys_uart_write_data_permitted),
							.sys_read_data(sys_uart_read_data),
							.sys_read_data_req(sys_uart_read_data_req),
							.sys_read_data_permitted(sys_uart_read_data_permitted)
						);	




	wire	[127:0]				npu_inst;
	wire						npu_inst_en;
	wire						npu_inst_ready;

	wire	[31:0]				npu_inst_time;
	wire						NPU_DDR_WRITE_CLK;
	wire	[31:0]				NPU_DDR_WRITE_ADDR;
	wire	[31:0]				NPU_DDR_WRITE_DATA;
	wire						NPU_DDR_WRITE_REQ;
	wire						NPU_DDR_WRITE_READY;
	wire						NPU_DDR_READ_CLK;
	wire	[31:0]				NPU_DDR_READ_ADDR;
	wire						NPU_DDR_READ_REQ;
	wire						NPU_DDR_READ_READY;
	wire	[31:0]				NPU_DDR_READ_DATA;
	wire						NPU_DDR_READ_DATA_VALID;
	wire						npu_inst_clk = CLOCK60;
	wire						npu_inst_rst_n = RESET_N;
    wire    [31:0]              npu_inst_addr;
    wire    [127:0]             npu_inst_q;
	wire						npu_inst_start_vad;


	wire						KEY3_DOWN;
    wire                        npu_inst_start = TEST_MODE? ((npu_inst_en && npu_inst==128'D2)|KEY3_DOWN) : (RUN_MODE||SIMU_MODE)? npu_inst_start_vad : 0;	
	npu_inst_fsm				npu_inst_fsm_inst(
									.clk(npu_inst_clk),
									.rst_n(npu_inst_rst_n),
									.npu_inst_addr(npu_inst_addr),
									.npu_inst_q(npu_inst_q),
									.npu_inst_start(npu_inst_start),
									.npu_inst_ready(npu_inst_ready),
									.npu_inst_time(npu_inst_time),

									.DDR_WRITE_CLK(NPU_DDR_WRITE_CLK),
									.DDR_WRITE_ADDR(NPU_DDR_WRITE_ADDR),
									.DDR_WRITE_DATA(NPU_DDR_WRITE_DATA),
									.DDR_WRITE_REQ(NPU_DDR_WRITE_REQ),
									.DDR_WRITE_READY(NPU_DDR_WRITE_READY),
									.DDR_READ_CLK(NPU_DDR_READ_CLK),
									.DDR_READ_ADDR(NPU_DDR_READ_ADDR),
									.DDR_READ_REQ(NPU_DDR_READ_REQ),
									.DDR_READ_READY(NPU_DDR_READ_READY),
									.DDR_READ_DATA(NPU_DDR_READ_DATA),
									.DDR_READ_DATA_VALID(NPU_DDR_READ_DATA_VALID)
								);

	reg		[1:0]				KEY3;
	always @(posedge npu_inst_clk)
		KEY3 <= {KEY3[0], KEY[3]};
	assign						KEY3_DOWN = (KEY3==2'B10);
                                

    reg     [31:0]      npu_inst_wraddr;
    always @(posedge npu_inst_clk)
        if(npu_inst_en && npu_inst==128'D1)
            npu_inst_wraddr <= 0;
        else if(npu_inst_en && npu_inst!=128'D1 && npu_inst!=128'D2)
            npu_inst_wraddr <= npu_inst_wraddr  +1;

    npu_inst_ram            npu_inst_ram_inst(
                                .data(npu_inst),
                                .wren(npu_inst_en && npu_inst!=128'D1 && npu_inst!=128'D2),
                                .wraddress(npu_inst_wraddr),
                                .wrclock(npu_inst_clk),
                                .rdclock(npu_inst_clk),
                                .rdaddress(npu_inst_addr),
                                .q(npu_inst_q)
                            );   

    npu_inst_ram_bak        npu_inst_ram_bak_inst(
                                .data(npu_inst),
                                .wren(npu_inst_en && npu_inst!=128'D1 && npu_inst!=128'D2),
                                .address(npu_inst_wraddr),
                                .clock(npu_inst_clk)
                            );   
							


	npu_inst_join			npu_inst_join_inst(
								.npu_inst_clk(npu_inst_clk),
								.npu_inst_rst_n(npu_inst_rst_n),
								.npu_inst_part(npu_inst_part),
								.npu_inst_part_en(npu_inst_part_en),
								.npu_inst(npu_inst),
								.npu_inst_en(npu_inst_en)
							);



	wire					cnn_paras_ready;
	wire					cnn_paras_en = !KEY[2];
	wire	[31:0]			cnn_paras_q;
	wire	[31:0]			cnn_paras_addr;

	wire					CNN_DDR_WRITE_CLK;
	wire	[31:0]			CNN_DDR_WRITE_ADDR;
	wire	[31:0]			CNN_DDR_WRITE_DATA;
	wire					CNN_DDR_WRITE_REQ;
	wire					CNN_DDR_WRITE_READY;

	npu_paras_rom			npu_paras_rom_inst(
								.clock(CLOCK60),
								.address(cnn_paras_addr),
								.q(cnn_paras_q)
							);
	
	npu_paras_config		npu_paras_config_inst(
								.clk(CLOCK60),
								.rst_n(RESET_N),
								.npu_paras_ready(cnn_paras_ready),
								.npu_paras_en(cnn_paras_en),
								.npu_paras_addr(cnn_paras_addr),
								.npu_paras_q(cnn_paras_q),

								.DDR_WRITE_CLK(CNN_DDR_WRITE_CLK),
								.DDR_WRITE_ADDR(CNN_DDR_WRITE_ADDR),
								.DDR_WRITE_DATA(CNN_DDR_WRITE_DATA),
								.DDR_WRITE_REQ(CNN_DDR_WRITE_REQ),
								.DDR_WRITE_READY(CNN_DDR_WRITE_READY)
							);




	wire		afi_phy_clk;
	wire		afi_phy_rst_n;



	wire        local_ready;
	wire        local_burstbegin;
	wire [31:0] local_addr;
	wire        local_rdata_valid;
	wire [31:0] local_rdata;
	wire [31:0] local_wdata;
	wire [3:0]  local_be;
	wire        local_read_req;
	wire        local_write_req;
	wire [2:0]  local_size;
	wire		local_waitrequest;

	wire        attach_ready;
	wire        attach_burstbegin;
	wire [31:0] attach_addr;
	wire        attach_rdata_valid;
	wire [31:0] attach_rdata;
	wire [31:0] attach_wdata;
	wire [3:0]  attach_be;
	wire        attach_read_req;
	wire        attach_write_req;
	wire [2:0]  attach_size;
	wire		attach_ready_w, attach_ready_r;
	assign		attach_ready = 	attach_write_req? attach_ready_w : 
								attach_read_req? attach_ready_r : 
								attach_ready_w && attach_ready_r;



	sram_controller		sram_controller_inst(
							.CLOCK(CLOCK40),
							.RESET_N(RESET_N),
							.sram_avalon_clock(afi_phy_clk),
							.sram_avalon_reset_n(afi_phy_rst_n),
							.sram_avalon_address(local_addr),
							.sram_avalon_writedata(local_wdata),
							.sram_avalon_write_n(!local_write_req),
							.sram_avalon_read_n(!local_read_req),
							.sram_avalon_readdata(local_rdata),
							.sram_avalon_readdatavalid(local_rdata_valid),
							.sram_avalon_waitrequest(local_waitrequest),

							.sram_pins_addr(SRAM_ADDR),
							.sram_pins_dq(SRAM_DQ),
							.sram_pins_ce_n(SRAM_CE_N),
							.sram_pins_oe_n(SRAM_OE_N),
							.sram_pins_we_n(SRAM_WE_N),
							.sram_pins_lb_n(SRAM_LB_N),
							.sram_pins_ub_n(SRAM_UB_N)
						);

	mux_ddr_access		mux_ddr_access_local_inst(
							.afi_phy_clk(afi_phy_clk),
							.afi_phy_rst_n(afi_phy_rst_n),

							.local_address(local_addr),
							.local_write_req(local_write_req),
							.local_read_req(local_read_req),
							.local_burstbegin(local_burstbegin),
							.local_wdata(local_wdata),
							.local_be(local_be),
							.local_size(local_size),
							.local_ready(!local_waitrequest),
							.local_rdata(local_rdata),
							.local_rdata_valid(local_rdata_valid),

							.local_init_done(RESET_N),


							.wport_clock_6(afi_phy_clk),
							.wport_addr_6(attach_addr),
							.wport_data_6(attach_wdata),
							.wport_req_6(attach_write_req),
							.wport_ready_6(attach_ready_w),
							.rport_clock_7(afi_phy_clk),
							.rport_addr_7(attach_addr),
							.rport_data_7(attach_rdata),
							.rport_data_valid_7(attach_rdata_valid),
							.rport_req_7(attach_read_req),
							.rport_ready_7(attach_ready_r),

							.wport_clock_4(),
							.wport_addr_4(),
							.wport_data_4(),
							.wport_req_4(),
							.wport_ready_4(),

							.rport_clock_3(),
							.rport_addr_3(),
							.rport_data_3(),
							.rport_data_valid_3(),
							.rport_req_3(),
							.rport_ready_3(),

							.wport_clock_2(CNN_DDR_WRITE_CLK),
							.wport_addr_2(CNN_DDR_WRITE_ADDR),
							.wport_data_2(CNN_DDR_WRITE_DATA),
							.wport_req_2(CNN_DDR_WRITE_REQ && (RUN_MODE||TEST_MODE||SIMU_MODE)),
							.wport_ready_2(CNN_DDR_WRITE_READY),

							.wport_clock_0(NPU_DDR_WRITE_CLK),
							.wport_addr_0(NPU_DDR_WRITE_ADDR),
							.wport_data_0(NPU_DDR_WRITE_DATA),
							.wport_req_0(NPU_DDR_WRITE_REQ && (RUN_MODE||TEST_MODE||SIMU_MODE)),
							.wport_ready_0(NPU_DDR_WRITE_READY),

							.rport_clock_1(NPU_DDR_READ_CLK),
							.rport_addr_1(NPU_DDR_READ_ADDR),
							.rport_data_1(NPU_DDR_READ_DATA),
							.rport_data_valid_1(NPU_DDR_READ_DATA_VALID),
							.rport_req_1(NPU_DDR_READ_REQ && (RUN_MODE||TEST_MODE||SIMU_MODE)),
							.rport_ready_1(NPU_DDR_READ_READY)
						);

	mux_ddr_access		mux_ddr_access_attach_inst(
							.afi_phy_clk(afi_phy_clk),
							.afi_phy_rst_n(afi_phy_rst_n),

							.local_address(attach_addr),
							.local_write_req(attach_write_req),
							.local_read_req(attach_read_req),
							.local_burstbegin(attach_burstbegin),
							.local_wdata(attach_wdata),
							.local_be(attach_be),
							.local_size(attach_size),
							.local_ready(attach_ready),
							.local_rdata(attach_rdata),
							.local_rdata_valid(attach_rdata_valid),

							.local_init_done(RESET_N),


							.wport_clock_4(sys_clk),
							.wport_addr_4(sys_ddr_write_addr),
							.wport_data_4(sys_ddr_write_data),
							.wport_req_4(sys_ddr_write_data_valid),
							.wport_ready_4(sys_ddr_write_data_permitted),

							.rport_clock_5(sys_clk),
							.rport_addr_5(sys_ddr_read_addr),
							.rport_data_5(sys_ddr_read_data),
							.rport_data_valid_5(sys_ddr_read_data_valid),
							.rport_req_5(sys_ddr_read_data_req),
							.rport_ready_5(sys_ddr_read_data_permitted),

							.wport_clock_0(),
							.wport_addr_0(),
							.wport_data_0(),
							.wport_req_0(),
							.wport_ready_0(),

							.wport_clock_2(),
							.wport_addr_2(),
							.wport_data_2(),
							.wport_req_2(),
							.wport_ready_2()
							
						);
	


endmodule