data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim/stream_source.v
 line:62: before: "integer"
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim/stream_source.v:39: Cannot find include file: stream_common.vh\n`include "stream_common.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh.sv\n             stream_common.vh\n             stream_common.vh.v\n             stream_common.vh.sv\n             obj_dir/stream_common.vh\n             obj_dir/stream_common.vh.v\n             obj_dir/stream_common.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module stream_source (clk, rst, dout_valid, dout_ready, dout_data);
`include "stream_common.vh"

  parameter Filename    = "undefined";
  parameter NumSymbols  = 2;
  parameter SymbolBits  = {32'd8, 32'd1};

  parameter MinThroughput = 0;
  parameter MaxThroughput = 100;
  parameter Period        = 1011;
  parameter Seed          = 1;

  localparam TotalWidth = calc_total(NumSymbols, SymbolBits);

  input                    clk;
  input                    rst;
  input                    dout_ready;
  output                   dout_valid;
  output [TotalWidth-1:0]  dout_data;



  wire enable = dout_valid & dout_ready;
  wire done;




  wire [TotalWidth-1:0] rdr_data;
  wire                  rdr_valid;
  file_reader
    #(.Filename (Filename),
    .NumSymbols (NumSymbols),
    .SymbolBits (SymbolBits))
  rdr (
    .clk      (clk),
    .rst      (rst),
    .rd_en    (enable),
    .rd_valid (rdr_valid),
    .rd_data  (rdr_data),
    .done     (done)
    );




  wire active;
  rate_ctrl
    #(.MaxThroughput(MaxThroughput),
      .MinThroughput(MinThroughput),
      .Period       (Period),
      .Seed         (Seed))
  rate(
    .clk   (clk),
    .rst   (rst),
    .active(active),
    .ack   (enable));

  assign dout_valid  = active & rdr_valid;
  assign dout_data = (dout_valid) ? rdr_data : {TotalWidth{1'bx}};

endmodule
module stream_source (clk, rst, dout_valid, dout_ready, dout_data);

`include "stream_common.vh"

  parameter Filename    = "undefined";
  parameter NumSymbols  = 2;
  parameter SymbolBits  = {32'd8, 32'd1};

  parameter MinThroughput = 0;
  parameter MaxThroughput = 100;
  parameter Period        = 1011;
  parameter Seed          = 1;

  localparam TotalWidth = calc_total(NumSymbols, SymbolBits);

  input                    clk;
  input                    rst;
  input                    dout_ready;
  output                   dout_valid;
  output [TotalWidth-1:0]  dout_data;



  wire enable = dout_valid & dout_ready;
  wire done;




  wire [TotalWidth-1:0] rdr_data;
  wire                  rdr_valid;
  file_reader
    #(.Filename (Filename),
    .NumSymbols (NumSymbols),
    .SymbolBits (SymbolBits))
  rdr (
    .clk      (clk),
    .rst      (rst),
    .rd_en    (enable),
    .rd_valid (rdr_valid),
    .rd_data  (rdr_data),
    .done     (done)
    );




  wire active;
  rate_ctrl
    #(.MaxThroughput(MaxThroughput),
      .MinThroughput(MinThroughput),
      .Period       (Period),
      .Seed         (Seed))
  rate(
    .clk   (clk),
    .rst   (rst),
    .active(active),
    .ack   (enable));

  assign dout_valid  = active & rdr_valid;
  assign dout_data = (dout_valid) ? rdr_data : {TotalWidth{1'bx}};

endmodule