data/full_repos/permissive/143278/ivltests/pr2976242b.v
 line:7: before: "real"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2976242b.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1 in = 1\'b1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2976242b.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #0.5 in = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2976242b.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #0.5 in = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2976242b.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #0.5 in = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2976242b.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #0.5 in = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2976242b.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #0.5 in = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2976242b.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #0.5 in = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2976242b.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (pass) $display("PASSED");\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2976242b.v:36: Unsupported: Ignoring delay on this delayed statement.\n  always @(out_arr) #0.1 if ((out_arr[1:0] !== ($stime % 4)) &&\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2976242b.v:24: Operator NEQCASE expects 32 bits on the LHS, but LHS\'s VARREF \'out_bit\' generates 1 bits.\n                                                                          : ... In instance top\n  always @(out_bit) if (out_bit !== ($stime % 2)) begin\n                                ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2976242b.v:30: Operator NEQCASE expects 32 bits on the LHS, but LHS\'s VARREF \'out_vec\' generates 4 bits.\n                                                                          : ... In instance top\n  always @(out_vec) if (out_vec !== $stime) begin\n                                ^~~\n%Error: data/full_repos/permissive/143278/ivltests/pr2976242b.v:35: Output port connection \'out\' as part of a module instance array requires 64 or 128 bits, but connection\'s VARREF \'out_arr\' generates 4 bits.\n                                                                  : ... In instance top\n  real_to_xx u3[1:0](out_arr, in);\n                     ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2976242b.v:36: Operator NEQCASE expects 32 bits on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                          : ... In instance top\n  always @(out_arr) #0.1 if ((out_arr[1:0] !== ($stime % 4)) &&\n                                           ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2976242b.v:37: Operator NEQCASE expects 32 bits on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                          : ... In instance top\n                             (out_arr[3:2] !== ($stime % 4))) begin\n                                           ^~~\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/pr2976242b.v:43: Implicit conversion of real to integer\n  bit_to_real u4(r_bit, in);\n                 ^~~~~\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/pr2976242b.v:49: Implicit conversion of real to integer\n  vec_to_real u5(r_vec, in);\n                 ^~~~~\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module real_to_xx (output wire real out, input wire in);
  real rval;
  assign out = rval;
  always @(posedge in) rval = rval + 1;
endmodule
module real_to_xx (output wire real out, input wire in);

  real rval;
  assign out = rval;
  always @(posedge in) rval = rval + 1;
endmodule