data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v
1: b'%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:40: Cannot find file containing module: \'clkdiv\'\n    clkdiv c1(clk,myclk);\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/clkdiv\n             data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/clkdiv.v\n             data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/clkdiv.sv\n             clkdiv\n             clkdiv.v\n             clkdiv.sv\n             obj_dir/clkdiv\n             obj_dir/clkdiv.v\n             obj_dir/clkdiv.sv\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:41: Cannot find file containing module: \'beepdiv\'\n    beepdiv c2(clk,beepclk);\n    ^~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:42: Cannot find file containing module: \'disdiv\'\n    disdiv c3(clk,disclk);\n    ^~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:62: Cannot find file containing module: \'mips\'\n    mips mips(realclk,reset,pc,instr,memwrite,memtoreg,\n    ^~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:67: Cannot find file containing module: \'icache2\'\n    icache2 icache2(clk,reset,pc,instr,iready,\n    ^~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:71: Cannot find file containing module: \'dcache2\'\n    dcache2 dcache2(realclk,reset,memwrite,memtoreg|memwrite,\n    ^~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:99: Cannot find file containing module: \'display\'\n    display dis0(T[3:0], C0,disop[0]);\n    ^~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:100: Cannot find file containing module: \'display\'\n    display dis1(T[7:4], C1,disop[1]);\n    ^~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:101: Cannot find file containing module: \'display\'\n    display dis2(T[11:8], C2,disop[2]);\n    ^~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:102: Cannot find file containing module: \'display\'\n    display dis3(T[15:12], C3,disop[3]);\n    ^~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:103: Cannot find file containing module: \'display\'\n    display dis4(T[19:16], C4,disop[4]);\n    ^~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:104: Cannot find file containing module: \'display\'\n    display dis5(T[23:20], C5,disop[5]);\n    ^~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:105: Cannot find file containing module: \'display\'\n    display dis6(T[27:24], C6,disop[6]);\n    ^~~~~~~\n%Error: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:106: Cannot find file containing module: \'display\'\n    display dis7(T[31:28], C7,disop[7]);\n    ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:159: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                                                             : ... In instance top\n            cnt<=3\'b0;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:112: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                                                             : ... In instance top\n        case(cnt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:112: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h1\' generates 3 bits.\n                                                                                                                                             : ... In instance top\n        case(cnt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:112: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h2\' generates 3 bits.\n                                                                                                                                             : ... In instance top\n        case(cnt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:112: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h3\' generates 3 bits.\n                                                                                                                                             : ... In instance top\n        case(cnt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:112: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                                                                             : ... In instance top\n        case(cnt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:112: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                                                                             : ... In instance top\n        case(cnt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:112: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                                                                             : ... In instance top\n        case(cnt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/top.v:112: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                                                                             : ... In instance top\n        case(cnt)\n        ^~~~\n%Error: Exiting due to 14 error(s), 9 warning(s)\n'
module top(
    input clk,reset,next,stop,
    input [9:0] SW,
    input [2:0] lsrc,
    output [15:0] LED,
    output reg [6:0] C,
    output reg [7:0] AN
    );
    
    wire [31:0] pc,instr,readdata;
    wire [31:0] writedata,dataadr;
    wire memwrite;
    
    reg [31:0] cycle;
    

    wire realclk,myclk,beepclk,disclk;
    clkdiv c1(clk,myclk);
    beepdiv c2(clk,beepclk);
    disdiv c3(clk,disclk);
    assign realclk=next|((~stop)&myclk);
    

    reg [7:0] disop;
    wire [7:0] disop0,disop1,disop2;
    reg [31:0] T;
    wire [31:0] t0,t1,t2;
    
    wire [6:0] C0,C1,C2,C3,C4,C5,C6,C7;
    
    wire iready,dready,memtoreg;
    

    initial
        cycle<=32'b0;
    always@(posedge realclk)
        cycle<=cycle+1;
    

    mips mips(realclk,reset,pc,instr,memwrite,memtoreg,
              dataadr,writedata,readdata,
              lsrc,LED,beepclk,
              dready,iready,
              SW,t0,disop0);
    icache2 icache2(clk,reset,pc,instr,iready,
                    SW,t1,disop1);


    dcache2 dcache2(realclk,reset,memwrite,memtoreg|memwrite,
                    dataadr,writedata,readdata,
                    dready,
                    SW,t2,disop2);


    

    parameter ZERO=8'b0;
    parameter EIGHT=8'b11111111;
    always@(*)
    case(SW[9:7])
    3'b000:
        case(SW[6:0])
        7'b0:begin T<=cycle;disop<=EIGHT;end
        default:begin T<=t0;disop<=disop0;end
        endcase
    3'b001:begin T<=t0;disop<=disop0;end
    3'b010:begin T<=t1;disop<=disop1;end
    3'b011:begin T<=t2;disop<=disop2;end
    3'b100:begin T<=t2;disop<=disop2;end
    3'b101:begin T<=t2;disop<=disop2;end
    3'b110:begin T<=t1;disop<=disop1;end
    3'b111:begin T<=t1;disop<=disop1;end
    default:begin T<=32'b0;disop<=ZERO;end
    endcase
    

    display dis0(T[3:0], C0,disop[0]);
    display dis1(T[7:4], C1,disop[1]);
    display dis2(T[11:8], C2,disop[2]);
    display dis3(T[15:12], C3,disop[3]);
    display dis4(T[19:16], C4,disop[4]);
    display dis5(T[23:20], C5,disop[5]);
    display dis6(T[27:24], C6,disop[6]);
    display dis7(T[31:28], C7,disop[7]);
    

    reg [3:0] cnt;
    always@(posedge disclk)
    begin
        case(cnt)
        3'b000:
            begin
            AN<=8'b11111110;
            C<=C0;
            cnt<=cnt+1;
            end
        3'b001:
            begin
            AN<=8'b11111101;
            C<=C1;
            cnt<=cnt+1;
            end
        3'b010:
            begin
            AN<=8'b11111011;
            C<=C2;
            cnt<=cnt+1;
            end
        3'b011:
            begin
            AN<=8'b11110111;
            C<=C3;
            cnt<=cnt+1;
            end
        3'b100:
            begin
            AN<=8'b11101111;
            C<=C4;
            cnt<=cnt+1;
            end
        3'b101:
            begin
            AN<=8'b11011111;
            C<=C5;
            cnt<=cnt+1;
            end
        3'b110:
            begin
            AN<=8'b10111111;
            C<=C6;
            cnt<=cnt+1;
            end
        3'b111:
            begin
            AN<=8'b01111111;
            C<=C7;
            cnt<=3'b0;
            end
        endcase
    end        
    
endmodule
module top(
    input clk,reset,next,stop,
    input [9:0] SW,
    input [2:0] lsrc,
    output [15:0] LED,
    output reg [6:0] C,
    output reg [7:0] AN
    );

    
    wire [31:0] pc,instr,readdata;
    wire [31:0] writedata,dataadr;
    wire memwrite;
    
    reg [31:0] cycle;
    

    wire realclk,myclk,beepclk,disclk;
    clkdiv c1(clk,myclk);
    beepdiv c2(clk,beepclk);
    disdiv c3(clk,disclk);
    assign realclk=next|((~stop)&myclk);
    

    reg [7:0] disop;
    wire [7:0] disop0,disop1,disop2;
    reg [31:0] T;
    wire [31:0] t0,t1,t2;
    
    wire [6:0] C0,C1,C2,C3,C4,C5,C6,C7;
    
    wire iready,dready,memtoreg;
    

    initial
        cycle<=32'b0;
    always@(posedge realclk)
        cycle<=cycle+1;
    

    mips mips(realclk,reset,pc,instr,memwrite,memtoreg,
              dataadr,writedata,readdata,
              lsrc,LED,beepclk,
              dready,iready,
              SW,t0,disop0);
    icache2 icache2(clk,reset,pc,instr,iready,
                    SW,t1,disop1);


    dcache2 dcache2(realclk,reset,memwrite,memtoreg|memwrite,
                    dataadr,writedata,readdata,
                    dready,
                    SW,t2,disop2);


    

    parameter ZERO=8'b0;
    parameter EIGHT=8'b11111111;
    always@(*)
    case(SW[9:7])
    3'b000:
        case(SW[6:0])
        7'b0:begin T<=cycle;disop<=EIGHT;end
        default:begin T<=t0;disop<=disop0;end
        endcase
    3'b001:begin T<=t0;disop<=disop0;end
    3'b010:begin T<=t1;disop<=disop1;end
    3'b011:begin T<=t2;disop<=disop2;end
    3'b100:begin T<=t2;disop<=disop2;end
    3'b101:begin T<=t2;disop<=disop2;end
    3'b110:begin T<=t1;disop<=disop1;end
    3'b111:begin T<=t1;disop<=disop1;end
    default:begin T<=32'b0;disop<=ZERO;end
    endcase
    

    display dis0(T[3:0], C0,disop[0]);
    display dis1(T[7:4], C1,disop[1]);
    display dis2(T[11:8], C2,disop[2]);
    display dis3(T[15:12], C3,disop[3]);
    display dis4(T[19:16], C4,disop[4]);
    display dis5(T[23:20], C5,disop[5]);
    display dis6(T[27:24], C6,disop[6]);
    display dis7(T[31:28], C7,disop[7]);
    

    reg [3:0] cnt;
    always@(posedge disclk)
    begin
        case(cnt)
        3'b000:
            begin
            AN<=8'b11111110;
            C<=C0;
            cnt<=cnt+1;
            end
        3'b001:
            begin
            AN<=8'b11111101;
            C<=C1;
            cnt<=cnt+1;
            end
        3'b010:
            begin
            AN<=8'b11111011;
            C<=C2;
            cnt<=cnt+1;
            end
        3'b011:
            begin
            AN<=8'b11110111;
            C<=C3;
            cnt<=cnt+1;
            end
        3'b100:
            begin
            AN<=8'b11101111;
            C<=C4;
            cnt<=cnt+1;
            end
        3'b101:
            begin
            AN<=8'b11011111;
            C<=C5;
            cnt<=cnt+1;
            end
        3'b110:
            begin
            AN<=8'b10111111;
            C<=C6;
            cnt<=cnt+1;
            end
        3'b111:
            begin
            AN<=8'b01111111;
            C<=C7;
            cnt<=3'b0;
            end
        endcase
    end        
    
endmodule