data/full_repos/permissive/208741034/seg_led_static/rtl/timer_count.v
 line:32: before: "/"
data/verilator_xmls/657677cd-66b7-48c5-a9b0-69f661034914.xml
module timer_count(
    input      clk,
    input    rst_n,

    output reg cnt_flag
    
);


parameter  MAX_CNT_NUM = 25_000_000;

reg [24 : 0]  cnt;

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
    cnt <= 25'd0;
    cnt_flag <= 1'd0;
    end
    else begin
        if(cnt < MAX_CNT_NUM)begin
        cnt <= cnt + 1'd1;
        cnt_flag <= 1'b0;
        end
        else begin
        cnt <= 25'd0;
        cnt_flag <= 1'b1;
        end
    end
    
end

endmodule
module timer_count(
    input      clk,
    input    rst_n,

    output reg cnt_flag
    
);



parameter  MAX_CNT_NUM = 25_000_000;

reg [24 : 0]  cnt;

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
    cnt <= 25'd0;
    cnt_flag <= 1'd0;
    end
    else begin
        if(cnt < MAX_CNT_NUM)begin
        cnt <= cnt + 1'd1;
        cnt_flag <= 1'b0;
        end
        else begin
        cnt <= 25'd0;
        cnt_flag <= 1'b1;
        end
    end
    
end

endmodule