data/full_repos/permissive/213361049/Div_tb.v
1: b'%Error: data/full_repos/permissive/213361049/Div_tb.v:8: Unsupported or unknown PLI call: $monitor\n  $monitor("A: %d B: %d Quotient: %d",A,B,Res);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/213361049/Div_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #100; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/213361049/Div_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/Div_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/Div_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/Div_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/Div_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module division_tb();
    parameter WIDTH = 16;
    reg [WIDTH-1:0] A;
    reg [WIDTH-1:0] B;
    wire [WIDTH-1:0] Res;
    division uut (A,B,Res);
    initial begin
		$monitor("A: %d B: %d Quotient: %d",A,B,Res);
        A = 0;  
		B = 0;  
		#100; 
		
        A = 100;    
		B = 10; 
		#100;
		
        A = 200;
		B = 40; 
		#100;
		
        A = 90; 
		B = 9;  
		#100;
		
        A = 70; 
		B = 10; 
		#100;
		
        A = 16; 
		B = 3;  
		#100;
		
        A = 255;    
		B = 5;  
		
    end
      
endmodule
module division_tb();

    parameter WIDTH = 16;
    reg [WIDTH-1:0] A;
    reg [WIDTH-1:0] B;
    wire [WIDTH-1:0] Res;
    division uut (A,B,Res);
    initial begin
		$monitor("A: %d B: %d Quotient: %d",A,B,Res);
        A = 0;  
		B = 0;  
		#100; 
		
        A = 100;    
		B = 10; 
		#100;
		
        A = 200;
		B = 40; 
		#100;
		
        A = 90; 
		B = 9;  
		#100;
		
        A = 70; 
		B = 10; 
		#100;
		
        A = 16; 
		B = 3;  
		#100;
		
        A = 255;    
		B = 5;  
		
    end
      
endmodule