data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/hdl/top_lib/top_gpio_out.v
data/verilator_xmls/fba9e05d-0be5-438e-bfbf-e1a2e5f52520.xml
module top_gpio_out
(
    input wire clk_100mhz,
    input wire reset_n,


    input wire bus_clk,
    inout wire [7:0] bus_data,
    input wire bus_rnw,

    output wire [3:0] led_out,
    output wire led0_r,
    output wire led0_g,
    output wire led1_r
);

assign led_out[3:0] = bus_data[3:0];

assign led0_r = ~reset_n;
assign led0_g = 0;
assign led1_r = 0;

endmodule
module top_gpio_out
(
    input wire clk_100mhz,
    input wire reset_n,


    input wire bus_clk,
    inout wire [7:0] bus_data,
    input wire bus_rnw,

    output wire [3:0] led_out,
    output wire led0_r,
    output wire led0_g,
    output wire led1_r
);


assign led_out[3:0] = bus_data[3:0];

assign led0_r = ~reset_n;
assign led0_g = 0;
assign led1_r = 0;

endmodule