data/full_repos/permissive/114642806/main/fsm.v
data/verilator_xmls/8216b74a-c713-42da-893a-45763aa7c526.xml
module counter5s(CLOCK_50, enable);
  input CLOCK_50;
  output enable;

  wire enable_second_counter;
	counter01 u1(CLOCK_50, enable_second_counter);
  counter5pos u3(enable_second_counter, enable);
endmodule
module counter5s(CLOCK_50, enable);

  input CLOCK_50;
  output enable;

  wire enable_second_counter;
	counter01 u1(CLOCK_50, enable_second_counter);
  counter5pos u3(enable_second_counter, enable);
endmodule