data/full_repos/permissive/168578692/Divider.v
data/verilator_xmls/9228d55e-0016-4e7f-80c9-231bd341db1c.xml
module Divider(
  input clock,
  output reg divided_Clock
);


reg [19:0] counter;


initial counter = 20'b00000000000000000000;
initial divided_Clock = 1'b0;


always @ (posedge clock) begin

  if(counter >= 20'hf423f) begin

    counter = 20'b00000000000000000000;

    divided_Clock = 1'b1;
  end
  else begin

    counter = counter + 1;
    divided_Clock = 1'b0;
  end
end
endmodule
module Divider(
  input clock,
  output reg divided_Clock
);



reg [19:0] counter;


initial counter = 20'b00000000000000000000;
initial divided_Clock = 1'b0;


always @ (posedge clock) begin

  if(counter >= 20'hf423f) begin

    counter = 20'b00000000000000000000;

    divided_Clock = 1'b1;
  end
  else begin

    counter = counter + 1;
    divided_Clock = 1'b0;
  end
end
endmodule