data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Basics/norgate.v
data/verilator_xmls/173db8e4-4d7a-4542-8f5f-4ca1d6fb6965.xml
module top_module( 
    input a, 
    input b, 
    output out );
    assign out = !(a|b);
endmodule
module top_module( 
    input a, 
    input b, 
    output out );

    assign out = !(a|b);
endmodule