data/full_repos/permissive/123690745/alutb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123690745/alutb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123690745/alutb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #100;  \n  ^\n%Error: data/full_repos/permissive/123690745/alutb.v:38: Cannot find file containing module: \'ALU\'\n ALU uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/ALU\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/ALU.v\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alutb;


	reg [31:0] A;
	reg [31:0] B;
	reg [4:0] msb;
	reg [4:0] lsb;
	reg [3:0] OP;


	wire [31:0] Out;


	ALU uut (
		.A(A), 
		.B(B),
		.msb(msb),
		.lsb(lsb),
		.Out(Out), 
		.OP(OP)
	);

	initial begin

		A = 32'h12345678;
		B = 32'hffffffff;
		OP = 13;
		msb = 3;
		lsb = 0;

		#100;
      OP = 13;
		msb = 11;
		lsb = 12;

		#100;  


	end
      
endmodule
module alutb;



	reg [31:0] A;
	reg [31:0] B;
	reg [4:0] msb;
	reg [4:0] lsb;
	reg [3:0] OP;


	wire [31:0] Out;


	ALU uut (
		.A(A), 
		.B(B),
		.msb(msb),
		.lsb(lsb),
		.Out(Out), 
		.OP(OP)
	);

	initial begin

		A = 32'h12345678;
		B = 32'hffffffff;
		OP = 13;
		msb = 3;
		lsb = 0;

		#100;
      OP = 13;
		msb = 11;
		lsb = 12;

		#100;  


	end
      
endmodule