data/full_repos/permissive/106408053/verilog/trigger_adv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n              ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module trigterm_range_byte (dataIn, clock, wrenb, din, dout, cin, cout);
input [7:0] dataIn;
input clock, wrenb, din, cin;
output dout, cout;
wire [6:0] chain, carry;
trigterm_range_bit bit0 (dataIn[0], clock, wrenb, din, chain[0], cin, carry[0]);
trigterm_range_bit bit1 (dataIn[1], clock, wrenb, chain[0], chain[1], carry[0], carry[1]);
trigterm_range_bit bit2 (dataIn[2], clock, wrenb, chain[1], chain[2], carry[1], carry[2]);
trigterm_range_bit bit3 (dataIn[3], clock, wrenb, chain[2], chain[3], carry[2], carry[3]);
trigterm_range_bit bit4 (dataIn[4], clock, wrenb, chain[3], chain[4], carry[3], carry[4]);
trigterm_range_bit bit5 (dataIn[5], clock, wrenb, chain[4], chain[5], carry[4], carry[5]);
trigterm_range_bit bit6 (dataIn[6], clock, wrenb, chain[5], chain[6], carry[5], carry[6]);
trigterm_range_bit bit7 (dataIn[7], clock, wrenb, chain[6], dout, carry[6], cout);
endmodule
module trigterm_range_byte (dataIn, clock, wrenb, din, dout, cin, cout);

input [7:0] dataIn;
input clock, wrenb, din, cin;
output dout, cout;
wire [6:0] chain, carry;
trigterm_range_bit bit0 (dataIn[0], clock, wrenb, din, chain[0], cin, carry[0]);
trigterm_range_bit bit1 (dataIn[1], clock, wrenb, chain[0], chain[1], carry[0], carry[1]);
trigterm_range_bit bit2 (dataIn[2], clock, wrenb, chain[1], chain[2], carry[1], carry[2]);
trigterm_range_bit bit3 (dataIn[3], clock, wrenb, chain[2], chain[3], carry[2], carry[3]);
trigterm_range_bit bit4 (dataIn[4], clock, wrenb, chain[3], chain[4], carry[3], carry[4]);
trigterm_range_bit bit5 (dataIn[5], clock, wrenb, chain[4], chain[5], carry[4], carry[5]);
trigterm_range_bit bit6 (dataIn[6], clock, wrenb, chain[5], chain[6], carry[5], carry[6]);
trigterm_range_bit bit7 (dataIn[7], clock, wrenb, chain[6], dout, carry[6], cout);
endmodule