data/full_repos/permissive/157101210/forwarding.t.v
1: b'%Error: data/full_repos/permissive/157101210/forwarding.t.v:1: Cannot find include file: forwarding.v\n`include "forwarding.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/forwarding.v\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/forwarding.v.v\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/forwarding.v.sv\n             forwarding.v\n             forwarding.v.v\n             forwarding.v.sv\n             obj_dir/forwarding.v\n             obj_dir/forwarding.v.v\n             obj_dir/forwarding.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/157101210/forwarding.t.v:18: Unsupported: Ignoring delay on this delayed statement.\n  targetReg=5\'b10101; targetData=32\'d3; #100\n                                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157101210/forwarding.t.v:22: Unsupported: Ignoring delay on this delayed statement.\n  targetReg=5\'b10000; targetData=32\'d3; #100\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/forwarding.t.v:26: Unsupported: Ignoring delay on this delayed statement.\n  targetReg=5\'b00001; targetData=32\'d3; #100\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/forwarding.t.v:31: Unsupported: Ignoring delay on this delayed statement.\n  targetReg=10000; targetData=32\'d3; #100\n                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/forwarding.t.v:41: Unsupported: Ignoring delay on this delayed statement.\n  targetReg=5\'b10101; targetData=32\'d3; #100\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/forwarding.t.v:45: Unsupported: Ignoring delay on this delayed statement.\n  targetReg=5\'b10000; targetData=32\'d3; #100\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/forwarding.t.v:49: Unsupported: Ignoring delay on this delayed statement.\n  targetReg=5\'b00001; targetData=32\'d3; #100\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/forwarding.t.v:54: Unsupported: Ignoring delay on this delayed statement.\n  targetReg=10000; targetData=32\'d3; #100\n                                     ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n'
module forwardingTest();
	reg[31:0] targetData, MEM_data, WB_data;
	reg[4:0] targetReg, MEM_reg, WB_reg;
	reg MEM_regWr, WB_regWr;
	wire[31:0] data;
	forwarding forwarding(targetReg, targetData, MEM_reg, MEM_data, MEM_regWr, WB_reg, WB_data, WB_regWr, data);

	initial begin
		$display("Starting forwarding testing");

		MEM_regWr=1; WB_regWr=1; 
		MEM_data=32'd1; WB_data=32'd2;
		MEM_reg=5'b10000; WB_reg=5'b00001;


		targetReg=5'b10101; targetData=32'd3; #100
		if(data !== 32'd3) $display("Test 1 failed - %d", data);


		targetReg=5'b10000; targetData=32'd3; #100
		if(data !== 32'd1) $display("Test 2 failed - %d", data);


		targetReg=5'b00001; targetData=32'd3; #100
		if(data !== 32'd2) $display("Test 3 failed - %d", data);

		WB_reg=5'b10000;

		targetReg=10000; targetData=32'd3; #100
		if(data !== 32'd1) $display("Test 4 failed - %d", data);



		MEM_regWr=0; WB_regWr=0; 
		MEM_data=32'd1; WB_data=32'd2;
		MEM_reg=5'b10000; WB_reg=5'b00001;


		targetReg=5'b10101; targetData=32'd3; #100
		if(data !== 32'd3) $display("Test 5 failed - %d", data);


		targetReg=5'b10000; targetData=32'd3; #100
		if(data !== 32'd3) $display("Test 6 failed - %d", data);


		targetReg=5'b00001; targetData=32'd3; #100
		if(data !== 32'd3) $display("Test 7 failed - %d", data);

		WB_reg=5'b10000;

		targetReg=10000; targetData=32'd3; #100
		if(data !== 32'd3) $display("Test 8 failed - %d", data);

		$display("Finished forwarding testing");
	end

endmodule
module forwardingTest();

	reg[31:0] targetData, MEM_data, WB_data;
	reg[4:0] targetReg, MEM_reg, WB_reg;
	reg MEM_regWr, WB_regWr;
	wire[31:0] data;
	forwarding forwarding(targetReg, targetData, MEM_reg, MEM_data, MEM_regWr, WB_reg, WB_data, WB_regWr, data);

	initial begin
		$display("Starting forwarding testing");

		MEM_regWr=1; WB_regWr=1; 
		MEM_data=32'd1; WB_data=32'd2;
		MEM_reg=5'b10000; WB_reg=5'b00001;


		targetReg=5'b10101; targetData=32'd3; #100
		if(data !== 32'd3) $display("Test 1 failed - %d", data);


		targetReg=5'b10000; targetData=32'd3; #100
		if(data !== 32'd1) $display("Test 2 failed - %d", data);


		targetReg=5'b00001; targetData=32'd3; #100
		if(data !== 32'd2) $display("Test 3 failed - %d", data);

		WB_reg=5'b10000;

		targetReg=10000; targetData=32'd3; #100
		if(data !== 32'd1) $display("Test 4 failed - %d", data);



		MEM_regWr=0; WB_regWr=0; 
		MEM_data=32'd1; WB_data=32'd2;
		MEM_reg=5'b10000; WB_reg=5'b00001;


		targetReg=5'b10101; targetData=32'd3; #100
		if(data !== 32'd3) $display("Test 5 failed - %d", data);


		targetReg=5'b10000; targetData=32'd3; #100
		if(data !== 32'd3) $display("Test 6 failed - %d", data);


		targetReg=5'b00001; targetData=32'd3; #100
		if(data !== 32'd3) $display("Test 7 failed - %d", data);

		WB_reg=5'b10000;

		targetReg=10000; targetData=32'd3; #100
		if(data !== 32'd3) $display("Test 8 failed - %d", data);

		$display("Finished forwarding testing");
	end

endmodule