data/full_repos/permissive/21438680/DAQ_Firmware/src/ram/alt_mem_ddrx_timing_param.v
None: at end of input
1: b'%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ram/alt_mem_ddrx_timing_param.v:4: Cannot find include file: alt_mem_ddrx_define.iv\n`include "alt_mem_ddrx_define.iv" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21438680/DAQ_Firmware/src/ram,data/full_repos/permissive/21438680/alt_mem_ddrx_define.iv\n             data/full_repos/permissive/21438680/DAQ_Firmware/src/ram,data/full_repos/permissive/21438680/alt_mem_ddrx_define.iv.v\n             data/full_repos/permissive/21438680/DAQ_Firmware/src/ram,data/full_repos/permissive/21438680/alt_mem_ddrx_define.iv.sv\n             alt_mem_ddrx_define.iv\n             alt_mem_ddrx_define.iv.v\n             alt_mem_ddrx_define.iv.sv\n             obj_dir/alt_mem_ddrx_define.iv\n             obj_dir/alt_mem_ddrx_define.iv.v\n             obj_dir/alt_mem_ddrx_define.iv.sv\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ram/alt_mem_ddrx_timing_param.v:535: Define or directive not defined: \'`MMR_TYPE_DDR1\'\n            if (cfg_type == `MMR_TYPE_DDR1)\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ram/alt_mem_ddrx_timing_param.v:535: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if (cfg_type == `MMR_TYPE_DDR1)\n                                          ^\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ram/alt_mem_ddrx_timing_param.v:562: syntax error, unexpected else\n            else if (cfg_type == `MMR_TYPE_DDR2)\n            ^~~~\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ram/alt_mem_ddrx_timing_param.v:562: Define or directive not defined: \'`MMR_TYPE_DDR2\'\n            else if (cfg_type == `MMR_TYPE_DDR2)\n                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ram/alt_mem_ddrx_timing_param.v:589: syntax error, unexpected else\n            else if (cfg_type == `MMR_TYPE_DDR3)\n            ^~~~\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ram/alt_mem_ddrx_timing_param.v:589: Define or directive not defined: \'`MMR_TYPE_DDR3\'\n            else if (cfg_type == `MMR_TYPE_DDR3)\n                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ram/alt_mem_ddrx_timing_param.v:621: Define or directive not defined: \'`MMR_TYPE_LPDDR1\'\n            else if (cfg_type == `MMR_TYPE_LPDDR1)\n                                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ram/alt_mem_ddrx_timing_param.v:648: Define or directive not defined: \'`MMR_TYPE_LPDDR2\'\n            else if (cfg_type == `MMR_TYPE_LPDDR2)\n                                 ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
function [MAX_FUNCTION_PORT_WIDTH - 1 : 0] max;
        input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value1;
        input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value2;
        begin
            if (value1 > value2)
                max = value1;
            else
                max = value2;
        end
    endfunction
function [MAX_FUNCTION_PORT_WIDTH - 1 : 0] max;

        input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value1;
        input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value2;
        begin
            if (value1 > value2)
                max = value1;
            else
                max = value2;
        end
    endfunction