data/full_repos/permissive/19880520/src/rtl/bp_osc.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/19880520/src/rtl/bp_osc.v:97: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                       : ... In instance bp_osc\n      sum = opa + opb + cin;\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module bp_osc #(parameter WIDTH = 8)
             (
              input wire                   clk,
              input wire                   reset_n,

              input wire [(WIDTH - 1) : 0] opa,
              input wire [(WIDTH - 1) : 0] opb,

              output wire                  dout
             );




  reg dout_reg;





  reg [WIDTH : 0] sum;
  reg 	          cin;





  assign dout = dout_reg;





     always @ (posedge clk or negedge reset_n)
       begin
         if (!reset_n)
           begin
             dout_reg <= 1'b0;
           end
         else
           begin
             dout_reg <= cin;
           end
       end










  always @*
    begin: adder_osc
      cin = ~sum[WIDTH];
      sum = opa + opb + cin;
    end
endmodule
module bp_osc #(parameter WIDTH = 8)
             (
              input wire                   clk,
              input wire                   reset_n,

              input wire [(WIDTH - 1) : 0] opa,
              input wire [(WIDTH - 1) : 0] opb,

              output wire                  dout
             );





  reg dout_reg;





  reg [WIDTH : 0] sum;
  reg 	          cin;





  assign dout = dout_reg;





     always @ (posedge clk or negedge reset_n)
       begin
         if (!reset_n)
           begin
             dout_reg <= 1'b0;
           end
         else
           begin
             dout_reg <= cin;
           end
       end










  always @*
    begin: adder_osc
      cin = ~sum[WIDTH];
      sum = opa + opb + cin;
    end
endmodule