data/full_repos/permissive/122184933/FPGA/slip_rx.v
data/verilator_xmls/1e54ebd8-f473-4d39-ad1e-e5541b2deeb3.xml
module slip_rx (

	input wire clk, rst,
	

	output reg frame,
	

	input wire [7:0] din,

	input wire din_rdy,
	

	output reg [7:0] dout,

	output reg dout_rdy,

	input wire dout_ack
);


localparam SOF 			= 0;
localparam READ			= 1;
localparam ESC			= 2;


localparam CHAR_END  	= 8'hC0;
localparam CHAR_ESC		= 8'hDB;
localparam CHAR_ESC_END	= 8'hDC;
localparam CHAR_ESC_ESC = 8'hDD;


reg [1:0] state;

reg [7:0] din_buf;


always @ (posedge clk or posedge rst)
begin

	if (rst) begin
		state <= SOF; frame <= 1'b0;
		dout_rdy <= 0; dout <= 0;

	end else begin

		if (dout_ack)
			dout_rdy <= 1'b0;
			

		if (din_rdy) begin

			case (state)

			SOF : begin
				dout <= din; 

				if (din == CHAR_END)
					state <= READ;
			end

			READ : begin
				dout <= din; 

				if (din == CHAR_END) begin

					if (frame) begin
						frame <= 1'b0; state <= SOF;
					end

				end else begin

					frame <= 1'b1;

					if (din == CHAR_ESC) begin
						state <= ESC;

					end else begin
						dout_rdy <= 1'b1;
					end
				end
			end

			ESC : begin

				dout <= din == CHAR_ESC_END ? CHAR_END : CHAR_ESC;

				state <= READ; dout_rdy <= 1'b1;
			end
			endcase
		end
	end
end

endmodule
module slip_rx (

	input wire clk, rst,
	

	output reg frame,
	

	input wire [7:0] din,

	input wire din_rdy,
	

	output reg [7:0] dout,

	output reg dout_rdy,

	input wire dout_ack
);



localparam SOF 			= 0;
localparam READ			= 1;
localparam ESC			= 2;


localparam CHAR_END  	= 8'hC0;
localparam CHAR_ESC		= 8'hDB;
localparam CHAR_ESC_END	= 8'hDC;
localparam CHAR_ESC_ESC = 8'hDD;


reg [1:0] state;

reg [7:0] din_buf;


always @ (posedge clk or posedge rst)
begin

	if (rst) begin
		state <= SOF; frame <= 1'b0;
		dout_rdy <= 0; dout <= 0;

	end else begin

		if (dout_ack)
			dout_rdy <= 1'b0;
			

		if (din_rdy) begin

			case (state)

			SOF : begin
				dout <= din; 

				if (din == CHAR_END)
					state <= READ;
			end

			READ : begin
				dout <= din; 

				if (din == CHAR_END) begin

					if (frame) begin
						frame <= 1'b0; state <= SOF;
					end

				end else begin

					frame <= 1'b1;

					if (din == CHAR_ESC) begin
						state <= ESC;

					end else begin
						dout_rdy <= 1'b1;
					end
				end
			end

			ESC : begin

				dout <= din == CHAR_ESC_END ? CHAR_END : CHAR_ESC;

				state <= READ; dout_rdy <= 1'b1;
			end
			endcase
		end
	end
end

endmodule