data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:1: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Mips/Type/Word.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Mips/Type/Word.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Mips/Type/Word.v.sv\n             Mips/Type/Word.v\n             Mips/Type/Word.v.v\n             Mips/Type/Word.v.sv\n             obj_dir/Mips/Type/Word.v\n             obj_dir/Mips/Type/Word.v.v\n             obj_dir/Mips/Type/Word.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:2: Cannot find include file: Mips/Type/RegAddr.v\n`include "Mips/Type/RegAddr.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:3: Cannot find include file: Mips/Instruction/Format/RFormat.v\n`include "Mips/Instruction/Format/RFormat.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:5: Cannot find include file: Mips/Control/Signal/Register/Signal/WriteAddrSource.v\n`include "Mips/Control/Signal/Register/Signal/WriteAddrSource.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:8: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteAddrSource_T\'\n ( `Mips_Control_Signal_Register_Signal_WriteAddrSource_T(input) control\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:8: syntax error, unexpected \'(\', expecting \'[\'\n ( `Mips_Control_Signal_Register_Signal_WriteAddrSource_T(input) control\n                                                          ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:9: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T(input) instruction\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:10: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n , `Mips_Type_RegAddr_T(output) wrAddr\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:13: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n`Mips_Type_RegAddr_T (wire) rs;\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:14: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n`Mips_Type_RegAddr_T (wire) rt;\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:15: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n`Mips_Type_RegAddr_T (wire) rd;\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:16: Define or directive not defined: \'`Mips_Instruction_Format_RFormat_Rs\'\nassign rs = `Mips_Instruction_Format_RFormat_Rs(instruction);\n            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:17: Define or directive not defined: \'`Mips_Instruction_Format_RFormat_Rd\'\nassign rd = `Mips_Instruction_Format_RFormat_Rd(instruction);\n            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:18: Define or directive not defined: \'`Mips_Instruction_Format_RFormat_Rt\'\nassign rt = `Mips_Instruction_Format_RFormat_Rt(instruction);\n            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:20: Define or directive not defined: \'`Mips_Type_RegAddr_T\'\n`Mips_Type_RegAddr_T (reg) wrAddr$;\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:23: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteAddrSource_Rd\'\n  `Mips_Control_Signal_Register_Signal_WriteAddrSource_Rd   : wrAddr$ = rd;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:24: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteAddrSource_Rt\'\n  `Mips_Control_Signal_Register_Signal_WriteAddrSource_Rt   : wrAddr$ = rt;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:25: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteAddrSource_R31\'\n  `Mips_Control_Signal_Register_Signal_WriteAddrSource_R31  : wrAddr$ = 5\'d31;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrAddr.v:26: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteAddrSource_None\'\n  `Mips_Control_Signal_Register_Signal_WriteAddrSource_None : wrAddr$ = 5\'b0;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n'
module Mips_Datapath_Register_wrAddr
	( `Mips_Control_Signal_Register_Signal_WriteAddrSource_T(input) control
	, `Mips_Type_Word_T(input) instruction
	, `Mips_Type_RegAddr_T(output) wrAddr
	);

`Mips_Type_RegAddr_T (wire) rs;
`Mips_Type_RegAddr_T (wire) rt;
`Mips_Type_RegAddr_T (wire) rd;
assign rs = `Mips_Instruction_Format_RFormat_Rs(instruction);
assign rd = `Mips_Instruction_Format_RFormat_Rd(instruction);
assign rt = `Mips_Instruction_Format_RFormat_Rt(instruction);

`Mips_Type_RegAddr_T (reg) wrAddr$;
always @(*)
	case(control)
		`Mips_Control_Signal_Register_Signal_WriteAddrSource_Rd   : wrAddr$ = rd;
		`Mips_Control_Signal_Register_Signal_WriteAddrSource_Rt   : wrAddr$ = rt;
		`Mips_Control_Signal_Register_Signal_WriteAddrSource_R31  : wrAddr$ = 5'd31;
		`Mips_Control_Signal_Register_Signal_WriteAddrSource_None : wrAddr$ = 5'b0;
		default                                                   : wrAddr$ = 5'b0;
	endcase
assign wrAddr = wrAddr$;

endmodule
module Mips_Datapath_Register_wrAddr
	( `Mips_Control_Signal_Register_Signal_WriteAddrSource_T(input) control
	, `Mips_Type_Word_T(input) instruction
	, `Mips_Type_RegAddr_T(output) wrAddr
	);


`Mips_Type_RegAddr_T (wire) rs;
`Mips_Type_RegAddr_T (wire) rt;
`Mips_Type_RegAddr_T (wire) rd;
assign rs = `Mips_Instruction_Format_RFormat_Rs(instruction);
assign rd = `Mips_Instruction_Format_RFormat_Rd(instruction);
assign rt = `Mips_Instruction_Format_RFormat_Rt(instruction);

`Mips_Type_RegAddr_T (reg) wrAddr$;
always @(*)
	case(control)
		`Mips_Control_Signal_Register_Signal_WriteAddrSource_Rd   : wrAddr$ = rd;
		`Mips_Control_Signal_Register_Signal_WriteAddrSource_Rt   : wrAddr$ = rt;
		`Mips_Control_Signal_Register_Signal_WriteAddrSource_R31  : wrAddr$ = 5'd31;
		`Mips_Control_Signal_Register_Signal_WriteAddrSource_None : wrAddr$ = 5'b0;
		default                                                   : wrAddr$ = 5'b0;
	endcase
assign wrAddr = wrAddr$;

endmodule