data/full_repos/permissive/187199324/stannel/Alu.v
1: b'%Error: data/full_repos/permissive/187199324/stannel/Alu.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:2: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:81: Define or directive not defined: \'`OP_ALU_ADD\'\n    wUpdateLogicFlags = func != `OP_ALU_ADD && func != `OP_ALU_SUB;\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:81: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n    wUpdateLogicFlags = func != `OP_ALU_ADD && func != `OP_ALU_SUB;\n                                            ^~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:81: Define or directive not defined: \'`OP_ALU_SUB\'\n    wUpdateLogicFlags = func != `OP_ALU_ADD && func != `OP_ALU_SUB;\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:83: Define or directive not defined: \'`OP_ALU_ADD\'\n      `OP_ALU_ADD:\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:83: syntax error, unexpected \':\', expecting endcase\n      `OP_ALU_ADD:\n                 ^\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:85: Define or directive not defined: \'`OP_ALU_SUB\'\n      `OP_ALU_SUB: begin\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:89: Define or directive not defined: \'`OP_ALU_COMPARE\'\n      `OP_ALU_COMPARE: begin\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:89: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      `OP_ALU_COMPARE: begin\n                       ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:93: Define or directive not defined: \'`OP_ALU_NOT\'\n      `OP_ALU_NOT:\n      ^~~~~~~~~~~\n%Warning-ENDLABEL: data/full_repos/permissive/187199324/stannel/Alu.v:94: End label \'internalAluOut\' does not match begin label \'\'\n        internalAluOut = ~aluB;\n        ^~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:94: syntax error, unexpected \'=\'\n        internalAluOut = ~aluB;\n                       ^\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:95: Define or directive not defined: \'`OP_ALU_OR\'\n      `OP_ALU_OR:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:97: Define or directive not defined: \'`OP_ALU_AND\'\n      `OP_ALU_AND:\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:99: Define or directive not defined: \'`OP_ALU_TEST\'\n      `OP_ALU_TEST:\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:101: Define or directive not defined: \'`OP_ALU_XOR\'\n      `OP_ALU_XOR:\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:109: Define or directive not defined: \'`OP_CONDITION_ZERO_EQUAL_UPPER_BITS\'\n      `OP_CONDITION_ZERO_EQUAL_UPPER_BITS:\n      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:111: Define or directive not defined: \'`OP_CONDITION_NEGATIVE_UPPER_BITS\'\n      `OP_CONDITION_NEGATIVE_UPPER_BITS:\n      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:113: Define or directive not defined: \'`OP_CONDITION_UNSIGNED_GREATER_UPPER_BITS\'\n      `OP_CONDITION_UNSIGNED_GREATER_UPPER_BITS:\n      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:115: Define or directive not defined: \'`OP_CONDITION_UNSIGNED_GREATER_OR_EQUAL_UPPER_BITS\'\n      `OP_CONDITION_UNSIGNED_GREATER_OR_EQUAL_UPPER_BITS:\n      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:117: Define or directive not defined: \'`OP_CONDITION_SIGNED_GREATER_UPPER_BITS\'\n      `OP_CONDITION_SIGNED_GREATER_UPPER_BITS:\n      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:119: Define or directive not defined: \'`OP_CONDITION_SIGNED_GREATER_OR_EQUAL_UPPER_BITS\'\n      `OP_CONDITION_SIGNED_GREATER_OR_EQUAL_UPPER_BITS:\n      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:121: Define or directive not defined: \'`OP_CONDITION_OVERFLOW_UPPER_BITS\'\n      `OP_CONDITION_OVERFLOW_UPPER_BITS:\n      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Alu.v:123: Define or directive not defined: \'`OP_CONDITION_NEVER_UPPER_BITS\'\n      `OP_CONDITION_NEVER_UPPER_BITS:\n      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 24 error(s), 1 warning(s)\n'
module Alu #(parameter dataBits = 8) (
    input wire clk,
    input wire reset,
    input wire [dataBits-1:0] aluA,
    input wire [dataBits-1:0] aluB,
    input wire [3:0] func,
    input wire [3:0] condition,
    input wire updateFlags,
    input wire loadFlagsFromSavedState,
    input wire [3:0] savedFlags,
    output wire [dataBits-1:0] aluOut,
    output reg conditionHolds,
    output wire [3:0] exportedAluFlags
  );

  reg carryBit;

  wire wZeroFlag = &(~internalAluOut);
  wire wSignFlag = internalAluOut[dataBits-1];
  wire wCarryFlag = carryBit;





  wire wOverflowFlag = additionStyleOverflow ?
    (aluA[dataBits-1] == aluB[dataBits-1] && aluA[dataBits-1] != internalAluOut[dataBits-1]) :
    (aluA[dataBits-1] != aluB[dataBits-1] && aluB[dataBits-1] == internalAluOut[dataBits-1]);

  assign exportedAluFlags = { zeroFlag, signFlag, carryFlag, overflowFlag };

  reg zeroFlag;
  reg signFlag;
  reg carryFlag;
  reg overflowFlag;
  always @(posedge clk) begin
    if (!reset)
      begin
        zeroFlag     <= 0;
        signFlag     <= 0;
        carryFlag    <= 0;
        overflowFlag <= 0;
      end
    else if (updateFlags)
      begin
        if (wUpdateLogicFlags)
          begin
            zeroFlag     <= wZeroFlag;
            signFlag     <= wSignFlag;
          end
        carryFlag    <= wCarryFlag;
        overflowFlag <= wOverflowFlag;
      end
    else if (loadFlagsFromSavedState)
      begin
        zeroFlag     <= savedFlags[3];
        signFlag     <= savedFlags[2];
        carryFlag    <= savedFlags[1];
        overflowFlag <= savedFlags[0];
      end
  end

  reg additionStyleOverflow;
  reg c;
  reg wUpdateLogicFlags;

  wire shouldNegateConditionResult = condition[0];


  reg [dataBits-1:0] internalAluOut;
  always @(*)
  begin
    additionStyleOverflow = 1;
    carryBit = 0;
    wUpdateLogicFlags = func != `OP_ALU_ADD && func != `OP_ALU_SUB;
    case (func)
      `OP_ALU_ADD:
        {carryBit, internalAluOut} = {1'b0,aluA} + {1'b0,aluB};
      `OP_ALU_SUB: begin
        {carryBit, internalAluOut} = {1'b0,aluA} - {1'b0,aluB};
        additionStyleOverflow = 0;
      end
      `OP_ALU_COMPARE: begin
        {carryBit, internalAluOut} = {1'b0,aluA} - {1'b0,aluB};
        additionStyleOverflow = 0;
      end
      `OP_ALU_NOT:
        internalAluOut = ~aluB;
      `OP_ALU_OR:
        internalAluOut = aluA | aluB;
      `OP_ALU_AND:
        internalAluOut = aluA & aluB;
      `OP_ALU_TEST:
        internalAluOut = aluA & aluB;
      `OP_ALU_XOR:
        internalAluOut = aluA ^ aluB;
      default:
        internalAluOut = 0;
    endcase


    case (condition[3:1])
      `OP_CONDITION_ZERO_EQUAL_UPPER_BITS:
        c = zeroFlag;
      `OP_CONDITION_NEGATIVE_UPPER_BITS:
        c = signFlag;
      `OP_CONDITION_UNSIGNED_GREATER_UPPER_BITS:
        c = ~carryFlag & ~zeroFlag;
      `OP_CONDITION_UNSIGNED_GREATER_OR_EQUAL_UPPER_BITS:
        c = ~carryFlag;
      `OP_CONDITION_SIGNED_GREATER_UPPER_BITS:
        c = ~(signFlag ^ overflowFlag) & ~zeroFlag;
      `OP_CONDITION_SIGNED_GREATER_OR_EQUAL_UPPER_BITS:
        c = ~(signFlag ^ overflowFlag);
      `OP_CONDITION_OVERFLOW_UPPER_BITS:
        c = overflowFlag;
      `OP_CONDITION_NEVER_UPPER_BITS:
        c = 0;
    endcase

    conditionHolds = c ^ shouldNegateConditionResult;
  end

  assign aluOut = internalAluOut;

endmodule
module Alu #(parameter dataBits = 8) (
    input wire clk,
    input wire reset,
    input wire [dataBits-1:0] aluA,
    input wire [dataBits-1:0] aluB,
    input wire [3:0] func,
    input wire [3:0] condition,
    input wire updateFlags,
    input wire loadFlagsFromSavedState,
    input wire [3:0] savedFlags,
    output wire [dataBits-1:0] aluOut,
    output reg conditionHolds,
    output wire [3:0] exportedAluFlags
  );


  reg carryBit;

  wire wZeroFlag = &(~internalAluOut);
  wire wSignFlag = internalAluOut[dataBits-1];
  wire wCarryFlag = carryBit;





  wire wOverflowFlag = additionStyleOverflow ?
    (aluA[dataBits-1] == aluB[dataBits-1] && aluA[dataBits-1] != internalAluOut[dataBits-1]) :
    (aluA[dataBits-1] != aluB[dataBits-1] && aluB[dataBits-1] == internalAluOut[dataBits-1]);

  assign exportedAluFlags = { zeroFlag, signFlag, carryFlag, overflowFlag };

  reg zeroFlag;
  reg signFlag;
  reg carryFlag;
  reg overflowFlag;
  always @(posedge clk) begin
    if (!reset)
      begin
        zeroFlag     <= 0;
        signFlag     <= 0;
        carryFlag    <= 0;
        overflowFlag <= 0;
      end
    else if (updateFlags)
      begin
        if (wUpdateLogicFlags)
          begin
            zeroFlag     <= wZeroFlag;
            signFlag     <= wSignFlag;
          end
        carryFlag    <= wCarryFlag;
        overflowFlag <= wOverflowFlag;
      end
    else if (loadFlagsFromSavedState)
      begin
        zeroFlag     <= savedFlags[3];
        signFlag     <= savedFlags[2];
        carryFlag    <= savedFlags[1];
        overflowFlag <= savedFlags[0];
      end
  end

  reg additionStyleOverflow;
  reg c;
  reg wUpdateLogicFlags;

  wire shouldNegateConditionResult = condition[0];


  reg [dataBits-1:0] internalAluOut;
  always @(*)
  begin
    additionStyleOverflow = 1;
    carryBit = 0;
    wUpdateLogicFlags = func != `OP_ALU_ADD && func != `OP_ALU_SUB;
    case (func)
      `OP_ALU_ADD:
        {carryBit, internalAluOut} = {1'b0,aluA} + {1'b0,aluB};
      `OP_ALU_SUB: begin
        {carryBit, internalAluOut} = {1'b0,aluA} - {1'b0,aluB};
        additionStyleOverflow = 0;
      end
      `OP_ALU_COMPARE: begin
        {carryBit, internalAluOut} = {1'b0,aluA} - {1'b0,aluB};
        additionStyleOverflow = 0;
      end
      `OP_ALU_NOT:
        internalAluOut = ~aluB;
      `OP_ALU_OR:
        internalAluOut = aluA | aluB;
      `OP_ALU_AND:
        internalAluOut = aluA & aluB;
      `OP_ALU_TEST:
        internalAluOut = aluA & aluB;
      `OP_ALU_XOR:
        internalAluOut = aluA ^ aluB;
      default:
        internalAluOut = 0;
    endcase


    case (condition[3:1])
      `OP_CONDITION_ZERO_EQUAL_UPPER_BITS:
        c = zeroFlag;
      `OP_CONDITION_NEGATIVE_UPPER_BITS:
        c = signFlag;
      `OP_CONDITION_UNSIGNED_GREATER_UPPER_BITS:
        c = ~carryFlag & ~zeroFlag;
      `OP_CONDITION_UNSIGNED_GREATER_OR_EQUAL_UPPER_BITS:
        c = ~carryFlag;
      `OP_CONDITION_SIGNED_GREATER_UPPER_BITS:
        c = ~(signFlag ^ overflowFlag) & ~zeroFlag;
      `OP_CONDITION_SIGNED_GREATER_OR_EQUAL_UPPER_BITS:
        c = ~(signFlag ^ overflowFlag);
      `OP_CONDITION_OVERFLOW_UPPER_BITS:
        c = overflowFlag;
      `OP_CONDITION_NEVER_UPPER_BITS:
        c = 0;
    endcase

    conditionHolds = c ^ shouldNegateConditionResult;
  end

  assign aluOut = internalAluOut;

endmodule