data/full_repos/permissive/141596082/helper/blink/system.v
data/verilator_xmls/958a93e7-fb60-4994-8c02-85b5c95a2cd8.xml
module system 
(
  input  clk_50,
  input  resetn,


  output  debug_led
);


reg[25:0] count;

always @(posedge clk_50) begin
    count <= count + 1;
end

assign debug_led = count[20];

endmodule
module system 
(
  input  clk_50,
  input  resetn,


  output  debug_led
);



reg[25:0] count;

always @(posedge clk_50) begin
    count <= count + 1;
end

assign debug_led = count[20];

endmodule