data/full_repos/permissive/166008742/src/tb_wb_spi.v
 line:118: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_wb_spi.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/166008742/src/tb_wb_spi.v:118: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_wb_spi.v:125: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_wb_spi.v:130: Unsupported: Ignoring delay on this delayed statement.\n                #13;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_wb_spi.v:132: Unsupported: Ignoring delay on this delayed statement.\n                #13;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_wb_spi.v:135: Unsupported: Ignoring delay on this delayed statement.\n            #25;\n            ^\n%Error: data/full_repos/permissive/166008742/src/tb_wb_spi.v:139: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/166008742/src/tb_wb_spi.v:146: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/166008742/src/tb_wb_spi.v:153: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/166008742/src/tb_wb_spi.v:161: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/166008742/src/tb_wb_spi.v:167: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_wb_spi.v:172: Unsupported: Ignoring delay on this delayed statement.\n                #13;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_wb_spi.v:174: Unsupported: Ignoring delay on this delayed statement.\n                #13;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_wb_spi.v:177: Unsupported: Ignoring delay on this delayed statement.\n            #25;\n            ^\n%Error: data/full_repos/permissive/166008742/src/tb_wb_spi.v:181: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/166008742/src/tb_wb_spi.v:188: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_wb_spi.v:194: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: Exiting due to 9 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_wb_spi();
    parameter ADDR_WIDTH = 16;
    parameter DATA_WIDTH = 32;

    reg reset;
    reg clk;


    reg [ADDR_WIDTH-1:0] wbs_address;
    reg [DATA_WIDTH-1:0] wbs_writedata;
    reg wbs_strobe;
    reg wbs_cycle;
    reg wbs_write;


    wire wbs_ack;
    wire [DATA_WIDTH-1:0] wbs_readdata;


    reg  mosi;
    reg  ss;
    reg  sclk;
    wire miso;
    
    wire spi_done;



    wb_spi #(ADDR_WIDTH, DATA_WIDTH) dut
    (
        .reset(reset),
        .clk(clk),


        .wbs_address(wbs_address),
        .wbs_writedata(wbs_writedata),
        .wbs_readdata(wbs_readdata),
        .wbs_strobe(wbs_strobe),
        .wbs_cycle(wbs_cycle),
        .wbs_write(wbs_write),
        .wbs_ack(wbs_ack),


        .mosi(mosi),
        .ss(ss), 
        .sclk(sclk),
        .miso(miso),

        .spi_done(spi_done)
    );


    always begin
        #3;
        clk <= ~clk;
    end



    initial begin
            clk <= 0;
            reset <= 1;
            wbs_address <= 0;
            wbs_writedata <= 0;
            wbs_strobe <= 0;
            wbs_cycle <= 0;
            wbs_write <= 0;

            mosi <= 0;
            ss <= 1;
            sclk <= 1;

        repeat (100) @(posedge clk);
            reset <= 0;


        repeat (2) begin


            @(posedge clk);
            ss <= 0;
            repeat (8) begin
                mosi <= $random() % 2;
                sclk <= 0;
                #13;
                sclk <= 1;
                #13;
            end
            ss <= 1;
            #25;



            @(posedge clk);
            wbs_address <= 0;
            wbs_writedata <= 0;
            wbs_write <= 0;
            wbs_strobe <= 1;
            wbs_cycle <= 1;

            @(posedge clk);
            wbs_strobe <= 0;
            wbs_cycle <= 0;
        end

        repeat (4) begin

            @(posedge clk);
            wbs_address <= 0;
            wbs_writedata <= $random() % 256;
            wbs_write <= 1;

            wbs_strobe <= 1;
            wbs_cycle <= 1;

            @(posedge clk);
            wbs_strobe <= 0;
            wbs_cycle <= 0;



            @(posedge clk);
            ss <= 0;
            repeat (8) begin
                mosi <= $random() % 2;
                sclk <= 0;
                #13;
                sclk <= 1;
                #13;
            end
            ss <= 1;
            #25;



            @(posedge clk);
            wbs_address <= 0;
            wbs_writedata <= 0;
            wbs_write <= 0;
            wbs_strobe <= 1;
            wbs_cycle <= 1;

            @(posedge clk);
            wbs_strobe <= 0;
            wbs_cycle <= 0;
        end


        #100;
    end

endmodule
module tb_wb_spi();

    parameter ADDR_WIDTH = 16;
    parameter DATA_WIDTH = 32;

    reg reset;
    reg clk;


    reg [ADDR_WIDTH-1:0] wbs_address;
    reg [DATA_WIDTH-1:0] wbs_writedata;
    reg wbs_strobe;
    reg wbs_cycle;
    reg wbs_write;


    wire wbs_ack;
    wire [DATA_WIDTH-1:0] wbs_readdata;


    reg  mosi;
    reg  ss;
    reg  sclk;
    wire miso;
    
    wire spi_done;



    wb_spi #(ADDR_WIDTH, DATA_WIDTH) dut
    (
        .reset(reset),
        .clk(clk),


        .wbs_address(wbs_address),
        .wbs_writedata(wbs_writedata),
        .wbs_readdata(wbs_readdata),
        .wbs_strobe(wbs_strobe),
        .wbs_cycle(wbs_cycle),
        .wbs_write(wbs_write),
        .wbs_ack(wbs_ack),


        .mosi(mosi),
        .ss(ss), 
        .sclk(sclk),
        .miso(miso),

        .spi_done(spi_done)
    );


    always begin
        #3;
        clk <= ~clk;
    end



    initial begin
            clk <= 0;
            reset <= 1;
            wbs_address <= 0;
            wbs_writedata <= 0;
            wbs_strobe <= 0;
            wbs_cycle <= 0;
            wbs_write <= 0;

            mosi <= 0;
            ss <= 1;
            sclk <= 1;

        repeat (100) @(posedge clk);
            reset <= 0;


        repeat (2) begin


            @(posedge clk);
            ss <= 0;
            repeat (8) begin
                mosi <= $random() % 2;
                sclk <= 0;
                #13;
                sclk <= 1;
                #13;
            end
            ss <= 1;
            #25;



            @(posedge clk);
            wbs_address <= 0;
            wbs_writedata <= 0;
            wbs_write <= 0;
            wbs_strobe <= 1;
            wbs_cycle <= 1;

            @(posedge clk);
            wbs_strobe <= 0;
            wbs_cycle <= 0;
        end

        repeat (4) begin

            @(posedge clk);
            wbs_address <= 0;
            wbs_writedata <= $random() % 256;
            wbs_write <= 1;

            wbs_strobe <= 1;
            wbs_cycle <= 1;

            @(posedge clk);
            wbs_strobe <= 0;
            wbs_cycle <= 0;



            @(posedge clk);
            ss <= 0;
            repeat (8) begin
                mosi <= $random() % 2;
                sclk <= 0;
                #13;
                sclk <= 1;
                #13;
            end
            ss <= 1;
            #25;



            @(posedge clk);
            wbs_address <= 0;
            wbs_writedata <= 0;
            wbs_write <= 0;
            wbs_strobe <= 1;
            wbs_cycle <= 1;

            @(posedge clk);
            wbs_strobe <= 0;
            wbs_cycle <= 0;
        end


        #100;
    end

endmodule