data/full_repos/permissive/136684942/src/IF_ID_Reg.v
data/verilator_xmls/1d45ccb4-d43f-4df6-8225-d10c165951ce.xml
module IF_ID_Reg(d1,d2,en,r,clk,q1,q2
    );
	input en;
	input r;
	input clk;
	input [31:0] d1,d2;
	output [31:0] q1,q2;
	reg [31:0] q1,q2;
	always @ (posedge clk)
	if ( r )
		begin
			q1 <= 0;
			q2 <= 0;
		end
	else if (en)
		begin
			q1 <= d1;
			q2 <= d2;
		end
	else 
		begin
			q1 <= q1;
			q2 <= q2;
		end
endmodule
module IF_ID_Reg(d1,d2,en,r,clk,q1,q2
    );

	input en;
	input r;
	input clk;
	input [31:0] d1,d2;
	output [31:0] q1,q2;
	reg [31:0] q1,q2;
	always @ (posedge clk)
	if ( r )
		begin
			q1 <= 0;
			q2 <= 0;
		end
	else if (en)
		begin
			q1 <= d1;
			q2 <= d2;
		end
	else 
		begin
			q1 <= q1;
			q2 <= q2;
		end
endmodule