data/full_repos/permissive/201196900/Verilog_32BitPriorityEncoder/Verilog/PriorityEncoderWithLadnerFischer.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/201196900/Verilog_32BitPriorityEncoder/Verilog/PriorityEncoderWithLadnerFischer.v:78: Cell has missing pin: \'A32N\'\nAND_A_NOT_GATE  AND_A_NOT_GATE(.A1N(orOut16_0_Q15), .B1(orOut16_0_Q16), .A2N(orOut16_0_Q14), .B2(orOut16_0_Q15), .A3N(orOut16_0_Q13), .B3(orOut16_0_Q14), .A4N(orOut16_0_Q12), .B4(orOut16_0_Q13),\n                ^~~~~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module AND_A_NOT_GATE(input A1N, input B1, input A2N, input B2, input A3N, input B3, input A4N, input B4,
                   input A5N, input B5, input A6N, input B6, input A7N, input B7, input A8N, input B8,
                   input A9N, input B9, input A10N, input B10,input A11N, input B11, input A12N, input B12,
                   input A13N, input B13, input A14N, input B14,input A15N, input B15, input A16N, input B16,
                   input A17N, input B17, input A18N, input B18, input A19N, input B19, input A20N, input B20,
                   input A21N, input B21, input A22N, input B22, input A23N, input B23, input A24N, input B24,
                   input A25N, input B25, input A26N, input B26,input A27N, input B27, input A28N, input B28,
                   input A29N, input B29, input A30N, input B30,input A31N, input B31, input A32N, input B32,
                   output [31:0] Q);
assign Q[0]=~A1N&B1;
assign Q[1]=~A2N&B2;
assign Q[2]=~A3N&B3;
assign Q[3]=~A4N&B4;
assign Q[4]=~A5N&B5;
assign Q[5]=~A6N&B6;
assign Q[6]=~A7N&B7;
assign Q[7]=~A8N&B8;
assign Q[8]=~A9N&B9;
assign Q[9]=~A10N&B10;
assign Q[10]=~A11N&B11;
assign Q[11]=~A12N&B12;
assign Q[12]=~A13N&B13;
assign Q[13]=~A14N&B14;
assign Q[14]=~A15N&B15;
assign Q[15]=~A16N&B16;
assign Q[16]=~A17N&B17;
assign Q[17]=~A18N&B18;
assign Q[18]=~A19N&B19;
assign Q[19]=~A20N&B20;
assign Q[20]=~A21N&B21;
assign Q[21]=~A22N&B22;
assign Q[22]=~A23N&B23;
assign Q[23]=~A24N&B24;
assign Q[24]=~A25N&B25;
assign Q[25]=~A26N&B26;
assign Q[26]=~A27N&B27;
assign Q[27]=~A28N&B28;
assign Q[28]=~A29N&B29;
assign Q[29]=~A30N&B30;
assign Q[30]=~A31N&B31;
assign Q[31]=~A32N&B32;
endmodule
module AND_A_NOT_GATE(input A1N, input B1, input A2N, input B2, input A3N, input B3, input A4N, input B4,
                   input A5N, input B5, input A6N, input B6, input A7N, input B7, input A8N, input B8,
                   input A9N, input B9, input A10N, input B10,input A11N, input B11, input A12N, input B12,
                   input A13N, input B13, input A14N, input B14,input A15N, input B15, input A16N, input B16,
                   input A17N, input B17, input A18N, input B18, input A19N, input B19, input A20N, input B20,
                   input A21N, input B21, input A22N, input B22, input A23N, input B23, input A24N, input B24,
                   input A25N, input B25, input A26N, input B26,input A27N, input B27, input A28N, input B28,
                   input A29N, input B29, input A30N, input B30,input A31N, input B31, input A32N, input B32,
                   output [31:0] Q);

assign Q[0]=~A1N&B1;
assign Q[1]=~A2N&B2;
assign Q[2]=~A3N&B3;
assign Q[3]=~A4N&B4;
assign Q[4]=~A5N&B5;
assign Q[5]=~A6N&B6;
assign Q[6]=~A7N&B7;
assign Q[7]=~A8N&B8;
assign Q[8]=~A9N&B9;
assign Q[9]=~A10N&B10;
assign Q[10]=~A11N&B11;
assign Q[11]=~A12N&B12;
assign Q[12]=~A13N&B13;
assign Q[13]=~A14N&B14;
assign Q[14]=~A15N&B15;
assign Q[15]=~A16N&B16;
assign Q[16]=~A17N&B17;
assign Q[17]=~A18N&B18;
assign Q[18]=~A19N&B19;
assign Q[19]=~A20N&B20;
assign Q[20]=~A21N&B21;
assign Q[21]=~A22N&B22;
assign Q[22]=~A23N&B23;
assign Q[23]=~A24N&B24;
assign Q[24]=~A25N&B25;
assign Q[25]=~A26N&B26;
assign Q[26]=~A27N&B27;
assign Q[27]=~A28N&B28;
assign Q[28]=~A29N&B29;
assign Q[29]=~A30N&B30;
assign Q[30]=~A31N&B31;
assign Q[31]=~A32N&B32;
endmodule