data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/test_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/test_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/test_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\nalways #500 clk = ~clk;    \n       ^\n%Error: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/test_tb.v:31: Cannot find file containing module: \'Test\'\n Test uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/Test\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/Test.v\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/Test.sv\n             Test\n             Test.v\n             Test.sv\n             obj_dir/Test\n             obj_dir/Test.v\n             obj_dir/Test.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_tb;


	reg clk;


	Test uut (
		.clk(clk)
	);

	initial begin

		clk = 0;


		#100;
        


	end
always #500 clk = ~clk;    
endmodule
module test_tb;



	reg clk;


	Test uut (
		.clk(clk)
	);

	initial begin

		clk = 0;


		#100;
        


	end
always #500 clk = ~clk;    
endmodule