data/full_repos/permissive/208636171/fpga/top_tb.v
 line:108: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #BREAKTIME\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #BAUDRATE rx <= char[0];    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #BAUDRATE rx <= char[1];    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #BAUDRATE rx <= char[2];    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #BAUDRATE rx <= char[3];    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #BAUDRATE rx <= char[4];    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #BAUDRATE rx <= char[5];    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #BAUDRATE rx <= char[6];    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #BAUDRATE rx <= char[7];    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #BAUDRATE rx <= 1;          \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #BAUDRATE rx <= 1;          \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n  # 0.03125 clk <= ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n  # 0.0208 clk_48mhz <= ~clk_48mhz;\n  ^\n%Error: data/full_repos/permissive/208636171/fpga/top_tb.v:107: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile(`VCD_OUTPUT"");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/208636171/fpga/top_tb.v:107: Define or directive not defined: \'`VCD_OUTPUT\'\n  $dumpfile(`VCD_OUTPUT"");\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/208636171/fpga/top_tb.v:108: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, top_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #BAUDRATE    send_char(8\'h00);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n       #WAIT        send_char(i);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #1000  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #BAUDRATE    send_char(8\'h00);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h01);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h02);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h03);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h04);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h05);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h06);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h07);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h08);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h09);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h0a);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h0b);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h0c);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h0d);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h0e);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #WAIT        send_char(8\'h0f);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/208636171/fpga/top_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #(WAIT * 4) $display("END of the simulation");\n  ^\n%Error: Exiting due to 3 error(s), 33 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb();



localparam BAUDRATE = 4;


localparam  BREAKTIME = 360;


localparam SERIAL_PACK = (BAUDRATE * 10);


localparam WAIT = (BAUDRATE * 4);


localparam DMX_PACKET_LEN = 12;





task send_break;
  begin
    rx <= 0;
    #BREAKTIME
    rx <= 1;
  end
endtask




  task send_char;
    input [7:0] char;
  begin
    rx <= 0;
    #BAUDRATE rx <= char[0];
    #BAUDRATE rx <= char[1];
    #BAUDRATE rx <= char[2];
    #BAUDRATE rx <= char[3];
    #BAUDRATE rx <= char[4];
    #BAUDRATE rx <= char[5];
    #BAUDRATE rx <= char[6];
    #BAUDRATE rx <= char[7];
    #BAUDRATE rx <= 1;
    #BAUDRATE rx <= 1;
  end
  endtask


reg clk = 0;


reg rx = 1;


wire led;

reg clk_48mhz = 0;


top #(.BAUDRATE(BAUDRATE))
  dut(
    .clk(clk),
    .rx(rx),
    .LED(led),
    .USBP(USBP),
    .USBN(USBN),
    .USBPU(USBPU),
    .clk_48mhz(clk_48mhz)
  );



always
  # 0.03125 clk <= ~clk;


always
  # 0.0208 clk_48mhz <= ~clk_48mhz;

reg[10:0] i;

initial begin


  $dumpfile(`"`VCD_OUTPUT`");
  $dumpvars(0, top_tb);




  #BAUDRATE    send_char(8'h00);
  for (i = 0; i < DMX_PACKET_LEN; i = i+1) begin
   	  	#WAIT        send_char(i);
 	end
  #1000
  send_break();
  #BAUDRATE    send_char(8'h00);
  #WAIT        send_char(8'h01);
  #WAIT        send_char(8'h02);
  #WAIT        send_char(8'h03);
  #WAIT        send_char(8'h04);
  #WAIT        send_char(8'h05);
  #WAIT        send_char(8'h06);
  #WAIT        send_char(8'h07);
  #WAIT        send_char(8'h08);
  #WAIT        send_char(8'h09);
  #WAIT        send_char(8'h0a);
  #WAIT        send_char(8'h0b);
  #WAIT        send_char(8'h0c);
  #WAIT        send_char(8'h0d);
  #WAIT        send_char(8'h0e);
  #WAIT        send_char(8'h0f);
  send_break();

  #(WAIT * 4) $display("END of the simulation");
  $finish;
end

endmodule
module top_tb();




localparam BAUDRATE = 4;


localparam  BREAKTIME = 360;


localparam SERIAL_PACK = (BAUDRATE * 10);


localparam WAIT = (BAUDRATE * 4);


localparam DMX_PACKET_LEN = 12;





task send_break;
  begin
    rx <= 0;
    #BREAKTIME
    rx <= 1;
  end
endtask




  task send_char;
    input [7:0] char;
  begin
    rx <= 0;
    #BAUDRATE rx <= char[0];
    #BAUDRATE rx <= char[1];
    #BAUDRATE rx <= char[2];
    #BAUDRATE rx <= char[3];
    #BAUDRATE rx <= char[4];
    #BAUDRATE rx <= char[5];
    #BAUDRATE rx <= char[6];
    #BAUDRATE rx <= char[7];
    #BAUDRATE rx <= 1;
    #BAUDRATE rx <= 1;
  end
  endtask


reg clk = 0;


reg rx = 1;


wire led;

reg clk_48mhz = 0;


top #(.BAUDRATE(BAUDRATE))
  dut(
    .clk(clk),
    .rx(rx),
    .LED(led),
    .USBP(USBP),
    .USBN(USBN),
    .USBPU(USBPU),
    .clk_48mhz(clk_48mhz)
  );



always
  # 0.03125 clk <= ~clk;


always
  # 0.0208 clk_48mhz <= ~clk_48mhz;

reg[10:0] i;

initial begin


  $dumpfile(`"`VCD_OUTPUT`");
  $dumpvars(0, top_tb);




  #BAUDRATE    send_char(8'h00);
  for (i = 0; i < DMX_PACKET_LEN; i = i+1) begin
   	  	#WAIT        send_char(i);
 	end
  #1000
  send_break();
  #BAUDRATE    send_char(8'h00);
  #WAIT        send_char(8'h01);
  #WAIT        send_char(8'h02);
  #WAIT        send_char(8'h03);
  #WAIT        send_char(8'h04);
  #WAIT        send_char(8'h05);
  #WAIT        send_char(8'h06);
  #WAIT        send_char(8'h07);
  #WAIT        send_char(8'h08);
  #WAIT        send_char(8'h09);
  #WAIT        send_char(8'h0a);
  #WAIT        send_char(8'h0b);
  #WAIT        send_char(8'h0c);
  #WAIT        send_char(8'h0d);
  #WAIT        send_char(8'h0e);
  #WAIT        send_char(8'h0f);
  send_break();

  #(WAIT * 4) $display("END of the simulation");
  $finish;
end

endmodule