data/full_repos/permissive/143278/ivltests/assign_add.v
 line:14: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/assign_add.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("%b + %b = %b", A, B, sum);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [8:0] A, B;
   wire [9:0] sum = A + B;

   initial begin
      A = 51;
      B = 39;
      #1 $display("%b + %b = %b", A, B, sum);
      if (sum !== 90) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   reg [8:0] A, B;
   wire [9:0] sum = A + B;

   initial begin
      A = 51;
      B = 39;
      #1 $display("%b + %b = %b", A, B, sum);
      if (sum !== 90) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule