data/full_repos/permissive/143638862/rtl/memio/cache/cache.v
 line:8: before: ")"
1: b"%Error: data/full_repos/permissive/143638862/rtl/memio/cache/cache.v:8: syntax error, unexpected ')', expecting '['\n    )(  \n    ^\n%Error: data/full_repos/permissive/143638862/rtl/memio/cache/cache.v:38: syntax error, unexpected assign\n    assign index = fulladdress[23:24-INDEXWIDTH];\n    ^~~~~~\n%Error: data/full_repos/permissive/143638862/rtl/memio/cache/cache.v:44: syntax error, unexpected always_comb\n    always_comb\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/143638862/rtl/memio/cache/cache.v:56: syntax error, unexpected always_comb\n    always_comb\n    ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module cache
    #(
        parameter OFFSETWIDTH = 5,
        parameter INDEXWIDTH = 11,
    )(

        input store,
        input load,
        input [23:0] fulladdress,
        input [7:0] d_in,
        output [7:0] d_out,
        input clock,
        output new_dout,



        output [15:0] data_to_ram,
        input [15:0] data_from_ram,
        output readreq, writereq,
        output read, write,
        input readready, writeready
    );



    localparam LINESIZEBYTES = 2 ** OFFSETWIDTH;
    localparam TAGWIDTH = 24 - INDEXWIDTH - OFFSETWIDTH;
    localparam LINEWIDTH = 1 + TAGWIDTH + 8 * LINESIZEBYTES;
    localparam NUMLINES = 2 ** INDEXWIDTH;


    wire [INDEXWIDTH-1:0] index;
    wire [TAGWIDTH-1:0] tag;
    wire [OFFSETWIDTH-1:0] offset;
    assign index = fulladdress[23:24-INDEXWIDTH];
    assign tag = fulladdress[23-INDEXWIDTH:OFFSETWIDTH];
    assign offset = fulladdress[OFFSETWIDTH-1:0];


    reg [LINEWIDTH-1:0] memory [NUMLINES-1:0];
    always_comb
    begin
        if (load && hit)
        begin
            d_out = memory[index][8*(offset+1):8*offset];
        else
            d_out = 0;
        end
    end


    wire hit;
    always_comb
    begin
        if ((load || store) &&
            memory[index][LINEWIDTH-1] &&
            (memory[index][LINEWIDTH-2:LINEWIDTH-1-TAGWIDTH] == tag))
            hit = 1;
        else
            hit = 0;
        end
    end














endmodule
module cache
    #(
        parameter OFFSETWIDTH = 5,
        parameter INDEXWIDTH = 11,
    )(

        input store,
        input load,
        input [23:0] fulladdress,
        input [7:0] d_in,
        output [7:0] d_out,
        input clock,
        output new_dout,



        output [15:0] data_to_ram,
        input [15:0] data_from_ram,
        output readreq, writereq,
        output read, write,
        input readready, writeready
    );




    localparam LINESIZEBYTES = 2 ** OFFSETWIDTH;
    localparam TAGWIDTH = 24 - INDEXWIDTH - OFFSETWIDTH;
    localparam LINEWIDTH = 1 + TAGWIDTH + 8 * LINESIZEBYTES;
    localparam NUMLINES = 2 ** INDEXWIDTH;


    wire [INDEXWIDTH-1:0] index;
    wire [TAGWIDTH-1:0] tag;
    wire [OFFSETWIDTH-1:0] offset;
    assign index = fulladdress[23:24-INDEXWIDTH];
    assign tag = fulladdress[23-INDEXWIDTH:OFFSETWIDTH];
    assign offset = fulladdress[OFFSETWIDTH-1:0];


    reg [LINEWIDTH-1:0] memory [NUMLINES-1:0];
    always_comb
    begin
        if (load && hit)
        begin
            d_out = memory[index][8*(offset+1):8*offset];
        else
            d_out = 0;
        end
    end


    wire hit;
    always_comb
    begin
        if ((load || store) &&
            memory[index][LINEWIDTH-1] &&
            (memory[index][LINEWIDTH-2:LINEWIDTH-1-TAGWIDTH] == tag))
            hit = 1;
        else
            hit = 0;
        end
    end














endmodule