data/full_repos/permissive/136422019/src/ram512.v
data/verilator_xmls/0ea93fa3-1fb4-437a-867d-aa2dc12f6d65.xml
module ram512(
	output reg [31:0] data_out,
	input wire [31:0] data_in, 
	input wire [8:0] address,
	input wire read, write
	
);

reg [31:0] i;

(*ram_file = "ram512.mif"*) reg [31:0] ram [0:511];

initial begin
	data_out = 32'b00000000000000000000000000000000;
	




















































	
	ram[0] <= 32'b00001_0011_00000000000000000000110;
	ram[1] <= 32'b11111_0011_00000000000000000000000;
	ram[2] <= 32'b11101_0011_00000000000000000000000;
	ram[3] <= 32'b11110_0011_00000000000000000000000;
	ram[4] <= 32'b11100_000000000000000000000000000;


	ram[66] <= 57;
	ram[56] <= 34;
	
end
	
always@(read, write) begin
	if(read == 1)
		data_out <= ram[address];
	else if(write == 1) begin
		ram[address] <= data_in;
		data_out <= 32'b00000000000000000000000000000000;
	end
	else
		data_out <= 32'b00000000000000000000000000000000;
end

endmodule
module ram512(
	output reg [31:0] data_out,
	input wire [31:0] data_in, 
	input wire [8:0] address,
	input wire read, write
	
);


reg [31:0] i;

(*ram_file = "ram512.mif"*) reg [31:0] ram [0:511];

initial begin
	data_out = 32'b00000000000000000000000000000000;
	




















































	
	ram[0] <= 32'b00001_0011_00000000000000000000110;
	ram[1] <= 32'b11111_0011_00000000000000000000000;
	ram[2] <= 32'b11101_0011_00000000000000000000000;
	ram[3] <= 32'b11110_0011_00000000000000000000000;
	ram[4] <= 32'b11100_000000000000000000000000000;


	ram[66] <= 57;
	ram[56] <= 34;
	
end
	
always@(read, write) begin
	if(read == 1)
		data_out <= ram[address];
	else if(write == 1) begin
		ram[address] <= data_in;
		data_out <= 32'b00000000000000000000000000000000;
	end
	else
		data_out <= 32'b00000000000000000000000000000000;
end

endmodule