data/full_repos/permissive/127311496/src/v/Cache/ICache.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:93: Cannot find file containing module: 'ICacheTag'\n ICacheTag cacheTag(.clka(clk), .wea(tagWe), .addra(tagAddr), .dina(tagDin), .douta({_tag1, _tag0}),\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/ICacheTag\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/ICacheTag.v\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/ICacheTag.sv\n             ICacheTag\n             ICacheTag.v\n             ICacheTag.sv\n             obj_dir/ICacheTag\n             obj_dir/ICacheTag.v\n             obj_dir/ICacheTag.sv\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:95: Cannot find file containing module: 'CacheLRUBit'\n CacheLRUBit cacheLRU(.clk(clk), .req(req), .addr(addrIn[14:6]), .hit({hit1, hit0}), .flag(LRUBit));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:43: Cannot find file containing module: 'ICacheData'\n ICacheData way0Data(.addra(PCIn[14:2]), .clka(~clkCPU), .douta(douta0), .ena(1'b1),\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:45: Cannot find file containing module: 'ICacheData'\n ICacheData way1Data(.addra(PCIn[14:2]), .clka(~clkCPU), .douta(douta1), .ena(1'b1),\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:55: Cannot find file containing module: 'AsyncHandshake'\n AsyncHandshake #(.STB_FREQ(1000 / CLKDDR_PERIOD), .ACK_FREQ(1000 / CLKCPU_PERIOD))\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:59: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) replaceStbCross(.clki(clkCPU), .clko(clkDDR), .i(replaceStb_CPU), .o(replaceStb_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:60: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) replaceBlockCross[26:0](.clki(clkCPU), .clko(clkDDR), .i(replaceBlock_CPU), .o(replaceBlock_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module ICache #(
	parameter CLKCPU_PERIOD = 10,
	parameter CLKDDR_PERIOD = 5
) (
	input clkCPU, input clkDDR, input rstCPU, input rstDDR,

	input [31:0] PCIn, input req, output [31:0] instOut, output iStall,
	input [31:0] invalidateAddr, input invalidateReq,


	output [31:0] ws_addr, input [511:0] ws_din, output ws_cyc, output ws_stb, input ws_ack
);

	
	wire [31:0] douta0, douta1;
	wire [8:0] addrb;
	wire [511:0] dinb;
	wire [1:0] web;
	
	wire replaceStb_CPU, replaceStb_DDR, completeStb_CPU, completeStb_DDR;
	wire [26:0] replaceBlock_CPU, replaceBlock_DDR;
	
	ICacheData way0Data(.addra(PCIn[14:2]), .clka(~clkCPU), .douta(douta0), .ena(1'b1),
		.addrb(addrb), .clkb(clkDDR), .dinb(dinb), .enb(1'b1), .web(web[0]));
	ICacheData way1Data(.addra(PCIn[14:2]), .clka(~clkCPU), .douta(douta1), .ena(1'b1),
		.addrb(addrb), .clkb(clkDDR), .dinb(dinb), .enb(1'b1), .web(web[1]));
	
	ICacheFSM_CPU FSM0(.clk(clkCPU), .rst(rstCPU), .addrIn(PCIn), .req(req), .dataOut(instOut), .stall(iStall),
		.invalidateAddr(invalidateAddr), .invalidateReq(invalidateReq), .douta0(douta0), .douta1(douta1),
		.replaceStb(replaceStb_CPU), .replaceBlock(replaceBlock_CPU), .completeStb(completeStb_CPU));
	ICacheFSM_DDR FSM1(.clk(clkDDR), .rst(rstDDR), .addrb(addrb), .dinb(dinb), .web(web),
		.replaceStb(replaceStb_DDR), .replaceBlock(replaceBlock_DDR), .completeStb(completeStb_DDR),
		.ws_addr(ws_addr), .ws_din(ws_din), .ws_cyc(ws_cyc), .ws_stb(ws_stb), .ws_ack(ws_ack));
	
	AsyncHandshake #(.STB_FREQ(1000 / CLKDDR_PERIOD), .ACK_FREQ(1000 / CLKCPU_PERIOD))
		completeCross(.clkStb(clkDDR), .clkAck(clkCPU),
		.stbI(completeStb_DDR), .stbO(completeStb_CPU),
		.ackI(completeStb_CPU), .ackO());
	ClockDomainCross #(0, 1) replaceStbCross(.clki(clkCPU), .clko(clkDDR), .i(replaceStb_CPU), .o(replaceStb_DDR));
	ClockDomainCross #(0, 1) replaceBlockCross[26:0](.clki(clkCPU), .clko(clkDDR), .i(replaceBlock_CPU), .o(replaceBlock_DDR));
	
endmodule
module ICache #(
	parameter CLKCPU_PERIOD = 10,
	parameter CLKDDR_PERIOD = 5
) (
	input clkCPU, input clkDDR, input rstCPU, input rstDDR,

	input [31:0] PCIn, input req, output [31:0] instOut, output iStall,
	input [31:0] invalidateAddr, input invalidateReq,


	output [31:0] ws_addr, input [511:0] ws_din, output ws_cyc, output ws_stb, input ws_ack
);


	
	wire [31:0] douta0, douta1;
	wire [8:0] addrb;
	wire [511:0] dinb;
	wire [1:0] web;
	
	wire replaceStb_CPU, replaceStb_DDR, completeStb_CPU, completeStb_DDR;
	wire [26:0] replaceBlock_CPU, replaceBlock_DDR;
	
	ICacheData way0Data(.addra(PCIn[14:2]), .clka(~clkCPU), .douta(douta0), .ena(1'b1),
		.addrb(addrb), .clkb(clkDDR), .dinb(dinb), .enb(1'b1), .web(web[0]));
	ICacheData way1Data(.addra(PCIn[14:2]), .clka(~clkCPU), .douta(douta1), .ena(1'b1),
		.addrb(addrb), .clkb(clkDDR), .dinb(dinb), .enb(1'b1), .web(web[1]));
	
	ICacheFSM_CPU FSM0(.clk(clkCPU), .rst(rstCPU), .addrIn(PCIn), .req(req), .dataOut(instOut), .stall(iStall),
		.invalidateAddr(invalidateAddr), .invalidateReq(invalidateReq), .douta0(douta0), .douta1(douta1),
		.replaceStb(replaceStb_CPU), .replaceBlock(replaceBlock_CPU), .completeStb(completeStb_CPU));
	ICacheFSM_DDR FSM1(.clk(clkDDR), .rst(rstDDR), .addrb(addrb), .dinb(dinb), .web(web),
		.replaceStb(replaceStb_DDR), .replaceBlock(replaceBlock_DDR), .completeStb(completeStb_DDR),
		.ws_addr(ws_addr), .ws_din(ws_din), .ws_cyc(ws_cyc), .ws_stb(ws_stb), .ws_ack(ws_ack));
	
	AsyncHandshake #(.STB_FREQ(1000 / CLKDDR_PERIOD), .ACK_FREQ(1000 / CLKCPU_PERIOD))
		completeCross(.clkStb(clkDDR), .clkAck(clkCPU),
		.stbI(completeStb_DDR), .stbO(completeStb_CPU),
		.ackI(completeStb_CPU), .ackO());
	ClockDomainCross #(0, 1) replaceStbCross(.clki(clkCPU), .clko(clkDDR), .i(replaceStb_CPU), .o(replaceStb_DDR));
	ClockDomainCross #(0, 1) replaceBlockCross[26:0](.clki(clkCPU), .clko(clkDDR), .i(replaceBlock_CPU), .o(replaceBlock_DDR));
	
endmodule