data/full_repos/permissive/12739552/alu_testbench.v
 line:46: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/12739552/alu_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10 if ( (Q==expectQ) && (Carry==expectCarry) && (Zero==expectZero) && (Minus1==expectMinus1) )\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/12739552/alu_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #10 test_vector(5\'b01001,1\'b1,16\'h4444,16\'h2345,16\'h8967,1\'b0,1\'b0,1\'b0);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/12739552/alu_testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10 test_vector(5\'b01001,1\'b0,16\'hf00f,16\'hc7c8,16\'hb7d7,1\'b1,1\'b0,1\'b0);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/12739552/alu_testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #10 test_vector(5\'b01001,1\'b1,16\'h3cc3,16\'h7cc7,16\'h8ab9,1\'b0,1\'b0,1\'b0);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/12739552/alu_testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #10 test_vector(5\'b01001,1\'b0,16\'hff00,16\'h0100,16\'h0000,1\'b1,1\'b1,1\'b0);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/12739552/alu_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #10 test_vector(5\'b01001,1\'b1,16\'h0000,16\'h0000,16\'h0000,1\'b0,1\'b1,1\'b0);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/12739552/alu_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #10 test_vector(5\'b01001,1\'b0,16\'h7777,16\'h8888,16\'hffff,1\'b0,1\'b0,1\'b1);\n    ^\n%Error: data/full_repos/permissive/12739552/alu_testbench.v:21: Can\'t find definition of variable: \'testSwap\'\n                                                              : ... Suggested alternative: \'testOp\'\n        $display($time, "M=%b, S=%h, Cn=%b, A = %h, B = %h", testOp, testSwap, testA, testB);\n                                                                     ^~~~~~~~\n%Error: data/full_repos/permissive/12739552/alu_testbench.v:26: Can\'t find definition of variable: \'Minus1\'\n        #10 if ( (Q==expectQ) && (Carry==expectCarry) && (Zero==expectZero) && (Minus1==expectMinus1) )\n                                                                                ^~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_testbench ();

reg [15:0] A, B;
reg [4:0] Op;
reg Swap;
wire [15:0] Q;
wire Carry, Zero, Sign;

BitsliceALU DUT (A, B, Op, Q, Flags);

task test_vector;
    input [4:0] testOp;
    input [15:0] testA, testB;
    input [15:0] expectQ;
    input expectCarry, expectZero, expectMinus1;
    begin
        $display($time, "M=%b, S=%h, Cn=%b, A = %h, B = %h", testOp, testSwap, testA, testB);
        A = testA;
        B = testB;
        Op = testOp;
        Swap = testSwap;
        #10 if ( (Q==expectQ) && (Carry==expectCarry) && (Zero==expectZero) && (Minus1==expectMinus1) )
            $display($time, "                                      passed.");
        else
            begin
                if (Q != expectQ)
                    $display($time, "   ... FAILED with Q = %h", Q);
                if (Carry != expectCarry)
                    $display($time, "   ... FAILED with Carry = %h", Carry);
                if (Zero != expectZero)
                    $display($time, "   ... FAILED with Zero = %h", Zero);
                if (Minus1 != expectMinus1)
                    $display($time, "   ... FAILED with Minus1 = %h", Minus1);
            end
    end
endtask

initial
begin
    $display($time, " ##### Testing addition... #####");

    #10 test_vector(5'b01001,1'b1,16'h4444,16'h2345,16'h8967,1'b0,1'b0,1'b0);
    #10 test_vector(5'b01001,1'b0,16'hf00f,16'hc7c8,16'hb7d7,1'b1,1'b0,1'b0);
    #10 test_vector(5'b01001,1'b1,16'h3cc3,16'h7cc7,16'h8ab9,1'b0,1'b0,1'b0);
    #10 test_vector(5'b01001,1'b0,16'hff00,16'h0100,16'h0000,1'b1,1'b1,1'b0);
    #10 test_vector(5'b01001,1'b1,16'h0000,16'h0000,16'h0000,1'b0,1'b1,1'b0);
    #10 test_vector(5'b01001,1'b0,16'h7777,16'h8888,16'hffff,1'b0,1'b0,1'b1);
end

endmodule
module alu_testbench ();


reg [15:0] A, B;
reg [4:0] Op;
reg Swap;
wire [15:0] Q;
wire Carry, Zero, Sign;

BitsliceALU DUT (A, B, Op, Q, Flags);

task test_vector;
    input [4:0] testOp;
    input [15:0] testA, testB;
    input [15:0] expectQ;
    input expectCarry, expectZero, expectMinus1;
    begin
        $display($time, "M=%b, S=%h, Cn=%b, A = %h, B = %h", testOp, testSwap, testA, testB);
        A = testA;
        B = testB;
        Op = testOp;
        Swap = testSwap;
        #10 if ( (Q==expectQ) && (Carry==expectCarry) && (Zero==expectZero) && (Minus1==expectMinus1) )
            $display($time, "                                      passed.");
        else
            begin
                if (Q != expectQ)
                    $display($time, "   ... FAILED with Q = %h", Q);
                if (Carry != expectCarry)
                    $display($time, "   ... FAILED with Carry = %h", Carry);
                if (Zero != expectZero)
                    $display($time, "   ... FAILED with Zero = %h", Zero);
                if (Minus1 != expectMinus1)
                    $display($time, "   ... FAILED with Minus1 = %h", Minus1);
            end
    end
endtask

initial
begin
    $display($time, " ##### Testing addition... #####");

    #10 test_vector(5'b01001,1'b1,16'h4444,16'h2345,16'h8967,1'b0,1'b0,1'b0);
    #10 test_vector(5'b01001,1'b0,16'hf00f,16'hc7c8,16'hb7d7,1'b1,1'b0,1'b0);
    #10 test_vector(5'b01001,1'b1,16'h3cc3,16'h7cc7,16'h8ab9,1'b0,1'b0,1'b0);
    #10 test_vector(5'b01001,1'b0,16'hff00,16'h0100,16'h0000,1'b1,1'b1,1'b0);
    #10 test_vector(5'b01001,1'b1,16'h0000,16'h0000,16'h0000,1'b0,1'b1,1'b0);
    #10 test_vector(5'b01001,1'b0,16'h7777,16'h8888,16'hffff,1'b0,1'b0,1'b1);
end

endmodule