data/full_repos/permissive/123366832/fpga/keyboard_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123366832/fpga/keyboard_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123366832/fpga/keyboard_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n    always #12.5 clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/123366832/fpga/keyboard_tb.v:64: Cannot find file containing module: \'keyboard\'\n keyboard uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123366832/fpga,data/full_repos/permissive/123366832/keyboard\n             data/full_repos/permissive/123366832/fpga,data/full_repos/permissive/123366832/keyboard.v\n             data/full_repos/permissive/123366832/fpga,data/full_repos/permissive/123366832/keyboard.sv\n             keyboard\n             keyboard.v\n             keyboard.sv\n             obj_dir/keyboard\n             obj_dir/keyboard.v\n             obj_dir/keyboard.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module keyboard_tb;


	reg clk;
	reg rst_n;
	reg [5:0] KBD_col;


	wire [4:0] KBD_row;
	wire b_0;
	wire b_1;
	wire b_2;
	wire b_3;
	wire b_4;
	wire b_5;
	wire b_6;
	wire b_7;
	wire b_8;
	wire b_9;
	wire b_a;
	wire b_b;
	wire b_c;
	wire b_d;
	wire b_e;
	wire b_f;
	wire b_runhalt;
	wire b_reset;
	wire b_step;
	wire b_storeinc;
	wire b_irq;
	wire b_dec;
	wire b_load;
	wire b_toA;
	wire b_toSP;
	wire b_toX;
	wire b_toY;
	wire b_toPC;


	keyboard uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.KBD_row(KBD_row), 
		.KBD_col(KBD_col), 
		.b_0(b_0), 
		.b_1(b_1), 
		.b_2(b_2), 
		.b_3(b_3), 
		.b_4(b_4), 
		.b_5(b_5), 
		.b_6(b_6), 
		.b_7(b_7), 
		.b_8(b_8), 
		.b_9(b_9), 
		.b_a(b_a), 
		.b_b(b_b), 
		.b_c(b_c), 
		.b_d(b_d), 
		.b_e(b_e), 
		.b_f(b_f), 
		.b_runhalt(b_runhalt), 
		.b_reset(b_reset), 
		.b_step(b_step), 
		.b_storeinc(b_storeinc), 
		.b_irq(b_irq), 
		.b_dec(b_dec), 
		.b_load(b_load), 
		.b_toA(b_toA), 
		.b_toSP(b_toSP), 
		.b_toX(b_toX), 
		.b_toY(b_toY), 
		.b_toPC(b_toPC)
	);

	initial begin

		clk = 0;
		rst_n = 0;
		KBD_col = 6'b111111;


		#100;
        

        rst_n = 1;
        
	end
    always #12.5 clk = ~clk;
endmodule
module keyboard_tb;



	reg clk;
	reg rst_n;
	reg [5:0] KBD_col;


	wire [4:0] KBD_row;
	wire b_0;
	wire b_1;
	wire b_2;
	wire b_3;
	wire b_4;
	wire b_5;
	wire b_6;
	wire b_7;
	wire b_8;
	wire b_9;
	wire b_a;
	wire b_b;
	wire b_c;
	wire b_d;
	wire b_e;
	wire b_f;
	wire b_runhalt;
	wire b_reset;
	wire b_step;
	wire b_storeinc;
	wire b_irq;
	wire b_dec;
	wire b_load;
	wire b_toA;
	wire b_toSP;
	wire b_toX;
	wire b_toY;
	wire b_toPC;


	keyboard uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.KBD_row(KBD_row), 
		.KBD_col(KBD_col), 
		.b_0(b_0), 
		.b_1(b_1), 
		.b_2(b_2), 
		.b_3(b_3), 
		.b_4(b_4), 
		.b_5(b_5), 
		.b_6(b_6), 
		.b_7(b_7), 
		.b_8(b_8), 
		.b_9(b_9), 
		.b_a(b_a), 
		.b_b(b_b), 
		.b_c(b_c), 
		.b_d(b_d), 
		.b_e(b_e), 
		.b_f(b_f), 
		.b_runhalt(b_runhalt), 
		.b_reset(b_reset), 
		.b_step(b_step), 
		.b_storeinc(b_storeinc), 
		.b_irq(b_irq), 
		.b_dec(b_dec), 
		.b_load(b_load), 
		.b_toA(b_toA), 
		.b_toSP(b_toSP), 
		.b_toX(b_toX), 
		.b_toY(b_toY), 
		.b_toPC(b_toPC)
	);

	initial begin

		clk = 0;
		rst_n = 0;
		KBD_col = 6'b111111;


		#100;
        

        rst_n = 1;
        
	end
    always #12.5 clk = ~clk;
endmodule