data/full_repos/permissive/203650831/hd44780_timer.v
None: at end of input
1: b'%Error: data/full_repos/permissive/203650831/hd44780_timer.v:10: Cannot find include file: ./hd44780_build_config.inc\n`include "./hd44780_build_config.inc" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203650831,data/full_repos/permissive/203650831/./hd44780_build_config.inc\n             data/full_repos/permissive/203650831,data/full_repos/permissive/203650831/./hd44780_build_config.inc.v\n             data/full_repos/permissive/203650831,data/full_repos/permissive/203650831/./hd44780_build_config.inc.sv\n             ./hd44780_build_config.inc\n             ./hd44780_build_config.inc.v\n             ./hd44780_build_config.inc.sv\n             obj_dir/./hd44780_build_config.inc\n             obj_dir/./hd44780_build_config.inc.v\n             obj_dir/./hd44780_build_config.inc.sv\n%Error: data/full_repos/permissive/203650831/hd44780_timer.v:36: Define or directive not defined: \'`H4_SYSFREQ\'\nmodule hd44780_state_timer  #(parameter SYSFREQ = `H4_SYSFREQ, parameter STATE_TIMER_BITS = `H4_TIMER_BITS)\n                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer.v:36: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nmodule hd44780_state_timer  #(parameter SYSFREQ = `H4_SYSFREQ, parameter STATE_TIMER_BITS = `H4_TIMER_BITS)\n                                                             ^\n%Error: data/full_repos/permissive/203650831/hd44780_timer.v:36: Define or directive not defined: \'`H4_TIMER_BITS\'\nmodule hd44780_state_timer  #(parameter SYSFREQ = `H4_SYSFREQ, parameter STATE_TIMER_BITS = `H4_TIMER_BITS)\n                                                                                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer.v:36: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule hd44780_state_timer  #(parameter SYSFREQ = `H4_SYSFREQ, parameter STATE_TIMER_BITS = `H4_TIMER_BITS)\n                                                                                                          ^\n%Error: data/full_repos/permissive/203650831/hd44780_timer.v:39: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire CLK_I,\n    ^~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer.v:40: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [STATE_TIMER_BITS-1:0] DAT_I,  \n ^~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer.v:41: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire start_strobe,             \n    ^~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer.v:42: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire busy              \n    ^~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer.v:45: Define or directive not defined: \'`H4_TIMER_BITS\'\n    reg [`H4_TIMER_BITS-1:0] st_count = 0;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer.v:48: syntax error, unexpected always\n always @(posedge CLK_I) begin\n ^~~~~~\n%Error: Exiting due to 11 error(s)\n'
module hd44780_state_timer  #(parameter SYSFREQ = `H4_SYSFREQ, parameter STATE_TIMER_BITS = `H4_TIMER_BITS)
(
    input wire RST_I,
    input wire CLK_I,
	input wire [STATE_TIMER_BITS-1:0] DAT_I,
    input wire start_strobe,
    output wire busy
    );

    reg [`H4_TIMER_BITS-1:0] st_count = 0;
    reg busy_reg = 0;

	always @(posedge CLK_I) begin
		if(RST_I == 1) begin
			st_count <= 0;
			busy_reg <= 0;

		end else begin
            if(start_strobe) begin
                st_count <= DAT_I;
    			busy_reg <= 1;
            end else if(|st_count) begin
    			st_count <= st_count-1;
		    end else begin

                busy_reg <= 0;
	        end
        end
	end

    assign busy = busy_reg;

endmodule
module hd44780_state_timer  #(parameter SYSFREQ = `H4_SYSFREQ, parameter STATE_TIMER_BITS = `H4_TIMER_BITS)
(
    input wire RST_I,
    input wire CLK_I,
	input wire [STATE_TIMER_BITS-1:0] DAT_I,
    input wire start_strobe,
    output wire busy
    );


    reg [`H4_TIMER_BITS-1:0] st_count = 0;
    reg busy_reg = 0;

	always @(posedge CLK_I) begin
		if(RST_I == 1) begin
			st_count <= 0;
			busy_reg <= 0;

		end else begin
            if(start_strobe) begin
                st_count <= DAT_I;
    			busy_reg <= 1;
            end else if(|st_count) begin
    			st_count <= st_count-1;
		    end else begin

                busy_reg <= 0;
	        end
        end
	end

    assign busy = busy_reg;

endmodule