data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v:29: Signal definition not found, creating implicitly: \'switch_debounced\'\n                                                                                        : ... Suggested alternative: \'switch_debounced_d\'\n    switch_debounced_d <= switch_debounced;   \n                          ^~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v:46: Signal definition not found, creating implicitly: \'ten_ms\'\n      .sample_en(ten_ms),      \n                 ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v:56: Signal definition not found, creating implicitly: \'ten_us\'\n                                                                                        : ... Suggested alternative: \'ten_ms\'\n        .timer_pulse(ten_us));\n                     ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v:18: Operator EQ expects 25 bits on the RHS, but RHS\'s REPLICATE generates 24 bits.\n                                                                                     : ... In instance fpga_top\n       if (counter == ( {blink_cnt, 20\'h42400} )) begin    \n                   ^~\n%Error: Exiting due to 4 warning(s)\n'
module WF_timer (
       input  wire clk,
       input  wire enable,
       output reg  timer_pulse
   );

   parameter [9:0] COUNT = 499;
   parameter       EVERY_CLK = 1'b0;

    reg [9:0] counter;

    always @ (posedge clk)
        if (enable)
          begin
            if (counter == COUNT)
              begin
                timer_pulse <= 1'b1;
                counter     <= 'b0;
              end
           else
             begin
              counter     <= counter + 'b1;
              if (EVERY_CLK)
               timer_pulse <= 1'b0;
             end

          end
        else
            timer_pulse <= 1'b0;

   endmodule
module WF_timer (
       input  wire clk,
       input  wire enable,
       output reg  timer_pulse
   );


   parameter [9:0] COUNT = 499;
   parameter       EVERY_CLK = 1'b0;

    reg [9:0] counter;

    always @ (posedge clk)
        if (enable)
          begin
            if (counter == COUNT)
              begin
                timer_pulse <= 1'b1;
                counter     <= 'b0;
              end
           else
             begin
              counter     <= counter + 'b1;
              if (EVERY_CLK)
               timer_pulse <= 1'b0;
             end

          end
        else
            timer_pulse <= 1'b0;

   endmodule