data/full_repos/permissive/147265957/testbench/maccumulator_simu.v
 line:35: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #4 onesig = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #4 onesig = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #4 tensig = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #4 tensig = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #4 rst = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #4 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #4 tensig = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #4 tensig = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #4 tensig = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #4 tensig = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #4 rst = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #4 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #4 onesig = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #4 onesig = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #4 lock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #4 onesig = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #4 onesig = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #4 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:39: Unsupported: Ignoring delay on this delayed statement.\n            #2 cp = ~cp;\n            ^\n%Error: data/full_repos/permissive/147265957/testbench/maccumulator_simu.v:42: Cannot find file containing module: \'maccumulator\'\n    maccumulator ma(cp, lock, rst, onesig, tensig, moneyv);\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147265957/testbench,data/full_repos/permissive/147265957/maccumulator\n             data/full_repos/permissive/147265957/testbench,data/full_repos/permissive/147265957/maccumulator.v\n             data/full_repos/permissive/147265957/testbench,data/full_repos/permissive/147265957/maccumulator.sv\n             maccumulator\n             maccumulator.v\n             maccumulator.sv\n             obj_dir/maccumulator\n             obj_dir/maccumulator.v\n             obj_dir/maccumulator.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module maccumulator_simu(
);
    reg [31:0] counter;
    reg rst;
    reg lock;
    reg onesig;
    reg tensig;
    reg cp;
    wire [7:0] moneyv;
    initial begin
        cp = 0;
        rst = 0;
        onesig = 0;
        tensig = 0;
        lock = 0;
        #4 onesig = 1;
        #4 onesig = 0;
        #4 tensig = 1;
        #4 tensig = 0;
        #4 rst = 1;
        #4 rst = 0;
        #4 tensig = 1;
        #4 tensig = 0;
        #4 tensig = 1;
        #4 tensig = 0;
        #4 rst = 1;
        #4 rst = 0;
        #4 onesig = 1;
        #4 onesig = 0;
        #4 lock = 1;
        #4 onesig = 1;
        #4 onesig = 0;
        #4 $finish;
    end
    initial begin
        for(counter = 0 ; counter < 999; counter = counter + 1) begin
            #2 cp = ~cp;
        end
    end
    maccumulator ma(cp, lock, rst, onesig, tensig, moneyv);

endmodule
module maccumulator_simu(
);

    reg [31:0] counter;
    reg rst;
    reg lock;
    reg onesig;
    reg tensig;
    reg cp;
    wire [7:0] moneyv;
    initial begin
        cp = 0;
        rst = 0;
        onesig = 0;
        tensig = 0;
        lock = 0;
        #4 onesig = 1;
        #4 onesig = 0;
        #4 tensig = 1;
        #4 tensig = 0;
        #4 rst = 1;
        #4 rst = 0;
        #4 tensig = 1;
        #4 tensig = 0;
        #4 tensig = 1;
        #4 tensig = 0;
        #4 rst = 1;
        #4 rst = 0;
        #4 onesig = 1;
        #4 onesig = 0;
        #4 lock = 1;
        #4 onesig = 1;
        #4 onesig = 0;
        #4 $finish;
    end
    initial begin
        for(counter = 0 ; counter < 999; counter = counter + 1) begin
            #2 cp = ~cp;
        end
    end
    maccumulator ma(cp, lock, rst, onesig, tensig, moneyv);

endmodule