data/full_repos/permissive/193790231/lab02/lab02part02_circuitA.v
 line:15: before: "/"
data/verilator_xmls/54d7f138-eff6-4be9-bf77-adc2d8970adf.xml
module lab02part02_circuitA(
		input 	[2:0]num,
		output 	[2:0]out
);


	assign out[2] = (num[2] & num[1]);
	assign out[1] = (~num[1]);
	assign out[0] = (num[0]);

endmodule
module lab02part02_circuitA(
		input 	[2:0]num,
		output 	[2:0]out
);



	assign out[2] = (num[2] & num[1]);
	assign out[1] = (~num[1]);
	assign out[0] = (num[0]);

endmodule