data/full_repos/permissive/174369527/mem/rom_tb.v
 line:44: before: "$"
1: b'%Error: data/full_repos/permissive/174369527/mem/rom_tb.v:44: Unsupported or unknown PLI call: $monitor\n   #10 $monitor ("address = %h, data = %h, read_en = %b, ce = %b", address, data, read_en, ce);\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174369527/mem/rom_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n   #10 $monitor ("address = %h, data = %h, read_en = %b, ce = %b", address, data, read_en, ce);\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174369527/mem/rom_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n     #5 address = i;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/mem/rom_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n     #5 read_en = 0;\n     ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rom_tb;
 reg [7:0] address;
 reg read_en, ce;
 wire [7:0] data;
 integer i;
 
 initial begin
   address = 0;
   read_en = 0;
   ce      = 0;
   #10 $monitor ("address = %h, data = %h, read_en = %b, ce = %b", address, data, read_en, ce);
   for (i = 0; i <256; i = i +1 )begin
     #5 address = i;
     read_en = 1;
     ce = 1;
     #5 read_en = 0;
     ce = 0;
     address = 0;
   end
 end
 
rom U(
address ,
data    ,
read_en ,
ce
);

endmodule
module rom_tb;

 reg [7:0] address;
 reg read_en, ce;
 wire [7:0] data;
 integer i;
 
 initial begin
   address = 0;
   read_en = 0;
   ce      = 0;
   #10 $monitor ("address = %h, data = %h, read_en = %b, ce = %b", address, data, read_en, ce);
   for (i = 0; i <256; i = i +1 )begin
     #5 address = i;
     read_en = 1;
     ce = 1;
     #5 read_en = 0;
     ce = 0;
     address = 0;
   end
 end
 
rom U(
address ,
data    ,
read_en ,
ce
);

endmodule