data/full_repos/permissive/111901713/testbench/test_endian.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_endian.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_endian;

	reg [31:0] i;

	initial begin
		i = 32'h12345678;
		#100;
        $display("%h %h %h %h", i[31:24], i[23:16], i[15:8], i[7:0]);

        $finish;
	end
      
endmodule
module test_endian;


	reg [31:0] i;

	initial begin
		i = 32'h12345678;
		#100;
        $display("%h %h %h %h", i[31:24], i[23:16], i[15:8], i[7:0]);

        $finish;
	end
      
endmodule