data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v
 line:151: before: "pos"
1: b'%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:22: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:41: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:60: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:89: Duplicate declaration of module: \'top_module\'\nmodule top_module ( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:113: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:138: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:165: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Error: Exiting due to 7 warning(s)\n'
module top_module (
    input [3:0] in,
    output reg [1:0] pos  );
    always @(*)begin
        case(in)
         4'h0: pos = 2'd0;
         4'h1: pos = 2'd0;
         4'h2: pos = 2'd1;
         4'h3: pos = 2'd0;
         4'h4: pos = 2'd2;
         4'h5: pos = 2'd0;
         4'h6: pos = 2'd1;
         4'h7: pos = 2'd0;
         4'h8: pos = 2'd3;
         4'h9: pos = 2'd0;
         4'ha: pos = 2'd1;
         4'hb: pos = 2'd0;
         4'hc: pos = 2'd2;
         4'hd: pos = 2'd0;
         4'he: pos = 2'd1;
         4'hf: pos = 2'd0;
        endcase
    end
endmodule
module top_module (
    input [3:0] in,
    output reg [1:0] pos  );

    always @(*)begin
        case(in)
         4'h0: pos = 2'd0;
         4'h1: pos = 2'd0;
         4'h2: pos = 2'd1;
         4'h3: pos = 2'd0;
         4'h4: pos = 2'd2;
         4'h5: pos = 2'd0;
         4'h6: pos = 2'd1;
         4'h7: pos = 2'd0;
         4'h8: pos = 2'd3;
         4'h9: pos = 2'd0;
         4'ha: pos = 2'd1;
         4'hb: pos = 2'd0;
         4'hc: pos = 2'd2;
         4'hd: pos = 2'd0;
         4'he: pos = 2'd1;
         4'hf: pos = 2'd0;
        endcase
    end
endmodule