data/full_repos/permissive/134057391/2019_ricoh2A03/code/rtl/tri_channel.v
data/verilator_xmls/50a49e50-e4a3-4280-b6bc-c988f29f5e77.xml
module tri_channel(
    input clk,
    input reset,
    input [7:0] r1,
    input [7:0] r3,
    input [7:0] r4,
    output [10:0] p,
    output tc,
    output [3:0] y
    );

   reg [10:0] prog_timer = {11{1'b0}};
   reg [4:0] step_gen = {5{1'b0}};

   wire [10:0] N = {r4[2:0], r3};
   wire terminal_count;



   always @(posedge clk)
       if (reset)
          prog_timer <= 11'b0;
       else if (terminal_count)
          prog_timer <= N;
       else
          prog_timer <= prog_timer - 1'b1;

   assign p = prog_timer;
     




   assign terminal_count = ~| prog_timer;
   assign tc = terminal_count;



   always @(posedge clk)
      if (reset)
         step_gen <= 5'b0;
      else if (terminal_count)
         step_gen <= step_gen + 1;






   assign y[0] = ! ( step_gen[0] ^ step_gen[4] );
   assign y[1] = ! ( step_gen[1] ^ step_gen[4] );
   assign y[2] = ! ( step_gen[2] ^ step_gen[4] );
   assign y[3] = ! ( step_gen[3] ^ step_gen[4] );
   
endmodule
module tri_channel(
    input clk,
    input reset,
    input [7:0] r1,
    input [7:0] r3,
    input [7:0] r4,
    output [10:0] p,
    output tc,
    output [3:0] y
    );


   reg [10:0] prog_timer = {11{1'b0}};
   reg [4:0] step_gen = {5{1'b0}};

   wire [10:0] N = {r4[2:0], r3};
   wire terminal_count;



   always @(posedge clk)
       if (reset)
          prog_timer <= 11'b0;
       else if (terminal_count)
          prog_timer <= N;
       else
          prog_timer <= prog_timer - 1'b1;

   assign p = prog_timer;
     




   assign terminal_count = ~| prog_timer;
   assign tc = terminal_count;



   always @(posedge clk)
      if (reset)
         step_gen <= 5'b0;
      else if (terminal_count)
         step_gen <= step_gen + 1;






   assign y[0] = ! ( step_gen[0] ^ step_gen[4] );
   assign y[1] = ! ( step_gen[1] ^ step_gen[4] );
   assign y[2] = ! ( step_gen[2] ^ step_gen[4] );
   assign y[3] = ! ( step_gen[3] ^ step_gen[4] );
   
endmodule