data/full_repos/permissive/201488448/2_circuits/1_combinational/02_gnd.v
data/verilator_xmls/0ad4428f-f43d-40ab-9aeb-d69d409e3533.xml
module top_module (
    output out);

    assign	out = 1'b0;
    
endmodule
module top_module (
    output out);


    assign	out = 1'b0;
    
endmodule