data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new/RegFile.v
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data/verilator_xmls/6362cc44-8e6a-40cc-9340-75f1ae0aa123.xml
module RegFile(
    input clk,

    input rf_wen,

    input[4:0] rf_addr_r1,
    input[4:0] rf_addr_r2,

    input[4:0] rf_addr_w,
    input[31:0] rf_data_w,

    output[31:0] rf_data_r1,
    output[31:0] rf_data_r2
    );
    
    reg[31:0] file[31:0];
    
    integer i;
    initial begin
        for(i=0; i<32; i=i+1) file[i] = 32'b0;
    end

    
    assign rf_data_r1 = file[rf_addr_r1];
    assign rf_data_r2 = file[rf_addr_r2];

    
    always@(negedge clk) begin
        if(rf_wen) begin
            file[rf_addr_w] <= rf_data_w;
        end
    end
    
endmodule
module RegFile(
    input clk,

    input rf_wen,

    input[4:0] rf_addr_r1,
    input[4:0] rf_addr_r2,

    input[4:0] rf_addr_w,
    input[31:0] rf_data_w,

    output[31:0] rf_data_r1,
    output[31:0] rf_data_r2
    );

    
    reg[31:0] file[31:0];
    
    integer i;
    initial begin
        for(i=0; i<32; i=i+1) file[i] = 32'b0;
    end

    
    assign rf_data_r1 = file[rf_addr_r1];
    assign rf_data_r2 = file[rf_addr_r2];

    
    always@(negedge clk) begin
        if(rf_wen) begin
            file[rf_addr_w] <= rf_data_w;
        end
    end
    
endmodule