data/full_repos/permissive/200314387/verilog/74377/test.v
 line:33: before: "if"
1: b'%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:3: Cannot find include file: hct74377.v\n`include "hct74377.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/74377,data/full_repos/permissive/200314387/hct74377.v\n             data/full_repos/permissive/200314387/verilog/74377,data/full_repos/permissive/200314387/hct74377.v.v\n             data/full_repos/permissive/200314387/verilog/74377,data/full_repos/permissive/200314387/hct74377.v.sv\n             hct74377.v\n             hct74377.v.v\n             hct74377.v.sv\n             obj_dir/hct74377.v\n             obj_dir/hct74377.v.v\n             obj_dir/hct74377.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:4: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:19: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:20: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,  register);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:35: Define or directive not defined: \'`Equals\'\n        `Equals(Q , 8\'bxxxxxxxx);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:35: syntax error, unexpected \',\'\n        `Equals(Q , 8\'bxxxxxxxx);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74377/test.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #1 \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:40: Define or directive not defined: \'`Equals\'\n        `Equals(Q , 8\'bzxxzzxxz);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:40: syntax error, unexpected \',\'\n        `Equals(Q , 8\'bzxxzzxxz);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74377/test.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #tPD \n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:47: Define or directive not defined: \'`Equals\'\n        `Equals(Q , 8\'bzxxzzxxz);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:47: syntax error, unexpected \',\'\n        `Equals(Q , 8\'bzxxzzxxz);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74377/test.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #tPD \n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:51: Define or directive not defined: \'`Equals\'\n        `Equals(Q , \'1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:51: syntax error, unexpected \',\'\n        `Equals(Q , \'1);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74377/test.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #tPD \n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:59: Define or directive not defined: \'`Equals\'\n        `Equals(Q , \'1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:59: syntax error, unexpected \',\'\n        `Equals(Q , \'1);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74377/test.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #tPD \n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:63: Define or directive not defined: \'`Equals\'\n        `Equals(Q , \'1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74377/test.v:63: syntax error, unexpected \',\'\n        `Equals(Q , \'1);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74377/test.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #tPD \n        ^\n%Error: Exiting due to 16 error(s), 6 warning(s)\n'
module icarus_tb();
    
	logic [7:0] D, Q;
	logic CP, _EN;
    
	hct74377 #(.LOG(1)) register(
        .D, .Q,
        .CP, ._EN
	);
    
    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0,  register);
        
`ifndef verilator        
        $monitor ("%9t ", $time, "TEST        CP=%b _EN=%b D=%8b Q=%8b", CP, _EN, D, Q);
`endif
    end

    initial begin
        parameter tPD = 14+1;

        D='0; 
        CP='x;
        _EN='x;

        $display("intial state x");
        `Equals(Q , 8'bxxxxxxxx);
        #1 

        $display("does not transitions to 0 (verilog register initial value) because I've hard coded to 'xz pattern to spot uninitialisd usage");
        #tPD 
        `Equals(Q , 8'bzxxzzxxz);

        $display("CP with enable loads");
        D='1;
        CP=0;
        _EN=0;
        #tPD 
        `Equals(Q , 8'bzxxzzxxz);

        CP=1;
        #tPD 
        `Equals(Q , '1);

        $display("CP with disable does not load");

        D='0;
        CP=0;
        _EN=1;
        #tPD 
        `Equals(Q , '1);

        CP=1;
        #tPD 
        `Equals(Q , '1);

    end
endmodule
module icarus_tb();

    
	logic [7:0] D, Q;
	logic CP, _EN;
    
	hct74377 #(.LOG(1)) register(
        .D, .Q,
        .CP, ._EN
	);
    
    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0,  register);
        
`ifndef verilator        
        $monitor ("%9t ", $time, "TEST        CP=%b _EN=%b D=%8b Q=%8b", CP, _EN, D, Q);
`endif
    end

    initial begin
        parameter tPD = 14+1;

        D='0; 
        CP='x;
        _EN='x;

        $display("intial state x");
        `Equals(Q , 8'bxxxxxxxx);
        #1 

        $display("does not transitions to 0 (verilog register initial value) because I've hard coded to 'xz pattern to spot uninitialisd usage");
        #tPD 
        `Equals(Q , 8'bzxxzzxxz);

        $display("CP with enable loads");
        D='1;
        CP=0;
        _EN=0;
        #tPD 
        `Equals(Q , 8'bzxxzzxxz);

        CP=1;
        #tPD 
        `Equals(Q , '1);

        $display("CP with disable does not load");

        D='0;
        CP=0;
        _EN=1;
        #tPD 
        `Equals(Q , '1);

        CP=1;
        #tPD 
        `Equals(Q , '1);

    end
endmodule