data/full_repos/permissive/193909872/Implementation/nexys2/reset_circuit.v
data/verilator_xmls/37827eb7-6777-462d-a47a-295223b0eda5.xml
module reset_circuit(
	
	input clk,
	input rst,
	output rst_asserted
	
	);

	reg [4:0] rst_q;

	always@(posedge clk) begin
		rst_q[0] 		<= rst;
		rst_q[1] 		<= rst_q[0];
		rst_q[2] 		<= rst_q[1];
		rst_q[3] 		<= rst_q[2];
		rst_q[4] 		<= rst_q[3];
	end

	assign rst_asserted = (rst_q[4] && (!rst_q[3]) && (!rst_q[2]) && (!rst_q[1]) && (!rst_q[0]));

endmodule
module reset_circuit(
	
	input clk,
	input rst,
	output rst_asserted
	
	);


	reg [4:0] rst_q;

	always@(posedge clk) begin
		rst_q[0] 		<= rst;
		rst_q[1] 		<= rst_q[0];
		rst_q[2] 		<= rst_q[1];
		rst_q[3] 		<= rst_q[2];
		rst_q[4] 		<= rst_q[3];
	end

	assign rst_asserted = (rst_q[4] && (!rst_q[3]) && (!rst_q[2]) && (!rst_q[1]) && (!rst_q[0]));

endmodule