data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic/int_cordic_tanh_sigm_rtl.v
'utf-8' codec can't decode byte 0xd5 in position 3: invalid continuation byte
1: b'%Error: data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic/int_cordic_tanh_sigm_rtl.v:41: Cannot find file containing module: \'int_cordic_exp_rtl\'\n int_cordic_exp_rtl cordic_exp_mdl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(src_x_exp), .rho(rho_exp));\n ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic,data/full_repos/permissive/130996185/int_cordic_exp_rtl\n             data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic,data/full_repos/permissive/130996185/int_cordic_exp_rtl.v\n             data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic,data/full_repos/permissive/130996185/int_cordic_exp_rtl.sv\n             int_cordic_exp_rtl\n             int_cordic_exp_rtl.v\n             int_cordic_exp_rtl.sv\n             obj_dir/int_cordic_exp_rtl\n             obj_dir/int_cordic_exp_rtl.v\n             obj_dir/int_cordic_exp_rtl.sv\n%Warning-WIDTH: data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic/int_cordic_tanh_sigm_rtl.v:45: Operator COND expects 49 bits on the Conditional True, but Conditional True\'s REPLICATE generates 48 bits.\n                                                                                                                                 : ... In instance int_cordic_tanh_sigm_rtl\n         (algorithm_reg[ITERATION+4]==2\'B01)? {DATA_UNIT, {FRAC_WIDTH{1\'B0}}} : \n                                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic/int_cordic_tanh_sigm_rtl.v:44: Operator ASSIGNW expects 34 bits on the Assign RHS, but Assign RHS\'s COND generates 49 bits.\n                                                                                                                                 : ... In instance int_cordic_tanh_sigm_rtl\n wire [33:0]  numer_div = (algorithm_reg[ITERATION+4]==2\'B10)? {DATA_UNIT, 1\'B0, {FRAC_WIDTH{1\'B0}}} : \n                        ^\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_cnn_inst_set_arch/00_user_logic/int_cordic_tanh_sigm_rtl.v:47: Cannot find file containing module: \'alt_lpm_div_ip\'\n alt_lpm_div_ip  alt_lpm_div_ip_inst(.clock(sys_clk),.denom(rho_exp+DATA_UNIT),.numer(numer_div),.quotient(rho_div));\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module int_cordic_tanh_sigm_rtl
#(parameter	DATA_WIDTH = 32,
  parameter	FRAC_WIDTH = 16,
  parameter	EPSILON = 16,
  parameter ITERATION = 8,
  parameter ROM_LATENCY = 2,
  parameter	DATA_UNIT = {{(DATA_WIDTH-FRAC_WIDTH-1){1'B0}}, 1'B1, {FRAC_WIDTH{1'B0}}},
  parameter	DATA_ZERO = {DATA_WIDTH{1'B0}}
)
(
	input	wire	sys_clk, sys_rst_n,
	input	wire	[DATA_WIDTH-1:0]	src_x,
	
	output	wire	[DATA_WIDTH-1:0]	rho,
	input	wire	[1:0]	algorithm
);

	reg		[1:0]	algorithm_reg	[0:ITERATION+4];
	integer			n;
	always @(posedge sys_clk)
		if(!sys_rst_n)
		begin
			for(n=0; n<ITERATION+5; n=n+1)
				algorithm_reg[n] <= 2'B00;
		end
		else
		begin
			for(n=ITERATION+4; n>=1; n=n-1)
				algorithm_reg[n] <= algorithm_reg[n-1];
			
			algorithm_reg[0] <= algorithm;
		end
			

	wire	[31:0]		rho_exp;
	wire	[31:0]		src_x_exp = (algorithm==2'B10)? {src_x[DATA_WIDTH-2:0], 1'B0} : 
									(algorithm==2'B01)? {src_x[DATA_WIDTH-1:0]} : 
									0;
	int_cordic_exp_rtl	cordic_exp_mdl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(src_x_exp), .rho(rho_exp));

	wire	[33:0]		rho_div;
	wire	[33:0]		numer_div = (algorithm_reg[ITERATION+4]==2'B10)? {DATA_UNIT, 1'B0, {FRAC_WIDTH{1'B0}}} : 
									(algorithm_reg[ITERATION+4]==2'B01)? {DATA_UNIT, {FRAC_WIDTH{1'B0}}} : 
									0;
	alt_lpm_div_ip		alt_lpm_div_ip_inst(.clock(sys_clk),.denom(rho_exp+DATA_UNIT),.numer(numer_div),.quotient(rho_div));

	assign				rho = DATA_UNIT-rho_div[DATA_WIDTH-1:0];
	
endmodule
module int_cordic_tanh_sigm_rtl
#(parameter	DATA_WIDTH = 32,
  parameter	FRAC_WIDTH = 16,
  parameter	EPSILON = 16,
  parameter ITERATION = 8,
  parameter ROM_LATENCY = 2,
  parameter	DATA_UNIT = {{(DATA_WIDTH-FRAC_WIDTH-1){1'B0}}, 1'B1, {FRAC_WIDTH{1'B0}}},
  parameter	DATA_ZERO = {DATA_WIDTH{1'B0}}
)
(
	input	wire	sys_clk, sys_rst_n,
	input	wire	[DATA_WIDTH-1:0]	src_x,
	
	output	wire	[DATA_WIDTH-1:0]	rho,
	input	wire	[1:0]	algorithm
);


	reg		[1:0]	algorithm_reg	[0:ITERATION+4];
	integer			n;
	always @(posedge sys_clk)
		if(!sys_rst_n)
		begin
			for(n=0; n<ITERATION+5; n=n+1)
				algorithm_reg[n] <= 2'B00;
		end
		else
		begin
			for(n=ITERATION+4; n>=1; n=n-1)
				algorithm_reg[n] <= algorithm_reg[n-1];
			
			algorithm_reg[0] <= algorithm;
		end
			

	wire	[31:0]		rho_exp;
	wire	[31:0]		src_x_exp = (algorithm==2'B10)? {src_x[DATA_WIDTH-2:0], 1'B0} : 
									(algorithm==2'B01)? {src_x[DATA_WIDTH-1:0]} : 
									0;
	int_cordic_exp_rtl	cordic_exp_mdl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(src_x_exp), .rho(rho_exp));

	wire	[33:0]		rho_div;
	wire	[33:0]		numer_div = (algorithm_reg[ITERATION+4]==2'B10)? {DATA_UNIT, 1'B0, {FRAC_WIDTH{1'B0}}} : 
									(algorithm_reg[ITERATION+4]==2'B01)? {DATA_UNIT, {FRAC_WIDTH{1'B0}}} : 
									0;
	alt_lpm_div_ip		alt_lpm_div_ip_inst(.clock(sys_clk),.denom(rho_exp+DATA_UNIT),.numer(numer_div),.quotient(rho_div));

	assign				rho = DATA_UNIT-rho_div[DATA_WIDTH-1:0];
	
endmodule