data/full_repos/permissive/149769583/top.v
 line:31: before: "="
1: b'%Error: data/full_repos/permissive/149769583/top.v:47: Cannot find file containing module: \'clkdiv2\'\n    clkdiv2 clkdiv (\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/clkdiv2\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/clkdiv2.v\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/clkdiv2.sv\n             clkdiv2\n             clkdiv2.v\n             clkdiv2.sv\n             obj_dir/clkdiv2\n             obj_dir/clkdiv2.v\n             obj_dir/clkdiv2.sv\n%Error: data/full_repos/permissive/149769583/top.v:55: Cannot find file containing module: \'sram\'\n    sram #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(RAM1_DATA_WIDTH), .DEPTH(DEPTH)) sram_inst1 (\n    ^~~~\n%Error: data/full_repos/permissive/149769583/top.v:64: Cannot find file containing module: \'sram\'\n    sram #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(RAM2_DATA_WIDTH), .DEPTH(DEPTH)) sram_inst2 (\n    ^~~~\n%Error: data/full_repos/permissive/149769583/top.v:73: Cannot find file containing module: \'mac1\'\n    mac1 mac_inst (\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/149769583/top.v:99: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                             : ... In instance top\n        if (cnt ==1\'b0)\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/149769583/top.v:117: Operator LTE expects 16 bits on the RHS, but RHS\'s SEL generates 10 bits.\n                                                              : ... In instance top\n  if(mac_acc_wire <= ram1wire[RAM1_DATA_WIDTH-25:RAM1_DATA_WIDTH-34]) begin\n                  ^~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module top #( parameter RAM1_DATA_WIDTH = 34, RAM2_DATA_WIDTH = 18, ADDR_WIDTH = 8, DEPTH = 32) (in_attr,out_class,clk,we1,rst_in,in_addr,ram1_data_in,ram2_data_in);



    input wire [RAM1_DATA_WIDTH-1:0] in_attr;
    input wire  clk, we1, rst_in;
    input wire [ADDR_WIDTH-1:0] in_addr;
    input wire [RAM1_DATA_WIDTH-1:0] ram1_data_in;
    input wire [RAM2_DATA_WIDTH-1:0] ram2_data_in;
    output reg [7:0] out_class;

    reg [4:0] c1 = 0;

    reg [19:0] mac_acc;

    wire ram1clk;
    wire ram2clk;









    reg [8:0] ram2_9bit_reg;
    reg [ADDR_WIDTH-1:0] next_addr;
    reg [2:0] cnt = 3'b000;
    reg start1,start2=1'b0;
    wire start3;
    wire [9:0] ram1_10bit_wire;
    wire [8:0] ram2_9bit_wire;
    wire [7:0] next_addr_wire;
    wire [RAM1_DATA_WIDTH-1:0] ram1wire;
    wire [RAM2_DATA_WIDTH-1:0] ram2wire;
    wire [15:0] mac_acc_wire;


	reg [7:0] out_class_reg;





    clkdiv2 clkdiv (
		.clk(clk),
        .invclk2(ram2clk),
        .clk2(ram1clk)
        );



    sram #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(RAM1_DATA_WIDTH), .DEPTH(DEPTH)) sram_inst1 (
        .clk(ram1clk),
        .addr_a(in_addr),
        .addr_b(next_addr_wire),
        .data_a(ram1_data_in),
        .we_a(we1),
        .q_b(ram1wire)
        );

    sram #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(RAM2_DATA_WIDTH), .DEPTH(DEPTH)) sram_inst2 (
        .clk(ram2clk),
        .addr_a(in_addr),
        .addr_b(next_addr_wire),
        .data_a(ram2_data_in),
        .we_a(we1),
        .q_b(ram2wire)
        );

    mac1 mac_inst (
        .inputattr(in_attr),
        .inputcoeff(ram1wire),
        .clk(clk),
        .rst_in(rst_in),
        .acc(mac_acc_wire)
        );














    always @(in_attr) begin
            start1 = 1;

     end
    always @(posedge ram2clk) begin
        if (cnt ==1'b0)
           start2 =  1;
        else
            start2 =  0;
     end



    assign start3 = start1 & start2;
    assign next_addr_wire = next_addr;

	always @(posedge ram2clk) begin
	    cnt = cnt + 1;
	    if (start3 == 1)
	    begin
	       next_addr = 0;
	       end
	    else begin
		if(mac_acc_wire <= ram1wire[RAM1_DATA_WIDTH-25:RAM1_DATA_WIDTH-34]) begin
			ram2_9bit_reg = ram2wire[RAM2_DATA_WIDTH-1:RAM2_DATA_WIDTH-9];
			if(ram2_9bit_reg[8] == 1'b1) begin
				out_class = ram2_9bit_reg[7:0];
				next_addr = 8'b00000000;
			end else begin
				next_addr = ram2_9bit_reg[7:0];
				out_class = 8'b00000000;
			end
		end else begin
			ram2_9bit_reg = ram2wire[RAM2_DATA_WIDTH-10:0];
			if(ram2_9bit_reg[RAM2_DATA_WIDTH-10] == 1'b1) begin
				out_class = ram2_9bit_reg[7:0];
				next_addr = 8'b00000000;
			end else begin
			    c1 = c1 +1;
				next_addr = ram2_9bit_reg[7:0];
				out_class = 8'b00000000;
			end
		end
		end
	end



endmodule
module top #( parameter RAM1_DATA_WIDTH = 34, RAM2_DATA_WIDTH = 18, ADDR_WIDTH = 8, DEPTH = 32) (in_attr,out_class,clk,we1,rst_in,in_addr,ram1_data_in,ram2_data_in);




    input wire [RAM1_DATA_WIDTH-1:0] in_attr;
    input wire  clk, we1, rst_in;
    input wire [ADDR_WIDTH-1:0] in_addr;
    input wire [RAM1_DATA_WIDTH-1:0] ram1_data_in;
    input wire [RAM2_DATA_WIDTH-1:0] ram2_data_in;
    output reg [7:0] out_class;

    reg [4:0] c1 = 0;

    reg [19:0] mac_acc;

    wire ram1clk;
    wire ram2clk;









    reg [8:0] ram2_9bit_reg;
    reg [ADDR_WIDTH-1:0] next_addr;
    reg [2:0] cnt = 3'b000;
    reg start1,start2=1'b0;
    wire start3;
    wire [9:0] ram1_10bit_wire;
    wire [8:0] ram2_9bit_wire;
    wire [7:0] next_addr_wire;
    wire [RAM1_DATA_WIDTH-1:0] ram1wire;
    wire [RAM2_DATA_WIDTH-1:0] ram2wire;
    wire [15:0] mac_acc_wire;


	reg [7:0] out_class_reg;





    clkdiv2 clkdiv (
		.clk(clk),
        .invclk2(ram2clk),
        .clk2(ram1clk)
        );



    sram #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(RAM1_DATA_WIDTH), .DEPTH(DEPTH)) sram_inst1 (
        .clk(ram1clk),
        .addr_a(in_addr),
        .addr_b(next_addr_wire),
        .data_a(ram1_data_in),
        .we_a(we1),
        .q_b(ram1wire)
        );

    sram #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(RAM2_DATA_WIDTH), .DEPTH(DEPTH)) sram_inst2 (
        .clk(ram2clk),
        .addr_a(in_addr),
        .addr_b(next_addr_wire),
        .data_a(ram2_data_in),
        .we_a(we1),
        .q_b(ram2wire)
        );

    mac1 mac_inst (
        .inputattr(in_attr),
        .inputcoeff(ram1wire),
        .clk(clk),
        .rst_in(rst_in),
        .acc(mac_acc_wire)
        );














    always @(in_attr) begin
            start1 = 1;

     end
    always @(posedge ram2clk) begin
        if (cnt ==1'b0)
           start2 =  1;
        else
            start2 =  0;
     end



    assign start3 = start1 & start2;
    assign next_addr_wire = next_addr;

	always @(posedge ram2clk) begin
	    cnt = cnt + 1;
	    if (start3 == 1)
	    begin
	       next_addr = 0;
	       end
	    else begin
		if(mac_acc_wire <= ram1wire[RAM1_DATA_WIDTH-25:RAM1_DATA_WIDTH-34]) begin
			ram2_9bit_reg = ram2wire[RAM2_DATA_WIDTH-1:RAM2_DATA_WIDTH-9];
			if(ram2_9bit_reg[8] == 1'b1) begin
				out_class = ram2_9bit_reg[7:0];
				next_addr = 8'b00000000;
			end else begin
				next_addr = ram2_9bit_reg[7:0];
				out_class = 8'b00000000;
			end
		end else begin
			ram2_9bit_reg = ram2wire[RAM2_DATA_WIDTH-10:0];
			if(ram2_9bit_reg[RAM2_DATA_WIDTH-10] == 1'b1) begin
				out_class = ram2_9bit_reg[7:0];
				next_addr = 8'b00000000;
			end else begin
			    c1 = c1 +1;
				next_addr = ram2_9bit_reg[7:0];
				out_class = 8'b00000000;
			end
		end
		end
	end



endmodule