data/full_repos/permissive/133976382/swap_endianness/vivado/se_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/133976382/swap_endianness/vivado/se_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #20 in_val1 = 32\'haabbccdd;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133976382/swap_endianness/vivado/se_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #20 in_val2 = 64\'h0001020304050607;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/133976382/swap_endianness/vivado/se_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #20 in_val3 = 256\'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f;\n        ^\n%Error: data/full_repos/permissive/133976382/swap_endianness/vivado/se_tb.v:29: Cannot find file containing module: \'swap_endianness\'\n    swap_endianness dut1 (\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133976382/swap_endianness/vivado,data/full_repos/permissive/133976382/swap_endianness\n             data/full_repos/permissive/133976382/swap_endianness/vivado,data/full_repos/permissive/133976382/swap_endianness.v\n             data/full_repos/permissive/133976382/swap_endianness/vivado,data/full_repos/permissive/133976382/swap_endianness.sv\n             swap_endianness\n             swap_endianness.v\n             swap_endianness.sv\n             obj_dir/swap_endianness\n             obj_dir/swap_endianness.v\n             obj_dir/swap_endianness.sv\n%Error: data/full_repos/permissive/133976382/swap_endianness/vivado/se_tb.v:34: Cannot find file containing module: \'swap_endianness\'\n    swap_endianness #(.WIDTH(64)) dut2 (\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133976382/swap_endianness/vivado/se_tb.v:39: Cannot find file containing module: \'swap_endianness\'\n    swap_endianness #(.WIDTH(256)) dut3 (\n    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module se_tb;
    reg     [31:0]    in_val1;
    wire    [31:0]    out_val1;
    reg     [63:0]    in_val2;
    wire    [63:0]    out_val2;
    reg     [255:0]    in_val3;
    wire    [255:0]    out_val3;

    initial begin
        in_val1 = 32'h00;
        in_val2 = 64'h00;
        in_val3 = 256'h00;

        #20 in_val1 = 32'haabbccdd;
        #20 in_val2 = 64'h0001020304050607;
        #20 in_val3 = 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f;
    end

    swap_endianness dut1 (
        .in_vect (in_val1),
        .out_vect (out_val1)
     );

    swap_endianness #(.WIDTH(64)) dut2 (
            .in_vect (in_val2),
            .out_vect (out_val2)
        );

    swap_endianness #(.WIDTH(256)) dut3 (
            .in_vect (in_val3),
            .out_vect (out_val3)
        );
endmodule
module se_tb;

    reg     [31:0]    in_val1;
    wire    [31:0]    out_val1;
    reg     [63:0]    in_val2;
    wire    [63:0]    out_val2;
    reg     [255:0]    in_val3;
    wire    [255:0]    out_val3;

    initial begin
        in_val1 = 32'h00;
        in_val2 = 64'h00;
        in_val3 = 256'h00;

        #20 in_val1 = 32'haabbccdd;
        #20 in_val2 = 64'h0001020304050607;
        #20 in_val3 = 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f;
    end

    swap_endianness dut1 (
        .in_vect (in_val1),
        .out_vect (out_val1)
     );

    swap_endianness #(.WIDTH(64)) dut2 (
            .in_vect (in_val2),
            .out_vect (out_val2)
        );

    swap_endianness #(.WIDTH(256)) dut3 (
            .in_vect (in_val3),
            .out_vect (out_val3)
        );
endmodule