data/full_repos/permissive/136422019/src/cla16_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/136422019/src/cla16_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/cla16_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/cla16_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/cla16_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/136422019/src/cla16_tb.v:15: Cannot find file containing module: \'cla16\'\n cla16 adder(S,Cout,PG,GG,A,B,Cin);  \n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/cla16\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/cla16.v\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/cla16.sv\n             cla16\n             cla16.v\n             cla16.sv\n             obj_dir/cla16\n             obj_dir/cla16.v\n             obj_dir/cla16.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cla16_tb;
	reg [31:0] test;
	

	reg [15:0] A;
	reg [15:0] B;
	reg Cin;
	

	wire [15:0] S;
	wire Cout;
	wire PG;
	wire GG;
	
	cla16 adder(S,Cout,PG,GG,A,B,Cin);
	
	initial begin 

		A <= 0; 
		B <= 0; 
		Cin <= 0;
		#100
		

		test <= 1;
		A <= 5;
		B <= 10;
		Cin <= 0; 
		#100
		test <= 2;
		A <= 50;
		B <= 25;
		Cin <= 1;
		#100
		test <= 3;
		A <= -5;
		B <= 10;
		Cin<= 0;
		#100;
	end
endmodule
module cla16_tb;

	reg [31:0] test;
	

	reg [15:0] A;
	reg [15:0] B;
	reg Cin;
	

	wire [15:0] S;
	wire Cout;
	wire PG;
	wire GG;
	
	cla16 adder(S,Cout,PG,GG,A,B,Cin);
	
	initial begin 

		A <= 0; 
		B <= 0; 
		Cin <= 0;
		#100
		

		test <= 1;
		A <= 5;
		B <= 10;
		Cin <= 0; 
		#100
		test <= 2;
		A <= 50;
		B <= 25;
		Cin <= 1;
		#100
		test <= 3;
		A <= -5;
		B <= 10;
		Cin<= 0;
		#100;
	end
endmodule