data/full_repos/permissive/191067740/icarus/tb_vga.v
 line:49: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/191067740/icarus/tb_vga.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #12.5 clk_4x = ~clk_4x;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/191067740/icarus/tb_vga.v:49: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/191067740/icarus/tb_vga.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #60\n        ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_vga;
    reg clk_4x, clk_2x, clk;
    reg reset;
	reg sel_ram;
	reg sel_ctl;
	reg we;
	reg [12:0] addr;
	reg [7:0] din;
	wire [7:0] ram_dout;
	wire [7:0] ctl_dout;
	wire [1:0] vga_r, vga_g, vga_b;
	wire vga_vs, vga_hs;
	

    always
        #12.5 clk_4x = ~clk_4x;
    

	always @(posedge clk_4x)
		{clk,clk_2x} <= {clk,clk_2x} + 2'b01;
	

    initial
    begin
`ifdef icarus
  		$dumpfile("tb_vga.vcd");
		$dumpvars;
`endif
        

        clk_4x = 1'b0;
        clk_2x = 1'b0;
        clk = 1'b0;
        reset = 1'b1;
		sel_ram = 1'b0;
		sel_ctl = 1'b0;
		we = 1'b0;
		addr = 13'h0000;
		din = 8'h00;
        

        #60
		@(posedge clk)
        reset = 1'b0;
        
`ifdef icarus


		#1000000 $finish;
`endif
    end
    

	vga uut
	(
		.clk(clk),
		.clk_4x(clk_4x),
		.reset(reset),
		.sel_ram(sel_ram),
		.sel_ctl(sel_ctl),
		.we(we),
		.addr(addr),
		.din(din),
		.ram_dout(ram_dout),
		.ctl_dout(ctl_dout),
		.vga_r(vga_r),
		.vga_g(vga_g),
		.vga_b(vga_b),
		.vga_vs(vga_vs),
		.vga_hs(vga_hs)
	);
endmodule
module tb_vga;

    reg clk_4x, clk_2x, clk;
    reg reset;
	reg sel_ram;
	reg sel_ctl;
	reg we;
	reg [12:0] addr;
	reg [7:0] din;
	wire [7:0] ram_dout;
	wire [7:0] ctl_dout;
	wire [1:0] vga_r, vga_g, vga_b;
	wire vga_vs, vga_hs;
	

    always
        #12.5 clk_4x = ~clk_4x;
    

	always @(posedge clk_4x)
		{clk,clk_2x} <= {clk,clk_2x} + 2'b01;
	

    initial
    begin
`ifdef icarus
  		$dumpfile("tb_vga.vcd");
		$dumpvars;
`endif
        

        clk_4x = 1'b0;
        clk_2x = 1'b0;
        clk = 1'b0;
        reset = 1'b1;
		sel_ram = 1'b0;
		sel_ctl = 1'b0;
		we = 1'b0;
		addr = 13'h0000;
		din = 8'h00;
        

        #60
		@(posedge clk)
        reset = 1'b0;
        
`ifdef icarus


		#1000000 $finish;
`endif
    end
    

	vga uut
	(
		.clk(clk),
		.clk_4x(clk_4x),
		.reset(reset),
		.sel_ram(sel_ram),
		.sel_ctl(sel_ctl),
		.we(we),
		.addr(addr),
		.din(din),
		.ram_dout(ram_dout),
		.ctl_dout(ctl_dout),
		.vga_r(vga_r),
		.vga_g(vga_g),
		.vga_b(vga_b),
		.vga_vs(vga_vs),
		.vga_hs(vga_hs)
	);
endmodule