data/full_repos/permissive/112626266/Alu.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/112626266/Alu.v:31: Multiple top level modules\n                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                : ... Top module \'alu_control\'\nmodule alu_control(ALUOp,FUNCT,op_code);\n       ^~~~~~~~~~~\n                                                                : ... Top module \'ALU\'\nmodule ALU(read_data1, read_data2, op_code, result, zero);\n       ^~~\n                                                                : ... Top module \'two_to_one_mux\'\nmodule two_to_one_mux(read_data2 , sign_extend , ALUSrc , write_data);\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module ALU(read_data1, read_data2, op_code, result, zero);
input [31:0] read_data1 , read_data2;
input [3:0] op_code;
output reg [31:0] result;
output reg zero ;
always@(*)
begin
zero=1'b0;
if(op_code == 0)
begin result = read_data1 + read_data2; end

else if(op_code == 1)
begin result = read_data1 - read_data2; 

if (result==0)  
zero=1'b1;
else 
zero=1'b0;
end

else if(op_code == 2)
begin result = read_data1 & read_data2; end

else if(op_code == 3)
begin result = read_data1 | read_data2; end

else if(op_code == 4)
begin result = read_data1 << read_data2; end

else if(op_code == 5)
begin result = read_data1 >> read_data2; end

else if(op_code == 6)
begin result = $signed(read_data1) >>> read_data2; end

else if(op_code == 7)
begin
if(read_data1 > read_data2) begin result = read_data1; end
else begin result = read_data2; end
end

else if(op_code == 8)
begin

if(read_data1 < read_data2) begin result = read_data1; end
else begin result = read_data2; end
end

else begin result = 32'bx; end

end

endmodule
module ALU(read_data1, read_data2, op_code, result, zero);

input [31:0] read_data1 , read_data2;
input [3:0] op_code;
output reg [31:0] result;
output reg zero ;
always@(*)
begin
zero=1'b0;
if(op_code == 0)
begin result = read_data1 + read_data2; end

else if(op_code == 1)
begin result = read_data1 - read_data2; 

if (result==0)  
zero=1'b1;
else 
zero=1'b0;
end

else if(op_code == 2)
begin result = read_data1 & read_data2; end

else if(op_code == 3)
begin result = read_data1 | read_data2; end

else if(op_code == 4)
begin result = read_data1 << read_data2; end

else if(op_code == 5)
begin result = read_data1 >> read_data2; end

else if(op_code == 6)
begin result = $signed(read_data1) >>> read_data2; end

else if(op_code == 7)
begin
if(read_data1 > read_data2) begin result = read_data1; end
else begin result = read_data2; end
end

else if(op_code == 8)
begin

if(read_data1 < read_data2) begin result = read_data1; end
else begin result = read_data2; end
end

else begin result = 32'bx; end

end

endmodule