data/full_repos/permissive/205926239/ISE_project/Sources/ps2_keyboard.v
1: b'%Warning-WIDTH: data/full_repos/permissive/205926239/ISE_project/Sources/ps2_keyboard.v:498: Operator EQ expects 16 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                           : ... In instance ps2_keyboard_interface\nassign extended = (q[8:1] == 16\'hE0) && rx_shifting_done;\n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205926239/ISE_project/Sources/ps2_keyboard.v:499: Operator EQ expects 16 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                           : ... In instance ps2_keyboard_interface\nassign released = (q[8:1] == 16\'hF0) && rx_shifting_done;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/205926239/ISE_project/Sources/ps2_keyboard.v:525: Operator EQ expects 16 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                           : ... In instance ps2_keyboard_interface\n  else if ((q[8:1] == 16\'h12) && rx_shifting_done && hold_released)\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/205926239/ISE_project/Sources/ps2_keyboard.v:523: Operator EQ expects 16 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                           : ... In instance ps2_keyboard_interface\n  else if ((q[8:1] == 16\'h12) && rx_shifting_done && ~hold_released)\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/205926239/ISE_project/Sources/ps2_keyboard.v:534: Operator EQ expects 16 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                           : ... In instance ps2_keyboard_interface\n  else if ((q[8:1] == 16\'h59) && rx_shifting_done && hold_released)\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/205926239/ISE_project/Sources/ps2_keyboard.v:532: Operator EQ expects 16 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                           : ... In instance ps2_keyboard_interface\n  else if ((q[8:1] == 16\'h59) && rx_shifting_done && ~hold_released)\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/205926239/ISE_project/Sources/ps2_keyboard.v:572: Operator NEQ expects 16 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                           : ... In instance ps2_keyboard_interface\n                               || ( (q[8:1] != 16\'h59)\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/205926239/ISE_project/Sources/ps2_keyboard.v:573: Operator NEQ expects 16 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                           : ... In instance ps2_keyboard_interface\n                                    &&(q[8:1] != 16\'h12)\n                                              ^~\n%Error: Exiting due to 8 warning(s)\n'
module ps2_keyboard_interface (
  clk,
  reset,
  ps2_clk,
  ps2_data,
  rx_extended,
  rx_released,
  rx_shift_key_on,
  rx_scan_code,
  rx_ascii,
  rx_data_ready,
  rx_read,
  tx_data,
  tx_write,
  tx_write_ack_o,
  tx_error_no_keyboard_ack
  );




parameter TIMER_60USEC_VALUE_PP = 3000;
parameter TIMER_60USEC_BITS_PP  = 12;
parameter TIMER_5USEC_VALUE_PP = 250;
parameter TIMER_5USEC_BITS_PP  = 8;
parameter TRAP_SHIFT_KEYS_PP = 0;














parameter m1_rx_clk_h = 1;
parameter m1_rx_clk_l = 0;
parameter m1_rx_falling_edge_marker = 13;
parameter m1_rx_rising_edge_marker = 14;
parameter m1_tx_force_clk_l = 3;
parameter m1_tx_first_wait_clk_h = 10;
parameter m1_tx_first_wait_clk_l = 11;
parameter m1_tx_reset_timer = 12;
parameter m1_tx_wait_clk_h = 2;
parameter m1_tx_clk_h = 4;
parameter m1_tx_clk_l = 5;
parameter m1_tx_wait_keyboard_ack = 6;
parameter m1_tx_done_recovery = 7;
parameter m1_tx_error_no_keyboard_ack = 8;
parameter m1_tx_rising_edge_marker = 9;
parameter m2_rx_data_ready = 1;
parameter m2_rx_data_ready_ack = 0;

  

input clk;
input reset;
inout ps2_clk;
inout ps2_data;
output rx_extended;
output rx_released;
output rx_shift_key_on;
output [7:0] rx_scan_code;
output [7:0] rx_ascii;
output rx_data_ready;
input rx_read;
input [7:0] tx_data;
input tx_write;
output tx_write_ack_o;
output tx_error_no_keyboard_ack;

reg rx_extended;
reg rx_released;
reg [7:0] rx_scan_code;
reg [7:0] rx_ascii;
reg rx_data_ready;
reg tx_error_no_keyboard_ack;


wire timer_60usec_done;
wire timer_5usec_done;
wire extended;
wire released;
wire shift_key_on;








wire rx_output_event;
wire rx_output_strobe;

wire tx_parity_bit;
wire rx_shifting_done;
wire tx_shifting_done;
wire [11:0] shift_key_plus_code;

reg [`TOTAL_BITS-1:0] q;
reg [3:0] m1_state;
reg [3:0] m1_next_state;
reg m2_state;
reg m2_next_state;
reg [3:0] bit_count;
reg enable_timer_60usec;
reg enable_timer_5usec;
reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;
reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;
reg [7:0] ascii;
reg left_shift_key;
reg right_shift_key;
reg hold_extended;
reg hold_released;
reg ps2_clk_s;
reg ps2_data_s;
reg ps2_clk_hi_z;
reg ps2_data_hi_z;




assign ps2_clk = ps2_clk_hi_z?1'bZ:1'b0;
assign ps2_data = ps2_data_hi_z?1'bZ:1'b0;




always @(posedge clk)
begin
  ps2_clk_s <= ps2_clk;
  ps2_data_s <= ps2_data;
end


always @(posedge clk)
begin : m1_state_register
  if (reset) m1_state <= m1_rx_clk_h;
  else m1_state <= m1_next_state;
end


always @(m1_state
         or q
         or tx_shifting_done
         or tx_write
         or ps2_clk_s
         or ps2_data_s
         or timer_60usec_done
         or timer_5usec_done
         )
begin : m1_state_logic


  ps2_clk_hi_z <= 1;
  ps2_data_hi_z <= 1;
  tx_error_no_keyboard_ack <= 0;
  enable_timer_60usec <= 0;
  enable_timer_5usec <= 0;

  case (m1_state)

    m1_rx_clk_h :
      begin
        enable_timer_60usec <= 1;
        if (tx_write) m1_next_state <= m1_tx_reset_timer;
        else if (~ps2_clk_s) m1_next_state <= m1_rx_falling_edge_marker;
        else m1_next_state <= m1_rx_clk_h;
      end
      
    m1_rx_falling_edge_marker :
      begin
        enable_timer_60usec <= 0;
        m1_next_state <= m1_rx_clk_l;
      end

    m1_rx_rising_edge_marker :
      begin
        enable_timer_60usec <= 0;
        m1_next_state <= m1_rx_clk_h;
      end


    m1_rx_clk_l :
      begin
        enable_timer_60usec <= 1;
        if (tx_write) m1_next_state <= m1_tx_reset_timer;
        else if (ps2_clk_s) m1_next_state <= m1_rx_rising_edge_marker;
        else m1_next_state <= m1_rx_clk_l;
      end

    m1_tx_reset_timer:
      begin
        enable_timer_60usec <= 0;
        m1_next_state <= m1_tx_force_clk_l;
      end

    m1_tx_force_clk_l :
      begin
        enable_timer_60usec <= 1;
        ps2_clk_hi_z <= 0;
        if (timer_60usec_done) m1_next_state <= m1_tx_first_wait_clk_h;
        else m1_next_state <= m1_tx_force_clk_l;
      end

    m1_tx_first_wait_clk_h :
      begin
        enable_timer_5usec <= 1;
        ps2_data_hi_z <= 0;
        if (~ps2_clk_s && timer_5usec_done)
          m1_next_state <= m1_tx_clk_l;
        else
          m1_next_state <= m1_tx_first_wait_clk_h;
      end
      





    m1_tx_first_wait_clk_l :
      begin
        ps2_data_hi_z <= 0;
        if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
        else m1_next_state <= m1_tx_first_wait_clk_l;
      end

    m1_tx_wait_clk_h :
      begin
        enable_timer_5usec <= 1;
        ps2_data_hi_z <= q[0];
        if (ps2_clk_s && timer_5usec_done)
          m1_next_state <= m1_tx_rising_edge_marker;
        else
          m1_next_state <= m1_tx_wait_clk_h;
      end

    m1_tx_rising_edge_marker :
      begin
        ps2_data_hi_z <= q[0];
        m1_next_state <= m1_tx_clk_h;
      end

    m1_tx_clk_h :
      begin
        ps2_data_hi_z <= q[0];
        if (tx_shifting_done) m1_next_state <= m1_tx_wait_keyboard_ack;
        else if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
        else m1_next_state <= m1_tx_clk_h;
      end

    m1_tx_clk_l :
      begin
        ps2_data_hi_z <= q[0];
        if (ps2_clk_s) m1_next_state <= m1_tx_wait_clk_h;
        else m1_next_state <= m1_tx_clk_l;
      end

    m1_tx_wait_keyboard_ack :
      begin
        if (~ps2_clk_s && ps2_data_s)
          m1_next_state <= m1_tx_error_no_keyboard_ack;
        else if (~ps2_clk_s && ~ps2_data_s)
          m1_next_state <= m1_tx_done_recovery;
        else m1_next_state <= m1_tx_wait_keyboard_ack;
      end

    m1_tx_done_recovery :
      begin
        if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
        else m1_next_state <= m1_tx_done_recovery;
      end

    m1_tx_error_no_keyboard_ack :
      begin
        tx_error_no_keyboard_ack <= 1;
        if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
        else m1_next_state <= m1_tx_error_no_keyboard_ack;
      end

    default : m1_next_state <= m1_rx_clk_h;
  endcase
end


always @(posedge clk)
begin : m2_state_register
  if (reset) m2_state <= m2_rx_data_ready_ack;
  else m2_state <= m2_next_state;
end


always @(m2_state or rx_output_strobe or rx_read)
begin : m2_state_logic
  case (m2_state)
    m2_rx_data_ready_ack:
          begin
            rx_data_ready <= 1'b0;
            if (rx_output_strobe) m2_next_state <= m2_rx_data_ready;
            else m2_next_state <= m2_rx_data_ready_ack;
          end
    m2_rx_data_ready:
          begin
            rx_data_ready <= 1'b1;
            if (rx_read) m2_next_state <= m2_rx_data_ready_ack;
            else m2_next_state <= m2_rx_data_ready;
          end
    default : m2_next_state <= m2_rx_data_ready_ack;
  endcase
end


always @(posedge clk)
begin
  if (   reset
      || rx_shifting_done
      || (m1_state == m1_tx_wait_keyboard_ack)
      ) bit_count <= 0;
  else if (timer_60usec_done
           && (m1_state == m1_rx_clk_h)
           && (ps2_clk_s)
      ) bit_count <= 0;
  else if ( (m1_state == m1_rx_falling_edge_marker)
           ||(m1_state == m1_tx_rising_edge_marker)
           )
    bit_count <= bit_count + 1;
end

assign rx_shifting_done = (bit_count == `TOTAL_BITS);
assign tx_shifting_done = (bit_count == `TOTAL_BITS-1);



assign tx_write_ack_o = (  (tx_write && (m1_state == m1_rx_clk_h))
                         ||(tx_write && (m1_state == m1_rx_clk_l))
                         );


assign tx_parity_bit = ~^tx_data;


always @(posedge clk)
begin
  if (reset) q <= 0;
  else if (tx_write_ack_o) q <= {1'b1,tx_parity_bit,tx_data,1'b0};
  else if ( (m1_state == m1_rx_falling_edge_marker)
           ||(m1_state == m1_tx_rising_edge_marker) )
    q <= {ps2_data_s,q[`TOTAL_BITS-1:1]};
end


always @(posedge clk)
begin
  if (~enable_timer_60usec) timer_60usec_count <= 0;
  else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1;
end
assign timer_60usec_done = (timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));


always @(posedge clk)
begin
  if (~enable_timer_5usec) timer_5usec_count <= 0;
  else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 1;
end
assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);




assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done;
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done;




always @(posedge clk)
begin
  if (reset || rx_output_event)
  begin
    hold_extended <= 0;
    hold_released <= 0;
  end
  else
  begin
    if (rx_shifting_done && extended) hold_extended <= 1;
    if (rx_shifting_done && released) hold_released <= 1;
  end
end



always @(posedge clk)
begin
  if (reset) left_shift_key <= 0;
  else if ((q[8:1] == `LEFT_SHIFT) && rx_shifting_done && ~hold_released)
    left_shift_key <= 1;
  else if ((q[8:1] == `LEFT_SHIFT) && rx_shifting_done && hold_released)
    left_shift_key <= 0;
end

always @(posedge clk)
begin
  if (reset) right_shift_key <= 0;
  else if ((q[8:1] == `RIGHT_SHIFT) && rx_shifting_done && ~hold_released)
    right_shift_key <= 1;
  else if ((q[8:1] == `RIGHT_SHIFT) && rx_shifting_done && hold_released)
    right_shift_key <= 0;
end

assign rx_shift_key_on = left_shift_key || right_shift_key;


always @(posedge clk)
begin
  if (reset)
  begin
    rx_extended <= 0;
    rx_released <= 0;
    rx_scan_code <= 0;
    rx_ascii <= 0;
  end
  else if (rx_output_strobe)
  begin
    rx_extended <= hold_extended;
    rx_released <= hold_released;
    rx_scan_code <= q[8:1];
    rx_ascii <= ascii;
  end
end





assign rx_output_event  = (rx_shifting_done
                          && ~extended 
                          && ~released
                          );

assign rx_output_strobe = (rx_shifting_done
                          && ~extended 
                          && ~released
                          && ( (TRAP_SHIFT_KEYS_PP == 0) 
                               || ( (q[8:1] != `RIGHT_SHIFT)
                                    &&(q[8:1] != `LEFT_SHIFT)
                                  )
                             )
                          );






assign shift_key_plus_code = {3'b0,rx_shift_key_on,q[8:1]};
always @(shift_key_plus_code)
begin
  casez (shift_key_plus_code)
    12'h?66 : ascii <= 8'h08;
    12'h?0d : ascii <= 8'h09;
    12'h?5a : ascii <= 8'h0d;
    12'h?76 : ascii <= 8'h1b;
    12'h?29 : ascii <= 8'h20;
    12'h116 : ascii <= 8'h21;
    12'h152 : ascii <= 8'h22;
    12'h126 : ascii <= 8'h23;
    12'h125 : ascii <= 8'h24;
    12'h12e : ascii <= 8'h25;
    12'h13d : ascii <= 8'h26;
    12'h052 : ascii <= 8'h27;
    12'h146 : ascii <= 8'h28;
    12'h145 : ascii <= 8'h29;
    12'h13e : ascii <= 8'h2a;
    12'h155 : ascii <= 8'h2b;
    12'h041 : ascii <= 8'h2c;
    12'h04e : ascii <= 8'h2d;
    12'h049 : ascii <= 8'h2e;
    12'h04a : ascii <= 8'h2f;
    12'h045 : ascii <= 8'h30;
    12'h016 : ascii <= 8'h31;
    12'h01e : ascii <= 8'h32;
    12'h026 : ascii <= 8'h33;
    12'h025 : ascii <= 8'h34;
    12'h02e : ascii <= 8'h35;
    12'h036 : ascii <= 8'h36;
    12'h03d : ascii <= 8'h37;
    12'h03e : ascii <= 8'h38;
    12'h046 : ascii <= 8'h39;
    12'h14c : ascii <= 8'h3a;
    12'h04c : ascii <= 8'h3b;
    12'h141 : ascii <= 8'h3c;
    12'h055 : ascii <= 8'h3d;
    12'h149 : ascii <= 8'h3e;
    12'h14a : ascii <= 8'h3f;
    12'h11e : ascii <= 8'h40;
    12'h11c : ascii <= 8'h41;
    12'h132 : ascii <= 8'h42;
    12'h121 : ascii <= 8'h43;
    12'h123 : ascii <= 8'h44;
    12'h124 : ascii <= 8'h45;
    12'h12b : ascii <= 8'h46;
    12'h134 : ascii <= 8'h47;
    12'h133 : ascii <= 8'h48;
    12'h143 : ascii <= 8'h49;
    12'h13b : ascii <= 8'h4a;
    12'h142 : ascii <= 8'h4b;
    12'h14b : ascii <= 8'h4c;
    12'h13a : ascii <= 8'h4d;
    12'h131 : ascii <= 8'h4e;
    12'h144 : ascii <= 8'h4f;
    12'h14d : ascii <= 8'h50;
    12'h115 : ascii <= 8'h51;
    12'h12d : ascii <= 8'h52;
    12'h11b : ascii <= 8'h53;
    12'h12c : ascii <= 8'h54;
    12'h13c : ascii <= 8'h55;
    12'h12a : ascii <= 8'h56;
    12'h11d : ascii <= 8'h57;
    12'h122 : ascii <= 8'h58;
    12'h135 : ascii <= 8'h59;
    12'h11a : ascii <= 8'h5a;
    12'h054 : ascii <= 8'h5b;
    12'h05d : ascii <= 8'h5c;
    12'h05b : ascii <= 8'h5d;
    12'h136 : ascii <= 8'h5e;
    12'h14e : ascii <= 8'h5f;
    12'h00e : ascii <= 8'h60;
    12'h01c : ascii <= 8'h61;
    12'h032 : ascii <= 8'h62;
    12'h021 : ascii <= 8'h63;
    12'h023 : ascii <= 8'h64;
    12'h024 : ascii <= 8'h65;
    12'h02b : ascii <= 8'h66;
    12'h034 : ascii <= 8'h67;
    12'h033 : ascii <= 8'h68;
    12'h043 : ascii <= 8'h69;
    12'h03b : ascii <= 8'h6a;
    12'h042 : ascii <= 8'h6b;
    12'h04b : ascii <= 8'h6c;
    12'h03a : ascii <= 8'h6d;
    12'h031 : ascii <= 8'h6e;
    12'h044 : ascii <= 8'h6f;
    12'h04d : ascii <= 8'h70;
    12'h015 : ascii <= 8'h71;
    12'h02d : ascii <= 8'h72;
    12'h01b : ascii <= 8'h73;
    12'h02c : ascii <= 8'h74;
    12'h03c : ascii <= 8'h75;
    12'h02a : ascii <= 8'h76;
    12'h01d : ascii <= 8'h77;
    12'h022 : ascii <= 8'h78;
    12'h035 : ascii <= 8'h79;
    12'h01a : ascii <= 8'h7a;
    12'h154 : ascii <= 8'h7b;
    12'h15d : ascii <= 8'h7c;
    12'h15b : ascii <= 8'h7d;
    12'h10e : ascii <= 8'h7e;
    12'h?71 : ascii <= 8'h7f;
    default : ascii <= 8'h2e;
  endcase
end


endmodule
module ps2_keyboard_interface (
  clk,
  reset,
  ps2_clk,
  ps2_data,
  rx_extended,
  rx_released,
  rx_shift_key_on,
  rx_scan_code,
  rx_ascii,
  rx_data_ready,
  rx_read,
  tx_data,
  tx_write,
  tx_write_ack_o,
  tx_error_no_keyboard_ack
  );





parameter TIMER_60USEC_VALUE_PP = 3000;
parameter TIMER_60USEC_BITS_PP  = 12;
parameter TIMER_5USEC_VALUE_PP = 250;
parameter TIMER_5USEC_BITS_PP  = 8;
parameter TRAP_SHIFT_KEYS_PP = 0;














parameter m1_rx_clk_h = 1;
parameter m1_rx_clk_l = 0;
parameter m1_rx_falling_edge_marker = 13;
parameter m1_rx_rising_edge_marker = 14;
parameter m1_tx_force_clk_l = 3;
parameter m1_tx_first_wait_clk_h = 10;
parameter m1_tx_first_wait_clk_l = 11;
parameter m1_tx_reset_timer = 12;
parameter m1_tx_wait_clk_h = 2;
parameter m1_tx_clk_h = 4;
parameter m1_tx_clk_l = 5;
parameter m1_tx_wait_keyboard_ack = 6;
parameter m1_tx_done_recovery = 7;
parameter m1_tx_error_no_keyboard_ack = 8;
parameter m1_tx_rising_edge_marker = 9;
parameter m2_rx_data_ready = 1;
parameter m2_rx_data_ready_ack = 0;

  

input clk;
input reset;
inout ps2_clk;
inout ps2_data;
output rx_extended;
output rx_released;
output rx_shift_key_on;
output [7:0] rx_scan_code;
output [7:0] rx_ascii;
output rx_data_ready;
input rx_read;
input [7:0] tx_data;
input tx_write;
output tx_write_ack_o;
output tx_error_no_keyboard_ack;

reg rx_extended;
reg rx_released;
reg [7:0] rx_scan_code;
reg [7:0] rx_ascii;
reg rx_data_ready;
reg tx_error_no_keyboard_ack;


wire timer_60usec_done;
wire timer_5usec_done;
wire extended;
wire released;
wire shift_key_on;








wire rx_output_event;
wire rx_output_strobe;

wire tx_parity_bit;
wire rx_shifting_done;
wire tx_shifting_done;
wire [11:0] shift_key_plus_code;

reg [`TOTAL_BITS-1:0] q;
reg [3:0] m1_state;
reg [3:0] m1_next_state;
reg m2_state;
reg m2_next_state;
reg [3:0] bit_count;
reg enable_timer_60usec;
reg enable_timer_5usec;
reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;
reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;
reg [7:0] ascii;
reg left_shift_key;
reg right_shift_key;
reg hold_extended;
reg hold_released;
reg ps2_clk_s;
reg ps2_data_s;
reg ps2_clk_hi_z;
reg ps2_data_hi_z;




assign ps2_clk = ps2_clk_hi_z?1'bZ:1'b0;
assign ps2_data = ps2_data_hi_z?1'bZ:1'b0;




always @(posedge clk)
begin
  ps2_clk_s <= ps2_clk;
  ps2_data_s <= ps2_data;
end


always @(posedge clk)
begin : m1_state_register
  if (reset) m1_state <= m1_rx_clk_h;
  else m1_state <= m1_next_state;
end


always @(m1_state
         or q
         or tx_shifting_done
         or tx_write
         or ps2_clk_s
         or ps2_data_s
         or timer_60usec_done
         or timer_5usec_done
         )
begin : m1_state_logic


  ps2_clk_hi_z <= 1;
  ps2_data_hi_z <= 1;
  tx_error_no_keyboard_ack <= 0;
  enable_timer_60usec <= 0;
  enable_timer_5usec <= 0;

  case (m1_state)

    m1_rx_clk_h :
      begin
        enable_timer_60usec <= 1;
        if (tx_write) m1_next_state <= m1_tx_reset_timer;
        else if (~ps2_clk_s) m1_next_state <= m1_rx_falling_edge_marker;
        else m1_next_state <= m1_rx_clk_h;
      end
      
    m1_rx_falling_edge_marker :
      begin
        enable_timer_60usec <= 0;
        m1_next_state <= m1_rx_clk_l;
      end

    m1_rx_rising_edge_marker :
      begin
        enable_timer_60usec <= 0;
        m1_next_state <= m1_rx_clk_h;
      end


    m1_rx_clk_l :
      begin
        enable_timer_60usec <= 1;
        if (tx_write) m1_next_state <= m1_tx_reset_timer;
        else if (ps2_clk_s) m1_next_state <= m1_rx_rising_edge_marker;
        else m1_next_state <= m1_rx_clk_l;
      end

    m1_tx_reset_timer:
      begin
        enable_timer_60usec <= 0;
        m1_next_state <= m1_tx_force_clk_l;
      end

    m1_tx_force_clk_l :
      begin
        enable_timer_60usec <= 1;
        ps2_clk_hi_z <= 0;
        if (timer_60usec_done) m1_next_state <= m1_tx_first_wait_clk_h;
        else m1_next_state <= m1_tx_force_clk_l;
      end

    m1_tx_first_wait_clk_h :
      begin
        enable_timer_5usec <= 1;
        ps2_data_hi_z <= 0;
        if (~ps2_clk_s && timer_5usec_done)
          m1_next_state <= m1_tx_clk_l;
        else
          m1_next_state <= m1_tx_first_wait_clk_h;
      end
      





    m1_tx_first_wait_clk_l :
      begin
        ps2_data_hi_z <= 0;
        if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
        else m1_next_state <= m1_tx_first_wait_clk_l;
      end

    m1_tx_wait_clk_h :
      begin
        enable_timer_5usec <= 1;
        ps2_data_hi_z <= q[0];
        if (ps2_clk_s && timer_5usec_done)
          m1_next_state <= m1_tx_rising_edge_marker;
        else
          m1_next_state <= m1_tx_wait_clk_h;
      end

    m1_tx_rising_edge_marker :
      begin
        ps2_data_hi_z <= q[0];
        m1_next_state <= m1_tx_clk_h;
      end

    m1_tx_clk_h :
      begin
        ps2_data_hi_z <= q[0];
        if (tx_shifting_done) m1_next_state <= m1_tx_wait_keyboard_ack;
        else if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
        else m1_next_state <= m1_tx_clk_h;
      end

    m1_tx_clk_l :
      begin
        ps2_data_hi_z <= q[0];
        if (ps2_clk_s) m1_next_state <= m1_tx_wait_clk_h;
        else m1_next_state <= m1_tx_clk_l;
      end

    m1_tx_wait_keyboard_ack :
      begin
        if (~ps2_clk_s && ps2_data_s)
          m1_next_state <= m1_tx_error_no_keyboard_ack;
        else if (~ps2_clk_s && ~ps2_data_s)
          m1_next_state <= m1_tx_done_recovery;
        else m1_next_state <= m1_tx_wait_keyboard_ack;
      end

    m1_tx_done_recovery :
      begin
        if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
        else m1_next_state <= m1_tx_done_recovery;
      end

    m1_tx_error_no_keyboard_ack :
      begin
        tx_error_no_keyboard_ack <= 1;
        if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
        else m1_next_state <= m1_tx_error_no_keyboard_ack;
      end

    default : m1_next_state <= m1_rx_clk_h;
  endcase
end


always @(posedge clk)
begin : m2_state_register
  if (reset) m2_state <= m2_rx_data_ready_ack;
  else m2_state <= m2_next_state;
end


always @(m2_state or rx_output_strobe or rx_read)
begin : m2_state_logic
  case (m2_state)
    m2_rx_data_ready_ack:
          begin
            rx_data_ready <= 1'b0;
            if (rx_output_strobe) m2_next_state <= m2_rx_data_ready;
            else m2_next_state <= m2_rx_data_ready_ack;
          end
    m2_rx_data_ready:
          begin
            rx_data_ready <= 1'b1;
            if (rx_read) m2_next_state <= m2_rx_data_ready_ack;
            else m2_next_state <= m2_rx_data_ready;
          end
    default : m2_next_state <= m2_rx_data_ready_ack;
  endcase
end


always @(posedge clk)
begin
  if (   reset
      || rx_shifting_done
      || (m1_state == m1_tx_wait_keyboard_ack)
      ) bit_count <= 0;
  else if (timer_60usec_done
           && (m1_state == m1_rx_clk_h)
           && (ps2_clk_s)
      ) bit_count <= 0;
  else if ( (m1_state == m1_rx_falling_edge_marker)
           ||(m1_state == m1_tx_rising_edge_marker)
           )
    bit_count <= bit_count + 1;
end

assign rx_shifting_done = (bit_count == `TOTAL_BITS);
assign tx_shifting_done = (bit_count == `TOTAL_BITS-1);



assign tx_write_ack_o = (  (tx_write && (m1_state == m1_rx_clk_h))
                         ||(tx_write && (m1_state == m1_rx_clk_l))
                         );


assign tx_parity_bit = ~^tx_data;


always @(posedge clk)
begin
  if (reset) q <= 0;
  else if (tx_write_ack_o) q <= {1'b1,tx_parity_bit,tx_data,1'b0};
  else if ( (m1_state == m1_rx_falling_edge_marker)
           ||(m1_state == m1_tx_rising_edge_marker) )
    q <= {ps2_data_s,q[`TOTAL_BITS-1:1]};
end


always @(posedge clk)
begin
  if (~enable_timer_60usec) timer_60usec_count <= 0;
  else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1;
end
assign timer_60usec_done = (timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));


always @(posedge clk)
begin
  if (~enable_timer_5usec) timer_5usec_count <= 0;
  else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 1;
end
assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);




assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done;
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done;




always @(posedge clk)
begin
  if (reset || rx_output_event)
  begin
    hold_extended <= 0;
    hold_released <= 0;
  end
  else
  begin
    if (rx_shifting_done && extended) hold_extended <= 1;
    if (rx_shifting_done && released) hold_released <= 1;
  end
end



always @(posedge clk)
begin
  if (reset) left_shift_key <= 0;
  else if ((q[8:1] == `LEFT_SHIFT) && rx_shifting_done && ~hold_released)
    left_shift_key <= 1;
  else if ((q[8:1] == `LEFT_SHIFT) && rx_shifting_done && hold_released)
    left_shift_key <= 0;
end

always @(posedge clk)
begin
  if (reset) right_shift_key <= 0;
  else if ((q[8:1] == `RIGHT_SHIFT) && rx_shifting_done && ~hold_released)
    right_shift_key <= 1;
  else if ((q[8:1] == `RIGHT_SHIFT) && rx_shifting_done && hold_released)
    right_shift_key <= 0;
end

assign rx_shift_key_on = left_shift_key || right_shift_key;


always @(posedge clk)
begin
  if (reset)
  begin
    rx_extended <= 0;
    rx_released <= 0;
    rx_scan_code <= 0;
    rx_ascii <= 0;
  end
  else if (rx_output_strobe)
  begin
    rx_extended <= hold_extended;
    rx_released <= hold_released;
    rx_scan_code <= q[8:1];
    rx_ascii <= ascii;
  end
end





assign rx_output_event  = (rx_shifting_done
                          && ~extended 
                          && ~released
                          );

assign rx_output_strobe = (rx_shifting_done
                          && ~extended 
                          && ~released
                          && ( (TRAP_SHIFT_KEYS_PP == 0) 
                               || ( (q[8:1] != `RIGHT_SHIFT)
                                    &&(q[8:1] != `LEFT_SHIFT)
                                  )
                             )
                          );






assign shift_key_plus_code = {3'b0,rx_shift_key_on,q[8:1]};
always @(shift_key_plus_code)
begin
  casez (shift_key_plus_code)
    12'h?66 : ascii <= 8'h08;
    12'h?0d : ascii <= 8'h09;
    12'h?5a : ascii <= 8'h0d;
    12'h?76 : ascii <= 8'h1b;
    12'h?29 : ascii <= 8'h20;
    12'h116 : ascii <= 8'h21;
    12'h152 : ascii <= 8'h22;
    12'h126 : ascii <= 8'h23;
    12'h125 : ascii <= 8'h24;
    12'h12e : ascii <= 8'h25;
    12'h13d : ascii <= 8'h26;
    12'h052 : ascii <= 8'h27;
    12'h146 : ascii <= 8'h28;
    12'h145 : ascii <= 8'h29;
    12'h13e : ascii <= 8'h2a;
    12'h155 : ascii <= 8'h2b;
    12'h041 : ascii <= 8'h2c;
    12'h04e : ascii <= 8'h2d;
    12'h049 : ascii <= 8'h2e;
    12'h04a : ascii <= 8'h2f;
    12'h045 : ascii <= 8'h30;
    12'h016 : ascii <= 8'h31;
    12'h01e : ascii <= 8'h32;
    12'h026 : ascii <= 8'h33;
    12'h025 : ascii <= 8'h34;
    12'h02e : ascii <= 8'h35;
    12'h036 : ascii <= 8'h36;
    12'h03d : ascii <= 8'h37;
    12'h03e : ascii <= 8'h38;
    12'h046 : ascii <= 8'h39;
    12'h14c : ascii <= 8'h3a;
    12'h04c : ascii <= 8'h3b;
    12'h141 : ascii <= 8'h3c;
    12'h055 : ascii <= 8'h3d;
    12'h149 : ascii <= 8'h3e;
    12'h14a : ascii <= 8'h3f;
    12'h11e : ascii <= 8'h40;
    12'h11c : ascii <= 8'h41;
    12'h132 : ascii <= 8'h42;
    12'h121 : ascii <= 8'h43;
    12'h123 : ascii <= 8'h44;
    12'h124 : ascii <= 8'h45;
    12'h12b : ascii <= 8'h46;
    12'h134 : ascii <= 8'h47;
    12'h133 : ascii <= 8'h48;
    12'h143 : ascii <= 8'h49;
    12'h13b : ascii <= 8'h4a;
    12'h142 : ascii <= 8'h4b;
    12'h14b : ascii <= 8'h4c;
    12'h13a : ascii <= 8'h4d;
    12'h131 : ascii <= 8'h4e;
    12'h144 : ascii <= 8'h4f;
    12'h14d : ascii <= 8'h50;
    12'h115 : ascii <= 8'h51;
    12'h12d : ascii <= 8'h52;
    12'h11b : ascii <= 8'h53;
    12'h12c : ascii <= 8'h54;
    12'h13c : ascii <= 8'h55;
    12'h12a : ascii <= 8'h56;
    12'h11d : ascii <= 8'h57;
    12'h122 : ascii <= 8'h58;
    12'h135 : ascii <= 8'h59;
    12'h11a : ascii <= 8'h5a;
    12'h054 : ascii <= 8'h5b;
    12'h05d : ascii <= 8'h5c;
    12'h05b : ascii <= 8'h5d;
    12'h136 : ascii <= 8'h5e;
    12'h14e : ascii <= 8'h5f;
    12'h00e : ascii <= 8'h60;
    12'h01c : ascii <= 8'h61;
    12'h032 : ascii <= 8'h62;
    12'h021 : ascii <= 8'h63;
    12'h023 : ascii <= 8'h64;
    12'h024 : ascii <= 8'h65;
    12'h02b : ascii <= 8'h66;
    12'h034 : ascii <= 8'h67;
    12'h033 : ascii <= 8'h68;
    12'h043 : ascii <= 8'h69;
    12'h03b : ascii <= 8'h6a;
    12'h042 : ascii <= 8'h6b;
    12'h04b : ascii <= 8'h6c;
    12'h03a : ascii <= 8'h6d;
    12'h031 : ascii <= 8'h6e;
    12'h044 : ascii <= 8'h6f;
    12'h04d : ascii <= 8'h70;
    12'h015 : ascii <= 8'h71;
    12'h02d : ascii <= 8'h72;
    12'h01b : ascii <= 8'h73;
    12'h02c : ascii <= 8'h74;
    12'h03c : ascii <= 8'h75;
    12'h02a : ascii <= 8'h76;
    12'h01d : ascii <= 8'h77;
    12'h022 : ascii <= 8'h78;
    12'h035 : ascii <= 8'h79;
    12'h01a : ascii <= 8'h7a;
    12'h154 : ascii <= 8'h7b;
    12'h15d : ascii <= 8'h7c;
    12'h15b : ascii <= 8'h7d;
    12'h10e : ascii <= 8'h7e;
    12'h?71 : ascii <= 8'h7f;
    default : ascii <= 8'h2e;
  endcase
end


endmodule