data/full_repos/permissive/147974511/src_old/singleKeyExpansion.v
1: b'%Error: data/full_repos/permissive/147974511/src_old/singleKeyExpansion.v:23: Cannot find file containing module: \'rcon\'\n   rcon uut1 (.r(keyNum),.rcon(Rcon));\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/147974511/src_old,data/full_repos/permissive/147974511/rcon\n             data/full_repos/permissive/147974511/src_old,data/full_repos/permissive/147974511/rcon.v\n             data/full_repos/permissive/147974511/src_old,data/full_repos/permissive/147974511/rcon.sv\n             rcon\n             rcon.v\n             rcon.sv\n             obj_dir/rcon\n             obj_dir/rcon.v\n             obj_dir/rcon.sv\n%Error: data/full_repos/permissive/147974511/src_old/singleKeyExpansion.v:24: Cannot find file containing module: \'subByte\'\n   subByte uut2 (.state(stp1) , .state_out(stp2));\n   ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/147974511/src_old/singleKeyExpansion.v:29: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 34 bits.\n                                                                                    : ... In instance singleKeyExpansion\n   stp1  <= { keyInput[25:0] , keyInput[31:24] }; \n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module singleKeyExpansion( 
  input  [127:0] keyInput ,
	input clk,
	input enable,
	input reset,
	input [3:0] keyNum,
  output  reg [127:0] keyOutput);
  
	reg [31:0] stp1 ;
  wire [31:0] stp2 ;
  wire [31:0]Rcon ;

 	 rcon uut1 (.r(keyNum),.rcon(Rcon));
   subByte uut2 (.state(stp1) , .state_out(stp2));
	 
	 always @(negedge clk)
	 begin 
		if(enable)
			stp1 	<= { keyInput[25:0] , keyInput[31:24] }; 
	 end 

always @(posedge clk) 
 begin
	if ( reset == 1 )
	begin 
	keyOutput = 0;

	end 
	else 
	begin 
		if(enable)
			begin 
				keyOutput[127:96] = keyInput[127:96] ^ stp2 ^ Rcon; 	
				keyOutput[95:64] = keyInput[95:64] ^ keyOutput[127:96];
				keyOutput[63:32] = keyInput[63:32] ^ keyOutput[95:64];
				keyOutput[31:0] = keyInput[31:0] ^ keyOutput[63:32];
			end
	end 
end
 endmodule
module singleKeyExpansion( 
  input  [127:0] keyInput ,
	input clk,
	input enable,
	input reset,
	input [3:0] keyNum,
  output  reg [127:0] keyOutput);

  
	reg [31:0] stp1 ;
  wire [31:0] stp2 ;
  wire [31:0]Rcon ;

 	 rcon uut1 (.r(keyNum),.rcon(Rcon));
   subByte uut2 (.state(stp1) , .state_out(stp2));
	 
	 always @(negedge clk)
	 begin 
		if(enable)
			stp1 	<= { keyInput[25:0] , keyInput[31:24] }; 
	 end 

always @(posedge clk) 
 begin
	if ( reset == 1 )
	begin 
	keyOutput = 0;

	end 
	else 
	begin 
		if(enable)
			begin 
				keyOutput[127:96] = keyInput[127:96] ^ stp2 ^ Rcon; 	
				keyOutput[95:64] = keyInput[95:64] ^ keyOutput[127:96];
				keyOutput[63:32] = keyInput[63:32] ^ keyOutput[95:64];
				keyOutput[31:0] = keyInput[31:0] ^ keyOutput[63:32];
			end
	end 
end
 endmodule