data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/uart_rx_6.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/uart_rx_6.v:34: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                              : ... In instance uart_rx_6\n  reg [6:0] M_ctr_d, M_ctr_q = 1\'h0;\n                               ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/uart_rx_6.v:35: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                              : ... In instance uart_rx_6\n  reg [2:0] M_bitCtr_d, M_bitCtr_q = 1\'h0;\n                                     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/uart_rx_6.v:36: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                              : ... In instance uart_rx_6\n  reg [7:0] M_savedData_d, M_savedData_q = 1\'h0;\n                                           ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/uart_rx_6.v:55: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                              : ... In instance uart_rx_6\n        M_bitCtr_d = 1\'h0;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/uart_rx_6.v:56: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                              : ... In instance uart_rx_6\n        M_ctr_d = 1\'h0;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/uart_rx_6.v:64: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                              : ... In instance uart_rx_6\n          M_ctr_d = 1\'h0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/uart_rx_6.v:63: Operator EQ expects 28 bits on the LHS, but LHS\'s VARREF \'M_ctr_q\' generates 7 bits.\n                                                                                                                                                              : ... In instance uart_rx_6\n        if (M_ctr_q == 28\'h0000032) begin\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/uart_rx_6.v:73: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                              : ... In instance uart_rx_6\n          M_ctr_d = 1\'h0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/uart_rx_6.v:70: Operator EQ expects 29 bits on the LHS, but LHS\'s VARREF \'M_ctr_q\' generates 7 bits.\n                                                                                                                                                              : ... In instance uart_rx_6\n        if (M_ctr_q == 29\'h00000063) begin\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/uart_rx_6.v:99: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                              : ... In instance uart_rx_6\n      M_state_q <= 1\'h0;\n                ^~\n%Error: Exiting due to 10 warning(s)\n'
module uart_rx_6 (
    input clk,
    input rst,
    input rx,
    output reg [7:0] data,
    output reg new_data
  );
  
  localparam CLK_FREQ = 26'h2faf080;
  localparam BAUD = 19'h7a120;
  
  
  localparam CLK_PER_BIT = 28'h0000064;
  
  localparam CTR_SIZE = 3'h7;
  
  localparam IDLE_state = 2'd0;
  localparam WAIT_HALF_state = 2'd1;
  localparam WAIT_FULL_state = 2'd2;
  localparam WAIT_HIGH_state = 2'd3;
  
  reg [1:0] M_state_d, M_state_q = IDLE_state;
  reg [6:0] M_ctr_d, M_ctr_q = 1'h0;
  reg [2:0] M_bitCtr_d, M_bitCtr_q = 1'h0;
  reg [7:0] M_savedData_d, M_savedData_q = 1'h0;
  reg M_newData_d, M_newData_q = 1'h0;
  reg M_rxd_d, M_rxd_q = 1'h0;
  
  always @* begin
    M_state_d = M_state_q;
    M_newData_d = M_newData_q;
    M_bitCtr_d = M_bitCtr_q;
    M_savedData_d = M_savedData_q;
    M_rxd_d = M_rxd_q;
    M_ctr_d = M_ctr_q;
    
    M_rxd_d = rx;
    M_newData_d = 1'h0;
    data = M_savedData_q;
    new_data = M_newData_q;
    
    case (M_state_q)
      IDLE_state: begin
        M_bitCtr_d = 1'h0;
        M_ctr_d = 1'h0;
        if (M_rxd_q == 1'h0) begin
          M_state_d = WAIT_HALF_state;
        end
      end
      WAIT_HALF_state: begin
        M_ctr_d = M_ctr_q + 1'h1;
        if (M_ctr_q == 28'h0000032) begin
          M_ctr_d = 1'h0;
          M_state_d = WAIT_FULL_state;
        end
      end
      WAIT_FULL_state: begin
        M_ctr_d = M_ctr_q + 1'h1;
        if (M_ctr_q == 29'h00000063) begin
          M_savedData_d = {M_rxd_q, M_savedData_q[1+6-:7]};
          M_bitCtr_d = M_bitCtr_q + 1'h1;
          M_ctr_d = 1'h0;
          if (M_bitCtr_q == 3'h7) begin
            M_state_d = WAIT_HIGH_state;
            M_newData_d = 1'h1;
          end
        end
      end
      WAIT_HIGH_state: begin
        if (M_rxd_q == 1'h1) begin
          M_state_d = IDLE_state;
        end
      end
      default: begin
        M_state_d = IDLE_state;
      end
    endcase
  end
  
  always @(posedge clk) begin
    M_ctr_q <= M_ctr_d;
    M_bitCtr_q <= M_bitCtr_d;
    M_savedData_q <= M_savedData_d;
    M_newData_q <= M_newData_d;
    M_rxd_q <= M_rxd_d;
    
    if (rst == 1'b1) begin
      M_state_q <= 1'h0;
    end else begin
      M_state_q <= M_state_d;
    end
  end
  
endmodule
module uart_rx_6 (
    input clk,
    input rst,
    input rx,
    output reg [7:0] data,
    output reg new_data
  );

  
  localparam CLK_FREQ = 26'h2faf080;
  localparam BAUD = 19'h7a120;
  
  
  localparam CLK_PER_BIT = 28'h0000064;
  
  localparam CTR_SIZE = 3'h7;
  
  localparam IDLE_state = 2'd0;
  localparam WAIT_HALF_state = 2'd1;
  localparam WAIT_FULL_state = 2'd2;
  localparam WAIT_HIGH_state = 2'd3;
  
  reg [1:0] M_state_d, M_state_q = IDLE_state;
  reg [6:0] M_ctr_d, M_ctr_q = 1'h0;
  reg [2:0] M_bitCtr_d, M_bitCtr_q = 1'h0;
  reg [7:0] M_savedData_d, M_savedData_q = 1'h0;
  reg M_newData_d, M_newData_q = 1'h0;
  reg M_rxd_d, M_rxd_q = 1'h0;
  
  always @* begin
    M_state_d = M_state_q;
    M_newData_d = M_newData_q;
    M_bitCtr_d = M_bitCtr_q;
    M_savedData_d = M_savedData_q;
    M_rxd_d = M_rxd_q;
    M_ctr_d = M_ctr_q;
    
    M_rxd_d = rx;
    M_newData_d = 1'h0;
    data = M_savedData_q;
    new_data = M_newData_q;
    
    case (M_state_q)
      IDLE_state: begin
        M_bitCtr_d = 1'h0;
        M_ctr_d = 1'h0;
        if (M_rxd_q == 1'h0) begin
          M_state_d = WAIT_HALF_state;
        end
      end
      WAIT_HALF_state: begin
        M_ctr_d = M_ctr_q + 1'h1;
        if (M_ctr_q == 28'h0000032) begin
          M_ctr_d = 1'h0;
          M_state_d = WAIT_FULL_state;
        end
      end
      WAIT_FULL_state: begin
        M_ctr_d = M_ctr_q + 1'h1;
        if (M_ctr_q == 29'h00000063) begin
          M_savedData_d = {M_rxd_q, M_savedData_q[1+6-:7]};
          M_bitCtr_d = M_bitCtr_q + 1'h1;
          M_ctr_d = 1'h0;
          if (M_bitCtr_q == 3'h7) begin
            M_state_d = WAIT_HIGH_state;
            M_newData_d = 1'h1;
          end
        end
      end
      WAIT_HIGH_state: begin
        if (M_rxd_q == 1'h1) begin
          M_state_d = IDLE_state;
        end
      end
      default: begin
        M_state_d = IDLE_state;
      end
    endcase
  end
  
  always @(posedge clk) begin
    M_ctr_q <= M_ctr_d;
    M_bitCtr_q <= M_bitCtr_d;
    M_savedData_q <= M_savedData_d;
    M_newData_q <= M_newData_d;
    M_rxd_q <= M_rxd_d;
    
    if (rst == 1'b1) begin
      M_state_q <= 1'h0;
    end else begin
      M_state_q <= M_state_d;
    end
  end
  
endmodule