data/full_repos/permissive/116308238/hdl/ph_finder.v
data/verilator_xmls/f79c6885-8ee8-4df1-8918-6f647c52f0a8.xml
module ph_finder(rxbyteclkhs, reset, din, din_valid, dout, dout_valid, ph_select);


	input wire rxbyteclkhs, reset;
	input wire [15:0] din;
	input wire din_valid;


	output reg [31:0] dout;
	output reg dout_valid;
	output reg ph_select;


	parameter STATE_HALF_PH	= 2'b00;
	parameter STATE_FULL_PH	= 2'b01;
	parameter STATE_BYPASS	= 2'b10;

	reg [7:0] prev_byte1, prev_byte2;
	reg [1:0] state;


	always @(posedge rxbyteclkhs) begin
		if(reset | ~din_valid) begin
			dout <= 32'd0;
			dout_valid <= 1'b0;
			ph_select <= 1'b0;
			prev_byte1 <= 8'd0;
			prev_byte2 <= 8'd0;
			state <= STATE_HALF_PH;
		end
		else begin
			case(state)
				STATE_HALF_PH: begin
					prev_byte1 <= din[15:8];
					prev_byte2 <= din[7:0];
					state <= STATE_FULL_PH;
				end

				STATE_FULL_PH: begin
					dout <= {din[7:0], din[15:8], prev_byte2, prev_byte1};
					dout_valid <= 1'b1;
					ph_select <= 1'b1;
					state <= STATE_BYPASS;
				end

				STATE_BYPASS: begin
					dout <= {din, 16'd0};
					ph_select <= 1'b0;
					state <= STATE_BYPASS;
				end

				default: begin
					dout <= 32'd0;
					dout_valid <= 1'b0;
					ph_select <= 1'b0;
				end
			endcase
		end
	end
endmodule
module ph_finder(rxbyteclkhs, reset, din, din_valid, dout, dout_valid, ph_select);



	input wire rxbyteclkhs, reset;
	input wire [15:0] din;
	input wire din_valid;


	output reg [31:0] dout;
	output reg dout_valid;
	output reg ph_select;


	parameter STATE_HALF_PH	= 2'b00;
	parameter STATE_FULL_PH	= 2'b01;
	parameter STATE_BYPASS	= 2'b10;

	reg [7:0] prev_byte1, prev_byte2;
	reg [1:0] state;


	always @(posedge rxbyteclkhs) begin
		if(reset | ~din_valid) begin
			dout <= 32'd0;
			dout_valid <= 1'b0;
			ph_select <= 1'b0;
			prev_byte1 <= 8'd0;
			prev_byte2 <= 8'd0;
			state <= STATE_HALF_PH;
		end
		else begin
			case(state)
				STATE_HALF_PH: begin
					prev_byte1 <= din[15:8];
					prev_byte2 <= din[7:0];
					state <= STATE_FULL_PH;
				end

				STATE_FULL_PH: begin
					dout <= {din[7:0], din[15:8], prev_byte2, prev_byte1};
					dout_valid <= 1'b1;
					ph_select <= 1'b1;
					state <= STATE_BYPASS;
				end

				STATE_BYPASS: begin
					dout <= {din, 16'd0};
					ph_select <= 1'b0;
					state <= STATE_BYPASS;
				end

				default: begin
					dout <= 32'd0;
					dout_valid <= 1'b0;
					ph_select <= 1'b0;
				end
			endcase
		end
	end
endmodule