data/full_repos/permissive/117756790/blinkers/variable_blinker.v
 line:46: before: "/"
1: b'%Warning-WIDTH: data/full_repos/permissive/117756790/blinkers/variable_blinker.v:32: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                   : ... In instance variable_blinker\n    out_counter_q <= 9\'b0;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module variable_blinker(
  input clk,
  input rst,
  input [9:0]rate,
  output blink
);

reg [16:0] counter_d, counter_q;
reg out;
wire out_n = ~out;

always @(counter_q) begin
  counter_d = counter_q + 1'b1;
end

reg [9:0] out_counter_d, out_counter_q;

always @(negedge counter_q[16]) begin
  out_counter_d = out_counter_q + 1'b1;
end

always @(posedge clk) begin
  if (rst) begin
    counter_q <= 17'b0;
    out_counter_q <= 9'b0;
    out <= 1'b0;
  end else begin
    if (out_counter_q >= rate) begin
      out <= ~out_n;
      out_counter_q <= 10'b0;
    end else begin
      out_counter_q <= out_counter_d;
    end

    counter_q <= counter_d;
  end
end

endmodule
module variable_blinker(
  input clk,
  input rst,
  input [9:0]rate,
  output blink
);


reg [16:0] counter_d, counter_q;
reg out;
wire out_n = ~out;

always @(counter_q) begin
  counter_d = counter_q + 1'b1;
end

reg [9:0] out_counter_d, out_counter_q;

always @(negedge counter_q[16]) begin
  out_counter_d = out_counter_q + 1'b1;
end

always @(posedge clk) begin
  if (rst) begin
    counter_q <= 17'b0;
    out_counter_q <= 9'b0;
    out <= 1'b0;
  end else begin
    if (out_counter_q >= rate) begin
      out <= ~out_n;
      out_counter_q <= 10'b0;
    end else begin
      out_counter_q <= out_counter_d;
    end

    counter_q <= counter_d;
  end
end

endmodule