data/full_repos/permissive/209997170/Sound/pwm_tutorial/source/wave.v
 line:9: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/pwm_tutorial/source/wave.v:25: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                                        : ... In instance wave\n      led[i] = acmp > ctr_q[7:0];\n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module wave #(
    parameter CTR_LEN = 25
  )(
    input wire clk,
    input wire rst,
    output reg[7:0] led
  );
 
  reg[CTR_LEN-1:0] ctr_d, ctr_q = {CTR_LEN{1'b0}};
  reg[3:0] i;
  reg[7:0] acmp;
  reg[8:0] result;
 
  always @(ctr_q) begin
    ctr_d = ctr_q + 1'b1;
 
    for (i = 0; i < 8; i = i + 1) begin
      result = ctr_q[CTR_LEN-1:CTR_LEN-9] + i * 8'd64;
 
      if (result[8])
        acmp = ~result[7:0];
      else
        acmp = result[7:0];
 
      led[i] = acmp > ctr_q[7:0];
    end
  end
 
  always @(posedge clk) begin
    if (rst) begin
      ctr_q <= {CTR_LEN{1'b0}};
    end else begin
      ctr_q <= ctr_d;
    end
  end
 
endmodule
module wave #(
    parameter CTR_LEN = 25
  )(
    input wire clk,
    input wire rst,
    output reg[7:0] led
  );

 
  reg[CTR_LEN-1:0] ctr_d, ctr_q = {CTR_LEN{1'b0}};
  reg[3:0] i;
  reg[7:0] acmp;
  reg[8:0] result;
 
  always @(ctr_q) begin
    ctr_d = ctr_q + 1'b1;
 
    for (i = 0; i < 8; i = i + 1) begin
      result = ctr_q[CTR_LEN-1:CTR_LEN-9] + i * 8'd64;
 
      if (result[8])
        acmp = ~result[7:0];
      else
        acmp = result[7:0];
 
      led[i] = acmp > ctr_q[7:0];
    end
  end
 
  always @(posedge clk) begin
    if (rst) begin
      ctr_q <= {CTR_LEN{1'b0}};
    end else begin
      ctr_q <= ctr_d;
    end
  end
 
endmodule