data/full_repos/permissive/185658197/src/step-3/verilog/multiplier.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/185658197/src/step-3/verilog/multiplier.v:83: Cell has missing pin: \'c\'\n  Subtractor #(.bits(16)) final_subtractor (\n                          ^~~~~~~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ROM #(parameter address_bits = 1, file = "") (
  input [(address_bits-1):0] address,
  output [15:0] data
);
  reg [15:0] memory [0:(2**address_bits-1)];  
  assign data = memory[address];

  initial
    $readmemh(file, memory); 
endmodule
module ROM #(parameter address_bits = 1, file = "") (
  input [(address_bits-1):0] address,
  output [15:0] data
);

  reg [15:0] memory [0:(2**address_bits-1)];  
  assign data = memory[address];

  initial
    $readmemh(file, memory); 
endmodule