data/full_repos/permissive/136422019/src/not32.v
data/verilator_xmls/69f9d0d5-f2d6-4061-bdb7-056e659d5e0d.xml
module not32(
	output wire [31:0] out,
	input wire [31:0] in_a
);

	assign out = ~in_a;
	
endmodule
module not32(
	output wire [31:0] out,
	input wire [31:0] in_a
);


	assign out = ~in_a;
	
endmodule