data/full_repos/permissive/174369527/verilator_test/02-Maskbus/maskbus.v
data/verilator_xmls/bd283724-5f79-469d-80aa-1d1ee2c77e4a.xml
module maskbus(i_sw, o_led);
	input [8:0] i_sw;
	output [8:0] o_led;

	wire [8:0] w_internal;

	assign w_internal = 9'h87;
	assign o_led = i_sw ^ w_internal;
endmodule
module maskbus(i_sw, o_led);

	input [8:0] i_sw;
	output [8:0] o_led;

	wire [8:0] w_internal;

	assign w_internal = 9'h87;
	assign o_led = i_sw ^ w_internal;
endmodule