data/full_repos/permissive/186443491/view/gold_miner.v
 line:272: before: "."
1: b'%Warning-MULTITOP: data/full_repos/permissive/186443491/view/gold_miner.v:411: Multiple top level modules\n                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                             : ... Top module \'gold_miner\'\nmodule gold_miner(\n       ^~~~~~~~~~\n                                                                             : ... Top module \'hex_decoder\'\nmodule hex_decoder(hex_digit, segments);\n       ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/186443491/view/gold_miner.v:97: Signal definition not found, creating implicitly: \'plot\'\n   .plot(plot), \n         ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/186443491/view/gold_miner.v:99: Signal definition not found, creating implicitly: \'background\'\n   .background(background),\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/186443491/view/gold_miner.v:256: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/186443491/view,data/full_repos/permissive/186443491/vga_adapter\n             data/full_repos/permissive/186443491/view,data/full_repos/permissive/186443491/vga_adapter.v\n             data/full_repos/permissive/186443491/view,data/full_repos/permissive/186443491/vga_adapter.sv\n             vga_adapter\n             vga_adapter.v\n             vga_adapter.sv\n             obj_dir/vga_adapter\n             obj_dir/vga_adapter.v\n             obj_dir/vga_adapter.sv\n%Error: data/full_repos/permissive/186443491/view/gold_miner.v:280: Cannot find file containing module: \'view\'\n view view(\n ^~~~\n%Error: data/full_repos/permissive/186443491/view/gold_miner.v:320: Cannot find file containing module: \'PS2_Controller\'\n PS2_Controller keyboard(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/186443491/view/gold_miner.v:386: Cannot find file containing module: \'audio\'\n audio audio0(\n ^~~~~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n'
module gold_miner(
		SW,
		KEY,
		CLOCK_50,
		VGA_CLK,
		VGA_HS,
		VGA_VS,
		VGA_BLANK_N,
		VGA_SYNC_N,
		VGA_R,
		VGA_G,
		VGA_B,
		PS2_CLK,
		PS2_DAT,
		FPGA_I2C_SCLK,
		FPGA_I2C_SDAT,
		AUD_ADCDAT,

		AUD_BCLK,
		AUD_ADCLRCK,
		AUD_DACLRCK,

		AUD_XCK,
		AUD_DACDAT,

		LEDR,
		HEX0,
		HEX1,
		HEX2,
		HEX3,
		HEX4,
		HEX5
		);
		
		input [9:0]SW;
		input	[3:0]KEY;
		input	CLOCK_50;

		input				AUD_ADCDAT;

		inout PS2_CLK, PS2_DAT;

		inout				AUD_BCLK;
		inout				AUD_ADCLRCK;
		inout				AUD_DACLRCK;

		inout				FPGA_I2C_SDAT;


		output				AUD_XCK;
		output				AUD_DACDAT;
		output				FPGA_I2C_SCLK;
		
		output			VGA_CLK;
		output			VGA_HS;
		output			VGA_VS;
		output			VGA_BLANK_N;
		output			VGA_SYNC_N;
		output	[7:0]	VGA_R;
		output	[7:0]	VGA_G;
		output	[7:0]	VGA_B;
		output [9:0] 	LEDR;

		output [6:0]HEX0;
		output [6:0]HEX1;
		output [6:0]HEX2;
		output [6:0]HEX3;
		output [6:0]HEX4;
		output [6:0]HEX5;
		
		wire resetn;
		assign resetn = KEY[0];

		
		fill f0
		(
			.CLOCK_50(CLOCK_50),

			.plot(plot), 
			.resetn(resetn),
			.background(background),

			.SW(SW),
			.KEY(KEY),

			.VGA_CLK(VGA_CLK),
			.VGA_HS(VGA_HS),
			.VGA_VS(VGA_VS),
			.VGA_BLANK_N(VGA_BLANK_N),
			.VGA_SYNC_N(VGA_SYNC_N),
			.VGA_R(VGA_R),
			.VGA_G(VGA_G),
			.VGA_B(VGA_B),
			.PS2_CLK(PS2_CLK),
			.PS2_DAT(PS2_DAT),
			
			.AUD_ADCDAT(AUD_ADCDAT),


			.AUD_BCLK(AUD_BCLK),
			.AUD_ADCLRCK(AUD_ADCLRCK),
			.AUD_DACLRCK(AUD_DACLRCK),

			.FPGA_I2C_SDAT(FPGA_I2C_SDAT),


			.AUD_XCK(AUD_XCK),
			.AUD_DACDAT(AUD_DACDAT),

			.FPGA_I2C_SCLK(FPGA_I2C_SCLK),

			.LEDR(LEDR),
			.HEX0(HEX0),
			.HEX1(HEX1),
			.HEX2(HEX2),
			.HEX3(HEX3),
			.HEX4(HEX4),
			.HEX5(HEX5)

		);

		

	endmodule
module gold_miner(
		SW,
		KEY,
		CLOCK_50,
		VGA_CLK,
		VGA_HS,
		VGA_VS,
		VGA_BLANK_N,
		VGA_SYNC_N,
		VGA_R,
		VGA_G,
		VGA_B,
		PS2_CLK,
		PS2_DAT,
		FPGA_I2C_SCLK,
		FPGA_I2C_SDAT,
		AUD_ADCDAT,

		AUD_BCLK,
		AUD_ADCLRCK,
		AUD_DACLRCK,

		AUD_XCK,
		AUD_DACDAT,

		LEDR,
		HEX0,
		HEX1,
		HEX2,
		HEX3,
		HEX4,
		HEX5
		);

		
		input [9:0]SW;
		input	[3:0]KEY;
		input	CLOCK_50;

		input				AUD_ADCDAT;

		inout PS2_CLK, PS2_DAT;

		inout				AUD_BCLK;
		inout				AUD_ADCLRCK;
		inout				AUD_DACLRCK;

		inout				FPGA_I2C_SDAT;


		output				AUD_XCK;
		output				AUD_DACDAT;
		output				FPGA_I2C_SCLK;
		
		output			VGA_CLK;
		output			VGA_HS;
		output			VGA_VS;
		output			VGA_BLANK_N;
		output			VGA_SYNC_N;
		output	[7:0]	VGA_R;
		output	[7:0]	VGA_G;
		output	[7:0]	VGA_B;
		output [9:0] 	LEDR;

		output [6:0]HEX0;
		output [6:0]HEX1;
		output [6:0]HEX2;
		output [6:0]HEX3;
		output [6:0]HEX4;
		output [6:0]HEX5;
		
		wire resetn;
		assign resetn = KEY[0];

		
		fill f0
		(
			.CLOCK_50(CLOCK_50),

			.plot(plot), 
			.resetn(resetn),
			.background(background),

			.SW(SW),
			.KEY(KEY),

			.VGA_CLK(VGA_CLK),
			.VGA_HS(VGA_HS),
			.VGA_VS(VGA_VS),
			.VGA_BLANK_N(VGA_BLANK_N),
			.VGA_SYNC_N(VGA_SYNC_N),
			.VGA_R(VGA_R),
			.VGA_G(VGA_G),
			.VGA_B(VGA_B),
			.PS2_CLK(PS2_CLK),
			.PS2_DAT(PS2_DAT),
			
			.AUD_ADCDAT(AUD_ADCDAT),


			.AUD_BCLK(AUD_BCLK),
			.AUD_ADCLRCK(AUD_ADCLRCK),
			.AUD_DACLRCK(AUD_DACLRCK),

			.FPGA_I2C_SDAT(FPGA_I2C_SDAT),


			.AUD_XCK(AUD_XCK),
			.AUD_DACDAT(AUD_DACDAT),

			.FPGA_I2C_SCLK(FPGA_I2C_SCLK),

			.LEDR(LEDR),
			.HEX0(HEX0),
			.HEX1(HEX1),
			.HEX2(HEX2),
			.HEX3(HEX3),
			.HEX4(HEX4),
			.HEX5(HEX5)

		);

		

	endmodule