data/full_repos/permissive/206842334/src/iterator.v
1: b'%Error: data/full_repos/permissive/206842334/src/iterator.v:2: Cannot find include file: parameters.v\n`include "parameters.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206842334/src,data/full_repos/permissive/206842334/parameters.v\n             data/full_repos/permissive/206842334/src,data/full_repos/permissive/206842334/parameters.v.v\n             data/full_repos/permissive/206842334/src,data/full_repos/permissive/206842334/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: data/full_repos/permissive/206842334/src/iterator.v:20: Define or directive not defined: \'`BYTE\'\n parameter [`BYTE-1:0] CONV_DIM_IMG    = 32;  \n            ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:21: Define or directive not defined: \'`BYTE\'\n parameter [`BYTE-1:0] CONV_DIM_OUT    = 32;  \n            ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:22: Define or directive not defined: \'`BYTE\'\n parameter [`BYTE-1:0] CONV_DIM_KERNEL = 5;   \n            ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:23: Define or directive not defined: \'`BYTE\'\n parameter [`BYTE-1:0] CONV_OUT_CH     = 32;  \n            ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:24: Define or directive not defined: \'`BYTE\'\n parameter [`BYTE-1:0] CONV_DIM_CH     = 3;\n            ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:25: Define or directive not defined: \'`BYTE\'\n parameter [`BYTE-1:0] STRIDE          = 1;\n            ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:26: Define or directive not defined: \'`BYTE\'\n parameter [`BYTE-1:0] PADDING         = 2;\n            ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:35: Define or directive not defined: \'`BYTE\'\n output reg [`BYTE-1:0] i;\n             ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:36: Define or directive not defined: \'`BYTE\'\n output reg [`BYTE-1:0] j; \n             ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:37: Define or directive not defined: \'`BYTE\'\n output reg [`BYTE-1:0] k; \n             ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:38: Define or directive not defined: \'`BYTE\'\n output reg [`BYTE-1:0] m; \n             ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:39: Define or directive not defined: \'`BYTE\'\n output reg [`BYTE-1:0] n; \n             ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:40: Define or directive not defined: \'`BYTE\'\n output reg [`BYTE-1:0] l; \n             ^~~~~\n%Error: data/full_repos/permissive/206842334/src/iterator.v:41: Define or directive not defined: \'`BYTE\'\n output signed [`BYTE-1:0]  in_row, in_col;\n                ^~~~~\n%Error: Exiting due to 15 error(s)\n'
module iterator(
	clk,
	reset,
	en_ctrl, 
	i, 
	j, 
	k,
	l,
	m, 
	n,
	en_sum,
	en_save,
	fin_r,
	in_row,
	in_col
);
	parameter [`BYTE-1:0] CONV_DIM_IMG    = 32;
	parameter [`BYTE-1:0] CONV_DIM_OUT    = 32;
	parameter [`BYTE-1:0] CONV_DIM_KERNEL = 5;
	parameter [`BYTE-1:0] CONV_OUT_CH     = 32;
	parameter [`BYTE-1:0] CONV_DIM_CH     = 3;
	parameter [`BYTE-1:0] STRIDE          = 1;
	parameter [`BYTE-1:0] PADDING         = 2;
	
	input clk;
	input en_ctrl;
	input reset;

	output en_sum;
	output en_save;
	output reg fin_r;
	output reg [`BYTE-1:0] i;
	output reg [`BYTE-1:0] j; 
	output reg [`BYTE-1:0] k; 
	output reg [`BYTE-1:0] m; 
	output reg [`BYTE-1:0] n; 
	output reg [`BYTE-1:0] l; 
	output signed [`BYTE-1:0]  in_row, in_col;

	reg fin, finish;
	
	wire cond;
	assign in_row = (STRIDE * j) + m - PADDING;
	assign in_col = (STRIDE * k) + n - PADDING;
	assign cond   = en_ctrl & ~fin_r;
	assign en_sum = (en_ctrl && (l < CONV_DIM_CH) && (in_row >= 8'd0 && in_col >= 8'd0 && in_row < CONV_DIM_IMG && in_col < CONV_DIM_IMG)) ? 1'b1 : 1'b0;
	assign en_save = (m > 8'd0 || n > 8'd0) ? 1'b0 : (j < 8'd2) ? 1'd1 : (l == 8'd0) ? 1'd1 : 1'b0; 
	


	always @(posedge clk) begin
		if(reset) begin
			fin <= 0;
			fin_r <= 0;
		end else begin
			fin <= finish;
			fin_r <= fin;
		end
	end
	
	always @(posedge clk) begin
		if(reset) begin
			i <= 0;
			j <= 0;
			k <= 0;
			m <= 0;
			n <= 0;
			finish <= 0;
		end else if(cond) begin
		    if(en_sum) begin
				l <= l + 8'd1;
			end else begin
				l <= 0;
				n <= n + 8'd1;
				if(n == (CONV_DIM_KERNEL-1)) begin
			    	n <= 8'b0;
			    	m <= m + 8'b1;
			    	if(m == (CONV_DIM_KERNEL-1)) begin
			    		m <= 0;
			       		k <= k + 8'b1;
			       		if(k == (CONV_DIM_OUT-1)) begin
			           		k <= 0;
			           		j <= j + 8'b1;
			           		if(j == (CONV_DIM_OUT-1)) begin
				           		j <= 0;
				           		i <= i + 8'b1;
				           		if(i == (CONV_OUT_CH-1)) begin
				            		i <= 0;
					          		finish <= 1;
				           		end
				   	    	end
			           	end
		           	end
			    end
			end
		end
	end

endmodule
module iterator(
	clk,
	reset,
	en_ctrl, 
	i, 
	j, 
	k,
	l,
	m, 
	n,
	en_sum,
	en_save,
	fin_r,
	in_row,
	in_col
);

	parameter [`BYTE-1:0] CONV_DIM_IMG    = 32;
	parameter [`BYTE-1:0] CONV_DIM_OUT    = 32;
	parameter [`BYTE-1:0] CONV_DIM_KERNEL = 5;
	parameter [`BYTE-1:0] CONV_OUT_CH     = 32;
	parameter [`BYTE-1:0] CONV_DIM_CH     = 3;
	parameter [`BYTE-1:0] STRIDE          = 1;
	parameter [`BYTE-1:0] PADDING         = 2;
	
	input clk;
	input en_ctrl;
	input reset;

	output en_sum;
	output en_save;
	output reg fin_r;
	output reg [`BYTE-1:0] i;
	output reg [`BYTE-1:0] j; 
	output reg [`BYTE-1:0] k; 
	output reg [`BYTE-1:0] m; 
	output reg [`BYTE-1:0] n; 
	output reg [`BYTE-1:0] l; 
	output signed [`BYTE-1:0]  in_row, in_col;

	reg fin, finish;
	
	wire cond;
	assign in_row = (STRIDE * j) + m - PADDING;
	assign in_col = (STRIDE * k) + n - PADDING;
	assign cond   = en_ctrl & ~fin_r;
	assign en_sum = (en_ctrl && (l < CONV_DIM_CH) && (in_row >= 8'd0 && in_col >= 8'd0 && in_row < CONV_DIM_IMG && in_col < CONV_DIM_IMG)) ? 1'b1 : 1'b0;
	assign en_save = (m > 8'd0 || n > 8'd0) ? 1'b0 : (j < 8'd2) ? 1'd1 : (l == 8'd0) ? 1'd1 : 1'b0; 
	


	always @(posedge clk) begin
		if(reset) begin
			fin <= 0;
			fin_r <= 0;
		end else begin
			fin <= finish;
			fin_r <= fin;
		end
	end
	
	always @(posedge clk) begin
		if(reset) begin
			i <= 0;
			j <= 0;
			k <= 0;
			m <= 0;
			n <= 0;
			finish <= 0;
		end else if(cond) begin
		    if(en_sum) begin
				l <= l + 8'd1;
			end else begin
				l <= 0;
				n <= n + 8'd1;
				if(n == (CONV_DIM_KERNEL-1)) begin
			    	n <= 8'b0;
			    	m <= m + 8'b1;
			    	if(m == (CONV_DIM_KERNEL-1)) begin
			    		m <= 0;
			       		k <= k + 8'b1;
			       		if(k == (CONV_DIM_OUT-1)) begin
			           		k <= 0;
			           		j <= j + 8'b1;
			           		if(j == (CONV_DIM_OUT-1)) begin
				           		j <= 0;
				           		i <= i + 8'b1;
				           		if(i == (CONV_OUT_CH-1)) begin
				            		i <= 0;
					          		finish <= 1;
				           		end
				   	    	end
			           	end
		           	end
			    end
			end
		end
	end

endmodule