data/full_repos/permissive/143278/ivltests/attrib02_port_decl.v
data/verilator_xmls/87d9411b-5e3a-41de-8764-e1143742f121.xml
module foo(clk, rst, inp, out);
  (* this_is_the_master_clock *)
  input  wire clk;
  input  wire rst;
  input  wire inp;
  output wire out;

  bar bar_instance (clk, rst, inp, out);

  initial begin
    $display("PASSED");
  end

endmodule
module foo(clk, rst, inp, out);

  (* this_is_the_master_clock *)
  input  wire clk;
  input  wire rst;
  input  wire inp;
  output wire out;

  bar bar_instance (clk, rst, inp, out);

  initial begin
    $display("PASSED");
  end

endmodule