data/full_repos/permissive/156966470/hdl/filter/jt49_dly.v
 line:67: before: "/"
data/verilator_xmls/a4d7a781-e82e-41b1-9365-2492f9105a3c.xml
module jt49_dly #(parameter dw=8, depth=10)(
    input                clk,
    input                cen,
    input                rst,
    input         [7:0]  din,
    output reg    [7:0]  dout,
    output reg    [7:0]  pre_dout

);

reg [depth-1:0] rdpos, wrpos;



reg [dw-1:0] ram[0:2**depth-1];
always @(posedge clk) 
    if(rst)
        pre_dout <= {dw{1'b0}};
    else begin
        pre_dout <= ram[rdpos];
        if( cen ) ram[wrpos] <= din;
    end

`ifdef SIMULATION
integer k;
initial begin
    for(k=0;k<=2**depth-1;k=k+1)
        ram[k] = 0;
end
`endif

always @(posedge clk)
    if( rst ) begin
        rdpos <= { {depth-1{1'b0}}, 1'b1};
        wrpos <= {depth{1'b1}};
        dout <= {dw{1'b0}};
    end else if(cen) begin
        dout <= pre_dout;
        rdpos <= rdpos+1'b1;
        wrpos <= wrpos+1'b1;
    end

endmodule
module jt49_dly #(parameter dw=8, depth=10)(
    input                clk,
    input                cen,
    input                rst,
    input         [7:0]  din,
    output reg    [7:0]  dout,
    output reg    [7:0]  pre_dout

);


reg [depth-1:0] rdpos, wrpos;



reg [dw-1:0] ram[0:2**depth-1];
always @(posedge clk) 
    if(rst)
        pre_dout <= {dw{1'b0}};
    else begin
        pre_dout <= ram[rdpos];
        if( cen ) ram[wrpos] <= din;
    end

`ifdef SIMULATION
integer k;
initial begin
    for(k=0;k<=2**depth-1;k=k+1)
        ram[k] = 0;
end
`endif

always @(posedge clk)
    if( rst ) begin
        rdpos <= { {depth-1{1'b0}}, 1'b1};
        wrpos <= {depth{1'b1}};
        dout <= {dw{1'b0}};
    end else if(cen) begin
        dout <= pre_dout;
        rdpos <= rdpos+1'b1;
        wrpos <= wrpos+1'b1;
    end

endmodule