data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/dm.v
data/verilator_xmls/e55a7344-6c99-4267-8804-200b9928185f.xml
module dm(
    input wire[31:0] dm_address_32,
    input wire[31:0] dm_w_data,
    input wire dm_we,
    input wire clk,

    output wire[31:0] dm_r_data
    );


    reg[31:0] dm[1023:0];
    wire[9:0] dm_address_10;

    assign dm_address_10 = dm_address_32[11:2];
    assign dm_r_data = dm[dm_address_10];

    always @ (posedge clk) begin
        if (dm_we) begin
            dm[dm_address_10] <= dm_w_data;
        end
    end


endmodule
module dm(
    input wire[31:0] dm_address_32,
    input wire[31:0] dm_w_data,
    input wire dm_we,
    input wire clk,

    output wire[31:0] dm_r_data
    );



    reg[31:0] dm[1023:0];
    wire[9:0] dm_address_10;

    assign dm_address_10 = dm_address_32[11:2];
    assign dm_r_data = dm[dm_address_10];

    always @ (posedge clk) begin
        if (dm_we) begin
            dm[dm_address_10] <= dm_w_data;
        end
    end


endmodule