data/full_repos/permissive/143278/ivltests/pr1958801.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1958801.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1958801.v:12: Operator GTES expects 32 bits on the RHS, but RHS\'s VARREF \'in01\' generates 1 bits.\n                                                                         : ... In instance x.inst\n    assign out00 = ( in00 >= in01 );\n                          ^~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module x;

    reg signed [31:0] a;
    reg signed b;
    wire c;

    s_cmpGe #(32, 1) inst(a, b, c);

    initial
    begin
        b = 0;
        a = -1;

        #1;

        $display("%d >= %d = %d", a, b, c);
        if (c !== 0) begin
	   $display("FAILED");
	   $finish;
	end

        $display("PASSED");
    end

endmodule
module x;


    reg signed [31:0] a;
    reg signed b;
    wire c;

    s_cmpGe #(32, 1) inst(a, b, c);

    initial
    begin
        b = 0;
        a = -1;

        #1;

        $display("%d >= %d = %d", a, b, c);
        if (c !== 0) begin
	   $display("FAILED");
	   $finish;
	end

        $display("PASSED");
    end

endmodule