data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_baud_rate_gen.v
 line:36: before: "$"
1: b'%Error: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_baud_rate_gen.v:36: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_baud_rate_gen.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #0\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_baud_rate_gen.v:37: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_baud_rate_gen.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_baud_rate_gen.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_baud_rate_gen.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #200\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_baud_rate_gen.v:50: Unsupported: Ignoring delay on this delayed statement.\n    always #1 i_clk_01 = ~i_clk_01;\n           ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_baud_rate_gen();
    

  localparam    BAUDRATE_DIVISOR_01         = 9;
  localparam    BAUDRATE_DIVISOR_BITS_01    = 4;


  reg i_clk_01;
  reg reset_01;

  wire o_tick_01;
  
    initial begin
        #0
        $dumpfile("dump.vcd");
        $dumpvars(1);

        reset_01 = 1;
        i_clk_01 = 0;
        #10
        reset_01 = 0;
        #10
        reset_01 = 1;
        
        #200
        $finish;
    end
    
    always #1 i_clk_01 = ~i_clk_01;
    
    baud_rate_gen
    #(
    .BAUDRATE_DIVISOR       (BAUDRATE_DIVISOR_01),
    .BAUDRATE_DIVISOR_BITS  (BAUDRATE_DIVISOR_BITS_01)
    )
    
    u_baud_rate_gen_01
    (
    .i_clk (i_clk_01),
    .i_reset (reset_01),
    .o_tick (o_tick_01)
    );

endmodule
module tb_baud_rate_gen();

    

  localparam    BAUDRATE_DIVISOR_01         = 9;
  localparam    BAUDRATE_DIVISOR_BITS_01    = 4;


  reg i_clk_01;
  reg reset_01;

  wire o_tick_01;
  
    initial begin
        #0
        $dumpfile("dump.vcd");
        $dumpvars(1);

        reset_01 = 1;
        i_clk_01 = 0;
        #10
        reset_01 = 0;
        #10
        reset_01 = 1;
        
        #200
        $finish;
    end
    
    always #1 i_clk_01 = ~i_clk_01;
    
    baud_rate_gen
    #(
    .BAUDRATE_DIVISOR       (BAUDRATE_DIVISOR_01),
    .BAUDRATE_DIVISOR_BITS  (BAUDRATE_DIVISOR_BITS_01)
    )
    
    u_baud_rate_gen_01
    (
    .i_clk (i_clk_01),
    .i_reset (reset_01),
    .o_tick (o_tick_01)
    );

endmodule