data/full_repos/permissive/210737016/wam_hrd.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/210737016/wam_hrd.v:81: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'wam_hrd\'\nmodule wam_hrd (             \n       ^~~~~~~\n                                                                    : ... Top module \'wam_par\'\nmodule wam_par (             \n       ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module wam_tch (
    input wire clk_19,
    input wire btn,
    output reg tch
    );

    reg  btn_pre;
    wire btn_edg;
    reg  [3:0] btn_cnt;

    always @(posedge clk_19)
        btn_pre <= btn;
    assign btn_edg = (~btn_pre) & (btn);

    always @ (posedge clk_19) begin
        if (btn_cnt > 0) begin
            if (btn_cnt > 4'b0100) begin
                btn_cnt <= 4'b0000;
                tch <= 1;
            end
            else begin
                if (btn_edg) begin
                    btn_cnt <= 0;
                end
                else begin
                    btn_cnt <= btn_cnt + 1;
                end
            end
        end
        else begin
            tch <= 0;
            if (btn_edg) begin
                btn_cnt <= 4'b0001;
            end
        end
    end
endmodule
module wam_tch (
    input wire clk_19,
    input wire btn,
    output reg tch
    );


    reg  btn_pre;
    wire btn_edg;
    reg  [3:0] btn_cnt;

    always @(posedge clk_19)
        btn_pre <= btn;
    assign btn_edg = (~btn_pre) & (btn);

    always @ (posedge clk_19) begin
        if (btn_cnt > 0) begin
            if (btn_cnt > 4'b0100) begin
                btn_cnt <= 4'b0000;
                tch <= 1;
            end
            else begin
                if (btn_edg) begin
                    btn_cnt <= 0;
                end
                else begin
                    btn_cnt <= btn_cnt + 1;
                end
            end
        end
        else begin
            tch <= 0;
            if (btn_edg) begin
                btn_cnt <= 4'b0001;
            end
        end
    end
endmodule