data/full_repos/permissive/175132042/behavioral/wb_intercon/bench/orpsoc_tb.v
 line:33: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_intercon/bench/orpsoc_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n   always #5 wb_clk <= ~wb_clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_intercon/bench/orpsoc_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #100 wb_mux_rst <= 0;\n      ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_intercon/bench/orpsoc_tb.v:32: syntax error, unexpected \'@\'\n      @(posedge wb_mux_done);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_intercon/bench/orpsoc_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #100 $display("==wb_mux tests done==");\n      ^\n%Error: data/full_repos/permissive/175132042/behavioral/wb_intercon/bench/orpsoc_tb.v:38: syntax error, unexpected \'@\'\n      @(posedge wb_arb_done);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_intercon/bench/orpsoc_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #100 $display("==wb_arbiter tests done==");\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/behavioral/wb_intercon/bench/orpsoc_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #3 $finish;\n      ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module orpsoc_tb;

   localparam WB_ARB_NUM_MASTERS = 5;
   
   reg	   wb_clk = 1'b1;

   reg	   wb_mux_rst = 1'b1;
   wire    wb_mux_done;
   
   reg	   wb_arb_rst = 1'b1;
   wire    wb_arb_done;

   vlog_tb_utils vlog_tb_utils0();

   wb_mux_tb
   wb_mux_tb0
     (.wb_clk_i (wb_clk),
      .wb_rst_i (wb_mux_rst),
      .done     (wb_mux_done));
   
   wb_arbiter_tb
     #(.NUM_MASTERS (WB_ARB_NUM_MASTERS))
   wb_arbiter_tb0
     (.wb_clk_i (wb_clk),
      .wb_rst_i (wb_arb_rst),
      .done     (wb_arb_done));

   always #5 wb_clk <= ~wb_clk;
   initial begin
      $display("==Running wb_mux tests==");
      #100 wb_mux_rst <= 0;
      @(posedge wb_mux_done);
      #100 $display("==wb_mux tests done==");
      wb_mux_rst <= 1;

      $display("==Running wb_arbiter tests==");
      wb_arb_rst <= 0;
      @(posedge wb_arb_done);
      #100 $display("==wb_arbiter tests done==");
      wb_arb_rst <= 1;

      #3 $finish;
   end
      
   
endmodule
module orpsoc_tb;


   localparam WB_ARB_NUM_MASTERS = 5;
   
   reg	   wb_clk = 1'b1;

   reg	   wb_mux_rst = 1'b1;
   wire    wb_mux_done;
   
   reg	   wb_arb_rst = 1'b1;
   wire    wb_arb_done;

   vlog_tb_utils vlog_tb_utils0();

   wb_mux_tb
   wb_mux_tb0
     (.wb_clk_i (wb_clk),
      .wb_rst_i (wb_mux_rst),
      .done     (wb_mux_done));
   
   wb_arbiter_tb
     #(.NUM_MASTERS (WB_ARB_NUM_MASTERS))
   wb_arbiter_tb0
     (.wb_clk_i (wb_clk),
      .wb_rst_i (wb_arb_rst),
      .done     (wb_arb_done));

   always #5 wb_clk <= ~wb_clk;
   initial begin
      $display("==Running wb_mux tests==");
      #100 wb_mux_rst <= 0;
      @(posedge wb_mux_done);
      #100 $display("==wb_mux tests done==");
      wb_mux_rst <= 1;

      $display("==Running wb_arbiter tests==");
      wb_arb_rst <= 0;
      @(posedge wb_arb_done);
      #100 $display("==wb_arbiter tests done==");
      wb_arb_rst <= 1;

      #3 $finish;
   end
      
   
endmodule