data/full_repos/permissive/146618947/gray_tarea8/contador_gray_tester.v
 line:29: before: "("
1: b'%Error: data/full_repos/permissive/146618947/gray_tarea8/contador_gray_tester.v:14: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("contador.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/146618947/gray_tarea8/contador_gray_tester.v:15: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars();\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/146618947/gray_tarea8/contador_gray_tester.v:25: syntax error, unexpected \'@\'\n      @ (posedge clk);\n      ^\n%Error: data/full_repos/permissive/146618947/gray_tarea8/contador_gray_tester.v:30: syntax error, unexpected \'@\'\n         @ (posedge clk);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/gray_tarea8/contador_gray_tester.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #15 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module contador_gray_tester (
                            input [4:0] data_out_cond,
                            input [4:0] data_out_est,
                            output reg  clk,
                            output reg  reset_L,
                            output reg  enable
                            );

   reg [4:0]                            data_out_cond_buff;
   reg [4:0]                            data_out_est_buff;

   initial begin
      $dumpfile("contador.vcd");
      $dumpvars();
   end

   initial begin
      clk = 1;
      enable = 0;
      reset_L = 0;
      data_out_cond_buff = 5'b0;
      data_out_est_buff = 5'b0;

      @ (posedge clk);
      reset_L = 1;
      enable = 1;

      repeat (400) begin
         @ (posedge clk);
      end

      $finish();
   end



   always @(posedge clk) begin
      data_out_cond_buff <= data_out_cond;
      data_out_est_buff <= data_out_est;

       if (data_out_cond_buff != data_out_est_buff) begin
          $display("Diferencia entre el conductual y estructural %t", $realtime);
       end

   end

   always
     begin
        #15 clk = ~clk;
     end

endmodule
module contador_gray_tester (
                            input [4:0] data_out_cond,
                            input [4:0] data_out_est,
                            output reg  clk,
                            output reg  reset_L,
                            output reg  enable
                            );


   reg [4:0]                            data_out_cond_buff;
   reg [4:0]                            data_out_est_buff;

   initial begin
      $dumpfile("contador.vcd");
      $dumpvars();
   end

   initial begin
      clk = 1;
      enable = 0;
      reset_L = 0;
      data_out_cond_buff = 5'b0;
      data_out_est_buff = 5'b0;

      @ (posedge clk);
      reset_L = 1;
      enable = 1;

      repeat (400) begin
         @ (posedge clk);
      end

      $finish();
   end



   always @(posedge clk) begin
      data_out_cond_buff <= data_out_cond;
      data_out_est_buff <= data_out_est;

       if (data_out_cond_buff != data_out_est_buff) begin
          $display("Diferencia entre el conductual y estructural %t", $realtime);
       end

   end

   always
     begin
        #15 clk = ~clk;
     end

endmodule