data/full_repos/permissive/197289583/tests/test_input_single.v
 line:71: before: "("
1: b'%Error: data/full_repos/permissive/197289583/tests/test_input_single.v:63: Cannot find include file: tasks.v\n`include "tasks.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197289583/tests,data/full_repos/permissive/197289583/tasks.v\n             data/full_repos/permissive/197289583/tests,data/full_repos/permissive/197289583/tasks.v.v\n             data/full_repos/permissive/197289583/tests,data/full_repos/permissive/197289583/tasks.v.sv\n             tasks.v\n             tasks.v.v\n             tasks.v.sv\n             obj_dir/tasks.v\n             obj_dir/tasks.v.v\n             obj_dir/tasks.v.sv\n%Error: data/full_repos/permissive/197289583/tests/test_input_single.v:19: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("tests/test_input.lxt2");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/197289583/tests/test_input_single.v:20: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, test);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/197289583/tests/test_input_single.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #(CLOCK_PERIOD/2) refclk = !refclk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/197289583/tests/test_input_single.v:73: Unsupported: Ignoring delay on this delayed statement.\n always @(posedge testreq) #5 sr <= {sr[6:0], testack};\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/197289583/tests/test_input_single.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #(25*USEC)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197289583/tests/test_input_single.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #BREAK;    \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/197289583/tests/test_input_single.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #(5*USEC);\n  ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module test;


	parameter CLOCK_PERIOD = 500;


	parameter PWID  = 500;
	parameter PGAP  = 500;
	parameter BREAK = 25000;


	localparam USEC = 1000;
	localparam MSEC = 1000000;


	initial begin
		$dumpfile("tests/test_input.lxt2");
		$dumpvars(0, test);
	end


	reg refclk;
	initial
		refclk = 1'b0;
	always
		#(CLOCK_PERIOD/2) refclk = !refclk;



	reg testreq;
	wire testack;
	initial testreq = 1'b0;


	wire [3:0] lcd_data;
	wire lcd_rs, lcd_e;


	reg [7:0] txin;
	reg txpend;

	initial txpend = 1'b0;
	initial txin = 8'd0;




	postcode p(
		.refclk(refclk),
		.testreq(testreq),
		.testack(testack),

		.lcd_data(lcd_data),
		.lcd_rs(lcd_rs),
		.lcd_e(lcd_e),

		.txin(txin),
		.tx_pending(txpend)
	);

`include "tasks.v"



	integer x;
	localparam WS = 3;


	reg [7:0] sr;
	initial sr = 0;
	always @(posedge testreq) #5 sr <= {sr[6:0], testack};

	initial begin

		#(25*USEC)


		pulsebreak(4);


		pulse(4);
		if (lastAck != 1'b0) begin
			$display("*** DUT ERROR at t=%d. DUT Acked an INPUT with txpend = 0", $time);
			$finish;
		end



		x = 0;
		txin = 8'h5A;
		while (x < 8+WS) begin

			pulse(1);
			x += 1;

			if (x == WS-1) begin
				txpend = 1'b1;
			end else if (x >= WS) begin
				txpend = 1'b0;
			end
		end
		#BREAK;


		if (sr != 8'h5A) begin
			$display("*** DUT ERROR at t=%d. INPUT phase, data mismatch. Got 0x%02X, wanted 0x%02X", $time, sr, txin);
			$finish;
		end

		$display("<OK>  Chained input test completed. time=%d", $time);

		#(5*USEC);
		$finish;
	end

endmodule
module test;



	parameter CLOCK_PERIOD = 500;


	parameter PWID  = 500;
	parameter PGAP  = 500;
	parameter BREAK = 25000;


	localparam USEC = 1000;
	localparam MSEC = 1000000;


	initial begin
		$dumpfile("tests/test_input.lxt2");
		$dumpvars(0, test);
	end


	reg refclk;
	initial
		refclk = 1'b0;
	always
		#(CLOCK_PERIOD/2) refclk = !refclk;



	reg testreq;
	wire testack;
	initial testreq = 1'b0;


	wire [3:0] lcd_data;
	wire lcd_rs, lcd_e;


	reg [7:0] txin;
	reg txpend;

	initial txpend = 1'b0;
	initial txin = 8'd0;




	postcode p(
		.refclk(refclk),
		.testreq(testreq),
		.testack(testack),

		.lcd_data(lcd_data),
		.lcd_rs(lcd_rs),
		.lcd_e(lcd_e),

		.txin(txin),
		.tx_pending(txpend)
	);

`include "tasks.v"



	integer x;
	localparam WS = 3;


	reg [7:0] sr;
	initial sr = 0;
	always @(posedge testreq) #5 sr <= {sr[6:0], testack};

	initial begin

		#(25*USEC)


		pulsebreak(4);


		pulse(4);
		if (lastAck != 1'b0) begin
			$display("*** DUT ERROR at t=%d. DUT Acked an INPUT with txpend = 0", $time);
			$finish;
		end



		x = 0;
		txin = 8'h5A;
		while (x < 8+WS) begin

			pulse(1);
			x += 1;

			if (x == WS-1) begin
				txpend = 1'b1;
			end else if (x >= WS) begin
				txpend = 1'b0;
			end
		end
		#BREAK;


		if (sr != 8'h5A) begin
			$display("*** DUT ERROR at t=%d. INPUT phase, data mismatch. Got 0x%02X, wanted 0x%02X", $time, sr, txin);
			$finish;
		end

		$display("<OK>  Chained input test completed. time=%d", $time);

		#(5*USEC);
		$finish;
	end

endmodule