data/full_repos/permissive/10136357/hardware/src/inst_decoder.v
1: b'%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n             consts.vh\n             consts.vh.v\n             consts.vh.sv\n             obj_dir/consts.vh\n             obj_dir/consts.vh.v\n             obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: Define or directive not defined: \'`STR_LEN\'\n output reg [(`STR_LEN * 8) - 1:0] str,\n              ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:161: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n output reg [(`STR_LEN * 8) - 1:0] str,\n                       ^\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:174: syntax error, unexpected type, expecting IDENTIFIER or \'=\' or do or final\n reg [1:0] type;\n           ^~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:187: syntax error, unexpected IDENTIFIER\n reg_decoder r1(wd_s, wd);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:200: Define or directive not defined: \'`OPCODE_OP\'\n   `OPCODE_OP:\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:201: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] = \n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:204: Define or directive not defined: \'`OPCODE_OP_IMM\'\n   `OPCODE_OP_IMM: begin\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:206: Define or directive not defined: \'`STR_LEN\'\n     str[(`STR_LEN - 8) * 8 - 1:0] = \n          ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:209: Define or directive not defined: \'`STR_LEN\'\n     str[(`STR_LEN - 8) * 8 - 1:0] = "";\n          ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:212: Define or directive not defined: \'`OPCODE_LUI\'\n   `OPCODE_LUI:\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:213: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] =\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_J\'\n   `OPCODE_J, `OPCODE_JAL:\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:216: Define or directive not defined: \'`OPCODE_JAL\'\n   `OPCODE_J, `OPCODE_JAL:\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:217: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] =\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:220: Define or directive not defined: \'`OPCODE_JALR\'\n   `OPCODE_JALR:\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:222: Define or directive not defined: \'`STR_LEN\'\n     str[(`STR_LEN - 8) * 8 - 1:0] =\n          ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:225: Define or directive not defined: \'`STR_LEN\'\n     str[(`STR_LEN - 8) * 8 - 1:0] = "";\n          ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:227: Define or directive not defined: \'`OPCODE_BRANCH\'\n   `OPCODE_BRANCH:\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:228: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] =\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:231: Define or directive not defined: \'`OPCODE_LOAD\'\n   `OPCODE_LOAD:\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:232: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] =\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:235: Define or directive not defined: \'`OPCODE_STORE\'\n   `OPCODE_STORE:\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:236: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] =\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:239: Define or directive not defined: \'`OPCODE_PCR\'\n   `OPCODE_PCR:\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:240: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] =\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:244: Define or directive not defined: \'`STR_LEN\'\n    str[(`STR_LEN - 8) * 8 - 1:0] = "";\n         ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:250: Define or directive not defined: \'`OPCODE_OP\'\n   `OPCODE_OP:\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:253: Define or directive not defined: \'`F3_MUL\'\n      `F3_MUL:    op_s = "mul     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:254: Define or directive not defined: \'`F3_MULH\'\n      `F3_MULH:   op_s = "mulh    ";\n      ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:255: Define or directive not defined: \'`F3_MULHSU\'\n      `F3_MULHSU: op_s = "mulhsu  ";\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:256: Define or directive not defined: \'`F3_MULHU\'\n      `F3_MULHU:  op_s = "mulhu   ";\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:257: Define or directive not defined: \'`F3_DIV\'\n      `F3_DIV:    op_s = "div     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:258: Define or directive not defined: \'`F3_DIVU\'\n      `F3_DIVU:   op_s = "divu    ";\n      ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:259: Define or directive not defined: \'`F3_REM\'\n      `F3_REM:    op_s = "rem     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:260: Define or directive not defined: \'`F3_REMU\'\n      `F3_REMU:   op_s = "remu    ";\n      ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:265: Define or directive not defined: \'`F3_ADD\'\n      `F3_ADD:  op_s = inst[16] ? "sub     " : "add     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:266: Define or directive not defined: \'`F3_SLL\'\n      `F3_SLL:  op_s = "sll     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:267: Define or directive not defined: \'`F3_SLT\'\n      `F3_SLT:  op_s = "slt     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:268: Define or directive not defined: \'`F3_SLTU\'\n      `F3_SLTU: op_s = "sltu    ";\n      ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:269: Define or directive not defined: \'`F3_XOR\'\n      `F3_XOR:  op_s = "xor     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:270: Define or directive not defined: \'`F3_SR\'\n      `F3_SR:   op_s = inst[16] ? "sra     " : "srl     ";\n      ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:271: Define or directive not defined: \'`F3_OR\'\n      `F3_OR:   op_s = "or      ";\n      ^~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:272: Define or directive not defined: \'`F3_AND\'\n      `F3_AND:  op_s = "and     ";\n      ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:277: Define or directive not defined: \'`OPCODE_OP_IMM\'\n   `OPCODE_OP_IMM:\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:279: Define or directive not defined: \'`F3_ADD\'\n     `F3_ADD:  op_s = inst == 32\'h00000013 ? "nop     " : "addi    ";\n     ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:280: Define or directive not defined: \'`F3_SLL\'\n     `F3_SLL:  op_s = "slli    ";\n     ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:281: Define or directive not defined: \'`F3_SLT\'\n     `F3_SLT:  op_s = "slti    ";\n     ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:282: Define or directive not defined: \'`F3_SLTU\'\n     `F3_SLTU: op_s = "sltiu   ";\n     ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/inst_decoder.v:283: Define or directive not defined: \'`F3_XOR\'\n     `F3_XOR:  op_s = "xori    ";\n     ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module inst_decoder (
	output reg [(`STR_LEN * 8) - 1:0] str,
	input [31:0] jump_target,
	input [31:0] branch_target,
	input [31:0] inst
);

	wire [6:0] opcode = inst[6:0];
	wire [9:7] funct3 = inst[9:7];
	wire [11:0] imm12 = inst[21:10];
	wire [19:0] imm20 = inst[26:7];
	wire [11:0] split_imm12 = {inst[31:27], inst[16:10]};
	wire [4:0] wd = inst[31:27];
	reg [(8 * 8) - 1:0] op_s;
	reg [1:0] type;

	wire [23:0] wd_s;
	wire [23:0] rs1_s;
	wire [23:0] rs2_s;
	wire [63:0] pcr_s;

	wire [47:0] imm12_s;
	wire [47:0] split_imm12_s;
	wire [55:0] imm20_s;
	wire [79:0] addr_s;
	wire [79:0] branch_addr_s;

	reg_decoder r1(wd_s, wd);
	reg_decoder r2(rs1_s, inst[26:22]);
	reg_decoder r3(rs2_s, inst[21:17]);
	pcreg_decoder r4(pcr_s, inst[26:22]);

	imm_decoder id(imm12_s, imm12);
	lui_decoder ld(imm20_s, imm20);
	imm_decoder sid(split_imm12_s, split_imm12);
	addr_decoder ad(addr_s, jump_target);
	addr_decoder bd(branch_addr_s, branch_target);

	always @ (*) begin
		case (opcode)
			`OPCODE_OP:
				str[(`STR_LEN - 8) * 8 - 1:0] = 
					{" ", wd_s, ",", rs1_s, ",", rs2_s};

			`OPCODE_OP_IMM: begin
				if (inst != 32'h00000013) 
					str[(`STR_LEN - 8) * 8 - 1:0] = 
						{" ", wd_s, ",", rs1_s, ",", imm12_s};
				else
					str[(`STR_LEN - 8) * 8 - 1:0] = "";
			end

			`OPCODE_LUI:
				str[(`STR_LEN - 8) * 8 - 1:0] =
					{" ", wd_s, ",", imm20_s};

			`OPCODE_J, `OPCODE_JAL:
				str[(`STR_LEN - 8) * 8 - 1:0] =
					{" ", addr_s};

			`OPCODE_JALR:
				if (inst != 32'h004000eb)
					str[(`STR_LEN - 8) * 8 - 1:0] =
						{" ", wd_s, ",", rs1_s, ",", addr_s};
				else
					str[(`STR_LEN - 8) * 8 - 1:0] = "";

			`OPCODE_BRANCH:
				str[(`STR_LEN - 8) * 8 - 1:0] =
					{" ", rs1_s, ",", rs2_s, ",", branch_addr_s};

			`OPCODE_LOAD:
				str[(`STR_LEN - 8) * 8 - 1:0] =
					{" ", wd_s, ",", imm12_s, "(", rs1_s, ")"};

			`OPCODE_STORE:
				str[(`STR_LEN - 8) * 8 - 1:0] =
					{" ", rs2_s, ",", split_imm12_s, "(", rs1_s, ")"};

			`OPCODE_PCR:
				str[(`STR_LEN - 8) * 8 - 1:0] =
					{" ", wd_s, ",", rs2_s, ",", pcr_s};

			default:
				str[(`STR_LEN - 8) * 8 - 1:0] = "";
		endcase
	end

	always @ (*) begin
		case (opcode)
			`OPCODE_OP:
				if (inst[10]) begin
					case (funct3)
						`F3_MUL:    op_s = "mul     ";
						`F3_MULH:   op_s = "mulh    ";
						`F3_MULHSU: op_s = "mulhsu  ";
						`F3_MULHU:  op_s = "mulhu   ";
						`F3_DIV:    op_s = "div     ";
						`F3_DIVU:   op_s = "divu    ";
						`F3_REM:    op_s = "rem     ";
						`F3_REMU:   op_s = "remu    ";
						default:    op_s = "???     ";
					endcase
				end else begin
					case (funct3)
						`F3_ADD:  op_s = inst[16] ? "sub     " : "add     ";
						`F3_SLL:  op_s = "sll     ";
						`F3_SLT:  op_s = "slt     ";
						`F3_SLTU: op_s = "sltu    ";
						`F3_XOR:  op_s = "xor     ";
						`F3_SR:   op_s = inst[16] ? "sra     " : "srl     ";
						`F3_OR:   op_s = "or      ";
						`F3_AND:  op_s = "and     ";
						default: op_s = "???     ";
					endcase
				end

			`OPCODE_OP_IMM:
				case (funct3)
					`F3_ADD:  op_s = inst == 32'h00000013 ? "nop     " : "addi    ";
					`F3_SLL:  op_s = "slli    ";
					`F3_SLT:  op_s = "slti    ";
					`F3_SLTU: op_s = "sltiu   ";
					`F3_XOR:  op_s = "xori    ";
					`F3_SR:   op_s = inst[16] ? "srai    " : "srli    ";
					`F3_OR:   op_s = "ori     ";
					`F3_AND:  op_s = "andi    ";
					default: op_s = "???     ";
				endcase

			`OPCODE_LUI:
				op_s = "lui     ";

			`OPCODE_J:
				op_s = "j       ";

			`OPCODE_JAL:
				op_s = "jal     ";

			`OPCODE_JALR:
				if (inst == 32'h004000eb)
					op_s = "ret     ";
				else
					op_s = wd == 5'd0 ? "jr      " : "jalr    "; 

			`OPCODE_LOAD:
				case (funct3) 
					`F3_LB:  op_s = "lb      ";
					`F3_LH:  op_s = "lh      ";
					`F3_LW:  op_s = "lw      ";
					`F3_LBU: op_s = "lbu     ";
					`F3_LHU: op_s = "lhu     ";
					default: op_s = "???     ";
				endcase

			`OPCODE_STORE:
				case (funct3)
					`F3_SB:  op_s = "sb      ";
					`F3_SH:  op_s = "sh      ";
					`F3_SW:  op_s = "sw      ";
					default: op_s = "???     ";
				endcase

			`OPCODE_BRANCH:
				case (funct3)
					`F3_BEQ:  op_s = "beq     ";
					`F3_BNE:  op_s = "bne     ";
					`F3_BLT:  op_s = "blt     ";
					`F3_BGE:  op_s = "bge     ";
					`F3_BLTU: op_s = "bltu    ";
					`F3_BGEU: op_s = "bgeu    ";
					default:  op_s = "???     ";
				endcase

			`OPCODE_PCR:
				case (funct3)
					`F3_CLEARPCR: op_s = "clearpcr";
					`F3_SETPCR:   op_s = "setpcr  ";
					`F3_MFPCR:    op_s = "mfpcr   ";
					`F3_MTPCR:    op_s = "mtpcr   ";
					default:      op_s = "???     ";
				endcase

			default:
				op_s = "???";
		endcase

		str[(`STR_LEN * 8) - 1:((`STR_LEN - 8) * 8)] = op_s;
	end


endmodule
module inst_decoder (
	output reg [(`STR_LEN * 8) - 1:0] str,
	input [31:0] jump_target,
	input [31:0] branch_target,
	input [31:0] inst
);


	wire [6:0] opcode = inst[6:0];
	wire [9:7] funct3 = inst[9:7];
	wire [11:0] imm12 = inst[21:10];
	wire [19:0] imm20 = inst[26:7];
	wire [11:0] split_imm12 = {inst[31:27], inst[16:10]};
	wire [4:0] wd = inst[31:27];
	reg [(8 * 8) - 1:0] op_s;
	reg [1:0] type;

	wire [23:0] wd_s;
	wire [23:0] rs1_s;
	wire [23:0] rs2_s;
	wire [63:0] pcr_s;

	wire [47:0] imm12_s;
	wire [47:0] split_imm12_s;
	wire [55:0] imm20_s;
	wire [79:0] addr_s;
	wire [79:0] branch_addr_s;

	reg_decoder r1(wd_s, wd);
	reg_decoder r2(rs1_s, inst[26:22]);
	reg_decoder r3(rs2_s, inst[21:17]);
	pcreg_decoder r4(pcr_s, inst[26:22]);

	imm_decoder id(imm12_s, imm12);
	lui_decoder ld(imm20_s, imm20);
	imm_decoder sid(split_imm12_s, split_imm12);
	addr_decoder ad(addr_s, jump_target);
	addr_decoder bd(branch_addr_s, branch_target);

	always @ (*) begin
		case (opcode)
			`OPCODE_OP:
				str[(`STR_LEN - 8) * 8 - 1:0] = 
					{" ", wd_s, ",", rs1_s, ",", rs2_s};

			`OPCODE_OP_IMM: begin
				if (inst != 32'h00000013) 
					str[(`STR_LEN - 8) * 8 - 1:0] = 
						{" ", wd_s, ",", rs1_s, ",", imm12_s};
				else
					str[(`STR_LEN - 8) * 8 - 1:0] = "";
			end

			`OPCODE_LUI:
				str[(`STR_LEN - 8) * 8 - 1:0] =
					{" ", wd_s, ",", imm20_s};

			`OPCODE_J, `OPCODE_JAL:
				str[(`STR_LEN - 8) * 8 - 1:0] =
					{" ", addr_s};

			`OPCODE_JALR:
				if (inst != 32'h004000eb)
					str[(`STR_LEN - 8) * 8 - 1:0] =
						{" ", wd_s, ",", rs1_s, ",", addr_s};
				else
					str[(`STR_LEN - 8) * 8 - 1:0] = "";

			`OPCODE_BRANCH:
				str[(`STR_LEN - 8) * 8 - 1:0] =
					{" ", rs1_s, ",", rs2_s, ",", branch_addr_s};

			`OPCODE_LOAD:
				str[(`STR_LEN - 8) * 8 - 1:0] =
					{" ", wd_s, ",", imm12_s, "(", rs1_s, ")"};

			`OPCODE_STORE:
				str[(`STR_LEN - 8) * 8 - 1:0] =
					{" ", rs2_s, ",", split_imm12_s, "(", rs1_s, ")"};

			`OPCODE_PCR:
				str[(`STR_LEN - 8) * 8 - 1:0] =
					{" ", wd_s, ",", rs2_s, ",", pcr_s};

			default:
				str[(`STR_LEN - 8) * 8 - 1:0] = "";
		endcase
	end

	always @ (*) begin
		case (opcode)
			`OPCODE_OP:
				if (inst[10]) begin
					case (funct3)
						`F3_MUL:    op_s = "mul     ";
						`F3_MULH:   op_s = "mulh    ";
						`F3_MULHSU: op_s = "mulhsu  ";
						`F3_MULHU:  op_s = "mulhu   ";
						`F3_DIV:    op_s = "div     ";
						`F3_DIVU:   op_s = "divu    ";
						`F3_REM:    op_s = "rem     ";
						`F3_REMU:   op_s = "remu    ";
						default:    op_s = "???     ";
					endcase
				end else begin
					case (funct3)
						`F3_ADD:  op_s = inst[16] ? "sub     " : "add     ";
						`F3_SLL:  op_s = "sll     ";
						`F3_SLT:  op_s = "slt     ";
						`F3_SLTU: op_s = "sltu    ";
						`F3_XOR:  op_s = "xor     ";
						`F3_SR:   op_s = inst[16] ? "sra     " : "srl     ";
						`F3_OR:   op_s = "or      ";
						`F3_AND:  op_s = "and     ";
						default: op_s = "???     ";
					endcase
				end

			`OPCODE_OP_IMM:
				case (funct3)
					`F3_ADD:  op_s = inst == 32'h00000013 ? "nop     " : "addi    ";
					`F3_SLL:  op_s = "slli    ";
					`F3_SLT:  op_s = "slti    ";
					`F3_SLTU: op_s = "sltiu   ";
					`F3_XOR:  op_s = "xori    ";
					`F3_SR:   op_s = inst[16] ? "srai    " : "srli    ";
					`F3_OR:   op_s = "ori     ";
					`F3_AND:  op_s = "andi    ";
					default: op_s = "???     ";
				endcase

			`OPCODE_LUI:
				op_s = "lui     ";

			`OPCODE_J:
				op_s = "j       ";

			`OPCODE_JAL:
				op_s = "jal     ";

			`OPCODE_JALR:
				if (inst == 32'h004000eb)
					op_s = "ret     ";
				else
					op_s = wd == 5'd0 ? "jr      " : "jalr    "; 

			`OPCODE_LOAD:
				case (funct3) 
					`F3_LB:  op_s = "lb      ";
					`F3_LH:  op_s = "lh      ";
					`F3_LW:  op_s = "lw      ";
					`F3_LBU: op_s = "lbu     ";
					`F3_LHU: op_s = "lhu     ";
					default: op_s = "???     ";
				endcase

			`OPCODE_STORE:
				case (funct3)
					`F3_SB:  op_s = "sb      ";
					`F3_SH:  op_s = "sh      ";
					`F3_SW:  op_s = "sw      ";
					default: op_s = "???     ";
				endcase

			`OPCODE_BRANCH:
				case (funct3)
					`F3_BEQ:  op_s = "beq     ";
					`F3_BNE:  op_s = "bne     ";
					`F3_BLT:  op_s = "blt     ";
					`F3_BGE:  op_s = "bge     ";
					`F3_BLTU: op_s = "bltu    ";
					`F3_BGEU: op_s = "bgeu    ";
					default:  op_s = "???     ";
				endcase

			`OPCODE_PCR:
				case (funct3)
					`F3_CLEARPCR: op_s = "clearpcr";
					`F3_SETPCR:   op_s = "setpcr  ";
					`F3_MFPCR:    op_s = "mfpcr   ";
					`F3_MTPCR:    op_s = "mtpcr   ";
					default:      op_s = "???     ";
				endcase

			default:
				op_s = "???";
		endcase

		str[(`STR_LEN * 8) - 1:((`STR_LEN - 8) * 8)] = op_s;
	end


endmodule