data/full_repos/permissive/190755935/src/comms/rtl/uart_in.v
 line:395: before: "="
1: b'%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_in.v:54: Cannot find include file: ../../pipe/rtl/pipe_defs.v\n`include "../../pipe/rtl/pipe_defs.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/190755935/src/comms/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v\n             data/full_repos/permissive/190755935/src/comms/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v.v\n             data/full_repos/permissive/190755935/src/comms/rtl,data/full_repos/permissive/190755935/../../pipe/rtl/pipe_defs.v.sv\n             ../../pipe/rtl/pipe_defs.v\n             ../../pipe/rtl/pipe_defs.v.v\n             ../../pipe/rtl/pipe_defs.v.sv\n             obj_dir/../../pipe/rtl/pipe_defs.v\n             obj_dir/../../pipe/rtl/pipe_defs.v.v\n             obj_dir/../../pipe/rtl/pipe_defs.v.sv\n%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_in.v:56: Define or directive not defined: \'`PS_DATA\'\nmodule uart_in  #( parameter PipeSpec = `PS_DATA( 8 ), parameter ClockFrequency = 12000000, parameter BaudRate = 9600 ) (\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_in.v:60: Define or directive not defined: \'`P_m\'\n        inout [`P_m(PipeSpec):0] pipe_out,\n               ^~~~\n%Error: data/full_repos/permissive/190755935/src/comms/rtl/uart_in.v:65: Define or directive not defined: \'`P_Data_w\'\n    wire [`P_Data_w(PipeSpec)-1:0] out_data;\n          ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module uart_in  #( parameter PipeSpec = `PS_DATA( 8 ), parameter ClockFrequency = 12000000, parameter BaudRate = 9600 ) (
        input clock,
        input reset,

        inout [`P_m(PipeSpec):0] pipe_out,

        input pin_rx
    );

    wire [`P_Data_w(PipeSpec)-1:0] out_data;
    wire                     out_valid;
    wire                     out_ready;

    uart_in_np #( .ClockFrequency( ClockFrequency ), .BaudRate( BaudRate ) )  u_i_np (
            .clock( clock ),
            .reset( reset ),

            .in_data( out_data ),
            .in_valid( out_valid ),
            .in_ready( out_ready ),

            .uart_rx( pin_rx )
        );

    p_pack_data        #( .PipeSpec( PipeSpec ) ) out_pack_d ( out_data,             pipe_out );
    p_pack_valid_ready #( .PipeSpec( PipeSpec ) ) out_pack_vr( out_valid, out_ready, pipe_out );

endmodule
module uart_in  #( parameter PipeSpec = `PS_DATA( 8 ), parameter ClockFrequency = 12000000, parameter BaudRate = 9600 ) (
        input clock,
        input reset,

        inout [`P_m(PipeSpec):0] pipe_out,

        input pin_rx
    );


    wire [`P_Data_w(PipeSpec)-1:0] out_data;
    wire                     out_valid;
    wire                     out_ready;

    uart_in_np #( .ClockFrequency( ClockFrequency ), .BaudRate( BaudRate ) )  u_i_np (
            .clock( clock ),
            .reset( reset ),

            .in_data( out_data ),
            .in_valid( out_valid ),
            .in_ready( out_ready ),

            .uart_rx( pin_rx )
        );

    p_pack_data        #( .PipeSpec( PipeSpec ) ) out_pack_d ( out_data,             pipe_out );
    p_pack_valid_ready #( .PipeSpec( PipeSpec ) ) out_pack_vr( out_valid, out_ready, pipe_out );

endmodule