data/full_repos/permissive/139225418/rtl/axi_lite_m.v
1: b'%Error: data/full_repos/permissive/139225418/rtl/axi_lite_m.v:55: Cannot find file containing module: \'axis_m\'\naxis_m axis_waddr ( .areset_n(aresetn), .aclk(aclk), \n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/139225418/rtl,data/full_repos/permissive/139225418/axis_m\n             data/full_repos/permissive/139225418/rtl,data/full_repos/permissive/139225418/axis_m.v\n             data/full_repos/permissive/139225418/rtl,data/full_repos/permissive/139225418/axis_m.sv\n             axis_m\n             axis_m.v\n             axis_m.sv\n             obj_dir/axis_m\n             obj_dir/axis_m.v\n             obj_dir/axis_m.sv\n%Error: data/full_repos/permissive/139225418/rtl/axi_lite_m.v:69: Cannot find file containing module: \'axis_m\'\naxis_m axis_wdata ( .areset_n(aresetn), .aclk(aclk), \n^~~~~~\n%Error: data/full_repos/permissive/139225418/rtl/axi_lite_m.v:86: Cannot find file containing module: \'axis_s\'\naxis_s axis_resp ( .areset_n(aresetn), .aclk(aclk),\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/139225418/rtl/axi_lite_m.v:106: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance axis_lite_m\nassign m_axi_arprot = 1\'b0;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/139225418/rtl/axi_lite_m.v:109: Cannot find file containing module: \'axis_m\'\naxis_m axis_raddr ( .areset_n(aresetn), .aclk(aclk), \n^~~~~~\n%Error: data/full_repos/permissive/139225418/rtl/axi_lite_m.v:122: Cannot find file containing module: \'axis_s\'\naxis_s axis_rdata ( .areset_n(aresetn), .aclk(aclk),\n^~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module axis_lite_m ( 

			  input  wire                            aclk,
			  input  wire                            aresetn,

			  output wire [32-1:0]         			 m_axi_awaddr,
			  output wire [3-1:0]                    m_axi_awprot,
			  output   	                             m_axi_awvalid,
			  input  wire                            m_axi_awready,

			  output wire [32-1:0]      			 m_axi_wdata,
			  output wire [32/8-1:0]    			 m_axi_wstrb,
			  output 	                             m_axi_wvalid,
			  input  wire                            m_axi_wready,

			  input  wire [2-1:0]                    m_axi_bresp,
			  input  wire                            m_axi_bvalid,
			  output 	                             m_axi_bready,

			  output wire [32-1:0]       			 m_axi_araddr,
			  output wire [3-1:0]                    m_axi_arprot,
			  output 	                             m_axi_arvalid,
			  input  wire                            m_axi_arready,

			  input  wire [32-1:0]      			 m_axi_rdata,
			  input  wire [2-1:0]                    m_axi_rresp,
			  input  wire                            m_axi_rvalid,
			  output 	                             m_axi_rready,

			  input	wire [32-1:0]					 app_waddr,
			  input	wire [32-1:0]					 app_wdata,
			  input	wire         					 app_wen,
			  
			  input	wire [32-1:0]					 app_raddr,
			  input	wire         					 app_ren,
			  output wire [32-1:0]					 app_rdata,
			  output                                 app_wdone ,
			  output                                 app_werror ,
			  output                                 app_rdone ,
			  output                                 app_rerror
			);




wire waddr_done,wdata_done,wresp_slave, wresp_slave_final;

axis_m axis_waddr ( .areset_n(aresetn), .aclk(aclk), 
					.data		(app_waddr), 
					.send		(app_wen),
					
					.tready		(m_axi_awready), 
					.tvalid		(m_axi_awvalid),
					.tlast		(m_axi_awvalid), 
					.tdata		(m_axi_awaddr),
					
					.finish		(waddr_done)
			);
			
assign m_axi_awprot = 3'o0;

axis_m axis_wdata ( .areset_n(aresetn), .aclk(aclk), 
					.data		(app_wdata), 
					.send		(app_wen),
					
					.tready		(m_axi_wready), 
					.tvalid		(m_axi_wvalid),
					.tlast		(m_axi_wvalid), 
					.tdata		(m_axi_wdata),
					
					.finish		(wdata_done)
			);
assign m_axi_wstrb = (m_axi_wvalid) ? 4'b1111 : 4'b0000;



wire [31:0] wchnl_resp;

axis_s axis_resp ( .areset_n(aresetn), .aclk(aclk),
					.data		(wchnl_resp),
					.ready 		(app_wen),
					
					.tready 	(m_axi_bready),
					.tvalid		(m_axi_bvalid),
					.tlast		(m_axi_bvalid),
					.tdata		( {30'b0,m_axi_bresp} ),
					
					.finish		(wresp_slave)
					);
					
assign wresp_slave_final= wresp_slave && (wchnl_resp[1:0] ==2'b00 || wchnl_resp[1:0] ==2'b01 );
					
assign app_wdone = waddr_done && wdata_done && wresp_slave_final ;
assign app_werror = wresp_slave && (wchnl_resp[1:0] ==2'b10 || wchnl_resp[1:0] ==2'b11 );


wire raddr_done,rdata_done;

assign m_axi_arprot = 1'b0;


axis_m axis_raddr ( .areset_n(aresetn), .aclk(aclk), 
					.data		(app_raddr), 
					.send		(app_ren),
					
					.tready		(m_axi_arready), 
					.tvalid		(m_axi_arvalid),
					.tlast		(m_axi_arvalid), 
					.tdata		(m_axi_araddr),
					
					.finish		(raddr_done)
			);


axis_s axis_rdata ( .areset_n(aresetn), .aclk(aclk),
					.data		(app_rdata),
					.ready 		(app_ren),
					
					.tready 	(m_axi_rready),
					.tvalid		(m_axi_rvalid),
					.tlast		(m_axi_rvalid),
					.tdata		(m_axi_rdata ),
					
					.finish		(rdata_done)
			);

assign app_rdone = raddr_done && rdata_done && (m_axi_rresp[1:0] ==2'b00 || m_axi_rresp[1:0] ==2'b01 );
assign app_rerror = wresp_slave && (m_axi_rresp[1:0] ==2'b10 || m_axi_rresp[1:0] ==2'b11 );
	

endmodule
module axis_lite_m ( 

			  input  wire                            aclk,
			  input  wire                            aresetn,

			  output wire [32-1:0]         			 m_axi_awaddr,
			  output wire [3-1:0]                    m_axi_awprot,
			  output   	                             m_axi_awvalid,
			  input  wire                            m_axi_awready,

			  output wire [32-1:0]      			 m_axi_wdata,
			  output wire [32/8-1:0]    			 m_axi_wstrb,
			  output 	                             m_axi_wvalid,
			  input  wire                            m_axi_wready,

			  input  wire [2-1:0]                    m_axi_bresp,
			  input  wire                            m_axi_bvalid,
			  output 	                             m_axi_bready,

			  output wire [32-1:0]       			 m_axi_araddr,
			  output wire [3-1:0]                    m_axi_arprot,
			  output 	                             m_axi_arvalid,
			  input  wire                            m_axi_arready,

			  input  wire [32-1:0]      			 m_axi_rdata,
			  input  wire [2-1:0]                    m_axi_rresp,
			  input  wire                            m_axi_rvalid,
			  output 	                             m_axi_rready,

			  input	wire [32-1:0]					 app_waddr,
			  input	wire [32-1:0]					 app_wdata,
			  input	wire         					 app_wen,
			  
			  input	wire [32-1:0]					 app_raddr,
			  input	wire         					 app_ren,
			  output wire [32-1:0]					 app_rdata,
			  output                                 app_wdone ,
			  output                                 app_werror ,
			  output                                 app_rdone ,
			  output                                 app_rerror
			);





wire waddr_done,wdata_done,wresp_slave, wresp_slave_final;

axis_m axis_waddr ( .areset_n(aresetn), .aclk(aclk), 
					.data		(app_waddr), 
					.send		(app_wen),
					
					.tready		(m_axi_awready), 
					.tvalid		(m_axi_awvalid),
					.tlast		(m_axi_awvalid), 
					.tdata		(m_axi_awaddr),
					
					.finish		(waddr_done)
			);
			
assign m_axi_awprot = 3'o0;

axis_m axis_wdata ( .areset_n(aresetn), .aclk(aclk), 
					.data		(app_wdata), 
					.send		(app_wen),
					
					.tready		(m_axi_wready), 
					.tvalid		(m_axi_wvalid),
					.tlast		(m_axi_wvalid), 
					.tdata		(m_axi_wdata),
					
					.finish		(wdata_done)
			);
assign m_axi_wstrb = (m_axi_wvalid) ? 4'b1111 : 4'b0000;



wire [31:0] wchnl_resp;

axis_s axis_resp ( .areset_n(aresetn), .aclk(aclk),
					.data		(wchnl_resp),
					.ready 		(app_wen),
					
					.tready 	(m_axi_bready),
					.tvalid		(m_axi_bvalid),
					.tlast		(m_axi_bvalid),
					.tdata		( {30'b0,m_axi_bresp} ),
					
					.finish		(wresp_slave)
					);
					
assign wresp_slave_final= wresp_slave && (wchnl_resp[1:0] ==2'b00 || wchnl_resp[1:0] ==2'b01 );
					
assign app_wdone = waddr_done && wdata_done && wresp_slave_final ;
assign app_werror = wresp_slave && (wchnl_resp[1:0] ==2'b10 || wchnl_resp[1:0] ==2'b11 );


wire raddr_done,rdata_done;

assign m_axi_arprot = 1'b0;


axis_m axis_raddr ( .areset_n(aresetn), .aclk(aclk), 
					.data		(app_raddr), 
					.send		(app_ren),
					
					.tready		(m_axi_arready), 
					.tvalid		(m_axi_arvalid),
					.tlast		(m_axi_arvalid), 
					.tdata		(m_axi_araddr),
					
					.finish		(raddr_done)
			);


axis_s axis_rdata ( .areset_n(aresetn), .aclk(aclk),
					.data		(app_rdata),
					.ready 		(app_ren),
					
					.tready 	(m_axi_rready),
					.tvalid		(m_axi_rvalid),
					.tlast		(m_axi_rvalid),
					.tdata		(m_axi_rdata ),
					
					.finish		(rdata_done)
			);

assign app_rdone = raddr_done && rdata_done && (m_axi_rresp[1:0] ==2'b00 || m_axi_rresp[1:0] ==2'b01 );
assign app_rerror = wresp_slave && (m_axi_rresp[1:0] ==2'b10 || m_axi_rresp[1:0] ==2'b11 );
	

endmodule