data/full_repos/permissive/110151336/lab_05/src/09_full_adder/common/full_adder_structural.v
data/verilator_xmls/404f5445-1820-4d67-b541-16dec7a26261.xml
module full_adder_structural
(
    input wire  x, y, carry_in,
    output wire z, carry_out
);
    wire [2:0] t;

    xor(t[0], x, y);
    xor(z, t[0], carry_in);
    and(t[1], x, y);
    and(t[2], t[0], carry_in);
    or (carry_out, t[1], t[2]);
    
endmodule
module full_adder_structural
(
    input wire  x, y, carry_in,
    output wire z, carry_out
);

    wire [2:0] t;

    xor(t[0], x, y);
    xor(z, t[0], carry_in);
    and(t[1], x, y);
    and(t[2], t[0], carry_in);
    or (carry_out, t[1], t[2]);
    
endmodule