data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_serializer_eof.v
1: b"%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_serializer_eof.v:56: Cannot find file containing module: 'stream_serializer'\n  stream_serializer #(\n  ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream,data/full_repos/permissive/181738725/stream_serializer\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream,data/full_repos/permissive/181738725/stream_serializer.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream,data/full_repos/permissive/181738725/stream_serializer.sv\n             stream_serializer\n             stream_serializer.v\n             stream_serializer.sv\n             obj_dir/stream_serializer\n             obj_dir/stream_serializer.v\n             obj_dir/stream_serializer.sv\n%Error: Exiting due to 1 error(s)\n"
module stream_serializer_eof #(
  parameter DataBits = 8,
  parameter Ratio = 2)
(
  input                      clk,
  input                      rst,

  input                      in_valid,
  output                     in_ready,
  input [Ratio*DataBits-1:0] in_data,
  input                      in_eof,

  output                     out_valid,
  input                      out_ready,
  output [DataBits-1:0]      out_data,
  output                     out_eof
);



  reg [Ratio*(DataBits+1)-1:0] in_data_i;
  reg                          fill;
  integer                      i;
  always @(*) begin
    for (i=0; i < Ratio; i=i+1) begin
      fill = (i==Ratio-1) ? in_eof : 1'b0;
      in_data_i[i*(DataBits+1) +: (DataBits+1)] = {fill, in_data[i*DataBits +: DataBits]};
    end
  end


  stream_serializer #(
    .DataBits (DataBits+1),
    .Ratio    (Ratio))
  ser (
    .rst       (rst),
    .clk       (clk),
    .in_valid  (in_valid),
    .in_ready  (in_ready),
    .in_data   (in_data_i),
    .out_valid (out_valid),
    .out_ready (out_ready),
    .out_data  ({out_eof, out_data}));

endmodule
module stream_serializer_eof #(
  parameter DataBits = 8,
  parameter Ratio = 2)
(
  input                      clk,
  input                      rst,

  input                      in_valid,
  output                     in_ready,
  input [Ratio*DataBits-1:0] in_data,
  input                      in_eof,

  output                     out_valid,
  input                      out_ready,
  output [DataBits-1:0]      out_data,
  output                     out_eof
);




  reg [Ratio*(DataBits+1)-1:0] in_data_i;
  reg                          fill;
  integer                      i;
  always @(*) begin
    for (i=0; i < Ratio; i=i+1) begin
      fill = (i==Ratio-1) ? in_eof : 1'b0;
      in_data_i[i*(DataBits+1) +: (DataBits+1)] = {fill, in_data[i*DataBits +: DataBits]};
    end
  end


  stream_serializer #(
    .DataBits (DataBits+1),
    .Ratio    (Ratio))
  ser (
    .rst       (rst),
    .clk       (clk),
    .in_valid  (in_valid),
    .in_ready  (in_ready),
    .in_data   (in_data_i),
    .out_valid (out_valid),
    .out_ready (out_ready),
    .out_data  ({out_eof, out_data}));

endmodule