data/full_repos/permissive/162646941/src/shift_reg.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/162646941/src/shift_reg.v:13: Cannot find file containing module: 'flipflop'\n   flipflop u0 (clk,din,inter[i]);\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162646941/src,data/full_repos/permissive/162646941/flipflop\n             data/full_repos/permissive/162646941/src,data/full_repos/permissive/162646941/flipflop.v\n             data/full_repos/permissive/162646941/src,data/full_repos/permissive/162646941/flipflop.sv\n             flipflop\n             flipflop.v\n             flipflop.sv\n             obj_dir/flipflop\n             obj_dir/flipflop.v\n             obj_dir/flipflop.sv\n%Error: data/full_repos/permissive/162646941/src/shift_reg.v:17: Cannot find file containing module: 'flipflop'\n   flipflop ux (clk,inter[i-1],inter[i]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/162646941/src/shift_reg.v:21: Cannot find file containing module: 'flipflop'\n   flipflop u15 (clk,inter[i-1],dout);\n   ^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module shift_reg(clk,din,dout);

	input clk,din;
	output dout;
	
	wire [14:0] inter;
	
	genvar i;	
	generate 
	for(i=0;i<16;i=i+1) begin : genfor
		
		if(i==0) begin
			flipflop u0 (clk,din,inter[i]);
		end

		if(i>0 && i<15) begin
			flipflop ux (clk,inter[i-1],inter[i]);
		end

		if(i==15) begin
			flipflop u15 (clk,inter[i-1],dout);
		end
	
	end
	endgenerate

endmodule
module shift_reg(clk,din,dout);


	input clk,din;
	output dout;
	
	wire [14:0] inter;
	
	genvar i;	
	generate 
	for(i=0;i<16;i=i+1) begin : genfor
		
		if(i==0) begin
			flipflop u0 (clk,din,inter[i]);
		end

		if(i>0 && i<15) begin
			flipflop ux (clk,inter[i-1],inter[i]);
		end

		if(i==15) begin
			flipflop u15 (clk,inter[i-1],dout);
		end
	
	end
	endgenerate

endmodule