data/full_repos/permissive/197806087/booth-multiplier/booth.v
data/verilator_xmls/6d2f77ec-1f65-4bac-a1c2-66e51b3fab2e.xml
module booth #(parameter OPERAND_BITS = 4) (
        input wire clk,
        input wire [OPERAND_BITS - 1:0] mul1,
        input wire [OPERAND_BITS - 1:0] mul2,




        output wire [2 * OPERAND_BITS - 1:0] res_out,
        output reg ready,
        output wire [2 * OPERAND_BITS - 1:0] comp
        );
    localparam N_BITS = $clog2(OPERAND_BITS + 1);
    reg [OPERAND_BITS - 1:0] A;
    reg [OPERAND_BITS - 1:0] Q;
    reg q0;
    reg [OPERAND_BITS - 1:0] M;
    reg [OPERAND_BITS - 1:0] mul2_mem;
    reg [N_BITS - 1:0] n;




    assign res_out = {A, Q};
    wire [1:0] op;
    assign op = {Q[0], q0};
    wire [2 * OPERAND_BITS:0] test;
    assign test = {A, Q, q0};
    assign comp = ~(res_out) + 1'b1;
    initial begin
        n <= OPERAND_BITS + 1;
    end
    always @(posedge clk) begin
        if (n == OPERAND_BITS + 1) begin
            A <= 0;
            Q <= mul2;
            q0 <= 1'b0;
            M <= mul1;
            mul2_mem <= mul2;
        end
        if (ready && ((mul1 != M) || (mul2 != mul2_mem))) begin
            ready = 0;
            n = OPERAND_BITS + 1;
            A <= 0;
            Q <= mul2;
            q0 <= 1'b0;
            M <= mul1;
            mul2_mem <= mul2;
        end
        if (n < OPERAND_BITS + 1 && n != 0) begin
            case(op)
                2'b01: A = A - M;
                2'b10: A = A + M;
                default: A = A;
            endcase
            {A, Q, q0} = {A, Q, q0} >> 1;
            A[OPERAND_BITS - 1] <= A[OPERAND_BITS - 2];
        end
        if(n <= 1) begin
            ready <= 1;
            n = 0;
        end
        else begin
            ready <= 0;
            n = n - 1;
        end
    end
endmodule
module booth #(parameter OPERAND_BITS = 4) (
        input wire clk,
        input wire [OPERAND_BITS - 1:0] mul1,
        input wire [OPERAND_BITS - 1:0] mul2,




        output wire [2 * OPERAND_BITS - 1:0] res_out,
        output reg ready,
        output wire [2 * OPERAND_BITS - 1:0] comp
        );

    localparam N_BITS = $clog2(OPERAND_BITS + 1);
    reg [OPERAND_BITS - 1:0] A;
    reg [OPERAND_BITS - 1:0] Q;
    reg q0;
    reg [OPERAND_BITS - 1:0] M;
    reg [OPERAND_BITS - 1:0] mul2_mem;
    reg [N_BITS - 1:0] n;




    assign res_out = {A, Q};
    wire [1:0] op;
    assign op = {Q[0], q0};
    wire [2 * OPERAND_BITS:0] test;
    assign test = {A, Q, q0};
    assign comp = ~(res_out) + 1'b1;
    initial begin
        n <= OPERAND_BITS + 1;
    end
    always @(posedge clk) begin
        if (n == OPERAND_BITS + 1) begin
            A <= 0;
            Q <= mul2;
            q0 <= 1'b0;
            M <= mul1;
            mul2_mem <= mul2;
        end
        if (ready && ((mul1 != M) || (mul2 != mul2_mem))) begin
            ready = 0;
            n = OPERAND_BITS + 1;
            A <= 0;
            Q <= mul2;
            q0 <= 1'b0;
            M <= mul1;
            mul2_mem <= mul2;
        end
        if (n < OPERAND_BITS + 1 && n != 0) begin
            case(op)
                2'b01: A = A - M;
                2'b10: A = A + M;
                default: A = A;
            endcase
            {A, Q, q0} = {A, Q, q0} >> 1;
            A[OPERAND_BITS - 1] <= A[OPERAND_BITS - 2];
        end
        if(n <= 1) begin
            ready <= 1;
            n = 0;
        end
        else begin
            ready <= 0;
            n = n - 1;
        end
    end
endmodule