data/full_repos/permissive/21051978/src/control.v
 line:46: before: ")"
1: b"%Error: data/full_repos/permissive/21051978/src/control.v:46: Define or directive not defined: '`aa'\n       else if (ppp == `aa)\n                       ^~~\n%Error: data/full_repos/permissive/21051978/src/control.v:46: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n       else if (ppp == `aa)\n                          ^\n%Error: data/full_repos/permissive/21051978/src/control.v:48: Define or directive not defined: '`uu'\n       else if (ppp == `uu)\n                       ^~~\n%Error: data/full_repos/permissive/21051978/src/control.v:50: Define or directive not defined: '`dd'\n       else if (ppp == `dd)\n                       ^~~\n%Error: data/full_repos/permissive/21051978/src/control.v:52: Define or directive not defined: '`ee'\n                                                            : ... Suggested alternative: '`else'\n       else if (ppp == `ee)\n                       ^~~\n%Error: data/full_repos/permissive/21051978/src/control.v:54: Define or directive not defined: '`w8'\n           if (ww==`w8)\n                   ^~~\n%Error: data/full_repos/permissive/21051978/src/control.v:56: Define or directive not defined: '`w16'\n           if (ww==`w16)\n                   ^~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:56: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n           if (ww==`w16)\n                       ^\n%Error: data/full_repos/permissive/21051978/src/control.v:58: Define or directive not defined: '`w32'\n           if (ww==`w32)\n                   ^~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:58: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n           if (ww==`w32)\n                       ^\n%Error: data/full_repos/permissive/21051978/src/control.v:61: Define or directive not defined: '`oo'\n        else if (ppp == `oo)\n                        ^~~\n%Error: data/full_repos/permissive/21051978/src/control.v:63: Define or directive not defined: '`w8'\n           if (ww==`w8)\n                   ^~~\n%Error: data/full_repos/permissive/21051978/src/control.v:65: Define or directive not defined: '`w16'\n           if (ww==`w16)\n                   ^~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:65: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n           if (ww==`w16)\n                       ^\n%Error: data/full_repos/permissive/21051978/src/control.v:67: Define or directive not defined: '`w32'\n           if (ww==`w32)\n                   ^~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:67: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n           if (ww==`w32)\n                       ^\n%Error: data/full_repos/permissive/21051978/src/control.v:70: Define or directive not defined: '`mm'\n        else if (ppp == `mm)\n                        ^~~\n%Error: data/full_repos/permissive/21051978/src/control.v:72: Define or directive not defined: '`w8'\n           if (ww==`w8)\n                   ^~~\n%Error: data/full_repos/permissive/21051978/src/control.v:74: Define or directive not defined: '`w16'\n           if (ww==`w16)\n                   ^~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:74: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n           if (ww==`w16)\n                       ^\n%Error: data/full_repos/permissive/21051978/src/control.v:76: Define or directive not defined: '`w32'\n           if (ww==`w32)\n                   ^~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:76: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n           if (ww==`w32)\n                       ^\n%Error: data/full_repos/permissive/21051978/src/control.v:79: Define or directive not defined: '`ll'\n        else if (ppp == `ll)\n                        ^~~\n%Error: data/full_repos/permissive/21051978/src/control.v:81: Define or directive not defined: '`w8'\n           if (ww==`w8)\n                   ^~~\n%Error: data/full_repos/permissive/21051978/src/control.v:83: Define or directive not defined: '`w16'\n           if (ww==`w16)\n                   ^~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:83: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n           if (ww==`w16)\n                       ^\n%Error: data/full_repos/permissive/21051978/src/control.v:85: Define or directive not defined: '`w32'\n           if (ww==`w32)\n                   ^~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:85: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n           if (ww==`w32)\n                       ^\n%Error: data/full_repos/permissive/21051978/src/control.v:99: syntax error, unexpected '=', expecting IDENTIFIER\n           aluop=instr[26:31];  \n                ^\n%Error: data/full_repos/permissive/21051978/src/control.v:100: Define or directive not defined: '`rd1wr1'\n           regop=`rd1wr1;  \n                 ^~~~~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:114: syntax error, unexpected '=', expecting IDENTIFIER\n               aluop=instr[26:31];  \n                    ^\n%Error: data/full_repos/permissive/21051978/src/control.v:115: Define or directive not defined: '`rd1wr1'\n               regop=`rd1wr1;  \n                     ^~~~~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:126: syntax error, unexpected '=', expecting IDENTIFIER\n               aluop=instr[26:31];  \n                    ^\n%Error: data/full_repos/permissive/21051978/src/control.v:127: Define or directive not defined: '`rd1wr1'\n               regop=`rd1wr1;  \n                     ^~~~~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:138: syntax error, unexpected '=', expecting IDENTIFIER\n               aluop=instr[26:31];  \n                    ^\n%Error: data/full_repos/permissive/21051978/src/control.v:139: Define or directive not defined: '`rd2wr1'\n               regop=`rd2wr1;  \n                     ^~~~~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:151: syntax error, unexpected '=', expecting IDENTIFIER\n           aluop=`alunop;  \n                ^\n%Error: data/full_repos/permissive/21051978/src/control.v:151: Define or directive not defined: '`alunop'\n           aluop=`alunop;  \n                 ^~~~~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:152: Define or directive not defined: '`rd2wr0'\n           regop=`rd2wr0;  \n                 ^~~~~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:163: syntax error, unexpected '=', expecting IDENTIFIER\n           aluop=`alunop;  \n                ^\n%Error: data/full_repos/permissive/21051978/src/control.v:163: Define or directive not defined: '`alunop'\n           aluop=`alunop;  \n                 ^~~~~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:164: Define or directive not defined: '`rd0wr1'\n           regop=`rd0wr1;  \n                 ^~~~~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:176: syntax error, unexpected '=', expecting IDENTIFIER\n           aluop=`alunop;\n                ^\n%Error: data/full_repos/permissive/21051978/src/control.v:176: Define or directive not defined: '`alunop'\n           aluop=`alunop;\n                 ^~~~~~~\n%Error: data/full_repos/permissive/21051978/src/control.v:177: Define or directive not defined: '`regnop'\n           regop=`regnop;\n                 ^~~~~~~\n%Error: Cannot continue\n"
module control(instr, 
   aluop, ww, 
   memEn, memWrEn, maddr, wbyteen,
   regop, rrdaddra, rrdaddrb, rwraddrd,
   reginmuxop, 
   aluinmuxop,
   immediate);


   input [0:31] instr;
   

   output [0:4] aluop, rrdaddra, rrdaddrb, rwraddrd;
   output [0:2] regop;
   output [0:1] ww;
   output [0:20] maddr;
   output memEn, memWrEn;
   output reginmuxop, aluinmuxop;
   output [0:15] wbyteen;
   output [0:127] immediate;
   

   reg [0:4] aluop, rrdaddra, rrdaddrb, rwraddrd;
   reg [0:2] ppp, regop;
   reg [0:1] ww, memop;
   reg [0:20] maddr;
   reg memEn, memWrEn;
   reg reginmuxop, aluinmuxop;
   reg [0:15] wbyteen;
   reg [0:127] immediate;
   

   parameter zero = 1'b0;
   parameter one = 1'b1;

   always @ (ppp or ww or instr)
       begin
       if (instr[5]== 1'b1)
       begin
           wbyteen=16'b1111111111111111;
       end
       else if (ppp == `aa)
           wbyteen=16'b1111111111111111;
       else if (ppp == `uu)
           wbyteen=16'b1111111100000000;
       else if (ppp == `dd)
           wbyteen=16'b0000000011111111;
       else if (ppp == `ee)
           begin
           if (ww==`w8)
               wbyteen=16'b1010101010101010;
           if (ww==`w16)
               wbyteen=16'b1100110011001100;
           if (ww==`w32)
               wbyteen=16'b1111000011110000;
           end
        else if (ppp == `oo)
           begin
           if (ww==`w8)
               wbyteen=16'b0101010101010101;
           if (ww==`w16)
               wbyteen=16'b0011001100110011;
           if (ww==`w32)
               wbyteen=16'b0000111100001111;
           end
        else if (ppp == `mm)
           begin
           if (ww==`w8)
               wbyteen=16'b1000000000000000;
           if (ww==`w16)
               wbyteen=16'b1100000000000000;
           if (ww==`w32)
               wbyteen=16'b1111000000000000;
           end
        else if (ppp == `ll)
           begin
           if (ww==`w8)
               wbyteen=16'b0000000000000001;
           if (ww==`w16)
               wbyteen=16'b0000000000000011;
           if (ww==`w32)
               wbyteen=16'b0000000000001111;
           end
      end

   always @ (instr)
       begin
       immediate={instr[16:20], {123{zero}}};
       ppp=instr[21:23];
       ww=instr[24:25];
       maddr=instr[11:31];
       rwraddrd=instr[6:10];
       if (instr[2] == 1'b1)
           begin
           aluop=instr[26:31];
           regop=`rd1wr1;
           rrdaddra=instr[11:15];
           rrdaddrb=instr[16:20];

           memEn=zero;
           memWrEn=zero;
           aluinmuxop=one;
           reginmuxop=zero;
           end

       else if (instr[3] == 1'b1)
           begin
           if ({instr[26:28], instr[31]} == 4'b0101)
               begin
               aluop=instr[26:31];
               regop=`rd1wr1;
               rrdaddra=instr[11:15];
               rrdaddrb=instr[16:20];

               memEn=zero;
               memWrEn=zero;
               aluinmuxop=one;
               reginmuxop=zero;
               end
           else if (instr[26:31]==6'b001000)
               begin
               aluop=instr[26:31];
               regop=`rd1wr1;
               rrdaddra=instr[11:15];
               rrdaddrb=instr[16:20];

               memEn=zero;
               memWrEn=zero;
               aluinmuxop=one;
               reginmuxop=zero;
               end
           else
               begin
               aluop=instr[26:31];
               regop=`rd2wr1;
               rrdaddra=instr[11:15];
               rrdaddrb=instr[16:20];

               memEn=zero;
               memWrEn=zero;
               aluinmuxop=zero;
               reginmuxop=zero;
               end
           end
       else if (instr[4]==1'b1)
           begin
           aluop=`alunop;
           regop=`rd2wr0;
           rrdaddra=instr[6:10];
           rrdaddrb=instr[6:10];

           memEn=one;
           memWrEn=one;
           aluinmuxop=zero;
           reginmuxop=zero;
           end
       else if (instr[5]==1'b1)
           begin
           aluop=`alunop;
           regop=`rd0wr1;
           rrdaddra=instr[11:15];
           rrdaddrb=instr[16:20];

           memEn=one;
           memWrEn=zero;
           aluinmuxop=zero;
           reginmuxop=one;
           end

       else
           begin
           aluop=`alunop;
           regop=`regnop;
           rrdaddra=instr[11:15];
           rrdaddrb=instr[16:20];

           memEn=zero;
           memWrEn=zero;
           reginmuxop=zero;
           aluinmuxop=zero;
           end
       end

endmodule
module control(instr, 
   aluop, ww, 
   memEn, memWrEn, maddr, wbyteen,
   regop, rrdaddra, rrdaddrb, rwraddrd,
   reginmuxop, 
   aluinmuxop,
   immediate);



   input [0:31] instr;
   

   output [0:4] aluop, rrdaddra, rrdaddrb, rwraddrd;
   output [0:2] regop;
   output [0:1] ww;
   output [0:20] maddr;
   output memEn, memWrEn;
   output reginmuxop, aluinmuxop;
   output [0:15] wbyteen;
   output [0:127] immediate;
   

   reg [0:4] aluop, rrdaddra, rrdaddrb, rwraddrd;
   reg [0:2] ppp, regop;
   reg [0:1] ww, memop;
   reg [0:20] maddr;
   reg memEn, memWrEn;
   reg reginmuxop, aluinmuxop;
   reg [0:15] wbyteen;
   reg [0:127] immediate;
   

   parameter zero = 1'b0;
   parameter one = 1'b1;

   always @ (ppp or ww or instr)
       begin
       if (instr[5]== 1'b1)
       begin
           wbyteen=16'b1111111111111111;
       end
       else if (ppp == `aa)
           wbyteen=16'b1111111111111111;
       else if (ppp == `uu)
           wbyteen=16'b1111111100000000;
       else if (ppp == `dd)
           wbyteen=16'b0000000011111111;
       else if (ppp == `ee)
           begin
           if (ww==`w8)
               wbyteen=16'b1010101010101010;
           if (ww==`w16)
               wbyteen=16'b1100110011001100;
           if (ww==`w32)
               wbyteen=16'b1111000011110000;
           end
        else if (ppp == `oo)
           begin
           if (ww==`w8)
               wbyteen=16'b0101010101010101;
           if (ww==`w16)
               wbyteen=16'b0011001100110011;
           if (ww==`w32)
               wbyteen=16'b0000111100001111;
           end
        else if (ppp == `mm)
           begin
           if (ww==`w8)
               wbyteen=16'b1000000000000000;
           if (ww==`w16)
               wbyteen=16'b1100000000000000;
           if (ww==`w32)
               wbyteen=16'b1111000000000000;
           end
        else if (ppp == `ll)
           begin
           if (ww==`w8)
               wbyteen=16'b0000000000000001;
           if (ww==`w16)
               wbyteen=16'b0000000000000011;
           if (ww==`w32)
               wbyteen=16'b0000000000001111;
           end
      end

   always @ (instr)
       begin
       immediate={instr[16:20], {123{zero}}};
       ppp=instr[21:23];
       ww=instr[24:25];
       maddr=instr[11:31];
       rwraddrd=instr[6:10];
       if (instr[2] == 1'b1)
           begin
           aluop=instr[26:31];
           regop=`rd1wr1;
           rrdaddra=instr[11:15];
           rrdaddrb=instr[16:20];

           memEn=zero;
           memWrEn=zero;
           aluinmuxop=one;
           reginmuxop=zero;
           end

       else if (instr[3] == 1'b1)
           begin
           if ({instr[26:28], instr[31]} == 4'b0101)
               begin
               aluop=instr[26:31];
               regop=`rd1wr1;
               rrdaddra=instr[11:15];
               rrdaddrb=instr[16:20];

               memEn=zero;
               memWrEn=zero;
               aluinmuxop=one;
               reginmuxop=zero;
               end
           else if (instr[26:31]==6'b001000)
               begin
               aluop=instr[26:31];
               regop=`rd1wr1;
               rrdaddra=instr[11:15];
               rrdaddrb=instr[16:20];

               memEn=zero;
               memWrEn=zero;
               aluinmuxop=one;
               reginmuxop=zero;
               end
           else
               begin
               aluop=instr[26:31];
               regop=`rd2wr1;
               rrdaddra=instr[11:15];
               rrdaddrb=instr[16:20];

               memEn=zero;
               memWrEn=zero;
               aluinmuxop=zero;
               reginmuxop=zero;
               end
           end
       else if (instr[4]==1'b1)
           begin
           aluop=`alunop;
           regop=`rd2wr0;
           rrdaddra=instr[6:10];
           rrdaddrb=instr[6:10];

           memEn=one;
           memWrEn=one;
           aluinmuxop=zero;
           reginmuxop=zero;
           end
       else if (instr[5]==1'b1)
           begin
           aluop=`alunop;
           regop=`rd0wr1;
           rrdaddra=instr[11:15];
           rrdaddrb=instr[16:20];

           memEn=one;
           memWrEn=zero;
           aluinmuxop=zero;
           reginmuxop=one;
           end

       else
           begin
           aluop=`alunop;
           regop=`regnop;
           rrdaddra=instr[11:15];
           rrdaddrb=instr[16:20];

           memEn=zero;
           memWrEn=zero;
           reginmuxop=zero;
           aluinmuxop=zero;
           end
       end

endmodule