data/full_repos/permissive/216654561/HW/Pcores/DDR_Controller/ddr_control_v1.00-b.v
 line:22: before: "ODT"
1: b"%Error: data/full_repos/permissive/216654561/HW/Pcores/DDR_Controller/ddr_control_v1.00-b.v:26: syntax error, unexpected '[', expecting IDENTIFIER or '=' or do or final\ninput [3:0]com,[13:0]add,DM,[2:0]AB_s,ck_s;  \n               ^\n%Error: data/full_repos/permissive/216654561/HW/Pcores/DDR_Controller/ddr_control_v1.00-b.v:29: syntax error, unexpected '[', expecting IDENTIFIER or '=' or do or final\ninout  [7:0]DQ,[7:0]data,DQS_DQS_m,DQS_DQS_s;\n               ^\n%Error: data/full_repos/permissive/216654561/HW/Pcores/DDR_Controller/ddr_control_v1.00-b.v:50: syntax error, unexpected '[', expecting IDENTIFIER or '=' or do or final\ninput [31:0]WDATA,[3:0]WSTRB;\n                  ^\n%Error: Exiting due to 3 error(s)\n"
module ddr_control(ck_s ODT ,CK ,CK_ ,CKE ,CS_ ,RAS_ ,CAS_ ,WE_ ,A ,AB_s,AB,DQ ,DQS_DQS_m ,RDQS_ ,RDQS ,DM ,com ,data ,add,ACLK,ARESETN,ARADDR,ARVA_ID,ARREADY,RDATA,RRESP,RVALID,RREADY,AWADDR,AWVALID,AWREADY,WDATA,WSTRB,BRESP,BVALID,BREADY);



input [3:0]com,[13:0]add,DM,[2:0]AB_s,ck_s;


inout  [7:0]DQ,[7:0]data,DQS_DQS_m,DQS_DQS_s;
output reg ODT,CK,CK_,CKE,CS_,RAS_,CAS_,WE_,A,AB,RDQS_,RDQS;




input ACLK,ARESETN;


input [31:0]ARADDR,ARVALID;
output ARREADY;


input RREADY;
output [31:0]RDATA,RRESP,RVALID;


input [31:0]AWADDR,AWVALID;
output AWREADY;


input [31:0]WDATA,[3:0]WSTRB;


input BREADY;
output BRESP,BVALID;



endmodule
module ddr_control(ck_s ODT ,CK ,CK_ ,CKE ,CS_ ,RAS_ ,CAS_ ,WE_ ,A ,AB_s,AB,DQ ,DQS_DQS_m ,RDQS_ ,RDQS ,DM ,com ,data ,add,ACLK,ARESETN,ARADDR,ARVA_ID,ARREADY,RDATA,RRESP,RVALID,RREADY,AWADDR,AWVALID,AWREADY,WDATA,WSTRB,BRESP,BVALID,BREADY);




input [3:0]com,[13:0]add,DM,[2:0]AB_s,ck_s;


inout  [7:0]DQ,[7:0]data,DQS_DQS_m,DQS_DQS_s;
output reg ODT,CK,CK_,CKE,CS_,RAS_,CAS_,WE_,A,AB,RDQS_,RDQS;




input ACLK,ARESETN;


input [31:0]ARADDR,ARVALID;
output ARREADY;


input RREADY;
output [31:0]RDATA,RRESP,RVALID;


input [31:0]AWADDR,AWVALID;
output AWREADY;


input [31:0]WDATA,[3:0]WSTRB;


input BREADY;
output BRESP,BVALID;



endmodule