data/full_repos/permissive/219917900/tx_rtl_files/rgb2bram.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/219917900/tx_rtl_files/rgb2bram.v:169: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'col_count\' generates 9 bits.\n                                                                                : ... In instance rgb2bram\n                        bramaddr24b <= bramaddr24b_ini + col_count;\n                                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module rgb2bram #(
 parameter ACTIVE_COLS = 320,
 parameter ACTIVE_ROWS = 180)

(
    input            clk125MHz,
    input wire rst,
    (* mark_debug = "true" *)	input pclk,
    (* mark_debug = "true" *)	input wire i_Hsync,
    (* mark_debug = "true" *)	input wire i_Vsync,
    (* mark_debug = "true" *) input wire [23:0] data24b,
    (* mark_debug = "true" *)	input wire vde,


    (* mark_debug = "true" *) output reg enout,
    (* mark_debug = "true" *) output reg [15:0] bramaddr24b = 'd0,
    (* mark_debug = "true" *) output reg [7:0] rgb_r,rgb_g,rgb_b,
    (* mark_debug = "true" *) output wire start_frame
 );  

(* mark_debug = "true" *) reg [9:0] o_Row_Count = 'd0;
(* mark_debug = "true" *) reg [9:0] o_Col_Count = 'd0;





(* mark_debug  = "true" *) reg [15:0] mitai_address;

reg [15:0] bramaddr24b_ini = 'd0;
wire [15:0] bramaddr24b_ini_next = bramaddr24b_ini < (ACTIVE_COLS*(ACTIVE_ROWS-1'b1)) ? bramaddr24b_ini + ACTIVE_COLS : bramaddr24b_ini;




(* mark_debug = "true" *) reg [13:0] row_count = 'd0;

wire hsync = i_Hsync;
wire vsync = i_Vsync;
reg [1:0] vsync_sr = 'b0;
reg [1:0] hsync_sr = 'b0;
wire hsyncf = (hsync_sr==2'b10);
wire vsyncf = (vsync_sr==2'b10);
reg [1:0] vsync_count = 'b0;
reg [1:0] pix_count = 'b0;
localparam pix_count_max = 2'b01;
wire [1:0] pix_count_next = ( pix_count == pix_count_max ? 2'b00 : pix_count + 1'b1);
wire pix_count_en = pix_count=='b0;
localparam vsync_count_max = 2'b10;
wire [1:0] vsync_count_next = (vsync_count==vsync_count_max ? 'b0 : vsync_count + 1'b1);
wire vsync_count_en = vsync_count=='b0;
reg [1:0] hsync_count = 'b0;
localparam hsync_count_max = 2'b01;
wire [1:0] hsync_count_next = ((hsync_count==hsync_count_max) ? 'b0 : hsync_count + 1'b1);
wire hsync_count_en = hsync_count=='b0;


reg [23:0] data_sampl;
reg [1:0] vsync_count_en_sr;
wire vsync_count_en_f = vsync_count_en_sr==2'b10;
reg [1:0] hsync_count_en_sr;
wire hsync_count_en_f = hsync_count_en_sr==2'b10;
(* mark_debug = "true" *) reg [2:0] cstate = 'd0;
localparam state_init = 0;
localparam state_start = 1;
localparam state_end = 2;

reg [8:0] col_count = 'd0;
wire [8:0] col_count_next = (col_count==ACTIVE_COLS-1'b1) ? col_count : col_count + 1'b1 ;
wire oneline_done = (col_count==(ACTIVE_COLS - 1'b1));



always @(posedge pclk) begin
    if (rst)begin


        rgb_r='d0;
        rgb_g='d0;
        rgb_b='d0;
        vsync_sr='d0;
        hsync_sr='d0;
        vsync_count='d0;
        pix_count='d0;
        hsync_count='d0;
        data_sampl='d0;
        vsync_count = 'd0;
        vsync_count_en_sr='d0;
        hsync_count_en_sr='d0;
        
    end
    else begin
    rgb_r <= data_sampl[23:16];
    rgb_g <= data_sampl[15:8];
    rgb_b <= data_sampl[7:0];
    mitai_address = bramaddr24b;
    data_sampl <= data24b;
    hsync_count_en_sr <= {hsync_count_en_sr[0],hsync_count_en};
    vsync_count_en_sr <= {vsync_count_en_sr[0],vsync_count_en};
    vsync_sr <= {vsync_sr[0],vsync};
    hsync_sr <= {hsync_sr[0],hsync};
    if (vde) begin
        pix_count <= pix_count_next;
    end
    if (vsyncf) begin
        vsync_count <= vsync_count_next;
    end
    if (!vsync) begin
        hsync_count <= 0;
        row_count <= 0;
    end
    else begin
        if (hsyncf) begin
            hsync_count <= hsync_count_next;
        end
        else begin
            if (!hsync) begin
                row_count <= 0;
            end
            else begin
                row_count <= row_count + 1'b1;
            end
        end
        
    end
end
end



always @(posedge pclk) begin
    if (rst) begin
        cstate='d0;
        bramaddr24b='d0;
        col_count='d0;
    end
    else begin
    case (cstate)
        state_init:
        begin
            enout <= 'b0;
            if (vsyncf) begin
                cstate <= state_start;
                bramaddr24b_ini <= 'd0;
                bramaddr24b <= 'd0;
                
            end
        end
        state_start:
        begin
            
            if ( bramaddr24b_ini == (ACTIVE_COLS * (ACTIVE_ROWS-1'b1)) && oneline_done) begin
                cstate <= state_end;
                enout<='b0;
                bramaddr24b_ini <= 'd0;
                col_count <= 'd0;
                
            end
            else begin
                if (hsync_count_en_f) begin
                    bramaddr24b_ini <= bramaddr24b_ini_next;
                    bramaddr24b <= bramaddr24b_ini;
                    col_count <= 'd0;
                end
                else begin
                    if (vde && hsync_count_en && pix_count_en) begin
                        enout <= 1'b1;
                        bramaddr24b <= bramaddr24b_ini + col_count;
                        col_count <= col_count_next;
                    end
                    else begin
                        enout <= 1'b0;
                    end
                end
            end
        end
        state_end:
        begin
            enout <= 'b0;
            if (vsyncf) begin
                cstate <= state_init;
            end
        end
    endcase
end
end


endmodule
module rgb2bram #(
 parameter ACTIVE_COLS = 320,
 parameter ACTIVE_ROWS = 180)

(
    input            clk125MHz,
    input wire rst,
    (* mark_debug = "true" *)	input pclk,
    (* mark_debug = "true" *)	input wire i_Hsync,
    (* mark_debug = "true" *)	input wire i_Vsync,
    (* mark_debug = "true" *) input wire [23:0] data24b,
    (* mark_debug = "true" *)	input wire vde,


    (* mark_debug = "true" *) output reg enout,
    (* mark_debug = "true" *) output reg [15:0] bramaddr24b = 'd0,
    (* mark_debug = "true" *) output reg [7:0] rgb_r,rgb_g,rgb_b,
    (* mark_debug = "true" *) output wire start_frame
 );
  

(* mark_debug = "true" *) reg [9:0] o_Row_Count = 'd0;
(* mark_debug = "true" *) reg [9:0] o_Col_Count = 'd0;





(* mark_debug  = "true" *) reg [15:0] mitai_address;

reg [15:0] bramaddr24b_ini = 'd0;
wire [15:0] bramaddr24b_ini_next = bramaddr24b_ini < (ACTIVE_COLS*(ACTIVE_ROWS-1'b1)) ? bramaddr24b_ini + ACTIVE_COLS : bramaddr24b_ini;




(* mark_debug = "true" *) reg [13:0] row_count = 'd0;

wire hsync = i_Hsync;
wire vsync = i_Vsync;
reg [1:0] vsync_sr = 'b0;
reg [1:0] hsync_sr = 'b0;
wire hsyncf = (hsync_sr==2'b10);
wire vsyncf = (vsync_sr==2'b10);
reg [1:0] vsync_count = 'b0;
reg [1:0] pix_count = 'b0;
localparam pix_count_max = 2'b01;
wire [1:0] pix_count_next = ( pix_count == pix_count_max ? 2'b00 : pix_count + 1'b1);
wire pix_count_en = pix_count=='b0;
localparam vsync_count_max = 2'b10;
wire [1:0] vsync_count_next = (vsync_count==vsync_count_max ? 'b0 : vsync_count + 1'b1);
wire vsync_count_en = vsync_count=='b0;
reg [1:0] hsync_count = 'b0;
localparam hsync_count_max = 2'b01;
wire [1:0] hsync_count_next = ((hsync_count==hsync_count_max) ? 'b0 : hsync_count + 1'b1);
wire hsync_count_en = hsync_count=='b0;


reg [23:0] data_sampl;
reg [1:0] vsync_count_en_sr;
wire vsync_count_en_f = vsync_count_en_sr==2'b10;
reg [1:0] hsync_count_en_sr;
wire hsync_count_en_f = hsync_count_en_sr==2'b10;
(* mark_debug = "true" *) reg [2:0] cstate = 'd0;
localparam state_init = 0;
localparam state_start = 1;
localparam state_end = 2;

reg [8:0] col_count = 'd0;
wire [8:0] col_count_next = (col_count==ACTIVE_COLS-1'b1) ? col_count : col_count + 1'b1 ;
wire oneline_done = (col_count==(ACTIVE_COLS - 1'b1));



always @(posedge pclk) begin
    if (rst)begin


        rgb_r='d0;
        rgb_g='d0;
        rgb_b='d0;
        vsync_sr='d0;
        hsync_sr='d0;
        vsync_count='d0;
        pix_count='d0;
        hsync_count='d0;
        data_sampl='d0;
        vsync_count = 'd0;
        vsync_count_en_sr='d0;
        hsync_count_en_sr='d0;
        
    end
    else begin
    rgb_r <= data_sampl[23:16];
    rgb_g <= data_sampl[15:8];
    rgb_b <= data_sampl[7:0];
    mitai_address = bramaddr24b;
    data_sampl <= data24b;
    hsync_count_en_sr <= {hsync_count_en_sr[0],hsync_count_en};
    vsync_count_en_sr <= {vsync_count_en_sr[0],vsync_count_en};
    vsync_sr <= {vsync_sr[0],vsync};
    hsync_sr <= {hsync_sr[0],hsync};
    if (vde) begin
        pix_count <= pix_count_next;
    end
    if (vsyncf) begin
        vsync_count <= vsync_count_next;
    end
    if (!vsync) begin
        hsync_count <= 0;
        row_count <= 0;
    end
    else begin
        if (hsyncf) begin
            hsync_count <= hsync_count_next;
        end
        else begin
            if (!hsync) begin
                row_count <= 0;
            end
            else begin
                row_count <= row_count + 1'b1;
            end
        end
        
    end
end
end



always @(posedge pclk) begin
    if (rst) begin
        cstate='d0;
        bramaddr24b='d0;
        col_count='d0;
    end
    else begin
    case (cstate)
        state_init:
        begin
            enout <= 'b0;
            if (vsyncf) begin
                cstate <= state_start;
                bramaddr24b_ini <= 'd0;
                bramaddr24b <= 'd0;
                
            end
        end
        state_start:
        begin
            
            if ( bramaddr24b_ini == (ACTIVE_COLS * (ACTIVE_ROWS-1'b1)) && oneline_done) begin
                cstate <= state_end;
                enout<='b0;
                bramaddr24b_ini <= 'd0;
                col_count <= 'd0;
                
            end
            else begin
                if (hsync_count_en_f) begin
                    bramaddr24b_ini <= bramaddr24b_ini_next;
                    bramaddr24b <= bramaddr24b_ini;
                    col_count <= 'd0;
                end
                else begin
                    if (vde && hsync_count_en && pix_count_en) begin
                        enout <= 1'b1;
                        bramaddr24b <= bramaddr24b_ini + col_count;
                        col_count <= col_count_next;
                    end
                    else begin
                        enout <= 1'b0;
                    end
                end
            end
        end
        state_end:
        begin
            enout <= 'b0;
            if (vsyncf) begin
                cstate <= state_init;
            end
        end
    endcase
end
end


endmodule