data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_to_seven.v
1: b'%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_to_seven.v:9: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h7e\' generates 7 bits.\n                                                                                            : ... In instance BCD_to_seven\n    4\'b0000: Sseg <= 7\'b1111110;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_to_seven.v:10: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h30\' generates 7 bits.\n                                                                                             : ... In instance BCD_to_seven\n    4\'b0001: Sseg <= 7\'b0110000;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_to_seven.v:11: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h6d\' generates 7 bits.\n                                                                                             : ... In instance BCD_to_seven\n    4\'b0010: Sseg <= 7\'b1101101;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_to_seven.v:12: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h79\' generates 7 bits.\n                                                                                             : ... In instance BCD_to_seven\n    4\'b0011: Sseg <= 7\'b1111001;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_to_seven.v:13: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h33\' generates 7 bits.\n                                                                                             : ... In instance BCD_to_seven\n    4\'b0100: Sseg <= 7\'b0110011;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_to_seven.v:14: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h5b\' generates 7 bits.\n                                                                                             : ... In instance BCD_to_seven\n    4\'b0101: Sseg <= 7\'b1011011;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_to_seven.v:15: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h5f\' generates 7 bits.\n                                                                                             : ... In instance BCD_to_seven\n    4\'b0110: Sseg <= 7\'b1011111;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_to_seven.v:16: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h72\' generates 7 bits.\n                                                                                             : ... In instance BCD_to_seven\n    4\'b0111: Sseg <= 7\'b1110010;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_to_seven.v:17: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h7f\' generates 7 bits.\n                                                                                             : ... In instance BCD_to_seven\n    4\'b1000: Sseg <= 7\'b1111111;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_to_seven.v:18: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h7b\' generates 7 bits.\n                                                                                             : ... In instance BCD_to_seven\n    4\'b1001: Sseg <= 7\'b1111011;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem5/BCD_to_seven.v:19: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n                                                                                             : ... In instance BCD_to_seven\n    default: Sseg <= {dummy};\n                  ^~\n%Error: Exiting due to 11 warning(s)\n'
module BCD_to_seven(binary,Sseg);

input [3:0]binary;
output reg [7:0]Sseg;
reg dummy;

always@(binary)
case (binary)
    4'b0000: Sseg <= 7'b1111110;
    4'b0001: Sseg <= 7'b0110000;
    4'b0010: Sseg <= 7'b1101101;
    4'b0011: Sseg <= 7'b1111001;
    4'b0100: Sseg <= 7'b0110011;
    4'b0101: Sseg <= 7'b1011011;
    4'b0110: Sseg <= 7'b1011111;
    4'b0111: Sseg <= 7'b1110010;
    4'b1000: Sseg <= 7'b1111111;
    4'b1001: Sseg <= 7'b1111011;
    default: Sseg <= {dummy};
endcase

endmodule
module BCD_to_seven(binary,Sseg);


input [3:0]binary;
output reg [7:0]Sseg;
reg dummy;

always@(binary)
case (binary)
    4'b0000: Sseg <= 7'b1111110;
    4'b0001: Sseg <= 7'b0110000;
    4'b0010: Sseg <= 7'b1101101;
    4'b0011: Sseg <= 7'b1111001;
    4'b0100: Sseg <= 7'b0110011;
    4'b0101: Sseg <= 7'b1011011;
    4'b0110: Sseg <= 7'b1011111;
    4'b0111: Sseg <= 7'b1110010;
    4'b1000: Sseg <= 7'b1111111;
    4'b1001: Sseg <= 7'b1111011;
    default: Sseg <= {dummy};
endcase

endmodule