data/full_repos/permissive/187199324/stannel/Enable_tb.v
 line:86: before: "begin"
1: b'%Error: data/full_repos/permissive/187199324/stannel/Enable_tb.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Enable_tb.v:6: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = clk !== 1\'b1;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/187199324/stannel/Enable_tb.v:11: Define or directive not defined: \'`ADDRESS_BITS\'\n  localparam addrBits = `ADDRESS_BITS;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable_tb.v:11: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam addrBits = `ADDRESS_BITS;\n                                     ^\n%Error: data/full_repos/permissive/187199324/stannel/Enable_tb.v:12: Define or directive not defined: \'`DATA_BITS\'\n  localparam dataBits = `DATA_BITS;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable_tb.v:12: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam dataBits = `DATA_BITS;\n                                  ^\n%Error: data/full_repos/permissive/187199324/stannel/Enable_tb.v:50: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Enable_tb.v:56: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable_tb.v:63: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Enable_tb.v:69: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable_tb.v:73: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("Enable_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Enable_tb.v:74: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, Enable_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Enable_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #2 enableWithNoSender;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Enable_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #2 enableWithSender;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Enable_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #2 $finish;\n    ^\n%Error: data/full_repos/permissive/187199324/stannel/Enable_tb.v:80: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n'
module Enable_tb();

  reg clk;
  always #1 clk = clk !== 1'b1;


  parameter romFile = "zeroes.hex";

  localparam addrBits = `ADDRESS_BITS;
  localparam dataBits = `DATA_BITS;

  reg  [addrBits-1:0] address;
  reg  [dataBits-1:0] dataIn;
  wire [dataBits-1:0] dataOut;
  reg                 readWriteMode;

  IceRam #(.addrBits(addrBits), .dataBits(dataBits), .romFile(romFile)) memory (
    .clk          (clk),
    .address      (address),
    .readWriteMode(readWriteMode),
    .dataIn       (dataIn),
    .dataOut      (dataOut)
  );


  reg                reset = 0;
  reg [addrBits-1:0] channel = 2;
  reg [addrBits-1:0] rxPid = 1;
  reg                finished;
  reg                rxCanReceive;

  Enable #(.addrBits(addrBits), .dataBits(dataBits)) e0 (
    .clk          (clk),
    .reset        (reset),
    .finished     (finished),
    .address      (address),
    .readWriteMode(readWriteMode),
    .dataOut      (dataOut),
    .dataIn       (dataIn),
    .channel      (channel),
    .rxPid        (rxPid),
    .rxCanReceive (rxCanReceive)
  );

  task enableWithNoSender;
    begin
      reset <= 1;
      @(posedge finished)
        begin
          reset <= 0;
          if (rxCanReceive) $error("Should not be able to receive");
          if (memory.ram[2] != rxPid) $error("Should have written rx pid to memory");
        end
    end
  endtask

  task enableWithSender;
    begin
      reset <= 1;
      memory.ram[2] <= 3;
      @(posedge finished)
        begin
          reset <= 0;
          if (!rxCanReceive) $error("Should be able to receive");
          if (memory.ram[2] != 3) $error("Should have retained sender in memory");
        end
    end
  endtask

  initial begin
    $dumpfile("Enable_tb.vcd");
    $dumpvars(0, Enable_tb);

    #2 enableWithNoSender;
    #2 enableWithSender;

    #2 $finish;
  end
endmodule
module Enable_tb();


  reg clk;
  always #1 clk = clk !== 1'b1;


  parameter romFile = "zeroes.hex";

  localparam addrBits = `ADDRESS_BITS;
  localparam dataBits = `DATA_BITS;

  reg  [addrBits-1:0] address;
  reg  [dataBits-1:0] dataIn;
  wire [dataBits-1:0] dataOut;
  reg                 readWriteMode;

  IceRam #(.addrBits(addrBits), .dataBits(dataBits), .romFile(romFile)) memory (
    .clk          (clk),
    .address      (address),
    .readWriteMode(readWriteMode),
    .dataIn       (dataIn),
    .dataOut      (dataOut)
  );


  reg                reset = 0;
  reg [addrBits-1:0] channel = 2;
  reg [addrBits-1:0] rxPid = 1;
  reg                finished;
  reg                rxCanReceive;

  Enable #(.addrBits(addrBits), .dataBits(dataBits)) e0 (
    .clk          (clk),
    .reset        (reset),
    .finished     (finished),
    .address      (address),
    .readWriteMode(readWriteMode),
    .dataOut      (dataOut),
    .dataIn       (dataIn),
    .channel      (channel),
    .rxPid        (rxPid),
    .rxCanReceive (rxCanReceive)
  );

  task enableWithNoSender;
    begin
      reset <= 1;
      @(posedge finished)
        begin
          reset <= 0;
          if (rxCanReceive) $error("Should not be able to receive");
          if (memory.ram[2] != rxPid) $error("Should have written rx pid to memory");
        end
    end
  endtask

  task enableWithSender;
    begin
      reset <= 1;
      memory.ram[2] <= 3;
      @(posedge finished)
        begin
          reset <= 0;
          if (!rxCanReceive) $error("Should be able to receive");
          if (memory.ram[2] != 3) $error("Should have retained sender in memory");
        end
    end
  endtask

  initial begin
    $dumpfile("Enable_tb.vcd");
    $dumpvars(0, Enable_tb);

    #2 enableWithNoSender;
    #2 enableWithSender;

    #2 $finish;
  end
endmodule