data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v
 line:444: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:390: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD/2) clk_p = 1\'b1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:391: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD/2);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:397: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD50/2) clk = 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:398: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD50/2);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:404: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD_OCLK/2) adc_oclk = 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:405: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD_OCLK/2);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:439: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD*128);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:441: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD*128);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:447: Unsupported: Ignoring delay on this delayed statement.\n  #(PERIOD/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:453: Unsupported: Ignoring delay on this delayed statement.\n  #(PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:57: Cannot find file containing module: \'sync_reset\'\n   sync_reset adc_res_sync( .glbl_reset(reset), .clk(clk), .reset(adc_reset) );\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports,data/full_repos/permissive/17242406/sync_reset\n             data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports,data/full_repos/permissive/17242406/sync_reset.v\n             data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports,data/full_repos/permissive/17242406/sync_reset.sv\n             sync_reset\n             sync_reset.v\n             sync_reset.sv\n             obj_dir/sync_reset\n             obj_dir/sync_reset.v\n             obj_dir/sync_reset.sv\n%Error: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:81: Cannot find file containing module: \'adc_rx\'\n   adc_rx adc_rx(.data_i_p(data_i_p[7:0]),\n   ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:421: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                                                                  : ... In instance adc_ddr3_tb\n      adc_ddr3_wr_count = 6\'b0;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:445: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                                                  : ... In instance adc_ddr3_tb\n  data_i_p[7:0] = ({$random} % 256);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:446: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                                                  : ... In instance adc_ddr3_tb\n  data_q_p[7:0] = ({$random} % 256);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:451: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                                                  : ... In instance adc_ddr3_tb\n  data_i_p[7:0] = ({$random} % 256);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_ddr3_tb.v:452: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                                                  : ... In instance adc_ddr3_tb\n  data_q_p[7:0] = ({$random} % 256);\n                ^\n%Error: Exiting due to 2 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adc_ddr3_tb;

   reg clk_p;
   wire clk_n;
   
   reg [7:0] data_i_p;
   wire [7:0] data_i_n;

   reg [7:0]  data_q_p;
   wire [7:0] data_q_n;

   wire [63:0] adc_i;
   wire [63:0] adc_q;
   reg 	       clk;

   reg [29:0] 	      sample_length;
   reg [17:0] 	      rbk_startpage;
   
   reg 	       reset;

   reg [2:0]   EIM_A;
   reg 	       EIM_LBA;
   reg 	       EIM_RW;
   reg [1:0]   EIM_CS;
   reg [15:0]  eim_din;
   wire [15:0] ro_d_b;

   reg 	       rbk_clear_error;
   wire        rbk_full_error;
   wire        rbk_empty_error;

   reg 	       rbk_enable;
   reg 	       rbk_init;
   
   wire 	      adc_reset;
   sync_reset adc_res_sync( .glbl_reset(reset), .clk(clk), .reset(adc_reset) );
   reg 		      adc_oclk;

   reg 		      adc_sample;
   reg [2:0] 	      adc_sample_s;
   wire 	      adc_sample_oclk;

   reg [29:0] 	      sample_count;
   
   always @(posedge adc_oclk) begin
      adc_sample_s[2:0] <= {adc_sample_s[1:0], adc_sample};
   end

   always @(posedge adc_oclk) begin
      if( !adc_sample_s[2] & adc_sample_s[1] ) begin
	 sample_count <= 30'b0;
      end else if( adc_sample_s[2] && (sample_count < sample_length) ) begin
	 sample_count <= sample_count + 30'b1;
      end else begin
	 sample_count <= sample_count;
      end
   end
   assign adc_sample_oclk = (sample_count < sample_length) && adc_sample_s[2];
   
   adc_rx adc_rx(.data_i_p(data_i_p[7:0]),
		 .data_i_n(data_i_n[7:0]),
		 .data_q_p(data_q_p[7:0]),
		 .data_q_n(data_q_n[7:0]),

		 .clk_p(clk_p),
		 .clk_n(clk_n),

		 .adc_i(adc_i),
		 .adc_q(adc_q),
		 .oclk(adc_oclk),

		 .reset(adc_reset)
		 );



   wire        adc_ddr3_cmd_en;
   wire [3:0]  adc_ddr3_cmd_instr;
   wire [5:0]  adc_ddr3_cmd_bl;
   wire [29:0] adc_ddr3_cmd_byte_addr;
   reg         adc_ddr3_cmd_empty; 
   reg 	       adc_ddr3_cmd_full;
   wire        adc_ddr3_wr_en;
   wire [7:0]  adc_ddr3_wr_mask;
   wire [63:0] adc_ddr3_wr_data;
   reg         adc_ddr3_wr_full;
   reg         adc_ddr3_wr_empty;
   reg [6:0]   adc_ddr3_wr_count;
   reg         adc_ddr3_wr_underrun;
   reg         adc_ddr3_wr_error;


   reg [5:0] 	      ddr3_burstcnt;
   reg [29:0] 	      ddr3_adc_adr;
   
   assign adc_ddr3_cmd_instr = 4'b0000;
   assign adc_ddr3_cmd_byte_addr = ddr3_adc_adr[29:0];
   assign adc_ddr3_cmd_bl = 6'b01_1111;
   assign adc_ddr3_cmd_en = (ddr3_burstcnt == 6'b11_1111);


   assign adc_ddr3_wr_data[63:0] = ddr3_burstcnt[0] ? adc_q[63:0] : adc_i[63:0];

   assign adc_ddr3_wr_en = (adc_sample_oclk || (ddr3_burstcnt != 6'b0));
   assign adc_ddr3_wr_mask = 8'b0;
   
   always @(posedge adc_oclk) begin
      if( adc_sample_oclk || (ddr3_burstcnt != 6'b0) ) begin
	 ddr3_burstcnt <= ddr3_burstcnt + 6'b1;
      end else begin
	 ddr3_burstcnt <= 6'b0;
      end


      if(!adc_ddr3_wr_en) begin
	 ddr3_adc_adr <= 30'b0;

      end else begin
	 if(adc_ddr3_cmd_en) begin
	    ddr3_adc_adr <= ddr3_adc_adr + 30'b1000;
	 end else begin
	    ddr3_adc_adr <= ddr3_adc_adr;
	 end
      end
   end



   
   parameter PERIOD = 16'd4;
   always begin
      clk_p = 1'b0;
      #(PERIOD/2) clk_p = 1'b1;
      #(PERIOD/2);
   end

   parameter PERIOD50 = 16'd20;
   always begin
      clk = 1'b0;
      #(PERIOD50/2) clk = 1'b1;
      #(PERIOD50/2);
   end

   parameter PERIOD_OCLK = 16'd8;
   always begin
      adc_oclk = 1'b0;
      #(PERIOD_OCLK/2) adc_oclk = 1'b1;
      #(PERIOD_OCLK/2);
   end
   
   assign clk_n = !clk_p;
   assign data_i_n = ~data_i_p;
   assign data_q_n = ~data_q_p;

   initial begin
      reset = 1'b1;
      data_i_p[7:0] = 8'b0;
      data_q_p[7:0] = 8'b0;

      adc_ddr3_cmd_empty = 1'b0;
      adc_ddr3_cmd_full = 1'b0;
      adc_ddr3_wr_full = 1'b0;
      adc_ddr3_wr_empty = 1'b0;
      adc_ddr3_wr_count = 6'b0;
      adc_ddr3_wr_error = 1'b0;
      adc_ddr3_wr_underrun = 1'b0;
      
      sample_length = 30'h1000;
      adc_sample = 1'b0;
      rbk_startpage = 18'h0;
      rbk_clear_error = 1'b0;
      rbk_enable = 1'b0;
      rbk_init = 1'b0;
      
      EIM_A = 3'b0;
      EIM_LBA = 0;
      EIM_RW = 0;
      EIM_CS = 2'b11;
      eim_din = 16'h0;
      
      $stop;
      #(PERIOD*128);
      reset = 1'b0;
      #(PERIOD*128);


      repeat(100) begin
	 data_i_p[7:0] = ({$random} % 256);
	 data_q_p[7:0] = ({$random} % 256);
	 #(PERIOD/2);
      end
      adc_sample = 1'b1;
      repeat(1000) begin
	 data_i_p[7:0] = ({$random} % 256);
	 data_q_p[7:0] = ({$random} % 256);
	 #(PERIOD/2);
      end

      $stop;
   end
   
endmodule
module adc_ddr3_tb;


   reg clk_p;
   wire clk_n;
   
   reg [7:0] data_i_p;
   wire [7:0] data_i_n;

   reg [7:0]  data_q_p;
   wire [7:0] data_q_n;

   wire [63:0] adc_i;
   wire [63:0] adc_q;
   reg 	       clk;

   reg [29:0] 	      sample_length;
   reg [17:0] 	      rbk_startpage;
   
   reg 	       reset;

   reg [2:0]   EIM_A;
   reg 	       EIM_LBA;
   reg 	       EIM_RW;
   reg [1:0]   EIM_CS;
   reg [15:0]  eim_din;
   wire [15:0] ro_d_b;

   reg 	       rbk_clear_error;
   wire        rbk_full_error;
   wire        rbk_empty_error;

   reg 	       rbk_enable;
   reg 	       rbk_init;
   
   wire 	      adc_reset;
   sync_reset adc_res_sync( .glbl_reset(reset), .clk(clk), .reset(adc_reset) );
   reg 		      adc_oclk;

   reg 		      adc_sample;
   reg [2:0] 	      adc_sample_s;
   wire 	      adc_sample_oclk;

   reg [29:0] 	      sample_count;
   
   always @(posedge adc_oclk) begin
      adc_sample_s[2:0] <= {adc_sample_s[1:0], adc_sample};
   end

   always @(posedge adc_oclk) begin
      if( !adc_sample_s[2] & adc_sample_s[1] ) begin
	 sample_count <= 30'b0;
      end else if( adc_sample_s[2] && (sample_count < sample_length) ) begin
	 sample_count <= sample_count + 30'b1;
      end else begin
	 sample_count <= sample_count;
      end
   end
   assign adc_sample_oclk = (sample_count < sample_length) && adc_sample_s[2];
   
   adc_rx adc_rx(.data_i_p(data_i_p[7:0]),
		 .data_i_n(data_i_n[7:0]),
		 .data_q_p(data_q_p[7:0]),
		 .data_q_n(data_q_n[7:0]),

		 .clk_p(clk_p),
		 .clk_n(clk_n),

		 .adc_i(adc_i),
		 .adc_q(adc_q),
		 .oclk(adc_oclk),

		 .reset(adc_reset)
		 );



   wire        adc_ddr3_cmd_en;
   wire [3:0]  adc_ddr3_cmd_instr;
   wire [5:0]  adc_ddr3_cmd_bl;
   wire [29:0] adc_ddr3_cmd_byte_addr;
   reg         adc_ddr3_cmd_empty; 
   reg 	       adc_ddr3_cmd_full;
   wire        adc_ddr3_wr_en;
   wire [7:0]  adc_ddr3_wr_mask;
   wire [63:0] adc_ddr3_wr_data;
   reg         adc_ddr3_wr_full;
   reg         adc_ddr3_wr_empty;
   reg [6:0]   adc_ddr3_wr_count;
   reg         adc_ddr3_wr_underrun;
   reg         adc_ddr3_wr_error;


   reg [5:0] 	      ddr3_burstcnt;
   reg [29:0] 	      ddr3_adc_adr;
   
   assign adc_ddr3_cmd_instr = 4'b0000;
   assign adc_ddr3_cmd_byte_addr = ddr3_adc_adr[29:0];
   assign adc_ddr3_cmd_bl = 6'b01_1111;
   assign adc_ddr3_cmd_en = (ddr3_burstcnt == 6'b11_1111);


   assign adc_ddr3_wr_data[63:0] = ddr3_burstcnt[0] ? adc_q[63:0] : adc_i[63:0];

   assign adc_ddr3_wr_en = (adc_sample_oclk || (ddr3_burstcnt != 6'b0));
   assign adc_ddr3_wr_mask = 8'b0;
   
   always @(posedge adc_oclk) begin
      if( adc_sample_oclk || (ddr3_burstcnt != 6'b0) ) begin
	 ddr3_burstcnt <= ddr3_burstcnt + 6'b1;
      end else begin
	 ddr3_burstcnt <= 6'b0;
      end


      if(!adc_ddr3_wr_en) begin
	 ddr3_adc_adr <= 30'b0;

      end else begin
	 if(adc_ddr3_cmd_en) begin
	    ddr3_adc_adr <= ddr3_adc_adr + 30'b1000;
	 end else begin
	    ddr3_adc_adr <= ddr3_adc_adr;
	 end
      end
   end



   
   parameter PERIOD = 16'd4;
   always begin
      clk_p = 1'b0;
      #(PERIOD/2) clk_p = 1'b1;
      #(PERIOD/2);
   end

   parameter PERIOD50 = 16'd20;
   always begin
      clk = 1'b0;
      #(PERIOD50/2) clk = 1'b1;
      #(PERIOD50/2);
   end

   parameter PERIOD_OCLK = 16'd8;
   always begin
      adc_oclk = 1'b0;
      #(PERIOD_OCLK/2) adc_oclk = 1'b1;
      #(PERIOD_OCLK/2);
   end
   
   assign clk_n = !clk_p;
   assign data_i_n = ~data_i_p;
   assign data_q_n = ~data_q_p;

   initial begin
      reset = 1'b1;
      data_i_p[7:0] = 8'b0;
      data_q_p[7:0] = 8'b0;

      adc_ddr3_cmd_empty = 1'b0;
      adc_ddr3_cmd_full = 1'b0;
      adc_ddr3_wr_full = 1'b0;
      adc_ddr3_wr_empty = 1'b0;
      adc_ddr3_wr_count = 6'b0;
      adc_ddr3_wr_error = 1'b0;
      adc_ddr3_wr_underrun = 1'b0;
      
      sample_length = 30'h1000;
      adc_sample = 1'b0;
      rbk_startpage = 18'h0;
      rbk_clear_error = 1'b0;
      rbk_enable = 1'b0;
      rbk_init = 1'b0;
      
      EIM_A = 3'b0;
      EIM_LBA = 0;
      EIM_RW = 0;
      EIM_CS = 2'b11;
      eim_din = 16'h0;
      
      $stop;
      #(PERIOD*128);
      reset = 1'b0;
      #(PERIOD*128);


      repeat(100) begin
	 data_i_p[7:0] = ({$random} % 256);
	 data_q_p[7:0] = ({$random} % 256);
	 #(PERIOD/2);
      end
      adc_sample = 1'b1;
      repeat(1000) begin
	 data_i_p[7:0] = ({$random} % 256);
	 data_q_p[7:0] = ({$random} % 256);
	 #(PERIOD/2);
      end

      $stop;
   end
   
endmodule