data/full_repos/permissive/212008255/codes/wallace_multiplier/wallace_tree.v
data/verilator_xmls/520348bf-faf7-49d4-bf1a-7e9f0caa89ef.xml
module wallace_tree(
	input [3:0] x,
	input [3:0] y,
	output [7:0] s,
	output c_8
	);
wire [7:0] a;
wire [7:0] b;
wire c_0;
wire c_4;

assign c_0=0;
assign a[0] = x[0] & y[0];
assign b[0] = 0;

assign a[1] = x[1] & y[0];
assign b[1] = x[0] & y[1];

half_adder qx8(x[2]& y[0], x[1] & y[1],a[2],b[3]);
assign b[2] = x[0] & y[2];

wire temp1,temp2;
full_adder qx1(x[3]&y[0],x[2]&y[1],x[1] &y[2],temp1,temp2);
half_adder qx2(temp1,x[0]&y[3],a[3],b[4]);


wire temp3,temp4;
full_adder qx3(x[3]&y[1],x[2]&y[2],x[1]&y[3],temp3,temp4);
half_adder qx4(temp3,temp2,a[4],b[5]);


wire temp5,temp6;
half_adder qx5(x[3]&y[2],x[2]&y[3],temp5,temp6);
half_adder qx6(temp5,temp4,a[5],b[6]);


half_adder qx7(x[3]&y[3],temp6,a[6],b[7]);


assign a[7]=0;

bit_4_carry_lookahead ux1(a[3:0],b[3:0],c_0,s[3:0],c_4);
bit_4_carry_lookahead ux2(a[7:4],b[7:4],c_4,s[7:4],c_8);

endmodule
module wallace_tree(
	input [3:0] x,
	input [3:0] y,
	output [7:0] s,
	output c_8
	);

wire [7:0] a;
wire [7:0] b;
wire c_0;
wire c_4;

assign c_0=0;
assign a[0] = x[0] & y[0];
assign b[0] = 0;

assign a[1] = x[1] & y[0];
assign b[1] = x[0] & y[1];

half_adder qx8(x[2]& y[0], x[1] & y[1],a[2],b[3]);
assign b[2] = x[0] & y[2];

wire temp1,temp2;
full_adder qx1(x[3]&y[0],x[2]&y[1],x[1] &y[2],temp1,temp2);
half_adder qx2(temp1,x[0]&y[3],a[3],b[4]);


wire temp3,temp4;
full_adder qx3(x[3]&y[1],x[2]&y[2],x[1]&y[3],temp3,temp4);
half_adder qx4(temp3,temp2,a[4],b[5]);


wire temp5,temp6;
half_adder qx5(x[3]&y[2],x[2]&y[3],temp5,temp6);
half_adder qx6(temp5,temp4,a[5],b[6]);


half_adder qx7(x[3]&y[3],temp6,a[6],b[7]);


assign a[7]=0;

bit_4_carry_lookahead ux1(a[3:0],b[3:0],c_0,s[3:0],c_4);
bit_4_carry_lookahead ux2(a[7:4],b[7:4],c_4,s[7:4],c_8);

endmodule