data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v
 line:30: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:56: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:70: Unsupported: Ignoring delay on this delayed statement.\n        entryhi = 32\'h00; #20;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:93: Unsupported: Ignoring delay on this delayed statement.\n        entryhi = 32\'h01; #20;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:96: Unsupported: Ignoring delay on this delayed statement.\n        entryhi = 32\'h00; #20;\n                          ^\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:34: Can\'t find definition of variable: \'w_idx\'\n        idx = w_idx;\n              ^~~~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:34: Can\'t find definition of variable: \'idx\'\n                                                                                  : ... Suggested alternative: \'w_idx\'\n        idx = w_idx;\n        ^~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:35: Can\'t find definition of variable: \'w_mask\'\n        mask = w_mask;\n               ^~~~~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:35: Can\'t find definition of variable: \'mask\'\n                                                                                  : ... Suggested alternative: \'w_mask\'\n        mask = w_mask;\n        ^~~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:36: Can\'t find definition of variable: \'w_entryhi\'\n                                                                                  : ... Suggested alternative: \'w_entrylo1\'\n        entryhi = w_entryhi;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:36: Can\'t find definition of variable: \'entryhi\'\n                                                                                  : ... Suggested alternative: \'w_entryhi\'\n        entryhi = w_entryhi;\n        ^~~~~~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:37: Can\'t find definition of variable: \'w_entrylo0\'\n                                                                                  : ... Suggested alternative: \'w_entrylo1\'\n        entrylo0 = w_entrylo0;\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:37: Can\'t find definition of variable: \'entrylo0\'\n                                                                                  : ... Suggested alternative: \'w_entrylo0\'\n        entrylo0 = w_entrylo0;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:38: Can\'t find definition of variable: \'entrylo1\'\n                                                                                  : ... Suggested alternative: \'entrylo0\'\n        entrylo1 = w_entrylo1;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:39: Can\'t find definition of variable: \'wen\'\n        wen = 1;\n        ^~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:50: Can\'t find definition of variable: \'vaddr\'\n                                                                                  : ... Suggested alternative: \'addr\'\n        vaddr = w_vaddr;\n        ^~~~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:51: Can\'t find definition of variable: \'store\'\n                                                                                  : ... Suggested alternative: \'w_store\'\n        store = w_store;\n        ^~~~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:56: Can\'t find definition of variable: \'clk\'\n    always #5 clk = ~clk;\n                     ^~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:63: Can\'t find definition of task/function: \'write_tlb\'\n        for (i=0; i<32; i=i+1) write_tlb(i, 12\'d0, 32\'d0, 32\'d0, 32\'d0);\n                               ^~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:65: Can\'t find definition of task/function: \'write_tlb\'\n        write_tlb(0, 12\'h0, 32\'h00002000, (32\'h1111 << 6) | 6\'b011010, (32\'h2222 << 6) | 6\'b011010);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/c/cache-testbench/icache_sim.v:66: Can\'t find definition of task/function: \'write_tlb\'\n        write_tlb(1, 12\'h0, 32\'h00004000, (32\'h3333 << 6) | 6\'b011110, (32\'h4444 << 6) | 6\'b011110);\n        ^~~~~~~~~\n%Error: Exiting due to 16 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module icache_fetch_sim();

    wire [31:0]addr;
    wire [31:0]addr_ok;
    wire [31:0]inst;
    wire [31:0]inst_ok;

    task fetch_inst(
        input [31:0]    w_entrylo1
    );
    begin
        idx = w_idx;
        mask = w_mask;
        entryhi = w_entryhi;
        entrylo0 = w_entrylo0;
        entrylo1 = w_entrylo1;
        wen = 1;
        #10;
        wen = 0;
    end
    endtask

    task lookup_tlb(
        input [31:0]    w_vaddr,
        input           w_store
    );
    begin
        vaddr = w_vaddr;
        store = w_store;
        #10;
    end
    endtask

    always #5 clk = ~clk;

    integer i;
    initial begin
        clk = 0;
        #10;

        for (i=0; i<32; i=i+1) write_tlb(i, 12'd0, 32'd0, 32'd0, 32'd0);
        #20;
        write_tlb(0, 12'h0, 32'h00002000, (32'h1111 << 6) | 6'b011010, (32'h2222 << 6) | 6'b011010);
        write_tlb(1, 12'h0, 32'h00004000, (32'h3333 << 6) | 6'b011110, (32'h4444 << 6) | 6'b011110);



        entryhi = 32'h00; #20;
        lookup_tlb(32'hf0000000, 1'b0);
        lookup_tlb(32'hf0000000, 1'b1);
        lookup_tlb(32'h00002000, 1'b0);
        lookup_tlb(32'h00002000, 1'b1);
        lookup_tlb(32'h00003000, 1'b0);
        lookup_tlb(32'h00003000, 1'b1);
        lookup_tlb(32'h00004000, 1'b0);
        lookup_tlb(32'h00004000, 1'b1);
        lookup_tlb(32'h00005000, 1'b0);
        lookup_tlb(32'h00005000, 1'b1);












        entryhi = 32'h01; #20;
        lookup_tlb(32'h00002000, 1'b0);
        lookup_tlb(32'h00002000, 1'b1);
        entryhi = 32'h00; #20;
        $finish;
    end

endmodule
module icache_fetch_sim();


    wire [31:0]addr;
    wire [31:0]addr_ok;
    wire [31:0]inst;
    wire [31:0]inst_ok;

    task fetch_inst(
        input [31:0]    w_entrylo1
    );
    begin
        idx = w_idx;
        mask = w_mask;
        entryhi = w_entryhi;
        entrylo0 = w_entrylo0;
        entrylo1 = w_entrylo1;
        wen = 1;
        #10;
        wen = 0;
    end
    endtask

    task lookup_tlb(
        input [31:0]    w_vaddr,
        input           w_store
    );
    begin
        vaddr = w_vaddr;
        store = w_store;
        #10;
    end
    endtask

    always #5 clk = ~clk;

    integer i;
    initial begin
        clk = 0;
        #10;

        for (i=0; i<32; i=i+1) write_tlb(i, 12'd0, 32'd0, 32'd0, 32'd0);
        #20;
        write_tlb(0, 12'h0, 32'h00002000, (32'h1111 << 6) | 6'b011010, (32'h2222 << 6) | 6'b011010);
        write_tlb(1, 12'h0, 32'h00004000, (32'h3333 << 6) | 6'b011110, (32'h4444 << 6) | 6'b011110);



        entryhi = 32'h00; #20;
        lookup_tlb(32'hf0000000, 1'b0);
        lookup_tlb(32'hf0000000, 1'b1);
        lookup_tlb(32'h00002000, 1'b0);
        lookup_tlb(32'h00002000, 1'b1);
        lookup_tlb(32'h00003000, 1'b0);
        lookup_tlb(32'h00003000, 1'b1);
        lookup_tlb(32'h00004000, 1'b0);
        lookup_tlb(32'h00004000, 1'b1);
        lookup_tlb(32'h00005000, 1'b0);
        lookup_tlb(32'h00005000, 1'b1);












        entryhi = 32'h01; #20;
        lookup_tlb(32'h00002000, 1'b0);
        lookup_tlb(32'h00002000, 1'b1);
        entryhi = 32'h00; #20;
        $finish;
    end

endmodule