data/full_repos/permissive/147690299/lab/25_seq_dff_param/rtl/board_top.v
1: b"%Error: data/full_repos/permissive/147690299/lab/25_seq_dff_param/rtl/board_top.v:16: Cannot find file containing module: 'dff_async_rst_n_param'\n    dff_async_rst_n_param \n    ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147690299/lab/25_seq_dff_param/rtl,data/full_repos/permissive/147690299/dff_async_rst_n_param\n             data/full_repos/permissive/147690299/lab/25_seq_dff_param/rtl,data/full_repos/permissive/147690299/dff_async_rst_n_param.v\n             data/full_repos/permissive/147690299/lab/25_seq_dff_param/rtl,data/full_repos/permissive/147690299/dff_async_rst_n_param.sv\n             dff_async_rst_n_param\n             dff_async_rst_n_param.v\n             dff_async_rst_n_param.sv\n             obj_dir/dff_async_rst_n_param\n             obj_dir/dff_async_rst_n_param.v\n             obj_dir/dff_async_rst_n_param.sv\n%Error: Exiting due to 1 error(s)\n"
module board_top
(
    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LED
);
    wire clk   = KEY[1];
    wire rst_n = SW [0];

    localparam WIDTH = 6;
    localparam ZEROD = { WIDTH {1'b0} };

    wire [WIDTH-1:0] d = SW [1 +: WIDTH];
    wire [WIDTH-1:0] q;

    dff_async_rst_n_param 
    #(
        .WIDTH ( WIDTH ), 
        .RESET ( ZEROD )
    ) 
    dff_async_rst_n_param
    (
        .clk   ( clk   ),
        .rst_n ( rst_n ),
        .d     ( d     ),
        .q     ( q     )
    );

    assign LED[      0] = rst_n;
    assign LED[WIDTH:1] = q;

endmodule
module board_top
(
    input  [ 1:0] KEY,
    input  [ 9:0] SW,
    output [ 9:0] LED
);

    wire clk   = KEY[1];
    wire rst_n = SW [0];

    localparam WIDTH = 6;
    localparam ZEROD = { WIDTH {1'b0} };

    wire [WIDTH-1:0] d = SW [1 +: WIDTH];
    wire [WIDTH-1:0] q;

    dff_async_rst_n_param 
    #(
        .WIDTH ( WIDTH ), 
        .RESET ( ZEROD )
    ) 
    dff_async_rst_n_param
    (
        .clk   ( clk   ),
        .rst_n ( rst_n ),
        .d     ( d     ),
        .q     ( q     )
    );

    assign LED[      0] = rst_n;
    assign LED[WIDTH:1] = q;

endmodule