data/full_repos/permissive/135820056/sys/spdif.v
data/verilator_xmls/5499ef42-a53e-4651-8820-e4def08e4a6e.xml
module spdif
(
    input           clk_i,
    input           rst_i,






    input           bit_out_en_i,


    output          spdif_o,


    input [31:0]    sample_i,
    output reg      sample_req_o
);




reg [15:0]  audio_sample_q;
reg [8:0]   subframe_count_q;

reg         load_subframe_q;
reg [7:0]   preamble_q;
wire [31:0] subframe_w;

reg [5:0]   bit_count_q;
reg         bit_toggle_q;

reg         spdif_out_q;

reg [5:0]   parity_count_q;

reg         channel_status_bit_q;




always @ (posedge rst_i or posedge clk_i )
begin
    if (rst_i == 1'b1)
        subframe_count_q    <= 9'd0;
    else if (load_subframe_q)
    begin

        if (subframe_count_q == 9'd383)
            subframe_count_q <= 9'd0;
        else
            subframe_count_q <= subframe_count_q + 9'd1;
    end
end




reg [15:0] sample_buf_q;

always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
   begin
        audio_sample_q      <= 16'h0000;
        sample_buf_q        <= 16'h0000;
        sample_req_o        <= 1'b0;
   end
   else if (load_subframe_q)
   begin

        if (subframe_count_q[0] == 1'b0)
        begin

            audio_sample_q <= sample_i[15:0];


            sample_buf_q <= sample_i[31:16];


            sample_req_o <= 1'b1;
        end
        else
        begin

            audio_sample_q <= sample_buf_q;

            sample_req_o <= 1'b0;
        end
   end
   else
        sample_req_o <= 1'b0;
end


assign subframe_w[3:0] = 4'b0000;


assign subframe_w[7:4] = 4'b0000;


assign subframe_w[11:8] = 4'b0000;


assign subframe_w[27:12] = audio_sample_q;


assign subframe_w[28] = 1'b0;


assign subframe_w[29] = 1'b0;


assign subframe_w[30] = channel_status_bit_q ;


assign subframe_w[31] = 1'b0;




localparam PREAMBLE_Z = 8'b00010111;
localparam PREAMBLE_Y = 8'b00100111;
localparam PREAMBLE_X = 8'b01000111;

reg [7:0] preamble_r;
reg       channel_status_bit_r;

always @ *
begin


    if (subframe_count_q == 9'd0)
        preamble_r = PREAMBLE_Z;

    else if (subframe_count_q[0] == 1'b1)
        preamble_r = PREAMBLE_Y;

    else
        preamble_r = PREAMBLE_X;

    if (subframe_count_q[8:1] == 8'd2)
        channel_status_bit_r = 1'b1;
    else if (subframe_count_q[8:1] == 8'd15)
        channel_status_bit_r = 1'b1;
    else if (subframe_count_q[8:1] == 8'd25)
        channel_status_bit_r = 1'b1;
    else
        channel_status_bit_r = 1'b0;
end

always @ (posedge rst_i or posedge clk_i )
begin
    if (rst_i == 1'b1)
    begin
        preamble_q  <= 8'h00;
        channel_status_bit_q <= 1'b0;
    end
    else if (load_subframe_q)
    begin
        preamble_q  <= preamble_r;
        channel_status_bit_q <= channel_status_bit_r;
    end
end




always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
   begin
        parity_count_q  <= 6'd0;
   end

   else if (bit_out_en_i)
   begin

        if (bit_count_q < 6'd8)
        begin
            parity_count_q  <= 6'd0;
        end

        else if (bit_count_q < 6'd62)
        begin

            if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1)
                parity_count_q <= parity_count_q + 6'd1;
        end
   end
end




always @ (posedge rst_i or posedge clk_i)
begin
    if (rst_i == 1'b1)
    begin
        bit_count_q     <= 6'b0;
        load_subframe_q <= 1'b1;
    end

    else if (bit_out_en_i)
    begin

        if (bit_count_q == 6'd63)
        begin
            bit_count_q     <= 6'd0;
            load_subframe_q <= 1'b1;
        end
        else
        begin
            bit_count_q     <= bit_count_q + 6'd1;
            load_subframe_q <= 1'b0;
        end
    end
    else
        load_subframe_q <= 1'b0;
end




always @ (posedge rst_i or posedge clk_i)
if (rst_i == 1'b1)
    bit_toggle_q    <= 1'b0;

else if (bit_out_en_i)
    bit_toggle_q <= ~bit_toggle_q;




reg bit_r;

always @ *
begin
    bit_r = spdif_out_q;


    if (bit_out_en_i)
    begin

        if (bit_count_q < 6'd8)
        begin
            bit_r = preamble_q[bit_count_q[2:0]];
        end

        else if (bit_count_q < 6'd62)
        begin
            if (subframe_w[bit_count_q / 2] == 1'b0)
            begin
                if (bit_toggle_q == 1'b0)
                    bit_r = ~spdif_out_q;
                else
                    bit_r = spdif_out_q;
            end
            else
                bit_r = ~spdif_out_q;
        end

        else
        begin

            if (parity_count_q[0] == 1'b0)
            begin
                if (bit_toggle_q == 1'b0)
                    bit_r = ~spdif_out_q;
                else
                    bit_r = spdif_out_q;
            end
            else
                bit_r = ~spdif_out_q;
        end
    end
end

always @ (posedge rst_i or posedge clk_i )
if (rst_i == 1'b1)
    spdif_out_q <= 1'b0;
else
    spdif_out_q <= bit_r;

assign spdif_o  = spdif_out_q;

endmodule
module spdif
(
    input           clk_i,
    input           rst_i,






    input           bit_out_en_i,


    output          spdif_o,


    input [31:0]    sample_i,
    output reg      sample_req_o
);





reg [15:0]  audio_sample_q;
reg [8:0]   subframe_count_q;

reg         load_subframe_q;
reg [7:0]   preamble_q;
wire [31:0] subframe_w;

reg [5:0]   bit_count_q;
reg         bit_toggle_q;

reg         spdif_out_q;

reg [5:0]   parity_count_q;

reg         channel_status_bit_q;




always @ (posedge rst_i or posedge clk_i )
begin
    if (rst_i == 1'b1)
        subframe_count_q    <= 9'd0;
    else if (load_subframe_q)
    begin

        if (subframe_count_q == 9'd383)
            subframe_count_q <= 9'd0;
        else
            subframe_count_q <= subframe_count_q + 9'd1;
    end
end




reg [15:0] sample_buf_q;

always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
   begin
        audio_sample_q      <= 16'h0000;
        sample_buf_q        <= 16'h0000;
        sample_req_o        <= 1'b0;
   end
   else if (load_subframe_q)
   begin

        if (subframe_count_q[0] == 1'b0)
        begin

            audio_sample_q <= sample_i[15:0];


            sample_buf_q <= sample_i[31:16];


            sample_req_o <= 1'b1;
        end
        else
        begin

            audio_sample_q <= sample_buf_q;

            sample_req_o <= 1'b0;
        end
   end
   else
        sample_req_o <= 1'b0;
end


assign subframe_w[3:0] = 4'b0000;


assign subframe_w[7:4] = 4'b0000;


assign subframe_w[11:8] = 4'b0000;


assign subframe_w[27:12] = audio_sample_q;


assign subframe_w[28] = 1'b0;


assign subframe_w[29] = 1'b0;


assign subframe_w[30] = channel_status_bit_q ;


assign subframe_w[31] = 1'b0;




localparam PREAMBLE_Z = 8'b00010111;
localparam PREAMBLE_Y = 8'b00100111;
localparam PREAMBLE_X = 8'b01000111;

reg [7:0] preamble_r;
reg       channel_status_bit_r;

always @ *
begin


    if (subframe_count_q == 9'd0)
        preamble_r = PREAMBLE_Z;

    else if (subframe_count_q[0] == 1'b1)
        preamble_r = PREAMBLE_Y;

    else
        preamble_r = PREAMBLE_X;

    if (subframe_count_q[8:1] == 8'd2)
        channel_status_bit_r = 1'b1;
    else if (subframe_count_q[8:1] == 8'd15)
        channel_status_bit_r = 1'b1;
    else if (subframe_count_q[8:1] == 8'd25)
        channel_status_bit_r = 1'b1;
    else
        channel_status_bit_r = 1'b0;
end

always @ (posedge rst_i or posedge clk_i )
begin
    if (rst_i == 1'b1)
    begin
        preamble_q  <= 8'h00;
        channel_status_bit_q <= 1'b0;
    end
    else if (load_subframe_q)
    begin
        preamble_q  <= preamble_r;
        channel_status_bit_q <= channel_status_bit_r;
    end
end




always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
   begin
        parity_count_q  <= 6'd0;
   end

   else if (bit_out_en_i)
   begin

        if (bit_count_q < 6'd8)
        begin
            parity_count_q  <= 6'd0;
        end

        else if (bit_count_q < 6'd62)
        begin

            if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1)
                parity_count_q <= parity_count_q + 6'd1;
        end
   end
end




always @ (posedge rst_i or posedge clk_i)
begin
    if (rst_i == 1'b1)
    begin
        bit_count_q     <= 6'b0;
        load_subframe_q <= 1'b1;
    end

    else if (bit_out_en_i)
    begin

        if (bit_count_q == 6'd63)
        begin
            bit_count_q     <= 6'd0;
            load_subframe_q <= 1'b1;
        end
        else
        begin
            bit_count_q     <= bit_count_q + 6'd1;
            load_subframe_q <= 1'b0;
        end
    end
    else
        load_subframe_q <= 1'b0;
end




always @ (posedge rst_i or posedge clk_i)
if (rst_i == 1'b1)
    bit_toggle_q    <= 1'b0;

else if (bit_out_en_i)
    bit_toggle_q <= ~bit_toggle_q;




reg bit_r;

always @ *
begin
    bit_r = spdif_out_q;


    if (bit_out_en_i)
    begin

        if (bit_count_q < 6'd8)
        begin
            bit_r = preamble_q[bit_count_q[2:0]];
        end

        else if (bit_count_q < 6'd62)
        begin
            if (subframe_w[bit_count_q / 2] == 1'b0)
            begin
                if (bit_toggle_q == 1'b0)
                    bit_r = ~spdif_out_q;
                else
                    bit_r = spdif_out_q;
            end
            else
                bit_r = ~spdif_out_q;
        end

        else
        begin

            if (parity_count_q[0] == 1'b0)
            begin
                if (bit_toggle_q == 1'b0)
                    bit_r = ~spdif_out_q;
                else
                    bit_r = spdif_out_q;
            end
            else
                bit_r = ~spdif_out_q;
        end
    end
end

always @ (posedge rst_i or posedge clk_i )
if (rst_i == 1'b1)
    spdif_out_q <= 1'b0;
else
    spdif_out_q <= bit_r;

assign spdif_o  = spdif_out_q;

endmodule