data/full_repos/permissive/128204663/build-data/share/SB_DFFESS.v
1: b"%Error: data/full_repos/permissive/128204663/build-data/share/SB_DFFESS.v:2: Duplicate declaration of signal: 'Q'\n                                                                           : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg Q = 0;\n     ^\n        data/full_repos/permissive/128204663/build-data/share/SB_DFFESS.v:1: ... Location of original declaration\nmodule SB_DFFESS (output Q, input C, E, S, D);\n                         ^\n%Error: Exiting due to 1 error(s)\n"
module SB_DFFESS (output Q, input C, E, S, D);
	reg Q = 0;
	always @(posedge C)
		if (E) begin
			if (S)
				Q <= 1;
			else
				Q <= D;
		end
endmodule
module SB_DFFESS (output Q, input C, E, S, D);

	reg Q = 0;
	always @(posedge C)
		if (E) begin
			if (S)
				Q <= 1;
			else
				Q <= D;
		end
endmodule