data/full_repos/permissive/167489907/Control Unit/program_counter.v
1: b'%Error: Cannot find file containing module: Unit,data/full_repos/permissive/167489907\n        ... Looked in:\n             data/full_repos/permissive/167489907/Control/Unit,data/full_repos/permissive/167489907\n             data/full_repos/permissive/167489907/Control/Unit,data/full_repos/permissive/167489907.v\n             data/full_repos/permissive/167489907/Control/Unit,data/full_repos/permissive/167489907.sv\n             Unit,data/full_repos/permissive/167489907\n             Unit,data/full_repos/permissive/167489907.v\n             Unit,data/full_repos/permissive/167489907.sv\n             obj_dir/Unit,data/full_repos/permissive/167489907\n             obj_dir/Unit,data/full_repos/permissive/167489907.v\n             obj_dir/Unit,data/full_repos/permissive/167489907.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/167489907/Control\n%Error: Cannot find file containing module: Unit/program_counter.v\n%Error: Exiting due to 3 error(s)\n'
module program_counter(
	input clk,
	input rst,
	input [31:0] in,
	input [1:0] PS,
	output reg [31:0] out);
	













wire [31:0] D;

assign D = PS == 2'b00 ? out :
			  PS == 2'b01 ? out + 32'd1 :
			  PS == 2'b10 ? in : out + in;
			  
parameter PC_RESET_VALUE = 32'h0000_0800;
always @(posedge clk or posedge rst)
	begin
		if (rst) out <= PC_RESET_VALUE;
		else out <= D;
	end
endmodule
module program_counter(
	input clk,
	input rst,
	input [31:0] in,
	input [1:0] PS,
	output reg [31:0] out);

	













wire [31:0] D;

assign D = PS == 2'b00 ? out :
			  PS == 2'b01 ? out + 32'd1 :
			  PS == 2'b10 ? in : out + in;
			  
parameter PC_RESET_VALUE = 32'h0000_0800;
always @(posedge clk or posedge rst)
	begin
		if (rst) out <= PC_RESET_VALUE;
		else out <= D;
	end
endmodule