data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v:1: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.sv\n             cmos_cells.v\n             cmos_cells.v.v\n             cmos_cells.v.sv\n             obj_dir/cmos_cells.v\n             obj_dir/cmos_cells.v.v\n             obj_dir/cmos_cells.v.sv\n%Error: Exiting due to 1 error(s)\n'
module ffd_p2s_synth(CLK, D, ENB, valid_in, Q, valid_out);
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  input CLK;
  input D;
  input ENB;
  output Q;
  reg Q;
  input valid_in;
  output valid_out;
  NOR _05_ (
    .A(valid_in),
    .B(Q),
    .Y(_01_)
  );
  NOT _06_ (
    .A(D),
    .Y(_02_)
  );
  NAND _07_ (
    .A(valid_in),
    .B(_02_),
    .Y(_03_)
  );
  NAND _08_ (
    .A(_03_),
    .B(ENB),
    .Y(_04_)
  );
  NOR _09_ (
    .A(_04_),
    .B(_01_),
    .Y(_00_)
  );
  always @(posedge CLK)
      Q <= _00_;
  assign valid_out = 1'b1;
endmodule
module ffd_p2s_synth(CLK, D, ENB, valid_in, Q, valid_out);

  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  input CLK;
  input D;
  input ENB;
  output Q;
  reg Q;
  input valid_in;
  output valid_out;
  NOR _05_ (
    .A(valid_in),
    .B(Q),
    .Y(_01_)
  );
  NOT _06_ (
    .A(D),
    .Y(_02_)
  );
  NAND _07_ (
    .A(valid_in),
    .B(_02_),
    .Y(_03_)
  );
  NAND _08_ (
    .A(_03_),
    .B(ENB),
    .Y(_04_)
  );
  NOR _09_ (
    .A(_04_),
    .B(_01_),
    .Y(_00_)
  );
  always @(posedge CLK)
      Q <= _00_;
  assign valid_out = 1'b1;
endmodule