data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/axi_arbiter.v
1: b"%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/axi_arbiter.v:112: Cannot find file containing module: 'axi_arbiter_wr'\n  axi_arbiter_wr #(\n  ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/axi_arbiter_wr\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/axi_arbiter_wr.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/axi_arbiter_wr.sv\n             axi_arbiter_wr\n             axi_arbiter_wr.v\n             axi_arbiter_wr.sv\n             obj_dir/axi_arbiter_wr\n             obj_dir/axi_arbiter_wr.v\n             obj_dir/axi_arbiter_wr.sv\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/axi_arbiter.v:164: Cannot find file containing module: 'axi_arbiter_rd'\n  axi_arbiter_rd #(\n  ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module axi_arbiter #(
  parameter Ports           = 2,
            DataBits        = 64,
            AddrBits        = 32,
            LenBits         = 4,
            NumPendingReads = 6,
            InBuffers       = 0,
            OutBuffer       = 1)
(
  input                        clk,
  input                        rst,

  input [Ports-1:0]            slv_awvalid,
  output [Ports-1:0]           slv_awready,
  input [Ports*AddrBits-1:0]   slv_awaddr,
  input [Ports*LenBits-1:0]    slv_awlen,

  input [Ports-1:0]            slv_wvalid,
  output [Ports-1:0]           slv_wready,
  input [Ports-1:0]            slv_wlast,
  input [Ports*DataBits/8-1:0] slv_wstrb,
  input [Ports*DataBits-1:0]   slv_wdata,

  output [Ports-1:0]           slv_bvalid,
  input [Ports-1:0]            slv_bready,
  output [Ports*2-1:0]         slv_bresp,
 	output [Ports*4-1:0]         slv_bid,

  input [Ports-1:0]            slv_arvalid,
  output [Ports-1:0]           slv_arready,
  input [Ports*AddrBits-1:0]   slv_araddr,
  input [Ports*LenBits-1:0]    slv_arlen,

  output [Ports-1:0]           slv_rvalid,
  input [Ports-1:0]            slv_rready,
  output [Ports*DataBits-1:0]  slv_rdata,
  output [Ports*2-1:0]         slv_rresp,
  output [Ports-1:0]           slv_rlast,
  output [Ports*4-1:0]         slv_rid,

  output                       mst_awvalid,
  input                        mst_awready,
  output [AddrBits-1:0]        mst_awaddr,
  output [LenBits-1:0]         mst_awlen,
  output [3:0]                 mst_awid,
  output [2:0]                 mst_awsize,
  output [1:0]                 mst_awburst,
  output [1:0]                 mst_awlock,

  output                       mst_wvalid,
  input                        mst_wready,
  output [3:0]                 mst_wid,
  output [DataBits/8-1:0]      mst_wstrb,
  output                       mst_wlast,
  output [DataBits-1:0]        mst_wdata,

  input                        mst_bvalid,
  output                       mst_bready,
  input [1:0]                  mst_bresp,
  input [3:0]                  mst_bid,

  output                       mst_arvalid,
  input                        mst_arready,
  output [AddrBits-1:0]        mst_araddr,
  output [LenBits-1:0]         mst_arlen,
  output [3:0]                 mst_arid,
  output [2:0]                 mst_arsize,
  output [1:0]                 mst_arburst,
  output [1:0]                 mst_arlock,

  input                        mst_rvalid,
  output                       mst_rready,
  input [3:0]                  mst_rid,
  input [DataBits-1:0]         mst_rdata,
  input [1:0]                  mst_rresp,
  input                        mst_rlast);




  axi_arbiter_wr #(
    .Ports          (Ports),
    .DataBits       (DataBits),
    .AddrBits       (AddrBits),
    .LenBits        (LenBits),
    .InBuffers      (InBuffers),
    .OutBuffer      (OutBuffer))
  arb_wr(
    .clk           (clk),
    .rst           (rst),

    .slv_awvalid   (slv_awvalid),
    .slv_awready   (slv_awready),
    .slv_awaddr    (slv_awaddr),
    .slv_awlen     (slv_awlen),

    .slv_wvalid    (slv_wvalid),
    .slv_wready    (slv_wready),
    .slv_wlast     (slv_wlast),
    .slv_wstrb     (slv_wstrb),
    .slv_wdata     (slv_wdata),

    .slv_bvalid    (slv_bvalid),
    .slv_bready    (slv_bready),
    .slv_bresp     (slv_bresp),
    .slv_bid       (slv_bid),

    .mst_awvalid   (mst_awvalid),
    .mst_awready   (mst_awready),
    .mst_awaddr    (mst_awaddr),
    .mst_awlen     (mst_awlen),
    .mst_awid      (mst_awid),
    .mst_awsize    (mst_awsize),
    .mst_awburst   (mst_awburst),
    .mst_awlock    (mst_awlock),

    .mst_wvalid    (mst_wvalid),
    .mst_wready    (mst_wready),
    .mst_wid       (mst_wid),
    .mst_wstrb     (mst_wstrb),
    .mst_wlast     (mst_wlast),
    .mst_wdata     (mst_wdata),

    .mst_bvalid    (mst_bvalid),
    .mst_bready    (mst_bready),
    .mst_bresp     (mst_bresp),
    .mst_bid       (mst_bid)
  );




  axi_arbiter_rd #(
    .Ports          (Ports),
    .DataBits       (DataBits),
    .AddrBits       (AddrBits),
    .LenBits        (LenBits),
    .NumPendingReads(NumPendingReads),
    .InBuffers      (InBuffers),
    .OutBuffer      (OutBuffer))
  arb_rd(
    .clk          (clk),
    .rst          (rst),

    .slv_arvalid  (slv_arvalid),
    .slv_arready  (slv_arready),
    .slv_araddr   (slv_araddr),
    .slv_arlen    (slv_arlen),

    .slv_rvalid   (slv_rvalid),
    .slv_rready   (slv_rready),
    .slv_rdata    (slv_rdata),
    .slv_rresp    (slv_rresp),
    .slv_rlast    (slv_rlast),
    .slv_rid      (slv_rid),

    .mst_arvalid  (mst_arvalid),
    .mst_arready  (mst_arready),
    .mst_araddr   (mst_araddr),
    .mst_arlen    (mst_arlen),
    .mst_arid     (mst_arid),
    .mst_arsize   (mst_arsize),
    .mst_arburst  (mst_arburst),
    .mst_arlock   (mst_arlock),

    .mst_rvalid   (mst_rvalid),
    .mst_rready   (mst_rready),
    .mst_rid      (mst_rid),
    .mst_rdata    (mst_rdata),
    .mst_rresp    (mst_rresp),
    .mst_rlast    (mst_rlast)
   );

endmodule
module axi_arbiter #(
  parameter Ports           = 2,
            DataBits        = 64,
            AddrBits        = 32,
            LenBits         = 4,
            NumPendingReads = 6,
            InBuffers       = 0,
            OutBuffer       = 1)
(
  input                        clk,
  input                        rst,

  input [Ports-1:0]            slv_awvalid,
  output [Ports-1:0]           slv_awready,
  input [Ports*AddrBits-1:0]   slv_awaddr,
  input [Ports*LenBits-1:0]    slv_awlen,

  input [Ports-1:0]            slv_wvalid,
  output [Ports-1:0]           slv_wready,
  input [Ports-1:0]            slv_wlast,
  input [Ports*DataBits/8-1:0] slv_wstrb,
  input [Ports*DataBits-1:0]   slv_wdata,

  output [Ports-1:0]           slv_bvalid,
  input [Ports-1:0]            slv_bready,
  output [Ports*2-1:0]         slv_bresp,
 	output [Ports*4-1:0]         slv_bid,

  input [Ports-1:0]            slv_arvalid,
  output [Ports-1:0]           slv_arready,
  input [Ports*AddrBits-1:0]   slv_araddr,
  input [Ports*LenBits-1:0]    slv_arlen,

  output [Ports-1:0]           slv_rvalid,
  input [Ports-1:0]            slv_rready,
  output [Ports*DataBits-1:0]  slv_rdata,
  output [Ports*2-1:0]         slv_rresp,
  output [Ports-1:0]           slv_rlast,
  output [Ports*4-1:0]         slv_rid,

  output                       mst_awvalid,
  input                        mst_awready,
  output [AddrBits-1:0]        mst_awaddr,
  output [LenBits-1:0]         mst_awlen,
  output [3:0]                 mst_awid,
  output [2:0]                 mst_awsize,
  output [1:0]                 mst_awburst,
  output [1:0]                 mst_awlock,

  output                       mst_wvalid,
  input                        mst_wready,
  output [3:0]                 mst_wid,
  output [DataBits/8-1:0]      mst_wstrb,
  output                       mst_wlast,
  output [DataBits-1:0]        mst_wdata,

  input                        mst_bvalid,
  output                       mst_bready,
  input [1:0]                  mst_bresp,
  input [3:0]                  mst_bid,

  output                       mst_arvalid,
  input                        mst_arready,
  output [AddrBits-1:0]        mst_araddr,
  output [LenBits-1:0]         mst_arlen,
  output [3:0]                 mst_arid,
  output [2:0]                 mst_arsize,
  output [1:0]                 mst_arburst,
  output [1:0]                 mst_arlock,

  input                        mst_rvalid,
  output                       mst_rready,
  input [3:0]                  mst_rid,
  input [DataBits-1:0]         mst_rdata,
  input [1:0]                  mst_rresp,
  input                        mst_rlast);





  axi_arbiter_wr #(
    .Ports          (Ports),
    .DataBits       (DataBits),
    .AddrBits       (AddrBits),
    .LenBits        (LenBits),
    .InBuffers      (InBuffers),
    .OutBuffer      (OutBuffer))
  arb_wr(
    .clk           (clk),
    .rst           (rst),

    .slv_awvalid   (slv_awvalid),
    .slv_awready   (slv_awready),
    .slv_awaddr    (slv_awaddr),
    .slv_awlen     (slv_awlen),

    .slv_wvalid    (slv_wvalid),
    .slv_wready    (slv_wready),
    .slv_wlast     (slv_wlast),
    .slv_wstrb     (slv_wstrb),
    .slv_wdata     (slv_wdata),

    .slv_bvalid    (slv_bvalid),
    .slv_bready    (slv_bready),
    .slv_bresp     (slv_bresp),
    .slv_bid       (slv_bid),

    .mst_awvalid   (mst_awvalid),
    .mst_awready   (mst_awready),
    .mst_awaddr    (mst_awaddr),
    .mst_awlen     (mst_awlen),
    .mst_awid      (mst_awid),
    .mst_awsize    (mst_awsize),
    .mst_awburst   (mst_awburst),
    .mst_awlock    (mst_awlock),

    .mst_wvalid    (mst_wvalid),
    .mst_wready    (mst_wready),
    .mst_wid       (mst_wid),
    .mst_wstrb     (mst_wstrb),
    .mst_wlast     (mst_wlast),
    .mst_wdata     (mst_wdata),

    .mst_bvalid    (mst_bvalid),
    .mst_bready    (mst_bready),
    .mst_bresp     (mst_bresp),
    .mst_bid       (mst_bid)
  );




  axi_arbiter_rd #(
    .Ports          (Ports),
    .DataBits       (DataBits),
    .AddrBits       (AddrBits),
    .LenBits        (LenBits),
    .NumPendingReads(NumPendingReads),
    .InBuffers      (InBuffers),
    .OutBuffer      (OutBuffer))
  arb_rd(
    .clk          (clk),
    .rst          (rst),

    .slv_arvalid  (slv_arvalid),
    .slv_arready  (slv_arready),
    .slv_araddr   (slv_araddr),
    .slv_arlen    (slv_arlen),

    .slv_rvalid   (slv_rvalid),
    .slv_rready   (slv_rready),
    .slv_rdata    (slv_rdata),
    .slv_rresp    (slv_rresp),
    .slv_rlast    (slv_rlast),
    .slv_rid      (slv_rid),

    .mst_arvalid  (mst_arvalid),
    .mst_arready  (mst_arready),
    .mst_araddr   (mst_araddr),
    .mst_arlen    (mst_arlen),
    .mst_arid     (mst_arid),
    .mst_arsize   (mst_arsize),
    .mst_arburst  (mst_arburst),
    .mst_arlock   (mst_arlock),

    .mst_rvalid   (mst_rvalid),
    .mst_rready   (mst_rready),
    .mst_rid      (mst_rid),
    .mst_rdata    (mst_rdata),
    .mst_rresp    (mst_rresp),
    .mst_rlast    (mst_rlast)
   );

endmodule