data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v
None: at end of input
1: b'%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:24: Cannot find include file: raggedstone_spinn_aer_if_top.h\n`include "raggedstone_spinn_aer_if_top.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if,data/full_repos/permissive/156407853/raggedstone_spinn_aer_if_top.h\n             data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if,data/full_repos/permissive/156407853/raggedstone_spinn_aer_if_top.h.v\n             data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if,data/full_repos/permissive/156407853/raggedstone_spinn_aer_if_top.h.sv\n             raggedstone_spinn_aer_if_top.h\n             raggedstone_spinn_aer_if_top.h.v\n             raggedstone_spinn_aer_if_top.h.sv\n             obj_dir/raggedstone_spinn_aer_if_top.h\n             obj_dir/raggedstone_spinn_aer_if_top.h.v\n             obj_dir/raggedstone_spinn_aer_if_top.h.sv\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:37: Define or directive not defined: \'`MODE_BITS\'\n  output reg  [`MODE_BITS - 1:0] msel,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:38: Define or directive not defined: \'`VKS_BITS\'\n  output reg   [`VKS_BITS - 1:0] vksel,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:126: Define or directive not defined: \'`LAST_MODE\'\n        if (msel == `LAST_MODE)\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (msel == `LAST_MODE)\n                              ^\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:136: Define or directive not defined: \'`LAST_MODE\'\n      if ((sel_state == 0) && (mode_sel == 1\'b0) && (msel == `LAST_MODE))\n                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:136: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if ((sel_state == 0) && (mode_sel == 1\'b0) && (msel == `LAST_MODE))\n                                                                       ^\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:138: Define or directive not defined: \'`LAST_VKS\'\n        if (vksel == `LAST_VKS)\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:194: Define or directive not defined: \'`VKS_ALT\'\n      `VKS_ALT: point <= 4\'b1110;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:194: syntax error, unexpected \':\', expecting endcase\n      `VKS_ALT: point <= 4\'b1110;\n              ^\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:206: Define or directive not defined: \'`RET_128\'\n      `RET_128:\n      ^~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:214: Define or directive not defined: \'`RET_64\'\n      `RET_64:\n      ^~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:222: Define or directive not defined: \'`RET_32\'\n      `RET_32:\n      ^~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:230: Define or directive not defined: \'`RET_16\'\n      `RET_16:\n      ^~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:238: Define or directive not defined: \'`COCHLEA\'\n      `COCHLEA:\n      ^~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:246: Define or directive not defined: \'`DIRECT\'\n      `DIRECT:\n      ^~~~~~~\n%Error: Exiting due to 16 error(s)\n'
module raggedstone_spinn_aer_if_user_int
(
  input  wire                    rst,
  input  wire                    clk,


  input  wire                    mode_sel,
  input  wire                    dump_mode,
  input  wire                    error,
  output reg  [`MODE_BITS - 1:0] msel,
  output reg   [`VKS_BITS - 1:0] vksel,


  output reg               [7:0] o_7seg,
  output reg               [3:0] o_strobe,
  output wire                    o_led_act,
  output wire                    o_led_dmp,
  output reg                     o_led_err
);



  localparam PRESCALE_BITS = 14;







  reg              [3:0] digit [0:3];
  reg              [3:0] point;
  reg              [1:0] curr_digit;

  reg                    display_clk;
  reg                    prescale_out;
  reg  [PRESCALE_BITS:0] prescale_cnt;










  function [6:0] bcd2sevenSeg;
    input [3:0] bcd;
    case (bcd)
            0: bcd2sevenSeg = 7'b000_0001;
            1: bcd2sevenSeg = 7'b100_1111;
            2: bcd2sevenSeg = 7'b001_0010;
            3: bcd2sevenSeg = 7'b000_0110;
            4: bcd2sevenSeg = 7'b100_1100;
            5: bcd2sevenSeg = 7'b010_0100;
            6: bcd2sevenSeg = 7'b110_0000;
            7: bcd2sevenSeg = 7'b000_1111;
            8: bcd2sevenSeg = 7'b000_0000;
            9: bcd2sevenSeg = 7'b000_1100;
           10: bcd2sevenSeg = 7'b111_1111;
           11: bcd2sevenSeg = 7'b111_0010;
           12: bcd2sevenSeg = 7'b110_0010;
           13: bcd2sevenSeg = 7'b110_1000;
      default: bcd2sevenSeg = 7'b111_1111;
    endcase
  endfunction










  reg sel_state;

  always @(posedge clk or posedge rst)
    if (rst)
      sel_state <= 0;
    else
      if (mode_sel == 1'b0)
        sel_state <= 1;
      else
        sel_state <= 0;





  always @(posedge clk or posedge rst)
    if (rst)
      msel <= 0;
    else
      if ((sel_state == 0) && (mode_sel == 1'b0))
      begin
        if (msel == `LAST_MODE)
          msel <= 0;
        else
          msel <= msel + 1;
      end

  always @(posedge clk or posedge rst)
    if (rst)
      vksel <= 0;
    else
      if ((sel_state == 0) && (mode_sel == 1'b0) && (msel == `LAST_MODE))
      begin
        if (vksel == `LAST_VKS)
	  vksel <= 0;
        else
	  vksel <= vksel + 1;
      end










  reg [23:0] lstate;

  assign o_led_act = lstate[23];

  always @(posedge clk or posedge rst)
    if (rst)
      lstate <= 0;
    else
      if (lstate == 24'hffffff)
        lstate <= 0;
      else
        lstate <= lstate + 1;





  assign o_led_dmp = dump_mode;





  always @(posedge clk or posedge rst)
    if (rst)
      o_led_err <= 1'b0;
    else
      if (error)
        o_led_err <= 1'b1;










  always @(posedge clk)
    case (vksel)
      `VKS_ALT: point <= 4'b1110;


      default: point <= 4'b1111;
    endcase





  always @(posedge clk)
    case (msel)
      `RET_128:
        begin
          digit[0] <= 4'd10;
          digit[1] <= 4'd1;
          digit[2] <= 4'd2;
          digit[3] <= 4'd8;
        end

      `RET_64:
        begin
          digit[0] <= 4'd10;
          digit[1] <= 4'd10;
          digit[2] <= 4'd6;
          digit[3] <= 4'd4;
        end

      `RET_32:
        begin
          digit[0] <= 4'd10;
          digit[1] <= 4'd10;
          digit[2] <= 4'd3;
          digit[3] <= 4'd2;
        end

      `RET_16:
        begin
          digit[0] <= 4'd10;
          digit[1] <= 4'd10;
          digit[2] <= 4'd1;
          digit[3] <= 4'd6;
        end

      `COCHLEA:
        begin
          digit[0] <= 4'd11;
          digit[1] <= 4'd12;
          digit[2] <= 4'd11;
          digit[3] <= 4'd13;
        end

      `DIRECT:
        begin
          digit[0] <= 4'd0;
          digit[1] <= 4'd0;
          digit[2] <= 4'd0;
          digit[3] <= 4'd0;
        end
    endcase








  always @(posedge display_clk or posedge rst)
    if (rst)
      curr_digit <= 0;
    else
      curr_digit <= curr_digit + 1;

  always @(posedge display_clk or posedge rst)
    if (rst)
      o_strobe <= 4'b0000;
    else
      case (curr_digit)
        0: o_strobe <= 4'b0001;
        1: o_strobe <= 4'b0010;
        2: o_strobe <= 4'b0100;
        3: o_strobe <= 4'b1000;
      endcase

  always @(posedge display_clk or posedge rst)
    if (rst)
      o_7seg <= 8'b1111_1111;
    else
      o_7seg <= {point[curr_digit], bcd2sevenSeg(digit[curr_digit])};





  always @(posedge clk or posedge rst)
    if (rst)
      prescale_cnt <= 0;
    else
      prescale_cnt <= prescale_cnt + 1;

  always @(posedge clk or posedge rst)
    if (rst)
      prescale_out <= 0;
    else
      prescale_out <= (prescale_cnt == 0);

  always @(posedge prescale_out)
    display_clk <= ~display_clk;

endmodule
module raggedstone_spinn_aer_if_user_int
(
  input  wire                    rst,
  input  wire                    clk,


  input  wire                    mode_sel,
  input  wire                    dump_mode,
  input  wire                    error,
  output reg  [`MODE_BITS - 1:0] msel,
  output reg   [`VKS_BITS - 1:0] vksel,


  output reg               [7:0] o_7seg,
  output reg               [3:0] o_strobe,
  output wire                    o_led_act,
  output wire                    o_led_dmp,
  output reg                     o_led_err
);




  localparam PRESCALE_BITS = 14;







  reg              [3:0] digit [0:3];
  reg              [3:0] point;
  reg              [1:0] curr_digit;

  reg                    display_clk;
  reg                    prescale_out;
  reg  [PRESCALE_BITS:0] prescale_cnt;










  function [6:0] bcd2sevenSeg;
    input [3:0] bcd;
    case (bcd)
            0: bcd2sevenSeg = 7'b000_0001;
            1: bcd2sevenSeg = 7'b100_1111;
            2: bcd2sevenSeg = 7'b001_0010;
            3: bcd2sevenSeg = 7'b000_0110;
            4: bcd2sevenSeg = 7'b100_1100;
            5: bcd2sevenSeg = 7'b010_0100;
            6: bcd2sevenSeg = 7'b110_0000;
            7: bcd2sevenSeg = 7'b000_1111;
            8: bcd2sevenSeg = 7'b000_0000;
            9: bcd2sevenSeg = 7'b000_1100;
           10: bcd2sevenSeg = 7'b111_1111;
           11: bcd2sevenSeg = 7'b111_0010;
           12: bcd2sevenSeg = 7'b110_0010;
           13: bcd2sevenSeg = 7'b110_1000;
      default: bcd2sevenSeg = 7'b111_1111;
    endcase
  endfunction










  reg sel_state;

  always @(posedge clk or posedge rst)
    if (rst)
      sel_state <= 0;
    else
      if (mode_sel == 1'b0)
        sel_state <= 1;
      else
        sel_state <= 0;





  always @(posedge clk or posedge rst)
    if (rst)
      msel <= 0;
    else
      if ((sel_state == 0) && (mode_sel == 1'b0))
      begin
        if (msel == `LAST_MODE)
          msel <= 0;
        else
          msel <= msel + 1;
      end

  always @(posedge clk or posedge rst)
    if (rst)
      vksel <= 0;
    else
      if ((sel_state == 0) && (mode_sel == 1'b0) && (msel == `LAST_MODE))
      begin
        if (vksel == `LAST_VKS)
	  vksel <= 0;
        else
	  vksel <= vksel + 1;
      end










  reg [23:0] lstate;

  assign o_led_act = lstate[23];

  always @(posedge clk or posedge rst)
    if (rst)
      lstate <= 0;
    else
      if (lstate == 24'hffffff)
        lstate <= 0;
      else
        lstate <= lstate + 1;





  assign o_led_dmp = dump_mode;





  always @(posedge clk or posedge rst)
    if (rst)
      o_led_err <= 1'b0;
    else
      if (error)
        o_led_err <= 1'b1;










  always @(posedge clk)
    case (vksel)
      `VKS_ALT: point <= 4'b1110;


      default: point <= 4'b1111;
    endcase





  always @(posedge clk)
    case (msel)
      `RET_128:
        begin
          digit[0] <= 4'd10;
          digit[1] <= 4'd1;
          digit[2] <= 4'd2;
          digit[3] <= 4'd8;
        end

      `RET_64:
        begin
          digit[0] <= 4'd10;
          digit[1] <= 4'd10;
          digit[2] <= 4'd6;
          digit[3] <= 4'd4;
        end

      `RET_32:
        begin
          digit[0] <= 4'd10;
          digit[1] <= 4'd10;
          digit[2] <= 4'd3;
          digit[3] <= 4'd2;
        end

      `RET_16:
        begin
          digit[0] <= 4'd10;
          digit[1] <= 4'd10;
          digit[2] <= 4'd1;
          digit[3] <= 4'd6;
        end

      `COCHLEA:
        begin
          digit[0] <= 4'd11;
          digit[1] <= 4'd12;
          digit[2] <= 4'd11;
          digit[3] <= 4'd13;
        end

      `DIRECT:
        begin
          digit[0] <= 4'd0;
          digit[1] <= 4'd0;
          digit[2] <= 4'd0;
          digit[3] <= 4'd0;
        end
    endcase








  always @(posedge display_clk or posedge rst)
    if (rst)
      curr_digit <= 0;
    else
      curr_digit <= curr_digit + 1;

  always @(posedge display_clk or posedge rst)
    if (rst)
      o_strobe <= 4'b0000;
    else
      case (curr_digit)
        0: o_strobe <= 4'b0001;
        1: o_strobe <= 4'b0010;
        2: o_strobe <= 4'b0100;
        3: o_strobe <= 4'b1000;
      endcase

  always @(posedge display_clk or posedge rst)
    if (rst)
      o_7seg <= 8'b1111_1111;
    else
      o_7seg <= {point[curr_digit], bcd2sevenSeg(digit[curr_digit])};





  always @(posedge clk or posedge rst)
    if (rst)
      prescale_cnt <= 0;
    else
      prescale_cnt <= prescale_cnt + 1;

  always @(posedge clk or posedge rst)
    if (rst)
      prescale_out <= 0;
    else
      prescale_out <= (prescale_cnt == 0);

  always @(posedge prescale_out)
    display_clk <= ~display_clk;

endmodule