data/full_repos/permissive/165490876/src/synth/PDMEncoder.v
data/verilator_xmls/df7e90cf-52e1-40d9-aec9-caf748061981.xml
module PDMEncoder  #(parameter DATA_BITS = 10)(
  input [DATA_BITS-1:0] amplitude,
  input wire clock,
  output wire digital_out
);
	reg [DATA_BITS:0] accumulator;
	
	always @(posedge clock) begin
	  accumulator <= (accumulator[DATA_BITS-1 : 0] + amplitude);
	end

	assign digital_out = accumulator[DATA_BITS];

endmodule
module PDMEncoder  #(parameter DATA_BITS = 10)(
  input [DATA_BITS-1:0] amplitude,
  input wire clock,
  output wire digital_out
);

	reg [DATA_BITS:0] accumulator;
	
	always @(posedge clock) begin
	  accumulator <= (accumulator[DATA_BITS-1 : 0] + amplitude);
	end

	assign digital_out = accumulator[DATA_BITS];

endmodule