data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v
 line:51: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_rst = 1\'b1;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0000000000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0000100000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0001000000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0001100000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0010000000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0010100000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0011000000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0011100000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0000000000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0000100000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0001000000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0001100000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0010000000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0010100000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0011000000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0011100000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_instruc = 16\'b0000000000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:54: Unsupported: Ignoring delay on this delayed statement.\n    always #1 i_clk = ~i_clk;\n           ^\n%Error: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_control.v:56: Cannot find file containing module: \'control\'\n    control #(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/control\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/control.v\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/control.sv\n             control\n             control.v\n             control.sv\n             obj_dir/control\n             obj_dir/control.v\n             obj_dir/control.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_control();

    parameter NB_INSTRUC      = 16;
    parameter NB_OPCODE       = 5;
    parameter NB_OPERAND      = 11;
    parameter NB_ADDR         = 11;


    reg                          i_clk;
    reg                          i_rst;
    reg [NB_INSTRUC - 1 : 0]     i_instruc;

    wire [NB_OPERAND - 1 : 0]    o_operand;
    wire [NB_ADDR -1 : 0]        o_addr;

    wire [1 : 0]                 o_SelA;
    wire                         o_SelB;
    wire                         o_WrAcc;
    wire                         o_op;
    wire                         o_WrRam;
    wire                         o_RdRam;


    initial begin
        i_clk = 1'b0;
        i_rst = 1'b0;
        i_instruc = {NB_INSTRUC{1'b0}};

        #10 i_rst = 1'b1;

        #10 i_instruc = 16'b0000000000011101;
        #10 i_instruc = 16'b0000100000011101;
        #10 i_instruc = 16'b0001000000011101;
        #10 i_instruc = 16'b0001100000011101;
        #10 i_instruc = 16'b0010000000000000;
        #10 i_instruc = 16'b0010100000000000;
        #10 i_instruc = 16'b0011000000000000;
        #10 i_instruc = 16'b0011100000000000;
        #10 i_instruc = 16'b0000000000000000;
        #10 i_instruc = 16'b0000100000000000;
        #10 i_instruc = 16'b0001000000000000;
        #10 i_instruc = 16'b0001100000000000;
        #10 i_instruc = 16'b0010000000000000;
        #10 i_instruc = 16'b0010100000011101;
        #10 i_instruc = 16'b0011000000011101;
        #10 i_instruc = 16'b0011100000011101;
        #10 i_instruc = 16'b0000000000011101;
        
        #10 $finish;
    end

    always #1 i_clk = ~i_clk;

    control #(
        .NB_INSTRUC (NB_INSTRUC),
        .NB_OPCODE  (NB_OPCODE),
        .NB_OPERAND (NB_OPERAND),
        .NB_ADDR  	(NB_ADDR)
    )
    tb_control (

        .i_clk      (i_clk),
        .i_rst      (i_rst),
        .i_instruc  (i_instruc),

        .o_operand  (o_operand),
        .o_addr     (o_addr),
        .o_SelA     (o_SelA),
        .o_SelB     (o_SelB),
        .o_WrAcc    (o_WrAcc),
        .o_op       (o_op),
        .o_WrRam    (o_WrRam),
        .o_RdRam    (o_RdRam)
    );

endmodule
module tb_control();


    parameter NB_INSTRUC      = 16;
    parameter NB_OPCODE       = 5;
    parameter NB_OPERAND      = 11;
    parameter NB_ADDR         = 11;


    reg                          i_clk;
    reg                          i_rst;
    reg [NB_INSTRUC - 1 : 0]     i_instruc;

    wire [NB_OPERAND - 1 : 0]    o_operand;
    wire [NB_ADDR -1 : 0]        o_addr;

    wire [1 : 0]                 o_SelA;
    wire                         o_SelB;
    wire                         o_WrAcc;
    wire                         o_op;
    wire                         o_WrRam;
    wire                         o_RdRam;


    initial begin
        i_clk = 1'b0;
        i_rst = 1'b0;
        i_instruc = {NB_INSTRUC{1'b0}};

        #10 i_rst = 1'b1;

        #10 i_instruc = 16'b0000000000011101;
        #10 i_instruc = 16'b0000100000011101;
        #10 i_instruc = 16'b0001000000011101;
        #10 i_instruc = 16'b0001100000011101;
        #10 i_instruc = 16'b0010000000000000;
        #10 i_instruc = 16'b0010100000000000;
        #10 i_instruc = 16'b0011000000000000;
        #10 i_instruc = 16'b0011100000000000;
        #10 i_instruc = 16'b0000000000000000;
        #10 i_instruc = 16'b0000100000000000;
        #10 i_instruc = 16'b0001000000000000;
        #10 i_instruc = 16'b0001100000000000;
        #10 i_instruc = 16'b0010000000000000;
        #10 i_instruc = 16'b0010100000011101;
        #10 i_instruc = 16'b0011000000011101;
        #10 i_instruc = 16'b0011100000011101;
        #10 i_instruc = 16'b0000000000011101;
        
        #10 $finish;
    end

    always #1 i_clk = ~i_clk;

    control #(
        .NB_INSTRUC (NB_INSTRUC),
        .NB_OPCODE  (NB_OPCODE),
        .NB_OPERAND (NB_OPERAND),
        .NB_ADDR  	(NB_ADDR)
    )
    tb_control (

        .i_clk      (i_clk),
        .i_rst      (i_rst),
        .i_instruc  (i_instruc),

        .o_operand  (o_operand),
        .o_addr     (o_addr),
        .o_SelA     (o_SelA),
        .o_SelB     (o_SelB),
        .o_WrAcc    (o_WrAcc),
        .o_op       (o_op),
        .o_WrRam    (o_WrRam),
        .o_RdRam    (o_RdRam)
    );

endmodule