data/full_repos/permissive/143278/ivltests/br_gh315.v
 line:14: before: ">"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh315.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #50  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/br_gh315.v:72: Unsupported: wait statements\n    wait(B === 8\'b11111111);\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh315.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #50  \n    ^\n%Error: data/full_repos/permissive/143278/ivltests/br_gh315.v:90: Unsupported: wait statements\n    wait(B === 8\'b00000000);\n    ^~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hct74245(
  input dir,
  input nOE,
  inout [7:0] A,
  inout [7:0] B,
  output [7:0] C
);



  specify
    (A *> C) = 100;
    (A *> B) = 10;
    (B *> A) = 10;
    (dir *> A) = 16;
    (dir *> B) = 16;
    (nOE *> A) = 16;
    (nOE *> B) = 16;
  endspecify

  assign A=nOE? 8'bzzzzzzzz : dir?8'bzzzzzzzz:B;
  assign B=nOE? 8'bzzzzzzzz : dir?A:8'bzzzzzzzz;
  assign C=A;





endmodule
module hct74245(
  input dir,
  input nOE,
  inout [7:0] A,
  inout [7:0] B,
  output [7:0] C
);




  specify
    (A *> C) = 100;
    (A *> B) = 10;
    (B *> A) = 10;
    (dir *> A) = 16;
    (dir *> B) = 16;
    (nOE *> A) = 16;
    (nOE *> B) = 16;
  endspecify

  assign A=nOE? 8'bzzzzzzzz : dir?8'bzzzzzzzz:B;
  assign B=nOE? 8'bzzzzzzzz : dir?A:8'bzzzzzzzz;
  assign C=A;





endmodule