data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc/pulse_sync.v
 line:23: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc/pulse_sync.v:43: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                               : ... In instance pulse_sync\n    out_sync   <= {out_sync, in_tog};\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pulse_sync (
  input      din_rst,
  input      din_clk,
  input      din_pulse,

  input      dout_rst,
  input      dout_clk,
  output reg dout_pulse
);


  reg in_tog;
  always @(posedge din_clk) begin
    in_tog <= (din_pulse) ? ~in_tog : in_tog;
    if (din_rst)
      in_tog <= 0;
  end


  reg [2:0] out_sync;
  always @(posedge dout_clk) begin
    out_sync   <= {out_sync, in_tog};
    dout_pulse <= out_sync[2] ^ out_sync[1];
    if (dout_rst) begin
      out_sync   <= 0;
      dout_pulse <= 0;
    end
  end

endmodule
module pulse_sync (
  input      din_rst,
  input      din_clk,
  input      din_pulse,

  input      dout_rst,
  input      dout_clk,
  output reg dout_pulse
);



  reg in_tog;
  always @(posedge din_clk) begin
    in_tog <= (din_pulse) ? ~in_tog : in_tog;
    if (din_rst)
      in_tog <= 0;
  end


  reg [2:0] out_sync;
  always @(posedge dout_clk) begin
    out_sync   <= {out_sync, in_tog};
    dout_pulse <= out_sync[2] ^ out_sync[1];
    if (dout_rst) begin
      out_sync   <= 0;
      dout_pulse <= 0;
    end
  end

endmodule