data/full_repos/permissive/124591763/servo/servo_drv_tb.v
 line:23: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/124591763/servo/servo_drv_tb.v:6: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk <= ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/124591763/servo/servo_drv_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("servo_drv_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/124591763/servo/servo_drv_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/124591763/servo/servo_drv_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #500\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/servo/servo_drv_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #500\n        ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module servo_drv_tb;

    reg       clk = 1'b0;
    reg [7:0] pos = 8'h0;

    always #5 clk <= ~clk;

    servo_drv uut (
        .clk   (clk  ),

        .on_t  ({7'h0, pos}),
        .srv_o (srv_o)
    );

    initial begin
        $dumpfile("servo_drv_tb.vcd");
        $dumpvars;

        #500
        pos = 8'd90;
        #500

        $display("sim done");
        $finish;
    end

endmodule
module servo_drv_tb;


    reg       clk = 1'b0;
    reg [7:0] pos = 8'h0;

    always #5 clk <= ~clk;

    servo_drv uut (
        .clk   (clk  ),

        .on_t  ({7'h0, pos}),
        .srv_o (srv_o)
    );

    initial begin
        $dumpfile("servo_drv_tb.vcd");
        $dumpvars;

        #500
        pos = 8'd90;
        #500

        $display("sim done");
        $finish;
    end

endmodule