data/full_repos/permissive/143286506/Ver2/resisterfile.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/143286506/Ver2/resisterfile.v:24: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'resisterfile\'\nmodule resisterfile(\n       ^~~~~~~~~~~~\n                                                                              : ... Top module \'writeback\'\nmodule writeback(clk,rstd,nextpc,pc);\n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module resisterfile(
  clk,
  rstd,
  wr,
  ra1,
  ra2,
  wa,
  wren,
  rr1,
  rr2
);
input clk,rstd,wren;
input [31:0] wr;
input [4:0] ra1,ra2,wa;
output [31:0] rr1,rr2;
reg [31:0] rf [0:31];
assign rr1 = rf[ra1];
assign rr2 = rf[ra2];
always @(negedge rstd or posedge clk)
    if (rstd == 0) rf [0] <= 32'h00000000;
    else if(wren == 0) rf [wa] <= wr;
endmodule
module resisterfile(
  clk,
  rstd,
  wr,
  ra1,
  ra2,
  wa,
  wren,
  rr1,
  rr2
);

input clk,rstd,wren;
input [31:0] wr;
input [4:0] ra1,ra2,wa;
output [31:0] rr1,rr2;
reg [31:0] rf [0:31];
assign rr1 = rf[ra1];
assign rr2 = rf[ra2];
always @(negedge rstd or posedge clk)
    if (rstd == 0) rf [0] <= 32'h00000000;
    else if(wren == 0) rf [wa] <= wr;
endmodule