data/full_repos/permissive/138713719/hdl/addr_bus_test.v
data/verilator_xmls/3f5398f8-7fad-436c-8f0d-772a98e52617.xml
module addr_bus_test
    (
    input wire clk,
    input wire rst,
    
    input wire en,
    
    output reg mem,
    output reg rw,
    input wire ready,
    
    output reg [19:0] addr,
    output reg [7:0] data2ram,
    input wire [7:0] data2fpga,
    
    output wire done,
    output wire result
    );
    
    

   

    localparam S_IDLE    = 3'd0,
               S_INIT    = 3'd1,
               S_WRITE   = 3'd2,
               S_READ    = 3'd3,
               S_COMPARE = 3'd4,
               S_REINIT  = 3'd5,
               S_DONE    = 3'd6;
    

    localparam INIT_ADDR = 20'h0_0000;
    localparam INIT_DATA = 8'b1010_1010;
    localparam TEST_DATA = ~INIT_DATA;
    

    localparam FAIL    = 1'b0,
               SUCCESS = 1'b1;
    
    

    

    reg [2:0] state_ff, state_ns;
    

    reg [19:0] addr_ff, addr_ns;
    reg [19:0] test_addr_ff, test_addr_ns;
    wire [7:0] data;
    reg result_ff, result_ns;
    
    

    

    assign data = (addr_ff == test_addr_ff) ? TEST_DATA : INIT_DATA;
    
    

    
    always @(posedge clk, posedge rst)
        if(rst)
            begin
                state_ff <= S_IDLE;
                addr_ff <= 20'h0_0001;
                test_addr_ff <= INIT_ADDR;
                result_ff <= FAIL;
            end
        else
            begin
                state_ff <= state_ns;
                addr_ff <= addr_ns;
                test_addr_ff <= test_addr_ns;
                result_ff <= result_ns;
            end
    
    

    
    always @*
        begin
            state_ns = state_ff;
            

            mem = 1'b0;
            rw = 1'b1;
            addr = 20'h0_0000;
            data2ram = 8'd0;
            
            addr_ns = addr_ff;
            test_addr_ns = test_addr_ff;
            result_ns = result_ff;
            
            case(state_ff)

                S_IDLE:
                    if(en)
                        begin                    

                            addr_ns = 20'h0_0001;
                            test_addr_ns = INIT_ADDR;
                            result_ns = FAIL;
                            
                            state_ns = S_INIT;
                        end
                

                S_INIT:
                    if(ready)
                        begin
                            mem = 1'b1;
                            rw = 1'b0;
                            addr = addr_ff;
                            data2ram = INIT_DATA;
                            

                            if(addr_ff[19])
                                begin

                                    addr_ns = INIT_ADDR;
                                    state_ns = S_WRITE;
                                end
                            else
                                begin
                                    addr_ns = addr_ff << 1;
                                    state_ns = S_INIT;
                                end
                        end
                

                S_WRITE:
                    if(ready)
                        begin
                            mem = 1'b1;
                            rw = 1'b0;
                            addr = test_addr_ff;
                            data2ram = TEST_DATA;
                            
                            state_ns = S_READ;
                        end
                

                S_READ:
                    if(ready)
                        begin                            
                            mem = 1'b1;
                            rw = 1'b1;
                            addr = addr_ff;
                            
                            state_ns = S_COMPARE;
                        end
                

                S_COMPARE:
                    if(ready)
                        if(data2fpga != data)
                            state_ns = S_DONE;
                        else
                            if(addr_ff[19])
                                begin
                                    if(test_addr_ff[19])
                                        begin


                                            result_ns = SUCCESS;
                                            state_ns = S_DONE;
                                        end
                                    else
                                        begin



                                            addr_ns = INIT_ADDR;
                                            state_ns = S_REINIT;
                                        end
                                end
                            else
                                begin

                                    if(addr_ff == 20'h0_0000)
                                        addr_ns = 20'h0_0001;
                                    else
                                        addr_ns = addr_ff << 1;
                                    
                                    state_ns = S_READ;
                                end
                

                S_REINIT:
                    if(ready)
                        begin
                            mem = 1'b1;
                            rw = 1'b0;
                            addr = test_addr_ff;
                            data2ram = INIT_DATA;
                            

                            if(test_addr_ff == 20'h0_0000)
                                test_addr_ns = 20'h0_0001;
                            else
                                test_addr_ns = test_addr_ff << 1;
                            
                            state_ns = S_WRITE;
                        end
                
                S_DONE:
                    state_ns = S_DONE;
                
                default:
                    state_ns = S_DONE;
            
            endcase
        end
    
    

    

    assign done = (state_ff == S_DONE);
    assign result = result_ff;
    
endmodule
module addr_bus_test
    (
    input wire clk,
    input wire rst,
    
    input wire en,
    
    output reg mem,
    output reg rw,
    input wire ready,
    
    output reg [19:0] addr,
    output reg [7:0] data2ram,
    input wire [7:0] data2fpga,
    
    output wire done,
    output wire result
    );

    
    

   

    localparam S_IDLE    = 3'd0,
               S_INIT    = 3'd1,
               S_WRITE   = 3'd2,
               S_READ    = 3'd3,
               S_COMPARE = 3'd4,
               S_REINIT  = 3'd5,
               S_DONE    = 3'd6;
    

    localparam INIT_ADDR = 20'h0_0000;
    localparam INIT_DATA = 8'b1010_1010;
    localparam TEST_DATA = ~INIT_DATA;
    

    localparam FAIL    = 1'b0,
               SUCCESS = 1'b1;
    
    

    

    reg [2:0] state_ff, state_ns;
    

    reg [19:0] addr_ff, addr_ns;
    reg [19:0] test_addr_ff, test_addr_ns;
    wire [7:0] data;
    reg result_ff, result_ns;
    
    

    

    assign data = (addr_ff == test_addr_ff) ? TEST_DATA : INIT_DATA;
    
    

    
    always @(posedge clk, posedge rst)
        if(rst)
            begin
                state_ff <= S_IDLE;
                addr_ff <= 20'h0_0001;
                test_addr_ff <= INIT_ADDR;
                result_ff <= FAIL;
            end
        else
            begin
                state_ff <= state_ns;
                addr_ff <= addr_ns;
                test_addr_ff <= test_addr_ns;
                result_ff <= result_ns;
            end
    
    

    
    always @*
        begin
            state_ns = state_ff;
            

            mem = 1'b0;
            rw = 1'b1;
            addr = 20'h0_0000;
            data2ram = 8'd0;
            
            addr_ns = addr_ff;
            test_addr_ns = test_addr_ff;
            result_ns = result_ff;
            
            case(state_ff)

                S_IDLE:
                    if(en)
                        begin                    

                            addr_ns = 20'h0_0001;
                            test_addr_ns = INIT_ADDR;
                            result_ns = FAIL;
                            
                            state_ns = S_INIT;
                        end
                

                S_INIT:
                    if(ready)
                        begin
                            mem = 1'b1;
                            rw = 1'b0;
                            addr = addr_ff;
                            data2ram = INIT_DATA;
                            

                            if(addr_ff[19])
                                begin

                                    addr_ns = INIT_ADDR;
                                    state_ns = S_WRITE;
                                end
                            else
                                begin
                                    addr_ns = addr_ff << 1;
                                    state_ns = S_INIT;
                                end
                        end
                

                S_WRITE:
                    if(ready)
                        begin
                            mem = 1'b1;
                            rw = 1'b0;
                            addr = test_addr_ff;
                            data2ram = TEST_DATA;
                            
                            state_ns = S_READ;
                        end
                

                S_READ:
                    if(ready)
                        begin                            
                            mem = 1'b1;
                            rw = 1'b1;
                            addr = addr_ff;
                            
                            state_ns = S_COMPARE;
                        end
                

                S_COMPARE:
                    if(ready)
                        if(data2fpga != data)
                            state_ns = S_DONE;
                        else
                            if(addr_ff[19])
                                begin
                                    if(test_addr_ff[19])
                                        begin


                                            result_ns = SUCCESS;
                                            state_ns = S_DONE;
                                        end
                                    else
                                        begin



                                            addr_ns = INIT_ADDR;
                                            state_ns = S_REINIT;
                                        end
                                end
                            else
                                begin

                                    if(addr_ff == 20'h0_0000)
                                        addr_ns = 20'h0_0001;
                                    else
                                        addr_ns = addr_ff << 1;
                                    
                                    state_ns = S_READ;
                                end
                

                S_REINIT:
                    if(ready)
                        begin
                            mem = 1'b1;
                            rw = 1'b0;
                            addr = test_addr_ff;
                            data2ram = INIT_DATA;
                            

                            if(test_addr_ff == 20'h0_0000)
                                test_addr_ns = 20'h0_0001;
                            else
                                test_addr_ns = test_addr_ff << 1;
                            
                            state_ns = S_WRITE;
                        end
                
                S_DONE:
                    state_ns = S_DONE;
                
                default:
                    state_ns = S_DONE;
            
            endcase
        end
    
    

    

    assign done = (state_ff == S_DONE);
    assign result = result_ff;
    
endmodule