data/full_repos/permissive/187199324/stannel/Heap.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/187199324/stannel/Heap.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:5: Define or directive not defined: \'`ADDRESS_BITS\'\n  parameter addrBits  = `ADDRESS_BITS,  \n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:5: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  parameter addrBits  = `ADDRESS_BITS,  \n                                     ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:6: Define or directive not defined: \'`DATA_BITS\'\n  parameter dataBits  = `DATA_BITS,\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:6: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  parameter dataBits  = `DATA_BITS,\n                                  ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:9: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter heapMax   = 8\'hFF,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:10: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter allocSize = 1) (\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:10: syntax error, unexpected \')\', expecting \';\'\n  parameter allocSize = 1) (\n                         ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                reset,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                 finished,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:16: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg  [addrBits-1:0] address,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:17: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                 readWriteMode,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:19: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire [dataBits-1:0] dataOut,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg  [dataBits-1:0] dataIn,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:23: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire                alloc,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg  [addrBits-1:0] allocAddress,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:25: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire                free,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [addrBits-1:0] freeAddress\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:27: syntax error, unexpected \')\', expecting \',\' or \';\'\n  );\n  ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:49: syntax error, unexpected always\n  always @(posedge clk)\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:83: Define or directive not defined: \'`RAM_READ\'\n    readWriteMode                   = `RAM_READ;\n                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:111: Define or directive not defined: \'`RAM_WRITE\'\n              readWriteMode = `RAM_WRITE;\n                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap.v:129: Define or directive not defined: \'`RAM_WRITE\'\n          readWriteMode = `RAM_WRITE;\n                          ^~~~~~~~~~\n%Error: Exiting due to 23 error(s)\n'
module Heap #(
  parameter addrBits  = `ADDRESS_BITS,
  parameter dataBits  = `DATA_BITS,

  parameter heapBase  = 0,
  parameter heapMax   = 8'hFF,
  parameter allocSize = 1) (

    input  wire                clk,
    input  wire                reset,
    output reg                 finished,

    output reg  [addrBits-1:0] address,
    output reg                 readWriteMode,

    input  wire [dataBits-1:0] dataOut,

    output reg  [dataBits-1:0] dataIn,

    input  wire                alloc,
    output reg  [addrBits-1:0] allocAddress,
    input  wire                free,
    input  wire [addrBits-1:0] freeAddress
  );


  reg [addrBits-1:0] heapFree;
  reg [addrBits-1:0] heapEnd;

  localparam STATE_INIT             = 2'd0;
  localparam STATE_UPDATE_HEAP_FREE = 2'd1;
  localparam STATE_WRITE_FREE       = 2'd2;

  reg [1:0] rState;


  reg wIncrementHeapEnd;
  reg wUpdateHeapFreeFromMemory;
  reg wUpdateHeapFreeFromFreedAddress;
  reg wAllocFromHeapEnd;
  reg wFinished;

  reg [1:0] wNextState;


  always @(posedge clk)
  begin
    if (!reset)
      begin
        rState   <= STATE_INIT;
        heapFree <= 0;
        heapEnd  <= heapBase;
        finished <= 0;
      end
    else
      begin
        rState <= wNextState;
        finished <= wFinished;

        if (wIncrementHeapEnd)
          heapEnd <= heapEnd + allocSize;

        if (wAllocFromHeapEnd)
          allocAddress <= heapEnd;
        else if (wUpdateHeapFreeFromMemory)
          allocAddress <= heapFree;

        if (wUpdateHeapFreeFromMemory)
          heapFree <= dataOut[7:0];
        else if (wUpdateHeapFreeFromFreedAddress)
          heapFree <= freeAddress;
      end
  end


  always @(*)
  begin
    address                         = {addrBits{1'bx}};
    dataIn                          = {dataBits{1'bx}};
    readWriteMode                   = `RAM_READ;
    wFinished                       = 0;
    wIncrementHeapEnd               = 0;
    wUpdateHeapFreeFromMemory       = 0;
    wUpdateHeapFreeFromFreedAddress = 0;
    wAllocFromHeapEnd               = 0;
    wNextState                      = rState;
    case (rState)
      STATE_INIT:
        begin
          if (alloc)
            begin
              if (heapEnd != heapMax)
                begin
                  wIncrementHeapEnd = 1;
                  wAllocFromHeapEnd = 1;
                  wFinished         = 1;
                  wNextState        = STATE_INIT;
                end
              else
                begin
                  address   = heapFree;
                  wNextState = STATE_UPDATE_HEAP_FREE;
                end
            end
          else if (free)
            begin
              address       = freeAddress;
              readWriteMode = `RAM_WRITE;
              dataIn        = { 8'b0, heapFree };
              wNextState    = STATE_WRITE_FREE;
            end
          else
            wNextState       = STATE_INIT;
        end
      STATE_UPDATE_HEAP_FREE:
        begin
          address                   = heapFree;
          wUpdateHeapFreeFromMemory = 1;
          wFinished                 = 1;
          wNextState                = STATE_INIT;
        end
      STATE_WRITE_FREE:
        begin

          address       = freeAddress;
          readWriteMode = `RAM_WRITE;
          dataIn        = { 8'b0, heapFree };

          wNextState                      = STATE_INIT;
          wUpdateHeapFreeFromFreedAddress = 1;
          wFinished                       = 1;
        end
      default: begin end
    endcase
  end

endmodule
module Heap #(
  parameter addrBits  = `ADDRESS_BITS,
  parameter dataBits  = `DATA_BITS,

  parameter heapBase  = 0,
  parameter heapMax   = 8'hFF,
  parameter allocSize = 1) (

    input  wire                clk,
    input  wire                reset,
    output reg                 finished,

    output reg  [addrBits-1:0] address,
    output reg                 readWriteMode,

    input  wire [dataBits-1:0] dataOut,

    output reg  [dataBits-1:0] dataIn,

    input  wire                alloc,
    output reg  [addrBits-1:0] allocAddress,
    input  wire                free,
    input  wire [addrBits-1:0] freeAddress
  );



  reg [addrBits-1:0] heapFree;
  reg [addrBits-1:0] heapEnd;

  localparam STATE_INIT             = 2'd0;
  localparam STATE_UPDATE_HEAP_FREE = 2'd1;
  localparam STATE_WRITE_FREE       = 2'd2;

  reg [1:0] rState;


  reg wIncrementHeapEnd;
  reg wUpdateHeapFreeFromMemory;
  reg wUpdateHeapFreeFromFreedAddress;
  reg wAllocFromHeapEnd;
  reg wFinished;

  reg [1:0] wNextState;


  always @(posedge clk)
  begin
    if (!reset)
      begin
        rState   <= STATE_INIT;
        heapFree <= 0;
        heapEnd  <= heapBase;
        finished <= 0;
      end
    else
      begin
        rState <= wNextState;
        finished <= wFinished;

        if (wIncrementHeapEnd)
          heapEnd <= heapEnd + allocSize;

        if (wAllocFromHeapEnd)
          allocAddress <= heapEnd;
        else if (wUpdateHeapFreeFromMemory)
          allocAddress <= heapFree;

        if (wUpdateHeapFreeFromMemory)
          heapFree <= dataOut[7:0];
        else if (wUpdateHeapFreeFromFreedAddress)
          heapFree <= freeAddress;
      end
  end


  always @(*)
  begin
    address                         = {addrBits{1'bx}};
    dataIn                          = {dataBits{1'bx}};
    readWriteMode                   = `RAM_READ;
    wFinished                       = 0;
    wIncrementHeapEnd               = 0;
    wUpdateHeapFreeFromMemory       = 0;
    wUpdateHeapFreeFromFreedAddress = 0;
    wAllocFromHeapEnd               = 0;
    wNextState                      = rState;
    case (rState)
      STATE_INIT:
        begin
          if (alloc)
            begin
              if (heapEnd != heapMax)
                begin
                  wIncrementHeapEnd = 1;
                  wAllocFromHeapEnd = 1;
                  wFinished         = 1;
                  wNextState        = STATE_INIT;
                end
              else
                begin
                  address   = heapFree;
                  wNextState = STATE_UPDATE_HEAP_FREE;
                end
            end
          else if (free)
            begin
              address       = freeAddress;
              readWriteMode = `RAM_WRITE;
              dataIn        = { 8'b0, heapFree };
              wNextState    = STATE_WRITE_FREE;
            end
          else
            wNextState       = STATE_INIT;
        end
      STATE_UPDATE_HEAP_FREE:
        begin
          address                   = heapFree;
          wUpdateHeapFreeFromMemory = 1;
          wFinished                 = 1;
          wNextState                = STATE_INIT;
        end
      STATE_WRITE_FREE:
        begin

          address       = freeAddress;
          readWriteMode = `RAM_WRITE;
          dataIn        = { 8'b0, heapFree };

          wNextState                      = STATE_INIT;
          wUpdateHeapFreeFromFreedAddress = 1;
          wFinished                       = 1;
        end
      default: begin end
    endcase
  end

endmodule