data/full_repos/permissive/168753118/rtl/modules/ALU.v
data/verilator_xmls/4773646f-f725-4abd-a37f-f4aac5e5cc5c.xml
module ALU
  #(parameter DATA_WIDTH = 32)(

    input [DATA_WIDTH-1:0]  a_data_in,
    input [DATA_WIDTH-1:0]  b_data_in,
    input [3:0]             uop_in,


    output reg [DATA_WIDTH-1:0] result_out
);























always@(*) begin
  case(uop_in)
    4'b0000: result_out = a_data_in + b_data_in;
    4'b0001: result_out = a_data_in - b_data_in;
    4'b0010: result_out = a_data_in|b_data_in;
    4'b0011: result_out = a_data_in&b_data_in;
    4'b0100: result_out = a_data_in^b_data_in;
    4'b1000: result_out = a_data_in;
    4'b1001: result_out = b_data_in;
    4'b1010: result_out = ($signed(a_data_in)<$signed(b_data_in))?32'd1:32'd0;
    4'b1011: result_out = (a_data_in<b_data_in)?32'd1:32'd0;
    4'b1101: result_out = $signed(a_data_in) >>> b_data_in[4:0];
    4'b1110: result_out = a_data_in >> b_data_in[4:0];
    4'b1111: result_out = a_data_in << b_data_in[4:0];
    default: result_out = 32'h00000000;
  endcase
end

endmodule
module ALU
  #(parameter DATA_WIDTH = 32)(

    input [DATA_WIDTH-1:0]  a_data_in,
    input [DATA_WIDTH-1:0]  b_data_in,
    input [3:0]             uop_in,


    output reg [DATA_WIDTH-1:0] result_out
);
























always@(*) begin
  case(uop_in)
    4'b0000: result_out = a_data_in + b_data_in;
    4'b0001: result_out = a_data_in - b_data_in;
    4'b0010: result_out = a_data_in|b_data_in;
    4'b0011: result_out = a_data_in&b_data_in;
    4'b0100: result_out = a_data_in^b_data_in;
    4'b1000: result_out = a_data_in;
    4'b1001: result_out = b_data_in;
    4'b1010: result_out = ($signed(a_data_in)<$signed(b_data_in))?32'd1:32'd0;
    4'b1011: result_out = (a_data_in<b_data_in)?32'd1:32'd0;
    4'b1101: result_out = $signed(a_data_in) >>> b_data_in[4:0];
    4'b1110: result_out = a_data_in >> b_data_in[4:0];
    4'b1111: result_out = a_data_in << b_data_in[4:0];
    default: result_out = 32'h00000000;
  endcase
end

endmodule