data/full_repos/permissive/169574047/counter/counter.srcs/sources_1/new/edge_dff.v
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data/verilator_xmls/76a2a36a-c493-45c6-935f-af6652cc3acf.xml
module edge_dff(output q,qbar, input d,clk,clear);


wire s, sbar, r, rbar, cbar;




assign cbar = ~clear;


assign sbar = ~(rbar & s),
       s = ~(sbar & cbar & ~clk),
       r = ~(rbar & ~clk & s),
       rbar = ~(r & cbar & d);


assign q = ~(s & qbar),
       qbar = ~(q & r & cbar);
       
endmodule
module edge_dff(output q,qbar, input d,clk,clear);



wire s, sbar, r, rbar, cbar;




assign cbar = ~clear;


assign sbar = ~(rbar & s),
       s = ~(sbar & cbar & ~clk),
       r = ~(rbar & ~clk & s),
       rbar = ~(r & cbar & d);


assign q = ~(s & qbar),
       qbar = ~(q & r & cbar);
       
endmodule