data/full_repos/permissive/160073872/fpga/hdl/soc.srcs/sources_1/new/mic_reader.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/160073872/fpga/hdl/soc.srcs/sources_1/new/mic_reader.v:34: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n                                                                                                    : ... In instance mic_reader\n            shr <= {shr, miso};\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mic_reader (
    input wire clk,
    input wire miso,
    output wire nCs,

    output reg [15:0] outData,
    output reg outStrobe
);
    parameter
        width = 32,
        divider = 228;

    
    
    reg[(width-1):0] counter = 0;
    
    always @(posedge clk)
        if (counter == (divider - 1))
            counter <= 0;
        else
            counter <= counter + 1;
    
    wire
        active = counter < 16,
        strobe = counter == 16;
    
    assign nCs = ~active;
    
    reg [15:0] shr;
 
 
    always @(posedge clk) begin
        if (active)
            shr <= {shr, miso};
        
        outStrobe <= strobe;
        if (strobe) begin
            outData <= shr >> 1;
        end
    end
endmodule
module mic_reader (
    input wire clk,
    input wire miso,
    output wire nCs,

    output reg [15:0] outData,
    output reg outStrobe
);

    parameter
        width = 32,
        divider = 228;

    
    
    reg[(width-1):0] counter = 0;
    
    always @(posedge clk)
        if (counter == (divider - 1))
            counter <= 0;
        else
            counter <= counter + 1;
    
    wire
        active = counter < 16,
        strobe = counter == 16;
    
    assign nCs = ~active;
    
    reg [15:0] shr;
 
 
    always @(posedge clk) begin
        if (active)
            shr <= {shr, miso};
        
        outStrobe <= strobe;
        if (strobe) begin
            outData <= shr >> 1;
        end
    end
endmodule