data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:3: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/src/cpu/core/storage/stations,data/full_repos/permissive/201275379/bus.v\n             data/full_repos/permissive/201275379/src/cpu/core/storage/stations,data/full_repos/permissive/201275379/bus.v.v\n             data/full_repos/permissive/201275379/src/cpu/core/storage/stations,data/full_repos/permissive/201275379/bus.v.sv\n             bus.v\n             bus.v.v\n             bus.v.sv\n             obj_dir/bus.v\n             obj_dir/bus.v.v\n             obj_dir/bus.v.sv\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:4: Cannot find include file: rob.v\n`include "rob.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:5: Cannot find include file: opgen.v\n`include "opgen.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:12: Define or directive not defined: \'`ROB_ADDR_BUS\'\n  input  [`ROB_ADDR_BUS]  rob_addr_in,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  input  [`ROB_ADDR_BUS]  rob_addr_in,\n                       ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:13: Define or directive not defined: \'`OPGEN_BUS\'\n  input  [`OPGEN_BUS]     opgen_in,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:14: Define or directive not defined: \'`SHAMT_BUS\'\n  input  [`SHAMT_BUS]     shamt_in,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:17: Define or directive not defined: \'`DATA_BUS\'\n  input  [`DATA_BUS]      operand_data_1_in,\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:18: Define or directive not defined: \'`DATA_BUS\'\n  input  [`DATA_BUS]      operand_data_2_in,\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:21: Define or directive not defined: \'`DATA_BUS\'\n  input  [`DATA_BUS]      bus_ref_id_in,\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:22: Define or directive not defined: \'`DATA_BUS\'\n  input  [`DATA_BUS]      bus_data_in,\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:25: Define or directive not defined: \'`ROB_ADDR_BUS\'\n  output  [`ROB_ADDR_BUS] rob_addr_out,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:26: Define or directive not defined: \'`OPGEN_BUS\'\n  output  [`OPGEN_BUS]    opgen_out,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:27: Define or directive not defined: \'`SHAMT_BUS\'\n  output  [`SHAMT_BUS]    shamt_out,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:28: Define or directive not defined: \'`DATA_BUS\'\n  output  [`DATA_BUS]     operand_data_1_out,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:29: Define or directive not defined: \'`DATA_BUS\'\n  output  [`DATA_BUS]     operand_data_2_out\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:33: Define or directive not defined: \'`ROB_ADDR_BUS\'\n  reg[`ROB_ADDR_BUS]  rob_addr;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:33: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`ROB_ADDR_BUS]  rob_addr;\n                   ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:34: Define or directive not defined: \'`OPGEN_BUS\'\n  reg[`OPGEN_BUS]     opgen;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`OPGEN_BUS]     opgen;\n                ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:35: Define or directive not defined: \'`SHAMT_BUS\'\n  reg[`SHAMT_BUS]     shamt;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`SHAMT_BUS]     shamt;\n                ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:38: Define or directive not defined: \'`DATA_BUS\'\n  reg[`DATA_BUS]      operand_data_1;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`DATA_BUS]      operand_data_1;\n               ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:39: Define or directive not defined: \'`DATA_BUS\'\n  reg[`DATA_BUS]      operand_data_2;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/storage/stations/RSLineInt.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`DATA_BUS]      operand_data_2;\n               ^\n%Error: Exiting due to 26 error(s)\n'
module RSLineInt(
  input                   clk,
  input                   rst,

  input                   write_en,
  input  [`ROB_ADDR_BUS]  rob_addr_in,
  input  [`OPGEN_BUS]     opgen_in,
  input  [`SHAMT_BUS]     shamt_in,
  input                   operand_is_ref_1_in,
  input                   operand_is_ref_2_in,
  input  [`DATA_BUS]      operand_data_1_in,
  input  [`DATA_BUS]      operand_data_2_in,

  input                   bus_en,
  input  [`DATA_BUS]      bus_ref_id_in,
  input  [`DATA_BUS]      bus_data_in,

  output                  ready,
  output  [`ROB_ADDR_BUS] rob_addr_out,
  output  [`OPGEN_BUS]    opgen_out,
  output  [`SHAMT_BUS]    shamt_out,
  output  [`DATA_BUS]     operand_data_1_out,
  output  [`DATA_BUS]     operand_data_2_out
);


  reg[`ROB_ADDR_BUS]  rob_addr;
  reg[`OPGEN_BUS]     opgen;
  reg[`SHAMT_BUS]     shamt;
  reg                 operand_is_ref_1;
  reg                 operand_is_ref_2;
  reg[`DATA_BUS]      operand_data_1;
  reg[`DATA_BUS]      operand_data_2;


  assign ready = !operand_is_ref_1 && !operand_is_ref_2;
  assign rob_addr_out = rob_addr;
  assign opgen_out = opgen;
  assign shamt_out = shamt;
  assign operand_data_1_out = operand_data_1;
  assign operand_data_2_out = operand_data_2;


  always @(posedge clk) begin
    if (!rst) begin
      rob_addr <= 0;
      opgen <= 0;
      shamt <= 0;
      operand_is_ref_1 <= 0;
      operand_is_ref_2 <= 0;
      operand_data_1 <= 0;
      operand_data_2 <= 0;
    end
    else if (bus_en) begin

      if (operand_is_ref_1 && bus_ref_id_in == operand_data_1) begin
        operand_is_ref_1 <= 0;
        operand_data_1 <= bus_data_in;
      end
      if (operand_is_ref_2 && bus_ref_id_in == operand_data_2) begin
        operand_is_ref_2 <= 0;
        operand_data_2 <= bus_data_in;
      end
    end
    else if (write_en) begin
      rob_addr <= rob_addr_in;
      opgen <= opgen_in;
      shamt <= shamt_in;
      operand_is_ref_1 <= operand_is_ref_1_in;
      operand_is_ref_2 <= operand_is_ref_2_in;
      operand_data_1 <= operand_data_1_in;
      operand_data_2 <= operand_data_2_in;
    end
  end

endmodule
module RSLineInt(
  input                   clk,
  input                   rst,

  input                   write_en,
  input  [`ROB_ADDR_BUS]  rob_addr_in,
  input  [`OPGEN_BUS]     opgen_in,
  input  [`SHAMT_BUS]     shamt_in,
  input                   operand_is_ref_1_in,
  input                   operand_is_ref_2_in,
  input  [`DATA_BUS]      operand_data_1_in,
  input  [`DATA_BUS]      operand_data_2_in,

  input                   bus_en,
  input  [`DATA_BUS]      bus_ref_id_in,
  input  [`DATA_BUS]      bus_data_in,

  output                  ready,
  output  [`ROB_ADDR_BUS] rob_addr_out,
  output  [`OPGEN_BUS]    opgen_out,
  output  [`SHAMT_BUS]    shamt_out,
  output  [`DATA_BUS]     operand_data_1_out,
  output  [`DATA_BUS]     operand_data_2_out
);



  reg[`ROB_ADDR_BUS]  rob_addr;
  reg[`OPGEN_BUS]     opgen;
  reg[`SHAMT_BUS]     shamt;
  reg                 operand_is_ref_1;
  reg                 operand_is_ref_2;
  reg[`DATA_BUS]      operand_data_1;
  reg[`DATA_BUS]      operand_data_2;


  assign ready = !operand_is_ref_1 && !operand_is_ref_2;
  assign rob_addr_out = rob_addr;
  assign opgen_out = opgen;
  assign shamt_out = shamt;
  assign operand_data_1_out = operand_data_1;
  assign operand_data_2_out = operand_data_2;


  always @(posedge clk) begin
    if (!rst) begin
      rob_addr <= 0;
      opgen <= 0;
      shamt <= 0;
      operand_is_ref_1 <= 0;
      operand_is_ref_2 <= 0;
      operand_data_1 <= 0;
      operand_data_2 <= 0;
    end
    else if (bus_en) begin

      if (operand_is_ref_1 && bus_ref_id_in == operand_data_1) begin
        operand_is_ref_1 <= 0;
        operand_data_1 <= bus_data_in;
      end
      if (operand_is_ref_2 && bus_ref_id_in == operand_data_2) begin
        operand_is_ref_2 <= 0;
        operand_data_2 <= bus_data_in;
      end
    end
    else if (write_en) begin
      rob_addr <= rob_addr_in;
      opgen <= opgen_in;
      shamt <= shamt_in;
      operand_is_ref_1 <= operand_is_ref_1_in;
      operand_is_ref_2 <= operand_is_ref_2_in;
      operand_data_1 <= operand_data_1_in;
      operand_data_2 <= operand_data_2_in;
    end
  end

endmodule