data/full_repos/permissive/139213403/FPGA/timer_counter_testbench.v
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/timer_counter_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/timer_counter_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/timer_counter_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/timer_counter_testbench.v:33: syntax error, unexpected \'@\'\n   @(negedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/timer_counter_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/timer_counter_testbench.v:44: syntax error, unexpected \'@\'\n   @(negedge reset);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/timer_counter_testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n   #(1000); \n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/timer_counter_testbench.v:51: syntax error, unexpected \'@\'\n   @(negedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/timer_counter_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n   #(1000);\n   ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module timer_counter_testbench;
	localparam T = 20;
	localparam M = 4, N = 4;

	reg clk, reset;
	reg [M-1:0] m;
	wire [N-1:0] counter;
	wire of;
	
	timer_counter #(.M_BITS(M), .N_BITS(N)) uut(.clk(clk), .reset(reset), .m(m), .counter(counter), .of(of));
	

	always
		begin
			clk = 1'b1;
			#(T / 2);
			clk = 1'b0;
			#(T / 2);
		end


	initial
		begin
			m = 0;
			reset = 1'b1;
			#(T / 2);
			reset = 1'b0;
		end
		
	task set_counter;
		input reg[M-1:0] m_i;
		begin
			@(negedge clk);
			m = m_i;
			reset = 1'b1;
			#(T / 2);
			reset = 1'b0;
		end
	endtask
	

	initial
		begin
			@(negedge reset);
			@(negedge clk);
			
			@(negedge clk);
			set_counter(10);
			#(1000);	
				
			@(negedge clk);
			set_counter(100);
			#(1000);
			
			$stop;
		end
endmodule
module timer_counter_testbench;

	localparam T = 20;
	localparam M = 4, N = 4;

	reg clk, reset;
	reg [M-1:0] m;
	wire [N-1:0] counter;
	wire of;
	
	timer_counter #(.M_BITS(M), .N_BITS(N)) uut(.clk(clk), .reset(reset), .m(m), .counter(counter), .of(of));
	

	always
		begin
			clk = 1'b1;
			#(T / 2);
			clk = 1'b0;
			#(T / 2);
		end


	initial
		begin
			m = 0;
			reset = 1'b1;
			#(T / 2);
			reset = 1'b0;
		end
		
	task set_counter;
		input reg[M-1:0] m_i;
		begin
			@(negedge clk);
			m = m_i;
			reset = 1'b1;
			#(T / 2);
			reset = 1'b0;
		end
	endtask
	

	initial
		begin
			@(negedge reset);
			@(negedge clk);
			
			@(negedge clk);
			set_counter(10);
			#(1000);	
				
			@(negedge clk);
			set_counter(100);
			#(1000);
			
			$stop;
		end
endmodule