data/full_repos/permissive/114664169/sequencerCore.v
1: b"%Error: data/full_repos/permissive/114664169/sequencerCore.v:64: Cannot find file containing module: 'ram'\nram myRam (\n^~~\n        ... Looked in:\n             data/full_repos/permissive/114664169,data/full_repos/permissive/114664169/ram\n             data/full_repos/permissive/114664169,data/full_repos/permissive/114664169/ram.v\n             data/full_repos/permissive/114664169,data/full_repos/permissive/114664169/ram.sv\n             ram\n             ram.v\n             ram.sv\n             obj_dir/ram\n             obj_dir/ram.v\n             obj_dir/ram.sv\n%Error: data/full_repos/permissive/114664169/sequencerCore.v:110: Cannot find file containing module: 'fifo'\nfifo myInputFifo (\n^~~~\n%Error: data/full_repos/permissive/114664169/sequencerCore.v:151: Cannot find file containing module: 'instructionparser'\ninstructionparser myInstructionParser (\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module sequencerCore(
	input sys_clock,
	
	output [23:0] o_output_bus,
	

	input i_trigger_sequence,
	input i_stop_sequence,
	output o_finished,
	

	input [31:0] i_shots,
	input [31:0] i_idle_state,
	

	input ti_clk,
	input [15:0] i_ep_data,
    input i_ep_write,
	input i_write_mode,


	input [15:0] i_spc0_value,
	input [15:0] i_spc1_value
);






wire w_ram_clock;
assign w_ram_clock = sys_clock;

wire w_ram_write_enable;
wire [9:0] w_ram_address;
wire [9:0] w_ram_instruction_address;
reg [9:0] r_fifo_ram_address; 
assign w_ram_address = i_write_mode ? r_fifo_ram_address : w_ram_instruction_address;

wire [31:0] w_ram_data_in;
wire [31:0] w_ram_data_out;

ram myRam (
	.clka(w_ram_clock ),
	.wea(w_ram_write_enable),
	.addra(w_ram_address),
	.dina(w_ram_data_in),
	.douta(w_ram_data_out)
);  


wire w_fifo_reset;
wire w_fifo_write_clock;
wire w_fifo_read_clock;
wire [15:0] w_fifo_data_in;
wire w_fifo_write_enable;
wire w_fifo_read_enable;
wire [31:0] w_fifo_data_out;
wire w_fifo_full;
wire w_fifo_empty;


assign w_ram_data_in[31:16] = w_fifo_data_out[15:0];
assign w_ram_data_in[15:0] = w_fifo_data_out[31:16];


assign w_fifo_data_in = i_ep_data;
assign w_fifo_write_clock = ti_clk & i_write_mode;
assign w_fifo_write_enable = i_ep_write & i_write_mode;
assign w_ram_write_enable = !w_fifo_empty;


initial begin
	r_fifo_ram_address <= 0;
end

assign w_fifo_read_enable = !w_fifo_empty;
assign w_fifo_read_clock = sys_clock;
assign w_fifo_reset = !i_write_mode;

always @(negedge sys_clock) begin
	if(w_fifo_read_enable == 1) begin
		r_fifo_ram_address <= r_fifo_ram_address + 1;
	end else if(i_write_mode == 0) begin
		r_fifo_ram_address <= 0;
	end
end

fifo myInputFifo (
	.rst(w_fifo_reset),
	.wr_clk(w_fifo_write_clock),
	.rd_clk(w_fifo_read_clock),
	.din(w_fifo_data_in),
	.wr_en(w_fifo_write_enable),
	.rd_en(w_fifo_read_enable),
	.dout(w_fifo_data_out),
	.full(w_fifo_full),
	.empty(w_fifo_empty)
);







wire w_spc_id;
assign w_spc_id = w_ram_data_out[26];
wire [15:0] w_spc_value;
assign w_spc_value = w_spc_id ? i_spc1_value : i_spc0_value;



wire w_stop_parsing;
assign w_stop_parsing = i_stop_sequence | i_write_mode;

reg [31:0] r_shots;
reg [31:0] r_idle_state;

initial begin
	r_shots <= 0;
	r_idle_state <= 0;
end

always @ (negedge i_write_mode) begin
	r_shots <= i_shots;
	r_idle_state <= i_idle_state;
end

instructionparser myInstructionParser (
	.sys_clock(sys_clock),
	.o_output_bus(o_output_bus),
	.o_ram_address(w_ram_instruction_address),
	.i_ram_data(w_ram_data_out),
	.i_spc_data(w_spc_value),
	.i_idle_state(r_idle_state[23:0]),
	.i_shots(r_shots),
	.i_trigger(i_trigger_sequence),
	.i_stop(w_stop_parsing),
	.o_finished(o_finished)
);

endmodule
module sequencerCore(
	input sys_clock,
	
	output [23:0] o_output_bus,
	

	input i_trigger_sequence,
	input i_stop_sequence,
	output o_finished,
	

	input [31:0] i_shots,
	input [31:0] i_idle_state,
	

	input ti_clk,
	input [15:0] i_ep_data,
    input i_ep_write,
	input i_write_mode,


	input [15:0] i_spc0_value,
	input [15:0] i_spc1_value
);







wire w_ram_clock;
assign w_ram_clock = sys_clock;

wire w_ram_write_enable;
wire [9:0] w_ram_address;
wire [9:0] w_ram_instruction_address;
reg [9:0] r_fifo_ram_address; 
assign w_ram_address = i_write_mode ? r_fifo_ram_address : w_ram_instruction_address;

wire [31:0] w_ram_data_in;
wire [31:0] w_ram_data_out;

ram myRam (
	.clka(w_ram_clock ),
	.wea(w_ram_write_enable),
	.addra(w_ram_address),
	.dina(w_ram_data_in),
	.douta(w_ram_data_out)
);  


wire w_fifo_reset;
wire w_fifo_write_clock;
wire w_fifo_read_clock;
wire [15:0] w_fifo_data_in;
wire w_fifo_write_enable;
wire w_fifo_read_enable;
wire [31:0] w_fifo_data_out;
wire w_fifo_full;
wire w_fifo_empty;


assign w_ram_data_in[31:16] = w_fifo_data_out[15:0];
assign w_ram_data_in[15:0] = w_fifo_data_out[31:16];


assign w_fifo_data_in = i_ep_data;
assign w_fifo_write_clock = ti_clk & i_write_mode;
assign w_fifo_write_enable = i_ep_write & i_write_mode;
assign w_ram_write_enable = !w_fifo_empty;


initial begin
	r_fifo_ram_address <= 0;
end

assign w_fifo_read_enable = !w_fifo_empty;
assign w_fifo_read_clock = sys_clock;
assign w_fifo_reset = !i_write_mode;

always @(negedge sys_clock) begin
	if(w_fifo_read_enable == 1) begin
		r_fifo_ram_address <= r_fifo_ram_address + 1;
	end else if(i_write_mode == 0) begin
		r_fifo_ram_address <= 0;
	end
end

fifo myInputFifo (
	.rst(w_fifo_reset),
	.wr_clk(w_fifo_write_clock),
	.rd_clk(w_fifo_read_clock),
	.din(w_fifo_data_in),
	.wr_en(w_fifo_write_enable),
	.rd_en(w_fifo_read_enable),
	.dout(w_fifo_data_out),
	.full(w_fifo_full),
	.empty(w_fifo_empty)
);







wire w_spc_id;
assign w_spc_id = w_ram_data_out[26];
wire [15:0] w_spc_value;
assign w_spc_value = w_spc_id ? i_spc1_value : i_spc0_value;



wire w_stop_parsing;
assign w_stop_parsing = i_stop_sequence | i_write_mode;

reg [31:0] r_shots;
reg [31:0] r_idle_state;

initial begin
	r_shots <= 0;
	r_idle_state <= 0;
end

always @ (negedge i_write_mode) begin
	r_shots <= i_shots;
	r_idle_state <= i_idle_state;
end

instructionparser myInstructionParser (
	.sys_clock(sys_clock),
	.o_output_bus(o_output_bus),
	.o_ram_address(w_ram_instruction_address),
	.i_ram_data(w_ram_data_out),
	.i_spc_data(w_spc_value),
	.i_idle_state(r_idle_state[23:0]),
	.i_shots(r_shots),
	.i_trigger(i_trigger_sequence),
	.i_stop(w_stop_parsing),
	.o_finished(o_finished)
);

endmodule