data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI_SLAVE.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI_SLAVE.v:7: Little bit endian vector: MSB < LSB of bit range: 0:7\n input[0:7] DATA_OUT;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI_SLAVE.v:8: Little bit endian vector: MSB < LSB of bit range: 0:7\n output reg[0:7] DATA_IN;\n           ^\n%Error: Exiting due to 2 warning(s)\n'
module FPGA_SPI_SLAVE(CLK,SCLK,MOSI,MISO,SS,DATA_IN,DATA_OUT,END_BIT);

	input wire CLK;
	input SCLK,MOSI,SS;
	output reg MISO;

	input[0:7] DATA_OUT;
	output reg[0:7] DATA_IN;

	output wire END_BIT;

	reg[2:0] Count;

	initial begin
		Count = 0;
		DATA_IN = 8'h0;
		MISO = 1;
	end

	assign END_BIT = Count != 0;
	

	always @(posedge SCLK or posedge SS) if(SS) begin
		DATA_IN <= 0;
	end else begin
		DATA_IN[Count] <= MOSI;
	end
	
	always @(negedge SCLK or posedge SS) if(SS) begin
		Count = 0;
	end else begin
		Count = Count + 1;
	end
	
	always @(negedge SCLK or negedge SS) if(!SS) begin
		MISO <= DATA_OUT[Count];
	end
		
		
endmodule
module FPGA_SPI_SLAVE(CLK,SCLK,MOSI,MISO,SS,DATA_IN,DATA_OUT,END_BIT);


	input wire CLK;
	input SCLK,MOSI,SS;
	output reg MISO;

	input[0:7] DATA_OUT;
	output reg[0:7] DATA_IN;

	output wire END_BIT;

	reg[2:0] Count;

	initial begin
		Count = 0;
		DATA_IN = 8'h0;
		MISO = 1;
	end

	assign END_BIT = Count != 0;
	

	always @(posedge SCLK or posedge SS) if(SS) begin
		DATA_IN <= 0;
	end else begin
		DATA_IN[Count] <= MOSI;
	end
	
	always @(negedge SCLK or posedge SS) if(SS) begin
		Count = 0;
	end else begin
		Count = Count + 1;
	end
	
	always @(negedge SCLK or negedge SS) if(!SS) begin
		MISO <= DATA_OUT[Count];
	end
		
		
endmodule