data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/sumador.v
1: b'%Error: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/sumador.v:10: Cannot find include file: sum_pipe.v\n`include "sum_pipe.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline,data/full_repos/permissive/178052224/sum_pipe.v\n             data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline,data/full_repos/permissive/178052224/sum_pipe.v.v\n             data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline,data/full_repos/permissive/178052224/sum_pipe.v.sv\n             sum_pipe.v\n             sum_pipe.v.v\n             sum_pipe.v.sv\n             obj_dir/sum_pipe.v\n             obj_dir/sum_pipe.v.v\n             obj_dir/sum_pipe.v.sv\n%Error: Exiting due to 1 error(s)\n'
module sumador(
               input               clk,
               input               reset_L,
               input       [3:0]   idx,
               input       [3:0]   dataA,
               input       [3:0]   dataB,
               output reg  [3:0]   sum30_dd, 
               output reg  [3:0]   idx_dd   );
    


    wire [3:0]		sum30_dd_in;

    sum_pipe pipeline(

		      .sum30_dd		(sum30_dd_in[3:0]),

		      .clk		(clk),
		      .reset_L		(reset_L),
		      .dataA		(dataA[3:0]),
		      .dataB		(dataB[3:0]));

    reg [3:0] idx_d;
    always@(*)begin
        sum30_dd = sum30_dd_in;
    end


    always@( posedge clk )begin
        if(!reset_L)begin
            idx_d   <= 'b0;
            idx_dd  <= 'b0;
        end

        idx_d <= idx;
        idx_dd <= idx_d;
        
    end
endmodule
module sumador(
               input               clk,
               input               reset_L,
               input       [3:0]   idx,
               input       [3:0]   dataA,
               input       [3:0]   dataB,
               output reg  [3:0]   sum30_dd, 
               output reg  [3:0]   idx_dd   );

    


    wire [3:0]		sum30_dd_in;

    sum_pipe pipeline(

		      .sum30_dd		(sum30_dd_in[3:0]),

		      .clk		(clk),
		      .reset_L		(reset_L),
		      .dataA		(dataA[3:0]),
		      .dataB		(dataB[3:0]));

    reg [3:0] idx_d;
    always@(*)begin
        sum30_dd = sum30_dd_in;
    end


    always@( posedge clk )begin
        if(!reset_L)begin
            idx_d   <= 'b0;
            idx_dd  <= 'b0;
        end

        idx_d <= idx;
        idx_dd <= idx_d;
        
    end
endmodule