data/full_repos/permissive/210844779/lab2/2.7/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.7/tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/210844779/lab2/2.7/tb.v:6: Cannot find file containing module: \'encoder\'\nencoder u0(I,Y);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab2/2.7,data/full_repos/permissive/210844779/encoder\n             data/full_repos/permissive/210844779/lab2/2.7,data/full_repos/permissive/210844779/encoder.v\n             data/full_repos/permissive/210844779/lab2/2.7,data/full_repos/permissive/210844779/encoder.sv\n             encoder\n             encoder.v\n             encoder.sv\n             obj_dir/encoder\n             obj_dir/encoder.v\n             obj_dir/encoder.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab2/2.7/tb.v:11: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\nI=$random;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

reg [7:0]I;
wire [2:0]Y;

encoder u0(I,Y);

always
begin

I=$random;

#10;

end

endmodule
module tb();


reg [7:0]I;
wire [2:0]Y;

encoder u0(I,Y);

always
begin

I=$random;

#10;

end

endmodule