data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v
1: b'%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:3: Cannot find include file: ../../define/bus.v\n`include "../../define/bus.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149848590/src/cpu/core/stage/mem,data/full_repos/permissive/149848590/../../define/bus.v\n             data/full_repos/permissive/149848590/src/cpu/core/stage/mem,data/full_repos/permissive/149848590/../../define/bus.v.v\n             data/full_repos/permissive/149848590/src/cpu/core/stage/mem,data/full_repos/permissive/149848590/../../define/bus.v.sv\n             ../../define/bus.v\n             ../../define/bus.v.v\n             ../../define/bus.v.sv\n             obj_dir/../../define/bus.v\n             obj_dir/../../define/bus.v.v\n             obj_dir/../../define/bus.v.sv\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:12: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] ram_read_data_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`DATA_BUS] ram_read_data_in,\n                    ^\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:18: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] result_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:20: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input [`REG_ADDR_BUS] write_reg_addr_in,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:21: Define or directive not defined: \'`ADDR_BUS\'\n    input [`ADDR_BUS] current_pc_addr_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:23: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] hi_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:24: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] lo_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:26: Define or directive not defined: \'`CP0_ADDR_BUS\'\n    input [`CP0_ADDR_BUS] cp0_addr_in,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:27: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] cp0_write_data_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:29: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] ram_read_data_out,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:36: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] result_out,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:38: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output [`REG_ADDR_BUS] write_reg_addr_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:41: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] hi_out,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:42: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] lo_out,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:45: Define or directive not defined: \'`CP0_ADDR_BUS\'\n    output [`CP0_ADDR_BUS] cp0_addr_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:46: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] cp0_write_data_out,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:48: Define or directive not defined: \'`ADDR_BUS\'\n    output [`ADDR_BUS] current_pc_addr_out\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:51: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    PipelineDeliverAsyn #(`DATA_BUS_WIDTH) ff_ram_read_data(\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:81: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    PipelineDeliver #(`DATA_BUS_WIDTH) ff_result(\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:93: Define or directive not defined: \'`REG_ADDR_BUS_WIDTH\'\n    PipelineDeliver #(`REG_ADDR_BUS_WIDTH) ff_write_reg_addr(\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:105: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    PipelineDeliver #(`DATA_BUS_WIDTH) ff_hi(\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:111: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    PipelineDeliver #(`DATA_BUS_WIDTH) ff_lo(\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:123: Define or directive not defined: \'`CP0_ADDR_BUS_WIDTH\'\n    PipelineDeliver #(`CP0_ADDR_BUS_WIDTH) ff_cp0_addr(\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:129: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    PipelineDeliver #(`DATA_BUS_WIDTH) ff_cp0_write_data(\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/mem/MEMWB.v:135: Define or directive not defined: \'`ADDR_BUS_WIDTH\'\n    PipelineDeliver #(`ADDR_BUS_WIDTH) ff_current_pc_addr(\n                      ^~~~~~~~~~~~~~~\n%Error: Exiting due to 26 error(s)\n'
module MEMWB(
    input clk,
    input rst,
    input flush,
    input stall_current_stage,
    input stall_next_stage,

    input [`DATA_BUS] ram_read_data_in,

    input mem_read_flag_in,
    input mem_write_flag_in,
    input mem_sign_ext_flag_in,
    input [3:0] mem_sel_in,
    input [`DATA_BUS] result_in,
    input  write_reg_en_in,
    input [`REG_ADDR_BUS] write_reg_addr_in,
    input [`ADDR_BUS] current_pc_addr_in,
    input hilo_write_en_in,
    input [`DATA_BUS] hi_in,
    input [`DATA_BUS] lo_in,
    input cp0_write_en_in,
    input [`CP0_ADDR_BUS] cp0_addr_in,
    input [`DATA_BUS] cp0_write_data_in,

    output [`DATA_BUS] ram_read_data_out,

    output mem_read_flag_out,
    output mem_write_flag_out,
    output mem_sign_ext_flag_out,
    output [3:0] mem_sel_out,

    output [`DATA_BUS] result_out,
    output write_reg_en_out,
    output [`REG_ADDR_BUS] write_reg_addr_out,

    output hilo_write_en_out,
    output [`DATA_BUS] hi_out,
    output [`DATA_BUS] lo_out,

    output cp0_write_en_out,
    output [`CP0_ADDR_BUS] cp0_addr_out,
    output [`DATA_BUS] cp0_write_data_out,

    output [`ADDR_BUS] current_pc_addr_out
);

    PipelineDeliverAsyn #(`DATA_BUS_WIDTH) ff_ram_read_data(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        ram_read_data_in, ram_read_data_out
    );

    PipelineDeliver #(1) ff_mem_read_flag(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        mem_read_flag_in, mem_read_flag_out
    );

    PipelineDeliver #(1) ff_mem_write_flag(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        mem_write_flag_in, mem_write_flag_out
    );

    PipelineDeliver #(1) ff_mem_sign_ext_flag(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        mem_sign_ext_flag_in, mem_sign_ext_flag_out
    );

    PipelineDeliver #(4) ff_mem_sel(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        mem_sel_in, mem_sel_out
    );

    PipelineDeliver #(`DATA_BUS_WIDTH) ff_result(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        result_in, result_out
    );

    PipelineDeliver #(1) ff_write_reg_en(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        write_reg_en_in, write_reg_en_out
    );

    PipelineDeliver #(`REG_ADDR_BUS_WIDTH) ff_write_reg_addr(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        write_reg_addr_in, write_reg_addr_out
    );

    PipelineDeliver #(1) ff_hilo_write_en(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        hilo_write_en_in, hilo_write_en_out
    );

    PipelineDeliver #(`DATA_BUS_WIDTH) ff_hi(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        hi_in, hi_out
    );

    PipelineDeliver #(`DATA_BUS_WIDTH) ff_lo(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        lo_in, lo_out
    );

    PipelineDeliver #(1) ff_cp0_write_en(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        cp0_write_en_in, cp0_write_en_out
    );

    PipelineDeliver #(`CP0_ADDR_BUS_WIDTH) ff_cp0_addr(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        cp0_addr_in, cp0_addr_out
    );

    PipelineDeliver #(`DATA_BUS_WIDTH) ff_cp0_write_data(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        cp0_write_data_in, cp0_write_data_out
    );

    PipelineDeliver #(`ADDR_BUS_WIDTH) ff_current_pc_addr(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        current_pc_addr_in, current_pc_addr_out
    );

endmodule
module MEMWB(
    input clk,
    input rst,
    input flush,
    input stall_current_stage,
    input stall_next_stage,

    input [`DATA_BUS] ram_read_data_in,

    input mem_read_flag_in,
    input mem_write_flag_in,
    input mem_sign_ext_flag_in,
    input [3:0] mem_sel_in,
    input [`DATA_BUS] result_in,
    input  write_reg_en_in,
    input [`REG_ADDR_BUS] write_reg_addr_in,
    input [`ADDR_BUS] current_pc_addr_in,
    input hilo_write_en_in,
    input [`DATA_BUS] hi_in,
    input [`DATA_BUS] lo_in,
    input cp0_write_en_in,
    input [`CP0_ADDR_BUS] cp0_addr_in,
    input [`DATA_BUS] cp0_write_data_in,

    output [`DATA_BUS] ram_read_data_out,

    output mem_read_flag_out,
    output mem_write_flag_out,
    output mem_sign_ext_flag_out,
    output [3:0] mem_sel_out,

    output [`DATA_BUS] result_out,
    output write_reg_en_out,
    output [`REG_ADDR_BUS] write_reg_addr_out,

    output hilo_write_en_out,
    output [`DATA_BUS] hi_out,
    output [`DATA_BUS] lo_out,

    output cp0_write_en_out,
    output [`CP0_ADDR_BUS] cp0_addr_out,
    output [`DATA_BUS] cp0_write_data_out,

    output [`ADDR_BUS] current_pc_addr_out
);


    PipelineDeliverAsyn #(`DATA_BUS_WIDTH) ff_ram_read_data(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        ram_read_data_in, ram_read_data_out
    );

    PipelineDeliver #(1) ff_mem_read_flag(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        mem_read_flag_in, mem_read_flag_out
    );

    PipelineDeliver #(1) ff_mem_write_flag(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        mem_write_flag_in, mem_write_flag_out
    );

    PipelineDeliver #(1) ff_mem_sign_ext_flag(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        mem_sign_ext_flag_in, mem_sign_ext_flag_out
    );

    PipelineDeliver #(4) ff_mem_sel(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        mem_sel_in, mem_sel_out
    );

    PipelineDeliver #(`DATA_BUS_WIDTH) ff_result(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        result_in, result_out
    );

    PipelineDeliver #(1) ff_write_reg_en(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        write_reg_en_in, write_reg_en_out
    );

    PipelineDeliver #(`REG_ADDR_BUS_WIDTH) ff_write_reg_addr(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        write_reg_addr_in, write_reg_addr_out
    );

    PipelineDeliver #(1) ff_hilo_write_en(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        hilo_write_en_in, hilo_write_en_out
    );

    PipelineDeliver #(`DATA_BUS_WIDTH) ff_hi(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        hi_in, hi_out
    );

    PipelineDeliver #(`DATA_BUS_WIDTH) ff_lo(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        lo_in, lo_out
    );

    PipelineDeliver #(1) ff_cp0_write_en(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        cp0_write_en_in, cp0_write_en_out
    );

    PipelineDeliver #(`CP0_ADDR_BUS_WIDTH) ff_cp0_addr(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        cp0_addr_in, cp0_addr_out
    );

    PipelineDeliver #(`DATA_BUS_WIDTH) ff_cp0_write_data(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        cp0_write_data_in, cp0_write_data_out
    );

    PipelineDeliver #(`ADDR_BUS_WIDTH) ff_current_pc_addr(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        current_pc_addr_in, current_pc_addr_out
    );

endmodule