data/full_repos/permissive/163025478/test.v
 line:47: before: "."
1: b'%Error: data/full_repos/permissive/163025478/test.v:1: Cannot find include file: cpu.v\n`include "cpu.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/163025478,data/full_repos/permissive/163025478/cpu.v\n             data/full_repos/permissive/163025478,data/full_repos/permissive/163025478/cpu.v.v\n             data/full_repos/permissive/163025478,data/full_repos/permissive/163025478/cpu.v.sv\n             cpu.v\n             cpu.v.v\n             cpu.v.sv\n             obj_dir/cpu.v\n             obj_dir/cpu.v.v\n             obj_dir/cpu.v.sv\n%Error: data/full_repos/permissive/163025478/test.v:13: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/163025478/test.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #4 reset <= 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/163025478/test.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #150 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/163025478/test.v:28: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk <= !clk;\n       ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module test();

reg clk;
reg reset;
wire [7:0] port; 

cpu c(clk, reset, port);

initial
begin
  $dumpfile("test.vcd");


  reset <= 1;
  clk <= 0;
  #4 reset <= 0;
  #150 $finish;
end

always #1 clk <= !clk;

endmodule
module test();


reg clk;
reg reset;
wire [7:0] port; 

cpu c(clk, reset, port);

initial
begin
  $dumpfile("test.vcd");


  reset <= 1;
  clk <= 0;
  #4 reset <= 0;
  #150 $finish;
end

always #1 clk <= !clk;

endmodule