data/full_repos/permissive/135077285/mux5Bits2.v
data/verilator_xmls/d2d874f6-9b01-4fd6-b3b8-9b971c42429c.xml
module mux5Bits2 (
  input wire [4:0] entrada1,
  input wire [4:0] entrada2,
  input wire seletor,
  output reg [4:0] saida
);


  always @(*) saida <= (seletor) ? entrada1 : entrada2;
endmodule
module mux5Bits2 (
  input wire [4:0] entrada1,
  input wire [4:0] entrada2,
  input wire seletor,
  output reg [4:0] saida
);



  always @(*) saida <= (seletor) ? entrada1 : entrada2;
endmodule