data/full_repos/permissive/210918583/boards/tf520/tf520r3_bus_top.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/210918583/boards/tf520/tf520r3_bus_top.v:118: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'tf520r3_bus_top\'\nmodule tf520r3_bus_top(\n       ^~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'ata\'\nmodule ata (\n       ^~~\n%Error: data/full_repos/permissive/210918583/boards/tf520/tf520r3_bus_top.v:71: Cannot find file containing module: \'bus_top\'\nbus_top BUSTOP(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210918583/boards/tf520,data/full_repos/permissive/210918583/bus_top\n             data/full_repos/permissive/210918583/boards/tf520,data/full_repos/permissive/210918583/bus_top.v\n             data/full_repos/permissive/210918583/boards/tf520,data/full_repos/permissive/210918583/bus_top.sv\n             bus_top\n             bus_top.v\n             bus_top.sv\n             obj_dir/bus_top\n             obj_dir/bus_top.v\n             obj_dir/bus_top.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module tf520r3_bus_top(

           input 	CLKCPU,
           input 	CLK7M,

           output   RESET,
           output   HALT, 
           output   HIGH,

           input 	BG20,
           input 	AS20,
           input 	DS20,
           input 	RW20,
           output 	RW,

           input [2:0] 	FC,
           input [1:0] 	SIZ,

           input [23:0] A,

           inout 	BGACK,
           input 	VPA,
           input 	DTACK,

           output 	BG,
           output 	LDS,
           output 	UDS,
           output 	VMA,
           output 	E,
           output 	AS,
           output 	BERR,

           output   DSACK1,
           output 	AVEC

          
       );

wire CPSENSE = 1'b1;
wire INTCYCLE = 1'b1;
wire SLOWCYCLE = 1'b1;
wire IDEWAIT = 1'b1;
wire INT2 = 1'b1;

wire [23:0] ADDRESS_MAP;

assign ADDRESS_MAP[0] = A[0];
assign ADDRESS_MAP[19:16] = {A[19:16]};

bus_top BUSTOP(

    .CLKCPU     ( CLKCPU        ), 
    .CLK7M      ( CLK7M         ),

    .INTCYCLE   ( INTCYCLE      ),
    .SLOWCYCLE  ( SLOWCYCLE     ),
    .IDEWAIT    ( IDEWAIT       ),
    .CPSENSE    ( CPSENSE       ), 

    .BG20       ( BG20          ),
    .BG         ( BG            ),
    .BGACK      ( BGACK         ),

    .AS20       ( AS20          ), 
    .DS20       ( DS20          ), 
    .RW20       ( RW20          ), 
    .DSACK1     ( DSACK1        ), 
    .AVEC       ( AVEC          ),

    .AS         ( AS            ), 
    .RW         ( RW            ),
    .LDS        ( LDS           ), 
    .UDS        ( UDS           ), 
    .FC         ( FC            ), 

    .INT2       ( INT2          ),
    .SIZ        ( SIZ           ),

    .A          ( ADDRESS_MAP   ), 
	       
    .VPA        ( VPA           ), 
    .DTACK      ( DTACK         ), 

    .VMA        ( VMA           ), 
    .E          ( E             ), 
    .BERR       ( BERR          ) 
);


assign RESET = 1'bz;
assign HALT = 1'bz;
assign HIGH = 1'b1;

endmodule
module tf520r3_bus_top(

           input 	CLKCPU,
           input 	CLK7M,

           output   RESET,
           output   HALT, 
           output   HIGH,

           input 	BG20,
           input 	AS20,
           input 	DS20,
           input 	RW20,
           output 	RW,

           input [2:0] 	FC,
           input [1:0] 	SIZ,

           input [23:0] A,

           inout 	BGACK,
           input 	VPA,
           input 	DTACK,

           output 	BG,
           output 	LDS,
           output 	UDS,
           output 	VMA,
           output 	E,
           output 	AS,
           output 	BERR,

           output   DSACK1,
           output 	AVEC

          
       );


wire CPSENSE = 1'b1;
wire INTCYCLE = 1'b1;
wire SLOWCYCLE = 1'b1;
wire IDEWAIT = 1'b1;
wire INT2 = 1'b1;

wire [23:0] ADDRESS_MAP;

assign ADDRESS_MAP[0] = A[0];
assign ADDRESS_MAP[19:16] = {A[19:16]};

bus_top BUSTOP(

    .CLKCPU     ( CLKCPU        ), 
    .CLK7M      ( CLK7M         ),

    .INTCYCLE   ( INTCYCLE      ),
    .SLOWCYCLE  ( SLOWCYCLE     ),
    .IDEWAIT    ( IDEWAIT       ),
    .CPSENSE    ( CPSENSE       ), 

    .BG20       ( BG20          ),
    .BG         ( BG            ),
    .BGACK      ( BGACK         ),

    .AS20       ( AS20          ), 
    .DS20       ( DS20          ), 
    .RW20       ( RW20          ), 
    .DSACK1     ( DSACK1        ), 
    .AVEC       ( AVEC          ),

    .AS         ( AS            ), 
    .RW         ( RW            ),
    .LDS        ( LDS           ), 
    .UDS        ( UDS           ), 
    .FC         ( FC            ), 

    .INT2       ( INT2          ),
    .SIZ        ( SIZ           ),

    .A          ( ADDRESS_MAP   ), 
	       
    .VPA        ( VPA           ), 
    .DTACK      ( DTACK         ), 

    .VMA        ( VMA           ), 
    .E          ( E             ), 
    .BERR       ( BERR          ) 
);


assign RESET = 1'bz;
assign HALT = 1'bz;
assign HIGH = 1'b1;

endmodule