data/full_repos/permissive/181738725/wavetrace/verilog/apb_master.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/apb_master.v:53: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module apb_master
(
  input             clk,
  input             rst,

  input             din_valid,
  output reg        din_ready,
  input [31:0]      din_data,

  output reg        dout_valid,
  output reg [31:0] dout_data,
  input             dout_ready,

  output reg [31:0] mst_paddr,
  output reg        mst_pwrite,
  output reg [31:0] mst_pwdata,
  output reg        mst_psel,
  output reg        mst_penable,
  input             mst_pready,
  input [31:0]      mst_prdata,
  input             mst_pslverr
  );

`include "util.vh"




  localparam Idle      = 0,
             WrAddr    = 1,
             WrData    = 2,
             WrEn      = 3,
             WrWait    = 4,
             RdAddr    = 5,
             RdEn      = 6,
             RdWait    = 7,
             RdData    = 8,
             NumStates = 9;

  localparam WrCmd  = 32'hABCDA000;
  localparam RdCmd  = 32'hABCDB001;

  reg [clog2(NumStates)-1:0] state;
  reg [7:0]                  burst_remain;

  always @(posedge clk) begin

    case (state)

      Idle:
        if (din_valid & din_ready) begin
          if (din_data == WrCmd) begin
            state <= WrAddr;
          end else if (din_data[31:8] == RdCmd[31:8] && din_data[7:0] > 0) begin
            state        <= RdAddr;
            burst_remain <= din_data[7:0];
          end
        end

      WrAddr:
        if (din_valid & din_ready) begin
          mst_paddr <= din_data;
          state     <= WrData;
        end

      WrData:
        if (din_valid & din_ready) begin
          mst_pwdata <= din_data;
          mst_pwrite <= 1;
          mst_psel   <= 1;
          din_ready  <= 0;
          state      <= WrEn;
        end

      WrEn:
        begin
          mst_penable <= 1;
          state       <= WrWait;
        end

      WrWait:
        if (mst_pready) begin
          mst_penable <= 0;
          mst_psel    <= 0;
          din_ready   <= 1;
          state       <= Idle;
        end

      RdAddr:
        if (din_valid & din_ready) begin
          mst_paddr  <= din_data;
          mst_pwrite <= 0;
          mst_psel   <= 1;
          din_ready  <= 0;
          state      <= RdEn;
        end

      RdEn:
        begin
          mst_penable <= 1;
          state       <= RdWait;
        end

      RdWait:
        if (mst_pready) begin
          mst_penable  <= 0;
          mst_psel     <= 0;
          dout_data    <= mst_prdata;
          dout_valid   <= 1;
          state        <= RdData;
          burst_remain <= burst_remain - 1;
        end

      RdData:
        if (dout_ready) begin
          dout_valid <= 0;
          if (burst_remain == 0) begin
            din_ready <= 1;
            state     <= Idle;
          end else begin
            mst_paddr <= mst_paddr + 4;
            mst_psel  <= 1;
            state     <= RdEn;
          end
        end
    endcase

    if (rst) begin
      state       <= Idle;
      din_ready   <= 1;
      dout_valid  <= 0;
      mst_pwrite  <= 0;
      mst_psel    <= 0;
      mst_penable <= 0;
    end
  end

endmodule
module apb_master
(
  input             clk,
  input             rst,

  input             din_valid,
  output reg        din_ready,
  input [31:0]      din_data,

  output reg        dout_valid,
  output reg [31:0] dout_data,
  input             dout_ready,

  output reg [31:0] mst_paddr,
  output reg        mst_pwrite,
  output reg [31:0] mst_pwdata,
  output reg        mst_psel,
  output reg        mst_penable,
  input             mst_pready,
  input [31:0]      mst_prdata,
  input             mst_pslverr
  );


`include "util.vh"




  localparam Idle      = 0,
             WrAddr    = 1,
             WrData    = 2,
             WrEn      = 3,
             WrWait    = 4,
             RdAddr    = 5,
             RdEn      = 6,
             RdWait    = 7,
             RdData    = 8,
             NumStates = 9;

  localparam WrCmd  = 32'hABCDA000;
  localparam RdCmd  = 32'hABCDB001;

  reg [clog2(NumStates)-1:0] state;
  reg [7:0]                  burst_remain;

  always @(posedge clk) begin

    case (state)

      Idle:
        if (din_valid & din_ready) begin
          if (din_data == WrCmd) begin
            state <= WrAddr;
          end else if (din_data[31:8] == RdCmd[31:8] && din_data[7:0] > 0) begin
            state        <= RdAddr;
            burst_remain <= din_data[7:0];
          end
        end

      WrAddr:
        if (din_valid & din_ready) begin
          mst_paddr <= din_data;
          state     <= WrData;
        end

      WrData:
        if (din_valid & din_ready) begin
          mst_pwdata <= din_data;
          mst_pwrite <= 1;
          mst_psel   <= 1;
          din_ready  <= 0;
          state      <= WrEn;
        end

      WrEn:
        begin
          mst_penable <= 1;
          state       <= WrWait;
        end

      WrWait:
        if (mst_pready) begin
          mst_penable <= 0;
          mst_psel    <= 0;
          din_ready   <= 1;
          state       <= Idle;
        end

      RdAddr:
        if (din_valid & din_ready) begin
          mst_paddr  <= din_data;
          mst_pwrite <= 0;
          mst_psel   <= 1;
          din_ready  <= 0;
          state      <= RdEn;
        end

      RdEn:
        begin
          mst_penable <= 1;
          state       <= RdWait;
        end

      RdWait:
        if (mst_pready) begin
          mst_penable  <= 0;
          mst_psel     <= 0;
          dout_data    <= mst_prdata;
          dout_valid   <= 1;
          state        <= RdData;
          burst_remain <= burst_remain - 1;
        end

      RdData:
        if (dout_ready) begin
          dout_valid <= 0;
          if (burst_remain == 0) begin
            din_ready <= 1;
            state     <= Idle;
          end else begin
            mst_paddr <= mst_paddr + 4;
            mst_psel  <= 1;
            state     <= RdEn;
          end
        end
    endcase

    if (rst) begin
      state       <= Idle;
      din_ready   <= 1;
      dout_valid  <= 0;
      mst_pwrite  <= 0;
      mst_psel    <= 0;
      mst_penable <= 0;
    end
  end

endmodule