data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v:32: Little bit endian vector: MSB < LSB of bit range: 0:9\n input[0:9] waddr,\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v:33: Little bit endian vector: MSB < LSB of bit range: 0:31\n input[0:31] data_in,\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v:36: Little bit endian vector: MSB < LSB of bit range: 0:9\n input[0:9] raddr,\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v:37: Little bit endian vector: MSB < LSB of bit range: 0:31\n output[0:31] d_out );\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v:39: Little bit endian vector: MSB < LSB of bit range: 0:31\n reg[0:31] ram[0:1023];\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v:40: Little bit endian vector: MSB < LSB of bit range: 0:31\n reg[0:31] internal;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v:12: Little bit endian vector: MSB < LSB of bit range: 0:9\n input[0:9] waddr,\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v:13: Little bit endian vector: MSB < LSB of bit range: 0:9\n input[0:9] raddr,\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v:14: Little bit endian vector: MSB < LSB of bit range: 0:31\n input[0:31] d_in,\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v:15: Little bit endian vector: MSB < LSB of bit range: 0:31\n output[0:31] d_out );\n       ^\n%Error: Exiting due to 10 warning(s)\n'
module dpram_512x32 (
	input clk,
	input wen,
	input ren,
	input[0:9] waddr,
	input[0:9] raddr,
	input[0:31] d_in,
	output[0:31] d_out );

		dual_port_sram memory_0 (
			.wclk		(clk),
			.wen		(wen),
			.waddr		(waddr),
			.data_in	(d_in),
			.rclk		(clk),
			.ren		(ren),
			.raddr		(raddr),
			.d_out		(d_out) );

endmodule
module dpram_512x32 (
	input clk,
	input wen,
	input ren,
	input[0:9] waddr,
	input[0:9] raddr,
	input[0:31] d_in,
	output[0:31] d_out );


		dual_port_sram memory_0 (
			.wclk		(clk),
			.wen		(wen),
			.waddr		(waddr),
			.data_in	(d_in),
			.rclk		(clk),
			.ren		(ren),
			.raddr		(raddr),
			.d_out		(d_out) );

endmodule