data/full_repos/permissive/18477150/lib/sonic/xcvr_xg/sonic_v1_15/synthesis/submodules/sonic_v1_15_pcs_eth_10g_mac_tx_st_timing_adapter_splitter_status_output.v
data/verilator_xmls/9ca85de9-6f03-4f5b-8e5d-df24658507fc.xml
module sonic_v1_15_pcs_eth_10g_mac_tx_st_timing_adapter_splitter_status_output (
    

      input              clk,

      input              reset_n,

      output reg         in_ready,
      input              in_valid,
      input      [39: 0] in_data,
      input      [ 6: 0] in_error,

      output reg         out_valid,
      output reg [39: 0] out_data,
      output reg [ 6: 0] out_error
);








   reg  [46: 0] in_payload;
   reg  [46: 0] out_payload;
   reg  [ 0: 0] ready;
   reg          out_ready = 1;





   always @* begin
     in_payload = {in_data,in_error};
     {out_data,out_error} = out_payload;
   end




   always @* begin
     ready[0] = out_ready;
     out_valid = in_valid;
     out_payload = in_payload;
     in_ready = ready[0];
   end




endmodule
module sonic_v1_15_pcs_eth_10g_mac_tx_st_timing_adapter_splitter_status_output (
    

      input              clk,

      input              reset_n,

      output reg         in_ready,
      input              in_valid,
      input      [39: 0] in_data,
      input      [ 6: 0] in_error,

      output reg         out_valid,
      output reg [39: 0] out_data,
      output reg [ 6: 0] out_error
);









   reg  [46: 0] in_payload;
   reg  [46: 0] out_payload;
   reg  [ 0: 0] ready;
   reg          out_ready = 1;





   always @* begin
     in_payload = {in_data,in_error};
     {out_data,out_error} = out_payload;
   end




   always @* begin
     ready[0] = out_ready;
     out_valid = in_valid;
     out_payload = in_payload;
     in_ready = ready[0];
   end




endmodule