data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sim_1/new/assembly.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sim_1/new/assembly.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2) Clk = 1\'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sim_1/new/assembly.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sim_1/new/assembly.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #180\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sim_1/new/assembly.v:49: Unsupported: Ignoring delay on this delayed statement.\n       #10000; \n       ^\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sim_1/new/assembly.v:28: Cannot find file containing module: \'Top\'\n    Top u(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sim_1/new,data/full_repos/permissive/194376374/Top\n             data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sim_1/new,data/full_repos/permissive/194376374/Top.v\n             data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sim_1/new,data/full_repos/permissive/194376374/Top.sv\n             Top\n             Top.v\n             Top.sv\n             obj_dir/Top\n             obj_dir/Top.v\n             obj_dir/Top.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module assembly( );

    reg Clk;
    reg reset;

    Top u(
    .Clk(Clk),
    .reset(reset)

    );
    
    parameter PERIOD = 50;

    always begin
        Clk = 1'b0;
        #(PERIOD/2) Clk = 1'b1;
        #(PERIOD/2);
    end
    
    initial begin


    reset<=1;
    #180

       reset <= 0;
       #10000; 
    end
endmodule
module assembly( );


    reg Clk;
    reg reset;

    Top u(
    .Clk(Clk),
    .reset(reset)

    );
    
    parameter PERIOD = 50;

    always begin
        Clk = 1'b0;
        #(PERIOD/2) Clk = 1'b1;
        #(PERIOD/2);
    end
    
    initial begin


    reset<=1;
    #180

       reset <= 0;
       #10000; 
    end
endmodule