data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v:1: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.sv\n             cmos_cells.v\n             cmos_cells.v.v\n             cmos_cells.v.sv\n             obj_dir/cmos_cells.v\n             obj_dir/cmos_cells.v.v\n             obj_dir/cmos_cells.v.sv\n%Error: Exiting due to 1 error(s)\n'
module p2s_s2p_synth(IN_CLK_2MHz, IN_CLK_250KHz, IN_LANE3, IN_LANE2, IN_LANE1, IN_LANE0, IN_ENB_TX, IN_RESET_TX, IN_VALID_TX, IN_ENB_RX, IN_RESET_RX, OUT_LANE3, OUT_LANE2, OUT_LANE1, OUT_LANE0);
  wire [1:0] CLK_RX;
  wire [2:0] CTR_TX;
  input IN_CLK_250KHz;
  input IN_CLK_2MHz;
  input IN_ENB_RX;
  input IN_ENB_TX;
  input [7:0] IN_LANE0;
  input [7:0] IN_LANE1;
  input [7:0] IN_LANE2;
  input [7:0] IN_LANE3;
  input IN_RESET_RX;
  input IN_RESET_TX;
  input IN_VALID_TX;
  wire [3:0] LANE;
  output [7:0] OUT_LANE0;
  output [7:0] OUT_LANE1;
  output [7:0] OUT_LANE2;
  output [7:0] OUT_LANE3;
  mux_ctr_synth ctr_tx_cond (
    .CLK(IN_CLK_2MHz),
    .CTR(CTR_TX),
    .reset(IN_RESET_TX),
    .valid_count(IN_VALID_TX)
  );
  s2p_synth low_rx_cond (
    .IN_CLK_s2p({ IN_CLK_250KHz, IN_CLK_2MHz }),
    .IN_DIR_s2p(1'b1),
    .IN_ENB_s2p(IN_ENB_RX),
    .IN_LANE_s2p(LANE),
    .IN_MODO_s2p(2'b00),
    .OUT_LANE0_s2p(OUT_LANE0),
    .OUT_LANE1_s2p(OUT_LANE1),
    .OUT_LANE2_s2p(OUT_LANE2),
    .OUT_LANE3_s2p(OUT_LANE3)
  );
  p2s_synth low_tx_cond (
    .IN_CLK_p2s(IN_CLK_2MHz),
    .IN_CTR_p2s(CTR_TX),
    .IN_ENB_p2s(IN_ENB_TX),
    .IN_LANE0_p2s(IN_LANE0),
    .IN_LANE1_p2s(IN_LANE1),
    .IN_LANE2_p2s(IN_LANE2),
    .IN_LANE3_p2s(IN_LANE3),
    .IN_RESET_p2s(IN_RESET_TX),
    .IN_VALID_BS(IN_VALID_TX),
    .OUT_LANE_p2s(LANE)
  );
  assign CLK_RX = { IN_CLK_250KHz, IN_CLK_2MHz };
endmodule
module p2s_s2p_synth(IN_CLK_2MHz, IN_CLK_250KHz, IN_LANE3, IN_LANE2, IN_LANE1, IN_LANE0, IN_ENB_TX, IN_RESET_TX, IN_VALID_TX, IN_ENB_RX, IN_RESET_RX, OUT_LANE3, OUT_LANE2, OUT_LANE1, OUT_LANE0);

  wire [1:0] CLK_RX;
  wire [2:0] CTR_TX;
  input IN_CLK_250KHz;
  input IN_CLK_2MHz;
  input IN_ENB_RX;
  input IN_ENB_TX;
  input [7:0] IN_LANE0;
  input [7:0] IN_LANE1;
  input [7:0] IN_LANE2;
  input [7:0] IN_LANE3;
  input IN_RESET_RX;
  input IN_RESET_TX;
  input IN_VALID_TX;
  wire [3:0] LANE;
  output [7:0] OUT_LANE0;
  output [7:0] OUT_LANE1;
  output [7:0] OUT_LANE2;
  output [7:0] OUT_LANE3;
  mux_ctr_synth ctr_tx_cond (
    .CLK(IN_CLK_2MHz),
    .CTR(CTR_TX),
    .reset(IN_RESET_TX),
    .valid_count(IN_VALID_TX)
  );
  s2p_synth low_rx_cond (
    .IN_CLK_s2p({ IN_CLK_250KHz, IN_CLK_2MHz }),
    .IN_DIR_s2p(1'b1),
    .IN_ENB_s2p(IN_ENB_RX),
    .IN_LANE_s2p(LANE),
    .IN_MODO_s2p(2'b00),
    .OUT_LANE0_s2p(OUT_LANE0),
    .OUT_LANE1_s2p(OUT_LANE1),
    .OUT_LANE2_s2p(OUT_LANE2),
    .OUT_LANE3_s2p(OUT_LANE3)
  );
  p2s_synth low_tx_cond (
    .IN_CLK_p2s(IN_CLK_2MHz),
    .IN_CTR_p2s(CTR_TX),
    .IN_ENB_p2s(IN_ENB_TX),
    .IN_LANE0_p2s(IN_LANE0),
    .IN_LANE1_p2s(IN_LANE1),
    .IN_LANE2_p2s(IN_LANE2),
    .IN_LANE3_p2s(IN_LANE3),
    .IN_RESET_p2s(IN_RESET_TX),
    .IN_VALID_BS(IN_VALID_TX),
    .OUT_LANE_p2s(LANE)
  );
  assign CLK_RX = { IN_CLK_250KHz, IN_CLK_2MHz };
endmodule