data/full_repos/permissive/143278/vhdl_tests/pr2555813b.v
data/verilator_xmls/ca9c6fc8-9d15-4c0e-ad43-86d09f6911fc.xml
module a__a(b_buf, b);
output b_buf;
input b;
endmodule
module a__a(b_buf, b);

output b_buf;
input b;
endmodule