data/full_repos/permissive/170402453/ShiftRegisterParallel.v
data/verilator_xmls/b36104a8-0b74-4460-89c4-d13d6bf92cd2.xml
module SerialReceiver(
    input CLK,
    input SerialIN,
    output [9:0] ParallelOUT
    );


endmodule
module SerialReceiver(
    input CLK,
    input SerialIN,
    output [9:0] ParallelOUT
    );



endmodule