data/full_repos/permissive/165490876/src/synth/EG.v
1: b'%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:35: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[0] = $rtoi((1000 * 2) / CLOCK_FREQ);\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:36: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[1] = $rtoi((1000 * 8) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:37: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[2] = $rtoi((1000 * 16) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:38: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[3] = $rtoi((1000 * 24) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:39: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[4] = $rtoi((1000 * 38) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:40: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[5] = $rtoi((1000 * 56) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:41: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[6] = $rtoi((1000 * 68) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:42: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[7] = $rtoi((1000 * 80) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:43: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[8] = $rtoi((1000 * 100) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:44: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[9] = $rtoi((1000 * 250) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:45: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[10] = $rtoi((1000 * 500) / CLOCK_FREQ);\n            ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:46: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[11] = $rtoi((1000 * 800) / CLOCK_FREQ);\n            ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:47: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[12] = $rtoi((1000 * 1000) / CLOCK_FREQ);\n            ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:48: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[13] = $rtoi((1000 * 3000) / CLOCK_FREQ);\n            ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:49: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[14] = $rtoi((1000 * 5000) / CLOCK_FREQ);\n            ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:50: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  adLut[15] = $rtoi((1000 * 8000) / CLOCK_FREQ); \n            ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:53: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[0] = $rtoi((1000 * 6) / CLOCK_FREQ);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:54: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[1] = $rtoi((1000 * 24) / CLOCK_FREQ);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:55: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[2] = $rtoi((1000 * 48) / CLOCK_FREQ);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:56: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[3] = $rtoi((1000 * 72) / CLOCK_FREQ);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:57: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[4] = $rtoi((1000 * 114) / CLOCK_FREQ);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:58: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[5] = $rtoi((1000 * 168) / CLOCK_FREQ);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:59: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[6] = $rtoi((1000 * 204) / CLOCK_FREQ);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:60: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[7] = $rtoi((1000 * 240) / CLOCK_FREQ);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:61: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[8] = $rtoi((1000 * 300) / CLOCK_FREQ);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:62: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[9] = $rtoi((1000 * 750) / CLOCK_FREQ);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:63: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[10] = $rtoi((1000 * 1500) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:64: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[11] = $rtoi((1000 * 2400) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:65: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[12] = $rtoi((1000 * 3000) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:66: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[13] = $rtoi((1000 * 9000) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:67: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[14] = $rtoi((1000 * 15000) / CLOCK_FREQ);\n           ^\n%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/EG.v:68: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RTOIS generates 32 bits.\n                                                                      : ... In instance EG\n  rLut[15] = $rtoi((1000 * 24000) / CLOCK_FREQ);\n           ^\n%Error: Exiting due to 32 warning(s)\n'
module EG #(parameter CLOCK_FREQ = 2080000) (
  input clock,	
  input gate,
  input ask,  
  input [7:0] ad,  
  input [7:0] sr,  
  input [7:0] askab,  
  output [3:0] out
);
	reg [7:0] adLut[0:31];
    reg [7:0] rLut[0:31];
	
    `define clockCyclesForDelay(delaymS) $rtoi((1000 * delaymS) / CLOCK_FREQ)
  
	initial begin
		adLut[0] = `clockCyclesForDelay(2);
		adLut[1] = `clockCyclesForDelay(8);
		adLut[2] = `clockCyclesForDelay(16);
		adLut[3] = `clockCyclesForDelay(24);
		adLut[4] = `clockCyclesForDelay(38);
		adLut[5] = `clockCyclesForDelay(56);
		adLut[6] = `clockCyclesForDelay(68);
		adLut[7] = `clockCyclesForDelay(80);
		adLut[8] = `clockCyclesForDelay(100);
		adLut[9] = `clockCyclesForDelay(250);
		adLut[10] = `clockCyclesForDelay(500);
		adLut[11] = `clockCyclesForDelay(800);
		adLut[12] = `clockCyclesForDelay(1000);
		adLut[13] = `clockCyclesForDelay(3000);
		adLut[14] = `clockCyclesForDelay(5000);
		adLut[15] = `clockCyclesForDelay(8000);	
	end

	initial begin
		rLut[0] = `clockCyclesForDelay(6);
		rLut[1] = `clockCyclesForDelay(24);
		rLut[2] = `clockCyclesForDelay(48);
		rLut[3] = `clockCyclesForDelay(72);
		rLut[4] = `clockCyclesForDelay(114);
		rLut[5] = `clockCyclesForDelay(168);
		rLut[6] = `clockCyclesForDelay(204);
		rLut[7] = `clockCyclesForDelay(240);
		rLut[8] = `clockCyclesForDelay(300);
		rLut[9] = `clockCyclesForDelay(750);
		rLut[10] = `clockCyclesForDelay(1500);
		rLut[11] = `clockCyclesForDelay(2400);
		rLut[12] = `clockCyclesForDelay(3000);
		rLut[13] = `clockCyclesForDelay(9000);
		rLut[14] = `clockCyclesForDelay(15000);
		rLut[15] = `clockCyclesForDelay(24000);
	end
				
endmodule
module EG #(parameter CLOCK_FREQ = 2080000) (
  input clock,	
  input gate,
  input ask,  
  input [7:0] ad,  
  input [7:0] sr,  
  input [7:0] askab,  
  output [3:0] out
);

	reg [7:0] adLut[0:31];
    reg [7:0] rLut[0:31];
	
    `define clockCyclesForDelay(delaymS) $rtoi((1000 * delaymS) / CLOCK_FREQ)
  
	initial begin
		adLut[0] = `clockCyclesForDelay(2);
		adLut[1] = `clockCyclesForDelay(8);
		adLut[2] = `clockCyclesForDelay(16);
		adLut[3] = `clockCyclesForDelay(24);
		adLut[4] = `clockCyclesForDelay(38);
		adLut[5] = `clockCyclesForDelay(56);
		adLut[6] = `clockCyclesForDelay(68);
		adLut[7] = `clockCyclesForDelay(80);
		adLut[8] = `clockCyclesForDelay(100);
		adLut[9] = `clockCyclesForDelay(250);
		adLut[10] = `clockCyclesForDelay(500);
		adLut[11] = `clockCyclesForDelay(800);
		adLut[12] = `clockCyclesForDelay(1000);
		adLut[13] = `clockCyclesForDelay(3000);
		adLut[14] = `clockCyclesForDelay(5000);
		adLut[15] = `clockCyclesForDelay(8000);	
	end

	initial begin
		rLut[0] = `clockCyclesForDelay(6);
		rLut[1] = `clockCyclesForDelay(24);
		rLut[2] = `clockCyclesForDelay(48);
		rLut[3] = `clockCyclesForDelay(72);
		rLut[4] = `clockCyclesForDelay(114);
		rLut[5] = `clockCyclesForDelay(168);
		rLut[6] = `clockCyclesForDelay(204);
		rLut[7] = `clockCyclesForDelay(240);
		rLut[8] = `clockCyclesForDelay(300);
		rLut[9] = `clockCyclesForDelay(750);
		rLut[10] = `clockCyclesForDelay(1500);
		rLut[11] = `clockCyclesForDelay(2400);
		rLut[12] = `clockCyclesForDelay(3000);
		rLut[13] = `clockCyclesForDelay(9000);
		rLut[14] = `clockCyclesForDelay(15000);
		rLut[15] = `clockCyclesForDelay(24000);
	end
				
endmodule