data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:23: Define or directive not defined: \'`ADDR_W\'\n  parameter [`ADDR_W - 1:0] ADDR_START = 0;\n             ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:30: Define or directive not defined: \'`WORD_W\'\n  localparam ADDR_COUNT = WORD_COUNT * `WORD_W / 8;\n                                       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:30: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n  localparam ADDR_COUNT = WORD_COUNT * `WORD_W / 8;\n                                               ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:31: Define or directive not defined: \'`ADDR_W\'\n  localparam [`ADDR_W - 1:0] ADDR_END = ADDR_START + ADDR_COUNT - 1;\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:32: Define or directive not defined: \'`ADDR_W\'\n  localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:32: Define or directive not defined: \'`ADDR_W\'\n  localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];\n                                                         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:33: Define or directive not defined: \'`ADDR_W\'\n  localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:33: Define or directive not defined: \'`ADDR_W\'\n  localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];\n                                                     ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:42: Define or directive not defined: \'`ADDR_W\'\n  input [`ADDR_W - 1:0] i_req_addr;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:43: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_req_wr_data;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:45: Define or directive not defined: \'`MEM_COUNT_W\'\n  input [`MEM_COUNT_W - 1:0] i_req_count;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:51: Define or directive not defined: \'`WORD_W\'\n  output reg [`WORD_W - 1:0] o_res_rd_data;\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:52: Define or directive not defined: \'`MEM_CODE_W\'\n  output reg [`MEM_CODE_W - 1:0] o_res_code;\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:53: Define or directive not defined: \'`WORD_W\'\n  output [`WORD_W * WORD_COUNT - 1:0] o_exposed_mem;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:53: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n  output [`WORD_W * WORD_COUNT - 1:0] o_exposed_mem;\n                  ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:56: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 2 - 1:0] s_addr_aligned = i_req_addr[`WORD_W - 1:2];\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:56: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 2 - 1:0] s_addr_aligned = i_req_addr[`WORD_W - 1:2];\n                                                       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:61: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] r_mem [WORD_END:WORD_START];\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:70: Define or directive not defined: \'`WORD_W\'\n      assign o_exposed_mem[`WORD_W * (j + 1) - 1:`WORD_W * j] = r_mem[j + WORD_START];\n                           ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:70: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n      assign o_exposed_mem[`WORD_W * (j + 1) - 1:`WORD_W * j] = r_mem[j + WORD_START];\n                                   ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:70: Define or directive not defined: \'`WORD_W\'\n      assign o_exposed_mem[`WORD_W * (j + 1) - 1:`WORD_W * j] = r_mem[j + WORD_START];\n                                                 ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:90: Define or directive not defined: \'`MEM_COUNT_NONE\'\n    end else if(i_req_count != `MEM_COUNT_NONE) begin\n                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:90: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    end else if(i_req_count != `MEM_COUNT_NONE) begin\n                                              ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:92: Define or directive not defined: \'`MEM_COUNT_HALF\'\n      if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||\n                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:93: Define or directive not defined: \'`MEM_COUNT_WORD\'\n        (i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin\n                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:96: Define or directive not defined: \'`MEM_CODE_MISALIGNED\'\n        o_res_code <= `MEM_CODE_MISALIGNED;\n                      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        o_res_code <= `MEM_CODE_MISALIGNED;\n                                          ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:101: Define or directive not defined: \'`MEM_CODE_OUT_OF_BOUNDS\'\n        o_res_code <= `MEM_CODE_OUT_OF_BOUNDS;\n                      ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:107: Define or directive not defined: \'`MEM_CODE_WRITE\'\n        o_res_code <= `MEM_CODE_WRITE;\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:111: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n          `MEM_COUNT_BYTE:\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:111: syntax error, unexpected \':\', expecting endcase\n          `MEM_COUNT_BYTE:\n                         ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:119: Define or directive not defined: \'`MEM_COUNT_HALF\'\n          `MEM_COUNT_HALF:\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:125: Define or directive not defined: \'`MEM_COUNT_WORD\'\n          `MEM_COUNT_WORD: r_mem[s_addr_aligned] <= i_req_wr_data;\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:127: Define or directive not defined: \'`MEM_CODE_INVALID\'\n          default: o_res_code <= `MEM_CODE_INVALID;\n                                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:134: Define or directive not defined: \'`MEM_CODE_READ\'\n        o_res_code <= `MEM_CODE_READ;\n                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:138: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n          `MEM_COUNT_BYTE:\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:138: syntax error, unexpected \':\', expecting endcase\n          `MEM_COUNT_BYTE:\n                         ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:146: Define or directive not defined: \'`MEM_COUNT_HALF\'\n          `MEM_COUNT_HALF:\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:152: Define or directive not defined: \'`MEM_COUNT_WORD\'\n          `MEM_COUNT_WORD: o_res_rd_data <= r_mem[s_addr_aligned];\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:154: Define or directive not defined: \'`MEM_CODE_INVALID\'\n          default: o_res_code <= `MEM_CODE_INVALID;\n                                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/readwrite_registers.v:162: Define or directive not defined: \'`MEM_CODE_INVALID\'\n      o_res_code <= `MEM_CODE_INVALID;\n                    ^~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module readwrite_registers(
  clk,
  aresetn,

  i_req_addr,
  i_req_wr_data,
  i_req_wr_en,
  i_req_count,

  o_res_rd_data,
  o_res_code,

  o_exposed_mem
);



  parameter [`ADDR_W - 1:0] ADDR_START = 0;
  parameter WORD_COUNT = 1;





  localparam ADDR_COUNT = WORD_COUNT * `WORD_W / 8;
  localparam [`ADDR_W - 1:0] ADDR_END = ADDR_START + ADDR_COUNT - 1;
  localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];
  localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];





  input clk;
  input aresetn;

  input [`ADDR_W - 1:0] i_req_addr;
  input [`WORD_W - 1:0] i_req_wr_data;
  input i_req_wr_en;
  input [`MEM_COUNT_W - 1:0] i_req_count;





  output reg [`WORD_W - 1:0] o_res_rd_data;
  output reg [`MEM_CODE_W - 1:0] o_res_code;
  output [`WORD_W * WORD_COUNT - 1:0] o_exposed_mem;


  wire [`WORD_W - 2 - 1:0] s_addr_aligned = i_req_addr[`WORD_W - 1:2];

  wire [1:0] s_offset = i_req_addr[1:0];


  reg [`WORD_W - 1:0] r_mem [WORD_END:WORD_START];





  genvar j;
  generate
    for(j = 0; j < WORD_COUNT; j = j + 1) begin: mem_assign
      assign o_exposed_mem[`WORD_W * (j + 1) - 1:`WORD_W * j] = r_mem[j + WORD_START];
    end
  endgenerate





  integer i;
  always@(posedge clk, negedge aresetn) begin
    if(aresetn == 0) begin

      for(i = 0; i < ADDR_COUNT; i = i + 1) begin
        r_mem[i] <= 0;
      end

      o_res_rd_data <= 0;
      o_res_code <= 0;


    end else if(i_req_count != `MEM_COUNT_NONE) begin

      if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||
        (i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin

        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_MISALIGNED;


      end else if(s_addr_aligned > ADDR_END) begin
        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_OUT_OF_BOUNDS;


      end else if(i_req_wr_en == 1) begin

        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_WRITE;


        case(i_req_count)
          `MEM_COUNT_BYTE:
            case(s_offset)
              0: r_mem[s_addr_aligned][7:0] <= i_req_wr_data[7:0];
              1: r_mem[s_addr_aligned][15:8] <= i_req_wr_data[7:0];
              2: r_mem[s_addr_aligned][23:16] <= i_req_wr_data[7:0];
              3: r_mem[s_addr_aligned][31:24] <= i_req_wr_data[7:0];
            endcase

          `MEM_COUNT_HALF:
            case(s_offset)
              0: r_mem[s_addr_aligned][15:0] <= i_req_wr_data[15:0];
              2: r_mem[s_addr_aligned][31:16] <= i_req_wr_data[15:0];
            endcase

          `MEM_COUNT_WORD: r_mem[s_addr_aligned] <= i_req_wr_data;

          default: o_res_code <= `MEM_CODE_INVALID;
        endcase

      end else begin


        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_READ;


        case(i_req_count)
          `MEM_COUNT_BYTE:
            case(s_offset)
              0: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][7:0];
              1: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][15:8];
              2: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][23:16];
              3: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][31:24];
            endcase

          `MEM_COUNT_HALF:
            case(s_offset)
              0: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][15:0];
              2: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][31:16];
            endcase

          `MEM_COUNT_WORD: o_res_rd_data <= r_mem[s_addr_aligned];

          default: o_res_code <= `MEM_CODE_INVALID;
        endcase

      end

    end else begin

      o_res_rd_data <= 0;
      o_res_code <= `MEM_CODE_INVALID;

    end
  end
endmodule
module readwrite_registers(
  clk,
  aresetn,

  i_req_addr,
  i_req_wr_data,
  i_req_wr_en,
  i_req_count,

  o_res_rd_data,
  o_res_code,

  o_exposed_mem
);




  parameter [`ADDR_W - 1:0] ADDR_START = 0;
  parameter WORD_COUNT = 1;





  localparam ADDR_COUNT = WORD_COUNT * `WORD_W / 8;
  localparam [`ADDR_W - 1:0] ADDR_END = ADDR_START + ADDR_COUNT - 1;
  localparam [`ADDR_W - 2 - 1:0] WORD_START = ADDR_START[`ADDR_W - 1:2];
  localparam [`ADDR_W - 2 - 1:0] WORD_END = ADDR_END[`ADDR_W - 1:2];





  input clk;
  input aresetn;

  input [`ADDR_W - 1:0] i_req_addr;
  input [`WORD_W - 1:0] i_req_wr_data;
  input i_req_wr_en;
  input [`MEM_COUNT_W - 1:0] i_req_count;





  output reg [`WORD_W - 1:0] o_res_rd_data;
  output reg [`MEM_CODE_W - 1:0] o_res_code;
  output [`WORD_W * WORD_COUNT - 1:0] o_exposed_mem;


  wire [`WORD_W - 2 - 1:0] s_addr_aligned = i_req_addr[`WORD_W - 1:2];

  wire [1:0] s_offset = i_req_addr[1:0];


  reg [`WORD_W - 1:0] r_mem [WORD_END:WORD_START];





  genvar j;
  generate
    for(j = 0; j < WORD_COUNT; j = j + 1) begin: mem_assign
      assign o_exposed_mem[`WORD_W * (j + 1) - 1:`WORD_W * j] = r_mem[j + WORD_START];
    end
  endgenerate





  integer i;
  always@(posedge clk, negedge aresetn) begin
    if(aresetn == 0) begin

      for(i = 0; i < ADDR_COUNT; i = i + 1) begin
        r_mem[i] <= 0;
      end

      o_res_rd_data <= 0;
      o_res_code <= 0;


    end else if(i_req_count != `MEM_COUNT_NONE) begin

      if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||
        (i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin

        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_MISALIGNED;


      end else if(s_addr_aligned > ADDR_END) begin
        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_OUT_OF_BOUNDS;


      end else if(i_req_wr_en == 1) begin

        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_WRITE;


        case(i_req_count)
          `MEM_COUNT_BYTE:
            case(s_offset)
              0: r_mem[s_addr_aligned][7:0] <= i_req_wr_data[7:0];
              1: r_mem[s_addr_aligned][15:8] <= i_req_wr_data[7:0];
              2: r_mem[s_addr_aligned][23:16] <= i_req_wr_data[7:0];
              3: r_mem[s_addr_aligned][31:24] <= i_req_wr_data[7:0];
            endcase

          `MEM_COUNT_HALF:
            case(s_offset)
              0: r_mem[s_addr_aligned][15:0] <= i_req_wr_data[15:0];
              2: r_mem[s_addr_aligned][31:16] <= i_req_wr_data[15:0];
            endcase

          `MEM_COUNT_WORD: r_mem[s_addr_aligned] <= i_req_wr_data;

          default: o_res_code <= `MEM_CODE_INVALID;
        endcase

      end else begin


        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_READ;


        case(i_req_count)
          `MEM_COUNT_BYTE:
            case(s_offset)
              0: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][7:0];
              1: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][15:8];
              2: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][23:16];
              3: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][31:24];
            endcase

          `MEM_COUNT_HALF:
            case(s_offset)
              0: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][15:0];
              2: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][31:16];
            endcase

          `MEM_COUNT_WORD: o_res_rd_data <= r_mem[s_addr_aligned];

          default: o_res_code <= `MEM_CODE_INVALID;
        endcase

      end

    end else begin

      o_res_rd_data <= 0;
      o_res_code <= `MEM_CODE_INVALID;

    end
  end
endmodule