data/full_repos/permissive/194847941/demo/12_game/sources/rtl/mcu/ram.v
None: at end of input
data/verilator_xmls/b4b0dd72-0af9-4dc0-b2aa-127de3b7b1a2.xml
module ram
#(
  parameter Len = 256
)
(
    input   wire		clk,
    

    input   wire		ram_wen,
    input   wire [7:0]	ram_waddr,
    input   wire [7:0]	ram_wdata,
    

    input   wire		ram_ren,
    input   wire [7:0]	ram_raddr,
    output  reg  [7:0]	ram_rdata
);

reg [7:0] ram_reg [0:Len-1];


always@(posedge clk)
begin
    if(ram_wen)
        ram_reg[ram_waddr] <= ram_wdata;
end


always@(posedge clk)
begin
    if(ram_ren)
        ram_rdata <= ram_reg[ram_raddr];
end

endmodule
module ram
#(
  parameter Len = 256
)
(
    input   wire		clk,
    

    input   wire		ram_wen,
    input   wire [7:0]	ram_waddr,
    input   wire [7:0]	ram_wdata,
    

    input   wire		ram_ren,
    input   wire [7:0]	ram_raddr,
    output  reg  [7:0]	ram_rdata
);


reg [7:0] ram_reg [0:Len-1];


always@(posedge clk)
begin
    if(ram_wen)
        ram_reg[ram_waddr] <= ram_wdata;
end


always@(posedge clk)
begin
    if(ram_ren)
        ram_rdata <= ram_reg[ram_raddr];
end

endmodule