data/full_repos/permissive/20270692/labs/lab11/sram/sram_fifo.v
1: b'%Error: data/full_repos/permissive/20270692/labs/lab11/sram/sram_fifo.v:13: Cannot find include file: sram.v\n`include "sram.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab11/sram,data/full_repos/permissive/20270692/sram.v\n             data/full_repos/permissive/20270692/labs/lab11/sram,data/full_repos/permissive/20270692/sram.v.v\n             data/full_repos/permissive/20270692/labs/lab11/sram,data/full_repos/permissive/20270692/sram.v.sv\n             sram.v\n             sram.v.v\n             sram.v.sv\n             obj_dir/sram.v\n             obj_dir/sram.v.v\n             obj_dir/sram.v.sv\n%Error: Exiting due to 1 error(s)\n'
module SRAM_fifo(
    readMode,
    writeMode,
    inputPacket,
    outputPacket,
    clk,
    rst
  );

  parameter bits = 8;
  parameter depth = 3;
  parameter ad_length = 1<<depth;

  input readMode, writeMode, clk, rst;

  reg readModeQ, writeModeQ;

  input [bits-1:0] inputPacket;
  wire [bits-1:0] inputPacket;

  reg [bits-1:0] inputPacketQ;

  output [bits-1:0] outputPacket;
  wire [bits-1:0] outputPacket;

  reg [2:0] readPtr;
  reg [2:0] writePtr;
  reg [2:0] address;
  reg [2:0] nextReadPtr, nextWritePtr;


  SRAM sram (.read(readModeQ),
             .write(writeModeQ),
             .address(address),
             .dataIn(inputPacketQ),
             .dataOut(outputPacket),
             .clk(clk)
  );

  always @(posedge clk or posedge rst)
    if (rst) begin
      readPtr <= 3'h0;
      writePtr <= 3'h0;
      address <= 3'h0;
      inputPacketQ <= {bits{1'b0}};
      nextReadPtr <= 3'h0;
      nextWritePtr <= 3'h0;
    end else begin


      readPtr = nextReadPtr;
      writePtr = nextWritePtr;

      if (readModeQ) begin
        address <= nextReadPtr;
      end else if (writeModeQ) begin
        address <= nextWritePtr;
      end


      readModeQ = readMode;
      writeModeQ = writeMode;
      inputPacketQ = inputPacket;
    end


  always @(readPtr or writePtr or readMode or writeMode) begin
    nextReadPtr <= readMode ? readPtr + 1: readPtr;
    nextWritePtr <= writeMode ? writePtr + 1: writePtr;
  end

endmodule
module SRAM_fifo(
    readMode,
    writeMode,
    inputPacket,
    outputPacket,
    clk,
    rst
  );


  parameter bits = 8;
  parameter depth = 3;
  parameter ad_length = 1<<depth;

  input readMode, writeMode, clk, rst;

  reg readModeQ, writeModeQ;

  input [bits-1:0] inputPacket;
  wire [bits-1:0] inputPacket;

  reg [bits-1:0] inputPacketQ;

  output [bits-1:0] outputPacket;
  wire [bits-1:0] outputPacket;

  reg [2:0] readPtr;
  reg [2:0] writePtr;
  reg [2:0] address;
  reg [2:0] nextReadPtr, nextWritePtr;


  SRAM sram (.read(readModeQ),
             .write(writeModeQ),
             .address(address),
             .dataIn(inputPacketQ),
             .dataOut(outputPacket),
             .clk(clk)
  );

  always @(posedge clk or posedge rst)
    if (rst) begin
      readPtr <= 3'h0;
      writePtr <= 3'h0;
      address <= 3'h0;
      inputPacketQ <= {bits{1'b0}};
      nextReadPtr <= 3'h0;
      nextWritePtr <= 3'h0;
    end else begin


      readPtr = nextReadPtr;
      writePtr = nextWritePtr;

      if (readModeQ) begin
        address <= nextReadPtr;
      end else if (writeModeQ) begin
        address <= nextWritePtr;
      end


      readModeQ = readMode;
      writeModeQ = writeMode;
      inputPacketQ = inputPacket;
    end


  always @(readPtr or writePtr or readMode or writeMode) begin
    nextReadPtr <= readMode ? readPtr + 1: readPtr;
    nextWritePtr <= writeMode ? writePtr + 1: writePtr;
  end

endmodule