data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire/block_buffer.v
None: at end of input
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire/block_buffer.v:40: Cannot find include file: tartcfg.v\n`include "tartcfg.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire,data/full_repos/permissive/20430511/tartcfg.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire,data/full_repos/permissive/20430511/tartcfg.v.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire,data/full_repos/permissive/20430511/tartcfg.v.sv\n             tartcfg.v\n             tartcfg.v.v\n             tartcfg.v.sv\n             obj_dir/tartcfg.v\n             obj_dir/tartcfg.v.v\n             obj_dir/tartcfg.v.sv\n%Error: Exiting due to 1 error(s)\n'
module block_buffer
  #( parameter WIDTH = 24,
     parameter MSB   = WIDTH-1,
     parameter ABITS = 9,
     parameter ASB   = ABITS-1,
     parameter DEPTH = 1 << ABITS,
     parameter DELAY = 3)
   (
     input          read_clock_i,
     input [ASB:0]  read_address_i,
     output [MSB:0] read_data_o,

     input          write_clock_i,
     input          write_enable_i,
     input [ASB:0]  write_address_i,
     input [MSB:0]  write_data_i
     );

`ifndef __USE_EXPLICT_BRAM
   reg [MSB:0] block_buffer [0:DEPTH-1];
   reg [MSB:0] block_data = {WIDTH{1'b0}};

   assign read_data_o = block_data;

 `ifdef __icarus

   integer j;
   initial
     for (j=0; j <DEPTH; j = j+1) block_buffer[j] = 24'h0FF1CE;
 `endif

   always @(posedge read_clock_i)
     block_data <= #DELAY block_buffer[read_address_i];

   always @(posedge write_clock_i)
     if (write_enable_i)
       block_buffer[write_address_i] <= #DELAY write_data_i;


`else
   wire [13:0]      ADDRA, ADDRB;
   wire [31:0]      a_data, b_data;
   wire [3:0]       web = {4{write_enable_i}};


   assign ADDRA = {read_address_i , {14-ABITS{1'b0}}};
   assign ADDRB = {write_address_i, {14-ABITS{1'b0}}};


   assign web = {4{write_enable_i}};

   assign read_data_o = a_data[MSB:0];
   assign b_data = {{(32-WIDTH){1'b0}}, write_data_i};





   RAMB16BWER
     #(
         .DATA_WIDTH_A(36),
         .DATA_WIDTH_B(36),

         .DOA_REG(0),
         .DOB_REG(0),

         .EN_RSTRAM_A("FALSE"),
         .EN_RSTRAM_B("FALSE"),
         .RSTTYPE("SYNC"),
         .RST_PRIORITY_A("CE"),
         .RST_PRIORITY_B("CE"),
         .SIM_COLLISION_CHECK("NONE"),
         .SIM_DEVICE("SPARTAN6"),
         .INIT_A(36'h000000000),
         .INIT_B(36'h000000000),
         .INIT_FILE("NONE"),
         .SRVAL_A(36'h000000000),
         .SRVAL_B(36'h000000000),

         .WRITE_MODE_A("WRITE_FIRST"),
         .WRITE_MODE_B("WRITE_FIRST")
       ) BLOCK_BUFFER0
       ( .ADDRA(ADDRA),
         .CLKA(read_clock_i),
         .ENA(1'b1),
         .REGCEA(1'b0),
         .RSTA(1'b0),
         .WEA(4'b0000),

         .DIA(32'h0),
         .DIPA(4'h0),
         .DOA(a_data),
         .DOPA(),
         

         .ADDRB(ADDRB),
         .CLKB(write_clock_i),
         .ENB(1'b1),
         .REGCEB(1'b0),
         .RSTB(1'b0),
         .WEB(web),

         .DIB(b_data),
         .DIPB(4'h0),
         .DOB(),
         .DOPB()
         );
`endif


endmodule
module block_buffer
  #( parameter WIDTH = 24,
     parameter MSB   = WIDTH-1,
     parameter ABITS = 9,
     parameter ASB   = ABITS-1,
     parameter DEPTH = 1 << ABITS,
     parameter DELAY = 3)
   (
     input          read_clock_i,
     input [ASB:0]  read_address_i,
     output [MSB:0] read_data_o,

     input          write_clock_i,
     input          write_enable_i,
     input [ASB:0]  write_address_i,
     input [MSB:0]  write_data_i
     );


`ifndef __USE_EXPLICT_BRAM
   reg [MSB:0] block_buffer [0:DEPTH-1];
   reg [MSB:0] block_data = {WIDTH{1'b0}};

   assign read_data_o = block_data;

 `ifdef __icarus

   integer j;
   initial
     for (j=0; j <DEPTH; j = j+1) block_buffer[j] = 24'h0FF1CE;
 `endif

   always @(posedge read_clock_i)
     block_data <= #DELAY block_buffer[read_address_i];

   always @(posedge write_clock_i)
     if (write_enable_i)
       block_buffer[write_address_i] <= #DELAY write_data_i;


`else
   wire [13:0]      ADDRA, ADDRB;
   wire [31:0]      a_data, b_data;
   wire [3:0]       web = {4{write_enable_i}};


   assign ADDRA = {read_address_i , {14-ABITS{1'b0}}};
   assign ADDRB = {write_address_i, {14-ABITS{1'b0}}};


   assign web = {4{write_enable_i}};

   assign read_data_o = a_data[MSB:0];
   assign b_data = {{(32-WIDTH){1'b0}}, write_data_i};





   RAMB16BWER
     #(
         .DATA_WIDTH_A(36),
         .DATA_WIDTH_B(36),

         .DOA_REG(0),
         .DOB_REG(0),

         .EN_RSTRAM_A("FALSE"),
         .EN_RSTRAM_B("FALSE"),
         .RSTTYPE("SYNC"),
         .RST_PRIORITY_A("CE"),
         .RST_PRIORITY_B("CE"),
         .SIM_COLLISION_CHECK("NONE"),
         .SIM_DEVICE("SPARTAN6"),
         .INIT_A(36'h000000000),
         .INIT_B(36'h000000000),
         .INIT_FILE("NONE"),
         .SRVAL_A(36'h000000000),
         .SRVAL_B(36'h000000000),

         .WRITE_MODE_A("WRITE_FIRST"),
         .WRITE_MODE_B("WRITE_FIRST")
       ) BLOCK_BUFFER0
       ( .ADDRA(ADDRA),
         .CLKA(read_clock_i),
         .ENA(1'b1),
         .REGCEA(1'b0),
         .RSTA(1'b0),
         .WEA(4'b0000),

         .DIA(32'h0),
         .DIPA(4'h0),
         .DOA(a_data),
         .DOPA(),
         

         .ADDRB(ADDRB),
         .CLKB(write_clock_i),
         .ENB(1'b1),
         .REGCEB(1'b0),
         .RSTB(1'b0),
         .WEB(web),

         .DIB(b_data),
         .DIPB(4'h0),
         .DOB(),
         .DOPB()
         );
`endif


endmodule