data/full_repos/permissive/119387855/mips_core.v
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1: b'%Error: data/full_repos/permissive/119387855/mips_core.v:99: Unsupported or unknown PLI call: $monitor\n  $monitor("instruction: %b R1r:%b R2r:%b RS: %32b, RT: %32b, signal: %b, RD adress: %5b AluResult: %b Zero: %b alu_op: %4b",instruction, read_reg_1, read_reg_2, read_data_1, read_data_2, reg_write, write_reg, alu_result, zero, alu_op);\n  ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_core(clock);
	input clock;
	wire [31:0] instruction;	
	wire [31:0] read_data_1,read_data_2;
	wire [31:0] alu_result;
	wire zero;
	wire [1:0] reg_dst ;
	wire alu_src;
	wire [1:0] mem_to_reg ;
	wire reg_write;
	wire mem_read;
	wire mem_write;
	wire [1:0] branch ;
	wire [3:0] alu_op ;
	wire [1:0] jump ;
	wire [1:0] byte_number ;
	wire [31:0] memory_data;
	
	reg [31:0] PC = 32'b0;
	
	reg [5:0] op_code;
	reg [5:0] funct;
	reg [4:0] read_reg_1;
	reg [4:0] read_reg_2;
	reg [4:0] write_reg;

														
	reg [4:0] shamt;
	reg [31:0] sign_extend_imme;
	reg [31:0] alu_input_1;
	reg [31:0] alu_input_2;
	reg [31:0] write_data;
	
	reg [31:0] jump_address;
	reg [31:0] branch_address;
	reg [31:0] last_pc_address = 32'b0;
	wire is_branch;
	
	always @* begin		
		op_code = instruction[31:26];
		funct = instruction[5:0];
		read_reg_1 = instruction[25:21];
		read_reg_2 = instruction[20:16];
		shamt = instruction[10:6];
		
		if(reg_dst == 2'b00) begin
			write_reg = instruction[20:16];
		end else if(reg_dst == 2'b11) begin
			write_reg = instruction[15:11];
		end else if(reg_dst == 2'b01 || reg_dst == 2'b10) begin
			write_reg = 5'b11111;
		end		
	
		sign_extend_imme = {{16{instruction[15]}}, instruction[15:0]};
		jump_address = {PC[31:28], (instruction[25:0] << 2)};
		branch_address = (is_branch == 1'b1) ? ( (sign_extend_imme << 2) + PC + 4 ) : PC + 4;
			
		if(jump == 2'b11) begin
			last_pc_address = jump_address;		
		end else if (jump == 2'b01 || jump == 2'b10) begin 
			last_pc_address = read_data_1;
		end else if(jump == 2'b00) begin
			last_pc_address = branch_address;
		end
		
		alu_input_1 = read_data_1;
		
		if(alu_src == 1'b0) begin
			alu_input_2 = read_data_2;					
		end else if(alu_src == 1'b1) begin
			alu_input_2 = sign_extend_imme;
		end
		
		if(mem_to_reg == 2'b00) begin
			write_data = alu_result;
		end else if(mem_to_reg == 2'b01 || mem_to_reg == 2'b10) begin
			write_data = PC + 4;
		end else if(mem_to_reg == 2'b11) begin
			write_data = memory_data;
		end		
				

	end
	
	mips_alu alu(zero, alu_result, alu_op, alu_input_1, alu_input_2, shamt);
	mips_control signals(reg_dst, alu_src, mem_to_reg, reg_write, mem_read, mem_write, branch, alu_op, jump, byte_number, op_code, funct);
	mips_instr_mem instruction_mem(instruction, PC);
	mips_registers registers(read_data_1, read_data_2, write_data, read_reg_1, read_reg_2, write_reg, reg_write);
	mips_data_mem memory(memory_data, alu_result, alu_input_2, mem_read, mem_write, byte_number);
	mips_is_branch branch_value(is_branch, branch, zero);

	always @(posedge clock) begin 
		PC <= last_pc_address;
		
	end
	

	initial begin
		$monitor("instruction: %b R1r:%b R2r:%b RS: %32b, RT: %32b, signal: %b, RD adress: %5b AluResult: %b Zero: %b alu_op: %4b",instruction, read_reg_1, read_reg_2, read_data_1, read_data_2, reg_write, write_reg, alu_result, zero, alu_op);
	end


endmodule
module mips_core(clock);

	input clock;
	wire [31:0] instruction;	
	wire [31:0] read_data_1,read_data_2;
	wire [31:0] alu_result;
	wire zero;
	wire [1:0] reg_dst ;
	wire alu_src;
	wire [1:0] mem_to_reg ;
	wire reg_write;
	wire mem_read;
	wire mem_write;
	wire [1:0] branch ;
	wire [3:0] alu_op ;
	wire [1:0] jump ;
	wire [1:0] byte_number ;
	wire [31:0] memory_data;
	
	reg [31:0] PC = 32'b0;
	
	reg [5:0] op_code;
	reg [5:0] funct;
	reg [4:0] read_reg_1;
	reg [4:0] read_reg_2;
	reg [4:0] write_reg;

														
	reg [4:0] shamt;
	reg [31:0] sign_extend_imme;
	reg [31:0] alu_input_1;
	reg [31:0] alu_input_2;
	reg [31:0] write_data;
	
	reg [31:0] jump_address;
	reg [31:0] branch_address;
	reg [31:0] last_pc_address = 32'b0;
	wire is_branch;
	
	always @* begin		
		op_code = instruction[31:26];
		funct = instruction[5:0];
		read_reg_1 = instruction[25:21];
		read_reg_2 = instruction[20:16];
		shamt = instruction[10:6];
		
		if(reg_dst == 2'b00) begin
			write_reg = instruction[20:16];
		end else if(reg_dst == 2'b11) begin
			write_reg = instruction[15:11];
		end else if(reg_dst == 2'b01 || reg_dst == 2'b10) begin
			write_reg = 5'b11111;
		end		
	
		sign_extend_imme = {{16{instruction[15]}}, instruction[15:0]};
		jump_address = {PC[31:28], (instruction[25:0] << 2)};
		branch_address = (is_branch == 1'b1) ? ( (sign_extend_imme << 2) + PC + 4 ) : PC + 4;
			
		if(jump == 2'b11) begin
			last_pc_address = jump_address;		
		end else if (jump == 2'b01 || jump == 2'b10) begin 
			last_pc_address = read_data_1;
		end else if(jump == 2'b00) begin
			last_pc_address = branch_address;
		end
		
		alu_input_1 = read_data_1;
		
		if(alu_src == 1'b0) begin
			alu_input_2 = read_data_2;					
		end else if(alu_src == 1'b1) begin
			alu_input_2 = sign_extend_imme;
		end
		
		if(mem_to_reg == 2'b00) begin
			write_data = alu_result;
		end else if(mem_to_reg == 2'b01 || mem_to_reg == 2'b10) begin
			write_data = PC + 4;
		end else if(mem_to_reg == 2'b11) begin
			write_data = memory_data;
		end		
				

	end
	
	mips_alu alu(zero, alu_result, alu_op, alu_input_1, alu_input_2, shamt);
	mips_control signals(reg_dst, alu_src, mem_to_reg, reg_write, mem_read, mem_write, branch, alu_op, jump, byte_number, op_code, funct);
	mips_instr_mem instruction_mem(instruction, PC);
	mips_registers registers(read_data_1, read_data_2, write_data, read_reg_1, read_reg_2, write_reg, reg_write);
	mips_data_mem memory(memory_data, alu_result, alu_input_2, mem_read, mem_write, byte_number);
	mips_is_branch branch_value(is_branch, branch, zero);

	always @(posedge clock) begin 
		PC <= last_pc_address;
		
	end
	

	initial begin
		$monitor("instruction: %b R1r:%b R2r:%b RS: %32b, RT: %32b, signal: %b, RD adress: %5b AluResult: %b Zero: %b alu_op: %4b",instruction, read_reg_1, read_reg_2, read_data_1, read_data_2, reg_write, write_reg, alu_result, zero, alu_op);
	end


endmodule