data/full_repos/permissive/208519918/Simple-Processor/Processor_TB.v
 line:35: before: ")"
1: b'%Warning-STMTDLY: data/full_repos/permissive/208519918/Simple-Processor/Processor_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n  RESET = 1; #1000\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/208519918/Simple-Processor/Processor_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n always @(CLK)#500 CLK <= ~CLK;\n              ^\n%Error: data/full_repos/permissive/208519918/Simple-Processor/Processor_TB.v:22: Cannot find file containing module: \'Processor\'\n Processor uut1 (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208519918/Simple-Processor,data/full_repos/permissive/208519918/Processor\n             data/full_repos/permissive/208519918/Simple-Processor,data/full_repos/permissive/208519918/Processor.v\n             data/full_repos/permissive/208519918/Simple-Processor,data/full_repos/permissive/208519918/Processor.sv\n             Processor\n             Processor.v\n             Processor.sv\n             obj_dir/Processor\n             obj_dir/Processor.v\n             obj_dir/Processor.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Processor_TB;


	reg CLK;
	reg RESET;
	

	wire [2:0] OPCODE;
	wire [4:0] STATE;
	wire [11:0] PC, A, MA;
	wire [15:0] IR, AC, MD;
	

	reg [15:0] MEMORY [0:4095];
	

    parameter ZERO = 16'b0000000000000000;


	Processor uut1 (
		.CLK(CLK), 
		.RESET(RESET),
		.STATE(STATE),
		.OPCODE(OPCODE),
		.IR(IR),
		.PC(PC),
		.A(A),
		.AC(AC),
		.MD(MD),
		.MA(MA),


	);
	
	initial begin

		$readmemb("Memory.mem", MEMORY);

		CLK = 1;
		RESET = 1; #1000
		RESET = 0;
	end
	

	always @(CLK)#500 CLK <= ~CLK;
endmodule
module Processor_TB;



	reg CLK;
	reg RESET;
	

	wire [2:0] OPCODE;
	wire [4:0] STATE;
	wire [11:0] PC, A, MA;
	wire [15:0] IR, AC, MD;
	

	reg [15:0] MEMORY [0:4095];
	

    parameter ZERO = 16'b0000000000000000;


	Processor uut1 (
		.CLK(CLK), 
		.RESET(RESET),
		.STATE(STATE),
		.OPCODE(OPCODE),
		.IR(IR),
		.PC(PC),
		.A(A),
		.AC(AC),
		.MD(MD),
		.MA(MA),


	);
	
	initial begin

		$readmemb("Memory.mem", MEMORY);

		CLK = 1;
		RESET = 1; #1000
		RESET = 0;
	end
	

	always @(CLK)#500 CLK <= ~CLK;
endmodule