data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/control_unit_testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/control_unit_testbench.v:15: Unsupported or unknown PLI call: $monitor\n    $monitor(clk, instruction, reg_dst, jump, branch, mem_read, mem_write, mem_to_reg, alu_src, reg_write, alu_op);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/control_unit_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/control_unit_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/control_unit_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #20    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/control_unit_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #20    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/control_unit_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #20    \n    ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control_unit_testbench;

wire clk;
reg [5:0] instruction;
wire reg_dst, jump, branch, mem_read, mem_write, mem_to_reg, alu_src, reg_write;
wire [1:0] alu_op;

clock my_clock(.clk(clk));
control_unit uut(.clk(clk), .instruction(instruction), .reg_dst(reg_dst), .jump(jump), .branch(branch), .mem_read(mem_read), 
                .mem_to_reg(mem_to_reg), .alu_op(alu_op), .mem_write(mem_write), .alu_src(alu_src), .reg_write(reg_write));

initial begin
    $monitor(clk, instruction, reg_dst, jump, branch, mem_read, mem_write, mem_to_reg, alu_src, reg_write, alu_op);
    

    instruction=6'b000000;
    #20

    instruction=6'b100011;
    #20

    instruction=6'b101011;
    #20    

    instruction=6'b000100;
    #20    

    instruction=6'b000010;
    #20    
    $finish;
end
endmodule
module control_unit_testbench;


wire clk;
reg [5:0] instruction;
wire reg_dst, jump, branch, mem_read, mem_write, mem_to_reg, alu_src, reg_write;
wire [1:0] alu_op;

clock my_clock(.clk(clk));
control_unit uut(.clk(clk), .instruction(instruction), .reg_dst(reg_dst), .jump(jump), .branch(branch), .mem_read(mem_read), 
                .mem_to_reg(mem_to_reg), .alu_op(alu_op), .mem_write(mem_write), .alu_src(alu_src), .reg_write(reg_write));

initial begin
    $monitor(clk, instruction, reg_dst, jump, branch, mem_read, mem_write, mem_to_reg, alu_src, reg_write, alu_op);
    

    instruction=6'b000000;
    #20

    instruction=6'b100011;
    #20

    instruction=6'b101011;
    #20    

    instruction=6'b000100;
    #20    

    instruction=6'b000010;
    #20    
    $finish;
end
endmodule