data/full_repos/permissive/205769493/src/arithmetic.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/205769493/src/arithmetic.v:16: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'m_8bit_plus1_adder\'\nmodule m_8bit_plus1_adder (w_bus_eight_out, w_bus_eight_in);\n       ^~~~~~~~~~~~~~~~~~\n                                                                           : ... Top module \'m_arithmetic_logic_unit\'\nmodule m_arithmetic_logic_unit (w_bus_alu_out, w_cf, word, w_bus_high_register_value, w_bus_low_register_value, w_clock);\n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module m_8bit_plus1_adder (w_bus_eight_out, w_bus_eight_in);
	output [7:0] w_bus_eight_out;
	input [7:0] w_bus_eight_in;

	assign w_bus_eight_out = w_bus_eight_in + 1;
endmodule
module m_8bit_plus1_adder (w_bus_eight_out, w_bus_eight_in);

	output [7:0] w_bus_eight_out;
	input [7:0] w_bus_eight_in;

	assign w_bus_eight_out = w_bus_eight_in + 1;
endmodule