data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v
 line:105: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:121: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'INIT_CTL_TARGET\' generates 1 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n            reg_ctl_target  <= INIT_CTL_TARGET;\n                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:169: Operator ADD expects 48 bits on the RHS, but RHS\'s VARREF \'reg_v\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                reg_cur_x <= reg_cur_x + reg_v;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:179: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_ctl_enable\' generates 1 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_CTL_ENABLE:  reg_ctl_enable  <= reg_mask(reg_ctl_enable,  s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:179: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_CTL_ENABLE:  reg_ctl_enable  <= reg_mask(reg_ctl_enable,  s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:180: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_ctl_target\' generates 3 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_CTL_TARGET:  reg_ctl_target  <= reg_mask(reg_ctl_target,  s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:180: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_CTL_TARGET:  reg_ctl_target  <= reg_mask(reg_ctl_target,  s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:181: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_ctl_pwm\' generates 2 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_CTL_PWM:     reg_ctl_pwm     <= reg_mask(reg_ctl_pwm,     s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:181: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_CTL_PWM:     reg_ctl_pwm     <= reg_mask(reg_ctl_pwm,     s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:182: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_target_x\' generates 48 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_TARGET_X:    reg_target_x    <= reg_mask(reg_target_x,    s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:182: Operator ASSIGNDLY expects 48 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_TARGET_X:    reg_target_x    <= reg_mask(reg_target_x,    s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:183: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_target_v\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_TARGET_V:    reg_target_v    <= reg_mask(reg_target_v,    s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:183: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_TARGET_V:    reg_target_v    <= reg_mask(reg_target_v,    s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:184: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_target_a\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_TARGET_A:    reg_target_a    <= reg_mask(reg_target_a,    s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:184: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_TARGET_A:    reg_target_a    <= reg_mask(reg_target_a,    s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:185: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_max_v\' generates 24 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_MAX_V:       reg_max_v       <= reg_mask(reg_max_v,       s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:185: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_MAX_V:       reg_max_v       <= reg_mask(reg_max_v,       s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:186: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_max_a\' generates 24 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_MAX_A:       reg_max_a       <= reg_mask(reg_max_a,       s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:186: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_MAX_A:       reg_max_a       <= reg_mask(reg_max_a,       s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:187: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_max_a_near\' generates 24 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_MAX_A_NEAR:  reg_max_a_near  <= reg_mask(reg_max_a_near,  s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:187: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_MAX_A_NEAR:  reg_max_a_near  <= reg_mask(reg_max_a_near,  s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:178: Operator CASE expects 8 bits on the Case expression, but Case expression\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                case ( s_wb_adr_i )\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:193: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n    assign s_wb_dat_o = (s_wb_adr_i == ADR_CORE_ID)     ? CORE_ID                 :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:194: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CTL_ENABLE)  ? reg_ctl_enable          :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:195: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CTL_TARGET)  ? reg_ctl_target          :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:196: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CTL_PWM)     ? reg_ctl_pwm             :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:197: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TARGET_X)    ? reg_target_x            :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:198: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TARGET_V)    ? reg_target_v            :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:199: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TARGET_A)    ? reg_target_a            :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:200: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_MAX_V)       ? reg_max_v               :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:201: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_MAX_A)       ? reg_max_a               :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:202: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_MAX_A_NEAR)  ? reg_max_a_near          :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:203: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CUR_X)       ? (reg_cur_x >>> X_SHIFT) :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:204: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CUR_V)       ? reg_cur_v               :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:205: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CUR_A)       ? reg_cur_a               :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:206: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TIME)        ? reg_time                :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:193: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'CORE_ID\' generates 32 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n    assign s_wb_dat_o = (s_wb_adr_i == ADR_CORE_ID)     ? CORE_ID                 :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:194: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_ctl_enable\' generates 1 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CTL_ENABLE)  ? reg_ctl_enable          :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:195: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_ctl_target\' generates 3 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CTL_TARGET)  ? reg_ctl_target          :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:196: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_ctl_pwm\' generates 2 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CTL_PWM)     ? reg_ctl_pwm             :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:197: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_target_x\' generates 48 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TARGET_X)    ? reg_target_x            :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:198: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_target_v\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TARGET_V)    ? reg_target_v            :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:199: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_target_a\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TARGET_A)    ? reg_target_a            :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:200: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_max_v\' generates 24 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_MAX_V)       ? reg_max_v               :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:201: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_max_a\' generates 24 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_MAX_A)       ? reg_max_a               :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:202: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_max_a_near\' generates 24 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_MAX_A_NEAR)  ? reg_max_a_near          :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:203: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'reg_cur_x\' generates 48 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CUR_X)       ? (reg_cur_x >>> X_SHIFT) :\n                                                                     ^~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:204: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_cur_v\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CUR_V)       ? reg_cur_v               :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:205: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_cur_a\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CUR_A)       ? reg_cur_a               :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:206: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_time\' generates 32 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TIME)        ? reg_time                :\n                                                        ^\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:212: Cannot find file containing module: \'stepper_motor_control_calc\'\n    stepper_motor_control_calc\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl,data/full_repos/permissive/2084115/stepper_motor_control_calc\n             data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl,data/full_repos/permissive/2084115/stepper_motor_control_calc.v\n             data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl,data/full_repos/permissive/2084115/stepper_motor_control_calc.sv\n             stepper_motor_control_calc\n             stepper_motor_control_calc.v\n             stepper_motor_control_calc.sv\n             obj_dir/stepper_motor_control_calc\n             obj_dir/stepper_motor_control_calc.v\n             obj_dir/stepper_motor_control_calc.sv\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:237: Cannot find file containing module: \'bipolar_stepper_motor_drive\'\n    bipolar_stepper_motor_drive\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 49 warning(s)\n'
function [WB_DAT_WIDTH-1:0] reg_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );
    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            reg_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction
function [WB_DAT_WIDTH-1:0] reg_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );

    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            reg_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction