data/full_repos/permissive/184431263/OAI/OAI24.v
data/verilator_xmls/eb3324e1-2ccc-40e9-9139-6c75f9315a95.xml
module OAI24(Y, A0, A1, B0, B1, C0, C1, D0, D1, VDD, VSS );
  input A0, A1, B0, B1, C0, C1, D0, D1;
  output Y;
  inout VDD, VSS;

  assign Y=~((A0 || A1) && (B0 || B1) && (C0 || C1) && (D0 || D1));
endmodule
module OAI24(Y, A0, A1, B0, B1, C0, C1, D0, D1, VDD, VSS );

  input A0, A1, B0, B1, C0, C1, D0, D1;
  output Y;
  inout VDD, VSS;

  assign Y=~((A0 || A1) && (B0 || B1) && (C0 || C1) && (D0 || D1));
endmodule