data/full_repos/permissive/160024456/day02/delta_test.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/160024456/day02/delta_test.v:13: Unsupported: Ignoring delay on this delayed statement.\n    b[0] = 119; b[1] = 115; b[2] = 112; b[3] = 105; b[4] = 111; b[5] = 103; b[6] = 115; b[7] = 106; b[8] = 100; b[9] = 102; b[10] = 101; b[11] = 99; b[12] = 106; b[13] = 100; b[14] = 113; b[15] = 109; b[16] = 110; b[17] = 120; b[18] = 97; b[19] = 107; b[20] = 117; b[21] = 100; b[22] = 114; b[23] = 104; b[24] = 98; b[25] = 122; #10\n                                                                                                                                                                                                                                                                                                                                         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/160024456/day02/delta_test.v:7: Cannot find file containing module: \'delta\'\n  delta dut (.a(a), .b(b), .r(r));\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/160024456/day02,data/full_repos/permissive/160024456/delta\n             data/full_repos/permissive/160024456/day02,data/full_repos/permissive/160024456/delta.v\n             data/full_repos/permissive/160024456/day02,data/full_repos/permissive/160024456/delta.sv\n             delta\n             delta.v\n             delta.sv\n             obj_dir/delta\n             obj_dir/delta.v\n             obj_dir/delta.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module delta_test;

  reg [25:0][7:0] a;
  reg [25:0][7:0] b;
  wire [5:0] r;

  delta dut (.a(a), .b(b), .r(r));

  initial begin
    $display("start");

    a[0] = 119; a[1] = 108; a[2] = 112; a[3] = 105; a[4] = 111; a[5] = 103; a[6] = 115; a[7] = 118; a[8] = 100; a[9] = 102; a[10] = 101; a[11] = 99; a[12] = 106; a[13] = 100; a[14] = 113; a[15] = 109; a[16] = 110; a[17] = 120; a[18] = 97; a[19] = 107; a[20] = 117; a[21] = 100; a[22] = 114; a[23] = 104; a[24] = 98; a[25] = 122;
    b[0] = 119; b[1] = 115; b[2] = 112; b[3] = 105; b[4] = 111; b[5] = 103; b[6] = 115; b[7] = 106; b[8] = 100; b[9] = 102; b[10] = 101; b[11] = 99; b[12] = 106; b[13] = 100; b[14] = 113; b[15] = 109; b[16] = 110; b[17] = 120; b[18] = 97; b[19] = 107; b[20] = 117; b[21] = 100; b[22] = 114; b[23] = 104; b[24] = 98; b[25] = 122; #10
    if (r != 24)
      $display("failed a=%b", a, ", b=%b", b, ", r=", r);

    $display("done");
  end

endmodule
module delta_test;


  reg [25:0][7:0] a;
  reg [25:0][7:0] b;
  wire [5:0] r;

  delta dut (.a(a), .b(b), .r(r));

  initial begin
    $display("start");

    a[0] = 119; a[1] = 108; a[2] = 112; a[3] = 105; a[4] = 111; a[5] = 103; a[6] = 115; a[7] = 118; a[8] = 100; a[9] = 102; a[10] = 101; a[11] = 99; a[12] = 106; a[13] = 100; a[14] = 113; a[15] = 109; a[16] = 110; a[17] = 120; a[18] = 97; a[19] = 107; a[20] = 117; a[21] = 100; a[22] = 114; a[23] = 104; a[24] = 98; a[25] = 122;
    b[0] = 119; b[1] = 115; b[2] = 112; b[3] = 105; b[4] = 111; b[5] = 103; b[6] = 115; b[7] = 106; b[8] = 100; b[9] = 102; b[10] = 101; b[11] = 99; b[12] = 106; b[13] = 100; b[14] = 113; b[15] = 109; b[16] = 110; b[17] = 120; b[18] = 97; b[19] = 107; b[20] = 117; b[21] = 100; b[22] = 114; b[23] = 104; b[24] = 98; b[25] = 122; #10
    if (r != 24)
      $display("failed a=%b", a, ", b=%b", b, ", r=", r);

    $display("done");
  end

endmodule