data/full_repos/permissive/209534045/src/wsg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/209534045/src/wsg.v:197: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'waveout\' generates 8 bits.\n                                                                  : ... In instance WSG_3CH.core\n            sndmix  <= sndmix + waveout;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/209534045/src/wsg.v:204: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'waveout\' generates 8 bits.\n                                                                  : ... In instance WSG_3CH.core\n            sndmix  <= sndmix + waveout;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/209534045/src/wsg.v:212: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'waveout\' generates 8 bits.\n                                                                  : ... In instance WSG_3CH.core\n            sndmix  <= sndmix + waveout;\n                              ^\n%Error: Exiting due to 3 warning(s)\n'
module WSG_3CH
(
   input			 CLK48M,
   input        RESET,

   input        CPUCLK,
   input  [4:0] ADRS,
   input  [3:0] DATA,
   input        WR,

	output		 WROMCLK,
   output [7:0] WROMADR,
   input  [3:0] WROMDAT,

	output		 PCMCLK,
   output [7:0] PCMOUT
);

wire WSGCLKx4;
WSGCLKGEN cgen( CLK48M, WSGCLKx4 );

wire  [2:0] W0, W1, W2;
wire  [3:0] V0, V1, V2;
wire [19:0] F0;
wire [15:0]     F1, F2;

WSGREGS regs
(
	RESET,
	CPUCLK, ADRS, WR, DATA,

	W0, W1, W2,
	V0, V1, V2,
	F0, F1, F2
);

WSGCORE core
(
	RESET, WSGCLKx4,
	WROMCLK, WROMADR, WROMDAT,

	W0, W1, W2, 
	V0, V1, V2,
	F0, F1, F2,

	PCMCLK, PCMOUT
);

endmodule
module WSG_3CH
(
   input			 CLK48M,
   input        RESET,

   input        CPUCLK,
   input  [4:0] ADRS,
   input  [3:0] DATA,
   input        WR,

	output		 WROMCLK,
   output [7:0] WROMADR,
   input  [3:0] WROMDAT,

	output		 PCMCLK,
   output [7:0] PCMOUT
);


wire WSGCLKx4;
WSGCLKGEN cgen( CLK48M, WSGCLKx4 );

wire  [2:0] W0, W1, W2;
wire  [3:0] V0, V1, V2;
wire [19:0] F0;
wire [15:0]     F1, F2;

WSGREGS regs
(
	RESET,
	CPUCLK, ADRS, WR, DATA,

	W0, W1, W2,
	V0, V1, V2,
	F0, F1, F2
);

WSGCORE core
(
	RESET, WSGCLKx4,
	WROMCLK, WROMADR, WROMDAT,

	W0, W1, W2, 
	V0, V1, V2,
	F0, F1, F2,

	PCMCLK, PCMOUT
);

endmodule