data/full_repos/permissive/204164783/procUnit.sv
 line:9: before: "]"
1: b"%Error: data/full_repos/permissive/204164783/procUnit.sv:49: Cannot find file containing module: 'fifo_32'\n    fifo_32 accfifo(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/204164783,data/full_repos/permissive/204164783/fifo_32\n             data/full_repos/permissive/204164783,data/full_repos/permissive/204164783/fifo_32.v\n             data/full_repos/permissive/204164783,data/full_repos/permissive/204164783/fifo_32.sv\n             fifo_32\n             fifo_32.v\n             fifo_32.sv\n             obj_dir/fifo_32\n             obj_dir/fifo_32.v\n             obj_dir/fifo_32.sv\n%Error: data/full_repos/permissive/204164783/procUnit.sv:61: Cannot find file containing module: 'procControl'\n    procControl ctrl(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/204164783/procUnit.sv:69: Cannot find file containing module: 'procRouter'\n    procRouter router(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/204164783/procUnit.sv:106: Cannot find file containing module: 'procCore'\n    procCore#(\n    ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module procUnit
#(
    parameter WDATA_ROW_LEN = 16
)
(
    input clock,
    input reset,

    input  [31:0] weights[WDATA_ROW_LEN],


    input  [23:0] confin_i,
	input         confvalid_i,
	output [23:0] confout_o,



	input         stall_omux_i,


	

	input  [39:0] broadcastdata_i,
	input         broadcastvalid_i,
	output        broadcaststall_o,
	

	input  [39:0] psum_i,
    input         psum_valid_i,
	output [39:0] psum_o,
	output        psum_to_prev_valid_o,
	output        psum_to_omux_valid_o,


    input         psum_can_send_i,
    output        psum_can_accept_o
	
);
    wire [31:0] fifodatain;
    wire fifowrite;

    wire fifofull;
    wire fifoempty;
    wire [31:0] fifodataout;
    wire fiforead;

    assign broadcaststall_o = fifofull;

    fifo_32 accfifo(
    	.aclr(reset),
    	.clock(clock),
    	.data(fifodatain),
    	.rdreq(fiforead),
    	.wrreq(fifowrite),
    	.empty(fifoempty),
    	.full(fifofull),
    	.q(fifodataout),
    	.usedw()
    );

    procControl ctrl(
        .clock(clock),
        .reset(reset),
        .confin_i(confin_i),
        .confvalid_i(confvalid_i),
        .confout_o(confout_o)
    );

    procRouter router(
        .clock(clock),
        .reset(reset),

	    .stall_omux_i(stall_omux_i),


	

	    .psum_i(psum_i),
        .psum_valid_i(psum_valid_i),
        .psum_o(psum_o),
	    .psum_to_prev_valid_o(psum_to_prev_valid_o),
	    .psum_to_omux_valid_o(psum_to_omux_valid_o),


        .psum_can_send_i(psum_can_send_i),
        .psum_can_accept_o(psum_can_accept_o),
	

	    .conf_i(confout_o),




        .fifo_empty_i(fifoempty),
        .fifo_rdreq_o(fiforead),
        .fifo_rddata_i(fifodataout)

    );

    wire accdata_valid;
    assign fifowrite = accdata_valid && !fifofull;

    wire [31:0] data      = broadcastdata_i[39:32] == confout_o[7:0] ? broadcastdata_i[31:0] : 32'b0;
    wire        datavalid = broadcastdata_i[39:32] == confout_o[7:0] ? broadcastvalid_i      : 1'b0;

    procCore#(
        .WDATA_ROW_LEN(WDATA_ROW_LEN)
    ) core(
        .clock(clock),
        .reset(reset),
        .conf_i(confout_o),
        .weights(weights),
        .data_i(data),
        .datavalid_i(datavalid),
        .stall_i(fifofull),
        .accresvalid_o(accdata_valid),
        .accres_o(fifodatain)
    );


endmodule
module procUnit
#(
    parameter WDATA_ROW_LEN = 16
)
(
    input clock,
    input reset,

    input  [31:0] weights[WDATA_ROW_LEN],


    input  [23:0] confin_i,
	input         confvalid_i,
	output [23:0] confout_o,



	input         stall_omux_i,


	

	input  [39:0] broadcastdata_i,
	input         broadcastvalid_i,
	output        broadcaststall_o,
	

	input  [39:0] psum_i,
    input         psum_valid_i,
	output [39:0] psum_o,
	output        psum_to_prev_valid_o,
	output        psum_to_omux_valid_o,


    input         psum_can_send_i,
    output        psum_can_accept_o
	
);

    wire [31:0] fifodatain;
    wire fifowrite;

    wire fifofull;
    wire fifoempty;
    wire [31:0] fifodataout;
    wire fiforead;

    assign broadcaststall_o = fifofull;

    fifo_32 accfifo(
    	.aclr(reset),
    	.clock(clock),
    	.data(fifodatain),
    	.rdreq(fiforead),
    	.wrreq(fifowrite),
    	.empty(fifoempty),
    	.full(fifofull),
    	.q(fifodataout),
    	.usedw()
    );

    procControl ctrl(
        .clock(clock),
        .reset(reset),
        .confin_i(confin_i),
        .confvalid_i(confvalid_i),
        .confout_o(confout_o)
    );

    procRouter router(
        .clock(clock),
        .reset(reset),

	    .stall_omux_i(stall_omux_i),


	

	    .psum_i(psum_i),
        .psum_valid_i(psum_valid_i),
        .psum_o(psum_o),
	    .psum_to_prev_valid_o(psum_to_prev_valid_o),
	    .psum_to_omux_valid_o(psum_to_omux_valid_o),


        .psum_can_send_i(psum_can_send_i),
        .psum_can_accept_o(psum_can_accept_o),
	

	    .conf_i(confout_o),




        .fifo_empty_i(fifoempty),
        .fifo_rdreq_o(fiforead),
        .fifo_rddata_i(fifodataout)

    );

    wire accdata_valid;
    assign fifowrite = accdata_valid && !fifofull;

    wire [31:0] data      = broadcastdata_i[39:32] == confout_o[7:0] ? broadcastdata_i[31:0] : 32'b0;
    wire        datavalid = broadcastdata_i[39:32] == confout_o[7:0] ? broadcastvalid_i      : 1'b0;

    procCore#(
        .WDATA_ROW_LEN(WDATA_ROW_LEN)
    ) core(
        .clock(clock),
        .reset(reset),
        .conf_i(confout_o),
        .weights(weights),
        .data_i(data),
        .datavalid_i(datavalid),
        .stall_i(fifofull),
        .accresvalid_o(accdata_valid),
        .accres_o(fifodatain)
    );


endmodule