data/full_repos/permissive/143278/vhdl_tests/pr2536040.v
data/verilator_xmls/4dc919b0-f616-454e-8235-6891b9d230f4.xml
module test ( input a, input _b_, output A, output b__);
  assign A = a;
  assign b__ = _b_;
endmodule
module test ( input a, input _b_, output A, output b__);

  assign A = a;
  assign b__ = _b_;
endmodule