data/full_repos/permissive/118027048/rtl/VarintParser.v
data/verilator_xmls/758a8724-56f5-408c-9118-0f70fec73790.xml
module VarintParser(
	input wire			clk,

	input wire			start,
	input wire			valid,
	input wire[7:0]		din,
	input wire			dsign,

	output wire[63:0]	dout,
	output wire			done,
	output wire			error
	);




	reg					active_ff		= 0;
	reg[63:0]			data_temp_ff	= 0;
	reg[63:0]			data_temp		= 0;
	reg[3:0]			bytecount		= 0;


	wire				active		= active_ff || start;


	assign				done		= active && valid && !din[7];


	wire[63:0]			dout_unsigned	= done ? data_temp : 0;


	wire[63:0]			dout_signed		= dout_unsigned[0] ? ~(dout_unsigned >> 1) : (dout_unsigned >> 1);


	assign				dout			= dsign ? dout_signed : dout_unsigned;



	assign				error		= (bytecount == 10) && active;


	always @(*) begin


		data_temp	<= data_temp_ff;


		if(valid) begin
			case(bytecount)
				0:	data_temp[0*7 +: 7]	<= din[6:0];
				1:	data_temp[1*7 +: 7]	<= din[6:0];
				2:	data_temp[2*7 +: 7]	<= din[6:0];
				3:	data_temp[3*7 +: 7]	<= din[6:0];
				4:	data_temp[4*7 +: 7]	<= din[6:0];
				5:	data_temp[5*7 +: 7]	<= din[6:0];
				6:	data_temp[6*7 +: 7]	<= din[6:0];
				7:	data_temp[7*7 +: 7]	<= din[6:0];
				8:	data_temp[8*7 +: 7]	<= din[6:0];
				9:	data_temp[63]		<= din[0];
			endcase
		end
		
	end

	always @(posedge clk) begin


		active_ff		<= active && !done;


		if(start)
			bytecount	<= 1;


		else if(valid)
			bytecount	<= bytecount + 1'h1;


		if(done) begin
			bytecount		<= 0;
			data_temp_ff	<= 0;
		end


		else
			data_temp_ff	<= data_temp;
	
	end

endmodule
module VarintParser(
	input wire			clk,

	input wire			start,
	input wire			valid,
	input wire[7:0]		din,
	input wire			dsign,

	output wire[63:0]	dout,
	output wire			done,
	output wire			error
	);





	reg					active_ff		= 0;
	reg[63:0]			data_temp_ff	= 0;
	reg[63:0]			data_temp		= 0;
	reg[3:0]			bytecount		= 0;


	wire				active		= active_ff || start;


	assign				done		= active && valid && !din[7];


	wire[63:0]			dout_unsigned	= done ? data_temp : 0;


	wire[63:0]			dout_signed		= dout_unsigned[0] ? ~(dout_unsigned >> 1) : (dout_unsigned >> 1);


	assign				dout			= dsign ? dout_signed : dout_unsigned;



	assign				error		= (bytecount == 10) && active;


	always @(*) begin


		data_temp	<= data_temp_ff;


		if(valid) begin
			case(bytecount)
				0:	data_temp[0*7 +: 7]	<= din[6:0];
				1:	data_temp[1*7 +: 7]	<= din[6:0];
				2:	data_temp[2*7 +: 7]	<= din[6:0];
				3:	data_temp[3*7 +: 7]	<= din[6:0];
				4:	data_temp[4*7 +: 7]	<= din[6:0];
				5:	data_temp[5*7 +: 7]	<= din[6:0];
				6:	data_temp[6*7 +: 7]	<= din[6:0];
				7:	data_temp[7*7 +: 7]	<= din[6:0];
				8:	data_temp[8*7 +: 7]	<= din[6:0];
				9:	data_temp[63]		<= din[0];
			endcase
		end
		
	end

	always @(posedge clk) begin


		active_ff		<= active && !done;


		if(start)
			bytecount	<= 1;


		else if(valid)
			bytecount	<= bytecount + 1'h1;


		if(done) begin
			bytecount		<= 0;
			data_temp_ff	<= 0;
		end


		else
			data_temp_ff	<= data_temp;
	
	end

endmodule