data/full_repos/permissive/204486675/components/clkdivider/clkdivider.v
1: b'%Warning-WIDTH: data/full_repos/permissive/204486675/components/clkdivider/clkdivider.v:32: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                          : ... In instance clockdiv\n count = 16\'b0000000000000000;\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/204486675/components/clkdivider/clkdivider.v:38: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                          : ... In instance clockdiv\n  count = 16\'b0;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/204486675/components/clkdivider/clkdivider.v:44: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                          : ... In instance clockdiv\n  count = 16\'b0000000000000000;\n        ^\n%Error: Exiting due to 3 warning(s)\n'
module clockdiv (
rst,
clkin,
clkout,
halfperiod
);

input rst;
input clkin;
output reg clkout;
input [16:0] halfperiod;

reg [16:0] count;
reg [16:0] lasthalfperiod;

always @ (posedge clkin or posedge rst)
if (rst)
begin
	count = 16'b0000000000000000;
	clkout = 1'b0;
end
else
begin
	if (halfperiod != lasthalfperiod)
		count = 16'b0;
		
	lasthalfperiod = halfperiod;

	if (count == halfperiod)
	begin
		count = 16'b0000000000000000;
		clkout = ~clkout;
	end
	else
	begin
		count = count + 1'b1;
	end
end

endmodule
module clockdiv (
rst,
clkin,
clkout,
halfperiod
);


input rst;
input clkin;
output reg clkout;
input [16:0] halfperiod;

reg [16:0] count;
reg [16:0] lasthalfperiod;

always @ (posedge clkin or posedge rst)
if (rst)
begin
	count = 16'b0000000000000000;
	clkout = 1'b0;
end
else
begin
	if (halfperiod != lasthalfperiod)
		count = 16'b0;
		
	lasthalfperiod = halfperiod;

	if (count == halfperiod)
	begin
		count = 16'b0000000000000000;
		clkout = ~clkout;
	end
	else
	begin
		count = count + 1'b1;
	end
end

endmodule