data/full_repos/permissive/169597129/top/rtl/clk_gen.v
None: at end of input
1: b'%Error: data/full_repos/permissive/169597129/top/rtl/clk_gen.v:12: Cannot find include file: nettype.h\n`include "nettype.h" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169597129/top/rtl,data/full_repos/permissive/169597129/nettype.h\n             data/full_repos/permissive/169597129/top/rtl,data/full_repos/permissive/169597129/nettype.h.v\n             data/full_repos/permissive/169597129/top/rtl,data/full_repos/permissive/169597129/nettype.h.sv\n             nettype.h\n             nettype.h.v\n             nettype.h.sv\n             obj_dir/nettype.h\n             obj_dir/nettype.h.v\n             obj_dir/nettype.h.sv\n%Error: data/full_repos/permissive/169597129/top/rtl/clk_gen.v:13: Cannot find include file: stddef.h\n`include "stddef.h" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/top/rtl/clk_gen.v:14: Cannot find include file: global_config.h\n`include "global_config.h" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/top/rtl/clk_gen.v:34: Define or directive not defined: \'`RESET_ENABLE\'\n assign dcm_reset  = (reset_sw == `RESET_ENABLE) ? `ENABLE : `DISABLE;\n                                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/top/rtl/clk_gen.v:34: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign dcm_reset  = (reset_sw == `RESET_ENABLE) ? `ENABLE : `DISABLE;\n                                               ^\n%Error: data/full_repos/permissive/169597129/top/rtl/clk_gen.v:34: Define or directive not defined: \'`ENABLE\'\n assign dcm_reset  = (reset_sw == `RESET_ENABLE) ? `ENABLE : `DISABLE;\n                                                   ^~~~~~~\n%Error: data/full_repos/permissive/169597129/top/rtl/clk_gen.v:34: Define or directive not defined: \'`DISABLE\'\n assign dcm_reset  = (reset_sw == `RESET_ENABLE) ? `ENABLE : `DISABLE;\n                                                             ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/top/rtl/clk_gen.v:36: Define or directive not defined: \'`RESET_ENABLE\'\n assign chip_reset = ((reset_sw == `RESET_ENABLE) || (locked == `DISABLE)) ?\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/top/rtl/clk_gen.v:36: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign chip_reset = ((reset_sw == `RESET_ENABLE) || (locked == `DISABLE)) ?\n                                                ^\n%Error: data/full_repos/permissive/169597129/top/rtl/clk_gen.v:36: Define or directive not defined: \'`DISABLE\'\n assign chip_reset = ((reset_sw == `RESET_ENABLE) || (locked == `DISABLE)) ?\n                                                                ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/top/rtl/clk_gen.v:37: Define or directive not defined: \'`RESET_ENABLE\'\n       `RESET_ENABLE : `RESET_DISABLE;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/top/rtl/clk_gen.v:37: Define or directive not defined: \'`RESET_DISABLE\'\n       `RESET_ENABLE : `RESET_DISABLE;\n                       ^~~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module clk_gen (

	input wire	clk_ref,
	input wire	reset_sw,

	output wire clk,
	output wire clk_,

	output wire chip_reset
);


	wire		locked;
	wire		dcm_reset;



	assign dcm_reset  = (reset_sw == `RESET_ENABLE) ? `ENABLE : `DISABLE;

	assign chip_reset = ((reset_sw == `RESET_ENABLE) || (locked == `DISABLE)) ?
							`RESET_ENABLE : `RESET_DISABLE;


	x_s3e_dcm x_s3e_dcm (
		.CLKIN_IN		 (clk_ref),
		.RST_IN			 (dcm_reset),
		.CLK0_OUT		 (clk),
		.CLK180_OUT		 (clk_),
		.LOCKED_OUT		 (locked)
   );

endmodule
module clk_gen (

	input wire	clk_ref,
	input wire	reset_sw,

	output wire clk,
	output wire clk_,

	output wire chip_reset
);



	wire		locked;
	wire		dcm_reset;



	assign dcm_reset  = (reset_sw == `RESET_ENABLE) ? `ENABLE : `DISABLE;

	assign chip_reset = ((reset_sw == `RESET_ENABLE) || (locked == `DISABLE)) ?
							`RESET_ENABLE : `RESET_DISABLE;


	x_s3e_dcm x_s3e_dcm (
		.CLKIN_IN		 (clk_ref),
		.RST_IN			 (dcm_reset),
		.CLK0_OUT		 (clk),
		.CLK180_OUT		 (clk_),
		.LOCKED_OUT		 (locked)
   );

endmodule