data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v
 line:32: before: "("
1: b"%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:14: Unsupported or unknown PLI call: $anyseq\nreg  [31:0] rs1      = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:15: Unsupported or unknown PLI call: $anyseq\nreg  [31:0] rs2      = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:16: Unsupported or unknown PLI call: $anyseq\nreg  [ 1:0] shamt    = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:19: Unsupported or unknown PLI call: $anyseq\nreg         f_xy     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:20: Unsupported or unknown PLI call: $anyseq\nreg         f_x1     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:21: Unsupported or unknown PLI call: $anyseq\nreg         f_x2     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:22: Unsupported or unknown PLI call: $anyseq\nreg         f_x4     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:23: Unsupported or unknown PLI call: $anyseq\nreg         f_yx     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:32: syntax error, unexpected '(', expecting property\n    restrict(onehot <= 1);\n             ^~~~~~\n%Error: Exiting due to 9 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module xc_sha3_ftb (

input clock,
input reset

);

reg  [31:0] rs1      = $anyseq;
reg  [31:0] rs2      = $anyseq;
reg  [ 1:0] shamt    = $anyseq;


reg         f_xy     = $anyseq;
reg         f_x1     = $anyseq;
reg         f_x2     = $anyseq;
reg         f_x4     = $anyseq;
reg         f_yx     = $anyseq;

reg [31:0] result       ;
reg [31:0] expectation  ;

wire [4:0] onehot = f_xy + f_x1 + f_x2 + f_x4 + f_yx;

always @(posedge clock) begin

    restrict(onehot <= 1);
    restrict(rs1[4:0] < 25);
    restrict(rs2[4:0] < 25);

    if(f_xy) begin

        assert(result == expectation);

    end else if (f_x1) begin
        
        assert(result == expectation);

    end else if (f_x2) begin
        
        assert(result == expectation);

    end else if (f_x4) begin
        
        assert(result == expectation);

    end else if (f_yx) begin
        
        assert(result == expectation);

    end


end





xc_sha3 i_sha3 (
.rs1   (rs1         ),
.rs2   (rs2         ),
.shamt (shamt       ),
.f_xy  (f_xy        ),
.f_x1  (f_x1        ),
.f_x2  (f_x2        ),
.f_x4  (f_x4        ),
.f_yx  (f_yx        ),
.result(result      )
);





fml_xc_sha3_checker i_sha3_checker (
.rs1   (rs1         ),
.rs2   (rs2         ),
.shamt (shamt       ),
.f_xy  (f_xy        ),
.f_x1  (f_x1        ),
.f_x2  (f_x2        ),
.f_x4  (f_x4        ),
.f_yx  (f_yx        ),
.result(expectation )
);


endmodule
module xc_sha3_ftb (

input clock,
input reset

);


reg  [31:0] rs1      = $anyseq;
reg  [31:0] rs2      = $anyseq;
reg  [ 1:0] shamt    = $anyseq;


reg         f_xy     = $anyseq;
reg         f_x1     = $anyseq;
reg         f_x2     = $anyseq;
reg         f_x4     = $anyseq;
reg         f_yx     = $anyseq;

reg [31:0] result       ;
reg [31:0] expectation  ;

wire [4:0] onehot = f_xy + f_x1 + f_x2 + f_x4 + f_yx;

always @(posedge clock) begin

    restrict(onehot <= 1);
    restrict(rs1[4:0] < 25);
    restrict(rs2[4:0] < 25);

    if(f_xy) begin

        assert(result == expectation);

    end else if (f_x1) begin
        
        assert(result == expectation);

    end else if (f_x2) begin
        
        assert(result == expectation);

    end else if (f_x4) begin
        
        assert(result == expectation);

    end else if (f_yx) begin
        
        assert(result == expectation);

    end


end





xc_sha3 i_sha3 (
.rs1   (rs1         ),
.rs2   (rs2         ),
.shamt (shamt       ),
.f_xy  (f_xy        ),
.f_x1  (f_x1        ),
.f_x2  (f_x2        ),
.f_x4  (f_x4        ),
.f_yx  (f_yx        ),
.result(result      )
);





fml_xc_sha3_checker i_sha3_checker (
.rs1   (rs1         ),
.rs2   (rs2         ),
.shamt (shamt       ),
.f_xy  (f_xy        ),
.f_x1  (f_x1        ),
.f_x2  (f_x2        ),
.f_x4  (f_x4        ),
.f_yx  (f_yx        ),
.result(expectation )
);


endmodule