data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/shift_left_2.v
data/verilator_xmls/423e2815-3ac6-45a0-8307-dee00f34d409.xml
module shift_left_2(in, shift);
parameter WIDTH_IN = 32;
parameter WIDTH_OUT = 32;

input[WIDTH_IN-1:0] in;
output[WIDTH_OUT-1:0] shift;

assign shift = in<<2;

endmodule
module shift_left_2(in, shift);

parameter WIDTH_IN = 32;
parameter WIDTH_OUT = 32;

input[WIDTH_IN-1:0] in;
output[WIDTH_OUT-1:0] shift;

assign shift = in<<2;

endmodule