data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer_reg4.v
 line:59: before: ";"
1: b'%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer_reg4.v:39: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                              : ... In instance muxer_reg4\n      out      <=  4\'b0; \n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/muxer_reg4.v:58: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                              : ... In instance muxer_reg4\n         default :  out  <= 4\'b0 ; \n                         ^~\n%Error: Exiting due to 2 warning(s)\n'
module muxer_reg4 #(
   parameter     RES = 14 
)
(

   input                 clk,rst,
   input      [  4-1: 0] sel,
   input      [RES-1: 0] in0,
   input      [RES-1: 0] in1,
   input      [RES-1: 0] in2,
   input      [RES-1: 0] in3,
   input      [RES-1: 0] in4,
   input      [RES-1: 0] in5,
   input      [RES-1: 0] in6,
   input      [RES-1: 0] in7,
   input      [RES-1: 0] in8,
   input      [RES-1: 0] in9,
   input      [RES-1: 0] in10,
   input      [RES-1: 0] in11,
   input      [RES-1: 0] in12,
   input      [RES-1: 0] in13,
   input      [RES-1: 0] in14,
   input      [RES-1: 0] in15,


   output reg [RES-1: 0] out
);



always @(posedge clk)
   if (rst)
      out      <=  4'b0; 
   else
      case (sel)
         4'd00   :  out  <= in0  ;
         4'd01   :  out  <= in1  ;
         4'd02   :  out  <= in2  ;
         4'd03   :  out  <= in3  ;
         4'd04   :  out  <= in4  ;
         4'd05   :  out  <= in5  ;
         4'd06   :  out  <= in6  ;
         4'd07   :  out  <= in7  ;
         4'd08   :  out  <= in8  ;
         4'd09   :  out  <= in9  ;
         4'd10   :  out  <= in10 ;
         4'd11   :  out  <= in11 ;
         4'd12   :  out  <= in12 ;
         4'd13   :  out  <= in13 ;
         4'd14   :  out  <= in14 ;
         4'd15   :  out  <= in15 ;
         default :  out  <= 4'b0 ; 
      endcase ;
   
 


endmodule
module muxer_reg4 #(
   parameter     RES = 14 
)
(

   input                 clk,rst,
   input      [  4-1: 0] sel,
   input      [RES-1: 0] in0,
   input      [RES-1: 0] in1,
   input      [RES-1: 0] in2,
   input      [RES-1: 0] in3,
   input      [RES-1: 0] in4,
   input      [RES-1: 0] in5,
   input      [RES-1: 0] in6,
   input      [RES-1: 0] in7,
   input      [RES-1: 0] in8,
   input      [RES-1: 0] in9,
   input      [RES-1: 0] in10,
   input      [RES-1: 0] in11,
   input      [RES-1: 0] in12,
   input      [RES-1: 0] in13,
   input      [RES-1: 0] in14,
   input      [RES-1: 0] in15,


   output reg [RES-1: 0] out
);




always @(posedge clk)
   if (rst)
      out      <=  4'b0; 
   else
      case (sel)
         4'd00   :  out  <= in0  ;
         4'd01   :  out  <= in1  ;
         4'd02   :  out  <= in2  ;
         4'd03   :  out  <= in3  ;
         4'd04   :  out  <= in4  ;
         4'd05   :  out  <= in5  ;
         4'd06   :  out  <= in6  ;
         4'd07   :  out  <= in7  ;
         4'd08   :  out  <= in8  ;
         4'd09   :  out  <= in9  ;
         4'd10   :  out  <= in10 ;
         4'd11   :  out  <= in11 ;
         4'd12   :  out  <= in12 ;
         4'd13   :  out  <= in13 ;
         4'd14   :  out  <= in14 ;
         4'd15   :  out  <= in15 ;
         default :  out  <= 4'b0 ; 
      endcase ;
   
 


endmodule