data/full_repos/permissive/193790231/lab02/lab02part03.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part03.v:20: Unsupported: Ignoring delay on this delayed statement.\n  sw={1\'b0, 4\'b0000, 4\'b0000}; #100;\n                               ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part03.v:21: Unsupported: Ignoring delay on this delayed statement.\n  sw={1\'b0, 4\'b0000, 4\'b0001}; #100;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part03.v:22: Unsupported: Ignoring delay on this delayed statement.\n  sw={1\'b0, 4\'b0001, 4\'b0000}; #100;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part03.v:23: Unsupported: Ignoring delay on this delayed statement.\n  sw={1\'b1, 4\'b0010, 4\'b0001}; #100;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part03.v:24: Unsupported: Ignoring delay on this delayed statement.\n  sw={1\'b1, 4\'b0100, 4\'b0001}; #100;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part03.v:25: Unsupported: Ignoring delay on this delayed statement.\n  sw={1\'b1, 4\'b1000, 4\'b1000}; #100;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab02/lab02part03.v:26: Unsupported: Ignoring delay on this delayed statement.\n  sw={1\'b1, 4\'b1111, 4\'b0000}; #100;\n                               ^\n%Error: data/full_repos/permissive/193790231/lab02/lab02part03.v:7: Cannot find file containing module: \'B_4xFullAdderRipple\'\n B_4xFullAdderRipple addAB(SW[8], SW[7:4], SW[3:0], LEDG[4], LEDG[3:0]);\n ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193790231/lab02,data/full_repos/permissive/193790231/B_4xFullAdderRipple\n             data/full_repos/permissive/193790231/lab02,data/full_repos/permissive/193790231/B_4xFullAdderRipple.v\n             data/full_repos/permissive/193790231/lab02,data/full_repos/permissive/193790231/B_4xFullAdderRipple.sv\n             B_4xFullAdderRipple\n             B_4xFullAdderRipple.v\n             B_4xFullAdderRipple.sv\n             obj_dir/B_4xFullAdderRipple\n             obj_dir/B_4xFullAdderRipple.v\n             obj_dir/B_4xFullAdderRipple.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lab02part03(
	input  [8:0]SW,
	output [8:0]LEDR,
	output [4:0]LEDG
);

	B_4xFullAdderRipple addAB(SW[8], SW[7:4], SW[3:0], LEDG[4], LEDG[3:0]);
	assign LEDR[8:0] = SW[8:0];
	
endmodule
module lab02part03(
	input  [8:0]SW,
	output [8:0]LEDR,
	output [4:0]LEDG
);


	B_4xFullAdderRipple addAB(SW[8], SW[7:4], SW[3:0], LEDG[4], LEDG[3:0]);
	assign LEDR[8:0] = SW[8:0];
	
endmodule