data/full_repos/permissive/188039952/Spartan 6/sendController.v
1: b'%Error: Cannot find file containing module: 6,data/full_repos/permissive/188039952\n        ... Looked in:\n             data/full_repos/permissive/188039952/Spartan/6,data/full_repos/permissive/188039952\n             data/full_repos/permissive/188039952/Spartan/6,data/full_repos/permissive/188039952.v\n             data/full_repos/permissive/188039952/Spartan/6,data/full_repos/permissive/188039952.sv\n             6,data/full_repos/permissive/188039952\n             6,data/full_repos/permissive/188039952.v\n             6,data/full_repos/permissive/188039952.sv\n             obj_dir/6,data/full_repos/permissive/188039952\n             obj_dir/6,data/full_repos/permissive/188039952.v\n             obj_dir/6,data/full_repos/permissive/188039952.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/188039952/Spartan\n%Error: Cannot find file containing module: 6/sendController.v\n%Error: Exiting due to 3 error(s)\n'
module sendController(
		input 		clk,
		input 		rst,
		input 		transmit,
		input [7:0] tx_byte,
		output 		dataClkP,
		output 		dataClkN,
		output 		dataP,
		output 		dataN,
		output 		syncOutP,
		output 		syncOutN,
		output reg 	is_transmitting
	);
	

	wire 			clkOut;
	reg 			dataOut 		= 1'b0;
	reg 			syncOut 		= 1'b0;
	reg [7:0] 	byteBuf 		= 8'd0;
	reg 			state 		= 1'b0;
	reg [2:0] 	bitCnt 		= 3'd7;
	reg [1:0] 	syncCnt 		= 2'd0;
	reg 			clkOutSel 	= 1'b0;
	

	localparam IDLE 			= 1'b0;
	localparam TRANS 			= 1'b1;
	

	OBUFDS #(
		.IOSTANDARD("DEFAULT")
	) OBUFDS_DATA (
		.O(dataP),
		.OB(dataN),
		.I(dataOut)
	);
	
	OBUFDS #(
		.IOSTANDARD("DEFAULT")
	) OBUFDS_CLOCK (
		.O(dataClkP),
		.OB(dataClkN),
		.I(clkOut)
	);
	
	OBUFDS #(
		.IOSTANDARD("DEFAULT")
	) IBUFDS_SYNC (
		.O(syncOutP),
		.OB(syncOutN),
		.I(syncOut)
	);
	
	assign clkOut = clkOutSel ? clk : 1'b0;
	

	always @(posedge clk) begin
		if (rst) begin
			dataOut 				<= 1'b0;
			syncOut 				<= 1'b0;
			byteBuf 				<= 8'd0;
			state 				<= 3'd0;
			is_transmitting 	<= 1'b0;
			bitCnt 				<= 3'd7;
			syncCnt 				<= 2'd0;
		clkOutSel 				<= 1'b0;
		end
		else begin
			case(state)
				IDLE : begin
					clkOutSel 	<= 1'b0;
					syncOut 		<= 1'b0;
					if (transmit == 1'b1) begin
						state 				<= TRANS;
						byteBuf 				<= tx_byte;
						is_transmitting 	<= 1'b1;
					end
					else begin
						state <= IDLE;
					end
				end
				TRANS : begin
					clkOutSel 	<= 1'b1;
					dataOut 		<= byteBuf[bitCnt];
					if (bitCnt == 3'd0) begin
						bitCnt 				<= 3'd7;
						state 				<= IDLE;
						is_transmitting 	<= 1'b0;
						if (syncCnt == 2'd3) begin
							syncCnt <= 2'd0;
							syncOut <= 1'b1;
						end
						else begin
							syncOut <= 1'b0;
							syncCnt <= syncCnt + 1;
						end
					end
					else begin
						syncOut 	<= 1'b0;
						bitCnt 	<= bitCnt - 1;
						state 	<= TRANS;
					end
				end
			endcase
		end
	end

endmodule
module sendController(
		input 		clk,
		input 		rst,
		input 		transmit,
		input [7:0] tx_byte,
		output 		dataClkP,
		output 		dataClkN,
		output 		dataP,
		output 		dataN,
		output 		syncOutP,
		output 		syncOutN,
		output reg 	is_transmitting
	);

	

	wire 			clkOut;
	reg 			dataOut 		= 1'b0;
	reg 			syncOut 		= 1'b0;
	reg [7:0] 	byteBuf 		= 8'd0;
	reg 			state 		= 1'b0;
	reg [2:0] 	bitCnt 		= 3'd7;
	reg [1:0] 	syncCnt 		= 2'd0;
	reg 			clkOutSel 	= 1'b0;
	

	localparam IDLE 			= 1'b0;
	localparam TRANS 			= 1'b1;
	

	OBUFDS #(
		.IOSTANDARD("DEFAULT")
	) OBUFDS_DATA (
		.O(dataP),
		.OB(dataN),
		.I(dataOut)
	);
	
	OBUFDS #(
		.IOSTANDARD("DEFAULT")
	) OBUFDS_CLOCK (
		.O(dataClkP),
		.OB(dataClkN),
		.I(clkOut)
	);
	
	OBUFDS #(
		.IOSTANDARD("DEFAULT")
	) IBUFDS_SYNC (
		.O(syncOutP),
		.OB(syncOutN),
		.I(syncOut)
	);
	
	assign clkOut = clkOutSel ? clk : 1'b0;
	

	always @(posedge clk) begin
		if (rst) begin
			dataOut 				<= 1'b0;
			syncOut 				<= 1'b0;
			byteBuf 				<= 8'd0;
			state 				<= 3'd0;
			is_transmitting 	<= 1'b0;
			bitCnt 				<= 3'd7;
			syncCnt 				<= 2'd0;
		clkOutSel 				<= 1'b0;
		end
		else begin
			case(state)
				IDLE : begin
					clkOutSel 	<= 1'b0;
					syncOut 		<= 1'b0;
					if (transmit == 1'b1) begin
						state 				<= TRANS;
						byteBuf 				<= tx_byte;
						is_transmitting 	<= 1'b1;
					end
					else begin
						state <= IDLE;
					end
				end
				TRANS : begin
					clkOutSel 	<= 1'b1;
					dataOut 		<= byteBuf[bitCnt];
					if (bitCnt == 3'd0) begin
						bitCnt 				<= 3'd7;
						state 				<= IDLE;
						is_transmitting 	<= 1'b0;
						if (syncCnt == 2'd3) begin
							syncCnt <= 2'd0;
							syncOut <= 1'b1;
						end
						else begin
							syncOut <= 1'b0;
							syncCnt <= syncCnt + 1;
						end
					end
					else begin
						syncOut 	<= 1'b0;
						bitCnt 	<= bitCnt - 1;
						state 	<= TRANS;
					end
				end
			endcase
		end
	end

endmodule