data/full_repos/permissive/146689564/whac_a_mole_v3.v
 line:77: before: "."
1: b'%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:708: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'frame\' generates 4 bits.\n                                                                         : ... In instance whac_a_mole_v3.u1\nassign en = ((q == frame) & enable) ? 1:0;  \n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:716: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'frame\' generates 4 bits.\n                                                                         : ... In instance whac_a_mole_v3.u1\n    if(q == frame)  \n         ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:440: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_1\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d0: y_posi = mole_1;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:441: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_2\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d1: y_posi = mole_2;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:442: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_3\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d2: y_posi = mole_3;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:443: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_4\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d3: y_posi = mole_4;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:444: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_1\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n    default: y_posi = mole_1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:447: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_1\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  else y_posi = mole_1;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:466: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n       mole_1 <= M_Y_S;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:467: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      mole_2 <= M_Y_S;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     mole_3 <= M_Y_S;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:469: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     mole_4 <= M_Y_S;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:475: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S1\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence1 <= S1;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:476: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S2\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence2 <= S2;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:477: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S3\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence3 <= S3;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:478: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S4\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence4 <= S4;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:501: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:496: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_1 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:509: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:504: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_2 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:517: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:512: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_3 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:525: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:520: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_4 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:531: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:535: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:539: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:543: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:547: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:551: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:555: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:559: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:568: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h33\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 == 7\'d51) \n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:573: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h33\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 == 7\'d51)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:578: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h34\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 < 7\'d52)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:583: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h34\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 < 7\'d52)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:640: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   x <= x_posi + counter[5:3];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:641: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   y <= y_posi + counter [2:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:653: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   x <= x_posi + counter[3:2];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:654: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   y <= y_posi + counter [1:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:669: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   x <= x_posi + counter[2:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:670: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 5 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   y <= y_posi + counter[7:3];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:230: Operator CASE expects 2 bits on the Case expression, but Case expression\'s VARREF \'difficulty\' generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.c0\n  case(difficulty)\n  ^~~~\n%Error: data/full_repos/permissive/146689564/whac_a_mole_v3.v:60: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146689564,data/full_repos/permissive/146689564/vga_adapter\n             data/full_repos/permissive/146689564,data/full_repos/permissive/146689564/vga_adapter.v\n             data/full_repos/permissive/146689564,data/full_repos/permissive/146689564/vga_adapter.sv\n             vga_adapter\n             vga_adapter.v\n             vga_adapter.sv\n             obj_dir/vga_adapter\n             obj_dir/vga_adapter.v\n             obj_dir/vga_adapter.sv\n%Error: data/full_repos/permissive/146689564/whac_a_mole_v3.v:88: Cannot find file containing module: \'keyboard_press_driver\'\n keyboard_press_driver KEYBOARD(\n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:139: Input port connection \'difficulty\' expects 1 bits on the pin connection, but pin connection\'s SEL generates 2 bits.\n                                                                         : ... In instance whac_a_mole_v3\n   .difficulty(SW[9:8]),\n    ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 48 warning(s)\n'
module datapath(
    input clk,
    input resetn,
    input draw_mole, draw_hammer, erase, clear, update, m,
    input [1:0]mole_id,
    input [3:0] h,
	 input valid,
	 input [7:0]outCode,
    output reg [7:0] x,
    output reg [6:0] y,
    output reg move,
    output reg [2:0]rgb,
    output reg [7:0]score
    );
    
    reg [7:0] x_counter;
    reg [6:0] y_counter;
    reg [7:0] counter;



    
    reg [7:0] x_posi;
    reg [6:0] y_posi;
    reg [7:0] mole_1, mole_2, mole_3, mole_4;
    reg [3:0] score_reg;
    reg [3:0] hammer, hammer_to_draw;

    reg [31:0] sequence1, sequence2, sequence3, sequence4;
    reg [3:0] direction;

    localparam  M_X_1 = 8'd19,
		M_X_2 = 8'd43,
		M_X_3 = 8'd67,
		M_X_4 = 8'd91,
		M_Y_S = 7'd59,
		M_Y_E = 7'd51,
		M_Y_H = 7'd47,
 		S1 = 24'b110000111100101100110000,
		S2 = 24'b110011000110011110110011,
		S3 = 24'b000110011011000111001100,
		S4 = 24'b001101100110110011011011;

   always @(*) begin
	case (mole_id)
	  2'd0: x_posi = M_X_1;
	  2'd1: x_posi = M_X_2;
	  2'd2: x_posi = M_X_3;
	  2'd3: x_posi = M_X_4;
     default: x_posi = M_X_1;
	endcase
   end

   always @(*) begin
	if(draw_hammer || erase)
	   y_posi = M_Y_H;
      else begin
		if(draw_mole) begin
			case (mole_id)
	  			2'd0: y_posi = mole_1;
	  			2'd1: y_posi = mole_2;
	  			2'd2: y_posi = mole_3;
	  			2'd3: y_posi = mole_4;
				default: y_posi = mole_1;
			endcase
		end
		else y_posi = mole_1;
		end
		end 

    always @ (posedge clk) begin
        if (resetn == 0) begin
	    x <= 8'd0;
	    y <= 7'd0;
       move <= 1'b0;
	    rgb <= 3'd0;
	    score <= 8'd0; 
	    
	    x_counter <= 8'd0;
 	    y_counter <= 7'd0;
    	 counter <= 8'd0;




       mole_1 <= M_Y_S;
 	    mole_2 <= M_Y_S;
	    mole_3 <= M_Y_S;
	    mole_4 <= M_Y_S;
	    
	    hammer <= 4'b0000;
	    hammer_to_draw <= 4'b0000;
	    score_reg <= 4'b0000;

	    sequence1 <= S1;
	    sequence2 <= S2;
	    sequence3 <= S3;
	    sequence4 <= S4;
	    direction <= 4'b0000;
        end

		  
		 if (m) begin
		     move<= 1'b0;
			  counter <= 8'd0;
		 end

	    if (update)begin
		   move <= 1'b0;
	    	hammer_to_draw <= hammer;
			hammer <= 4'd0;
			score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];
			score_reg <= 4'd0;
		

		if(mole_1 == M_Y_S)begin
			direction[0] <= sequence1[23];
			sequence1 <= sequence1 << 1'b1;
		end
		else begin
			if(mole_1 == M_Y_E)
			    direction[0] <= 1'b0;
		end
		if(mole_2 == M_Y_S)begin
			direction[1] <= sequence2[23];
			sequence2 <= sequence2 << 1'b1;
		end
		else begin
			if(mole_2 == M_Y_E)
			    direction[1] <= 1'b0;
		end
		if(mole_3 == M_Y_S)begin
			direction[2] <= sequence3[23];
			sequence3 <= sequence3 << 1'b1;
		end
		else begin
			if(mole_3 == M_Y_E)
			    direction[2] <= 1'b0;
		end
		if(mole_4 == M_Y_S)begin
			direction[3] <= sequence4[23];
			sequence4 <= sequence4 << 1'b1;
		end
		else begin
			if(mole_4 == M_Y_E)
			    direction[3] <= 1'b0;
		end
		

		if(direction[0] == 1) begin
			if(mole_1 > M_Y_E)
				mole_1 <= mole_1 -1'b1;
		end
		else if(direction[0] == 0)begin
			if(mole_1 < M_Y_S)
				mole_1 <= mole_1 + 1'b1;
		end
		if(direction[1] == 1) begin
			if(mole_2 > M_Y_E)
				mole_2 <= mole_2 -1'b1;
		end
		else if(direction[1] == 0)begin
			if(mole_2 < M_Y_S)
				mole_2 <= mole_2 + 1'b1;
		end
		if(direction[2] == 1) begin
			if(mole_3 > M_Y_E)
				mole_3 <= mole_3 -1'b1;
		end
		else if(direction[2] == 0) begin
			if(mole_3 < M_Y_S)
				mole_3 <= mole_3 + 1'b1;
		end
		if(direction[3] == 1) begin
			if(mole_4 > M_Y_E)
				mole_4 <= mole_4 - 1'b1;
		end
		else if(direction[3] == 0) begin
			if(mole_4 < M_Y_S)
				mole_4 <= mole_4 + 1'b1;
		end 	
	    end
	   
		
		if(update == 0)begin
		if(valid == 1 && outCode[7:0] == 8'h1b) begin
			hammer[0] <= 1'b1;
			if(mole_1 == 7'd51) 
				score_reg[0] <= 1'b1;
	    	end
	    	if(h[1] == 0) begin
			hammer[1] <= 1'b1;
			if(mole_2 == 7'd51)
			score_reg[1] <= 1'b1;
	    	end
	    	if(h[2] == 0) begin
			hammer[2] <= 1'b1;
			if(mole_3 < 7'd52)
				score_reg[2] <= 1'b1;
	    	end
	    	if(h[3] == 0) begin
			hammer[3] <= 1'b1;
			if(mole_4 < 7'd52)
				score_reg[3] <= 1'b1;
	    	end
		end

         	
	 
	    if (clear) begin
		if (y_counter < 60) begin
			rgb<= 3'b111;
		end 
		else begin
			rgb <= 3'b000;
		end

		x_counter <= x_counter + 8'd1;

		if (x_counter == 159)begin
			x_counter <= 0;
			y_counter <= y_counter+ 7'd1;
		end

		if (x_counter == 159 & y_counter == 119)begin
			y_counter <= 0;
			move <= 1'b1;
		end

		x<= x_counter;
		y<= y_counter;
	
	    end



	    if (draw_mole) begin

	    if (counter[5:0] == 6'b111111)begin
			move <= 1'b1;
			counter <= 8'd0;
		 end
		 rgb <= 3'b110;
		 if (counter[2:0] == 3'd0)begin
			if (counter[5:3] == 3'd0 ||counter[5:3] == 3'd3 ||counter[5:3] == 3'd4 ||counter[5:3] == 3'd7)
				rgb <= 3'b111;   	
		 end
		 if (counter[2:0] == 3'd2 || counter[2:0] == 3'd3)begin
			if (counter[5:3] == 3'd2 ||counter[5:3] == 3'd5)
				rgb <= 3'b000;   	
		 end
		 if (counter[2:0] == 3'd5)begin
			if (counter[5:3] == 3'd3 ||counter[5:3] == 3'd4)
				rgb <= 3'b100;   	
		 end
		 if (counter[2:0] == 3'd6 ||counter[2:0] == 3'd7)begin
				rgb <= 3'b000;   	
		 end
	    counter <= counter +8'd1;
		 x <= x_posi + counter[5:3];
		 y <= y_posi + counter [2:0];
	    end

	    if (draw_hammer) begin
	        if (counter[3:0] == 4'b1111)begin
				move <= 1'b1;
				counter <= 8'd0;
			end
			if (hammer_to_draw[mole_id] == 1'b1)
				rgb <= 3'b011;
			else rgb <= 3'b000;
			counter <= counter +8'd1;
			x <= x_posi + counter[3:2];
			y <= y_posi + counter [1:0];
	    end
	    
	    if(erase) begin
			if(counter[7:0] == 8'd159)begin
				move <= 1'b1;
				counter <= 8'd0;
			end
			if (counter[7:3] < 5'd13) begin
				rgb<= 3'b111;
			end
			else begin
			rgb <= 3'b000;
			end
			counter <= counter + 8'd1;
			x <= x_posi + counter[2:0];
			y <= y_posi + counter[7:3];
			end
      end

    
    
    
endmodule
module datapath(
    input clk,
    input resetn,
    input draw_mole, draw_hammer, erase, clear, update, m,
    input [1:0]mole_id,
    input [3:0] h,
	 input valid,
	 input [7:0]outCode,
    output reg [7:0] x,
    output reg [6:0] y,
    output reg move,
    output reg [2:0]rgb,
    output reg [7:0]score
    );

    
    reg [7:0] x_counter;
    reg [6:0] y_counter;
    reg [7:0] counter;



    
    reg [7:0] x_posi;
    reg [6:0] y_posi;
    reg [7:0] mole_1, mole_2, mole_3, mole_4;
    reg [3:0] score_reg;
    reg [3:0] hammer, hammer_to_draw;

    reg [31:0] sequence1, sequence2, sequence3, sequence4;
    reg [3:0] direction;

    localparam  M_X_1 = 8'd19,
		M_X_2 = 8'd43,
		M_X_3 = 8'd67,
		M_X_4 = 8'd91,
		M_Y_S = 7'd59,
		M_Y_E = 7'd51,
		M_Y_H = 7'd47,
 		S1 = 24'b110000111100101100110000,
		S2 = 24'b110011000110011110110011,
		S3 = 24'b000110011011000111001100,
		S4 = 24'b001101100110110011011011;

   always @(*) begin
	case (mole_id)
	  2'd0: x_posi = M_X_1;
	  2'd1: x_posi = M_X_2;
	  2'd2: x_posi = M_X_3;
	  2'd3: x_posi = M_X_4;
     default: x_posi = M_X_1;
	endcase
   end

   always @(*) begin
	if(draw_hammer || erase)
	   y_posi = M_Y_H;
      else begin
		if(draw_mole) begin
			case (mole_id)
	  			2'd0: y_posi = mole_1;
	  			2'd1: y_posi = mole_2;
	  			2'd2: y_posi = mole_3;
	  			2'd3: y_posi = mole_4;
				default: y_posi = mole_1;
			endcase
		end
		else y_posi = mole_1;
		end
		end 

    always @ (posedge clk) begin
        if (resetn == 0) begin
	    x <= 8'd0;
	    y <= 7'd0;
       move <= 1'b0;
	    rgb <= 3'd0;
	    score <= 8'd0; 
	    
	    x_counter <= 8'd0;
 	    y_counter <= 7'd0;
    	 counter <= 8'd0;




       mole_1 <= M_Y_S;
 	    mole_2 <= M_Y_S;
	    mole_3 <= M_Y_S;
	    mole_4 <= M_Y_S;
	    
	    hammer <= 4'b0000;
	    hammer_to_draw <= 4'b0000;
	    score_reg <= 4'b0000;

	    sequence1 <= S1;
	    sequence2 <= S2;
	    sequence3 <= S3;
	    sequence4 <= S4;
	    direction <= 4'b0000;
        end

		  
		 if (m) begin
		     move<= 1'b0;
			  counter <= 8'd0;
		 end

	    if (update)begin
		   move <= 1'b0;
	    	hammer_to_draw <= hammer;
			hammer <= 4'd0;
			score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];
			score_reg <= 4'd0;
		

		if(mole_1 == M_Y_S)begin
			direction[0] <= sequence1[23];
			sequence1 <= sequence1 << 1'b1;
		end
		else begin
			if(mole_1 == M_Y_E)
			    direction[0] <= 1'b0;
		end
		if(mole_2 == M_Y_S)begin
			direction[1] <= sequence2[23];
			sequence2 <= sequence2 << 1'b1;
		end
		else begin
			if(mole_2 == M_Y_E)
			    direction[1] <= 1'b0;
		end
		if(mole_3 == M_Y_S)begin
			direction[2] <= sequence3[23];
			sequence3 <= sequence3 << 1'b1;
		end
		else begin
			if(mole_3 == M_Y_E)
			    direction[2] <= 1'b0;
		end
		if(mole_4 == M_Y_S)begin
			direction[3] <= sequence4[23];
			sequence4 <= sequence4 << 1'b1;
		end
		else begin
			if(mole_4 == M_Y_E)
			    direction[3] <= 1'b0;
		end
		

		if(direction[0] == 1) begin
			if(mole_1 > M_Y_E)
				mole_1 <= mole_1 -1'b1;
		end
		else if(direction[0] == 0)begin
			if(mole_1 < M_Y_S)
				mole_1 <= mole_1 + 1'b1;
		end
		if(direction[1] == 1) begin
			if(mole_2 > M_Y_E)
				mole_2 <= mole_2 -1'b1;
		end
		else if(direction[1] == 0)begin
			if(mole_2 < M_Y_S)
				mole_2 <= mole_2 + 1'b1;
		end
		if(direction[2] == 1) begin
			if(mole_3 > M_Y_E)
				mole_3 <= mole_3 -1'b1;
		end
		else if(direction[2] == 0) begin
			if(mole_3 < M_Y_S)
				mole_3 <= mole_3 + 1'b1;
		end
		if(direction[3] == 1) begin
			if(mole_4 > M_Y_E)
				mole_4 <= mole_4 - 1'b1;
		end
		else if(direction[3] == 0) begin
			if(mole_4 < M_Y_S)
				mole_4 <= mole_4 + 1'b1;
		end 	
	    end
	   
		
		if(update == 0)begin
		if(valid == 1 && outCode[7:0] == 8'h1b) begin
			hammer[0] <= 1'b1;
			if(mole_1 == 7'd51) 
				score_reg[0] <= 1'b1;
	    	end
	    	if(h[1] == 0) begin
			hammer[1] <= 1'b1;
			if(mole_2 == 7'd51)
			score_reg[1] <= 1'b1;
	    	end
	    	if(h[2] == 0) begin
			hammer[2] <= 1'b1;
			if(mole_3 < 7'd52)
				score_reg[2] <= 1'b1;
	    	end
	    	if(h[3] == 0) begin
			hammer[3] <= 1'b1;
			if(mole_4 < 7'd52)
				score_reg[3] <= 1'b1;
	    	end
		end

         	
	 
	    if (clear) begin
		if (y_counter < 60) begin
			rgb<= 3'b111;
		end 
		else begin
			rgb <= 3'b000;
		end

		x_counter <= x_counter + 8'd1;

		if (x_counter == 159)begin
			x_counter <= 0;
			y_counter <= y_counter+ 7'd1;
		end

		if (x_counter == 159 & y_counter == 119)begin
			y_counter <= 0;
			move <= 1'b1;
		end

		x<= x_counter;
		y<= y_counter;
	
	    end



	    if (draw_mole) begin

	    if (counter[5:0] == 6'b111111)begin
			move <= 1'b1;
			counter <= 8'd0;
		 end
		 rgb <= 3'b110;
		 if (counter[2:0] == 3'd0)begin
			if (counter[5:3] == 3'd0 ||counter[5:3] == 3'd3 ||counter[5:3] == 3'd4 ||counter[5:3] == 3'd7)
				rgb <= 3'b111;   	
		 end
		 if (counter[2:0] == 3'd2 || counter[2:0] == 3'd3)begin
			if (counter[5:3] == 3'd2 ||counter[5:3] == 3'd5)
				rgb <= 3'b000;   	
		 end
		 if (counter[2:0] == 3'd5)begin
			if (counter[5:3] == 3'd3 ||counter[5:3] == 3'd4)
				rgb <= 3'b100;   	
		 end
		 if (counter[2:0] == 3'd6 ||counter[2:0] == 3'd7)begin
				rgb <= 3'b000;   	
		 end
	    counter <= counter +8'd1;
		 x <= x_posi + counter[5:3];
		 y <= y_posi + counter [2:0];
	    end

	    if (draw_hammer) begin
	        if (counter[3:0] == 4'b1111)begin
				move <= 1'b1;
				counter <= 8'd0;
			end
			if (hammer_to_draw[mole_id] == 1'b1)
				rgb <= 3'b011;
			else rgb <= 3'b000;
			counter <= counter +8'd1;
			x <= x_posi + counter[3:2];
			y <= y_posi + counter [1:0];
	    end
	    
	    if(erase) begin
			if(counter[7:0] == 8'd159)begin
				move <= 1'b1;
				counter <= 8'd0;
			end
			if (counter[7:3] < 5'd13) begin
				rgb<= 3'b111;
			end
			else begin
			rgb <= 3'b000;
			end
			counter <= counter + 8'd1;
			x <= x_posi + counter[2:0];
			y <= y_posi + counter[7:3];
			end
      end

    
    
    
endmodule