data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/design/d_trig.v
data/verilator_xmls/0a5bd9a5-192c-4d55-8f5f-9211055466f6.xml
module d_trig(
    D, DCLR, C, CLR,
    Q, notQ
    );


    parameter CLEAR_VAL   = 1;


    input wire D, DCLR, C, CLR;
    output wire Q, notQ;


    reg Q_reg = 0;



    always @(posedge C or posedge CLR) begin
        if(CLR == CLEAR_VAL)
            Q_reg <= DCLR;
        else
            Q_reg <= D;
    end

    assign Q    = Q_reg;
    assign notQ = !Q_reg;

endmodule
module d_trig(
    D, DCLR, C, CLR,
    Q, notQ
    );



    parameter CLEAR_VAL   = 1;


    input wire D, DCLR, C, CLR;
    output wire Q, notQ;


    reg Q_reg = 0;



    always @(posedge C or posedge CLR) begin
        if(CLR == CLEAR_VAL)
            Q_reg <= DCLR;
        else
            Q_reg <= D;
    end

    assign Q    = Q_reg;
    assign notQ = !Q_reg;

endmodule