data/full_repos/permissive/21108957/test/testbench_seq.sv
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1: b'%Error: data/full_repos/permissive/21108957/test/testbench_seq.sv:3: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n  logic clk, randomize, next, start_over;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/21108957/test/testbench_seq.sv:3: syntax error, unexpected \',\', expecting IDENTIFIER or \'=\' or do or final\n  logic clk, randomize, next, start_over;\n                      ^\n%Error: data/full_repos/permissive/21108957/test/testbench_seq.sv:6: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n  sequence_generator dut(.clk, .randomize, .next, .start_over, .seq);\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/21108957/test/testbench_seq.sv:6: syntax error, unexpected \',\'\n  sequence_generator dut(.clk, .randomize, .next, .start_over, .seq);\n                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/21108957/test/testbench_seq.sv:9: Unsupported: Ignoring delay on this delayed statement.\n    clk = 0; #5; clk = 1; #5;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21108957/test/testbench_seq.sv:9: Unsupported: Ignoring delay on this delayed statement.\n    clk = 0; #5; clk = 1; #5;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/21108957/test/testbench_seq.sv:14: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Error: data/full_repos/permissive/21108957/test/testbench_seq.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n    randomize = 1;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/21108957/test/testbench_seq.sv:16: syntax error, unexpected \'=\'\n    randomize = 1;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/21108957/test/testbench_seq.sv:20: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: data/full_repos/permissive/21108957/test/testbench_seq.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n    randomize = 0;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/21108957/test/testbench_seq.sv:22: syntax error, unexpected \'=\'\n    randomize = 0;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/21108957/test/testbench_seq.sv:26: Unsupported: Ignoring delay on this delayed statement.\n    #5000;\n    ^\n%Error: Exiting due to 8 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
  
  logic clk, randomize, next, start_over;
  logic [3:0] seq;
  
  sequence_generator dut(.clk, .randomize, .next, .start_over, .seq);
  
  always begin
    clk = 0; #5; clk = 1; #5;
  end
  
  initial begin
    
    #2;
    
    randomize = 1;
    next = 1;
    start_over = 1;
    
    #20;
    
    randomize = 0;
    start_over = 0;
    next = 1;
    
    #5000;
    
  end
  
endmodule
module testbench();

  
  logic clk, randomize, next, start_over;
  logic [3:0] seq;
  
  sequence_generator dut(.clk, .randomize, .next, .start_over, .seq);
  
  always begin
    clk = 0; #5; clk = 1; #5;
  end
  
  initial begin
    
    #2;
    
    randomize = 1;
    next = 1;
    start_over = 1;
    
    #20;
    
    randomize = 0;
    start_over = 0;
    next = 1;
    
    #5000;
    
  end
  
endmodule