data/full_repos/permissive/140999934/CPU/sram_cpu/wb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/140999934/CPU/sram_cpu/wb.v:63: syntax error, unexpected break, expecting IDENTIFIER or do or final\n wire break;\n      ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/sram_cpu/wb.v:86: syntax error, unexpected break, expecting TYPE-IDENTIFIER\n   break,\n   ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/sram_cpu/wb.v:230: syntax error, unexpected break, expecting TYPE-IDENTIFIER\n  if (break)       \n      ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/sram_cpu/wb.v:236: syntax error, unexpected '[', expecting IDENTIFIER\n   cause_r[6:2] <= 5'h4;\n          ^\n%Error: data/full_repos/permissive/140999934/CPU/sram_cpu/wb.v:240: syntax error, unexpected '[', expecting IDENTIFIER\n   cause_r[6:2] <= 5'h5;\n          ^\n%Error: data/full_repos/permissive/140999934/CPU/sram_cpu/wb.v:244: syntax error, unexpected '[', expecting IDENTIFIER\n   cause_r[6:2] <= 5'ha;\n          ^\n%Error: data/full_repos/permissive/140999934/CPU/sram_cpu/wb.v:248: syntax error, unexpected '[', expecting IDENTIFIER\n   cause_r[6:2] <= 5'hc;\n          ^\n%Error: data/full_repos/permissive/140999934/CPU/sram_cpu/wb.v:252: syntax error, unexpected '[', expecting IDENTIFIER\n      cause_r[9:8] <= mem_result[9:8];\n             ^\n%Error: data/full_repos/permissive/140999934/CPU/sram_cpu/wb.v:360: syntax error, unexpected break, expecting TYPE-IDENTIFIER\n assign exc_happened = syscall | break | (addr_exc[1:0]!=2'b00) | ov_exc | ri_exc;\n                                 ^~~~~\n%Error: Exiting due to 9 error(s)\n"
module wb(
	input wire     		WB_valid,
	input wire [160:0]	MEM_WB_bus_r,
	output wire [  3:0]	rf_wen,
	output wire [  4:0] rf_wdest,
	output wire [ 31:0] rf_wdata,
	output wire 		WB_over,


	input wire 		    clk,
	input wire 	       	resetn,
	output wire [ 32:0] exc_bus,
	output wire [  4:0] WB_wdest,
	output wire     	cancel,



	output wire [ 31:0] WB_pc,
	output wire [ 31:0] HI_data,
	output wire [ 31:0] LO_data
);

	wire [31:0] mem_result;
	wire [31:0] lo_result;
	wire 		hi_write;
	wire 		lo_write;


	wire [1:0] halfword;
	wire [3:0] wen;
	wire [4:0] wdest;


	wire mfhi;
	wire mflo;
	wire mtc0;
	wire mfc0;
	wire [7:0] cp0r_addr;
	wire syscall;
	wire eret;
	wire break;
	wire [1:0] addr_exc;
	wire ov_exc;
	wire ri_exc;
	wire is_ds;
	wire [31:0] badvaddr;


	wire [31:0] pc;
	assign {halfword,
	        wen,
			wdest,
			mem_result,
			lo_result,
			hi_write,
			lo_write,
			mfhi,
			mflo,
			mtc0,
			mfc0,
			cp0r_addr,
			syscall,
			eret,
			break,
			addr_exc,
			ov_exc,
			ri_exc,
			is_ds,
			badvaddr,
			pc} = MEM_WB_bus_r;



	reg [31:0] hi;
	reg [31:0] lo;

	always @(posedge clk) 
	begin
	    if (!resetn)
	    begin
	       hi <= 32'd0;
	    end
		else if (hi_write && WB_valid) 
		begin
			hi <= mem_result;
		end
	end

	always @(posedge clk) 
	begin
	    if (!resetn)
	    begin
	       lo <= 32'd0;
	    end
		else if (lo_write && WB_valid) 
		begin
			lo <= lo_result;
		end
	end





	wire [31:0] cp0r_status;
	wire [31:0] cp0r_cause;
	wire [31:0] cp0r_epc;
	wire [31:0] cp0r_badvaddr;
	wire [31:0] cp0r_count;
	wire [31:0] cp0r_compare;


	wire status_wen;
	wire epc_wen;
	wire cause_wen;
	wire count_wen;
	wire compare_wen;
	assign status_wen = mtc0 & (cp0r_addr=={5'd12,3'd0});
	assign epc_wen = mtc0 & (cp0r_addr=={5'd14,3'd0});
	assign cause_wen = mtc0 & (cp0r_addr=={5'd13,3'd0});
	assign count_wen = mtc0 & (cp0r_addr=={5'd9,3'd0});
	assign compare_wen = mtc0 & (cp0r_addr=={5'd11,3'd0});


	wire [31:0] cp0r_rdata;
	assign cp0r_rdata = (cp0r_addr=={5'd8,3'd0}) ? cp0r_badvaddr :
	                    (cp0r_addr=={5'd9,3'd0}) ? cp0r_count :
	                    (cp0r_addr=={5'd11,3'd0}) ? cp0r_compare :
	                    (cp0r_addr=={5'd12,3'd0}) ? cp0r_status :
						(cp0r_addr=={5'd13,3'd0}) ? cp0r_cause :
						(cp0r_addr=={5'd14,3'd0}) ? cp0r_epc : 32'd0;




	reg [31:0] status_r;
	assign cp0r_status = status_r;
	always @(posedge clk) 
	begin
		if (!resetn) 
		begin
			status_r[31:23] <= 9'd0;
			status_r[22] <= 1'b1;
			status_r[21:16] <= 6'd0;
			status_r[7:0] <= 8'd0;
		end
		else if (eret)
		begin
		    status_r[1] <= 1'b0;
		end
		else if ((cp0r_status[0] && ~cp0r_status[1] && 
                    ( (cp0r_cause[15] & cp0r_status[15])
                    | (cp0r_cause[14] & cp0r_status[14])
                    | (cp0r_cause[13] & cp0r_status[13])
                    | (cp0r_cause[12] & cp0r_status[12])
                    | (cp0r_cause[11] & cp0r_status[11])
                    | (cp0r_cause[10] & cp0r_status[10])
                    | (cp0r_cause[9] & cp0r_status[9])
                    | (cp0r_cause[8] & cp0r_status[8]))) | exc_happened) 
		begin
			status_r[1] <= 1'b1;
		end
		else if (status_wen && WB_valid)
		begin
			status_r <= {
							9'd0,
							1'd1,
							6'd0,
							mem_result[15:8],
							6'd0,
							mem_result[1:0]
						};
		end
	end




	reg [31:0] cause_r;
	assign cp0r_cause = cause_r;
	always @(posedge clk) 
	begin
		if (!resetn)
		begin
			cause_r[31:7] <= 25'd0;
			cause_r[1:0] <= 2'd0;
		end

		cause_r[15] <= cause_r[30];
		if ((exc_happened | int_happened) & WB_over)
		begin
			cause_r[31] <= is_ds;
		end
		if (compare_wen && WB_valid)
		begin
		    cause_r[30] <= 1'b0;
		end 
		else if (count_r == compare_r)
		begin
			cause_r[30] <= 1'b1;
			cause_r[15] <= cause_r[30];
			cause_r[6:2] <= 5'h0;
		end
		if (syscall)
		begin
			cause_r[6:2] <= 5'h8;
		end
		if (break)
		begin
			cause_r[6:2] <= 5'h9;
		end
		if (addr_exc[1] == 1'b1)
		begin
			cause_r[6:2] <= 5'h4;
		end
		if (addr_exc[1:0] == 2'b01)
		begin
			cause_r[6:2] <= 5'h5;
		end
		if (ri_exc)
		begin 				
			cause_r[6:2] <= 5'ha;
		end
		if (ov_exc)
		begin 				
			cause_r[6:2] <= 5'hc;
		end
		if (cause_wen && WB_valid)
		begin
		    cause_r[9:8] <= mem_result[9:8];
		end
	end




	reg [31:0] epc_r;
	assign cp0r_epc = epc_r;
	always @(posedge clk)
	begin
		if (exc_valid && is_ds)
		begin
		   epc_r <= pc - 32'd4;
		end
		else if (exc_valid && ~is_ds)
		begin
			epc_r <= pc;
		end
		else if (epc_wen && WB_valid)
		begin
		   epc_r <= mem_result;
		end
	end



	reg [31:0] badvaddr_r;
	assign cp0r_badvaddr = badvaddr_r;
	always @(posedge clk) 
	begin
		if ((addr_exc[1:0] == 2'b10) || (addr_exc[1:0] == 2'b01))
		begin
			badvaddr_r <= badvaddr;
		end
		else if (addr_exc[1:0] == 2'b11)
		begin
		    badvaddr_r <= pc;
		end
	end



	reg [31:0] count_r;
	reg count0;
	assign cp0r_count = count_r;
	always @(posedge clk) 
	begin
	    if (!resetn)
	    begin
	       count0 <= 1'b0;
	    end
	    else if (count0)
	    begin
	       count0 <= 1'b0;
           count_r <= count_r + 1'b1;
	    end
	    else if (~count0)
	    begin
	       count0 <= 1'b1;
	    end
		if (count_wen && WB_valid)
		begin
			count_r <= mem_result;
		end
	end



	reg [31:0] compare_r;
	assign cp0r_compare = compare_r;
	always @(posedge clk) 
	begin
		if (compare_wen && WB_valid)
		begin
			compare_r <= mem_result;
		end
	end
   

   assign cancel = exc_valid;

   
   





	assign WB_over = WB_valid;



	assign rf_wen = wen & {4{WB_over}} & {4{(~exc_happened)}};
	assign rf_wdest = wdest;
	assign rf_wdata = mfhi ? hi :
					  mflo ? lo :
					  mfc0 ? cp0r_rdata : 
					  halfword[1] ? {{16{mem_result[15]}},mem_result[15:0]} :
					  halfword[0] ? {16'd0,mem_result[15:0]} :  
					  mem_result;



	wire 	    exc_happened;
	reg         int_happened;
	wire 		exc_valid;
	wire [31:0] exc_pc;
	assign exc_happened = syscall | break | (addr_exc[1:0]!=2'b00) | ov_exc | ri_exc;
	always @(posedge clk)
	begin
	    if (!resetn)
	    begin
	        int_happened <= 1'b0;
	    end
	    else if (cp0r_status[0] && ~cp0r_status[1] && 
	        ( (cp0r_cause[15] & cp0r_status[15])
            | (cp0r_cause[14] & cp0r_status[14])
            | (cp0r_cause[13] & cp0r_status[13])
            | (cp0r_cause[12] & cp0r_status[12])
            | (cp0r_cause[11] & cp0r_status[11])
            | (cp0r_cause[10] & cp0r_status[10])
            | (cp0r_cause[9] & cp0r_status[9])
            | (cp0r_cause[8] & cp0r_status[8])))
        begin
	        int_happened <= 1'b1;
	    end
	    else if (exc_valid)
	    begin
	        int_happened <= 1'b0;
	    end
	end

	assign exc_valid = ((exc_happened | eret | int_happened) & WB_valid);


	assign exc_pc = (exc_happened | int_happened) ? `EXC_ENTER_ADDR : cp0r_epc;
	assign exc_bus = {exc_valid,exc_pc};




	assign WB_wdest = rf_wdest & {5{WB_valid}};



	assign WB_pc = pc;
	assign HI_data = hi;
	assign LO_data = lo;

endmodule
module wb(
	input wire     		WB_valid,
	input wire [160:0]	MEM_WB_bus_r,
	output wire [  3:0]	rf_wen,
	output wire [  4:0] rf_wdest,
	output wire [ 31:0] rf_wdata,
	output wire 		WB_over,


	input wire 		    clk,
	input wire 	       	resetn,
	output wire [ 32:0] exc_bus,
	output wire [  4:0] WB_wdest,
	output wire     	cancel,



	output wire [ 31:0] WB_pc,
	output wire [ 31:0] HI_data,
	output wire [ 31:0] LO_data
);


	wire [31:0] mem_result;
	wire [31:0] lo_result;
	wire 		hi_write;
	wire 		lo_write;


	wire [1:0] halfword;
	wire [3:0] wen;
	wire [4:0] wdest;


	wire mfhi;
	wire mflo;
	wire mtc0;
	wire mfc0;
	wire [7:0] cp0r_addr;
	wire syscall;
	wire eret;
	wire break;
	wire [1:0] addr_exc;
	wire ov_exc;
	wire ri_exc;
	wire is_ds;
	wire [31:0] badvaddr;


	wire [31:0] pc;
	assign {halfword,
	        wen,
			wdest,
			mem_result,
			lo_result,
			hi_write,
			lo_write,
			mfhi,
			mflo,
			mtc0,
			mfc0,
			cp0r_addr,
			syscall,
			eret,
			break,
			addr_exc,
			ov_exc,
			ri_exc,
			is_ds,
			badvaddr,
			pc} = MEM_WB_bus_r;



	reg [31:0] hi;
	reg [31:0] lo;

	always @(posedge clk) 
	begin
	    if (!resetn)
	    begin
	       hi <= 32'd0;
	    end
		else if (hi_write && WB_valid) 
		begin
			hi <= mem_result;
		end
	end

	always @(posedge clk) 
	begin
	    if (!resetn)
	    begin
	       lo <= 32'd0;
	    end
		else if (lo_write && WB_valid) 
		begin
			lo <= lo_result;
		end
	end





	wire [31:0] cp0r_status;
	wire [31:0] cp0r_cause;
	wire [31:0] cp0r_epc;
	wire [31:0] cp0r_badvaddr;
	wire [31:0] cp0r_count;
	wire [31:0] cp0r_compare;


	wire status_wen;
	wire epc_wen;
	wire cause_wen;
	wire count_wen;
	wire compare_wen;
	assign status_wen = mtc0 & (cp0r_addr=={5'd12,3'd0});
	assign epc_wen = mtc0 & (cp0r_addr=={5'd14,3'd0});
	assign cause_wen = mtc0 & (cp0r_addr=={5'd13,3'd0});
	assign count_wen = mtc0 & (cp0r_addr=={5'd9,3'd0});
	assign compare_wen = mtc0 & (cp0r_addr=={5'd11,3'd0});


	wire [31:0] cp0r_rdata;
	assign cp0r_rdata = (cp0r_addr=={5'd8,3'd0}) ? cp0r_badvaddr :
	                    (cp0r_addr=={5'd9,3'd0}) ? cp0r_count :
	                    (cp0r_addr=={5'd11,3'd0}) ? cp0r_compare :
	                    (cp0r_addr=={5'd12,3'd0}) ? cp0r_status :
						(cp0r_addr=={5'd13,3'd0}) ? cp0r_cause :
						(cp0r_addr=={5'd14,3'd0}) ? cp0r_epc : 32'd0;




	reg [31:0] status_r;
	assign cp0r_status = status_r;
	always @(posedge clk) 
	begin
		if (!resetn) 
		begin
			status_r[31:23] <= 9'd0;
			status_r[22] <= 1'b1;
			status_r[21:16] <= 6'd0;
			status_r[7:0] <= 8'd0;
		end
		else if (eret)
		begin
		    status_r[1] <= 1'b0;
		end
		else if ((cp0r_status[0] && ~cp0r_status[1] && 
                    ( (cp0r_cause[15] & cp0r_status[15])
                    | (cp0r_cause[14] & cp0r_status[14])
                    | (cp0r_cause[13] & cp0r_status[13])
                    | (cp0r_cause[12] & cp0r_status[12])
                    | (cp0r_cause[11] & cp0r_status[11])
                    | (cp0r_cause[10] & cp0r_status[10])
                    | (cp0r_cause[9] & cp0r_status[9])
                    | (cp0r_cause[8] & cp0r_status[8]))) | exc_happened) 
		begin
			status_r[1] <= 1'b1;
		end
		else if (status_wen && WB_valid)
		begin
			status_r <= {
							9'd0,
							1'd1,
							6'd0,
							mem_result[15:8],
							6'd0,
							mem_result[1:0]
						};
		end
	end




	reg [31:0] cause_r;
	assign cp0r_cause = cause_r;
	always @(posedge clk) 
	begin
		if (!resetn)
		begin
			cause_r[31:7] <= 25'd0;
			cause_r[1:0] <= 2'd0;
		end

		cause_r[15] <= cause_r[30];
		if ((exc_happened | int_happened) & WB_over)
		begin
			cause_r[31] <= is_ds;
		end
		if (compare_wen && WB_valid)
		begin
		    cause_r[30] <= 1'b0;
		end 
		else if (count_r == compare_r)
		begin
			cause_r[30] <= 1'b1;
			cause_r[15] <= cause_r[30];
			cause_r[6:2] <= 5'h0;
		end
		if (syscall)
		begin
			cause_r[6:2] <= 5'h8;
		end
		if (break)
		begin
			cause_r[6:2] <= 5'h9;
		end
		if (addr_exc[1] == 1'b1)
		begin
			cause_r[6:2] <= 5'h4;
		end
		if (addr_exc[1:0] == 2'b01)
		begin
			cause_r[6:2] <= 5'h5;
		end
		if (ri_exc)
		begin 				
			cause_r[6:2] <= 5'ha;
		end
		if (ov_exc)
		begin 				
			cause_r[6:2] <= 5'hc;
		end
		if (cause_wen && WB_valid)
		begin
		    cause_r[9:8] <= mem_result[9:8];
		end
	end




	reg [31:0] epc_r;
	assign cp0r_epc = epc_r;
	always @(posedge clk)
	begin
		if (exc_valid && is_ds)
		begin
		   epc_r <= pc - 32'd4;
		end
		else if (exc_valid && ~is_ds)
		begin
			epc_r <= pc;
		end
		else if (epc_wen && WB_valid)
		begin
		   epc_r <= mem_result;
		end
	end



	reg [31:0] badvaddr_r;
	assign cp0r_badvaddr = badvaddr_r;
	always @(posedge clk) 
	begin
		if ((addr_exc[1:0] == 2'b10) || (addr_exc[1:0] == 2'b01))
		begin
			badvaddr_r <= badvaddr;
		end
		else if (addr_exc[1:0] == 2'b11)
		begin
		    badvaddr_r <= pc;
		end
	end



	reg [31:0] count_r;
	reg count0;
	assign cp0r_count = count_r;
	always @(posedge clk) 
	begin
	    if (!resetn)
	    begin
	       count0 <= 1'b0;
	    end
	    else if (count0)
	    begin
	       count0 <= 1'b0;
           count_r <= count_r + 1'b1;
	    end
	    else if (~count0)
	    begin
	       count0 <= 1'b1;
	    end
		if (count_wen && WB_valid)
		begin
			count_r <= mem_result;
		end
	end



	reg [31:0] compare_r;
	assign cp0r_compare = compare_r;
	always @(posedge clk) 
	begin
		if (compare_wen && WB_valid)
		begin
			compare_r <= mem_result;
		end
	end
   

   assign cancel = exc_valid;

   
   





	assign WB_over = WB_valid;



	assign rf_wen = wen & {4{WB_over}} & {4{(~exc_happened)}};
	assign rf_wdest = wdest;
	assign rf_wdata = mfhi ? hi :
					  mflo ? lo :
					  mfc0 ? cp0r_rdata : 
					  halfword[1] ? {{16{mem_result[15]}},mem_result[15:0]} :
					  halfword[0] ? {16'd0,mem_result[15:0]} :  
					  mem_result;



	wire 	    exc_happened;
	reg         int_happened;
	wire 		exc_valid;
	wire [31:0] exc_pc;
	assign exc_happened = syscall | break | (addr_exc[1:0]!=2'b00) | ov_exc | ri_exc;
	always @(posedge clk)
	begin
	    if (!resetn)
	    begin
	        int_happened <= 1'b0;
	    end
	    else if (cp0r_status[0] && ~cp0r_status[1] && 
	        ( (cp0r_cause[15] & cp0r_status[15])
            | (cp0r_cause[14] & cp0r_status[14])
            | (cp0r_cause[13] & cp0r_status[13])
            | (cp0r_cause[12] & cp0r_status[12])
            | (cp0r_cause[11] & cp0r_status[11])
            | (cp0r_cause[10] & cp0r_status[10])
            | (cp0r_cause[9] & cp0r_status[9])
            | (cp0r_cause[8] & cp0r_status[8])))
        begin
	        int_happened <= 1'b1;
	    end
	    else if (exc_valid)
	    begin
	        int_happened <= 1'b0;
	    end
	end

	assign exc_valid = ((exc_happened | eret | int_happened) & WB_valid);


	assign exc_pc = (exc_happened | int_happened) ? `EXC_ENTER_ADDR : cp0r_epc;
	assign exc_bus = {exc_valid,exc_pc};




	assign WB_wdest = rf_wdest & {5{WB_valid}};



	assign WB_pc = pc;
	assign HI_data = hi;
	assign LO_data = lo;

endmodule