data/full_repos/permissive/17099167/system/hardware/cores/arbiter/arbiter_bytebus.v
None: at end of input
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/arbiter/arbiter_bytebus.v:47: Cannot find include file: orpsoc-defines.v\n`include "orpsoc-defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/arbiter,data/full_repos/permissive/17099167/orpsoc-defines.v\n             data/full_repos/permissive/17099167/system/hardware/cores/arbiter,data/full_repos/permissive/17099167/orpsoc-defines.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/arbiter,data/full_repos/permissive/17099167/orpsoc-defines.v.sv\n             orpsoc-defines.v\n             orpsoc-defines.v.v\n             orpsoc-defines.v.sv\n             obj_dir/orpsoc-defines.v\n             obj_dir/orpsoc-defines.v.v\n             obj_dir/orpsoc-defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module arbiter_bytebus
  (


   wbm0_adr_o,
   wbm0_dat_o,
   wbm0_sel_o,
   wbm0_we_o,
   wbm0_cyc_o,
   wbm0_stb_o,
   wbm0_cti_o,
   wbm0_bte_o,
   wbm0_dat_i,
   wbm0_ack_i,
   wbm0_err_i,
   wbm0_rty_i,



   wbs0_adr_i,
   wbs0_dat_i,
   wbs0_we_i,
   wbs0_cyc_i,
   wbs0_stb_i,
   wbs0_cti_i,
   wbs0_bte_i,
   wbs0_dat_o,
   wbs0_ack_o,
   wbs0_err_o,
   wbs0_rty_o,



   wbs1_adr_i,
   wbs1_dat_i,
   wbs1_we_i,
   wbs1_cyc_i,
   wbs1_stb_i,
   wbs1_cti_i,
   wbs1_bte_i,
   wbs1_dat_o,
   wbs1_ack_o,
   wbs1_err_o,
   wbs1_rty_o,



   wbs2_adr_i,
   wbs2_dat_i,
   wbs2_we_i,
   wbs2_cyc_i,
   wbs2_stb_i,
   wbs2_cti_i,
   wbs2_bte_i,
   wbs2_dat_o,
   wbs2_ack_o,
   wbs2_err_o,
   wbs2_rty_o,



   wbs3_adr_i,
   wbs3_dat_i,
   wbs3_we_i,
   wbs3_cyc_i,
   wbs3_stb_i,
   wbs3_cti_i,
   wbs3_bte_i,
   wbs3_dat_o,
   wbs3_ack_o,
   wbs3_err_o,
   wbs3_rty_o,



   wbs4_adr_i,
   wbs4_dat_i,
   wbs4_we_i,
   wbs4_cyc_i,
   wbs4_stb_i,
   wbs4_cti_i,
   wbs4_bte_i,
   wbs4_dat_o,
   wbs4_ack_o,
   wbs4_err_o,
   wbs4_rty_o,

   
   wb_clk, wb_rst
   );
   

   parameter wb_dat_width = 32;
   parameter wbs_dat_width = 8;
   parameter wb_adr_width = 32;

   parameter wb_addr_match_width = 8;

   parameter wb_num_slaves = 20;


   
   parameter slave0_adr =  8'h00; 
   parameter slave1_adr =  8'h00; 
   parameter slave2_adr =  8'h00; 
   parameter slave3_adr =  8'h00; 
   parameter slave4_adr =  8'h00; 
   parameter slave5_adr =  8'h00; 
   parameter slave6_adr =  8'h00; 
   parameter slave7_adr =  8'h00; 
   parameter slave8_adr =  8'h00; 
   parameter slave9_adr =  8'h00; 
   parameter slave10_adr = 8'h00;
   parameter slave11_adr = 8'h00;
   parameter slave12_adr = 8'h00;
   parameter slave13_adr = 8'h00;
   parameter slave14_adr = 8'h00;
   parameter slave15_adr = 8'h00;
   parameter slave16_adr = 8'h00;
   parameter slave17_adr = 8'h00;
   parameter slave18_adr = 8'h00;
   parameter slave19_adr = 8'h00;
   

`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
   
   input wb_clk;
   input wb_rst;
   

   input [wb_adr_width-1:0] wbm0_adr_o;
   input [wb_dat_width-1:0] wbm0_dat_o;
   input [3:0] 		    wbm0_sel_o;
   input 		    wbm0_we_o;
   input 		    wbm0_cyc_o;
   input 		    wbm0_stb_o;
   input [2:0] 		    wbm0_cti_o;
   input [1:0] 		    wbm0_bte_o;
   output [wb_dat_width-1:0] wbm0_dat_i;   
   output 		     wbm0_ack_i;
   output 		     wbm0_err_i;
   output 		     wbm0_rty_i;   
   
   


   output [wb_adr_width-1:0] wbs0_adr_i;
   output [wbs_dat_width-1:0] wbs0_dat_i;
   output 		     wbs0_we_i;
   output 		     wbs0_cyc_i;
   output 		     wbs0_stb_i;
   output [2:0] 	     wbs0_cti_i;
   output [1:0] 	     wbs0_bte_i;
   input [wbs_dat_width-1:0]  wbs0_dat_o;
   input 		     wbs0_ack_o;
   input 		     wbs0_err_o;
   input 		     wbs0_rty_o;
   


   output [wb_adr_width-1:0] wbs1_adr_i;
   output [wbs_dat_width-1:0] wbs1_dat_i;
   output 		     wbs1_we_i;
   output 		     wbs1_cyc_i;
   output 		     wbs1_stb_i;
   output [2:0] 	     wbs1_cti_i;
   output [1:0] 	     wbs1_bte_i;
   input [wbs_dat_width-1:0]  wbs1_dat_o;
   input 		     wbs1_ack_o;
   input 		     wbs1_err_o;
   input 		     wbs1_rty_o;
   


   output [wb_adr_width-1:0] wbs2_adr_i;
   output [wbs_dat_width-1:0] wbs2_dat_i;
   output 		     wbs2_we_i;
   output 		     wbs2_cyc_i;
   output 		     wbs2_stb_i;
   output [2:0] 	     wbs2_cti_i;
   output [1:0] 	     wbs2_bte_i;
   input [wbs_dat_width-1:0]  wbs2_dat_o;
   input 		     wbs2_ack_o;
   input 		     wbs2_err_o;
   input 		     wbs2_rty_o;
   


   output [wb_adr_width-1:0] wbs3_adr_i;
   output [wbs_dat_width-1:0] wbs3_dat_i;
   output 		     wbs3_we_i;
   output 		     wbs3_cyc_i;
   output 		     wbs3_stb_i;
   output [2:0] 	     wbs3_cti_i;
   output [1:0] 	     wbs3_bte_i;
   input [wbs_dat_width-1:0]  wbs3_dat_o;
   input 		     wbs3_ack_o;
   input 		     wbs3_err_o;
   input 		     wbs3_rty_o;
   


   output [wb_adr_width-1:0] wbs4_adr_i;
   output [wbs_dat_width-1:0] wbs4_dat_i;
   output 		     wbs4_we_i;
   output 		     wbs4_cyc_i;
   output 		     wbs4_stb_i;
   output [2:0] 	     wbs4_cti_i;
   output [1:0] 	     wbs4_bte_i;
   input [wbs_dat_width-1:0]  wbs4_dat_o;
   input 		     wbs4_ack_o;
   input 		     wbs4_err_o;
   input 		     wbs4_rty_o;
   


   reg 		     watchdog_err;
   

   wire [wb_adr_width-1:0]   wbm_adr_o;
   wire [wbs_dat_width-1:0]  wbm_dat_o;
   wire [3:0] 		     wbm_sel_o;
   wire 		     wbm_we_o;
   wire 		     wbm_cyc_o;
   wire 		     wbm_stb_o;
   wire [2:0] 		     wbm_cti_o;
   wire [1:0] 		     wbm_bte_o;
   
   wire [wbs_dat_width-1:0]   wbm_dat_byte_i;   
   wire 		     wbm_ack_i;
   wire 		     wbm_err_i;
   wire 		     wbm_rty_i;   

   

   assign wbm_adr_o = wbm0_adr_o;



   assign wbm_dat_o = wbm0_sel_o[3] ? wbm0_dat_o[31:24] :
		      wbm0_sel_o[2] ? wbm0_dat_o[23:16] :
		      wbm0_sel_o[1] ? wbm0_dat_o[15:8] :
		      wbm0_dat_o[7:0];
   
   assign wbm_we_o = wbm0_we_o;
   
   assign wbm_cyc_o = wbm0_stb_o;
   
   assign wbm_stb_o = wbm0_stb_o;


   assign wbm_cti_o = wbm0_cti_o;
   
   assign wbm_bte_o = wbm0_bte_o;


   assign wbm0_dat_i = (wbm0_sel_o[3]) ? {wbm_dat_byte_i, 24'd0} :
		       (wbm0_sel_o[2]) ? {8'd0, wbm_dat_byte_i, 16'd0} :
		       (wbm0_sel_o[1]) ? {16'd0, wbm_dat_byte_i, 8'd0} :
	               {24'd0, wbm_dat_byte_i};

   assign wbm0_ack_i = wbm_ack_i;
   assign wbm0_err_i = wbm_err_i;
   assign wbm0_rty_i = wbm_rty_i;

`ifdef ARBITER_BYTEBUS_WATCHDOG
   reg [`ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer;
   reg 			     wbm_stb_r;
   wire 		     wbm_stb_edge;

   always @(posedge wb_clk)
     wbm_stb_r <= wbm_stb_o;

   assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);
   

   always @(posedge wb_clk)
     if (wb_rst) watchdog_timer <= 0;
     else if (wbm_ack_i)
       watchdog_timer <= 0;
     else if (wbm_stb_edge)
       watchdog_timer <= 1;
     else if (|watchdog_timer)
       watchdog_timer <= watchdog_timer + 1;

   always @(posedge wb_clk) 
     watchdog_err <= (&watchdog_timer);
   
`else
   always @(posedge wb_clk) 
     watchdog_err <= 0;
      
`endif

   

   wire [wb_adr_width-1:0]   wbs_adr_i;
   wire [wbs_dat_width-1:0]  wbs_dat_i;
   wire 		     wbs_we_i;
   wire 		     wbs_cyc_i;
   wire 		     wbs_stb_i;
   wire [2:0] 		     wbs_cti_i;
   wire [1:0] 		     wbs_bte_i;
   wire [wbs_dat_width-1:0]  wbs_dat_o;
   wire 		     wbs_ack_o;
   wire 		     wbs_err_o;
   wire 		     wbs_rty_o;

   

   wire [wb_num_slaves-1:0]  wb_slave_sel;
   

   wire [wbs_dat_width-1:0]  wbs_dat_o_mux_i [0:wb_num_slaves-1];
   wire 		     wbs_ack_o_mux_i [0:wb_num_slaves-1];
   wire 		     wbs_err_o_mux_i [0:wb_num_slaves-1];
   wire 		     wbs_rty_o_mux_i [0:wb_num_slaves-1];


   assign wb_slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave0_adr;
   assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
   assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
   assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
   assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;






   assign wbs0_adr_i = wbm_adr_o;
   assign wbs0_dat_i = wbm_dat_o;
   assign wbs0_cyc_i = wbm_cyc_o & wb_slave_sel[0];
   assign wbs0_stb_i = wbm_stb_o & wb_slave_sel[0];   
   assign  wbs0_we_i =  wbm_we_o;
   assign wbs0_cti_i = wbm_cti_o;
   assign wbs0_bte_i = wbm_bte_o;
   assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
   assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel[0];
   assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel[0];
   assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel[0];



   assign wbs1_adr_i = wbm_adr_o;
   assign wbs1_dat_i = wbm_dat_o;
   assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel[1];
   assign wbs1_stb_i = wbm_stb_o & wb_slave_sel[1];   
   assign  wbs1_we_i =  wbm_we_o;
   assign wbs1_cti_i = wbm_cti_o;
   assign wbs1_bte_i = wbm_bte_o;
   assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
   assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel[1];
   assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel[1];
   assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel[1];



   assign wbs2_adr_i = wbm_adr_o;
   assign wbs2_dat_i = wbm_dat_o;
   assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel[2];
   assign wbs2_stb_i = wbm_stb_o & wb_slave_sel[2];   
   assign  wbs2_we_i =  wbm_we_o;
   assign wbs2_cti_i = wbm_cti_o;
   assign wbs2_bte_i = wbm_bte_o;
   assign wbs_dat_o_mux_i[2] = wbs2_dat_o;
   assign wbs_ack_o_mux_i[2] = wbs2_ack_o & wb_slave_sel[2];
   assign wbs_err_o_mux_i[2] = wbs2_err_o & wb_slave_sel[2];
   assign wbs_rty_o_mux_i[2] = wbs2_rty_o & wb_slave_sel[2];



   assign wbs3_adr_i = wbm_adr_o;
   assign wbs3_dat_i = wbm_dat_o;
   assign wbs3_cyc_i = wbm_cyc_o & wb_slave_sel[3];
   assign wbs3_stb_i = wbm_stb_o & wb_slave_sel[3];   
   assign  wbs3_we_i =  wbm_we_o;
   assign wbs3_cti_i = wbm_cti_o;
   assign wbs3_bte_i = wbm_bte_o;
   assign wbs_dat_o_mux_i[3] = wbs3_dat_o;
   assign wbs_ack_o_mux_i[3] = wbs3_ack_o & wb_slave_sel[3];
   assign wbs_err_o_mux_i[3] = wbs3_err_o & wb_slave_sel[3];
   assign wbs_rty_o_mux_i[3] = wbs3_rty_o & wb_slave_sel[3];



   assign wbs4_adr_i = wbm_adr_o;
   assign wbs4_dat_i = wbm_dat_o;
   assign wbs4_cyc_i = wbm_cyc_o & wb_slave_sel[4];
   assign wbs4_stb_i = wbm_stb_o & wb_slave_sel[4];   
   assign  wbs4_we_i =  wbm_we_o;
   assign wbs4_cti_i = wbm_cti_o;
   assign wbs4_bte_i = wbm_bte_o;
   assign wbs_dat_o_mux_i[4] = wbs4_dat_o;
   assign wbs_ack_o_mux_i[4] = wbs4_ack_o & wb_slave_sel[4];
   assign wbs_err_o_mux_i[4] = wbs4_err_o & wb_slave_sel[4];
   assign wbs_rty_o_mux_i[4] = wbs4_rty_o & wb_slave_sel[4];






   assign wbm_dat_byte_i = wb_slave_sel[0] ? wbs_dat_o_mux_i[0] :
 		      wb_slave_sel[1] ? wbs_dat_o_mux_i[1] :
		      wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
		      wb_slave_sel[3] ? wbs_dat_o_mux_i[3] :
		      wb_slave_sel[4] ? wbs_dat_o_mux_i[4] :

		      wbs_dat_o_mux_i[0];

   assign wbm_ack_i = wbs_ack_o_mux_i[0]  |
		      wbs_ack_o_mux_i[1]  |
		      wbs_ack_o_mux_i[2]  |
		      wbs_ack_o_mux_i[3]  |
		      wbs_ack_o_mux_i[4]
		      ;
   

   assign wbm_err_i = wbs_err_o_mux_i[0] |
		      wbs_err_o_mux_i[1] |
		      wbs_err_o_mux_i[2] |
		      wbs_err_o_mux_i[3] |
		      wbs_err_o_mux_i[4] |
		      watchdog_err  ;

   
   assign wbm_rty_i = wbs_rty_o_mux_i[0]  |
		      wbs_rty_o_mux_i[1]  |
		      wbs_rty_o_mux_i[2]  |
		      wbs_rty_o_mux_i[3]  |
		      wbs_rty_o_mux_i[4]
	              ;

endmodule
module arbiter_bytebus
  (


   wbm0_adr_o,
   wbm0_dat_o,
   wbm0_sel_o,
   wbm0_we_o,
   wbm0_cyc_o,
   wbm0_stb_o,
   wbm0_cti_o,
   wbm0_bte_o,
   wbm0_dat_i,
   wbm0_ack_i,
   wbm0_err_i,
   wbm0_rty_i,



   wbs0_adr_i,
   wbs0_dat_i,
   wbs0_we_i,
   wbs0_cyc_i,
   wbs0_stb_i,
   wbs0_cti_i,
   wbs0_bte_i,
   wbs0_dat_o,
   wbs0_ack_o,
   wbs0_err_o,
   wbs0_rty_o,



   wbs1_adr_i,
   wbs1_dat_i,
   wbs1_we_i,
   wbs1_cyc_i,
   wbs1_stb_i,
   wbs1_cti_i,
   wbs1_bte_i,
   wbs1_dat_o,
   wbs1_ack_o,
   wbs1_err_o,
   wbs1_rty_o,



   wbs2_adr_i,
   wbs2_dat_i,
   wbs2_we_i,
   wbs2_cyc_i,
   wbs2_stb_i,
   wbs2_cti_i,
   wbs2_bte_i,
   wbs2_dat_o,
   wbs2_ack_o,
   wbs2_err_o,
   wbs2_rty_o,



   wbs3_adr_i,
   wbs3_dat_i,
   wbs3_we_i,
   wbs3_cyc_i,
   wbs3_stb_i,
   wbs3_cti_i,
   wbs3_bte_i,
   wbs3_dat_o,
   wbs3_ack_o,
   wbs3_err_o,
   wbs3_rty_o,



   wbs4_adr_i,
   wbs4_dat_i,
   wbs4_we_i,
   wbs4_cyc_i,
   wbs4_stb_i,
   wbs4_cti_i,
   wbs4_bte_i,
   wbs4_dat_o,
   wbs4_ack_o,
   wbs4_err_o,
   wbs4_rty_o,

   
   wb_clk, wb_rst
   );

   

   parameter wb_dat_width = 32;
   parameter wbs_dat_width = 8;
   parameter wb_adr_width = 32;

   parameter wb_addr_match_width = 8;

   parameter wb_num_slaves = 20;


   
   parameter slave0_adr =  8'h00; 
   parameter slave1_adr =  8'h00; 
   parameter slave2_adr =  8'h00; 
   parameter slave3_adr =  8'h00; 
   parameter slave4_adr =  8'h00; 
   parameter slave5_adr =  8'h00; 
   parameter slave6_adr =  8'h00; 
   parameter slave7_adr =  8'h00; 
   parameter slave8_adr =  8'h00; 
   parameter slave9_adr =  8'h00; 
   parameter slave10_adr = 8'h00;
   parameter slave11_adr = 8'h00;
   parameter slave12_adr = 8'h00;
   parameter slave13_adr = 8'h00;
   parameter slave14_adr = 8'h00;
   parameter slave15_adr = 8'h00;
   parameter slave16_adr = 8'h00;
   parameter slave17_adr = 8'h00;
   parameter slave18_adr = 8'h00;
   parameter slave19_adr = 8'h00;
   

`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
   
   input wb_clk;
   input wb_rst;
   

   input [wb_adr_width-1:0] wbm0_adr_o;
   input [wb_dat_width-1:0] wbm0_dat_o;
   input [3:0] 		    wbm0_sel_o;
   input 		    wbm0_we_o;
   input 		    wbm0_cyc_o;
   input 		    wbm0_stb_o;
   input [2:0] 		    wbm0_cti_o;
   input [1:0] 		    wbm0_bte_o;
   output [wb_dat_width-1:0] wbm0_dat_i;   
   output 		     wbm0_ack_i;
   output 		     wbm0_err_i;
   output 		     wbm0_rty_i;   
   
   


   output [wb_adr_width-1:0] wbs0_adr_i;
   output [wbs_dat_width-1:0] wbs0_dat_i;
   output 		     wbs0_we_i;
   output 		     wbs0_cyc_i;
   output 		     wbs0_stb_i;
   output [2:0] 	     wbs0_cti_i;
   output [1:0] 	     wbs0_bte_i;
   input [wbs_dat_width-1:0]  wbs0_dat_o;
   input 		     wbs0_ack_o;
   input 		     wbs0_err_o;
   input 		     wbs0_rty_o;
   


   output [wb_adr_width-1:0] wbs1_adr_i;
   output [wbs_dat_width-1:0] wbs1_dat_i;
   output 		     wbs1_we_i;
   output 		     wbs1_cyc_i;
   output 		     wbs1_stb_i;
   output [2:0] 	     wbs1_cti_i;
   output [1:0] 	     wbs1_bte_i;
   input [wbs_dat_width-1:0]  wbs1_dat_o;
   input 		     wbs1_ack_o;
   input 		     wbs1_err_o;
   input 		     wbs1_rty_o;
   


   output [wb_adr_width-1:0] wbs2_adr_i;
   output [wbs_dat_width-1:0] wbs2_dat_i;
   output 		     wbs2_we_i;
   output 		     wbs2_cyc_i;
   output 		     wbs2_stb_i;
   output [2:0] 	     wbs2_cti_i;
   output [1:0] 	     wbs2_bte_i;
   input [wbs_dat_width-1:0]  wbs2_dat_o;
   input 		     wbs2_ack_o;
   input 		     wbs2_err_o;
   input 		     wbs2_rty_o;
   


   output [wb_adr_width-1:0] wbs3_adr_i;
   output [wbs_dat_width-1:0] wbs3_dat_i;
   output 		     wbs3_we_i;
   output 		     wbs3_cyc_i;
   output 		     wbs3_stb_i;
   output [2:0] 	     wbs3_cti_i;
   output [1:0] 	     wbs3_bte_i;
   input [wbs_dat_width-1:0]  wbs3_dat_o;
   input 		     wbs3_ack_o;
   input 		     wbs3_err_o;
   input 		     wbs3_rty_o;
   


   output [wb_adr_width-1:0] wbs4_adr_i;
   output [wbs_dat_width-1:0] wbs4_dat_i;
   output 		     wbs4_we_i;
   output 		     wbs4_cyc_i;
   output 		     wbs4_stb_i;
   output [2:0] 	     wbs4_cti_i;
   output [1:0] 	     wbs4_bte_i;
   input [wbs_dat_width-1:0]  wbs4_dat_o;
   input 		     wbs4_ack_o;
   input 		     wbs4_err_o;
   input 		     wbs4_rty_o;
   


   reg 		     watchdog_err;
   

   wire [wb_adr_width-1:0]   wbm_adr_o;
   wire [wbs_dat_width-1:0]  wbm_dat_o;
   wire [3:0] 		     wbm_sel_o;
   wire 		     wbm_we_o;
   wire 		     wbm_cyc_o;
   wire 		     wbm_stb_o;
   wire [2:0] 		     wbm_cti_o;
   wire [1:0] 		     wbm_bte_o;
   
   wire [wbs_dat_width-1:0]   wbm_dat_byte_i;   
   wire 		     wbm_ack_i;
   wire 		     wbm_err_i;
   wire 		     wbm_rty_i;   

   

   assign wbm_adr_o = wbm0_adr_o;



   assign wbm_dat_o = wbm0_sel_o[3] ? wbm0_dat_o[31:24] :
		      wbm0_sel_o[2] ? wbm0_dat_o[23:16] :
		      wbm0_sel_o[1] ? wbm0_dat_o[15:8] :
		      wbm0_dat_o[7:0];
   
   assign wbm_we_o = wbm0_we_o;
   
   assign wbm_cyc_o = wbm0_stb_o;
   
   assign wbm_stb_o = wbm0_stb_o;


   assign wbm_cti_o = wbm0_cti_o;
   
   assign wbm_bte_o = wbm0_bte_o;


   assign wbm0_dat_i = (wbm0_sel_o[3]) ? {wbm_dat_byte_i, 24'd0} :
		       (wbm0_sel_o[2]) ? {8'd0, wbm_dat_byte_i, 16'd0} :
		       (wbm0_sel_o[1]) ? {16'd0, wbm_dat_byte_i, 8'd0} :
	               {24'd0, wbm_dat_byte_i};

   assign wbm0_ack_i = wbm_ack_i;
   assign wbm0_err_i = wbm_err_i;
   assign wbm0_rty_i = wbm_rty_i;

`ifdef ARBITER_BYTEBUS_WATCHDOG
   reg [`ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer;
   reg 			     wbm_stb_r;
   wire 		     wbm_stb_edge;

   always @(posedge wb_clk)
     wbm_stb_r <= wbm_stb_o;

   assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);
   

   always @(posedge wb_clk)
     if (wb_rst) watchdog_timer <= 0;
     else if (wbm_ack_i)
       watchdog_timer <= 0;
     else if (wbm_stb_edge)
       watchdog_timer <= 1;
     else if (|watchdog_timer)
       watchdog_timer <= watchdog_timer + 1;

   always @(posedge wb_clk) 
     watchdog_err <= (&watchdog_timer);
   
`else
   always @(posedge wb_clk) 
     watchdog_err <= 0;
      
`endif

   

   wire [wb_adr_width-1:0]   wbs_adr_i;
   wire [wbs_dat_width-1:0]  wbs_dat_i;
   wire 		     wbs_we_i;
   wire 		     wbs_cyc_i;
   wire 		     wbs_stb_i;
   wire [2:0] 		     wbs_cti_i;
   wire [1:0] 		     wbs_bte_i;
   wire [wbs_dat_width-1:0]  wbs_dat_o;
   wire 		     wbs_ack_o;
   wire 		     wbs_err_o;
   wire 		     wbs_rty_o;

   

   wire [wb_num_slaves-1:0]  wb_slave_sel;
   

   wire [wbs_dat_width-1:0]  wbs_dat_o_mux_i [0:wb_num_slaves-1];
   wire 		     wbs_ack_o_mux_i [0:wb_num_slaves-1];
   wire 		     wbs_err_o_mux_i [0:wb_num_slaves-1];
   wire 		     wbs_rty_o_mux_i [0:wb_num_slaves-1];


   assign wb_slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave0_adr;
   assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
   assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
   assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
   assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;






   assign wbs0_adr_i = wbm_adr_o;
   assign wbs0_dat_i = wbm_dat_o;
   assign wbs0_cyc_i = wbm_cyc_o & wb_slave_sel[0];
   assign wbs0_stb_i = wbm_stb_o & wb_slave_sel[0];   
   assign  wbs0_we_i =  wbm_we_o;
   assign wbs0_cti_i = wbm_cti_o;
   assign wbs0_bte_i = wbm_bte_o;
   assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
   assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel[0];
   assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel[0];
   assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel[0];



   assign wbs1_adr_i = wbm_adr_o;
   assign wbs1_dat_i = wbm_dat_o;
   assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel[1];
   assign wbs1_stb_i = wbm_stb_o & wb_slave_sel[1];   
   assign  wbs1_we_i =  wbm_we_o;
   assign wbs1_cti_i = wbm_cti_o;
   assign wbs1_bte_i = wbm_bte_o;
   assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
   assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel[1];
   assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel[1];
   assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel[1];



   assign wbs2_adr_i = wbm_adr_o;
   assign wbs2_dat_i = wbm_dat_o;
   assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel[2];
   assign wbs2_stb_i = wbm_stb_o & wb_slave_sel[2];   
   assign  wbs2_we_i =  wbm_we_o;
   assign wbs2_cti_i = wbm_cti_o;
   assign wbs2_bte_i = wbm_bte_o;
   assign wbs_dat_o_mux_i[2] = wbs2_dat_o;
   assign wbs_ack_o_mux_i[2] = wbs2_ack_o & wb_slave_sel[2];
   assign wbs_err_o_mux_i[2] = wbs2_err_o & wb_slave_sel[2];
   assign wbs_rty_o_mux_i[2] = wbs2_rty_o & wb_slave_sel[2];



   assign wbs3_adr_i = wbm_adr_o;
   assign wbs3_dat_i = wbm_dat_o;
   assign wbs3_cyc_i = wbm_cyc_o & wb_slave_sel[3];
   assign wbs3_stb_i = wbm_stb_o & wb_slave_sel[3];   
   assign  wbs3_we_i =  wbm_we_o;
   assign wbs3_cti_i = wbm_cti_o;
   assign wbs3_bte_i = wbm_bte_o;
   assign wbs_dat_o_mux_i[3] = wbs3_dat_o;
   assign wbs_ack_o_mux_i[3] = wbs3_ack_o & wb_slave_sel[3];
   assign wbs_err_o_mux_i[3] = wbs3_err_o & wb_slave_sel[3];
   assign wbs_rty_o_mux_i[3] = wbs3_rty_o & wb_slave_sel[3];



   assign wbs4_adr_i = wbm_adr_o;
   assign wbs4_dat_i = wbm_dat_o;
   assign wbs4_cyc_i = wbm_cyc_o & wb_slave_sel[4];
   assign wbs4_stb_i = wbm_stb_o & wb_slave_sel[4];   
   assign  wbs4_we_i =  wbm_we_o;
   assign wbs4_cti_i = wbm_cti_o;
   assign wbs4_bte_i = wbm_bte_o;
   assign wbs_dat_o_mux_i[4] = wbs4_dat_o;
   assign wbs_ack_o_mux_i[4] = wbs4_ack_o & wb_slave_sel[4];
   assign wbs_err_o_mux_i[4] = wbs4_err_o & wb_slave_sel[4];
   assign wbs_rty_o_mux_i[4] = wbs4_rty_o & wb_slave_sel[4];






   assign wbm_dat_byte_i = wb_slave_sel[0] ? wbs_dat_o_mux_i[0] :
 		      wb_slave_sel[1] ? wbs_dat_o_mux_i[1] :
		      wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
		      wb_slave_sel[3] ? wbs_dat_o_mux_i[3] :
		      wb_slave_sel[4] ? wbs_dat_o_mux_i[4] :

		      wbs_dat_o_mux_i[0];

   assign wbm_ack_i = wbs_ack_o_mux_i[0]  |
		      wbs_ack_o_mux_i[1]  |
		      wbs_ack_o_mux_i[2]  |
		      wbs_ack_o_mux_i[3]  |
		      wbs_ack_o_mux_i[4]
		      ;
   

   assign wbm_err_i = wbs_err_o_mux_i[0] |
		      wbs_err_o_mux_i[1] |
		      wbs_err_o_mux_i[2] |
		      wbs_err_o_mux_i[3] |
		      wbs_err_o_mux_i[4] |
		      watchdog_err  ;

   
   assign wbm_rty_i = wbs_rty_o_mux_i[0]  |
		      wbs_rty_o_mux_i[1]  |
		      wbs_rty_o_mux_i[2]  |
		      wbs_rty_o_mux_i[3]  |
		      wbs_rty_o_mux_i[4]
	              ;

endmodule