data/full_repos/permissive/135475029/lab_8/src/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/135475029/lab_8/src/ALU.v:48: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                       : ... In instance ALU\n  assign addout = a + sel_b + aluop[1];\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ALU(
  input [31:0] a,
  input [31:0] b,
	input [3:0] aluop,
	output [31:0] result,
	output zero
);

  wire [31:0] logicout;
  wire [31:0] addout;
  wire [31:0] arithout;
  wire [31:0] n_b;
  wire [31:0] sel_b;
  wire [31:0] slt;

  wire [1:0] logicsel;


  assign logicsel = aluop[1:0];
  assign logicout = (logicsel == 2'b00) ? a & b :
                    (logicsel == 2'b01) ? a | b :
						        (logicsel == 2'b10) ? a ^ b :
                                          ~(a | b) ;


  assign n_b = ~b ;
  assign sel_b = (aluop[1])? n_b : b ;
  assign addout = a + sel_b + aluop[1];


  assign slt = { 31'b0, addout[31] };


  assign arithout = (aluop[3]) ? slt : addout;


  assign result = (aluop[2]) ? logicout : arithout;


  assign zero = (result == 32'b0) ? 1: 0;

endmodule
module ALU(
  input [31:0] a,
  input [31:0] b,
	input [3:0] aluop,
	output [31:0] result,
	output zero
);


  wire [31:0] logicout;
  wire [31:0] addout;
  wire [31:0] arithout;
  wire [31:0] n_b;
  wire [31:0] sel_b;
  wire [31:0] slt;

  wire [1:0] logicsel;


  assign logicsel = aluop[1:0];
  assign logicout = (logicsel == 2'b00) ? a & b :
                    (logicsel == 2'b01) ? a | b :
						        (logicsel == 2'b10) ? a ^ b :
                                          ~(a | b) ;


  assign n_b = ~b ;
  assign sel_b = (aluop[1])? n_b : b ;
  assign addout = a + sel_b + aluop[1];


  assign slt = { 31'b0, addout[31] };


  assign arithout = (aluop[3]) ? slt : addout;


  assign result = (aluop[2]) ? logicout : arithout;


  assign zero = (result == 32'b0) ? 1: 0;

endmodule