data/full_repos/permissive/129155059/proyecto-01/byte_striping/testbench_byte_striping.v
1: b"%Error: data/full_repos/permissive/129155059/proyecto-01/byte_striping/testbench_byte_striping.v:11: Cannot find file containing module: 'byte_striping_cond'\n  byte_striping_cond BS_conduct(\n  ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/byte_striping,data/full_repos/permissive/129155059/byte_striping_cond\n             data/full_repos/permissive/129155059/proyecto-01/byte_striping,data/full_repos/permissive/129155059/byte_striping_cond.v\n             data/full_repos/permissive/129155059/proyecto-01/byte_striping,data/full_repos/permissive/129155059/byte_striping_cond.sv\n             byte_striping_cond\n             byte_striping_cond.v\n             byte_striping_cond.sv\n             obj_dir/byte_striping_cond\n             obj_dir/byte_striping_cond.v\n             obj_dir/byte_striping_cond.sv\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_striping/testbench_byte_striping.v:25: Cannot find file containing module: 'byte_striping_synth'\n  byte_striping_synth BS_struct(\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_striping/testbench_byte_striping.v:39: Cannot find file containing module: 'tester_byte_striping'\n  tester_byte_striping BS_tester(\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module testbench;
  wire [7:0] lane0s, lane1s, lane2s, lane3s, entradaBS;
  wire [7:0] lane0c, lane1c, lane2c, lane3c;
  wire lanevalid;
  wire validBS, relojMUX, relojBS;
  wire [1:0] counts, countc;
  wire reset;

  byte_striping_cond BS_conduct(
    .stripedLane0 (lane0c),
    .stripedLane1 (lane1c),
    .stripedLane2 (lane2c),
    .stripedLane3 (lane3c),
    .byteStripingVLD (validBS),
    .byteStripingIN (entradaBS),
    .laneVLD (validlane),
    .clk250k  (relojBS),
    .clk1Mhz  (relojMUX),
    .counter (countc),
    .reset (reset)
    );

  byte_striping_synth BS_struct(
    .stripedLane0 (lane0s),
    .stripedLane1 (lane1s),
    .stripedLane2 (lane2s),
    .stripedLane3 (lane3s),
    .byteStripingVLD (validBS),
    .byteStripingIN (entradaBS),
    .laneVLD (validlane),
    .clk250k  (relojBS),
    .clk1Mhz  (relojMUX),
    .counter (counts),
    .reset (reset)
    );

  tester_byte_striping BS_tester(
    .stripedLane0 (lane0),
    .stripedLane1 (lane1),
    .stripedLane2 (lane2),
    .stripedLane3 (lane3),
    .byteStripingVLD (validBS),
    .byteStripingIN (entradaBS),
    .laneVLD (validlane),
    .clk250k  (relojBS),
    .clk1Mhz  (relojMUX),
    .reset (reset)
    );

endmodule
module testbench;

  wire [7:0] lane0s, lane1s, lane2s, lane3s, entradaBS;
  wire [7:0] lane0c, lane1c, lane2c, lane3c;
  wire lanevalid;
  wire validBS, relojMUX, relojBS;
  wire [1:0] counts, countc;
  wire reset;

  byte_striping_cond BS_conduct(
    .stripedLane0 (lane0c),
    .stripedLane1 (lane1c),
    .stripedLane2 (lane2c),
    .stripedLane3 (lane3c),
    .byteStripingVLD (validBS),
    .byteStripingIN (entradaBS),
    .laneVLD (validlane),
    .clk250k  (relojBS),
    .clk1Mhz  (relojMUX),
    .counter (countc),
    .reset (reset)
    );

  byte_striping_synth BS_struct(
    .stripedLane0 (lane0s),
    .stripedLane1 (lane1s),
    .stripedLane2 (lane2s),
    .stripedLane3 (lane3s),
    .byteStripingVLD (validBS),
    .byteStripingIN (entradaBS),
    .laneVLD (validlane),
    .clk250k  (relojBS),
    .clk1Mhz  (relojMUX),
    .counter (counts),
    .reset (reset)
    );

  tester_byte_striping BS_tester(
    .stripedLane0 (lane0),
    .stripedLane1 (lane1),
    .stripedLane2 (lane2),
    .stripedLane3 (lane3),
    .byteStripingVLD (validBS),
    .byteStripingIN (entradaBS),
    .laneVLD (validlane),
    .clk250k  (relojBS),
    .clk1Mhz  (relojMUX),
    .reset (reset)
    );

endmodule