data/full_repos/permissive/163670715/abl.v
None: at end of input
1: b'%Error: data/full_repos/permissive/163670715/abl.v:25: Cannot find include file: states.i\n`include "states.i" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/163670715,data/full_repos/permissive/163670715/states.i\n             data/full_repos/permissive/163670715,data/full_repos/permissive/163670715/states.i.v\n             data/full_repos/permissive/163670715,data/full_repos/permissive/163670715/states.i.sv\n             states.i\n             states.i.v\n             states.i.sv\n             obj_dir/states.i\n             obj_dir/states.i.v\n             obj_dir/states.i.sv\n%Error: Exiting due to 1 error(s)\n'
module abl(
    input clk,
    input [4:0] op,   
    input RDY,
    output CO,
    output PCL8,
    output reg [7:0] ABL,
    input SB_DIR,
    inout [7:0] DB,
    inout [7:0] SB );

`include "states.i"

reg [7:0] PCL;
reg [7:0] SPL = 8'hFF;
reg [7:0] AHL;
reg [7:0] base;
wire [7:0] offset;
wire [8:0] PCL1 = ABL + 1;













reg CI;
reg use_sb;
reg oe_pcl;
reg load_ahl;
reg load_pcl;
wire load_abl = (op != AB_RMW);
wire load_spl = (op == AB_TXS);
wire irq = ( op == AB_IRQ0 );

assign PCL8 = PCL1[8];
assign DB = oe_pcl ? PCL : 8'hZZ;
assign SB = SB_DIR ? SPL : 8'hZZ;

assign offset = use_sb ? SB : 8'h00;

wire [7:0] P = base ^ offset;
wire [7:0] G = base & offset;



wire C1 = (CI & P[0]) | G[0];
wire C2 = (C1 & P[1]) | G[1];
wire C3 = (C2 & P[2]) | G[2];
wire C4 = (C3 & P[3]) | G[3];
wire C5 = (C4 & P[4]) | G[4];
wire C6 = (C5 & P[5]) | G[5];
wire C7 = (C6 & P[6]) | G[6];

assign CO = (C7 & P[7]) | G[7];


wire [7:0] EAL = P ^ { C7, C6, C5, C4, C3, C2, C1, CI };

always @(*)
    case( op )
        AB_BRK1   :                     oe_pcl = 1;
        AB_JSR1   :                     oe_pcl = 1;
        default   :                     oe_pcl = 0;
    endcase



always @(*)
    casez( op[4:3] )
        0 :                             base = AHL;
        1 :    case( op[1:0] )
                   0 :                  base = DB;
                   1 :                  base = 8'hfa;
                   2 :                  base = 8'hfc;
                   3 :                  base = 8'hfe;
               endcase
        2:                              base = PCL;
        3:                              base = SPL;
    endcase


always @(posedge clk)
    if( RDY )
        if( load_spl )                  SPL <= SB;
        else case( op )
            AB_RTS0, 
            AB_PLA:                     SPL <= SPL + 1;

            AB_BRK, 
            AB_BRK1, 
            AB_JSR0, 
            AB_PHA :                    SPL <= SPL - 1;
        endcase


always @(*)
    case( op )
        AB_ABS0   :                     use_sb = 1; 
        AB_JMP0   :                     use_sb = 1;
        AB_BRA0   :                     use_sb = 1;
        AB_INDX0  :                     use_sb = 1;
        AB_INDX1  :                     use_sb = 1;
        AB_ZPXY   :                     use_sb = 1;
    default:                            use_sb = 0;
    endcase


always @(*)
    case( op )
        AB_INDX0,
        AB_ZPXY,
        AB_RTS0,
        AB_PHA,
        AB_BRK,
        AB_DATA,
        AB_TXS,
        AB_FETCH,
        AB_IND0:                        load_ahl = 1;
        default:                        load_ahl = 0;
    endcase


always @(*) 
    case( op )
        AB_ZPXY,
        AB_BRK,
        AB_ABS0,
        AB_JMP0,
        AB_TXS,
        AB_FETCH,
        AB_IND0:                        load_pcl = 1;
        default:                        load_pcl = 0;
    endcase


always @(*) 
    case( op )
        AB_INDX0,
        AB_PLA,
        AB_RTS0,
        AB_RTS1:                        CI = 1;
        default:                        CI = 0;
    endcase


always @(posedge clk)
    if( RDY & load_ahl )                AHL <= DB; 


always @(negedge clk)
    if( RDY )
        if( irq )                       PCL <= ABL;
        else if( load_pcl )             PCL <= PCL1;


always @(posedge clk)
    if( RDY & load_abl )                ABL <= EAL;

endmodule
module abl(
    input clk,
    input [4:0] op,   
    input RDY,
    output CO,
    output PCL8,
    output reg [7:0] ABL,
    input SB_DIR,
    inout [7:0] DB,
    inout [7:0] SB );


`include "states.i"

reg [7:0] PCL;
reg [7:0] SPL = 8'hFF;
reg [7:0] AHL;
reg [7:0] base;
wire [7:0] offset;
wire [8:0] PCL1 = ABL + 1;













reg CI;
reg use_sb;
reg oe_pcl;
reg load_ahl;
reg load_pcl;
wire load_abl = (op != AB_RMW);
wire load_spl = (op == AB_TXS);
wire irq = ( op == AB_IRQ0 );

assign PCL8 = PCL1[8];
assign DB = oe_pcl ? PCL : 8'hZZ;
assign SB = SB_DIR ? SPL : 8'hZZ;

assign offset = use_sb ? SB : 8'h00;

wire [7:0] P = base ^ offset;
wire [7:0] G = base & offset;



wire C1 = (CI & P[0]) | G[0];
wire C2 = (C1 & P[1]) | G[1];
wire C3 = (C2 & P[2]) | G[2];
wire C4 = (C3 & P[3]) | G[3];
wire C5 = (C4 & P[4]) | G[4];
wire C6 = (C5 & P[5]) | G[5];
wire C7 = (C6 & P[6]) | G[6];

assign CO = (C7 & P[7]) | G[7];


wire [7:0] EAL = P ^ { C7, C6, C5, C4, C3, C2, C1, CI };

always @(*)
    case( op )
        AB_BRK1   :                     oe_pcl = 1;
        AB_JSR1   :                     oe_pcl = 1;
        default   :                     oe_pcl = 0;
    endcase



always @(*)
    casez( op[4:3] )
        0 :                             base = AHL;
        1 :    case( op[1:0] )
                   0 :                  base = DB;
                   1 :                  base = 8'hfa;
                   2 :                  base = 8'hfc;
                   3 :                  base = 8'hfe;
               endcase
        2:                              base = PCL;
        3:                              base = SPL;
    endcase


always @(posedge clk)
    if( RDY )
        if( load_spl )                  SPL <= SB;
        else case( op )
            AB_RTS0, 
            AB_PLA:                     SPL <= SPL + 1;

            AB_BRK, 
            AB_BRK1, 
            AB_JSR0, 
            AB_PHA :                    SPL <= SPL - 1;
        endcase


always @(*)
    case( op )
        AB_ABS0   :                     use_sb = 1; 
        AB_JMP0   :                     use_sb = 1;
        AB_BRA0   :                     use_sb = 1;
        AB_INDX0  :                     use_sb = 1;
        AB_INDX1  :                     use_sb = 1;
        AB_ZPXY   :                     use_sb = 1;
    default:                            use_sb = 0;
    endcase


always @(*)
    case( op )
        AB_INDX0,
        AB_ZPXY,
        AB_RTS0,
        AB_PHA,
        AB_BRK,
        AB_DATA,
        AB_TXS,
        AB_FETCH,
        AB_IND0:                        load_ahl = 1;
        default:                        load_ahl = 0;
    endcase


always @(*) 
    case( op )
        AB_ZPXY,
        AB_BRK,
        AB_ABS0,
        AB_JMP0,
        AB_TXS,
        AB_FETCH,
        AB_IND0:                        load_pcl = 1;
        default:                        load_pcl = 0;
    endcase


always @(*) 
    case( op )
        AB_INDX0,
        AB_PLA,
        AB_RTS0,
        AB_RTS1:                        CI = 1;
        default:                        CI = 0;
    endcase


always @(posedge clk)
    if( RDY & load_ahl )                AHL <= DB; 


always @(negedge clk)
    if( RDY )
        if( irq )                       PCL <= ABL;
        else if( load_pcl )             PCL <= PCL1;


always @(posedge clk)
    if( RDY & load_abl )                ABL <= EAL;

endmodule