data/full_repos/permissive/115771353/rtl/hworb/eth_rx_fifo_wraper.v
1: b"%Error: data/full_repos/permissive/115771353/rtl/hworb/eth_rx_fifo_wraper.v:168: Cannot find file containing module: 'async_fifo'\n  async_fifo #(16, 10)\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115771353/rtl/hworb,data/full_repos/permissive/115771353/async_fifo\n             data/full_repos/permissive/115771353/rtl/hworb,data/full_repos/permissive/115771353/async_fifo.v\n             data/full_repos/permissive/115771353/rtl/hworb,data/full_repos/permissive/115771353/async_fifo.sv\n             async_fifo\n             async_fifo.v\n             async_fifo.sv\n             obj_dir/async_fifo\n             obj_dir/async_fifo.v\n             obj_dir/async_fifo.sv\n%Error: data/full_repos/permissive/115771353/rtl/hworb/eth_rx_fifo_wraper.v:186: Cannot find file containing module: 'async_fifo'\n  async_fifo #(8, 10)\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module eth_rx_fifo_wraper (
  input              clk_i,
  input              reset_n,
  input              clk_en,

  input              rx_len_fifo_read,
  input              rx_data_fifo_read,

  input              rx_write,
  input              rx_eof,
  input [7:0]        rx_dbout,
  input              rxmac_clk,

  output wire [15:0] rx_len_fifo_data,
  output wire [7:0]  rx_data_fifo_data,

  output wire        rx_data_fifo_full,
  output wire        rx_data_fifo_empty,
  output wire        rx_len_fifo_full,
  output wire        rx_len_fifo_empty
);



  reg         rx_write_1d;
  reg         rx_eof_1d;
  reg [7:0]   rx_dbout_1d;
  reg [12:0]  byte_cnt;
  reg [1:0]   eth_rxfifo_ctrl_fsm;

  reg         mac_wr_rx_data_fifo;
  reg         mac_wr_rx_len_fifo;

  reg [7:0]   rx_fifo_data;

  wire [15:0] rx_len_fifo_data_minus1;
  wire        byte_enb_sel;
  wire [15:0] rx_fifo_len;

  wire        mac_wr_rx_data_fifo_x;
  wire        mac_wr_rx_len_fifo_x;

  



  parameter [1:0]
	RX_FSM_IDLE    	= 2'd0,
	RX_FSM_WR_DATA  = 2'd1,
	RX_FSM_WR_LEN   = 2'd2;



  assign byte_enb_sel = ( (rx_write_1d == 1'b1) && byte_cnt < 13'd2047 ) ? 1:0;
  assign rx_fifo_len[15:0] = {3'b000, byte_cnt[12:0]};
  assign rx_len_fifo_data  = (rx_len_fifo_data_minus1 + 1);
 
  assign mac_wr_rx_data_fifo_x = mac_wr_rx_data_fifo & clk_en;
  assign mac_wr_rx_len_fifo_x  = mac_wr_rx_len_fifo & clk_en;
   


  always @(posedge rxmac_clk or negedge reset_n) 
  begin
    if (!reset_n) begin
      rx_write_1d <= 1'b0;
      rx_eof_1d <= 1'b0;
      rx_dbout_1d <= 8'h00;
      mac_wr_rx_data_fifo <= 1'b0;
	end
	else if (clk_en) begin
      rx_write_1d <= rx_write;
      rx_eof_1d <= rx_eof;
      rx_dbout_1d <= rx_dbout;
      mac_wr_rx_data_fifo <= (rx_eof_1d | byte_enb_sel);
	end
 end




  always @(posedge rxmac_clk or negedge reset_n) 
  begin
    if (!reset_n) begin
      rx_fifo_data[7:0] <= 8'd0;
	end
	else if (clk_en) begin
      rx_fifo_data[7:0] <= rx_dbout_1d[7:0];
	end
  end
  



  always @(posedge rxmac_clk or negedge reset_n) 
  begin
    if (!reset_n) begin
      eth_rxfifo_ctrl_fsm <= RX_FSM_IDLE;
      byte_cnt <= 13'd0;
      mac_wr_rx_len_fifo <= 1'b0;
	end
	else if (clk_en) begin

      mac_wr_rx_len_fifo <= 1'b0;

      case (eth_rxfifo_ctrl_fsm)

        RX_FSM_IDLE:
        begin
          if (rx_write == 1'b1) begin 
            byte_cnt <= 13'd0;
            eth_rxfifo_ctrl_fsm <= RX_FSM_WR_DATA;
          end
        end
		
        RX_FSM_WR_DATA:
        begin
          if (rx_eof_1d == 1'b1) begin
            eth_rxfifo_ctrl_fsm <= RX_FSM_WR_LEN;
          end
          else begin
            if (rx_write == 1'b1 && byte_cnt < 13'd2047) begin 
              byte_cnt <= byte_cnt + 1;
            end
            eth_rxfifo_ctrl_fsm <= RX_FSM_WR_DATA;
          end
        end
				 
        RX_FSM_WR_LEN:
        begin

          eth_rxfifo_ctrl_fsm <= RX_FSM_IDLE;
          mac_wr_rx_len_fifo <= 1'b1;
        end
				 
        default:
        begin
          eth_rxfifo_ctrl_fsm <= RX_FSM_IDLE;
          byte_cnt <= 13'd0;
          mac_wr_rx_len_fifo <= 1'b0;
        end
	  endcase 
    end
  end
   
   


  async_fifo #(16, 10)
  u_rx_len_fifo
  (
  	.wrst_n (reset_n),
  	.wclk   (rxmac_clk),
    .winc   (mac_wr_rx_len_fifo_x),
    .wdata  (rx_fifo_len[15:0]),
    .wfull  (rx_len_fifo_full),
    
    .rrst_n (reset_n),
    .rclk   (clk_i),
    .rinc   (rx_len_fifo_read),
    .rdata  (rx_len_fifo_data_minus1[15:0]),
    .rempty (rx_len_fifo_empty)
  );
	


  async_fifo #(8, 10)
  u_rx_data_fifo
  (
  	.wrst_n (reset_n),
  	.wclk   (rxmac_clk),
    .winc   (mac_wr_rx_data_fifo_x),
    .wdata  (rx_fifo_data[7:0]),
    .wfull  (rx_data_fifo_full),
    
    .rrst_n (reset_n),
    .rclk   (clk_i),
    .rinc   (rx_data_fifo_read),
    .rdata  (rx_data_fifo_data[7:0]),
    .rempty (rx_data_fifo_empty)
  );

endmodule
module eth_rx_fifo_wraper (
  input              clk_i,
  input              reset_n,
  input              clk_en,

  input              rx_len_fifo_read,
  input              rx_data_fifo_read,

  input              rx_write,
  input              rx_eof,
  input [7:0]        rx_dbout,
  input              rxmac_clk,

  output wire [15:0] rx_len_fifo_data,
  output wire [7:0]  rx_data_fifo_data,

  output wire        rx_data_fifo_full,
  output wire        rx_data_fifo_empty,
  output wire        rx_len_fifo_full,
  output wire        rx_len_fifo_empty
);




  reg         rx_write_1d;
  reg         rx_eof_1d;
  reg [7:0]   rx_dbout_1d;
  reg [12:0]  byte_cnt;
  reg [1:0]   eth_rxfifo_ctrl_fsm;

  reg         mac_wr_rx_data_fifo;
  reg         mac_wr_rx_len_fifo;

  reg [7:0]   rx_fifo_data;

  wire [15:0] rx_len_fifo_data_minus1;
  wire        byte_enb_sel;
  wire [15:0] rx_fifo_len;

  wire        mac_wr_rx_data_fifo_x;
  wire        mac_wr_rx_len_fifo_x;

  



  parameter [1:0]
	RX_FSM_IDLE    	= 2'd0,
	RX_FSM_WR_DATA  = 2'd1,
	RX_FSM_WR_LEN   = 2'd2;



  assign byte_enb_sel = ( (rx_write_1d == 1'b1) && byte_cnt < 13'd2047 ) ? 1:0;
  assign rx_fifo_len[15:0] = {3'b000, byte_cnt[12:0]};
  assign rx_len_fifo_data  = (rx_len_fifo_data_minus1 + 1);
 
  assign mac_wr_rx_data_fifo_x = mac_wr_rx_data_fifo & clk_en;
  assign mac_wr_rx_len_fifo_x  = mac_wr_rx_len_fifo & clk_en;
   


  always @(posedge rxmac_clk or negedge reset_n) 
  begin
    if (!reset_n) begin
      rx_write_1d <= 1'b0;
      rx_eof_1d <= 1'b0;
      rx_dbout_1d <= 8'h00;
      mac_wr_rx_data_fifo <= 1'b0;
	end
	else if (clk_en) begin
      rx_write_1d <= rx_write;
      rx_eof_1d <= rx_eof;
      rx_dbout_1d <= rx_dbout;
      mac_wr_rx_data_fifo <= (rx_eof_1d | byte_enb_sel);
	end
 end




  always @(posedge rxmac_clk or negedge reset_n) 
  begin
    if (!reset_n) begin
      rx_fifo_data[7:0] <= 8'd0;
	end
	else if (clk_en) begin
      rx_fifo_data[7:0] <= rx_dbout_1d[7:0];
	end
  end
  



  always @(posedge rxmac_clk or negedge reset_n) 
  begin
    if (!reset_n) begin
      eth_rxfifo_ctrl_fsm <= RX_FSM_IDLE;
      byte_cnt <= 13'd0;
      mac_wr_rx_len_fifo <= 1'b0;
	end
	else if (clk_en) begin

      mac_wr_rx_len_fifo <= 1'b0;

      case (eth_rxfifo_ctrl_fsm)

        RX_FSM_IDLE:
        begin
          if (rx_write == 1'b1) begin 
            byte_cnt <= 13'd0;
            eth_rxfifo_ctrl_fsm <= RX_FSM_WR_DATA;
          end
        end
		
        RX_FSM_WR_DATA:
        begin
          if (rx_eof_1d == 1'b1) begin
            eth_rxfifo_ctrl_fsm <= RX_FSM_WR_LEN;
          end
          else begin
            if (rx_write == 1'b1 && byte_cnt < 13'd2047) begin 
              byte_cnt <= byte_cnt + 1;
            end
            eth_rxfifo_ctrl_fsm <= RX_FSM_WR_DATA;
          end
        end
				 
        RX_FSM_WR_LEN:
        begin

          eth_rxfifo_ctrl_fsm <= RX_FSM_IDLE;
          mac_wr_rx_len_fifo <= 1'b1;
        end
				 
        default:
        begin
          eth_rxfifo_ctrl_fsm <= RX_FSM_IDLE;
          byte_cnt <= 13'd0;
          mac_wr_rx_len_fifo <= 1'b0;
        end
	  endcase 
    end
  end
   
   


  async_fifo #(16, 10)
  u_rx_len_fifo
  (
  	.wrst_n (reset_n),
  	.wclk   (rxmac_clk),
    .winc   (mac_wr_rx_len_fifo_x),
    .wdata  (rx_fifo_len[15:0]),
    .wfull  (rx_len_fifo_full),
    
    .rrst_n (reset_n),
    .rclk   (clk_i),
    .rinc   (rx_len_fifo_read),
    .rdata  (rx_len_fifo_data_minus1[15:0]),
    .rempty (rx_len_fifo_empty)
  );
	


  async_fifo #(8, 10)
  u_rx_data_fifo
  (
  	.wrst_n (reset_n),
  	.wclk   (rxmac_clk),
    .winc   (mac_wr_rx_data_fifo_x),
    .wdata  (rx_fifo_data[7:0]),
    .wfull  (rx_data_fifo_full),
    
    .rrst_n (reset_n),
    .rclk   (clk_i),
    .rinc   (rx_data_fifo_read),
    .rdata  (rx_data_fifo_data[7:0]),
    .rempty (rx_data_fifo_empty)
  );

endmodule