data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v
1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:11: Cannot find include file: sm_cpu.vh\n`include "sm_cpu.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh.v\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh.sv\n             sm_cpu.vh\n             sm_cpu.vh.v\n             sm_cpu.vh.sv\n             obj_dir/sm_cpu.vh\n             obj_dir/sm_cpu.vh.v\n             obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:12: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:178: Define or directive not defined: \'`PC_EXC\'\n    assign pc_new = pcExc == `PC_EXC  ?  cp0_ExcHandler :\n                             ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:178: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n    assign pc_new = pcExc == `PC_EXC  ?  cp0_ExcHandler :\n                                      ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:179: Define or directive not defined: \'`PC_ERET\'\n                    pcExc == `PC_ERET ?  cp0_EPC        :\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:235: Define or directive not defined: \'`PC_EXC\'\n    assign pcExc = exception      ? `PC_EXC  :\n                                    ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:235: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign pcExc = exception      ? `PC_EXC  :\n                                             ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:236: Define or directive not defined: \'`PC_ERET\'\n                   cw_cpzExcEret  ? `PC_ERET : `PC_FLOW;\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:236: Define or directive not defined: \'`PC_FLOW\'\n                   cw_cpzExcEret  ? `PC_ERET : `PC_FLOW;\n                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:244: Define or directive not defined: \'`ALU_ADD\'\n        aluControl  = `ALU_ADD;\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:244: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        aluControl  = `ALU_ADD;\n                              ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`C_SPEC\'\n            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD;  end\n              ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD;  end\n                     ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`F_ADDU\'\n            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD;  end\n                        ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`S_ANY\'\n            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD;  end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`ALU_ADD\'\n            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD;  end\n                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            { `C_SPEC,  `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD;  end\n                                                                                                       ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`C_SPEC\'\n            { `C_SPEC,  `F_OR,   `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR;   end\n              ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`F_OR\'\n            { `C_SPEC,  `F_OR,   `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR;   end\n                        ^~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`S_ANY\'\n            { `C_SPEC,  `F_OR,   `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR;   end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`ALU_OR\'\n            { `C_SPEC,  `F_OR,   `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR;   end\n                                                                                               ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`C_SPEC\'\n            { `C_SPEC,  `F_SRL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL;  end\n              ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`F_SRL\'\n            { `C_SPEC,  `F_SRL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL;  end\n                        ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`S_ANY\'\n            { `C_SPEC,  `F_SRL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL;  end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`ALU_SRL\'\n            { `C_SPEC,  `F_SRL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL;  end\n                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`C_SPEC\'\n            { `C_SPEC,  `F_SLL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL;  end\n              ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`F_SLL\'\n            { `C_SPEC,  `F_SLL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL;  end\n                        ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`S_ANY\'\n            { `C_SPEC,  `F_SLL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL;  end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`ALU_SLL\'\n            { `C_SPEC,  `F_SLL,  `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL;  end\n                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`C_SPEC\'\n            { `C_SPEC,  `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n              ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`F_SLTU\'\n            { `C_SPEC,  `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n                        ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`S_ANY\'\n            { `C_SPEC,  `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`ALU_SLTU\'\n            { `C_SPEC,  `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n                                                                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`C_SPEC\'\n            { `C_SPEC,  `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n              ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`F_SUBU\'\n            { `C_SPEC,  `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n                        ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`S_ANY\'\n            { `C_SPEC,  `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`ALU_SUBU\'\n            { `C_SPEC,  `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n                                                                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`C_ADDIU\'\n            { `C_ADDIU, `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD;  end\n              ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`F_ANY\'\n            { `C_ADDIU, `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD;  end\n                        ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`S_ANY\'\n            { `C_ADDIU, `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD;  end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`ALU_ADD\'\n            { `C_ADDIU, `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD;  end\n                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`C_LUI\'\n            { `C_LUI,   `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI;  end\n              ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`F_ANY\'\n            { `C_LUI,   `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI;  end\n                        ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`S_ANY\'\n            { `C_LUI,   `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI;  end\n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`ALU_LUI\'\n            { `C_LUI,   `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI;  end\n                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`C_LW\'\n            { `C_LW,    `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n              ^~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`F_ANY\'\n            { `C_LW,    `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n                        ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`S_ANY\'\n            { `C_LW,    `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n                                 ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`ALU_ADD\'\n            { `C_LW,    `F_ANY,  `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:267: Define or directive not defined: \'`C_SW\'\n            { `C_SW,    `F_ANY,  `S_ANY } : begin memWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n              ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module sm_alu
(
    input  [31:0] srcA,
    input  [31:0] srcB,
    input  [ 2:0] oper,
    input  [ 4:0] shift,
    output        zero,
    output reg [31:0] result
);
    always @ (*) begin
        case (oper)
            default   : result = srcA + srcB;
            `ALU_ADD  : result = srcA + srcB;
            `ALU_OR   : result = srcA | srcB;
            `ALU_LUI  : result = (srcB << 16);
            `ALU_SRL  : result = srcB >> shift;
            `ALU_SLL  : result = srcB << shift;
            `ALU_SLTU : result = (srcA < srcB) ? 1 : 0;
            `ALU_SUBU : result = srcA - srcB;
        endcase
    end

    assign zero   = (result == 0);
endmodule
module sm_alu
(
    input  [31:0] srcA,
    input  [31:0] srcB,
    input  [ 2:0] oper,
    input  [ 4:0] shift,
    output        zero,
    output reg [31:0] result
);

    always @ (*) begin
        case (oper)
            default   : result = srcA + srcB;
            `ALU_ADD  : result = srcA + srcB;
            `ALU_OR   : result = srcA | srcB;
            `ALU_LUI  : result = (srcB << 16);
            `ALU_SRL  : result = srcB >> shift;
            `ALU_SLL  : result = srcB << shift;
            `ALU_SLTU : result = (srcA < srcB) ? 1 : 0;
            `ALU_SUBU : result = srcA - srcB;
        endcase
    end

    assign zero   = (result == 0);
endmodule