data/full_repos/permissive/143278/ivltests/wireland.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wireland.v:31: Unsupported: Ignoring delay on this delayed statement.\n       #1 ;  \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wireland.v:34: Unsupported: Ignoring delay on this delayed statement.\n       #1 ;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wireland.v:40: Unsupported: Ignoring delay on this delayed statement.\n       #1 ;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/wireland.v:42: Unsupported: Ignoring delay on this delayed statement.\n       #1 ;\n       ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

  wire y;
  reg  a,b;
  reg  error;

  assign y = a && (b ? 0 : 1);

  initial
    begin
       error = 0;
       #1 ;
       b = 1;
       a = 1;
       #1 ;
       if(y !== 0)
         begin
           $display("FAILED");
           error = 1;
         end
       #1 ;
       b = 0;
       #1 ;
       if(y !== 1)
         begin
           $display("FAILED");
           error = 1;
         end
       if(error === 0)
         $display("PASSED");
    end

endmodule
module main;


  wire y;
  reg  a,b;
  reg  error;

  assign y = a && (b ? 0 : 1);

  initial
    begin
       error = 0;
       #1 ;
       b = 1;
       a = 1;
       #1 ;
       if(y !== 0)
         begin
           $display("FAILED");
           error = 1;
         end
       #1 ;
       b = 0;
       #1 ;
       if(y !== 1)
         begin
           $display("FAILED");
           error = 1;
         end
       if(error === 0)
         $display("PASSED");
    end

endmodule