data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/data_memory.v
data/verilator_xmls/5142f011-f1f6-4978-b0be-d5e4dc5bec47.xml
module data_memory(input wire clk, input wire [31:0] addr, input wire signed [31:0] write_data, 
                output reg signed [31:0] read_data, input wire mem_write, input wire mem_read);


reg [31:0] data_mem [0:127];


initial begin




    data_mem[4]= 20;
    data_mem[16]= 10;
    data_mem[20]= 200;
    data_mem[24]= 250;
    data_mem[28]= 350;
    data_mem[32]= 450;
end



always@(negedge clk) begin
    if(mem_read) read_data=data_mem[addr];
    if(mem_write) data_mem[addr]=write_data;
end

endmodule
module data_memory(input wire clk, input wire [31:0] addr, input wire signed [31:0] write_data, 
                output reg signed [31:0] read_data, input wire mem_write, input wire mem_read);



reg [31:0] data_mem [0:127];


initial begin




    data_mem[4]= 20;
    data_mem[16]= 10;
    data_mem[20]= 200;
    data_mem[24]= 250;
    data_mem[28]= 350;
    data_mem[32]= 450;
end



always@(negedge clk) begin
    if(mem_read) read_data=data_mem[addr];
    if(mem_write) data_mem[addr]=write_data;
end

endmodule