data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v
 line:142: before: "*"
1: b'%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:126: Unsupported: Ignoring delay on this delayed statement.\n        #10 a = ~a;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:128: Unsupported: Ignoring delay on this delayed statement.\n        #20 b = ~b;\n        ^\n%Error: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:134: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("descripciones.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:135: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, descripciones);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:143: Unsupported or unknown PLI call: $timeformat\n        $timeformat(-9, 0, "ns", 5);\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:145: Unsupported or unknown PLI call: $monitor\n        $monitor("%t\\t%b\\t%b\\t%b\\t%b\\t%b", $stime, a, b, f_func, f_proc, f_est);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/01_intro/01-3_descripciones/descripciones.v:148: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish;\n        ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module descripciones ();


    reg a = 0, b = 0;



    wire f_func = a & ~b | ~a & b;


    reg f_proc;



    always @(a, b)

    begin

        if (a == 0)
            f_proc = b;

        else
            f_proc = ~b;
    end






    wire f_est;

    wire not_a, not_b, and1_out, and2_out;


    not not1 (not_a, a);
    not not2 (not_b, b);
    and and1 (and1_out, a, not_b);
    and and2 (and2_out, not_a, b);
    or  or1  (f_est, and1_out, and2_out);




    always
        #10 a = ~a;
    always
        #20 b = ~b;


    initial
    begin

        $dumpfile("descripciones.vcd");
        $dumpvars(0, descripciones);







        $timeformat(-9, 0, "ns", 5);
        $display("t\ta\tb\tf_func\tf_proc\tf_est");
        $monitor("%t\t%b\t%b\t%b\t%b\t%b", $stime, a, b, f_func, f_proc, f_est);


        #100 $finish;
    end



endmodule
module descripciones ();



    reg a = 0, b = 0;



    wire f_func = a & ~b | ~a & b;


    reg f_proc;



    always @(a, b)

    begin

        if (a == 0)
            f_proc = b;

        else
            f_proc = ~b;
    end






    wire f_est;

    wire not_a, not_b, and1_out, and2_out;


    not not1 (not_a, a);
    not not2 (not_b, b);
    and and1 (and1_out, a, not_b);
    and and2 (and2_out, not_a, b);
    or  or1  (f_est, and1_out, and2_out);




    always
        #10 a = ~a;
    always
        #20 b = ~b;


    initial
    begin

        $dumpfile("descripciones.vcd");
        $dumpvars(0, descripciones);







        $timeformat(-9, 0, "ns", 5);
        $display("t\ta\tb\tf_func\tf_proc\tf_est");
        $monitor("%t\t%b\t%b\t%b\t%b\t%b", $stime, a, b, f_func, f_proc, f_est);


        #100 $finish;
    end



endmodule