data/full_repos/permissive/206301883/us_timer.v
data/verilator_xmls/d02c7fc4-68b2-4531-8212-456efcec7982.xml
module us_timer(
input wire clk,
output wire [31:0]time_stamp
    );

reg [31:0]count = 0;
reg [6:0]counter = 0;


assign time_stamp = count;


always@(posedge clk) begin
        if (counter == 'h64)
            begin
            counter <= 0;
            count <= count+1;
            end
        else begin counter <= counter + 1'h1; end
	end

endmodule
module us_timer(
input wire clk,
output wire [31:0]time_stamp
    );


reg [31:0]count = 0;
reg [6:0]counter = 0;


assign time_stamp = count;


always@(posedge clk) begin
        if (counter == 'h64)
            begin
            counter <= 0;
            count <= count+1;
            end
        else begin counter <= counter + 1'h1; end
	end

endmodule