data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v
 line:84 column:2: Illegal character '`'
1: b'%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD_2/2) clk_2=~clk_2;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #1000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:21: Cannot find file containing module: \'UARTTransmeter\'\nUARTTransmeter uart_transmeter_0(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTTransmeter\n             data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTTransmeter.v\n             data/full_repos/permissive/106583614/Lab2,data/full_repos/permissive/106583614/UARTTransmeter.sv\n             UARTTransmeter\n             UARTTransmeter.v\n             UARTTransmeter.sv\n             obj_dir/UARTTransmeter\n             obj_dir/UARTTransmeter.v\n             obj_dir/UARTTransmeter.sv\n%Error: data/full_repos/permissive/106583614/Lab2/UARTSystem_tb.v:32: Cannot find file containing module: \'UARTReciver\'\nUARTReciver uart_reciver_0(\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UARTSystem_tb;
reg clk;
reg clk_2;
reg rst_n;

reg [2:0] baud_in;

reg [7:0] Tx_DATA;
reg Tx_EN, Tx_WR;

reg Rx_EN;

wire Rx_PERROR, Rx_FERROR, Rx_VALID;

wire [7:0] Rx_DATA;

wire Tx_BUSY, Tx_D;

UARTTransmeter uart_transmeter_0(
	.clk(clk) ,
	.reset(rst_n) ,
	.Tx_DATA(Tx_DATA) ,
	.baud_select(baud_in) ,
	.Tx_WR(Tx_WR) ,
	.Tx_EN(Tx_EN) ,
	.Tx_D(Tx_D) ,
	.Tx_BUSY(Tx_BUSY)
);

UARTReciver uart_reciver_0(
	.clk(clk_2) ,
	.reset(rst_n) ,
	.baud_select(baud_in) ,
	.Rx_EN(Rx_EN) ,
	.Rx_PERROR(Rx_PERROR) ,
	.Rx_FERROR(Rx_FERROR) ,
	.Rx_DATA(Rx_DATA) ,
	.Rx_VALID(Rx_VALID) ,
	.Rx_D (Tx_D)
);


localparam CLK_PERIOD = 20;
always #(CLK_PERIOD/2) clk=~clk;


localparam CLK_PERIOD_2 = 20;
always #(CLK_PERIOD_2/2) clk_2=~clk_2;

initial 
begin
	clk = 1;
	clk_2 = 1;
	Tx_EN = 1;
	Rx_EN = 1;
	Tx_DATA = 8'b11111110;
	Tx_WR = 0;
	rst_n = 1;
	#10;
	Tx_WR = 1;
	rst_n = 0;
	#10;
	baud_in = 3'b111;
	
	#100;

	#10;
	Tx_WR = 0;
	
	#1000000;
	Tx_DATA = 8'b10111010;
	Tx_WR = 1;

	#20;
	Tx_WR = 0;

	$finish;

end

endmodule
module UARTSystem_tb;

reg clk;
reg clk_2;
reg rst_n;

reg [2:0] baud_in;

reg [7:0] Tx_DATA;
reg Tx_EN, Tx_WR;

reg Rx_EN;

wire Rx_PERROR, Rx_FERROR, Rx_VALID;

wire [7:0] Rx_DATA;

wire Tx_BUSY, Tx_D;

UARTTransmeter uart_transmeter_0(
	.clk(clk) ,
	.reset(rst_n) ,
	.Tx_DATA(Tx_DATA) ,
	.baud_select(baud_in) ,
	.Tx_WR(Tx_WR) ,
	.Tx_EN(Tx_EN) ,
	.Tx_D(Tx_D) ,
	.Tx_BUSY(Tx_BUSY)
);

UARTReciver uart_reciver_0(
	.clk(clk_2) ,
	.reset(rst_n) ,
	.baud_select(baud_in) ,
	.Rx_EN(Rx_EN) ,
	.Rx_PERROR(Rx_PERROR) ,
	.Rx_FERROR(Rx_FERROR) ,
	.Rx_DATA(Rx_DATA) ,
	.Rx_VALID(Rx_VALID) ,
	.Rx_D (Tx_D)
);


localparam CLK_PERIOD = 20;
always #(CLK_PERIOD/2) clk=~clk;


localparam CLK_PERIOD_2 = 20;
always #(CLK_PERIOD_2/2) clk_2=~clk_2;

initial 
begin
	clk = 1;
	clk_2 = 1;
	Tx_EN = 1;
	Rx_EN = 1;
	Tx_DATA = 8'b11111110;
	Tx_WR = 0;
	rst_n = 1;
	#10;
	Tx_WR = 1;
	rst_n = 0;
	#10;
	baud_in = 3'b111;
	
	#100;

	#10;
	Tx_WR = 0;
	
	#1000000;
	Tx_DATA = 8'b10111010;
	Tx_WR = 1;

	#20;
	Tx_WR = 0;

	$finish;

end

endmodule