data/full_repos/permissive/100796583/cpu/MBScore_alu.v
1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n             data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n             MBScore_const.v\n             MBScore_const.v.v\n             MBScore_const.v.sv\n             obj_dir/MBScore_const.v\n             obj_dir/MBScore_const.v.v\n             obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:5: Define or directive not defined: \'`DATA_WIDTH\'\n    input  [`DATA_WIDTH-1:0]        alu_in_a,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:6: Define or directive not defined: \'`DATA_WIDTH\'\n    input  [`DATA_WIDTH-1:0]        alu_in_b,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:7: Define or directive not defined: \'`ALU_OP_WIDTH\'\n    input  [`ALU_OP_WIDTH-1:0]      alu_op_type,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:8: Define or directive not defined: \'`DATA_WIDTH\'\n    output [`DATA_WIDTH-1:0]        alu_out,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:13: Define or directive not defined: \'`DATA_WIDTH\'\n    reg [`DATA_WIDTH-1:0]           alu_out_r;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:18: Define or directive not defined: \'`ALU_OP_ADD\'\n        `ALU_OP_ADD:    {cf_r,alu_out_r} <= {1\'b0 + alu_in_a} + {1\'b0 + alu_in_b};\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:18: syntax error, unexpected \':\', expecting endcase\n        `ALU_OP_ADD:    {cf_r,alu_out_r} <= {1\'b0 + alu_in_a} + {1\'b0 + alu_in_b};\n                   ^\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:19: Define or directive not defined: \'`ALU_OP_ADDU\'\n        `ALU_OP_ADDU:   {cf_r,alu_out_r} <= {1\'b0,alu_in_a + alu_in_b};\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:20: Define or directive not defined: \'`ALU_OP_SUB\'\n        `ALU_OP_SUB:    {cf_r,alu_out_r} <= {1\'b0 + alu_in_a} - {1\'b0 + alu_in_b};\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:21: Define or directive not defined: \'`ALU_OP_SUBU\'\n        `ALU_OP_SUBU:   {cf_r,alu_out_r} <= {1\'b0,alu_in_a - alu_in_b};\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:22: Define or directive not defined: \'`ALU_OP_AND\'\n        `ALU_OP_AND:    {cf_r,alu_out_r} <= {1\'b0,alu_in_a & alu_in_b};\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:23: Define or directive not defined: \'`ALU_OP_OR\'\n        `ALU_OP_OR:     {cf_r,alu_out_r} <= {1\'b0,alu_in_a | alu_in_b};\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:24: Define or directive not defined: \'`ALU_OP_XOR\'\n        `ALU_OP_XOR:    {cf_r,alu_out_r} <= {1\'b0,alu_in_a ^ alu_in_b};\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:25: Define or directive not defined: \'`ALU_OP_NOR\'\n        `ALU_OP_NOR:    {cf_r,alu_out_r} <= {1\'b0,~(alu_in_a | alu_in_b)};\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:26: Define or directive not defined: \'`ALU_OP_SLL\'\n        `ALU_OP_SLL:    {cf_r,alu_out_r} <= {1\'b0,alu_in_b << alu_in_a};\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:27: Define or directive not defined: \'`ALU_OP_SRL\'\n        `ALU_OP_SRL:    {cf_r,alu_out_r} <= {1\'b0,alu_in_b >> alu_in_a};\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:28: Define or directive not defined: \'`ALU_OP_SRA\'\n        `ALU_OP_SRA:    {cf_r,alu_out_r} <= {1\'b0,$signed(alu_in_b) >>> alu_in_a};\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:29: Define or directive not defined: \'`ALU_OP_EQ\'\n        `ALU_OP_EQ:     {cf_r,alu_out_r} <= {1\'b0,(alu_in_a == alu_in_b) ? 32\'d1 : 32\'d0};\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:30: Define or directive not defined: \'`ALU_OP_NE\'\n        `ALU_OP_NE:     {cf_r,alu_out_r} <= {1\'b0,(alu_in_a != alu_in_b) ? 32\'d1 : 32\'d0};\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:31: Define or directive not defined: \'`ALU_OP_LT\'\n        `ALU_OP_LT:     {cf_r,alu_out_r} <= {1\'b0,( $signed(alu_in_a) < $signed(alu_in_b) ) ? 32\'d1 : 32\'d0}; \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:32: Define or directive not defined: \'`ALU_OP_LTU\'\n        `ALU_OP_LTU:    {cf_r,alu_out_r} <= {1\'b0,( alu_in_a < alu_in_b ) ? 32\'d1 : 32\'d0}; \n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:40: syntax error, unexpected endmodule\nendmodule \n^~~~~~~~~\n%Error: Cannot continue\n'
module MBScore_alu(
    input                           clk,
    input                           rst_n,
    input  [`DATA_WIDTH-1:0]        alu_in_a,
    input  [`DATA_WIDTH-1:0]        alu_in_b,
    input  [`ALU_OP_WIDTH-1:0]      alu_op_type,
    output [`DATA_WIDTH-1:0]        alu_out,
    output                          cf
);

    reg                             cf_r;
    reg [`DATA_WIDTH-1:0]           alu_out_r;

    always @(negedge clk)
    begin
        case(alu_op_type)
        `ALU_OP_ADD:    {cf_r,alu_out_r} <= {1'b0 + alu_in_a} + {1'b0 + alu_in_b};
        `ALU_OP_ADDU:   {cf_r,alu_out_r} <= {1'b0,alu_in_a + alu_in_b};
        `ALU_OP_SUB:    {cf_r,alu_out_r} <= {1'b0 + alu_in_a} - {1'b0 + alu_in_b};
        `ALU_OP_SUBU:   {cf_r,alu_out_r} <= {1'b0,alu_in_a - alu_in_b};
        `ALU_OP_AND:    {cf_r,alu_out_r} <= {1'b0,alu_in_a & alu_in_b};
        `ALU_OP_OR:     {cf_r,alu_out_r} <= {1'b0,alu_in_a | alu_in_b};
        `ALU_OP_XOR:    {cf_r,alu_out_r} <= {1'b0,alu_in_a ^ alu_in_b};
        `ALU_OP_NOR:    {cf_r,alu_out_r} <= {1'b0,~(alu_in_a | alu_in_b)};
        `ALU_OP_SLL:    {cf_r,alu_out_r} <= {1'b0,alu_in_b << alu_in_a};
        `ALU_OP_SRL:    {cf_r,alu_out_r} <= {1'b0,alu_in_b >> alu_in_a};
        `ALU_OP_SRA:    {cf_r,alu_out_r} <= {1'b0,$signed(alu_in_b) >>> alu_in_a};
        `ALU_OP_EQ:     {cf_r,alu_out_r} <= {1'b0,(alu_in_a == alu_in_b) ? 32'd1 : 32'd0};
        `ALU_OP_NE:     {cf_r,alu_out_r} <= {1'b0,(alu_in_a != alu_in_b) ? 32'd1 : 32'd0};
        `ALU_OP_LT:     {cf_r,alu_out_r} <= {1'b0,( $signed(alu_in_a) < $signed(alu_in_b) ) ? 32'd1 : 32'd0}; 
        `ALU_OP_LTU:    {cf_r,alu_out_r} <= {1'b0,( alu_in_a < alu_in_b ) ? 32'd1 : 32'd0}; 
        default:        {cf_r,alu_out_r} <= {1'b0,alu_out_r};
        endcase
    end

    assign cf      = cf_r;
    assign alu_out = alu_out_r;

endmodule
module MBScore_alu(
    input                           clk,
    input                           rst_n,
    input  [`DATA_WIDTH-1:0]        alu_in_a,
    input  [`DATA_WIDTH-1:0]        alu_in_b,
    input  [`ALU_OP_WIDTH-1:0]      alu_op_type,
    output [`DATA_WIDTH-1:0]        alu_out,
    output                          cf
);


    reg                             cf_r;
    reg [`DATA_WIDTH-1:0]           alu_out_r;

    always @(negedge clk)
    begin
        case(alu_op_type)
        `ALU_OP_ADD:    {cf_r,alu_out_r} <= {1'b0 + alu_in_a} + {1'b0 + alu_in_b};
        `ALU_OP_ADDU:   {cf_r,alu_out_r} <= {1'b0,alu_in_a + alu_in_b};
        `ALU_OP_SUB:    {cf_r,alu_out_r} <= {1'b0 + alu_in_a} - {1'b0 + alu_in_b};
        `ALU_OP_SUBU:   {cf_r,alu_out_r} <= {1'b0,alu_in_a - alu_in_b};
        `ALU_OP_AND:    {cf_r,alu_out_r} <= {1'b0,alu_in_a & alu_in_b};
        `ALU_OP_OR:     {cf_r,alu_out_r} <= {1'b0,alu_in_a | alu_in_b};
        `ALU_OP_XOR:    {cf_r,alu_out_r} <= {1'b0,alu_in_a ^ alu_in_b};
        `ALU_OP_NOR:    {cf_r,alu_out_r} <= {1'b0,~(alu_in_a | alu_in_b)};
        `ALU_OP_SLL:    {cf_r,alu_out_r} <= {1'b0,alu_in_b << alu_in_a};
        `ALU_OP_SRL:    {cf_r,alu_out_r} <= {1'b0,alu_in_b >> alu_in_a};
        `ALU_OP_SRA:    {cf_r,alu_out_r} <= {1'b0,$signed(alu_in_b) >>> alu_in_a};
        `ALU_OP_EQ:     {cf_r,alu_out_r} <= {1'b0,(alu_in_a == alu_in_b) ? 32'd1 : 32'd0};
        `ALU_OP_NE:     {cf_r,alu_out_r} <= {1'b0,(alu_in_a != alu_in_b) ? 32'd1 : 32'd0};
        `ALU_OP_LT:     {cf_r,alu_out_r} <= {1'b0,( $signed(alu_in_a) < $signed(alu_in_b) ) ? 32'd1 : 32'd0}; 
        `ALU_OP_LTU:    {cf_r,alu_out_r} <= {1'b0,( alu_in_a < alu_in_b ) ? 32'd1 : 32'd0}; 
        default:        {cf_r,alu_out_r} <= {1'b0,alu_out_r};
        endcase
    end

    assign cf      = cf_r;
    assign alu_out = alu_out_r;

endmodule