data/full_repos/permissive/143278/blif/blif_sign_ext_tb.v
 line:24: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/blif/blif_sign_ext_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n         #1;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/blif/blif_sign_ext_tb.v:21: Cannot find file containing module: \'sign_ext\'\n   sign_ext se(.\\D[3] (D[3]), .\\D[2] (D[2]), .\\D[1] (D[1]), .\\D[0] (D[0]),\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/blif,data/full_repos/permissive/143278/sign_ext\n             data/full_repos/permissive/143278/blif,data/full_repos/permissive/143278/sign_ext.v\n             data/full_repos/permissive/143278/blif,data/full_repos/permissive/143278/sign_ext.sv\n             sign_ext\n             sign_ext.v\n             sign_ext.sv\n             obj_dir/sign_ext\n             obj_dir/sign_ext.v\n             obj_dir/sign_ext.sv\n%Warning-WIDTH: data/full_repos/permissive/143278/blif/blif_sign_ext_tb.v:28: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'D\' generates 4 bits.\n                                                                            : ... In instance main\n         q = D;\n           ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   parameter W=3, WO=5;
   reg signed [W:0]  D;
   reg signed [WO:0] q;
   wire [WO:0] Q;

   sign_ext se(.\D[3] (D[3]), .\D[2] (D[2]), .\D[1] (D[1]), .\D[0] (D[0]),
           .\Q[5] (Q[5]), .\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0]));

   int		 ddx;
   initial begin
      for (ddx = 0 ; ddx < 1 << (W+1) ; ddx = ddx+1) begin
	 D = ddx[W:0];
         q = D;

         $display("D = %b, q = %b", D, q);

         #1;
	 if (Q !== q) begin
	    $display("FAILED -- D=%b, Q=%b (should be %b)", D, Q, q);
	    $finish;
         end
      end
      $display("PASSED");
   end

endmodule
module main;


   parameter W=3, WO=5;
   reg signed [W:0]  D;
   reg signed [WO:0] q;
   wire [WO:0] Q;

   sign_ext se(.\D[3] (D[3]), .\D[2] (D[2]), .\D[1] (D[1]), .\D[0] (D[0]),
           .\Q[5] (Q[5]), .\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0]));

   int		 ddx;
   initial begin
      for (ddx = 0 ; ddx < 1 << (W+1) ; ddx = ddx+1) begin
	 D = ddx[W:0];
         q = D;

         $display("D = %b, q = %b", D, q);

         #1;
	 if (Q !== q) begin
	    $display("FAILED -- D=%b, Q=%b (should be %b)", D, Q, q);
	    $finish;
         end
      end
      $display("PASSED");
   end

endmodule