data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v
 line:3: before: "primitive"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:40: Unsupported: Ignoring delay on this delayed statement.\n #50 a=0;b=0;c=0;d=1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:41: Unsupported: Ignoring delay on this delayed statement.\n #50 a=0;b=0;c=1;d=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:42: Unsupported: Ignoring delay on this delayed statement.\n #50 a=0;b=0;c=1;d=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:43: Unsupported: Ignoring delay on this delayed statement.\n #50 a=0;b=1;c=0;d=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:44: Unsupported: Ignoring delay on this delayed statement.\n #50 a=0;b=1;c=0;d=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:45: Unsupported: Ignoring delay on this delayed statement.\n #50 a=0;b=1;c=1;d=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:46: Unsupported: Ignoring delay on this delayed statement.\n #50 a=0;b=1;c=1;d=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:47: Unsupported: Ignoring delay on this delayed statement.\n #50 a=1;b=0;c=0;d=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:48: Unsupported: Ignoring delay on this delayed statement.\n #50 a=1;b=0;c=0;d=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:49: Unsupported: Ignoring delay on this delayed statement.\n #50 a=1;b=0;c=1;d=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:50: Unsupported: Ignoring delay on this delayed statement.\n #50 a=1;b=0;c=1;d=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:51: Unsupported: Ignoring delay on this delayed statement.\n #50 a=1;b=1;c=0;d=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:52: Unsupported: Ignoring delay on this delayed statement.\n #50 a=1;b=1;c=0;d=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:53: Unsupported: Ignoring delay on this delayed statement.\n #50 a=1;b=1;c=1;d=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_majority_function/4_bit_majority_function.v:54: Unsupported: Ignoring delay on this delayed statement.\n #50 a=1;b=1;c=1;d=1;\n ^\n%Error: Exiting due to 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_four_bit_function();
    wire e;
    reg a,b,c,d;
    fourbit G(e,a,b,c,d);
    initial
        begin
	    a=0;b=0;c=0;d=0;
	#50 a=0;b=0;c=0;d=1;
	#50 a=0;b=0;c=1;d=0;
	#50 a=0;b=0;c=1;d=1;
	#50 a=0;b=1;c=0;d=0;
	#50 a=0;b=1;c=0;d=1;
	#50 a=0;b=1;c=1;d=0;
	#50 a=0;b=1;c=1;d=1;
	#50 a=1;b=0;c=0;d=0;
	#50 a=1;b=0;c=0;d=1;
	#50 a=1;b=0;c=1;d=0;
	#50 a=1;b=0;c=1;d=1;
	#50 a=1;b=1;c=0;d=0;
	#50 a=1;b=1;c=0;d=1;
	#50 a=1;b=1;c=1;d=0;
	#50 a=1;b=1;c=1;d=1;
	end
endmodule
module test_four_bit_function();

    wire e;
    reg a,b,c,d;
    fourbit G(e,a,b,c,d);
    initial
        begin
	    a=0;b=0;c=0;d=0;
	#50 a=0;b=0;c=0;d=1;
	#50 a=0;b=0;c=1;d=0;
	#50 a=0;b=0;c=1;d=1;
	#50 a=0;b=1;c=0;d=0;
	#50 a=0;b=1;c=0;d=1;
	#50 a=0;b=1;c=1;d=0;
	#50 a=0;b=1;c=1;d=1;
	#50 a=1;b=0;c=0;d=0;
	#50 a=1;b=0;c=0;d=1;
	#50 a=1;b=0;c=1;d=0;
	#50 a=1;b=0;c=1;d=1;
	#50 a=1;b=1;c=0;d=0;
	#50 a=1;b=1;c=0;d=1;
	#50 a=1;b=1;c=1;d=0;
	#50 a=1;b=1;c=1;d=1;
	end
endmodule