data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/gray2bin.v
data/verilator_xmls/1aa81dba-4765-4114-a7db-3e6c6f149bb2.xml
module gray2bin #(
    parameter WIDTH = 8)
(
    input [WIDTH-1:0] gray,
    output reg [WIDTH-1:0] bin
);

    integer i;
    always @(*) begin
        bin[WIDTH-1] = gray[WIDTH-1];
        for (i = WIDTH-2; i >= 0; i = i - 1) begin
            bin[i] = bin[i+1] ^ gray[i];
        end
    end

endmodule
module gray2bin #(
    parameter WIDTH = 8)
(
    input [WIDTH-1:0] gray,
    output reg [WIDTH-1:0] bin
);


    integer i;
    always @(*) begin
        bin[WIDTH-1] = gray[WIDTH-1];
        for (i = WIDTH-2; i >= 0; i = i - 1) begin
            bin[i] = bin[i+1] ^ gray[i];
        end
    end

endmodule