data/full_repos/permissive/114459345/srcCache/ctrl.v
1: b'%Error: data/full_repos/permissive/114459345/srcCache/ctrl.v:6: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/ctrl.v:19: Define or directive not defined: \'`CtrlWidth\'\n output reg[`CtrlWidth] stall\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ctrl.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n output reg[`CtrlWidth] stall\n                      ^\n%Error: data/full_repos/permissive/114459345/srcCache/ctrl.v:23: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ctrl.v:26: Define or directive not defined: \'`Stop\'\n  else if(req_id == `Stop) begin\n                    ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ctrl.v:29: Define or directive not defined: \'`Stop\'\n  else if(req_if == `Stop) begin\n                    ^~~~~\n%Error: Exiting due to 6 error(s)\n'
module ctrl(

	input wire rst,
	

	input wire req_id,
	

	input wire req_if,
	

	output reg[`CtrlWidth] stall
);

	always @ (*) begin
		if(rst == `RstEnable) begin
			stall <= 6'b000000;
		end
		else if(req_id == `Stop) begin
			stall <= 6'b000111;
		end
		else if(req_if == `Stop) begin
			stall <= 6'b000011;
		end
		else begin
			stall <= 6'b000000;
		end
	end

endmodule
module ctrl(

	input wire rst,
	

	input wire req_id,
	

	input wire req_if,
	

	output reg[`CtrlWidth] stall
);


	always @ (*) begin
		if(rst == `RstEnable) begin
			stall <= 6'b000000;
		end
		else if(req_id == `Stop) begin
			stall <= 6'b000111;
		end
		else if(req_if == `Stop) begin
			stall <= 6'b000011;
		end
		else begin
			stall <= 6'b000000;
		end
	end

endmodule