data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/test_wrmem.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/test_wrmem.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/test_wrmem.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #30 rxlen <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/test_wrmem.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #30 rxlen <= 8;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/test_wrmem.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #30 rxlen <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/test_wrmem.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #30 rxlen <= 8;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/test_wrmem.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #30 rxlen <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/test_wrmem.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #30 rxlen <= 8;\n    ^\n%Error: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/test_wrmem.v:30: Cannot find file containing module: \'test_wrmem_bd_wrapper\'\ntest_wrmem_bd_wrapper i0(.CLK(clk), .XGMII_RESET(reset), .RXD(rxd), .RXLEN(rxlen));\n^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new,data/full_repos/permissive/156650005/test_wrmem_bd_wrapper\n             data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new,data/full_repos/permissive/156650005/test_wrmem_bd_wrapper.v\n             data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new,data/full_repos/permissive/156650005/test_wrmem_bd_wrapper.sv\n             test_wrmem_bd_wrapper\n             test_wrmem_bd_wrapper.v\n             test_wrmem_bd_wrapper.sv\n             obj_dir/test_wrmem_bd_wrapper\n             obj_dir/test_wrmem_bd_wrapper.v\n             obj_dir/test_wrmem_bd_wrapper.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_wrmem();

reg clk;
reg reset;
reg [63:0] rxd;
reg [3:0] rxlen;

initial begin
    clk = 0;
    forever clk = #1 !clk;
end

initial begin
    reset = 1;
    #10 reset = 0;
end

initial begin
    rxd <= 0;
    rxlen <= 8;
    #30 rxlen <= 0;
    #30 rxlen <= 8;
    #30 rxlen <= 0;
    #30 rxlen <= 8;
    #30 rxlen <= 0;
    #30 rxlen <= 8;
end

test_wrmem_bd_wrapper i0(.CLK(clk), .XGMII_RESET(reset), .RXD(rxd), .RXLEN(rxlen));

endmodule
module test_wrmem();


reg clk;
reg reset;
reg [63:0] rxd;
reg [3:0] rxlen;

initial begin
    clk = 0;
    forever clk = #1 !clk;
end

initial begin
    reset = 1;
    #10 reset = 0;
end

initial begin
    rxd <= 0;
    rxlen <= 8;
    #30 rxlen <= 0;
    #30 rxlen <= 8;
    #30 rxlen <= 0;
    #30 rxlen <= 8;
    #30 rxlen <= 0;
    #30 rxlen <= 8;
end

test_wrmem_bd_wrapper i0(.CLK(clk), .XGMII_RESET(reset), .RXD(rxd), .RXLEN(rxlen));

endmodule