data/full_repos/permissive/21702465/source/sirc_handler.v
1: b'%Error: data/full_repos/permissive/21702465/source/sirc_handler.v:88: Cannot find file containing module: \'CLOCK_TRNG\'\n CLOCK_TRNG CLOCK_TRNG1(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21702465/source,data/full_repos/permissive/21702465/CLOCK_TRNG\n             data/full_repos/permissive/21702465/source,data/full_repos/permissive/21702465/CLOCK_TRNG.v\n             data/full_repos/permissive/21702465/source,data/full_repos/permissive/21702465/CLOCK_TRNG.sv\n             CLOCK_TRNG\n             CLOCK_TRNG.v\n             CLOCK_TRNG.sv\n             obj_dir/CLOCK_TRNG\n             obj_dir/CLOCK_TRNG.v\n             obj_dir/CLOCK_TRNG.sv\n%Error: data/full_repos/permissive/21702465/source/sirc_handler.v:103: Cannot find file containing module: \'BUFGMUX_CTRL\'\n BUFGMUX_CTRL MEMCLK (\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/21702465/source/sirc_handler.v:110: Cannot find file containing module: \'RMEM\'\n RMEM rmem1 (\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/21702465/source/sirc_handler.v:340: Bit extraction of array[15:0] requires 4 bit index, not 6 bits.\n                                                                             : ... In instance SircHandler\n       challenge[memCount] <= inputMemoryReadData;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/21702465/source/sirc_handler.v:407: Bit extraction of array[1:0] requires 1 bit index, not 13 bits.\n                                                                             : ... In instance SircHandler\n        outputMemoryWriteData <= response[outputMemoryWriteAdd];\n                                         ^\n%Error: data/full_repos/permissive/21702465/source/sirc_handler.v:444: Cannot find file containing module: \'testPUF\'\n testPUF #(\n ^~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module SircHandler #(













	localparam  IDLE = 0;
	localparam  READING_IN_PARAMETERS = 1;
	localparam  READ = 2;
	localparam  WAIT_READ = 3;
	localparam  COMPUTE = 4;
	localparam  WRITE = 5;



	reg [2:0] currState;




	reg	[7:0]	challenge [0:15];
	reg	[7:0]	response	[0:1];




	wire [127:0] challengeReg;
	wire [15:0]	responseReg;


	reg [31:0]	responseRegBuffer;




	assign challengeReg = {
		challenge[15],challenge[14],challenge[13],challenge[12],challenge[11],challenge[10],challenge[9],challenge[8],
		challenge[7],challenge[6],challenge[5],challenge[4],challenge[3],challenge[2],challenge[1],challenge[0]};


	always @(*) begin
		{response[0], response[1]} <= responseReg;
	end


	reg paramCount;


	reg [31:0] op_mode;
	reg [31:0] pc_challenge;
	
	reg calibrate;
	reg read_temp;
	reg test_start;
	wire test_done;


	assign register32WriteData = 32'd0;
	assign register32WriteEn = 0;
	assign outputMemoryWriteByteMask = {OUTMEM_BYTE_WIDTH{1'b1}};


	reg inputDone;
	reg [5:0] memCount;
	reg [4:0] regCount;
	reg [7:0] bitCount;
	reg [5:0] resp_wait_count;
	reg [5:0] slowRmemCount;


	reg challenge_ready;
	wire response_ready;

	initial begin
		currState = IDLE;
		pc_challenge = 0;
		op_mode = 0;

		userRunClear = 0;

		register32Address = 0;

		inputMemoryReadReq = 0;
		inputMemoryReadAdd = 0;

		outputMemoryWriteReq = 0;
		outputMemoryWriteAdd = 0;
		outputMemoryWriteData = 0;

		paramCount = 0;

		inputDone = 0;
		challenge_ready = 0;
	end


	always @(posedge clk) begin
		if(reset) begin
			currState <= IDLE;

			userRunClear <= 0;

			register32Address <= 0;

			inputMemoryReadReq <= 0;
			inputMemoryReadAdd <= 0;

			outputMemoryWriteReq <= 0;
			outputMemoryWriteAdd <= 0;
			outputMemoryWriteData <= 0;

			paramCount <= 0;

			inputDone <= 0;
			challenge_ready <= 0;

		end
		else begin
			case(currState)
				IDLE: begin

					userRunClear <= 0;
					inputMemoryReadReq <= 0;
					challenge_ready <= 0;


					if(userRunValue == 1 && userRunClear != 1) begin

						currState <= READING_IN_PARAMETERS;
						register32Address <= 0;
						register32CmdReq <= 1;
						paramCount <= 0;
					end
				end
				READING_IN_PARAMETERS: begin


					if(register32CmdAck == 1 && register32CmdReq == 1) begin
						register32Address <= register32Address + 1;
					end


					if(register32CmdAck == 1 && register32Address == 8'd1)begin
						register32CmdReq <= 0;
					end


					if(register32ReadDataValid) begin
							op_mode <= pc_challenge;
							pc_challenge <= register32ReadData;
							paramCount <= 1;


							if(paramCount == 1)begin

								currState <= READ;
								inputMemoryReadReq <= 1;
								inputMemoryReadAdd <= 0;
								outputMemoryWriteAdd <= 0;
								inputDone <= 0;
								memCount <= 0;
								

								

								if(op_mode == 32'h00000000) begin
									calibrate <= 1;
									read_temp <= 0;
								end
								

								else if (op_mode == 32'h00000001) begin
									read_temp <= 1;
									calibrate <= 0;
								end
								

								else begin
									calibrate <= 0;
									read_temp <= 0;
								end
								

								
							end
					end
				end
				READ: begin

					if(inputDone == 0) begin
						inputMemoryReadReq <= 1;
					end
					else begin
						inputMemoryReadReq <= 0;
					end


					if(inputMemoryReadReq == 1 && inputMemoryReadAck == 1 && inputMemoryReadAdd != 15)begin
						inputMemoryReadAdd <= inputMemoryReadAdd + 1;
						currState <= WAIT_READ;
					end
					else if(inputMemoryReadReq == 1 && inputMemoryReadAck == 1 && inputMemoryReadAdd == 15)begin
						inputDone <= 1;
						currState <= WAIT_READ;
					end
				end

				WAIT_READ: begin
					if (inputMemoryReadDataValid == 1) begin

						if(memCount <= 15) begin
							challenge[memCount] <= inputMemoryReadData;
							memCount <= memCount+1;
							currState <= READ;
						end
						else begin
							currState <= COMPUTE;
							regCount <= 0;
							bitCount <= 0;
							resp_wait_count <= 0;
							challenge_ready <= 0;
						end
					end
				end

				COMPUTE: begin



					if(regCount == 0) begin
						challenge_ready <= 1;
						regCount <= regCount+1;
					end
					else begin
						challenge_ready <= 0;
					end


					if(calibrate == 1) begin						
						if(resp_wait_count == 10) begin
							currState <= WRITE;
							memCount <= 0;
							regCount <= 0;
							outputMemoryWriteAdd <= 0;
						end
						
						resp_wait_count <= resp_wait_count + 1;
					end
					

					if(calibrate != 1) begin
						test_start <= 1;
						
						if(test_done == 1) begin
							currState <= WRITE;
							memCount <= 0;
							regCount <= 0;
							test_start <= 0;
							outputMemoryWriteAdd <= 0;
							

							raddr <= 0;
							slowRmemCount <= 0;
						end
					end

				end

				WRITE: begin
					outputMemoryWriteReq <= 1;
					

					if(slowRmemCount == 10) begin
						slowRmemCount <= 0;
						

						if(calibrate == 1) begin
							if(outputMemoryWriteAdd <= 1) begin
								outputMemoryWriteData <= response[outputMemoryWriteAdd];
							end
						end
						

						else begin
							outputMemoryWriteData <= douta;
						end



						if(outputMemoryWriteReq == 1  && outputMemoryWriteAck == 1 && outputMemoryWriteAdd != 550) begin
							outputMemoryWriteAdd <= outputMemoryWriteAdd + 1;
							raddr <= raddr + 1;
							memCount <= memCount+1;
							currState <= WRITE;
						end


						if(outputMemoryWriteReq == 1  && outputMemoryWriteAck == 1 && outputMemoryWriteAdd == 550) begin
							outputMemoryWriteReq <= 0;
							currState <= IDLE;
							userRunClear <= 1;
						end
					end
					
					else begin
						slowRmemCount <= slowRmemCount + 1;
					end
					
				end

			endcase
		end
   end


	testPUF #(
		.N_CB(N_CB),
		.CHALLENGE_WIDTH(32),
		.PDL_CONFIG_WIDTH(128),
		.RESPONSE_WIDTH(6)
		) testPUF(

	    .clk_1(clk_1),
	    .clk_2(clk_2),
	    .clk_RNG(clk_RNG),
		 .rst(RST),

		 .sw(sw),
	    .mem_we(wea),
	    .mem_waddr(waddr),
	    .mem_din(dina),



	   .clk(clk),
		.reset(reset),
		.calb_trigger(challenge_ready),
		.pdl_config(challengeReg),
		.pc_challenge(pc_challenge[31:0]),
		.done(response_ready),
		.raw_response(responseReg[5:0]),
		
		.calibrate(calibrate),
		.read_temp(read_temp),
		.test_start(test_start),
		.test_done(test_done),
		.LED(LED)
	 );

endmodule
module SircHandler #(













	localparam  IDLE = 0;

	localparam  READING_IN_PARAMETERS = 1;
	localparam  READ = 2;
	localparam  WAIT_READ = 3;
	localparam  COMPUTE = 4;
	localparam  WRITE = 5;



	reg [2:0] currState;




	reg	[7:0]	challenge [0:15];
	reg	[7:0]	response	[0:1];




	wire [127:0] challengeReg;
	wire [15:0]	responseReg;


	reg [31:0]	responseRegBuffer;




	assign challengeReg = {
		challenge[15],challenge[14],challenge[13],challenge[12],challenge[11],challenge[10],challenge[9],challenge[8],
		challenge[7],challenge[6],challenge[5],challenge[4],challenge[3],challenge[2],challenge[1],challenge[0]};


	always @(*) begin
		{response[0], response[1]} <= responseReg;
	end


	reg paramCount;


	reg [31:0] op_mode;
	reg [31:0] pc_challenge;
	
	reg calibrate;
	reg read_temp;
	reg test_start;
	wire test_done;


	assign register32WriteData = 32'd0;
	assign register32WriteEn = 0;
	assign outputMemoryWriteByteMask = {OUTMEM_BYTE_WIDTH{1'b1}};


	reg inputDone;
	reg [5:0] memCount;
	reg [4:0] regCount;
	reg [7:0] bitCount;
	reg [5:0] resp_wait_count;
	reg [5:0] slowRmemCount;


	reg challenge_ready;
	wire response_ready;

	initial begin
		currState = IDLE;
		pc_challenge = 0;
		op_mode = 0;

		userRunClear = 0;

		register32Address = 0;

		inputMemoryReadReq = 0;
		inputMemoryReadAdd = 0;

		outputMemoryWriteReq = 0;
		outputMemoryWriteAdd = 0;
		outputMemoryWriteData = 0;

		paramCount = 0;

		inputDone = 0;
		challenge_ready = 0;
	end


	always @(posedge clk) begin
		if(reset) begin
			currState <= IDLE;

			userRunClear <= 0;

			register32Address <= 0;

			inputMemoryReadReq <= 0;
			inputMemoryReadAdd <= 0;

			outputMemoryWriteReq <= 0;
			outputMemoryWriteAdd <= 0;
			outputMemoryWriteData <= 0;

			paramCount <= 0;

			inputDone <= 0;
			challenge_ready <= 0;

		end
		else begin
			case(currState)
				IDLE: begin

					userRunClear <= 0;
					inputMemoryReadReq <= 0;
					challenge_ready <= 0;


					if(userRunValue == 1 && userRunClear != 1) begin

						currState <= READING_IN_PARAMETERS;
						register32Address <= 0;
						register32CmdReq <= 1;
						paramCount <= 0;
					end
				end
				READING_IN_PARAMETERS: begin


					if(register32CmdAck == 1 && register32CmdReq == 1) begin
						register32Address <= register32Address + 1;
					end


					if(register32CmdAck == 1 && register32Address == 8'd1)begin
						register32CmdReq <= 0;
					end


					if(register32ReadDataValid) begin
							op_mode <= pc_challenge;
							pc_challenge <= register32ReadData;
							paramCount <= 1;


							if(paramCount == 1)begin

								currState <= READ;
								inputMemoryReadReq <= 1;
								inputMemoryReadAdd <= 0;
								outputMemoryWriteAdd <= 0;
								inputDone <= 0;
								memCount <= 0;
								

								

								if(op_mode == 32'h00000000) begin
									calibrate <= 1;
									read_temp <= 0;
								end
								

								else if (op_mode == 32'h00000001) begin
									read_temp <= 1;
									calibrate <= 0;
								end
								

								else begin
									calibrate <= 0;
									read_temp <= 0;
								end
								

								
							end
					end
				end
				READ: begin

					if(inputDone == 0) begin
						inputMemoryReadReq <= 1;
					end
					else begin
						inputMemoryReadReq <= 0;
					end


					if(inputMemoryReadReq == 1 && inputMemoryReadAck == 1 && inputMemoryReadAdd != 15)begin
						inputMemoryReadAdd <= inputMemoryReadAdd + 1;
						currState <= WAIT_READ;
					end
					else if(inputMemoryReadReq == 1 && inputMemoryReadAck == 1 && inputMemoryReadAdd == 15)begin
						inputDone <= 1;
						currState <= WAIT_READ;
					end
				end

				WAIT_READ: begin
					if (inputMemoryReadDataValid == 1) begin

						if(memCount <= 15) begin
							challenge[memCount] <= inputMemoryReadData;
							memCount <= memCount+1;
							currState <= READ;
						end
						else begin
							currState <= COMPUTE;
							regCount <= 0;
							bitCount <= 0;
							resp_wait_count <= 0;
							challenge_ready <= 0;
						end
					end
				end

				COMPUTE: begin



					if(regCount == 0) begin
						challenge_ready <= 1;
						regCount <= regCount+1;
					end
					else begin
						challenge_ready <= 0;
					end


					if(calibrate == 1) begin						
						if(resp_wait_count == 10) begin
							currState <= WRITE;
							memCount <= 0;
							regCount <= 0;
							outputMemoryWriteAdd <= 0;
						end
						
						resp_wait_count <= resp_wait_count + 1;
					end
					

					if(calibrate != 1) begin
						test_start <= 1;
						
						if(test_done == 1) begin
							currState <= WRITE;
							memCount <= 0;
							regCount <= 0;
							test_start <= 0;
							outputMemoryWriteAdd <= 0;
							

							raddr <= 0;
							slowRmemCount <= 0;
						end
					end

				end

				WRITE: begin
					outputMemoryWriteReq <= 1;
					

					if(slowRmemCount == 10) begin
						slowRmemCount <= 0;
						

						if(calibrate == 1) begin
							if(outputMemoryWriteAdd <= 1) begin
								outputMemoryWriteData <= response[outputMemoryWriteAdd];
							end
						end
						

						else begin
							outputMemoryWriteData <= douta;
						end



						if(outputMemoryWriteReq == 1  && outputMemoryWriteAck == 1 && outputMemoryWriteAdd != 550) begin
							outputMemoryWriteAdd <= outputMemoryWriteAdd + 1;
							raddr <= raddr + 1;
							memCount <= memCount+1;
							currState <= WRITE;
						end


						if(outputMemoryWriteReq == 1  && outputMemoryWriteAck == 1 && outputMemoryWriteAdd == 550) begin
							outputMemoryWriteReq <= 0;
							currState <= IDLE;
							userRunClear <= 1;
						end
					end
					
					else begin
						slowRmemCount <= slowRmemCount + 1;
					end
					
				end

			endcase
		end
   end


	testPUF #(
		.N_CB(N_CB),
		.CHALLENGE_WIDTH(32),
		.PDL_CONFIG_WIDTH(128),
		.RESPONSE_WIDTH(6)
		) testPUF(

	    .clk_1(clk_1),
	    .clk_2(clk_2),
	    .clk_RNG(clk_RNG),
		 .rst(RST),

		 .sw(sw),
	    .mem_we(wea),
	    .mem_waddr(waddr),
	    .mem_din(dina),



	   .clk(clk),
		.reset(reset),
		.calb_trigger(challenge_ready),
		.pdl_config(challengeReg),
		.pc_challenge(pc_challenge[31:0]),
		.done(response_ready),
		.raw_response(responseReg[5:0]),
		
		.calibrate(calibrate),
		.read_temp(read_temp),
		.test_start(test_start),
		.test_done(test_done),
		.LED(LED)
	 );

endmodule