data/full_repos/permissive/147086086/Lab3/hw/fm_transmitter/fm_transmitter.v
1: b"%Error: data/full_repos/permissive/147086086/Lab3/hw/fm_transmitter/fm_transmitter.v:21: Cannot find file containing module: 'mypll'\nmypll pll_inst(.inclk0 (MAX10_CLK1_50),\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/147086086/Lab3/hw/fm_transmitter,data/full_repos/permissive/147086086/mypll\n             data/full_repos/permissive/147086086/Lab3/hw/fm_transmitter,data/full_repos/permissive/147086086/mypll.v\n             data/full_repos/permissive/147086086/Lab3/hw/fm_transmitter,data/full_repos/permissive/147086086/mypll.sv\n             mypll\n             mypll.v\n             mypll.sv\n             obj_dir/mypll\n             obj_dir/mypll.v\n             obj_dir/mypll.sv\n%Error: data/full_repos/permissive/147086086/Lab3/hw/fm_transmitter/fm_transmitter.v:26: Cannot find file containing module: 'simple_uart_receiver'\nsimple_uart_receiver uart_rec(.i_clk (sys_clk), \n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module fm_transmitter(MAX10_CLK1_50, GPIO, KEY, LEDR);

input           MAX10_CLK1_50;
inout   [35:0]  GPIO;
input   [1:0]   KEY;
output  [9:0]   LEDR;

parameter   NCO_PHASE_STEP_CARRIER = 32'h5C28_F5C2;

wire    sys_rst_n = KEY[0];
wire    sys_clk;

wire    [7:0]   uart_dat;
reg     [7:0]   sample;

reg     [31:0]  nco_phase;
reg     [31:0]  nco_phase_step;
wire    [31:0]  nco_phase_step_carrier = NCO_PHASE_STEP_CARRIER;
wire    [31:0]  nco_phase_step_deviation = { {(32-8-13){sample[7]}}, sample, 13'b0 };

mypll pll_inst(.inclk0 (MAX10_CLK1_50),
                .c0 (sys_clk),
                .locked (LEDR[0])
                );
    
simple_uart_receiver uart_rec(.i_clk (sys_clk), 
                                .i_rst_n (sys_rst_n), 
                                .i_rx (GPIO[0]), 
                                .o_dat (uart_dat), 
                                .o_dat_vld ()
                                );
                               
always @(posedge sys_clk)
    sample <= uart_dat - 128;
    
always @(posedge sys_clk)
    nco_phase_step <= nco_phase_step_carrier + nco_phase_step_deviation;
    
always @(posedge sys_clk)
    nco_phase <= nco_phase + nco_phase_step;

assign GPIO[35] = nco_phase[31];
                                
endmodule
module fm_transmitter(MAX10_CLK1_50, GPIO, KEY, LEDR);


input           MAX10_CLK1_50;
inout   [35:0]  GPIO;
input   [1:0]   KEY;
output  [9:0]   LEDR;

parameter   NCO_PHASE_STEP_CARRIER = 32'h5C28_F5C2;

wire    sys_rst_n = KEY[0];
wire    sys_clk;

wire    [7:0]   uart_dat;
reg     [7:0]   sample;

reg     [31:0]  nco_phase;
reg     [31:0]  nco_phase_step;
wire    [31:0]  nco_phase_step_carrier = NCO_PHASE_STEP_CARRIER;
wire    [31:0]  nco_phase_step_deviation = { {(32-8-13){sample[7]}}, sample, 13'b0 };

mypll pll_inst(.inclk0 (MAX10_CLK1_50),
                .c0 (sys_clk),
                .locked (LEDR[0])
                );
    
simple_uart_receiver uart_rec(.i_clk (sys_clk), 
                                .i_rst_n (sys_rst_n), 
                                .i_rx (GPIO[0]), 
                                .o_dat (uart_dat), 
                                .o_dat_vld ()
                                );
                               
always @(posedge sys_clk)
    sample <= uart_dat - 128;
    
always @(posedge sys_clk)
    nco_phase_step <= nco_phase_step_carrier + nco_phase_step_deviation;
    
always @(posedge sys_clk)
    nco_phase <= nco_phase + nco_phase_step;

assign GPIO[35] = nco_phase[31];
                                
endmodule