data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv
 line:24: before: "class"
1: b'%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:24: Unsupported: classes\nclass temp_capp_tag;\n^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:28: Unsupported: classes\nclass init_data;\n^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:44: Unsupported: classes\nclass bridge_axi_item;\n^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n    constraint addr_range{\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:60: syntax error, unexpected IDENTIFIER\n    constraint addr_range{\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:67: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n    constraint size_len_range{\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:93: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n    constraint rand_all_resp{\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:93: syntax error, unexpected IDENTIFIER\n    constraint rand_all_resp{\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:174: Unsupported: new constructor\n    function new(string name = "reg_addr");\n             ^~~\n%Warning-ENDLABEL: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:176: End label \'reg_addr\' does not match begin label \'bridge_axi_item\'\nendclass: reg_addr\n^~~~~~~~\n                   ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:178: Unsupported: classes\nclass reg_rst_value;  \n^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:195: Unsupported: new constructor\n    function new(string name = "reg_rst_value");\n             ^~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:199: Unsupported: classes\nclass init_host_mem;\n^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:200: syntax error, unexpected ::, expecting \'(\' or \';\'\n    function host_mem_model::byte_packet_queue init_data_queue(int length);\n                           ^~\n                                                                                                      : ... Perhaps \'host_mem_model\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:201: Unsupported: new with arguments\n        init_data init_data_item=new();                \n                                 ^~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:202: syntax error, unexpected for\n        for(int i=0; i<length; i++)begin\n        ^~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:203: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n            void\'(init_data_item.randomize());\n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:216: Define or directive not defined: \'`uvm_object_utils\'\n    `uvm_object_utils(bfm_seq_return_initial_credits)\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:228: Unsupported: new constructor\n    function new(string name= "bfm_seq_return_initial_credits");\n             ^~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:229: Unsupported: super\n        super.new(name);\n        ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:229: Unsupported: new with arguments\n        super.new(name);\n              ^~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:229: Unsupported: dotted new\n        super.new(name);\n        ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:277: Define or directive not defined: \'`uvm_do_on_with\'\n            `uvm_do_on_with(trans, p_sequencer.tx_sqr, {trans.packet_type==tl_tx_trans::RETURN_TLX_CREDITS; trans.tlx_vc_0==temp_tlx_vc_0; \n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:277: syntax error, unexpected \',\'\n            `uvm_do_on_with(trans, p_sequencer.tx_sqr, {trans.packet_type==tl_tx_trans::RETURN_TLX_CREDITS; trans.tlx_vc_0==temp_tlx_vc_0; \n                                 ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:277: syntax error, unexpected \';\'\n            `uvm_do_on_with(trans, p_sequencer.tx_sqr, {trans.packet_type==tl_tx_trans::RETURN_TLX_CREDITS; trans.tlx_vc_0==temp_tlx_vc_0; \n                                                                                                                                         ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:278: syntax error, unexpected \';\'\n                                                        trans.tlx_vc_3==temp_tlx_vc_3;trans.tlx_dcp_0==temp_tlx_dcp_0;trans.tlx_dcp_3==temp_tlx_dcp_3;})\n                                                                                     ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:278: syntax error, unexpected \';\'\n                                                        trans.tlx_vc_3==temp_tlx_vc_3;trans.tlx_dcp_0==temp_tlx_dcp_0;trans.tlx_dcp_3==temp_tlx_dcp_3;})\n                                                                                                                     ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:278: syntax error, unexpected \';\'\n                                                        trans.tlx_vc_3==temp_tlx_vc_3;trans.tlx_dcp_0==temp_tlx_dcp_0;trans.tlx_dcp_3==temp_tlx_dcp_3;})\n                                                                                                                                                     ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:292: Define or directive not defined: \'`uvm_object_utils\'\n    `uvm_object_utils(bfm_seq_initial_config)\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:294: syntax error, unexpected IDENTIFIER\n    tl_tx_trans trans;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:300: syntax error, unexpected IDENTIFIER, expecting "\'{"\n    bit [63:0] temp_data_carrier;\n               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:303: Unsupported: super\n        super.new(name);\n        ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:303: Unsupported: new with arguments\n        super.new(name);\n              ^~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:303: Unsupported: dotted new\n        super.new(name);\n        ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:304: syntax error, unexpected endfunction\n    endfunction: new\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:317: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n            void\'(capp_tag.randomize());\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:317: syntax error, unexpected \'(\'\n            void\'(capp_tag.randomize());\n                                     ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:318: Define or directive not defined: \'`uvm_do_on_with\'\n            `uvm_do_on_with(trans, p_sequencer.tx_sqr, {trans.packet_type==tl_tx_trans::CONFIG_READ; trans.plength==temp_plength; trans.config_type==0;\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:318: syntax error, unexpected \',\'\n            `uvm_do_on_with(trans, p_sequencer.tx_sqr, {trans.packet_type==tl_tx_trans::CONFIG_READ; trans.plength==temp_plength; trans.config_type==0;\n                                 ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:318: syntax error, unexpected \';\'\n            `uvm_do_on_with(trans, p_sequencer.tx_sqr, {trans.packet_type==tl_tx_trans::CONFIG_READ; trans.plength==temp_plength; trans.config_type==0;\n                                                                                                                                ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:318: syntax error, unexpected \';\'\n            `uvm_do_on_with(trans, p_sequencer.tx_sqr, {trans.packet_type==tl_tx_trans::CONFIG_READ; trans.plength==temp_plength; trans.config_type==0;\n                                                                                                                                                      ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:319: syntax error, unexpected \';\'\n                                                        trans.capp_tag==capp_tag.capp; trans.physical_addr==temp_addr;})\n                                                                                     ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:319: syntax error, unexpected \';\'\n                                                        trans.capp_tag==capp_tag.capp; trans.physical_addr==temp_addr;})\n                                                                                                                     ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:325: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n            void\'(capp_tag.randomize());\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:325: syntax error, unexpected \'(\'\n            void\'(capp_tag.randomize());\n                                     ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:326: Define or directive not defined: \'`uvm_do_on_with\'\n            `uvm_do_on_with(trans, p_sequencer.tx_sqr, {trans.packet_type==tl_tx_trans::CONFIG_WRITE; trans.plength==temp_plength; trans.config_type==0;\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:326: syntax error, unexpected \',\'\n            `uvm_do_on_with(trans, p_sequencer.tx_sqr, {trans.packet_type==tl_tx_trans::CONFIG_WRITE; trans.plength==temp_plength; trans.config_type==0;\n                                 ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:326: syntax error, unexpected \';\'\n            `uvm_do_on_with(trans, p_sequencer.tx_sqr, {trans.packet_type==tl_tx_trans::CONFIG_WRITE; trans.plength==temp_plength; trans.config_type==0;\n                                                                                                                                 ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:326: syntax error, unexpected \';\'\n            `uvm_do_on_with(trans, p_sequencer.tx_sqr, {trans.packet_type==tl_tx_trans::CONFIG_WRITE; trans.plength==temp_plength; trans.config_type==0;\n                                                                                                                                                       ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:327: syntax error, unexpected \';\'\n                                                        trans.capp_tag==capp_tag.capp; trans.physical_addr==temp_addr;\n                                                                                     ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/seq_lib/bfm_seq_lib.sv:327: syntax error, unexpected \';\'\n                                                        trans.capp_tag==capp_tag.capp; trans.physical_addr==temp_addr;\n                                                                                                                     ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
function new(string name= "bfm_seq_write_4k");
        super.new(name);
    endfunction
function new(string name= "bfm_seq_write_4k");

        super.new(name);
    endfunction