data/full_repos/permissive/153960117/hdl/bias_add_tb.v
 line:56: before: "signed"
1: b'%Error: data/full_repos/permissive/153960117/hdl/bias_add_tb.v:18: Cannot find include file: bias_add.v\n`include "bias_add.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/153960117/hdl,data/full_repos/permissive/153960117/bias_add.v\n             data/full_repos/permissive/153960117/hdl,data/full_repos/permissive/153960117/bias_add.v.v\n             data/full_repos/permissive/153960117/hdl,data/full_repos/permissive/153960117/bias_add.v.sv\n             bias_add.v\n             bias_add.v.v\n             bias_add.v.sv\n             obj_dir/bias_add.v\n             obj_dir/bias_add.v.v\n             obj_dir/bias_add.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/153960117/hdl/bias_add_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/153960117/hdl/bias_add_tb.v:31: Unsupported: event data types\n    event end_trigger;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/153960117/hdl/bias_add_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    initial #1 display_header();\n            ^\n%Error: data/full_repos/permissive/153960117/hdl/bias_add_tb.v:137: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/bias_add_tb.v:150: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/bias_add_tb.v:167: syntax error, unexpected \'@\'\n        repeat(5) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/153960117/hdl/bias_add_tb.v:172: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/bias_add_tb.v:177: syntax error, unexpected \'@\'\n            @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/153960117/hdl/bias_add_tb.v:182: syntax error, unexpected \'@\'\n        repeat(10) @(negedge clk);\n                   ^\n%Error: data/full_repos/permissive/153960117/hdl/bias_add_tb.v:188: syntax error, unexpected ->\n        -> end_trigger;\n        ^~\n%Error: Exiting due to 9 error(s), 2 warning(s)\n'
module bias_add_tb;




    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam NUM_WIDTH    = 16;
    localparam NUM_POINT    = 8;



    function real num_f2r;
        input signed [NUM_WIDTH-1:0] value;

        begin
            num_f2r = value / ((1<<NUM_POINT) * 1.0);
        end
    endfunction


    function signed [NUM_WIDTH-1:0] num_r2f;
        input real value;

        begin
            num_r2f = value * (1<<(NUM_POINT));
        end
    endfunction


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'bias_add'");
    end
`endif




    reg         [NUM_WIDTH-1:0] bias;
    reg         [NUM_WIDTH-1:0] up_data;
    wire signed [NUM_WIDTH-1:0] dn_data;


    reg                         up_valid;
    reg                         dn_valid;




    bias_add #(
        .NUM_WIDTH  (NUM_WIDTH))
    uut (
        .clk        (clk),

        .bias       (bias),

        .up_data    (up_data),
        .dn_data    (dn_data)
    );



    always @(posedge clk)
        dn_valid <= up_valid;




    task display_signals;
        $display(
            "%d",
            $time,

            "\t<bias> %f",
            num_f2r(bias),

            "\t<up> %b %f  ",
            up_valid,
            num_f2r(up_data),

            "\t<dn> %b %f",
            dn_valid,
            num_f2r(dn_data),

        );

    endtask

    task display_header;
        $display(
            "\t\ttime",

            "\t\tbias",

            "\t\tup",

            "\t\t\tdn",
        );
    endtask




    initial begin


        bias        = num_r2f(2.5);
        up_data     = 'b0;
        up_valid    = 1'b0;



        repeat(5) @(negedge clk);

`ifdef TB_VERBOSE
    $display("send data");
`endif
        @(negedge clk);

        repeat(20) begin
            up_valid    <= 1'b1;
            up_data     <= num_r2f(num_f2r(up_data)+1.0);
            @(negedge clk);
        end

        up_valid    <= 1'b0;
        up_data     <= 'b0;
        repeat(10) @(negedge clk);


`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule
module bias_add_tb;





    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam NUM_WIDTH    = 16;
    localparam NUM_POINT    = 8;



    function real num_f2r;
        input signed [NUM_WIDTH-1:0] value;

        begin
            num_f2r = value / ((1<<NUM_POINT) * 1.0);
        end
    endfunction


    function signed [NUM_WIDTH-1:0] num_r2f;
        input real value;

        begin
            num_r2f = value * (1<<(NUM_POINT));
        end
    endfunction


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'bias_add'");
    end
`endif




    reg         [NUM_WIDTH-1:0] bias;
    reg         [NUM_WIDTH-1:0] up_data;
    wire signed [NUM_WIDTH-1:0] dn_data;


    reg                         up_valid;
    reg                         dn_valid;




    bias_add #(
        .NUM_WIDTH  (NUM_WIDTH))
    uut (
        .clk        (clk),

        .bias       (bias),

        .up_data    (up_data),
        .dn_data    (dn_data)
    );



    always @(posedge clk)
        dn_valid <= up_valid;




    task display_signals;
        $display(
            "%d",
            $time,

            "\t<bias> %f",
            num_f2r(bias),

            "\t<up> %b %f  ",
            up_valid,
            num_f2r(up_data),

            "\t<dn> %b %f",
            dn_valid,
            num_f2r(dn_data),

        );

    endtask

    task display_header;
        $display(
            "\t\ttime",

            "\t\tbias",

            "\t\tup",

            "\t\t\tdn",
        );
    endtask




    initial begin


        bias        = num_r2f(2.5);
        up_data     = 'b0;
        up_valid    = 1'b0;



        repeat(5) @(negedge clk);

`ifdef TB_VERBOSE
    $display("send data");
`endif
        @(negedge clk);

        repeat(20) begin
            up_valid    <= 1'b1;
            up_data     <= num_r2f(num_f2r(up_data)+1.0);
            @(negedge clk);
        end

        up_valid    <= 1'b0;
        up_data     <= 'b0;
        repeat(10) @(negedge clk);


`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule