data/full_repos/permissive/143278/ivltests/binary_nand.v
 line:26: before: "~&"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/binary_nand.v:32: Unsupported: Ignoring delay on this delayed statement.\n #1 result1 = A ~& B;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/binary_nand.v:43: Unsupported: Ignoring delay on this delayed statement.\n #1 result1 = A ~& B;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/binary_nand.v:54: Unsupported: Ignoring delay on this delayed statement.\n #1 result1 = A ~& B;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/binary_nand.v:65: Unsupported: Ignoring delay on this delayed statement.\n #1 result1 = A ~& B;\n ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg A, B;
   reg result1;
   wire result2 = A ~& B;

   initial
     begin
	A = 0;
	B = 0;
	#1 result1 = A ~& B;
	if (result1 !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end
	if (result2 !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

	A = 1;
	#1 result1 = A ~& B;
	if (result1 !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end
	if (result2 !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

	B = 1;
	#1 result1 = A ~& B;
	if (result1 !== 1'b0) begin
	   $display("FAILED");
	   $finish;
	end
	if (result2 !== 1'b0) begin
	   $display("FAILED");
	   $finish;
	end

	A = 0;
	#1 result1 = A ~& B;
	if (result1 !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end
	if (result2 !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

	$display("PASSED");
     end

endmodule
module main;


   reg A, B;
   reg result1;
   wire result2 = A ~& B;

   initial
     begin
	A = 0;
	B = 0;
	#1 result1 = A ~& B;
	if (result1 !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end
	if (result2 !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

	A = 1;
	#1 result1 = A ~& B;
	if (result1 !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end
	if (result2 !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

	B = 1;
	#1 result1 = A ~& B;
	if (result1 !== 1'b0) begin
	   $display("FAILED");
	   $finish;
	end
	if (result2 !== 1'b0) begin
	   $display("FAILED");
	   $finish;
	end

	A = 0;
	#1 result1 = A ~& B;
	if (result1 !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end
	if (result2 !== 1'b1) begin
	   $display("FAILED");
	   $finish;
	end

	$display("PASSED");
     end

endmodule