data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:1: Cannot find include file: Util/Math.v\n`include "Util/Math.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu,data/full_repos/permissive/131921633/Util/Math.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu,data/full_repos/permissive/131921633/Util/Math.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu,data/full_repos/permissive/131921633/Util/Math.v.sv\n             Util/Math.v\n             Util/Math.v.v\n             Util/Math.v.sv\n             obj_dir/Util/Math.v\n             obj_dir/Util/Math.v.v\n             obj_dir/Util/Math.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:2: Cannot find include file: Mips/Control/Signal/Alu/Signal/Func.v\n`include "Mips/Control/Signal/Alu/Signal/Func.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:3: Cannot find include file: Mips/Type/AluStatus.v\n`include "Mips/Type/AluStatus.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:4: Cannot find include file: Mips/Datapath/Alu/alu.v\n`include "Mips/Datapath/Alu/alu.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:5: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:14: Define or directive not defined: \'`Data_Control_Control_T\'\n ( `Data_Control_Control_T     (input)  ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:14: syntax error, unexpected \'(\', expecting \'[\'\n ( `Data_Control_Control_T     (input)  ctrl\n                                ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:17: Define or directive not defined: \'`Mips_Control_Signal_Alu_Signal_Func_T\'\n , `Mips_Control_Signal_Alu_Signal_Func_T (input)  func\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:19: Define or directive not defined: \'`Mips_Type_AluStatus_T\'\n , `Mips_Type_AluStatus_T          (output) status\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:22: Define or directive not defined: \'`Util_Math_log2_expr\'\n`Util_Math_log2_expr\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:26: Define or directive not defined: \'`Mips_Type_AluStatus_T\'\n`Mips_Type_AluStatus_T         (wire) status$;\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:26: syntax error, unexpected \'(\'\n`Mips_Type_AluStatus_T         (wire) status$;\n                                ^~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:42: syntax error, unexpected always\nalways @(*)\n^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:44: Define or directive not defined: \'`Mips_Control_Signal_Alu_Signal_Func_Mulu\'\n  `Mips_Control_Signal_Alu_Signal_Func_Mulu : {store_hi, store_lo} = 2\'b11;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:45: Define or directive not defined: \'`Mips_Control_Signal_Alu_Signal_Func_Muls\'\n  `Mips_Control_Signal_Alu_Signal_Func_Muls : {store_hi, store_lo} = 2\'b11;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:46: Define or directive not defined: \'`Mips_Control_Signal_Alu_Signal_Func_Divu\'\n  `Mips_Control_Signal_Alu_Signal_Func_Divu : {store_hi, store_lo} = 2\'b11;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:47: Define or directive not defined: \'`Mips_Control_Signal_Alu_Signal_Func_Divs\'\n  `Mips_Control_Signal_Alu_Signal_Func_Divs : {store_hi, store_lo} = 2\'b11;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:48: Define or directive not defined: \'`Mips_Control_Signal_Alu_Signal_Func_Mthi\'\n  `Mips_Control_Signal_Alu_Signal_Func_Mthi : {store_hi, store_lo} = 2\'b10;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:49: Define or directive not defined: \'`Mips_Control_Signal_Alu_Signal_Func_Mtlo\'\n  `Mips_Control_Signal_Alu_Signal_Func_Mtlo : {store_hi, store_lo} = 2\'b01;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:53: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways @(posedge `Data_Control_Control_Clock(ctrl))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:54: Define or directive not defined: \'`Data_Control_Control_Reset\'\n if(`Data_Control_Control_Reset(ctrl))\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:59: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways @(posedge `Data_Control_Control_Clock(ctrl))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/hilo.v:60: Define or directive not defined: \'`Data_Control_Control_Reset\'\n if(`Data_Control_Control_Reset(ctrl))\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 23 error(s)\n'
module Mips_Datapath_Alu_hilo #
	( parameter DATA_W  = 32
	, parameter SHAMT_W = Util_Math_log2(DATA_W)
	)
	( `Data_Control_Control_T     (input)  ctrl
	, `Mips_Datapath_Alu_hilo_Type_Data_T  (input)  data1
	, `Mips_Datapath_Alu_hilo_Type_Data_T  (input)  data2
	, `Mips_Control_Signal_Alu_Signal_Func_T (input)  func
	, `Mips_Datapath_Alu_hilo_Type_Data_T  (output) result
	, `Mips_Type_AluStatus_T          (output) status
	);

`Util_Math_log2_expr

`Mips_Datapath_Alu_hilo_Type_Data_T (reg)  reg_hi, reg_lo;
`Mips_Datapath_Alu_hilo_Type_Data_T (wire) res_hi, res_lo;
`Mips_Type_AluStatus_T         (wire) status$;

Mips_Datapath_Alu_alu #
	( .DATA_W  (DATA_W)
	) GALU
	( .data1  (data1)
	, .data2  (data2)
	, .func   (func)
	, .reg_lo (reg_lo)
	, .reg_hi (reg_hi)
	, .res_lo (res_lo)
	, .res_hi (res_hi)
	, .status (status$)
	);

reg store_hi, store_lo;
always @(*)
	case(func)
		`Mips_Control_Signal_Alu_Signal_Func_Mulu : {store_hi, store_lo} = 2'b11;
		`Mips_Control_Signal_Alu_Signal_Func_Muls : {store_hi, store_lo} = 2'b11;
		`Mips_Control_Signal_Alu_Signal_Func_Divu : {store_hi, store_lo} = 2'b11;
		`Mips_Control_Signal_Alu_Signal_Func_Divs : {store_hi, store_lo} = 2'b11;
		`Mips_Control_Signal_Alu_Signal_Func_Mthi : {store_hi, store_lo} = 2'b10;
		`Mips_Control_Signal_Alu_Signal_Func_Mtlo : {store_hi, store_lo} = 2'b01;
		default                                        : {store_hi, store_lo} = 2'b00;
	endcase

always @(posedge `Data_Control_Control_Clock(ctrl))
	if(`Data_Control_Control_Reset(ctrl))
		reg_hi <= DATA_W'(0);
	else if(store_hi)
		reg_hi <= res_hi;

always @(posedge `Data_Control_Control_Clock(ctrl))
	if(`Data_Control_Control_Reset(ctrl))
		reg_lo <= DATA_W'(0);
	else if(store_lo)
		reg_lo <= res_lo;

assign result = res_lo;
assign status = status$;

endmodule
module Mips_Datapath_Alu_hilo #
	( parameter DATA_W  = 32
	, parameter SHAMT_W = Util_Math_log2(DATA_W)
	)
	( `Data_Control_Control_T     (input)  ctrl
	, `Mips_Datapath_Alu_hilo_Type_Data_T  (input)  data1
	, `Mips_Datapath_Alu_hilo_Type_Data_T  (input)  data2
	, `Mips_Control_Signal_Alu_Signal_Func_T (input)  func
	, `Mips_Datapath_Alu_hilo_Type_Data_T  (output) result
	, `Mips_Type_AluStatus_T          (output) status
	);


`Util_Math_log2_expr

`Mips_Datapath_Alu_hilo_Type_Data_T (reg)  reg_hi, reg_lo;
`Mips_Datapath_Alu_hilo_Type_Data_T (wire) res_hi, res_lo;
`Mips_Type_AluStatus_T         (wire) status$;

Mips_Datapath_Alu_alu #
	( .DATA_W  (DATA_W)
	) GALU
	( .data1  (data1)
	, .data2  (data2)
	, .func   (func)
	, .reg_lo (reg_lo)
	, .reg_hi (reg_hi)
	, .res_lo (res_lo)
	, .res_hi (res_hi)
	, .status (status$)
	);

reg store_hi, store_lo;
always @(*)
	case(func)
		`Mips_Control_Signal_Alu_Signal_Func_Mulu : {store_hi, store_lo} = 2'b11;
		`Mips_Control_Signal_Alu_Signal_Func_Muls : {store_hi, store_lo} = 2'b11;
		`Mips_Control_Signal_Alu_Signal_Func_Divu : {store_hi, store_lo} = 2'b11;
		`Mips_Control_Signal_Alu_Signal_Func_Divs : {store_hi, store_lo} = 2'b11;
		`Mips_Control_Signal_Alu_Signal_Func_Mthi : {store_hi, store_lo} = 2'b10;
		`Mips_Control_Signal_Alu_Signal_Func_Mtlo : {store_hi, store_lo} = 2'b01;
		default                                        : {store_hi, store_lo} = 2'b00;
	endcase

always @(posedge `Data_Control_Control_Clock(ctrl))
	if(`Data_Control_Control_Reset(ctrl))
		reg_hi <= DATA_W'(0);
	else if(store_hi)
		reg_hi <= res_hi;

always @(posedge `Data_Control_Control_Clock(ctrl))
	if(`Data_Control_Control_Reset(ctrl))
		reg_lo <= DATA_W'(0);
	else if(store_lo)
		reg_lo <= res_lo;

assign result = res_lo;
assign status = status$;

endmodule