data/full_repos/permissive/173814379/implementation/testbench/testmem_v1r0.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/173814379/implementation/testbench/testmem_v1r0.v:22: Multiple top level modules\n                                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                  : ... Top module \'epRISC_testRAM\'\nmodule epRISC_testRAM(iAddr, iClk, iData, iWrite, oData);\n       ^~~~~~~~~~~~~~\n                                                                                                  : ... Top module \'epRISC_testSDRAM\'\nmodule epRISC_testSDRAM(iAddr, iClk, iData, iWrite, oData);\n       ^~~~~~~~~~~~~~~~\n                                                                                                  : ... Top module \'epRISC_testROM\'\nmodule epRISC_testROM(iClk, iAddr, oData, iEnable);\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module epRISC_testRAM(iAddr, iClk, iData, iWrite, oData);

    input iClk, iWrite;
    input [11:0] iAddr;
    input [31:0] iData;
    output wire [31:0] oData;

    reg [31:0] rDataOut, rContents[0:4095];
    
    assign oData = rDataOut;
    
    always @(posedge iClk) begin
        if(iWrite)
            rContents[iAddr] = iData;
        else
            rDataOut = rContents[iAddr];
    end
    
endmodule
module epRISC_testRAM(iAddr, iClk, iData, iWrite, oData);


    input iClk, iWrite;
    input [11:0] iAddr;
    input [31:0] iData;
    output wire [31:0] oData;

    reg [31:0] rDataOut, rContents[0:4095];
    
    assign oData = rDataOut;
    
    always @(posedge iClk) begin
        if(iWrite)
            rContents[iAddr] = iData;
        else
            rDataOut = rContents[iAddr];
    end
    
endmodule