data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/ALU.v
 line:38: before: "ALUOut"
data/verilator_xmls/da89dae9-e511-4238-893f-50eef543438a.xml
module ALU(A, B, aluc, ALUOut);
    input [31:0] A, B;
    input [3:0] aluc;
    output reg [31:0] ALUOut;
    
    always @(A, B, aluc)
    begin
        case (aluc)
            'd0: ALUOut[31:0] <= A&B;
            'd1: ALUOut[31:0] <= A|B;
            'd2: ALUOut[31:0] <= A+B;
            'd3: ALUOut[31:0] <= A^B;
            'd6: ALUOut[31:0] <= A-B;
            'd7: ALUOut[31:0] <= A<B?1:0;
            'd12: ALUOut[31:0] <= ~(A|B);
            default ALUOut <= 'bX;
        endcase
    end
endmodule
module ALU(A, B, aluc, ALUOut);

    input [31:0] A, B;
    input [3:0] aluc;
    output reg [31:0] ALUOut;
    
    always @(A, B, aluc)
    begin
        case (aluc)
            'd0: ALUOut[31:0] <= A&B;
            'd1: ALUOut[31:0] <= A|B;
            'd2: ALUOut[31:0] <= A+B;
            'd3: ALUOut[31:0] <= A^B;
            'd6: ALUOut[31:0] <= A-B;
            'd7: ALUOut[31:0] <= A<B?1:0;
            'd12: ALUOut[31:0] <= ~(A|B);
            default ALUOut <= 'bX;
        endcase
    end
endmodule