data/full_repos/permissive/171930001/digital_video/video_sync_test.v
 line:12: before: "$"
1: b'%Error: data/full_repos/permissive/171930001/digital_video/video_sync_test.v:8: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("simulation/video_sync_test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/171930001/digital_video/video_sync_test.v:9: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, video_sync_test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/171930001/digital_video/video_sync_test.v:11: Unsupported: Ignoring delay on this delayed statement.\n    # 40 rst = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/171930001/digital_video/video_sync_test.v:12: Unsupported: Ignoring delay on this delayed statement.\n    # 48000000 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/171930001/digital_video/video_sync_test.v:16: Unsupported: Ignoring delay on this delayed statement.\nalways #4 clk = !clk;\n       ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module video_sync_test;

reg rst = 1;

initial begin
    $dumpfile("simulation/video_sync_test.vcd");
    $dumpvars(0, video_sync_test);

    # 40 rst = 0;
    # 48000000 $finish;
end

reg clk = 0;
always #4 clk = !clk;

wire blanking_wire;
wire hsync_wire;
wire vsync_wire;
wire [9:0] x_wire;
wire [9:0] y_wire;

video_sync sync(
    .clk(clk),
    .rst(rst),
    .blanking(blanking_wire),
    .h_sync(hsync_wire),
    .v_sync(vsync_wire),
    .x(x_wire),
    .y(y_wire)
);

endmodule
module video_sync_test;


reg rst = 1;

initial begin
    $dumpfile("simulation/video_sync_test.vcd");
    $dumpvars(0, video_sync_test);

    # 40 rst = 0;
    # 48000000 $finish;
end

reg clk = 0;
always #4 clk = !clk;

wire blanking_wire;
wire hsync_wire;
wire vsync_wire;
wire [9:0] x_wire;
wire [9:0] y_wire;

video_sync sync(
    .clk(clk),
    .rst(rst),
    .blanking(blanking_wire),
    .h_sync(hsync_wire),
    .v_sync(vsync_wire),
    .x(x_wire),
    .y(y_wire)
);

endmodule