data/full_repos/permissive/185301529/BHR.sv
 line:25: before: ":"
1: b'%Warning-WIDTH: data/full_repos/permissive/185301529/BHR.sv:15: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance BHR\n data = 1\'b0;\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module BHR#(parameter size = 4)
(
	input clk,
	input load,
	input outcome,
	
	output logic [size-1:0] out
);

logic [size-1:0] data;

assign out = data;

initial begin
	data = 1'b0;
end

always_ff @(posedge clk) begin
	if(load) begin
		data = data << 1;
		data[0] = outcome;
	end
end

endmodule
module BHR#(parameter size = 4)
(
	input clk,
	input load,
	input outcome,
	
	output logic [size-1:0] out
);


logic [size-1:0] data;

assign out = data;

initial begin
	data = 1'b0;
end

always_ff @(posedge clk) begin
	if(load) begin
		data = data << 1;
		data[0] = outcome;
	end
end

endmodule