data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v
'utf-8' codec can't decode byte 0xbd in position 1847: invalid start byte
1: b'%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:33: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v.v\n             data/full_repos/permissive/220187565/wishbone_cyc10/cpu,data/full_repos/permissive/220187565/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:42: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] mem_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegAddrBus] mem_wd,\n                       ^\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:44: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] mem_wdata,\n ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:44: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_wdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:46: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire mem_LLbit_value,\n ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:47: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`PhyAddrBus]mem_LLbit_addr,\n ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:47: Define or directive not defined: \'`PhyAddrBus\'\n input wire [`PhyAddrBus]mem_LLbit_addr,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:49: Define or directive not defined: \'`CSRWriteTypeBus\'\n input wire[`CSRWriteTypeBus] mem_csr_reg_we,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:50: Define or directive not defined: \'`CSRAddrBus\'\n input wire[`CSRAddrBus] mem_csr_reg_addr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:51: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_csr_reg_data,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:55: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] mem_original_data_i,\n ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:55: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_original_data_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:58: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wb_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:60: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] wb_wdata,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:60: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wb_wdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:63: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg wb_LLbit_value,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:64: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [`PhyAddrBus]wb_LLbit_addr,\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:64: Define or directive not defined: \'`PhyAddrBus\'\n output reg [`PhyAddrBus]wb_LLbit_addr,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:66: Define or directive not defined: \'`CSRWriteTypeBus\'\n output reg[`CSRWriteTypeBus] wb_csr_reg_we,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:67: Define or directive not defined: \'`CSRAddrBus\'\n output reg[`CSRAddrBus] wb_csr_reg_addr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:68: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wb_csr_reg_data,\n            ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:72: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [`RegBus] mem_original_data_o\n ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:72: Define or directive not defined: \'`RegBus\'\n output reg [`RegBus] mem_original_data_o\n             ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:78: Define or directive not defined: \'`RstEnable\'\n  if(rst_n == `RstEnable)\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:80: Define or directive not defined: \'`NOPRegAddr\'\n   wb_wd <= `NOPRegAddr;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:81: Define or directive not defined: \'`WriteDisable\'\n   wb_wreg <= `WriteDisable;\n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:82: Define or directive not defined: \'`ZeroWord\'\n   wb_wdata <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:86: Define or directive not defined: \'`ZeroWord\'\n   wb_LLbit_addr <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:88: Define or directive not defined: \'`CSRWriteDisable\'\n   wb_csr_reg_we <= `CSRWriteDisable;\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:89: Define or directive not defined: \'`NOPRegAddr\'\n   wb_csr_reg_addr <= `NOPRegAddr;\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:90: Define or directive not defined: \'`ZeroWord\'\n   wb_csr_reg_data <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:93: Define or directive not defined: \'`ZeroWord\'\n   mem_original_data_o <= `ZeroWord;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:95: Define or directive not defined: \'`Flush\'\n  else if(flush == `Flush)\n                   ^~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:97: Define or directive not defined: \'`NOPRegAddr\'\n   wb_wd <= `NOPRegAddr;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:98: Define or directive not defined: \'`WriteDisable\'\n   wb_wreg <= `WriteDisable;\n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:99: Define or directive not defined: \'`ZeroWord\'\n   wb_wdata <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:103: Define or directive not defined: \'`ZeroWord\'\n   wb_LLbit_addr <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:105: Define or directive not defined: \'`CSRWriteDisable\'\n   wb_csr_reg_we <= `CSRWriteDisable;\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:106: Define or directive not defined: \'`NOPRegAddr\'\n   wb_csr_reg_addr <= `NOPRegAddr;\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:107: Define or directive not defined: \'`ZeroWord\'\n   wb_csr_reg_data <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:110: Define or directive not defined: \'`ZeroWord\'\n   mem_original_data_o <= `ZeroWord;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:112: Define or directive not defined: \'`Stop\'\n  else if(stall[4] == `Stop && stall[5] == `NoStop)\n                      ^~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:112: Define or directive not defined: \'`NoStop\'\n  else if(stall[4] == `Stop && stall[5] == `NoStop)\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:114: Define or directive not defined: \'`NOPRegAddr\'\n   wb_wd <= `NOPRegAddr;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:115: Define or directive not defined: \'`WriteDisable\'\n   wb_wreg <= `WriteDisable;\n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:116: Define or directive not defined: \'`ZeroWord\'\n   wb_wdata <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:120: Define or directive not defined: \'`ZeroWord\'\n   wb_LLbit_addr <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:122: Define or directive not defined: \'`CSRWriteDisable\'\n   wb_csr_reg_we <= `CSRWriteDisable;\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220187565/wishbone_cyc10/cpu/mem_wb.v:123: Define or directive not defined: \'`NOPRegAddr\'\n   wb_csr_reg_addr <= `NOPRegAddr;\n                      ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module mem_wb(
	input wire clk,
	input wire rst_n,
	input wire[5:0] stall,
	input wire flush,
	

	input wire[`RegAddrBus] mem_wd,
	input wire mem_wreg,
	input wire[`RegBus] mem_wdata,
	input wire mem_LLbit_we,
	input wire mem_LLbit_value,
	input wire [`PhyAddrBus]mem_LLbit_addr,
	
	input wire[`CSRWriteTypeBus] mem_csr_reg_we,
	input wire[`CSRAddrBus] mem_csr_reg_addr,
	input wire[`RegBus] mem_csr_reg_data,


	input wire [1:0] mem_cnt_i,
	input wire[`RegBus] mem_original_data_i,


	output reg[`RegAddrBus] wb_wd,
	output reg wb_wreg,
	output reg[`RegBus] wb_wdata,
	
	output reg wb_LLbit_we,
	output reg wb_LLbit_value,
	output reg [`PhyAddrBus]wb_LLbit_addr,

	output reg[`CSRWriteTypeBus] wb_csr_reg_we,
	output reg[`CSRAddrBus] wb_csr_reg_addr,
	output reg[`RegBus] wb_csr_reg_data,


	output reg [1:0] mem_cnt_o,
	output reg [`RegBus] mem_original_data_o
);


	always @ (posedge clk or negedge rst_n)
	begin
		if(rst_n == `RstEnable)
		begin
			wb_wd <= `NOPRegAddr;
			wb_wreg <= `WriteDisable;
			wb_wdata <= `ZeroWord;
			
			wb_LLbit_we <= 1'b0;
			wb_LLbit_value <= 1'b0;
			wb_LLbit_addr <= `ZeroWord;
			
			wb_csr_reg_we <= `CSRWriteDisable;
			wb_csr_reg_addr <= `NOPRegAddr;
			wb_csr_reg_data <= `ZeroWord;

			mem_cnt_o <= 2'h0;
			mem_original_data_o <= `ZeroWord;
		end
		else if(flush == `Flush)
		begin
			wb_wd <= `NOPRegAddr;
			wb_wreg <= `WriteDisable;
			wb_wdata <= `ZeroWord;
			
			wb_LLbit_we <= 1'b0;
			wb_LLbit_value <= 1'b0;
			wb_LLbit_addr <= `ZeroWord;

			wb_csr_reg_we <= `CSRWriteDisable;
			wb_csr_reg_addr <= `NOPRegAddr;
			wb_csr_reg_data <= `ZeroWord;

			mem_cnt_o <= 2'h0;
			mem_original_data_o <= `ZeroWord;
		end
		else if(stall[4] == `Stop && stall[5] == `NoStop)
		begin
			wb_wd <= `NOPRegAddr;
			wb_wreg <= `WriteDisable;
			wb_wdata <= `ZeroWord;

			wb_LLbit_we <= 1'b0;
			wb_LLbit_value <= 1'b0;
			wb_LLbit_addr <= `ZeroWord;

			wb_csr_reg_we <= `CSRWriteDisable;
			wb_csr_reg_addr <= `NOPRegAddr;
			wb_csr_reg_data <= `ZeroWord;

			mem_cnt_o <= mem_cnt_i;
			mem_original_data_o <= mem_original_data_i;
		end
		else if(stall[4] == `NoStop)
		begin
			wb_wd <= mem_wd;
			wb_wreg <= mem_wreg;
			wb_wdata <= mem_wdata;

			wb_LLbit_we <= mem_LLbit_we;
			wb_LLbit_value <= mem_LLbit_value;
			wb_LLbit_addr <= mem_LLbit_addr;

			wb_csr_reg_we <= mem_csr_reg_we;
			wb_csr_reg_addr <= mem_csr_reg_addr;
			wb_csr_reg_data <= mem_csr_reg_data;

			mem_cnt_o <= 2'h0;
			mem_original_data_o <= `ZeroWord;
		end
		else
		begin
			mem_cnt_o <= mem_cnt_i;
			mem_original_data_o <= mem_original_data_i;
		end
	end
endmodule
module mem_wb(
	input wire clk,
	input wire rst_n,
	input wire[5:0] stall,
	input wire flush,
	

	input wire[`RegAddrBus] mem_wd,
	input wire mem_wreg,
	input wire[`RegBus] mem_wdata,
	input wire mem_LLbit_we,
	input wire mem_LLbit_value,
	input wire [`PhyAddrBus]mem_LLbit_addr,
	
	input wire[`CSRWriteTypeBus] mem_csr_reg_we,
	input wire[`CSRAddrBus] mem_csr_reg_addr,
	input wire[`RegBus] mem_csr_reg_data,


	input wire [1:0] mem_cnt_i,
	input wire[`RegBus] mem_original_data_i,


	output reg[`RegAddrBus] wb_wd,
	output reg wb_wreg,
	output reg[`RegBus] wb_wdata,
	
	output reg wb_LLbit_we,
	output reg wb_LLbit_value,
	output reg [`PhyAddrBus]wb_LLbit_addr,

	output reg[`CSRWriteTypeBus] wb_csr_reg_we,
	output reg[`CSRAddrBus] wb_csr_reg_addr,
	output reg[`RegBus] wb_csr_reg_data,


	output reg [1:0] mem_cnt_o,
	output reg [`RegBus] mem_original_data_o
);



	always @ (posedge clk or negedge rst_n)
	begin
		if(rst_n == `RstEnable)
		begin
			wb_wd <= `NOPRegAddr;
			wb_wreg <= `WriteDisable;
			wb_wdata <= `ZeroWord;
			
			wb_LLbit_we <= 1'b0;
			wb_LLbit_value <= 1'b0;
			wb_LLbit_addr <= `ZeroWord;
			
			wb_csr_reg_we <= `CSRWriteDisable;
			wb_csr_reg_addr <= `NOPRegAddr;
			wb_csr_reg_data <= `ZeroWord;

			mem_cnt_o <= 2'h0;
			mem_original_data_o <= `ZeroWord;
		end
		else if(flush == `Flush)
		begin
			wb_wd <= `NOPRegAddr;
			wb_wreg <= `WriteDisable;
			wb_wdata <= `ZeroWord;
			
			wb_LLbit_we <= 1'b0;
			wb_LLbit_value <= 1'b0;
			wb_LLbit_addr <= `ZeroWord;

			wb_csr_reg_we <= `CSRWriteDisable;
			wb_csr_reg_addr <= `NOPRegAddr;
			wb_csr_reg_data <= `ZeroWord;

			mem_cnt_o <= 2'h0;
			mem_original_data_o <= `ZeroWord;
		end
		else if(stall[4] == `Stop && stall[5] == `NoStop)
		begin
			wb_wd <= `NOPRegAddr;
			wb_wreg <= `WriteDisable;
			wb_wdata <= `ZeroWord;

			wb_LLbit_we <= 1'b0;
			wb_LLbit_value <= 1'b0;
			wb_LLbit_addr <= `ZeroWord;

			wb_csr_reg_we <= `CSRWriteDisable;
			wb_csr_reg_addr <= `NOPRegAddr;
			wb_csr_reg_data <= `ZeroWord;

			mem_cnt_o <= mem_cnt_i;
			mem_original_data_o <= mem_original_data_i;
		end
		else if(stall[4] == `NoStop)
		begin
			wb_wd <= mem_wd;
			wb_wreg <= mem_wreg;
			wb_wdata <= mem_wdata;

			wb_LLbit_we <= mem_LLbit_we;
			wb_LLbit_value <= mem_LLbit_value;
			wb_LLbit_addr <= mem_LLbit_addr;

			wb_csr_reg_we <= mem_csr_reg_we;
			wb_csr_reg_addr <= mem_csr_reg_addr;
			wb_csr_reg_data <= mem_csr_reg_data;

			mem_cnt_o <= 2'h0;
			mem_original_data_o <= `ZeroWord;
		end
		else
		begin
			mem_cnt_o <= mem_cnt_i;
			mem_original_data_o <= mem_original_data_i;
		end
	end
endmodule