data/full_repos/permissive/136794488/source/pipeir.v
data/verilator_xmls/f944fecb-b1bc-4c8d-9fa6-b84109b3fc38.xml
module pipeir  ( pc4,ins,clock,resetn,dpc4,inst ); 

	input  [31:0] pc4,ins;
   input         clock,resetn;   
   
   output [31:0] dpc4,inst;
   
   wire   [31:0] ins ;
   wire          clock,resetn;
   reg    [31:0] inst,dpc4 ;
   
   always @ (negedge resetn or posedge clock)
      if ( resetn == 0) begin
         inst[31:0] <= 32'b0;
			dpc4[31:0] <= 32'b0;
      end else begin
         inst[31:0] <= ins[31:0];
			dpc4[31:0] <= pc4[31:0];
      end
		
endmodule
module pipeir  ( pc4,ins,clock,resetn,dpc4,inst );
 

	input  [31:0] pc4,ins;
   input         clock,resetn;   
   
   output [31:0] dpc4,inst;
   
   wire   [31:0] ins ;
   wire          clock,resetn;
   reg    [31:0] inst,dpc4 ;
   
   always @ (negedge resetn or posedge clock)
      if ( resetn == 0) begin
         inst[31:0] <= 32'b0;
			dpc4[31:0] <= 32'b0;
      end else begin
         inst[31:0] <= ins[31:0];
			dpc4[31:0] <= pc4[31:0];
      end
		
endmodule