data/full_repos/permissive/14193640/fpga/controller_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/controller_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/controller_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/controller_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #40;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/controller_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #1000;\n      ^\n%Error: data/full_repos/permissive/14193640/fpga/controller_testbench.v:13: Cannot find file containing module: \'controller\'\n   controller uut\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/14193640/fpga,data/full_repos/permissive/14193640/controller\n             data/full_repos/permissive/14193640/fpga,data/full_repos/permissive/14193640/controller.v\n             data/full_repos/permissive/14193640/fpga,data/full_repos/permissive/14193640/controller.sv\n             controller\n             controller.v\n             controller.sv\n             obj_dir/controller\n             obj_dir/controller.v\n             obj_dir/controller.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module controller_testbench;

   reg clk, reset_n;
   wire serial_clk, output_enable_n, latch_enable;
   wire [3:0] serial_data_out_red;
   wire [3:0] serial_data_out_green;
   wire [3:0] serial_data_out_blue;
   wire [15:0] row_select_n;
   

   controller uut
     (.clk(clk), .reset_n(reset_n), .serial_clk(serial_clk),
      .latch_enable(latch_enable), .output_enable_n(output_enable_n),
      .serial_data_out_red(serial_data_out_red), 
      .serial_data_out_green(serial_data_out_green),
      .serial_data_out_blue(serial_data_out_blue),
      .row_select_n(row_select_n));
   

   always begin
      clk = 1'b1;
      #10;
      clk = 1'b0;
      #10;
   end

   initial begin
      clk = 0;
      reset_n = 0;
      #40;
      reset_n = 1;
      #1000;
      $stop;
   end
   
endmodule
module controller_testbench;


   reg clk, reset_n;
   wire serial_clk, output_enable_n, latch_enable;
   wire [3:0] serial_data_out_red;
   wire [3:0] serial_data_out_green;
   wire [3:0] serial_data_out_blue;
   wire [15:0] row_select_n;
   

   controller uut
     (.clk(clk), .reset_n(reset_n), .serial_clk(serial_clk),
      .latch_enable(latch_enable), .output_enable_n(output_enable_n),
      .serial_data_out_red(serial_data_out_red), 
      .serial_data_out_green(serial_data_out_green),
      .serial_data_out_blue(serial_data_out_blue),
      .row_select_n(row_select_n));
   

   always begin
      clk = 1'b1;
      #10;
      clk = 1'b0;
      #10;
   end

   initial begin
      clk = 0;
      reset_n = 0;
      #40;
      reset_n = 1;
      #1000;
      $stop;
   end
   
endmodule