data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v
 line:113: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:90: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_HALF_PERIOD tb_clk = !tb_clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:152: Unsupported: Ignoring delay on this delayed statement.\n      #(4 * CLK_HALF_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:185: Unsupported: Ignoring delay on this delayed statement.\n      #(4 * CLK_HALF_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:190: Unsupported: Ignoring delay on this delayed statement.\n      #(150 * CLK_HALF_PERIOD);\n      ^\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:111: Can\'t find definition of \'w_ctr_reg\' in dotted variable: \'dut.w_ctr_reg\'\n          $display("dut w_ctr      = %02x:", dut.w_ctr_reg);\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:112: Can\'t find definition of \'w_tmp\' in dotted variable: \'dut.w_tmp\'\n          $display("dut w_tmp      = %02x:", dut.w_tmp);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:128: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);\n                   ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:128: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);\n                                  ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:128: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:128: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);\n                                                                ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:131: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);\n                   ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:131: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);\n                                  ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:131: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:131: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);\n                                                                ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:134: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);\n                   ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:134: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);\n                                  ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:134: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:134: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);\n                                                                ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:137: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);\n                   ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:137: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);\n                                  ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:137: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:137: Can\'t find definition of \'w_mem\' in dotted variable: \'dut.w_mem\'\n               dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);\n                                                                ^~~~~\n%Error: data/full_repos/permissive/15361741/src/tb/tb_sha256_w_mem.v:139: Can\'t find definition of \'w_new\' in dotted variable: \'dut.w_new\'\n      $display("w_new = %08x", dut.w_new);\n                                   ^~~~~\n%Error: Exiting due to 19 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sha256_w_mem();




  parameter DEBUG          = 1;
  parameter DISPLAY_CYCLES = 0;

  parameter CLK_HALF_PERIOD = 2;





  reg            tb_clk;
  reg            tb_reset_n;

  reg           tb_init;
  reg           tb_next;
  reg [511 : 0] tb_block;
  wire [31 : 0] tb_w;

  reg [63 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;





  sha256_w_mem dut(
                   .clk(tb_clk),
                   .reset_n(tb_reset_n),

                   .block(tb_block),

                   .init(tb_init),
                   .next(tb_next),

                   .w(tb_w)
                  );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD tb_clk = !tb_clk;
    end








  always @ (posedge tb_clk)
    begin : dut_monitor
      cycle_ctr = cycle_ctr + 1;

      if (DISPLAY_CYCLES)
        begin
          $display("cycle = %016x:", cycle_ctr);
        end

      if (DEBUG)
        begin
          $display("dut w_ctr      = %02x:", dut.w_ctr_reg);
          $display("dut w_tmp      = %02x:", dut.w_tmp);
          dump_w_state();
        end
    end







  task dump_w_state;
    begin
      $display("W state:");

      $display("w0_reg  = %08x, w1_reg  = %08x, w2_reg  = %08x, w3_reg  = %08x",
               dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);

      $display("w4_reg  = %08x, w5_reg  = %08x, w6_reg  = %08x, w7_reg  = %08x",
               dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);

      $display("w8_reg  = %08x, w9_reg  = %08x, w10_reg = %08x, w11_reg = %08x",
               dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);

      $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x",
               dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);

      $display("w_new = %08x", dut.w_new);
      $display("");
    end
  endtask





  task reset_dut;
    begin
      $display("*** Toggle reset.");
      tb_reset_n = 0;
      #(4 * CLK_HALF_PERIOD);
      tb_reset_n = 1;
    end
  endtask





  task init_sim;
    begin
      $display("*** Simulation init.");
      tb_clk = 0;
      tb_reset_n = 1;
      cycle_ctr = 0;

      tb_init = 0;
      tb_block = 512'h0;
    end
  endtask








  task test_w_schedule;
    begin
      $display("*** Test of W schedule processing. --");
      tb_block = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
      tb_init = 1;
      #(4 * CLK_HALF_PERIOD);
      tb_init = 0;
      dump_w_state();

      tb_next = 1;
      #(150 * CLK_HALF_PERIOD);
    end
  endtask





  initial
    begin : w_mem_test
      $display("   -- Testbench for sha256 w memory started --");
      init_sim();
      reset_dut();
      test_w_schedule();

      $display("*** Simulation done.");
      $finish;
    end

endmodule
module tb_sha256_w_mem();





  parameter DEBUG          = 1;
  parameter DISPLAY_CYCLES = 0;

  parameter CLK_HALF_PERIOD = 2;





  reg            tb_clk;
  reg            tb_reset_n;

  reg           tb_init;
  reg           tb_next;
  reg [511 : 0] tb_block;
  wire [31 : 0] tb_w;

  reg [63 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;





  sha256_w_mem dut(
                   .clk(tb_clk),
                   .reset_n(tb_reset_n),

                   .block(tb_block),

                   .init(tb_init),
                   .next(tb_next),

                   .w(tb_w)
                  );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD tb_clk = !tb_clk;
    end








  always @ (posedge tb_clk)
    begin : dut_monitor
      cycle_ctr = cycle_ctr + 1;

      if (DISPLAY_CYCLES)
        begin
          $display("cycle = %016x:", cycle_ctr);
        end

      if (DEBUG)
        begin
          $display("dut w_ctr      = %02x:", dut.w_ctr_reg);
          $display("dut w_tmp      = %02x:", dut.w_tmp);
          dump_w_state();
        end
    end







  task dump_w_state;
    begin
      $display("W state:");

      $display("w0_reg  = %08x, w1_reg  = %08x, w2_reg  = %08x, w3_reg  = %08x",
               dut.w_mem[00], dut.w_mem[01], dut.w_mem[02], dut.w_mem[03]);

      $display("w4_reg  = %08x, w5_reg  = %08x, w6_reg  = %08x, w7_reg  = %08x",
               dut.w_mem[04], dut.w_mem[05], dut.w_mem[06], dut.w_mem[07]);

      $display("w8_reg  = %08x, w9_reg  = %08x, w10_reg = %08x, w11_reg = %08x",
               dut.w_mem[08], dut.w_mem[09], dut.w_mem[10], dut.w_mem[11]);

      $display("w12_reg = %08x, w13_reg = %08x, w14_reg = %08x, w15_reg = %08x",
               dut.w_mem[12], dut.w_mem[13], dut.w_mem[14], dut.w_mem[15]);

      $display("w_new = %08x", dut.w_new);
      $display("");
    end
  endtask





  task reset_dut;
    begin
      $display("*** Toggle reset.");
      tb_reset_n = 0;
      #(4 * CLK_HALF_PERIOD);
      tb_reset_n = 1;
    end
  endtask





  task init_sim;
    begin
      $display("*** Simulation init.");
      tb_clk = 0;
      tb_reset_n = 1;
      cycle_ctr = 0;

      tb_init = 0;
      tb_block = 512'h0;
    end
  endtask








  task test_w_schedule;
    begin
      $display("*** Test of W schedule processing. --");
      tb_block = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
      tb_init = 1;
      #(4 * CLK_HALF_PERIOD);
      tb_init = 0;
      dump_w_state();

      tb_next = 1;
      #(150 * CLK_HALF_PERIOD);
    end
  endtask





  initial
    begin : w_mem_test
      $display("   -- Testbench for sha256 w memory started --");
      init_sim();
      reset_dut();
      test_w_schedule();

      $display("*** Simulation done.");
      $finish;
    end

endmodule