data/full_repos/permissive/109846502/LCD_dp_tb.v
 line:133: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #2 init_sel = 2\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #2 init_sel = 2\'d1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #2 init_sel = 2\'d2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #2 init_sel = 2\'d3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #5 data_sel = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #5 DB_sel = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #5 state = 2\'d1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #5 index = 2\'d1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #5 index = 2\'d2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #5 index = 2\'d3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #5 statelocal = 3\'d4;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #5 index = 2\'d1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #20 state = 2\'d2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #20 state = 2\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #5 statelocal = 3\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #5 index = 2\'d1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #5 index = 2\'d2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #5 index = 2\'d3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/LCD_dp_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #300 $finish;\n  ^\n%Error: data/full_repos/permissive/109846502/LCD_dp_tb.v:47: Cannot find file containing module: \'LCD_dp\'\n LCD_dp uut (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/LCD_dp\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/LCD_dp.v\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/LCD_dp.sv\n             LCD_dp\n             LCD_dp.v\n             LCD_dp.sv\n             obj_dir/LCD_dp\n             obj_dir/LCD_dp.v\n             obj_dir/LCD_dp.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module LCD_dp_tb;


	reg [1:0] init_sel;
	reg data_sel;
	reg DB_sel;
	reg [1:0] state;
	reg [2:0] statelocal;
	reg [1:0] index;
	reg [3:0] A1;
	reg [3:0] A2;
	reg [3:0] A3;
	reg [3:0] A4;
	reg [3:0] B1;
	reg [3:0] B2;
	reg [3:0] B3;
	reg [3:0] B4;


	wire [7:0] DB_out;


	LCD_dp uut (
		.init_sel(init_sel), 
		.data_sel(data_sel), 
		.DB_sel(DB_sel), 
		.state(state), 
		.statelocal(statelocal), 
		.index(index), 
		.A1(A1), 
		.A2(A2), 
		.A3(A3), 
		.A4(A4), 
		.B1(B1), 
		.B2(B2), 
		.B3(B3), 
		.B4(B4), 
		.DB_out(DB_out)
	);

	initial begin

		init_sel = 0;
		data_sel = 0;
		DB_sel = 0;
		state = 0;
		statelocal = 0;
		index = 0;
		A1 = 0;
		A2 = 0;
		A3 = 0;
		A4 = 0;
		B1 = 0;
		B2 = 0;
		B3 = 0;
		B4 = 0;


		#100;
        

		#2 init_sel = 2'd0;
		#2 init_sel = 2'd1;
		#2 init_sel = 2'd2;
		#2 init_sel = 2'd3;
		
		#5 data_sel = 1'b1;
		#5 DB_sel = 1'b1;
		

		#5 state = 2'd1;
		statelocal = 3'd0;
		index = 2'd0;
		#5 index = 2'd1;
		#5 index = 2'd2;
		#5 index = 2'd3;
		
		#5 statelocal = 3'd4;
		index = 2'd0;
		#5 index = 2'd1;
		
		
		

		#20 state = 2'd2;
		

		#20 state = 2'd0;
		A1 = 4'd9;
		A2 = 4'd3;
		A3 = 4'd7;
		A4 = 4'd1;
		B1 = 4'd2;
		B2 = 4'd4;
		B3 = 4'd6;
		B4 = 4'd8;
		
		#5 statelocal = 3'd0;
		index = 2'd0;
		
		#5 index = 2'd1;
		#5 index = 2'd2;
		#5 index = 2'd3;
		

	end
	
	initial begin
		#300 $finish;
	end
      
endmodule
module LCD_dp_tb;



	reg [1:0] init_sel;
	reg data_sel;
	reg DB_sel;
	reg [1:0] state;
	reg [2:0] statelocal;
	reg [1:0] index;
	reg [3:0] A1;
	reg [3:0] A2;
	reg [3:0] A3;
	reg [3:0] A4;
	reg [3:0] B1;
	reg [3:0] B2;
	reg [3:0] B3;
	reg [3:0] B4;


	wire [7:0] DB_out;


	LCD_dp uut (
		.init_sel(init_sel), 
		.data_sel(data_sel), 
		.DB_sel(DB_sel), 
		.state(state), 
		.statelocal(statelocal), 
		.index(index), 
		.A1(A1), 
		.A2(A2), 
		.A3(A3), 
		.A4(A4), 
		.B1(B1), 
		.B2(B2), 
		.B3(B3), 
		.B4(B4), 
		.DB_out(DB_out)
	);

	initial begin

		init_sel = 0;
		data_sel = 0;
		DB_sel = 0;
		state = 0;
		statelocal = 0;
		index = 0;
		A1 = 0;
		A2 = 0;
		A3 = 0;
		A4 = 0;
		B1 = 0;
		B2 = 0;
		B3 = 0;
		B4 = 0;


		#100;
        

		#2 init_sel = 2'd0;
		#2 init_sel = 2'd1;
		#2 init_sel = 2'd2;
		#2 init_sel = 2'd3;
		
		#5 data_sel = 1'b1;
		#5 DB_sel = 1'b1;
		

		#5 state = 2'd1;
		statelocal = 3'd0;
		index = 2'd0;
		#5 index = 2'd1;
		#5 index = 2'd2;
		#5 index = 2'd3;
		
		#5 statelocal = 3'd4;
		index = 2'd0;
		#5 index = 2'd1;
		
		
		

		#20 state = 2'd2;
		

		#20 state = 2'd0;
		A1 = 4'd9;
		A2 = 4'd3;
		A3 = 4'd7;
		A4 = 4'd1;
		B1 = 4'd2;
		B2 = 4'd4;
		B3 = 4'd6;
		B4 = 4'd8;
		
		#5 statelocal = 3'd0;
		index = 2'd0;
		
		#5 index = 2'd1;
		#5 index = 2'd2;
		#5 index = 2'd3;
		

	end
	
	initial begin
		#300 $finish;
	end
      
endmodule