data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_sequence.v
'utf-8' codec can't decode byte 0xb6 in position 478: invalid start byte
1: b'%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_sequence.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #12 clock = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_sequence.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #5 clock = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_sequence.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #3 clock = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_sequence.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10 clock = 1\'b1;\n    ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module task_sequence;

reg clock;

initial
    init_sequence;

always
    asymmetric_sequence;


task init_sequence;
begin
    clock = 1'b0;
end
endtask



task asymmetric_sequence;
begin
    #12 clock = 1'b0;
    #5 clock = 1'b1;
    #3 clock = 1'b0;
    #10 clock = 1'b1;
end
endtask

endmodule
module task_sequence;


reg clock;

initial
    init_sequence;

always
    asymmetric_sequence;


task init_sequence;
begin
    clock = 1'b0;
end
endtask



task asymmetric_sequence;
begin
    #12 clock = 1'b0;
    #5 clock = 1'b1;
    #3 clock = 1'b0;
    #10 clock = 1'b1;
end
endtask

endmodule