data/full_repos/permissive/18921956/HardwareLab/Lab8/Timer.v
data/verilator_xmls/a8fa8485-f26c-476f-b3cb-958a1a6ef248.xml
module Timer(BCD3, BCD2, timesup, reset, clk);

	output[3:0] BCD3, BCD2;
	output timesup;
	input clk, reset;

	reg[3:0] BCD3, BCD2;
	wire[3:0] next_BCD3, next_BCD2;
	wire timesup;
	always@(posedge clk or negedge reset)begin
		if (!reset) begin
			BCD2 <= 4'b0000;
			BCD3 <= 4'b0011;
		end else begin
			BCD2 <= next_BCD2;
			BCD3 <= next_BCD3;
		end
	end
	

	assign next_BCD2 = (BCD2==4'd0)? ((BCD3==4'd0)? BCD2:4'd9) : (BCD2-4'd1);
	assign next_BCD3 = (BCD2==4'd0)? ((BCD3==4'd0)? BCD3:BCD3-4'd1) : BCD3;
	assign timesup = (BCD2==0)? ((BCD3==0)? 1'd1:1'd0) : 1'd0;
endmodule
module Timer(BCD3, BCD2, timesup, reset, clk);


	output[3:0] BCD3, BCD2;
	output timesup;
	input clk, reset;

	reg[3:0] BCD3, BCD2;
	wire[3:0] next_BCD3, next_BCD2;
	wire timesup;
	always@(posedge clk or negedge reset)begin
		if (!reset) begin
			BCD2 <= 4'b0000;
			BCD3 <= 4'b0011;
		end else begin
			BCD2 <= next_BCD2;
			BCD3 <= next_BCD3;
		end
	end
	

	assign next_BCD2 = (BCD2==4'd0)? ((BCD3==4'd0)? BCD2:4'd9) : (BCD2-4'd1);
	assign next_BCD3 = (BCD2==4'd0)? ((BCD3==4'd0)? BCD3:BCD3-4'd1) : BCD3;
	assign timesup = (BCD2==0)? ((BCD3==0)? 1'd1:1'd0) : 1'd0;
endmodule