data/full_repos/permissive/129155059/proyecto-01/s2p_reg_cond.v
 line:23: before: "~"
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/s2p_reg_cond.v:1: Cannot find include file: definitions.v\n`include "definitions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01,data/full_repos/permissive/129155059/definitions.v\n             data/full_repos/permissive/129155059/proyecto-01,data/full_repos/permissive/129155059/definitions.v.v\n             data/full_repos/permissive/129155059/proyecto-01,data/full_repos/permissive/129155059/definitions.v.sv\n             definitions.v\n             definitions.v.v\n             definitions.v.sv\n             obj_dir/definitions.v\n             obj_dir/definitions.v.v\n             obj_dir/definitions.v.sv\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p_reg_cond.v:13: syntax error, unexpected \'~\', expecting TYPE-IDENTIFIER\n  always @ (~RESET) begin\n            ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p_reg_cond.v:28: syntax error, unexpected <=, expecting IDENTIFIER\n        Q <= Q;\n          ^~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p_reg_cond.v:32: syntax error, unexpected <=, expecting IDENTIFIER\n        Q <= DATA[7:0];\n          ^~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p_reg_cond.v:37: Define or directive not defined: \'`PUSH\'\n          `PUSH:\n          ^~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p_reg_cond.v:37: syntax error, unexpected \':\', expecting endcase\n          `PUSH:\n               ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p_reg_cond.v:51: Define or directive not defined: \'`CYCLE\'\n          `CYCLE:\n          ^~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p_reg_cond.v:64: Define or directive not defined: \'`LOAD\'\n          `LOAD:\n          ^~~~~\n%Error: Cannot continue\n'
module s2p_reg_cond ( input   wire  [7:0] D,
                      input   wire  [1:0] MODO,
                      input   wire        CLK, ENB, DIR, S_IN, RESET,
                      output  reg   [7:0] Q,
                      output  reg         S_OUT
  );

  reg [2:0] CTR;
  reg [8:0] DATA;

  always @ (~RESET) begin
    Q <= 8'b00000000;
    S_OUT <= 1'b0;
    CTR <= 3'b111;


  end

  always @ (posedge CLK) begin

    if (RESET) begin

      CTR <= CTR + 1;

      if (~ENB) begin
        Q <= Q;
      end else begin

      if (CTR == 3'b001) begin
        Q <= DATA[7:0];
        S_OUT <= DATA[8];
      end

        case (MODO)
          `PUSH:
          begin

              if (DIR == 0) begin
                DATA[8] <= DATA[7];
                DATA[7:0] <= {DATA[6 : 0], S_IN};
              end else begin
                DATA[8] <= DATA[0];
                DATA[7:0] <= {S_IN, DATA[7 : 1]};
              end


          end

          `CYCLE:
          begin

              if (DIR == 0) begin
                DATA[7 : 0] <= {DATA[6 : 0], DATA[7]};
                DATA[8] <= 0;
              end else begin
                DATA[7 : 0] <= {DATA[0], DATA[7 : 1]};
                DATA[8] <= 0;
              end

          end

          `LOAD:
          begin
            DATA[7 : 0] <= D[7 : 0];
            DATA[8] <= 0;
          end

          default:
          begin
            DATA[7 : 0] <= D[7 : 0];
            DATA[8] <= 0;
          end

        endcase

      end
    end else begin
      Q <= 8'b0;
      S_OUT <= 1'b0;
      CTR <= 3'b111;


    end
  end

endmodule
module s2p_reg_cond ( input   wire  [7:0] D,
                      input   wire  [1:0] MODO,
                      input   wire        CLK, ENB, DIR, S_IN, RESET,
                      output  reg   [7:0] Q,
                      output  reg         S_OUT
  );


  reg [2:0] CTR;
  reg [8:0] DATA;

  always @ (~RESET) begin
    Q <= 8'b00000000;
    S_OUT <= 1'b0;
    CTR <= 3'b111;


  end

  always @ (posedge CLK) begin

    if (RESET) begin

      CTR <= CTR + 1;

      if (~ENB) begin
        Q <= Q;
      end else begin

      if (CTR == 3'b001) begin
        Q <= DATA[7:0];
        S_OUT <= DATA[8];
      end

        case (MODO)
          `PUSH:
          begin

              if (DIR == 0) begin
                DATA[8] <= DATA[7];
                DATA[7:0] <= {DATA[6 : 0], S_IN};
              end else begin
                DATA[8] <= DATA[0];
                DATA[7:0] <= {S_IN, DATA[7 : 1]};
              end


          end

          `CYCLE:
          begin

              if (DIR == 0) begin
                DATA[7 : 0] <= {DATA[6 : 0], DATA[7]};
                DATA[8] <= 0;
              end else begin
                DATA[7 : 0] <= {DATA[0], DATA[7 : 1]};
                DATA[8] <= 0;
              end

          end

          `LOAD:
          begin
            DATA[7 : 0] <= D[7 : 0];
            DATA[8] <= 0;
          end

          default:
          begin
            DATA[7 : 0] <= D[7 : 0];
            DATA[8] <= 0;
          end

        endcase

      end
    end else begin
      Q <= 8'b0;
      S_OUT <= 1'b0;
      CTR <= 3'b111;


    end
  end

endmodule