data/full_repos/permissive/205926239/ISE_project/Sources/inversion.v
data/verilator_xmls/c308c8db-c5ff-4f77-a499-288b5139142b.xml
module inversion(clk, a, b, a_inv, b_inv);
    
	 input clk;
	 input a;
    input b;
    output a_inv;
    output b_inv;
    
	reg a_inv, b_inv;
	
	always @(posedge clk)
		begin
			a_inv = !a;
			b_inv = !b;
		end
	

endmodule
module inversion(clk, a, b, a_inv, b_inv);

    
	 input clk;
	 input a;
    input b;
    output a_inv;
    output b_inv;
    
	reg a_inv, b_inv;
	
	always @(posedge clk)
		begin
			a_inv = !a;
			b_inv = !b;
		end
	

endmodule