data/full_repos/permissive/210250459/src/mem.v
data/verilator_xmls/6d69fa40-6ecb-4f70-a6bf-a7afc2165f97.xml
module Memory(out, in, addr, mem_read_sig, mem_wrt_sig, clk);

output reg [31:0] out;
input [31:0] in;
input [31:0] addr;
input mem_read_sig, mem_wrt_sig;
input clk;

reg [7:0] mem[1023:0];

always @(mem_read_sig) out = {mem[addr + 3], mem[addr + 2], mem[addr + 1], mem[addr]};

always @(posedge clk) begin
    if (mem_wrt_sig) {mem[addr + 3], mem[addr + 2], mem[addr + 1], mem[addr]} = in;
    $display($time, " [4 Memory] addr = %d out = %d in = %d", addr, out, in);
end

endmodule
module Memory(out, in, addr, mem_read_sig, mem_wrt_sig, clk);


output reg [31:0] out;
input [31:0] in;
input [31:0] addr;
input mem_read_sig, mem_wrt_sig;
input clk;

reg [7:0] mem[1023:0];

always @(mem_read_sig) out = {mem[addr + 3], mem[addr + 2], mem[addr + 1], mem[addr]};

always @(posedge clk) begin
    if (mem_wrt_sig) {mem[addr + 3], mem[addr + 2], mem[addr + 1], mem[addr]} = in;
    $display($time, " [4 Memory] addr = %d out = %d in = %d", addr, out, in);
end

endmodule