data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:26: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("chdr_chunker_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:27: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,chdr_chunker_tb);\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:67: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:72: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:75: syntax error, unexpected \'@\'\n               @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:79: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:90: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:92: syntax error, unexpected \'@\'\n         @(posedge clk);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n      #100 reset = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n      #200000;\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:115: syntax error, unexpected \'@\'\n      while(reset) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:119: syntax error, unexpected \'@\'\n      while(o_tvalid) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:126: syntax error, unexpected \'@\'\n      while(o_tvalid) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:133: syntax error, unexpected \'@\'\n      while(o_tvalid) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:138: syntax error, unexpected \'@\'\n      while(o_tvalid) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:143: syntax error, unexpected \'@\'\n      while(o_tvalid) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:152: syntax error, unexpected \'@\'\n      while(o_tvalid) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:159: syntax error, unexpected \'@\'\n      while(o_tvalid) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:164: syntax error, unexpected \'@\'\n      while(o_tvalid) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:166: syntax error, unexpected \'@\'\n      while(o_tvalid) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/packet_proc/chdr_chunker/chdr_chunker_tb.v:168: syntax error, unexpected \'@\'\n      while(o_tvalid) @(posedge clk);\n                      ^\n%Error: Exiting due to 19 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function check_result;
      input [31:0]   o_xfer_count_arg;
      input [31:0]   i_xfer_count_arg;
      input [63:0]   o_last_tdata_arg;
      input          error_arg;
      begin

         check_result = 1;
         check_result = check_result & ((o_xfer_count_arg == o_xfer_count) !== 0);
         check_result = check_result & ((i_xfer_count_arg == i_xfer_count) !== 0);
         check_result = check_result & ((o_last_tdata_arg == o_last_tdata) !== 0);
         check_result = check_result & ((error_arg == error) != 0);
         
         if (check_result) begin
            $display ("... Passed");
         end else begin
            $display ("... FAILED!!!");
            $display ("o_xfer_count = %d (Expected %d)",o_xfer_count,o_xfer_count_arg);
            $display ("i_xfer_count = %d (Expected %d)",i_xfer_count,i_xfer_count_arg);
            $display ("o_last_tdata = %h (Expected %h)",o_last_tdata,o_last_tdata_arg);
            $display ("error = %d  (Expected %d)",error,error_arg);
         end


         o_xfer_count = 0;
         i_xfer_count = 0;
         o_last_tdata = 64'h0;
      end
   endfunction
function check_result;

      input [31:0]   o_xfer_count_arg;
      input [31:0]   i_xfer_count_arg;
      input [63:0]   o_last_tdata_arg;
      input          error_arg;
      begin

         check_result = 1;
         check_result = check_result & ((o_xfer_count_arg == o_xfer_count) !== 0);
         check_result = check_result & ((i_xfer_count_arg == i_xfer_count) !== 0);
         check_result = check_result & ((o_last_tdata_arg == o_last_tdata) !== 0);
         check_result = check_result & ((error_arg == error) != 0);
         
         if (check_result) begin
            $display ("... Passed");
         end else begin
            $display ("... FAILED!!!");
            $display ("o_xfer_count = %d (Expected %d)",o_xfer_count,o_xfer_count_arg);
            $display ("i_xfer_count = %d (Expected %d)",i_xfer_count,i_xfer_count_arg);
            $display ("o_last_tdata = %h (Expected %h)",o_last_tdata,o_last_tdata_arg);
            $display ("error = %d  (Expected %d)",error,error_arg);
         end


         o_xfer_count = 0;
         i_xfer_count = 0;
         o_last_tdata = 64'h0;
      end
   endfunction