data/full_repos/permissive/136422019/src/and32.v
data/verilator_xmls/a0c34d6b-3d00-4020-9683-98316431b404.xml
module and32(
	output wire [31:0] out,
	input wire [31:0] in_a, in_b
);

	assign out = in_a & in_b;
	
endmodule
module and32(
	output wire [31:0] out,
	input wire [31:0] in_a, in_b
);


	assign out = in_a & in_b;
	
endmodule