data/full_repos/permissive/201488448/2_circuits/2_sequential/fsm/02_fsm1s.v
data/verilator_xmls/67f81053-7a98-4389-a020-915686778602.xml
module top_module(clk, reset, in, out);
    input clk;
    input reset;
    input in;
    output out;
    reg out;

	parameter A=0, B=1;
	reg state;
	reg next;
    
    always@(*) begin
		case (state)
			A: next = in ? A : B;
			B: next = in ? B : A;
		endcase
    end
    
    always @(posedge clk) begin
		if (reset) state <= B;
        else state <= next;
	end
    
	assign out = (state==B);
    
endmodule
module top_module(clk, reset, in, out);

    input clk;
    input reset;
    input in;
    output out;
    reg out;

	parameter A=0, B=1;
	reg state;
	reg next;
    
    always@(*) begin
		case (state)
			A: next = in ? A : B;
			B: next = in ? B : A;
		endcase
    end
    
    always @(posedge clk) begin
		if (reset) state <= B;
        else state <= next;
	end
    
	assign out = (state==B);
    
endmodule