data/full_repos/permissive/211316121/lab7_1/Traffic.v
data/verilator_xmls/d80df452-d447-43cb-b1a0-9552c0d2c2a2.xml
module oneSecond(
    input clk,
    input clr,
    output reg oneSec
    );
    
    parameter N = 9_999999;
    reg [31:0] p;
    
    always @(posedge clk)
    if(clr) p<=0;
    else
    begin
        oneSec <= 0;
        if(p < N)
            p <= p + 1;
        else
        begin
            p <= 0;
            oneSec <= 1;
        end
    end
endmodule
module oneSecond(
    input clk,
    input clr,
    output reg oneSec
    );

    
    parameter N = 9_999999;
    reg [31:0] p;
    
    always @(posedge clk)
    if(clr) p<=0;
    else
    begin
        oneSec <= 0;
        if(p < N)
            p <= p + 1;
        else
        begin
            p <= 0;
            oneSec <= 1;
        end
    end
endmodule