data/full_repos/permissive/1840016/lab5/mips_pipeline.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:139: Signal definition not found, creating implicitly: \'HDU_PCWrite\'\n        else if (HDU_PCWrite)\n                 ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:183: Signal definition not found, creating implicitly: \'HDU_MuxCtl\'\n        if (reset || HDU_MuxCtl)\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:107: Cannot find file containing module: \'reg32\'\n    reg32  IF_PC(clk, reset, IF_pc_final, IF_pc); \n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/1840016/lab5,data/full_repos/permissive/1840016/reg32\n             data/full_repos/permissive/1840016/lab5,data/full_repos/permissive/1840016/reg32.v\n             data/full_repos/permissive/1840016/lab5,data/full_repos/permissive/1840016/reg32.sv\n             reg32\n             reg32.v\n             reg32.sv\n             obj_dir/reg32\n             obj_dir/reg32.v\n             obj_dir/reg32.sv\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:109: Cannot find file containing module: \'add32\'\n    add32  IF_PCADD(IF_pc, 32\'d4, NO_STALL_PC);\n    ^~~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:111: Cannot find file containing module: \'mux2\'\n    mux2   IF_PCMUX_STALL(HDU_PCWrite, NO_STALL_PC, ID_pc4, IF_pc4 );\n    ^~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:118: Cannot find file containing module: \'add32\'\n    add32   IF_JADD(IDIF_JumperSignExtended, IF_PCTOP4, IF_JumperPC);\n    ^~~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:120: Cannot find file containing module: \'mux2\'\n    mux2 #(32) IF_PCMUX(MEM_PCSrc, IF_pc4, MEM_btgt, IF_pc_next);\n    ^~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:126: Cannot find file containing module: \'mux2\'\n    mux2 #(32) IF_JumperPCMUX(IF_Jumper, IF_pc_next, IF_JumperPC, IF_pc_final);\n    ^~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:130: Cannot find file containing module: \'rom32\'\n    rom32   IMEM(IF_pc, IF_instr);\n    ^~~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:158: Cannot find file containing module: \'reg_file\'\n    reg_file RFILE(clk, WB_RegWrite, ID_rs, ID_rt, WB_RegRd, ID_rd1, ID_rd2, WB_wd);\n    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:163: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                           : ... In instance mips_pipeline\n    assign ID_JumperNotSignExtended[31:27] = 4\'d0;\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:168: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                           : ... In instance mips_pipeline\n    assign IDIF_JumperSignExtended[31:27] = 4\'d0;\n                                          ^\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:172: Cannot find file containing module: \'HazardDetect\'\n    HazardDetect HDU(clk, reset, EX_MemRead, EX_rt, EX_rs, ID_rt, ID_rs, HDU_MuxCtl, HDU_PCWrite);\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:174: Cannot find file containing module: \'control_pipeline\'\n    control_pipeline CTL(.opcode(ID_op), .RegDst(ID_RegDst),\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:246: Cannot find file containing module: \'add32\'\n    add32   EX_BRADD(EX_pc4, EX_offset, EX_btgt);\n    ^~~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:248: Cannot find file containing module: \'mux2\'\n    mux2 #(32)  ALUMUX(EX_ALUSrc, EX_rd2, EX_extend, EX_alub);\n    ^~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:251: Cannot find file containing module: \'ForwardUnit\'\n ForwardUnit EX_Forward_Unit(EX_rs, EX_rt, MEM_RegRd, WB_RegRd, MEM_RegWrite, WB_RegWrite, EX_forwarding_a, EX_forwarding_b);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:253: Cannot find file containing module: \'mux3\'\n    mux3 ALUMUX_FWD_A( EX_forwarding_a, \n    ^~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:259: Cannot find file containing module: \'mux3\'\n    mux3 ALUMUX_FWD_B( EX_forwarding_b, \n    ^~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:265: Cannot find file containing module: \'alu\'\n    alu   EX_ALU(EX_Operation, EX_forwarding_out_a, EX_forwarding_out_b, EX_ALUOut, EX_Zero);\n    ^~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:267: Cannot find file containing module: \'mux2\'\n    mux2 #(5)  EX_RFMUX(EX_RegDst, EX_rt, EX_rd, EX_RegRd);\n    ^~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:269: Cannot find file containing module: \'alu_ctl\'\n    alu_ctl  EX_ALUCTL(EX_ALUOp, EX_funct, EX_Operation);\n    ^~~~~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:310: Cannot find file containing module: \'mem32\'\n    mem32   MEM_DMEM(clk, MEM_MemRead, MEM_MemWrite, MEM_ALUOut, MEM_rd2, MEM_memout);\n    ^~~~~\n%Error: data/full_repos/permissive/1840016/lab5/mips_pipeline.v:337: Cannot find file containing module: \'mux2\'\n    mux2 #(32) WB_WRMUX(WB_MemtoReg, WB_ALUOut, WB_memout, WB_wd);\n    ^~~~\n%Error: Exiting due to 20 error(s), 4 warning(s)\n'
module mips_pipeline(clk, reset);
input clk, reset;






    
    wire [31:0] IF_instr, IF_pc, IF_pc_next, IF_pc_final, IF_pc4, IF_PCTOP4, NO_STALL_PC;
    wire IF_Jumper;



    reg [31:0] IFPCPrev;

    reg [31:0]  ID_instr, ID_pc4;

    wire [5:0]  ID_op;
    wire [4:0]  ID_rs, ID_rt, ID_rd;
    wire [15:0] ID_immed;
    wire [31:0] ID_extend, ID_rd1, ID_rd2;
    

    wire [31:0] ID_JumperNotSignExtended;
    wire [31:0] IDIF_JumperSignExtended;
    wire [31:0] IF_JumperPC;

    assign ID_op = ID_instr[31:26];
    assign ID_rs = ID_instr[25:21];
    assign ID_rt = ID_instr[20:16];
    assign ID_rd = ID_instr[15:11];
    assign ID_immed = ID_instr[15:0];

    wire ID_RegWrite, ID_Branch, ID_RegDst, ID_MemtoReg,
         ID_MemRead, ID_MemWrite, ID_ALUSrc;
    wire [1:0] ID_ALUOp;



    reg  [31:0] EX_pc4, EX_extend, EX_rd1, EX_rd2;
    wire [31:0] EX_offset, EX_btgt, EX_alub, EX_ALUOut;
    reg  [4:0]  EX_rt, EX_rd, EX_rs;
    wire [4:0]  EX_RegRd;
    wire [5:0]  EX_funct;
       

    wire [31:0] EX_forwarding_out_a, EX_forwarding_out_b;
    wire [1:0]  EX_forwarding_a, EX_forwarding_b;
    
    reg  EX_RegWrite, EX_Branch, EX_RegDst, EX_MemtoReg,
         EX_MemRead, EX_MemWrite, EX_ALUSrc;

    wire EX_Zero;

    reg  [1:0] EX_ALUOp;
    wire [2:0] EX_Operation;



    wire MEM_PCSrc;

    reg  MEM_RegWrite, MEM_Branch, MEM_MemtoReg, 
         MEM_MemRead, MEM_MemWrite, MEM_Zero;

    reg  [31:0] MEM_btgt, MEM_ALUOut, MEM_rd2;
    wire [31:0] MEM_memout;
    reg  [4:0] MEM_RegRd;



    reg WB_RegWrite, WB_MemtoReg;

    reg  [31:0] WB_memout, WB_ALUOut;
    wire [31:0] WB_wd;
    reg  [4:0] WB_RegRd;
    
    








    reg32		IF_PC(clk, reset, IF_pc_final, IF_pc); 
    
    add32 	IF_PCADD(IF_pc, 32'd4, NO_STALL_PC);
    
    mux2   IF_PCMUX_STALL(HDU_PCWrite, NO_STALL_PC, ID_pc4, IF_pc4 );
    
    assign IF_PCTOP4[31:0] = 32'd0;
    assign IF_PCTOP4[31:27] = IF_pc4[31:27];
    


    add32   IF_JADD(IDIF_JumperSignExtended, IF_PCTOP4, IF_JumperPC);
  
    mux2 #(32)	IF_PCMUX(MEM_PCSrc, IF_pc4, MEM_btgt, IF_pc_next);
  




    mux2 #(32) IF_JumperPCMUX(IF_Jumper, IF_pc_next, IF_JumperPC, IF_pc_final);
    

    
    rom32 		IMEM(IF_pc, IF_instr);

    always @(posedge clk)
    begin
        if (reset)
        begin
            ID_instr <= 0;
            ID_pc4   <= 0;
        end
        else if (HDU_PCWrite)
        begin
            ID_instr <= ID_instr;
            ID_pc4   <= ID_pc4;
        end    
        else 
        begin
            ID_instr <= IF_instr;
            ID_pc4   <= IF_pc_final;
        end
    end




    



    reg_file	RFILE(clk, WB_RegWrite, ID_rs, ID_rt, WB_RegRd, ID_rd1, ID_rd2, WB_wd);


    assign ID_extend = { {16{ID_immed[15]}}, ID_immed };
    
    assign ID_JumperNotSignExtended[31:27] = 4'd0;
    assign ID_JumperNotSignExtended[26:0] = ID_instr[26:0];
    

    assign IDIF_JumperSignExtended = ID_JumperNotSignExtended << 2;
    assign IDIF_JumperSignExtended[31:27] = 4'd0;
    

    
    HazardDetect HDU(clk, reset, EX_MemRead, EX_rt, EX_rs, ID_rt, ID_rs, HDU_MuxCtl, HDU_PCWrite);

    control_pipeline CTL(.opcode(ID_op), .RegDst(ID_RegDst),
                       .ALUSrc(ID_ALUSrc), .MemtoReg(ID_MemtoReg), 
                       .RegWrite(ID_RegWrite), .MemRead(ID_MemRead),
                       .MemWrite(ID_MemWrite), .Branch(ID_Branch), 
                       .ALUOp(ID_ALUOp), .Jumper(IF_Jumper));


    always @(posedge clk)
    begin
        if (reset || HDU_MuxCtl)
        begin
            EX_RegDst   <= 0;
	          EX_ALUOp    <= 0;
            EX_ALUSrc   <= 0;
            EX_Branch   <= 0;
            EX_MemRead  <= 0;
            EX_MemWrite <= 0;
            EX_RegWrite <= 0;
            EX_MemtoReg <= 0;
            EX_RegDst   <= 0;
            EX_ALUOp    <= 0;
            EX_ALUSrc   <= 0;
            EX_Branch   <= 0;
            EX_MemRead  <= 0;
            EX_MemWrite <= 0;
            EX_RegWrite <= 0;
            EX_MemtoReg <= 0;

            EX_pc4      <= 0;
            EX_rd1      <= 0;
            EX_rd2      <= 0;
            EX_extend   <= 0;
            EX_rt       <= 0;
            EX_rd       <= 0;
        end
        else begin
            
            EX_RegDst   <= ID_RegDst;
            EX_ALUOp    <= ID_ALUOp;
            EX_ALUSrc   <= ID_ALUSrc;
            EX_Branch   <= ID_Branch;
            EX_MemRead  <= ID_MemRead;
            EX_MemWrite <= ID_MemWrite;
            EX_RegWrite <= ID_RegWrite;
            EX_MemtoReg <= ID_MemtoReg;
            EX_RegDst   <= ID_RegDst;
            EX_ALUOp    <= ID_ALUOp;
            EX_ALUSrc   <= ID_ALUSrc;
            EX_Branch   <= ID_Branch;
            EX_MemRead  <= ID_MemRead;
            EX_MemWrite <= ID_MemWrite;
            EX_RegWrite <= ID_RegWrite;
            EX_MemtoReg <= ID_MemtoReg;
            EX_pc4      <= ID_pc4;
            EX_rd1      <= ID_rd1;
            EX_rd2      <= ID_rd2;
            EX_extend   <= ID_extend;
            EX_rt       <= ID_rt;
            EX_rd       <= ID_rd;
            EX_rs       <= ID_rs;
        end  
    end






    assign EX_offset = EX_extend << 2;

    assign EX_funct = EX_extend[5:0];  

    add32 		EX_BRADD(EX_pc4, EX_offset, EX_btgt);

    mux2 #(32) 	ALUMUX(EX_ALUSrc, EX_rd2, EX_extend, EX_alub);
    

	ForwardUnit EX_Forward_Unit(EX_rs, EX_rt, MEM_RegRd, WB_RegRd, MEM_RegWrite, WB_RegWrite, EX_forwarding_a, EX_forwarding_b);
       
    mux3 ALUMUX_FWD_A( EX_forwarding_a, 
    				   EX_rd1,
    				   MEM_ALUOut,
    				   WB_wd,
    				   EX_forwarding_out_a );
    				   
    mux3 ALUMUX_FWD_B( EX_forwarding_b, 
    				   EX_alub,
    				   MEM_ALUOut,
    				   WB_wd,
    				   EX_forwarding_out_b );

    alu 		EX_ALU(EX_Operation, EX_forwarding_out_a, EX_forwarding_out_b, EX_ALUOut, EX_Zero);

    mux2 #(5) 	EX_RFMUX(EX_RegDst, EX_rt, EX_rd, EX_RegRd);

    alu_ctl 	EX_ALUCTL(EX_ALUOp, EX_funct, EX_Operation);
    
    

    always @(posedge clk)
    begin
        if (reset)
        begin
            MEM_Branch   <= 0;
            MEM_MemRead  <= 0;
            MEM_MemWrite <= 0;
            MEM_RegWrite <= 0;
            MEM_MemtoReg <= 0;
            MEM_Zero     <= 0;

            MEM_btgt     <= 0;
            MEM_ALUOut   <= 0;
            MEM_rd2      <= 0;
            MEM_RegRd    <= 0;
        end
        else begin
            MEM_Branch   <= EX_Branch;
            MEM_MemRead  <= EX_MemRead;
            MEM_MemWrite <= EX_MemWrite;
            MEM_RegWrite <= EX_RegWrite;
            MEM_MemtoReg <= EX_MemtoReg;
            MEM_Zero     <= EX_Zero;

            MEM_btgt     <= EX_btgt;
            MEM_ALUOut   <= EX_ALUOut;
            MEM_rd2      <= EX_rd2;
            MEM_RegRd    <= EX_RegRd;
        end
    end







    mem32 		MEM_DMEM(clk, MEM_MemRead, MEM_MemWrite, MEM_ALUOut, MEM_rd2, MEM_memout);

    and  		MEM_BR_AND(MEM_PCSrc, MEM_Branch, MEM_Zero);

    always @(posedge clk)
    begin
        if (reset)
        begin
            WB_RegWrite <= 0;
            WB_MemtoReg <= 0;
            WB_ALUOut   <= 0;
            WB_memout   <= 0;
            WB_RegRd    <= 0;
        end
        else begin
            WB_RegWrite <= MEM_RegWrite;
            WB_MemtoReg <= MEM_MemtoReg;
            WB_ALUOut   <= MEM_ALUOut;
            WB_memout   <= MEM_memout;
            WB_RegRd    <= MEM_RegRd;
        end
    end       





    mux2 #(32)	WB_WRMUX(WB_MemtoReg, WB_ALUOut, WB_memout, WB_wd);


endmodule
module mips_pipeline(clk, reset);

input clk, reset;






    
    wire [31:0] IF_instr, IF_pc, IF_pc_next, IF_pc_final, IF_pc4, IF_PCTOP4, NO_STALL_PC;
    wire IF_Jumper;



    reg [31:0] IFPCPrev;

    reg [31:0]  ID_instr, ID_pc4;

    wire [5:0]  ID_op;
    wire [4:0]  ID_rs, ID_rt, ID_rd;
    wire [15:0] ID_immed;
    wire [31:0] ID_extend, ID_rd1, ID_rd2;
    

    wire [31:0] ID_JumperNotSignExtended;
    wire [31:0] IDIF_JumperSignExtended;
    wire [31:0] IF_JumperPC;

    assign ID_op = ID_instr[31:26];
    assign ID_rs = ID_instr[25:21];
    assign ID_rt = ID_instr[20:16];
    assign ID_rd = ID_instr[15:11];
    assign ID_immed = ID_instr[15:0];

    wire ID_RegWrite, ID_Branch, ID_RegDst, ID_MemtoReg,
         ID_MemRead, ID_MemWrite, ID_ALUSrc;
    wire [1:0] ID_ALUOp;



    reg  [31:0] EX_pc4, EX_extend, EX_rd1, EX_rd2;
    wire [31:0] EX_offset, EX_btgt, EX_alub, EX_ALUOut;
    reg  [4:0]  EX_rt, EX_rd, EX_rs;
    wire [4:0]  EX_RegRd;
    wire [5:0]  EX_funct;
       

    wire [31:0] EX_forwarding_out_a, EX_forwarding_out_b;
    wire [1:0]  EX_forwarding_a, EX_forwarding_b;
    
    reg  EX_RegWrite, EX_Branch, EX_RegDst, EX_MemtoReg,
         EX_MemRead, EX_MemWrite, EX_ALUSrc;

    wire EX_Zero;

    reg  [1:0] EX_ALUOp;
    wire [2:0] EX_Operation;



    wire MEM_PCSrc;

    reg  MEM_RegWrite, MEM_Branch, MEM_MemtoReg, 
         MEM_MemRead, MEM_MemWrite, MEM_Zero;

    reg  [31:0] MEM_btgt, MEM_ALUOut, MEM_rd2;
    wire [31:0] MEM_memout;
    reg  [4:0] MEM_RegRd;



    reg WB_RegWrite, WB_MemtoReg;

    reg  [31:0] WB_memout, WB_ALUOut;
    wire [31:0] WB_wd;
    reg  [4:0] WB_RegRd;
    
    








    reg32		IF_PC(clk, reset, IF_pc_final, IF_pc); 
    
    add32 	IF_PCADD(IF_pc, 32'd4, NO_STALL_PC);
    
    mux2   IF_PCMUX_STALL(HDU_PCWrite, NO_STALL_PC, ID_pc4, IF_pc4 );
    
    assign IF_PCTOP4[31:0] = 32'd0;
    assign IF_PCTOP4[31:27] = IF_pc4[31:27];
    


    add32   IF_JADD(IDIF_JumperSignExtended, IF_PCTOP4, IF_JumperPC);
  
    mux2 #(32)	IF_PCMUX(MEM_PCSrc, IF_pc4, MEM_btgt, IF_pc_next);
  




    mux2 #(32) IF_JumperPCMUX(IF_Jumper, IF_pc_next, IF_JumperPC, IF_pc_final);
    

    
    rom32 		IMEM(IF_pc, IF_instr);

    always @(posedge clk)
    begin
        if (reset)
        begin
            ID_instr <= 0;
            ID_pc4   <= 0;
        end
        else if (HDU_PCWrite)
        begin
            ID_instr <= ID_instr;
            ID_pc4   <= ID_pc4;
        end    
        else 
        begin
            ID_instr <= IF_instr;
            ID_pc4   <= IF_pc_final;
        end
    end




    



    reg_file	RFILE(clk, WB_RegWrite, ID_rs, ID_rt, WB_RegRd, ID_rd1, ID_rd2, WB_wd);


    assign ID_extend = { {16{ID_immed[15]}}, ID_immed };
    
    assign ID_JumperNotSignExtended[31:27] = 4'd0;
    assign ID_JumperNotSignExtended[26:0] = ID_instr[26:0];
    

    assign IDIF_JumperSignExtended = ID_JumperNotSignExtended << 2;
    assign IDIF_JumperSignExtended[31:27] = 4'd0;
    

    
    HazardDetect HDU(clk, reset, EX_MemRead, EX_rt, EX_rs, ID_rt, ID_rs, HDU_MuxCtl, HDU_PCWrite);

    control_pipeline CTL(.opcode(ID_op), .RegDst(ID_RegDst),
                       .ALUSrc(ID_ALUSrc), .MemtoReg(ID_MemtoReg), 
                       .RegWrite(ID_RegWrite), .MemRead(ID_MemRead),
                       .MemWrite(ID_MemWrite), .Branch(ID_Branch), 
                       .ALUOp(ID_ALUOp), .Jumper(IF_Jumper));


    always @(posedge clk)
    begin
        if (reset || HDU_MuxCtl)
        begin
            EX_RegDst   <= 0;
	          EX_ALUOp    <= 0;
            EX_ALUSrc   <= 0;
            EX_Branch   <= 0;
            EX_MemRead  <= 0;
            EX_MemWrite <= 0;
            EX_RegWrite <= 0;
            EX_MemtoReg <= 0;
            EX_RegDst   <= 0;
            EX_ALUOp    <= 0;
            EX_ALUSrc   <= 0;
            EX_Branch   <= 0;
            EX_MemRead  <= 0;
            EX_MemWrite <= 0;
            EX_RegWrite <= 0;
            EX_MemtoReg <= 0;

            EX_pc4      <= 0;
            EX_rd1      <= 0;
            EX_rd2      <= 0;
            EX_extend   <= 0;
            EX_rt       <= 0;
            EX_rd       <= 0;
        end
        else begin
            
            EX_RegDst   <= ID_RegDst;
            EX_ALUOp    <= ID_ALUOp;
            EX_ALUSrc   <= ID_ALUSrc;
            EX_Branch   <= ID_Branch;
            EX_MemRead  <= ID_MemRead;
            EX_MemWrite <= ID_MemWrite;
            EX_RegWrite <= ID_RegWrite;
            EX_MemtoReg <= ID_MemtoReg;
            EX_RegDst   <= ID_RegDst;
            EX_ALUOp    <= ID_ALUOp;
            EX_ALUSrc   <= ID_ALUSrc;
            EX_Branch   <= ID_Branch;
            EX_MemRead  <= ID_MemRead;
            EX_MemWrite <= ID_MemWrite;
            EX_RegWrite <= ID_RegWrite;
            EX_MemtoReg <= ID_MemtoReg;
            EX_pc4      <= ID_pc4;
            EX_rd1      <= ID_rd1;
            EX_rd2      <= ID_rd2;
            EX_extend   <= ID_extend;
            EX_rt       <= ID_rt;
            EX_rd       <= ID_rd;
            EX_rs       <= ID_rs;
        end  
    end






    assign EX_offset = EX_extend << 2;

    assign EX_funct = EX_extend[5:0];  

    add32 		EX_BRADD(EX_pc4, EX_offset, EX_btgt);

    mux2 #(32) 	ALUMUX(EX_ALUSrc, EX_rd2, EX_extend, EX_alub);
    

	ForwardUnit EX_Forward_Unit(EX_rs, EX_rt, MEM_RegRd, WB_RegRd, MEM_RegWrite, WB_RegWrite, EX_forwarding_a, EX_forwarding_b);
       
    mux3 ALUMUX_FWD_A( EX_forwarding_a, 
    				   EX_rd1,
    				   MEM_ALUOut,
    				   WB_wd,
    				   EX_forwarding_out_a );
    				   
    mux3 ALUMUX_FWD_B( EX_forwarding_b, 
    				   EX_alub,
    				   MEM_ALUOut,
    				   WB_wd,
    				   EX_forwarding_out_b );

    alu 		EX_ALU(EX_Operation, EX_forwarding_out_a, EX_forwarding_out_b, EX_ALUOut, EX_Zero);

    mux2 #(5) 	EX_RFMUX(EX_RegDst, EX_rt, EX_rd, EX_RegRd);

    alu_ctl 	EX_ALUCTL(EX_ALUOp, EX_funct, EX_Operation);
    
    

    always @(posedge clk)
    begin
        if (reset)
        begin
            MEM_Branch   <= 0;
            MEM_MemRead  <= 0;
            MEM_MemWrite <= 0;
            MEM_RegWrite <= 0;
            MEM_MemtoReg <= 0;
            MEM_Zero     <= 0;

            MEM_btgt     <= 0;
            MEM_ALUOut   <= 0;
            MEM_rd2      <= 0;
            MEM_RegRd    <= 0;
        end
        else begin
            MEM_Branch   <= EX_Branch;
            MEM_MemRead  <= EX_MemRead;
            MEM_MemWrite <= EX_MemWrite;
            MEM_RegWrite <= EX_RegWrite;
            MEM_MemtoReg <= EX_MemtoReg;
            MEM_Zero     <= EX_Zero;

            MEM_btgt     <= EX_btgt;
            MEM_ALUOut   <= EX_ALUOut;
            MEM_rd2      <= EX_rd2;
            MEM_RegRd    <= EX_RegRd;
        end
    end







    mem32 		MEM_DMEM(clk, MEM_MemRead, MEM_MemWrite, MEM_ALUOut, MEM_rd2, MEM_memout);

    and  		MEM_BR_AND(MEM_PCSrc, MEM_Branch, MEM_Zero);

    always @(posedge clk)
    begin
        if (reset)
        begin
            WB_RegWrite <= 0;
            WB_MemtoReg <= 0;
            WB_ALUOut   <= 0;
            WB_memout   <= 0;
            WB_RegRd    <= 0;
        end
        else begin
            WB_RegWrite <= MEM_RegWrite;
            WB_MemtoReg <= MEM_MemtoReg;
            WB_ALUOut   <= MEM_ALUOut;
            WB_memout   <= MEM_memout;
            WB_RegRd    <= MEM_RegRd;
        end
    end       





    mux2 #(32)	WB_WRMUX(WB_MemtoReg, WB_ALUOut, WB_memout, WB_wd);


endmodule