data/full_repos/permissive/183843067/passwd.v
1: b'%Warning-WIDTH: data/full_repos/permissive/183843067/passwd.v:195: Input port connection \'K\' expects 10 bits on the pin connection, but pin connection\'s VARREF \'SYS_K\' generates 1 bits.\n                                                                 : ... In instance Top\nPasswd PASS(.CLK(SYS_CLK),.del(SYS_DEL),.K(SYS_K),.lock(SYS_LOCK),.Data(USER_DATA));\n                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Display(
	input [15:0] DataIn,
	input CLK,
	output reg [3:0] Data,
	output reg [3:0] Ctrl
);

integer i;
initial
	begin
		i=0;
		Data<=4'b1111;
		Ctrl<=4'b1111;
	end

always @ ( posedge CLK )
	begin
		case(i)
			0: 
				begin
					Data<=DataIn[15:12];
					Ctrl<=4'b0111;
				end
			1:
				begin
					Data<=DataIn[11:8];
					Ctrl<=4'b1011;
				end
			2:
				begin
					Data<=DataIn[7:4];
					Ctrl<=4'b1101;
				end
			3:
				begin
					Data<=DataIn[3:0];
					Ctrl<=4'b1110;
				end
			default:
				begin
					Data<=4'b1111;
					Ctrl<=4'b1111;
				end
		endcase
		i=i+1;
		if ( i==4)
			i=0;
	end

endmodule
module Display(
	input [15:0] DataIn,
	input CLK,
	output reg [3:0] Data,
	output reg [3:0] Ctrl
);


integer i;
initial
	begin
		i=0;
		Data<=4'b1111;
		Ctrl<=4'b1111;
	end

always @ ( posedge CLK )
	begin
		case(i)
			0: 
				begin
					Data<=DataIn[15:12];
					Ctrl<=4'b0111;
				end
			1:
				begin
					Data<=DataIn[11:8];
					Ctrl<=4'b1011;
				end
			2:
				begin
					Data<=DataIn[7:4];
					Ctrl<=4'b1101;
				end
			3:
				begin
					Data<=DataIn[3:0];
					Ctrl<=4'b1110;
				end
			default:
				begin
					Data<=4'b1111;
					Ctrl<=4'b1111;
				end
		endcase
		i=i+1;
		if ( i==4)
			i=0;
	end

endmodule