data/full_repos/permissive/129127690/memory_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/129127690/memory_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129127690/memory_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129127690/memory_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129127690/memory_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129127690/memory_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129127690/memory_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n   clk <= 1; #10; clk <= 0; #10;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/129127690/memory_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n   clk <= 1; #10; clk <= 0; #10;\n                            ^\n%Error: data/full_repos/permissive/129127690/memory_tb.v:11: Cannot find file containing module: \'memory\'\n memory #(32) rmem(dira,dirwrite,datawrite,clk,memwrite,memread,a);\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/memory\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/memory.v\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/memory.sv\n             memory\n             memory.v\n             memory.sv\n             obj_dir/memory\n             obj_dir/memory.v\n             obj_dir/memory.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_tb ();

	reg [31:0] dira,dirb,dirwrite;
	
	wire [31:0] a,b;
	
	reg[31:0] datawrite;
	
	reg clk,memwrite,memread;
	
	memory #(32) rmem(dira,dirwrite,datawrite,clk,memwrite,memread,a);

	
	
	initial begin
		
		dirb <= 0;
		memwrite <= 1;
		memread <= 1;
		dirwrite <= 5;
		datawrite <= 54;
		dira <= 5;
		#20
		
		
		memwrite <= 1;
		memread <= 1;
		dirwrite <= 8;
		datawrite <= 4;
		dira <= 5;
		#20
		
		memwrite <= 0;
		memread <= 1;
		dira <= 8;
		#20
		
		memwrite <= 0;
		memread <= 1;
		dirb <= 8;
		#20
		
		
		memwrite <= 0;
		memread <= 1;
		dirb <= 5;
		#20;
	
	end
	
	
		always
		begin
			clk <= 1; #10; clk <= 0; #10;
		end
	
	
endmodule
module memory_tb ();


	reg [31:0] dira,dirb,dirwrite;
	
	wire [31:0] a,b;
	
	reg[31:0] datawrite;
	
	reg clk,memwrite,memread;
	
	memory #(32) rmem(dira,dirwrite,datawrite,clk,memwrite,memread,a);

	
	
	initial begin
		
		dirb <= 0;
		memwrite <= 1;
		memread <= 1;
		dirwrite <= 5;
		datawrite <= 54;
		dira <= 5;
		#20
		
		
		memwrite <= 1;
		memread <= 1;
		dirwrite <= 8;
		datawrite <= 4;
		dira <= 5;
		#20
		
		memwrite <= 0;
		memread <= 1;
		dira <= 8;
		#20
		
		memwrite <= 0;
		memread <= 1;
		dirb <= 8;
		#20
		
		
		memwrite <= 0;
		memread <= 1;
		dirb <= 5;
		#20;
	
	end
	
	
		always
		begin
			clk <= 1; #10; clk <= 0; #10;
		end
	
	
endmodule