data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire/tart_acquire.v
None: at end of input
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire/tart_acquire.v:77: Cannot find include file: tartcfg.v\n`include "tartcfg.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire,data/full_repos/permissive/20430511/tartcfg.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire,data/full_repos/permissive/20430511/tartcfg.v.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/acquire,data/full_repos/permissive/20430511/tartcfg.v.sv\n             tartcfg.v\n             tartcfg.v.v\n             tartcfg.v.sv\n             obj_dir/tartcfg.v\n             obj_dir/tartcfg.v.v\n             obj_dir/tartcfg.v.sv\n%Error: Exiting due to 1 error(s)\n'
module tart_acquire
  #(
    parameter AXNUM = 24,
    parameter MSB   = AXNUM-1,


    parameter ABITS = 21,
    parameter ASB   = ABITS-1,


    parameter BBITS = 8,
    parameter BSB   = BBITS-1,
    parameter KBITS = BBITS*3,
    parameter KSB   = KBITS-1,
    parameter XBITS = 4,
    parameter XSB   = XBITS-1,


    parameter PIPED = 1,
    parameter CHECK = 1,
    parameter RESET = 0,


    parameter DELAY = 3)
   (
    input          clock_i,
    input          reset_i,


    input          locked_i,
    input          strobe_i,
    input          middle_i,
    input [MSB:0]  signal_i,


    input          cyc_i,
    input          stb_i,
    input          we_i,
    output         ack_o,
    output         wat_o,
    output         rty_o,
    output         err_o,
    input [1:0]    adr_i,
    input [BSB:0]  dat_i,
    output [BSB:0] dat_o,


    input          io_busy_i,


    output         mcb_ce_o,
    output         mcb_wr_o,
    input          mcb_rdy_i,
    input          mcb_ack_i,
    output [ASB:0] mcb_adr_o,
    input [31:0]   mcb_dat_i,
    output [31:0]  mcb_dat_o,


    output         enabled_o,
    output         oflow_o,
    output [2:0]   state_o
    );





   wire            cyc_w, stb_w, ack_w;
   reg             ack = 1'b0;
   reg [BSB:0]     dat = {BBITS{1'b0}};
   wire [BSB:0]    dat_w;
   wire            fetch, store;



   wire [BSB:0]    aq_stream, aq_system;
   reg             en_acquire = 1'b0;



   wire [MSB:0]    data_in;
   wire            request, mcb_512mb;
   reg             mcb_err = 1'b0, mcb_wat = 1'b0, active = 1'b0;
   wire [2:0]      cap_state;



   reg             data_sent = 1'b0;
   reg [1:0]       index = 2'h0;
   wire            send, wrap_index, oflow;
   wire [2:0]      next_index;





   assign enabled_o  = en_acquire;
   assign oflow_o    = oflow;
   assign state_o    = cap_state;







   assign aq_stream  = index == 2'b00 ? data_in[23:16] :
                       index == 2'b01 ? data_in[15: 8] :
                       data_in[7:0];


   assign aq_system  = {en_acquire, mcb_err, mcb_rdy_i, mcb_512mb, oflow, cap_state};


   assign mcb_512mb  = ABITS >= 25;





   assign ack_o      = ack;
   assign wat_o      = 1'b0;
   assign rty_o      = 1'b0;
   assign err_o      = 1'b0;
   assign dat_o      = dat;


   assign cyc_w      = CHECK ? cyc_i : 1'b1;
   assign stb_w      = cyc_w && stb_i;
   assign ack_w      = PIPED ? stb_w : stb_w && !ack;
   assign dat_w      = dat;


   assign fetch      = PIPED ? stb_w && !we_i : stb_w && !we_i &&  ack;
   assign store      = PIPED ? stb_w &&  we_i : stb_w &&  we_i && !ack;





   assign send       = fetch && adr_i == `AQ_STREAM && active;
   assign wrap_index = index == 2'b10;
   assign next_index = wrap_index ? 3'h0 : index + 1;









   always @(posedge clock_i)
     if (reset_i && RESET)
       ack <= #DELAY 1'b0;
     else
       ack <= #DELAY ack_w;






   always @(posedge clock_i)
     if (stb_w)
       case (adr_i)
         `AQ_STREAM: dat <= #DELAY aq_stream;
         `AQ_SYSTEM: dat <= #DELAY aq_system;
         default:    dat <= #DELAY 8'bx;
       endcase



   always @(posedge clock_i)
     if (reset_i)
       en_acquire <= #DELAY 1'b0;
     else if (store)
       case (adr_i)

         `AQ_SYSTEM: en_acquire <= #DELAY dat_i[BSB];
       endcase










   always @(posedge clock_i)
     if (reset_i && RESET)
       data_sent <= #DELAY 1'b0;
     else
       data_sent <= #DELAY wrap_index && send;




   always @(posedge clock_i)
     if (!io_busy_i)
       index <= #DELAY 2'h0;
     else if (send)
       index <= #DELAY next_index[1:0];



   always @(posedge clock_i)
     if (reset_i && RESET)
       active <= #DELAY 1'b0;
     else if (cap_state > 2)
       active <= #DELAY 1'b1;





   always @(posedge clock_i)
     if (reset_i)
       mcb_wat <= #DELAY 1'b0;
     else if (wrap_index && send)
       mcb_wat <= #DELAY 1'b1;
     else if (mcb_ack_i)
       mcb_wat <= #DELAY 1'b0;

   always @(posedge clock_i)
     if (reset_i)
       mcb_err <= #DELAY 1'b0;
     else if (mcb_wat && send)
       mcb_err <= #DELAY 1'b1;





   dram_prefetch
     #( .WIDTH(AXNUM)
       ) PREFETCH
       (
        .clock_i     (clock_i),
        .reset_i     (reset_i),

        .dram_ready  (mcb_ack_i),
        .dram_request(request),
        .dram_data   (mcb_dat_i[MSB:0]),
        .data_sent   (data_sent),
        .fetched_data(data_in)
        );













   raw_acquire
     #( .AXNUM(AXNUM),
        .ABITS(ABITS),
        .RESET(RESET),
        .DELAY(DELAY)
        ) RAWDATA
       (
        .clock_i  (clock_i),
        .reset_i  (reset_i),


        .locked_i (locked_i),
        .strobe_i (strobe_i),
        .middle_i (middle_i),
        .signal_i (signal_i),


        .capture_i(en_acquire),
        .request_i(request),


        .mcb_ce_o (mcb_ce_o),
        .mcb_wr_o (mcb_wr_o),
        .mcb_rdy_i(mcb_rdy_i),
        .mcb_adr_o(mcb_adr_o),
        .mcb_dat_o(mcb_dat_o),


        .oflow_o  (oflow),
        .state_o  (cap_state)
        );








   initial begin
      if (KBITS < AXNUM) begin : INIT_ERROR
         $write("Invalid initialisation parameters:\n");
         $write("  AXNUM = %1d\n", AXNUM);
         $write("  KBITS = %1d\n", KBITS);
         $write("  BBITS = %1d\n", BBITS);
         $error;
      end
   end



endmodule
module tart_acquire
  #(
    parameter AXNUM = 24,
    parameter MSB   = AXNUM-1,


    parameter ABITS = 21,
    parameter ASB   = ABITS-1,


    parameter BBITS = 8,
    parameter BSB   = BBITS-1,
    parameter KBITS = BBITS*3,
    parameter KSB   = KBITS-1,
    parameter XBITS = 4,
    parameter XSB   = XBITS-1,


    parameter PIPED = 1,
    parameter CHECK = 1,
    parameter RESET = 0,


    parameter DELAY = 3)
   (
    input          clock_i,
    input          reset_i,


    input          locked_i,
    input          strobe_i,
    input          middle_i,
    input [MSB:0]  signal_i,


    input          cyc_i,
    input          stb_i,
    input          we_i,
    output         ack_o,
    output         wat_o,
    output         rty_o,
    output         err_o,
    input [1:0]    adr_i,
    input [BSB:0]  dat_i,
    output [BSB:0] dat_o,


    input          io_busy_i,


    output         mcb_ce_o,
    output         mcb_wr_o,
    input          mcb_rdy_i,
    input          mcb_ack_i,
    output [ASB:0] mcb_adr_o,
    input [31:0]   mcb_dat_i,
    output [31:0]  mcb_dat_o,


    output         enabled_o,
    output         oflow_o,
    output [2:0]   state_o
    );






   wire            cyc_w, stb_w, ack_w;
   reg             ack = 1'b0;
   reg [BSB:0]     dat = {BBITS{1'b0}};
   wire [BSB:0]    dat_w;
   wire            fetch, store;



   wire [BSB:0]    aq_stream, aq_system;
   reg             en_acquire = 1'b0;



   wire [MSB:0]    data_in;
   wire            request, mcb_512mb;
   reg             mcb_err = 1'b0, mcb_wat = 1'b0, active = 1'b0;
   wire [2:0]      cap_state;



   reg             data_sent = 1'b0;
   reg [1:0]       index = 2'h0;
   wire            send, wrap_index, oflow;
   wire [2:0]      next_index;





   assign enabled_o  = en_acquire;
   assign oflow_o    = oflow;
   assign state_o    = cap_state;







   assign aq_stream  = index == 2'b00 ? data_in[23:16] :
                       index == 2'b01 ? data_in[15: 8] :
                       data_in[7:0];


   assign aq_system  = {en_acquire, mcb_err, mcb_rdy_i, mcb_512mb, oflow, cap_state};


   assign mcb_512mb  = ABITS >= 25;





   assign ack_o      = ack;
   assign wat_o      = 1'b0;
   assign rty_o      = 1'b0;
   assign err_o      = 1'b0;
   assign dat_o      = dat;


   assign cyc_w      = CHECK ? cyc_i : 1'b1;
   assign stb_w      = cyc_w && stb_i;
   assign ack_w      = PIPED ? stb_w : stb_w && !ack;
   assign dat_w      = dat;


   assign fetch      = PIPED ? stb_w && !we_i : stb_w && !we_i &&  ack;
   assign store      = PIPED ? stb_w &&  we_i : stb_w &&  we_i && !ack;





   assign send       = fetch && adr_i == `AQ_STREAM && active;
   assign wrap_index = index == 2'b10;
   assign next_index = wrap_index ? 3'h0 : index + 1;









   always @(posedge clock_i)
     if (reset_i && RESET)
       ack <= #DELAY 1'b0;
     else
       ack <= #DELAY ack_w;






   always @(posedge clock_i)
     if (stb_w)
       case (adr_i)
         `AQ_STREAM: dat <= #DELAY aq_stream;
         `AQ_SYSTEM: dat <= #DELAY aq_system;
         default:    dat <= #DELAY 8'bx;
       endcase



   always @(posedge clock_i)
     if (reset_i)
       en_acquire <= #DELAY 1'b0;
     else if (store)
       case (adr_i)

         `AQ_SYSTEM: en_acquire <= #DELAY dat_i[BSB];
       endcase










   always @(posedge clock_i)
     if (reset_i && RESET)
       data_sent <= #DELAY 1'b0;
     else
       data_sent <= #DELAY wrap_index && send;




   always @(posedge clock_i)
     if (!io_busy_i)
       index <= #DELAY 2'h0;
     else if (send)
       index <= #DELAY next_index[1:0];



   always @(posedge clock_i)
     if (reset_i && RESET)
       active <= #DELAY 1'b0;
     else if (cap_state > 2)
       active <= #DELAY 1'b1;





   always @(posedge clock_i)
     if (reset_i)
       mcb_wat <= #DELAY 1'b0;
     else if (wrap_index && send)
       mcb_wat <= #DELAY 1'b1;
     else if (mcb_ack_i)
       mcb_wat <= #DELAY 1'b0;

   always @(posedge clock_i)
     if (reset_i)
       mcb_err <= #DELAY 1'b0;
     else if (mcb_wat && send)
       mcb_err <= #DELAY 1'b1;





   dram_prefetch
     #( .WIDTH(AXNUM)
       ) PREFETCH
       (
        .clock_i     (clock_i),
        .reset_i     (reset_i),

        .dram_ready  (mcb_ack_i),
        .dram_request(request),
        .dram_data   (mcb_dat_i[MSB:0]),
        .data_sent   (data_sent),
        .fetched_data(data_in)
        );













   raw_acquire
     #( .AXNUM(AXNUM),
        .ABITS(ABITS),
        .RESET(RESET),
        .DELAY(DELAY)
        ) RAWDATA
       (
        .clock_i  (clock_i),
        .reset_i  (reset_i),


        .locked_i (locked_i),
        .strobe_i (strobe_i),
        .middle_i (middle_i),
        .signal_i (signal_i),


        .capture_i(en_acquire),
        .request_i(request),


        .mcb_ce_o (mcb_ce_o),
        .mcb_wr_o (mcb_wr_o),
        .mcb_rdy_i(mcb_rdy_i),
        .mcb_adr_o(mcb_adr_o),
        .mcb_dat_o(mcb_dat_o),


        .oflow_o  (oflow),
        .state_o  (cap_state)
        );








   initial begin
      if (KBITS < AXNUM) begin : INIT_ERROR
         $write("Invalid initialisation parameters:\n");
         $write("  AXNUM = %1d\n", AXNUM);
         $write("  KBITS = %1d\n", KBITS);
         $write("  BBITS = %1d\n", BBITS);
         $error;
      end
   end



endmodule