data/full_repos/permissive/169661644/hw3_1/mux2_1.v
data/verilator_xmls/7abe88b4-e0d9-4dcf-baa8-f0ed038ea2fc.xml
module mux2_1(InA, InB, InC, InD, S, Out);
    input   InA, InB, InC, InD;
    input   S;
    output  Out;



endmodule
module mux2_1(InA, InB, InC, InD, S, Out);

    input   InA, InB, InC, InD;
    input   S;
    output  Out;



endmodule