data/full_repos/permissive/108382235/Pipelined.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC,  SwitchClk_10, reset);\n       ^~~~~~~~~\n                                                                       : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_MEM.M_Dmemory\n  if (MemRead) ReadData=Dmemory[Address[31:2]];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_MEM.M_Dmemory\n  else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n                                                                    : ... In instance Pipelined\n   IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n                ^~\n%Error: Exiting due to 5 warning(s)\n'
module IDStage(JumpAddr_28, RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, ALUOp, ReadData1, ReadData2, Immediate_32, PCWrite, IFID_Write, IDEX_Flush1, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, Instruction, WriteReg, WriteData, MEMWB_RegWrite, IDEX_Rt, IDEX_MemRead, clock, reset);
	input MEMWB_RegWrite, IDEX_MemRead, clock, reset;
	input [31:0] Instruction, WriteData;
	input [4:0] IDEX_Rt, WriteReg;
	output [27:0] JumpAddr_28;
	output RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, PCWrite, IFID_Write, IDEX_Flush1;
	output [1:0] ALUOp;
	output [31:0] ReadData1, ReadData2, Immediate_32,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
	
	wire [27:0] JumpAddr_28;
	wire RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, PCWrite, IFID_Write, IDEX_Flush1, Andi;
	wire [1:0] ALUOp;
	wire [31:0] ReadData1, ReadData2, Immediate_32, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, Immediate_Zero, Immediate_Sign;
	
	RegisterFile M_RegFile(ReadData1,ReadData2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,Instruction[25:21],Instruction[20:16],WriteReg,WriteData,MEMWB_RegWrite,clock, reset);
	Control M_Control(RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Andi, Instruction[31:26]);
	ZeroExtend M_ZeroExtend(Immediate_Zero, Instruction[15:0]);
	SignExtend M_SignExtend(Immediate_Sign, Instruction[15:0]);
	Mux_32bit_2to1 M_Mux_Addi(Immediate_32, Immediate_Sign, Immediate_Zero, Andi);
	ShiftLeftTwo_26to28 M_Shift_Jump(JumpAddr_28, Instruction[25:0]);
	LoadUseHazardDetectionUnit M_LoadUse(PCWrite, IFID_Write, IDEX_Flush1, Instruction[31:26], Instruction[25:21], Instruction[20:16], IDEX_MemRead, IDEX_Rt);
endmodule
module IDStage(JumpAddr_28, RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, ALUOp, ReadData1, ReadData2, Immediate_32, PCWrite, IFID_Write, IDEX_Flush1, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, Instruction, WriteReg, WriteData, MEMWB_RegWrite, IDEX_Rt, IDEX_MemRead, clock, reset);

	input MEMWB_RegWrite, IDEX_MemRead, clock, reset;
	input [31:0] Instruction, WriteData;
	input [4:0] IDEX_Rt, WriteReg;
	output [27:0] JumpAddr_28;
	output RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, PCWrite, IFID_Write, IDEX_Flush1;
	output [1:0] ALUOp;
	output [31:0] ReadData1, ReadData2, Immediate_32,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
	
	wire [27:0] JumpAddr_28;
	wire RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, PCWrite, IFID_Write, IDEX_Flush1, Andi;
	wire [1:0] ALUOp;
	wire [31:0] ReadData1, ReadData2, Immediate_32, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, Immediate_Zero, Immediate_Sign;
	
	RegisterFile M_RegFile(ReadData1,ReadData2,s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,Instruction[25:21],Instruction[20:16],WriteReg,WriteData,MEMWB_RegWrite,clock, reset);
	Control M_Control(RegDst, Jump, Branch, BranchN, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, Andi, Instruction[31:26]);
	ZeroExtend M_ZeroExtend(Immediate_Zero, Instruction[15:0]);
	SignExtend M_SignExtend(Immediate_Sign, Instruction[15:0]);
	Mux_32bit_2to1 M_Mux_Addi(Immediate_32, Immediate_Sign, Immediate_Zero, Andi);
	ShiftLeftTwo_26to28 M_Shift_Jump(JumpAddr_28, Instruction[25:0]);
	LoadUseHazardDetectionUnit M_LoadUse(PCWrite, IFID_Write, IDEX_Flush1, Instruction[31:26], Instruction[25:21], Instruction[20:16], IDEX_MemRead, IDEX_Rt);
endmodule