data/full_repos/permissive/154446712/Digital STDP Implementation/STDP.v
1: b'%Error: Cannot find file containing module: STDP\n        ... Looked in:\n             data/full_repos/permissive/154446712/Digital/STDP\n             data/full_repos/permissive/154446712/Digital/STDP.v\n             data/full_repos/permissive/154446712/Digital/STDP.sv\n             STDP\n             STDP.v\n             STDP.sv\n             obj_dir/STDP\n             obj_dir/STDP.v\n             obj_dir/STDP.sv\n%Error: Cannot find file containing module: Implementation,data/full_repos/permissive/154446712\n%Error: Cannot find file containing module: data/full_repos/permissive/154446712/Digital\n%Error: Cannot find file containing module: Implementation/STDP.v\n%Error: Exiting due to 4 error(s)\n'
module STDP(preSynapticSpike, postSynapticSpike, clk, ENABLE, LEDR, dataToSend);
	input preSynapticSpike;
	input postSynapticSpike;
	input clk;
	input ENABLE;
	output dataToSend;
	output wire [9:0] LEDR;

	integer currentWeight = 0;
	reg [27:0]  clkCount = 28'd0;
	reg STDP_CLK = 0;

	reg signed [17:0] r1 = 0;
	reg signed [17:0] o1 = 0;

	reg [2:0] statePre = 2'b0;
	reg [2:0] nextStatePre = 2'b0;
	reg outPre = 0;
	reg [2:0] statePost = 2'b0;
	reg [2:0] nextStatePost = 2'b0;
	reg outPost = 0;
	localparam A=0, B=1, C=2;

	always @(*)
		begin
			dataToSend.currentSynapticWeight = currentWeight;
		end


	always @ (posedge clk)
		begin

			clkCount <= clkCount + 1;
			if (clkCount == 28'd6250)
				begin
					clkCount <= 0;
					STDP_CLK <= ~STDP_CLK;
				end
		end


	always @ (posedge STDP_CLK)
		begin
			if (ENABLE == 1)
				begin
					currentWeight = currentWeight + 1;
					if (outPre)
						begin

							r1 = 18'sd1;
							o1 = o1 - (o1 >>> 7);

							currentWeight = currentWeight - ((o1 >>> 9));
						end
					else if (outPost)
						begin

							r1 = r1 - (r1 >>> 4);
							o1 = 18'sd1;

							currentWeight = currentWeight + ((r1 >>> 12));
						end
					else begin
						r1 = r1 - (r1 >>> 4);
						o1 = o1 - (o1 >>> 7);
					end
				end
		end


	always @ (posedge STDP_CLK)
		begin
			statePre = nextStatePre;
			case (statePre)
				A : if (preSynapticSpike) nextStatePre = C;
					else nextStatePre = B;
				B : if (preSynapticSpike) begin
						outPre = outPre | 1;
						nextStatePre = C;
					end
				C : if (~preSynapticSpike) nextStatePre = B;
				default : begin
					nextStatePre = 3'bX;
				end
			endcase
			cycleCountPre = cycleCountPre + 1;
			if (cycleCountPre == 0)
				begin
					if (outPre == 1)
						begin
							LEDR[8] <= ~LEDR[8];
						end
					else begin
						LEDR[8] <= 0;
					end
					cycleCountPre <= 1;
					outPre <= 0;
				end
		end


	always @ (posedge STDP_CLK)
		begin
			statePost = nextStatePost;
			case (statePost)
				A : if (postSynapticSpike) nextStatePost = C;
					else nextStatePost = B;
				B : if (postSynapticSpike) begin
						outPost = outPost | 1;
						nextStatePost = C;
					end
				C : if (~postSynapticSpike) nextStatePost = B;
				default : begin

					nextStatePost = 3'bX;
				end
			endcase
			cycleCountPost = cycleCountPost + 1;
			if (cycleCountPost == 0)
				begin
					if (outPost == 1)
						begin
							LEDR[9] <= ~LEDR[9];
						end
					else begin
						LEDR[9] <= 0;
					end
					cycleCountPost <= 1;
					outPost <= 0;
				end
		end
endmodule
module STDP(preSynapticSpike, postSynapticSpike, clk, ENABLE, LEDR, dataToSend);

	input preSynapticSpike;
	input postSynapticSpike;
	input clk;
	input ENABLE;
	output dataToSend;
	output wire [9:0] LEDR;

	integer currentWeight = 0;
	reg [27:0]  clkCount = 28'd0;
	reg STDP_CLK = 0;

	reg signed [17:0] r1 = 0;
	reg signed [17:0] o1 = 0;

	reg [2:0] statePre = 2'b0;
	reg [2:0] nextStatePre = 2'b0;
	reg outPre = 0;
	reg [2:0] statePost = 2'b0;
	reg [2:0] nextStatePost = 2'b0;
	reg outPost = 0;
	localparam A=0, B=1, C=2;

	always @(*)
		begin
			dataToSend.currentSynapticWeight = currentWeight;
		end


	always @ (posedge clk)
		begin

			clkCount <= clkCount + 1;
			if (clkCount == 28'd6250)
				begin
					clkCount <= 0;
					STDP_CLK <= ~STDP_CLK;
				end
		end


	always @ (posedge STDP_CLK)
		begin
			if (ENABLE == 1)
				begin
					currentWeight = currentWeight + 1;
					if (outPre)
						begin

							r1 = 18'sd1;
							o1 = o1 - (o1 >>> 7);

							currentWeight = currentWeight - ((o1 >>> 9));
						end
					else if (outPost)
						begin

							r1 = r1 - (r1 >>> 4);
							o1 = 18'sd1;

							currentWeight = currentWeight + ((r1 >>> 12));
						end
					else begin
						r1 = r1 - (r1 >>> 4);
						o1 = o1 - (o1 >>> 7);
					end
				end
		end


	always @ (posedge STDP_CLK)
		begin
			statePre = nextStatePre;
			case (statePre)
				A : if (preSynapticSpike) nextStatePre = C;
					else nextStatePre = B;
				B : if (preSynapticSpike) begin
						outPre = outPre | 1;
						nextStatePre = C;
					end
				C : if (~preSynapticSpike) nextStatePre = B;
				default : begin
					nextStatePre = 3'bX;
				end
			endcase
			cycleCountPre = cycleCountPre + 1;
			if (cycleCountPre == 0)
				begin
					if (outPre == 1)
						begin
							LEDR[8] <= ~LEDR[8];
						end
					else begin
						LEDR[8] <= 0;
					end
					cycleCountPre <= 1;
					outPre <= 0;
				end
		end


	always @ (posedge STDP_CLK)
		begin
			statePost = nextStatePost;
			case (statePost)
				A : if (postSynapticSpike) nextStatePost = C;
					else nextStatePost = B;
				B : if (postSynapticSpike) begin
						outPost = outPost | 1;
						nextStatePost = C;
					end
				C : if (~postSynapticSpike) nextStatePost = B;
				default : begin

					nextStatePost = 3'bX;
				end
			endcase
			cycleCountPost = cycleCountPost + 1;
			if (cycleCountPost == 0)
				begin
					if (outPost == 1)
						begin
							LEDR[9] <= ~LEDR[9];
						end
					else begin
						LEDR[9] <= 0;
					end
					cycleCountPost <= 1;
					outPost <= 0;
				end
		end
endmodule