data/full_repos/permissive/15946916/Project 2/IdealMemory.v
 line:38: before: "#"
1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/15946916\n        ... Looked in:\n             data/full_repos/permissive/15946916/Project/2,data/full_repos/permissive/15946916\n             data/full_repos/permissive/15946916/Project/2,data/full_repos/permissive/15946916.v\n             data/full_repos/permissive/15946916/Project/2,data/full_repos/permissive/15946916.sv\n             2,data/full_repos/permissive/15946916\n             2,data/full_repos/permissive/15946916.v\n             2,data/full_repos/permissive/15946916.sv\n             obj_dir/2,data/full_repos/permissive/15946916\n             obj_dir/2,data/full_repos/permissive/15946916.v\n             obj_dir/2,data/full_repos/permissive/15946916.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/15946916/Project\n%Error: Cannot find file containing module: 2/IdealMemory.v\n%Error: Exiting due to 3 error(s)\n'
module InstrMem (Mem_Addr, Dout);

   parameter T_rd = 10;
   parameter MemSize = 1024, WordSize = 32;
   
   input  [WordSize-1:0] Mem_Addr;
   output [WordSize-1:0] Dout;
   reg [WordSize-1:0] Dout;
   
   reg [WordSize-1:0] 	 Mem[0:MemSize-1];
   


    `include "imeminit_simple_test.v"
always
      #T_rd assign  Dout = Mem[ Mem_Addr >> 2 ];
endmodule
module InstrMem (Mem_Addr, Dout);


   parameter T_rd = 10;
   parameter MemSize = 1024, WordSize = 32;
   
   input  [WordSize-1:0] Mem_Addr;
   output [WordSize-1:0] Dout;
   reg [WordSize-1:0] Dout;
   
   reg [WordSize-1:0] 	 Mem[0:MemSize-1];
   


    `include "imeminit_simple_test.v"
always
      #T_rd assign  Dout = Mem[ Mem_Addr >> 2 ];
endmodule