data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Square_root/Square_Root_ReciprocalorNo_multicycle_tb.v
 line:247: before: "real"
1: b'%Error: Cannot find file containing module: Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Square_root/Square_Root_ReciprocalorNo_multicycle_tb.v\n%Error: Exiting due to 3 error(s)\n'
module Square_Root_Reciprocal_GS_multicycle_tb;



	parameter WL = 24;
	parameter LUT_bits = 15;
	parameter LUT_addWidth = 12;
	parameter dWL = 26;
	parameter ITERATION = 0;





	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din;


	wire [WL-1:0] dout;



	reg [WL-1:0] Testdata_vec_NR [`Testdata_Depth-1:0];

	reg [WL-1:0] Simu_Result_Matlab [`Testdata_Depth-1:0];
	

	real real_din, real_MATLAB_reuslt, real_Xilinx_result;
	real real_dout;


	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;




	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction



	Square_Root_Reciprocal_GS_multicycle
	#(
		.WL(WL),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth),
		.ITERATION(ITERATION),
		.dWL(dWL)
	  )
	Fang_Square_Root_Reciprocal_GS_multicycle (
		.CLK(CLK), 
		.nRST(nRST), 
		.CE(CE), 
		.din(din), 
		.dout(dout)
	);


	integer count;
	real count_mismatched = 0;
	initial begin







		$readmemb("ini_input_binary_isqt_GS_iter0.txt", Testdata_vec_NR);		
	

		$readmemb("LUT_isqt_GS_iter0.txt", Square_Root_Reciprocal_GS_multicycle_tb.Fang_Square_Root_Reciprocal_GS_multicycle.LUT);
		$readmemb("result_binary_isqt_GS_iter0.txt", Simu_Result_Matlab);



		nRST = 0; CE = 0;
		@(posedge CLK); CE = 1; 
		nRST = 1;
		
		if(ITERATION==0) begin
			for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
				din = Testdata_vec_NR[count];
				$display("MATLAB: %f, Xilinx: %f", unsigned_fixedToFloat(Simu_Result_Matlab[count-2], 1, WL-1), unsigned_fixedToFloat(dout, 1, WL-1));
				if (unsigned_fixedToFloat(Simu_Result_Matlab[count-2], 1, WL-1)-unsigned_fixedToFloat(dout, 1, WL-1)<=2^-23)

					$display("MATCHED");
				else begin
					count_mismatched = count_mismatched + 1;
					$display("MISMATCHED HERE <================= !!! ");
					$display("The NO.%d result is not matched, MATLAB: %b, Xilinx: %b ", count, Simu_Result_Matlab[count-2], dout);
				end
				@(posedge CLK);
				if (count==`Testdata_Depth) begin
					$display("Mismatched proporbility: %f", count_mismatched/`Testdata_Depth);
					$finish;
				end
			end
		end else if (ITERATION == 1) begin
			for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
				din = Testdata_vec_NR[count];
				@(posedge CLK);
				$display("MATLAB: %f, Xilinx: %f", unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1), unsigned_fixedToFloat(dout, 1, WL-1));
				if (unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1)-unsigned_fixedToFloat(dout, 1, WL-1)<=2^-23)

					$display("MATCHED");
				else begin
					count_mismatched = count_mismatched + 1;
					$display("MISMATCHED HERE <================= !!! ");
					$display("The NO.%d result is not matched, MATLAB: %b, Xilinx: %b ", count, Simu_Result_Matlab[count-1], dout);
				end
				@(posedge CLK);
				if (count==`Testdata_Depth) begin
					$display("Mismatched proporbility: %f", count_mismatched/`Testdata_Depth);
					$finish;
				end
			end
		end
	end



	always @ din real_din = unsigned_fixedToFloat(din, 1, WL-1);

	always @ dout real_Xilinx_result = unsigned_fixedToFloat(dout, 1, WL-1);
	always @ Simu_Result_Matlab[count] real_MATLAB_reuslt = unsigned_fixedToFloat(Simu_Result_Matlab[count], 1, WL-1);
	
endmodule
module Square_Root_Reciprocal_GS_multicycle_tb;




	parameter WL = 24;
	parameter LUT_bits = 15;
	parameter LUT_addWidth = 12;
	parameter dWL = 26;
	parameter ITERATION = 0;





	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din;


	wire [WL-1:0] dout;



	reg [WL-1:0] Testdata_vec_NR [`Testdata_Depth-1:0];

	reg [WL-1:0] Simu_Result_Matlab [`Testdata_Depth-1:0];
	

	real real_din, real_MATLAB_reuslt, real_Xilinx_result;
	real real_dout;


	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;




	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction



	Square_Root_Reciprocal_GS_multicycle
	#(
		.WL(WL),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth),
		.ITERATION(ITERATION),
		.dWL(dWL)
	  )
	Fang_Square_Root_Reciprocal_GS_multicycle (
		.CLK(CLK), 
		.nRST(nRST), 
		.CE(CE), 
		.din(din), 
		.dout(dout)
	);


	integer count;
	real count_mismatched = 0;
	initial begin







		$readmemb("ini_input_binary_isqt_GS_iter0.txt", Testdata_vec_NR);		
	

		$readmemb("LUT_isqt_GS_iter0.txt", Square_Root_Reciprocal_GS_multicycle_tb.Fang_Square_Root_Reciprocal_GS_multicycle.LUT);
		$readmemb("result_binary_isqt_GS_iter0.txt", Simu_Result_Matlab);



		nRST = 0; CE = 0;
		@(posedge CLK); CE = 1; 
		nRST = 1;
		
		if(ITERATION==0) begin
			for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
				din = Testdata_vec_NR[count];
				$display("MATLAB: %f, Xilinx: %f", unsigned_fixedToFloat(Simu_Result_Matlab[count-2], 1, WL-1), unsigned_fixedToFloat(dout, 1, WL-1));
				if (unsigned_fixedToFloat(Simu_Result_Matlab[count-2], 1, WL-1)-unsigned_fixedToFloat(dout, 1, WL-1)<=2^-23)

					$display("MATCHED");
				else begin
					count_mismatched = count_mismatched + 1;
					$display("MISMATCHED HERE <================= !!! ");
					$display("The NO.%d result is not matched, MATLAB: %b, Xilinx: %b ", count, Simu_Result_Matlab[count-2], dout);
				end
				@(posedge CLK);
				if (count==`Testdata_Depth) begin
					$display("Mismatched proporbility: %f", count_mismatched/`Testdata_Depth);
					$finish;
				end
			end
		end else if (ITERATION == 1) begin
			for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
				din = Testdata_vec_NR[count];
				@(posedge CLK);
				$display("MATLAB: %f, Xilinx: %f", unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1), unsigned_fixedToFloat(dout, 1, WL-1));
				if (unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1)-unsigned_fixedToFloat(dout, 1, WL-1)<=2^-23)

					$display("MATCHED");
				else begin
					count_mismatched = count_mismatched + 1;
					$display("MISMATCHED HERE <================= !!! ");
					$display("The NO.%d result is not matched, MATLAB: %b, Xilinx: %b ", count, Simu_Result_Matlab[count-1], dout);
				end
				@(posedge CLK);
				if (count==`Testdata_Depth) begin
					$display("Mismatched proporbility: %f", count_mismatched/`Testdata_Depth);
					$finish;
				end
			end
		end
	end



	always @ din real_din = unsigned_fixedToFloat(din, 1, WL-1);

	always @ dout real_Xilinx_result = unsigned_fixedToFloat(dout, 1, WL-1);
	always @ Simu_Result_Matlab[count] real_MATLAB_reuslt = unsigned_fixedToFloat(Simu_Result_Matlab[count], 1, WL-1);
	
endmodule