data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v
 line:71: before: "$"
1: b'%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:28: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tests/registro/test5.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:29: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, test5);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:44: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #0 modo = 2\'b10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #0 dir = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #0 s_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #0 d = 4\'b0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #2 modo = 2\'b10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #10 d = 4\'b0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #2 enb = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 4\'b1111;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #10 enb = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #2 d = 4\'b1111;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #10 d = 4\'bxxxx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #10 d = 4\'b0x0x;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #4 d = 4\'b101x;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #4 d = 4\'bx10x;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea2/pruebas/registro/test5.v:76: Unsupported or unknown PLI call: $monitor\n    $monitor(\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test5;
  initial begin
    $display("Test Bench 5 registro");
    $display("Prueba la funcionalidad de carga en paralelo");
    $display("********************************************");
    $dumpfile("tests/registro/test5.vcd");
    $dumpvars(0, test5);
  end
  reg clk  = 0;
  reg enb  = 1;
  reg dir  = 1;
  reg s_in = 0;

  reg [1:0] modo  = 2'b01;
  reg [3:0] d     = 4'b0110;

  wire [3:0] q;
  wire s_out;

  registro registro1(clk, enb, dir, s_in, modo, d, q, s_out);

  always #1 clk = ~clk;

  initial begin


    #0 modo = 2'b10;
    #0 dir = 1;
    #0 s_in = 0;
    #0 d = 4'b0000;
    #1;


    #2 modo = 2'b10;


    #10 d = 4'b0000;
    #2 enb = 0;
    #2 d = 4'b1111;
    #10 enb = 1;
    #2 d = 4'b1111;
    #10 d = 4'bxxxx;


    #10 d = 4'b0x0x;
    #4 d = 4'b101x;
    #4 d = 4'bx10x;

    #10 $finish;
  end

  initial begin
    $display("\t\ttiempo\tdir\ts_in\tmodo\td\tq\ts_out\n");
    $monitor(
      "%d", $time,
      "\t%b", dir,
      "\t%b", s_in,
      "\t%2b", modo,
      "\t%4b", d,
      "\t%4b", q,
      "\t%b", s_out);
  end
endmodule
module test5;

  initial begin
    $display("Test Bench 5 registro");
    $display("Prueba la funcionalidad de carga en paralelo");
    $display("********************************************");
    $dumpfile("tests/registro/test5.vcd");
    $dumpvars(0, test5);
  end
  reg clk  = 0;
  reg enb  = 1;
  reg dir  = 1;
  reg s_in = 0;

  reg [1:0] modo  = 2'b01;
  reg [3:0] d     = 4'b0110;

  wire [3:0] q;
  wire s_out;

  registro registro1(clk, enb, dir, s_in, modo, d, q, s_out);

  always #1 clk = ~clk;

  initial begin


    #0 modo = 2'b10;
    #0 dir = 1;
    #0 s_in = 0;
    #0 d = 4'b0000;
    #1;


    #2 modo = 2'b10;


    #10 d = 4'b0000;
    #2 enb = 0;
    #2 d = 4'b1111;
    #10 enb = 1;
    #2 d = 4'b1111;
    #10 d = 4'bxxxx;


    #10 d = 4'b0x0x;
    #4 d = 4'b101x;
    #4 d = 4'bx10x;

    #10 $finish;
  end

  initial begin
    $display("\t\ttiempo\tdir\ts_in\tmodo\td\tq\ts_out\n");
    $monitor(
      "%d", $time,
      "\t%b", dir,
      "\t%b", s_in,
      "\t%2b", modo,
      "\t%4b", d,
      "\t%4b", q,
      "\t%b", s_out);
  end
endmodule