data/full_repos/permissive/10136357/hardware/src/multiplier.v
1: b'%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n             consts.vh\n             consts.vh.v\n             consts.vh.sv\n             obj_dir/consts.vh\n             obj_dir/consts.vh.v\n             obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:41: Define or directive not defined: \'`MUL_LO\'\n   `MUL_LO, `MUL_HI:\n   ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:41: syntax error, unexpected \',\', expecting endcase\n   `MUL_LO, `MUL_HI:\n          ^\n%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:41: Define or directive not defined: \'`MUL_HI\'\n   `MUL_LO, `MUL_HI:\n            ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:43: Define or directive not defined: \'`MUL_HI_SU\'\n   `MUL_HI_SU:\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:45: Define or directive not defined: \'`MUL_HI_UU\'\n   `MUL_HI_UU:\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/multiplier.v:52: Define or directive not defined: \'`MUL_LO\'\n assign multiplier_result = (mul_sel == `MUL_LO) ? result[31:0] : result[63:0];\n                                        ^~~~~~~\n%Error: Cannot continue\n'
module multiplier (
	output [31:0] multiplier_result,
	input [31:0] op1,
	input [31:0] op2,
	input [1:0] mul_sel
);
	wire [63:0] sext_op1 = op1[31] ? {32'hFFFFFFFF, op1} : {32'h0, op1};
	wire [63:0] sext_op2 = op2[31] ? {32'hFFFFFFFF, op2} : {32'h0, op2};

	reg [63:0] result;

	always @ (*) begin
		case (mul_sel)
			`MUL_LO, `MUL_HI:
				result = $signed(sext_op1) * $signed(sext_op2);
			`MUL_HI_SU:
				result = $signed(sext_op1) * {32'h0, op2};
			`MUL_HI_UU:
				result = {32'h0, op1} * {32'h0, op2};
			default:
				result = 0;
		endcase
	end

	assign multiplier_result = (mul_sel == `MUL_LO) ? result[31:0] : result[63:0];
endmodule
module multiplier (
	output [31:0] multiplier_result,
	input [31:0] op1,
	input [31:0] op2,
	input [1:0] mul_sel
);

	wire [63:0] sext_op1 = op1[31] ? {32'hFFFFFFFF, op1} : {32'h0, op1};
	wire [63:0] sext_op2 = op2[31] ? {32'hFFFFFFFF, op2} : {32'h0, op2};

	reg [63:0] result;

	always @ (*) begin
		case (mul_sel)
			`MUL_LO, `MUL_HI:
				result = $signed(sext_op1) * $signed(sext_op2);
			`MUL_HI_SU:
				result = $signed(sext_op1) * {32'h0, op2};
			`MUL_HI_UU:
				result = {32'h0, op1} * {32'h0, op2};
			default:
				result = 0;
		endcase
	end

	assign multiplier_result = (mul_sel == `MUL_LO) ? result[31:0] : result[63:0];
endmodule