data/full_repos/permissive/143278/ivltests/pr872.v
 line:25: before: "="
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr872.v:12: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (test !== 0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire test;

   foo u1(test);

   initial begin
      #1 if (test !== 0) begin
	 $display("FAILED -- foo.bar == %b (%b)", test, u1.bar);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   wire test;

   foo u1(test);

   initial begin
      #1 if (test !== 0) begin
	 $display("FAILED -- foo.bar == %b (%b)", test, u1.bar);
	 $finish;
      end

      $display("PASSED");
   end

endmodule