data/full_repos/permissive/143278/ivltests/pr2832234.v
 line:21: before: "("
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr2832234.v:21: syntax error, unexpected (-for-strength, expecting \'(\'\n  pullup (weak1) (y2);\n          ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr2832234.v:23: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 q1(y1, y2, ctl);\n          ^~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2832234.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2832234.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2832234.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2832234.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2832234.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2832234.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n'
module top;
  reg pass;
  reg ctl, ctl2, in, in2;
  wire y1, y2, ctlb, y2b;

  assign y1 = in;
  pullup (weak1) (y2);

  tranif0 q1(y1, y2, ctl);

  assign y2 = ctl2 ? in2 : 1'bz;

  not q2(ctlb, ctl);
  not q3(y2b, y2);

  initial begin
    pass = 1'b1;

    ctl = 1'b0;
    ctl2 = 1'b0;
    in = 1'b1;
    #1;
    if (ctlb !== 1'b1) begin
      $display("Failed ctlb with ctl = 0, expected 1'b1, got %b", ctlb);
      pass = 1'b0;
    end
    if (y2 !== 1'b1) begin
      $display("Failed tran with ctl = 0, in = 1, expected 1'b1, got %b", y2);
      pass = 1'b0;
    end
    if (y2b !== 1'b0) begin
      $display("Failed y2b with ctl = 0, in = 1, expected 1'b0, got %b", y2b);
      pass = 1'b0;
    end
    in = 1'b0;
    #1;
    if (y2 !== 1'b0) begin
      $display("Failed tran with ctl = 0, in = 0, expected 1'b0, got %b", y2);
      pass = 1'b0;
    end
    if (y2b !== 1'b1) begin
      $display("Failed y2b with ctl = 0, in = 0, expected 1'b1, got %b", y2b);
      pass = 1'b0;
    end


    ctl = 1'b1;
    #1;
    if (ctlb !== 1'b0) begin
      $display("Failed ctlb with ctl = 1, expected 1'b0, got %b", ctlb);
      pass = 1'b0;
    end
    if (y2 !== 1'b1) begin
      $display("Failed tran with ctl = 1, expected 1'b1, got %b", y2);
      pass = 1'b0;
    end
    if (y2b !== 1'b0) begin
      $display("Failed y2b with ctl = 1, expected 1'b0, got %b", y2b);
      pass = 1'b0;
    end


    ctl2 = 1'b1;
    in2 = 1'b1;
    #1;
    if (y2 !== 1'b1) begin
      $display("Failed tran with ctl2 = 1, in2 = 1, expected 1'b1, got %b", y2);
      pass = 1'b0;
    end
    if (y2b !== 1'b0) begin
      $display("Failed y2b with ctl2 = 1, in2 = 1, expected 1'b0, got %b", y2b);
      pass = 1'b0;
    end
    in2 = 1'b0;
    #1;
    if (y2 !== 1'b0) begin
      $display("Failed tran with ctl2 = 1, in2 = 0, expected 1'b0, got %b", y2);
      pass = 1'b0;
    end
    if (y2b !== 1'b1) begin
      $display("Failed y2b with ctl2 = 1, in2 = 0, expected 1'b1, got %b", y2b);
      pass = 1'b0;
    end


    ctl2 = 1'b0;
    #1;
    if (y2 !== 1'b1) begin
      $display("Failed tran with ctl2 = 0, expected 1'b1, got %b", y2);
      pass = 1'b0;
    end
    if (y2b !== 1'b0) begin
      $display("Failed y2b with ctl2 = 0, expected 1'b0, got %b", y2b);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;
  reg ctl, ctl2, in, in2;
  wire y1, y2, ctlb, y2b;

  assign y1 = in;
  pullup (weak1) (y2);

  tranif0 q1(y1, y2, ctl);

  assign y2 = ctl2 ? in2 : 1'bz;

  not q2(ctlb, ctl);
  not q3(y2b, y2);

  initial begin
    pass = 1'b1;

    ctl = 1'b0;
    ctl2 = 1'b0;
    in = 1'b1;
    #1;
    if (ctlb !== 1'b1) begin
      $display("Failed ctlb with ctl = 0, expected 1'b1, got %b", ctlb);
      pass = 1'b0;
    end
    if (y2 !== 1'b1) begin
      $display("Failed tran with ctl = 0, in = 1, expected 1'b1, got %b", y2);
      pass = 1'b0;
    end
    if (y2b !== 1'b0) begin
      $display("Failed y2b with ctl = 0, in = 1, expected 1'b0, got %b", y2b);
      pass = 1'b0;
    end
    in = 1'b0;
    #1;
    if (y2 !== 1'b0) begin
      $display("Failed tran with ctl = 0, in = 0, expected 1'b0, got %b", y2);
      pass = 1'b0;
    end
    if (y2b !== 1'b1) begin
      $display("Failed y2b with ctl = 0, in = 0, expected 1'b1, got %b", y2b);
      pass = 1'b0;
    end


    ctl = 1'b1;
    #1;
    if (ctlb !== 1'b0) begin
      $display("Failed ctlb with ctl = 1, expected 1'b0, got %b", ctlb);
      pass = 1'b0;
    end
    if (y2 !== 1'b1) begin
      $display("Failed tran with ctl = 1, expected 1'b1, got %b", y2);
      pass = 1'b0;
    end
    if (y2b !== 1'b0) begin
      $display("Failed y2b with ctl = 1, expected 1'b0, got %b", y2b);
      pass = 1'b0;
    end


    ctl2 = 1'b1;
    in2 = 1'b1;
    #1;
    if (y2 !== 1'b1) begin
      $display("Failed tran with ctl2 = 1, in2 = 1, expected 1'b1, got %b", y2);
      pass = 1'b0;
    end
    if (y2b !== 1'b0) begin
      $display("Failed y2b with ctl2 = 1, in2 = 1, expected 1'b0, got %b", y2b);
      pass = 1'b0;
    end
    in2 = 1'b0;
    #1;
    if (y2 !== 1'b0) begin
      $display("Failed tran with ctl2 = 1, in2 = 0, expected 1'b0, got %b", y2);
      pass = 1'b0;
    end
    if (y2b !== 1'b1) begin
      $display("Failed y2b with ctl2 = 1, in2 = 0, expected 1'b1, got %b", y2b);
      pass = 1'b0;
    end


    ctl2 = 1'b0;
    #1;
    if (y2 !== 1'b1) begin
      $display("Failed tran with ctl2 = 0, expected 1'b1, got %b", y2);
      pass = 1'b0;
    end
    if (y2b !== 1'b0) begin
      $display("Failed y2b with ctl2 = 0, expected 1'b0, got %b", y2b);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule