data/full_repos/permissive/143278/ivltests/const.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/const.v:45: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/const.v:49: Unsupported: Ignoring delay on this delayed statement.\n       #1\n       ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/const.v:46: Operator NEQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                     : ... In instance main\n   for (exp_dat = 0; exp_dat != 4\'hf; exp_dat = exp_dat + 1)\n                             ^~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main(
clk,
dat
);

parameter dat_width =32;
input clk;
output [dat_width-1:0] dat;
reg [dat_width-1:0] dat;
reg [32-1:0] exp_dat;
reg error;

initial
  begin
    exp_dat = 0;
    dat = 0;
  end

initial
  begin
   dat = #1 'h00010203;
   exp_dat = #1 'h0010203;
   error = 0;
   #10;
   for (exp_dat = 0; exp_dat != 4'hf; exp_dat = exp_dat + 1)
     begin
       dat = exp_dat;
       #1
       if(dat !== exp_dat)
         begin
           $display("ERROR: dat = %h, exp_dat = %h",dat,exp_dat);
	   error = 1;
         end
       else
         $display("Okay: dat = %h, exp_dat = %h",dat,exp_dat);
     end
    if(error === 0)
       $display("PASSED");
    else
       $display("FAILED");
   end
endmodule
module main(
clk,
dat
);


parameter dat_width =32;
input clk;
output [dat_width-1:0] dat;
reg [dat_width-1:0] dat;
reg [32-1:0] exp_dat;
reg error;

initial
  begin
    exp_dat = 0;
    dat = 0;
  end

initial
  begin
   dat = #1 'h00010203;
   exp_dat = #1 'h0010203;
   error = 0;
   #10;
   for (exp_dat = 0; exp_dat != 4'hf; exp_dat = exp_dat + 1)
     begin
       dat = exp_dat;
       #1
       if(dat !== exp_dat)
         begin
           $display("ERROR: dat = %h, exp_dat = %h",dat,exp_dat);
	   error = 1;
         end
       else
         $display("Okay: dat = %h, exp_dat = %h",dat,exp_dat);
     end
    if(error === 0)
       $display("PASSED");
    else
       $display("FAILED");
   end
endmodule