data/full_repos/permissive/13953309/NW_fifo.v
 line:103: before: "typedef"
1: b"%Error: data/full_repos/permissive/13953309/NW_fifo.v:110: syntax error, unexpected IDENTIFIER, expecting '.' or ';'\ntypedef flit_t fifo_elements_t;\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:134: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:135: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t data_out, second_data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:275: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:276: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t data_out, second_data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:513: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:514: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:515: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t second_data_out;\n                             ^~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module fifo_buffer (push, pop, data_in, data_out, second_data_out, clk, rst_n);


   parameter init_fifo_contents = 0;



   parameter int unsigned size = 4;

   parameter output_reg = 0;

   parameter low_power = 0;

   parameter always_write = 0;

   input     push, pop;
   input     fifo_elements_t data_in;
   output    fifo_elements_t data_out;
   output    fifo_elements_t second_data_out;
   input     clk, rst_n;


   logic unsigned [size-1:0] rd_ptr, wt_ptr;
   
   fifo_elements_t fifo_mem[0:size-1];

   logic select_bypass;
   
   integer i,j;

   always@(posedge clk) begin

      assert (size>=2) else $fatal();

      if (!rst_n) begin



	 if ((init_fifo_contents==2)&&(output_reg==0)) begin

	    fifo_mem[0]<=1;
	    rd_ptr<={{size-1{1'b0}},1'b1};
            wt_ptr <= {{size-2{1'b0}},2'b10};
	 end else if (init_fifo_contents==1) begin

	    for (i=0; i<size-1; i=i+1) begin
	       fifo_mem[i]<=1'b1<<(i+output_reg);
	    end
	    rd_ptr<={{size-1{1'b0}},1'b1};
            wt_ptr<={1'b1,{size-1{1'b0}}}; 
	 end else begin



	    rd_ptr<={{size-1{1'b0}},1'b1};
            wt_ptr<={{size-1{1'b0}},1'b1};
	 end
	 
      end else begin

	 if (push || always_write) begin

	    for (i=0; i<size; i++) begin
	       if (wt_ptr[i]==1'b1) begin
		  fifo_mem[i] <= data_in;
	       end
	    end
	 end

	 if (push) begin

	    wt_ptr <= {wt_ptr[size-2:0], wt_ptr[size-1]};
	 end
	 
	 if (pop) begin

            rd_ptr <= {rd_ptr[size-2:0], rd_ptr[size-1]};	    
	 end
	 
      end
   end


   always_comb begin




      data_out = 'x;  
      second_data_out ='x;
      
      for (j=0; j<size; j++) begin
	 if (rd_ptr[j]==1'b1) begin


	    data_out = fifo_mem[j];
	    

	    if ((j+1)==size) begin
	       second_data_out = fifo_mem[0];
	    end else begin
	       second_data_out = fifo_mem[j+1];
	    end

	 end
      end 

   end

endmodule
module fifo_buffer (push, pop, data_in, data_out, second_data_out, clk, rst_n);



   parameter init_fifo_contents = 0;



   parameter int unsigned size = 4;

   parameter output_reg = 0;

   parameter low_power = 0;

   parameter always_write = 0;

   input     push, pop;
   input     fifo_elements_t data_in;
   output    fifo_elements_t data_out;
   output    fifo_elements_t second_data_out;
   input     clk, rst_n;


   logic unsigned [size-1:0] rd_ptr, wt_ptr;
   
   fifo_elements_t fifo_mem[0:size-1];

   logic select_bypass;
   
   integer i,j;

   always@(posedge clk) begin

      assert (size>=2) else $fatal();

      if (!rst_n) begin



	 if ((init_fifo_contents==2)&&(output_reg==0)) begin

	    fifo_mem[0]<=1;
	    rd_ptr<={{size-1{1'b0}},1'b1};
            wt_ptr <= {{size-2{1'b0}},2'b10};
	 end else if (init_fifo_contents==1) begin

	    for (i=0; i<size-1; i=i+1) begin
	       fifo_mem[i]<=1'b1<<(i+output_reg);
	    end
	    rd_ptr<={{size-1{1'b0}},1'b1};
            wt_ptr<={1'b1,{size-1{1'b0}}}; 
	 end else begin



	    rd_ptr<={{size-1{1'b0}},1'b1};
            wt_ptr<={{size-1{1'b0}},1'b1};
	 end
	 
      end else begin

	 if (push || always_write) begin

	    for (i=0; i<size; i++) begin
	       if (wt_ptr[i]==1'b1) begin
		  fifo_mem[i] <= data_in;
	       end
	    end
	 end

	 if (push) begin

	    wt_ptr <= {wt_ptr[size-2:0], wt_ptr[size-1]};
	 end
	 
	 if (pop) begin

            rd_ptr <= {rd_ptr[size-2:0], rd_ptr[size-1]};	    
	 end
	 
      end
   end


   always_comb begin




      data_out = 'x;  
      second_data_out ='x;
      
      for (j=0; j<size; j++) begin
	 if (rd_ptr[j]==1'b1) begin


	    data_out = fifo_mem[j];
	    

	    if ((j+1)==size) begin
	       second_data_out = fifo_mem[0];
	    end else begin
	       second_data_out = fifo_mem[j+1];
	    end

	 end
      end 

   end

endmodule