data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v
 line:65: before: "begin"
1: b'%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:27: Define or directive not defined: \'`ADDR_WIDTH\'\n reg [`ADDR_WIDTH-1:0] ra;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:28: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] rq;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:30: Define or directive not defined: \'`ADDR_WIDTH\'\n reg [`ADDR_WIDTH-1:0] wa;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:31: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] wd;\n      ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n initial forever #(PERIOD / 2.0) clk = ~clk;\n                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:38: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile(`VCD"");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:38: Define or directive not defined: \'`VCD\'\n  $dumpfile(`VCD"");\n            ^~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:39: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:47: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] expected;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:50: Define or directive not defined: \'`DATA_WIDTH\'\n  expected <= (a | (a << 20) | 20\'h55000) & {`DATA_WIDTH{1\'b1}};\n                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:67: Define or directive not defined: \'`ADDR_WIDTH\'\n  for (a = 0; a < (1<<`ADDR_WIDTH); a = a + ADDR_INCR) begin\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:67: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  for (a = 0; a < (1<<`ADDR_WIDTH); a = a + ADDR_INCR) begin\n                                 ^\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:67: syntax error, unexpected \')\', expecting \';\'\n  for (a = 0; a < (1<<`ADDR_WIDTH); a = a + ADDR_INCR) begin\n                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n initial #(1) begin\n         ^\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:73: syntax error, unexpected \'@\'\n   @(posedge clk) begin\n   ^\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:79: Define or directive not defined: \'`ADDR_WIDTH\'\n  for (a = 0; a < (1<<`ADDR_WIDTH); a = a + ADDR_INCR) begin\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:79: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  for (a = 0; a < (1<<`ADDR_WIDTH); a = a + ADDR_INCR) begin\n                                 ^\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:87: syntax error, unexpected $display\n     $display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected, a);\n     ^~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:89: syntax error, unexpected $display\n     $display("%d: OK: act=%x exp=%x at %x", $time, rq, expected, a);\n     ^~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:99: Unsupported or unknown PLI call: $finish_and_return\n   $finish_and_return( (error_cnt == 0) ? 0 : -1 );\n   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_sdp/sim/bram_sdp_tb.v:102: Define or directive not defined: \'`TOP\'\n case (`TOP"")\n       ^~~~\n%Error: Cannot continue\n'
module TB;
	localparam PERIOD = 50;
	localparam ADDR_INCR = 1;

	reg clk;
	reg rce;
	reg [`ADDR_WIDTH-1:0] ra;
	wire [`DATA_WIDTH-1:0] rq;
	reg wce;
	reg [`ADDR_WIDTH-1:0] wa;
	reg [`DATA_WIDTH-1:0] wd;

	initial clk = 0;
	initial ra = 0;
	initial rce = 0;
	initial forever #(PERIOD / 2.0) clk = ~clk;
	initial begin
		$dumpfile(`STRINGIFY(`VCD));
		$dumpvars;
	end

	integer a;

	reg done;
	initial done = 1'b0;

	reg [`DATA_WIDTH-1:0] expected;

	always @(posedge clk) begin
		expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH{1'b1}};
	end

	wire error = ((a != 0) && read_test) ? rq !== expected : 0;

	integer error_cnt = 0;
	always @ (posedge clk)
	begin
		if (error)
			error_cnt <= error_cnt + 1'b1;
	end

	reg read_test;
	initial read_test = 0;

	initial #(1) begin

		for (a = 0; a < (1<<`ADDR_WIDTH); a = a + ADDR_INCR) begin
			@(negedge clk) begin
				wa = a;
				wd = a | (a << 20) | 20'h55000;
				wce = 1;
			end
			@(posedge clk) begin
				#(PERIOD/10) wce = 0;
			end
		end

		read_test = 1;
		for (a = 0; a < (1<<`ADDR_WIDTH); a = a + ADDR_INCR) begin
			@(negedge clk) begin
				ra = a;
				rce = 1;
			end
			@(posedge clk) begin
				#(PERIOD/10) rce = 0;
				if ( rq !== expected) begin
					$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected, a);
				end else begin
					$display("%d: OK: act=%x exp=%x at %x", $time, rq, expected, a);
				end
			end
		end
		done = 1'b1;
	end


	always @(posedge clk) begin
		if (done)
			$finish_and_return( (error_cnt == 0) ? 0 : -1 );
	end

	case (`STRINGIFY(`TOP))
		"BRAM_SDP_36x1024": begin
			BRAM_SDP_36x1024 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_32x1024": begin
			BRAM_SDP_32x1024 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_18x2048": begin
			BRAM_SDP_18x2048 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_16x2048": begin
			BRAM_SDP_16x2048 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_9x4096": begin
			BRAM_SDP_9x4096 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_8x4096": begin
			BRAM_SDP_8x4096 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_4x8192": begin
			BRAM_SDP_4x8192 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_2x16384": begin
			BRAM_SDP_2x16384 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_1x32768": begin
			BRAM_SDP_1x32768 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
	endcase
endmodule
module TB;

	localparam PERIOD = 50;
	localparam ADDR_INCR = 1;

	reg clk;
	reg rce;
	reg [`ADDR_WIDTH-1:0] ra;
	wire [`DATA_WIDTH-1:0] rq;
	reg wce;
	reg [`ADDR_WIDTH-1:0] wa;
	reg [`DATA_WIDTH-1:0] wd;

	initial clk = 0;
	initial ra = 0;
	initial rce = 0;
	initial forever #(PERIOD / 2.0) clk = ~clk;
	initial begin
		$dumpfile(`STRINGIFY(`VCD));
		$dumpvars;
	end

	integer a;

	reg done;
	initial done = 1'b0;

	reg [`DATA_WIDTH-1:0] expected;

	always @(posedge clk) begin
		expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH{1'b1}};
	end

	wire error = ((a != 0) && read_test) ? rq !== expected : 0;

	integer error_cnt = 0;
	always @ (posedge clk)
	begin
		if (error)
			error_cnt <= error_cnt + 1'b1;
	end

	reg read_test;
	initial read_test = 0;

	initial #(1) begin

		for (a = 0; a < (1<<`ADDR_WIDTH); a = a + ADDR_INCR) begin
			@(negedge clk) begin
				wa = a;
				wd = a | (a << 20) | 20'h55000;
				wce = 1;
			end
			@(posedge clk) begin
				#(PERIOD/10) wce = 0;
			end
		end

		read_test = 1;
		for (a = 0; a < (1<<`ADDR_WIDTH); a = a + ADDR_INCR) begin
			@(negedge clk) begin
				ra = a;
				rce = 1;
			end
			@(posedge clk) begin
				#(PERIOD/10) rce = 0;
				if ( rq !== expected) begin
					$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected, a);
				end else begin
					$display("%d: OK: act=%x exp=%x at %x", $time, rq, expected, a);
				end
			end
		end
		done = 1'b1;
	end


	always @(posedge clk) begin
		if (done)
			$finish_and_return( (error_cnt == 0) ? 0 : -1 );
	end

	case (`STRINGIFY(`TOP))
		"BRAM_SDP_36x1024": begin
			BRAM_SDP_36x1024 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_32x1024": begin
			BRAM_SDP_32x1024 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_18x2048": begin
			BRAM_SDP_18x2048 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_16x2048": begin
			BRAM_SDP_16x2048 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_9x4096": begin
			BRAM_SDP_9x4096 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_8x4096": begin
			BRAM_SDP_8x4096 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_4x8192": begin
			BRAM_SDP_4x8192 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_2x16384": begin
			BRAM_SDP_2x16384 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
		"BRAM_SDP_1x32768": begin
			BRAM_SDP_1x32768 #() bram (
				.clk(clk),
				.rce(rce),
				.ra(ra),
				.rq(rq),
				.wce(wce),
				.wa(wa),
				.wd(wd)
			);
		end
	endcase
endmodule