data/full_repos/permissive/138961980/powlib_std.v
 line:24: before: "if"
1: b'%Error: data/full_repos/permissive/138961980/powlib_std.v:195: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh.v\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh.sv\n             powlib_std.vh\n             powlib_std.vh.v\n             powlib_std.vh.sv\n             obj_dir/powlib_std.vh\n             obj_dir/powlib_std.vh.v\n             obj_dir/powlib_std.vh.sv\n%Error: data/full_repos/permissive/138961980/powlib_std.v:221: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:252: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:207: Define or directive not defined: \'`POWLIB_DW\'\n            wire [`POWLIB_DW-1:0] d0 = powlib_grayencode(d); \n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:233: Define or directive not defined: \'`POWLIB_DW\'\n            wire [`POWLIB_DW-1:0] d0 = powlib_graydecode(d); \n                  ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module powlib_grayencodeff(d,q,clk,rst,vld);



`include "powlib_std.vh"

  parameter                       W    = 1;
  parameter      [W-1:0]          INIT = 0;
  parameter                       EAR  = 0;
  parameter                       EVLD = 0;
  input     wire [W-1:0]          d;
  input     wire                  vld;
  input     wire                  clk;
  input     wire                  rst;
  output    wire [W-1:0]          q;
  
            wire [`POWLIB_DW-1:0] d0 = powlib_grayencode(d); 
            wire [W-1:0]          d1 = d0[W-1:0];
  
  powlib_flipflop #(.W(W),.INIT(powlib_grayencode(INIT)),.EAR(EAR),.EVLD(EVLD)) ff_inst (
    .d(d1),.q(q),.vld(vld),.clk(clk),.rst(rst));
    
endmodule
module powlib_grayencodeff(d,q,clk,rst,vld);




`include "powlib_std.vh"

  parameter                       W    = 1;
  parameter      [W-1:0]          INIT = 0;
  parameter                       EAR  = 0;
  parameter                       EVLD = 0;
  input     wire [W-1:0]          d;
  input     wire                  vld;
  input     wire                  clk;
  input     wire                  rst;
  output    wire [W-1:0]          q;
  
            wire [`POWLIB_DW-1:0] d0 = powlib_grayencode(d); 
            wire [W-1:0]          d1 = d0[W-1:0];
  
  powlib_flipflop #(.W(W),.INIT(powlib_grayencode(INIT)),.EAR(EAR),.EVLD(EVLD)) ff_inst (
    .d(d1),.q(q),.vld(vld),.clk(clk),.rst(rst));
    
endmodule