data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/fifo/afifo_gray.v
 line:151: before: "="
data/verilator_xmls/1935a166-90dc-4003-8546-e30aae790241.xml
module afifo_gray
  #( parameter WIDTH = 16,
     parameter MSB   = WIDTH-1,
     parameter ABITS = 4,
     parameter ASB   = ABITS-1,
     parameter ASIZE = 1 << ABITS,
     parameter DELAY = 3)
   (
		 input          rd_clk_i,
		 input          wr_clk_i,
		 input          rst_i,


		 input          wr_en_i,
		 input [MSB:0]  wr_data_i,
		 input          rd_en_i,
		 output [MSB:0] rd_data_o,
   

		 output reg     wfull_o  = 1'b0,
		 output reg     rempty_o = 1'b1
	   );





   wire [ABITS:0]   wp_bin_next, wp_gray_next;
   wire [ABITS:0]   rp_bin_next, rp_gray_next;

   reg [ABITS:0]    wp_bin = 0, wp_gray = 0;
   reg [ABITS:0]    rp_bin = 0, rp_gray = 0;

   (* ASYNC_REG = "TRUE" *)
   reg [ABITS:0]    wp_s = 0;
   (* ASYNC_REG = "TRUE" *)
   reg [ABITS:0]    rp_s = 0;

   wire [ABITS:0]   wp_bin_x, rp_bin_x;

   reg              rd_rst   = 1'b1, wr_rst   = 1'b1;
   reg              rd_rst_r = 1'b1, wr_rst_r = 1'b1;





   always @(posedge rd_clk_i or posedge rst_i)
	   if (rst_i)          rd_rst   <= #DELAY 1'b1;
	   else if (!rd_rst_r) rd_rst   <= #DELAY 1'b0;

   always @(posedge rd_clk_i or posedge rst_i)
	   if (rst_i)          rd_rst_r <= #DELAY 1'b1;
	   else                rd_rst_r <= #DELAY 1'b0;

   always @(posedge wr_clk_i or posedge rst_i)
	   if (rst_i)	         wr_rst   <= #DELAY 1'b1;
	   else if (!wr_rst_r) wr_rst   <= #DELAY 1'b0;

   always @(posedge wr_clk_i or posedge rst_i)
	   if (rst_i)	         wr_rst_r <= #DELAY 1'b1;
	   else  		           wr_rst_r <= #DELAY 1'b0;





	 reg [MSB:0]     sram [0:ASIZE-1];
	 
	 assign	rd_data_o	= sram [rp_bin[ASB:0]];
	 
	 always @(posedge wr_clk_i) begin
		  if (wr_en_i && !wr_rst)
			  sram [wp_bin [ASB:0]] <= #DELAY wr_data_i;
	 end

	 



   assign wp_bin_next  = wp_bin + {{ABITS{1'b0}},1'b1};
   assign wp_gray_next = wp_bin_next ^ {1'b0, wp_bin_next[ABITS:1]};

   assign rp_bin_next  = rp_bin + {{ABITS{1'b0}},1'b1};
   assign rp_gray_next = rp_bin_next ^ {1'b0, rp_bin_next[ABITS:1]};

   always @(posedge wr_clk_i)
	   if (wr_rst)	     wp_bin  <= #DELAY {ABITS+1{1'b0}};
	   else if (wr_en_i) wp_bin  <= #DELAY wp_bin_next;

   always @(posedge wr_clk_i)
	   if (wr_rst)	     wp_gray <= #DELAY {ABITS+1{1'b0}};
	   else if (wr_en_i) wp_gray <= #DELAY wp_gray_next;

   always @(posedge rd_clk_i)
	   if (rd_rst)       rp_bin  <= #DELAY {ABITS+1{1'b0}};
	   else if (rd_en_i) rp_bin  <= #DELAY rp_bin_next;

   always @(posedge rd_clk_i)
	   if (rd_rst)       rp_gray <= #DELAY {ABITS+1{1'b0}};
	   else if (rd_en_i) rp_gray <= #DELAY rp_gray_next;





   always @(posedge rd_clk_i)
     wp_s <= #DELAY wp_gray;

   always @(posedge wr_clk_i)
     rp_s <= #DELAY rp_gray;





   assign wp_bin_x = wp_s ^ {1'b0, wp_bin_x[ABITS:1]};
   assign rp_bin_x = rp_s ^ {1'b0, rp_bin_x[ABITS:1]};

   always @(posedge rd_clk_i)
     if (rst_i)
       rempty_o <= #DELAY 1'b1;
     else
       rempty_o <= #DELAY wp_s == rp_gray || rd_en_i && wp_s == rp_gray_next;

   always @(posedge wr_clk_i)
     if (rst_i)
       wfull_o <= #DELAY 1'b0;
     else
       wfull_o <= #DELAY ((wp_bin[ASB:0] == rp_bin_x[ASB:0]) && (wp_bin[ABITS] != rp_bin_x[ABITS])) ||
                  (wr_en_i && (wp_bin_next[ASB:0] == rp_bin_x[ASB:0]) && (wp_bin_next[ABITS] != rp_bin_x[ABITS]));





   always @(posedge wr_clk_i)
	   if (wr_en_i && wfull_o)
		   $display("%m WARNING: Writing while FIFO is FULL (%t)", $time);

   always @(posedge rd_clk_i)
	   if (rd_en_i && rempty_o)
		   $display("%m WARNING: Reading while FIFO is EMPTY (%t)", $time);


endmodule
module afifo_gray
  #( parameter WIDTH = 16,
     parameter MSB   = WIDTH-1,
     parameter ABITS = 4,
     parameter ASB   = ABITS-1,
     parameter ASIZE = 1 << ABITS,
     parameter DELAY = 3)
   (
		 input          rd_clk_i,
		 input          wr_clk_i,
		 input          rst_i,


		 input          wr_en_i,
		 input [MSB:0]  wr_data_i,
		 input          rd_en_i,
		 output [MSB:0] rd_data_o,
   

		 output reg     wfull_o  = 1'b0,
		 output reg     rempty_o = 1'b1
	   );






   wire [ABITS:0]   wp_bin_next, wp_gray_next;
   wire [ABITS:0]   rp_bin_next, rp_gray_next;

   reg [ABITS:0]    wp_bin = 0, wp_gray = 0;
   reg [ABITS:0]    rp_bin = 0, rp_gray = 0;

   (* ASYNC_REG = "TRUE" *)
   reg [ABITS:0]    wp_s = 0;
   (* ASYNC_REG = "TRUE" *)
   reg [ABITS:0]    rp_s = 0;

   wire [ABITS:0]   wp_bin_x, rp_bin_x;

   reg              rd_rst   = 1'b1, wr_rst   = 1'b1;
   reg              rd_rst_r = 1'b1, wr_rst_r = 1'b1;





   always @(posedge rd_clk_i or posedge rst_i)
	   if (rst_i)          rd_rst   <= #DELAY 1'b1;
	   else if (!rd_rst_r) rd_rst   <= #DELAY 1'b0;

   always @(posedge rd_clk_i or posedge rst_i)
	   if (rst_i)          rd_rst_r <= #DELAY 1'b1;
	   else                rd_rst_r <= #DELAY 1'b0;

   always @(posedge wr_clk_i or posedge rst_i)
	   if (rst_i)	         wr_rst   <= #DELAY 1'b1;
	   else if (!wr_rst_r) wr_rst   <= #DELAY 1'b0;

   always @(posedge wr_clk_i or posedge rst_i)
	   if (rst_i)	         wr_rst_r <= #DELAY 1'b1;
	   else  		           wr_rst_r <= #DELAY 1'b0;





	 reg [MSB:0]     sram [0:ASIZE-1];
	 
	 assign	rd_data_o	= sram [rp_bin[ASB:0]];
	 
	 always @(posedge wr_clk_i) begin
		  if (wr_en_i && !wr_rst)
			  sram [wp_bin [ASB:0]] <= #DELAY wr_data_i;
	 end

	 



   assign wp_bin_next  = wp_bin + {{ABITS{1'b0}},1'b1};
   assign wp_gray_next = wp_bin_next ^ {1'b0, wp_bin_next[ABITS:1]};

   assign rp_bin_next  = rp_bin + {{ABITS{1'b0}},1'b1};
   assign rp_gray_next = rp_bin_next ^ {1'b0, rp_bin_next[ABITS:1]};

   always @(posedge wr_clk_i)
	   if (wr_rst)	     wp_bin  <= #DELAY {ABITS+1{1'b0}};
	   else if (wr_en_i) wp_bin  <= #DELAY wp_bin_next;

   always @(posedge wr_clk_i)
	   if (wr_rst)	     wp_gray <= #DELAY {ABITS+1{1'b0}};
	   else if (wr_en_i) wp_gray <= #DELAY wp_gray_next;

   always @(posedge rd_clk_i)
	   if (rd_rst)       rp_bin  <= #DELAY {ABITS+1{1'b0}};
	   else if (rd_en_i) rp_bin  <= #DELAY rp_bin_next;

   always @(posedge rd_clk_i)
	   if (rd_rst)       rp_gray <= #DELAY {ABITS+1{1'b0}};
	   else if (rd_en_i) rp_gray <= #DELAY rp_gray_next;





   always @(posedge rd_clk_i)
     wp_s <= #DELAY wp_gray;

   always @(posedge wr_clk_i)
     rp_s <= #DELAY rp_gray;





   assign wp_bin_x = wp_s ^ {1'b0, wp_bin_x[ABITS:1]};
   assign rp_bin_x = rp_s ^ {1'b0, rp_bin_x[ABITS:1]};

   always @(posedge rd_clk_i)
     if (rst_i)
       rempty_o <= #DELAY 1'b1;
     else
       rempty_o <= #DELAY wp_s == rp_gray || rd_en_i && wp_s == rp_gray_next;

   always @(posedge wr_clk_i)
     if (rst_i)
       wfull_o <= #DELAY 1'b0;
     else
       wfull_o <= #DELAY ((wp_bin[ASB:0] == rp_bin_x[ASB:0]) && (wp_bin[ABITS] != rp_bin_x[ABITS])) ||
                  (wr_en_i && (wp_bin_next[ASB:0] == rp_bin_x[ASB:0]) && (wp_bin_next[ABITS] != rp_bin_x[ABITS]));





   always @(posedge wr_clk_i)
	   if (wr_en_i && wfull_o)
		   $display("%m WARNING: Writing while FIFO is FULL (%t)", $time);

   always @(posedge rd_clk_i)
	   if (rd_en_i && rempty_o)
		   $display("%m WARNING: Reading while FIFO is EMPTY (%t)", $time);


endmodule