data/full_repos/permissive/200650987/project/display/soc_up/rtl/MIRROR_SWAMP/core/reg_file.v
data/verilator_xmls/ae76e18a-264c-407a-8d51-82fd3e27dff5.xml
module reg_file(
	input clk,
	input [4:0] waddr,
	input [4:0] raddr1,
	input [4:0] raddr2,
	input wen,
	input [31:0] wdata,
	output [31:0] rdata1,
	output [31:0] rdata2
);


	reg [31:0] regs [31:1];


	assign rdata1 = (raddr1 == 0 ? 0 : regs[raddr1]);
	assign rdata2 = (raddr2 == 0 ? 0 : regs[raddr2]);


	always @(posedge clk) if (wen) regs[waddr] <= wdata;

endmodule
module reg_file(
	input clk,
	input [4:0] waddr,
	input [4:0] raddr1,
	input [4:0] raddr2,
	input wen,
	input [31:0] wdata,
	output [31:0] rdata1,
	output [31:0] rdata2
);



	reg [31:0] regs [31:1];


	assign rdata1 = (raddr1 == 0 ? 0 : regs[raddr1]);
	assign rdata2 = (raddr2 == 0 ? 0 : regs[raddr2]);


	always @(posedge clk) if (wen) regs[waddr] <= wdata;

endmodule