data/full_repos/permissive/102515926/Modules/CIRCUIT6.v
1: b'%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:21: Cannot find file containing module: \'ADD\'\n    ADD #(16) add1(a, b, t1);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.v\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.sv\n             ADD\n             ADD.v\n             ADD.sv\n             obj_dir/ADD\n             obj_dir/ADD.v\n             obj_dir/ADD.sv\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:22: Cannot find file containing module: \'ADD\'\n    ADD #(16) add2(r1, c, t2);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:23: Cannot find file containing module: \'ADD\'\n    ADD #(16) add3(r2, d, t3);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:24: Cannot find file containing module: \'ADD\'\n    ADD #(16) add4(r3, e, t4);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:25: Cannot find file containing module: \'ADD\'\n    ADD #(16) add5(r4, f, t5);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:26: Cannot find file containing module: \'ADD\'\n    ADD #(16) add6(r5, g, t6);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:27: Cannot find file containing module: \'ADD\'\n    ADD #(16) add7(r6, h, t7);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:29: Cannot find file containing module: \'DIV\'\n    DIV #(16) div1(r7, num, avgwire);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:30: Cannot find file containing module: \'REG\'\n    REG #(16) reg8(avgwire, Clk, Rst, avg);\n    ^~~\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:33: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t1\' generates 32 bits.\n                                                                          : ... In instance CIRCUIT6\n        r1 <= t1;\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:34: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t2\' generates 32 bits.\n                                                                          : ... In instance CIRCUIT6\n        r2 <= t2;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:35: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t3\' generates 32 bits.\n                                                                          : ... In instance CIRCUIT6\n        r3 <= t3;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:36: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t4\' generates 32 bits.\n                                                                          : ... In instance CIRCUIT6\n        r4 <= t4;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:37: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t5\' generates 32 bits.\n                                                                          : ... In instance CIRCUIT6\n        r5 <= t5;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:38: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t6\' generates 32 bits.\n                                                                          : ... In instance CIRCUIT6\n        r6 <= t6;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/102515926/Modules/CIRCUIT6.v:39: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'t7\' generates 32 bits.\n                                                                          : ... In instance CIRCUIT6\n        r7 <= t7;\n           ^~\n%Error: Exiting due to 9 error(s), 7 warning(s)\n'
module CIRCUIT6(a, b, c, d, e, f, g, h, num, Clk, Rst, avg);
    
    input Clk, Rst;
    input [15:0] a, b, c, d, e, f, g, h, num;

    output [15:0] avg;

    reg [15:0] r1, r2, r3, r4, r5, r6, r7;

    wire [15:0] avgwire;
    wire [31:0] t1, t2, t3, t4, t5, t6, t7;
    
    ADD #(16) add1(a, b, t1);
    ADD #(16) add2(r1, c, t2);
    ADD #(16) add3(r2, d, t3);
    ADD #(16) add4(r3, e, t4);
    ADD #(16) add5(r4, f, t5);
    ADD #(16) add6(r5, g, t6);
    ADD #(16) add7(r6, h, t7);
    
    DIV #(16) div1(r7, num, avgwire);
    REG #(16) reg8(avgwire, Clk, Rst, avg);
    
    always @(r1, r2, r3, r4, r5, r6, r7) begin
        r1 <= t1;
        r2 <= t2;
        r3 <= t3;
        r4 <= t4;
        r5 <= t5;
        r6 <= t6;
        r7 <= t7;
    end

endmodule
module CIRCUIT6(a, b, c, d, e, f, g, h, num, Clk, Rst, avg);

    
    input Clk, Rst;
    input [15:0] a, b, c, d, e, f, g, h, num;

    output [15:0] avg;

    reg [15:0] r1, r2, r3, r4, r5, r6, r7;

    wire [15:0] avgwire;
    wire [31:0] t1, t2, t3, t4, t5, t6, t7;
    
    ADD #(16) add1(a, b, t1);
    ADD #(16) add2(r1, c, t2);
    ADD #(16) add3(r2, d, t3);
    ADD #(16) add4(r3, e, t4);
    ADD #(16) add5(r4, f, t5);
    ADD #(16) add6(r5, g, t6);
    ADD #(16) add7(r6, h, t7);
    
    DIV #(16) div1(r7, num, avgwire);
    REG #(16) reg8(avgwire, Clk, Rst, avg);
    
    always @(r1, r2, r3, r4, r5, r6, r7) begin
        r1 <= t1;
        r2 <= t2;
        r3 <= t3;
        r4 <= t4;
        r5 <= t5;
        r6 <= t6;
        r7 <= t7;
    end

endmodule