data/full_repos/permissive/163115503/numbers/top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/163115503/numbers/top.v:4: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/163115503/numbers/top.v:10: syntax error, unexpected always\n    always @(posedge CLK) begin\n    ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module top(
    input CLK,
    output LED,
);

    reg [7:0] eightbit;
    reg [15:0] sixteenbit;
    reg led_state;

    always @(posedge CLK) begin
        eightbit <= eightbit + 1;

        if (eightbit == 255) begin
            led_state = 1;
        end
    end

    assign LED = led_state;
endmodule
module top(
    input CLK,
    output LED,
);


    reg [7:0] eightbit;
    reg [15:0] sixteenbit;
    reg led_state;

    always @(posedge CLK) begin
        eightbit <= eightbit + 1;

        if (eightbit == 255) begin
            led_state = 1;
        end
    end

    assign LED = led_state;
endmodule