data/full_repos/permissive/200893858/Adders/RippleCarryAdders/HalfAdder_tb.v
1: b'%Error: data/full_repos/permissive/200893858/Adders/RippleCarryAdders/HalfAdder_tb.v:1: Cannot find include file: HalfAdder.v\n`include "HalfAdder.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200893858/Adders/RippleCarryAdders,data/full_repos/permissive/200893858/HalfAdder.v\n             data/full_repos/permissive/200893858/Adders/RippleCarryAdders,data/full_repos/permissive/200893858/HalfAdder.v.v\n             data/full_repos/permissive/200893858/Adders/RippleCarryAdders,data/full_repos/permissive/200893858/HalfAdder.v.sv\n             HalfAdder.v\n             HalfAdder.v.v\n             HalfAdder.v.sv\n             obj_dir/HalfAdder.v\n             obj_dir/HalfAdder.v.v\n             obj_dir/HalfAdder.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/200893858/Adders/RippleCarryAdders/HalfAdder_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n #10 b=0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200893858/Adders/RippleCarryAdders/HalfAdder_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10 a=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/200893858/Adders/RippleCarryAdders/HalfAdder_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #10 b=1;\n ^\n%Error: data/full_repos/permissive/200893858/Adders/RippleCarryAdders/HalfAdder_tb.v:20: Unsupported or unknown PLI call: $monitor\n $monitor($time, "a = %b, b = %b, Sum = %b, ca = %b",a,b,sum, ca);\n ^~~~~~~~\n%Error: data/full_repos/permissive/200893858/Adders/RippleCarryAdders/HalfAdder_tb.v:21: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("HalfAdder.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/200893858/Adders/RippleCarryAdders/HalfAdder_tb.v:22: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n'
module top;

reg a, b;
wire sum, ca;

	HalfAdder HA_0(a,b,sum,ca);

initial
begin
	a=0;
	#10 b=0;
	#10 a=1;
	#10 b=1;
end

initial
begin
	$monitor($time, "a = %b, b = %b, Sum = %b, ca = %b",a,b,sum, ca);
	$dumpfile("HalfAdder.vcd");
	$dumpvars;
end

endmodule
module top;


reg a, b;
wire sum, ca;

	HalfAdder HA_0(a,b,sum,ca);

initial
begin
	a=0;
	#10 b=0;
	#10 a=1;
	#10 b=1;
end

initial
begin
	$monitor($time, "a = %b, b = %b, Sum = %b, ca = %b",a,b,sum, ca);
	$dumpfile("HalfAdder.vcd");
	$dumpvars;
end

endmodule