data/full_repos/permissive/115035459/verilog/src/mza-test027.pll_509divider.althea.revA.v
1: b"%Error: data/full_repos/permissive/115035459/verilog/src/mza-test027.pll_509divider.althea.revA.v:40: Cannot find file containing module: 'pll'\n pll pll_instance (.CLK_IN1(clock509), .CLK_OUT1(clock127), .RESET(reset), .LOCKED(led_0));\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/pll\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/pll.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test027.pll_509divider.althea.revA.v:42: Cannot find file containing module: 'ODDR2'\n ODDR2 doughnut (.C0(clock127), .C1(~clock127), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test027.pll_509divider.althea.revA.v:43: Cannot find file containing module: 'OBUFDS'\n OBUFDS supercool (.I(clock127oddr), .O(clock_p), .OB(clock_n));\n ^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module mza_test027_pll_509divider_althea (
	output clock_p,
	output clock_n,
	input lemo,
	output led_0,
	output led_1,
	output led_2,
	output led_3,
	output led_4,
	output led_5,
	output led_6,
	output led_7
);
	wire clock509;
	assign clock509 = lemo;





	reg reset = 1;
	reg [12:0] reset_counter = 0;
	always @(posedge clock509) begin
		if (reset) begin
			if (reset_counter[10]) begin
				reset <= 0;
			end
		end
		reset_counter <= reset_counter + 1;
	end
	wire clock127;
	pll pll_instance (.CLK_IN1(clock509), .CLK_OUT1(clock127), .RESET(reset), .LOCKED(led_0));
	wire clock127oddr;
	ODDR2 doughnut (.C0(clock127), .C1(~clock127), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr));
	OBUFDS supercool (.I(clock127oddr), .O(clock_p), .OB(clock_n));
	assign led_7 = reset;
	assign led_6 = 0;
	assign led_5 = 0;
	assign led_4 = 0;
	assign led_3 = 0;
	assign led_2 = 0;
	assign led_1 = 0;
endmodule
module mza_test027_pll_509divider_althea (
	output clock_p,
	output clock_n,
	input lemo,
	output led_0,
	output led_1,
	output led_2,
	output led_3,
	output led_4,
	output led_5,
	output led_6,
	output led_7
);

	wire clock509;
	assign clock509 = lemo;





	reg reset = 1;
	reg [12:0] reset_counter = 0;
	always @(posedge clock509) begin
		if (reset) begin
			if (reset_counter[10]) begin
				reset <= 0;
			end
		end
		reset_counter <= reset_counter + 1;
	end
	wire clock127;
	pll pll_instance (.CLK_IN1(clock509), .CLK_OUT1(clock127), .RESET(reset), .LOCKED(led_0));
	wire clock127oddr;
	ODDR2 doughnut (.C0(clock127), .C1(~clock127), .CE(1'b1), .D0(1'b0), .D1(1'b1), .R(1'b0), .S(1'b0), .Q(clock127oddr));
	OBUFDS supercool (.I(clock127oddr), .O(clock_p), .OB(clock_n));
	assign led_7 = reset;
	assign led_6 = 0;
	assign led_5 = 0;
	assign led_4 = 0;
	assign led_3 = 0;
	assign led_2 = 0;
	assign led_1 = 0;
endmodule