data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/dcfifo/gray_dec_1p.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/74231296-fa65-49fc-b638-91731c401098.xml
module gray_dec_1p
#(
parameter	WIDTH = 6
)
(
input		wire					clock,
input		wire	[WIDTH-1:0]		src,
output		reg		[WIDTH-1:0]		dst
);


integer	p;
reg		[WIDTH-1:0]	dst_x;
always @(*)
begin
	dst_x[WIDTH-1] = src[WIDTH-1];
	for(p=WIDTH-2; p>=0; p=p-1)
	begin
		dst_x[p] = src[p]^dst_x[p+1];
	end
end


always @(posedge clock)
	dst <= dst_x;

endmodule
module gray_dec_1p
#(
parameter	WIDTH = 6
)
(
input		wire					clock,
input		wire	[WIDTH-1:0]		src,
output		reg		[WIDTH-1:0]		dst
);



integer	p;
reg		[WIDTH-1:0]	dst_x;
always @(*)
begin
	dst_x[WIDTH-1] = src[WIDTH-1];
	for(p=WIDTH-2; p>=0; p=p-1)
	begin
		dst_x[p] = src[p]^dst_x[p+1];
	end
end


always @(posedge clock)
	dst <= dst_x;

endmodule