data/full_repos/permissive/202237519/verilog/a/a.v
data/verilator_xmls/7e406b3d-e845-42fc-bab7-dfc1beed86cc.xml
module and_module (a,b,c);

input a,b;
output c;

assign c = a+b;

endmodule
module and_module (a,b,c);


input a,b;
output c;

assign c = a+b;

endmodule