data/full_repos/permissive/113002755/verilog/RNG/lfsr_4.v
data/verilator_xmls/0a1f69af-570a-4c8c-ad28-15a6b143f874.xml
module lfsr_4(next_bit, state, seed, clk, rst);
	output next_bit; 
	output [3:0] state;
	reg [3:0] state;
	input [3:0] seed;
	input clk, rst;
	
	wire linear_feedback;


	assign linear_feedback =  state[3] ^ state[2];
	assign next_bit = linear_feedback;
	
	always @(posedge clk or negedge rst)
	if (!rst) 
	begin
	  state <= seed ;
	end 
	else
	begin
	 state <= {state[2],
				state[1],
				state[0],
				linear_feedback};
	 end 
 
 endmodule
module lfsr_4(next_bit, state, seed, clk, rst);

	output next_bit; 
	output [3:0] state;
	reg [3:0] state;
	input [3:0] seed;
	input clk, rst;
	
	wire linear_feedback;


	assign linear_feedback =  state[3] ^ state[2];
	assign next_bit = linear_feedback;
	
	always @(posedge clk or negedge rst)
	if (!rst) 
	begin
	  state <= seed ;
	end 
	else
	begin
	 state <= {state[2],
				state[1],
				state[0],
				linear_feedback};
	 end 
 
 endmodule