data/full_repos/permissive/155656868/src/control_unit.v
None: at end of input
data/verilator_xmls/822377cf-af00-45ef-b79a-e21d445f3579.xml
module control_unit #(parameter OPCODE=3)
                     (input [OPCODE-1:0] opcode,
                      output ld, st, beq, j, alu_en,
                      output [OPCODE-1:0] alu_op);


    parameter ADD = 3'b000;
    parameter SUB = 3'b001;
    parameter AND = 3'b011;
    parameter OR  = 3'b010;
    parameter LD  = 3'b111;
    parameter ST  = 3'b101;
    parameter BEQ = 3'b110;
    parameter J   = 3'b100;


    assign alu_op = opcode;


    reg [4:0] control_sig;


    always @(opcode) begin
        case (opcode)
            ADD:     control_sig <= 5'b00001;
            SUB:     control_sig <= 5'b00001;
            AND:     control_sig <= 5'b00001;
            OR:      control_sig <= 5'b00001;
            LD:      control_sig <= 5'b10000;
            ST:      control_sig <= 5'b01000;
            BEQ:     control_sig <= 5'b00100;
            J:       control_sig <= 5'b00010;
            default: control_sig <= 5'b00000;
        endcase
    end

    assign ld      = control_sig[4];
    assign st      = control_sig[3];
    assign beq     = control_sig[2];
    assign j       = control_sig[1];
    assign alu_en  = control_sig[0];

endmodule
module control_unit #(parameter OPCODE=3)
                     (input [OPCODE-1:0] opcode,
                      output ld, st, beq, j, alu_en,
                      output [OPCODE-1:0] alu_op);



    parameter ADD = 3'b000;
    parameter SUB = 3'b001;
    parameter AND = 3'b011;
    parameter OR  = 3'b010;
    parameter LD  = 3'b111;
    parameter ST  = 3'b101;
    parameter BEQ = 3'b110;
    parameter J   = 3'b100;


    assign alu_op = opcode;


    reg [4:0] control_sig;


    always @(opcode) begin
        case (opcode)
            ADD:     control_sig <= 5'b00001;
            SUB:     control_sig <= 5'b00001;
            AND:     control_sig <= 5'b00001;
            OR:      control_sig <= 5'b00001;
            LD:      control_sig <= 5'b10000;
            ST:      control_sig <= 5'b01000;
            BEQ:     control_sig <= 5'b00100;
            J:       control_sig <= 5'b00010;
            default: control_sig <= 5'b00000;
        endcase
    end

    assign ld      = control_sig[4];
    assign st      = control_sig[3];
    assign beq     = control_sig[2];
    assign j       = control_sig[1];
    assign alu_en  = control_sig[0];

endmodule