data/full_repos/permissive/189570969/1180300220-崔涵/1180300220-崔涵-完整工程/project_1.srcs/sources_1/new/yu.v
data/verilator_xmls/3af508f5-25f2-44cb-941a-73febd782ece.xml
module yu(
    input a,
    input d,
    output c
    );
    assign c=a&d;
endmodule
module yu(
    input a,
    input d,
    output c
    );

    assign c=a&d;
endmodule