data/full_repos/permissive/102955443/testrotor.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #(5) i_clock <= !i_clock;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/102955443/testrotor.v:36: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("testrotor.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/102955443/testrotor.v:37: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,testrotor);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testrotor();	
	reg [2:0] rotor_type_3 = 3'b010;
	reg [2:0] rotor_type_2 = 3'b001;

	reg [4:0] rotor_start_3 = 5'b00000;
	reg [4:0] rotor_start_2 = 5'b00000;
	reg [4:0] rotor_start_1 = 5'b00000;

	reg [4:0] ring_position_3 = 5'b00000;
	reg [4:0] ring_position_2 = 5'b00000;
	reg [4:0] ring_position_1 = 5'b00000;
	reg reflector_type = 1'b0;
	
	reg i_clock = 0;
	
	reg reset;
	reg rotate = 0;
	
	wire [4:0] rotor1;
	wire [4:0] rotor2;
	wire [4:0] rotor3;
	
	integer i;
	
	rotor rotorcontrol(.clock(i_clock),.rotor1(rotor1),.rotor2(rotor2),.rotor3(rotor3),
	        .reset(reset),.rotate(rotate),
	        .rotor_type_2(rotor_type_2),.rotor_type_3(rotor_type_3),
		    .rotor_start_1(rotor_start_1),.rotor_start_2(rotor_start_2),.rotor_start_3(rotor_start_3)
			);
	
	always
		#(5) i_clock <= !i_clock;
 
    initial
	begin
		$dumpfile("testrotor.vcd");
		$dumpvars(0,testrotor);
		
		#5
		reset = 1;
		#10
		reset = 0;
		for (i = 0; i < 128; i = i + 1) 		
		begin
		#10
			rotate = 1;
		#10
			rotate = 0;
		#20
			$display("Rotors [%c] [%c] [%c]",rotor1+65,rotor2+65,rotor3+65);
		end


		#10

		$finish;
	end
endmodule
module testrotor();
	
	reg [2:0] rotor_type_3 = 3'b010;
	reg [2:0] rotor_type_2 = 3'b001;

	reg [4:0] rotor_start_3 = 5'b00000;
	reg [4:0] rotor_start_2 = 5'b00000;
	reg [4:0] rotor_start_1 = 5'b00000;

	reg [4:0] ring_position_3 = 5'b00000;
	reg [4:0] ring_position_2 = 5'b00000;
	reg [4:0] ring_position_1 = 5'b00000;
	reg reflector_type = 1'b0;
	
	reg i_clock = 0;
	
	reg reset;
	reg rotate = 0;
	
	wire [4:0] rotor1;
	wire [4:0] rotor2;
	wire [4:0] rotor3;
	
	integer i;
	
	rotor rotorcontrol(.clock(i_clock),.rotor1(rotor1),.rotor2(rotor2),.rotor3(rotor3),
	        .reset(reset),.rotate(rotate),
	        .rotor_type_2(rotor_type_2),.rotor_type_3(rotor_type_3),
		    .rotor_start_1(rotor_start_1),.rotor_start_2(rotor_start_2),.rotor_start_3(rotor_start_3)
			);
	
	always
		#(5) i_clock <= !i_clock;
 
    initial
	begin
		$dumpfile("testrotor.vcd");
		$dumpvars(0,testrotor);
		
		#5
		reset = 1;
		#10
		reset = 0;
		for (i = 0; i < 128; i = i + 1) 		
		begin
		#10
			rotate = 1;
		#10
			rotate = 0;
		#20
			$display("Rotors [%c] [%c] [%c]",rotor1+65,rotor2+65,rotor3+65);
		end


		#10

		$finish;
	end
endmodule