data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:19: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen,data/full_repos/permissive/214858095/test_exec.svh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen,data/full_repos/permissive/214858095/test_exec.svh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen,data/full_repos/permissive/214858095/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:26: Cannot find include file: rfnoc_block_siggen_regs.vh\n  `include "rfnoc_block_siggen_regs.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:21: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgTestExec::*;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:101: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);\n                                               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:104: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:105: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::item_t      item_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:305: syntax error, unexpected IDENTIFIER\n    item_t items[$];\n           ^~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:308: Unsupported: fork statements\n      fork\n      ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:312: Unsupported: wait statements\n            wait(!m_rfnoc_chdr_tvalid[port]);\n            ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:313: Unsupported: wait statements\n          wait(m_rfnoc_chdr_tvalid[port]);\n          ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:316: Unsupported: Ignoring delay on this delayed statement.\n          #(CHDR_CLK_PER*timeout);\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:353: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(value === expected, {err_msg, "initial value"});\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:353: syntax error, unexpected \',\'\n    `ASSERT_ERROR(value === expected, {err_msg, "initial value"});\n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:359: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(value === expected, {err_msg, "write max value"});\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:359: syntax error, unexpected \',\'\n    `ASSERT_ERROR(value === expected, {err_msg, "write max value"});\n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:365: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(value === expected, {err_msg, "write zero"});\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:365: syntax error, unexpected \',\'\n    `ASSERT_ERROR(value === expected, {err_msg, "write zero"});\n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:397: syntax error, unexpected IDENTIFIER\n      item_t items[$];\n             ^~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:404: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:405: syntax error, unexpected \',\'\n        items.size() == spp,\n                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:429: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:430: syntax error, unexpected \',\'\n            actual == expected_const,\n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:437: Define or directive not defined: \'`ASSERT_ERROR\'\n          `ASSERT_ERROR(\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:438: syntax error, unexpected \',\'\n            samples_are_close(actual, expected_sine),\n                                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:446: Define or directive not defined: \'`ASSERT_ERROR\'\n            `ASSERT_ERROR(items[i] !== items[i-1],\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:446: syntax error, unexpected \',\'\n            `ASSERT_ERROR(items[i] !== items[i-1],\n                                                 ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:475: Define or directive not defined: \'`ASSERT_FATAL\'\n    `ASSERT_FATAL(gain <= MAX_GAIN_R   || gain >= MIN_GAIN_R,  "Gain out of range");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:475: syntax error, unexpected \',\'\n    `ASSERT_FATAL(gain <= MAX_GAIN_R   || gain >= MIN_GAIN_R,  "Gain out of range");\n                                                            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:476: Define or directive not defined: \'`ASSERT_FATAL\'\n    `ASSERT_FATAL(re   <= MAX_CONST_R  || re   >= MIN_CONST_R, "Real out of range");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:476: syntax error, unexpected \',\'\n    `ASSERT_FATAL(re   <= MAX_CONST_R  || re   >= MIN_CONST_R, "Real out of range");\n                                                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:477: Define or directive not defined: \'`ASSERT_FATAL\'\n    `ASSERT_FATAL(im   <= MAX_CONST_R  || im   >= MIN_CONST_R, "Imag out of range");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:477: syntax error, unexpected \',\'\n    `ASSERT_FATAL(im   <= MAX_CONST_R  || im   >= MIN_CONST_R, "Imag out of range");\n                                                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:511: Define or directive not defined: \'`ASSERT_FATAL\'\n    `ASSERT_FATAL(gain  <= MAX_GAIN_R  || gain  >= MIN_GAIN_R,  "Gain out of range");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:511: syntax error, unexpected \',\'\n    `ASSERT_FATAL(gain  <= MAX_GAIN_R  || gain  >= MIN_GAIN_R,  "Gain out of range");\n                                                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:512: Define or directive not defined: \'`ASSERT_FATAL\'\n    `ASSERT_FATAL(x     <= MAX_CART_R  || x     >= MIN_CART_R,  "X out of range");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:512: syntax error, unexpected \',\'\n    `ASSERT_FATAL(x     <= MAX_CART_R  || x     >= MIN_CART_R,  "X out of range");\n                                                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:513: Define or directive not defined: \'`ASSERT_FATAL\'\n    `ASSERT_FATAL(y     <= MAX_CART_R  || y     >= MIN_CART_R,  "Y out of range");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:513: syntax error, unexpected \',\'\n    `ASSERT_FATAL(y     <= MAX_CART_R  || y     >= MIN_CART_R,  "Y out of range");\n                                                             ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:514: Define or directive not defined: \'`ASSERT_FATAL\'\n    `ASSERT_FATAL(phase <= MAX_PHASE_R || phase >= MIN_PHASE_R, "Phase out of range");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:514: syntax error, unexpected \',\'\n    `ASSERT_FATAL(phase <= MAX_PHASE_R || phase >= MIN_PHASE_R, "Phase out of range");\n                                                              ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:547: Define or directive not defined: \'`ASSERT_FATAL\'\n    `ASSERT_FATAL(gain <= MAX_GAIN_R || gain >= MIN_GAIN_R, "Gain out of range");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:547: syntax error, unexpected \',\'\n    `ASSERT_FATAL(gain <= MAX_GAIN_R || gain >= MIN_GAIN_R, "Gain out of range");\n                                                          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:569: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test($sformatf("Test registers (port %0d)", port), 1ms);\n                                                                  ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:582: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test($sformatf("Test waveforms (port %0d)", port), 1ms);\n                                                                  ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:597: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test($sformatf("Test gain (port %0d)", port), 1ms);\n                                                             ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:625: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test($sformatf("Test phase (port %0d)", port), 1ms);\n                                                              ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:638: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test($sformatf("Test packet length (port %0d)", port), 1ms);\n                                                                      ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:672: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test("Flush block then reset it", 10us);\n                                                 ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:680: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test("Verify Block Info", 2us);\n                                         ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:681: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_siggen/rfnoc_block_siggen_tb.sv:681: syntax error, unexpected \',\'\n    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");\n                                                 ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
function bit samples_are_close(
    logic [31:0] samp_a, samp_b,
    real         threshold = 3.0
  );
    real ax, ay, bx, by;
    real distance;


    ax = signed'(samp_a[31:16]);
    ay = signed'(samp_a[15: 0]);
    bx = signed'(samp_b[31:16]);
    by = signed'(samp_b[15: 0]);

    distance = $sqrt( (ax-bx)*(ax-bx) + (ay-by)*(ay-by) );

    return distance <= threshold;
  endfunction
function bit samples_are_close(
    logic [31:0] samp_a, samp_b,
    real         threshold = 3.0
  );

    real ax, ay, bx, by;
    real distance;


    ax = signed'(samp_a[31:16]);
    ay = signed'(samp_a[15: 0]);
    bx = signed'(samp_b[31:16]);
    by = signed'(samp_b[15: 0]);

    distance = $sqrt( (ax-bx)*(ax-bx) + (ay-by)*(ay-by) );

    return distance <= threshold;
  endfunction