data/full_repos/permissive/143278/ivltests/array_lval_select4b.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/143278/ivltests/array_lval_select4b.v:10: Unsupported: Verilog 1995 force\n  force array1[index] = 1'b1;\n  ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/array_lval_select4b.v:11: Unsupported: Verilog 1995 release\n  release array1[index];\n  ^~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top;

wire array1[2:1];

integer index = 1;

initial begin
  force array1[index] = 1'b1;
  release array1[index];
end

endmodule
module top;


wire array1[2:1];

integer index = 1;

initial begin
  force array1[index] = 1'b1;
  release array1[index];
end

endmodule