data/full_repos/permissive/114643454/src/ex_mem.v
 line:6: before: "]"
1: b"%Error: data/full_repos/permissive/114643454/src/ex_mem.v:6: Define or directive not defined: '`RegAddrBus'\n    input   wire[`RegAddrBus]   ex_wd,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:6: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n    input   wire[`RegAddrBus]   ex_wd,\n                            ^\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:8: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegBus]       ex_wdata,\n    ^~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:8: Define or directive not defined: '`RegBus'\n    input   wire[`RegBus]       ex_wdata,\n                 ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`AluOpBus]     ex_aluop,\n    ^~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:11: Define or directive not defined: '`AluOpBus'\n    input   wire[`AluOpBus]     ex_aluop,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:12: Define or directive not defined: '`RegBus'\n    input   wire[`RegBus]       ex_mem_addr,\n                 ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:13: Define or directive not defined: '`RegBus'\n    input   wire[`RegBus]       ex_reg2,\n                 ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:15: Define or directive not defined: '`RegAddrBus'\n    output  reg[`RegAddrBus]    mem_wd,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:17: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output  reg[`RegBus]        mem_wdata,\n    ^~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:17: Define or directive not defined: '`RegBus'\n    output  reg[`RegBus]        mem_wdata,\n                ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:19: Define or directive not defined: '`AluOpBus'\n    output  reg[`AluOpBus]      mem_aluop,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:20: Define or directive not defined: '`RegBus'\n    output  reg[`RegBus]        mem_mem_addr,\n                ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:21: Define or directive not defined: '`RegBus'\n    output  reg[`RegBus]        mem_reg2\n                ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:26: Define or directive not defined: '`RstEnable'\n        if (rst == `RstEnable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:27: Define or directive not defined: '`NOPRegAddr'\n            mem_wd <= `NOPRegAddr;\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:28: Define or directive not defined: '`WriteDisable'\n            mem_wreg <= `WriteDisable;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:29: Define or directive not defined: '`ZeroWord'\n            mem_wdata <= `ZeroWord;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:31: Define or directive not defined: '`EXE_NOP_OP'\n            mem_aluop <= `EXE_NOP_OP;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:32: Define or directive not defined: '`ZeroWord'\n            mem_mem_addr <= `ZeroWord;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:33: Define or directive not defined: '`ZeroWord'\n            mem_reg2 <= `ZeroWord;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:34: Define or directive not defined: '`Stop'\n        end else if (stall[3] == `Stop && stall[4] == `NoStop) begin\n                                 ^~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:34: Define or directive not defined: '`NoStop'\n        end else if (stall[3] == `Stop && stall[4] == `NoStop) begin\n                                                      ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:35: Define or directive not defined: '`NOPRegAddr'\n            mem_wd <= `NOPRegAddr;\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:36: Define or directive not defined: '`WriteDisable'\n            mem_wreg <= `WriteDisable;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:37: Define or directive not defined: '`ZeroWord'\n            mem_wdata <= `ZeroWord;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:39: Define or directive not defined: '`EXE_NOP_OP'\n            mem_aluop <= `EXE_NOP_OP;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:40: Define or directive not defined: '`ZeroWord'\n            mem_mem_addr <= `ZeroWord;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:41: Define or directive not defined: '`ZeroWord'\n            mem_reg2 <= `ZeroWord;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/ex_mem.v:42: Define or directive not defined: '`NoStop'\n        end else if (stall[3] == `NoStop) begin\n                                 ^~~~~~~\n%Error: Exiting due to 30 error(s)\n"
module ex_mem (

    input   wire                clk,
    input   wire                rst,

    input   wire[`RegAddrBus]   ex_wd,
    input   wire                ex_wreg,
    input   wire[`RegBus]       ex_wdata,
    input   wire[5 : 0]         stall,

    input   wire[`AluOpBus]     ex_aluop,
    input   wire[`RegBus]       ex_mem_addr,
    input   wire[`RegBus]       ex_reg2,

    output  reg[`RegAddrBus]    mem_wd,
    output  reg                 mem_wreg,
    output  reg[`RegBus]        mem_wdata,

    output  reg[`AluOpBus]      mem_aluop,
    output  reg[`RegBus]        mem_mem_addr,
    output  reg[`RegBus]        mem_reg2

);

    always @ (posedge clk) begin
        if (rst == `RstEnable) begin
            mem_wd <= `NOPRegAddr;
            mem_wreg <= `WriteDisable;
            mem_wdata <= `ZeroWord;

            mem_aluop <= `EXE_NOP_OP;
            mem_mem_addr <= `ZeroWord;
            mem_reg2 <= `ZeroWord;
        end else if (stall[3] == `Stop && stall[4] == `NoStop) begin
            mem_wd <= `NOPRegAddr;
            mem_wreg <= `WriteDisable;
            mem_wdata <= `ZeroWord;

            mem_aluop <= `EXE_NOP_OP;
            mem_mem_addr <= `ZeroWord;
            mem_reg2 <= `ZeroWord;
        end else if (stall[3] == `NoStop) begin

            mem_wd <= ex_wd;
            mem_wreg <= ex_wreg;
            mem_wdata <= ex_wdata;

            mem_aluop <= ex_aluop;
            mem_mem_addr <= ex_mem_addr;
            mem_reg2 <= ex_reg2;
        end
    end

endmodule
module ex_mem (

    input   wire                clk,
    input   wire                rst,

    input   wire[`RegAddrBus]   ex_wd,
    input   wire                ex_wreg,
    input   wire[`RegBus]       ex_wdata,
    input   wire[5 : 0]         stall,

    input   wire[`AluOpBus]     ex_aluop,
    input   wire[`RegBus]       ex_mem_addr,
    input   wire[`RegBus]       ex_reg2,

    output  reg[`RegAddrBus]    mem_wd,
    output  reg                 mem_wreg,
    output  reg[`RegBus]        mem_wdata,

    output  reg[`AluOpBus]      mem_aluop,
    output  reg[`RegBus]        mem_mem_addr,
    output  reg[`RegBus]        mem_reg2

);


    always @ (posedge clk) begin
        if (rst == `RstEnable) begin
            mem_wd <= `NOPRegAddr;
            mem_wreg <= `WriteDisable;
            mem_wdata <= `ZeroWord;

            mem_aluop <= `EXE_NOP_OP;
            mem_mem_addr <= `ZeroWord;
            mem_reg2 <= `ZeroWord;
        end else if (stall[3] == `Stop && stall[4] == `NoStop) begin
            mem_wd <= `NOPRegAddr;
            mem_wreg <= `WriteDisable;
            mem_wdata <= `ZeroWord;

            mem_aluop <= `EXE_NOP_OP;
            mem_mem_addr <= `ZeroWord;
            mem_reg2 <= `ZeroWord;
        end else if (stall[3] == `NoStop) begin

            mem_wd <= ex_wd;
            mem_wreg <= ex_wreg;
            mem_wdata <= ex_wdata;

            mem_aluop <= ex_aluop;
            mem_mem_addr <= ex_mem_addr;
            mem_reg2 <= ex_reg2;
        end
    end

endmodule