data/full_repos/permissive/157005262/verilog/traffic_tb.v
 line:28: before: "$"
1: b'%Error: data/full_repos/permissive/157005262/verilog/traffic_tb.v:1: Cannot find include file: traffic.v\n`include "traffic.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/traffic.v\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/traffic.v.v\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/traffic.v.sv\n             traffic.v\n             traffic.v.v\n             traffic.v.sv\n             obj_dir/traffic.v\n             obj_dir/traffic.v.v\n             obj_dir/traffic.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/157005262/verilog/traffic_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n    forever #1 clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/157005262/verilog/traffic_tb.v:15: Unsupported or unknown PLI call: $monitor\n      $monitor($time, " clk = %b, go = %b, red = %b, yellow = %b, green = %b",\n      ^~~~~~~~\n%Error: data/full_repos/permissive/157005262/verilog/traffic_tb.v:17: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile(`VCD_FILE);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/157005262/verilog/traffic_tb.v:17: Define or directive not defined: \'`VCD_FILE\'\n      $dumpfile(`VCD_FILE);\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/157005262/verilog/traffic_tb.v:18: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/157005262/verilog/traffic_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #4 go <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/157005262/verilog/traffic_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #12 go <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/157005262/verilog/traffic_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #12 $finish;\n      ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module Top;
  reg clk = 1;
  reg go = 0;
  wire red, yellow, green;

  traffic t(clk, go, red, yellow, green);

  initial
    forever #1 clk = ~clk;

  initial
    begin
      $monitor($time, " clk = %b, go = %b, red = %b, yellow = %b, green = %b",
               clk, go, red, yellow, green);
      $dumpfile(`VCD_FILE);
      $dumpvars;

      #4 go <= 1;
      #12 go <= 0;
      #12 $finish;
    end
endmodule
module Top;

  reg clk = 1;
  reg go = 0;
  wire red, yellow, green;

  traffic t(clk, go, red, yellow, green);

  initial
    forever #1 clk = ~clk;

  initial
    begin
      $monitor($time, " clk = %b, go = %b, red = %b, yellow = %b, green = %b",
               clk, go, red, yellow, green);
      $dumpfile(`VCD_FILE);
      $dumpvars;

      #4 go <= 1;
      #12 go <= 0;
      #12 $finish;
    end
endmodule