data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_CONV1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_CONV1.v:33: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_CONV1.v:46: Unsupported: Ignoring delay on this delayed statement.\n         #400000;\n         ^\n%Error: data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI/TB_CONV1.v:31: Cannot find file containing module: \'CONV1\'\n    CONV1 uut( .clk(clk), .reset(reset), .R(R), .G(G), .B(B), .y(y), .states(state), .count(count));\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/CONV1\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/CONV1.v\n             data/full_repos/permissive/139285952/CNN/CNN.srcs/sources_1/imports/VLSI,data/full_repos/permissive/139285952/CONV1.sv\n             CONV1\n             CONV1.v\n             CONV1.sv\n             obj_dir/CONV1\n             obj_dir/CONV1.v\n             obj_dir/CONV1.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_CONV1;
    reg clk;
    reg [7:0] R,G,B;
    reg reset;
    
    wire signed [21:0] y;
    wire [1:0] state;
    wire [6:0] count;
    
    CONV1 uut( .clk(clk), .reset(reset), .R(R), .G(G), .B(B), .y(y), .states(state), .count(count));
    
    always #5 clk = ~clk;
         
    integer image_R,image_G,image_B;
    integer output_File;
    integer filter_num = 0;
         
     initial begin
         clk = 0;
         reset = 0;
         image_R=$fopen("image_R.txt","r");
         image_G=$fopen("image_G.txt","r");
         image_B=$fopen("image_B.txt","r");
         output_File=$fopen("convimage.txt","w");
         #400000;
         $finish;
     end
     
     always @ (posedge clk)
     begin
        $fwrite(output_File,"%d\n",y);
        if( (state == 1) && ( count < 64 ))
        begin
             $fscanf(image_R,"%d\n",R);
             $fscanf(image_G,"%d\n",G);
             $fscanf(image_B,"%d\n",B);
        end
         if($feof(image_R)&& $feof(image_G)&& $feof(image_B) && (filter_num != 7))
         begin
            $fclose(image_R);$fclose(image_G);$fclose(image_B);
            filter_num = filter_num + 1;
            image_R=$fopen("image_R.txt","r");
            image_G=$fopen("image_G.txt","r");
            image_B=$fopen("image_B.txt","r");
         end else if($feof(image_R)&& $feof(image_G)&& $feof(image_B) && (filter_num == 7))
         begin
            $fclose(image_R);$fclose(image_G);$fclose(image_B);
         end
         
     end
endmodule
module TB_CONV1;

    reg clk;
    reg [7:0] R,G,B;
    reg reset;
    
    wire signed [21:0] y;
    wire [1:0] state;
    wire [6:0] count;
    
    CONV1 uut( .clk(clk), .reset(reset), .R(R), .G(G), .B(B), .y(y), .states(state), .count(count));
    
    always #5 clk = ~clk;
         
    integer image_R,image_G,image_B;
    integer output_File;
    integer filter_num = 0;
         
     initial begin
         clk = 0;
         reset = 0;
         image_R=$fopen("image_R.txt","r");
         image_G=$fopen("image_G.txt","r");
         image_B=$fopen("image_B.txt","r");
         output_File=$fopen("convimage.txt","w");
         #400000;
         $finish;
     end
     
     always @ (posedge clk)
     begin
        $fwrite(output_File,"%d\n",y);
        if( (state == 1) && ( count < 64 ))
        begin
             $fscanf(image_R,"%d\n",R);
             $fscanf(image_G,"%d\n",G);
             $fscanf(image_B,"%d\n",B);
        end
         if($feof(image_R)&& $feof(image_G)&& $feof(image_B) && (filter_num != 7))
         begin
            $fclose(image_R);$fclose(image_G);$fclose(image_B);
            filter_num = filter_num + 1;
            image_R=$fopen("image_R.txt","r");
            image_G=$fopen("image_G.txt","r");
            image_B=$fopen("image_B.txt","r");
         end else if($feof(image_R)&& $feof(image_G)&& $feof(image_B) && (filter_num == 7))
         begin
            $fclose(image_R);$fclose(image_G);$fclose(image_B);
         end
         
     end
endmodule