data/full_repos/permissive/201275379/src/cpu/cache/InstCache.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/src/cpu/cache/InstCache.v:3: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/src/cpu/cache,data/full_repos/permissive/201275379/bus.v\n             data/full_repos/permissive/201275379/src/cpu/cache,data/full_repos/permissive/201275379/bus.v.v\n             data/full_repos/permissive/201275379/src/cpu/cache,data/full_repos/permissive/201275379/bus.v.sv\n             bus.v\n             bus.v.v\n             bus.v.sv\n             obj_dir/bus.v\n             obj_dir/bus.v.v\n             obj_dir/bus.v.sv\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/InstCache.v:4: Cannot find include file: cache.v\n`include "cache.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/InstCache.v:12: Define or directive not defined: \'`ADDR_BUS\'\n  input   [`ADDR_BUS] addr_read,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/InstCache.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  input   [`ADDR_BUS] addr_read,\n                    ^\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/InstCache.v:13: Define or directive not defined: \'`ADDR_BUS\'\n  input   [`ADDR_BUS] addr_inv,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/InstCache.v:15: Define or directive not defined: \'`DATA_BUS\'\n  output  [`DATA_BUS] data_out,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/InstCache.v:59: Define or directive not defined: \'`ICACHE_LINE_WIDTH\'\n  localparam kIndexWidth = `ICACHE_LINE_WIDTH - 2,\n                           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/InstCache.v:60: Define or directive not defined: \'`ADDR_BUS_WIDTH\'\n      kTagWidth = `ADDR_BUS_WIDTH - `ICACHE_LINE_WIDTH - `ICACHE_WIDTH;\n                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/InstCache.v:60: Define or directive not defined: \'`ICACHE_LINE_WIDTH\'\n      kTagWidth = `ADDR_BUS_WIDTH - `ICACHE_LINE_WIDTH - `ICACHE_WIDTH;\n                                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/InstCache.v:60: Define or directive not defined: \'`ICACHE_WIDTH\'\n      kTagWidth = `ADDR_BUS_WIDTH - `ICACHE_LINE_WIDTH - `ICACHE_WIDTH;\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/InstCache.v:60: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      kTagWidth = `ADDR_BUS_WIDTH - `ICACHE_LINE_WIDTH - `ICACHE_WIDTH;\n                                                                      ^\n%Error: Exiting due to 11 error(s)\n'
module InstCache(
  input               clk,
  input               rst,

  input               read_en,
  input               hit_invalidate,
  input   [`ADDR_BUS] addr_read,
  input   [`ADDR_BUS] addr_inv,
  output              ready,
  output  [`DATA_BUS] data_out,

  output  [3:0]       arid,
  output  [31:0]      araddr,
  output  [7:0]       arlen,
  output  [2:0]       arsize,
  output  [1:0]       arburst,
  output  [1:0]       arlock,
  output  [3:0]       arcache,
  output  [2:0]       arprot,
  output              arvalid,
  input               arready,

  input   [3:0]       rid,
  input   [31:0]      rdata,
  input   [1:0]       rresp,
  input               rlast,
  input               rvalid,
  output              rready,

  output  [3:0]       awid,
  output  [31:0]      awaddr,
  output  [7:0]       awlen,
  output  [2:0]       awsize,
  output  [1:0]       awburst,
  output  [1:0]       awlock,
  output  [3:0]       awcache,
  output  [2:0]       awprot,
  output              awvalid,
  input               awready,

  output  [3:0]       wid,
  output  [31:0]      wdata,
  output  [3:0]       wstrb,
  output              wlast,
  output              wvalid,
  input               wready,

  input   [3:0]       bid,
  input   [1:0]       bresp,
  input               bvalid,
  output              bready
);

  localparam kIndexWidth = `ICACHE_LINE_WIDTH - 2,
      kTagWidth = `ADDR_BUS_WIDTH - `ICACHE_LINE_WIDTH - `ICACHE_WIDTH;




endmodule
module InstCache(
  input               clk,
  input               rst,

  input               read_en,
  input               hit_invalidate,
  input   [`ADDR_BUS] addr_read,
  input   [`ADDR_BUS] addr_inv,
  output              ready,
  output  [`DATA_BUS] data_out,

  output  [3:0]       arid,
  output  [31:0]      araddr,
  output  [7:0]       arlen,
  output  [2:0]       arsize,
  output  [1:0]       arburst,
  output  [1:0]       arlock,
  output  [3:0]       arcache,
  output  [2:0]       arprot,
  output              arvalid,
  input               arready,

  input   [3:0]       rid,
  input   [31:0]      rdata,
  input   [1:0]       rresp,
  input               rlast,
  input               rvalid,
  output              rready,

  output  [3:0]       awid,
  output  [31:0]      awaddr,
  output  [7:0]       awlen,
  output  [2:0]       awsize,
  output  [1:0]       awburst,
  output  [1:0]       awlock,
  output  [3:0]       awcache,
  output  [2:0]       awprot,
  output              awvalid,
  input               awready,

  output  [3:0]       wid,
  output  [31:0]      wdata,
  output  [3:0]       wstrb,
  output              wlast,
  output              wvalid,
  input               wready,

  input   [3:0]       bid,
  input   [1:0]       bresp,
  input               bvalid,
  output              bready
);


  localparam kIndexWidth = `ICACHE_LINE_WIDTH - 2,
      kTagWidth = `ADDR_BUS_WIDTH - `ICACHE_LINE_WIDTH - `ICACHE_WIDTH;




endmodule