data/full_repos/permissive/159902111/MCPU_experiment/MIPS.v
1: b'%Error: data/full_repos/permissive/159902111/MCPU_experiment/MIPS.v:1: Cannot find include file: Instruction_def.v\n`include "Instruction_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159902111/MCPU_experiment,data/full_repos/permissive/159902111/Instruction_def.v\n             data/full_repos/permissive/159902111/MCPU_experiment,data/full_repos/permissive/159902111/Instruction_def.v.v\n             data/full_repos/permissive/159902111/MCPU_experiment,data/full_repos/permissive/159902111/Instruction_def.v.sv\n             Instruction_def.v\n             Instruction_def.v.v\n             Instruction_def.v.sv\n             obj_dir/Instruction_def.v\n             obj_dir/Instruction_def.v.v\n             obj_dir/Instruction_def.v.sv\n%Error: data/full_repos/permissive/159902111/MCPU_experiment/MIPS.v:2: Cannot find include file: BEOp_def.v\n`include "BEOp_def.v" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module MIPS(
  input clk,
  input rst
  );
  wire       MemWrite, Sign;
  wire [3:0] BE_signal;
  wire [31:0] final_Addr, DataIn, DataOut;
  assign BE_signal = 4'b1111;
  assign Sign = 1'b0;
  Memory my_Memory(clk, rst, final_Addr, DataIn, MemWrite, BE_signal, Sign, DataOut);
  Multi_CPU Multi_CPU(.clk(clk), .reset(rst), .MIO_ready(), .Data_in(DataOut), .INT(), .mem_w(MemWrite),
    .inst_out(), .PC_out(), .Addr_out(final_Addr), .Data_out(DataIn), .state(), .CPU_MIO());
endmodule
module MIPS(
  input clk,
  input rst
  );

  wire       MemWrite, Sign;
  wire [3:0] BE_signal;
  wire [31:0] final_Addr, DataIn, DataOut;
  assign BE_signal = 4'b1111;
  assign Sign = 1'b0;
  Memory my_Memory(clk, rst, final_Addr, DataIn, MemWrite, BE_signal, Sign, DataOut);
  Multi_CPU Multi_CPU(.clk(clk), .reset(rst), .MIO_ready(), .Data_in(DataOut), .INT(), .mem_w(MemWrite),
    .inst_out(), .PC_out(), .Addr_out(final_Addr), .Data_out(DataIn), .state(), .CPU_MIO());
endmodule