data/full_repos/permissive/115035459/verilog/src/mza-test022.frequency-counter.uart.v
None: at end of input
1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test022.frequency-counter.uart.v:8: Cannot find include file: lib/hex2bcd.v\n`include "lib/hex2bcd.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.sv\n             lib/hex2bcd.v\n             lib/hex2bcd.v.v\n             lib/hex2bcd.v.sv\n             obj_dir/lib/hex2bcd.v\n             obj_dir/lib/hex2bcd.v.v\n             obj_dir/lib/hex2bcd.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test022.frequency-counter.uart.v:9: Cannot find include file: lib/segmented_display_driver.v\n`include "lib/segmented_display_driver.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test022.frequency-counter.uart.v:10: Cannot find include file: lib/frequency_counter.v\n`include "lib/frequency_counter.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module mytop (
	input clock,
	output [5:1] LED,
	inout [7:0] J1,
	inout [7:0] J2,
	inout [7:0] J3,
	input RX,
	output TX
);
	reg [31:0] counter = 0;
	wire [31:0] result;
	reg [31:0] result2 = 32'h87654321;

	reg [23:0] value2 = 24'd12345678;

	wire [31:0] bcd2;

	reg [31:0] buffered_bcd2 = 32'h88888888;
	wire external_reference_clock;
	wire raw_external_clock_to_measure;
	wire mirror_of_raw_external_clock_to_measure;
	reg external_clock_to_measure = 0;
	wire reference_clock;
	wire signal_output;

	assign signal_output = clock;
	assign J2[1] = signal_output;
	assign J2[2] = signal_output;

	assign external_reference_clock = J1[6];


	assign raw_external_clock_to_measure = J1[7];


	assign reference_clock = external_reference_clock;
	assign J1[0] = signal_output;


	assign J3[0] = J1[7];
	localparam N = 1;
	wire frequency_counter_sync;
	frequency_counter #(.FREQUENCY_OF_REFERENCE_CLOCK(25000000), .LOG2_OF_DIVIDE_RATIO(25), .N(N)) fc (.reference_clock(reference_clock), .unknown_clock(raw_external_clock_to_measure), .frequency_of_unknown_clock(result), .valid(frequency_counter_sync));

	wire [7:0] segment;
	assign { J1[4], J1[1], J3[4], J3[5], J1[2], J1[5], J1[3], J3[2] } = segment;
	wire [7:0] anode;
	assign { J2[7], J2[4], J2[5], J2[6], J3[6], J3[7], J3[3], J3[1] } = anode;
	wire [7:0] dp = (N==1) ? 8'b01000000 : (N==10) ? 8'b00100000 : 8'b00010000;










	wire segmented_display_driver_sync;
	segmented_display_driver #(.NUMBER_OF_SEGMENTS(8), .NUMBER_OF_NYBBLES(8)) my_segmented_display_driver (.clock(clock), .data(buffered_bcd2), .dp(dp), .cathode(segment), .anode(anode), .sync_anode(segmented_display_driver_sync), .sync_cathode());
	wire hex2bcd_sync;
	assign LED[5] = 0;
	assign LED[4] = signal_output;
	assign LED[3] = segmented_display_driver_sync;
	assign LED[2] = hex2bcd_sync;
	assign LED[1] = frequency_counter_sync;




	localparam uart_line_pickoff = 22;
	localparam slow_clock_pickoff = 19;

	reg reset = 1;
	wire uart_resetb;
	assign uart_resetb = ~reset;


	always @(posedge clock) begin
		counter <= counter + 1'b1;
		if (reset) begin



			if (counter[10]) begin
				reset <= 0;
			end
			value2 <= 24'd12345678;
			result2 <= 32'h87654321;
			buffered_bcd2 <= 32'h88888888;
		end
		if (counter[slow_clock_pickoff:0]==0) begin
			buffered_bcd2 <= bcd2;


		end else if (counter[slow_clock_pickoff:0]==1) begin
			value2 <= result2[23:0];

		end else if (counter[slow_clock_pickoff:0]==2) begin
			result2 <= result;
		end





















































	end

	hex2bcd #(.INPUT_SIZE_IN_NYBBLES(6)) h2binst2 ( .clock(clock), .reset(~uart_resetb), .hex_in(value2), .bcd_out(bcd2), .sync(hex2bcd_sync) );













	assign TX = 0;
endmodule
module mytop (
	input clock,
	output [5:1] LED,
	inout [7:0] J1,
	inout [7:0] J2,
	inout [7:0] J3,
	input RX,
	output TX
);

	reg [31:0] counter = 0;
	wire [31:0] result;
	reg [31:0] result2 = 32'h87654321;

	reg [23:0] value2 = 24'd12345678;

	wire [31:0] bcd2;

	reg [31:0] buffered_bcd2 = 32'h88888888;
	wire external_reference_clock;
	wire raw_external_clock_to_measure;
	wire mirror_of_raw_external_clock_to_measure;
	reg external_clock_to_measure = 0;
	wire reference_clock;
	wire signal_output;

	assign signal_output = clock;
	assign J2[1] = signal_output;
	assign J2[2] = signal_output;

	assign external_reference_clock = J1[6];


	assign raw_external_clock_to_measure = J1[7];


	assign reference_clock = external_reference_clock;
	assign J1[0] = signal_output;


	assign J3[0] = J1[7];
	localparam N = 1;
	wire frequency_counter_sync;
	frequency_counter #(.FREQUENCY_OF_REFERENCE_CLOCK(25000000), .LOG2_OF_DIVIDE_RATIO(25), .N(N)) fc (.reference_clock(reference_clock), .unknown_clock(raw_external_clock_to_measure), .frequency_of_unknown_clock(result), .valid(frequency_counter_sync));

	wire [7:0] segment;
	assign { J1[4], J1[1], J3[4], J3[5], J1[2], J1[5], J1[3], J3[2] } = segment;
	wire [7:0] anode;
	assign { J2[7], J2[4], J2[5], J2[6], J3[6], J3[7], J3[3], J3[1] } = anode;
	wire [7:0] dp = (N==1) ? 8'b01000000 : (N==10) ? 8'b00100000 : 8'b00010000;










	wire segmented_display_driver_sync;
	segmented_display_driver #(.NUMBER_OF_SEGMENTS(8), .NUMBER_OF_NYBBLES(8)) my_segmented_display_driver (.clock(clock), .data(buffered_bcd2), .dp(dp), .cathode(segment), .anode(anode), .sync_anode(segmented_display_driver_sync), .sync_cathode());
	wire hex2bcd_sync;
	assign LED[5] = 0;
	assign LED[4] = signal_output;
	assign LED[3] = segmented_display_driver_sync;
	assign LED[2] = hex2bcd_sync;
	assign LED[1] = frequency_counter_sync;




	localparam uart_line_pickoff = 22;
	localparam slow_clock_pickoff = 19;

	reg reset = 1;
	wire uart_resetb;
	assign uart_resetb = ~reset;


	always @(posedge clock) begin
		counter <= counter + 1'b1;
		if (reset) begin



			if (counter[10]) begin
				reset <= 0;
			end
			value2 <= 24'd12345678;
			result2 <= 32'h87654321;
			buffered_bcd2 <= 32'h88888888;
		end
		if (counter[slow_clock_pickoff:0]==0) begin
			buffered_bcd2 <= bcd2;


		end else if (counter[slow_clock_pickoff:0]==1) begin
			value2 <= result2[23:0];

		end else if (counter[slow_clock_pickoff:0]==2) begin
			result2 <= result;
		end





















































	end

	hex2bcd #(.INPUT_SIZE_IN_NYBBLES(6)) h2binst2 ( .clock(clock), .reset(~uart_resetb), .hex_in(value2), .bcd_out(bcd2), .sync(hex2bcd_sync) );













	assign TX = 0;
endmodule