data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n         ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n                ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) GSR = GSR_int;\n            ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) GSR = GSR_int;\n                   ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) GTS = GTS_int;\n            ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) GTS = GTS_int;\n                   ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) PRLD = PRLD_int;\n            ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) PRLD = PRLD_int;\n                   ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized34
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \G_1PIPE_IFACE.s_di_r_reg[15] ,
    s_dwe_o,
    \G_1PIPE_IFACE.s_daddr_r_reg[12] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[5] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[7] ,
    s_daddr_o,
    s_di_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \G_1PIPE_IFACE.s_di_r_reg[15] ;
  input s_dwe_o;
  input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
  input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
  input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
  input [3:0]s_daddr_o;
  input [14:0]s_di_o;

  wire [0:0]E;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
  wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__36_n_0 ;
  wire \current_state[3]_i_3__36_n_0 ;
  wire \current_state[3]_i_4__36_n_0 ;
  wire data_out_sel;
  wire data_out_sel_i_1__36_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire \shadow[0]_i_1__36_n_0 ;
  wire \shadow[10]_i_1__36_n_0 ;
  wire \shadow[11]_i_1__36_n_0 ;
  wire \shadow[12]_i_1__36_n_0 ;
  wire \shadow[13]_i_1__36_n_0 ;
  wire \shadow[14]_i_1__36_n_0 ;
  wire \shadow[15]_i_1__36_n_0 ;
  wire \shadow[1]_i_1__36_n_0 ;
  wire \shadow[2]_i_1__36_n_0 ;
  wire \shadow[3]_i_1__36_n_0 ;
  wire \shadow[4]_i_1__36_n_0 ;
  wire \shadow[5]_i_1__36_n_0 ;
  wire \shadow[6]_i_1__36_n_0 ;
  wire \shadow[7]_i_1__36_n_0 ;
  wire \shadow[8]_i_1__36_n_0 ;
  wire \shadow[9]_i_1__36_n_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__36_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__36 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__36 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__36 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(clear));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__36 
       (.I0(cnt_reg[2]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[1]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__36 
       (.I0(\current_state[3]_i_4__36_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__36_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__36_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__36 
       (.I0(s_dwe_o),
        .I1(\current_state[3]_i_4__36_n_0 ),
        .I2(current_state[0]),
        .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
        .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__36 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__36_n_0 ),
        .I2(\current_state[3]_i_4__36_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__36 
       (.I0(\current_state[3]_i_2__36_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__36_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__36_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__36 
       (.I0(cnt_reg[2]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[1]),
        .I3(cnt_reg[3]),
        .O(\current_state[3]_i_2__36_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \current_state[3]_i_3__36 
       (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
        .O(\current_state[3]_i_3__36_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__36 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__36_n_0 ));
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__36
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__36_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__36_n_0),
        .Q(data_out_sel),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__36 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[0]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__36 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[10]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__36 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[11]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__36 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[12]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__36 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[13]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__36 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[14]_i_1__36_n_0 ));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__36 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__36 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[1]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__36 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[2]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__36 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[3]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__36 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[4]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__36 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[5]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__36 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[6]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__36 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[7]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__36 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[8]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__36 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[9]_i_1__36_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[0]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[10]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[11]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[12]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[13]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[14]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[1]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[2]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[3]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[4]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[5]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[6]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[7]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[8]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[9]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0104)) 
    shift_en_i_1__36
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[1]),
        .I3(current_state[2]),
        .O(shift_en_i_1__36_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__36_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__35
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized34
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \G_1PIPE_IFACE.s_di_r_reg[15] ,
    s_dwe_o,
    \G_1PIPE_IFACE.s_daddr_r_reg[12] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[5] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[7] ,
    s_daddr_o,
    s_di_o);

  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \G_1PIPE_IFACE.s_di_r_reg[15] ;
  input s_dwe_o;
  input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
  input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
  input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
  input [3:0]s_daddr_o;
  input [14:0]s_di_o;

  wire [0:0]E;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
  wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__36_n_0 ;
  wire \current_state[3]_i_3__36_n_0 ;
  wire \current_state[3]_i_4__36_n_0 ;
  wire data_out_sel;
  wire data_out_sel_i_1__36_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire \shadow[0]_i_1__36_n_0 ;
  wire \shadow[10]_i_1__36_n_0 ;
  wire \shadow[11]_i_1__36_n_0 ;
  wire \shadow[12]_i_1__36_n_0 ;
  wire \shadow[13]_i_1__36_n_0 ;
  wire \shadow[14]_i_1__36_n_0 ;
  wire \shadow[15]_i_1__36_n_0 ;
  wire \shadow[1]_i_1__36_n_0 ;
  wire \shadow[2]_i_1__36_n_0 ;
  wire \shadow[3]_i_1__36_n_0 ;
  wire \shadow[4]_i_1__36_n_0 ;
  wire \shadow[5]_i_1__36_n_0 ;
  wire \shadow[6]_i_1__36_n_0 ;
  wire \shadow[7]_i_1__36_n_0 ;
  wire \shadow[8]_i_1__36_n_0 ;
  wire \shadow[9]_i_1__36_n_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__36_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__36 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__36 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__36 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(clear));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__36 
       (.I0(cnt_reg[2]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[1]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__36 
       (.I0(\current_state[3]_i_4__36_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__36_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__36_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__36 
       (.I0(s_dwe_o),
        .I1(\current_state[3]_i_4__36_n_0 ),
        .I2(current_state[0]),
        .I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
        .I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__36 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__36_n_0 ),
        .I2(\current_state[3]_i_4__36_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__36 
       (.I0(\current_state[3]_i_2__36_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__36_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__36_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__36 
       (.I0(cnt_reg[2]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[1]),
        .I3(cnt_reg[3]),
        .O(\current_state[3]_i_2__36_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \current_state[3]_i_3__36 
       (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
        .O(\current_state[3]_i_3__36_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__36 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__36_n_0 ));
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__36
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__36_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__36_n_0),
        .Q(data_out_sel),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__36 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[0]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__36 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[10]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__36 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[11]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__36 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[12]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__36 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[13]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__36 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[14]_i_1__36_n_0 ));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__36 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__36 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[1]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__36 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[2]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__36 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[3]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__36 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[4]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__36 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[5]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__36 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[6]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__36 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[7]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__36 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[8]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__36 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(\shadow[9]_i_1__36_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[0]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[10]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[11]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[12]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[13]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[14]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[1]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[2]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[3]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[4]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[5]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[6]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[7]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[8]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[9]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0104)) 
    shift_en_i_1__36
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[1]),
        .I3(current_state[2]),
        .O(shift_en_i_1__36_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__36_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__35
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule