data/full_repos/permissive/180199545/DrawObject/object_test_top_tb.v
 line:47: before: "Clk_cnt"
1: b'%Warning-STMTDLY: data/full_repos/permissive/180199545/DrawObject/object_test_top_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n       #20 clk_tb = ~clk_tb;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/180199545/DrawObject/object_test_top_tb.v:47: syntax error, unexpected \'@\'\n       @(posedge clk_tb) Clk_cnt = Clk_cnt + 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/180199545/DrawObject/object_test_top_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #45;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module object_top_tb();


   reg reset_tb;
   reg clk_tb;
   reg [11:0]Clk_cnt;

	
	wire vga_h_sync_tb;
	wire vga_v_sync_tb;
	wire inDisplayArea_tb;
	wire [9:0]   CounterX_tb;
	wire [8:0]   CounterY_tb;
	


hvsync_generator UUT (
      .clk(clk_tb), 
      .reset(reset_tb),
      .vga_h_sync(vga_h_sync_tb),
      .vga_v_sync(vga_v_sync_tb),
      .inDisplayArea(inDisplayArea_tb),
      .CounterX(CounterX_tb),
      .CounterY(CounterY_tb)
   );


always
  begin  : CLK_GENERATOR
       #20 clk_tb = ~clk_tb;
end


initial
  begin  : CLK_COUNTER
    Clk_cnt = 0;
    forever
       begin
	      @(posedge clk_tb) Clk_cnt = Clk_cnt + 1;
       end 
  end
  

initial
begin
   clk_tb=0;
	reset_tb=1;
	#45;
	reset_tb=0;
	
	end
endmodule
module object_top_tb();



   reg reset_tb;
   reg clk_tb;
   reg [11:0]Clk_cnt;

	
	wire vga_h_sync_tb;
	wire vga_v_sync_tb;
	wire inDisplayArea_tb;
	wire [9:0]   CounterX_tb;
	wire [8:0]   CounterY_tb;
	


hvsync_generator UUT (
      .clk(clk_tb), 
      .reset(reset_tb),
      .vga_h_sync(vga_h_sync_tb),
      .vga_v_sync(vga_v_sync_tb),
      .inDisplayArea(inDisplayArea_tb),
      .CounterX(CounterX_tb),
      .CounterY(CounterY_tb)
   );


always
  begin  : CLK_GENERATOR
       #20 clk_tb = ~clk_tb;
end


initial
  begin  : CLK_COUNTER
    Clk_cnt = 0;
    forever
       begin
	      @(posedge clk_tb) Clk_cnt = Clk_cnt + 1;
       end 
  end
  

initial
begin
   clk_tb=0;
	reset_tb=1;
	#45;
	reset_tb=0;
	
	end
endmodule