data/full_repos/permissive/167856740/cpu/add.v
data/verilator_xmls/449abd90-7b9e-41ba-b4e2-836d9c26ce35.xml
module add(
    input [31:0] I_data1,
    input [31:0] I_data2,
    output [31:0] O_data
    );

	assign O_data = I_data1 + I_data2;	

endmodule
module add(
    input [31:0] I_data1,
    input [31:0] I_data2,
    output [31:0] O_data
    );


	assign O_data = I_data1 + I_data2;	

endmodule