data/full_repos/permissive/183345139/hba_reg_bank/hba_reg_bank.v
 line:223: before: "begin"
1: b'%Warning-WIDTH: data/full_repos/permissive/183345139/hba_reg_bank/hba_reg_bank.v:88: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'periph_addr\' generates 4 bits.\n                                                                                   : ... In instance hba_reg_bank\nwire addr_decode_hit = (periph_addr == PERIPH_ADDR) &&\n                                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/183345139/hba_reg_bank/hba_reg_bank.v:89: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'reg_addr\' generates 8 bits.\n                                                                                   : ... In instance hba_reg_bank\n    (reg_addr >= REG_OFFSET) && (reg_addr < REG_OFFSET+4);\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/183345139/hba_reg_bank/hba_reg_bank.v:89: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'reg_addr\' generates 8 bits.\n                                                                                   : ... In instance hba_reg_bank\n    (reg_addr >= REG_OFFSET) && (reg_addr < REG_OFFSET+4);\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/183345139/hba_reg_bank/hba_reg_bank.v:169: Operator CASE expects 32 bits on the Case expression, but Case expression\'s VARREF \'reg_addr\' generates 8 bits.\n                                                                                    : ... In instance hba_reg_bank\n                case(reg_addr)\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/183345139/hba_reg_bank/hba_reg_bank.v:202: Operator CASE expects 32 bits on the Case expression, but Case expression\'s VARREF \'reg_addr\' generates 8 bits.\n                                                                                    : ... In instance hba_reg_bank\n                case(reg_addr)\n                ^~~~\n%Warning-UNSIGNED: data/full_repos/permissive/183345139/hba_reg_bank/hba_reg_bank.v:89: Comparison is constant due to unsigned arithmetic\n                                                                                      : ... In instance hba_reg_bank\n    (reg_addr >= REG_OFFSET) && (reg_addr < REG_OFFSET+4);\n              ^~\n%Error: Exiting due to 6 warning(s)\n'
module hba_reg_bank #
(



    parameter integer DBUS_WIDTH = 8,
    parameter integer PERIPH_ADDR_WIDTH = 4,
    parameter integer REG_ADDR_WIDTH = 8,
    parameter integer ADDR_WIDTH = PERIPH_ADDR_WIDTH + REG_ADDR_WIDTH,
    parameter integer PERIPH_ADDR = 0,




    parameter integer REG_OFFSET = 0,
    parameter integer REG0 = REG_OFFSET,
    parameter integer REG1 = REG_OFFSET+1,
    parameter integer REG2 = REG_OFFSET+2,
    parameter integer REG3 = REG_OFFSET+3

)
(

    input wire hba_clk,
    input wire hba_reset,
    input wire hba_rnw,
    input wire hba_select,
    input wire [ADDR_WIDTH-1:0] hba_abus,
    input wire [DBUS_WIDTH-1:0] hba_dbus,

    output reg [DBUS_WIDTH-1:0] hba_dbus_slave,
    output reg hba_xferack_slave,




    output reg [DBUS_WIDTH-1:0] slv_reg0,
    output reg [DBUS_WIDTH-1:0] slv_reg1,
    output reg [DBUS_WIDTH-1:0] slv_reg2,
    output reg [DBUS_WIDTH-1:0] slv_reg3,

    input wire [DBUS_WIDTH-1:0] slv_reg0_in,
    input wire [DBUS_WIDTH-1:0] slv_reg1_in,
    input wire [DBUS_WIDTH-1:0] slv_reg2_in,
    input wire [DBUS_WIDTH-1:0] slv_reg3_in,

    input wire slv_wr_en,
    input wire [3:0] slv_wr_mask,
    input wire [3:0] slv_autoclr_mask
);



wire [REG_ADDR_WIDTH-1:0] reg_addr = hba_abus[REG_ADDR_WIDTH-1:0];

wire [PERIPH_ADDR_WIDTH-1:0] periph_addr = 
    hba_abus[ADDR_WIDTH-1:ADDR_WIDTH-PERIPH_ADDR_WIDTH];


wire addr_decode_hit = (periph_addr == PERIPH_ADDR) &&
    (reg_addr >= REG_OFFSET) && (reg_addr < REG_OFFSET+4);


wire addr_hit_clear = ~hba_select | hba_xferack_slave;

reg addr_hit;





always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        addr_hit <= 0;
    end else begin
        if (addr_hit_clear)
            addr_hit <= 0;
        else
            addr_hit <= addr_decode_hit;
    end
end


reg [7:0] regbank_state;


localparam IDLE   = 0;
localparam READ   = 1;
localparam WRITE  = 2;
localparam WAIT   = 3;

always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        regbank_state <= IDLE;
        hba_xferack_slave <= 0;
        hba_dbus_slave <= 0;
        slv_reg0 <= 0;
        slv_reg1 <= 0;
        slv_reg2 <= 0;
        slv_reg3 <= 0;
    end else begin


        if (slv_wr_en) begin
            if (slv_wr_mask[0]) begin
                slv_reg0 <= slv_reg0_in;
            end
            if (slv_wr_mask[1]) begin
                slv_reg1 <= slv_reg1_in;
            end
            if (slv_wr_mask[2]) begin
                slv_reg2 <= slv_reg2_in;
            end
            if (slv_wr_mask[3]) begin
                slv_reg3 <= slv_reg3_in;
            end
        end

        case (regbank_state)
            IDLE : begin
                hba_xferack_slave <= 0;
                hba_dbus_slave <= 0;

                if (addr_hit)
                begin
                    if (hba_rnw)
                        regbank_state <= READ;
                    else
                        regbank_state <= WRITE;
                end
            end
            READ : begin
                hba_xferack_slave <= 1;
                regbank_state <= WAIT;
                case(reg_addr)
                    REG0 : begin
                        hba_dbus_slave <= slv_reg0;
                        if (slv_autoclr_mask[0]) begin
                            slv_reg0 <= 0;
                        end
                    end
                    REG1 : begin
                        hba_dbus_slave <= slv_reg1;
                        if (slv_autoclr_mask[1]) begin
                            slv_reg1 <= 0;
                        end
                    end
                    REG2 : begin
                        hba_dbus_slave <= slv_reg2;
                        if (slv_autoclr_mask[2]) begin
                            slv_reg2 <= 0;
                        end
                    end
                    REG3 : begin
                        hba_dbus_slave <= slv_reg3;
                        if (slv_autoclr_mask[3]) begin
                            slv_reg3 <= 0;
                        end
                    end
                    default : begin
                        hba_dbus_slave <= 0;
                    end
                endcase
            end
            WRITE : begin
                hba_xferack_slave <= 1;
                regbank_state <= WAIT;
                case(reg_addr)
                    REG0 : begin
                        slv_reg0 <= hba_dbus;
                    end
                    REG1 : begin
                        slv_reg1 <= hba_dbus;
                    end
                    REG2 : begin
                        slv_reg2 <= hba_dbus;
                    end
                    REG3 : begin
                        slv_reg3 <= hba_dbus;
                    end
                    default : ;
                endcase
            end
            WAIT : begin
                regbank_state <= IDLE;
                hba_xferack_slave <= 0;
                hba_dbus_slave <= 0;
            end
            default begin
                regbank_state <= IDLE;
                hba_xferack_slave <= 0;
                hba_dbus_slave <= 0;
            end
        endcase
    end
end

endmodule
module hba_reg_bank #
(



    parameter integer DBUS_WIDTH = 8,
    parameter integer PERIPH_ADDR_WIDTH = 4,
    parameter integer REG_ADDR_WIDTH = 8,
    parameter integer ADDR_WIDTH = PERIPH_ADDR_WIDTH + REG_ADDR_WIDTH,
    parameter integer PERIPH_ADDR = 0,




    parameter integer REG_OFFSET = 0,
    parameter integer REG0 = REG_OFFSET,
    parameter integer REG1 = REG_OFFSET+1,
    parameter integer REG2 = REG_OFFSET+2,
    parameter integer REG3 = REG_OFFSET+3

)
(

    input wire hba_clk,
    input wire hba_reset,
    input wire hba_rnw,
    input wire hba_select,
    input wire [ADDR_WIDTH-1:0] hba_abus,
    input wire [DBUS_WIDTH-1:0] hba_dbus,

    output reg [DBUS_WIDTH-1:0] hba_dbus_slave,
    output reg hba_xferack_slave,




    output reg [DBUS_WIDTH-1:0] slv_reg0,
    output reg [DBUS_WIDTH-1:0] slv_reg1,
    output reg [DBUS_WIDTH-1:0] slv_reg2,
    output reg [DBUS_WIDTH-1:0] slv_reg3,

    input wire [DBUS_WIDTH-1:0] slv_reg0_in,
    input wire [DBUS_WIDTH-1:0] slv_reg1_in,
    input wire [DBUS_WIDTH-1:0] slv_reg2_in,
    input wire [DBUS_WIDTH-1:0] slv_reg3_in,

    input wire slv_wr_en,
    input wire [3:0] slv_wr_mask,
    input wire [3:0] slv_autoclr_mask
);




wire [REG_ADDR_WIDTH-1:0] reg_addr = hba_abus[REG_ADDR_WIDTH-1:0];

wire [PERIPH_ADDR_WIDTH-1:0] periph_addr = 
    hba_abus[ADDR_WIDTH-1:ADDR_WIDTH-PERIPH_ADDR_WIDTH];


wire addr_decode_hit = (periph_addr == PERIPH_ADDR) &&
    (reg_addr >= REG_OFFSET) && (reg_addr < REG_OFFSET+4);


wire addr_hit_clear = ~hba_select | hba_xferack_slave;

reg addr_hit;





always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        addr_hit <= 0;
    end else begin
        if (addr_hit_clear)
            addr_hit <= 0;
        else
            addr_hit <= addr_decode_hit;
    end
end


reg [7:0] regbank_state;


localparam IDLE   = 0;
localparam READ   = 1;
localparam WRITE  = 2;
localparam WAIT   = 3;

always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        regbank_state <= IDLE;
        hba_xferack_slave <= 0;
        hba_dbus_slave <= 0;
        slv_reg0 <= 0;
        slv_reg1 <= 0;
        slv_reg2 <= 0;
        slv_reg3 <= 0;
    end else begin


        if (slv_wr_en) begin
            if (slv_wr_mask[0]) begin
                slv_reg0 <= slv_reg0_in;
            end
            if (slv_wr_mask[1]) begin
                slv_reg1 <= slv_reg1_in;
            end
            if (slv_wr_mask[2]) begin
                slv_reg2 <= slv_reg2_in;
            end
            if (slv_wr_mask[3]) begin
                slv_reg3 <= slv_reg3_in;
            end
        end

        case (regbank_state)
            IDLE : begin
                hba_xferack_slave <= 0;
                hba_dbus_slave <= 0;

                if (addr_hit)
                begin
                    if (hba_rnw)
                        regbank_state <= READ;
                    else
                        regbank_state <= WRITE;
                end
            end
            READ : begin
                hba_xferack_slave <= 1;
                regbank_state <= WAIT;
                case(reg_addr)
                    REG0 : begin
                        hba_dbus_slave <= slv_reg0;
                        if (slv_autoclr_mask[0]) begin
                            slv_reg0 <= 0;
                        end
                    end
                    REG1 : begin
                        hba_dbus_slave <= slv_reg1;
                        if (slv_autoclr_mask[1]) begin
                            slv_reg1 <= 0;
                        end
                    end
                    REG2 : begin
                        hba_dbus_slave <= slv_reg2;
                        if (slv_autoclr_mask[2]) begin
                            slv_reg2 <= 0;
                        end
                    end
                    REG3 : begin
                        hba_dbus_slave <= slv_reg3;
                        if (slv_autoclr_mask[3]) begin
                            slv_reg3 <= 0;
                        end
                    end
                    default : begin
                        hba_dbus_slave <= 0;
                    end
                endcase
            end
            WRITE : begin
                hba_xferack_slave <= 1;
                regbank_state <= WAIT;
                case(reg_addr)
                    REG0 : begin
                        slv_reg0 <= hba_dbus;
                    end
                    REG1 : begin
                        slv_reg1 <= hba_dbus;
                    end
                    REG2 : begin
                        slv_reg2 <= hba_dbus;
                    end
                    REG3 : begin
                        slv_reg3 <= hba_dbus;
                    end
                    default : ;
                endcase
            end
            WAIT : begin
                regbank_state <= IDLE;
                hba_xferack_slave <= 0;
                hba_dbus_slave <= 0;
            end
            default begin
                regbank_state <= IDLE;
                hba_xferack_slave <= 0;
                hba_dbus_slave <= 0;
            end
        endcase
    end
end

endmodule