data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs/raisin64_nexys4_ddr_top.v
1: b'%Error: data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs/raisin64_nexys4_ddr_top.v:37: Cannot find file containing module: \'IBUFG\'\n    IBUFG clk_in_buf (.I(CLK100MHZ), .O(clk_in));\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs,data/full_repos/permissive/155005690/IBUFG\n             data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs,data/full_repos/permissive/155005690/IBUFG.v\n             data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs,data/full_repos/permissive/155005690/IBUFG.sv\n             IBUFG\n             IBUFG.v\n             IBUFG.sv\n             obj_dir/IBUFG\n             obj_dir/IBUFG.v\n             obj_dir/IBUFG.sv\n%Error: data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs/raisin64_nexys4_ddr_top.v:39: Cannot find file containing module: \'clk_synth\'\n    clk_synth dig_pll(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs/raisin64_nexys4_ddr_top.v:45: Cannot find file containing module: \'clk_vga\'\n    clk_vga vid_pll(\n    ^~~~~~~\n%Error: data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs/raisin64_nexys4_ddr_top.v:68: Cannot find file containing module: \'raisin64\'\n    raisin64 #(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs/raisin64_nexys4_ddr_top.v:107: Cannot find file containing module: \'memory_map\'\n    memory_map memory_map_external(\n    ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs/raisin64_nexys4_ddr_top.v:120: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'mem_from_cpu\' generates 64 bits.\n                                                                                                          : ... In instance raisin64_nexys4_ddr_top\n        else if(led_en & mem_from_cpu_write) led_reg <= mem_from_cpu;\n                                                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs/raisin64_nexys4_ddr_top.v:141: Cannot find file containing module: \'vgaCharGen\'\n    vgaCharGen #(\n    ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs/raisin64_nexys4_ddr_top.v:162: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'sw_pre0\' generates 16 bits.\n                                                                                                          : ... In instance raisin64_nexys4_ddr_top\n    assign mem_to_cpu = sw_en ? sw_pre0 :\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/155005690/raisin64-nexys4ddr.srcs/raisin64_nexys4_ddr_top.v:163: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'vga_dout\' generates 16 bits.\n                                                                                                          : ... In instance raisin64_nexys4_ddr_top\n                        vga_en ? vga_dout :\n                               ^\n%Error: Exiting due to 6 error(s), 3 warning(s)\n'
module raisin64_nexys4_ddr_top(
    input CLK100MHZ,
    input CPU_RESETN,
    input[15:0] SW,
    output[15:0] LED,
    inout[8:1] JB,
    output[3:0] VGA_R,
    output[3:0] VGA_G,
    output[3:0] VGA_B,
    output VGA_HS,
    output VGA_VS,


    inout[15:0] ddr2_dq,
    inout[1:0] ddr2_dqs_n,
    inout[1:0] ddr2_dqs_p,
    output[12:0] ddr2_addr,
    output[2:0] ddr2_ba,
    output ddr2_ras_n,
    output ddr2_cas_n,
    output ddr2_we_n,
    output ddr2_ck_p,
    output ddr2_ck_n,
    output ddr2_cke,
    output ddr2_cs_n,
    output[1:0] ddr2_dm,
    output ddr2_odt
    );

    localparam IMEM_INIT = "/home/christopher/git/raisin64-nexys4ddr/software/imem.hex";
    localparam DMEM_INIT = "/home/christopher/git/raisin64-nexys4ddr/software/dmem.hex";


    wire clk_cpu, clk_vga, clk_in;
    wire dig_pll_locked, vid_pll_locked;

    IBUFG clk_in_buf (.I(CLK100MHZ), .O(clk_in));

    clk_synth dig_pll(
        .locked(dig_pll_locked),
        .clk_in(clk_in),
        .clk_cpu(clk_cpu)
        );

    clk_vga vid_pll(
        .locked(vid_pll_locked),
        .clk_in(clk_in),
        .clk_vga(clk_vga)
        );


    reg[31:0] rst_stretch = 32'hFFFFFFFF;
    wire reset_req_n, rst_n;

    assign reset_req_n = CPU_RESETN & dig_pll_locked & vid_pll_locked;

    always @(posedge clk_cpu) rst_stretch = {reset_req_n,rst_stretch[31:1]};
    assign rst_n = reset_req_n & &rst_stretch;


    wire[63:0] mem_from_cpu;
    wire[63:0] mem_to_cpu;
    wire[63:0] mem_addr;
    wire mem_addr_valid;
    wire mem_from_cpu_write;
    wire mem_to_cpu_ready;

    raisin64 #(
        .IMEM_INIT(IMEM_INIT),
        .DMEM_INIT(DMEM_INIT)
        ) cpu (
        .clk(clk_cpu),
        .clk_100mhz(clk_in),
        .rst_n(rst_n),

        .mem_din(mem_to_cpu),
        .mem_dout(mem_from_cpu),
        .mem_addr(mem_addr),
        .mem_addr_valid(mem_addr_valid),
        .mem_dout_write(mem_from_cpu_write),
        .mem_din_ready(mem_to_cpu_ready),

        .ddr2_addr(ddr2_addr),
        .ddr2_ba(ddr2_ba),
        .ddr2_cas_n(ddr2_cas_n),
        .ddr2_ck_n(ddr2_ck_n),
        .ddr2_ck_p(ddr2_ck_p),
        .ddr2_cke(ddr2_cke),
        .ddr2_ras_n(ddr2_ras_n),
        .ddr2_we_n(ddr2_we_n),
        .ddr2_dq(ddr2_dq),
        .ddr2_dqs_n(ddr2_dqs_n),
        .ddr2_dqs_p(ddr2_dqs_p),
        .ddr2_cs_n(ddr2_cs_n),
        .ddr2_dm(ddr2_dm),
        .ddr2_odt(ddr2_odt),

        .jtag_tck(JB[4]),
        .jtag_tms(JB[1]),
        .jtag_tdi(JB[2]),
        .jtag_trst(JB[7]),
        .jtag_tdo(JB[3])
        );


    wire led_en, sw_en, vga_en;
    memory_map memory_map_external(
        .addr(mem_addr_valid ? mem_addr : 64'h0),
        .led(led_en),
        .sw(sw_en),
        .vga(vga_en)
        );




    reg[15:0] led_reg;
    always @(posedge clk_cpu or negedge rst_n) begin
        if(~rst_n) led_reg <= 16'h0;
        else if(led_en & mem_from_cpu_write) led_reg <= mem_from_cpu;
    end

    assign LED[15:0] = led_reg;


    reg[15:0] sw_pre0, sw_pre1;
    always @(posedge clk_cpu or negedge rst_n) begin
        if(~rst_n) begin
            sw_pre0 <= 16'h0;
            sw_pre1 <= 16'h0;
        end else begin
            sw_pre0 <= sw_pre1;
            sw_pre1 <= SW;
        end
    end


    wire[15:0] vga_dout;


    vgaCharGen #(
        .SINGLE_CYCLE_DESIGN(0)
        ) vga_cg(
        .pixel_clk(clk_vga),
        .rst_p(~rst_n),
        .pixel_clkEn(1'b1),
        .cpu_clk(clk_cpu),
        .cpu_addr(mem_addr[18:3]),
        .cpu_oe(vga_en),
        .cpu_we(vga_en & mem_from_cpu_write),
        .cpu_dataIn(mem_from_cpu[15:0]),
        .cpu_dataOut(vga_dout),
        .VGA_R(VGA_R),
        .VGA_G(VGA_G),
        .VGA_B(VGA_B),
        .VGA_HS(VGA_HS),
        .VGA_VS(VGA_VS)
        );


    assign mem_to_cpu_ready = mem_addr_valid;
    assign mem_to_cpu = sw_en ? sw_pre0 :
                        vga_en ? vga_dout :
                        64'h0;

endmodule
module raisin64_nexys4_ddr_top(
    input CLK100MHZ,
    input CPU_RESETN,
    input[15:0] SW,
    output[15:0] LED,
    inout[8:1] JB,
    output[3:0] VGA_R,
    output[3:0] VGA_G,
    output[3:0] VGA_B,
    output VGA_HS,
    output VGA_VS,


    inout[15:0] ddr2_dq,
    inout[1:0] ddr2_dqs_n,
    inout[1:0] ddr2_dqs_p,
    output[12:0] ddr2_addr,
    output[2:0] ddr2_ba,
    output ddr2_ras_n,
    output ddr2_cas_n,
    output ddr2_we_n,
    output ddr2_ck_p,
    output ddr2_ck_n,
    output ddr2_cke,
    output ddr2_cs_n,
    output[1:0] ddr2_dm,
    output ddr2_odt
    );


    localparam IMEM_INIT = "/home/christopher/git/raisin64-nexys4ddr/software/imem.hex";
    localparam DMEM_INIT = "/home/christopher/git/raisin64-nexys4ddr/software/dmem.hex";


    wire clk_cpu, clk_vga, clk_in;
    wire dig_pll_locked, vid_pll_locked;

    IBUFG clk_in_buf (.I(CLK100MHZ), .O(clk_in));

    clk_synth dig_pll(
        .locked(dig_pll_locked),
        .clk_in(clk_in),
        .clk_cpu(clk_cpu)
        );

    clk_vga vid_pll(
        .locked(vid_pll_locked),
        .clk_in(clk_in),
        .clk_vga(clk_vga)
        );


    reg[31:0] rst_stretch = 32'hFFFFFFFF;
    wire reset_req_n, rst_n;

    assign reset_req_n = CPU_RESETN & dig_pll_locked & vid_pll_locked;

    always @(posedge clk_cpu) rst_stretch = {reset_req_n,rst_stretch[31:1]};
    assign rst_n = reset_req_n & &rst_stretch;


    wire[63:0] mem_from_cpu;
    wire[63:0] mem_to_cpu;
    wire[63:0] mem_addr;
    wire mem_addr_valid;
    wire mem_from_cpu_write;
    wire mem_to_cpu_ready;

    raisin64 #(
        .IMEM_INIT(IMEM_INIT),
        .DMEM_INIT(DMEM_INIT)
        ) cpu (
        .clk(clk_cpu),
        .clk_100mhz(clk_in),
        .rst_n(rst_n),

        .mem_din(mem_to_cpu),
        .mem_dout(mem_from_cpu),
        .mem_addr(mem_addr),
        .mem_addr_valid(mem_addr_valid),
        .mem_dout_write(mem_from_cpu_write),
        .mem_din_ready(mem_to_cpu_ready),

        .ddr2_addr(ddr2_addr),
        .ddr2_ba(ddr2_ba),
        .ddr2_cas_n(ddr2_cas_n),
        .ddr2_ck_n(ddr2_ck_n),
        .ddr2_ck_p(ddr2_ck_p),
        .ddr2_cke(ddr2_cke),
        .ddr2_ras_n(ddr2_ras_n),
        .ddr2_we_n(ddr2_we_n),
        .ddr2_dq(ddr2_dq),
        .ddr2_dqs_n(ddr2_dqs_n),
        .ddr2_dqs_p(ddr2_dqs_p),
        .ddr2_cs_n(ddr2_cs_n),
        .ddr2_dm(ddr2_dm),
        .ddr2_odt(ddr2_odt),

        .jtag_tck(JB[4]),
        .jtag_tms(JB[1]),
        .jtag_tdi(JB[2]),
        .jtag_trst(JB[7]),
        .jtag_tdo(JB[3])
        );


    wire led_en, sw_en, vga_en;
    memory_map memory_map_external(
        .addr(mem_addr_valid ? mem_addr : 64'h0),
        .led(led_en),
        .sw(sw_en),
        .vga(vga_en)
        );




    reg[15:0] led_reg;
    always @(posedge clk_cpu or negedge rst_n) begin
        if(~rst_n) led_reg <= 16'h0;
        else if(led_en & mem_from_cpu_write) led_reg <= mem_from_cpu;
    end

    assign LED[15:0] = led_reg;


    reg[15:0] sw_pre0, sw_pre1;
    always @(posedge clk_cpu or negedge rst_n) begin
        if(~rst_n) begin
            sw_pre0 <= 16'h0;
            sw_pre1 <= 16'h0;
        end else begin
            sw_pre0 <= sw_pre1;
            sw_pre1 <= SW;
        end
    end


    wire[15:0] vga_dout;


    vgaCharGen #(
        .SINGLE_CYCLE_DESIGN(0)
        ) vga_cg(
        .pixel_clk(clk_vga),
        .rst_p(~rst_n),
        .pixel_clkEn(1'b1),
        .cpu_clk(clk_cpu),
        .cpu_addr(mem_addr[18:3]),
        .cpu_oe(vga_en),
        .cpu_we(vga_en & mem_from_cpu_write),
        .cpu_dataIn(mem_from_cpu[15:0]),
        .cpu_dataOut(vga_dout),
        .VGA_R(VGA_R),
        .VGA_G(VGA_G),
        .VGA_B(VGA_B),
        .VGA_HS(VGA_HS),
        .VGA_VS(VGA_VS)
        );


    assign mem_to_cpu_ready = mem_addr_valid;
    assign mem_to_cpu = sw_en ? sw_pre0 :
                        vga_en ? vga_dout :
                        64'h0;

endmodule