data/full_repos/permissive/134871193/sort2.v
 line:70: before: "end"
1: b"%Error: data/full_repos/permissive/134871193/sort2.v:19: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\nreg [width-1:0] sequence ;\n                ^~~~~~~~\n%Error: data/full_repos/permissive/134871193/sort2.v:19: syntax error, unexpected ';', expecting IDENTIFIER or '=' or do or final\nreg [width-1:0] sequence ;\n                         ^\n%Error: data/full_repos/permissive/134871193/sort2.v:45: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n  sequence = p1 ;\n  ^~~~~~~~\n%Error: data/full_repos/permissive/134871193/sort2.v:45: syntax error, unexpected '='\n  sequence = p1 ;\n           ^\n%Error: data/full_repos/permissive/134871193/sort2.v:47: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n  sequence = p2 ;\n  ^~~~~~~~\n%Error: data/full_repos/permissive/134871193/sort2.v:47: syntax error, unexpected '='\n  sequence = p2 ;\n           ^\n%Error: data/full_repos/permissive/134871193/sort2.v:49: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n  sequence = p3 ;\n  ^~~~~~~~\n%Error: data/full_repos/permissive/134871193/sort2.v:49: syntax error, unexpected '='\n  sequence = p3 ;\n           ^\n%Error: data/full_repos/permissive/134871193/sort2.v:51: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n  sequence = p4 ;\n  ^~~~~~~~\n%Error: data/full_repos/permissive/134871193/sort2.v:51: syntax error, unexpected '='\n  sequence = p4 ;\n           ^\n%Error: data/full_repos/permissive/134871193/sort2.v:53: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n  sequence = p5 ;\n  ^~~~~~~~\n%Error: data/full_repos/permissive/134871193/sort2.v:53: syntax error, unexpected '='\n  sequence = p5 ;\n           ^\n%Error: data/full_repos/permissive/134871193/sort2.v:55: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n  sequence = p6 ;\n  ^~~~~~~~\n%Error: data/full_repos/permissive/134871193/sort2.v:55: syntax error, unexpected '='\n  sequence = p6 ;\n           ^\n%Error: data/full_repos/permissive/134871193/sort2.v:57: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\nalways@(sequence) \n        ^~~~~~~~\n%Error: data/full_repos/permissive/134871193/sort2.v:57: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\nalways@(sequence) \n                ^\n%Error: data/full_repos/permissive/134871193/sort2.v:58: Unsupported: SystemVerilog 2005 reserved word not implemented: 'sequence'\n case(sequence)\n      ^~~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n"
module sort2(no1,no2,no3,a,b,c,clk,rst);
parameter width=3;
output[width-1:0] no1,no2,no3;
input clk,rst;
input[width-1:0] a,b,c;

reg [width-1:0] no1,no2,no3;
reg [width-1:0] no_1,no_2,no_3;
reg [width-1:0] op1 = 3'b000;
reg [width-1:0] op2 = 3'b000;
reg [width-1:0] op3 = 3'b000;

parameter p1 = 3'b000;
parameter p2 = 3'b001;
parameter p3 = 3'b011;
parameter p4 = 3'b010;
parameter p5 = 3'b110;
parameter p6 = 3'b111;
reg [width-1:0] sequence ;

always@(posedge clk or posedge rst)
begin
	if(rst)
	begin
		no1<=3'b000;
		no2<=3'b000;
		no3<=3'b000;
	end
	else begin
		no1<=no_1;
		no2<=no_2;
		no3<=no_3;
	     end
end

always@(a or b or c)
begin
	op1 = a ;
	op2 = b ;
	op3 = c ;
end
always@(op1 or op2 or op3)
begin
	     if(op1>=op2&&op2>=op3)
		sequence = p1 ;
	else if (op1>=op3&&op3>op2)
		sequence = p2 ;
	else if (op2>op1&&op1>=op3)
		sequence = p3 ;
	else if (op2>=op3&&op3>op1)
		sequence = p4 ;
	else if (op3>op1&&op1>=op2)
		sequence = p5 ;
	else if (op3>op2&&op2>op1)
		sequence = p6 ;
end
always@(sequence)	
	case(sequence)

	p1:  begin no_1=op1;no_2=op2;no_3=op3; end
	p2:  begin no_1=op1;no_2=op3;no_3=op2; end
	p3:  begin no_1=op2;no_2=op1;no_3=op3; end
	p4:  begin no_1=op2;no_2=op3;no_3=op1; end
	p5:  begin no_1=op3;no_2=op1;no_3=op2; end
	p6:  begin no_1=op3;no_2=op2;no_3=op1; end

	default:  begin no_1=no_1;no_2=no_2;no_3=no_3; end

	endcase
end


endmodule
module sort2(no1,no2,no3,a,b,c,clk,rst);

parameter width=3;
output[width-1:0] no1,no2,no3;
input clk,rst;
input[width-1:0] a,b,c;

reg [width-1:0] no1,no2,no3;
reg [width-1:0] no_1,no_2,no_3;
reg [width-1:0] op1 = 3'b000;
reg [width-1:0] op2 = 3'b000;
reg [width-1:0] op3 = 3'b000;

parameter p1 = 3'b000;
parameter p2 = 3'b001;
parameter p3 = 3'b011;
parameter p4 = 3'b010;
parameter p5 = 3'b110;
parameter p6 = 3'b111;
reg [width-1:0] sequence ;

always@(posedge clk or posedge rst)
begin
	if(rst)
	begin
		no1<=3'b000;
		no2<=3'b000;
		no3<=3'b000;
	end
	else begin
		no1<=no_1;
		no2<=no_2;
		no3<=no_3;
	     end
end

always@(a or b or c)
begin
	op1 = a ;
	op2 = b ;
	op3 = c ;
end
always@(op1 or op2 or op3)
begin
	     if(op1>=op2&&op2>=op3)
		sequence = p1 ;
	else if (op1>=op3&&op3>op2)
		sequence = p2 ;
	else if (op2>op1&&op1>=op3)
		sequence = p3 ;
	else if (op2>=op3&&op3>op1)
		sequence = p4 ;
	else if (op3>op1&&op1>=op2)
		sequence = p5 ;
	else if (op3>op2&&op2>op1)
		sequence = p6 ;
end
always@(sequence)	
	case(sequence)

	p1:  begin no_1=op1;no_2=op2;no_3=op3; end
	p2:  begin no_1=op1;no_2=op3;no_3=op2; end
	p3:  begin no_1=op2;no_2=op1;no_3=op3; end
	p4:  begin no_1=op2;no_2=op3;no_3=op1; end
	p5:  begin no_1=op3;no_2=op1;no_3=op2; end
	p6:  begin no_1=op3;no_2=op2;no_3=op1; end

	default:  begin no_1=no_1;no_2=no_2;no_3=no_3; end

	endcase
end


endmodule