data/full_repos/permissive/116476954/mux.v
data/verilator_xmls/b0c0dba9-b749-4fe1-b37a-f54a859e01f2.xml
module mux2_1(adir, adpc, fch, admem);

input [4:0] adir;
input [4:0] adpc;
input fch;
output [4:0] admem;

reg [4:0] admem;

    always @ (fch,adpc,adir) begin
        
        case (fch)
            1'b1 : admem = adpc; 
          
            1'b0 : admem = adir;
        endcase
    end

endmodule
module mux2_1(adir, adpc, fch, admem);


input [4:0] adir;
input [4:0] adpc;
input fch;
output [4:0] admem;

reg [4:0] admem;

    always @ (fch,adpc,adir) begin
        
        case (fch)
            1'b1 : admem = adpc; 
          
            1'b0 : admem = adir;
        endcase
    end

endmodule