data/full_repos/permissive/114642806/main/fsm.v
data/verilator_xmls/8216b74a-c713-42da-893a-45763aa7c526.xml
module counter10s(CLOCK_50, enable);
	input CLOCK_50;
	output enable;
	wire enable_second_counter;
	counter01 u2(CLOCK_50, enable_second_counter);
	counter10pos u5(enable_second_counter, enable);
endmodule
module counter10s(CLOCK_50, enable);

	input CLOCK_50;
	output enable;
	wire enable_second_counter;
	counter01 u2(CLOCK_50, enable_second_counter);
	counter10pos u5(enable_second_counter, enable);
endmodule