data/full_repos/permissive/205926239/ISE_project/keyboard_clock.v
data/verilator_xmls/e6fe0b74-13b7-442d-9db4-b0bd5f0ca763.xml
module keyboard_clock(clk, clk_kbd);
    input clk;
    output clk_kbd;

	reg [23:0] counter;
	
	always @(posedge clk)
		counter<=counter+1;
		
	assign clk_kbd = counter[23];
	
	
endmodule
module keyboard_clock(clk, clk_kbd);

    input clk;
    output clk_kbd;

	reg [23:0] counter;
	
	always @(posedge clk)
		counter<=counter+1;
		
	assign clk_kbd = counter[23];
	
	
endmodule