data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v
None: at end of input
1: b'%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:22: Cannot find include file: top_defines.vh\n`include "top_defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159016511/src/rtl/tcm,data/full_repos/permissive/159016511/top_defines.vh\n             data/full_repos/permissive/159016511/src/rtl/tcm,data/full_repos/permissive/159016511/top_defines.vh.v\n             data/full_repos/permissive/159016511/src/rtl/tcm,data/full_repos/permissive/159016511/top_defines.vh.sv\n             top_defines.vh\n             top_defines.vh.v\n             top_defines.vh.sv\n             obj_dir/top_defines.vh\n             obj_dir/top_defines.vh.v\n             obj_dir/top_defines.vh.sv\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:23: Cannot find include file: core_defines.vh\n`include "core_defines.vh" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:34: Define or directive not defined: \'`ADDR_WIDTH\'\n input [`ADDR_WIDTH - 1 : 0] data_dtcm_addr,   \n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:35: Define or directive not defined: \'`DATA_WIDTH\'\n input wire [`DATA_WIDTH - 1 : 0] data_dtcm_wdata,  \n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:36: Define or directive not defined: \'`DATA_WIDTH\'\n output wire [`DATA_WIDTH - 1 : 0] data_dtcm_rdata,  \n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:41: Define or directive not defined: \'`ADDR_WIDTH\'\n input [`ADDR_WIDTH - 1 : 0] instr_dtcm_addr,   \n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:42: Define or directive not defined: \'`DATA_WIDTH\'\n output wire [`DATA_WIDTH - 1 : 0] instr_dtcm_rdata,  \n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:49: Define or directive not defined: \'`ADDR_WIDTH\'\n input [`ADDR_WIDTH - 1 : 0] dma_dtcm_addr,   \n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:50: Define or directive not defined: \'`DATA_WIDTH\'\n input wire [`DATA_WIDTH - 1 : 0] dma_dtcm_wdata,  \n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:51: Define or directive not defined: \'`DATA_WIDTH\'\n output wire [`DATA_WIDTH - 1 : 0] dma_dtcm_rdata,  \n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:63: Define or directive not defined: \'`ADDR_WIDTH\'\n wire [`ADDR_WIDTH - 1 : 0] dtcm_addr; \n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:64: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH - 1 : 0] dtcm_wdata; \n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159016511/src/rtl/tcm/dtcm.v:77: Define or directive not defined: \'`DATA_WIDTH\'\nwire [`DATA_WIDTH - 1 : 0] dtcm_rdata;\n      ^~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module dtcm (

	input clk,
	input rstn,


	input data_dtcm_access,
	output wire data_dtcm_ready,
	input data_dtcm_rd0_wr1,
	input wire [3:0] data_dtcm_byte_strobe,
	input [`ADDR_WIDTH - 1 : 0] data_dtcm_addr,
	input wire [`DATA_WIDTH - 1 : 0] data_dtcm_wdata,
	output wire [`DATA_WIDTH - 1 : 0] data_dtcm_rdata,
	output reg data_dtcm_rdata_valid,


	input instr_dtcm_access,
	input [`ADDR_WIDTH - 1 : 0] instr_dtcm_addr,
	output wire [`DATA_WIDTH - 1 : 0] instr_dtcm_rdata,
	output reg instr_dtcm_rdata_valid,


	input dma_dtcm_access,
	output wire dma_dtcm_ready,
	input dma_dtcm_rd0_wr1,
	input [`ADDR_WIDTH - 1 : 0] dma_dtcm_addr,
	input wire [`DATA_WIDTH - 1 : 0] dma_dtcm_wdata,
	output wire [`DATA_WIDTH - 1 : 0] dma_dtcm_rdata,
	output reg dma_dtcm_rdata_valid

);





	wire dtcm_access;			
	wire dtcm_rd0_wr1;		
	wire dtcm_wen;
	wire [`ADDR_WIDTH - 1 : 0] dtcm_addr;	
	wire [`DATA_WIDTH - 1 : 0] dtcm_wdata;	

	assign dtcm_access = data_dtcm_access || dma_dtcm_access;
	assign dtcm_rd0_wr1 = data_dtcm_rd0_wr1 || dma_dtcm_rd0_wr1;
	assign dtcm_wen = dtcm_access & dtcm_rd0_wr1;
	assign dtcm_addr = dma_dtcm_access? dma_dtcm_addr : (data_dtcm_access? data_dtcm_addr : instr_dtcm_addr);
	assign dtcm_wdata = dma_dtcm_access? dma_dtcm_wdata : data_dtcm_wdata;

	assign data_dtcm_ready = (!(dma_dtcm_access && dma_dtcm_rd0_wr1)) || (!data_dtcm_rd0_wr1 && (!(dma_dtcm_access && dma_dtcm_rd0_wr1 && (dma_dtcm_addr == data_dtcm_addr)))) ;
	assign dma_dtcm_ready = dma_dtcm_access;

wire[14 : 2] dtcm_word_addr = dtcm_addr[14 : 2];
`ifndef SIM
wire [`DATA_WIDTH - 1 : 0] dtcm_rdata;
sram_4Kx32 dtcm (
    .CLK	(clk),
    .RADDR	(dtcm_word_addr),
    .WADDR	(dtcm_word_addr),
    .WD		(dtcm_wdata),
    .WEN	(dtcm_wen),
    .RD		(dtcm_rdata)
);
`else
reg [`DATA_WIDTH - 1 : 0] dtcm [`DTCM_SIZE - 1 : 0];
always @ (posedge clk or negedge rstn)
begin
	if(dtcm_wen)
	begin
		if(data_dtcm_byte_strobe[3])
			dtcm[dtcm_word_addr][31:24] <= dtcm_wdata[31:24];
		if(data_dtcm_byte_strobe[2])
			dtcm[dtcm_word_addr][23:16] <= dtcm_wdata[23:16];
		if(data_dtcm_byte_strobe[1])
			dtcm[dtcm_word_addr][15:8]  <= dtcm_wdata[15:8];
		if(data_dtcm_byte_strobe[0])
			dtcm[dtcm_word_addr][7:0]   <= dtcm_wdata[7:0];
	end

end

reg [`DATA_WIDTH - 1 : 0] dtcm_rdata;
always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		dtcm_rdata <= 32'h0;
	end
	else
	begin
		dtcm_rdata <= dtcm[dtcm_word_addr];
	end
end
`endif

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		data_dtcm_rdata_valid <= 1'b0;
	end
	else
	begin
		data_dtcm_rdata_valid <= data_dtcm_access & (!data_dtcm_rd0_wr1);
	end
end

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		instr_dtcm_rdata_valid <= 1'b0;
	end
	else
	begin
		instr_dtcm_rdata_valid <= instr_dtcm_access && !data_dtcm_access;
	end
end


always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		dma_dtcm_rdata_valid <= 1'b0;
	end
	else
	begin
		dma_dtcm_rdata_valid <= dma_dtcm_access & (!dma_dtcm_rd0_wr1);
	end
end



assign data_dtcm_rdata = dtcm_rdata;

assign instr_dtcm_rdata = dtcm_rdata;

assign dma_dtcm_rdata = dtcm_rdata;


endmodule
module dtcm (

	input clk,
	input rstn,


	input data_dtcm_access,
	output wire data_dtcm_ready,
	input data_dtcm_rd0_wr1,
	input wire [3:0] data_dtcm_byte_strobe,
	input [`ADDR_WIDTH - 1 : 0] data_dtcm_addr,
	input wire [`DATA_WIDTH - 1 : 0] data_dtcm_wdata,
	output wire [`DATA_WIDTH - 1 : 0] data_dtcm_rdata,
	output reg data_dtcm_rdata_valid,


	input instr_dtcm_access,
	input [`ADDR_WIDTH - 1 : 0] instr_dtcm_addr,
	output wire [`DATA_WIDTH - 1 : 0] instr_dtcm_rdata,
	output reg instr_dtcm_rdata_valid,


	input dma_dtcm_access,
	output wire dma_dtcm_ready,
	input dma_dtcm_rd0_wr1,
	input [`ADDR_WIDTH - 1 : 0] dma_dtcm_addr,
	input wire [`DATA_WIDTH - 1 : 0] dma_dtcm_wdata,
	output wire [`DATA_WIDTH - 1 : 0] dma_dtcm_rdata,
	output reg dma_dtcm_rdata_valid

);






	wire dtcm_access;			
	wire dtcm_rd0_wr1;		
	wire dtcm_wen;
	wire [`ADDR_WIDTH - 1 : 0] dtcm_addr;	
	wire [`DATA_WIDTH - 1 : 0] dtcm_wdata;	

	assign dtcm_access = data_dtcm_access || dma_dtcm_access;
	assign dtcm_rd0_wr1 = data_dtcm_rd0_wr1 || dma_dtcm_rd0_wr1;
	assign dtcm_wen = dtcm_access & dtcm_rd0_wr1;
	assign dtcm_addr = dma_dtcm_access? dma_dtcm_addr : (data_dtcm_access? data_dtcm_addr : instr_dtcm_addr);
	assign dtcm_wdata = dma_dtcm_access? dma_dtcm_wdata : data_dtcm_wdata;

	assign data_dtcm_ready = (!(dma_dtcm_access && dma_dtcm_rd0_wr1)) || (!data_dtcm_rd0_wr1 && (!(dma_dtcm_access && dma_dtcm_rd0_wr1 && (dma_dtcm_addr == data_dtcm_addr)))) ;
	assign dma_dtcm_ready = dma_dtcm_access;

wire[14 : 2] dtcm_word_addr = dtcm_addr[14 : 2];
`ifndef SIM
wire [`DATA_WIDTH - 1 : 0] dtcm_rdata;
sram_4Kx32 dtcm (
    .CLK	(clk),
    .RADDR	(dtcm_word_addr),
    .WADDR	(dtcm_word_addr),
    .WD		(dtcm_wdata),
    .WEN	(dtcm_wen),
    .RD		(dtcm_rdata)
);
`else
reg [`DATA_WIDTH - 1 : 0] dtcm [`DTCM_SIZE - 1 : 0];
always @ (posedge clk or negedge rstn)
begin
	if(dtcm_wen)
	begin
		if(data_dtcm_byte_strobe[3])
			dtcm[dtcm_word_addr][31:24] <= dtcm_wdata[31:24];
		if(data_dtcm_byte_strobe[2])
			dtcm[dtcm_word_addr][23:16] <= dtcm_wdata[23:16];
		if(data_dtcm_byte_strobe[1])
			dtcm[dtcm_word_addr][15:8]  <= dtcm_wdata[15:8];
		if(data_dtcm_byte_strobe[0])
			dtcm[dtcm_word_addr][7:0]   <= dtcm_wdata[7:0];
	end

end

reg [`DATA_WIDTH - 1 : 0] dtcm_rdata;
always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		dtcm_rdata <= 32'h0;
	end
	else
	begin
		dtcm_rdata <= dtcm[dtcm_word_addr];
	end
end
`endif

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		data_dtcm_rdata_valid <= 1'b0;
	end
	else
	begin
		data_dtcm_rdata_valid <= data_dtcm_access & (!data_dtcm_rd0_wr1);
	end
end

always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		instr_dtcm_rdata_valid <= 1'b0;
	end
	else
	begin
		instr_dtcm_rdata_valid <= instr_dtcm_access && !data_dtcm_access;
	end
end


always @ (posedge clk or negedge rstn)
begin
	if(!rstn)
	begin
		dma_dtcm_rdata_valid <= 1'b0;
	end
	else
	begin
		dma_dtcm_rdata_valid <= dma_dtcm_access & (!dma_dtcm_rd0_wr1);
	end
end



assign data_dtcm_rdata = dtcm_rdata;

assign instr_dtcm_rdata = dtcm_rdata;

assign dma_dtcm_rdata = dtcm_rdata;


endmodule