data/full_repos/permissive/205673649/BIP/Source/instruction_decoder.v
data/verilator_xmls/270bff74-4a20-445a-b902-5894f5186610.xml
module instruction_decoder
#(
    parameter NB_OPCODE = 5,
    parameter NB_DECODER_SEL_A = 2
)
(
    input [NB_OPCODE-1:0] i_opcode,
    output reg o_wrPc,
    output reg [NB_DECODER_SEL_A-1:0] o_selA,
    output reg o_selB,
    output reg o_wrAcc,
    output reg [NB_OPCODE-1:0] o_op,
    output reg o_wrRam,
    output reg o_rdRam
);
always @(*)
begin
    case(i_opcode)
        5'b00000:
        begin
            o_wrPc = 0;
            o_selA = 0;
            o_selB = 0;
            o_wrAcc = 0;
            o_op = i_opcode;
            o_wrRam = 0;
            o_rdRam = 0;
        end
        5'b00001:
        begin
           o_wrPc = 1;
           o_selA = 0;
           o_selB = 0;
           o_wrAcc = 0;
           o_op = i_opcode;
           o_wrRam = 1; 
           o_rdRam = 0;
        end
        5'b00010:
        begin
           o_wrPc = 1;
           o_selA = 0;
           o_selB = 0;
           o_wrAcc = 1;
           o_op = i_opcode;
           o_wrRam = 0;
           o_rdRam = 1; 
        end
        5'b00011:
        begin
           o_wrPc = 1;
           o_selA = 1;
           o_selB = 0;
           o_wrAcc = 1;
           o_op = i_opcode;
           o_wrRam = 0;
           o_rdRam = 0;
        end
        5'b00100:
        begin
           o_wrPc = 1;
           o_selA = 2;
           o_selB = 0;
           o_wrAcc = 1;
           o_op = i_opcode;
           o_wrRam = 0;
           o_rdRam = 1;
        end
        5'b00101:
        begin
            o_wrPc = 1;
            o_selA = 2;
            o_selB = 1;
            o_wrAcc = 1;
            o_op = i_opcode;
            o_wrRam = 0;
            o_rdRam = 0; 
        end
        5'b00110:
        begin
            o_wrPc = 1;
            o_selA = 2;
            o_selB = 0;
            o_wrAcc = 1;
            o_op = i_opcode;
            o_wrRam = 0;
            o_rdRam = 1; 
        end
        5'b00111:
        begin
            o_wrPc = 1;
            o_selA = 2;
            o_selB = 1;
            o_wrAcc = 1;
            o_op = i_opcode;
            o_wrRam = 0;
            o_rdRam = 0; 
        end
        default:
        begin
            o_wrPc = 0;
            o_selA = 0;
            o_selB = 0;
            o_wrAcc = 0;
            o_op = 0;
            o_wrRam= 0;
            o_rdRam= 0;
        end
    endcase
end
endmodule
module instruction_decoder
#(
    parameter NB_OPCODE = 5,
    parameter NB_DECODER_SEL_A = 2
)
(
    input [NB_OPCODE-1:0] i_opcode,
    output reg o_wrPc,
    output reg [NB_DECODER_SEL_A-1:0] o_selA,
    output reg o_selB,
    output reg o_wrAcc,
    output reg [NB_OPCODE-1:0] o_op,
    output reg o_wrRam,
    output reg o_rdRam
);

always @(*)
begin
    case(i_opcode)
        5'b00000:
        begin
            o_wrPc = 0;
            o_selA = 0;
            o_selB = 0;
            o_wrAcc = 0;
            o_op = i_opcode;
            o_wrRam = 0;
            o_rdRam = 0;
        end
        5'b00001:
        begin
           o_wrPc = 1;
           o_selA = 0;
           o_selB = 0;
           o_wrAcc = 0;
           o_op = i_opcode;
           o_wrRam = 1; 
           o_rdRam = 0;
        end
        5'b00010:
        begin
           o_wrPc = 1;
           o_selA = 0;
           o_selB = 0;
           o_wrAcc = 1;
           o_op = i_opcode;
           o_wrRam = 0;
           o_rdRam = 1; 
        end
        5'b00011:
        begin
           o_wrPc = 1;
           o_selA = 1;
           o_selB = 0;
           o_wrAcc = 1;
           o_op = i_opcode;
           o_wrRam = 0;
           o_rdRam = 0;
        end
        5'b00100:
        begin
           o_wrPc = 1;
           o_selA = 2;
           o_selB = 0;
           o_wrAcc = 1;
           o_op = i_opcode;
           o_wrRam = 0;
           o_rdRam = 1;
        end
        5'b00101:
        begin
            o_wrPc = 1;
            o_selA = 2;
            o_selB = 1;
            o_wrAcc = 1;
            o_op = i_opcode;
            o_wrRam = 0;
            o_rdRam = 0; 
        end
        5'b00110:
        begin
            o_wrPc = 1;
            o_selA = 2;
            o_selB = 0;
            o_wrAcc = 1;
            o_op = i_opcode;
            o_wrRam = 0;
            o_rdRam = 1; 
        end
        5'b00111:
        begin
            o_wrPc = 1;
            o_selA = 2;
            o_selB = 1;
            o_wrAcc = 1;
            o_op = i_opcode;
            o_wrRam = 0;
            o_rdRam = 0; 
        end
        default:
        begin
            o_wrPc = 0;
            o_selA = 0;
            o_selB = 0;
            o_wrAcc = 0;
            o_op = 0;
            o_wrRam= 0;
            o_rdRam= 0;
        end
    endcase
end
endmodule