data/full_repos/permissive/138473269/rtl/mano_cache.v
Syntax Error
1: b'%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:5: Cannot find include file: rtl/basic_params.v\n`include "rtl/basic_params.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138473269/rtl,data/full_repos/permissive/138473269/rtl/basic_params.v\n             data/full_repos/permissive/138473269/rtl,data/full_repos/permissive/138473269/rtl/basic_params.v.v\n             data/full_repos/permissive/138473269/rtl,data/full_repos/permissive/138473269/rtl/basic_params.v.sv\n             rtl/basic_params.v\n             rtl/basic_params.v.v\n             rtl/basic_params.v.sv\n             obj_dir/rtl/basic_params.v\n             obj_dir/rtl/basic_params.v.v\n             obj_dir/rtl/basic_params.v.sv\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:20: Define or directive not defined: \'`addrwidth\'\n input [`addrwidth-1:0] cpu_addr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:21: Define or directive not defined: \'`datawidth\'\n input [`datawidth-1:0] cpu_din ;   \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:22: Define or directive not defined: \'`datawidth\'\n output [`datawidth-1:0] cpu_dout;  \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:23: Define or directive not defined: \'`datawidth\'\n reg   [`datawidth-1:0] cpu_dout;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:33: Define or directive not defined: \'`addrwidth\'\n output [`addrwidth-1:0] mem_addr;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:34: Define or directive not defined: \'`addrwidth\'\n reg     [`addrwidth-1:0] mem_addr;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:35: Define or directive not defined: \'`datawidth\'\n input [`datawidth-1:0] mem_din ;   \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:36: Define or directive not defined: \'`datawidth\'\n output [`datawidth-1:0] mem_dout;   \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:37: Define or directive not defined: \'`datawidth\'\n reg   [`datawidth-1:0] mem_dout;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:40: Define or directive not defined: \'`cachewidth\'\n reg [`cachewidth-1:0] cacheBank [0:`cachecap-1];\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:40: Define or directive not defined: \'`cachecap\'\n reg [`cachewidth-1:0] cacheBank [0:`cachecap-1];\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:41: Define or directive not defined: \'`cachewidth\'\n reg [`cachewidth-1:0] zero = 0;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:57: Define or directive not defined: \'`cachewidth\'\n  for (i = 0; i < `cachewidth; i = i+1) begin\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:57: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  for (i = 0; i < `cachewidth; i = i+1) begin\n                             ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:57: syntax error, unexpected \')\', expecting \';\'\n  for (i = 0; i < `cachewidth; i = i+1) begin\n                                      ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:71: syntax error, unexpected \'=\', expecting IDENTIFIER\n     cache_hit = 1;\n               ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:77: syntax error, unexpected \'=\', expecting IDENTIFIER\n      cache_hit = 0;\n                ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:84: syntax error, unexpected \'[\', expecting IDENTIFIER\n      selectedRow[21:6] = mem_din;\n                 ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:99: syntax error, unexpected \'=\', expecting IDENTIFIER\n     cache_hit = 0;\n               ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n     selectedRow[21:6] = mem_din;\n                ^\n%Error: data/full_repos/permissive/138473269/rtl/mano_cache.v:117: syntax error, unexpected end\n  end\n  ^~~\n%Error: Exiting due to 22 error(s)\n'
module dmc256x16 (	clr, 
					clk, 

					cpu_addr, cpu_rd, cpu_wr, cpu_din, cpu_dout, cache_hit,

					ir_ld_b, 

					mem_addr, mem_rd, mem_wr, mem_din, mem_dout,
					b);
	input 	clr;
	input 	clk;
	input 	cpu_rd;
	input 	cpu_wr;
	input	[`addrwidth-1:0] cpu_addr;
	input	[`datawidth-1:0] cpu_din ;
	output	[`datawidth-1:0] cpu_dout;
	reg  	[`datawidth-1:0] cpu_dout;
	output  cache_hit;
	reg     cache_hit;


	output ir_ld_b=0;
	reg ir_ld_b;
	
	output 	mem_rd;
	output 	mem_wr;
	output	[`addrwidth-1:0] mem_addr;
	reg	    [`addrwidth-1:0] mem_addr;
	input	[`datawidth-1:0] mem_din ;
	output	[`datawidth-1:0] mem_dout;
	reg  	[`datawidth-1:0] mem_dout;


	reg [`cachewidth-1:0] cacheBank [0:`cachecap-1];
	reg [`cachewidth-1:0] zero = 0;
	output b;
	reg b = 0;

	reg [7:0] offset;
	reg [3:0] tag;
	reg [21:0] selectedRow;

	reg mem_rd_reg;
	reg mem_wr_reg;

	integer i;

	initial
	begin
		cache_hit = 1;
		for (i = 0; i < `cachewidth; i = i+1) begin
			cacheBank[i] = zero;
		end
	end

	always @(cpu_addr, posedge clk)
	begin
		if (cpu_rd == 1) begin
			offset = cpu_addr[7:0];
			tag = cpu_addr[11:8];
			selectedRow = cacheBank[offset];
			if (selectedRow[0] == 1) begin

				if (tag == selectedRow[5:2]) begin
					cache_hit = 1;
					cpu_dout = selectedRow[21:6];
				end
				else begin
					if (b == 0) 
					begin
						cache_hit = 0;
						mem_addr = cpu_addr;
						mem_rd_reg = 1'b1;
						b = 1;
					end
					else
					begin
						selectedRow[21:6] = mem_din;
						selectedRow[5:2] = tag;
						selectedRow[1] = 0;
						selectedRow[0] = 1;
						cacheBank[offset] = selectedRow;
						cpu_dout = selectedRow[21:6];
						b = 0;
						cache_hit = 1;
					end
				end
			end
			else begin
				if (b == 0) 
				begin

					cache_hit = 0;
					mem_addr = cpu_addr;
					mem_rd_reg = 1'b1;
					b = 1;
				end
				else
				begin
					selectedRow[21:6] = mem_din;
					selectedRow[5:2] = tag;
					selectedRow[1] = 0;
					selectedRow[0] = 1;
					cacheBank[offset] = selectedRow;
					cpu_dout = selectedRow[21:6];
					b = 0;
					cache_hit = 1;
					ir_ld_b=1;
				end
			end
		end
	end

	assign mem_rd = mem_rd_reg;

	reg [7:0] offsetIncoming;
	reg [3:0] tagIncoming;
	reg [21:0] selectedRow2;
	reg [21:0] rowToWrite;


	always @(cpu_din)
	begin
		if(cpu_din[15:12]==3 | cpu_din[15:12]==5 | cpu_din[15:12]==6) begin
			offsetIncoming = cpu_din[7:0];
			tagIncoming = cpu_din[11:8];
			selectedRow2 = cacheBank[offsetIncoming];
			if (selectedRow2[0] == 1) begin
				if (selectedRow2[1] == 1) begin
					mem_wr_reg = 1'b1;
					mem_addr[11:8] = selectedRow2[5:2];
					mem_addr[7:0] = offsetIncoming;
					mem_dout = selectedRow2[21:6];
					rowToWrite[1] = 0;
				end
			end
			rowToWrite[21:6] = cpu_din;
			rowToWrite[5:2] = tag;
			rowToWrite[1] = 1;
			rowToWrite[0] = 1;
			cacheBank[offsetIncoming] = rowToWrite;
		end
	end

	assign mem_wr = mem_wr_reg;
endmodule
module dmc256x16 (	clr, 
					clk, 

					cpu_addr, cpu_rd, cpu_wr, cpu_din, cpu_dout, cache_hit,

					ir_ld_b, 

					mem_addr, mem_rd, mem_wr, mem_din, mem_dout,
					b);

	input 	clr;
	input 	clk;
	input 	cpu_rd;
	input 	cpu_wr;
	input	[`addrwidth-1:0] cpu_addr;
	input	[`datawidth-1:0] cpu_din ;
	output	[`datawidth-1:0] cpu_dout;
	reg  	[`datawidth-1:0] cpu_dout;
	output  cache_hit;
	reg     cache_hit;


	output ir_ld_b=0;
	reg ir_ld_b;
	
	output 	mem_rd;
	output 	mem_wr;
	output	[`addrwidth-1:0] mem_addr;
	reg	    [`addrwidth-1:0] mem_addr;
	input	[`datawidth-1:0] mem_din ;
	output	[`datawidth-1:0] mem_dout;
	reg  	[`datawidth-1:0] mem_dout;


	reg [`cachewidth-1:0] cacheBank [0:`cachecap-1];
	reg [`cachewidth-1:0] zero = 0;
	output b;
	reg b = 0;

	reg [7:0] offset;
	reg [3:0] tag;
	reg [21:0] selectedRow;

	reg mem_rd_reg;
	reg mem_wr_reg;

	integer i;

	initial
	begin
		cache_hit = 1;
		for (i = 0; i < `cachewidth; i = i+1) begin
			cacheBank[i] = zero;
		end
	end

	always @(cpu_addr, posedge clk)
	begin
		if (cpu_rd == 1) begin
			offset = cpu_addr[7:0];
			tag = cpu_addr[11:8];
			selectedRow = cacheBank[offset];
			if (selectedRow[0] == 1) begin

				if (tag == selectedRow[5:2]) begin
					cache_hit = 1;
					cpu_dout = selectedRow[21:6];
				end
				else begin
					if (b == 0) 
					begin
						cache_hit = 0;
						mem_addr = cpu_addr;
						mem_rd_reg = 1'b1;
						b = 1;
					end
					else
					begin
						selectedRow[21:6] = mem_din;
						selectedRow[5:2] = tag;
						selectedRow[1] = 0;
						selectedRow[0] = 1;
						cacheBank[offset] = selectedRow;
						cpu_dout = selectedRow[21:6];
						b = 0;
						cache_hit = 1;
					end
				end
			end
			else begin
				if (b == 0) 
				begin

					cache_hit = 0;
					mem_addr = cpu_addr;
					mem_rd_reg = 1'b1;
					b = 1;
				end
				else
				begin
					selectedRow[21:6] = mem_din;
					selectedRow[5:2] = tag;
					selectedRow[1] = 0;
					selectedRow[0] = 1;
					cacheBank[offset] = selectedRow;
					cpu_dout = selectedRow[21:6];
					b = 0;
					cache_hit = 1;
					ir_ld_b=1;
				end
			end
		end
	end

	assign mem_rd = mem_rd_reg;

	reg [7:0] offsetIncoming;
	reg [3:0] tagIncoming;
	reg [21:0] selectedRow2;
	reg [21:0] rowToWrite;


	always @(cpu_din)
	begin
		if(cpu_din[15:12]==3 | cpu_din[15:12]==5 | cpu_din[15:12]==6) begin
			offsetIncoming = cpu_din[7:0];
			tagIncoming = cpu_din[11:8];
			selectedRow2 = cacheBank[offsetIncoming];
			if (selectedRow2[0] == 1) begin
				if (selectedRow2[1] == 1) begin
					mem_wr_reg = 1'b1;
					mem_addr[11:8] = selectedRow2[5:2];
					mem_addr[7:0] = offsetIncoming;
					mem_dout = selectedRow2[21:6];
					rowToWrite[1] = 0;
				end
			end
			rowToWrite[21:6] = cpu_din;
			rowToWrite[5:2] = tag;
			rowToWrite[1] = 1;
			rowToWrite[0] = 1;
			cacheBank[offsetIncoming] = rowToWrite;
		end
	end

	assign mem_wr = mem_wr_reg;
endmodule