data/full_repos/permissive/18921956/template/if-else.v
data/verilator_xmls/b22b8d39-4d8f-4e2a-ad9e-d56a6df1e362.xml
module If_Else_Block (
    output reg o_sum,
    input i_a,
    input i_b,
    input en
);







always @(*) begin
    if (en) begin
        o_sum = i_a + i_b;
    end else begin
        o_sum = 0;
    end
end

endmodule
module If_Else_Block (
    output reg o_sum,
    input i_a,
    input i_b,
    input en
);








always @(*) begin
    if (en) begin
        o_sum = i_a + i_b;
    end else begin
        o_sum = 0;
    end
end

endmodule