data/full_repos/permissive/174323821/hdl/cpu/jtframe_virq.v
data/verilator_xmls/8978ad11-8d9e-4a93-91c2-c46abaec60c1.xml
module jtframe_virq(
    input      rst,
    input      clk,
    input      LVBL,
    input      dip_pause,
    input      skip_en,
    input      skip_but,

    input      clr,
    input      custom_in,
    output reg blin_n,
    output reg blout_n,
    output reg custom_n
);

reg last_LVBL, last_cin, skip;

always @(posedge clk, posedge rst) begin : int_gen
    if( rst ) begin
        custom_n <= 1;
        blin_n   <= 1;
        blout_n  <= 1;
        last_cin <= 0;
        skip     <= 0;
    end else begin
        last_LVBL <= LVBL;
        last_cin  <= custom_in;

        if( !skip_en) begin
            skip <= 0;
        end else begin
            if( LVBL && !last_LVBL ) begin
                if( skip_but )
                    skip <= ~skip;
                else
                    skip <= 0;
            end
        end

        if( clr ) begin
            custom_n <= 1;
            blin_n   <= 1;
            blout_n  <= 1;
        end else if( !skip && dip_pause ) begin
            if( custom_in && !last_cin ) custom_n <= 0;
            if( !LVBL &&  last_LVBL    ) blin_n   <= 0;
            if(  LVBL && !last_LVBL    ) blout_n  <= 0;
        end
    end
end

endmodule
module jtframe_virq(
    input      rst,
    input      clk,
    input      LVBL,
    input      dip_pause,
    input      skip_en,
    input      skip_but,

    input      clr,
    input      custom_in,
    output reg blin_n,
    output reg blout_n,
    output reg custom_n
);


reg last_LVBL, last_cin, skip;

always @(posedge clk, posedge rst) begin : int_gen
    if( rst ) begin
        custom_n <= 1;
        blin_n   <= 1;
        blout_n  <= 1;
        last_cin <= 0;
        skip     <= 0;
    end else begin
        last_LVBL <= LVBL;
        last_cin  <= custom_in;

        if( !skip_en) begin
            skip <= 0;
        end else begin
            if( LVBL && !last_LVBL ) begin
                if( skip_but )
                    skip <= ~skip;
                else
                    skip <= 0;
            end
        end

        if( clr ) begin
            custom_n <= 1;
            blin_n   <= 1;
            blout_n  <= 1;
        end else if( !skip && dip_pause ) begin
            if( custom_in && !last_cin ) custom_n <= 0;
            if( !LVBL &&  last_LVBL    ) blin_n   <= 0;
            if(  LVBL && !last_LVBL    ) blout_n  <= 0;
        end
    end
end

endmodule