data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new/sopc_tb.v
 line:17: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new/sopc_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n            forever #5 clk <= ~clk;\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new/sopc_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n            #5 rst <= 1\'B0;  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new/sopc_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n            #1000 $stop;\n            ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new/sopc_tb.v:20: Cannot find file containing module: \'sopc\'\n    sopc y86_sopc\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new,data/full_repos/permissive/114896735/sopc\n             data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new,data/full_repos/permissive/114896735/sopc.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sim_1/new,data/full_repos/permissive/114896735/sopc.sv\n             sopc\n             sopc.v\n             sopc.sv\n             obj_dir/sopc\n             obj_dir/sopc.v\n             obj_dir/sopc.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sopc_tb;
    reg clk;
    reg rst;
    
    initial
        begin
            clk <= 1'B0;
            forever #5 clk <= ~clk;
        end
        
    initial
        begin
            rst <= 1'B1;  
            #5 rst <= 1'B0;  
            #1000 $stop;
        end
    
    sopc y86_sopc
    (
        .clk(clk),
        .rst(rst)
    );
endmodule
module sopc_tb;

    reg clk;
    reg rst;
    
    initial
        begin
            clk <= 1'B0;
            forever #5 clk <= ~clk;
        end
        
    initial
        begin
            rst <= 1'B1;  
            #5 rst <= 1'B0;  
            #1000 $stop;
        end
    
    sopc y86_sopc
    (
        .clk(clk),
        .rst(rst)
    );
endmodule