data/full_repos/permissive/157049472/Verilog Source Files/BranchL.v
1: b'%Error: Cannot find file containing module: Source\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Source\n             data/full_repos/permissive/157049472/Verilog/Source.v\n             data/full_repos/permissive/157049472/Verilog/Source.sv\n             Source\n             Source.v\n             Source.sv\n             obj_dir/Source\n             obj_dir/Source.v\n             obj_dir/Source.sv\n%Error: Cannot find file containing module: Files,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Files/BranchL.v\n%Error: Exiting due to 4 error(s)\n'
module BranchL(
	input wire [5:0] opcode,
	input wire [25:0] offset_in,
	input wire [31:0] rs_value,
	input wire zflag_ff,input wire oflag_ff,
	input wire cflag_ff,
	input wire sflag_ff,
	input wire clk,
	output reg [25:0] offset_out,
	input wire rst,
	output reg branch
    );
	
	wire zflag, oflag, cflag, sflag;
	DFlipFlop zFlagFF (.clk(clk),.rst(rst),.in(zflag_ff),.out(zflag)),
				 oFlagFF (.clk(clk),.rst(rst),.in(oflag_ff),.out(oflag)),
				 cFlagFF (.clk(clk),.rst(rst),.in(cflag_ff),.out(cflag)),
				 sFlagFF (.clk(clk),.rst(rst),.in(sflag_ff),.out(sflag));


	always @(opcode or offset_in or rs_value or zflag or oflag or cflag or sflag or rst)
	begin
		if(rst)
		begin
			offset_out = 0;
			branch = 0;
		end
		else
		begin
			branch = 1;
			case(opcode)
				6'd3: begin
					offset_out = offset_in;
				end
				6'd4: begin
					offset_out = rs_value[25:0];
				end
				6'd5: begin
					if(zflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd6: begin
					if(!zflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd7: begin
					if(cflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd8: begin
					if(!cflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd9: begin
					if(sflag)
						offset_out = offset_in; 	
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd10: begin
					if(!sflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd11: begin
					if(oflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd12: begin
					if(!oflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd13: begin
					offset_out = offset_in;
				end
				6'd14: begin
					offset_out = rs_value[25:0];
				end
				default: begin
					branch = 0;
					offset_out = 0;
				end
			endcase
		end
	end


endmodule
module BranchL(
	input wire [5:0] opcode,
	input wire [25:0] offset_in,
	input wire [31:0] rs_value,
	input wire zflag_ff,input wire oflag_ff,
	input wire cflag_ff,
	input wire sflag_ff,
	input wire clk,
	output reg [25:0] offset_out,
	input wire rst,
	output reg branch
    );

	
	wire zflag, oflag, cflag, sflag;
	DFlipFlop zFlagFF (.clk(clk),.rst(rst),.in(zflag_ff),.out(zflag)),
				 oFlagFF (.clk(clk),.rst(rst),.in(oflag_ff),.out(oflag)),
				 cFlagFF (.clk(clk),.rst(rst),.in(cflag_ff),.out(cflag)),
				 sFlagFF (.clk(clk),.rst(rst),.in(sflag_ff),.out(sflag));


	always @(opcode or offset_in or rs_value or zflag or oflag or cflag or sflag or rst)
	begin
		if(rst)
		begin
			offset_out = 0;
			branch = 0;
		end
		else
		begin
			branch = 1;
			case(opcode)
				6'd3: begin
					offset_out = offset_in;
				end
				6'd4: begin
					offset_out = rs_value[25:0];
				end
				6'd5: begin
					if(zflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd6: begin
					if(!zflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd7: begin
					if(cflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd8: begin
					if(!cflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd9: begin
					if(sflag)
						offset_out = offset_in; 	
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd10: begin
					if(!sflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd11: begin
					if(oflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd12: begin
					if(!oflag)
						offset_out = offset_in;
					else begin
						branch = 0;
						offset_out = 0;
					end
				end
				6'd13: begin
					offset_out = offset_in;
				end
				6'd14: begin
					offset_out = rs_value[25:0];
				end
				default: begin
					branch = 0;
					offset_out = 0;
				end
			endcase
		end
	end


endmodule