data/full_repos/permissive/174242803/src/exmem.v
1: b'%Error: data/full_repos/permissive/174242803/src/exmem.v:45: Unsupported or unknown PLI call: $writememb\n   $writememb("./src/memory_files/ram.after.dat", mips_ram) ;  \n   ^~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module exmem
   (input clk, memwrite,
    input [7:0] adr,
    input [7:0] writedata,
    output reg [7:0] memdata
    );

	integer i;
   reg [7:0] mips_ram [0:256];

	parameter WIDTH = 8; 
	parameter RAM_ADDR_BITS = 8;




	initial begin
		for(i=0; i<256; i=i+1) begin
			mips_ram[i]=8'b0;
		end

		$display("RAM: Memory initialized to 0");

		$readmemh("./src/memory_files/fib.dat", mips_ram);

		$display ("RAM: External Memory File: ram.dat loaded into RAM.");
	end

	integer k;
	initial begin
		$display("RAM: Contents of Mem after reading data file:");
		for (k=0; k<256; k=k+1) $display("%d:%h",k,mips_ram[k]);
	end


   always @(negedge clk) begin
		if (memwrite) begin
			mips_ram[adr] <= writedata;
			$writememb("./src/memory_files/ram.after.dat", mips_ram) ;
		end

		memdata <= mips_ram[adr];
	end
endmodule
module exmem
   (input clk, memwrite,
    input [7:0] adr,
    input [7:0] writedata,
    output reg [7:0] memdata
    );


	integer i;
   reg [7:0] mips_ram [0:256];

	parameter WIDTH = 8; 
	parameter RAM_ADDR_BITS = 8;




	initial begin
		for(i=0; i<256; i=i+1) begin
			mips_ram[i]=8'b0;
		end

		$display("RAM: Memory initialized to 0");

		$readmemh("./src/memory_files/fib.dat", mips_ram);

		$display ("RAM: External Memory File: ram.dat loaded into RAM.");
	end

	integer k;
	initial begin
		$display("RAM: Contents of Mem after reading data file:");
		for (k=0; k<256; k=k+1) $display("%d:%h",k,mips_ram[k]);
	end


   always @(negedge clk) begin
		if (memwrite) begin
			mips_ram[adr] <= writedata;
			$writememb("./src/memory_files/ram.after.dat", mips_ram) ;
		end

		memdata <= mips_ram[adr];
	end
endmodule