data/full_repos/permissive/129155059/proyecto-02/all/memory_cond.v
data/verilator_xmls/e79297f5-27ee-44c5-9cc8-4b65e5a36465.xml
module memory_cond #(parameter DATA_WIDTH = 8, parameter ADDRESS_WIDTH = 3, parameter BUFFER_DEPTH = 8
)(
  input CLK,
  input ENB,
  input sRead,
  input sWrite,

  input [ADDRESS_WIDTH-1:0] addressRead,
  input [ADDRESS_WIDTH-1:0] addressWrite,
  input [DATA_WIDTH-1:0] inputData,
  output reg [DATA_WIDTH-1:0] outputData
  );

  reg [DATA_WIDTH-1:0] memoria [BUFFER_DEPTH-1:0];

  always @ ( posedge CLK ) begin
    if (sRead) begin
      outputData <= memoria[addressRead];
    end
    if (sWrite) begin
      memoria[addressWrite] <= inputData;
    end
  end
endmodule
module memory_cond #(parameter DATA_WIDTH = 8, parameter ADDRESS_WIDTH = 3, parameter BUFFER_DEPTH = 8
)(
  input CLK,
  input ENB,
  input sRead,
  input sWrite,

  input [ADDRESS_WIDTH-1:0] addressRead,
  input [ADDRESS_WIDTH-1:0] addressWrite,
  input [DATA_WIDTH-1:0] inputData,
  output reg [DATA_WIDTH-1:0] outputData
  );


  reg [DATA_WIDTH-1:0] memoria [BUFFER_DEPTH-1:0];

  always @ ( posedge CLK ) begin
    if (sRead) begin
      outputData <= memoria[addressRead];
    end
    if (sWrite) begin
      memoria[addressWrite] <= inputData;
    end
  end
endmodule