data/full_repos/permissive/174323821/hdl/clocking/jtframe_cen96.v
data/verilator_xmls/12d5a6ba-a1a3-4422-8d9b-753eaa0913e0.xml
module jtframe_cen96(
    input   clk,
    output  reg cen16,
    output  reg cen8,
    output  reg cen12,
    output  reg cen6,
    output  reg cen6b
);

reg [3:0] cencnt12 = 4'd0;
reg [3:0] cencnt16 = 4'd0;

always @(posedge clk) begin
    cencnt12 <= cencnt12==4'd11 ? 4'd0 : cencnt12+4'd1;
    cencnt16 <= cencnt16 + 1'd1;
end

always @(posedge clk) begin
    cen16  <= cencnt12 == 4'd0 || cencnt12 == 4'd6;
    cen8   <= cencnt12 == 4'd0;
    cen12  <= cencnt16 == 4'd0 || cencnt16 == 4'd8;
    cen6   <= cencnt16 == 4'd0;
    cen6b  <= cencnt16 == 4'd8;
end
endmodule
module jtframe_cen96(
    input   clk,
    output  reg cen16,
    output  reg cen8,
    output  reg cen12,
    output  reg cen6,
    output  reg cen6b
);


reg [3:0] cencnt12 = 4'd0;
reg [3:0] cencnt16 = 4'd0;

always @(posedge clk) begin
    cencnt12 <= cencnt12==4'd11 ? 4'd0 : cencnt12+4'd1;
    cencnt16 <= cencnt16 + 1'd1;
end

always @(posedge clk) begin
    cen16  <= cencnt12 == 4'd0 || cencnt12 == 4'd6;
    cen8   <= cencnt12 == 4'd0;
    cen12  <= cencnt16 == 4'd0 || cencnt16 == 4'd8;
    cen6   <= cencnt16 == 4'd0;
    cen6b  <= cencnt16 == 4'd8;
end
endmodule