data/full_repos/permissive/211316121/lab8_1/RAM.v
data/verilator_xmls/5b6ce63a-5309-4219-a4c9-4264290deb83.xml
module RAM(
    input clk,
    input wen,
    input [3:0] din,
    input [3:0] addr,
    output [3:0] qout
);
reg [3:0] mem [15:0];
always@(posedge clk)
    if(wen)
        mem[addr]<=din;
assign qout=mem[addr];
endmodule
module RAM(
    input clk,
    input wen,
    input [3:0] din,
    input [3:0] addr,
    output [3:0] qout
);

reg [3:0] mem [15:0];
always@(posedge clk)
    if(wen)
        mem[addr]<=din;
assign qout=mem[addr];
endmodule