data/full_repos/permissive/17877624/src/hardware/Audio_Top.sv
1: b"%Error: data/full_repos/permissive/17877624/src/hardware/Audio_Top.sv:59: Cannot find file containing module: 'bell'\nbell b0 (.clock(OSC_50_B8A), .address(addr_bell), .q(M_bell));\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/17877624/src/hardware,data/full_repos/permissive/17877624/bell\n             data/full_repos/permissive/17877624/src/hardware,data/full_repos/permissive/17877624/bell.v\n             data/full_repos/permissive/17877624/src/hardware,data/full_repos/permissive/17877624/bell.sv\n             bell\n             bell.v\n             bell.sv\n             obj_dir/bell\n             obj_dir/bell.v\n             obj_dir/bell.sv\n%Error: data/full_repos/permissive/17877624/src/hardware/Audio_Top.sv:60: Cannot find file containing module: 'city'\ncity c0 (.clock(OSC_50_B8A), .address(addr_city), .q(M_city));\n^~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/Audio_Top.sv:61: Cannot find file containing module: 'whoosh_new'\nwhoosh_new w0 (.clock(OSC_50_B8A), .address(addr_who), .q(M_who));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/Audio_Top.sv:62: Cannot find file containing module: 'sword'\nsword s0 (.clock(OSC_50_B8A), .address(addr_sw), .q(M_sw));\n^~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/Audio_Top.sv:65: Cannot find file containing module: 'clock_pll'\nclock_pll pll (\n^~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/Audio_Top.sv:73: Cannot find file containing module: 'i2c_av_config'\ni2c_av_config av_config (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/Audio_Top.sv:86: Cannot find file containing module: 'audio_codec'\naudio_codec ac (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/Audio_Top.sv:102: Cannot find file containing module: 'audio_effects'\naudio_effects ae (\n^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module Audio_top (
    input  OSC_50_B8A,
	 input logic 	  resetn,
	 input logic [15:0]  writedata,
	 input logic address,
	 input logic write,
	 input logic chipselect,
	 output logic irq,
    inout  AUD_ADCLRCK,
    input  AUD_ADCDAT,
    inout  AUD_DACLRCK,
    output AUD_DACDAT,
    output AUD_XCK, 
    inout  AUD_BCLK,
    output AUD_I2C_SCLK,
    inout  AUD_I2C_SDAT,
    output AUD_MUTE,

    input  [3:0] KEY,
    input  [3:0] SW,
    output [3:0] LED
);

wire reset = !KEY[0];
wire main_clk;
wire audio_clk;
wire ctrl;

wire [1:0] sample_end;
wire [1:0] sample_req;
wire [15:0] audio_output;
wire [15:0] audio_sample;
wire [15:0] audio_sw;
wire [15:0] audio_ip;


wire [15:0] M_bell;
wire [15:0] M_city;
wire [15:0] M_who;
wire [15:0] M_sw;


wire [14:0] addr_bell;
wire [14:0] addr_city;
wire [14:0] addr_who;
wire [14:0] addr_sw;


bell b0 (.clock(OSC_50_B8A), .address(addr_bell), .q(M_bell));
city c0 (.clock(OSC_50_B8A), .address(addr_city), .q(M_city));
whoosh_new w0 (.clock(OSC_50_B8A), .address(addr_who), .q(M_who));
sword s0 (.clock(OSC_50_B8A), .address(addr_sw), .q(M_sw));


clock_pll pll (
    .refclk (OSC_50_B8A),
    .rst (reset),
    .outclk_0 (audio_clk),
    .outclk_1 (main_clk)
);


i2c_av_config av_config (
    .clk (main_clk),
    .reset (reset),
    .i2c_sclk (AUD_I2C_SCLK),
    .i2c_sdat (AUD_I2C_SDAT),
    .status (LED)
);

assign AUD_XCK = audio_clk;
assign AUD_MUTE = (SW != 4'b0);



audio_codec ac (
    .clk (audio_clk),
    .reset (reset),
    .sample_end (sample_end),
    .sample_req (sample_req),
    .audio_output (audio_output),
    .channel_sel (2'b10),

    .AUD_ADCLRCK (AUD_ADCLRCK),
    .AUD_ADCDAT (AUD_ADCDAT),
    .AUD_DACLRCK (AUD_DACLRCK),
    .AUD_DACDAT (AUD_DACDAT),
    .AUD_BCLK (AUD_BCLK)
);


audio_effects ae (
    .clk (audio_clk),
    .sample_end (sample_end[1]),
    .sample_req (sample_req[1]),
    .audio_output (audio_output),
    .audio_sample  (audio_sample),
    .addr_bell(addr_bell),
    .addr_city(addr_city),
    .addr_who(addr_who),
    .addr_sw(addr_sw),
    .M_bell(M_bell),
    .M_who(M_who),
    .M_city(M_city),
    .M_sw(M_sw),
	 .control(ctrl)
);



 always_ff @(posedge OSC_50_B8A)
     if (resetn) begin
	ctrl <= 0;


     end
	else if (chipselect && write)
	begin
		 
	 case(address)
	1'b0:	ctrl <= writedata[0];
	1'b1: audio_sw <= writedata;
	endcase
	end
endmodule
module Audio_top (
    input  OSC_50_B8A,
	 input logic 	  resetn,
	 input logic [15:0]  writedata,
	 input logic address,
	 input logic write,
	 input logic chipselect,
	 output logic irq,
    inout  AUD_ADCLRCK,
    input  AUD_ADCDAT,
    inout  AUD_DACLRCK,
    output AUD_DACDAT,
    output AUD_XCK, 
    inout  AUD_BCLK,
    output AUD_I2C_SCLK,
    inout  AUD_I2C_SDAT,
    output AUD_MUTE,

    input  [3:0] KEY,
    input  [3:0] SW,
    output [3:0] LED
);


wire reset = !KEY[0];
wire main_clk;
wire audio_clk;
wire ctrl;

wire [1:0] sample_end;
wire [1:0] sample_req;
wire [15:0] audio_output;
wire [15:0] audio_sample;
wire [15:0] audio_sw;
wire [15:0] audio_ip;


wire [15:0] M_bell;
wire [15:0] M_city;
wire [15:0] M_who;
wire [15:0] M_sw;


wire [14:0] addr_bell;
wire [14:0] addr_city;
wire [14:0] addr_who;
wire [14:0] addr_sw;


bell b0 (.clock(OSC_50_B8A), .address(addr_bell), .q(M_bell));
city c0 (.clock(OSC_50_B8A), .address(addr_city), .q(M_city));
whoosh_new w0 (.clock(OSC_50_B8A), .address(addr_who), .q(M_who));
sword s0 (.clock(OSC_50_B8A), .address(addr_sw), .q(M_sw));


clock_pll pll (
    .refclk (OSC_50_B8A),
    .rst (reset),
    .outclk_0 (audio_clk),
    .outclk_1 (main_clk)
);


i2c_av_config av_config (
    .clk (main_clk),
    .reset (reset),
    .i2c_sclk (AUD_I2C_SCLK),
    .i2c_sdat (AUD_I2C_SDAT),
    .status (LED)
);

assign AUD_XCK = audio_clk;
assign AUD_MUTE = (SW != 4'b0);



audio_codec ac (
    .clk (audio_clk),
    .reset (reset),
    .sample_end (sample_end),
    .sample_req (sample_req),
    .audio_output (audio_output),
    .channel_sel (2'b10),

    .AUD_ADCLRCK (AUD_ADCLRCK),
    .AUD_ADCDAT (AUD_ADCDAT),
    .AUD_DACLRCK (AUD_DACLRCK),
    .AUD_DACDAT (AUD_DACDAT),
    .AUD_BCLK (AUD_BCLK)
);


audio_effects ae (
    .clk (audio_clk),
    .sample_end (sample_end[1]),
    .sample_req (sample_req[1]),
    .audio_output (audio_output),
    .audio_sample  (audio_sample),
    .addr_bell(addr_bell),
    .addr_city(addr_city),
    .addr_who(addr_who),
    .addr_sw(addr_sw),
    .M_bell(M_bell),
    .M_who(M_who),
    .M_city(M_city),
    .M_sw(M_sw),
	 .control(ctrl)
);



 always_ff @(posedge OSC_50_B8A)
     if (resetn) begin
	ctrl <= 0;


     end
	else if (chipselect && write)
	begin
		 
	 case(address)
	1'b0:	ctrl <= writedata[0];
	1'b1: audio_sw <= writedata;
	endcase
	end
endmodule