data/full_repos/permissive/117436613/testbench/test.v
 line:41: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/test.v:37: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk <= ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/117436613/testbench/test.v:41: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clk);\n             ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

	reg    clk = 0;
	reg    reset_n = 0;

    MMIX_system u0 (


        .clk_clk       (clk),
        .reset_reset_n (reset_n),










        .flash_wire_ADDR  (),
        .flash_wire_CE_N  (),
        .flash_wire_OE_N  (),
        .flash_wire_WE_N  (),
        .flash_wire_RST_N (),
        .flash_wire_DQ    ()






    );

	always #10 clk <= ~clk;

	initial begin
		reset_n <= 0;
		repeat (2) @(posedge clk);
		reset_n <= 1;
	end

endmodule
module test();


	reg    clk = 0;
	reg    reset_n = 0;

    MMIX_system u0 (


        .clk_clk       (clk),
        .reset_reset_n (reset_n),










        .flash_wire_ADDR  (),
        .flash_wire_CE_N  (),
        .flash_wire_OE_N  (),
        .flash_wire_WE_N  (),
        .flash_wire_RST_N (),
        .flash_wire_DQ    ()






    );

	always #10 clk <= ~clk;

	initial begin
		reset_n <= 0;
		repeat (2) @(posedge clk);
		reset_n <= 1;
	end

endmodule