data/full_repos/permissive/2084115/rtl/math/jelly_signed_divide_multicycle.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_signed_divide_multicycle.v:66: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 33 bits.\n                                                                                               : ... In instance jelly_signed_divide_multicycle\n    wire    [DATA_WIDTH-1:0]    next_counter = {reg_counter, 1\'b1};\n                                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_signed_divide_multicycle.v:81: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 65 bits.\n                                                                                               : ... In instance jelly_signed_divide_multicycle\n    assign {remainder1, quotient1} = {reg_remainder, reg_quotient, ~quotient2[DATA_WIDTH]};\n                                   ^\n%Error: Exiting due to 2 warning(s)\n'
function [DATA_WIDTH-1:0]   neg;
    input   [DATA_WIDTH-1:0]    in_data;
        begin
            neg = ~in_data + 1;
        end
    endfunction
function [DATA_WIDTH-1:0]   neg;

    input   [DATA_WIDTH-1:0]    in_data;
        begin
            neg = ~in_data + 1;
        end
    endfunction