data/full_repos/permissive/216615048/src/simulation/data_mem_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/data_mem_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nforever #50 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/data_mem_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/data_mem_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/data_mem_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Error: data/full_repos/permissive/216615048/src/simulation/data_mem_tb.v:10: Cannot find file containing module: \'DataMem\'\nDataMem DM(clk, mr, mw, addr, data_in, data_out);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/DataMem\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/DataMem.v\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/DataMem.sv\n             DataMem\n             DataMem.v\n             DataMem.sv\n             obj_dir/DataMem\n             obj_dir/DataMem.v\n             obj_dir/DataMem.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module data_mem_tb();
reg clk,mr,mw;
reg [31:0]data_in;
reg [5:0]addr;
wire [31:0]data_out;


DataMem DM(clk, mr, mw, addr, data_in, data_out);

initial begin
forever #50 clk = ~clk;
end

initial begin

clk=0;

mr=0;
mw=1;
addr=1;
data_in=10;
#100
mr=0;
mw=1;
addr=2;
data_in=55;
#100
mr=1;
mw=0;
addr=1;
#100
mr=1;
mw=0;
addr=2;

end 

endmodule
module data_mem_tb();

reg clk,mr,mw;
reg [31:0]data_in;
reg [5:0]addr;
wire [31:0]data_out;


DataMem DM(clk, mr, mw, addr, data_in, data_out);

initial begin
forever #50 clk = ~clk;
end

initial begin

clk=0;

mr=0;
mw=1;
addr=1;
data_in=10;
#100
mr=0;
mw=1;
addr=2;
data_in=55;
#100
mr=1;
mw=0;
addr=1;
#100
mr=1;
mw=0;
addr=2;

end 

endmodule