data/full_repos/permissive/13136965/clkgen.v
1: b"%Error: data/full_repos/permissive/13136965/clkgen.v:2: Duplicate declaration of signal: 'out'\n                                                      : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg out;\n    ^~~\n        data/full_repos/permissive/13136965/clkgen.v:1: ... Location of original declaration\nmodule clock(output out);\n                    ^~~\n%Error: Exiting due to 1 error(s)\n"
module clock(output out);
reg out;

initial
begin
	out = 1'b0;
end

always 
begin
	out= #1 ~out;
end

endmodule
module clock(output out);

reg out;

initial
begin
	out = 1'b0;
end

always 
begin
	out= #1 ~out;
end

endmodule