data/full_repos/permissive/143278/ivltests/sv_uwire1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sv_uwire1.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (foo !== 4\'b1001) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   logic [3:0] foo;


   logic [1:0] bar;
   assign foo[2:1] = bar;

   initial begin

      foo[0] = 1'b1;
      foo[3] = 1'b1;
      bar = 2'b00;

      #1 if (foo !== 4'b1001) begin
	 $display("FAILED -- foo=%b", foo);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   logic [3:0] foo;


   logic [1:0] bar;
   assign foo[2:1] = bar;

   initial begin

      foo[0] = 1'b1;
      foo[3] = 1'b1;
      bar = 2'b00;

      #1 if (foo !== 4'b1001) begin
	 $display("FAILED -- foo=%b", foo);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule