data/full_repos/permissive/20688874/viterbi/pmsmtb.v
1: b'%Error: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:3: Cannot find include file: pmsm.v\n`include "pmsm.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/pmsm.v\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/pmsm.v.v\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/pmsm.v.sv\n             pmsm.v\n             pmsm.v.v\n             pmsm.v.sv\n             obj_dir/pmsm.v\n             obj_dir/pmsm.v.v\n             obj_dir/pmsm.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:16: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:18: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:20: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:22: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:24: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:26: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:29: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:31: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:34: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:36: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Error: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:40: Unsupported or unknown PLI call: $shm_open\n $shm_open("pmsm.shm");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/20688874/viterbi/pmsmtb.v:41: Unsupported or unknown PLI call: $shm_probe\n $shm_probe("AC"); \n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s), 10 warning(s)\n'
module pmsmtb;
    reg [3:0]	npm0, npm1, npm2, npm3;
    reg 	clk, reset;
    wire [3:0] 	pm0, pm1, pm2, pm3;

    pmsm pmsm1(npm0, npm1, npm2, npm3, pm0, pm1, pm2, pm3, clk, reset);

    initial
        begin
            npm0=4'd0; npm1=4'd1; npm2=4'd2; npm3=4'd3; 
            clk=1'b0; reset=1'b0;
            #10;
            clk=1'b1; reset=1'b0;
	    #10;
            clk=1'b0; reset=1'b1;
	    #10;
            clk=1'b1; reset=1'b1;
	    #10;
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
	    #10;
	    npm0=4'd2; npm1=4'd3; npm2=4'd5; npm3=4'd9; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
	    npm0=4'd5; npm1=4'd1; npm2=4'd15; npm3=4'd3; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
        end
initial
    begin
	$shm_open("pmsm.shm");
	$shm_probe("AC");	
    end
endmodule
module pmsmtb;

    reg [3:0]	npm0, npm1, npm2, npm3;
    reg 	clk, reset;
    wire [3:0] 	pm0, pm1, pm2, pm3;

    pmsm pmsm1(npm0, npm1, npm2, npm3, pm0, pm1, pm2, pm3, clk, reset);

    initial
        begin
            npm0=4'd0; npm1=4'd1; npm2=4'd2; npm3=4'd3; 
            clk=1'b0; reset=1'b0;
            #10;
            clk=1'b1; reset=1'b0;
	    #10;
            clk=1'b0; reset=1'b1;
	    #10;
            clk=1'b1; reset=1'b1;
	    #10;
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
	    #10;
	    npm0=4'd2; npm1=4'd3; npm2=4'd5; npm3=4'd9; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
	    npm0=4'd5; npm1=4'd1; npm2=4'd15; npm3=4'd3; 
            clk=1'b0; reset=1'b0;
	    #10;
            clk=1'b1; reset=1'b0;
            #10;
        end
initial
    begin
	$shm_open("pmsm.shm");
	$shm_probe("AC");	
    end
endmodule