data/full_repos/permissive/148324174/FIFO/fifo1.v
1: b"%Error: data/full_repos/permissive/148324174/FIFO/fifo1.v:16: Cannot find file containing module: 'sync_r2w'\nsync_r2w #(ASIZE) U1(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/148324174/FIFO,data/full_repos/permissive/148324174/sync_r2w\n             data/full_repos/permissive/148324174/FIFO,data/full_repos/permissive/148324174/sync_r2w.v\n             data/full_repos/permissive/148324174/FIFO,data/full_repos/permissive/148324174/sync_r2w.sv\n             sync_r2w\n             sync_r2w.v\n             sync_r2w.sv\n             obj_dir/sync_r2w\n             obj_dir/sync_r2w.v\n             obj_dir/sync_r2w.sv\n%Error: data/full_repos/permissive/148324174/FIFO/fifo1.v:23: Cannot find file containing module: 'sync_w2r'\nsync_w2r #(ASIZE) U2(\n^~~~~~~~\n%Error: data/full_repos/permissive/148324174/FIFO/fifo1.v:30: Cannot find file containing module: 'fifomem'\nfifomem #(DSIZE, ASIZE) U3(\n^~~~~~~\n%Error: data/full_repos/permissive/148324174/FIFO/fifo1.v:39: Cannot find file containing module: 'rptr_empty'\nrptr_empty #(ASIZE) U4(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/148324174/FIFO/fifo1.v:49: Cannot find file containing module: 'wptr_full'\nwptr_full #(ASIZE) U5(\n^~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module fifo1 #(
    parameter DSIZE = 8,
    parameter ASIZE = 4
    )(
    output [DSIZE-1:0] rdata,
    output             wfull,
    output             rempty,
    input  [DSIZE-1:0] wdata,
    input              winc, wclk, wrst,
    input              rinc, rclk, rrst
    );

wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wrptr2, rwptr2;

sync_r2w #(ASIZE) U1(
    .wrptr2(wrptr2),
    .rptr(rptr),
    .wclk(wclk),
    .wrst(wrst)
    );

sync_w2r #(ASIZE) U2(
    .rwptr2(rwptr2),
    .wptr(wptr),
    .rclk(rclk),
    .rrst(rrst)
    );

fifomem #(DSIZE, ASIZE) U3(
    .rdata(rdata),
    .wdata(wdata),
    .waddr(waddr),
    .raddr(raddr),
    .wclken(winc),
    .wclk(wclk)
    );

rptr_empty #(ASIZE) U4(
    .rempty(rempty),
    .raddr(raddr),
    .rptr(rptr),
    .rwptr2(rwptr2),
    .rinc(rinc),
    .rclk(rclk),
    .rrst(rrst)
    );

wptr_full #(ASIZE) U5(
    .wfull(wfull),
    .waddr(waddr),
    .wptr(wptr),
    .wrptr2(wrptr2),
    .winc(winc),
    .wclk(wclk),
    .wrst(wrst)
    );

endmodule
module fifo1 #(
    parameter DSIZE = 8,
    parameter ASIZE = 4
    )(
    output [DSIZE-1:0] rdata,
    output             wfull,
    output             rempty,
    input  [DSIZE-1:0] wdata,
    input              winc, wclk, wrst,
    input              rinc, rclk, rrst
    );


wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wrptr2, rwptr2;

sync_r2w #(ASIZE) U1(
    .wrptr2(wrptr2),
    .rptr(rptr),
    .wclk(wclk),
    .wrst(wrst)
    );

sync_w2r #(ASIZE) U2(
    .rwptr2(rwptr2),
    .wptr(wptr),
    .rclk(rclk),
    .rrst(rrst)
    );

fifomem #(DSIZE, ASIZE) U3(
    .rdata(rdata),
    .wdata(wdata),
    .waddr(waddr),
    .raddr(raddr),
    .wclken(winc),
    .wclk(wclk)
    );

rptr_empty #(ASIZE) U4(
    .rempty(rempty),
    .raddr(raddr),
    .rptr(rptr),
    .rwptr2(rwptr2),
    .rinc(rinc),
    .rclk(rclk),
    .rrst(rrst)
    );

wptr_full #(ASIZE) U5(
    .wfull(wfull),
    .waddr(waddr),
    .wptr(wptr),
    .wrptr2(wrptr2),
    .winc(winc),
    .wclk(wclk),
    .wrst(wrst)
    );

endmodule