data/full_repos/permissive/211316121/lab7_2/TrafficFarm.v
data/verilator_xmls/25bc4578-aa7e-43e4-a633-38d4d2910e9c.xml
module TrafficFarm_Top(
    input clk,
    input [2:0] sw,
    output [5:0] led
    );
    wire clr=sw[0];
    wire reset=sw[1];
    wire C=sw[2];
    wire ST;
    wire clk3,TS,TL;
    
    clkdiv top_1s(clk,clr,clk3);
    
    count top_15_45(clk3,ST,TS,TL);
   
    TrafficFarm top_tra(TS,TL,C,clk3,reset,led,ST);
    
endmodule
module TrafficFarm_Top(
    input clk,
    input [2:0] sw,
    output [5:0] led
    );

    wire clr=sw[0];
    wire reset=sw[1];
    wire C=sw[2];
    wire ST;
    wire clk3,TS,TL;
    
    clkdiv top_1s(clk,clr,clk3);
    
    count top_15_45(clk3,ST,TS,TL);
   
    TrafficFarm top_tra(TS,TL,C,clk3,reset,led,ST);
    
endmodule