data/full_repos/permissive/18426314/verilog/xilinx/clkgen.v
1: b"%Error: data/full_repos/permissive/18426314/verilog/xilinx/clkgen.v:9: Cannot find file containing module: 'ODDR2'\nODDR2 ODDR2_inst (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/18426314/verilog/xilinx,data/full_repos/permissive/18426314/ODDR2\n             data/full_repos/permissive/18426314/verilog/xilinx,data/full_repos/permissive/18426314/ODDR2.v\n             data/full_repos/permissive/18426314/verilog/xilinx,data/full_repos/permissive/18426314/ODDR2.sv\n             ODDR2\n             ODDR2.v\n             ODDR2.sv\n             obj_dir/ODDR2\n             obj_dir/ODDR2.v\n             obj_dir/ODDR2.sv\n%Error: data/full_repos/permissive/18426314/verilog/xilinx/clkgen.v:20: Cannot find file containing module: 'DCM_CLKGEN'\nDCM_CLKGEN #(  \n^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module clkgen(input wire clkin, output wire clkout, clk25m, locked);


wire clkout_div ;




ODDR2 ODDR2_inst (
   .Q (clk25m),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(1),
   .D0(0),
   .D1(1),
   .R (0),
   .S (0)
);

DCM_CLKGEN #(
	.CLKFXDV_DIVIDE(4),
	.CLKFX_DIVIDE(1),
	.CLKFX_MD_MAX(0.0),
	.CLKFX_MULTIPLY(4),
	.CLKIN_PERIOD(40.0),
	.SPREAD_SPECTRUM("NONE"),

	.STARTUP_WAIT("FALSE")
) DCM (
	.CLKFX(clkout),
	.CLKFX180(),
	.CLKFXDV(clkout_div),
	.LOCKED(locked),
	.PROGDONE(),
	.STATUS(),
	.CLKIN(clkin),
	.FREEZEDCM(1'b0),
	.PROGCLK(1'b0),
	.PROGDATA(1'b0),
	.PROGEN(1'b0),
	.RST(1'b0)
);

endmodule
module clkgen(input wire clkin, output wire clkout, clk25m, locked);



wire clkout_div ;




ODDR2 ODDR2_inst (
   .Q (clk25m),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(1),
   .D0(0),
   .D1(1),
   .R (0),
   .S (0)
);

DCM_CLKGEN #(
	.CLKFXDV_DIVIDE(4),
	.CLKFX_DIVIDE(1),
	.CLKFX_MD_MAX(0.0),
	.CLKFX_MULTIPLY(4),
	.CLKIN_PERIOD(40.0),
	.SPREAD_SPECTRUM("NONE"),

	.STARTUP_WAIT("FALSE")
) DCM (
	.CLKFX(clkout),
	.CLKFX180(),
	.CLKFXDV(clkout_div),
	.LOCKED(locked),
	.PROGDONE(),
	.STATUS(),
	.CLKIN(clkin),
	.FREEZEDCM(1'b0),
	.PROGCLK(1'b0),
	.PROGDATA(1'b0),
	.PROGEN(1'b0),
	.RST(1'b0)
);

endmodule