data/full_repos/permissive/138443719/03-modules/src/main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/138443719/03-modules/src/main.v:19: Unsupported: Ignoring delay on this delayed statement.\n          #1;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/138443719/03-modules/src/main.v:28: Unsupported or unknown PLI call: $monitor\n    $monitor("Outs have changed! New values are: %b %b %b", out1, out2, out3) ;\n    ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hello_world;


  reg in1, in2, in3;
  wire out1, out2, out3;

  gate_level_module dut_module1(in1, in2, in3, out1);
  simplified_logic_module dut_module2(in1, in2, in3, out2);
  behavioral_module dut_module3(in1, in2, in3, out3);

  integer i, j, k;

  initial begin
    for (i = 0; i < 2; i = i + 1) begin
      for (j = 0; j < 2; j = j + 1) begin
        for (k = 0; k < 2; k = k + 1) begin
          in1= i; in2 = j; in3 = k;
          $display("Input values are: %b %b %b", in1, in2, in3);
          #1;
        end
      end
    end
    $finish;
  end

  initial begin

    $monitor("Outs have changed! New values are: %b %b %b", out1, out2, out3) ;
  end
endmodule
module hello_world;



  reg in1, in2, in3;
  wire out1, out2, out3;

  gate_level_module dut_module1(in1, in2, in3, out1);
  simplified_logic_module dut_module2(in1, in2, in3, out2);
  behavioral_module dut_module3(in1, in2, in3, out3);

  integer i, j, k;

  initial begin
    for (i = 0; i < 2; i = i + 1) begin
      for (j = 0; j < 2; j = j + 1) begin
        for (k = 0; k < 2; k = k + 1) begin
          in1= i; in2 = j; in3 = k;
          $display("Input values are: %b %b %b", in1, in2, in3);
          #1;
        end
      end
    end
    $finish;
  end

  initial begin

    $monitor("Outs have changed! New values are: %b %b %b", out1, out2, out3) ;
  end
endmodule