data/full_repos/permissive/180199545/Potentiometer/potentiometer_test_top.v
1: b"%Error: data/full_repos/permissive/180199545/Potentiometer/potentiometer_test_top.v:77: syntax error, unexpected '(', expecting IDENTIFIER\n  .JPorts(inJA),\n  ^\n%Error: Exiting due to 1 error(s)\n"
module potentiometer_test_top (   
		MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS,
		ClkPort,
		Led,
		JA
	  );




	input	ClkPort;	
	


	output 	MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS;

	input [7:0]	JA;
	output [7:0]	Led;
	
	
	

	wire		reset, ClkPort;
	wire		board_clk, sys_clk;
	reg [7:0]	inJA;
	reg [7:0]	outLed;
	wire [7:0]	Led_wire;

	


	assign {MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS} = 5'b11111;
	assign Led[7:0] = outLed[7:0];
	
	








	
	BUFGP BUFGP1 (board_clk, ClkPort); 	








	
	always @ (board_clk)
	begin
		inJA[7:0] = JA[7:0];
	end



	read_potentiometer(
		.JPorts(inJA),
		.reset(reset),
		.sys_clk(board_clk),
		.Value(Led_wire)
		);




	
	always @ (Led_wire)
	begin
		outLed[7:0] = Led_wire[7:0];
	end

endmodule
module potentiometer_test_top (   
		MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS,
		ClkPort,
		Led,
		JA
	  );





	input	ClkPort;	
	


	output 	MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS;

	input [7:0]	JA;
	output [7:0]	Led;
	
	
	

	wire		reset, ClkPort;
	wire		board_clk, sys_clk;
	reg [7:0]	inJA;
	reg [7:0]	outLed;
	wire [7:0]	Led_wire;

	


	assign {MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS} = 5'b11111;
	assign Led[7:0] = outLed[7:0];
	
	








	
	BUFGP BUFGP1 (board_clk, ClkPort); 	








	
	always @ (board_clk)
	begin
		inJA[7:0] = JA[7:0];
	end



	read_potentiometer(
		.JPorts(inJA),
		.reset(reset),
		.sys_clk(board_clk),
		.Value(Led_wire)
		);




	
	always @ (Led_wire)
	begin
		outLed[7:0] = Led_wire[7:0];
	end

endmodule