data/full_repos/permissive/2047449/clock_divider.v
data/verilator_xmls/0af0ae81-b3c0-4548-9f0b-05fcd27964a1.xml
module clock_divider(
	input clk,
	input clr,
	output clk6,
	output clk17
);

reg [17:0] q;

always @(posedge clk or posedge clr)
	if (clr == 1)
		q <= 0;
	else
		q <= q + 1;

assign clk6 = q[6];
assign clk17 = q[17];

endmodule
module clock_divider(
	input clk,
	input clr,
	output clk6,
	output clk17
);


reg [17:0] q;

always @(posedge clk or posedge clr)
	if (clr == 1)
		q <= 0;
	else
		q <= q + 1;

assign clk6 = q[6];
assign clk17 = q[17];

endmodule