data/full_repos/permissive/149231262/Verilog_pingpong/robeimodel/verilog/counttest.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/149231262/Verilog_pingpong/robeimodel/verilog/counttest.v:1: Cannot find include file: count.v\n`include "count.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149231262/Verilog_pingpong/robeimodel/verilog,data/full_repos/permissive/149231262/count.v\n             data/full_repos/permissive/149231262/Verilog_pingpong/robeimodel/verilog,data/full_repos/permissive/149231262/count.v.v\n             data/full_repos/permissive/149231262/Verilog_pingpong/robeimodel/verilog,data/full_repos/permissive/149231262/count.v.sv\n             count.v\n             count.v.v\n             count.v.sv\n             obj_dir/count.v\n             obj_dir/count.v.v\n             obj_dir/count.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/149231262/Verilog_pingpong/robeimodel/verilog/counttest.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #800000 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/149231262/Verilog_pingpong/robeimodel/verilog/counttest.v:19: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk=~clk;\n        ^\n%Error: data/full_repos/permissive/149231262/Verilog_pingpong/robeimodel/verilog/counttest.v:22: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("C:/Users/Administrator/Desktop/robeimodel/counttest.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/149231262/Verilog_pingpong/robeimodel/verilog/counttest.v:23: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module counttest();

	wire clk;
	wire countmax;


	count count1(
		.clk(clk),
		.countmax(countmax));

	initial
	begin
		clk=1'b0;
		#800000 $finish;
	end
	
	always #1 clk=~clk;
	
	initial begin
		$dumpfile ("C:/Users/Administrator/Desktop/robeimodel/counttest.vcd");
		$dumpvars;
	end
endmodule
module counttest();


	wire clk;
	wire countmax;


	count count1(
		.clk(clk),
		.countmax(countmax));

	initial
	begin
		clk=1'b0;
		#800000 $finish;
	end
	
	always #1 clk=~clk;
	
	initial begin
		$dumpfile ("C:/Users/Administrator/Desktop/robeimodel/counttest.vcd");
		$dumpvars;
	end
endmodule