data/full_repos/permissive/159902111/Single Cycle Processor/RF.v
1: b'%Error: Cannot find file containing module: Cycle\n        ... Looked in:\n             data/full_repos/permissive/159902111/Single/Cycle\n             data/full_repos/permissive/159902111/Single/Cycle.v\n             data/full_repos/permissive/159902111/Single/Cycle.sv\n             Cycle\n             Cycle.v\n             Cycle.sv\n             obj_dir/Cycle\n             obj_dir/Cycle.v\n             obj_dir/Cycle.sv\n%Error: Cannot find file containing module: Processor,data/full_repos/permissive/159902111\n%Error: Cannot find file containing module: data/full_repos/permissive/159902111/Single\n%Error: Cannot find file containing module: Processor/RF.v\n%Error: Exiting due to 4 error(s)\n'
module RF(
  input clk,
  input rst_n,
  input RegWrite_i,
  input [4:0]wa_i,
  input [4:0]ra1_i,
  input [4:0]ra2_i,
  input [31:0]wd_i,
  
  output [31:0]rd1_o,
  output [31:0]rd2_o
  );
  
  reg [31:0] Regfile [31:0];
  integer    i;
  
  always@(posedge clk or negedge rst_n)
  begin
    if (!rst_n)
      begin
        for (i = 1'b0; i < 32; i = i+1)
          Regfile[i] = 32'h0;
      end
    else
      begin
        if (RegWrite_i)
          begin
            Regfile[wa_i] = (!wa_i)? 32'h0 : wd_i;

          end
      end

  end

  assign rd1_o = Regfile[ra1_i];
  assign rd2_o = Regfile[ra2_i];
endmodule
module RF(
  input clk,
  input rst_n,
  input RegWrite_i,
  input [4:0]wa_i,
  input [4:0]ra1_i,
  input [4:0]ra2_i,
  input [31:0]wd_i,
  
  output [31:0]rd1_o,
  output [31:0]rd2_o
  );

  
  reg [31:0] Regfile [31:0];
  integer    i;
  
  always@(posedge clk or negedge rst_n)
  begin
    if (!rst_n)
      begin
        for (i = 1'b0; i < 32; i = i+1)
          Regfile[i] = 32'h0;
      end
    else
      begin
        if (RegWrite_i)
          begin
            Regfile[wa_i] = (!wa_i)? 32'h0 : wd_i;

          end
      end

  end

  assign rd1_o = Regfile[ra1_i];
  assign rd2_o = Regfile[ra2_i];
endmodule