data/full_repos/permissive/201025648/Verilog/3.1.v
 line:3: before: "output"
1: b"%Error: data/full_repos/permissive/201025648/Verilog/3.1.v:3: syntax error, unexpected output, expecting ';'\noutput oY;\n^~~~~~\n%Error: Exiting due to 1 error(s)\n"
module logic_gates(oY, iA, iB, iC)

output oY;

input iA,iB, iC;

and(and1, iA, iB)
and (and2, iA, iC)

or (oY, and1, and2);

endmodule
module logic_gates(oY, iA, iB, iC)

output oY;


input iA,iB, iC;

and(and1, iA, iB)
and (and2, iA, iC)

or (oY, and1, and2);

endmodule