data/full_repos/permissive/114091260/material/CPU设计代码/第三步/top_test.v
 line:37 column:13: Illegal character '"'
1: b'%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:39: Unsupported or unknown PLI call: $monitor\n  $monitor("%h : %b : %h : %h : %h : %h : %h : %b : %h : %h : %h : %h : %b : %b : %b", \n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10 rst <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #10 rst <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10 enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10 start <=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10 start <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:52: Unsupported: Ignoring delay on this delayed statement.\n always #5\n        ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_test;


	reg clk;
	reg enable;
	reg start;
	reg rst;
	reg [3:0] select_y;


	wire [15:0] y;


	top uut (
		.clk(clk), 
		.enable(enable), 
		.start(start), 
		.rst(rst), 
		.select_y(select_y), 
		.y(y)
	);

	initial begin

		clk = 0;
		enable = 0;
		start = 0;
		rst = 1;
		select_y = 0;


		#100;
        

		$display("pc :               id_ir                :reg_A :reg_B :reg_C\
: da  :  dd  : w : reC1 :  gr1  :  gr2  :  gr3   :zf :nf:cf");
		$monitor("%h : %b : %h : %h : %h : %h : %h : %b : %h : %h : %h : %h : %b : %b : %b", 
			uut.u_pcpu.pc, uut.u_pcpu.id_ir, uut.u_pcpu.reg_A, uut.u_pcpu.reg_B,
			uut.u_pcpu.reg_C, uut.d_addr, uut.d_dataout, uut.d_we, uut.u_pcpu.reg_C1,
			uut.u_pcpu.gr[1], uut.u_pcpu.gr[2], uut.u_pcpu.gr[3],
			uut.u_pcpu.zf, uut.u_pcpu.nf, uut.u_pcpu.cf);

		#10 rst <= 0;
		#10 rst <= 1;
		#10 enable <= 1;
		#10 start <=1;
		#10 start <= 0;
	end
	
	always #5
		clk = ~clk;
      
endmodule
module top_test;



	reg clk;
	reg enable;
	reg start;
	reg rst;
	reg [3:0] select_y;


	wire [15:0] y;


	top uut (
		.clk(clk), 
		.enable(enable), 
		.start(start), 
		.rst(rst), 
		.select_y(select_y), 
		.y(y)
	);

	initial begin

		clk = 0;
		enable = 0;
		start = 0;
		rst = 1;
		select_y = 0;


		#100;
        

		$display("pc :               id_ir                :reg_A :reg_B :reg_C\
: da  :  dd  : w : reC1 :  gr1  :  gr2  :  gr3   :zf :nf:cf");
		$monitor("%h : %b : %h : %h : %h : %h : %h : %b : %h : %h : %h : %h : %b : %b : %b", 
			uut.u_pcpu.pc, uut.u_pcpu.id_ir, uut.u_pcpu.reg_A, uut.u_pcpu.reg_B,
			uut.u_pcpu.reg_C, uut.d_addr, uut.d_dataout, uut.d_we, uut.u_pcpu.reg_C1,
			uut.u_pcpu.gr[1], uut.u_pcpu.gr[2], uut.u_pcpu.gr[3],
			uut.u_pcpu.zf, uut.u_pcpu.nf, uut.u_pcpu.cf);

		#10 rst <= 0;
		#10 rst <= 1;
		#10 enable <= 1;
		#10 start <=1;
		#10 start <= 0;
	end
	
	always #5
		clk = ~clk;
      
endmodule