data/full_repos/permissive/211316121/lab8_2_nexys4/Display.v
data/verilator_xmls/6768e043-c1d4-4bd6-ae9b-77158dc57bba.xml
module clkdiv_7seg(
    input mclk,
    output [2:0] clk_seg
    );
    reg [27:0] q;
    always@(posedge mclk)
         q<=q+1;
    assign clk_seg[0]=q[15];
    assign clk_seg[1]=q[16];
    assign clk_seg[2]=q[17];       
endmodule
module clkdiv_7seg(
    input mclk,
    output [2:0] clk_seg
    );

    reg [27:0] q;
    always@(posedge mclk)
         q<=q+1;
    assign clk_seg[0]=q[15];
    assign clk_seg[1]=q[16];
    assign clk_seg[2]=q[17];       
endmodule