data/full_repos/permissive/113268705/FPGA_SPI/tb_FPGA_SPI.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_SPI/tb_FPGA_SPI.v:65: Unsupported: Ignoring delay on this delayed statement.\n   #500 ss = 0;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_SPI/tb_FPGA_SPI.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_SPI/tb_FPGA_SPI.v:45: Little bit endian vector: MSB < LSB of bit range: 0:7\n reg [0:7] data_in;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/113268705/FPGA_SPI/tb_FPGA_SPI.v:46: Little bit endian vector: MSB < LSB of bit range: 0:7\n reg[0:7] data_out;\n    ^\n%Error: data/full_repos/permissive/113268705/FPGA_SPI/tb_FPGA_SPI.v:90: Cannot find file containing module: \'FPGA_SPI\'\n FPGA_SPI spi(.CLK(clk),.SCLK(sclk),.MOSI(mosi),.MISO(miso),.SS(ss));\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113268705/FPGA_SPI,data/full_repos/permissive/113268705/FPGA_SPI\n             data/full_repos/permissive/113268705/FPGA_SPI,data/full_repos/permissive/113268705/FPGA_SPI.v\n             data/full_repos/permissive/113268705/FPGA_SPI,data/full_repos/permissive/113268705/FPGA_SPI.sv\n             FPGA_SPI\n             FPGA_SPI.v\n             FPGA_SPI.sv\n             obj_dir/FPGA_SPI\n             obj_dir/FPGA_SPI.v\n             obj_dir/FPGA_SPI.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_FPGA_SPI;
	reg clk;
	

	
	reg sclk;
	reg mosi,ss;
	wire miso;
	
	integer div_clk,i;
	
	reg [0:7] data_in;
	reg[0:7] data_out;
	
	initial begin
		clk = 0;
		sclk = 0;
		mosi = 0;
		ss = 1;
		div_clk = 0;
		
		data_in = 8'h0;
		data_out = 8'h0;
		i = 0;
	end
	
	always @(posedge clk) begin
		if(ss==1) begin
			div_clk = 0;
			sclk = 0;
			data_out <= data_in;
			#500 ss = 0;
		end
		div_clk = div_clk + 1;
		if(sclk == 0) begin
			mosi = data_out[i];
		end
		
		if(div_clk == 5) begin
			div_clk = 0;
			sclk = ~sclk;
			if(sclk == 1) begin
				data_in[i] = miso;
				i = i + 1;
			end else begin
				if(i == 8) begin
					i = 0;
					ss = 1;
				end
			end
		end
	end
	
	always begin
		#10 clk = ~clk;
	end
	FPGA_SPI spi(.CLK(clk),.SCLK(sclk),.MOSI(mosi),.MISO(miso),.SS(ss));
	
endmodule
module tb_FPGA_SPI;

	reg clk;
	

	
	reg sclk;
	reg mosi,ss;
	wire miso;
	
	integer div_clk,i;
	
	reg [0:7] data_in;
	reg[0:7] data_out;
	
	initial begin
		clk = 0;
		sclk = 0;
		mosi = 0;
		ss = 1;
		div_clk = 0;
		
		data_in = 8'h0;
		data_out = 8'h0;
		i = 0;
	end
	
	always @(posedge clk) begin
		if(ss==1) begin
			div_clk = 0;
			sclk = 0;
			data_out <= data_in;
			#500 ss = 0;
		end
		div_clk = div_clk + 1;
		if(sclk == 0) begin
			mosi = data_out[i];
		end
		
		if(div_clk == 5) begin
			div_clk = 0;
			sclk = ~sclk;
			if(sclk == 1) begin
				data_in[i] = miso;
				i = i + 1;
			end else begin
				if(i == 8) begin
					i = 0;
					ss = 1;
				end
			end
		end
	end
	
	always begin
		#10 clk = ~clk;
	end
	FPGA_SPI spi(.CLK(clk),.SCLK(sclk),.MOSI(mosi),.MISO(miso),.SS(ss));
	
endmodule