data/full_repos/permissive/113582216/Experiment/design/main.v
1: b"%Error: data/full_repos/permissive/113582216/Experiment/design/main.v:42: Cannot find file containing module: 'clkGen'\n    clkGen u1(\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113582216/Experiment/design,data/full_repos/permissive/113582216/clkGen\n             data/full_repos/permissive/113582216/Experiment/design,data/full_repos/permissive/113582216/clkGen.v\n             data/full_repos/permissive/113582216/Experiment/design,data/full_repos/permissive/113582216/clkGen.sv\n             clkGen\n             clkGen.v\n             clkGen.sv\n             obj_dir/clkGen\n             obj_dir/clkGen.v\n             obj_dir/clkGen.sv\n%Error: data/full_repos/permissive/113582216/Experiment/design/main.v:47: Cannot find file containing module: 'controller'\n    controller u2(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/113582216/Experiment/design/main.v:57: Cannot find file containing module: 'digitDisplay'\n    digitDisplay u3(\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113582216/Experiment/design/main.v:75: Cannot find file containing module: 'keyPress'\n    keyPress u4(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/113582216/Experiment/design/main.v:81: Cannot find file containing module: 'keyClick'\n    keyClick u5(\n    ^~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module main(
    input clk,
    input [1:0] btn,
    output [3:0] an,
    output ca,
    output cb,
    output cc,
    output cd,
    output ce,
    output cf,
    output cg,
    output dp
    );

    wire clk5ms;
    wire rst, toggle;
    wire [3:0] dsec;
    wire [3:0] sec0;
    wire [3:0] sec1;
    wire [3:0] min;

    clkGen u1(
    .clk50MHz_i (clk),
    .clk5ms_o   (clk5ms)
    );

    controller u2(
    .rst_i      (rst),
    .toggle_i   (toggle),
    .clk_i      (clk5ms),
    .dsec_o     (dsec),
    .sec0_o     (sec0),
    .sec1_o     (sec1),
    .min_o      (min)
    );

    digitDisplay u3(
    .bcd_i0     (dsec),
    .bcd_i1     (sec0),
    .bcd_i2     (sec1),
    .bcd_i3     (min),
    .dp_i       (4'b0101),
    .clk_i      (clk5ms),
    .sel_o      (an),
    .a_o        (ca),
    .b_o        (cb),
    .c_o        (cc),
    .d_o        (cd),
    .e_o        (ce),
    .f_o        (cf),
    .g_o        (cg),
    .dp_o       (dp)
    );

    keyPress u4(
    .key_i      (btn[1]),
    .pressed_o  (rst),
    .clk_i      (clk5ms)
    );

    keyClick u5(
    .key_i      (btn[0]),
    .clicked_o  (toggle),
    .clk_i      (clk5ms)
    );

endmodule
module main(
    input clk,
    input [1:0] btn,
    output [3:0] an,
    output ca,
    output cb,
    output cc,
    output cd,
    output ce,
    output cf,
    output cg,
    output dp
    );


    wire clk5ms;
    wire rst, toggle;
    wire [3:0] dsec;
    wire [3:0] sec0;
    wire [3:0] sec1;
    wire [3:0] min;

    clkGen u1(
    .clk50MHz_i (clk),
    .clk5ms_o   (clk5ms)
    );

    controller u2(
    .rst_i      (rst),
    .toggle_i   (toggle),
    .clk_i      (clk5ms),
    .dsec_o     (dsec),
    .sec0_o     (sec0),
    .sec1_o     (sec1),
    .min_o      (min)
    );

    digitDisplay u3(
    .bcd_i0     (dsec),
    .bcd_i1     (sec0),
    .bcd_i2     (sec1),
    .bcd_i3     (min),
    .dp_i       (4'b0101),
    .clk_i      (clk5ms),
    .sel_o      (an),
    .a_o        (ca),
    .b_o        (cb),
    .c_o        (cc),
    .d_o        (cd),
    .e_o        (ce),
    .f_o        (cf),
    .g_o        (cg),
    .dp_o       (dp)
    );

    keyPress u4(
    .key_i      (btn[1]),
    .pressed_o  (rst),
    .clk_i      (clk5ms)
    );

    keyClick u5(
    .key_i      (btn[0]),
    .clicked_o  (toggle),
    .clk_i      (clk5ms)
    );

endmodule