data/full_repos/permissive/207835546/FSM/traffic_light.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/207835546/FSM/traffic_light.v:4: Little bit endian vector: MSB < LSB of bit range: 0:2\noutput reg [0:2]light;\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/207835546/FSM/traffic_light.v:7: Little bit endian vector: MSB < LSB of bit range: 0:1\nreg[0:1]state;\n   ^\n%Error: Exiting due to 2 warning(s)\n'
module cyclic_lamp(clk,light);

input clk;
output reg [0:2]light;
parameter S0=0,S1=1,S2=2;
parameter RED=3'b100,GREEN=3'b010,YELLOW=3'b001;
reg[0:1]state;
always @(posedge clk)
	case (state)
		S0:begin
			light<=GREEN; state<=S1;
			end
		S1: begin
			light <=YELLOW; state<=S2;
			end
		S2:begin 
			light<=RED; state<=S0;
			end
		default:begin 
			light<=RED;
			state<=S0;
			end
	endcase
endmodule
module cyclic_lamp(clk,light);


input clk;
output reg [0:2]light;
parameter S0=0,S1=1,S2=2;
parameter RED=3'b100,GREEN=3'b010,YELLOW=3'b001;
reg[0:1]state;
always @(posedge clk)
	case (state)
		S0:begin
			light<=GREEN; state<=S1;
			end
		S1: begin
			light <=YELLOW; state<=S2;
			end
		S2:begin 
			light<=RED; state<=S0;
			end
		default:begin 
			light<=RED;
			state<=S0;
			end
	endcase
endmodule