data/full_repos/permissive/118082957/testbench/indiv_tb.v
 line:17: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #10 $display ("A = %b B = %b opALU = %b || Rout = %b", A, B, opALU, Rout);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #10 $display ("A = %b B = %b opALU = %b || Rout = %b", A, B, opALU, Rout);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10 rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #10 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10 $display ("Q = %h", q);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#435\n^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n%Error: data/full_repos/permissive/118082957/testbench/indiv_tb.v:100: Unsupported or unknown PLI call: $monitor\n$monitor("ADDR 0002: %d \\n",$time,CPUTEST.dut.ram_ins.mem256x16[16\'h0002]);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n#20 rst=1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/testbench/indiv_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n#10000\n^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPUTEST;
reg clk, rst;
wire MemRW_IO;
wire [7:0]MemAddr_IO;
wire [15:0]MemD_IO;

	proj1 dut(clk, rst, MemRW_IO, MemAddr_IO, MemD_IO);

always
 #5 clk = !clk;

initial begin
$monitor("ADDR 0002: %d \n",$time,CPUTEST.dut.ram_ins.mem256x16[16'h0002]);
clk=1'b0;
rst=1'b1;
$readmemh("memory_copy.list", CPUTEST.dut.ram_ins.mem256x16);
#20 rst=1'b0;
#10000

$finish;
end
endmodule
module CPUTEST;

reg clk, rst;
wire MemRW_IO;
wire [7:0]MemAddr_IO;
wire [15:0]MemD_IO;

	proj1 dut(clk, rst, MemRW_IO, MemAddr_IO, MemD_IO);

always
 #5 clk = !clk;

initial begin
$monitor("ADDR 0002: %d \n",$time,CPUTEST.dut.ram_ins.mem256x16[16'h0002]);
clk=1'b0;
rst=1'b1;
$readmemh("memory_copy.list", CPUTEST.dut.ram_ins.mem256x16);
#20 rst=1'b0;
#10000

$finish;
end
endmodule