data/full_repos/permissive/154590168/rtl_cpu/DmAdConv.v
data/verilator_xmls/42bd7770-53d9-4b8f-9fd5-c07e4f955735.xml
module  DmAdConv (
    input   [15:0]  mm_addr,
    input           mm_en,
    output  [15:0]  dm_addr,
    output          dm_en,
    output  [7:0]   io_addr,
    output          io_en
);

wire    dm_bo;
wire    io_bo;

assign  {dm_bo, dm_addr} = mm_addr - 16'h100;
assign  dm_en = mm_en & ~dm_bo;

assign  {io_bo, io_addr} = mm_addr[7:0] - 8'h20;
assign  io_en = mm_en & dm_bo & ~io_bo;

endmodule
module  DmAdConv (
    input   [15:0]  mm_addr,
    input           mm_en,
    output  [15:0]  dm_addr,
    output          dm_en,
    output  [7:0]   io_addr,
    output          io_en
);


wire    dm_bo;
wire    io_bo;

assign  {dm_bo, dm_addr} = mm_addr - 16'h100;
assign  dm_en = mm_en & ~dm_bo;

assign  {io_bo, io_addr} = mm_addr[7:0] - 8'h20;
assign  io_en = mm_en & dm_bo & ~io_bo;

endmodule