data/full_repos/permissive/143278/ivltests/pr1694427.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1694427.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (b !== 0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1694427.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (b !== 1) begin\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ();

   reg[7:0]   a;
   reg        b;

   always @*
     begin
	b = 1'b0;
	case (a)
	  8'd66: b = 1'b1;
	  default:		        ;
	endcase
     end

   initial begin
      a = 0;
      #1 if (b !== 0) begin
	 $display("FAILED  -- a=%h  b=%b", a, b);
	 $finish;
      end

      a = 66;
      #1 if (b !== 1) begin
	 $display("FAILED  -- a=%h  b=%b", a, b);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module test ();


   reg[7:0]   a;
   reg        b;

   always @*
     begin
	b = 1'b0;
	case (a)
	  8'd66: b = 1'b1;
	  default:		        ;
	endcase
     end

   initial begin
      a = 0;
      #1 if (b !== 0) begin
	 $display("FAILED  -- a=%h  b=%b", a, b);
	 $finish;
      end

      a = 66;
      #1 if (b !== 1) begin
	 $display("FAILED  -- a=%h  b=%b", a, b);
	 $finish;
      end

      $display("PASSED");
   end
endmodule