data/full_repos/permissive/213397499/verilog/bfp_krnl.v
1: b"%Error: data/full_repos/permissive/213397499/verilog/bfp_krnl.v:68: Cannot find file containing module: 'bfp_compute_engine'\nbfp_compute_engine #(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/213397499/verilog,data/full_repos/permissive/213397499/bfp_compute_engine\n             data/full_repos/permissive/213397499/verilog,data/full_repos/permissive/213397499/bfp_compute_engine.v\n             data/full_repos/permissive/213397499/verilog,data/full_repos/permissive/213397499/bfp_compute_engine.sv\n             bfp_compute_engine\n             bfp_compute_engine.v\n             bfp_compute_engine.sv\n             obj_dir/bfp_compute_engine\n             obj_dir/bfp_compute_engine.v\n             obj_dir/bfp_compute_engine.sv\n%Error: Exiting due to 1 error(s)\n"
module bfp_krnl
# (

  parameter pc = 64,

  parameter in_data_width=8,

  parameter out_data_width=32
)
(
  input  wire                        clk,
  input  wire                        rst_n,


  input  wire  [pc*in_data_width-1:0]  coef,
  output  wire                          coef_rdy,
  input  wire                          coef_vld,

  input  wire                           up_vld,
  input  wire  [pc*in_data_width-1:0]  up_dat,
  output wire                           up_rdy,


  input wire    [4:0]               shift_bits,


  input  wire                        filter_finish_data,


  output wire                        filter_finish_cal,

  input  wire  [32-1:0]      bias_dat,
  input  wire                        bias_vld,

  input  wire                           acc_result_vld,


  output wire                        dn_vld,
  output wire  [in_data_width-1:0]    dn_dat,
  input  wire                        dn_rdy

);
wire                    ce_up_vld;
wire                    acc_result_vld_real;
wire                    ce_up_rdy;
assign acc_result_vld_real = acc_result_vld & up_vld & coef_vld;



assign ce_up_vld = up_vld & dn_rdy;

assign up_rdy = ce_up_rdy & coef_vld & up_vld;
assign coef_rdy = up_rdy;

localparam PE = 4;
localparam ENABLE_8OUT = 1;
localparam LATENCY_ADD = 1;
localparam LATENCY_MUL = 2;

bfp_compute_engine #(
    .pc(pc),
    .pe(PE),
    .in_data_width(in_data_width),
    .out_data_width(out_data_width),
    .latency_add(LATENCY_ADD),
    .latency_mul(LATENCY_MUL),
    .bias_data_width(32)
) u_compute_engine
(
    .rst_n(rst_n),
    .clk(clk),
    .coef(coef),
    .coef_vld(coef_vld),
    .up_vld(ce_up_vld),
    .up_dat(up_dat),
    .up_rdy(ce_up_rdy),
    .shift_bits(shift_bits),
    .filter_finish_data(filter_finish_data),
    .filter_finish_cal(filter_finish_cal),
    .bias_dat(bias_dat),
    .bias_vld(bias_vld),
    .acc_result_vld(acc_result_vld_real),
    .dn_vld(dn_vld),
    .dn_dat(dn_dat),
    .dn_rdy(dn_rdy)
); 
endmodule
module bfp_krnl
# (

  parameter pc = 64,

  parameter in_data_width=8,

  parameter out_data_width=32
)
(
  input  wire                        clk,
  input  wire                        rst_n,


  input  wire  [pc*in_data_width-1:0]  coef,
  output  wire                          coef_rdy,
  input  wire                          coef_vld,

  input  wire                           up_vld,
  input  wire  [pc*in_data_width-1:0]  up_dat,
  output wire                           up_rdy,


  input wire    [4:0]               shift_bits,


  input  wire                        filter_finish_data,


  output wire                        filter_finish_cal,

  input  wire  [32-1:0]      bias_dat,
  input  wire                        bias_vld,

  input  wire                           acc_result_vld,


  output wire                        dn_vld,
  output wire  [in_data_width-1:0]    dn_dat,
  input  wire                        dn_rdy

);

wire                    ce_up_vld;
wire                    acc_result_vld_real;
wire                    ce_up_rdy;
assign acc_result_vld_real = acc_result_vld & up_vld & coef_vld;



assign ce_up_vld = up_vld & dn_rdy;

assign up_rdy = ce_up_rdy & coef_vld & up_vld;
assign coef_rdy = up_rdy;

localparam PE = 4;
localparam ENABLE_8OUT = 1;
localparam LATENCY_ADD = 1;
localparam LATENCY_MUL = 2;

bfp_compute_engine #(
    .pc(pc),
    .pe(PE),
    .in_data_width(in_data_width),
    .out_data_width(out_data_width),
    .latency_add(LATENCY_ADD),
    .latency_mul(LATENCY_MUL),
    .bias_data_width(32)
) u_compute_engine
(
    .rst_n(rst_n),
    .clk(clk),
    .coef(coef),
    .coef_vld(coef_vld),
    .up_vld(ce_up_vld),
    .up_dat(up_dat),
    .up_rdy(ce_up_rdy),
    .shift_bits(shift_bits),
    .filter_finish_data(filter_finish_data),
    .filter_finish_cal(filter_finish_cal),
    .bias_dat(bias_dat),
    .bias_vld(bias_vld),
    .acc_result_vld(acc_result_vld_real),
    .dn_vld(dn_vld),
    .dn_dat(dn_dat),
    .dn_rdy(dn_rdy)
); 
endmodule