data/full_repos/permissive/118082957/main/proj1.v
 line:18: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:10: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20 rst=1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:17: Unsupported: Ignoring delay on this delayed statement.\n#435\n^\n%Warning-IMPLICIT: data/full_repos/permissive/118082957/main/proj1.v:648: Signal definition not found, creating implicitly: \'Zflag_reg\'\n   MAR_next, Zflag_reg, zflag_next);\n             ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/118082957/main/proj1.v:648: Signal definition not found, creating implicitly: \'zflag_next\'\n   MAR_next, Zflag_reg, zflag_next);\n                        ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/118082957/main/proj1.v:696: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'ACC_reg\' generates 16 bits.\n                                                                     : ... In instance tb_proj1.dut.datapath\n zflag = (!ACC_reg)? 1:0;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/118082957/main/proj1.v:19: Bit extraction of array[255:0] requires 8 bit index, not 16 bits.\n                                                                    : ... In instance tb_proj1\n$display("0x00d %d\\n",tb_proj1.dut.ram_ins.mem256x16[16\'h000d]);\n                                                    ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ctr (
 clk,
 rst,
 zflag,
 opcode,
 muxPC,
 muxMAR,
 muxACC,
 loadMAR,
 loadPC,
 loadACC,
 loadMDR,
 loadIR,
 opALU,
 MemRW
);
 input clk;
 input rst;
 input zflag;
 input [7:0]opcode;
 output reg muxPC;
 output reg muxMAR;
 output reg muxACC;
 output reg loadMAR;
 output reg loadPC;
 output reg loadACC;
 output reg loadMDR;
 output reg loadIR;
 output reg [1:0] opALU;
 output reg MemRW;


parameter op_add=8'b001;
parameter op_or= 8'b010;
parameter op_jump=8'b011;
parameter op_jumpz=8'b100;
parameter op_load=8'b101;
parameter op_store=8'b110;


parameter op_halt = 8'b000;
parameter op_sub = 8'b111;
parameter op_and = 8'h08;







/
reg [4:0] CURRENT_STATE;
reg [4:0] NEXT_STATE;
parameter FETCH_1 		= 5'b00000;
parameter FETCH_2 		= 5'b00001;
parameter FETCH_3 		= 5'b00010;
parameter DECODE 		= 5'b00011;
parameter EXECADD_1 	= 5'b00100;
parameter EXECADD_2		= 5'b00101;
parameter EXECOR_1		= 5'b00110;
parameter EXECOR_2		= 5'b00111;
parameter EXECLOAD_1	= 5'b01000;
parameter EXECLOAD_2	= 5'b01001;
parameter EXECSTORE_1	= 5'b01010;
parameter EXECJUMP		= 5'b01011;


parameter HALT_STATE	= 5'b01100;
parameter EXECSUB_1     = 5'b01101;
parameter EXECSUB_2     = 5'b01110;
parameter EXECAND_1		= 5'b01111;
parameter EXECAND_2		= 5'b10000;
parameter BUFFER_JUMP	= 5'b10001;

always @(posedge clk) begin


	if (rst)
		CURRENT_STATE = FETCH_1;
	else
		CURRENT_STATE = NEXT_STATE;
		
end 

always @(CURRENT_STATE or opcode or zflag) begin

	case (CURRENT_STATE)
			FETCH_1:
				NEXT_STATE = FETCH_2;
			FETCH_2:
				NEXT_STATE = FETCH_3;
			FETCH_3:
				NEXT_STATE = DECODE;
			DECODE: begin
			
			case (opcode)
				op_add:   begin NEXT_STATE = EXECADD_1;   end
				op_or:    begin NEXT_STATE = EXECOR_1;    end
				op_jump:  begin NEXT_STATE = EXECJUMP;    end
				op_jumpz: begin if (zflag) begin 
							NEXT_STATE = EXECJUMP; 
						  end else begin 
							NEXT_STATE = FETCH_1; 
						  end 
						  end
				op_load:  begin NEXT_STATE = EXECLOAD_1;  end
				op_store: begin NEXT_STATE = EXECSTORE_1; end
				op_halt:  begin NEXT_STATE = HALT_STATE;  end
				op_sub:   begin NEXT_STATE = EXECSUB_1;   end
				op_and:   begin NEXT_STATE = EXECAND_1;   end
				default:  begin NEXT_STATE = HALT_STATE;  end
			endcase  
			end 

			EXECADD_1:
				NEXT_STATE = EXECADD_2;
			EXECADD_2:
				NEXT_STATE = FETCH_1;
			EXECOR_1:
				NEXT_STATE = EXECOR_2;
			EXECOR_2:
				NEXT_STATE = FETCH_1;
			EXECLOAD_1:
				NEXT_STATE = EXECLOAD_2;
			EXECLOAD_2:
				NEXT_STATE = FETCH_1;
			EXECSTORE_1:
				NEXT_STATE = FETCH_1;
			EXECJUMP:
				NEXT_STATE = FETCH_1;
			HALT_STATE:
				NEXT_STATE = HALT_STATE;
			EXECSUB_1: 
				NEXT_STATE = EXECSUB_2;
			EXECSUB_2:
				NEXT_STATE = FETCH_1;
			EXECAND_1:
				NEXT_STATE = EXECAND_2;
			EXECAND_2:
				NEXT_STATE = FETCH_1;
			BUFFER_JUMP:
				NEXT_STATE = FETCH_1;
	endcase
	
end

	always @(CURRENT_STATE) begin
		
		muxPC = 0; 
		muxMAR = 0;
		muxACC = 0;
		loadMAR = 0;
		loadPC = 0;
		loadACC = 0;
		loadMDR = 0;
		loadIR = 0;
		opALU = 0;
		MemRW = 0;
		
		case (CURRENT_STATE)
		FETCH_1:     begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 1;
				loadPC = 1;
				loadACC = 0;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
			    end

		FETCH_2:     begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 1;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
			    end

		FETCH_3:     begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 0;
				loadIR = 1;
				opALU = 0;
				MemRW = 0;
			    end

		DECODE:      begin
				muxPC = 0; 
				muxMAR = 1;
				muxACC = 0;
				loadMAR = 1;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
			     end

		EXECADD_1:   begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 1;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
			    end

		EXECADD_2:   begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 1;
				loadMDR = 0;
				loadIR = 0;
				opALU = 1;
				MemRW = 0;
			    end

		EXECOR_1:    begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 1;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;			
			    end

		EXECOR_2:    begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 1;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;			
			    end

		EXECLOAD_1:  begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 1;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;			
				end

		EXECLOAD_2:  begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 1;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 1;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;			
			    end

		EXECSTORE_1: begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 1;			
			    end

		EXECJUMP:    begin
				muxPC = 1; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 1;
				loadACC = 0;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;			
			    end
		EXECSUB_1:   begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 1;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
			    end

		EXECSUB_2:   begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 1;
				loadMDR = 0;
				loadIR = 0;
				opALU = 2;
				MemRW = 0;
			    end
		EXECAND_1:   begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 1;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
			    end

		EXECAND_2:   begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 1;
				loadMDR = 0;
				loadIR = 0;
				opALU = 3;
				MemRW = 0;
			    end	
		BUFFER_JUMP: begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 1;
				loadACC = 0;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
				end
	endcase
end 
endmodule
module ctr (
 clk,
 rst,
 zflag,
 opcode,
 muxPC,
 muxMAR,
 muxACC,
 loadMAR,
 loadPC,
 loadACC,
 loadMDR,
 loadIR,
 opALU,
 MemRW
);

 input clk;
 input rst;
 input zflag;
 input [7:0]opcode;
 output reg muxPC;
 output reg muxMAR;
 output reg muxACC;
 output reg loadMAR;
 output reg loadPC;
 output reg loadACC;
 output reg loadMDR;
 output reg loadIR;
 output reg [1:0] opALU;
 output reg MemRW;


parameter op_add=8'b001;
parameter op_or= 8'b010;
parameter op_jump=8'b011;
parameter op_jumpz=8'b100;
parameter op_load=8'b101;
parameter op_store=8'b110;


parameter op_halt = 8'b000;
parameter op_sub = 8'b111;
parameter op_and = 8'h08;







/
reg [4:0] CURRENT_STATE;
reg [4:0] NEXT_STATE;
parameter FETCH_1 		= 5'b00000;
parameter FETCH_2 		= 5'b00001;
parameter FETCH_3 		= 5'b00010;
parameter DECODE 		= 5'b00011;
parameter EXECADD_1 	= 5'b00100;
parameter EXECADD_2		= 5'b00101;
parameter EXECOR_1		= 5'b00110;
parameter EXECOR_2		= 5'b00111;
parameter EXECLOAD_1	= 5'b01000;
parameter EXECLOAD_2	= 5'b01001;
parameter EXECSTORE_1	= 5'b01010;
parameter EXECJUMP		= 5'b01011;


parameter HALT_STATE	= 5'b01100;
parameter EXECSUB_1     = 5'b01101;
parameter EXECSUB_2     = 5'b01110;
parameter EXECAND_1		= 5'b01111;
parameter EXECAND_2		= 5'b10000;
parameter BUFFER_JUMP	= 5'b10001;

always @(posedge clk) begin


	if (rst)
		CURRENT_STATE = FETCH_1;
	else
		CURRENT_STATE = NEXT_STATE;
		
end 

always @(CURRENT_STATE or opcode or zflag) begin

	case (CURRENT_STATE)
			FETCH_1:
				NEXT_STATE = FETCH_2;
			FETCH_2:
				NEXT_STATE = FETCH_3;
			FETCH_3:
				NEXT_STATE = DECODE;
			DECODE: begin
			
			case (opcode)
				op_add:   begin NEXT_STATE = EXECADD_1;   end
				op_or:    begin NEXT_STATE = EXECOR_1;    end
				op_jump:  begin NEXT_STATE = EXECJUMP;    end
				op_jumpz: begin if (zflag) begin 
							NEXT_STATE = EXECJUMP; 
						  end else begin 
							NEXT_STATE = FETCH_1; 
						  end 
						  end
				op_load:  begin NEXT_STATE = EXECLOAD_1;  end
				op_store: begin NEXT_STATE = EXECSTORE_1; end
				op_halt:  begin NEXT_STATE = HALT_STATE;  end
				op_sub:   begin NEXT_STATE = EXECSUB_1;   end
				op_and:   begin NEXT_STATE = EXECAND_1;   end
				default:  begin NEXT_STATE = HALT_STATE;  end
			endcase  
			end 

			EXECADD_1:
				NEXT_STATE = EXECADD_2;
			EXECADD_2:
				NEXT_STATE = FETCH_1;
			EXECOR_1:
				NEXT_STATE = EXECOR_2;
			EXECOR_2:
				NEXT_STATE = FETCH_1;
			EXECLOAD_1:
				NEXT_STATE = EXECLOAD_2;
			EXECLOAD_2:
				NEXT_STATE = FETCH_1;
			EXECSTORE_1:
				NEXT_STATE = FETCH_1;
			EXECJUMP:
				NEXT_STATE = FETCH_1;
			HALT_STATE:
				NEXT_STATE = HALT_STATE;
			EXECSUB_1: 
				NEXT_STATE = EXECSUB_2;
			EXECSUB_2:
				NEXT_STATE = FETCH_1;
			EXECAND_1:
				NEXT_STATE = EXECAND_2;
			EXECAND_2:
				NEXT_STATE = FETCH_1;
			BUFFER_JUMP:
				NEXT_STATE = FETCH_1;
	endcase
	
end

	always @(CURRENT_STATE) begin
		
		muxPC = 0; 
		muxMAR = 0;
		muxACC = 0;
		loadMAR = 0;
		loadPC = 0;
		loadACC = 0;
		loadMDR = 0;
		loadIR = 0;
		opALU = 0;
		MemRW = 0;
		
		case (CURRENT_STATE)
		FETCH_1:     begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 1;
				loadPC = 1;
				loadACC = 0;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
			    end

		FETCH_2:     begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 1;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
			    end

		FETCH_3:     begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 0;
				loadIR = 1;
				opALU = 0;
				MemRW = 0;
			    end

		DECODE:      begin
				muxPC = 0; 
				muxMAR = 1;
				muxACC = 0;
				loadMAR = 1;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
			     end

		EXECADD_1:   begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 1;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
			    end

		EXECADD_2:   begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 1;
				loadMDR = 0;
				loadIR = 0;
				opALU = 1;
				MemRW = 0;
			    end

		EXECOR_1:    begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 1;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;			
			    end

		EXECOR_2:    begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 1;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;			
			    end

		EXECLOAD_1:  begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 1;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;			
				end

		EXECLOAD_2:  begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 1;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 1;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;			
			    end

		EXECSTORE_1: begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 1;			
			    end

		EXECJUMP:    begin
				muxPC = 1; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 1;
				loadACC = 0;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;			
			    end
		EXECSUB_1:   begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 1;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
			    end

		EXECSUB_2:   begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 1;
				loadMDR = 0;
				loadIR = 0;
				opALU = 2;
				MemRW = 0;
			    end
		EXECAND_1:   begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 0;
				loadMDR = 1;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
			    end

		EXECAND_2:   begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 0;
				loadACC = 1;
				loadMDR = 0;
				loadIR = 0;
				opALU = 3;
				MemRW = 0;
			    end	
		BUFFER_JUMP: begin
				muxPC = 0; 
				muxMAR = 0;
				muxACC = 0;
				loadMAR = 0;
				loadPC = 1;
				loadACC = 0;
				loadMDR = 0;
				loadIR = 0;
				opALU = 0;
				MemRW = 0;
				end
	endcase
end 
endmodule