data/full_repos/permissive/160788788/mux.v
data/verilator_xmls/29ad692f-76e4-48cb-95b4-b685f1aab969.xml
module mux(in_1, in_0, op, out);
	input [31:0] in_1, in_0;
	input op;

	output [31:0] out;


	assign out = op ? in_1 : in_0;

endmodule
module mux(in_1, in_0, op, out);

	input [31:0] in_1, in_0;
	input op;

	output [31:0] out;


	assign out = op ? in_1 : in_0;

endmodule