data/full_repos/permissive/193669196/ahb_ic/rtl/monitor.v
 line:12: before: "["
1: b"%Error: data/full_repos/permissive/193669196/ahb_ic/rtl/monitor.v:18: Duplicate declaration of signal: 'start_addr'\n  input   wire [31:0] start_addr[NUM_MASTERS-1 :0],        \n                      ^~~~~~~~~~\n        data/full_repos/permissive/193669196/ahb_ic/rtl/monitor.v:17: ... Location of original declaration\n  input   wire [31:0] start_addr[NUM_MASTERS-1 :0],        \n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/193669196/ahb_ic/rtl/monitor.v:18: Duplicate declaration of port: 'start_addr'\n  input   wire [31:0] start_addr[NUM_MASTERS-1 :0],        \n                      ^~~~~~~~~~\n        data/full_repos/permissive/193669196/ahb_ic/rtl/monitor.v:17: ... Location of original declaration\n  input   wire [31:0] start_addr[NUM_MASTERS-1 :0],        \n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/193669196/ahb_ic/rtl/monitor.v:19: Can't find definition of variable: 'NUM_SLAVES'\n  output  reg         hsel_s[NUM_SLAVES-1 :0],          \n                             ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module monitor #(
  parameter NUM_MASTERS  = 16
  )(  

  input  wire         hclk,
  input  wire         hresetn,

  input   wire [ 1:0] htrans_m[NUM_MASTERS-1 :0],
  input   wire [31:0] haddr_m[NUM_MASTERS-1 :0],
  input   wire [ 2:0] hsize_m[NUM_MASTERS-1 :0],
  input   wire [31:0] hwdata_m[NUM_MASTERS-1 :0],
  input   wire        hwrite_m[NUM_MASTERS-1 :0],
  output  reg  [31:0] hrdata_m[NUM_MASTERS-1 :0],
  output  reg         hready_m[NUM_MASTERS-1 :0],
  output  reg         hresp_m[NUM_MASTERS-1 :0],

  input   wire [31:0] start_addr[NUM_MASTERS-1 :0],
  input   wire [31:0] start_addr[NUM_MASTERS-1 :0],
  output  reg         hsel_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] haddr_s[NUM_SLAVES-1 :0],
  output  reg  [ 2:0] hsize_s[NUM_SLAVES-1 :0],
  output  reg         hwrite_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] hwdata_s[NUM_SLAVES-1 :0],
  input   wire [31:0] hrdata_s[NUM_SLAVES-1 :0],
  input   wire        hready_s[NUM_SLAVES-1 :0],
  input   wire        hresp_s[NUM_SLAVES-1 :0]
);

endmodule
module monitor #(
  parameter NUM_MASTERS  = 16
  )(  

  input  wire         hclk,
  input  wire         hresetn,

  input   wire [ 1:0] htrans_m[NUM_MASTERS-1 :0],
  input   wire [31:0] haddr_m[NUM_MASTERS-1 :0],
  input   wire [ 2:0] hsize_m[NUM_MASTERS-1 :0],
  input   wire [31:0] hwdata_m[NUM_MASTERS-1 :0],
  input   wire        hwrite_m[NUM_MASTERS-1 :0],
  output  reg  [31:0] hrdata_m[NUM_MASTERS-1 :0],
  output  reg         hready_m[NUM_MASTERS-1 :0],
  output  reg         hresp_m[NUM_MASTERS-1 :0],

  input   wire [31:0] start_addr[NUM_MASTERS-1 :0],
  input   wire [31:0] start_addr[NUM_MASTERS-1 :0],
  output  reg         hsel_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] haddr_s[NUM_SLAVES-1 :0],
  output  reg  [ 2:0] hsize_s[NUM_SLAVES-1 :0],
  output  reg         hwrite_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] hwdata_s[NUM_SLAVES-1 :0],
  input   wire [31:0] hrdata_s[NUM_SLAVES-1 :0],
  input   wire        hready_s[NUM_SLAVES-1 :0],
  input   wire        hresp_s[NUM_SLAVES-1 :0]
);


endmodule