data/full_repos/permissive/108195533/IF_stage.v
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1: b"%Error: data/full_repos/permissive/108195533/IF_stage.v:1: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'WIDTH'\n                                                         : ... In instance IF_stage\nmodule IF_stage #(parameter MEM_WIDTH=8, parameter WIDTH, parameter OFF_WIDTH=6)(clk, reset, addr, instr, jump, stall, jumpOffset);\n                                                   ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module IF_stage #(parameter MEM_WIDTH=8, parameter WIDTH, parameter OFF_WIDTH=6)(clk, reset, addr, instr, jump, stall, jumpOffset);
	input clk, reset, jump, stall;
	output [WIDTH-1:0] instr;
	wire [WIDTH-1:0] instrRead;
	output [MEM_WIDTH-1:0] addr;
	input [OFF_WIDTH-1:0] jumpOffset;
	wire [MEM_WIDTH-1:0] jumpAddress;
	
	signExtend SE(.offset(jumpOffset), .fixed(jumpAddress));
	PC pcIF(.clk(clk), .reset(reset), .PCOut(addr), .PCIn(jumpAddress), .load(jump), .en(~stall));
	instrMem memIF(.addr(addr), .instr(instrRead));
	

	
	assign instr = instrRead;

endmodule
module IF_stage #(parameter MEM_WIDTH=8, parameter WIDTH, parameter OFF_WIDTH=6)(clk, reset, addr, instr, jump, stall, jumpOffset);

	input clk, reset, jump, stall;
	output [WIDTH-1:0] instr;
	wire [WIDTH-1:0] instrRead;
	output [MEM_WIDTH-1:0] addr;
	input [OFF_WIDTH-1:0] jumpOffset;
	wire [MEM_WIDTH-1:0] jumpAddress;
	
	signExtend SE(.offset(jumpOffset), .fixed(jumpAddress));
	PC pcIF(.clk(clk), .reset(reset), .PCOut(addr), .PCIn(jumpAddress), .load(jump), .en(~stall));
	instrMem memIF(.addr(addr), .instr(instrRead));
	

	
	assign instr = instrRead;

endmodule