data/full_repos/permissive/203526788/IceStick/UART_String/top.v
None: at end of input
1: b'%Error: data/full_repos/permissive/203526788/IceStick/UART_String/top.v:1: Cannot find include file: async.v\n`include "async.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203526788/IceStick/UART_String,data/full_repos/permissive/203526788/async.v\n             data/full_repos/permissive/203526788/IceStick/UART_String,data/full_repos/permissive/203526788/async.v.v\n             data/full_repos/permissive/203526788/IceStick/UART_String,data/full_repos/permissive/203526788/async.v.sv\n             async.v\n             async.v.v\n             async.v.sv\n             obj_dir/async.v\n             obj_dir/async.v.v\n             obj_dir/async.v.sv\n%Error: Exiting due to 1 error(s)\n'
module top(input wire CLK_IN);



	parameter ClkFrequency = 12000000;
	parameter Baud = 115200;


	
	wire pulse;
	wire done;
	PULSE_GEN #(.FREQ(1000)) sampler (CLK_IN, pulse);


	async_transmitter #(ClkFrequency, Baud) TXD(.clk(CLK_IN), .TxD(TX), .TxD_start(pulse), .TxD_data(8'd95), .TxD_busy(done));
	























endmodule
module top(input wire CLK_IN);




	parameter ClkFrequency = 12000000;
	parameter Baud = 115200;


	
	wire pulse;
	wire done;
	PULSE_GEN #(.FREQ(1000)) sampler (CLK_IN, pulse);


	async_transmitter #(ClkFrequency, Baud) TXD(.clk(CLK_IN), .TxD(TX), .TxD_start(pulse), .TxD_data(8'd95), .TxD_busy(done));
	























endmodule