data/full_repos/permissive/147690299/lab/12_comb_mux_1bit/tb/testbench.sv
 line:39: before: ")"
1: b'%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/12_comb_mux_1bit/tb/testbench.sv:24: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/12_comb_mux_1bit/tb/testbench.sv:26: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/12_comb_mux_1bit/tb/testbench.sv:28: Unsupported: Ignoring delay on this delayed statement.\n            #10\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/12_comb_mux_1bit/tb/testbench.sv:30: Unsupported: Ignoring delay on this delayed statement.\n            #5\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/12_comb_mux_1bit/tb/testbench.sv:32: Unsupported: Ignoring delay on this delayed statement.\n            #5;             \n            ^\n%Error: data/full_repos/permissive/147690299/lab/12_comb_mux_1bit/tb/testbench.sv:38: Unsupported or unknown PLI call: $monitor\n        $monitor("a=%b b=%b sel=%b y=%b", \n        ^~~~~~~~\n%Error: data/full_repos/permissive/147690299/lab/12_comb_mux_1bit/tb/testbench.sv:39: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                  a,   b,   sel,   y,   );\n                                        ^\n%Error: data/full_repos/permissive/147690299/lab/12_comb_mux_1bit/tb/testbench.sv:42: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;   \n        ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

    reg        a;
    reg        b;
    reg        sel;
    wire [4:0] y;
 

    lab_top dut
    (
        .idata0  ( a       ),
        .idata1  ( b       ),
        .sel     ( sel     ),
        .y       ( y       ) 
    );

    initial
        begin
            a = 1'b0;
            b = 1'b1;
            #5;
            sel = 1'b0;
            #10;
            sel = 1'b1;
            #10
            b = 1'b0;
            #5
            b = 1'b1;
            #5;
            $finish();
        end


    initial 
        $monitor("a=%b b=%b sel=%b y=%b", 
                  a,   b,   sel,   y,   );

    initial 
        $dumpvars;
endmodule
module testbench;


    reg        a;
    reg        b;
    reg        sel;
    wire [4:0] y;
 

    lab_top dut
    (
        .idata0  ( a       ),
        .idata1  ( b       ),
        .sel     ( sel     ),
        .y       ( y       ) 
    );

    initial
        begin
            a = 1'b0;
            b = 1'b1;
            #5;
            sel = 1'b0;
            #10;
            sel = 1'b1;
            #10
            b = 1'b0;
            #5
            b = 1'b1;
            #5;
            $finish();
        end


    initial 
        $monitor("a=%b b=%b sel=%b y=%b", 
                  a,   b,   sel,   y,   );

    initial 
        $dumpvars;
endmodule