data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v
1: b'%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:3: Cannot find include file: ../../define/global_def.v\n`include "../../define/global_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147520230/src/cpu/stage/WB,data/full_repos/permissive/147520230/../../define/global_def.v\n             data/full_repos/permissive/147520230/src/cpu/stage/WB,data/full_repos/permissive/147520230/../../define/global_def.v.v\n             data/full_repos/permissive/147520230/src/cpu/stage/WB,data/full_repos/permissive/147520230/../../define/global_def.v.sv\n             ../../define/global_def.v\n             ../../define/global_def.v.v\n             ../../define/global_def.v.sv\n             obj_dir/../../define/global_def.v\n             obj_dir/../../define/global_def.v.v\n             obj_dir/../../define/global_def.v.sv\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:9: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     result_in,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`DATA_BUS]     result_in,\n                          ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`REG_ADDR_BUS] write_reg_addr_in,\n    ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:11: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input   wire[`REG_ADDR_BUS] write_reg_addr_in,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`DATA_BUS]     write_hi_data_in,\n    ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:13: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     write_hi_data_in,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:14: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     write_lo_data_in,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:17: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     result_out,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire[`REG_ADDR_BUS] write_reg_addr_out,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:19: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  wire[`REG_ADDR_BUS] write_reg_addr_out,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:23: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire[`DATA_BUS]     write_hi_data_out,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:23: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     write_hi_data_out,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:24: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     write_lo_data_out\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:27: Define or directive not defined: \'`RST_ENABLE\'\n    assign  result_out          = (rst == `RST_ENABLE) ? `ZERO_WORD     : result_in;\n                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:27: Define or directive not defined: \'`ZERO_WORD\'\n    assign  result_out          = (rst == `RST_ENABLE) ? `ZERO_WORD     : result_in;\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:28: Define or directive not defined: \'`RST_ENABLE\'\n    assign  write_reg_en_out    = (rst == `RST_ENABLE) ? `WRITE_DISABLE : write_reg_en_in;\n                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:28: Define or directive not defined: \'`WRITE_DISABLE\'\n    assign  write_reg_en_out    = (rst == `RST_ENABLE) ? `WRITE_DISABLE : write_reg_en_in;\n                                                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:29: Define or directive not defined: \'`RST_ENABLE\'\n    assign  write_reg_addr_out  = (rst == `RST_ENABLE) ? `ZERO_REG_ADDR : write_reg_addr_in;\n                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:29: Define or directive not defined: \'`ZERO_REG_ADDR\'\n    assign  write_reg_addr_out  = (rst == `RST_ENABLE) ? `ZERO_REG_ADDR : write_reg_addr_in;\n                                                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:30: Define or directive not defined: \'`RST_ENABLE\'\n    assign  write_hilo_en_out   = (rst == `RST_ENABLE) ? `WRITE_DISABLE : write_hilo_en_in;\n                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:30: Define or directive not defined: \'`WRITE_DISABLE\'\n    assign  write_hilo_en_out   = (rst == `RST_ENABLE) ? `WRITE_DISABLE : write_hilo_en_in;\n                                                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:31: Define or directive not defined: \'`RST_ENABLE\'\n    assign  write_hi_data_out   = (rst == `RST_ENABLE) ? `ZERO_WORD     : write_hi_data_in;\n                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:31: Define or directive not defined: \'`ZERO_WORD\'\n    assign  write_hi_data_out   = (rst == `RST_ENABLE) ? `ZERO_WORD     : write_hi_data_in;\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:32: Define or directive not defined: \'`RST_ENABLE\'\n    assign  write_lo_data_out   = (rst == `RST_ENABLE) ? `ZERO_WORD     : write_lo_data_in;\n                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/WB/WB.v:32: Define or directive not defined: \'`ZERO_WORD\'\n    assign  write_lo_data_out   = (rst == `RST_ENABLE) ? `ZERO_WORD     : write_lo_data_in;\n                                                         ^~~~~~~~~~\n%Error: Exiting due to 26 error(s)\n'
module  WB(
    input   wire                rst,


    input   wire[`DATA_BUS]     result_in,
    input   wire                write_reg_en_in,
    input   wire[`REG_ADDR_BUS] write_reg_addr_in,
    input   wire                write_hilo_en_in,
    input   wire[`DATA_BUS]     write_hi_data_in,
    input   wire[`DATA_BUS]     write_lo_data_in,


    output  wire[`DATA_BUS]     result_out,
    output  wire                write_reg_en_out,
    output  wire[`REG_ADDR_BUS] write_reg_addr_out,


    output  wire                write_hilo_en_out,
    output  wire[`DATA_BUS]     write_hi_data_out,
    output  wire[`DATA_BUS]     write_lo_data_out
);

    assign  result_out          = (rst == `RST_ENABLE) ? `ZERO_WORD     : result_in;
    assign  write_reg_en_out    = (rst == `RST_ENABLE) ? `WRITE_DISABLE : write_reg_en_in;
    assign  write_reg_addr_out  = (rst == `RST_ENABLE) ? `ZERO_REG_ADDR : write_reg_addr_in;
    assign  write_hilo_en_out   = (rst == `RST_ENABLE) ? `WRITE_DISABLE : write_hilo_en_in;
    assign  write_hi_data_out   = (rst == `RST_ENABLE) ? `ZERO_WORD     : write_hi_data_in;
    assign  write_lo_data_out   = (rst == `RST_ENABLE) ? `ZERO_WORD     : write_lo_data_in;

endmodule
module  WB(
    input   wire                rst,


    input   wire[`DATA_BUS]     result_in,
    input   wire                write_reg_en_in,
    input   wire[`REG_ADDR_BUS] write_reg_addr_in,
    input   wire                write_hilo_en_in,
    input   wire[`DATA_BUS]     write_hi_data_in,
    input   wire[`DATA_BUS]     write_lo_data_in,


    output  wire[`DATA_BUS]     result_out,
    output  wire                write_reg_en_out,
    output  wire[`REG_ADDR_BUS] write_reg_addr_out,


    output  wire                write_hilo_en_out,
    output  wire[`DATA_BUS]     write_hi_data_out,
    output  wire[`DATA_BUS]     write_lo_data_out
);


    assign  result_out          = (rst == `RST_ENABLE) ? `ZERO_WORD     : result_in;
    assign  write_reg_en_out    = (rst == `RST_ENABLE) ? `WRITE_DISABLE : write_reg_en_in;
    assign  write_reg_addr_out  = (rst == `RST_ENABLE) ? `ZERO_REG_ADDR : write_reg_addr_in;
    assign  write_hilo_en_out   = (rst == `RST_ENABLE) ? `WRITE_DISABLE : write_hilo_en_in;
    assign  write_hi_data_out   = (rst == `RST_ENABLE) ? `ZERO_WORD     : write_hi_data_in;
    assign  write_lo_data_out   = (rst == `RST_ENABLE) ? `ZERO_WORD     : write_lo_data_in;

endmodule