data/full_repos/permissive/201196900/Verilog_Uart/uart_rx.v
data/verilator_xmls/35ca2887-76db-4401-a1b6-f45e392db0c9.xml
module UART_RX(input SYSCLK,
				input [7:0] DATA,
				input SEND,
				output reg BUSY_FLAG,
				output reg COMPLATE_FLAG,
				output reg ERROR_FLAG);



endmodule
module UART_RX(input SYSCLK,
				input [7:0] DATA,
				input SEND,
				output reg BUSY_FLAG,
				output reg COMPLATE_FLAG,
				output reg ERROR_FLAG);




endmodule