data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Reciprocal/Reciprocal_Pipelined.v
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1: b'%Error: Cannot find file containing module: Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Reciprocal/Reciprocal_Pipelined.v\n%Error: Exiting due to 3 error(s)\n'
module Reciprocal_Pipelined_GS
	  #(parameter 
				WL = 24,  
				LUT_addWidth = 12, 
				LUT_bits = 15,
				dWL = 27)
		(
			input CLK, nRST,
			input CE,
			input [WL-1:0] din,
			
			output [WL-1:0] dout
			
		);
			reg   [LUT_bits-1:0] LUT [2**LUT_addWidth-1:0];
			reg   [WL-1:0]  			  din_delay;
			wire  [dWL-1:0] 			  d1_net, r2_net;
			reg	[dWL-1:0] 			  p2;
			reg   [LUT_bits-1:0] 	  iniValue;
			reg   [LUT_bits-1 : 0] 	  iniValue_delay;
			reg   [LUT_bits-1 : 0] 	  iniValue_delay2;
			reg   [LUT_addWidth-1:0]  reg_cmp;


	always @*   reg_cmp <= din[WL-2 : WL-1-LUT_addWidth];
	always @ (posedge CLK) begin
			if(~nRST) begin
					din_delay <= 0;
					iniValue <= 0;
					p2 <= 0;
					iniValue_delay <= 0;
					iniValue_delay2 <= 0;
			end else begin
				if (CE) begin
					din_delay <= din;
					iniValue <= LUT[reg_cmp];
					iniValue_delay <= iniValue;
					iniValue_delay2 <= iniValue_delay;
					p2 <= ~d1_net;
				end
			end
	end		

mult_unsigned_pipe #(.WI1(1), .WF1(LUT_bits-1), .WI2(1), .WF2(WL-1), .WIO(1), .WFO(dWL-1)) multiplier_1 
						  (.CLK(CLK), .RST(RST), .in1(iniValue), .in2(din_delay), .out(d1_net));


mult_unsigned_pipe #(.WI1(1), .WF1(LUT_bits-1), .WI2(1), .WF2(dWL-1), .WIO(1),.WFO(dWL-1)) multiplier_2 
						  (.CLK(CLK), .RST(RST), .in1(iniValue_delay2), .in2(p2), .out(r2_net));
		

		ux_round2nearest
			#(
				.WordLength(dWL),
				.RoundLength(dWL-WL)
			 )
		round_0 
			(
				.CLK(CLK),
				.RESET(RST),
				.CE(CE),
				.x(r2_net),
				.y(dout)
			 );			
		
endmodule
module Reciprocal_Pipelined_GS
	  #(parameter 
				WL = 24,  
				LUT_addWidth = 12, 
				LUT_bits = 15,
				dWL = 27)
		(
			input CLK, nRST,
			input CE,
			input [WL-1:0] din,
			
			output [WL-1:0] dout
			
		);

			reg   [LUT_bits-1:0] LUT [2**LUT_addWidth-1:0];
			reg   [WL-1:0]  			  din_delay;
			wire  [dWL-1:0] 			  d1_net, r2_net;
			reg	[dWL-1:0] 			  p2;
			reg   [LUT_bits-1:0] 	  iniValue;
			reg   [LUT_bits-1 : 0] 	  iniValue_delay;
			reg   [LUT_bits-1 : 0] 	  iniValue_delay2;
			reg   [LUT_addWidth-1:0]  reg_cmp;


	always @*   reg_cmp <= din[WL-2 : WL-1-LUT_addWidth];
	always @ (posedge CLK) begin
			if(~nRST) begin
					din_delay <= 0;
					iniValue <= 0;
					p2 <= 0;
					iniValue_delay <= 0;
					iniValue_delay2 <= 0;
			end else begin
				if (CE) begin
					din_delay <= din;
					iniValue <= LUT[reg_cmp];
					iniValue_delay <= iniValue;
					iniValue_delay2 <= iniValue_delay;
					p2 <= ~d1_net;
				end
			end
	end		

mult_unsigned_pipe #(.WI1(1), .WF1(LUT_bits-1), .WI2(1), .WF2(WL-1), .WIO(1), .WFO(dWL-1)) multiplier_1 
						  (.CLK(CLK), .RST(RST), .in1(iniValue), .in2(din_delay), .out(d1_net));


mult_unsigned_pipe #(.WI1(1), .WF1(LUT_bits-1), .WI2(1), .WF2(dWL-1), .WIO(1),.WFO(dWL-1)) multiplier_2 
						  (.CLK(CLK), .RST(RST), .in1(iniValue_delay2), .in2(p2), .out(r2_net));
		

		ux_round2nearest
			#(
				.WordLength(dWL),
				.RoundLength(dWL-WL)
			 )
		round_0 
			(
				.CLK(CLK),
				.RESET(RST),
				.CE(CE),
				.x(r2_net),
				.y(dout)
			 );			
		
endmodule