data/full_repos/permissive/201488448/2_circuits/1_combinational/03_nor.v
data/verilator_xmls/9628f18c-30be-4c92-8398-424dd4f23a88.xml
module top_module (
    input in1,
    input in2,
    output out);

    assign	out = ~(in1|in2);
    
endmodule
module top_module (
    input in1,
    input in2,
    output out);


    assign	out = ~(in1|in2);
    
endmodule