data/full_repos/permissive/202776140/memory_bidi_stim.v
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-STMTDLY: data/full_repos/permissive/202776140/memory_bidi_stim.v:30: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/202776140/memory_bidi_stim.v:38: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/202776140/memory_bidi_stim.v:44: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/202776140/memory_bidi_stim.v:51: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/202776140/memory_bidi_stim.v:58: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/202776140/memory_bidi_stim.v:65: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_bidi_stim (
    reset,
    clk,
    read_write,
    enable,
    address,
    data_in,
    data_out
);

output reg reset;
output reg clk;
output reg read_write;
output reg enable;
output reg [15:0] address;
output reg [15:0] data_out;
input wire [15:0] data_in;


initial begin
    reset = 1'b0;
    clk = 1'b0;
    read_write = 1'b1;
    enable = 1'b0;
    address = 16'h0000;
    data_out = {16{1'hz}};

#10
    reset = 1'b1;

    read_write = 1'b0;
    enable = 1'b1;
    address = 16'h0000;
    data_out = 16'h5A5A;

#10
    read_write = 1'b0;
    enable = 1'b1;
    address = 16'h0010;
    data_out = 16'hA5A5;

#10

    read_write = 1'b1;
    enable = 1'b0;
    address = 16'h0000;
    data_out = {16{1'hz}};

#10

    read_write = 1'b1;
    enable = 1'b1;
    address = 16'h0000;
    $display(data_in);

#10
    read_write = 1'b1;
    enable = 1'b1;
    address = 16'h0010;
    $display(data_in);
end

always #5 clk <= ~clk;

endmodule
module memory_bidi_stim (
    reset,
    clk,
    read_write,
    enable,
    address,
    data_in,
    data_out
);


output reg reset;
output reg clk;
output reg read_write;
output reg enable;
output reg [15:0] address;
output reg [15:0] data_out;
input wire [15:0] data_in;


initial begin
    reset = 1'b0;
    clk = 1'b0;
    read_write = 1'b1;
    enable = 1'b0;
    address = 16'h0000;
    data_out = {16{1'hz}};

#10
    reset = 1'b1;

    read_write = 1'b0;
    enable = 1'b1;
    address = 16'h0000;
    data_out = 16'h5A5A;

#10
    read_write = 1'b0;
    enable = 1'b1;
    address = 16'h0010;
    data_out = 16'hA5A5;

#10

    read_write = 1'b1;
    enable = 1'b0;
    address = 16'h0000;
    data_out = {16{1'hz}};

#10

    read_write = 1'b1;
    enable = 1'b1;
    address = 16'h0000;
    $display(data_in);

#10
    read_write = 1'b1;
    enable = 1'b1;
    address = 16'h0010;
    $display(data_in);
end

always #5 clk <= ~clk;

endmodule