data/full_repos/permissive/188643792/src/cdd.v
data/verilator_xmls/d76363d6-f27e-42c1-8b10-3547af15b746.xml
module cdd (
    clock,
    reset,
    data,
    out0,
    out1,
    out2,
    out3,
    out4,
    out5,
    ledr
);


    input clock;
    input reset;
    input [3:0] data;


    output reg [3:0] out0;
    output reg [3:0] out1;
    output reg [3:0] out2;
    output reg [3:0] out3;
    output reg [3:0] out4;
    output reg [3:0] out5;
    output [2:0] ledr;


    reg [3:0] shift_reg [5:0];
    reg [3:0] memory;
    reg [3:0] state;
    reg [2:0] counter;
    

    assign ledr = counter;


    parameter RESET  = 0;
    parameter WAIT   = 1;
    parameter OUTPUT = 2;
    parameter READ   = 3;
    parameter SHIFT  = 4;


    always@(posedge clock or negedge reset) begin
        if (!reset) begin
            state <= RESET;
        end else begin
            case (state)
                RESET:
                    state <= WAIT;

                WAIT:
                    if (counter == 3'd2) begin
                        state <= OUTPUT;
                    end

                OUTPUT:
                    if (counter == 3'd4) begin
                        state <= READ;
                    end

                READ:
                    if (counter == 3'd6) begin
                        state <= SHIFT;
                    end

                SHIFT:
                    if (counter == 3'd7) begin
                        state <= WAIT;
                    end
            endcase
        end
    end


    always@(posedge clock) begin
        case (state)
            RESET: begin
                out0 = 4'd0;
                out1 = 4'd0;
                out2 = 4'd0;
                out3 = 4'd0;
                out4 = 4'd0;
                out5 = 4'd0;
                counter = 3'd0;
            end

            WAIT: begin
                counter = counter + 1;
            end 

            OUTPUT: begin
                out0 <= shift_reg[0];
                out1 <= shift_reg[1];
                out2 <= shift_reg[2];
                out3 <= shift_reg[3];
                out4 <= shift_reg[4];
                out5 <= shift_reg[5];
                counter = counter + 1;
            end

            READ: begin
                memory <= data;
                counter = counter + 1;
            end

            SHIFT: begin        
                shift_reg[0] <= memory;
                shift_reg[1] <= shift_reg[0];
                shift_reg[2] <= shift_reg[1];
                shift_reg[3] <= shift_reg[2];
                shift_reg[4] <= shift_reg[3];
                shift_reg[5] <= shift_reg[4];
                counter = counter + 1;
            end
        endcase
    end
endmodule
module cdd (
    clock,
    reset,
    data,
    out0,
    out1,
    out2,
    out3,
    out4,
    out5,
    ledr
);



    input clock;
    input reset;
    input [3:0] data;


    output reg [3:0] out0;
    output reg [3:0] out1;
    output reg [3:0] out2;
    output reg [3:0] out3;
    output reg [3:0] out4;
    output reg [3:0] out5;
    output [2:0] ledr;


    reg [3:0] shift_reg [5:0];
    reg [3:0] memory;
    reg [3:0] state;
    reg [2:0] counter;
    

    assign ledr = counter;


    parameter RESET  = 0;
    parameter WAIT   = 1;
    parameter OUTPUT = 2;
    parameter READ   = 3;
    parameter SHIFT  = 4;


    always@(posedge clock or negedge reset) begin
        if (!reset) begin
            state <= RESET;
        end else begin
            case (state)
                RESET:
                    state <= WAIT;

                WAIT:
                    if (counter == 3'd2) begin
                        state <= OUTPUT;
                    end

                OUTPUT:
                    if (counter == 3'd4) begin
                        state <= READ;
                    end

                READ:
                    if (counter == 3'd6) begin
                        state <= SHIFT;
                    end

                SHIFT:
                    if (counter == 3'd7) begin
                        state <= WAIT;
                    end
            endcase
        end
    end


    always@(posedge clock) begin
        case (state)
            RESET: begin
                out0 = 4'd0;
                out1 = 4'd0;
                out2 = 4'd0;
                out3 = 4'd0;
                out4 = 4'd0;
                out5 = 4'd0;
                counter = 3'd0;
            end

            WAIT: begin
                counter = counter + 1;
            end 

            OUTPUT: begin
                out0 <= shift_reg[0];
                out1 <= shift_reg[1];
                out2 <= shift_reg[2];
                out3 <= shift_reg[3];
                out4 <= shift_reg[4];
                out5 <= shift_reg[5];
                counter = counter + 1;
            end

            READ: begin
                memory <= data;
                counter = counter + 1;
            end

            SHIFT: begin        
                shift_reg[0] <= memory;
                shift_reg[1] <= shift_reg[0];
                shift_reg[2] <= shift_reg[1];
                shift_reg[3] <= shift_reg[2];
                shift_reg[4] <= shift_reg[3];
                shift_reg[5] <= shift_reg[4];
                counter = counter + 1;
            end
        endcase
    end
endmodule