data/full_repos/permissive/135077285/instructionMemory.v
data/verilator_xmls/68c0862b-aa28-4c8c-8d95-e5f23d5566ec.xml
module instructionMemory (
  input wire reset,
  input wire [31:0] readAddress,
  output reg [31:0] instruction
);

  reg [31:0] memory [0:5];

  integer i;

  initial begin
    $readmemb("instructions.bin", memory);
    $display("rdata:");
    for (i = 0; i < 6; i = i + 1)
      $display("%d: %b", i, memory[i]);
  end

  always @(readAddress) begin
    instruction <= memory[readAddress / 4];
    $display("# %t, RA: %d, %b", $time, readAddress, instruction);
  end

endmodule
module instructionMemory (
  input wire reset,
  input wire [31:0] readAddress,
  output reg [31:0] instruction
);


  reg [31:0] memory [0:5];

  integer i;

  initial begin
    $readmemb("instructions.bin", memory);
    $display("rdata:");
    for (i = 0; i < 6; i = i + 1)
      $display("%d: %b", i, memory[i]);
  end

  always @(readAddress) begin
    instruction <= memory[readAddress / 4];
    $display("# %t, RA: %d, %b", $time, readAddress, instruction);
  end

endmodule