data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator/PPgen_wordslice.v
None: at end of input
1: b"%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator/PPgen_wordslice.v:53: Cannot find file containing module: 'PPgen_9bits'\nPPgen_9bits b2v_inst(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator,data/full_repos/permissive/13847835/PPgen_9bits\n             data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator,data/full_repos/permissive/13847835/PPgen_9bits.v\n             data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator,data/full_repos/permissive/13847835/PPgen_9bits.sv\n             PPgen_9bits\n             PPgen_9bits.v\n             PPgen_9bits.sv\n             obj_dir/PPgen_9bits\n             obj_dir/PPgen_9bits.v\n             obj_dir/PPgen_9bits.sv\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator/PPgen_wordslice.v:62: Cannot find file containing module: 'PPgen_9bits'\nPPgen_9bits b2v_inst3(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator/PPgen_wordslice.v:71: Cannot find file containing module: 'PPgen_9bits'\nPPgen_9bits b2v_inst4(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator/PPgen_wordslice.v:80: Cannot find file containing module: 'PPgen_9bits'\nPPgen_9bits b2v_inst5(\n^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module PPgen_wordslice(
	Double,
	Negate,
	Single,
	Y,
	Sign3,
	Sign2,
	Sign1,
	Sign0,
	PP0,
	PP1,
	PP2,
	PP3
);


input wire	[3:0] Double;
input wire	[3:0] Negate;
input wire	[3:0] Single;
input wire	[7:0] Y;
output wire	Sign3;
output wire	Sign2;
output wire	Sign1;
output wire	Sign0;
output wire	[8:0] PP0;
output wire	[8:0] PP1;
output wire	[8:0] PP2;
output wire	[8:0] PP3;






PPgen_9bits	b2v_inst(
	.Single(Single[3]),
	.Double(Double[3]),
	.Negate(Negate[3]),
	.Y(Y),
	.Sign(Sign3),
	.PP(PP3));


PPgen_9bits	b2v_inst3(
	.Single(Single[2]),
	.Double(Double[2]),
	.Negate(Negate[2]),
	.Y(Y),
	.Sign(Sign2),
	.PP(PP2));


PPgen_9bits	b2v_inst4(
	.Single(Single[1]),
	.Double(Double[1]),
	.Negate(Negate[1]),
	.Y(Y),
	.Sign(Sign1),
	.PP(PP1));


PPgen_9bits	b2v_inst5(
	.Single(Single[0]),
	.Double(Double[0]),
	.Negate(Negate[0]),
	.Y(Y),
	.Sign(Sign0),
	.PP(PP0));


endmodule
module PPgen_wordslice(
	Double,
	Negate,
	Single,
	Y,
	Sign3,
	Sign2,
	Sign1,
	Sign0,
	PP0,
	PP1,
	PP2,
	PP3
);



input wire	[3:0] Double;
input wire	[3:0] Negate;
input wire	[3:0] Single;
input wire	[7:0] Y;
output wire	Sign3;
output wire	Sign2;
output wire	Sign1;
output wire	Sign0;
output wire	[8:0] PP0;
output wire	[8:0] PP1;
output wire	[8:0] PP2;
output wire	[8:0] PP3;






PPgen_9bits	b2v_inst(
	.Single(Single[3]),
	.Double(Double[3]),
	.Negate(Negate[3]),
	.Y(Y),
	.Sign(Sign3),
	.PP(PP3));


PPgen_9bits	b2v_inst3(
	.Single(Single[2]),
	.Double(Double[2]),
	.Negate(Negate[2]),
	.Y(Y),
	.Sign(Sign2),
	.PP(PP2));


PPgen_9bits	b2v_inst4(
	.Single(Single[1]),
	.Double(Double[1]),
	.Negate(Negate[1]),
	.Y(Y),
	.Sign(Sign1),
	.PP(PP1));


PPgen_9bits	b2v_inst5(
	.Single(Single[0]),
	.Double(Double[0]),
	.Negate(Negate[0]),
	.Y(Y),
	.Sign(Sign0),
	.PP(PP0));


endmodule