data/full_repos/permissive/159823067/omercevik_hw4_32bitMips_SingleCycle_Datapath_verilog_files/mips_memory.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/97dfa1ac-2bfa-4797-835a-1240334df656.xml
module mips_memory
( write_data_address, write_data, read_mem, signal_mem_write, signal_mem_read, clk );

	output reg [31:0] read_mem;
	input [31:0] write_data_address, write_data;
	input signal_mem_write, signal_mem_read, clk;
	
	reg [31:0] memory [255:0];

	always @(posedge clk)
	begin
		if( signal_mem_read == 1'b1 )
		begin
			read_mem <= memory[write_data_address];
		end
		if( signal_mem_write == 1'b1 )
		begin
			memory[write_data_address] <= write_data;
		end
	end
	
endmodule
module mips_memory
( write_data_address, write_data, read_mem, signal_mem_write, signal_mem_read, clk );


	output reg [31:0] read_mem;
	input [31:0] write_data_address, write_data;
	input signal_mem_write, signal_mem_read, clk;
	
	reg [31:0] memory [255:0];

	always @(posedge clk)
	begin
		if( signal_mem_read == 1'b1 )
		begin
			read_mem <= memory[write_data_address];
		end
		if( signal_mem_write == 1'b1 )
		begin
			memory[write_data_address] <= write_data;
		end
	end
	
endmodule