data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_サンプル回路/FPGA/FPGA_stopwatch/key_module.v
data/verilator_xmls/e20b90b3-bc51-499f-b138-2e65b6b5080a.xml
module key_module(

		CLK, 
		RSTN,
		PSW_1D,


		PSW_SIG
);


input		CLK;
input		RSTN;
input		PSW_1D;


output	PSW_SIG;


reg		PSW_2D;
reg	[1:0]		PSW_DIFF;
reg	[18:0]	PSW_COUNT;
reg	PSW_SIG;




	always@( posedge CLK or negedge RSTN) begin
		if( !RSTN )begin
    		PSW_2D <= 1'b0;
		end

		else begin
    		PSW_2D <= PSW_1D;
		end
	end




	always@( posedge CLK or negedge RSTN) begin
		if( !RSTN )begin
	    	PSW_DIFF <= 2'd0;
		end

		else if(PSW_1D == 1 && PSW_2D == 1)begin
	    	PSW_DIFF <= 2'd0;
		end
	  	else if(PSW_1D == 0 && PSW_2D == 1)begin
	    	PSW_DIFF <= 2'd1;
		end
	  	else if(PSW_1D == 0 && PSW_2D == 0)begin
	    	PSW_DIFF <= 2'd2;
		end
	  	else begin
	    	PSW_DIFF <= 2'd3;
		end
	end




	always@( posedge CLK or negedge RSTN) begin
		if( !RSTN )begin
	    	PSW_COUNT <= 19'd0;
		end

	  	else if( PSW_DIFF == 2'd0)begin
	    	PSW_COUNT <= 19'd0;
		end
	  	else if( PSW_DIFF == 2'd1)begin
	    	PSW_COUNT <= 19'd1;
		end
	  	else if( PSW_DIFF == 2'd2)begin
	    	if( 19'd1 <= PSW_COUNT && PSW_COUNT < 19'd500000 )begin
	      		PSW_COUNT <= PSW_COUNT + 19'd1;
			end
	    	else begin
	      		PSW_COUNT <= 19'd0;
			end
		end
		else begin
			PSW_COUNT <= 19'd0;
		end
	end




	always@( posedge CLK or negedge RSTN) begin
	  	if( RSTN == 1'b0 )begin
	    	PSW_SIG <= 1'b0;
		end
	  	else if( PSW_COUNT >= 19'd500000 )begin
	    	PSW_SIG = 1'b1;
		end
	  	else begin
	    	PSW_SIG = 1'b0;
		end
	end

endmodule
module key_module(

		CLK, 
		RSTN,
		PSW_1D,


		PSW_SIG
);



input		CLK;
input		RSTN;
input		PSW_1D;


output	PSW_SIG;


reg		PSW_2D;
reg	[1:0]		PSW_DIFF;
reg	[18:0]	PSW_COUNT;
reg	PSW_SIG;




	always@( posedge CLK or negedge RSTN) begin
		if( !RSTN )begin
    		PSW_2D <= 1'b0;
		end

		else begin
    		PSW_2D <= PSW_1D;
		end
	end




	always@( posedge CLK or negedge RSTN) begin
		if( !RSTN )begin
	    	PSW_DIFF <= 2'd0;
		end

		else if(PSW_1D == 1 && PSW_2D == 1)begin
	    	PSW_DIFF <= 2'd0;
		end
	  	else if(PSW_1D == 0 && PSW_2D == 1)begin
	    	PSW_DIFF <= 2'd1;
		end
	  	else if(PSW_1D == 0 && PSW_2D == 0)begin
	    	PSW_DIFF <= 2'd2;
		end
	  	else begin
	    	PSW_DIFF <= 2'd3;
		end
	end




	always@( posedge CLK or negedge RSTN) begin
		if( !RSTN )begin
	    	PSW_COUNT <= 19'd0;
		end

	  	else if( PSW_DIFF == 2'd0)begin
	    	PSW_COUNT <= 19'd0;
		end
	  	else if( PSW_DIFF == 2'd1)begin
	    	PSW_COUNT <= 19'd1;
		end
	  	else if( PSW_DIFF == 2'd2)begin
	    	if( 19'd1 <= PSW_COUNT && PSW_COUNT < 19'd500000 )begin
	      		PSW_COUNT <= PSW_COUNT + 19'd1;
			end
	    	else begin
	      		PSW_COUNT <= 19'd0;
			end
		end
		else begin
			PSW_COUNT <= 19'd0;
		end
	end




	always@( posedge CLK or negedge RSTN) begin
	  	if( RSTN == 1'b0 )begin
	    	PSW_SIG <= 1'b0;
		end
	  	else if( PSW_COUNT >= 19'd500000 )begin
	    	PSW_SIG = 1'b1;
		end
	  	else begin
	    	PSW_SIG = 1'b0;
		end
	end

endmodule