data/full_repos/permissive/109936328/tb/tb_timer.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:14: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] req_addr;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:15: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] req_wr_data;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:17: Define or directive not defined: \'`MEM_COUNT_W\'\n  reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:17: Define or directive not defined: \'`MEM_COUNT_NONE\'\n  reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:17: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;\n                                                      ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:19: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] res_rd_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:20: Define or directive not defined: \'`MEM_CODE_W\'\n  wire [`MEM_CODE_W - 1:0] res_code;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:26: Define or directive not defined: \'`ADDR_W\'\n    input [`ADDR_W - 1:0] addr;\n           ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:27: Define or directive not defined: \'`WORD_W\'\n    input [`WORD_W - 1:0] data;\n           ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:28: Define or directive not defined: \'`WORD_W\'\n    input [`WORD_W - 1:0] wr_mask;\n           ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:29: Define or directive not defined: \'`MEM_COUNT_W\'\n    input [`MEM_COUNT_W - 1:0] count;\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:31: Define or directive not defined: \'`WORD_W\'\n    reg [`WORD_W - 1:0] temp;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:34: Define or directive not defined: \'`WORD_W\'\n    if(wr_mask == {`WORD_W{1\'b1}}) begin\n                   ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_timer.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_PERIOD;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_timer.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #CLK_PERIOD;\n    ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:57: Define or directive not defined: \'`MEM_COUNT_NONE\'\n    req_count = `MEM_COUNT_NONE;\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:57: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    req_count = `MEM_COUNT_NONE;\n                               ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:63: Define or directive not defined: \'`ADDR_W\'\n    input [`ADDR_W - 1:0] addr;\n           ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:64: Define or directive not defined: \'`WORD_W\'\n    input [`WORD_W - 1:0] wr_mask;\n           ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:65: Define or directive not defined: \'`MEM_COUNT_W\'\n    input [`MEM_COUNT_W - 1:0] count;\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:67: Define or directive not defined: \'`WORD_W\'\n    reg [`WORD_W - 1:0] temp;\n         ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_timer.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #CLK_PERIOD;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_timer.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #CLK_PERIOD;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_timer.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #CLK_PERIOD;\n    ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:90: Define or directive not defined: \'`MEM_COUNT_NONE\'\n    req_count = `MEM_COUNT_NONE;\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:90: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    req_count = `MEM_COUNT_NONE;\n                               ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:97: Define or directive not defined: \'`ADDR_W\'\n      ((0) + (`ADDR_W\'h0)),\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:98: Define or directive not defined: \'`WORD_W\'\n      `WORD_W\'h8,\n      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:99: Define or directive not defined: \'`WORD_W\'\n      `WORD_W\'h8,\n      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:100: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n      `MEM_COUNT_BYTE\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:108: Define or directive not defined: \'`ADDR_W\'\n      ((0) + (`ADDR_W\'h0)),\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:109: Define or directive not defined: \'`WORD_W\'\n      `WORD_W\'h0,\n      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:110: Define or directive not defined: \'`WORD_W\'\n      `WORD_W\'h8,\n      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:111: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n      `MEM_COUNT_BYTE\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:117: Define or directive not defined: \'`WORD_W\'\n    output reg [`WORD_W - 1:0] count;\n                ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:119: Define or directive not defined: \'`ADDR_W\'\n    req_addr = ((0) + (`ADDR_W\'h16));\n                       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:120: Define or directive not defined: \'`MEM_COUNT_WORD\'\n    req_count = `MEM_COUNT_WORD;\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:120: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    req_count = `MEM_COUNT_WORD;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_timer.v:123: Unsupported: Ignoring delay on this delayed statement.\n    #CLK_PERIOD;\n    ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:126: Define or directive not defined: \'`MEM_COUNT_NONE\'\n    req_count = `MEM_COUNT_NONE;\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:126: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    req_count = `MEM_COUNT_NONE;\n                               ^\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:135: Define or directive not defined: \'`ADDR_W\'\n      ((0) + (`ADDR_W\'h0)),\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:137: Define or directive not defined: \'`WORD_W\'\n      `WORD_W\'h4,\n      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:138: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n      `MEM_COUNT_BYTE\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:144: Define or directive not defined: \'`WORD_W\'\n    input [`WORD_W - 1:0] load_val;\n           ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:145: Define or directive not defined: \'`WORD_W\'\n    reg [`WORD_W - 1:0] temp;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:148: Define or directive not defined: \'`ADDR_W\'\n      `ADDR_W\'h8,\n      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:150: Define or directive not defined: \'`WORD_W\'\n      {`WORD_W{1\'b1}},\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:151: Define or directive not defined: \'`MEM_COUNT_WORD\'\n      `MEM_COUNT_WORD\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:155: Define or directive not defined: \'`ADDR_W\'\n      `ADDR_W\'h0,\n      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:156: Define or directive not defined: \'`WORD_W\'\n      `WORD_W\'h2,\n      ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:157: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n      `MEM_COUNT_BYTE\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:163: Define or directive not defined: \'`WORD_W\'\n    input [`WORD_W - 1:0] threshold;\n           ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_timer.v:166: Define or directive not defined: \'`ADDR_W\'\n      ((0) + (`ADDR_W\'h4)),\n              ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module tb_timer;
  localparam CLK_HPERIOD = 5;
  localparam CLK_PERIOD = 2 * CLK_HPERIOD;

  reg clk = 0;
  reg aresetn = 0;

  reg [`ADDR_W - 1:0] req_addr;
  reg [`WORD_W - 1:0] req_wr_data;
  reg req_wr_en = 0;
  reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;

  wire [`WORD_W - 1:0] res_rd_data;
  wire [`MEM_CODE_W - 1:0] res_code;

  wire threshold_trigger;
  assign threshold_trigger = dut.timer.threshold_trigger;

  task write_register;
    input [`ADDR_W - 1:0] addr;
    input [`WORD_W - 1:0] data;
    input [`WORD_W - 1:0] wr_mask;
    input [`MEM_COUNT_W - 1:0] count;

    reg [`WORD_W - 1:0] temp;
  begin

    if(wr_mask == {`WORD_W{1'b1}}) begin
      req_addr = addr;
      req_wr_data = data;
      req_wr_en = 1;
      req_count = count;
    end else begin
      req_addr = addr;
      req_wr_en = 0;
      req_count = count;

      #CLK_PERIOD;

      temp = res_rd_data;
      temp = temp | (data & wr_mask);
      temp = temp & ~(~data & wr_mask);
      
      req_wr_en = 1;
      req_wr_data = temp;
    end

    #CLK_PERIOD;
    
    req_wr_en = 0;
    req_count = `MEM_COUNT_NONE;
  end
  endtask


  task toggle_bits;
    input [`ADDR_W - 1:0] addr;
    input [`WORD_W - 1:0] wr_mask;
    input [`MEM_COUNT_W - 1:0] count;

    reg [`WORD_W - 1:0] temp;
  begin
    req_addr = addr;
    req_wr_en = 0;
    req_count = count;

    #CLK_PERIOD;

    temp = res_rd_data;
    temp = temp ^ wr_mask;

    req_wr_en = 1;
    req_wr_data = temp;

    #CLK_PERIOD;

    temp = temp ^ wr_mask;

    req_wr_data = temp;

    #CLK_PERIOD;

    req_wr_en = 0;
    req_count = `MEM_COUNT_NONE;
  end
  endtask

  task start_timer;
  begin
    write_register(
      `TMR_ADDR(`ADDR_W'h0),
      `WORD_W'h8,
      `WORD_W'h8,
      `MEM_COUNT_BYTE
    );
  end
  endtask

  task stop_timer;
  begin
    write_register(
      `TMR_ADDR(`ADDR_W'h0),
      `WORD_W'h0,
      `WORD_W'h8,
      `MEM_COUNT_BYTE
    );
  end
  endtask

  task read_timer_count;
    output reg [`WORD_W - 1:0] count;
  begin
    req_addr = `TMR_ADDR(`ADDR_W'h16);
    req_count = `MEM_COUNT_WORD;
    req_wr_en = 0;

    #CLK_PERIOD;

    count = res_rd_data;
    req_count = `MEM_COUNT_NONE;
    req_wr_en = 0;
  end
  endtask

  task set_dir;
    input backwards;
  begin
    write_register(
      `TMR_ADDR(`ADDR_W'h0),
      backwards << 2,
      `WORD_W'h4,
      `MEM_COUNT_BYTE
    );
  end
  endtask

  task load_value;
    input [`WORD_W - 1:0] load_val;
    reg [`WORD_W - 1:0] temp;
  begin
    write_register(
      `ADDR_W'h8,
      load_val,
      {`WORD_W{1'b1}},
      `MEM_COUNT_WORD
    );

    toggle_bits(
      `ADDR_W'h0,
      `WORD_W'h2,
      `MEM_COUNT_BYTE
    );
  end
  endtask

  task set_threshold;
    input [`WORD_W - 1:0] threshold;
  begin
    write_register(
      `TMR_ADDR(`ADDR_W'h4),
      threshold,
      `WORD_W'hffffffff,
      `MEM_COUNT_WORD
    );
  end
  endtask

  task set_trigger_en;
    input en;
  begin
    write_register(
      `TMR_ADDR(`ADDR_W'h0),
      en,
      `WORD_W'h1,
      `MEM_COUNT_BYTE
    );
  end
  endtask

  reg [`WORD_W - 1:0] timer_count;
  integer i;
  initial begin
    $dumpfile("tb_timer.vcd");
    $dumpvars();
    for(i = 0; i < 1; i = i + 1) begin
      $dumpvars(0, dut.timer.rw_reg.readwrite_registers.r_mem[i]);
    end
    #CLK_PERIOD;
    aresetn = 1;

    load_value(
      `WORD_W'h10000000
    );

    start_timer();

    repeat(10) begin
      #CLK_PERIOD;
    end

    stop_timer();

    repeat(3) begin
      #CLK_PERIOD;
    end 

    set_dir(1);

    set_threshold(`WORD_W'h10000000);
    set_trigger_en(1'b1);

    start_timer();

    wait(threshold_trigger == 1);
    #CLK_PERIOD;

    set_dir(0);

    repeat(5) begin
      #CLK_PERIOD;
    end

    $finish();
  end

  always begin: clk_gen
    #CLK_HPERIOD;
    clk = ~clk;
  end

  timer#(
    .ADDR_START(`ADDR_START)
  ) dut(
    .clk(clk),
    .aresetn(aresetn),
    
    .i_req_addr(req_addr),
    .i_req_wr_data(req_wr_data),
    .i_req_wr_en(req_wr_en),
    .i_req_count(req_count),

    .o_res_rd_data(res_rd_data),
    .o_res_code(res_code)
  );
endmodule
module tb_timer;

  localparam CLK_HPERIOD = 5;
  localparam CLK_PERIOD = 2 * CLK_HPERIOD;

  reg clk = 0;
  reg aresetn = 0;

  reg [`ADDR_W - 1:0] req_addr;
  reg [`WORD_W - 1:0] req_wr_data;
  reg req_wr_en = 0;
  reg [`MEM_COUNT_W - 1:0] req_count = `MEM_COUNT_NONE;

  wire [`WORD_W - 1:0] res_rd_data;
  wire [`MEM_CODE_W - 1:0] res_code;

  wire threshold_trigger;
  assign threshold_trigger = dut.timer.threshold_trigger;

  task write_register;
    input [`ADDR_W - 1:0] addr;
    input [`WORD_W - 1:0] data;
    input [`WORD_W - 1:0] wr_mask;
    input [`MEM_COUNT_W - 1:0] count;

    reg [`WORD_W - 1:0] temp;
  begin

    if(wr_mask == {`WORD_W{1'b1}}) begin
      req_addr = addr;
      req_wr_data = data;
      req_wr_en = 1;
      req_count = count;
    end else begin
      req_addr = addr;
      req_wr_en = 0;
      req_count = count;

      #CLK_PERIOD;

      temp = res_rd_data;
      temp = temp | (data & wr_mask);
      temp = temp & ~(~data & wr_mask);
      
      req_wr_en = 1;
      req_wr_data = temp;
    end

    #CLK_PERIOD;
    
    req_wr_en = 0;
    req_count = `MEM_COUNT_NONE;
  end
  endtask


  task toggle_bits;
    input [`ADDR_W - 1:0] addr;
    input [`WORD_W - 1:0] wr_mask;
    input [`MEM_COUNT_W - 1:0] count;

    reg [`WORD_W - 1:0] temp;
  begin
    req_addr = addr;
    req_wr_en = 0;
    req_count = count;

    #CLK_PERIOD;

    temp = res_rd_data;
    temp = temp ^ wr_mask;

    req_wr_en = 1;
    req_wr_data = temp;

    #CLK_PERIOD;

    temp = temp ^ wr_mask;

    req_wr_data = temp;

    #CLK_PERIOD;

    req_wr_en = 0;
    req_count = `MEM_COUNT_NONE;
  end
  endtask

  task start_timer;
  begin
    write_register(
      `TMR_ADDR(`ADDR_W'h0),
      `WORD_W'h8,
      `WORD_W'h8,
      `MEM_COUNT_BYTE
    );
  end
  endtask

  task stop_timer;
  begin
    write_register(
      `TMR_ADDR(`ADDR_W'h0),
      `WORD_W'h0,
      `WORD_W'h8,
      `MEM_COUNT_BYTE
    );
  end
  endtask

  task read_timer_count;
    output reg [`WORD_W - 1:0] count;
  begin
    req_addr = `TMR_ADDR(`ADDR_W'h16);
    req_count = `MEM_COUNT_WORD;
    req_wr_en = 0;

    #CLK_PERIOD;

    count = res_rd_data;
    req_count = `MEM_COUNT_NONE;
    req_wr_en = 0;
  end
  endtask

  task set_dir;
    input backwards;
  begin
    write_register(
      `TMR_ADDR(`ADDR_W'h0),
      backwards << 2,
      `WORD_W'h4,
      `MEM_COUNT_BYTE
    );
  end
  endtask

  task load_value;
    input [`WORD_W - 1:0] load_val;
    reg [`WORD_W - 1:0] temp;
  begin
    write_register(
      `ADDR_W'h8,
      load_val,
      {`WORD_W{1'b1}},
      `MEM_COUNT_WORD
    );

    toggle_bits(
      `ADDR_W'h0,
      `WORD_W'h2,
      `MEM_COUNT_BYTE
    );
  end
  endtask

  task set_threshold;
    input [`WORD_W - 1:0] threshold;
  begin
    write_register(
      `TMR_ADDR(`ADDR_W'h4),
      threshold,
      `WORD_W'hffffffff,
      `MEM_COUNT_WORD
    );
  end
  endtask

  task set_trigger_en;
    input en;
  begin
    write_register(
      `TMR_ADDR(`ADDR_W'h0),
      en,
      `WORD_W'h1,
      `MEM_COUNT_BYTE
    );
  end
  endtask

  reg [`WORD_W - 1:0] timer_count;
  integer i;
  initial begin
    $dumpfile("tb_timer.vcd");
    $dumpvars();
    for(i = 0; i < 1; i = i + 1) begin
      $dumpvars(0, dut.timer.rw_reg.readwrite_registers.r_mem[i]);
    end
    #CLK_PERIOD;
    aresetn = 1;

    load_value(
      `WORD_W'h10000000
    );

    start_timer();

    repeat(10) begin
      #CLK_PERIOD;
    end

    stop_timer();

    repeat(3) begin
      #CLK_PERIOD;
    end 

    set_dir(1);

    set_threshold(`WORD_W'h10000000);
    set_trigger_en(1'b1);

    start_timer();

    wait(threshold_trigger == 1);
    #CLK_PERIOD;

    set_dir(0);

    repeat(5) begin
      #CLK_PERIOD;
    end

    $finish();
  end

  always begin: clk_gen
    #CLK_HPERIOD;
    clk = ~clk;
  end

  timer#(
    .ADDR_START(`ADDR_START)
  ) dut(
    .clk(clk),
    .aresetn(aresetn),
    
    .i_req_addr(req_addr),
    .i_req_wr_data(req_wr_data),
    .i_req_wr_en(req_wr_en),
    .i_req_count(req_count),

    .o_res_rd_data(res_rd_data),
    .o_res_code(res_code)
  );
endmodule