data/full_repos/permissive/206169433/single cycle/single_cycle.v
1: b'%Error: Cannot find file containing module: cycle,data/full_repos/permissive/206169433\n        ... Looked in:\n             data/full_repos/permissive/206169433/single/cycle,data/full_repos/permissive/206169433\n             data/full_repos/permissive/206169433/single/cycle,data/full_repos/permissive/206169433.v\n             data/full_repos/permissive/206169433/single/cycle,data/full_repos/permissive/206169433.sv\n             cycle,data/full_repos/permissive/206169433\n             cycle,data/full_repos/permissive/206169433.v\n             cycle,data/full_repos/permissive/206169433.sv\n             obj_dir/cycle,data/full_repos/permissive/206169433\n             obj_dir/cycle,data/full_repos/permissive/206169433.v\n             obj_dir/cycle,data/full_repos/permissive/206169433.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/206169433/single\n%Error: Cannot find file containing module: cycle/single_cycle.v\n%Error: Exiting due to 3 error(s)\n'
module single_cycle(clk);
    input clk;

    wire [31:0] pc_in, pc_out,
                pc_add_4,
                instruction,
                jump_address,
                add_output,
                branch_address;



    wire [4:0] regwrite_address;
    wire [31:0] regwrite_data,
                regread_data1,
                regread_data2;



    wire [31:0] sign_extension;

    wire [31:0] alu_in,
                alu_out;
    
    wire [3:0] alu_control;

    wire alu_zero;



    wire [31:0] mem_read;



    wire branch,
         regdst,
         jump,
         branch_beq,
         branch_bne,
         memtoreg,
         memread,
         memwrite,
         alusrc,
         regwrite;

    wire [1:0] aluop;





  assign pc_add_4 = pc_out + 4;
    assign pc_in = jump == 0 ? branch_address : jump_address; 

    assign add_output = pc_add_4 + (sign_extension<< 2);
    assign jump_address = {pc_add_4[31:28], instruction[25:0], 2'b0};
    assign branch_address = branch == 1 ? add_output : pc_add_4;

    assign regwrite_address = regdst == 0 ? instruction[20:16] : instruction[15:11];

    assign regwrite_data = memtoreg == 0 ? alu_out : mem_read;


    assign alu_in = alusrc == 0 ? regread_data2 : sign_extension;


    assign branch = ((branch_beq && alu_zero) | (branch_bne && ~alu_zero) );

    

    
    pc PC(clk, pc_in, pc_out);


    im InstructionMemory(pc_out, instruction);


    sign_extension SignExtension(instruction[15:0], sign_extension);


    register Register(clk, instruction[25:21], instruction[20:16],
                            regread_data1, regread_data2,
                            regwrite_address, regwrite_data,
                            regwrite);



    alu alu(regread_data1, alu_in, alu_control, alu_out, alu_zero);


    mem mem(clk, alu_out, regread_data2, mem_read, memread, memwrite);





    control Control(instruction[31:26], 
                    regdst, jump, branch_beq,
                    branch_bne, memread, memtoreg,
                    memwrite, regwrite, alusrc, aluop);



    alu_control ALU_Control(instruction[5:0], aluop, alu_control);




endmodule
module single_cycle(clk);

    input clk;

    wire [31:0] pc_in, pc_out,
                pc_add_4,
                instruction,
                jump_address,
                add_output,
                branch_address;



    wire [4:0] regwrite_address;
    wire [31:0] regwrite_data,
                regread_data1,
                regread_data2;



    wire [31:0] sign_extension;

    wire [31:0] alu_in,
                alu_out;
    
    wire [3:0] alu_control;

    wire alu_zero;



    wire [31:0] mem_read;



    wire branch,
         regdst,
         jump,
         branch_beq,
         branch_bne,
         memtoreg,
         memread,
         memwrite,
         alusrc,
         regwrite;

    wire [1:0] aluop;





  assign pc_add_4 = pc_out + 4;
    assign pc_in = jump == 0 ? branch_address : jump_address; 

    assign add_output = pc_add_4 + (sign_extension<< 2);
    assign jump_address = {pc_add_4[31:28], instruction[25:0], 2'b0};
    assign branch_address = branch == 1 ? add_output : pc_add_4;

    assign regwrite_address = regdst == 0 ? instruction[20:16] : instruction[15:11];

    assign regwrite_data = memtoreg == 0 ? alu_out : mem_read;


    assign alu_in = alusrc == 0 ? regread_data2 : sign_extension;


    assign branch = ((branch_beq && alu_zero) | (branch_bne && ~alu_zero) );

    

    
    pc PC(clk, pc_in, pc_out);


    im InstructionMemory(pc_out, instruction);


    sign_extension SignExtension(instruction[15:0], sign_extension);


    register Register(clk, instruction[25:21], instruction[20:16],
                            regread_data1, regread_data2,
                            regwrite_address, regwrite_data,
                            regwrite);



    alu alu(regread_data1, alu_in, alu_control, alu_out, alu_zero);


    mem mem(clk, alu_out, regread_data2, mem_read, memread, memwrite);





    control Control(instruction[31:26], 
                    regdst, jump, branch_beq,
                    branch_bne, memread, memtoreg,
                    memwrite, regwrite, alusrc, aluop);



    alu_control ALU_Control(instruction[5:0], aluop, alu_control);




endmodule