data/full_repos/permissive/118895292/peripheral/uart/baud_generator.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/uart/baud_generator.v:23: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'oversample_ctr\' generates 3 bits.\n                                                                                        : ... In instance baud_generator\n  if (oversample_ctr == (OVERSAMPLE_AMOUNT - 1))\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/uart/baud_generator.v:19: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'baud_ctr\' generates 16 bits.\n                                                                                        : ... In instance baud_generator\n if (baud_ctr == (SYS_CLOCK_HZ / (BAUD_RATE * OVERSAMPLE_AMOUNT)))\n              ^~\n%Error: Exiting due to 2 warning(s)\n'
module baud_generator(
	clk,
	out_clk,
	out_oversample_clk);

parameter BAUD_RATE = 115200;
parameter SYS_CLOCK_HZ = 50000000;
parameter OVERSAMPLE_AMOUNT = 8;

input clk;
output reg out_clk;
output reg out_oversample_clk;

reg [15:0] baud_ctr = 0;
reg [2:0] oversample_ctr = 0;

always @(posedge clk)
begin
	if (baud_ctr == (SYS_CLOCK_HZ / (BAUD_RATE * OVERSAMPLE_AMOUNT)))
	begin
		out_oversample_clk <= 1;
		baud_ctr <= 0;
		if (oversample_ctr == (OVERSAMPLE_AMOUNT - 1))
		begin
			out_clk <= 1;
			oversample_ctr <= 0;
		end
		else
		begin
			oversample_ctr <= oversample_ctr + 1;
		end
	end
	else
	begin
		baud_ctr <= baud_ctr + 1;
		out_clk <= 0;
		out_oversample_clk <= 0;
	end
end

endmodule
module baud_generator(
	clk,
	out_clk,
	out_oversample_clk);


parameter BAUD_RATE = 115200;
parameter SYS_CLOCK_HZ = 50000000;
parameter OVERSAMPLE_AMOUNT = 8;

input clk;
output reg out_clk;
output reg out_oversample_clk;

reg [15:0] baud_ctr = 0;
reg [2:0] oversample_ctr = 0;

always @(posedge clk)
begin
	if (baud_ctr == (SYS_CLOCK_HZ / (BAUD_RATE * OVERSAMPLE_AMOUNT)))
	begin
		out_oversample_clk <= 1;
		baud_ctr <= 0;
		if (oversample_ctr == (OVERSAMPLE_AMOUNT - 1))
		begin
			out_clk <= 1;
			oversample_ctr <= 0;
		end
		else
		begin
			oversample_ctr <= oversample_ctr + 1;
		end
	end
	else
	begin
		baud_ctr <= baud_ctr + 1;
		out_clk <= 0;
		out_oversample_clk <= 0;
	end
end

endmodule