data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_5.v
data/verilator_xmls/82cccdd7-3e25-4fce-b045-17aeb5190ba1.xml
module carrysave_4is2 (
input [4:0] in,
output c0,
output c1,
output sum
);
wire connection;
FullAdder FA0 (in[0],in[1],in[2],connection,c0);
FullAdder FA1 (connection,in[4],in[3],sum,c1);
endmodule
module carrysave_4is2 (
input [4:0] in,
output c0,
output c1,
output sum
);

wire connection;
FullAdder FA0 (in[0],in[1],in[2],connection,c0);
FullAdder FA1 (connection,in[4],in[3],sum,c1);
endmodule