data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sources_1/new/edge_trigger.v
data/verilator_xmls/de8d163a-0727-4c97-ad2b-049921aaebc0.xml
module edge_trigger
    (
    input wire clk,reset,
    input wire level,
    output wire tick
    );
    
    reg delay_reg;
    
    always@(posedge clk,posedge reset) begin
        if(reset) begin
            delay_reg <= 1'b0;
        end else begin
            delay_reg <= level;
        end
    end
    
    assign tick = ~delay_reg & level;
endmodule
module edge_trigger
    (
    input wire clk,reset,
    input wire level,
    output wire tick
    );

    
    reg delay_reg;
    
    always@(posedge clk,posedge reset) begin
        if(reset) begin
            delay_reg <= 1'b0;
        end else begin
            delay_reg <= level;
        end
    end
    
    assign tick = ~delay_reg & level;
endmodule