data/full_repos/permissive/167489907/Examples/D-Flip-Flop/dff_async_reset.v
data/verilator_xmls/0b048f96-bd8a-472c-a761-fab44bfe93d6.xml
module dff_async_reset(q, data, clk, reset, enable);
input data, clk, reset, enable;
output reg q;

always @(posedge clk or negedge reset)
if (~reset) begin
	q <= 1'b0;
	end
else if (enable) begin
	q <= data;
	end
endmodule
module dff_async_reset(q, data, clk, reset, enable);

input data, clk, reset, enable;
output reg q;

always @(posedge clk or negedge reset)
if (~reset) begin
	q <= 1'b0;
	end
else if (enable) begin
	q <= data;
	end
endmodule