data/full_repos/permissive/114652687/dut1/tap_top.v
1: b'%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:70: Cannot find include file: tap_defines.v\n`include "tap_defines.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114652687/dut1,data/full_repos/permissive/114652687/tap_defines.v\n             data/full_repos/permissive/114652687/dut1,data/full_repos/permissive/114652687/tap_defines.v.v\n             data/full_repos/permissive/114652687/dut1,data/full_repos/permissive/114652687/tap_defines.v.sv\n             tap_defines.v\n             tap_defines.v.v\n             tap_defines.v.sv\n             obj_dir/tap_defines.v\n             obj_dir/tap_defines.v.v\n             obj_dir/tap_defines.v.sv\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:358: Define or directive not defined: \'`IR_LENGTH\'\nreg [`IR_LENGTH-1:0]  jtag_ir;           \n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:359: Define or directive not defined: \'`IR_LENGTH\'\nreg [`IR_LENGTH-1:0]  latched_jtag_ir;  \n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:365: Define or directive not defined: \'`IR_LENGTH\'\n    jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH\'b0;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:365: Define or directive not defined: \'`IR_LENGTH\'\n    jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH\'b0;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:367: Define or directive not defined: \'`IR_LENGTH\'\n    jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH\'b0;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:367: Define or directive not defined: \'`IR_LENGTH\'\n    jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH\'b0;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:371: Define or directive not defined: \'`IR_LENGTH\'\n    jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:371: Define or directive not defined: \'`IR_LENGTH\'\n    jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:381: Define or directive not defined: \'`IDCODE\'\n    latched_jtag_ir <= `IDCODE;    \n                       ^~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:381: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    latched_jtag_ir <= `IDCODE;    \n                              ^\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:383: Define or directive not defined: \'`IDCODE\'\n    latched_jtag_ir <= `IDCODE;    \n                       ^~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:383: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    latched_jtag_ir <= `IDCODE;    \n                              ^\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:407: Define or directive not defined: \'`IDCODE_VALUE\'\n    idcode_reg <= `IDCODE_VALUE;    \n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:407: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    idcode_reg <= `IDCODE_VALUE;    \n                               ^\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:409: Define or directive not defined: \'`IDCODE_VALUE\'\n    idcode_reg <= `IDCODE_VALUE;    \n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:409: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    idcode_reg <= `IDCODE_VALUE;    \n                               ^\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:411: Define or directive not defined: \'`IDCODE_VALUE\'\n    idcode_reg <=  `IDCODE_VALUE;\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:411: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    idcode_reg <=  `IDCODE_VALUE;\n                                ^\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:469: Define or directive not defined: \'`IDCODE\'\n    `IDCODE:            idcode_select           = 1\'b1;     \n    ^~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:469: syntax error, unexpected \':\', expecting endcase\n    `IDCODE:            idcode_select           = 1\'b1;     \n           ^\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:470: Define or directive not defined: \'`DEBUG\'\n    `DEBUG:             debug_select            = 1\'b1;     \n    ^~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:471: Define or directive not defined: \'`IP1\'\n    `IP1:               ip1_select              = 1\'b1;\n    ^~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:472: Define or directive not defined: \'`IP2\'\n    `IP2:               ip2_select              = 1\'b1;\n    ^~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:493: Define or directive not defined: \'`IDCODE\'\n        `IDCODE:            tdo_mux_out = idcode_tdo;        \n        ^~~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:494: Define or directive not defined: \'`DEBUG\'\n        `DEBUG:             tdo_mux_out = debug_tdo_i;       \n        ^~~~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:495: Define or directive not defined: \'`IP1\'\n        `IP1:               tdo_mux_out = ip1_tdo_i;\n        ^~~~\n%Error: data/full_repos/permissive/114652687/dut1/tap_top.v:496: Define or directive not defined: \'`IP2\'\n        `IP2:               tdo_mux_out = ip2_tdo_i;\n        ^~~~\n%Error: Exiting due to 28 error(s)\n'
module tap_top(

                tms_pad_i, 
                tck_pad_i, 
                trstn_pad_i, 
                tdi_pad_i, 
                tdo_pad_o, 
                tdo_padoe_o,
 

                test_logic_reset_o,
                run_test_idle_o,
                shift_dr_o,
                pause_dr_o, 
                update_dr_o,
                capture_dr_o,
 

                debug_select_o,
                ip1_select_o,
                ip2_select_o,
 

                tdi_o, 
 

                debug_tdo_i,
                ip1_tdo_i,
                ip2_tdo_i
              );
 
 

input   tms_pad_i;
input   tck_pad_i;
input   trstn_pad_i;
input   tdi_pad_i;
output  tdo_pad_o;
output  tdo_padoe_o;
 

output  test_logic_reset_o;
output  run_test_idle_o;
output  shift_dr_o;
output  pause_dr_o;
output  update_dr_o;
output  capture_dr_o;
 

output  debug_select_o;
output  ip1_select_o;
output  ip2_select_o;
 

output  tdi_o;
 

input   debug_tdo_i;
input   ip1_tdo_i;
input   ip2_tdo_i;
 

reg     test_logic_reset;
reg     run_test_idle;
reg     select_dr_scan;
reg     capture_dr;
reg     shift_dr;
reg     exit1_dr;
reg     pause_dr;
reg     exit2_dr;
reg     update_dr;
reg     select_ir_scan;
reg     capture_ir;
reg     shift_ir;
reg     exit1_ir;
reg     pause_ir;
reg     exit2_ir;
reg     update_ir;
 

reg     idcode_select;
reg     debug_select;
reg     bypass_select;
reg     ip1_select;
reg     ip2_select;
 

reg     tdo_pad_o;
reg     tdo_padoe_o;
 
assign tdi_o = tdi_pad_i;
 
assign test_logic_reset_o = test_logic_reset;
assign run_test_idle_o = run_test_idle;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
assign capture_dr_o = capture_dr;
 
assign debug_select_o = debug_select;
assign ip1_select_o = ip1_select;
assign ip2_select_o = ip2_select;
 
 



`define STATE_test_logic_reset 4'hF
`define STATE_run_test_idle    4'hC
`define STATE_select_dr_scan   4'h7
`define STATE_capture_dr       4'h6
`define STATE_shift_dr         4'h2
`define STATE_exit1_dr         4'h1
`define STATE_pause_dr         4'h3
`define STATE_exit2_dr         4'h0
`define STATE_update_dr        4'h5
`define STATE_select_ir_scan   4'h4
`define STATE_capture_ir       4'hE
`define STATE_shift_ir         4'hA
`define STATE_exit1_ir         4'h9
`define STATE_pause_ir         4'hB
`define STATE_exit2_ir         4'h8
`define STATE_update_ir        4'hD
 
reg [3:0] TAP_state = `STATE_test_logic_reset;
reg [3:0] next_TAP_state;
 

always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
	if(trstn_pad_i == 0)
		TAP_state = `STATE_test_logic_reset;
	else
		TAP_state = next_TAP_state;
end
 
 

always @ (TAP_state or tms_pad_i)
begin
	case(TAP_state)
		`STATE_test_logic_reset:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset; 
			else next_TAP_state = `STATE_run_test_idle;
			end
		`STATE_run_test_idle:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan; 
			else next_TAP_state = `STATE_run_test_idle;
			end
		`STATE_select_dr_scan:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan; 
			else next_TAP_state = `STATE_capture_dr;
			end
		`STATE_capture_dr:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_exit1_dr; 
			else next_TAP_state = `STATE_shift_dr;
			end
		`STATE_shift_dr:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_exit1_dr; 
			else next_TAP_state = `STATE_shift_dr;
			end
		`STATE_exit1_dr:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_update_dr; 
			else next_TAP_state = `STATE_pause_dr;
			end
		`STATE_pause_dr:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_exit2_dr; 
			else next_TAP_state = `STATE_pause_dr;
			end
		`STATE_exit2_dr:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_update_dr; 
			else next_TAP_state = `STATE_shift_dr;
			end
		`STATE_update_dr:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan; 
			else next_TAP_state = `STATE_run_test_idle;
			end
		`STATE_select_ir_scan:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
			else next_TAP_state = `STATE_capture_ir;
			end
		`STATE_capture_ir:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_exit1_ir; 
			else next_TAP_state = `STATE_shift_ir;
			end
		`STATE_shift_ir:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_exit1_ir; 
			else next_TAP_state = `STATE_shift_ir;
			end
		`STATE_exit1_ir:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_update_ir;
			else next_TAP_state = `STATE_pause_ir;
			end
		`STATE_pause_ir:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_exit2_ir;
			else next_TAP_state = `STATE_pause_ir;
			end
		`STATE_exit2_ir:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_update_ir;
			else next_TAP_state = `STATE_shift_ir;
			end
		`STATE_update_ir:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
			else next_TAP_state = `STATE_run_test_idle;
			end
		default: next_TAP_state = `STATE_test_logic_reset;
	endcase
end
 
 

always @ (TAP_state)
begin

	test_logic_reset = 1'b0;
	run_test_idle = 1'b0;
	select_dr_scan = 1'b0;
	capture_dr = 1'b0;
	shift_dr = 1'b0;
	exit1_dr = 1'b0;
	pause_dr = 1'b0;
	exit2_dr = 1'b0;
	update_dr = 1'b0;
	select_ir_scan = 1'b0;
	capture_ir = 1'b0;
	shift_ir = 1'b0;
	exit1_ir = 1'b0;
	pause_ir = 1'b0;
	exit2_ir = 1'b0;
	update_ir = 1'b0;
 
	case(TAP_state)
		`STATE_test_logic_reset: test_logic_reset = 1'b1;
		`STATE_run_test_idle:    run_test_idle = 1'b1;
		`STATE_select_dr_scan:   select_dr_scan = 1'b1;
		`STATE_capture_dr:       capture_dr = 1'b1;
		`STATE_shift_dr:         shift_dr = 1'b1;
		`STATE_exit1_dr:         exit1_dr = 1'b1;
		`STATE_pause_dr:         pause_dr = 1'b1;
		`STATE_exit2_dr:         exit2_dr = 1'b1;
		`STATE_update_dr:        update_dr = 1'b1;
		`STATE_select_ir_scan:   select_ir_scan = 1'b1;
		`STATE_capture_ir:       capture_ir = 1'b1;
		`STATE_shift_ir:         shift_ir = 1'b1;
		`STATE_exit1_ir:         exit1_ir = 1'b1;
		`STATE_pause_ir:         pause_ir = 1'b1;
		`STATE_exit2_ir:         exit2_ir = 1'b1;
		`STATE_update_ir:        update_ir = 1'b1;
		default: ;
	endcase
end
 

 
 
 

reg [`IR_LENGTH-1:0]  jtag_ir;
reg [`IR_LENGTH-1:0]  latched_jtag_ir;
wire                  instruction_tdo;
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
  else if (test_logic_reset == 1)
    jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
  else if(capture_ir)
    jtag_ir <= latched_jtag_ir;
  else if(shift_ir)
    jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
end
 
assign instruction_tdo = jtag_ir[0];
 


always @ (negedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    latched_jtag_ir <= `IDCODE;
  else if (test_logic_reset)
    latched_jtag_ir <= `IDCODE;
  else if(update_ir)
    latched_jtag_ir <= jtag_ir;
end
 

 
 
 

reg [31:0] idcode_reg;
wire        idcode_tdo;
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    idcode_reg <= `IDCODE_VALUE;
  else if (test_logic_reset)
    idcode_reg <= `IDCODE_VALUE;
  else if(idcode_select & capture_dr)
    idcode_reg <=  `IDCODE_VALUE;
  else if(idcode_select & shift_dr)
    idcode_reg <=  {tdi_pad_i, idcode_reg[31:1]};
 
end
 
assign idcode_tdo = idcode_reg[0];
 

 
 

wire  bypassed_tdo;
reg   bypass_reg;
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if (trstn_pad_i == 0)
     bypass_reg <=  1'b0;
  else if (test_logic_reset == 1)
     bypass_reg <=  1'b0;
  else if (bypass_select & capture_dr)
    bypass_reg<= 1'b0;
  else if(bypass_select & shift_dr)
    bypass_reg<= tdi_pad_i;
end
 
assign bypassed_tdo = bypass_reg;
 

 
 

always @ (latched_jtag_ir)
begin
  idcode_select           = 1'b0;
  debug_select            = 1'b0;
  bypass_select           = 1'b0;
  ip1_select              = 1'b0;
  ip2_select              = 1'b0;
 
  case(latched_jtag_ir)
    `IDCODE:            idcode_select           = 1'b1;
    `DEBUG:             debug_select            = 1'b1;
    `IP1:               ip1_select              = 1'b1;
    `IP2:               ip2_select              = 1'b1;
    default:            bypass_select           = 1'b1;
  endcase
end
 
 

reg tdo_mux_out;
 
always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or
          debug_tdo_i or bypassed_tdo or ip1_tdo_i or ip2_tdo_i)
begin
  if(shift_ir)
    tdo_mux_out = instruction_tdo;
  else
    begin
      case(latched_jtag_ir)
        `IDCODE:            tdo_mux_out = idcode_tdo;
        `DEBUG:             tdo_mux_out = debug_tdo_i;
        `IP1:               tdo_mux_out = ip1_tdo_i;
        `IP2:               tdo_mux_out = ip2_tdo_i;
        default:            tdo_mux_out = bypassed_tdo;
      endcase
    end
end
 
 

always @ (negedge tck_pad_i)
begin
	tdo_pad_o = tdo_mux_out;
end
 
 

always @ (posedge tck_pad_i)
begin
  tdo_padoe_o <= shift_ir | shift_dr;
end

 
endmodule
module tap_top(

                tms_pad_i, 
                tck_pad_i, 
                trstn_pad_i, 
                tdi_pad_i, 
                tdo_pad_o, 
                tdo_padoe_o,
 

                test_logic_reset_o,
                run_test_idle_o,
                shift_dr_o,
                pause_dr_o, 
                update_dr_o,
                capture_dr_o,
 

                debug_select_o,
                ip1_select_o,
                ip2_select_o,
 

                tdi_o, 
 

                debug_tdo_i,
                ip1_tdo_i,
                ip2_tdo_i
              );

 
 

input   tms_pad_i;
input   tck_pad_i;
input   trstn_pad_i;
input   tdi_pad_i;
output  tdo_pad_o;
output  tdo_padoe_o;
 

output  test_logic_reset_o;
output  run_test_idle_o;
output  shift_dr_o;
output  pause_dr_o;
output  update_dr_o;
output  capture_dr_o;
 

output  debug_select_o;
output  ip1_select_o;
output  ip2_select_o;
 

output  tdi_o;
 

input   debug_tdo_i;
input   ip1_tdo_i;
input   ip2_tdo_i;
 

reg     test_logic_reset;
reg     run_test_idle;
reg     select_dr_scan;
reg     capture_dr;
reg     shift_dr;
reg     exit1_dr;
reg     pause_dr;
reg     exit2_dr;
reg     update_dr;
reg     select_ir_scan;
reg     capture_ir;
reg     shift_ir;
reg     exit1_ir;
reg     pause_ir;
reg     exit2_ir;
reg     update_ir;
 

reg     idcode_select;
reg     debug_select;
reg     bypass_select;
reg     ip1_select;
reg     ip2_select;
 

reg     tdo_pad_o;
reg     tdo_padoe_o;
 
assign tdi_o = tdi_pad_i;
 
assign test_logic_reset_o = test_logic_reset;
assign run_test_idle_o = run_test_idle;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
assign capture_dr_o = capture_dr;
 
assign debug_select_o = debug_select;
assign ip1_select_o = ip1_select;
assign ip2_select_o = ip2_select;
 
 



`define STATE_test_logic_reset 4'hF
`define STATE_run_test_idle    4'hC
`define STATE_select_dr_scan   4'h7
`define STATE_capture_dr       4'h6
`define STATE_shift_dr         4'h2
`define STATE_exit1_dr         4'h1
`define STATE_pause_dr         4'h3
`define STATE_exit2_dr         4'h0
`define STATE_update_dr        4'h5
`define STATE_select_ir_scan   4'h4
`define STATE_capture_ir       4'hE
`define STATE_shift_ir         4'hA
`define STATE_exit1_ir         4'h9
`define STATE_pause_ir         4'hB
`define STATE_exit2_ir         4'h8
`define STATE_update_ir        4'hD
 
reg [3:0] TAP_state = `STATE_test_logic_reset;
reg [3:0] next_TAP_state;
 

always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
	if(trstn_pad_i == 0)
		TAP_state = `STATE_test_logic_reset;
	else
		TAP_state = next_TAP_state;
end
 
 

always @ (TAP_state or tms_pad_i)
begin
	case(TAP_state)
		`STATE_test_logic_reset:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset; 
			else next_TAP_state = `STATE_run_test_idle;
			end
		`STATE_run_test_idle:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan; 
			else next_TAP_state = `STATE_run_test_idle;
			end
		`STATE_select_dr_scan:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan; 
			else next_TAP_state = `STATE_capture_dr;
			end
		`STATE_capture_dr:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_exit1_dr; 
			else next_TAP_state = `STATE_shift_dr;
			end
		`STATE_shift_dr:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_exit1_dr; 
			else next_TAP_state = `STATE_shift_dr;
			end
		`STATE_exit1_dr:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_update_dr; 
			else next_TAP_state = `STATE_pause_dr;
			end
		`STATE_pause_dr:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_exit2_dr; 
			else next_TAP_state = `STATE_pause_dr;
			end
		`STATE_exit2_dr:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_update_dr; 
			else next_TAP_state = `STATE_shift_dr;
			end
		`STATE_update_dr:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan; 
			else next_TAP_state = `STATE_run_test_idle;
			end
		`STATE_select_ir_scan:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
			else next_TAP_state = `STATE_capture_ir;
			end
		`STATE_capture_ir:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_exit1_ir; 
			else next_TAP_state = `STATE_shift_ir;
			end
		`STATE_shift_ir:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_exit1_ir; 
			else next_TAP_state = `STATE_shift_ir;
			end
		`STATE_exit1_ir:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_update_ir;
			else next_TAP_state = `STATE_pause_ir;
			end
		`STATE_pause_ir:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_exit2_ir;
			else next_TAP_state = `STATE_pause_ir;
			end
		`STATE_exit2_ir:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_update_ir;
			else next_TAP_state = `STATE_shift_ir;
			end
		`STATE_update_ir:
			begin
			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
			else next_TAP_state = `STATE_run_test_idle;
			end
		default: next_TAP_state = `STATE_test_logic_reset;
	endcase
end
 
 

always @ (TAP_state)
begin

	test_logic_reset = 1'b0;
	run_test_idle = 1'b0;
	select_dr_scan = 1'b0;
	capture_dr = 1'b0;
	shift_dr = 1'b0;
	exit1_dr = 1'b0;
	pause_dr = 1'b0;
	exit2_dr = 1'b0;
	update_dr = 1'b0;
	select_ir_scan = 1'b0;
	capture_ir = 1'b0;
	shift_ir = 1'b0;
	exit1_ir = 1'b0;
	pause_ir = 1'b0;
	exit2_ir = 1'b0;
	update_ir = 1'b0;
 
	case(TAP_state)
		`STATE_test_logic_reset: test_logic_reset = 1'b1;
		`STATE_run_test_idle:    run_test_idle = 1'b1;
		`STATE_select_dr_scan:   select_dr_scan = 1'b1;
		`STATE_capture_dr:       capture_dr = 1'b1;
		`STATE_shift_dr:         shift_dr = 1'b1;
		`STATE_exit1_dr:         exit1_dr = 1'b1;
		`STATE_pause_dr:         pause_dr = 1'b1;
		`STATE_exit2_dr:         exit2_dr = 1'b1;
		`STATE_update_dr:        update_dr = 1'b1;
		`STATE_select_ir_scan:   select_ir_scan = 1'b1;
		`STATE_capture_ir:       capture_ir = 1'b1;
		`STATE_shift_ir:         shift_ir = 1'b1;
		`STATE_exit1_ir:         exit1_ir = 1'b1;
		`STATE_pause_ir:         pause_ir = 1'b1;
		`STATE_exit2_ir:         exit2_ir = 1'b1;
		`STATE_update_ir:        update_ir = 1'b1;
		default: ;
	endcase
end
 

 
 
 

reg [`IR_LENGTH-1:0]  jtag_ir;
reg [`IR_LENGTH-1:0]  latched_jtag_ir;
wire                  instruction_tdo;
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
  else if (test_logic_reset == 1)
    jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
  else if(capture_ir)
    jtag_ir <= latched_jtag_ir;
  else if(shift_ir)
    jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
end
 
assign instruction_tdo = jtag_ir[0];
 


always @ (negedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    latched_jtag_ir <= `IDCODE;
  else if (test_logic_reset)
    latched_jtag_ir <= `IDCODE;
  else if(update_ir)
    latched_jtag_ir <= jtag_ir;
end
 

 
 
 

reg [31:0] idcode_reg;
wire        idcode_tdo;
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    idcode_reg <= `IDCODE_VALUE;
  else if (test_logic_reset)
    idcode_reg <= `IDCODE_VALUE;
  else if(idcode_select & capture_dr)
    idcode_reg <=  `IDCODE_VALUE;
  else if(idcode_select & shift_dr)
    idcode_reg <=  {tdi_pad_i, idcode_reg[31:1]};
 
end
 
assign idcode_tdo = idcode_reg[0];
 

 
 

wire  bypassed_tdo;
reg   bypass_reg;
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if (trstn_pad_i == 0)
     bypass_reg <=  1'b0;
  else if (test_logic_reset == 1)
     bypass_reg <=  1'b0;
  else if (bypass_select & capture_dr)
    bypass_reg<= 1'b0;
  else if(bypass_select & shift_dr)
    bypass_reg<= tdi_pad_i;
end
 
assign bypassed_tdo = bypass_reg;
 

 
 

always @ (latched_jtag_ir)
begin
  idcode_select           = 1'b0;
  debug_select            = 1'b0;
  bypass_select           = 1'b0;
  ip1_select              = 1'b0;
  ip2_select              = 1'b0;
 
  case(latched_jtag_ir)
    `IDCODE:            idcode_select           = 1'b1;
    `DEBUG:             debug_select            = 1'b1;
    `IP1:               ip1_select              = 1'b1;
    `IP2:               ip2_select              = 1'b1;
    default:            bypass_select           = 1'b1;
  endcase
end
 
 

reg tdo_mux_out;
 
always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or
          debug_tdo_i or bypassed_tdo or ip1_tdo_i or ip2_tdo_i)
begin
  if(shift_ir)
    tdo_mux_out = instruction_tdo;
  else
    begin
      case(latched_jtag_ir)
        `IDCODE:            tdo_mux_out = idcode_tdo;
        `DEBUG:             tdo_mux_out = debug_tdo_i;
        `IP1:               tdo_mux_out = ip1_tdo_i;
        `IP2:               tdo_mux_out = ip2_tdo_i;
        default:            tdo_mux_out = bypassed_tdo;
      endcase
    end
end
 
 

always @ (negedge tck_pad_i)
begin
	tdo_pad_o = tdo_mux_out;
end
 
 

always @ (posedge tck_pad_i)
begin
  tdo_padoe_o <= shift_ir | shift_dr;
end

 
endmodule