data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:23: Cannot find include file: FIFO.syn.v\n`include "FIFO.syn.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/processor/syn/netlist,data/full_repos/permissive/21051978/FIFO.syn.v\n             data/full_repos/permissive/21051978/processor/syn/netlist,data/full_repos/permissive/21051978/FIFO.syn.v.v\n             data/full_repos/permissive/21051978/processor/syn/netlist,data/full_repos/permissive/21051978/FIFO.syn.v.sv\n             FIFO.syn.v\n             FIFO.syn.v.v\n             FIFO.syn.v.sv\n             obj_dir/FIFO.syn.v\n             obj_dir/FIFO.syn.v.v\n             obj_dir/FIFO.syn.v.sv\n%Error: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:24: Cannot find include file: /auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v\n`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:112: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:113: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 1;\n     ^\n%Error: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:161: Unsupported or unknown PLI call: $sdf_annotate\n  $sdf_annotate("../sdf/FIFO.sdf",fifo_cb,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");\n  ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:187: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:194: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:201: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:208: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:215: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:222: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:229: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:237: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:244: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:251: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:258: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:265: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:272: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:279: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:286: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:306: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:313: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/syn/netlist/fifotb2.v:370: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Error: Exiting due to 3 error(s), 22 warning(s)\n'
module tb_fifo();

	parameter DEPTH = 8;

	parameter WIDTH = 8;
	
	
	
	
	
	
	


	


	wire [7:0] d_out;
	wire empty_cb,full_cb;
	
	
	
	
	
	
	

	


	reg push_cb,pop_cb,rst,clock;

	reg [WIDTH-1:0] d_in;
	
	
	
	
	
	
	
	
	



	
	
	
	
	
	
	
	
	
	
	
	

	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;
    end	
	
	
	
	
	
	
	
	
	

	

	FIFO fifo_cb (


		d_out,empty_cb,full_cb,d_in,push_cb,pop_cb,rst,clock);
	
	
	
	
	
	

	

	initial
	begin
		$sdf_annotate("../sdf/FIFO.sdf",fifo_cb,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");

		$display($time, " << Starting the simulation >>");

		rst=1'd1;
		push_cb=1'd0;
		pop_cb=1'd0;
		d_in=8'd45;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd231;
		
		

		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd230;
		
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd179;
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd37;
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd174;
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd179;
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd235;
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd39;
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd201;
		
		

		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		


		
		
		
				

		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd18;

		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		
		
		

		
		
		
		
		
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_fifo();


	parameter DEPTH = 8;

	parameter WIDTH = 8;
	
	
	
	
	
	
	


	


	wire [7:0] d_out;
	wire empty_cb,full_cb;
	
	
	
	
	
	
	

	


	reg push_cb,pop_cb,rst,clock;

	reg [WIDTH-1:0] d_in;
	
	
	
	
	
	
	
	
	



	
	
	
	
	
	
	
	
	
	
	
	

	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;
    end	
	
	
	
	
	
	
	
	
	

	

	FIFO fifo_cb (


		d_out,empty_cb,full_cb,d_in,push_cb,pop_cb,rst,clock);
	
	
	
	
	
	

	

	initial
	begin
		$sdf_annotate("../sdf/FIFO.sdf",fifo_cb,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");

		$display($time, " << Starting the simulation >>");

		rst=1'd1;
		push_cb=1'd0;
		pop_cb=1'd0;
		d_in=8'd45;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd231;
		
		

		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd230;
		
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd179;
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd37;
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd174;
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd179;
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd235;
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd39;
		
		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd201;
		
		

		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		


		
		
		
				

		
		#10
		rst=1'd0;
		push_cb=1'd1;
		pop_cb=1'd0;
		d_in=8'd18;

		
		#10
		rst=1'd0;
		push_cb=1'd0;
		pop_cb=1'd1;
		d_in=8'd12;
		
		
		
		
		

		
		
		
		
		
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule