data/full_repos/permissive/156417892/hdl/Execute/MuxRegDest/MuxRegDest_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/MuxRegDest/MuxRegDest_test.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/MuxRegDest/MuxRegDest_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/Execute/MuxRegDest/MuxRegDest_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: data/full_repos/permissive/156417892/hdl/Execute/MuxRegDest/MuxRegDest_test.v:31: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("./vvp.out.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/156417892/hdl/Execute/MuxRegDest/MuxRegDest_test.v:32: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_test;


   reg [4:0] rt, rd;
   reg RegDest;
   

   wire [4:0] rw;
   

   MuxRegDest uut(rt,
              rd,
              RegDest,
              rw);
              
   initial begin

    #10;
    rt = 5'h1F;
    rd = 5'h0F;
    RegDest = 1;
    #10;
    RegDest = 0;
    #10;
   end


   initial begin
      $dumpfile("./vvp.out.vcd");
      $dumpvars;
   end

endmodule
module main_test;



   reg [4:0] rt, rd;
   reg RegDest;
   

   wire [4:0] rw;
   

   MuxRegDest uut(rt,
              rd,
              RegDest,
              rw);
              
   initial begin

    #10;
    rt = 5'h1F;
    rd = 5'h0F;
    RegDest = 1;
    #10;
    RegDest = 0;
    #10;
   end


   initial begin
      $dumpfile("./vvp.out.vcd");
      $dumpvars;
   end

endmodule