data/full_repos/permissive/166115772/old_attempt/verilog/calcu-16.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/166115772/old_attempt/verilog/calcu-16.v:4: Little bit endian vector: MSB < LSB of bit range: 0:25\n    wire [0:25] instruction, memDataOut;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/old_attempt/verilog/calcu-16.v:6: Little bit endian vector: MSB < LSB of bit range: 0:2\n    wire [0:2] aluSel, regSel1, regSel2, regSelData;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/old_attempt/verilog/calcu-16.v:7: Little bit endian vector: MSB < LSB of bit range: 0:15\n    wire [0:15] aluOut, regDataOut1, regDataOut2, aluA, aluB, regDataIn, address;\n         ^\n%Error: data/full_repos/permissive/166115772/old_attempt/verilog/calcu-16.v:9: Cannot find file containing module: \'controlUnit\'\n    controlUnit ctrlUnit (\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166115772/old_attempt/verilog,data/full_repos/permissive/166115772/controlUnit\n             data/full_repos/permissive/166115772/old_attempt/verilog,data/full_repos/permissive/166115772/controlUnit.v\n             data/full_repos/permissive/166115772/old_attempt/verilog,data/full_repos/permissive/166115772/controlUnit.sv\n             controlUnit\n             controlUnit.v\n             controlUnit.sv\n             obj_dir/controlUnit\n             obj_dir/controlUnit.v\n             obj_dir/controlUnit.sv\n%Error: data/full_repos/permissive/166115772/old_attempt/verilog/calcu-16.v:29: Cannot find file containing module: \'regFile\'\n    regFile registerFile (\n    ^~~~~~~\n%Error: data/full_repos/permissive/166115772/old_attempt/verilog/calcu-16.v:39: Cannot find file containing module: \'memory\'\n    memory RAM (\n    ^~~~~~\n%Error: data/full_repos/permissive/166115772/old_attempt/verilog/calcu-16.v:46: Cannot find file containing module: \'alu\'\n    alu ALU (\n    ^~~\n%Error: data/full_repos/permissive/166115772/old_attempt/verilog/calcu-16.v:55: Cannot find file containing module: \'programCounter\'\n    programCounter PC (\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/166115772/old_attempt/verilog/calcu-16.v:62: Cannot find file containing module: \'instructionReg\'\n    instructionReg IR (\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 3 warning(s)\n'
module calcu16 (
    input clk
);
    wire [0:25] instruction, memDataOut;
    wire aluCarry, aluEnable, regLoad, instrLoad, pcClk;
    wire [0:2] aluSel, regSel1, regSel2, regSelData;
    wire [0:15] aluOut, regDataOut1, regDataOut2, aluA, aluB, regDataIn, address;

    controlUnit ctrlUnit (
        .clk(clk),
        .aluCarry(aluCarry),
        .instruction(instruction),
        .aluOut(aluOut),
        .regDataOut1(regDataOut1),
        .regDataOut2(regDataOut2),
        .aluEnable(aluEnable),
        .regLoad(regLoad),
        .instrLoad(instrLoad),
        .pcClk(pcClk),
        .aluSel(aluSel),
        .regSel1(regSel1),
        .regSel2(regSel2),
        .regSelData(regSelData),
        .aluA(aluA),
        .aluB(aluB),
        .regDataIn(regDataIn)
    );
    
    regFile registerFile (
        .sel1(regSel1),
        .sel2(regSel2),
        .dataSel(regSelData),
        .dataIn(regDataIn),
        .load(regLoad),
        .dataOut1(regDataOut1),
        .dataOut2(regDataOut2)
    );

    memory RAM (
        .load(),
        .dataIn(),
        .address(address),
        .dataOut(memDataOut)
    );
    
    alu ALU (
        .a(aluA),
        .b(aluB),
        .select(aluSel),
        .enable(aluEnable),
        .out(aluOut),
        .carry(aluCarry)
    );

    programCounter PC (
        .data(),
        .load(),
        .clk(pcClk),
        .count(address)
    );
    
    instructionReg IR (
        .dataIn(memDataOut),
        .load(instrLoad),
        .dataOut(instruction)
    );
endmodule
module calcu16 (
    input clk
);

    wire [0:25] instruction, memDataOut;
    wire aluCarry, aluEnable, regLoad, instrLoad, pcClk;
    wire [0:2] aluSel, regSel1, regSel2, regSelData;
    wire [0:15] aluOut, regDataOut1, regDataOut2, aluA, aluB, regDataIn, address;

    controlUnit ctrlUnit (
        .clk(clk),
        .aluCarry(aluCarry),
        .instruction(instruction),
        .aluOut(aluOut),
        .regDataOut1(regDataOut1),
        .regDataOut2(regDataOut2),
        .aluEnable(aluEnable),
        .regLoad(regLoad),
        .instrLoad(instrLoad),
        .pcClk(pcClk),
        .aluSel(aluSel),
        .regSel1(regSel1),
        .regSel2(regSel2),
        .regSelData(regSelData),
        .aluA(aluA),
        .aluB(aluB),
        .regDataIn(regDataIn)
    );
    
    regFile registerFile (
        .sel1(regSel1),
        .sel2(regSel2),
        .dataSel(regSelData),
        .dataIn(regDataIn),
        .load(regLoad),
        .dataOut1(regDataOut1),
        .dataOut2(regDataOut2)
    );

    memory RAM (
        .load(),
        .dataIn(),
        .address(address),
        .dataOut(memDataOut)
    );
    
    alu ALU (
        .a(aluA),
        .b(aluB),
        .select(aluSel),
        .enable(aluEnable),
        .out(aluOut),
        .carry(aluCarry)
    );

    programCounter PC (
        .data(),
        .load(),
        .clk(pcClk),
        .count(address)
    );
    
    instructionReg IR (
        .dataIn(memDataOut),
        .load(instrLoad),
        .dataOut(instruction)
    );
endmodule