data/full_repos/permissive/191241380/common/videosyncs.v
1: b'%Warning-UNSIGNED: data/full_repos/permissive/191241380/common/videosyncs.v:70: Comparison is constant due to unsigned arithmetic\n                                                                              : ... In instance videosyncs\n    if (hcont>=8 && hcont<HACTIVE+8 && vcont>=0 && vcont<VACTIVE)\n                                            ^~\n                   ... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module videosyncs (
  input wire clk,
  output reg hs,
  output reg vs,
 	output wire [10:0] hc,
  output wire [10:0] vc,
  output reg display_enable
  );
	





  parameter HACTIVE     = 640;
  parameter HFRONTPORCH = 656;
  parameter HSYNCPULSE  = 752;
	parameter HTOTAL      = 800;
  parameter VACTIVE     = 480;
  parameter VFRONTPORCH = 490;
  parameter VSYNCPULSE  = 492;
  parameter VTOTAL      = 525;
  parameter HSYNCPOL    = 1'b0;
  parameter VSYNCPOL    = 1'b0;

  reg [10:0] hcont = 0;
  reg [10:0] vcont = 0;
	
  assign hc = hcont;
  assign vc = vcont;


  always @(posedge clk) begin
      if (hcont == HTOTAL-1) begin
         hcont <= 11'd0;
         if (vcont == VTOTAL-1) begin
            vcont <= 11'd0;
         end
         else begin
            vcont <= vcont + 11'd1;
         end
      end
      else begin
         hcont <= hcont + 11'd1;
      end
  end
   

  always @* begin
    if (hcont>=8 && hcont<HACTIVE+8 && vcont>=0 && vcont<VACTIVE)
      display_enable = 1'b1;
    else
      display_enable = 1'b0;

    if (hcont>=HFRONTPORCH+8 && hcont<HSYNCPULSE+8)
      hs = HSYNCPOL;
    else
      hs = ~HSYNCPOL;

    if (vcont>=VFRONTPORCH && vcont<VSYNCPULSE)
      vs = VSYNCPOL;
    else
      vs = ~VSYNCPOL;
  end
endmodule
module videosyncs (
  input wire clk,
  output reg hs,
  output reg vs,
 	output wire [10:0] hc,
  output wire [10:0] vc,
  output reg display_enable
  );

	





  parameter HACTIVE     = 640;
  parameter HFRONTPORCH = 656;
  parameter HSYNCPULSE  = 752;
	parameter HTOTAL      = 800;
  parameter VACTIVE     = 480;
  parameter VFRONTPORCH = 490;
  parameter VSYNCPULSE  = 492;
  parameter VTOTAL      = 525;
  parameter HSYNCPOL    = 1'b0;
  parameter VSYNCPOL    = 1'b0;

  reg [10:0] hcont = 0;
  reg [10:0] vcont = 0;
	
  assign hc = hcont;
  assign vc = vcont;


  always @(posedge clk) begin
      if (hcont == HTOTAL-1) begin
         hcont <= 11'd0;
         if (vcont == VTOTAL-1) begin
            vcont <= 11'd0;
         end
         else begin
            vcont <= vcont + 11'd1;
         end
      end
      else begin
         hcont <= hcont + 11'd1;
      end
  end
   

  always @* begin
    if (hcont>=8 && hcont<HACTIVE+8 && vcont>=0 && vcont<VACTIVE)
      display_enable = 1'b1;
    else
      display_enable = 1'b0;

    if (hcont>=HFRONTPORCH+8 && hcont<HSYNCPULSE+8)
      hs = HSYNCPOL;
    else
      hs = ~HSYNCPOL;

    if (vcont>=VFRONTPORCH && vcont<VSYNCPULSE)
      vs = VSYNCPOL;
    else
      vs = ~VSYNCPOL;
  end
endmodule