data/full_repos/permissive/140357212/Tomasulo/sete_seg.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/140357212/Tomasulo/sete_seg.v:3: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output reg [0:6] out;\n             ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sete_seg (Entrada, out);
  input [3:0] Entrada;
  output reg [0:6] out;


  always begin
    case(Entrada)
   4'b0000: out = 7'b1000000;
	4'b0001: out = 7'b1111001;
	4'b0010: out = 7'b0100100;
	4'b0011: out = 7'b0110000;
	4'b0100: out = 7'b0011001;
	4'b0101: out = 7'b0010010;
	4'b0110: out = 7'b0000010;
	4'b0111: out = 7'b1111000;
	4'b1000: out = 7'b0000000;
	4'b1001: out = 7'b0011000;
	default: out = 7'b1000000;

    endcase
  end
endmodule
module sete_seg (Entrada, out);

  input [3:0] Entrada;
  output reg [0:6] out;


  always begin
    case(Entrada)
   4'b0000: out = 7'b1000000;
	4'b0001: out = 7'b1111001;
	4'b0010: out = 7'b0100100;
	4'b0011: out = 7'b0110000;
	4'b0100: out = 7'b0011001;
	4'b0101: out = 7'b0010010;
	4'b0110: out = 7'b0000010;
	4'b0111: out = 7'b1111000;
	4'b1000: out = 7'b0000000;
	4'b1001: out = 7'b0011000;
	default: out = 7'b1000000;

    endcase
  end
endmodule