data/full_repos/permissive/20270692/labs/lab8/jk/jk_flipflop.v
data/verilator_xmls/9c8bda26-f023-459d-864f-60a9bc7905d9.xml
module jk_ff (j, k, clk, q, qb);

  input j, k, clk;
  wire j, k, clk;

  output q, qb;
  reg q, qb;

  always @ (posedge clk)
  case ({j,k})
    2'b00: begin


           end
    2'b01: begin
             q <=1'b0;
             qb<=1'b1;
           end
    2'b10: begin
             q <=1'b1;
             qb<=1'b0;
           end
    2'b11: begin
             q <=qb;
             qb<= q;
           end
  endcase

endmodule
module jk_ff (j, k, clk, q, qb);


  input j, k, clk;
  wire j, k, clk;

  output q, qb;
  reg q, qb;

  always @ (posedge clk)
  case ({j,k})
    2'b00: begin


           end
    2'b01: begin
             q <=1'b0;
             qb<=1'b1;
           end
    2'b10: begin
             q <=1'b1;
             qb<=1'b0;
           end
    2'b11: begin
             q <=qb;
             qb<= q;
           end
  endcase

endmodule