data/full_repos/permissive/105546923/projects/blink/sim/top_tb.v
 line:12: before: "$"
1: b'%Error: data/full_repos/permissive/105546923/projects/blink/sim/top_tb.v:9: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./build/iverilog/blink.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/105546923/projects/blink/sim/top_tb.v:10: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,top_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/blink/sim/top_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n # 500 $finish;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105546923/projects/blink/sim/top_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk_i = ~clk_i;\n          ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb;

   reg clk_i = 0;
   wire [7:0] led_o;
   
   initial
     begin
	
	$dumpfile("./build/iverilog/blink.vcd");
	$dumpvars(0,top_tb);
	
	# 500 $finish;
	
     end

   
   always #1 clk_i = ~clk_i;
   
   
   top tb (
	   .ice_clk_i (clk_i),
	   .led_o (led_o)
	   );
    

endmodule
module top_tb;


   reg clk_i = 0;
   wire [7:0] led_o;
   
   initial
     begin
	
	$dumpfile("./build/iverilog/blink.vcd");
	$dumpvars(0,top_tb);
	
	# 500 $finish;
	
     end

   
   always #1 clk_i = ~clk_i;
   
   
   top tb (
	   .ice_clk_i (clk_i),
	   .led_o (led_o)
	   );
    

endmodule