data/full_repos/permissive/106408053/verilog/trigger_adv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n              ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module trigterm_4bit (addr, clock, wrenb, din, dout, hit);
input [3:0] addr;
input clock, wrenb, din;
output dout, hit;
SRLC16E ram (
  .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), 
  .CLK(clock), .CE(wrenb), .D(din), .Q15(dout), .Q(hit));
endmodule
module trigterm_4bit (addr, clock, wrenb, din, dout, hit);

input [3:0] addr;
input clock, wrenb, din;
output dout, hit;
SRLC16E ram (
  .A0(addr[0]), .A1(addr[1]), .A2(addr[2]), .A3(addr[3]), 
  .CLK(clock), .CE(wrenb), .D(din), .Q15(dout), .Q(hit));
endmodule