data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Division/flot_Divide.v
1: b'%Error: Cannot find file containing module: Project/SourceCode/Division,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Division,data/full_repos/permissive/119107706\n             Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Division/flot_Divide.v\n%Error: Exiting due to 3 error(s)\n'
module flot_Divide
			#(parameter 		  
			 
									  WIDTH = 32,
									  WIDTH_exp = 8,
									  WIDTH_mat = 23,
									  LUT_addWidth = 12,
									  LUT_bits = 24

									  
									  )
			( input 				  CLK,
									  nRST,
			  input [WIDTH-1:0] OP1,
			  input [WIDTH-1:0] OP2,
			  input 				  CE,								
			  input 				  exce_in,
			  output reg 		  exce_out,
			  output [WIDTH_mat+WIDTH_exp:0] result
			 ); 				 

wire exce_out_rec, exce_out_mul;
wire [WIDTH-1:0] result_rec;



	flot_Rec_Hung
	  #(
		.WIDTH(WIDTH),	
		.WIDTH_exp(WIDTH_exp),
		.WIDTH_mat(WIDTH_mat),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth)
		)
	Fang_flo_Rec_Hung 
		(
		.CLK(CLK), 
		.nRST(nRST), 
		.OP(OP2), 
		.CE(CE),
		.exce_in(exce_in),
		.result(result_rec),
		.exce_out(exce_out_rec)
		);



	multiplier_float 
	#(
		.WIDTH(WIDTH),	
		.WIDTH_exp(WIDTH_exp),
		.WIDTH_mat(WIDTH_mat)
		)
	Fang_floMul (
		.CLK(CLK), 
		.RST(RST), 
		.OP1(OP1), 
		.OP2(result_rec), 
		.exce_in(exce_in), 
		.exce_out(exce_out_mul), 
		.result(result)
	);



always @* begin
	if(exce_in||exce_out_mul||exce_out_rec) 
		exce_out <= 1'b1;
	else
		exce_out <= 1'b0;
end


endmodule
module flot_Divide
			#(parameter 		  
			 
									  WIDTH = 32,
									  WIDTH_exp = 8,
									  WIDTH_mat = 23,
									  LUT_addWidth = 12,
									  LUT_bits = 24

									  
									  )
			( input 				  CLK,
									  nRST,
			  input [WIDTH-1:0] OP1,
			  input [WIDTH-1:0] OP2,
			  input 				  CE,								
			  input 				  exce_in,
			  output reg 		  exce_out,
			  output [WIDTH_mat+WIDTH_exp:0] result
			 );
 				 

wire exce_out_rec, exce_out_mul;
wire [WIDTH-1:0] result_rec;



	flot_Rec_Hung
	  #(
		.WIDTH(WIDTH),	
		.WIDTH_exp(WIDTH_exp),
		.WIDTH_mat(WIDTH_mat),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth)
		)
	Fang_flo_Rec_Hung 
		(
		.CLK(CLK), 
		.nRST(nRST), 
		.OP(OP2), 
		.CE(CE),
		.exce_in(exce_in),
		.result(result_rec),
		.exce_out(exce_out_rec)
		);



	multiplier_float 
	#(
		.WIDTH(WIDTH),	
		.WIDTH_exp(WIDTH_exp),
		.WIDTH_mat(WIDTH_mat)
		)
	Fang_floMul (
		.CLK(CLK), 
		.RST(RST), 
		.OP1(OP1), 
		.OP2(result_rec), 
		.exce_in(exce_in), 
		.exce_out(exce_out_mul), 
		.result(result)
	);



always @* begin
	if(exce_in||exce_out_mul||exce_out_rec) 
		exce_out <= 1'b1;
	else
		exce_out <= 1'b0;
end


endmodule