data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v
 line:78: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Error: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_execute_alu.v:81: Cannot find file containing module: \'seg_execute_alu\'\n    seg_execute_alu \n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_execute_alu\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_execute_alu.v\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_execute_alu.sv\n             seg_execute_alu\n             seg_execute_alu.v\n             seg_execute_alu.sv\n             obj_dir/seg_execute_alu\n             obj_dir/seg_execute_alu.v\n             obj_dir/seg_execute_alu.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_seg_execute_alu();
    
    localparam LEN          = 32;
    localparam NB_ALUCTL    = 4;
    

    reg  [NB_ALUCTL - 1: 0]     i_ALUctl;
    reg  [LEN - 1: 0]           i_data_a;
    reg  [LEN - 1: 0]           i_data_b;

    wire [LEN - 1: 0]    o_ALUOut;
    wire                 o_zero;

    initial 
    begin
        i_ALUctl    = 0;
        i_data_a    = 0;
        i_data_b    = 0;

        #10
        i_data_a    = 32'h00001111; 
        i_data_b    = 32'h11110000;
        #10
        i_ALUctl = 4'b0000;
        #10
        i_ALUctl = 4'b0001;
        #10
        i_ALUctl = 4'b0010;
        #10
        i_ALUctl = 4'b0011;
        #10
        i_data_a    = 32'h11111111; 
        i_data_b    = 32'h11110000;
        i_ALUctl = 4'b0110;
        #10
        i_data_a    = 3; 
        i_data_b    = 2;
        i_ALUctl = 4'b0111;
        #10
        i_ALUctl = 4'b1000;
        #10
        i_ALUctl = 4'b1001;
        #10
        i_ALUctl = 4'b1010;
        #10
        i_data_a    = 32'h00001111; 
        i_data_b    = 2;
        i_ALUctl = 4'b1011;
        #10
        i_data_a    = 32'h11110000; 
        i_data_b    = 2;
        i_ALUctl = 4'b1100;
        #10
        i_ALUctl = 4'b1101;

        #10 $finish;
    end

    seg_execute_alu 
    #(
        .LEN        (LEN        ),
        .NB_ALUCTL  (NB_ALUCTL  )
    )
    u_seg_execute_alu
    (
    	.i_ALUctl   (i_ALUctl    ),
        .i_data_a   (i_data_a   ),
        .i_data_b   (i_data_b   ),
        .o_ALUOut   (o_ALUOut   ),
        .o_zero     (o_zero     )
    );

endmodule
module tb_seg_execute_alu();

    
    localparam LEN          = 32;
    localparam NB_ALUCTL    = 4;
    

    reg  [NB_ALUCTL - 1: 0]     i_ALUctl;
    reg  [LEN - 1: 0]           i_data_a;
    reg  [LEN - 1: 0]           i_data_b;

    wire [LEN - 1: 0]    o_ALUOut;
    wire                 o_zero;

    initial 
    begin
        i_ALUctl    = 0;
        i_data_a    = 0;
        i_data_b    = 0;

        #10
        i_data_a    = 32'h00001111; 
        i_data_b    = 32'h11110000;
        #10
        i_ALUctl = 4'b0000;
        #10
        i_ALUctl = 4'b0001;
        #10
        i_ALUctl = 4'b0010;
        #10
        i_ALUctl = 4'b0011;
        #10
        i_data_a    = 32'h11111111; 
        i_data_b    = 32'h11110000;
        i_ALUctl = 4'b0110;
        #10
        i_data_a    = 3; 
        i_data_b    = 2;
        i_ALUctl = 4'b0111;
        #10
        i_ALUctl = 4'b1000;
        #10
        i_ALUctl = 4'b1001;
        #10
        i_ALUctl = 4'b1010;
        #10
        i_data_a    = 32'h00001111; 
        i_data_b    = 2;
        i_ALUctl = 4'b1011;
        #10
        i_data_a    = 32'h11110000; 
        i_data_b    = 2;
        i_ALUctl = 4'b1100;
        #10
        i_ALUctl = 4'b1101;

        #10 $finish;
    end

    seg_execute_alu 
    #(
        .LEN        (LEN        ),
        .NB_ALUCTL  (NB_ALUCTL  )
    )
    u_seg_execute_alu
    (
    	.i_ALUctl   (i_ALUctl    ),
        .i_data_a   (i_data_a   ),
        .i_data_b   (i_data_b   ),
        .o_ALUOut   (o_ALUOut   ),
        .o_zero     (o_zero     )
    );

endmodule