data/full_repos/permissive/157005262/verilog/adder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/157005262/verilog/adder.v:6: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'c_in\' generates 1 bits.\n                                                                      : ... In instance adder8.a1\n  assign s = x + y + c_in;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/157005262/verilog/adder.v:7: Operator ADD expects 32 or 5 bits on the RHS, but RHS\'s VARREF \'c_in\' generates 1 bits.\n                                                                      : ... In instance adder8.a1\n  assign c_out = (x + y + c_in) >= 16;\n                        ^\n%Error: Exiting due to 2 warning(s)\n'
module adder4(input wire [3:0] x,
              input wire [3:0] y,
              input wire c_in,
              output wire [3:0] s,
              output wire c_out);
  assign s = x + y + c_in;
  assign c_out = (x + y + c_in) >= 16;
endmodule
module adder4(input wire [3:0] x,
              input wire [3:0] y,
              input wire c_in,
              output wire [3:0] s,
              output wire c_out);

  assign s = x + y + c_in;
  assign c_out = (x + y + c_in) >= 16;
endmodule