data/full_repos/permissive/132220215/nBitAdder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/132220215/nBitAdder.v:19: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'Cin\' generates 1 bits.\n                                                                   : ... In instance nBitAdder\n assign {Cout,Sum} = a + b + Cin;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module nBitAdder(

   Cout,
   Sum,
   a,
   b,
   Cin);

 
 parameter N = 8;
 output Cout;
 output [N-1:0] Sum;
 input [N-1:0] a;
 input [N-1:0] b;
 input Cin; 

 assign {Cout,Sum} = a + b + Cin;
endmodule
module nBitAdder(

   Cout,
   Sum,
   a,
   b,
   Cin);


 
 parameter N = 8;
 output Cout;
 output [N-1:0] Sum;
 input [N-1:0] a;
 input [N-1:0] b;
 input Cin; 

 assign {Cout,Sum} = a + b + Cin;
endmodule