data/full_repos/permissive/166014265/test/ClockDomain.v
 line:16: before: ";"
1: b'%Error: data/full_repos/permissive/166014265/test/ClockDomain.v:16: Unsupported: event data types\nevent      eCLK;\n^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/166014265/test/ClockDomain.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #(N_CYCLE) CLK = 1\'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/166014265/test/ClockDomain.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #(P_CYCLE) CLK = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/166014265/test/ClockDomain.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #(DELAY) forever begin\n    ^\n%Error: data/full_repos/permissive/166014265/test/ClockDomain.v:33: syntax error, unexpected \'@\'\n    @(posedge CLK) #(STB) RST = 1\'b1;\n    ^\n%Error: data/full_repos/permissive/166014265/test/ClockDomain.v:39: syntax error, unexpected \'@\'\n        @(posedge CLK) #(STB) -> eCLK;\n        ^\n%Error: data/full_repos/permissive/166014265/test/ClockDomain.v:45: syntax error, unexpected \'@\'\n    @(posedge CLK);\n    ^\n%Error: data/full_repos/permissive/166014265/test/ClockDomain.v:52: syntax error, unexpected \'@\'\n    @(posedge CLK);\n    ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ClockDomain #
( parameter CYCLE = 10000
, parameter DUTY  = 50
, parameter PHASE = 0
);

localparam N_CYCLE = CYCLE * (100 - DUTY) / 100;
localparam P_CYCLE = CYCLE * DUTY / 100;
localparam DELAY   = CYCLE * PHASE / 360;

localparam STB = 1;

reg        CLK;
event      eCLK;
reg        RST;
reg        EN;
reg [31:0] CNT;


initial begin
    CLK = 1'b0;
    #(DELAY) forever begin
        #(N_CYCLE) CLK = 1'b1;
        #(P_CYCLE) CLK = 1'b0;
    end
end


initial begin
    RST = 1'b0;
    @(posedge CLK) #(STB) RST = 1'b1;
    @(posedge CLK) #(STB) RST = 1'b0;
end

initial begin
    forever
        @(posedge CLK) #(STB) -> eCLK;
end


initial begin
    EN = 1'b0;
    @(posedge CLK);
    @(posedge CLK) #(STB) EN = 1'b1;
end


initial begin
    CNT = {32{1'b0}};
    @(posedge CLK);
    forever
        @(posedge CLK) #(STB) CNT = CNT + 1'b1;
end

endmodule
module ClockDomain #
( parameter CYCLE = 10000
, parameter DUTY  = 50
, parameter PHASE = 0
);


localparam N_CYCLE = CYCLE * (100 - DUTY) / 100;
localparam P_CYCLE = CYCLE * DUTY / 100;
localparam DELAY   = CYCLE * PHASE / 360;

localparam STB = 1;

reg        CLK;
event      eCLK;
reg        RST;
reg        EN;
reg [31:0] CNT;


initial begin
    CLK = 1'b0;
    #(DELAY) forever begin
        #(N_CYCLE) CLK = 1'b1;
        #(P_CYCLE) CLK = 1'b0;
    end
end


initial begin
    RST = 1'b0;
    @(posedge CLK) #(STB) RST = 1'b1;
    @(posedge CLK) #(STB) RST = 1'b0;
end

initial begin
    forever
        @(posedge CLK) #(STB) -> eCLK;
end


initial begin
    EN = 1'b0;
    @(posedge CLK);
    @(posedge CLK) #(STB) EN = 1'b1;
end


initial begin
    CNT = {32{1'b0}};
    @(posedge CLK);
    forever
        @(posedge CLK) #(STB) CNT = CNT + 1'b1;
end

endmodule