data/full_repos/permissive/143278/ivltests/pr1867161b.v
 line:13: before: ","
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr1867161b.v:13: Unsupported or unknown PLI call: $monitor\n    $monitor(a[35],, a[43]);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1867161b.v:13: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    $monitor(a[35],, a[43]);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1867161b.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #2 b = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1867161b.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #2 b = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1867161b.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #2 b = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1867161b.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #2 b = 0;\n    ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test (
  input rst
);

  reg [31:0]   a[99-1:35];
  reg [5:0]  b;

  always @(b) begin
    a[35 + (b<<3)] <= #1 a[35 + (b<<3)] + 32'd1;
  end

  initial begin
    $monitor(a[35],, a[43]);
    a[35] = 32'd0;
    a[43] = 32'd8;
    b = 0;
    #2 b = 1;
    #2 b = 0;
    #2 b = 1;
    #2 b = 0;
  end
endmodule
module test (
  input rst
);


  reg [31:0]   a[99-1:35];
  reg [5:0]  b;

  always @(b) begin
    a[35 + (b<<3)] <= #1 a[35 + (b<<3)] + 32'd1;
  end

  initial begin
    $monitor(a[35],, a[43]);
    a[35] = 32'd0;
    a[43] = 32'd8;
    b = 0;
    #2 b = 1;
    #2 b = 0;
    #2 b = 1;
    #2 b = 0;
  end
endmodule