data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v
 line:251: before: ","
1: b'%Warning-LITENDIAN: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:172: Little bit endian vector: MSB < LSB of bit range: 0:7\nwire  [0:7] SPCD;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:173: Cannot find file containing module: \'SPCHIP_ROM\'\nSPCHIP_ROM spchip( ~VCLKx8, SPCA, SPCD, DLCL,DLAD,DLDT,DLEN );\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219228794/src,data/full_repos/permissive/219228794/SPCHIP_ROM\n             data/full_repos/permissive/219228794/src,data/full_repos/permissive/219228794/SPCHIP_ROM.v\n             data/full_repos/permissive/219228794/src,data/full_repos/permissive/219228794/SPCHIP_ROM.sv\n             SPCHIP_ROM\n             SPCHIP_ROM.v\n             SPCHIP_ROM.sv\n             obj_dir/SPCHIP_ROM\n             obj_dir/SPCHIP_ROM.v\n             obj_dir/SPCHIP_ROM.sv\n%Warning-WIDTH: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:191: Operator GTE expects 8 bits on the LHS, but LHS\'s VARREF \'sano\' generates 6 bits.\n                                                                               : ... In instance VIDEO.spr\n    if (sano >= 8\'h30) phase <= 0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:236: Operator ADD expects 9 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                               : ... In instance VIDEO.spr\nwire [8:0] wpx = px+xcnt[3:0];\n                   ^\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:247: Cannot find file containing module: \'SPCLUT_ROM\'\nSPCLUT_ROM spclut(VCLKx8, pix, opix, DLCL,DLAD,DLDT,DLEN );\n^~~~~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:258: Cannot find file containing module: \'LineBuf\'\nLineBuf lbuf(VCLKx8,lbwe & (lbdt!=0),lbad,lbdt, VCLKx8,(radr0==radr1),radr0,ispt);\n^~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:72: Cannot find file containing module: \'VRAM2048\'\nVRAM2048 cram( CPUCL, CPUAD[10:0], CS_CRAM, CPUWR, CPUWD, OD_CRAM, VCLKx4, BGVA, BGCR ); \n^~~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:73: Cannot find file containing module: \'VRAM2048\'\nVRAM2048 vram( CPUCL, CPUAD[10:0], CS_VRAM, CPUWR, CPUWD, OD_VRAM, VCLKx4, BGVA, BGVR ); \n^~~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:74: Cannot find file containing module: \'VRAM4096\'\nVRAM4096 mram( CPUCL, CPUAD[11:0], CS_MRAM, CPUWR, CPUWD, OD_MRAM,~VCLKx8, SAAD, SATD );\n^~~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:75: Cannot find file containing module: \'VRAM32\'\nVRAM32   zrm0( CPUCL, CPUAD[ 4:0], CS_ZRM0, CPUWR, CPUWD, OD_ZRM0, VCLKx4, ZRMA, ZRM0 ); \n^~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:76: Cannot find file containing module: \'VRAM32\'\nVRAM32   zrm1( CPUCL, CPUAD[ 4:0], CS_ZRM1, CPUWR, CPUWD, OD_ZRM1, VCLKx4, ZRMA, ZRM1 ); \n^~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:92: Little bit endian vector: MSB < LSB of bit range: 0:7\nwire  [0:7] BGCD;\n      ^\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:93: Cannot find file containing module: \'BGCHIP_ROM\'\nBGCHIP_ROM bgchip( VCLKx2, BGCA, BGCD, DLCL,DLAD,DLDT,DLEN );\n^~~~~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:97: Cannot find file containing module: \'BGCLUT_ROM\'\nBGCLUT_ROM bgclut( ~VCLK, BGCT, BGPT, DLCL,DLAD,DLDT,DLEN );\n^~~~~~~~~~\n%Error: data/full_repos/permissive/219228794/src/GreenBeret_VIDEO.v:117: Cannot find file containing module: \'PALET_ROM\'\nPALET_ROM  palet( VCLK, PALIN, PALET, DLCL,DLAD,DLDT,DLEN );\n^~~~~~~~~\n%Error: Exiting due to 11 error(s), 4 warning(s)\n'
module VIDEO
(
	input				VCLKx8,
	input				VCLKx4,
	input				VCLKx2,
	input				VCLK,

	input  [8:0]	HP,
	input	 [8:0]	VP,

	input				PALD,
	input				CPUD,

	output			PCLK,
	output [11:0]	POUT,

	input				CPUCL,
	input				CPUMX,
	input	 [15:0]	CPUAD,
	input				CPUWR,
	input	  [7:0]	CPUWD,
	output			CPUDV,
	output  [7:0]	CPURD,
	

	input				DLCL,
	input  [17:0]  DLAD,
	input   [7:0]	DLDT,
	input				DLEN
);


wire				CS_CRAM = ( CPUAD[15:11] ==  5'b1100_0              ) & CPUMX;
wire				CS_VRAM = ( CPUAD[15:11] ==  5'b1100_1              ) & CPUMX;
wire				CS_MRAM = ( CPUAD[15:12] ==  4'b1101                ) & CPUMX;
wire				CS_ZRM0 = ( CPUAD[15: 5] == 11'b1110_0000_000       ) & CPUMX;
wire				CS_ZRM1 = ( CPUAD[15: 5] == 11'b1110_0000_001       ) & CPUMX;
wire				CS_SPRB = ( CPUAD[15: 0] == 16'b1110_0000_0100_0011 ) & CPUMX;

wire  [7:0]		OD_CRAM, OD_VRAM;
wire  [7:0]		OD_MRAM;
wire  [7:0]		OD_ZRM0, OD_ZRM1;

assign CPUDV = CS_CRAM | CS_VRAM | CS_MRAM | CS_ZRM0 | CS_ZRM1 ;

assign CPURD = CS_CRAM ? OD_CRAM :
					CS_VRAM ? OD_VRAM :
					CS_MRAM ? OD_MRAM :
					CS_ZRM0 ? OD_ZRM0 :
					CS_ZRM1 ? OD_ZRM1 :
					8'h0;


wire [10:0]	BGVA;
wire  [7:0]	BGCR, BGVR;

reg			SPRB;
wire  [7:0] SATA;
wire  [7:0] SATD;
wire [11:0] SAAD = {3'b000,SPRB,SATA};
always @( posedge CPUCL ) if ( CS_SPRB & CPUWR ) SPRB <= ~CPUWD[3];

wire  [4:0] ZRMA;
wire  [7:0] ZRM0, ZRM1;
wire [15:0] ZRMD = {ZRM1,ZRM0};

VRAM2048 cram( CPUCL, CPUAD[10:0], CS_CRAM, CPUWR, CPUWD, OD_CRAM, VCLKx4, BGVA, BGCR ); 
VRAM2048 vram( CPUCL, CPUAD[10:0], CS_VRAM, CPUWR, CPUWD, OD_VRAM, VCLKx4, BGVA, BGVR ); 
VRAM4096 mram( CPUCL, CPUAD[11:0], CS_MRAM, CPUWR, CPUWD, OD_MRAM,~VCLKx8, SAAD, SATD );
VRAM32   zrm0( CPUCL, CPUAD[ 4:0], CS_ZRM0, CPUWR, CPUWD, OD_ZRM0, VCLKx4, ZRMA, ZRM0 ); 
VRAM32   zrm1( CPUCL, CPUAD[ 4:0], CS_ZRM1, CPUWR, CPUWD, OD_ZRM1, VCLKx4, ZRMA, ZRM1 ); 



wire  [8:0] BGVP = VP+9'd16;
wire  [8:0] BGHP = HP+9'd8+(ZRMD[8:0]);

assign		ZRMA = BGVP[7:3];
assign		BGVA = {BGVP[7:3],BGHP[8:3]};
wire  [8:0] BGCH = {BGCR[6],BGVR};
wire  [3:0] BGCL = BGCR[3:0];
wire  [1:0] BGFL = BGCR[5:4];

wire  [2:0] BGHH = BGHP[2:0]^{3{BGFL[0]}};
wire  [2:0] BGVV = BGVP[2:0]^{3{BGFL[1]}};
wire [13:0] BGCA = {BGCH,BGVV[2:0],BGHH[2:1]};
wire  [0:7] BGCD;
BGCHIP_ROM	bgchip( VCLKx2, BGCA, BGCD, DLCL,DLAD,DLDT,DLEN );

wire  [7:0] BGCT = {BGCL,(BGHH[0] ? BGCD[4:7]:BGCD[0:3])};
wire  [3:0] BGPT;
BGCLUT_ROM	bgclut( ~VCLK, BGCT, BGPT, DLCL,DLAD,DLDT,DLEN );

reg			BGHI;
always @( negedge VCLK ) BGHI <= ~BGCR[7];



wire [8:0]	SPHP = HP+9'd9;
wire [8:0]	SPVP = VP+9'd18;
wire [3:0]  SPPT;
SPRRENDER	spr( VCLKx8,VCLK, SPHP,SPVP,SATA,SATD, SPPT, DLCL,DLAD,DLDT,DLEN );



wire [4:0] COLMIX = (BGHI & (|BGPT)) ? {1'b1,BGPT} : (|SPPT) ? {1'b0,SPPT} : {1'b1,BGPT}; 



wire [4:0] PALIN = PALD ? VP[6:2] : COLMIX;
wire [7:0] PALET;
PALET_ROM  palet( VCLK, PALIN, PALET, DLCL,DLAD,DLDT,DLEN );
wire [7:0] PALOT = PALD ? ( (|VP[8:7]) ? 8'h0 : PALET ) : PALET;



assign PCLK = ~VCLK;
assign POUT = {PALOT[7:6],2'b00,PALOT[5:3],1'b0,PALOT[2:0],1'b0}; 

endmodule
module VIDEO
(
	input				VCLKx8,
	input				VCLKx4,
	input				VCLKx2,
	input				VCLK,

	input  [8:0]	HP,
	input	 [8:0]	VP,

	input				PALD,
	input				CPUD,

	output			PCLK,
	output [11:0]	POUT,

	input				CPUCL,
	input				CPUMX,
	input	 [15:0]	CPUAD,
	input				CPUWR,
	input	  [7:0]	CPUWD,
	output			CPUDV,
	output  [7:0]	CPURD,
	

	input				DLCL,
	input  [17:0]  DLAD,
	input   [7:0]	DLDT,
	input				DLEN
);



wire				CS_CRAM = ( CPUAD[15:11] ==  5'b1100_0              ) & CPUMX;
wire				CS_VRAM = ( CPUAD[15:11] ==  5'b1100_1              ) & CPUMX;
wire				CS_MRAM = ( CPUAD[15:12] ==  4'b1101                ) & CPUMX;
wire				CS_ZRM0 = ( CPUAD[15: 5] == 11'b1110_0000_000       ) & CPUMX;
wire				CS_ZRM1 = ( CPUAD[15: 5] == 11'b1110_0000_001       ) & CPUMX;
wire				CS_SPRB = ( CPUAD[15: 0] == 16'b1110_0000_0100_0011 ) & CPUMX;

wire  [7:0]		OD_CRAM, OD_VRAM;
wire  [7:0]		OD_MRAM;
wire  [7:0]		OD_ZRM0, OD_ZRM1;

assign CPUDV = CS_CRAM | CS_VRAM | CS_MRAM | CS_ZRM0 | CS_ZRM1 ;

assign CPURD = CS_CRAM ? OD_CRAM :
					CS_VRAM ? OD_VRAM :
					CS_MRAM ? OD_MRAM :
					CS_ZRM0 ? OD_ZRM0 :
					CS_ZRM1 ? OD_ZRM1 :
					8'h0;


wire [10:0]	BGVA;
wire  [7:0]	BGCR, BGVR;

reg			SPRB;
wire  [7:0] SATA;
wire  [7:0] SATD;
wire [11:0] SAAD = {3'b000,SPRB,SATA};
always @( posedge CPUCL ) if ( CS_SPRB & CPUWR ) SPRB <= ~CPUWD[3];

wire  [4:0] ZRMA;
wire  [7:0] ZRM0, ZRM1;
wire [15:0] ZRMD = {ZRM1,ZRM0};

VRAM2048 cram( CPUCL, CPUAD[10:0], CS_CRAM, CPUWR, CPUWD, OD_CRAM, VCLKx4, BGVA, BGCR ); 
VRAM2048 vram( CPUCL, CPUAD[10:0], CS_VRAM, CPUWR, CPUWD, OD_VRAM, VCLKx4, BGVA, BGVR ); 
VRAM4096 mram( CPUCL, CPUAD[11:0], CS_MRAM, CPUWR, CPUWD, OD_MRAM,~VCLKx8, SAAD, SATD );
VRAM32   zrm0( CPUCL, CPUAD[ 4:0], CS_ZRM0, CPUWR, CPUWD, OD_ZRM0, VCLKx4, ZRMA, ZRM0 ); 
VRAM32   zrm1( CPUCL, CPUAD[ 4:0], CS_ZRM1, CPUWR, CPUWD, OD_ZRM1, VCLKx4, ZRMA, ZRM1 ); 



wire  [8:0] BGVP = VP+9'd16;
wire  [8:0] BGHP = HP+9'd8+(ZRMD[8:0]);

assign		ZRMA = BGVP[7:3];
assign		BGVA = {BGVP[7:3],BGHP[8:3]};
wire  [8:0] BGCH = {BGCR[6],BGVR};
wire  [3:0] BGCL = BGCR[3:0];
wire  [1:0] BGFL = BGCR[5:4];

wire  [2:0] BGHH = BGHP[2:0]^{3{BGFL[0]}};
wire  [2:0] BGVV = BGVP[2:0]^{3{BGFL[1]}};
wire [13:0] BGCA = {BGCH,BGVV[2:0],BGHH[2:1]};
wire  [0:7] BGCD;
BGCHIP_ROM	bgchip( VCLKx2, BGCA, BGCD, DLCL,DLAD,DLDT,DLEN );

wire  [7:0] BGCT = {BGCL,(BGHH[0] ? BGCD[4:7]:BGCD[0:3])};
wire  [3:0] BGPT;
BGCLUT_ROM	bgclut( ~VCLK, BGCT, BGPT, DLCL,DLAD,DLDT,DLEN );

reg			BGHI;
always @( negedge VCLK ) BGHI <= ~BGCR[7];



wire [8:0]	SPHP = HP+9'd9;
wire [8:0]	SPVP = VP+9'd18;
wire [3:0]  SPPT;
SPRRENDER	spr( VCLKx8,VCLK, SPHP,SPVP,SATA,SATD, SPPT, DLCL,DLAD,DLDT,DLEN );



wire [4:0] COLMIX = (BGHI & (|BGPT)) ? {1'b1,BGPT} : (|SPPT) ? {1'b0,SPPT} : {1'b1,BGPT}; 



wire [4:0] PALIN = PALD ? VP[6:2] : COLMIX;
wire [7:0] PALET;
PALET_ROM  palet( VCLK, PALIN, PALET, DLCL,DLAD,DLDT,DLEN );
wire [7:0] PALOT = PALD ? ( (|VP[8:7]) ? 8'h0 : PALET ) : PALET;



assign PCLK = ~VCLK;
assign POUT = {PALOT[7:6],2'b00,PALOT[5:3],1'b0,PALOT[2:0],1'b0}; 

endmodule