data/full_repos/permissive/125531440/core/src/main/verilog/loopback/async_fifo_fwft.v
1: b'%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/async_fifo_fwft.v:69: Cannot find include file: functions.vh\n`include "functions.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/functions.vh\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/functions.vh.v\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/functions.vh.sv\n             functions.vh\n             functions.vh.v\n             functions.vh.sv\n             obj_dir/functions.vh\n             obj_dir/functions.vh.v\n             obj_dir/functions.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module async_fifo_fwft #(
	parameter C_WIDTH = 32,
	parameter C_DEPTH = 1024,

	parameter C_REAL_DEPTH = 2**clog2(C_DEPTH),
	parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),
	parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1)
)
(
	input RD_CLK,
	input RD_RST,
	input WR_CLK,
	input WR_RST,
	input [C_WIDTH-1:0] WR_DATA,
	input WR_EN,
	output [C_WIDTH-1:0] RD_DATA,
	input RD_EN,
	output WR_FULL,
	output RD_EMPTY
);

`include "functions.vh"

reg		[C_WIDTH-1:0]			rData=0;
reg		[C_WIDTH-1:0]			rCache=0;
reg		[1:0]					rCount=0;
reg								rFifoDataValid=0;
reg								rDataValid=0;
reg								rCacheValid=0;
wire	[C_WIDTH-1:0]			wData;
wire							wEmpty;
wire							wRen = RD_EN || (rCount < 2'd2);


assign RD_DATA = rData;
assign RD_EMPTY = !rDataValid;




async_fifo #(.C_WIDTH(C_WIDTH), .C_DEPTH(C_DEPTH)) fifo (
	.WR_CLK(WR_CLK),
	.WR_RST(WR_RST),
	.RD_CLK(RD_CLK),
	.RD_RST(RD_RST),
	.WR_EN(WR_EN),
	.WR_DATA(WR_DATA),
	.WR_FULL(WR_FULL),
	.RD_EN(wRen),
	.RD_DATA(wData),
	.RD_EMPTY(wEmpty)
);

always @ (posedge RD_CLK) begin
	if (RD_RST) begin
		rCount <= #1 0;
		rDataValid <= #1 0;
		rCacheValid <= #1 0;
		rFifoDataValid <= #1 0;
	end
	else begin

		rCount <= #1 rCount + (wRen & !wEmpty) - (!RD_EMPTY & RD_EN);


		rFifoDataValid <= #1 (wRen & !wEmpty);


		if (rFifoDataValid) begin
			if (RD_EN | !rDataValid) begin
				rData <= #1 wData;
				rDataValid <= #1 1'd1;
				rCacheValid <= #1 1'd0;
			end
			else begin
				rCacheValid <= #1 1'd1;
			end
			rCache  <= #1 wData;
		end
		else begin
			if (RD_EN | !rDataValid) begin
				rData <= #1 rCache;
				rDataValid <= #1 rCacheValid;
				rCacheValid <= #1 1'd0;
			end
		end
	end
end
 
endmodule
module async_fifo_fwft #(
	parameter C_WIDTH = 32,
	parameter C_DEPTH = 1024,

	parameter C_REAL_DEPTH = 2**clog2(C_DEPTH),
	parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),
	parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1)
)
(
	input RD_CLK,
	input RD_RST,
	input WR_CLK,
	input WR_RST,
	input [C_WIDTH-1:0] WR_DATA,
	input WR_EN,
	output [C_WIDTH-1:0] RD_DATA,
	input RD_EN,
	output WR_FULL,
	output RD_EMPTY
);


`include "functions.vh"

reg		[C_WIDTH-1:0]			rData=0;
reg		[C_WIDTH-1:0]			rCache=0;
reg		[1:0]					rCount=0;
reg								rFifoDataValid=0;
reg								rDataValid=0;
reg								rCacheValid=0;
wire	[C_WIDTH-1:0]			wData;
wire							wEmpty;
wire							wRen = RD_EN || (rCount < 2'd2);


assign RD_DATA = rData;
assign RD_EMPTY = !rDataValid;




async_fifo #(.C_WIDTH(C_WIDTH), .C_DEPTH(C_DEPTH)) fifo (
	.WR_CLK(WR_CLK),
	.WR_RST(WR_RST),
	.RD_CLK(RD_CLK),
	.RD_RST(RD_RST),
	.WR_EN(WR_EN),
	.WR_DATA(WR_DATA),
	.WR_FULL(WR_FULL),
	.RD_EN(wRen),
	.RD_DATA(wData),
	.RD_EMPTY(wEmpty)
);

always @ (posedge RD_CLK) begin
	if (RD_RST) begin
		rCount <= #1 0;
		rDataValid <= #1 0;
		rCacheValid <= #1 0;
		rFifoDataValid <= #1 0;
	end
	else begin

		rCount <= #1 rCount + (wRen & !wEmpty) - (!RD_EMPTY & RD_EN);


		rFifoDataValid <= #1 (wRen & !wEmpty);


		if (rFifoDataValid) begin
			if (RD_EN | !rDataValid) begin
				rData <= #1 wData;
				rDataValid <= #1 1'd1;
				rCacheValid <= #1 1'd0;
			end
			else begin
				rCacheValid <= #1 1'd1;
			end
			rCache  <= #1 wData;
		end
		else begin
			if (RD_EN | !rDataValid) begin
				rData <= #1 rCache;
				rDataValid <= #1 rCacheValid;
				rCacheValid <= #1 1'd0;
			end
		end
	end
end
 
endmodule