data/full_repos/permissive/169496369/data_memory.v
data/verilator_xmls/90fd936d-a91c-47fb-ab72-05bc9c79e499.xml
module data_memory(clk, memread, memwrite, read_address, write_address, data_wr, data_re);
    input clk, memread, memwrite;
    input [5:0]read_address, write_address;
    input [31:0]data_wr;

    
    output logic [31:0]data_re;
        
    logic [7:0]data_mem[63:0];
    


    initial
    begin
        $readmemh("data.mem", data_mem, 0, 63);
    end
    
    always_comb
    begin
        if(memread && !memwrite)
            begin










                    data_re = {data_mem[read_address], data_mem[read_address + 6'd1], data_mem[read_address + 6'd2], data_mem[read_address + 6'd3]};
            end
        else
            data_re = 32'd0;
    end
    
    always_ff@(posedge clk)
    begin
        if(memwrite && !memread)
        begin










                {data_mem[write_address], data_mem[write_address + 6'd1], data_mem[write_address + 6'd2], data_mem[write_address + 6'd3]} <= data_wr;
        end
    end
endmodule
module data_memory(clk, memread, memwrite, read_address, write_address, data_wr, data_re);

    input clk, memread, memwrite;
    input [5:0]read_address, write_address;
    input [31:0]data_wr;

    
    output logic [31:0]data_re;
        
    logic [7:0]data_mem[63:0];
    


    initial
    begin
        $readmemh("data.mem", data_mem, 0, 63);
    end
    
    always_comb
    begin
        if(memread && !memwrite)
            begin










                    data_re = {data_mem[read_address], data_mem[read_address + 6'd1], data_mem[read_address + 6'd2], data_mem[read_address + 6'd3]};
            end
        else
            data_re = 32'd0;
    end
    
    always_ff@(posedge clk)
    begin
        if(memwrite && !memread)
        begin










                {data_mem[write_address], data_mem[write_address + 6'd1], data_mem[write_address + 6'd2], data_mem[write_address + 6'd3]} <= data_wr;
        end
    end
endmodule