data/full_repos/permissive/160895047/ALU.v
1: b"%Error: data/full_repos/permissive/160895047/ALU.v:17: Input/output/inout does not appear in port list: 'CLOCK'\ninput CLOCK;\n      ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module ALU(
	Control,
	A,
	B,
	Result,
	Zero
);
input CLOCK;
input [2:0] Control;
input [31:0] A;
input [31:0] B;
output [31:0] Result;
output Zero;

wire CLOCK;
wire [2:0] Control;
wire [31:0] A;
wire [31:0] B;
reg [31:0] Result;
wire Zero;

assign Zero = (Result == 0);



always @*
begin
	case (Control)
		`ALU_ADD: Result = A + B;
		`ALU_SUBTRACT: Result = A - B;
		`ALU_AND: Result = A & B;
		`ALU_OR: Result = A | B;
		`ALU_SLT: Result = (A < B) ? 1 : 0;
		`ALU_SHIFT_LEFT: Result = A << B;
		default: $display("Unknown Control Signal: %b", Control);
	endcase

end
endmodule
module ALU(
	Control,
	A,
	B,
	Result,
	Zero
);

input CLOCK;
input [2:0] Control;
input [31:0] A;
input [31:0] B;
output [31:0] Result;
output Zero;

wire CLOCK;
wire [2:0] Control;
wire [31:0] A;
wire [31:0] B;
reg [31:0] Result;
wire Zero;

assign Zero = (Result == 0);



always @*
begin
	case (Control)
		`ALU_ADD: Result = A + B;
		`ALU_SUBTRACT: Result = A - B;
		`ALU_AND: Result = A & B;
		`ALU_OR: Result = A | B;
		`ALU_SLT: Result = (A < B) ? 1 : 0;
		`ALU_SHIFT_LEFT: Result = A << B;
		default: $display("Unknown Control Signal: %b", Control);
	endcase

end
endmodule