data/full_repos/permissive/181415525/danmaku_de2/image_generator/simple.v
 line:46 column:52: Illegal character "'"
1: b'%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/image_generator/simple.v:33: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'pause\' generates 1 bits.\n                                                                                            : ... In instance simple\n    counter <= counter + pause;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/image_generator/simple.v:42: Operator EQ expects 12 bits on the RHS, but RHS\'s CONST \'11\'h190\' generates 11 bits.\n                                                                                            : ... In instance simple\n    (hcnt == 11\'d400 || vcnt == 11\'d300) ? 32\'h00_00_00_ff : 32\'h00_00_00_00\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/image_generator/simple.v:42: Operator EQ expects 12 bits on the RHS, but RHS\'s CONST \'11\'h12c\' generates 11 bits.\n                                                                                            : ... In instance simple\n    (hcnt == 11\'d400 || vcnt == 11\'d300) ? 32\'h00_00_00_ff : 32\'h00_00_00_00\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/image_generator/simple.v:44: Operator EQ expects 12 bits on the RHS, but RHS\'s CONST \'11\'h31f\' generates 11 bits.\n                                                                                            : ... In instance simple\n    (hcnt == 11\'d799 || vcnt == 11\'d599) ? 32\'h00_00_00_ff : 32\'h00_00_00_00\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/image_generator/simple.v:44: Operator EQ expects 12 bits on the RHS, but RHS\'s CONST \'11\'h257\' generates 11 bits.\n                                                                                            : ... In instance simple\n    (hcnt == 11\'d799 || vcnt == 11\'d599) ? 32\'h00_00_00_ff : 32\'h00_00_00_00\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/image_generator/simple.v:46: Operator LT expects 12 bits on the RHS, but RHS\'s CONST \'11\'h258\' generates 11 bits.\n                                                                                            : ... In instance simple\n    (hcnt < 11\'d600 && hcnt > 11\'d200 && vcnt < 11\'d 450 && vcnt > 11\'d150) ? 32\'h00_00_00_ff: 32\'h00_00_00_00\n          ^\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/image_generator/simple.v:46: Operator GT expects 12 bits on the RHS, but RHS\'s CONST \'11\'hc8\' generates 11 bits.\n                                                                                            : ... In instance simple\n    (hcnt < 11\'d600 && hcnt > 11\'d200 && vcnt < 11\'d 450 && vcnt > 11\'d150) ? 32\'h00_00_00_ff: 32\'h00_00_00_00\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/image_generator/simple.v:46: Operator LT expects 12 bits on the RHS, but RHS\'s CONST \'11\'h1c2\' generates 11 bits.\n                                                                                            : ... In instance simple\n    (hcnt < 11\'d600 && hcnt > 11\'d200 && vcnt < 11\'d 450 && vcnt > 11\'d150) ? 32\'h00_00_00_ff: 32\'h00_00_00_00\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/181415525/danmaku_de2/image_generator/simple.v:46: Operator GT expects 12 bits on the RHS, but RHS\'s CONST \'11\'h96\' generates 11 bits.\n                                                                                            : ... In instance simple\n    (hcnt < 11\'d600 && hcnt > 11\'d200 && vcnt < 11\'d 450 && vcnt > 11\'d150) ? 32\'h00_00_00_ff: 32\'h00_00_00_00\n                                                                 ^\n%Error: Exiting due to 9 warning(s)\n'
module simple(
  input wire pxlClk,
  input wire rst,
  input wire[11:0] hcnt,
  input wire[11:0] vcnt,
  input wire[11:0] hsize,
  input wire[11:0] vsize,
  
  output wire[7:0] pixel_r_out,
  output wire[7:0] pixel_g_out,
  output wire[7:0] pixel_b_out,
  output wire[7:0] pixel_a_out,
  
  input wire pause
);

reg[32:0] counter;
wire[1:0] picNum;
wire[7:0] realAlpha;

always @(posedge pxlClk or negedge rst) begin
  if(!rst) begin
    counter <= 0;
  end else begin
    counter <= counter + pause;
  end
end

assign picNum = counter[28:27];

assign pixel_a_out = realAlpha;
assign {pixel_r_out, pixel_g_out, pixel_b_out, realAlpha} = 
  (picNum == 2'd0)?(
    (hcnt == 11'd400 || vcnt == 11'd300) ? 32'h00_00_00_ff : 32'h00_00_00_00
  ):((picNum == 2'd1)?(
    (hcnt == 11'd799 || vcnt == 11'd599) ? 32'h00_00_00_ff : 32'h00_00_00_00
  ):((picNum == 2'd2)?(
    (hcnt < 11'd600 && hcnt > 11'd200 && vcnt < 11'd 450 && vcnt > 11'd150) ? 32'h00_00_00_ff: 32'h00_00_00_00
  ):(
    ((hcnt[4] == 0 && vcnt[4] == 0) || (hcnt[4] == 1 && vcnt[4] == 1)) ? 32'h00_00_00_ff: 32'h00_00_00_00
  )));
  

endmodule
module simple(
  input wire pxlClk,
  input wire rst,
  input wire[11:0] hcnt,
  input wire[11:0] vcnt,
  input wire[11:0] hsize,
  input wire[11:0] vsize,
  
  output wire[7:0] pixel_r_out,
  output wire[7:0] pixel_g_out,
  output wire[7:0] pixel_b_out,
  output wire[7:0] pixel_a_out,
  
  input wire pause
);


reg[32:0] counter;
wire[1:0] picNum;
wire[7:0] realAlpha;

always @(posedge pxlClk or negedge rst) begin
  if(!rst) begin
    counter <= 0;
  end else begin
    counter <= counter + pause;
  end
end

assign picNum = counter[28:27];

assign pixel_a_out = realAlpha;
assign {pixel_r_out, pixel_g_out, pixel_b_out, realAlpha} = 
  (picNum == 2'd0)?(
    (hcnt == 11'd400 || vcnt == 11'd300) ? 32'h00_00_00_ff : 32'h00_00_00_00
  ):((picNum == 2'd1)?(
    (hcnt == 11'd799 || vcnt == 11'd599) ? 32'h00_00_00_ff : 32'h00_00_00_00
  ):((picNum == 2'd2)?(
    (hcnt < 11'd600 && hcnt > 11'd200 && vcnt < 11'd 450 && vcnt > 11'd150) ? 32'h00_00_00_ff: 32'h00_00_00_00
  ):(
    ((hcnt[4] == 0 && vcnt[4] == 0) || (hcnt[4] == 1 && vcnt[4] == 1)) ? 32'h00_00_00_ff: 32'h00_00_00_00
  )));
  

endmodule