data/full_repos/permissive/13201424/vlog/eth_top.v
1: b"%Error: data/full_repos/permissive/13201424/vlog/eth_top.v:51: Cannot find file containing module: 'IBUFG'\n IBUFG eth_rx_clk_ibufg (\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/13201424/vlog,data/full_repos/permissive/13201424/IBUFG\n             data/full_repos/permissive/13201424/vlog,data/full_repos/permissive/13201424/IBUFG.v\n             data/full_repos/permissive/13201424/vlog,data/full_repos/permissive/13201424/IBUFG.sv\n             IBUFG\n             IBUFG.v\n             IBUFG.sv\n             obj_dir/IBUFG\n             obj_dir/IBUFG.v\n             obj_dir/IBUFG.sv\n%Error: data/full_repos/permissive/13201424/vlog/eth_top.v:67: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic'\n                                                             : ... In instance eth_top\n wire rx_rst = rx_rst[0];\n                     ^\n%Error: data/full_repos/permissive/13201424/vlog/eth_top.v:71: Cannot find file containing module: 'eth_mac_rx'\n eth_mac_rx eth_mac_rx_0 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/13201424/vlog/eth_top.v:86: Cannot find file containing module: 'fifo_9x2048'\n fifo_9x2048 rx_fifo (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/13201424/vlog/eth_top.v:102: Cannot find file containing module: 'eth_mac_tx'\n eth_mac_tx eth_mac_tx_0 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/13201424/vlog/eth_top.v:119: Cannot find file containing module: 'fifo_9x2048'\n fifo_9x2048 tx_fifo (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/13201424/vlog/eth_top.v:132: Cannot find file containing module: 'eth_mcb_if'\n eth_mcb_if eth_mcb_if_0 (\n ^~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module eth_top (

	input clk,
	input rst,
	
	input eth_rx_clk_in,
	input [7:0] eth_rx_d_in,
	input eth_rx_err_in,
	input eth_rx_dv_in,
	
	output eth_gtx_clk_out,
	output [7:0] eth_tx_d_out,
	output eth_tx_en_out,
	output eth_tx_err_out,
	
	output mcb_cmd_en_out,
	output [2:0] mcb_cmd_instr_out,
	output [5:0] mcb_cmd_bl_out,
	output [29:0] mcb_cmd_byte_addr_out,
	input mcb_cmd_empty_in,
	input mcb_cmd_full_in,
	
	output mcb_wr_en_out,
	output [7:0] mcb_wr_mask_out,
	output [63:0] mcb_wr_data_out,
	input mcb_wr_full_in,
	input mcb_wr_empty_in,
	input mcb_wr_error_in,
	input mcb_wr_underrun_in,
	input [6:0] mcb_wr_count_in,
	
	output mcb_rd_en_out,
	input [63:0] mcb_rd_data_in,
	input mcb_rd_full_in,
	input mcb_rd_empty_in,
	input mcb_rd_error_in,
	input mcb_rd_overflow_in,
	input [6:0] mcb_rd_count_in
);
	

	wire rx_clk;
	`ifndef SIMULATION
	IBUFG eth_rx_clk_ibufg (
		.I(eth_rx_clk_in),
		.O(rx_clk)
	);
	`else
	assign rx_clk = eth_rx_clk_in;
	`endif


	assign eth_gtx_clk_out = clk;
	


	reg [1:0] rx_rst_r;
	always @ (posedge rx_clk)
		rx_rst_r <= (rst) ? 2'b00 : {rst, rx_rst_r[1]};
	wire rx_rst = rx_rst[0];
	


	eth_mac_rx eth_mac_rx_0 (
		.clk(rx_clk),
		.rst(rx_rst),
		
		.eth_rx_d_in(eth_rx_d_in),
		.eth_rx_err_in(eth_rx_err_in),
		.eth_rx_dv_in(eth_rx_dv_in),
		
		.wr_en_out(mac_wr_en),
		.wr_d_out(mac_wr_d),
		.wr_full_in(mac_full)
	);
	


	fifo_9x2048 rx_fifo (
		.clk(clk),
		.rst(rst),
		
		.rd_en(mcb_rd_en),
		.dout(mcb_rd_d),
		.empty(mcb_rd_empty),
		
		.wr_en(mac_wr_en),
		.din(mac_wr_d),
		.full(mac_wr_full)
	);
	
	wire tx_start;
	

	eth_mac_tx eth_mac_tx_0 (
		.clk(clk),
		.rst(rst),
		
		.start_in(tx_start),
		
		.eth_tx_d_out(eth_tx_d_out),
		.eth_tx_en_out(eth_tx_en_out),
		.eth_tx_err_out(eth_rx_err_out),
		
		.rd_en_out(mac_rd_en),
		.rd_d_in(mac_rd_d),
		.rd_empty_in(mac_rd_empty)
	);
	


	fifo_9x2048 tx_fifo (
		.clk(clk),
		.rst(rst),
		
		.rd_en(mac_rd_en),
		.dout(mac_rd_d),
		.empty(mac_rd_empty),
		
		.wr_en(mcb_wr_en),
		.din(mcb_wr_d),
		.full(mcb_wr_full)
	);

	eth_mcb_if eth_mcb_if_0 (
		.clk(clk),
		.rst(rst),

		.rd_en_out(mcb_rd_en),
		.rd_empty_in(mcb_rd_empty),
		.rd_addr_out(mcb_rd_addr),
		.rd_d_in(mcb_rd_d),
		
		.wr_start(tx_start),
		.wr_en_out(mcb_wr_en),
		.wr_d_out(mcb_wr_d),
		.wr_full_in(mcb_wr_full),
		
		.mcb_cmd_en_out(mcb_cmd_en_out),
		.mcb_cmd_instr_out(mcb_cmd_instr_out),
		.mcb_cmd_bl_out(mcb_cmd_bl_out),
		.mcb_cmd_byte_addr_out(mcb_cmd_byte_addr_out),
		.mcb_cmd_empty_in(mcb_cmd_empty_in),
		.mcb_cmd_full_in(mcb_cmd_full_in),
		
		.mcb_wr_en_out(mcb_wr_en_out),
		.mcb_wr_mask_out(mcb_wr_mask_out),
		.mcb_wr_data_out(mcb_wr_data_out),
		.mcb_wr_full_in(mcb_wr_full_in),
		.mcb_wr_empty_in(mcb_wr_empty_in),
		.mcb_wr_error_in(mcb_wr_error_in),
		.mcb_wr_underrun_in(mcb_wr_underrun_in),
		.mcb_wr_count_in(mcb_wr_count_in),
		
		.mcb_rd_en_out(mcb_rd_en_out),
		.mcb_rd_data_in(mcb_rd_data_in),
		.mcb_rd_full_in(mcb_rd_full_in),
		.mcb_rd_empty_in(mcb_rd_empty_in),
		.mcb_rd_error_in(mcb_rd_error_in),
		.mcb_rd_overflow_in(mcb_rd_overflow_in),
		.mcb_rd_count_in(mcb_rd_count_in)
	);
	
endmodule
module eth_top (

	input clk,
	input rst,
	
	input eth_rx_clk_in,
	input [7:0] eth_rx_d_in,
	input eth_rx_err_in,
	input eth_rx_dv_in,
	
	output eth_gtx_clk_out,
	output [7:0] eth_tx_d_out,
	output eth_tx_en_out,
	output eth_tx_err_out,
	
	output mcb_cmd_en_out,
	output [2:0] mcb_cmd_instr_out,
	output [5:0] mcb_cmd_bl_out,
	output [29:0] mcb_cmd_byte_addr_out,
	input mcb_cmd_empty_in,
	input mcb_cmd_full_in,
	
	output mcb_wr_en_out,
	output [7:0] mcb_wr_mask_out,
	output [63:0] mcb_wr_data_out,
	input mcb_wr_full_in,
	input mcb_wr_empty_in,
	input mcb_wr_error_in,
	input mcb_wr_underrun_in,
	input [6:0] mcb_wr_count_in,
	
	output mcb_rd_en_out,
	input [63:0] mcb_rd_data_in,
	input mcb_rd_full_in,
	input mcb_rd_empty_in,
	input mcb_rd_error_in,
	input mcb_rd_overflow_in,
	input [6:0] mcb_rd_count_in
);

	

	wire rx_clk;
	`ifndef SIMULATION
	IBUFG eth_rx_clk_ibufg (
		.I(eth_rx_clk_in),
		.O(rx_clk)
	);
	`else
	assign rx_clk = eth_rx_clk_in;
	`endif


	assign eth_gtx_clk_out = clk;
	


	reg [1:0] rx_rst_r;
	always @ (posedge rx_clk)
		rx_rst_r <= (rst) ? 2'b00 : {rst, rx_rst_r[1]};
	wire rx_rst = rx_rst[0];
	


	eth_mac_rx eth_mac_rx_0 (
		.clk(rx_clk),
		.rst(rx_rst),
		
		.eth_rx_d_in(eth_rx_d_in),
		.eth_rx_err_in(eth_rx_err_in),
		.eth_rx_dv_in(eth_rx_dv_in),
		
		.wr_en_out(mac_wr_en),
		.wr_d_out(mac_wr_d),
		.wr_full_in(mac_full)
	);
	


	fifo_9x2048 rx_fifo (
		.clk(clk),
		.rst(rst),
		
		.rd_en(mcb_rd_en),
		.dout(mcb_rd_d),
		.empty(mcb_rd_empty),
		
		.wr_en(mac_wr_en),
		.din(mac_wr_d),
		.full(mac_wr_full)
	);
	
	wire tx_start;
	

	eth_mac_tx eth_mac_tx_0 (
		.clk(clk),
		.rst(rst),
		
		.start_in(tx_start),
		
		.eth_tx_d_out(eth_tx_d_out),
		.eth_tx_en_out(eth_tx_en_out),
		.eth_tx_err_out(eth_rx_err_out),
		
		.rd_en_out(mac_rd_en),
		.rd_d_in(mac_rd_d),
		.rd_empty_in(mac_rd_empty)
	);
	


	fifo_9x2048 tx_fifo (
		.clk(clk),
		.rst(rst),
		
		.rd_en(mac_rd_en),
		.dout(mac_rd_d),
		.empty(mac_rd_empty),
		
		.wr_en(mcb_wr_en),
		.din(mcb_wr_d),
		.full(mcb_wr_full)
	);

	eth_mcb_if eth_mcb_if_0 (
		.clk(clk),
		.rst(rst),

		.rd_en_out(mcb_rd_en),
		.rd_empty_in(mcb_rd_empty),
		.rd_addr_out(mcb_rd_addr),
		.rd_d_in(mcb_rd_d),
		
		.wr_start(tx_start),
		.wr_en_out(mcb_wr_en),
		.wr_d_out(mcb_wr_d),
		.wr_full_in(mcb_wr_full),
		
		.mcb_cmd_en_out(mcb_cmd_en_out),
		.mcb_cmd_instr_out(mcb_cmd_instr_out),
		.mcb_cmd_bl_out(mcb_cmd_bl_out),
		.mcb_cmd_byte_addr_out(mcb_cmd_byte_addr_out),
		.mcb_cmd_empty_in(mcb_cmd_empty_in),
		.mcb_cmd_full_in(mcb_cmd_full_in),
		
		.mcb_wr_en_out(mcb_wr_en_out),
		.mcb_wr_mask_out(mcb_wr_mask_out),
		.mcb_wr_data_out(mcb_wr_data_out),
		.mcb_wr_full_in(mcb_wr_full_in),
		.mcb_wr_empty_in(mcb_wr_empty_in),
		.mcb_wr_error_in(mcb_wr_error_in),
		.mcb_wr_underrun_in(mcb_wr_underrun_in),
		.mcb_wr_count_in(mcb_wr_count_in),
		
		.mcb_rd_en_out(mcb_rd_en_out),
		.mcb_rd_data_in(mcb_rd_data_in),
		.mcb_rd_full_in(mcb_rd_full_in),
		.mcb_rd_empty_in(mcb_rd_empty_in),
		.mcb_rd_error_in(mcb_rd_error_in),
		.mcb_rd_overflow_in(mcb_rd_overflow_in),
		.mcb_rd_count_in(mcb_rd_count_in)
	);
	
endmodule