data/full_repos/permissive/174263347/crtv10/hdl/crt_scan.v
1: b'%Warning-WIDTH: data/full_repos/permissive/174263347/crtv10/hdl/crt_scan.v:74: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                             : ... In instance crt_scan\n            vreg <= 8\'b0000_0000;\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module crt_scan (clk, reset, pxclk, med_res, video_data_latch, hcnt, vcnt, href, hsync, vsync);

    input           clk, reset;
    input           pxclk;
    input           med_res;
    output          video_data_latch;
    
    output  [9:0]   hcnt;
    output  [8:0]   vcnt;
	output			href;
    output          hsync;
    output          vsync;

    reg     [9:0]   hreg;
    reg     [8:0]   vreg;
	reg				hsreg;
	reg				vsreg;

    wire            eof_frame, eof_line;
    wire            hsync_beg,   hsync_end;
    wire            vsync_beg,   vsync_end;



    assign  video_data_latch =  hcnt[0];



    assign  hcnt = hreg;
    assign  vcnt = vreg;



    assign  href = ~(hreg[8] | hreg[9]) & ~(vreg[6] | vreg[7] | vreg[8]);



    assign eof_line  = med_res ? (10'd587 == hcnt) : (10'd466 == hcnt);
    assign hsync_beg = med_res ? (10'd378 == hcnt) : (10'd327 == hcnt);
    assign hsync_end = med_res ? (10'd421 == hcnt) : (10'd361 == hcnt);

    assign eof_frame = med_res ? (9'd411 == vcnt) : (9'd261 == vcnt);
    assign vsync_beg = med_res ? (9'd233 == vcnt) : (9'd158 == vcnt);
    assign vsync_end = med_res ? (9'd242 == vcnt) : (9'd167 == vcnt);




    always @ (posedge reset or posedge clk)
        if (reset)
            hreg <= 10'b00_0000_0000;
        else if (pxclk)
           	if (eof_line)
	            	hreg <= 10'b00_0000_0000;
   			else
                    hreg <= hreg + 1;




    always @ (posedge reset or posedge clk)
        if (reset)
            vreg <= 8'b0000_0000;
        else if (pxclk)
            if (eof_line)
            	if (eof_frame)
		            	vreg <= 9'b0_0000_0000;
    			else
                        vreg <= vreg + 1;




	assign hsync = hsreg;

    always @ (posedge reset or posedge clk)
        if (reset)
            hsreg <= 1'b0;
        else if (pxclk)
            if (hsync_beg)
            	hsreg <= 1'b1;
  			else if (hsync_end)
                hsreg <= 1'b0;
        


	assign vsync = vsreg;

    always @ (posedge reset or posedge clk)
        if (reset)
            vsreg <= 1'b0;
        else if (pxclk)
            if (eof_line)
                if (vsync_beg)
                	vsreg <= 1'b1;
  			    else if (vsync_end)
                    vsreg <= 1'b0;

endmodule
module crt_scan (clk, reset, pxclk, med_res, video_data_latch, hcnt, vcnt, href, hsync, vsync);


    input           clk, reset;
    input           pxclk;
    input           med_res;
    output          video_data_latch;
    
    output  [9:0]   hcnt;
    output  [8:0]   vcnt;
	output			href;
    output          hsync;
    output          vsync;

    reg     [9:0]   hreg;
    reg     [8:0]   vreg;
	reg				hsreg;
	reg				vsreg;

    wire            eof_frame, eof_line;
    wire            hsync_beg,   hsync_end;
    wire            vsync_beg,   vsync_end;



    assign  video_data_latch =  hcnt[0];



    assign  hcnt = hreg;
    assign  vcnt = vreg;



    assign  href = ~(hreg[8] | hreg[9]) & ~(vreg[6] | vreg[7] | vreg[8]);



    assign eof_line  = med_res ? (10'd587 == hcnt) : (10'd466 == hcnt);
    assign hsync_beg = med_res ? (10'd378 == hcnt) : (10'd327 == hcnt);
    assign hsync_end = med_res ? (10'd421 == hcnt) : (10'd361 == hcnt);

    assign eof_frame = med_res ? (9'd411 == vcnt) : (9'd261 == vcnt);
    assign vsync_beg = med_res ? (9'd233 == vcnt) : (9'd158 == vcnt);
    assign vsync_end = med_res ? (9'd242 == vcnt) : (9'd167 == vcnt);




    always @ (posedge reset or posedge clk)
        if (reset)
            hreg <= 10'b00_0000_0000;
        else if (pxclk)
           	if (eof_line)
	            	hreg <= 10'b00_0000_0000;
   			else
                    hreg <= hreg + 1;




    always @ (posedge reset or posedge clk)
        if (reset)
            vreg <= 8'b0000_0000;
        else if (pxclk)
            if (eof_line)
            	if (eof_frame)
		            	vreg <= 9'b0_0000_0000;
    			else
                        vreg <= vreg + 1;




	assign hsync = hsreg;

    always @ (posedge reset or posedge clk)
        if (reset)
            hsreg <= 1'b0;
        else if (pxclk)
            if (hsync_beg)
            	hsreg <= 1'b1;
  			else if (hsync_end)
                hsreg <= 1'b0;
        


	assign vsync = vsreg;

    always @ (posedge reset or posedge clk)
        if (reset)
            vsreg <= 1'b0;
        else if (pxclk)
            if (eof_line)
                if (vsync_beg)
                	vsreg <= 1'b1;
  			    else if (vsync_end)
                    vsreg <= 1'b0;

endmodule