data/full_repos/permissive/201488448/1_verilog/03_not.v
data/verilator_xmls/c935ece8-318d-456e-87f4-e2888d3c0f17.xml
module top_module(
	input in,
	output out
);
	
	assign out = ~in;
	
endmodule
module top_module(
	input in,
	output out
);

	
	assign out = ~in;
	
endmodule