data/full_repos/permissive/214823094/tutorials/simulation/lab1.v
data/verilator_xmls/3e430267-12fb-4d21-86e2-077b36861ad7.xml
module lab1(
    input [7:0] SW,
     output [7:0] LED
    );
    
    assign LED[0] = ~SW[0];
    assign LED[1] = SW[1] & ~SW[2];
    assign LED[3] = SW[2] & SW[3];
    assign LED[2] = LED[1] | LED[3];
    
    assign LED[7:4] = SW[7:4];
    
endmodule
module lab1(
    input [7:0] SW,
     output [7:0] LED
    );

    
    assign LED[0] = ~SW[0];
    assign LED[1] = SW[1] & ~SW[2];
    assign LED[3] = SW[2] & SW[3];
    assign LED[2] = LED[1] | LED[3];
    
    assign LED[7:4] = SW[7:4];
    
endmodule