data/full_repos/permissive/123690745/IDEX.v
 line:28: before: "="
data/verilator_xmls/f28be2b4-b5df-45fb-aeb1-a7faa379bc62.xml
module IDEX(
	 input InterruptRequest,
    input clk,
	 input reset,
    input FlushE,
	 input Nullify,
    input [4:0] RsD,
    output reg[4:0] RsE  = 0,
    input [4:0] RtD,
    output reg[4:0] RtE = 0,
    input [4:0] RdD,
    output reg[4:0] RdE = 0,
    input [31:0] RD1D,
    output reg[31:0] RD1E = 0,
    input [31:0] RD2D,
    output reg[31:0] RD2E = 0,
	 input [31:0] SignImmD,
	 output reg[31:0] SignImmE,
	 input [31:0] InstrD,
	 output reg[31:0] InstrE
    );
	always @(posedge clk) begin
		if (FlushE || reset || Nullify || InterruptRequest) begin
			RsE <= 0;
			RtE <= 0;
			RdE <= 0;
			RD1E <= 0;
			RD2E <= 0;
			SignImmE <= 0;
			InstrE <= 0;
		end
		else begin
			RsE <= RsD;
			RtE <= RtD;
			RdE <= RdD;
			RD1E <= RD1D;
			RD2E <= RD2D;
			SignImmE <= SignImmD;
			InstrE <= InstrD;
		end
	end

endmodule
module IDEX(
	 input InterruptRequest,
    input clk,
	 input reset,
    input FlushE,
	 input Nullify,
    input [4:0] RsD,
    output reg[4:0] RsE  = 0,
    input [4:0] RtD,
    output reg[4:0] RtE = 0,
    input [4:0] RdD,
    output reg[4:0] RdE = 0,
    input [31:0] RD1D,
    output reg[31:0] RD1E = 0,
    input [31:0] RD2D,
    output reg[31:0] RD2E = 0,
	 input [31:0] SignImmD,
	 output reg[31:0] SignImmE,
	 input [31:0] InstrD,
	 output reg[31:0] InstrE
    );

	always @(posedge clk) begin
		if (FlushE || reset || Nullify || InterruptRequest) begin
			RsE <= 0;
			RtE <= 0;
			RdE <= 0;
			RD1E <= 0;
			RD2E <= 0;
			SignImmE <= 0;
			InstrE <= 0;
		end
		else begin
			RsE <= RsD;
			RtE <= RtD;
			RdE <= RdD;
			RD1E <= RD1D;
			RD2E <= RD2D;
			SignImmE <= SignImmD;
			InstrE <= InstrD;
		end
	end

endmodule