data/full_repos/permissive/186676986/tlc.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/186676986/tlc.v:79: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'Y2RD\' generates 2 bits.\n                                                             : ... In instance tlc\n  repeat(Y2RD) \n  ^~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/186676986/tlc.v:83: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'R2GD\' generates 2 bits.\n                                                             : ... In instance tlc\n  repeat(R2GD) \n  ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/186676986/tlc.v:91: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'Y2RD\' generates 2 bits.\n                                                             : ... In instance tlc\n  repeat(Y2RD) \n  ^~~~~~\n%Error: Exiting due to 3 warning(s)\n'
module tlc(
    input X,
    input slowclk,
    input clr,
    output reg [1:0] hwy,
    output reg [1:0] cntry
    );

parameter R=2'd0,
			 Y=2'd1,
			 G=2'd2;
			
parameter S0=3'd0,
			 S1=3'd1,
			 S2=3'd2,
			 S3=3'd3,
			 S4=3'd4;
			 
parameter Y2RD = 2'd3,
			 R2GD = 2'd2;
			 
			 
reg [2:0] state;
reg [2:0] next_state;

always@(posedge slowclk)
if(clr)
	state<=S0;
else
	state<=next_state;

always@(state)
begin	
	hwy=G;
	cntry=R;
	case(state)
	S0: ;
	S1: hwy=Y;
	S2: hwy=R;
	S3: begin
		 hwy=R;
		 cntry=G;
		 end
	S4: begin
		 hwy=R;
		 cntry=Y;
		 end
	endcase
end

always@(state or X)
begin
case(state)
S0: if(X)
		next_state=S1;
		else
		next_state=S0;
	S1: begin
		repeat(Y2RD) 
		next_state=S2;
		end
	S2: begin
		repeat(R2GD) 
		next_state=S3;
		end
	S3: if(X)
		next_state=S3;
		else
		next_state=S4;
	S4: begin 
		repeat(Y2RD) 
		next_state=S0;
		end	
		
default: next_state=S0;
endcase
end


endmodule
module tlc(
    input X,
    input slowclk,
    input clr,
    output reg [1:0] hwy,
    output reg [1:0] cntry
    );


parameter R=2'd0,
			 Y=2'd1,
			 G=2'd2;
			
parameter S0=3'd0,
			 S1=3'd1,
			 S2=3'd2,
			 S3=3'd3,
			 S4=3'd4;
			 
parameter Y2RD = 2'd3,
			 R2GD = 2'd2;
			 
			 
reg [2:0] state;
reg [2:0] next_state;

always@(posedge slowclk)
if(clr)
	state<=S0;
else
	state<=next_state;

always@(state)
begin	
	hwy=G;
	cntry=R;
	case(state)
	S0: ;
	S1: hwy=Y;
	S2: hwy=R;
	S3: begin
		 hwy=R;
		 cntry=G;
		 end
	S4: begin
		 hwy=R;
		 cntry=Y;
		 end
	endcase
end

always@(state or X)
begin
case(state)
S0: if(X)
		next_state=S1;
		else
		next_state=S0;
	S1: begin
		repeat(Y2RD) 
		next_state=S2;
		end
	S2: begin
		repeat(R2GD) 
		next_state=S3;
		end
	S3: if(X)
		next_state=S3;
		else
		next_state=S4;
	S4: begin 
		repeat(Y2RD) 
		next_state=S0;
		end	
		
default: next_state=S0;
endcase
end


endmodule