data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv:14: Cannot find include file: sim_cvita_lib.svh\n`include "sim_cvita_lib.svh" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/crossbar/crossbar_tb,data/full_repos/permissive/214858095/sim_cvita_lib.svh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/crossbar/crossbar_tb,data/full_repos/permissive/214858095/sim_cvita_lib.svh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/crossbar/crossbar_tb,data/full_repos/permissive/214858095/sim_cvita_lib.svh.sv\n             sim_cvita_lib.svh\n             sim_cvita_lib.svh.v\n             sim_cvita_lib.svh.sv\n             obj_dir/sim_cvita_lib.svh\n             obj_dir/sim_cvita_lib.svh.v\n             obj_dir/sim_cvita_lib.svh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv:78: Unsupported or unknown PLI call: $urandom_range\n      gen_dst_sid = $urandom_range(\'d0, NUM_NODES-\'d1);\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv:80: Unsupported or unknown PLI call: $urandom_range\n      rnum = $urandom_range(\'d0, NUM_NODES-\'d2);\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv:104: syntax error, unexpected ::\n    std::process p;\n       ^~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv:105: syntax error, unexpected ::, expecting \';\'\n    p = process::self();\n               ^~\n                                                                                                                                                         : ... Perhaps \'process\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv:110: syntax error, unexpected \'@\'\n      while (start_stb !== 1) @(posedge clk);\n                              ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/crossbar/crossbar_tb/chdr_traffic_source_sim.sv:178: Unsupported or unknown PLI call: $urandom_range\n    throttle <= ($urandom_range(32\'d99, 32\'d0) > {24\'h0, injection_rate});\n                 ^~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
function [15:0] gen_dst_sid;
    input [7:0] traffic_patt;
    input [15:0] last_sid;

    logic [31:0] rnum;
    
    if (traffic_patt == TRAFFIC_PATT_UNIFORM) begin
      gen_dst_sid = $urandom_range('d0, NUM_NODES-'d1);
    end else if (traffic_patt == TRAFFIC_PATT_UNIFORM_OTHERS) begin
      rnum = $urandom_range('d0, NUM_NODES-'d2);
      if (rnum < NODE_ID)
        gen_dst_sid = rnum[15:0];
      else
        gen_dst_sid = rnum[15:0] + 16'd1;
    end else if (traffic_patt == TRAFFIC_PATT_SEQUENTIAL) begin
      gen_dst_sid = (last_sid + 16'd1) % NUM_NODES;
    end else if (traffic_patt == TRAFFIC_PATT_NEIGHBOR) begin
      gen_dst_sid = (NODE_ID + 16'd1) % NUM_NODES;
    end else if (traffic_patt == TRAFFIC_PATT_LOOPBACK) begin
      gen_dst_sid = NODE_ID;
    end else if (traffic_patt == TRAFFIC_PATT_BIT_COMPLEMENT) begin
      gen_dst_sid = (NUM_NODES - NODE_ID - 1) % NUM_NODES;
    end else if (traffic_patt == TRAFFIC_PATT_RANDOM_PERM) begin

      gen_dst_sid = 0;
    end else begin
      gen_dst_sid = 'd0;
    end
  endfunction
function [15:0] gen_dst_sid;

    input [7:0] traffic_patt;
    input [15:0] last_sid;

    logic [31:0] rnum;
    
    if (traffic_patt == TRAFFIC_PATT_UNIFORM) begin
      gen_dst_sid = $urandom_range('d0, NUM_NODES-'d1);
    end else if (traffic_patt == TRAFFIC_PATT_UNIFORM_OTHERS) begin
      rnum = $urandom_range('d0, NUM_NODES-'d2);
      if (rnum < NODE_ID)
        gen_dst_sid = rnum[15:0];
      else
        gen_dst_sid = rnum[15:0] + 16'd1;
    end else if (traffic_patt == TRAFFIC_PATT_SEQUENTIAL) begin
      gen_dst_sid = (last_sid + 16'd1) % NUM_NODES;
    end else if (traffic_patt == TRAFFIC_PATT_NEIGHBOR) begin
      gen_dst_sid = (NODE_ID + 16'd1) % NUM_NODES;
    end else if (traffic_patt == TRAFFIC_PATT_LOOPBACK) begin
      gen_dst_sid = NODE_ID;
    end else if (traffic_patt == TRAFFIC_PATT_BIT_COMPLEMENT) begin
      gen_dst_sid = (NUM_NODES - NODE_ID - 1) % NUM_NODES;
    end else if (traffic_patt == TRAFFIC_PATT_RANDOM_PERM) begin

      gen_dst_sid = 0;
    end else begin
      gen_dst_sid = 'd0;
    end
  endfunction