data/full_repos/permissive/174323821/hdl/clocking/jtframe_sync.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/174323821/hdl/clocking/jtframe_sync.v:65: Multiple top level modules\n                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                      : ... Top module \'jtframe_sync\'\nmodule jtframe_sync #( parameter\n       ^~~~~~~~~~~~\n                                                                                      : ... Top module \'jtframe_sync_cen\'\nmodule jtframe_sync_cen #(parameter W=1, LATCHIN=0)(\n       ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module jtframe_sync_cen #(parameter W=1, LATCHIN=0)(
    input   clk_in,
    input   clk_out,
    input   cen,
    input   [W-1:0] raw,
    output  [W-1:0] sync
);

reg  [W-1:0] latched;
wire [W-1:0] eff;

always @(posedge clk_in) if(cen) latched <= raw;
assign eff = LATCHIN ? latched : raw;

generate
    genvar i;
    for( i=0; i<W; i=i+1 ) begin : synchronizer
        reg [1:0] s;
        assign sync[i] = s[1];

        always @(posedge clk_out) begin
            s <= { s[0], eff[i] };
        end
    end
endgenerate

endmodule
module jtframe_sync_cen #(parameter W=1, LATCHIN=0)(
    input   clk_in,
    input   clk_out,
    input   cen,
    input   [W-1:0] raw,
    output  [W-1:0] sync
);


reg  [W-1:0] latched;
wire [W-1:0] eff;

always @(posedge clk_in) if(cen) latched <= raw;
assign eff = LATCHIN ? latched : raw;

generate
    genvar i;
    for( i=0; i<W; i=i+1 ) begin : synchronizer
        reg [1:0] s;
        assign sync[i] = s[1];

        always @(posedge clk_out) begin
            s <= { s[0], eff[i] };
        end
    end
endgenerate

endmodule