data/full_repos/permissive/212763527/school_project/8_mult_div/testbenches/tb_divider.v
 line:37: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/8_mult_div/testbenches/tb_divider.v:19: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD/2) \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/8_mult_div/testbenches/tb_divider.v:39: Unsupported: Ignoring delay on this delayed statement.\n            #CLK_PERIOD\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/8_mult_div/testbenches/tb_divider.v:41: Unsupported: Ignoring delay on this delayed statement.\n            #(33*CLK_PERIOD)  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/8_mult_div/testbenches/tb_divider.v:44: Unsupported: Ignoring delay on this delayed statement.\n            #CLK_PERIOD\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/8_mult_div/testbenches/tb_divider.v:37: Unsupported: Ignoring delay on this delayed statement.\n        repeat (2) #CLK_PERIOD begin\n                   ^\n%Error: data/full_repos/permissive/212763527/school_project/8_mult_div/testbenches/tb_divider.v:22: Cannot find file containing module: \'divider\'\n    divider #(32) utt (\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/school_project/8_mult_div/testbenches,data/full_repos/permissive/212763527/divider\n             data/full_repos/permissive/212763527/school_project/8_mult_div/testbenches,data/full_repos/permissive/212763527/divider.v\n             data/full_repos/permissive/212763527/school_project/8_mult_div/testbenches,data/full_repos/permissive/212763527/divider.sv\n             divider\n             divider.v\n             divider.sv\n             obj_dir/divider\n             obj_dir/divider.v\n             obj_dir/divider.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_divider;

    reg clk = 1'b0;


    reg [31:0] a;
    reg [31:0] b;
    reg e = 1'b1;
    reg read = 1'b1;


    wire [31:0] q;
    wire [31:0] r;
    wire d;

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;
    
    divider #(32) utt (
        clk,
        e,
        read,
        a,
        b,
        q,
        r,
        d
    );

    initial begin

        a = 405;
        b = 5;
        repeat (2) #CLK_PERIOD begin
            read = 1'b1;
            #CLK_PERIOD
            read = 1'b0;
            #(33*CLK_PERIOD)
            e = 1'b0;

            #CLK_PERIOD
            e = 1'b1;
            a = a - 23;
            b = b + 5;
            read = 1'b1;
        end
        $finish;
    end

endmodule
module tb_divider;


    reg clk = 1'b0;


    reg [31:0] a;
    reg [31:0] b;
    reg e = 1'b1;
    reg read = 1'b1;


    wire [31:0] q;
    wire [31:0] r;
    wire d;

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;
    
    divider #(32) utt (
        clk,
        e,
        read,
        a,
        b,
        q,
        r,
        d
    );

    initial begin

        a = 405;
        b = 5;
        repeat (2) #CLK_PERIOD begin
            read = 1'b1;
            #CLK_PERIOD
            read = 1'b0;
            #(33*CLK_PERIOD)
            e = 1'b0;

            #CLK_PERIOD
            e = 1'b1;
            a = a - 23;
            b = b + 5;
            read = 1'b1;
        end
        $finish;
    end

endmodule