data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #10\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Error: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:48: Unsupported or unknown PLI call: $monitor\n        $monitor("sel=%b din_case=%b din_block=%b dout0_case=%b dout1_case=%b dout2_case=%b dout3_case=%b dout0_block=%b dout1_block=%b dout2_block=%b dout3_block=%b", \n        ^~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_04/src/5_lab4_hdl_nbit_4in1_demux/simulation/testbench.v:52: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;   \n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
parameter DATA_CASE_WIDTH = 8;
parameter DATA_BLOCK_WIDTH  = 2;

    wire  [DATA_CASE_WIDTH-1:0] dout0_case;
	wire  [DATA_CASE_WIDTH-1:0] dout1_case;
    wire  [DATA_CASE_WIDTH-1:0] dout2_case;
	wire  [DATA_CASE_WIDTH-1:0] dout3_case;
	wire  [DATA_BLOCK_WIDTH-1:0] dout0_block;
	wire  [DATA_BLOCK_WIDTH-1:0] dout1_block;
    wire  [DATA_BLOCK_WIDTH-1:0] dout2_block;
	wire  [DATA_BLOCK_WIDTH-1:0] dout3_block;
	reg   [1:0] sel;
	reg   [DATA_CASE_WIDTH-1:0] din_case;
	reg   [DATA_BLOCK_WIDTH-1:0] din_block;
	
 

	bn_demux_1_4_case #(DATA_CASE_WIDTH) bn_demux_1_4_case (.din(din_case), .sel(sel), .dout0(dout0_case), .dout1(dout1_case), .dout2(dout2_case), .dout3(dout3_case));
	b2_demux_1_4_block b2_demux_1_4_block (.din(din_block), .sel(sel), .dout0(dout0_block), .dout1(dout1_block), .dout2(dout2_block), .dout3(dout3_block));
	
	initial 
        begin
			din_case=8'b11111111;
			din_block=din_case;
			#5;
            sel = 2'b00;
			#10;
			sel = 2'b01;
			#10
			sel = 2'b10;
			#10;
			sel = 2'b11;
			#10;
			din_case=8'b10101010;
			din_block=din_case;
			#10;
			din_case=8'b01010101;
			din_block=din_case;
			#10;
        end


    initial 
        $monitor("sel=%b din_case=%b din_block=%b dout0_case=%b dout1_case=%b dout2_case=%b dout3_case=%b dout0_block=%b dout1_block=%b dout2_block=%b dout3_block=%b", 
		         sel, din_case, din_block, dout0_case, dout1_case, dout2_case, dout3_case, dout0_block, dout1_block, dout2_block, dout3_block);

    initial 
        $dumpvars;
endmodule
module testbench;

parameter DATA_CASE_WIDTH = 8;
parameter DATA_BLOCK_WIDTH  = 2;

    wire  [DATA_CASE_WIDTH-1:0] dout0_case;
	wire  [DATA_CASE_WIDTH-1:0] dout1_case;
    wire  [DATA_CASE_WIDTH-1:0] dout2_case;
	wire  [DATA_CASE_WIDTH-1:0] dout3_case;
	wire  [DATA_BLOCK_WIDTH-1:0] dout0_block;
	wire  [DATA_BLOCK_WIDTH-1:0] dout1_block;
    wire  [DATA_BLOCK_WIDTH-1:0] dout2_block;
	wire  [DATA_BLOCK_WIDTH-1:0] dout3_block;
	reg   [1:0] sel;
	reg   [DATA_CASE_WIDTH-1:0] din_case;
	reg   [DATA_BLOCK_WIDTH-1:0] din_block;
	
 

	bn_demux_1_4_case #(DATA_CASE_WIDTH) bn_demux_1_4_case (.din(din_case), .sel(sel), .dout0(dout0_case), .dout1(dout1_case), .dout2(dout2_case), .dout3(dout3_case));
	b2_demux_1_4_block b2_demux_1_4_block (.din(din_block), .sel(sel), .dout0(dout0_block), .dout1(dout1_block), .dout2(dout2_block), .dout3(dout3_block));
	
	initial 
        begin
			din_case=8'b11111111;
			din_block=din_case;
			#5;
            sel = 2'b00;
			#10;
			sel = 2'b01;
			#10
			sel = 2'b10;
			#10;
			sel = 2'b11;
			#10;
			din_case=8'b10101010;
			din_block=din_case;
			#10;
			din_case=8'b01010101;
			din_block=din_case;
			#10;
        end


    initial 
        $monitor("sel=%b din_case=%b din_block=%b dout0_case=%b dout1_case=%b dout2_case=%b dout3_case=%b dout0_block=%b dout1_block=%b dout2_block=%b dout3_block=%b", 
		         sel, din_case, din_block, dout0_case, dout1_case, dout2_case, dout3_case, dout0_block, dout1_block, dout2_block, dout3_block);

    initial 
        $dumpvars;
endmodule