data/full_repos/permissive/156966470/hdl/jt49_cen.v
data/verilator_xmls/4df3e214-5776-4059-8c8f-c17b20c5b180.xml
module jt49_cen(
    input       clk,
    input       rst_n,
    input       cen,
    input       sel,
    output  reg cen16,
    output  reg cen256
);

reg [9:0] cencnt;
parameter CLKDIV = 3;
localparam eg = CLKDIV;

wire toggle16 = sel ? ~|cencnt[CLKDIV-1:0] : ~|cencnt[CLKDIV:0];
wire toggle256= sel ? ~|cencnt[eg-2:0]     : ~|cencnt[eg-1:0];


always @(posedge clk, negedge rst_n) begin
    if(!rst_n)
        cencnt <= 10'd0;
    else begin 
        if(cen) cencnt <= cencnt+10'd1;
    end
end

always @(posedge clk) begin
    cen16  <= cen & toggle16;
    cen256 <= cen & toggle256;
end


endmodule
module jt49_cen(
    input       clk,
    input       rst_n,
    input       cen,
    input       sel,
    output  reg cen16,
    output  reg cen256
);


reg [9:0] cencnt;
parameter CLKDIV = 3;
localparam eg = CLKDIV;

wire toggle16 = sel ? ~|cencnt[CLKDIV-1:0] : ~|cencnt[CLKDIV:0];
wire toggle256= sel ? ~|cencnt[eg-2:0]     : ~|cencnt[eg-1:0];


always @(posedge clk, negedge rst_n) begin
    if(!rst_n)
        cencnt <= 10'd0;
    else begin 
        if(cen) cencnt <= cencnt+10'd1;
    end
end

always @(posedge clk) begin
    cen16  <= cen & toggle16;
    cen256 <= cen & toggle256;
end


endmodule