data/full_repos/permissive/150214807/lab5.v
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1: b'%Error: data/full_repos/permissive/150214807/lab5.v:100: Unsupported or unknown PLI call: $monitor\n$monitor(,$time,"r1=%b r2=%b reset=%b, w=%b, d=%h, rd1=%h, rd2=%h rw=%b",rr1,rr2,rst,w,wd,rd1,rd2,rw);\n^~~~~~~~\n%Error: data/full_repos/permissive/150214807/lab5.v:100: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n$monitor(,$time,"r1=%b r2=%b reset=%b, w=%b, d=%h, rd1=%h, rd2=%h rw=%b",rr1,rr2,rst,w,wd,rd1,rd2,rw);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:102: Unsupported: Ignoring delay on this delayed statement.\n#30 rst = 1\'b1; wd=32\'hAFAFAFAF; w=2\'b10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:103: Unsupported: Ignoring delay on this delayed statement.\n#10 rw=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:104: Unsupported: Ignoring delay on this delayed statement.\n#15 w=2\'b01;\n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:105: Unsupported: Ignoring delay on this delayed statement.\n#20 wd=32\'hFAFAFAFA;\n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:106: Unsupported: Ignoring delay on this delayed statement.\n#10 rst=1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:107: Unsupported: Ignoring delay on this delayed statement.\n#200 $finish;\n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab5.v:111: Unsupported: Ignoring delay on this delayed statement.\n#7 clk = ~clk;\n^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux4_1(regData,q1,q2,q3,q4,reg_no);
	input [31:0] q1,q2,q3,q4;
	input [1:0] reg_no;
	output [31:0] regData;
	wire [31:0] w1,w2,w3,w4;
	wire [1:0] neg_reg;
	not n1(neg_reg[1],reg_no[1]);
	not n0(neg_reg[0],reg_no[0]);
	genvar j;
	generate for (j=0;j<32;j=j+1) begin: and_iter
		and s0(w1[j],q1[j],neg_reg[1],neg_reg[0]);
		and s1(w2[j],q2[j],neg_reg[1],reg_no[0]);
		and s2(w3[j],q3[j],reg_no[1],neg_reg[0]);
		and s3(w4[j],q4[j],reg_no[1],reg_no[0]);
		or fingate(regData[j],w1[j],w2[j],w3[j],w4[j]);
	end
	endgenerate
endmodule
module mux4_1(regData,q1,q2,q3,q4,reg_no);

	input [31:0] q1,q2,q3,q4;
	input [1:0] reg_no;
	output [31:0] regData;
	wire [31:0] w1,w2,w3,w4;
	wire [1:0] neg_reg;
	not n1(neg_reg[1],reg_no[1]);
	not n0(neg_reg[0],reg_no[0]);
	genvar j;
	generate for (j=0;j<32;j=j+1) begin: and_iter
		and s0(w1[j],q1[j],neg_reg[1],neg_reg[0]);
		and s1(w2[j],q2[j],neg_reg[1],reg_no[0]);
		and s2(w3[j],q3[j],reg_no[1],neg_reg[0]);
		and s3(w4[j],q4[j],reg_no[1],reg_no[0]);
		or fingate(regData[j],w1[j],w2[j],w3[j],w4[j]);
	end
	endgenerate
endmodule