data/full_repos/permissive/127241521/updown-blinker/tests/main_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/127241521/updown-blinker/tests/main_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #10  PB = 2;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/127241521/updown-blinker/tests/main_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #50  PB = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127241521/updown-blinker/tests/main_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #100 PB = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127241521/updown-blinker/tests/main_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #110 PB = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127241521/updown-blinker/tests/main_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #150 PB = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/127241521/updown-blinker/tests/main_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #160 PB = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127241521/updown-blinker/tests/main_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n always #10 OSC_FPGA = ~OSC_FPGA;\n        ^\n%Error: data/full_repos/permissive/127241521/updown-blinker/tests/main_test.v:13: Cannot find file containing module: \'main\'\n main uut(\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/127241521/updown-blinker/tests,data/full_repos/permissive/127241521/main\n             data/full_repos/permissive/127241521/updown-blinker/tests,data/full_repos/permissive/127241521/main.v\n             data/full_repos/permissive/127241521/updown-blinker/tests,data/full_repos/permissive/127241521/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_test;


	reg OSC_FPGA;
	reg [1:0] PB;


	wire [1:0] LED;


	main uut(
		.OSC_FPGA(OSC_FPGA), 
		.PB(PB), 
		.LED(LED)
	);

	initial begin

		OSC_FPGA = 0;
		PB = 0;
		
		#10  PB = 2;
		#50  PB = 0;
		#100 PB = 1;
		#110 PB = 0;
      #150 PB = 1;
		#160 PB = 0;
	end
	
	always #10 OSC_FPGA = ~OSC_FPGA;
       
endmodule
module main_test;



	reg OSC_FPGA;
	reg [1:0] PB;


	wire [1:0] LED;


	main uut(
		.OSC_FPGA(OSC_FPGA), 
		.PB(PB), 
		.LED(LED)
	);

	initial begin

		OSC_FPGA = 0;
		PB = 0;
		
		#10  PB = 2;
		#50  PB = 0;
		#100 PB = 1;
		#110 PB = 0;
      #150 PB = 1;
		#160 PB = 0;
	end
	
	always #10 OSC_FPGA = ~OSC_FPGA;
       
endmodule