data/full_repos/permissive/106966316/extencion_signo_tb.v
 line:31: before: "reg"
1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/extencion_signo_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/extencion_signo_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/extencion_signo_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/extencion_signo_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/106966316/extencion_signo_tb.v:28: Cannot find file containing module: \'extencion_signo\'\n    extencion_signo uut (\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/extencion_signo\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/extencion_signo.v\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/extencion_signo.sv\n             extencion_signo\n             extencion_signo.v\n             extencion_signo.sv\n             obj_dir/extencion_signo\n             obj_dir/extencion_signo.v\n             obj_dir/extencion_signo.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module extencion_signo_tb;
    
    reg [15:0] instr;
    wire [31:0] oinstr;
    
    extencion_signo uut (
        .instr(instr),
        .oinstr(oinstr)
    );
    
    initial begin 
    
    instr = 16'b1111111111111111;
    #100;
    
    instr = 16'b0111111111111111;
    #100;
    
    instr = 16'b1111111111111111;
    #100;
    
    instr = 16'b0111111111111111;
    #100;
    
    end
    
endmodule
module extencion_signo_tb;

    
    reg [15:0] instr;
    wire [31:0] oinstr;
    
    extencion_signo uut (
        .instr(instr),
        .oinstr(oinstr)
    );
    
    initial begin 
    
    instr = 16'b1111111111111111;
    #100;
    
    instr = 16'b0111111111111111;
    #100;
    
    instr = 16'b1111111111111111;
    #100;
    
    instr = 16'b0111111111111111;
    #100;
    
    end
    
endmodule