data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/demux-1x4/demux-1x4.v
1: b"%Error: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/demux-1x4/demux-1x4.v:8: Duplicate declaration of signal: 'a'\n                                                                                                                        : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg  a, b, c, d;\n     ^\n        data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/demux-1x4/demux-1x4.v:5: ... Location of original declaration\n    output a, b, c, d        \n           ^\n%Error: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/demux-1x4/demux-1x4.v:8: Duplicate declaration of signal: 'b'\nreg  a, b, c, d;\n        ^\n        data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/demux-1x4/demux-1x4.v:5: ... Location of original declaration\n    output a, b, c, d        \n              ^\n%Error: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/demux-1x4/demux-1x4.v:8: Duplicate declaration of signal: 'c'\nreg  a, b, c, d;\n           ^\n        data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/demux-1x4/demux-1x4.v:5: ... Location of original declaration\n    output a, b, c, d        \n                 ^\n%Error: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/demux-1x4/demux-1x4.v:8: Duplicate declaration of signal: 'd'\nreg  a, b, c, d;\n              ^\n        data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/demux-1x4/demux-1x4.v:5: ... Location of original declaration\n    output a, b, c, d        \n                    ^\n%Error: Exiting due to 4 error(s)\n"
module demux_1x4(
    input  y,
    input  [1:0] sel,
    output a, b, c, d
);

reg  a, b, c, d;

always @ ( * ) begin
    case(sel)
        2'b00 : begin
            a <= y; b <= 0; c <= 0; d <= 0;
        end
        2'b01 : begin
            a <= 0; b <= y; c <= 0; d <= 0;
        end
        2'b10 : begin
            a <= 0; b <= 0; c <= y; d <= 0;
        end
        2'b11 : begin
            a <= 0; b <= 0; c <= 0; d <= y;
        end
    endcase
end

endmodule
module demux_1x4(
    input  y,
    input  [1:0] sel,
    output a, b, c, d
);


reg  a, b, c, d;

always @ ( * ) begin
    case(sel)
        2'b00 : begin
            a <= y; b <= 0; c <= 0; d <= 0;
        end
        2'b01 : begin
            a <= 0; b <= y; c <= 0; d <= 0;
        end
        2'b10 : begin
            a <= 0; b <= 0; c <= y; d <= 0;
        end
        2'b11 : begin
            a <= 0; b <= 0; c <= 0; d <= y;
        end
    endcase
end

endmodule