data/full_repos/permissive/12139067/common_hdl/hwrandom_core.v
1: b'%Error: data/full_repos/permissive/12139067/common_hdl/hwrandom_core.v:23: Cannot find file containing module: \'ringosc\'\n    ringosc #(.NUMGATES(i + 1)) osc (.reset(reset), .clkout(ringout[i]));\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/12139067/common_hdl,data/full_repos/permissive/12139067/ringosc\n             data/full_repos/permissive/12139067/common_hdl,data/full_repos/permissive/12139067/ringosc.v\n             data/full_repos/permissive/12139067/common_hdl,data/full_repos/permissive/12139067/ringosc.sv\n             ringosc\n             ringosc.v\n             ringosc.sv\n             obj_dir/ringosc\n             obj_dir/ringosc.v\n             obj_dir/ringosc.sv\n%Error: data/full_repos/permissive/12139067/common_hdl/hwrandom_core.v:57: Cannot find file containing module: \'uart_transmitter\'\n    uart_transmitter #(.comm_clk_frequency(comm_clk_frequency)) utx (.clk(clk), .uart_tx(TxD[j]), .rx_new_byte(TxD_start[j]), .rx_byte(out_byte), .tx_ready(TxD_ready[j]));\n    ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/12139067/common_hdl/hwrandom_core.v:71: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n                                                                                 : ... In instance hwrandom_core\n    TxD_start[port_counter] <= 1;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/12139067/common_hdl/hwrandom_core.v:81: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n                                                                                 : ... In instance hwrandom_core\n      else TxD_start[port_counter] <= 0;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/12139067/common_hdl/hwrandom_core.v:69: Bit extraction of var[0:0] requires 1 bit index, not 2 bits.\n                                                                                 : ... In instance hwrandom_core\n      if (TxD_ready[port_counter])\n                   ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module hwrandom_core(clk, TxD, reset, disp_word);
`else
module hwrandom_core(clk, TxD, reset);
`endif
   
   parameter NUM_PORTS = 1;
   



   parameter NUM_RINGOSCS = 241;

   wire [NUM_RINGOSCS-1:0] ringout;

   input 		   clk;
   input 		   reset;
   
   generate
      genvar 	      i;
      for (i = 0; i < NUM_RINGOSCS; i = i + 1)
	begin: for_ringosc
	   ringosc #(.NUMGATES(i + 1)) osc (.reset(reset), .clkout(ringout[i]));
	end
   endgenerate
   
   wire       ringxor;
   assign ringxor = ^ringout;






   



   


   reg [7:0]  out_byte;
   reg [3:0]  bit_counter = 0;


   output [NUM_PORTS-1:0] TxD;
   
   wire [NUM_PORTS-1:0]   TxD_ready;
   reg [NUM_PORTS-1:0] 	  TxD_start;

   parameter comm_clk_frequency = 50_000_000;

   generate
      genvar 		  j;
      for (j = 0; j < NUM_PORTS; j = j + 1)
	begin: for_uarts
	   uart_transmitter #(.comm_clk_frequency(comm_clk_frequency)) utx (.clk(clk), .uart_tx(TxD[j]), .rx_new_byte(TxD_start[j]), .rx_byte(out_byte), .tx_ready(TxD_ready[j]));
	end
   endgenerate

   reg [$clog2(NUM_PORTS)+1:0] port_counter = 0;

   always @(posedge clk)
     begin
	out_byte[bit_counter[2:0]] <= ringxor;

	if (bit_counter == 4'b0111)
	  begin
	     if (TxD_ready[port_counter])
	       begin
		  TxD_start[port_counter] <= 1;
		  



		  if (port_counter == NUM_PORTS-1)
		    port_counter <= 0;
		  else
		    port_counter <= port_counter + 1;
	       end
	     else TxD_start[port_counter] <= 0;
	     



	     bit_counter <= 4'b1111;
	  end
	else
	  bit_counter <= bit_counter + 1;
     end

`ifdef DISPLAY

   output reg [31:0] 	disp_word;

   reg [24:0] 		disp_counter;
   always @ (posedge clk)
     begin
	disp_counter <= disp_counter + 1;
	if (disp_counter == 0)
	  begin
	     disp_word <= disp_word << 8;
	     disp_word[7:0] <= out_byte;
	  end
     end
`endif
endmodule
module hwrandom_core(clk, TxD, reset, disp_word);

`else
module hwrandom_core(clk, TxD, reset);
`endif
   
   parameter NUM_PORTS = 1;
   



   parameter NUM_RINGOSCS = 241;

   wire [NUM_RINGOSCS-1:0] ringout;

   input 		   clk;
   input 		   reset;
   
   generate
      genvar 	      i;
      for (i = 0; i < NUM_RINGOSCS; i = i + 1)
	begin: for_ringosc
	   ringosc #(.NUMGATES(i + 1)) osc (.reset(reset), .clkout(ringout[i]));
	end
   endgenerate
   
   wire       ringxor;
   assign ringxor = ^ringout;






   



   


   reg [7:0]  out_byte;
   reg [3:0]  bit_counter = 0;


   output [NUM_PORTS-1:0] TxD;
   
   wire [NUM_PORTS-1:0]   TxD_ready;
   reg [NUM_PORTS-1:0] 	  TxD_start;

   parameter comm_clk_frequency = 50_000_000;

   generate
      genvar 		  j;
      for (j = 0; j < NUM_PORTS; j = j + 1)
	begin: for_uarts
	   uart_transmitter #(.comm_clk_frequency(comm_clk_frequency)) utx (.clk(clk), .uart_tx(TxD[j]), .rx_new_byte(TxD_start[j]), .rx_byte(out_byte), .tx_ready(TxD_ready[j]));
	end
   endgenerate

   reg [$clog2(NUM_PORTS)+1:0] port_counter = 0;

   always @(posedge clk)
     begin
	out_byte[bit_counter[2:0]] <= ringxor;

	if (bit_counter == 4'b0111)
	  begin
	     if (TxD_ready[port_counter])
	       begin
		  TxD_start[port_counter] <= 1;
		  



		  if (port_counter == NUM_PORTS-1)
		    port_counter <= 0;
		  else
		    port_counter <= port_counter + 1;
	       end
	     else TxD_start[port_counter] <= 0;
	     



	     bit_counter <= 4'b1111;
	  end
	else
	  bit_counter <= bit_counter + 1;
     end

`ifdef DISPLAY

   output reg [31:0] 	disp_word;

   reg [24:0] 		disp_counter;
   always @ (posedge clk)
     begin
	disp_counter <= disp_counter + 1;
	if (disp_counter == 0)
	  begin
	     disp_word <= disp_word << 8;
	     disp_word[7:0] <= out_byte;
	  end
     end
`endif
endmodule