data/full_repos/permissive/160976968/adder.v
1: b"%Error: data/full_repos/permissive/160976968/adder.v:10: syntax error, unexpected '(', expecting IDENTIFIER\n comparator(SW[3:0], 0, X_EC);\n            ^~\n%Error: Exiting due to 1 error(s)\n"
module circuitA(V, c, A);
	input [3:0]V;
	input c;
	output [3:0]A;
	assign A[3] = c & V[1];
	assign A[2] = (~c & V[3] & V[2] & V[1] & ~V[0])
					| (~c & V[3] & V[2] & V[1] & V[0])
					| (c & ~V[3] & ~V[2] & ~V[1] & ~V[0])
					| (c & ~V[3] & ~V[2] & ~V[1] & V[0]);
	assign A[1] = (~c & V[3] & V[2] & ~V[1] & ~V[0])
					| (~c & V[3] & V[2] & ~V[1] & V[0])
					| (c & ~V[3] & ~V[2] & ~V[1] & ~V[0])
					| (c & ~V[3] & ~V[2] & ~V[1] & V[0]);
	assign A[0] = (~c & V[3] & ~V[2] & V[1] & V[0])
					| (~c & V[3] & V[2] & ~V[1] & V[0])
					| (~c & V[3] & V[2] & V[1] & V[0])
					| (c & ~V[3] & ~V[2] & ~V[1] & V[0])
					| (c & ~V[3] & ~V[2] & V[1] & V[0]);
endmodule
module circuitA(V, c, A);

	input [3:0]V;
	input c;
	output [3:0]A;
	assign A[3] = c & V[1];
	assign A[2] = (~c & V[3] & V[2] & V[1] & ~V[0])
					| (~c & V[3] & V[2] & V[1] & V[0])
					| (c & ~V[3] & ~V[2] & ~V[1] & ~V[0])
					| (c & ~V[3] & ~V[2] & ~V[1] & V[0]);
	assign A[1] = (~c & V[3] & V[2] & ~V[1] & ~V[0])
					| (~c & V[3] & V[2] & ~V[1] & V[0])
					| (c & ~V[3] & ~V[2] & ~V[1] & ~V[0])
					| (c & ~V[3] & ~V[2] & ~V[1] & V[0]);
	assign A[0] = (~c & V[3] & ~V[2] & V[1] & V[0])
					| (~c & V[3] & V[2] & ~V[1] & V[0])
					| (~c & V[3] & V[2] & V[1] & V[0])
					| (c & ~V[3] & ~V[2] & ~V[1] & V[0])
					| (c & ~V[3] & ~V[2] & V[1] & V[0]);
endmodule