data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v
 line:59: before: "@"
1: b'%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:51: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("CLB_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:52: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1, r_clk, r_clk_en, r_mode, r_c_bus, r_c_dimension, r_b_in, w_b_out, inst);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:59: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:63: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:67: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:70: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:73: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:76: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:79: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:83: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:87: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:90: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:93: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:96: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:101: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:105: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:109: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:113: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:116: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:119: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:122: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:127: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:131: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:135: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:139: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:142: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:145: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:148: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:153: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:157: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:161: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:165: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:168: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:171: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:174: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:179: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:183: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:187: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:187: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:191: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:191: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:194: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:197: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:200: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:203: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:206: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:209: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:212: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:212: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:215: syntax error, unexpected \'@\'\n  #200 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:215: Unsupported: Ignoring delay on this delayed statement.\n  #200 @(posedge r_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n  #50 r_clk <= ~r_clk;\n  ^\n%Error: Exiting due to 47 error(s), 46 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CLB_tb;

	reg r_clk;
	reg r_clk_en;
	reg r_mode;
	reg [7:0] r_c_bus;
	reg [1:0] r_c_dimension;
	reg [1:0] r_b_in;
	wire w_b_out;

	CLB#(0, 4, 1, 2, 2) inst (
		.clk(r_clk),
		.clk_en(r_clk_en),
		.mode(r_mode),

		.c_clk(r_clk),
		.c_bus(r_c_bus),
		.c_uid(1'b0),
		.c_dimension(r_c_dimension),

		.b_in(r_b_in),
		.b_out(w_b_out)
	);

	initial begin
		$dumpfile("CLB_tb.vcd");
		$dumpvars(1, r_clk, r_clk_en, r_mode, r_c_bus, r_c_dimension, r_b_in, w_b_out, inst);
		r_clk <= 'b1;
		r_clk_en <= 'b0;
		r_mode <= 'b0;
		r_c_bus <= 'h0;
		r_c_dimension <= 'h0;
		r_b_in <= 'h0;
		#100 @(posedge r_clk);


		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_bus <= {1'b0, 1'b1, 2'h0, 4'h1};
		#50 @(posedge r_clk);

		r_c_bus <= {1'b0, 1'b1, 2'h1, 4'hd};
		#50 @(posedge r_clk);

		r_c_bus <= {1'b0, 1'b1, 2'h2, 4'hd};
		#50 @(posedge r_clk);

		r_c_bus <= {1'b0, 1'b1, 2'h3, 4'hb};
		#50 @(posedge r_clk);

		r_c_bus <= {1'b1, 1'b0, 2'h0, 4'h4};
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_b_in <= 'h0;
		#50 @(posedge r_clk);

		r_b_in <= 'h1;
		#50 @(posedge r_clk);

		r_b_in <= 'h2;
		#50 @(posedge r_clk);

		r_b_in <= 'h3;
		#50 @(posedge r_clk);



		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h1;
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_b_in <= 'h0;
		#50 @(posedge r_clk);

		r_b_in <= 'h1;
		#50 @(posedge r_clk);

		r_b_in <= 'h2;
		#50 @(posedge r_clk);

		r_b_in <= 'h3;
		#50 @(posedge r_clk);



		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h2;
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_b_in <= 'h0;
		#50 @(posedge r_clk);

		r_b_in <= 'h1;
		#50 @(posedge r_clk);

		r_b_in <= 'h2;
		#50 @(posedge r_clk);

		r_b_in <= 'h3;
		#50 @(posedge r_clk);



		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h3;
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_b_in <= 'h0;
		#50 @(posedge r_clk);

		r_b_in <= 'h1;
		#50 @(posedge r_clk);

		r_b_in <= 'h2;
		#50 @(posedge r_clk);

		r_b_in <= 'h3;
		#50 @(posedge r_clk);



		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h2;
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_b_in <= 'h0;
		#50 @(posedge r_clk);

		r_b_in <= 'h1;
		#50 @(posedge r_clk);

		r_clk_en <= 'b1;
		#50 @(posedge r_clk);

		r_clk_en <= 'b0;
		#50 @(posedge r_clk);

		r_b_in <= 'h2;
		#50 @(posedge r_clk);

		r_b_in <= 'h3;
		#50 @(posedge r_clk);

		r_clk_en <= 'b1;
		#50 @(posedge r_clk);

		r_clk_en <= 'b0;
		#50 @(posedge r_clk);


		#200 @(posedge r_clk);

		$finish;
	end

	always begin
		#50 r_clk <= ~r_clk;
	end

endmodule
module CLB_tb;


	reg r_clk;
	reg r_clk_en;
	reg r_mode;
	reg [7:0] r_c_bus;
	reg [1:0] r_c_dimension;
	reg [1:0] r_b_in;
	wire w_b_out;

	CLB#(0, 4, 1, 2, 2) inst (
		.clk(r_clk),
		.clk_en(r_clk_en),
		.mode(r_mode),

		.c_clk(r_clk),
		.c_bus(r_c_bus),
		.c_uid(1'b0),
		.c_dimension(r_c_dimension),

		.b_in(r_b_in),
		.b_out(w_b_out)
	);

	initial begin
		$dumpfile("CLB_tb.vcd");
		$dumpvars(1, r_clk, r_clk_en, r_mode, r_c_bus, r_c_dimension, r_b_in, w_b_out, inst);
		r_clk <= 'b1;
		r_clk_en <= 'b0;
		r_mode <= 'b0;
		r_c_bus <= 'h0;
		r_c_dimension <= 'h0;
		r_b_in <= 'h0;
		#100 @(posedge r_clk);


		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_bus <= {1'b0, 1'b1, 2'h0, 4'h1};
		#50 @(posedge r_clk);

		r_c_bus <= {1'b0, 1'b1, 2'h1, 4'hd};
		#50 @(posedge r_clk);

		r_c_bus <= {1'b0, 1'b1, 2'h2, 4'hd};
		#50 @(posedge r_clk);

		r_c_bus <= {1'b0, 1'b1, 2'h3, 4'hb};
		#50 @(posedge r_clk);

		r_c_bus <= {1'b1, 1'b0, 2'h0, 4'h4};
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_b_in <= 'h0;
		#50 @(posedge r_clk);

		r_b_in <= 'h1;
		#50 @(posedge r_clk);

		r_b_in <= 'h2;
		#50 @(posedge r_clk);

		r_b_in <= 'h3;
		#50 @(posedge r_clk);



		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h1;
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_b_in <= 'h0;
		#50 @(posedge r_clk);

		r_b_in <= 'h1;
		#50 @(posedge r_clk);

		r_b_in <= 'h2;
		#50 @(posedge r_clk);

		r_b_in <= 'h3;
		#50 @(posedge r_clk);



		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h2;
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_b_in <= 'h0;
		#50 @(posedge r_clk);

		r_b_in <= 'h1;
		#50 @(posedge r_clk);

		r_b_in <= 'h2;
		#50 @(posedge r_clk);

		r_b_in <= 'h3;
		#50 @(posedge r_clk);



		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h3;
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_b_in <= 'h0;
		#50 @(posedge r_clk);

		r_b_in <= 'h1;
		#50 @(posedge r_clk);

		r_b_in <= 'h2;
		#50 @(posedge r_clk);

		r_b_in <= 'h3;
		#50 @(posedge r_clk);



		r_mode <= 'b1;
		#100 @(posedge r_clk);


		r_c_dimension <= 'h2;
		#50 @(posedge r_clk);


		r_mode <= 'b0;
		#100 @(posedge r_clk);


		r_b_in <= 'h0;
		#50 @(posedge r_clk);

		r_b_in <= 'h1;
		#50 @(posedge r_clk);

		r_clk_en <= 'b1;
		#50 @(posedge r_clk);

		r_clk_en <= 'b0;
		#50 @(posedge r_clk);

		r_b_in <= 'h2;
		#50 @(posedge r_clk);

		r_b_in <= 'h3;
		#50 @(posedge r_clk);

		r_clk_en <= 'b1;
		#50 @(posedge r_clk);

		r_clk_en <= 'b0;
		#50 @(posedge r_clk);


		#200 @(posedge r_clk);

		$finish;
	end

	always begin
		#50 r_clk <= ~r_clk;
	end

endmodule