data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v
data/verilator_xmls/c6985e7a-8c79-4e1a-be66-e6c7e848fd57.xml
module mac_36(a, b, c, out);
parameter DATA_WIDTH = 4;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out = a * b + c;

endmodule
module mac_36(a, b, c, out);

parameter DATA_WIDTH = 4;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out = a * b + c;

endmodule