data/full_repos/permissive/205055389/test/verga/buf.v
 line:16: before: "7"
1: b'%Error: data/full_repos/permissive/205055389/test/verga/buf.v:6: Unsupported or unknown PLI call: $monitor\n    $monitor("%4d: a=%b : x=%b  y=%b  z=%b : i=%b j=%b k=%b",$time,a,x,y,z,i,j,k);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/buf.v:10: Unsupported: Ignoring delay on this delayed statement.\n #10 a = 1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/buf.v:11: Unsupported: Ignoring delay on this delayed statement.\n #10 a = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/buf.v:12: Unsupported: Ignoring delay on this delayed statement.\n #10 a = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/buf.v:13: Unsupported: Ignoring delay on this delayed statement.\n #10 a = 0;\n ^\n%Error: data/full_repos/permissive/205055389/test/verga/buf.v:16: syntax error, unexpected \',\', expecting \')\'\n  buf #7 b(x,y,z,a);\n              ^\n%Error: data/full_repos/permissive/205055389/test/verga/buf.v:17: syntax error, unexpected \',\', expecting \')\'\n  not #5 n(i,j,k,a);\n              ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg a;
  wire x,y,z,i,j,k;

  initial
    $monitor("%4d: a=%b : x=%b  y=%b  z=%b : i=%b j=%b k=%b",$time,a,x,y,z,i,j,k);

  initial
    begin
	#10 a = 1;
	#10 a = 0;
	#10 a = 1;
	#10 a = 0;
    end

  buf #7 b(x,y,z,a);
  not #5 n(i,j,k,a);

endmodule
module top;

  reg a;
  wire x,y,z,i,j,k;

  initial
    $monitor("%4d: a=%b : x=%b  y=%b  z=%b : i=%b j=%b k=%b",$time,a,x,y,z,i,j,k);

  initial
    begin
	#10 a = 1;
	#10 a = 0;
	#10 a = 1;
	#10 a = 0;
    end

  buf #7 b(x,y,z,a);
  not #5 n(i,j,k,a);

endmodule