data/full_repos/permissive/149848590/src/cpu/core/registers/HILOReadProxy.v
1: b'%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILOReadProxy.v:3: Cannot find include file: ../define/bus.v\n`include "../define/bus.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149848590/src/cpu/core/registers,data/full_repos/permissive/149848590/../define/bus.v\n             data/full_repos/permissive/149848590/src/cpu/core/registers,data/full_repos/permissive/149848590/../define/bus.v.v\n             data/full_repos/permissive/149848590/src/cpu/core/registers,data/full_repos/permissive/149848590/../define/bus.v.sv\n             ../define/bus.v\n             ../define/bus.v.v\n             ../define/bus.v.sv\n             obj_dir/../define/bus.v\n             obj_dir/../define/bus.v.v\n             obj_dir/../define/bus.v.sv\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILOReadProxy.v:7: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] hi_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILOReadProxy.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`DATA_BUS] hi_in,\n                    ^\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILOReadProxy.v:8: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] lo_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILOReadProxy.v:11: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] mem_hi_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILOReadProxy.v:12: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] mem_lo_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILOReadProxy.v:15: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] wb_hi_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILOReadProxy.v:16: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] wb_lo_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILOReadProxy.v:18: Define or directive not defined: \'`DATA_BUS\'\n    output reg[`DATA_BUS] hi_out,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/registers/HILOReadProxy.v:19: Define or directive not defined: \'`DATA_BUS\'\n    output reg[`DATA_BUS] lo_out\n               ^~~~~~~~~\n%Error: Exiting due to 10 error(s)\n'
module HILOReadProxy(

    input [`DATA_BUS] hi_in,
    input [`DATA_BUS] lo_in,

    input mem_hilo_write_en,
    input [`DATA_BUS] mem_hi_in,
    input [`DATA_BUS] mem_lo_in,

    input wb_hilo_write_en,
    input [`DATA_BUS] wb_hi_in,
    input [`DATA_BUS] wb_lo_in,

    output reg[`DATA_BUS] hi_out,
    output reg[`DATA_BUS] lo_out
);


    always @(*) begin
        if (mem_hilo_write_en) begin
            hi_out <= mem_hi_in;
            lo_out <= mem_lo_in;
        end
        else if (wb_hilo_write_en) begin
            hi_out <= wb_hi_in;
            lo_out <= wb_lo_in;
        end
        else begin
            hi_out <= hi_in;
            lo_out <= lo_in;
        end
    end

endmodule
module HILOReadProxy(

    input [`DATA_BUS] hi_in,
    input [`DATA_BUS] lo_in,

    input mem_hilo_write_en,
    input [`DATA_BUS] mem_hi_in,
    input [`DATA_BUS] mem_lo_in,

    input wb_hilo_write_en,
    input [`DATA_BUS] wb_hi_in,
    input [`DATA_BUS] wb_lo_in,

    output reg[`DATA_BUS] hi_out,
    output reg[`DATA_BUS] lo_out
);



    always @(*) begin
        if (mem_hilo_write_en) begin
            hi_out <= mem_hi_in;
            lo_out <= mem_lo_in;
        end
        else if (wb_hilo_write_en) begin
            hi_out <= wb_hi_in;
            lo_out <= wb_lo_in;
        end
        else begin
            hi_out <= hi_in;
            lo_out <= lo_in;
        end
    end

endmodule