data/full_repos/permissive/162646941/src/ander3.v
data/verilator_xmls/602e5d83-b143-4320-b9c2-35edd257dc7d.xml
module ander3 (a, b, result);

  input [15:0] a,b;
  output [15:0] result;
  wire [15:0] c;

  assign c[15:8] = a[15:8] & b[15:8];
  assign c[7:0] = a[7:0] & b[7:0];
  assign result = c;

endmodule
module ander3 (a, b, result);


  input [15:0] a,b;
  output [15:0] result;
  wire [15:0] c;

  assign c[15:8] = a[15:8] & b[15:8];
  assign c[7:0] = a[7:0] & b[7:0];
  assign result = c;

endmodule