data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v
 line:24: before: ";"
1: b'%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:62: Cannot find include file: clogb2.vh\n`include "clogb2.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197252258/tb/sim/common/sim_receiver,data/full_repos/permissive/197252258/clogb2.vh\n             data/full_repos/permissive/197252258/tb/sim/common/sim_receiver,data/full_repos/permissive/197252258/clogb2.vh.v\n             data/full_repos/permissive/197252258/tb/sim/common/sim_receiver,data/full_repos/permissive/197252258/clogb2.vh.sv\n             clogb2.vh\n             clogb2.vh.v\n             clogb2.vh.sv\n             obj_dir/clogb2.vh\n             obj_dir/clogb2.vh.v\n             obj_dir/clogb2.vh.sv\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:7: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   next_seq_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:8: Define or directive not defined: \'`TX_CNT_W\'\n    input   [`TX_CNT_W-1:0]         next_seq_tx_id_in,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:9: Define or directive not defined: \'`FLOW_ID_W\'\n    input   [`FLOW_ID_W-1:0]        next_seq_fid_in,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:11: Define or directive not defined: \'`FLOW_ID_W\'\n    output  reg [`FLOW_ID_W-1:0]    resp_fid,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:12: Define or directive not defined: \'`PKT_TYPE_W\'\n    output  reg [`PKT_TYPE_W-1:0]   resp_pkt_type,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:13: Define or directive not defined: \'`PKT_DATA_W\'\n    output  reg [`PKT_DATA_W-1:0]   resp_pkt_data\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:19: Define or directive not defined: \'`FLOW_ID_W\'\nreg  [`FLOW_ID_W-1:0]       read_resp_fid;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:20: Define or directive not defined: \'`PKT_TYPE_W\'\nreg  [`PKT_TYPE_W-1:0]      read_resp_pkt_type;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:21: Define or directive not defined: \'`PKT_DATA_W\'\nreg  [`PKT_DATA_W-1:0]      read_resp_pkt_data;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:24: Define or directive not defined: \'`FLOW_ID_NONE\'\n    read_resp_fid       = `FLOW_ID_NONE;\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    read_resp_fid       = `FLOW_ID_NONE;\n                                       ^\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:25: Define or directive not defined: \'`NONE_PKT\'\n    read_resp_pkt_type  = `NONE_PKT;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:25: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    read_resp_pkt_type  = `NONE_PKT;\n                                   ^\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:26: Define or directive not defined: \'`PKT_DATA_W\'\n    read_resp_pkt_data  = {`PKT_DATA_W{1\'b0}};\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:30: Unsupported or unknown PLI call: $init\n    $init;\n    ^~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:34: Unsupported or unknown PLI call: $send_clk\n    $send_clk;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:44: Define or directive not defined: \'`FLOW_ID_NONE\'\n        resp_fid        <= `FLOW_ID_NONE;\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:44: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        resp_fid        <= `FLOW_ID_NONE;\n                                        ^\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:45: Define or directive not defined: \'`NONE_PKT\'\n        resp_pkt_type   <= `NONE_PKT;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        resp_pkt_type   <= `NONE_PKT;\n                                    ^\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:46: Define or directive not defined: \'`PKT_DATA_W\'\n        resp_pkt_data   <= {`PKT_DATA_W{1\'b0}};\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:52: Unsupported or unknown PLI call: $read_inputs\n        $read_inputs;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/tb/sim/common/sim_receiver/sim_receiver.v:58: Unsupported or unknown PLI call: $write_outputs\n        $write_outputs;\n        ^~~~~~~~~~~~~~\n%Error: Exiting due to 24 error(s)\n'
module sim_receiver #(parameter RTT              = -1,
                      parameter LOSS_PROB        = -1)(

    input                           clk,              
    input                           rst_n,           
   
    input   [`FLOW_SEQ_NUM_W-1:0]   next_seq_in,
    input   [`TX_CNT_W-1:0]         next_seq_tx_id_in,
    input   [`FLOW_ID_W-1:0]        next_seq_fid_in,

    output  reg [`FLOW_ID_W-1:0]    resp_fid,
    output  reg [`PKT_TYPE_W-1:0]   resp_pkt_type,
    output  reg [`PKT_DATA_W-1:0]   resp_pkt_data
);    

localparam  LINK_RTT        = RTT;
localparam  LINK_LOSS_PROB  = LOSS_PROB;

reg  [`FLOW_ID_W-1:0]       read_resp_fid;
reg  [`PKT_TYPE_W-1:0]      read_resp_pkt_type;
reg  [`PKT_DATA_W-1:0]      read_resp_pkt_data;

initial begin
    read_resp_fid       = `FLOW_ID_NONE;
    read_resp_pkt_type  = `NONE_PKT;
    read_resp_pkt_data  = {`PKT_DATA_W{1'b0}};
end

initial begin
    $init;
end

always @(posedge clk) begin
    $send_clk;
end

always @(posedge clk) begin
    if (rst_n) begin
        resp_fid        <= read_resp_fid;
        resp_pkt_type   <= read_resp_pkt_type;
        resp_pkt_data   <= read_resp_pkt_data;
    end
    else begin
        resp_fid        <= `FLOW_ID_NONE;
        resp_pkt_type   <= `NONE_PKT;
        resp_pkt_data   <= {`PKT_DATA_W{1'b0}};
    end    
end

always @(posedge clk) begin
    if (rst_n) begin
        $read_inputs;
    end
end

always @(posedge clk) begin
    if (rst_n) begin
        $write_outputs;
    end
end

`include "clogb2.vh"
endmodule
module sim_receiver #(parameter RTT              = -1,
                      parameter LOSS_PROB        = -1)(

    input                           clk,              
    input                           rst_n,           
   
    input   [`FLOW_SEQ_NUM_W-1:0]   next_seq_in,
    input   [`TX_CNT_W-1:0]         next_seq_tx_id_in,
    input   [`FLOW_ID_W-1:0]        next_seq_fid_in,

    output  reg [`FLOW_ID_W-1:0]    resp_fid,
    output  reg [`PKT_TYPE_W-1:0]   resp_pkt_type,
    output  reg [`PKT_DATA_W-1:0]   resp_pkt_data
);
    

localparam  LINK_RTT        = RTT;
localparam  LINK_LOSS_PROB  = LOSS_PROB;

reg  [`FLOW_ID_W-1:0]       read_resp_fid;
reg  [`PKT_TYPE_W-1:0]      read_resp_pkt_type;
reg  [`PKT_DATA_W-1:0]      read_resp_pkt_data;

initial begin
    read_resp_fid       = `FLOW_ID_NONE;
    read_resp_pkt_type  = `NONE_PKT;
    read_resp_pkt_data  = {`PKT_DATA_W{1'b0}};
end

initial begin
    $init;
end

always @(posedge clk) begin
    $send_clk;
end

always @(posedge clk) begin
    if (rst_n) begin
        resp_fid        <= read_resp_fid;
        resp_pkt_type   <= read_resp_pkt_type;
        resp_pkt_data   <= read_resp_pkt_data;
    end
    else begin
        resp_fid        <= `FLOW_ID_NONE;
        resp_pkt_type   <= `NONE_PKT;
        resp_pkt_data   <= {`PKT_DATA_W{1'b0}};
    end    
end

always @(posedge clk) begin
    if (rst_n) begin
        $read_inputs;
    end
end

always @(posedge clk) begin
    if (rst_n) begin
        $write_outputs;
    end
end

`include "clogb2.vh"
endmodule