data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v
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1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:12: Cannot find include file: lib/spi.v\n`include "lib/spi.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/spi.v.sv\n             lib/spi.v\n             lib/spi.v.v\n             lib/spi.v.sv\n             obj_dir/lib/spi.v\n             obj_dir/lib/spi.v.v\n             obj_dir/lib/spi.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:452: Unsupported: Ignoring delay on this delayed statement.\n   #300;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:456: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:458: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:463: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:465: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:470: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:472: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:476: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:499: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test040.spi-pollable-memory.v:503: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n'
module top (
	input clock100,
	input rpi_spi_sclk,
	input rpi_spi_mosi,
	output rpi_spi_miso,
	input rpi_spi_ce0,
	input rpi_spi_ce1,
	output pmod4_5,
	output pmod4_6,
	output pmod4_7,
	output pmod4_8,
	output led1,
	output led2,
	output led3
);
	reg reset1 = 1;
	wire clock_ram;
	wire clock_spi;
`ifdef USE_SLOW_CLOCK
	wire clock16;
	reg reset2 = 1;
	wire pll_locked;
	easypll #(.DIVR(4'd3), .DIVF(7'd40), .DIVQ(3'd6)) mp (.clock_input(clock100), .reset_active_low(~reset1), .global_clock_output(clock16), .pll_is_locked(pll_locked));
	assign clock_ram = clock16;
	assign clock_spi = clock16;
`else
	assign clock_ram = clock100;
	assign clock_spi = clock100;
`endif
	reg [7:0] reset_counter = 0;
	always @(posedge clock100) begin
		if (reset1) begin
			if (reset_counter[7]) begin
				reset1 <= 0;
			end else begin
				reset_counter <= reset_counter + 1'b1;
			end
`ifdef USE_SLOW_CLOCK
		end else if (reset2) begin
			if (pll_locked) begin
				reset2 <= 0;
			end
`endif
		end
	end







	wire [7:0] command8;
	wire [15:0] address16;
	wire [31:0] data32;


	wire [31:0] read_data32;

	wire transaction_valid;

	SPI_peripheral_command8_address16_data32 spi_c8_a16_d32 (.clock(clock_spi),
		.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(rpi_spi_miso), .SSEL(rpi_spi_ce1),
		.transaction_valid(transaction_valid), .command8(command8), .address16(address16), .data32(data32), .data32_to_controller(read_data32));
`ifdef USE_INFERRED_RAM_16
	wire [3:0] address4 = address16[3:0];
	RAM_inferred #(.addr_width(4), .data_width(32)) myram (.reset(reset1),
		.wclk(clock_ram), .waddr(address4), .din(data32), .write_en(transaction_valid),
		.rclk(clock_ram), .raddr(address4), .dout(read_data32));
`elsif USE_BRAM_256
	wire [7:0] address8 = address16[7:0];
	RAM_ice40_256_32bit myram (.reset(reset1),
		.write_clock(clock_ram), .write_address(address8), .write_data(data32), .write_enable(transaction_valid),
		.read_clock(clock_ram), .read_address(address8), .read_data(read_data32));
`elsif USE_BRAM_512
	wire [8:0] address9 = address16[8:0];
	RAM_ice40_512_32bit myram (.reset(reset1),
		.write_clock(clock_ram), .write_address(address9), .write_data(data32), .write_enable(transaction_valid),
		.read_clock(clock_ram), .read_address(address9), .read_data(read_data32));
`elsif USE_BRAM_1K
	wire [9:0] address10 = address16[9:0];
	RAM_ice40_1k_32bit myram (.reset(reset1),
		.write_clock(clock_ram), .write_address(address10), .write_data(data32), .write_enable(transaction_valid),
		.read_clock(clock_ram), .read_address(address10), .read_data(read_data32));
`elsif USE_BRAM_2K
	wire [10:0] address11 = address16[10:0];
	RAM_ice40_2k_32bit myram (.reset(reset1),
		.write_clock(clock_ram), .write_address(address11), .write_data(data32), .write_enable(transaction_valid),
		.read_clock(clock_ram), .read_address(address11), .read_data(read_data32));
`endif

















	wire [2:0] leds = { led1, led2, led3 };

	assign leds = data32[2:0];





	assign pmod4_5 = rpi_spi_sclk;
	assign pmod4_6 = rpi_spi_mosi;
	assign pmod4_7 = rpi_spi_miso;
	assign pmod4_8 = rpi_spi_ce1;
endmodule
module top (
	input clock100,
	input rpi_spi_sclk,
	input rpi_spi_mosi,
	output rpi_spi_miso,
	input rpi_spi_ce0,
	input rpi_spi_ce1,
	output pmod4_5,
	output pmod4_6,
	output pmod4_7,
	output pmod4_8,
	output led1,
	output led2,
	output led3
);

	reg reset1 = 1;
	wire clock_ram;
	wire clock_spi;
`ifdef USE_SLOW_CLOCK
	wire clock16;
	reg reset2 = 1;
	wire pll_locked;
	easypll #(.DIVR(4'd3), .DIVF(7'd40), .DIVQ(3'd6)) mp (.clock_input(clock100), .reset_active_low(~reset1), .global_clock_output(clock16), .pll_is_locked(pll_locked));
	assign clock_ram = clock16;
	assign clock_spi = clock16;
`else
	assign clock_ram = clock100;
	assign clock_spi = clock100;
`endif
	reg [7:0] reset_counter = 0;
	always @(posedge clock100) begin
		if (reset1) begin
			if (reset_counter[7]) begin
				reset1 <= 0;
			end else begin
				reset_counter <= reset_counter + 1'b1;
			end
`ifdef USE_SLOW_CLOCK
		end else if (reset2) begin
			if (pll_locked) begin
				reset2 <= 0;
			end
`endif
		end
	end







	wire [7:0] command8;
	wire [15:0] address16;
	wire [31:0] data32;


	wire [31:0] read_data32;

	wire transaction_valid;

	SPI_peripheral_command8_address16_data32 spi_c8_a16_d32 (.clock(clock_spi),
		.SCK(rpi_spi_sclk), .MOSI(rpi_spi_mosi), .MISO(rpi_spi_miso), .SSEL(rpi_spi_ce1),
		.transaction_valid(transaction_valid), .command8(command8), .address16(address16), .data32(data32), .data32_to_controller(read_data32));
`ifdef USE_INFERRED_RAM_16
	wire [3:0] address4 = address16[3:0];
	RAM_inferred #(.addr_width(4), .data_width(32)) myram (.reset(reset1),
		.wclk(clock_ram), .waddr(address4), .din(data32), .write_en(transaction_valid),
		.rclk(clock_ram), .raddr(address4), .dout(read_data32));
`elsif USE_BRAM_256
	wire [7:0] address8 = address16[7:0];
	RAM_ice40_256_32bit myram (.reset(reset1),
		.write_clock(clock_ram), .write_address(address8), .write_data(data32), .write_enable(transaction_valid),
		.read_clock(clock_ram), .read_address(address8), .read_data(read_data32));
`elsif USE_BRAM_512
	wire [8:0] address9 = address16[8:0];
	RAM_ice40_512_32bit myram (.reset(reset1),
		.write_clock(clock_ram), .write_address(address9), .write_data(data32), .write_enable(transaction_valid),
		.read_clock(clock_ram), .read_address(address9), .read_data(read_data32));
`elsif USE_BRAM_1K
	wire [9:0] address10 = address16[9:0];
	RAM_ice40_1k_32bit myram (.reset(reset1),
		.write_clock(clock_ram), .write_address(address10), .write_data(data32), .write_enable(transaction_valid),
		.read_clock(clock_ram), .read_address(address10), .read_data(read_data32));
`elsif USE_BRAM_2K
	wire [10:0] address11 = address16[10:0];
	RAM_ice40_2k_32bit myram (.reset(reset1),
		.write_clock(clock_ram), .write_address(address11), .write_data(data32), .write_enable(transaction_valid),
		.read_clock(clock_ram), .read_address(address11), .read_data(read_data32));
`endif

















	wire [2:0] leds = { led1, led2, led3 };

	assign leds = data32[2:0];





	assign pmod4_5 = rpi_spi_sclk;
	assign pmod4_6 = rpi_spi_mosi;
	assign pmod4_7 = rpi_spi_miso;
	assign pmod4_8 = rpi_spi_ce1;
endmodule