data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_wb_camera_if.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_wb_camera_if.sv:41: Cannot find include file: wb_camera_if.sv\n`include "wb_camera_if.sv" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/204736068/SoM/RTL/vision/tb,data/full_repos/permissive/204736068/wb_camera_if.sv\n             data/full_repos/permissive/204736068/SoM/RTL/vision/tb,data/full_repos/permissive/204736068/wb_camera_if.sv.v\n             data/full_repos/permissive/204736068/SoM/RTL/vision/tb,data/full_repos/permissive/204736068/wb_camera_if.sv.sv\n             wb_camera_if.sv\n             wb_camera_if.sv.v\n             wb_camera_if.sv.sv\n             obj_dir/wb_camera_if.sv\n             obj_dir/wb_camera_if.sv.v\n             obj_dir/wb_camera_if.sv.sv\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_wb_camera_if.sv:76: Cannot find include file: camera_model.sv\n    `include "camera_model.sv" \n             ^~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_wb_camera_if.sv:83: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_wb_camera_if.sv:84: Unsupported: Ignoring delay on this delayed statement.\n    always #50 pixel_clk = ~pixel_clk;\n           ^\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_wb_camera_if.sv:91: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_wb_camera_if.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_wb_camera_if.sv:92: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_wb_camera_if.sv:94: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_wb_camera_if.sv:96: syntax error, unexpected \'@\'\n        repeat (5) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_wb_camera_if.sv:101: syntax error, unexpected \'@\'\n        repeat (5) @(posedge clk);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/204736068/SoM/RTL/vision/tb/tb_wb_camera_if.sv:104: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Error: Exiting due to 6 error(s), 4 warning(s)\n'
module tb;


    parameter ROWS = 12;
    parameter COLS = 16;
    parameter ADR_WIDTH = 10;
    
    logic              clk=0;
    logic              rst;


    logic              pixel_clk=0;
    logic [7:0]        pixel_dat;
    logic              frame_vld;
    logic              line_vld;
      

    logic             m_wb_cyc;
    logic             m_wb_stb;
    logic [ADR_WIDTH-1:0]    m_wb_adr;
    logic [31:0]     m_o_wb_dat;
    logic             m_wb_we;
    logic              m_wb_ack;

    logic [$clog2(COLS):0] num_rows;
    logic [$clog2(ROWS):0] num_cols;
    logic overrun;
    

    logic [ADR_WIDTH-1:0]       wr_addr_start;        
    logic [31:0] timestamp;
        

    `include "camera_model.sv"



    wb_camera_if #(.ADR_WIDTH(ADR_WIDTH), .COLS(COLS), .ROWS(ROWS)) u_wb_camera_if (.*);
    

    always #10 clk = ~clk;
    always #50 pixel_clk = ~pixel_clk;


    assign m_wb_ack = m_wb_cyc & m_wb_stb;
    
    initial begin
        $display("Starting simulation, dumping to tb_wb_camera_if.vcd");
        $dumpfile("tb_wb_camera_if.vcd");
        $dumpvars(0, tb);
         
        #100;
        rst = 1;
        repeat (5) @(posedge clk);
        rst = 0;
        wr_addr_start= 'h1234;
        timestamp = 'hdeadbabe;
        
        repeat (5) @(posedge clk);
        send_incr_frame;
        
        #1000;
        $display("Number of rows: %d", num_rows);
        $display("Number of cols: %d", num_cols);
        $display("Ending simulation");
        
        $finish;
    end
    
endmodule
module tb;



    parameter ROWS = 12;
    parameter COLS = 16;
    parameter ADR_WIDTH = 10;
    
    logic              clk=0;
    logic              rst;


    logic              pixel_clk=0;
    logic [7:0]        pixel_dat;
    logic              frame_vld;
    logic              line_vld;
      

    logic             m_wb_cyc;
    logic             m_wb_stb;
    logic [ADR_WIDTH-1:0]    m_wb_adr;
    logic [31:0]     m_o_wb_dat;
    logic             m_wb_we;
    logic              m_wb_ack;

    logic [$clog2(COLS):0] num_rows;
    logic [$clog2(ROWS):0] num_cols;
    logic overrun;
    

    logic [ADR_WIDTH-1:0]       wr_addr_start;        
    logic [31:0] timestamp;
        

    `include "camera_model.sv"



    wb_camera_if #(.ADR_WIDTH(ADR_WIDTH), .COLS(COLS), .ROWS(ROWS)) u_wb_camera_if (.*);
    

    always #10 clk = ~clk;
    always #50 pixel_clk = ~pixel_clk;


    assign m_wb_ack = m_wb_cyc & m_wb_stb;
    
    initial begin
        $display("Starting simulation, dumping to tb_wb_camera_if.vcd");
        $dumpfile("tb_wb_camera_if.vcd");
        $dumpvars(0, tb);
         
        #100;
        rst = 1;
        repeat (5) @(posedge clk);
        rst = 0;
        wr_addr_start= 'h1234;
        timestamp = 'hdeadbabe;
        
        repeat (5) @(posedge clk);
        send_incr_frame;
        
        #1000;
        $display("Number of rows: %d", num_rows);
        $display("Number of cols: %d", num_cols);
        $display("Ending simulation");
        
        $finish;
    end
    
endmodule