data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v
1: b'%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:21: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:43: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:66: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:77: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:88: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:99: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:114: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:136: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:1: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MULTITOP: data/full_repos/permissive/148324174/HDLBits/Circuits/ShiftReg.v:122: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                       : ... Top module \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                                                                                       : ... Top module \'MUXDFF\'\nmodule MUXDFF (\n       ^~~~~~\n%Error: Exiting due to 9 warning(s)\n'
module top_module (
    input  clk,
    input  enable,
    input  S,
    input  A, B, C,
    output Z 
                   );
    reg [7:0] Q;
always @(posedge clk)begin
    if (enable) Q <= {Q[6:0], S};
    else Q <= Q;
end
always @(*)begin





case ({A, B, C})
  3'b000: Z = Q[0];
  3'b001: Z = Q[1];
  3'b010: Z = Q[2];
  3'b011: Z = Q[3];
  3'b100: Z = Q[4];
  3'b101: Z = Q[5];
  3'b110: Z = Q[6];
  3'b111: Z = Q[7];
endcase
end
endmodule
module top_module (
    input  clk,
    input  enable,
    input  S,
    input  A, B, C,
    output Z 
                   );

    reg [7:0] Q;
always @(posedge clk)begin
    if (enable) Q <= {Q[6:0], S};
    else Q <= Q;
end
always @(*)begin





case ({A, B, C})
  3'b000: Z = Q[0];
  3'b001: Z = Q[1];
  3'b010: Z = Q[2];
  3'b011: Z = Q[3];
  3'b100: Z = Q[4];
  3'b101: Z = Q[5];
  3'b110: Z = Q[6];
  3'b111: Z = Q[7];
endcase
end
endmodule