data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v
1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:21: Cannot find include file: char_def.vh\n`include "char_def.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.v\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src,data/full_repos/permissive/111502990/char_def.vh.sv\n             char_def.vh\n             char_def.vh.v\n             char_def.vh.sv\n             obj_dir/char_def.vh\n             obj_dir/char_def.vh.v\n             obj_dir/char_def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:22: Cannot find include file: state_def.vh\n`include "state_def.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:48: Define or directive not defined: \'`spi_idle\'\n    assign cs = (current_state == `spi_idle && spi_en == 1) ? 1 : 0;\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:48: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n    assign cs = (current_state == `spi_idle && spi_en == 1) ? 1 : 0;\n                                            ^~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:49: Define or directive not defined: \'`spi_done\'\n    assign spi_fin = (current_state == `spi_done) ? 1 : 0;\n                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign spi_fin = (current_state == `spi_done) ? 1 : 0;\n                                                ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:53: Define or directive not defined: \'`spi_idle\'\n            current_state <= `spi_idle;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            current_state <= `spi_idle;\n                                      ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:56: Define or directive not defined: \'`spi_idle\'\n                `spi_idle: begin\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:56: syntax error, unexpected \':\', expecting endcase\n                `spi_idle: begin\n                         ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:58: Define or directive not defined: \'`spi_send\'\n                        current_state <= `spi_send;\n                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:61: Define or directive not defined: \'`spi_send\'\n                `spi_send: begin\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:61: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `spi_send: begin\n                           ^~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:63: Define or directive not defined: \'`spi_hold1\'\n                        current_state <= `spi_hold1;\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:66: Define or directive not defined: \'`spi_hold1\'\n                `spi_hold1: begin\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:67: Define or directive not defined: \'`spi_hold2\'\n                    current_state <= `spi_hold2;\n                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:69: Define or directive not defined: \'`spi_hold2\'\n                `spi_hold2: begin\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:70: Define or directive not defined: \'`spi_hold3\'\n                    current_state <= `spi_hold3;\n                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:72: Define or directive not defined: \'`spi_hold3\'\n                `spi_hold3: begin\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:73: Define or directive not defined: \'`spi_hold4\'\n                    current_state <= `spi_hold4;\n                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:75: Define or directive not defined: \'`spi_hold4\'\n                `spi_hold4: begin\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:76: Define or directive not defined: \'`spi_done\'\n                    current_state <= `spi_done;\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:78: Define or directive not defined: \'`spi_done\'\n                `spi_done: begin\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:80: Define or directive not defined: \'`spi_idle\'\n                        current_state <= `spi_idle;\n                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:84: Define or directive not defined: \'`spi_idle\'\n                    current_state <= `spi_idle;\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:94: Define or directive not defined: \'`spi_send\'\n        else if(current_state == `spi_send) begin\n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:108: Define or directive not defined: \'`spi_idle\'\n        else if(current_state == `spi_idle) begin\n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/display_src/spi_ctrl.v:113: Define or directive not defined: \'`spi_send\'\n        else if(current_state == `spi_send) begin\n                                 ^~~~~~~~~\n%Error: Cannot continue\n'
module spi_ctrl(
    clk,
    rst,
    spi_en,
    spi_data,
    cs,
    sdo,
    sclk,
    spi_fin
    );
    input clk, rst, spi_en;
    input [7:0] spi_data;
    output cs, sdo, sclk, spi_fin;

    reg t_sdo, falling;
    reg [2:0] current_state;
    reg [7:0] shift_register;
    reg [3:0] shift_counter;
    reg [4:0] counter;

    wire clk_divided = ~counter[4];
    assign sclk = clk_divided;
    assign sdo = t_sdo;

    assign cs = (current_state == `spi_idle && spi_en == 1) ? 1 : 0;
    assign spi_fin = (current_state == `spi_done) ? 1 : 0;

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            current_state <= `spi_idle;
        end else begin
            case(current_state)
                `spi_idle: begin
                    if(spi_en) begin
                        current_state <= `spi_send;
                    end
                end
                `spi_send: begin
                    if(shift_counter == 4'b1000 && falling == 0) begin
                        current_state <= `spi_hold1;
                    end
                end
                `spi_hold1: begin
                    current_state <= `spi_hold2;
                end
                `spi_hold2: begin
                    current_state <= `spi_hold3;
                end
                `spi_hold3: begin
                    current_state <= `spi_hold4;
                end
                `spi_hold4: begin
                    current_state <= `spi_done;
                end
                `spi_done: begin
                    if(spi_en == 0) begin
                        current_state <= `spi_idle;
                    end
                end
                default: begin
                    current_state <= `spi_idle;
                end
            endcase
        end
    end

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            counter <= 5'b0;
        end
        else if(current_state == `spi_send) begin
            counter <= counter + 1;
        end
        else begin
            counter <= 5'b0;
        end
    end

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            falling <= 0;
            shift_counter <= 4'b0;
            shift_register <= 8'b0;
        end
        else if(current_state == `spi_idle) begin
            shift_counter <= 4'b0;
            shift_register <= spi_data;
            t_sdo <= 1;
        end
        else if(current_state == `spi_send) begin
            if(clk_divided == 0 && falling == 0) begin
                falling <= 1;
                t_sdo <= shift_register[7];
                shift_register <= {shift_register[6:0], 1'b0};
                shift_counter <= shift_counter + 1;
            end
            else if(clk_divided == 1) begin
                falling <= 0;
            end
        end
    end

endmodule
module spi_ctrl(
    clk,
    rst,
    spi_en,
    spi_data,
    cs,
    sdo,
    sclk,
    spi_fin
    );

    input clk, rst, spi_en;
    input [7:0] spi_data;
    output cs, sdo, sclk, spi_fin;

    reg t_sdo, falling;
    reg [2:0] current_state;
    reg [7:0] shift_register;
    reg [3:0] shift_counter;
    reg [4:0] counter;

    wire clk_divided = ~counter[4];
    assign sclk = clk_divided;
    assign sdo = t_sdo;

    assign cs = (current_state == `spi_idle && spi_en == 1) ? 1 : 0;
    assign spi_fin = (current_state == `spi_done) ? 1 : 0;

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            current_state <= `spi_idle;
        end else begin
            case(current_state)
                `spi_idle: begin
                    if(spi_en) begin
                        current_state <= `spi_send;
                    end
                end
                `spi_send: begin
                    if(shift_counter == 4'b1000 && falling == 0) begin
                        current_state <= `spi_hold1;
                    end
                end
                `spi_hold1: begin
                    current_state <= `spi_hold2;
                end
                `spi_hold2: begin
                    current_state <= `spi_hold3;
                end
                `spi_hold3: begin
                    current_state <= `spi_hold4;
                end
                `spi_hold4: begin
                    current_state <= `spi_done;
                end
                `spi_done: begin
                    if(spi_en == 0) begin
                        current_state <= `spi_idle;
                    end
                end
                default: begin
                    current_state <= `spi_idle;
                end
            endcase
        end
    end

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            counter <= 5'b0;
        end
        else if(current_state == `spi_send) begin
            counter <= counter + 1;
        end
        else begin
            counter <= 5'b0;
        end
    end

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            falling <= 0;
            shift_counter <= 4'b0;
            shift_register <= 8'b0;
        end
        else if(current_state == `spi_idle) begin
            shift_counter <= 4'b0;
            shift_register <= spi_data;
            t_sdo <= 1;
        end
        else if(current_state == `spi_send) begin
            if(clk_divided == 0 && falling == 0) begin
                falling <= 1;
                t_sdo <= shift_register[7];
                shift_register <= {shift_register[6:0], 1'b0};
                shift_counter <= shift_counter + 1;
            end
            else if(clk_divided == 1) begin
                falling <= 0;
            end
        end
    end

endmodule