data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/packages/PkgComplex.sv
 line:17: before: "package"
1: b'%Warning-UNPACKED: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/packages/PkgComplex.sv:33: Unsupported: Unpacked struct/union\n  typedef struct {\n          ^~~~~~\n                   ... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/packages/PkgComplex.sv:65: Operator ITORD expects 32 bits on the LHS, but LHS\'s VARREF \'x\' generates 16 bits.\n    return real\'(x) / (2.0**15);\n           ^~~~\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/packages/PkgComplex.sv:74: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RTOIROUNDS generates 32 bits.\n    return s16_t\'(val);\n    ^~~~~~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function sc16_t div_sc16(sc16_t x, sc16_t y);
    return complex_to_sc16(div(sc16_to_complex(x), sc16_to_complex(y)));
  endfunction
function sc16_t div_sc16(sc16_t x, sc16_t y);

    return complex_to_sc16(div(sc16_to_complex(x), sc16_to_complex(y)));
  endfunction