data/full_repos/permissive/175948336/UART/Transmitter/tx_byte.v
1: b"%Error: data/full_repos/permissive/175948336/UART/Transmitter/tx_byte.v:37: Cannot find file containing module: 'memory'\n memory m1(clk,add,out_byte);\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175948336/UART/Transmitter,data/full_repos/permissive/175948336/memory\n             data/full_repos/permissive/175948336/UART/Transmitter,data/full_repos/permissive/175948336/memory.v\n             data/full_repos/permissive/175948336/UART/Transmitter,data/full_repos/permissive/175948336/memory.sv\n             memory\n             memory.v\n             memory.sv\n             obj_dir/memory\n             obj_dir/memory.v\n             obj_dir/memory.sv\n%Error: data/full_repos/permissive/175948336/UART/Transmitter/tx_byte.v:38: Cannot find file containing module: 'baud_rate_gen'\n baud_rate_gen brg1(clk,nclk);\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module tx_byte(clk,tx,ip);
	input clk,ip;
	wire nclk;
	output reg tx;
	reg com;
	wire [7:0] t_byte;
	reg [4:0] add;
	reg [4:0] pos;
	wire [7:0] out_byte;
	reg en;
	initial begin
		add=0;
		tx=1;
		pos=0;
		com=0;
	end		
	memory m1(clk,add,out_byte);
	baud_rate_gen brg1(clk,nclk);
	always @(posedge nclk) begin
	if (add<16) begin	
		if (pos==9) begin
			tx=1;
			add=add+1;
			pos=0;
			com=0;
		end		
		else if(com==1) begin
			tx = out_byte[pos-1];	
			pos=pos+1;
		end
		else if((ip==1) && (pos==0)) begin
				com=1;
				tx=0;
				pos=pos+1;	
		end
		
	end
	else if(ip==0) begin
				pos=0;
				add=0;
	end
	end
endmodule
module tx_byte(clk,tx,ip);

	input clk,ip;
	wire nclk;
	output reg tx;
	reg com;
	wire [7:0] t_byte;
	reg [4:0] add;
	reg [4:0] pos;
	wire [7:0] out_byte;
	reg en;
	initial begin
		add=0;
		tx=1;
		pos=0;
		com=0;
	end		
	memory m1(clk,add,out_byte);
	baud_rate_gen brg1(clk,nclk);
	always @(posedge nclk) begin
	if (add<16) begin	
		if (pos==9) begin
			tx=1;
			add=add+1;
			pos=0;
			com=0;
		end		
		else if(com==1) begin
			tx = out_byte[pos-1];	
			pos=pos+1;
		end
		else if((ip==1) && (pos==0)) begin
				com=1;
				tx=0;
				pos=pos+1;	
		end
		
	end
	else if(ip==0) begin
				pos=0;
				add=0;
	end
	end
endmodule