data/full_repos/permissive/112219256/mycpu.v
1: b'%Error: data/full_repos/permissive/112219256/mycpu.v:520: syntax error, unexpected int\n    .int               (            int_i),  \n     ^~~\n%Error: Exiting due to 1 error(s)\n'
module mycpu(
    input         clk,
    input         resetn,
    input  [ 5:0] int_i,

    output        inst_req,
    output [ 1:0] inst_size,
    output [31:0] inst_addr,
    input  [31:0] inst_rdata,
    input         inst_addr_ok,
    input         inst_data_ok,
   
    output        data_req,
    output        data_wr,
   
    output [ 1:0] data_rsize,
    output [31:0] data_raddr,
    input  [31:0] data_rdata,
    input         data_raddr_ok,
    input         data_rdata_ok,
   
    output [ 1:0] data_wsize,
    output [31:0] data_waddr,
    input  [31:0] data_wdata,
    input         data_waddr_ok,
    input         data_wdata_ok

  `ifdef SIMU_DEBUG
   ,output [31:0] debug_wb_pc,
    output [ 3:0] debug_wb_rf_wen,
    output [ 4:0] debug_wb_rf_wnum,
    output [31:0] debug_wb_rf_wdata
  `endif
);





wire rst = ~resetn;

wire         JSrc;
wire [ 1:0] PCSrc;

wire [ 4:0] RegRaddr1;
wire [ 4:0] RegRaddr2;
wire [31:0] RegRdata1;
wire [31:0] RegRdata2;

wire                   DSI_ID;
wire                DSI_IF_ID;

wire [31:0]           PC_next;
wire [31:0]          PC_IF_ID;
wire [31:0]    PC_add_4_IF_ID;
wire            PC_AdEL_IF_ID;
wire                  PC_AdEL;
wire [31:0]        Inst_IF_ID;

wire                  PCWrite;
wire                  IRWrite;

wire [31:0]       J_target_ID;
wire [31:0]      JR_target_ID;
wire [31:0]      Br_target_ID;
wire [31:0]       PC_add_4_ID;

wire [ 1:0]     RegRdata1_src;
wire [ 1:0]     RegRdata2_src;

wire               is_rs_read;
wire               is_rt_read;
wire             ID_EXE_Stall;

wire [31:0]         PC_ID_EXE;
wire [31:0]   PC_add_4_ID_EXE;
wire [ 1:0]     RegDst_ID_EXE;
wire [ 1:0]    ALUSrcA_ID_EXE;
wire [ 1:0]    ALUSrcB_ID_EXE;
wire [ 3:0]      ALUop_ID_EXE;
wire [ 3:0]   RegWrite_ID_EXE;
wire [ 3:0]   MemWrite_ID_EXE;
wire         is_signed_ID_EXE;
wire             MemEn_ID_EXE;
wire          MemToReg_ID_EXE;
wire [ 1:0]       MULT_ID_EXE;
wire [ 1:0]        DIV_ID_EXE;
wire [ 1:0]       MFHL_ID_EXE;
wire [ 1:0]       MTHL_ID_EXE;
wire                LB_ID_EXE; 
wire               LBU_ID_EXE; 
wire                LH_ID_EXE; 
wire               LHU_ID_EXE; 
wire [ 1:0]         LW_ID_EXE; 
wire [ 1:0]         SW_ID_EXE; 
wire                SB_ID_EXE; 
wire                SH_ID_EXE; 

wire [ 4:0]   RegWaddr_ID_EXE;
wire [31:0]     ALUResult_EXE;
wire [31:0]     ALUResult_MEM;

wire [31:0]  RegRdata1_ID_EXE;
wire [31:0]  RegRdata2_ID_EXE;
wire [31:0]         Sa_ID_EXE;
wire [31:0]  SgnExtend_ID_EXE;
wire [31:0]    ZExtend_ID_EXE;

wire            MemEn_EXE_MEM;
wire         MemToReg_EXE_MEM;
wire [ 3:0]  MemWrite_EXE_MEM;
wire [ 3:0]  RegWrite_EXE_MEM;
wire [ 3:0]      RegWrite_EXE;
wire [ 4:0]  RegWaddr_EXE_MEM;
wire [ 1:0]      MULT_EXE_MEM;
wire [ 1:0]      MFHL_EXE_MEM;
wire [ 1:0]      MTHL_EXE_MEM;
wire               LB_EXE_MEM; 
wire              LBU_EXE_MEM; 
wire               LH_EXE_MEM; 
wire              LHU_EXE_MEM; 
wire [ 1:0]        LW_EXE_MEM; 
wire [31:0] ALUResult_EXE_MEM;
wire [31:0]  MemWdata_EXE_MEM;
wire [31:0]        PC_EXE_MEM;
wire [31:0] RegRdata1_EXE_MEM;
wire [31:0] RegRdata2_EXE_MEM;

wire          MemToReg_MEM_WB;
wire [ 3:0]   RegWrite_MEM_WB;
wire [ 4:0]   RegWaddr_MEM_WB;
wire [ 1:0]       MFHL_MEM_WB;
wire                LB_MEM_WB; 
wire               LBU_MEM_WB; 
wire                LH_MEM_WB; 
wire               LHU_MEM_WB; 
wire [ 1:0]         LW_MEM_WB; 


wire [31:0]  ALUResult_MEM_WB;
wire [31:0]  RegRdata2_MEM_WB;

wire [31:0]         PC_MEM_WB;
wire [31:0]             PC_WB;
wire [31:0]       RegWdata_WB;
wire [ 4:0]       RegWaddr_WB;
wire [ 3:0]       RegWrite_WB;

wire [31:0] RegWdata_Bypass_WB;


wire [63:0]  MULT_Result;
wire [31:0]  DIV_quotient;
wire [31:0]  DIV_remainder;
wire DIV_Busy;
wire DIV_Complete;



wire [31:0] HI_in;
wire [31:0] LO_in;
wire [ 1:0] HILO_Write;
wire [31:0] HI_out;
wire [31:0] LO_out;


wire [31:0] CP0Raddr;
wire [31:0] CP0Rdata;
wire [31:0] CP0Waddr;
wire [31:0] CP0Wdata;
wire [ 3:0] CP0Write;
wire [31:0]      epc;


wire [ 4:0] rd;
wire [31:0] RegRdata2_Final;

wire [31:0] cp0Rdata_EXE_MEM;
wire [31:0] cp0Rdata_MEM_WB;
wire           mfc0_ID_EXE;
wire           mfc0_EXE_MEM;
wire           mfc0_MEM_WB;

wire [31:0] Bypass_EXE;
wire [31:0] Bypass_MEM;


wire [31:0] Exc_BadVaddr;
wire [31:0] Exc_EPC;
wire [ 5:0] Exc_Cause;

wire ex_int_handle;
wire eret_handle;
wire [ 6:0] Exc_Vec;
wire DSI_ID_EXE,eret_ID_EXE,cp0_Write_ID_EXE,Exc_BD;
wire [ 4:0] Rd_ID_EXE;
wire [ 3:0] Exc_vec_ID_EXE;

wire PC_abnormal;

nextpc_gen nextpc_gen(
    .clk               (               clk),
    .rst               (               rst),
    .PCWrite           (           PCWrite),
    .JSrc              (              JSrc),
    .PCSrc             (             PCSrc),
    .eret              (       eret_handle),
    .epc               (               epc),
    .JR_target         (      JR_target_ID),
    .J_target          (       J_target_ID),
    .Br_addr           (      Br_target_ID),
    .inst_sram_addr    (    inst_sram_addr),
    .PC_next           (           PC_next),
    .PC_AdEL           (           PC_AdEL),
    .ex_int_handle     (     ex_int_handle),
    .PC_abnormal       (       PC_abnormal)
  );


fetch_stage fe_stage(
    .clk               (              clk),
    .rst               (              rst),
    .DSI_ID            (           DSI_ID),
    .IRWrite           (          IRWrite),
    .PC_AdEL           (          PC_AdEL),
    .PC_next           (          PC_next),
    .PC_abnormal       (      PC_abnormal),
    .inst_sram_en      (     inst_sram_en),
    .inst_sram_rdata   (  inst_sram_rdata),
    .PC_IF_ID          (         PC_IF_ID),
    .PC_add_4_IF_ID    (   PC_add_4_IF_ID),
    .Inst_IF_ID        (       Inst_IF_ID),
    .PC_AdEL_IF_ID     (    PC_AdEL_IF_ID),
    .DSI_IF_ID         (        DSI_IF_ID)
  );


decode_stage de_stage(
    .clk               (               clk),
    .rst               (               rst),
    .Inst_IF_ID        (        Inst_IF_ID),
    .PC_IF_ID          (          PC_IF_ID),
    .PC_add_4_IF_ID    (    PC_add_4_IF_ID),
    .DSI_IF_ID         (         DSI_IF_ID),
    .PC_AdEL_IF_ID     (     PC_AdEL_IF_ID),
    
    .ex_int_handle_ID  (     ex_int_handle),

    .RegRaddr1_ID      (         RegRaddr1),
    .RegRaddr2_ID      (         RegRaddr2),
    .RegRdata1_ID      (         RegRdata1),
    .RegRdata2_ID      (         RegRdata2),

    .Bypass_EXE        (        Bypass_EXE),
    .Bypass_MEM        (        Bypass_MEM),
    .RegWdata_WB       (RegWdata_Bypass_WB),
    .MULT_Result       (       MULT_Result),
    .HI                (            HI_out),
    .LO                (            LO_out),
    .MFHL_ID_EXE_1     (       MFHL_ID_EXE),
    .MFHL_EXE_MEM      (      MFHL_EXE_MEM),
    .MFHL_MEM_WB       (       MFHL_MEM_WB),
    .MULT_EXE_MEM      (      MULT_EXE_MEM),
    .RegRdata1_src     (     RegRdata1_src),
    .RegRdata2_src     (     RegRdata2_src),
    .ID_EXE_Stall      (      ID_EXE_Stall),
    .DIV_Complete      (      DIV_Complete),
    .JSrc              (              JSrc),
    .PCSrc             (             PCSrc),
    .J_target_ID       (       J_target_ID),
    .JR_target_ID      (      JR_target_ID),
    .Br_target_ID      (      Br_target_ID),

    .ALUSrcA_ID_EXE    (    ALUSrcA_ID_EXE),
    .ALUSrcB_ID_EXE    (    ALUSrcB_ID_EXE),
    .ALUop_ID_EXE      (      ALUop_ID_EXE),
    .RegWrite_ID_EXE   (   RegWrite_ID_EXE),
    .MemWrite_ID_EXE   (   MemWrite_ID_EXE),
    .MemEn_ID_EXE      (      MemEn_ID_EXE),
    .MemToReg_ID_EXE   (   MemToReg_ID_EXE),
    .is_signed_ID_EXE  (  is_signed_ID_EXE),
    .MULT_ID_EXE       (       MULT_ID_EXE),
    .DIV_ID_EXE        (        DIV_ID_EXE),
    .MFHL_ID_EXE       (       MFHL_ID_EXE),
    .MTHL_ID_EXE       (       MTHL_ID_EXE),
    .LB_ID_EXE         (         LB_ID_EXE),
    .LBU_ID_EXE        (        LBU_ID_EXE),
    .LH_ID_EXE         (         LH_ID_EXE),
    .LHU_ID_EXE        (        LHU_ID_EXE),
    .LW_ID_EXE         (         LW_ID_EXE),
    .SW_ID_EXE         (         SW_ID_EXE),
    .SB_ID_EXE         (         SB_ID_EXE),
    .SH_ID_EXE         (         SH_ID_EXE),
    .DSI_ID_EXE        (        DSI_ID_EXE),
    .eret_ID_EXE       (       eret_ID_EXE),
    .Rd_ID_EXE         (         Rd_ID_EXE),
    .Exc_vec_ID_EXE    (    Exc_vec_ID_EXE),
    .RegWaddr_ID_EXE   (   RegWaddr_ID_EXE),
    .PC_add_4_ID_EXE   (   PC_add_4_ID_EXE),
    .PC_ID_EXE         (         PC_ID_EXE),
    .RegRdata1_ID_EXE  (  RegRdata1_ID_EXE),
    .RegRdata2_ID_EXE  (  RegRdata2_ID_EXE),
    .Sa_ID_EXE         (         Sa_ID_EXE),
    .SgnExtend_ID_EXE  (  SgnExtend_ID_EXE),
    .ZExtend_ID_EXE    (    ZExtend_ID_EXE),
    .cp0_Write_ID_EXE  (  cp0_Write_ID_EXE),
    .mfc0_ID_EXE       (       mfc0_ID_EXE),

    .is_rs_read_ID     (        is_rs_read),
    .is_rt_read_ID     (        is_rt_read),

    .is_j_or_br_ID     (            DSI_ID)
  );


execute_stage exe_stage(
    .clk               (              clk),
    .rst               (              rst),
    .PC_add_4_ID_EXE   (  PC_add_4_ID_EXE),
    .cp0_Write_ID_EXE  ( cp0_Write_ID_EXE),
    .PC_ID_EXE         (        PC_ID_EXE),
    .RegRdata1_ID_EXE  ( RegRdata1_ID_EXE),
    .RegRdata2_ID_EXE  ( RegRdata2_ID_EXE),
    .Sa_ID_EXE         (        Sa_ID_EXE),
    .SgnExtend_ID_EXE  ( SgnExtend_ID_EXE),
    .ZExtend_ID_EXE    (   ZExtend_ID_EXE),
    .RegWaddr_ID_EXE   (  RegWaddr_ID_EXE),
    .MemEn_ID_EXE      (     MemEn_ID_EXE),
    .MemToReg_ID_EXE   (  MemToReg_ID_EXE),
    .is_signed_ID_EXE  ( is_signed_ID_EXE),
    .DSI_ID_EXE        (       DSI_ID_EXE),
    .Rd_ID_EXE         (        Rd_ID_EXE),
    .Exc_vec_ID_EXE    (   Exc_vec_ID_EXE),
    .ALUSrcA_ID_EXE    (   ALUSrcA_ID_EXE),
    .ALUSrcB_ID_EXE    (   ALUSrcB_ID_EXE),
    .ALUop_ID_EXE      (     ALUop_ID_EXE),
    .MemWrite_ID_EXE   (  MemWrite_ID_EXE),
    .RegWrite_ID_EXE   (  RegWrite_ID_EXE),
    .MULT_ID_EXE       (      MULT_ID_EXE),
    .MFHL_ID_EXE       (      MFHL_ID_EXE),
    .MTHL_ID_EXE       (      MTHL_ID_EXE),
    .LB_ID_EXE         (        LB_ID_EXE),
    .LBU_ID_EXE        (       LBU_ID_EXE),
    .LH_ID_EXE         (        LH_ID_EXE),
    .LHU_ID_EXE        (       LHU_ID_EXE),
    .LW_ID_EXE         (        LW_ID_EXE),
    .SW_ID_EXE         (        SW_ID_EXE),
    .SB_ID_EXE         (        SB_ID_EXE),
    .SH_ID_EXE         (        SH_ID_EXE),
    .MemEn_EXE_MEM     (    MemEn_EXE_MEM),
    .MemToReg_EXE_MEM  ( MemToReg_EXE_MEM),
    .MemWrite_EXE_MEM  ( MemWrite_EXE_MEM),
    .RegWrite_EXE_MEM  ( RegWrite_EXE_MEM),
    .MULT_EXE_MEM      (     MULT_EXE_MEM),
    .MFHL_EXE_MEM      (     MFHL_EXE_MEM),
    .MTHL_EXE_MEM      (     MTHL_EXE_MEM),
    .LB_EXE_MEM        (       LB_EXE_MEM),
    .LBU_EXE_MEM       (      LBU_EXE_MEM),
    .LH_EXE_MEM        (       LH_EXE_MEM),
    .LHU_EXE_MEM       (      LHU_EXE_MEM),
    .LW_EXE_MEM        (       LW_EXE_MEM),
    .RegWaddr_EXE_MEM  ( RegWaddr_EXE_MEM),
    .ALUResult_EXE_MEM (ALUResult_EXE_MEM),
    .MemWdata_EXE_MEM  ( MemWdata_EXE_MEM),
    .PC_EXE_MEM        (       PC_EXE_MEM),
    .RegRdata1_EXE_MEM (RegRdata1_EXE_MEM),
    .RegRdata2_EXE_MEM (RegRdata2_EXE_MEM),
    .Bypass_EXE        (       Bypass_EXE),

    .cp0Rdata_EXE      (         CP0Rdata),
    .mfc0_ID_EXE       (      mfc0_ID_EXE),
    .mfc0_EXE_MEM      (     mfc0_EXE_MEM),
    .cp0Rdata_EXE_MEM  ( cp0Rdata_EXE_MEM),

    .Exc_BadVaddr      (     Exc_BadVaddr),
    .Exc_EPC           (          Exc_EPC),
    .Exc_Vec           (          Exc_Vec),
    .Exc_BD            (          Exc_BD ),
    
    .ex_int_handle     (    ex_int_handle)
    );


memory_stage mem_stage(
    .clk               (              clk),
    .rst               (              rst),
    .MemEn_EXE_MEM     (    MemEn_EXE_MEM),
    .MemToReg_EXE_MEM  ( MemToReg_EXE_MEM),
    .MemWrite_EXE_MEM  ( MemWrite_EXE_MEM),
    .RegWrite_EXE_MEM  ( RegWrite_EXE_MEM),
    .RegWaddr_EXE_MEM  ( RegWaddr_EXE_MEM),
    .ALUResult_EXE_MEM (ALUResult_EXE_MEM),
    .MemWdata_EXE_MEM  ( MemWdata_EXE_MEM),
    .RegRdata2_EXE_MEM (RegRdata2_EXE_MEM),
    .PC_EXE_MEM        (       PC_EXE_MEM),
    .MFHL_EXE_MEM      (     MFHL_EXE_MEM),
    .LB_EXE_MEM        (       LB_EXE_MEM),
    .LBU_EXE_MEM       (      LBU_EXE_MEM),
    .LH_EXE_MEM        (       LH_EXE_MEM),
    .LHU_EXE_MEM       (      LHU_EXE_MEM),
    .LW_EXE_MEM        (       LW_EXE_MEM),
    .MemEn_MEM         (     data_sram_en),
    .MemWrite_MEM      (    data_sram_wen),
    .data_sram_addr    (   data_sram_addr),

    .MemWdata_MEM      (  data_sram_wdata),
    .MemToReg_MEM_WB   (  MemToReg_MEM_WB),
    .RegWrite_MEM_WB   (  RegWrite_MEM_WB),
    .LB_MEM_WB         (        LB_MEM_WB),
    .LBU_MEM_WB        (       LBU_MEM_WB),
    .LH_MEM_WB         (        LH_MEM_WB),
    .LHU_MEM_WB        (       LHU_MEM_WB),
    .LW_MEM_WB         (        LW_MEM_WB),
    .RegWaddr_MEM_WB   (  RegWaddr_MEM_WB),
    .ALUResult_MEM_WB  ( ALUResult_MEM_WB),
    .RegRdata2_MEM_WB  ( RegRdata2_MEM_WB),
    .PC_MEM_WB         (        PC_MEM_WB),
    .MFHL_MEM_WB       (      MFHL_MEM_WB),

    .Bypass_MEM        (       Bypass_MEM),
    
    .cp0Rdata_MEM_WB   (  cp0Rdata_MEM_WB),
    .mfc0_MEM_WB       (      mfc0_MEM_WB),
    .mfc0_EXE_MEM      (     mfc0_EXE_MEM),
    .cp0Rdata_EXE_MEM  ( cp0Rdata_EXE_MEM)
  );


writeback_stage wb_stage(
    .clk               (              clk),
    .rst               (              rst),
    .MemToReg_MEM_WB   (  MemToReg_MEM_WB),
    .RegWrite_MEM_WB   (  RegWrite_MEM_WB),
    .MFHL_MEM_WB       (      MFHL_MEM_WB),
    .LB_MEM_WB         (        LB_MEM_WB),
    .LBU_MEM_WB        (       LBU_MEM_WB),
    .LH_MEM_WB         (        LH_MEM_WB),
    .LHU_MEM_WB        (       LHU_MEM_WB),
    .LW_MEM_WB         (        LW_MEM_WB),
    .RegWaddr_MEM_WB   (  RegWaddr_MEM_WB),
    .ALUResult_MEM_WB  ( ALUResult_MEM_WB),
    .RegRdata2_MEM_WB  ( RegRdata2_MEM_WB),
    .MemRdata_MEM_WB   (  data_sram_rdata),
    .PC_MEM_WB         (        PC_MEM_WB),
    .HI_MEM_WB         (           HI_out),
    .LO_MEM_WB         (           LO_out),
    .RegWdata_WB       (      RegWdata_WB),
    .RegWdata_Bypass_WB(RegWdata_Bypass_WB),
    .RegWaddr_WB       (      RegWaddr_WB),
    .RegWrite_WB       (      RegWrite_WB),
    .PC_WB             (            PC_WB),
    
    .cp0Rdata_MEM_WB   (  cp0Rdata_MEM_WB),
    .mfc0_MEM_WB       (      mfc0_MEM_WB)
);

Bypass_Unit bypass_unit(
    .clk                (              clk),
    .rst                (              rst),

    .is_rs_read         (       is_rs_read),
    .is_rt_read         (       is_rt_read),

    .MemToReg_ID_EXE    (  MemToReg_ID_EXE),
    .MemToReg_EXE_MEM   ( MemToReg_EXE_MEM),
    .MemToReg_MEM_WB    (  MemToReg_MEM_WB),

    .RegWaddr_EXE_MEM   ( RegWaddr_EXE_MEM),
    .RegWaddr_MEM_WB    (  RegWaddr_MEM_WB),
    .RegWaddr_ID_EXE    (  RegWaddr_ID_EXE),

    .rs_ID              (Inst_IF_ID[25:21]),
    .rt_ID              (Inst_IF_ID[20:16]),

    .RegWrite_ID_EXE    (  RegWrite_ID_EXE),
    .RegWrite_EXE_MEM   ( RegWrite_EXE_MEM),
    .RegWrite_MEM_WB    (  RegWrite_MEM_WB),
    
    .DIV_Busy           (         DIV_Busy),
    .DIV                (      |DIV_ID_EXE),
    
    .ex_int_handle      (    ex_int_handle),

    .PCWrite            (          PCWrite),
    .IRWrite            (          IRWrite),
    .ID_EXE_Stall       (     ID_EXE_Stall),

    .RegRdata1_src      (    RegRdata1_src),
    .RegRdata2_src      (    RegRdata2_src)
);

reg_file RegFile(
    .clk               (              clk),
    .rst               (              rst),
    .waddr             (      RegWaddr_WB),
    .raddr1            (        RegRaddr1),
    .raddr2            (        RegRaddr2),
    .wen               (      RegWrite_WB),
    .wdata             (      RegWdata_WB),
    .rdata1            (        RegRdata1),
    .rdata2            (        RegRdata2)
);

cp0reg cp0(
    .clk               (              clk),
    .rst               (              rst),
    .eret              (      eret_ID_EXE),
    .int               (            int_i),
    .Exc_BD            (           Exc_BD),
    .Exc_Vec           (          Exc_Vec),
    .waddr             (         CP0Waddr),
    .raddr             (         CP0Raddr),
    .wen               ( cp0_Write_ID_EXE),
    .wdata             (         CP0Wdata),
    .epc_in            (          Exc_EPC),
    .Exc_BadVaddr      (     Exc_BadVaddr),
    .rdata             (         CP0Rdata),
    .epc_value         (              epc),
    .ex_int_handle     (    ex_int_handle),
    .eret_handle       (      eret_handle)

);

multiplyer mul(
    .x          (              RegRdata1_ID_EXE),
    .y          (              RegRdata2_ID_EXE),
    .mul_clk    (                           clk),
    .resetn     (                        resetn),
    .clken      (                  |MULT_ID_EXE),
    .mul_signed (MULT_ID_EXE[0]&~MULT_ID_EXE[1]),
    .result     (                   MULT_Result)
);

divider div(
    .div_clk    (                           clk),
    .rst        (                           rst),
    .x          (              RegRdata1_ID_EXE),
    .y          (              RegRdata2_ID_EXE),
    .div        (                   |DIV_ID_EXE),
    .div_signed (  DIV_ID_EXE[0]&~DIV_ID_EXE[1]),
    .s          (                  DIV_quotient),
    .r          (                 DIV_remainder),
    .busy       (                      DIV_Busy),
    .complete   (                  DIV_Complete)
);

HILO HILO(
    .clk        (                           clk),
    .rst        (                           rst),
    .HI_in      (                         HI_in),
    .LO_in      (                         LO_in),
    .HILO_Write (                    HILO_Write),
    .HI_out     (                        HI_out),
    .LO_out     (                        LO_out)
);


assign HI_in = |MULT_EXE_MEM    ? MULT_Result[63:32] :
                MTHL_EXE_MEM[1] ? RegRdata1_EXE_MEM  :
                DIV_Complete    ? DIV_remainder      : 'd0;
assign LO_in = |MULT_EXE_MEM    ? MULT_Result[31: 0] :
                MTHL_EXE_MEM[0] ? RegRdata1_EXE_MEM  :
                DIV_Complete    ? DIV_quotient       : 'd0;
assign HILO_Write[1] = |MULT_EXE_MEM | DIV_Complete | MTHL_EXE_MEM[1];
assign HILO_Write[0] = |MULT_EXE_MEM | DIV_Complete | MTHL_EXE_MEM[0];

assign CP0Waddr = Rd_ID_EXE;
assign CP0Wdata = RegRdata2_ID_EXE;
assign CP0Raddr = Rd_ID_EXE;



`ifdef SIMU_DEBUG
assign debug_wb_pc       = PC_WB;
assign debug_wb_rf_wen   = RegWrite_WB;
assign debug_wb_rf_wnum  = RegWaddr_WB;
assign debug_wb_rf_wdata = RegWdata_WB;
`endif

endmodule
module mycpu(
    input         clk,
    input         resetn,
    input  [ 5:0] int_i,

    output        inst_req,
    output [ 1:0] inst_size,
    output [31:0] inst_addr,
    input  [31:0] inst_rdata,
    input         inst_addr_ok,
    input         inst_data_ok,
   
    output        data_req,
    output        data_wr,
   
    output [ 1:0] data_rsize,
    output [31:0] data_raddr,
    input  [31:0] data_rdata,
    input         data_raddr_ok,
    input         data_rdata_ok,
   
    output [ 1:0] data_wsize,
    output [31:0] data_waddr,
    input  [31:0] data_wdata,
    input         data_waddr_ok,
    input         data_wdata_ok

  `ifdef SIMU_DEBUG
   ,output [31:0] debug_wb_pc,
    output [ 3:0] debug_wb_rf_wen,
    output [ 4:0] debug_wb_rf_wnum,
    output [31:0] debug_wb_rf_wdata
  `endif
);






wire rst = ~resetn;

wire         JSrc;
wire [ 1:0] PCSrc;

wire [ 4:0] RegRaddr1;
wire [ 4:0] RegRaddr2;
wire [31:0] RegRdata1;
wire [31:0] RegRdata2;

wire                   DSI_ID;
wire                DSI_IF_ID;

wire [31:0]           PC_next;
wire [31:0]          PC_IF_ID;
wire [31:0]    PC_add_4_IF_ID;
wire            PC_AdEL_IF_ID;
wire                  PC_AdEL;
wire [31:0]        Inst_IF_ID;

wire                  PCWrite;
wire                  IRWrite;

wire [31:0]       J_target_ID;
wire [31:0]      JR_target_ID;
wire [31:0]      Br_target_ID;
wire [31:0]       PC_add_4_ID;

wire [ 1:0]     RegRdata1_src;
wire [ 1:0]     RegRdata2_src;

wire               is_rs_read;
wire               is_rt_read;
wire             ID_EXE_Stall;

wire [31:0]         PC_ID_EXE;
wire [31:0]   PC_add_4_ID_EXE;
wire [ 1:0]     RegDst_ID_EXE;
wire [ 1:0]    ALUSrcA_ID_EXE;
wire [ 1:0]    ALUSrcB_ID_EXE;
wire [ 3:0]      ALUop_ID_EXE;
wire [ 3:0]   RegWrite_ID_EXE;
wire [ 3:0]   MemWrite_ID_EXE;
wire         is_signed_ID_EXE;
wire             MemEn_ID_EXE;
wire          MemToReg_ID_EXE;
wire [ 1:0]       MULT_ID_EXE;
wire [ 1:0]        DIV_ID_EXE;
wire [ 1:0]       MFHL_ID_EXE;
wire [ 1:0]       MTHL_ID_EXE;
wire                LB_ID_EXE; 
wire               LBU_ID_EXE; 
wire                LH_ID_EXE; 
wire               LHU_ID_EXE; 
wire [ 1:0]         LW_ID_EXE; 
wire [ 1:0]         SW_ID_EXE; 
wire                SB_ID_EXE; 
wire                SH_ID_EXE; 

wire [ 4:0]   RegWaddr_ID_EXE;
wire [31:0]     ALUResult_EXE;
wire [31:0]     ALUResult_MEM;

wire [31:0]  RegRdata1_ID_EXE;
wire [31:0]  RegRdata2_ID_EXE;
wire [31:0]         Sa_ID_EXE;
wire [31:0]  SgnExtend_ID_EXE;
wire [31:0]    ZExtend_ID_EXE;

wire            MemEn_EXE_MEM;
wire         MemToReg_EXE_MEM;
wire [ 3:0]  MemWrite_EXE_MEM;
wire [ 3:0]  RegWrite_EXE_MEM;
wire [ 3:0]      RegWrite_EXE;
wire [ 4:0]  RegWaddr_EXE_MEM;
wire [ 1:0]      MULT_EXE_MEM;
wire [ 1:0]      MFHL_EXE_MEM;
wire [ 1:0]      MTHL_EXE_MEM;
wire               LB_EXE_MEM; 
wire              LBU_EXE_MEM; 
wire               LH_EXE_MEM; 
wire              LHU_EXE_MEM; 
wire [ 1:0]        LW_EXE_MEM; 
wire [31:0] ALUResult_EXE_MEM;
wire [31:0]  MemWdata_EXE_MEM;
wire [31:0]        PC_EXE_MEM;
wire [31:0] RegRdata1_EXE_MEM;
wire [31:0] RegRdata2_EXE_MEM;

wire          MemToReg_MEM_WB;
wire [ 3:0]   RegWrite_MEM_WB;
wire [ 4:0]   RegWaddr_MEM_WB;
wire [ 1:0]       MFHL_MEM_WB;
wire                LB_MEM_WB; 
wire               LBU_MEM_WB; 
wire                LH_MEM_WB; 
wire               LHU_MEM_WB; 
wire [ 1:0]         LW_MEM_WB; 


wire [31:0]  ALUResult_MEM_WB;
wire [31:0]  RegRdata2_MEM_WB;

wire [31:0]         PC_MEM_WB;
wire [31:0]             PC_WB;
wire [31:0]       RegWdata_WB;
wire [ 4:0]       RegWaddr_WB;
wire [ 3:0]       RegWrite_WB;

wire [31:0] RegWdata_Bypass_WB;


wire [63:0]  MULT_Result;
wire [31:0]  DIV_quotient;
wire [31:0]  DIV_remainder;
wire DIV_Busy;
wire DIV_Complete;



wire [31:0] HI_in;
wire [31:0] LO_in;
wire [ 1:0] HILO_Write;
wire [31:0] HI_out;
wire [31:0] LO_out;


wire [31:0] CP0Raddr;
wire [31:0] CP0Rdata;
wire [31:0] CP0Waddr;
wire [31:0] CP0Wdata;
wire [ 3:0] CP0Write;
wire [31:0]      epc;


wire [ 4:0] rd;
wire [31:0] RegRdata2_Final;

wire [31:0] cp0Rdata_EXE_MEM;
wire [31:0] cp0Rdata_MEM_WB;
wire           mfc0_ID_EXE;
wire           mfc0_EXE_MEM;
wire           mfc0_MEM_WB;

wire [31:0] Bypass_EXE;
wire [31:0] Bypass_MEM;


wire [31:0] Exc_BadVaddr;
wire [31:0] Exc_EPC;
wire [ 5:0] Exc_Cause;

wire ex_int_handle;
wire eret_handle;
wire [ 6:0] Exc_Vec;
wire DSI_ID_EXE,eret_ID_EXE,cp0_Write_ID_EXE,Exc_BD;
wire [ 4:0] Rd_ID_EXE;
wire [ 3:0] Exc_vec_ID_EXE;

wire PC_abnormal;

nextpc_gen nextpc_gen(
    .clk               (               clk),
    .rst               (               rst),
    .PCWrite           (           PCWrite),
    .JSrc              (              JSrc),
    .PCSrc             (             PCSrc),
    .eret              (       eret_handle),
    .epc               (               epc),
    .JR_target         (      JR_target_ID),
    .J_target          (       J_target_ID),
    .Br_addr           (      Br_target_ID),
    .inst_sram_addr    (    inst_sram_addr),
    .PC_next           (           PC_next),
    .PC_AdEL           (           PC_AdEL),
    .ex_int_handle     (     ex_int_handle),
    .PC_abnormal       (       PC_abnormal)
  );


fetch_stage fe_stage(
    .clk               (              clk),
    .rst               (              rst),
    .DSI_ID            (           DSI_ID),
    .IRWrite           (          IRWrite),
    .PC_AdEL           (          PC_AdEL),
    .PC_next           (          PC_next),
    .PC_abnormal       (      PC_abnormal),
    .inst_sram_en      (     inst_sram_en),
    .inst_sram_rdata   (  inst_sram_rdata),
    .PC_IF_ID          (         PC_IF_ID),
    .PC_add_4_IF_ID    (   PC_add_4_IF_ID),
    .Inst_IF_ID        (       Inst_IF_ID),
    .PC_AdEL_IF_ID     (    PC_AdEL_IF_ID),
    .DSI_IF_ID         (        DSI_IF_ID)
  );


decode_stage de_stage(
    .clk               (               clk),
    .rst               (               rst),
    .Inst_IF_ID        (        Inst_IF_ID),
    .PC_IF_ID          (          PC_IF_ID),
    .PC_add_4_IF_ID    (    PC_add_4_IF_ID),
    .DSI_IF_ID         (         DSI_IF_ID),
    .PC_AdEL_IF_ID     (     PC_AdEL_IF_ID),
    
    .ex_int_handle_ID  (     ex_int_handle),

    .RegRaddr1_ID      (         RegRaddr1),
    .RegRaddr2_ID      (         RegRaddr2),
    .RegRdata1_ID      (         RegRdata1),
    .RegRdata2_ID      (         RegRdata2),

    .Bypass_EXE        (        Bypass_EXE),
    .Bypass_MEM        (        Bypass_MEM),
    .RegWdata_WB       (RegWdata_Bypass_WB),
    .MULT_Result       (       MULT_Result),
    .HI                (            HI_out),
    .LO                (            LO_out),
    .MFHL_ID_EXE_1     (       MFHL_ID_EXE),
    .MFHL_EXE_MEM      (      MFHL_EXE_MEM),
    .MFHL_MEM_WB       (       MFHL_MEM_WB),
    .MULT_EXE_MEM      (      MULT_EXE_MEM),
    .RegRdata1_src     (     RegRdata1_src),
    .RegRdata2_src     (     RegRdata2_src),
    .ID_EXE_Stall      (      ID_EXE_Stall),
    .DIV_Complete      (      DIV_Complete),
    .JSrc              (              JSrc),
    .PCSrc             (             PCSrc),
    .J_target_ID       (       J_target_ID),
    .JR_target_ID      (      JR_target_ID),
    .Br_target_ID      (      Br_target_ID),

    .ALUSrcA_ID_EXE    (    ALUSrcA_ID_EXE),
    .ALUSrcB_ID_EXE    (    ALUSrcB_ID_EXE),
    .ALUop_ID_EXE      (      ALUop_ID_EXE),
    .RegWrite_ID_EXE   (   RegWrite_ID_EXE),
    .MemWrite_ID_EXE   (   MemWrite_ID_EXE),
    .MemEn_ID_EXE      (      MemEn_ID_EXE),
    .MemToReg_ID_EXE   (   MemToReg_ID_EXE),
    .is_signed_ID_EXE  (  is_signed_ID_EXE),
    .MULT_ID_EXE       (       MULT_ID_EXE),
    .DIV_ID_EXE        (        DIV_ID_EXE),
    .MFHL_ID_EXE       (       MFHL_ID_EXE),
    .MTHL_ID_EXE       (       MTHL_ID_EXE),
    .LB_ID_EXE         (         LB_ID_EXE),
    .LBU_ID_EXE        (        LBU_ID_EXE),
    .LH_ID_EXE         (         LH_ID_EXE),
    .LHU_ID_EXE        (        LHU_ID_EXE),
    .LW_ID_EXE         (         LW_ID_EXE),
    .SW_ID_EXE         (         SW_ID_EXE),
    .SB_ID_EXE         (         SB_ID_EXE),
    .SH_ID_EXE         (         SH_ID_EXE),
    .DSI_ID_EXE        (        DSI_ID_EXE),
    .eret_ID_EXE       (       eret_ID_EXE),
    .Rd_ID_EXE         (         Rd_ID_EXE),
    .Exc_vec_ID_EXE    (    Exc_vec_ID_EXE),
    .RegWaddr_ID_EXE   (   RegWaddr_ID_EXE),
    .PC_add_4_ID_EXE   (   PC_add_4_ID_EXE),
    .PC_ID_EXE         (         PC_ID_EXE),
    .RegRdata1_ID_EXE  (  RegRdata1_ID_EXE),
    .RegRdata2_ID_EXE  (  RegRdata2_ID_EXE),
    .Sa_ID_EXE         (         Sa_ID_EXE),
    .SgnExtend_ID_EXE  (  SgnExtend_ID_EXE),
    .ZExtend_ID_EXE    (    ZExtend_ID_EXE),
    .cp0_Write_ID_EXE  (  cp0_Write_ID_EXE),
    .mfc0_ID_EXE       (       mfc0_ID_EXE),

    .is_rs_read_ID     (        is_rs_read),
    .is_rt_read_ID     (        is_rt_read),

    .is_j_or_br_ID     (            DSI_ID)
  );


execute_stage exe_stage(
    .clk               (              clk),
    .rst               (              rst),
    .PC_add_4_ID_EXE   (  PC_add_4_ID_EXE),
    .cp0_Write_ID_EXE  ( cp0_Write_ID_EXE),
    .PC_ID_EXE         (        PC_ID_EXE),
    .RegRdata1_ID_EXE  ( RegRdata1_ID_EXE),
    .RegRdata2_ID_EXE  ( RegRdata2_ID_EXE),
    .Sa_ID_EXE         (        Sa_ID_EXE),
    .SgnExtend_ID_EXE  ( SgnExtend_ID_EXE),
    .ZExtend_ID_EXE    (   ZExtend_ID_EXE),
    .RegWaddr_ID_EXE   (  RegWaddr_ID_EXE),
    .MemEn_ID_EXE      (     MemEn_ID_EXE),
    .MemToReg_ID_EXE   (  MemToReg_ID_EXE),
    .is_signed_ID_EXE  ( is_signed_ID_EXE),
    .DSI_ID_EXE        (       DSI_ID_EXE),
    .Rd_ID_EXE         (        Rd_ID_EXE),
    .Exc_vec_ID_EXE    (   Exc_vec_ID_EXE),
    .ALUSrcA_ID_EXE    (   ALUSrcA_ID_EXE),
    .ALUSrcB_ID_EXE    (   ALUSrcB_ID_EXE),
    .ALUop_ID_EXE      (     ALUop_ID_EXE),
    .MemWrite_ID_EXE   (  MemWrite_ID_EXE),
    .RegWrite_ID_EXE   (  RegWrite_ID_EXE),
    .MULT_ID_EXE       (      MULT_ID_EXE),
    .MFHL_ID_EXE       (      MFHL_ID_EXE),
    .MTHL_ID_EXE       (      MTHL_ID_EXE),
    .LB_ID_EXE         (        LB_ID_EXE),
    .LBU_ID_EXE        (       LBU_ID_EXE),
    .LH_ID_EXE         (        LH_ID_EXE),
    .LHU_ID_EXE        (       LHU_ID_EXE),
    .LW_ID_EXE         (        LW_ID_EXE),
    .SW_ID_EXE         (        SW_ID_EXE),
    .SB_ID_EXE         (        SB_ID_EXE),
    .SH_ID_EXE         (        SH_ID_EXE),
    .MemEn_EXE_MEM     (    MemEn_EXE_MEM),
    .MemToReg_EXE_MEM  ( MemToReg_EXE_MEM),
    .MemWrite_EXE_MEM  ( MemWrite_EXE_MEM),
    .RegWrite_EXE_MEM  ( RegWrite_EXE_MEM),
    .MULT_EXE_MEM      (     MULT_EXE_MEM),
    .MFHL_EXE_MEM      (     MFHL_EXE_MEM),
    .MTHL_EXE_MEM      (     MTHL_EXE_MEM),
    .LB_EXE_MEM        (       LB_EXE_MEM),
    .LBU_EXE_MEM       (      LBU_EXE_MEM),
    .LH_EXE_MEM        (       LH_EXE_MEM),
    .LHU_EXE_MEM       (      LHU_EXE_MEM),
    .LW_EXE_MEM        (       LW_EXE_MEM),
    .RegWaddr_EXE_MEM  ( RegWaddr_EXE_MEM),
    .ALUResult_EXE_MEM (ALUResult_EXE_MEM),
    .MemWdata_EXE_MEM  ( MemWdata_EXE_MEM),
    .PC_EXE_MEM        (       PC_EXE_MEM),
    .RegRdata1_EXE_MEM (RegRdata1_EXE_MEM),
    .RegRdata2_EXE_MEM (RegRdata2_EXE_MEM),
    .Bypass_EXE        (       Bypass_EXE),

    .cp0Rdata_EXE      (         CP0Rdata),
    .mfc0_ID_EXE       (      mfc0_ID_EXE),
    .mfc0_EXE_MEM      (     mfc0_EXE_MEM),
    .cp0Rdata_EXE_MEM  ( cp0Rdata_EXE_MEM),

    .Exc_BadVaddr      (     Exc_BadVaddr),
    .Exc_EPC           (          Exc_EPC),
    .Exc_Vec           (          Exc_Vec),
    .Exc_BD            (          Exc_BD ),
    
    .ex_int_handle     (    ex_int_handle)
    );


memory_stage mem_stage(
    .clk               (              clk),
    .rst               (              rst),
    .MemEn_EXE_MEM     (    MemEn_EXE_MEM),
    .MemToReg_EXE_MEM  ( MemToReg_EXE_MEM),
    .MemWrite_EXE_MEM  ( MemWrite_EXE_MEM),
    .RegWrite_EXE_MEM  ( RegWrite_EXE_MEM),
    .RegWaddr_EXE_MEM  ( RegWaddr_EXE_MEM),
    .ALUResult_EXE_MEM (ALUResult_EXE_MEM),
    .MemWdata_EXE_MEM  ( MemWdata_EXE_MEM),
    .RegRdata2_EXE_MEM (RegRdata2_EXE_MEM),
    .PC_EXE_MEM        (       PC_EXE_MEM),
    .MFHL_EXE_MEM      (     MFHL_EXE_MEM),
    .LB_EXE_MEM        (       LB_EXE_MEM),
    .LBU_EXE_MEM       (      LBU_EXE_MEM),
    .LH_EXE_MEM        (       LH_EXE_MEM),
    .LHU_EXE_MEM       (      LHU_EXE_MEM),
    .LW_EXE_MEM        (       LW_EXE_MEM),
    .MemEn_MEM         (     data_sram_en),
    .MemWrite_MEM      (    data_sram_wen),
    .data_sram_addr    (   data_sram_addr),

    .MemWdata_MEM      (  data_sram_wdata),
    .MemToReg_MEM_WB   (  MemToReg_MEM_WB),
    .RegWrite_MEM_WB   (  RegWrite_MEM_WB),
    .LB_MEM_WB         (        LB_MEM_WB),
    .LBU_MEM_WB        (       LBU_MEM_WB),
    .LH_MEM_WB         (        LH_MEM_WB),
    .LHU_MEM_WB        (       LHU_MEM_WB),
    .LW_MEM_WB         (        LW_MEM_WB),
    .RegWaddr_MEM_WB   (  RegWaddr_MEM_WB),
    .ALUResult_MEM_WB  ( ALUResult_MEM_WB),
    .RegRdata2_MEM_WB  ( RegRdata2_MEM_WB),
    .PC_MEM_WB         (        PC_MEM_WB),
    .MFHL_MEM_WB       (      MFHL_MEM_WB),

    .Bypass_MEM        (       Bypass_MEM),
    
    .cp0Rdata_MEM_WB   (  cp0Rdata_MEM_WB),
    .mfc0_MEM_WB       (      mfc0_MEM_WB),
    .mfc0_EXE_MEM      (     mfc0_EXE_MEM),
    .cp0Rdata_EXE_MEM  ( cp0Rdata_EXE_MEM)
  );


writeback_stage wb_stage(
    .clk               (              clk),
    .rst               (              rst),
    .MemToReg_MEM_WB   (  MemToReg_MEM_WB),
    .RegWrite_MEM_WB   (  RegWrite_MEM_WB),
    .MFHL_MEM_WB       (      MFHL_MEM_WB),
    .LB_MEM_WB         (        LB_MEM_WB),
    .LBU_MEM_WB        (       LBU_MEM_WB),
    .LH_MEM_WB         (        LH_MEM_WB),
    .LHU_MEM_WB        (       LHU_MEM_WB),
    .LW_MEM_WB         (        LW_MEM_WB),
    .RegWaddr_MEM_WB   (  RegWaddr_MEM_WB),
    .ALUResult_MEM_WB  ( ALUResult_MEM_WB),
    .RegRdata2_MEM_WB  ( RegRdata2_MEM_WB),
    .MemRdata_MEM_WB   (  data_sram_rdata),
    .PC_MEM_WB         (        PC_MEM_WB),
    .HI_MEM_WB         (           HI_out),
    .LO_MEM_WB         (           LO_out),
    .RegWdata_WB       (      RegWdata_WB),
    .RegWdata_Bypass_WB(RegWdata_Bypass_WB),
    .RegWaddr_WB       (      RegWaddr_WB),
    .RegWrite_WB       (      RegWrite_WB),
    .PC_WB             (            PC_WB),
    
    .cp0Rdata_MEM_WB   (  cp0Rdata_MEM_WB),
    .mfc0_MEM_WB       (      mfc0_MEM_WB)
);

Bypass_Unit bypass_unit(
    .clk                (              clk),
    .rst                (              rst),

    .is_rs_read         (       is_rs_read),
    .is_rt_read         (       is_rt_read),

    .MemToReg_ID_EXE    (  MemToReg_ID_EXE),
    .MemToReg_EXE_MEM   ( MemToReg_EXE_MEM),
    .MemToReg_MEM_WB    (  MemToReg_MEM_WB),

    .RegWaddr_EXE_MEM   ( RegWaddr_EXE_MEM),
    .RegWaddr_MEM_WB    (  RegWaddr_MEM_WB),
    .RegWaddr_ID_EXE    (  RegWaddr_ID_EXE),

    .rs_ID              (Inst_IF_ID[25:21]),
    .rt_ID              (Inst_IF_ID[20:16]),

    .RegWrite_ID_EXE    (  RegWrite_ID_EXE),
    .RegWrite_EXE_MEM   ( RegWrite_EXE_MEM),
    .RegWrite_MEM_WB    (  RegWrite_MEM_WB),
    
    .DIV_Busy           (         DIV_Busy),
    .DIV                (      |DIV_ID_EXE),
    
    .ex_int_handle      (    ex_int_handle),

    .PCWrite            (          PCWrite),
    .IRWrite            (          IRWrite),
    .ID_EXE_Stall       (     ID_EXE_Stall),

    .RegRdata1_src      (    RegRdata1_src),
    .RegRdata2_src      (    RegRdata2_src)
);

reg_file RegFile(
    .clk               (              clk),
    .rst               (              rst),
    .waddr             (      RegWaddr_WB),
    .raddr1            (        RegRaddr1),
    .raddr2            (        RegRaddr2),
    .wen               (      RegWrite_WB),
    .wdata             (      RegWdata_WB),
    .rdata1            (        RegRdata1),
    .rdata2            (        RegRdata2)
);

cp0reg cp0(
    .clk               (              clk),
    .rst               (              rst),
    .eret              (      eret_ID_EXE),
    .int               (            int_i),
    .Exc_BD            (           Exc_BD),
    .Exc_Vec           (          Exc_Vec),
    .waddr             (         CP0Waddr),
    .raddr             (         CP0Raddr),
    .wen               ( cp0_Write_ID_EXE),
    .wdata             (         CP0Wdata),
    .epc_in            (          Exc_EPC),
    .Exc_BadVaddr      (     Exc_BadVaddr),
    .rdata             (         CP0Rdata),
    .epc_value         (              epc),
    .ex_int_handle     (    ex_int_handle),
    .eret_handle       (      eret_handle)

);

multiplyer mul(
    .x          (              RegRdata1_ID_EXE),
    .y          (              RegRdata2_ID_EXE),
    .mul_clk    (                           clk),
    .resetn     (                        resetn),
    .clken      (                  |MULT_ID_EXE),
    .mul_signed (MULT_ID_EXE[0]&~MULT_ID_EXE[1]),
    .result     (                   MULT_Result)
);

divider div(
    .div_clk    (                           clk),
    .rst        (                           rst),
    .x          (              RegRdata1_ID_EXE),
    .y          (              RegRdata2_ID_EXE),
    .div        (                   |DIV_ID_EXE),
    .div_signed (  DIV_ID_EXE[0]&~DIV_ID_EXE[1]),
    .s          (                  DIV_quotient),
    .r          (                 DIV_remainder),
    .busy       (                      DIV_Busy),
    .complete   (                  DIV_Complete)
);

HILO HILO(
    .clk        (                           clk),
    .rst        (                           rst),
    .HI_in      (                         HI_in),
    .LO_in      (                         LO_in),
    .HILO_Write (                    HILO_Write),
    .HI_out     (                        HI_out),
    .LO_out     (                        LO_out)
);


assign HI_in = |MULT_EXE_MEM    ? MULT_Result[63:32] :
                MTHL_EXE_MEM[1] ? RegRdata1_EXE_MEM  :
                DIV_Complete    ? DIV_remainder      : 'd0;
assign LO_in = |MULT_EXE_MEM    ? MULT_Result[31: 0] :
                MTHL_EXE_MEM[0] ? RegRdata1_EXE_MEM  :
                DIV_Complete    ? DIV_quotient       : 'd0;
assign HILO_Write[1] = |MULT_EXE_MEM | DIV_Complete | MTHL_EXE_MEM[1];
assign HILO_Write[0] = |MULT_EXE_MEM | DIV_Complete | MTHL_EXE_MEM[0];

assign CP0Waddr = Rd_ID_EXE;
assign CP0Wdata = RegRdata2_ID_EXE;
assign CP0Raddr = Rd_ID_EXE;



`ifdef SIMU_DEBUG
assign debug_wb_pc       = PC_WB;
assign debug_wb_rf_wen   = RegWrite_WB;
assign debug_wb_rf_wnum  = RegWaddr_WB;
assign debug_wb_rf_wdata = RegWdata_WB;
`endif

endmodule