data/full_repos/permissive/18461059/rtl/edac_top.v
1: b'%Error: data/full_repos/permissive/18461059/rtl/edac_top.v:1: Cannot find include file: encoder.v\n`include "encoder.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18461059/rtl,data/full_repos/permissive/18461059/encoder.v\n             data/full_repos/permissive/18461059/rtl,data/full_repos/permissive/18461059/encoder.v.v\n             data/full_repos/permissive/18461059/rtl,data/full_repos/permissive/18461059/encoder.v.sv\n             encoder.v\n             encoder.v.v\n             encoder.v.sv\n             obj_dir/encoder.v\n             obj_dir/encoder.v.v\n             obj_dir/encoder.v.sv\n%Error: data/full_repos/permissive/18461059/rtl/edac_top.v:2: Cannot find include file: decoder.v\n`include "decoder.v" \n         ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module edac_top (clk, reset_b,Data_valid_08p,DataParity_valid_12p,Data_in_08p,Data_out_10p,Parity_out_10p,Data_out_14p,EDACerr1_14p, EDACerr2_14p,
		DataParity_in_12p);

	parameter k = 128;
	parameter r = 9;
	input wire clk, reset_b,Data_valid_08p,DataParity_valid_12p;
	input wire [k:1] Data_in_08p;
	output wire [k:1] Data_out_10p;
	output wire [r:1] Parity_out_10p;
	output wire [k:1] Data_out_14p;
	output wire EDACerr1_14p, EDACerr2_14p;
	input wire [k+r:1] DataParity_in_12p;
		

	Encoder #(.DATA_BITS(k),.PARITY_BITS(r)) enc1(
	.clk(clk),
	.reset_b(reset_b),
	.Data_valid_08p(Data_valid_08p),
	.Data_in_08p(Data_in_08p),
	.Data_out_10p(Data_out_10p),
	.Parity_out_10p(Parity_out_10p)
	);	
	

	Decoder #(.DATA_BITS(k),.PARITY_BITS(r))dec1(
	.clk(clk),
	.reset_b(reset_b),
	.DataParity_valid_12p(DataParity_valid_12p),
	.DataParity_in_12p(DataParity_in_12p),
	.Data_out_14p(Data_out_14p),
	.EDACerr1_14p(EDACerr1_14p),
	.EDACerr2_14p(EDACerr2_14p)
	); 

endmodule
module edac_top (clk, reset_b,Data_valid_08p,DataParity_valid_12p,Data_in_08p,Data_out_10p,Parity_out_10p,Data_out_14p,EDACerr1_14p, EDACerr2_14p,
		DataParity_in_12p);


	parameter k = 128;
	parameter r = 9;
	input wire clk, reset_b,Data_valid_08p,DataParity_valid_12p;
	input wire [k:1] Data_in_08p;
	output wire [k:1] Data_out_10p;
	output wire [r:1] Parity_out_10p;
	output wire [k:1] Data_out_14p;
	output wire EDACerr1_14p, EDACerr2_14p;
	input wire [k+r:1] DataParity_in_12p;
		

	Encoder #(.DATA_BITS(k),.PARITY_BITS(r)) enc1(
	.clk(clk),
	.reset_b(reset_b),
	.Data_valid_08p(Data_valid_08p),
	.Data_in_08p(Data_in_08p),
	.Data_out_10p(Data_out_10p),
	.Parity_out_10p(Parity_out_10p)
	);	
	

	Decoder #(.DATA_BITS(k),.PARITY_BITS(r))dec1(
	.clk(clk),
	.reset_b(reset_b),
	.DataParity_valid_12p(DataParity_valid_12p),
	.DataParity_in_12p(DataParity_in_12p),
	.Data_out_14p(Data_out_14p),
	.EDACerr1_14p(EDACerr1_14p),
	.EDACerr2_14p(EDACerr2_14p)
	); 

endmodule