data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_TF.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_TF.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_TF.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_TF.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_TF.v:66: Unsupported: Ignoring delay on this delayed statement.\nalways#2 clk = ~clk;      \n      ^\n%Error: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/SPI_Master_TF.v:39: Cannot find file containing module: \'SPI_Master\'\n SPI_Master uut (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/SPI_Master\n             data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/SPI_Master.v\n             data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/SPI_Master.sv\n             SPI_Master\n             SPI_Master.v\n             SPI_Master.sv\n             obj_dir/SPI_Master\n             obj_dir/SPI_Master.v\n             obj_dir/SPI_Master.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SPI_Master_TF;


	reg clk;
	reg [31:0] ToSPI;
	reg enable;
	reg reset;


	wire MOSI;
	wire SPI_CS;
	wire sClk;


	SPI_Master uut (
		.clk(clk), 
		.sClk(sClk),
		.ToSPI(ToSPI), 
		.enable(enable), 
		.reset(reset), 
		.MOSI(MOSI), 
		.SPI_CS(SPI_CS)
	);

	initial begin

		clk = 0;
		ToSPI = 0;
		enable = 0;
		reset = 1;
		#5
		reset = 0;
		#5;
		reset = 1;
		#5;
		enable =1;
		ToSPI = 32'b10110011100011110000111110000010;
		        


	end
always#2 clk = ~clk;      
endmodule
module SPI_Master_TF;



	reg clk;
	reg [31:0] ToSPI;
	reg enable;
	reg reset;


	wire MOSI;
	wire SPI_CS;
	wire sClk;


	SPI_Master uut (
		.clk(clk), 
		.sClk(sClk),
		.ToSPI(ToSPI), 
		.enable(enable), 
		.reset(reset), 
		.MOSI(MOSI), 
		.SPI_CS(SPI_CS)
	);

	initial begin

		clk = 0;
		ToSPI = 0;
		enable = 0;
		reset = 1;
		#5
		reset = 0;
		#5;
		reset = 1;
		#5;
		enable =1;
		ToSPI = 32'b10110011100011110000111110000010;
		        


	end
always#2 clk = ~clk;      
endmodule