data/full_repos/permissive/214278225/2_upDownCounter/upDownCounter/delay.v
data/verilator_xmls/e8cc057e-58e7-479c-9b29-d133edb17f52.xml
module delay(rst, clk, out);
	input clk;
	input rst;
	
	output out;
	
	parameter CNT_WIDTH = 26;
	
	reg [CNT_WIDTH-1:0] timer, timerNext;

	always @(posedge clk) begin
		timer <= #1 timerNext;
	end

	always @(*) begin
		if(rst) begin
			timerNext = 0;
		end else begin
			timerNext = timer + 1;
		end
	end

	assign out = (timer==0);
	
endmodule
module delay(rst, clk, out);

	input clk;
	input rst;
	
	output out;
	
	parameter CNT_WIDTH = 26;
	
	reg [CNT_WIDTH-1:0] timer, timerNext;

	always @(posedge clk) begin
		timer <= #1 timerNext;
	end

	always @(*) begin
		if(rst) begin
			timerNext = 0;
		end else begin
			timerNext = timer + 1;
		end
	end

	assign out = (timer==0);
	
endmodule