data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v
 line:41: before: "signed"
1: b'%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:18: Cannot find include file: multiply_acc.v\n`include "multiply_acc.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/153960117/hdl,data/full_repos/permissive/153960117/multiply_acc.v\n             data/full_repos/permissive/153960117/hdl,data/full_repos/permissive/153960117/multiply_acc.v.v\n             data/full_repos/permissive/153960117/hdl,data/full_repos/permissive/153960117/multiply_acc.v.sv\n             multiply_acc.v\n             multiply_acc.v.v\n             multiply_acc.v.sv\n             obj_dir/multiply_acc.v\n             obj_dir/multiply_acc.v.v\n             obj_dir/multiply_acc.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:31: Unsupported: event data types\n    event end_trigger;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    initial #1 display_header();\n            ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:113: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:148: syntax error, unexpected \'@\'\n        repeat(6) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:150: syntax error, unexpected \'@\'\n        repeat(6) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:152: syntax error, unexpected \'@\'\n        repeat(6) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:160: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:165: syntax error, unexpected \'@\'\n            @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:171: syntax error, unexpected \'@\'\n        repeat (10) @(negedge clk);\n                    ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:182: syntax error, unexpected \'@\'\n            @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:186: syntax error, unexpected \'@\'\n        repeat (10) @(negedge clk);\n                    ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:191: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:194: syntax error, unexpected \'@\'\n        repeat (5) @(negedge clk);\n                   ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:200: syntax error, unexpected \'@\'\n            @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:204: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:210: syntax error, unexpected \'@\'\n            @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:214: syntax error, unexpected \'@\'\n        repeat (10) @(negedge clk);\n                    ^\n%Error: data/full_repos/permissive/153960117/hdl/multiply_acc_tb.v:220: syntax error, unexpected ->\n        -> end_trigger;\n        ^~\n%Error: Exiting due to 19 error(s), 2 warning(s)\n'
module multiply_acc_tb;




    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam IMG_WIDTH    = 16;
    localparam KER_WIDTH    = 8;


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'multiply_acc' img: %d, ker: %d, result: %d",
            IMG_WIDTH, KER_WIDTH, (IMG_WIDTH+KER_WIDTH+1));
    end
`endif




    reg                             rst;

    reg     [IMG_WIDTH-1:0]         img;
    reg     [KER_WIDTH-1:0]         ker;
    reg                             val;

    wire    [IMG_WIDTH+KER_WIDTH:0] result;




    multiply_acc #(
        .IMG_WIDTH  (IMG_WIDTH),
        .KER_WIDTH  (KER_WIDTH))
    uut (
        .clk    (clk),
        .rst    (rst),

        .val    (val),
        .img    (img),
        .ker    (ker),

        .result (result)
    );




    task display_signals;
        $display(
            "%d\t%d",
            $time, rst,

            "\t%b\t%d\t%d",
            val,
            $signed(img),
            $signed(ker),

            "\t%d",
            $signed(result),
        );
    endtask

    task display_header;
        $display(
            "\t\ttime\trst",

            "\tval",
            "\tma",
            "\tker",

            "\t\tresult",

        );
    endtask





    initial begin

        rst = 0;

        val = 1'b0;
        img = 'b0;
        ker = 'b0;


`ifdef TB_VERBOSE
    $display("RESET");
`endif

        repeat(6) @(posedge clk);
        rst <= 1'b1;
        repeat(6) @(posedge clk);
        rst <= 1'b0;
        repeat(6) @(posedge clk);


`ifdef TB_VERBOSE
    $display("test continuous stream");
`endif

        img <= 1'b1;
        @(negedge clk);
        repeat (10) begin
            val <= 1'b1;
            img <= img * -'b1;
            ker <= ker +  'b1;
            @(negedge clk);
        end

        val <= 1'b0;
        img <=  'b0;
        ker <=  'b0;
        repeat (10) @(negedge clk);


`ifdef TB_VERBOSE
    $display("test non-continuous ready");
`endif

        repeat (5) begin
            val <= 1'b1;
            img <=  'b1;
            ker <= ker + 'b1;
            @(negedge clk);
        end

        val <= 1'b0;
        repeat (10) @(negedge clk);

        val <= 1'b1;
        img <=  'b1;
        ker <= ker + 'b1;
        @(negedge clk);

        val  <= 1'b0;
        repeat (5) @(negedge clk);

        repeat (5) begin
            val <= 1'b1;
            img <=  'b1;
            ker <= ker + 'b1;
            @(negedge clk);
        end

        val  <= 1'b0;
        @(negedge clk);

        repeat (20) begin
            val <= 1'b1;
            img <=  'b1;
            ker <= ker + 'b1;
            @(negedge clk);
        end

        val  <= 1'b0;
        repeat (10) @(negedge clk);


`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule
module multiply_acc_tb;





    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam IMG_WIDTH    = 16;
    localparam KER_WIDTH    = 8;


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'multiply_acc' img: %d, ker: %d, result: %d",
            IMG_WIDTH, KER_WIDTH, (IMG_WIDTH+KER_WIDTH+1));
    end
`endif




    reg                             rst;

    reg     [IMG_WIDTH-1:0]         img;
    reg     [KER_WIDTH-1:0]         ker;
    reg                             val;

    wire    [IMG_WIDTH+KER_WIDTH:0] result;




    multiply_acc #(
        .IMG_WIDTH  (IMG_WIDTH),
        .KER_WIDTH  (KER_WIDTH))
    uut (
        .clk    (clk),
        .rst    (rst),

        .val    (val),
        .img    (img),
        .ker    (ker),

        .result (result)
    );




    task display_signals;
        $display(
            "%d\t%d",
            $time, rst,

            "\t%b\t%d\t%d",
            val,
            $signed(img),
            $signed(ker),

            "\t%d",
            $signed(result),
        );
    endtask

    task display_header;
        $display(
            "\t\ttime\trst",

            "\tval",
            "\tma",
            "\tker",

            "\t\tresult",

        );
    endtask





    initial begin

        rst = 0;

        val = 1'b0;
        img = 'b0;
        ker = 'b0;


`ifdef TB_VERBOSE
    $display("RESET");
`endif

        repeat(6) @(posedge clk);
        rst <= 1'b1;
        repeat(6) @(posedge clk);
        rst <= 1'b0;
        repeat(6) @(posedge clk);


`ifdef TB_VERBOSE
    $display("test continuous stream");
`endif

        img <= 1'b1;
        @(negedge clk);
        repeat (10) begin
            val <= 1'b1;
            img <= img * -'b1;
            ker <= ker +  'b1;
            @(negedge clk);
        end

        val <= 1'b0;
        img <=  'b0;
        ker <=  'b0;
        repeat (10) @(negedge clk);


`ifdef TB_VERBOSE
    $display("test non-continuous ready");
`endif

        repeat (5) begin
            val <= 1'b1;
            img <=  'b1;
            ker <= ker + 'b1;
            @(negedge clk);
        end

        val <= 1'b0;
        repeat (10) @(negedge clk);

        val <= 1'b1;
        img <=  'b1;
        ker <= ker + 'b1;
        @(negedge clk);

        val  <= 1'b0;
        repeat (5) @(negedge clk);

        repeat (5) begin
            val <= 1'b1;
            img <=  'b1;
            ker <= ker + 'b1;
            @(negedge clk);
        end

        val  <= 1'b0;
        @(negedge clk);

        repeat (20) begin
            val <= 1'b1;
            img <=  'b1;
            ker <= ker + 'b1;
            @(negedge clk);
        end

        val  <= 1'b0;
        repeat (10) @(negedge clk);


`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule