data/full_repos/permissive/131069375/uv-risc/verilog/alu.v
None: at end of input
data/verilator_xmls/2733e3c7-e929-4798-aaba-90e9817307ca.xml
module alu
(
 input 		   sub, muls,
 input [2:0] 	   out_sel,
 input [15:0] 	   x, y,
 output [15:0] 	   result_hi,
 output reg [15:0] result,
 output 	   C,N,V,Z
);
endmodule
module alu
(
 input 		   sub, muls,
 input [2:0] 	   out_sel,
 input [15:0] 	   x, y,
 output [15:0] 	   result_hi,
 output reg [15:0] result,
 output 	   C,N,V,Z
);

endmodule