data/full_repos/permissive/112219256/HILO.v
data/verilator_xmls/bdf0417e-aa23-420e-a9fd-3a072ba48af1.xml
module HILO(
    input clk,
    input rst,
    input  [31:0] HI_in,
    input  [31:0] LO_in,
    input  [ 1:0] HILO_Write,
    output [31:0] HI_out,
    output [31:0] LO_out
);

    reg [31:0] HI;
    reg [31:0] LO;
    always @ (posedge clk) begin
begin
        if (HILO_Write[1]) HI <= HI_in;
        else               HI <= HI;
        if (HILO_Write[0]) LO <= LO_in;
        else               LO <= LO;
        end
    end

    assign HI_out = HI;
    assign LO_out = LO;
endmodule
module HILO(
    input clk,
    input rst,
    input  [31:0] HI_in,
    input  [31:0] LO_in,
    input  [ 1:0] HILO_Write,
    output [31:0] HI_out,
    output [31:0] LO_out
);


    reg [31:0] HI;
    reg [31:0] LO;
    always @ (posedge clk) begin
begin
        if (HILO_Write[1]) HI <= HI_in;
        else               HI <= HI;
        if (HILO_Write[0]) LO <= LO_in;
        else               LO <= LO;
        end
    end

    assign HI_out = HI;
    assign LO_out = LO;
endmodule