data/full_repos/permissive/177233467/instruction_fetch.v
data/verilator_xmls/476b7aec-ba0c-4e86-85c1-ae149f8950f3.xml
module instruction_fetch
(
  input wire clk, resetn,
  input wire [31:0] pc,
  output reg [code_width - 1:0]  code_mem_rd
);

parameter code_width = 32;
parameter code_words = 512;
parameter code_addr_width = 9;

  reg [code_width - 1:0]  code_mem[code_words - 1:0];
  wire [code_addr_width - 1: 0] code_addr;





  initial begin


      $readmemb("./bin/lotsa_instructions.mem", code_mem);
  end


  assign code_addr = pc[code_addr_width + 1:2];












  always @(posedge clk) begin
    if (!resetn)
      code_mem_rd <= 32'hFF_FF_FF_FF;
    else
      code_mem_rd <= code_mem[code_addr];
  end










endmodule
module instruction_fetch
(
  input wire clk, resetn,
  input wire [31:0] pc,
  output reg [code_width - 1:0]  code_mem_rd
);


parameter code_width = 32;
parameter code_words = 512;
parameter code_addr_width = 9;

  reg [code_width - 1:0]  code_mem[code_words - 1:0];
  wire [code_addr_width - 1: 0] code_addr;





  initial begin


      $readmemb("./bin/lotsa_instructions.mem", code_mem);
  end


  assign code_addr = pc[code_addr_width + 1:2];












  always @(posedge clk) begin
    if (!resetn)
      code_mem_rd <= 32'hFF_FF_FF_FF;
    else
      code_mem_rd <= code_mem[code_addr];
  end










endmodule