data/full_repos/permissive/211878730/atlys/led/led.v
data/verilator_xmls/d917a9a4-4207-4bfe-b439-a772955b3b01.xml
module led(s1, q);
	input  wire s1;
	output wire q;
	
	assign q = s1;
endmodule
module led(s1, q);

	input  wire s1;
	output wire q;
	
	assign q = s1;
endmodule