data/full_repos/permissive/143278/ivltests/pr1746401.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1746401.v:13: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1746401.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (sign !== 1\'b1) begin\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();
   reg [1:0] array[1:0];
   reg	     sign;
   reg	     clk = 1'b0;

   always @(posedge clk)
     sign = array[1][1];

   initial begin
      array[0] = 1;
      array[1] = 2;

      #1 clk = 1;

      #1 if (sign !== 1'b1) begin
	 $display("FAILED -- array[1][1] = %b, sign=%b", array[1][1], sign);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module test();

   reg [1:0] array[1:0];
   reg	     sign;
   reg	     clk = 1'b0;

   always @(posedge clk)
     sign = array[1][1];

   initial begin
      array[0] = 1;
      array[1] = 2;

      #1 clk = 1;

      #1 if (sign !== 1'b1) begin
	 $display("FAILED -- array[1][1] = %b, sign=%b", array[1][1], sign);
	 $finish;
      end

      $display("PASSED");
   end

endmodule