data/full_repos/permissive/216946917/tests/data/designs/constants/constants_simple_rtl.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/216946917/tests/data/designs/constants/constants_simple_rtl.v:15: Signal definition not found, creating implicitly: \'h\'\n    OrWrapper y(b, c, e, h);\n                         ^\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Constants(input clock, input [5:0] io_wide_bus, output reduced, output [2: 0] out);

  reg reduce_it;
  assign reduced = reduce_it;

  AndOr mod(reduce_it, 1'b0, 1'b1, out[0], out[1], out[2]);
  
  always @(posedge clock) begin
    reduce_it = |io_wide_bus;
  end
endmodule
module Constants(input clock, input [5:0] io_wide_bus, output reduced, output [2: 0] out);


  reg reduce_it;
  assign reduced = reduce_it;

  AndOr mod(reduce_it, 1'b0, 1'b1, out[0], out[1], out[2]);
  
  always @(posedge clock) begin
    reduce_it = |io_wide_bus;
  end
endmodule