data/full_repos/permissive/146073027/Simple 32bit integer ALU.v
 line:28: before: "assign"
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/146073027/Simple\n        ... Looked in:\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple.v\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple.sv\n             data/full_repos/permissive/146073027/Simple\n             data/full_repos/permissive/146073027/Simple.v\n             data/full_repos/permissive/146073027/Simple.sv\n             obj_dir/data/full_repos/permissive/146073027/Simple\n             obj_dir/data/full_repos/permissive/146073027/Simple.v\n             obj_dir/data/full_repos/permissive/146073027/Simple.sv\n%Error: Cannot find file containing module: 32bit\n%Error: Cannot find file containing module: integer\n%Error: Cannot find file containing module: ALU.v\n%Error: Exiting due to 4 error(s)\n'
module multiplexer(outReal,in1,in2,choice);
  output [31:0]outReal;
  wire [31:0]out[0:7];
  input [31:0]in1,in2;
  input [2:0]choice;
  reg [31:0]outReal1;
  wire c_out;
  
  bitwise_and ba(out[0],in1,in2);
  bitwise_or bo(out[1],in1,in2);
  thirtytwo_bit_fa tbf(c_out,out[2],0,in1,in2);
  ones_complement oc(out[3],in1);
  twos_complement tc(out[4],in1);
  subtractor sbt(out[5],c_in,x,y);
  sixteen_bit_multiplicator sbm(out[6],in1,in2);
  thirty_two_bit_comparator ttbc(out[7],in1,in2);
  
  always@(choice)
    begin
      if(choice==0)
        assign outReal1=out[0];
      else if(choice==1)
        assign outReal1=out[1];
      else if(choice==2)
        assign outReal1=out[2];
      else if(choice==3)
        assign outReal1=out[3];
      else if(choice==4)
        assign outReal1=out[4];
      else if(choice==5)
        assign outReal1=out[5];
      else if(choice==6)
        assign outReal1=out[6];
      else if(choice==7)
        assign outReal1=out[7];
    end
  assign outReal=outReal1;
endmodule
module multiplexer(outReal,in1,in2,choice);

  output [31:0]outReal;
  wire [31:0]out[0:7];
  input [31:0]in1,in2;
  input [2:0]choice;
  reg [31:0]outReal1;
  wire c_out;
  
  bitwise_and ba(out[0],in1,in2);
  bitwise_or bo(out[1],in1,in2);
  thirtytwo_bit_fa tbf(c_out,out[2],0,in1,in2);
  ones_complement oc(out[3],in1);
  twos_complement tc(out[4],in1);
  subtractor sbt(out[5],c_in,x,y);
  sixteen_bit_multiplicator sbm(out[6],in1,in2);
  thirty_two_bit_comparator ttbc(out[7],in1,in2);
  
  always@(choice)
    begin
      if(choice==0)
        assign outReal1=out[0];
      else if(choice==1)
        assign outReal1=out[1];
      else if(choice==2)
        assign outReal1=out[2];
      else if(choice==3)
        assign outReal1=out[3];
      else if(choice==4)
        assign outReal1=out[4];
      else if(choice==5)
        assign outReal1=out[5];
      else if(choice==6)
        assign outReal1=out[6];
      else if(choice==7)
        assign outReal1=out[7];
    end
  assign outReal=outReal1;
endmodule