data/full_repos/permissive/210844779/lab6/6.3/dff.v
 line:15: before: "$"
data/verilator_xmls/9174ebbf-343f-4cc1-a3f8-94064244a8ff.xml
module dff(d,clk,rst,q);
  
  input d,clk,rst;
  output reg q;
  
  always @(posedge clk,posedge rst)
  begin
  if (rst)
    q<=0;
  else
    q<=d;
  end
  
  specify
  $setuphold(posedge clk,d,3,4);
  endspecify
  
endmodule
module dff(d,clk,rst,q);

  
  input d,clk,rst;
  output reg q;
  
  always @(posedge clk,posedge rst)
  begin
  if (rst)
    q<=0;
  else
    q<=d;
  end
  
  specify
  $setuphold(posedge clk,d,3,4);
  endspecify
  
endmodule