data/full_repos/permissive/219917900/rx_rtl_files/rx_majority_wrapper.v
1: b'%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/rx_majority_wrapper.v:111: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance rx_majority_wrapper\n        count_edge <= 1\'b0;\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/rx_majority_wrapper.v:160: Cannot find file containing module: \'n2one\'\n    n2one #(.whereisid(whereisid)) n2one_inst(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/219917900/rx_rtl_files,data/full_repos/permissive/219917900/n2one\n             data/full_repos/permissive/219917900/rx_rtl_files,data/full_repos/permissive/219917900/n2one.v\n             data/full_repos/permissive/219917900/rx_rtl_files,data/full_repos/permissive/219917900/n2one.sv\n             n2one\n             n2one.v\n             n2one.sv\n             obj_dir/n2one\n             obj_dir/n2one.v\n             obj_dir/n2one.sv\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/rx_majority_wrapper.v:245: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                                           : ... In instance rx_majority_wrapper\n                            sel = j;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/rx_majority_wrapper.v:257: Bit extraction of array[149:0] requires 8 bit index, not 16 bits.\n                                                                                           : ... In instance rx_majority_wrapper\n                        data_out_one <= data_out_seg_reg[sel];\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/rx_majority_wrapper.v:258: Bit extraction of array[149:0] requires 8 bit index, not 16 bits.\n                                                                                           : ... In instance rx_majority_wrapper\n                        en_out_one <= en_out_seg_reg[sel];\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/219917900/rx_rtl_files/rx_majority_wrapper.v:255: Bit extraction of array[149:0] requires 8 bit index, not 16 bits.\n                                                                                           : ... In instance rx_majority_wrapper\n                    if (en_out_seg_reg[sel]) begin\n                                      ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module rx_majority_wrapper #(parameter whereis_segment_num = 34,whereisid = 0, SEGMENT_NUM_MAX = 150
)
(
    input wire clk125MHz,
    input wire reset,
    input wire [7:0] rx_data,
    input wire rx_enable,
    output wire tmp,
    input wire [7:0] redundancy,
    output reg [15:0] seg_out,
    output wire en_out,
    output wire [7:0] data_out
);


(* mark_debug = "true" *) reg rx_en;
(* mark_debug = "true" *) reg [7:0] rxdata;
(* mark_debug = "true" *) reg [11:0] count_edge = 0;
(* mark_debug = "true" *) reg [15:0] segment_num = 0;
reg segment_num_en = 0;
(* mark_debug = "true" *) reg [7:0] rx_id_fordebug;
(* mark_debug = "true" *) reg [7:0] aux_fordebug;





localparam ip_src_addr = 32'hc0a80140;

localparam eth_dst_mac = 48'hdeadbeef0123;

(* mark_debug = "true" *) reg validation;


always @(posedge clk125MHz) begin
    if (reset) begin
        validation = 1;
        count_edge = 0;
        segment_num_en = 0;
        
    end

    rx_en <= rx_enable;
    rxdata <= rx_data;

    if (validation) begin
        case (count_edge)
            (6): begin
                if (eth_dst_mac[47:40] != rxdata)
                    validation <= 0;
                end
            (7): begin
                if (eth_dst_mac[39:32] != rxdata)
                    validation <= 0;
                end
            (8): begin
                if (eth_dst_mac[31:24] != rxdata)
                    validation <= 0;
                end
            (9) : begin
                if (eth_dst_mac[23:16] != rxdata)
                    validation <= 0;
                end
            (10) : begin
                if (eth_dst_mac[15:8] != rxdata)
                    validation <= 0;
                end
            (11): begin
                if (eth_dst_mac[7:0] != rxdata)
                    validation <= 0;
                end

            (26): begin
                if (ip_src_addr[31:24] != rxdata)
                    validation <= 0;
                
            end
            (27): begin
                if (ip_src_addr[23:16] != rxdata)
                    validation <= 0;
            end
            (28): begin
                if (ip_src_addr[15:8] != rxdata)
                    validation <= 0;
                    end
            
            (29): begin
                if (ip_src_addr[7:0] != rxdata)
                    validation <= 0;
                    end
            (32): begin
                if (8'h01 != rxdata)
                    validation <= 0;
                end
            (33): begin
                if (8'h02 != rxdata)
                    validation <= 0;
                end

        endcase
    end

    if (rx_en && rx_enable) begin
        count_edge <= count_edge + 1'b1;
    end	else begin
        validation <= 1;
        count_edge <= 1'b0;
        segment_num <= 0;
        segment_num_en <= 0;
    end

    if (count_edge == whereis_segment_num) begin
        segment_num[15:8] <= rxdata;
    end
    else if (count_edge == whereis_segment_num +1 && validation) begin
        segment_num[7:0] <= rxdata;
        segment_num_en <= 1'b1;
    end
    else if (count_edge == whereis_segment_num + 2) begin
        rx_id_fordebug <= rxdata;
    end
    else if (count_edge == whereis_segment_num+3) begin
        aux_fordebug <= rxdata;
    end
end


wire rx_enable_seg[SEGMENT_NUM_MAX - 1: 0];

wire [7:0] data_out_seg[SEGMENT_NUM_MAX - 1: 0];
wire en_out_seg[SEGMENT_NUM_MAX - 1: 0];

wire [7:0] data_out_seg_wire[SEGMENT_NUM_MAX - 1: 0];




genvar i;
reg rxen_seg_reg [SEGMENT_NUM_MAX - 1 : 0];
reg [7:0] rxdata_reg;

generate
for (i=0; i<SEGMENT_NUM_MAX; i=i+1) begin
    n2one #(.whereisid(whereisid)) n2one_inst(
        .clk(clk125MHz),
        .rst(reset),
        .rxd(rxdata),
        .rxen(rx_enable_seg[i]),
        .redundancy(redundancy),
        .en_out_reg(en_out_seg[i]),
        .data_out_reg(data_out_seg[i])
    );
    
    assign rx_enable_seg[i] = (segment_num_en && (segment_num == i));
    


end
endgenerate




reg [15:0] sel = 0;
reg [7:0] data_out_seg_reg[SEGMENT_NUM_MAX - 1: 0];
reg en_out_seg_reg[SEGMENT_NUM_MAX - 1: 0];
reg [7:0] data_out_one;
reg en_out_one;
reg [7:0] data_out_one_reg,data_out_one_reg_reg;
reg en_out_one_reg, en_out_one_reg_reg;

integer j;

(* mark_debug = "true" *) reg [2:0] state = 0;

localparam state_max = 2;
wire [2:0] state_next = (state == state_max) ? 3'b0 : (state + 1'b1);
integer k;
always @(posedge clk125MHz) begin
    if (reset) begin
        state = 0;
        en_out_one = 0;
        data_out_one = 8'hff;
    end
    else begin
        for (k=0; k<SEGMENT_NUM_MAX; k=k+1) begin
            en_out_seg_reg[k] <= en_out_seg[k];
            data_out_seg_reg[k] <= data_out_seg[k];
        end

        case (state)
            0:
                begin
                    for (j=0; j < SEGMENT_NUM_MAX; j=j+1) begin
                        if (en_out_seg[j]) begin
                            sel = j;
                            state <= 1;
                        end
                        else begin
                            sel = sel;
                        end
                    end
                end
            1:
                begin
                    if (en_out_seg_reg[sel]) begin
                        seg_out <= sel;
                        data_out_one <= data_out_seg_reg[sel];
                        en_out_one <= en_out_seg_reg[sel];
                    end
                    else begin
                        data_out_one <= 8'hff;
                        en_out_one <= 0;
                        state <= 0;
                    end
                end
            2:
                begin
                end
            3:
                begin
                end
            4:
                begin


                end

            5:
                begin
                end
            6:
                begin
                end
            default:
                begin
                end
        endcase
    end
end

assign data_out = data_out_one;
assign en_out = en_out_one;

endmodule
module rx_majority_wrapper #(parameter whereis_segment_num = 34,whereisid = 0, SEGMENT_NUM_MAX = 150
)
(
    input wire clk125MHz,
    input wire reset,
    input wire [7:0] rx_data,
    input wire rx_enable,
    output wire tmp,
    input wire [7:0] redundancy,
    output reg [15:0] seg_out,
    output wire en_out,
    output wire [7:0] data_out
);



(* mark_debug = "true" *) reg rx_en;
(* mark_debug = "true" *) reg [7:0] rxdata;
(* mark_debug = "true" *) reg [11:0] count_edge = 0;
(* mark_debug = "true" *) reg [15:0] segment_num = 0;
reg segment_num_en = 0;
(* mark_debug = "true" *) reg [7:0] rx_id_fordebug;
(* mark_debug = "true" *) reg [7:0] aux_fordebug;





localparam ip_src_addr = 32'hc0a80140;

localparam eth_dst_mac = 48'hdeadbeef0123;

(* mark_debug = "true" *) reg validation;


always @(posedge clk125MHz) begin
    if (reset) begin
        validation = 1;
        count_edge = 0;
        segment_num_en = 0;
        
    end

    rx_en <= rx_enable;
    rxdata <= rx_data;

    if (validation) begin
        case (count_edge)
            (6): begin
                if (eth_dst_mac[47:40] != rxdata)
                    validation <= 0;
                end
            (7): begin
                if (eth_dst_mac[39:32] != rxdata)
                    validation <= 0;
                end
            (8): begin
                if (eth_dst_mac[31:24] != rxdata)
                    validation <= 0;
                end
            (9) : begin
                if (eth_dst_mac[23:16] != rxdata)
                    validation <= 0;
                end
            (10) : begin
                if (eth_dst_mac[15:8] != rxdata)
                    validation <= 0;
                end
            (11): begin
                if (eth_dst_mac[7:0] != rxdata)
                    validation <= 0;
                end

            (26): begin
                if (ip_src_addr[31:24] != rxdata)
                    validation <= 0;
                
            end
            (27): begin
                if (ip_src_addr[23:16] != rxdata)
                    validation <= 0;
            end
            (28): begin
                if (ip_src_addr[15:8] != rxdata)
                    validation <= 0;
                    end
            
            (29): begin
                if (ip_src_addr[7:0] != rxdata)
                    validation <= 0;
                    end
            (32): begin
                if (8'h01 != rxdata)
                    validation <= 0;
                end
            (33): begin
                if (8'h02 != rxdata)
                    validation <= 0;
                end

        endcase
    end

    if (rx_en && rx_enable) begin
        count_edge <= count_edge + 1'b1;
    end	else begin
        validation <= 1;
        count_edge <= 1'b0;
        segment_num <= 0;
        segment_num_en <= 0;
    end

    if (count_edge == whereis_segment_num) begin
        segment_num[15:8] <= rxdata;
    end
    else if (count_edge == whereis_segment_num +1 && validation) begin
        segment_num[7:0] <= rxdata;
        segment_num_en <= 1'b1;
    end
    else if (count_edge == whereis_segment_num + 2) begin
        rx_id_fordebug <= rxdata;
    end
    else if (count_edge == whereis_segment_num+3) begin
        aux_fordebug <= rxdata;
    end
end


wire rx_enable_seg[SEGMENT_NUM_MAX - 1: 0];

wire [7:0] data_out_seg[SEGMENT_NUM_MAX - 1: 0];
wire en_out_seg[SEGMENT_NUM_MAX - 1: 0];

wire [7:0] data_out_seg_wire[SEGMENT_NUM_MAX - 1: 0];




genvar i;
reg rxen_seg_reg [SEGMENT_NUM_MAX - 1 : 0];
reg [7:0] rxdata_reg;

generate
for (i=0; i<SEGMENT_NUM_MAX; i=i+1) begin
    n2one #(.whereisid(whereisid)) n2one_inst(
        .clk(clk125MHz),
        .rst(reset),
        .rxd(rxdata),
        .rxen(rx_enable_seg[i]),
        .redundancy(redundancy),
        .en_out_reg(en_out_seg[i]),
        .data_out_reg(data_out_seg[i])
    );
    
    assign rx_enable_seg[i] = (segment_num_en && (segment_num == i));
    


end
endgenerate




reg [15:0] sel = 0;
reg [7:0] data_out_seg_reg[SEGMENT_NUM_MAX - 1: 0];
reg en_out_seg_reg[SEGMENT_NUM_MAX - 1: 0];
reg [7:0] data_out_one;
reg en_out_one;
reg [7:0] data_out_one_reg,data_out_one_reg_reg;
reg en_out_one_reg, en_out_one_reg_reg;

integer j;

(* mark_debug = "true" *) reg [2:0] state = 0;

localparam state_max = 2;
wire [2:0] state_next = (state == state_max) ? 3'b0 : (state + 1'b1);
integer k;
always @(posedge clk125MHz) begin
    if (reset) begin
        state = 0;
        en_out_one = 0;
        data_out_one = 8'hff;
    end
    else begin
        for (k=0; k<SEGMENT_NUM_MAX; k=k+1) begin
            en_out_seg_reg[k] <= en_out_seg[k];
            data_out_seg_reg[k] <= data_out_seg[k];
        end

        case (state)
            0:
                begin
                    for (j=0; j < SEGMENT_NUM_MAX; j=j+1) begin
                        if (en_out_seg[j]) begin
                            sel = j;
                            state <= 1;
                        end
                        else begin
                            sel = sel;
                        end
                    end
                end
            1:
                begin
                    if (en_out_seg_reg[sel]) begin
                        seg_out <= sel;
                        data_out_one <= data_out_seg_reg[sel];
                        en_out_one <= en_out_seg_reg[sel];
                    end
                    else begin
                        data_out_one <= 8'hff;
                        en_out_one <= 0;
                        state <= 0;
                    end
                end
            2:
                begin
                end
            3:
                begin
                end
            4:
                begin


                end

            5:
                begin
                end
            6:
                begin
                end
            default:
                begin
                end
        endcase
    end
end

assign data_out = data_out_one;
assign en_out = en_out_one;

endmodule