data/full_repos/permissive/135852214/Verilog/enc_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/enc_sim.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/enc_sim.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/enc_sim.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Error: data/full_repos/permissive/135852214/Verilog/enc_sim.v:34: Cannot find file containing module: \'encoder\'\n encoder uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/encoder\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/encoder.v\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/encoder.sv\n             encoder\n             encoder.v\n             encoder.sv\n             obj_dir/encoder\n             obj_dir/encoder.v\n             obj_dir/encoder.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module enc_sim;


	reg [6:0] in;


	wire [3:0] out;


	encoder uut (
		.in(in), 
		.out(out)
	);

	initial begin

		in = 0;


		#100;
      in = 7'b0000111;
		#100;
		in = 7'b0110100;
		#100
		in = 7'b1111000;


	end
      
endmodule
module enc_sim;



	reg [6:0] in;


	wire [3:0] out;


	encoder uut (
		.in(in), 
		.out(out)
	);

	initial begin

		in = 0;


		#100;
      in = 7'b0000111;
		#100;
		in = 7'b0110100;
		#100
		in = 7'b1111000;


	end
      
endmodule