data/full_repos/permissive/121770408/Slave.v
 line:18: before: "mosi"
1: b'%Warning-WIDTH: data/full_repos/permissive/121770408/Slave.v:23: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                               : ... In instance Slave1\naddress <= {address,mosi};\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/121770408/Slave.v:28: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                               : ... In instance Slave1\ndata <= {data,mosi};\n     ^~\n%Warning-WIDTH: data/full_repos/permissive/121770408/Slave.v:33: Bit extraction of array[309:0] requires 9 bit index, not 8 bits.\n                                                               : ... In instance Slave1\nmiso <= arr[address][7];\n           ^\n%Warning-WIDTH: data/full_repos/permissive/121770408/Slave.v:34: Bit extraction of array[309:0] requires 9 bit index, not 8 bits.\n                                                               : ... In instance Slave1\narr[address]<=arr[address]<<1;\n   ^\n%Warning-WIDTH: data/full_repos/permissive/121770408/Slave.v:34: Bit extraction of array[309:0] requires 9 bit index, not 8 bits.\n                                                               : ... In instance Slave1\narr[address]<=arr[address]<<1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/121770408/Slave.v:42: Bit extraction of array[309:0] requires 9 bit index, not 8 bits.\n                                                               : ... In instance Slave1\narr[address]<=data;\n   ^\n%Error: Exiting due to 6 warning(s)\n'
module Slave1(clk,miso,mosi,ss);
input clk;
input [0:0]mosi;
input ss;
output reg[0:0]miso;
reg [7:0] address,data;reg x1;
reg [7:0] arr [0:309];
reg k;
reg [6:0] i=0;
initial begin
arr[233]=185;
end
always @(mosi or ss)begin
if(i==0 && ss==0)begin
x1 <= mosi;
end
end
always @(posedge clk or mosi)begin
if(ss==0)begin


if(i>0 && i<9)begin
address <= {address,mosi};
end


if(i>8 && i<17 && x1==1)begin
data <= {data,mosi};
end


else if(i>8 && i<17 && x1==0)begin
miso <= arr[address][7];
arr[address]<=arr[address]<<1;
end
if(i==17)
miso<=1'bz;


i<=i+1;
if(i>16 && x1==1)
arr[address]<=data;
end

end
endmodule
module Slave1(clk,miso,mosi,ss);

input clk;
input [0:0]mosi;
input ss;
output reg[0:0]miso;
reg [7:0] address,data;reg x1;
reg [7:0] arr [0:309];
reg k;
reg [6:0] i=0;
initial begin
arr[233]=185;
end
always @(mosi or ss)begin
if(i==0 && ss==0)begin
x1 <= mosi;
end
end
always @(posedge clk or mosi)begin
if(ss==0)begin


if(i>0 && i<9)begin
address <= {address,mosi};
end


if(i>8 && i<17 && x1==1)begin
data <= {data,mosi};
end


else if(i>8 && i<17 && x1==0)begin
miso <= arr[address][7];
arr[address]<=arr[address]<<1;
end
if(i==17)
miso<=1'bz;


i<=i+1;
if(i>16 && x1==1)
arr[address]<=data;
end

end
endmodule