data/full_repos/permissive/107735152/src/error/error_overload_block.v
 line:28: before: ")"
1: b"%Error: data/full_repos/permissive/107735152/src/error/error_overload_block.v:28: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n           )\n           ^\n%Error: data/full_repos/permissive/107735152/src/error/error_overload_block.v:32: syntax error, unexpected ';', expecting ',' or ':'\n        interframe <= 1'b1;\n                          ^\n%Error: data/full_repos/permissive/107735152/src/error/error_overload_block.v:45: syntax error, unexpected endcase\n     endcase\n     ^~~~~~~\n%Error: Cannot continue\n"
module error(input reset, samplePoint, eofErro, crcErro, stuffErro, overloadFlag, output erro, interframe);

	reg 		[3:0]stateRead;
	
	initial 	erro = 1'b1;
	
	parameter 	reset = 0; 
	parameter	state = 0;
	parameter 	stateAux = 1;
  
  
  
	always	@ (posedge samplePoint or posedge reset) begin
		if(reset)
			begin
			  stateRead <= state;
			end
		
		else
			if (~reset)
				begin
					case(stateRead)
					  state : 
							begin		
								if( (eofErro    == 1'b0) || 
									(stuffErro  == 1'b0) || 
									(crcErro    == 1'b0) ||
								   )
									begin
										stateRead <= stateAux;
									end
								interframe <= 1'b1;
								
								if(overloadFlag == 1'b0)
									begin
										stateRead <= stateAux;
									end
								
							end
						
					  stateAux : 
							begin		
							  stateRead <= state;
							end
					endcase
				end
		
	end
    
endmodule
module error(input reset, samplePoint, eofErro, crcErro, stuffErro, overloadFlag, output erro, interframe);


	reg 		[3:0]stateRead;
	
	initial 	erro = 1'b1;
	
	parameter 	reset = 0; 
	parameter	state = 0;
	parameter 	stateAux = 1;
  
  
  
	always	@ (posedge samplePoint or posedge reset) begin
		if(reset)
			begin
			  stateRead <= state;
			end
		
		else
			if (~reset)
				begin
					case(stateRead)
					  state : 
							begin		
								if( (eofErro    == 1'b0) || 
									(stuffErro  == 1'b0) || 
									(crcErro    == 1'b0) ||
								   )
									begin
										stateRead <= stateAux;
									end
								interframe <= 1'b1;
								
								if(overloadFlag == 1'b0)
									begin
										stateRead <= stateAux;
									end
								
							end
						
					  stateAux : 
							begin		
							  stateRead <= state;
							end
					endcase
				end
		
	end
    
endmodule