data/full_repos/permissive/207835546/Multiplexer/Mux1/mux1.v
data/verilator_xmls/8deb8f06-b8e6-4899-8147-f666c1d3489f.xml
module mux1 (sel,d,q);

input [1:0] sel;
input [3:0] d;
output q;

wire q;
wire [1:0] sel;
wire [3:0] d;

assign q=d[sel];

endmodule
module mux1 (sel,d,q);


input [1:0] sel;
input [3:0] d;
output q;

wire q;
wire [1:0] sel;
wire [3:0] d;

assign q=d[sel];

endmodule