data/full_repos/permissive/175132042/rtl/wb_ram/bench/wb_ram_tb.v
 line:100: before: "eg"
1: b'%Warning-STMTDLY: data/full_repos/permissive/175132042/rtl/wb_ram/bench/wb_ram_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n   initial #1800 wbm_rst <= 1\'b0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/175132042/rtl/wb_ram/bench/wb_ram_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n   initial #200 wb_rst <= 1\'b0;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/rtl/wb_ram/bench/wb_ram_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n   always #100 wb_clk <= !wb_clk;\n          ^\n%Warning-IMPLICIT: data/full_repos/permissive/175132042/rtl/wb_ram/bench/wb_ram_tb.v:74: Signal definition not found, creating implicitly: \'done\'\n   always @(done) begin\n            ^~~~\n%Error: data/full_repos/permissive/175132042/rtl/wb_ram/bench/wb_ram_tb.v:30: Cannot find file containing module: \'vlog_tb_utils\'\n   vlog_tb_utils vlog_tb_utils0();\n   ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175132042/rtl/wb_ram/bench,data/full_repos/permissive/175132042/vlog_tb_utils\n             data/full_repos/permissive/175132042/rtl/wb_ram/bench,data/full_repos/permissive/175132042/vlog_tb_utils.v\n             data/full_repos/permissive/175132042/rtl/wb_ram/bench,data/full_repos/permissive/175132042/vlog_tb_utils.sv\n             vlog_tb_utils\n             vlog_tb_utils.v\n             vlog_tb_utils.sv\n             obj_dir/vlog_tb_utils\n             obj_dir/vlog_tb_utils.v\n             obj_dir/vlog_tb_utils.sv\n%Error: data/full_repos/permissive/175132042/rtl/wb_ram/bench/wb_ram_tb.v:53: Cannot find file containing module: \'wb_bfm_transactor\'\n   wb_bfm_transactor\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/rtl/wb_ram/bench/wb_ram_tb.v:81: Cannot find file containing module: \'wb_ram\'\n   wb_ram\n   ^~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module wb_ram_tb;

   localparam MEMORY_SIZE = 1024;
   
   vlog_tb_utils vlog_tb_utils0();

   reg wbm_rst = 1'b1;
   
   reg wb_clk = 1'b1;
   reg wb_rst = 1'b1;
   
   initial #1800 wbm_rst <= 1'b0;

   initial #200 wb_rst <= 1'b0;
   always #100 wb_clk <= !wb_clk;

   wire [31:0] wb_adr;
   wire [31:0] wb_dat;
   wire [3:0]  wb_sel;
   wire        wb_we;
   wire        wb_cyc;
   wire        wb_stb;
   wire [2:0]  wb_cti;
   wire [1:0]  wb_bte;
   wire [31:0] wb_rdt;
   wire        wb_ack;
   
   wb_bfm_transactor
     #(.MEM_HIGH (MEMORY_SIZE-1),
       .VERBOSE  (0))
   master
     (.wb_clk_i (wb_clk),
      .wb_rst_i (wbm_rst),
      .wb_adr_o (wb_adr),
      .wb_dat_o (wb_dat),
      .wb_sel_o (wb_sel),
      .wb_we_o  (wb_we), 
      .wb_cyc_o (wb_cyc),
      .wb_stb_o (wb_stb),
      .wb_cti_o (wb_cti),
      .wb_bte_o (wb_bte),
      .wb_dat_i (wb_rdt),
      .wb_ack_i (wb_ack),
      .wb_err_i (1'b0),
      .wb_rty_i (1'b0),

      .done(done));
   
   always @(done) begin
      if(done === 1) begin
	 $display("All tests passed!");
	 $finish;
      end
   end

   wb_ram
     #(.depth (MEMORY_SIZE))
   dut
     (
      .wb_clk_i (wb_clk),
      .wb_rst_i (wb_rst),
      .wb_adr_i (wb_adr[$clog2(MEMORY_SIZE)-1:0]),
      .wb_stb_i (wb_stb),
      .wb_cyc_i (wb_cyc),
      .wb_cti_i (wb_cti),
      .wb_bte_i (wb_bte),
      .wb_we_i  (wb_we) ,
      .wb_sel_i (wb_sel),
      .wb_dat_i (wb_dat),
      .wb_dat_o (wb_rdt),
      .wb_ack_o (wb_ack),
      .wb_err_o ());
   
endmodule
module wb_ram_tb;


   localparam MEMORY_SIZE = 1024;
   
   vlog_tb_utils vlog_tb_utils0();

   reg wbm_rst = 1'b1;
   
   reg wb_clk = 1'b1;
   reg wb_rst = 1'b1;
   
   initial #1800 wbm_rst <= 1'b0;

   initial #200 wb_rst <= 1'b0;
   always #100 wb_clk <= !wb_clk;

   wire [31:0] wb_adr;
   wire [31:0] wb_dat;
   wire [3:0]  wb_sel;
   wire        wb_we;
   wire        wb_cyc;
   wire        wb_stb;
   wire [2:0]  wb_cti;
   wire [1:0]  wb_bte;
   wire [31:0] wb_rdt;
   wire        wb_ack;
   
   wb_bfm_transactor
     #(.MEM_HIGH (MEMORY_SIZE-1),
       .VERBOSE  (0))
   master
     (.wb_clk_i (wb_clk),
      .wb_rst_i (wbm_rst),
      .wb_adr_o (wb_adr),
      .wb_dat_o (wb_dat),
      .wb_sel_o (wb_sel),
      .wb_we_o  (wb_we), 
      .wb_cyc_o (wb_cyc),
      .wb_stb_o (wb_stb),
      .wb_cti_o (wb_cti),
      .wb_bte_o (wb_bte),
      .wb_dat_i (wb_rdt),
      .wb_ack_i (wb_ack),
      .wb_err_i (1'b0),
      .wb_rty_i (1'b0),

      .done(done));
   
   always @(done) begin
      if(done === 1) begin
	 $display("All tests passed!");
	 $finish;
      end
   end

   wb_ram
     #(.depth (MEMORY_SIZE))
   dut
     (
      .wb_clk_i (wb_clk),
      .wb_rst_i (wb_rst),
      .wb_adr_i (wb_adr[$clog2(MEMORY_SIZE)-1:0]),
      .wb_stb_i (wb_stb),
      .wb_cyc_i (wb_cyc),
      .wb_cti_i (wb_cti),
      .wb_bte_i (wb_bte),
      .wb_we_i  (wb_we) ,
      .wb_sel_i (wb_sel),
      .wb_dat_i (wb_dat),
      .wb_dat_o (wb_rdt),
      .wb_ack_o (wb_ack),
      .wb_err_o ());
   
endmodule