data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/timer_interface.v
1: b"%Error: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/timer_interface.v:52: Cannot find file containing module: 'clock_scaler'\n clock_scaler clock_scaler(clk, clk_scaled); \n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1,data/full_repos/permissive/172396252/clock_scaler\n             data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1,data/full_repos/permissive/172396252/clock_scaler.v\n             data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1,data/full_repos/permissive/172396252/clock_scaler.sv\n             clock_scaler\n             clock_scaler.v\n             clock_scaler.sv\n             obj_dir/clock_scaler\n             obj_dir/clock_scaler.v\n             obj_dir/clock_scaler.sv\n%Error: Exiting due to 1 error(s)\n"
module timer_interface(
    input rst_n,
    input clk,
    input read_enable,
    input write_enable,
    inout [31:0] data_bus,
    input [19:0] address_bus,
    output timer_irq_n
    );

	reg [1:0] control = 0;
	reg [15:0] load = 0;
	reg [15:0] count = 0;
	reg [1:0] ack = 0;
	reg run_again = 0;

	wire timer_enabled = control[0];
	wire auto_restart = control[1];

	reg [15:0] data;
	assign data_bus = read_enable ? {16'h0000,data} : 32'hzzzzzzzz;
	assign timer_irq_n = ack == 0;

	wire clk_scaled;
	reg has_set_ack = 0;
	reg has_decremented = 0;


	clock_scaler clock_scaler(clk, clk_scaled); 

	always @(posedge clk) begin
		if (!rst_n) begin
			control = 0;
			load = 0;
			ack = 0;
			data = 0;
			has_decremented = 0;
			count = 0;
			run_again = 1;
		end
		

		if (timer_enabled) begin

			has_decremented = clk_scaled & has_decremented;
			

			if (clk_scaled && !has_decremented && count != 0) begin
				count = count - 1;
				has_decremented = 1;

				if (count == 0) begin
					ack = {auto_restart && ack[0] == 1, 1'b1};
					control = {2{control[1]}};
				end
			end

			if (count == 0 && (run_again || auto_restart)) begin
				count = load;
				run_again = auto_restart;
			end
		end

		else begin
			run_again = 1;
		end



		data <= 16'h0000;
		case (address_bus[12:0])
			0: begin
				if (write_enable)
					control = data_bus[1:0];
				else data[1:0] = control;
			end
			1: begin
				if (write_enable)
					load <= data_bus[15:0];
				else data[15:0] <= load;
			end
			2: begin
				data[15:0] = count;
			end
			3: begin
				if (write_enable)
					ack = data_bus[1:0];
				else data[1:0] = ack;
			end
		endcase
	end

endmodule
module timer_interface(
    input rst_n,
    input clk,
    input read_enable,
    input write_enable,
    inout [31:0] data_bus,
    input [19:0] address_bus,
    output timer_irq_n
    );


	reg [1:0] control = 0;
	reg [15:0] load = 0;
	reg [15:0] count = 0;
	reg [1:0] ack = 0;
	reg run_again = 0;

	wire timer_enabled = control[0];
	wire auto_restart = control[1];

	reg [15:0] data;
	assign data_bus = read_enable ? {16'h0000,data} : 32'hzzzzzzzz;
	assign timer_irq_n = ack == 0;

	wire clk_scaled;
	reg has_set_ack = 0;
	reg has_decremented = 0;


	clock_scaler clock_scaler(clk, clk_scaled); 

	always @(posedge clk) begin
		if (!rst_n) begin
			control = 0;
			load = 0;
			ack = 0;
			data = 0;
			has_decremented = 0;
			count = 0;
			run_again = 1;
		end
		

		if (timer_enabled) begin

			has_decremented = clk_scaled & has_decremented;
			

			if (clk_scaled && !has_decremented && count != 0) begin
				count = count - 1;
				has_decremented = 1;

				if (count == 0) begin
					ack = {auto_restart && ack[0] == 1, 1'b1};
					control = {2{control[1]}};
				end
			end

			if (count == 0 && (run_again || auto_restart)) begin
				count = load;
				run_again = auto_restart;
			end
		end

		else begin
			run_again = 1;
		end



		data <= 16'h0000;
		case (address_bus[12:0])
			0: begin
				if (write_enable)
					control = data_bus[1:0];
				else data[1:0] = control;
			end
			1: begin
				if (write_enable)
					load <= data_bus[15:0];
				else data[15:0] <= load;
			end
			2: begin
				data[15:0] = count;
			end
			3: begin
				if (write_enable)
					ack = data_bus[1:0];
				else data[1:0] = ack;
			end
		endcase
	end

endmodule