data/full_repos/permissive/16552133/src/verilog/Karpentium_Processor_III.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/16552133/src/verilog/Karpentium_Processor_III.v:41: Signal definition not found, creating implicitly: \'en0\'\n                                                                                                : ... Suggested alternative: \'en\'\n  out = en0 ? dataBUS : 16\'hZZ;\n        ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/16552133/src/verilog/Karpentium_Processor_III.v:46: Signal definition not found, creating implicitly: \'s2\'\n                                                                                                : ... Suggested alternative: \'c2\'\n assign MAR_in = (s2) ? dataBUS[5:0] : dataBUS[5:0];\n                  ^~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_Processor_III.v:31: Cannot find file containing module: \'controller\'\n controller Controller(clk,clr,OPCODE,c0,c1,c2,c3,c4,en0,en1,en2,en3,en4,en5,en6,en7,s1,s2);\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/16552133/src/verilog,data/full_repos/permissive/16552133/controller\n             data/full_repos/permissive/16552133/src/verilog,data/full_repos/permissive/16552133/controller.v\n             data/full_repos/permissive/16552133/src/verilog,data/full_repos/permissive/16552133/controller.sv\n             controller\n             controller.v\n             controller.sv\n             obj_dir/controller\n             obj_dir/controller.v\n             obj_dir/controller.sv\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_Processor_III.v:32: Cannot find file containing module: \'program_counter\'\n program_counter PC(clk,dataBUS[5:0],PC_out,c0,clr);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_Processor_III.v:33: Cannot find file containing module: \'program_memory\'\n program_memory #(6,16) PM(clk,PC_out,dataBUS,en3);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_Processor_III.v:34: Cannot find file containing module: \'instruction_register\'\n instruction_register IR (clk,dataBUS,dataBUS,OPCODE,c3,en5,clr);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_Processor_III.v:35: Cannot find file containing module: \'memory_address_register\'\n memory_address_register MAR(clk,MAR_in,MAR_out,c2);\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_Processor_III.v:36: Cannot find file containing module: \'memory_data_register\'\n memory_data_register MDR (clk,RAMio,dataBUS,c4,en6,clr);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_Processor_III.v:37: Cannot find file containing module: \'alu_with_acc\'\n alu_with_acc ALU (clk,dataBUS,dataBUS,s1,en4);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_Processor_III.v:38: Cannot find file containing module: \'random_access_memory\'\n random_access_memory #(6,16) RAM(clk,MAR_out,RAMio,en7,clr,c1);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n'
module Karpentium_Processor(clk,clr,in,out,en);
	input clk,clr,en;
	input [15:0]in;
	output [15:0]out;
	

	reg [15:0]rIn;
	reg [15:0]out;
	

	wire [2:0]s1;
	wire [3:0]OPCODE;
	wire [5:0]PC_out,MAR_in,MAR_out;
	wire [1:0]c0,c4;
	wire c1,c2,c3;
	wire [15:0]acc,RAMio;

	wire [15:0]dataBUS;
	
	controller Controller(clk,clr,OPCODE,c0,c1,c2,c3,c4,en0,en1,en2,en3,en4,en5,en6,en7,s1,s2);
	program_counter PC(clk,dataBUS[5:0],PC_out,c0,clr);
	program_memory #(6,16) PM(clk,PC_out,dataBUS,en3);
	instruction_register IR (clk,dataBUS,dataBUS,OPCODE,c3,en5,clr);
	memory_address_register MAR(clk,MAR_in,MAR_out,c2);
	memory_data_register MDR (clk,RAMio,dataBUS,c4,en6,clr);
	alu_with_acc ALU (clk,dataBUS,dataBUS,s1,en4);
	random_access_memory #(6,16) RAM(clk,MAR_out,RAMio,en7,clr,c1);
	
	always @(posedge clk) begin
		out = en0 ? dataBUS : 16'hZZ;
		rIn = in;
	end
	

	assign MAR_in = (s2) ? dataBUS[5:0] : dataBUS[5:0];
	
endmodule
module Karpentium_Processor(clk,clr,in,out,en);

	input clk,clr,en;
	input [15:0]in;
	output [15:0]out;
	

	reg [15:0]rIn;
	reg [15:0]out;
	

	wire [2:0]s1;
	wire [3:0]OPCODE;
	wire [5:0]PC_out,MAR_in,MAR_out;
	wire [1:0]c0,c4;
	wire c1,c2,c3;
	wire [15:0]acc,RAMio;

	wire [15:0]dataBUS;
	
	controller Controller(clk,clr,OPCODE,c0,c1,c2,c3,c4,en0,en1,en2,en3,en4,en5,en6,en7,s1,s2);
	program_counter PC(clk,dataBUS[5:0],PC_out,c0,clr);
	program_memory #(6,16) PM(clk,PC_out,dataBUS,en3);
	instruction_register IR (clk,dataBUS,dataBUS,OPCODE,c3,en5,clr);
	memory_address_register MAR(clk,MAR_in,MAR_out,c2);
	memory_data_register MDR (clk,RAMio,dataBUS,c4,en6,clr);
	alu_with_acc ALU (clk,dataBUS,dataBUS,s1,en4);
	random_access_memory #(6,16) RAM(clk,MAR_out,RAMio,en7,clr,c1);
	
	always @(posedge clk) begin
		out = en0 ? dataBUS : 16'hZZ;
		rIn = in;
	end
	

	assign MAR_in = (s2) ? dataBUS[5:0] : dataBUS[5:0];
	
endmodule