data/full_repos/permissive/200104480/Processor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:440: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'singleBit\' generates 1 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.A.ze\n assign dataOut = 32\'b0 + singleBit;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:361: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'dataIn\' generates 16 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.ZE\n assign dataOut = 32\'b0 + dataIn;\n                        ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ControlUnit(input [5:0] opcode,
			input [5:0] funct,
			output reg MemtoReg,
			output reg MemWrite,
			output reg BranchEQ,
			output reg BranchNE,
			output reg [1:0] ALUSrc,
			output reg RegDst,
			output reg RegWrite,
			output reg Jump,
			output reg [2:0] ALUControl);
			
	always @(opcode, funct)
	begin
		MemtoReg = 1'b0;
		MemWrite = 1'b0;
		BranchEQ = 1'b0;
		BranchNE = 1'b0;
		ALUSrc = 2'b00;
		RegDst = 1'b0;
		RegWrite = 1'b0;
		Jump = 1'b0;
		ALUControl = 3'b000;
		if (opcode == 6'b000000)
		begin
			RegWrite = 1'b1;
			RegDst = 1'b1;
			case (funct)
				6'b100000: ALUControl = 3'b010;
				6'b100010: ALUControl = 3'b110;
				6'b100100: ALUControl = 3'b000;
				6'b100101: ALUControl = 3'b001;
				6'b101010: ALUControl = 3'b111;
				default: ALUControl = 3'bxxx;
			endcase
		end
		else
		begin
			case (opcode)

				6'b100011:
				begin
					RegWrite = 1'b1;
					ALUSrc = 2'b01;
					MemtoReg = 1'b1;
					ALUControl = 3'b010;
				end

				6'b101011:
				begin
					RegDst = 1'bx;
					ALUSrc = 2'b01;
					MemWrite = 1'b1;
					MemtoReg = 1'bx;
					ALUControl = 3'b010;
				end

				6'b000100:
				begin
					RegDst = 1'bx;
					BranchEQ = 1'b1;
					MemtoReg = 1'bx;
					ALUControl = 3'b110;
				end

				6'b001000:
				begin
					RegWrite = 1'b1;
					ALUSrc = 2'b01;
					ALUControl = 3'b010;
				end

				6'b000010:
				begin
					RegDst = 1'bx;
					ALUSrc = 2'bxx;
					BranchEQ = 1'bx;
					MemtoReg = 1'bx;
					Jump= 1'b1;
				end

				6'b001101:
				begin
					RegWrite = 1'b1;
					ALUSrc = 2'b01;
					ALUControl = 3'b001;
				end

				6'b001100:
				begin
					RegWrite = 1'b1;
					ALUSrc = 2'b01;
					ALUControl = 3'b000;
				end

				6'b001010:
				begin
					RegWrite = 1'b1;
					ALUSrc = 2'b01;
					ALUControl = 3'b111;
				end

				6'b000101:
				begin
					RegDst = 1'bx;
					BranchNE = 1'b1;
					MemtoReg = 1'bx;
					ALUControl = 3'b110;
				end

				6'b001001:
				begin
					RegWrite = 1'b1;
					ALUSrc = 2'b10;
					ALUControl = 3'b010;
				end
				default:
				begin
					MemtoReg = 1'bx;
					MemWrite = 1'bx;
					BranchEQ = 1'bx;
					ALUSrc = 2'bxx;
					RegDst = 1'bx;
					RegWrite = 1'bx;
					Jump= 1'bx;
					ALUControl = 3'bxxx;
				end
			endcase
		end
	end
endmodule
module ControlUnit(input [5:0] opcode,
			input [5:0] funct,
			output reg MemtoReg,
			output reg MemWrite,
			output reg BranchEQ,
			output reg BranchNE,
			output reg [1:0] ALUSrc,
			output reg RegDst,
			output reg RegWrite,
			output reg Jump,
			output reg [2:0] ALUControl);

			
	always @(opcode, funct)
	begin
		MemtoReg = 1'b0;
		MemWrite = 1'b0;
		BranchEQ = 1'b0;
		BranchNE = 1'b0;
		ALUSrc = 2'b00;
		RegDst = 1'b0;
		RegWrite = 1'b0;
		Jump = 1'b0;
		ALUControl = 3'b000;
		if (opcode == 6'b000000)
		begin
			RegWrite = 1'b1;
			RegDst = 1'b1;
			case (funct)
				6'b100000: ALUControl = 3'b010;
				6'b100010: ALUControl = 3'b110;
				6'b100100: ALUControl = 3'b000;
				6'b100101: ALUControl = 3'b001;
				6'b101010: ALUControl = 3'b111;
				default: ALUControl = 3'bxxx;
			endcase
		end
		else
		begin
			case (opcode)

				6'b100011:
				begin
					RegWrite = 1'b1;
					ALUSrc = 2'b01;
					MemtoReg = 1'b1;
					ALUControl = 3'b010;
				end

				6'b101011:
				begin
					RegDst = 1'bx;
					ALUSrc = 2'b01;
					MemWrite = 1'b1;
					MemtoReg = 1'bx;
					ALUControl = 3'b010;
				end

				6'b000100:
				begin
					RegDst = 1'bx;
					BranchEQ = 1'b1;
					MemtoReg = 1'bx;
					ALUControl = 3'b110;
				end

				6'b001000:
				begin
					RegWrite = 1'b1;
					ALUSrc = 2'b01;
					ALUControl = 3'b010;
				end

				6'b000010:
				begin
					RegDst = 1'bx;
					ALUSrc = 2'bxx;
					BranchEQ = 1'bx;
					MemtoReg = 1'bx;
					Jump= 1'b1;
				end

				6'b001101:
				begin
					RegWrite = 1'b1;
					ALUSrc = 2'b01;
					ALUControl = 3'b001;
				end

				6'b001100:
				begin
					RegWrite = 1'b1;
					ALUSrc = 2'b01;
					ALUControl = 3'b000;
				end

				6'b001010:
				begin
					RegWrite = 1'b1;
					ALUSrc = 2'b01;
					ALUControl = 3'b111;
				end

				6'b000101:
				begin
					RegDst = 1'bx;
					BranchNE = 1'b1;
					MemtoReg = 1'bx;
					ALUControl = 3'b110;
				end

				6'b001001:
				begin
					RegWrite = 1'b1;
					ALUSrc = 2'b10;
					ALUControl = 3'b010;
				end
				default:
				begin
					MemtoReg = 1'bx;
					MemWrite = 1'bx;
					BranchEQ = 1'bx;
					ALUSrc = 2'bxx;
					RegDst = 1'bx;
					RegWrite = 1'bx;
					Jump= 1'bx;
					ALUControl = 3'bxxx;
				end
			endcase
		end
	end
endmodule