data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:93: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance marsohod2\nreg  [1:0]  awm = 1\'b0;\n                  ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:101: Cannot find file containing module: \'biosrom\'\nbiosrom BIOSROM(  \n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/projects/07_reduced86,data/full_repos/permissive/136510272/biosrom\n             data/full_repos/permissive/136510272/projects/07_reduced86,data/full_repos/permissive/136510272/biosrom.v\n             data/full_repos/permissive/136510272/projects/07_reduced86,data/full_repos/permissive/136510272/biosrom.sv\n             biosrom\n             biosrom.v\n             biosrom.sv\n             obj_dir/biosrom\n             obj_dir/biosrom.v\n             obj_dir/biosrom.sv\n%Error: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:114: Cannot find file containing module: \'comram\'\ncomram COMMONRAM(  \n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:130: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                          : ... In instance marsohod2\nreg [7:0]   ps2_command = 1\'b0;\n                          ^~~~\n%Error: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:139: Cannot find file containing module: \'PS2_Controller\'\nPS2_Controller Keyboard(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:169: Cannot find file containing module: \'port_controller\'\nport_controller PortCTRL(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:203: Cannot find file containing module: \'vga\'\nvga VGA_ADAPTER(\n^~~\n%Error: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:225: Cannot find file containing module: \'fontrom\'\nfontrom VGA_FONT_ROM(\n^~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:234: Cannot find file containing module: \'fontram\'\nfontram VGA_VIDEORAM(\n^~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:277: Cannot find file containing module: \'cpu\'\ncpu CPU(  \n^~~\n%Error: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:306: Cannot find file containing module: \'pll\'\npll PLL(\n^~~\n%Error: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:326: Cannot find file containing module: \'serial\'\nserial SERIAL(\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:335: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                          : ... In instance marsohod2\nreg [7:0]  prg_idata = 1\'b0;   \n                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:336: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                          : ... In instance marsohod2\nreg [13:0] prg_addr = 1\'b0;    \n                      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:353: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                          : ... In instance marsohod2\n        prg_addr   <= 16\'h0000;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/marsohod2.v:359: Operator EQ expects 16 bits on the LHS, but LHS\'s VARREF \'prg_addr\' generates 14 bits.\n                                                                                          : ... In instance marsohod2\n        if (prg_addr == 16\'h3FFE)   begin\n                     ^~\n%Error: Exiting due to 10 error(s), 6 warning(s)\n'
module marsohod2(




    input   wire        clk,


    output  reg  [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);



reg [1:0] div = 2'b00;
reg cpu_latency = 1'b0;
reg clk25 = 1'b0;

always @(posedge clk) begin

    div <= div + 1'b1;


    if (cpu_latency) begin


	    clk25 <= div[1];


	end else if (div == 2'b11) begin

	    cpu_latency <= 1'b1;
        kbd_reset   <= 1'b0;


    end else begin

        kbd_reset   <= 1'b1;

    end

end

wire [15:0] a;
reg  [7:0]  i;
wire [7:0]  o;
wire w;
reg  [1:0]  awm = 1'b0;

wire [7:0]  q_rom;
wire [7:0]  q_ram;
wire [7:0]  q_vid;
reg         wren_vram;
reg         wren_cram;

biosrom BIOSROM(

    .clock   (clk),
    .addr_rd (a[13:0]),
    .q       (q_rom),


    .addr_wr (prg_addr),
    .data_wr (prg_idata),
    .wren    (prg_wren && prg_negedge == 2'b10),

);

comram COMMONRAM(

    .clock   (clk),
    .addr_rd (a[13:0]),
    .q       (q_ram),

    .addr_wr (a[13:0]),
    .data_wr (o),
    .wren    (wren_cram),
);



reg         kbd_reset = 1'b0;
reg [7:0]   ps2_command = 1'b0;
reg         ps2_command_send = 1'b0;
wire        ps2_command_was_sent;
wire        ps2_error_communication_timed_out;
wire [7:0]  ps2_data;
wire        ps2_data_clk;

always @(posedge div[0]) if (ps2_data_clk) led[3:1] <= ps2_data[2:0];

PS2_Controller Keyboard(


    .CLOCK_50       (div[0]),
	.reset          (kbd_reset),
	.the_command    (ps2_command),
	.send_command   (ps2_command_send),


	.PS2_CLK(ps2_keyb[1]),
 	.PS2_DAT(ps2_keyb[0]),


	.command_was_sent  (ps2_command_was_sent),
	.error_communication_timed_out (ps2_error_communication_timed_out),


	.received_data      (ps2_data),
	.received_data_en   (ps2_data_clk)

);

wire [15:0] port_addr;
wire [15:0] port_in;
wire [15:0] port_out;
wire        port_bit;
wire        port_clk;
wire        port_read;


port_controller PortCTRL(

    .clock50    (div[0]),
    .port_addr  (port_addr),
    .port_in    (port_in),
    .port_out   (port_out),
    .port_bit   (port_bit),
    .port_clk   (port_clk),
    .port_read  (port_read),


    .ps2_data     (ps2_data),
    .ps2_data_clk (ps2_data_clk),
    

    .cursor      (cursor)

);






wire [11:0] adapter_font;
wire [ 7:0] adapter_data;
wire [11:0] font_char_addr;
wire [ 7:0] font_char_data;
wire [10:0] cursor;





vga VGA_ADAPTER(

	.clk	(clk),
	.red 	(vga_red),
	.green	(vga_green),
	.blue	(vga_blue),
	.hs		(vga_hs),
	.vs		(vga_vs),


    .adapter_font (adapter_font),
    .adapter_data (adapter_data),


    .font_char_addr (font_char_addr),
    .font_char_data (font_char_data),
    
    .cursor (cursor)

);


fontrom VGA_FONT_ROM(

    .clock      (clk),
    .addr_rd    (adapter_font),

    .q          (adapter_data)
);


fontram VGA_VIDEORAM(

    .clock      (clk),
    .addr_rd    (font_char_addr),
    .q          (font_char_data),


    .addr_wr    (a[11:0]),
    .data_wr    (o),
    .wren       (wren_vram),
    .qw         (q_vid),
);



always @(posedge clk) begin awm[1:0] <= {awm[0], clk25}; end


wire awf = (awm == 2'b01);


always @* begin

    casex (a)


        16'b00xx_xxxx_xxxx_xxxx: begin i = q_ram; {wren_vram, wren_cram} = {1'b0, w && awf}; end


        16'b1011_xxxx_xxxx_xxxx: begin i = q_vid; {wren_vram, wren_cram} = {w && awf, 1'b0}; end


        16'b11xx_xxxx_xxxx_xxxx: begin i = q_rom; {wren_vram, wren_cram} = 2'b00; end


        default: begin i = 8'h00; {wren_vram, wren_cram} = 2'b00; end

    endcase

end



cpu CPU(

    prg_enable | ~keys[0],
    (clk),
    (clk25 && cpu_latency),
    i,
    o,
    a,
    w,


    port_addr,
    port_in,
    port_out,
    port_bit,
    port_clk,
    port_read

);



wire locked;
wire clock_25;
wire clock_12;
wire clock_6;

pll PLL(

    .clk        (clk),
    .locked     (locked),
    .c0         (clock_25),
    .c1         (clock_12),
    .c2         (clock_6)

);



wire [7:0]  rx_byte;
wire        rx_ready;
wire        clk12;
reg         rom_bank_wr;

serial SERIAL(

	.clk12    (locked & clock_12),
	.rx       (ftdi_rx),
	.rx_byte  (rx_byte),
	.rx_ready (rx_ready)

);

reg [7:0]  prg_idata = 1'b0;
reg [13:0] prg_addr = 1'b0;
reg        prg_wren = 1'b0;
reg        prg_enable = 1'b0;
reg [1:0]  prg_negedge = 2'b00;


always @(posedge clk) prg_negedge <= {prg_negedge[0], rx_ready};


always @(posedge rx_ready) begin

    prg_idata <= rx_byte;

    if (prg_enable == 1'b0) begin

        prg_enable <= 1'b1;
        prg_wren   <= 1'b1;
        prg_addr   <= 16'h0000;
        led[0]     <= 1'b1;

    end
    else begin

        if (prg_addr == 16'h3FFE)begin
            prg_enable <= 1'b0;
            prg_wren   <= 1'b0;
            led[0]     <= 1'b0;
        end

        prg_addr <= prg_addr + 1'b1;

    end

end

endmodule
module marsohod2(




    input   wire        clk,


    output  reg  [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);




reg [1:0] div = 2'b00;
reg cpu_latency = 1'b0;
reg clk25 = 1'b0;

always @(posedge clk) begin

    div <= div + 1'b1;


    if (cpu_latency) begin


	    clk25 <= div[1];


	end else if (div == 2'b11) begin

	    cpu_latency <= 1'b1;
        kbd_reset   <= 1'b0;


    end else begin

        kbd_reset   <= 1'b1;

    end

end

wire [15:0] a;
reg  [7:0]  i;
wire [7:0]  o;
wire w;
reg  [1:0]  awm = 1'b0;

wire [7:0]  q_rom;
wire [7:0]  q_ram;
wire [7:0]  q_vid;
reg         wren_vram;
reg         wren_cram;

biosrom BIOSROM(

    .clock   (clk),
    .addr_rd (a[13:0]),
    .q       (q_rom),


    .addr_wr (prg_addr),
    .data_wr (prg_idata),
    .wren    (prg_wren && prg_negedge == 2'b10),

);

comram COMMONRAM(

    .clock   (clk),
    .addr_rd (a[13:0]),
    .q       (q_ram),

    .addr_wr (a[13:0]),
    .data_wr (o),
    .wren    (wren_cram),
);



reg         kbd_reset = 1'b0;
reg [7:0]   ps2_command = 1'b0;
reg         ps2_command_send = 1'b0;
wire        ps2_command_was_sent;
wire        ps2_error_communication_timed_out;
wire [7:0]  ps2_data;
wire        ps2_data_clk;

always @(posedge div[0]) if (ps2_data_clk) led[3:1] <= ps2_data[2:0];

PS2_Controller Keyboard(


    .CLOCK_50       (div[0]),
	.reset          (kbd_reset),
	.the_command    (ps2_command),
	.send_command   (ps2_command_send),


	.PS2_CLK(ps2_keyb[1]),
 	.PS2_DAT(ps2_keyb[0]),


	.command_was_sent  (ps2_command_was_sent),
	.error_communication_timed_out (ps2_error_communication_timed_out),


	.received_data      (ps2_data),
	.received_data_en   (ps2_data_clk)

);

wire [15:0] port_addr;
wire [15:0] port_in;
wire [15:0] port_out;
wire        port_bit;
wire        port_clk;
wire        port_read;


port_controller PortCTRL(

    .clock50    (div[0]),
    .port_addr  (port_addr),
    .port_in    (port_in),
    .port_out   (port_out),
    .port_bit   (port_bit),
    .port_clk   (port_clk),
    .port_read  (port_read),


    .ps2_data     (ps2_data),
    .ps2_data_clk (ps2_data_clk),
    

    .cursor      (cursor)

);






wire [11:0] adapter_font;
wire [ 7:0] adapter_data;
wire [11:0] font_char_addr;
wire [ 7:0] font_char_data;
wire [10:0] cursor;





vga VGA_ADAPTER(

	.clk	(clk),
	.red 	(vga_red),
	.green	(vga_green),
	.blue	(vga_blue),
	.hs		(vga_hs),
	.vs		(vga_vs),


    .adapter_font (adapter_font),
    .adapter_data (adapter_data),


    .font_char_addr (font_char_addr),
    .font_char_data (font_char_data),
    
    .cursor (cursor)

);


fontrom VGA_FONT_ROM(

    .clock      (clk),
    .addr_rd    (adapter_font),

    .q          (adapter_data)
);


fontram VGA_VIDEORAM(

    .clock      (clk),
    .addr_rd    (font_char_addr),
    .q          (font_char_data),


    .addr_wr    (a[11:0]),
    .data_wr    (o),
    .wren       (wren_vram),
    .qw         (q_vid),
);



always @(posedge clk) begin awm[1:0] <= {awm[0], clk25}; end


wire awf = (awm == 2'b01);


always @* begin

    casex (a)


        16'b00xx_xxxx_xxxx_xxxx: begin i = q_ram; {wren_vram, wren_cram} = {1'b0, w && awf}; end


        16'b1011_xxxx_xxxx_xxxx: begin i = q_vid; {wren_vram, wren_cram} = {w && awf, 1'b0}; end


        16'b11xx_xxxx_xxxx_xxxx: begin i = q_rom; {wren_vram, wren_cram} = 2'b00; end


        default: begin i = 8'h00; {wren_vram, wren_cram} = 2'b00; end

    endcase

end



cpu CPU(

    prg_enable | ~keys[0],
    (clk),
    (clk25 && cpu_latency),
    i,
    o,
    a,
    w,


    port_addr,
    port_in,
    port_out,
    port_bit,
    port_clk,
    port_read

);



wire locked;
wire clock_25;
wire clock_12;
wire clock_6;

pll PLL(

    .clk        (clk),
    .locked     (locked),
    .c0         (clock_25),
    .c1         (clock_12),
    .c2         (clock_6)

);



wire [7:0]  rx_byte;
wire        rx_ready;
wire        clk12;
reg         rom_bank_wr;

serial SERIAL(

	.clk12    (locked & clock_12),
	.rx       (ftdi_rx),
	.rx_byte  (rx_byte),
	.rx_ready (rx_ready)

);

reg [7:0]  prg_idata = 1'b0;
reg [13:0] prg_addr = 1'b0;
reg        prg_wren = 1'b0;
reg        prg_enable = 1'b0;
reg [1:0]  prg_negedge = 2'b00;


always @(posedge clk) prg_negedge <= {prg_negedge[0], rx_ready};


always @(posedge rx_ready) begin

    prg_idata <= rx_byte;

    if (prg_enable == 1'b0) begin

        prg_enable <= 1'b1;
        prg_wren   <= 1'b1;
        prg_addr   <= 16'h0000;
        led[0]     <= 1'b1;

    end
    else begin

        if (prg_addr == 16'h3FFE)begin
            prg_enable <= 1'b0;
            prg_wren   <= 1'b0;
            led[0]     <= 1'b0;
        end

        prg_addr <= prg_addr + 1'b1;

    end

end

endmodule