data/full_repos/permissive/184916587/ALU_RECV.v
data/verilator_xmls/11c131a4-5f02-45c9-b967-521eab3318de.xml
module sltu_32(
	input[31:0] sltu_rs1,
	input[31:0] sltu_rs2,
	output reg[31:0] sltu_rd
);

	always @(*)
	begin
		if(sltu_rs1[30:0]<sltu_rs2[30:0])
			sltu_rd=32'b11111111111111111111111111111111;
		else begin
			sltu_rd=32'b00000000000000000000000000000000;
		end
	end
endmodule
module sltu_32(
	input[31:0] sltu_rs1,
	input[31:0] sltu_rs2,
	output reg[31:0] sltu_rd
);


	always @(*)
	begin
		if(sltu_rs1[30:0]<sltu_rs2[30:0])
			sltu_rd=32'b11111111111111111111111111111111;
		else begin
			sltu_rd=32'b00000000000000000000000000000000;
		end
	end
endmodule