data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Seg7.v
'utf-8' codec can't decode byte 0xca in position 536: invalid continuation byte
1: b'%Warning-SELRANGE: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Seg7.v:28: Selection index out of range: 14:11 outside 3:0\n                                                                                       : ... In instance Seg7\n case(led[14:11])\n         ^\n                   ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Warning-SELRANGE: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Seg7.v:28: Selection index out of range: 6:3 outside 3:0\n                                                                                       : ... In instance Seg7\n case(led[14:11])\n         ^\n%Error: Exiting due to 2 warning(s)\n'
module Seg7(led,seg);
	input  [3:0] led;
	output reg [7:0] seg;
	
always@(1) begin
	case(led[14:11])
	    4'b0000:seg = 8'b11000000;
	    4'b0001:seg = 8'b11111001;
	    4'b0010: seg = 8'b10100100;
	    4'b0011: seg = 8'b10110000;
	    4'b0100: seg = 8'b10011001;
	    4'b0101: seg = 8'b10010010;
	    4'b0110: seg = 8'b10000010;
	    4'b0111: seg = 8'b11111000;
	    4'b1000:seg = 8'b10000000;
        4'b1001:seg = 8'b10011000;
        4'b1010: seg = 8'b10001000;
        4'b1011: seg = 8'b10000011;
        4'b1100: seg = 8'b11000110;
        4'b1101: seg = 8'b10100001;
        4'b1110: seg = 8'b10000110;
        4'b1111: seg = 8'b10001110;	    
	endcase
end	
endmodule
module Seg7(led,seg);

	input  [3:0] led;
	output reg [7:0] seg;
	
always@(1) begin
	case(led[14:11])
	    4'b0000:seg = 8'b11000000;
	    4'b0001:seg = 8'b11111001;
	    4'b0010: seg = 8'b10100100;
	    4'b0011: seg = 8'b10110000;
	    4'b0100: seg = 8'b10011001;
	    4'b0101: seg = 8'b10010010;
	    4'b0110: seg = 8'b10000010;
	    4'b0111: seg = 8'b11111000;
	    4'b1000:seg = 8'b10000000;
        4'b1001:seg = 8'b10011000;
        4'b1010: seg = 8'b10001000;
        4'b1011: seg = 8'b10000011;
        4'b1100: seg = 8'b11000110;
        4'b1101: seg = 8'b10100001;
        4'b1110: seg = 8'b10000110;
        4'b1111: seg = 8'b10001110;	    
	endcase
end	
endmodule