data/full_repos/permissive/125927162/UART/UART_TX_tb.v
 line:54: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_TX_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk = !clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/125927162/UART/UART_TX_tb.v:43: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("UART_TX.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/UART/UART_TX_tb.v:44: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, DUT);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_TX_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #2\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_TX_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_TX_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #3\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/UART/UART_TX_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n      #2000\n      ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UART_TX_tb();
   localparam BITS = 8;
   localparam STOPBITS = 1;
   localparam PARITY = 2;

   reg clk;
   reg rst;
   reg data_ready;
   
   wire rx;
   wire data_sent;
   
   reg [BITS - 1:0] data = 8'b01010111;
   
   UART_TX #(.BITS(BITS), .STOPBITS(STOPBITS), .PARITY(PARITY))
   DUT(
       .clk(clk),
       .rst(rst),
       .tx(rx),
       .data_ready(data_ready),
       .data(data),
       .data_sent(data_sent)
       );

   always #1 clk = !clk;
   
   initial begin
      $dumpfile("UART_TX.vcd");
      $dumpvars(0, DUT);
      clk = 0;
      rst = 1;
      #2
	rst = 0;
      #1
	data_ready = 1;
      #3
	data_ready = 0;
      #2000
      $finish;   
   end

   
endmodule
module UART_TX_tb();

   localparam BITS = 8;
   localparam STOPBITS = 1;
   localparam PARITY = 2;

   reg clk;
   reg rst;
   reg data_ready;
   
   wire rx;
   wire data_sent;
   
   reg [BITS - 1:0] data = 8'b01010111;
   
   UART_TX #(.BITS(BITS), .STOPBITS(STOPBITS), .PARITY(PARITY))
   DUT(
       .clk(clk),
       .rst(rst),
       .tx(rx),
       .data_ready(data_ready),
       .data(data),
       .data_sent(data_sent)
       );

   always #1 clk = !clk;
   
   initial begin
      $dumpfile("UART_TX.vcd");
      $dumpvars(0, DUT);
      clk = 0;
      rst = 1;
      #2
	rst = 0;
      #1
	data_ready = 1;
      #3
	data_ready = 0;
      #2000
      $finish;   
   end

   
endmodule