data/full_repos/permissive/109209652/verilog/convolve_census/convolve.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/109209652/verilog/convolve_census/convolve.v:62: Operator OR expects 1600 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                          : ... In instance convolve\n    is_buf_val <= (is_buf_val << 1) |  1\'b1;\n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109209652/verilog/convolve_census/convolve.v:90: Cannot find file containing module: \'shift_reg\'\n          shift_reg #(8, ROW_SZ-KRNL_SZ) row_shift_buf(\n          ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109209652/verilog/convolve_census,data/full_repos/permissive/109209652/shift_reg\n             data/full_repos/permissive/109209652/verilog/convolve_census,data/full_repos/permissive/109209652/shift_reg.v\n             data/full_repos/permissive/109209652/verilog/convolve_census,data/full_repos/permissive/109209652/shift_reg.sv\n             shift_reg\n             shift_reg.v\n             shift_reg.sv\n             obj_dir/shift_reg\n             obj_dir/shift_reg.v\n             obj_dir/shift_reg.sv\n%Error: data/full_repos/permissive/109209652/verilog/convolve_census/convolve.v:80: Cannot find file containing module: \'shift_reg\'\n          shift_reg #(8, ROW_SZ-KRNL_SZ) row_shift_buf(\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/109209652/verilog/convolve_census/convolve.v:149: Cannot find file containing module: \'convolve_mult\'\n    convolve_mult my_mult(\n    ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module convolve #(parameter KRNL_SZ = 5, parameter ROW_SZ = 320, parameter COL_SZ = 240)(
	input		clk,
	input		reset,

	input		[7:0]	in_val,
	input		[9:0]	in_x,
	input		[9:0]	in_y,
	input				is_in_val,

	output		[7:0]	out_val,
	output	reg	[9:0]	out_x,
	output	reg	[9:0]	out_y,
	output	reg			is_out_val,







	input signed	[(KRNL_SZ*KRNL_SZ*8)-1 : 0] kernel
);



	reg		[7:0] conv_r [(KRNL_SZ*KRNL_SZ)-1 : 0];



	wire	[7:0] carry_over_wires [KRNL_SZ-2 : 0];



	reg		[(ROW_SZ*KRNL_SZ)-1 : 0] is_buf_val;



	reg		[9:0] in_x_reg;
	reg		[9:0] in_y_reg;

	always@ (posedge clk) begin
		if (is_in_val) begin
			in_x_reg <= in_x;
			in_y_reg <= in_y;
		end
	end


	wire		[9:0]	out_x_stg0;
	wire		[9:0]	out_y_stg0;
	assign out_x_stg0 = in_x_reg < (ROW_SZ-(KRNL_SZ/2)-1) ? (in_x_reg + ROW_SZ) - (ROW_SZ-(KRNL_SZ/2)-1) : in_x_reg - (ROW_SZ-(KRNL_SZ/2)-1);
	assign out_y_stg0 = out_x <= (KRNL_SZ/2) ? (in_y_reg < 1 ? COL_SZ-1 : in_y_reg-1) : (in_y_reg < 2 ? COL_SZ-2+in_y_reg : in_y_reg-2);


	always@ (posedge clk) begin
		if (reset) begin
			is_buf_val <= 0;
		end
		else begin
			if (is_in_val) begin
				is_buf_val <= (is_buf_val << 1) |  1'b1;
			end
		end
	end


	wire				is_out_val_stg0;
	assign is_out_val_stg0 = is_in_val & is_buf_val[ROW_SZ*(KRNL_SZ/2) + (ROW_SZ-KRNL_SZ) + (KRNL_SZ/2)];


	genvar i, j;
	generate
	    for (i = 0; i < KRNL_SZ; i = i + 1) begin: SHIFT_BUF
	    	wire [7:0] row_buf_sr_out;


	        if (i == KRNL_SZ-1) begin

	        	shift_reg #(8, ROW_SZ-KRNL_SZ) row_shift_buf(
					.clk(clk), 
					.shift(is_in_val),
					.sr_in(in_val),
					.sr_out(row_buf_sr_out)
				);
				
	        end
	        else begin
	        	
	        	shift_reg #(8, ROW_SZ-KRNL_SZ) row_shift_buf(
					.clk(clk), 
					.shift(is_in_val),
					.sr_in(carry_over_wires[i]),
					.sr_out(row_buf_sr_out)
				);

	        end


	        for (j = 0; j < KRNL_SZ; j = j + 1) begin: CONV_REGS

				if (j == 0) begin
					if(i != 0) begin
						assign carry_over_wires[i-1] = conv_r[KRNL_SZ*i + j];
					end

					always@ (posedge clk) begin
						if (is_in_val) begin
							conv_r[KRNL_SZ*i + j] <= conv_r[KRNL_SZ*i + (j+1)];
						end
					end

				end

				else if (j == KRNL_SZ-1) begin

					always@ (posedge clk) begin
						if (is_in_val) begin
							conv_r[KRNL_SZ*i + j] <= row_buf_sr_out;
						end
					end

				end
				else begin

					always@ (posedge clk) begin
						if (is_in_val) begin
							conv_r[KRNL_SZ*i + j] <= conv_r[KRNL_SZ*i + (j+1)];
						end
					end

				end
			end
	        
	    end
	endgenerate




	wire	signed	[15:0] mult [(KRNL_SZ*KRNL_SZ)-1 : 0];
	reg		signed	[15:0] mult_reg [(KRNL_SZ*KRNL_SZ)-1 : 0];
	genvar k, l;
	generate

		for (k = 0; k < KRNL_SZ; k = k + 1) begin: MULT_OUTER
			for (l = 0; l < KRNL_SZ; l = l + 1) begin: MULT_INNER
				
				convolve_mult my_mult(
					.out(mult[KRNL_SZ*k + l]),
					.a(conv_r[KRNL_SZ*k + l]),
					.b(kernel[((KRNL_SZ*KRNL_SZ - KRNL_SZ*k - l)*8 - 1) : (KRNL_SZ*KRNL_SZ - KRNL_SZ*k - l - 1)*8])
				);

				always @(posedge clk) begin
					mult_reg[KRNL_SZ*k + l] <= mult[KRNL_SZ*k + l];
				end
			end
		end

	endgenerate

	integer sum_i;



	always @(posedge clk) begin
		if (reset) begin
			out_x <= 0;
			out_y <= 0;
			is_out_val <= 0;
		end
		else begin
			out_x <= out_x_stg0;
			out_y <= out_y_stg0;
			is_out_val <= is_out_val_stg0;
		end
	end


	reg		signed	[15:0]	conv_sum;
	always@ (*) begin
	 	conv_sum = 16'b0;
		for(sum_i = 0; sum_i < (KRNL_SZ*KRNL_SZ); sum_i = sum_i + 1) begin
			conv_sum = conv_sum + mult_reg[sum_i];
		end
	end

	assign out_val = conv_sum[15] ? 8'd0 : conv_sum[11:4];

endmodule
module convolve #(parameter KRNL_SZ = 5, parameter ROW_SZ = 320, parameter COL_SZ = 240)(
	input		clk,
	input		reset,

	input		[7:0]	in_val,
	input		[9:0]	in_x,
	input		[9:0]	in_y,
	input				is_in_val,

	output		[7:0]	out_val,
	output	reg	[9:0]	out_x,
	output	reg	[9:0]	out_y,
	output	reg			is_out_val,







	input signed	[(KRNL_SZ*KRNL_SZ*8)-1 : 0] kernel
);




	reg		[7:0] conv_r [(KRNL_SZ*KRNL_SZ)-1 : 0];



	wire	[7:0] carry_over_wires [KRNL_SZ-2 : 0];



	reg		[(ROW_SZ*KRNL_SZ)-1 : 0] is_buf_val;



	reg		[9:0] in_x_reg;
	reg		[9:0] in_y_reg;

	always@ (posedge clk) begin
		if (is_in_val) begin
			in_x_reg <= in_x;
			in_y_reg <= in_y;
		end
	end


	wire		[9:0]	out_x_stg0;
	wire		[9:0]	out_y_stg0;
	assign out_x_stg0 = in_x_reg < (ROW_SZ-(KRNL_SZ/2)-1) ? (in_x_reg + ROW_SZ) - (ROW_SZ-(KRNL_SZ/2)-1) : in_x_reg - (ROW_SZ-(KRNL_SZ/2)-1);
	assign out_y_stg0 = out_x <= (KRNL_SZ/2) ? (in_y_reg < 1 ? COL_SZ-1 : in_y_reg-1) : (in_y_reg < 2 ? COL_SZ-2+in_y_reg : in_y_reg-2);


	always@ (posedge clk) begin
		if (reset) begin
			is_buf_val <= 0;
		end
		else begin
			if (is_in_val) begin
				is_buf_val <= (is_buf_val << 1) |  1'b1;
			end
		end
	end


	wire				is_out_val_stg0;
	assign is_out_val_stg0 = is_in_val & is_buf_val[ROW_SZ*(KRNL_SZ/2) + (ROW_SZ-KRNL_SZ) + (KRNL_SZ/2)];


	genvar i, j;
	generate
	    for (i = 0; i < KRNL_SZ; i = i + 1) begin: SHIFT_BUF
	    	wire [7:0] row_buf_sr_out;


	        if (i == KRNL_SZ-1) begin

	        	shift_reg #(8, ROW_SZ-KRNL_SZ) row_shift_buf(
					.clk(clk), 
					.shift(is_in_val),
					.sr_in(in_val),
					.sr_out(row_buf_sr_out)
				);
				
	        end
	        else begin
	        	
	        	shift_reg #(8, ROW_SZ-KRNL_SZ) row_shift_buf(
					.clk(clk), 
					.shift(is_in_val),
					.sr_in(carry_over_wires[i]),
					.sr_out(row_buf_sr_out)
				);

	        end


	        for (j = 0; j < KRNL_SZ; j = j + 1) begin: CONV_REGS

				if (j == 0) begin
					if(i != 0) begin
						assign carry_over_wires[i-1] = conv_r[KRNL_SZ*i + j];
					end

					always@ (posedge clk) begin
						if (is_in_val) begin
							conv_r[KRNL_SZ*i + j] <= conv_r[KRNL_SZ*i + (j+1)];
						end
					end

				end

				else if (j == KRNL_SZ-1) begin

					always@ (posedge clk) begin
						if (is_in_val) begin
							conv_r[KRNL_SZ*i + j] <= row_buf_sr_out;
						end
					end

				end
				else begin

					always@ (posedge clk) begin
						if (is_in_val) begin
							conv_r[KRNL_SZ*i + j] <= conv_r[KRNL_SZ*i + (j+1)];
						end
					end

				end
			end
	        
	    end
	endgenerate




	wire	signed	[15:0] mult [(KRNL_SZ*KRNL_SZ)-1 : 0];
	reg		signed	[15:0] mult_reg [(KRNL_SZ*KRNL_SZ)-1 : 0];
	genvar k, l;
	generate

		for (k = 0; k < KRNL_SZ; k = k + 1) begin: MULT_OUTER
			for (l = 0; l < KRNL_SZ; l = l + 1) begin: MULT_INNER
				
				convolve_mult my_mult(
					.out(mult[KRNL_SZ*k + l]),
					.a(conv_r[KRNL_SZ*k + l]),
					.b(kernel[((KRNL_SZ*KRNL_SZ - KRNL_SZ*k - l)*8 - 1) : (KRNL_SZ*KRNL_SZ - KRNL_SZ*k - l - 1)*8])
				);

				always @(posedge clk) begin
					mult_reg[KRNL_SZ*k + l] <= mult[KRNL_SZ*k + l];
				end
			end
		end

	endgenerate

	integer sum_i;



	always @(posedge clk) begin
		if (reset) begin
			out_x <= 0;
			out_y <= 0;
			is_out_val <= 0;
		end
		else begin
			out_x <= out_x_stg0;
			out_y <= out_y_stg0;
			is_out_val <= is_out_val_stg0;
		end
	end


	reg		signed	[15:0]	conv_sum;
	always@ (*) begin
	 	conv_sum = 16'b0;
		for(sum_i = 0; sum_i < (KRNL_SZ*KRNL_SZ); sum_i = sum_i + 1) begin
			conv_sum = conv_sum + mult_reg[sum_i];
		end
	end

	assign out_val = conv_sum[15] ? 8'd0 : conv_sum[11:4];

endmodule