data/full_repos/permissive/199399537/sdram_cmd.v
'utf-8' codec can't decode byte 0xcc in position 1340: invalid continuation byte
1: b'%Error: data/full_repos/permissive/199399537/sdram_cmd.v:35: Cannot find include file: sdr_para.v\n`include "sdr_para.v"  //             SDRAM                                 \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/sdr_para.v\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/sdr_para.v.v\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/sdr_para.v.sv\n             sdr_para.v\n             sdr_para.v.v\n             sdr_para.v.sv\n             obj_dir/sdr_para.v\n             obj_dir/sdr_para.v.v\n             obj_dir/sdr_para.v.sv\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:61: Define or directive not defined: \'`I_NOP\'\n    `I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:61: syntax error, unexpected \',\', expecting endcase\n    `I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: \n          ^\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:61: Define or directive not defined: \'`I_TRP\'\n    `I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: \n           ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:61: Define or directive not defined: \'`I_TRF1\'\n    `I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: \n                  ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:61: Define or directive not defined: \'`I_TRF2\'\n    `I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: \n                          ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:61: Define or directive not defined: \'`I_TRF3\'\n    `I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: \n                                  ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:61: Define or directive not defined: \'`I_TRF4\'\n    `I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: \n                                          ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:61: Define or directive not defined: \'`I_TRF5\'\n    `I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: \n                                                  ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:61: Define or directive not defined: \'`I_TRF6\'\n    `I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: \n                                                          ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:61: Define or directive not defined: \'`I_TRF7\'\n    `I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: \n                                                                  ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:61: Define or directive not defined: \'`I_TRF8\'\n    `I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: \n                                                                          ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:61: Define or directive not defined: \'`I_TMRD\'\n    `I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: \n                                                                                  ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:63: Define or directive not defined: \'`CMD_NOP\'\n      sdram_cmd_r <= `CMD_NOP; \n                     ^~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:68: Define or directive not defined: \'`I_PRE\'\n    `I_PRE:  \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:69: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:70: Define or directive not defined: \'`CMD_PRGE\'\n      sdram_cmd_r <= `CMD_PRGE; \n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:75: Define or directive not defined: \'`I_AR1\'\n    `I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:  \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:75: syntax error, unexpected \',\'\n    `I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:  \n          ^\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:75: Define or directive not defined: \'`I_AR2\'\n    `I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:  \n           ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:75: Define or directive not defined: \'`I_AR3\'\n    `I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:  \n                  ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:75: Define or directive not defined: \'`I_AR4\'\n    `I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:  \n                         ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:75: Define or directive not defined: \'`I_AR5\'\n    `I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:  \n                                ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:75: Define or directive not defined: \'`I_AR6\'\n    `I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:  \n                                       ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:75: Define or directive not defined: \'`I_AR7\'\n    `I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:  \n                                              ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:75: Define or directive not defined: \'`I_AR8\'\n    `I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:  \n                                                     ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:77: Define or directive not defined: \'`CMD_A_REF\'\n      sdram_cmd_r <= `CMD_A_REF; \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:82: Define or directive not defined: \'`I_MRS\'\n    `I_MRS:  \n    ^~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:84: Define or directive not defined: \'`CMD_LMR\'\n       sdram_cmd_r <= `CMD_LMR; \n                      ^~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:97: Define or directive not defined: \'`I_DONE\'\n    `I_DONE:\n    ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:101: Define or directive not defined: \'`W_IDLE\'\n        `W_IDLE,`W_TRCD,`W_CL,`W_TRFC,`W_RD,`W_WD,`W_TDAL: \n        ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:101: Define or directive not defined: \'`W_TRCD\'\n        `W_IDLE,`W_TRCD,`W_CL,`W_TRFC,`W_RD,`W_WD,`W_TDAL: \n                ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:101: Define or directive not defined: \'`W_CL\'\n        `W_IDLE,`W_TRCD,`W_CL,`W_TRFC,`W_RD,`W_WD,`W_TDAL: \n                        ^~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:101: Define or directive not defined: \'`W_TRFC\'\n        `W_IDLE,`W_TRCD,`W_CL,`W_TRFC,`W_RD,`W_WD,`W_TDAL: \n                              ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:101: Define or directive not defined: \'`W_RD\'\n        `W_IDLE,`W_TRCD,`W_CL,`W_TRFC,`W_RD,`W_WD,`W_TDAL: \n                                      ^~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:101: Define or directive not defined: \'`W_WD\'\n        `W_IDLE,`W_TRCD,`W_CL,`W_TRFC,`W_RD,`W_WD,`W_TDAL: \n                                            ^~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:101: Define or directive not defined: \'`W_TDAL\'\n        `W_IDLE,`W_TRCD,`W_CL,`W_TRFC,`W_RD,`W_WD,`W_TDAL: \n                                                  ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:103: Define or directive not defined: \'`CMD_NOP\'\n            sdram_cmd_r <= `CMD_NOP;\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:109: Define or directive not defined: \'`W_ACTIVE\'\n         `W_ACTIVE: \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:111: Define or directive not defined: \'`CMD_ACTIVE\'\n            sdram_cmd_r  <= `CMD_ACTIVE;   \n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:117: Define or directive not defined: \'`W_READ\'\n         `W_READ: \n         ^~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:119: Define or directive not defined: \'`CMD_READ\'\n            sdram_cmd_r <= `CMD_READ;   \n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:127: Define or directive not defined: \'`W_WRITE\'\n         `W_WRITE: \n         ^~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:129: Define or directive not defined: \'`CMD_WRITE\'\n             sdram_cmd_r <= `CMD_WRITE; \n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:137: Define or directive not defined: \'`W_AR\'\n         `W_AR: \n         ^~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:139: Define or directive not defined: \'`CMD_A_REF\'\n             sdram_cmd_r <= `CMD_A_REF; \n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:145: Define or directive not defined: \'`CMD_NOP\'\n         sdram_cmd_r <= `CMD_NOP;\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_cmd.v:153: Define or directive not defined: \'`CMD_NOP\'\n       sdram_cmd_r <= `CMD_NOP;\n                      ^~~~~~~~\n%Error: Cannot continue\n'
module sdram_cmd(
				clk,rst_n,
				sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n,sdram_ba,sdram_addr,
				sys_addr,
				init_state,work_state
			);

			
input clk;
input rst_n;


output 			sdram_cke;
output 			sdram_cs_n;
output 			sdram_ras_n;
output 			sdram_cas_n;
output 			sdram_we_n;
output[1:0] 	sdram_ba;
output[12:0] sdram_addr;


input[21:0] sys_addr;


input[4:0] init_state;
input[3:0] work_state;


`include "sdr_para.v"



reg[4:0] 	sdram_cmd_r;
reg[1:0] 	sdram_ba_r;
reg[11:0] 	sdram_addr_r;



assign {sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n} = sdram_cmd_r;
assign sdram_ba = sdram_ba_r;
assign sdram_addr = {1'b0,sdram_addr_r};



always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) 
			begin
				sdram_cmd_r <= 5'b01111;
				sdram_ba_r <= 2'b11;
				sdram_addr_r <= 12'hfff;
			end
			
	else
		case (init_state)
				`I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: 
					begin
						sdram_cmd_r <= `CMD_NOP;
						sdram_ba_r <= 2'b11;
						sdram_addr_r <= 12'hfff;	
					end
					
				`I_PRE:
					begin
						sdram_cmd_r <= `CMD_PRGE;
						sdram_ba_r <= 2'b11;
						sdram_addr_r <= 12'hfff;
					end 
					
				`I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:
					begin
						sdram_cmd_r <= `CMD_A_REF;
						sdram_ba_r <= 2'b11;
						sdram_addr_r <= 12'hfff;						
					end 	
					
				`I_MRS:
						begin
							sdram_cmd_r <= `CMD_LMR;
							sdram_ba_r <= 2'b00;
							sdram_addr_r <= {
										 2'b00,
										 1'b0,
										 2'b00,
										 
										 3'b010,
										 1'b0,
										 3'b011
									};
						end	
						
				`I_DONE:
					case (work_state)
					

								`W_IDLE,`W_TRCD,`W_CL,`W_TRFC,`W_RD,`W_WD,`W_TDAL: 
										begin
												sdram_cmd_r <= `CMD_NOP;
												sdram_ba_r <= 2'b11;
												sdram_addr_r <= 12'hfff;
										end
										

									`W_ACTIVE: 
											begin
												sdram_cmd_r 	<= `CMD_ACTIVE;
												sdram_ba_r 		<= sys_addr[21:20];
												sdram_addr_r 	<= sys_addr[19:8];
											end
								
									
									`W_READ: 
											begin
												sdram_cmd_r <= `CMD_READ;
												sdram_ba_r <= sys_addr[21:20];
												sdram_addr_r <= {
																4'b0100,
																sys_addr[7:0]
															};
											end
										
									`W_WRITE: 
											begin
													sdram_cmd_r <= `CMD_WRITE;
													sdram_ba_r <= sys_addr[21:20];
													sdram_addr_r <= {
																	4'b0100,
																	sys_addr[7:0]
																};
											end				
											
									`W_AR: 
											begin
													sdram_cmd_r <= `CMD_A_REF;
													sdram_ba_r <= 2'b11;
													sdram_addr_r <= 12'hfff;	
											end
											
							default: begin
									sdram_cmd_r <= `CMD_NOP;
									sdram_ba_r <= 2'b11;
									sdram_addr_r <= 12'hfff;	
								end
						endcase
						
						
				default: begin
							sdram_cmd_r <= `CMD_NOP;
							sdram_ba_r <= 2'b11;
							sdram_addr_r <= 12'hfff;	
						end
			endcase
end

endmodule
module sdram_cmd(
				clk,rst_n,
				sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n,sdram_ba,sdram_addr,
				sys_addr,
				init_state,work_state
			);


			
input clk;
input rst_n;


output 			sdram_cke;
output 			sdram_cs_n;
output 			sdram_ras_n;
output 			sdram_cas_n;
output 			sdram_we_n;
output[1:0] 	sdram_ba;
output[12:0] sdram_addr;


input[21:0] sys_addr;


input[4:0] init_state;
input[3:0] work_state;


`include "sdr_para.v"



reg[4:0] 	sdram_cmd_r;
reg[1:0] 	sdram_ba_r;
reg[11:0] 	sdram_addr_r;



assign {sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n} = sdram_cmd_r;
assign sdram_ba = sdram_ba_r;
assign sdram_addr = {1'b0,sdram_addr_r};



always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) 
			begin
				sdram_cmd_r <= 5'b01111;
				sdram_ba_r <= 2'b11;
				sdram_addr_r <= 12'hfff;
			end
			
	else
		case (init_state)
				`I_NOP,`I_TRP,`I_TRF1,`I_TRF2,`I_TRF3,`I_TRF4,`I_TRF5,`I_TRF6,`I_TRF7,`I_TRF8,`I_TMRD: 
					begin
						sdram_cmd_r <= `CMD_NOP;
						sdram_ba_r <= 2'b11;
						sdram_addr_r <= 12'hfff;	
					end
					
				`I_PRE:
					begin
						sdram_cmd_r <= `CMD_PRGE;
						sdram_ba_r <= 2'b11;
						sdram_addr_r <= 12'hfff;
					end 
					
				`I_AR1,`I_AR2,`I_AR3,`I_AR4,`I_AR5,`I_AR6,`I_AR7,`I_AR8:
					begin
						sdram_cmd_r <= `CMD_A_REF;
						sdram_ba_r <= 2'b11;
						sdram_addr_r <= 12'hfff;						
					end 	
					
				`I_MRS:
						begin
							sdram_cmd_r <= `CMD_LMR;
							sdram_ba_r <= 2'b00;
							sdram_addr_r <= {
										 2'b00,
										 1'b0,
										 2'b00,
										 
										 3'b010,
										 1'b0,
										 3'b011
									};
						end	
						
				`I_DONE:
					case (work_state)
					

								`W_IDLE,`W_TRCD,`W_CL,`W_TRFC,`W_RD,`W_WD,`W_TDAL: 
										begin
												sdram_cmd_r <= `CMD_NOP;
												sdram_ba_r <= 2'b11;
												sdram_addr_r <= 12'hfff;
										end
										

									`W_ACTIVE: 
											begin
												sdram_cmd_r 	<= `CMD_ACTIVE;
												sdram_ba_r 		<= sys_addr[21:20];
												sdram_addr_r 	<= sys_addr[19:8];
											end
								
									
									`W_READ: 
											begin
												sdram_cmd_r <= `CMD_READ;
												sdram_ba_r <= sys_addr[21:20];
												sdram_addr_r <= {
																4'b0100,
																sys_addr[7:0]
															};
											end
										
									`W_WRITE: 
											begin
													sdram_cmd_r <= `CMD_WRITE;
													sdram_ba_r <= sys_addr[21:20];
													sdram_addr_r <= {
																	4'b0100,
																	sys_addr[7:0]
																};
											end				
											
									`W_AR: 
											begin
													sdram_cmd_r <= `CMD_A_REF;
													sdram_ba_r <= 2'b11;
													sdram_addr_r <= 12'hfff;	
											end
											
							default: begin
									sdram_cmd_r <= `CMD_NOP;
									sdram_ba_r <= 2'b11;
									sdram_addr_r <= 12'hfff;	
								end
						endcase
						
						
				default: begin
							sdram_cmd_r <= `CMD_NOP;
							sdram_ba_r <= 2'b11;
							sdram_addr_r <= 12'hfff;	
						end
			endcase
end

endmodule