data/full_repos/permissive/114811571/test/samples/register_assign/register_assign.v
 line:15: before: "Sel"
data/verilator_xmls/76b657a0-a74c-4e65-a1f0-69a519f5d850.xml
module register_assign(input clk, input [1:0] a, output [1:0] yout);

   reg [1:0] y;
   

   always @(posedge clk) begin
     y <= a;
   end

   wire [1:0] y_tmp;
   
   assign yout = y;

endmodule
module register_assign(input clk, input [1:0] a, output [1:0] yout);


   reg [1:0] y;
   

   always @(posedge clk) begin
     y <= a;
   end

   wire [1:0] y_tmp;
   
   assign yout = y;

endmodule