data/full_repos/permissive/129797190/rtl/cpu/csrs.v
1: b'%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:193: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 65 bits.\n                                                                       : ... In instance csrs\n          12\'h300:        read_value_out = {40\'b0, 2\'b0, 7\'b0, mstatus_mpie, 7\'b0, mstatus_mie, 7\'b0};\n                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:196: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 63 bits.\n                                                                       : ... In instance csrs\n            12\'h305:          read_value_out = {mtvec_base, 2\'b0, mtvec_mode};\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:228: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 63 bits.\n                                                                       : ... In instance csrs\n            12\'h342:         read_value_out = {mcause_interrupt, 55\'b0, mcause_code};\n                                            ^\n%Warning-SELRANGE: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:284: Selection index out of range: 64:63 outside 63:0\n                                                                          : ... In instance csrs\n            12\'hBc1:        read_value_out = cycle[64:63];\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:284: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                       : ... In instance csrs\n            12\'hBc1:        read_value_out = cycle[64:63];\n                                           ^\n%Warning-SELRANGE: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:285: Selection index out of range: 64:63 outside 63:0\n                                                                          : ... In instance csrs\n            12\'hBc2:      read_value_out = instret[64:63];\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:285: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                       : ... In instance csrs\n            12\'hBc2:      read_value_out = instret[64:63];\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:320: Selection index out of range: 64:63 outside 63:0\n                                                                          : ... In instance csrs\n            12\'hC80:         read_value_out = cycle[64:63];\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:320: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                       : ... In instance csrs\n            12\'hC80:         read_value_out = cycle[64:63];\n                                            ^\n%Warning-SELRANGE: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:321: Selection index out of range: 64:63 outside 63:0\n                                                                          : ... In instance csrs\n            12\'hC81:          read_value_out = cycle[64:63];\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:321: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                       : ... In instance csrs\n            12\'hC81:          read_value_out = cycle[64:63];\n                                             ^\n%Warning-SELRANGE: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:322: Selection index out of range: 64:63 outside 63:0\n                                                                          : ... In instance csrs\n            12\'hC82:       read_value_out = instret[64:63];\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:322: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                       : ... In instance csrs\n            12\'hC82:       read_value_out = instret[64:63];\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h300\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h301\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h304\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h305\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h643\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h644\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h645\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h646\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h647\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h649\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h64a\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h64b\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h64c\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h64d\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h64e\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h64f\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h330\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h331\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h364\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h333\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h334\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h335\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h336\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h337\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h338\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h339\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h33a\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h33b\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h33c\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h33d\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h33e\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h33f\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h340\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h341\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h342\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h343\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h344\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3a0\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3a1\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3a2\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3a3\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3b0\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3b1\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3b2\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3b3\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3b4\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3b5\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3b6\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3b7\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3b8\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3b9\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3ba\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3bb\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3bc\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3bd\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3be\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h3bf\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hbf1\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hbf2\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb01\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb02\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb03\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb04\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb05\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb06\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb07\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb08\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb09\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb0a\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb0b\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb0c\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb0d\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb0e\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb0f\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb10\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb11\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb12\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb13\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb14\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb15\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb16\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb17\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb18\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb19\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb1a\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb1b\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb1c\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb1d\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb1e\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb1f\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hbc1\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hbc2\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb81\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb82\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb83\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb84\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb85\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb86\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb87\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb88\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb89\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb8a\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb8b\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb8c\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb8d\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb8e\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb8f\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb90\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb91\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb92\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb93\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb94\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb95\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb96\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb97\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb98\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb99\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb9a\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb9b\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb9c\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb9d\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb9e\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hb9f\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hc00\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hc01\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hc02\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hc80\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hc81\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hc82\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hf11\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hf12\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hf13\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:192: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'hf14\' generates 12 bits.\n                                                                       : ... In instance csrs\n        case (csr_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:329: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h0\' generates 2 bits.\n                                                                       : ... In instance csrs\n        case (write_op_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:329: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h1\' generates 2 bits.\n                                                                       : ... In instance csrs\n        case (write_op_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:329: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n                                                                       : ... In instance csrs\n        case (write_op_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:344: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                       : ... In instance csrs\n                12\'h342:   {mcause_interrupt, mcause_code} <= {new_value[63], new_value[7:0]};\n                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:338: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h300\' generates 12 bits.\n                                                                       : ... In instance csrs\n            case (csr_in)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:338: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h304\' generates 12 bits.\n                                                                       : ... In instance csrs\n            case (csr_in)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:338: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h305\' generates 12 bits.\n                                                                       : ... In instance csrs\n            case (csr_in)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:338: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h340\' generates 12 bits.\n                                                                       : ... In instance csrs\n            case (csr_in)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:338: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h341\' generates 12 bits.\n                                                                       : ... In instance csrs\n            case (csr_in)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:338: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h342\' generates 12 bits.\n                                                                       : ... In instance csrs\n            case (csr_in)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:338: Operator CASE expects 24 bits on the Case Item, but Case Item\'s CONST \'12\'h343\' generates 12 bits.\n                                                                       : ... In instance csrs\n            case (csr_in)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/csrs.v:350: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'instr_retired_in\' generates 1 bits.\n                                                                       : ... In instance csrs\n        instret <= instret + instr_retired_in;\n                           ^\n%Error: Exiting due to 158 warning(s)\n'
module csrs (
    input clk,
    input stall_in,

    input read_in,
    input write_in,
    input [2:0] write_op_in,
    input src_in,

    input instr_retired_in,

    input [23:0] csr_in,
    input [63:0] rs1_value_in,
    input [63:0] imm_value_in,

    output reg [63:0] read_value_out,
    output wire [63:0] cycle_out
);
    wire [63:0] write_value;
    reg [63:0] new_value;

    reg mstatus_mpie;
    reg mstatus_mie;
    reg mie_meie;
    reg mie_mtie;
    reg mie_msie;
    reg [63:4] mtvec_base;
    reg mtvec_mode;
    reg [63:0] mscratch;
    reg [63:4] mepc;
    reg mcause_interrupt;
    reg [6:0] mcause_code;
    reg [63:0] mtval;
    reg mip_meip;
    reg mip_mtip;
    reg mip_msip;
    reg [63:0] cycle;
    reg [63:0] instret;

    assign write_value = src_in ? rs1_value_in : imm_value_in;
    assign cycle_out = cycle;

    always @* begin
        case (csr_in)
          `CSR_MSTATUS:        read_value_out = {40'b0, 2'b0, 7'b0, mstatus_mpie, 7'b0, mstatus_mie, 7'b0};
            `CSR_MISA:           read_value_out = `MISA_VALUE;
            `CSR_MIE:            read_value_out = {40'b0, mie_meie, 7'b0, mie_mtie, 7'b0, mie_msie, 7'b0};
            `CSR_MTVEC:          read_value_out = {mtvec_base, 2'b0, mtvec_mode};
            `CSR_MHPMEVENT3:     read_value_out = 64'b0;
            `CSR_MHPMEVENT4:     read_value_out = 64'b0;
            `CSR_MHPMEVENT5:     read_value_out = 64'b0;
            `CSR_MHPMEVENT6:     read_value_out = 64'b0;
            `CSR_MHPMEVENT7:     read_value_out = 64'b0;
            `CSR_MHPMEVENT7:     read_value_out = 64'b0;
            `CSR_MHPMEVENT9:     read_value_out = 64'b0;
            `CSR_MHPMEVENT10:    read_value_out = 64'b0;
            `CSR_MHPMEVENT11:    read_value_out = 64'b0;
            `CSR_MHPMEVENT12:    read_value_out = 64'b0;
            `CSR_MHPMEVENT13:    read_value_out = 64'b0;
            `CSR_MHPMEVENT14:    read_value_out = 64'b0;
            `CSR_MHPMEVENT15:    read_value_out = 64'b0;
            `CSR_MHPMEVENT16:    read_value_out = 64'b0;
            `CSR_MHPMEVENT17:    read_value_out = 64'b0;
            `CSR_MHPMEVENT18:    read_value_out = 64'b0;
            `CSR_MHPMEVENT19:    read_value_out = 64'b0;
            `CSR_MHPMEVENT20:    read_value_out = 64'b0;
            `CSR_MHPMEVENT21:    read_value_out = 64'b0;
            `CSR_MHPMEVENT22:    read_value_out = 64'b0;
            `CSR_MHPMEVENT23:    read_value_out = 64'b0;
            `CSR_MHPMEVENT24:    read_value_out = 64'b0;
            `CSR_MHPMEVENT25:    read_value_out = 64'b0;
            `CSR_MHPMEVENT26:    read_value_out = 64'b0;
            `CSR_MHPMEVENT27:    read_value_out = 64'b0;
            `CSR_MHPMEVENT28:    read_value_out = 64'b0;
            `CSR_MHPMEVENT29:    read_value_out = 64'b0;
            `CSR_MHPMEVENT30:    read_value_out = 64'b0;
            `CSR_MHPMEVENT31:    read_value_out = 64'b0;
            `CSR_MSCRATCH:       read_value_out = mscratch;
            `CSR_MEPC:           read_value_out = {mepc, 4'b0};
            `CSR_MCAUSE:         read_value_out = {mcause_interrupt, 55'b0, mcause_code};
            `CSR_MTVAL:          read_value_out = mtval;
            `CSR_MIP:            read_value_out = {40'b0, mip_meip, 7'b0, mip_mtip, 7'b0, mip_msip, 7'b0};
            `CSR_PMPCFG0:        read_value_out = 64'b0;
            `CSR_PMPCFG1:        read_value_out = 64'b0;
            `CSR_PMPCFG2:        read_value_out = 64'b0;
            `CSR_PMPCFG3:        read_value_out = 64'b0;
            `CSR_PMPADDR0:       read_value_out = 64'b0;
            `CSR_PMPADDR1:       read_value_out = 64'b0;
            `CSR_PMPADDR2:       read_value_out = 64'b0;
            `CSR_PMPADDR3:       read_value_out = 64'b0;
            `CSR_PMPADDR4:       read_value_out = 64'b0;
            `CSR_PMPADDR5:       read_value_out = 64'b0;
            `CSR_PMPADDR6:       read_value_out = 64'b0;
            `CSR_PMPADDR7:       read_value_out = 64'b0;
            `CSR_PMPADDR8:       read_value_out = 64'b0;
            `CSR_PMPADDR9:       read_value_out = 64'b0;
            `CSR_PMPADDR10:      read_value_out = 64'b0;
            `CSR_PMPADDR11:      read_value_out = 64'b0;
            `CSR_PMPADDR12:      read_value_out = 64'b0;
            `CSR_PMPADDR13:      read_value_out = 64'b0;
            `CSR_PMPADDR14:      read_value_out = 64'b0;
            `CSR_PMPADDR15:      read_value_out = 64'b0;
            `CSR_MCYCLE:         read_value_out = cycle[63:0];
            `CSR_MINSTRET:       read_value_out = instret[63:0];
            `CSR_MHPMCOUNTER1:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER2:   read_value_out = 64'b0; 
            `CSR_MHPMCOUNTER3:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER4:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER5:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER6:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER7:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER8:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER9:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER10:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER11:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER12:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER13:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER14:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER15:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER16:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER17:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER18:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER19:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER20:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER21:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER22:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER23:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER24:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER25:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER26:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER27:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER28:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER29:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER30:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER31:  read_value_out = 64'b0;
            `CSR_MCYCLEH:        read_value_out = cycle[64:63];
            `CSR_MINSTRETH:      read_value_out = instret[64:63];
            `CSR_MHPMCOUNTER1H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER2H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER3H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER4H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER5H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER6H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER7H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER8H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER9H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER10H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER11H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER12H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER13H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER14H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER15H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER16H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER17H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER18H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER19H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER20H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER21H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER22H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER23H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER24H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER25H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER26H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER27H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER28H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER29H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER30H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER31H: read_value_out = 64'b0;
            `CSR_CYCLE:          read_value_out = cycle[63:0];
            `CSR_TIME:           read_value_out = cycle[63:0];
            `CSR_INSTRET:        read_value_out = instret[63:0];
            `CSR_CYCLEH:         read_value_out = cycle[64:63];
            `CSR_TIMEH:          read_value_out = cycle[64:63];
            `CSR_INSTRETH:       read_value_out = instret[64:63];
            `CSR_MVENDORID:      read_value_out = 64'b0;
            `CSR_MARCHID:        read_value_out = 64'b0;
            `CSR_MIMPID:         read_value_out = 64'b0;
            `CSR_MHARTID:        read_value_out = 64'b0;
        endcase

        case (write_op_in)
            `CSR_WRITE_OP_RW: new_value = write_value;
            `CSR_WRITE_OP_RS: new_value = read_value_out |  write_value;
            `CSR_WRITE_OP_RC: new_value = read_value_out & ~write_value;
        endcase
    end

    always @(posedge clk) begin
        if (!stall_in && write_in) begin
            case (csr_in)
                `CSR_MSTATUS:  {mstatus_mpie, mstatus_mie} <= {new_value[15], new_value[7]};
                `CSR_MIE:      {mie_meie, mie_mtie, mie_msie} <= {new_value[23], new_value[15], new_value[7]};
                `CSR_MTVEC:    {mtvec_base, mtvec_mode} <= {new_value[63:4], new_value[0]};
                `CSR_MSCRATCH: mscratch <= new_value;
                `CSR_MEPC:     mepc <= new_value[63:4];
                `CSR_MCAUSE:   {mcause_interrupt, mcause_code} <= {new_value[63], new_value[7:0]};
                `CSR_MTVAL:    mtval <= new_value;
            endcase
        end

        cycle <= cycle + 1;
        instret <= instret + instr_retired_in;
    end
endmodule
module csrs (
    input clk,
    input stall_in,

    input read_in,
    input write_in,
    input [2:0] write_op_in,
    input src_in,

    input instr_retired_in,

    input [23:0] csr_in,
    input [63:0] rs1_value_in,
    input [63:0] imm_value_in,

    output reg [63:0] read_value_out,
    output wire [63:0] cycle_out
);

    wire [63:0] write_value;
    reg [63:0] new_value;

    reg mstatus_mpie;
    reg mstatus_mie;
    reg mie_meie;
    reg mie_mtie;
    reg mie_msie;
    reg [63:4] mtvec_base;
    reg mtvec_mode;
    reg [63:0] mscratch;
    reg [63:4] mepc;
    reg mcause_interrupt;
    reg [6:0] mcause_code;
    reg [63:0] mtval;
    reg mip_meip;
    reg mip_mtip;
    reg mip_msip;
    reg [63:0] cycle;
    reg [63:0] instret;

    assign write_value = src_in ? rs1_value_in : imm_value_in;
    assign cycle_out = cycle;

    always @* begin
        case (csr_in)
          `CSR_MSTATUS:        read_value_out = {40'b0, 2'b0, 7'b0, mstatus_mpie, 7'b0, mstatus_mie, 7'b0};
            `CSR_MISA:           read_value_out = `MISA_VALUE;
            `CSR_MIE:            read_value_out = {40'b0, mie_meie, 7'b0, mie_mtie, 7'b0, mie_msie, 7'b0};
            `CSR_MTVEC:          read_value_out = {mtvec_base, 2'b0, mtvec_mode};
            `CSR_MHPMEVENT3:     read_value_out = 64'b0;
            `CSR_MHPMEVENT4:     read_value_out = 64'b0;
            `CSR_MHPMEVENT5:     read_value_out = 64'b0;
            `CSR_MHPMEVENT6:     read_value_out = 64'b0;
            `CSR_MHPMEVENT7:     read_value_out = 64'b0;
            `CSR_MHPMEVENT7:     read_value_out = 64'b0;
            `CSR_MHPMEVENT9:     read_value_out = 64'b0;
            `CSR_MHPMEVENT10:    read_value_out = 64'b0;
            `CSR_MHPMEVENT11:    read_value_out = 64'b0;
            `CSR_MHPMEVENT12:    read_value_out = 64'b0;
            `CSR_MHPMEVENT13:    read_value_out = 64'b0;
            `CSR_MHPMEVENT14:    read_value_out = 64'b0;
            `CSR_MHPMEVENT15:    read_value_out = 64'b0;
            `CSR_MHPMEVENT16:    read_value_out = 64'b0;
            `CSR_MHPMEVENT17:    read_value_out = 64'b0;
            `CSR_MHPMEVENT18:    read_value_out = 64'b0;
            `CSR_MHPMEVENT19:    read_value_out = 64'b0;
            `CSR_MHPMEVENT20:    read_value_out = 64'b0;
            `CSR_MHPMEVENT21:    read_value_out = 64'b0;
            `CSR_MHPMEVENT22:    read_value_out = 64'b0;
            `CSR_MHPMEVENT23:    read_value_out = 64'b0;
            `CSR_MHPMEVENT24:    read_value_out = 64'b0;
            `CSR_MHPMEVENT25:    read_value_out = 64'b0;
            `CSR_MHPMEVENT26:    read_value_out = 64'b0;
            `CSR_MHPMEVENT27:    read_value_out = 64'b0;
            `CSR_MHPMEVENT28:    read_value_out = 64'b0;
            `CSR_MHPMEVENT29:    read_value_out = 64'b0;
            `CSR_MHPMEVENT30:    read_value_out = 64'b0;
            `CSR_MHPMEVENT31:    read_value_out = 64'b0;
            `CSR_MSCRATCH:       read_value_out = mscratch;
            `CSR_MEPC:           read_value_out = {mepc, 4'b0};
            `CSR_MCAUSE:         read_value_out = {mcause_interrupt, 55'b0, mcause_code};
            `CSR_MTVAL:          read_value_out = mtval;
            `CSR_MIP:            read_value_out = {40'b0, mip_meip, 7'b0, mip_mtip, 7'b0, mip_msip, 7'b0};
            `CSR_PMPCFG0:        read_value_out = 64'b0;
            `CSR_PMPCFG1:        read_value_out = 64'b0;
            `CSR_PMPCFG2:        read_value_out = 64'b0;
            `CSR_PMPCFG3:        read_value_out = 64'b0;
            `CSR_PMPADDR0:       read_value_out = 64'b0;
            `CSR_PMPADDR1:       read_value_out = 64'b0;
            `CSR_PMPADDR2:       read_value_out = 64'b0;
            `CSR_PMPADDR3:       read_value_out = 64'b0;
            `CSR_PMPADDR4:       read_value_out = 64'b0;
            `CSR_PMPADDR5:       read_value_out = 64'b0;
            `CSR_PMPADDR6:       read_value_out = 64'b0;
            `CSR_PMPADDR7:       read_value_out = 64'b0;
            `CSR_PMPADDR8:       read_value_out = 64'b0;
            `CSR_PMPADDR9:       read_value_out = 64'b0;
            `CSR_PMPADDR10:      read_value_out = 64'b0;
            `CSR_PMPADDR11:      read_value_out = 64'b0;
            `CSR_PMPADDR12:      read_value_out = 64'b0;
            `CSR_PMPADDR13:      read_value_out = 64'b0;
            `CSR_PMPADDR14:      read_value_out = 64'b0;
            `CSR_PMPADDR15:      read_value_out = 64'b0;
            `CSR_MCYCLE:         read_value_out = cycle[63:0];
            `CSR_MINSTRET:       read_value_out = instret[63:0];
            `CSR_MHPMCOUNTER1:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER2:   read_value_out = 64'b0; 
            `CSR_MHPMCOUNTER3:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER4:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER5:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER6:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER7:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER8:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER9:   read_value_out = 64'b0;
            `CSR_MHPMCOUNTER10:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER11:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER12:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER13:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER14:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER15:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER16:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER17:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER18:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER19:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER20:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER21:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER22:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER23:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER24:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER25:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER26:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER27:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER28:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER29:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER30:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER31:  read_value_out = 64'b0;
            `CSR_MCYCLEH:        read_value_out = cycle[64:63];
            `CSR_MINSTRETH:      read_value_out = instret[64:63];
            `CSR_MHPMCOUNTER1H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER2H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER3H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER4H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER5H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER6H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER7H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER8H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER9H:  read_value_out = 64'b0;
            `CSR_MHPMCOUNTER10H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER11H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER12H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER13H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER14H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER15H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER16H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER17H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER18H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER19H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER20H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER21H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER22H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER23H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER24H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER25H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER26H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER27H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER28H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER29H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER30H: read_value_out = 64'b0;
            `CSR_MHPMCOUNTER31H: read_value_out = 64'b0;
            `CSR_CYCLE:          read_value_out = cycle[63:0];
            `CSR_TIME:           read_value_out = cycle[63:0];
            `CSR_INSTRET:        read_value_out = instret[63:0];
            `CSR_CYCLEH:         read_value_out = cycle[64:63];
            `CSR_TIMEH:          read_value_out = cycle[64:63];
            `CSR_INSTRETH:       read_value_out = instret[64:63];
            `CSR_MVENDORID:      read_value_out = 64'b0;
            `CSR_MARCHID:        read_value_out = 64'b0;
            `CSR_MIMPID:         read_value_out = 64'b0;
            `CSR_MHARTID:        read_value_out = 64'b0;
        endcase

        case (write_op_in)
            `CSR_WRITE_OP_RW: new_value = write_value;
            `CSR_WRITE_OP_RS: new_value = read_value_out |  write_value;
            `CSR_WRITE_OP_RC: new_value = read_value_out & ~write_value;
        endcase
    end

    always @(posedge clk) begin
        if (!stall_in && write_in) begin
            case (csr_in)
                `CSR_MSTATUS:  {mstatus_mpie, mstatus_mie} <= {new_value[15], new_value[7]};
                `CSR_MIE:      {mie_meie, mie_mtie, mie_msie} <= {new_value[23], new_value[15], new_value[7]};
                `CSR_MTVEC:    {mtvec_base, mtvec_mode} <= {new_value[63:4], new_value[0]};
                `CSR_MSCRATCH: mscratch <= new_value;
                `CSR_MEPC:     mepc <= new_value[63:4];
                `CSR_MCAUSE:   {mcause_interrupt, mcause_code} <= {new_value[63], new_value[7:0]};
                `CSR_MTVAL:    mtval <= new_value;
            endcase
        end

        cycle <= cycle + 1;
        instret <= instret + instr_retired_in;
    end
endmodule