data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/VGA_Sync_Pulses.v
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data/verilator_xmls/1f168535-ce9d-49fb-bea2-0f944ac41121.xml
module VGA_Sync_Pulses 
  #(parameter TOTAL_COLS  = 80,
   parameter TOTAL_ROWS  = 52,
   parameter ACTIVE_COLS = 64,
   parameter ACTIVE_ROWS = 48)
  (input            i_Clk, 
   output           o_HSync,
   output           o_VSync,
   output reg [10:0] o_Col_Count = 0, 
   output reg [10:0] o_Row_Count = 0
  );  
  
  always @(posedge i_Clk)
  begin
    if (o_Col_Count == TOTAL_COLS-1)
    begin
      o_Col_Count <= 0;
      if (o_Row_Count == TOTAL_ROWS-1)
        o_Row_Count <= 0;
      else
        o_Row_Count <= o_Row_Count + 1;
    end
    else
      o_Col_Count <= o_Col_Count + 1;
      
  end
	  
  assign o_HSync = o_Col_Count < ACTIVE_COLS ? 1'b1 : 1'b0;
  assign o_VSync = o_Row_Count < ACTIVE_ROWS ? 1'b1 : 1'b0;
  
endmodule
module VGA_Sync_Pulses 
  #(parameter TOTAL_COLS  = 80,
   parameter TOTAL_ROWS  = 52,
   parameter ACTIVE_COLS = 64,
   parameter ACTIVE_ROWS = 48)
  (input            i_Clk, 
   output           o_HSync,
   output           o_VSync,
   output reg [10:0] o_Col_Count = 0, 
   output reg [10:0] o_Row_Count = 0
  );
  
  
  always @(posedge i_Clk)
  begin
    if (o_Col_Count == TOTAL_COLS-1)
    begin
      o_Col_Count <= 0;
      if (o_Row_Count == TOTAL_ROWS-1)
        o_Row_Count <= 0;
      else
        o_Row_Count <= o_Row_Count + 1;
    end
    else
      o_Col_Count <= o_Col_Count + 1;
      
  end
	  
  assign o_HSync = o_Col_Count < ACTIVE_COLS ? 1'b1 : 1'b0;
  assign o_VSync = o_Row_Count < ACTIVE_ROWS ? 1'b1 : 1'b0;
  
endmodule