data/full_repos/permissive/20951436/Code/fpga code/advanced code/Advanced code.v
1: b'%Error: Cannot find file containing module: code/advanced\n        ... Looked in:\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.v\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.sv\n             code/advanced\n             code/advanced.v\n             code/advanced.sv\n             obj_dir/code/advanced\n             obj_dir/code/advanced.v\n             obj_dir/code/advanced.sv\n%Error: Cannot find file containing module: code,data/full_repos/permissive/20951436\n%Error: Cannot find file containing module: data/full_repos/permissive/20951436/Code/fpga\n%Error: Cannot find file containing module: code/Advanced\n%Error: Cannot find file containing module: code.v\n%Error: Exiting due to 5 error(s)\n'
module squareroot(input clk, input [63:0] oprnd, output [31:0] rootoprnd, input en, output reg comp_sig);

	reg [31:0] present_guess; initial present_guess<=0;
	assign rootoprnd = present_guess; 
	reg count;
	reg [63:0] oprnd_reg;


	wire [31:0] next_guess; wire [63:0] correction;
	assign next_guess = (present_guess + correction[31:0])>>1 ;

	wire [31:0] remainder; wire div_comp; reg en_div; initial en_div<=0;
	division corr_compute(clk,0,oprnd_reg,present_guess,en_div,correction,remainder,div_comp); 
	
	reg en_hist; 
	reg div_start; initial div_start<=0;
	always @(negedge clk) begin
		en_hist<=en;
		if (en && (~en_hist)) begin


			comp_sig<=0;
			count<=0;
			en_div<=1;
			oprnd_reg<=oprnd;
			div_start<=0;
		end else begin
			case (count)
				0: begin
					div_start<=1;
					if (div_comp && div_start) begin
						count<=count+1;
						comp_sig<= (next_guess[31:1]==present_guess[31:1]);
						en_div<=0;
					end
				end
				1: begin

					div_start<=0;
					present_guess<=next_guess;
					if (!comp_sig) begin 
						en_div<=1;
						count<=count+1;
					end
				end
			endcase
		end
	end

endmodule
module squareroot(input clk, input [63:0] oprnd, output [31:0] rootoprnd, input en, output reg comp_sig);


	reg [31:0] present_guess; initial present_guess<=0;
	assign rootoprnd = present_guess; 
	reg count;
	reg [63:0] oprnd_reg;


	wire [31:0] next_guess; wire [63:0] correction;
	assign next_guess = (present_guess + correction[31:0])>>1 ;

	wire [31:0] remainder; wire div_comp; reg en_div; initial en_div<=0;
	division corr_compute(clk,0,oprnd_reg,present_guess,en_div,correction,remainder,div_comp); 
	
	reg en_hist; 
	reg div_start; initial div_start<=0;
	always @(negedge clk) begin
		en_hist<=en;
		if (en && (~en_hist)) begin


			comp_sig<=0;
			count<=0;
			en_div<=1;
			oprnd_reg<=oprnd;
			div_start<=0;
		end else begin
			case (count)
				0: begin
					div_start<=1;
					if (div_comp && div_start) begin
						count<=count+1;
						comp_sig<= (next_guess[31:1]==present_guess[31:1]);
						en_div<=0;
					end
				end
				1: begin

					div_start<=0;
					present_guess<=next_guess;
					if (!comp_sig) begin 
						en_div<=1;
						count<=count+1;
					end
				end
			endcase
		end
	end

endmodule