data/full_repos/permissive/175261487/src/acia_rx.v
None: at end of input
data/verilator_xmls/60104083-9322-4970-b746-0ba2ec5210c3.xml
module acia_rx(
	input clk,
	input rst,
	input rx_serial,
	output reg [7:0] rx_dat,
	output reg rx_stb,
	output reg rx_err
);

    parameter SCW = 8;
	parameter sym_cnt = 139;
	

	reg [7:0] in_pipe;
	reg in_state;
	wire all_zero = ~|in_pipe;
	wire all_one = &in_pipe;
	always @(posedge clk)
		if(rst)
		begin

			in_pipe <= 8'hff;
			in_state <= 1'b1;
		end
		else
		begin

			in_pipe <= {in_pipe[6:0],rx_serial};
	

			if(in_state && all_zero)
				in_state <= 1'b0;
			else if(!in_state && all_one)
				in_state <= 1'b1;
		end


	reg [8:0] rx_sr;
	reg [3:0] rx_bcnt;
	reg [SCW-1:0] rx_rcnt;
	reg rx_busy;
	always @(posedge clk)
		if(rst)
		begin
			rx_busy <= 1'b0;
			rx_stb <= 1'b0;
			rx_err <= 1'b0;
		end
		else
		begin
			if(!rx_busy)
			begin
				if(!in_state)
				begin

					rx_bcnt <= 4'h9;
					rx_rcnt <= sym_cnt/2;
					rx_busy <= 1'b1;
				end
				

				rx_stb <= 1'b0;
			end
			else
			begin
				if(~|rx_rcnt)
				begin

					rx_sr <= {in_state,rx_sr[8:1]};
					rx_rcnt <= sym_cnt;
					rx_bcnt <= rx_bcnt - 1;
					
					if(~|rx_bcnt)
					begin

						rx_dat <= rx_sr[8:1];
						rx_busy <= 1'b0;
						if(in_state && ~rx_sr[0])
						begin

							rx_err <= 1'b0;
							rx_stb <= 1'b1;
						end
						else

							rx_err <= 1'b1;
					end
				end
				else
					rx_rcnt <= rx_rcnt - 1;
			end
		end
endmodule
module acia_rx(
	input clk,
	input rst,
	input rx_serial,
	output reg [7:0] rx_dat,
	output reg rx_stb,
	output reg rx_err
);


    parameter SCW = 8;
	parameter sym_cnt = 139;
	

	reg [7:0] in_pipe;
	reg in_state;
	wire all_zero = ~|in_pipe;
	wire all_one = &in_pipe;
	always @(posedge clk)
		if(rst)
		begin

			in_pipe <= 8'hff;
			in_state <= 1'b1;
		end
		else
		begin

			in_pipe <= {in_pipe[6:0],rx_serial};
	

			if(in_state && all_zero)
				in_state <= 1'b0;
			else if(!in_state && all_one)
				in_state <= 1'b1;
		end


	reg [8:0] rx_sr;
	reg [3:0] rx_bcnt;
	reg [SCW-1:0] rx_rcnt;
	reg rx_busy;
	always @(posedge clk)
		if(rst)
		begin
			rx_busy <= 1'b0;
			rx_stb <= 1'b0;
			rx_err <= 1'b0;
		end
		else
		begin
			if(!rx_busy)
			begin
				if(!in_state)
				begin

					rx_bcnt <= 4'h9;
					rx_rcnt <= sym_cnt/2;
					rx_busy <= 1'b1;
				end
				

				rx_stb <= 1'b0;
			end
			else
			begin
				if(~|rx_rcnt)
				begin

					rx_sr <= {in_state,rx_sr[8:1]};
					rx_rcnt <= sym_cnt;
					rx_bcnt <= rx_bcnt - 1;
					
					if(~|rx_bcnt)
					begin

						rx_dat <= rx_sr[8:1];
						rx_busy <= 1'b0;
						if(in_state && ~rx_sr[0])
						begin

							rx_err <= 1'b0;
							rx_stb <= 1'b1;
						end
						else

							rx_err <= 1'b1;
					end
				end
				else
					rx_rcnt <= rx_rcnt - 1;
			end
		end
endmodule