data/full_repos/permissive/115771353/rtl/hworb/internet_rx.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/internet_rx.v:45: Operator VAR \'RX_INT_IDLE\' expects 2 bits on the Initial value, but Initial value\'s CONST \'3\'h0\' generates 3 bits.\n                                                                               : ... In instance internet_rx\n RX_INT_IDLE                = 3\'d0, \n ^~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/internet_rx.v:46: Operator VAR \'RX_INT_GETHEADERLEN\' expects 2 bits on the Initial value, but Initial value\'s CONST \'3\'h1\' generates 3 bits.\n                                                                               : ... In instance internet_rx\n RX_INT_GETHEADERLEN       = 3\'d1, \n ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/internet_rx.v:47: Operator VAR \'RX_INT_GETHEADERBYTE\' expects 2 bits on the Initial value, but Initial value\'s CONST \'3\'h2\' generates 3 bits.\n                                                                               : ... In instance internet_rx\n RX_INT_GETHEADERBYTE       = 3\'d2, \n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/internet_rx.v:48: Operator VAR \'RX_INT_COMPLETEFRAGMENT\' expects 2 bits on the Initial value, but Initial value\'s CONST \'3\'h3\' generates 3 bits.\n                                                                               : ... In instance internet_rx\n RX_INT_COMPLETEFRAGMENT    = 3\'d3;\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/internet_rx.v:372: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                : ... In instance internet_rx\n  assign checksumInt = checksumLong[15:0] + checksumLong[16];\n                                          ^\n%Error: Exiting due to 5 warning(s)\n'
module internet_rx #(
  parameter [31:0] DEVICE_IP      = 32'h8d59342b
)
(
  input              clk,
  input              reset_n,
  
  input              newFrame,
  input              frameType,
  input              newFrameByte,
  input [7:0]        frameData,
  output reg         newDatagram,
  output reg  [15:0] datagramSize,
  output wire [7:0]  protocol,
  output wire [31:0] sourceIP
);



  parameter [1:0]
	RX_INT_IDLE    	           = 3'd0,	
	RX_INT_GETHEADERLEN   	   = 3'd1,	
	RX_INT_GETHEADERBYTE   	   = 3'd2,	
	RX_INT_COMPLETEFRAGMENT    = 3'd3;
  
  reg [1:0]  ip_rx_cur_fsm;
  reg [1:0]  ip_rx_nxt_fsm;
  reg [1:0]  returnState;
  reg [5:0]  headerLen;
  reg [5:0]  nextHeaderLen;
  reg [10:0] datagramLen;
  reg [10:0] nextDatagramLen;
  wire [10:0] dataLen;
  reg [10:0] nextDataLen;
  reg        incCnt;
  reg        rstCnt;
  reg [5:0]  cnt;
  reg        latchFrameData;
  reg [7:0]  frameDataLatch;
  reg [31:0] targetIP;
  reg        shiftInTargetIP;
  reg        shiftInSourceIP;
  reg        latchProtocol;

  reg        checkState;
  parameter  stMSB = 1'b0;
  parameter  stLSB = 1'b1;
  reg [16:0] checksumLong;
  wire [15:0] checksumInt;
  reg [7:0]  latchMSB;
  reg        newHeader;
  reg        newByte;
  reg        lastNewByte;
  reg [7:0]  inByte;
  wire [15:0] checksum;

  reg [15:0] identification;
  reg        shiftInIdentification;
  reg [12:0] fragmentOffset;
  reg        shiftInFragmentOffset;
  reg        moreFragments;
  reg        latchMoreFragments;

  parameter  TIMERWIDTH = 7;
  reg [6:0]  timeout0;
  reg        resetTimeout;
  parameter  FULLTIME = 7'b1111111;
  reg [31:0] sourceIPSig;
  reg [7:0]  protocolSig;


  assign sourceIP = sourceIPSig;
  assign protocol = protocolSig;
	


  assign dataLen = datagramLen - {5'b00000,headerLen[5:0]};
	


  always @(posedge clk or negedge reset_n) 
  begin

    if (!reset_n) begin
	  ip_rx_cur_fsm <= RX_INT_IDLE;
	  returnState <= RX_INT_IDLE;
	  timeout0 <= FULLTIME;
	  cnt <= 6'b0;
	  moreFragments <= 1'b0;
	end
	else begin










		ip_rx_cur_fsm <= ip_rx_nxt_fsm;
	  			

	  if (incCnt)
	    cnt <= cnt + 1;
	  else if (rstCnt)
		cnt <= 6'b0;
	  			

      if (latchFrameData)
	    frameDataLatch <= frameData;
	  			

      headerLen <= nextHeaderLen;
      datagramLen <= nextDatagramLen;


      if (shiftInSourceIP)
        sourceIPSig <= {sourceIPSig[23:0], frameData};
      
      if (shiftInTargetIP)
        targetIP <= {targetIP[23:0], frameData};
      
      if (latchProtocol)
        protocolSig <= frameData;
      
      if (shiftInFragmentOffset)
        fragmentOffset <= {fragmentOffset[4:0], frameData};
      
      if (latchMoreFragments)
        moreFragments <= frameData[5];
      
      if (shiftInIdentification)
        identification <= {identification[7:0], frameData};
      			

      if (resetTimeout)
        timeout0 <= 7'b0;
	  else begin

		if (timeout0 != FULLTIME)
		  timeout0 <= timeout0 + 1;
		else
		  timeout0 <= FULLTIME;
		
	  end
			
    end
  end



































  always @(ip_rx_cur_fsm or returnState or cnt or frameData or datagramLen or headerLen or dataLen or newFrame or frameType or checksum or targetIP or timeout0 or	fragmentOffset or moreFragments or newFrameByte)
  begin

    datagramSize <= 16'b0;
	incCnt <= 1'b0;
	rstCnt <= 1'b0;
	newDatagram <= 1'b0;

	nextHeaderLen <= headerLen;
	nextDatagramLen <= datagramLen;
	latchFrameData <= 1'b0;
	shiftInSourceIP <= 1'b0;
	shiftInTargetIP <= 1'b0;
	latchProtocol <= 1'b0;
	newHeader <= 1'b0;
	newByte <= 1'b0;
	inByte <= 8'b0;
	latchMoreFragments <= 1'b0;
	shiftInFragmentOffset <= 1'b0;

	shiftInIdentification <= 1'b0;		
	resetTimeout <= 1'b0;
	
	case(ip_rx_cur_fsm)
	  RX_INT_IDLE:
	  begin
	    resetTimeout <= 1'b1;

		if (!newFrame || !frameType)
		  ip_rx_nxt_fsm <= RX_INT_IDLE;
		else begin

		  rstCnt <= 1'b1;
		  newHeader <= 1'b1;
		  ip_rx_nxt_fsm <= RX_INT_GETHEADERLEN;
		end
	  end	  

      RX_INT_GETHEADERLEN:
	  begin
		if (newFrameByte) begin  

	      if (frameData[7:4] != 4)
		    ip_rx_nxt_fsm <= RX_INT_IDLE;
	      else begin
		    ip_rx_nxt_fsm <= RX_INT_GETHEADERBYTE;

		    inByte <= frameData;
		    newByte <= 1'b1;

		    nextHeaderLen <= {frameData[3:0], 2'b00};
	      end
		  incCnt <= 1'b1;
		end
		else
		  ip_rx_nxt_fsm <= RX_INT_GETHEADERLEN;
	  end	  
			
      RX_INT_GETHEADERBYTE:
	  begin


	    if (cnt == headerLen)  begin

	      if (checksum == 0 && (targetIP == DEVICE_IP || targetIP == 32'hFFFFFFFF))  
		    ip_rx_nxt_fsm <= RX_INT_COMPLETEFRAGMENT;
	      else

		    ip_rx_nxt_fsm <= RX_INT_IDLE;
		end			
		else if (newFrameByte) begin  




				

	      newByte <= 1'b1;
	      inByte <= frameData;
				

	      case(cnt[4:0])				
	        5'd2:
	        begin
  	          nextDatagramLen[10:8] <= frameData[2:0];
	        end	
						
	        5'd3:
	        begin
	          nextDatagramLen[7:0] <= frameData;
	        end	
						
	        5'd4, 5'd5:
	        begin
	          shiftInIdentification <= 1'b1;
	        end	
						
	        5'd6:
	        begin
	          shiftInFragmentOffset <= 1'b1;
	          latchMoreFragments <= 1'b1;
	        end	
						
	        5'd7:
	        begin
	          shiftInFragmentOffset <= 1'b1;
	        end	
						
	        5'd9:
	        begin
	          latchProtocol <= 1'b1;
	        end	
						
	        5'd12, 5'd13, 5'd14, 5'd15:
	        begin
	          shiftInSourceIP <= 1'b1;
	        end	
						
	        5'd16, 5'd17, 5'd18, 5'd19:
	        begin
 	          shiftInTargetIP <= 1'b1;
	        end	
						
	        default:
	        begin
	        end	
		  
	      endcase
		  incCnt <= 1'b1;
		  ip_rx_nxt_fsm <= RX_INT_GETHEADERBYTE;
          resetTimeout <= 1'b1;
		end
	    else if (timeout0 == FULLTIME)
		  ip_rx_nxt_fsm <= RX_INT_IDLE;

	    else begin
		  ip_rx_nxt_fsm <= RX_INT_GETHEADERBYTE;
	    end
				
	  end	  
			
	  RX_INT_COMPLETEFRAGMENT:
	  begin


		ip_rx_nxt_fsm <= RX_INT_IDLE;
		if (!moreFragments) begin

		  newDatagram <= 1'b1;
		  datagramSize <= {5'b00000, dataLen};
	    end
	  end	  
				
      default:
	  begin
 	    ip_rx_nxt_fsm <= RX_INT_IDLE;
	  end	  
	  
	endcase
  end
	

  assign checksumInt = checksumLong[15:0] + checksumLong[16];
  assign checksum = ~checksumInt;


  always @(posedge clk or negedge reset_n) 
  begin

    if (!reset_n) begin
	  checkState <= stMSB;
	  latchMSB <= 8'b0;
	  checksumLong <= 17'b0;
	  lastNewByte <= 1'b0;
	end
	else begin

	  lastNewByte <= newByte;		
			
      case(checkState)
	    stMSB:
		begin
		  if (newHeader)  begin

			checkState <= stMSB;
			checksumLong <= 17'b0;
		  end	
		  else if (newByte && !lastNewByte)  begin

			checkState <= stLSB;
			latchMSB <= inByte;
		  end	
		  else
			checkState <= stMSB;
		end
					
	    stLSB:
		begin		
		  if (newHeader)  begin

			checkState <= stMSB;
			checksumLong <= 17'b0;
		  end	
		  else if (newByte && !lastNewByte)  begin

			checkState <= stMSB;
			checksumLong <= {1'b0,checksumInt} + {1'b0,latchMSB,inByte};
		  end	
		  else
			checkState <= stLSB;
		end
					
		default:
		begin
		  checkState <= stMSB;
		end
		  
	  endcase
	  
    end
  end
	
endmodule
module internet_rx #(
  parameter [31:0] DEVICE_IP      = 32'h8d59342b
)
(
  input              clk,
  input              reset_n,
  
  input              newFrame,
  input              frameType,
  input              newFrameByte,
  input [7:0]        frameData,
  output reg         newDatagram,
  output reg  [15:0] datagramSize,
  output wire [7:0]  protocol,
  output wire [31:0] sourceIP
);




  parameter [1:0]
	RX_INT_IDLE    	           = 3'd0,	
	RX_INT_GETHEADERLEN   	   = 3'd1,	
	RX_INT_GETHEADERBYTE   	   = 3'd2,	
	RX_INT_COMPLETEFRAGMENT    = 3'd3;
  
  reg [1:0]  ip_rx_cur_fsm;
  reg [1:0]  ip_rx_nxt_fsm;
  reg [1:0]  returnState;
  reg [5:0]  headerLen;
  reg [5:0]  nextHeaderLen;
  reg [10:0] datagramLen;
  reg [10:0] nextDatagramLen;
  wire [10:0] dataLen;
  reg [10:0] nextDataLen;
  reg        incCnt;
  reg        rstCnt;
  reg [5:0]  cnt;
  reg        latchFrameData;
  reg [7:0]  frameDataLatch;
  reg [31:0] targetIP;
  reg        shiftInTargetIP;
  reg        shiftInSourceIP;
  reg        latchProtocol;

  reg        checkState;
  parameter  stMSB = 1'b0;
  parameter  stLSB = 1'b1;
  reg [16:0] checksumLong;
  wire [15:0] checksumInt;
  reg [7:0]  latchMSB;
  reg        newHeader;
  reg        newByte;
  reg        lastNewByte;
  reg [7:0]  inByte;
  wire [15:0] checksum;

  reg [15:0] identification;
  reg        shiftInIdentification;
  reg [12:0] fragmentOffset;
  reg        shiftInFragmentOffset;
  reg        moreFragments;
  reg        latchMoreFragments;

  parameter  TIMERWIDTH = 7;
  reg [6:0]  timeout0;
  reg        resetTimeout;
  parameter  FULLTIME = 7'b1111111;
  reg [31:0] sourceIPSig;
  reg [7:0]  protocolSig;


  assign sourceIP = sourceIPSig;
  assign protocol = protocolSig;
	


  assign dataLen = datagramLen - {5'b00000,headerLen[5:0]};
	


  always @(posedge clk or negedge reset_n) 
  begin

    if (!reset_n) begin
	  ip_rx_cur_fsm <= RX_INT_IDLE;
	  returnState <= RX_INT_IDLE;
	  timeout0 <= FULLTIME;
	  cnt <= 6'b0;
	  moreFragments <= 1'b0;
	end
	else begin










		ip_rx_cur_fsm <= ip_rx_nxt_fsm;
	  			

	  if (incCnt)
	    cnt <= cnt + 1;
	  else if (rstCnt)
		cnt <= 6'b0;
	  			

      if (latchFrameData)
	    frameDataLatch <= frameData;
	  			

      headerLen <= nextHeaderLen;
      datagramLen <= nextDatagramLen;


      if (shiftInSourceIP)
        sourceIPSig <= {sourceIPSig[23:0], frameData};
      
      if (shiftInTargetIP)
        targetIP <= {targetIP[23:0], frameData};
      
      if (latchProtocol)
        protocolSig <= frameData;
      
      if (shiftInFragmentOffset)
        fragmentOffset <= {fragmentOffset[4:0], frameData};
      
      if (latchMoreFragments)
        moreFragments <= frameData[5];
      
      if (shiftInIdentification)
        identification <= {identification[7:0], frameData};
      			

      if (resetTimeout)
        timeout0 <= 7'b0;
	  else begin

		if (timeout0 != FULLTIME)
		  timeout0 <= timeout0 + 1;
		else
		  timeout0 <= FULLTIME;
		
	  end
			
    end
  end



































  always @(ip_rx_cur_fsm or returnState or cnt or frameData or datagramLen or headerLen or dataLen or newFrame or frameType or checksum or targetIP or timeout0 or	fragmentOffset or moreFragments or newFrameByte)
  begin

    datagramSize <= 16'b0;
	incCnt <= 1'b0;
	rstCnt <= 1'b0;
	newDatagram <= 1'b0;

	nextHeaderLen <= headerLen;
	nextDatagramLen <= datagramLen;
	latchFrameData <= 1'b0;
	shiftInSourceIP <= 1'b0;
	shiftInTargetIP <= 1'b0;
	latchProtocol <= 1'b0;
	newHeader <= 1'b0;
	newByte <= 1'b0;
	inByte <= 8'b0;
	latchMoreFragments <= 1'b0;
	shiftInFragmentOffset <= 1'b0;

	shiftInIdentification <= 1'b0;		
	resetTimeout <= 1'b0;
	
	case(ip_rx_cur_fsm)
	  RX_INT_IDLE:
	  begin
	    resetTimeout <= 1'b1;

		if (!newFrame || !frameType)
		  ip_rx_nxt_fsm <= RX_INT_IDLE;
		else begin

		  rstCnt <= 1'b1;
		  newHeader <= 1'b1;
		  ip_rx_nxt_fsm <= RX_INT_GETHEADERLEN;
		end
	  end	  

      RX_INT_GETHEADERLEN:
	  begin
		if (newFrameByte) begin  

	      if (frameData[7:4] != 4)
		    ip_rx_nxt_fsm <= RX_INT_IDLE;
	      else begin
		    ip_rx_nxt_fsm <= RX_INT_GETHEADERBYTE;

		    inByte <= frameData;
		    newByte <= 1'b1;

		    nextHeaderLen <= {frameData[3:0], 2'b00};
	      end
		  incCnt <= 1'b1;
		end
		else
		  ip_rx_nxt_fsm <= RX_INT_GETHEADERLEN;
	  end	  
			
      RX_INT_GETHEADERBYTE:
	  begin


	    if (cnt == headerLen)  begin

	      if (checksum == 0 && (targetIP == DEVICE_IP || targetIP == 32'hFFFFFFFF))  
		    ip_rx_nxt_fsm <= RX_INT_COMPLETEFRAGMENT;
	      else

		    ip_rx_nxt_fsm <= RX_INT_IDLE;
		end			
		else if (newFrameByte) begin  




				

	      newByte <= 1'b1;
	      inByte <= frameData;
				

	      case(cnt[4:0])				
	        5'd2:
	        begin
  	          nextDatagramLen[10:8] <= frameData[2:0];
	        end	
						
	        5'd3:
	        begin
	          nextDatagramLen[7:0] <= frameData;
	        end	
						
	        5'd4, 5'd5:
	        begin
	          shiftInIdentification <= 1'b1;
	        end	
						
	        5'd6:
	        begin
	          shiftInFragmentOffset <= 1'b1;
	          latchMoreFragments <= 1'b1;
	        end	
						
	        5'd7:
	        begin
	          shiftInFragmentOffset <= 1'b1;
	        end	
						
	        5'd9:
	        begin
	          latchProtocol <= 1'b1;
	        end	
						
	        5'd12, 5'd13, 5'd14, 5'd15:
	        begin
	          shiftInSourceIP <= 1'b1;
	        end	
						
	        5'd16, 5'd17, 5'd18, 5'd19:
	        begin
 	          shiftInTargetIP <= 1'b1;
	        end	
						
	        default:
	        begin
	        end	
		  
	      endcase
		  incCnt <= 1'b1;
		  ip_rx_nxt_fsm <= RX_INT_GETHEADERBYTE;
          resetTimeout <= 1'b1;
		end
	    else if (timeout0 == FULLTIME)
		  ip_rx_nxt_fsm <= RX_INT_IDLE;

	    else begin
		  ip_rx_nxt_fsm <= RX_INT_GETHEADERBYTE;
	    end
				
	  end	  
			
	  RX_INT_COMPLETEFRAGMENT:
	  begin


		ip_rx_nxt_fsm <= RX_INT_IDLE;
		if (!moreFragments) begin

		  newDatagram <= 1'b1;
		  datagramSize <= {5'b00000, dataLen};
	    end
	  end	  
				
      default:
	  begin
 	    ip_rx_nxt_fsm <= RX_INT_IDLE;
	  end	  
	  
	endcase
  end
	

  assign checksumInt = checksumLong[15:0] + checksumLong[16];
  assign checksum = ~checksumInt;


  always @(posedge clk or negedge reset_n) 
  begin

    if (!reset_n) begin
	  checkState <= stMSB;
	  latchMSB <= 8'b0;
	  checksumLong <= 17'b0;
	  lastNewByte <= 1'b0;
	end
	else begin

	  lastNewByte <= newByte;		
			
      case(checkState)
	    stMSB:
		begin
		  if (newHeader)  begin

			checkState <= stMSB;
			checksumLong <= 17'b0;
		  end	
		  else if (newByte && !lastNewByte)  begin

			checkState <= stLSB;
			latchMSB <= inByte;
		  end	
		  else
			checkState <= stMSB;
		end
					
	    stLSB:
		begin		
		  if (newHeader)  begin

			checkState <= stMSB;
			checksumLong <= 17'b0;
		  end	
		  else if (newByte && !lastNewByte)  begin

			checkState <= stMSB;
			checksumLong <= {1'b0,checksumInt} + {1'b0,latchMSB,inByte};
		  end	
		  else
			checkState <= stLSB;
		end
					
		default:
		begin
		  checkState <= stMSB;
		end
		  
	  endcase
	  
    end
  end
	
endmodule