data/full_repos/permissive/219219909/Complex_Multiplier/vedic_3x3.v
1: b"%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_3x3.v:39: Cannot find file containing module: 'half_adder'\nhalf_adder M0 (.a(w[0]),.b(w[1]),.s(c[1]),.c(co[0]));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219219909/Complex_Multiplier,data/full_repos/permissive/219219909/half_adder\n             data/full_repos/permissive/219219909/Complex_Multiplier,data/full_repos/permissive/219219909/half_adder.v\n             data/full_repos/permissive/219219909/Complex_Multiplier,data/full_repos/permissive/219219909/half_adder.sv\n             half_adder\n             half_adder.v\n             half_adder.sv\n             obj_dir/half_adder\n             obj_dir/half_adder.v\n             obj_dir/half_adder.sv\n%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_3x3.v:40: Cannot find file containing module: 'adder_4bit'\nadder_4bit M1 (.a(w[3]),.b(w[2]),.c(co[0]),.d(w[4]),.s(c[2]),.c0(co[1]),.c1(co[2]));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_3x3.v:41: Cannot find file containing module: 'CSA_3'\nCSA_3 M2 (.a(w[5]),.b(w[6]),.c(co[1]),.s(c[3]),.co(co[3]));\n^~~~~\n%Error: data/full_repos/permissive/219219909/Complex_Multiplier/vedic_3x3.v:42: Cannot find file containing module: 'CSA_3'\nCSA_3 M3 (.a(w[7]),.b(co[2]),.c(co[3]),.s(c[4]),.co(c[5]));\n^~~~~\n%Error: Exiting due to 4 error(s)\n"
module vedic_3x3(
    input [2:0] a,
    input [2:0] b,
    output [5:0] c
    );
wire [7:0] w;
wire [3:0] co;

assign c[0]=a[0]&b[0];
assign w[0]=a[0]&b[1];
assign w[1]=a[1]&b[0];
assign w[2]=a[2]&b[0];
assign w[3]=a[0]&b[2];
assign w[4]=a[1]&b[1];
assign w[5]=a[2]&b[1];
assign w[6]=a[1]&b[2];
assign w[7]=a[2]&b[2];

half_adder M0 (.a(w[0]),.b(w[1]),.s(c[1]),.c(co[0]));
adder_4bit M1 (.a(w[3]),.b(w[2]),.c(co[0]),.d(w[4]),.s(c[2]),.c0(co[1]),.c1(co[2]));
CSA_3 M2 (.a(w[5]),.b(w[6]),.c(co[1]),.s(c[3]),.co(co[3]));
CSA_3 M3 (.a(w[7]),.b(co[2]),.c(co[3]),.s(c[4]),.co(c[5]));

endmodule
module vedic_3x3(
    input [2:0] a,
    input [2:0] b,
    output [5:0] c
    );

wire [7:0] w;
wire [3:0] co;

assign c[0]=a[0]&b[0];
assign w[0]=a[0]&b[1];
assign w[1]=a[1]&b[0];
assign w[2]=a[2]&b[0];
assign w[3]=a[0]&b[2];
assign w[4]=a[1]&b[1];
assign w[5]=a[2]&b[1];
assign w[6]=a[1]&b[2];
assign w[7]=a[2]&b[2];

half_adder M0 (.a(w[0]),.b(w[1]),.s(c[1]),.c(co[0]));
adder_4bit M1 (.a(w[3]),.b(w[2]),.c(co[0]),.d(w[4]),.s(c[2]),.c0(co[1]),.c1(co[2]));
CSA_3 M2 (.a(w[5]),.b(w[6]),.c(co[1]),.s(c[3]),.co(co[3]));
CSA_3 M3 (.a(w[7]),.b(co[2]),.c(co[3]),.s(c[4]),.co(c[5]));

endmodule