data/full_repos/permissive/132220215/testbenches/shiftReg_tb.v
 line:28: before: "clr"
1: b'%Error: data/full_repos/permissive/132220215/testbenches/shiftReg_tb.v:2: Cannot find include file: ../clock_gen.v\n`include "../clock_gen.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../clock_gen.v\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../clock_gen.v.v\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../clock_gen.v.sv\n             ../clock_gen.v\n             ../clock_gen.v.v\n             ../clock_gen.v.sv\n             obj_dir/../clock_gen.v\n             obj_dir/../clock_gen.v.v\n             obj_dir/../clock_gen.v.sv\n%Error: data/full_repos/permissive/132220215/testbenches/shiftReg_tb.v:3: Cannot find include file: ../shiftReg.v\n`include "../shiftReg.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/132220215/testbenches/shiftReg_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("ShiftReg.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/132220215/testbenches/shiftReg_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,shift_reg_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/shiftReg_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #100 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module shift_reg_tb;

 output clk_sig,Din_sig;
 input Dout_sig;

 clock #(.period(10)) CLK0(clk_sig); 
 clock #(.period(20)) D_SIG(Din_sig);
 shiftReg #(.N(4)) SR0(.Din(Din_sig),.clk(clk_sig),.Dout(Dout_sig));

 initial
 begin
	 $dumpfile("ShiftReg.vcd");
	 $dumpvars(0,shift_reg_tb);
	 #100 $finish;
 end

endmodule
module shift_reg_tb;


 output clk_sig,Din_sig;
 input Dout_sig;

 clock #(.period(10)) CLK0(clk_sig); 
 clock #(.period(20)) D_SIG(Din_sig);
 shiftReg #(.N(4)) SR0(.Din(Din_sig),.clk(clk_sig),.Dout(Dout_sig));

 initial
 begin
	 $dumpfile("ShiftReg.vcd");
	 $dumpvars(0,shift_reg_tb);
	 #100 $finish;
 end

endmodule