data/full_repos/permissive/118928497/mode1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/118928497/mode1_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #50 reset <= 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/118928497/mode1_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10 in_ai <= 8\'d3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/118928497/mode1_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10 in_ai <= 8\'d5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/118928497/mode1_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 in_ai <= 8\'d7;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/118928497/mode1_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #1done <= 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/118928497/mode1_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10done <= 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/118928497/mode1_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #9 in_ai <= 8\'d9;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/118928497/mode1_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #10 in_ai <= 8\'d11;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/118928497/mode1_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #10 enable <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/118928497/mode1_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #20 enable <= 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/118928497/mode1_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk <= ~clk;\n    ^\n%Error: data/full_repos/permissive/118928497/mode1_tb.v:9: Cannot find file containing module: \'Product_Sum\'\nProduct_Sum Product_Sum (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/118928497,data/full_repos/permissive/118928497/Product_Sum\n             data/full_repos/permissive/118928497,data/full_repos/permissive/118928497/Product_Sum.v\n             data/full_repos/permissive/118928497,data/full_repos/permissive/118928497/Product_Sum.sv\n             Product_Sum\n             Product_Sum.v\n             Product_Sum.sv\n             obj_dir/Product_Sum\n             obj_dir/Product_Sum.v\n             obj_dir/Product_Sum.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mode1_tb ();

reg clk, reset;
reg done, enable, valid_in;
reg [7:0]in_ai;
reg [7:0]in_xi;
wire [15:0]result;

Product_Sum Product_Sum (
    .clk                (clk),
    .reset              (reset),
    .done               (done),
    .enable             (enable),
    .valid_in           (valid_in),
    .in_ai              (in_ai),
    .in_xi              (in_xi),
    .result             (result)
);

initial begin
    clk <= 1;
    reset <= 1;
    done <= 0;
    enable <= 1;
    valid_in <= 1;
    #50 reset <= 0;

    in_ai <= 8'd1;
    in_xi <= 8'd2;

    #10 in_ai <= 8'd3;
    in_xi <= 8'd4;

    #10 in_ai <= 8'd5;
    in_xi <= 8'd6;

    #10 in_ai <= 8'd7;
    in_xi <= 8'd8;
    #1done <= 1'b1;
    #10done <= 1'b0;

    #9 in_ai <= 8'd9;
    in_xi <= 8'd10;

    #10 in_ai <= 8'd11;
    in_xi <= 8'd12;

    #10 enable <= 0;
    #20 enable <= 1;
end

always begin
    #5 clk <= ~clk;
end

endmodule
module mode1_tb ();


reg clk, reset;
reg done, enable, valid_in;
reg [7:0]in_ai;
reg [7:0]in_xi;
wire [15:0]result;

Product_Sum Product_Sum (
    .clk                (clk),
    .reset              (reset),
    .done               (done),
    .enable             (enable),
    .valid_in           (valid_in),
    .in_ai              (in_ai),
    .in_xi              (in_xi),
    .result             (result)
);

initial begin
    clk <= 1;
    reset <= 1;
    done <= 0;
    enable <= 1;
    valid_in <= 1;
    #50 reset <= 0;

    in_ai <= 8'd1;
    in_xi <= 8'd2;

    #10 in_ai <= 8'd3;
    in_xi <= 8'd4;

    #10 in_ai <= 8'd5;
    in_xi <= 8'd6;

    #10 in_ai <= 8'd7;
    in_xi <= 8'd8;
    #1done <= 1'b1;
    #10done <= 1'b0;

    #9 in_ai <= 8'd9;
    in_xi <= 8'd10;

    #10 in_ai <= 8'd11;
    in_xi <= 8'd12;

    #10 enable <= 0;
    #20 enable <= 1;
end

always begin
    #5 clk <= ~clk;
end

endmodule