data/full_repos/permissive/128426084/src/sim_1/imports/project_1/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/128426084/src/sim_1/imports/project_1/testbench.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/128426084/src/sim_1/imports/project_1/testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: data/full_repos/permissive/128426084/src/sim_1/imports/project_1/testbench.v:74: Unsupported: wait statements\n    wait (vs == 1\'b0);\n    ^~~~\n%Error: data/full_repos/permissive/128426084/src/sim_1/imports/project_1/testbench.v:75: syntax error, unexpected \'@\'\n    @(negedge vs) $display("Info: negedge VS at %t",$time);\n    ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;







  reg clk;
  wire pclk_mirror;
  wire vs, hs;
  wire [3:0] r, g, b;


  
  vga_example my_example (
    .clk(clk),
    .vs(vs),
    .hs(hs),
    .r(r),
    .g(g),
    .b(b),
    .pclk_mirror(pclk_mirror)
  );



  tiff_writer my_writer (
    .pclk_mirror(pclk_mirror),
    .r({r,r}),
    .g({g,g}),
    .b({b,b}),
    .go(vs),
    .xdim(16'd1056),
    .ydim(16'd628)
  );




  always
  begin
    clk = 1'b0;
    #5;
    clk = 1'b1;
    #5;
  end









   
  initial
  begin
    $display("If simulation ends before the testbench");
    $display("completes, use the menu option to run all.");
    $display("Prepare to wait a long time...");
    wait (vs == 1'b0);
    @(negedge vs) $display("Info: negedge VS at %t",$time);
    @(negedge vs) $display("Info: negedge VS at %t",$time);

    $display("Simulation is over, check the waveforms.");
    $stop;
  end

endmodule
module testbench;








  reg clk;
  wire pclk_mirror;
  wire vs, hs;
  wire [3:0] r, g, b;


  
  vga_example my_example (
    .clk(clk),
    .vs(vs),
    .hs(hs),
    .r(r),
    .g(g),
    .b(b),
    .pclk_mirror(pclk_mirror)
  );



  tiff_writer my_writer (
    .pclk_mirror(pclk_mirror),
    .r({r,r}),
    .g({g,g}),
    .b({b,b}),
    .go(vs),
    .xdim(16'd1056),
    .ydim(16'd628)
  );




  always
  begin
    clk = 1'b0;
    #5;
    clk = 1'b1;
    #5;
  end









   
  initial
  begin
    $display("If simulation ends before the testbench");
    $display("completes, use the menu option to run all.");
    $display("Prepare to wait a long time...");
    wait (vs == 1'b0);
    @(negedge vs) $display("Info: negedge VS at %t",$time);
    @(negedge vs) $display("Info: negedge VS at %t",$time);

    $display("Simulation is over, check the waveforms.");
    $stop;
  end

endmodule