data/full_repos/permissive/132220215/n_bit_adder.v
1: b'%Error: data/full_repos/permissive/132220215/n_bit_adder.v:3: Cannot find include file: full_adder.v\n`include "full_adder.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132220215,data/full_repos/permissive/132220215/full_adder.v\n             data/full_repos/permissive/132220215,data/full_repos/permissive/132220215/full_adder.v.v\n             data/full_repos/permissive/132220215,data/full_repos/permissive/132220215/full_adder.v.sv\n             full_adder.v\n             full_adder.v.v\n             full_adder.v.sv\n             obj_dir/full_adder.v\n             obj_dir/full_adder.v.v\n             obj_dir/full_adder.v.sv\n%Error: Exiting due to 1 error(s)\n'
module nBitAdder #(parameter N = 8) (
	output [N-1:0] sum,
	output cout,
	input [N-1:0] a,
	input [N-1:0] b,
	input cin);

 wire [N:0] c_int;
 assign c_int[0] = 0;
 assign cout = c_int[N];
 genvar i;

 generate
	 for(i=0;i<N;i=i+1)
	 begin
		 full_add FA(.a_sig(a[i]),.b_sig(b[i]),.cin_sig(c_int[i]),.cout_sig(c_int[i+1]),.sum_sig(sum[i]));
	 end
 endgenerate

 endmodule
module nBitAdder #(parameter N = 8) (
	output [N-1:0] sum,
	output cout,
	input [N-1:0] a,
	input [N-1:0] b,
	input cin);


 wire [N:0] c_int;
 assign c_int[0] = 0;
 assign cout = c_int[N];
 genvar i;

 generate
	 for(i=0;i<N;i=i+1)
	 begin
		 full_add FA(.a_sig(a[i]),.b_sig(b[i]),.cin_sig(c_int[i]),.cout_sig(c_int[i+1]),.sum_sig(sum[i]));
	 end
 endgenerate

 endmodule