data/full_repos/permissive/20804006/src/shift.v
1: b'%Warning-WIDTH: data/full_repos/permissive/20804006/src/shift.v:14: Operator OR expects 6 bits on the RHS, but RHS\'s VARREF \'in\' generates 1 bits.\n                                                                  : ... In instance shift\n       q <= q << 1 | in;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module shift (input            clk,
              input            rst_n,
              input            in,
              output reg [5:0] q
              );
   
   always @(posedge clk, negedge rst_n) 
     if (!rst_n) 
       q = 0;
     else 
       q <= q << 1 | in;
   
endmodule
module shift (input            clk,
              input            rst_n,
              input            in,
              output reg [5:0] q
              );

   
   always @(posedge clk, negedge rst_n) 
     if (!rst_n) 
       q = 0;
     else 
       q <= q << 1 | in;
   
endmodule