data/full_repos/permissive/159479522/tb_show_time.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/159479522/tb_show_time.v:32: Unsupported: Ignoring delay on this delayed statement.\n           #(5) clk <= ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159479522/tb_show_time.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #(5)  reset<=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/159479522/tb_show_time.v:48: Unsupported: Ignoring delay on this delayed statement.\n       #(5)   start_led<=1;\n       ^\n%Error: data/full_repos/permissive/159479522/tb_show_time.v:29: Cannot find file containing module: \'Show_time\'\n    Show_time T1(reset,clk,clk_sec,power_led,module_select,water_select,model_now,start_led,if_finish,water_level,time_now,time_all);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159479522,data/full_repos/permissive/159479522/Show_time\n             data/full_repos/permissive/159479522,data/full_repos/permissive/159479522/Show_time.v\n             data/full_repos/permissive/159479522,data/full_repos/permissive/159479522/Show_time.sv\n             Show_time\n             Show_time.v\n             Show_time.sv\n             obj_dir/Show_time\n             obj_dir/Show_time.v\n             obj_dir/Show_time.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_show_time();
reg reset,clk,clk_sec,power_led,module_select,water_select,start_led,if_finish;
    reg [2:0]model_now;
    reg [3:0] water_level;
    wire [5:0]time_now;
    wire [5:0]time_all;   
    Show_time T1(reset,clk,clk_sec,power_led,module_select,water_select,model_now,start_led,if_finish,water_level,time_now,time_all);
  
   always  begin
           #(5) clk <= ~clk;
           clk_sec<=~clk_sec;
   end    
    initial begin
        clk<=0;
        clk_sec<=0;
      reset <= 0;
      start_led<=0;
      power_led<=0;
      water_select <= 0;
      module_select <= 0;
      water_level<=2;
      if_finish<=0;
      model_now<=0;
      #(5)  reset<=1;
            power_led<=1;
       #(5)   start_led<=1;
    end
   
endmodule
module tb_show_time();

reg reset,clk,clk_sec,power_led,module_select,water_select,start_led,if_finish;
    reg [2:0]model_now;
    reg [3:0] water_level;
    wire [5:0]time_now;
    wire [5:0]time_all;   
    Show_time T1(reset,clk,clk_sec,power_led,module_select,water_select,model_now,start_led,if_finish,water_level,time_now,time_all);
  
   always  begin
           #(5) clk <= ~clk;
           clk_sec<=~clk_sec;
   end    
    initial begin
        clk<=0;
        clk_sec<=0;
      reset <= 0;
      start_led<=0;
      power_led<=0;
      water_select <= 0;
      module_select <= 0;
      water_level<=2;
      if_finish<=0;
      model_now<=0;
      #(5)  reset<=1;
            power_led<=1;
       #(5)   start_led<=1;
    end
   
endmodule