data/full_repos/permissive/211316121/lab5_2/TransFF.v
data/verilator_xmls/75e9f43b-e33a-4aff-85cf-98cd7b56ec35.xml
module TtoD(
	input d,
	input clk,
	input clr,
	input set,
	output q,
	output nq
);

wire t;

assign t=d^q;

TFF T(t,clk,clr,set,q,nq); 

endmodule
module TtoD(
	input d,
	input clk,
	input clr,
	input set,
	output q,
	output nq
);


wire t;

assign t=d^q;

TFF T(t,clk,clr,set,q,nq); 

endmodule