data/full_repos/permissive/143278/ivltests/pr2909555.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2909555.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2909555.v:13: Operator FUNCREF \'Copy\' expects 8 bits on the Function Argument, but Function Argument\'s VARREF \'a\' generates 9 bits.\n                                                                         : ... In instance top\n  assign res_a = Copy(a);\n                 ^~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2909555.v:14: Operator FUNCREF \'Copy\' expects 8 bits on the Function Argument, but Function Argument\'s VARREF \'b\' generates 7 bits.\n                                                                         : ... In instance top\n  assign res_b = Copy(b);\n                 ^~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2909555.v:15: Operator FUNCREF \'Copy\' expects 8 bits on the Function Argument, but Function Argument\'s VARREF \'c\' generates 7 bits.\n                                                                         : ... In instance top\n  assign res_c = Copy(c);\n                 ^~~~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass;

  reg  [8:0] a;
  wire [7:0] res_a;

  reg [6:0] b;
  wire [7:0] res_b;

  reg signed [6:0] c;
  wire [7:0] res_c;

  assign res_a = Copy(a);
  assign res_b = Copy(b);
  assign res_c = Copy(c);

  initial begin
    pass = 1'b1;
    a = 9'h101;
    b = -7'd1;
    c = -7'd1;
    #1;

    if (res_a !== 8'h01) begin
      $display("Failed to crop a vector, got %b.", res_a);
      pass = 1'b0;
    end

    if (res_b !== 8'h7f) begin
      $display("Failed to zero extend an unsigned vector, got %b.", res_b);
      pass = 1'b0;
    end

    if (res_c !== 8'hff) begin
      $display("Failed to sign extend a signed vector, got %b.", res_c);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end

  function [7:0] Copy;
    input [7:0] Value;
    begin
      Copy = Value;
    end
  endfunction
endmodule
module top;

  reg pass;

  reg  [8:0] a;
  wire [7:0] res_a;

  reg [6:0] b;
  wire [7:0] res_b;

  reg signed [6:0] c;
  wire [7:0] res_c;

  assign res_a = Copy(a);
  assign res_b = Copy(b);
  assign res_c = Copy(c);

  initial begin
    pass = 1'b1;
    a = 9'h101;
    b = -7'd1;
    c = -7'd1;
    #1;

    if (res_a !== 8'h01) begin
      $display("Failed to crop a vector, got %b.", res_a);
      pass = 1'b0;
    end

    if (res_b !== 8'h7f) begin
      $display("Failed to zero extend an unsigned vector, got %b.", res_b);
      pass = 1'b0;
    end

    if (res_c !== 8'hff) begin
      $display("Failed to sign extend a signed vector, got %b.", res_c);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end

  function [7:0] Copy;
    input [7:0] Value;
    begin
      Copy = Value;
    end
  endfunction
endmodule