data/full_repos/permissive/109846502/bcd2bin.v
1: b'%Warning-WIDTH: data/full_repos/permissive/109846502/bcd2bin.v:26: Operator ADD expects 32 or 14 bits on the RHS, but RHS\'s VARREF \'N4\' generates 4 bits.\n                                                                 : ... In instance bcd2bin\nassign out = N1 * 1000 + N2 * 100 + N3 * 10 + N4;\n                                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module bcd2bin(
		input [3:0] N1, N2, N3, N4,
		output [13:0] out
    );
	 
assign out = N1 * 1000 + N2 * 100 + N3 * 10 + N4;

endmodule
module bcd2bin(
		input [3:0] N1, N2, N3, N4,
		output [13:0] out
    );

	 
assign out = N1 * 1000 + N2 * 100 + N3 * 10 + N4;

endmodule