data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_wr.v
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1: b"%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_wr.v:50: Cannot find file containing module: 'uart_rtl'\n uart_rtl   uart_rtl_inst(\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart,data/full_repos/permissive/143584361/uart_rtl\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart,data/full_repos/permissive/143584361/uart_rtl.v\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart,data/full_repos/permissive/143584361/uart_rtl.sv\n             uart_rtl\n             uart_rtl.v\n             uart_rtl.sv\n             obj_dir/uart_rtl\n             obj_dir/uart_rtl.v\n             obj_dir/uart_rtl.sv\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_wr.v:65: Cannot find file containing module: 'dc_fifo'\n dc_fifo    #(\n ^~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_wr.v:83: Cannot find file containing module: 'dc_fifo'\n dc_fifo    #(\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module uart_wr
#(	
	parameter	UART_DATA_WIDTH = 8,
	parameter	UART_ADDR_WIDTH = 2,
	parameter	SYS_UART_DATA_MULT = 4,
	parameter	SYS_DATA_WIDTH = UART_DATA_WIDTH*SYS_UART_DATA_MULT
)
(
	input	wire						sys_clk, sys_rst_n,

	input	wire						uart_sys_clk, uart_sys_rst_n,
	input	wire						uart_rxd,
	output	wire						uart_txd,
	

	input		[SYS_DATA_WIDTH-1:0]	sys_write_data,
	input								sys_write_data_valid,
	output								sys_write_data_permitted,
	output		[UART_DATA_WIDTH-1:0]	sys_read_data,
	input								sys_read_data_req,
	output								sys_read_data_permitted
	);
	wire								logic_uart_write_data_empty;
	wire		[SYS_DATA_WIDTH-1:0]	logic_uart_write_data;
	wire								logic_uart_write_data_valid = !logic_uart_write_data_empty;
	wire								logic_uart_write_data_req;
	wire		[UART_DATA_WIDTH-1:0]	logic_uart_read_data;
	wire								logic_uart_read_data_valid;

	wire		[SYS_DATA_WIDTH-1:0]	logic_fifo_write_data;
	wire								logic_fifo_write_data_valid;
	wire		[5:0]					logic_fifo_write_usedw;
	wire								logic_fifo_write_full;
	wire		[UART_DATA_WIDTH-1:0]	logic_fifo_read_data;
	wire								logic_fifo_read_data_req;
	wire								logic_fifo_read_empty;


	assign		logic_fifo_write_data = sys_write_data;
	assign		logic_fifo_write_data_valid = sys_write_data_valid;
	assign		sys_write_data_permitted = (logic_fifo_write_usedw[5:3]==0);
	assign		sys_read_data = logic_fifo_read_data;
	assign		logic_fifo_read_data_req = sys_read_data_req;
	assign		sys_read_data_permitted = !logic_fifo_read_empty;
	
	
	wire		uart_tx_busy;
	assign		logic_uart_write_data_req = !uart_tx_busy && !logic_uart_write_data_empty;

	uart_rtl			uart_rtl_inst(
							.clock(uart_sys_clk),
							.rst(!uart_sys_rst_n),
							.uart_rxd(uart_rxd),
							.uart_txd(uart_txd),

							.rx_en(logic_uart_read_data_valid),
							.rx_data(logic_uart_read_data),
							.tx_en(logic_uart_write_data_req),
							.tx_busy(uart_tx_busy),
							.tx_data(logic_uart_write_data)
						);
						


	dc_fifo				#(
							.LOG2N(6),
							.DATA_WIDTH(32)
						)
						alt_fifo_32b_64w_inst(
							.aclr(!uart_sys_rst_n),
							.wrclock(sys_clk),
							.wrreq(logic_fifo_write_data_valid),
							.data(logic_fifo_write_data),
							.wrfull(logic_fifo_write_full),
							.wrusedw(logic_fifo_write_usedw),
							.rdclock(uart_sys_clk),
							.rdreq(logic_uart_write_data_req),
							.q(logic_uart_write_data),
							.rdempty(logic_uart_write_data_empty)
						);	


	dc_fifo				#(
							.LOG2N(4),
							.DATA_WIDTH(8)
						)
						alt_fifo_8b_4w_inst(
							.aclr(!uart_sys_rst_n),
							.wrclock(uart_sys_clk),
							.wrreq(logic_uart_read_data_valid),
							.data(logic_uart_read_data),
							.rdclock(sys_clk),
							.rdreq(logic_fifo_read_data_req),
							.q(logic_fifo_read_data),
							.rdempty(logic_fifo_read_empty)
						);
						
endmodule
module uart_wr
#(	
	parameter	UART_DATA_WIDTH = 8,
	parameter	UART_ADDR_WIDTH = 2,
	parameter	SYS_UART_DATA_MULT = 4,
	parameter	SYS_DATA_WIDTH = UART_DATA_WIDTH*SYS_UART_DATA_MULT
)
(
	input	wire						sys_clk, sys_rst_n,

	input	wire						uart_sys_clk, uart_sys_rst_n,
	input	wire						uart_rxd,
	output	wire						uart_txd,
	

	input		[SYS_DATA_WIDTH-1:0]	sys_write_data,
	input								sys_write_data_valid,
	output								sys_write_data_permitted,
	output		[UART_DATA_WIDTH-1:0]	sys_read_data,
	input								sys_read_data_req,
	output								sys_read_data_permitted
	);

	wire								logic_uart_write_data_empty;
	wire		[SYS_DATA_WIDTH-1:0]	logic_uart_write_data;
	wire								logic_uart_write_data_valid = !logic_uart_write_data_empty;
	wire								logic_uart_write_data_req;
	wire		[UART_DATA_WIDTH-1:0]	logic_uart_read_data;
	wire								logic_uart_read_data_valid;

	wire		[SYS_DATA_WIDTH-1:0]	logic_fifo_write_data;
	wire								logic_fifo_write_data_valid;
	wire		[5:0]					logic_fifo_write_usedw;
	wire								logic_fifo_write_full;
	wire		[UART_DATA_WIDTH-1:0]	logic_fifo_read_data;
	wire								logic_fifo_read_data_req;
	wire								logic_fifo_read_empty;


	assign		logic_fifo_write_data = sys_write_data;
	assign		logic_fifo_write_data_valid = sys_write_data_valid;
	assign		sys_write_data_permitted = (logic_fifo_write_usedw[5:3]==0);
	assign		sys_read_data = logic_fifo_read_data;
	assign		logic_fifo_read_data_req = sys_read_data_req;
	assign		sys_read_data_permitted = !logic_fifo_read_empty;
	
	
	wire		uart_tx_busy;
	assign		logic_uart_write_data_req = !uart_tx_busy && !logic_uart_write_data_empty;

	uart_rtl			uart_rtl_inst(
							.clock(uart_sys_clk),
							.rst(!uart_sys_rst_n),
							.uart_rxd(uart_rxd),
							.uart_txd(uart_txd),

							.rx_en(logic_uart_read_data_valid),
							.rx_data(logic_uart_read_data),
							.tx_en(logic_uart_write_data_req),
							.tx_busy(uart_tx_busy),
							.tx_data(logic_uart_write_data)
						);
						


	dc_fifo				#(
							.LOG2N(6),
							.DATA_WIDTH(32)
						)
						alt_fifo_32b_64w_inst(
							.aclr(!uart_sys_rst_n),
							.wrclock(sys_clk),
							.wrreq(logic_fifo_write_data_valid),
							.data(logic_fifo_write_data),
							.wrfull(logic_fifo_write_full),
							.wrusedw(logic_fifo_write_usedw),
							.rdclock(uart_sys_clk),
							.rdreq(logic_uart_write_data_req),
							.q(logic_uart_write_data),
							.rdempty(logic_uart_write_data_empty)
						);	


	dc_fifo				#(
							.LOG2N(4),
							.DATA_WIDTH(8)
						)
						alt_fifo_8b_4w_inst(
							.aclr(!uart_sys_rst_n),
							.wrclock(uart_sys_clk),
							.wrreq(logic_uart_read_data_valid),
							.data(logic_uart_read_data),
							.rdclock(sys_clk),
							.rdreq(logic_fifo_read_data_req),
							.q(logic_fifo_read_data),
							.rdempty(logic_fifo_read_empty)
						);
						
endmodule