data/full_repos/permissive/190595283/Modulos/AND.v
data/verilator_xmls/12286e21-6ff4-4bfb-9484-96f85af1b338.xml
module Door_BNE_BEQ (branch,flag,out);
  input [1:0] branch;
  input flag;
  output reg out;
  always @ ( * ) begin
  case (branch)
    2'b00: out = 0;
    2'b11: out = (flag == 1) ? 1 : 0;
    2'b01: out = (flag != 1) ? 1 : 0;
    default: out = 0;
  endcase
  end
endmodule
module Door_BNE_BEQ (branch,flag,out);

  input [1:0] branch;
  input flag;
  output reg out;
  always @ ( * ) begin
  case (branch)
    2'b00: out = 0;
    2'b11: out = (flag == 1) ? 1 : 0;
    2'b01: out = (flag != 1) ? 1 : 0;
    default: out = 0;
  endcase
  end
endmodule