data/full_repos/permissive/169220768/code/mux4.v
data/verilator_xmls/9f3fc0c1-ae1f-4cb9-97f9-e618d7b6807a.xml
module mux4 #(parameter WIDTH = 32)(
    input [1:0] sel,
    input [WIDTH-1:0] d0,
    input [WIDTH-1:0] d1,
	 input [WIDTH-1:0] d2,
	 input [WIDTH-1:0] d3,
    output reg [WIDTH-1:0] out
    );
	always@(*)
		case(sel)
			2'b00: out=d0;
			2'b01: out=d1;
			2'b10: out=d2;
			2'b11: out=d3;
			default:;
		endcase
endmodule
module mux4 #(parameter WIDTH = 32)(
    input [1:0] sel,
    input [WIDTH-1:0] d0,
    input [WIDTH-1:0] d1,
	 input [WIDTH-1:0] d2,
	 input [WIDTH-1:0] d3,
    output reg [WIDTH-1:0] out
    );

	always@(*)
		case(sel)
			2'b00: out=d0;
			2'b01: out=d1;
			2'b10: out=d2;
			2'b11: out=d3;
			default:;
		endcase
endmodule