data/full_repos/permissive/123318949/08 - Ready-made OR gate/tb_or_gate.v
1: b'%Error: Invalid Option: -\n'
module stimulate (
  output clk,
  output [9:0] out
  );

  reg clock = 1'b1;
  reg [9:0] out_s = 10'b0000000000;

  initial begin
    while (1) begin
      #1; clock <= 1'b0;
      #1; clock <= 1'b1;
    end
  end

  always @(posedge clk) begin
    out_s <= out_s + 1;
  end

  assign clk = clock;
  assign out = out_s;

endmodule
module stimulate (
  output clk,
  output [9:0] out
  );


  reg clock = 1'b1;
  reg [9:0] out_s = 10'b0000000000;

  initial begin
    while (1) begin
      #1; clock <= 1'b0;
      #1; clock <= 1'b1;
    end
  end

  always @(posedge clk) begin
    out_s <= out_s + 1;
  end

  assign clk = clock;
  assign out = out_s;

endmodule