data/full_repos/permissive/147690299/lab/13_comb_mux_Nbit/rtl/b2_mux_3_1.v
 line:52: before: "("
1: b'%Warning-MULTITOP: data/full_repos/permissive/147690299/lab/13_comb_mux_Nbit/rtl/b2_mux_3_1.v:21: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'b2_mux_3_1_case_full\'\nmodule b2_mux_3_1_case_full\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'b2_mux_3_1_case\'\nmodule b2_mux_3_1_case\n       ^~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'b2_mux_3_1_case_default\'\nmodule b2_mux_3_1_case_default\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'b2_mux_3_1_casez\'\nmodule b2_mux_3_1_casez\n       ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module b2_mux_3_1_casez
#(
    parameter WIDTH = 1
)(
    input      [WIDTH-1:0] d0, d1, d2, 
    input      [      1:0] sel,
    output reg [WIDTH-1:0] y
);

    always @(*)
        casez (sel)
            2'b00: y = d0;
            2'b01: y = d1;
            2'b1?: y = d2;
        endcase
endmodule
module b2_mux_3_1_casez
#(
    parameter WIDTH = 1
)(
    input      [WIDTH-1:0] d0, d1, d2, 
    input      [      1:0] sel,
    output reg [WIDTH-1:0] y
);


    always @(*)
        casez (sel)
            2'b00: y = d0;
            2'b01: y = d1;
            2'b1?: y = d2;
        endcase
endmodule