data/full_repos/permissive/138243369/f3_keyproc.v
data/verilator_xmls/c29cb1e5-51e3-4312-96fc-964eba216e7b.xml
module f3_keyproc(
input wire [4:0] func3_keys,
output reg scramble,
output reg [3:0] instruction);










initial begin
	instruction = 4'd0;
end

always @(*) begin

	if (func3_keys[4]) begin


		if (func3_keys[3]) begin
			instruction = 4'd5;
		end
		else begin
			instruction = 4'd2;
		end
	end
	else if (func3_keys[3]) begin


		if (func3_keys[4]) begin
			instruction = 4'd5;
		end
		else begin
			instruction = 4'd3;
		end
	end
	else if (func3_keys[2]) begin

		instruction = 4'd1;
	end
	else if (func3_keys[1]) begin

		instruction = 4'd4;
	end
	else begin
		instruction = 4'd0;
	end

	scramble = func3_keys[0];
end

endmodule
module f3_keyproc(
input wire [4:0] func3_keys,
output reg scramble,
output reg [3:0] instruction);











initial begin
	instruction = 4'd0;
end

always @(*) begin

	if (func3_keys[4]) begin


		if (func3_keys[3]) begin
			instruction = 4'd5;
		end
		else begin
			instruction = 4'd2;
		end
	end
	else if (func3_keys[3]) begin


		if (func3_keys[4]) begin
			instruction = 4'd5;
		end
		else begin
			instruction = 4'd3;
		end
	end
	else if (func3_keys[2]) begin

		instruction = 4'd1;
	end
	else if (func3_keys[1]) begin

		instruction = 4'd4;
	end
	else begin
		instruction = 4'd0;
	end

	scramble = func3_keys[0];
end

endmodule