data/full_repos/permissive/115920613/rtl/ram.v
data/verilator_xmls/2c2a6d23-66cc-49fc-8576-ab079a89003d.xml
module ram #(
    parameter RAM_FILENAME        = "../../../roms/ram.hex"
) (
    input clk,
    input [12:0] address,
    input w_en,
    input [7:0] din,
    output reg [7:0] dout
);

    reg [7:0] ram_data[0:8191];

    initial
        $readmemh(RAM_FILENAME, ram_data, 0, 8191);

    always @(posedge clk)
    begin
        dout <= ram_data[address];
        if (w_en) ram_data[address] <= din;
    end

endmodule
module ram #(
    parameter RAM_FILENAME        = "../../../roms/ram.hex"
) (
    input clk,
    input [12:0] address,
    input w_en,
    input [7:0] din,
    output reg [7:0] dout
);


    reg [7:0] ram_data[0:8191];

    initial
        $readmemh(RAM_FILENAME, ram_data, 0, 8191);

    always @(posedge clk)
    begin
        dout <= ram_data[address];
        if (w_en) ram_data[address] <= din;
    end

endmodule