data/full_repos/permissive/132439949/sources_1/new/get_clock_2Hz.v
 line:27: before: ","
data/verilator_xmls/6d19b721-42d3-430b-bacb-e229a5f5a9bb.xml
module get_clock_2Hz(
    input CLOCK,
    output reg new_clk
    );
    
    initial begin
        new_clk = 0;
    end
    
    reg [24:0] COUNT = 25'b0;
    
    always @ (posedge CLOCK) begin
        COUNT <= COUNT + 1;
        new_clk <= (COUNT == 25'b0) ? ~new_clk : new_clk;
    end
    
endmodule
module get_clock_2Hz(
    input CLOCK,
    output reg new_clk
    );

    
    initial begin
        new_clk = 0;
    end
    
    reg [24:0] COUNT = 25'b0;
    
    always @ (posedge CLOCK) begin
        COUNT <= COUNT + 1;
        new_clk <= (COUNT == 25'b0) ? ~new_clk : new_clk;
    end
    
endmodule