data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v
1: b'%Warning-WIDTH: data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v:757: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h2a\' generates 6 bits.\n                                                                              : ... In instance pipeline_riscv.ALU\n    case (alu_code)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v:526: Operator EQ expects 6 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                              : ... In instance pipeline_riscv.CTRL\n    if (rd[1]!=0 && ((J_type[1] && funct[1]==7\'h08) || S_type[1]==6\'h2B)) begin\n                                                                ^~\n%Error: Exiting due to 2 warning(s)\n'
module rf (
  input           clk,
  input           nrst,
  input           wr_en,
  input   [4:0]   rd_addrA,
  input   [4:0]   rd_addrB,
  input   [4:0]   wr_addr,
  input   [31:0]  wr_data,
  output  [31:0]  rd_dataA,
  output  [31:0]  rd_dataB
  );

  reg [31:0] mem [31:0];
  integer i;
  assign rd_dataA = mem[rd_addrA];
  assign rd_dataB = mem[rd_addrB];

	always@(posedge clk) begin
		if (!nrst)
			for (i=0;i<=31;i=i+1)
				mem[i] <= 0;
		else
			if (wr_en)
				if (wr_addr!=0)
					mem[wr_addr] <= wr_data;
	end

endmodule
module rf (
  input           clk,
  input           nrst,
  input           wr_en,
  input   [4:0]   rd_addrA,
  input   [4:0]   rd_addrB,
  input   [4:0]   wr_addr,
  input   [31:0]  wr_data,
  output  [31:0]  rd_dataA,
  output  [31:0]  rd_dataB
  );


  reg [31:0] mem [31:0];
  integer i;
  assign rd_dataA = mem[rd_addrA];
  assign rd_dataB = mem[rd_addrB];

	always@(posedge clk) begin
		if (!nrst)
			for (i=0;i<=31;i=i+1)
				mem[i] <= 0;
		else
			if (wr_en)
				if (wr_addr!=0)
					mem[wr_addr] <= wr_data;
	end

endmodule