data/full_repos/permissive/207610706/src/aes_encryption_decryption/aes_cipher.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/207610706/src/aes_encryption_decryption/aes_cipher.sv:1: Cannot find include file: aeses_defines.vh\n`include "aeses_defines.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207610706/src/aes_encryption_decryption,data/full_repos/permissive/207610706/aeses_defines.vh\n             data/full_repos/permissive/207610706/src/aes_encryption_decryption,data/full_repos/permissive/207610706/aeses_defines.vh.v\n             data/full_repos/permissive/207610706/src/aes_encryption_decryption,data/full_repos/permissive/207610706/aeses_defines.vh.sv\n             aeses_defines.vh\n             aeses_defines.vh.v\n             aeses_defines.vh.sv\n             obj_dir/aeses_defines.vh\n             obj_dir/aeses_defines.vh.v\n             obj_dir/aeses_defines.vh.sv\n%Error: data/full_repos/permissive/207610706/src/aes_encryption_decryption/aes_cipher.sv:102: Define or directive not defined: \'`KEY_256\'\n                if(mode == `KEY_256)\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/aes_encryption_decryption/aes_cipher.sv:102: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                if(mode == `KEY_256)\n                                   ^\n%Error: data/full_repos/permissive/207610706/src/aes_encryption_decryption/aes_cipher.sv:104: Define or directive not defined: \'`KEY_192\'\n                else if(mode == `KEY_192)\n                                ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module aes_cipher(
        clk, rst,
        pctx, e_dneg,
        round_key, inv_round_key,
        mode, start_operation,
        cptx, valid_cptx);

input clk, rst;

input [0:127] pctx;
input e_dneg;
input [0:127] round_key, inv_round_key;

input [1:0] mode;
input start_operation;

output [0:127] cptx;
output reg valid_cptx;


localparam IDLE = 1'b0;
localparam OPERATION = 1'b1;


reg state;
reg [0:127] aes_state;
reg [3:0] round_count;


wire [0:127] xored_next_state;
wire [0:127] no_mix_col_next_state;
wire [0:127] r_key;


reg [3:0] next_round_count;
reg next_state;
reg next_valid_cptx;

reg [0:127] next_aes_state;
reg next_aes_state_we;


always@(posedge clk)
begin
    if(rst)
    begin
        state <= IDLE;
        round_count <= 4'd0;
        valid_cptx <= 1'b0;
    end
    else
    begin
        state <= next_state;
        round_count <= next_round_count;
        valid_cptx <= next_valid_cptx;
    end
end

always@(posedge clk)
begin
    if(!rst && next_aes_state_we)
        aes_state <= next_aes_state;
end




always@(*)
begin
    next_round_count = round_count;
    next_state = state;
    next_valid_cptx = 1'b0;
    
    case(state)
        IDLE:
            begin
            if(start_operation)
                begin
                next_state = OPERATION;
                
                if(mode == `KEY_256)
                    next_round_count = 4'd0;
                else if(mode == `KEY_192)
                    next_round_count = 4'd2;
                else
                    next_round_count = 4'd4;
                
                end
            end
        OPERATION:
            begin
            next_round_count = round_count + 1;
            if(round_count == 4'd13)
                begin
                next_state = IDLE;
                next_valid_cptx = 1'b1;
                end
            end
    endcase
end


reg [0:127] pre_keyaddition_1, pre_keyaddition;
reg no_mix_col_round;

always@(*)
begin


    no_mix_col_round = round_count == 4'd13;
    


    pre_keyaddition_1 = no_mix_col_round ? no_mix_col_next_state : pctx;
    pre_keyaddition = ~no_mix_col_round && state != IDLE ? xored_next_state : pre_keyaddition_1;
    
    next_aes_state = pre_keyaddition ^ r_key;
    
    next_aes_state_we = state != IDLE | start_operation;
end


wire [31:0] aes_state_words[0:3];
wire [0:79] sbox_tbox_mapping[0:15];

wire [0:7] sbox_mapping [0:15];
wire [0:31] tbox_mapping [0:15];



genvar i;
generate
    for(i = 0; i < 4; i++)
        begin: split_aes_state
        assign aes_state_words[i] = aes_state[i*32:(i+1)*32-1];
        end
endgenerate


direct_sbox_tbox st0(aes_state_words[0], sbox_tbox_mapping[0:3]);
direct_sbox_tbox st1(aes_state_words[1], sbox_tbox_mapping[4:7]);
direct_sbox_tbox st2(aes_state_words[2], sbox_tbox_mapping[8:11]);
direct_sbox_tbox st3(aes_state_words[3], sbox_tbox_mapping[12:15]);


genvar j;
generate
    for(j = 0; j < 16; j=j+1)
    begin: encryption_decryption_xor_mux
        assign tbox_mapping[j] = e_dneg ? sbox_tbox_mapping[(5*j)%16][8:39]:
            sbox_tbox_mapping[(13*j)%16][48:79];
        assign sbox_mapping[j] = e_dneg ? sbox_tbox_mapping[(5*j)%16][0:7]:
            sbox_tbox_mapping[(13*j)%16][40:47];
    end
endgenerate


assign r_key = e_dneg ? round_key : inv_round_key;




assign no_mix_col_next_state =
    {sbox_mapping[0], sbox_mapping[1], sbox_mapping[2], sbox_mapping[3],
     sbox_mapping[4], sbox_mapping[5], sbox_mapping[6], sbox_mapping[7],
     sbox_mapping[8], sbox_mapping[9], sbox_mapping[10], sbox_mapping[11],
     sbox_mapping[12], sbox_mapping[13], sbox_mapping[14], sbox_mapping[15]};

assign xored_next_state =
    {tbox_mapping[0] ^ tbox_mapping[1] ^ tbox_mapping[2] ^ tbox_mapping[3],
     tbox_mapping[4] ^ tbox_mapping[5] ^ tbox_mapping[6] ^ tbox_mapping[7],
     tbox_mapping[8] ^ tbox_mapping[9] ^ tbox_mapping[10] ^ tbox_mapping[11],
     tbox_mapping[12] ^ tbox_mapping[13] ^ tbox_mapping[14] ^ tbox_mapping[15]};


assign cptx = valid_cptx ? aes_state : {64{2'b10}};

endmodule
module aes_cipher(
        clk, rst,
        pctx, e_dneg,
        round_key, inv_round_key,
        mode, start_operation,
        cptx, valid_cptx);


input clk, rst;

input [0:127] pctx;
input e_dneg;
input [0:127] round_key, inv_round_key;

input [1:0] mode;
input start_operation;

output [0:127] cptx;
output reg valid_cptx;


localparam IDLE = 1'b0;
localparam OPERATION = 1'b1;


reg state;
reg [0:127] aes_state;
reg [3:0] round_count;


wire [0:127] xored_next_state;
wire [0:127] no_mix_col_next_state;
wire [0:127] r_key;


reg [3:0] next_round_count;
reg next_state;
reg next_valid_cptx;

reg [0:127] next_aes_state;
reg next_aes_state_we;


always@(posedge clk)
begin
    if(rst)
    begin
        state <= IDLE;
        round_count <= 4'd0;
        valid_cptx <= 1'b0;
    end
    else
    begin
        state <= next_state;
        round_count <= next_round_count;
        valid_cptx <= next_valid_cptx;
    end
end

always@(posedge clk)
begin
    if(!rst && next_aes_state_we)
        aes_state <= next_aes_state;
end




always@(*)
begin
    next_round_count = round_count;
    next_state = state;
    next_valid_cptx = 1'b0;
    
    case(state)
        IDLE:
            begin
            if(start_operation)
                begin
                next_state = OPERATION;
                
                if(mode == `KEY_256)
                    next_round_count = 4'd0;
                else if(mode == `KEY_192)
                    next_round_count = 4'd2;
                else
                    next_round_count = 4'd4;
                
                end
            end
        OPERATION:
            begin
            next_round_count = round_count + 1;
            if(round_count == 4'd13)
                begin
                next_state = IDLE;
                next_valid_cptx = 1'b1;
                end
            end
    endcase
end


reg [0:127] pre_keyaddition_1, pre_keyaddition;
reg no_mix_col_round;

always@(*)
begin


    no_mix_col_round = round_count == 4'd13;
    


    pre_keyaddition_1 = no_mix_col_round ? no_mix_col_next_state : pctx;
    pre_keyaddition = ~no_mix_col_round && state != IDLE ? xored_next_state : pre_keyaddition_1;
    
    next_aes_state = pre_keyaddition ^ r_key;
    
    next_aes_state_we = state != IDLE | start_operation;
end


wire [31:0] aes_state_words[0:3];
wire [0:79] sbox_tbox_mapping[0:15];

wire [0:7] sbox_mapping [0:15];
wire [0:31] tbox_mapping [0:15];



genvar i;
generate
    for(i = 0; i < 4; i++)
        begin: split_aes_state
        assign aes_state_words[i] = aes_state[i*32:(i+1)*32-1];
        end
endgenerate


direct_sbox_tbox st0(aes_state_words[0], sbox_tbox_mapping[0:3]);
direct_sbox_tbox st1(aes_state_words[1], sbox_tbox_mapping[4:7]);
direct_sbox_tbox st2(aes_state_words[2], sbox_tbox_mapping[8:11]);
direct_sbox_tbox st3(aes_state_words[3], sbox_tbox_mapping[12:15]);


genvar j;
generate
    for(j = 0; j < 16; j=j+1)
    begin: encryption_decryption_xor_mux
        assign tbox_mapping[j] = e_dneg ? sbox_tbox_mapping[(5*j)%16][8:39]:
            sbox_tbox_mapping[(13*j)%16][48:79];
        assign sbox_mapping[j] = e_dneg ? sbox_tbox_mapping[(5*j)%16][0:7]:
            sbox_tbox_mapping[(13*j)%16][40:47];
    end
endgenerate


assign r_key = e_dneg ? round_key : inv_round_key;




assign no_mix_col_next_state =
    {sbox_mapping[0], sbox_mapping[1], sbox_mapping[2], sbox_mapping[3],
     sbox_mapping[4], sbox_mapping[5], sbox_mapping[6], sbox_mapping[7],
     sbox_mapping[8], sbox_mapping[9], sbox_mapping[10], sbox_mapping[11],
     sbox_mapping[12], sbox_mapping[13], sbox_mapping[14], sbox_mapping[15]};

assign xored_next_state =
    {tbox_mapping[0] ^ tbox_mapping[1] ^ tbox_mapping[2] ^ tbox_mapping[3],
     tbox_mapping[4] ^ tbox_mapping[5] ^ tbox_mapping[6] ^ tbox_mapping[7],
     tbox_mapping[8] ^ tbox_mapping[9] ^ tbox_mapping[10] ^ tbox_mapping[11],
     tbox_mapping[12] ^ tbox_mapping[13] ^ tbox_mapping[14] ^ tbox_mapping[15]};


assign cptx = valid_cptx ? aes_state : {64{2'b10}};

endmodule