data/full_repos/permissive/141490569/SENSOR-TEST/hdl/spi/spi_control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/141490569/SENSOR-TEST/hdl/spi/spi_control.v:99: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h10\' generates 5 bits.\n                                                                                         : ... In instance spi_control\n   spi_pos <= 5\'h10;\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/141490569/SENSOR-TEST/hdl/spi/spi_control.v:133: Bit extraction of var[7:0] requires 3 bit index, not 6 bits.\n                                                                                          : ... In instance spi_control\n     spi_data_out[spi_pos] <= miso;\n                 ^\n%Error: Exiting due to 2 warning(s)\n'
module spi_control (
	input  wire        clk,
	input  wire        reset,


	output reg         sclk,
	input  wire        miso,
	output reg         mosi,
	output reg         miso_mosi_dir,
	output reg         cs_n,


	input  wire [6:0]  spi_reg,
	input  wire [7:0]  spi_data_in,
	output reg  [7:0]  spi_data_out,
	input  wire        spi_send,
	output reg         spi_done,
	input  wire        spi_rw
	);
	
parameter DIVIDE_COUNT = 32'd125;

reg  [31:0] divide_counter;
reg         clk_en, spi_done_r;

wire [7:0]  instruction_word;
wire [15:0] full_transfer_word;


reg  [5:0] spi_pos;



assign instruction_word = {spi_rw, spi_reg};

assign full_transfer_word = {instruction_word, spi_data_in};


always @(posedge clk) begin
	if (reset == 1'b1) begin
		divide_counter <= 32'h00;
		clk_en <= 1'b0;
	end else begin
		divide_counter <= divide_counter + 1'b1;
		clk_en <= 1'b0;

		if (divide_counter == DIVIDE_COUNT) begin
			divide_counter <= 32'h00;
			clk_en <= 1'b1;
		end
	end
end


always @(posedge clk) begin
	if (reset == 1'b1) begin
		sclk <= 1'b1;
		cs_n <= 1'b1;

		spi_data_out <= 8'h00;
		spi_done     <= 1'b1;
		spi_done_r   <= 1'b1;

		miso_mosi_dir <= 1'b0;
		mosi          <= 1'b1;
		spi_pos       <= 6'h0;
	end else begin

		if (spi_send == 1'b1 && spi_done == 1'b1) begin
			spi_pos <= 5'h10;
			sclk <= 1'b1;
			cs_n <= 1'b0;
			spi_done <= 1'b0;
			spi_done_r <= 1'b0;
		end

		if (clk_en == 1'b1) begin
			if (spi_rw == 1'b1 && spi_pos <= 8) begin
				miso_mosi_dir <= 1'b0;
			end else begin
				miso_mosi_dir <= 1'b1;
			end
			

			sclk <= ~sclk;

			if (sclk == 1'b1) begin
				if (spi_pos > 6'h0) begin
					spi_pos  <= spi_pos - 1'b1;
					spi_done <= 1'b0;
					spi_done_r <= 1'b0;
				end else begin
					cs_n <= 1'b1;
					spi_done_r <= 1'b1;
					spi_done <= spi_done_r;
					sclk <= 1'b1;
				end
				
				mosi <= full_transfer_word[spi_pos - 1];
			end
			
			if (sclk == 1'b0) begin
				if (spi_pos < 8) begin
					spi_data_out[spi_pos] <= miso;
				end
			end
		end
	end
end

endmodule
module spi_control (
	input  wire        clk,
	input  wire        reset,


	output reg         sclk,
	input  wire        miso,
	output reg         mosi,
	output reg         miso_mosi_dir,
	output reg         cs_n,


	input  wire [6:0]  spi_reg,
	input  wire [7:0]  spi_data_in,
	output reg  [7:0]  spi_data_out,
	input  wire        spi_send,
	output reg         spi_done,
	input  wire        spi_rw
	);

	
parameter DIVIDE_COUNT = 32'd125;

reg  [31:0] divide_counter;
reg         clk_en, spi_done_r;

wire [7:0]  instruction_word;
wire [15:0] full_transfer_word;


reg  [5:0] spi_pos;



assign instruction_word = {spi_rw, spi_reg};

assign full_transfer_word = {instruction_word, spi_data_in};


always @(posedge clk) begin
	if (reset == 1'b1) begin
		divide_counter <= 32'h00;
		clk_en <= 1'b0;
	end else begin
		divide_counter <= divide_counter + 1'b1;
		clk_en <= 1'b0;

		if (divide_counter == DIVIDE_COUNT) begin
			divide_counter <= 32'h00;
			clk_en <= 1'b1;
		end
	end
end


always @(posedge clk) begin
	if (reset == 1'b1) begin
		sclk <= 1'b1;
		cs_n <= 1'b1;

		spi_data_out <= 8'h00;
		spi_done     <= 1'b1;
		spi_done_r   <= 1'b1;

		miso_mosi_dir <= 1'b0;
		mosi          <= 1'b1;
		spi_pos       <= 6'h0;
	end else begin

		if (spi_send == 1'b1 && spi_done == 1'b1) begin
			spi_pos <= 5'h10;
			sclk <= 1'b1;
			cs_n <= 1'b0;
			spi_done <= 1'b0;
			spi_done_r <= 1'b0;
		end

		if (clk_en == 1'b1) begin
			if (spi_rw == 1'b1 && spi_pos <= 8) begin
				miso_mosi_dir <= 1'b0;
			end else begin
				miso_mosi_dir <= 1'b1;
			end
			

			sclk <= ~sclk;

			if (sclk == 1'b1) begin
				if (spi_pos > 6'h0) begin
					spi_pos  <= spi_pos - 1'b1;
					spi_done <= 1'b0;
					spi_done_r <= 1'b0;
				end else begin
					cs_n <= 1'b1;
					spi_done_r <= 1'b1;
					spi_done <= spi_done_r;
					sclk <= 1'b1;
				end
				
				mosi <= full_transfer_word[spi_pos - 1];
			end
			
			if (sclk == 1'b0) begin
				if (spi_pos < 8) begin
					spi_data_out[spi_pos] <= miso;
				end
			end
		end
	end
end

endmodule