data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\nalways #(t/2) clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #(t*8)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #(t*2)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #(t*5)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #t\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #(t)\n ^\n%Error: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:809: Cannot find file containing module: \'mult\'\nmult u1 (\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/141578247/TESTBENCH_simple,data/full_repos/permissive/141578247/mult\n             data/full_repos/permissive/141578247/TESTBENCH_simple,data/full_repos/permissive/141578247/mult.v\n             data/full_repos/permissive/141578247/TESTBENCH_simple,data/full_repos/permissive/141578247/mult.sv\n             mult\n             mult.v\n             mult.sv\n             obj_dir/mult\n             obj_dir/mult.v\n             obj_dir/mult.sv\n%Error: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:820: Cannot find file containing module: \'add\'\nadd u2 (\n^~~\n%Error: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:831: Cannot find file containing module: \'sqrt\'\nsqrt u3 (\n^~~~\n%Error: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:841: Cannot find file containing module: \'div\'\ndiv u4 (\n^~~\n%Error: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:852: Cannot find file containing module: \'sub\'\nsub u5 (\n^~~\n%Error: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:863: Cannot find file containing module: \'INS_atan\'\nINS_atan u6(\n^~~~~~~~\n%Error: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:873: Cannot find file containing module: \'equl\'\nequl u7 (\n^~~~\n%Error: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_euler_tb.v:884: Cannot find file containing module: \'less\'\nless u8 (\n^~~~\n%Error: Exiting due to 8 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module INS_euler_tb;

reg clk, rst, in_euler_en;
reg [31:0] in_c11, in_c12, in_c13, in_c23, in_c33;

parameter t = 20;

initial begin
	clk = 1'b1;
	rst = 1'b1;
	in_c11 = 32'h0;
	in_c12 = 32'h0;
	in_c13 = 32'h0;
	in_c23 = 32'h0;
	in_c33 = 32'h0;
	in_euler_en = 'b0;
end

always #(t/2) clk = ~clk;

initial begin
	#(t*8)
		rst = 1'b0;
	#(t*2)
		rst = 1'b1;
	#(t*5)
		in_c11 = 32'h40000000;
		in_c12 = 32'hBF800000;
		in_c13 = 32'hBF000000;
		in_c23 = 32'hC0000000;
		in_c33 = 32'h3F800000;
	#t
		in_euler_en = 1'b1;
	#(t)
		in_euler_en = 1'b0;

end



reg [31:0] out_pitch, out_roll, out_yaw;
reg out_euler_finish;
parameter 		IDLE					=	7'd0,
               START					=	7'd1,
               EULER_1				=	7'd2,
               EULER_1_TMP			=	7'd3,
               EULER_1_1			=	7'd4,

               EULER_2_0			=	7'd6,

               EULER_2			   =	7'd8,
               EULER_2_TMP		   =	7'd9,
               EULER_2_1		   =	7'd10,

               EULER_3_0		   =	7'd12,

               EULER_3			   =	7'd14,
               EULER_3_TMP		   =	7'd15,
               EULER_3_1		   =	7'd16,

               EULER_4_0		   =	7'd18,

               EULER_4           =	7'd20,
               EULER_4_TMP	   	=	7'd21,
               EULER_4_1		   =	7'd22,

               EULER_5_0		   =	7'd24,

               EULER_5        	=	7'd26,
               EULER_5_TMP	   	=	7'd27,
               EULER_5_1		   =	7'd28,

               EULER_6_0		   =	7'd30,

               EULER_6        	=	7'd32,
               EULER_6_TMP	   	=	7'd33,
               EULER_6_1		   =	7'd34,

					EULER_7_0			=	7'd36,

					EULER_7        	=	7'd38,
					EULER_7_TMP    	=	7'd39,
					EULER_7_1			=	7'd40,

					EULER_8_0		   =	7'd42,

					EULER_8        	=	7'd44,
					EULER_8_TMP	   	=	7'd45,
					EULER_8_1		   =	7'd46,

					EULER_9_0		   =	7'd48,

					EULER_9        	=	7'd50,
					EULER_9_TMP	   	=	7'd51,
					EULER_9_1		   =	7'd52,

					EULER_10_0		   =	7'd54,

					EULER_10       	=	7'd56,
					EULER_10_TMP   	=	7'd57,
					EULER_10_1		   =	7'd58,

					EULER_11_0			=	7'd60,

					EULER_11       	=	7'd62,
					EULER_11_TMP   	=	7'd63,
					EULER_11_1		   =	7'd64,

					EULER_12_0		   =	7'd66,

					EULER_12       	=	7'd68,
					EULER_12_TMP   	=	7'd69,
					EULER_12_1			=	7'd70,

					EULER_13_0		   =	7'd72,

					EULER_13       	=	7'd74,
					EULER_13_TMP   	=	7'd75,
					EULER_13_1		   =	7'd76,

					EULER_14_0		   =	7'd78,

					EULER_14       	=	7'd80,
					EULER_14_TMP   	=	7'd81,
					EULER_15       	=	7'd82,
					EULER_15_TMP   	=	7'd83,
					EULER_15_1		   =	7'd84,

					EULER_16_0		   =	7'd86,

					EULER_16       	=	7'd88,
					EULER_16_TMP   	=	7'd89,
					EULER_17				=	7'd90,
					EULER_17_TMP	   =	7'd91,
					EULER_17_1		   =	7'd92,

					END_0		   		=	7'd94,

					END				   =	7'd96,
					END_TMP				=	7'd97,
					FINISH				=	7'd98;
					
reg [6:0] c_state, n_state;

always @ (posedge clk or negedge rst) begin
	if(!rst) begin
			c_state <= IDLE;
		end	
		else begin
			c_state <= n_state;
	end
end

wire add_end, mult_end, sqrt_end, div_end, sub_end, equl_end, less_end, atan_end;

always @ (c_state or in_euler_en or add_end or mult_end or sqrt_end or div_end or sub_end or equl_end or less_end or atan_end) begin
	case(c_state)
		IDLE				: 	begin
									if(in_euler_en) n_state = START;
									else n_state = IDLE;
								end				
		START				:  n_state = EULER_1;
		EULER_1			:  n_state = EULER_1_TMP;			
		EULER_1_TMP		:  n_state = EULER_1_1;	
		EULER_1_1		:  n_state = EULER_2_0;

		EULER_2_0		:  begin
									if(sub_end)
										n_state = EULER_2;			
									else	
										n_state = EULER_2_0;
								end

		EULER_2			:  n_state = EULER_2_TMP;			
		EULER_2_TMP		:  n_state = EULER_2_1;
		EULER_2_1		:  n_state = EULER_3_0;

		EULER_3_0		:  begin
									if(sub_end)
										n_state = EULER_3;			
									else	
										n_state = EULER_3_0;
								end

		EULER_3			:  n_state = EULER_3_TMP;			
		EULER_3_TMP		:  n_state = EULER_3_1; 
		EULER_3_1		:  n_state = EULER_4_0;

		EULER_4_0		:  begin
									if(sqrt_end)
										n_state = EULER_4;			
									else	
										n_state = EULER_4_0;
								end

		EULER_4        :  n_state = EULER_4_TMP;	      
		EULER_4_TMP	   :  n_state = EULER_4_1;  		
		EULER_4_1		:  n_state = EULER_5_0;

		EULER_5_0		:  begin
									if(atan_end)
										n_state = EULER_5;			
									else	
										n_state = EULER_5_0;	
								end

		EULER_5        :  n_state = EULER_5_TMP;	      
		EULER_5_TMP	   :  n_state = EULER_5_1;           
		EULER_5_1		:  n_state = EULER_6_0;

		EULER_6_0		:  begin
									if(sqrt_end)
										n_state = EULER_6;			
									else	
										n_state = EULER_6_0;	
								end

		EULER_6        :  n_state = EULER_6_TMP;       
		EULER_6_TMP	   :  n_state = EULER_6_1;          
		EULER_6_1		:  n_state = EULER_7_0;

		EULER_7_0		:  begin
									if(div_end)
										n_state = EULER_7;			
									else	
										n_state = EULER_7_0;	
								end

		EULER_7        :  n_state = EULER_7_TMP;       
		EULER_7_TMP    :  n_state = EULER_7_1;           
		EULER_7_1		:  n_state = EULER_8_0;

		EULER_8_0		:  begin
									if(div_end)
										n_state = EULER_8;			
									else	
										n_state = EULER_8_0;	
								end

		EULER_8        :  n_state = EULER_8_TMP;	      
		EULER_8_TMP	   :  n_state = EULER_8_1;           
		EULER_8_1		:  n_state = EULER_9_0;

		EULER_9_0		:  begin
									if(add_end)
										n_state = EULER_9;			
									else	
										n_state = EULER_9_0;	
								end

		EULER_9        :  n_state = EULER_9_TMP;	      
		EULER_9_TMP	   :  n_state = EULER_9_1;          
		EULER_9_1		:  n_state = EULER_10_0;

		EULER_10_0		:  begin
									if(sqrt_end)
										n_state = EULER_10;			
									else	
										n_state = EULER_10_0;
								end

		EULER_10       :  n_state = EULER_10_TMP;      
		EULER_10_TMP   :  n_state = EULER_10_1;          
		EULER_10_1		:  n_state = EULER_11_0;

		EULER_11_0		:  begin
									if(sqrt_end)
										n_state = EULER_11;			
									else	
										n_state = EULER_11_0;
								end

		EULER_11       :  n_state = EULER_11_TMP;       
		EULER_11_TMP   :  n_state = EULER_11_1;          
		EULER_11_1		:  n_state = EULER_12_0;

		EULER_12_0		:  begin
									if(div_end)
										n_state = EULER_12;			
									else	
										n_state = EULER_12_0;
								end

		EULER_12       :  n_state = EULER_12_TMP;      
		EULER_12_TMP   :  n_state = EULER_12_1;          
		EULER_12_1		:  n_state = EULER_13_0;

		EULER_13_0		:  begin
									if(div_end)
										n_state = EULER_13;			
									else	
										n_state = EULER_13_0;	
								end

		EULER_13       :  n_state = EULER_13_TMP;      
		EULER_13_TMP   :  n_state = EULER_13_1;          
		EULER_13_1		:  n_state = EULER_14_0;

		EULER_14_0		:  begin
									if(atan_end)
										n_state = EULER_14;			
									else	
										n_state = EULER_14_0;
								end

		EULER_14       :  n_state = EULER_14_TMP;        
		EULER_14_TMP   :  n_state = EULER_15;         		
		EULER_15       :  n_state = EULER_15_TMP;      
		EULER_15_TMP   :  n_state = EULER_15_1;          
		EULER_15_1		:  n_state = EULER_16_0;

		EULER_16_0		:  begin
									if(add_end)
										n_state = EULER_16;			
									else	
										n_state = EULER_16_0;
								end

		EULER_16       :  n_state = EULER_16_TMP;      
		EULER_16_TMP   :  n_state = EULER_17;              
		EULER_17			:  n_state = EULER_17_TMP;
		EULER_17_TMP	:  n_state = EULER_17_1;
		EULER_17_1		:  n_state = END_0;

		END_0				:  begin
									if(mult_end)
										n_state = END;			
									else	
										n_state = END_0;	
								end							

		END				:  n_state = END_TMP;
		END_TMP			:  n_state = FINISH;
		FINISH			:  n_state = IDLE;
		default			:  n_state = IDLE;
	endcase
end

parameter ZERO	= 32'h0,
			 ONE = 32'h3F800000,
			 RAD2DEG = 32'h42652EE1,
			 PI360 = 32'h40C90FDA,
			 PI180 = 32'h40490FDA,
			 PI270 = 32'h4096CBE4,
			 PI90 = 32'h3FC90FDA,
			 PI90n = 32'hBFC90FDA;

reg sclr, ce;
reg [31:0] in_c11_tmp, in_c12_tmp, in_c13_tmp,
			  in_c23_tmp, in_c33_tmp;
reg [31:0] norm_c11_tmp, norm_c12_tmp, norm_c23_tmp, norm_c33_tmp;			  
reg [31:0] out_pitch_tmp, out_roll_tmp, out_yaw_tmp;
reg [31:0] out_pitch_deg, out_roll_deg;
reg [31:0] out_roll_main, out_yaw_main;
reg equl_c33_tmp, sign_c23_tmp, equl_c11_tmp, sign_c12_tmp, sign_yaw_tmp;
reg add_start, mult_start, sqrt_start, div_start, sub_start, equl_start, less_start, atan_start;
reg [31:0] mult_in_a, mult_in_b;
wire [31:0] mult_out;
reg [31:0] add_in_a, add_in_b;
wire [31:0] add_out;
reg [31:0] sqrt_in;
wire [31:0] sqrt_out;
reg [31:0] div_in_a, div_in_b;
wire [31:0] div_out;
reg [31:0] sub_in_a, sub_in_b;
wire [31:0] sub_out;
reg [31:0] atan_in_a, atan_in_b;
wire [31:0] atan_out;
reg [31:0] equl_in, less_in, equl_in0,less_in0;
wire equl_out, less_out;

always @ (posedge clk or negedge rst) begin
	if(!rst) begin
			in_c11_tmp <= 32'h0;
			in_c12_tmp <= 32'h0;
			in_c13_tmp <= 32'h0;
			in_c23_tmp <= 32'h0;
			in_c33_tmp <= 32'h0;
			norm_c11_tmp <= 32'h0;
			norm_c12_tmp <= 32'h0;
			norm_c23_tmp <= 32'h0;
			norm_c33_tmp <= 32'h0;	
			equl_c33_tmp <= 1'b0;
			sign_c23_tmp <= 1'b0;
			equl_c11_tmp <= 1'b0;
			sign_c12_tmp <= 1'b0;
			sign_yaw_tmp <= 1'b0;
			out_pitch_tmp <= 32'h0;
			out_roll_tmp <= 32'h0;
			out_yaw_tmp <= 32'h0;
			out_pitch_deg <= 32'h0;
			out_roll_deg <= 32'h0;
			out_roll_main <= 32'h0;
			out_yaw_main <= 32'h0;
			out_pitch <= 32'h0; 
			out_roll <= 32'h0; 
			out_yaw <= 32'h0;
			out_euler_finish <= 1'b0;
			mult_in_a <= 32'h0;
			mult_in_b <= 32'h0;
			add_in_a <= 32'h0;
			add_in_b <= 32'h0;
			div_in_a <= 32'h0;
			div_in_b <= 32'h0;
			sqrt_in <= 32'h0;
			sub_in_a <= 32'h0;
			sub_in_b <= 32'h0;
			atan_in_a <= 32'h0;
			atan_in_b <= 32'h0;
			equl_in <= 32'h0;
			less_in <= 32'h0;
			equl_in0<= 32'h0;
			less_in0<= 32'h0;
			add_start <= 1'b0;
			mult_start <= 1'b0;
			sqrt_start <= 1'b0;
			div_start <= 1'b0;
			sub_start <= 1'b0;
			equl_start <= 1'b0;
			less_start <= 1'b0;
			atan_start <= 1'b0;
			sclr <= 1'b1;
			ce <= 1'b0;
		end
	else begin
			case(c_state)
				IDLE			:	begin
										if(in_euler_en) begin
												in_c11_tmp <= in_c11;
												in_c12_tmp <= in_c12;
												in_c13_tmp <= in_c13;
												in_c23_tmp <= in_c23;
												in_c33_tmp <= in_c33;
												mult_in_a <= 32'h0;
												mult_in_b <= 32'h0;
												add_in_a <= 32'h0;
												add_in_b <= 32'h0;
												div_in_a <= 32'h0;
												div_in_b <= 32'h0;
												sqrt_in <= 32'h0;
												sub_in_a <= 32'h0;
												sub_in_b <= 32'h0;
												atan_in_a <= 32'h0;
												atan_in_b <= 32'h0;
												equl_in <= 32'h0;
												less_in <= 32'h0;
												equl_in0<= 32'h0;
												less_in0<= 32'h0;
												add_start <= 1'b0;
												mult_start <= 1'b0;
												sqrt_start <= 1'b0;
												div_start <= 1'b0;
												sub_start <= 1'b0;
												equl_start <= 1'b0;
												less_start <= 1'b0;
												atan_start <= 1'b0;
												out_euler_finish <= 1'b0;
												sclr <= 1'b1;
												ce <= 1'b0;
											end
											else begin											
												mult_in_a <= 32'h0;
												mult_in_b <= 32'h0;
												add_in_a <= 32'h0;
												add_in_b <= 32'h0;
												div_in_a <= 32'h0;
												div_in_b <= 32'h0;
												sqrt_in <= 32'h0;
												sub_in_a <= 32'h0;
												sub_in_b <= 32'h0;
												atan_in_a <= 32'h0;
												atan_in_b <= 32'h0;
												equl_in <= 32'h0;
												less_in <= 32'h0;
												equl_in0<= 32'h0;
												less_in0<= 32'h0;
												add_start <= 1'b0;
												mult_start <= 1'b0;
												sqrt_start <= 1'b0;
												div_start <= 1'b0;
												sub_start <= 1'b0;
												equl_start <= 1'b0;
												less_start <= 1'b0;
												atan_start <= 1'b0;
												out_euler_finish <= out_euler_finish;
												sclr <= 1'b1;
												ce <= 1'b0;
										end
									end
				START			:	begin					

										sclr <= 1'b0;
										ce <= 1'b1;
									end
				EULER_1		:	begin					
										sub_in_a <= ZERO;
										sub_in_b <= in_c13_tmp;
										mult_in_a <= in_c13_tmp;
										mult_in_b <= in_c13_tmp;
									end
				EULER_1_1	:	begin					
										sub_start <= 1'b1;
										mult_start <= 1'b1;
									end
				EULER_2_0	:	begin					
										sub_start <= 1'b0;
										mult_start <= 1'b0;
									end
				EULER_2		:	begin					
										atan_in_b <= sub_out;
										sub_in_a <= ONE;
										sub_in_b <= mult_out;
										mult_in_a <= in_c23_tmp;
										mult_in_b <= in_c23_tmp;
									end
				EULER_2_1	:	begin					
										sub_start <= 1'b1;
										mult_start <= 1'b1;
									end
				EULER_3_0	:	begin					
										sub_start <= 1'b0;
										mult_start <= 1'b0;
									end
				EULER_3		:	begin					
										sqrt_in <= sub_out;
										add_in_a <= mult_out;
										mult_in_a <= in_c33_tmp;
										mult_in_b <= in_c33_tmp;
									end
				EULER_3_1	:	begin					
										sqrt_start <= 1'b1;
										mult_start <= 1'b1;
									end
				EULER_4_0	:	begin					
										sqrt_start <= 1'b0;
										mult_start <= 1'b0;
									end
				EULER_4		:	begin					
										atan_in_a <=sqrt_out;
										add_in_b <= mult_out;
									end
				EULER_4_1	:	begin					
										add_start <= 1'b1;
										atan_start <= 1'b1;
									end
				EULER_5_0	:	begin					
										add_start <= 1'b0;
										atan_start <= 1'b0;
									end
				EULER_5		:	begin
										out_pitch_tmp <= atan_out;
										sqrt_in <= add_out;
										mult_in_a <= in_c11_tmp;
										mult_in_b <= in_c11_tmp;
									end
				EULER_5_1	:	begin					
										sqrt_start <= 1'b1;
									end
				EULER_6_0	:	begin					
										sqrt_start  <= 1'b0;
									end
				EULER_6		:	begin
										div_in_a <= in_c23_tmp;
										div_in_b <= sqrt_out;
									end					
				EULER_6_1	:	begin					
										mult_start <= 1'b1;
										div_start <= 1'b1;
									end
				EULER_7_0	:	begin					
										mult_start <= 1'b0;
										div_start <= 1'b0;
									end
				EULER_7		:	begin										
										norm_c23_tmp <= div_out;
										add_in_a <= mult_out;
										mult_in_a <= in_c12_tmp;
										mult_in_b <= in_c12_tmp;
										div_in_a <= in_c33_tmp;
										div_in_b <= sqrt_out;
									end					
				EULER_7_1	:	begin					
										mult_start <= 1'b1;
										div_start <= 1'b1;
									end
				EULER_8_0	:	begin					
										mult_start <= 1'b0;
										div_start <= 1'b0;
									end
				EULER_8		:	begin					
										norm_c33_tmp <= div_out;
										add_in_b <= mult_out;
										mult_in_a <= out_pitch_tmp;
										mult_in_b <= RAD2DEG;
									end									
				EULER_8_1	:	begin					
										mult_start <= 1'b1;
										add_start <= 1'b1;
									end
				EULER_9_0	:	begin					
										mult_start <= 1'b0;
										add_start <= 1'b0;
									end
				EULER_9		:	begin					
										out_pitch_deg <= mult_out;
										sqrt_in <= add_out;
										equl_in <= in_c33_tmp;
										less_in <= in_c23_tmp;
										atan_in_b <= norm_c23_tmp;
										atan_in_a <= norm_c33_tmp;
									end									
				EULER_9_1	:	begin					
										equl_start <= 1'b1;
										less_start <= 1'b1;
										sqrt_start <= 1'b1;									
									end
				EULER_10_0	:	begin					
										equl_start <= 1'b0;
										less_start <= 1'b0;
										sqrt_start <= 1'b0;									
									end
				EULER_10		:	begin	
										div_in_a <= in_c12_tmp;
										div_in_b <= sqrt_out;
										equl_c33_tmp <= equl_out;
										sign_c23_tmp <= less_out;
									end
				EULER_10_1	:	begin					
										div_start <= 1'b1;
										sqrt_start <= 1'b1;
										atan_start <= 1'b1;
									end
				EULER_11_0	:	begin					
										div_start <= 1'b0;
										sqrt_start <= 1'b0;
										atan_start <= 1'b0;
									end
				EULER_11		:	begin	
										norm_c12_tmp <= div_out;
										div_in_a <= in_c11_tmp;
										div_in_b <= sqrt_out;
										equl_in <= in_c11_tmp;
										less_in <= in_c12_tmp;
										
									end
				EULER_11_1	:	begin					
										div_start <= 1'b1;
										equl_start <= 1'b1;
										less_start <= 1'b1;
									end
				EULER_12_0	:	begin					
										div_start <= 1'b0;
										equl_start <= 1'b0;
										less_start <= 1'b0;
									end
				EULER_12		:	begin										
										norm_c11_tmp <= div_out;
										equl_c11_tmp <= equl_out;
										sign_c12_tmp <= less_out;
										div_in_a <= norm_c12_tmp;
										div_in_b <= div_out;
										atan_in_a <= div_out;
										atan_in_b <= norm_c12_tmp;
										out_roll_main <= atan_out;
									end
				EULER_12_1	:	begin					
										div_start <= 1'b1;										
  								   end
				EULER_13_0	:	begin					
										div_start <= 1'b0;									
									end
				EULER_13		:	begin					
										less_in <= div_out;
										if((equl_c33_tmp) && (sign_c23_tmp))
											out_roll_tmp <= PI90n;
										if((equl_c33_tmp) && (!sign_c23_tmp))
											out_roll_tmp <= PI90;
										else
											out_roll_tmp <= out_roll_main;	
									end
				EULER_13_1	:	begin					
										less_start <= 1'b1;
										atan_start <= 1'b1;
									end
				EULER_14_0	:	begin					
										less_start <= 1'b0;
										atan_start <= 1'b0;
									end
				EULER_14		:	begin					
										out_yaw_main <= atan_out;
										sign_yaw_tmp <= less_out;
									end
				EULER_15		:	begin										
										mult_in_a <= out_roll_tmp;
										mult_in_b <= RAD2DEG;
										add_in_a <= out_yaw_main;
										add_in_b <= PI360;
									end
				EULER_15_1	:	begin					
										mult_start <= 1'b1;
										add_start <= 1'b1;
									end
				EULER_16_0	:	begin					
										mult_start <= 1'b0;
										add_start <= 1'b0;
									end
				EULER_16		:	begin					
										out_roll_deg <= mult_out;
										if(sign_yaw_tmp)
											out_yaw_tmp <= add_out;
										else if((equl_c11_tmp) && (sign_c12_tmp))
											out_yaw_tmp <= PI270;
										else if((equl_c11_tmp) && (!sign_c12_tmp))
											out_yaw_tmp <= PI90;
										else 
											out_yaw_tmp <= out_yaw_main;		
									end				
				EULER_17		:	begin					
										mult_in_a <= out_yaw_tmp;
										mult_in_b <= RAD2DEG;
									end	
				EULER_17_1	:	begin					
										mult_start <= 1'b1;
									end
				END_0		:	begin					
										mult_start <= 1'b0;
									end				
				END			:	begin
										out_pitch <= out_pitch_deg;
										out_roll <= out_roll_deg;
										out_yaw <= mult_out;
									end
				FINISH		:	out_euler_finish <= 1'b1;
				default		:  begin
										mult_in_a <= mult_in_a;
										mult_in_b <= mult_in_b;
										mult_start <= mult_start;
										add_in_a <= add_in_a;
										add_in_b <= add_in_b;
										add_start <= add_start;
										div_in_a <= div_in_a;
										div_in_b <= div_in_b;
										div_start <= div_start;
										sqrt_in <= sqrt_in;
										sqrt_start <= sqrt_start;
										sub_in_a <= sub_in_a;
										sub_in_b <= sub_in_b;
										sub_start <= sub_start;
										atan_in_a <= atan_in_a;
										atan_in_b <= atan_in_b;
										atan_start <= atan_start;
										equl_in <= equl_in;
										equl_in0<= equl_in0;
										equl_start <= equl_start;
										less_in <= less_in;
										less_in0<= less_in0;
										less_start <= less_start;
									end
			endcase
	end
end

mult u1 (
  .a(mult_in_a),
  .b(mult_in_b),
  .operation_nd(mult_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(mult_out),
  .rdy(mult_end)
);

add u2 (
  .a(add_in_a),
  .b(add_in_b),
  .operation_nd(add_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(add_out),
  .rdy(add_end)
);

sqrt u3 (
  .a(sqrt_in),
  .operation_nd(sqrt_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(sqrt_out),
  .rdy(sqrt_end)
);

div u4 (
  .a(div_in_a),
  .b(div_in_b),
  .operation_nd(div_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(div_out),
  .rdy(div_end)
);

sub u5 (
  .a(sub_in_a),
  .b(sub_in_b),
  .operation_nd(sub_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(sub_out),
  .rdy(sub_end)
);

INS_atan u6(
	.clk(clk),
	.rst(rst),
	.en(atan_start),
	.a(atan_in_a),
	.b(atan_in_b),
	.result(atan_out),
	.atan_finish(atan_end)
);

equl u7 (
  .a(equl_in),
  .b(equl_in0),
  .operation_nd(equl_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(equl_out),
  .rdy(equl_end)
);

less u8 (
  .a(less_in),
  .b(less_in0),
  .operation_nd(less_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(less_out),
  .rdy(less_end)
);

endmodule
module INS_euler_tb;


reg clk, rst, in_euler_en;
reg [31:0] in_c11, in_c12, in_c13, in_c23, in_c33;

parameter t = 20;

initial begin
	clk = 1'b1;
	rst = 1'b1;
	in_c11 = 32'h0;
	in_c12 = 32'h0;
	in_c13 = 32'h0;
	in_c23 = 32'h0;
	in_c33 = 32'h0;
	in_euler_en = 'b0;
end

always #(t/2) clk = ~clk;

initial begin
	#(t*8)
		rst = 1'b0;
	#(t*2)
		rst = 1'b1;
	#(t*5)
		in_c11 = 32'h40000000;
		in_c12 = 32'hBF800000;
		in_c13 = 32'hBF000000;
		in_c23 = 32'hC0000000;
		in_c33 = 32'h3F800000;
	#t
		in_euler_en = 1'b1;
	#(t)
		in_euler_en = 1'b0;

end



reg [31:0] out_pitch, out_roll, out_yaw;
reg out_euler_finish;
parameter 		IDLE					=	7'd0,
               START					=	7'd1,
               EULER_1				=	7'd2,
               EULER_1_TMP			=	7'd3,
               EULER_1_1			=	7'd4,

               EULER_2_0			=	7'd6,

               EULER_2			   =	7'd8,
               EULER_2_TMP		   =	7'd9,
               EULER_2_1		   =	7'd10,

               EULER_3_0		   =	7'd12,

               EULER_3			   =	7'd14,
               EULER_3_TMP		   =	7'd15,
               EULER_3_1		   =	7'd16,

               EULER_4_0		   =	7'd18,

               EULER_4           =	7'd20,
               EULER_4_TMP	   	=	7'd21,
               EULER_4_1		   =	7'd22,

               EULER_5_0		   =	7'd24,

               EULER_5        	=	7'd26,
               EULER_5_TMP	   	=	7'd27,
               EULER_5_1		   =	7'd28,

               EULER_6_0		   =	7'd30,

               EULER_6        	=	7'd32,
               EULER_6_TMP	   	=	7'd33,
               EULER_6_1		   =	7'd34,

					EULER_7_0			=	7'd36,

					EULER_7        	=	7'd38,
					EULER_7_TMP    	=	7'd39,
					EULER_7_1			=	7'd40,

					EULER_8_0		   =	7'd42,

					EULER_8        	=	7'd44,
					EULER_8_TMP	   	=	7'd45,
					EULER_8_1		   =	7'd46,

					EULER_9_0		   =	7'd48,

					EULER_9        	=	7'd50,
					EULER_9_TMP	   	=	7'd51,
					EULER_9_1		   =	7'd52,

					EULER_10_0		   =	7'd54,

					EULER_10       	=	7'd56,
					EULER_10_TMP   	=	7'd57,
					EULER_10_1		   =	7'd58,

					EULER_11_0			=	7'd60,

					EULER_11       	=	7'd62,
					EULER_11_TMP   	=	7'd63,
					EULER_11_1		   =	7'd64,

					EULER_12_0		   =	7'd66,

					EULER_12       	=	7'd68,
					EULER_12_TMP   	=	7'd69,
					EULER_12_1			=	7'd70,

					EULER_13_0		   =	7'd72,

					EULER_13       	=	7'd74,
					EULER_13_TMP   	=	7'd75,
					EULER_13_1		   =	7'd76,

					EULER_14_0		   =	7'd78,

					EULER_14       	=	7'd80,
					EULER_14_TMP   	=	7'd81,
					EULER_15       	=	7'd82,
					EULER_15_TMP   	=	7'd83,
					EULER_15_1		   =	7'd84,

					EULER_16_0		   =	7'd86,

					EULER_16       	=	7'd88,
					EULER_16_TMP   	=	7'd89,
					EULER_17				=	7'd90,
					EULER_17_TMP	   =	7'd91,
					EULER_17_1		   =	7'd92,

					END_0		   		=	7'd94,

					END				   =	7'd96,
					END_TMP				=	7'd97,
					FINISH				=	7'd98;
					
reg [6:0] c_state, n_state;

always @ (posedge clk or negedge rst) begin
	if(!rst) begin
			c_state <= IDLE;
		end	
		else begin
			c_state <= n_state;
	end
end

wire add_end, mult_end, sqrt_end, div_end, sub_end, equl_end, less_end, atan_end;

always @ (c_state or in_euler_en or add_end or mult_end or sqrt_end or div_end or sub_end or equl_end or less_end or atan_end) begin
	case(c_state)
		IDLE				: 	begin
									if(in_euler_en) n_state = START;
									else n_state = IDLE;
								end				
		START				:  n_state = EULER_1;
		EULER_1			:  n_state = EULER_1_TMP;			
		EULER_1_TMP		:  n_state = EULER_1_1;	
		EULER_1_1		:  n_state = EULER_2_0;

		EULER_2_0		:  begin
									if(sub_end)
										n_state = EULER_2;			
									else	
										n_state = EULER_2_0;
								end

		EULER_2			:  n_state = EULER_2_TMP;			
		EULER_2_TMP		:  n_state = EULER_2_1;
		EULER_2_1		:  n_state = EULER_3_0;

		EULER_3_0		:  begin
									if(sub_end)
										n_state = EULER_3;			
									else	
										n_state = EULER_3_0;
								end

		EULER_3			:  n_state = EULER_3_TMP;			
		EULER_3_TMP		:  n_state = EULER_3_1; 
		EULER_3_1		:  n_state = EULER_4_0;

		EULER_4_0		:  begin
									if(sqrt_end)
										n_state = EULER_4;			
									else	
										n_state = EULER_4_0;
								end

		EULER_4        :  n_state = EULER_4_TMP;	      
		EULER_4_TMP	   :  n_state = EULER_4_1;  		
		EULER_4_1		:  n_state = EULER_5_0;

		EULER_5_0		:  begin
									if(atan_end)
										n_state = EULER_5;			
									else	
										n_state = EULER_5_0;	
								end

		EULER_5        :  n_state = EULER_5_TMP;	      
		EULER_5_TMP	   :  n_state = EULER_5_1;           
		EULER_5_1		:  n_state = EULER_6_0;

		EULER_6_0		:  begin
									if(sqrt_end)
										n_state = EULER_6;			
									else	
										n_state = EULER_6_0;	
								end

		EULER_6        :  n_state = EULER_6_TMP;       
		EULER_6_TMP	   :  n_state = EULER_6_1;          
		EULER_6_1		:  n_state = EULER_7_0;

		EULER_7_0		:  begin
									if(div_end)
										n_state = EULER_7;			
									else	
										n_state = EULER_7_0;	
								end

		EULER_7        :  n_state = EULER_7_TMP;       
		EULER_7_TMP    :  n_state = EULER_7_1;           
		EULER_7_1		:  n_state = EULER_8_0;

		EULER_8_0		:  begin
									if(div_end)
										n_state = EULER_8;			
									else	
										n_state = EULER_8_0;	
								end

		EULER_8        :  n_state = EULER_8_TMP;	      
		EULER_8_TMP	   :  n_state = EULER_8_1;           
		EULER_8_1		:  n_state = EULER_9_0;

		EULER_9_0		:  begin
									if(add_end)
										n_state = EULER_9;			
									else	
										n_state = EULER_9_0;	
								end

		EULER_9        :  n_state = EULER_9_TMP;	      
		EULER_9_TMP	   :  n_state = EULER_9_1;          
		EULER_9_1		:  n_state = EULER_10_0;

		EULER_10_0		:  begin
									if(sqrt_end)
										n_state = EULER_10;			
									else	
										n_state = EULER_10_0;
								end

		EULER_10       :  n_state = EULER_10_TMP;      
		EULER_10_TMP   :  n_state = EULER_10_1;          
		EULER_10_1		:  n_state = EULER_11_0;

		EULER_11_0		:  begin
									if(sqrt_end)
										n_state = EULER_11;			
									else	
										n_state = EULER_11_0;
								end

		EULER_11       :  n_state = EULER_11_TMP;       
		EULER_11_TMP   :  n_state = EULER_11_1;          
		EULER_11_1		:  n_state = EULER_12_0;

		EULER_12_0		:  begin
									if(div_end)
										n_state = EULER_12;			
									else	
										n_state = EULER_12_0;
								end

		EULER_12       :  n_state = EULER_12_TMP;      
		EULER_12_TMP   :  n_state = EULER_12_1;          
		EULER_12_1		:  n_state = EULER_13_0;

		EULER_13_0		:  begin
									if(div_end)
										n_state = EULER_13;			
									else	
										n_state = EULER_13_0;	
								end

		EULER_13       :  n_state = EULER_13_TMP;      
		EULER_13_TMP   :  n_state = EULER_13_1;          
		EULER_13_1		:  n_state = EULER_14_0;

		EULER_14_0		:  begin
									if(atan_end)
										n_state = EULER_14;			
									else	
										n_state = EULER_14_0;
								end

		EULER_14       :  n_state = EULER_14_TMP;        
		EULER_14_TMP   :  n_state = EULER_15;         		
		EULER_15       :  n_state = EULER_15_TMP;      
		EULER_15_TMP   :  n_state = EULER_15_1;          
		EULER_15_1		:  n_state = EULER_16_0;

		EULER_16_0		:  begin
									if(add_end)
										n_state = EULER_16;			
									else	
										n_state = EULER_16_0;
								end

		EULER_16       :  n_state = EULER_16_TMP;      
		EULER_16_TMP   :  n_state = EULER_17;              
		EULER_17			:  n_state = EULER_17_TMP;
		EULER_17_TMP	:  n_state = EULER_17_1;
		EULER_17_1		:  n_state = END_0;

		END_0				:  begin
									if(mult_end)
										n_state = END;			
									else	
										n_state = END_0;	
								end							

		END				:  n_state = END_TMP;
		END_TMP			:  n_state = FINISH;
		FINISH			:  n_state = IDLE;
		default			:  n_state = IDLE;
	endcase
end

parameter ZERO	= 32'h0,
			 ONE = 32'h3F800000,
			 RAD2DEG = 32'h42652EE1,
			 PI360 = 32'h40C90FDA,
			 PI180 = 32'h40490FDA,
			 PI270 = 32'h4096CBE4,
			 PI90 = 32'h3FC90FDA,
			 PI90n = 32'hBFC90FDA;

reg sclr, ce;
reg [31:0] in_c11_tmp, in_c12_tmp, in_c13_tmp,
			  in_c23_tmp, in_c33_tmp;
reg [31:0] norm_c11_tmp, norm_c12_tmp, norm_c23_tmp, norm_c33_tmp;			  
reg [31:0] out_pitch_tmp, out_roll_tmp, out_yaw_tmp;
reg [31:0] out_pitch_deg, out_roll_deg;
reg [31:0] out_roll_main, out_yaw_main;
reg equl_c33_tmp, sign_c23_tmp, equl_c11_tmp, sign_c12_tmp, sign_yaw_tmp;
reg add_start, mult_start, sqrt_start, div_start, sub_start, equl_start, less_start, atan_start;
reg [31:0] mult_in_a, mult_in_b;
wire [31:0] mult_out;
reg [31:0] add_in_a, add_in_b;
wire [31:0] add_out;
reg [31:0] sqrt_in;
wire [31:0] sqrt_out;
reg [31:0] div_in_a, div_in_b;
wire [31:0] div_out;
reg [31:0] sub_in_a, sub_in_b;
wire [31:0] sub_out;
reg [31:0] atan_in_a, atan_in_b;
wire [31:0] atan_out;
reg [31:0] equl_in, less_in, equl_in0,less_in0;
wire equl_out, less_out;

always @ (posedge clk or negedge rst) begin
	if(!rst) begin
			in_c11_tmp <= 32'h0;
			in_c12_tmp <= 32'h0;
			in_c13_tmp <= 32'h0;
			in_c23_tmp <= 32'h0;
			in_c33_tmp <= 32'h0;
			norm_c11_tmp <= 32'h0;
			norm_c12_tmp <= 32'h0;
			norm_c23_tmp <= 32'h0;
			norm_c33_tmp <= 32'h0;	
			equl_c33_tmp <= 1'b0;
			sign_c23_tmp <= 1'b0;
			equl_c11_tmp <= 1'b0;
			sign_c12_tmp <= 1'b0;
			sign_yaw_tmp <= 1'b0;
			out_pitch_tmp <= 32'h0;
			out_roll_tmp <= 32'h0;
			out_yaw_tmp <= 32'h0;
			out_pitch_deg <= 32'h0;
			out_roll_deg <= 32'h0;
			out_roll_main <= 32'h0;
			out_yaw_main <= 32'h0;
			out_pitch <= 32'h0; 
			out_roll <= 32'h0; 
			out_yaw <= 32'h0;
			out_euler_finish <= 1'b0;
			mult_in_a <= 32'h0;
			mult_in_b <= 32'h0;
			add_in_a <= 32'h0;
			add_in_b <= 32'h0;
			div_in_a <= 32'h0;
			div_in_b <= 32'h0;
			sqrt_in <= 32'h0;
			sub_in_a <= 32'h0;
			sub_in_b <= 32'h0;
			atan_in_a <= 32'h0;
			atan_in_b <= 32'h0;
			equl_in <= 32'h0;
			less_in <= 32'h0;
			equl_in0<= 32'h0;
			less_in0<= 32'h0;
			add_start <= 1'b0;
			mult_start <= 1'b0;
			sqrt_start <= 1'b0;
			div_start <= 1'b0;
			sub_start <= 1'b0;
			equl_start <= 1'b0;
			less_start <= 1'b0;
			atan_start <= 1'b0;
			sclr <= 1'b1;
			ce <= 1'b0;
		end
	else begin
			case(c_state)
				IDLE			:	begin
										if(in_euler_en) begin
												in_c11_tmp <= in_c11;
												in_c12_tmp <= in_c12;
												in_c13_tmp <= in_c13;
												in_c23_tmp <= in_c23;
												in_c33_tmp <= in_c33;
												mult_in_a <= 32'h0;
												mult_in_b <= 32'h0;
												add_in_a <= 32'h0;
												add_in_b <= 32'h0;
												div_in_a <= 32'h0;
												div_in_b <= 32'h0;
												sqrt_in <= 32'h0;
												sub_in_a <= 32'h0;
												sub_in_b <= 32'h0;
												atan_in_a <= 32'h0;
												atan_in_b <= 32'h0;
												equl_in <= 32'h0;
												less_in <= 32'h0;
												equl_in0<= 32'h0;
												less_in0<= 32'h0;
												add_start <= 1'b0;
												mult_start <= 1'b0;
												sqrt_start <= 1'b0;
												div_start <= 1'b0;
												sub_start <= 1'b0;
												equl_start <= 1'b0;
												less_start <= 1'b0;
												atan_start <= 1'b0;
												out_euler_finish <= 1'b0;
												sclr <= 1'b1;
												ce <= 1'b0;
											end
											else begin											
												mult_in_a <= 32'h0;
												mult_in_b <= 32'h0;
												add_in_a <= 32'h0;
												add_in_b <= 32'h0;
												div_in_a <= 32'h0;
												div_in_b <= 32'h0;
												sqrt_in <= 32'h0;
												sub_in_a <= 32'h0;
												sub_in_b <= 32'h0;
												atan_in_a <= 32'h0;
												atan_in_b <= 32'h0;
												equl_in <= 32'h0;
												less_in <= 32'h0;
												equl_in0<= 32'h0;
												less_in0<= 32'h0;
												add_start <= 1'b0;
												mult_start <= 1'b0;
												sqrt_start <= 1'b0;
												div_start <= 1'b0;
												sub_start <= 1'b0;
												equl_start <= 1'b0;
												less_start <= 1'b0;
												atan_start <= 1'b0;
												out_euler_finish <= out_euler_finish;
												sclr <= 1'b1;
												ce <= 1'b0;
										end
									end
				START			:	begin					

										sclr <= 1'b0;
										ce <= 1'b1;
									end
				EULER_1		:	begin					
										sub_in_a <= ZERO;
										sub_in_b <= in_c13_tmp;
										mult_in_a <= in_c13_tmp;
										mult_in_b <= in_c13_tmp;
									end
				EULER_1_1	:	begin					
										sub_start <= 1'b1;
										mult_start <= 1'b1;
									end
				EULER_2_0	:	begin					
										sub_start <= 1'b0;
										mult_start <= 1'b0;
									end
				EULER_2		:	begin					
										atan_in_b <= sub_out;
										sub_in_a <= ONE;
										sub_in_b <= mult_out;
										mult_in_a <= in_c23_tmp;
										mult_in_b <= in_c23_tmp;
									end
				EULER_2_1	:	begin					
										sub_start <= 1'b1;
										mult_start <= 1'b1;
									end
				EULER_3_0	:	begin					
										sub_start <= 1'b0;
										mult_start <= 1'b0;
									end
				EULER_3		:	begin					
										sqrt_in <= sub_out;
										add_in_a <= mult_out;
										mult_in_a <= in_c33_tmp;
										mult_in_b <= in_c33_tmp;
									end
				EULER_3_1	:	begin					
										sqrt_start <= 1'b1;
										mult_start <= 1'b1;
									end
				EULER_4_0	:	begin					
										sqrt_start <= 1'b0;
										mult_start <= 1'b0;
									end
				EULER_4		:	begin					
										atan_in_a <=sqrt_out;
										add_in_b <= mult_out;
									end
				EULER_4_1	:	begin					
										add_start <= 1'b1;
										atan_start <= 1'b1;
									end
				EULER_5_0	:	begin					
										add_start <= 1'b0;
										atan_start <= 1'b0;
									end
				EULER_5		:	begin
										out_pitch_tmp <= atan_out;
										sqrt_in <= add_out;
										mult_in_a <= in_c11_tmp;
										mult_in_b <= in_c11_tmp;
									end
				EULER_5_1	:	begin					
										sqrt_start <= 1'b1;
									end
				EULER_6_0	:	begin					
										sqrt_start  <= 1'b0;
									end
				EULER_6		:	begin
										div_in_a <= in_c23_tmp;
										div_in_b <= sqrt_out;
									end					
				EULER_6_1	:	begin					
										mult_start <= 1'b1;
										div_start <= 1'b1;
									end
				EULER_7_0	:	begin					
										mult_start <= 1'b0;
										div_start <= 1'b0;
									end
				EULER_7		:	begin										
										norm_c23_tmp <= div_out;
										add_in_a <= mult_out;
										mult_in_a <= in_c12_tmp;
										mult_in_b <= in_c12_tmp;
										div_in_a <= in_c33_tmp;
										div_in_b <= sqrt_out;
									end					
				EULER_7_1	:	begin					
										mult_start <= 1'b1;
										div_start <= 1'b1;
									end
				EULER_8_0	:	begin					
										mult_start <= 1'b0;
										div_start <= 1'b0;
									end
				EULER_8		:	begin					
										norm_c33_tmp <= div_out;
										add_in_b <= mult_out;
										mult_in_a <= out_pitch_tmp;
										mult_in_b <= RAD2DEG;
									end									
				EULER_8_1	:	begin					
										mult_start <= 1'b1;
										add_start <= 1'b1;
									end
				EULER_9_0	:	begin					
										mult_start <= 1'b0;
										add_start <= 1'b0;
									end
				EULER_9		:	begin					
										out_pitch_deg <= mult_out;
										sqrt_in <= add_out;
										equl_in <= in_c33_tmp;
										less_in <= in_c23_tmp;
										atan_in_b <= norm_c23_tmp;
										atan_in_a <= norm_c33_tmp;
									end									
				EULER_9_1	:	begin					
										equl_start <= 1'b1;
										less_start <= 1'b1;
										sqrt_start <= 1'b1;									
									end
				EULER_10_0	:	begin					
										equl_start <= 1'b0;
										less_start <= 1'b0;
										sqrt_start <= 1'b0;									
									end
				EULER_10		:	begin	
										div_in_a <= in_c12_tmp;
										div_in_b <= sqrt_out;
										equl_c33_tmp <= equl_out;
										sign_c23_tmp <= less_out;
									end
				EULER_10_1	:	begin					
										div_start <= 1'b1;
										sqrt_start <= 1'b1;
										atan_start <= 1'b1;
									end
				EULER_11_0	:	begin					
										div_start <= 1'b0;
										sqrt_start <= 1'b0;
										atan_start <= 1'b0;
									end
				EULER_11		:	begin	
										norm_c12_tmp <= div_out;
										div_in_a <= in_c11_tmp;
										div_in_b <= sqrt_out;
										equl_in <= in_c11_tmp;
										less_in <= in_c12_tmp;
										
									end
				EULER_11_1	:	begin					
										div_start <= 1'b1;
										equl_start <= 1'b1;
										less_start <= 1'b1;
									end
				EULER_12_0	:	begin					
										div_start <= 1'b0;
										equl_start <= 1'b0;
										less_start <= 1'b0;
									end
				EULER_12		:	begin										
										norm_c11_tmp <= div_out;
										equl_c11_tmp <= equl_out;
										sign_c12_tmp <= less_out;
										div_in_a <= norm_c12_tmp;
										div_in_b <= div_out;
										atan_in_a <= div_out;
										atan_in_b <= norm_c12_tmp;
										out_roll_main <= atan_out;
									end
				EULER_12_1	:	begin					
										div_start <= 1'b1;										
  								   end
				EULER_13_0	:	begin					
										div_start <= 1'b0;									
									end
				EULER_13		:	begin					
										less_in <= div_out;
										if((equl_c33_tmp) && (sign_c23_tmp))
											out_roll_tmp <= PI90n;
										if((equl_c33_tmp) && (!sign_c23_tmp))
											out_roll_tmp <= PI90;
										else
											out_roll_tmp <= out_roll_main;	
									end
				EULER_13_1	:	begin					
										less_start <= 1'b1;
										atan_start <= 1'b1;
									end
				EULER_14_0	:	begin					
										less_start <= 1'b0;
										atan_start <= 1'b0;
									end
				EULER_14		:	begin					
										out_yaw_main <= atan_out;
										sign_yaw_tmp <= less_out;
									end
				EULER_15		:	begin										
										mult_in_a <= out_roll_tmp;
										mult_in_b <= RAD2DEG;
										add_in_a <= out_yaw_main;
										add_in_b <= PI360;
									end
				EULER_15_1	:	begin					
										mult_start <= 1'b1;
										add_start <= 1'b1;
									end
				EULER_16_0	:	begin					
										mult_start <= 1'b0;
										add_start <= 1'b0;
									end
				EULER_16		:	begin					
										out_roll_deg <= mult_out;
										if(sign_yaw_tmp)
											out_yaw_tmp <= add_out;
										else if((equl_c11_tmp) && (sign_c12_tmp))
											out_yaw_tmp <= PI270;
										else if((equl_c11_tmp) && (!sign_c12_tmp))
											out_yaw_tmp <= PI90;
										else 
											out_yaw_tmp <= out_yaw_main;		
									end				
				EULER_17		:	begin					
										mult_in_a <= out_yaw_tmp;
										mult_in_b <= RAD2DEG;
									end	
				EULER_17_1	:	begin					
										mult_start <= 1'b1;
									end
				END_0		:	begin					
										mult_start <= 1'b0;
									end				
				END			:	begin
										out_pitch <= out_pitch_deg;
										out_roll <= out_roll_deg;
										out_yaw <= mult_out;
									end
				FINISH		:	out_euler_finish <= 1'b1;
				default		:  begin
										mult_in_a <= mult_in_a;
										mult_in_b <= mult_in_b;
										mult_start <= mult_start;
										add_in_a <= add_in_a;
										add_in_b <= add_in_b;
										add_start <= add_start;
										div_in_a <= div_in_a;
										div_in_b <= div_in_b;
										div_start <= div_start;
										sqrt_in <= sqrt_in;
										sqrt_start <= sqrt_start;
										sub_in_a <= sub_in_a;
										sub_in_b <= sub_in_b;
										sub_start <= sub_start;
										atan_in_a <= atan_in_a;
										atan_in_b <= atan_in_b;
										atan_start <= atan_start;
										equl_in <= equl_in;
										equl_in0<= equl_in0;
										equl_start <= equl_start;
										less_in <= less_in;
										less_in0<= less_in0;
										less_start <= less_start;
									end
			endcase
	end
end

mult u1 (
  .a(mult_in_a),
  .b(mult_in_b),
  .operation_nd(mult_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(mult_out),
  .rdy(mult_end)
);

add u2 (
  .a(add_in_a),
  .b(add_in_b),
  .operation_nd(add_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(add_out),
  .rdy(add_end)
);

sqrt u3 (
  .a(sqrt_in),
  .operation_nd(sqrt_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(sqrt_out),
  .rdy(sqrt_end)
);

div u4 (
  .a(div_in_a),
  .b(div_in_b),
  .operation_nd(div_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(div_out),
  .rdy(div_end)
);

sub u5 (
  .a(sub_in_a),
  .b(sub_in_b),
  .operation_nd(sub_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(sub_out),
  .rdy(sub_end)
);

INS_atan u6(
	.clk(clk),
	.rst(rst),
	.en(atan_start),
	.a(atan_in_a),
	.b(atan_in_b),
	.result(atan_out),
	.atan_finish(atan_end)
);

equl u7 (
  .a(equl_in),
  .b(equl_in0),
  .operation_nd(equl_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(equl_out),
  .rdy(equl_end)
);

less u8 (
  .a(less_in),
  .b(less_in0),
  .operation_nd(less_start),
  .clk(clk),
  .sclr(sclr),
  .ce(ce),
  .result(less_out),
  .rdy(less_end)
);

endmodule