data/full_repos/permissive/220330507/rtl/decoder.v
 line:287: before: "out_act_branch_ialu_res_ff_gt0"
1: b'%Error: data/full_repos/permissive/220330507/rtl/decoder.v:1: Cannot find include file: opcodes.v\n`include "opcodes.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220330507/rtl,data/full_repos/permissive/220330507/opcodes.v\n             data/full_repos/permissive/220330507/rtl,data/full_repos/permissive/220330507/opcodes.v.v\n             data/full_repos/permissive/220330507/rtl,data/full_repos/permissive/220330507/opcodes.v.sv\n             opcodes.v\n             opcodes.v.v\n             opcodes.v.sv\n             obj_dir/opcodes.v\n             obj_dir/opcodes.v.v\n             obj_dir/opcodes.v.sv\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:103: Define or directive not defined: \'`INSTR_NOP\'\n    assign out_instr           = (src1_stall || src2_stall) ? `INSTR_NOP : instr_ff;  \n                                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:103: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign out_instr           = (src1_stall || src2_stall) ? `INSTR_NOP : instr_ff;  \n                                                                         ^\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:118: Define or directive not defined: \'`OPCODE_U_TYPE\'\n    assign src2_reg_idx        = (opcode != `OPCODE_U_TYPE) ? src2_reg_idx_pre : res_reg_idx;\n                                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:118: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign src2_reg_idx        = (opcode != `OPCODE_U_TYPE) ? src2_reg_idx_pre : res_reg_idx;\n                                                          ^\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:245: Define or directive not defined: \'`OPCODE_S_TYPE\'\n            `OPCODE_S_TYPE,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:245: syntax error, unexpected \',\', expecting endcase\n            `OPCODE_S_TYPE,\n                          ^\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:246: Define or directive not defined: \'`OPCODE_ADD\'\n            `OPCODE_ADD,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:247: Define or directive not defined: \'`OPCODE_SUB\'\n            `OPCODE_SUB,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:248: Define or directive not defined: \'`OPCODE_MUL\'\n            `OPCODE_MUL,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:249: Define or directive not defined: \'`OPCODE_SLL\'\n            `OPCODE_SLL,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:250: Define or directive not defined: \'`OPCODE_SRL\'\n            `OPCODE_SRL,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:251: Define or directive not defined: \'`OPCODE_SRA\'\n            `OPCODE_SRA,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:252: Define or directive not defined: \'`OPCODE_AND\'\n            `OPCODE_AND,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:253: Define or directive not defined: \'`OPCODE_OR\'\n            `OPCODE_OR ,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:254: Define or directive not defined: \'`OPCODE_XOR\'\n            `OPCODE_XOR:\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:260: Define or directive not defined: \'`OPCODE_J_TYPE\'\n            `OPCODE_J_TYPE:\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:261: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            begin\n            ^~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:266: syntax error, unexpected \':\', expecting clocking\n            default:\n                   ^\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:287: Define or directive not defined: \'`OPCODE_U_TYPE\'\n        else if (opcode == `OPCODE_U_TYPE)\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:291: Define or directive not defined: \'`FUNC2_JAL\'\n                `FUNC2_JAL:\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:329: Define or directive not defined: \'`FUNC2_INC\'\n                `FUNC2_INC:\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:368: Define or directive not defined: \'`FUNC2_INCL\'\n                `FUNC2_INCL:\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:401: Define or directive not defined: \'`FUNC2_LI\'\n                `FUNC2_LI:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:439: Define or directive not defined: \'`FUNC2_LIL\'\n                `FUNC2_LIL:\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:472: Define or directive not defined: \'`FUNC2_ADDPCI\'\n                `FUNC2_ADDPCI:\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:522: Define or directive not defined: \'`OPCODE_S_TYPE\'\n        else if (opcode == `OPCODE_S_TYPE)\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:527: Define or directive not defined: \'`FUNC1_BEQ\'\n                `FUNC1_BEQ:\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:555: syntax error, unexpected \'=\', expecting IDENTIFIER\n                        cycle_in_instr_next                    = 1;\n                                                               ^\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:563: syntax error, unexpected \'=\', expecting IDENTIFIER\n                        cycle_in_instr_next                    = 0;\n                                                               ^\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:574: Define or directive not defined: \'`FUNC1_BNEQ\'\n                `FUNC1_BNEQ:\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:602: syntax error, unexpected \'=\', expecting IDENTIFIER\n                        cycle_in_instr_next                    = 1;\n                                                               ^\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:610: syntax error, unexpected \'=\', expecting IDENTIFIER\n                        cycle_in_instr_next                    = 0;\n                                                               ^\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:621: Define or directive not defined: \'`FUNC1_BGE\'\n                `FUNC1_BGE:\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:649: syntax error, unexpected \'=\', expecting IDENTIFIER\n                        cycle_in_instr_next                    = 1;\n                                                               ^\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:657: syntax error, unexpected \'=\', expecting IDENTIFIER\n                        cycle_in_instr_next                    = 0;\n                                                               ^\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:668: Define or directive not defined: \'`FUNC1_BLT\'\n                `FUNC1_BLT:\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:696: syntax error, unexpected \'=\', expecting IDENTIFIER\n                        cycle_in_instr_next                    = 1;\n                                                               ^\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:704: syntax error, unexpected \'=\', expecting IDENTIFIER\n                        cycle_in_instr_next                    = 0;\n                                                               ^\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:715: Define or directive not defined: \'`FUNC1_SH\'\n                `FUNC1_SH:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:747: Define or directive not defined: \'`FUNC1_SHO\'\n                `FUNC1_SHO:\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:785: Define or directive not defined: \'`FUNC1_SB\'\n                `FUNC1_SB:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:818: Define or directive not defined: \'`FUNC1_SBO\'\n                `FUNC1_SBO:\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:868: Define or directive not defined: \'`OPCODE_J_TYPE\'\n        else if (opcode == `OPCODE_J_TYPE)\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:873: Define or directive not defined: \'`FUNC3_JALR\'\n                `FUNC3_JALR:\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:905: Define or directive not defined: \'`FUNC3_LH\'\n                `FUNC3_LH:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:937: Define or directive not defined: \'`FUNC3_LHO\'\n                `FUNC3_LHO:\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:977: Define or directive not defined: \'`FUNC3_LB\'\n                `FUNC3_LB:\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:1009: Define or directive not defined: \'`FUNC3_LBO\'\n                `FUNC3_LBO:\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/220330507/rtl/decoder.v:1049: Define or directive not defined: \'`FUNC3_LBU\'\n                `FUNC3_LBU:\n                ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module decoder #(parameter OPCODE_WIDTH    =  4,
                           PMEM_ADDR_WIDTH = 12,
                           PMEM_WORD_WIDTH = 16,
                           IALU_WORD_WIDTH = 16,
                           REG_IDX_WIDTH   =  4,
                           PC_WIDTH        = 12)
       (
       input                         clock,
       input                         reset,
       input                         in_flush,
       input  [PMEM_WORD_WIDTH-1:0]  in_instr,
       input                         in_instr_is_bubble,
       input  [       PC_WIDTH-1:0]  in_pc,
       input  [IALU_WORD_WIDTH-1:0]  in_res_EX,
       input  [IALU_WORD_WIDTH-1:0]  in_res_MEM,
       input  [  REG_IDX_WIDTH-1:0]  in_res_reg_idx_EX,
       input  [  REG_IDX_WIDTH-1:0]  in_res_reg_idx_MEM,
       input                         in_res_valid_EX,
       input                         in_res_valid_MEM,
       input  [IALU_WORD_WIDTH-1:0]  in_src1,
       input  [IALU_WORD_WIDTH-1:0]  in_src2,
       output                        out_act_branch_ialu_res_ff_eq0,
       output                        out_act_branch_ialu_res_ff_gt0,
       output                        out_act_branch_ialu_res_ff_lt0,
       output                        out_act_ex_incr_pc_is_res,
       output                        out_act_ialu_add,
       output                        out_act_ialu_and,
       output                        out_act_ialu_mul,
       output                        out_act_ialu_neg_src2,
       output                        out_act_ialu_or,
       output                        out_act_ialu_sll,
       output                        out_act_ialu_sra,
       output                        out_act_ialu_src2_is_res,
       output                        out_act_ialu_srl,
       output                        out_act_ialu_xor,
       output                        out_act_jump_to_ialu_res,
       output                        out_act_load_dmem_byte_signed,
       output                        out_act_load_dmem_byte_unsigned,
       output                        out_act_load_dmem_word,
       output                        out_act_store_dmem_byte,
       output                        out_act_store_dmem_word,
       output                        out_act_write_res_to_reg,
       output                 [2:0]  out_cycle_in_instr,
       output [PMEM_WORD_WIDTH-1:0]  out_instr,
       output                        out_instr_is_bubble,
       output [       PC_WIDTH-1:0]  out_pc,
       output [  REG_IDX_WIDTH-1:0]  out_res_reg_idx,
       output                        out_res_valid_EX,
       output                        out_res_valid_MEM,
       output [IALU_WORD_WIDTH-1:0]  out_src1,
       output [  REG_IDX_WIDTH-1:0]  out_src1_reg_idx,
       output [IALU_WORD_WIDTH-1:0]  out_src2,
       output [  REG_IDX_WIDTH-1:0]  out_src2_reg_idx,
       output [IALU_WORD_WIDTH-1:0]  out_src3,
       output                        out_stall
       );

    localparam IMMA_WIDTH  = 4;
    localparam IMMB_WITHD  = 16;
    localparam FUNC1_WIDTH = 4;
    localparam FUNC2_WIDTH = 4;
    localparam FUNC3_WIDTH = 4;
    
    reg  [                2:0]  cycle_in_instr_next;
    reg  [                2:0]  cycle_in_instr_ff;

    reg                         flush_ff;
    wire [PMEM_WORD_WIDTH-1:0]  instr_1st_word;
    reg  [PMEM_WORD_WIDTH-1:0]  instr_ff;
    reg  [PMEM_WORD_WIDTH-1:0]  instr_ff2;
    reg                         instr_is_bubble_ff;

    reg  [PMEM_ADDR_WIDTH-1:0]  jump_offset;

    reg  [       PC_WIDTH-1:0]  pc_ff;
    reg  [       PC_WIDTH-1:0]  pc_ff2;

    reg  [IALU_WORD_WIDTH-1:0]  src1_mod;
    reg                         src1_stall;
    reg                         src1_used;
    reg  [IALU_WORD_WIDTH-1:0]  src2_mod;
    reg                         src2_stall;
    reg                         src2_used;

    

    wire [   OPCODE_WIDTH-1:0]  opcode           = instr_1st_word [OPCODE_WIDTH-1:0];
    wire [  REG_IDX_WIDTH-1:0]  res_reg_idx      = instr_1st_word [7:4];
    wire [  REG_IDX_WIDTH-1:0]  src1_reg_idx     = instr_1st_word [11:8];
    wire [  REG_IDX_WIDTH-1:0]  src2_reg_idx_pre = instr_1st_word [15:12];
    wire [  REG_IDX_WIDTH-1:0]  src2_reg_idx;
    wire [    FUNC1_WIDTH-1:0]  func1            = instr_1st_word [7:4];
    wire [    FUNC2_WIDTH-1:0]  func2            = instr_1st_word [11:8];
    wire [    FUNC3_WIDTH-1:0]  func3            = instr_1st_word [15:12];
    wire [                3:0]  immA             = instr_1st_word [15:12];
    wire [PMEM_WORD_WIDTH-1:0]  immB             = instr_ff;

    

    assign out_cycle_in_instr  = cycle_in_instr_ff; 
    assign out_instr           = (src1_stall || src2_stall) ? `INSTR_NOP : instr_ff;
    




    assign out_instr_is_bubble = (src1_stall || src2_stall || flush_ff || instr_is_bubble_ff ) ? 1 : 0;
    
    assign out_pc              = pc_ff;
    assign out_res_reg_idx     = res_reg_idx;
    assign out_src1_reg_idx    = src1_reg_idx;
    assign out_src2_reg_idx    = src2_reg_idx;
    assign out_stall           = src1_stall | src2_stall;
    

    assign src2_reg_idx        = (opcode != `OPCODE_U_TYPE) ? src2_reg_idx_pre : res_reg_idx;




    always @(posedge clock or posedge reset)
    begin
        if (!reset) begin
            cycle_in_instr_ff  <= cycle_in_instr_next;
            flush_ff           <= in_flush;
            instr_ff           <= in_instr;
            instr_ff2          <= instr_ff;
            instr_is_bubble_ff <= in_instr_is_bubble;
            pc_ff              <= in_pc;
            pc_ff2             <= pc_ff;
        end
        else begin
            cycle_in_instr_ff  <= 0;
            flush_ff           <= 0;
            instr_ff           <= 0;
            instr_ff2          <= 0;
            instr_is_bubble_ff <= 0;
            pc_ff              <= 0;
            pc_ff2             <= 0;
        end
    end


    assign instr_1st_word = (cycle_in_instr_ff == 0) ? instr_ff : instr_ff2;




    always @(*)
    begin

        if ((src1_reg_idx == in_res_reg_idx_EX) && in_res_valid_EX)
        begin
            src1_mod = in_res_EX;
            src1_stall = 0;
        end

        else if ((src1_reg_idx == in_res_reg_idx_MEM) && in_res_valid_MEM)
        begin
            src1_mod = in_res_MEM;
            src1_stall = 0;
        end

        else if ((src1_reg_idx == in_res_reg_idx_EX) && !in_res_valid_EX && in_res_valid_MEM && cycle_in_instr_ff == 0 && src1_used)
        begin
            src1_mod   = 0;
            src1_stall = 1;
        end

        else
        begin
            src1_mod = in_src1;
            src1_stall = 0;
        end
    end




    always @(*)
    begin

        if ((src2_reg_idx == in_res_reg_idx_EX) && in_res_valid_EX)
        begin
            src2_mod = in_res_EX;
            src2_stall = 0;
        end

        else if ((src2_reg_idx == in_res_reg_idx_MEM) && in_res_valid_MEM)
        begin
            src2_mod = in_res_MEM;
            src2_stall = 0;
        end

        else if ((src2_reg_idx == in_res_reg_idx_EX) && !in_res_valid_EX && in_res_valid_MEM && cycle_in_instr_ff == 0 && src2_used)
        begin
            src2_mod   = 0;
            src2_stall = 1;
        end

        else
        begin
            src2_mod = in_src2;
            src2_stall = 0;
        end
    end


    task zero_outputs;
        out_act_branch_ialu_res_ff_eq0  = 0;
        out_act_branch_ialu_res_ff_gt0  = 0;
        out_act_branch_ialu_res_ff_lt0  = 0;
        out_act_ex_incr_pc_is_res       = 0;
        out_act_ialu_add                = 0;
        out_act_ialu_and                = 0;
        out_act_ialu_mul                = 0;
        out_act_ialu_neg_src2           = 0;
        out_act_ialu_or                 = 0;
        out_act_ialu_sll                = 0; 
        out_act_ialu_sra                = 0; 
        out_act_ialu_src2_is_res        = 0;
        out_act_ialu_srl                = 0; 
        out_act_ialu_xor                = 0;
        out_act_jump_to_ialu_res        = 0;
        out_act_load_dmem_byte_signed   = 0;
        out_act_load_dmem_byte_unsigned = 0;
        out_act_load_dmem_word          = 0;
        out_act_store_dmem_byte         = 0;
        out_act_store_dmem_word         = 0;
        out_act_write_res_to_reg        = 0;
        out_res_valid_EX                = 0;
        out_res_valid_MEM               = 0;
        out_src1                        = 0;
        out_src2                        = 0;
        out_src3                        = 0;
    endtask;



    always @(*)
    begin
        case (opcode)
            `OPCODE_S_TYPE,
            `OPCODE_ADD,
            `OPCODE_SUB,
            `OPCODE_MUL,
            `OPCODE_SLL,
            `OPCODE_SRL,
            `OPCODE_SRA,
            `OPCODE_AND,
            `OPCODE_OR ,
            `OPCODE_XOR:
            begin
                src1_used = 1;
                src2_used = 1;
            end

            `OPCODE_J_TYPE:
            begin
                src1_used = 1;
                src2_used = 0;
            end

            default:
            begin
                src1_used = 0;
                src2_used = 0;
            end

        endcase
    end




    always @(*)
    begin

        if (flush_ff == 1 || src1_stall == 1 || src2_stall == 1) begin
            cycle_in_instr_next      = 0;
            zero_outputs();
        end
        

        else if (opcode == `OPCODE_U_TYPE)
        begin
            case (func2)

                `FUNC2_JAL:
                begin
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 1;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 1;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                        out_src1                               = 0;
                        out_src2                               = immB;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end
                end
                

                `FUNC2_INC:
                begin
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 1;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = immB;
                        out_src2                               = src2_mod;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end

                end


                `FUNC2_INCL:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 1;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = {{12{immA[3]}}, immA};
                        out_src2                               = src2_mod;
                        out_src3                               = 0;
                
                end
                

                `FUNC2_LI:
                begin
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 1;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = 0;
                        out_src2                               = immB;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end
                end
                

                `FUNC2_LIL:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 1;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = 0;
                        out_src2[IMMA_WIDTH-1:0]               = immA;
                        out_src2[IALU_WORD_WIDTH-1:IMMA_WIDTH] = 0;
                        out_src3                               = 0;
                end
                

                `FUNC2_ADDPCI:
                begin
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 1;
                        out_res_valid_MEM                      = 1;
                        out_src1[IALU_WORD_WIDTH-1:PC_WIDTH]   = 0;
                        out_src1[PC_WIDTH-1:0]                 = pc_ff2;
                        out_src2                               = immB;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end
                end


                default:
                begin
                        cycle_in_instr_next                    = 0;
                        zero_outputs();

                        $display("WARNING: unknown U-Type instruction with opcode %b, func2 %b at time %0t.\n", opcode, func2, $time);
                end
            endcase
        end


        else if (opcode == `OPCODE_S_TYPE)
        begin
            case (func1)
                

                `FUNC1_BEQ:
                begin

                        out_act_branch_ialu_res_ff_eq0         = 1;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                    

                    if (cycle_in_instr_ff == 0) begin
                        cycle_in_instr_next                    = 1;
                        out_act_ialu_neg_src2                  = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = src2_mod;
                        out_src3                               = 0;
                    end

                    else if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_src1                               = immB;
                        out_src2[PC_WIDTH-1:0]                 = pc_ff2;
                        out_src2[IALU_WORD_WIDTH-1:PC_WIDTH]   = 0;
                        out_src3                               = 0;
                    end

                end


                `FUNC1_BNEQ:
                begin

                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 1;
                        out_act_branch_ialu_res_ff_lt0         = 1;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                    

                    if (cycle_in_instr_ff == 0) begin
                        cycle_in_instr_next                    = 1;
                        out_act_ialu_neg_src2                  = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = src2_mod;
                        out_src3                               = 0;
                    end

                    else if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_src1                               = immB;
                        out_src2[PC_WIDTH-1:0]                 = pc_ff2;
                        out_src2[IALU_WORD_WIDTH-1:PC_WIDTH]   = 0;
                        out_src3                               = 0;
                    end

                end


                `FUNC1_BGE:
                begin

                        out_act_branch_ialu_res_ff_eq0         = 1;
                        out_act_branch_ialu_res_ff_gt0         = 1;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                    

                    if (cycle_in_instr_ff == 0) begin
                        cycle_in_instr_next                    = 1;
                        out_act_ialu_neg_src2                  = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = src2_mod;
                        out_src3                               = 0;
                    end

                    else if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_src1                               = immB;
                        out_src2[PC_WIDTH-1:0]                 = pc_ff2;
                        out_src2[IALU_WORD_WIDTH-1:PC_WIDTH]   = 0;
                        out_src3                               = 0;
                    end

                end
                

                `FUNC1_BLT:
                begin

                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 1;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                    

                    if (cycle_in_instr_ff == 0) begin
                        cycle_in_instr_next                    = 1;
                        out_act_ialu_neg_src2                  = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = src2_mod;
                        out_src3                               = 0;
                    end

                    else if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_src1                               = immB;
                        out_src2[PC_WIDTH-1:0]                 = pc_ff2;
                        out_src2[IALU_WORD_WIDTH-1:PC_WIDTH]   = 0;
                        out_src3                               = 0;
                    end

                end
                

                `FUNC1_SH:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 1;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                        out_src1                               = 0;
                        out_src2                               = src2_mod;
                        out_src3                               = src1_mod;
                end


                `FUNC1_SHO:
                begin
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 1;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                        out_src1                               = immB;
                        out_src2                               = src2_mod;
                        out_src3                               = src1_mod;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end
                end


                `FUNC1_SB:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 1;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                        out_src1                               = 0;
                        out_src2                               = src2_mod;
                        out_src3                               = src1_mod;

                end


                `FUNC1_SBO:
                begin
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 1;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                        out_src1                               = immB;
                        out_src2                               = src2_mod;
                        out_src3                               = src1_mod;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end

                end

                default:
                begin
                    cycle_in_instr_next       = 0;
                    zero_outputs();

                    $display("WARNING: unknown S-Type instruction with opcode %b, func1 %b at time %0t.\n", opcode, func1, $time);
                end
                
            endcase
        end


        else if (opcode == `OPCODE_J_TYPE)
        begin
            case (func3)
                

                `FUNC3_JALR:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 1;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 1;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                        out_src1                               = 0;
                        out_src2                               = src1_mod;
                        out_src3                               = 0;
                end


                `FUNC3_LH:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 1;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = 0;
                        out_src2                               = src1_mod;
                        out_src3                               = 0;
                end
    

                `FUNC3_LHO:
                begin
                    
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 1;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = immB;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end

                end


                `FUNC3_LB:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 1;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = 0;
                        out_src2                               = src1_mod;
                        out_src3                               = 0;
                end
                

                `FUNC3_LBO:
                begin
                    
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 1;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = immB;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end

                end


                `FUNC3_LBU:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 1;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = 0;
                        out_src2                               = src1_mod;
                        out_src3                               = 0;
                end
                

                `FUNC3_LBUO:
                begin
                    
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 1;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = immB;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end

                end


                `FUNC3_ADDPC:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 1;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = src1_mod;
                        out_src2[IALU_WORD_WIDTH-1:PC_WIDTH]   = 0;
                        out_src2[PC_WIDTH-1:0]                 = pc_ff;
                        out_src3                               = 0;
                end

                default:
                begin
                        cycle_in_instr_next                    = 0;
                        zero_outputs();
    
                        $display("WARNING: unknown J-Type instruction with opcode %b, func3 %b at time %0t.\n", opcode, func3, $time);
                end
                
            endcase
        end
    

        else if (opcode == `OPCODE_ADD) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 1;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_SUB) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 1;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 1;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_MUL) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 1;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_SLL) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 1; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_SRL) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 1; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_SRA) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 1; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_AND) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 1;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_OR) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 1;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end


        else if (opcode == `OPCODE_XOR) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 1;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_NOP) begin
            cycle_in_instr_next       = 0;
            zero_outputs();
        end
        

        else begin
            cycle_in_instr_next       = 0;
            zero_outputs();
            
            $display("WARNING: unknown R-Type instruction with opcode %b at time %0t.\n", opcode, $time);
        end
    end

endmodule
module decoder #(parameter OPCODE_WIDTH    =  4,
                           PMEM_ADDR_WIDTH = 12,
                           PMEM_WORD_WIDTH = 16,
                           IALU_WORD_WIDTH = 16,
                           REG_IDX_WIDTH   =  4,
                           PC_WIDTH        = 12)
       (
       input                         clock,
       input                         reset,
       input                         in_flush,
       input  [PMEM_WORD_WIDTH-1:0]  in_instr,
       input                         in_instr_is_bubble,
       input  [       PC_WIDTH-1:0]  in_pc,
       input  [IALU_WORD_WIDTH-1:0]  in_res_EX,
       input  [IALU_WORD_WIDTH-1:0]  in_res_MEM,
       input  [  REG_IDX_WIDTH-1:0]  in_res_reg_idx_EX,
       input  [  REG_IDX_WIDTH-1:0]  in_res_reg_idx_MEM,
       input                         in_res_valid_EX,
       input                         in_res_valid_MEM,
       input  [IALU_WORD_WIDTH-1:0]  in_src1,
       input  [IALU_WORD_WIDTH-1:0]  in_src2,
       output                        out_act_branch_ialu_res_ff_eq0,
       output                        out_act_branch_ialu_res_ff_gt0,
       output                        out_act_branch_ialu_res_ff_lt0,
       output                        out_act_ex_incr_pc_is_res,
       output                        out_act_ialu_add,
       output                        out_act_ialu_and,
       output                        out_act_ialu_mul,
       output                        out_act_ialu_neg_src2,
       output                        out_act_ialu_or,
       output                        out_act_ialu_sll,
       output                        out_act_ialu_sra,
       output                        out_act_ialu_src2_is_res,
       output                        out_act_ialu_srl,
       output                        out_act_ialu_xor,
       output                        out_act_jump_to_ialu_res,
       output                        out_act_load_dmem_byte_signed,
       output                        out_act_load_dmem_byte_unsigned,
       output                        out_act_load_dmem_word,
       output                        out_act_store_dmem_byte,
       output                        out_act_store_dmem_word,
       output                        out_act_write_res_to_reg,
       output                 [2:0]  out_cycle_in_instr,
       output [PMEM_WORD_WIDTH-1:0]  out_instr,
       output                        out_instr_is_bubble,
       output [       PC_WIDTH-1:0]  out_pc,
       output [  REG_IDX_WIDTH-1:0]  out_res_reg_idx,
       output                        out_res_valid_EX,
       output                        out_res_valid_MEM,
       output [IALU_WORD_WIDTH-1:0]  out_src1,
       output [  REG_IDX_WIDTH-1:0]  out_src1_reg_idx,
       output [IALU_WORD_WIDTH-1:0]  out_src2,
       output [  REG_IDX_WIDTH-1:0]  out_src2_reg_idx,
       output [IALU_WORD_WIDTH-1:0]  out_src3,
       output                        out_stall
       );


    localparam IMMA_WIDTH  = 4;
    localparam IMMB_WITHD  = 16;
    localparam FUNC1_WIDTH = 4;
    localparam FUNC2_WIDTH = 4;
    localparam FUNC3_WIDTH = 4;
    
    reg  [                2:0]  cycle_in_instr_next;
    reg  [                2:0]  cycle_in_instr_ff;

    reg                         flush_ff;
    wire [PMEM_WORD_WIDTH-1:0]  instr_1st_word;
    reg  [PMEM_WORD_WIDTH-1:0]  instr_ff;
    reg  [PMEM_WORD_WIDTH-1:0]  instr_ff2;
    reg                         instr_is_bubble_ff;

    reg  [PMEM_ADDR_WIDTH-1:0]  jump_offset;

    reg  [       PC_WIDTH-1:0]  pc_ff;
    reg  [       PC_WIDTH-1:0]  pc_ff2;

    reg  [IALU_WORD_WIDTH-1:0]  src1_mod;
    reg                         src1_stall;
    reg                         src1_used;
    reg  [IALU_WORD_WIDTH-1:0]  src2_mod;
    reg                         src2_stall;
    reg                         src2_used;

    

    wire [   OPCODE_WIDTH-1:0]  opcode           = instr_1st_word [OPCODE_WIDTH-1:0];
    wire [  REG_IDX_WIDTH-1:0]  res_reg_idx      = instr_1st_word [7:4];
    wire [  REG_IDX_WIDTH-1:0]  src1_reg_idx     = instr_1st_word [11:8];
    wire [  REG_IDX_WIDTH-1:0]  src2_reg_idx_pre = instr_1st_word [15:12];
    wire [  REG_IDX_WIDTH-1:0]  src2_reg_idx;
    wire [    FUNC1_WIDTH-1:0]  func1            = instr_1st_word [7:4];
    wire [    FUNC2_WIDTH-1:0]  func2            = instr_1st_word [11:8];
    wire [    FUNC3_WIDTH-1:0]  func3            = instr_1st_word [15:12];
    wire [                3:0]  immA             = instr_1st_word [15:12];
    wire [PMEM_WORD_WIDTH-1:0]  immB             = instr_ff;

    

    assign out_cycle_in_instr  = cycle_in_instr_ff; 
    assign out_instr           = (src1_stall || src2_stall) ? `INSTR_NOP : instr_ff;
    




    assign out_instr_is_bubble = (src1_stall || src2_stall || flush_ff || instr_is_bubble_ff ) ? 1 : 0;
    
    assign out_pc              = pc_ff;
    assign out_res_reg_idx     = res_reg_idx;
    assign out_src1_reg_idx    = src1_reg_idx;
    assign out_src2_reg_idx    = src2_reg_idx;
    assign out_stall           = src1_stall | src2_stall;
    

    assign src2_reg_idx        = (opcode != `OPCODE_U_TYPE) ? src2_reg_idx_pre : res_reg_idx;




    always @(posedge clock or posedge reset)
    begin
        if (!reset) begin
            cycle_in_instr_ff  <= cycle_in_instr_next;
            flush_ff           <= in_flush;
            instr_ff           <= in_instr;
            instr_ff2          <= instr_ff;
            instr_is_bubble_ff <= in_instr_is_bubble;
            pc_ff              <= in_pc;
            pc_ff2             <= pc_ff;
        end
        else begin
            cycle_in_instr_ff  <= 0;
            flush_ff           <= 0;
            instr_ff           <= 0;
            instr_ff2          <= 0;
            instr_is_bubble_ff <= 0;
            pc_ff              <= 0;
            pc_ff2             <= 0;
        end
    end


    assign instr_1st_word = (cycle_in_instr_ff == 0) ? instr_ff : instr_ff2;




    always @(*)
    begin

        if ((src1_reg_idx == in_res_reg_idx_EX) && in_res_valid_EX)
        begin
            src1_mod = in_res_EX;
            src1_stall = 0;
        end

        else if ((src1_reg_idx == in_res_reg_idx_MEM) && in_res_valid_MEM)
        begin
            src1_mod = in_res_MEM;
            src1_stall = 0;
        end

        else if ((src1_reg_idx == in_res_reg_idx_EX) && !in_res_valid_EX && in_res_valid_MEM && cycle_in_instr_ff == 0 && src1_used)
        begin
            src1_mod   = 0;
            src1_stall = 1;
        end

        else
        begin
            src1_mod = in_src1;
            src1_stall = 0;
        end
    end




    always @(*)
    begin

        if ((src2_reg_idx == in_res_reg_idx_EX) && in_res_valid_EX)
        begin
            src2_mod = in_res_EX;
            src2_stall = 0;
        end

        else if ((src2_reg_idx == in_res_reg_idx_MEM) && in_res_valid_MEM)
        begin
            src2_mod = in_res_MEM;
            src2_stall = 0;
        end

        else if ((src2_reg_idx == in_res_reg_idx_EX) && !in_res_valid_EX && in_res_valid_MEM && cycle_in_instr_ff == 0 && src2_used)
        begin
            src2_mod   = 0;
            src2_stall = 1;
        end

        else
        begin
            src2_mod = in_src2;
            src2_stall = 0;
        end
    end


    task zero_outputs;
        out_act_branch_ialu_res_ff_eq0  = 0;
        out_act_branch_ialu_res_ff_gt0  = 0;
        out_act_branch_ialu_res_ff_lt0  = 0;
        out_act_ex_incr_pc_is_res       = 0;
        out_act_ialu_add                = 0;
        out_act_ialu_and                = 0;
        out_act_ialu_mul                = 0;
        out_act_ialu_neg_src2           = 0;
        out_act_ialu_or                 = 0;
        out_act_ialu_sll                = 0; 
        out_act_ialu_sra                = 0; 
        out_act_ialu_src2_is_res        = 0;
        out_act_ialu_srl                = 0; 
        out_act_ialu_xor                = 0;
        out_act_jump_to_ialu_res        = 0;
        out_act_load_dmem_byte_signed   = 0;
        out_act_load_dmem_byte_unsigned = 0;
        out_act_load_dmem_word          = 0;
        out_act_store_dmem_byte         = 0;
        out_act_store_dmem_word         = 0;
        out_act_write_res_to_reg        = 0;
        out_res_valid_EX                = 0;
        out_res_valid_MEM               = 0;
        out_src1                        = 0;
        out_src2                        = 0;
        out_src3                        = 0;
    endtask;



    always @(*)
    begin
        case (opcode)
            `OPCODE_S_TYPE,
            `OPCODE_ADD,
            `OPCODE_SUB,
            `OPCODE_MUL,
            `OPCODE_SLL,
            `OPCODE_SRL,
            `OPCODE_SRA,
            `OPCODE_AND,
            `OPCODE_OR ,
            `OPCODE_XOR:
            begin
                src1_used = 1;
                src2_used = 1;
            end

            `OPCODE_J_TYPE:
            begin
                src1_used = 1;
                src2_used = 0;
            end

            default:
            begin
                src1_used = 0;
                src2_used = 0;
            end

        endcase
    end




    always @(*)
    begin

        if (flush_ff == 1 || src1_stall == 1 || src2_stall == 1) begin
            cycle_in_instr_next      = 0;
            zero_outputs();
        end
        

        else if (opcode == `OPCODE_U_TYPE)
        begin
            case (func2)

                `FUNC2_JAL:
                begin
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 1;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 1;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                        out_src1                               = 0;
                        out_src2                               = immB;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end
                end
                

                `FUNC2_INC:
                begin
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 1;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = immB;
                        out_src2                               = src2_mod;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end

                end


                `FUNC2_INCL:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 1;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = {{12{immA[3]}}, immA};
                        out_src2                               = src2_mod;
                        out_src3                               = 0;
                
                end
                

                `FUNC2_LI:
                begin
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 1;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = 0;
                        out_src2                               = immB;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end
                end
                

                `FUNC2_LIL:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 1;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = 0;
                        out_src2[IMMA_WIDTH-1:0]               = immA;
                        out_src2[IALU_WORD_WIDTH-1:IMMA_WIDTH] = 0;
                        out_src3                               = 0;
                end
                

                `FUNC2_ADDPCI:
                begin
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 1;
                        out_res_valid_MEM                      = 1;
                        out_src1[IALU_WORD_WIDTH-1:PC_WIDTH]   = 0;
                        out_src1[PC_WIDTH-1:0]                 = pc_ff2;
                        out_src2                               = immB;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end
                end


                default:
                begin
                        cycle_in_instr_next                    = 0;
                        zero_outputs();

                        $display("WARNING: unknown U-Type instruction with opcode %b, func2 %b at time %0t.\n", opcode, func2, $time);
                end
            endcase
        end


        else if (opcode == `OPCODE_S_TYPE)
        begin
            case (func1)
                

                `FUNC1_BEQ:
                begin

                        out_act_branch_ialu_res_ff_eq0         = 1;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                    

                    if (cycle_in_instr_ff == 0) begin
                        cycle_in_instr_next                    = 1;
                        out_act_ialu_neg_src2                  = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = src2_mod;
                        out_src3                               = 0;
                    end

                    else if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_src1                               = immB;
                        out_src2[PC_WIDTH-1:0]                 = pc_ff2;
                        out_src2[IALU_WORD_WIDTH-1:PC_WIDTH]   = 0;
                        out_src3                               = 0;
                    end

                end


                `FUNC1_BNEQ:
                begin

                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 1;
                        out_act_branch_ialu_res_ff_lt0         = 1;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                    

                    if (cycle_in_instr_ff == 0) begin
                        cycle_in_instr_next                    = 1;
                        out_act_ialu_neg_src2                  = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = src2_mod;
                        out_src3                               = 0;
                    end

                    else if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_src1                               = immB;
                        out_src2[PC_WIDTH-1:0]                 = pc_ff2;
                        out_src2[IALU_WORD_WIDTH-1:PC_WIDTH]   = 0;
                        out_src3                               = 0;
                    end

                end


                `FUNC1_BGE:
                begin

                        out_act_branch_ialu_res_ff_eq0         = 1;
                        out_act_branch_ialu_res_ff_gt0         = 1;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                    

                    if (cycle_in_instr_ff == 0) begin
                        cycle_in_instr_next                    = 1;
                        out_act_ialu_neg_src2                  = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = src2_mod;
                        out_src3                               = 0;
                    end

                    else if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_src1                               = immB;
                        out_src2[PC_WIDTH-1:0]                 = pc_ff2;
                        out_src2[IALU_WORD_WIDTH-1:PC_WIDTH]   = 0;
                        out_src3                               = 0;
                    end

                end
                

                `FUNC1_BLT:
                begin

                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 1;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                    

                    if (cycle_in_instr_ff == 0) begin
                        cycle_in_instr_next                    = 1;
                        out_act_ialu_neg_src2                  = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = src2_mod;
                        out_src3                               = 0;
                    end

                    else if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_src1                               = immB;
                        out_src2[PC_WIDTH-1:0]                 = pc_ff2;
                        out_src2[IALU_WORD_WIDTH-1:PC_WIDTH]   = 0;
                        out_src3                               = 0;
                    end

                end
                

                `FUNC1_SH:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 1;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                        out_src1                               = 0;
                        out_src2                               = src2_mod;
                        out_src3                               = src1_mod;
                end


                `FUNC1_SHO:
                begin
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 1;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                        out_src1                               = immB;
                        out_src2                               = src2_mod;
                        out_src3                               = src1_mod;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end
                end


                `FUNC1_SB:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 1;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                        out_src1                               = 0;
                        out_src2                               = src2_mod;
                        out_src3                               = src1_mod;

                end


                `FUNC1_SBO:
                begin
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 1;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 0;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                        out_src1                               = immB;
                        out_src2                               = src2_mod;
                        out_src3                               = src1_mod;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end

                end

                default:
                begin
                    cycle_in_instr_next       = 0;
                    zero_outputs();

                    $display("WARNING: unknown S-Type instruction with opcode %b, func1 %b at time %0t.\n", opcode, func1, $time);
                end
                
            endcase
        end


        else if (opcode == `OPCODE_J_TYPE)
        begin
            case (func3)
                

                `FUNC3_JALR:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 1;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 1;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 0;
                        out_src1                               = 0;
                        out_src2                               = src1_mod;
                        out_src3                               = 0;
                end


                `FUNC3_LH:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 1;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = 0;
                        out_src2                               = src1_mod;
                        out_src3                               = 0;
                end
    

                `FUNC3_LHO:
                begin
                    
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 1;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = immB;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end

                end


                `FUNC3_LB:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 1;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = 0;
                        out_src2                               = src1_mod;
                        out_src3                               = 0;
                end
                

                `FUNC3_LBO:
                begin
                    
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 1;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = immB;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end

                end


                `FUNC3_LBU:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 0;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 1;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 1;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = 0;
                        out_src2                               = src1_mod;
                        out_src3                               = 0;
                end
                

                `FUNC3_LBUO:
                begin
                    
                    if (cycle_in_instr_ff == 1) begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 1;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 0;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = src1_mod;
                        out_src2                               = immB;
                        out_src3                               = 0;
                    end
                    else begin
                        cycle_in_instr_next                    = 1;
                        zero_outputs();
                    end

                end


                `FUNC3_ADDPC:
                begin
                        cycle_in_instr_next                    = 0;
                        out_act_branch_ialu_res_ff_eq0         = 0;
                        out_act_branch_ialu_res_ff_gt0         = 0;
                        out_act_branch_ialu_res_ff_lt0         = 0;
                        out_act_ex_incr_pc_is_res              = 0;
                        out_act_ialu_add                       = 1;
                        out_act_ialu_and                       = 0;
                        out_act_ialu_mul                       = 0;
                        out_act_ialu_neg_src2                  = 0;
                        out_act_ialu_or                        = 0;
                        out_act_ialu_sll                       = 0; 
                        out_act_ialu_sra                       = 0; 
                        out_act_ialu_src2_is_res               = 0;
                        out_act_ialu_srl                       = 0; 
                        out_act_ialu_xor                       = 0;
                        out_act_jump_to_ialu_res               = 0;
                        out_act_load_dmem_byte_signed          = 0;
                        out_act_load_dmem_byte_unsigned        = 0;
                        out_act_load_dmem_word                 = 0;
                        out_act_store_dmem_byte                = 0;
                        out_act_store_dmem_word                = 0;
                        out_act_write_res_to_reg               = 1;
                        out_res_valid_EX                       = 1;
                        out_res_valid_MEM                      = 1;
                        out_src1                               = src1_mod;
                        out_src2[IALU_WORD_WIDTH-1:PC_WIDTH]   = 0;
                        out_src2[PC_WIDTH-1:0]                 = pc_ff;
                        out_src3                               = 0;
                end

                default:
                begin
                        cycle_in_instr_next                    = 0;
                        zero_outputs();
    
                        $display("WARNING: unknown J-Type instruction with opcode %b, func3 %b at time %0t.\n", opcode, func3, $time);
                end
                
            endcase
        end
    

        else if (opcode == `OPCODE_ADD) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 1;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_SUB) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 1;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 1;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_MUL) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 1;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_SLL) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 1; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_SRL) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 1; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_SRA) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 1; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_AND) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 1;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_OR) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 1;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 0;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end


        else if (opcode == `OPCODE_XOR) begin
                cycle_in_instr_next                    = 0;
                out_act_branch_ialu_res_ff_eq0         = 0;
                out_act_branch_ialu_res_ff_gt0         = 0;
                out_act_branch_ialu_res_ff_lt0         = 0;
                out_act_ex_incr_pc_is_res              = 0;
                out_act_ialu_add                       = 0;
                out_act_ialu_and                       = 0;
                out_act_ialu_mul                       = 0;
                out_act_ialu_neg_src2                  = 0;
                out_act_ialu_or                        = 0;
                out_act_ialu_sll                       = 0; 
                out_act_ialu_sra                       = 0; 
                out_act_ialu_src2_is_res               = 0;
                out_act_ialu_srl                       = 0; 
                out_act_ialu_xor                       = 1;
                out_act_jump_to_ialu_res               = 0;
                out_act_load_dmem_byte_signed          = 0;
                out_act_load_dmem_byte_unsigned        = 0;
                out_act_load_dmem_word                 = 0;
                out_act_store_dmem_byte                = 0;
                out_act_store_dmem_word                = 0;
                out_act_write_res_to_reg               = 1;
                out_res_valid_EX                       = 1;
                out_res_valid_MEM                      = 1;
                out_src1                               = src1_mod;
                out_src2                               = src2_mod;
                out_src3                               = 0;
        end
        

        else if (opcode == `OPCODE_NOP) begin
            cycle_in_instr_next       = 0;
            zero_outputs();
        end
        

        else begin
            cycle_in_instr_next       = 0;
            zero_outputs();
            
            $display("WARNING: unknown R-Type instruction with opcode %b at time %0t.\n", opcode, $time);
        end
    end

endmodule