data/full_repos/permissive/178355189/bus_arbiter.v
data/verilator_xmls/3c57a1bb-0ff4-4cbd-99a3-b325ae2ff4cf.xml
module bus_arbiter(
    input clk,
    input rst,

    input data_req_0,
    input[ADDRESS_WIDTH-1:0] data_addr_0,
    output[DATA_WIDTH-1:0] data_0,
    output data_rdy_0,
    input data_req_1,
    input[ADDRESS_WIDTH-1:0] data_addr_1,
    output[DATA_WIDTH-1:0] data_1,
    output data_rdy_1,
    input data_req_2,
    input[ADDRESS_WIDTH-1:0] data_addr_2,
    output[DATA_WIDTH-1:0] data_2,
    output data_rdy_2,
    input data_req_3,
    input[ADDRESS_WIDTH-1:0] data_addr_3,
    output[DATA_WIDTH-1:0] data_3,
    output data_rdy_3,
    input data_req_4,
    input[ADDRESS_WIDTH-1:0] data_addr_4,
    output[DATA_WIDTH-1:0] data_4,
    output data_rdy_4,
    input data_req_5,
    input[ADDRESS_WIDTH-1:0] data_addr_5,
    output[DATA_WIDTH-1:0] data_5,
    output data_rdy_5,
    input data_req_6,
    input[ADDRESS_WIDTH-1:0] data_addr_6,
    output[DATA_WIDTH-1:0] data_6,
    output data_rdy_6,
    input data_req_7,
    input[ADDRESS_WIDTH-1:0] data_addr_7,
    output[DATA_WIDTH-1:0] data_7,
    output data_rdy_7,

    output[ADDRESS_WIDTH-1:0] mem_data_addr,
    input[DATA_WIDTH-1:0] mem_data
);

parameter ADDRESS_WIDTH = 8;
parameter DATA_WIDTH = 8;



reg[DATA_WIDTH-1:0] data_reg_0;
assign data_0 = data_reg_0;


reg data_rdy_reg_0;
assign data_rdy_0 = data_rdy_reg_0;


wire data_req_outstanding_0;
assign data_req_outstanding_0 = (data_req_0 & !data_rdy_reg_0);


reg data_cmpl_read_reg_0;


reg[DATA_WIDTH-1:0] data_reg_1;
assign data_1 = data_reg_1;


reg data_rdy_reg_1;
assign data_rdy_1 = data_rdy_reg_1;


wire data_req_outstanding_1;
assign data_req_outstanding_1 = (data_req_1 & !data_rdy_reg_1);


reg data_cmpl_read_reg_1;


reg[DATA_WIDTH-1:0] data_reg_2;
assign data_2 = data_reg_2;


reg data_rdy_reg_2;
assign data_rdy_2 = data_rdy_reg_2;


wire data_req_outstanding_2;
assign data_req_outstanding_2 = (data_req_2 & !data_rdy_reg_2);


reg data_cmpl_read_reg_2;


reg[DATA_WIDTH-1:0] data_reg_3;
assign data_3 = data_reg_3;


reg data_rdy_reg_3;
assign data_rdy_3 = data_rdy_reg_3;


wire data_req_outstanding_3;
assign data_req_outstanding_3 = (data_req_3 & !data_rdy_reg_3);


reg data_cmpl_read_reg_3;


reg[DATA_WIDTH-1:0] data_reg_4;
assign data_4 = data_reg_4;


reg data_rdy_reg_4;
assign data_rdy_4 = data_rdy_reg_4;


wire data_req_outstanding_4;
assign data_req_outstanding_4 = (data_req_4 & !data_rdy_reg_4);


reg data_cmpl_read_reg_4;


reg[DATA_WIDTH-1:0] data_reg_5;
assign data_5 = data_reg_5;


reg data_rdy_reg_5;
assign data_rdy_5 = data_rdy_reg_5;


wire data_req_outstanding_5;
assign data_req_outstanding_5 = (data_req_5 & !data_rdy_reg_5);


reg data_cmpl_read_reg_5;


reg[DATA_WIDTH-1:0] data_reg_6;
assign data_6 = data_reg_6;


reg data_rdy_reg_6;
assign data_rdy_6 = data_rdy_reg_6;


wire data_req_outstanding_6;
assign data_req_outstanding_6 = (data_req_6 & !data_rdy_reg_6);


reg data_cmpl_read_reg_6;


reg[DATA_WIDTH-1:0] data_reg_7;
assign data_7 = data_reg_7;


reg data_rdy_reg_7;
assign data_rdy_7 = data_rdy_reg_7;


wire data_req_outstanding_7;
assign data_req_outstanding_7 = (data_req_7 & !data_rdy_reg_7);


reg data_cmpl_read_reg_7;



assign mem_data_addr = (
    (data_req_outstanding_0 ? data_addr_0 :
    (data_req_outstanding_1 ? data_addr_1 :
    (data_req_outstanding_2 ? data_addr_2 :
    (data_req_outstanding_3 ? data_addr_3 :
    (data_req_outstanding_4 ? data_addr_4 :
    (data_req_outstanding_5 ? data_addr_5 :
    (data_req_outstanding_6 ? data_addr_6 :
    (data_req_outstanding_7 ? data_addr_7 :
    0
    )
    )
    )
    )
    )
    )
    )
    )
);


always @(posedge clk) begin
    if (rst) begin
        data_rdy_reg_0 <= 0;
        data_reg_0 <= 0;
        data_cmpl_read_reg_0 <= 0;
        data_rdy_reg_1 <= 0;
        data_reg_1 <= 0;
        data_cmpl_read_reg_1 <= 0;
        data_rdy_reg_2 <= 0;
        data_reg_2 <= 0;
        data_cmpl_read_reg_2 <= 0;
        data_rdy_reg_3 <= 0;
        data_reg_3 <= 0;
        data_cmpl_read_reg_3 <= 0;
        data_rdy_reg_4 <= 0;
        data_reg_4 <= 0;
        data_cmpl_read_reg_4 <= 0;
        data_rdy_reg_5 <= 0;
        data_reg_5 <= 0;
        data_cmpl_read_reg_5 <= 0;
        data_rdy_reg_6 <= 0;
        data_reg_6 <= 0;
        data_cmpl_read_reg_6 <= 0;
        data_rdy_reg_7 <= 0;
        data_reg_7 <= 0;
        data_cmpl_read_reg_7 <= 0;
    end else begin

        if (!data_req_0) begin
            data_rdy_reg_0 <= 0;
            data_cmpl_read_reg_0 <= 0;
        end
        if (!data_req_1) begin
            data_rdy_reg_1 <= 0;
            data_cmpl_read_reg_1 <= 0;
        end
        if (!data_req_2) begin
            data_rdy_reg_2 <= 0;
            data_cmpl_read_reg_2 <= 0;
        end
        if (!data_req_3) begin
            data_rdy_reg_3 <= 0;
            data_cmpl_read_reg_3 <= 0;
        end
        if (!data_req_4) begin
            data_rdy_reg_4 <= 0;
            data_cmpl_read_reg_4 <= 0;
        end
        if (!data_req_5) begin
            data_rdy_reg_5 <= 0;
            data_cmpl_read_reg_5 <= 0;
        end
        if (!data_req_6) begin
            data_rdy_reg_6 <= 0;
            data_cmpl_read_reg_6 <= 0;
        end
        if (!data_req_7) begin
            data_rdy_reg_7 <= 0;
            data_cmpl_read_reg_7 <= 0;
        end


        if (data_req_outstanding_0) begin
            if (data_cmpl_read_reg_0) begin
                data_reg_0 <= mem_data;
                data_rdy_reg_0 <= 1;
            end else begin
                data_cmpl_read_reg_0 <= 1;
            end
        end
            else
        if (data_req_outstanding_1) begin
            if (data_cmpl_read_reg_1) begin
                data_reg_1 <= mem_data;
                data_rdy_reg_1 <= 1;
            end else begin
                data_cmpl_read_reg_1 <= 1;
            end
        end
            else
        if (data_req_outstanding_2) begin
            if (data_cmpl_read_reg_2) begin
                data_reg_2 <= mem_data;
                data_rdy_reg_2 <= 1;
            end else begin
                data_cmpl_read_reg_2 <= 1;
            end
        end
            else
        if (data_req_outstanding_3) begin
            if (data_cmpl_read_reg_3) begin
                data_reg_3 <= mem_data;
                data_rdy_reg_3 <= 1;
            end else begin
                data_cmpl_read_reg_3 <= 1;
            end
        end
            else
        if (data_req_outstanding_4) begin
            if (data_cmpl_read_reg_4) begin
                data_reg_4 <= mem_data;
                data_rdy_reg_4 <= 1;
            end else begin
                data_cmpl_read_reg_4 <= 1;
            end
        end
            else
        if (data_req_outstanding_5) begin
            if (data_cmpl_read_reg_5) begin
                data_reg_5 <= mem_data;
                data_rdy_reg_5 <= 1;
            end else begin
                data_cmpl_read_reg_5 <= 1;
            end
        end
            else
        if (data_req_outstanding_6) begin
            if (data_cmpl_read_reg_6) begin
                data_reg_6 <= mem_data;
                data_rdy_reg_6 <= 1;
            end else begin
                data_cmpl_read_reg_6 <= 1;
            end
        end
            else
        if (data_req_outstanding_7) begin
            if (data_cmpl_read_reg_7) begin
                data_reg_7 <= mem_data;
                data_rdy_reg_7 <= 1;
            end else begin
                data_cmpl_read_reg_7 <= 1;
            end
        end
    end
end

endmodule
module bus_arbiter(
    input clk,
    input rst,

    input data_req_0,
    input[ADDRESS_WIDTH-1:0] data_addr_0,
    output[DATA_WIDTH-1:0] data_0,
    output data_rdy_0,
    input data_req_1,
    input[ADDRESS_WIDTH-1:0] data_addr_1,
    output[DATA_WIDTH-1:0] data_1,
    output data_rdy_1,
    input data_req_2,
    input[ADDRESS_WIDTH-1:0] data_addr_2,
    output[DATA_WIDTH-1:0] data_2,
    output data_rdy_2,
    input data_req_3,
    input[ADDRESS_WIDTH-1:0] data_addr_3,
    output[DATA_WIDTH-1:0] data_3,
    output data_rdy_3,
    input data_req_4,
    input[ADDRESS_WIDTH-1:0] data_addr_4,
    output[DATA_WIDTH-1:0] data_4,
    output data_rdy_4,
    input data_req_5,
    input[ADDRESS_WIDTH-1:0] data_addr_5,
    output[DATA_WIDTH-1:0] data_5,
    output data_rdy_5,
    input data_req_6,
    input[ADDRESS_WIDTH-1:0] data_addr_6,
    output[DATA_WIDTH-1:0] data_6,
    output data_rdy_6,
    input data_req_7,
    input[ADDRESS_WIDTH-1:0] data_addr_7,
    output[DATA_WIDTH-1:0] data_7,
    output data_rdy_7,

    output[ADDRESS_WIDTH-1:0] mem_data_addr,
    input[DATA_WIDTH-1:0] mem_data
);


parameter ADDRESS_WIDTH = 8;
parameter DATA_WIDTH = 8;



reg[DATA_WIDTH-1:0] data_reg_0;
assign data_0 = data_reg_0;


reg data_rdy_reg_0;
assign data_rdy_0 = data_rdy_reg_0;


wire data_req_outstanding_0;
assign data_req_outstanding_0 = (data_req_0 & !data_rdy_reg_0);


reg data_cmpl_read_reg_0;


reg[DATA_WIDTH-1:0] data_reg_1;
assign data_1 = data_reg_1;


reg data_rdy_reg_1;
assign data_rdy_1 = data_rdy_reg_1;


wire data_req_outstanding_1;
assign data_req_outstanding_1 = (data_req_1 & !data_rdy_reg_1);


reg data_cmpl_read_reg_1;


reg[DATA_WIDTH-1:0] data_reg_2;
assign data_2 = data_reg_2;


reg data_rdy_reg_2;
assign data_rdy_2 = data_rdy_reg_2;


wire data_req_outstanding_2;
assign data_req_outstanding_2 = (data_req_2 & !data_rdy_reg_2);


reg data_cmpl_read_reg_2;


reg[DATA_WIDTH-1:0] data_reg_3;
assign data_3 = data_reg_3;


reg data_rdy_reg_3;
assign data_rdy_3 = data_rdy_reg_3;


wire data_req_outstanding_3;
assign data_req_outstanding_3 = (data_req_3 & !data_rdy_reg_3);


reg data_cmpl_read_reg_3;


reg[DATA_WIDTH-1:0] data_reg_4;
assign data_4 = data_reg_4;


reg data_rdy_reg_4;
assign data_rdy_4 = data_rdy_reg_4;


wire data_req_outstanding_4;
assign data_req_outstanding_4 = (data_req_4 & !data_rdy_reg_4);


reg data_cmpl_read_reg_4;


reg[DATA_WIDTH-1:0] data_reg_5;
assign data_5 = data_reg_5;


reg data_rdy_reg_5;
assign data_rdy_5 = data_rdy_reg_5;


wire data_req_outstanding_5;
assign data_req_outstanding_5 = (data_req_5 & !data_rdy_reg_5);


reg data_cmpl_read_reg_5;


reg[DATA_WIDTH-1:0] data_reg_6;
assign data_6 = data_reg_6;


reg data_rdy_reg_6;
assign data_rdy_6 = data_rdy_reg_6;


wire data_req_outstanding_6;
assign data_req_outstanding_6 = (data_req_6 & !data_rdy_reg_6);


reg data_cmpl_read_reg_6;


reg[DATA_WIDTH-1:0] data_reg_7;
assign data_7 = data_reg_7;


reg data_rdy_reg_7;
assign data_rdy_7 = data_rdy_reg_7;


wire data_req_outstanding_7;
assign data_req_outstanding_7 = (data_req_7 & !data_rdy_reg_7);


reg data_cmpl_read_reg_7;



assign mem_data_addr = (
    (data_req_outstanding_0 ? data_addr_0 :
    (data_req_outstanding_1 ? data_addr_1 :
    (data_req_outstanding_2 ? data_addr_2 :
    (data_req_outstanding_3 ? data_addr_3 :
    (data_req_outstanding_4 ? data_addr_4 :
    (data_req_outstanding_5 ? data_addr_5 :
    (data_req_outstanding_6 ? data_addr_6 :
    (data_req_outstanding_7 ? data_addr_7 :
    0
    )
    )
    )
    )
    )
    )
    )
    )
);


always @(posedge clk) begin
    if (rst) begin
        data_rdy_reg_0 <= 0;
        data_reg_0 <= 0;
        data_cmpl_read_reg_0 <= 0;
        data_rdy_reg_1 <= 0;
        data_reg_1 <= 0;
        data_cmpl_read_reg_1 <= 0;
        data_rdy_reg_2 <= 0;
        data_reg_2 <= 0;
        data_cmpl_read_reg_2 <= 0;
        data_rdy_reg_3 <= 0;
        data_reg_3 <= 0;
        data_cmpl_read_reg_3 <= 0;
        data_rdy_reg_4 <= 0;
        data_reg_4 <= 0;
        data_cmpl_read_reg_4 <= 0;
        data_rdy_reg_5 <= 0;
        data_reg_5 <= 0;
        data_cmpl_read_reg_5 <= 0;
        data_rdy_reg_6 <= 0;
        data_reg_6 <= 0;
        data_cmpl_read_reg_6 <= 0;
        data_rdy_reg_7 <= 0;
        data_reg_7 <= 0;
        data_cmpl_read_reg_7 <= 0;
    end else begin

        if (!data_req_0) begin
            data_rdy_reg_0 <= 0;
            data_cmpl_read_reg_0 <= 0;
        end
        if (!data_req_1) begin
            data_rdy_reg_1 <= 0;
            data_cmpl_read_reg_1 <= 0;
        end
        if (!data_req_2) begin
            data_rdy_reg_2 <= 0;
            data_cmpl_read_reg_2 <= 0;
        end
        if (!data_req_3) begin
            data_rdy_reg_3 <= 0;
            data_cmpl_read_reg_3 <= 0;
        end
        if (!data_req_4) begin
            data_rdy_reg_4 <= 0;
            data_cmpl_read_reg_4 <= 0;
        end
        if (!data_req_5) begin
            data_rdy_reg_5 <= 0;
            data_cmpl_read_reg_5 <= 0;
        end
        if (!data_req_6) begin
            data_rdy_reg_6 <= 0;
            data_cmpl_read_reg_6 <= 0;
        end
        if (!data_req_7) begin
            data_rdy_reg_7 <= 0;
            data_cmpl_read_reg_7 <= 0;
        end


        if (data_req_outstanding_0) begin
            if (data_cmpl_read_reg_0) begin
                data_reg_0 <= mem_data;
                data_rdy_reg_0 <= 1;
            end else begin
                data_cmpl_read_reg_0 <= 1;
            end
        end
            else
        if (data_req_outstanding_1) begin
            if (data_cmpl_read_reg_1) begin
                data_reg_1 <= mem_data;
                data_rdy_reg_1 <= 1;
            end else begin
                data_cmpl_read_reg_1 <= 1;
            end
        end
            else
        if (data_req_outstanding_2) begin
            if (data_cmpl_read_reg_2) begin
                data_reg_2 <= mem_data;
                data_rdy_reg_2 <= 1;
            end else begin
                data_cmpl_read_reg_2 <= 1;
            end
        end
            else
        if (data_req_outstanding_3) begin
            if (data_cmpl_read_reg_3) begin
                data_reg_3 <= mem_data;
                data_rdy_reg_3 <= 1;
            end else begin
                data_cmpl_read_reg_3 <= 1;
            end
        end
            else
        if (data_req_outstanding_4) begin
            if (data_cmpl_read_reg_4) begin
                data_reg_4 <= mem_data;
                data_rdy_reg_4 <= 1;
            end else begin
                data_cmpl_read_reg_4 <= 1;
            end
        end
            else
        if (data_req_outstanding_5) begin
            if (data_cmpl_read_reg_5) begin
                data_reg_5 <= mem_data;
                data_rdy_reg_5 <= 1;
            end else begin
                data_cmpl_read_reg_5 <= 1;
            end
        end
            else
        if (data_req_outstanding_6) begin
            if (data_cmpl_read_reg_6) begin
                data_reg_6 <= mem_data;
                data_rdy_reg_6 <= 1;
            end else begin
                data_cmpl_read_reg_6 <= 1;
            end
        end
            else
        if (data_req_outstanding_7) begin
            if (data_cmpl_read_reg_7) begin
                data_reg_7 <= mem_data;
                data_rdy_reg_7 <= 1;
            end else begin
                data_cmpl_read_reg_7 <= 1;
            end
        end
    end
end

endmodule