data/full_repos/permissive/113780415/src/top_test.v
 line:1736: before: "&&"
1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(posedge clk && enable == 1'b1)\n                                   ^~\n%Error: Cannot continue\n"
module control(confirm, clk, resetn, ld_user, enable_aalu, ld_left, ld_right, stop_left, stop_right, stop_user, status,

return_to_load_left, go_to_get_user, curr_state, plot, color, xOut, yOut, opponent, enable_winner_indicator);

	input clk, resetn;

	input confirm;

	input [1:0] status;

	input return_to_load_left;

        input stop_left, stop_right, stop_user;

        input go_to_get_user;

        output reg enable_winner_indicator;

	output reg ld_user, ld_left, ld_right;

	output [5:0] curr_state;
	reg [1:0] current_opponent;	

	output reg [1:0] opponent;

	reg[5:0] current_state, next_state;

	reg enable_counter_clear, enable_counter_fill;

	output reg plot;



	reg [7:0] initialX_rock = 80;

	reg [6:0] initialY_rock = 40;

	reg [7:0] initialX_scissors = 110;

	reg [6:0] initialY_scissors = 80;

	reg [7:0] initialX_paper = 50;

	reg [6:0] initialY_paper = 80;

	output reg [2:0] color;

	output reg [7:0] xOut;

	output reg [6:0] yOut;

	output reg enable_aalu;

	wire [3:0] counter_count_fill, counter_count_clear;

	wire fill_done, clear_done;

	

	




	





	

	localparam LOAD_LEFT = 5'd0,

		   LOAD_LEFT_WAIT = 5'd1,

		   LOAD_RIGHT = 5'd2,

		   LOAD_RIGHT_WAIT = 5'd3,

		   GET_USER = 5'd4,

		   DRAW_SQUARE_ROCK = 5'd5,

		   CLEAR_SCISSORS = 5'd6,

		   DRAW_SQUARE_PAPER = 5'd7,

		   CLEAR_ROCK = 5'd8,

		   DRAW_SQUARE_SCISSORS = 5'd9,

		   CLEAR_PAPER = 5'd10,

		   COMPARE = 5'd11;

		  





	assign curr_state[5:0] = current_state[5:0];

	

	always@(*)

	begin: state_table

		case(current_state)

			LOAD_LEFT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_LEFT;

			LOAD_LEFT_WAIT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_RIGHT;

			LOAD_RIGHT : next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_RIGHT;

			LOAD_RIGHT_WAIT: next_state = ~stop_right? LOAD_RIGHT_WAIT: GET_USER;

			GET_USER: next_state = (confirm == 1'b1)? DRAW_SQUARE_ROCK: GET_USER;

			DRAW_SQUARE_ROCK: if (fill_done == 1'b1) begin

								           next_state <= CLEAR_SCISSORS;

								   end else begin

									         next_state <= DRAW_SQUARE_ROCK;

									end

			CLEAR_SCISSORS: if (stop_user == 1'b0 && fill_done == 1'b1) begin

			                          next_state <= COMPARE;

									end else if (stop_user == 1'b1 && fill_done == 1'b1) begin

								           next_state <= DRAW_SQUARE_PAPER;

								   end else begin

									         next_state <= CLEAR_SCISSORS;

									end

			

			DRAW_SQUARE_PAPER: if (fill_done == 1'b1) begin

								           next_state <= CLEAR_ROCK;

								   end else begin

									         next_state <= DRAW_SQUARE_PAPER;

									end

			

			CLEAR_ROCK: if (stop_user == 1'b0 && fill_done == 1'b1) begin

			                          next_state <= COMPARE;

									end else if (stop_user == 1'b1 && fill_done == 1'b1) begin

								           next_state <= DRAW_SQUARE_SCISSORS;

								   end else begin

									         next_state <= CLEAR_ROCK;

									end

			

			DRAW_SQUARE_SCISSORS: if (fill_done == 1'b1) begin

								           next_state <= CLEAR_PAPER;

								   end else begin

									         next_state <= DRAW_SQUARE_SCISSORS;

									end

			

			CLEAR_PAPER: if (stop_user == 1'b0 && fill_done == 1'b1) begin

			                          next_state <= COMPARE;

									end else if (stop_user == 1'b1 && fill_done == 1'b1) begin

								           next_state <= DRAW_SQUARE_ROCK;

								   end else begin

									         next_state <= CLEAR_PAPER;

									end

			COMPARE: next_state = (status == 2'b00 || status == 2'b11)? GET_USER: LOAD_LEFT;

			default: next_state = LOAD_LEFT;

		endcase

	end

	

	always @(posedge clear_done) begin

	   if (stop_user == 1'b0) begin

	        opponent <= current_opponent;

	        

	    end   

	end

	



	    

	always @(*)

	begin: enable_signals

		ld_left = 1'b0;

		ld_right = 1'b0;

		ld_user = 1'b0;

		enable_aalu = 1'b0;

		plot = 1'b0;

		enable_counter_fill = 1'b0;

		

		enable_winner_indicator = 1'b0;

		

		  

		case (current_state)

		   LOAD_LEFT: begin

			ld_left <= 1'b1;

			end

		   LOAD_RIGHT: begin

		   ld_right <= 1'b1;

		   enable_aalu <= 1'b1;

			end

	           GET_USER: begin

	           ld_user <= 1'b1;

	           end

	           DRAW_SQUARE_ROCK: begin

	                enable_counter_fill = 1'b1;

	                color = 3'b001;

	                plot = 1'b1;

	                xOut <= initialX_rock + counter_count_fill[1:0];

	                yOut <= initialY_rock + counter_count_fill[3:2];

	                current_opponent <= 2'b00;

	                end

	           CLEAR_SCISSORS: begin

	                enable_counter_fill = 1'b1;

	                color = 3'b000;

	                plot = 1'b1;

	                xOut <= initialX_scissors + counter_count_fill[1:0];

	                yOut <= initialY_scissors + counter_count_fill[3:2];

	                current_opponent <= 2'b00;

	                end

	           DRAW_SQUARE_PAPER: begin

	                enable_counter_fill = 1'b1;

	                color = 3'b001;

	                plot = 1'b1;

	                xOut <= initialX_paper + counter_count_fill[1:0];

	                yOut <= initialY_paper + counter_count_fill[3:2];

	                current_opponent <= 2'b01;

	                end

	           CLEAR_ROCK: begin

	                enable_counter_fill = 1'b1;

	                color = 3'b000;

	                plot = 1'b1;

	                xOut <= initialX_rock + counter_count_fill[1:0];

	                yOut <= initialY_rock + counter_count_fill[3:2];

	                current_opponent <= 2'b01;

	                end

	           DRAW_SQUARE_SCISSORS: begin

	                enable_counter_fill = 1'b1;

	                color = 3'b001;

	                plot = 1'b1;

	                xOut <= initialX_scissors + counter_count_fill[1:0];

	                yOut <= initialY_scissors + counter_count_fill[3:2];

	                current_opponent <= 2'b10;

	                end

	           CLEAR_PAPER: begin

	                enable_counter_fill = 1'b1;

	                color = 3'b000;

	                plot = 1'b1;

	                xOut <= initialX_paper + counter_count_fill[1:0];

	                yOut <= initialY_paper + counter_count_fill[3:2];

	                current_opponent <= 2'b10;

	                end

	           COMPARE: begin

	                enable_winner_indicator <= 1'b1;

	                end

		endcase

        end






	


	always @(posedge clk)

	begin: state_FFs

		if (resetn == 1'b0)

		    current_state <= LOAD_LEFT;
		else

		    current_state <= next_state;

	end
	

	counter4Bit drawCount(

	        .clock(clk),

	        .reset(resetn),

	        .enable(enable_counter_fill),

	        .count(counter_count_fill[3:0]),

	        .count_done(fill_done)

	        );

	        








	        

	   

endmodule
module control(confirm, clk, resetn, ld_user, enable_aalu, ld_left, ld_right, stop_left, stop_right, stop_user, status,

return_to_load_left, go_to_get_user, curr_state, plot, color, xOut, yOut, opponent, enable_winner_indicator);


	input clk, resetn;

	input confirm;

	input [1:0] status;

	input return_to_load_left;

        input stop_left, stop_right, stop_user;

        input go_to_get_user;

        output reg enable_winner_indicator;

	output reg ld_user, ld_left, ld_right;

	output [5:0] curr_state;
	reg [1:0] current_opponent;	

	output reg [1:0] opponent;

	reg[5:0] current_state, next_state;

	reg enable_counter_clear, enable_counter_fill;

	output reg plot;



	reg [7:0] initialX_rock = 80;

	reg [6:0] initialY_rock = 40;

	reg [7:0] initialX_scissors = 110;

	reg [6:0] initialY_scissors = 80;

	reg [7:0] initialX_paper = 50;

	reg [6:0] initialY_paper = 80;

	output reg [2:0] color;

	output reg [7:0] xOut;

	output reg [6:0] yOut;

	output reg enable_aalu;

	wire [3:0] counter_count_fill, counter_count_clear;

	wire fill_done, clear_done;

	

	




	





	

	localparam LOAD_LEFT = 5'd0,

		   LOAD_LEFT_WAIT = 5'd1,

		   LOAD_RIGHT = 5'd2,

		   LOAD_RIGHT_WAIT = 5'd3,

		   GET_USER = 5'd4,

		   DRAW_SQUARE_ROCK = 5'd5,

		   CLEAR_SCISSORS = 5'd6,

		   DRAW_SQUARE_PAPER = 5'd7,

		   CLEAR_ROCK = 5'd8,

		   DRAW_SQUARE_SCISSORS = 5'd9,

		   CLEAR_PAPER = 5'd10,

		   COMPARE = 5'd11;

		  





	assign curr_state[5:0] = current_state[5:0];

	

	always@(*)

	begin: state_table

		case(current_state)

			LOAD_LEFT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_LEFT;

			LOAD_LEFT_WAIT: next_state = ~stop_left? LOAD_LEFT_WAIT : LOAD_RIGHT;

			LOAD_RIGHT : next_state = ~stop_right? LOAD_RIGHT_WAIT: LOAD_RIGHT;

			LOAD_RIGHT_WAIT: next_state = ~stop_right? LOAD_RIGHT_WAIT: GET_USER;

			GET_USER: next_state = (confirm == 1'b1)? DRAW_SQUARE_ROCK: GET_USER;

			DRAW_SQUARE_ROCK: if (fill_done == 1'b1) begin

								           next_state <= CLEAR_SCISSORS;

								   end else begin

									         next_state <= DRAW_SQUARE_ROCK;

									end

			CLEAR_SCISSORS: if (stop_user == 1'b0 && fill_done == 1'b1) begin

			                          next_state <= COMPARE;

									end else if (stop_user == 1'b1 && fill_done == 1'b1) begin

								           next_state <= DRAW_SQUARE_PAPER;

								   end else begin

									         next_state <= CLEAR_SCISSORS;

									end

			

			DRAW_SQUARE_PAPER: if (fill_done == 1'b1) begin

								           next_state <= CLEAR_ROCK;

								   end else begin

									         next_state <= DRAW_SQUARE_PAPER;

									end

			

			CLEAR_ROCK: if (stop_user == 1'b0 && fill_done == 1'b1) begin

			                          next_state <= COMPARE;

									end else if (stop_user == 1'b1 && fill_done == 1'b1) begin

								           next_state <= DRAW_SQUARE_SCISSORS;

								   end else begin

									         next_state <= CLEAR_ROCK;

									end

			

			DRAW_SQUARE_SCISSORS: if (fill_done == 1'b1) begin

								           next_state <= CLEAR_PAPER;

								   end else begin

									         next_state <= DRAW_SQUARE_SCISSORS;

									end

			

			CLEAR_PAPER: if (stop_user == 1'b0 && fill_done == 1'b1) begin

			                          next_state <= COMPARE;

									end else if (stop_user == 1'b1 && fill_done == 1'b1) begin

								           next_state <= DRAW_SQUARE_ROCK;

								   end else begin

									         next_state <= CLEAR_PAPER;

									end

			COMPARE: next_state = (status == 2'b00 || status == 2'b11)? GET_USER: LOAD_LEFT;

			default: next_state = LOAD_LEFT;

		endcase

	end

	

	always @(posedge clear_done) begin

	   if (stop_user == 1'b0) begin

	        opponent <= current_opponent;

	        

	    end   

	end

	



	    

	always @(*)

	begin: enable_signals

		ld_left = 1'b0;

		ld_right = 1'b0;

		ld_user = 1'b0;

		enable_aalu = 1'b0;

		plot = 1'b0;

		enable_counter_fill = 1'b0;

		

		enable_winner_indicator = 1'b0;

		

		  

		case (current_state)

		   LOAD_LEFT: begin

			ld_left <= 1'b1;

			end

		   LOAD_RIGHT: begin

		   ld_right <= 1'b1;

		   enable_aalu <= 1'b1;

			end

	           GET_USER: begin

	           ld_user <= 1'b1;

	           end

	           DRAW_SQUARE_ROCK: begin

	                enable_counter_fill = 1'b1;

	                color = 3'b001;

	                plot = 1'b1;

	                xOut <= initialX_rock + counter_count_fill[1:0];

	                yOut <= initialY_rock + counter_count_fill[3:2];

	                current_opponent <= 2'b00;

	                end

	           CLEAR_SCISSORS: begin

	                enable_counter_fill = 1'b1;

	                color = 3'b000;

	                plot = 1'b1;

	                xOut <= initialX_scissors + counter_count_fill[1:0];

	                yOut <= initialY_scissors + counter_count_fill[3:2];

	                current_opponent <= 2'b00;

	                end

	           DRAW_SQUARE_PAPER: begin

	                enable_counter_fill = 1'b1;

	                color = 3'b001;

	                plot = 1'b1;

	                xOut <= initialX_paper + counter_count_fill[1:0];

	                yOut <= initialY_paper + counter_count_fill[3:2];

	                current_opponent <= 2'b01;

	                end

	           CLEAR_ROCK: begin

	                enable_counter_fill = 1'b1;

	                color = 3'b000;

	                plot = 1'b1;

	                xOut <= initialX_rock + counter_count_fill[1:0];

	                yOut <= initialY_rock + counter_count_fill[3:2];

	                current_opponent <= 2'b01;

	                end

	           DRAW_SQUARE_SCISSORS: begin

	                enable_counter_fill = 1'b1;

	                color = 3'b001;

	                plot = 1'b1;

	                xOut <= initialX_scissors + counter_count_fill[1:0];

	                yOut <= initialY_scissors + counter_count_fill[3:2];

	                current_opponent <= 2'b10;

	                end

	           CLEAR_PAPER: begin

	                enable_counter_fill = 1'b1;

	                color = 3'b000;

	                plot = 1'b1;

	                xOut <= initialX_paper + counter_count_fill[1:0];

	                yOut <= initialY_paper + counter_count_fill[3:2];

	                current_opponent <= 2'b10;

	                end

	           COMPARE: begin

	                enable_winner_indicator <= 1'b1;

	                end

		endcase

        end






	


	always @(posedge clk)

	begin: state_FFs

		if (resetn == 1'b0)

		    current_state <= LOAD_LEFT;
		else

		    current_state <= next_state;

	end
	

	counter4Bit drawCount(

	        .clock(clk),

	        .reset(resetn),

	        .enable(enable_counter_fill),

	        .count(counter_count_fill[3:0]),

	        .count_done(fill_done)

	        );

	        








	        

	   

endmodule