data/full_repos/permissive/129155059/proyecto-01/s2p_cond.v
 line:23: before: "~"
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/s2p_cond.v:1: Cannot find include file: s2p_reg_cond.v\n`include "s2p_reg_cond.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01,data/full_repos/permissive/129155059/s2p_reg_cond.v\n             data/full_repos/permissive/129155059/proyecto-01,data/full_repos/permissive/129155059/s2p_reg_cond.v.v\n             data/full_repos/permissive/129155059/proyecto-01,data/full_repos/permissive/129155059/s2p_reg_cond.v.sv\n             s2p_reg_cond.v\n             s2p_reg_cond.v.v\n             s2p_reg_cond.v.sv\n             obj_dir/s2p_reg_cond.v\n             obj_dir/s2p_reg_cond.v.v\n             obj_dir/s2p_reg_cond.v.sv\n%Error: data/full_repos/permissive/129155059/proyecto-01/s2p_cond.v:3: Cannot find include file: ffd_s2p_cond.v\n`include "ffd_s2p_cond.v" \n         ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module s2p_cond(    input [1:0]  IN_CLK_s2p,
                    input [3:0]  IN_LANE_s2p,
                    input [1:0]  IN_MODO_s2p,
                    input        IN_DIR_s2p,
                    input        IN_ENB_s2p,
                    input        IN_RESET_s2p,
                    output [7:0] OUT_LANE3_s2p,
                    output [7:0] OUT_LANE2_s2p,
                    output [7:0] OUT_LANE1_s2p,
                    output [7:0] OUT_LANE0_s2p
                    );





  s2p_reg_cond  reg_lane3(  .CLK    (IN_CLK_s2p[0]),
                            .ENB    (IN_ENB_s2p),
                            .S_IN   (IN_LANE_s2p[3]),
                            .RESET  (IN_RESET_s2p),
                            .Q      (OUT_LANE3_s2p),
                            .MODO   (IN_MODO_s2p),
                            .DIR    (IN_DIR_s2p)
                            );

  s2p_reg_cond  reg_lane2(  .CLK    (IN_CLK_s2p[0]),
                            .ENB    (IN_ENB_s2p),
                            .S_IN   (IN_LANE_s2p[2]),
                            .RESET  (IN_RESET_s2p),
                            .Q      (OUT_LANE2_s2p),
                            .MODO   (IN_MODO_s2p),
                            .DIR    (IN_DIR_s2p)
                            );

  s2p_reg_cond  reg_lane1(  .CLK    (IN_CLK_s2p[0]),
                            .ENB    (IN_ENB_s2p),
                            .S_IN   (IN_LANE_s2p[1]),
                            .RESET  (IN_RESET_s2p),
                            .Q      (OUT_LANE1_s2p),
                            .MODO   (IN_MODO_s2p),
                            .DIR    (IN_DIR_s2p)
                            );

  s2p_reg_cond  reg_lane0(  .CLK    (IN_CLK_s2p[0]),
                            .ENB    (IN_ENB_s2p),
                            .S_IN   (IN_LANE_s2p[0]),
                            .RESET  (IN_RESET_s2p),
                            .Q      (OUT_LANE0_s2p),
                            .MODO   (IN_MODO_s2p),
                            .DIR    (IN_DIR_s2p)
                            );





























































endmodule
module s2p_cond(    input [1:0]  IN_CLK_s2p,
                    input [3:0]  IN_LANE_s2p,
                    input [1:0]  IN_MODO_s2p,
                    input        IN_DIR_s2p,
                    input        IN_ENB_s2p,
                    input        IN_RESET_s2p,
                    output [7:0] OUT_LANE3_s2p,
                    output [7:0] OUT_LANE2_s2p,
                    output [7:0] OUT_LANE1_s2p,
                    output [7:0] OUT_LANE0_s2p
                    );






  s2p_reg_cond  reg_lane3(  .CLK    (IN_CLK_s2p[0]),
                            .ENB    (IN_ENB_s2p),
                            .S_IN   (IN_LANE_s2p[3]),
                            .RESET  (IN_RESET_s2p),
                            .Q      (OUT_LANE3_s2p),
                            .MODO   (IN_MODO_s2p),
                            .DIR    (IN_DIR_s2p)
                            );

  s2p_reg_cond  reg_lane2(  .CLK    (IN_CLK_s2p[0]),
                            .ENB    (IN_ENB_s2p),
                            .S_IN   (IN_LANE_s2p[2]),
                            .RESET  (IN_RESET_s2p),
                            .Q      (OUT_LANE2_s2p),
                            .MODO   (IN_MODO_s2p),
                            .DIR    (IN_DIR_s2p)
                            );

  s2p_reg_cond  reg_lane1(  .CLK    (IN_CLK_s2p[0]),
                            .ENB    (IN_ENB_s2p),
                            .S_IN   (IN_LANE_s2p[1]),
                            .RESET  (IN_RESET_s2p),
                            .Q      (OUT_LANE1_s2p),
                            .MODO   (IN_MODO_s2p),
                            .DIR    (IN_DIR_s2p)
                            );

  s2p_reg_cond  reg_lane0(  .CLK    (IN_CLK_s2p[0]),
                            .ENB    (IN_ENB_s2p),
                            .S_IN   (IN_LANE_s2p[0]),
                            .RESET  (IN_RESET_s2p),
                            .Q      (OUT_LANE0_s2p),
                            .MODO   (IN_MODO_s2p),
                            .DIR    (IN_DIR_s2p)
                            );





























































endmodule