data/full_repos/permissive/213507744/crc/test_bench_encoder.v
 line:17: before: "<<"
1: b'%Error: data/full_repos/permissive/213507744/crc/test_bench_encoder.v:1: Cannot find include file: encoder.v\n`include "encoder.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/213507744/crc,data/full_repos/permissive/213507744/encoder.v\n             data/full_repos/permissive/213507744/crc,data/full_repos/permissive/213507744/encoder.v.v\n             data/full_repos/permissive/213507744/crc,data/full_repos/permissive/213507744/encoder.v.sv\n             encoder.v\n             encoder.v.v\n             encoder.v.sv\n             obj_dir/encoder.v\n             obj_dir/encoder.v.v\n             obj_dir/encoder.v.sv\n%Error: data/full_repos/permissive/213507744/crc/test_bench_encoder.v:10: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/213507744/crc/test_bench_encoder.v:11: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, test_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/213507744/crc/test_bench_encoder.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/213507744/crc/test_bench_encoder.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/213507744/crc/test_bench_encoder.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/213507744/crc/test_bench_encoder.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;\n    ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module test_tb;
  reg clk = 0;
  reg  [7:0] in;
  reg  [7:0] gen;
  wire [7:0] out;
  CRCEncoder encoder(clk, in, gen, out);
  initial begin
    $dumpfile("test.vcd");
    $dumpvars(0, test_tb);
    gen = 'h19;
    in = 'b00000001;
    #1 clk = ~clk;
    #1 clk = ~clk;
    in = 'b00000010;
    #1 clk = ~clk;
    #1 clk = ~clk;
    $finish;
end
endmodule
module test_tb;

  reg clk = 0;
  reg  [7:0] in;
  reg  [7:0] gen;
  wire [7:0] out;
  CRCEncoder encoder(clk, in, gen, out);
  initial begin
    $dumpfile("test.vcd");
    $dumpvars(0, test_tb);
    gen = 'h19;
    in = 'b00000001;
    #1 clk = ~clk;
    #1 clk = ~clk;
    in = 'b00000010;
    #1 clk = ~clk;
    #1 clk = ~clk;
    $finish;
end
endmodule