data/full_repos/permissive/124803629/src/Pipeline_CPU/Pipeline_CPU_tb.v
1: b'%Error: data/full_repos/permissive/124803629/src/Pipeline_CPU/Pipeline_CPU_tb.v:56: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/124803629/src/Pipeline_CPU/Pipeline_CPU_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #13 reset <= 1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/124803629/src/Pipeline_CPU/Pipeline_CPU_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n forever #10 sysclk = ~sysclk;\n         ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module baudrate_generator(sysclk, reset, brclk, brclk16);
input sysclk,reset;
output reg brclk, brclk16;
reg [11:0] cnt;
reg [7:0] cnt16;

always @(posedge sysclk or negedge reset)
begin
	if(~reset) begin
		cnt <= 12'd0;
		cnt16 <= 8'd0;
		brclk <= 1;
		brclk16 <= 1;
	end
	else begin
		if(cnt16 == 8'd162) begin
			cnt16 <= 8'd0;
			brclk16 <= ~brclk16;
			end
		else
			cnt16 <= cnt16 + 8'd1;
		if(cnt == 12'd2603) begin
			cnt <= 12'd0;
			brclk <= ~brclk;
			end
		else
			cnt <= cnt + 12'd1;
	end
end

endmodule
module baudrate_generator(sysclk, reset, brclk, brclk16);

input sysclk,reset;
output reg brclk, brclk16;
reg [11:0] cnt;
reg [7:0] cnt16;

always @(posedge sysclk or negedge reset)
begin
	if(~reset) begin
		cnt <= 12'd0;
		cnt16 <= 8'd0;
		brclk <= 1;
		brclk16 <= 1;
	end
	else begin
		if(cnt16 == 8'd162) begin
			cnt16 <= 8'd0;
			brclk16 <= ~brclk16;
			end
		else
			cnt16 <= cnt16 + 8'd1;
		if(cnt == 12'd2603) begin
			cnt <= 12'd0;
			brclk <= ~brclk;
			end
		else
			cnt <= cnt + 12'd1;
	end
end

endmodule