data/full_repos/permissive/146618947/generate_tarea7/block_cond.v
1: b"%Error: data/full_repos/permissive/146618947/generate_tarea7/block_cond.v:20: Cannot find file containing module: 'word_cluster_cond'\n   word_cluster_cond wc_cond (\n   ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146618947/generate_tarea7,data/full_repos/permissive/146618947/word_cluster_cond\n             data/full_repos/permissive/146618947/generate_tarea7,data/full_repos/permissive/146618947/word_cluster_cond.v\n             data/full_repos/permissive/146618947/generate_tarea7,data/full_repos/permissive/146618947/word_cluster_cond.sv\n             word_cluster_cond\n             word_cluster_cond.v\n             word_cluster_cond.sv\n             obj_dir/word_cluster_cond\n             obj_dir/word_cluster_cond.v\n             obj_dir/word_cluster_cond.sv\n%Error: Exiting due to 1 error(s)\n"
module block_cond #(
                    parameter BUS_SIZE = 32,
                    parameter WORD_SIZE = 4,
                    parameter WORD_NUM = BUS_SIZE / WORD_SIZE
                    )
                    (
                     input clk,
                     input reset,
                     input [BUS_SIZE-1:0] data_in,
                     output reg error,
                     output [BUS_SIZE-1:0] data_out,
                     output [WORD_NUM-1:0] word_bus
                     );

   reg [1:0]                                   state;
   reg [WORD_SIZE-1:0]                         current_pos;



   word_cluster_cond wc_cond (
                              .clk (clk),
                              .reset (reset),
                              .data_in (data_in),
                              .data_out (data_out),
                              .word_bus (word_bus)
                              );

   always @(posedge clk) begin
      if (!reset) begin
         state <= 0;
         current_pos <= 0;
         error <= 0;
      end else begin
         case (state)
            0: begin

               if  (data_in[BUS_SIZE-1:BUS_SIZE-WORD_SIZE] == {WORD_SIZE{1'b1}}
                    && data_in[WORD_SIZE-1:0] == current_pos) begin
                  state <= 'b00;
                  current_pos <= current_pos + 1;
                  error <= 0;
               end else begin
                  current_pos <= 0;
                  state <= 'b01;
                  error <= 1;
               end
            end

           1 : begin

              if (data_in[BUS_SIZE-1:BUS_SIZE-WORD_SIZE] == {WORD_SIZE{1'b1}}
                  && data_in[WORD_SIZE-1:0] == current_pos) begin
                 state <= 'b00;
                 current_pos <= current_pos + 1;
                 error <= 0;
              end else begin
                 current_pos <= 0;
                 state <= 'b01;
                 error <= 1;
              end
           end

         endcase

      end
   end

endmodule
module block_cond #(
                    parameter BUS_SIZE = 32,
                    parameter WORD_SIZE = 4,
                    parameter WORD_NUM = BUS_SIZE / WORD_SIZE
                    )
                    (
                     input clk,
                     input reset,
                     input [BUS_SIZE-1:0] data_in,
                     output reg error,
                     output [BUS_SIZE-1:0] data_out,
                     output [WORD_NUM-1:0] word_bus
                     );


   reg [1:0]                                   state;
   reg [WORD_SIZE-1:0]                         current_pos;



   word_cluster_cond wc_cond (
                              .clk (clk),
                              .reset (reset),
                              .data_in (data_in),
                              .data_out (data_out),
                              .word_bus (word_bus)
                              );

   always @(posedge clk) begin
      if (!reset) begin
         state <= 0;
         current_pos <= 0;
         error <= 0;
      end else begin
         case (state)
            0: begin

               if  (data_in[BUS_SIZE-1:BUS_SIZE-WORD_SIZE] == {WORD_SIZE{1'b1}}
                    && data_in[WORD_SIZE-1:0] == current_pos) begin
                  state <= 'b00;
                  current_pos <= current_pos + 1;
                  error <= 0;
               end else begin
                  current_pos <= 0;
                  state <= 'b01;
                  error <= 1;
               end
            end

           1 : begin

              if (data_in[BUS_SIZE-1:BUS_SIZE-WORD_SIZE] == {WORD_SIZE{1'b1}}
                  && data_in[WORD_SIZE-1:0] == current_pos) begin
                 state <= 'b00;
                 current_pos <= current_pos + 1;
                 error <= 0;
              end else begin
                 current_pos <= 0;
                 state <= 'b01;
                 error <= 1;
              end
           end

         endcase

      end
   end

endmodule