data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v
1: b"%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:34: Cannot find file containing module: 'sm_top'\n    sm_top sm_top\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110151336/lab_11/src/board/de10_standard,data/full_repos/permissive/110151336/sm_top\n             data/full_repos/permissive/110151336/lab_11/src/board/de10_standard,data/full_repos/permissive/110151336/sm_top.v\n             data/full_repos/permissive/110151336/lab_11/src/board/de10_standard,data/full_repos/permissive/110151336/sm_top.sv\n             sm_top\n             sm_top.v\n             sm_top.sv\n             obj_dir/sm_top\n             obj_dir/sm_top.v\n             obj_dir/sm_top.sv\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:51: Cannot find file containing module: 'sm_hex_display'\n    sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:52: Cannot find file containing module: 'sm_hex_display'\n    sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:53: Cannot find file containing module: 'sm_hex_display'\n    sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:54: Cannot find file containing module: 'sm_hex_display'\n    sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:55: Cannot find file containing module: 'sm_hex_display'\n    sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_11/src/board/de10_standard/de10_standard.v:56: Cannot find file containing module: 'sm_hex_display'\n    sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module de10_standard
(
    input                       CLOCK2_50,
    input                       CLOCK3_50,
    input                       CLOCK4_50,
    input                       CLOCK_50,

    input            [3:0]      KEY,

    input            [9:0]      SW,

    output           [9:0]      LEDR,

    output           [6:0]      HEX0,
    output           [6:0]      HEX1,
    output           [6:0]      HEX2,
    output           [6:0]      HEX3,
    output           [6:0]      HEX4,
    output           [6:0]      HEX5
);


    wire          clk;
    wire          clkIn     =  CLOCK_50;
    wire          rst_n     =  KEY[0];
    wire          clkEnable =  SW [9] | ~KEY[1];
    wire [  3:0 ] clkDevide =  SW [8:5];
    wire [  4:0 ] regAddr   =  SW [4:0];
    wire [ 31:0 ] regData;


    sm_top sm_top
    (
        .clkIn      ( clkIn     ),
        .rst_n      ( rst_n     ),
        .clkDevide  ( clkDevide ),
        .clkEnable  ( clkEnable ),
        .clk        ( clk       ),
        .regAddr    ( regAddr   ),
        .regData    ( regData   )
    );


    assign LEDR[0]   = clk;
    assign LEDR[9:1] = regData[8:0];

    wire [ 31:0 ] h7segment = regData;

    sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
    sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
    sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
    sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
    sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
    sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );

endmodule
module de10_standard
(
    input                       CLOCK2_50,
    input                       CLOCK3_50,
    input                       CLOCK4_50,
    input                       CLOCK_50,

    input            [3:0]      KEY,

    input            [9:0]      SW,

    output           [9:0]      LEDR,

    output           [6:0]      HEX0,
    output           [6:0]      HEX1,
    output           [6:0]      HEX2,
    output           [6:0]      HEX3,
    output           [6:0]      HEX4,
    output           [6:0]      HEX5
);



    wire          clk;
    wire          clkIn     =  CLOCK_50;
    wire          rst_n     =  KEY[0];
    wire          clkEnable =  SW [9] | ~KEY[1];
    wire [  3:0 ] clkDevide =  SW [8:5];
    wire [  4:0 ] regAddr   =  SW [4:0];
    wire [ 31:0 ] regData;


    sm_top sm_top
    (
        .clkIn      ( clkIn     ),
        .rst_n      ( rst_n     ),
        .clkDevide  ( clkDevide ),
        .clkEnable  ( clkEnable ),
        .clk        ( clk       ),
        .regAddr    ( regAddr   ),
        .regData    ( regData   )
    );


    assign LEDR[0]   = clk;
    assign LEDR[9:1] = regData[8:0];

    wire [ 31:0 ] h7segment = regData;

    sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
    sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
    sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
    sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
    sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
    sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );

endmodule