data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:210: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg0 (\n               ^~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:216: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:222: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg2 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:228: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg3 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:234: Cell has missing pin: \'en\'\n  reg_ar_as_w18 reg4 (\n                ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:240: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg5 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:246: Cell has missing pin: \'en\'\n  reg_ar_as_w25 reg6 (\n                ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:252: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg7 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:580: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg0 (\n               ^~~~\n%Error: Exiting due to 9 warning(s)\n'
module rst_n
  (
  clk,
  rst_n
  );

  input clk;
  output rst_n;

  wire [3:0] cnt;
  wire [3:0] n1;
  wire [3:0] n2;
  wire n0;

  add_pu4_pu4_o4 add0 (
    .i0(cnt),
    .i1(4'b0001),
    .o(n1));
  eq_w4 eq0 (
    .i0(cnt),
    .i1(4'b1111),
    .o(n0));
  binary_mux_s1_w4 mux0 (
    .i0(n1),
    .i1(4'b1111),
    .sel(n0),
    .o(n2));
  reg_ar_as_w4 reg0 (
    .clk(clk),
    .d(n2),
    .reset(4'b0000),
    .set(4'b0000),
    .q(cnt));
  AL_DFF rst_n_reg (
    .clk(clk),
    .d(n0),
    .reset(1'b0),
    .set(1'b0),
    .q(rst_n));

endmodule
module rst_n
  (
  clk,
  rst_n
  );


  input clk;
  output rst_n;

  wire [3:0] cnt;
  wire [3:0] n1;
  wire [3:0] n2;
  wire n0;

  add_pu4_pu4_o4 add0 (
    .i0(cnt),
    .i1(4'b0001),
    .o(n1));
  eq_w4 eq0 (
    .i0(cnt),
    .i1(4'b1111),
    .o(n0));
  binary_mux_s1_w4 mux0 (
    .i0(n1),
    .i1(4'b1111),
    .sel(n0),
    .o(n2));
  reg_ar_as_w4 reg0 (
    .clk(clk),
    .d(n2),
    .reset(4'b0000),
    .set(4'b0000),
    .q(cnt));
  AL_DFF rst_n_reg (
    .clk(clk),
    .d(n0),
    .reset(1'b0),
    .set(1'b0),
    .q(rst_n));

endmodule