data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:186: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h6488\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b0000: angle = 18\'d25736 ;    \n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:187: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h3b58\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b0001: angle = 18\'d15192;     \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:188: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h1f5b\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b0010: angle = 18\'d8027;      \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:189: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'hfeb\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b0011: angle = 18\'d4075;      \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:190: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h7fd\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b0100: angle = 18\'d2045;      \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:191: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h400\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b0101: angle = 18\'d1024;      \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:192: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h200\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b0110: angle = 18\'d512;       \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:193: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h100\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b0111: angle = 18\'d256;       \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:194: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h80\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b1000: angle = 18\'d128;       \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:195: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h40\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b1001: angle = 18\'d64;        \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:196: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h20\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b1010: angle = 18\'d32;        \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:197: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h10\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b1011: angle = 18\'d16;        \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:198: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h8\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b1100: angle = 18\'d8;         \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:199: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h4\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b1101: angle = 18\'d4;         \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:200: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h2\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b1110: angle = 18\'d2;         \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:201: Operator ASSIGN expects 19 bits on the Assign RHS, but Assign RHS\'s CONST \'18\'h1\' generates 18 bits.\n                                                                                         : ... In instance chen_cordic\n    4\'b1111: angle = 18\'d1;         \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h6488\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[0].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h3b58\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[1].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h1f5b\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[2].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'hfeb\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[3].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h7fd\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[4].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h400\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[5].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h200\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[6].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h100\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[7].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h80\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[8].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h40\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[9].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h20\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[10].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h10\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[11].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h8\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[12].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h4\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[13].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h2\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[14].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/104443190/chen_cordic/chen_cordic_radian.v:215: Operator VAR \'angle\' expects 18 bits on the Initial value, but Initial value\'s CONST \'19\'h1\' generates 19 bits.\n                                                                                         : ... In instance chen_cordic.genblk2[15].inst_rotator\n    parameter signed [17:0] angle=0;\n                            ^~~~~\n%Error: Exiting due to 32 warning(s)\n'
module  chen_cordic #(
    
    parameter ROTATE_TYPE = "ROTATE",
    parameter DATABITS = 17,
    parameter ITERATIONS = 16

    )(

    input clk,
    input rst_n,
    
    input Validin,
    input signed [DATABITS-1:0] Xin,
    input signed [DATABITS-1:0] Yin,  
    input signed [17:0] Ain,
    
    output reg Validout,
    output reg signed [DATABITS-1:0] Xout,
    output reg signed [DATABITS-1:0] Yout,
    output reg signed [17:0] Aout
    
    );
    

    
    localparam pi = 18'sd102943;
    localparam half_pi = 18'sd51471;
    localparam K = 16'sb0100110110111010;
    

 

    reg signed [DATABITS-1:0] xtemp,ytemp;
    reg signed [17:0] atemp;
    
generate
if (ROTATE_TYPE == "ROTATE") begin: Rotating
    
    always@(posedge clk)
    if(!rst_n)
        {xtemp,ytemp,atemp} <= 0;
    else if( Ain <= half_pi && Ain >= -half_pi)     
        begin
            xtemp <= Xin;
            ytemp <= Yin;
            atemp <= Ain;
        end
    else if( Ain > half_pi )
        begin
            xtemp <= -Xin;
            ytemp <= -Yin;
            atemp <= Ain - pi;
        end
    else if( Ain < -half_pi )
        begin
            xtemp <= -Xin;
            ytemp <= -Yin;
            atemp <= Ain + pi;
        end
       
end else if(ROTATE_TYPE == "VECTOR") begin : Vectoring
    
    always@(posedge clk)
    if(!rst_n)
        {xtemp,ytemp,atemp} <= 0;
    else if(Xin>=0)
        begin
            xtemp <= Xin;
            ytemp <= Yin;
            atemp <= 0;
        end
    else if( Xin < 0 && Yin >= 0 )   
        begin 
            xtemp <= -Xin;
            ytemp <= -Yin;
            atemp <= +pi;
        end
    else if( Xin < 0 && Yin < 0 )
        begin 
            xtemp <= -Xin;
            ytemp <= -Yin;
            atemp <= -pi;
        end

end
endgenerate



    wire [DATABITS-1:0] x[ITERATIONS:0];
    wire [DATABITS-1:0] y[ITERATIONS:0];
    wire [17:0] a[ITERATIONS:0];
    
    assign { x[0],y[0],a[0] } = {xtemp,ytemp,atemp};

    genvar i;
    generate for(i=0;i<=ITERATIONS-1;i=i+1) begin
      rotator inst_rotator (clk,rst_n,x[i],y[i],a[i],x[i+1],y[i+1],a[i+1]);
      defparam inst_rotator.ROTATE_TYPE = ROTATE_TYPE;
      defparam inst_rotator.ITERATE_INDEX = i;
      defparam inst_rotator.DATABITS = DATABITS;
      defparam inst_rotator.angle = angle(i);
    end 
    endgenerate
    
    
    reg [ITERATIONS:0] valid_temp;
    always@(posedge clk)
    if(~rst_n)
        valid_temp <= 0;
    else 
        valid_temp <= {valid_temp[ITERATIONS-1:0],Validin};
        
 

    
    reg Validout_reg;
    reg signed [DATABITS+16-1:0] Xout_reg,Yout_reg;
    reg signed [17:0] Aout_reg;

    always@(posedge clk)
    if(!rst_n)
        begin
            { Validout_reg,Xout_reg,Yout_reg,Aout_reg } <= 0;
            { Validout,Xout,Yout,Aout } <= 0;
        end
    else 
        begin
            Validout_reg <= valid_temp[ITERATIONS];
            Xout_reg <= K*$signed(x[ITERATIONS]);
            Yout_reg <= K*$signed(y[ITERATIONS]);
            Aout_reg <= a[ITERATIONS];
            
            if(Validout_reg)
                begin
                    Validout <= Validout_reg;
                    Xout <= Xout_reg[DATABITS+14:15];
                    Yout <= Yout_reg[DATABITS+14:15];
                    Aout <= Aout_reg;
                end
            else 
                { Validout,Xout,Yout,Aout } <= 0;
        end
   
    


function signed [18:0] angle;
  input [3:0] i;
  begin
    case (i)
    4'b0000: angle = 18'd25736 ;
    4'b0001: angle = 18'd15192;
    4'b0010: angle = 18'd8027;
    4'b0011: angle = 18'd4075;
    4'b0100: angle = 18'd2045;
    4'b0101: angle = 18'd1024;
    4'b0110: angle = 18'd512;
    4'b0111: angle = 18'd256;
    4'b1000: angle = 18'd128;
    4'b1001: angle = 18'd64;
    4'b1010: angle = 18'd32;
    4'b1011: angle = 18'd16;
    4'b1100: angle = 18'd8;
    4'b1101: angle = 18'd4;
    4'b1110: angle = 18'd2;
    4'b1111: angle = 18'd1;
    endcase
  end
endfunction

endmodule
module  chen_cordic #(
    
    parameter ROTATE_TYPE = "ROTATE",
    parameter DATABITS = 17,
    parameter ITERATIONS = 16

    )(

    input clk,
    input rst_n,
    
    input Validin,
    input signed [DATABITS-1:0] Xin,
    input signed [DATABITS-1:0] Yin,  
    input signed [17:0] Ain,
    
    output reg Validout,
    output reg signed [DATABITS-1:0] Xout,
    output reg signed [DATABITS-1:0] Yout,
    output reg signed [17:0] Aout
    
    );

    

    
    localparam pi = 18'sd102943;
    localparam half_pi = 18'sd51471;
    localparam K = 16'sb0100110110111010;
    

 

    reg signed [DATABITS-1:0] xtemp,ytemp;
    reg signed [17:0] atemp;
    
generate
if (ROTATE_TYPE == "ROTATE") begin: Rotating
    
    always@(posedge clk)
    if(!rst_n)
        {xtemp,ytemp,atemp} <= 0;
    else if( Ain <= half_pi && Ain >= -half_pi)     
        begin
            xtemp <= Xin;
            ytemp <= Yin;
            atemp <= Ain;
        end
    else if( Ain > half_pi )
        begin
            xtemp <= -Xin;
            ytemp <= -Yin;
            atemp <= Ain - pi;
        end
    else if( Ain < -half_pi )
        begin
            xtemp <= -Xin;
            ytemp <= -Yin;
            atemp <= Ain + pi;
        end
       
end else if(ROTATE_TYPE == "VECTOR") begin : Vectoring
    
    always@(posedge clk)
    if(!rst_n)
        {xtemp,ytemp,atemp} <= 0;
    else if(Xin>=0)
        begin
            xtemp <= Xin;
            ytemp <= Yin;
            atemp <= 0;
        end
    else if( Xin < 0 && Yin >= 0 )   
        begin 
            xtemp <= -Xin;
            ytemp <= -Yin;
            atemp <= +pi;
        end
    else if( Xin < 0 && Yin < 0 )
        begin 
            xtemp <= -Xin;
            ytemp <= -Yin;
            atemp <= -pi;
        end

end
endgenerate



    wire [DATABITS-1:0] x[ITERATIONS:0];
    wire [DATABITS-1:0] y[ITERATIONS:0];
    wire [17:0] a[ITERATIONS:0];
    
    assign { x[0],y[0],a[0] } = {xtemp,ytemp,atemp};

    genvar i;
    generate for(i=0;i<=ITERATIONS-1;i=i+1) begin
      rotator inst_rotator (clk,rst_n,x[i],y[i],a[i],x[i+1],y[i+1],a[i+1]);
      defparam inst_rotator.ROTATE_TYPE = ROTATE_TYPE;
      defparam inst_rotator.ITERATE_INDEX = i;
      defparam inst_rotator.DATABITS = DATABITS;
      defparam inst_rotator.angle = angle(i);
    end 
    endgenerate
    
    
    reg [ITERATIONS:0] valid_temp;
    always@(posedge clk)
    if(~rst_n)
        valid_temp <= 0;
    else 
        valid_temp <= {valid_temp[ITERATIONS-1:0],Validin};
        
 

    
    reg Validout_reg;
    reg signed [DATABITS+16-1:0] Xout_reg,Yout_reg;
    reg signed [17:0] Aout_reg;

    always@(posedge clk)
    if(!rst_n)
        begin
            { Validout_reg,Xout_reg,Yout_reg,Aout_reg } <= 0;
            { Validout,Xout,Yout,Aout } <= 0;
        end
    else 
        begin
            Validout_reg <= valid_temp[ITERATIONS];
            Xout_reg <= K*$signed(x[ITERATIONS]);
            Yout_reg <= K*$signed(y[ITERATIONS]);
            Aout_reg <= a[ITERATIONS];
            
            if(Validout_reg)
                begin
                    Validout <= Validout_reg;
                    Xout <= Xout_reg[DATABITS+14:15];
                    Yout <= Yout_reg[DATABITS+14:15];
                    Aout <= Aout_reg;
                end
            else 
                { Validout,Xout,Yout,Aout } <= 0;
        end
   
    


function signed [18:0] angle;
  input [3:0] i;
  begin
    case (i)
    4'b0000: angle = 18'd25736 ;
    4'b0001: angle = 18'd15192;
    4'b0010: angle = 18'd8027;
    4'b0011: angle = 18'd4075;
    4'b0100: angle = 18'd2045;
    4'b0101: angle = 18'd1024;
    4'b0110: angle = 18'd512;
    4'b0111: angle = 18'd256;
    4'b1000: angle = 18'd128;
    4'b1001: angle = 18'd64;
    4'b1010: angle = 18'd32;
    4'b1011: angle = 18'd16;
    4'b1100: angle = 18'd8;
    4'b1101: angle = 18'd4;
    4'b1110: angle = 18'd2;
    4'b1111: angle = 18'd1;
    endcase
  end
endfunction

endmodule