data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/syzygy-adc-top.v
1: b"%Error: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/syzygy-adc-top.v:113: Cannot find file containing module: 'syzygy_adc_phy'\nsyzygy_adc_phy adc_phy1_impl (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl,data/full_repos/permissive/120851390/syzygy_adc_phy\n             data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl,data/full_repos/permissive/120851390/syzygy_adc_phy.v\n             data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl,data/full_repos/permissive/120851390/syzygy_adc_phy.sv\n             syzygy_adc_phy\n             syzygy_adc_phy.v\n             syzygy_adc_phy.sv\n             obj_dir/syzygy_adc_phy\n             obj_dir/syzygy_adc_phy.v\n             obj_dir/syzygy_adc_phy.sv\n%Error: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/syzygy-adc-top.v:126: Cannot find file containing module: 'syzygy_adc_phy'\nsyzygy_adc_phy adc_phy2_impl (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/syzygy-adc-top.v:139: Cannot find file containing module: 'syzygy_adc_dco'\nsyzygy_adc_dco adc_dco_impl (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/syzygy-adc-top.v:147: Cannot find file containing module: 'syzygy_adc_frame'\nsyzygy_adc_frame adc_frame_impl (\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/syzygy-adc-top.v:159: Cannot find file containing module: 'syzygy_adc_enc'\nsyzygy_adc_enc adc_enc_impl (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120851390/pod-adc-ltc2264/hdl/syzygy-adc-top.v:166: Cannot find file containing module: 'IDELAYCTRL'\nIDELAYCTRL idelay_adc (\n^~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module syzygy_adc_top (
	input  wire                clk,
	input  wire                idelay_ref,
	input  wire                reset_async,


	input  wire [1:0]          adc_out_1p,
	input  wire [1:0]          adc_out_1n,
	input  wire [1:0]          adc_out_2p,
	input  wire [1:0]          adc_out_2n,
	input  wire                adc_dco_p,
	input  wire                adc_dco_n,
	input  wire                adc_fr_p,
	input  wire                adc_fr_n,
	output wire                adc_encode_p,
	output wire                adc_encode_n,
	input  wire                adc_sdo,
	output wire                adc_sdi,
	output wire                adc_cs_n,
	output wire                adc_sck,

	output wire                adc_data_clk,
	output wire [15:0]         adc_data_1,
	output wire [15:0]         adc_data_2,
	output wire                data_valid,
	
	output wire                idelay_rdy
	


	);

wire adc_frame, bufio_clk;
wire bitslip;
reg  reset_sync;
reg  reset_idelay = 1'b1;

wire [13:0] adc_data1, adc_data2;
reg  [7:0]  reset_idelay_cnt = 8'h10;
reg  [7:0]  reset_serdes_cnt = 8'h10;



assign adc_sdi  = 1'b1;
assign adc_cs_n = 1'b1;
assign adc_sck  = 1'b1;



always @(posedge adc_data_clk or posedge reset_async) begin
	if(reset_async == 1'b1) begin
		reset_sync <= 1'b1;
		reset_serdes_cnt <= 8'h10;
	end else begin
		if (reset_serdes_cnt > 00) begin
			reset_serdes_cnt <= reset_serdes_cnt - 1'b1;
			reset_sync <= 1'b1;
		end else begin
			reset_sync <= 1'b0;
		end
	end
end




always @(posedge idelay_ref) begin
	if(reset_async == 1'b1) begin
		reset_idelay <= 1'b1;
		reset_idelay_cnt <= 8'h10;
	end else begin
		if (reset_idelay_cnt > 8'h00) begin
			reset_idelay_cnt <= reset_idelay_cnt - 1'b1;
			reset_idelay <= 1'b1;
		end else begin
			reset_idelay <= 1'b0;
		end
	end
end

syzygy_adc_phy adc_phy1_impl (
	.reset         (reset_sync),
	
	.adc_out_p     (adc_out_1p),
	.adc_out_n     (adc_out_1n),
	.adc_bufio_clk (bufio_clk),
	.adc_slow_clk  (adc_data_clk),

	.bitslip       (bitslip),

	.adc_data_out  (adc_data_1)
);

syzygy_adc_phy adc_phy2_impl (
	.reset         (reset_sync),
	
	.adc_out_p     (adc_out_2p),
	.adc_out_n     (adc_out_2n),
	.adc_bufio_clk (bufio_clk),
	.adc_slow_clk  (adc_data_clk),

	.bitslip       (bitslip),

	.adc_data_out  (adc_data_2)
);

syzygy_adc_dco adc_dco_impl (
	.reset         (reset_async),
	.adc_dco_p     (adc_dco_p),
	.adc_dco_n     (adc_dco_n),
	.clk_out_bufio (bufio_clk),
	.clk_out_div   (adc_data_clk)
);

syzygy_adc_frame adc_frame_impl (
	.slow_clk   (adc_data_clk),
	.reset      (reset_sync),
	
	.adc_bufio_clk (bufio_clk),
	.adc_fr_p   (adc_fr_p),
	.adc_fr_n   (adc_fr_n),

	.data_valid (data_valid),
	.bitslip    (bitslip)
);

syzygy_adc_enc adc_enc_impl (
	.clk          (clk),

	.adc_encode_p (adc_encode_p),
	.adc_encode_n (adc_encode_n)
);

IDELAYCTRL idelay_adc (
	.RST    (reset_idelay),
	.REFCLK (idelay_ref),
	.RDY    (idelay_rdy)
);

endmodule
module syzygy_adc_top (
	input  wire                clk,
	input  wire                idelay_ref,
	input  wire                reset_async,


	input  wire [1:0]          adc_out_1p,
	input  wire [1:0]          adc_out_1n,
	input  wire [1:0]          adc_out_2p,
	input  wire [1:0]          adc_out_2n,
	input  wire                adc_dco_p,
	input  wire                adc_dco_n,
	input  wire                adc_fr_p,
	input  wire                adc_fr_n,
	output wire                adc_encode_p,
	output wire                adc_encode_n,
	input  wire                adc_sdo,
	output wire                adc_sdi,
	output wire                adc_cs_n,
	output wire                adc_sck,

	output wire                adc_data_clk,
	output wire [15:0]         adc_data_1,
	output wire [15:0]         adc_data_2,
	output wire                data_valid,
	
	output wire                idelay_rdy
	


	);


wire adc_frame, bufio_clk;
wire bitslip;
reg  reset_sync;
reg  reset_idelay = 1'b1;

wire [13:0] adc_data1, adc_data2;
reg  [7:0]  reset_idelay_cnt = 8'h10;
reg  [7:0]  reset_serdes_cnt = 8'h10;



assign adc_sdi  = 1'b1;
assign adc_cs_n = 1'b1;
assign adc_sck  = 1'b1;



always @(posedge adc_data_clk or posedge reset_async) begin
	if(reset_async == 1'b1) begin
		reset_sync <= 1'b1;
		reset_serdes_cnt <= 8'h10;
	end else begin
		if (reset_serdes_cnt > 00) begin
			reset_serdes_cnt <= reset_serdes_cnt - 1'b1;
			reset_sync <= 1'b1;
		end else begin
			reset_sync <= 1'b0;
		end
	end
end




always @(posedge idelay_ref) begin
	if(reset_async == 1'b1) begin
		reset_idelay <= 1'b1;
		reset_idelay_cnt <= 8'h10;
	end else begin
		if (reset_idelay_cnt > 8'h00) begin
			reset_idelay_cnt <= reset_idelay_cnt - 1'b1;
			reset_idelay <= 1'b1;
		end else begin
			reset_idelay <= 1'b0;
		end
	end
end

syzygy_adc_phy adc_phy1_impl (
	.reset         (reset_sync),
	
	.adc_out_p     (adc_out_1p),
	.adc_out_n     (adc_out_1n),
	.adc_bufio_clk (bufio_clk),
	.adc_slow_clk  (adc_data_clk),

	.bitslip       (bitslip),

	.adc_data_out  (adc_data_1)
);

syzygy_adc_phy adc_phy2_impl (
	.reset         (reset_sync),
	
	.adc_out_p     (adc_out_2p),
	.adc_out_n     (adc_out_2n),
	.adc_bufio_clk (bufio_clk),
	.adc_slow_clk  (adc_data_clk),

	.bitslip       (bitslip),

	.adc_data_out  (adc_data_2)
);

syzygy_adc_dco adc_dco_impl (
	.reset         (reset_async),
	.adc_dco_p     (adc_dco_p),
	.adc_dco_n     (adc_dco_n),
	.clk_out_bufio (bufio_clk),
	.clk_out_div   (adc_data_clk)
);

syzygy_adc_frame adc_frame_impl (
	.slow_clk   (adc_data_clk),
	.reset      (reset_sync),
	
	.adc_bufio_clk (bufio_clk),
	.adc_fr_p   (adc_fr_p),
	.adc_fr_n   (adc_fr_n),

	.data_valid (data_valid),
	.bitslip    (bitslip)
);

syzygy_adc_enc adc_enc_impl (
	.clk          (clk),

	.adc_encode_p (adc_encode_p),
	.adc_encode_n (adc_encode_n)
);

IDELAYCTRL idelay_adc (
	.RST    (reset_idelay),
	.REFCLK (idelay_ref),
	.RDY    (idelay_rdy)
);

endmodule