data/full_repos/permissive/118082957/main/proj1.v
 line:18: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:10: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = !clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20 rst=1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/118082957/main/proj1.v:17: Unsupported: Ignoring delay on this delayed statement.\n#435\n^\n%Warning-IMPLICIT: data/full_repos/permissive/118082957/main/proj1.v:648: Signal definition not found, creating implicitly: \'Zflag_reg\'\n   MAR_next, Zflag_reg, zflag_next);\n             ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/118082957/main/proj1.v:648: Signal definition not found, creating implicitly: \'zflag_next\'\n   MAR_next, Zflag_reg, zflag_next);\n                        ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/118082957/main/proj1.v:696: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'ACC_reg\' generates 16 bits.\n                                                                     : ... In instance tb_proj1.dut.datapath\n zflag = (!ACC_reg)? 1:0;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/118082957/main/proj1.v:19: Bit extraction of array[255:0] requires 8 bit index, not 16 bits.\n                                                                    : ... In instance tb_proj1\n$display("0x00d %d\\n",tb_proj1.dut.ram_ins.mem256x16[16\'h000d]);\n                                                    ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram(
 we,
 d,
 q,
 addr
 );

input we;
input [15:0]  d;
output reg [15:0] q;
input [7:0] addr;

reg [15:0] mem256x16 [0:255];







always @(*) begin
	if (we) begin
		mem256x16[addr] = d;
	end else begin
		q = mem256x16[addr];
	end

end

endmodule
module ram(
 we,
 d,
 q,
 addr
 );


input we;
input [15:0]  d;
output reg [15:0] q;
input [7:0] addr;

reg [15:0] mem256x16 [0:255];







always @(*) begin
	if (we) begin
		mem256x16[addr] = d;
	end else begin
		q = mem256x16[addr];
	end

end

endmodule