data/full_repos/permissive/156600739/rtl/perips/sirv_gnrl_pipe_stage.sv
 line:69: before: ":"
data/verilator_xmls/83abe07d-87d6-482d-8c80-e37999c28b72.xml
module sirv_gnrl_pipe_stage # (


  parameter CUT_READY = 0,
  parameter DP = 1,
  parameter DW = 32
) (
  input           i_vld, 
  output          i_rdy, 
  input  [DW-1:0] i_dat,
  output          o_vld, 
  input           o_rdy, 
  output reg [DW-1:0] o_dat,

  input           clk,
  input           rst_n
);

  genvar i;
  generate

  if(DP == 0) begin: dp_eq_0

      assign o_vld = i_vld;
      assign i_rdy = o_rdy;
      always @(i_dat)
          o_dat = i_dat;


  end
  else begin: dp_gt_0

      wire vld_set;
      wire vld_clr;
      wire vld_ena;
      reg vld_r;
      wire vld_nxt;


      assign vld_set = i_vld & i_rdy;

      assign vld_clr = o_vld & o_rdy;

      assign vld_ena = vld_set | vld_clr;
      assign vld_nxt = vld_set | (~vld_clr);


      always @(posedge clk or negedge rst_n) begin : p_vld_r
        if (!rst_n)
          vld_r <= 1'b0;
        else if (vld_ena)
          vld_r <= vld_nxt;
      end: p_vld_r

      assign o_vld = vld_r;


      always @(posedge clk) begin : p_o_dat
        if (vld_set)
          o_dat <= i_dat;
      end: p_o_dat

      if(CUT_READY == 1) begin:cut_ready

          assign i_rdy = (~vld_r);
      end
      else begin:no_cut_ready

          assign i_rdy = (~vld_r) | vld_clr;
      end
  end
  endgenerate


endmodule
module sirv_gnrl_pipe_stage # (


  parameter CUT_READY = 0,
  parameter DP = 1,
  parameter DW = 32
) (
  input           i_vld, 
  output          i_rdy, 
  input  [DW-1:0] i_dat,
  output          o_vld, 
  input           o_rdy, 
  output reg [DW-1:0] o_dat,

  input           clk,
  input           rst_n
);


  genvar i;
  generate

  if(DP == 0) begin: dp_eq_0

      assign o_vld = i_vld;
      assign i_rdy = o_rdy;
      always @(i_dat)
          o_dat = i_dat;


  end
  else begin: dp_gt_0

      wire vld_set;
      wire vld_clr;
      wire vld_ena;
      reg vld_r;
      wire vld_nxt;


      assign vld_set = i_vld & i_rdy;

      assign vld_clr = o_vld & o_rdy;

      assign vld_ena = vld_set | vld_clr;
      assign vld_nxt = vld_set | (~vld_clr);


      always @(posedge clk or negedge rst_n) begin : p_vld_r
        if (!rst_n)
          vld_r <= 1'b0;
        else if (vld_ena)
          vld_r <= vld_nxt;
      end: p_vld_r

      assign o_vld = vld_r;


      always @(posedge clk) begin : p_o_dat
        if (vld_set)
          o_dat <= i_dat;
      end: p_o_dat

      if(CUT_READY == 1) begin:cut_ready

          assign i_rdy = (~vld_r);
      end
      else begin:no_cut_ready

          assign i_rdy = (~vld_r) | vld_clr;
      end
  end
  endgenerate


endmodule