data/full_repos/permissive/131242578/ice40_fpga/top.v
data/verilator_xmls/71d89da2-9afa-42e1-b7f9-22b1c94a899b.xml
module top (hwclk, led1, led2, led3, led4, led5, led6, led7, led8 );

    input hwclk;
    output led1;
    output led2;
    output led3;
    output led4;
    output led5;
    output led6;
    output led7;
    output led8;


    reg [24:0] counter = 25'b0;
    reg [7:0] leds = 8'b0;


    assign led1 = leds[0];
    assign led2 = leds[1];
    assign led3 = leds[2];
    assign led4 = leds[3];
    assign led5 = leds[4];
    assign led6 = leds[5];
    assign led7 = leds[6];
    assign led8 = leds[7];


    always @ (posedge hwclk) begin
        counter <= counter + 1;



        	if (counter == 12000000)
        	begin
        		leds <= leds +1;
        		counter <= 0;
        	end 
    end

endmodule
module top (hwclk, led1, led2, led3, led4, led5, led6, led7, led8 );


    input hwclk;
    output led1;
    output led2;
    output led3;
    output led4;
    output led5;
    output led6;
    output led7;
    output led8;


    reg [24:0] counter = 25'b0;
    reg [7:0] leds = 8'b0;


    assign led1 = leds[0];
    assign led2 = leds[1];
    assign led3 = leds[2];
    assign led4 = leds[3];
    assign led5 = leds[4];
    assign led6 = leds[5];
    assign led7 = leds[6];
    assign led8 = leds[7];


    always @ (posedge hwclk) begin
        counter <= counter + 1;



        	if (counter == 12000000)
        	begin
        		leds <= leds +1;
        		counter <= 0;
        	end 
    end

endmodule