data/full_repos/permissive/211316121/lab3_3_module/Carry_bit.v
data/verilator_xmls/87498bd2-2045-4d64-ae81-a310b30cc157.xml
module carry_bit(
input [3:0] A,
input [3:0] B,
input C0,
input [3:0]P,
input [3:0] G,
output [3:0] C
    );

    
    assign C[0]=C0;
    assign C[1]=G[0] | P[0] &C0;
    assign C[2]=G[1] | P[1]&G[0] | P[1]&P[0]&C0;
    assign C[3]=G[2] | P[2]&G[1] | P[2]&P[1]&G[0] | P[2]&P[1]&P[0]&C0;
    
    
endmodule
module carry_bit(
input [3:0] A,
input [3:0] B,
input C0,
input [3:0]P,
input [3:0] G,
output [3:0] C
    );


    
    assign C[0]=C0;
    assign C[1]=G[0] | P[0] &C0;
    assign C[2]=G[1] | P[1]&G[0] | P[1]&P[0]&C0;
    assign C[3]=G[2] | P[2]&G[1] | P[2]&P[1]&G[0] | P[2]&P[1]&P[0]&C0;
    
    
endmodule