data/full_repos/permissive/132220215/testbenches/clock_gen_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/132220215/testbenches/clock_gen_tb.v:3: Cannot find include file: ../clock_gen.v\n`include "../clock_gen.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../clock_gen.v\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../clock_gen.v.v\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../clock_gen.v.sv\n             ../clock_gen.v\n             ../clock_gen.v.v\n             ../clock_gen.v.sv\n             obj_dir/../clock_gen.v\n             obj_dir/../clock_gen.v.v\n             obj_dir/../clock_gen.v.sv\n%Error: data/full_repos/permissive/132220215/testbenches/clock_gen_tb.v:12: Unsupported or unknown PLI call: $monitor\n  $monitor("TIME : %g, CLK : %b",$time,out_sig);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/132220215/testbenches/clock_gen_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("CLK.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/132220215/testbenches/clock_gen_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,clock_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/clock_gen_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #100 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module clock_tb;

 input out_sig;
 clock #(.period(20)) CLK0 (.out(out_sig)); 

 initial
 begin
	 $monitor("TIME : %g, CLK : %b",$time,out_sig);
	 $dumpfile("CLK.vcd");
	 $dumpvars(0,clock_tb);
	 #100 $finish;
 end
endmodule
module clock_tb;


 input out_sig;
 clock #(.period(20)) CLK0 (.out(out_sig)); 

 initial
 begin
	 $monitor("TIME : %g, CLK : %b",$time,out_sig);
	 $dumpfile("CLK.vcd");
	 $dumpvars(0,clock_tb);
	 #100 $finish;
 end
endmodule