data/full_repos/permissive/146618947/mux_21/mux.v
data/verilator_xmls/993b2933-e523-464e-8f8d-8fba208f6eb6.xml
module mux (
            input      selector,
            input      reset,
            input      data_0,
            input      data_1,
            output reg data_out
            );

   always @ (*) begin
      if (!reset) begin
         if (selector) begin
            data_out = data_1;
         end else begin
            data_out = data_0;
         end
      end
   end

   endmodule
module mux (
            input      selector,
            input      reset,
            input      data_0,
            input      data_1,
            output reg data_out
            );


   always @ (*) begin
      if (!reset) begin
         if (selector) begin
            data_out = data_1;
         end else begin
            data_out = data_0;
         end
      end
   end

   endmodule