data/full_repos/permissive/143278/ivltests/br_gh316a.v
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1: b'%Error: data/full_repos/permissive/143278/ivltests/br_gh316a.v:25: Unsupported or unknown PLI call: $monitor\n  $monitor($time,,EN,,I,,O);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/br_gh316a.v:25: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  $monitor($time,,EN,,I,,O);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316a.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #4;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316a.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #0 if (O !== 0) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316a.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #1 I = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316a.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1 EN = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316a.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316a.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #0 if (O !== 0) failed = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316a.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh316a.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #0 if (O !== 1) failed = 1;\n  ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

reg     EN;
reg     I;
tri     O;

pulldown(O);

dut dut(EN, I, O);

reg failed = 0;

initial begin
  $monitor($time,,EN,,I,,O);
  EN = 0;
  #4;
  #0 if (O !== 0) failed = 1;
  #1 I = 1;
  #1 EN = 1;
  #3;
  #0 if (O !== 0) failed = 1;
  #1;
  #0 if (O !== 1) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module test();


reg     EN;
reg     I;
tri     O;

pulldown(O);

dut dut(EN, I, O);

reg failed = 0;

initial begin
  $monitor($time,,EN,,I,,O);
  EN = 0;
  #4;
  #0 if (O !== 0) failed = 1;
  #1 I = 1;
  #1 EN = 1;
  #3;
  #0 if (O !== 0) failed = 1;
  #1;
  #0 if (O !== 1) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule