data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v:38: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'sw\' generates 4 bits.\n                                                                                                           : ... In instance mc6800_controller.program_rom_inst\n            ((sw << 12) | 4\'h0): begin\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v:38: Operator OR expects 16 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                                           : ... In instance mc6800_controller.program_rom_inst\n            ((sw << 12) | 4\'h0): begin\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v:41: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'sw\' generates 4 bits.\n                                                                                                           : ... In instance mc6800_controller.program_rom_inst\n            ((sw << 12) | 4\'h1): begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v:41: Operator OR expects 16 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                                           : ... In instance mc6800_controller.program_rom_inst\n            ((sw << 12) | 4\'h1): begin\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v:44: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'sw\' generates 4 bits.\n                                                                                                           : ... In instance mc6800_controller.program_rom_inst\n            ((sw << 12) | 4\'h2): begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v:44: Operator OR expects 16 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                                                           : ... In instance mc6800_controller.program_rom_inst\n            ((sw << 12) | 4\'h2): begin\n                        ^\n%Error: Exiting due to 6 warning(s)\n'
module cpu_clock_gen(input CLK100MHZ, output [1:0] out);
    reg [8:0] counter;
    reg [1:0] state;
    assign out = state;
    always @ (posedge CLK100MHZ) begin
        counter <= counter + 1;
        state[0] <= counter[8];
        state[1] <= !counter[8];
    end
endmodule
module cpu_clock_gen(input CLK100MHZ, output [1:0] out);

    reg [8:0] counter;
    reg [1:0] state;
    assign out = state;
    always @ (posedge CLK100MHZ) begin
        counter <= counter + 1;
        state[0] <= counter[8];
        state[1] <= !counter[8];
    end
endmodule