data/full_repos/permissive/219428126/half_adder.v
data/verilator_xmls/340f9f43-7805-4006-bf20-4f033769739e.xml
module half_adder(
	A,
	B,
	S,
	C
);


input wire	A;
input wire	B;
output wire	S;
output wire	C;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;

assign	C = SYNTHESIZED_WIRE_0;



assign	SYNTHESIZED_WIRE_1 = B | A;

assign	SYNTHESIZED_WIRE_0 = A & B;

assign	SYNTHESIZED_WIRE_2 =  ~SYNTHESIZED_WIRE_0;

assign	S = SYNTHESIZED_WIRE_1 & SYNTHESIZED_WIRE_2;


endmodule
module half_adder(
	A,
	B,
	S,
	C
);



input wire	A;
input wire	B;
output wire	S;
output wire	C;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;

assign	C = SYNTHESIZED_WIRE_0;



assign	SYNTHESIZED_WIRE_1 = B | A;

assign	SYNTHESIZED_WIRE_0 = A & B;

assign	SYNTHESIZED_WIRE_2 =  ~SYNTHESIZED_WIRE_0;

assign	S = SYNTHESIZED_WIRE_1 & SYNTHESIZED_WIRE_2;


endmodule