data/full_repos/permissive/114459345/srcCache/test_coding.v
 line:16: before: ","
1: b'%Error: data/full_repos/permissive/114459345/srcCache/test_coding.v:16: syntax error, unexpected \',\', expecting \'}\'\n  b = {reg1_i[31:1] + reg2_i[31:1] + {30{1\'b0}, reg1_i[0] & reg2_i[0]}, 1\'b0};\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/114459345/srcCache/test_coding.v:21: Unsupported: Ignoring delay on this delayed statement.\n  forever #1 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module test_mod;
	
	reg[31:0] t;
	reg[31:0] m;
	reg clk;
	reg a;
	reg b;
	reg c;
	
	initial begin



		b = {reg1_i[31:1] + reg2_i[31:1] + {30{1'b0}, reg1_i[0] & reg2_i[0]}, 1'b0};
		a = 1'b0;
		clk = 1'b0;
		c = {{0{"1"}},1'b0};
		$display(c);
		forever #1 clk = ~clk;


	end
	
	always @ (posedge clk) begin



		a <= ~a;


	end
	
	always @ (posedge clk) begin
		b <= a;
	end
	
	always @ (b) begin







	end
	




endmodule
module test_mod;

	
	reg[31:0] t;
	reg[31:0] m;
	reg clk;
	reg a;
	reg b;
	reg c;
	
	initial begin



		b = {reg1_i[31:1] + reg2_i[31:1] + {30{1'b0}, reg1_i[0] & reg2_i[0]}, 1'b0};
		a = 1'b0;
		clk = 1'b0;
		c = {{0{"1"}},1'b0};
		$display(c);
		forever #1 clk = ~clk;


	end
	
	always @ (posedge clk) begin



		a <= ~a;


	end
	
	always @ (posedge clk) begin
		b <= a;
	end
	
	always @ (b) begin







	end
	




endmodule