data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_delta_wrapped_tb.v
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_delta_wrapped_tb.v:3: Cannot find include file: ovl_delta_wrapped.v\n`include "ovl_delta_wrapped.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_delta_wrapped.v\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_delta_wrapped.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_delta_wrapped.v.sv\n             ovl_delta_wrapped.v\n             ovl_delta_wrapped.v.v\n             ovl_delta_wrapped.v.sv\n             obj_dir/ovl_delta_wrapped.v\n             obj_dir/ovl_delta_wrapped.v.v\n             obj_dir/ovl_delta_wrapped.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_delta_wrapped_tb.v:4: Cannot find include file: ovl_ported/ovl_delta.v\n`include "ovl_ported/ovl_delta.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module main();



   reg clk;
   reg rst;



   reg [2:0] min;
   reg [2:0] max;
   reg [11:0] test_expr;
   reg        prevConfigInvalid;


   wire       out;

   reg [11:0] test_expr_prev;
   
   ovl_delta_wrapped ovl_dw_t(.clk(clk),
                              .rst(rst),
                              .min(min),
                              .max(max),
                              .test_expr(test_expr),
                              .prevConfigInvalid(prevConfigInvalid),
                              .out(out));

   initial begin
      clk = 0;
      rst = 1;
      min = 0;
      max = 0;
      test_expr = 0;
      test_expr_prev = 0;
      
      prevConfigInvalid = 0;
   end

   always begin
      clk = #5 !clk;
   end

   always @(posedge clk) begin
      test_expr_prev <= test_expr;
   end
   

endmodule
module main();




   reg clk;
   reg rst;



   reg [2:0] min;
   reg [2:0] max;
   reg [11:0] test_expr;
   reg        prevConfigInvalid;


   wire       out;

   reg [11:0] test_expr_prev;
   
   ovl_delta_wrapped ovl_dw_t(.clk(clk),
                              .rst(rst),
                              .min(min),
                              .max(max),
                              .test_expr(test_expr),
                              .prevConfigInvalid(prevConfigInvalid),
                              .out(out));

   initial begin
      clk = 0;
      rst = 1;
      min = 0;
      max = 0;
      test_expr = 0;
      test_expr_prev = 0;
      
      prevConfigInvalid = 0;
   end

   always begin
      clk = #5 !clk;
   end

   always @(posedge clk) begin
      test_expr_prev <= test_expr;
   end
   

endmodule