data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Square_root/flot_isqrt.v
 line:55: before: "integer"
1: b'%Error: Cannot find file containing module: Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Square_root/flot_isqrt.v\n%Error: Exiting due to 3 error(s)\n'
module flot_isqrt_Ito
			#(parameter 		  
			
									  WIDTH = 32,
									  WIDTH_exp = 8,
									  WIDTH_mat = 23,
									  LUT_addWidth = 6,
									  LUT_bits = 13
			


									  )			
			( input 				  CLK,
									  nRST,
			  input [WIDTH-1:0] OP,
			  input 				  CE,
			  input 				  exce_in,
			  output reg 		  exce_out,
			  output reg [WIDTH_mat+WIDTH_exp:0] result
			 ); 


	function integer log2;
		input integer n;
		begin
			log2 = 0;
			while (2**log2<n) begin
				log2 = log2 + 1;
			end
		end
	endfunction



	reg 					  sign;
	reg [WIDTH_exp-1:0] exp;
	reg [WIDTH_exp:0] exp_out;
	reg [WIDTH_mat	 :0] mati;
	wire[WIDTH_mat+1:0] mati_tmp;
	wire[WIDTH_mat+1:0] mati_tmp2;
	reg [WIDTH_mat-1:0] mati_out;

	always @ * begin
		if(!nRST) begin
			sign 	 = 0;	
			exp  	 = 0;
			mati 	 = 0;
		end else begin
			sign 	 = OP[WIDTH-1];		
			exp  	 = OP[WIDTH-1-1:WIDTH-1-WIDTH_exp];
			mati[WIDTH_mat] 		= 1'b1;
			mati[WIDTH_mat-1 :0] = OP[WIDTH_mat-1 :0];
		end
	end


	Square_Root_Reciprocal_Ito_Iter1
	#(
		.WL(WIDTH_mat+1),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth),
		.dWL(WIDTH_mat+1+3),
		.WLO(WIDTH_mat+2)
    )
	Fang_Square_Root_Reciprocal_Ito_Iter1
	(
		.CLK(CLK), 
		.nRST(nRST),
		.CE(CE), 
		.din(mati), 
		.dout(mati_tmp)
	);




	reg [WIDTH_exp-1:0] bias = (2**(WIDTH_exp-1))-1;
	reg [WIDTH_exp-1:0] diff;
	
	reg [31:0] sqrttwo = 32'b1_0110_1010_0000_1001_1110_0110_0110_011;
	mult_unsigned 
	 #(.WI1(1),   .WF1(WIDTH_mat+1), .WI2(1),   	  .WF2(WIDTH_mat+1),   .WIO(1),    		.WFO(WIDTH_mat+1)) 
	multiplier_scaling
	  (.CLK(CLK), .RST(nRST),      .in1(mati_tmp), .in2(sqrttwo[31:(32-WIDTH_mat-2)]),  .out(mati_tmp2));	
	
	always @ * begin
		if(!nRST) begin
			exp_out = 0;
			mati_out = 0;
			diff = 0;
		end else begin
			if (exp>=bias) begin
				diff = exp - bias;
				if (diff[0]==1'b0) begin
					exp_out = bias - (exp - bias)/2 - 1;
					mati_out = mati_tmp[WIDTH_mat-1:0];
				end else begin
					exp_out = bias - (exp - bias)/2 - 1;
					mati_out = mati_tmp2[WIDTH_mat :1];
				end
			end else begin
				diff = bias - exp;
				if (diff[0]==1'b0) begin
					exp_out  = bias + (bias - exp)/2;
					mati_out = mati_tmp[WIDTH_mat-1:0]-1;
				end else begin
					exp_out  = bias + (bias - exp)/2;
					mati_out = mati_tmp2[WIDTH_mat :1];
				end
			end
		end
	end 



	always @* begin
		if(!nRST) begin
			result = 0;
		end else begin
			result = {sign, exp_out[WIDTH_exp-1:0], mati_out};
		end
	end



always @* begin
	if(exce_in||exp_out[WIDTH_exp]) 
		exce_out <= 1'b1;
	else
		exce_out <= 1'b0;
end


endmodule
module flot_isqrt_Ito
			#(parameter 		  
			
									  WIDTH = 32,
									  WIDTH_exp = 8,
									  WIDTH_mat = 23,
									  LUT_addWidth = 6,
									  LUT_bits = 13
			


									  )			
			( input 				  CLK,
									  nRST,
			  input [WIDTH-1:0] OP,
			  input 				  CE,
			  input 				  exce_in,
			  output reg 		  exce_out,
			  output reg [WIDTH_mat+WIDTH_exp:0] result
			 );
 


	function integer log2;
		input integer n;
		begin
			log2 = 0;
			while (2**log2<n) begin
				log2 = log2 + 1;
			end
		end
	endfunction



	reg 					  sign;
	reg [WIDTH_exp-1:0] exp;
	reg [WIDTH_exp:0] exp_out;
	reg [WIDTH_mat	 :0] mati;
	wire[WIDTH_mat+1:0] mati_tmp;
	wire[WIDTH_mat+1:0] mati_tmp2;
	reg [WIDTH_mat-1:0] mati_out;

	always @ * begin
		if(!nRST) begin
			sign 	 = 0;	
			exp  	 = 0;
			mati 	 = 0;
		end else begin
			sign 	 = OP[WIDTH-1];		
			exp  	 = OP[WIDTH-1-1:WIDTH-1-WIDTH_exp];
			mati[WIDTH_mat] 		= 1'b1;
			mati[WIDTH_mat-1 :0] = OP[WIDTH_mat-1 :0];
		end
	end


	Square_Root_Reciprocal_Ito_Iter1
	#(
		.WL(WIDTH_mat+1),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth),
		.dWL(WIDTH_mat+1+3),
		.WLO(WIDTH_mat+2)
    )
	Fang_Square_Root_Reciprocal_Ito_Iter1
	(
		.CLK(CLK), 
		.nRST(nRST),
		.CE(CE), 
		.din(mati), 
		.dout(mati_tmp)
	);




	reg [WIDTH_exp-1:0] bias = (2**(WIDTH_exp-1))-1;
	reg [WIDTH_exp-1:0] diff;
	
	reg [31:0] sqrttwo = 32'b1_0110_1010_0000_1001_1110_0110_0110_011;
	mult_unsigned 
	 #(.WI1(1),   .WF1(WIDTH_mat+1), .WI2(1),   	  .WF2(WIDTH_mat+1),   .WIO(1),    		.WFO(WIDTH_mat+1)) 
	multiplier_scaling
	  (.CLK(CLK), .RST(nRST),      .in1(mati_tmp), .in2(sqrttwo[31:(32-WIDTH_mat-2)]),  .out(mati_tmp2));	
	
	always @ * begin
		if(!nRST) begin
			exp_out = 0;
			mati_out = 0;
			diff = 0;
		end else begin
			if (exp>=bias) begin
				diff = exp - bias;
				if (diff[0]==1'b0) begin
					exp_out = bias - (exp - bias)/2 - 1;
					mati_out = mati_tmp[WIDTH_mat-1:0];
				end else begin
					exp_out = bias - (exp - bias)/2 - 1;
					mati_out = mati_tmp2[WIDTH_mat :1];
				end
			end else begin
				diff = bias - exp;
				if (diff[0]==1'b0) begin
					exp_out  = bias + (bias - exp)/2;
					mati_out = mati_tmp[WIDTH_mat-1:0]-1;
				end else begin
					exp_out  = bias + (bias - exp)/2;
					mati_out = mati_tmp2[WIDTH_mat :1];
				end
			end
		end
	end 



	always @* begin
		if(!nRST) begin
			result = 0;
		end else begin
			result = {sign, exp_out[WIDTH_exp-1:0], mati_out};
		end
	end



always @* begin
	if(exce_in||exp_out[WIDTH_exp]) 
		exce_out <= 1'b1;
	else
		exce_out <= 1'b0;
end


endmodule