data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v
1: b"%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:44: Duplicate declaration of signal: 's_der'\n                                                                          : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;\n       ^~~~~\n        data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:5: ... Location of original declaration\n  input s_der,       \n        ^~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:44: Duplicate declaration of signal: 's_izq'\n  wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;\n              ^~~~~\n        data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:16: ... Location of original declaration\n  input s_izq,       \n        ^~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:44: Duplicate declaration of signal: 'd_n'\n  wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;\n                     ^~~\n        data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:26: ... Location of original declaration\n  input d_n,          \n        ^~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:44: Duplicate declaration of signal: 'dir'\n  wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;\n                          ^~~\n        data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:29: ... Location of original declaration\n  input dir,         \n        ^~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:44: Duplicate declaration of signal: 'clkenb'\n  wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;\n                               ^~~~~~\n        data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:38: ... Location of original declaration\n  input clkenb,      \n        ^~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:45: Duplicate declaration of signal: 'modo'\n  wire [1:0] modo;\n             ^~~~\n        data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:31: ... Location of original declaration\n  input [1:0] modo,        \n              ^~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:47: Duplicate declaration of signal: 's_out'\n  wire s_out;\n       ^~~~~\n        data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:41: ... Location of original declaration\n  output s_out       \n         ^~~~~\n%Error: Exiting due to 7 error(s)\n"
module bitHolder (
  input s_der,










  input s_izq,









  input d_n,


  input dir,

  input [1:0] modo,






  input clkenb,


  output s_out

);
  wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;
  wire [1:0] modo;

  wire s_out;

  parameter notoe = 1'b0;

  wire d_in;

  wire nand1Y;

  ternarioDoble d_n_prima(
    .a(s_der),
    .b(s_izq),
    .c(d_n),
    .s1(dir),
    .s2(modo[1]),
    .y(d_in)
  );

  parameter notpreset = 1'b1;
  parameter notclear = 1'b1;

  wire notq;


  notGate ng1(.a(clkenb), .y(clkenb_not));
  notGate ng2(.a(clkenb_not), .y(clkenb_ret));

  ffD bitValue(
    .d(d_in),

    .clk(clkenb_ret),

    .notpreset(notpreset),
    .notclear(notclear),
    .q(s_out),
    .notq(notq)
  );

endmodule
module bitHolder (
  input s_der,










  input s_izq,









  input d_n,


  input dir,

  input [1:0] modo,






  input clkenb,


  output s_out

);

  wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;
  wire [1:0] modo;

  wire s_out;

  parameter notoe = 1'b0;

  wire d_in;

  wire nand1Y;

  ternarioDoble d_n_prima(
    .a(s_der),
    .b(s_izq),
    .c(d_n),
    .s1(dir),
    .s2(modo[1]),
    .y(d_in)
  );

  parameter notpreset = 1'b1;
  parameter notclear = 1'b1;

  wire notq;


  notGate ng1(.a(clkenb), .y(clkenb_not));
  notGate ng2(.a(clkenb_not), .y(clkenb_ret));

  ffD bitValue(
    .d(d_in),

    .clk(clkenb_ret),

    .notpreset(notpreset),
    .notclear(notclear),
    .q(s_out),
    .notq(notq)
  );

endmodule