data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/axi_join.v
data/verilator_xmls/5a77e684-a8a2-4206-a7b9-94a0469bf77f.xml
module axi_join
  #(parameter INPUTS=2)
  (input [INPUTS-1:0] i_tlast, input [INPUTS-1:0] i_tvalid, output [INPUTS-1:0] i_tready,
   output o_tlast, output o_tvalid, input o_tready);

   wire   all_here = &i_tvalid;
   assign o_tvalid = all_here;
   assign o_tlast = |i_tlast;
   assign i_tready = {INPUTS{o_tready & all_here}};
   
endmodule
module axi_join
  #(parameter INPUTS=2)
  (input [INPUTS-1:0] i_tlast, input [INPUTS-1:0] i_tvalid, output [INPUTS-1:0] i_tready,
   output o_tlast, output o_tvalid, input o_tready);


   wire   all_here = &i_tvalid;
   assign o_tvalid = all_here;
   assign o_tlast = |i_tlast;
   assign i_tready = {INPUTS{o_tready & all_here}};
   
endmodule