data/full_repos/permissive/11455462/90522229_4_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_4_tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n      #30\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_4_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n      #30\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_4_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n      #30 \n      ^\n%Error: data/full_repos/permissive/11455462/90522229_4_tb.v:4: Cannot find file containing module: \'bcd_greey\'\n   bcd_greey test(a,b,c,d,in);\n   ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/bcd_greey\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/bcd_greey.v\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/bcd_greey.sv\n             bcd_greey\n             bcd_greey.v\n             bcd_greey.sv\n             obj_dir/bcd_greey\n             obj_dir/bcd_greey.v\n             obj_dir/bcd_greey.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bcd_greey_tb;
   reg [3:0] in;
   wire a,b,c,d;
   bcd_greey test(a,b,c,d,in);
   initial 
   begin
      in = 4'b0000;
      #30
      in = 4'b0001;
      #30
      in = 4'b0010;
      #30 
      in = 4'b1111;
      
   end
endmodule
module bcd_greey_tb;

   reg [3:0] in;
   wire a,b,c,d;
   bcd_greey test(a,b,c,d,in);
   initial 
   begin
      in = 4'b0000;
      #30
      in = 4'b0001;
      #30
      in = 4'b0010;
      #30 
      in = 4'b1111;
      
   end
endmodule