data/full_repos/permissive/147790758/tb2_b27s.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:15: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:18: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:24: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:27: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:48: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:51: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:57: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_b27s.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/147790758/tb2_b27s.v:9: Cannot find file containing module: \'b27s\'\nb27s DUT (.sw(datain), .led(dataout));\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/b27s\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/b27s.v\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/b27s.sv\n             b27s\n             b27s.v\n             b27s.sv\n             obj_dir/b27s\n             obj_dir/b27s.v\n             obj_dir/b27s.sv\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb2_b27s();
	reg [3:0]datain;
	wire [6:0]dataout;
	reg [6:0]expected;
	integer i;
	
b27s DUT (.sw(datain), .led(dataout));


initial begin: make_data
	$display("**UNIT TEST STARTED**");
	datain = 4'd0; expected = 7'b0111111;
	#10;
	check_data(dataout, expected);
	datain = 4'd1; expected = 7'b0000110 ;
	#10;
	check_data(dataout, expected);
	datain = 4'd2; expected = 7'b1011011 ;
	#10;
	check_data(dataout, expected);
	datain = 4'd3; expected =7'b1001111 ;
	#10;
	check_data(dataout, expected);
	datain = 4'd4; expected = 7'b1100110 ;
	#10;
	check_data(dataout, expected);
	datain = 4'd5; expected = 7'b1101101;
	#10;
	check_data(dataout, expected);
	datain = 4'd6; expected = 7'b1111101;
	#10;
	check_data(dataout, expected);
	datain = 4'd7; expected = 7'b0000111;
	#10;
	check_data(dataout, expected);
	datain = 4'd8; expected = 7'b1111111;
	#10;
	check_data(dataout, expected);
	datain = 4'd9; expected = 7'b1101111;
	#10;
	check_data(dataout, expected);
	datain = 4'd10; expected = 7'b1110111;
	#10;
	check_data(dataout, expected);
	datain = 4'd11; expected = 7'b1111100;
	#10;
	check_data(dataout, expected);
	datain = 4'd12; expected = 7'b0111001;
	#10;
	check_data(dataout, expected);
	datain = 4'd13; expected = 7'b1011110;
	#10;
	check_data(dataout, expected);
	datain = 4'd14; expected = 7'b1111011;
	#10;
	check_data(dataout, expected);
	datain = 4'd15; expected = 7'b1110001;
	#10;
	check_data(dataout, expected);
	$display("**ALL TESTS PASSED**");
	$stop;
	end
	
	task check_data;
		input [6:0]dataout;
		input [6:0]expected;
	begin	
		$display("Now testing with inputs: %b, Expected result: %b Actual result: %b", datain, expected, dataout);
		if (dataout != expected) begin
			$display("ERROR: Expected %b, but got %b. Inputs were: %b", expected, dataout, datain);
			$display("**ERROR: UNIT DOES NOT WORK PROPERLY**");
			$stop;
		end
	end	
	endtask
	
	endmodule
module tb2_b27s();

	reg [3:0]datain;
	wire [6:0]dataout;
	reg [6:0]expected;
	integer i;
	
b27s DUT (.sw(datain), .led(dataout));


initial begin: make_data
	$display("**UNIT TEST STARTED**");
	datain = 4'd0; expected = 7'b0111111;
	#10;
	check_data(dataout, expected);
	datain = 4'd1; expected = 7'b0000110 ;
	#10;
	check_data(dataout, expected);
	datain = 4'd2; expected = 7'b1011011 ;
	#10;
	check_data(dataout, expected);
	datain = 4'd3; expected =7'b1001111 ;
	#10;
	check_data(dataout, expected);
	datain = 4'd4; expected = 7'b1100110 ;
	#10;
	check_data(dataout, expected);
	datain = 4'd5; expected = 7'b1101101;
	#10;
	check_data(dataout, expected);
	datain = 4'd6; expected = 7'b1111101;
	#10;
	check_data(dataout, expected);
	datain = 4'd7; expected = 7'b0000111;
	#10;
	check_data(dataout, expected);
	datain = 4'd8; expected = 7'b1111111;
	#10;
	check_data(dataout, expected);
	datain = 4'd9; expected = 7'b1101111;
	#10;
	check_data(dataout, expected);
	datain = 4'd10; expected = 7'b1110111;
	#10;
	check_data(dataout, expected);
	datain = 4'd11; expected = 7'b1111100;
	#10;
	check_data(dataout, expected);
	datain = 4'd12; expected = 7'b0111001;
	#10;
	check_data(dataout, expected);
	datain = 4'd13; expected = 7'b1011110;
	#10;
	check_data(dataout, expected);
	datain = 4'd14; expected = 7'b1111011;
	#10;
	check_data(dataout, expected);
	datain = 4'd15; expected = 7'b1110001;
	#10;
	check_data(dataout, expected);
	$display("**ALL TESTS PASSED**");
	$stop;
	end
	
	task check_data;
		input [6:0]dataout;
		input [6:0]expected;
	begin	
		$display("Now testing with inputs: %b, Expected result: %b Actual result: %b", datain, expected, dataout);
		if (dataout != expected) begin
			$display("ERROR: Expected %b, but got %b. Inputs were: %b", expected, dataout, datain);
			$display("**ERROR: UNIT DOES NOT WORK PROPERLY**");
			$stop;
		end
	end	
	endtask
	
	endmodule