data/full_repos/permissive/120483935/pwm.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/120483935/pwm.v:18: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'pwm'\n                                                                 : ... In instance pwm_8bit\n  pwm <= (counter > duty_cycle) ? 1 : 0;\n  ^~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module pwm_8bit(
  input clock,


  input[7:0] duty_cycle,

  output pwm
  );

reg[7:0]  counter;
initial   counter = 0;

always@(posedge clock)
begin
  counter = counter + 1;

  pwm <= (counter > duty_cycle) ? 1 : 0;
end

endmodule
module pwm_8bit(
  input clock,


  input[7:0] duty_cycle,

  output pwm
  );


reg[7:0]  counter;
initial   counter = 0;

always@(posedge clock)
begin
  counter = counter + 1;

  pwm <= (counter > duty_cycle) ? 1 : 0;
end

endmodule