data/full_repos/permissive/201488448/1_verilog/36_reduction.v
data/verilator_xmls/15dec6c7-24e9-436d-880c-2f8dc008c6ec.xml
module top_module (
    input [7:0] in,
    output parity); 

    assign	parity = ^in;
    
endmodule
module top_module (
    input [7:0] in,
    output parity);
 

    assign	parity = ^in;
    
endmodule