data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_1.v
 line:35: before: ")"
data/verilator_xmls/a2ec85b2-aa53-45d8-b595-f1e0cd621aa1.xml
module Top (
input [4:0] a,
input [4:0] b,
input [4:0] c,
output [8:0] addition
);
wire [8:0] sum;
wire [7:0] cout;
carrysave_3is2stage instantiated (a[4:0],b[4:0],c[4:0],sum[8:0],cout[7:0]);
assign addition[8:0] = sum[8:0] + ({cout[7:0],1'b0});
endmodule
module Top (
input [4:0] a,
input [4:0] b,
input [4:0] c,
output [8:0] addition
);

wire [8:0] sum;
wire [7:0] cout;
carrysave_3is2stage instantiated (a[4:0],b[4:0],c[4:0],sum[8:0],cout[7:0]);
assign addition[8:0] = sum[8:0] + ({cout[7:0],1'b0});
endmodule