data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v
1: b'%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:3: Cannot find include file: ../../define/global_def.v\n`include "../../define/global_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147520230/src/cpu/stage/MEM,data/full_repos/permissive/147520230/../../define/global_def.v\n             data/full_repos/permissive/147520230/src/cpu/stage/MEM,data/full_repos/permissive/147520230/../../define/global_def.v.v\n             data/full_repos/permissive/147520230/src/cpu/stage/MEM,data/full_repos/permissive/147520230/../../define/global_def.v.sv\n             ../../define/global_def.v\n             ../../define/global_def.v.v\n             ../../define/global_def.v.sv\n             obj_dir/../../define/global_def.v\n             obj_dir/../../define/global_def.v.v\n             obj_dir/../../define/global_def.v.sv\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:14: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     result_in,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`DATA_BUS]     result_in,\n                          ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`REG_ADDR_BUS] write_reg_addr_in,\n    ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:16: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input   wire[`REG_ADDR_BUS] write_reg_addr_in,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`DATA_BUS]     write_hi_data_in,\n    ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:18: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     write_hi_data_in,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:19: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     write_lo_data_in,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:22: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     result_out,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire[`REG_ADDR_BUS] write_reg_addr_out,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:24: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  wire[`REG_ADDR_BUS] write_reg_addr_out,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:26: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire[`DATA_BUS]     write_hi_data_out,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:26: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     write_hi_data_out,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:27: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     write_lo_data_out\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:30: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    PipelineDeliver #(`DATA_BUS_WIDTH)    ff_result(\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:48: Define or directive not defined: \'`REG_ADDR_BUS_WIDTH\'\n    PipelineDeliver #(`REG_ADDR_BUS_WIDTH)    ff_write_reg_addr(\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:66: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_write_hi_data(\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/MEM/MEM_WB.v:75: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_write_lo_data(\n                      ^~~~~~~~~~~~~~~\n%Error: Exiting due to 18 error(s)\n'
module  MEM_WB(
    input   wire                clk,
    input   wire                rst,


    input   wire                stall_current_stage,
    input   wire                stall_next_stage,


    input   wire[`DATA_BUS]     result_in,
    input   wire                write_reg_en_in,
    input   wire[`REG_ADDR_BUS] write_reg_addr_in,
    input   wire                write_hilo_en_in,
    input   wire[`DATA_BUS]     write_hi_data_in,
    input   wire[`DATA_BUS]     write_lo_data_in,


    output  wire[`DATA_BUS]     result_out,
    output  wire                write_reg_en_out,
    output  wire[`REG_ADDR_BUS] write_reg_addr_out,
    output  wire                write_hilo_en_out,
    output  wire[`DATA_BUS]     write_hi_data_out,
    output  wire[`DATA_BUS]     write_lo_data_out
);

    PipelineDeliver #(`DATA_BUS_WIDTH)    ff_result(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (result_in),         
        .out                    (result_out)
    );

    PipelineDeliver #(1)    ff_write_reg_en(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_reg_en_in),   
        .out                    (write_reg_en_out)
    );

    PipelineDeliver #(`REG_ADDR_BUS_WIDTH)    ff_write_reg_addr(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_reg_addr_in), 
        .out                    (write_reg_addr_out)
    );

    PipelineDeliver #(1)    ff_write_hilo_en(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_hilo_en_in),  
        .out                    (write_hilo_en_out)
    );

    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_write_hi_data(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_hi_data_in),  
        .out                    (write_hi_data_out)
    );

    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_write_lo_data(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_lo_data_in),  
        .out                    (write_lo_data_out)
    );    

endmodule
module  MEM_WB(
    input   wire                clk,
    input   wire                rst,


    input   wire                stall_current_stage,
    input   wire                stall_next_stage,


    input   wire[`DATA_BUS]     result_in,
    input   wire                write_reg_en_in,
    input   wire[`REG_ADDR_BUS] write_reg_addr_in,
    input   wire                write_hilo_en_in,
    input   wire[`DATA_BUS]     write_hi_data_in,
    input   wire[`DATA_BUS]     write_lo_data_in,


    output  wire[`DATA_BUS]     result_out,
    output  wire                write_reg_en_out,
    output  wire[`REG_ADDR_BUS] write_reg_addr_out,
    output  wire                write_hilo_en_out,
    output  wire[`DATA_BUS]     write_hi_data_out,
    output  wire[`DATA_BUS]     write_lo_data_out
);


    PipelineDeliver #(`DATA_BUS_WIDTH)    ff_result(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (result_in),         
        .out                    (result_out)
    );

    PipelineDeliver #(1)    ff_write_reg_en(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_reg_en_in),   
        .out                    (write_reg_en_out)
    );

    PipelineDeliver #(`REG_ADDR_BUS_WIDTH)    ff_write_reg_addr(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_reg_addr_in), 
        .out                    (write_reg_addr_out)
    );

    PipelineDeliver #(1)    ff_write_hilo_en(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_hilo_en_in),  
        .out                    (write_hilo_en_out)
    );

    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_write_hi_data(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_hi_data_in),  
        .out                    (write_hi_data_out)
    );

    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_write_lo_data(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_lo_data_in),  
        .out                    (write_lo_data_out)
    );    

endmodule