data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/fifo_2clk.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/fifo_2clk.v:45: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/fifo_2clk.v:46: Cannot find include file: graycode.vh\n`include "graycode.vh" \n         ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module fifo_2clk(wr_clk, wr_rst, wr_en, wr_data, wr_free, wr_full,
                 rd_clk, rd_rst, rd_en, rd_data, rd_used, rd_empty);
`include "util.vh"
`include "graycode.vh"
  parameter              Width     = 8;
  parameter              Depth     = 128;
  localparam             AddrBits  = clog2(Depth);
  localparam             UsedBits  = clog2(Depth+1);

  input                     wr_clk;
  input                     wr_rst;
  input                     wr_en;
  input      [Width-1:0]    wr_data;
  output reg [UsedBits-1:0] wr_free;
  output reg                wr_full;

  input                     rd_clk;
  input                     rd_rst;
  input                     rd_en;
  output [Width-1:0]        rd_data;
  output reg [UsedBits-1:0] rd_used;
  output reg                rd_empty;





  wire [AddrBits:0] wbin, wbin_n, wgray, wgray_n,
                          rbin_n, rgray, rgray_n;
  fifo_ptr #(
    .AddrBits(AddrBits))
  wptr (
    .clk       (wr_clk),
    .rst       (wr_rst),
    .inc       (wr_en),
    .pbin      (wbin),
    .pbin_next (wbin_n),
    .pgray     (wgray),
    .pgray_next(wgray_n));

  fifo_ptr #(
    .AddrBits(AddrBits))
  rptr (
    .clk       (rd_clk),
    .rst       (rd_rst),
    .inc       (rd_en),
    .pbin      ( ),
    .pbin_next (rbin_n),
    .pgray     (rgray),
    .pgray_next(rgray_n));





  reg [AddrBits:0]  rgray_rr, rgray_r,
                    wgray_rr, wgray_r;
  wire [AddrBits:0] rbin_rr, wbin_rr;

  always @(posedge wr_clk)
    if (wr_rst) {rgray_rr, rgray_r} <= 0;
    else        {rgray_rr, rgray_r} <= {rgray_r, rgray};

  always @(posedge rd_clk)
    if (rd_rst) {wgray_rr, wgray_r} <= 0;
    else        {wgray_rr, wgray_r} <= {wgray_r, wgray};

  assign wbin_rr = gray2bin(wgray_rr, AddrBits + 1);
  assign rbin_rr = gray2bin(rgray_rr, AddrBits + 1);




  always @(posedge wr_clk) begin
    if (wr_rst) begin
      wr_full <= 0;
      wr_free <= Depth;
    end else begin




      wr_full <= (wgray_n == {~rgray_rr[AddrBits:AddrBits-1],
                               rgray_rr[AddrBits-2:0]});


      wr_free <= rbin_rr[AddrBits-1:0] - wbin_n[AddrBits-1:0] +
                 ((rbin_rr[AddrBits] ~^ wbin_n[AddrBits]) << AddrBits);
    end
  end




  always @(posedge rd_clk) begin
    if (rd_rst) begin
      rd_empty <= 1;
      rd_used  <= 0;
    end else begin
      rd_empty <= (rgray_n == wgray_rr);
      rd_used  <= wbin_rr[AddrBits-1:0] - rbin_n[AddrBits-1:0] +
                  ((wbin_rr[AddrBits] ^ rbin_n[AddrBits]) << AddrBits);
    end
  end




  wire [AddrBits-1:0] wr_addr, rd_addr;

  assign wr_addr = wbin[AddrBits-1:0];
  assign rd_addr = rbin_n[AddrBits-1:0];

  ram_2c_1r_1w #(
    .Width(Width),
    .Depth(Depth),
    .ReportCollision(0))
  ram (
    .wr_clk (wr_clk),
    .wr_en  (wr_en),
    .wr_addr(wr_addr),
    .wr_data(wr_data),
    .rd_clk (rd_clk),
    .rd_addr(rd_addr),
    .rd_data(rd_data));

endmodule
module fifo_2clk(wr_clk, wr_rst, wr_en, wr_data, wr_free, wr_full,
                 rd_clk, rd_rst, rd_en, rd_data, rd_used, rd_empty);

`include "util.vh"
`include "graycode.vh"
  parameter              Width     = 8;
  parameter              Depth     = 128;
  localparam             AddrBits  = clog2(Depth);
  localparam             UsedBits  = clog2(Depth+1);

  input                     wr_clk;
  input                     wr_rst;
  input                     wr_en;
  input      [Width-1:0]    wr_data;
  output reg [UsedBits-1:0] wr_free;
  output reg                wr_full;

  input                     rd_clk;
  input                     rd_rst;
  input                     rd_en;
  output [Width-1:0]        rd_data;
  output reg [UsedBits-1:0] rd_used;
  output reg                rd_empty;





  wire [AddrBits:0] wbin, wbin_n, wgray, wgray_n,
                          rbin_n, rgray, rgray_n;
  fifo_ptr #(
    .AddrBits(AddrBits))
  wptr (
    .clk       (wr_clk),
    .rst       (wr_rst),
    .inc       (wr_en),
    .pbin      (wbin),
    .pbin_next (wbin_n),
    .pgray     (wgray),
    .pgray_next(wgray_n));

  fifo_ptr #(
    .AddrBits(AddrBits))
  rptr (
    .clk       (rd_clk),
    .rst       (rd_rst),
    .inc       (rd_en),
    .pbin      ( ),
    .pbin_next (rbin_n),
    .pgray     (rgray),
    .pgray_next(rgray_n));





  reg [AddrBits:0]  rgray_rr, rgray_r,
                    wgray_rr, wgray_r;
  wire [AddrBits:0] rbin_rr, wbin_rr;

  always @(posedge wr_clk)
    if (wr_rst) {rgray_rr, rgray_r} <= 0;
    else        {rgray_rr, rgray_r} <= {rgray_r, rgray};

  always @(posedge rd_clk)
    if (rd_rst) {wgray_rr, wgray_r} <= 0;
    else        {wgray_rr, wgray_r} <= {wgray_r, wgray};

  assign wbin_rr = gray2bin(wgray_rr, AddrBits + 1);
  assign rbin_rr = gray2bin(rgray_rr, AddrBits + 1);




  always @(posedge wr_clk) begin
    if (wr_rst) begin
      wr_full <= 0;
      wr_free <= Depth;
    end else begin




      wr_full <= (wgray_n == {~rgray_rr[AddrBits:AddrBits-1],
                               rgray_rr[AddrBits-2:0]});


      wr_free <= rbin_rr[AddrBits-1:0] - wbin_n[AddrBits-1:0] +
                 ((rbin_rr[AddrBits] ~^ wbin_n[AddrBits]) << AddrBits);
    end
  end




  always @(posedge rd_clk) begin
    if (rd_rst) begin
      rd_empty <= 1;
      rd_used  <= 0;
    end else begin
      rd_empty <= (rgray_n == wgray_rr);
      rd_used  <= wbin_rr[AddrBits-1:0] - rbin_n[AddrBits-1:0] +
                  ((wbin_rr[AddrBits] ^ rbin_n[AddrBits]) << AddrBits);
    end
  end




  wire [AddrBits-1:0] wr_addr, rd_addr;

  assign wr_addr = wbin[AddrBits-1:0];
  assign rd_addr = rbin_n[AddrBits-1:0];

  ram_2c_1r_1w #(
    .Width(Width),
    .Depth(Depth),
    .ReportCollision(0))
  ram (
    .wr_clk (wr_clk),
    .wr_en  (wr_en),
    .wr_addr(wr_addr),
    .wr_data(wr_data),
    .rd_clk (rd_clk),
    .rd_addr(rd_addr),
    .rd_data(rd_data));

endmodule