data/full_repos/permissive/170402453/SMPS_ZVS/PacketScheduler.v
 line:49: before: "."
1: b'%Error: data/full_repos/permissive/170402453/SMPS_ZVS/PacketScheduler.v:76: Can\'t find definition of variable: \'endMemIndex\'\n                                                                          : ... Suggested alternative: \'endmemIndex\'\n  if(memIndex!=endMemIndex) begin\n               ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/170402453/SMPS_ZVS/PacketScheduler.v:77: Signal definition not found, creating implicitly: \'addra\'\n   addra = memIndex;\n   ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module PacketScheduler(
    input clk,
	 input [23:0] DCDC_VSense1,
    input [23:0] DCDC_CSense1,
    input [23:0] DCDC_VSense2,
    input [23:0] DCDC_CSense2,
    input [23:0] SMPS_50V_VSense,
    input [23:0] SMPS_50V_CSense,
	 input [23:0] PFC_In_VSense,
    input [23:0] PFC_Out_VSense,
	 output voltageSet1,
	 output currentSet1,
	 output voltageSet2,
	 output currentSet2,
	 output smpsRelay
    );
	 


	 reg [14:0] memIndex,endmemIndex;
	 wire RS232CLK,SENDINGCLK;
	 wire [8:0] RX;
	 reg [8:0] TX;
	 wire ReceiveCLK;
	 reg sendCLK;
	 wire [7:0] RXData;
	 reg [7:0] TXData;
	 wire sendDoneCLK;
	 reg [5:0] parity_DCDCV1;
	 reg [5:0] parity_DCDCV2;
	 reg [5:0] parity_DCDCC1;
	 reg [5:0] parity_DCDCC2;
	 reg [5:0] parity_SMPSV;
	 reg [5:0] parity_SMPSC;
	 reg [5:0] parity_PFC_INV;
	 reg [5:0] parity_PFC_OUTV;
	 


	 kBMemory30kB mem(.clka(clka),
		  .rsta(rsta),
		  .wea(wea),
		  .addra(addra),
		  .dina(dina),
		  .douta(douta)
	 );
	 
	 defparam sclk1.Divider=14;
	 SubClock sclk1(clk,RS232CLK);
	 
	 RS232 serial(RS232CLK,RX,TX,ReceiveCLK,sendCLK,RXData,TXData,sendDoneCLK);
	 
	 defparam sclk2.Divider=667;
	 SubClock sclk2(clk,SENDINGCLK);
	 
	 
	 initial begin
		 memIndex=0;
		 endmemIndex = 0;
		 TX = 0;
		 sendCLK = 0;
		 TXData = 0;
		 parity_DCDCV1 = 0;
		 parity_DCDCV2 = 0;
		 parity_DCDCC1 = 0;
		 parity_DCDCC2 = 0;
		 parity_SMPSV = 0;
		 parity_SMPSC = 0;
		 parity_PFC_INV = 0;
		 parity_PFC_OUTV = 0;
	 end
	 
	 always @(posedge SENDINGCLK) begin

		if(memIndex!=endMemIndex) begin
			addra = memIndex;

			memIndex = memIndex+1;
		end
	 end
	 
	 always @(*) begin
		if(parity_DCDCV1 != ^DCDC_VSense1) begin

			parity_DCDCV1 = ^DCDC_VSense1;



		end
	 end
endmodule
module PacketScheduler(
    input clk,
	 input [23:0] DCDC_VSense1,
    input [23:0] DCDC_CSense1,
    input [23:0] DCDC_VSense2,
    input [23:0] DCDC_CSense2,
    input [23:0] SMPS_50V_VSense,
    input [23:0] SMPS_50V_CSense,
	 input [23:0] PFC_In_VSense,
    input [23:0] PFC_Out_VSense,
	 output voltageSet1,
	 output currentSet1,
	 output voltageSet2,
	 output currentSet2,
	 output smpsRelay
    );

	 


	 reg [14:0] memIndex,endmemIndex;
	 wire RS232CLK,SENDINGCLK;
	 wire [8:0] RX;
	 reg [8:0] TX;
	 wire ReceiveCLK;
	 reg sendCLK;
	 wire [7:0] RXData;
	 reg [7:0] TXData;
	 wire sendDoneCLK;
	 reg [5:0] parity_DCDCV1;
	 reg [5:0] parity_DCDCV2;
	 reg [5:0] parity_DCDCC1;
	 reg [5:0] parity_DCDCC2;
	 reg [5:0] parity_SMPSV;
	 reg [5:0] parity_SMPSC;
	 reg [5:0] parity_PFC_INV;
	 reg [5:0] parity_PFC_OUTV;
	 


	 kBMemory30kB mem(.clka(clka),
		  .rsta(rsta),
		  .wea(wea),
		  .addra(addra),
		  .dina(dina),
		  .douta(douta)
	 );
	 
	 defparam sclk1.Divider=14;
	 SubClock sclk1(clk,RS232CLK);
	 
	 RS232 serial(RS232CLK,RX,TX,ReceiveCLK,sendCLK,RXData,TXData,sendDoneCLK);
	 
	 defparam sclk2.Divider=667;
	 SubClock sclk2(clk,SENDINGCLK);
	 
	 
	 initial begin
		 memIndex=0;
		 endmemIndex = 0;
		 TX = 0;
		 sendCLK = 0;
		 TXData = 0;
		 parity_DCDCV1 = 0;
		 parity_DCDCV2 = 0;
		 parity_DCDCC1 = 0;
		 parity_DCDCC2 = 0;
		 parity_SMPSV = 0;
		 parity_SMPSC = 0;
		 parity_PFC_INV = 0;
		 parity_PFC_OUTV = 0;
	 end
	 
	 always @(posedge SENDINGCLK) begin

		if(memIndex!=endMemIndex) begin
			addra = memIndex;

			memIndex = memIndex+1;
		end
	 end
	 
	 always @(*) begin
		if(parity_DCDCV1 != ^DCDC_VSense1) begin

			parity_DCDCV1 = ^DCDC_VSense1;



		end
	 end
endmodule