data/full_repos/permissive/205673649/BIP/Source/count_clock.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/205673649/BIP/Source/count_clock.v:38: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                : ... In instance count_clock\n        o_counter <= 1\'b0;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module count_clock
#(
    parameter NB_OPCODE = 5,
    parameter NB_ADDR = 11
)
(
    input i_clk,
    input i_rst,
    input [NB_OPCODE-1:0] i_opcode,
    output reg [NB_ADDR-1:0] o_counter
);

always @(posedge i_clk)
begin
    if(!i_rst)
        o_counter <= 1'b0;
    else if(i_opcode != 0)
        o_counter <= o_counter + 1'b1;
    else
        o_counter <= o_counter;
end
endmodule
module count_clock
#(
    parameter NB_OPCODE = 5,
    parameter NB_ADDR = 11
)
(
    input i_clk,
    input i_rst,
    input [NB_OPCODE-1:0] i_opcode,
    output reg [NB_ADDR-1:0] o_counter
);


always @(posedge i_clk)
begin
    if(!i_rst)
        o_counter <= 1'b0;
    else if(i_opcode != 0)
        o_counter <= o_counter + 1'b1;
    else
        o_counter <= o_counter;
end
endmodule