data/full_repos/permissive/117851934/ddr_layout_V5/ip/dac2904/hdl/dac2904_tb.v
 line:56: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/dac2904/hdl/dac2904_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n     forever #5 clk = !clk;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/dac2904/hdl/dac2904_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n     forever #20 sample_clk = !sample_clk;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/dac2904/hdl/dac2904_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/dac2904/hdl/dac2904_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/dac2904/hdl/dac2904_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/dac2904/hdl/dac2904_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n     #5\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/dac2904/hdl/dac2904_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n     #5\n     ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/dac2904/hdl/dac2904_tb.v:20: Cannot find file containing module: \'dac2904\'\n dac2904 tb(clk,reset_n,chipselect,write,writedata,waitrequest,sample_clk,dac_data);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117851934/ddr_layout_V5/ip/dac2904/hdl,data/full_repos/permissive/117851934/dac2904\n             data/full_repos/permissive/117851934/ddr_layout_V5/ip/dac2904/hdl,data/full_repos/permissive/117851934/dac2904.v\n             data/full_repos/permissive/117851934/ddr_layout_V5/ip/dac2904/hdl,data/full_repos/permissive/117851934/dac2904.sv\n             dac2904\n             dac2904.v\n             dac2904.sv\n             obj_dir/dac2904\n             obj_dir/dac2904.v\n             obj_dir/dac2904.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dac2904_tb;

 	reg sample_clk,clk,reset_n,chipselect,write;
 	wire waitrequest;
 	wire [13:0] dac_data;
 	reg [31:0] writedata;
				
 dac2904 tb(clk,reset_n,chipselect,write,writedata,waitrequest,sample_clk,dac_data);


 initial                         
   begin
     clk = 0;
     forever #`delay clk = !clk;
   end

 initial                         
   begin
     sample_clk=0;
     forever #`sample_delay sample_clk = !sample_clk;
   end
task  avalon_write;
  input [31:0] data;
  begin
  #`delay;
	writedata=data;
	chipselect=1;
	write=1;
	#`delay;
	chipselect=0;
	write=0;
	#`write_delay;
	end
endtask
   
 initial                         
   begin
     reset_n = 1;
     #`delay
     reset_n = 0;
     #`delay
     reset_n = 1;
     
     avalon_write(32'h2);
     avalon_write(32'h3); 
     avalon_write(32'h4); 
     avalon_write(32'h5); 
     
   end


 endmodule
module dac2904_tb;


 	reg sample_clk,clk,reset_n,chipselect,write;
 	wire waitrequest;
 	wire [13:0] dac_data;
 	reg [31:0] writedata;
				
 dac2904 tb(clk,reset_n,chipselect,write,writedata,waitrequest,sample_clk,dac_data);


 initial                         
   begin
     clk = 0;
     forever #`delay clk = !clk;
   end

 initial                         
   begin
     sample_clk=0;
     forever #`sample_delay sample_clk = !sample_clk;
   end
task  avalon_write;
  input [31:0] data;
  begin
  #`delay;
	writedata=data;
	chipselect=1;
	write=1;
	#`delay;
	chipselect=0;
	write=0;
	#`write_delay;
	end
endtask
   
 initial                         
   begin
     reset_n = 1;
     #`delay
     reset_n = 0;
     #`delay
     reset_n = 1;
     
     avalon_write(32'h2);
     avalon_write(32'h3); 
     avalon_write(32'h4); 
     avalon_write(32'h5); 
     
   end


 endmodule