data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/rmw_address_unit.v
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/rmw_address_unit.v:149: Cannot find file containing module: 'FD'\n   FD #(.INIT(INIT0)) FD0[MSB:0] (.D(d), .Q(r), .C(clk));\n   ^~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/FD\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/FD.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/FD.sv\n             FD\n             FD.v\n             FD.sv\n             obj_dir/FD\n             obj_dir/FD.v\n             obj_dir/FD.sv\n%Error: Internal Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/rmw_address_unit.v:149: ../V3Width.cpp:3377: Visit function missing? Widthed expectation for this node: PARSEREF 0x5603e8a11280 <e790> {c149}  MSB [TEXT]\n                                                                                                                            : ... In instance rmw_address_unit.DBL_FD0\n   FD #(.INIT(INIT0)) FD0[MSB:0] (.D(d), .Q(r), .C(clk));\n                          ^~~\n"
module dbl_fd
  #(parameter WIDTH = 4,
    parameter MSB = WIDTH-1,
    parameter INIT0 = {WIDTH{1'b0}},
    parameter INIT1 = {WIDTH{1'b0}},
    parameter DELAY = 3)
   (
    input          clk,
    input [MSB:0]  d,
    output [MSB:0] q
    );

`ifdef __icarus
   reg [MSB:0]     q0 = INIT0, q1 = INIT1;

   assign q = q1;

   always @(posedge clk)
     {q1, q0} <= #DELAY {q0, d};

`else
   wire [MSB:0]    r;

   (* KEEP = "TRUE" *)
   FD #(.INIT(INIT0)) FD0[MSB:0] (.D(d), .Q(r), .C(clk));

   (* KEEP = "TRUE" *)
   FD #(.INIT(INIT1)) FD1[MSB:0] (.D(r), .Q(q), .C(clk));

`endif


endmodule
module dbl_fd
  #(parameter WIDTH = 4,
    parameter MSB = WIDTH-1,
    parameter INIT0 = {WIDTH{1'b0}},
    parameter INIT1 = {WIDTH{1'b0}},
    parameter DELAY = 3)
   (
    input          clk,
    input [MSB:0]  d,
    output [MSB:0] q
    );


`ifdef __icarus
   reg [MSB:0]     q0 = INIT0, q1 = INIT1;

   assign q = q1;

   always @(posedge clk)
     {q1, q0} <= #DELAY {q0, d};

`else
   wire [MSB:0]    r;

   (* KEEP = "TRUE" *)
   FD #(.INIT(INIT0)) FD0[MSB:0] (.D(d), .Q(r), .C(clk));

   (* KEEP = "TRUE" *)
   FD #(.INIT(INIT1)) FD1[MSB:0] (.D(r), .Q(q), .C(clk));

`endif


endmodule