data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v
1: b'%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:73: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160924877/evaluate/e203/core,data/full_repos/permissive/160924877/e203_defines.v\n             data/full_repos/permissive/160924877/evaluate/e203/core,data/full_repos/permissive/160924877/e203_defines.v.v\n             data/full_repos/permissive/160924877/evaluate/e203/core,data/full_repos/permissive/160924877/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:76: Define or directive not defined: \'`E203_PC_SIZE\'\n output [`E203_PC_SIZE-1:0] inspect_pc,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:98: Define or directive not defined: \'`E203_PC_SIZE\'\n input  [`E203_PC_SIZE-1:0] pc_rtvec,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:107: Define or directive not defined: \'`E203_PC_SIZE\'\n output  [`E203_PC_SIZE-1:0] cmt_dpc,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:116: Define or directive not defined: \'`E203_PC_SIZE\'\n input  [`E203_PC_SIZE-1:0] dpc_r     ,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:130: Define or directive not defined: \'`E203_HART_ID_W\'\n input  [`E203_HART_ID_W-1:0] core_mhartid,  \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:151: Define or directive not defined: \'`E203_ADDR_SIZE\'\n output [`E203_ADDR_SIZE-1:0]   ppi_icb_cmd_addr, \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:153: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN-1:0]        ppi_icb_cmd_wdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:154: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN/8-1:0]      ppi_icb_cmd_wmask,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:154: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n output [`E203_XLEN/8-1:0]      ppi_icb_cmd_wmask,\n                   ^\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:160: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0]        ppi_icb_rsp_rdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:167: Define or directive not defined: \'`E203_ADDR_SIZE\'\n output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:169: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:170: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:176: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:183: Define or directive not defined: \'`E203_ADDR_SIZE\'\n output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:185: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:186: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:192: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:202: Define or directive not defined: \'`E203_ADDR_SIZE\'\n output [`E203_ADDR_SIZE-1:0]   mem_icb_cmd_addr, \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:204: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN-1:0]        mem_icb_cmd_wdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:205: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN/8-1:0]      mem_icb_cmd_wmask,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:211: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0]        mem_icb_rsp_rdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:217: Define or directive not defined: \'`E203_ADDR_SIZE\'\n output [`E203_ADDR_SIZE-1:0]   dm_icb_cmd_addr, \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:219: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN-1:0]        dm_icb_cmd_wdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:223: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0]        dm_icb_rsp_rdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_cpu_top.v:298: syntax error, unexpected assign\n  assign ppi_icb_rsp_excl_ok   = 1\'b0;\n  ^~~~~~\n%Error: Exiting due to 27 error(s)\n'
module e203_cpu_top(
	output [`E203_PC_SIZE-1:0] inspect_pc,
	output inspect_dbg_irq      ,
	output inspect_mem_cmd_valid,
	output inspect_mem_cmd_ready,
	output inspect_mem_rsp_valid,
	output inspect_mem_rsp_ready,
	output inspect_core_clk     ,

	output core_csr_clk         ,

		



	output core_wfi,




	output tm_stop,


	input  [`E203_PC_SIZE-1:0] pc_rtvec,





	output  dbg_irq_r,


	output  [`E203_PC_SIZE-1:0] cmt_dpc,
	output  cmt_dpc_ena,
	output  [3-1:0] cmt_dcause,
	output  cmt_dcause_ena,
	output  wr_dcsr_ena    ,
	output  wr_dpc_ena     ,
	output  wr_dscratch_ena,
	output  [32-1:0] wr_csr_nxt    ,
	input  [32-1:0] dcsr_r    ,
	input  [`E203_PC_SIZE-1:0] dpc_r     ,
	input  [32-1:0] dscratch_r,


	input  dbg_mode,
	input  dbg_halt_r,
	input  dbg_step_r,
	input  dbg_ebreakm_r,
	input  dbg_stopcycle,
	input  dbg_irq_a,




	input  [`E203_HART_ID_W-1:0] core_mhartid,  


	input  ext_irq_a,

	input  sft_irq_a,

	input  tmr_irq_a,
	
	

	input tcm_sd,

	input tcm_ds,
	




	output                         ppi_icb_cmd_valid,
	input                          ppi_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   ppi_icb_cmd_addr, 
	output                         ppi_icb_cmd_read, 
	output [`E203_XLEN-1:0]        ppi_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      ppi_icb_cmd_wmask,


	input                          ppi_icb_rsp_valid,
	output                         ppi_icb_rsp_ready,
	input                          ppi_icb_rsp_err  ,
	input  [`E203_XLEN-1:0]        ppi_icb_rsp_rdata,




	output                         clint_icb_cmd_valid,
	input                          clint_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, 
	output                         clint_icb_cmd_read, 
	output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,


	input                          clint_icb_rsp_valid,
	output                         clint_icb_rsp_ready,
	input                          clint_icb_rsp_err  ,
	input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,




	output                         plic_icb_cmd_valid,
	input                          plic_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, 
	output                         plic_icb_cmd_read, 
	output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,


	input                          plic_icb_rsp_valid,
	output                         plic_icb_rsp_ready,
	input                          plic_icb_rsp_err  ,
	input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,







	output                         mem_icb_cmd_valid,
	input                          mem_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   mem_icb_cmd_addr, 
	output                         mem_icb_cmd_read, 
	output [`E203_XLEN-1:0]        mem_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      mem_icb_cmd_wmask,


	input                          mem_icb_rsp_valid,
	output                         mem_icb_rsp_ready,
	input                          mem_icb_rsp_err  ,
	input  [`E203_XLEN-1:0]        mem_icb_rsp_rdata,



	output                         dm_icb_cmd_valid,
	input                          dm_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   dm_icb_cmd_addr, 
	output                         dm_icb_cmd_read, 
	output [`E203_XLEN-1:0]        dm_icb_cmd_wdata,

	input                          dm_icb_rsp_valid,
	output                         dm_icb_rsp_ready,
	input  [`E203_XLEN-1:0]        dm_icb_rsp_rdata,



	input  test_mode,


	input  clk,


	input  rst_n
	);

	`ifdef E203_HAS_ITCM
	wire  itcm_ls;

	wire rst_itcm;

	wire                          itcm_ram_cs  ;
	wire                          itcm_ram_we  ;
	wire  [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr;
	wire  [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem ;
	wire  [`E203_ITCM_RAM_DW-1:0] itcm_ram_din ;
		`ifndef E203_HAS_LOCKSTEP
	wire  [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout;
		`endif
	wire                          clk_itcm_ram ;
	`endif

	
	`ifdef E203_HAS_DTCM
	wire  dtcm_ls;

	wire rst_dtcm;
	wire                          dtcm_ram_cs  ;
	wire                          dtcm_ram_we  ;
	wire  [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr;
	wire  [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem ;
	wire  [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din ;
		`ifndef E203_HAS_LOCKSTEP
	wire  [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout;
		`endif
	wire                          clk_dtcm_ram ;
	`endif


`ifndef E203_HAS_LOCKSTEP
	wire ppi_icb_rsp_excl_ok   ;
	wire plic_icb_rsp_excl_ok  ;
	wire clint_icb_rsp_excl_ok ;
	wire mem_icb_rsp_excl_ok   ;


		`ifdef E203_HAS_PPI
	wire ppi_icb_enable;
	wire [`E203_ADDR_SIZE-1:0] ppi_region_indic;
		`endif

		`ifdef E203_HAS_PLIC
	wire plic_icb_enable;
	wire [`E203_ADDR_SIZE-1:0] plic_region_indic;
		`endif

		`ifdef E203_HAS_CLINT
	wire clint_icb_enable;
	wire [`E203_ADDR_SIZE-1:0] clint_region_indic;
		`endif

		`ifdef E203_HAS_MEM_ITF
	wire mem_icb_enable;
		`endif


`endif

		assign ppi_icb_rsp_excl_ok   = 1'b0;
		assign plic_icb_rsp_excl_ok  = 1'b0;
		assign clint_icb_rsp_excl_ok = 1'b0;
		assign mem_icb_rsp_excl_ok   = 1'b0;


		`ifdef E203_HAS_PPI
		assign ppi_icb_enable = 1'b1;
		assign ppi_region_indic = `E203_PPI_ADDR_BASE;
		`else
		assign ppi_icb_enable = 1'b0;
		`endif

		`ifdef E203_HAS_PLIC
		assign plic_icb_enable = 1'b1;
		assign plic_region_indic = `E203_PLIC_ADDR_BASE;
		`else
		assign plic_icb_enable = 1'b0;
		`endif

		`ifdef E203_HAS_CLINT
		assign clint_icb_enable = 1'b1;
		assign clint_region_indic = `E203_CLINT_ADDR_BASE;
		`else
		assign clint_icb_enable = 1'b0;
		`endif

		`ifdef E203_HAS_MEM_ITF
		assign mem_icb_enable = 1'b1;
		`else
		assign mem_icb_enable = 1'b0;
		`endif

		

	e203_cpu #(.MASTER(1)) u_e203_cpu(
		.inspect_pc               (inspect_pc), 
		.inspect_dbg_irq          (inspect_dbg_irq      ),
		.inspect_mem_cmd_valid    (inspect_mem_cmd_valid), 
		.inspect_mem_cmd_ready    (inspect_mem_cmd_ready), 
		.inspect_mem_rsp_valid    (inspect_mem_rsp_valid),
		.inspect_mem_rsp_ready    (inspect_mem_rsp_ready),
		.inspect_core_clk         (inspect_core_clk     ),


		.core_csr_clk          (core_csr_clk      ),


		.tm_stop (tm_stop),
		.pc_rtvec(pc_rtvec),
	`ifdef E203_HAS_ITCM
		.itcm_ls (itcm_ls),
	`endif
	`ifdef E203_HAS_DTCM
		.dtcm_ls (dtcm_ls),
	`endif
		.core_wfi        (core_wfi),
		.dbg_irq_r       (dbg_irq_r      ),

		.cmt_dpc         (cmt_dpc        ),
		.cmt_dpc_ena     (cmt_dpc_ena    ),
		.cmt_dcause      (cmt_dcause     ),
		.cmt_dcause_ena  (cmt_dcause_ena ),

		.wr_dcsr_ena     (wr_dcsr_ena    ),
		.wr_dpc_ena      (wr_dpc_ena     ),
		.wr_dscratch_ena (wr_dscratch_ena),


																		 
		.wr_csr_nxt      (wr_csr_nxt    ),
																		 
		.dcsr_r          (dcsr_r         ),
		.dpc_r           (dpc_r          ),
		.dscratch_r      (dscratch_r     ),

		.dbg_mode        (dbg_mode),
		.dbg_halt_r      (dbg_halt_r),
		.dbg_step_r      (dbg_step_r),
		.dbg_ebreakm_r   (dbg_ebreakm_r),
		.dbg_stopcycle   (dbg_stopcycle),

		.core_mhartid    (core_mhartid),  
		.dbg_irq_a       (dbg_irq_a),
		.ext_irq_a       (ext_irq_a),
		.sft_irq_a       (sft_irq_a),
		.tmr_irq_a       (tmr_irq_a),

		.ppi_region_indic      (ppi_region_indic),
		.ppi_icb_enable        (ppi_icb_enable),
		.ppi_icb_cmd_valid     (ppi_icb_cmd_valid),
		.ppi_icb_cmd_ready     (ppi_icb_cmd_ready),
		.ppi_icb_cmd_addr      (ppi_icb_cmd_addr ),
		.ppi_icb_cmd_read      (ppi_icb_cmd_read ),
		.ppi_icb_cmd_wdata     (ppi_icb_cmd_wdata),
		.ppi_icb_cmd_wmask     (ppi_icb_cmd_wmask),
		.ppi_icb_cmd_lock      (),
		.ppi_icb_cmd_excl      (),
		.ppi_icb_cmd_size      (),
		
		.ppi_icb_rsp_valid     (ppi_icb_rsp_valid),
		.ppi_icb_rsp_ready     (ppi_icb_rsp_ready),
		.ppi_icb_rsp_err       (ppi_icb_rsp_err  ),
		.ppi_icb_rsp_excl_ok   (ppi_icb_rsp_excl_ok  ),
		.ppi_icb_rsp_rdata     (ppi_icb_rsp_rdata),

		.clint_region_indic      (clint_region_indic),
		.clint_icb_enable        (clint_icb_enable),
		.clint_icb_cmd_valid     (clint_icb_cmd_valid),
		.clint_icb_cmd_ready     (clint_icb_cmd_ready),
		.clint_icb_cmd_addr      (clint_icb_cmd_addr ),
		.clint_icb_cmd_read      (clint_icb_cmd_read ),
		.clint_icb_cmd_wdata     (clint_icb_cmd_wdata),
		.clint_icb_cmd_wmask     (clint_icb_cmd_wmask),
		.clint_icb_cmd_lock      (),
		.clint_icb_cmd_excl      (),
		.clint_icb_cmd_size      (),
		
		.clint_icb_rsp_valid     (clint_icb_rsp_valid),
		.clint_icb_rsp_ready     (clint_icb_rsp_ready),
		.clint_icb_rsp_err       (clint_icb_rsp_err  ),
		.clint_icb_rsp_excl_ok   (clint_icb_rsp_excl_ok  ),
		.clint_icb_rsp_rdata     (clint_icb_rsp_rdata),

		.plic_region_indic      (plic_region_indic),
		.plic_icb_enable        (plic_icb_enable),
		.plic_icb_cmd_valid     (plic_icb_cmd_valid),
		.plic_icb_cmd_ready     (plic_icb_cmd_ready),
		.plic_icb_cmd_addr      (plic_icb_cmd_addr ),
		.plic_icb_cmd_read      (plic_icb_cmd_read ),
		.plic_icb_cmd_wdata     (plic_icb_cmd_wdata),
		.plic_icb_cmd_wmask     (plic_icb_cmd_wmask),
		.plic_icb_cmd_lock      (),
		.plic_icb_cmd_excl      (),
		.plic_icb_cmd_size      (),
		
		.plic_icb_rsp_valid     (plic_icb_rsp_valid),
		.plic_icb_rsp_ready     (plic_icb_rsp_ready),
		.plic_icb_rsp_err       (plic_icb_rsp_err  ),
		.plic_icb_rsp_excl_ok   (plic_icb_rsp_excl_ok  ),
		.plic_icb_rsp_rdata     (plic_icb_rsp_rdata),



	`ifdef E203_HAS_MEM_ITF
		.mem_icb_enable     (mem_icb_enable),
		.mem_icb_cmd_valid  (mem_icb_cmd_valid),
		.mem_icb_cmd_ready  (mem_icb_cmd_ready),
		.mem_icb_cmd_addr   (mem_icb_cmd_addr ),
		.mem_icb_cmd_read   (mem_icb_cmd_read ),
		.mem_icb_cmd_wdata  (mem_icb_cmd_wdata),
		.mem_icb_cmd_wmask  (mem_icb_cmd_wmask),
		.mem_icb_cmd_lock   (),
		.mem_icb_cmd_excl   (),
		.mem_icb_cmd_size   (),
		.mem_icb_cmd_burst  (),
		.mem_icb_cmd_beat   (),
		
		.mem_icb_rsp_valid  (mem_icb_rsp_valid),
		.mem_icb_rsp_ready  (mem_icb_rsp_ready),
		.mem_icb_rsp_err    (mem_icb_rsp_err  ),
		.mem_icb_rsp_excl_ok(mem_icb_rsp_excl_ok  ),
		.mem_icb_rsp_rdata  (mem_icb_rsp_rdata),
	`endif

		.dm_icb_cmd_valid    (dm_icb_cmd_valid  ),
	    .dm_icb_cmd_ready    (dm_icb_cmd_ready  ),
	    .dm_icb_cmd_addr     (dm_icb_cmd_addr   ),
	    .dm_icb_cmd_read     (dm_icb_cmd_read   ),
	    .dm_icb_cmd_wdata    (dm_icb_cmd_wdata  ),
	     
	    .dm_icb_rsp_valid    (dm_icb_rsp_valid  ),
	    .dm_icb_rsp_ready    (dm_icb_rsp_ready  ),
	    .dm_icb_rsp_rdata    (dm_icb_rsp_rdata  ),

	`ifdef E203_HAS_ITCM
		.itcm_ram_cs   (itcm_ram_cs  ),
		.itcm_ram_we   (itcm_ram_we  ),
		.itcm_ram_addr (itcm_ram_addr), 
		.itcm_ram_wem  (itcm_ram_wem ),
		.itcm_ram_din  (itcm_ram_din ),         
		.itcm_ram_dout (itcm_ram_dout),
		.clk_itcm_ram  (clk_itcm_ram ),  
		.rst_itcm(rst_itcm),
	`endif

	`ifdef E203_HAS_DTCM
		.dtcm_ram_cs   (dtcm_ram_cs  ),
		.dtcm_ram_we   (dtcm_ram_we  ),
		.dtcm_ram_addr (dtcm_ram_addr), 
		.dtcm_ram_wem  (dtcm_ram_wem ),
		.dtcm_ram_din  (dtcm_ram_din ),         
		.dtcm_ram_dout (dtcm_ram_dout),
		.clk_dtcm_ram  (clk_dtcm_ram ),  
		.rst_dtcm(rst_dtcm),
	`endif

		.test_mode     (test_mode), 
	`ifndef E203_HAS_LOCKSTEP
	`endif
		.rst_n         (rst_n),
		.clk           (clk  ) 

	);

	e203_srams u_e203_srams(
	`ifdef E203_HAS_DTCM
	 .dtcm_ram_sd (tcm_sd),
	 .dtcm_ram_ds (tcm_ds),
	 .dtcm_ram_ls (dtcm_ls),

	 .dtcm_ram_cs   (dtcm_ram_cs  ),
	 .dtcm_ram_we   (dtcm_ram_we  ),
	 .dtcm_ram_addr (dtcm_ram_addr), 
	 .dtcm_ram_wem  (dtcm_ram_wem ),
	 .dtcm_ram_din  (dtcm_ram_din ),         
	 .dtcm_ram_dout (dtcm_ram_dout),
	 .clk_dtcm_ram  (clk_dtcm_ram ),  
	 .rst_dtcm(rst_dtcm),
	`endif

	`ifdef E203_HAS_ITCM
	 .itcm_ram_sd (tcm_sd),
	 .itcm_ram_ds (tcm_ds),
	 .itcm_ram_ls (itcm_ls),

	 .itcm_ram_cs   (itcm_ram_cs  ),
	 .itcm_ram_we   (itcm_ram_we  ),
	 .itcm_ram_addr (itcm_ram_addr), 
	 .itcm_ram_wem  (itcm_ram_wem ),
	 .itcm_ram_din  (itcm_ram_din ),         
	 .itcm_ram_dout (itcm_ram_dout),
	 .clk_itcm_ram  (clk_itcm_ram ),  
	 .rst_itcm(rst_itcm),
	`endif
	 .test_mode (test_mode) 
	);

	


endmodule
module e203_cpu_top(
	output [`E203_PC_SIZE-1:0] inspect_pc,
	output inspect_dbg_irq      ,
	output inspect_mem_cmd_valid,
	output inspect_mem_cmd_ready,
	output inspect_mem_rsp_valid,
	output inspect_mem_rsp_ready,
	output inspect_core_clk     ,

	output core_csr_clk         ,

		



	output core_wfi,




	output tm_stop,


	input  [`E203_PC_SIZE-1:0] pc_rtvec,





	output  dbg_irq_r,


	output  [`E203_PC_SIZE-1:0] cmt_dpc,
	output  cmt_dpc_ena,
	output  [3-1:0] cmt_dcause,
	output  cmt_dcause_ena,
	output  wr_dcsr_ena    ,
	output  wr_dpc_ena     ,
	output  wr_dscratch_ena,
	output  [32-1:0] wr_csr_nxt    ,
	input  [32-1:0] dcsr_r    ,
	input  [`E203_PC_SIZE-1:0] dpc_r     ,
	input  [32-1:0] dscratch_r,


	input  dbg_mode,
	input  dbg_halt_r,
	input  dbg_step_r,
	input  dbg_ebreakm_r,
	input  dbg_stopcycle,
	input  dbg_irq_a,




	input  [`E203_HART_ID_W-1:0] core_mhartid,  


	input  ext_irq_a,

	input  sft_irq_a,

	input  tmr_irq_a,
	
	

	input tcm_sd,

	input tcm_ds,
	




	output                         ppi_icb_cmd_valid,
	input                          ppi_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   ppi_icb_cmd_addr, 
	output                         ppi_icb_cmd_read, 
	output [`E203_XLEN-1:0]        ppi_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      ppi_icb_cmd_wmask,


	input                          ppi_icb_rsp_valid,
	output                         ppi_icb_rsp_ready,
	input                          ppi_icb_rsp_err  ,
	input  [`E203_XLEN-1:0]        ppi_icb_rsp_rdata,




	output                         clint_icb_cmd_valid,
	input                          clint_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, 
	output                         clint_icb_cmd_read, 
	output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,


	input                          clint_icb_rsp_valid,
	output                         clint_icb_rsp_ready,
	input                          clint_icb_rsp_err  ,
	input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,




	output                         plic_icb_cmd_valid,
	input                          plic_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, 
	output                         plic_icb_cmd_read, 
	output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,


	input                          plic_icb_rsp_valid,
	output                         plic_icb_rsp_ready,
	input                          plic_icb_rsp_err  ,
	input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,







	output                         mem_icb_cmd_valid,
	input                          mem_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   mem_icb_cmd_addr, 
	output                         mem_icb_cmd_read, 
	output [`E203_XLEN-1:0]        mem_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      mem_icb_cmd_wmask,


	input                          mem_icb_rsp_valid,
	output                         mem_icb_rsp_ready,
	input                          mem_icb_rsp_err  ,
	input  [`E203_XLEN-1:0]        mem_icb_rsp_rdata,



	output                         dm_icb_cmd_valid,
	input                          dm_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   dm_icb_cmd_addr, 
	output                         dm_icb_cmd_read, 
	output [`E203_XLEN-1:0]        dm_icb_cmd_wdata,

	input                          dm_icb_rsp_valid,
	output                         dm_icb_rsp_ready,
	input  [`E203_XLEN-1:0]        dm_icb_rsp_rdata,



	input  test_mode,


	input  clk,


	input  rst_n
	);


	`ifdef E203_HAS_ITCM
	wire  itcm_ls;

	wire rst_itcm;

	wire                          itcm_ram_cs  ;
	wire                          itcm_ram_we  ;
	wire  [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr;
	wire  [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem ;
	wire  [`E203_ITCM_RAM_DW-1:0] itcm_ram_din ;
		`ifndef E203_HAS_LOCKSTEP
	wire  [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout;
		`endif
	wire                          clk_itcm_ram ;
	`endif

	
	`ifdef E203_HAS_DTCM
	wire  dtcm_ls;

	wire rst_dtcm;
	wire                          dtcm_ram_cs  ;
	wire                          dtcm_ram_we  ;
	wire  [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr;
	wire  [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem ;
	wire  [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din ;
		`ifndef E203_HAS_LOCKSTEP
	wire  [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout;
		`endif
	wire                          clk_dtcm_ram ;
	`endif


`ifndef E203_HAS_LOCKSTEP
	wire ppi_icb_rsp_excl_ok   ;
	wire plic_icb_rsp_excl_ok  ;
	wire clint_icb_rsp_excl_ok ;
	wire mem_icb_rsp_excl_ok   ;


		`ifdef E203_HAS_PPI
	wire ppi_icb_enable;
	wire [`E203_ADDR_SIZE-1:0] ppi_region_indic;
		`endif

		`ifdef E203_HAS_PLIC
	wire plic_icb_enable;
	wire [`E203_ADDR_SIZE-1:0] plic_region_indic;
		`endif

		`ifdef E203_HAS_CLINT
	wire clint_icb_enable;
	wire [`E203_ADDR_SIZE-1:0] clint_region_indic;
		`endif

		`ifdef E203_HAS_MEM_ITF
	wire mem_icb_enable;
		`endif


`endif

		assign ppi_icb_rsp_excl_ok   = 1'b0;
		assign plic_icb_rsp_excl_ok  = 1'b0;
		assign clint_icb_rsp_excl_ok = 1'b0;
		assign mem_icb_rsp_excl_ok   = 1'b0;


		`ifdef E203_HAS_PPI
		assign ppi_icb_enable = 1'b1;
		assign ppi_region_indic = `E203_PPI_ADDR_BASE;
		`else
		assign ppi_icb_enable = 1'b0;
		`endif

		`ifdef E203_HAS_PLIC
		assign plic_icb_enable = 1'b1;
		assign plic_region_indic = `E203_PLIC_ADDR_BASE;
		`else
		assign plic_icb_enable = 1'b0;
		`endif

		`ifdef E203_HAS_CLINT
		assign clint_icb_enable = 1'b1;
		assign clint_region_indic = `E203_CLINT_ADDR_BASE;
		`else
		assign clint_icb_enable = 1'b0;
		`endif

		`ifdef E203_HAS_MEM_ITF
		assign mem_icb_enable = 1'b1;
		`else
		assign mem_icb_enable = 1'b0;
		`endif

		

	e203_cpu #(.MASTER(1)) u_e203_cpu(
		.inspect_pc               (inspect_pc), 
		.inspect_dbg_irq          (inspect_dbg_irq      ),
		.inspect_mem_cmd_valid    (inspect_mem_cmd_valid), 
		.inspect_mem_cmd_ready    (inspect_mem_cmd_ready), 
		.inspect_mem_rsp_valid    (inspect_mem_rsp_valid),
		.inspect_mem_rsp_ready    (inspect_mem_rsp_ready),
		.inspect_core_clk         (inspect_core_clk     ),


		.core_csr_clk          (core_csr_clk      ),


		.tm_stop (tm_stop),
		.pc_rtvec(pc_rtvec),
	`ifdef E203_HAS_ITCM
		.itcm_ls (itcm_ls),
	`endif
	`ifdef E203_HAS_DTCM
		.dtcm_ls (dtcm_ls),
	`endif
		.core_wfi        (core_wfi),
		.dbg_irq_r       (dbg_irq_r      ),

		.cmt_dpc         (cmt_dpc        ),
		.cmt_dpc_ena     (cmt_dpc_ena    ),
		.cmt_dcause      (cmt_dcause     ),
		.cmt_dcause_ena  (cmt_dcause_ena ),

		.wr_dcsr_ena     (wr_dcsr_ena    ),
		.wr_dpc_ena      (wr_dpc_ena     ),
		.wr_dscratch_ena (wr_dscratch_ena),


																		 
		.wr_csr_nxt      (wr_csr_nxt    ),
																		 
		.dcsr_r          (dcsr_r         ),
		.dpc_r           (dpc_r          ),
		.dscratch_r      (dscratch_r     ),

		.dbg_mode        (dbg_mode),
		.dbg_halt_r      (dbg_halt_r),
		.dbg_step_r      (dbg_step_r),
		.dbg_ebreakm_r   (dbg_ebreakm_r),
		.dbg_stopcycle   (dbg_stopcycle),

		.core_mhartid    (core_mhartid),  
		.dbg_irq_a       (dbg_irq_a),
		.ext_irq_a       (ext_irq_a),
		.sft_irq_a       (sft_irq_a),
		.tmr_irq_a       (tmr_irq_a),

		.ppi_region_indic      (ppi_region_indic),
		.ppi_icb_enable        (ppi_icb_enable),
		.ppi_icb_cmd_valid     (ppi_icb_cmd_valid),
		.ppi_icb_cmd_ready     (ppi_icb_cmd_ready),
		.ppi_icb_cmd_addr      (ppi_icb_cmd_addr ),
		.ppi_icb_cmd_read      (ppi_icb_cmd_read ),
		.ppi_icb_cmd_wdata     (ppi_icb_cmd_wdata),
		.ppi_icb_cmd_wmask     (ppi_icb_cmd_wmask),
		.ppi_icb_cmd_lock      (),
		.ppi_icb_cmd_excl      (),
		.ppi_icb_cmd_size      (),
		
		.ppi_icb_rsp_valid     (ppi_icb_rsp_valid),
		.ppi_icb_rsp_ready     (ppi_icb_rsp_ready),
		.ppi_icb_rsp_err       (ppi_icb_rsp_err  ),
		.ppi_icb_rsp_excl_ok   (ppi_icb_rsp_excl_ok  ),
		.ppi_icb_rsp_rdata     (ppi_icb_rsp_rdata),

		.clint_region_indic      (clint_region_indic),
		.clint_icb_enable        (clint_icb_enable),
		.clint_icb_cmd_valid     (clint_icb_cmd_valid),
		.clint_icb_cmd_ready     (clint_icb_cmd_ready),
		.clint_icb_cmd_addr      (clint_icb_cmd_addr ),
		.clint_icb_cmd_read      (clint_icb_cmd_read ),
		.clint_icb_cmd_wdata     (clint_icb_cmd_wdata),
		.clint_icb_cmd_wmask     (clint_icb_cmd_wmask),
		.clint_icb_cmd_lock      (),
		.clint_icb_cmd_excl      (),
		.clint_icb_cmd_size      (),
		
		.clint_icb_rsp_valid     (clint_icb_rsp_valid),
		.clint_icb_rsp_ready     (clint_icb_rsp_ready),
		.clint_icb_rsp_err       (clint_icb_rsp_err  ),
		.clint_icb_rsp_excl_ok   (clint_icb_rsp_excl_ok  ),
		.clint_icb_rsp_rdata     (clint_icb_rsp_rdata),

		.plic_region_indic      (plic_region_indic),
		.plic_icb_enable        (plic_icb_enable),
		.plic_icb_cmd_valid     (plic_icb_cmd_valid),
		.plic_icb_cmd_ready     (plic_icb_cmd_ready),
		.plic_icb_cmd_addr      (plic_icb_cmd_addr ),
		.plic_icb_cmd_read      (plic_icb_cmd_read ),
		.plic_icb_cmd_wdata     (plic_icb_cmd_wdata),
		.plic_icb_cmd_wmask     (plic_icb_cmd_wmask),
		.plic_icb_cmd_lock      (),
		.plic_icb_cmd_excl      (),
		.plic_icb_cmd_size      (),
		
		.plic_icb_rsp_valid     (plic_icb_rsp_valid),
		.plic_icb_rsp_ready     (plic_icb_rsp_ready),
		.plic_icb_rsp_err       (plic_icb_rsp_err  ),
		.plic_icb_rsp_excl_ok   (plic_icb_rsp_excl_ok  ),
		.plic_icb_rsp_rdata     (plic_icb_rsp_rdata),



	`ifdef E203_HAS_MEM_ITF
		.mem_icb_enable     (mem_icb_enable),
		.mem_icb_cmd_valid  (mem_icb_cmd_valid),
		.mem_icb_cmd_ready  (mem_icb_cmd_ready),
		.mem_icb_cmd_addr   (mem_icb_cmd_addr ),
		.mem_icb_cmd_read   (mem_icb_cmd_read ),
		.mem_icb_cmd_wdata  (mem_icb_cmd_wdata),
		.mem_icb_cmd_wmask  (mem_icb_cmd_wmask),
		.mem_icb_cmd_lock   (),
		.mem_icb_cmd_excl   (),
		.mem_icb_cmd_size   (),
		.mem_icb_cmd_burst  (),
		.mem_icb_cmd_beat   (),
		
		.mem_icb_rsp_valid  (mem_icb_rsp_valid),
		.mem_icb_rsp_ready  (mem_icb_rsp_ready),
		.mem_icb_rsp_err    (mem_icb_rsp_err  ),
		.mem_icb_rsp_excl_ok(mem_icb_rsp_excl_ok  ),
		.mem_icb_rsp_rdata  (mem_icb_rsp_rdata),
	`endif

		.dm_icb_cmd_valid    (dm_icb_cmd_valid  ),
	    .dm_icb_cmd_ready    (dm_icb_cmd_ready  ),
	    .dm_icb_cmd_addr     (dm_icb_cmd_addr   ),
	    .dm_icb_cmd_read     (dm_icb_cmd_read   ),
	    .dm_icb_cmd_wdata    (dm_icb_cmd_wdata  ),
	     
	    .dm_icb_rsp_valid    (dm_icb_rsp_valid  ),
	    .dm_icb_rsp_ready    (dm_icb_rsp_ready  ),
	    .dm_icb_rsp_rdata    (dm_icb_rsp_rdata  ),

	`ifdef E203_HAS_ITCM
		.itcm_ram_cs   (itcm_ram_cs  ),
		.itcm_ram_we   (itcm_ram_we  ),
		.itcm_ram_addr (itcm_ram_addr), 
		.itcm_ram_wem  (itcm_ram_wem ),
		.itcm_ram_din  (itcm_ram_din ),         
		.itcm_ram_dout (itcm_ram_dout),
		.clk_itcm_ram  (clk_itcm_ram ),  
		.rst_itcm(rst_itcm),
	`endif

	`ifdef E203_HAS_DTCM
		.dtcm_ram_cs   (dtcm_ram_cs  ),
		.dtcm_ram_we   (dtcm_ram_we  ),
		.dtcm_ram_addr (dtcm_ram_addr), 
		.dtcm_ram_wem  (dtcm_ram_wem ),
		.dtcm_ram_din  (dtcm_ram_din ),         
		.dtcm_ram_dout (dtcm_ram_dout),
		.clk_dtcm_ram  (clk_dtcm_ram ),  
		.rst_dtcm(rst_dtcm),
	`endif

		.test_mode     (test_mode), 
	`ifndef E203_HAS_LOCKSTEP
	`endif
		.rst_n         (rst_n),
		.clk           (clk  ) 

	);

	e203_srams u_e203_srams(
	`ifdef E203_HAS_DTCM
	 .dtcm_ram_sd (tcm_sd),
	 .dtcm_ram_ds (tcm_ds),
	 .dtcm_ram_ls (dtcm_ls),

	 .dtcm_ram_cs   (dtcm_ram_cs  ),
	 .dtcm_ram_we   (dtcm_ram_we  ),
	 .dtcm_ram_addr (dtcm_ram_addr), 
	 .dtcm_ram_wem  (dtcm_ram_wem ),
	 .dtcm_ram_din  (dtcm_ram_din ),         
	 .dtcm_ram_dout (dtcm_ram_dout),
	 .clk_dtcm_ram  (clk_dtcm_ram ),  
	 .rst_dtcm(rst_dtcm),
	`endif

	`ifdef E203_HAS_ITCM
	 .itcm_ram_sd (tcm_sd),
	 .itcm_ram_ds (tcm_ds),
	 .itcm_ram_ls (itcm_ls),

	 .itcm_ram_cs   (itcm_ram_cs  ),
	 .itcm_ram_we   (itcm_ram_we  ),
	 .itcm_ram_addr (itcm_ram_addr), 
	 .itcm_ram_wem  (itcm_ram_wem ),
	 .itcm_ram_din  (itcm_ram_din ),         
	 .itcm_ram_dout (itcm_ram_dout),
	 .clk_itcm_ram  (clk_itcm_ram ),  
	 .rst_itcm(rst_itcm),
	`endif
	 .test_mode (test_mode) 
	);

	


endmodule