data/full_repos/permissive/189570969/1180300220-崔涵/1180300220-崔涵-完整工程/project_1.srcs/sources_1/new/huotwo.v
data/verilator_xmls/e0ca3b8d-a85b-48af-91b4-568e4185bd93.xml
module huotwo(
    input a,
    input b,
    output c
    );
    assign c=a|b;
endmodule
module huotwo(
    input a,
    input b,
    output c
    );

    assign c=a|b;
endmodule