data/full_repos/permissive/201699429/src/csi_rx_clk_phy.v
1: b"%Error: data/full_repos/permissive/201699429/src/csi_rx_clk_phy.v:29: Cannot find file containing module: 'IBUFDS_DPHY'\nIBUFDS_DPHY #(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201699429/src,data/full_repos/permissive/201699429/IBUFDS_DPHY\n             data/full_repos/permissive/201699429/src,data/full_repos/permissive/201699429/IBUFDS_DPHY.v\n             data/full_repos/permissive/201699429/src,data/full_repos/permissive/201699429/IBUFDS_DPHY.sv\n             IBUFDS_DPHY\n             IBUFDS_DPHY.v\n             IBUFDS_DPHY.sv\n             obj_dir/IBUFDS_DPHY\n             obj_dir/IBUFDS_DPHY.v\n             obj_dir/IBUFDS_DPHY.sv\n%Error: data/full_repos/permissive/201699429/src/csi_rx_clk_phy.v:44: Cannot find file containing module: 'BUFGCE'\nBUFGCE u_BUFGCE_CLK\n^~~~~~\n%Error: data/full_repos/permissive/201699429/src/csi_rx_clk_phy.v:64: Cannot find file containing module: 'BUFGCE_DIV'\nBUFGCE_DIV #(\n^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module csi_rx_clk_phy(
  input   RST_N,

  input   MIPI_CLK_P,
  input   MIPI_CLK_N,

  output  CLK_BIT,
  output  CLK_DIV,
  output  CLK_BYTE
);

wire clk_bit_pre;




IBUFDS_DPHY #(
  .DIFF_TERM    ( "TRUE"            ),
  .IOSTANDARD   ( "MIPI_DPHY_DCI"   ),
  .SIM_DEVICE   ( "ULTRASCALE_PLUS" )
)
u_IBUFDS_DPHY(
  .I            ( MIPI_CLK_P  ),
  .IB           ( MIPI_CLK_N  ),
  .HSRX_DISABLE ( 1'b0        ),
  .LPRX_DISABLE ( 1'b1        ),
  .HSRX_O       ( clk_bit_pre ),
  .LPRX_O_N     (),
  .LPRX_O_P     ()
);

BUFGCE u_BUFGCE_CLK
(
  .CE ( 1'b1        ),
  .I  ( clk_bit_pre ),
  .O  ( CLK_BIT     )
);

BUFGCE_DIV #(
  .BUFGCE_DIVIDE  ( 4       ),
  .CE_TYPE        ( "SYNC"  ),
  .HARDSYNC_CLR   ( "FALSE" )
)
u_BUFGCE_DIV2(
  .O              ( CLK_BYTE    ),

  .CE             ( 1'b1        ),
  .CLR            ( ~RST_N      ),
  .I              ( clk_bit_pre )
);


endmodule
module csi_rx_clk_phy(
  input   RST_N,

  input   MIPI_CLK_P,
  input   MIPI_CLK_N,

  output  CLK_BIT,
  output  CLK_DIV,
  output  CLK_BYTE
);


wire clk_bit_pre;




IBUFDS_DPHY #(
  .DIFF_TERM    ( "TRUE"            ),
  .IOSTANDARD   ( "MIPI_DPHY_DCI"   ),
  .SIM_DEVICE   ( "ULTRASCALE_PLUS" )
)
u_IBUFDS_DPHY(
  .I            ( MIPI_CLK_P  ),
  .IB           ( MIPI_CLK_N  ),
  .HSRX_DISABLE ( 1'b0        ),
  .LPRX_DISABLE ( 1'b1        ),
  .HSRX_O       ( clk_bit_pre ),
  .LPRX_O_N     (),
  .LPRX_O_P     ()
);

BUFGCE u_BUFGCE_CLK
(
  .CE ( 1'b1        ),
  .I  ( clk_bit_pre ),
  .O  ( CLK_BIT     )
);

BUFGCE_DIV #(
  .BUFGCE_DIVIDE  ( 4       ),
  .CE_TYPE        ( "SYNC"  ),
  .HARDSYNC_CLR   ( "FALSE" )
)
u_BUFGCE_DIV2(
  .O              ( CLK_BYTE    ),

  .CE             ( 1'b1        ),
  .CLR            ( ~RST_N      ),
  .I              ( clk_bit_pre )
);


endmodule