data/full_repos/permissive/167489907/Memory/ROM/rom_case_nice.v
data/verilator_xmls/3c5945e9-fce0-426e-80e2-f342952ca37b.xml
module rom_case(out, address);
	output reg [31:0] out;
	input  [15:0] address;
	always @(address) begin
		case (address)





			16'h0000:  out = 32'b11010010100_0000000000000000_01000;
			16'h0001:  out = 32'b1101001101100000_000000_0100001000;

			16'h0002:  out = 32'b11010010100_0000000000001000_01011;
			16'h0003:  out = 32'b1101001101100000_001000_0101101011;

			16'h0004:  out = 32'b11010010100000000000000000100111;


			16'h0005:  out = 32'b1101001101100000_011000_0011100111;
			16'h0006:  out = 32'b11111000000000110000000100000111;
			16'h0007:  out = 32'b11010001000001100101011111100000;
			16'h0008:  out = 32'b11010001000100000000001111100101;
			16'h0009:  out = 32'b10110010000001000110011111100010;
			16'h000a:  out = 32'b10001011000001010000000001000010;
			16'h000b:  out = 32'b10001011000001010000000000000000;
			16'h000c:  out = 32'b10001011000001010000000010100101;
			16'h000d:  out = 32'b10001011000000100000000010100010;
			16'h000e:  out = 32'b11010011011000000000010010100101;
			16'h000f:  out = 32'b10001011000001010000000000000000;
			16'h0010:  out = 32'b11010011011000000000010010100101;
			16'h0011:  out = 32'b10001011000001010000000001000010;
			16'h0012:  out = 32'b11001011000001010000001111100101;
			16'h0013:  out = 32'b10001011000000100000000000000000;
			16'h0014:  out = 32'b10001011000000100000000000000000;
			16'h0015:  out = 32'b11111000000000011000000100000000;
			16'h0016:  out = 32'b11111000000000100000000100000010;
			16'h0017:  out = 32'b11111000000000101000000100000101;
			16'h0018:  out = 32'b10010001000000000000001111100000;
			16'h0019:  out = 32'b10010010000000000000001111100001;
			16'h001a:  out = 32'b11010010000000000000001111100010;
			16'h001b:  out = 32'b10110010000000000000001111100011;
			16'h001c:  out = 32'b10101010000111110000001111100100;
			16'h001d:  out = 32'b10001010000111110000001111100101;
			16'h001e:  out = 32'b10001010000111110000001111100110;
			16'h001f:  out = 32'b11111000010000110000000100000111;
			16'h0020:  out = 32'b11010001000000000000010011100111;
			16'h0021:  out = 32'b10110101111111111111111111000111;
			16'h0022:  out = 32'b11010010100111111111111111100000;
			16'h0023:  out = 32'b11010001000000000000011111100001;
			16'h0024:  out = 32'b11010010100111111111111111100010;
			16'h0025:  out = 32'b11010001000000000000011111100011;
			16'h0026:  out = 32'b11010010100111111111111111100100;
			16'h0027:  out = 32'b11010001000000000000011111100101;
			16'h0028:  out = 32'b11010001000000000000011111100110;
			16'h0029:  out = 32'b11111000010000110000000100000111;
			16'h002a:  out = 32'b11010001000000000000010011100111;
			16'h002b:  out = 32'b10110101111111111111111111000111;
			16'h002c:  out = 32'b11111000010000011000000100000100;
			16'h002d:  out = 32'b11111000010000100000000100000010;
			16'h002e:  out = 32'b11111000010000101000000100000101;
			16'h002f:  out = 32'b10010001000000000000000001000011;
			16'h0030:  out = 32'b10110010000000010000000001100011;
			16'h0031:  out = 32'b11010010100000000000000100000111;
			16'h0032:  out = 32'b11001011000001110000000001100011;
			16'h0033:  out = 32'b11010010100000000000000000100111;
			16'h0034:  out = 32'b11001010000001110000000001100001;
			16'h0035:  out = 32'b11001011000001010000000000100001;
			16'h0036:  out = 32'b10110010000000000000000010000000;
			16'h0037:  out = 32'b11010010100000000000000000000101;
			16'h0038:  out = 32'b11010010100000000000000000000110;
			16'h0039:  out = 32'b11111000010000110000000100000111;
			16'h003a:  out = 32'b11010001000000000000010011100111;
			16'h003b:  out = 32'b10110101111111111111111111000111;
			16'h003c:  out = 32'b11010110000000000000000101100000;
			default: out=32'b11010110000000000000000101100000;
		endcase
	end
endmodule
module rom_case(out, address);

	output reg [31:0] out;
	input  [15:0] address;
	always @(address) begin
		case (address)





			16'h0000:  out = 32'b11010010100_0000000000000000_01000;
			16'h0001:  out = 32'b1101001101100000_000000_0100001000;

			16'h0002:  out = 32'b11010010100_0000000000001000_01011;
			16'h0003:  out = 32'b1101001101100000_001000_0101101011;

			16'h0004:  out = 32'b11010010100000000000000000100111;


			16'h0005:  out = 32'b1101001101100000_011000_0011100111;
			16'h0006:  out = 32'b11111000000000110000000100000111;
			16'h0007:  out = 32'b11010001000001100101011111100000;
			16'h0008:  out = 32'b11010001000100000000001111100101;
			16'h0009:  out = 32'b10110010000001000110011111100010;
			16'h000a:  out = 32'b10001011000001010000000001000010;
			16'h000b:  out = 32'b10001011000001010000000000000000;
			16'h000c:  out = 32'b10001011000001010000000010100101;
			16'h000d:  out = 32'b10001011000000100000000010100010;
			16'h000e:  out = 32'b11010011011000000000010010100101;
			16'h000f:  out = 32'b10001011000001010000000000000000;
			16'h0010:  out = 32'b11010011011000000000010010100101;
			16'h0011:  out = 32'b10001011000001010000000001000010;
			16'h0012:  out = 32'b11001011000001010000001111100101;
			16'h0013:  out = 32'b10001011000000100000000000000000;
			16'h0014:  out = 32'b10001011000000100000000000000000;
			16'h0015:  out = 32'b11111000000000011000000100000000;
			16'h0016:  out = 32'b11111000000000100000000100000010;
			16'h0017:  out = 32'b11111000000000101000000100000101;
			16'h0018:  out = 32'b10010001000000000000001111100000;
			16'h0019:  out = 32'b10010010000000000000001111100001;
			16'h001a:  out = 32'b11010010000000000000001111100010;
			16'h001b:  out = 32'b10110010000000000000001111100011;
			16'h001c:  out = 32'b10101010000111110000001111100100;
			16'h001d:  out = 32'b10001010000111110000001111100101;
			16'h001e:  out = 32'b10001010000111110000001111100110;
			16'h001f:  out = 32'b11111000010000110000000100000111;
			16'h0020:  out = 32'b11010001000000000000010011100111;
			16'h0021:  out = 32'b10110101111111111111111111000111;
			16'h0022:  out = 32'b11010010100111111111111111100000;
			16'h0023:  out = 32'b11010001000000000000011111100001;
			16'h0024:  out = 32'b11010010100111111111111111100010;
			16'h0025:  out = 32'b11010001000000000000011111100011;
			16'h0026:  out = 32'b11010010100111111111111111100100;
			16'h0027:  out = 32'b11010001000000000000011111100101;
			16'h0028:  out = 32'b11010001000000000000011111100110;
			16'h0029:  out = 32'b11111000010000110000000100000111;
			16'h002a:  out = 32'b11010001000000000000010011100111;
			16'h002b:  out = 32'b10110101111111111111111111000111;
			16'h002c:  out = 32'b11111000010000011000000100000100;
			16'h002d:  out = 32'b11111000010000100000000100000010;
			16'h002e:  out = 32'b11111000010000101000000100000101;
			16'h002f:  out = 32'b10010001000000000000000001000011;
			16'h0030:  out = 32'b10110010000000010000000001100011;
			16'h0031:  out = 32'b11010010100000000000000100000111;
			16'h0032:  out = 32'b11001011000001110000000001100011;
			16'h0033:  out = 32'b11010010100000000000000000100111;
			16'h0034:  out = 32'b11001010000001110000000001100001;
			16'h0035:  out = 32'b11001011000001010000000000100001;
			16'h0036:  out = 32'b10110010000000000000000010000000;
			16'h0037:  out = 32'b11010010100000000000000000000101;
			16'h0038:  out = 32'b11010010100000000000000000000110;
			16'h0039:  out = 32'b11111000010000110000000100000111;
			16'h003a:  out = 32'b11010001000000000000010011100111;
			16'h003b:  out = 32'b10110101111111111111111111000111;
			16'h003c:  out = 32'b11010110000000000000000101100000;
			default: out=32'b11010110000000000000000101100000;
		endcase
	end
endmodule