data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v
1: b"%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:26: syntax error, unexpected int, expecting IDENTIFIER or '[' or do or final\n    input wire [6:0] int,\n                     ^~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [31:0] araddr,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:32: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output wire [7:0] arlen,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:33: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [2:0] arsize,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:34: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output wire [1:0] arburst,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:35: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [1:0] arlock,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:36: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [3:0] arcache,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:37: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [2:0] arprot,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:38: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg arvalid,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:39: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input wire arready,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:41: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [3:0] rid,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:42: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [31:0] rdata,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:43: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [1:0] rresp,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:44: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire rlast,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:45: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire rvalid,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:46: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg rready,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:48: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output wire [3:0] awid,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:49: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [31:0] awaddr,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:50: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output wire [7:0] awlen,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:51: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [2:0] awsize,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:52: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output wire [1:0] awburst,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:53: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [1:0] awlock,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:54: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [3:0] awcache,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:55: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [2:0] awprot,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:56: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg awvalid,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:57: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input wire awready,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:59: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [3:0] wid,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:60: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [31:0] wdata,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:61: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output reg [3:0] wstrb,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:62: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output wire wlast,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:63: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg wvalid,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:64: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input wire wready,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:66: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [3:0] bid,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:67: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [1:0] bresp,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:68: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire bvalid,\n    ^~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:69: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg bready,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:72: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output wire [31:0] debug_wb_pc,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:73: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [ 3:0] debug_wb_rf_wen,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:74: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [ 4:0] debug_wb_rf_wnum,\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:75: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [31:0] debug_wb_rf_wdata\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:76: syntax error, unexpected ')', expecting ',' or ';'\n    );\n    ^\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:100: syntax error, unexpected IDENTIFIER\n    pipeline_cpu cpu_core (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:132: syntax error, unexpected assign\n    assign inst_sram_data_valid = (inst_size == 2'b00 && inst_addr[1:0] == 2'b00) ? 4'b0001\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:212: syntax error, unexpected assign\n    assign wid = 4'd0;\n    ^~~~~~\n%Error: data/full_repos/permissive/140999934/CPU/axi_cpu/cpu_axi_interface.v:218: syntax error, unexpected always\n    always @(posedge aclk) \n    ^~~~~~\n%Error: Exiting due to 45 error(s)\n"
module cpu_axi_interface(
    input wire aclk,
    input wire aresetn,
    input wire [6:0] int,
    


    output wire [3:0] arid,
    output reg [31:0] araddr,
    output wire [7:0] arlen,
    output reg [2:0] arsize,
    output wire [1:0] arburst,
    output wire [1:0] arlock,
    output wire [3:0] arcache,
    output wire [2:0] arprot,
    output reg arvalid,
    input wire arready,

    input wire [3:0] rid,
    input wire [31:0] rdata,
    input wire [1:0] rresp,
    input wire rlast,
    input wire rvalid,
    output reg rready,

    output wire [3:0] awid,
    output reg [31:0] awaddr,
    output wire [7:0] awlen,
    output reg [2:0] awsize,
    output wire [1:0] awburst,
    output wire [1:0] awlock,
    output wire [3:0] awcache,
    output wire [2:0] awprot,
    output reg awvalid,
    input wire awready,

    output wire [3:0] wid,
    output reg [31:0] wdata,
    output reg [3:0] wstrb,
    output wire wlast,
    output reg wvalid,
    input wire wready,

    input wire [3:0] bid,
    input wire [1:0] bresp,
    input wire bvalid,
    output reg bready,
    

    output wire [31:0] debug_wb_pc,
    output wire [ 3:0] debug_wb_rf_wen,
    output wire [ 4:0] debug_wb_rf_wnum,
    output wire [31:0] debug_wb_rf_wdata
    );




    wire inst_req;
    wire inst_wr;
    wire [1:0] inst_size;
    wire [31:0] inst_addr;
    wire [31:0] inst_wdata;
    reg [31:0] inst_rdata;
    reg inst_addr_ok;
    reg inst_data_ok;
    

    wire data_req;
    wire data_wr;
    wire [1:0] data_size;
    wire [31:0] data_addr;
    wire [31:0] data_wdata;
    reg [31:0] data_rdata;
    reg data_addr_ok;
    reg data_data_ok;
    
    pipeline_cpu cpu_core (
        .clk        (aclk       ),
        .resetn     (aresetn    ),
        .int        (int        ),
        
        .inst_req   (inst_req   ),
        .inst_wr    (inst_wr    ),
        .inst_size  (inst_size  ),
        .inst_addr  (inst_addr  ),
        .inst_wdata (inst_wdata ),
        .inst_rdata (inst_rdata ),
        .inst_addr_ok(inst_addr_ok),
        .inst_data_ok(inst_data_ok),
        
        .data_req   (data_req   ),
        .data_wr    (data_wr    ),
        .data_size  (data_size  ),
        .data_addr  (data_addr  ),
        .data_wdata (data_wdata ),
        .data_rdata (data_rdata ),
        .data_addr_ok(data_addr_ok),
        .data_data_ok(data_data_ok),
        
        .debug_wb_pc      ( debug_wb_pc     ),
        .debug_wb_rf_wen  ( debug_wb_rf_wen ),
        .debug_wb_rf_wnum ( debug_wb_rf_wnum),
        .debug_wb_rf_wdata(debug_wb_rf_wdata)
    );


    wire [3:0] inst_sram_data_valid;
    wire [3:0] data_sram_data_valid;
    assign inst_sram_data_valid = (inst_size == 2'b00 && inst_addr[1:0] == 2'b00) ? 4'b0001
                                : (inst_size == 2'b00 && inst_addr[1:0] == 2'b01) ? 4'b0010
                                : (inst_size == 2'b00 && inst_addr[1:0] == 2'b10) ? 4'b0100
                                : (inst_size == 2'b00 && inst_addr[1:0] == 2'b11) ? 4'b1000
                                : (inst_size == 2'b01 && inst_addr[1:0] == 2'b00) ? 4'b0011
                                : (inst_size == 2'b01 && inst_addr[1:0] == 2'b10) ? 4'b1100
                                : (inst_size == 2'b10 && inst_addr[1:0] == 2'b00) ? 4'b1111 : 4'b0000;
    assign data_sram_data_valid = (data_size == 2'b00 && data_addr[1:0] == 2'b00) ? 4'b0001
                                : (data_size == 2'b00 && data_addr[1:0] == 2'b01) ? 4'b0010
                                : (data_size == 2'b00 && data_addr[1:0] == 2'b10) ? 4'b0100
                                : (data_size == 2'b00 && data_addr[1:0] == 2'b11) ? 4'b1000
                                : (data_size == 2'b01 && data_addr[1:0] == 2'b00) ? 4'b0011
                                : (data_size == 2'b01 && data_addr[1:0] == 2'b10) ? 4'b1100
                                : (data_size == 2'b10 && data_addr[1:0] == 2'b00) ? 4'b1111 : 4'b0000;
                                
    always @(posedge aclk) begin
        if (inst_addr_ok) begin
            if (inst_wr)
            begin
                case(inst_size)
                    2'b00 : awsize <= 3'b011;
                    2'b01 : awsize <= 3'b100;
                    2'b10 : awsize <= 3'b101;
                    default : awsize <= 3'b000;
                endcase
            end
            else
            begin
                case(inst_size)
                    2'b00 : arsize <= 3'b011;
                    2'b01 : arsize <= 3'b100;
                    2'b10 : arsize <= 3'b101;
                    default : arsize <= 3'b000;
                endcase
            end
        end
        else if (data_addr_ok) begin
            if (data_wr)
            begin
                case(data_size)
                    2'b00 : awsize <= 3'b011;
                    2'b01 : awsize <= 3'b100;
                    2'b10 : awsize <= 3'b101;
                    default : awsize <= 3'b000;
                endcase
            end
            else
            begin
                case(data_size)
                    2'b00 : arsize <= 3'b011;
                    2'b01 : arsize <= 3'b100;
                    2'b10 : arsize <= 3'b101;
                    default : arsize <= 3'b000;
                endcase
            end
        end
    end    




        

    assign arid = 4'd0;
    assign arlen = 8'd0;
    assign arburst = 2'b01;
    assign arlock = 2'd0;
    assign arcache = 4'd0;
    assign arprot = 3'd0;


    assign awid = 4'd0;
    assign awlen = 8'd0;
    assign awburst = 2'b01;
    assign awlock = 2'd0;
    assign awcache = 4'd0;
    assign awprot = 3'd0;
    

    reg [3:0] rstrb;
    assign wid = 4'd0;
    assign wlast = 1'b1;
    
    reg stall;
    reg current_inst_or_data;

    always @(posedge aclk) 
    begin
        if (!aresetn) begin

            awvalid <= 1'b0;
            arvalid <= 1'b0;
            wvalid <= 1'b0;
            bready <= 1'b0;
            rready <= 1'b0;
            stall <= 1'b0;
            
            inst_addr_ok <= 1'b0;
            inst_data_ok <= 1'b0;
            data_addr_ok <= 1'b0;
            data_data_ok <= 1'b0;
        end
        else if (bvalid && bready)
        begin
            bready <= 1'b0;
            stall <= 1'b0;
            if (current_inst_or_data)
            begin
                inst_data_ok <= 1'b1;
            end
            else
            begin
                data_data_ok <= 1'b1;
            end
        end
        else if (rvalid && rready)
        begin
            rready <= 1'b0;
            stall <= 1'b0;
            if (current_inst_or_data)
            begin
                inst_data_ok <= 1'b1;
                if (rstrb[0])
                begin
                    inst_rdata[7:0] <= rdata[7:0];
                end
                else
                begin
                    inst_rdata[7:0] <= 8'd0;
                end
                if (rstrb[1])
                begin
                    inst_rdata[15:8] <= rdata[15:8];
                end
                else
                begin
                    inst_rdata[15:8] <= 8'd0;
                end
                if (rstrb[2])
                begin
                    inst_rdata[23:16] <= rdata[23:16];
                end
                else
                begin
                    inst_rdata[23:16] <= 8'd0;
                end
                if (rstrb[3])
                begin
                    inst_rdata[31:24] <= rdata[31:24];
                end
                else
                begin
                    inst_rdata[31:24] <= 8'd0;
                end
            end
            else
            begin
                data_data_ok <= 1'b1;
                if (rstrb[0])
                begin
                    data_rdata[7:0] <= rdata[7:0];
                end
                else
                begin
                    data_rdata[7:0] <= 8'd0;
                end
                if (rstrb[1])
                begin
                    data_rdata[15:8] <= rdata[15:8];
                end
                else
                begin
                    data_rdata[15:8] <= 8'd0;
                end
                if (rstrb[2])
                begin
                    data_rdata[23:16] <= rdata[23:16];
                end
                else
                begin
                    data_rdata[23:16] <= 8'd0;
                end
                if (rstrb[3])
                begin
                    data_rdata[31:24] <= rdata[31:24];
                end
                else
                begin
                    data_rdata[31:24] <= 8'd0;
                end
            end
        end
        else if ((awready && awvalid) || (wready && wvalid))
        begin
            if (awvalid && awvalid)
            begin
                awvalid <= 1'b0;
            end
            else if (wready && wvalid)
            begin
                wvalid <= 1'b0;
            end
            bready <= 1'b1;
        end
        else if (arready && arvalid)
        begin
            arvalid <= 1'b0;
            rready <= 1'b1;
        end
        else if (data_addr_ok)
        begin
            awaddr <= data_addr;
            wdata <= data_wdata;
            wstrb <= data_sram_data_valid;
            rstrb <= data_sram_data_valid;
            araddr <= data_addr;
            awvalid <= data_wr;
            wvalid <= data_wr;
            arvalid <= ~data_wr;
            data_addr_ok <= 1'b0;
        end
        else if (inst_addr_ok)
        begin
            awaddr <= inst_addr;
            wdata <= inst_wdata;
            wstrb <= inst_sram_data_valid;
            rstrb <= inst_sram_data_valid;
            araddr <= inst_addr;
            awvalid <= inst_wr;
            wvalid <= inst_wr;
            arvalid <= ~inst_wr;
            inst_addr_ok <= 1'b0;
        end
        else if (data_req && data_wr && ~stall)
        begin
            data_addr_ok <= 1'b1;
            inst_data_ok <= 1'b0;
            data_data_ok <= 1'b0;
            stall <= 1'b1;
            current_inst_or_data <= 1'b0;
        end
        else if (inst_req && inst_wr && ~stall)
        begin
            inst_addr_ok <= 1'b1;
            inst_data_ok <= 1'b0;
            data_data_ok <= 1'b0;
            stall <= 1'b1;
            current_inst_or_data <= 1'b1;
        end
        else if (data_req && ~data_wr && ~stall)
        begin
            data_addr_ok <= 1'b1;
            inst_data_ok <= 1'b0;
            data_data_ok <= 1'b0;
            stall <= 1'b1;
            current_inst_or_data <= 1'b0;
        end
        else if (inst_req && ~inst_wr && ~stall)
        begin
            inst_addr_ok <= 1'b1;
            inst_data_ok <= 1'b0;
            data_data_ok <= 1'b0;
            stall <= 1'b1;
            current_inst_or_data <= 1'b1;
        end
        else
        begin
            inst_data_ok <= 1'b0;
            data_data_ok <= 1'b0;
        end
    end


endmodule
module cpu_axi_interface(
    input wire aclk,
    input wire aresetn,
    input wire [6:0] int,
    


    output wire [3:0] arid,
    output reg [31:0] araddr,
    output wire [7:0] arlen,
    output reg [2:0] arsize,
    output wire [1:0] arburst,
    output wire [1:0] arlock,
    output wire [3:0] arcache,
    output wire [2:0] arprot,
    output reg arvalid,
    input wire arready,

    input wire [3:0] rid,
    input wire [31:0] rdata,
    input wire [1:0] rresp,
    input wire rlast,
    input wire rvalid,
    output reg rready,

    output wire [3:0] awid,
    output reg [31:0] awaddr,
    output wire [7:0] awlen,
    output reg [2:0] awsize,
    output wire [1:0] awburst,
    output wire [1:0] awlock,
    output wire [3:0] awcache,
    output wire [2:0] awprot,
    output reg awvalid,
    input wire awready,

    output wire [3:0] wid,
    output reg [31:0] wdata,
    output reg [3:0] wstrb,
    output wire wlast,
    output reg wvalid,
    input wire wready,

    input wire [3:0] bid,
    input wire [1:0] bresp,
    input wire bvalid,
    output reg bready,
    

    output wire [31:0] debug_wb_pc,
    output wire [ 3:0] debug_wb_rf_wen,
    output wire [ 4:0] debug_wb_rf_wnum,
    output wire [31:0] debug_wb_rf_wdata
    );





    wire inst_req;
    wire inst_wr;
    wire [1:0] inst_size;
    wire [31:0] inst_addr;
    wire [31:0] inst_wdata;
    reg [31:0] inst_rdata;
    reg inst_addr_ok;
    reg inst_data_ok;
    

    wire data_req;
    wire data_wr;
    wire [1:0] data_size;
    wire [31:0] data_addr;
    wire [31:0] data_wdata;
    reg [31:0] data_rdata;
    reg data_addr_ok;
    reg data_data_ok;
    
    pipeline_cpu cpu_core (
        .clk        (aclk       ),
        .resetn     (aresetn    ),
        .int        (int        ),
        
        .inst_req   (inst_req   ),
        .inst_wr    (inst_wr    ),
        .inst_size  (inst_size  ),
        .inst_addr  (inst_addr  ),
        .inst_wdata (inst_wdata ),
        .inst_rdata (inst_rdata ),
        .inst_addr_ok(inst_addr_ok),
        .inst_data_ok(inst_data_ok),
        
        .data_req   (data_req   ),
        .data_wr    (data_wr    ),
        .data_size  (data_size  ),
        .data_addr  (data_addr  ),
        .data_wdata (data_wdata ),
        .data_rdata (data_rdata ),
        .data_addr_ok(data_addr_ok),
        .data_data_ok(data_data_ok),
        
        .debug_wb_pc      ( debug_wb_pc     ),
        .debug_wb_rf_wen  ( debug_wb_rf_wen ),
        .debug_wb_rf_wnum ( debug_wb_rf_wnum),
        .debug_wb_rf_wdata(debug_wb_rf_wdata)
    );


    wire [3:0] inst_sram_data_valid;
    wire [3:0] data_sram_data_valid;
    assign inst_sram_data_valid = (inst_size == 2'b00 && inst_addr[1:0] == 2'b00) ? 4'b0001
                                : (inst_size == 2'b00 && inst_addr[1:0] == 2'b01) ? 4'b0010
                                : (inst_size == 2'b00 && inst_addr[1:0] == 2'b10) ? 4'b0100
                                : (inst_size == 2'b00 && inst_addr[1:0] == 2'b11) ? 4'b1000
                                : (inst_size == 2'b01 && inst_addr[1:0] == 2'b00) ? 4'b0011
                                : (inst_size == 2'b01 && inst_addr[1:0] == 2'b10) ? 4'b1100
                                : (inst_size == 2'b10 && inst_addr[1:0] == 2'b00) ? 4'b1111 : 4'b0000;
    assign data_sram_data_valid = (data_size == 2'b00 && data_addr[1:0] == 2'b00) ? 4'b0001
                                : (data_size == 2'b00 && data_addr[1:0] == 2'b01) ? 4'b0010
                                : (data_size == 2'b00 && data_addr[1:0] == 2'b10) ? 4'b0100
                                : (data_size == 2'b00 && data_addr[1:0] == 2'b11) ? 4'b1000
                                : (data_size == 2'b01 && data_addr[1:0] == 2'b00) ? 4'b0011
                                : (data_size == 2'b01 && data_addr[1:0] == 2'b10) ? 4'b1100
                                : (data_size == 2'b10 && data_addr[1:0] == 2'b00) ? 4'b1111 : 4'b0000;
                                
    always @(posedge aclk) begin
        if (inst_addr_ok) begin
            if (inst_wr)
            begin
                case(inst_size)
                    2'b00 : awsize <= 3'b011;
                    2'b01 : awsize <= 3'b100;
                    2'b10 : awsize <= 3'b101;
                    default : awsize <= 3'b000;
                endcase
            end
            else
            begin
                case(inst_size)
                    2'b00 : arsize <= 3'b011;
                    2'b01 : arsize <= 3'b100;
                    2'b10 : arsize <= 3'b101;
                    default : arsize <= 3'b000;
                endcase
            end
        end
        else if (data_addr_ok) begin
            if (data_wr)
            begin
                case(data_size)
                    2'b00 : awsize <= 3'b011;
                    2'b01 : awsize <= 3'b100;
                    2'b10 : awsize <= 3'b101;
                    default : awsize <= 3'b000;
                endcase
            end
            else
            begin
                case(data_size)
                    2'b00 : arsize <= 3'b011;
                    2'b01 : arsize <= 3'b100;
                    2'b10 : arsize <= 3'b101;
                    default : arsize <= 3'b000;
                endcase
            end
        end
    end    




        

    assign arid = 4'd0;
    assign arlen = 8'd0;
    assign arburst = 2'b01;
    assign arlock = 2'd0;
    assign arcache = 4'd0;
    assign arprot = 3'd0;


    assign awid = 4'd0;
    assign awlen = 8'd0;
    assign awburst = 2'b01;
    assign awlock = 2'd0;
    assign awcache = 4'd0;
    assign awprot = 3'd0;
    

    reg [3:0] rstrb;
    assign wid = 4'd0;
    assign wlast = 1'b1;
    
    reg stall;
    reg current_inst_or_data;

    always @(posedge aclk) 
    begin
        if (!aresetn) begin

            awvalid <= 1'b0;
            arvalid <= 1'b0;
            wvalid <= 1'b0;
            bready <= 1'b0;
            rready <= 1'b0;
            stall <= 1'b0;
            
            inst_addr_ok <= 1'b0;
            inst_data_ok <= 1'b0;
            data_addr_ok <= 1'b0;
            data_data_ok <= 1'b0;
        end
        else if (bvalid && bready)
        begin
            bready <= 1'b0;
            stall <= 1'b0;
            if (current_inst_or_data)
            begin
                inst_data_ok <= 1'b1;
            end
            else
            begin
                data_data_ok <= 1'b1;
            end
        end
        else if (rvalid && rready)
        begin
            rready <= 1'b0;
            stall <= 1'b0;
            if (current_inst_or_data)
            begin
                inst_data_ok <= 1'b1;
                if (rstrb[0])
                begin
                    inst_rdata[7:0] <= rdata[7:0];
                end
                else
                begin
                    inst_rdata[7:0] <= 8'd0;
                end
                if (rstrb[1])
                begin
                    inst_rdata[15:8] <= rdata[15:8];
                end
                else
                begin
                    inst_rdata[15:8] <= 8'd0;
                end
                if (rstrb[2])
                begin
                    inst_rdata[23:16] <= rdata[23:16];
                end
                else
                begin
                    inst_rdata[23:16] <= 8'd0;
                end
                if (rstrb[3])
                begin
                    inst_rdata[31:24] <= rdata[31:24];
                end
                else
                begin
                    inst_rdata[31:24] <= 8'd0;
                end
            end
            else
            begin
                data_data_ok <= 1'b1;
                if (rstrb[0])
                begin
                    data_rdata[7:0] <= rdata[7:0];
                end
                else
                begin
                    data_rdata[7:0] <= 8'd0;
                end
                if (rstrb[1])
                begin
                    data_rdata[15:8] <= rdata[15:8];
                end
                else
                begin
                    data_rdata[15:8] <= 8'd0;
                end
                if (rstrb[2])
                begin
                    data_rdata[23:16] <= rdata[23:16];
                end
                else
                begin
                    data_rdata[23:16] <= 8'd0;
                end
                if (rstrb[3])
                begin
                    data_rdata[31:24] <= rdata[31:24];
                end
                else
                begin
                    data_rdata[31:24] <= 8'd0;
                end
            end
        end
        else if ((awready && awvalid) || (wready && wvalid))
        begin
            if (awvalid && awvalid)
            begin
                awvalid <= 1'b0;
            end
            else if (wready && wvalid)
            begin
                wvalid <= 1'b0;
            end
            bready <= 1'b1;
        end
        else if (arready && arvalid)
        begin
            arvalid <= 1'b0;
            rready <= 1'b1;
        end
        else if (data_addr_ok)
        begin
            awaddr <= data_addr;
            wdata <= data_wdata;
            wstrb <= data_sram_data_valid;
            rstrb <= data_sram_data_valid;
            araddr <= data_addr;
            awvalid <= data_wr;
            wvalid <= data_wr;
            arvalid <= ~data_wr;
            data_addr_ok <= 1'b0;
        end
        else if (inst_addr_ok)
        begin
            awaddr <= inst_addr;
            wdata <= inst_wdata;
            wstrb <= inst_sram_data_valid;
            rstrb <= inst_sram_data_valid;
            araddr <= inst_addr;
            awvalid <= inst_wr;
            wvalid <= inst_wr;
            arvalid <= ~inst_wr;
            inst_addr_ok <= 1'b0;
        end
        else if (data_req && data_wr && ~stall)
        begin
            data_addr_ok <= 1'b1;
            inst_data_ok <= 1'b0;
            data_data_ok <= 1'b0;
            stall <= 1'b1;
            current_inst_or_data <= 1'b0;
        end
        else if (inst_req && inst_wr && ~stall)
        begin
            inst_addr_ok <= 1'b1;
            inst_data_ok <= 1'b0;
            data_data_ok <= 1'b0;
            stall <= 1'b1;
            current_inst_or_data <= 1'b1;
        end
        else if (data_req && ~data_wr && ~stall)
        begin
            data_addr_ok <= 1'b1;
            inst_data_ok <= 1'b0;
            data_data_ok <= 1'b0;
            stall <= 1'b1;
            current_inst_or_data <= 1'b0;
        end
        else if (inst_req && ~inst_wr && ~stall)
        begin
            inst_addr_ok <= 1'b1;
            inst_data_ok <= 1'b0;
            data_data_ok <= 1'b0;
            stall <= 1'b1;
            current_inst_or_data <= 1'b1;
        end
        else
        begin
            inst_data_ok <= 1'b0;
            data_data_ok <= 1'b0;
        end
    end


endmodule