data/full_repos/permissive/150331006/src/Down_count.v
1: b'%Warning-WIDTH: data/full_repos/permissive/150331006/src/Down_count.v:14: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'Q\' generates 11 bits.\n                                                                        : ... In instance Down_count\n   count <= Q;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Down_count(KEY,CLK,EN,CLR,Q,DONE);
	input KEY,CLK,EN,CLR;
	input [10:0] Q;
	output reg DONE;
	integer count;
	
	always @(posedge CLK)
	begin
		if (CLR)
			count <= Q;
		else if (EN & KEY)
		begin
			count <= count - 1;
			if (count == 0)
				DONE <= 1;
			else
				DONE <= 0;
		end
	end
endmodule
module Down_count(KEY,CLK,EN,CLR,Q,DONE);

	input KEY,CLK,EN,CLR;
	input [10:0] Q;
	output reg DONE;
	integer count;
	
	always @(posedge CLK)
	begin
		if (CLR)
			count <= Q;
		else if (EN & KEY)
		begin
			count <= count - 1;
			if (count == 0)
				DONE <= 1;
			else
				DONE <= 0;
		end
	end
endmodule