data/full_repos/permissive/146324357/tf_resampler.v
 line:35: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/146324357/tf_resampler.v:16: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/146324357/tf_resampler.v:18: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/146324357/tf_resampler.v:24: Unsupported: Ignoring delay on this delayed statement.\n #20000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/146324357/tf_resampler.v:26: Unsupported: Ignoring delay on this delayed statement.\n #20100;\n ^\n%Error: data/full_repos/permissive/146324357/tf_resampler.v:66: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/146324357/tf_resampler.v:69: syntax error, unexpected \'@\'\n    @(posedge clkin);\n    ^\n%Error: data/full_repos/permissive/146324357/tf_resampler.v:76: syntax error, unexpected \'@\'\n    @(posedge clkout);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/146324357/tf_resampler.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tf_resampler;

real vin;
wire real vout;
reg clkin;
reg clkout;

always
begin
 clkin = 0;
 #5000;
 clkin = 1;
 #5000;
end

always
begin
 clkout = 0;
 #20000;
 clkout = 1;
 #20100;
end

resampler resampler_i(
  .vin(vin),
  .clk(clkout),
  .vout(vout)
);


real freq = 1e9;
real phase = 0.0;
real amplitude = 1.0;
real dt;
real vin_prev;

always @(posedge clkin)
begin
  vin_prev = vin;
  phase = freq*2*3.14159265358979*$realtime*1e-15;
  vin = amplitude*$sin(phase);
  if(vin==vin_prev)
    vin = vin + 1e-12;
end

real vout_compare;
real error;
real sum_sq_error;
real sum_sq_sig;
integer n;

always @(posedge clkout)
begin
  vout_compare = amplitude*$sin(freq*2*3.14159265358979*($realtime-50000.0)*1e-15);
end



initial
begin   
  $dumpvars;
  repeat(1000)
  begin
    @(posedge clkin);
  end    
  sum_sq_error = 0.0;
  sum_sq_sig = 0.0;
  n = 0;
  repeat(100000)
  begin
    @(posedge clkout);
    #1;
    error = vout_compare-vout;
    sum_sq_error = sum_sq_error + error*error;
    sum_sq_sig = sum_sq_sig + vout*vout;
    n = n+1;
  end  
  $display("Mean Squared error = %e",sum_sq_error/(1.0*n));
  $display("Mean Squared sig = %e",sum_sq_sig/(1.0*n));
  $display("SNR after resample is %f dB",10.0*$log10(sum_sq_sig/sum_sq_error));
  $finish;
end

endmodule
module tf_resampler;


real vin;
wire real vout;
reg clkin;
reg clkout;

always
begin
 clkin = 0;
 #5000;
 clkin = 1;
 #5000;
end

always
begin
 clkout = 0;
 #20000;
 clkout = 1;
 #20100;
end

resampler resampler_i(
  .vin(vin),
  .clk(clkout),
  .vout(vout)
);


real freq = 1e9;
real phase = 0.0;
real amplitude = 1.0;
real dt;
real vin_prev;

always @(posedge clkin)
begin
  vin_prev = vin;
  phase = freq*2*3.14159265358979*$realtime*1e-15;
  vin = amplitude*$sin(phase);
  if(vin==vin_prev)
    vin = vin + 1e-12;
end

real vout_compare;
real error;
real sum_sq_error;
real sum_sq_sig;
integer n;

always @(posedge clkout)
begin
  vout_compare = amplitude*$sin(freq*2*3.14159265358979*($realtime-50000.0)*1e-15);
end



initial
begin   
  $dumpvars;
  repeat(1000)
  begin
    @(posedge clkin);
  end    
  sum_sq_error = 0.0;
  sum_sq_sig = 0.0;
  n = 0;
  repeat(100000)
  begin
    @(posedge clkout);
    #1;
    error = vout_compare-vout;
    sum_sq_error = sum_sq_error + error*error;
    sum_sq_sig = sum_sq_sig + vout*vout;
    n = n+1;
  end  
  $display("Mean Squared error = %e",sum_sq_error/(1.0*n));
  $display("Mean Squared sig = %e",sum_sq_sig/(1.0*n));
  $display("SNR after resample is %f dB",10.0*$log10(sum_sq_sig/sum_sq_error));
  $finish;
end

endmodule