data/full_repos/permissive/10136357/hardware/src/alu.v
1: b'%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:26: Cannot find include file: consts.vh\n`include "consts.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.v\n             data/full_repos/permissive/10136357/hardware/src,data/full_repos/permissive/10136357/consts.vh.sv\n             consts.vh\n             consts.vh.v\n             consts.vh.sv\n             obj_dir/consts.vh\n             obj_dir/consts.vh.v\n             obj_dir/consts.vh.sv\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:37: Define or directive not defined: \'`ALU_ADD\'\n   `ALU_ADD:  alu_out = op1 + op2;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:37: syntax error, unexpected \':\', expecting endcase\n   `ALU_ADD:  alu_out = op1 + op2;\n           ^\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:38: Define or directive not defined: \'`ALU_SLL\'\n   `ALU_SLL:  alu_out = op1 << op2;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:39: Define or directive not defined: \'`ALU_SLT\'\n   `ALU_SLT:  alu_out = $signed(op1) < $signed(op2) ? 1 : 0;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:40: Define or directive not defined: \'`ALU_SLTU\'\n   `ALU_SLTU: alu_out = op1 < op2 ? 1 : 0;\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:41: Define or directive not defined: \'`ALU_XOR\'\n   `ALU_XOR:  alu_out = op1 ^ op2;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:42: Define or directive not defined: \'`ALU_SRL\'\n   `ALU_SRL:  alu_out = op1 >> op2;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:43: Define or directive not defined: \'`ALU_SRA\'\n   `ALU_SRA:  alu_out = $signed(op1) >>> op2;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:44: Define or directive not defined: \'`ALU_OR\'\n   `ALU_OR:   alu_out = op1 | op2;\n   ^~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:45: Define or directive not defined: \'`ALU_AND\'\n   `ALU_AND:  alu_out = op1 & op2;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:46: Define or directive not defined: \'`ALU_MUL\'\n   `ALU_MUL:  alu_out = multiplier_result;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:47: Define or directive not defined: \'`ALU_DIV\'\n   `ALU_DIV:  alu_out = $signed(op1) / $signed(op2);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:48: Define or directive not defined: \'`ALU_DIVU\'\n   `ALU_DIVU: alu_out = op1 / op2;\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:49: Define or directive not defined: \'`ALU_REM\'\n   `ALU_REM:  alu_out = $signed(op1) % $signed(op2);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:50: Define or directive not defined: \'`ALU_REMU\'\n   `ALU_REMU: alu_out = op1 % op2;\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:51: Define or directive not defined: \'`ALU_LUI\'\n   `ALU_LUI:  alu_out = op1 << 12;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/10136357/hardware/src/alu.v:52: Define or directive not defined: \'`ALU_NONE\'\n   `ALU_NONE: alu_out = 0;\n   ^~~~~~~~~\n%Error: Cannot continue\n'
module alu (
	output reg [31:0] alu_out,
	input [31:0] op1,
	input [31:0] op2,
	input [31:0] multiplier_result,
	input [4:0] alu_sel
);
	always @ (*) begin
		case (alu_sel)
			`ALU_ADD:  alu_out = op1 + op2;
			`ALU_SLL:  alu_out = op1 << op2;
			`ALU_SLT:  alu_out = $signed(op1) < $signed(op2) ? 1 : 0;
			`ALU_SLTU: alu_out = op1 < op2 ? 1 : 0;
			`ALU_XOR:  alu_out = op1 ^ op2;
			`ALU_SRL:  alu_out = op1 >> op2;
			`ALU_SRA:  alu_out = $signed(op1) >>> op2;
			`ALU_OR:   alu_out = op1 | op2;
			`ALU_AND:  alu_out = op1 & op2;
			`ALU_MUL:  alu_out = multiplier_result;
			`ALU_DIV:  alu_out = $signed(op1) / $signed(op2);
			`ALU_DIVU: alu_out = op1 / op2;
			`ALU_REM:  alu_out = $signed(op1) % $signed(op2);
			`ALU_REMU: alu_out = op1 % op2;
			`ALU_LUI:  alu_out = op1 << 12;
			`ALU_NONE: alu_out = 0;
		endcase
	end

endmodule
module alu (
	output reg [31:0] alu_out,
	input [31:0] op1,
	input [31:0] op2,
	input [31:0] multiplier_result,
	input [4:0] alu_sel
);

	always @ (*) begin
		case (alu_sel)
			`ALU_ADD:  alu_out = op1 + op2;
			`ALU_SLL:  alu_out = op1 << op2;
			`ALU_SLT:  alu_out = $signed(op1) < $signed(op2) ? 1 : 0;
			`ALU_SLTU: alu_out = op1 < op2 ? 1 : 0;
			`ALU_XOR:  alu_out = op1 ^ op2;
			`ALU_SRL:  alu_out = op1 >> op2;
			`ALU_SRA:  alu_out = $signed(op1) >>> op2;
			`ALU_OR:   alu_out = op1 | op2;
			`ALU_AND:  alu_out = op1 & op2;
			`ALU_MUL:  alu_out = multiplier_result;
			`ALU_DIV:  alu_out = $signed(op1) / $signed(op2);
			`ALU_DIVU: alu_out = op1 / op2;
			`ALU_REM:  alu_out = $signed(op1) % $signed(op2);
			`ALU_REMU: alu_out = op1 % op2;
			`ALU_LUI:  alu_out = op1 << 12;
			`ALU_NONE: alu_out = 0;
		endcase
	end

endmodule