data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:14: Cannot find include file: ../../utils/sim/sim.v\n`include "../../utils/sim/sim.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/190755935/src/image/sim,data/full_repos/permissive/190755935/../../utils/sim/sim.v\n             data/full_repos/permissive/190755935/src/image/sim,data/full_repos/permissive/190755935/../../utils/sim/sim.v.v\n             data/full_repos/permissive/190755935/src/image/sim,data/full_repos/permissive/190755935/../../utils/sim/sim.v.sv\n             ../../utils/sim/sim.v\n             ../../utils/sim/sim.v.v\n             ../../utils/sim/sim.v.sv\n             obj_dir/../../utils/sim/sim.v\n             obj_dir/../../utils/sim/sim.v.v\n             obj_dir/../../utils/sim/sim.v.sv\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:16: Cannot find include file: ../../image/rtl/image_defs.v\n`include "../../image/rtl/image_defs.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:21: Define or directive not defined: \'`IS_w\'\n        parameter [`IS_w-1:0] InIS = `IS_DEFAULT,\n                   ^~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:21: Define or directive not defined: \'`IS_DEFAULT\'\n        parameter [`IS_w-1:0] InIS = `IS_DEFAULT,\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:21: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        parameter [`IS_w-1:0] InIS = `IS_DEFAULT,\n                                                ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:22: Define or directive not defined: \'`IS_w\'\n        parameter [`IS_w-1:0] OutIS = `IS_DEFAULT\n                   ^~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:22: Define or directive not defined: \'`IS_DEFAULT\'\n        parameter [`IS_w-1:0] OutIS = `IS_DEFAULT\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:23: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    )();\n    ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:25: Define or directive not defined: \'`OutputDebug\'\n    parameter Output=`OutputDebug;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:25: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    parameter Output=`OutputDebug;\n                                 ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:28: Define or directive not defined: \'`Realtime\'\n    `Realtime\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:31: Define or directive not defined: \'`Clock10MHz\'\n    `Clock10MHz\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:41: syntax error, unexpected \'@\'\n            @( posedge clock );\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n            #2\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n            #2\n            ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:53: Define or directive not defined: \'`Info\'\n            `Info( "    Reset");\n            ^~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:53: syntax error, unexpected \';\'\n            `Info( "    Reset");\n                               ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:71: Define or directive not defined: \'`I_w\'\n    localparam InImageWidth  = `I_w( InIS );\n                               ^~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:72: Define or directive not defined: \'`I_w\'\n    localparam OutImageWidth = `I_w( OutIS );\n                               ^~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:81: syntax error, unexpected IDENTIFIER\n    image_reformat #(\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:96: Define or directive not defined: \'`IS_C0_WIDTH\'\n    localparam InC0Width    = `IS_C0_WIDTH( InIS );\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:97: Define or directive not defined: \'`IS_C1_WIDTH\'\n    localparam InC1Width    = `IS_C1_WIDTH( InIS );\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:98: Define or directive not defined: \'`IS_C2_WIDTH\'\n    localparam InC2Width    = `IS_C2_WIDTH( InIS );\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:99: Define or directive not defined: \'`IS_ALPHA_WIDTH\'\n    localparam InAlphaWidth = `IS_ALPHA_WIDTH( InIS );\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:100: Define or directive not defined: \'`IS_Z_WIDTH\'\n    localparam InZWidth     = `IS_Z_WIDTH( InIS );\n                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:120: syntax error, unexpected assign\n    assign `I_Start( InIS, image_in ) = in_start;\n    ^~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:120: Define or directive not defined: \'`I_Start\'\n    assign `I_Start( InIS, image_in ) = in_start;\n           ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:121: Define or directive not defined: \'`I_Stop\'\n    assign `I_Stop(  InIS, image_in ) = in_stop;\n           ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:122: Define or directive not defined: \'`I_Error\'\n                                                                                  : ... Suggested alternative: \'`error\'\n    assign `I_Error( InIS, image_in ) = in_error;\n           ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:123: Define or directive not defined: \'`I_Valid\'\n    assign `I_Valid( InIS, image_in ) = in_valid;\n           ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:126: Define or directive not defined: \'`I_Request\'\n    assign in_request = `I_Request( InIS, image_in );\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:127: Define or directive not defined: \'`I_Cancel\'\n    assign in_cancel  = `I_Cancel( InIS, image_in );\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:128: Define or directive not defined: \'`I_Ready\'\n    assign in_ready   = `I_Ready( InIS, image_in );\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:132: Define or directive not defined: \'`IS_C0_WIDTH\'\n    localparam OutC0Width    = `IS_C0_WIDTH( OutIS );\n                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:133: Define or directive not defined: \'`IS_C1_WIDTH\'\n    localparam OutC1Width    = `IS_C1_WIDTH( OutIS );\n                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:134: Define or directive not defined: \'`IS_C2_WIDTH\'\n    localparam OutC2Width    = `IS_C2_WIDTH( OutIS );\n                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:135: Define or directive not defined: \'`IS_ALPHA_WIDTH\'\n    localparam OutAlphaWidth = `IS_ALPHA_WIDTH( OutIS );\n                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:136: Define or directive not defined: \'`IS_Z_WIDTH\'\n    localparam OutZWidth     = `IS_Z_WIDTH( OutIS );\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:153: syntax error, unexpected assign\n    assign out_start = `I_Start( OutIS, image_out );\n    ^~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:153: Define or directive not defined: \'`I_Start\'\n    assign out_start = `I_Start( OutIS, image_out );\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:154: Define or directive not defined: \'`I_Stop\'\n    assign out_stop  = `I_Stop( OutIS, image_out );\n                       ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:155: Define or directive not defined: \'`I_Error\'\n                                                                                  : ... Suggested alternative: \'`error\'\n    assign out_error = `I_Error( OutIS, image_out );\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:156: Define or directive not defined: \'`I_Valid\'\n    assign out_valid = `I_Valid( OutIS, image_out );\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:158: Define or directive not defined: \'`I_Request\'\n    assign `I_Request( OutIS, image_out ) = out_request;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:159: Define or directive not defined: \'`I_Cancel\'\n    assign `I_Cancel(  OutIS, image_out ) = out_cancel;\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:160: Define or directive not defined: \'`I_Ready\'\n    assign `I_Ready(   OutIS, image_out ) = out_ready;\n           ^~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:185: Define or directive not defined: \'`InfoDo\'\n            `InfoDo $display( "    Test Initial State" );\n            ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:187: Define or directive not defined: \'`InfoDo\'\n            `InfoDo $display( "        InIS %x", InIS );\n            ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:188: Define or directive not defined: \'`InfoDo\'\n            `InfoDo $display( "             In Format    %d",  `IS_FORMAT( InIS ) );\n            ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:188: Define or directive not defined: \'`IS_FORMAT\'\n            `InfoDo $display( "             In Format    %d",  `IS_FORMAT( InIS ) );\n                                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:189: Define or directive not defined: \'`InfoDo\'\n            `InfoDo $display( "             In C0_w      %d",  `I_C0_w( InIS ) );\n            ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_reformat_tb.v:189: Define or directive not defined: \'`I_C0_w\'\n            `InfoDo $display( "             In C0_w      %d",  `I_C0_w( InIS ) );\n                                                               ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module image_reformat_instance #(
        parameter [`IS_w-1:0] InIS = `IS_DEFAULT,
        parameter [`IS_w-1:0] OutIS = `IS_DEFAULT
    )();

    parameter Output=`OutputDebug;


    `Realtime


    `Clock10MHz

    task i_init;
        begin
        end
    endtask

    task  i_clock;
        begin
            #2
            @( posedge clock );

            #2
            ;
        end
    endtask

    reg  reset;
    task  i_reset;
        begin
            reset = 1;
            i_clock;
            `Info( "    Reset");
            reset = 0;
            i_clock;
        end
    endtask

    task test_init;
        begin
            i_init;
            i_reset;

        end
    endtask





    localparam InImageWidth  = `I_w( InIS );
    localparam OutImageWidth = `I_w( OutIS );





    wire [InImageWidth-1:0]  image_in;
    wire [OutImageWidth-1:0] image_out;

    image_reformat #(
            .InIS( InIS ),
            .OutIS( OutIS )
        ) ir (
            .clock( clock ),
            .reset( reset ),

            .image_in( image_in ),
            .image_out( image_out )
        );





    localparam InC0Width    = `IS_C0_WIDTH( InIS );
    localparam InC1Width    = `IS_C1_WIDTH( InIS );
    localparam InC2Width    = `IS_C2_WIDTH( InIS );
    localparam InAlphaWidth = `IS_ALPHA_WIDTH( InIS );
    localparam InZWidth     = `IS_Z_WIDTH( InIS );


    reg                  in_start;
    reg                  in_stop;
    reg                  in_valid;
    reg                  in_error;

    reg [ InC0Width-1:0 ]    in_c0;
    reg [ InC1Width-1:0 ]    in_c1;
    reg [ InC2Width-1:0 ]    in_c2;
    reg [ InAlphaWidth-1:0 ] in_alpha;
    reg [ InZWidth-1:0 ]     in_z;

    wire                 in_ready;
    wire                 in_request;
    wire                 in_cancel;



    assign `I_Start( InIS, image_in ) = in_start;
    assign `I_Stop(  InIS, image_in ) = in_stop;
    assign `I_Error( InIS, image_in ) = in_error;
    assign `I_Valid( InIS, image_in ) = in_valid;


    assign in_request = `I_Request( InIS, image_in );
    assign in_cancel  = `I_Cancel( InIS, image_in );
    assign in_ready   = `I_Ready( InIS, image_in );



    localparam OutC0Width    = `IS_C0_WIDTH( OutIS );
    localparam OutC1Width    = `IS_C1_WIDTH( OutIS );
    localparam OutC2Width    = `IS_C2_WIDTH( OutIS );
    localparam OutAlphaWidth = `IS_ALPHA_WIDTH( OutIS );
    localparam OutZWidth     = `IS_Z_WIDTH( OutIS );

    wire                 out_start;
    wire                 out_stop;
    wire                 out_valid;
    wire                 out_error;

    wire [ OutC0Width-1:0 ]    out_c0;
    wire [ OutC1Width-1:0 ]    out_c1;
    wire [ OutC2Width-1:0 ]    out_c2;
    wire [ OutAlphaWidth-1:0 ] out_alpha;
    wire [ OutZWidth-1:0 ]     out_z;

    reg                  out_ready;
    reg                  out_request;
    reg                  out_cancel;

    assign out_start = `I_Start( OutIS, image_out );
    assign out_stop  = `I_Stop( OutIS, image_out );
    assign out_error = `I_Error( OutIS, image_out );
    assign out_valid = `I_Valid( OutIS, image_out );

    assign `I_Request( OutIS, image_out ) = out_request;
    assign `I_Cancel(  OutIS, image_out ) = out_cancel;
    assign `I_Ready(   OutIS, image_out ) = out_ready;

    task test_image_init;
        begin
            in_start <= 0;
            in_stop <= 0;
            in_valid <= 0;
            in_error <= 0;
            in_c0 <= 0;
            in_c1 <= 0;
            in_c2 <= 0;
            in_alpha <= 0;
            in_z <= 0;
            out_ready <= 0;
            out_request <= 0;
            out_cancel <= 0;
        end
    endtask





    task test_initial_state(  inout integer AssertErrorCount, inout integer AssertTestCount );
        begin
            `InfoDo $display( "    Test Initial State" );

            `InfoDo $display( "        InIS %x", InIS );
            `InfoDo $display( "             In Format    %d",  `IS_FORMAT( InIS ) );
            `InfoDo $display( "             In C0_w      %d",  `I_C0_w( InIS ) );
            `InfoDo $display( "             In C1_w      %d",  `I_C1_w( InIS ) );
            `InfoDo $display( "             In C2_w      %d",  `I_C2_w( InIS ) );
            `InfoDo $display( "             In Alpha_w   %d",  `I_Alpha_w( InIS ) );
            `InfoDo $display( "             In Z_w       %d",  `I_Z_w( InIS ) );

            `InfoDo $display( "        OutIS %x", OutIS );
            `InfoDo $display( "            Out Format    %d",  `IS_FORMAT( OutIS ) );
            `InfoDo $display( "            Out C0_w      %d",  `I_C0_w( OutIS ) );
            `InfoDo $display( "            Out C1_w      %d",  `I_C1_w( OutIS ) );
            `InfoDo $display( "            Out C2_w      %d",  `I_C2_w( OutIS ) );
            `InfoDo $display( "            Out Alpha_w   %d",  `I_Alpha_w( OutIS ) );
            `InfoDo $display( "            Out Z_w       %d",  `I_Z_w( OutIS ) );

            `InfoDo $display( "       In I_w %d", `I_w( InIS ) );
            `InfoDo $display( "      Out I_w %d", `I_w( OutIS ) );

            i_clock;
            i_clock;

            `AssertEqual( out_start,  0, "Initial states" );
            `AssertEqual( out_stop,   0, "Initial states" );
            `AssertEqual( out_valid,  0, "Initial states" );
            `AssertEqual( out_error,  0, "Initial states" );
            `AssertEqual( in_ready,   0, "Initial states" );
            `AssertEqual( in_request, 0, "Initial states" );
            `AssertEqual( in_cancel,  0, "Initial states" );

        end
    endtask

    task test_in_2_out( inout integer AssertErrorCount, inout integer AssertTestCount );
        begin

            in_start = 0;
            in_stop = 0;
            in_valid = 0;
            in_error = 0;

            #1

            `AssertEqual( out_start, in_start, "Low Out Start" );
            `AssertEqual( out_stop,  in_stop,  "Low Out Stop" );
            `AssertEqual( out_valid, in_start, "Low Out Valid" );
            `AssertEqual( out_error, in_error, "Low Out Error" );

            in_start = 1;
            in_stop = 1;
            in_valid = 1;
            in_error = 1;

            #1

            `AssertEqual( out_start, in_start, "High Out Start" );
            `AssertEqual( out_stop,  in_stop,  "High Out Stop" );
            `AssertEqual( out_valid, in_start, "High Out Valid" );
            `AssertEqual( out_error, in_error, "High Out Error" );

        end
    endtask

    task test_out_2_in( inout integer AssertErrorCount, inout integer AssertTestCount );
        begin

            out_ready = 0;
            out_request = 0;
            out_cancel = 0;

            #1

            `AssertEqual( in_ready,   out_ready,   "Low Out Ready" );
            `AssertEqual( in_request, out_request, "Low Out Request" );
            `AssertEqual( in_cancel,  out_cancel,  "Low Out Cancel" );

            out_ready = 1;
            out_request = 1;
            out_cancel = 1;

            #1

            `AssertEqual( in_ready,   out_ready,   "High Out Ready" );
            `AssertEqual( in_request, out_request, "High Out Request" );
            `AssertEqual( in_cancel,  out_cancel,  "High Out Cancel" );

        end
    endtask

endmodule
module image_reformat_instance #(
        parameter [`IS_w-1:0] InIS = `IS_DEFAULT,
        parameter [`IS_w-1:0] OutIS = `IS_DEFAULT
    )();


    parameter Output=`OutputDebug;


    `Realtime


    `Clock10MHz

    task i_init;
        begin
        end
    endtask

    task  i_clock;
        begin
            #2
            @( posedge clock );

            #2
            ;
        end
    endtask

    reg  reset;
    task  i_reset;
        begin
            reset = 1;
            i_clock;
            `Info( "    Reset");
            reset = 0;
            i_clock;
        end
    endtask

    task test_init;
        begin
            i_init;
            i_reset;

        end
    endtask





    localparam InImageWidth  = `I_w( InIS );
    localparam OutImageWidth = `I_w( OutIS );





    wire [InImageWidth-1:0]  image_in;
    wire [OutImageWidth-1:0] image_out;

    image_reformat #(
            .InIS( InIS ),
            .OutIS( OutIS )
        ) ir (
            .clock( clock ),
            .reset( reset ),

            .image_in( image_in ),
            .image_out( image_out )
        );





    localparam InC0Width    = `IS_C0_WIDTH( InIS );
    localparam InC1Width    = `IS_C1_WIDTH( InIS );
    localparam InC2Width    = `IS_C2_WIDTH( InIS );
    localparam InAlphaWidth = `IS_ALPHA_WIDTH( InIS );
    localparam InZWidth     = `IS_Z_WIDTH( InIS );


    reg                  in_start;
    reg                  in_stop;
    reg                  in_valid;
    reg                  in_error;

    reg [ InC0Width-1:0 ]    in_c0;
    reg [ InC1Width-1:0 ]    in_c1;
    reg [ InC2Width-1:0 ]    in_c2;
    reg [ InAlphaWidth-1:0 ] in_alpha;
    reg [ InZWidth-1:0 ]     in_z;

    wire                 in_ready;
    wire                 in_request;
    wire                 in_cancel;



    assign `I_Start( InIS, image_in ) = in_start;
    assign `I_Stop(  InIS, image_in ) = in_stop;
    assign `I_Error( InIS, image_in ) = in_error;
    assign `I_Valid( InIS, image_in ) = in_valid;


    assign in_request = `I_Request( InIS, image_in );
    assign in_cancel  = `I_Cancel( InIS, image_in );
    assign in_ready   = `I_Ready( InIS, image_in );



    localparam OutC0Width    = `IS_C0_WIDTH( OutIS );
    localparam OutC1Width    = `IS_C1_WIDTH( OutIS );
    localparam OutC2Width    = `IS_C2_WIDTH( OutIS );
    localparam OutAlphaWidth = `IS_ALPHA_WIDTH( OutIS );
    localparam OutZWidth     = `IS_Z_WIDTH( OutIS );

    wire                 out_start;
    wire                 out_stop;
    wire                 out_valid;
    wire                 out_error;

    wire [ OutC0Width-1:0 ]    out_c0;
    wire [ OutC1Width-1:0 ]    out_c1;
    wire [ OutC2Width-1:0 ]    out_c2;
    wire [ OutAlphaWidth-1:0 ] out_alpha;
    wire [ OutZWidth-1:0 ]     out_z;

    reg                  out_ready;
    reg                  out_request;
    reg                  out_cancel;

    assign out_start = `I_Start( OutIS, image_out );
    assign out_stop  = `I_Stop( OutIS, image_out );
    assign out_error = `I_Error( OutIS, image_out );
    assign out_valid = `I_Valid( OutIS, image_out );

    assign `I_Request( OutIS, image_out ) = out_request;
    assign `I_Cancel(  OutIS, image_out ) = out_cancel;
    assign `I_Ready(   OutIS, image_out ) = out_ready;

    task test_image_init;
        begin
            in_start <= 0;
            in_stop <= 0;
            in_valid <= 0;
            in_error <= 0;
            in_c0 <= 0;
            in_c1 <= 0;
            in_c2 <= 0;
            in_alpha <= 0;
            in_z <= 0;
            out_ready <= 0;
            out_request <= 0;
            out_cancel <= 0;
        end
    endtask





    task test_initial_state(  inout integer AssertErrorCount, inout integer AssertTestCount );
        begin
            `InfoDo $display( "    Test Initial State" );

            `InfoDo $display( "        InIS %x", InIS );
            `InfoDo $display( "             In Format    %d",  `IS_FORMAT( InIS ) );
            `InfoDo $display( "             In C0_w      %d",  `I_C0_w( InIS ) );
            `InfoDo $display( "             In C1_w      %d",  `I_C1_w( InIS ) );
            `InfoDo $display( "             In C2_w      %d",  `I_C2_w( InIS ) );
            `InfoDo $display( "             In Alpha_w   %d",  `I_Alpha_w( InIS ) );
            `InfoDo $display( "             In Z_w       %d",  `I_Z_w( InIS ) );

            `InfoDo $display( "        OutIS %x", OutIS );
            `InfoDo $display( "            Out Format    %d",  `IS_FORMAT( OutIS ) );
            `InfoDo $display( "            Out C0_w      %d",  `I_C0_w( OutIS ) );
            `InfoDo $display( "            Out C1_w      %d",  `I_C1_w( OutIS ) );
            `InfoDo $display( "            Out C2_w      %d",  `I_C2_w( OutIS ) );
            `InfoDo $display( "            Out Alpha_w   %d",  `I_Alpha_w( OutIS ) );
            `InfoDo $display( "            Out Z_w       %d",  `I_Z_w( OutIS ) );

            `InfoDo $display( "       In I_w %d", `I_w( InIS ) );
            `InfoDo $display( "      Out I_w %d", `I_w( OutIS ) );

            i_clock;
            i_clock;

            `AssertEqual( out_start,  0, "Initial states" );
            `AssertEqual( out_stop,   0, "Initial states" );
            `AssertEqual( out_valid,  0, "Initial states" );
            `AssertEqual( out_error,  0, "Initial states" );
            `AssertEqual( in_ready,   0, "Initial states" );
            `AssertEqual( in_request, 0, "Initial states" );
            `AssertEqual( in_cancel,  0, "Initial states" );

        end
    endtask

    task test_in_2_out( inout integer AssertErrorCount, inout integer AssertTestCount );
        begin

            in_start = 0;
            in_stop = 0;
            in_valid = 0;
            in_error = 0;

            #1

            `AssertEqual( out_start, in_start, "Low Out Start" );
            `AssertEqual( out_stop,  in_stop,  "Low Out Stop" );
            `AssertEqual( out_valid, in_start, "Low Out Valid" );
            `AssertEqual( out_error, in_error, "Low Out Error" );

            in_start = 1;
            in_stop = 1;
            in_valid = 1;
            in_error = 1;

            #1

            `AssertEqual( out_start, in_start, "High Out Start" );
            `AssertEqual( out_stop,  in_stop,  "High Out Stop" );
            `AssertEqual( out_valid, in_start, "High Out Valid" );
            `AssertEqual( out_error, in_error, "High Out Error" );

        end
    endtask

    task test_out_2_in( inout integer AssertErrorCount, inout integer AssertTestCount );
        begin

            out_ready = 0;
            out_request = 0;
            out_cancel = 0;

            #1

            `AssertEqual( in_ready,   out_ready,   "Low Out Ready" );
            `AssertEqual( in_request, out_request, "Low Out Request" );
            `AssertEqual( in_cancel,  out_cancel,  "Low Out Cancel" );

            out_ready = 1;
            out_request = 1;
            out_cancel = 1;

            #1

            `AssertEqual( in_ready,   out_ready,   "High Out Ready" );
            `AssertEqual( in_request, out_request, "High Out Request" );
            `AssertEqual( in_cancel,  out_cancel,  "High Out Cancel" );

        end
    endtask

endmodule