data/full_repos/permissive/156417892/hdl/Execute/ALUexec/ALUexec.v
1: b'%Warning-WIDTH: data/full_repos/permissive/156417892/hdl/Execute/ALUexec/ALUexec.v:18: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s XOR generates 32 bits.\n                                                                                     : ... In instance ALUexec\n      zero = !(iA ^ iB);\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ALUexec(clk,
               iA,
               iB,
               iALUctrl,
               res,
               zero);
                  
   input [31:0] iA, iB;
   input [2:0] iALUctrl;
   output reg zero;
   output reg [31:0] res;

   input clk;
    
   always @(posedge clk) begin
      zero = !(iA ^ iB);

      case(iALUctrl)
         3'b010: res = iA + iB;
         3'b110: res = iA - iB;
         3'b000: res = iA & iB;
         3'b001: res = iA | iB;
         3'b111: res = (iA < iB) ? 32'h1:32'h0;
         default: res = 32'hxxxxxxxx;
      endcase
   end
endmodule
module ALUexec(clk,
               iA,
               iB,
               iALUctrl,
               res,
               zero);

                  
   input [31:0] iA, iB;
   input [2:0] iALUctrl;
   output reg zero;
   output reg [31:0] res;

   input clk;
    
   always @(posedge clk) begin
      zero = !(iA ^ iB);

      case(iALUctrl)
         3'b010: res = iA + iB;
         3'b110: res = iA - iB;
         3'b000: res = iA & iB;
         3'b001: res = iA | iB;
         3'b111: res = (iA < iB) ? 32'h1:32'h0;
         default: res = 32'hxxxxxxxx;
      endcase
   end
endmodule