data/full_repos/permissive/13953309/NW_fifo.v
 line:103: before: "typedef"
1: b"%Error: data/full_repos/permissive/13953309/NW_fifo.v:110: syntax error, unexpected IDENTIFIER, expecting '.' or ';'\ntypedef flit_t fifo_elements_t;\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:134: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:135: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t data_out, second_data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:275: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:276: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t data_out, second_data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:513: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:514: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:515: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t second_data_out;\n                             ^~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module fifo_flags (push, pop, flags, clk, rst_n);
   input push, pop;
   output fifov_flags_t flags;
   input clk, rst_n;
   
   parameter size = 8;
   parameter init_fifo_contents = 0;

   reg [size:0]   counter;

   logic 	  was_push, was_pop;

   fifov_flags_t flags_reg;
   logic 	  add, sub, same;

   logic 	  fast_empty;
   


   always@(posedge clk) begin
      if (!rst_n) begin
	 



	 if (init_fifo_contents==2) begin

	    counter<={{(size-1){1'b0}},2'b10};
	 end else if (init_fifo_contents==1) begin

	    counter<={2'b01,{(size-1){1'b0}}}; 
	 end else begin

	    counter<={{size{1'b0}},1'b1};
	 end

	 was_push<=1'b0;
	 was_pop<=1'b0;

	 fast_empty <=1'b1;
	 
      end else begin
 	 if (add) begin
	    assert (counter!={1'b1,{size{1'b0}}}) else $fatal;
	    counter <= {counter[size-1:0], 1'b0};
	 end else if (sub) begin
	    assert (counter!={{size{1'b0}},1'b1}) else $fatal;
	    counter <= {1'b0, counter[size:1]};
	 end
	 
	 assert (counter!=0) else $fatal;

	 was_push<=push;
	 was_pop<=pop;

	 assert (push!==1'bx) else $fatal;
	 assert (pop!==1'bx) else $fatal;

	 fast_empty <= (flags.empty && !push && !pop) || (flags.nearly_empty && pop && !push);
	 
      end
      
   end

   assign add = was_push && !was_pop;
   assign sub = was_pop && !was_push;
   assign same = !(add || sub);
   
   assign flags.full = (counter[size] && !sub) || (counter[size-1] && add);
   assign flags.empty = (counter[0] && !add) || (counter[1] && sub);

   assign flags.nearly_full = (counter[size-1:0] && same) || (counter[size] && sub) || (counter[size-2] && add);
   assign flags.nearly_empty = (counter[1] && same) || (counter[0] && add) || (counter[2] && sub);
    
   assign flags.fast_empty = fast_empty;



endmodule
module fifo_flags (push, pop, flags, clk, rst_n);

   input push, pop;
   output fifov_flags_t flags;
   input clk, rst_n;
   
   parameter size = 8;
   parameter init_fifo_contents = 0;

   reg [size:0]   counter;

   logic 	  was_push, was_pop;

   fifov_flags_t flags_reg;
   logic 	  add, sub, same;

   logic 	  fast_empty;
   


   always@(posedge clk) begin
      if (!rst_n) begin
	 



	 if (init_fifo_contents==2) begin

	    counter<={{(size-1){1'b0}},2'b10};
	 end else if (init_fifo_contents==1) begin

	    counter<={2'b01,{(size-1){1'b0}}}; 
	 end else begin

	    counter<={{size{1'b0}},1'b1};
	 end

	 was_push<=1'b0;
	 was_pop<=1'b0;

	 fast_empty <=1'b1;
	 
      end else begin
 	 if (add) begin
	    assert (counter!={1'b1,{size{1'b0}}}) else $fatal;
	    counter <= {counter[size-1:0], 1'b0};
	 end else if (sub) begin
	    assert (counter!={{size{1'b0}},1'b1}) else $fatal;
	    counter <= {1'b0, counter[size:1]};
	 end
	 
	 assert (counter!=0) else $fatal;

	 was_push<=push;
	 was_pop<=pop;

	 assert (push!==1'bx) else $fatal;
	 assert (pop!==1'bx) else $fatal;

	 fast_empty <= (flags.empty && !push && !pop) || (flags.nearly_empty && pop && !push);
	 
      end
      
   end

   assign add = was_push && !was_pop;
   assign sub = was_pop && !was_push;
   assign same = !(add || sub);
   
   assign flags.full = (counter[size] && !sub) || (counter[size-1] && add);
   assign flags.empty = (counter[0] && !add) || (counter[1] && sub);

   assign flags.nearly_full = (counter[size-1:0] && same) || (counter[size] && sub) || (counter[size-2] && add);
   assign flags.nearly_empty = (counter[1] && same) || (counter[0] && add) || (counter[2] && sub);
    
   assign flags.fast_empty = fast_empty;



endmodule