data/full_repos/permissive/116468596/vgaControlMod.v
1: b"%Error: data/full_repos/permissive/116468596/vgaControlMod.v:36: Cannot find file containing module: 'tenBitCount'\n    tenBitCount horizontal (.clk(clk), .enable(enable), .up(up), .down(1'b0), .LD(LD), .reset(hReset), .loadD(loadD), .outQ(hOutQ), .TC(TC));\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/tenBitCount\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/tenBitCount.v\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/tenBitCount.sv\n             tenBitCount\n             tenBitCount.v\n             tenBitCount.sv\n             obj_dir/tenBitCount\n             obj_dir/tenBitCount.v\n             obj_dir/tenBitCount.sv\n%Error: data/full_repos/permissive/116468596/vgaControlMod.v:37: Cannot find file containing module: 'tenBitCountY'\n    tenBitCountY vertical (.clk(clk), .enable(TC), .up(up), .down(1'b0), .LD(LD), .reset(vReset), .loadD(loadD), .outQ(vOutQ));\n    ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module vgaControlMod(
    input clk, enable, up, LD,
    input [9:0] loadD,
    output Hsync, Vsync, activeRegion,
    output [9:0] hOutQ, 
    output [9:0] vOutQ,
    output goodWall, topWall, bottomWall, leftWall, rightWall,
    output greenSquare,
    output frame
    );
    wire topgreenWall;
    wire hReset, vReset;
    wire TC;
    
    tenBitCount horizontal (.clk(clk), .enable(enable), .up(up), .down(1'b0), .LD(LD), .reset(hReset), .loadD(loadD), .outQ(hOutQ), .TC(TC));
    tenBitCountY vertical (.clk(clk), .enable(TC), .up(up), .down(1'b0), .LD(LD), .reset(vReset), .loadD(loadD), .outQ(vOutQ));
    assign activeRegion = ( (hOutQ > 10'd0) & (hOutQ < 10'd639) & (vOutQ > 10'd0) & (vOutQ < 10'd479) );
    assign hReset = ( hOutQ == 10'd799);
    assign vReset = ( vOutQ == 10'd524 & hOutQ == 10'd799);
    assign Hsync = (hOutQ < 10'd655) | (hOutQ > 10'd750); 
    assign Vsync = (vOutQ < 10'd489) | (vOutQ > 10'd490);
     
    assign topWall = ((hOutQ >= 10'd0) & (hOutQ <= 10'd639)) & ((vOutQ >= 10'd0) & (vOutQ <= 10'd8)); 
    assign bottomWall = ((hOutQ >= 10'd0) & (hOutQ <= 10'd639)) & ((vOutQ >= 10'd471) & (vOutQ <= 10'd479)); 
    assign leftWall = ((hOutQ >= 10'd0) & (hOutQ <= 10'd8)) & ((vOutQ >= 10'd0) & (vOutQ <= 10'd479)); 
    assign rightWall = ((hOutQ >= 10'd631) & (hOutQ <= 10'd639)) & ((vOutQ >= 10'd0) & (vOutQ <= 10'd479)); 


    assign goodWall = topWall | bottomWall | leftWall | rightWall;
    assign frame = ( (hOutQ == 10'd755) & (vOutQ == 10'd0) );
                 
endmodule
module vgaControlMod(
    input clk, enable, up, LD,
    input [9:0] loadD,
    output Hsync, Vsync, activeRegion,
    output [9:0] hOutQ, 
    output [9:0] vOutQ,
    output goodWall, topWall, bottomWall, leftWall, rightWall,
    output greenSquare,
    output frame
    );

    wire topgreenWall;
    wire hReset, vReset;
    wire TC;
    
    tenBitCount horizontal (.clk(clk), .enable(enable), .up(up), .down(1'b0), .LD(LD), .reset(hReset), .loadD(loadD), .outQ(hOutQ), .TC(TC));
    tenBitCountY vertical (.clk(clk), .enable(TC), .up(up), .down(1'b0), .LD(LD), .reset(vReset), .loadD(loadD), .outQ(vOutQ));
    assign activeRegion = ( (hOutQ > 10'd0) & (hOutQ < 10'd639) & (vOutQ > 10'd0) & (vOutQ < 10'd479) );
    assign hReset = ( hOutQ == 10'd799);
    assign vReset = ( vOutQ == 10'd524 & hOutQ == 10'd799);
    assign Hsync = (hOutQ < 10'd655) | (hOutQ > 10'd750); 
    assign Vsync = (vOutQ < 10'd489) | (vOutQ > 10'd490);
     
    assign topWall = ((hOutQ >= 10'd0) & (hOutQ <= 10'd639)) & ((vOutQ >= 10'd0) & (vOutQ <= 10'd8)); 
    assign bottomWall = ((hOutQ >= 10'd0) & (hOutQ <= 10'd639)) & ((vOutQ >= 10'd471) & (vOutQ <= 10'd479)); 
    assign leftWall = ((hOutQ >= 10'd0) & (hOutQ <= 10'd8)) & ((vOutQ >= 10'd0) & (vOutQ <= 10'd479)); 
    assign rightWall = ((hOutQ >= 10'd631) & (hOutQ <= 10'd639)) & ((vOutQ >= 10'd0) & (vOutQ <= 10'd479)); 


    assign goodWall = topWall | bottomWall | leftWall | rightWall;
    assign frame = ( (hOutQ == 10'd755) & (vOutQ == 10'd0) );
                 
endmodule