data/full_repos/permissive/135852214/Verilog/rfa_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/rfa_sim.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/rfa_sim.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/rfa_sim.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/rfa_sim.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/135852214/Verilog/rfa_sim.v:34: Cannot find file containing module: \'RFA\'\n RFA uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/RFA\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/RFA.v\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/RFA.sv\n             RFA\n             RFA.v\n             RFA.sv\n             obj_dir/RFA\n             obj_dir/RFA.v\n             obj_dir/RFA.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rfa_sim;


	reg [6:0] in;


	wire [6:0] out;


	RFA uut (
		.in(in), 
		.out(out)
	);

	initial begin

		in = 0;

		#100;

		in = 7'b1110000;
		#100;
		in = 7'b1001100;
		#100;
		in = 7'b0111100;
		#100;
		in = 7'b0101010;
		
	end
      
endmodule
module rfa_sim;



	reg [6:0] in;


	wire [6:0] out;


	RFA uut (
		.in(in), 
		.out(out)
	);

	initial begin

		in = 0;

		#100;

		in = 7'b1110000;
		#100;
		in = 7'b1001100;
		#100;
		in = 7'b0111100;
		#100;
		in = 7'b0101010;
		
	end
      
endmodule