data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/EnablePC_Pipeline.v
data/verilator_xmls/588a7017-20c0-4cb7-87ff-c1357bb9eb4b.xml
module EnablePC_Pipeline (
        input syscall,
        input show, 
        input rst,
        input go,
        input clk,
        output pc_enable
    );
    wire enable_in;
    wire rst_in;
    reg pc_enable_out;

    initial begin
        pc_enable_out = 0;
    end

    assign enable_in = syscall & ~show;

    assign rst_in = rst | go;

    assign pc_enable = ~pc_enable_out;

    always @(negedge clk or posedge rst_in) begin
        if (rst_in == 1) begin
            pc_enable_out = 0;
        end
        else if (enable_in != 0) begin
            pc_enable_out <= syscall;
        end
    end

endmodule
module EnablePC_Pipeline (
        input syscall,
        input show, 
        input rst,
        input go,
        input clk,
        output pc_enable
    );

    wire enable_in;
    wire rst_in;
    reg pc_enable_out;

    initial begin
        pc_enable_out = 0;
    end

    assign enable_in = syscall & ~show;

    assign rst_in = rst | go;

    assign pc_enable = ~pc_enable_out;

    always @(negedge clk or posedge rst_in) begin
        if (rst_in == 1) begin
            pc_enable_out = 0;
        end
        else if (enable_in != 0) begin
            pc_enable_out <= syscall;
        end
    end

endmodule