data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_sync_ring_128_2.sv
 line:6: before: "-"
1: b"%Error: data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_sync_ring_128_2.sv:42: Define or directive not defined: '`TX_READ_ADDR_WIDTH'\n   input [`TX_READ_ADDR_WIDTH-1:0]  rd_address;\n          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_sync_ring_128_2.sv:48: Define or directive not defined: '`TX_WRITE_ADDR_WIDTH'\n   logic [`TX_WRITE_ADDR_WIDTH-1:0]  mapped_read_address;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/shared/circbuf/sonic_sync_ring_128_2.sv:50: Define or directive not defined: '`TX_READ_ADDR_WIDTH'\n   assign mapped_read_address = {rd_address[`TX_READ_ADDR_WIDTH-1:6], rd_address[4:0]};\n                                            ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module sonic_sync_ring_128_2 (

   data_out,

   data_in, wren, rd_clock, wr_clock, wr_address, rd_address
   ) ;

   input [127:0] data_in;
   input 	 wren;
   input 	 rd_clock;
   input 	 wr_clock;
   input [8:0] 	 wr_address;
   input [`TX_READ_ADDR_WIDTH-1:0]  rd_address;
   output [1:0]  data_out;

   logic [1:0] 	 data_out_ms, data_out_ls;
   logic 	 data_sel;
   logic 	 data_sel_r;
   logic [`TX_WRITE_ADDR_WIDTH-1:0]  mapped_read_address;

   assign mapped_read_address = {rd_address[`TX_READ_ADDR_WIDTH-1:6], rd_address[4:0]};


   always @ ( posedge rd_clock ) begin
      data_sel <= rd_address[5];

   end
   
   sonic_dpram_async_64_2 top_half (.data(data_in[127:64]),
				    .wrclock(wr_clock),
				    .rdclock(rd_clock),
				    .rdaddress(mapped_read_address),
				    .wraddress(wr_address),
				    .wren(wren),
				    .q(data_out_ms)
				    );

   sonic_dpram_async_64_2 bot_half (.data(data_in[63:0]),
				    .wrclock(wr_clock),
				    .rdclock(rd_clock),
				    .rdaddress(mapped_read_address),
				    .wraddress(wr_address),
				    .wren(wren),
				    .q(data_out_ls)
				    );
   
   assign data_out = (data_sel) ? data_out_ms : data_out_ls;
      
endmodule
module sonic_sync_ring_128_2 (

   data_out,

   data_in, wren, rd_clock, wr_clock, wr_address, rd_address
   ) ;


   input [127:0] data_in;
   input 	 wren;
   input 	 rd_clock;
   input 	 wr_clock;
   input [8:0] 	 wr_address;
   input [`TX_READ_ADDR_WIDTH-1:0]  rd_address;
   output [1:0]  data_out;

   logic [1:0] 	 data_out_ms, data_out_ls;
   logic 	 data_sel;
   logic 	 data_sel_r;
   logic [`TX_WRITE_ADDR_WIDTH-1:0]  mapped_read_address;

   assign mapped_read_address = {rd_address[`TX_READ_ADDR_WIDTH-1:6], rd_address[4:0]};


   always @ ( posedge rd_clock ) begin
      data_sel <= rd_address[5];

   end
   
   sonic_dpram_async_64_2 top_half (.data(data_in[127:64]),
				    .wrclock(wr_clock),
				    .rdclock(rd_clock),
				    .rdaddress(mapped_read_address),
				    .wraddress(wr_address),
				    .wren(wren),
				    .q(data_out_ms)
				    );

   sonic_dpram_async_64_2 bot_half (.data(data_in[63:0]),
				    .wrclock(wr_clock),
				    .rdclock(rd_clock),
				    .rdaddress(mapped_read_address),
				    .wraddress(wr_address),
				    .wren(wren),
				    .q(data_out_ls)
				    );
   
   assign data_out = (data_sel) ? data_out_ms : data_out_ls;
      
endmodule