data/full_repos/permissive/19572582/Lab4/lab4_part1.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:160: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'lab4_part1\'\nmodule lab4_part1 (SW, LEDG, HEX3, HEX2, HEX1, HEX0, KEY);\n       ^~~~~~~~~~\n                                                                            : ... Top module \'b2d_ssd\'\nmodule b2d_ssd (X, SSD);\n       ^~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:181: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output reg [0:6] SSD;\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:48: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX3, HEX2, HEX1, HEX0;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:55: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab4_part1\n hex_ssd H0 (Q[3:0], HEX0);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:56: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab4_part1\n hex_ssd H1 (Q[7:4], HEX1);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:57: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab4_part1\n hex_ssd H2 (Q[11:8], HEX2);\n              ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:58: Input port connection \'BIN\' expects 16 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab4_part1\n hex_ssd H3 (Q[15:12], HEX3);\n              ^\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab4/lab4_part1.v:162: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output reg [0:6] SSD;\n             ^\n%Error: Exiting due to 8 warning(s)\n'
module lab4_part1 (SW, LEDG, HEX3, HEX2, HEX1, HEX0, KEY);
	input [3:0] SW;
	input [3:0] KEY;
	
	output [7:0] LEDG;
	output [0:6] HEX3, HEX2, HEX1, HEX0;

	wire [15:0] Q;
	wire [3:0] Q2;
		
	counter_16bit C0 (SW[1], KEY[0], SW[0], Q);
	
	hex_ssd H0 (Q[3:0], HEX0);
	hex_ssd H1 (Q[7:4], HEX1);
	hex_ssd H2 (Q[11:8], HEX2);
	hex_ssd H3 (Q[15:12], HEX3);
		
	counter_4bit C1 (SW[1], KEY[0], SW[0], Q2);
	assign LEDG[3:0] = Q2;
  
endmodule
module lab4_part1 (SW, LEDG, HEX3, HEX2, HEX1, HEX0, KEY);

	input [3:0] SW;
	input [3:0] KEY;
	
	output [7:0] LEDG;
	output [0:6] HEX3, HEX2, HEX1, HEX0;

	wire [15:0] Q;
	wire [3:0] Q2;
		
	counter_16bit C0 (SW[1], KEY[0], SW[0], Q);
	
	hex_ssd H0 (Q[3:0], HEX0);
	hex_ssd H1 (Q[7:4], HEX1);
	hex_ssd H2 (Q[11:8], HEX2);
	hex_ssd H3 (Q[15:12], HEX3);
		
	counter_4bit C1 (SW[1], KEY[0], SW[0], Q2);
	assign LEDG[3:0] = Q2;
  
endmodule