data/full_repos/permissive/100331186/tarea4/modulos/registro4bits.v
1: b"%Error: data/full_repos/permissive/100331186/tarea4/modulos/registro4bits.v:25: Duplicate declaration of signal: 's_out'\n                                                                              : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire clkenb,s_out;\n              ^~~~~\n        data/full_repos/permissive/100331186/tarea4/modulos/registro4bits.v:21: ... Location of original declaration\n  output s_out         \n         ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module registro4bits (
  input        clk,
  input        enb,


  input        dir,


  input        s_in,
  input  [1:0] modo,



  input  [3:0] d,
  output [3:0] q,
  output s_out
);
  parameter bits = 4;
  wire socMSBout, socLSBout;
  wire clkenb,s_out;

  serialOcontiguo socMSB(
    .usual(q[0]),
    .s_in(s_in),
    .modo(modo),
    .out(socMSBout)
  );

  serialOcontiguo socLSB(
    .usual(q[3]),
    .s_in(s_in),
    .modo(modo),
    .out(socLSBout)
  );

  enabler enabler1(
    .clk(clk),
    .enb(enb),
    .eclk(clkenb)
  );


  bitHolder bitHolder0(
    .s_der(socLSBout),
    .s_izq(q[1]),
    .d_n(d[0]),
    .dir(dir),
    .modo(modo),
    .clkenb(clkenb),
    .s_out(q[0])
  );

  bitHolder bitHolder1(
    .s_der(q[0]),
    .s_izq(q[2]),
    .d_n(d[1]),
    .dir(dir),
    .modo(modo),
    .clkenb(clkenb),
    .s_out(q[1])
  );

  bitHolder bitHolder2(
    .s_der(q[1]),
    .s_izq(q[3]),
    .d_n(d[2]),
    .dir(dir),
    .modo(modo),
    .clkenb(clkenb),
    .s_out(q[2])
  );

  bitHolder bitHolder3(
    .s_der(q[2]),
    .s_izq(socMSBout),
    .d_n(d[3]),
    .dir(dir),
    .modo(modo),
    .clkenb(clkenb),
    .s_out(q[3])
  );

  wire [1:0] not_modo;
  wire is_modo_00;
  
  notGate notModo0(.a(modo[0]), .y(not_modo[0]));
  notGate notModo1(.a(modo[1]), .y(not_modo[1]));

  enabler modoCheck(.clk(not_modo[0]), .enb(not_modo[1]), .eclk(is_modo_00));

  salidaSerial salida(
    .modo(modo),
    .s_der(q[0]),
    .s_izq(q[3]),
    .dir(dir),
    .s_out(s_out)
  );



parameter notpreset = 1'b1;
parameter notclear = 1'b1;
wire notq;

wire s_out_ff;
ffD s_out_reg(
	.d(s_out),

	 .clk(clkenb),

	 .notpreset(notpreset),
	 .notclear(notclear),
	 .q(s_out_ff),
	 .notq(notq)
	 );


endmodule
module registro4bits (
  input        clk,
  input        enb,


  input        dir,


  input        s_in,
  input  [1:0] modo,



  input  [3:0] d,
  output [3:0] q,
  output s_out
);

  parameter bits = 4;
  wire socMSBout, socLSBout;
  wire clkenb,s_out;

  serialOcontiguo socMSB(
    .usual(q[0]),
    .s_in(s_in),
    .modo(modo),
    .out(socMSBout)
  );

  serialOcontiguo socLSB(
    .usual(q[3]),
    .s_in(s_in),
    .modo(modo),
    .out(socLSBout)
  );

  enabler enabler1(
    .clk(clk),
    .enb(enb),
    .eclk(clkenb)
  );


  bitHolder bitHolder0(
    .s_der(socLSBout),
    .s_izq(q[1]),
    .d_n(d[0]),
    .dir(dir),
    .modo(modo),
    .clkenb(clkenb),
    .s_out(q[0])
  );

  bitHolder bitHolder1(
    .s_der(q[0]),
    .s_izq(q[2]),
    .d_n(d[1]),
    .dir(dir),
    .modo(modo),
    .clkenb(clkenb),
    .s_out(q[1])
  );

  bitHolder bitHolder2(
    .s_der(q[1]),
    .s_izq(q[3]),
    .d_n(d[2]),
    .dir(dir),
    .modo(modo),
    .clkenb(clkenb),
    .s_out(q[2])
  );

  bitHolder bitHolder3(
    .s_der(q[2]),
    .s_izq(socMSBout),
    .d_n(d[3]),
    .dir(dir),
    .modo(modo),
    .clkenb(clkenb),
    .s_out(q[3])
  );

  wire [1:0] not_modo;
  wire is_modo_00;
  
  notGate notModo0(.a(modo[0]), .y(not_modo[0]));
  notGate notModo1(.a(modo[1]), .y(not_modo[1]));

  enabler modoCheck(.clk(not_modo[0]), .enb(not_modo[1]), .eclk(is_modo_00));

  salidaSerial salida(
    .modo(modo),
    .s_der(q[0]),
    .s_izq(q[3]),
    .dir(dir),
    .s_out(s_out)
  );



parameter notpreset = 1'b1;
parameter notclear = 1'b1;
wire notq;

wire s_out_ff;
ffD s_out_reg(
	.d(s_out),

	 .clk(clkenb),

	 .notpreset(notpreset),
	 .notclear(notclear),
	 .q(s_out_ff),
	 .notq(notq)
	 );


endmodule