data/full_repos/permissive/127311496/src/v/Cache/ICache.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:93: Cannot find file containing module: 'ICacheTag'\n ICacheTag cacheTag(.clka(clk), .wea(tagWe), .addra(tagAddr), .dina(tagDin), .douta({_tag1, _tag0}),\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/ICacheTag\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/ICacheTag.v\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/ICacheTag.sv\n             ICacheTag\n             ICacheTag.v\n             ICacheTag.sv\n             obj_dir/ICacheTag\n             obj_dir/ICacheTag.v\n             obj_dir/ICacheTag.sv\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:95: Cannot find file containing module: 'CacheLRUBit'\n CacheLRUBit cacheLRU(.clk(clk), .req(req), .addr(addrIn[14:6]), .hit({hit1, hit0}), .flag(LRUBit));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:43: Cannot find file containing module: 'ICacheData'\n ICacheData way0Data(.addra(PCIn[14:2]), .clka(~clkCPU), .douta(douta0), .ena(1'b1),\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:45: Cannot find file containing module: 'ICacheData'\n ICacheData way1Data(.addra(PCIn[14:2]), .clka(~clkCPU), .douta(douta1), .ena(1'b1),\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:55: Cannot find file containing module: 'AsyncHandshake'\n AsyncHandshake #(.STB_FREQ(1000 / CLKDDR_PERIOD), .ACK_FREQ(1000 / CLKCPU_PERIOD))\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:59: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) replaceStbCross(.clki(clkCPU), .clko(clkDDR), .i(replaceStb_CPU), .o(replaceStb_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:60: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) replaceBlockCross[26:0](.clki(clkCPU), .clko(clkDDR), .i(replaceBlock_CPU), .o(replaceBlock_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module ICacheFSM_DDR(
	input clk, input rst,

	output [31:0] ws_addr, input [511:0] ws_din, output ws_cyc, output ws_stb, input ws_ack,

	output [8:0] addrb, output reg [511:0] dinb = 0, output [1:0] web,

	input replaceStb, input [26:0] replaceBlock, output completeStb
);

	localparam STATE_IDLE = 2'h0;
	localparam STATE_WAIT = 2'h1;
	localparam STATE_WRITE = 2'h2;
	reg [1:0] state = STATE_IDLE;
	
	reg [25:0] addr = 0;
	reg waySel;
	
	assign ws_addr = {addr, 6'h0};
	assign addrb = addr[8:0];
	
	assign ws_stb = (state == STATE_WAIT);
	assign ws_cyc = (state == STATE_WAIT);
	assign completeStb = (state == STATE_WRITE);
	assign web = (state == STATE_WRITE)? {waySel, ~waySel}: 2'b0;
	
	always @ (posedge clk)
	if(rst)
	begin
		state <= STATE_IDLE;
	end
	else
	case(state)
	STATE_IDLE: begin
		if(replaceStb)
		begin
			state <= STATE_WAIT;
			addr <= replaceBlock[25:0];
			waySel <= replaceBlock[26];
		end
	end
	STATE_WAIT: begin
		if(ws_ack)
		begin
			state <= STATE_WRITE;
			dinb <= ws_din;
		end
	end
	STATE_WRITE: begin
		state <= STATE_IDLE;
	end
	endcase

endmodule
module ICacheFSM_DDR(
	input clk, input rst,

	output [31:0] ws_addr, input [511:0] ws_din, output ws_cyc, output ws_stb, input ws_ack,

	output [8:0] addrb, output reg [511:0] dinb = 0, output [1:0] web,

	input replaceStb, input [26:0] replaceBlock, output completeStb
);


	localparam STATE_IDLE = 2'h0;
	localparam STATE_WAIT = 2'h1;
	localparam STATE_WRITE = 2'h2;
	reg [1:0] state = STATE_IDLE;
	
	reg [25:0] addr = 0;
	reg waySel;
	
	assign ws_addr = {addr, 6'h0};
	assign addrb = addr[8:0];
	
	assign ws_stb = (state == STATE_WAIT);
	assign ws_cyc = (state == STATE_WAIT);
	assign completeStb = (state == STATE_WRITE);
	assign web = (state == STATE_WRITE)? {waySel, ~waySel}: 2'b0;
	
	always @ (posedge clk)
	if(rst)
	begin
		state <= STATE_IDLE;
	end
	else
	case(state)
	STATE_IDLE: begin
		if(replaceStb)
		begin
			state <= STATE_WAIT;
			addr <= replaceBlock[25:0];
			waySel <= replaceBlock[26];
		end
	end
	STATE_WAIT: begin
		if(ws_ack)
		begin
			state <= STATE_WRITE;
			dinb <= ws_din;
		end
	end
	STATE_WRITE: begin
		state <= STATE_IDLE;
	end
	endcase

endmodule