data/full_repos/permissive/211878730/atlys/practice/encoder.v
data/verilator_xmls/b9a86985-6dfa-4493-8d73-698b6e81f33f.xml
module encoder(
	input  wire [3:0] data,
	output reg  [2:0] y
	);
	
	always @(*) begin
		case (data)
			4'b0001: y = 3'b000;
			4'b0010: y = 3'b001;
			4'b0100: y = 3'b010;
			4'b1000: y = 3'b011;
			default: y = 3'b100;
		endcase
	end
endmodule
module encoder(
	input  wire [3:0] data,
	output reg  [2:0] y
	);

	
	always @(*) begin
		case (data)
			4'b0001: y = 3'b000;
			4'b0010: y = 3'b001;
			4'b0100: y = 3'b010;
			4'b1000: y = 3'b011;
			default: y = 3'b100;
		endcase
	end
endmodule