data/full_repos/permissive/117337560/memory_design/memory_design.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/117337560/memory_design/memory_design.v:27: Unsupported: Ignoring delay on this delayed statement.\n     #100 clk=1;address=5\'b00001;data_input=8\'b00000010;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117337560/memory_design/memory_design.v:28: Unsupported: Ignoring delay on this delayed statement.\n     #100 clk=0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/memory_design/memory_design.v:29: Unsupported: Ignoring delay on this delayed statement.\n          #100 clk=1;read_write=0;address=5\'b00001;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/memory_design/memory_design.v:30: Unsupported: Ignoring delay on this delayed statement.\n     #100 clk=0;read_write=1;address=5\'b00010;data_input=8\'b00000011;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/memory_design/memory_design.v:31: Unsupported: Ignoring delay on this delayed statement.\n     #100 clk=1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/memory_design/memory_design.v:32: Unsupported: Ignoring delay on this delayed statement.\n     #100 clk=0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/117337560/memory_design/memory_design.v:33: Unsupported: Ignoring delay on this delayed statement.\n     #100 clk=1;read_write=0;address=5\'b00010;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/117337560/memory_design/memory_design.v:11: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_input\' generates 8 bits.\n                                                                                     : ... In instance test_memory_design.G\n   memory[address] <= data_input;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/117337560/memory_design/memory_design.v:13: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 6 bits.\n                                                                                     : ... In instance test_memory_design.G\n   data_output <= memory[address];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/117337560/memory_design/memory_design.v:27: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1\' generates 5 bits.\n                                                                                     : ... In instance test_memory_design\n     #100 clk=1;address=5\'b00001;data_input=8\'b00000010;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/117337560/memory_design/memory_design.v:29: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1\' generates 5 bits.\n                                                                                     : ... In instance test_memory_design\n          #100 clk=1;read_write=0;address=5\'b00001;\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/117337560/memory_design/memory_design.v:30: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h2\' generates 5 bits.\n                                                                                     : ... In instance test_memory_design\n     #100 clk=0;read_write=1;address=5\'b00010;data_input=8\'b00000011;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/117337560/memory_design/memory_design.v:33: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h2\' generates 5 bits.\n                                                                                     : ... In instance test_memory_design\n     #100 clk=1;read_write=0;address=5\'b00010;\n                                    ^\n%Error: Exiting due to 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_design(output reg [7:0] data_output, input [7:0] data_input, input [5:0] address, input enable, read_write, clk);
    reg [5:0] memory[63:0];
    always @(posedge clk)
	begin
	    if (enable) 
		begin
		    if (read_write)
			memory[address] <= data_input;
		    else 
			data_output <= memory[address];
		end
	end
endmodule
module memory_design(output reg [7:0] data_output, input [7:0] data_input, input [5:0] address, input enable, read_write, clk);

    reg [5:0] memory[63:0];
    always @(posedge clk)
	begin
	    if (enable) 
		begin
		    if (read_write)
			memory[address] <= data_input;
		    else 
			data_output <= memory[address];
		end
	end
endmodule