data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v
1: b'%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:35: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117088385/rtl/e203/core,data/full_repos/permissive/117088385/e203_defines.v\n             data/full_repos/permissive/117088385/rtl/e203/core,data/full_repos/permissive/117088385/e203_defines.v.v\n             data/full_repos/permissive/117088385/rtl/e203/core,data/full_repos/permissive/117088385/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:48: Define or directive not defined: \'`E203_PC_SIZE\'\n  input  [`E203_PC_SIZE-1:0] pc_rtvec,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:57: Define or directive not defined: \'`E203_PC_SIZE\'\n  output  [`E203_PC_SIZE-1:0] cmt_dpc,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:66: Define or directive not defined: \'`E203_PC_SIZE\'\n  input  [`E203_PC_SIZE-1:0] dpc_r     ,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:80: Define or directive not defined: \'`E203_HART_ID_W\'\n  input  [`E203_HART_ID_W-1:0] core_mhartid,  \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:140: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  output [`E203_ADDR_SIZE-1:0]   ppi_icb_cmd_addr, \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:142: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0]        ppi_icb_cmd_wdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:143: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN/8-1:0]      ppi_icb_cmd_wmask,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:143: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n  output [`E203_XLEN/8-1:0]      ppi_icb_cmd_wmask,\n                    ^\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:149: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0]        ppi_icb_rsp_rdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:156: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:158: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:159: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:165: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:172: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:174: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:175: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:181: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:191: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  output [`E203_ADDR_SIZE-1:0]   fio_icb_cmd_addr, \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:193: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0]        fio_icb_cmd_wdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:194: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN/8-1:0]      fio_icb_cmd_wmask,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:200: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0]        fio_icb_rsp_rdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:209: Define or directive not defined: \'`E203_ADDR_SIZE\'\n  output [`E203_ADDR_SIZE-1:0]   mem_icb_cmd_addr, \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:211: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN-1:0]        mem_icb_cmd_wdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:212: Define or directive not defined: \'`E203_XLEN\'\n  output [`E203_XLEN/8-1:0]      mem_icb_cmd_wmask,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:218: Define or directive not defined: \'`E203_XLEN\'\n  input  [`E203_XLEN-1:0]        mem_icb_rsp_rdata,\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:328: Define or directive not defined: \'`E203_PPI_ADDR_BASE\'\n    .ppi_region_indic      (`E203_PPI_ADDR_BASE),\n                            ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:350: Define or directive not defined: \'`E203_CLINT_ADDR_BASE\'\n    .clint_region_indic      (`E203_CLINT_ADDR_BASE),\n                              ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117088385/rtl/e203/core/e203_cpu_top.v:372: Define or directive not defined: \'`E203_PLIC_ADDR_BASE\'\n    .plic_region_indic      (`E203_PLIC_ADDR_BASE),\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 29 error(s)\n'
module e203_cpu_top(


  output core_wfi,




  output tm_stop,


  input  [`E203_PC_SIZE-1:0] pc_rtvec,





  output  dbg_irq_r,


  output  [`E203_PC_SIZE-1:0] cmt_dpc,
  output  cmt_dpc_ena,
  output  [3-1:0] cmt_dcause,
  output  cmt_dcause_ena,
  output  wr_dcsr_ena    ,
  output  wr_dpc_ena     ,
  output  wr_dscratch_ena,
  output  [32-1:0] wr_csr_nxt    ,
  input  [32-1:0] dcsr_r    ,
  input  [`E203_PC_SIZE-1:0] dpc_r     ,
  input  [32-1:0] dscratch_r,


  input  dbg_mode,
  input  dbg_halt_r,
  input  dbg_step_r,
  input  dbg_ebreakm_r,
  input  dbg_stopcycle,
  input  dbg_irq_a,




  input  [`E203_HART_ID_W-1:0] core_mhartid,  


  input  ext_irq_a,

  input  sft_irq_a,

  input  tmr_irq_a,
  
  

  input tcm_sd,

  input tcm_ds,
    
  `ifdef E203_HAS_ITCM_EXTITF



  input                          ext2itcm_icb_cmd_valid,
  output                         ext2itcm_icb_cmd_ready,
  input  [`E203_ITCM_ADDR_WIDTH-1:0]   ext2itcm_icb_cmd_addr, 
  input                          ext2itcm_icb_cmd_read, 
  input  [`E203_XLEN-1:0]        ext2itcm_icb_cmd_wdata,
  input  [`E203_XLEN/8-1:0]      ext2itcm_icb_cmd_wmask,


  output                         ext2itcm_icb_rsp_valid,
  input                          ext2itcm_icb_rsp_ready,
  output                         ext2itcm_icb_rsp_err  ,
  output [`E203_XLEN-1:0]        ext2itcm_icb_rsp_rdata,

  `endif

  `ifdef E203_HAS_DTCM_EXTITF



  input                          ext2dtcm_icb_cmd_valid,
  output                         ext2dtcm_icb_cmd_ready,
  input  [`E203_DTCM_ADDR_WIDTH-1:0]   ext2dtcm_icb_cmd_addr, 
  input                          ext2dtcm_icb_cmd_read, 
  input  [`E203_XLEN-1:0]        ext2dtcm_icb_cmd_wdata,
  input  [`E203_XLEN/8-1:0]      ext2dtcm_icb_cmd_wmask,


  output                         ext2dtcm_icb_rsp_valid,
  input                          ext2dtcm_icb_rsp_ready,
  output                         ext2dtcm_icb_rsp_err  ,
  output [`E203_XLEN-1:0]        ext2dtcm_icb_rsp_rdata,

  `endif

  




  output                         ppi_icb_cmd_valid,
  input                          ppi_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   ppi_icb_cmd_addr, 
  output                         ppi_icb_cmd_read, 
  output [`E203_XLEN-1:0]        ppi_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      ppi_icb_cmd_wmask,


  input                          ppi_icb_rsp_valid,
  output                         ppi_icb_rsp_ready,
  input                          ppi_icb_rsp_err  ,
  input  [`E203_XLEN-1:0]        ppi_icb_rsp_rdata,




  output                         clint_icb_cmd_valid,
  input                          clint_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, 
  output                         clint_icb_cmd_read, 
  output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,


  input                          clint_icb_rsp_valid,
  output                         clint_icb_rsp_ready,
  input                          clint_icb_rsp_err  ,
  input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,




  output                         plic_icb_cmd_valid,
  input                          plic_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, 
  output                         plic_icb_cmd_read, 
  output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,


  input                          plic_icb_rsp_valid,
  output                         plic_icb_rsp_ready,
  input                          plic_icb_rsp_err  ,
  input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,







  output                         fio_icb_cmd_valid,
  input                          fio_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   fio_icb_cmd_addr, 
  output                         fio_icb_cmd_read, 
  output [`E203_XLEN-1:0]        fio_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      fio_icb_cmd_wmask,


  input                          fio_icb_rsp_valid,
  output                         fio_icb_rsp_ready,
  input                          fio_icb_rsp_err  ,
  input  [`E203_XLEN-1:0]        fio_icb_rsp_rdata,






  output                         mem_icb_cmd_valid,
  input                          mem_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   mem_icb_cmd_addr, 
  output                         mem_icb_cmd_read, 
  output [`E203_XLEN-1:0]        mem_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      mem_icb_cmd_wmask,


  input                          mem_icb_rsp_valid,
  output                         mem_icb_rsp_ready,
  input                          mem_icb_rsp_err  ,
  input  [`E203_XLEN-1:0]        mem_icb_rsp_rdata,




  input  test_mode,


  input  clk,


  input  rst_n
  );


  `ifdef E203_HAS_ITCM
  wire  itcm_ls;

  wire                          itcm_ram_cs  ;
  wire                          itcm_ram_we  ;
  wire  [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr;
  wire  [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem ;
  wire  [`E203_ITCM_RAM_DW-1:0] itcm_ram_din ;
  wire  [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout;
  wire                          clk_itcm_ram ;
  `endif

  
  `ifdef E203_HAS_DTCM
  wire  dtcm_ls;

  wire                          dtcm_ram_cs  ;
  wire                          dtcm_ram_we  ;
  wire  [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr;
  wire  [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem ;
  wire  [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din ;
  wire  [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout;
  wire                          clk_dtcm_ram ;
  `endif

  e203_cpu u_e203_cpu(
    .tm_stop (tm_stop),
    .pc_rtvec(pc_rtvec),
  `ifdef E203_HAS_ITCM
    .itcm_ls (itcm_ls),
  `endif
  `ifdef E203_HAS_DTCM
    .dtcm_ls (dtcm_ls),
  `endif
    .core_wfi        (core_wfi),
    .dbg_irq_r       (dbg_irq_r      ),

    .cmt_dpc         (cmt_dpc        ),
    .cmt_dpc_ena     (cmt_dpc_ena    ),
    .cmt_dcause      (cmt_dcause     ),
    .cmt_dcause_ena  (cmt_dcause_ena ),

    .wr_dcsr_ena     (wr_dcsr_ena    ),
    .wr_dpc_ena      (wr_dpc_ena     ),
    .wr_dscratch_ena (wr_dscratch_ena),


                                     
    .wr_csr_nxt      (wr_csr_nxt    ),
                                     
    .dcsr_r          (dcsr_r         ),
    .dpc_r           (dpc_r          ),
    .dscratch_r      (dscratch_r     ),

    .dbg_mode        (dbg_mode),
    .dbg_halt_r      (dbg_halt_r),
    .dbg_step_r      (dbg_step_r),
    .dbg_ebreakm_r   (dbg_ebreakm_r),
    .dbg_stopcycle   (dbg_stopcycle),

    .core_mhartid            (core_mhartid),  
    .dbg_irq_a               (dbg_irq_a),
    .ext_irq_a               (ext_irq_a),
    .sft_irq_a               (sft_irq_a),
    .tmr_irq_a               (tmr_irq_a),

  `ifdef E203_HAS_ITCM_EXTITF
    .ext2itcm_icb_cmd_valid  (ext2itcm_icb_cmd_valid),
    .ext2itcm_icb_cmd_ready  (ext2itcm_icb_cmd_ready),
    .ext2itcm_icb_cmd_addr   (ext2itcm_icb_cmd_addr ),
    .ext2itcm_icb_cmd_read   (ext2itcm_icb_cmd_read ),
    .ext2itcm_icb_cmd_wdata  (ext2itcm_icb_cmd_wdata),
    .ext2itcm_icb_cmd_wmask  (ext2itcm_icb_cmd_wmask),
    
    .ext2itcm_icb_rsp_valid  (ext2itcm_icb_rsp_valid),
    .ext2itcm_icb_rsp_ready  (ext2itcm_icb_rsp_ready),
    .ext2itcm_icb_rsp_err    (ext2itcm_icb_rsp_err  ),
    .ext2itcm_icb_rsp_rdata  (ext2itcm_icb_rsp_rdata),
  `endif

  `ifdef E203_HAS_DTCM_EXTITF
    .ext2dtcm_icb_cmd_valid  (ext2dtcm_icb_cmd_valid),
    .ext2dtcm_icb_cmd_ready  (ext2dtcm_icb_cmd_ready),
    .ext2dtcm_icb_cmd_addr   (ext2dtcm_icb_cmd_addr ),
    .ext2dtcm_icb_cmd_read   (ext2dtcm_icb_cmd_read ),
    .ext2dtcm_icb_cmd_wdata  (ext2dtcm_icb_cmd_wdata),
    .ext2dtcm_icb_cmd_wmask  (ext2dtcm_icb_cmd_wmask),
    
    .ext2dtcm_icb_rsp_valid  (ext2dtcm_icb_rsp_valid),
    .ext2dtcm_icb_rsp_ready  (ext2dtcm_icb_rsp_ready),
    .ext2dtcm_icb_rsp_err    (ext2dtcm_icb_rsp_err  ),
    .ext2dtcm_icb_rsp_rdata  (ext2dtcm_icb_rsp_rdata),
  `endif


    .ppi_region_indic      (`E203_PPI_ADDR_BASE),
    `ifdef E203_HAS_PPI
    .ppi_icb_enable        (1'b1),
    `else
    .ppi_icb_enable        (1'b0),
    `endif
    .ppi_icb_cmd_valid     (ppi_icb_cmd_valid),
    .ppi_icb_cmd_ready     (ppi_icb_cmd_ready),
    .ppi_icb_cmd_addr      (ppi_icb_cmd_addr ),
    .ppi_icb_cmd_read      (ppi_icb_cmd_read ),
    .ppi_icb_cmd_wdata     (ppi_icb_cmd_wdata),
    .ppi_icb_cmd_wmask     (ppi_icb_cmd_wmask),
    .ppi_icb_cmd_lock      (),
    .ppi_icb_cmd_excl      (),
    .ppi_icb_cmd_size      (),
    
    .ppi_icb_rsp_valid     (ppi_icb_rsp_valid),
    .ppi_icb_rsp_ready     (ppi_icb_rsp_ready),
    .ppi_icb_rsp_err       (ppi_icb_rsp_err  ),
    .ppi_icb_rsp_excl_ok   (1'b0  ),
    .ppi_icb_rsp_rdata     (ppi_icb_rsp_rdata),

    .clint_region_indic      (`E203_CLINT_ADDR_BASE),
    `ifdef E203_HAS_CLINT
    .clint_icb_enable        (1'b1),
    `else
    .clint_icb_enable        (1'b0),
    `endif
    .clint_icb_cmd_valid     (clint_icb_cmd_valid),
    .clint_icb_cmd_ready     (clint_icb_cmd_ready),
    .clint_icb_cmd_addr      (clint_icb_cmd_addr ),
    .clint_icb_cmd_read      (clint_icb_cmd_read ),
    .clint_icb_cmd_wdata     (clint_icb_cmd_wdata),
    .clint_icb_cmd_wmask     (clint_icb_cmd_wmask),
    .clint_icb_cmd_lock      (),
    .clint_icb_cmd_excl      (),
    .clint_icb_cmd_size      (),
    
    .clint_icb_rsp_valid     (clint_icb_rsp_valid),
    .clint_icb_rsp_ready     (clint_icb_rsp_ready),
    .clint_icb_rsp_err       (clint_icb_rsp_err  ),
    .clint_icb_rsp_excl_ok   (1'b0  ),
    .clint_icb_rsp_rdata     (clint_icb_rsp_rdata),

    .plic_region_indic      (`E203_PLIC_ADDR_BASE),
    `ifdef E203_HAS_PLIC
    .plic_icb_enable        (1'b1),
    `else
    .plic_icb_enable        (1'b0),
    `endif
    .plic_icb_cmd_valid     (plic_icb_cmd_valid),
    .plic_icb_cmd_ready     (plic_icb_cmd_ready),
    .plic_icb_cmd_addr      (plic_icb_cmd_addr ),
    .plic_icb_cmd_read      (plic_icb_cmd_read ),
    .plic_icb_cmd_wdata     (plic_icb_cmd_wdata),
    .plic_icb_cmd_wmask     (plic_icb_cmd_wmask),
    .plic_icb_cmd_lock      (),
    .plic_icb_cmd_excl      (),
    .plic_icb_cmd_size      (),
    
    .plic_icb_rsp_valid     (plic_icb_rsp_valid),
    .plic_icb_rsp_ready     (plic_icb_rsp_ready),
    .plic_icb_rsp_err       (plic_icb_rsp_err  ),
    .plic_icb_rsp_excl_ok   (1'b0  ),
    .plic_icb_rsp_rdata     (plic_icb_rsp_rdata),


  `ifdef E203_HAS_FIO
    `ifdef E203_HAS_FIO
    .fio_icb_enable        (1'b1),
    `else
    .fio_icb_enable        (1'b0),
    `endif
    .fio_region_indic      (`E203_FIO_ADDR_BASE),
    .fio_icb_cmd_valid     (fio_icb_cmd_valid),
    .fio_icb_cmd_ready     (fio_icb_cmd_ready),
    .fio_icb_cmd_addr      (fio_icb_cmd_addr ),
    .fio_icb_cmd_read      (fio_icb_cmd_read ),
    .fio_icb_cmd_wdata     (fio_icb_cmd_wdata),
    .fio_icb_cmd_wmask     (fio_icb_cmd_wmask),
    .fio_icb_cmd_lock      (),
    .fio_icb_cmd_excl      (),
    .fio_icb_cmd_size      (),
    
    .fio_icb_rsp_valid     (fio_icb_rsp_valid),
    .fio_icb_rsp_ready     (fio_icb_rsp_ready),
    .fio_icb_rsp_err       (fio_icb_rsp_err  ),
    .fio_icb_rsp_excl_ok   (1'b0  ),
    .fio_icb_rsp_rdata     (fio_icb_rsp_rdata),
  `endif

  `ifdef E203_HAS_MEM_ITF
    `ifdef E203_HAS_MEM_ITF
    .mem_icb_enable        (1'b1),
    `else
    .mem_icb_enable        (1'b0),
    `endif
    .mem_icb_cmd_valid  (mem_icb_cmd_valid),
    .mem_icb_cmd_ready  (mem_icb_cmd_ready),
    .mem_icb_cmd_addr   (mem_icb_cmd_addr ),
    .mem_icb_cmd_read   (mem_icb_cmd_read ),
    .mem_icb_cmd_wdata  (mem_icb_cmd_wdata),
    .mem_icb_cmd_wmask  (mem_icb_cmd_wmask),
    .mem_icb_cmd_lock   (),
    .mem_icb_cmd_excl   (),
    .mem_icb_cmd_size   (),
    .mem_icb_cmd_burst  (),
    .mem_icb_cmd_beat   (),
    
    .mem_icb_rsp_valid  (mem_icb_rsp_valid),
    .mem_icb_rsp_ready  (mem_icb_rsp_ready),
    .mem_icb_rsp_err    (mem_icb_rsp_err  ),
    .mem_icb_rsp_excl_ok(1'b0  ),
    .mem_icb_rsp_rdata  (mem_icb_rsp_rdata),
  `endif

  `ifdef E203_HAS_ITCM
    .itcm_ram_cs   (itcm_ram_cs  ),
    .itcm_ram_we   (itcm_ram_we  ),
    .itcm_ram_addr (itcm_ram_addr), 
    .itcm_ram_wem  (itcm_ram_wem ),
    .itcm_ram_din  (itcm_ram_din ),         
    .itcm_ram_dout (itcm_ram_dout),
    .clk_itcm_ram  (clk_itcm_ram ),  
  `endif

  `ifdef E203_HAS_DTCM
    .dtcm_ram_cs   (dtcm_ram_cs  ),
    .dtcm_ram_we   (dtcm_ram_we  ),
    .dtcm_ram_addr (dtcm_ram_addr), 
    .dtcm_ram_wem  (dtcm_ram_wem ),
    .dtcm_ram_din  (dtcm_ram_din ),         
    .dtcm_ram_dout (dtcm_ram_dout),
    .clk_dtcm_ram  (clk_dtcm_ram ),  
  `endif

    .test_mode     (test_mode), 
    .clk           (clk  ),
    .rst_n         (rst_n) 

  );

  e203_srams u_e203_srams(
  `ifdef E203_HAS_DTCM
   .dtcm_ram_sd (tcm_sd),
   .dtcm_ram_ds (tcm_ds),
   .dtcm_ram_ls (dtcm_ls),

   .dtcm_ram_cs   (dtcm_ram_cs  ),
   .dtcm_ram_we   (dtcm_ram_we  ),
   .dtcm_ram_addr (dtcm_ram_addr), 
   .dtcm_ram_wem  (dtcm_ram_wem ),
   .dtcm_ram_din  (dtcm_ram_din ),         
   .dtcm_ram_dout (dtcm_ram_dout),
   .clk_dtcm_ram  (clk_dtcm_ram ),  
  `endif

  `ifdef E203_HAS_ITCM
   .itcm_ram_sd (tcm_sd),
   .itcm_ram_ds (tcm_ds),
   .itcm_ram_ls (itcm_ls),

   .itcm_ram_cs   (itcm_ram_cs  ),
   .itcm_ram_we   (itcm_ram_we  ),
   .itcm_ram_addr (itcm_ram_addr), 
   .itcm_ram_wem  (itcm_ram_wem ),
   .itcm_ram_din  (itcm_ram_din ),         
   .itcm_ram_dout (itcm_ram_dout),
   .clk_itcm_ram  (clk_itcm_ram ),  
  `endif
   .test_mode (test_mode) 
  );

endmodule
module e203_cpu_top(


  output core_wfi,




  output tm_stop,


  input  [`E203_PC_SIZE-1:0] pc_rtvec,





  output  dbg_irq_r,


  output  [`E203_PC_SIZE-1:0] cmt_dpc,
  output  cmt_dpc_ena,
  output  [3-1:0] cmt_dcause,
  output  cmt_dcause_ena,
  output  wr_dcsr_ena    ,
  output  wr_dpc_ena     ,
  output  wr_dscratch_ena,
  output  [32-1:0] wr_csr_nxt    ,
  input  [32-1:0] dcsr_r    ,
  input  [`E203_PC_SIZE-1:0] dpc_r     ,
  input  [32-1:0] dscratch_r,


  input  dbg_mode,
  input  dbg_halt_r,
  input  dbg_step_r,
  input  dbg_ebreakm_r,
  input  dbg_stopcycle,
  input  dbg_irq_a,




  input  [`E203_HART_ID_W-1:0] core_mhartid,  


  input  ext_irq_a,

  input  sft_irq_a,

  input  tmr_irq_a,
  
  

  input tcm_sd,

  input tcm_ds,
    
  `ifdef E203_HAS_ITCM_EXTITF



  input                          ext2itcm_icb_cmd_valid,
  output                         ext2itcm_icb_cmd_ready,
  input  [`E203_ITCM_ADDR_WIDTH-1:0]   ext2itcm_icb_cmd_addr, 
  input                          ext2itcm_icb_cmd_read, 
  input  [`E203_XLEN-1:0]        ext2itcm_icb_cmd_wdata,
  input  [`E203_XLEN/8-1:0]      ext2itcm_icb_cmd_wmask,


  output                         ext2itcm_icb_rsp_valid,
  input                          ext2itcm_icb_rsp_ready,
  output                         ext2itcm_icb_rsp_err  ,
  output [`E203_XLEN-1:0]        ext2itcm_icb_rsp_rdata,

  `endif

  `ifdef E203_HAS_DTCM_EXTITF



  input                          ext2dtcm_icb_cmd_valid,
  output                         ext2dtcm_icb_cmd_ready,
  input  [`E203_DTCM_ADDR_WIDTH-1:0]   ext2dtcm_icb_cmd_addr, 
  input                          ext2dtcm_icb_cmd_read, 
  input  [`E203_XLEN-1:0]        ext2dtcm_icb_cmd_wdata,
  input  [`E203_XLEN/8-1:0]      ext2dtcm_icb_cmd_wmask,


  output                         ext2dtcm_icb_rsp_valid,
  input                          ext2dtcm_icb_rsp_ready,
  output                         ext2dtcm_icb_rsp_err  ,
  output [`E203_XLEN-1:0]        ext2dtcm_icb_rsp_rdata,

  `endif

  




  output                         ppi_icb_cmd_valid,
  input                          ppi_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   ppi_icb_cmd_addr, 
  output                         ppi_icb_cmd_read, 
  output [`E203_XLEN-1:0]        ppi_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      ppi_icb_cmd_wmask,


  input                          ppi_icb_rsp_valid,
  output                         ppi_icb_rsp_ready,
  input                          ppi_icb_rsp_err  ,
  input  [`E203_XLEN-1:0]        ppi_icb_rsp_rdata,




  output                         clint_icb_cmd_valid,
  input                          clint_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, 
  output                         clint_icb_cmd_read, 
  output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,


  input                          clint_icb_rsp_valid,
  output                         clint_icb_rsp_ready,
  input                          clint_icb_rsp_err  ,
  input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,




  output                         plic_icb_cmd_valid,
  input                          plic_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, 
  output                         plic_icb_cmd_read, 
  output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,


  input                          plic_icb_rsp_valid,
  output                         plic_icb_rsp_ready,
  input                          plic_icb_rsp_err  ,
  input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,







  output                         fio_icb_cmd_valid,
  input                          fio_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   fio_icb_cmd_addr, 
  output                         fio_icb_cmd_read, 
  output [`E203_XLEN-1:0]        fio_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      fio_icb_cmd_wmask,


  input                          fio_icb_rsp_valid,
  output                         fio_icb_rsp_ready,
  input                          fio_icb_rsp_err  ,
  input  [`E203_XLEN-1:0]        fio_icb_rsp_rdata,






  output                         mem_icb_cmd_valid,
  input                          mem_icb_cmd_ready,
  output [`E203_ADDR_SIZE-1:0]   mem_icb_cmd_addr, 
  output                         mem_icb_cmd_read, 
  output [`E203_XLEN-1:0]        mem_icb_cmd_wdata,
  output [`E203_XLEN/8-1:0]      mem_icb_cmd_wmask,


  input                          mem_icb_rsp_valid,
  output                         mem_icb_rsp_ready,
  input                          mem_icb_rsp_err  ,
  input  [`E203_XLEN-1:0]        mem_icb_rsp_rdata,




  input  test_mode,


  input  clk,


  input  rst_n
  );



  `ifdef E203_HAS_ITCM
  wire  itcm_ls;

  wire                          itcm_ram_cs  ;
  wire                          itcm_ram_we  ;
  wire  [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr;
  wire  [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem ;
  wire  [`E203_ITCM_RAM_DW-1:0] itcm_ram_din ;
  wire  [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout;
  wire                          clk_itcm_ram ;
  `endif

  
  `ifdef E203_HAS_DTCM
  wire  dtcm_ls;

  wire                          dtcm_ram_cs  ;
  wire                          dtcm_ram_we  ;
  wire  [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr;
  wire  [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem ;
  wire  [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din ;
  wire  [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout;
  wire                          clk_dtcm_ram ;
  `endif

  e203_cpu u_e203_cpu(
    .tm_stop (tm_stop),
    .pc_rtvec(pc_rtvec),
  `ifdef E203_HAS_ITCM
    .itcm_ls (itcm_ls),
  `endif
  `ifdef E203_HAS_DTCM
    .dtcm_ls (dtcm_ls),
  `endif
    .core_wfi        (core_wfi),
    .dbg_irq_r       (dbg_irq_r      ),

    .cmt_dpc         (cmt_dpc        ),
    .cmt_dpc_ena     (cmt_dpc_ena    ),
    .cmt_dcause      (cmt_dcause     ),
    .cmt_dcause_ena  (cmt_dcause_ena ),

    .wr_dcsr_ena     (wr_dcsr_ena    ),
    .wr_dpc_ena      (wr_dpc_ena     ),
    .wr_dscratch_ena (wr_dscratch_ena),


                                     
    .wr_csr_nxt      (wr_csr_nxt    ),
                                     
    .dcsr_r          (dcsr_r         ),
    .dpc_r           (dpc_r          ),
    .dscratch_r      (dscratch_r     ),

    .dbg_mode        (dbg_mode),
    .dbg_halt_r      (dbg_halt_r),
    .dbg_step_r      (dbg_step_r),
    .dbg_ebreakm_r   (dbg_ebreakm_r),
    .dbg_stopcycle   (dbg_stopcycle),

    .core_mhartid            (core_mhartid),  
    .dbg_irq_a               (dbg_irq_a),
    .ext_irq_a               (ext_irq_a),
    .sft_irq_a               (sft_irq_a),
    .tmr_irq_a               (tmr_irq_a),

  `ifdef E203_HAS_ITCM_EXTITF
    .ext2itcm_icb_cmd_valid  (ext2itcm_icb_cmd_valid),
    .ext2itcm_icb_cmd_ready  (ext2itcm_icb_cmd_ready),
    .ext2itcm_icb_cmd_addr   (ext2itcm_icb_cmd_addr ),
    .ext2itcm_icb_cmd_read   (ext2itcm_icb_cmd_read ),
    .ext2itcm_icb_cmd_wdata  (ext2itcm_icb_cmd_wdata),
    .ext2itcm_icb_cmd_wmask  (ext2itcm_icb_cmd_wmask),
    
    .ext2itcm_icb_rsp_valid  (ext2itcm_icb_rsp_valid),
    .ext2itcm_icb_rsp_ready  (ext2itcm_icb_rsp_ready),
    .ext2itcm_icb_rsp_err    (ext2itcm_icb_rsp_err  ),
    .ext2itcm_icb_rsp_rdata  (ext2itcm_icb_rsp_rdata),
  `endif

  `ifdef E203_HAS_DTCM_EXTITF
    .ext2dtcm_icb_cmd_valid  (ext2dtcm_icb_cmd_valid),
    .ext2dtcm_icb_cmd_ready  (ext2dtcm_icb_cmd_ready),
    .ext2dtcm_icb_cmd_addr   (ext2dtcm_icb_cmd_addr ),
    .ext2dtcm_icb_cmd_read   (ext2dtcm_icb_cmd_read ),
    .ext2dtcm_icb_cmd_wdata  (ext2dtcm_icb_cmd_wdata),
    .ext2dtcm_icb_cmd_wmask  (ext2dtcm_icb_cmd_wmask),
    
    .ext2dtcm_icb_rsp_valid  (ext2dtcm_icb_rsp_valid),
    .ext2dtcm_icb_rsp_ready  (ext2dtcm_icb_rsp_ready),
    .ext2dtcm_icb_rsp_err    (ext2dtcm_icb_rsp_err  ),
    .ext2dtcm_icb_rsp_rdata  (ext2dtcm_icb_rsp_rdata),
  `endif


    .ppi_region_indic      (`E203_PPI_ADDR_BASE),
    `ifdef E203_HAS_PPI
    .ppi_icb_enable        (1'b1),
    `else
    .ppi_icb_enable        (1'b0),
    `endif
    .ppi_icb_cmd_valid     (ppi_icb_cmd_valid),
    .ppi_icb_cmd_ready     (ppi_icb_cmd_ready),
    .ppi_icb_cmd_addr      (ppi_icb_cmd_addr ),
    .ppi_icb_cmd_read      (ppi_icb_cmd_read ),
    .ppi_icb_cmd_wdata     (ppi_icb_cmd_wdata),
    .ppi_icb_cmd_wmask     (ppi_icb_cmd_wmask),
    .ppi_icb_cmd_lock      (),
    .ppi_icb_cmd_excl      (),
    .ppi_icb_cmd_size      (),
    
    .ppi_icb_rsp_valid     (ppi_icb_rsp_valid),
    .ppi_icb_rsp_ready     (ppi_icb_rsp_ready),
    .ppi_icb_rsp_err       (ppi_icb_rsp_err  ),
    .ppi_icb_rsp_excl_ok   (1'b0  ),
    .ppi_icb_rsp_rdata     (ppi_icb_rsp_rdata),

    .clint_region_indic      (`E203_CLINT_ADDR_BASE),
    `ifdef E203_HAS_CLINT
    .clint_icb_enable        (1'b1),
    `else
    .clint_icb_enable        (1'b0),
    `endif
    .clint_icb_cmd_valid     (clint_icb_cmd_valid),
    .clint_icb_cmd_ready     (clint_icb_cmd_ready),
    .clint_icb_cmd_addr      (clint_icb_cmd_addr ),
    .clint_icb_cmd_read      (clint_icb_cmd_read ),
    .clint_icb_cmd_wdata     (clint_icb_cmd_wdata),
    .clint_icb_cmd_wmask     (clint_icb_cmd_wmask),
    .clint_icb_cmd_lock      (),
    .clint_icb_cmd_excl      (),
    .clint_icb_cmd_size      (),
    
    .clint_icb_rsp_valid     (clint_icb_rsp_valid),
    .clint_icb_rsp_ready     (clint_icb_rsp_ready),
    .clint_icb_rsp_err       (clint_icb_rsp_err  ),
    .clint_icb_rsp_excl_ok   (1'b0  ),
    .clint_icb_rsp_rdata     (clint_icb_rsp_rdata),

    .plic_region_indic      (`E203_PLIC_ADDR_BASE),
    `ifdef E203_HAS_PLIC
    .plic_icb_enable        (1'b1),
    `else
    .plic_icb_enable        (1'b0),
    `endif
    .plic_icb_cmd_valid     (plic_icb_cmd_valid),
    .plic_icb_cmd_ready     (plic_icb_cmd_ready),
    .plic_icb_cmd_addr      (plic_icb_cmd_addr ),
    .plic_icb_cmd_read      (plic_icb_cmd_read ),
    .plic_icb_cmd_wdata     (plic_icb_cmd_wdata),
    .plic_icb_cmd_wmask     (plic_icb_cmd_wmask),
    .plic_icb_cmd_lock      (),
    .plic_icb_cmd_excl      (),
    .plic_icb_cmd_size      (),
    
    .plic_icb_rsp_valid     (plic_icb_rsp_valid),
    .plic_icb_rsp_ready     (plic_icb_rsp_ready),
    .plic_icb_rsp_err       (plic_icb_rsp_err  ),
    .plic_icb_rsp_excl_ok   (1'b0  ),
    .plic_icb_rsp_rdata     (plic_icb_rsp_rdata),


  `ifdef E203_HAS_FIO
    `ifdef E203_HAS_FIO
    .fio_icb_enable        (1'b1),
    `else
    .fio_icb_enable        (1'b0),
    `endif
    .fio_region_indic      (`E203_FIO_ADDR_BASE),
    .fio_icb_cmd_valid     (fio_icb_cmd_valid),
    .fio_icb_cmd_ready     (fio_icb_cmd_ready),
    .fio_icb_cmd_addr      (fio_icb_cmd_addr ),
    .fio_icb_cmd_read      (fio_icb_cmd_read ),
    .fio_icb_cmd_wdata     (fio_icb_cmd_wdata),
    .fio_icb_cmd_wmask     (fio_icb_cmd_wmask),
    .fio_icb_cmd_lock      (),
    .fio_icb_cmd_excl      (),
    .fio_icb_cmd_size      (),
    
    .fio_icb_rsp_valid     (fio_icb_rsp_valid),
    .fio_icb_rsp_ready     (fio_icb_rsp_ready),
    .fio_icb_rsp_err       (fio_icb_rsp_err  ),
    .fio_icb_rsp_excl_ok   (1'b0  ),
    .fio_icb_rsp_rdata     (fio_icb_rsp_rdata),
  `endif

  `ifdef E203_HAS_MEM_ITF
    `ifdef E203_HAS_MEM_ITF
    .mem_icb_enable        (1'b1),
    `else
    .mem_icb_enable        (1'b0),
    `endif
    .mem_icb_cmd_valid  (mem_icb_cmd_valid),
    .mem_icb_cmd_ready  (mem_icb_cmd_ready),
    .mem_icb_cmd_addr   (mem_icb_cmd_addr ),
    .mem_icb_cmd_read   (mem_icb_cmd_read ),
    .mem_icb_cmd_wdata  (mem_icb_cmd_wdata),
    .mem_icb_cmd_wmask  (mem_icb_cmd_wmask),
    .mem_icb_cmd_lock   (),
    .mem_icb_cmd_excl   (),
    .mem_icb_cmd_size   (),
    .mem_icb_cmd_burst  (),
    .mem_icb_cmd_beat   (),
    
    .mem_icb_rsp_valid  (mem_icb_rsp_valid),
    .mem_icb_rsp_ready  (mem_icb_rsp_ready),
    .mem_icb_rsp_err    (mem_icb_rsp_err  ),
    .mem_icb_rsp_excl_ok(1'b0  ),
    .mem_icb_rsp_rdata  (mem_icb_rsp_rdata),
  `endif

  `ifdef E203_HAS_ITCM
    .itcm_ram_cs   (itcm_ram_cs  ),
    .itcm_ram_we   (itcm_ram_we  ),
    .itcm_ram_addr (itcm_ram_addr), 
    .itcm_ram_wem  (itcm_ram_wem ),
    .itcm_ram_din  (itcm_ram_din ),         
    .itcm_ram_dout (itcm_ram_dout),
    .clk_itcm_ram  (clk_itcm_ram ),  
  `endif

  `ifdef E203_HAS_DTCM
    .dtcm_ram_cs   (dtcm_ram_cs  ),
    .dtcm_ram_we   (dtcm_ram_we  ),
    .dtcm_ram_addr (dtcm_ram_addr), 
    .dtcm_ram_wem  (dtcm_ram_wem ),
    .dtcm_ram_din  (dtcm_ram_din ),         
    .dtcm_ram_dout (dtcm_ram_dout),
    .clk_dtcm_ram  (clk_dtcm_ram ),  
  `endif

    .test_mode     (test_mode), 
    .clk           (clk  ),
    .rst_n         (rst_n) 

  );

  e203_srams u_e203_srams(
  `ifdef E203_HAS_DTCM
   .dtcm_ram_sd (tcm_sd),
   .dtcm_ram_ds (tcm_ds),
   .dtcm_ram_ls (dtcm_ls),

   .dtcm_ram_cs   (dtcm_ram_cs  ),
   .dtcm_ram_we   (dtcm_ram_we  ),
   .dtcm_ram_addr (dtcm_ram_addr), 
   .dtcm_ram_wem  (dtcm_ram_wem ),
   .dtcm_ram_din  (dtcm_ram_din ),         
   .dtcm_ram_dout (dtcm_ram_dout),
   .clk_dtcm_ram  (clk_dtcm_ram ),  
  `endif

  `ifdef E203_HAS_ITCM
   .itcm_ram_sd (tcm_sd),
   .itcm_ram_ds (tcm_ds),
   .itcm_ram_ls (itcm_ls),

   .itcm_ram_cs   (itcm_ram_cs  ),
   .itcm_ram_we   (itcm_ram_we  ),
   .itcm_ram_addr (itcm_ram_addr), 
   .itcm_ram_wem  (itcm_ram_wem ),
   .itcm_ram_din  (itcm_ram_din ),         
   .itcm_ram_dout (itcm_ram_dout),
   .clk_itcm_ram  (clk_itcm_ram ),  
  `endif
   .test_mode (test_mode) 
  );

endmodule