data/full_repos/permissive/208556773/src/rapcore.v
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1: b"%Error: data/full_repos/permissive/208556773/src/rapcore.v:5: Define or directive not defined: '`MOTOR_COUNT'\n  parameter num_motors = `MOTOR_COUNT,\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/208556773/src/rapcore.v:5: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n  parameter num_motors = `MOTOR_COUNT,\n                                     ^\n%Error: data/full_repos/permissive/208556773/src/rapcore.v:6: Define or directive not defined: '`MOVE_DURATION_BITS'\n  parameter move_duration_bits = `MOVE_DURATION_BITS\n                                 ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/208556773/src/rapcore.v:7: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n  )(\n  ^\n%Error: data/full_repos/permissive/208556773/src/rapcore.v:150: syntax error, unexpected assign\n  assign resetn = &resetn_counter;\n  ^~~~~~\n%Error: data/full_repos/permissive/208556773/src/rapcore.v:161: syntax error, unexpected always\n    always @(posedge buffered_clk) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/208556773/src/rapcore.v:174: syntax error, unexpected IDENTIFIER\n  SPIWord word_proc (\n  ^~~~~~~\n%Error: data/full_repos/permissive/208556773/src/rapcore.v:193: Define or directive not defined: '`DEFAULT_MICROSTEPS'\n                      .default_microsteps(`DEFAULT_MICROSTEPS),\n                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/208556773/src/rapcore.v:194: Define or directive not defined: '`DEFAULT_CURRENT'\n                      .default_current(`DEFAULT_CURRENT),\n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/208556773/src/rapcore.v:196: Define or directive not defined: '`BUFFER_SIZE'\n                      .BUFFER_SIZE(`BUFFER_SIZE),\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/208556773/src/rapcore.v:197: Define or directive not defined: '`DEFAULT_CLOCK_DIVISOR'\n                      .default_clock_divisor(`DEFAULT_CLOCK_DIVISOR),\n                                             ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/208556773/src/rapcore.v:198: Define or directive not defined: '`ENCODER_BITS'\n                      .encoder_bits(`ENCODER_BITS),\n                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/208556773/src/rapcore.v:199: Define or directive not defined: '`USE_DDA'\n                      .use_dda(`USE_DDA)) spifsm\n                               ^~~~~~~~\n%Error: Exiting due to 13 error(s)\n"
module rapcore #(
  parameter num_motors = `MOTOR_COUNT,
  parameter move_duration_bits = `MOVE_DURATION_BITS
  )(
    `ifdef LED
      output wire [`LED:1] LED,
    `endif
    `ifdef tinyfpgabx
      output USBPU,
    `endif
    `ifdef SPI_INTERFACE
      input  wire SCK,
      input  wire CS,
      input  wire COPI,
      output wire CIPO,
    `endif
    `ifdef DUAL_HBRIDGE
      output wire [`DUAL_HBRIDGE-1:0] PHASE_A1,
      output wire [`DUAL_HBRIDGE-1:0] PHASE_A2,
      output wire [`DUAL_HBRIDGE-1:0] PHASE_B1,
      output wire [`DUAL_HBRIDGE-1:0] PHASE_B2,
    `endif
    `ifdef VREF_AB
      output wire [`DUAL_HBRIDGE-1:0] VREF_A,
      output wire [`DUAL_HBRIDGE-1:0] VREF_B,
    `endif
    `ifdef ULTIBRIDGE
      output wire CHARGEPUMP,
      input  wire [`ULTIBRIDGE-1:0] analog_cmp1,
      output wire [`ULTIBRIDGE-1:0] analog_out1,
      input  wire [`ULTIBRIDGE-1:0] analog_cmp2,
      output wire [`ULTIBRIDGE-1:0] analog_out2,
      output wire [`ULTIBRIDGE-1:0] PHASE_A1,
      output wire [`ULTIBRIDGE-1:0] PHASE_A2,
      output wire [`ULTIBRIDGE-1:0] PHASE_B1,
      output wire [`ULTIBRIDGE-1:0] PHASE_B2,
      output wire [`ULTIBRIDGE-1:0] PHASE_A1_H,
      output wire [`ULTIBRIDGE-1:0] PHASE_A2_H,
      output wire [`ULTIBRIDGE-1:0] PHASE_B1_H,
      output wire [`ULTIBRIDGE-1:0] PHASE_B2_H,
    `endif
    `ifdef QUAD_ENC
      input wire [`QUAD_ENC-1:0] ENC_B,
      input wire [`QUAD_ENC-1:0] ENC_A,
    `endif
    `ifdef BUFFER_DTR
      output wire BUFFER_DTR,
    `endif
    `ifdef MOVE_DONE
      output wire MOVE_DONE,
    `endif
    `ifdef HALT
      input wire HALT,
    `endif
    `ifdef STEPINPUT
      input wire [num_motors-1:0] STEPINPUT,
      input wire [num_motors-1:0] DIRINPUT,
      input wire [num_motors-1:0] ENINPUT,
    `endif
    `ifdef STEPOUTPUT
      output wire [num_motors-1:0] STEPOUTPUT,
      output wire [num_motors-1:0] ENOUTPUT,
      output wire [num_motors-1:0] DIROUTPUT,
    `endif
    `ifdef LA_IN
      input wire [`LA_IN:1] LA_IN,
    `endif
    `ifdef LA_OUT
      output wire [`LA_OUT:1] LA_OUT,
    `endif
    `ifdef RESETN
      input resetn_in,
    `endif
    input CLK
);

  `ifdef tinyfpgabx

    assign USBPU = 0;
  `endif




  `ifndef BUFFER_DTR
    wire BUFFER_DTR;
  `endif
  `ifndef MOVE_DONE
    wire MOVE_DONE;
  `endif
  `ifndef HALT
    wire HALT;
  `endif


  `ifdef QUAD_ENC
    localparam num_encoders = `QUAD_ENC;
  `else
    localparam num_encoders = 0;
  `endif





  `ifndef BUFFERED_PLL
    wire buffered_clk = CLK;
  `else
    wire buffered_clk;
  `endif


  `ifdef PWMPLL

    wire pwm_clock;
    wire pwmpll_locked;
    `ifndef BUFFERED_PLL
      pwm_pll ppll (.clock_in(CLK),
                    .clock_out(pwm_clock),
                    .locked(pwmpll_locked));
    `else


      pwm_pll ppll (.clock_in(CLK),
                    .clock_out(pwm_clock),
                    .clock_out_buffered(buffered_clk),
                    .locked(pwmpll_locked));
    `endif
  `else
    wire pwm_clock = buffered_clk;
  `endif


  `ifdef SPIPLL
    wire spi_clock;
    wire spipll_locked;
    spi_pll ppll (.clock_in(CLK),
                  .clock_out(spi_clock),
                  .locked(pwmpll_locked));
  `else
    wire spi_clock = buffered_clk;
  `endif



  wire resetn;
  assign resetn = &resetn_counter;
  `ifdef RESETN
    reg [7:0] resetn_counter;
    always @(posedge buffered_clk)
    if(!resetn_in)
      resetn_counter <= 0;
    else
      resetn_counter <= resetn_counter + !resetn;
  `endif
  `ifndef RESETN
    reg [7:0] resetn_counter = 0;
    always @(posedge buffered_clk) begin
      resetn_counter <= resetn_counter + !resetn;
    end
  `endif
  wire reset = resetn;




  wire [63:0] word_send_data;
  wire [63:0] word_data_received;
  wire word_received;

  SPIWord word_proc (
                .clk(spi_clock),
                .resetn (resetn),
                .SCK(SCK),
                .CS(CS),
                .COPI(COPI),
                .CIPO(CIPO),
                .word_send_data(word_send_data),
                .word_received(word_received),
                .word_data_received(word_data_received));







  spi_state_machine #(.num_motors(num_motors),
                      .move_duration_bits(move_duration_bits),
                      .default_microsteps(`DEFAULT_MICROSTEPS),
                      .default_current(`DEFAULT_CURRENT),
                      .num_encoders(num_encoders),
                      .BUFFER_SIZE(`BUFFER_SIZE),
                      .default_clock_divisor(`DEFAULT_CLOCK_DIVISOR),
                      .encoder_bits(`ENCODER_BITS),
                      .use_dda(`USE_DDA)) spifsm
  (

  `ifdef DUAL_HBRIDGE
    .PHASE_A1(PHASE_A1),
    .PHASE_A2(PHASE_A2),
    .PHASE_B1(PHASE_B1),
    .PHASE_B2(PHASE_B2),
  `endif
  `ifdef VREF_AB
    .VREF_A(VREF_A),
    .VREF_B(VREF_B),
  `endif
  `ifdef ULTIBRIDGE
    .CHARGEPUMP (CHARGEPUMP ),
    .analog_cmp1(analog_cmp1),
    .analog_out1(analog_out1),
    .analog_cmp2(analog_cmp2),
    .analog_out2(analog_out2),
    .PHASE_A1(PHASE_A1),
    .PHASE_A2(PHASE_A2),
    .PHASE_B1(PHASE_B1),
    .PHASE_B2(PHASE_B2),
    .PHASE_A1_H(PHASE_A1_H),
    .PHASE_A2_H(PHASE_A2_H),
    .PHASE_B1_H(PHASE_B1_H),
    .PHASE_B2_H(PHASE_B2_H),
  `endif
  `ifdef QUAD_ENC
    .ENC_B(ENC_B),
    .ENC_A(ENC_A),
  `endif




    `ifdef STEPINPUT
      .STEPINPUT(STEPINPUT),
      .DIRINPUT(DIRINPUT),
      .ENINPUT(ENINPUT),
    `endif
    `ifdef STEPOUTPUT
      .STEPOUTPUT(STEPOUTPUT),
      .DIROUTPUT(DIROUTPUT),
      .ENOUTPUT(ENOUTPUT),
    `endif

    .CLK(CLK),
    .pwm_clock(pwm_clock),
    .resetn(resetn),

    .word_data_received(word_data_received),
    .word_send_data(word_send_data),
    .word_received(word_received),

    .buffer_dtr(BUFFER_DTR),
    .move_done(MOVE_DONE),
    .halt(HALT)

  );


endmodule
module rapcore #(
  parameter num_motors = `MOTOR_COUNT,
  parameter move_duration_bits = `MOVE_DURATION_BITS
  )(
    `ifdef LED
      output wire [`LED:1] LED,
    `endif
    `ifdef tinyfpgabx
      output USBPU,
    `endif
    `ifdef SPI_INTERFACE
      input  wire SCK,
      input  wire CS,
      input  wire COPI,
      output wire CIPO,
    `endif
    `ifdef DUAL_HBRIDGE
      output wire [`DUAL_HBRIDGE-1:0] PHASE_A1,
      output wire [`DUAL_HBRIDGE-1:0] PHASE_A2,
      output wire [`DUAL_HBRIDGE-1:0] PHASE_B1,
      output wire [`DUAL_HBRIDGE-1:0] PHASE_B2,
    `endif
    `ifdef VREF_AB
      output wire [`DUAL_HBRIDGE-1:0] VREF_A,
      output wire [`DUAL_HBRIDGE-1:0] VREF_B,
    `endif
    `ifdef ULTIBRIDGE
      output wire CHARGEPUMP,
      input  wire [`ULTIBRIDGE-1:0] analog_cmp1,
      output wire [`ULTIBRIDGE-1:0] analog_out1,
      input  wire [`ULTIBRIDGE-1:0] analog_cmp2,
      output wire [`ULTIBRIDGE-1:0] analog_out2,
      output wire [`ULTIBRIDGE-1:0] PHASE_A1,
      output wire [`ULTIBRIDGE-1:0] PHASE_A2,
      output wire [`ULTIBRIDGE-1:0] PHASE_B1,
      output wire [`ULTIBRIDGE-1:0] PHASE_B2,
      output wire [`ULTIBRIDGE-1:0] PHASE_A1_H,
      output wire [`ULTIBRIDGE-1:0] PHASE_A2_H,
      output wire [`ULTIBRIDGE-1:0] PHASE_B1_H,
      output wire [`ULTIBRIDGE-1:0] PHASE_B2_H,
    `endif
    `ifdef QUAD_ENC
      input wire [`QUAD_ENC-1:0] ENC_B,
      input wire [`QUAD_ENC-1:0] ENC_A,
    `endif
    `ifdef BUFFER_DTR
      output wire BUFFER_DTR,
    `endif
    `ifdef MOVE_DONE
      output wire MOVE_DONE,
    `endif
    `ifdef HALT
      input wire HALT,
    `endif
    `ifdef STEPINPUT
      input wire [num_motors-1:0] STEPINPUT,
      input wire [num_motors-1:0] DIRINPUT,
      input wire [num_motors-1:0] ENINPUT,
    `endif
    `ifdef STEPOUTPUT
      output wire [num_motors-1:0] STEPOUTPUT,
      output wire [num_motors-1:0] ENOUTPUT,
      output wire [num_motors-1:0] DIROUTPUT,
    `endif
    `ifdef LA_IN
      input wire [`LA_IN:1] LA_IN,
    `endif
    `ifdef LA_OUT
      output wire [`LA_OUT:1] LA_OUT,
    `endif
    `ifdef RESETN
      input resetn_in,
    `endif
    input CLK
);


  `ifdef tinyfpgabx

    assign USBPU = 0;
  `endif




  `ifndef BUFFER_DTR
    wire BUFFER_DTR;
  `endif
  `ifndef MOVE_DONE
    wire MOVE_DONE;
  `endif
  `ifndef HALT
    wire HALT;
  `endif


  `ifdef QUAD_ENC
    localparam num_encoders = `QUAD_ENC;
  `else
    localparam num_encoders = 0;
  `endif





  `ifndef BUFFERED_PLL
    wire buffered_clk = CLK;
  `else
    wire buffered_clk;
  `endif


  `ifdef PWMPLL

    wire pwm_clock;
    wire pwmpll_locked;
    `ifndef BUFFERED_PLL
      pwm_pll ppll (.clock_in(CLK),
                    .clock_out(pwm_clock),
                    .locked(pwmpll_locked));
    `else


      pwm_pll ppll (.clock_in(CLK),
                    .clock_out(pwm_clock),
                    .clock_out_buffered(buffered_clk),
                    .locked(pwmpll_locked));
    `endif
  `else
    wire pwm_clock = buffered_clk;
  `endif


  `ifdef SPIPLL
    wire spi_clock;
    wire spipll_locked;
    spi_pll ppll (.clock_in(CLK),
                  .clock_out(spi_clock),
                  .locked(pwmpll_locked));
  `else
    wire spi_clock = buffered_clk;
  `endif



  wire resetn;
  assign resetn = &resetn_counter;
  `ifdef RESETN
    reg [7:0] resetn_counter;
    always @(posedge buffered_clk)
    if(!resetn_in)
      resetn_counter <= 0;
    else
      resetn_counter <= resetn_counter + !resetn;
  `endif
  `ifndef RESETN
    reg [7:0] resetn_counter = 0;
    always @(posedge buffered_clk) begin
      resetn_counter <= resetn_counter + !resetn;
    end
  `endif
  wire reset = resetn;




  wire [63:0] word_send_data;
  wire [63:0] word_data_received;
  wire word_received;

  SPIWord word_proc (
                .clk(spi_clock),
                .resetn (resetn),
                .SCK(SCK),
                .CS(CS),
                .COPI(COPI),
                .CIPO(CIPO),
                .word_send_data(word_send_data),
                .word_received(word_received),
                .word_data_received(word_data_received));







  spi_state_machine #(.num_motors(num_motors),
                      .move_duration_bits(move_duration_bits),
                      .default_microsteps(`DEFAULT_MICROSTEPS),
                      .default_current(`DEFAULT_CURRENT),
                      .num_encoders(num_encoders),
                      .BUFFER_SIZE(`BUFFER_SIZE),
                      .default_clock_divisor(`DEFAULT_CLOCK_DIVISOR),
                      .encoder_bits(`ENCODER_BITS),
                      .use_dda(`USE_DDA)) spifsm
  (

  `ifdef DUAL_HBRIDGE
    .PHASE_A1(PHASE_A1),
    .PHASE_A2(PHASE_A2),
    .PHASE_B1(PHASE_B1),
    .PHASE_B2(PHASE_B2),
  `endif
  `ifdef VREF_AB
    .VREF_A(VREF_A),
    .VREF_B(VREF_B),
  `endif
  `ifdef ULTIBRIDGE
    .CHARGEPUMP (CHARGEPUMP ),
    .analog_cmp1(analog_cmp1),
    .analog_out1(analog_out1),
    .analog_cmp2(analog_cmp2),
    .analog_out2(analog_out2),
    .PHASE_A1(PHASE_A1),
    .PHASE_A2(PHASE_A2),
    .PHASE_B1(PHASE_B1),
    .PHASE_B2(PHASE_B2),
    .PHASE_A1_H(PHASE_A1_H),
    .PHASE_A2_H(PHASE_A2_H),
    .PHASE_B1_H(PHASE_B1_H),
    .PHASE_B2_H(PHASE_B2_H),
  `endif
  `ifdef QUAD_ENC
    .ENC_B(ENC_B),
    .ENC_A(ENC_A),
  `endif




    `ifdef STEPINPUT
      .STEPINPUT(STEPINPUT),
      .DIRINPUT(DIRINPUT),
      .ENINPUT(ENINPUT),
    `endif
    `ifdef STEPOUTPUT
      .STEPOUTPUT(STEPOUTPUT),
      .DIROUTPUT(DIROUTPUT),
      .ENOUTPUT(ENOUTPUT),
    `endif

    .CLK(CLK),
    .pwm_clock(pwm_clock),
    .resetn(resetn),

    .word_data_received(word_data_received),
    .word_send_data(word_send_data),
    .word_received(word_received),

    .buffer_dtr(BUFFER_DTR),
    .move_done(MOVE_DONE),
    .halt(HALT)

  );


endmodule