data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:11: Little bit endian vector: MSB < LSB of bit range: -1:0\noutput reg signed [SIZE_1-1:0] qp;        \n                  ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:12: Little bit endian vector: MSB < LSB of bit range: -1:0\noutput reg signed [(SIZE_2)*1-1:0] qtp;        \n                  ^\n%Warning-LITENDIAN: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:13: Little bit endian vector: MSB < LSB of bit range: -1:0\noutput reg signed [SIZE_9-1:0] qw;       \n                  ^\n%Warning-LITENDIAN: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:14: Little bit endian vector: MSB < LSB of bit range: -1:0\ninput signed [SIZE_1-1:0] dp;    \n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:15: Little bit endian vector: MSB < LSB of bit range: -1:0\ninput signed [(SIZE_2)*1-1:0] dtp;    \n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:16: Little bit endian vector: MSB < LSB of bit range: -1:0\ninput signed [SIZE_9-1:0] dw;    \n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:17: Little bit endian vector: MSB < LSB of bit range: -1:0\ninput [SIZE_address_pix-1:0] write_addressp, read_addressp;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:18: Little bit endian vector: MSB < LSB of bit range: -1:0\ninput [SIZE_address_pix_t-1:0] write_addresstp, read_addresstp;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:19: Little bit endian vector: MSB < LSB of bit range: -1:0\ninput [SIZE_address_wei-1:0] write_addressw, read_addressw;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:22: Little bit endian vector: MSB < LSB of bit range: -1:0\nreg signed [SIZE_1-1:0] mem [0:picture_size*picture_size*8+picture_size*picture_size-1];\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:23: Little bit endian vector: MSB < LSB of bit range: -1:0\nreg signed [(SIZE_2)*1-1:0] mem_t [0:picture_size*picture_size*4-1];\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:24: Little bit endian vector: MSB < LSB of bit range: -1:0\nreg signed [SIZE_9-1:0] weight [0:256];\n           ^\n%Warning-WIDTH: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:29: Bit extraction of array[256:0] requires 9 bit index, not 2 bits.\n                                                                                   : ... In instance RAM\n  if (we_w) weight[write_addressw] <= dw;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/126160535/verilog/code/neuroset/RAM.v:35: Bit extraction of array[256:0] requires 9 bit index, not 2 bits.\n                                                                                   : ... In instance RAM\n        if (re_w) qw <= weight[read_addressw];\n                              ^\n%Error: Exiting due to 14 warning(s)\n'
module RAM(qp,qtp,qw,dp,dtp,dw,write_addressp,read_addressp,write_addresstp,read_addresstp,write_addressw,read_addressw,we_p,we_tp,we_w,re_p,re_tp,re_w,clk);
parameter picture_size=0;
parameter SIZE_1=0;
parameter SIZE_2=0;
parameter SIZE_4=0;
parameter SIZE_9=0;
parameter SIZE_address_pix=0;
parameter SIZE_address_pix_t=0;
parameter SIZE_address_wei=0;

output reg signed [SIZE_1-1:0] qp;
output reg signed [(SIZE_2)*1-1:0] qtp;
output reg signed [SIZE_9-1:0] qw;
input signed [SIZE_1-1:0] dp;
input signed [(SIZE_2)*1-1:0] dtp;
input signed [SIZE_9-1:0] dw;
input [SIZE_address_pix-1:0] write_addressp, read_addressp;
input [SIZE_address_pix_t-1:0] write_addresstp, read_addresstp;
input [SIZE_address_wei-1:0] write_addressw, read_addressw;
input we_p,we_tp,we_w,re_p,re_tp,re_w,clk;

reg signed [SIZE_1-1:0] mem [0:picture_size*picture_size*8+picture_size*picture_size-1];
reg signed [(SIZE_2)*1-1:0] mem_t [0:picture_size*picture_size*4-1];
reg signed [SIZE_9-1:0] weight [0:256];
always @ (posedge clk)
    begin
        if (we_p) mem[write_addressp] <= dp;
		if (we_tp) mem_t[write_addresstp] <= dtp;
		if (we_w) weight[write_addressw] <= dw;
    end
always @ (posedge clk)
    begin
        if (re_p) qp <= mem[read_addressp];
		if (re_tp) qtp <= mem_t[read_addresstp];
        if (re_w) qw <= weight[read_addressw];
    end
endmodule
module RAM(qp,qtp,qw,dp,dtp,dw,write_addressp,read_addressp,write_addresstp,read_addresstp,write_addressw,read_addressw,we_p,we_tp,we_w,re_p,re_tp,re_w,clk);

parameter picture_size=0;
parameter SIZE_1=0;
parameter SIZE_2=0;
parameter SIZE_4=0;
parameter SIZE_9=0;
parameter SIZE_address_pix=0;
parameter SIZE_address_pix_t=0;
parameter SIZE_address_wei=0;

output reg signed [SIZE_1-1:0] qp;
output reg signed [(SIZE_2)*1-1:0] qtp;
output reg signed [SIZE_9-1:0] qw;
input signed [SIZE_1-1:0] dp;
input signed [(SIZE_2)*1-1:0] dtp;
input signed [SIZE_9-1:0] dw;
input [SIZE_address_pix-1:0] write_addressp, read_addressp;
input [SIZE_address_pix_t-1:0] write_addresstp, read_addresstp;
input [SIZE_address_wei-1:0] write_addressw, read_addressw;
input we_p,we_tp,we_w,re_p,re_tp,re_w,clk;

reg signed [SIZE_1-1:0] mem [0:picture_size*picture_size*8+picture_size*picture_size-1];
reg signed [(SIZE_2)*1-1:0] mem_t [0:picture_size*picture_size*4-1];
reg signed [SIZE_9-1:0] weight [0:256];
always @ (posedge clk)
    begin
        if (we_p) mem[write_addressp] <= dp;
		if (we_tp) mem_t[write_addresstp] <= dtp;
		if (we_w) weight[write_addressw] <= dw;
    end
always @ (posedge clk)
    begin
        if (re_p) qp <= mem[read_addressp];
		if (re_tp) qtp <= mem_t[read_addresstp];
        if (re_w) qw <= weight[read_addressw];
    end
endmodule