data/full_repos/permissive/118895561/Project 2/regfilepc.v
1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/118895561\n        ... Looked in:\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561.v\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561.sv\n             2,data/full_repos/permissive/118895561\n             2,data/full_repos/permissive/118895561.v\n             2,data/full_repos/permissive/118895561.sv\n             obj_dir/2,data/full_repos/permissive/118895561\n             obj_dir/2,data/full_repos/permissive/118895561.v\n             obj_dir/2,data/full_repos/permissive/118895561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/118895561/Project\n%Error: Cannot find file containing module: 2/regfilepc.v\n%Error: Exiting due to 3 error(s)\n'
module regfilepc #(parameter WIDTH = 8)(
	input clk,
	input reset,
	input stall,
	input [WIDTH-1:0] Data_In,
	output reg [WIDTH-1:0] Data_Out,
	output PC_EXP,
	input  INT_REQ
    );
	
	assign PC_EXP = ((Data_Out >= 32'h0000_3000) && (Data_Out <= 32'h0000_4fff) && Data_Out[1:0] == 2'b0) ? 1'b0 :
																																			  1'b1 ;
	
	initial begin
		Data_Out <=  32'h0000_3000;
	end
	
	always @ (posedge clk)
		if(reset) begin
			Data_Out <=  32'h0000_3000;
		end	
		else if(stall == 0 || INT_REQ) begin
			Data_Out <=  Data_In;
		end
endmodule
module regfilepc #(parameter WIDTH = 8)(
	input clk,
	input reset,
	input stall,
	input [WIDTH-1:0] Data_In,
	output reg [WIDTH-1:0] Data_Out,
	output PC_EXP,
	input  INT_REQ
    );

	
	assign PC_EXP = ((Data_Out >= 32'h0000_3000) && (Data_Out <= 32'h0000_4fff) && Data_Out[1:0] == 2'b0) ? 1'b0 :
																																			  1'b1 ;
	
	initial begin
		Data_Out <=  32'h0000_3000;
	end
	
	always @ (posedge clk)
		if(reset) begin
			Data_Out <=  32'h0000_3000;
		end	
		else if(stall == 0 || INT_REQ) begin
			Data_Out <=  Data_In;
		end
endmodule