data/full_repos/permissive/152183157/IC_CDesign8.v
 line:279: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/152183157/IC_CDesign8.v:269: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk=~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/152183157/IC_CDesign8.v:279: Unsupported: Ignoring delay on this delayed statement.\n #500 $stop;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/152183157/IC_CDesign8.v:132: Multiple top level modules\n                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                         : ... Top module \'oreg\'\nmodule oreg(output reg [8:0]oregout,\n       ^~~~\n                                                                         : ... Top module \'remreg\'\nmodule remreg();\n       ^~~~~~\n                                                                         : ... Top module \'complement\'\nmodule complement(output reg [8:0]comout,\n       ^~~~~~~~~~\n                                                                         : ... Top module \'IC\'\nmodule IC;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/152183157/IC_CDesign8.v:85: Operator ADD expects 9 bits on the RHS, but RHS\'s ARRAYSEL generates 1 bits.\n                                                                     : ... In instance IC.icw\nassign resulttmp[9]=resulttmp[8]+resone[9];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/152183157/IC_CDesign8.v:92: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 10 bits.\n                                                                     : ... In instance IC.icw\n  remainder=remaindertmp[8];\n           ^\n%Warning-WIDTH: data/full_repos/permissive/152183157/IC_CDesign8.v:94: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 10 bits.\n                                                                     : ... In instance IC.icw\n  remainder=remaindertmp[9];\n           ^\n%Warning-WIDTH: data/full_repos/permissive/152183157/IC_CDesign8.v:173: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'comtmp\' generates 8 bits.\n                                                                      : ... In instance complement\n comout=comtmp;\n       ^\n%Warning-INFINITELOOP: data/full_repos/permissive/152183157/IC_CDesign8.v:269: Infinite loop (condition always true)\n                                                                             : ... In instance IC\n forever #10 clk=~clk;\n ^~~~~~~\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module IC;
wire [1:0]sign;
wire [8:0]remainder;
wire [8:0]result;
reg [8:0]divisor;
reg [8:0]dividend;
reg clk;

initial
begin
	clk=1'b0;
	forever #10 clk=~clk;
end


initial
begin

	dividend=9'b0_1011_0000;
	divisor=9'b0_0001_0101;
	#500 $stop;
end


IC_CDesign icw(sign,remainder,result,dividend,divisor,clk);
endmodule
module IC;

wire [1:0]sign;
wire [8:0]remainder;
wire [8:0]result;
reg [8:0]divisor;
reg [8:0]dividend;
reg clk;

initial
begin
	clk=1'b0;
	forever #10 clk=~clk;
end


initial
begin

	dividend=9'b0_1011_0000;
	divisor=9'b0_0001_0101;
	#500 $stop;
end


IC_CDesign icw(sign,remainder,result,dividend,divisor,clk);
endmodule