data/full_repos/permissive/120518070/main/source/tb_counterI.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_counterI.sv:15: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_counterI.sv:17: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_counterI.sv:35: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_counterI.sv:39: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_counterI.sv:43: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_counterI.sv:47: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_counterI.sv:51: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_counterI.sv:55: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_counterI();
	localparam CLK_PERIOD = 20;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	reg tb_n_rst;
	reg tb_clear;
	reg tb_count_enable;
	reg tb_rollover_flag;
	reg [7:0] tb_count_out;
		
	counterI DUT 
			(.clk(tb_clk),.n_rst(tb_n_rst),.clear(tb_clear),.count_enable(tb_count_enable),
			   .rollover_val(8'b11111111),.count_out(tb_count_out),.rollover_flag(tb_rollover_flag));

	initial
	begin
	tb_n_rst = 0;
	tb_clear = 0;
	tb_count_enable = 0;
	@(negedge tb_clk);
	tb_n_rst = 1;
	tb_clear = 0;
	tb_count_enable = 0;
	@(negedge tb_clk);
	tb_n_rst = 1;
	tb_clear = 0;
	tb_count_enable = 1;
	@(negedge tb_clk);
	tb_n_rst = 1;
	tb_clear = 0;
	tb_count_enable = 1;
	@(negedge tb_clk);
	tb_n_rst = 1;
	tb_clear = 0;
	tb_count_enable = 1;
	@(negedge tb_clk);
	tb_n_rst = 1;
	tb_clear = 1;
	tb_count_enable = 0;
	@(negedge tb_clk);
	tb_n_rst = 1;
	tb_clear = 0;
	tb_count_enable = 1;
	end
endmodule
module tb_counterI();

	localparam CLK_PERIOD = 20;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	reg tb_n_rst;
	reg tb_clear;
	reg tb_count_enable;
	reg tb_rollover_flag;
	reg [7:0] tb_count_out;
		
	counterI DUT 
			(.clk(tb_clk),.n_rst(tb_n_rst),.clear(tb_clear),.count_enable(tb_count_enable),
			   .rollover_val(8'b11111111),.count_out(tb_count_out),.rollover_flag(tb_rollover_flag));

	initial
	begin
	tb_n_rst = 0;
	tb_clear = 0;
	tb_count_enable = 0;
	@(negedge tb_clk);
	tb_n_rst = 1;
	tb_clear = 0;
	tb_count_enable = 0;
	@(negedge tb_clk);
	tb_n_rst = 1;
	tb_clear = 0;
	tb_count_enable = 1;
	@(negedge tb_clk);
	tb_n_rst = 1;
	tb_clear = 0;
	tb_count_enable = 1;
	@(negedge tb_clk);
	tb_n_rst = 1;
	tb_clear = 0;
	tb_count_enable = 1;
	@(negedge tb_clk);
	tb_n_rst = 1;
	tb_clear = 1;
	tb_count_enable = 0;
	@(negedge tb_clk);
	tb_n_rst = 1;
	tb_clear = 0;
	tb_count_enable = 1;
	end
endmodule