data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v
None: at end of input
1: b'%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:11: Cannot find include file: riscv_defs.v\n`include "riscv_defs.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v.v\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v.sv\n             riscv_defs.v\n             riscv_defs.v.v\n             riscv_defs.v.sv\n             obj_dir/riscv_defs.v\n             obj_dir/riscv_defs.v.v\n             obj_dir/riscv_defs.v.sv\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:20: Define or directive not defined: \'`RV_XLEN\'\n        input  wire    [`RV_XLEN-1:0] op_left_i,\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:21: Define or directive not defined: \'`RV_XLEN\'\n        input  wire    [`RV_XLEN-1:0] op_right_i,\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:22: Define or directive not defined: \'`RV_XLEN\'\n        output reg     [`RV_XLEN-1:0] op_result_o,\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:23: Define or directive not defined: \'`RV_ALUOP_RANGE\'\n        input  wire [`RV_ALUOP_RANGE] op_opcode_i,\n                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        input  wire [`RV_ALUOP_RANGE] op_opcode_i,\n                                    ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:25: Define or directive not defined: \'`RV_XLEN\'\n        input  wire    [`RV_XLEN-1:0] cmp_left_i,\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input  wire    [`RV_XLEN-1:0] cmp_right_i,\n        ^~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:26: Define or directive not defined: \'`RV_XLEN\'\n        input  wire    [`RV_XLEN-1:0] cmp_right_i,\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n        output reg                    cmp_result_o,\n        ^~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:28: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n        input  wire             [2:0] cmp_opcode_i\n        ^~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:29: syntax error, unexpected \')\', expecting \',\' or \';\'\n    );\n    ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:35: Define or directive not defined: \'`RV_XLEN\'\n    reg  [`RV_XLEN-1:0] op_result_mux_out;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:37: syntax error, unexpected genvar\n    genvar              genvar_i;\n    ^~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:38: Define or directive not defined: \'`RV_XLEN\'\n    reg  [`RV_XLEN-1:0] shift_left_array[0:`RV_XLEN_X];\n          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:38: Define or directive not defined: \'`RV_XLEN_X\'\n    reg  [`RV_XLEN-1:0] shift_left_array[0:`RV_XLEN_X];\n                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg  [`RV_XLEN-1:0] shift_left_array[0:`RV_XLEN_X];\n                                                     ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:39: Define or directive not defined: \'`RV_XLEN\'\n    reg  [`RV_XLEN-1:0] shift_right_array[0:`RV_XLEN_X];\n          ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:39: Define or directive not defined: \'`RV_XLEN_X\'\n    reg  [`RV_XLEN-1:0] shift_right_array[0:`RV_XLEN_X];\n                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg  [`RV_XLEN-1:0] shift_right_array[0:`RV_XLEN_X];\n                                                      ^\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:50: syntax error, unexpected always\n    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:50: Define or directive not defined: \'`RV_SYNC_LOGIC_CLOCK\'\n    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin\n             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:61: Define or directive not defined: \'`RV_XLEN\'\n        op_result_mux_out = { `RV_XLEN {1\'b0} };  \n                              ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:63: Define or directive not defined: \'`RV_ALUOP_ADD\'\n            `RV_ALUOP_ADD  : op_result_mux_out = op_left_i + op_right_i;\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:64: Define or directive not defined: \'`RV_ALUOP_SUB\'\n            `RV_ALUOP_SUB  : op_result_mux_out = op_left_i - op_right_i;\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:65: Define or directive not defined: \'`RV_ALUOP_SLL\'\n            `RV_ALUOP_SLL  : op_result_mux_out = shift_left_array[`RV_XLEN_X];\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:65: Define or directive not defined: \'`RV_XLEN_X\'\n            `RV_ALUOP_SLL  : op_result_mux_out = shift_left_array[`RV_XLEN_X];\n                                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:66: Define or directive not defined: \'`RV_ALUOP_SLT\'\n            `RV_ALUOP_SLT  : op_result_mux_out = { { `RV_XLEN-1 {1\'b0} }, cmp_lts };\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:66: Define or directive not defined: \'`RV_XLEN\'\n            `RV_ALUOP_SLT  : op_result_mux_out = { { `RV_XLEN-1 {1\'b0} }, cmp_lts };\n                                                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:67: Define or directive not defined: \'`RV_ALUOP_SLTU\'\n            `RV_ALUOP_SLTU : op_result_mux_out = { { `RV_XLEN-1 {1\'b0} }, cmp_ltu };\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:67: Define or directive not defined: \'`RV_XLEN\'\n            `RV_ALUOP_SLTU : op_result_mux_out = { { `RV_XLEN-1 {1\'b0} }, cmp_ltu };\n                                                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:68: Define or directive not defined: \'`RV_ALUOP_XOR\'\n            `RV_ALUOP_XOR  : op_result_mux_out = op_left_i ^ op_right_i;\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:69: Define or directive not defined: \'`RV_ALUOP_SRL\'\n            `RV_ALUOP_SRL  : op_result_mux_out = shift_right_array[`RV_XLEN_X];\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:69: Define or directive not defined: \'`RV_XLEN_X\'\n            `RV_ALUOP_SRL  : op_result_mux_out = shift_right_array[`RV_XLEN_X];\n                                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:70: Define or directive not defined: \'`RV_ALUOP_SRA\'\n            `RV_ALUOP_SRA  : op_result_mux_out = shift_right_array[`RV_XLEN_X];\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:70: Define or directive not defined: \'`RV_XLEN_X\'\n            `RV_ALUOP_SRA  : op_result_mux_out = shift_right_array[`RV_XLEN_X];\n                                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:71: Define or directive not defined: \'`RV_ALUOP_OR\'\n            `RV_ALUOP_OR   : op_result_mux_out = op_left_i | op_right_i;\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:72: Define or directive not defined: \'`RV_ALUOP_AND\'\n            `RV_ALUOP_AND  : op_result_mux_out = op_left_i & op_right_i;\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:73: Define or directive not defined: \'`RV_ALUOP_MOV\'\n            `RV_ALUOP_MOV  : op_result_mux_out = op_right_i;\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:88: Define or directive not defined: \'`RV_XLEN_X\'\n    generate for (genvar_i = 0; genvar_i < `RV_XLEN_X; genvar_i = genvar_i + 1) begin : shifter\n                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:93: Define or directive not defined: \'`RV_XLEN\'\n                shift_left_array[genvar_i + 1][`RV_XLEN - 1:2**genvar_i] = shift_left_array[genvar_i][`RV_XLEN - 1 - 2**genvar_i:0];\n                                               ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:93: Define or directive not defined: \'`RV_XLEN\'\n                shift_left_array[genvar_i + 1][`RV_XLEN - 1:2**genvar_i] = shift_left_array[genvar_i][`RV_XLEN - 1 - 2**genvar_i:0];\n                                                                                                      ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:95: Define or directive not defined: \'`RV_ALUOP_SRA\'\n                if (op_opcode_i == `RV_ALUOP_SRA && op_left_i[`RV_XLEN-1] == 1\'b1) begin\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:95: Define or directive not defined: \'`RV_XLEN\'\n                if (op_opcode_i == `RV_ALUOP_SRA && op_left_i[`RV_XLEN-1] == 1\'b1) begin\n                                                              ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:96: Define or directive not defined: \'`RV_XLEN\'\n                    shift_right_array[genvar_i + 1][`RV_XLEN - 1:`RV_XLEN - 2**genvar_i] = { 2**genvar_i {1\'b1} };\n                                                    ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:96: Define or directive not defined: \'`RV_XLEN\'\n                    shift_right_array[genvar_i + 1][`RV_XLEN - 1:`RV_XLEN - 2**genvar_i] = { 2**genvar_i {1\'b1} };\n                                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:98: Define or directive not defined: \'`RV_XLEN\'\n                    shift_right_array[genvar_i + 1][`RV_XLEN - 1:`RV_XLEN - 2**genvar_i] = { 2**genvar_i {1\'b0} };\n                                                    ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:98: Define or directive not defined: \'`RV_XLEN\'\n                    shift_right_array[genvar_i + 1][`RV_XLEN - 1:`RV_XLEN - 2**genvar_i] = { 2**genvar_i {1\'b0} };\n                                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:100: Define or directive not defined: \'`RV_XLEN\'\n                shift_right_array[genvar_i + 1][`RV_XLEN - 1 - 2**genvar_i:0] = shift_right_array[genvar_i][`RV_XLEN - 1:2**genvar_i];\n                                                ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_alu.v:100: Define or directive not defined: \'`RV_XLEN\'\n                shift_right_array[genvar_i + 1][`RV_XLEN - 1 - 2**genvar_i:0] = shift_right_array[genvar_i][`RV_XLEN - 1:2**genvar_i];\n                                                                                                            ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module merlin_alu
    (

        input  wire                   clk_i,
        input  wire                   stage_en_i,
        input  wire                   reset_i,

        input  wire    [`RV_XLEN-1:0] op_left_i,
        input  wire    [`RV_XLEN-1:0] op_right_i,
        output reg     [`RV_XLEN-1:0] op_result_o,
        input  wire [`RV_ALUOP_RANGE] op_opcode_i,

        input  wire    [`RV_XLEN-1:0] cmp_left_i,
        input  wire    [`RV_XLEN-1:0] cmp_right_i,
        output reg                    cmp_result_o,
        input  wire             [2:0] cmp_opcode_i
    );





    reg  [`RV_XLEN-1:0] op_result_mux_out;

    genvar              genvar_i;
    reg  [`RV_XLEN-1:0] shift_left_array[0:`RV_XLEN_X];
    reg  [`RV_XLEN-1:0] shift_right_array[0:`RV_XLEN_X];

    reg                 cmp_lts;
    reg                 cmp_ltu;







    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
        if (stage_en_i) begin
            op_result_o <= op_result_mux_out;
        end
    end





    always @ (*) begin
        op_result_mux_out = { `RV_XLEN {1'b0} };
        case (op_opcode_i)
            `RV_ALUOP_ADD  : op_result_mux_out = op_left_i + op_right_i;
            `RV_ALUOP_SUB  : op_result_mux_out = op_left_i - op_right_i;
            `RV_ALUOP_SLL  : op_result_mux_out = shift_left_array[`RV_XLEN_X];
            `RV_ALUOP_SLT  : op_result_mux_out = { { `RV_XLEN-1 {1'b0} }, cmp_lts };
            `RV_ALUOP_SLTU : op_result_mux_out = { { `RV_XLEN-1 {1'b0} }, cmp_ltu };
            `RV_ALUOP_XOR  : op_result_mux_out = op_left_i ^ op_right_i;
            `RV_ALUOP_SRL  : op_result_mux_out = shift_right_array[`RV_XLEN_X];
            `RV_ALUOP_SRA  : op_result_mux_out = shift_right_array[`RV_XLEN_X];
            `RV_ALUOP_OR   : op_result_mux_out = op_left_i | op_right_i;
            `RV_ALUOP_AND  : op_result_mux_out = op_left_i & op_right_i;
            `RV_ALUOP_MOV  : op_result_mux_out = op_right_i;
            default : begin
            end
        endcase
    end





    always @ (*) begin
        shift_left_array[0]  = op_left_i;
        shift_right_array[0] = op_left_i;
    end

    generate for (genvar_i = 0; genvar_i < `RV_XLEN_X; genvar_i = genvar_i + 1) begin : shifter
        always @ (*) begin
            if (op_right_i[genvar_i] == 1'b1) begin

                shift_left_array[genvar_i + 1][2**genvar_i - 1:   0] = { 2**genvar_i {1'b0} };
                shift_left_array[genvar_i + 1][`RV_XLEN - 1:2**genvar_i] = shift_left_array[genvar_i][`RV_XLEN - 1 - 2**genvar_i:0];

                if (op_opcode_i == `RV_ALUOP_SRA && op_left_i[`RV_XLEN-1] == 1'b1) begin
                    shift_right_array[genvar_i + 1][`RV_XLEN - 1:`RV_XLEN - 2**genvar_i] = { 2**genvar_i {1'b1} };
                end else begin
                    shift_right_array[genvar_i + 1][`RV_XLEN - 1:`RV_XLEN - 2**genvar_i] = { 2**genvar_i {1'b0} };
                end
                shift_right_array[genvar_i + 1][`RV_XLEN - 1 - 2**genvar_i:0] = shift_right_array[genvar_i][`RV_XLEN - 1:2**genvar_i];
            end else begin

                shift_left_array[genvar_i + 1] = shift_left_array[genvar_i];

                shift_right_array[genvar_i + 1] = shift_right_array[genvar_i];
            end
        end
    end endgenerate





    always @ (*) begin
        cmp_lts = $signed(cmp_left_i) < $signed(cmp_right_i);
        cmp_ltu = cmp_left_i < cmp_right_i;
    end

    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
        if (stage_en_i) begin
            cmp_result_o <= 1'b0;
            case (cmp_opcode_i)
                `RV_ALUCOND_EQ  : begin
                    if (cmp_left_i == cmp_right_i) begin
                        cmp_result_o <= 1'b1;
                    end
                end
                `RV_ALUCOND_NE  : begin
                    if (cmp_left_i != cmp_right_i) begin
                        cmp_result_o <= 1'b1;
                    end
                end
                `RV_ALUCOND_LT  : begin
                    cmp_result_o <= cmp_lts;
                end
                `RV_ALUCOND_GE  : begin
                    cmp_result_o <= ~cmp_lts;
                end
                `RV_ALUCOND_LTU : begin
                    cmp_result_o <= cmp_ltu;
                end
                `RV_ALUCOND_GEU : begin
                    cmp_result_o <= ~cmp_ltu;
                end
                default : begin
                end
            endcase
        end
    end
endmodule
module merlin_alu
    (

        input  wire                   clk_i,
        input  wire                   stage_en_i,
        input  wire                   reset_i,

        input  wire    [`RV_XLEN-1:0] op_left_i,
        input  wire    [`RV_XLEN-1:0] op_right_i,
        output reg     [`RV_XLEN-1:0] op_result_o,
        input  wire [`RV_ALUOP_RANGE] op_opcode_i,

        input  wire    [`RV_XLEN-1:0] cmp_left_i,
        input  wire    [`RV_XLEN-1:0] cmp_right_i,
        output reg                    cmp_result_o,
        input  wire             [2:0] cmp_opcode_i
    );






    reg  [`RV_XLEN-1:0] op_result_mux_out;

    genvar              genvar_i;
    reg  [`RV_XLEN-1:0] shift_left_array[0:`RV_XLEN_X];
    reg  [`RV_XLEN-1:0] shift_right_array[0:`RV_XLEN_X];

    reg                 cmp_lts;
    reg                 cmp_ltu;







    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
        if (stage_en_i) begin
            op_result_o <= op_result_mux_out;
        end
    end





    always @ (*) begin
        op_result_mux_out = { `RV_XLEN {1'b0} };
        case (op_opcode_i)
            `RV_ALUOP_ADD  : op_result_mux_out = op_left_i + op_right_i;
            `RV_ALUOP_SUB  : op_result_mux_out = op_left_i - op_right_i;
            `RV_ALUOP_SLL  : op_result_mux_out = shift_left_array[`RV_XLEN_X];
            `RV_ALUOP_SLT  : op_result_mux_out = { { `RV_XLEN-1 {1'b0} }, cmp_lts };
            `RV_ALUOP_SLTU : op_result_mux_out = { { `RV_XLEN-1 {1'b0} }, cmp_ltu };
            `RV_ALUOP_XOR  : op_result_mux_out = op_left_i ^ op_right_i;
            `RV_ALUOP_SRL  : op_result_mux_out = shift_right_array[`RV_XLEN_X];
            `RV_ALUOP_SRA  : op_result_mux_out = shift_right_array[`RV_XLEN_X];
            `RV_ALUOP_OR   : op_result_mux_out = op_left_i | op_right_i;
            `RV_ALUOP_AND  : op_result_mux_out = op_left_i & op_right_i;
            `RV_ALUOP_MOV  : op_result_mux_out = op_right_i;
            default : begin
            end
        endcase
    end





    always @ (*) begin
        shift_left_array[0]  = op_left_i;
        shift_right_array[0] = op_left_i;
    end

    generate for (genvar_i = 0; genvar_i < `RV_XLEN_X; genvar_i = genvar_i + 1) begin : shifter
        always @ (*) begin
            if (op_right_i[genvar_i] == 1'b1) begin

                shift_left_array[genvar_i + 1][2**genvar_i - 1:   0] = { 2**genvar_i {1'b0} };
                shift_left_array[genvar_i + 1][`RV_XLEN - 1:2**genvar_i] = shift_left_array[genvar_i][`RV_XLEN - 1 - 2**genvar_i:0];

                if (op_opcode_i == `RV_ALUOP_SRA && op_left_i[`RV_XLEN-1] == 1'b1) begin
                    shift_right_array[genvar_i + 1][`RV_XLEN - 1:`RV_XLEN - 2**genvar_i] = { 2**genvar_i {1'b1} };
                end else begin
                    shift_right_array[genvar_i + 1][`RV_XLEN - 1:`RV_XLEN - 2**genvar_i] = { 2**genvar_i {1'b0} };
                end
                shift_right_array[genvar_i + 1][`RV_XLEN - 1 - 2**genvar_i:0] = shift_right_array[genvar_i][`RV_XLEN - 1:2**genvar_i];
            end else begin

                shift_left_array[genvar_i + 1] = shift_left_array[genvar_i];

                shift_right_array[genvar_i + 1] = shift_right_array[genvar_i];
            end
        end
    end endgenerate





    always @ (*) begin
        cmp_lts = $signed(cmp_left_i) < $signed(cmp_right_i);
        cmp_ltu = cmp_left_i < cmp_right_i;
    end

    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
        if (stage_en_i) begin
            cmp_result_o <= 1'b0;
            case (cmp_opcode_i)
                `RV_ALUCOND_EQ  : begin
                    if (cmp_left_i == cmp_right_i) begin
                        cmp_result_o <= 1'b1;
                    end
                end
                `RV_ALUCOND_NE  : begin
                    if (cmp_left_i != cmp_right_i) begin
                        cmp_result_o <= 1'b1;
                    end
                end
                `RV_ALUCOND_LT  : begin
                    cmp_result_o <= cmp_lts;
                end
                `RV_ALUCOND_GE  : begin
                    cmp_result_o <= ~cmp_lts;
                end
                `RV_ALUCOND_LTU : begin
                    cmp_result_o <= cmp_ltu;
                end
                `RV_ALUCOND_GEU : begin
                    cmp_result_o <= ~cmp_ltu;
                end
                default : begin
                end
            endcase
        end
    end
endmodule