data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v
1: b'%Warning-WIDTH: data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v:757: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h2a\' generates 6 bits.\n                                                                              : ... In instance pipeline_riscv.ALU\n    case (alu_code)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v:526: Operator EQ expects 6 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                              : ... In instance pipeline_riscv.CTRL\n    if (rd[1]!=0 && ((J_type[1] && funct[1]==7\'h08) || S_type[1]==6\'h2B)) begin\n                                                                ^~\n%Error: Exiting due to 2 warning(s)\n'
module reg_fwd(
  input             clk,
  input             nrst,
  input       [2:0] fwd_opA0,
  input       [2:0] fwd_opB0,
  input       [2:0] fwd_jr0,
  output reg  [2:0] fwd_opA,
  output reg  [2:0] fwd_opB,
  output reg  [2:0] fwd_sw,
  output      [2:0] fwd_jr
  );
  
  assign fwd_jr = fwd_jr0;
  
  always@(posedge clk) begin
    if (!nrst) begin
      fwd_opA <= 0;
      fwd_opB <= 0;
      fwd_sw  <= 0;
    end else begin
      fwd_opA <= fwd_opA0;
      fwd_opB <= fwd_opB0;
      fwd_sw  <= fwd_jr0;
    end
  end
endmodule
module reg_fwd(
  input             clk,
  input             nrst,
  input       [2:0] fwd_opA0,
  input       [2:0] fwd_opB0,
  input       [2:0] fwd_jr0,
  output reg  [2:0] fwd_opA,
  output reg  [2:0] fwd_opB,
  output reg  [2:0] fwd_sw,
  output      [2:0] fwd_jr
  );

  
  assign fwd_jr = fwd_jr0;
  
  always@(posedge clk) begin
    if (!nrst) begin
      fwd_opA <= 0;
      fwd_opB <= 0;
      fwd_sw  <= 0;
    end else begin
      fwd_opA <= fwd_opA0;
      fwd_opB <= fwd_opB0;
      fwd_sw  <= fwd_jr0;
    end
  end
endmodule