data/full_repos/permissive/197806087/vga/vgaimproved/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/197806087/vga/vgaimproved/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n                #5; clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/197806087/vga/vgaimproved/tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n                #5; clk = ~clk;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/vga/vgaimproved/tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n                #5; clk = ~clk;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/197806087/vga/vgaimproved/tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n                #5; clk = ~clk;\n                ^\n%Error: data/full_repos/permissive/197806087/vga/vgaimproved/tb.v:26: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("data/dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/197806087/vga/vgaimproved/tb.v:27: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/197806087/vga/vgaimproved/tb.v:30: Unsupported or unknown PLI call: $monitor\n        $monitor("At time=%2t, clk=%d, h_sync_pulse=%d, v_sync_pulse=%d",\n        ^~~~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
    reg clk;
    wire h_sync, h_porch, h_sync_pulse, v_sync, v_porch,
         v_sync_pulse;
    wire [1:0] R, G, B;
    counter c1(.clk(clk), .h_sync_pulse(h_sync_pulse),
            .v_sync_pulse(v_sync_pulse), .R(R), .G(G), .B(B));
    integer i;
    initial begin
        clk = 0;
        if(0) begin
            for(i = 0; i <= 1000; i = i+1) begin
                #5; clk = ~clk;
                #5; clk = ~clk;
            end
        end
        if(1) begin
            for(i = 0; i <= 200000; i = i+1) begin
                #5; clk = ~clk;
                #5; clk = ~clk;
            end
        end
    end
    initial begin
        $dumpfile("data/dumpfile.vcd");
        $dumpvars(0, tb);
    end
    initial begin
        $monitor("At time=%2t, clk=%d, h_sync_pulse=%d, v_sync_pulse=%d",
                $time, clk, h_sync_pulse, v_sync_pulse);
    end
endmodule
module tb;

    reg clk;
    wire h_sync, h_porch, h_sync_pulse, v_sync, v_porch,
         v_sync_pulse;
    wire [1:0] R, G, B;
    counter c1(.clk(clk), .h_sync_pulse(h_sync_pulse),
            .v_sync_pulse(v_sync_pulse), .R(R), .G(G), .B(B));
    integer i;
    initial begin
        clk = 0;
        if(0) begin
            for(i = 0; i <= 1000; i = i+1) begin
                #5; clk = ~clk;
                #5; clk = ~clk;
            end
        end
        if(1) begin
            for(i = 0; i <= 200000; i = i+1) begin
                #5; clk = ~clk;
                #5; clk = ~clk;
            end
        end
    end
    initial begin
        $dumpfile("data/dumpfile.vcd");
        $dumpvars(0, tb);
    end
    initial begin
        $monitor("At time=%2t, clk=%d, h_sync_pulse=%d, v_sync_pulse=%d",
                $time, clk, h_sync_pulse, v_sync_pulse);
    end
endmodule