data/full_repos/permissive/178917770/design.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/178917770/design.v:237: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'flopenr\'\nmodule flopenr #(parameter WIDTH = 4)\n       ^~~~~~~\n                                                                    : ... Top module \'processor\'\nmodule processor(input clk, reset,\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/178917770/design.v:250: Duplicate declaration of signal: \'MemWrite\'\n                                                         : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire MemToReg, MemWrite, RegWrite, ALUSrc, J, initRd;\n                   ^~~~~~~~\n        data/full_repos/permissive/178917770/design.v:240: ... Location of original declaration\n                 output MemWrite,BeqFlag,\n                        ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module extendImm(input [3:0] imm,
             
                 output [7:0] imm8);
  
  assign imm8={4'b0,imm};
endmodule
module extendImm(input [3:0] imm,
             
                 output [7:0] imm8);

  
  assign imm8={4'b0,imm};
endmodule