data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v
 line:49: before: "("
1: b'%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:49: syntax error, unexpected \'@\'\n    repeat(4) @(posedge jclk);\n              ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:50: Unsupported: wait statements\n    wait(rv32i_top.pll_locked == 1\'b1);\n    ^~~~\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:52: syntax error, unexpected \'@\'\n    repeat(4) @(posedge jclk);\n              ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:130: Unsupported: wait statements\n    wait(rv32i_top.pll_locked == 1\'b1);\n    ^~~~\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:132: syntax error, unexpected \'@\'\n    repeat(10) @(posedge jclk);\n               ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:149: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:151: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:152: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:154: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 1;  \n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:155: syntax error, unexpected \'@\'\n        repeat(5) @(negedge jclk);  \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:160: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:161: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:162: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:164: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:173: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 1; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:174: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:175: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk); \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:176: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 1; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:177: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:178: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk); \n                  ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:183: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:186: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:187: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tdi = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:188: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:189: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:193: Unsupported: Ignoring delay on this delayed statement.\n            #0.1 tms = 0; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:194: Unsupported: Ignoring delay on this delayed statement.\n            #0.1 tdi = addr[i];\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:195: Unsupported: Ignoring delay on this delayed statement.\n            #0.1 jtck_en = 1;\n            ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:196: syntax error, unexpected \'@\'\n            repeat(1) @(negedge jclk);\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:198: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:199: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tdi = addr[i];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:200: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:201: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:204: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 1; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:205: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:206: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:208: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:209: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:210: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:212: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:224: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 1; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:225: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:226: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk); \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:229: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:230: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:231: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:234: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:235: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tdi = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:236: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:237: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:243: Unsupported: Ignoring delay on this delayed statement.\n            #0.1 tms = 0; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:244: Unsupported: Ignoring delay on this delayed statement.\n            #0.1 tdi = data[i];\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:246: Unsupported: Ignoring delay on this delayed statement.\n            #0.1 jtck_en = 1;\n            ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:247: syntax error, unexpected \'@\'\n            repeat(1) @(negedge jclk);\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:249: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:250: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tdi = data[i];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:251: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jrx_data[i] = tdo;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:252: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:253: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:256: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 1; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:257: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:258: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:260: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 tms = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:261: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 1;\n        ^\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:262: syntax error, unexpected \'@\'\n        repeat(1) @(negedge jclk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/125344718/rv32i_arty_bram/src/sim/sim_rv32i_top.v:264: Unsupported: Ignoring delay on this delayed statement.\n        #0.1 jtck_en = 0;\n        ^\n%Error: Exiting due to 24 error(s), 42 warning(s)\n'
module sim_rv32i_top();

localparam DMI_REQOP_NOP = 2'h0;
localparam DMI_REQOP_RD = 2'h1;
localparam DMI_REQOP_WR = 2'h2;

localparam DMI_ADDR_SBADDRESS0 = 7'h39;
localparam DMI_ADDR_SBDATA0 = 7'h3C;

localparam DMI_ADDR_WIDTH = 7;
localparam DMI_DATA_WIDTH = 32;
localparam DMI_OP_WIDTH = 2;
localparam JTAG_DATA_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH);
localparam TX_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH);
localparam RX_WIDTH = (DMI_DATA_WIDTH+DMI_OP_WIDTH);


parameter CLOCK_FREQ_MHZ = 100.0;


parameter CLOCK_PROIOD = 1000.0/CLOCK_FREQ_MHZ;
reg         clock;
initial begin clock = 1'b0; forever clock = #(CLOCK_PROIOD/2) ~clock; end


parameter JCLK_FREQ_MHZ = 100.0;
parameter JCLK_PROIOD = 1000.0/JCLK_FREQ_MHZ;
reg jclk;
initial begin jclk = 1'b0; forever jclk = #(JCLK_PROIOD/2) ~jclk; end


wire tdo;
wire tck;
reg tdi;
reg tms;

reg [JTAG_DATA_WIDTH-1:0] jtx_data = 'h0;
reg [JTAG_DATA_WIDTH-1:0] jrx_data = 'h0;

reg jtck_en = 1'b0;
assign tck = jclk&jtck_en;


initial begin: sim_main
    
    jtck_en = 1'b0;
    repeat(4) @(posedge jclk);
    wait(rv32i_top.pll_locked == 1'b1);
    jtck_en = 1'b0;
    repeat(4) @(posedge jclk);
    
    goto_rti();
    shift_ir(6'h09);
    shift_dr('h0, 32);
    

    shift_ir(6'h23);

    sim_jtag_op(DMI_ADDR_SBADDRESS0, 32'h80001000, DMI_REQOP_WR);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(DMI_ADDR_SBADDRESS0, 32'h80001000, DMI_REQOP_RD);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(DMI_ADDR_SBDATA0, 32'h12345678, DMI_REQOP_WR);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(DMI_ADDR_SBDATA0, 32'h00000000, DMI_REQOP_RD);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(7'h44, 32'h00000001, DMI_REQOP_WR);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(DMI_ADDR_SBDATA0, 32'h00000000, DMI_REQOP_RD);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(7'h48, 32'h00000001, DMI_REQOP_WR);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(DMI_ADDR_SBDATA0, 32'h00000000, DMI_REQOP_RD);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(7'h44, 32'h00000001, DMI_REQOP_WR);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(DMI_ADDR_SBDATA0, 32'h00000000, DMI_REQOP_RD);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(7'h48, 32'h00000001, DMI_REQOP_WR);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(DMI_ADDR_SBDATA0, 32'h00000000, DMI_REQOP_RD);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    shift_ir(6'h22);
    shift_dr('h1, 32);
    $display("JTAG Reset System");
    shift_dr('h0, 32);
    
    wait(rv32i_top.pll_locked == 1'b1);
 
    repeat(10) @(posedge jclk);
    $finish;
end

task sim_jtag_op;
    input [6:0] addr;
    input [31:0] data;
    input [1:0] op;
    integer i;
    begin
        $display("SHIFT-DR: %X", {addr, data, op});
        shift_dr({addr, data, op}, JTAG_DATA_WIDTH);
    end
endtask

task goto_rti;
    begin
        repeat(1) @(negedge jclk);
        
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);
        
        #0.1 tms = 1;
        repeat(5) @(negedge jclk);  


        

        #0.1 tms = 0; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);
        
        #0.1 jtck_en = 0;
    end
endtask

task shift_ir;
    input [5:0] addr;
    integer i;
    begin

        #0.1 tms = 1; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk); 
        #0.1 tms = 1; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk); 
        

        tms = 0; 
        jtck_en = 1;
        repeat(1) @(negedge jclk);
        

        #0.1 tms = 0; 
        #0.1 tdi = 0;
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);
        

        for(i=0; i<5; i=i+1) begin
            #0.1 tms = 0; 
            #0.1 tdi = addr[i];
            #0.1 jtck_en = 1;
            repeat(1) @(negedge jclk);
        end
        #0.1 tms = 1;
        #0.1 tdi = addr[i];
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);
        

        #0.1 tms = 1; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);

        #0.1 tms = 0; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);

        #0.1 jtck_en = 0;
        
        $display("JTAG IR ",  "0x%X, ", addr);
    end
endtask

task shift_dr;
    input [JTAG_DATA_WIDTH-1:0] data;
    input integer dlen;
    integer i;
    begin

        #0.1 tms = 1; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk); 
        

        #0.1 tms = 0; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);


        #0.1 tms = 0; 
        #0.1 tdi = 0;
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);
        

        jtx_data = data;
        jrx_data = 'h0;
        for(i=0; i<(dlen-1); i=i+1) begin
            #0.1 tms = 0; 
            #0.1 tdi = data[i];
            jrx_data[i] = tdo;
            #0.1 jtck_en = 1;
            repeat(1) @(negedge jclk);
        end
        #0.1 tms = 1;
        #0.1 tdi = data[i];
        #0.1 jrx_data[i] = tdo;
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);
        

        #0.1 tms = 1; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);

        #0.1 tms = 0; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);

        #0.1 jtck_en = 0;
        
        if(dlen == JTAG_DATA_WIDTH) begin
            $display("JTAG DR ",  "TX:", 
                                "A[%X]", jtx_data[(DMI_DATA_WIDTH+DMI_OP_WIDTH)+:DMI_ADDR_WIDTH],
                                "_D[%X]", jtx_data[DMI_OP_WIDTH+:DMI_DATA_WIDTH],
                                "_O[%X]", jtx_data[0+:DMI_OP_WIDTH],
                                ", RX:",
                                "A[%X]", jrx_data[(DMI_DATA_WIDTH+DMI_OP_WIDTH)+:DMI_ADDR_WIDTH],
                                "_D[%X]", jrx_data[DMI_OP_WIDTH+:DMI_DATA_WIDTH],
                                "_O[%X]", jrx_data[0+:DMI_OP_WIDTH]);
        end
        else begin
            $display("JTAG DR ",  "TX: 0x%X, ", jtx_data, "RX: 0x%X", jrx_data);
        end
    end
endtask

initial begin: init_value
    tdi = 1'b0;
    tms = 1'b0;
end

JTAG_SIME2 #(
    .PART_NAME("7A35T")
) jtag_sim_arty_inst (
    .TDO(tdo),
    .TCK(tck),
    .TDI(tdi),
    .TMS(tms)
);

rv32i_top rv32i_top(
    .board_clock(clock)
);

endmodule
module sim_rv32i_top();


localparam DMI_REQOP_NOP = 2'h0;
localparam DMI_REQOP_RD = 2'h1;
localparam DMI_REQOP_WR = 2'h2;

localparam DMI_ADDR_SBADDRESS0 = 7'h39;
localparam DMI_ADDR_SBDATA0 = 7'h3C;

localparam DMI_ADDR_WIDTH = 7;
localparam DMI_DATA_WIDTH = 32;
localparam DMI_OP_WIDTH = 2;
localparam JTAG_DATA_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH);
localparam TX_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH);
localparam RX_WIDTH = (DMI_DATA_WIDTH+DMI_OP_WIDTH);


parameter CLOCK_FREQ_MHZ = 100.0;


parameter CLOCK_PROIOD = 1000.0/CLOCK_FREQ_MHZ;
reg         clock;
initial begin clock = 1'b0; forever clock = #(CLOCK_PROIOD/2) ~clock; end


parameter JCLK_FREQ_MHZ = 100.0;
parameter JCLK_PROIOD = 1000.0/JCLK_FREQ_MHZ;
reg jclk;
initial begin jclk = 1'b0; forever jclk = #(JCLK_PROIOD/2) ~jclk; end


wire tdo;
wire tck;
reg tdi;
reg tms;

reg [JTAG_DATA_WIDTH-1:0] jtx_data = 'h0;
reg [JTAG_DATA_WIDTH-1:0] jrx_data = 'h0;

reg jtck_en = 1'b0;
assign tck = jclk&jtck_en;


initial begin: sim_main
    
    jtck_en = 1'b0;
    repeat(4) @(posedge jclk);
    wait(rv32i_top.pll_locked == 1'b1);
    jtck_en = 1'b0;
    repeat(4) @(posedge jclk);
    
    goto_rti();
    shift_ir(6'h09);
    shift_dr('h0, 32);
    

    shift_ir(6'h23);

    sim_jtag_op(DMI_ADDR_SBADDRESS0, 32'h80001000, DMI_REQOP_WR);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(DMI_ADDR_SBADDRESS0, 32'h80001000, DMI_REQOP_RD);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(DMI_ADDR_SBDATA0, 32'h12345678, DMI_REQOP_WR);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(DMI_ADDR_SBDATA0, 32'h00000000, DMI_REQOP_RD);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(7'h44, 32'h00000001, DMI_REQOP_WR);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(DMI_ADDR_SBDATA0, 32'h00000000, DMI_REQOP_RD);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(7'h48, 32'h00000001, DMI_REQOP_WR);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(DMI_ADDR_SBDATA0, 32'h00000000, DMI_REQOP_RD);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(7'h44, 32'h00000001, DMI_REQOP_WR);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(DMI_ADDR_SBDATA0, 32'h00000000, DMI_REQOP_RD);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(7'h48, 32'h00000001, DMI_REQOP_WR);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    sim_jtag_op(DMI_ADDR_SBDATA0, 32'h00000000, DMI_REQOP_RD);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    sim_jtag_op(7'h0, 32'h00000000, DMI_REQOP_NOP);
    
    shift_ir(6'h22);
    shift_dr('h1, 32);
    $display("JTAG Reset System");
    shift_dr('h0, 32);
    
    wait(rv32i_top.pll_locked == 1'b1);
 
    repeat(10) @(posedge jclk);
    $finish;
end

task sim_jtag_op;
    input [6:0] addr;
    input [31:0] data;
    input [1:0] op;
    integer i;
    begin
        $display("SHIFT-DR: %X", {addr, data, op});
        shift_dr({addr, data, op}, JTAG_DATA_WIDTH);
    end
endtask

task goto_rti;
    begin
        repeat(1) @(negedge jclk);
        
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);
        
        #0.1 tms = 1;
        repeat(5) @(negedge jclk);  


        

        #0.1 tms = 0; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);
        
        #0.1 jtck_en = 0;
    end
endtask

task shift_ir;
    input [5:0] addr;
    integer i;
    begin

        #0.1 tms = 1; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk); 
        #0.1 tms = 1; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk); 
        

        tms = 0; 
        jtck_en = 1;
        repeat(1) @(negedge jclk);
        

        #0.1 tms = 0; 
        #0.1 tdi = 0;
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);
        

        for(i=0; i<5; i=i+1) begin
            #0.1 tms = 0; 
            #0.1 tdi = addr[i];
            #0.1 jtck_en = 1;
            repeat(1) @(negedge jclk);
        end
        #0.1 tms = 1;
        #0.1 tdi = addr[i];
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);
        

        #0.1 tms = 1; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);

        #0.1 tms = 0; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);

        #0.1 jtck_en = 0;
        
        $display("JTAG IR ",  "0x%X, ", addr);
    end
endtask

task shift_dr;
    input [JTAG_DATA_WIDTH-1:0] data;
    input integer dlen;
    integer i;
    begin

        #0.1 tms = 1; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk); 
        

        #0.1 tms = 0; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);


        #0.1 tms = 0; 
        #0.1 tdi = 0;
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);
        

        jtx_data = data;
        jrx_data = 'h0;
        for(i=0; i<(dlen-1); i=i+1) begin
            #0.1 tms = 0; 
            #0.1 tdi = data[i];
            jrx_data[i] = tdo;
            #0.1 jtck_en = 1;
            repeat(1) @(negedge jclk);
        end
        #0.1 tms = 1;
        #0.1 tdi = data[i];
        #0.1 jrx_data[i] = tdo;
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);
        

        #0.1 tms = 1; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);

        #0.1 tms = 0; 
        #0.1 jtck_en = 1;
        repeat(1) @(negedge jclk);

        #0.1 jtck_en = 0;
        
        if(dlen == JTAG_DATA_WIDTH) begin
            $display("JTAG DR ",  "TX:", 
                                "A[%X]", jtx_data[(DMI_DATA_WIDTH+DMI_OP_WIDTH)+:DMI_ADDR_WIDTH],
                                "_D[%X]", jtx_data[DMI_OP_WIDTH+:DMI_DATA_WIDTH],
                                "_O[%X]", jtx_data[0+:DMI_OP_WIDTH],
                                ", RX:",
                                "A[%X]", jrx_data[(DMI_DATA_WIDTH+DMI_OP_WIDTH)+:DMI_ADDR_WIDTH],
                                "_D[%X]", jrx_data[DMI_OP_WIDTH+:DMI_DATA_WIDTH],
                                "_O[%X]", jrx_data[0+:DMI_OP_WIDTH]);
        end
        else begin
            $display("JTAG DR ",  "TX: 0x%X, ", jtx_data, "RX: 0x%X", jrx_data);
        end
    end
endtask

initial begin: init_value
    tdi = 1'b0;
    tms = 1'b0;
end

JTAG_SIME2 #(
    .PART_NAME("7A35T")
) jtag_sim_arty_inst (
    .TDO(tdo),
    .TCK(tck),
    .TDI(tdi),
    .TMS(tms)
);

rv32i_top rv32i_top(
    .board_clock(clock)
);

endmodule