data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 0; reset = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 0; reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 1; reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 1; reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 0; reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 0; reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 0; reset = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 0; K = 1; reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = 1; K = 1; reset = 1;\n    ^\n%Error: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitTest.v:5: Cannot find file containing module: \'bitCount\'\n  bitCount count(K, CLK, reset, Q);\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop,data/full_repos/permissive/172602559/bitCount\n             data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop,data/full_repos/permissive/172602559/bitCount.v\n             data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop,data/full_repos/permissive/172602559/bitCount.sv\n             bitCount\n             bitCount.v\n             bitCount.sv\n             obj_dir/bitCount\n             obj_dir/bitCount.v\n             obj_dir/bitCount.sv\n%Error: Exiting due to 1 error(s), 43 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bitTest();
  wire [1:0] Q;
  reg K, CLK, reset;
  
  bitCount count(K, CLK, reset, Q);
  
  initial
  begin
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 1;
    #10 CLK = 0; K = 0; reset = 1;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 1;
    #10 CLK = 1; K = 1; reset = 1;
    #10 CLK = 1; K = 1; reset = 1;
    
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 1;
    #10 CLK = 1; K = 1; reset = 1;
    #10 CLK = 0; K = 0; reset = 1;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 1;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 1;
    #10 CLK = 1; K = 1; reset = 1;
    #10 CLK = 1; K = 1; reset = 1;
  end
endmodule
module bitTest();

  wire [1:0] Q;
  reg K, CLK, reset;
  
  bitCount count(K, CLK, reset, Q);
  
  initial
  begin
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 1;
    #10 CLK = 0; K = 0; reset = 1;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 1;
    #10 CLK = 1; K = 1; reset = 1;
    #10 CLK = 1; K = 1; reset = 1;
    
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 1;
    #10 CLK = 1; K = 1; reset = 1;
    #10 CLK = 0; K = 0; reset = 1;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 1;
    #10 CLK = 0; K = 1; reset = 0;
    #10 CLK = 1; K = 1; reset = 0;
    #10 CLK = 0; K = 0; reset = 0;
    #10 CLK = 1; K = 0; reset = 0;
    #10 CLK = 0; K = 1; reset = 1;
    #10 CLK = 1; K = 1; reset = 1;
    #10 CLK = 1; K = 1; reset = 1;
  end
endmodule