data/full_repos/permissive/136422019/src/computer.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/136422019/src/computer.v:26: Signal definition not found, creating implicitly: \'clkOut\'\n                                                                         : ... Suggested alternative: \'cOut\'\nassign clkOut = clk;\n       ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/136422019/src/computer.v:25: Cannot find file containing module: \'Clock\'\nClock clkInstance(clk);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/Clock\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/Clock.v\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/Clock.sv\n             Clock\n             Clock.v\n             Clock.sv\n             obj_dir/Clock\n             obj_dir/Clock.v\n             obj_dir/Clock.sv\n%Error: data/full_repos/permissive/136422019/src/computer.v:54: Cannot find file containing module: \'regR0\'\nregR0 R0(r0_out, busmux_out, r0In, clk, clr, BAout);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:55: Cannot find file containing module: \'reg32\'\nreg32 R1(r1_out, busmux_out, r1In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:56: Cannot find file containing module: \'reg32\'\nreg32 R2(r2_out, busmux_out, r2In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:57: Cannot find file containing module: \'reg32\'\nreg32 R3(r3_out, busmux_out, r3In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:58: Cannot find file containing module: \'reg32\'\nreg32 R4(r4_out, busmux_out, r4In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:59: Cannot find file containing module: \'reg32\'\nreg32 R5(r5_out, busmux_out, r5In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:60: Cannot find file containing module: \'reg32\'\nreg32 R6(r6_out, busmux_out, r6In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:61: Cannot find file containing module: \'reg32\'\nreg32 R7(r7_out, busmux_out, r7In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:62: Cannot find file containing module: \'reg32\'\nreg32 R8(r8_out, busmux_out, r8In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:63: Cannot find file containing module: \'reg32\'\nreg32 R9(r9_out, busmux_out, r9In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:64: Cannot find file containing module: \'reg32\'\nreg32 R10(r10_out, busmux_out, r10In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:65: Cannot find file containing module: \'reg32\'\nreg32 R11(r11_out, busmux_out, r11In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:66: Cannot find file containing module: \'reg32\'\nreg32 R12(r12_out, busmux_out, r12In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:67: Cannot find file containing module: \'reg32\'\nreg32 R13(r13_out, busmux_out, r13In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:68: Cannot find file containing module: \'reg32\'\nreg32 R14(r14_out, busmux_out, r14In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:69: Cannot find file containing module: \'reg32\'\nreg32 R15(r15_out, busmux_out, r15In, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:72: Cannot find file containing module: \'reg32\'\nreg32 HI(HI_out, busmux_out, HIIn, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:73: Cannot find file containing module: \'reg32\'\nreg32 LO(LO_out, busmux_out, LOIn, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:74: Cannot find file containing module: \'reg32\'\nreg32 PC(PC_out, busmux_out, PCIn, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:75: Cannot find file containing module: \'reg32\'\nreg32 IR(IR_out, busmux_out, IRIn, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:76: Cannot find file containing module: \'reg32\'\nreg32 Y(Y_out, busmux_out, Y_en, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:77: Cannot find file containing module: \'reg64\'\nreg64 Z(Zhigh_out, Zlow_out, Z_in, Z_en, clk, clr, Zlow_en, Zhigh_en);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:79: Cannot find file containing module: \'encoder\'\nencoder encoder1(select,\n^~~~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:84: Cannot find file containing module: \'Bus32\'\nBus32 bus1(busmux_out, \n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:90: Cannot find file containing module: \'alu\'\nalu alu1(Z_in,\n^~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:95: Cannot find file containing module: \'reg32\'\nreg32 MAR(mem_address, busmux_out, MARIn, clk, clr);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:101: Cannot find file containing module: \'mdr\'\nmdr MDR(MDR_out, mem_data, busmux_out, MDRIn, clk, clr, mdr_read);\n^~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:103: Cannot find file containing module: \'ram512\'\nram512 dodgeram(Mdatain, MDR_out, mem_address, mread_en, mwrite_en);\n^~~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:104: Cannot find file containing module: \'stack32\'\nstack32 stack(Sdatain, MDR_out, sread_en, swrite_en);\n^~~~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:106: Cannot find file containing module: \'selectAndEncode\'\nselectAndEncode encode(C_out, \n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:113: Cannot find file containing module: \'conFF\'\nconFF compare(conFF_Out, busmux_out, IR_out[1:0], clk, conIn);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:115: Cannot find file containing module: \'inPort\'\ninPort port1(InPort_out, InPort_dataIn, clr, clk);\n^~~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:116: Cannot find file containing module: \'outPort\'\noutPort port2(outPort_out, busmux_out, clr, clk, outPortIn);\n^~~~~~~\n%Error: data/full_repos/permissive/136422019/src/computer.v:121: Cannot find file containing module: \'ControlUnit\'\nControlUnit cu(\n^~~~~~~~~~~\n%Error: Exiting due to 35 error(s), 1 warning(s)\n'
module computer(
	input wire reset,
	input wire [31:0]InPort_dataIn
);

wire[4:0] opcode;


wire Rin, Rout, Gra, Grb, Grc;


wire HIIn, LOIn, conIn, PCIn, IRIn, Y_en, Z_en, MARIn, MDRIn, outPortIn;


wire cOut, InPortOut, BAout, PCOut, MDROut, Zhigh_en, Zlow_en, HIOut, LOOut;

wire PCinc_en;

wire mread_en, mwrite_en, sread_en, swrite_en, run, clr;

wire stop;

wire clk;
Clock clkInstance(clk);
assign clkOut = clk;


wire [31:0] busmux_out;


wire[31:0] InPort_out, outPort_out;


wire [8:0] mem_address;


wire [63:0] Z_in; 


wire [31:0] r0_out, r1_out, r2_out, r3_out, r4_out, r5_out, r6_out, r7_out, r8_out, r9_out, r10_out, r11_out, 
r12_out, r13_out, r14_out, r15_out, HI_out, LO_out, PC_out, IR_out, Y_out, Zhigh_out, Zlow_out, MDR_out, C_out;


wire r0In, r1In, r2In, r3In, r4In, r5In, r6In, r7In, r8In, r9In, r10In, r11In, r12In, r13In, r14In, r15In;


wire r0Out, r1Out, r2Out, r3Out, r4Out, r5Out, r6Out, r7Out, r8Out, r9Out, r10Out, r11Out, r12Out, r13Out, r14Out, r15Out;


wire [4:0] select;


regR0 R0(r0_out, busmux_out, r0In, clk, clr, BAout);
reg32 R1(r1_out, busmux_out, r1In, clk, clr);
reg32 R2(r2_out, busmux_out, r2In, clk, clr);
reg32 R3(r3_out, busmux_out, r3In, clk, clr);
reg32 R4(r4_out, busmux_out, r4In, clk, clr);
reg32 R5(r5_out, busmux_out, r5In, clk, clr);
reg32 R6(r6_out, busmux_out, r6In, clk, clr);
reg32 R7(r7_out, busmux_out, r7In, clk, clr);
reg32 R8(r8_out, busmux_out, r8In, clk, clr);
reg32 R9(r9_out, busmux_out, r9In, clk, clr);
reg32 R10(r10_out, busmux_out, r10In, clk, clr);
reg32 R11(r11_out, busmux_out, r11In, clk, clr);
reg32 R12(r12_out, busmux_out, r12In, clk, clr);
reg32 R13(r13_out, busmux_out, r13In, clk, clr);
reg32 R14(r14_out, busmux_out, r14In, clk, clr);
reg32 R15(r15_out, busmux_out, r15In, clk, clr);


reg32 HI(HI_out, busmux_out, HIIn, clk, clr);
reg32 LO(LO_out, busmux_out, LOIn, clk, clr);
reg32 PC(PC_out, busmux_out, PCIn, clk, clr);
reg32 IR(IR_out, busmux_out, IRIn, clk, clr);
reg32 Y(Y_out, busmux_out, Y_en, clk, clr);
reg64 Z(Zhigh_out, Zlow_out, Z_in, Z_en, clk, clr, Zlow_en, Zhigh_en);

encoder encoder1(select,
	r0Out, r1Out, r2Out, r3Out, r4Out, r5Out, r6Out, r7Out, r8Out, r9Out, r10Out, r11Out,
	r12Out, r13Out, r14Out, r15Out, HIOut, LOOut, PCOut, MDROut, InPortOut, Zhigh_en, Zlow_en, cOut 
);

Bus32 bus1(busmux_out, 
	r0_out, r1_out, r2_out, r3_out, r4_out, r5_out, r6_out, r7_out, r8_out, r9_out, r10_out, r11_out, r12_out, r13_out, r14_out, 
	r15_out, HI_out, LO_out, PC_out, MDR_out, InPort_out, Zhigh_out, Zlow_out, C_out,
	select
);

alu alu1(Z_in,
Y_out, busmux_out, opcode, PCinc_en);



reg32 MAR(mem_address, busmux_out, MARIn, clk, clr);

wire [31:0] Mdatain, Sdatain, mem_data;
wire mdr_read;
assign mdr_read = mread_en | sread_en;
assign mem_data = Mdatain | Sdatain;
mdr MDR(MDR_out, mem_data, busmux_out, MDRIn, clk, clr, mdr_read);

ram512 dodgeram(Mdatain, MDR_out, mem_address, mread_en, mwrite_en);
stack32 stack(Sdatain, MDR_out, sread_en, swrite_en);

selectAndEncode encode(C_out, 
	r0In, r1In, r2In, r3In, r4In, r5In, r6In, r7In, r8In, r9In, r10In, r11In, r12In, r13In, r14In, r15In,
	r0Out, r1Out, r2Out, r3Out, r4Out, r5Out, r6Out, r7Out, r8Out, r9Out, r10Out, r11Out, r12Out, r13Out, r14Out, r15Out, 
	IR_out,
	Gra, Grb, Grc, Rin, Rout, BAout
);

conFF compare(conFF_Out, busmux_out, IR_out[1:0], clk, conIn);

inPort port1(InPort_out, InPort_dataIn, clr, clk);
outPort port2(outPort_out, busmux_out, clr, clk, outPortIn);




ControlUnit cu(
	Rin, Rout, Gra, Grb, Grc,
	HIIn, LOIn, conIn, PCIn, IRIn, Y_en, Z_en, MARIn, MDRIn, outPortIn, cOut, InPortOut, BAout,
	PCOut, MDROut, Zhigh_en, Zlow_en, HIOut, LOOut,
	PCinc_en,
	opcode,
	mread_en, mwrite_en, sread_en, swrite_en, run, clr,
	stateOut,
	clk, reset, stop, conFF_Out,
	IR_out
);

endmodule
module computer(
	input wire reset,
	input wire [31:0]InPort_dataIn
);


wire[4:0] opcode;


wire Rin, Rout, Gra, Grb, Grc;


wire HIIn, LOIn, conIn, PCIn, IRIn, Y_en, Z_en, MARIn, MDRIn, outPortIn;


wire cOut, InPortOut, BAout, PCOut, MDROut, Zhigh_en, Zlow_en, HIOut, LOOut;

wire PCinc_en;

wire mread_en, mwrite_en, sread_en, swrite_en, run, clr;

wire stop;

wire clk;
Clock clkInstance(clk);
assign clkOut = clk;


wire [31:0] busmux_out;


wire[31:0] InPort_out, outPort_out;


wire [8:0] mem_address;


wire [63:0] Z_in; 


wire [31:0] r0_out, r1_out, r2_out, r3_out, r4_out, r5_out, r6_out, r7_out, r8_out, r9_out, r10_out, r11_out, 
r12_out, r13_out, r14_out, r15_out, HI_out, LO_out, PC_out, IR_out, Y_out, Zhigh_out, Zlow_out, MDR_out, C_out;


wire r0In, r1In, r2In, r3In, r4In, r5In, r6In, r7In, r8In, r9In, r10In, r11In, r12In, r13In, r14In, r15In;


wire r0Out, r1Out, r2Out, r3Out, r4Out, r5Out, r6Out, r7Out, r8Out, r9Out, r10Out, r11Out, r12Out, r13Out, r14Out, r15Out;


wire [4:0] select;


regR0 R0(r0_out, busmux_out, r0In, clk, clr, BAout);
reg32 R1(r1_out, busmux_out, r1In, clk, clr);
reg32 R2(r2_out, busmux_out, r2In, clk, clr);
reg32 R3(r3_out, busmux_out, r3In, clk, clr);
reg32 R4(r4_out, busmux_out, r4In, clk, clr);
reg32 R5(r5_out, busmux_out, r5In, clk, clr);
reg32 R6(r6_out, busmux_out, r6In, clk, clr);
reg32 R7(r7_out, busmux_out, r7In, clk, clr);
reg32 R8(r8_out, busmux_out, r8In, clk, clr);
reg32 R9(r9_out, busmux_out, r9In, clk, clr);
reg32 R10(r10_out, busmux_out, r10In, clk, clr);
reg32 R11(r11_out, busmux_out, r11In, clk, clr);
reg32 R12(r12_out, busmux_out, r12In, clk, clr);
reg32 R13(r13_out, busmux_out, r13In, clk, clr);
reg32 R14(r14_out, busmux_out, r14In, clk, clr);
reg32 R15(r15_out, busmux_out, r15In, clk, clr);


reg32 HI(HI_out, busmux_out, HIIn, clk, clr);
reg32 LO(LO_out, busmux_out, LOIn, clk, clr);
reg32 PC(PC_out, busmux_out, PCIn, clk, clr);
reg32 IR(IR_out, busmux_out, IRIn, clk, clr);
reg32 Y(Y_out, busmux_out, Y_en, clk, clr);
reg64 Z(Zhigh_out, Zlow_out, Z_in, Z_en, clk, clr, Zlow_en, Zhigh_en);

encoder encoder1(select,
	r0Out, r1Out, r2Out, r3Out, r4Out, r5Out, r6Out, r7Out, r8Out, r9Out, r10Out, r11Out,
	r12Out, r13Out, r14Out, r15Out, HIOut, LOOut, PCOut, MDROut, InPortOut, Zhigh_en, Zlow_en, cOut 
);

Bus32 bus1(busmux_out, 
	r0_out, r1_out, r2_out, r3_out, r4_out, r5_out, r6_out, r7_out, r8_out, r9_out, r10_out, r11_out, r12_out, r13_out, r14_out, 
	r15_out, HI_out, LO_out, PC_out, MDR_out, InPort_out, Zhigh_out, Zlow_out, C_out,
	select
);

alu alu1(Z_in,
Y_out, busmux_out, opcode, PCinc_en);



reg32 MAR(mem_address, busmux_out, MARIn, clk, clr);

wire [31:0] Mdatain, Sdatain, mem_data;
wire mdr_read;
assign mdr_read = mread_en | sread_en;
assign mem_data = Mdatain | Sdatain;
mdr MDR(MDR_out, mem_data, busmux_out, MDRIn, clk, clr, mdr_read);

ram512 dodgeram(Mdatain, MDR_out, mem_address, mread_en, mwrite_en);
stack32 stack(Sdatain, MDR_out, sread_en, swrite_en);

selectAndEncode encode(C_out, 
	r0In, r1In, r2In, r3In, r4In, r5In, r6In, r7In, r8In, r9In, r10In, r11In, r12In, r13In, r14In, r15In,
	r0Out, r1Out, r2Out, r3Out, r4Out, r5Out, r6Out, r7Out, r8Out, r9Out, r10Out, r11Out, r12Out, r13Out, r14Out, r15Out, 
	IR_out,
	Gra, Grb, Grc, Rin, Rout, BAout
);

conFF compare(conFF_Out, busmux_out, IR_out[1:0], clk, conIn);

inPort port1(InPort_out, InPort_dataIn, clr, clk);
outPort port2(outPort_out, busmux_out, clr, clk, outPortIn);




ControlUnit cu(
	Rin, Rout, Gra, Grb, Grc,
	HIIn, LOIn, conIn, PCIn, IRIn, Y_en, Z_en, MARIn, MDRIn, outPortIn, cOut, InPortOut, BAout,
	PCOut, MDROut, Zhigh_en, Zlow_en, HIOut, LOOut,
	PCinc_en,
	opcode,
	mread_en, mwrite_en, sread_en, swrite_en, run, clr,
	stateOut,
	clk, reset, stop, conFF_Out,
	IR_out
);

endmodule