data/full_repos/permissive/207835546/Shift Register/Shift_test.v
1: b'%Error: Cannot find file containing module: Register,data/full_repos/permissive/207835546\n        ... Looked in:\n             data/full_repos/permissive/207835546/Shift/Register,data/full_repos/permissive/207835546\n             data/full_repos/permissive/207835546/Shift/Register,data/full_repos/permissive/207835546.v\n             data/full_repos/permissive/207835546/Shift/Register,data/full_repos/permissive/207835546.sv\n             Register,data/full_repos/permissive/207835546\n             Register,data/full_repos/permissive/207835546.v\n             Register,data/full_repos/permissive/207835546.sv\n             obj_dir/Register,data/full_repos/permissive/207835546\n             obj_dir/Register,data/full_repos/permissive/207835546.v\n             obj_dir/Register,data/full_repos/permissive/207835546.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/207835546/Shift\n%Error: Cannot find file containing module: Register/Shift_test.v\n%Error: Exiting due to 3 error(s)\n'
module uni_shift_8b_tst;
  reg [7:0] ip;
  reg [1:0] sh_ro_lt_rt;
  reg load,rst_a,clk;
  wire [7:0] op;


   uni_shift_8b u1 (.op(op), .ip(ip), .sh_ro_lt_rt(sh_ro_lt_rt), .load(load) , .rst_a(rst_a) , .clk(clk));

initial
  begin
     clk=1'b1;
     forever #50 clk=~clk;   
  end
  
   initial
     begin
    ip = 8'b11001100;
    rst_a = 1'b1;
    load = 1'b1;
    sh_ro_lt_rt = 2'b00;
    #100;
    
    ip = 8'b10001100;
    rst_a = 1'b0;
    load = 1'b1;
    sh_ro_lt_rt = 2'b01;
    #100;
    
    ip = 8'b11001100;

    load = 1'b0;
    sh_ro_lt_rt = 2'b01;
    #100;
    
    ip = 8'b10101101;
    
    load = 1'b1;
    sh_ro_lt_rt = 2'b01;
    #100;
    
    ip = 8'b11001101;

    load = 1'b0;
    sh_ro_lt_rt = 2'b01;
    #100;

    ip = 8'b11101100;
    load = 1'b1;
    sh_ro_lt_rt = 2'b10;
    #100;

    ip = 8'b11110000;
    load = 1'b0;
    sh_ro_lt_rt = 2'b10;
    #100;

    ip = 8'b11001100;
    load = 1'b1;
    sh_ro_lt_rt = 2'b11;
    #100;

    ip = 8'b11001101;
    load = 1'b0;
    sh_ro_lt_rt = 2'b11;
    #100;
    
    ip = 8'b11001000;
    load = 1'b1;
    sh_ro_lt_rt = 2'b11;
    #100;
    $finish;
 end
 
 initial 
 begin 
	$dumpfile("Shift Wave.vcd");
	$dumpvars;
	$monitor("Input=%b, Load = %b, Shift R/L=%b, Output=%b",ip,load,sh_ro_lt_rt,op);
 end
endmodule
module uni_shift_8b_tst;

  reg [7:0] ip;
  reg [1:0] sh_ro_lt_rt;
  reg load,rst_a,clk;
  wire [7:0] op;


   uni_shift_8b u1 (.op(op), .ip(ip), .sh_ro_lt_rt(sh_ro_lt_rt), .load(load) , .rst_a(rst_a) , .clk(clk));

initial
  begin
     clk=1'b1;
     forever #50 clk=~clk;   
  end
  
   initial
     begin
    ip = 8'b11001100;
    rst_a = 1'b1;
    load = 1'b1;
    sh_ro_lt_rt = 2'b00;
    #100;
    
    ip = 8'b10001100;
    rst_a = 1'b0;
    load = 1'b1;
    sh_ro_lt_rt = 2'b01;
    #100;
    
    ip = 8'b11001100;

    load = 1'b0;
    sh_ro_lt_rt = 2'b01;
    #100;
    
    ip = 8'b10101101;
    
    load = 1'b1;
    sh_ro_lt_rt = 2'b01;
    #100;
    
    ip = 8'b11001101;

    load = 1'b0;
    sh_ro_lt_rt = 2'b01;
    #100;

    ip = 8'b11101100;
    load = 1'b1;
    sh_ro_lt_rt = 2'b10;
    #100;

    ip = 8'b11110000;
    load = 1'b0;
    sh_ro_lt_rt = 2'b10;
    #100;

    ip = 8'b11001100;
    load = 1'b1;
    sh_ro_lt_rt = 2'b11;
    #100;

    ip = 8'b11001101;
    load = 1'b0;
    sh_ro_lt_rt = 2'b11;
    #100;
    
    ip = 8'b11001000;
    load = 1'b1;
    sh_ro_lt_rt = 2'b11;
    #100;
    $finish;
 end
 
 initial 
 begin 
	$dumpfile("Shift Wave.vcd");
	$dumpvars;
	$monitor("Input=%b, Load = %b, Shift R/L=%b, Output=%b",ip,load,sh_ro_lt_rt,op);
 end
endmodule