data/full_repos/permissive/143278/ivltests/pr3587570.v
 line:1: before: "primitive"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3587570.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr3587570.v:24: syntax error, unexpected \'(\', expecting IDENTIFIER\n  passthrough (o1, i);\n               ^~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  reg i;
  wire o1, o1b, o2, o2b;

  initial begin
    i = 1'b0;
    #1;
    if ((o1 !== 1'b0) && (o1b !== 1'b1) &&
        (o2 !== 1'b0) && (o2b !== 1'b1)) $display("FAILED");
    else $display("PASSED");
  end

  passthrough (o1, i);
  passthrough (o1b, !i);
  passthrough (o2, i);
  passthrough (o2b, ~i);
endmodule
module test;

  reg i;
  wire o1, o1b, o2, o2b;

  initial begin
    i = 1'b0;
    #1;
    if ((o1 !== 1'b0) && (o1b !== 1'b1) &&
        (o2 !== 1'b0) && (o2b !== 1'b1)) $display("FAILED");
    else $display("PASSED");
  end

  passthrough (o1, i);
  passthrough (o1b, !i);
  passthrough (o2, i);
  passthrough (o2b, ~i);
endmodule