data/full_repos/permissive/214823094/submissions/lab_5/project_5/binary_counter.v
data/verilator_xmls/71f5d023-728a-45d9-a242-2e8416a71566.xml
module clkdiv(
    input mclk,



    output clk1_4hz
    );
    reg [27:0]q;
    always@(posedge mclk)




         q<=q+1;



    assign clk1_4hz=q[26];         
endmodule
module clkdiv(
    input mclk,



    output clk1_4hz
    );

    reg [27:0]q;
    always@(posedge mclk)




         q<=q+1;



    assign clk1_4hz=q[26];         
endmodule