data/full_repos/permissive/174369527/simpleCPU/src/rom.v
data/verilator_xmls/882810db-c099-42cc-89c1-546c74248a19.xml
module rom (
	clk,
	addr,
	DO,
	EN
	);

parameter AddrSize = 11;
parameter WordSize = 9;

input clk;
input [AddrSize-1:0] addr;
output reg [WordSize-1:0] DO;
reg [WordSize-1:0] r_DO;
input EN;

reg [WordSize-1:0] Mem [0:(1<<AddrSize)-1];

always @ (posedge clk)
	r_DO <= DO;

always @ (posedge clk)
begin
	if (EN)
		DO <= Mem[addr];
	else
		DO <= {WordSize{1'b0}};
end

initial begin
	$display("Loading rom.");
	$readmemb("rom.mem", Mem);
end

endmodule
module rom (
	clk,
	addr,
	DO,
	EN
	);


parameter AddrSize = 11;
parameter WordSize = 9;

input clk;
input [AddrSize-1:0] addr;
output reg [WordSize-1:0] DO;
reg [WordSize-1:0] r_DO;
input EN;

reg [WordSize-1:0] Mem [0:(1<<AddrSize)-1];

always @ (posedge clk)
	r_DO <= DO;

always @ (posedge clk)
begin
	if (EN)
		DO <= Mem[addr];
	else
		DO <= {WordSize{1'b0}};
end

initial begin
	$display("Loading rom.");
	$readmemb("rom.mem", Mem);
end

endmodule