data/full_repos/permissive/184916587/ALU_RECV.v
data/verilator_xmls/11c131a4-5f02-45c9-b967-521eab3318de.xml
module ALU_RECV(



	input[9:0] alu_op,
	input[4:0] ls_op,
	input[4:0] j_op,
	input[4:0] b_op,
	input[31:0] pc_in,
	input[31:0] rs1,
	input[31:0] rs2,
	input[31:0] address_imm,
	output reg[31:0] rd,
	output reg[31:0] pc_out,
	output reg[31:0] address,


	output[31:0] A_add_rd,

	output[31:0] S_sub_rd,

	output[31:0] SLL_sll_rd,

	output[31:0] SLT_slt_rd,

	output[31:0] SLTU_sltu_rd,

	output[31:0] X_xor_rd,

	output[31:0] SRL_srl_rd,

	output[31:0] SRA_sra_rd,

	output[31:0] O_or_rd,

	output[31:0] AND_and_rd
	);

	reg[31:0] rs1_num;
	reg[31:0] rs2_num;


	always @* begin
		case(alu_op)
			10'b0000000001:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=A_add_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000000010:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=S_sub_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000000011:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=SLL_sll_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000000101:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=SLT_slt_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000000110:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=SLTU_sltu_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000000111:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=X_xor_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000001000:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=SRL_srl_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000001001:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=SRA_sra_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000001010:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=O_or_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000001011:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=AND_and_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end

			10'b1000000001:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=A_add_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000000010:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=S_sub_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000000011:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=SLL_sll_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000000101:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=SLT_slt_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000000110:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=SLTU_sltu_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000000111:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=X_xor_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000001000:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=SRL_srl_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000001001:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=SRA_sra_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000001010:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=O_or_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000001011:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=AND_and_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
		endcase
	end

	always @* begin
		case(ls_op)
			5'b00001:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				address=A_add_rd;
				rd={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b00010:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				address=A_add_rd;
				rd={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b00011:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				address=A_add_rd;
				rd={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b00100:begin
				rs2_num={{28{1'b0}},4'b1100};
				rs1_num=address_imm;
				rd=SLL_sll_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b00101:begin
				rs1_num=pc_in;
				rs2_num=address_imm;
				rd=A_add_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b00110:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				address=A_add_rd;
				rd={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b00111:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				address=A_add_rd;
				rd={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b01000:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				address=A_add_rd;
				rd={32{1'b0}};
				pc_out={32{1'b0}};
			end
		endcase
	end

	always @* begin
		case(j_op)
			5'b00001:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				pc_out=A_add_rd;
				rd=pc_in+4;
				address={32{1'b0}};
			end
			5'b00010:begin
				rs1_num=pc_in;
				rs2_num=address_imm;
				pc_out=A_add_rd;
				rd=pc_in+4;
				address={32{1'b0}};
			end
		endcase
	end

	always @* begin
		case(b_op)
			5'b00001:begin
				if(rs1==rs2) begin
					rs1_num=pc_in;
					rs2_num=address_imm;
					pc_out=A_add_rd;
					rd={32{1'b0}};
					address={32{1'b0}};
				end
			end
			5'b00010:begin
				if(rs1!=rs2) begin
					rs1_num=pc_in;
					rs2_num=address_imm;
					pc_out=A_add_rd;
					rd={32{1'b0}};
					address={32{1'b0}};
				end
			end
			5'b00011:begin
				if(rs1<=rs2) begin
					rs1_num=pc_in;
					rs2_num=address_imm;
					pc_out=A_add_rd;
					rd={32{1'b0}};
					address={32{1'b0}};
				end
			end
			5'b00100:begin
				if(rs1>=rs2) begin
					rs1_num=pc_in;
					rs2_num=address_imm;
					pc_out=A_add_rd;
					rd={32{1'b0}};
					address={32{1'b0}};
				end
			end
			5'b00101:begin
				if(rs1[30:0]<=rs2[30:0]) begin
					rs1_num=pc_in;
					rs2_num=address_imm;
					pc_out=A_add_rd;
					rd={32{1'b0}};
					address={32{1'b0}};
				end
			end
			5'b00111:begin
				if(rs1[30:0]>=rs2[30:0]) begin
					rs1_num=pc_in;
					rs2_num=address_imm;
					pc_out=A_add_rd;
					rd={32{1'b0}};
					address={32{1'b0}};
				end
			end
		endcase
	end

	add_32 add_add(
		.add_rs1(rs1_num),
		.add_rs2(rs2_num),
		.add_rd(A_add_rd)
	);
	sub_32 sub_sub(
		.sub_rs1(rs1_num),
		.sub_rs2(rs2_num),
		.sub_rd(S_sub_rd)
	);
	sll_32 sll_sll(
		.sll_rs1(rs1_num),
		.sll_rs2(rs2_num),
		.sll_rd(SLL_sll_rd)
	);
	slt_32 slt_slt(
		.slt_rs1(rs1_num),
		.slt_rs2(rs2_num),
		.slt_rd(SLT_slt_rd)
	);
	sltu_32 sltu_sltu(
		.sltu_rs1(rs1_num),
		.sltu_rs2(rs2_num),
		.sltu_rd(SLTU_sltu_rd)
	);
	xor_32 xor_xor(
		.xor_rs1(rs1_num),
		.xor_rs2(rs2_num),
		.xor_rd(X_xor_rd)
	);
	srl_32 srl_srl(
		.srl_rs1(rs1_num),
		.srl_rs2(rs2_num),
		.srl_rd(SRL_srl_rd)
	);
	sra_32 sra_sra(
		.sra_rs1(rs1_num),
		.sra_rs2(rs2_num),
		.sra_rd(SRA_sra_rd)
	);
	or_32 or_or(
		.or_rs1(rs1_num),
		.or_rs2(rs2_num),
		.or_rd(O_or_rd)
	);
	and_32 and_and(
		.and_rs1(rs1_num),
		.and_rs2(rs2_num),
		.and_rd(AND_and_rd)
	);
endmodule
module ALU_RECV(



	input[9:0] alu_op,
	input[4:0] ls_op,
	input[4:0] j_op,
	input[4:0] b_op,
	input[31:0] pc_in,
	input[31:0] rs1,
	input[31:0] rs2,
	input[31:0] address_imm,
	output reg[31:0] rd,
	output reg[31:0] pc_out,
	output reg[31:0] address,


	output[31:0] A_add_rd,

	output[31:0] S_sub_rd,

	output[31:0] SLL_sll_rd,

	output[31:0] SLT_slt_rd,

	output[31:0] SLTU_sltu_rd,

	output[31:0] X_xor_rd,

	output[31:0] SRL_srl_rd,

	output[31:0] SRA_sra_rd,

	output[31:0] O_or_rd,

	output[31:0] AND_and_rd
	);


	reg[31:0] rs1_num;
	reg[31:0] rs2_num;


	always @* begin
		case(alu_op)
			10'b0000000001:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=A_add_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000000010:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=S_sub_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000000011:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=SLL_sll_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000000101:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=SLT_slt_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000000110:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=SLTU_sltu_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000000111:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=X_xor_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000001000:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=SRL_srl_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000001001:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=SRA_sra_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000001010:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=O_or_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b0000001011:begin
				rs1_num=rs1;
				rs2_num=rs2;
				rd=AND_and_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end

			10'b1000000001:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=A_add_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000000010:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=S_sub_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000000011:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=SLL_sll_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000000101:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=SLT_slt_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000000110:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=SLTU_sltu_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000000111:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=X_xor_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000001000:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=SRL_srl_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000001001:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=SRA_sra_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000001010:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=O_or_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			10'b1000001011:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				rd=AND_and_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
		endcase
	end

	always @* begin
		case(ls_op)
			5'b00001:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				address=A_add_rd;
				rd={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b00010:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				address=A_add_rd;
				rd={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b00011:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				address=A_add_rd;
				rd={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b00100:begin
				rs2_num={{28{1'b0}},4'b1100};
				rs1_num=address_imm;
				rd=SLL_sll_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b00101:begin
				rs1_num=pc_in;
				rs2_num=address_imm;
				rd=A_add_rd;
				address={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b00110:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				address=A_add_rd;
				rd={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b00111:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				address=A_add_rd;
				rd={32{1'b0}};
				pc_out={32{1'b0}};
			end
			5'b01000:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				address=A_add_rd;
				rd={32{1'b0}};
				pc_out={32{1'b0}};
			end
		endcase
	end

	always @* begin
		case(j_op)
			5'b00001:begin
				rs1_num=rs1;
				rs2_num=address_imm;
				pc_out=A_add_rd;
				rd=pc_in+4;
				address={32{1'b0}};
			end
			5'b00010:begin
				rs1_num=pc_in;
				rs2_num=address_imm;
				pc_out=A_add_rd;
				rd=pc_in+4;
				address={32{1'b0}};
			end
		endcase
	end

	always @* begin
		case(b_op)
			5'b00001:begin
				if(rs1==rs2) begin
					rs1_num=pc_in;
					rs2_num=address_imm;
					pc_out=A_add_rd;
					rd={32{1'b0}};
					address={32{1'b0}};
				end
			end
			5'b00010:begin
				if(rs1!=rs2) begin
					rs1_num=pc_in;
					rs2_num=address_imm;
					pc_out=A_add_rd;
					rd={32{1'b0}};
					address={32{1'b0}};
				end
			end
			5'b00011:begin
				if(rs1<=rs2) begin
					rs1_num=pc_in;
					rs2_num=address_imm;
					pc_out=A_add_rd;
					rd={32{1'b0}};
					address={32{1'b0}};
				end
			end
			5'b00100:begin
				if(rs1>=rs2) begin
					rs1_num=pc_in;
					rs2_num=address_imm;
					pc_out=A_add_rd;
					rd={32{1'b0}};
					address={32{1'b0}};
				end
			end
			5'b00101:begin
				if(rs1[30:0]<=rs2[30:0]) begin
					rs1_num=pc_in;
					rs2_num=address_imm;
					pc_out=A_add_rd;
					rd={32{1'b0}};
					address={32{1'b0}};
				end
			end
			5'b00111:begin
				if(rs1[30:0]>=rs2[30:0]) begin
					rs1_num=pc_in;
					rs2_num=address_imm;
					pc_out=A_add_rd;
					rd={32{1'b0}};
					address={32{1'b0}};
				end
			end
		endcase
	end

	add_32 add_add(
		.add_rs1(rs1_num),
		.add_rs2(rs2_num),
		.add_rd(A_add_rd)
	);
	sub_32 sub_sub(
		.sub_rs1(rs1_num),
		.sub_rs2(rs2_num),
		.sub_rd(S_sub_rd)
	);
	sll_32 sll_sll(
		.sll_rs1(rs1_num),
		.sll_rs2(rs2_num),
		.sll_rd(SLL_sll_rd)
	);
	slt_32 slt_slt(
		.slt_rs1(rs1_num),
		.slt_rs2(rs2_num),
		.slt_rd(SLT_slt_rd)
	);
	sltu_32 sltu_sltu(
		.sltu_rs1(rs1_num),
		.sltu_rs2(rs2_num),
		.sltu_rd(SLTU_sltu_rd)
	);
	xor_32 xor_xor(
		.xor_rs1(rs1_num),
		.xor_rs2(rs2_num),
		.xor_rd(X_xor_rd)
	);
	srl_32 srl_srl(
		.srl_rs1(rs1_num),
		.srl_rs2(rs2_num),
		.srl_rd(SRL_srl_rd)
	);
	sra_32 sra_sra(
		.sra_rs1(rs1_num),
		.sra_rs2(rs2_num),
		.sra_rd(SRA_sra_rd)
	);
	or_32 or_or(
		.or_rs1(rs1_num),
		.or_rs2(rs2_num),
		.or_rd(O_or_rd)
	);
	and_32 and_and(
		.and_rs1(rs1_num),
		.and_rs2(rs2_num),
		.and_rd(AND_and_rd)
	);
endmodule