data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:160: Unsupported: Ignoring delay on this delayed statement.\n  #5000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:162: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:168: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:170: Unsupported: Ignoring delay on this delayed statement.\n  #30;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:127: Cell has missing pin: \'local_clock509_in_p\'\n mza_test028_pll_509divider_and_revo_encoder_althea uut (\n                                                    ^~~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:127: Cell has missing pin: \'local_clock509_in_n\'\n mza_test028_pll_509divider_and_revo_encoder_althea uut (\n                                                    ^~~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:183: Multiple top level modules\n                                                                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                                                                 : ... Top module \'mything_tb\'\nmodule mything_tb;\n       ^~~~~~~~~~\n                                                                                                                                 : ... Top module \'mza_test028_pll_509divider_and_revo_encoder_althea_top\'\nmodule mza_test028_pll_509divider_and_revo_encoder_althea_top (\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:36: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS remote_input_clock_instance (.I(remote_clock509_in_p), .IB(remote_clock509_in_n), .O(remote_clock509));\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/IBUFGDS.sv\n             IBUFGDS\n             IBUFGDS.v\n             IBUFGDS.sv\n             obj_dir/IBUFGDS\n             obj_dir/IBUFGDS.v\n             obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:37: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS local_input_clock_instance (.I(local_clock509_in_p), .IB(local_clock509_in_n), .O(local_clock509));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:42: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS trigger_input_instance (.I(remote_revo_in_p), .IB(remote_revo_in_n), .O(rawtrg));\n ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:61: Cannot find file containing module: \'simplepll_BASE\'\n simplepll_BASE #(.OVERALL_DIVIDE(2), .MULTIPLY(4), .DIVIDE1(8), .DIVIDE2(4), .PERIOD(1.965), .COMPENSATION("INTERNAL")) mypll (.clockin(clock509), .reset(reset), .clock1out(rawclock127), .clock1out180(rawclock127b), .clock2out(rawclock254), .clock2out180(rawclock254b), .locked(locked));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:64: Cannot find file containing module: \'BUFG\'\n BUFG mybufg1 (.I(rawclock127), .O(clock127));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:65: Cannot find file containing module: \'BUFG\'\n BUFG mybufg2 (.I(rawclock127b), .O(clock127b));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:68: Cannot find file containing module: \'BUFG\'\n BUFG mybufg3 (.I(rawclock254), .O(clock254));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:69: Cannot find file containing module: \'BUFG\'\n BUFG mybufg4 (.I(rawclock254b), .O(clock254b));\n ^~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:84: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut1 (.C0(clock127), .C1(clock127b), .CE(1\'b1), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr1));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:85: Cannot find file containing module: \'OBUFDS\'\n OBUFDS supercool (.I(clock127oddr1), .O(clock127_out_p), .OB(clock127_out_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:87: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut2 (.C0(clock127), .C1(clock127b), .CE(~trg),  .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr2));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:88: Cannot find file containing module: \'OBUFDS\'\n OBUFDS grouch2 (.I(clock127oddr2), .O(trg_out_p), .OB(trg_out_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:98: Cannot find file containing module: \'ODDR2\'\n ODDR2 doughnut3 (.C0(clock127), .C1(clock127b), .CE(1\'b1), .D0(1\'b0), .D1(1\'b1), .R(1\'b0), .S(1\'b0), .Q(clock127oddr3));\n ^~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:99: Cannot find file containing module: \'OBUFDS\'\n OBUFDS outa (.I(clock127oddr3), .O(outa_p), .OB(outa_n));\n ^~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test028.pll_509divider_and_revo_encoder.althea.revA.v:100: Cannot find file containing module: \'OBUFDS\'\n OBUFDS out1 (.I(trg), .O(out1_p), .OB(out1_n));\n ^~~~~~\n%Error: Exiting due to 15 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mything_tb;

	reg remote_clock509_in_p;
	reg remote_clock509_in_n;
	reg remote_revo_in_p;
	reg remote_revo_in_n;

	wire clock127_out_p;
	wire clock127_out_n;
	wire trg_out_p;
	wire trg_out_n;
	wire out1_p;
	wire out1_n;
	wire outa_p;
	wire outa_n;
	wire led_0;
	wire led_1;
	wire led_2;
	wire led_3;
	wire led_4;
	wire led_5;
	wire led_6;
	wire led_7;

	mza_test028_pll_509divider_and_revo_encoder_althea uut (
		.remote_clock509_in_p(remote_clock509_in_p), 
		.remote_clock509_in_n(remote_clock509_in_n), 
		.remote_revo_in_p(remote_revo_in_p), 
		.remote_revo_in_n(remote_revo_in_n), 
		.clock127_out_p(clock127_out_p), 
		.clock127_out_n(clock127_out_n), 
		.trg_out_p(trg_out_p), 
		.trg_out_n(trg_out_n), 
		.out1_p(out1_p), 
		.out1_n(out1_n), 
		.outa_p(outa_p), 
		.outa_n(outa_n), 
		.led_0(led_0), 
		.led_1(led_1), 
		.led_2(led_2), 
		.led_3(led_3), 
		.led_4(led_4), 
		.led_5(led_5), 
		.led_6(led_6), 
		.led_7(led_7)
	);
	wire raw_recovered_reco;
	assign raw_recovered_reco = clock127_out_p ^ trg_out_p;
	reg recovered_revo;
	initial begin

		remote_clock509_in_p = 0; remote_clock509_in_n = 1;
		remote_revo_in_p = 0; remote_revo_in_n = 1;
		recovered_revo = 0;

		#100;

		#5000;
		remote_revo_in_p = 1; remote_revo_in_n = 0;
		#2;
		remote_revo_in_p = 0; remote_revo_in_n = 1;
		#50;
		remote_revo_in_p = 1; remote_revo_in_n = 0;
		#8;
		remote_revo_in_p = 0; remote_revo_in_n = 1;
		#50;
		remote_revo_in_p = 1; remote_revo_in_n = 0;
		#30;
		remote_revo_in_p = 0; remote_revo_in_n = 1;
	end
	always begin
		#1;
		remote_clock509_in_p = ~ remote_clock509_in_p;
		remote_clock509_in_n = ~ remote_clock509_in_n;
	end
	always @(negedge clock127_out_p) begin
		recovered_revo <= raw_recovered_reco;
	end
endmodule
module mything_tb;


	reg remote_clock509_in_p;
	reg remote_clock509_in_n;
	reg remote_revo_in_p;
	reg remote_revo_in_n;

	wire clock127_out_p;
	wire clock127_out_n;
	wire trg_out_p;
	wire trg_out_n;
	wire out1_p;
	wire out1_n;
	wire outa_p;
	wire outa_n;
	wire led_0;
	wire led_1;
	wire led_2;
	wire led_3;
	wire led_4;
	wire led_5;
	wire led_6;
	wire led_7;

	mza_test028_pll_509divider_and_revo_encoder_althea uut (
		.remote_clock509_in_p(remote_clock509_in_p), 
		.remote_clock509_in_n(remote_clock509_in_n), 
		.remote_revo_in_p(remote_revo_in_p), 
		.remote_revo_in_n(remote_revo_in_n), 
		.clock127_out_p(clock127_out_p), 
		.clock127_out_n(clock127_out_n), 
		.trg_out_p(trg_out_p), 
		.trg_out_n(trg_out_n), 
		.out1_p(out1_p), 
		.out1_n(out1_n), 
		.outa_p(outa_p), 
		.outa_n(outa_n), 
		.led_0(led_0), 
		.led_1(led_1), 
		.led_2(led_2), 
		.led_3(led_3), 
		.led_4(led_4), 
		.led_5(led_5), 
		.led_6(led_6), 
		.led_7(led_7)
	);
	wire raw_recovered_reco;
	assign raw_recovered_reco = clock127_out_p ^ trg_out_p;
	reg recovered_revo;
	initial begin

		remote_clock509_in_p = 0; remote_clock509_in_n = 1;
		remote_revo_in_p = 0; remote_revo_in_n = 1;
		recovered_revo = 0;

		#100;

		#5000;
		remote_revo_in_p = 1; remote_revo_in_n = 0;
		#2;
		remote_revo_in_p = 0; remote_revo_in_n = 1;
		#50;
		remote_revo_in_p = 1; remote_revo_in_n = 0;
		#8;
		remote_revo_in_p = 0; remote_revo_in_n = 1;
		#50;
		remote_revo_in_p = 1; remote_revo_in_n = 0;
		#30;
		remote_revo_in_p = 0; remote_revo_in_n = 1;
	end
	always begin
		#1;
		remote_clock509_in_p = ~ remote_clock509_in_p;
		remote_clock509_in_n = ~ remote_clock509_in_n;
	end
	always @(negedge clock127_out_p) begin
		recovered_revo <= raw_recovered_reco;
	end
endmodule