data/full_repos/permissive/211316121/lab7_2/TrafficFarm.v
data/verilator_xmls/25bc4578-aa7e-43e4-a633-38d4d2910e9c.xml
module TrafficFarm(
input TS,
input TL,
input C,
input clk,
input reset,
output [5:0] lights,
output reg ST
);
parameter HG=6'b0_0_1_1_0_0,
            HY=6'b0_1_0_1_0_0,
            FG=6'b1_0_0_0_0_1,
            FY=6'b1_0_0_0_1_0;
reg [5:0] state;

always@(posedge clk)
begin
if(reset) begin state<=HG;ST<=1; end
else
    begin
    ST<=0;
        case(state)
            HG:if(TL&C)  begin state<=HY;ST<=1;end
            HY:if(TS)    begin state<=FG;ST<=1;end
            FG:if(TL|~C) begin state<=FY;ST<=1;end
            FY:if(TS)    begin state<=HG;ST<=1;end
            default:     begin state<=HG;ST<=1;end
        endcase
    end
end

assign lights=state;
endmodule
module TrafficFarm(
input TS,
input TL,
input C,
input clk,
input reset,
output [5:0] lights,
output reg ST
);

parameter HG=6'b0_0_1_1_0_0,
            HY=6'b0_1_0_1_0_0,
            FG=6'b1_0_0_0_0_1,
            FY=6'b1_0_0_0_1_0;
reg [5:0] state;

always@(posedge clk)
begin
if(reset) begin state<=HG;ST<=1; end
else
    begin
    ST<=0;
        case(state)
            HG:if(TL&C)  begin state<=HY;ST<=1;end
            HY:if(TS)    begin state<=FG;ST<=1;end
            FG:if(TL|~C) begin state<=FY;ST<=1;end
            FY:if(TS)    begin state<=HG;ST<=1;end
            default:     begin state<=HG;ST<=1;end
        endcase
    end
end

assign lights=state;
endmodule