data/full_repos/permissive/210844779/lab7/7.3/tb.v
 line:3: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab7/7.3/tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk=~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab7/7.3/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab7/7.3/tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/210844779/lab7/7.3/tb.v:6: Cannot find file containing module: \'multi\'\n  multi u0(a,b,clk,out,load);\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab7/7.3,data/full_repos/permissive/210844779/multi\n             data/full_repos/permissive/210844779/lab7/7.3,data/full_repos/permissive/210844779/multi.v\n             data/full_repos/permissive/210844779/lab7/7.3,data/full_repos/permissive/210844779/multi.sv\n             multi\n             multi.v\n             multi.sv\n             obj_dir/multi\n             obj_dir/multi.v\n             obj_dir/multi.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab7/7.3/tb.v:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n    a=$random;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab7/7.3/tb.v:14: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n    b=$random;\n     ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  reg [3:0] a,b;
  reg clk=1,load;
  wire [7:0]out;
  
  multi u0(a,b,clk,out,load);
  
  always
  #5 clk=~clk;
  
  always
  begin
    a=$random;
    b=$random;
    load=1;
    #10
    load=0;
    #50;
  end
  
endmodule
module tb();

  reg [3:0] a,b;
  reg clk=1,load;
  wire [7:0]out;
  
  multi u0(a,b,clk,out,load);
  
  always
  #5 clk=~clk;
  
  always
  begin
    a=$random;
    b=$random;
    load=1;
    #10
    load=0;
    #50;
  end
  
endmodule