data/full_repos/permissive/111433415/verilog/03_combinacionales/03-3_alarma/alarma_tb.v
 line:73: before: "$"
1: b'%Error: data/full_repos/permissive/111433415/verilog/03_combinacionales/03-3_alarma/alarma_tb.v:66: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("alarma_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/03_combinacionales/03-3_alarma/alarma_tb.v:67: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,test);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/03_combinacionales/03-3_alarma/alarma_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #(64*10) $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/03_combinacionales/03-3_alarma/alarma_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #(10) x = x + 1;\n        ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ();



    reg [5:0] x;


    wire a;



    alarma uut (x[5], x[4], x[3], x[2], x[1], x[0], a);


    initial begin

        x = 6'b000000;



        $dumpfile("alarma_tb.vcd");
        $dumpvars(0,test);



        #(64*`BTIME) $finish;
    end



    always
        #(`BTIME) x = x + 1;

endmodule
module test ();




    reg [5:0] x;


    wire a;



    alarma uut (x[5], x[4], x[3], x[2], x[1], x[0], a);


    initial begin

        x = 6'b000000;



        $dumpfile("alarma_tb.vcd");
        $dumpvars(0,test);



        #(64*`BTIME) $finish;
    end



    always
        #(`BTIME) x = x + 1;

endmodule