data/full_repos/permissive/16591284/fifo_with_bram/fifo.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/16591284/fifo_with_bram/fifo.v:32: Unsupported: Ignoring delay on this delayed statement.\n    forever #(5) CLK = ~CLK;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/16591284/fifo_with_bram/fifo.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Error: data/full_repos/permissive/16591284/fifo_with_bram/fifo.v:40: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile(VCD);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/16591284/fifo_with_bram/fifo.v:41: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, fifo);\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  parameter VCD = "uut.vcd";
    

  reg  CLK;
  reg  RST_X;
  wire ENQ;
  wire DEQ;
  wire [`WIDTH-1:0] DIN;
  

  wire [`WIDTH-1:0] DOUT;
  wire EMPTY;
  wire FULL;

  FIFO #(.WIDTH(`WIDTH), .DEPTH(`DEPTH), .W_CNT(`W_CNT), .W_POS(`W_POS))
  fifo(CLK, RST_X, ENQ, DEQ, DIN, DOUT, EMPTY, FULL);
  
  initial begin
    CLK = 0;
    forever #(`CLKIN_HALF_PERIOD) CLK = ~CLK;
  end
  initial begin
    RST_X = 0;
    #`RESET_TIME;
    RST_X = 1;
  end
  initial begin
    $dumpfile(VCD);
    $dumpvars(0, fifo);
  end

  reg [`WIDTH-1:0] cycle;
  assign DIN = cycle;
  assign ENQ = (cycle<20) && !FULL;
  assign DEQ = (cycle%2)  && !EMPTY;

  always @(posedge CLK) begin
    if (!RST_X) begin
      cycle <= 0;
    end else begin
      cycle <= cycle + 1;
      $write("cycle(DIN): %d DOUT: %d ENQ: %d DEQ: %d EMPTY %d FULL %d\n", 
             cycle, DOUT, ENQ, DEQ, EMPTY, FULL);
      if (cycle == `HALT_CYCLE) $finish;
    end
  end
endmodule
module test;

  parameter VCD = "uut.vcd";
    

  reg  CLK;
  reg  RST_X;
  wire ENQ;
  wire DEQ;
  wire [`WIDTH-1:0] DIN;
  

  wire [`WIDTH-1:0] DOUT;
  wire EMPTY;
  wire FULL;

  FIFO #(.WIDTH(`WIDTH), .DEPTH(`DEPTH), .W_CNT(`W_CNT), .W_POS(`W_POS))
  fifo(CLK, RST_X, ENQ, DEQ, DIN, DOUT, EMPTY, FULL);
  
  initial begin
    CLK = 0;
    forever #(`CLKIN_HALF_PERIOD) CLK = ~CLK;
  end
  initial begin
    RST_X = 0;
    #`RESET_TIME;
    RST_X = 1;
  end
  initial begin
    $dumpfile(VCD);
    $dumpvars(0, fifo);
  end

  reg [`WIDTH-1:0] cycle;
  assign DIN = cycle;
  assign ENQ = (cycle<20) && !FULL;
  assign DEQ = (cycle%2)  && !EMPTY;

  always @(posedge CLK) begin
    if (!RST_X) begin
      cycle <= 0;
    end else begin
      cycle <= cycle + 1;
      $write("cycle(DIN): %d DOUT: %d ENQ: %d DEQ: %d EMPTY %d FULL %d\n", 
             cycle, DOUT, ENQ, DEQ, EMPTY, FULL);
      if (cycle == `HALT_CYCLE) $finish;
    end
  end
endmodule