data/full_repos/permissive/157049472/Verilog Source Files/ALU.v
1: b'%Error: Cannot find file containing module: Source\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Source\n             data/full_repos/permissive/157049472/Verilog/Source.v\n             data/full_repos/permissive/157049472/Verilog/Source.sv\n             Source\n             Source.v\n             Source.sv\n             obj_dir/Source\n             obj_dir/Source.v\n             obj_dir/Source.sv\n%Error: Cannot find file containing module: Files,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Files/ALU.v\n%Error: Exiting due to 4 error(s)\n'
module ALU(input wire [31:0] a, input wire [31:0] b, input wire [3:0] control, output reg [31:0] result,output reg zero_flag,
				output reg carry_flag, output reg sign_flag, output reg overflow_flag);

	always @(a or b or control)
	begin
		carry_flag = 0;
		zero_flag = 0;
		sign_flag =0;
		overflow_flag = 0;
		case(control)
			4'b0000: {carry_flag,result} = a+b;
			4'b0001: result = ~b+1;
			4'b0010: result = a&b;
			4'b0011: result = a^b;
			4'b0100: result = a<<b;
			4'b0101: result = a>>b;
			4'b0110: result = a>>>b;
			4'b0111: result = a;
			4'b1000: result = b;
			4'b1001: result = a + b[15:0];
			default:  result = 32'd0;
		endcase
		zero_flag = (result == 32'd0)?1:0;
		sign_flag = result[31];
		overflow_flag = carry_flag^(result[31]^(a[31]^b[31]));
	end	

endmodule
module ALU(input wire [31:0] a, input wire [31:0] b, input wire [3:0] control, output reg [31:0] result,output reg zero_flag,
				output reg carry_flag, output reg sign_flag, output reg overflow_flag);


	always @(a or b or control)
	begin
		carry_flag = 0;
		zero_flag = 0;
		sign_flag =0;
		overflow_flag = 0;
		case(control)
			4'b0000: {carry_flag,result} = a+b;
			4'b0001: result = ~b+1;
			4'b0010: result = a&b;
			4'b0011: result = a^b;
			4'b0100: result = a<<b;
			4'b0101: result = a>>b;
			4'b0110: result = a>>>b;
			4'b0111: result = a;
			4'b1000: result = b;
			4'b1001: result = a + b[15:0];
			default:  result = 32'd0;
		endcase
		zero_flag = (result == 32'd0)?1:0;
		sign_flag = result[31];
		overflow_flag = carry_flag^(result[31]^(a[31]^b[31]));
	end	

endmodule