data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v
 line:28: before: "begin"
1: b'%Error: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:1: Cannot find include file: c17.v\n`include "c17.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200893858/TestBenchGenerator/Outputs,data/full_repos/permissive/200893858/c17.v\n             data/full_repos/permissive/200893858/TestBenchGenerator/Outputs,data/full_repos/permissive/200893858/c17.v.v\n             data/full_repos/permissive/200893858/TestBenchGenerator/Outputs,data/full_repos/permissive/200893858/c17.v.sv\n             c17.v\n             c17.v.v\n             c17.v.sv\n             obj_dir/c17.v\n             obj_dir/c17.v.v\n             obj_dir/c17.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n #5 N1=1\'b0 ; N2=1\'b0 ; N3=1\'b0 ; N6=1\'b0 ; N7=1\'b1 ; \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n #5 N1=1\'b0 ; N2=1\'b0 ; N3=1\'b0 ; N6=1\'b1 ; N7=1\'b0 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n #5 N1=1\'b0 ; N2=1\'b0 ; N3=1\'b0 ; N6=1\'b1 ; N7=1\'b1 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n #5 N1=1\'b0 ; N2=1\'b0 ; N3=1\'b1 ; N6=1\'b0 ; N7=1\'b0 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n #5 N1=1\'b0 ; N2=1\'b0 ; N3=1\'b1 ; N6=1\'b0 ; N7=1\'b1 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n #5 N1=1\'b0 ; N2=1\'b0 ; N3=1\'b1 ; N6=1\'b1 ; N7=1\'b0 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #5 N1=1\'b0 ; N2=1\'b0 ; N3=1\'b1 ; N6=1\'b1 ; N7=1\'b1 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #5 N1=1\'b0 ; N2=1\'b1 ; N3=1\'b0 ; N6=1\'b0 ; N7=1\'b0 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #5 N1=1\'b0 ; N2=1\'b1 ; N3=1\'b0 ; N6=1\'b0 ; N7=1\'b1 ; \n ^\n%Error: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:21: Unsupported or unknown PLI call: $monitor\n$monitor ($time, ": N1=%b N2=%b N3=%b N6=%b N7=%b N22=%b N23=%b ",N1,N2,N3,N6,N7,N22,N23);\n^~~~~~~~\n%Error: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:22: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("c17.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/200893858/TestBenchGenerator/Outputs/c17_tb.v:23: Unsupported or unknown PLI call: $dumpvars\n$dumpvars;\n^~~~~~~~~\n%Error: Exiting due to 4 error(s), 9 warning(s)\n'
module top;
reg N1,N2,
	N3,N6,N7;
wire N22,N23;
c17  m0(N1,N2,N3,N6,N7,N22,N23);
initial begin
	N1=1'b0 ; N2=1'b0 ; N3=1'b0 ; N6=1'b0 ; N7=1'b0 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b0 ; N6=1'b0 ; N7=1'b1 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b0 ; N6=1'b1 ; N7=1'b0 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b0 ; N6=1'b1 ; N7=1'b1 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b1 ; N6=1'b0 ; N7=1'b0 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b1 ; N6=1'b0 ; N7=1'b1 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b1 ; N6=1'b1 ; N7=1'b0 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b1 ; N6=1'b1 ; N7=1'b1 ; 
	#5 N1=1'b0 ; N2=1'b1 ; N3=1'b0 ; N6=1'b0 ; N7=1'b0 ; 
	#5 N1=1'b0 ; N2=1'b1 ; N3=1'b0 ; N6=1'b0 ; N7=1'b1 ; 
end

initial begin
$monitor ($time, ": N1=%b N2=%b N3=%b N6=%b N7=%b N22=%b N23=%b ",N1,N2,N3,N6,N7,N22,N23);
$dumpfile("c17.vcd");
$dumpvars;
end

endmodule
module top;

reg N1,N2,
	N3,N6,N7;
wire N22,N23;
c17  m0(N1,N2,N3,N6,N7,N22,N23);
initial begin
	N1=1'b0 ; N2=1'b0 ; N3=1'b0 ; N6=1'b0 ; N7=1'b0 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b0 ; N6=1'b0 ; N7=1'b1 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b0 ; N6=1'b1 ; N7=1'b0 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b0 ; N6=1'b1 ; N7=1'b1 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b1 ; N6=1'b0 ; N7=1'b0 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b1 ; N6=1'b0 ; N7=1'b1 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b1 ; N6=1'b1 ; N7=1'b0 ; 
	#5 N1=1'b0 ; N2=1'b0 ; N3=1'b1 ; N6=1'b1 ; N7=1'b1 ; 
	#5 N1=1'b0 ; N2=1'b1 ; N3=1'b0 ; N6=1'b0 ; N7=1'b0 ; 
	#5 N1=1'b0 ; N2=1'b1 ; N3=1'b0 ; N6=1'b0 ; N7=1'b1 ; 
end

initial begin
$monitor ($time, ": N1=%b N2=%b N3=%b N6=%b N7=%b N22=%b N23=%b ",N1,N2,N3,N6,N7,N22,N23);
$dumpfile("c17.vcd");
$dumpvars;
end

endmodule