data/full_repos/permissive/178052224/Tarea6/demux_no_delay/src/demux_comb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea6/demux_no_delay/src/demux_comb.v:37: Unsupported: Ignoring delay on this delayed statement.\n                #5 s = ~s; \n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea6/demux_no_delay/src/demux_comb.v:45: Unsupported: Ignoring delay on this delayed statement.\n                #5 s = ~s; \n                ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module demux_comb(
                    input clk, reset_L, valid_in,
                    output reg [3:0] data_out0,
                    output reg [3:0] data_out1,
                    input [3:0] data_in,
                    output valid_out0, valid_out1                   );


    reg s;


    always@(*) begin

        if (reset_L == 0) begin
            data_out0 = 0;
            data_out1 = 0;
            valid_out0 = 'b0;
            valid_out1 = 'b0;

            s = 0;
        end


        else begin
            if (s==0) begin
                data_out0 = data_in;

                valid_out0 = valid_in;
                valid_out1 = 0;
                #5 s = ~s; 
            end     
            
            else begin

                data_out1 = data_in;
                valid_out0 = 0;
                valid_out1 = valid_in;
                #5 s = ~s; 
            end
        end 
    end
    
endmodule
module demux_comb(
                    input clk, reset_L, valid_in,
                    output reg [3:0] data_out0,
                    output reg [3:0] data_out1,
                    input [3:0] data_in,
                    output valid_out0, valid_out1                   );



    reg s;


    always@(*) begin

        if (reset_L == 0) begin
            data_out0 = 0;
            data_out1 = 0;
            valid_out0 = 'b0;
            valid_out1 = 'b0;

            s = 0;
        end


        else begin
            if (s==0) begin
                data_out0 = data_in;

                valid_out0 = valid_in;
                valid_out1 = 0;
                #5 s = ~s; 
            end     
            
            else begin

                data_out1 = data_in;
                valid_out0 = 0;
                valid_out1 = valid_in;
                #5 s = ~s; 
            end
        end 
    end
    
endmodule