data/full_repos/permissive/107735152/frameMakerTop-Proj/frameMakerTop/datarate.v
data/verilator_xmls/05fb7d41-5cc0-4c95-886a-fcc688bfff45.xml
module datarate (samplePoint, samplePointFD, edl, brs, brsStop, samplePointOUT);

	input wire samplePoint, samplePointFD, edl, brs, brsStop;
	output wire samplePointOUT;

	reg switch;
	reg init = 1;

	assign samplePointOUT = (switch == 0) ? samplePoint : samplePointFD;

	always @(samplePoint)
		begin
			if (init) begin
				init <= 0;
				switch <= 0;
			end else begin
				if (edl & brs & brsStop)
					switch <= edl & brs & brsStop;
				else
					switch <= 0;
			end
		end

endmodule
module datarate (samplePoint, samplePointFD, edl, brs, brsStop, samplePointOUT);


	input wire samplePoint, samplePointFD, edl, brs, brsStop;
	output wire samplePointOUT;

	reg switch;
	reg init = 1;

	assign samplePointOUT = (switch == 0) ? samplePoint : samplePointFD;

	always @(samplePoint)
		begin
			if (init) begin
				init <= 0;
				switch <= 0;
			end else begin
				if (edl & brs & brsStop)
					switch <= edl & brs & brsStop;
				else
					switch <= 0;
			end
		end

endmodule