data/full_repos/permissive/217441787/fpga/cache.v
1: b'%Error: data/full_repos/permissive/217441787/fpga/cache.v:97: Cannot find file containing module: \'bram_256_72\'\n    bram_256_72 cache_way_0(clk, rst, addr_line_mux, ~rst, cache_way_we_0, cache_way_rd_0, cache_way_wr_0);\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/217441787/fpga,data/full_repos/permissive/217441787/bram_256_72\n             data/full_repos/permissive/217441787/fpga,data/full_repos/permissive/217441787/bram_256_72.v\n             data/full_repos/permissive/217441787/fpga,data/full_repos/permissive/217441787/bram_256_72.sv\n             bram_256_72\n             bram_256_72.v\n             bram_256_72.sv\n             obj_dir/bram_256_72\n             obj_dir/bram_256_72.v\n             obj_dir/bram_256_72.sv\n%Error: data/full_repos/permissive/217441787/fpga/cache.v:98: Cannot find file containing module: \'bram_256_72\'\n    bram_256_72 cache_way_1(clk, rst, addr_line_mux, ~rst, cache_way_we_1, cache_way_rd_1, cache_way_wr_1);\n    ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/217441787/fpga/cache.v:270: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                     : ... In instance cache\n                        cache_line_wb_src <= {2\'b1, addr_word};\n                                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module cache(
    input wire clk,
    input wire rst, 
    input wire [16:0] sys_addr,
    output reg [31:0] sys_rdata,
    input wire sys_valid,
    output reg sys_ready,
    output reg [16:0] mem_addr,
    input wire [31:0] mem_rdata,
    output reg mem_valid,
    input wire mem_ready
    );












    

    






    

    


    

    localparam CACHE_WAY = 2; 
    localparam CACHE_WAY_BITS = 1;
    localparam CACHE_LINE = 256;
    localparam CACHE_LINE_BITS = 8;
    localparam CACHE_LEN = 2;
    localparam CACHE_LEN_ABITS = 1;
    localparam CACHE_LEN_DBITS = 64;
    localparam CACHE_ADDR_BITS = 15;
    localparam CACHE_TAG_BITS = CACHE_ADDR_BITS - CACHE_LINE_BITS - CACHE_LEN_ABITS;
    localparam CACHE_VALID_BITS = 1;
    localparam CACHE_LRU_BITS = 1;
    localparam CACHE_LEN_TOTAL = CACHE_LEN_DBITS + CACHE_TAG_BITS + CACHE_VALID_BITS + CACHE_LRU_BITS;
    
    localparam BIT_TAG_START = 64;
    localparam BIT_TAG_END = 64 + 6 - 1;
    localparam BIT_LRU = 71;
    localparam BIT_VALID = 70;
    
    wire [CACHE_ADDR_BITS - 1: 0] sys_word_addr = sys_addr[CACHE_ADDR_BITS + 1: 2];
    
    wire [CACHE_LEN_ABITS - 1: 0] addr_word = sys_word_addr[CACHE_LEN_ABITS - 1: 0];
    wire [CACHE_LINE_BITS - 1: 0] addr_line = sys_word_addr[CACHE_LINE_BITS + CACHE_LEN_ABITS - 1: CACHE_LEN_ABITS];
    wire [CACHE_TAG_BITS - 1: 0]  addr_tag  = sys_word_addr[CACHE_ADDR_BITS - 1: CACHE_LINE_BITS + CACHE_LEN_ABITS];
    
    wire [CACHE_LEN_TOTAL - 1: 0] cache_way_rd_0;
    wire [CACHE_LEN_TOTAL - 1: 0] cache_way_rd_1;
    wire [CACHE_LEN_TOTAL - 1: 0] cache_way_wr_0;
    wire [CACHE_LEN_TOTAL - 1: 0] cache_way_wr_1;
    reg                           cache_way_we_0;
    reg                           cache_way_we_1;
    
    wire [CACHE_LINE_BITS - 1: 0] addr_line_mux;
    reg addr_line_sel;
    

    bram_256_72 cache_way_0(clk, rst, addr_line_mux, ~rst, cache_way_we_0, cache_way_rd_0, cache_way_wr_0);
    bram_256_72 cache_way_1(clk, rst, addr_line_mux, ~rst, cache_way_we_1, cache_way_rd_1, cache_way_wr_1);
    
    wire cache_comparator_0_comb = ((addr_tag == cache_way_rd_0[BIT_TAG_END: BIT_TAG_START]) && (cache_way_rd_0[BIT_VALID])) ? 1'b1 : 1'b0;
    wire cache_comparator_1_comb = ((addr_tag == cache_way_rd_1[BIT_TAG_END: BIT_TAG_START]) && (cache_way_rd_1[BIT_VALID])) ? 1'b1 : 1'b0;
`ifdef USE_3_CYCLE_CACHE
    reg cache_comparator_0;
    reg cache_comparator_1;
    
    always@(posedge clk) begin
        cache_comparator_0 <= cache_comparator_0_comb;
        cache_comparator_1 <= cache_comparator_1_comb;
    end
`else
    wire cache_comparator_0 = cache_comparator_0_comb;
    wire cache_comparator_1 = cache_comparator_1_comb;
`endif

    wire [31: 0] cache_way_0_output_mux = 
        (addr_word == 1'b0) ? (cache_way_rd_0[31:0]) :
                              (cache_way_rd_0[63:32]);
    wire [31: 0] cache_way_1_output_mux = 
        (addr_word == 1'b0) ? (cache_way_rd_1[31:0]) :
                              (cache_way_rd_1[63:32]);
    
    










    
    wire cache_lru_bit_0 = cache_way_rd_0[BIT_LRU];
    wire cache_lru_bit_1 = cache_way_rd_1[BIT_LRU];
    wire cache_lru_way_0_newer = (cache_lru_bit_0 == cache_lru_bit_1) ? 1 : 0;
    wire cache_lru_way_1_newer = !cache_lru_way_0_newer;

    wire [71: 0] cache_way_0_input_overlay;
    wire [71: 0] cache_way_1_input_overlay;


    assign cache_way_0_input_overlay[BIT_TAG_END: 0] = cache_way_rd_0[BIT_TAG_END: 0];
    assign cache_way_1_input_overlay[BIT_TAG_END: 0] = cache_way_rd_1[BIT_TAG_END: 0];
    assign cache_way_0_input_overlay[BIT_LRU: BIT_VALID] = {cache_way_rd_1[BIT_LRU], 1'b1};
    assign cache_way_1_input_overlay[BIT_LRU: BIT_VALID] = {!cache_way_rd_0[BIT_LRU], 1'b1};
                             
    reg [1:0] cache_line_wb_src;
    assign cache_way_wr_0 = 
        (cache_line_wb_src == 2'b00) ? ({!cache_way_rd_1[BIT_LRU], 71'd0}) : 
        (cache_line_wb_src == 2'b01) ? (cache_way_0_input_overlay) : 
        (cache_line_wb_src == 2'b10) ? ({cache_way_rd_1[BIT_LRU], 1'b1, addr_tag, cache_way_rd_0[63:32], mem_rdata}) :
                                       ({cache_way_rd_1[BIT_LRU], 1'b1, addr_tag, mem_rdata, cache_way_rd_0[31:0]});
    assign cache_way_wr_1 = 
        (cache_line_wb_src == 2'b00) ? ({!cache_way_rd_0[BIT_LRU], 71'd0}) : 
        (cache_line_wb_src == 2'b01) ? (cache_way_1_input_overlay) : 
        (cache_line_wb_src == 2'b10) ? ({cache_way_rd_0[BIT_LRU], 1'b1, addr_tag, cache_way_rd_1[63:32], mem_rdata}) :
                                       ({cache_way_rd_0[BIT_LRU], 1'b1, addr_tag, mem_rdata, cache_way_rd_1[31:0]});
    
    reg [2: 0] cache_state;
    

    localparam STATE_RESET = 3'd0;
    localparam STATE_IDLE = 3'd1;
    localparam STATE_RW_COMPARE = 3'd2;
    localparam STATE_RW_CHECK = 3'd3;
    localparam STATE_RW_MISS_1 = 3'd4;
    localparam STATE_RW_MISS_2 = 3'd5;
    localparam STATE_RW_MISS_3 = 3'd6;
    localparam STATE_WAIT = 3'd7;
    
    reg [CACHE_LINE_BITS - 1: 0] invalidate_counter;
    assign addr_line_mux = (addr_line_sel) ? invalidate_counter : addr_line;
    reg cache_way;
    
    always@(posedge clk) begin
        if (rst) begin
            cache_state <= STATE_RESET;
            sys_ready <= 1'b0;
            mem_valid <= 1'b0;
            cache_way_we_0 <= 1'b0;
            cache_way_we_1 <= 1'b0;
            cache_line_wb_src <= 2'b00;
            invalidate_counter <= 8'hFF;
            addr_line_sel <= 1'b1;
        end
        else begin
            case (cache_state)
                STATE_RESET: begin
                    cache_way_we_0 <= 1'b1;
                    cache_way_we_1 <= 1'b1;
                    invalidate_counter <= invalidate_counter - 1;
                    if (invalidate_counter == 8'd0) begin
                        cache_state <= STATE_IDLE;
                        $display("cache ready");
                    end
                end
                STATE_IDLE: begin
                    addr_line_sel <= 1'b0;
                    cache_way_we_0 <= 1'b0;
                    cache_way_we_1 <= 1'b0;
                    sys_ready <= 1'b0;
                    if (sys_valid) begin
                    `ifdef USE_3_CYCLE_CACHE
                        cache_state <= STATE_RW_COMPARE;
                    `else
                        cache_state <= STATE_RW_CHECK;
                    `endif
                    end
                end
                STATE_RW_COMPARE: begin

                    cache_state <= STATE_RW_CHECK;
                end
                STATE_RW_CHECK: begin
                    if (cache_comparator_0) begin

                        sys_rdata <= cache_way_0_output_mux;
                        sys_ready <= 1'b1;

                        cache_way_we_0 <= 1'b1;
                        cache_way_we_1 <= 1'b0;
                        cache_line_wb_src <= 2'b01;
                        cache_state <= STATE_WAIT;

                    end
                    else if (cache_comparator_1) begin
                        sys_rdata <= cache_way_1_output_mux;
                        sys_ready <= 1'b1;
                        cache_way_we_0 <= 1'b0;
                        cache_way_we_1 <= 1'b1;
                        cache_line_wb_src <= 2'b01;
                        cache_state <= STATE_WAIT;

                    end
                    else begin

                        mem_addr <= {sys_addr[CACHE_ADDR_BITS + 1: 3], !addr_word, 2'b00};
                        mem_valid <= 1'b1;
                        cache_state <= STATE_RW_MISS_1;
                        cache_way <= cache_lru_way_1_newer;

                    end
                end
                STATE_RW_MISS_1: begin
                    if (mem_ready) begin

                        cache_line_wb_src <= {1'b1, !addr_word};
                        if (cache_way)
                            cache_way_we_0 <= 1'b1;
                        else
                            cache_way_we_1 <= 1'b1;
                        mem_valid <= 1'b0;
                        cache_state <= STATE_RW_MISS_2;
                    end
                end
                STATE_RW_MISS_2: begin
                    cache_way_we_0 <= 1'b0;
                    cache_way_we_1 <= 1'b0;
                    if (!mem_ready) begin
                        mem_addr <= {sys_addr[CACHE_ADDR_BITS + 1: 3], addr_word, 2'b00};
                        mem_valid <= 1'b1;
                        cache_state <= STATE_RW_MISS_3;
                    end
                end
                STATE_RW_MISS_3: begin
                    if (mem_ready) begin


                        cache_line_wb_src <= {2'b1, addr_word};
                        if (cache_way)
                            cache_way_we_0 <= 1'b1;
                        else
                            cache_way_we_1 <= 1'b1;
                        sys_ready <= 1'b1;
                        sys_rdata <= mem_rdata;
                        cache_state <= STATE_WAIT;
                    end
                end
                STATE_WAIT: begin
                    cache_way_we_0 <= 1'b0;
                    cache_way_we_1 <= 1'b0;
                    mem_valid <= 1'b0;
                    `ifdef USE_LONGER_PULSE
                    sys_ready <= 1'b1;
                    if (!sys_valid) begin
                        cache_state <= STATE_IDLE;
                    end
                    `else
                    sys_ready <= 1'b0;
                    cache_state <= STATE_IDLE;
                    `endif
                end
            endcase
        end
    end
    

endmodule
module cache(
    input wire clk,
    input wire rst, 
    input wire [16:0] sys_addr,
    output reg [31:0] sys_rdata,
    input wire sys_valid,
    output reg sys_ready,
    output reg [16:0] mem_addr,
    input wire [31:0] mem_rdata,
    output reg mem_valid,
    input wire mem_ready
    );













    

    






    

    


    

    localparam CACHE_WAY = 2; 
    localparam CACHE_WAY_BITS = 1;
    localparam CACHE_LINE = 256;
    localparam CACHE_LINE_BITS = 8;
    localparam CACHE_LEN = 2;
    localparam CACHE_LEN_ABITS = 1;
    localparam CACHE_LEN_DBITS = 64;
    localparam CACHE_ADDR_BITS = 15;
    localparam CACHE_TAG_BITS = CACHE_ADDR_BITS - CACHE_LINE_BITS - CACHE_LEN_ABITS;
    localparam CACHE_VALID_BITS = 1;
    localparam CACHE_LRU_BITS = 1;
    localparam CACHE_LEN_TOTAL = CACHE_LEN_DBITS + CACHE_TAG_BITS + CACHE_VALID_BITS + CACHE_LRU_BITS;
    
    localparam BIT_TAG_START = 64;
    localparam BIT_TAG_END = 64 + 6 - 1;
    localparam BIT_LRU = 71;
    localparam BIT_VALID = 70;
    
    wire [CACHE_ADDR_BITS - 1: 0] sys_word_addr = sys_addr[CACHE_ADDR_BITS + 1: 2];
    
    wire [CACHE_LEN_ABITS - 1: 0] addr_word = sys_word_addr[CACHE_LEN_ABITS - 1: 0];
    wire [CACHE_LINE_BITS - 1: 0] addr_line = sys_word_addr[CACHE_LINE_BITS + CACHE_LEN_ABITS - 1: CACHE_LEN_ABITS];
    wire [CACHE_TAG_BITS - 1: 0]  addr_tag  = sys_word_addr[CACHE_ADDR_BITS - 1: CACHE_LINE_BITS + CACHE_LEN_ABITS];
    
    wire [CACHE_LEN_TOTAL - 1: 0] cache_way_rd_0;
    wire [CACHE_LEN_TOTAL - 1: 0] cache_way_rd_1;
    wire [CACHE_LEN_TOTAL - 1: 0] cache_way_wr_0;
    wire [CACHE_LEN_TOTAL - 1: 0] cache_way_wr_1;
    reg                           cache_way_we_0;
    reg                           cache_way_we_1;
    
    wire [CACHE_LINE_BITS - 1: 0] addr_line_mux;
    reg addr_line_sel;
    

    bram_256_72 cache_way_0(clk, rst, addr_line_mux, ~rst, cache_way_we_0, cache_way_rd_0, cache_way_wr_0);
    bram_256_72 cache_way_1(clk, rst, addr_line_mux, ~rst, cache_way_we_1, cache_way_rd_1, cache_way_wr_1);
    
    wire cache_comparator_0_comb = ((addr_tag == cache_way_rd_0[BIT_TAG_END: BIT_TAG_START]) && (cache_way_rd_0[BIT_VALID])) ? 1'b1 : 1'b0;
    wire cache_comparator_1_comb = ((addr_tag == cache_way_rd_1[BIT_TAG_END: BIT_TAG_START]) && (cache_way_rd_1[BIT_VALID])) ? 1'b1 : 1'b0;
`ifdef USE_3_CYCLE_CACHE
    reg cache_comparator_0;
    reg cache_comparator_1;
    
    always@(posedge clk) begin
        cache_comparator_0 <= cache_comparator_0_comb;
        cache_comparator_1 <= cache_comparator_1_comb;
    end
`else
    wire cache_comparator_0 = cache_comparator_0_comb;
    wire cache_comparator_1 = cache_comparator_1_comb;
`endif

    wire [31: 0] cache_way_0_output_mux = 
        (addr_word == 1'b0) ? (cache_way_rd_0[31:0]) :
                              (cache_way_rd_0[63:32]);
    wire [31: 0] cache_way_1_output_mux = 
        (addr_word == 1'b0) ? (cache_way_rd_1[31:0]) :
                              (cache_way_rd_1[63:32]);
    
    










    
    wire cache_lru_bit_0 = cache_way_rd_0[BIT_LRU];
    wire cache_lru_bit_1 = cache_way_rd_1[BIT_LRU];
    wire cache_lru_way_0_newer = (cache_lru_bit_0 == cache_lru_bit_1) ? 1 : 0;
    wire cache_lru_way_1_newer = !cache_lru_way_0_newer;

    wire [71: 0] cache_way_0_input_overlay;
    wire [71: 0] cache_way_1_input_overlay;


    assign cache_way_0_input_overlay[BIT_TAG_END: 0] = cache_way_rd_0[BIT_TAG_END: 0];
    assign cache_way_1_input_overlay[BIT_TAG_END: 0] = cache_way_rd_1[BIT_TAG_END: 0];
    assign cache_way_0_input_overlay[BIT_LRU: BIT_VALID] = {cache_way_rd_1[BIT_LRU], 1'b1};
    assign cache_way_1_input_overlay[BIT_LRU: BIT_VALID] = {!cache_way_rd_0[BIT_LRU], 1'b1};
                             
    reg [1:0] cache_line_wb_src;
    assign cache_way_wr_0 = 
        (cache_line_wb_src == 2'b00) ? ({!cache_way_rd_1[BIT_LRU], 71'd0}) : 
        (cache_line_wb_src == 2'b01) ? (cache_way_0_input_overlay) : 
        (cache_line_wb_src == 2'b10) ? ({cache_way_rd_1[BIT_LRU], 1'b1, addr_tag, cache_way_rd_0[63:32], mem_rdata}) :
                                       ({cache_way_rd_1[BIT_LRU], 1'b1, addr_tag, mem_rdata, cache_way_rd_0[31:0]});
    assign cache_way_wr_1 = 
        (cache_line_wb_src == 2'b00) ? ({!cache_way_rd_0[BIT_LRU], 71'd0}) : 
        (cache_line_wb_src == 2'b01) ? (cache_way_1_input_overlay) : 
        (cache_line_wb_src == 2'b10) ? ({cache_way_rd_0[BIT_LRU], 1'b1, addr_tag, cache_way_rd_1[63:32], mem_rdata}) :
                                       ({cache_way_rd_0[BIT_LRU], 1'b1, addr_tag, mem_rdata, cache_way_rd_1[31:0]});
    
    reg [2: 0] cache_state;
    

    localparam STATE_RESET = 3'd0;
    localparam STATE_IDLE = 3'd1;
    localparam STATE_RW_COMPARE = 3'd2;
    localparam STATE_RW_CHECK = 3'd3;
    localparam STATE_RW_MISS_1 = 3'd4;
    localparam STATE_RW_MISS_2 = 3'd5;
    localparam STATE_RW_MISS_3 = 3'd6;
    localparam STATE_WAIT = 3'd7;
    
    reg [CACHE_LINE_BITS - 1: 0] invalidate_counter;
    assign addr_line_mux = (addr_line_sel) ? invalidate_counter : addr_line;
    reg cache_way;
    
    always@(posedge clk) begin
        if (rst) begin
            cache_state <= STATE_RESET;
            sys_ready <= 1'b0;
            mem_valid <= 1'b0;
            cache_way_we_0 <= 1'b0;
            cache_way_we_1 <= 1'b0;
            cache_line_wb_src <= 2'b00;
            invalidate_counter <= 8'hFF;
            addr_line_sel <= 1'b1;
        end
        else begin
            case (cache_state)
                STATE_RESET: begin
                    cache_way_we_0 <= 1'b1;
                    cache_way_we_1 <= 1'b1;
                    invalidate_counter <= invalidate_counter - 1;
                    if (invalidate_counter == 8'd0) begin
                        cache_state <= STATE_IDLE;
                        $display("cache ready");
                    end
                end
                STATE_IDLE: begin
                    addr_line_sel <= 1'b0;
                    cache_way_we_0 <= 1'b0;
                    cache_way_we_1 <= 1'b0;
                    sys_ready <= 1'b0;
                    if (sys_valid) begin
                    `ifdef USE_3_CYCLE_CACHE
                        cache_state <= STATE_RW_COMPARE;
                    `else
                        cache_state <= STATE_RW_CHECK;
                    `endif
                    end
                end
                STATE_RW_COMPARE: begin

                    cache_state <= STATE_RW_CHECK;
                end
                STATE_RW_CHECK: begin
                    if (cache_comparator_0) begin

                        sys_rdata <= cache_way_0_output_mux;
                        sys_ready <= 1'b1;

                        cache_way_we_0 <= 1'b1;
                        cache_way_we_1 <= 1'b0;
                        cache_line_wb_src <= 2'b01;
                        cache_state <= STATE_WAIT;

                    end
                    else if (cache_comparator_1) begin
                        sys_rdata <= cache_way_1_output_mux;
                        sys_ready <= 1'b1;
                        cache_way_we_0 <= 1'b0;
                        cache_way_we_1 <= 1'b1;
                        cache_line_wb_src <= 2'b01;
                        cache_state <= STATE_WAIT;

                    end
                    else begin

                        mem_addr <= {sys_addr[CACHE_ADDR_BITS + 1: 3], !addr_word, 2'b00};
                        mem_valid <= 1'b1;
                        cache_state <= STATE_RW_MISS_1;
                        cache_way <= cache_lru_way_1_newer;

                    end
                end
                STATE_RW_MISS_1: begin
                    if (mem_ready) begin

                        cache_line_wb_src <= {1'b1, !addr_word};
                        if (cache_way)
                            cache_way_we_0 <= 1'b1;
                        else
                            cache_way_we_1 <= 1'b1;
                        mem_valid <= 1'b0;
                        cache_state <= STATE_RW_MISS_2;
                    end
                end
                STATE_RW_MISS_2: begin
                    cache_way_we_0 <= 1'b0;
                    cache_way_we_1 <= 1'b0;
                    if (!mem_ready) begin
                        mem_addr <= {sys_addr[CACHE_ADDR_BITS + 1: 3], addr_word, 2'b00};
                        mem_valid <= 1'b1;
                        cache_state <= STATE_RW_MISS_3;
                    end
                end
                STATE_RW_MISS_3: begin
                    if (mem_ready) begin


                        cache_line_wb_src <= {2'b1, addr_word};
                        if (cache_way)
                            cache_way_we_0 <= 1'b1;
                        else
                            cache_way_we_1 <= 1'b1;
                        sys_ready <= 1'b1;
                        sys_rdata <= mem_rdata;
                        cache_state <= STATE_WAIT;
                    end
                end
                STATE_WAIT: begin
                    cache_way_we_0 <= 1'b0;
                    cache_way_we_1 <= 1'b0;
                    mem_valid <= 1'b0;
                    `ifdef USE_LONGER_PULSE
                    sys_ready <= 1'b1;
                    if (!sys_valid) begin
                        cache_state <= STATE_IDLE;
                    end
                    `else
                    sys_ready <= 1'b0;
                    cache_state <= STATE_IDLE;
                    `endif
                end
            endcase
        end
    end
    

endmodule