data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/capture/signal_phase_DDR.v
 line:79: before: "if"
1: b'%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/capture/signal_phase_DDR.v:124: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'RZERO\' generates 3 bits.\n                                                                                                                 : ... In instance signal_phase_DDR\n   reg [RBITS:0]     phase = RZERO;\n                             ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/capture/signal_phase_DDR.v:248: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'RZERO\' generates 3 bits.\n                                                                                                                 : ... In instance signal_phase_DDR\n        phase <= #DELAY RZERO;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/capture/signal_phase_DDR.v:249: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'RZERO\' generates 3 bits.\n                                                                                                                 : ... In instance signal_phase_DDR\n        delta <= #DELAY RZERO;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/capture/signal_phase_DDR.v:304: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'lnext\' generates 4 bits.\n                                                                                                                 : ... In instance signal_phase_DDR\n        count <= #DELAY lnext;\n              ^~\n%Error: Exiting due to 4 warning(s)\n'
module signal_phase_DDR
  #(
    parameter RATIO = 6,
    parameter RBITS = 3,
    parameter RSB   = RBITS-1,
    parameter RMAX  = RATIO-1,
    parameter RZERO = 3'h0,


    parameter TICKS = 2,
    parameter TSB   = TICKS-1,
    parameter TSC   = TSB-1,
    parameter POLAR = 0,


    parameter LIMIT = 2,
    parameter COUNT = 7,
    parameter CBITS = 3,
    parameter CSB   = CBITS-1,
    parameter CZERO = 0,


    parameter RESET = 0,


    parameter NOISY = 0,
    parameter DELAY = 3)
   (
    input            clk_e_i,
    input            clk_s_i,
    input            clk_n_i,
    input            reset_i,

    input            enable_i,
    input            invert_i,
    output           strobe_o,
    output           middle_o,
    input            sig_p_i,
    input            sig_n_i,


    output [RBITS:0] phase_o,
    output [RBITS:0] delta_o,
    output           locked_o,
    output           error_o,
    input            retry_i,


    output           ref_p_o,
    output           ref_n_o
    );




   reg               pos_e = 1'b0, neg_e = 1'b0;
   reg [TSB:0]       pos, neg;
   reg               stb_p, stb_n;
   wire              pos_w, neg_w, cycled;



   (* NOMERGE = "TRUE" *)
   reg               sig_n, sig_p;
   reg [1:0]         xedge = 2'b00;
   wire              edg_0, edg_1, edg_w;



   wire [RBITS:0]    cnext = cycle + 1;
   wire              cwrap = cycle == RMAX;
   reg [RSB:0]       cycle = RZERO;
   reg [RBITS:0]     phase = RZERO;
   reg signed [RBITS:0] delta;
   wire [RBITS:0]    phase_w = {cycle, xedge[0]};
   wire [RBITS:0]    delta_w = phase_w - phase;


   reg               valid = 1'b0, error = 1'b0;






   assign strobe_o = stb_p;
   assign middle_o = stb_n;
   assign phase_o  = phase;
   assign delta_o  = delta;

   assign locked_o = valid;
   assign error_o  = error;

   assign ref_p_o  = pos[TSB];
   assign ref_n_o  = neg[TSB];





   assign pos_w  = pos[TSB] ^ pos[TSC];
   assign neg_w  = neg[TSB] ^ neg[TSC];

   assign cycled = POLAR ? (pos_w && !invert_i || neg_w && invert_i) : pos_w;







   assign edg_0   = sig_p ^ sig_p_i && sig_n ^ sig_n_i;
   assign edg_1   = sig_p ^ sig_n;




   assign edg_w   = sig_n ^ sig_n_i;











   always @(posedge clk_e_i)
     pos_e <= #DELAY ~pos_e;

   always @(negedge clk_e_i)
     neg_e <= #DELAY ~neg_e;



   always @(posedge clk_s_i)
     if (reset_i && RESET) begin
        pos <= #DELAY {TICKS{1'b0}};
        neg <= #DELAY {TICKS{1'b0}};
     end
     else begin
        pos <= #DELAY {pos[TSC:0], pos_e};
        neg <= #DELAY {neg[TSC:0], neg_e};
     end



   always @(posedge clk_s_i)
     if (reset_i && RESET)
       {xedge, stb_n, stb_p} <= #DELAY 4'h0;
     else begin
        stb_p <= #DELAY pos_w;
        stb_n <= #DELAY neg_w;
        xedge <= #DELAY {edg_1, edg_0};
     end










   always @(posedge clk_s_i)
     if (reset_i && RESET) begin
        sig_p <= #DELAY 1'b0;
        sig_n <= #DELAY 1'b0;
     end
     else begin
        sig_p <= #DELAY sig_p_i;
        sig_n <= #DELAY sig_n_i;
     end







   always @(posedge clk_s_i)
     if (reset_i && RESET || cycled)
       cycle <= #DELAY RZERO;
     else
       cycle <= #DELAY cnext[RSB:0];






   always @(posedge clk_s_i)
     if (reset_i && RESET) begin
        phase <= #DELAY RZERO;
        delta <= #DELAY RZERO;
     end
     else if (xedge[0] || xedge[1]) begin
        phase <= #DELAY phase_w;
        delta <= #DELAY delta_w;
     end








   wire [CBITS:0] lnext;
   wire           lwrap, llost, bound;
   reg [CSB:0]    count = CZERO;
   reg            ledge = 1'b0;


   assign lnext = count + 1;
   assign lwrap = lnext == COUNT[CBITS:0];
   assign llost = valid && (delta < -LIMIT || delta > LIMIT);
   assign bound = -LIMIT <= delta && delta <= LIMIT;




   always @(posedge clk_s_i)
     ledge <= #DELAY enable_i && (|xedge) && !error;



   always @(posedge clk_s_i)
     if (reset_i && RESET || retry_i || !enable_i)
       error <= #DELAY 1'b0;
     else if (valid && !bound)
       error <= #DELAY 1'b1;






   always @(posedge clk_s_i)
     if (reset_i && RESET || error || retry_i || !enable_i) begin
        valid <= #DELAY 1'b0;
        count <= #DELAY CZERO;
     end
     else if (valid) begin
        valid <= #DELAY valid;
        count <= #DELAY count;
     end
     else if (ledge &&  bound) begin
        valid <= #DELAY lwrap;
        count <= #DELAY lnext;
     end
     else if (ledge && !bound) begin
        valid <= #DELAY 1'b0;
        count <= #DELAY CZERO;
     end



endmodule
module signal_phase_DDR
  #(
    parameter RATIO = 6,
    parameter RBITS = 3,
    parameter RSB   = RBITS-1,
    parameter RMAX  = RATIO-1,
    parameter RZERO = 3'h0,


    parameter TICKS = 2,
    parameter TSB   = TICKS-1,
    parameter TSC   = TSB-1,
    parameter POLAR = 0,


    parameter LIMIT = 2,
    parameter COUNT = 7,
    parameter CBITS = 3,
    parameter CSB   = CBITS-1,
    parameter CZERO = 0,


    parameter RESET = 0,


    parameter NOISY = 0,
    parameter DELAY = 3)
   (
    input            clk_e_i,
    input            clk_s_i,
    input            clk_n_i,
    input            reset_i,

    input            enable_i,
    input            invert_i,
    output           strobe_o,
    output           middle_o,
    input            sig_p_i,
    input            sig_n_i,


    output [RBITS:0] phase_o,
    output [RBITS:0] delta_o,
    output           locked_o,
    output           error_o,
    input            retry_i,


    output           ref_p_o,
    output           ref_n_o
    );





   reg               pos_e = 1'b0, neg_e = 1'b0;
   reg [TSB:0]       pos, neg;
   reg               stb_p, stb_n;
   wire              pos_w, neg_w, cycled;



   (* NOMERGE = "TRUE" *)
   reg               sig_n, sig_p;
   reg [1:0]         xedge = 2'b00;
   wire              edg_0, edg_1, edg_w;



   wire [RBITS:0]    cnext = cycle + 1;
   wire              cwrap = cycle == RMAX;
   reg [RSB:0]       cycle = RZERO;
   reg [RBITS:0]     phase = RZERO;
   reg signed [RBITS:0] delta;
   wire [RBITS:0]    phase_w = {cycle, xedge[0]};
   wire [RBITS:0]    delta_w = phase_w - phase;


   reg               valid = 1'b0, error = 1'b0;






   assign strobe_o = stb_p;
   assign middle_o = stb_n;
   assign phase_o  = phase;
   assign delta_o  = delta;

   assign locked_o = valid;
   assign error_o  = error;

   assign ref_p_o  = pos[TSB];
   assign ref_n_o  = neg[TSB];





   assign pos_w  = pos[TSB] ^ pos[TSC];
   assign neg_w  = neg[TSB] ^ neg[TSC];

   assign cycled = POLAR ? (pos_w && !invert_i || neg_w && invert_i) : pos_w;







   assign edg_0   = sig_p ^ sig_p_i && sig_n ^ sig_n_i;
   assign edg_1   = sig_p ^ sig_n;




   assign edg_w   = sig_n ^ sig_n_i;











   always @(posedge clk_e_i)
     pos_e <= #DELAY ~pos_e;

   always @(negedge clk_e_i)
     neg_e <= #DELAY ~neg_e;



   always @(posedge clk_s_i)
     if (reset_i && RESET) begin
        pos <= #DELAY {TICKS{1'b0}};
        neg <= #DELAY {TICKS{1'b0}};
     end
     else begin
        pos <= #DELAY {pos[TSC:0], pos_e};
        neg <= #DELAY {neg[TSC:0], neg_e};
     end



   always @(posedge clk_s_i)
     if (reset_i && RESET)
       {xedge, stb_n, stb_p} <= #DELAY 4'h0;
     else begin
        stb_p <= #DELAY pos_w;
        stb_n <= #DELAY neg_w;
        xedge <= #DELAY {edg_1, edg_0};
     end










   always @(posedge clk_s_i)
     if (reset_i && RESET) begin
        sig_p <= #DELAY 1'b0;
        sig_n <= #DELAY 1'b0;
     end
     else begin
        sig_p <= #DELAY sig_p_i;
        sig_n <= #DELAY sig_n_i;
     end







   always @(posedge clk_s_i)
     if (reset_i && RESET || cycled)
       cycle <= #DELAY RZERO;
     else
       cycle <= #DELAY cnext[RSB:0];






   always @(posedge clk_s_i)
     if (reset_i && RESET) begin
        phase <= #DELAY RZERO;
        delta <= #DELAY RZERO;
     end
     else if (xedge[0] || xedge[1]) begin
        phase <= #DELAY phase_w;
        delta <= #DELAY delta_w;
     end








   wire [CBITS:0] lnext;
   wire           lwrap, llost, bound;
   reg [CSB:0]    count = CZERO;
   reg            ledge = 1'b0;


   assign lnext = count + 1;
   assign lwrap = lnext == COUNT[CBITS:0];
   assign llost = valid && (delta < -LIMIT || delta > LIMIT);
   assign bound = -LIMIT <= delta && delta <= LIMIT;




   always @(posedge clk_s_i)
     ledge <= #DELAY enable_i && (|xedge) && !error;



   always @(posedge clk_s_i)
     if (reset_i && RESET || retry_i || !enable_i)
       error <= #DELAY 1'b0;
     else if (valid && !bound)
       error <= #DELAY 1'b1;






   always @(posedge clk_s_i)
     if (reset_i && RESET || error || retry_i || !enable_i) begin
        valid <= #DELAY 1'b0;
        count <= #DELAY CZERO;
     end
     else if (valid) begin
        valid <= #DELAY valid;
        count <= #DELAY count;
     end
     else if (ledge &&  bound) begin
        valid <= #DELAY lwrap;
        count <= #DELAY lnext;
     end
     else if (ledge && !bound) begin
        valid <= #DELAY 1'b0;
        count <= #DELAY CZERO;
     end



endmodule