data/full_repos/permissive/143278/ivltests/pr1510724.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1510724.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1510724.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module manyNands(y, a, b);
  parameter count = 3;
  output [count-1:0] y;
  input [count-1:0] a, b;

  assign y = ~(a & b);
endmodule
module manyNands(y, a, b);

  parameter count = 3;
  output [count-1:0] y;
  input [count-1:0] a, b;

  assign y = ~(a & b);
endmodule