data/full_repos/permissive/187464337/five_stage_pipelined_computer/pipeline_registers.v
None: at end of input
1: b'%Warning-MULTITOP: data/full_repos/permissive/187464337/five_stage_pipelined_computer/pipeline_registers.v:20: Multiple top level modules\n                                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                             : ... Top module \'if_id_reg\'\nmodule if_id_reg(\n       ^~~~~~~~~\n                                                                                                             : ... Top module \'id_ex_reg\'\nmodule id_ex_reg(\n       ^~~~~~~~~\n                                                                                                             : ... Top module \'ex_mem_reg\'\nmodule ex_mem_reg(\n       ^~~~~~~~~~\n                                                                                                             : ... Top module \'mem_wb_reg\'\nmodule mem_wb_reg(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module if_id_reg(
   input clk,
   input resetn,
   input enable,
   input [31:0] pc4_in,
   input [31:0] instruction_in,
   output reg [31:0] pc4,
   output reg [31:0] instruction
);
   always @(posedge clk)
      if (~resetn) begin
         pc4 <= 0;
         instruction <= 0;
      end else if (enable) begin
         pc4 <= pc4_in;
         instruction <= instruction_in;
      end
endmodule
module if_id_reg(
   input clk,
   input resetn,
   input enable,
   input [31:0] pc4_in,
   input [31:0] instruction_in,
   output reg [31:0] pc4,
   output reg [31:0] instruction
);

   always @(posedge clk)
      if (~resetn) begin
         pc4 <= 0;
         instruction <= 0;
      end else if (enable) begin
         pc4 <= pc4_in;
         instruction <= instruction_in;
      end
endmodule