data/full_repos/permissive/211471959/src/hdl/flash.v
 line:26: before: "="
data/verilator_xmls/ea6d1523-a96f-40de-9e86-bf412349c23d.xml
module flash(
    input clk,
    input reset,
    output reg [15:0] led = 0
    );
    
    integer flash_delay = 0;
    always @(posedge clk, posedge reset) begin
        if (reset) begin
            flash_delay <= 0;
            led <= 0;
        end
        else begin
            if(flash_delay >= 3) begin
                flash_delay <= 0;
                led <= ~led;
            end
            else begin
                flash_delay <= flash_delay + 1;
            end
        end
    end
endmodule
module flash(
    input clk,
    input reset,
    output reg [15:0] led = 0
    );

    
    integer flash_delay = 0;
    always @(posedge clk, posedge reset) begin
        if (reset) begin
            flash_delay <= 0;
            led <= 0;
        end
        else begin
            if(flash_delay >= 3) begin
                flash_delay <= 0;
                led <= ~led;
            end
            else begin
                flash_delay <= flash_delay + 1;
            end
        end
    end
endmodule