data/full_repos/permissive/124844461/Lab1/alu.v
data/verilator_xmls/e5e5d436-1e5d-48d3-8408-e78012cb2f28.xml
module alu(x,y,aluop,result,equal);
input[31:0]x;
input[31:0]y;
input[3:0]aluop;
output reg [31:0]result;
output reg equal;


always@(x or y or aluop)
begin
    case(aluop)
    0:result=x<<(y[4:0]);
    1:result=($signed(x))>>>(y[4:0]);
    2:result=x>>(y[4:0]);
    3:result=x*y;
    4:result=x/y;
    5:result=x+y;
    6:result=x-y;
    7:result=x&y;
    8:result=x|y;
    9:result=x^y;
    10:result=~(x|y);
    11:result= ($signed(x)<$signed(y))?1:0;
    12:result= ($unsigned(x)<$unsigned(y))?1:0;
    default:result=result;
    endcase
end

always@(x or y or aluop)
begin
    equal=(x==y)?1:0;
end
    
endmodule
module alu(x,y,aluop,result,equal);

input[31:0]x;
input[31:0]y;
input[3:0]aluop;
output reg [31:0]result;
output reg equal;


always@(x or y or aluop)
begin
    case(aluop)
    0:result=x<<(y[4:0]);
    1:result=($signed(x))>>>(y[4:0]);
    2:result=x>>(y[4:0]);
    3:result=x*y;
    4:result=x/y;
    5:result=x+y;
    6:result=x-y;
    7:result=x&y;
    8:result=x|y;
    9:result=x^y;
    10:result=~(x|y);
    11:result= ($signed(x)<$signed(y))?1:0;
    12:result= ($unsigned(x)<$unsigned(y))?1:0;
    default:result=result;
    endcase
end

always@(x or y or aluop)
begin
    equal=(x==y)?1:0;
end
    
endmodule