data/full_repos/permissive/143278/ivltests/pr1913937.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1913937.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1913937.v:18: Operator SHIFTL expects 4 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                         : ... In instance test\n   assign a = |((c & ~(1\'b1<<9\'h00)) & b);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1913937.v:18: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s REDOR generates 1 bits.\n                                                                         : ... In instance test\n   assign a = |((c & ~(1\'b1<<9\'h00)) & b);\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1913937.v:27: Operator SHIFTL expects 4 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                         : ... In instance test\n      ra = |((c & ~(1\'b1<<9\'h00)) & b);\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1913937.v:27: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s REDOR generates 1 bits.\n                                                                         : ... In instance test\n      ra = |((c & ~(1\'b1<<9\'h00)) & b);\n         ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ();
   reg pass = 1'b1;

   reg [1:0] ra;
   wire [1:0] a;
   wire [3:0] b = 4'b1111;
   wire [3:0] c = 4'b1111;

   assign a = |((c & ~(1'b1<<9'h00)) & b);

   initial begin
      #1;
      if (a !== 2'b01) begin
          $display("FAILED: cont. assign, expected 2'b01, got %b", a);
          pass = 1'b0;
      end

      ra = |((c & ~(1'b1<<9'h00)) & b);
      if (ra !== 2'b01) begin
          $display("FAILED: proc. assign, expected 2'b01, got %b", ra);
          pass = 1'b0;
      end

      if (pass) $display("PASSED");
   end
endmodule
module test ();

   reg pass = 1'b1;

   reg [1:0] ra;
   wire [1:0] a;
   wire [3:0] b = 4'b1111;
   wire [3:0] c = 4'b1111;

   assign a = |((c & ~(1'b1<<9'h00)) & b);

   initial begin
      #1;
      if (a !== 2'b01) begin
          $display("FAILED: cont. assign, expected 2'b01, got %b", a);
          pass = 1'b0;
      end

      ra = |((c & ~(1'b1<<9'h00)) & b);
      if (ra !== 2'b01) begin
          $display("FAILED: proc. assign, expected 2'b01, got %b", ra);
          pass = 1'b0;
      end

      if (pass) $display("PASSED");
   end
endmodule