data/full_repos/permissive/114091260/material/CPU设计代码/第三步/top.v
1: b'%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top.v:2: Cannot find include file: def.v\n`include "def.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5,data/full_repos/permissive/114091260/def.v\n             data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5,data/full_repos/permissive/114091260/def.v.v\n             data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5,data/full_repos/permissive/114091260/def.v.sv\n             def.v\n             def.v.v\n             def.v.sv\n             obj_dir/def.v\n             obj_dir/def.v.v\n             obj_dir/def.v.sv\n%Error: Exiting due to 1 error(s)\n'
module top(
    input clk,
    input enable,
    input start,
    input rst,
    input [3:0] select_y,
    output [15:0] y
    );
	
	wire [15:0] i_datain;
	wire [15:0] d_datain;
	wire [7:0] i_addr;
	wire [7:0] d_addr;
	wire d_we;
	wire [15:0] d_dataout;

	pcpu u_pcpu (
		.clock(clk), 
		.enable(enable), 
		.reset(rst), 
		.start(start), 
		.i_datain(i_datain), 
		.d_datain(d_datain), 
		.select_y(select_y), 
		.i_addr(i_addr), 
		.d_addr(d_addr), 
		.d_we(d_we), 
		.d_dataout(d_dataout), 
		.y(y)
	);
	i_memory i_mem (
		.clk(clk),
		.rst(rst),
		.addr(i_addr),
		.we(1'b0),
		.datain(16'b0000_0000_0000_0000),
		.dataout(i_datain)
	);
	d_memory d_mem (
		.clk(clk),
		.rst(rst),
		.addr(d_addr),
		.we(d_we),
		.datain(d_dataout),
		.dataout(d_datain)
	);

endmodule
module top(
    input clk,
    input enable,
    input start,
    input rst,
    input [3:0] select_y,
    output [15:0] y
    );

	
	wire [15:0] i_datain;
	wire [15:0] d_datain;
	wire [7:0] i_addr;
	wire [7:0] d_addr;
	wire d_we;
	wire [15:0] d_dataout;

	pcpu u_pcpu (
		.clock(clk), 
		.enable(enable), 
		.reset(rst), 
		.start(start), 
		.i_datain(i_datain), 
		.d_datain(d_datain), 
		.select_y(select_y), 
		.i_addr(i_addr), 
		.d_addr(d_addr), 
		.d_we(d_we), 
		.d_dataout(d_dataout), 
		.y(y)
	);
	i_memory i_mem (
		.clk(clk),
		.rst(rst),
		.addr(i_addr),
		.we(1'b0),
		.datain(16'b0000_0000_0000_0000),
		.dataout(i_datain)
	);
	d_memory d_mem (
		.clk(clk),
		.rst(rst),
		.addr(d_addr),
		.we(d_we),
		.datain(d_dataout),
		.dataout(d_datain)
	);

endmodule