data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v
 line:80: before: "for"
1: b'%Warning-STMTDLY: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #25 clr = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #20 clk = ~clk;\n  ^\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:61: Can\'t find definition of \'dataBUS\' in dotted variable: \'uut.dataBUS\'\n assign dataBUS = uut.dataBUS;\n                      ^~~~~~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:62: Can\'t find definition of \'MAR_out\' in dotted variable: \'uut.MAR_out\'\n assign MAR_out = uut.MAR_out;\n                      ^~~~~~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:63: Can\'t find definition of \'PC\' in dotted signal: \'uut.PC\'\n assign PC_IN = uut.PC.in;\n                    ^~\n        ... Known scopes under \'PC\': uut\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:64: Can\'t find definition of \'IR\' in dotted scope/variable: \'uut.IR\'\n assign opcode = uut.IR.instr[15:12];\n                     ^~\n        ... Known scopes under \'uut\': <no cells found>\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:65: Can\'t find definition of \'IR\' in dotted scope/variable: \'uut.IR\'\n assign instr = uut.IR.instr;\n                    ^~\n        ... Known scopes under \'uut\': <no cells found>\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:66: Can\'t find definition of \'c0\' in dotted variable: \'uut.c0\'\n assign c0 = {uut.c0};\n                  ^~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:67: Can\'t find definition of \'c3\' in dotted variable: \'uut.c3\'\n assign c_line = {uut.c3,uut.c2,uut.c1};\n                      ^~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:67: Can\'t find definition of \'c2\' in dotted variable: \'uut.c2\'\n assign c_line = {uut.c3,uut.c2,uut.c1};\n                             ^~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:67: Can\'t find definition of \'c1\' in dotted variable: \'uut.c1\'\n assign c_line = {uut.c3,uut.c2,uut.c1};\n                                    ^~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:68: Can\'t find definition of \'c4\' in dotted variable: \'uut.c4\'\n assign c4 = {uut.c4};\n                  ^~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:69: Can\'t find definition of \'en7\' in dotted variable: \'uut.en7\'\n assign en_line = {uut.en7,uut.en6,uut.en5,uut.en4,uut.en3,uut.en2,uut.en1,uut.en0};\n                       ^~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:69: Can\'t find definition of \'en6\' in dotted variable: \'uut.en6\'\n assign en_line = {uut.en7,uut.en6,uut.en5,uut.en4,uut.en3,uut.en2,uut.en1,uut.en0};\n                               ^~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:69: Can\'t find definition of \'en5\' in dotted variable: \'uut.en5\'\n assign en_line = {uut.en7,uut.en6,uut.en5,uut.en4,uut.en3,uut.en2,uut.en1,uut.en0};\n                                       ^~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:69: Can\'t find definition of \'en4\' in dotted variable: \'uut.en4\'\n assign en_line = {uut.en7,uut.en6,uut.en5,uut.en4,uut.en3,uut.en2,uut.en1,uut.en0};\n                                               ^~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:69: Can\'t find definition of \'en3\' in dotted variable: \'uut.en3\'\n assign en_line = {uut.en7,uut.en6,uut.en5,uut.en4,uut.en3,uut.en2,uut.en1,uut.en0};\n                                                       ^~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:69: Can\'t find definition of \'en2\' in dotted variable: \'uut.en2\'\n assign en_line = {uut.en7,uut.en6,uut.en5,uut.en4,uut.en3,uut.en2,uut.en1,uut.en0};\n                                                               ^~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:69: Can\'t find definition of \'en1\' in dotted variable: \'uut.en1\'\n assign en_line = {uut.en7,uut.en6,uut.en5,uut.en4,uut.en3,uut.en2,uut.en1,uut.en0};\n                                                                       ^~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:69: Can\'t find definition of \'en0\' in dotted variable: \'uut.en0\'\n assign en_line = {uut.en7,uut.en6,uut.en5,uut.en4,uut.en3,uut.en2,uut.en1,uut.en0};\n                                                                               ^~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:70: Can\'t find definition of \'s2\' in dotted variable: \'uut.s2\'\n assign s_line = {uut.s2,uut.s1};\n                      ^~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:70: Can\'t find definition of \'s1\' in dotted variable: \'uut.s1\'\n assign s_line = {uut.s2,uut.s1};\n                             ^~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:71: Can\'t find definition of \'Controller\' in dotted scope/variable: \'uut.Controller\'\n assign curr_state = uut.Controller.curr_state;\n                         ^~~~~~~~~~\n        ... Known scopes under \'uut\': <no cells found>\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:72: Can\'t find definition of \'Controller\' in dotted scope/variable: \'uut.Controller\'\n assign next_state = uut.Controller.next_state;\n                         ^~~~~~~~~~\n        ... Known scopes under \'uut\': <no cells found>\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:73: Can\'t find definition of \'PC_out\' in dotted variable: \'uut.PC_out\'\n assign PC = uut.PC_out;\n                 ^~~~~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:74: Can\'t find definition of \'MDR\' in dotted signal: \'uut.MDR\'\n assign MDR = uut.MDR.data;\n                  ^~~\n        ... Known scopes under \'MDR\': uut\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:75: Can\'t find definition of \'MAR_in\' in dotted variable: \'uut.MAR_in\'\n assign MAR_in = uut.MAR_in;\n                     ^~~~~~\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:76: Can\'t find definition of \'MAR\' in dotted signal: \'uut.MAR\'\n assign MAR = uut.MAR.out;\n                  ^~~\n        ... Known scopes under \'MAR\': uut\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:77: Can\'t find definition of \'ALU\' in dotted scope/variable: \'uut.ALU\'\n assign accumulator = uut.ALU.accumulator;\n                          ^~~\n        ... Known scopes under \'uut\': <no cells found>\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:81: Can\'t find definition of \'RAM\' in dotted scope/variable: \'uut.RAM\'\n  assign MEM[i] = uut.RAM.MEM[i];\n                      ^~~\n        ... Known scopes under \'uut\': <no cells found>\n%Error: data/full_repos/permissive/16552133/src/verilog/Karpentium_vtf.v:84: Can\'t find definition of \'PM\' in dotted signal: \'uut.PM\'\n  assign PM[i] = uut.PM.pdra[i];\n                     ^~\n        ... Known scopes under \'PM\': <no cells found>\n%Error: Exiting due to 29 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Karpentium_vtf;


	reg clk;
	reg clr;
	reg [15:0] in;


	wire [15:0] out;
	

	Karpentium_Processor_III uut (
		.clk(clk), 
		.clr(clr), 
		.in(in), 
		.out(out)
	);
	

	wire [15:0]MEM [63:0];
	wire [15:0]PM [63:0];
	wire [15:0] dataBUS;
	wire [15:0]accumulator;
	wire [5:0] PC_IN;
	wire [5:0] MAR_out;
	wire [15:0] MDR;
	wire [5:0] PC, MAR_in, MAR;
	wire [1:0] c0;
	wire [1:0] c4;
	wire [2:0] c_line;
	wire [7:0] en_line;
	wire [4:0] s_line;
	wire [5:0] curr_state,next_state;
	wire [15:0] instr;
	wire [3:0] opcode;

	assign dataBUS = uut.dataBUS;
	assign MAR_out = uut.MAR_out;
	assign PC_IN = uut.PC.in;
	assign opcode = uut.IR.instr[15:12];
	assign instr = uut.IR.instr;
	assign c0 = {uut.c0};
	assign c_line = {uut.c3,uut.c2,uut.c1};
	assign c4 = {uut.c4};
	assign en_line = {uut.en7,uut.en6,uut.en5,uut.en4,uut.en3,uut.en2,uut.en1,uut.en0};
	assign s_line = {uut.s2,uut.s1};
	assign curr_state = uut.Controller.curr_state;
	assign next_state = uut.Controller.next_state;
	assign PC = uut.PC_out;
	assign MDR = uut.MDR.data;
	assign MAR_in = uut.MAR_in;
	assign MAR = uut.MAR.out;
	assign accumulator = uut.ALU.accumulator;
	
	genvar i;
	for(i=0;i<64;i=i+1) begin: Memory
		assign MEM[i] = uut.RAM.MEM[i];
	end
	for(i=0;i<64;i=i+1) begin: PrograMEM
		assign PM[i] = uut.PM.pdra[i];
	end
	
	initial begin

		clk = 0;
		clr = 1;
		in = 0;
        

		#25 clr = 0;
	end
	
	always begin
		#20 clk = ~clk;
	end
      
endmodule
module Karpentium_vtf;



	reg clk;
	reg clr;
	reg [15:0] in;


	wire [15:0] out;
	

	Karpentium_Processor_III uut (
		.clk(clk), 
		.clr(clr), 
		.in(in), 
		.out(out)
	);
	

	wire [15:0]MEM [63:0];
	wire [15:0]PM [63:0];
	wire [15:0] dataBUS;
	wire [15:0]accumulator;
	wire [5:0] PC_IN;
	wire [5:0] MAR_out;
	wire [15:0] MDR;
	wire [5:0] PC, MAR_in, MAR;
	wire [1:0] c0;
	wire [1:0] c4;
	wire [2:0] c_line;
	wire [7:0] en_line;
	wire [4:0] s_line;
	wire [5:0] curr_state,next_state;
	wire [15:0] instr;
	wire [3:0] opcode;

	assign dataBUS = uut.dataBUS;
	assign MAR_out = uut.MAR_out;
	assign PC_IN = uut.PC.in;
	assign opcode = uut.IR.instr[15:12];
	assign instr = uut.IR.instr;
	assign c0 = {uut.c0};
	assign c_line = {uut.c3,uut.c2,uut.c1};
	assign c4 = {uut.c4};
	assign en_line = {uut.en7,uut.en6,uut.en5,uut.en4,uut.en3,uut.en2,uut.en1,uut.en0};
	assign s_line = {uut.s2,uut.s1};
	assign curr_state = uut.Controller.curr_state;
	assign next_state = uut.Controller.next_state;
	assign PC = uut.PC_out;
	assign MDR = uut.MDR.data;
	assign MAR_in = uut.MAR_in;
	assign MAR = uut.MAR.out;
	assign accumulator = uut.ALU.accumulator;
	
	genvar i;
	for(i=0;i<64;i=i+1) begin: Memory
		assign MEM[i] = uut.RAM.MEM[i];
	end
	for(i=0;i<64;i=i+1) begin: PrograMEM
		assign PM[i] = uut.PM.pdra[i];
	end
	
	initial begin

		clk = 0;
		clr = 1;
		in = 0;
        

		#25 clr = 0;
	end
	
	always begin
		#20 clk = ~clk;
	end
      
endmodule