data/full_repos/permissive/143278/ivltests/pr772.v
 line:13: before: "("
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr772.v:13: syntax error, unexpected \'@\'\n      repeat (10) @(posedge clk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr772.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #1 reset_b = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr772.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #3 forever #10 clk=~clk;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr772.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #3 forever #10 clk=~clk;\n      ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module err ();

parameter kuku = "AAAAA";


reg reset_b,clk;
initial begin
      reset_b  = 0;
      repeat (10) @(posedge clk);
      #1 reset_b = 1;
end

initial begin
      clk = 1'b1;
      #3 forever #10 clk=~clk;
end






always @(posedge clk or negedge reset_b)
  if (!reset_b) begin
  end
  else begin
    if ((kuku=="RRRRR") || (kuku=="AAAAA") || (kuku=="BBBBB"))
	$display("PASSED");
    else $display("FAILED");
    $finish;
  end


endmodule
module err ();


parameter kuku = "AAAAA";


reg reset_b,clk;
initial begin
      reset_b  = 0;
      repeat (10) @(posedge clk);
      #1 reset_b = 1;
end

initial begin
      clk = 1'b1;
      #3 forever #10 clk=~clk;
end






always @(posedge clk or negedge reset_b)
  if (!reset_b) begin
  end
  else begin
    if ((kuku=="RRRRR") || (kuku=="AAAAA") || (kuku=="BBBBB"))
	$display("PASSED");
    else $display("FAILED");
    $finish;
  end


endmodule