data/full_repos/permissive/167962127/saw_wave.v
data/verilator_xmls/d91fdbbc-d946-45a5-9eb3-e8e334835c19.xml
module saw_wave(
  input i_clk,
  input [15:0] i_addr,
  output reg [15:0] o_data
);

  reg [15:0] r_delay;


  always @ (posedge i_clk)
  begin
    r_delay <= i_addr;
    o_data <= r_delay;
  end

endmodule
module saw_wave(
  input i_clk,
  input [15:0] i_addr,
  output reg [15:0] o_data
);


  reg [15:0] r_delay;


  always @ (posedge i_clk)
  begin
    r_delay <= i_addr;
    o_data <= r_delay;
  end

endmodule