data/full_repos/permissive/127284763/Indicators.v
None: at end of input
data/verilator_xmls/a667e23e-9962-497f-9a6f-02440761e02b.xml
module Indicators(	input  clk,
					input  left,
					input  right,
					input  reset,
					output [5:0] TailLights);

	reg [5:0] state;
 	reg [5:0] nextstate;


 	parameter   S00 = 6'b000000,
 	            SLA = 6'b001000,
                SLB = 6'b011000,
 	            SLC = 6'b111000,
 	            SRA = 6'b000100,
 	            SRB = 6'b000110,
 	            SRC = 6'b000111;


	always @ (posedge clk, posedge reset)
		if (reset) state <= S00;
		else state <= nextstate;


	always @ (*)
		case (state)

			S00:	begin 
                        if (left & ~right) begin
                           nextstate = SLA;
                        end
                        else if (~left & right) begin
                           nextstate = SRA;
                        end
                        else begin
                           nextstate = S00;
                        end
				    end
			SLA:	nextstate = SLB;
			SLB:	nextstate = SLC;
			SLC:	nextstate = S00;
			SRA:	nextstate = SRB;
			SRB:	nextstate = SRC;
			SRC:	nextstate = S00;
			default: nextstate = S00;

		endcase


	assign TailLights = state;


endmodule
module Indicators(	input  clk,
					input  left,
					input  right,
					input  reset,
					output [5:0] TailLights);


	reg [5:0] state;
 	reg [5:0] nextstate;


 	parameter   S00 = 6'b000000,
 	            SLA = 6'b001000,
                SLB = 6'b011000,
 	            SLC = 6'b111000,
 	            SRA = 6'b000100,
 	            SRB = 6'b000110,
 	            SRC = 6'b000111;


	always @ (posedge clk, posedge reset)
		if (reset) state <= S00;
		else state <= nextstate;


	always @ (*)
		case (state)

			S00:	begin 
                        if (left & ~right) begin
                           nextstate = SLA;
                        end
                        else if (~left & right) begin
                           nextstate = SRA;
                        end
                        else begin
                           nextstate = S00;
                        end
				    end
			SLA:	nextstate = SLB;
			SLB:	nextstate = SLC;
			SLC:	nextstate = S00;
			SRA:	nextstate = SRB;
			SRB:	nextstate = SRC;
			SRC:	nextstate = S00;
			default: nextstate = S00;

		endcase


	assign TailLights = state;


endmodule