data/full_repos/permissive/193148725/Timer/Timer.v
1: b"%Error: data/full_repos/permissive/193148725/Timer/Timer.v:21: Cannot find file containing module: 'counter'\ncounter #(.MAX_VAL(DIV_CONST-1), .WIDTH(26) ) freq_div( .i_clk    (i_clk),      \n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193148725/Timer,data/full_repos/permissive/193148725/counter\n             data/full_repos/permissive/193148725/Timer,data/full_repos/permissive/193148725/counter.v\n             data/full_repos/permissive/193148725/Timer,data/full_repos/permissive/193148725/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: data/full_repos/permissive/193148725/Timer/Timer.v:26: Cannot find file containing module: 'posedge_det'\nposedge_det posset (.i_clk(i_clk),   \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/193148725/Timer/Timer.v:31: Cannot find file containing module: 'posedge_det'\nposedge_det posup (.i_clk(i_clk),                   \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/193148725/Timer/Timer.v:35: Cannot find file containing module: 'posedge_det'\nposedge_det posdown (.i_clk(i_clk),                   \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/193148725/Timer/Timer.v:66: Cannot find file containing module: 'dec_7seg'\ndec_7seg    dec_sec_0(.i_dat (o_seg),    \n^~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module Timer(i_clk, i_up, i_down,o_seg_dec, i_set, o_seg);

parameter DIV_CONST = 50_000_000;

wire         div;
wire         pos_up;
wire         pos_down;
wire         pos_set;
wire         tick_1hz;
input        i_clk;
input        i_up;
input        i_down;
input        i_set;
output [6:0] o_seg_dec;
output  reg [3:0]   o_seg;


reg rst_s;


counter #(.MAX_VAL(DIV_CONST-1), .WIDTH(26) ) freq_div( .i_clk    (i_clk),
                                                        .i_rst_n  (i_set), 
                                                        .o_tick   (tick_1hz),
																		  .o_div    (div)
                                                       );
posedge_det posset (.i_clk(i_clk),
						.sig_in(i_set),
                  .sig_out(pos_set));
						
						
posedge_det posup (.i_clk(i_clk),																		 
						.sig_in(i_up),
                  .sig_out(pos_up));

posedge_det posdown (.i_clk(i_clk),																		 
						.sig_in(i_down),
                  .sig_out(pos_down));						
						
always @(posedge i_clk) begin
  if (rst_s == 1'b1) begin
      o_seg <= 4'h0;
      rst_s <= 1'b0;
		if (pos_up) begin
		o_seg <= o_seg + 4'h1;
		end
		if (pos_down) begin
		o_seg <= o_seg - 4'h1;
		end
	end
  else if (rst_s == 1'b0) begin
      rst_s <= 1'b1;
		if (o_seg > 0) begin
			if (tick_1hz) begin
			o_seg <= o_seg - 1'h1;
			end
		end else begin
			if (div) begin
			o_seg <= 4'hA;
			end else begin
			o_seg <= 4'h0;
			end
		end 	
  end
 end
  
dec_7seg    dec_sec_0(.i_dat (o_seg),
                      .o_seg (o_seg_dec)
                      );  
endmodule
module Timer(i_clk, i_up, i_down,o_seg_dec, i_set, o_seg);


parameter DIV_CONST = 50_000_000;

wire         div;
wire         pos_up;
wire         pos_down;
wire         pos_set;
wire         tick_1hz;
input        i_clk;
input        i_up;
input        i_down;
input        i_set;
output [6:0] o_seg_dec;
output  reg [3:0]   o_seg;


reg rst_s;


counter #(.MAX_VAL(DIV_CONST-1), .WIDTH(26) ) freq_div( .i_clk    (i_clk),
                                                        .i_rst_n  (i_set), 
                                                        .o_tick   (tick_1hz),
																		  .o_div    (div)
                                                       );
posedge_det posset (.i_clk(i_clk),
						.sig_in(i_set),
                  .sig_out(pos_set));
						
						
posedge_det posup (.i_clk(i_clk),																		 
						.sig_in(i_up),
                  .sig_out(pos_up));

posedge_det posdown (.i_clk(i_clk),																		 
						.sig_in(i_down),
                  .sig_out(pos_down));						
						
always @(posedge i_clk) begin
  if (rst_s == 1'b1) begin
      o_seg <= 4'h0;
      rst_s <= 1'b0;
		if (pos_up) begin
		o_seg <= o_seg + 4'h1;
		end
		if (pos_down) begin
		o_seg <= o_seg - 4'h1;
		end
	end
  else if (rst_s == 1'b0) begin
      rst_s <= 1'b1;
		if (o_seg > 0) begin
			if (tick_1hz) begin
			o_seg <= o_seg - 1'h1;
			end
		end else begin
			if (div) begin
			o_seg <= 4'hA;
			end else begin
			o_seg <= 4'h0;
			end
		end 	
  end
 end
  
dec_7seg    dec_sec_0(.i_dat (o_seg),
                      .o_seg (o_seg_dec)
                      );  
endmodule