data/full_repos/permissive/1840016/lab1/mux.v
data/verilator_xmls/50323ae7-112f-4d38-81f5-6fd9f28963b1.xml
module mux (in_a, in_b, sel, out);
	input in_a, in_b, sel;
	output out; 

	reg out;

	always @(in_a or in_b or sel)
	begin
		case(sel)
		1'b0: out = in_a;
		1'b1: out = in_b;
		endcase
	end
endmodule
module mux (in_a, in_b, sel, out);

	input in_a, in_b, sel;
	output out; 

	reg out;

	always @(in_a or in_b or sel)
	begin
		case(sel)
		1'b0: out = in_a;
		1'b1: out = in_b;
		endcase
	end
endmodule