data/full_repos/permissive/206842334/testbenches/conv_ctrl_tb.v
 line:19: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/conv_ctrl_tb.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/conv_ctrl_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #10 enclk = ~enclk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/conv_ctrl_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #10 enclk = ~enclk;\n    ^\n%Error: data/full_repos/permissive/206842334/testbenches/conv_ctrl_tb.v:30: Cannot find file containing module: \'conv_ctrl\'\nconv_ctrl groundctrl (clk, reset, en_ctrl, s_addr, w_addr, b_addr, save_addr, en_sum, en_save, en_read, en_write, en_mac, finish);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/conv_ctrl\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/conv_ctrl.v\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/conv_ctrl.sv\n             conv_ctrl\n             conv_ctrl.v\n             conv_ctrl.sv\n             obj_dir/conv_ctrl\n             obj_dir/conv_ctrl.v\n             obj_dir/conv_ctrl.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module conv_ctrl_tb;

reg clk, reset, en_ctrl, enclk;
wire en_sum, finish, en_save, en_read, en_write, en_mac;
wire [15:0] s_addr, w_addr, b_addr, save_addr;

localparam CLK_PERIOD = 20;
always #(CLK_PERIOD/2) clk=~clk;

task run_clock;
begin
    #10 enclk = ~enclk;
    #10 enclk = ~enclk;
end
endtask

initial begin
    clk<=1'b0; reset <= 1;
    run_clock; reset <= 0; 
    run_clock; en_ctrl <= 1;
end

always @(posedge clk) begin
    if(finish) begin
        en_ctrl <= 0;
        $stop;
    end
end

conv_ctrl groundctrl (clk, reset, en_ctrl, s_addr, w_addr, b_addr, save_addr, en_sum, en_save, en_read, en_write, en_mac, finish);

endmodule
module conv_ctrl_tb;


reg clk, reset, en_ctrl, enclk;
wire en_sum, finish, en_save, en_read, en_write, en_mac;
wire [15:0] s_addr, w_addr, b_addr, save_addr;

localparam CLK_PERIOD = 20;
always #(CLK_PERIOD/2) clk=~clk;

task run_clock;
begin
    #10 enclk = ~enclk;
    #10 enclk = ~enclk;
end
endtask

initial begin
    clk<=1'b0; reset <= 1;
    run_clock; reset <= 0; 
    run_clock; en_ctrl <= 1;
end

always @(posedge clk) begin
    if(finish) begin
        en_ctrl <= 0;
        $stop;
    end
end

conv_ctrl groundctrl (clk, reset, en_ctrl, s_addr, w_addr, b_addr, save_addr, en_sum, en_save, en_read, en_write, en_mac, finish);

endmodule