data/full_repos/permissive/143278/contrib/div16.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:176: Unsupported: Ignoring delay on this delayed statement.\n   #200;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/contrib/div16.v:221: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:222: Unsupported: Ignoring delay on this delayed statement.\n      #1 start = 1;\n      ^\n%Error: data/full_repos/permissive/143278/contrib/div16.v:223: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:224: Unsupported: Ignoring delay on this delayed statement.\n      #1 start = 0;\n      ^\n%Error: data/full_repos/permissive/143278/contrib/div16.v:225: syntax error, unexpected \'@\'\n      while (~done) @(posedge clk);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:226: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:245: Unsupported: Ignoring delay on this delayed statement.\n      #10 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:246: Unsupported: Ignoring delay on this delayed statement.\n      #10 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/contrib/div16.v:252: Unsupported: Ignoring delay on this delayed statement.\n   #133 resetb = 1;\n   ^\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module div16 (clk, resetb, start, a, b, q, r, done);

parameter N = 16;

input		clk;
input		resetb;
input		start;
input [N-1:0]	a;
input [N-1:0]	b;
output [N-1:0]	q;
output [N-1:0]	r;
output		done;


reg [N-1:0]	q;
reg		done;





reg [N-1:0]	power;






reg [N-1:0]	accum;




reg [(2*N-1):0]	bpower;


assign r = accum;




wire [2*N-1:0] accum_minus_bpower = accum - bpower;

always @(posedge clk or negedge resetb) begin
   if (~resetb) begin
      q <= 0;
      accum <= 0;
      power <= 0;
      bpower <= 0;
      done <= 0;
   end
   else begin
      if (start) begin

         q      <= 0;
         accum  <= a;
         power[N-1] <= 1'b1;
         bpower <= b << N-1;
         done <= 0;
      end
      else begin


         if (power != 0) begin




            if ( ~accum_minus_bpower[2*N-1]) begin



               q     <= q | power;
               accum <= accum_minus_bpower;
            end


            power  <= power >> 1;
            bpower <= bpower >> 1;
         end
         else begin

            done <= 1;
         end
      end
   end
end
endmodule
module div16 (clk, resetb, start, a, b, q, r, done);


parameter N = 16;

input		clk;
input		resetb;
input		start;
input [N-1:0]	a;
input [N-1:0]	b;
output [N-1:0]	q;
output [N-1:0]	r;
output		done;


reg [N-1:0]	q;
reg		done;





reg [N-1:0]	power;






reg [N-1:0]	accum;




reg [(2*N-1):0]	bpower;


assign r = accum;




wire [2*N-1:0] accum_minus_bpower = accum - bpower;

always @(posedge clk or negedge resetb) begin
   if (~resetb) begin
      q <= 0;
      accum <= 0;
      power <= 0;
      bpower <= 0;
      done <= 0;
   end
   else begin
      if (start) begin

         q      <= 0;
         accum  <= a;
         power[N-1] <= 1'b1;
         bpower <= b << N-1;
         done <= 0;
      end
      else begin


         if (power != 0) begin




            if ( ~accum_minus_bpower[2*N-1]) begin



               q     <= q | power;
               accum <= accum_minus_bpower;
            end


            power  <= power >> 1;
            bpower <= bpower >> 1;
         end
         else begin

            done <= 1;
         end
      end
   end
end
endmodule