data/full_repos/permissive/108164888/main/code/test_bench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/108164888/main/code/test_bench.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/108164888/main/code/test_bench.v:35: Cannot find file containing module: \'ReductionModulo\'\n ReductionModulo uut (\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/108164888/main/code,data/full_repos/permissive/108164888/ReductionModulo\n             data/full_repos/permissive/108164888/main/code,data/full_repos/permissive/108164888/ReductionModulo.v\n             data/full_repos/permissive/108164888/main/code,data/full_repos/permissive/108164888/ReductionModulo.sv\n             ReductionModulo\n             ReductionModulo.v\n             ReductionModulo.sv\n             obj_dir/ReductionModulo\n             obj_dir/ReductionModulo.v\n             obj_dir/ReductionModulo.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_bench;


	reg [31:0] number;
	reg [31:0] m;


	wire [31:0] result;


	ReductionModulo uut (
		.number(number), 
		.m(m), 
		.result(result)
	);

	initial begin

		number = 13;
		m = 3;


		#100;
        


	end
	
endmodule
module test_bench;



	reg [31:0] number;
	reg [31:0] m;


	wire [31:0] result;


	ReductionModulo uut (
		.number(number), 
		.m(m), 
		.result(result)
	);

	initial begin

		number = 13;
		m = 3;


		#100;
        


	end
	
endmodule