data/full_repos/permissive/122184933/FPGA/gray.v
 line:14: before: "int"
data/verilator_xmls/0eb64fd5-b6a6-4035-a401-b1f4dda97f79.xml
module gray # (

	parameter WIDTH = 8
)
(

	input wire clk, rst, enable,

	output reg [WIDTH-1:0] out
);


reg [WIDTH-1:0] cnt;

integer i;


always @ (posedge clk or posedge rst)
begin

	if (rst) begin
		out <= 0; cnt <= 1;

	end else if (enable) begin

		cnt <= cnt + 1'b1;

		out[WIDTH - 1] <= cnt[WIDTH-1];

		for (i = 0; i < WIDTH-1; i = i + 1) 
			out[i] <= cnt[i] ^ cnt[i+1];
	end
end

endmodule
module gray # (

	parameter WIDTH = 8
)
(

	input wire clk, rst, enable,

	output reg [WIDTH-1:0] out
);



reg [WIDTH-1:0] cnt;

integer i;


always @ (posedge clk or posedge rst)
begin

	if (rst) begin
		out <= 0; cnt <= 1;

	end else if (enable) begin

		cnt <= cnt + 1'b1;

		out[WIDTH - 1] <= cnt[WIDTH-1];

		for (i = 0; i < WIDTH-1; i = i + 1) 
			out[i] <= cnt[i] ^ cnt[i+1];
	end
end

endmodule