data/full_repos/permissive/205055389/test/verga/display1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/205055389/test/verga/display1.v:9: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                            : ... In instance top\n        d = a[4:2];\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205055389/test/verga/display1.v:10: Bit extraction of var[7:0] requires 3 bit index, not 8 bits.\n                                                                             : ... In instance top\n $display("%h",a[c +: 4]);\n                ^\n%Error: Exiting due to 2 warning(s)\n'
module top;
  reg [7:0] a,b,c,d;

  initial
    begin
	a = 8'h7a;
	b = 0;
        c = 1;
        d = a[4:2];
	$display("%h",a[c +: 4]);
	$display("%h",a[4:2]);
	$display("%h",d);
    end

endmodule
module top;

  reg [7:0] a,b,c,d;

  initial
    begin
	a = 8'h7a;
	b = 0;
        c = 1;
        d = a[4:2];
	$display("%h",a[c +: 4]);
	$display("%h",a[4:2]);
	$display("%h",d);
    end

endmodule