data/full_repos/permissive/191467986/rtl/ALU.v
data/verilator_xmls/81268530-1e6e-4a7c-86e5-4e3d78054fb6.xml
module ALU
(

    input   [DATA_WIDTH - 1:0]  i_A_DATA,
    input   [DATA_WIDTH - 1:0]  i_B_DATA,
    input                       i_WRITE_BUS,
    input                       i_SUB,
    output   [DATA_WIDTH - 1:0] o_BUS,


    input                       i_CLOCK,
    input                       i_CLEAR,
    input                       i_UPDATE_FLAGS,

    output                      o_ZERO_FLAG,
    output                      o_CARRY_FLAG
);

    parameter   DATA_WIDTH = 8;


    reg [DATA_WIDTH:0]  r_RESULT    = 0;



    reg [1:0]           r_FLAGS     = 2'b10;


    always @(i_A_DATA, i_B_DATA, i_SUB)
    begin
        if(i_SUB)
            r_RESULT = i_A_DATA - i_B_DATA;
        else
            r_RESULT = i_A_DATA + i_B_DATA;
    end


    always @(posedge i_CLOCK, posedge i_CLEAR)
    begin

        if(i_CLEAR)
            r_FLAGS <= 0;
        else begin

            if(i_UPDATE_FLAGS) begin

                r_FLAGS[1:1] <= (r_RESULT == 0) ? 1'b1 : 1'b0;


                r_FLAGS[0:0] <= r_RESULT[DATA_WIDTH:DATA_WIDTH];
            end
        end
    end

    assign o_BUS = (i_WRITE_BUS) ? r_RESULT[DATA_WIDTH - 1:0] : {DATA_WIDTH {1'bz}};
    assign o_ZERO_FLAG = r_FLAGS[1:1];
    assign o_CARRY_FLAG = r_FLAGS[0:0];
endmodule
module ALU
(

    input   [DATA_WIDTH - 1:0]  i_A_DATA,
    input   [DATA_WIDTH - 1:0]  i_B_DATA,
    input                       i_WRITE_BUS,
    input                       i_SUB,
    output   [DATA_WIDTH - 1:0] o_BUS,


    input                       i_CLOCK,
    input                       i_CLEAR,
    input                       i_UPDATE_FLAGS,

    output                      o_ZERO_FLAG,
    output                      o_CARRY_FLAG
);


    parameter   DATA_WIDTH = 8;


    reg [DATA_WIDTH:0]  r_RESULT    = 0;



    reg [1:0]           r_FLAGS     = 2'b10;


    always @(i_A_DATA, i_B_DATA, i_SUB)
    begin
        if(i_SUB)
            r_RESULT = i_A_DATA - i_B_DATA;
        else
            r_RESULT = i_A_DATA + i_B_DATA;
    end


    always @(posedge i_CLOCK, posedge i_CLEAR)
    begin

        if(i_CLEAR)
            r_FLAGS <= 0;
        else begin

            if(i_UPDATE_FLAGS) begin

                r_FLAGS[1:1] <= (r_RESULT == 0) ? 1'b1 : 1'b0;


                r_FLAGS[0:0] <= r_RESULT[DATA_WIDTH:DATA_WIDTH];
            end
        end
    end

    assign o_BUS = (i_WRITE_BUS) ? r_RESULT[DATA_WIDTH - 1:0] : {DATA_WIDTH {1'bz}};
    assign o_ZERO_FLAG = r_FLAGS[1:1];
    assign o_CARRY_FLAG = r_FLAGS[0:0];
endmodule