data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/memory/imem.v
data/verilator_xmls/95c65f8f-bae8-4ff4-88af-2f13de7f507f.xml
module imem (
        input  wire [5:0]  a,
        output wire [31:0] y
    );

    reg [31:0] rom [0:63];

    initial begin
        $readmemh ("memfile.dat", rom);
    end

    assign y = rom[a];
    
endmodule
module imem (
        input  wire [5:0]  a,
        output wire [31:0] y
    );


    reg [31:0] rom [0:63];

    initial begin
        $readmemh ("memfile.dat", rom);
    end

    assign y = rom[a];
    
endmodule