data/full_repos/permissive/147086086/Lab2/hw/nco/nco_tb.v
 line:26: before: "i_rst_n"
1: b'%Warning-STMTDLY: data/full_repos/permissive/147086086/Lab2/hw/nco/nco_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    forever #(PERIOD/2) i_clk = ~i_clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/147086086/Lab2/hw/nco/nco_tb.v:26: syntax error, unexpected \'@\'\n    @(negedge i_clk) i_rst_n = 1\'b1;\n    ^\n%Error: data/full_repos/permissive/147086086/Lab2/hw/nco/nco_tb.v:29: syntax error, unexpected \'@\'\n        repeat (500000) @(negedge i_clk);\n                        ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

parameter PERIOD = 20;

reg         i_clk, i_rst_n;
reg  [9:0]  i_freq_step;
wire [3:0]  o_dac;

nco  nco_inst(.MAX10_CLK1_50 (i_clk), 
                .KEY ({i_rst_n, 1'b0}),
                .SW (i_freq_step), 
                .VGA_R (o_dac)
                );

initial begin
    i_clk = 0;
    forever #(PERIOD/2) i_clk = ~i_clk;
end

initial begin
    i_rst_n = 1'b0;
    i_freq_step = 10'd64;

    @(negedge i_clk) i_rst_n = 1'b1;

    repeat (15) begin
        repeat (500000) @(negedge i_clk);
        i_freq_step = i_freq_step + 50;
    end

    $finish;  
end
  
endmodule
module testbench;


parameter PERIOD = 20;

reg         i_clk, i_rst_n;
reg  [9:0]  i_freq_step;
wire [3:0]  o_dac;

nco  nco_inst(.MAX10_CLK1_50 (i_clk), 
                .KEY ({i_rst_n, 1'b0}),
                .SW (i_freq_step), 
                .VGA_R (o_dac)
                );

initial begin
    i_clk = 0;
    forever #(PERIOD/2) i_clk = ~i_clk;
end

initial begin
    i_rst_n = 1'b0;
    i_freq_step = 10'd64;

    @(negedge i_clk) i_rst_n = 1'b1;

    repeat (15) begin
        repeat (500000) @(negedge i_clk);
        i_freq_step = i_freq_step + 50;
    end

    $finish;  
end
  
endmodule