data/full_repos/permissive/219943485/keyboard.v
data/verilator_xmls/20dc33e4-4a6b-45d8-a7db-607dc6dd1413.xml
module keyboard(
          			clk, 
						rst_n,
                  left,
                  down,
                  right,
                  up,
						ps2_data,
                  ps2_clk

);
               
input 					 clk;
input 					 rst_n;
input					    ps2_data;
input                 ps2_clk;
output					 left;
output					 down;
output					 right;
output					 up;


reg [21:0] data_temp;

reg  left;
reg  down;
reg  right;
reg  up;         
		     
wire ps2clk_neg;


reg [1:0] left_temp;
reg [1:0] right_temp;
reg [1:0] down_temp;
reg [1:0] up_temp;
wire left_neg;
wire down_neg;
wire right_neg;
wire up_neg;




reg [1:0] clk_temp;


always @ (posedge clk)
begin
    clk_temp <= {clk_temp[0], ps2_clk};
end

assign ps2clk_neg = (clk_temp == 2'b10);


/


always @ (posedge clk or negedge rst_n)
begin
    if (~rst_n)
       left <= 1'd0;
    else if (data_temp == 22'b10011010110_10111000000)
		 left <= 1'b1;
    else if (data_temp == 22'b10011010110_11111100000)
		 left <= 1'b0;
end

always @ (posedge clk or negedge rst_n)
begin
    if (~rst_n)
       down <= 1'd0;
    else if (data_temp == 22'b11011100100_10111000000)
		 down <= 1'b1;
    else if (data_temp == 22'b11011100100_11111100000)
		 down <= 1'b0;
end

always @ (posedge clk or negedge rst_n)
begin
    if (~rst_n)
       right <= 1'd0;
    else if (data_temp == 22'b11011101000_10111000000)
		 right <= 1'b1;
    else if (data_temp == 22'b11011101000_11111100000)
		 right <= 1'b0;
end

always @ (posedge clk or negedge rst_n)
begin
    if (~rst_n)
       up <= 1'd0;
    else if (data_temp == 22'b10011101010_10111000000)
		 up <= 1'b1;
    else if (data_temp == 22'b10011101010_11111100000)
		 up <= 1'b0;
end

endmodule
module keyboard(
          			clk, 
						rst_n,
                  left,
                  down,
                  right,
                  up,
						ps2_data,
                  ps2_clk

);

               
input 					 clk;
input 					 rst_n;
input					    ps2_data;
input                 ps2_clk;
output					 left;
output					 down;
output					 right;
output					 up;


reg [21:0] data_temp;

reg  left;
reg  down;
reg  right;
reg  up;         
		     
wire ps2clk_neg;


reg [1:0] left_temp;
reg [1:0] right_temp;
reg [1:0] down_temp;
reg [1:0] up_temp;
wire left_neg;
wire down_neg;
wire right_neg;
wire up_neg;




reg [1:0] clk_temp;


always @ (posedge clk)
begin
    clk_temp <= {clk_temp[0], ps2_clk};
end

assign ps2clk_neg = (clk_temp == 2'b10);


/


always @ (posedge clk or negedge rst_n)
begin
    if (~rst_n)
       left <= 1'd0;
    else if (data_temp == 22'b10011010110_10111000000)
		 left <= 1'b1;
    else if (data_temp == 22'b10011010110_11111100000)
		 left <= 1'b0;
end

always @ (posedge clk or negedge rst_n)
begin
    if (~rst_n)
       down <= 1'd0;
    else if (data_temp == 22'b11011100100_10111000000)
		 down <= 1'b1;
    else if (data_temp == 22'b11011100100_11111100000)
		 down <= 1'b0;
end

always @ (posedge clk or negedge rst_n)
begin
    if (~rst_n)
       right <= 1'd0;
    else if (data_temp == 22'b11011101000_10111000000)
		 right <= 1'b1;
    else if (data_temp == 22'b11011101000_11111100000)
		 right <= 1'b0;
end

always @ (posedge clk or negedge rst_n)
begin
    if (~rst_n)
       up <= 1'd0;
    else if (data_temp == 22'b10011101010_10111000000)
		 up <= 1'b1;
    else if (data_temp == 22'b10011101010_11111100000)
		 up <= 1'b0;
end

endmodule