data/full_repos/permissive/188595972/src/clocks.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/188595972/src/clocks.v:32: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'ClockModule\'\nmodule ClockModule(clk,rst_n,clk_m); \n       ^~~~~~~~~~~\n                                                                       : ... Top module \'KeyboardClockModule\'\nmodule KeyboardClockModule(clk_modified,clk,rst_n);\n       ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module ClockModule(clk,rst_n,clk_m);
    input clk,rst_n;
    output reg clk_m;
    reg [2:0]count,Y;
    reg clk_Y;
    always@(negedge clk or negedge rst_n)
        if(!rst_n)
          begin
            count<=3'b000;
            clk_m<=1'b0;
          end
        else
          begin
            count<=Y;
            clk_m<=clk_Y;
          end
    always@(count or clk_m)
      begin
        if(count==3'b100)
          begin
            Y=3'b000;
            clk_Y=~clk_m;
          end
        else
          begin
            Y=count+3'b1;
            clk_Y=clk_m;
          end
      end
    endmodule
module ClockModule(clk,rst_n,clk_m);

    input clk,rst_n;
    output reg clk_m;
    reg [2:0]count,Y;
    reg clk_Y;
    always@(negedge clk or negedge rst_n)
        if(!rst_n)
          begin
            count<=3'b000;
            clk_m<=1'b0;
          end
        else
          begin
            count<=Y;
            clk_m<=clk_Y;
          end
    always@(count or clk_m)
      begin
        if(count==3'b100)
          begin
            Y=3'b000;
            clk_Y=~clk_m;
          end
        else
          begin
            Y=count+3'b1;
            clk_Y=clk_m;
          end
      end
    endmodule