data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/reg_r_det_early.v
data/verilator_xmls/3480a8c0-9940-49fc-a51c-4fe9bfe727b8.xml
module reg_r_det_early(
	      input wire clk,
	      input wire [18:0] bus_a,
	      input wire [18:0] my_a,
	      input wire ena,
	      output wire pulse

	      );

   reg 			  gotread, gotread_d;
   reg [7:0] 		  state;
   
   always @(posedge clk) begin
      if( (bus_a[18:1] == my_a[18:1]) && ena ) begin
	 gotread <= 1'b1;
      end else begin
	 gotread <= 1'b0;
      end
   end

   always @(posedge clk) begin
      gotread_d <= gotread;
   end

   assign pulse = !gotread_d && gotread;
   
endmodule
module reg_r_det_early(
	      input wire clk,
	      input wire [18:0] bus_a,
	      input wire [18:0] my_a,
	      input wire ena,
	      output wire pulse

	      );


   reg 			  gotread, gotread_d;
   reg [7:0] 		  state;
   
   always @(posedge clk) begin
      if( (bus_a[18:1] == my_a[18:1]) && ena ) begin
	 gotread <= 1'b1;
      end else begin
	 gotread <= 1'b0;
      end
   end

   always @(posedge clk) begin
      gotread_d <= gotread;
   end

   assign pulse = !gotread_d && gotread;
   
endmodule