data/full_repos/permissive/121803953/Lab1/lab1.v
data/verilator_xmls/012f2d9a-376f-4eca-8f5d-548a280b9e02.xml
module lab1a(a, b, c, d, R, U, K);
	input a, b, c, d;
	output R, U, K;
	part1 mod1(a, b, c, R);
	part2 mod2(a, b, c, d, U);
	part3 mod3(a, b, K);
endmodule
module lab1a(a, b, c, d, R, U, K);

	input a, b, c, d;
	output R, U, K;
	part1 mod1(a, b, c, R);
	part2 mod2(a, b, c, d, U);
	part3 mod3(a, b, K);
endmodule