data/full_repos/permissive/129155059/proyecto-01/byte_joining/tester.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/tester.v:28: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("bytejoining.vcd");  \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/tester.v:29: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;    \n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_joining/tester.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #1 LE = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_joining/tester.v:43: Unsupported: Ignoring delay on this delayed statement.\n   #1 Contador = 0;\n   ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/tester.v:46: syntax error, unexpected \'@\'\n  @(posedge clk250k);\n  ^\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/tester.v:50: syntax error, unexpected \'@\'\n   @(posedge clk250k);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_joining/tester.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #100 LE = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_joining/tester.v:59: Unsupported: Ignoring delay on this delayed statement.\n   #1 Contador = dato;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_joining/tester.v:65: Unsupported: Ignoring delay on this delayed statement.\n always #2000 clk250k  <= ~clk250k;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_joining/tester.v:66: Unsupported: Ignoring delay on this delayed statement.\n always  #500 clk1Mhz <= ~clk1Mhz;  \n         ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester(
	input [7:0] byte_joining_desc_cond,
	input [7:0] byte_joining_desc_estruc,
	output reg [1:0] ctr_3,
	output reg [7:0] Lane_0,
  output reg [7:0] Lane_1,
  output reg [7:0] Lane_2,
  output reg [7:0] Lane_3,
	output reg clk250k
	);





	reg [31:0] Contador;
	reg [2:0] dir;
	reg LE;
	wire [31:0] dato;

	memTrans m1 (dir, LE, dato);

	assign dato = (~LE)? Contador : 32'bz;

  reg clk1Mhz;

	initial begin
		$dumpfile("bytejoining.vcd");
		$dumpvars;
		clk1Mhz <= 1;
		clk250k <= 1 ;
		Lane_0 <= 8'b00000000;
		Lane_1 <= 8'b00000001;
		Lane_2 <= 8'b00000010;
    Lane_3 <= 8'b00000100;
		ctr_3 <=2'b11;



		#1 LE = 0;
		Contador = 0;
		for (dir=0; dir<=5; dir=dir+1) begin
			#1 Contador = 0;
		end

		@(posedge clk250k);
		@(posedge clk250k);

		repeat (16) begin
			@(posedge clk250k);
      Lane_0 <= Lane_0 + 1;
      Lane_1 <= Lane_1 + 1;
      Lane_2 <= Lane_2 + 1;
      Lane_3 <= Lane_3 + 1;
		end

		#100 LE = 1;
		for (dir=0; dir<= 5; dir=dir+1) begin
			#1 Contador = dato;
		 	$display("PwrCntr[%d]: %d", dir, Contador);
		end
		$finish;
	end

	always	#2000 clk250k 	<= ~clk250k;
	always 	#500 clk1Mhz <= ~clk1Mhz;
  always @ (posedge clk1Mhz) begin
    if (ctr_3 == 2'b11) begin
      ctr_3 <= 2'b00;
    end else begin
      ctr_3 <= ctr_3 + 1;
    end
  end

endmodule
module tester(
	input [7:0] byte_joining_desc_cond,
	input [7:0] byte_joining_desc_estruc,
	output reg [1:0] ctr_3,
	output reg [7:0] Lane_0,
  output reg [7:0] Lane_1,
  output reg [7:0] Lane_2,
  output reg [7:0] Lane_3,
	output reg clk250k
	);






	reg [31:0] Contador;
	reg [2:0] dir;
	reg LE;
	wire [31:0] dato;

	memTrans m1 (dir, LE, dato);

	assign dato = (~LE)? Contador : 32'bz;

  reg clk1Mhz;

	initial begin
		$dumpfile("bytejoining.vcd");
		$dumpvars;
		clk1Mhz <= 1;
		clk250k <= 1 ;
		Lane_0 <= 8'b00000000;
		Lane_1 <= 8'b00000001;
		Lane_2 <= 8'b00000010;
    Lane_3 <= 8'b00000100;
		ctr_3 <=2'b11;



		#1 LE = 0;
		Contador = 0;
		for (dir=0; dir<=5; dir=dir+1) begin
			#1 Contador = 0;
		end

		@(posedge clk250k);
		@(posedge clk250k);

		repeat (16) begin
			@(posedge clk250k);
      Lane_0 <= Lane_0 + 1;
      Lane_1 <= Lane_1 + 1;
      Lane_2 <= Lane_2 + 1;
      Lane_3 <= Lane_3 + 1;
		end

		#100 LE = 1;
		for (dir=0; dir<= 5; dir=dir+1) begin
			#1 Contador = dato;
		 	$display("PwrCntr[%d]: %d", dir, Contador);
		end
		$finish;
	end

	always	#2000 clk250k 	<= ~clk250k;
	always 	#500 clk1Mhz <= ~clk1Mhz;
  always @ (posedge clk1Mhz) begin
    if (ctr_3 == 2'b11) begin
      ctr_3 <= 2'b00;
    end else begin
      ctr_3 <= ctr_3 + 1;
    end
  end

endmodule