data/full_repos/permissive/193790231/lab04/lab04part03.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/193790231/lab04/lab04part03.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/193790231/lab04/lab04part03.v:8: Cannot find file containing module: \'count1\'\n count1 lpmcount(KEY[1], SW[0], SW[1], LEDR[15:0]);\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193790231/lab04,data/full_repos/permissive/193790231/count1\n             data/full_repos/permissive/193790231/lab04,data/full_repos/permissive/193790231/count1.v\n             data/full_repos/permissive/193790231/lab04,data/full_repos/permissive/193790231/count1.sv\n             count1\n             count1.v\n             count1.sv\n             obj_dir/count1\n             obj_dir/count1.v\n             obj_dir/count1.sv\n%Error: data/full_repos/permissive/193790231/lab04/lab04part03.v:9: Cannot find file containing module: \'hexDecoder7Seg\'\n hexDecoder7Seg h3(HEX3[6:0], LEDR[15:12]);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193790231/lab04/lab04part03.v:10: Cannot find file containing module: \'hexDecoder7Seg\'\n hexDecoder7Seg h2(HEX2[6:0], LEDR[11:8]);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193790231/lab04/lab04part03.v:11: Cannot find file containing module: \'hexDecoder7Seg\'\n hexDecoder7Seg h1(HEX1[6:0], LEDR[7:4]);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193790231/lab04/lab04part03.v:12: Cannot find file containing module: \'hexDecoder7Seg\'\n hexDecoder7Seg h0(HEX0[6:0], LEDR[3:0]);\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lab04part03(
	output [15:0]LEDR,
	output [6:0]HEX3, HEX2, HEX1, HEX0,
	input  [1:0]SW,
	input  [1:1]KEY
);

	count1 lpmcount(KEY[1], SW[0], SW[1], LEDR[15:0]);
	hexDecoder7Seg h3(HEX3[6:0], LEDR[15:12]);
	hexDecoder7Seg h2(HEX2[6:0], LEDR[11:8]);
	hexDecoder7Seg h1(HEX1[6:0], LEDR[7:4]);
	hexDecoder7Seg h0(HEX0[6:0], LEDR[3:0]);
endmodule
module lab04part03(
	output [15:0]LEDR,
	output [6:0]HEX3, HEX2, HEX1, HEX0,
	input  [1:0]SW,
	input  [1:1]KEY
);


	count1 lpmcount(KEY[1], SW[0], SW[1], LEDR[15:0]);
	hexDecoder7Seg h3(HEX3[6:0], LEDR[15:12]);
	hexDecoder7Seg h2(HEX2[6:0], LEDR[11:8]);
	hexDecoder7Seg h1(HEX1[6:0], LEDR[7:4]);
	hexDecoder7Seg h0(HEX0[6:0], LEDR[3:0]);
endmodule