data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v
 line:61: before: "localparam"
1: b'%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:1: Cannot find include file: anton_common.vh\n`include "anton_common.vh" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143344034/hdl,data/full_repos/permissive/143344034/anton_common.vh\n             data/full_repos/permissive/143344034/hdl,data/full_repos/permissive/143344034/anton_common.vh.v\n             data/full_repos/permissive/143344034/hdl,data/full_repos/permissive/143344034/anton_common.vh.sv\n             anton_common.vh\n             anton_common.vh.v\n             anton_common.vh.sv\n             obj_dir/anton_common.vh\n             obj_dir/anton_common.vh.v\n             obj_dir/anton_common.vh.sv\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:4: Define or directive not defined: \'`BUFFER_END_DEFAULT\'\n  parameter  BUFFER_END  = `BUFFER_END_DEFAULT,   \n                           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:4: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  parameter  BUFFER_END  = `BUFFER_END_DEFAULT,   \n                                              ^\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:5: Define or directive not defined: \'`RESET_DELAY_DEFAULT\'\n  parameter  RESET_DELAY = `RESET_DELAY_DEFAULT,  \n                           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:5: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  parameter  RESET_DELAY = `RESET_DELAY_DEFAULT,  \n                                               ^\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:6: Define or directive not defined: \'`CLOG2\'\n  localparam BUFFER_BITS = `CLOG2(BUFFER_END+1)   \n                           ^~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:7: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:53: syntax error, unexpected assign\n  assign pixelIxComb     = (regCtrl32bit) ? {pixelIxB[BUFFER_BITS-1:2], channelIxRemapped} : pixelIxB[BUFFER_BITS-1:0];  \n  ^~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:55: Define or directive not defined: \'`ENUM_STATE_TRANSMIT\'\n  assign streamOutput    = !regCtrlInit    && regCtrlRun && stateB == `ENUM_STATE_TRANSMIT; \n                                                                      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:56: Define or directive not defined: \'`ENUM_STATE_RESET\'\n  assign streamReset     = !regCtrlInit    && regCtrlRun && stateB == `ENUM_STATE_RESET;\n                                                                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:59: syntax error, unexpected assign\n  assign streamBitOf     = streamPatternOf && pixelBitIxB   == \'d7;    \n  ^~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:62: syntax error, unexpected assign\n  assign streamPixelOf   = streamChannelOf && streamPixelLast;         \n  ^~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:121: Define or directive not defined: \'`ENUM_STATE_RESET\'\n    if (streamPixelOf) stateB <= `ENUM_STATE_RESET;\n                                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_stream_logic.v:131: Define or directive not defined: \'`ENUM_STATE_TRANSMIT\'\n      stateB          <= `ENUM_STATE_TRANSMIT;\n                         ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module anton_neopixel_stream_logic #(
  parameter  BUFFER_END  = `BUFFER_END_DEFAULT,
  parameter  RESET_DELAY = `RESET_DELAY_DEFAULT,
  localparam BUFFER_BITS = `CLOG2(BUFFER_END+1)
)(
  input                    clk6_4mhz,
  input                    regCtrlInit,
  input                    regCtrlRun,
  input                    regCtrlLoop,
  input                    regCtrlLimit,
  input                    regCtrl32bit,
  input                    [12:0] regMax,
  
  input                    initSlow,
  output                   initSlowDone,

  output [2:0]             bitPatternIx,
  output [2:0]             pixelBitIx,
  output [1:0]             channelIx,
  output [BUFFER_BITS-1:0] pixelIxMax,
  output [BUFFER_BITS-1:0] pixelIxComb,
  
  output                   state,
  output                   streamOutput,
  output                   streamReset,
  output                   streamBitOf,
  output                   streamChannelOf,
  output                   streamPixelOf,
  output                   streamSyncOf
);

  reg [2:0]             bitPatternIxB     = 'd0;
  reg [2:0]             pixelBitIxB       = 'd0;
  reg [BUFFER_BITS-1:0] pixelIxB          = {BUFFER_BITS{1'b0}};
  reg [11:0]            resetDelayCount   = 'd0;
  reg [1:0]             channelIxB        = 'd0;
  reg [1:0]             channelIxRemapped = 'd0;

  reg                   stateB            = 'b0;
  reg [3:0]             cycle             = 'd0;  

  reg                   initSlowDoneB     = 'b0;
  



  wire [BUFFER_BITS-1:0] pixelIxEquiv    = (regCtrl32bit) ? {pixelIxB[BUFFER_BITS-1:2], 2'b11} : pixelIxB;
  wire [BUFFER_BITS-1:0] pixelIxMaxEquiv = (regCtrl32bit) ? {pixelIxMax[BUFFER_BITS-1:2], 2'b00} : pixelIxMax;
  wire [BUFFER_BITS-3:0] pixelIxPartial  = pixelIxB[BUFFER_BITS-1:2] + 1;
  
  assign pixelIxComb     = (regCtrl32bit) ? {pixelIxB[BUFFER_BITS-1:2], channelIxRemapped} : pixelIxB[BUFFER_BITS-1:0];

  assign streamOutput    = !regCtrlInit    && regCtrlRun && stateB == `ENUM_STATE_TRANSMIT; 
  assign streamReset     = !regCtrlInit    && regCtrlRun && stateB == `ENUM_STATE_RESET;

  wire   streamPatternOf = streamOutput    && bitPatternIxB == 'd7;
  assign streamBitOf     = streamPatternOf && pixelBitIxB   == 'd7;
  assign streamChannelOf = streamBitOf     && channelIxB    == 'd2;
  wire   streamPixelLast = pixelIxEquiv    >= pixelIxMaxEquiv;
  assign streamPixelOf   = streamChannelOf && streamPixelLast;

  always @(posedge clk6_4mhz) if (streamOutput) bitPatternIxB <= bitPatternIxB + 1;



  assign pixelIxMax = (regCtrlLimit) ? regMax[BUFFER_BITS-1:0] : BUFFER_END[BUFFER_BITS-1:0];



  always @(*) begin
    case (channelIxB)
      default: channelIxRemapped = 'd1;
      'd1:     channelIxRemapped = 'd0; 
      'd2:     channelIxRemapped = 'd2; 
    endcase
  end

  always @(posedge clk6_4mhz) begin 


    if (streamPatternOf) pixelBitIxB <= (streamBitOf) ? 0 : pixelBitIxB +1;

    if (initSlow) begin
      pixelIxB    <= {BUFFER_BITS{1'b0}};
      pixelBitIxB <= 'd0;  
      initSlowDoneB  <= 'b1;
    end

    if (initSlowDoneB) begin
      initSlowDoneB  <= 'b0;
    end

    if (streamBitOf) begin

      channelIxB <= (streamChannelOf) ? 'd0 : channelIxB + 'd1;
    end

    if (streamChannelOf) begin



        if (streamPixelLast)  begin

          pixelIxB <= 'd0;
        end else begin


          pixelIxB <= (regCtrl32bit) ? {pixelIxPartial, 2'b00} : pixelIxB + 'd1;
        end
    end
  end


  assign streamSyncOf = (resetDelayCount == RESET_DELAY);


  always @(posedge clk6_4mhz) begin

    if (streamPixelOf) stateB <= `ENUM_STATE_RESET;

    if (streamReset) begin

      resetDelayCount <= resetDelayCount + 'b1;
    end

    if (streamSyncOf) begin  

      if (cycle == 'd5) $finish;
      stateB          <= `ENUM_STATE_TRANSMIT;
      cycle           <= cycle + 'd1;
      resetDelayCount <= 'd0;
    end
  end


  assign bitPatternIx = bitPatternIxB;
  assign pixelBitIx   = pixelBitIxB;
  assign channelIx    = channelIxB;
  assign state        = stateB;
  assign initSlowDone = initSlowDoneB;

endmodule
module anton_neopixel_stream_logic #(
  parameter  BUFFER_END  = `BUFFER_END_DEFAULT,
  parameter  RESET_DELAY = `RESET_DELAY_DEFAULT,
  localparam BUFFER_BITS = `CLOG2(BUFFER_END+1)
)(
  input                    clk6_4mhz,
  input                    regCtrlInit,
  input                    regCtrlRun,
  input                    regCtrlLoop,
  input                    regCtrlLimit,
  input                    regCtrl32bit,
  input                    [12:0] regMax,
  
  input                    initSlow,
  output                   initSlowDone,

  output [2:0]             bitPatternIx,
  output [2:0]             pixelBitIx,
  output [1:0]             channelIx,
  output [BUFFER_BITS-1:0] pixelIxMax,
  output [BUFFER_BITS-1:0] pixelIxComb,
  
  output                   state,
  output                   streamOutput,
  output                   streamReset,
  output                   streamBitOf,
  output                   streamChannelOf,
  output                   streamPixelOf,
  output                   streamSyncOf
);


  reg [2:0]             bitPatternIxB     = 'd0;
  reg [2:0]             pixelBitIxB       = 'd0;
  reg [BUFFER_BITS-1:0] pixelIxB          = {BUFFER_BITS{1'b0}};
  reg [11:0]            resetDelayCount   = 'd0;
  reg [1:0]             channelIxB        = 'd0;
  reg [1:0]             channelIxRemapped = 'd0;

  reg                   stateB            = 'b0;
  reg [3:0]             cycle             = 'd0;  

  reg                   initSlowDoneB     = 'b0;
  



  wire [BUFFER_BITS-1:0] pixelIxEquiv    = (regCtrl32bit) ? {pixelIxB[BUFFER_BITS-1:2], 2'b11} : pixelIxB;
  wire [BUFFER_BITS-1:0] pixelIxMaxEquiv = (regCtrl32bit) ? {pixelIxMax[BUFFER_BITS-1:2], 2'b00} : pixelIxMax;
  wire [BUFFER_BITS-3:0] pixelIxPartial  = pixelIxB[BUFFER_BITS-1:2] + 1;
  
  assign pixelIxComb     = (regCtrl32bit) ? {pixelIxB[BUFFER_BITS-1:2], channelIxRemapped} : pixelIxB[BUFFER_BITS-1:0];

  assign streamOutput    = !regCtrlInit    && regCtrlRun && stateB == `ENUM_STATE_TRANSMIT; 
  assign streamReset     = !regCtrlInit    && regCtrlRun && stateB == `ENUM_STATE_RESET;

  wire   streamPatternOf = streamOutput    && bitPatternIxB == 'd7;
  assign streamBitOf     = streamPatternOf && pixelBitIxB   == 'd7;
  assign streamChannelOf = streamBitOf     && channelIxB    == 'd2;
  wire   streamPixelLast = pixelIxEquiv    >= pixelIxMaxEquiv;
  assign streamPixelOf   = streamChannelOf && streamPixelLast;

  always @(posedge clk6_4mhz) if (streamOutput) bitPatternIxB <= bitPatternIxB + 1;



  assign pixelIxMax = (regCtrlLimit) ? regMax[BUFFER_BITS-1:0] : BUFFER_END[BUFFER_BITS-1:0];



  always @(*) begin
    case (channelIxB)
      default: channelIxRemapped = 'd1;
      'd1:     channelIxRemapped = 'd0; 
      'd2:     channelIxRemapped = 'd2; 
    endcase
  end

  always @(posedge clk6_4mhz) begin 


    if (streamPatternOf) pixelBitIxB <= (streamBitOf) ? 0 : pixelBitIxB +1;

    if (initSlow) begin
      pixelIxB    <= {BUFFER_BITS{1'b0}};
      pixelBitIxB <= 'd0;  
      initSlowDoneB  <= 'b1;
    end

    if (initSlowDoneB) begin
      initSlowDoneB  <= 'b0;
    end

    if (streamBitOf) begin

      channelIxB <= (streamChannelOf) ? 'd0 : channelIxB + 'd1;
    end

    if (streamChannelOf) begin



        if (streamPixelLast)  begin

          pixelIxB <= 'd0;
        end else begin


          pixelIxB <= (regCtrl32bit) ? {pixelIxPartial, 2'b00} : pixelIxB + 'd1;
        end
    end
  end


  assign streamSyncOf = (resetDelayCount == RESET_DELAY);


  always @(posedge clk6_4mhz) begin

    if (streamPixelOf) stateB <= `ENUM_STATE_RESET;

    if (streamReset) begin

      resetDelayCount <= resetDelayCount + 'b1;
    end

    if (streamSyncOf) begin  

      if (cycle == 'd5) $finish;
      stateB          <= `ENUM_STATE_TRANSMIT;
      cycle           <= cycle + 'd1;
      resetDelayCount <= 'd0;
    end
  end


  assign bitPatternIx = bitPatternIxB;
  assign pixelBitIx   = pixelBitIxB;
  assign channelIx    = channelIxB;
  assign state        = stateB;
  assign initSlowDone = initSlowDoneB;

endmodule