data/full_repos/permissive/143278/ivltests/hierspace.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/hierspace.v:32: Unsupported: Ignoring delay on this delayed statement.\n #1 inst.x   <= 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/hierspace.v:33: Unsupported: Ignoring delay on this delayed statement.\n #1 inst .x  <= 1\'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/hierspace.v:34: Unsupported: Ignoring delay on this delayed statement.\n #1 inst. x  <= 1\'bz;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/hierspace.v:35: Unsupported: Ignoring delay on this delayed statement.\n #1 inst . x <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/hierspace.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module m (x);
   output x;
   reg	  x;
endmodule
module m (x);

   output x;
   reg	  x;
endmodule