data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4_control.v
 line:181: before: "("
1: b'%Error: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4_control.v:127: Cannot find file containing module: \'jelly_pipeline_insert_ff\'\n    jelly_pipeline_insert_ff\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/video,data/full_repos/permissive/2084115/jelly_pipeline_insert_ff\n             data/full_repos/permissive/2084115/rtl/video,data/full_repos/permissive/2084115/jelly_pipeline_insert_ff.v\n             data/full_repos/permissive/2084115/rtl/video,data/full_repos/permissive/2084115/jelly_pipeline_insert_ff.sv\n             jelly_pipeline_insert_ff\n             jelly_pipeline_insert_ff.v\n             jelly_pipeline_insert_ff.sv\n             obj_dir/jelly_pipeline_insert_ff\n             obj_dir/jelly_pipeline_insert_ff.v\n             obj_dir/jelly_pipeline_insert_ff.sv\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4_control.v:196: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'pixels\' generates 24 bits.\n                                                                                                   : ... In instance jelly_vdma_axi4s_to_axi4_control\n        pixels_to_byte = pixels << PIXEL_SIZE;\n                                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4_control.v:259: Operator FUNCREF \'pixels_to_count\' expects 24 bits on the Function Argument, but Function Argument\'s VARREF \'param_width\' generates 12 bits.\n                                                                                                   : ... In instance jelly_vdma_axi4s_to_axi4_control\n                        reg_awhcount <= pixels_to_count(param_width);\n                                        ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4_control.v:261: Operator FUNCREF \'pixels_to_byte\' expects 24 bits on the Function Argument, but Function Argument\'s VARREF \'param_width\' generates 12 bits.\n                                                                                                   : ... In instance jelly_vdma_axi4s_to_axi4_control\n                        if ( (param_size != 0) && pixels_to_byte(param_width) == param_stride ) begin\n                                                  ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4_control.v:261: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'param_stride\' generates 14 bits.\n                                                                                                   : ... In instance jelly_vdma_axi4s_to_axi4_control\n                        if ( (param_size != 0) && pixels_to_byte(param_width) == param_stride ) begin\n                                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4_control.v:268: Operator FUNCREF \'pixels_to_count\' expects 24 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_width\' generates 12 bits.\n                                                                                                   : ... In instance jelly_vdma_axi4s_to_axi4_control\n                        reg_awhcount <= pixels_to_count(reg_param_width);\n                                        ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4_control.v:270: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'reg_param_width\' generates 12 bits.\n                                                                                                   : ... In instance jelly_vdma_axi4s_to_axi4_control\n                        if ( (reg_param_size != 0) && (reg_param_width << AXI4_DATA_SIZE) == reg_param_stride ) begin\n                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4_control.v:295: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'reg_param_stride\' generates 14 bits.\n                                                                                                   : ... In instance jelly_vdma_axi4s_to_axi4_control\n                        reg_awaddr   <= reg_awaddr + reg_param_stride;\n                                                   ^\n%Error: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4s_to_axi4_control.v:328: Cannot find file containing module: \'jelly_axi4_dma_writer\'\n    jelly_axi4_dma_writer\n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n'
function    [AXI4_ADDR_WIDTH-1:0]   pixels_to_byte(input [SIZE_WIDTH-1:0] pixels);
    begin
        pixels_to_byte = pixels << PIXEL_SIZE;
    end
    endfunction
function    [AXI4_ADDR_WIDTH-1:0]   pixels_to_byte(input [SIZE_WIDTH-1:0] pixels);

    begin
        pixels_to_byte = pixels << PIXEL_SIZE;
    end
    endfunction