data/full_repos/permissive/167580717/src/display/VideoController.sv
 line:64: before: "typedef"
1: b'%Error: data/full_repos/permissive/167580717/src/display/VideoController.sv:1: Cannot find include file: DataType.svh\n`include "DataType.svh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167580717/src/display,data/full_repos/permissive/167580717/DataType.svh\n             data/full_repos/permissive/167580717/src/display,data/full_repos/permissive/167580717/DataType.svh.v\n             data/full_repos/permissive/167580717/src/display,data/full_repos/permissive/167580717/DataType.svh.sv\n             DataType.svh\n             DataType.svh.v\n             DataType.svh.sv\n             obj_dir/DataType.svh\n             obj_dir/DataType.svh.v\n             obj_dir/DataType.svh.sv\n%Error: data/full_repos/permissive/167580717/src/display/VideoController.sv:21: Define or directive not defined: \'`BAUD_RATE\'\n        .Baud(`BAUD_RATE)\n              ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module VideoController(
	 input                               clk200M,
    input                               clk100M,
    input                               clk50M,
	 input                               clk25M,
    input                               rst,
    input                               uartRx,
    output  VgaSignal_t                 vga,

    output  logic[70:0]                 debug,
	 input										cur_sw
    );


    logic         uartReady;
    logic [7:0]   uartDataReceived;

    AsyncUartReceiver #(
        .ClkFrequency(100_000_000),
        .Baud(`BAUD_RATE)
    ) 
	 uartReceiver(
        .clk(clk100M),
        .RxD(uartRx),
        .RxD_data_ready(uartReady),
        .RxD_data(uartDataReceived)
    );



    logic blinkStatus;

    BlinkGenerator #(
        .ClkFrequency(100_000_000)
    ) blink(
        .clk(clk100M),
		.sync_reset(1'b0),
        .status(blinkStatus)
    );



    logic [70:0] vt100_debug;
    assign debug = vt100_debug;
    Cursor_t cursor;

	VT100Parser vt100Parser(
        .clk(clk100M),
        .rst,
        .dataReady(uartReady),
        .data(uartDataReceived),
        .ramRes(textRamResultParser),
        .ramReq(textRamRequestParser),
        .debug(vt100_debug),
        .cursorInfo(cursor)
    );



    TextRamRequest_t textRamRequestParser, textRamRequestRenderer;
    TextRamResult_t textRamResultParser, textRamResultRenderer;

    TextRam textRam(
        .aclr_a(rst),
        .aclr_b(rst),
        .address_a(textRamRequestParser.address),
        .address_b(textRamRequestRenderer.address),
        .clock_a(clk100M),
        .clock_b(clk100M),
        .data_a(textRamRequestParser.data),
        .data_b(textRamRequestRenderer.data),
        .wren_a(textRamRequestParser.wren),
        .wren_b(textRamRequestRenderer.wren),
        .q_a(textRamResultParser),
        .q_b(textRamResultRenderer)
    );
	 
	 wire [8:0] vid_dati,vid_dato;
	 wire [18:0] vid_addr_o,vid_addr_i;
	 wire vid_wr;
	 
	 
	 VideoRam VideoRam(
		.clock(clk100M),
		.data(vid_dati),
		.rdaddress(vid_addr_o),
		.wraddress(vid_addr_i),
		.wren(vid_wr),
		.q(vid_dato)
	 );


    DisplayController controller(
        .clk(clk25M),
		  .fclk(clk100M),
        .rst,
        .blinkStatus,
        .cursor,
        .textRamResult(textRamResultRenderer),
        .textRamRequest(textRamRequestRenderer),
        .vid_dati,
        .vid_addr_o,
		  .vid_addr_i,
		  .vid_wr,
		  .vid_dato,
        .vga,
		  .cur_sw
    );

endmodule
module VideoController(
	 input                               clk200M,
    input                               clk100M,
    input                               clk50M,
	 input                               clk25M,
    input                               rst,
    input                               uartRx,
    output  VgaSignal_t                 vga,

    output  logic[70:0]                 debug,
	 input										cur_sw
    );



    logic         uartReady;
    logic [7:0]   uartDataReceived;

    AsyncUartReceiver #(
        .ClkFrequency(100_000_000),
        .Baud(`BAUD_RATE)
    ) 
	 uartReceiver(
        .clk(clk100M),
        .RxD(uartRx),
        .RxD_data_ready(uartReady),
        .RxD_data(uartDataReceived)
    );



    logic blinkStatus;

    BlinkGenerator #(
        .ClkFrequency(100_000_000)
    ) blink(
        .clk(clk100M),
		.sync_reset(1'b0),
        .status(blinkStatus)
    );



    logic [70:0] vt100_debug;
    assign debug = vt100_debug;
    Cursor_t cursor;

	VT100Parser vt100Parser(
        .clk(clk100M),
        .rst,
        .dataReady(uartReady),
        .data(uartDataReceived),
        .ramRes(textRamResultParser),
        .ramReq(textRamRequestParser),
        .debug(vt100_debug),
        .cursorInfo(cursor)
    );



    TextRamRequest_t textRamRequestParser, textRamRequestRenderer;
    TextRamResult_t textRamResultParser, textRamResultRenderer;

    TextRam textRam(
        .aclr_a(rst),
        .aclr_b(rst),
        .address_a(textRamRequestParser.address),
        .address_b(textRamRequestRenderer.address),
        .clock_a(clk100M),
        .clock_b(clk100M),
        .data_a(textRamRequestParser.data),
        .data_b(textRamRequestRenderer.data),
        .wren_a(textRamRequestParser.wren),
        .wren_b(textRamRequestRenderer.wren),
        .q_a(textRamResultParser),
        .q_b(textRamResultRenderer)
    );
	 
	 wire [8:0] vid_dati,vid_dato;
	 wire [18:0] vid_addr_o,vid_addr_i;
	 wire vid_wr;
	 
	 
	 VideoRam VideoRam(
		.clock(clk100M),
		.data(vid_dati),
		.rdaddress(vid_addr_o),
		.wraddress(vid_addr_i),
		.wren(vid_wr),
		.q(vid_dato)
	 );


    DisplayController controller(
        .clk(clk25M),
		  .fclk(clk100M),
        .rst,
        .blinkStatus,
        .cursor,
        .textRamResult(textRamResultRenderer),
        .textRamRequest(textRamRequestRenderer),
        .vid_dati,
        .vid_addr_o,
		  .vid_addr_i,
		  .vid_wr,
		  .vid_dato,
        .vga,
		  .cur_sw
    );

endmodule