data/full_repos/permissive/200314387/verilog/rom/test.v
 line:62: before: "if"
1: b'%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:5: Cannot find include file: rom.v\n`include "rom.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/rom,data/full_repos/permissive/200314387/rom.v\n             data/full_repos/permissive/200314387/verilog/rom,data/full_repos/permissive/200314387/rom.v.v\n             data/full_repos/permissive/200314387/verilog/rom,data/full_repos/permissive/200314387/rom.v.sv\n             rom.v\n             rom.v.v\n             rom.v.sv\n             obj_dir/rom.v\n             obj_dir/rom.v.v\n             obj_dir/rom.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:6: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:28: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'bzzzzzzzz);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:28: syntax error, unexpected \',\'\n    `Equals(D, 8\'bzzzzzzzz);\n             ^\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:36: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'b00000010);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:36: syntax error, unexpected \',\'\n    `Equals(D, 8\'b00000010);\n             ^\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:43: Define or directive not defined: \'`Equals\'\n     `Equals(D, 8\'b00001111);\n     ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:43: syntax error, unexpected \',\'\n     `Equals(D, 8\'b00001111);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:49: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'b00001111);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:49: syntax error, unexpected \',\'\n    `Equals(D, 8\'b00001111);\n             ^\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:55: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'b00001111);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:55: syntax error, unexpected \',\'\n    `Equals(D, 8\'b00001111);\n             ^\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:61: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'b00000001);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:61: syntax error, unexpected \',\'\n    `Equals(D, 8\'b00000001);\n             ^\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:65: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'b00000011);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:65: syntax error, unexpected \',\'\n    `Equals(D, 8\'b00000011);\n             ^\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:71: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'b00000010);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/rom/test.v:71: syntax error, unexpected \',\'\n    `Equals(D, 8\'b00000010);\n             ^\n%Error: Exiting due to 18 error(s)\n'
module test();

 logic _OE, _CS;
 logic [3:0] A;
 wire [7:0] D;
 
  rom #(.DEPTH(16), .AWIDTH(4), .FILENAME("data.rom")) r1(._CS(_CS), ._OE(_OE), .A(A), .D(D));

    always @* 
        $display($time, " A=%d, D=%d", A, D);

 integer count = 1000;

 initial begin
    _OE=1'b1;
    _CS=1'b0;
    #200
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - output disabled",_OE, _CS, A, D);
    `Equals(D, 8'bzzzzzzzz);


    A=4'b0010;
    _OE=1'b0;
    _CS=1'b0;
    #200
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - setup write 2 @ 2",_OE, _CS, A, D);
    `Equals(D, 8'b00000010);
 
    A=4'b1111;
    _OE=1'b0;
    _CS=1'b0;
    #200
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - setup write 2 @ 2",_OE, _CS, A, D);
     `Equals(D, 8'b00001111);
 
    $display($time, " tweak A1");
    A=1;
    #(r1.tACC/2)
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - A=1 but not prop yet ",_OE, _CS, A, D);
    `Equals(D, 8'b00001111);

    $display($time, " tweak A2");
    A=2;
    #(r1.tACC/2)
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - A=2 but not prop yet - resets inertial timer",_OE, _CS, A, D);
    `Equals(D, 8'b00001111);

    $display($time, " tweak A3");
    A=3;
    #(r1.tACC/2)
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - A=3 but not prop yet - resets inertial timer",_OE, _CS, A, D);
    `Equals(D, 8'b00000001);

    #(r1.tACC/2+1)
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - A=£ propagated",_OE, _CS, A, D);
    `Equals(D, 8'b00000011);

    $display($time, " tweak A3");
    A=2;
    #(r1.tACC+1)
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - setup write 2 @ 2",_OE, _CS, A, D);
    `Equals(D, 8'b00000010);

 
 end

endmodule
module test();


 logic _OE, _CS;
 logic [3:0] A;
 wire [7:0] D;
 
  rom #(.DEPTH(16), .AWIDTH(4), .FILENAME("data.rom")) r1(._CS(_CS), ._OE(_OE), .A(A), .D(D));

    always @* 
        $display($time, " A=%d, D=%d", A, D);

 integer count = 1000;

 initial begin
    _OE=1'b1;
    _CS=1'b0;
    #200
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - output disabled",_OE, _CS, A, D);
    `Equals(D, 8'bzzzzzzzz);


    A=4'b0010;
    _OE=1'b0;
    _CS=1'b0;
    #200
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - setup write 2 @ 2",_OE, _CS, A, D);
    `Equals(D, 8'b00000010);
 
    A=4'b1111;
    _OE=1'b0;
    _CS=1'b0;
    #200
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - setup write 2 @ 2",_OE, _CS, A, D);
     `Equals(D, 8'b00001111);
 
    $display($time, " tweak A1");
    A=1;
    #(r1.tACC/2)
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - A=1 but not prop yet ",_OE, _CS, A, D);
    `Equals(D, 8'b00001111);

    $display($time, " tweak A2");
    A=2;
    #(r1.tACC/2)
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - A=2 but not prop yet - resets inertial timer",_OE, _CS, A, D);
    `Equals(D, 8'b00001111);

    $display($time, " tweak A3");
    A=3;
    #(r1.tACC/2)
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - A=3 but not prop yet - resets inertial timer",_OE, _CS, A, D);
    `Equals(D, 8'b00000001);

    #(r1.tACC/2+1)
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - A=£ propagated",_OE, _CS, A, D);
    `Equals(D, 8'b00000011);

    $display($time, " tweak A3");
    A=2;
    #(r1.tACC+1)
    $display($time, " TEST: _OE=%1b, _CS=%1b, A=%8b, d=%8b - setup write 2 @ 2",_OE, _CS, A, D);
    `Equals(D, 8'b00000010);

 
 end

endmodule