data/full_repos/permissive/155713836/tb/tb_chiplet_sys.sv
 line:48: before: "="
1: b'%Warning-STMTDLY: data/full_repos/permissive/155713836/tb/tb_chiplet_sys.sv:152: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = !clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/155713836/tb/tb_chiplet_sys.sv:271: Unsupported: Ignoring delay on this delayed statement.\n    #1000 $finish;\n    ^\n%Error: data/full_repos/permissive/155713836/tb/tb_chiplet_sys.sv:264: Can\'t find definition of \'w_m_tx_fsm_packet_valid\' in dotted variable: \'chipletsys.w_m_tx_fsm_packet_valid\'\n    if (chipletsys.w_m_tx_fsm_packet_valid == 1\'b1) begin\n                   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/155713836/tb/tb_chiplet_sys.sv:266: Can\'t find definition of \'w_m_tx_fsm_packet\' in dotted variable: \'chipletsys.w_m_tx_fsm_packet\'\n        $fwrite(g, "%d, %h\\n", $time, chipletsys.w_m_tx_fsm_packet);\n                                                 ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_chiplet_sys ();


  parameter FIFO_DEPTH = 32;
  parameter LOG2_FIFO_DEPTH = 5;
  parameter DATA_LINE_WIDTH = 40;
  parameter CONTROL_LINE_WIDTH = 0;
  parameter WORD_SIZE = 32;

  reg clk = 0;

  reg [WORD_SIZE-1:0] o_slave_rx_data;
  reg o_slave_rx_data_valid;
  reg [WORD_SIZE-1:0] o_slave_rx_addr;
  reg o_slave_rx_addr_valid;  
  reg [2:0] o_slave_rx_cmd;
  reg o_slave_rx_cmd_valid;
  reg [5:0] o_slave_rx_feature0; 
  reg o_slave_rx_feature0_valid;
  reg [5:0] o_slave_rx_feature1; 
  reg o_slave_rx_feature1_valid;
  reg [2:0] o_slave_rx_length; 
  reg o_slave_rx_length_valid;

  reg [5:0] stream_counter = 0;
  reg [1075:0] i_stream_2_fsm;
  reg i_stream_2_fsm_valid;
  reg o_m_tx_fsm_ready;

  reg w_master_tx_packetstream_valid;

  integer i;








  reg [0:0] mode_bank [0:5] = {
    1'b0,
    1'b1,
    1'b0,
    1'b1,
    1'b0,
    1'b1};

  reg [0:0] valid_bank [0:5] = {
    1'b1,
    1'b1,
    1'b1,
    1'b1,
    1'b1,
    1'b1};





  reg [2:0] cmd_bank [0:5] = {
    3'b001,
    3'b001,
    3'b000,
    3'b000,
    3'b010,
    3'b010};







  reg [2:0] length_bank [0:5] = {
    3'b001,
    3'b010,
    3'b001,
    3'b010,
    3'b001,
    3'b010};

  reg [31:0] address_bank [0:5] = {
    32'hFFDD0000,
    32'h00000888,
    32'hAABB0000,
    32'h00000AAA,
    32'hFFDD0000,
    32'h00000888};

  reg [1023:0] data_bank [0:5] = {
    1023'h000000BB000000AA,
    1023'h00003666000024440000567800001234,
    1023'h0,
    1023'h0,
    1023'h000000BB000000AA,
    1023'h00003666000024440000567800001234};

  reg [5:0] feature0_bank [0:5] = {
    6'b000000,
    6'b000001,
    6'b000000,
    6'b000010,
    6'b000000,
    6'b000011};

  reg [5:0] feature1_bank [0:5] = {
    6'b000000,
    6'b111111,
    6'b000000,
    6'b000111,
    6'b000000,
    6'b111000};






  initial begin
    clk = 0;
  end  


  always #1 clk = !clk;

  always @ (posedge clk) begin

    if (o_m_tx_fsm_ready == 1'b1) begin
      stream_counter = stream_counter + 1'b1;
      i_stream_2_fsm_valid = 1'b1;
    end else begin
      stream_counter = stream_counter;
      i_stream_2_fsm_valid = 1'b0;
    end

    if ( (stream_counter < 5) || (stream_counter > 10) ) begin
      i_stream_2_fsm = 'b0;
    end else begin

      i_stream_2_fsm = {  feature1_bank[stream_counter-5],
			feature0_bank[stream_counter-5], 					
			data_bank[stream_counter-5],
			address_bank[stream_counter-5],
			length_bank[stream_counter-5],
			cmd_bank[stream_counter-5],
			valid_bank[stream_counter-5],
			mode_bank[stream_counter-5]};
     end

  end



  chiplet_sys chipletsys(

    .clk(clk),

    .i_master_tx_packetstream(i_stream_2_fsm),
    .i_master_tx_packetstream_valid(i_stream_2_fsm_valid),
    .o_master_tx_fsm_ready(o_m_tx_fsm_ready),

    .i_slave_tx_packetstream(),
    .i_slave_tx_packetstream_wen(),
    .o_slave_tx_fsm_ready(),

    .i_slave_rx_ready(1'b1),
    .i_master_rx_ready(1'b1),

    .o_slave_rx_data(o_slave_rx_data),
    .o_slave_rx_data_valid(o_slave_rx_data_valid), 
    .o_slave_rx_addr(o_slave_rx_addr), 
    .o_slave_rx_addr_valid(o_slave_rx_addr_valid), 
    .o_slave_rx_cmd(o_slave_rx_cmd),
    .o_slave_rx_cmd_valid(o_slave_rx_cmd_valid),
    .o_slave_rx_feature0(o_slave_rx_feature0),
    .o_slave_rx_feature0_valid(o_slave_rx_feature0_valid),
    .o_slave_rx_feature1(o_slave_rx_feature1),
    .o_slave_rx_feature1_valid(o_slave_rx_feature1_valid),
    .o_slave_rx_length(o_slave_rx_length),
    .o_slave_rx_length_valid(o_slave_rx_length_valid),

    .o_master_rx_data(),
    .o_master_rx_data_valid(),
    .o_master_rx_addr(),
    .o_master_rx_addr_valid(),
    .o_master_rx_cmd(),
    .o_master_rx_cmd_valid(),
    .o_master_rx_feature0(),
    .o_master_rx_feature0_valid(),
    .o_master_rx_length(),
    .o_master_rx_length_valid()
  );   




  integer f;
  initial begin
    f = $fopen("output_dump.txt","w");
    $fwrite(f, "\n------------------------------------------\n");
    $fwrite(f, "Field - Timestamp - Value ");
    $fwrite(f, "\n------------------------------------------\n");
  end

  always @ (posedge clk) begin
    if (o_slave_rx_cmd_valid == 1'b1) begin
        $fwrite(f, "------------------------------------------ \n");
        $fwrite(f, "CMD value %d, %h\n",$time, o_slave_rx_cmd);
    end
    if (o_slave_rx_addr_valid == 1'b1) begin
        $fwrite(f, "Addr value %d, %h\n",$time, o_slave_rx_addr);
    end
    if (o_slave_rx_data_valid == 1'b1) begin
        $fwrite(f, "Data value %d, %h\n",$time, o_slave_rx_data);
    end
    if (o_slave_rx_feature0_valid == 1'b1) begin
        $fwrite(f, "feature0 value %d, %h\n",$time, o_slave_rx_feature0);
    end
    if (o_slave_rx_feature1_valid == 1'b1) begin
        $fwrite(f, "feature1 value %d, %h\n",$time, o_slave_rx_feature1);
    end
    if (o_slave_rx_length_valid == 1'b1) begin
        $fwrite(f, "Length value %d, %h\n",$time, o_slave_rx_length);
    end
  end

  integer g;
  initial begin
    g = $fopen("input_dump.txt","w");
    $fwrite(g, "\n------------------------------------------\n");
    $fwrite(g, "Timestamp - Generated Flit ");
    $fwrite(g, "\n------------------------------------------\n");
  end

  always @ (posedge clk) begin
    if (chipletsys.w_m_tx_fsm_packet_valid == 1'b1) begin
        $fwrite(g, "------------------------------------------ \n");
        $fwrite(g, "%d, %h\n", $time, chipletsys.w_m_tx_fsm_packet);
    end
  end

  initial begin
    #1000 $finish;
  end


endmodule
module tb_chiplet_sys ();



  parameter FIFO_DEPTH = 32;
  parameter LOG2_FIFO_DEPTH = 5;
  parameter DATA_LINE_WIDTH = 40;
  parameter CONTROL_LINE_WIDTH = 0;
  parameter WORD_SIZE = 32;

  reg clk = 0;

  reg [WORD_SIZE-1:0] o_slave_rx_data;
  reg o_slave_rx_data_valid;
  reg [WORD_SIZE-1:0] o_slave_rx_addr;
  reg o_slave_rx_addr_valid;  
  reg [2:0] o_slave_rx_cmd;
  reg o_slave_rx_cmd_valid;
  reg [5:0] o_slave_rx_feature0; 
  reg o_slave_rx_feature0_valid;
  reg [5:0] o_slave_rx_feature1; 
  reg o_slave_rx_feature1_valid;
  reg [2:0] o_slave_rx_length; 
  reg o_slave_rx_length_valid;

  reg [5:0] stream_counter = 0;
  reg [1075:0] i_stream_2_fsm;
  reg i_stream_2_fsm_valid;
  reg o_m_tx_fsm_ready;

  reg w_master_tx_packetstream_valid;

  integer i;








  reg [0:0] mode_bank [0:5] = {
    1'b0,
    1'b1,
    1'b0,
    1'b1,
    1'b0,
    1'b1};

  reg [0:0] valid_bank [0:5] = {
    1'b1,
    1'b1,
    1'b1,
    1'b1,
    1'b1,
    1'b1};





  reg [2:0] cmd_bank [0:5] = {
    3'b001,
    3'b001,
    3'b000,
    3'b000,
    3'b010,
    3'b010};







  reg [2:0] length_bank [0:5] = {
    3'b001,
    3'b010,
    3'b001,
    3'b010,
    3'b001,
    3'b010};

  reg [31:0] address_bank [0:5] = {
    32'hFFDD0000,
    32'h00000888,
    32'hAABB0000,
    32'h00000AAA,
    32'hFFDD0000,
    32'h00000888};

  reg [1023:0] data_bank [0:5] = {
    1023'h000000BB000000AA,
    1023'h00003666000024440000567800001234,
    1023'h0,
    1023'h0,
    1023'h000000BB000000AA,
    1023'h00003666000024440000567800001234};

  reg [5:0] feature0_bank [0:5] = {
    6'b000000,
    6'b000001,
    6'b000000,
    6'b000010,
    6'b000000,
    6'b000011};

  reg [5:0] feature1_bank [0:5] = {
    6'b000000,
    6'b111111,
    6'b000000,
    6'b000111,
    6'b000000,
    6'b111000};






  initial begin
    clk = 0;
  end  


  always #1 clk = !clk;

  always @ (posedge clk) begin

    if (o_m_tx_fsm_ready == 1'b1) begin
      stream_counter = stream_counter + 1'b1;
      i_stream_2_fsm_valid = 1'b1;
    end else begin
      stream_counter = stream_counter;
      i_stream_2_fsm_valid = 1'b0;
    end

    if ( (stream_counter < 5) || (stream_counter > 10) ) begin
      i_stream_2_fsm = 'b0;
    end else begin

      i_stream_2_fsm = {  feature1_bank[stream_counter-5],
			feature0_bank[stream_counter-5], 					
			data_bank[stream_counter-5],
			address_bank[stream_counter-5],
			length_bank[stream_counter-5],
			cmd_bank[stream_counter-5],
			valid_bank[stream_counter-5],
			mode_bank[stream_counter-5]};
     end

  end



  chiplet_sys chipletsys(

    .clk(clk),

    .i_master_tx_packetstream(i_stream_2_fsm),
    .i_master_tx_packetstream_valid(i_stream_2_fsm_valid),
    .o_master_tx_fsm_ready(o_m_tx_fsm_ready),

    .i_slave_tx_packetstream(),
    .i_slave_tx_packetstream_wen(),
    .o_slave_tx_fsm_ready(),

    .i_slave_rx_ready(1'b1),
    .i_master_rx_ready(1'b1),

    .o_slave_rx_data(o_slave_rx_data),
    .o_slave_rx_data_valid(o_slave_rx_data_valid), 
    .o_slave_rx_addr(o_slave_rx_addr), 
    .o_slave_rx_addr_valid(o_slave_rx_addr_valid), 
    .o_slave_rx_cmd(o_slave_rx_cmd),
    .o_slave_rx_cmd_valid(o_slave_rx_cmd_valid),
    .o_slave_rx_feature0(o_slave_rx_feature0),
    .o_slave_rx_feature0_valid(o_slave_rx_feature0_valid),
    .o_slave_rx_feature1(o_slave_rx_feature1),
    .o_slave_rx_feature1_valid(o_slave_rx_feature1_valid),
    .o_slave_rx_length(o_slave_rx_length),
    .o_slave_rx_length_valid(o_slave_rx_length_valid),

    .o_master_rx_data(),
    .o_master_rx_data_valid(),
    .o_master_rx_addr(),
    .o_master_rx_addr_valid(),
    .o_master_rx_cmd(),
    .o_master_rx_cmd_valid(),
    .o_master_rx_feature0(),
    .o_master_rx_feature0_valid(),
    .o_master_rx_length(),
    .o_master_rx_length_valid()
  );   




  integer f;
  initial begin
    f = $fopen("output_dump.txt","w");
    $fwrite(f, "\n------------------------------------------\n");
    $fwrite(f, "Field - Timestamp - Value ");
    $fwrite(f, "\n------------------------------------------\n");
  end

  always @ (posedge clk) begin
    if (o_slave_rx_cmd_valid == 1'b1) begin
        $fwrite(f, "------------------------------------------ \n");
        $fwrite(f, "CMD value %d, %h\n",$time, o_slave_rx_cmd);
    end
    if (o_slave_rx_addr_valid == 1'b1) begin
        $fwrite(f, "Addr value %d, %h\n",$time, o_slave_rx_addr);
    end
    if (o_slave_rx_data_valid == 1'b1) begin
        $fwrite(f, "Data value %d, %h\n",$time, o_slave_rx_data);
    end
    if (o_slave_rx_feature0_valid == 1'b1) begin
        $fwrite(f, "feature0 value %d, %h\n",$time, o_slave_rx_feature0);
    end
    if (o_slave_rx_feature1_valid == 1'b1) begin
        $fwrite(f, "feature1 value %d, %h\n",$time, o_slave_rx_feature1);
    end
    if (o_slave_rx_length_valid == 1'b1) begin
        $fwrite(f, "Length value %d, %h\n",$time, o_slave_rx_length);
    end
  end

  integer g;
  initial begin
    g = $fopen("input_dump.txt","w");
    $fwrite(g, "\n------------------------------------------\n");
    $fwrite(g, "Timestamp - Generated Flit ");
    $fwrite(g, "\n------------------------------------------\n");
  end

  always @ (posedge clk) begin
    if (chipletsys.w_m_tx_fsm_packet_valid == 1'b1) begin
        $fwrite(g, "------------------------------------------ \n");
        $fwrite(g, "%d, %h\n", $time, chipletsys.w_m_tx_fsm_packet);
    end
  end

  initial begin
    #1000 $finish;
  end


endmodule