data/full_repos/permissive/2084115/rtl/misc/jelly2_data_logger_fifo.sv
 line:34: before: "["
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/misc/jelly2_data_logger_fifo.sv:67: Operator ASSIGNW expects 128 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 129 bits.\n                                                                                         : ... In instance jelly2_data_logger_fifo\n    assign fifo_s_pack = {fifo_s_timer, s_data};\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/2084115/rtl/misc/jelly2_data_logger_fifo.sv:70: Cannot find file containing module: \'jelly_fifo_generic_fwtf\'\n    jelly_fifo_generic_fwtf\n    ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/misc,data/full_repos/permissive/2084115/jelly_fifo_generic_fwtf\n             data/full_repos/permissive/2084115/rtl/misc,data/full_repos/permissive/2084115/jelly_fifo_generic_fwtf.v\n             data/full_repos/permissive/2084115/rtl/misc,data/full_repos/permissive/2084115/jelly_fifo_generic_fwtf.sv\n             jelly_fifo_generic_fwtf\n             jelly_fifo_generic_fwtf.v\n             jelly_fifo_generic_fwtf.sv\n             obj_dir/jelly_fifo_generic_fwtf\n             obj_dir/jelly_fifo_generic_fwtf.v\n             obj_dir/jelly_fifo_generic_fwtf.sv\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/misc/jelly2_data_logger_fifo.sv:160: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 8 bits.\n                                                                                          : ... In instance jelly2_data_logger_fifo\n                if ( (s_wb_adr_i == ADR_CTL_CONTROL) && s_wb_sel_i[0] ) begin\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/misc/jelly2_data_logger_fifo.sv:164: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_limit_size\' generates 11 bits.\n                                                                                          : ... In instance jelly2_data_logger_fifo\n                    reg_limit_size <= reg_mask(reg_limit_size, s_wb_dat_i, s_wb_sel_i);\n                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/misc/jelly2_data_logger_fifo.sv:164: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                          : ... In instance jelly2_data_logger_fifo\n                    reg_limit_size <= reg_mask(reg_limit_size, s_wb_dat_i, s_wb_sel_i);\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/misc/jelly2_data_logger_fifo.sv:163: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 8 bits.\n                                                                                          : ... In instance jelly2_data_logger_fifo\n                if ( s_wb_adr_i == ADR_LIMIT_SIZE ) begin\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/misc/jelly2_data_logger_fifo.sv:181: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'fifo_m_timer\' generates 1 bits.\n                                                                                          : ... In instance jelly2_data_logger_fifo\n        ADR_POL_TIMER0:     s_wb_dat_o = WB_DAT_WIDTH\'(fifo_m_timer >> (0*WB_DAT_WIDTH));\n                                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/misc/jelly2_data_logger_fifo.sv:182: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'fifo_m_timer\' generates 1 bits.\n                                                                                          : ... In instance jelly2_data_logger_fifo\n        ADR_POL_TIMER1:     s_wb_dat_o = WB_DAT_WIDTH\'(fifo_m_timer >> (1*WB_DAT_WIDTH));\n                                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/misc/jelly2_data_logger_fifo.sv:174: Operator CASE expects 32 bits on the Case expression, but Case expression\'s VARREF \'s_wb_adr_i\' generates 8 bits.\n                                                                                          : ... In instance jelly2_data_logger_fifo\n        case (s_wb_adr_i)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/misc/jelly2_data_logger_fifo.sv:196: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 8 bits.\n                                                                                          : ... In instance jelly2_data_logger_fifo\n    assign fifo_m_ready = (s_wb_stb_i && (s_wb_adr_i == ADR_CTL_CONTROL) && s_wb_we_i && s_wb_sel_i[0] && s_wb_dat_i[0])\n                                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/misc/jelly2_data_logger_fifo.sv:197: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 8 bits.\n                                                                                          : ... In instance jelly2_data_logger_fifo\n                        | (s_wb_stb_i && (s_wb_adr_i == ADR_READ_DATA) && ~s_wb_we_i)\n                                                     ^~\n%Error: Exiting due to 1 error(s), 10 warning(s)\n'
function [WB_DAT_WIDTH-1:0] reg_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );
    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            reg_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction
function [WB_DAT_WIDTH-1:0] reg_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );

    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            reg_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction