data/full_repos/permissive/180282590/SimpleGPUonS7.srcs/sources_1/new/FiFO.v
data/verilator_xmls/03035d30-89e1-45b8-94f7-991c4eab3937.xml
module FIFO(clk_i, data_i, reset_i, r_en_i, w_en_i, data_o, empty_o, full_o, count_o );
input clk_i;
input reset_i;
input [DATA_WIDTH-1:0]data_i;
input r_en_i;
input w_en_i;

output reg [DATA_WIDTH-1:0]data_o;
output empty_o;
output full_o;
output count_o; 

parameter DATA_WIDTH = 8;
parameter RAM_DEPTH = 8;
  
reg [RAM_DEPTH:0]count;
reg [DATA_WIDTH-1:0]memory[RAM_DEPTH-1:0];
reg [2:0]wr_pointer, rd_pointer;
reg full, empty;
reg [DATA_WIDTH-1:0]dataout;


always @( posedge clk_i or posedge reset_i)
begin
   if( reset_i )
   begin
      dataout <= 0;

   end
   else
   begin
      if( r_en_i && !empty_o )
         dataout <= memory[rd_pointer];

      else
         dataout <= dataout;

   end
end


always @(posedge clk_i)
begin
   if( w_en_i && !full_o )
      memory[wr_pointer] <= data_i;

   else
      memory[wr_pointer] <= memory[wr_pointer];
end




always @ (posedge clk_i or posedge reset_i)
begin 
	if(reset_i)
	begin

		wr_pointer <= 0;
		rd_pointer <= 0;
	end
	else
	begin

		if(!full_o && w_en_i)
		wr_pointer <= wr_pointer+1;

		else
		wr_pointer <= wr_pointer;

		if(!empty_o && r_en_i)
		rd_pointer <= rd_pointer+1;

		else
		rd_pointer <= rd_pointer;
	end
end


always @(posedge clk_i or posedge reset_i)
begin
   if( reset_i )
       count <= 0;




   else if( (!full_o && w_en_i) && ( !empty_o && r_en_i ) )
       count <= count;

   else if( !full_o && w_en_i )
       count <= count + 1;

   else if( !empty_o && r_en_i )
       count <= count - 1;
   else
      count <= count;
end



always @(count)
begin
if(count==0)
  empty = 1 ;
  else
  empty = 0;

  if(count==RAM_DEPTH)
   full = 1;
   else
   full = 0;
end

endmodule
module FIFO(clk_i, data_i, reset_i, r_en_i, w_en_i, data_o, empty_o, full_o, count_o );

input clk_i;
input reset_i;
input [DATA_WIDTH-1:0]data_i;
input r_en_i;
input w_en_i;

output reg [DATA_WIDTH-1:0]data_o;
output empty_o;
output full_o;
output count_o; 

parameter DATA_WIDTH = 8;
parameter RAM_DEPTH = 8;
  
reg [RAM_DEPTH:0]count;
reg [DATA_WIDTH-1:0]memory[RAM_DEPTH-1:0];
reg [2:0]wr_pointer, rd_pointer;
reg full, empty;
reg [DATA_WIDTH-1:0]dataout;


always @( posedge clk_i or posedge reset_i)
begin
   if( reset_i )
   begin
      dataout <= 0;

   end
   else
   begin
      if( r_en_i && !empty_o )
         dataout <= memory[rd_pointer];

      else
         dataout <= dataout;

   end
end


always @(posedge clk_i)
begin
   if( w_en_i && !full_o )
      memory[wr_pointer] <= data_i;

   else
      memory[wr_pointer] <= memory[wr_pointer];
end




always @ (posedge clk_i or posedge reset_i)
begin 
	if(reset_i)
	begin

		wr_pointer <= 0;
		rd_pointer <= 0;
	end
	else
	begin

		if(!full_o && w_en_i)
		wr_pointer <= wr_pointer+1;

		else
		wr_pointer <= wr_pointer;

		if(!empty_o && r_en_i)
		rd_pointer <= rd_pointer+1;

		else
		rd_pointer <= rd_pointer;
	end
end


always @(posedge clk_i or posedge reset_i)
begin
   if( reset_i )
       count <= 0;




   else if( (!full_o && w_en_i) && ( !empty_o && r_en_i ) )
       count <= count;

   else if( !full_o && w_en_i )
       count <= count + 1;

   else if( !empty_o && r_en_i )
       count <= count - 1;
   else
      count <= count;
end



always @(count)
begin
if(count==0)
  empty = 1 ;
  else
  empty = 0;

  if(count==RAM_DEPTH)
   full = 1;
   else
   full = 0;
end

endmodule