data/full_repos/permissive/159902111/ALU_sample/alu_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:1: Cannot find include file: ./defines.v\n`include "./defines.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159902111/ALU_sample,data/full_repos/permissive/159902111/./defines.v\n             data/full_repos/permissive/159902111/ALU_sample,data/full_repos/permissive/159902111/./defines.v.v\n             data/full_repos/permissive/159902111/ALU_sample,data/full_repos/permissive/159902111/./defines.v.sv\n             ./defines.v\n             ./defines.v.v\n             ./defines.v.sv\n             obj_dir/./defines.v\n             obj_dir/./defines.v.v\n             obj_dir/./defines.v.sv\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:24: Define or directive not defined: \'`ALUOP_NOP\'\n    aluop=`ALUOP_NOP;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    aluop=`ALUOP_NOP;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk<=~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:44: Define or directive not defined: \'`ALUOP_NOP\'\n      `ALUOP_NOP:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:44: syntax error, unexpected \':\', expecting endcase\n      `ALUOP_NOP:\n                ^\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:47: Define or directive not defined: \'`ALUOP_SUB\'\n      `ALUOP_SUB:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:53: Define or directive not defined: \'`ALUOP_ADD\'\n      `ALUOP_ADD,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:53: syntax error, unexpected \',\'\n      `ALUOP_ADD,\n                ^\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:54: Define or directive not defined: \'`ALUOP_SLT\'\n      `ALUOP_SLT,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:55: Define or directive not defined: \'`ALUOP_SLTU\'\n      `ALUOP_SLTU,\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:56: Define or directive not defined: \'`ALUOP_AND\'\n      `ALUOP_AND,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:57: Define or directive not defined: \'`ALUOP_NOR\'\n      `ALUOP_NOR,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:58: Define or directive not defined: \'`ALUOP_OR\'\n      `ALUOP_OR,\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:59: Define or directive not defined: \'`ALUOP_LUI\'\n      `ALUOP_LUI,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:60: Define or directive not defined: \'`ALUOP_SLL\'\n      `ALUOP_SLL,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:61: Define or directive not defined: \'`ALUOP_SRL\'\n      `ALUOP_SRL,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:62: Define or directive not defined: \'`ALUOP_SRA\'\n      `ALUOP_SRA:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:68: Define or directive not defined: \'`ALUOP_DIV\'\n      `ALUOP_DIV,\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:69: Define or directive not defined: \'`ALUOP_DIVU\'\n      `ALUOP_DIVU,\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:70: Define or directive not defined: \'`ALUOP_MULT\'\n      `ALUOP_MULT,\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:71: Define or directive not defined: \'`ALUOP_MULTU\'\n      `ALUOP_MULTU:\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/ALU_sample/alu_tb.v:85: syntax error, unexpected $fclose\n        $fclose(fd);\n        ^~~~~~~\n%Error: Cannot continue\n'
module alu_tb(
  );
  `timescale  1ns/1ps
  reg clk;
  reg [31:0]line_cnt;
  reg [31:0]tmp_hi,tmp_lo;
  reg   tmp_zero;
  wire  [63:0]aluout;
  wire  zero;
  
  reg   [4:0]aluop;
  reg   [31:0]src0,src1;

  integer cnt,fd;
  initial
  begin
    clk=1;
    fd=$fopen("data.txt","r");
    line_cnt=0;
    tmp_lo=0;
    tmp_hi=0;
    tmp_zero=0;
    aluop=`ALUOP_NOP;
    src0=0;
    src1=0;
  end
  always
    #10 clk<=~clk;
    
  alu alu0(
  .aluop_i(aluop),
  .src0_i(src0),
  .src1_i(src1),
  .aluout_o(aluout),
  .zero_o(zero)
  );
  
  always@(posedge clk)
  begin
    line_cnt<=line_cnt+1;
    
    case(aluop)
      `ALUOP_NOP:

          ;
      `ALUOP_SUB:
          if(aluout[31:0]!=tmp_lo || zero!=tmp_zero)
            begin
              $display("testcase %d failed!",line_cnt);
              $stop;
            end
      `ALUOP_ADD,
      `ALUOP_SLT,
      `ALUOP_SLTU,
      `ALUOP_AND,
      `ALUOP_NOR,
      `ALUOP_OR,
      `ALUOP_LUI,
      `ALUOP_SLL,
      `ALUOP_SRL,
      `ALUOP_SRA:
          if(aluout[31:0]!=tmp_lo)
            begin
              $display("testcase %d failed!",line_cnt);
              $stop;
            end
      `ALUOP_DIV,
      `ALUOP_DIVU,
      `ALUOP_MULT,
      `ALUOP_MULTU:
          if(aluout!={tmp_hi,tmp_lo})
            begin
              $display("testcase %d failed!",line_cnt);
              $stop;
            end
      default:
          $display("unknown aluop!");
    endcase
    
    cnt=$fscanf(fd,"0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t",aluop,src0,src1,tmp_hi,tmp_lo,tmp_zero);
    $display("%x %x %x %x %x %x /cnt:%d",aluop,src0,src1,tmp_hi,tmp_lo,tmp_zero,cnt);
    if (cnt!=6)
      begin
        $fclose(fd);
        $display("pass!");
        $stop;
      end
  end
  
endmodule
module alu_tb(
  );

  `timescale  1ns/1ps
  reg clk;
  reg [31:0]line_cnt;
  reg [31:0]tmp_hi,tmp_lo;
  reg   tmp_zero;
  wire  [63:0]aluout;
  wire  zero;
  
  reg   [4:0]aluop;
  reg   [31:0]src0,src1;

  integer cnt,fd;
  initial
  begin
    clk=1;
    fd=$fopen("data.txt","r");
    line_cnt=0;
    tmp_lo=0;
    tmp_hi=0;
    tmp_zero=0;
    aluop=`ALUOP_NOP;
    src0=0;
    src1=0;
  end
  always
    #10 clk<=~clk;
    
  alu alu0(
  .aluop_i(aluop),
  .src0_i(src0),
  .src1_i(src1),
  .aluout_o(aluout),
  .zero_o(zero)
  );
  
  always@(posedge clk)
  begin
    line_cnt<=line_cnt+1;
    
    case(aluop)
      `ALUOP_NOP:

          ;
      `ALUOP_SUB:
          if(aluout[31:0]!=tmp_lo || zero!=tmp_zero)
            begin
              $display("testcase %d failed!",line_cnt);
              $stop;
            end
      `ALUOP_ADD,
      `ALUOP_SLT,
      `ALUOP_SLTU,
      `ALUOP_AND,
      `ALUOP_NOR,
      `ALUOP_OR,
      `ALUOP_LUI,
      `ALUOP_SLL,
      `ALUOP_SRL,
      `ALUOP_SRA:
          if(aluout[31:0]!=tmp_lo)
            begin
              $display("testcase %d failed!",line_cnt);
              $stop;
            end
      `ALUOP_DIV,
      `ALUOP_DIVU,
      `ALUOP_MULT,
      `ALUOP_MULTU:
          if(aluout!={tmp_hi,tmp_lo})
            begin
              $display("testcase %d failed!",line_cnt);
              $stop;
            end
      default:
          $display("unknown aluop!");
    endcase
    
    cnt=$fscanf(fd,"0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t",aluop,src0,src1,tmp_hi,tmp_lo,tmp_zero);
    $display("%x %x %x %x %x %x /cnt:%d",aluop,src0,src1,tmp_hi,tmp_lo,tmp_zero,cnt);
    if (cnt!=6)
      begin
        $fclose(fd);
        $display("pass!");
        $stop;
      end
  end
  
endmodule