data/full_repos/permissive/135852214/Verilog/microproc_sim.v
1: b"%Error: data/full_repos/permissive/135852214/Verilog/microproc_sim.v:27: Cannot find file containing module: 'microprocessor'\n   microprocessor UUT (\n   ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/microprocessor\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/microprocessor.v\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/microprocessor.sv\n             microprocessor\n             microprocessor.v\n             microprocessor.sv\n             obj_dir/microprocessor\n             obj_dir/microprocessor.v\n             obj_dir/microprocessor.sv\n%Error: Exiting due to 1 error(s)\n"
module microprocessor_microprocessor_sch_tb();


   reg CTRL_A;
   reg RESET;
   reg CLK;
   reg WE_A;
   reg [11:0] DATA_IN;
   reg WE_B;
   reg CIN;
   reg WE_PC;
   reg CTRL_PC;
   reg CTRL_ADDR;


   wire [11:0] ADDR_OUT;
   wire [11:0] DATA_OUT;
   wire OVF;




   microprocessor UUT (
		.ADDR_OUT(ADDR_OUT), 
		.DATA_OUT(DATA_OUT), 
		.CTRL_A(CTRL_A), 
		.RESET(RESET), 
		.CLK(CLK), 
		.WE_A(WE_A), 
		.DATA_IN(DATA_IN), 
		.WE_B(WE_B), 
		.CIN(CIN), 
		.OVF(OVF), 
		.WE_PC(WE_PC), 
		.CTRL_PC(CTRL_PC), 
		.CTRL_ADDR(CTRL_ADDR)
   );

   `ifdef auto_init
       initial begin
		CTRL_A = 0;
		RESET = 0;
		CLK = 0;
		WE_A = 0;
		DATA_IN = 0;
		WE_B = 0;
		CIN = 0;
		WE_PC = 0;
		CTRL_PC = 0;
		CTRL_ADDR = 0;
   `endif
endmodule
module microprocessor_microprocessor_sch_tb();



   reg CTRL_A;
   reg RESET;
   reg CLK;
   reg WE_A;
   reg [11:0] DATA_IN;
   reg WE_B;
   reg CIN;
   reg WE_PC;
   reg CTRL_PC;
   reg CTRL_ADDR;


   wire [11:0] ADDR_OUT;
   wire [11:0] DATA_OUT;
   wire OVF;




   microprocessor UUT (
		.ADDR_OUT(ADDR_OUT), 
		.DATA_OUT(DATA_OUT), 
		.CTRL_A(CTRL_A), 
		.RESET(RESET), 
		.CLK(CLK), 
		.WE_A(WE_A), 
		.DATA_IN(DATA_IN), 
		.WE_B(WE_B), 
		.CIN(CIN), 
		.OVF(OVF), 
		.WE_PC(WE_PC), 
		.CTRL_PC(CTRL_PC), 
		.CTRL_ADDR(CTRL_ADDR)
   );

   `ifdef auto_init
       initial begin
		CTRL_A = 0;
		RESET = 0;
		CLK = 0;
		WE_A = 0;
		DATA_IN = 0;
		WE_B = 0;
		CIN = 0;
		WE_PC = 0;
		CTRL_PC = 0;
		CTRL_ADDR = 0;
   `endif
endmodule