data/full_repos/permissive/143278/ivltests/pr673.v
 line:23: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr673.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #10 period = $time;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr673.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #30 $display("bye.");\n  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr673.v:6: Unsized constant being X/Z extended to 64 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                    : ... In instance main\n  if (period !== \'hx) $display ("init wrong");\n                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr673.v:7: Unsized constant being X/Z extended to 64 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                    : ... In instance main\n  if (period === \'hx)\n                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr673.v:15: Operator NEQCASE expects 64 bits on the RHS, but RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                     : ... In instance main\n  if (period !== 1\'bx)\n             ^~~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

reg[63:0]  period;

initial begin
  if (period !== 'hx) $display ("init wrong");
  if (period === 'hx)
    $display ("init right");
  else
    $display ("init wrong 2: %h", period);
end

always @ (period) begin

  if (period !== 1'bx)
    $display ("right %t %d", $time,period);
  else
    $display("wrong %t %d",$time,period);
end

initial begin
  #10 period = $time;
  #30 $display("bye.");
  $finish(0);
end

endmodule
module main;


reg[63:0]  period;

initial begin
  if (period !== 'hx) $display ("init wrong");
  if (period === 'hx)
    $display ("init right");
  else
    $display ("init wrong 2: %h", period);
end

always @ (period) begin

  if (period !== 1'bx)
    $display ("right %t %d", $time,period);
  else
    $display("wrong %t %d",$time,period);
end

initial begin
  #10 period = $time;
  #30 $display("bye.");
  $finish(0);
end

endmodule