data/full_repos/permissive/201275379/src/cpu/core/stage/pc/GHR.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/GHR.v:3: Cannot find include file: branch.v\n`include "branch.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/src/cpu/core/stage/pc,data/full_repos/permissive/201275379/branch.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/pc,data/full_repos/permissive/201275379/branch.v.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/pc,data/full_repos/permissive/201275379/branch.v.sv\n             branch.v\n             branch.v.v\n             branch.v.sv\n             obj_dir/branch.v\n             obj_dir/branch.v.v\n             obj_dir/branch.v.sv\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/GHR.v:12: Define or directive not defined: \'`GHR_BUS\'\n  output  [`GHR_BUS]  ghr_out\n           ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/GHR.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  output  [`GHR_BUS]  ghr_out\n                   ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/GHR.v:15: Define or directive not defined: \'`GHR_BUS\'\n  reg[`GHR_BUS] ghr;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/GHR.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`GHR_BUS] ghr;\n              ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/GHR.v:23: Define or directive not defined: \'`GHR_WIDTH\'\n      ghr <= {ghr[`GHR_WIDTH - 2:0], is_taken};\n                  ^~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module GHR(
  input               clk,
  input               rst,

  input               is_branch,
  input               is_taken,

  output  [`GHR_BUS]  ghr_out
);

  reg[`GHR_BUS] ghr;
  assign ghr_out = ghr;

  always @(posedge clk) begin
    if (!rst) begin
      ghr <= 0;
    end
    else if (is_branch) begin
      ghr <= {ghr[`GHR_WIDTH - 2:0], is_taken};
    end
  end

endmodule
module GHR(
  input               clk,
  input               rst,

  input               is_branch,
  input               is_taken,

  output  [`GHR_BUS]  ghr_out
);


  reg[`GHR_BUS] ghr;
  assign ghr_out = ghr;

  always @(posedge clk) begin
    if (!rst) begin
      ghr <= 0;
    end
    else if (is_branch) begin
      ghr <= {ghr[`GHR_WIDTH - 2:0], is_taken};
    end
  end

endmodule