data/full_repos/permissive/139213403/FPGA/parity_calculator.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/8fba35f7-9a33-4d81-a7f8-ac8323bc763e.xml
module parity_calculator
#(
	parameter DBIT=8
)
(
	input wire [DBIT-1:0] data,
	input wire [3:0] dbit,
	input wire [1:0] pbit,
	output wire parity
);



wire zero;
wire xs;

assign zero = 0;
assign xs = (dbit == 7) ? ^data[6:0] : ^data[7:0];
assign parity = pbit == 0 ? zero :
					 pbit == 1 ? xs  :
					 ~xs;

endmodule
module parity_calculator
#(
	parameter DBIT=8
)
(
	input wire [DBIT-1:0] data,
	input wire [3:0] dbit,
	input wire [1:0] pbit,
	output wire parity
);




wire zero;
wire xs;

assign zero = 0;
assign xs = (dbit == 7) ? ^data[6:0] : ^data[7:0];
assign parity = pbit == 0 ? zero :
					 pbit == 1 ? xs  :
					 ~xs;

endmodule