data/full_repos/permissive/120944384/code/tb/tb_imitator_dvp_ifc.v
None: at end of input
1: b'%Error: data/full_repos/permissive/120944384/code/tb/tb_imitator_dvp_ifc.v:37: Cannot find include file: ../task_write_file.v\n`include "../task_write_file.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120944384/code/tb,data/full_repos/permissive/120944384/../task_write_file.v\n             data/full_repos/permissive/120944384/code/tb,data/full_repos/permissive/120944384/../task_write_file.v.v\n             data/full_repos/permissive/120944384/code/tb,data/full_repos/permissive/120944384/../task_write_file.v.sv\n             ../task_write_file.v\n             ../task_write_file.v.v\n             ../task_write_file.v.sv\n             obj_dir/../task_write_file.v\n             obj_dir/../task_write_file.v.v\n             obj_dir/../task_write_file.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/120944384/code/tb/tb_imitator_dvp_ifc.v:18: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk_sys = ~clk_sys;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120944384/code/tb/tb_imitator_dvp_ifc.v:19: Unsupported: Ignoring delay on this delayed statement.\nalways #2.604 pclk = ~pclk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/120944384/code/tb/tb_imitator_dvp_ifc.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10000;\n ^\n%Error: data/full_repos/permissive/120944384/code/tb/tb_imitator_dvp_ifc.v:44: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/120944384/code/tb/tb_imitator_dvp_ifc.v:46: syntax error, unexpected \'@\'\n @(posedge clk_sys);\n ^\n%Error: data/full_repos/permissive/120944384/code/tb/tb_imitator_dvp_ifc.v:86: syntax error, unexpected $fopen, expecting TYPE-IDENTIFIER\n integer file_Y1_out  = $fopen("../result_images/Y1_comp_out.txt" ,"w");\n                        ^~~~~~\n%Error: data/full_repos/permissive/120944384/code/tb/tb_imitator_dvp_ifc.v:97: syntax error, unexpected $fopen, expecting TYPE-IDENTIFIER\n integer file_Y2_out  = $fopen("../result_images/Y2_comp_out.txt" ,"w");\n                        ^~~~~~\n%Error: data/full_repos/permissive/120944384/code/tb/tb_imitator_dvp_ifc.v:120: syntax error, unexpected \'@\'\n  forever @( posedge clk_sys )\n          ^\n%Error: data/full_repos/permissive/120944384/code/tb/tb_imitator_dvp_ifc.v:127: syntax error, unexpected else\n    else if ( count_line == 720 )\n    ^~~~\n%Error: Cannot continue\n'
module tb_imitator_dvp_ifc;	

reg run_test;
reg stop_test;
reg [9:0] count_line;
reg reset_n;
reg clk_sys=0;
reg pclk   =0;
always #5 clk_sys = ~clk_sys;
always #2.604 pclk = ~pclk;

wire [7:0] D1;
wire [7:0] D2;
wire       HREF;
wire       VSYNC;

wire [7:0] Y1;
wire [7:0] Y2;
wire [7:0] CbCr1;
wire [7:0] CbCr2;
wire       SOF;
wire       EOF;
wire       validY;
wire       validCb;
wire       validCr;
wire last_data = EOF;
wire end_frame = count_line == 'd720;
`include "../task_write_file.v"
initial begin
	reset_n    <= 0;
	run_test   <= 0;
	stop_test  <= 0;
	#10000;
	reset_n  <= 1;
	@(posedge clk_sys);
	run_test    <=1;
	@(posedge clk_sys);
	run_test <=0;
end

imitator_dvp_ifc imitator_dvp_ifc_inst 
(
	.pclk      (pclk      ),  
	.reset_n   (reset_n   ),
	.run_test  (run_test  ),
	.stop_test (stop_test ),
	.VSYNC     (VSYNC     ),
    .HREF      (HREF      ),
    .D1        (D1        ),
    .D2        (D2        )
);

convert2avl_stream convert_to_avlstream_image_1
(
	.pclk      (pclk      ), 
	.clk_sys   (clk_sys   ),
	.reset_n   (reset_n   ),

	.VSYNC     (VSYNC     ),
	.HREF      (HREF      ),
	.D1        (D1        ),
	.D2        (D2        ),

	.Y1        (Y1        ),
	.CbCr1     (CbCr1     ),
	.Y2        (Y2        ),
	.CbCr2     (CbCr2     ),
	.validY    (validY    ),
	.validCb   (validCb   ),
	.validCr   (validCr   ),
	.SOF       (SOF       ),
	.EOF       (EOF       )
);


initial begin
	integer file_Y1_out  = $fopen("../result_images/Y1_comp_out.txt" ,"w");
	integer file_Cb1_out = $fopen("../result_images/Cb1_comp_out.txt","w");
	integer file_Cr1_out = $fopen("../result_images/Cr1_comp_out.txt","w");

	@(posedge reset_n);
	@(posedge clk_sys);
	write_comp_image_to_file_1(file_Y1_out, file_Cb1_out, file_Cr1_out);
end


initial begin
	integer file_Y2_out  = $fopen("../result_images/Y2_comp_out.txt" ,"w");
	integer file_Cb2_out = $fopen("../result_images/Cb2_comp_out.txt","w");
	integer file_Cr2_out = $fopen("../result_images/Cr2_comp_out.txt","w");
	@(posedge reset_n);
	@(posedge clk_sys);
	write_comp_image_to_file_2(file_Y2_out, file_Cb2_out, file_Cr2_out);
end


		
always @(posedge clk_sys, negedge reset_n)
	if(!reset_n)
		count_line <='0;
	else if(end_frame)
		count_line <='0;
	else if(last_data)
		count_line <= count_line + 1;	

integer test_file,test_file1;	
initial
	begin
		test_file  = $fopen("../test_filez.txt","w");
		test_file1  = $fopen("../test_file1z.txt","w");
		forever @( posedge clk_sys )
			begin
				if (validY)
					begin
						$fwrite (test_file,Y1,"\n");
						$fwrite (test_file1,CbCr1,"\n");
					end
				else if ( count_line == 720 )
					begin
						$fclose(test_file);
						$fclose(test_file1);
						$stop;
					end
			end   	
	end
	
endmodule
module tb_imitator_dvp_ifc;
	

reg run_test;
reg stop_test;
reg [9:0] count_line;
reg reset_n;
reg clk_sys=0;
reg pclk   =0;
always #5 clk_sys = ~clk_sys;
always #2.604 pclk = ~pclk;

wire [7:0] D1;
wire [7:0] D2;
wire       HREF;
wire       VSYNC;

wire [7:0] Y1;
wire [7:0] Y2;
wire [7:0] CbCr1;
wire [7:0] CbCr2;
wire       SOF;
wire       EOF;
wire       validY;
wire       validCb;
wire       validCr;
wire last_data = EOF;
wire end_frame = count_line == 'd720;
`include "../task_write_file.v"
initial begin
	reset_n    <= 0;
	run_test   <= 0;
	stop_test  <= 0;
	#10000;
	reset_n  <= 1;
	@(posedge clk_sys);
	run_test    <=1;
	@(posedge clk_sys);
	run_test <=0;
end

imitator_dvp_ifc imitator_dvp_ifc_inst 
(
	.pclk      (pclk      ),  
	.reset_n   (reset_n   ),
	.run_test  (run_test  ),
	.stop_test (stop_test ),
	.VSYNC     (VSYNC     ),
    .HREF      (HREF      ),
    .D1        (D1        ),
    .D2        (D2        )
);

convert2avl_stream convert_to_avlstream_image_1
(
	.pclk      (pclk      ), 
	.clk_sys   (clk_sys   ),
	.reset_n   (reset_n   ),

	.VSYNC     (VSYNC     ),
	.HREF      (HREF      ),
	.D1        (D1        ),
	.D2        (D2        ),

	.Y1        (Y1        ),
	.CbCr1     (CbCr1     ),
	.Y2        (Y2        ),
	.CbCr2     (CbCr2     ),
	.validY    (validY    ),
	.validCb   (validCb   ),
	.validCr   (validCr   ),
	.SOF       (SOF       ),
	.EOF       (EOF       )
);


initial begin
	integer file_Y1_out  = $fopen("../result_images/Y1_comp_out.txt" ,"w");
	integer file_Cb1_out = $fopen("../result_images/Cb1_comp_out.txt","w");
	integer file_Cr1_out = $fopen("../result_images/Cr1_comp_out.txt","w");

	@(posedge reset_n);
	@(posedge clk_sys);
	write_comp_image_to_file_1(file_Y1_out, file_Cb1_out, file_Cr1_out);
end


initial begin
	integer file_Y2_out  = $fopen("../result_images/Y2_comp_out.txt" ,"w");
	integer file_Cb2_out = $fopen("../result_images/Cb2_comp_out.txt","w");
	integer file_Cr2_out = $fopen("../result_images/Cr2_comp_out.txt","w");
	@(posedge reset_n);
	@(posedge clk_sys);
	write_comp_image_to_file_2(file_Y2_out, file_Cb2_out, file_Cr2_out);
end


		
always @(posedge clk_sys, negedge reset_n)
	if(!reset_n)
		count_line <='0;
	else if(end_frame)
		count_line <='0;
	else if(last_data)
		count_line <= count_line + 1;	

integer test_file,test_file1;	
initial
	begin
		test_file  = $fopen("../test_filez.txt","w");
		test_file1  = $fopen("../test_file1z.txt","w");
		forever @( posedge clk_sys )
			begin
				if (validY)
					begin
						$fwrite (test_file,Y1,"\n");
						$fwrite (test_file1,CbCr1,"\n");
					end
				else if ( count_line == 720 )
					begin
						$fclose(test_file);
						$fclose(test_file1);
						$stop;
					end
			end   	
	end
	
endmodule