data/full_repos/permissive/126366342/verilog modules/mips_rom.v
1: b'%Error: Cannot find file containing module: modules,data/full_repos/permissive/126366342\n        ... Looked in:\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342.v\n             data/full_repos/permissive/126366342/verilog/modules,data/full_repos/permissive/126366342.sv\n             modules,data/full_repos/permissive/126366342\n             modules,data/full_repos/permissive/126366342.v\n             modules,data/full_repos/permissive/126366342.sv\n             obj_dir/modules,data/full_repos/permissive/126366342\n             obj_dir/modules,data/full_repos/permissive/126366342.v\n             obj_dir/modules,data/full_repos/permissive/126366342.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/126366342/verilog\n%Error: Cannot find file containing module: modules/mips_rom.v\n%Error: Exiting due to 3 error(s)\n'
module mips_rom(
    input [31:0] address,
    output reg [31:0] data
);

always @(address) begin
    case(address)






	 32'h0000_0000: data = 32'b1000_1100_0000_0001_0000_0000_0111_1111;
	 32'h0000_0001: data = 32'b1000_1100_0000_0010_0000_0000_1000_0010;
	 32'h0000_0002: data = 32'b1000_1100_0000_0011_0000_0000_1000_0100;
	 32'h0000_0003: data = 32'b1000_1100_0000_0100_0000_0000_1000_1000;
	 32'h0000_0004: data = 32'b1000_1100_0000_0101_0000_0000_1000_1100;
	 32'h0000_0005: data = 32'b1010_1100_0010_0011_0000_0000_0000_0000;
	 32'h0000_0006: data = 32'b1010_1100_0010_0010_0000_0000_0001_0000;
	 32'h0000_0007: data = 32'b1010_1100_0010_0100_0000_0000_0010_0000;
	 32'h0000_0008: data = 32'b1010_1100_0010_0101_0000_0000_0011_0000;
	 32'h0000_001F: data = 32'b00000000000000110000100000000000;
	 32'h0000_0020: data = 32'b10001001101010111100110111101111;
	 32'h0000_0021: data = 32'b00000001001000110100010101100111;
	 32'h0000_0022: data = 32'h13345779;
	 32'h0000_0023: data = 32'h9BBCDFF1;




    default: data = 32'hFFFF_FFFF;
    endcase
end


endmodule
module mips_rom(
    input [31:0] address,
    output reg [31:0] data
);


always @(address) begin
    case(address)






	 32'h0000_0000: data = 32'b1000_1100_0000_0001_0000_0000_0111_1111;
	 32'h0000_0001: data = 32'b1000_1100_0000_0010_0000_0000_1000_0010;
	 32'h0000_0002: data = 32'b1000_1100_0000_0011_0000_0000_1000_0100;
	 32'h0000_0003: data = 32'b1000_1100_0000_0100_0000_0000_1000_1000;
	 32'h0000_0004: data = 32'b1000_1100_0000_0101_0000_0000_1000_1100;
	 32'h0000_0005: data = 32'b1010_1100_0010_0011_0000_0000_0000_0000;
	 32'h0000_0006: data = 32'b1010_1100_0010_0010_0000_0000_0001_0000;
	 32'h0000_0007: data = 32'b1010_1100_0010_0100_0000_0000_0010_0000;
	 32'h0000_0008: data = 32'b1010_1100_0010_0101_0000_0000_0011_0000;
	 32'h0000_001F: data = 32'b00000000000000110000100000000000;
	 32'h0000_0020: data = 32'b10001001101010111100110111101111;
	 32'h0000_0021: data = 32'b00000001001000110100010101100111;
	 32'h0000_0022: data = 32'h13345779;
	 32'h0000_0023: data = 32'h9BBCDFF1;




    default: data = 32'hFFFF_FFFF;
    endcase
end


endmodule