data/full_repos/permissive/11455462/90522175_3(tb) (1).v
 line:7 column:16: Illegal character "'"
1: b'%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:8: Unsupported: Ignoring delay on this delayed statement.\n        #40;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:10: Unsupported: Ignoring delay on this delayed statement.\n        #40;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:12: Unsupported: Ignoring delay on this delayed statement.\n        #40;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:14: Unsupported: Ignoring delay on this delayed statement.\n        #40;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:16: Unsupported: Ignoring delay on this delayed statement.\n        #40;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:18: Unsupported: Ignoring delay on this delayed statement.\n        #40;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:20: Unsupported: Ignoring delay on this delayed statement.\n        #40;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:22: Unsupported: Ignoring delay on this delayed statement.\n        #40;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:24: Unsupported: Ignoring delay on this delayed statement.\n        #40;\n        ^\n%Error: Cannot find file containing module: (1).v\n        ... Looked in:\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v.v\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v.sv\n             (1).v\n             (1).v.v\n             (1).v.sv\n             obj_dir/(1).v\n             obj_dir/(1).v.v\n             obj_dir/(1).v.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_BCD_Seven_segment();
    reg [3:0] in;
    wire [6:0] out;
    BCD_Seven_segment Bss(in,out);
    initial
    begin
        in = 4'b 0000;
        #40;
        in = 4'b 0001;
        #40;
        in = 4'b 0010;
        #40;
        in = 4'b 0011;
        #40;
        in = 4'b 0100;
        #40;
        in = 4'b 0101;
        #40;
        in = 4'b 0110;
        #40;
        in = 4'b 0111;
        #40;
        in = 4'b 1000;
        #40;
        in = 4'b 1001;
    end
 endmodule
module tb_BCD_Seven_segment();

    reg [3:0] in;
    wire [6:0] out;
    BCD_Seven_segment Bss(in,out);
    initial
    begin
        in = 4'b 0000;
        #40;
        in = 4'b 0001;
        #40;
        in = 4'b 0010;
        #40;
        in = 4'b 0011;
        #40;
        in = 4'b 0100;
        #40;
        in = 4'b 0101;
        #40;
        in = 4'b 0110;
        #40;
        in = 4'b 0111;
        #40;
        in = 4'b 1000;
        #40;
        in = 4'b 1001;
    end
 endmodule