data/full_repos/permissive/14593708/data/register-file/register.v
1: b"%Error: data/full_repos/permissive/14593708/data/register-file/register.v:12: Cannot find file containing module: 'data_flip_flop'\n            data_flip_flop dff(data[i], set, value[i], q_bar);\n            ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/14593708/data/register-file,data/full_repos/permissive/14593708/data_flip_flop\n             data/full_repos/permissive/14593708/data/register-file,data/full_repos/permissive/14593708/data_flip_flop.v\n             data/full_repos/permissive/14593708/data/register-file,data/full_repos/permissive/14593708/data_flip_flop.sv\n             data_flip_flop\n             data_flip_flop.v\n             data_flip_flop.sv\n             obj_dir/data_flip_flop\n             obj_dir/data_flip_flop.v\n             obj_dir/data_flip_flop.sv\n%Error: Exiting due to 1 error(s)\n"
module register#(parameter BIT_WIDTH = 32)
                (input[BIT_WIDTH - 1:0]   data,
                 input                    set,
                 output[BIT_WIDTH - 1: 0] value);

    genvar i;

    generate
        for (i = 0; i < BIT_WIDTH; i = i + 1)
        begin : data_flip_flop
            wire q_bar;
            data_flip_flop dff(data[i], set, value[i], q_bar);
        end
    endgenerate

endmodule
module register#(parameter BIT_WIDTH = 32)
                (input[BIT_WIDTH - 1:0]   data,
                 input                    set,
                 output[BIT_WIDTH - 1: 0] value);


    genvar i;

    generate
        for (i = 0; i < BIT_WIDTH; i = i + 1)
        begin : data_flip_flop
            wire q_bar;
            data_flip_flop dff(data[i], set, value[i], q_bar);
        end
    endgenerate

endmodule