data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:210: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg0 (\n               ^~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:216: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:222: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg2 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:228: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg3 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:234: Cell has missing pin: \'en\'\n  reg_ar_as_w18 reg4 (\n                ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:240: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg5 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:246: Cell has missing pin: \'en\'\n  reg_ar_as_w25 reg6 (\n                ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:252: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg7 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/3_Seg_4bit/seg4_tdread.v:580: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg0 (\n               ^~~~\n%Error: Exiting due to 9 warning(s)\n'
module seg4
  (
  clk_24m,
  sm_bit,
  sm_seg
  );

  input clk_24m;
  output [3:0] sm_bit;
  output [7:0] sm_seg;

  parameter CNT_TIME = 2400000;










  wire [24:0] cnt;
  wire [17:0] cnt_w;
  wire [3:0] n10;
  wire [3:0] n11;
  wire [3:0] n12;
  wire [3:0] n17;
  wire [3:0] n18;
  wire [3:0] n19;
  wire [24:0] n2;
  wire [3:0] n25;
  wire [3:0] n26;
  wire [3:0] n27;
  wire [17:0] n29;
  wire [24:0] n3;
  wire [17:0] n30;
  wire [3:0] n31;
  wire [3:0] n32;
  wire [3:0] n5;
  wire [3:0] n6;
  wire [3:0] n7;
  wire [3:0] sm_bit1_num;
  wire [3:0] sm_bit2_num;
  wire [3:0] sm_bit3_num;
  wire [3:0] sm_bit4_num;
  wire [3:0] sm_bit_reg;
  wire [3:0] sm_seg_num;
  wire [7:0] sm_seg_reg;
  wire n0;
  wire n1;
  wire n13;
  wire n14;
  wire n15;
  wire n16;
  wire n20;
  wire n21;
  wire n22;
  wire n23;
  wire n24;
  wire n28;
  wire n4;
  wire n8;
  wire n9;
  wire rst_n;

  add_pu25_pu25_o25 add0 (
    .i0(cnt),
    .i1(25'b0000000000000000000000001),
    .o(n2));
  add_pu4_pu4_o4 add1 (
    .i0(sm_bit1_num),
    .i1(4'b0001),
    .o(n5));
  add_pu4_pu4_o4 add2 (
    .i0(sm_bit2_num),
    .i1(4'b0001),
    .o(n10));
  add_pu4_pu4_o4 add3 (
    .i0(sm_bit3_num),
    .i1(4'b0001),
    .o(n17));
  add_pu4_pu4_o4 add4 (
    .i0(sm_bit4_num),
    .i1(4'b0001),
    .o(n25));
  add_pu18_pu18_o18 add5 (
    .i0(cnt_w),
    .i1(18'b000000000000000001),
    .o(n29));
  eq_w25 eq0 (
    .i0(cnt),
    .i1(25'b0001001001001111100000000),
    .o(n1));
  eq_w4 eq1 (
    .i0(sm_bit1_num),
    .i1(4'b1001),
    .o(n4));
  eq_w4 eq2 (
    .i0(sm_bit2_num),
    .i1(4'b1010),
    .o(n9));
  eq_w4 eq3 (
    .i0(sm_bit2_num),
    .i1(4'b1001),
    .o(n13));
  eq_w4 eq4 (
    .i0(sm_bit3_num),
    .i1(4'b1010),
    .o(n16));
  eq_w4 eq5 (
    .i0(sm_bit3_num),
    .i1(4'b1001),
    .o(n20));
  eq_w4 eq6 (
    .i0(sm_bit4_num),
    .i1(4'b1010),
    .o(n24));
  eq_w18 eq7 (
    .i0(cnt_w),
    .i1(18'b111111111111111111),
    .o(n28));
  binary_mux_s1_w25 mux0 (
    .i0(n2),
    .i1(25'b0000000000000000000000000),
    .sel(n1),
    .o(n3));
  binary_mux_s1_w4 mux1 (
    .i0(n5),
    .i1(4'b0000),
    .sel(n4),
    .o(n6));
  binary_mux_s2_w4 mux10 (
    .i0(sm_bit1_num),
    .i1(sm_bit2_num),
    .i2(sm_bit3_num),
    .i3(sm_bit4_num),
    .sel(cnt_w[17:16]),
    .o(n31));
  binary_mux_s2_w4 mux11 (
    .i0(4'b1110),
    .i1(4'b1101),
    .i2(4'b1011),
    .i3(4'b0111),
    .sel(cnt_w[17:16]),
    .o(n32));
  binary_mux_s4_w8 mux12 (
    .i0(8'b11000000),
    .i1(8'b11111001),
    .i10(8'b11000000),
    .i11(8'b11000000),
    .i12(8'b11000000),
    .i13(8'b11000000),
    .i14(8'b11000000),
    .i15(8'b11000000),
    .i2(8'b10100100),
    .i3(8'b10110000),
    .i4(8'b10011001),
    .i5(8'b10010010),
    .i6(8'b10000010),
    .i7(8'b11111000),
    .i8(8'b10000000),
    .i9(8'b10010000),
    .sel(sm_seg_num),
    .o(sm_seg_reg));
  binary_mux_s1_w4 mux2 (
    .i0(sm_bit1_num),
    .i1(n6),
    .sel(n1),
    .o(n7));
  binary_mux_s1_w4 mux3 (
    .i0(n10),
    .i1(4'b0000),
    .sel(n9),
    .o(n11));
  binary_mux_s1_w4 mux4 (
    .i0(sm_bit2_num),
    .i1(n11),
    .sel(n8),
    .o(n12));
  binary_mux_s1_w4 mux5 (
    .i0(n17),
    .i1(4'b0000),
    .sel(n16),
    .o(n18));
  binary_mux_s1_w4 mux6 (
    .i0(sm_bit3_num),
    .i1(n18),
    .sel(n15),
    .o(n19));
  binary_mux_s1_w4 mux7 (
    .i0(n25),
    .i1(4'b0000),
    .sel(n24),
    .o(n26));
  binary_mux_s1_w4 mux8 (
    .i0(sm_bit4_num),
    .i1(n26),
    .sel(n23),
    .o(n27));
  binary_mux_s1_w18 mux9 (
    .i0(n29),
    .i1(18'b000000000000000000),
    .sel(n28),
    .o(n30));
  reg_ar_as_w4 reg0 (
    .clk(clk_24m),
    .d(n7),
    .reset({n0,n0,n0,n0}),
    .set(4'b0000),
    .q(sm_bit1_num));
  reg_ar_as_w4 reg1 (
    .clk(clk_24m),
    .d(n12),
    .reset({n0,n0,n0,n0}),
    .set(4'b0000),
    .q(sm_bit2_num));
  reg_ar_as_w4 reg2 (
    .clk(clk_24m),
    .d(n19),
    .reset({n0,n0,n0,n0}),
    .set(4'b0000),
    .q(sm_bit3_num));
  reg_ar_as_w4 reg3 (
    .clk(clk_24m),
    .d(n27),
    .reset({n0,n0,n0,n0}),
    .set(4'b0000),
    .q(sm_bit4_num));
  reg_ar_as_w18 reg4 (
    .clk(clk_24m),
    .d(n30),
    .reset({n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0}),
    .set(18'b000000000000000000),
    .q(cnt_w));
  reg_ar_as_w4 reg5 (
    .clk(clk_24m),
    .d(n31),
    .reset({n0,n0,n0,n0}),
    .set(4'b0000),
    .q(sm_seg_num));
  reg_ar_as_w25 reg6 (
    .clk(clk_24m),
    .d(n3),
    .reset({n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0}),
    .set(25'b0000000000000000000000000),
    .q(cnt));
  reg_ar_as_w4 reg7 (
    .clk(clk_24m),
    .d(n32),
    .reset(4'b0000),
    .set({n0,n0,n0,n0}),
    .q(sm_bit_reg));
  buf u10 (sm_seg[3], sm_seg_reg[3]);
  and u11 (n21, n1, n20);
  buf u12 (sm_seg[2], sm_seg_reg[2]);
  and u13 (n22, n21, n13);
  buf u14 (sm_seg[1], sm_seg_reg[1]);
  and u15 (n23, n22, n4);
  buf u16 (sm_bit[3], sm_bit_reg[3]);
  buf u17 (sm_bit[2], sm_bit_reg[2]);
  buf u18 (sm_bit[1], sm_bit_reg[1]);
  buf u19 (sm_bit[0], sm_bit_reg[0]);
  not u2 (n0, rst_n);
  buf u20 (sm_seg[0], sm_seg_reg[0]);
  and u3 (n8, n1, n4);
  buf u4 (sm_seg[7], sm_seg_reg[7]);
  buf u5 (sm_seg[6], sm_seg_reg[6]);
  and u6 (n14, n1, n13);
  buf u7 (sm_seg[5], sm_seg_reg[5]);
  and u8 (n15, n14, n4);
  buf u9 (sm_seg[4], sm_seg_reg[4]);
  rst_n ux_rst (
    .clk(clk_24m),
    .rst_n(rst_n));

endmodule
module seg4
  (
  clk_24m,
  sm_bit,
  sm_seg
  );


  input clk_24m;
  output [3:0] sm_bit;
  output [7:0] sm_seg;

  parameter CNT_TIME = 2400000;










  wire [24:0] cnt;
  wire [17:0] cnt_w;
  wire [3:0] n10;
  wire [3:0] n11;
  wire [3:0] n12;
  wire [3:0] n17;
  wire [3:0] n18;
  wire [3:0] n19;
  wire [24:0] n2;
  wire [3:0] n25;
  wire [3:0] n26;
  wire [3:0] n27;
  wire [17:0] n29;
  wire [24:0] n3;
  wire [17:0] n30;
  wire [3:0] n31;
  wire [3:0] n32;
  wire [3:0] n5;
  wire [3:0] n6;
  wire [3:0] n7;
  wire [3:0] sm_bit1_num;
  wire [3:0] sm_bit2_num;
  wire [3:0] sm_bit3_num;
  wire [3:0] sm_bit4_num;
  wire [3:0] sm_bit_reg;
  wire [3:0] sm_seg_num;
  wire [7:0] sm_seg_reg;
  wire n0;
  wire n1;
  wire n13;
  wire n14;
  wire n15;
  wire n16;
  wire n20;
  wire n21;
  wire n22;
  wire n23;
  wire n24;
  wire n28;
  wire n4;
  wire n8;
  wire n9;
  wire rst_n;

  add_pu25_pu25_o25 add0 (
    .i0(cnt),
    .i1(25'b0000000000000000000000001),
    .o(n2));
  add_pu4_pu4_o4 add1 (
    .i0(sm_bit1_num),
    .i1(4'b0001),
    .o(n5));
  add_pu4_pu4_o4 add2 (
    .i0(sm_bit2_num),
    .i1(4'b0001),
    .o(n10));
  add_pu4_pu4_o4 add3 (
    .i0(sm_bit3_num),
    .i1(4'b0001),
    .o(n17));
  add_pu4_pu4_o4 add4 (
    .i0(sm_bit4_num),
    .i1(4'b0001),
    .o(n25));
  add_pu18_pu18_o18 add5 (
    .i0(cnt_w),
    .i1(18'b000000000000000001),
    .o(n29));
  eq_w25 eq0 (
    .i0(cnt),
    .i1(25'b0001001001001111100000000),
    .o(n1));
  eq_w4 eq1 (
    .i0(sm_bit1_num),
    .i1(4'b1001),
    .o(n4));
  eq_w4 eq2 (
    .i0(sm_bit2_num),
    .i1(4'b1010),
    .o(n9));
  eq_w4 eq3 (
    .i0(sm_bit2_num),
    .i1(4'b1001),
    .o(n13));
  eq_w4 eq4 (
    .i0(sm_bit3_num),
    .i1(4'b1010),
    .o(n16));
  eq_w4 eq5 (
    .i0(sm_bit3_num),
    .i1(4'b1001),
    .o(n20));
  eq_w4 eq6 (
    .i0(sm_bit4_num),
    .i1(4'b1010),
    .o(n24));
  eq_w18 eq7 (
    .i0(cnt_w),
    .i1(18'b111111111111111111),
    .o(n28));
  binary_mux_s1_w25 mux0 (
    .i0(n2),
    .i1(25'b0000000000000000000000000),
    .sel(n1),
    .o(n3));
  binary_mux_s1_w4 mux1 (
    .i0(n5),
    .i1(4'b0000),
    .sel(n4),
    .o(n6));
  binary_mux_s2_w4 mux10 (
    .i0(sm_bit1_num),
    .i1(sm_bit2_num),
    .i2(sm_bit3_num),
    .i3(sm_bit4_num),
    .sel(cnt_w[17:16]),
    .o(n31));
  binary_mux_s2_w4 mux11 (
    .i0(4'b1110),
    .i1(4'b1101),
    .i2(4'b1011),
    .i3(4'b0111),
    .sel(cnt_w[17:16]),
    .o(n32));
  binary_mux_s4_w8 mux12 (
    .i0(8'b11000000),
    .i1(8'b11111001),
    .i10(8'b11000000),
    .i11(8'b11000000),
    .i12(8'b11000000),
    .i13(8'b11000000),
    .i14(8'b11000000),
    .i15(8'b11000000),
    .i2(8'b10100100),
    .i3(8'b10110000),
    .i4(8'b10011001),
    .i5(8'b10010010),
    .i6(8'b10000010),
    .i7(8'b11111000),
    .i8(8'b10000000),
    .i9(8'b10010000),
    .sel(sm_seg_num),
    .o(sm_seg_reg));
  binary_mux_s1_w4 mux2 (
    .i0(sm_bit1_num),
    .i1(n6),
    .sel(n1),
    .o(n7));
  binary_mux_s1_w4 mux3 (
    .i0(n10),
    .i1(4'b0000),
    .sel(n9),
    .o(n11));
  binary_mux_s1_w4 mux4 (
    .i0(sm_bit2_num),
    .i1(n11),
    .sel(n8),
    .o(n12));
  binary_mux_s1_w4 mux5 (
    .i0(n17),
    .i1(4'b0000),
    .sel(n16),
    .o(n18));
  binary_mux_s1_w4 mux6 (
    .i0(sm_bit3_num),
    .i1(n18),
    .sel(n15),
    .o(n19));
  binary_mux_s1_w4 mux7 (
    .i0(n25),
    .i1(4'b0000),
    .sel(n24),
    .o(n26));
  binary_mux_s1_w4 mux8 (
    .i0(sm_bit4_num),
    .i1(n26),
    .sel(n23),
    .o(n27));
  binary_mux_s1_w18 mux9 (
    .i0(n29),
    .i1(18'b000000000000000000),
    .sel(n28),
    .o(n30));
  reg_ar_as_w4 reg0 (
    .clk(clk_24m),
    .d(n7),
    .reset({n0,n0,n0,n0}),
    .set(4'b0000),
    .q(sm_bit1_num));
  reg_ar_as_w4 reg1 (
    .clk(clk_24m),
    .d(n12),
    .reset({n0,n0,n0,n0}),
    .set(4'b0000),
    .q(sm_bit2_num));
  reg_ar_as_w4 reg2 (
    .clk(clk_24m),
    .d(n19),
    .reset({n0,n0,n0,n0}),
    .set(4'b0000),
    .q(sm_bit3_num));
  reg_ar_as_w4 reg3 (
    .clk(clk_24m),
    .d(n27),
    .reset({n0,n0,n0,n0}),
    .set(4'b0000),
    .q(sm_bit4_num));
  reg_ar_as_w18 reg4 (
    .clk(clk_24m),
    .d(n30),
    .reset({n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0}),
    .set(18'b000000000000000000),
    .q(cnt_w));
  reg_ar_as_w4 reg5 (
    .clk(clk_24m),
    .d(n31),
    .reset({n0,n0,n0,n0}),
    .set(4'b0000),
    .q(sm_seg_num));
  reg_ar_as_w25 reg6 (
    .clk(clk_24m),
    .d(n3),
    .reset({n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0}),
    .set(25'b0000000000000000000000000),
    .q(cnt));
  reg_ar_as_w4 reg7 (
    .clk(clk_24m),
    .d(n32),
    .reset(4'b0000),
    .set({n0,n0,n0,n0}),
    .q(sm_bit_reg));
  buf u10 (sm_seg[3], sm_seg_reg[3]);
  and u11 (n21, n1, n20);
  buf u12 (sm_seg[2], sm_seg_reg[2]);
  and u13 (n22, n21, n13);
  buf u14 (sm_seg[1], sm_seg_reg[1]);
  and u15 (n23, n22, n4);
  buf u16 (sm_bit[3], sm_bit_reg[3]);
  buf u17 (sm_bit[2], sm_bit_reg[2]);
  buf u18 (sm_bit[1], sm_bit_reg[1]);
  buf u19 (sm_bit[0], sm_bit_reg[0]);
  not u2 (n0, rst_n);
  buf u20 (sm_seg[0], sm_seg_reg[0]);
  and u3 (n8, n1, n4);
  buf u4 (sm_seg[7], sm_seg_reg[7]);
  buf u5 (sm_seg[6], sm_seg_reg[6]);
  and u6 (n14, n1, n13);
  buf u7 (sm_seg[5], sm_seg_reg[5]);
  and u8 (n15, n14, n4);
  buf u9 (sm_seg[4], sm_seg_reg[4]);
  rst_n ux_rst (
    .clk(clk_24m),
    .rst_n(rst_n));

endmodule