data/full_repos/permissive/133043770/sineWaveExampleTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/133043770/sineWaveExampleTest.v:40: Unsupported: Ignoring delay on this delayed statement.\n    always #5 Clk = ~Clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/133043770/sineWaveExampleTest.v:33: Cannot find file containing module: \'sine_wave_gen\'\n    sine_wave_gen uut (\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133043770,data/full_repos/permissive/133043770/sine_wave_gen\n             data/full_repos/permissive/133043770,data/full_repos/permissive/133043770/sine_wave_gen.v\n             data/full_repos/permissive/133043770,data/full_repos/permissive/133043770/sine_wave_gen.sv\n             sine_wave_gen\n             sine_wave_gen.v\n             sine_wave_gen.sv\n             obj_dir/sine_wave_gen\n             obj_dir/sine_wave_gen.v\n             obj_dir/sine_wave_gen.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sineWaveExampleTest;

    reg Clk;


    wire [7:0] data_out;


    sine_wave_gen uut (
        .Clk(Clk), 
        .data_out(data_out)
    );


    initial Clk = 0;
    always #5 Clk = ~Clk;
    
endmodule
module sineWaveExampleTest;


    reg Clk;


    wire [7:0] data_out;


    sine_wave_gen uut (
        .Clk(Clk), 
        .data_out(data_out)
    );


    initial Clk = 0;
    always #5 Clk = ~Clk;
    
endmodule