data/full_repos/permissive/184916587/IMemory.v
1: b"%Error: data/full_repos/permissive/184916587/IMemory.v:16: Duplicate declaration of signal: 'instr'\n                                                         : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg[31:0] instr;\n           ^~~~~\n        data/full_repos/permissive/184916587/IMemory.v:9: ... Location of original declaration\n output[31:0] instr\n              ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module IMemory(
	input[31:0] address,
	output[31:0] instr
);

	reg[31:0] instr1=32'b00000000001000001110010010110011;
	reg[31:0] instr2=32'b01000000000100010000000110110011;
	reg[31:0] instr3=32'b00000000110000111010000010110011;

	reg[31:0] instr;

	always @(*)
	begin
		if(address===0) begin
			instr=instr1;
		end
		else if(address===4) begin
			instr=instr2;
		end
		else if(address===8) begin
			instr=instr3;
		end
	end
endmodule
module IMemory(
	input[31:0] address,
	output[31:0] instr
);


	reg[31:0] instr1=32'b00000000001000001110010010110011;
	reg[31:0] instr2=32'b01000000000100010000000110110011;
	reg[31:0] instr3=32'b00000000110000111010000010110011;

	reg[31:0] instr;

	always @(*)
	begin
		if(address===0) begin
			instr=instr1;
		end
		else if(address===4) begin
			instr=instr2;
		end
		else if(address===8) begin
			instr=instr3;
		end
	end
endmodule