data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v
1: b'%Error: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:11: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("fsm111.vcd"); \n^~~~~~~~~\n%Error: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:12: Unsupported or unknown PLI call: $dumpvars\n$dumpvars; \n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:17: Unsupported: Ignoring delay on this delayed statement.\n#00 clk <= 1\'b0 ; \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:18: Unsupported: Ignoring delay on this delayed statement.\nforever #50 clk <= ~ clk ; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:21: Unsupported: Ignoring delay on this delayed statement.\ninitial forever #100 in = $random %2 ; \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:25: Unsupported: Ignoring delay on this delayed statement.\n#0000 rst = 1\'b1; #0050 rst = 1\'b0; #0050 rst = 1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:25: Unsupported: Ignoring delay on this delayed statement.\n#0000 rst = 1\'b1; #0050 rst = 1\'b0; #0050 rst = 1\'b1; \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:25: Unsupported: Ignoring delay on this delayed statement.\n#0000 rst = 1\'b1; #0050 rst = 1\'b0; #0050 rst = 1\'b1; \n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:26: Unsupported: Ignoring delay on this delayed statement.\n#2000 rst = 1\'b0; #0050 rst = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Lab4_FSM_Modelling/fsm111.v:26: Unsupported: Ignoring delay on this delayed statement.\n#2000 rst = 1\'b0; #0050 rst = 1\'b1;\n                  ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_fsm111();

reg in , clk , rst ; 
wire out ; 

fsm111 uut (.z(out) ,.y(in) ,.clk(clk),.rst(rst));

initial 
begin 
$dumpfile("fsm111.vcd"); 
$dumpvars; 
end

initial 
begin 
#00 clk <= 1'b0 ; 
forever #50 clk <= ~ clk ; 
end

initial forever #100 in = $random %2 ; 

initial 
begin 
#0000 rst = 1'b1; #0050 rst = 1'b0; #0050 rst = 1'b1; 
#2000 rst = 1'b0; #0050 rst = 1'b1;
end 
endmodule
module tb_fsm111();


reg in , clk , rst ; 
wire out ; 

fsm111 uut (.z(out) ,.y(in) ,.clk(clk),.rst(rst));

initial 
begin 
$dumpfile("fsm111.vcd"); 
$dumpvars; 
end

initial 
begin 
#00 clk <= 1'b0 ; 
forever #50 clk <= ~ clk ; 
end

initial forever #100 in = $random %2 ; 

initial 
begin 
#0000 rst = 1'b1; #0050 rst = 1'b0; #0050 rst = 1'b1; 
#2000 rst = 1'b0; #0050 rst = 1'b1;
end 
endmodule