data/full_repos/permissive/185451826/4.state_machine/detect_2.v
1: b'%Error: data/full_repos/permissive/185451826/4.state_machine/detect_2.v:30: Can\'t find definition of variable: \'Currnet_state\'\n                                                                          : ... Suggested alternative: \'Current_state\'\n      case(Currnet_state)\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/185451826/4.state_machine/detect_2.v:32: Can\'t find definition of variable: \'out_t\'\n                                                                          : ... Suggested alternative: \'out_o\'\n    out_t = 1\'b0;\n    ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/185451826/4.state_machine/detect_2.v:50: Signal definition not found, creating implicitly: \'_out_o\'\n                                                                                     : ... Suggested alternative: \'out_o\'\n  assign _out_o = out_r;\n         ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module detect_2(
		input clk_i,
		input rst_n_i,
		output out_o
		);
   reg 		       out_r;


   reg [1:0] 	       Current_state;
   reg [1:0] 	       Next_state;

   parameter [1:0] S0 = 2'b00;
   parameter [1:0] S1 = 2'b01;
   parameter [1:0] S2 = 2'b10;
   parameter [1:0] S3 = 2'b11;


   always@(posedge clk_i or negedge rst_n_i) begin
      if(!rst_n_i) begin
	 Current_state <= 0;
      end
      else begin
	 Current_state <= Next_state;
      end
   end


   always@(*) begin
      out_r = 1'b0;
      case(Currnet_state)
	S0: begin
	   out_t = 1'b0;
	   Next_state = S1;
	end
	S1: begin
	   out_t = 1'b1;
	   Next_state = S2;
	end
	S2: begin
	   out_t = 1'b0;
	   Next_state = S3;
	end
	S3: begin
	   out_t = 1'b1;
	   Next_state = Next_state;
	end
      endcase
   end

  assign _out_o = out_r;
endmodule
module detect_2(
		input clk_i,
		input rst_n_i,
		output out_o
		);

   reg 		       out_r;


   reg [1:0] 	       Current_state;
   reg [1:0] 	       Next_state;

   parameter [1:0] S0 = 2'b00;
   parameter [1:0] S1 = 2'b01;
   parameter [1:0] S2 = 2'b10;
   parameter [1:0] S3 = 2'b11;


   always@(posedge clk_i or negedge rst_n_i) begin
      if(!rst_n_i) begin
	 Current_state <= 0;
      end
      else begin
	 Current_state <= Next_state;
      end
   end


   always@(*) begin
      out_r = 1'b0;
      case(Currnet_state)
	S0: begin
	   out_t = 1'b0;
	   Next_state = S1;
	end
	S1: begin
	   out_t = 1'b1;
	   Next_state = S2;
	end
	S2: begin
	   out_t = 1'b0;
	   Next_state = S3;
	end
	S3: begin
	   out_t = 1'b1;
	   Next_state = Next_state;
	end
      endcase
   end

  assign _out_o = out_r;
endmodule