data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/Write_Master/byte_enable_generator.v
data/verilator_xmls/8eeda7c9-42e4-4030-9ffd-e44cfef86957.xml
module two_hundred_fifty_six_bit_byteenable_FSM (
  clk,
  reset,

  write_in,
  byteenable_in,
  waitrequest_out,

  byteenable_out,
  waitrequest_in
);


  input clk;
  input reset;

  input write_in;
  input [31:0] byteenable_in;
  output wire waitrequest_out;

  output wire [31:0] byteenable_out; 
  input waitrequest_in;



  wire partial_lower_half_transfer;
  wire full_lower_half_transfer;
  wire partial_upper_half_transfer;
  wire full_upper_half_transfer;
  wire full_word_transfer;
  reg state_bit;
  wire transfer_done;
  wire advance_to_next_state;
  wire lower_enable;
  wire upper_enable;
  wire lower_stall;
  wire upper_stall;
  wire two_stage_transfer;


  always @ (posedge clk or posedge reset)
  begin
    if (reset)
    begin
      state_bit <= 0;
    end
    else
    begin
      if (transfer_done == 1)
      begin
        state_bit <= 0;
      end
      else if (advance_to_next_state == 1)
      begin
        state_bit <= 1;
      end
    end
  end

  assign partial_lower_half_transfer = (byteenable_in[15:0] != 0);
  assign full_lower_half_transfer = (byteenable_in[15:0] == 16'hFFFF);
  assign partial_upper_half_transfer = (byteenable_in[31:16] != 0);
  assign full_upper_half_transfer = (byteenable_in[31:16] == 16'hFFFF);
  assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
  assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);

  assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0);

  assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) |
                         ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) |
                         ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0));

  assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) |
                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) |
                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0));

  assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) |
                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) |
                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1));

  one_hundred_twenty_eight_bit_byteenable_FSM lower_one_hundred_twenty_eight_bit_byteenable_FSM (
    .clk (clk),
    .reset (reset),
    .write_in (lower_enable),
    .byteenable_in (byteenable_in[15:0]),
    .waitrequest_out (lower_stall),    
    .byteenable_out (byteenable_out[15:0]),
    .waitrequest_in (waitrequest_in)
  );

  one_hundred_twenty_eight_bit_byteenable_FSM upper_one_hundred_twenty_eight_bit_byteenable_FSM (
    .clk (clk),
    .reset (reset),
    .write_in (upper_enable),
    .byteenable_in (byteenable_in[31:16]),
    .waitrequest_out (upper_stall),    
    .byteenable_out (byteenable_out[31:16]),
    .waitrequest_in (waitrequest_in)
  );

  assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));

endmodule
module two_hundred_fifty_six_bit_byteenable_FSM (
  clk,
  reset,

  write_in,
  byteenable_in,
  waitrequest_out,

  byteenable_out,
  waitrequest_in
);



  input clk;
  input reset;

  input write_in;
  input [31:0] byteenable_in;
  output wire waitrequest_out;

  output wire [31:0] byteenable_out; 
  input waitrequest_in;



  wire partial_lower_half_transfer;
  wire full_lower_half_transfer;
  wire partial_upper_half_transfer;
  wire full_upper_half_transfer;
  wire full_word_transfer;
  reg state_bit;
  wire transfer_done;
  wire advance_to_next_state;
  wire lower_enable;
  wire upper_enable;
  wire lower_stall;
  wire upper_stall;
  wire two_stage_transfer;


  always @ (posedge clk or posedge reset)
  begin
    if (reset)
    begin
      state_bit <= 0;
    end
    else
    begin
      if (transfer_done == 1)
      begin
        state_bit <= 0;
      end
      else if (advance_to_next_state == 1)
      begin
        state_bit <= 1;
      end
    end
  end

  assign partial_lower_half_transfer = (byteenable_in[15:0] != 0);
  assign full_lower_half_transfer = (byteenable_in[15:0] == 16'hFFFF);
  assign partial_upper_half_transfer = (byteenable_in[31:16] != 0);
  assign full_upper_half_transfer = (byteenable_in[31:16] == 16'hFFFF);
  assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
  assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);

  assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0);

  assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) |
                         ((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) |
                         ((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0));

  assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) |
                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) |
                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0));

  assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) |
                        ((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) |
                        ((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1));

  one_hundred_twenty_eight_bit_byteenable_FSM lower_one_hundred_twenty_eight_bit_byteenable_FSM (
    .clk (clk),
    .reset (reset),
    .write_in (lower_enable),
    .byteenable_in (byteenable_in[15:0]),
    .waitrequest_out (lower_stall),    
    .byteenable_out (byteenable_out[15:0]),
    .waitrequest_in (waitrequest_in)
  );

  one_hundred_twenty_eight_bit_byteenable_FSM upper_one_hundred_twenty_eight_bit_byteenable_FSM (
    .clk (clk),
    .reset (reset),
    .write_in (upper_enable),
    .byteenable_in (byteenable_in[31:16]),
    .waitrequest_out (upper_stall),    
    .byteenable_out (byteenable_out[31:16]),
    .waitrequest_in (waitrequest_in)
  );

  assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));

endmodule