data/full_repos/permissive/185824253/rtl/myCPU/32bit_cla_adder.v
data/verilator_xmls/ad288fc4-cad0-4feb-8db5-3fd9730c9278.xml
module cla_4(
	input  [3:0] g,
	input  [3:0] p,
	input        cin,
	output [2:0] carry_out,
	output       D,
	output       T
	);
	assign carry_out[0] = g[0] | p[0]&cin;
	assign carry_out[1] = g[1] | p[1]&g[0] | p[1]&p[0]&cin;
	assign carry_out[2] = g[2] | p[2]&g[1] | p[2]&p[1]&g[0] | p[2]&p[1]&p[0]&cin;
	assign D            = g[3] | p[3]&g[2] | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0];
	assign T = p[3]&p[2]&p[1]&p[0];
endmodule
module cla_4(
	input  [3:0] g,
	input  [3:0] p,
	input        cin,
	output [2:0] carry_out,
	output       D,
	output       T
	);

	assign carry_out[0] = g[0] | p[0]&cin;
	assign carry_out[1] = g[1] | p[1]&g[0] | p[1]&p[0]&cin;
	assign carry_out[2] = g[2] | p[2]&g[1] | p[2]&p[1]&g[0] | p[2]&p[1]&p[0]&cin;
	assign D            = g[3] | p[3]&g[2] | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0];
	assign T = p[3]&p[2]&p[1]&p[0];
endmodule