data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/probador.v
 line:96: before: "("
1: b'%Error: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/probador.v:9: Cannot find include file: checker_sumador.v\n`include "checker_sumador.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline,data/full_repos/permissive/178052224/checker_sumador.v\n             data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline,data/full_repos/permissive/178052224/checker_sumador.v.v\n             data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline,data/full_repos/permissive/178052224/checker_sumador.v.sv\n             checker_sumador.v\n             checker_sumador.v.v\n             checker_sumador.v.sv\n             obj_dir/checker_sumador.v\n             obj_dir/checker_sumador.v.v\n             obj_dir/checker_sumador.v.sv\n%Error: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/probador.v:39: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("sumador.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/probador.v:40: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/probador.v:43: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/probador.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #1; \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/probador.v:50: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/probador.v:54: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea9/mod_y_pipeline/probador.v:66: Unsupported: Ignoring delay on this delayed statement.\n    always #2 clk <=~clk;\n           ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n'
module probador(
    output reg          clk,
    output reg          reset_L,
    output reg  [3:0]   idx,
    output reg  [3:0]   dataA,
    output reg  [3:0]   dataB,
    input       [3:0]   idx_dd_cond,
    input       [3:0]   idx_dd_estruc,
    input       [3:0]   sum30_dd_cond,
    input       [3:0]   sum30_dd_estruc);





    
   checker_sumador sum_check(

			     .sumador_checks_out(sumador_checks_out),

			     .clk		(clk),
			     .reset_L		(reset_L),
			     .salida_sumador_c	(sum30_dd_cond[3:0]),
			     .salida_sumador_e	(sum30_dd_estruc[3:0]));


    initial begin
        $dumpfile("sumador.vcd");
        $dumpvars;
        

        @(posedge clk);
        reset_L <= 0;
        dataA <= 0;
        dataB <= 0;
        idx   <= 0;

        #1; 
        @(posedge clk);
        reset_L <= 1;
        
        repeat(20) begin
        @(posedge clk);
            dataA <= dataA + 1;
            dataB <= dataB + 1;
            idx <= idx + 1;
        end
        $finish;    
   end

    initial begin
    clk <=0;
    end

    always #2 clk <=~clk;


endmodule
module probador(
    output reg          clk,
    output reg          reset_L,
    output reg  [3:0]   idx,
    output reg  [3:0]   dataA,
    output reg  [3:0]   dataB,
    input       [3:0]   idx_dd_cond,
    input       [3:0]   idx_dd_estruc,
    input       [3:0]   sum30_dd_cond,
    input       [3:0]   sum30_dd_estruc);






    
   checker_sumador sum_check(

			     .sumador_checks_out(sumador_checks_out),

			     .clk		(clk),
			     .reset_L		(reset_L),
			     .salida_sumador_c	(sum30_dd_cond[3:0]),
			     .salida_sumador_e	(sum30_dd_estruc[3:0]));


    initial begin
        $dumpfile("sumador.vcd");
        $dumpvars;
        

        @(posedge clk);
        reset_L <= 0;
        dataA <= 0;
        dataB <= 0;
        idx   <= 0;

        #1; 
        @(posedge clk);
        reset_L <= 1;
        
        repeat(20) begin
        @(posedge clk);
            dataA <= dataA + 1;
            dataB <= dataB + 1;
            idx <= idx + 1;
        end
        $finish;    
   end

    initial begin
    clk <=0;
    end

    always #2 clk <=~clk;


endmodule