data/full_repos/permissive/206301883/start_tx.v
data/verilator_xmls/6f9f7a93-e34c-4df8-973d-4eb380a61b2d.xml
module start_tx(
input clk,
output  tx_start
    );
reg [32:0]count=0;
reg temp=0;
reg done = 0;
assign tx_start = temp;

always @(posedge clk)
begin
    if (done == 0) begin
        if (count == 10000000) begin
            temp <= 1;
            count <= 0;
            done <=1;
        end
        else begin
            count <= count +1;

        end
    end
    else begin temp <=0; end
end
endmodule
module start_tx(
input clk,
output  tx_start
    );

reg [32:0]count=0;
reg temp=0;
reg done = 0;
assign tx_start = temp;

always @(posedge clk)
begin
    if (done == 0) begin
        if (count == 10000000) begin
            temp <= 1;
            count <= 0;
            done <=1;
        end
        else begin
            count <= count +1;

        end
    end
    else begin temp <=0; end
end
endmodule