data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/p_SSYNC2DO_C_PP.v
data/verilator_xmls/f3dae3df-8731-484e-90c5-1906321dcf64.xml
module p_SSYNC2DO_C_PP (
  clk
 ,d
 ,clr_
 ,q
 );


input clk ;
input d ;
input clr_ ;
output q ;
reg q,d0;
always @(posedge clk or negedge clr_)
begin
    if(~clr_)
        {q,d0} <= 2'd0;
    else
        {q,d0} <= {d0,d};
end
endmodule
module p_SSYNC2DO_C_PP (
  clk
 ,d
 ,clr_
 ,q
 );



input clk ;
input d ;
input clr_ ;
output q ;
reg q,d0;
always @(posedge clk or negedge clr_)
begin
    if(~clr_)
        {q,d0} <= 2'd0;
    else
        {q,d0} <= {d0,d};
end
endmodule