data/full_repos/permissive/20662519/Servo.v
 line:49 column:16: Illegal character "'"
1: b'%Warning-WIDTH: data/full_repos/permissive/20662519/Servo.v:42: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                              : ... In instance Servo\nassign speed = data[POSITION_DATA_LEN+:SPEED_DATA_LEN-1]; \n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20662519/Servo.v:43: Operator ITORD expects 32 bits on the LHS, but LHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance Servo\nassign freq = CLK_FREQUENCY*(speed/1000.0); \n                             ^~~~~\n%Warning-REALCVT: data/full_repos/permissive/20662519/Servo.v:43: Implicit conversion of real to integer\nassign freq = CLK_FREQUENCY*(speed/1000.0); \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/20662519/Servo.v:54: Operator NEQ expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'address\' generates 8 bits.\n                                                              : ... In instance Servo\n      if(address!=MAX_RAM_POS-1)begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/20662519/Servo.v:65: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 7 bits.\n                                                              : ... In instance Servo\nassign pos = data[0+:POSITION_DATA_LEN-1];\n           ^\n%Warning-SELRANGE: data/full_repos/permissive/20662519/Servo.v:67: Selection index out of range: 27:8 outside 20:0\n                                                                 : ... In instance Servo\nassign pulseCount = ctr[8+:CTR_LEN-1]; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/20662519/Servo.v:67: Operator ASSIGNW expects 13 bits on the Assign RHS, but Assign RHS\'s SEL generates 20 bits.\n                                                              : ... In instance Servo\nassign pulseCount = ctr[8+:CTR_LEN-1]; \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/20662519/Servo.v:70: Operator ADD expects 13 bits on the LHS, but LHS\'s VARREF \'pos\' generates 8 bits.\n                                                              : ... In instance Servo\n  servo_q = pulseCount < (pos + 9\'d165) ;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/20662519/Servo.v:70: Operator ADD expects 13 bits on the RHS, but RHS\'s CONST \'9\'ha5\' generates 9 bits.\n                                                              : ... In instance Servo\n  servo_q = pulseCount < (pos + 9\'d165) ;\n                              ^\n%Error: Exiting due to 9 warning(s)\n'
module Servo #(
  parameter CLK_FREQUENCY = 50000000,
  parameter VALUE_SCALING = 256,
  parameter CTR_LEN = 21,
  parameter SPEED_DATA_LEN = 5,
  parameter POSITION_DATA_LEN = 8,  
  parameter ADDR_LEN = 8,
  parameter MAX_RAM_POS = 256,
  parameter DATA_LEN = 13
)(
input  clk,
input  rst,
input  [DATA_LEN-1:0] data,
output reg [ADDR_LEN-1:0] address,
output reg servo_q
);

wire[CTR_LEN-1:0] freq;
wire[SPEED_DATA_LEN-1:0] speed;

assign speed = data[POSITION_DATA_LEN+:SPEED_DATA_LEN-1];
assign freq = CLK_FREQUENCY*(speed/1000.0);


reg[CTR_LEN-1:0] ctr;
always@(posedge clk)begin
  if(rst)begin
    address<= '0;
    ctr <= '0;
  end else begin
    ctr = ctr + 1'b1;
    if(ctr>=freq )begin
      if(address!=MAX_RAM_POS-1)begin
        address <= address+1'b1;
      end
      ctr = '0;
    end
  end
end


wire[POSITION_DATA_LEN-1:0] pos;
wire[CTR_LEN-1-8:0] pulseCount ;
assign pos = data[0+:POSITION_DATA_LEN-1];

assign pulseCount = ctr[8+:CTR_LEN-1];

always @(posedge clk) begin
  servo_q = pulseCount < (pos + 9'd165) ;

end

endmodule
module Servo #(
  parameter CLK_FREQUENCY = 50000000,
  parameter VALUE_SCALING = 256,
  parameter CTR_LEN = 21,
  parameter SPEED_DATA_LEN = 5,
  parameter POSITION_DATA_LEN = 8,  
  parameter ADDR_LEN = 8,
  parameter MAX_RAM_POS = 256,
  parameter DATA_LEN = 13
)(
input  clk,
input  rst,
input  [DATA_LEN-1:0] data,
output reg [ADDR_LEN-1:0] address,
output reg servo_q
);


wire[CTR_LEN-1:0] freq;
wire[SPEED_DATA_LEN-1:0] speed;

assign speed = data[POSITION_DATA_LEN+:SPEED_DATA_LEN-1];
assign freq = CLK_FREQUENCY*(speed/1000.0);


reg[CTR_LEN-1:0] ctr;
always@(posedge clk)begin
  if(rst)begin
    address<= '0;
    ctr <= '0;
  end else begin
    ctr = ctr + 1'b1;
    if(ctr>=freq )begin
      if(address!=MAX_RAM_POS-1)begin
        address <= address+1'b1;
      end
      ctr = '0;
    end
  end
end


wire[POSITION_DATA_LEN-1:0] pos;
wire[CTR_LEN-1-8:0] pulseCount ;
assign pos = data[0+:POSITION_DATA_LEN-1];

assign pulseCount = ctr[8+:CTR_LEN-1];

always @(posedge clk) begin
  servo_q = pulseCount < (pos + 9'd165) ;

end

endmodule