data/full_repos/permissive/10379745/hard/hazard_unit.sv
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1: b'%Warning-MULTITOP: data/full_repos/permissive/10379745/hard/hazard_unit.sv:1: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'hazard_unit\'\nmodule hazard_unit ( if_hazard.hzrd HZRD );\n       ^~~~~~~~~~~\n                                                                            : ... Top module \'if_hazard\'\nmodule hazard_unit ( if_hazard.hzrd HZRD );\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hard/hazard_unit.sv:1: Unsupported: Interfaced port on top level module\nmodule hazard_unit ( if_hazard.hzrd HZRD );\n                                    ^~~~\n%Error: data/full_repos/permissive/10379745/hard/hazard_unit.sv:1: Cannot find file containing interface: \'if_hazard\'\nmodule hazard_unit ( if_hazard.hzrd HZRD );\n                     ^~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/10379745/hard/hazard_unit.sv:1: ../V3LinkDot.cpp:2055: Unlinked interface\nmodule hazard_unit ( if_hazard.hzrd HZRD );\n                     ^~~~~~~~~\n'
module hazard_unit ( if_hazard.hzrd HZRD );



















assign HZRD.ALU_FWD_A = 
   ((HZRD.RS_E != 0) && (HZRD.RS_E == HZRD.REGDST_M ) && HZRD.WRITEREG_M ) ? 2'b01 :
   ((HZRD.RS_E != 0) && (HZRD.RS_E == HZRD.REGDST_W ) && HZRD.WRITEREG_W ) ? 2'b10 :
                                                                             2'b00 ;

assign HZRD.ALU_FWD_B = 
   ((HZRD.RT_E != 0) && (HZRD.RT_E == HZRD.REGDST_M ) && HZRD.WRITEREG_M ) ? 2'b01 :
   ((HZRD.RT_E != 0) && (HZRD.RT_E == HZRD.REGDST_W ) && HZRD.WRITEREG_W ) ? 2'b10 :
                                                                             2'b00 ;



logic lw_stall, mdiv_stall, load_or_mf_at_m, mfhl_at_m;

assign load_or_mf_at_m  = ( HZRD.ALUORMEM_M | mfhl_at_m     ) &
                          ( ( HZRD.RS_E == HZRD.REGDST_M )  | 
                            ( HZRD.RT_E == HZRD.REGDST_M )  );

assign lw_stall = load_or_mf_at_m;




assign mfhl_at_m  = ^HZRD.MFCOP_SEL_M;
assign mdiv_stall = HZRD.MDIV_BUSY_M & mfhl_at_m;

assign HZRD.STALL_FDE = lw_stall | mdiv_stall;
assign HZRD.STALL_M   = mdiv_stall;

assign HZRD.RESET_M   = lw_stall & ~mdiv_stall;
assign HZRD.RESET_W   = mdiv_stall;

endmodule
module hazard_unit ( if_hazard.hzrd HZRD );




















assign HZRD.ALU_FWD_A = 
   ((HZRD.RS_E != 0) && (HZRD.RS_E == HZRD.REGDST_M ) && HZRD.WRITEREG_M ) ? 2'b01 :
   ((HZRD.RS_E != 0) && (HZRD.RS_E == HZRD.REGDST_W ) && HZRD.WRITEREG_W ) ? 2'b10 :
                                                                             2'b00 ;

assign HZRD.ALU_FWD_B = 
   ((HZRD.RT_E != 0) && (HZRD.RT_E == HZRD.REGDST_M ) && HZRD.WRITEREG_M ) ? 2'b01 :
   ((HZRD.RT_E != 0) && (HZRD.RT_E == HZRD.REGDST_W ) && HZRD.WRITEREG_W ) ? 2'b10 :
                                                                             2'b00 ;



logic lw_stall, mdiv_stall, load_or_mf_at_m, mfhl_at_m;

assign load_or_mf_at_m  = ( HZRD.ALUORMEM_M | mfhl_at_m     ) &
                          ( ( HZRD.RS_E == HZRD.REGDST_M )  | 
                            ( HZRD.RT_E == HZRD.REGDST_M )  );

assign lw_stall = load_or_mf_at_m;




assign mfhl_at_m  = ^HZRD.MFCOP_SEL_M;
assign mdiv_stall = HZRD.MDIV_BUSY_M & mfhl_at_m;

assign HZRD.STALL_FDE = lw_stall | mdiv_stall;
assign HZRD.STALL_M   = mdiv_stall;

assign HZRD.RESET_M   = lw_stall & ~mdiv_stall;
assign HZRD.RESET_W   = mdiv_stall;

endmodule