data/full_repos/permissive/184916587/Test_Decode_INST.v
 line:70: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Decode_INST.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #0 inst=32\'b01000000000100010000000110110011;  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Decode_INST.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #5 inst=32\'b00000000001000001110010010110011;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Decode_INST.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #5 inst=32\'b00000000110000111010000010110011;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Decode_INST.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #5 inst=32\'b10000111011000001100110010010011;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Decode_INST.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #5 inst=32\'b00101010110100011000111100000011;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Decode_INST.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #5 inst=32\'b00010101110011100000000011100111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Decode_INST.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #5 inst=32\'b00010101110100010110000101101111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Decode_INST.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #5 inst=32\'b10111111010001011111110010110111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Decode_INST.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #5 inst=32\'b11101110111001001010111100010111;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Decode_INST.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #5 inst=32\'b11100101100111000001000110100011;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Decode_INST.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #5 inst=32\'b11101010000111010110000101100011;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_Decode_INST.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #5 $finish; \n  ^\n%Error: data/full_repos/permissive/184916587/Test_Decode_INST.v:74: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("Decode_INST.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/184916587/Test_Decode_INST.v:75: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,Test_Decoder_INST);\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_Decoder_INST;

	reg[31:0] inst;

	wire[9:0] alu_op;
	wire[4:0] rs1;
	wire[4:0] rs2;
	wire[4:0] rd;
	wire[31:0] address_imm;
	wire[4:0] ls_op;
	wire[4:0] j_op;
	wire[4:0] b_op;

	Decode_INST test_decode_inst(

		.inst(inst),
		.alu_op(alu_op),
		.rs1(rs1),
		.rs2(rs2),
		.rd(rd),
		.address_imm(address_imm),
		.ls_op(ls_op),
		.j_op(j_op),
		.b_op(b_op)
		);

	initial begin
























		#0 inst=32'b01000000000100010000000110110011;
		#5 inst=32'b00000000001000001110010010110011;
		#5 inst=32'b00000000110000111010000010110011;
		#5 inst=32'b10000111011000001100110010010011;
		#5 inst=32'b00101010110100011000111100000011;
		#5 inst=32'b00010101110011100000000011100111;
		#5 inst=32'b00010101110100010110000101101111;
		#5 inst=32'b10111111010001011111110010110111;
		#5 inst=32'b11101110111001001010111100010111;
		#5 inst=32'b11100101100111000001000110100011;
		#5 inst=32'b11101010000111010110000101100011;
		#5 $finish; 
	end

	initial begin
		$dumpfile("Decode_INST.vcd");
		$dumpvars(0,Test_Decoder_INST);
	end

endmodule
module Test_Decoder_INST;


	reg[31:0] inst;

	wire[9:0] alu_op;
	wire[4:0] rs1;
	wire[4:0] rs2;
	wire[4:0] rd;
	wire[31:0] address_imm;
	wire[4:0] ls_op;
	wire[4:0] j_op;
	wire[4:0] b_op;

	Decode_INST test_decode_inst(

		.inst(inst),
		.alu_op(alu_op),
		.rs1(rs1),
		.rs2(rs2),
		.rd(rd),
		.address_imm(address_imm),
		.ls_op(ls_op),
		.j_op(j_op),
		.b_op(b_op)
		);

	initial begin
























		#0 inst=32'b01000000000100010000000110110011;
		#5 inst=32'b00000000001000001110010010110011;
		#5 inst=32'b00000000110000111010000010110011;
		#5 inst=32'b10000111011000001100110010010011;
		#5 inst=32'b00101010110100011000111100000011;
		#5 inst=32'b00010101110011100000000011100111;
		#5 inst=32'b00010101110100010110000101101111;
		#5 inst=32'b10111111010001011111110010110111;
		#5 inst=32'b11101110111001001010111100010111;
		#5 inst=32'b11100101100111000001000110100011;
		#5 inst=32'b11101010000111010110000101100011;
		#5 $finish; 
	end

	initial begin
		$dumpfile("Decode_INST.vcd");
		$dumpvars(0,Test_Decoder_INST);
	end

endmodule