data/full_repos/permissive/191834901/VerilogHDL/mainMemory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/191834901/VerilogHDL/mainMemory.v:20: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'instMemory\'\nmodule instMemory #(parameter instructionW=32, parameter addrW=16) (\n       ^~~~~~~~~~\n                                                                                  : ... Top module \'dataMemory\'\nmodule dataMemory #(parameter dataW=32, parameter addrW=16) (\n       ^~~~~~~~~~\n                                                                                  : ... Top module \'controlPathDriver\'\nmodule controlPathDriver #(parameter controlWordWidth=16, parameter caddrW=16) (\n       ^~~~~~~~~~~~~~~~~\n                                                                                  : ... Top module \'registerFile\'\nmodule registerFile #(parameter dataWidth=32, parameter addrWidth=5) (\n       ^~~~~~~~~~~~\n                                                                                  : ... Top module \'registerNx\'\nmodule registerNx #(parameter regWidth=8)(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module ControlPath32v2 (
    output reg [14:0] controlWord,
    input  [10:0] instrBits,
    input  sysCLK
);

	
	wire [3:0]ALUi, ALUr;
	CP_RFormatDecoder cpr(ALUr, {instrBits[10], instrBits[9:7]});
	CP_IFormatDecoder cpi(ALUi, {instrBits[10], instrBits[9:7]});

	initial controlWord = 15'b0;
	always@(posedge sysCLK) begin
		case(instrBits[6:2])

			5'b00000: controlWord <= {1'b0, 3'b000, 1'bx, 1'b0, 1'b1, 4'b0000, 1'b0, 1'b1, 2'b01};
			5'b11000: controlWord <= {1'b0, 3'bxxx, 1'bx, 1'b0, 1'b0, 	 ALUr, 1'b0, 1'b1, 2'b00};
			5'b00100: controlWord <= {1'b0, 3'b000, 1'bx, 1'b0, 1'b1, 	 ALUi, 1'b0, 1'b1, 2'b00};
			5'b01000: controlWord <= {1'b0, 3'b001, 1'bx, 1'b0, 1'b1, 4'b0000, 1'b1, 1'b0, 2'bxx};
			default: controlWord <= 15'b0;
		endcase
	end
endmodule
module ControlPath32v2 (
    output reg [14:0] controlWord,
    input  [10:0] instrBits,
    input  sysCLK
);


	
	wire [3:0]ALUi, ALUr;
	CP_RFormatDecoder cpr(ALUr, {instrBits[10], instrBits[9:7]});
	CP_IFormatDecoder cpi(ALUi, {instrBits[10], instrBits[9:7]});

	initial controlWord = 15'b0;
	always@(posedge sysCLK) begin
		case(instrBits[6:2])

			5'b00000: controlWord <= {1'b0, 3'b000, 1'bx, 1'b0, 1'b1, 4'b0000, 1'b0, 1'b1, 2'b01};
			5'b11000: controlWord <= {1'b0, 3'bxxx, 1'bx, 1'b0, 1'b0, 	 ALUr, 1'b0, 1'b1, 2'b00};
			5'b00100: controlWord <= {1'b0, 3'b000, 1'bx, 1'b0, 1'b1, 	 ALUi, 1'b0, 1'b1, 2'b00};
			5'b01000: controlWord <= {1'b0, 3'b001, 1'bx, 1'b0, 1'b1, 4'b0000, 1'b1, 1'b0, 2'bxx};
			default: controlWord <= 15'b0;
		endcase
	end
endmodule