data/full_repos/permissive/143278/ivltests/credence20041209.v
 line:78: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/credence20041209.v:78: Unsupported: Ignoring delay on this delayed statement.\n   #10000 $display("This test doesn\'t check itself.");\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/credence20041209.v:26: Operator ITORD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                : ... In instance vtest.v19\n          start_edge = ( v_value[0] * 1.95)\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/credence20041209.v:27: Operator ITORD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                : ... In instance vtest.v19\n          + ( v_value[1] * 3.9 )\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/credence20041209.v:28: Operator ITORD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                : ... In instance vtest.v19\n          + ( v_value[2] * 7.8 )\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/credence20041209.v:29: Operator ITORD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                : ... In instance vtest.v19\n          + ( v_value[3] * 15.6 )\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/credence20041209.v:30: Operator ITORD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                : ... In instance vtest.v19\n          + ( v_value[4] * 31.2 )\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/credence20041209.v:31: Operator ITORD expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                : ... In instance vtest.v19\n          + ( v_value[5] * 62.5 )\n                     ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module verr (clk, vout);

input        clk;
output       vout;

reg          vout;
real         start_edge;
real         end_edge;

wire         trigger_en;
wire [9:0]   v_value;

initial vout = 1'b0;

always @( posedge clk)
   begin
     if (trigger_en)
        begin
          start_edge = ( v_value[0] * 1.95)
          + ( v_value[1] * 3.9 )
          + ( v_value[2] * 7.8 )
          + ( v_value[3] * 15.6 )
          + ( v_value[4] * 31.2 )
          + ( v_value[5] * 62.5 )
          + ( v_value[6] * 125 )
          + ( v_value[7] * 250 )
          + ( v_value[8] * 0 )
          + ( v_value[9] * 0 )
          + 0;
          end_edge = start_edge + 100;
        end
     else
       begin
         start_edge <= start_edge;
         end_edge   <= end_edge;
       end
   end

endmodule
module verr (clk, vout);


input        clk;
output       vout;

reg          vout;
real         start_edge;
real         end_edge;

wire         trigger_en;
wire [9:0]   v_value;

initial vout = 1'b0;

always @( posedge clk)
   begin
     if (trigger_en)
        begin
          start_edge = ( v_value[0] * 1.95)
          + ( v_value[1] * 3.9 )
          + ( v_value[2] * 7.8 )
          + ( v_value[3] * 15.6 )
          + ( v_value[4] * 31.2 )
          + ( v_value[5] * 62.5 )
          + ( v_value[6] * 125 )
          + ( v_value[7] * 250 )
          + ( v_value[8] * 0 )
          + ( v_value[9] * 0 )
          + 0;
          end_edge = start_edge + 100;
        end
     else
       begin
         start_edge <= start_edge;
         end_edge   <= end_edge;
       end
   end

endmodule