data/full_repos/permissive/172908596/R type Instruction/R_type.v
1: b'%Error: Cannot find file containing module: type\n        ... Looked in:\n             data/full_repos/permissive/172908596/R/type\n             data/full_repos/permissive/172908596/R/type.v\n             data/full_repos/permissive/172908596/R/type.sv\n             type\n             type.v\n             type.sv\n             obj_dir/type\n             obj_dir/type.v\n             obj_dir/type.sv\n%Error: Cannot find file containing module: Instruction,data/full_repos/permissive/172908596\n%Error: Cannot find file containing module: data/full_repos/permissive/172908596/R\n%Error: Cannot find file containing module: Instruction/R_type.v\n%Error: Exiting due to 4 error(s)\n'
module R_ins(r1,r2,r3,clk,ctrl,a,b,rd);
input [4:0] r1;
input [4:0] r2;
input [4:0] r3;
input [5:0] ctrl;
input clk;
reg [63:0] regFile[0:31];
output wire [63:0] a;
output wire [63:0] b;
output wire [63:0] rd;
wire cout, zero, overflow;
integer i;
initial
begin
	for(i=0;i<32;i=i+1)
	begin
		regFile[i] <= 64'b10101;
	end
end

	assign a=regFile[r1];
	assign b=regFile[r2];
ALU m1(a,b,ctrl[3:0],ctrl[5:4],rd,cout,zero,overflow);

	always@(posedge clk)
	begin	
		regFile[r3] <= rd;
	end

endmodule
module R_ins(r1,r2,r3,clk,ctrl,a,b,rd);

input [4:0] r1;
input [4:0] r2;
input [4:0] r3;
input [5:0] ctrl;
input clk;
reg [63:0] regFile[0:31];
output wire [63:0] a;
output wire [63:0] b;
output wire [63:0] rd;
wire cout, zero, overflow;
integer i;
initial
begin
	for(i=0;i<32;i=i+1)
	begin
		regFile[i] <= 64'b10101;
	end
end

	assign a=regFile[r1];
	assign b=regFile[r2];
ALU m1(a,b,ctrl[3:0],ctrl[5:4],rd,cout,zero,overflow);

	always@(posedge clk)
	begin	
		regFile[r3] <= rd;
	end

endmodule