data/full_repos/permissive/143278/ivltests/pr2801662.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2801662.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #1.999;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2801662.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #0.002;\n    ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
   reg in, pass;
   wire out;

   assign #(1?2:1) out = in;


  initial begin
    pass = 1'b1;
    in = 1'b0;
    #1.999;
    if (out !== 1'bx) begin
      $display("Failed signal at begining, expected 1'bx, got %b", out);
      pass = 1'b0;
    end
    #0.002;
    if (out !== in) begin
      $display("Failed signal at end, expected %b, got %b", in, out);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module test;

   reg in, pass;
   wire out;

   assign #(1?2:1) out = in;


  initial begin
    pass = 1'b1;
    in = 1'b0;
    #1.999;
    if (out !== 1'bx) begin
      $display("Failed signal at begining, expected 1'bx, got %b", out);
      pass = 1'b0;
    end
    #0.002;
    if (out !== in) begin
      $display("Failed signal at end, expected %b, got %b", in, out);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule