data/full_repos/permissive/214278225/4_calculator/calc.v
1: b'%Error: data/full_repos/permissive/214278225/4_calculator/calc.v:17: Cannot find file containing module: \'debounce\'\ndebounce dbc (.clk(clk), .rst(rst), .in(validIn), .out(validClean));  \n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214278225/4_calculator,data/full_repos/permissive/214278225/debounce\n             data/full_repos/permissive/214278225/4_calculator,data/full_repos/permissive/214278225/debounce.v\n             data/full_repos/permissive/214278225/4_calculator,data/full_repos/permissive/214278225/debounce.sv\n             debounce\n             debounce.v\n             debounce.sv\n             obj_dir/debounce\n             obj_dir/debounce.v\n             obj_dir/debounce.sv\n%Warning-WIDTH: data/full_repos/permissive/214278225/4_calculator/calc.v:63: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'operatorNxt\' generates 3 bits.\n                                                                           : ... In instance calc\n                        ledOutNxt = operatorNxt;\n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module calc(clk, rst, validIn, dataIn, ledOut);
input clk, rst, validIn;
input  [7:0] dataIn;
output reg [7:0] ledOut;

reg [1:0] state, stateNxt;
reg [7:0] number, numberNxt, ledOutNxt;
reg [2:0] operator, operatorNxt;


wire valid;
wire validClean;
reg validReg;
assign valid = validClean &!validReg; 

debounce dbc (.clk(clk), .rst(rst), .in(validIn), .out(validClean));

always @(posedge clk) begin
	validReg   <= #1 validClean;
	state      <= #1 stateNxt;
	number     <= #1 numberNxt;
	operator   <= #1 operatorNxt;
	ledOut     <= #1 ledOutNxt;
end

always @(*) begin
	stateNxt    = state;
	numberNxt   = number;
	operatorNxt = operator;
	ledOutNxt   = ledOut;
	if(rst) begin
		stateNxt    = 0;
		numberNxt   = 0;
		operatorNxt = 0;
		ledOutNxt   = 0;
	end else begin
		case(state)
			0: begin
				if(valid)begin
					numberNxt = dataIn;
					stateNxt = state+1;
					ledOutNxt = numberNxt;
				end
				else begin
					stateNxt = 0;
					ledOutNxt = ledOut;
				end
			end
			1: begin
				if(valid)begin
					operatorNxt = dataIn[2:0];
					if(operatorNxt == 3 || operatorNxt == 4 || operatorNxt == 5)begin
						stateNxt = 0;
						case(operatorNxt)
                            3: ledOutNxt = number * number;
                            4: ledOutNxt = number+1;
                            5: ledOutNxt = number-1;
                        endcase
					end
                    else begin
                        stateNxt = state + 1;
                        ledOutNxt = operatorNxt;
                    end
				end
			end
			2: begin
                if(valid)begin
                    numberNxt = dataIn;
                    case(operator)
                        0: ledOutNxt = number * numberNxt;
                        1: ledOutNxt = number + numberNxt;
                        2: ledOutNxt = number - numberNxt;
                    endcase
                    stateNxt = 0;
                end
			end	
		endcase
	end
end
endmodule
module calc(clk, rst, validIn, dataIn, ledOut);

input clk, rst, validIn;
input  [7:0] dataIn;
output reg [7:0] ledOut;

reg [1:0] state, stateNxt;
reg [7:0] number, numberNxt, ledOutNxt;
reg [2:0] operator, operatorNxt;


wire valid;
wire validClean;
reg validReg;
assign valid = validClean &!validReg; 

debounce dbc (.clk(clk), .rst(rst), .in(validIn), .out(validClean));

always @(posedge clk) begin
	validReg   <= #1 validClean;
	state      <= #1 stateNxt;
	number     <= #1 numberNxt;
	operator   <= #1 operatorNxt;
	ledOut     <= #1 ledOutNxt;
end

always @(*) begin
	stateNxt    = state;
	numberNxt   = number;
	operatorNxt = operator;
	ledOutNxt   = ledOut;
	if(rst) begin
		stateNxt    = 0;
		numberNxt   = 0;
		operatorNxt = 0;
		ledOutNxt   = 0;
	end else begin
		case(state)
			0: begin
				if(valid)begin
					numberNxt = dataIn;
					stateNxt = state+1;
					ledOutNxt = numberNxt;
				end
				else begin
					stateNxt = 0;
					ledOutNxt = ledOut;
				end
			end
			1: begin
				if(valid)begin
					operatorNxt = dataIn[2:0];
					if(operatorNxt == 3 || operatorNxt == 4 || operatorNxt == 5)begin
						stateNxt = 0;
						case(operatorNxt)
                            3: ledOutNxt = number * number;
                            4: ledOutNxt = number+1;
                            5: ledOutNxt = number-1;
                        endcase
					end
                    else begin
                        stateNxt = state + 1;
                        ledOutNxt = operatorNxt;
                    end
				end
			end
			2: begin
                if(valid)begin
                    numberNxt = dataIn;
                    case(operator)
                        0: ledOutNxt = number * numberNxt;
                        1: ledOutNxt = number + numberNxt;
                        2: ledOutNxt = number - numberNxt;
                    endcase
                    stateNxt = 0;
                end
			end	
		endcase
	end
end
endmodule