data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:403: Multiple top level modules\n                                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                      : ... Top module \'fpga_top\'\nmodule fpga_top (\n       ^~~~~~~~\n                                                                                                      : ... Top module \'WF_random_5\'\n   module WF_random_5 (\n          ^~~~~~~~~~~\n                                                                                                      : ... Top module \'WF_bram256x16\'\n   module WF_bram256x16 (\n          ^~~~~~~~~~~~~\n                                                                                                      : ... Top module \'WF_switch_debounce\'\n   module WF_switch_debounce (\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:224: Duplicate declaration of signal: \'scan_done\'\n                                                                                           : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire scan_done = dotclk_done;\n       ^~~~~~~~~\n        data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:214: ... Location of original declaration\n   output scan_done,  \n          ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:57: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:59: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:65: Signal definition not found, creating implicitly: \'two_ms\'\n           .timer_pulse(two_ms));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:71: Signal definition not found, creating implicitly: \'one_second\'\n           .timer_pulse(one_second));\n                        ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:78: Signal definition not found, creating implicitly: \'scan_done\'\n     .scan_done(scan_done),\n                ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:124: Signal definition not found, creating implicitly: \'center_pushed\'\n     assign center_pushed = joystick[3] && !joystick_d[3];\n            ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:125: Signal definition not found, creating implicitly: \'north_pushed\'\n     assign north_pushed  = joystick[0] && !joystick_d[0];\n            ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:126: Signal definition not found, creating implicitly: \'south_pushed\'\n                                                                                                      : ... Suggested alternative: \'north_pushed\'\n     assign south_pushed  = joystick[2] && !joystick_d[2];\n            ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:127: Signal definition not found, creating implicitly: \'east_pushed\'\n                                                                                                      : ... Suggested alternative: \'north_pushed\'\n     assign east_pushed   = joystick[1] && !joystick_d[1];\n            ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_RGB_dot_matrix_joystick_demo.v:128: Signal definition not found, creating implicitly: \'west_pushed\'\n                                                                                                      : ... Suggested alternative: \'east_pushed\'\n     assign west_pushed   = joystick[4] && !joystick_d[4];\n            ^~~~~~~~~~~\n%Error: Exiting due to 1 error(s), 11 warning(s)\n'
module WF_joystick_board (
     input        clk,
     input        scan_enable,

     input [7:0]  slide_leds_red,
     input [7:0]  slide_leds_green,
     input [3:0]  status_leds_red,
     input [3:0]  status_leds_blue,
     input [11:0] circle_leds_red,
     input [11:0] circle_leds_green,

     output reg  [7:0] slide_switches,
     output reg  [4:0] joystick_switches,

     input       [7:0] header_outputs,
     output reg  [7:0] header_inputs,


     output       LOAD,
     output reg   CLK_OUT,
     output       MST_OUT_SLV_IN,
     input        MST_IN_SLV_OUT
     );


   reg [5:0] columns;

   reg       shiftclk_en;
   reg [5:0] dataout_index;

   reg [7:0]  current_row;
   reg [15:0] data_out;
   reg [23:0] data_in;
   reg  [4:0] joystick;


   reg        shiftclk_en_d;
   wire       load_clk;



    always @ (posedge clk)
      if (load_clk)
       begin
        header_inputs[7:0]     <= data_in[23:16];
        joystick_switches[4:0] <= ~data_in[4:0];
        slide_switches[7:0]    <= ~data_in[15:8];
       end




   always @ (posedge clk)
     begin
       if (columns == 6'h0)
         columns <= 6'h01;

       if (scan_enable)
         columns <= {columns[4:0],columns[5]};
     end






   always @ (posedge clk)
     begin
       if (scan_enable)
         begin
           shiftclk_en     <= 1'b1;
           dataout_index   <= 6'b0;
         end
       else
         begin
           if (shiftclk_en)
             begin
               if (dataout_index == 6'd47)
                 shiftclk_en <= 1'b0;
               else
                 dataout_index <= dataout_index + 6'h1;
             end
         end
   end


   always @ (posedge clk)
     if (shiftclk_en )
       begin
         if (dataout_index[0])
           begin
             data_out <= {data_out[14:0],1'b0};
           end


         else

            data_in <= {data_in[22:0],MST_IN_SLV_OUT};

         if (dataout_index == 5'd31)
           data_out <= {header_outputs,8'h00};

       end
     else
         data_out<= { current_row[7:0],2'b0,columns};




    always @ (posedge clk)
      shiftclk_en_d <= shiftclk_en;

    assign load_clk = shiftclk_en_d && ~shiftclk_en;




   always @(*)
      case (columns)
        6'd1 : current_row = ~slide_leds_red[7:0];
        6'd2 : current_row = ~slide_leds_green[7:0];
        6'd4 : current_row = ~circle_leds_red[7:0];
        6'd8 : current_row = ~circle_leds_green[7:0];
        6'd16: current_row = ~{status_leds_red[3:0],circle_leds_red[11:8]};
        default:
         current_row = ~{status_leds_blue[3:0],circle_leds_green[11:8]};
      endcase



   assign LOAD = ~shiftclk_en;


   always @ (posedge clk)
     if (shiftclk_en)
       CLK_OUT <= ~CLK_OUT;
     else
       begin
         if (load_clk)
           CLK_OUT <= 1'b1;
         else
           CLK_OUT <= 1'b0;
       end

   assign MST_OUT_SLV_IN = data_out[15];

endmodule
module WF_joystick_board (
     input        clk,
     input        scan_enable,

     input [7:0]  slide_leds_red,
     input [7:0]  slide_leds_green,
     input [3:0]  status_leds_red,
     input [3:0]  status_leds_blue,
     input [11:0] circle_leds_red,
     input [11:0] circle_leds_green,

     output reg  [7:0] slide_switches,
     output reg  [4:0] joystick_switches,

     input       [7:0] header_outputs,
     output reg  [7:0] header_inputs,


     output       LOAD,
     output reg   CLK_OUT,
     output       MST_OUT_SLV_IN,
     input        MST_IN_SLV_OUT
     );



   reg [5:0] columns;

   reg       shiftclk_en;
   reg [5:0] dataout_index;

   reg [7:0]  current_row;
   reg [15:0] data_out;
   reg [23:0] data_in;
   reg  [4:0] joystick;


   reg        shiftclk_en_d;
   wire       load_clk;



    always @ (posedge clk)
      if (load_clk)
       begin
        header_inputs[7:0]     <= data_in[23:16];
        joystick_switches[4:0] <= ~data_in[4:0];
        slide_switches[7:0]    <= ~data_in[15:8];
       end




   always @ (posedge clk)
     begin
       if (columns == 6'h0)
         columns <= 6'h01;

       if (scan_enable)
         columns <= {columns[4:0],columns[5]};
     end






   always @ (posedge clk)
     begin
       if (scan_enable)
         begin
           shiftclk_en     <= 1'b1;
           dataout_index   <= 6'b0;
         end
       else
         begin
           if (shiftclk_en)
             begin
               if (dataout_index == 6'd47)
                 shiftclk_en <= 1'b0;
               else
                 dataout_index <= dataout_index + 6'h1;
             end
         end
   end


   always @ (posedge clk)
     if (shiftclk_en )
       begin
         if (dataout_index[0])
           begin
             data_out <= {data_out[14:0],1'b0};
           end


         else

            data_in <= {data_in[22:0],MST_IN_SLV_OUT};

         if (dataout_index == 5'd31)
           data_out <= {header_outputs,8'h00};

       end
     else
         data_out<= { current_row[7:0],2'b0,columns};




    always @ (posedge clk)
      shiftclk_en_d <= shiftclk_en;

    assign load_clk = shiftclk_en_d && ~shiftclk_en;




   always @(*)
      case (columns)
        6'd1 : current_row = ~slide_leds_red[7:0];
        6'd2 : current_row = ~slide_leds_green[7:0];
        6'd4 : current_row = ~circle_leds_red[7:0];
        6'd8 : current_row = ~circle_leds_green[7:0];
        6'd16: current_row = ~{status_leds_red[3:0],circle_leds_red[11:8]};
        default:
         current_row = ~{status_leds_blue[3:0],circle_leds_green[11:8]};
      endcase



   assign LOAD = ~shiftclk_en;


   always @ (posedge clk)
     if (shiftclk_en)
       CLK_OUT <= ~CLK_OUT;
     else
       begin
         if (load_clk)
           CLK_OUT <= 1'b1;
         else
           CLK_OUT <= 1'b0;
       end

   assign MST_OUT_SLV_IN = data_out[15];

endmodule