data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/clk_div.v
data/verilator_xmls/6a8ec07f-7b36-41c0-ac17-8e88877e4ae3.xml
module clk_div_IIC(clk_i,rst_i,clk_o);

	localparam f_i = 100000000,
				  f_o = 100000,
				  const_div = f_i/f_o ;

	input clk_i,rst_i;
	output wire clk_o;

	wire divide;
	reg clk_temp=1'b0;

	assign clk_o=(divide)? clk_temp:clk_i;
	assign divide =(const_div==1) ? 1'b0 : 1'b1 ;
	integer cnt=0;

	always @(posedge clk_i or posedge rst_i)
	begin 
		if(rst_i)
			begin
				cnt=0;
				clk_temp=1'b0;
			end 
		else
		begin
			if(divide)	
			begin
				cnt=cnt+1;
				case(cnt) 
				const_div/2: clk_temp=1'b1;
				const_div  : begin 
									clk_temp=1'b0;
									cnt=0;
								 end
				endcase
			end						
		end 	
	end 		
endmodule
module clk_div_IIC(clk_i,rst_i,clk_o);


	localparam f_i = 100000000,
				  f_o = 100000,
				  const_div = f_i/f_o ;

	input clk_i,rst_i;
	output wire clk_o;

	wire divide;
	reg clk_temp=1'b0;

	assign clk_o=(divide)? clk_temp:clk_i;
	assign divide =(const_div==1) ? 1'b0 : 1'b1 ;
	integer cnt=0;

	always @(posedge clk_i or posedge rst_i)
	begin 
		if(rst_i)
			begin
				cnt=0;
				clk_temp=1'b0;
			end 
		else
		begin
			if(divide)	
			begin
				cnt=cnt+1;
				case(cnt) 
				const_div/2: clk_temp=1'b1;
				const_div  : begin 
									clk_temp=1'b0;
									cnt=0;
								 end
				endcase
			end						
		end 	
	end 		
endmodule