data/full_repos/permissive/102515926/Modules/REG.v
data/verilator_xmls/969e3893-9fb9-44f2-8580-9d033ec24943.xml
module REG(d, Clk, Rst, q);

    parameter DATAWIDTH = 8;

    input Clk, Rst;
    input [DATAWIDTH - 1:0] d;
    
    output reg [DATAWIDTH - 1:0] q;
    
    always @(posedge Clk) begin
        if(Rst)
            q <= 0;
        else
            q <= d;
    end
    
endmodule
module REG(d, Clk, Rst, q);


    parameter DATAWIDTH = 8;

    input Clk, Rst;
    input [DATAWIDTH - 1:0] d;
    
    output reg [DATAWIDTH - 1:0] q;
    
    always @(posedge Clk) begin
        if(Rst)
            q <= 0;
        else
            q <= d;
    end
    
endmodule