data/full_repos/permissive/119913252/proj1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/119913252/proj1_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n   #5   ctr = ctr + 1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/119913252/proj1_tb.v:15: Cannot find file containing module: \'proj1\'\nproj1 instance1 (x1_test,x2_test,x3_test,f_test);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/119913252,data/full_repos/permissive/119913252/proj1\n             data/full_repos/permissive/119913252,data/full_repos/permissive/119913252/proj1.v\n             data/full_repos/permissive/119913252,data/full_repos/permissive/119913252/proj1.sv\n             proj1\n             proj1.v\n             proj1.sv\n             obj_dir/proj1\n             obj_dir/proj1.v\n             obj_dir/proj1.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module proj1_tb;
   reg  [2:0]  ctr;
   wire   x1_test, x2_test, x3_test;
   wire   f_test;
   

proj1 instance1 (x1_test,x2_test,x3_test,f_test);


initial
  begin        
     ctr = 3'b0;
  end

always
   #5   ctr = ctr + 1;
  
assign x1_test = ctr[2];
assign x2_test = ctr[1];
assign x3_test = ctr[0];


endmodule
module proj1_tb;

   reg  [2:0]  ctr;
   wire   x1_test, x2_test, x3_test;
   wire   f_test;
   

proj1 instance1 (x1_test,x2_test,x3_test,f_test);


initial
  begin        
     ctr = 3'b0;
  end

always
   #5   ctr = ctr + 1;
  
assign x1_test = ctr[2];
assign x2_test = ctr[1];
assign x3_test = ctr[0];


endmodule