data/full_repos/permissive/174369527/SISD/alu_uadd-behav.v
data/verilator_xmls/1395b59a-476f-44a6-b0fa-340e57589482.xml
module alu_uadd
	(
	i_s1,
	i_s2,
	o_result,
	o_carry
	);
	parameter SIZE = 8;
	input wire [SIZE-1:0] i_s1;
	input wire [SIZE-1:0] i_s2;
	output wire [SIZE-1:0] o_result;
	output wire [0:0] o_carry;

	assign {o_carry, o_result} = i_s1 + i_s2;
endmodule
module alu_uadd
	(
	i_s1,
	i_s2,
	o_result,
	o_carry
	);

	parameter SIZE = 8;
	input wire [SIZE-1:0] i_s1;
	input wire [SIZE-1:0] i_s2;
	output wire [SIZE-1:0] o_result;
	output wire [0:0] o_carry;

	assign {o_carry, o_result} = i_s1 + i_s2;
endmodule