data/full_repos/permissive/165514176/message_rom.v
 line:58: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/165514176/message_rom.v:58: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                     : ... In instance message_rom\n  reg [7:0] data_d, data_q =  7\'b0;\n                              ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/165514176/message_rom.v:67: Cannot find file containing module: \'Binary_to_BCD\'\n Binary_to_BCD #(.INPUT_WIDTH(size),.DECIMAL_DIGITS(numdigits)) binary_to_BCD (\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165514176,data/full_repos/permissive/165514176/Binary_to_BCD\n             data/full_repos/permissive/165514176,data/full_repos/permissive/165514176/Binary_to_BCD.v\n             data/full_repos/permissive/165514176,data/full_repos/permissive/165514176/Binary_to_BCD.sv\n             Binary_to_BCD\n             Binary_to_BCD.v\n             Binary_to_BCD.sv\n             obj_dir/Binary_to_BCD\n             obj_dir/Binary_to_BCD.v\n             obj_dir/Binary_to_BCD.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module message_rom (
    input clk,
    input [7:0] addr,
    output [7:0] data,
	 input [31:0] valuetoprint,
	 output conversiondone,
	 input startconv,
	 input isneg
  );

   localparam STATE_SIZE = 4;
  localparam IDLE = 0,
    PRINT_MESSAGE = 1,
	 STATE2 = 2,
	 NEGCHECK =3,
	 CALC = 4;
   localparam size = 32,
	numdigits =10;
  reg [STATE_SIZE-1:0] state_d, state_q;
  
  wire [7:0] rom_data [13:0];
 
  assign rom_data[0] = "H";
  assign rom_data[1] = "e";
  assign rom_data[2] = "l";
  assign rom_data[3] = "l";
  assign rom_data[4] = "o";
  assign rom_data[5] = " ";
  assign rom_data[6] = "W";
  assign rom_data[7] = "o";
  assign rom_data[8] = "r";
  assign rom_data[9] = "l";
  assign rom_data[10] = "d";
  assign rom_data[11] = "!";
  assign rom_data[12] = "!";
  assign rom_data[13] = "\n";
 
  reg [7:0] data_d, data_q =  7'b0;


  
  assign data = data_q;
  wire [39:0] coverted;
  reg start = 1'b0;
  wire done;
  assign conversiondone = done;
 Binary_to_BCD #(.INPUT_WIDTH(size),.DECIMAL_DIGITS(numdigits)) binary_to_BCD (
    .i_Clock(clk),
    .i_Binary(valuetoprint),
    .i_Start(start),
    .o_BCD(coverted),
	 .o_DV(done)
  );
  always @(*) begin
		data_d = data_q;
		state_d = state_q;
		start = 1'b0;

		
		case (state_q)
      IDLE: begin

		  state_d = STATE2;
      end

		STATE2: begin
				if(valuetoprint == 32'd2147483646)
				begin
				data_d = ":";
				end
				else begin
				data_d =  valuetoprint[addr*8-1 -: 8];
				end

			end
		  default: state_d = IDLE;
    endcase
		
		    



  end
 
  always @(posedge clk) begin
    state_q <= state_d;
	 data_q <= data_d;
	 
  end
 
endmodule
module message_rom (
    input clk,
    input [7:0] addr,
    output [7:0] data,
	 input [31:0] valuetoprint,
	 output conversiondone,
	 input startconv,
	 input isneg
  );


   localparam STATE_SIZE = 4;
  localparam IDLE = 0,
    PRINT_MESSAGE = 1,
	 STATE2 = 2,
	 NEGCHECK =3,
	 CALC = 4;
   localparam size = 32,
	numdigits =10;
  reg [STATE_SIZE-1:0] state_d, state_q;
  
  wire [7:0] rom_data [13:0];
 
  assign rom_data[0] = "H";
  assign rom_data[1] = "e";
  assign rom_data[2] = "l";
  assign rom_data[3] = "l";
  assign rom_data[4] = "o";
  assign rom_data[5] = " ";
  assign rom_data[6] = "W";
  assign rom_data[7] = "o";
  assign rom_data[8] = "r";
  assign rom_data[9] = "l";
  assign rom_data[10] = "d";
  assign rom_data[11] = "!";
  assign rom_data[12] = "!";
  assign rom_data[13] = "\n";
 
  reg [7:0] data_d, data_q =  7'b0;


  
  assign data = data_q;
  wire [39:0] coverted;
  reg start = 1'b0;
  wire done;
  assign conversiondone = done;
 Binary_to_BCD #(.INPUT_WIDTH(size),.DECIMAL_DIGITS(numdigits)) binary_to_BCD (
    .i_Clock(clk),
    .i_Binary(valuetoprint),
    .i_Start(start),
    .o_BCD(coverted),
	 .o_DV(done)
  );
  always @(*) begin
		data_d = data_q;
		state_d = state_q;
		start = 1'b0;

		
		case (state_q)
      IDLE: begin

		  state_d = STATE2;
      end

		STATE2: begin
				if(valuetoprint == 32'd2147483646)
				begin
				data_d = ":";
				end
				else begin
				data_d =  valuetoprint[addr*8-1 -: 8];
				end

			end
		  default: state_d = IDLE;
    endcase
		
		    



  end
 
  always @(posedge clk) begin
    state_q <= state_d;
	 data_q <= data_d;
	 
  end
 
endmodule