data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/NextState.v
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data/verilator_xmls/40f7273b-2268-498b-a631-5af3e29a28a2.xml
module NextState(
InputState, opcode, OutputState
);
    input [5:0] opcode;
    output reg [2:0] OutputState;
    input [2:0] InputState;
    

    parameter [2:0] StateIF = 3'b000;
    parameter [2:0] StateID = 3'b001 ;
    parameter [2:0] StateEXE = 3'b010; 
    parameter [2:0] StateWB = 3'b011;
    parameter [2:0] StateMEM = 3'b100;

    always @ (InputState or opcode)begin
        case (InputState)
            StateIF: OutputState = StateID;
            StateID: begin
                case (opcode[5:3])
                    3'b111: OutputState = StateIF;
                    default: OutputState = StateEXE;
                endcase                                
            end
            StateEXE:
                case(opcode[5:2])
                    4'b1101: OutputState = StateIF;
                    4'b1100: OutputState = StateMEM;
                    default: OutputState = StateWB;
                endcase
            StateMEM:
                    if(opcode == 6'b110000) OutputState = StateIF;
                    else OutputState = StateWB;
            StateWB: OutputState = StateIF;
        endcase       
    end    
    
endmodule
module NextState(
InputState, opcode, OutputState
);

    input [5:0] opcode;
    output reg [2:0] OutputState;
    input [2:0] InputState;
    

    parameter [2:0] StateIF = 3'b000;
    parameter [2:0] StateID = 3'b001 ;
    parameter [2:0] StateEXE = 3'b010; 
    parameter [2:0] StateWB = 3'b011;
    parameter [2:0] StateMEM = 3'b100;

    always @ (InputState or opcode)begin
        case (InputState)
            StateIF: OutputState = StateID;
            StateID: begin
                case (opcode[5:3])
                    3'b111: OutputState = StateIF;
                    default: OutputState = StateEXE;
                endcase                                
            end
            StateEXE:
                case(opcode[5:2])
                    4'b1101: OutputState = StateIF;
                    4'b1100: OutputState = StateMEM;
                    default: OutputState = StateWB;
                endcase
            StateMEM:
                    if(opcode == 6'b110000) OutputState = StateIF;
                    else OutputState = StateWB;
            StateWB: OutputState = StateIF;
        endcase       
    end    
    
endmodule