data/full_repos/permissive/160437780/Source/ultraSonic.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160437780/Source/ultraSonic.v:37: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                           : ... In instance ultraSonic\n        counter <= 24\'d0;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ultraSonic(
input CLK100MHZ,
input echo,
output reg trig,
output reg [1:0] choose

);


reg [25:0] counter = 26'd0;
parameter loop_count = 26'd30000000;
parameter trig_end   = 26'd1000;

reg [25:0] echo_count = 26'd0;
parameter threshold = 26'd300000;


always @ (posedge CLK100MHZ) begin
    

    if (counter < trig_end) begin
        echo_count <= 0;
        trig <= 1;
        counter <= counter + 1;
    end else if (counter < loop_count) begin
        trig <= 0;
        counter <= counter + 1;
        
        if (echo) begin
            echo_count <= echo_count + 1;
        end
        
    end else begin

        counter <= 24'd0;

        trig <= 0;
        
        if (echo_count < threshold)
            choose <= 2'b01;
        else
            choose <= 2'b10;
    end
    
end

endmodule
module ultraSonic(
input CLK100MHZ,
input echo,
output reg trig,
output reg [1:0] choose

);



reg [25:0] counter = 26'd0;
parameter loop_count = 26'd30000000;
parameter trig_end   = 26'd1000;

reg [25:0] echo_count = 26'd0;
parameter threshold = 26'd300000;


always @ (posedge CLK100MHZ) begin
    

    if (counter < trig_end) begin
        echo_count <= 0;
        trig <= 1;
        counter <= counter + 1;
    end else if (counter < loop_count) begin
        trig <= 0;
        counter <= counter + 1;
        
        if (echo) begin
            echo_count <= echo_count + 1;
        end
        
    end else begin

        counter <= 24'd0;

        trig <= 0;
        
        if (echo_count < threshold)
            choose <= 2'b01;
        else
            choose <= 2'b10;
    end
    
end

endmodule