data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/signext.v
data/verilator_xmls/9e5df2dd-0986-452a-8429-6498748eb568.xml
module signext(
    input [15:0] a,
    input extend,
    output reg [31:0] y
    );
    
    always@(*)
    if(extend)
        y<= #1 { {16{a[15]}},a };
    else
        y<= #1 { 16'b0,a };
    
endmodule
module signext(
    input [15:0] a,
    input extend,
    output reg [31:0] y
    );

    
    always@(*)
    if(extend)
        y<= #1 { {16{a[15]}},a };
    else
        y<= #1 { 16'b0,a };
    
endmodule