data/full_repos/permissive/20430511/hardware/FPGA/wishbone/legacy/wb4_get_block.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/5ca4d847-9a75-444e-9af7-3bd346ba6348.xml
module wb4_get_block
  #(parameter BSIZE = 24,
    parameter BMAX  = BSIZE-1,
    parameter BBITS = 5,
    parameter BSB   = BBITS-1,
    parameter DELAY = 3)
   (
    input          clk_i,
    input          rst_i,
    output reg     cyc_o = 1'b0,
    output reg     stb_o = 1'b0,
    output         we_o,
    input          ack_i,
    input          wat_i,
    input          rty_i,
    input          err_i,
    output [BSB:0] adr_o,

    input          read_i,
    output reg     done_o = 1'b0
    );

   reg [BSB:0]     blk = {BBITS{1'b0}};
   reg [BSB:0]     wat = BMAX;
   wire [BBITS:0]  blk_nxt = blk + 1;
   wire [BBITS:0]  wat_prv = wat - 1;
   wire            cyc_w = !err_i && !rty_i && (wat > 1 || !ack_i);
   wire            stb_w = blk < BMAX || wat_i;


   assign we_o  = 1'b0;
   assign adr_o = blk;





   always @(posedge clk_i)
     if (rst_i)
       {cyc_o, stb_o} <= #DELAY 2'b00;
     else if (read_i)
       {cyc_o, stb_o} <= #DELAY 2'b11;
     else if (cyc_o)
       {cyc_o, stb_o} <= #DELAY {cyc_w, stb_w};
     else
       {cyc_o, stb_o} <= #DELAY 2'b00;



   always @(posedge clk_i)
     if (read_i)
       blk <= #DELAY {BBITS{1'b0}};
     else if (cyc_o && !wat_i)
       blk <= #DELAY blk_nxt[BSB:0];



   always @(posedge clk_i)
     if (rst_i || done_o)
       wat <= #DELAY BMAX;
     else if (cyc_o && ack_i)
       wat <= #DELAY wat_prv[BSB:0];





   always @(posedge clk_i)
     done_o <= #DELAY cyc_o && wat == 1 && ack_i;


endmodule
module wb4_get_block
  #(parameter BSIZE = 24,
    parameter BMAX  = BSIZE-1,
    parameter BBITS = 5,
    parameter BSB   = BBITS-1,
    parameter DELAY = 3)
   (
    input          clk_i,
    input          rst_i,
    output reg     cyc_o = 1'b0,
    output reg     stb_o = 1'b0,
    output         we_o,
    input          ack_i,
    input          wat_i,
    input          rty_i,
    input          err_i,
    output [BSB:0] adr_o,

    input          read_i,
    output reg     done_o = 1'b0
    );


   reg [BSB:0]     blk = {BBITS{1'b0}};
   reg [BSB:0]     wat = BMAX;
   wire [BBITS:0]  blk_nxt = blk + 1;
   wire [BBITS:0]  wat_prv = wat - 1;
   wire            cyc_w = !err_i && !rty_i && (wat > 1 || !ack_i);
   wire            stb_w = blk < BMAX || wat_i;


   assign we_o  = 1'b0;
   assign adr_o = blk;





   always @(posedge clk_i)
     if (rst_i)
       {cyc_o, stb_o} <= #DELAY 2'b00;
     else if (read_i)
       {cyc_o, stb_o} <= #DELAY 2'b11;
     else if (cyc_o)
       {cyc_o, stb_o} <= #DELAY {cyc_w, stb_w};
     else
       {cyc_o, stb_o} <= #DELAY 2'b00;



   always @(posedge clk_i)
     if (read_i)
       blk <= #DELAY {BBITS{1'b0}};
     else if (cyc_o && !wat_i)
       blk <= #DELAY blk_nxt[BSB:0];



   always @(posedge clk_i)
     if (rst_i || done_o)
       wat <= #DELAY BMAX;
     else if (cyc_o && ack_i)
       wat <= #DELAY wat_prv[BSB:0];





   always @(posedge clk_i)
     done_o <= #DELAY cyc_o && wat == 1 && ack_i;


endmodule