data/full_repos/permissive/133149315/common/gck.v
data/verilator_xmls/cd67f490-45e5-43d6-a89e-5d93bc0a8fb5.xml
module gck(
input i_clk,
input i_clk_en,

output o_clk
);

reg latch;
always @(i_clk or i_clk_en)begin
    if(!i_clk)
        latch <= i_clk_en;
end

assign o_clk = i_clk & latch;

endmodule
module gck(
input i_clk,
input i_clk_en,

output o_clk
);


reg latch;
always @(i_clk or i_clk_en)begin
    if(!i_clk)
        latch <= i_clk_en;
end

assign o_clk = i_clk & latch;

endmodule