data/full_repos/permissive/179947554/simplecpu.v
 line:177: before: "$"
1: b'%Error: data/full_repos/permissive/179947554/simplecpu.v:174: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/179947554/simplecpu.v:175: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, icarus_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/179947554/simplecpu.v:177: Unsupported: Ignoring delay on this delayed statement.\n    #60 $finish;       \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/179947554/simplecpu.v:182: Unsupported: Ignoring delay on this delayed statement.\n    #1 i_clk = ~i_clk;   \n    ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter (i_clk, wr_stb, incr_stb, data, result);
  input        i_clk;
  input        wr_stb;
  input        incr_stb;
  input  [7:0] data;
  output [7:0] result;

  reg [7:0] internal_value=0;
  assign result= internal_value;

  always @(posedge i_clk)
    if (wr_stb)	
      internal_value <= data;
    else if (incr_stb)
      internal_value <= internal_value + 1;
endmodule
module counter (i_clk, wr_stb, incr_stb, data, result);

  input        i_clk;
  input        wr_stb;
  input        incr_stb;
  input  [7:0] data;
  output [7:0] result;

  reg [7:0] internal_value=0;
  assign result= internal_value;

  always @(posedge i_clk)
    if (wr_stb)	
      internal_value <= data;
    else if (incr_stb)
      internal_value <= internal_value + 1;
endmodule