data/full_repos/permissive/165126488/HDMI_test.v
1: b'%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:70: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];\n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:75: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4\'d4;\n                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:78: Operator AND expects 4 bits on the LHS, but LHS\'s REPLICATE generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance_acc_inc = balance - ({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0));\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:78: Operator NOT expects 4 bits on the LHS, but LHS\'s LOGOR generates 1 bits.\n                                                                   : ... In instance HDMI_test.encode_B\nwire [3:0] balance_acc_inc = balance - ({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0));\n                                                                      ^\n%Error: data/full_repos/permissive/165126488/HDMI_test.v:37: Cannot find file containing module: \'DCM_SP\'\nDCM_SP #(.CLKFX_MULTIPLY(10)) DCM_TMDS_inst(.CLKIN(pixclk), .CLKFX(DCM_TMDS_CLKFX), .RST(1\'b0));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165126488,data/full_repos/permissive/165126488/DCM_SP\n             data/full_repos/permissive/165126488,data/full_repos/permissive/165126488/DCM_SP.v\n             data/full_repos/permissive/165126488,data/full_repos/permissive/165126488/DCM_SP.sv\n             DCM_SP\n             DCM_SP.v\n             DCM_SP.sv\n             obj_dir/DCM_SP\n             obj_dir/DCM_SP.v\n             obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/165126488/HDMI_test.v:38: Cannot find file containing module: \'BUFG\'\nBUFG BUFG_TMDSp(.I(DCM_TMDS_CLKFX), .O(clk_TMDS));\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:48: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s SEL generates 9 bits.\n                                                                   : ... In instance HDMI_test\n TMDS_shift_red   <= TMDS_shift_load ? TMDS_red   : TMDS_shift_red  [9:1];\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:49: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s SEL generates 9 bits.\n                                                                   : ... In instance HDMI_test\n TMDS_shift_green <= TMDS_shift_load ? TMDS_green : TMDS_shift_green[9:1];\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/165126488/HDMI_test.v:50: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s SEL generates 9 bits.\n                                                                   : ... In instance HDMI_test\n TMDS_shift_blue  <= TMDS_shift_load ? TMDS_blue  : TMDS_shift_blue [9:1]; \n                                     ^\n%Error: data/full_repos/permissive/165126488/HDMI_test.v:54: Cannot find file containing module: \'OBUFDS\'\nOBUFDS OBUFDS_red  (.I(TMDS_shift_red  [0]), .O(TMDSp[2]), .OB(TMDSn[2]));\n^~~~~~\n%Error: data/full_repos/permissive/165126488/HDMI_test.v:55: Cannot find file containing module: \'OBUFDS\'\nOBUFDS OBUFDS_green(.I(TMDS_shift_green[0]), .O(TMDSp[1]), .OB(TMDSn[1]));\n^~~~~~\n%Error: data/full_repos/permissive/165126488/HDMI_test.v:56: Cannot find file containing module: \'OBUFDS\'\nOBUFDS OBUFDS_blue (.I(TMDS_shift_blue [0]), .O(TMDSp[0]), .OB(TMDSn[0]));\n^~~~~~\n%Error: data/full_repos/permissive/165126488/HDMI_test.v:57: Cannot find file containing module: \'OBUFDS\'\nOBUFDS OBUFDS_clock(.I(pixclk), .O(TMDSp_clock), .OB(TMDSn_clock));\n^~~~~~\n%Error: Exiting due to 6 error(s), 21 warning(s)\n'
module HDMI_test(
	input pixclk,
	output [2:0] TMDSp, TMDSn,
	output TMDSp_clock, TMDSn_clock
);


reg [9:0] CounterX, CounterY;
reg hSync, vSync, DrawArea;
always @(posedge pixclk) DrawArea <= (CounterX<640) && (CounterY<480);

always @(posedge pixclk) CounterX <= (CounterX==799) ? 0 : CounterX+1;
always @(posedge pixclk) if(CounterX==799) CounterY <= (CounterY==524) ? 0 : CounterY+1;

always @(posedge pixclk) hSync <= (CounterX>=656) && (CounterX<752);
always @(posedge pixclk) vSync <= (CounterY>=490) && (CounterY<492);


wire [7:0] W = {8{CounterX[7:0]==CounterY[7:0]}};
wire [7:0] A = {8{CounterX[7:5]==3'h2 && CounterY[7:5]==3'h2}};
reg [7:0] red, green, blue;
always @(posedge pixclk) red <= ({CounterX[5:0] & {6{CounterY[4:3]==~CounterX[4:3]}}, 2'b00} | W) & ~A;
always @(posedge pixclk) green <= (CounterX[7:0] & {8{CounterY[6]}} | W) & ~A;
always @(posedge pixclk) blue <= CounterY[7:0] | W | A;


wire [9:0] TMDS_red, TMDS_green, TMDS_blue;
TMDS_encoder encode_R(.clk(pixclk), .VD(red  ), .CD(2'b00)        , .VDE(DrawArea), .TMDS(TMDS_red));
TMDS_encoder encode_G(.clk(pixclk), .VD(green), .CD(2'b00)        , .VDE(DrawArea), .TMDS(TMDS_green));
TMDS_encoder encode_B(.clk(pixclk), .VD(blue ), .CD({vSync,hSync}), .VDE(DrawArea), .TMDS(TMDS_blue));


wire clk_TMDS, DCM_TMDS_CLKFX;
DCM_SP #(.CLKFX_MULTIPLY(10)) DCM_TMDS_inst(.CLKIN(pixclk), .CLKFX(DCM_TMDS_CLKFX), .RST(1'b0));
BUFG BUFG_TMDSp(.I(DCM_TMDS_CLKFX), .O(clk_TMDS));


reg [3:0] TMDS_mod10=0;
reg [9:0] TMDS_shift_red=0, TMDS_shift_green=0, TMDS_shift_blue=0;
reg TMDS_shift_load=0;
always @(posedge clk_TMDS) TMDS_shift_load <= (TMDS_mod10==4'd9);

always @(posedge clk_TMDS)
begin
	TMDS_shift_red   <= TMDS_shift_load ? TMDS_red   : TMDS_shift_red  [9:1];
	TMDS_shift_green <= TMDS_shift_load ? TMDS_green : TMDS_shift_green[9:1];
	TMDS_shift_blue  <= TMDS_shift_load ? TMDS_blue  : TMDS_shift_blue [9:1];	
	TMDS_mod10 <= (TMDS_mod10==4'd9) ? 4'd0 : TMDS_mod10+4'd1;
end

OBUFDS OBUFDS_red  (.I(TMDS_shift_red  [0]), .O(TMDSp[2]), .OB(TMDSn[2]));
OBUFDS OBUFDS_green(.I(TMDS_shift_green[0]), .O(TMDSp[1]), .OB(TMDSn[1]));
OBUFDS OBUFDS_blue (.I(TMDS_shift_blue [0]), .O(TMDSp[0]), .OB(TMDSn[0]));
OBUFDS OBUFDS_clock(.I(pixclk), .O(TMDSp_clock), .OB(TMDSn_clock));
endmodule
module HDMI_test(
	input pixclk,
	output [2:0] TMDSp, TMDSn,
	output TMDSp_clock, TMDSn_clock
);



reg [9:0] CounterX, CounterY;
reg hSync, vSync, DrawArea;
always @(posedge pixclk) DrawArea <= (CounterX<640) && (CounterY<480);

always @(posedge pixclk) CounterX <= (CounterX==799) ? 0 : CounterX+1;
always @(posedge pixclk) if(CounterX==799) CounterY <= (CounterY==524) ? 0 : CounterY+1;

always @(posedge pixclk) hSync <= (CounterX>=656) && (CounterX<752);
always @(posedge pixclk) vSync <= (CounterY>=490) && (CounterY<492);


wire [7:0] W = {8{CounterX[7:0]==CounterY[7:0]}};
wire [7:0] A = {8{CounterX[7:5]==3'h2 && CounterY[7:5]==3'h2}};
reg [7:0] red, green, blue;
always @(posedge pixclk) red <= ({CounterX[5:0] & {6{CounterY[4:3]==~CounterX[4:3]}}, 2'b00} | W) & ~A;
always @(posedge pixclk) green <= (CounterX[7:0] & {8{CounterY[6]}} | W) & ~A;
always @(posedge pixclk) blue <= CounterY[7:0] | W | A;


wire [9:0] TMDS_red, TMDS_green, TMDS_blue;
TMDS_encoder encode_R(.clk(pixclk), .VD(red  ), .CD(2'b00)        , .VDE(DrawArea), .TMDS(TMDS_red));
TMDS_encoder encode_G(.clk(pixclk), .VD(green), .CD(2'b00)        , .VDE(DrawArea), .TMDS(TMDS_green));
TMDS_encoder encode_B(.clk(pixclk), .VD(blue ), .CD({vSync,hSync}), .VDE(DrawArea), .TMDS(TMDS_blue));


wire clk_TMDS, DCM_TMDS_CLKFX;
DCM_SP #(.CLKFX_MULTIPLY(10)) DCM_TMDS_inst(.CLKIN(pixclk), .CLKFX(DCM_TMDS_CLKFX), .RST(1'b0));
BUFG BUFG_TMDSp(.I(DCM_TMDS_CLKFX), .O(clk_TMDS));


reg [3:0] TMDS_mod10=0;
reg [9:0] TMDS_shift_red=0, TMDS_shift_green=0, TMDS_shift_blue=0;
reg TMDS_shift_load=0;
always @(posedge clk_TMDS) TMDS_shift_load <= (TMDS_mod10==4'd9);

always @(posedge clk_TMDS)
begin
	TMDS_shift_red   <= TMDS_shift_load ? TMDS_red   : TMDS_shift_red  [9:1];
	TMDS_shift_green <= TMDS_shift_load ? TMDS_green : TMDS_shift_green[9:1];
	TMDS_shift_blue  <= TMDS_shift_load ? TMDS_blue  : TMDS_shift_blue [9:1];	
	TMDS_mod10 <= (TMDS_mod10==4'd9) ? 4'd0 : TMDS_mod10+4'd1;
end

OBUFDS OBUFDS_red  (.I(TMDS_shift_red  [0]), .O(TMDSp[2]), .OB(TMDSn[2]));
OBUFDS OBUFDS_green(.I(TMDS_shift_green[0]), .O(TMDSp[1]), .OB(TMDSn[1]));
OBUFDS OBUFDS_blue (.I(TMDS_shift_blue [0]), .O(TMDSp[0]), .OB(TMDSn[0]));
OBUFDS OBUFDS_clock(.I(pixclk), .O(TMDSp_clock), .OB(TMDSn_clock));
endmodule