data/full_repos/permissive/166115772/src/calcu-16.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/166115772/src/calcu-16.v:5: Little bit endian vector: MSB < LSB of bit range: 0:15\n    reg [0:15] regArray [0:7];  \n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/src/calcu-16.v:6: Little bit endian vector: MSB < LSB of bit range: 0:15\n    reg [0:15] pc = 0;  \n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/src/calcu-16.v:7: Little bit endian vector: MSB < LSB of bit range: 0:25\n    reg [0:25] ir;  \n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/src/calcu-16.v:10: Little bit endian vector: MSB < LSB of bit range: 0:25\n    reg [0:25] memory [0:65535];\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/src/calcu-16.v:12: Little bit endian vector: MSB < LSB of bit range: 0:3\n    reg [0:3] opcode;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/src/calcu-16.v:13: Little bit endian vector: MSB < LSB of bit range: 0:2\n    reg [0:2] regSel1;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/src/calcu-16.v:14: Little bit endian vector: MSB < LSB of bit range: 0:2\n    reg [0:2] regSel2;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/src/calcu-16.v:15: Little bit endian vector: MSB < LSB of bit range: 0:2\n    reg [0:2] regSel3;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/src/calcu-16.v:16: Little bit endian vector: MSB < LSB of bit range: 0:15\n    reg [0:15] immediate;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/166115772/src/calcu-16.v:18: Little bit endian vector: MSB < LSB of bit range: 0:16\n    reg [0:16] tmp;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/166115772/src/calcu-16.v:59: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 16 bits.\n                                                                      : ... In instance calcu16\n                memory[immediate + regArray[regSel2]] = regArray[regSel1];\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/166115772/src/calcu-16.v:61: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 26 bits.\n                                                                      : ... In instance calcu16\n                regArray[regSel1] = memory[immediate + regArray[regSel2]];\n                                  ^\n%Error: Exiting due to 12 warning(s)\n'
module calcu16 (
    input clk
);

    reg [0:15] regArray [0:7];
    reg [0:15] pc = 0;
    reg [0:25] ir;


    reg [0:25] memory [0:65535];

    reg [0:3] opcode;
    reg [0:2] regSel1;
    reg [0:2] regSel2;
    reg [0:2] regSel3;
    reg [0:15] immediate;

    reg [0:16] tmp;

    integer i;

    initial begin

        for (i = 0; i < 8; i = i + 1)
            regArray[i] <= 0;
        
        $readmemb("program.bin", memory);
        







    end

    always @(posedge clk) begin
        ir = memory[pc];

        opcode = ir[0:3];
        regSel1 = ir[4:6];
        regSel2 = ir[7:9];
        regSel3 = ir[10:12];
        immediate = ir[10:25];

        pc = pc + 1;
        
        case (opcode)
            4'b0001:
                regArray[regSel1] = regArray[regSel2] + regArray[regSel3];
            4'b0010:
                regArray[regSel1] = regArray[regSel2] + immediate;
            4'b0011:
                pc = immediate;
            4'b0100:
                pc = (regArray[regSel1] == regArray[regSel2]) ? immediate : pc;
            4'b0101:
                memory[immediate + regArray[regSel2]] = regArray[regSel1];
            4'b0110:
                regArray[regSel1] = memory[immediate + regArray[regSel2]];
            4'b0111:
                regArray[regSel1] = regArray[regSel2] ^ regArray[regSel3];
            4'b1000:
                regArray[regSel1] = regArray[regSel2] & regArray[regSel3];
        endcase
    end

endmodule
module calcu16 (
    input clk
);


    reg [0:15] regArray [0:7];
    reg [0:15] pc = 0;
    reg [0:25] ir;


    reg [0:25] memory [0:65535];

    reg [0:3] opcode;
    reg [0:2] regSel1;
    reg [0:2] regSel2;
    reg [0:2] regSel3;
    reg [0:15] immediate;

    reg [0:16] tmp;

    integer i;

    initial begin

        for (i = 0; i < 8; i = i + 1)
            regArray[i] <= 0;
        
        $readmemb("program.bin", memory);
        







    end

    always @(posedge clk) begin
        ir = memory[pc];

        opcode = ir[0:3];
        regSel1 = ir[4:6];
        regSel2 = ir[7:9];
        regSel3 = ir[10:12];
        immediate = ir[10:25];

        pc = pc + 1;
        
        case (opcode)
            4'b0001:
                regArray[regSel1] = regArray[regSel2] + regArray[regSel3];
            4'b0010:
                regArray[regSel1] = regArray[regSel2] + immediate;
            4'b0011:
                pc = immediate;
            4'b0100:
                pc = (regArray[regSel1] == regArray[regSel2]) ? immediate : pc;
            4'b0101:
                memory[immediate + regArray[regSel2]] = regArray[regSel1];
            4'b0110:
                regArray[regSel1] = memory[immediate + regArray[regSel2]];
            4'b0111:
                regArray[regSel1] = regArray[regSel2] ^ regArray[regSel3];
            4'b1000:
                regArray[regSel1] = regArray[regSel2] & regArray[regSel3];
        endcase
    end

endmodule