data/full_repos/permissive/155656868/src/seven_seg_display.v
data/verilator_xmls/13d9d865-9800-4c74-a4f7-c8e903df4ea6.xml
module seven_seg_display(clk, num, seven_seg_display);
	input  clk;
	input  [3:0] num;
	output reg [6:0] seven_seg_display;

	always @(posedge clk) begin
		case(num)
			4'b0000: seven_seg_display <= 7'b1000000;
			4'b0001: seven_seg_display <= 7'b1111001;
			4'b0010: seven_seg_display <= 7'b0100100;
			4'b0011: seven_seg_display <= 7'b0110000;
			4'b0100: seven_seg_display <= 7'b0011001;
			4'b0101: seven_seg_display <= 7'b0010010;
			4'b0110: seven_seg_display <= 7'b0000010;
			4'b0111: seven_seg_display <= 7'b1111000;
			4'b1000: seven_seg_display <= 7'b0000000;
			4'b1001: seven_seg_display <= 7'b0011000;
			4'b1010: seven_seg_display <= 7'b0001000;
			4'b1011: seven_seg_display <= 7'b0000011;
			4'b1100: seven_seg_display <= 7'b0100111;
			4'b1101: seven_seg_display <= 7'b0100001;
			4'b1110: seven_seg_display <= 7'b0000110;
			4'b1111: seven_seg_display <= 7'b0001110;
		endcase
	end
endmodule
module seven_seg_display(clk, num, seven_seg_display);

	input  clk;
	input  [3:0] num;
	output reg [6:0] seven_seg_display;

	always @(posedge clk) begin
		case(num)
			4'b0000: seven_seg_display <= 7'b1000000;
			4'b0001: seven_seg_display <= 7'b1111001;
			4'b0010: seven_seg_display <= 7'b0100100;
			4'b0011: seven_seg_display <= 7'b0110000;
			4'b0100: seven_seg_display <= 7'b0011001;
			4'b0101: seven_seg_display <= 7'b0010010;
			4'b0110: seven_seg_display <= 7'b0000010;
			4'b0111: seven_seg_display <= 7'b1111000;
			4'b1000: seven_seg_display <= 7'b0000000;
			4'b1001: seven_seg_display <= 7'b0011000;
			4'b1010: seven_seg_display <= 7'b0001000;
			4'b1011: seven_seg_display <= 7'b0000011;
			4'b1100: seven_seg_display <= 7'b0100111;
			4'b1101: seven_seg_display <= 7'b0100001;
			4'b1110: seven_seg_display <= 7'b0000110;
			4'b1111: seven_seg_display <= 7'b0001110;
		endcase
	end
endmodule