data/full_repos/permissive/115035459/verilog/src/lib/generic.v
 line:299: before: "if"
1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d0; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:160: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d0; a <= 1; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:161: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d1; a <= 0; b <= 1; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:162: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d2; a <= 0; b <= 0; c <= 1; d <= 0; e <= 0; f <= 0; g <= 0; h <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:163: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d3; a <= 0; b <= 0; c <= 0; d <= 1; e <= 0; f <= 0; g <= 0; h <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d4; a <= 0; b <= 0; c <= 0; d <= 0; e <= 1; f <= 0; g <= 0; h <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d5; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 1; g <= 0; h <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d6; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 1; h <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:167: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d7; a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; f <= 0; g <= 0; h <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:169: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d0; a <= 0; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:170: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d1; a <= 1; b <= 0; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d2; a <= 1; b <= 1; c <= 0; d <= 1; e <= 1; f <= 1; g <= 1; h <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d3; a <= 1; b <= 1; c <= 1; d <= 0; e <= 1; f <= 1; g <= 1; h <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:173: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d4; a <= 1; b <= 1; c <= 1; d <= 1; e <= 0; f <= 1; g <= 1; h <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d5; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 0; g <= 1; h <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d6; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 0; h <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:176: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d7; a <= 1; b <= 1; c <= 1; d <= 1; e <= 1; f <= 1; g <= 1; h <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:261: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:262: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:263: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:264: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:265: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d4;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:266: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:267: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d6;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:268: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d7;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:270: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d7;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:271: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d6;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:272: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:273: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d4;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:274: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:275: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:276: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:277: Unsupported: Ignoring delay on this delayed statement.\n  #1; sel <= 3\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:280: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:304: Unsupported: Ignoring delay on this delayed statement.\n    2\'b00:   begin #DELAY_RISE; O0_prev <= O0; end\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:305: Unsupported: Ignoring delay on this delayed statement.\n    2\'b01:   begin #DELAY_RISE; O1 <= O0; O0_prev <= O0; end\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:306: Unsupported: Ignoring delay on this delayed statement.\n    2\'b10:   begin #DELAY_FALL; O1 <= O0; O0_prev <= O0; end\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:307: Unsupported: Ignoring delay on this delayed statement.\n    default: begin #DELAY_RISE; O0_prev <= O0; end\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:395: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:397: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d00; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:398: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d01; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:399: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d02; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:400: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d03; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:401: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d04; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:402: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d05; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:403: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d06; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:404: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d07; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:405: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d08; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:406: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d09; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:407: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d10; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:408: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d11; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:409: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d12; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:410: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d13; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:411: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d14; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:412: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_coarse <= 4\'d15; #100; enable <= 1;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:413: Unsupported: Ignoring delay on this delayed statement.\n  #4000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:414: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_medium <= 2\'d0; #100; enable <= 1;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:415: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_medium <= 2\'d1; #100; enable <= 1;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:416: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_medium <= 2\'d2; #100; enable <= 1;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:417: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_medium <= 2\'d3; #100; enable <= 1;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:418: Unsupported: Ignoring delay on this delayed statement.\n  #4000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:419: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_fine <= 2\'d0; #100; enable <= 1;\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:420: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_fine <= 2\'d1; #100; enable <= 1;\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:421: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_fine <= 2\'d2; #100; enable <= 1;\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:422: Unsupported: Ignoring delay on this delayed statement.\n  #2000; enable <= 0; select_fine <= 2\'d3; #100; enable <= 1;\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:423: Unsupported: Ignoring delay on this delayed statement.\n  #4000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:425: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:492: Unsupported: Ignoring delay on this delayed statement.\n  #HALF_PERIOD_OF_CLOCK_NS;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:567: Unsupported: Ignoring delay on this delayed statement.\n  #100; minuend <= 47;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:568: Unsupported: Ignoring delay on this delayed statement.\n  #STEP_DURATION; subtrahend <= 11;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:569: Unsupported: Ignoring delay on this delayed statement.\n  #STEP_DURATION; subtrahend <= 17;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:570: Unsupported: Ignoring delay on this delayed statement.\n  #STEP_DURATION; subtrahend <= 27;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:571: Unsupported: Ignoring delay on this delayed statement.\n  #STEP_DURATION; subtrahend <= 37;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:572: Unsupported: Ignoring delay on this delayed statement.\n  #STEP_DURATION; subtrahend <= 47;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:573: Unsupported: Ignoring delay on this delayed statement.\n  #STEP_DURATION; subtrahend <= 48;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:574: Unsupported: Ignoring delay on this delayed statement.\n  #STEP_DURATION; subtrahend <= 49;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:575: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:576: Unsupported: Ignoring delay on this delayed statement.\n  #STEP_DURATION; minuend <= 53;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:577: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:19: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                    : ... Top module \'mux\'\nmodule mux #(\n       ^~~\n                                                                                    : ... Top module \'mux_2to1\'\nmodule mux_2to1 #(\n       ^~~~~~~~\n                                                                                    : ... Top module \'mux_4to1\'\nmodule mux_4to1 #(\n       ^~~~~~~~\n                                                                                    : ... Top module \'mux_16to1\'\nmodule mux_16to1 #(\n       ^~~~~~~~~\n                                                                                    : ... Top module \'mux_32to1\'\nmodule mux_32to1 #(\n       ^~~~~~~~~\n                                                                                    : ... Top module \'mux_8to1_tb\'\nmodule mux_8to1_tb;\n       ^~~~~~~~~~~\n                                                                                    : ... Top module \'demux_1to16\'\nmodule demux_1to16 #(\n       ^~~~~~~~~~~\n                                                                                    : ... Top module \'demux_1to32\'\nmodule demux_1to32 #(\n       ^~~~~~~~~~~\n                                                                                    : ... Top module \'demux_1to8_tb\'\nmodule demux_1to8_tb;\n       ^~~~~~~~~~~~~\n                                                                                    : ... Top module \'ring_oscillator_tb\'\nmodule ring_oscillator_tb;\n       ^~~~~~~~~~~~~~~~~~\n                                                                                    : ... Top module \'bus_entry_3state\'\nmodule bus_entry_3state #(\n       ^~~~~~~~~~~~~~~~\n                                                                                    : ... Top module \'ddr\'\nmodule ddr (\n       ^~~\n                                                                                    : ... Top module \'pipeline\'\nmodule pipeline #(\n       ^~~~~~~~\n                                                                                    : ... Top module \'arithmetic_pipeline_tb\'\nmodule arithmetic_pipeline_tb();\n       ^~~~~~~~~~~~~~~~~~~~~~\n                                                                                    : ... Top module \'cdc_pipeline\'\nmodule cdc_pipeline #(\n       ^~~~~~~~~~~~\n                                                                                    : ... Top module \'resync\'\nmodule resync #(\n       ^~~~~~\n                                                                                    : ... Top module \'bitslip\'\nmodule bitslip #(\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:365: Bit extraction of var[23:0] requires 5 bit index, not 4 bits.\n                                                                                  : ... In instance ring_oscillator_tb.ro\n and_gate #(.DELAY_RISE(COARSE_DELAY), .DELAY_FALL(COARSE_DELAY), .TESTBENCH(TESTBENCH)) coarse_bride (.I0(stage[select_coarse]), .I1(enable), .O(stage[number_of_coarse_stages]));\n                                                                                                                ^\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/generic.v:509: Cannot find file containing module: \'ODDR2\'\n ODDR2 #(.DDR_ALIGNMENT("NONE")) ddr (.C0(clock0), .C1(clock180), .CE(1\'b1), .D0(data0_in), .D1(data1_in), .R(reset), .S(1\'b0), .Q(data_out));\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.v\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/ODDR2.sv\n             ODDR2\n             ODDR2.v\n             ODDR2.sv\n             obj_dir/ODDR2\n             obj_dir/ODDR2.v\n             obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s), 105 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module demux_1to32 #(
	parameter WIDTH = 1,
	parameter [WIDTH-1:0] default_value = 0
) (
	input [WIDTH-1:0] in,
	input [4:0] sel,
	output [WIDTH-1:0]
		out00, out01, out02, out03, out04, out05, out06, out07,
		out08, out09, out10, out11, out12, out13, out14, out15,
		out16, out17, out18, out19, out20, out21, out22, out23,
		out24, out25, out26, out27, out28, out29, out30, out31
);
	assign out00 = (sel==5'd00) ? in : default_value;
	assign out01 = (sel==5'd01) ? in : default_value;
	assign out02 = (sel==5'd02) ? in : default_value;
	assign out03 = (sel==5'd03) ? in : default_value;
	assign out04 = (sel==5'd04) ? in : default_value;
	assign out05 = (sel==5'd05) ? in : default_value;
	assign out06 = (sel==5'd06) ? in : default_value;
	assign out07 = (sel==5'd07) ? in : default_value;
	assign out08 = (sel==5'd08) ? in : default_value;
	assign out09 = (sel==5'd09) ? in : default_value;
	assign out10 = (sel==5'd10) ? in : default_value;
	assign out11 = (sel==5'd11) ? in : default_value;
	assign out12 = (sel==5'd12) ? in : default_value;
	assign out13 = (sel==5'd13) ? in : default_value;
	assign out14 = (sel==5'd14) ? in : default_value;
	assign out15 = (sel==5'd15) ? in : default_value;
	assign out16 = (sel==5'd16) ? in : default_value;
	assign out17 = (sel==5'd17) ? in : default_value;
	assign out18 = (sel==5'd18) ? in : default_value;
	assign out19 = (sel==5'd19) ? in : default_value;
	assign out20 = (sel==5'd20) ? in : default_value;
	assign out21 = (sel==5'd21) ? in : default_value;
	assign out22 = (sel==5'd22) ? in : default_value;
	assign out23 = (sel==5'd23) ? in : default_value;
	assign out24 = (sel==5'd24) ? in : default_value;
	assign out25 = (sel==5'd25) ? in : default_value;
	assign out26 = (sel==5'd26) ? in : default_value;
	assign out27 = (sel==5'd27) ? in : default_value;
	assign out28 = (sel==5'd28) ? in : default_value;
	assign out29 = (sel==5'd29) ? in : default_value;
	assign out30 = (sel==5'd30) ? in : default_value;
	assign out31 = (sel==5'd31) ? in : default_value;
endmodule
module demux_1to32 #(
	parameter WIDTH = 1,
	parameter [WIDTH-1:0] default_value = 0
) (
	input [WIDTH-1:0] in,
	input [4:0] sel,
	output [WIDTH-1:0]
		out00, out01, out02, out03, out04, out05, out06, out07,
		out08, out09, out10, out11, out12, out13, out14, out15,
		out16, out17, out18, out19, out20, out21, out22, out23,
		out24, out25, out26, out27, out28, out29, out30, out31
);

	assign out00 = (sel==5'd00) ? in : default_value;
	assign out01 = (sel==5'd01) ? in : default_value;
	assign out02 = (sel==5'd02) ? in : default_value;
	assign out03 = (sel==5'd03) ? in : default_value;
	assign out04 = (sel==5'd04) ? in : default_value;
	assign out05 = (sel==5'd05) ? in : default_value;
	assign out06 = (sel==5'd06) ? in : default_value;
	assign out07 = (sel==5'd07) ? in : default_value;
	assign out08 = (sel==5'd08) ? in : default_value;
	assign out09 = (sel==5'd09) ? in : default_value;
	assign out10 = (sel==5'd10) ? in : default_value;
	assign out11 = (sel==5'd11) ? in : default_value;
	assign out12 = (sel==5'd12) ? in : default_value;
	assign out13 = (sel==5'd13) ? in : default_value;
	assign out14 = (sel==5'd14) ? in : default_value;
	assign out15 = (sel==5'd15) ? in : default_value;
	assign out16 = (sel==5'd16) ? in : default_value;
	assign out17 = (sel==5'd17) ? in : default_value;
	assign out18 = (sel==5'd18) ? in : default_value;
	assign out19 = (sel==5'd19) ? in : default_value;
	assign out20 = (sel==5'd20) ? in : default_value;
	assign out21 = (sel==5'd21) ? in : default_value;
	assign out22 = (sel==5'd22) ? in : default_value;
	assign out23 = (sel==5'd23) ? in : default_value;
	assign out24 = (sel==5'd24) ? in : default_value;
	assign out25 = (sel==5'd25) ? in : default_value;
	assign out26 = (sel==5'd26) ? in : default_value;
	assign out27 = (sel==5'd27) ? in : default_value;
	assign out28 = (sel==5'd28) ? in : default_value;
	assign out29 = (sel==5'd29) ? in : default_value;
	assign out30 = (sel==5'd30) ? in : default_value;
	assign out31 = (sel==5'd31) ? in : default_value;
endmodule