data/full_repos/permissive/209644662/hardware/generator_z/impl/verif/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/209644662/hardware/generator_z/impl/verif/tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    always #0.625 clk <= ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/209644662/hardware/generator_z/impl/verif/tb.v:91: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb\n  d0 <= $random;\n     ^~\n%Warning-WIDTH: data/full_repos/permissive/209644662/hardware/generator_z/impl/verif/tb.v:92: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb\n  d1 <= $random;\n     ^~\n%Warning-WIDTH: data/full_repos/permissive/209644662/hardware/generator_z/impl/verif/tb.v:93: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb\n  d2 <= $random;\n     ^~\n%Warning-WIDTH: data/full_repos/permissive/209644662/hardware/generator_z/impl/verif/tb.v:94: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                            : ... In instance tb\n  d3 <= $random;\n     ^~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/impl/verif/tb.v:118: Cannot find file containing module: \'top\'\ntop dut(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/209644662/hardware/generator_z/impl/verif,data/full_repos/permissive/209644662/top\n             data/full_repos/permissive/209644662/hardware/generator_z/impl/verif,data/full_repos/permissive/209644662/top.v\n             data/full_repos/permissive/209644662/hardware/generator_z/impl/verif,data/full_repos/permissive/209644662/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();





    reg clk;
    reg [3:0] reset_count;
    reg [19:0] count;

    reg [15:0] d0;
    reg [15:0] d1;
    reg [15:0] d2;
    reg [15:0] d3;
    reg ren;
    reg wen;
    wire [15:0] dout;
    wire [15:0] cout;
    wire valid;
    wire af;
        
    wire reset;
    
    initial begin
      clk<=1'b1;
      reset_count<=4'd0;
      count<=0;
      wen<=0;
      ren<=0;
    end
    
    always #0.625 clk <= ~clk;
    
    always @(posedge clk) begin
      if (!(&reset_count)) begin 
        reset_count <= reset_count + 1;
      end
      count <= count + 1;
    end
    
    assign reset = !reset_count[3];
    






    integer    config_data_file    ;
    reg [31:0] config_addr_i;
    reg [31:0] config_data_i;
    reg [31:0] config_addr;
    reg [31:0] config_data;
    reg tile_config_done;

    initial begin
      config_addr_i <= 0;
      config_data_i <= 0;
      config_addr <= 0;
      config_data <= 0;
      tile_config_done <= 0;
    end
    `define NULL 0
    
    initial begin
      config_data_file = $fopen("tile_config.dat", "r");
      if (config_data_file == `NULL) begin
        $display("config_data_file handle was NULL");
        $finish;
      end
    end
    always @(posedge clk) begin
      if (!reset) begin
        $fscanf(config_data_file, "%h %h\n", config_addr_i,config_data_i); 
        if (!$feof(config_data_file)) begin
          config_addr <= config_addr_i;
          config_data <= config_data_i;
        end else begin
          tile_config_done <= 1'b1;
        end
      end
    end






always @(posedge clk) begin
  d0 <= $random;
  d1 <= $random;
  d2 <= $random;
  d3 <= $random;
end


always @(posedge clk) begin
  if ((count==20'd100)||(count==20'd612)||(count==20'd620)||(count==20'd1132)||(count==20'd1135)||(count==20'd1647)) begin
    wen<=~wen;
  end
end

always @(posedge clk) begin
  if (count==20'd110) begin
    ren<=~ren;
  end else if (count==20'd621) begin
    ren<=~ren;
  end
end







top dut(

.clk_in(clk),
.config_addr_in(config_addr),
.config_data_in(config_data),
.reset_in(reset)
);

endmodule
module tb();






    reg clk;
    reg [3:0] reset_count;
    reg [19:0] count;

    reg [15:0] d0;
    reg [15:0] d1;
    reg [15:0] d2;
    reg [15:0] d3;
    reg ren;
    reg wen;
    wire [15:0] dout;
    wire [15:0] cout;
    wire valid;
    wire af;
        
    wire reset;
    
    initial begin
      clk<=1'b1;
      reset_count<=4'd0;
      count<=0;
      wen<=0;
      ren<=0;
    end
    
    always #0.625 clk <= ~clk;
    
    always @(posedge clk) begin
      if (!(&reset_count)) begin 
        reset_count <= reset_count + 1;
      end
      count <= count + 1;
    end
    
    assign reset = !reset_count[3];
    






    integer    config_data_file    ;
    reg [31:0] config_addr_i;
    reg [31:0] config_data_i;
    reg [31:0] config_addr;
    reg [31:0] config_data;
    reg tile_config_done;

    initial begin
      config_addr_i <= 0;
      config_data_i <= 0;
      config_addr <= 0;
      config_data <= 0;
      tile_config_done <= 0;
    end
    `define NULL 0
    
    initial begin
      config_data_file = $fopen("tile_config.dat", "r");
      if (config_data_file == `NULL) begin
        $display("config_data_file handle was NULL");
        $finish;
      end
    end
    always @(posedge clk) begin
      if (!reset) begin
        $fscanf(config_data_file, "%h %h\n", config_addr_i,config_data_i); 
        if (!$feof(config_data_file)) begin
          config_addr <= config_addr_i;
          config_data <= config_data_i;
        end else begin
          tile_config_done <= 1'b1;
        end
      end
    end






always @(posedge clk) begin
  d0 <= $random;
  d1 <= $random;
  d2 <= $random;
  d3 <= $random;
end


always @(posedge clk) begin
  if ((count==20'd100)||(count==20'd612)||(count==20'd620)||(count==20'd1132)||(count==20'd1135)||(count==20'd1647)) begin
    wen<=~wen;
  end
end

always @(posedge clk) begin
  if (count==20'd110) begin
    ren<=~ren;
  end else if (count==20'd621) begin
    ren<=~ren;
  end
end







top dut(

.clk_in(clk),
.config_addr_in(config_addr),
.config_data_in(config_data),
.reset_in(reset)
);

endmodule