data/full_repos/permissive/12014746/hw/fpga/source/pcie_if/tx_engine.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/ceac5a42-e85d-4f21-909f-c88116e08154.xml
module tx_engine    #(

  parameter C_DATA_WIDTH = 64,
  parameter KEEP_WIDTH = C_DATA_WIDTH / 8
)(

  input                           clk_i,
  input                           rst_n,


  input                           s_axis_tx_tready,
  output  reg [C_DATA_WIDTH-1:0]  s_axis_tx_tdata,
  output  reg [KEEP_WIDTH-1:0]    s_axis_tx_tkeep,
  output  reg                     s_axis_tx_tlast,
  output  reg                     s_axis_tx_tvalid,
  output                          tx_src_dsc,

  input                           req_compl_wd_i,
  output reg                      compl_done_o,
  input [2:0]                     req_tc_i,
  input                           req_td_i,
  input                           req_ep_i,
  input [1:0]                     req_attr_i,
  input [9:0]                     req_len_i,
  input [15:0]                    req_rid_i,
  input [7:0]                     req_tag_i,
  input [6:0]                     req_addr_i,
  input [15:0]                    completer_id_i,

  input [31:0]                    reg_data_i,
  input                           sys_ddr_dma_req_i,
  input [31:0]                    sys_ddr_dma_rd_addr_i,
  input [11:0]                    sys_ddr_dma_req_len_i,
  output reg                      sys_ddr_dma_req_done_o,
  input [7:0]                     sys_ddr_dma_req_tag_i, 
  input [31:0]                    ddr_sys_dma_wr_addr_i,

  input                           sys_user_dma_req_i,
  output reg                      sys_user_dma_req_done_o,
  input [11:0]                    sys_user_dma_req_len_i,
  input [31:0]                    sys_user_dma_rd_addr_i,
  input [7:0]                     sys_user_dma_tag_i,
  input                           ddr_pc_dma_sys_addr_load_i,

  input [63:0]                    dma_rd_data_i,
  input                           dma_fifo_data_avail_i,
  output reg                      rd_fifo_rd_o,

  input                           user_str_data_avail_i,
  output reg                      user_str_dma_done_o,
  input [31:0]                    user_sys_dma_wr_addr_i,
  output reg                      user_str_data_rd_o,
  input [63:0]                    user_str_data_i,
  input [4:0]                     user_str_len_i,

  input                           intr_req_i,
  output reg                      intr_req_done_o,
  output reg                      cfg_interrupt_o,
  input                           cfg_interrupt_rdy_i
);


    localparam IDLE         = 'd0,
               SEND_DATA    = 'd1,
               SEND_ACK_CPLD= 'd2,
               SEND_DMA_REQ = 'd3,
               WR_HD1       = 'd4,
               WR_HD2       = 'd5,
               WR_DATA      = 'd6,
               REQ_INTR     = 'd7,
               WR_UH        = 'd8,
               WR_USR_DATA  = 'd9,
               USER_DMA_REQ = 'd10,
               SEND_ACK_DMA = 'd11;



    localparam  MEM_RD = 7'b0000000,
               MEM_WR = 7'b1000000,
               CPLD   = 7'b1001010;

    reg [3:0]      state;
    reg [31:0]     rd_data_p;
    reg [31:0]     user_rd_data_p;
    reg [4:0]      wr_cntr;
    reg [31:0]     ddr_sys_dma_mem_addr;
    reg [31:0]     user1_sys_dma_mem_addr;
    reg [31:0]     user2_sys_dma_mem_addr;
    wire [5:0]     user_wr_len;


    assign tx_src_dsc = 1'b0;
    assign user_wr_len = user_str_len_i*2;



    always @(posedge clk_i)
    begin
        if(ddr_pc_dma_sys_addr_load_i)
           ddr_sys_dma_mem_addr <= ddr_sys_dma_wr_addr_i;
        else if(state == WR_HD2)
           ddr_sys_dma_mem_addr <= ddr_sys_dma_mem_addr + 128;  
    end


    always@(posedge clk_i)
    begin
        rd_data_p         <= dma_rd_data_i[31:0];
        user_rd_data_p    <= user_str_data_i[31:0];
    end


    always @ ( posedge clk_i ) 
    begin
        if (!rst_n ) 
        begin
           s_axis_tx_tlast   <= 1'b0;
           s_axis_tx_tvalid  <= 1'b0;
           s_axis_tx_tkeep   <= {KEEP_WIDTH{1'b0}};
           compl_done_o      <= 1'b0;
           sys_ddr_dma_req_done_o    <= 1'b0;
           wr_cntr           <= 0;
           intr_req_done_o   <=  1'b0;
           user_str_data_rd_o <= 1'b0;
           state             <= IDLE;
           user_str_dma_done_o <= 1'b0;
			  rd_fifo_rd_o <=  1'b0;
        end 
        else 
        begin
            case (state)
                IDLE : begin
                    s_axis_tx_tlast  <= 1'b0;
                    s_axis_tx_tvalid <= 1'b0;
                    intr_req_done_o  <=  1'b0;
                    wr_cntr <= 0;
                    if (req_compl_wd_i)
                    begin
                        s_axis_tx_tlast  <= 1'b0;
                        s_axis_tx_tvalid <= 1'b1;

                        s_axis_tx_tdata  <= {
                                              completer_id_i,
                                              {3'b0},
                                              {1'b0},
                                              {12'd4},
                                              {1'b0},
                                              CPLD,
                                              {1'b0},
                                              req_tc_i,
                                              {4'b0},
                                              req_td_i,
                                              req_ep_i,
                                              req_attr_i,
                                              {2'b0},
                                              req_len_i
                                              };
                        s_axis_tx_tkeep   <=  8'hFF;
                        state             <= SEND_DATA;
                    end   
                    else if(sys_ddr_dma_req_i)
                    begin
                      s_axis_tx_tlast  <= 1'b0;
                      s_axis_tx_tvalid <= 1'b1;
                      s_axis_tx_tdata  <= {
                                            completer_id_i,
                                            sys_ddr_dma_req_tag_i,
                                            {4'b1111},
                                            {4'b1111},
                                            {1'b0},
                                            MEM_RD,
                                            {1'b0},
                                            {3'b0},
                                            {4'b0},
                                            1'b0,
                                            1'b0,
                                            {2'b0},
                                            {2'b0},
                                            sys_ddr_dma_req_len_i[11:2]
                                            };
                        s_axis_tx_tkeep   <=  8'hFF;
                        state             <= SEND_DMA_REQ;
                    end 
                    else if(sys_user_dma_req_i)
                    begin
                        s_axis_tx_tlast  <= 1'b0;
                        s_axis_tx_tvalid <= 1'b1;
                        s_axis_tx_tdata  <= {
                                            completer_id_i,
                                            sys_user_dma_tag_i,
                                            {4'b1111},
                                            {4'b1111},
                                            {1'b0},
                                            MEM_RD,
                                            {1'b0},
                                            {3'b0},
                                            {4'b0},
                                            1'b0,
                                            1'b0,
                                            {2'b0},
                                            {2'b0},
                                            sys_user_dma_req_len_i[11:2]
                                            };
                        s_axis_tx_tkeep   <=  8'hFF;
                        state             <= USER_DMA_REQ;
                    end 
                    else if(dma_fifo_data_avail_i & s_axis_tx_tready)
                    begin
                        rd_fifo_rd_o <=  1'b1;
                        state        <=  WR_HD1;
                    end
                    else if(user_str_data_avail_i & s_axis_tx_tready)
                    begin
                        s_axis_tx_tvalid   <=  1'b1;
                        s_axis_tx_tdata    <=  {
                                                completer_id_i,
                                                    8'h00,
                                                    8'hFF,
                                                    1'b0,
                                                    MEM_WR,
                                                    1'b0,
                                                    3'b000,
                                                    4'b0000,
                                                    1'b0,
                                                    1'b0,
                                                    2'b00,
                                                    2'b00,
                                                    {4'h0,user_wr_len}
                                                };
                        s_axis_tx_tkeep         <=  8'hFF;
                        state                   <=  WR_UH;
                        user_str_data_rd_o      <=  1'b1;
                        wr_cntr                 <=  user_str_len_i;
                    end
                    else if(intr_req_i & ~intr_req_done_o)
                        state       <=  REQ_INTR;
                    else 
                    begin
                        s_axis_tx_tlast   <= 1'b0;
                        s_axis_tx_tvalid  <= 1'b0;
                        s_axis_tx_tdata   <= 64'b0;
                        s_axis_tx_tkeep   <= 8'h00;
                        compl_done_o      <= 1'b0;
                    end
                end
                
                SEND_DATA : begin
                    if (s_axis_tx_tready) 
                    begin
                        s_axis_tx_tlast  <= 1'b1;
                        s_axis_tx_tvalid <= 1'b1;

                        s_axis_tx_tdata  <= {
                                        reg_data_i,
                                        req_rid_i,
                                        req_tag_i,
                                        {1'b0},
                                        req_addr_i
                                        };
                        s_axis_tx_tkeep   <= 8'hFF;
                        state             <= SEND_ACK_CPLD;
                    end 
                    else
                        state             <= SEND_DATA;
                end
                
                SEND_ACK_CPLD:begin
                    if(~req_compl_wd_i)
                    begin
                        compl_done_o   <= 1'b0;
                        state          <= IDLE;
                    end
                    if (s_axis_tx_tready) 
                    begin
                        compl_done_o           <= req_compl_wd_i;
                        s_axis_tx_tlast        <= 1'b0;
                        s_axis_tx_tvalid       <= 1'b0;
                    end
                end
                 
                SEND_ACK_DMA:begin
                    sys_ddr_dma_req_done_o <= 1'b0;
                    sys_user_dma_req_done_o <= 1'b0;
                    if (s_axis_tx_tready) 
                    begin
                        s_axis_tx_tlast        <= 1'b0;
                        s_axis_tx_tvalid       <= 1'b0;
                        state                  <= IDLE;
                    end
                end
 
                SEND_DMA_REQ:begin
                    if (s_axis_tx_tready) 
                    begin
                        s_axis_tx_tlast  <= 1'b1;
                        s_axis_tx_tvalid <= 1'b1;
                        s_axis_tx_tdata  <= {32'h00000000,sys_ddr_dma_rd_addr_i};
                        s_axis_tx_tkeep  <= 8'h0F;
                        state            <= SEND_ACK_DMA;
                        sys_ddr_dma_req_done_o <= 1'b1;
                    end
                    else
                        state            <= SEND_DMA_REQ;
                end

                USER_DMA_REQ:begin
                    if (s_axis_tx_tready) 
                    begin
                        s_axis_tx_tlast  <= 1'b1;
                        s_axis_tx_tvalid <= 1'b1;
                        s_axis_tx_tdata  <= {32'h00000000,sys_user_dma_rd_addr_i};
                        s_axis_tx_tkeep  <= 8'h0F;
                        state            <= SEND_ACK_DMA;
                        sys_user_dma_req_done_o <= 1'b1;
                    end
                    else
                        state            <= USER_DMA_REQ;
                    end
                WR_HD1:begin
                    s_axis_tx_tvalid        <=  1'b1;
                    s_axis_tx_tdata         <=  {
                                                completer_id_i,
                                                8'h00,
                                                8'hFF,
                                                1'b0,
                                                MEM_WR,
                                                1'b0,
                                                3'b000,
                                                4'b0000,
                                                1'b0,
                                                1'b0,
                                                2'b00,
                                                2'b00,
                                                10'd32
                                                };
                    s_axis_tx_tkeep         <=  8'hFF;
                    state                   <=  WR_HD2;
                end
                WR_HD2:begin
                    state                   <=  WR_DATA;
                    s_axis_tx_tdata[31:0]   <=  ddr_sys_dma_mem_addr;
                    s_axis_tx_tdata[63:32]  <=  dma_rd_data_i[63:32];
                    s_axis_tx_tkeep         <=  8'hFF;
                end
                WR_DATA:begin
                    if(wr_cntr == 13)
                        rd_fifo_rd_o    <=    1'b0;
                    if(wr_cntr == 15)
                    begin
                        s_axis_tx_tlast <=    1'b1;
                        s_axis_tx_tkeep <=    8'h0F;
                    end
                    if(wr_cntr == 16)
                    begin
                       state            <=    IDLE;
                       s_axis_tx_tlast  <=    1'b0;
                       s_axis_tx_tvalid <=    1'b0;
                    end
                    wr_cntr             <=    wr_cntr + 1'b1;
                    s_axis_tx_tdata     <=    {dma_rd_data_i[63:32],rd_data_p};
                end
                WR_UH:begin
                    state                   <=  WR_USR_DATA;
                    s_axis_tx_tdata[31:0]   <=  user_sys_dma_wr_addr_i;
                    s_axis_tx_tdata[63:32]  <=  user_str_data_i[63:32];
                    s_axis_tx_tkeep         <=  8'hFF;
                    if(wr_cntr==1)
                    begin
                        user_str_data_rd_o    <=    1'b0;
                    end
                end 
                WR_USR_DATA:begin
                    if(wr_cntr == 2)
                        user_str_data_rd_o    <=    1'b0;
                    if(wr_cntr == 1)
                    begin
                        s_axis_tx_tlast     <= 1'b1;
                        s_axis_tx_tkeep     <= 8'h0F; 
                        user_str_dma_done_o <= 1'b1;
                    end  
                    if(wr_cntr == 0)
                    begin
                       state            <=    IDLE;
                       s_axis_tx_tlast  <=    1'b0;
                       s_axis_tx_tvalid <=    1'b0;
                       user_str_dma_done_o <= 1'b0;
                    end
                    wr_cntr             <=    wr_cntr - 1'b1;
                    s_axis_tx_tdata     <=    {user_str_data_i[63:32],user_rd_data_p};
                end 
                REQ_INTR:begin
                    cfg_interrupt_o <= 1'b1;
                    if(cfg_interrupt_rdy_i)
                    begin
                        cfg_interrupt_o <= 1'b0;
                        state           <= IDLE;
                        intr_req_done_o <= 1'b1;
                    end
                end
            endcase
        end
    end

endmodule
module tx_engine    #(

  parameter C_DATA_WIDTH = 64,
  parameter KEEP_WIDTH = C_DATA_WIDTH / 8
)(

  input                           clk_i,
  input                           rst_n,


  input                           s_axis_tx_tready,
  output  reg [C_DATA_WIDTH-1:0]  s_axis_tx_tdata,
  output  reg [KEEP_WIDTH-1:0]    s_axis_tx_tkeep,
  output  reg                     s_axis_tx_tlast,
  output  reg                     s_axis_tx_tvalid,
  output                          tx_src_dsc,

  input                           req_compl_wd_i,
  output reg                      compl_done_o,
  input [2:0]                     req_tc_i,
  input                           req_td_i,
  input                           req_ep_i,
  input [1:0]                     req_attr_i,
  input [9:0]                     req_len_i,
  input [15:0]                    req_rid_i,
  input [7:0]                     req_tag_i,
  input [6:0]                     req_addr_i,
  input [15:0]                    completer_id_i,

  input [31:0]                    reg_data_i,
  input                           sys_ddr_dma_req_i,
  input [31:0]                    sys_ddr_dma_rd_addr_i,
  input [11:0]                    sys_ddr_dma_req_len_i,
  output reg                      sys_ddr_dma_req_done_o,
  input [7:0]                     sys_ddr_dma_req_tag_i, 
  input [31:0]                    ddr_sys_dma_wr_addr_i,

  input                           sys_user_dma_req_i,
  output reg                      sys_user_dma_req_done_o,
  input [11:0]                    sys_user_dma_req_len_i,
  input [31:0]                    sys_user_dma_rd_addr_i,
  input [7:0]                     sys_user_dma_tag_i,
  input                           ddr_pc_dma_sys_addr_load_i,

  input [63:0]                    dma_rd_data_i,
  input                           dma_fifo_data_avail_i,
  output reg                      rd_fifo_rd_o,

  input                           user_str_data_avail_i,
  output reg                      user_str_dma_done_o,
  input [31:0]                    user_sys_dma_wr_addr_i,
  output reg                      user_str_data_rd_o,
  input [63:0]                    user_str_data_i,
  input [4:0]                     user_str_len_i,

  input                           intr_req_i,
  output reg                      intr_req_done_o,
  output reg                      cfg_interrupt_o,
  input                           cfg_interrupt_rdy_i
);



    localparam IDLE         = 'd0,
               SEND_DATA    = 'd1,
               SEND_ACK_CPLD= 'd2,
               SEND_DMA_REQ = 'd3,
               WR_HD1       = 'd4,
               WR_HD2       = 'd5,
               WR_DATA      = 'd6,
               REQ_INTR     = 'd7,
               WR_UH        = 'd8,
               WR_USR_DATA  = 'd9,
               USER_DMA_REQ = 'd10,
               SEND_ACK_DMA = 'd11;



    localparam  MEM_RD = 7'b0000000,
               MEM_WR = 7'b1000000,
               CPLD   = 7'b1001010;

    reg [3:0]      state;
    reg [31:0]     rd_data_p;
    reg [31:0]     user_rd_data_p;
    reg [4:0]      wr_cntr;
    reg [31:0]     ddr_sys_dma_mem_addr;
    reg [31:0]     user1_sys_dma_mem_addr;
    reg [31:0]     user2_sys_dma_mem_addr;
    wire [5:0]     user_wr_len;


    assign tx_src_dsc = 1'b0;
    assign user_wr_len = user_str_len_i*2;



    always @(posedge clk_i)
    begin
        if(ddr_pc_dma_sys_addr_load_i)
           ddr_sys_dma_mem_addr <= ddr_sys_dma_wr_addr_i;
        else if(state == WR_HD2)
           ddr_sys_dma_mem_addr <= ddr_sys_dma_mem_addr + 128;  
    end


    always@(posedge clk_i)
    begin
        rd_data_p         <= dma_rd_data_i[31:0];
        user_rd_data_p    <= user_str_data_i[31:0];
    end


    always @ ( posedge clk_i ) 
    begin
        if (!rst_n ) 
        begin
           s_axis_tx_tlast   <= 1'b0;
           s_axis_tx_tvalid  <= 1'b0;
           s_axis_tx_tkeep   <= {KEEP_WIDTH{1'b0}};
           compl_done_o      <= 1'b0;
           sys_ddr_dma_req_done_o    <= 1'b0;
           wr_cntr           <= 0;
           intr_req_done_o   <=  1'b0;
           user_str_data_rd_o <= 1'b0;
           state             <= IDLE;
           user_str_dma_done_o <= 1'b0;
			  rd_fifo_rd_o <=  1'b0;
        end 
        else 
        begin
            case (state)
                IDLE : begin
                    s_axis_tx_tlast  <= 1'b0;
                    s_axis_tx_tvalid <= 1'b0;
                    intr_req_done_o  <=  1'b0;
                    wr_cntr <= 0;
                    if (req_compl_wd_i)
                    begin
                        s_axis_tx_tlast  <= 1'b0;
                        s_axis_tx_tvalid <= 1'b1;

                        s_axis_tx_tdata  <= {
                                              completer_id_i,
                                              {3'b0},
                                              {1'b0},
                                              {12'd4},
                                              {1'b0},
                                              CPLD,
                                              {1'b0},
                                              req_tc_i,
                                              {4'b0},
                                              req_td_i,
                                              req_ep_i,
                                              req_attr_i,
                                              {2'b0},
                                              req_len_i
                                              };
                        s_axis_tx_tkeep   <=  8'hFF;
                        state             <= SEND_DATA;
                    end   
                    else if(sys_ddr_dma_req_i)
                    begin
                      s_axis_tx_tlast  <= 1'b0;
                      s_axis_tx_tvalid <= 1'b1;
                      s_axis_tx_tdata  <= {
                                            completer_id_i,
                                            sys_ddr_dma_req_tag_i,
                                            {4'b1111},
                                            {4'b1111},
                                            {1'b0},
                                            MEM_RD,
                                            {1'b0},
                                            {3'b0},
                                            {4'b0},
                                            1'b0,
                                            1'b0,
                                            {2'b0},
                                            {2'b0},
                                            sys_ddr_dma_req_len_i[11:2]
                                            };
                        s_axis_tx_tkeep   <=  8'hFF;
                        state             <= SEND_DMA_REQ;
                    end 
                    else if(sys_user_dma_req_i)
                    begin
                        s_axis_tx_tlast  <= 1'b0;
                        s_axis_tx_tvalid <= 1'b1;
                        s_axis_tx_tdata  <= {
                                            completer_id_i,
                                            sys_user_dma_tag_i,
                                            {4'b1111},
                                            {4'b1111},
                                            {1'b0},
                                            MEM_RD,
                                            {1'b0},
                                            {3'b0},
                                            {4'b0},
                                            1'b0,
                                            1'b0,
                                            {2'b0},
                                            {2'b0},
                                            sys_user_dma_req_len_i[11:2]
                                            };
                        s_axis_tx_tkeep   <=  8'hFF;
                        state             <= USER_DMA_REQ;
                    end 
                    else if(dma_fifo_data_avail_i & s_axis_tx_tready)
                    begin
                        rd_fifo_rd_o <=  1'b1;
                        state        <=  WR_HD1;
                    end
                    else if(user_str_data_avail_i & s_axis_tx_tready)
                    begin
                        s_axis_tx_tvalid   <=  1'b1;
                        s_axis_tx_tdata    <=  {
                                                completer_id_i,
                                                    8'h00,
                                                    8'hFF,
                                                    1'b0,
                                                    MEM_WR,
                                                    1'b0,
                                                    3'b000,
                                                    4'b0000,
                                                    1'b0,
                                                    1'b0,
                                                    2'b00,
                                                    2'b00,
                                                    {4'h0,user_wr_len}
                                                };
                        s_axis_tx_tkeep         <=  8'hFF;
                        state                   <=  WR_UH;
                        user_str_data_rd_o      <=  1'b1;
                        wr_cntr                 <=  user_str_len_i;
                    end
                    else if(intr_req_i & ~intr_req_done_o)
                        state       <=  REQ_INTR;
                    else 
                    begin
                        s_axis_tx_tlast   <= 1'b0;
                        s_axis_tx_tvalid  <= 1'b0;
                        s_axis_tx_tdata   <= 64'b0;
                        s_axis_tx_tkeep   <= 8'h00;
                        compl_done_o      <= 1'b0;
                    end
                end
                
                SEND_DATA : begin
                    if (s_axis_tx_tready) 
                    begin
                        s_axis_tx_tlast  <= 1'b1;
                        s_axis_tx_tvalid <= 1'b1;

                        s_axis_tx_tdata  <= {
                                        reg_data_i,
                                        req_rid_i,
                                        req_tag_i,
                                        {1'b0},
                                        req_addr_i
                                        };
                        s_axis_tx_tkeep   <= 8'hFF;
                        state             <= SEND_ACK_CPLD;
                    end 
                    else
                        state             <= SEND_DATA;
                end
                
                SEND_ACK_CPLD:begin
                    if(~req_compl_wd_i)
                    begin
                        compl_done_o   <= 1'b0;
                        state          <= IDLE;
                    end
                    if (s_axis_tx_tready) 
                    begin
                        compl_done_o           <= req_compl_wd_i;
                        s_axis_tx_tlast        <= 1'b0;
                        s_axis_tx_tvalid       <= 1'b0;
                    end
                end
                 
                SEND_ACK_DMA:begin
                    sys_ddr_dma_req_done_o <= 1'b0;
                    sys_user_dma_req_done_o <= 1'b0;
                    if (s_axis_tx_tready) 
                    begin
                        s_axis_tx_tlast        <= 1'b0;
                        s_axis_tx_tvalid       <= 1'b0;
                        state                  <= IDLE;
                    end
                end
 
                SEND_DMA_REQ:begin
                    if (s_axis_tx_tready) 
                    begin
                        s_axis_tx_tlast  <= 1'b1;
                        s_axis_tx_tvalid <= 1'b1;
                        s_axis_tx_tdata  <= {32'h00000000,sys_ddr_dma_rd_addr_i};
                        s_axis_tx_tkeep  <= 8'h0F;
                        state            <= SEND_ACK_DMA;
                        sys_ddr_dma_req_done_o <= 1'b1;
                    end
                    else
                        state            <= SEND_DMA_REQ;
                end

                USER_DMA_REQ:begin
                    if (s_axis_tx_tready) 
                    begin
                        s_axis_tx_tlast  <= 1'b1;
                        s_axis_tx_tvalid <= 1'b1;
                        s_axis_tx_tdata  <= {32'h00000000,sys_user_dma_rd_addr_i};
                        s_axis_tx_tkeep  <= 8'h0F;
                        state            <= SEND_ACK_DMA;
                        sys_user_dma_req_done_o <= 1'b1;
                    end
                    else
                        state            <= USER_DMA_REQ;
                    end
                WR_HD1:begin
                    s_axis_tx_tvalid        <=  1'b1;
                    s_axis_tx_tdata         <=  {
                                                completer_id_i,
                                                8'h00,
                                                8'hFF,
                                                1'b0,
                                                MEM_WR,
                                                1'b0,
                                                3'b000,
                                                4'b0000,
                                                1'b0,
                                                1'b0,
                                                2'b00,
                                                2'b00,
                                                10'd32
                                                };
                    s_axis_tx_tkeep         <=  8'hFF;
                    state                   <=  WR_HD2;
                end
                WR_HD2:begin
                    state                   <=  WR_DATA;
                    s_axis_tx_tdata[31:0]   <=  ddr_sys_dma_mem_addr;
                    s_axis_tx_tdata[63:32]  <=  dma_rd_data_i[63:32];
                    s_axis_tx_tkeep         <=  8'hFF;
                end
                WR_DATA:begin
                    if(wr_cntr == 13)
                        rd_fifo_rd_o    <=    1'b0;
                    if(wr_cntr == 15)
                    begin
                        s_axis_tx_tlast <=    1'b1;
                        s_axis_tx_tkeep <=    8'h0F;
                    end
                    if(wr_cntr == 16)
                    begin
                       state            <=    IDLE;
                       s_axis_tx_tlast  <=    1'b0;
                       s_axis_tx_tvalid <=    1'b0;
                    end
                    wr_cntr             <=    wr_cntr + 1'b1;
                    s_axis_tx_tdata     <=    {dma_rd_data_i[63:32],rd_data_p};
                end
                WR_UH:begin
                    state                   <=  WR_USR_DATA;
                    s_axis_tx_tdata[31:0]   <=  user_sys_dma_wr_addr_i;
                    s_axis_tx_tdata[63:32]  <=  user_str_data_i[63:32];
                    s_axis_tx_tkeep         <=  8'hFF;
                    if(wr_cntr==1)
                    begin
                        user_str_data_rd_o    <=    1'b0;
                    end
                end 
                WR_USR_DATA:begin
                    if(wr_cntr == 2)
                        user_str_data_rd_o    <=    1'b0;
                    if(wr_cntr == 1)
                    begin
                        s_axis_tx_tlast     <= 1'b1;
                        s_axis_tx_tkeep     <= 8'h0F; 
                        user_str_dma_done_o <= 1'b1;
                    end  
                    if(wr_cntr == 0)
                    begin
                       state            <=    IDLE;
                       s_axis_tx_tlast  <=    1'b0;
                       s_axis_tx_tvalid <=    1'b0;
                       user_str_dma_done_o <= 1'b0;
                    end
                    wr_cntr             <=    wr_cntr - 1'b1;
                    s_axis_tx_tdata     <=    {user_str_data_i[63:32],user_rd_data_p};
                end 
                REQ_INTR:begin
                    cfg_interrupt_o <= 1'b1;
                    if(cfg_interrupt_rdy_i)
                    begin
                        cfg_interrupt_o <= 1'b0;
                        state           <= IDLE;
                        intr_req_done_o <= 1'b1;
                    end
                end
            endcase
        end
    end

endmodule