data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_incn_r.v
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_incn_r.v:72: Cannot find include file: mc_defines.v\n`include "mc_defines.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl,data/full_repos/permissive/137416811/mc_defines.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl,data/full_repos/permissive/137416811/mc_defines.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl,data/full_repos/permissive/137416811/mc_defines.v.sv\n             mc_defines.v\n             mc_defines.v.v\n             mc_defines.v.sv\n             obj_dir/mc_defines.v\n             obj_dir/mc_defines.v.v\n             obj_dir/mc_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module mc_incn_r(clk, inc_in, inc_out);

parameter	incN_width = 32;

input		clk;
input	[incN_width-1:0]	inc_in;
output	[incN_width-1:0]	inc_out;

parameter	incN_center = incN_width / 2;

reg	[incN_center:0]		out_r;
wire	[31:0]			tmp_zeros = 32'h0;
wire	[incN_center-1:0]	inc_next;

always @(posedge clk)
	out_r <= #1 inc_in[incN_center - 1:0] + {tmp_zeros[incN_center-2:0], 1'h1};

assign inc_out[incN_width-1:incN_center] = inc_in[incN_width-1:incN_center] + inc_next;

assign inc_next = out_r[incN_center] ?
			{tmp_zeros[incN_center-2:0], 1'h1} : tmp_zeros[incN_center-2:0];

assign inc_out[incN_center-1:0]  = out_r;

endmodule
module mc_incn_r(clk, inc_in, inc_out);


parameter	incN_width = 32;

input		clk;
input	[incN_width-1:0]	inc_in;
output	[incN_width-1:0]	inc_out;

parameter	incN_center = incN_width / 2;

reg	[incN_center:0]		out_r;
wire	[31:0]			tmp_zeros = 32'h0;
wire	[incN_center-1:0]	inc_next;

always @(posedge clk)
	out_r <= #1 inc_in[incN_center - 1:0] + {tmp_zeros[incN_center-2:0], 1'h1};

assign inc_out[incN_width-1:incN_center] = inc_in[incN_width-1:incN_center] + inc_next;

assign inc_next = out_r[incN_center] ?
			{tmp_zeros[incN_center-2:0], 1'h1} : tmp_zeros[incN_center-2:0];

assign inc_out[incN_center-1:0]  = out_r;

endmodule