data/full_repos/permissive/163576144/ip_repo/AXI_LCD_IP_1230_1.0/hdl/core_LCD_Sender.v
data/verilator_xmls/d7ce55e6-60d9-4fd0-afbc-22f703f26158.xml
module core_LCD_Sender#(
parameter PSEND_CMD ='d1,
parameter PSEND_PARA='d2
)
(

	odata,
	odcx,
	ordx,
	owrx,

	iclk,
	irstn,
	idata,
	icmd,
	ostatus
);
output reg[15:0] odata;
output reg	 odcx;
output reg	 ordx;
output reg	 owrx;
output reg[ 7:0] ostatus;

input wire	 iclk;
input wire	 irstn;
input wire[15:0] idata;
input wire[ 7:0] icmd;

reg[7:0] state;
parameter IDLE		='d0;
parameter SEND_CMD	='d1;
parameter SEND_PARA	='d2;

integer cnt;

always @ (posedge iclk or negedge irstn)
if(!irstn)begin
	state<=IDLE;
	owrx<=1;
	ordx<=0;
end else case(state)
	IDLE:begin
		case(icmd)
		PSEND_CMD:begin
			state<=SEND_CMD;
			ostatus<=8'b0000_0001;
			cnt<=0;
		end
		PSEND_PARA:begin
			state<=SEND_PARA;
			ostatus<=8'b0000_0010;
			cnt<=0;
		end
		default:begin
			state<=IDLE;
			owrx<=1;
			ordx<=0;
			ostatus<=8'b0000_0000;
			cnt<=0;
		end
		endcase
	end
	SEND_CMD:begin
		case(cnt)
		'd0:begin
			owrx<=0;
			ordx<=1;
			odcx<=0;
			odata<=idata;
			cnt<=cnt+1;
		end
		'd1:begin
			owrx<=1;
			ostatus<=8'b1000_0001;
			state<=IDLE;
		end
		endcase
	end
	SEND_PARA:begin
		case(cnt)
		'd0:begin
			owrx<=0;
			ordx<=1;
			odcx<=1;
			odata<=idata;
			cnt<=cnt+1;
		end
		'd1:begin
			owrx<=1;
			ostatus<=8'b1000_0010;
			state<=IDLE;
		end
		endcase	
	end
endcase


endmodule
module core_LCD_Sender#(
parameter PSEND_CMD ='d1,
parameter PSEND_PARA='d2
)
(

	odata,
	odcx,
	ordx,
	owrx,

	iclk,
	irstn,
	idata,
	icmd,
	ostatus
);

output reg[15:0] odata;
output reg	 odcx;
output reg	 ordx;
output reg	 owrx;
output reg[ 7:0] ostatus;

input wire	 iclk;
input wire	 irstn;
input wire[15:0] idata;
input wire[ 7:0] icmd;

reg[7:0] state;
parameter IDLE		='d0;
parameter SEND_CMD	='d1;
parameter SEND_PARA	='d2;

integer cnt;

always @ (posedge iclk or negedge irstn)
if(!irstn)begin
	state<=IDLE;
	owrx<=1;
	ordx<=0;
end else case(state)
	IDLE:begin
		case(icmd)
		PSEND_CMD:begin
			state<=SEND_CMD;
			ostatus<=8'b0000_0001;
			cnt<=0;
		end
		PSEND_PARA:begin
			state<=SEND_PARA;
			ostatus<=8'b0000_0010;
			cnt<=0;
		end
		default:begin
			state<=IDLE;
			owrx<=1;
			ordx<=0;
			ostatus<=8'b0000_0000;
			cnt<=0;
		end
		endcase
	end
	SEND_CMD:begin
		case(cnt)
		'd0:begin
			owrx<=0;
			ordx<=1;
			odcx<=0;
			odata<=idata;
			cnt<=cnt+1;
		end
		'd1:begin
			owrx<=1;
			ostatus<=8'b1000_0001;
			state<=IDLE;
		end
		endcase
	end
	SEND_PARA:begin
		case(cnt)
		'd0:begin
			owrx<=0;
			ordx<=1;
			odcx<=1;
			odata<=idata;
			cnt<=cnt+1;
		end
		'd1:begin
			owrx<=1;
			ostatus<=8'b1000_0010;
			state<=IDLE;
		end
		endcase	
	end
endcase


endmodule