data/full_repos/permissive/128117771/Automaton-VGA-80bit/image.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/128117771/Automaton-VGA-80bit/image.v:25: Bit extraction of array[59:0] requires 6 bit index, not 7 bits.\n                                                                                   : ... In instance image\n    data <= rom[row][col];\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/128117771/Automaton-VGA-80bit/image.v:33: Bit extraction of array[59:0] requires 6 bit index, not 7 bits.\n                                                                                   : ... In instance image\n      rom [rowW] <= dataW;\n          ^\n%Error: Exiting due to 2 warning(s)\n'
module image (

    input wire clk,
    input wire [6:0] row,
    input wire [6:0] col,
    output reg data,

    input wire [6:0] rowW,
    input wire [79:0] dataW
  );


  reg [79:0] rom [0:59];








  always @(posedge clk) begin
    data <= rom[row][col];
  end

  reg [6:0] counter = 0;


  always @(posedge clk) begin
    if (rowW != row) begin
      rom [rowW] <= dataW;
    end
  end

endmodule
module image (

    input wire clk,
    input wire [6:0] row,
    input wire [6:0] col,
    output reg data,

    input wire [6:0] rowW,
    input wire [79:0] dataW
  );



  reg [79:0] rom [0:59];








  always @(posedge clk) begin
    data <= rom[row][col];
  end

  reg [6:0] counter = 0;


  always @(posedge clk) begin
    if (rowW != row) begin
      rom [rowW] <= dataW;
    end
  end

endmodule