data/full_repos/permissive/104784866/CLB/Verilog/src/CLB.v
None: at end of input
1: b"%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB.v:98: Cannot find file containing module: 'AsyncRAM'\n AsyncRAM#(LUT_WIDTH, DIMENSION) lut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104784866/CLB/Verilog/src,data/full_repos/permissive/104784866/AsyncRAM\n             data/full_repos/permissive/104784866/CLB/Verilog/src,data/full_repos/permissive/104784866/AsyncRAM.v\n             data/full_repos/permissive/104784866/CLB/Verilog/src,data/full_repos/permissive/104784866/AsyncRAM.sv\n             AsyncRAM\n             AsyncRAM.v\n             AsyncRAM.sv\n             obj_dir/AsyncRAM\n             obj_dir/AsyncRAM.v\n             obj_dir/AsyncRAM.sv\n%Error: Exiting due to 1 error(s)\n"
module CLB#(

		parameter UID = 0,

		parameter DIMENSION = 4,

		parameter UID_WIDTH = 16,

		parameter LUT_WIDTH = 4,

		parameter DIMENSION_WIDTH = 2
	) (

		clk,
		clk_en,


		mode,
		c_clk,
		c_bus,
		c_uid,
		c_dimension,


		b_in,
		b_out
	);


	parameter CONFIG_WORD_WIDTH = DIMENSION + LUT_WIDTH + 2;


	input clk;
	input clk_en;


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [UID_WIDTH-1:0] c_uid;
	input [DIMENSION_WIDTH-1:0] c_dimension;


	input [LUT_WIDTH-1:0] b_in;
	output b_out;

	wire w_lut_clk;
	wire [LUT_WIDTH-1:0]  w_lut_addr;
	wire w_lut_rw;
	wire [DIMENSION-1:0] w_lut_data_in;
	wire [DIMENSION-1:0] w_lut_data_out;

	reg [DIMENSION-1:0] configReg;
	reg registeredOutput;


	AsyncRAM#(LUT_WIDTH, DIMENSION) lut (
		.clk(w_lut_clk),
		.addr(w_lut_addr),
		.rw(w_lut_rw),
		.data_in(w_lut_data_in),
		.data_out(w_lut_data_out)
	);


	assign w_lut_clk = c_clk;
	assign w_lut_addr = mode? `C_BUS_LUT_ADDR : b_in;
	assign w_lut_rw = mode && `C_BUS_RAM_WRITE && (UID == c_uid);
	assign w_lut_data_in = `C_BUS_LUT_DATA;
	assign b_out = (`CONFIGREG_OUTPUTTYPESELECTOR_DIM)? registeredOutput : w_lut_data_out[c_dimension];


	always @(posedge c_clk) begin
		if(mode && `C_BUS_REG_WRITE && (UID == c_uid)) begin
			`CONFIGREG_OUTPUTTYPESELECTOR_FULL = `C_BUS_OUTPUTTYPESELECTOR;
		end
	end



	always @(posedge clk or posedge mode) begin
		if(mode) begin
			registeredOutput <= 'b0;
		end
		else if(clk_en) begin
			registeredOutput <= w_lut_data_out[c_dimension];
		end
	end

endmodule
module CLB#(

		parameter UID = 0,

		parameter DIMENSION = 4,

		parameter UID_WIDTH = 16,

		parameter LUT_WIDTH = 4,

		parameter DIMENSION_WIDTH = 2
	) (

		clk,
		clk_en,


		mode,
		c_clk,
		c_bus,
		c_uid,
		c_dimension,


		b_in,
		b_out
	);



	parameter CONFIG_WORD_WIDTH = DIMENSION + LUT_WIDTH + 2;


	input clk;
	input clk_en;


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [UID_WIDTH-1:0] c_uid;
	input [DIMENSION_WIDTH-1:0] c_dimension;


	input [LUT_WIDTH-1:0] b_in;
	output b_out;

	wire w_lut_clk;
	wire [LUT_WIDTH-1:0]  w_lut_addr;
	wire w_lut_rw;
	wire [DIMENSION-1:0] w_lut_data_in;
	wire [DIMENSION-1:0] w_lut_data_out;

	reg [DIMENSION-1:0] configReg;
	reg registeredOutput;


	AsyncRAM#(LUT_WIDTH, DIMENSION) lut (
		.clk(w_lut_clk),
		.addr(w_lut_addr),
		.rw(w_lut_rw),
		.data_in(w_lut_data_in),
		.data_out(w_lut_data_out)
	);


	assign w_lut_clk = c_clk;
	assign w_lut_addr = mode? `C_BUS_LUT_ADDR : b_in;
	assign w_lut_rw = mode && `C_BUS_RAM_WRITE && (UID == c_uid);
	assign w_lut_data_in = `C_BUS_LUT_DATA;
	assign b_out = (`CONFIGREG_OUTPUTTYPESELECTOR_DIM)? registeredOutput : w_lut_data_out[c_dimension];


	always @(posedge c_clk) begin
		if(mode && `C_BUS_REG_WRITE && (UID == c_uid)) begin
			`CONFIGREG_OUTPUTTYPESELECTOR_FULL = `C_BUS_OUTPUTTYPESELECTOR;
		end
	end



	always @(posedge clk or posedge mode) begin
		if(mode) begin
			registeredOutput <= 'b0;
		end
		else if(clk_en) begin
			registeredOutput <= w_lut_data_out[c_dimension];
		end
	end

endmodule