data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:84: Cannot find include file: sim_clks_rsts.vh\n`include "sim_clks_rsts.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc,data/full_repos/permissive/214858095/sim_clks_rsts.vh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc,data/full_repos/permissive/214858095/sim_clks_rsts.vh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc,data/full_repos/permissive/214858095/sim_clks_rsts.vh.sv\n             sim_clks_rsts.vh\n             sim_clks_rsts.vh.v\n             sim_clks_rsts.vh.sv\n             obj_dir/sim_clks_rsts.vh\n             obj_dir/sim_clks_rsts.vh.v\n             obj_dir/sim_clks_rsts.vh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:85: Cannot find include file: sim_cvita_lib.svh\n`include "sim_cvita_lib.svh" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:86: Cannot find include file: sim_set_rb_lib.svh\n`include "sim_set_rb_lib.svh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:87: Cannot find include file: noc_shell_regs.vh\n`include "noc_shell_regs.vh" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:88: Cannot find include file: data_types.vh\n`include "data_types.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:223: syntax error, unexpected IDENTIFIER, expecting \')\'\n  function void set_data_type(input cvita_data_type_t _data_type, input int unsigned stream = 0);\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:261: syntax error, unexpected \'(\', expecting IDENTIFIER\n      s_cvita_ack.reset();\n                        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:262: syntax error, unexpected \'(\', expecting IDENTIFIER\n      m_cvita_cmd.reset();\n                        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:263: syntax error, unexpected \'(\', expecting IDENTIFIER\n      m_cvita_data.reset();\n                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:264: syntax error, unexpected \'(\', expecting IDENTIFIER\n      s_cvita_data.reset();\n                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:265: syntax error, unexpected \'(\', expecting IDENTIFIER\n      m_axis_data.reset();\n                        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:266: syntax error, unexpected \'(\', expecting IDENTIFIER\n      s_axis_data.reset();\n                        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:296: syntax error, unexpected \'(\', expecting IDENTIFIER\n      check_downstream(stream);\n                       ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:303: syntax error, unexpected int, expecting IDENTIFIER or genvar\n      for (int unsigned i = 0; i < num_pkts; i++) begin\n           ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:306: syntax error, unexpected \'=\', expecting IDENTIFIER\n          pkt.hdr = \'{pkt_type:DATA, has_time:metadata.has_time, eob:metadata.eob  ,\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:311: syntax error, unexpected \'=\', expecting IDENTIFIER\n          pkt.hdr = \'{pkt_type:DATA, has_time:metadata.has_time, eob:1\'b0,\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:341: syntax error, unexpected \'=\', expecting IDENTIFIER\n      metadata.eob = pkt.hdr.eob;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:342: syntax error, unexpected \'=\', expecting IDENTIFIER\n      metadata.has_time = pkt.hdr.has_time;\n                        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:343: syntax error, unexpected \'=\', expecting IDENTIFIER\n      metadata.timestamp = pkt.hdr.timestamp;\n                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:358: syntax error, unexpected \'(\', expecting IDENTIFIER\n      m_cvita_data.push_pkt(pkt, stream);\n                            ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:373: syntax error, unexpected \'(\', expecting IDENTIFIER\n      m_axis_data.push_word(word, eop, stream);\n                            ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:386: syntax error, unexpected \'(\', expecting IDENTIFIER\n      s_cvita_data.pull_pkt(pkt, stream);\n                            ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:402: syntax error, unexpected \'(\', expecting IDENTIFIER\n      s_axis_data.pull_word(word, eop, stream);\n                            ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:426: syntax error, unexpected \'(\', expecting IDENTIFIER\n      check_upstream(stream);\n                     ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:446: syntax error, unexpected \'=\', expecting IDENTIFIER\n      cmd_pkt.hdr = \'{pkt_type:CMD, has_time:metadata.has_time, eob:metadata.eob,\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:450: syntax error, unexpected \'(\', expecting IDENTIFIER\n      payload.push_back(word);\n                        ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:451: syntax error, unexpected \'=\', expecting IDENTIFIER\n      cmd_pkt.payload = payload;\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:452: syntax error, unexpected \'(\', expecting IDENTIFIER\n      m_cvita_cmd.push_pkt(cmd_pkt);\n                           ^~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:477: syntax error, unexpected \'(\', expecting IDENTIFIER\n      s_cvita_ack.pull_pkt(resp_pkt);\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:479: syntax error, unexpected \'=\', expecting IDENTIFIER\n      metadata.eob = resp_pkt.hdr.eob;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:480: syntax error, unexpected \'=\', expecting IDENTIFIER\n      metadata.has_time = resp_pkt.hdr.has_time;\n                        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:481: syntax error, unexpected \'=\', expecting IDENTIFIER\n      metadata.timestamp = resp_pkt.hdr.timestamp;\n                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:532: syntax error, unexpected \'=\', expecting IDENTIFIER\n      md.has_time = 1;\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/rfnoc/sim_rfnoc_lib.svh:533: syntax error, unexpected \'=\', expecting IDENTIFIER\n      md.timestamp = timestamp;\n                   ^\n%Error: Cannot continue\n'
function int unsigned get_spp(input int unsigned stream = 0);
    check_stream(stream);
    return(spp[stream]);
  endfunction
function int unsigned get_spp(input int unsigned stream = 0);

    check_stream(stream);
    return(spp[stream]);
  endfunction