data/full_repos/permissive/161029703/src/uma/PriorityEncoder/PriorityEncoder_width16.v
data/verilator_xmls/fed06496-644b-49f6-85ec-f5d686c41708.xml
module PriorityEncoder16(enable_n, data, result, result_valid);
	input 		      enable_n;
	input  [15:0]     data;
	output [3:0]      result;
	output		      result_valid;
	
	wire r3Raw = |data[7:0];
	wire r2Raw = |data[3:0] | 
					(|data[11:8]  & ~|{data[7:4]});
	wire r1Raw = |data[1:0] | 
					(|data[5:4]   & ~|{data[3:2]}) | 
					(|data[9:8]   & ~|{data[3:2], data[7:6]}) |
					(|data[13:12] & ~|{data[3:2], data[7:6], data[11:10]});
	wire r0Raw = data[0]  |
					(data[2]  & ~data[1]) | 
					(data[4]  & ~data[1] & ~data[3]) |
					(data[6]  & ~data[1] & ~data[3] & ~data[5]) |
					(data[8]  & ~data[1] & ~data[3] & ~data[5] & ~data[7]) | 
					(data[10] & ~data[1] & ~data[3] & ~data[5] & ~data[7] & ~data[9]) |
					(data[12] & ~data[1] & ~data[3] & ~data[5] & ~data[7] & ~data[9] & ~data[11]) |
					(data[14] & ~data[1] & ~data[3] & ~data[5] & ~data[7] & ~data[9] & ~data[11] & ~data[13]);
	wire [3:0]   result = {enable_n, enable_n, enable_n, enable_n} | ~{r3Raw, r2Raw, r1Raw, r0Raw};					 
	wire         result_valid = |data & ~enable_n;
endmodule
module PriorityEncoder16(enable_n, data, result, result_valid);

	input 		      enable_n;
	input  [15:0]     data;
	output [3:0]      result;
	output		      result_valid;
	
	wire r3Raw = |data[7:0];
	wire r2Raw = |data[3:0] | 
					(|data[11:8]  & ~|{data[7:4]});
	wire r1Raw = |data[1:0] | 
					(|data[5:4]   & ~|{data[3:2]}) | 
					(|data[9:8]   & ~|{data[3:2], data[7:6]}) |
					(|data[13:12] & ~|{data[3:2], data[7:6], data[11:10]});
	wire r0Raw = data[0]  |
					(data[2]  & ~data[1]) | 
					(data[4]  & ~data[1] & ~data[3]) |
					(data[6]  & ~data[1] & ~data[3] & ~data[5]) |
					(data[8]  & ~data[1] & ~data[3] & ~data[5] & ~data[7]) | 
					(data[10] & ~data[1] & ~data[3] & ~data[5] & ~data[7] & ~data[9]) |
					(data[12] & ~data[1] & ~data[3] & ~data[5] & ~data[7] & ~data[9] & ~data[11]) |
					(data[14] & ~data[1] & ~data[3] & ~data[5] & ~data[7] & ~data[9] & ~data[11] & ~data[13]);
	wire [3:0]   result = {enable_n, enable_n, enable_n, enable_n} | ~{r3Raw, r2Raw, r1Raw, r0Raw};					 
	wire         result_valid = |data & ~enable_n;
endmodule