data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v
 line:434: before: ")"
1: b"%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:434: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:439: syntax error, unexpected input\ninput CLK, RST, EN, WE;\n^~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:450: syntax error, unexpected assign\nassign DO = mem[addr_reg][dw-1:0];\n^~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:522: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:527: syntax error, unexpected input\ninput CLK, RST, EN, WE;\n^~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:538: syntax error, unexpected assign\nassign DO = mem[addr_reg][dw-1:0];\n^~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:566: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:571: syntax error, unexpected input\ninput CLK, RST, EN, WE;\n^~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:582: syntax error, unexpected assign\nassign DO = mem[addr_reg][dw-1:0];\n^~~~~~\n%Error: Exiting due to 9 error(s)\n"
module lpm_ram_dq (
    address,
    inclock,
    outclock,
    data,
    we,
    q
);

parameter lpm_width = 8;
parameter lpm_widthad = 11;
parameter lpm_indata = "REGISTERED";
parameter lpm_address_control = "REGISTERED";
parameter lpm_outdata = "UNREGISTERED";
parameter lpm_hint = "USE_EAB=ON";

localparam dw = lpm_width;
localparam aw = lpm_widthad;

input [aw-1:0] address;
input inclock;
input outclock;
input [dw-1:0] data;
input we;
output [dw-1:0] q;

reg	[dw-1:0]	mem [(1<<aw)-1:0];
reg	[aw-1:0]	addr_reg;




assign q = mem[addr_reg];




always @(posedge inclock)
    addr_reg <= #1 address;




always @(posedge inclock)
	if (we)
		mem[address] <= #1 data;

endmodule
module lpm_ram_dq (
    address,
    inclock,
    outclock,
    data,
    we,
    q
);


parameter lpm_width = 8;
parameter lpm_widthad = 11;
parameter lpm_indata = "REGISTERED";
parameter lpm_address_control = "REGISTERED";
parameter lpm_outdata = "UNREGISTERED";
parameter lpm_hint = "USE_EAB=ON";

localparam dw = lpm_width;
localparam aw = lpm_widthad;

input [aw-1:0] address;
input inclock;
input outclock;
input [dw-1:0] data;
input we;
output [dw-1:0] q;

reg	[dw-1:0]	mem [(1<<aw)-1:0];
reg	[aw-1:0]	addr_reg;




assign q = mem[addr_reg];




always @(posedge inclock)
    addr_reg <= #1 address;




always @(posedge inclock)
	if (we)
		mem[address] <= #1 data;

endmodule