data/full_repos/permissive/205055389/test/verga/edges1.v
 line:36: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/edges1.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 b = 1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/edges1.v:27: Unsupported: Ignoring delay on this delayed statement.\n #1 b = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/edges1.v:28: Unsupported: Ignoring delay on this delayed statement.\n #1 c = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/edges1.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 c = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/edges1.v:30: Unsupported: Ignoring delay on this delayed statement.\n #1 c = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/edges1.v:32: Unsupported: Ignoring delay on this delayed statement.\n #1 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/edges1.v:33: Unsupported: Ignoring delay on this delayed statement.\n #1 x = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/edges1.v:34: Unsupported: Ignoring delay on this delayed statement.\n #1 x = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/edges1.v:35: Unsupported: Ignoring delay on this delayed statement.\n #1 x = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/edges1.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 $display("done");\n ^\n%Error: Exiting due to 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg[31:0] a,b,c;
  reg x;
  integer i;

  always @(*)
    begin
      a = b + c;
    end 

  always @(posedge x)
    $display("%d: posedge x=%b",$time,x);

  always @(negedge x)
    $display("%d: negedge x=%b",$time,x);

  always @(a)
    $display("a = %d",a);

  initial
    begin
	b = 0; c = 0;
	#1 b = 1;
	#1 b = 2;
	#1 c = 2;
	#1 c = 2;
	#1 c = 2;
	$display("x=%b",x);
	#1 x = 1;
	#1 x = 0;
	#1 x = 1;
	#1 x = 0;
	#1 $display("done");
    end

endmodule
module top;

  reg[31:0] a,b,c;
  reg x;
  integer i;

  always @(*)
    begin
      a = b + c;
    end 

  always @(posedge x)
    $display("%d: posedge x=%b",$time,x);

  always @(negedge x)
    $display("%d: negedge x=%b",$time,x);

  always @(a)
    $display("a = %d",a);

  initial
    begin
	b = 0; c = 0;
	#1 b = 1;
	#1 b = 2;
	#1 c = 2;
	#1 c = 2;
	#1 c = 2;
	$display("x=%b",x);
	#1 x = 1;
	#1 x = 0;
	#1 x = 1;
	#1 x = 0;
	#1 $display("done");
    end

endmodule