data/full_repos/permissive/115351337/uart/reciever.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:41: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n                                                                       : ... In instance uart_rx\n    reg [1:0]  state = IDLE;\n                       ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:69: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'RECIEVE\' generates 3 bits.\n                                                                       : ... In instance uart_rx\n                    state <= RECIEVE;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:72: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n                                                                       : ... In instance uart_rx\n                    state <= IDLE;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:84: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'DONE\' generates 3 bits.\n                                                                       : ... In instance uart_rx\n                    state <= DONE;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:86: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'RECIEVE\' generates 3 bits.\n                                                                       : ... In instance uart_rx\n                    state <= RECIEVE;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:80: Operator LT expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'bit_recieved\' generates 3 bits.\n                                                                       : ... In instance uart_rx\n                if (bit_recieved < 8 && count == SAMPLE) begin\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:94: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n                                                                       : ... In instance uart_rx\n                    state <= IDLE;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:97: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'DONE\' generates 3 bits.\n                                                                       : ... In instance uart_rx\n                    state <= DONE;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:102: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 3 bits.\n                                                                        : ... In instance uart_rx\n                state <= IDLE;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/115351337/uart/reciever.v:66: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 2 bits.\n                                                                       : ... In instance uart_rx\n        case (state)\n        ^~~~\n%Error: Exiting due to 10 warning(s)\n'
module uart_rx (
    input            clk,
    input            rx,
    input            clear,
    output reg [7:0] data,
    output           done
);
    parameter LIMIT          = 104;
    parameter SAMPLE         = LIMIT/2;
    parameter IDLE           = 3'b00;
    parameter RECIEVE        = 3'b01;
    parameter DONE           = 3'b10;

    reg [1:0]  state = IDLE;
    reg [31:0] count = 0;
    reg [1:0]  stop_bits = 0;
    reg [2:0]  bit_recieved = 0;
    reg        op_complete = 0;

    always @(posedge clk) begin
        if (count == LIMIT) begin
            count <= 0;
        end else begin
            count <= count + 1;
        end
    end

    always @(posedge clk) begin
        if (clear == 1'b1) begin
            done <= 1'b0;
        end else if (op_complete == 1'b1) begin
            done <= op_complete;
        end else begin
            done <= done;
        end
    end

    always @(posedge clk) begin
        case (state)
            IDLE: begin
                if (rx == 1'b0 && count == SAMPLE && done == 1'b0) begin
                    state <= RECIEVE;
                    data <= 0;
                end else begin
                    state <= IDLE;
                    bit_recieved <= 0;
                    stop_bits <= 0;
                    op_complete <= 1'b0;
                end
            end

            RECIEVE: begin
                if (bit_recieved < 8 && count == SAMPLE) begin
                    data[bit_recieved] <= rx;
                    bit_recieved <= bit_recieved + 1;
                end else if (bit_recieved == 7) begin
                    state <= DONE;
                end else begin
                    state <= RECIEVE;
                end
            end

            DONE: begin
                if (stop_bits < 3 && count == SAMPLE) begin
                    stop_bits <= stop_bits + 1;
                end else if (stop_bits == 3) begin
                    state <= IDLE;
                    op_complete <= 1'b1;
                end else begin
                    state <= DONE;
                end
            end

            default: begin
                state <= IDLE;
            end
        endcase
    end
endmodule
module uart_rx (
    input            clk,
    input            rx,
    input            clear,
    output reg [7:0] data,
    output           done
);

    parameter LIMIT          = 104;
    parameter SAMPLE         = LIMIT/2;
    parameter IDLE           = 3'b00;
    parameter RECIEVE        = 3'b01;
    parameter DONE           = 3'b10;

    reg [1:0]  state = IDLE;
    reg [31:0] count = 0;
    reg [1:0]  stop_bits = 0;
    reg [2:0]  bit_recieved = 0;
    reg        op_complete = 0;

    always @(posedge clk) begin
        if (count == LIMIT) begin
            count <= 0;
        end else begin
            count <= count + 1;
        end
    end

    always @(posedge clk) begin
        if (clear == 1'b1) begin
            done <= 1'b0;
        end else if (op_complete == 1'b1) begin
            done <= op_complete;
        end else begin
            done <= done;
        end
    end

    always @(posedge clk) begin
        case (state)
            IDLE: begin
                if (rx == 1'b0 && count == SAMPLE && done == 1'b0) begin
                    state <= RECIEVE;
                    data <= 0;
                end else begin
                    state <= IDLE;
                    bit_recieved <= 0;
                    stop_bits <= 0;
                    op_complete <= 1'b0;
                end
            end

            RECIEVE: begin
                if (bit_recieved < 8 && count == SAMPLE) begin
                    data[bit_recieved] <= rx;
                    bit_recieved <= bit_recieved + 1;
                end else if (bit_recieved == 7) begin
                    state <= DONE;
                end else begin
                    state <= RECIEVE;
                end
            end

            DONE: begin
                if (stop_bits < 3 && count == SAMPLE) begin
                    stop_bits <= stop_bits + 1;
                end else if (stop_bits == 3) begin
                    state <= IDLE;
                    op_complete <= 1'b1;
                end else begin
                    state <= DONE;
                end
            end

            default: begin
                state <= IDLE;
            end
        endcase
    end
endmodule