data/full_repos/permissive/154590168/rtl_cpu/PcAndIr.v
1: b'%Error: data/full_repos/permissive/154590168/rtl_cpu/PcAndIr.v:55: Cannot find include file: OpNumber.v\n`include "OpNumber.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v.v\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v.sv\n             OpNumber.v\n             OpNumber.v.v\n             OpNumber.v.sv\n             obj_dir/OpNumber.v\n             obj_dir/OpNumber.v.v\n             obj_dir/OpNumber.v.sv\n%Error: Exiting due to 1 error(s)\n'
module  PcAndIr (
    input               clock,
    input               reset,
    input       [15:0]  pm_rdata,
    input       [7:0]   dm_rdata,
    input       [7:0]   io_rdata,
    input       [7:0]   rf_rdata,
    input       [7:0]   sreg,
    input       [15:0]  alu_ro,
    input               alu_zf,
    input               irq,
    input       [15:0]  irq_addr,
    input               sr_if,
    input       [0:82]  op_decode,
    input               tim_cyc_end,
    input               tim_pc_en,
    output  reg [15:0]  pc,
    output      [15:0]  pc_new,
    output              pc_new_en,
    output  reg [15:0]  ir,
    output  reg [15:0]  ir_2nd,
    output  reg [1:0]   cycle,
    output              skip_en,
    output              irq_det,
    output              irq_ret
);




reg         as_reset;
reg         sy_reset;
wire[15:0]  pc_inc;
wire[15:0]  pc_jmp_mx;
wire        pc_jmp_en;
wire        pc_mx_alu;
wire        pc_mx_ret_l;
wire        pc_mx_ret_h;
wire        brn_cyc_end;
wire        ir_en;
wire        ir_2nd_en;
wire        cyc_end;
wire        skp_det;
reg         skp_1st;
reg         skp_2nd;
wire        skp_2nd_det;
wire        skp_cyc_end;
reg         irq_det_1d;
reg         irq_det_2d;


`include "OpNumber.v"
wire    op_jmp    = op_decode[B_JMP   ];
wire    op_rjmp   = op_decode[B_RJMP  ];
wire    op_ijmp   = op_decode[B_IJMP  ];
wire    op_call   = op_decode[B_CALL  ];
wire    op_rcall  = op_decode[B_RCALL ];
wire    op_icall  = op_decode[B_ICALL ];
wire    op_ret    = op_decode[B_RET   ];
wire    op_reti   = op_decode[B_RETI  ];
wire    op_cpse   = op_decode[B_CPSE  ];
wire    op_sbrc   = op_decode[B_SBRC  ];
wire    op_sbrs   = op_decode[B_SBRS  ];
wire    op_sbic   = op_decode[B_SBIC  ];
wire    op_sbis   = op_decode[B_SBIS  ];
wire    op_brbs   = op_decode[B_BRBS  ];
wire    op_brbc   = op_decode[B_BRBC  ];
wire    op_lds    = op_decode[B_LDS   ];
wire    op_sts    = op_decode[B_STS   ];





always @(posedge clock) begin
    as_reset <= reset;
    sy_reset <= as_reset;
end

always @(posedge clock or posedge reset) begin
    if (reset) begin
        pc <= 16'h0000;
    end else begin
        pc <= pc_new_en ? pc_new : pc;
    end
end

assign  pc_new_en = ~sy_reset & (tim_pc_en | cyc_end | skip_en) & ~irq_det;

assign  pc_new = irq_det_2d ? irq_addr
               : (~skip_en & pc_jmp_en) ? pc_jmp_mx : pc_inc;

assign  pc_inc = pc + 1'b1;

assign  pc_jmp_mx = (pc_mx_alu   ? alu_ro               : 16'h0000)
                  | (pc_mx_ret_l ? {pc[15:8], dm_rdata} : 16'h0000)
                  | (pc_mx_ret_h ? {dm_rdata, pc[7:0]}  : 16'h0000);

assign  pc_jmp_en = pc_mx_alu | pc_mx_ret_l | pc_mx_ret_h;

assign  pc_mx_alu = (op_jmp  & (cycle == 2'd1))
                  | (op_rjmp & (cycle == 2'd0))
                  | (op_ijmp & (cycle == 2'd0))
                  | (op_call  & (cycle == 2'd2))
                  | (op_rcall & (cycle == 2'd1))
                  | (op_icall & (cycle == 2'd1))
                  | (op_brbs & (cycle == 2'd0) &  sreg[ir[2:0]])
                  | (op_brbc & (cycle == 2'd0) & ~sreg[ir[2:0]]);

assign  pc_mx_ret_l = (op_ret  & (cycle == 2'd1))
                    | (op_reti & (cycle == 2'd1));
assign  pc_mx_ret_h = (op_ret  & (cycle == 2'd2))
                    | (op_reti & (cycle == 2'd2));


assign  brn_cyc_end = (op_brbs & ~sreg[ir[2:0]])
                    | (op_brbc &  sreg[ir[2:0]]);




always @(posedge clock or posedge reset) begin
    if (reset) begin
        ir <= 16'h0000;
        ir_2nd <= 16'h0000;
    end else begin

        ir <= irq_det ? 16'hd000 : ir_en ? pm_rdata : ir;
        ir_2nd <= ir_2nd_en ? pm_rdata : ir_2nd;
    end
end

assign  ir_en = ~sy_reset & cyc_end;

assign  ir_2nd_en = (op_jmp  & (cycle == 2'd0))
                  | (op_call & (cycle == 2'd0))
                  | (op_lds  & (cycle == 2'd0))
                  | (op_sts  & (cycle == 2'd0));


always @(posedge clock or posedge reset) begin
    if (reset) begin
        cycle <= 2'd0;
    end else begin
        cycle <= cyc_end ? 2'd0 : (cycle + 1'b1);
    end
end

assign  cyc_end = tim_cyc_end | brn_cyc_end | skp_cyc_end;




assign  skp_det = ~skip_en
                & ( (op_cpse & alu_zf)
                  | (op_sbrc & ~rf_rdata[ir[2:0]])
                  | (op_sbrs &  rf_rdata[ir[2:0]])
                  | (op_sbic & (cycle == 2'd1) & ~io_rdata[ir[2:0]])
                  | (op_sbis & (cycle == 2'd1) &  io_rdata[ir[2:0]]) );

always @(posedge clock) begin
    skp_1st <= skp_det;
    skp_2nd <= skp_2nd_det;
end

assign  skp_2nd_det = (skp_1st & op_jmp )
                    | (skp_1st & op_call)
                    | (skp_1st & op_lds )
                    | (skp_1st & op_sts );

assign  skp_cyc_end = (skp_1st & ~skp_2nd_det) | skp_2nd;

assign  skip_en = skp_1st | skp_2nd;




assign  irq_det = (irq & sr_if) & (cyc_end & ~skp_det);
assign  irq_ret = op_reti & (cycle == 2'd2);

always @(posedge clock) begin
    irq_det_1d <= irq_det;
    irq_det_2d <= irq_det_1d;
end

endmodule
module  PcAndIr (
    input               clock,
    input               reset,
    input       [15:0]  pm_rdata,
    input       [7:0]   dm_rdata,
    input       [7:0]   io_rdata,
    input       [7:0]   rf_rdata,
    input       [7:0]   sreg,
    input       [15:0]  alu_ro,
    input               alu_zf,
    input               irq,
    input       [15:0]  irq_addr,
    input               sr_if,
    input       [0:82]  op_decode,
    input               tim_cyc_end,
    input               tim_pc_en,
    output  reg [15:0]  pc,
    output      [15:0]  pc_new,
    output              pc_new_en,
    output  reg [15:0]  ir,
    output  reg [15:0]  ir_2nd,
    output  reg [1:0]   cycle,
    output              skip_en,
    output              irq_det,
    output              irq_ret
);





reg         as_reset;
reg         sy_reset;
wire[15:0]  pc_inc;
wire[15:0]  pc_jmp_mx;
wire        pc_jmp_en;
wire        pc_mx_alu;
wire        pc_mx_ret_l;
wire        pc_mx_ret_h;
wire        brn_cyc_end;
wire        ir_en;
wire        ir_2nd_en;
wire        cyc_end;
wire        skp_det;
reg         skp_1st;
reg         skp_2nd;
wire        skp_2nd_det;
wire        skp_cyc_end;
reg         irq_det_1d;
reg         irq_det_2d;


`include "OpNumber.v"
wire    op_jmp    = op_decode[B_JMP   ];
wire    op_rjmp   = op_decode[B_RJMP  ];
wire    op_ijmp   = op_decode[B_IJMP  ];
wire    op_call   = op_decode[B_CALL  ];
wire    op_rcall  = op_decode[B_RCALL ];
wire    op_icall  = op_decode[B_ICALL ];
wire    op_ret    = op_decode[B_RET   ];
wire    op_reti   = op_decode[B_RETI  ];
wire    op_cpse   = op_decode[B_CPSE  ];
wire    op_sbrc   = op_decode[B_SBRC  ];
wire    op_sbrs   = op_decode[B_SBRS  ];
wire    op_sbic   = op_decode[B_SBIC  ];
wire    op_sbis   = op_decode[B_SBIS  ];
wire    op_brbs   = op_decode[B_BRBS  ];
wire    op_brbc   = op_decode[B_BRBC  ];
wire    op_lds    = op_decode[B_LDS   ];
wire    op_sts    = op_decode[B_STS   ];





always @(posedge clock) begin
    as_reset <= reset;
    sy_reset <= as_reset;
end

always @(posedge clock or posedge reset) begin
    if (reset) begin
        pc <= 16'h0000;
    end else begin
        pc <= pc_new_en ? pc_new : pc;
    end
end

assign  pc_new_en = ~sy_reset & (tim_pc_en | cyc_end | skip_en) & ~irq_det;

assign  pc_new = irq_det_2d ? irq_addr
               : (~skip_en & pc_jmp_en) ? pc_jmp_mx : pc_inc;

assign  pc_inc = pc + 1'b1;

assign  pc_jmp_mx = (pc_mx_alu   ? alu_ro               : 16'h0000)
                  | (pc_mx_ret_l ? {pc[15:8], dm_rdata} : 16'h0000)
                  | (pc_mx_ret_h ? {dm_rdata, pc[7:0]}  : 16'h0000);

assign  pc_jmp_en = pc_mx_alu | pc_mx_ret_l | pc_mx_ret_h;

assign  pc_mx_alu = (op_jmp  & (cycle == 2'd1))
                  | (op_rjmp & (cycle == 2'd0))
                  | (op_ijmp & (cycle == 2'd0))
                  | (op_call  & (cycle == 2'd2))
                  | (op_rcall & (cycle == 2'd1))
                  | (op_icall & (cycle == 2'd1))
                  | (op_brbs & (cycle == 2'd0) &  sreg[ir[2:0]])
                  | (op_brbc & (cycle == 2'd0) & ~sreg[ir[2:0]]);

assign  pc_mx_ret_l = (op_ret  & (cycle == 2'd1))
                    | (op_reti & (cycle == 2'd1));
assign  pc_mx_ret_h = (op_ret  & (cycle == 2'd2))
                    | (op_reti & (cycle == 2'd2));


assign  brn_cyc_end = (op_brbs & ~sreg[ir[2:0]])
                    | (op_brbc &  sreg[ir[2:0]]);




always @(posedge clock or posedge reset) begin
    if (reset) begin
        ir <= 16'h0000;
        ir_2nd <= 16'h0000;
    end else begin

        ir <= irq_det ? 16'hd000 : ir_en ? pm_rdata : ir;
        ir_2nd <= ir_2nd_en ? pm_rdata : ir_2nd;
    end
end

assign  ir_en = ~sy_reset & cyc_end;

assign  ir_2nd_en = (op_jmp  & (cycle == 2'd0))
                  | (op_call & (cycle == 2'd0))
                  | (op_lds  & (cycle == 2'd0))
                  | (op_sts  & (cycle == 2'd0));


always @(posedge clock or posedge reset) begin
    if (reset) begin
        cycle <= 2'd0;
    end else begin
        cycle <= cyc_end ? 2'd0 : (cycle + 1'b1);
    end
end

assign  cyc_end = tim_cyc_end | brn_cyc_end | skp_cyc_end;




assign  skp_det = ~skip_en
                & ( (op_cpse & alu_zf)
                  | (op_sbrc & ~rf_rdata[ir[2:0]])
                  | (op_sbrs &  rf_rdata[ir[2:0]])
                  | (op_sbic & (cycle == 2'd1) & ~io_rdata[ir[2:0]])
                  | (op_sbis & (cycle == 2'd1) &  io_rdata[ir[2:0]]) );

always @(posedge clock) begin
    skp_1st <= skp_det;
    skp_2nd <= skp_2nd_det;
end

assign  skp_2nd_det = (skp_1st & op_jmp )
                    | (skp_1st & op_call)
                    | (skp_1st & op_lds )
                    | (skp_1st & op_sts );

assign  skp_cyc_end = (skp_1st & ~skp_2nd_det) | skp_2nd;

assign  skip_en = skp_1st | skp_2nd;




assign  irq_det = (irq & sr_if) & (cyc_end & ~skp_det);
assign  irq_ret = op_reti & (cycle == 2'd2);

always @(posedge clock) begin
    irq_det_1d <= irq_det;
    irq_det_2d <= irq_det_1d;
end

endmodule