data/full_repos/permissive/18469949/tb_LC3_MIO.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/18469949/tb_LC3_MIO.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #2 reset=0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/18469949/tb_LC3_MIO.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #2 DATAin=16\'h0100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18469949/tb_LC3_MIO.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #2 LD_MAR=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18469949/tb_LC3_MIO.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #2 LD_MDR=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18469949/tb_LC3_MIO.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18469949/tb_LC3_MIO.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #2 LD_MAR=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18469949/tb_LC3_MIO.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #1 CLK=~CLK;\n  ^\n%Error: data/full_repos/permissive/18469949/tb_LC3_MIO.v:71: Cannot find file containing module: \'LC3_MIO\'\nLC3_MIO tb_mio(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18469949,data/full_repos/permissive/18469949/LC3_MIO\n             data/full_repos/permissive/18469949,data/full_repos/permissive/18469949/LC3_MIO.v\n             data/full_repos/permissive/18469949,data/full_repos/permissive/18469949/LC3_MIO.sv\n             LC3_MIO\n             LC3_MIO.v\n             LC3_MIO.sv\n             obj_dir/LC3_MIO\n             obj_dir/LC3_MIO.v\n             obj_dir/LC3_MIO.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_LC3_MIO;

reg				CLK;
reg				reset;
reg	[15:0]	DATAin;
reg				MIO_EN;
reg				R_W;
reg				LD_MAR;
reg				LD_MDR;
reg				GateMDR;
wire	[15:0]	MDRbus_out;
wire				KB_INT;
wire				R;

initial
	begin
		reset=1;
		CLK=1;
		DATAin=16'b0;
		MIO_EN=0;
		R_W=0;
		LD_MAR=0;
		LD_MDR=0;
		GateMDR=0;
	end
	
initial
	begin
		#2	reset=0;
		#2	DATAin=16'h0100;
			LD_MAR=1;
		#2	LD_MAR=0;
		#2	LD_MDR=1;
			MIO_EN=1;
			R_W=0;
			GateMDR=1;
		#20
			MIO_EN=0;
			R_W=0;
			DATAin=16'h000f;
			LD_MAR=1;
		#2	LD_MAR=0;
			MIO_EN=1;
			
	end
	
initial
	forever
		#1	CLK=~CLK;

LC3_MIO	tb_mio(
		.clk						(CLK),
		.reset					(reset),
		.DATABUS					(DATAin),
		.MIO_EN					(MIO_EN),
		.R_W						(R_W),
		.LD_MAR					(LD_MAR),
		.LD_MDR					(LD_MDR),
		.GateMDR					(GateMDR),
		.MDRbus_out				(MDRbus_out),
		.KB_INT					(KB_INT),
		.R							(R),
		
		.LD_char					(LD_char),
		.I_char					(I_char),
		.DDR						(DDR),
		.WR_DDR					(WR_DDR)
    );

endmodule
module tb_LC3_MIO;


reg				CLK;
reg				reset;
reg	[15:0]	DATAin;
reg				MIO_EN;
reg				R_W;
reg				LD_MAR;
reg				LD_MDR;
reg				GateMDR;
wire	[15:0]	MDRbus_out;
wire				KB_INT;
wire				R;

initial
	begin
		reset=1;
		CLK=1;
		DATAin=16'b0;
		MIO_EN=0;
		R_W=0;
		LD_MAR=0;
		LD_MDR=0;
		GateMDR=0;
	end
	
initial
	begin
		#2	reset=0;
		#2	DATAin=16'h0100;
			LD_MAR=1;
		#2	LD_MAR=0;
		#2	LD_MDR=1;
			MIO_EN=1;
			R_W=0;
			GateMDR=1;
		#20
			MIO_EN=0;
			R_W=0;
			DATAin=16'h000f;
			LD_MAR=1;
		#2	LD_MAR=0;
			MIO_EN=1;
			
	end
	
initial
	forever
		#1	CLK=~CLK;

LC3_MIO	tb_mio(
		.clk						(CLK),
		.reset					(reset),
		.DATABUS					(DATAin),
		.MIO_EN					(MIO_EN),
		.R_W						(R_W),
		.LD_MAR					(LD_MAR),
		.LD_MDR					(LD_MDR),
		.GateMDR					(GateMDR),
		.MDRbus_out				(MDRbus_out),
		.KB_INT					(KB_INT),
		.R							(R),
		
		.LD_char					(LD_char),
		.I_char					(I_char),
		.DDR						(DDR),
		.WR_DDR					(WR_DDR)
    );

endmodule