data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v
 line:56: before: "#"
1: b'%Error: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:26: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("simple-memory-using-1d-array-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:27: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, simple_memory_using_1d_array_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = ~CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #15;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/memory/simple-memory-using-1d-array/simple-memory-using-1d-array-tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: Exiting due to 2 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simple_memory_using_1d_array_tb;


reg  CLK;
reg  WRITE;
reg  [3:0] ADDR;
reg  [7:0] WDATA;
wire [7:0] RDATA;
integer i;


simple_memory_using_1d_array uut(
    .clk(CLK),
    .write(WRITE),
    .addr(ADDR),
    .wdata(WDATA),
    .rdata(RDATA)
);


initial begin
    $dumpfile("simple-memory-using-1d-array-tb.vcd");
    $dumpvars(0, simple_memory_using_1d_array_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    WRITE = 0;
    ADDR = 4'h0;
    WDATA = 8'h00;


    #15;
    WRITE = 1;
    for (i = 0; i < 16; i = i+1) begin
        ADDR = i;
        #20;
    end


    WRITE = 0;
    #20


    #20;
    ADDR = 4'h4;


    #20;
    WRITE = 1;
    WDATA = 8'h22;
    ADDR = 4'h3;


    #20;
    WRITE = 1;
    WDATA = 8'h33;
    ADDR = 4'h7;


    #20;
    WRITE = 0;
    ADDR = 4'h2;


    #20;
    WRITE = 0;
    ADDR = 4'h3;


    #20;
    WRITE = 0;
    ADDR = 4'h7;

    #20;

    $display("test complete");
    $finish;
end

endmodule
module simple_memory_using_1d_array_tb;



reg  CLK;
reg  WRITE;
reg  [3:0] ADDR;
reg  [7:0] WDATA;
wire [7:0] RDATA;
integer i;


simple_memory_using_1d_array uut(
    .clk(CLK),
    .write(WRITE),
    .addr(ADDR),
    .wdata(WDATA),
    .rdata(RDATA)
);


initial begin
    $dumpfile("simple-memory-using-1d-array-tb.vcd");
    $dumpvars(0, simple_memory_using_1d_array_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    WRITE = 0;
    ADDR = 4'h0;
    WDATA = 8'h00;


    #15;
    WRITE = 1;
    for (i = 0; i < 16; i = i+1) begin
        ADDR = i;
        #20;
    end


    WRITE = 0;
    #20


    #20;
    ADDR = 4'h4;


    #20;
    WRITE = 1;
    WDATA = 8'h22;
    ADDR = 4'h3;


    #20;
    WRITE = 1;
    WDATA = 8'h33;
    ADDR = 4'h7;


    #20;
    WRITE = 0;
    ADDR = 4'h2;


    #20;
    WRITE = 0;
    ADDR = 4'h3;


    #20;
    WRITE = 0;
    ADDR = 4'h7;

    #20;

    $display("test complete");
    $finish;
end

endmodule