data/full_repos/permissive/111258339/src/mips.v
1: b'%Error: data/full_repos/permissive/111258339/src/mips.v:1: Cannot find include file: src/Define/ctrl_encode_def.v\n`include "src/Define/ctrl_encode_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111258339/src,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v\n             data/full_repos/permissive/111258339/src,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v.v\n             data/full_repos/permissive/111258339/src,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v.sv\n             src/Define/ctrl_encode_def.v\n             src/Define/ctrl_encode_def.v.v\n             src/Define/ctrl_encode_def.v.sv\n             obj_dir/src/Define/ctrl_encode_def.v\n             obj_dir/src/Define/ctrl_encode_def.v.v\n             obj_dir/src/Define/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/111258339/src/mips.v:54: Define or directive not defined: \'`ALUOP_ADDU\'\n        .ALUOp(`ALUOP_ADDU),\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/mips.v:76: Define or directive not defined: \'`EXTOP_SIGNED\'\n        .EXTOp(`EXTOP_SIGNED),\n               ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module mips(
  input wire clk,
  input wire reset
);
    wire[31:0]    pc_current;
    wire[31:0]    pc_temp;
    wire[31:0]    pc_next;
    wire[31:0]    pc_add4;
    wire[31:0]    pc_branch;
    wire[31:0]    instr;


    wire[31:0]    rf_read_data1;
    wire[31:0]    rf_read_data2;
    wire[4:0]    write_addr;
    wire[4:0]    final_write_addr;
    wire[31:0]    ext_output;

    wire[31:0]    alu_num_1;
    wire[31:0]    alu_num_2;
    wire    Zero;

    wire[31:0]    alu_result;
    wire[31:0]    dm_write_data;
    wire[31:0]    dm_read_data;
    wire[31:0] mem2reg_data;
    wire[31:0] final_mem2reg_data;


    wire[1:0] ALUOp;
    wire ALUSrc;
    wire RegWrite;
    wire RegDst;
    wire MemWrite;
    wire MemRead;
    wire Mem2Reg;
    wire Branch;
    wire Jump;
    wire isJal;


    assign pc_add4 = pc_current + 4;

    pc pc(
        .clk(clk),
        .reset(reset),
        .data(pc_next),
        .dout(pc_current)
    );

    alu pc_branch_alu(
        .ALUOp(`ALUOP_ADDU),
        .num_1(pc_add4),
        .num_2({ext_output[29:0], 2'b00}),
        .result(pc_branch)
    );

    mux branch_mux(
        .d0(pc_add4),
        .d1(pc_branch),
        .signal(Branch & Zero),
        .output_data(pc_temp)
    );

    mux jump_mux(
        .d0({pc_add4[31:28], instr[25:0], 2'b00}),
        .d1(pc_temp),
        .signal(Jump),
        .output_data(pc_next)
    );

    EXT ext(
        .Immediate16(instr[15:0]),
        .EXTOp(`EXTOP_SIGNED),
        .Immediate32(ext_output)
    );

    im im(
        .addr(pc_current[11:2]),
        .dout(instr)
    );

    ctrl ctrl(
        .OP(instr[31:26]),
        .funct(instr[5:0]),
        .ALUOp(ALUOp),
        .ALUSrc(ALUSrc),
        .RegWrite(RegWrite),
        .RegDst(RegDst),
        .MemWrite(MemWrite),
        .MemRead(MemRead),
        .Mem2Reg(Mem2Reg),
        .Branch(Branch),
        .Jump(Jump)
    );

    mux write_addr_mux(

        .d0(instr[20:16]),
        .d1(instr[15:11]),

        .signal(RegDst),

        .output_data(write_addr)
    );

    mux jal_addr_mux(

        .d0(31),
        .d1(write_addr),

        .signal(Jump),

        .output_data(final_write_addr)
        );
        mux jal_data_mux(

        .d0(pc_add4),
        .d1(mem2reg_data),

        .signal(Jump),

        .output_data(final_mem2reg_data)
    );

        RF rf(

        .clk(clk),
        .RA1(instr[25:21]),
        .RA2(instr[20:16]),
        .WA1(final_write_addr),
        .WD(final_mem2reg_data),

        .RD1(rf_read_data1),
        .RD2(rf_read_data2),

        .RegWrite(RegWrite)
    );

    assign alu_num_1 = rf_read_data1;
    mux alu_src_mux(
        .d0(rf_read_data2),
        .d1(ext_output),
        .signal(ALUSrc),
        .output_data(alu_num_2)
    );

    alu alu(

        .num_1(alu_num_1),
        .num_2(alu_num_2),
        .ALUOp(ALUOp),

        .Zero(Zero),
        .result(alu_result)
    );

    assign dm_write_data = rf_read_data2;
    dm dm(
        .clk(clk),
        .addr(alu_result),
        .write_data(dm_write_data),
        .MemWrite(MemWrite),


        .read_data(dm_read_data)
    );

    mux mem2reg_mux(
        .d0(alu_result),
        .d1(dm_read_data),
        .signal(Mem2Reg),
        .output_data(mem2reg_data)
    );

    always @(clk) begin
        if (!clk) begin






        $stop;
        end
    end

endmodule
module mips(
  input wire clk,
  input wire reset
);

    wire[31:0]    pc_current;
    wire[31:0]    pc_temp;
    wire[31:0]    pc_next;
    wire[31:0]    pc_add4;
    wire[31:0]    pc_branch;
    wire[31:0]    instr;


    wire[31:0]    rf_read_data1;
    wire[31:0]    rf_read_data2;
    wire[4:0]    write_addr;
    wire[4:0]    final_write_addr;
    wire[31:0]    ext_output;

    wire[31:0]    alu_num_1;
    wire[31:0]    alu_num_2;
    wire    Zero;

    wire[31:0]    alu_result;
    wire[31:0]    dm_write_data;
    wire[31:0]    dm_read_data;
    wire[31:0] mem2reg_data;
    wire[31:0] final_mem2reg_data;


    wire[1:0] ALUOp;
    wire ALUSrc;
    wire RegWrite;
    wire RegDst;
    wire MemWrite;
    wire MemRead;
    wire Mem2Reg;
    wire Branch;
    wire Jump;
    wire isJal;


    assign pc_add4 = pc_current + 4;

    pc pc(
        .clk(clk),
        .reset(reset),
        .data(pc_next),
        .dout(pc_current)
    );

    alu pc_branch_alu(
        .ALUOp(`ALUOP_ADDU),
        .num_1(pc_add4),
        .num_2({ext_output[29:0], 2'b00}),
        .result(pc_branch)
    );

    mux branch_mux(
        .d0(pc_add4),
        .d1(pc_branch),
        .signal(Branch & Zero),
        .output_data(pc_temp)
    );

    mux jump_mux(
        .d0({pc_add4[31:28], instr[25:0], 2'b00}),
        .d1(pc_temp),
        .signal(Jump),
        .output_data(pc_next)
    );

    EXT ext(
        .Immediate16(instr[15:0]),
        .EXTOp(`EXTOP_SIGNED),
        .Immediate32(ext_output)
    );

    im im(
        .addr(pc_current[11:2]),
        .dout(instr)
    );

    ctrl ctrl(
        .OP(instr[31:26]),
        .funct(instr[5:0]),
        .ALUOp(ALUOp),
        .ALUSrc(ALUSrc),
        .RegWrite(RegWrite),
        .RegDst(RegDst),
        .MemWrite(MemWrite),
        .MemRead(MemRead),
        .Mem2Reg(Mem2Reg),
        .Branch(Branch),
        .Jump(Jump)
    );

    mux write_addr_mux(

        .d0(instr[20:16]),
        .d1(instr[15:11]),

        .signal(RegDst),

        .output_data(write_addr)
    );

    mux jal_addr_mux(

        .d0(31),
        .d1(write_addr),

        .signal(Jump),

        .output_data(final_write_addr)
        );
        mux jal_data_mux(

        .d0(pc_add4),
        .d1(mem2reg_data),

        .signal(Jump),

        .output_data(final_mem2reg_data)
    );

        RF rf(

        .clk(clk),
        .RA1(instr[25:21]),
        .RA2(instr[20:16]),
        .WA1(final_write_addr),
        .WD(final_mem2reg_data),

        .RD1(rf_read_data1),
        .RD2(rf_read_data2),

        .RegWrite(RegWrite)
    );

    assign alu_num_1 = rf_read_data1;
    mux alu_src_mux(
        .d0(rf_read_data2),
        .d1(ext_output),
        .signal(ALUSrc),
        .output_data(alu_num_2)
    );

    alu alu(

        .num_1(alu_num_1),
        .num_2(alu_num_2),
        .ALUOp(ALUOp),

        .Zero(Zero),
        .result(alu_result)
    );

    assign dm_write_data = rf_read_data2;
    dm dm(
        .clk(clk),
        .addr(alu_result),
        .write_data(dm_write_data),
        .MemWrite(MemWrite),


        .read_data(dm_read_data)
    );

    mux mem2reg_mux(
        .d0(alu_result),
        .d1(dm_read_data),
        .signal(Mem2Reg),
        .output_data(mem2reg_data)
    );

    always @(clk) begin
        if (!clk) begin






        $stop;
        end
    end

endmodule