data/full_repos/permissive/133245813/axis_multiplier/axi_mm2s_interface.v
1: b'%Warning-WIDTH: data/full_repos/permissive/133245813/axis_multiplier/axi_mm2s_interface.v:189: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 13 bits.\n                                                                                             : ... In instance axi_mm2s_interface\n     rdata <= {busy_reg, ctrl_reg[11:0]};\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/133245813/axis_multiplier/axi_mm2s_interface.v:210: Operator AND expects 32 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                             : ... In instance axi_mm2s_interface\n   ctrl_reg[11:0] <= (s_axi_wdata[11:0] & wmask) | (ctrl_reg[11:0] & ~wmask);\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/133245813/axis_multiplier/axi_mm2s_interface.v:210: Operator AND expects 32 bits on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                             : ... In instance axi_mm2s_interface\n   ctrl_reg[11:0] <= (s_axi_wdata[11:0] & wmask) | (ctrl_reg[11:0] & ~wmask);\n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/133245813/axis_multiplier/axi_mm2s_interface.v:210: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s OR generates 32 bits.\n                                                                                             : ... In instance axi_mm2s_interface\n   ctrl_reg[11:0] <= (s_axi_wdata[11:0] & wmask) | (ctrl_reg[11:0] & ~wmask);\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/133245813/axis_multiplier/axi_mm2s_interface.v:304: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'wr_ptr_cv\' generates 2 bits.\n                                                                                             : ... In instance axi_mm2s_interface\n                        if (wr_ptr_cv == ctrl_reg[10:8]-2)\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/133245813/axis_multiplier/axi_mm2s_interface.v:296: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'wr_ptr_cv\' generates 2 bits.\n                                                                                             : ... In instance axi_mm2s_interface\n                    if (wr_ptr_cv == ctrl_reg[10:8]-1)\n                                  ^~\n%Error: Exiting due to 6 warning(s)\n'
module axi_mm2s_interface
	(

        input  wire        aclk,
        input  wire        aresetn,


        output wire        s_axi_awready,
        input  wire [31:0] s_axi_awaddr,
        input  wire        s_axi_awvalid,

        output wire        s_axi_wready,
        input  wire [31:0] s_axi_wdata,
        input  wire [3:0]  s_axi_wstrb,
        input  wire        s_axi_wvalid,

        input  wire        s_axi_bready,
        output wire [1:0]  s_axi_bresp,
        output wire        s_axi_bvalid,

        output wire        s_axi_arready,
        input  wire [31:0] s_axi_araddr,
        input  wire        s_axi_arvalid,

        input  wire        s_axi_rready,
        output wire [31:0] s_axi_rdata,
        output wire [1:0]  s_axi_rresp,
        output wire        s_axi_rvalid,

        input  wire        m_axis_tready,
        output wire [31:0] m_axis_tdata,
        output wire        m_axis_tvalid,
        output wire        m_axis_tlast,

        output wire        en,
        output wire [7:0]  mult_const
    );















	localparam C_ADDR_BITS = 8;

	localparam C_ADDR_CTRL = 8'h00,
			   C_ADDR_DATA0 = 8'h04,
			   C_ADDR_DATA1 = 8'h08,
			   C_ADDR_DATA2 = 8'h0c,
			   C_ADDR_DATA3 = 8'h10;

	localparam S_WRIDLE = 2'd0,
			   S_WRDATA = 2'd1,
			   S_WRRESP = 2'd2;

	localparam S_RDIDLE = 2'd0,
			   S_RDDATA = 2'd1;

    localparam S_IDLE = 2'h0,
               S_WRITE_STREAM = 2'h1;


	reg [1:0] wstate_cs, wstate_ns;
	reg [C_ADDR_BITS-1:0] waddr;
	wire [31:0] wmask;
	wire aw_hs, w_hs;

	reg [1:0] rstate_cs, rstate_ns;
	wire [C_ADDR_BITS-1:0] raddr;
	reg [31:0] rdata;
	wire ar_hs;

    reg [11:0] ctrl_reg;
    wire busy_reg;
    reg [31:0] data_reg [0:3];
    reg start_reg;           

    reg [1:0] mm2sstate_cs, mm2sstate_ns;
    reg [1:0] wr_ptr_cv, wr_ptr_nv;
    reg m_axis_tlast_cv, m_axis_tlast_nv;


	assign s_axi_awready = (wstate_cs == S_WRIDLE);
	assign s_axi_wready = (wstate_cs == S_WRDATA);
	assign s_axi_bresp = 2'b00;
	assign s_axi_bvalid = (wstate_cs == S_WRRESP);
	assign wmask = {{8{s_axi_wstrb[3]}}, {8{s_axi_wstrb[2]}}, {8{s_axi_wstrb[1]}}, {8{s_axi_wstrb[0]}}};
	assign aw_hs = s_axi_awvalid & s_axi_awready;
	assign w_hs = s_axi_wvalid & s_axi_wready;


	always @(posedge aclk)
	begin
		if (!aresetn)
			wstate_cs <= S_WRIDLE;
		else
			wstate_cs <= wstate_ns;
	end
	

	always @(*)
	begin
		case (wstate_cs)
			S_WRIDLE:
				if (s_axi_awvalid)
					wstate_ns = S_WRDATA;
				else
					wstate_ns = S_WRIDLE;
			S_WRDATA:
				if (s_axi_wvalid)
					wstate_ns = S_WRRESP;
				else
					wstate_ns = S_WRDATA;
			S_WRRESP:
				if (s_axi_bready)
					wstate_ns = S_WRIDLE;
				else
					wstate_ns = S_WRRESP;
			default:
				wstate_ns = S_WRIDLE;
		endcase
	end
	

	always @(posedge aclk)
	begin
		if (aw_hs)
			waddr <= s_axi_awaddr[C_ADDR_BITS-1:0];
	end   


	assign s_axi_arready = (rstate_cs == S_RDIDLE);
	assign s_axi_rdata = rdata;
	assign s_axi_rresp = 2'b00;
	assign s_axi_rvalid = (rstate_cs == S_RDDATA);
	assign ar_hs = s_axi_arvalid & s_axi_arready;
	assign raddr = s_axi_araddr[C_ADDR_BITS-1:0];
	

	always @(posedge aclk)
	begin
		if (!aresetn)
			rstate_cs <= S_RDIDLE;
		else
			rstate_cs <= rstate_ns;
	end


	always @(*) 
	begin
		case (rstate_cs)
			S_RDIDLE:
				if (s_axi_arvalid)
					rstate_ns = S_RDDATA;
				else
					rstate_ns = S_RDIDLE;
			S_RDDATA:
				if (s_axi_rready)
					rstate_ns = S_RDIDLE;
				else
					rstate_ns = S_RDDATA;
			default:
				rstate_ns = S_RDIDLE;
		endcase
	end
	

	always @(posedge aclk)
	begin
	    if (!aresetn)
	        rdata <= 0;
		else if (ar_hs)
			case (raddr)
				C_ADDR_CTRL: 
					rdata <= {busy_reg, ctrl_reg[11:0]};
                C_ADDR_DATA0:
                    rdata <= data_reg[0];
                C_ADDR_DATA1:
                    rdata <= data_reg[1];
                C_ADDR_DATA2:
                    rdata <= data_reg[2];
                C_ADDR_DATA3:
                    rdata <= data_reg[3];   		
			endcase
	end
    

   	assign en = ctrl_reg[11]; 
    assign mult_const = ctrl_reg[7:0];
   	
	always @(posedge aclk)
	begin
	    if (!aresetn)
            ctrl_reg[11:0] <= 0;
		else if (w_hs && waddr == C_ADDR_CTRL)
			ctrl_reg[11:0] <= (s_axi_wdata[11:0] & wmask) | (ctrl_reg[11:0] & ~wmask);
	end
	
	always @(posedge aclk)
	begin
	    if (!aresetn)
	    begin
	        start_reg <= 0;
            data_reg[0] <= 0;
            data_reg[1] <= 0;
            data_reg[2] <= 0;
            data_reg[3] <= 0;
        end
		else if (w_hs && waddr == C_ADDR_DATA0)
		begin
		    if (ctrl_reg[10:8] == 1)
                start_reg <= 1;
			data_reg[0][31:0] <= (s_axi_wdata[31:0] & wmask) | (data_reg[0][31:0] & ~wmask);
	    end
		else if (w_hs && waddr == C_ADDR_DATA1)
        begin
            if (ctrl_reg[10:8] == 2)
                start_reg <= 1;
            data_reg[1][31:0] <= (s_axi_wdata[31:0] & wmask) | (data_reg[1][31:0] & ~wmask);
        end
		else if (w_hs && waddr == C_ADDR_DATA2)
        begin
            if (ctrl_reg[10:8] == 3)
                start_reg <= 1;
            data_reg[2][31:0] <= (s_axi_wdata[31:0] & wmask) | (data_reg[2][31:0] & ~wmask);
        end
		else if (w_hs && waddr == C_ADDR_DATA3)
        begin
            if (ctrl_reg[10:8] == 4)
                start_reg <= 1;
            data_reg[3][31:0] <= (s_axi_wdata[31:0] & wmask) | (data_reg[3][31:0] & ~wmask);
        end
	    else
        begin
            start_reg <= 0;
        end
	end


    assign busy_reg = (mm2sstate_cs == S_WRITE_STREAM) ? 1 : 0;
    assign m_axis_tdata = data_reg[wr_ptr_cv];
    assign m_axis_tvalid = (mm2sstate_cs == S_WRITE_STREAM) ? 1 : 0;
    assign m_axis_tlast = m_axis_tlast_cv;


    always @(posedge aclk)
    begin
        if (!aresetn)
        begin
            mm2sstate_cs <= S_IDLE;
            wr_ptr_cv <= 0;
            m_axis_tlast_cv <= 0;
        end
        else
        begin
            mm2sstate_cs <= mm2sstate_ns;
            wr_ptr_cv <= wr_ptr_nv;
            m_axis_tlast_cv <= m_axis_tlast_nv;
        end 
    end


    always @(*)
    begin
        mm2sstate_ns = mm2sstate_cs;
        wr_ptr_nv = wr_ptr_cv;
        m_axis_tlast_nv = m_axis_tlast_cv;
        case (mm2sstate_cs)
            S_IDLE:
            begin
                if (start_reg)
                begin
                    mm2sstate_ns = S_WRITE_STREAM;
                    if (ctrl_reg[10:8] == 1)
                        m_axis_tlast_nv = 1;    
                end
            end
            S_WRITE_STREAM:
            begin
                if (m_axis_tready)
                begin
                    if (wr_ptr_cv == ctrl_reg[10:8]-1)
                    begin
                        mm2sstate_ns = S_IDLE;
                        wr_ptr_nv = 0;
                        m_axis_tlast_nv = 0;
                    end
                    else
                    begin
                        if (wr_ptr_cv == ctrl_reg[10:8]-2)
                        begin
                            m_axis_tlast_nv = 1;
                        end
                        wr_ptr_nv = wr_ptr_cv + 1;
                    end
                end
            end
        endcase
    end
                         
endmodule
module axi_mm2s_interface
	(

        input  wire        aclk,
        input  wire        aresetn,


        output wire        s_axi_awready,
        input  wire [31:0] s_axi_awaddr,
        input  wire        s_axi_awvalid,

        output wire        s_axi_wready,
        input  wire [31:0] s_axi_wdata,
        input  wire [3:0]  s_axi_wstrb,
        input  wire        s_axi_wvalid,

        input  wire        s_axi_bready,
        output wire [1:0]  s_axi_bresp,
        output wire        s_axi_bvalid,

        output wire        s_axi_arready,
        input  wire [31:0] s_axi_araddr,
        input  wire        s_axi_arvalid,

        input  wire        s_axi_rready,
        output wire [31:0] s_axi_rdata,
        output wire [1:0]  s_axi_rresp,
        output wire        s_axi_rvalid,

        input  wire        m_axis_tready,
        output wire [31:0] m_axis_tdata,
        output wire        m_axis_tvalid,
        output wire        m_axis_tlast,

        output wire        en,
        output wire [7:0]  mult_const
    );
















	localparam C_ADDR_BITS = 8;

	localparam C_ADDR_CTRL = 8'h00,
			   C_ADDR_DATA0 = 8'h04,
			   C_ADDR_DATA1 = 8'h08,
			   C_ADDR_DATA2 = 8'h0c,
			   C_ADDR_DATA3 = 8'h10;

	localparam S_WRIDLE = 2'd0,
			   S_WRDATA = 2'd1,
			   S_WRRESP = 2'd2;

	localparam S_RDIDLE = 2'd0,
			   S_RDDATA = 2'd1;

    localparam S_IDLE = 2'h0,
               S_WRITE_STREAM = 2'h1;


	reg [1:0] wstate_cs, wstate_ns;
	reg [C_ADDR_BITS-1:0] waddr;
	wire [31:0] wmask;
	wire aw_hs, w_hs;

	reg [1:0] rstate_cs, rstate_ns;
	wire [C_ADDR_BITS-1:0] raddr;
	reg [31:0] rdata;
	wire ar_hs;

    reg [11:0] ctrl_reg;
    wire busy_reg;
    reg [31:0] data_reg [0:3];
    reg start_reg;           

    reg [1:0] mm2sstate_cs, mm2sstate_ns;
    reg [1:0] wr_ptr_cv, wr_ptr_nv;
    reg m_axis_tlast_cv, m_axis_tlast_nv;


	assign s_axi_awready = (wstate_cs == S_WRIDLE);
	assign s_axi_wready = (wstate_cs == S_WRDATA);
	assign s_axi_bresp = 2'b00;
	assign s_axi_bvalid = (wstate_cs == S_WRRESP);
	assign wmask = {{8{s_axi_wstrb[3]}}, {8{s_axi_wstrb[2]}}, {8{s_axi_wstrb[1]}}, {8{s_axi_wstrb[0]}}};
	assign aw_hs = s_axi_awvalid & s_axi_awready;
	assign w_hs = s_axi_wvalid & s_axi_wready;


	always @(posedge aclk)
	begin
		if (!aresetn)
			wstate_cs <= S_WRIDLE;
		else
			wstate_cs <= wstate_ns;
	end
	

	always @(*)
	begin
		case (wstate_cs)
			S_WRIDLE:
				if (s_axi_awvalid)
					wstate_ns = S_WRDATA;
				else
					wstate_ns = S_WRIDLE;
			S_WRDATA:
				if (s_axi_wvalid)
					wstate_ns = S_WRRESP;
				else
					wstate_ns = S_WRDATA;
			S_WRRESP:
				if (s_axi_bready)
					wstate_ns = S_WRIDLE;
				else
					wstate_ns = S_WRRESP;
			default:
				wstate_ns = S_WRIDLE;
		endcase
	end
	

	always @(posedge aclk)
	begin
		if (aw_hs)
			waddr <= s_axi_awaddr[C_ADDR_BITS-1:0];
	end   


	assign s_axi_arready = (rstate_cs == S_RDIDLE);
	assign s_axi_rdata = rdata;
	assign s_axi_rresp = 2'b00;
	assign s_axi_rvalid = (rstate_cs == S_RDDATA);
	assign ar_hs = s_axi_arvalid & s_axi_arready;
	assign raddr = s_axi_araddr[C_ADDR_BITS-1:0];
	

	always @(posedge aclk)
	begin
		if (!aresetn)
			rstate_cs <= S_RDIDLE;
		else
			rstate_cs <= rstate_ns;
	end


	always @(*) 
	begin
		case (rstate_cs)
			S_RDIDLE:
				if (s_axi_arvalid)
					rstate_ns = S_RDDATA;
				else
					rstate_ns = S_RDIDLE;
			S_RDDATA:
				if (s_axi_rready)
					rstate_ns = S_RDIDLE;
				else
					rstate_ns = S_RDDATA;
			default:
				rstate_ns = S_RDIDLE;
		endcase
	end
	

	always @(posedge aclk)
	begin
	    if (!aresetn)
	        rdata <= 0;
		else if (ar_hs)
			case (raddr)
				C_ADDR_CTRL: 
					rdata <= {busy_reg, ctrl_reg[11:0]};
                C_ADDR_DATA0:
                    rdata <= data_reg[0];
                C_ADDR_DATA1:
                    rdata <= data_reg[1];
                C_ADDR_DATA2:
                    rdata <= data_reg[2];
                C_ADDR_DATA3:
                    rdata <= data_reg[3];   		
			endcase
	end
    

   	assign en = ctrl_reg[11]; 
    assign mult_const = ctrl_reg[7:0];
   	
	always @(posedge aclk)
	begin
	    if (!aresetn)
            ctrl_reg[11:0] <= 0;
		else if (w_hs && waddr == C_ADDR_CTRL)
			ctrl_reg[11:0] <= (s_axi_wdata[11:0] & wmask) | (ctrl_reg[11:0] & ~wmask);
	end
	
	always @(posedge aclk)
	begin
	    if (!aresetn)
	    begin
	        start_reg <= 0;
            data_reg[0] <= 0;
            data_reg[1] <= 0;
            data_reg[2] <= 0;
            data_reg[3] <= 0;
        end
		else if (w_hs && waddr == C_ADDR_DATA0)
		begin
		    if (ctrl_reg[10:8] == 1)
                start_reg <= 1;
			data_reg[0][31:0] <= (s_axi_wdata[31:0] & wmask) | (data_reg[0][31:0] & ~wmask);
	    end
		else if (w_hs && waddr == C_ADDR_DATA1)
        begin
            if (ctrl_reg[10:8] == 2)
                start_reg <= 1;
            data_reg[1][31:0] <= (s_axi_wdata[31:0] & wmask) | (data_reg[1][31:0] & ~wmask);
        end
		else if (w_hs && waddr == C_ADDR_DATA2)
        begin
            if (ctrl_reg[10:8] == 3)
                start_reg <= 1;
            data_reg[2][31:0] <= (s_axi_wdata[31:0] & wmask) | (data_reg[2][31:0] & ~wmask);
        end
		else if (w_hs && waddr == C_ADDR_DATA3)
        begin
            if (ctrl_reg[10:8] == 4)
                start_reg <= 1;
            data_reg[3][31:0] <= (s_axi_wdata[31:0] & wmask) | (data_reg[3][31:0] & ~wmask);
        end
	    else
        begin
            start_reg <= 0;
        end
	end


    assign busy_reg = (mm2sstate_cs == S_WRITE_STREAM) ? 1 : 0;
    assign m_axis_tdata = data_reg[wr_ptr_cv];
    assign m_axis_tvalid = (mm2sstate_cs == S_WRITE_STREAM) ? 1 : 0;
    assign m_axis_tlast = m_axis_tlast_cv;


    always @(posedge aclk)
    begin
        if (!aresetn)
        begin
            mm2sstate_cs <= S_IDLE;
            wr_ptr_cv <= 0;
            m_axis_tlast_cv <= 0;
        end
        else
        begin
            mm2sstate_cs <= mm2sstate_ns;
            wr_ptr_cv <= wr_ptr_nv;
            m_axis_tlast_cv <= m_axis_tlast_nv;
        end 
    end


    always @(*)
    begin
        mm2sstate_ns = mm2sstate_cs;
        wr_ptr_nv = wr_ptr_cv;
        m_axis_tlast_nv = m_axis_tlast_cv;
        case (mm2sstate_cs)
            S_IDLE:
            begin
                if (start_reg)
                begin
                    mm2sstate_ns = S_WRITE_STREAM;
                    if (ctrl_reg[10:8] == 1)
                        m_axis_tlast_nv = 1;    
                end
            end
            S_WRITE_STREAM:
            begin
                if (m_axis_tready)
                begin
                    if (wr_ptr_cv == ctrl_reg[10:8]-1)
                    begin
                        mm2sstate_ns = S_IDLE;
                        wr_ptr_nv = 0;
                        m_axis_tlast_nv = 0;
                    end
                    else
                    begin
                        if (wr_ptr_cv == ctrl_reg[10:8]-2)
                        begin
                            m_axis_tlast_nv = 1;
                        end
                        wr_ptr_nv = wr_ptr_cv + 1;
                    end
                end
            end
        endcase
    end
                         
endmodule