data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/nexys4.sv
1: b"%Error: data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/nexys4.sv:28: Cannot find file containing module: 'cpu'\ncpu \n^~~\n        ... Looked in:\n             data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl,data/full_repos/permissive/169639758/cpu\n             data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl,data/full_repos/permissive/169639758/cpu.v\n             data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl,data/full_repos/permissive/169639758/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s)\n"
module top(
	input clk,
	output reg[15:0]led
	);

wire [15:0]wdata;
wire [15:0]waddr;
wire [15:0]raddr;
wire [15:0]rdata;
wire wr;
wire rd;

assign led = raddr;

sram ram0(
        .clk(clk),
        .waddr(waddr),
        .wdata(wdata),
        .we(wr),
        .raddr(raddr),
        .rdata(rdata),
        .re(rd)
	);

cpu 
`ifdef BIGCPU
        #(
        .RWIDTH(32),
        .SWIDTH(5)
        )
`endif
        cpu0(
        .clk(clk),
        .mem_raddr_o(raddr),
        .mem_rdata_i(rdata),
        .mem_waddr_o(waddr),
        .mem_wdata_o(wdata),
        .mem_wr_o(wr),
        .mem_rd_o(rd)
        );

endmodule
module top(
	input clk,
	output reg[15:0]led
	);


wire [15:0]wdata;
wire [15:0]waddr;
wire [15:0]raddr;
wire [15:0]rdata;
wire wr;
wire rd;

assign led = raddr;

sram ram0(
        .clk(clk),
        .waddr(waddr),
        .wdata(wdata),
        .we(wr),
        .raddr(raddr),
        .rdata(rdata),
        .re(rd)
	);

cpu 
`ifdef BIGCPU
        #(
        .RWIDTH(32),
        .SWIDTH(5)
        )
`endif
        cpu0(
        .clk(clk),
        .mem_raddr_o(raddr),
        .mem_rdata_i(rdata),
        .mem_waddr_o(waddr),
        .mem_wdata_o(wdata),
        .mem_wr_o(wr),
        .mem_rd_o(rd)
        );

endmodule