data/full_repos/permissive/213507744/Graph/vga_controller.v
 line:9: before: ";"
1: b"%Error: data/full_repos/permissive/213507744/Graph/vga_controller.v:9: syntax error, unexpected ';', expecting ')' or ','\ninput   [7:0]   rgb_input;\n                         ^\n%Error: data/full_repos/permissive/213507744/Graph/vga_controller.v:16: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\noutput  reg [9:0]   col_address,\n^~~~~~\n%Error: data/full_repos/permissive/213507744/Graph/vga_controller.v:17: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\noutput  reg [2:0]   red,\n^~~~~~\n%Error: data/full_repos/permissive/213507744/Graph/vga_controller.v:18: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\noutput  reg [2:0]   green,\n^~~~~~\n%Error: data/full_repos/permissive/213507744/Graph/vga_controller.v:19: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\noutput  reg [1:0]   blue,\n^~~~~~\n%Error: data/full_repos/permissive/213507744/Graph/vga_controller.v:20: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\noutput  reg readn,\n^~~~~~\n%Error: data/full_repos/permissive/213507744/Graph/vga_controller.v:22: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\noutput  reg horizontal_sync,\n^~~~~~\n%Error: data/full_repos/permissive/213507744/Graph/vga_controller.v:23: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\noutput  reg vertical_sync,\n^~~~~~\n%Error: data/full_repos/permissive/213507744/Graph/vga_controller.v:24: syntax error, unexpected ')', expecting IDENTIFIER or '=' or do or final\n);\n^\n%Error: data/full_repos/permissive/213507744/Graph/vga_controller.v:27: syntax error, unexpected always\n    always @ (posedge clk or negedge clrn) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/213507744/Graph/vga_controller.v:41: syntax error, unexpected always\n    always @ (posedge clk or negedge clrn) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/213507744/Graph/vga_controller.v:61: syntax error, unexpected always\n    always @ (posedge clk) begin\n    ^~~~~~\n%Error: Exiting due to 12 error(s)\n"
module vga_controller(
input   [7:0]   rgb_input;

input clk,
input clrn,

output  reg [8:0]   row_address,

output  reg [9:0]   col_address,
output  reg [2:0]   red,
output  reg [2:0]   green,
output  reg [1:0]   blue,
output  reg readn,

output  reg horizontal_sync,
output  reg vertical_sync,
);
    reg [9:0]   horizontal_count;

    always @ (posedge clk or negedge clrn) begin
        if (!clrn) begin
            horizontal_count <= 10'h0;

        end else if (horizontal_count == 10'd799) begin
            horizontal_count <= 10'h0;

        end else begin
            horizontal_count <= horizontal_count + 10'h1;

        end
    end

    reg [9:0]   vertical_count;
    always @ (posedge clk or negedge clrn) begin
        if (!clrn) begin
            vertical_count <= 10'h0;

        end else if (horizontal_count == 10'd799) begin
            if (vertical_count == 10'd524) begin
                vertical_count <= 10'h0;
            end else begin
                vertical_count <= vertical_count + 10'h1;
            end
        end

    wire    [9:0]   row = vertical_count - 10'd35;
    wire    [9:0]   col = horizontal_count - 10'd143;
    wire            horizontal_sync_signal = (horizontal_count > 10'd95);
    wire            vertical_sync_signal = (vertical_count > 10'd1);
    wire            read =  (horizontal_count > 10'd142) &&
                            (horizontal_count < 10'd783) &&
                            (vertical_count > 10'd34) &&
                            (vertical_count < 10'd515);
    always @ (posedge clk) begin
        row_address <= row[8:0];
        col_address <= col;
        horizontal_sync <= horizontal_sync_signal;
        vertical_sync <= vertical_sync_signal;
        readn <= ~read;
        red <= readn ? 3'h0 : rgb_input[7:5];
        greed <= readn ? 3'h0 : rgb_input[4:2];
        blue <= readn ? 2'h0 : rgb_input[1:0];
    end
endmodule
module vga_controller(
input   [7:0]   rgb_input;


input clk,
input clrn,

output  reg [8:0]   row_address,

output  reg [9:0]   col_address,
output  reg [2:0]   red,
output  reg [2:0]   green,
output  reg [1:0]   blue,
output  reg readn,

output  reg horizontal_sync,
output  reg vertical_sync,
);
    reg [9:0]   horizontal_count;

    always @ (posedge clk or negedge clrn) begin
        if (!clrn) begin
            horizontal_count <= 10'h0;

        end else if (horizontal_count == 10'd799) begin
            horizontal_count <= 10'h0;

        end else begin
            horizontal_count <= horizontal_count + 10'h1;

        end
    end

    reg [9:0]   vertical_count;
    always @ (posedge clk or negedge clrn) begin
        if (!clrn) begin
            vertical_count <= 10'h0;

        end else if (horizontal_count == 10'd799) begin
            if (vertical_count == 10'd524) begin
                vertical_count <= 10'h0;
            end else begin
                vertical_count <= vertical_count + 10'h1;
            end
        end

    wire    [9:0]   row = vertical_count - 10'd35;
    wire    [9:0]   col = horizontal_count - 10'd143;
    wire            horizontal_sync_signal = (horizontal_count > 10'd95);
    wire            vertical_sync_signal = (vertical_count > 10'd1);
    wire            read =  (horizontal_count > 10'd142) &&
                            (horizontal_count < 10'd783) &&
                            (vertical_count > 10'd34) &&
                            (vertical_count < 10'd515);
    always @ (posedge clk) begin
        row_address <= row[8:0];
        col_address <= col;
        horizontal_sync <= horizontal_sync_signal;
        vertical_sync <= vertical_sync_signal;
        readn <= ~read;
        red <= readn ? 3'h0 : rgb_input[7:5];
        greed <= readn ? 3'h0 : rgb_input[4:2];
        blue <= readn ? 2'h0 : rgb_input[1:0];
    end
endmodule