data/full_repos/permissive/136510272/sketchs/x86_ld_decoder/main.v
 line:23: before: "]"
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/sketchs/x86_ld_decoder/main.v:19: Operator ASSIGNW expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'IP\' generates 16 bits.\n                                                                                     : ... In instance main\nassign o_addr = IP;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/sketchs/x86_ld_decoder/main.v:35: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                     : ... In instance main\n    IP = 1\'b0;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/sketchs/x86_ld_decoder/main.v:36: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                     : ... In instance main\n    AR = 1\'b0;\n       ^\n%Error: data/full_repos/permissive/136510272/sketchs/x86_ld_decoder/main.v:43: Cannot find file containing module: \'regfile\'\nregfile REG(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/sketchs/x86_ld_decoder,data/full_repos/permissive/136510272/regfile\n             data/full_repos/permissive/136510272/sketchs/x86_ld_decoder,data/full_repos/permissive/136510272/regfile.v\n             data/full_repos/permissive/136510272/sketchs/x86_ld_decoder,data/full_repos/permissive/136510272/regfile.sv\n             regfile\n             regfile.v\n             regfile.sv\n             obj_dir/regfile\n             obj_dir/regfile.v\n             obj_dir/regfile.sv\n%Error: data/full_repos/permissive/136510272/sketchs/x86_ld_decoder/main.v:54: Cannot find file containing module: \'modrmbits\'\nmodrmbits ModrmBits(\n^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module main(

    input   wire            clock,
    input   wire            clock_100,
    output  wire [19:0]     o_addr,
    input   wire [15:0]     i_data

);

`define AX 4'h0
`define CX 4'h1
`define DX 4'h2
`define BX 4'h3
`define SP 4'h4
`define BP 4'h5
`define SI 4'h6
`define DI 4'h7

assign o_addr = IP;

reg [15:0] IP;
reg [19:0] AR;
reg [15:0] SEG[6];


reg [2:0]  A_in;    reg [2:0]  B_in;    reg [2:0]  C_in;
reg [31:0] A_out;   reg [31:0] B_out;   reg [31:0] W_in;
reg regClock;

reg [4:0] ModRM_byte;
reg [7:0] ModRM_info;

initial begin

    IP = 1'b0;
    AR = 1'b0;
    
end




regfile REG(

    .clock  (regClock),
    .A_in   (A_in),
    .B_in   (B_in),
    .W_in   (W_in),
    .A_out  (A_out),
    .B_out  (B_out)

);

modrmbits ModrmBits(

    .clock_100  (clock_100),
    .mbyte      (ModRM_byte),
    .minfo      (minfo16)

);





always @(posedge clock) begin




    
    IP <= IP + 1'b1;
    


    

        


    

end

endmodule
module main(

    input   wire            clock,
    input   wire            clock_100,
    output  wire [19:0]     o_addr,
    input   wire [15:0]     i_data

);


`define AX 4'h0
`define CX 4'h1
`define DX 4'h2
`define BX 4'h3
`define SP 4'h4
`define BP 4'h5
`define SI 4'h6
`define DI 4'h7

assign o_addr = IP;

reg [15:0] IP;
reg [19:0] AR;
reg [15:0] SEG[6];


reg [2:0]  A_in;    reg [2:0]  B_in;    reg [2:0]  C_in;
reg [31:0] A_out;   reg [31:0] B_out;   reg [31:0] W_in;
reg regClock;

reg [4:0] ModRM_byte;
reg [7:0] ModRM_info;

initial begin

    IP = 1'b0;
    AR = 1'b0;
    
end




regfile REG(

    .clock  (regClock),
    .A_in   (A_in),
    .B_in   (B_in),
    .W_in   (W_in),
    .A_out  (A_out),
    .B_out  (B_out)

);

modrmbits ModrmBits(

    .clock_100  (clock_100),
    .mbyte      (ModRM_byte),
    .minfo      (minfo16)

);





always @(posedge clock) begin




    
    IP <= IP + 1'b1;
    


    

        


    

end

endmodule