data/full_repos/permissive/129155059/03-library/modulos_estructural.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/modulos_estructural.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #14;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/129155059/03-library/modulos_estructural.v:33: Multiple top level modules\n                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                           : ... Top module \'NOR\'\nmodule NOR (\n       ^~~\n                                                                                           : ... Top module \'NOT\'\nmodule NOT (\n       ^~~\n                                                                                           : ... Top module \'mux2a1\'\nmodule mux2a1(\n       ^~~~~~\n                                                                                           : ... Top module \'FLOP_D\'\nmodule FLOP_D (\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/129155059/03-library/modulos_estructural.v:52: Signal definition not found, creating implicitly: \'x\'\n NAND   nand1(Sel,1\'b1,x);\n                       ^\n%Warning-IMPLICIT: data/full_repos/permissive/129155059/03-library/modulos_estructural.v:53: Signal definition not found, creating implicitly: \'z\'\n NAND   nand2(In2,Sel,z);\n                      ^\n%Warning-IMPLICIT: data/full_repos/permissive/129155059/03-library/modulos_estructural.v:54: Signal definition not found, creating implicitly: \'y\'\n NAND   nand3(x,In1,y);\n                    ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module NAND (
	input A,
	input B,
	output wire out);


	nand #(11:11:22,7:7:15) gate1(out,A,B);





endmodule
module NAND (
	input A,
	input B,
	output wire out);



	nand #(11:11:22,7:7:15) gate1(out,A,B);





endmodule