data/full_repos/permissive/173670949/ram.v
data/verilator_xmls/4f4d525f-741e-4def-afed-95e49816526a.xml
module ram (DIN, WR_ADDR, WR_EN, CLK, RD_ADDR, DOUT);

    parameter addr_width = 9;
    parameter data_width = 8;

    input [addr_width-1:0]  WR_ADDR;
    input [data_width-1:0]  DIN;
    input                   WR_EN;
    input                   CLK;
    input  [addr_width-1:0] RD_ADDR;
    output [data_width-1:0] DOUT;



    reg [data_width-1:0] DOUT;
    reg [data_width-1:0] mem[(1<<addr_width)-1:0];

    always @(posedge CLK) begin
        if (WR_EN)
            mem[WR_ADDR] <= DIN;
        DOUT <= mem[RD_ADDR];
    end

endmodule
module ram (DIN, WR_ADDR, WR_EN, CLK, RD_ADDR, DOUT);


    parameter addr_width = 9;
    parameter data_width = 8;

    input [addr_width-1:0]  WR_ADDR;
    input [data_width-1:0]  DIN;
    input                   WR_EN;
    input                   CLK;
    input  [addr_width-1:0] RD_ADDR;
    output [data_width-1:0] DOUT;



    reg [data_width-1:0] DOUT;
    reg [data_width-1:0] mem[(1<<addr_width)-1:0];

    always @(posedge CLK) begin
        if (WR_EN)
            mem[WR_ADDR] <= DIN;
        DOUT <= mem[RD_ADDR];
    end

endmodule