data/full_repos/permissive/114643454/src/riscv_min_sopc_tb.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/114643454/src/riscv_min_sopc_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n         forever #10 CLOCK_50 = ~CLOCK_50;\n                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/114643454/src/riscv_min_sopc_tb.v:15: Define or directive not defined: \'`RstEnable\'\n        rst = `RstEnable;\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/riscv_min_sopc_tb.v:15: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rst = `RstEnable;\n                        ^\n%Error: data/full_repos/permissive/114643454/src/riscv_min_sopc_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("cpu-riscv.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/riscv_min_sopc_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/riscv_min_sopc_tb.v:18: Define or directive not defined: \'`RstDisable\'\n        #195 rst = `RstDisable;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/riscv_min_sopc_tb.v:18: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #195 rst = `RstDisable;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/114643454/src/riscv_min_sopc_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #195 rst = `RstDisable;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114643454/src/riscv_min_sopc_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #100000 $finish;\n        ^\n%Error: Exiting due to 6 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module riscv_min_sooc_tb ();

    reg     CLOCK_50;
    reg     rst;


    initial begin
         CLOCK_50 = 1'b0;
         forever #10 CLOCK_50 = ~CLOCK_50;
    end

    initial begin
        rst = `RstEnable;
        $dumpfile("cpu-riscv.vcd");
        $dumpvars(0);
        #195 rst = `RstDisable;
        #100000 $finish;

    end

    riscv_min_sopc riscv_min_sopc0 (
        .clk(CLOCK_50),
        .rst(rst)
    );

endmodule
module riscv_min_sooc_tb ();


    reg     CLOCK_50;
    reg     rst;


    initial begin
         CLOCK_50 = 1'b0;
         forever #10 CLOCK_50 = ~CLOCK_50;
    end

    initial begin
        rst = `RstEnable;
        $dumpfile("cpu-riscv.vcd");
        $dumpvars(0);
        #195 rst = `RstDisable;
        #100000 $finish;

    end

    riscv_min_sopc riscv_min_sopc0 (
        .clk(CLOCK_50),
        .rst(rst)
    );

endmodule