data/full_repos/permissive/113344787/src/hex/hex_to_seg_tb.v
1: b'%Error: data/full_repos/permissive/113344787/src/hex/hex_to_seg_tb.v:14: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile ("src/hex/hex_to_seg_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/113344787/src/hex/hex_to_seg_tb.v:15: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/113344787/src/hex/hex_to_seg_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n            #10\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hex_to_seg_tb;
    reg [3:0] hex_digit;
    wire [6:0] seg;

    hex_to_seg u_hex_to_seg (
        .hex_digit  (hex_digit),
        .seg        (seg)
    );

    integer i;

    initial
    begin
        $dumpfile ("src/hex/hex_to_seg_tb.vcd");
        $dumpvars;
        for (i = 0; i < 17; i = i + 1) begin
            #10
            hex_digit = i;
        end
    end
endmodule
module hex_to_seg_tb;

    reg [3:0] hex_digit;
    wire [6:0] seg;

    hex_to_seg u_hex_to_seg (
        .hex_digit  (hex_digit),
        .seg        (seg)
    );

    integer i;

    initial
    begin
        $dumpfile ("src/hex/hex_to_seg_tb.vcd");
        $dumpvars;
        for (i = 0; i < 17; i = i + 1) begin
            #10
            hex_digit = i;
        end
    end
endmodule