data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_core_reset.v
1: b"%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_core_reset.v:29: Cannot find file containing module: 'sync_reset'\n  sync_reset sync_reset_synced_dla_rstn (\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/sync_reset\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/sync_reset.v\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/sync_reset.sv\n             sync_reset\n             sync_reset.v\n             sync_reset.sv\n             obj_dir/sync_reset\n             obj_dir/sync_reset.v\n             obj_dir/sync_reset.sv\n%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_core_reset.v:42: Cannot find file containing module: 'sync_reset'\n  sync_reset sync_reset_synced_core_rstn (\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_core_reset.v:63: Cannot find file containing module: 'sync_reset'\n  sync_reset sync_reset_synced_rstn (\n  ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module NV_NVDLA_core_reset (
   dla_reset_rstn
  ,direct_reset_
  ,test_mode
  ,synced_rstn
  ,core_reset_rstn
  ,nvdla_clk
  );



input dla_reset_rstn;
input direct_reset_;
input test_mode;
output synced_rstn;
input core_reset_rstn;
input nvdla_clk;
wire synced_core_rstn;
wire synced_dla_rstn;
reg combined_rstn;
  sync_reset sync_reset_synced_dla_rstn (
     .clk (nvdla_clk)
    ,.inreset_ (dla_reset_rstn)
    ,.direct_reset_ (direct_reset_)
    ,.test_mode (test_mode)
    ,.outreset_ (synced_dla_rstn)
    );






  sync_reset sync_reset_synced_core_rstn (
     .clk (nvdla_clk)
    ,.inreset_ (core_reset_rstn)
    ,.direct_reset_ (direct_reset_)
    ,.test_mode (test_mode)
    ,.outreset_ (synced_core_rstn)
    );







always @(posedge nvdla_clk or negedge synced_dla_rstn) begin
  if (!synced_dla_rstn) begin
    combined_rstn <= 1'b0;
  end else begin
  combined_rstn <= synced_dla_rstn & synced_core_rstn;
  end
end
  sync_reset sync_reset_synced_rstn (
     .clk (nvdla_clk)
    ,.inreset_ (combined_rstn)
    ,.direct_reset_ (direct_reset_)
    ,.test_mode (test_mode)
    ,.outreset_ (synced_rstn)
    );





endmodule
module NV_NVDLA_core_reset (
   dla_reset_rstn
  ,direct_reset_
  ,test_mode
  ,synced_rstn
  ,core_reset_rstn
  ,nvdla_clk
  );




input dla_reset_rstn;
input direct_reset_;
input test_mode;
output synced_rstn;
input core_reset_rstn;
input nvdla_clk;
wire synced_core_rstn;
wire synced_dla_rstn;
reg combined_rstn;
  sync_reset sync_reset_synced_dla_rstn (
     .clk (nvdla_clk)
    ,.inreset_ (dla_reset_rstn)
    ,.direct_reset_ (direct_reset_)
    ,.test_mode (test_mode)
    ,.outreset_ (synced_dla_rstn)
    );






  sync_reset sync_reset_synced_core_rstn (
     .clk (nvdla_clk)
    ,.inreset_ (core_reset_rstn)
    ,.direct_reset_ (direct_reset_)
    ,.test_mode (test_mode)
    ,.outreset_ (synced_core_rstn)
    );







always @(posedge nvdla_clk or negedge synced_dla_rstn) begin
  if (!synced_dla_rstn) begin
    combined_rstn <= 1'b0;
  end else begin
  combined_rstn <= synced_dla_rstn & synced_core_rstn;
  end
end
  sync_reset sync_reset_synced_rstn (
     .clk (nvdla_clk)
    ,.inreset_ (combined_rstn)
    ,.direct_reset_ (direct_reset_)
    ,.test_mode (test_mode)
    ,.outreset_ (synced_rstn)
    );





endmodule