data/full_repos/permissive/193790231/B_FSMs.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/193790231/B_FSMs.v:66: Multiple top level modules\n                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                   : ... Top module \'FSM_4xSequenceDetectorA\'\nmodule FSM_4xSequenceDetectorA(\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                   : ... Top module \'FSM_4xSequenceDetectorB\'\nmodule FSM_4xSequenceDetectorB(\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                   : ... Top module \'FSM_4xSequenceDetectorC\'\nmodule FSM_4xSequenceDetectorC(\n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193790231/B_FSMs.v:130: Cannot find file containing module: \'shiftRegisterNx\'\n    shiftRegisterNx #(4) detect0(.Q(shiftRegA), .D(~W), .sregCLK(pCLK), .sregRESN(nREST));\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193790231,data/full_repos/permissive/193790231/shiftRegisterNx\n             data/full_repos/permissive/193790231,data/full_repos/permissive/193790231/shiftRegisterNx.v\n             data/full_repos/permissive/193790231,data/full_repos/permissive/193790231/shiftRegisterNx.sv\n             shiftRegisterNx\n             shiftRegisterNx.v\n             shiftRegisterNx.sv\n             obj_dir/shiftRegisterNx\n             obj_dir/shiftRegisterNx.v\n             obj_dir/shiftRegisterNx.sv\n%Error: data/full_repos/permissive/193790231/B_FSMs.v:131: Cannot find file containing module: \'shiftRegisterNx\'\n    shiftRegisterNx #(4) detect1(.Q(shiftRegB), .D(W), .sregCLK(pCLK), .sregRESN(nREST));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193790231/B_FSMs.v:111: Cannot find file containing module: \'registerNx\'\n    registerNx #(4) ffx4(.Q(fQ[3:0]), .D(fD[3:0]), .regCLK(pCLK), .regRESN(nREST)); \n    ^~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module FSM_4xSequenceDetectorB(
    output reg fOut, 

    input W, pCLK, nREST
);

    parameter A = 4'b0000;
    parameter B = 4'b0001;
    parameter C = 4'b0010;
    parameter D = 4'b0011;
    parameter E = 4'b0100;
    parameter F = 4'b0101;
    parameter G = 4'b0110;
    parameter H = 4'b0111;
    parameter I = 4'b1000;


    wire [3:0]fQ;
    reg  [3:0]fD;

    always@(*) begin
        case({fQ[3:0],W})
            5'b00000: fD = B;
            5'b00001: fD = F;
            5'b00010: fD = C;
            5'b00011: fD = F;
            5'b00100: fD = D;
            5'b00101: fD = F;
            5'b00110: fD = E;
            5'b00111: fD = F;
            5'b01000: fD = E;
            5'b01001: fD = F;
            5'b01010: fD = B;
            5'b01011: fD = G;
            5'b01100: fD = B;
            5'b01101: fD = H;
            5'b01110: fD = B;
            5'b01111: fD = I;
            5'b10000: fD = B;
            5'b10001: fD = I;
            default:  fD = A; 
        endcase
    end


    registerNx #(4) ffx4(.Q(fQ[3:0]), .D(fD[3:0]), .regCLK(pCLK), .regRESN(nREST)); 


    always@(*) begin
        case(fQ[3:0])
            4'd4: fOut = 1'b1;
            4'd8: fOut = 1'b1;
            default: fOut = 1'b0;
        endcase
    end
endmodule
module FSM_4xSequenceDetectorB(
    output reg fOut, 

    input W, pCLK, nREST
);


    parameter A = 4'b0000;
    parameter B = 4'b0001;
    parameter C = 4'b0010;
    parameter D = 4'b0011;
    parameter E = 4'b0100;
    parameter F = 4'b0101;
    parameter G = 4'b0110;
    parameter H = 4'b0111;
    parameter I = 4'b1000;


    wire [3:0]fQ;
    reg  [3:0]fD;

    always@(*) begin
        case({fQ[3:0],W})
            5'b00000: fD = B;
            5'b00001: fD = F;
            5'b00010: fD = C;
            5'b00011: fD = F;
            5'b00100: fD = D;
            5'b00101: fD = F;
            5'b00110: fD = E;
            5'b00111: fD = F;
            5'b01000: fD = E;
            5'b01001: fD = F;
            5'b01010: fD = B;
            5'b01011: fD = G;
            5'b01100: fD = B;
            5'b01101: fD = H;
            5'b01110: fD = B;
            5'b01111: fD = I;
            5'b10000: fD = B;
            5'b10001: fD = I;
            default:  fD = A; 
        endcase
    end


    registerNx #(4) ffx4(.Q(fQ[3:0]), .D(fD[3:0]), .regCLK(pCLK), .regRESN(nREST)); 


    always@(*) begin
        case(fQ[3:0])
            4'd4: fOut = 1'b1;
            4'd8: fOut = 1'b1;
            default: fOut = 1'b0;
        endcase
    end
endmodule