data/full_repos/permissive/173003307/sim/vga_sig_gen_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173003307/sim/vga_sig_gen_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #10 CLK <= ~CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173003307/sim/vga_sig_gen_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #10 RESET = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173003307/sim/vga_sig_gen_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #20 RESET = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173003307/sim/vga_sig_gen_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #40 VGA_DATA <= ~VGA_DATA;\n        ^\n%Error: data/full_repos/permissive/173003307/sim/vga_sig_gen_tb.v:39: Cannot find file containing module: \'VGA_Sig_Gen\'\nVGA_Sig_Gen uut(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173003307/sim,data/full_repos/permissive/173003307/VGA_Sig_Gen\n             data/full_repos/permissive/173003307/sim,data/full_repos/permissive/173003307/VGA_Sig_Gen.v\n             data/full_repos/permissive/173003307/sim,data/full_repos/permissive/173003307/VGA_Sig_Gen.sv\n             VGA_Sig_Gen\n             VGA_Sig_Gen.v\n             VGA_Sig_Gen.sv\n             obj_dir/VGA_Sig_Gen\n             obj_dir/VGA_Sig_Gen.v\n             obj_dir/VGA_Sig_Gen.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vga_sig_gen_tb(

    );

    reg CLK;
    reg [15:0] CONFIG_COLOURS;
    reg VGA_DATA;
    reg RESET;
    
    wire DPR_CLK;
    wire VGA_HS;
    wire VGA_VS;
    wire [14:0] VGA_ADDR;
    wire [7:0] VGA_COLOUR;

    
VGA_Sig_Gen uut(
            .CLK(CLK),
            .RESET(RESET),

            .CONFIG_COLOURS(CONFIG_COLOURS),

            .DPR_CLK(DPR_CLK),
            .VGA_ADDR(VGA_ADDR),
            .VGA_DATA(VGA_DATA),

            .VGA_HS(VGA_HS),
            .VGA_VS(VGA_VS),
            .VGA_COLOUR(VGA_COLOUR)
            ); 
    

    initial
        CLK = 0;
        
    always
        #10 CLK <= ~CLK;
    
    initial
    begin
        CONFIG_COLOURS = 16'hAA00;
        VGA_DATA = 0;
        RESET = 1'b0;
        #10 RESET = 1'b1;
        #20 RESET = 1'b0;
    end
    
    always
    begin
        #40 VGA_DATA <= ~VGA_DATA;
    end    
   
endmodule
module vga_sig_gen_tb(

    );


    reg CLK;
    reg [15:0] CONFIG_COLOURS;
    reg VGA_DATA;
    reg RESET;
    
    wire DPR_CLK;
    wire VGA_HS;
    wire VGA_VS;
    wire [14:0] VGA_ADDR;
    wire [7:0] VGA_COLOUR;

    
VGA_Sig_Gen uut(
            .CLK(CLK),
            .RESET(RESET),

            .CONFIG_COLOURS(CONFIG_COLOURS),

            .DPR_CLK(DPR_CLK),
            .VGA_ADDR(VGA_ADDR),
            .VGA_DATA(VGA_DATA),

            .VGA_HS(VGA_HS),
            .VGA_VS(VGA_VS),
            .VGA_COLOUR(VGA_COLOUR)
            ); 
    

    initial
        CLK = 0;
        
    always
        #10 CLK <= ~CLK;
    
    initial
    begin
        CONFIG_COLOURS = 16'hAA00;
        VGA_DATA = 0;
        RESET = 1'b0;
        #10 RESET = 1'b1;
        #20 RESET = 1'b0;
    end
    
    always
    begin
        #40 VGA_DATA <= ~VGA_DATA;
    end    
   
endmodule