data/full_repos/permissive/132173046/src/tests/top_usage_tb.v
1: b'%Warning-REDEFMACRO: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:6: Redefining existing define: \'VERILATOR\', with different value: \n                     ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message.\n%Warning-REDEFMACRO: Previous definition is here, with value: 1\n%Error: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:74: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("test_top.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:75: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n      #1 reset_n_in = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n      #1 cs1_n_in = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n          #1 sdi1_in = test_spi1_data[7];\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n          #1 sck1_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n          #1 sck1_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n      #1 cs1_n_in = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n      #1 cs0_n_in = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n          #1 sdi0_in = test_spi0_data[351];\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n          #1 sck0_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:146: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n          #1 sck0_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n      #1 cs0_n_in = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n      #1 reset_n_in = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:207: Unsupported: Ignoring delay on this delayed statement.\n              #1 clk_in = 1;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n              #1 clk_in = 0;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:214: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk_in = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:215: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk_in = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk_in = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:222: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk_in = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:228: Unsupported: Ignoring delay on this delayed statement.\n      #1 cs1_n_in = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:234: Unsupported: Ignoring delay on this delayed statement.\n          #1 sck1_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:237: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:238: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:239: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:240: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:241: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:246: Unsupported: Ignoring delay on this delayed statement.\n          #1 sck1_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:249: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:250: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:251: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:252: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:253: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n          #1 clk_in = 0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/132173046/src/tests/top_usage_tb.v:257: Unsupported: Ignoring delay on this delayed statement.\n      #1 cs1_n_in = 1;\n      ^\n%Error: Exiting due to 2 error(s), 60 warning(s)\n'
module test_top();

  `define VERILATOR

  reg clk_in = 0;

  reg reset_n_in = 0;

  reg sck0_in;
  reg sdi0_in;
  reg cs0_n_in;

  reg sck1_in;
  reg sdi1_in;
  wire sdo1_out;
  reg cs1_n_in;

  wire ready_n_ts_inout;

  wire status_led_n_out;

  `define SHAPOOL_NO_NONCE_OFFSET

  localparam POOL_SIZE      = 1;
  localparam POOL_SIZE_LOG2 = 0;
  localparam BASE_TARGET    = 3;

  top
  #(.POOL_SIZE(POOL_SIZE),
    .POOL_SIZE_LOG2(POOL_SIZE_LOG2),
    .BASE_TARGET(BASE_TARGET))
  uut (
    clk_in,
    reset_n_in,

    sck0_in,
    sdi0_in,
    cs0_n_in,

    sck1_in,
    sdi1_in,
    sdo1_out,
    cs1_n_in,

    ready_n_ts_inout,

    status_led_n_out
  );



  reg [31:0] n = 0;
  reg [31:0] i = 0;

  localparam [359:0] test_spi0_data0 = {
    128'hdc6a3b8d_0c69421a_cb1a5434_e536f7d5,
    128'hc3c1b9e4_4cbb9b8f_95f0172e_fc48d2df,
    96'hdc141787_358b0553_535f0119
  };

  localparam [7:0] test_spi1_data0 = {
    8'h00
  };

  reg [359:0] test_spi0_data;
  reg [7:0] test_spi1_data;
  reg [31:0] result;

  initial
    begin

      $dumpfile("test_top.vcd");
      $dumpvars;

      test_spi0_data = test_spi0_data0;
      test_spi1_data = test_spi1_data0;


      clk_in = 0;
      reset_n_in = 1;
      sck0_in = 0;
      cs0_n_in = 1;
      sck1_in = 0;
      cs1_n_in = 1;



      #1 reset_n_in = 0;




 

      #1 cs1_n_in = 0;

      for (i = 0; i < 8; i = i + 1)
        begin

          #1 sdi1_in = test_spi1_data[7];
          test_spi1_data <= { test_spi1_data[6:0], 1'b0 };

          #1 sck1_in = 1;
          

          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;

          #1 sck1_in = 0;
          

          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
        end

      #1 cs1_n_in = 1;





      #1 cs0_n_in = 0;
     
      for (i = 0; i < 360; i = i + 1)
        begin

          #1 sdi0_in = test_spi0_data[351];
          test_spi0_data <= { test_spi0_data[350:0], 1'b0 };

          #1 sck0_in = 1;
          

          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;

          #1 sck0_in = 0;
          

          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
        end

      #1 cs0_n_in = 1;

      $display("Device configuration");
      $display("  nonce start MSB: %h", uut.nonce_start);

      $display("Job parameters:");
      $display("  SHA256 state:       %h", uut.sha_state[255:128]);
      $display("                      %h", uut.sha_state[127:0]);
      $display("  message head:       %h", uut.message_head);




 

      #1 reset_n_in = 1;

      for (n = 0; n < 50 && !ready_n_ts_inout; n = n + 1)
        begin

          for (i = 0; i < 64; i = i + 1)
            begin
              $display("nonce: %d", uut.pool.nonce);
              $display("round: %d", uut.pool.round);
              $display("  Kt: %h", uut.pool.Kt);
              $display("  success:                %b", uut.pool.success);
              $display("    |match_flags:         %b", |uut.pool.match_flags);
              $display("    round == 0:           %b", uut.pool.round == 0);
              $display("    skip_first:           %b", uut.pool.skip_first);
              $display("    skip_second:          %b", uut.pool.skip_second);
              $display("  u0.M: %h", uut.pool.tracks[0].u0.M[511:384]);
              $display("  u0.M: %h", uut.pool.tracks[0].u0.M[383:256]);
              $display("  u0.M: %h", uut.pool.tracks[0].u0.M[255:128]);
              $display("  u0.M: %h", uut.pool.tracks[0].u0.M[127:0]);
              $display("  u0.Wt: %h", uut.pool.tracks[0].u0.Wt);
              $display("  H_u0: %h", uut.pool.tracks[0].H_u0);
              $display("  u1.M: %h", uut.pool.tracks[0].u1.M[511:384]);
              $display("  u1.M: %h", uut.pool.tracks[0].u1.M[383:256]);
              $display("  u1.M: %h", uut.pool.tracks[0].u1.M[255:128]);
              $display("  u1.M: %h", uut.pool.tracks[0].u1.M[127:0]);
              $display("  u1.Wt: %h", uut.pool.tracks[0].u1.Wt);
              $display("  H_u1 (bs): %h", uut.pool.tracks[0].H_bs);
              $display("  H: %h", uut.pool.tracks[0].H);
              $display("    test bits: %h", { uut.pool.tracks[0].H[BASE_TARGET+16-1:16], uut.pool.tracks[0].H[15:0] & uut.pool.difficulty_bm });
              $display("");

              #1 clk_in = 1;
              #1 clk_in = 0;
            end

        end


      #1 clk_in = 1;
      #1 clk_in = 0;

      $display("nonce: %h", uut.nonce);
      $display("ext_io.result_data: %h", uut.ext_io.result_data);


      #1 clk_in = 1;
      #1 clk_in = 0;

      $display("nonce: %h", uut.nonce);
      $display("ext_io.result_data: %h", uut.ext_io.result_data);


      #1 cs1_n_in = 0;
      
      for (i = 0; i < 32; i = i + 1)
        begin
          $display("[%d] (%b) %b", i, ready_n_ts_inout, sdo1_out);

          #1 sck1_in = 1;
          

          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;

          result <= { result[30:0], sdo1_out };

          #1 sck1_in = 0;
          

          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
        end

      #1 cs1_n_in = 1;

      $display("top_test result: %h", result);

    end

endmodule
module test_top();


  `define VERILATOR

  reg clk_in = 0;

  reg reset_n_in = 0;

  reg sck0_in;
  reg sdi0_in;
  reg cs0_n_in;

  reg sck1_in;
  reg sdi1_in;
  wire sdo1_out;
  reg cs1_n_in;

  wire ready_n_ts_inout;

  wire status_led_n_out;

  `define SHAPOOL_NO_NONCE_OFFSET

  localparam POOL_SIZE      = 1;
  localparam POOL_SIZE_LOG2 = 0;
  localparam BASE_TARGET    = 3;

  top
  #(.POOL_SIZE(POOL_SIZE),
    .POOL_SIZE_LOG2(POOL_SIZE_LOG2),
    .BASE_TARGET(BASE_TARGET))
  uut (
    clk_in,
    reset_n_in,

    sck0_in,
    sdi0_in,
    cs0_n_in,

    sck1_in,
    sdi1_in,
    sdo1_out,
    cs1_n_in,

    ready_n_ts_inout,

    status_led_n_out
  );



  reg [31:0] n = 0;
  reg [31:0] i = 0;

  localparam [359:0] test_spi0_data0 = {
    128'hdc6a3b8d_0c69421a_cb1a5434_e536f7d5,
    128'hc3c1b9e4_4cbb9b8f_95f0172e_fc48d2df,
    96'hdc141787_358b0553_535f0119
  };

  localparam [7:0] test_spi1_data0 = {
    8'h00
  };

  reg [359:0] test_spi0_data;
  reg [7:0] test_spi1_data;
  reg [31:0] result;

  initial
    begin

      $dumpfile("test_top.vcd");
      $dumpvars;

      test_spi0_data = test_spi0_data0;
      test_spi1_data = test_spi1_data0;


      clk_in = 0;
      reset_n_in = 1;
      sck0_in = 0;
      cs0_n_in = 1;
      sck1_in = 0;
      cs1_n_in = 1;



      #1 reset_n_in = 0;




 

      #1 cs1_n_in = 0;

      for (i = 0; i < 8; i = i + 1)
        begin

          #1 sdi1_in = test_spi1_data[7];
          test_spi1_data <= { test_spi1_data[6:0], 1'b0 };

          #1 sck1_in = 1;
          

          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;

          #1 sck1_in = 0;
          

          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
        end

      #1 cs1_n_in = 1;





      #1 cs0_n_in = 0;
     
      for (i = 0; i < 360; i = i + 1)
        begin

          #1 sdi0_in = test_spi0_data[351];
          test_spi0_data <= { test_spi0_data[350:0], 1'b0 };

          #1 sck0_in = 1;
          

          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;

          #1 sck0_in = 0;
          

          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
        end

      #1 cs0_n_in = 1;

      $display("Device configuration");
      $display("  nonce start MSB: %h", uut.nonce_start);

      $display("Job parameters:");
      $display("  SHA256 state:       %h", uut.sha_state[255:128]);
      $display("                      %h", uut.sha_state[127:0]);
      $display("  message head:       %h", uut.message_head);




 

      #1 reset_n_in = 1;

      for (n = 0; n < 50 && !ready_n_ts_inout; n = n + 1)
        begin

          for (i = 0; i < 64; i = i + 1)
            begin
              $display("nonce: %d", uut.pool.nonce);
              $display("round: %d", uut.pool.round);
              $display("  Kt: %h", uut.pool.Kt);
              $display("  success:                %b", uut.pool.success);
              $display("    |match_flags:         %b", |uut.pool.match_flags);
              $display("    round == 0:           %b", uut.pool.round == 0);
              $display("    skip_first:           %b", uut.pool.skip_first);
              $display("    skip_second:          %b", uut.pool.skip_second);
              $display("  u0.M: %h", uut.pool.tracks[0].u0.M[511:384]);
              $display("  u0.M: %h", uut.pool.tracks[0].u0.M[383:256]);
              $display("  u0.M: %h", uut.pool.tracks[0].u0.M[255:128]);
              $display("  u0.M: %h", uut.pool.tracks[0].u0.M[127:0]);
              $display("  u0.Wt: %h", uut.pool.tracks[0].u0.Wt);
              $display("  H_u0: %h", uut.pool.tracks[0].H_u0);
              $display("  u1.M: %h", uut.pool.tracks[0].u1.M[511:384]);
              $display("  u1.M: %h", uut.pool.tracks[0].u1.M[383:256]);
              $display("  u1.M: %h", uut.pool.tracks[0].u1.M[255:128]);
              $display("  u1.M: %h", uut.pool.tracks[0].u1.M[127:0]);
              $display("  u1.Wt: %h", uut.pool.tracks[0].u1.Wt);
              $display("  H_u1 (bs): %h", uut.pool.tracks[0].H_bs);
              $display("  H: %h", uut.pool.tracks[0].H);
              $display("    test bits: %h", { uut.pool.tracks[0].H[BASE_TARGET+16-1:16], uut.pool.tracks[0].H[15:0] & uut.pool.difficulty_bm });
              $display("");

              #1 clk_in = 1;
              #1 clk_in = 0;
            end

        end


      #1 clk_in = 1;
      #1 clk_in = 0;

      $display("nonce: %h", uut.nonce);
      $display("ext_io.result_data: %h", uut.ext_io.result_data);


      #1 clk_in = 1;
      #1 clk_in = 0;

      $display("nonce: %h", uut.nonce);
      $display("ext_io.result_data: %h", uut.ext_io.result_data);


      #1 cs1_n_in = 0;
      
      for (i = 0; i < 32; i = i + 1)
        begin
          $display("[%d] (%b) %b", i, ready_n_ts_inout, sdo1_out);

          #1 sck1_in = 1;
          

          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;

          result <= { result[30:0], sdo1_out };

          #1 sck1_in = 0;
          

          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
          #1 clk_in = 1;
          #1 clk_in = 0;
        end

      #1 cs1_n_in = 1;

      $display("top_test result: %h", result);

    end

endmodule