data/full_repos/permissive/104053853/digitron.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/104053853/digitron.v:22: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'frequency_divider\'\nmodule frequency_divider (input clock,\n       ^~~~~~~~~~~~~~~~~\n                                                                     : ... Top module \'hello_printer\'\nmodule hello_printer (input switch,\n       ^~~~~~~~~~~~~\n                                                                     : ... Top module \'fin_printer\'\nmodule fin_printer (input switch,\n       ^~~~~~~~~~~\n                                                                     : ... Top module \'digit_printer\'\nmodule digit_printer (input switch,\n       ^~~~~~~~~~~~~\n                                                                     : ... Top module \'bi_printer\'\nmodule bi_printer (input [7:0] seq1,\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module frequency_divider (input clock,
                          output reg new_clock);
reg [14:0] counter;

initial
begin
  counter = 0;
  new_clock = 0;
end

always @ (posedge clock)
begin
  counter <= counter + 1;
  if (counter == 16383)
  begin
    counter <= 0;
    new_clock <= ~new_clock;
  end
end
endmodule
module frequency_divider (input clock,
                          output reg new_clock);

reg [14:0] counter;

initial
begin
  counter = 0;
  new_clock = 0;
end

always @ (posedge clock)
begin
  counter <= counter + 1;
  if (counter == 16383)
  begin
    counter <= 0;
    new_clock <= ~new_clock;
  end
end
endmodule