data/full_repos/permissive/143278/ivltests/vhdl_test3.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_test3.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_test3.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_test3.v:7: Cannot find file containing module: \'dummy\'\n   dummy dut (.clk(clk), .\\input (in[3:0]), .\\output (out));\n   ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/dummy\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/dummy.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/dummy.sv\n             dummy\n             dummy.v\n             dummy.sv\n             obj_dir/dummy\n             obj_dir/dummy.v\n             obj_dir/dummy.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg clk;
   reg [4:0] in;
   wire [15:0] out;

   dummy dut (.clk(clk), .\input (in[3:0]), .\output (out));

   initial begin
      clk = 0;
      for (in = 0 ; in <= 16 ; in = in+1) begin
	 #1 clk = 1;
	 #1 clk = 0;
	 $display("input = %b, output=%b", in[3:0], out);
      end
   end

endmodule
module main;


   reg clk;
   reg [4:0] in;
   wire [15:0] out;

   dummy dut (.clk(clk), .\input (in[3:0]), .\output (out));

   initial begin
      clk = 0;
      for (in = 0 ; in <= 16 ; in = in+1) begin
	 #1 clk = 1;
	 #1 clk = 0;
	 $display("input = %b, output=%b", in[3:0], out);
      end
   end

endmodule