data/full_repos/permissive/131196995/hardware/clock.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/131196995/hardware/clock.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock(output clk);
    reg theClock = 1;

    assign clk = theClock;
    
    always begin
        #500;
        theClock = !theClock;
    end
endmodule
module clock(output clk);

    reg theClock = 1;

    assign clk = theClock;
    
    always begin
        #500;
        theClock = !theClock;
    end
endmodule