data/full_repos/permissive/160794640/example/divisor_test.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160794640/example/divisor_test.v:14: Operator NEGATE expects 63 bits on the LHS, but LHS\'s VARREF \'pcpi_rs2\' generates 32 bits.\n                                                                              : ... In instance divisor_test\n    divisor <= (divs && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/160794640/example/divisor_test.v:14: Operator COND expects 63 bits on the Conditional False, but Conditional False\'s VARREF \'pcpi_rs2\' generates 32 bits.\n                                                                              : ... In instance divisor_test\n    divisor <= (divs && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;\n                                     ^\n%Error: Exiting due to 2 warning(s)\n'
module divisor_test (
	input             clk, resetn,

	input [31:0]      pcpi_rs2,
        input             divs,
	output reg [62:0] divisor
);
	always @(posedge clk) begin
	   divisor <= (divs && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
	end
   
endmodule
module divisor_test (
	input             clk, resetn,

	input [31:0]      pcpi_rs2,
        input             divs,
	output reg [62:0] divisor
);

	always @(posedge clk) begin
	   divisor <= (divs && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
	end
   
endmodule