data/full_repos/permissive/106596430/moduleverilog.v
1: b'%Warning-WIDTH: data/full_repos/permissive/106596430/moduleverilog.v:74: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance DisplayInterface\n        counterDisplay <= 1\'b0;\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106596430/moduleverilog.v:126: Cannot find file containing module: \'hex2seg\'\n      hex2seg seg1 (.number(hexOutput),\n      ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/hex2seg\n             data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/hex2seg.v\n             data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/hex2seg.sv\n             hex2seg\n             hex2seg.v\n             hex2seg.sv\n             obj_dir/hex2seg\n             obj_dir/hex2seg.v\n             obj_dir/hex2seg.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module DisplayInterface(input clk5,
												input reset,
												input [3:0] point,
												input [15:0] dispVal,
												output reg [7:0] digit,
												output [7:0] segment
												);

					localparam  compare = 2047;
          reg [10:0] countClkDiv;
					reg [1:0] counterDisplay;
					reg Enable;
					reg [3:0] hexOutput;
					reg pointOn;


          always @(posedge clk5)
          	begin
          			if(reset)
									begin
              			countClkDiv <= 11'b0;
										Enable <= 1'b0;
									end
                else if (countClkDiv == compare)
									begin
										countClkDiv <= 11'b0;
										Enable <= 1'b1;
									end
								else
									begin
										countClkDiv <= countClkDiv + 1'b1;
										Enable <= 1'b0;
									end
						end



					always @(posedge clk5)
						begin
							if(reset)
								counterDisplay <= 1'b0;
							else if(Enable)
								counterDisplay <= counterDisplay + 1'b1;
							else
								counterDisplay <= counterDisplay;
						end


					always @(counterDisplay)
						case(counterDisplay)
							2'b00: hexOutput = dispVal[3:0];
							2'b01: hexOutput = dispVal[7:4];
							2'b10: hexOutput = dispVal[11:8];
							2'b11: hexOutput = dispVal[15:12];
						endcase


					always @(counterDisplay,point)
						case(counterDisplay)
							2'b00: begin
											digit = 8'b11111110;
											if(point[0] == 1'b1)
												pointOn = 1'b1;
											else
												pointOn = 1'b0;
										 end
							2'b01: begin
											digit = 8'b11111101;
											if(point[1] == 1'b1)
												pointOn = 1'b1;
											else
												pointOn = 1'b0;
										 end
							2'b10: begin
											digit = 8'b11111011;
											if(point[2] == 1'b1)
												pointOn = 1'b1;
											else
												pointOn = 1'b0;
										 end
							2'b11: begin
											digit = 8'b11110111;
											if(point[3] == 1'b1)
												pointOn = 1'b1;
											else
												pointOn = 1'b0;
										end
						endcase

						assign segment[0] = ~pointOn;


						hex2seg seg1 (.number(hexOutput),
													.pattern (segment[7:1])
													);

endmodule
module DisplayInterface(input clk5,
												input reset,
												input [3:0] point,
												input [15:0] dispVal,
												output reg [7:0] digit,
												output [7:0] segment
												);


					localparam  compare = 2047;
          reg [10:0] countClkDiv;
					reg [1:0] counterDisplay;
					reg Enable;
					reg [3:0] hexOutput;
					reg pointOn;


          always @(posedge clk5)
          	begin
          			if(reset)
									begin
              			countClkDiv <= 11'b0;
										Enable <= 1'b0;
									end
                else if (countClkDiv == compare)
									begin
										countClkDiv <= 11'b0;
										Enable <= 1'b1;
									end
								else
									begin
										countClkDiv <= countClkDiv + 1'b1;
										Enable <= 1'b0;
									end
						end



					always @(posedge clk5)
						begin
							if(reset)
								counterDisplay <= 1'b0;
							else if(Enable)
								counterDisplay <= counterDisplay + 1'b1;
							else
								counterDisplay <= counterDisplay;
						end


					always @(counterDisplay)
						case(counterDisplay)
							2'b00: hexOutput = dispVal[3:0];
							2'b01: hexOutput = dispVal[7:4];
							2'b10: hexOutput = dispVal[11:8];
							2'b11: hexOutput = dispVal[15:12];
						endcase


					always @(counterDisplay,point)
						case(counterDisplay)
							2'b00: begin
											digit = 8'b11111110;
											if(point[0] == 1'b1)
												pointOn = 1'b1;
											else
												pointOn = 1'b0;
										 end
							2'b01: begin
											digit = 8'b11111101;
											if(point[1] == 1'b1)
												pointOn = 1'b1;
											else
												pointOn = 1'b0;
										 end
							2'b10: begin
											digit = 8'b11111011;
											if(point[2] == 1'b1)
												pointOn = 1'b1;
											else
												pointOn = 1'b0;
										 end
							2'b11: begin
											digit = 8'b11110111;
											if(point[3] == 1'b1)
												pointOn = 1'b1;
											else
												pointOn = 1'b0;
										end
						endcase

						assign segment[0] = ~pointOn;


						hex2seg seg1 (.number(hexOutput),
													.pattern (segment[7:1])
													);

endmodule