data/full_repos/permissive/210844779/lab5/5.4/and.v
data/verilator_xmls/b165f56b-bc4a-4fe2-91b6-05949a52baac.xml
module and_1(a,b,c);
  input [15:0]a;
  input b;
  output [15:0]c;
    
  genvar i;
  
  generate for (i=15;i>=0;i=i-1)
	begin:loop
      and u1(c[i],a[i],b);
	end
  endgenerate
  
  endmodule
module and_1(a,b,c);

  input [15:0]a;
  input b;
  output [15:0]c;
    
  genvar i;
  
  generate for (i=15;i>=0;i=i-1)
	begin:loop
      and u1(c[i],a[i],b);
	end
  endgenerate
  
  endmodule