data/full_repos/permissive/121592400/learnCosts.v
1: b'%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:50: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s CONST \'11\'h48\' generates 11 bits.\n                                                                    : ... In instance learnCosts\n      address_count <= 11\'h48 + n*2;  \n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:50: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                    : ... In instance learnCosts\n      address_count <= 11\'h48 + n*2;  \n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:75: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s CONST \'11\'h68e\' generates 11 bits.\n                                                                    : ... In instance learnCosts\n      address_count <= 11\'h68E + 2*k;  \n                               ^\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:75: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                    : ... In instance learnCosts\n      address_count <= 11\'h68E + 2*k;  \n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:80: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s CONST \'11\'h8\' generates 11 bits.\n                                                                    : ... In instance learnCosts\n      address_count <= 11\'h8 + k*2;  \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:80: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                    : ... In instance learnCosts\n      address_count <= 11\'h8 + k*2;  \n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:87: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                    : ... In instance learnCosts\n     address_count <= sinkID_address_buf + k*2;  \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:99: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s CONST \'11\'h148\' generates 11 bits.\n                                                                    : ... In instance learnCosts\n     address_count <= 11\'h148 + n*2;  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:99: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                    : ... In instance learnCosts\n     address_count <= 11\'h148 + n*2;  \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:105: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s CONST \'11\'h1c8\' generates 11 bits.\n                                                                     : ... In instance learnCosts\n     address_count <= 11\'h1C8 + n*2;  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:105: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                     : ... In instance learnCosts\n     address_count <= 11\'h1C8 + n*2;  \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:135: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s CONST \'11\'h48\' generates 11 bits.\n                                                                     : ... In instance learnCosts\n     address_count <= 11\'h48 + neighborCount*2;  \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:135: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                     : ... In instance learnCosts\n     address_count <= 11\'h48 + neighborCount*2;  \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:142: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s CONST \'11\'h148\' generates 11 bits.\n                                                                     : ... In instance learnCosts\n     address_count <= 11\'h148 + neighborCount*2;  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:142: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                     : ... In instance learnCosts\n     address_count <= 11\'h148 + neighborCount*2;  \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:148: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s CONST \'11\'h1c8\' generates 11 bits.\n                                                                     : ... In instance learnCosts\n     address_count <= 11\'h1C8 + neighborCount*2;  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:148: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                     : ... In instance learnCosts\n     address_count <= 11\'h1C8 + neighborCount*2;  \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:154: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s CONST \'11\'hc8\' generates 11 bits.\n                                                                     : ... In instance learnCosts\n     address_count <= 11\'hC8 + neighborCount*2;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:154: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                     : ... In instance learnCosts\n     address_count <= 11\'hC8 + neighborCount*2;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:167: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s CONST \'11\'h68e\' generates 11 bits.\n                                                                     : ... In instance learnCosts\n      address_count <= 11\'h68E + 2*neighborCount;  \n                               ^\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:167: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                     : ... In instance learnCosts\n      address_count <= 11\'h68E + 2*neighborCount;  \n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:172: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s CONST \'11\'h8\' generates 11 bits.\n                                                                     : ... In instance learnCosts\n      address_count <= 11\'h8 + k*2;  \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:172: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                     : ... In instance learnCosts\n      address_count <= 11\'h8 + k*2;  \n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/121592400/learnCosts.v:179: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                     : ... In instance learnCosts\n     address_count <= sinkID_address_buf + 2*k;  \n                   ^~\n%Error: Exiting due to 24 warning(s)\n'
module learnCosts(clock, nrst, en, fsourceID, fbatteryStat, fValue, fclusterID, initial_epsilon, address, wr_en, data_in, data_out, done);
	input clock, nrst, en;
	input [`WORD_WIDTH-1:0] fsourceID, fbatteryStat, fValue, fclusterID, data_in, initial_epsilon;
	output done, wr_en;
	output [10:0] address;
	output [`WORD_WIDTH-1: 0] data_out;


	reg [10:0] address_count;
	reg [`WORD_WIDTH-1:0] data_out_buf, neighborCount, neighborCount_buf, knownSinkCount, cur_nID, cur_knownSink, cur_qValue, sinkID_address_buf;
	reg done_buf, found, reinit, wr_en_buf;
	reg [`WORD_WIDTH-1:0] n, k;
	reg [4:0] state;

	always @ (posedge clock) begin
		if (!nrst) begin
			done_buf <= 0;
			state <= 22;
			wr_en_buf <= 0;
			found <= 0;
			reinit <= 0;
			n = 0;
			k = 0;
		end
		else begin
			case (state)
				0: begin
					state <= 1;
					address_count <= 11'h68A;
				end
				1: begin
					neighborCount <= data_in;
					state <= 2;
					address_count <= 11'h688;
				end
				2: begin
					knownSinkCount <= data_in;
					state <= 3;
				end
				3: begin

					if (n == neighborCount)
						state <= 12;
					else begin
						address_count <= 11'h48 + n*2;
						state <= 4;
					end
				end
				4: begin
					cur_nID = data_in;


					if (cur_nID == fsourceID) begin
						found <= 1;
						state <= 5;


						sinkID_address_buf <= 16'h248 + 16*n;
					end
					else begin
						n = n + 1;
						state <= 3;
					end
				end
				5: begin
					if (k == knownSinkCount) begin


						data_out_buf = k;
						address_count <= 11'h68E + 2*k;
						wr_en_buf <= 1;
						state <= 8;
					end
					else begin
						address_count <= 11'h8 + k*2;
						state <= 6;
					end
				end
				6: begin
					cur_knownSink = data_in;
					data_out_buf = cur_knownSink;
					address_count <= sinkID_address_buf + k*2;
					wr_en_buf <= 1;
					state <= 7;
				end
				7: begin
					wr_en_buf <= 0;
					k = k + 1;
					state <= 5;
				end
				8: begin

					data_out_buf = fbatteryStat;
					address_count <= 11'h148 + n*2;
					wr_en_buf <= 1;
					state <= 9;
				end
				9: begin
					wr_en_buf <= 0;
					address_count <= 11'h1C8 + n*2;
					state <= 10;
				end
				10: begin
					cur_qValue = data_in;
					data_out_buf = cur_qValue;
					wr_en_buf <= 1;

					if (cur_qValue < fValue)
						reinit <= 1;
					else
						reinit <= 0;

					state <= 11;
				end
				11: begin
					if (found) begin
						if (reinit) begin
							data_out_buf = initial_epsilon;
							address_count <= 11'h4;
							wr_en_buf <= 1;
							state <= 20;
						end
						else
							state <= 21;
					end
					else 
						state <= 21;
				end
				12: begin
					address_count <= 11'h48 + neighborCount*2;
					data_out_buf = fsourceID;
					wr_en_buf <= 1;
					state <= 13;
				end
				13: begin

					address_count <= 11'h148 + neighborCount*2;
					data_out_buf = fbatteryStat;
					wr_en_buf <= 1;
					state <= 14;	
				end
				14: begin
					address_count <= 11'h1C8 + neighborCount*2;
					data_out_buf = fValue;
					wr_en_buf <= 1;
					state <= 15;
				end
				15: begin
					address_count <= 11'hC8 + neighborCount*2;
					data_out_buf = fclusterID;
					wr_en_buf <= 1;
					k = 0;


					sinkID_address_buf <= 16'h248 + 16*neighborCount;
					
					state <= 16; 
				end
				16: begin
					if (k == knownSinkCount) begin
						state <= 19;
						address_count <= 11'h68E + 2*neighborCount;
						data_out_buf = k;
						wr_en_buf <= 1;
					end
					else begin
						address_count <= 11'h8 + k*2;
						state <= 17;
					end
				end
				17: begin
					cur_knownSink = data_in;
					data_out_buf = cur_knownSink;
					address_count <= sinkID_address_buf + 2*k;
					wr_en_buf <= 1;
					state <= 18;
				end
				18: begin
					wr_en_buf <= 0;
					k = k + 1;
					state <= 16;
				end
				19: begin
					data_out_buf = neighborCount + 1;
					address_count <= 11'h68A;
					wr_en_buf <= 1;
					state <= 20;
				end
				20: begin
					wr_en_buf <= 0;
					state <= 21;
				end
				21: begin
					done_buf <= 1;
					state <= 22;
				end
				22: begin
					if (en) begin
						state <= 0;
						done_buf <= 0;
						wr_en_buf <= 0;
						found <= 0;
						reinit <= 0;
						n = 0;
						k = 0;
					end
					else
						state <= 22;
				end

				default: 
					state <= 22;
			endcase
		end
	end

	assign done = done_buf;
	assign address = address_count;
	assign data_out = data_out_buf;
	assign wr_en = wr_en_buf;
endmodule
module learnCosts(clock, nrst, en, fsourceID, fbatteryStat, fValue, fclusterID, initial_epsilon, address, wr_en, data_in, data_out, done);

	input clock, nrst, en;
	input [`WORD_WIDTH-1:0] fsourceID, fbatteryStat, fValue, fclusterID, data_in, initial_epsilon;
	output done, wr_en;
	output [10:0] address;
	output [`WORD_WIDTH-1: 0] data_out;


	reg [10:0] address_count;
	reg [`WORD_WIDTH-1:0] data_out_buf, neighborCount, neighborCount_buf, knownSinkCount, cur_nID, cur_knownSink, cur_qValue, sinkID_address_buf;
	reg done_buf, found, reinit, wr_en_buf;
	reg [`WORD_WIDTH-1:0] n, k;
	reg [4:0] state;

	always @ (posedge clock) begin
		if (!nrst) begin
			done_buf <= 0;
			state <= 22;
			wr_en_buf <= 0;
			found <= 0;
			reinit <= 0;
			n = 0;
			k = 0;
		end
		else begin
			case (state)
				0: begin
					state <= 1;
					address_count <= 11'h68A;
				end
				1: begin
					neighborCount <= data_in;
					state <= 2;
					address_count <= 11'h688;
				end
				2: begin
					knownSinkCount <= data_in;
					state <= 3;
				end
				3: begin

					if (n == neighborCount)
						state <= 12;
					else begin
						address_count <= 11'h48 + n*2;
						state <= 4;
					end
				end
				4: begin
					cur_nID = data_in;


					if (cur_nID == fsourceID) begin
						found <= 1;
						state <= 5;


						sinkID_address_buf <= 16'h248 + 16*n;
					end
					else begin
						n = n + 1;
						state <= 3;
					end
				end
				5: begin
					if (k == knownSinkCount) begin


						data_out_buf = k;
						address_count <= 11'h68E + 2*k;
						wr_en_buf <= 1;
						state <= 8;
					end
					else begin
						address_count <= 11'h8 + k*2;
						state <= 6;
					end
				end
				6: begin
					cur_knownSink = data_in;
					data_out_buf = cur_knownSink;
					address_count <= sinkID_address_buf + k*2;
					wr_en_buf <= 1;
					state <= 7;
				end
				7: begin
					wr_en_buf <= 0;
					k = k + 1;
					state <= 5;
				end
				8: begin

					data_out_buf = fbatteryStat;
					address_count <= 11'h148 + n*2;
					wr_en_buf <= 1;
					state <= 9;
				end
				9: begin
					wr_en_buf <= 0;
					address_count <= 11'h1C8 + n*2;
					state <= 10;
				end
				10: begin
					cur_qValue = data_in;
					data_out_buf = cur_qValue;
					wr_en_buf <= 1;

					if (cur_qValue < fValue)
						reinit <= 1;
					else
						reinit <= 0;

					state <= 11;
				end
				11: begin
					if (found) begin
						if (reinit) begin
							data_out_buf = initial_epsilon;
							address_count <= 11'h4;
							wr_en_buf <= 1;
							state <= 20;
						end
						else
							state <= 21;
					end
					else 
						state <= 21;
				end
				12: begin
					address_count <= 11'h48 + neighborCount*2;
					data_out_buf = fsourceID;
					wr_en_buf <= 1;
					state <= 13;
				end
				13: begin

					address_count <= 11'h148 + neighborCount*2;
					data_out_buf = fbatteryStat;
					wr_en_buf <= 1;
					state <= 14;	
				end
				14: begin
					address_count <= 11'h1C8 + neighborCount*2;
					data_out_buf = fValue;
					wr_en_buf <= 1;
					state <= 15;
				end
				15: begin
					address_count <= 11'hC8 + neighborCount*2;
					data_out_buf = fclusterID;
					wr_en_buf <= 1;
					k = 0;


					sinkID_address_buf <= 16'h248 + 16*neighborCount;
					
					state <= 16; 
				end
				16: begin
					if (k == knownSinkCount) begin
						state <= 19;
						address_count <= 11'h68E + 2*neighborCount;
						data_out_buf = k;
						wr_en_buf <= 1;
					end
					else begin
						address_count <= 11'h8 + k*2;
						state <= 17;
					end
				end
				17: begin
					cur_knownSink = data_in;
					data_out_buf = cur_knownSink;
					address_count <= sinkID_address_buf + 2*k;
					wr_en_buf <= 1;
					state <= 18;
				end
				18: begin
					wr_en_buf <= 0;
					k = k + 1;
					state <= 16;
				end
				19: begin
					data_out_buf = neighborCount + 1;
					address_count <= 11'h68A;
					wr_en_buf <= 1;
					state <= 20;
				end
				20: begin
					wr_en_buf <= 0;
					state <= 21;
				end
				21: begin
					done_buf <= 1;
					state <= 22;
				end
				22: begin
					if (en) begin
						state <= 0;
						done_buf <= 0;
						wr_en_buf <= 0;
						found <= 0;
						reinit <= 0;
						n = 0;
						k = 0;
					end
					else
						state <= 22;
				end

				default: 
					state <= 22;
			endcase
		end
	end

	assign done = done_buf;
	assign address = address_count;
	assign data_out = data_out_buf;
	assign wr_en = wr_en_buf;
endmodule