data/full_repos/permissive/198223683/rtl/video/lspc_regs.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/198223683/rtl/video/lspc_regs.v:111: Cannot find file containing module: 'FDS16bit'\n FDS16bit B138(~LSPOE, CPU_DATA_MUX, CPU_DATA_OUT);\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/198223683/rtl/video,data/full_repos/permissive/198223683/FDS16bit\n             data/full_repos/permissive/198223683/rtl/video,data/full_repos/permissive/198223683/FDS16bit.v\n             data/full_repos/permissive/198223683/rtl/video,data/full_repos/permissive/198223683/FDS16bit.sv\n             FDS16bit\n             FDS16bit.v\n             FDS16bit.sv\n             obj_dir/FDS16bit\n             obj_dir/FDS16bit.v\n             obj_dir/FDS16bit.sv\n%Error: data/full_repos/permissive/198223683/rtl/video/lspc_regs.v:116: Cannot find file containing module: 'FDS16bit'\n FDS16bit F155(~WR_VRAM_RW, M68K_DATA, REG_VRAMRW);\n ^~~~~~~~\n%Error: data/full_repos/permissive/198223683/rtl/video/lspc_regs.v:122: Cannot find file containing module: 'FDPCell'\n FDPCell D38(~WR_VRAM_RW, 1'b1, 1'b1, D32A_OUT, D38_Q, nVRAM_WRITE_REQ);\n ^~~~~~~\n%Error: data/full_repos/permissive/198223683/rtl/video/lspc_regs.v:123: Cannot find file containing module: 'FDPCell'\n FDPCell D28(D112B_OUT, 1'b1, 1'b1, D38_Q, , D28_nQ);\n ^~~~~~~\n%Error: data/full_repos/permissive/198223683/rtl/video/lspc_regs.v:127: Cannot find file containing module: 'FDS16bit'\n FDS16bit H105(~WR_VRAM_MOD, M68K_DATA, REG_VRAMMOD);\n ^~~~~~~~\n%Error: data/full_repos/permissive/198223683/rtl/video/lspc_regs.v:131: Cannot find file containing module: 'FDS16bit'\n FDS16bit F47(~WR_VRAM_ADDR, M68K_DATA, REG_VRAMADDR);\n ^~~~~~~~\n%Error: data/full_repos/permissive/198223683/rtl/video/lspc_regs.v:134: Cannot find file containing module: 'FDSCell'\n FDSCell E105(WR_LSPC_MODE, M68K_DATA[15:12], AA_SPEED[7:4]);\n ^~~~~~~\n%Error: data/full_repos/permissive/198223683/rtl/video/lspc_regs.v:135: Cannot find file containing module: 'FDSCell'\n FDSCell C87(WR_LSPC_MODE, M68K_DATA[11:8], AA_SPEED[3:0]);\n ^~~~~~~\n%Error: data/full_repos/permissive/198223683/rtl/video/lspc_regs.v:136: Cannot find file containing module: 'FDPCell'\n FDPCell E74(WR_LSPC_MODE, M68K_DATA[7], 1'b1, RESET, TIMER_MODE[2]);\n ^~~~~~~\n%Error: data/full_repos/permissive/198223683/rtl/video/lspc_regs.v:137: Cannot find file containing module: 'FDRCell'\n FDRCell E61(WR_LSPC_MODE, M68K_DATA[6:3], RESET, {TIMER_MODE[1:0], TIMER_IRQ_EN, AA_DISABLE});\n ^~~~~~~\n%Error: data/full_repos/permissive/198223683/rtl/video/lspc_regs.v:140: Cannot find file containing module: 'FDPCell'\n FDPCell D34(WR_TIMER_STOP, M68K_DATA[0], RESETP, 1'b1, , TIMER_STOP);\n ^~~~~~~\n%Error: Exiting due to 11 error(s)\n"
module lspc_regs(
	input RESET,
	input RESETP,
	
	input [3:1] M68K_ADDR,
	input [15:0] M68K_DATA,
	
	input LSPOE,
	input LSPWE,
	
	input VMODE,
	input [8:0] RASTERC,
	input [2:0] AA_COUNT,
	input [15:0] VRAM_LOW_READ,
	input [15:0] VRAM_HIGH_READ,
	
	
	output WR_VRAM_ADDR,
	output WR_VRAM_RW,
	output WR_TIMER_HIGH,
	output WR_TIMER_LOW,
	output WR_IRQ_ACK,
	
	output [15:0] REG_VRAMADDR,
	output [15:0] REG_VRAMMOD,
	output [15:0] REG_VRAMRW,
	output [15:0] REG_LSPCMODE,
	output [15:0] CPU_DATA_OUT,
	output [7:0] AA_SPEED,
	output [2:0] TIMER_MODE,
	output TIMER_IRQ_EN,
	output AA_DISABLE,
	output TIMER_STOP,
	output nVRAM_WRITE_REQ,
	input D112B_OUT
);

	reg [7:0] WR_DECODED;
	wire [15:0] CPU_DATA_MUX;
	


	always @(*)
	begin
		if (~LSPWE)
		begin
			case (M68K_ADDR)
				3'h0 : WR_DECODED <= 8'b11111110;
				3'h1 : WR_DECODED <= 8'b11111101;
				3'h2 : WR_DECODED <= 8'b11111011;
				3'h3 : WR_DECODED <= 8'b11110111;
				3'h4 : WR_DECODED <= 8'b11101111;
				3'h5 : WR_DECODED <= 8'b11011111;
				3'h6 : WR_DECODED <= 8'b10111111;
				3'h7 : WR_DECODED <= 8'b01111111;
			endcase
		end
		else
			WR_DECODED <= 8'b11111111;
	end
	
	assign WR_VRAM_ADDR = WR_DECODED[0];
	assign WR_VRAM_RW = WR_DECODED[1];
	wire WR_VRAM_MOD = WR_DECODED[2];
	wire WR_LSPC_MODE = WR_DECODED[3];
	assign WR_TIMER_HIGH = WR_DECODED[4];
	assign WR_TIMER_LOW = WR_DECODED[5];
	assign WR_IRQ_ACK = WR_DECODED[6];
	wire WR_TIMER_STOP = WR_DECODED[7];
	
	

	assign REG_LSPCMODE = {RASTERC, 3'b0, VMODE, AA_COUNT};
	






	wire CPU_READ_SW = ~|{~|{M68K_ADDR[1], ~M68K_ADDR[2]}, ~|{REG_VRAMADDR[15], M68K_ADDR[2]}};
	





	assign CPU_DATA_MUX = M68K_ADDR[2] ?
							CPU_READ_SW ? REG_LSPCMODE : REG_VRAMMOD
							:
							CPU_READ_SW ? VRAM_HIGH_READ : VRAM_LOW_READ;
	


	FDS16bit B138(~LSPOE, CPU_DATA_MUX, CPU_DATA_OUT);




	FDS16bit F155(~WR_VRAM_RW, M68K_DATA, REG_VRAMRW);



	wire D32A_OUT = D28_nQ & 1'b1;
	wire D38_Q, D28_nQ;
	FDPCell D38(~WR_VRAM_RW, 1'b1, 1'b1, D32A_OUT, D38_Q, nVRAM_WRITE_REQ);
	FDPCell D28(D112B_OUT, 1'b1, 1'b1, D38_Q, , D28_nQ);
	


	FDS16bit H105(~WR_VRAM_MOD, M68K_DATA, REG_VRAMMOD);
	


	FDS16bit F47(~WR_VRAM_ADDR, M68K_DATA, REG_VRAMADDR);


	FDSCell E105(WR_LSPC_MODE, M68K_DATA[15:12], AA_SPEED[7:4]);
	FDSCell C87(WR_LSPC_MODE, M68K_DATA[11:8], AA_SPEED[3:0]);
	FDPCell E74(WR_LSPC_MODE, M68K_DATA[7], 1'b1, RESET, TIMER_MODE[2]);
	FDRCell E61(WR_LSPC_MODE, M68K_DATA[6:3], RESET, {TIMER_MODE[1:0], TIMER_IRQ_EN, AA_DISABLE});
	

	FDPCell D34(WR_TIMER_STOP, M68K_DATA[0], RESETP, 1'b1, , TIMER_STOP);

endmodule
module lspc_regs(
	input RESET,
	input RESETP,
	
	input [3:1] M68K_ADDR,
	input [15:0] M68K_DATA,
	
	input LSPOE,
	input LSPWE,
	
	input VMODE,
	input [8:0] RASTERC,
	input [2:0] AA_COUNT,
	input [15:0] VRAM_LOW_READ,
	input [15:0] VRAM_HIGH_READ,
	
	
	output WR_VRAM_ADDR,
	output WR_VRAM_RW,
	output WR_TIMER_HIGH,
	output WR_TIMER_LOW,
	output WR_IRQ_ACK,
	
	output [15:0] REG_VRAMADDR,
	output [15:0] REG_VRAMMOD,
	output [15:0] REG_VRAMRW,
	output [15:0] REG_LSPCMODE,
	output [15:0] CPU_DATA_OUT,
	output [7:0] AA_SPEED,
	output [2:0] TIMER_MODE,
	output TIMER_IRQ_EN,
	output AA_DISABLE,
	output TIMER_STOP,
	output nVRAM_WRITE_REQ,
	input D112B_OUT
);


	reg [7:0] WR_DECODED;
	wire [15:0] CPU_DATA_MUX;
	


	always @(*)
	begin
		if (~LSPWE)
		begin
			case (M68K_ADDR)
				3'h0 : WR_DECODED <= 8'b11111110;
				3'h1 : WR_DECODED <= 8'b11111101;
				3'h2 : WR_DECODED <= 8'b11111011;
				3'h3 : WR_DECODED <= 8'b11110111;
				3'h4 : WR_DECODED <= 8'b11101111;
				3'h5 : WR_DECODED <= 8'b11011111;
				3'h6 : WR_DECODED <= 8'b10111111;
				3'h7 : WR_DECODED <= 8'b01111111;
			endcase
		end
		else
			WR_DECODED <= 8'b11111111;
	end
	
	assign WR_VRAM_ADDR = WR_DECODED[0];
	assign WR_VRAM_RW = WR_DECODED[1];
	wire WR_VRAM_MOD = WR_DECODED[2];
	wire WR_LSPC_MODE = WR_DECODED[3];
	assign WR_TIMER_HIGH = WR_DECODED[4];
	assign WR_TIMER_LOW = WR_DECODED[5];
	assign WR_IRQ_ACK = WR_DECODED[6];
	wire WR_TIMER_STOP = WR_DECODED[7];
	
	

	assign REG_LSPCMODE = {RASTERC, 3'b0, VMODE, AA_COUNT};
	






	wire CPU_READ_SW = ~|{~|{M68K_ADDR[1], ~M68K_ADDR[2]}, ~|{REG_VRAMADDR[15], M68K_ADDR[2]}};
	





	assign CPU_DATA_MUX = M68K_ADDR[2] ?
							CPU_READ_SW ? REG_LSPCMODE : REG_VRAMMOD
							:
							CPU_READ_SW ? VRAM_HIGH_READ : VRAM_LOW_READ;
	


	FDS16bit B138(~LSPOE, CPU_DATA_MUX, CPU_DATA_OUT);




	FDS16bit F155(~WR_VRAM_RW, M68K_DATA, REG_VRAMRW);



	wire D32A_OUT = D28_nQ & 1'b1;
	wire D38_Q, D28_nQ;
	FDPCell D38(~WR_VRAM_RW, 1'b1, 1'b1, D32A_OUT, D38_Q, nVRAM_WRITE_REQ);
	FDPCell D28(D112B_OUT, 1'b1, 1'b1, D38_Q, , D28_nQ);
	


	FDS16bit H105(~WR_VRAM_MOD, M68K_DATA, REG_VRAMMOD);
	


	FDS16bit F47(~WR_VRAM_ADDR, M68K_DATA, REG_VRAMADDR);


	FDSCell E105(WR_LSPC_MODE, M68K_DATA[15:12], AA_SPEED[7:4]);
	FDSCell C87(WR_LSPC_MODE, M68K_DATA[11:8], AA_SPEED[3:0]);
	FDPCell E74(WR_LSPC_MODE, M68K_DATA[7], 1'b1, RESET, TIMER_MODE[2]);
	FDRCell E61(WR_LSPC_MODE, M68K_DATA[6:3], RESET, {TIMER_MODE[1:0], TIMER_IRQ_EN, AA_DISABLE});
	

	FDPCell D34(WR_TIMER_STOP, M68K_DATA[0], RESETP, 1'b1, , TIMER_STOP);

endmodule