data/full_repos/permissive/143278/fpga_tests/sqrt_tb.v
 line:52: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/sqrt_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = !clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/sqrt_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #1 reset = 0;\n  ^\n%Error: data/full_repos/permissive/143278/fpga_tests/sqrt_tb.v:25: syntax error, unexpected \'@\'\n  @(negedge clk) ;\n  ^\n%Error: data/full_repos/permissive/143278/fpga_tests/sqrt_tb.v:32: syntax error, unexpected \'@\'\n     @(posedge clk)  ;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/sqrt_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #100 GSR = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/sqrt_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #100 x = 1;\n      ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [31:0] x;
   reg	      clk, reset;

   wire [15:0] y;
   wire        rdy;

   chip_root dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));

   (* ivl_synthesis_off *)
   always #5 clk = !clk;

   task reset_dut;
      begin
	 reset = 1;
	 #1 reset = 0;
	 @(negedge clk) ;
      end
   endtask

   task crank_dut;
      begin
	 while (rdy == 0) begin
	    @(posedge clk);
	 end
      end
   endtask

   reg        GSR;
   assign      glbl.GSR = GSR;

   integer idx;

   (* ivl_synthesis_off *)
   initial begin
      reset = 0;
      clk = 0;


      GSR = 1;
      #100 GSR = 0;
      #100 x = 1;
      reset_dut;
      crank_dut;
      $display("x=%d, y=%d", x, y);

      x = 3;
      reset_dut;
      crank_dut;
      $display("x=%d, y=%d", x, y);

      x = 4;
      reset_dut;
      crank_dut;
      $display("x=%d, y=%d", x, y);

      for (idx = 0 ;  idx < 200 ;  idx = idx + 1) begin
	 x = $random;
	 reset_dut;
	 crank_dut;
	 $display("x=%d, y=%d", x, y);

	 if (x < (y * y)) begin
	    $display("ERROR: y is too big");
	    $finish;
	 end

	 if (x > ((y + 1)*(y + 1))) begin
	    $display("ERROR: y is too small");
	    $finish;
	 end
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   reg [31:0] x;
   reg	      clk, reset;

   wire [15:0] y;
   wire        rdy;

   chip_root dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));

   (* ivl_synthesis_off *)
   always #5 clk = !clk;

   task reset_dut;
      begin
	 reset = 1;
	 #1 reset = 0;
	 @(negedge clk) ;
      end
   endtask

   task crank_dut;
      begin
	 while (rdy == 0) begin
	    @(posedge clk);
	 end
      end
   endtask

   reg        GSR;
   assign      glbl.GSR = GSR;

   integer idx;

   (* ivl_synthesis_off *)
   initial begin
      reset = 0;
      clk = 0;


      GSR = 1;
      #100 GSR = 0;
      #100 x = 1;
      reset_dut;
      crank_dut;
      $display("x=%d, y=%d", x, y);

      x = 3;
      reset_dut;
      crank_dut;
      $display("x=%d, y=%d", x, y);

      x = 4;
      reset_dut;
      crank_dut;
      $display("x=%d, y=%d", x, y);

      for (idx = 0 ;  idx < 200 ;  idx = idx + 1) begin
	 x = $random;
	 reset_dut;
	 crank_dut;
	 $display("x=%d, y=%d", x, y);

	 if (x < (y * y)) begin
	    $display("ERROR: y is too big");
	    $finish;
	 end

	 if (x > ((y + 1)*(y + 1))) begin
	    $display("ERROR: y is too small");
	    $finish;
	 end
      end

      $display("PASSED");
      $finish;
   end

endmodule