data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/m_stat.v
'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte
1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/m_stat.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n             const_defination.v\n             const_defination.v.v\n             const_defination.v.sv\n             obj_dir/const_defination.v\n             obj_dir/const_defination.v.v\n             obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/m_stat.v:26: Define or directive not defined: \'`statBus\'\n input wire[`statBus] stat,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/m_stat.v:26: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`statBus] stat,\n                    ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/m_stat.v:27: Define or directive not defined: \'`statBus\'\n output reg[`statBus] m_stat\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/m_stat.v:34: Define or directive not defined: \'`dmem_error\'\n   m_stat=`dmem_error;\n          ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module m_stat(
	input wire dmem_error,
	input wire[`statBus] stat,
	output reg[`statBus] m_stat
    );
	
	always@(*)
	begin
		if(dmem_error==1)
		begin
			m_stat=`dmem_error;
		end
		else
		begin
			m_stat=stat;
		end
	end
endmodule
module m_stat(
	input wire dmem_error,
	input wire[`statBus] stat,
	output reg[`statBus] m_stat
    );

	
	always@(*)
	begin
		if(dmem_error==1)
		begin
			m_stat=`dmem_error;
		end
		else
		begin
			m_stat=stat;
		end
	end
endmodule