data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #200000  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #550000000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #200000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:135: Unsupported: Ignoring delay on this delayed statement.\n        # 1 clock = ~clock;\n        ^\n%Error: data/full_repos/permissive/105948944/simulations/movingReverse_testBench.v:35: Cannot find file containing module: \'movingReverse\'\n    movingReverse testU1(\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/movingReverse\n             data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/movingReverse.v\n             data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/movingReverse.sv\n             movingReverse\n             movingReverse.v\n             movingReverse.sv\n             obj_dir/movingReverse\n             obj_dir/movingReverse.v\n             obj_dir/movingReverse.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module movingReverse_testBench(
    );
    
    reg clock;
    reg canMove_reg;
    reg isMoving_forward_reg;
    reg sensorIR_back_reg;
    reg [3:0] sensIP_back_reg;
    reg [3:0] presentINs_Reg;
    wire [3:0]sendToH_BridgeINs_wire;
    wire isMoving_out_wire;
    
    movingReverse testU1(
        .clock(clock),
        .canMove(canMove_reg),
        .isMoving_forward(isMoving_forward_reg),
        .sensorIR_back(sensorIR_back_reg),
        .sensIP_back(sensIP_back_reg),
        .presentINs(presentINs_Reg),
        .sendToH_BridgeINs(sendToH_BridgeINs_wire),
        .isMoving_out(isMoving_out_wire)

        );
       
    initial begin
        clock <= 0;
        canMove_reg <= 1'b1;
        isMoving_forward_reg <= 1'b0;
        sensIP_back_reg  <= 4'b0000;
        sensorIR_back_reg <= 1'b0;

        presentINs_Reg <= 4'b0000;
        
        #200000
        sensIP_back_reg  <= 4'b0000;
        
        #200000
        sensIP_back_reg  <= 4'b0001;
        
        #200000
        sensIP_back_reg  <= 4'b0010;
        
        #200000
        sensIP_back_reg  <= 4'b0011;
        
        #200000
        sensIP_back_reg  <= 4'b0100;
        
        #200000
        sensIP_back_reg  <= 4'b0101;
        
        #200000
        sensIP_back_reg  <= 4'b0110;
        
        #200000
        sensIP_back_reg  <= 4'b0111;
        
        #200000
        sensIP_back_reg  <= 4'b1000;
        
        #200000
        sensIP_back_reg  <= 4'b1001;
        
        #200000
        sensIP_back_reg  <= 4'b1010;
        
        #200000
        sensIP_back_reg  <= 4'b1011;
        
        #200000
        sensIP_back_reg  <= 4'b1100;
        
        #200000
        sensIP_back_reg  <= 4'b1110;
        
        #200000
        sensIP_back_reg  <= 4'b1111;
        
        #200000
        sensIP_back_reg  <= 4'b0110;
        sensorIR_back_reg <= 1'b1;
        
        #200000
        sensorIR_back_reg <= 1'b0;
        sensIP_back_reg  <= 4'b0000;
        

        #550000000


        

        isMoving_forward_reg <= 1'b0;
        canMove_reg <= 1;
        sensorIR_back_reg <= 1'b0;
        sensIP_back_reg  <= 4'b1001;
        #200000
        isMoving_forward_reg <= 1'b0;
        canMove_reg <= 0;
        sensorIR_back_reg <= 1'b0;
        sensIP_back_reg  <= 4'b0000;
        
    end
    
    always@(posedge clock) begin
        if (~isMoving_out_wire)
            canMove_reg <= 0;
        else
             canMove_reg <= canMove_reg;
    end
    
        always begin
        # 1 clock = ~clock;
        end    
endmodule
module movingReverse_testBench(
    );

    
    reg clock;
    reg canMove_reg;
    reg isMoving_forward_reg;
    reg sensorIR_back_reg;
    reg [3:0] sensIP_back_reg;
    reg [3:0] presentINs_Reg;
    wire [3:0]sendToH_BridgeINs_wire;
    wire isMoving_out_wire;
    
    movingReverse testU1(
        .clock(clock),
        .canMove(canMove_reg),
        .isMoving_forward(isMoving_forward_reg),
        .sensorIR_back(sensorIR_back_reg),
        .sensIP_back(sensIP_back_reg),
        .presentINs(presentINs_Reg),
        .sendToH_BridgeINs(sendToH_BridgeINs_wire),
        .isMoving_out(isMoving_out_wire)

        );
       
    initial begin
        clock <= 0;
        canMove_reg <= 1'b1;
        isMoving_forward_reg <= 1'b0;
        sensIP_back_reg  <= 4'b0000;
        sensorIR_back_reg <= 1'b0;

        presentINs_Reg <= 4'b0000;
        
        #200000
        sensIP_back_reg  <= 4'b0000;
        
        #200000
        sensIP_back_reg  <= 4'b0001;
        
        #200000
        sensIP_back_reg  <= 4'b0010;
        
        #200000
        sensIP_back_reg  <= 4'b0011;
        
        #200000
        sensIP_back_reg  <= 4'b0100;
        
        #200000
        sensIP_back_reg  <= 4'b0101;
        
        #200000
        sensIP_back_reg  <= 4'b0110;
        
        #200000
        sensIP_back_reg  <= 4'b0111;
        
        #200000
        sensIP_back_reg  <= 4'b1000;
        
        #200000
        sensIP_back_reg  <= 4'b1001;
        
        #200000
        sensIP_back_reg  <= 4'b1010;
        
        #200000
        sensIP_back_reg  <= 4'b1011;
        
        #200000
        sensIP_back_reg  <= 4'b1100;
        
        #200000
        sensIP_back_reg  <= 4'b1110;
        
        #200000
        sensIP_back_reg  <= 4'b1111;
        
        #200000
        sensIP_back_reg  <= 4'b0110;
        sensorIR_back_reg <= 1'b1;
        
        #200000
        sensorIR_back_reg <= 1'b0;
        sensIP_back_reg  <= 4'b0000;
        

        #550000000


        

        isMoving_forward_reg <= 1'b0;
        canMove_reg <= 1;
        sensorIR_back_reg <= 1'b0;
        sensIP_back_reg  <= 4'b1001;
        #200000
        isMoving_forward_reg <= 1'b0;
        canMove_reg <= 0;
        sensorIR_back_reg <= 1'b0;
        sensIP_back_reg  <= 4'b0000;
        
    end
    
    always@(posedge clock) begin
        if (~isMoving_out_wire)
            canMove_reg <= 0;
        else
             canMove_reg <= canMove_reg;
    end
    
        always begin
        # 1 clock = ~clock;
        end    
endmodule