data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_flow_tb.v
 line:36: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_flow_tb.v:5: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clock <= ~clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_flow_tb.v:19: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("iobstb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_flow_tb.v:20: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_flow_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_flow_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_flow_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_flow_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_flow_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iobs_flow_tb;

reg	clock	= 1;
always	#5 clock	<= ~clock;

reg	reset_n;

reg	[1:0]	dm	= 2'b11;
reg	send	= 0;
wire	[1:0]	dqs;

wire	[1:0]	ddr_dm;
wire	[1:0]	ddr_dqs;


initial begin : Sim
	$write ("%% ");
	$dumpfile ("iobstb.vcd");
	$dumpvars;
	
	#1
	reset_n	<= 0;
	
	#20
	reset_n	<= 1;
	
	#20
	dm	<= 2'b00;
	send	<= 1;
	
	#10
	send	<= 0;
	
	#40
	$finish;
end


iobs_flow FLOWIOBS0 (
	.clock_i	(clock),
	.reset_ni	(reset_n),
	
	.ctl_dm_i	(dm),
	.ctl_dqs_i	({send, send}),
	.ctl_dqs_o	(dqs),
	
	.ddr_dm_o	(ddr_dm),
	.ddr_dqs_io	(ddr_dqs)
);


endmodule
module iobs_flow_tb;


reg	clock	= 1;
always	#5 clock	<= ~clock;

reg	reset_n;

reg	[1:0]	dm	= 2'b11;
reg	send	= 0;
wire	[1:0]	dqs;

wire	[1:0]	ddr_dm;
wire	[1:0]	ddr_dqs;


initial begin : Sim
	$write ("%% ");
	$dumpfile ("iobstb.vcd");
	$dumpvars;
	
	#1
	reset_n	<= 0;
	
	#20
	reset_n	<= 1;
	
	#20
	dm	<= 2'b00;
	send	<= 1;
	
	#10
	send	<= 0;
	
	#40
	$finish;
end


iobs_flow FLOWIOBS0 (
	.clock_i	(clock),
	.reset_ni	(reset_n),
	
	.ctl_dm_i	(dm),
	.ctl_dqs_i	({send, send}),
	.ctl_dqs_o	(dqs),
	
	.ddr_dm_o	(ddr_dm),
	.ddr_dqs_io	(ddr_dqs)
);


endmodule