data/full_repos/permissive/104269513/Fifo_mem.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/Fifo_mem.v:125: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/Fifo_mem.v:128: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk = ~clk; \n        ^\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:137: Too many digits for 32 bit number: \'hff_9999_1010_0101_1010\n    in_fifo <= \'hff_9999_1010_0101_1010;\n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:141: Too many digits for 32 bit number: \'h00_0101_1010_0101_1010\n    in_fifo <= \'h00_0101_1010_0101_1010;   \n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:146: Too many digits for 32 bit number: \'h00_ABCD_AAAA_CAFE_0000\n    in_fifo <= \'h00_ABCD_AAAA_CAFE_0000; \n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:150: Too many digits for 32 bit number: \'hff_0101_1010_0101_9999\n    in_fifo <= \'hff_0101_1010_0101_9999;   \n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:156: Too many digits for 32 bit number: \'hff_9999_1010_0101_1010\n    in_fifo <= \'hff_9999_1010_0101_1010;\n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:160: Too many digits for 32 bit number: \'h00_0101_1010_0101_1010\n    in_fifo <= \'h00_0101_1010_0101_1010;   \n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:163: Too many digits for 32 bit number: \'h00_ABCD_AAAA_CAFE_0000\n   in_fifo <= \'h00_ABCD_AAAA_CAFE_0000;    \n              ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:166: Too many digits for 32 bit number: \'hff_0101_1010_0101_9999\n    in_fifo <= \'hff_0101_1010_0101_9999;\n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/Fifo_mem.v:172: Too many digits for 32 bit number: \'hff_0101_1010_0101_9999\n    in_fifo <= \'hff_0101_1010_0101_9999;\n               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifomem_tb(); 


reg clk, rst;
integer count;


reg fiforead, fifowrite;
reg [71:0] in_fifo;
wire [71:0] out_fifo;

wire full;
wire nearly_full;
wire nearly_empty;
wire empty;

fifomem UUT (
				.fiforead(fiforead),
				.fifowrite(fifowrite),

				

				.full(full),
				.nearly_full(nearly_full),
				.nearly_empty(nearly_empty),
				.empty(empty),
				

				.in_fifo(in_fifo),
				.out_fifo(out_fifo),
				

				.clk(clk),
				.rst(rst)
				);
initial begin
fiforead = 'h0;
fifowrite = 'h0;
in_fifo = 'h0;
count = 0;
clk = 0;
rst = 1;
#10
rst = 0;

forever #10 clk = ~clk; 
end

always @(posedge clk)
begin
		if (count < 1)
			begin
				fiforead = 'h1;
				fifowrite = 'h1;
				in_fifo <= 'hff_9999_1010_0101_1010;
			end
		else if (count < 2)
			begin
				in_fifo <= 'h00_0101_1010_0101_1010;			
			end
		else if (count < 4)
			begin
				fiforead <= 'h0;
				in_fifo <= 'h00_ABCD_AAAA_CAFE_0000;	
			end
		else if (count < 6)
			begin
				in_fifo <= 'hff_0101_1010_0101_9999;			
			end
		else if (count < 11)
			begin
				fiforead <= 'h1;
				fifowrite <= 'h0;
				in_fifo <= 'hff_9999_1010_0101_1010;
			end
		else if (count < 12)
			begin
				in_fifo <= 'h00_0101_1010_0101_1010;			
			end
		else if (count < 13)
			in_fifo <= 'h00_ABCD_AAAA_CAFE_0000;				
		else if (count < 14)
			begin
				in_fifo <= 'hff_0101_1010_0101_9999;
			end
		else if (count < 15)
			begin
				fiforead <= 'h0;
				fifowrite <= 'h1;
				in_fifo <= 'hff_0101_1010_0101_9999;
			end
		
count <= count + 1;
end

endmodule
module fifomem_tb();
 


reg clk, rst;
integer count;


reg fiforead, fifowrite;
reg [71:0] in_fifo;
wire [71:0] out_fifo;

wire full;
wire nearly_full;
wire nearly_empty;
wire empty;

fifomem UUT (
				.fiforead(fiforead),
				.fifowrite(fifowrite),

				

				.full(full),
				.nearly_full(nearly_full),
				.nearly_empty(nearly_empty),
				.empty(empty),
				

				.in_fifo(in_fifo),
				.out_fifo(out_fifo),
				

				.clk(clk),
				.rst(rst)
				);
initial begin
fiforead = 'h0;
fifowrite = 'h0;
in_fifo = 'h0;
count = 0;
clk = 0;
rst = 1;
#10
rst = 0;

forever #10 clk = ~clk; 
end

always @(posedge clk)
begin
		if (count < 1)
			begin
				fiforead = 'h1;
				fifowrite = 'h1;
				in_fifo <= 'hff_9999_1010_0101_1010;
			end
		else if (count < 2)
			begin
				in_fifo <= 'h00_0101_1010_0101_1010;			
			end
		else if (count < 4)
			begin
				fiforead <= 'h0;
				in_fifo <= 'h00_ABCD_AAAA_CAFE_0000;	
			end
		else if (count < 6)
			begin
				in_fifo <= 'hff_0101_1010_0101_9999;			
			end
		else if (count < 11)
			begin
				fiforead <= 'h1;
				fifowrite <= 'h0;
				in_fifo <= 'hff_9999_1010_0101_1010;
			end
		else if (count < 12)
			begin
				in_fifo <= 'h00_0101_1010_0101_1010;			
			end
		else if (count < 13)
			in_fifo <= 'h00_ABCD_AAAA_CAFE_0000;				
		else if (count < 14)
			begin
				in_fifo <= 'hff_0101_1010_0101_9999;
			end
		else if (count < 15)
			begin
				fiforead <= 'h0;
				fifowrite <= 'h1;
				in_fifo <= 'hff_0101_1010_0101_9999;
			end
		
count <= count + 1;
end

endmodule