data/full_repos/permissive/178052224/Tarea8/probador.v
 line:82: before: "("
1: b'%Error: data/full_repos/permissive/178052224/Tarea8/probador.v:9: Cannot find include file: checker_gray.v\n`include "checker_gray.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/178052224/Tarea8,data/full_repos/permissive/178052224/checker_gray.v\n             data/full_repos/permissive/178052224/Tarea8,data/full_repos/permissive/178052224/checker_gray.v.v\n             data/full_repos/permissive/178052224/Tarea8,data/full_repos/permissive/178052224/checker_gray.v.sv\n             checker_gray.v\n             checker_gray.v.v\n             checker_gray.v.sv\n             obj_dir/checker_gray.v\n             obj_dir/checker_gray.v.v\n             obj_dir/checker_gray.v.sv\n%Error: data/full_repos/permissive/178052224/Tarea8/probador.v:33: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("contador_gray.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea8/probador.v:34: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea8/probador.v:40: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/178052224/Tarea8/probador.v:50: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/178052224/Tarea8/probador.v:55: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/178052224/Tarea8/probador.v:60: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/178052224/Tarea8/probador.v:65: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea8/probador.v:77: Unsupported: Ignoring delay on this delayed statement.\n    always #2 clk <=~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module probador(
    output reg          clk,
    output reg          enable,
    output reg          reset_L,
    input       [4:0]   salida_gray_cond,
    input       [4:0]   salida_gray_estruct);



    wire		gray_checks_out;


   checker_gray gray_check(

			   .gray_checks_out	(gray_checks_out),

			   .clk			(clk),
			   .reset_L		(reset_L),
			   .salida_gray_c	(salida_gray_cond[4:0]),
			   .salida_gray_e	(salida_gray_estruct[4:0]));

    initial begin
        $dumpfile("contador_gray.vcd");
        $dumpvars;
        

        enable <= 0;
        
        repeat(2) begin
        @(posedge clk);
        reset_L <= 0;

        end


        enable <= 1;
        reset_L <= 1;
        
        repeat(596) begin
        @(posedge clk);

        end

        repeat(4) begin
        @(posedge clk);

        end

        repeat(2) begin
        @(posedge clk);
        enable <= 0;
        end

        repeat(2) begin
        @(posedge clk);
        reset_L <= 0;
        end   

        $finish;    
   end

    initial begin
    clk <=0;

    end

    always #2 clk <=~clk;


endmodule
module probador(
    output reg          clk,
    output reg          enable,
    output reg          reset_L,
    input       [4:0]   salida_gray_cond,
    input       [4:0]   salida_gray_estruct);




    wire		gray_checks_out;


   checker_gray gray_check(

			   .gray_checks_out	(gray_checks_out),

			   .clk			(clk),
			   .reset_L		(reset_L),
			   .salida_gray_c	(salida_gray_cond[4:0]),
			   .salida_gray_e	(salida_gray_estruct[4:0]));

    initial begin
        $dumpfile("contador_gray.vcd");
        $dumpvars;
        

        enable <= 0;
        
        repeat(2) begin
        @(posedge clk);
        reset_L <= 0;

        end


        enable <= 1;
        reset_L <= 1;
        
        repeat(596) begin
        @(posedge clk);

        end

        repeat(4) begin
        @(posedge clk);

        end

        repeat(2) begin
        @(posedge clk);
        enable <= 0;
        end

        repeat(2) begin
        @(posedge clk);
        reset_L <= 0;
        end   

        $finish;    
   end

    initial begin
    clk <=0;

    end

    always #2 clk <=~clk;


endmodule