data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:86: Multiple top level modules\n                                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                     : ... Top module \'b2_mux_2_1_case\'\nmodule b2_mux_2_1_case\n       ^~~~~~~~~~~~~~~\n                                                                                                     : ... Top module \'lab4\'\nmodule lab4\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n                                                                                                 : ... In instance lab4.b2_mux_2_1_comb_incorrect\n    assign y = (sel & d1) | ((~sel) & d0);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator NOT expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n                                                                                                 : ... In instance lab4.b2_mux_2_1_comb_incorrect\n    assign y = (sel & d1) | ((~sel) & d0);\n                              ^\n%Error: Exiting due to 3 warning(s)\n'
module lab4
(
    input   [ 1:0]  KEY,
    input   [ 9:0]  SW,
    output  [ 9:0]  LEDR
);

	b2_mux_2_1_sel b2_mux_2_1_sel(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[1:0]));
	b2_mux_2_1_if b2_mux_2_1_if(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[3:2]));
	b2_mux_2_1_comb_correct1 b2_mux_2_1_comb_correct1(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[5:4]));
	b2_mux_2_1_comb_correct2 b2_mux_2_1_comb_correct2(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[7:6]));
	b2_mux_2_1_comb_incorrect b2_mux_2_1_comb_incorrect(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[9:8]));
	
endmodule
module lab4
(
    input   [ 1:0]  KEY,
    input   [ 9:0]  SW,
    output  [ 9:0]  LEDR
);


	b2_mux_2_1_sel b2_mux_2_1_sel(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[1:0]));
	b2_mux_2_1_if b2_mux_2_1_if(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[3:2]));
	b2_mux_2_1_comb_correct1 b2_mux_2_1_comb_correct1(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[5:4]));
	b2_mux_2_1_comb_correct2 b2_mux_2_1_comb_correct2(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[7:6]));
	b2_mux_2_1_comb_incorrect b2_mux_2_1_comb_incorrect(.d0(SW[1:0]),.d1(SW[3:2]),.sel(KEY[0]),.y(LEDR[9:8]));
	
endmodule