data/full_repos/permissive/195227969/work/cold_store/abandoned_m_inputmux.v
 line:501: before: "="
1: b"%Error: data/full_repos/permissive/195227969/work/cold_store/abandoned_m_inputmux.v:501: syntax error, unexpected '=', expecting ',' or ';'\n               genvar k = 0;\n                        ^\n%Error: Exiting due to 1 error(s)\n"
module m_inputmux_lowlevel
  # ( parameter MULDIV = 1,
      DAT_I_ZERO_WHEN_INACTIVE = 0,
      IWIDTH = 8,
      SRAMADRWIDTH = 0,
      MTIMETAP = 32,
      MTIMETAP_LOWLIM = 32
      )
   (
    input              clk,
    input [31:0]       DAT_O,
    input [IWIDTH-1:0] DAT_I,
    input [31:0]       Dsram,
    input [31:0]       ADR_O,
    input              sra_msb,
    input              sa00,
    input              STB_O,
    input              sram_ack,
    input              mie,
    input              mpie,
    input              meie,
    input              mrinstretie,
    input              msie,
    input              mtie,
    input              mtimeincie,
    input              mrinstretip,
    input              msip,
    input              mtip,
    input              mtimeincip,
    input              meip,
    input              qACK,
    input              corerunning,

    input [31:0]       MULDIVREG,
    input              clrM,
    input              ceM,

    
    output             sysregack,
    output [31:0]      Di,
    output [31:0]      rDee,
    output [31:0]      theio
    );
   wire [31:0]         shADR_O = {sra_msb,ADR_O[31:1]};
   wire [32:0]         zeros = 33'h0;
   

   generate







      wire             cmb_sa00mod;
      wire             sa00mod;
      SB_LUT4 #(.LUT_INIT(16'h0100)) inst_presa00mod( .O(cmb_sa00mod), .I3(corerunning), .I2(sram_ack), .I1(qACK), .I0(sa00)); 
      SB_DFF sa00mod_r( .Q(sa00mod), .C(clk), .D(cmb_sa00mod));
      SB_LUT4 #(.LUT_INIT(16'hf0ca)) cmb [31:0] (.O(Di),.I3(sa00mod),.I2(DAT_O),.I1(rDee),.I0(shADR_O));
      
      

      if ( IWIDTH == 32 )
        assign theio = DAT_I[IWIDTH-1:0];
      else
        assign theio = {zeros[31:IWIDTH],DAT_I};
      
      if ( MTIMETAP < MTIMETAP_LOWLIM ) begin
         assign sysregack = 1'b0;
         wire [31:0] cDee;
         
         if ( SRAMADRWIDTH == 0 ) begin
            if ( MULDIV == 0 ) begin

               SB_LUT4 #(.LUT_INIT(16'haaaa)) l_cDee [31:0] (.O(cDee), .I3(1'b0), .I2(1'b0), .I1(1'b0), .I0(theio));
            end else begin

               SB_LUT4 #(.LUT_INIT(16'hcaca)) l_cDee [31:0] (.O(cDee), .I3(1'b0), .I2(STB_O), .I1(theio), .I0(MULDIVREG));
            end
         end else begin
            if ( MULDIV == 0 ) begin

               SB_LUT4 #(.LUT_INIT(16'hcaca)) l_cDee [31:0] (.O(cDee), .I3(1'b0), .I2(STB_O), .I1(theio), .I0(Dsram));
            end else begin
               wire STB_O_or_ReadM;
               SB_LUT4 #(.LUT_INIT(16'hf8f8)) l_STB_O_or_ReadM( .O(STB_O_or_ReadM), .I3(1'b0), .I2(STB_O), .I1(clrM), .I0(ceM));
               
               if ( DAT_I_ZERO_WHEN_INACTIVE == 1 ) begin

                  SB_LUT4 #(.LUT_INIT(16'hfcaa)) l_cDee [31:0] (.O(cDee), .I3(STB_O_or_ReadM), .I2(theio), .I1(MULDIVREG), .I0(Dsram));
               end else begin

                  wire [31:0] mux_i_mul;
                  SB_LUT4 #(.LUT_INIT(16'hcaca)) l_mux_i_mul [31:0] (.O(mux_i_mul), .I3(1'b0), .I2(STB_O),          .I1(theio),     .I0(MULDIVREG));
                  SB_LUT4 #(.LUT_INIT(16'hcaca)) l_cDee [31:0]      (.O(cDee),      .I3(1'b0), .I2(STB_O_or_ReadM), .I1(mux_i_mul), .I0(Dsram));
               end
            end
         end
         SB_DFFE r_rDee [31:0] (.Q(rDee), .C(clk), .E(corerunning), .D(cDee) );

      end else begin

         SB_LUT4 #(.LUT_INIT(16'he000)) l_sysregack( .O(sysregack), .I3(STB_O), .I2(ADR_O[29]), .I1(ADR_O[28]), .I0(ADR_O[27]) );
         
         if ( SRAMADRWIDTH == 0 ) begin
            if ( MULDIV == 0 ) begin

               morework NotImplemented();
            end else begin

               morework NotImplemented();
            end 
         end else begin
            if ( MULDIV == 0 ) begin


               wire [31:0] cDee;
               wire   adrok;
               SB_LUT4 #(.LUT_INIT(16'h1000)) l_adrok( .O(adrok), .I3(ADR_O[30]), .I2(ADR_O[29]),   .I1(ADR_O[28]), .I0(ADR_O[27]));
               genvar k = 0;
               
               for ( k = 0; k < 32; k = k + 1 ) begin
                  if ( k == 3 ) begin



                     wire k3a,k3b;
                     SB_LUT4 #(.LUT_INIT(16'h00ac)) l_k3a( .O(k3a), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(DAT_I[3]), .I0(msip));
                     SB_LUT4 #(.LUT_INIT(16'hac00)) l_k3b( .O(k3b), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(msie),     .I0(mie));
                     SB_LUT4 #(.LUT_INIT(16'hfcaa)) l_cDee3( .O(cDee[3]), .I3(STB_O), .I2(k3a), .I1(k3b), .I0(Dsram[3]));                  
                  end else if ( k == 7 ) begin



                     wire k7a,k7b;
                     SB_LUT4 #(.LUT_INIT(16'h00ac)) l_k7a( .O(k7a), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(DAT_I[7]), .I0(mtip));
                     SB_LUT4 #(.LUT_INIT(16'hac00)) l_k7b( .O(k7b), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(mtie),     .I0(mpie));
                     SB_LUT4 #(.LUT_INIT(16'hfcaa)) l_cDee7( .O(cDee[7]), .I3(STB_O), .I2(k7a), .I1(k7b), .I0(Dsram[7]));                  
                  end else if ( k == 11 ) begin



                     wire k11a,k11b;
                     SB_LUT4 #(.LUT_INIT(16'h00ac)) l_k11a( .O(k11a), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(DAT_I[11]), .I0(meip));
                     SB_LUT4 #(.LUT_INIT(16'hac00)) l_k11b( .O(k11b), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(meie),      .I0(1'b1));
                     SB_LUT4 #(.LUT_INIT(16'hfcaa)) l_cDee11( .O(cDee[11]), .I3(STB_O), .I2(k11a), .I1(k11b), .I0(Dsram[11]));                  
                  end else if ( k == 12 ) begin


                     wire k12;
                     SB_LUT4 #(.LUT_INIT(16'hc2c2)) l_k12( .O(k12), .I3(1'b0), .I2(ADR_O[28]), .I1(ADR_O[27]), .I0(DAT_I[12]));
                     SB_LUT4 #(.LUT_INIT(16'hcaca)) l_cDee12( .O(cDee[12]), .I3(1'b0), .I2(STB_O), .I1(k12), .I0(Dsram[12]));                  
                  end else if ( k == 16 ) begin



                     wire k16a,k16b;
                     SB_LUT4 #(.LUT_INIT(16'h00ac)) l_k16a( .O(k16a), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(DAT_I[16]), .I0(mtimeincip));
                     SB_LUT4 #(.LUT_INIT(16'hac00)) l_k16b( .O(k16b), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(mtimeincie),.I0(1'b0));
                     SB_LUT4 #(.LUT_INIT(16'hfcaa)) l_cDee16( .O(cDee[16]), .I3(STB_O), .I2(k16a), .I1(k16b), .I0(Dsram[16]));                  
                  end else if ( k == 17 ) begin




                     wire k17a,k17b;
                     SB_LUT4 #(.LUT_INIT(16'h00ac)) l_k17a( .O(k17a), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(DAT_I[17]), .I0(mrinstretip));
                     SB_LUT4 #(.LUT_INIT(16'hac00)) l_k17b( .O(k17b), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(mrinstretie),.I0(1'b0));
                     SB_LUT4 #(.LUT_INIT(16'hfcaa)) l_cDee17( .O(cDee[17]), .I3(STB_O), .I2(k17a), .I1(k17b), .I0(Dsram[17]));                  
                  end else begin

                     SB_LUT4 #(.LUT_INIT(16'hc0aa)) l_mux( .O(cDee[k]), .I3(STB_O), .I2(adrok),   .I1(DAT_I[k]), .I0(Dsram[k]));
                  end
               end
               SB_DFFE r_rDee [31:0] (.Q(rDee), .C(clk), .E(corerunning), .D(cDee) );

               
            end else begin
               if ( DAT_I_ZERO_WHEN_INACTIVE == 1 ) begin

               end else begin

               end
            end
         end
      end
   endgenerate
   
endmodule
module m_inputmux_lowlevel
  # ( parameter MULDIV = 1,
      DAT_I_ZERO_WHEN_INACTIVE = 0,
      IWIDTH = 8,
      SRAMADRWIDTH = 0,
      MTIMETAP = 32,
      MTIMETAP_LOWLIM = 32
      )
   (
    input              clk,
    input [31:0]       DAT_O,
    input [IWIDTH-1:0] DAT_I,
    input [31:0]       Dsram,
    input [31:0]       ADR_O,
    input              sra_msb,
    input              sa00,
    input              STB_O,
    input              sram_ack,
    input              mie,
    input              mpie,
    input              meie,
    input              mrinstretie,
    input              msie,
    input              mtie,
    input              mtimeincie,
    input              mrinstretip,
    input              msip,
    input              mtip,
    input              mtimeincip,
    input              meip,
    input              qACK,
    input              corerunning,

    input [31:0]       MULDIVREG,
    input              clrM,
    input              ceM,

    
    output             sysregack,
    output [31:0]      Di,
    output [31:0]      rDee,
    output [31:0]      theio
    );

   wire [31:0]         shADR_O = {sra_msb,ADR_O[31:1]};
   wire [32:0]         zeros = 33'h0;
   

   generate







      wire             cmb_sa00mod;
      wire             sa00mod;
      SB_LUT4 #(.LUT_INIT(16'h0100)) inst_presa00mod( .O(cmb_sa00mod), .I3(corerunning), .I2(sram_ack), .I1(qACK), .I0(sa00)); 
      SB_DFF sa00mod_r( .Q(sa00mod), .C(clk), .D(cmb_sa00mod));
      SB_LUT4 #(.LUT_INIT(16'hf0ca)) cmb [31:0] (.O(Di),.I3(sa00mod),.I2(DAT_O),.I1(rDee),.I0(shADR_O));
      
      

      if ( IWIDTH == 32 )
        assign theio = DAT_I[IWIDTH-1:0];
      else
        assign theio = {zeros[31:IWIDTH],DAT_I};
      
      if ( MTIMETAP < MTIMETAP_LOWLIM ) begin
         assign sysregack = 1'b0;
         wire [31:0] cDee;
         
         if ( SRAMADRWIDTH == 0 ) begin
            if ( MULDIV == 0 ) begin

               SB_LUT4 #(.LUT_INIT(16'haaaa)) l_cDee [31:0] (.O(cDee), .I3(1'b0), .I2(1'b0), .I1(1'b0), .I0(theio));
            end else begin

               SB_LUT4 #(.LUT_INIT(16'hcaca)) l_cDee [31:0] (.O(cDee), .I3(1'b0), .I2(STB_O), .I1(theio), .I0(MULDIVREG));
            end
         end else begin
            if ( MULDIV == 0 ) begin

               SB_LUT4 #(.LUT_INIT(16'hcaca)) l_cDee [31:0] (.O(cDee), .I3(1'b0), .I2(STB_O), .I1(theio), .I0(Dsram));
            end else begin
               wire STB_O_or_ReadM;
               SB_LUT4 #(.LUT_INIT(16'hf8f8)) l_STB_O_or_ReadM( .O(STB_O_or_ReadM), .I3(1'b0), .I2(STB_O), .I1(clrM), .I0(ceM));
               
               if ( DAT_I_ZERO_WHEN_INACTIVE == 1 ) begin

                  SB_LUT4 #(.LUT_INIT(16'hfcaa)) l_cDee [31:0] (.O(cDee), .I3(STB_O_or_ReadM), .I2(theio), .I1(MULDIVREG), .I0(Dsram));
               end else begin

                  wire [31:0] mux_i_mul;
                  SB_LUT4 #(.LUT_INIT(16'hcaca)) l_mux_i_mul [31:0] (.O(mux_i_mul), .I3(1'b0), .I2(STB_O),          .I1(theio),     .I0(MULDIVREG));
                  SB_LUT4 #(.LUT_INIT(16'hcaca)) l_cDee [31:0]      (.O(cDee),      .I3(1'b0), .I2(STB_O_or_ReadM), .I1(mux_i_mul), .I0(Dsram));
               end
            end
         end
         SB_DFFE r_rDee [31:0] (.Q(rDee), .C(clk), .E(corerunning), .D(cDee) );

      end else begin

         SB_LUT4 #(.LUT_INIT(16'he000)) l_sysregack( .O(sysregack), .I3(STB_O), .I2(ADR_O[29]), .I1(ADR_O[28]), .I0(ADR_O[27]) );
         
         if ( SRAMADRWIDTH == 0 ) begin
            if ( MULDIV == 0 ) begin

               morework NotImplemented();
            end else begin

               morework NotImplemented();
            end 
         end else begin
            if ( MULDIV == 0 ) begin


               wire [31:0] cDee;
               wire   adrok;
               SB_LUT4 #(.LUT_INIT(16'h1000)) l_adrok( .O(adrok), .I3(ADR_O[30]), .I2(ADR_O[29]),   .I1(ADR_O[28]), .I0(ADR_O[27]));
               genvar k = 0;
               
               for ( k = 0; k < 32; k = k + 1 ) begin
                  if ( k == 3 ) begin



                     wire k3a,k3b;
                     SB_LUT4 #(.LUT_INIT(16'h00ac)) l_k3a( .O(k3a), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(DAT_I[3]), .I0(msip));
                     SB_LUT4 #(.LUT_INIT(16'hac00)) l_k3b( .O(k3b), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(msie),     .I0(mie));
                     SB_LUT4 #(.LUT_INIT(16'hfcaa)) l_cDee3( .O(cDee[3]), .I3(STB_O), .I2(k3a), .I1(k3b), .I0(Dsram[3]));                  
                  end else if ( k == 7 ) begin



                     wire k7a,k7b;
                     SB_LUT4 #(.LUT_INIT(16'h00ac)) l_k7a( .O(k7a), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(DAT_I[7]), .I0(mtip));
                     SB_LUT4 #(.LUT_INIT(16'hac00)) l_k7b( .O(k7b), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(mtie),     .I0(mpie));
                     SB_LUT4 #(.LUT_INIT(16'hfcaa)) l_cDee7( .O(cDee[7]), .I3(STB_O), .I2(k7a), .I1(k7b), .I0(Dsram[7]));                  
                  end else if ( k == 11 ) begin



                     wire k11a,k11b;
                     SB_LUT4 #(.LUT_INIT(16'h00ac)) l_k11a( .O(k11a), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(DAT_I[11]), .I0(meip));
                     SB_LUT4 #(.LUT_INIT(16'hac00)) l_k11b( .O(k11b), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(meie),      .I0(1'b1));
                     SB_LUT4 #(.LUT_INIT(16'hfcaa)) l_cDee11( .O(cDee[11]), .I3(STB_O), .I2(k11a), .I1(k11b), .I0(Dsram[11]));                  
                  end else if ( k == 12 ) begin


                     wire k12;
                     SB_LUT4 #(.LUT_INIT(16'hc2c2)) l_k12( .O(k12), .I3(1'b0), .I2(ADR_O[28]), .I1(ADR_O[27]), .I0(DAT_I[12]));
                     SB_LUT4 #(.LUT_INIT(16'hcaca)) l_cDee12( .O(cDee[12]), .I3(1'b0), .I2(STB_O), .I1(k12), .I0(Dsram[12]));                  
                  end else if ( k == 16 ) begin



                     wire k16a,k16b;
                     SB_LUT4 #(.LUT_INIT(16'h00ac)) l_k16a( .O(k16a), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(DAT_I[16]), .I0(mtimeincip));
                     SB_LUT4 #(.LUT_INIT(16'hac00)) l_k16b( .O(k16b), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(mtimeincie),.I0(1'b0));
                     SB_LUT4 #(.LUT_INIT(16'hfcaa)) l_cDee16( .O(cDee[16]), .I3(STB_O), .I2(k16a), .I1(k16b), .I0(Dsram[16]));                  
                  end else if ( k == 17 ) begin




                     wire k17a,k17b;
                     SB_LUT4 #(.LUT_INIT(16'h00ac)) l_k17a( .O(k17a), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(DAT_I[17]), .I0(mrinstretip));
                     SB_LUT4 #(.LUT_INIT(16'hac00)) l_k17b( .O(k17b), .I3(ADR_O[28]), .I2(ADR_O[27]), .I1(mrinstretie),.I0(1'b0));
                     SB_LUT4 #(.LUT_INIT(16'hfcaa)) l_cDee17( .O(cDee[17]), .I3(STB_O), .I2(k17a), .I1(k17b), .I0(Dsram[17]));                  
                  end else begin

                     SB_LUT4 #(.LUT_INIT(16'hc0aa)) l_mux( .O(cDee[k]), .I3(STB_O), .I2(adrok),   .I1(DAT_I[k]), .I0(Dsram[k]));
                  end
               end
               SB_DFFE r_rDee [31:0] (.Q(rDee), .C(clk), .E(corerunning), .D(cDee) );

               
            end else begin
               if ( DAT_I_ZERO_WHEN_INACTIVE == 1 ) begin

               end else begin

               end
            end
         end
      end
   endgenerate
   
endmodule