data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v
 line:16: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n  always #3.5 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:17: syntax error, unexpected \'@\'\n repeat(1) @(posedge clk);\n           ^\n%Error: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:19: syntax error, unexpected \'@\'\n repeat(1) @(posedge clk);\n           ^\n%Error: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:21: syntax error, unexpected \'@\'\n repeat(4) @(posedge clk);\n           ^\n%Error: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:23: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n   #1 in=1\'b1;\n   ^\n%Error: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:28: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #1 in=1\'b0;\n    ^\n%Error: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:32: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #1 in=1\'b1;\n    ^\n%Error: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:37: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n   #1 in=1\'b1;\n   ^\n%Error: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:41: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n   #1 in=1\'b0;\n   ^\n%Error: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:46: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #1 in=1\'b1;\n    ^\n%Error: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:50: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #1 in=1\'b0;\n    ^\n%Error: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:55: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/214278225/3_stateMachine/debounce/debounce_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n   #1 in=1\'b0;\n   ^\n%Error: Exiting due to 11 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module debounce_tb;
  reg clk,rst,in;
  wire out;

  always #3.5 clk = ~clk;

  debounce DUT(in, clk, out, rst);

initial begin
	$display("Simulation Begins...");
	initialize;
	repeat(1) @(posedge clk);
	rst <= 1;
	repeat(1) @(posedge clk);
	rst <= 0;
	repeat(4) @(posedge clk);
	repeat(10) begin
	  @(posedge clk);
	  #1 in=1'b1;
	end
	repeat(50) begin
		repeat(2) begin
		  @(posedge clk);
		  #1 in=1'b0;
		end
		repeat(2) begin
		  @(posedge clk);
		  #1 in=1'b1;
		end
	end
	repeat(100) begin
	  @(posedge clk);
	  #1 in=1'b1;
	end
	repeat(10) begin
	  @(posedge clk);
	  #1 in=1'b0;
	end
		repeat(50) begin
		repeat(2) begin
		  @(posedge clk);
		  #1 in=1'b1;
		end
		repeat(2) begin
		  @(posedge clk);
		  #1 in=1'b0;
		end
	end
	repeat(100) begin
	  @(posedge clk);
	  #1 in=1'b0;
	end
	$finish;
end

task initialize;
begin
		clk = 0;
		rst = 0;
		in = 0;
end
endtask

endmodule
module debounce_tb;

  reg clk,rst,in;
  wire out;

  always #3.5 clk = ~clk;

  debounce DUT(in, clk, out, rst);

initial begin
	$display("Simulation Begins...");
	initialize;
	repeat(1) @(posedge clk);
	rst <= 1;
	repeat(1) @(posedge clk);
	rst <= 0;
	repeat(4) @(posedge clk);
	repeat(10) begin
	  @(posedge clk);
	  #1 in=1'b1;
	end
	repeat(50) begin
		repeat(2) begin
		  @(posedge clk);
		  #1 in=1'b0;
		end
		repeat(2) begin
		  @(posedge clk);
		  #1 in=1'b1;
		end
	end
	repeat(100) begin
	  @(posedge clk);
	  #1 in=1'b1;
	end
	repeat(10) begin
	  @(posedge clk);
	  #1 in=1'b0;
	end
		repeat(50) begin
		repeat(2) begin
		  @(posedge clk);
		  #1 in=1'b1;
		end
		repeat(2) begin
		  @(posedge clk);
		  #1 in=1'b0;
		end
	end
	repeat(100) begin
	  @(posedge clk);
	  #1 in=1'b0;
	end
	$finish;
end

task initialize;
begin
		clk = 0;
		rst = 0;
		in = 0;
end
endtask

endmodule