data/full_repos/permissive/123690745/MicroSystem.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123690745/MicroSystem.v:58: Unsupported: Ignoring delay on this delayed statement.\n   always #(500/160) clk = ~clk;   \n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123690745/MicroSystem.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/123690745/MicroSystem.v:35: Cannot find file containing module: \'Bridge\'\n Bridge Bridge (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/Bridge\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/Bridge.v\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/Bridge.sv\n             Bridge\n             Bridge.v\n             Bridge.sv\n             obj_dir/Bridge\n             obj_dir/Bridge.v\n             obj_dir/Bridge.sv\n%Error: data/full_repos/permissive/123690745/MicroSystem.v:42: Cannot find file containing module: \'mips\'\n mips uut (\n ^~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MicroSystem;


	reg clk;
	reg reset;
	
	reg MemWriteM;
	reg CPUAddress;


	Bridge Bridge (
		.MemWriteM(MemWriteM), 
		.CPUAddress(CPUAddress)
	);



	mips uut (
		.clk(clk),
		.reset(reset)
	);

	initial begin

		clk = 0;
		reset = 0;






	end
   always #(500/160) clk = ~clk;   
	initial begin

		MemWriteM = 0;
		CPUAddress = 0;


		#100;
        


	end
      
endmodule
module MicroSystem;



	reg clk;
	reg reset;
	
	reg MemWriteM;
	reg CPUAddress;


	Bridge Bridge (
		.MemWriteM(MemWriteM), 
		.CPUAddress(CPUAddress)
	);



	mips uut (
		.clk(clk),
		.reset(reset)
	);

	initial begin

		clk = 0;
		reset = 0;






	end
   always #(500/160) clk = ~clk;   
	initial begin

		MemWriteM = 0;
		CPUAddress = 0;


		#100;
        


	end
      
endmodule