data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl/hex_driver.v
1: b"%Error: data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl/hex_driver.v:46: Cannot find file containing module: 'clock_divider'\n    clock_divider #(100000) cd1(.clk_in(CLK_50MHZ), .clk_out(sc_circuit_clk));\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl,data/full_repos/permissive/168456532/clock_divider\n             data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl,data/full_repos/permissive/168456532/clock_divider.v\n             data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl,data/full_repos/permissive/168456532/clock_divider.sv\n             clock_divider\n             clock_divider.v\n             clock_divider.sv\n             obj_dir/clock_divider\n             obj_dir/clock_divider.v\n             obj_dir/clock_divider.sv\n%Error: data/full_repos/permissive/168456532/FPGA_Pong.srcs/sources_1/imports/hdl/hex_driver.v:48: Cannot find file containing module: 'scan_control'\n    scan_control sc_circuit(.seg(seg), .an(an), .tho_seg(tho_seg), .hun_seg(hun_seg), .ten_seg(ten_seg), .lsb_seg(lsb_seg), .clk(sc_circuit_clk));\n    ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module hex_driver(output [6:0] seg, output [3:0] an, input [3:0] tho_dig, input [3:0] hun_dig, input [3:0] ten_dig, input [3:0] lsb_dig, input CLK_50MHZ);
    wire [6:0] tho_seg, hun_seg, ten_seg, lsb_seg;
    wire sc_circuit_clk;

    BCDToLED btl_lsb(.seg(lsb_seg), .x(lsb_dig));
    BCDToLED btl_ten(.seg(ten_seg), .x(ten_dig));
    BCDToLED btl_hun(.seg(hun_seg), .x(hun_dig));
    BCDToLED btl_tho(.seg(tho_seg), .x(tho_dig));

    clock_divider #(100000) cd1(.clk_in(CLK_50MHZ), .clk_out(sc_circuit_clk));

    scan_control sc_circuit(.seg(seg), .an(an), .tho_seg(tho_seg), .hun_seg(hun_seg), .ten_seg(ten_seg), .lsb_seg(lsb_seg), .clk(sc_circuit_clk));
endmodule
module hex_driver(output [6:0] seg, output [3:0] an, input [3:0] tho_dig, input [3:0] hun_dig, input [3:0] ten_dig, input [3:0] lsb_dig, input CLK_50MHZ);

    wire [6:0] tho_seg, hun_seg, ten_seg, lsb_seg;
    wire sc_circuit_clk;

    BCDToLED btl_lsb(.seg(lsb_seg), .x(lsb_dig));
    BCDToLED btl_ten(.seg(ten_seg), .x(ten_dig));
    BCDToLED btl_hun(.seg(hun_seg), .x(hun_dig));
    BCDToLED btl_tho(.seg(tho_seg), .x(tho_dig));

    clock_divider #(100000) cd1(.clk_in(CLK_50MHZ), .clk_out(sc_circuit_clk));

    scan_control sc_circuit(.seg(seg), .an(an), .tho_seg(tho_seg), .hun_seg(hun_seg), .ten_seg(ten_seg), .lsb_seg(lsb_seg), .clk(sc_circuit_clk));
endmodule