data/full_repos/permissive/173150157/rtl/test/tmds_encoder_dvi_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/tmds_encoder_dvi_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/tmds_encoder_dvi_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/tmds_encoder_dvi_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n       #5 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/173150157/rtl/test/tmds_encoder_dvi_tb.v:34: Cannot find file containing module: \'tmds_encoder_dvi\'\n    tmds_encoder_dvi tmds_test (\n    ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173150157/rtl/test,data/full_repos/permissive/173150157/tmds_encoder_dvi\n             data/full_repos/permissive/173150157/rtl/test,data/full_repos/permissive/173150157/tmds_encoder_dvi.v\n             data/full_repos/permissive/173150157/rtl/test,data/full_repos/permissive/173150157/tmds_encoder_dvi.sv\n             tmds_encoder_dvi\n             tmds_encoder_dvi.v\n             tmds_encoder_dvi.sv\n             obj_dir/tmds_encoder_dvi\n             obj_dir/tmds_encoder_dvi.v\n             obj_dir/tmds_encoder_dvi.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tmds_encode_dvi_tb();

    reg rst;
    reg clk;

    reg [7:0] data;
    reg [1:0] ctrl;
    reg de;
    wire [9:0] tmds;
    reg [8:0] cycle;


    initial begin
        $display("\t               1s    B   O");
        clk = 1;
        rst = 1;
        de = 0;
        ctrl = 2'b00;

        #10
        rst = 0;

        #10
        de = 1;
    end

    tmds_encoder_dvi tmds_test (
        .i_clk(clk),
        .i_rst(rst),
        .i_data(data),
        .i_ctrl(ctrl),
        .i_de(de),
        .o_tmds(tmds)
    );

    always @ (posedge clk or posedge rst)
    begin
        if (rst)
        begin
            cycle <= 0;
            data <= 0;
        end
        else
        begin
            cycle <= cycle + 1;
            data <= cycle[7:0];
        end
    end

    always
       #5 clk = ~clk;

endmodule
module tmds_encode_dvi_tb();


    reg rst;
    reg clk;

    reg [7:0] data;
    reg [1:0] ctrl;
    reg de;
    wire [9:0] tmds;
    reg [8:0] cycle;


    initial begin
        $display("\t               1s    B   O");
        clk = 1;
        rst = 1;
        de = 0;
        ctrl = 2'b00;

        #10
        rst = 0;

        #10
        de = 1;
    end

    tmds_encoder_dvi tmds_test (
        .i_clk(clk),
        .i_rst(rst),
        .i_data(data),
        .i_ctrl(ctrl),
        .i_de(de),
        .o_tmds(tmds)
    );

    always @ (posedge clk or posedge rst)
    begin
        if (rst)
        begin
            cycle <= 0;
            data <= 0;
        end
        else
        begin
            cycle <= cycle + 1;
            data <= cycle[7:0];
        end
    end

    always
       #5 clk = ~clk;

endmodule