data/full_repos/permissive/189567834/DD_FIR/DD_FIR.srcs/sources_1/imports/vivado_demo/code/fp16_align.v
data/verilator_xmls/516786f4-88d5-44aa-9755-7c80d719e7f9.xml
module fadd_align (a,b,sub,sign,temp_exp,op_sub,large_frac11,small_frac14);	
	input[15:0] a, b;
	input sub;
	output sign;
	output[4:0] temp_exp;
	output op_sub;
	output[10:0] large_frac11;
	output[13:0] small_frac14;


	wire exchange = (b[14:0] > a[14:0]);
	wire [15:0] fp_large = exchange? b : a;
	wire [15:0] fp_small = exchange? a : b;


	wire fp_large_hidden_bit = |fp_large[14:10];
	wire fp_small_hidden_bit = |fp_small[14:10];
	wire [10:0] large_frac11 = {fp_large_hidden_bit, fp_large[9:0]};
	wire [10:0] small_frac11 = {fp_small_hidden_bit, fp_small[9:0]};


	assign temp_exp = fp_large[14:10];


	assign sign = exchange ? sub^b[15] : a[15];


	assign op_sub = sub ^ fp_large[15] ^ fp_small[15];


	wire[4:0] exp_diff = fp_large[14:10] - fp_small[14:10];


	wire[23:0] small_frac25 = (exp_diff >= 13) ? 
								{13'h0, small_frac11} : 
								{small_frac11, 13'h0} >> exp_diff;


	assign small_frac14 = {small_frac25[23:11], |small_frac25[10:0]};
endmodule
module fadd_align (a,b,sub,sign,temp_exp,op_sub,large_frac11,small_frac14);
	
	input[15:0] a, b;
	input sub;
	output sign;
	output[4:0] temp_exp;
	output op_sub;
	output[10:0] large_frac11;
	output[13:0] small_frac14;


	wire exchange = (b[14:0] > a[14:0]);
	wire [15:0] fp_large = exchange? b : a;
	wire [15:0] fp_small = exchange? a : b;


	wire fp_large_hidden_bit = |fp_large[14:10];
	wire fp_small_hidden_bit = |fp_small[14:10];
	wire [10:0] large_frac11 = {fp_large_hidden_bit, fp_large[9:0]};
	wire [10:0] small_frac11 = {fp_small_hidden_bit, fp_small[9:0]};


	assign temp_exp = fp_large[14:10];


	assign sign = exchange ? sub^b[15] : a[15];


	assign op_sub = sub ^ fp_large[15] ^ fp_small[15];


	wire[4:0] exp_diff = fp_large[14:10] - fp_small[14:10];


	wire[23:0] small_frac25 = (exp_diff >= 13) ? 
								{13'h0, small_frac11} : 
								{small_frac11, 13'h0} >> exp_diff;


	assign small_frac14 = {small_frac25[23:11], |small_frac25[10:0]};
endmodule