data/full_repos/permissive/122271920/hdl/Nu6509.v
1: b'%Warning-WIDTH: data/full_repos/permissive/122271920/hdl/Nu6509.v:76: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'_so\' generates 1 bits.\n                                                                    : ... In instance Nu6509\nassign mx =                               ((ctr == 7) & !flag_816 ? _so : \'bz);\n                                                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/122271920/hdl/Nu6509.v:76: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                    : ... In instance Nu6509\nassign mx =                               ((ctr == 7) & !flag_816 ? _so : \'bz);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/122271920/hdl/Nu6509.v:77: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'_so\' generates 1 bits.\n                                                                    : ... In instance Nu6509\nassign _abort =                           ((ctr == 7) & flag_816 ? _so : \'bz);\n                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/122271920/hdl/Nu6509.v:77: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                    : ... In instance Nu6509\nassign _abort =                           ((ctr == 7) & flag_816 ? _so : \'bz);\n              ^\n%Error: data/full_repos/permissive/122271920/hdl/Nu6509.v:84: Cannot find file containing module: \'register\'\nregister #(.WIDTH(8), .RESET(4\'b1111))    reg_0000(phi2_6509, !_reset, we_bank & !address_6502[0], data_6502, data_0000);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122271920/hdl,data/full_repos/permissive/122271920/register\n             data/full_repos/permissive/122271920/hdl,data/full_repos/permissive/122271920/register.v\n             data/full_repos/permissive/122271920/hdl,data/full_repos/permissive/122271920/register.sv\n             register\n             register.v\n             register.sv\n             obj_dir/register\n             obj_dir/register.v\n             obj_dir/register.sv\n%Error: data/full_repos/permissive/122271920/hdl/Nu6509.v:86: Cannot find file containing module: \'register\'\nregister #(.WIDTH(8), .RESET(4\'b1111))    reg_0001(phi2_6509, !_reset, we_bank & address_6502[0], data_6502, data_0001);\n^~~~~~~~\n%Error: data/full_repos/permissive/122271920/hdl/Nu6509.v:88: Cannot find file containing module: \'register\'\nregister #(.WIDTH(1))                     reg_opcode(phi2_6509, !_reset, _rdy, sync & data_6502[7] & !data_6502[6] & (data_6502[4:0] == 5\'b10001), flag_opcode);\n^~~~~~~~\n%Error: data/full_repos/permissive/122271920/hdl/Nu6509.v:89: Cannot find file containing module: \'register\'\nregister #(.WIDTH(1))                     reg_clock1(phi2_6509, !_reset, _rdy, address_6502[0], data_cycle1);\n^~~~~~~~\n%Error: data/full_repos/permissive/122271920/hdl/Nu6509.v:91: Cannot find file containing module: \'register\'\nregister #(.WIDTH(1))                     reg_clock2(phi2_6509, !_reset, _rdy, flag_opcode & (data_cycle1 ^ address_6502[0]), data_cycle2);\n^~~~~~~~\n%Error: data/full_repos/permissive/122271920/hdl/Nu6509.v:93: Cannot find file containing module: \'register\'\nregister #(.WIDTH(1))                     reg_clock3(phi2_6509, !_reset, _rdy, data_cycle2, data_cycle3);\n^~~~~~~~\n%Error: data/full_repos/permissive/122271920/hdl/Nu6509.v:95: Cannot find file containing module: \'register\'\nregister #(.WIDTH(1))                     reg_clock4(phi2_6509, !_reset, _rdy, data_cycle3, data_cycle4);\n^~~~~~~~\n%Error: data/full_repos/permissive/122271920/hdl/Nu6509.v:97: Cannot find file containing module: \'register\'\nregister #(.WIDTH(1))                     reg_clock5(phi2_6509, !_reset, _rdy, data_cycle4, data_cycle5); \n^~~~~~~~\n%Error: data/full_repos/permissive/122271920/hdl/Nu6509.v:100: Cannot find file containing module: \'register\'\nregister #(.WIDTH(8))                     reg_bank(!phi2_6509, !_reset, 1, data_6502, data_baddr);\n^~~~~~~~\n%Error: Exiting due to 9 error(s), 4 warning(s)\n'
module Nu6509(input _reset,
              input phi2_6509,
              input r_w,
              input [15:0]address_6502,
              inout [7:0]data_6502,
              inout [7:0]data_6509,
              input _rdy,
              input be,
              input vpa,
              input vda,
              input _so,
              input e,
              output sync,
              output mx,
              output _abort,
              output reg [7:0]address_bank
             );
 


reg [7:0]data_6502_out;
reg [7:0]data_6509_out;
wire [7:0]data_0000;
wire [7:0]data_0001;
wire [7:0]data_bank;
wire [7:0]data_baddr;
wire flag_opcode;
wire data_cycle1;
wire data_cycle2;
wire data_cycle3;
wire data_cycle4;
wire data_cycle5;
wire flag_ext;
wire flag_full;
wire sel_bank;
wire ce_bank;
wire oe_bank;
wire we_bank;
reg flag_816;
reg [2:0]ctr;



assign ce_bank =                          !flag_ext & address_6502[15:1] == 0;
assign we_bank =                          ce_bank & !r_w;
assign oe_bank =                          r_w & ce_bank;

assign sync =                             ((ctr == 7) & flag_816 ? (vpa & vda) : vpa);
assign mx =                               ((ctr == 7) & !flag_816 ? _so : 'bz);
assign _abort =                           ((ctr == 7) & flag_816 ? _so : 'bz);
assign flag_ext =                         flag_816 & !e;
assign data_6509 =                        data_6509_out;
assign data_6502 =                        data_6502_out;



register #(.WIDTH(8), .RESET(4'b1111))    reg_0000(phi2_6509, !_reset, we_bank & !address_6502[0], data_6502, data_0000);

register #(.WIDTH(8), .RESET(4'b1111))    reg_0001(phi2_6509, !_reset, we_bank & address_6502[0], data_6502, data_0001);

register #(.WIDTH(1))                     reg_opcode(phi2_6509, !_reset, _rdy, sync & data_6502[7] & !data_6502[6] & (data_6502[4:0] == 5'b10001), flag_opcode);
register #(.WIDTH(1))                     reg_clock1(phi2_6509, !_reset, _rdy, address_6502[0], data_cycle1);

register #(.WIDTH(1))                     reg_clock2(phi2_6509, !_reset, _rdy, flag_opcode & (data_cycle1 ^ address_6502[0]), data_cycle2);

register #(.WIDTH(1))                     reg_clock3(phi2_6509, !_reset, _rdy, data_cycle2, data_cycle3);

register #(.WIDTH(1))                     reg_clock4(phi2_6509, !_reset, _rdy, data_cycle3, data_cycle4);

register #(.WIDTH(1))                     reg_clock5(phi2_6509, !_reset, _rdy, data_cycle4, data_cycle5);
assign sel_bank =                         (data_cycle5 & !sync) | data_cycle4;


register #(.WIDTH(8))                     reg_bank(!phi2_6509, !_reset, 1, data_6502, data_baddr);

always @(*)
begin
   case({flag_ext, flag_full, sel_bank})
      3'b000:
         address_bank = {4'b0000,data_0000[3:0]};
      3'b001:
         address_bank = {4'b0000,data_0001[3:0]};
      3'b010:
         address_bank = data_0000;
      3'b011:
         address_bank = data_0001;
      default:
         address_bank = data_baddr;
   endcase
end

assign data_bank = (address_6502[0] ? data_0001 : data_0000);

always @(*)
begin
   if(oe_bank & !flag_full)
      data_6502_out = {4'b0000, data_bank[3:0]};
   else if(oe_bank & flag_full)
      data_6502_out = data_bank;
   else if(r_w & _rdy & phi2_6509)
      data_6502_out = data_6509;
   else
      data_6502_out = 8'bz;
end

always @(*)
begin
   if(!r_w & _rdy & phi2_6509 & be)
      data_6509_out = data_6502;
   else
      data_6509_out = 8'bz;
end

always @(posedge phi2_6509)
begin
   if(ctr < 7)
      ctr <= ctr + 1;
   else if(ctr == 7)
      flag_816 <= e;
end



fsm_flag						                  flag_fsm1(
                                                    we_bank & address_6502[0] & phi2_6509 & !flag_ext, 
                                                    !_reset, 
                                                    data_6502, 
                                                    flag_full
                                                   );

endmodule
module Nu6509(input _reset,
              input phi2_6509,
              input r_w,
              input [15:0]address_6502,
              inout [7:0]data_6502,
              inout [7:0]data_6509,
              input _rdy,
              input be,
              input vpa,
              input vda,
              input _so,
              input e,
              output sync,
              output mx,
              output _abort,
              output reg [7:0]address_bank
             );

 


reg [7:0]data_6502_out;
reg [7:0]data_6509_out;
wire [7:0]data_0000;
wire [7:0]data_0001;
wire [7:0]data_bank;
wire [7:0]data_baddr;
wire flag_opcode;
wire data_cycle1;
wire data_cycle2;
wire data_cycle3;
wire data_cycle4;
wire data_cycle5;
wire flag_ext;
wire flag_full;
wire sel_bank;
wire ce_bank;
wire oe_bank;
wire we_bank;
reg flag_816;
reg [2:0]ctr;



assign ce_bank =                          !flag_ext & address_6502[15:1] == 0;
assign we_bank =                          ce_bank & !r_w;
assign oe_bank =                          r_w & ce_bank;

assign sync =                             ((ctr == 7) & flag_816 ? (vpa & vda) : vpa);
assign mx =                               ((ctr == 7) & !flag_816 ? _so : 'bz);
assign _abort =                           ((ctr == 7) & flag_816 ? _so : 'bz);
assign flag_ext =                         flag_816 & !e;
assign data_6509 =                        data_6509_out;
assign data_6502 =                        data_6502_out;



register #(.WIDTH(8), .RESET(4'b1111))    reg_0000(phi2_6509, !_reset, we_bank & !address_6502[0], data_6502, data_0000);

register #(.WIDTH(8), .RESET(4'b1111))    reg_0001(phi2_6509, !_reset, we_bank & address_6502[0], data_6502, data_0001);

register #(.WIDTH(1))                     reg_opcode(phi2_6509, !_reset, _rdy, sync & data_6502[7] & !data_6502[6] & (data_6502[4:0] == 5'b10001), flag_opcode);
register #(.WIDTH(1))                     reg_clock1(phi2_6509, !_reset, _rdy, address_6502[0], data_cycle1);

register #(.WIDTH(1))                     reg_clock2(phi2_6509, !_reset, _rdy, flag_opcode & (data_cycle1 ^ address_6502[0]), data_cycle2);

register #(.WIDTH(1))                     reg_clock3(phi2_6509, !_reset, _rdy, data_cycle2, data_cycle3);

register #(.WIDTH(1))                     reg_clock4(phi2_6509, !_reset, _rdy, data_cycle3, data_cycle4);

register #(.WIDTH(1))                     reg_clock5(phi2_6509, !_reset, _rdy, data_cycle4, data_cycle5);
assign sel_bank =                         (data_cycle5 & !sync) | data_cycle4;


register #(.WIDTH(8))                     reg_bank(!phi2_6509, !_reset, 1, data_6502, data_baddr);

always @(*)
begin
   case({flag_ext, flag_full, sel_bank})
      3'b000:
         address_bank = {4'b0000,data_0000[3:0]};
      3'b001:
         address_bank = {4'b0000,data_0001[3:0]};
      3'b010:
         address_bank = data_0000;
      3'b011:
         address_bank = data_0001;
      default:
         address_bank = data_baddr;
   endcase
end

assign data_bank = (address_6502[0] ? data_0001 : data_0000);

always @(*)
begin
   if(oe_bank & !flag_full)
      data_6502_out = {4'b0000, data_bank[3:0]};
   else if(oe_bank & flag_full)
      data_6502_out = data_bank;
   else if(r_w & _rdy & phi2_6509)
      data_6502_out = data_6509;
   else
      data_6502_out = 8'bz;
end

always @(*)
begin
   if(!r_w & _rdy & phi2_6509 & be)
      data_6509_out = data_6502;
   else
      data_6509_out = 8'bz;
end

always @(posedge phi2_6509)
begin
   if(ctr < 7)
      ctr <= ctr + 1;
   else if(ctr == 7)
      flag_816 <= e;
end



fsm_flag						                  flag_fsm1(
                                                    we_bank & address_6502[0] & phi2_6509 & !flag_ext, 
                                                    !_reset, 
                                                    data_6502, 
                                                    flag_full
                                                   );

endmodule