data/full_repos/permissive/203650831/hd44780_controller_tb.v
 line:119: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_controller_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = (clk === 1\'b0);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/203650831/hd44780_controller_tb.v:107: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("hd44780_controller_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_controller_tb.v:108: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, hd44780_controller_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_controller_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n        #90 start_addr = 0;             \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_controller_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n        #10 cont_ststart = 1;                    \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_controller_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n        #10 cont_ststart = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_controller_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #20000 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hd44780_controller_tb;











    reg clk = 1;


    always #5 clk = (clk === 1'b0);

    wire wb_reset;
    wire wb_clk;
    hd44780_syscon syscon(
        .i_clk(clk),
        .RST_O(wb_reset),
        .CLK_O(wb_clk)
        );



    parameter address_bits = 8, data_bits = 16;

    reg [address_bits-1:0] start_addr = 0;
    reg [address_bits-1:0] addr_w_reg = 0;

    wire [address_bits-1:0] addr_r_wires;
    reg [data_bits-1:0] data_w_reg = 0;

    wire [data_bits-1:0] data_r_wire;
    reg ram_wen = 0;

    hd44780_ram #(.initfile("settings/ctrlrtest0d.mem"),.filehex(0),.addr_width(address_bits),.data_width(data_bits)) rammy(
        .din(data_w_reg),
        .write_en(ram_wen),
        .waddr(addr_w_reg),
        .wclk(wb_clk),
        .raddr(addr_r_wires),
        .rclk(wb_clk),
        .dout(data_r_wire));



    reg cont_ststart = 0;
    wire cont_busy;
    wire cont_error;
    wire o_rs;
    wire o_e;
    wire [3:0] o_lcd_data;

    hd44780_controller #(.ram_dwidth(16),.ram_awidth(8)) cont (
        .RST_I(wb_reset),
        .CLK_I(wb_clk),
        .STB_I(cont_ststart),


        .o_read_addr_lines(addr_r_wires),
        .i_start_addr(start_addr),
        .i_read_data_lines(data_r_wire),


        .busy(cont_busy),
        .error(cont_error),



        .o_lcd_nybble(o_lcd_data),
        .o_rs(o_rs),
        .o_e(o_e)
    );






    initial begin
        $dumpfile("hd44780_controller_tb.vcd");
        $dumpvars(0, hd44780_controller_tb);
    end

    initial begin


        #90 start_addr = 0;
        #10 cont_ststart = 1;
        #10 cont_ststart = 0;


        #20000 $finish;


    end

endmodule
module hd44780_controller_tb;












    reg clk = 1;


    always #5 clk = (clk === 1'b0);

    wire wb_reset;
    wire wb_clk;
    hd44780_syscon syscon(
        .i_clk(clk),
        .RST_O(wb_reset),
        .CLK_O(wb_clk)
        );



    parameter address_bits = 8, data_bits = 16;

    reg [address_bits-1:0] start_addr = 0;
    reg [address_bits-1:0] addr_w_reg = 0;

    wire [address_bits-1:0] addr_r_wires;
    reg [data_bits-1:0] data_w_reg = 0;

    wire [data_bits-1:0] data_r_wire;
    reg ram_wen = 0;

    hd44780_ram #(.initfile("settings/ctrlrtest0d.mem"),.filehex(0),.addr_width(address_bits),.data_width(data_bits)) rammy(
        .din(data_w_reg),
        .write_en(ram_wen),
        .waddr(addr_w_reg),
        .wclk(wb_clk),
        .raddr(addr_r_wires),
        .rclk(wb_clk),
        .dout(data_r_wire));



    reg cont_ststart = 0;
    wire cont_busy;
    wire cont_error;
    wire o_rs;
    wire o_e;
    wire [3:0] o_lcd_data;

    hd44780_controller #(.ram_dwidth(16),.ram_awidth(8)) cont (
        .RST_I(wb_reset),
        .CLK_I(wb_clk),
        .STB_I(cont_ststart),


        .o_read_addr_lines(addr_r_wires),
        .i_start_addr(start_addr),
        .i_read_data_lines(data_r_wire),


        .busy(cont_busy),
        .error(cont_error),



        .o_lcd_nybble(o_lcd_data),
        .o_rs(o_rs),
        .o_e(o_e)
    );






    initial begin
        $dumpfile("hd44780_controller_tb.vcd");
        $dumpvars(0, hd44780_controller_tb);
    end

    initial begin


        #90 start_addr = 0;
        #10 cont_ststart = 1;
        #10 cont_ststart = 0;


        #20000 $finish;


    end

endmodule