data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/testbench.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/testbench.sv:20: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/testbench.sv:20: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/testbench.sv:11: Cannot find file containing module: \'PPGen_wordslice\'\n PPGen_wordslice dut(Double, Negate, Single, Y, PP0, PP1, PP2, PP3, Sign0, Sign1, Sign2, Sign3);\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester,data/full_repos/permissive/13847835/PPGen_wordslice\n             data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester,data/full_repos/permissive/13847835/PPGen_wordslice.v\n             data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester,data/full_repos/permissive/13847835/PPGen_wordslice.sv\n             PPGen_wordslice\n             PPGen_wordslice.v\n             PPGen_wordslice.sv\n             obj_dir/PPGen_wordslice\n             obj_dir/PPGen_wordslice.v\n             obj_dir/PPGen_wordslice.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
	logic clk;
	logic [3:0] Double, Negate, Single;
	logic [7:0] Y;
	logic Sign3, Sign2, Sign1, Sign0;
	logic [8:0] PP0, PP1, PP2, PP3;
    logic [59:0] vectors[1048576:0], currentvec;
    logic [20:0] vectornum, errors;
    

	PPGen_wordslice dut(Double, Negate, Single, Y, PP0, PP1, PP2, PP3, Sign0, Sign1, Sign2, Sign3);


	initial begin
		$readmemb("output.txt", vectors);
		vectornum = 0; errors = 0;
	end

    always begin
       clk = 1; #10; clk = 0; #10;
    end
      

    always @(posedge clk) begin
       currentvec = vectors[vectornum];
	   Double = currentvec[59:56];
	   Negate = currentvec[55:52];
	   Single = currentvec[51:48];
	   Y = currentvec[47:40];
       if (vectornum === 1048576) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);
         $stop;
       end
    end

    always @(negedge clk) begin
       if (
	   (Sign3 !== currentvec[39] | PP3 !== currentvec[38:30]) |
	   (Sign2 !== currentvec[29] | PP2 !== currentvec[28:20]) |
	   (Sign1 !== currentvec[19] | PP1 !== currentvec[18:10]) |
	   (Sign0 !== currentvec[9] | PP0 !== currentvec[8:0])) begin
          $display("Error: at %b", currentvec[59:40]);
          errors = errors + 1;
       end
       vectornum = vectornum + 1;
    end
endmodule
module testbench();

	logic clk;
	logic [3:0] Double, Negate, Single;
	logic [7:0] Y;
	logic Sign3, Sign2, Sign1, Sign0;
	logic [8:0] PP0, PP1, PP2, PP3;
    logic [59:0] vectors[1048576:0], currentvec;
    logic [20:0] vectornum, errors;
    

	PPGen_wordslice dut(Double, Negate, Single, Y, PP0, PP1, PP2, PP3, Sign0, Sign1, Sign2, Sign3);


	initial begin
		$readmemb("output.txt", vectors);
		vectornum = 0; errors = 0;
	end

    always begin
       clk = 1; #10; clk = 0; #10;
    end
      

    always @(posedge clk) begin
       currentvec = vectors[vectornum];
	   Double = currentvec[59:56];
	   Negate = currentvec[55:52];
	   Single = currentvec[51:48];
	   Y = currentvec[47:40];
       if (vectornum === 1048576) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);
         $stop;
       end
    end

    always @(negedge clk) begin
       if (
	   (Sign3 !== currentvec[39] | PP3 !== currentvec[38:30]) |
	   (Sign2 !== currentvec[29] | PP2 !== currentvec[28:20]) |
	   (Sign1 !== currentvec[19] | PP1 !== currentvec[18:10]) |
	   (Sign0 !== currentvec[9] | PP0 !== currentvec[8:0])) begin
          $display("Error: at %b", currentvec[59:40]);
          errors = errors + 1;
       end
       vectornum = vectornum + 1;
    end
endmodule