data/full_repos/permissive/135008983/code/modulo_counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/135008983/code/modulo_counter.v:27: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'Q\' generates 4 bits.\n                                                                             : ... In instance modulo_counter\n   if (Q == MOD-1) Q <= 4\'b0000;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/135008983/code/modulo_counter.v:32: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'Q\' generates 4 bits.\n                                                                             : ... In instance modulo_counter\nassign Carry_out = (Q == MOD-1); \n                      ^~\n%Error: Exiting due to 2 warning(s)\n'
module modulo_counter(Q, Carry_out, unable, CP, Clear, nRST, En, Store, Status_Value); 
parameter     N =  4; 
parameter   MOD = 16; 
output 					Carry_out; 
output reg 	[N-1:0] 	Q; 
output reg    			unable;
input   				CP, Clear, nRST, En, Store;
input 		[1:0] 		Status_Value;

always @(posedge En or negedge nRST) 
begin
	if(!nRST) unable <= 0;
	else begin
		if (Status_Value == 2'b11) unable <= 0;
		else unable <= 1;
	end
end

always @ (posedge CP or negedge Clear) 
begin
	if(!Clear) Q <= 4'b0000; 
	else if(!unable)begin
		if(En) begin	
			if (Q == MOD-1) Q <= 4'b0000;
			else Q <= Q+1'b1;
		end
	end 
end
assign Carry_out = (Q == MOD-1);	
endmodule
module modulo_counter(Q, Carry_out, unable, CP, Clear, nRST, En, Store, Status_Value);
 
parameter     N =  4; 
parameter   MOD = 16; 
output 					Carry_out; 
output reg 	[N-1:0] 	Q; 
output reg    			unable;
input   				CP, Clear, nRST, En, Store;
input 		[1:0] 		Status_Value;

always @(posedge En or negedge nRST) 
begin
	if(!nRST) unable <= 0;
	else begin
		if (Status_Value == 2'b11) unable <= 0;
		else unable <= 1;
	end
end

always @ (posedge CP or negedge Clear) 
begin
	if(!Clear) Q <= 4'b0000; 
	else if(!unable)begin
		if(En) begin	
			if (Q == MOD-1) Q <= 4'b0000;
			else Q <= Q+1'b1;
		end
	end 
end
assign Carry_out = (Q == MOD-1);	
endmodule