data/full_repos/permissive/115035459/verilog/src/lib/reset.v
 line:43: before: "20"
1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #200; downstream_pll_locked <= 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #1000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #20; downstream_pll_locked <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #100; upstream_reset <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #200; downstream_pll_locked <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:181: Unsupported: Ignoring delay on this delayed statement.\n  #1000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:183: Unsupported: Ignoring delay on this delayed statement.\n  #100; downstream_pll_locked <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:184: Unsupported: Ignoring delay on this delayed statement.\n  #1000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:185: Unsupported: Ignoring delay on this delayed statement.\n  #200; downstream_pll_locked <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:187: Unsupported: Ignoring delay on this delayed statement.\n  #1000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:189: Unsupported: Ignoring delay on this delayed statement.\n  #100; clock_enabled <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:190: Unsupported: Ignoring delay on this delayed statement.\n  #100; downstream_pll_locked <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:191: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #1000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:196: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:53: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                  : ... Top module \'reset3_wait4plls\'\nmodule reset3_wait4plls #(\n       ^~~~~~~~~~~~~~~~\n                                                                                  : ... Top module \'reset_promulgator\'\nmodule reset_promulgator #(\n       ^~~~~~~~~~~~~~~~~\n                                                                                  : ... Top module \'reset_tb\'\nmodule reset_tb();\n       ^~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n                                                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:48: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n                                                                       : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK1_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK1_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset1_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked1_input), .clock_input(clock1_input), .reset_output(reset1_output));\n                                                                                                                               ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n                                                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:49: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n                                                                       : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK2_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK2_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset2_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked2_input), .clock_input(clock2_input), .reset_output(reset2_output));\n                                                                                                                               ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'PLL_LOCKED_PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n                                                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/reset.v:50: Parameter pin not found: \'RESET_PIPELINE_PICKOFF\'\n                                                                       : ... Suggested alternative: \'PIPELINE_PICKOFF\'\n reset_wait4pll #(.COUNTER_BIT_PICKOFF(CLOCK3_BIT_PICKOFF), .PLL_LOCKED_PIPELINE_PICKOFF(PLL_LOCKED_PIPELINE_CLOCK3_PICKOFF), .RESET_PIPELINE_PICKOFF(RESET_PIPELINE_PICKOFF)) reset3_wait4pll (.reset_input(reset_input), .pll_locked_input(pll_locked3_input), .clock_input(clock3_input), .reset_output(reset3_output));\n                                                                                                                               ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reset #(
	parameter FREQUENCY = 10000000.0,
	parameter PLL_LOCK_TIME = 0.05,
	parameter SYNCHRONOUS_ONLY = 1,
	parameter SIGNIFICANT_BIT_NUMBER_B = $clog2(FREQUENCY*PLL_LOCK_TIME) + 1,

	parameter SIGNIFICANT_BIT_NUMBER_A = SIGNIFICANT_BIT_NUMBER_B/4
) (
	input upstream_clock,
	input upstream_reset,
	input downstream_pll_locked,
	output downstream_reset
);
	reg [SIGNIFICANT_BIT_NUMBER_A:0] counterA = 0;
	reg [SIGNIFICANT_BIT_NUMBER_B:0] counterB = 0;
	reg internal_reset_state = 1;
	reg sychronous_reset_source = 1;
	if (SYNCHRONOUS_ONLY) begin


		assign downstream_reset = sychronous_reset_source;
	end else begin
		wire asychronous_reset_source;
		assign asychronous_reset_source = upstream_reset || (counterB[SIGNIFICANT_BIT_NUMBER_B]&&(~downstream_pll_locked));
		assign downstream_reset = asychronous_reset_source || sychronous_reset_source;
	end
	always @(posedge upstream_clock) begin
		if (upstream_reset) begin
			counterA <= 0;
			sychronous_reset_source <= 1;
			counterB <= 0;
			internal_reset_state <= 1;
		end else if (internal_reset_state) begin
			if (counterA[SIGNIFICANT_BIT_NUMBER_A]) begin
				sychronous_reset_source <= 0;
				if (counterB[SIGNIFICANT_BIT_NUMBER_B]) begin
					internal_reset_state <= 0;
				end else begin
					counterB <= counterB + 1'b1;
				end
			end else begin
				counterA <= counterA + 1'b1;
			end
		end else if (~downstream_pll_locked) begin
			counterA <= 0;
			sychronous_reset_source <= 1;
			counterB <= 0;
			internal_reset_state <= 1;
		end
	end
endmodule
module reset #(
	parameter FREQUENCY = 10000000.0,
	parameter PLL_LOCK_TIME = 0.05,
	parameter SYNCHRONOUS_ONLY = 1,
	parameter SIGNIFICANT_BIT_NUMBER_B = $clog2(FREQUENCY*PLL_LOCK_TIME) + 1,

	parameter SIGNIFICANT_BIT_NUMBER_A = SIGNIFICANT_BIT_NUMBER_B/4
) (
	input upstream_clock,
	input upstream_reset,
	input downstream_pll_locked,
	output downstream_reset
);

	reg [SIGNIFICANT_BIT_NUMBER_A:0] counterA = 0;
	reg [SIGNIFICANT_BIT_NUMBER_B:0] counterB = 0;
	reg internal_reset_state = 1;
	reg sychronous_reset_source = 1;
	if (SYNCHRONOUS_ONLY) begin


		assign downstream_reset = sychronous_reset_source;
	end else begin
		wire asychronous_reset_source;
		assign asychronous_reset_source = upstream_reset || (counterB[SIGNIFICANT_BIT_NUMBER_B]&&(~downstream_pll_locked));
		assign downstream_reset = asychronous_reset_source || sychronous_reset_source;
	end
	always @(posedge upstream_clock) begin
		if (upstream_reset) begin
			counterA <= 0;
			sychronous_reset_source <= 1;
			counterB <= 0;
			internal_reset_state <= 1;
		end else if (internal_reset_state) begin
			if (counterA[SIGNIFICANT_BIT_NUMBER_A]) begin
				sychronous_reset_source <= 0;
				if (counterB[SIGNIFICANT_BIT_NUMBER_B]) begin
					internal_reset_state <= 0;
				end else begin
					counterB <= counterB + 1'b1;
				end
			end else begin
				counterA <= counterA + 1'b1;
			end
		end else if (~downstream_pll_locked) begin
			counterA <= 0;
			sychronous_reset_source <= 1;
			counterB <= 0;
			internal_reset_state <= 1;
		end
	end
endmodule