data/full_repos/permissive/212763527/school_project/proj3_safe/sources/mealy.v
1: b"%Error: data/full_repos/permissive/212763527/school_project/proj3_safe/sources/mealy.v:13: Duplicate declaration of signal: 'p'\n                                                                                         : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg [7:0] p;\n          ^\n        data/full_repos/permissive/212763527/school_project/proj3_safe/sources/mealy.v:5: ... Location of original declaration\n             output [7:0] p,  \n                          ^\n%Error: data/full_repos/permissive/212763527/school_project/proj3_safe/sources/mealy.v:14: Duplicate declaration of signal: 'pass'\nreg pass;\n    ^~~~\n        data/full_repos/permissive/212763527/school_project/proj3_safe/sources/mealy.v:6: ... Location of original declaration\n             output pass,    \n                    ^~~~\n%Error: data/full_repos/permissive/212763527/school_project/proj3_safe/sources/mealy.v:15: Duplicate declaration of signal: 'fail'\nreg fail;\n    ^~~~\n        data/full_repos/permissive/212763527/school_project/proj3_safe/sources/mealy.v:7: ... Location of original declaration\n             output fail);   \n                    ^~~~\n%Error: Exiting due to 3 error(s)\n"
module mealy(input [7:0] din,
             input clk,
             input rst,
             input [1:0]X,
             output [7:0] p,
             output pass,
             output fail);

parameter S0 = 3'b000, S1 = 3'b010, S2 = 3'b110, S3 = 3'b100,
          S4 = 3'b011, S5 = 3'b111, S6 = 3'b101;

reg [2:0] curr_state;
reg [7:0] p;
reg pass;
reg fail;


always @(negedge clk) begin
    if (rst) begin
        fail <= 1'b0;
        pass <= 1'b0;
        curr_state <= S0;
        p <= din;
    end else begin
        if (!pass && !fail)
            case (curr_state)
                S0: if (X == p[7:6]) begin
                        curr_state <= S1;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end else begin
                        curr_state <= S4;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end
                S1: if (X == p[5:4]) begin
                        curr_state <= S2;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end else begin
                        curr_state <= S5;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end
                S2: if (X == p[3:2]) begin
                        curr_state <= S3;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end else begin
                        curr_state <= S6;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end
                S3: if (X == p[1:0]) begin
                        curr_state <= S3;
                        pass <= 1'b1;
                        fail <= 1'b0;
                    end else begin
                        curr_state <= S6;
                        pass <= 1'b0;
                        fail <= 1'b1;
                    end
                S4: begin
                        curr_state <= S5;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end
                S5: begin
                        curr_state <= S6;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end
                S6: begin
                        curr_state <= S6;
                        pass <= 1'b0;
                        fail <= 1'b1;
                    end
                default: begin

                            curr_state <= S0;
                            pass <= 1'b1;
                            fail <= 1'b1;
                        end
            endcase
    end
end

endmodule
module mealy(input [7:0] din,
             input clk,
             input rst,
             input [1:0]X,
             output [7:0] p,
             output pass,
             output fail);


parameter S0 = 3'b000, S1 = 3'b010, S2 = 3'b110, S3 = 3'b100,
          S4 = 3'b011, S5 = 3'b111, S6 = 3'b101;

reg [2:0] curr_state;
reg [7:0] p;
reg pass;
reg fail;


always @(negedge clk) begin
    if (rst) begin
        fail <= 1'b0;
        pass <= 1'b0;
        curr_state <= S0;
        p <= din;
    end else begin
        if (!pass && !fail)
            case (curr_state)
                S0: if (X == p[7:6]) begin
                        curr_state <= S1;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end else begin
                        curr_state <= S4;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end
                S1: if (X == p[5:4]) begin
                        curr_state <= S2;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end else begin
                        curr_state <= S5;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end
                S2: if (X == p[3:2]) begin
                        curr_state <= S3;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end else begin
                        curr_state <= S6;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end
                S3: if (X == p[1:0]) begin
                        curr_state <= S3;
                        pass <= 1'b1;
                        fail <= 1'b0;
                    end else begin
                        curr_state <= S6;
                        pass <= 1'b0;
                        fail <= 1'b1;
                    end
                S4: begin
                        curr_state <= S5;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end
                S5: begin
                        curr_state <= S6;
                        pass <= 1'b0;
                        fail <= 1'b0;
                    end
                S6: begin
                        curr_state <= S6;
                        pass <= 1'b0;
                        fail <= 1'b1;
                    end
                default: begin

                            curr_state <= S0;
                            pass <= 1'b1;
                            fail <= 1'b1;
                        end
            endcase
    end
end

endmodule