data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v
1: b'%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:20: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 4\'hf;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:23: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'he\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 4\'he;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:26: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hd\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 4\'hd;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:29: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hc\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 4\'hc;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hb\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 4\'hb;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:35: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 4\'ha;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:38: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h9\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 4\'h9;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:41: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 4\'h8;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:44: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 3\'h7;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:47: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 3\'h6;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:50: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 3\'h5;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:53: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 3\'h4;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:56: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 2\'h3;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:59: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 2\'h2;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:62: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 1\'h1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:65: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 1\'h0;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:68: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h2f\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 6\'h2f;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:71: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h2e\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 6\'h2e;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:74: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h2d\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 6\'h2d;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:77: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h2c\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 6\'h2c;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:80: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h2b\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 6\'h2b;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:83: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h2a\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 6\'h2a;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:86: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h29\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 6\'h29;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:89: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h28\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 6\'h28;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:92: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h27\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 6\'h27;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:95: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h26\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 6\'h26;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:98: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h25\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n        outvalue = 6\'h25;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:101: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h24\' generates 6 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 6\'h24;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:104: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h23\' generates 6 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 6\'h23;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:107: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h22\' generates 6 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 6\'h22;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:110: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h21\' generates 6 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 6\'h21;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:113: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 6\'h20;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:116: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4f\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h4f;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:119: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h4e;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:122: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4d\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h4d;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:125: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4c\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h4c;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:128: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4b\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h4b;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:131: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4a\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h4a;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:134: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h49\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h49;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:137: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h48\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h48;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:140: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h47\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h47;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:143: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h46\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h46;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:146: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h45\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h45;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:149: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h44\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h44;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:152: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h43\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h43;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:155: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h42\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h42;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:158: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h41\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h41;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:161: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h40\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h40;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:164: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h6f\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h6f;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:167: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h6e\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h6e;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:170: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h6d\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h6d;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:173: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h6c\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h6c;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:176: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h6b\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h6b;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:179: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h6a\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h6a;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:182: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h69\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h69;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:185: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h68\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h68;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:188: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h67\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h67;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:191: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h66\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h66;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:194: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h65\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h65;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:197: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h64\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h64;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:200: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h63\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h63;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:203: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h62\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h62;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:206: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h61\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h61;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:209: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h60\' generates 7 bits.\n                                                                                                                                          : ... In instance lookup_39\n        outvalue = 7\'h60;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hb\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hd\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'he\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hf\' generates 4 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h20\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h21\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h22\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h23\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h24\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h25\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h26\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h27\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h28\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h29\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h2a\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h2b\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h2c\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h2d\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h2e\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'6\'h2f\' generates 6 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h40\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h41\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h42\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h43\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h44\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h45\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h46\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h47\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h48\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h49\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h4a\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h4b\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h4c\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h4d\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h4e\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h4f\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h60\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h61\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h62\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h63\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h64\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h65\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h66\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h67\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h68\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h69\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h6a\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h6b\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h6c\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h6d\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h6e\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/209997170/bloxorz/work/planAhead/bloxorz/bloxorz.srcs/sources_1/imports/verilog/lookup_39.v:18: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'7\'h6f\' generates 7 bits.\n                                                                                                                                         : ... In instance lookup_39\n    case (value)\n    ^~~~\n%Error: Exiting due to 128 warning(s)\n'
module lookup_39 (
    input clk,
    input rst,
    input [7:0] value,
    output reg [7:0] outvalue
  );
  
  
  
  always @* begin
    
    case (value)
      1'h0: begin
        outvalue = 4'hf;
      end
      1'h1: begin
        outvalue = 4'he;
      end
      2'h2: begin
        outvalue = 4'hd;
      end
      2'h3: begin
        outvalue = 4'hc;
      end
      3'h4: begin
        outvalue = 4'hb;
      end
      3'h5: begin
        outvalue = 4'ha;
      end
      3'h6: begin
        outvalue = 4'h9;
      end
      3'h7: begin
        outvalue = 4'h8;
      end
      4'h8: begin
        outvalue = 3'h7;
      end
      4'h9: begin
        outvalue = 3'h6;
      end
      4'ha: begin
        outvalue = 3'h5;
      end
      4'hb: begin
        outvalue = 3'h4;
      end
      4'hc: begin
        outvalue = 2'h3;
      end
      4'hd: begin
        outvalue = 2'h2;
      end
      4'he: begin
        outvalue = 1'h1;
      end
      4'hf: begin
        outvalue = 1'h0;
      end
      6'h20: begin
        outvalue = 6'h2f;
      end
      6'h21: begin
        outvalue = 6'h2e;
      end
      6'h22: begin
        outvalue = 6'h2d;
      end
      6'h23: begin
        outvalue = 6'h2c;
      end
      6'h24: begin
        outvalue = 6'h2b;
      end
      6'h25: begin
        outvalue = 6'h2a;
      end
      6'h26: begin
        outvalue = 6'h29;
      end
      6'h27: begin
        outvalue = 6'h28;
      end
      6'h28: begin
        outvalue = 6'h27;
      end
      6'h29: begin
        outvalue = 6'h26;
      end
      6'h2a: begin
        outvalue = 6'h25;
      end
      6'h2b: begin
        outvalue = 6'h24;
      end
      6'h2c: begin
        outvalue = 6'h23;
      end
      6'h2d: begin
        outvalue = 6'h22;
      end
      6'h2e: begin
        outvalue = 6'h21;
      end
      6'h2f: begin
        outvalue = 6'h20;
      end
      7'h40: begin
        outvalue = 7'h4f;
      end
      7'h41: begin
        outvalue = 7'h4e;
      end
      7'h42: begin
        outvalue = 7'h4d;
      end
      7'h43: begin
        outvalue = 7'h4c;
      end
      7'h44: begin
        outvalue = 7'h4b;
      end
      7'h45: begin
        outvalue = 7'h4a;
      end
      7'h46: begin
        outvalue = 7'h49;
      end
      7'h47: begin
        outvalue = 7'h48;
      end
      7'h48: begin
        outvalue = 7'h47;
      end
      7'h49: begin
        outvalue = 7'h46;
      end
      7'h4a: begin
        outvalue = 7'h45;
      end
      7'h4b: begin
        outvalue = 7'h44;
      end
      7'h4c: begin
        outvalue = 7'h43;
      end
      7'h4d: begin
        outvalue = 7'h42;
      end
      7'h4e: begin
        outvalue = 7'h41;
      end
      7'h4f: begin
        outvalue = 7'h40;
      end
      7'h60: begin
        outvalue = 7'h6f;
      end
      7'h61: begin
        outvalue = 7'h6e;
      end
      7'h62: begin
        outvalue = 7'h6d;
      end
      7'h63: begin
        outvalue = 7'h6c;
      end
      7'h64: begin
        outvalue = 7'h6b;
      end
      7'h65: begin
        outvalue = 7'h6a;
      end
      7'h66: begin
        outvalue = 7'h69;
      end
      7'h67: begin
        outvalue = 7'h68;
      end
      7'h68: begin
        outvalue = 7'h67;
      end
      7'h69: begin
        outvalue = 7'h66;
      end
      7'h6a: begin
        outvalue = 7'h65;
      end
      7'h6b: begin
        outvalue = 7'h64;
      end
      7'h6c: begin
        outvalue = 7'h63;
      end
      7'h6d: begin
        outvalue = 7'h62;
      end
      7'h6e: begin
        outvalue = 7'h61;
      end
      7'h6f: begin
        outvalue = 7'h60;
      end
      8'h80: begin
        outvalue = 8'h8f;
      end
      8'h81: begin
        outvalue = 8'h8e;
      end
      8'h82: begin
        outvalue = 8'h8d;
      end
      8'h83: begin
        outvalue = 8'h8c;
      end
      8'h84: begin
        outvalue = 8'h8b;
      end
      8'h85: begin
        outvalue = 8'h8a;
      end
      8'h86: begin
        outvalue = 8'h89;
      end
      8'h87: begin
        outvalue = 8'h88;
      end
      8'h88: begin
        outvalue = 8'h87;
      end
      8'h89: begin
        outvalue = 8'h86;
      end
      8'h8a: begin
        outvalue = 8'h85;
      end
      8'h8b: begin
        outvalue = 8'h84;
      end
      8'h8c: begin
        outvalue = 8'h83;
      end
      8'h8d: begin
        outvalue = 8'h82;
      end
      8'h8e: begin
        outvalue = 8'h81;
      end
      8'h8f: begin
        outvalue = 8'h80;
      end
      8'ha0: begin
        outvalue = 8'haf;
      end
      8'ha1: begin
        outvalue = 8'hae;
      end
      8'ha2: begin
        outvalue = 8'had;
      end
      8'ha3: begin
        outvalue = 8'hac;
      end
      8'ha4: begin
        outvalue = 8'hab;
      end
      8'ha5: begin
        outvalue = 8'haa;
      end
      8'ha6: begin
        outvalue = 8'ha9;
      end
      8'ha7: begin
        outvalue = 8'ha8;
      end
      8'ha8: begin
        outvalue = 8'ha7;
      end
      8'ha9: begin
        outvalue = 8'ha6;
      end
      8'haa: begin
        outvalue = 8'ha5;
      end
      8'hab: begin
        outvalue = 8'ha4;
      end
      8'hac: begin
        outvalue = 8'ha3;
      end
      8'had: begin
        outvalue = 8'ha2;
      end
      8'hae: begin
        outvalue = 8'ha1;
      end
      8'haf: begin
        outvalue = 8'ha0;
      end
      8'hc0: begin
        outvalue = 8'hcf;
      end
      8'hc1: begin
        outvalue = 8'hce;
      end
      8'hc2: begin
        outvalue = 8'hcd;
      end
      8'hc3: begin
        outvalue = 8'hcc;
      end
      8'hc4: begin
        outvalue = 8'hcb;
      end
      8'hc5: begin
        outvalue = 8'hca;
      end
      8'hc6: begin
        outvalue = 8'hc9;
      end
      8'hc7: begin
        outvalue = 8'hc8;
      end
      8'hc8: begin
        outvalue = 8'hc7;
      end
      8'hc9: begin
        outvalue = 8'hc6;
      end
      8'hca: begin
        outvalue = 8'hc5;
      end
      8'hcb: begin
        outvalue = 8'hc4;
      end
      8'hcc: begin
        outvalue = 8'hc3;
      end
      8'hcd: begin
        outvalue = 8'hc2;
      end
      8'hce: begin
        outvalue = 8'hc1;
      end
      8'hcf: begin
        outvalue = 8'hc0;
      end
      8'he0: begin
        outvalue = 8'hef;
      end
      8'he1: begin
        outvalue = 8'hee;
      end
      8'he2: begin
        outvalue = 8'hed;
      end
      8'he3: begin
        outvalue = 8'hec;
      end
      8'he4: begin
        outvalue = 8'heb;
      end
      8'he5: begin
        outvalue = 8'hea;
      end
      8'he6: begin
        outvalue = 8'he9;
      end
      8'he7: begin
        outvalue = 8'he8;
      end
      8'he8: begin
        outvalue = 8'he7;
      end
      8'he9: begin
        outvalue = 8'he6;
      end
      8'hea: begin
        outvalue = 8'he5;
      end
      8'heb: begin
        outvalue = 8'he4;
      end
      8'hec: begin
        outvalue = 8'he3;
      end
      8'hed: begin
        outvalue = 8'he2;
      end
      8'hee: begin
        outvalue = 8'he1;
      end
      8'hef: begin
        outvalue = 8'he0;
      end
      default: begin
        outvalue = value;
      end
    endcase
  end
endmodule
module lookup_39 (
    input clk,
    input rst,
    input [7:0] value,
    output reg [7:0] outvalue
  );

  
  
  
  always @* begin
    
    case (value)
      1'h0: begin
        outvalue = 4'hf;
      end
      1'h1: begin
        outvalue = 4'he;
      end
      2'h2: begin
        outvalue = 4'hd;
      end
      2'h3: begin
        outvalue = 4'hc;
      end
      3'h4: begin
        outvalue = 4'hb;
      end
      3'h5: begin
        outvalue = 4'ha;
      end
      3'h6: begin
        outvalue = 4'h9;
      end
      3'h7: begin
        outvalue = 4'h8;
      end
      4'h8: begin
        outvalue = 3'h7;
      end
      4'h9: begin
        outvalue = 3'h6;
      end
      4'ha: begin
        outvalue = 3'h5;
      end
      4'hb: begin
        outvalue = 3'h4;
      end
      4'hc: begin
        outvalue = 2'h3;
      end
      4'hd: begin
        outvalue = 2'h2;
      end
      4'he: begin
        outvalue = 1'h1;
      end
      4'hf: begin
        outvalue = 1'h0;
      end
      6'h20: begin
        outvalue = 6'h2f;
      end
      6'h21: begin
        outvalue = 6'h2e;
      end
      6'h22: begin
        outvalue = 6'h2d;
      end
      6'h23: begin
        outvalue = 6'h2c;
      end
      6'h24: begin
        outvalue = 6'h2b;
      end
      6'h25: begin
        outvalue = 6'h2a;
      end
      6'h26: begin
        outvalue = 6'h29;
      end
      6'h27: begin
        outvalue = 6'h28;
      end
      6'h28: begin
        outvalue = 6'h27;
      end
      6'h29: begin
        outvalue = 6'h26;
      end
      6'h2a: begin
        outvalue = 6'h25;
      end
      6'h2b: begin
        outvalue = 6'h24;
      end
      6'h2c: begin
        outvalue = 6'h23;
      end
      6'h2d: begin
        outvalue = 6'h22;
      end
      6'h2e: begin
        outvalue = 6'h21;
      end
      6'h2f: begin
        outvalue = 6'h20;
      end
      7'h40: begin
        outvalue = 7'h4f;
      end
      7'h41: begin
        outvalue = 7'h4e;
      end
      7'h42: begin
        outvalue = 7'h4d;
      end
      7'h43: begin
        outvalue = 7'h4c;
      end
      7'h44: begin
        outvalue = 7'h4b;
      end
      7'h45: begin
        outvalue = 7'h4a;
      end
      7'h46: begin
        outvalue = 7'h49;
      end
      7'h47: begin
        outvalue = 7'h48;
      end
      7'h48: begin
        outvalue = 7'h47;
      end
      7'h49: begin
        outvalue = 7'h46;
      end
      7'h4a: begin
        outvalue = 7'h45;
      end
      7'h4b: begin
        outvalue = 7'h44;
      end
      7'h4c: begin
        outvalue = 7'h43;
      end
      7'h4d: begin
        outvalue = 7'h42;
      end
      7'h4e: begin
        outvalue = 7'h41;
      end
      7'h4f: begin
        outvalue = 7'h40;
      end
      7'h60: begin
        outvalue = 7'h6f;
      end
      7'h61: begin
        outvalue = 7'h6e;
      end
      7'h62: begin
        outvalue = 7'h6d;
      end
      7'h63: begin
        outvalue = 7'h6c;
      end
      7'h64: begin
        outvalue = 7'h6b;
      end
      7'h65: begin
        outvalue = 7'h6a;
      end
      7'h66: begin
        outvalue = 7'h69;
      end
      7'h67: begin
        outvalue = 7'h68;
      end
      7'h68: begin
        outvalue = 7'h67;
      end
      7'h69: begin
        outvalue = 7'h66;
      end
      7'h6a: begin
        outvalue = 7'h65;
      end
      7'h6b: begin
        outvalue = 7'h64;
      end
      7'h6c: begin
        outvalue = 7'h63;
      end
      7'h6d: begin
        outvalue = 7'h62;
      end
      7'h6e: begin
        outvalue = 7'h61;
      end
      7'h6f: begin
        outvalue = 7'h60;
      end
      8'h80: begin
        outvalue = 8'h8f;
      end
      8'h81: begin
        outvalue = 8'h8e;
      end
      8'h82: begin
        outvalue = 8'h8d;
      end
      8'h83: begin
        outvalue = 8'h8c;
      end
      8'h84: begin
        outvalue = 8'h8b;
      end
      8'h85: begin
        outvalue = 8'h8a;
      end
      8'h86: begin
        outvalue = 8'h89;
      end
      8'h87: begin
        outvalue = 8'h88;
      end
      8'h88: begin
        outvalue = 8'h87;
      end
      8'h89: begin
        outvalue = 8'h86;
      end
      8'h8a: begin
        outvalue = 8'h85;
      end
      8'h8b: begin
        outvalue = 8'h84;
      end
      8'h8c: begin
        outvalue = 8'h83;
      end
      8'h8d: begin
        outvalue = 8'h82;
      end
      8'h8e: begin
        outvalue = 8'h81;
      end
      8'h8f: begin
        outvalue = 8'h80;
      end
      8'ha0: begin
        outvalue = 8'haf;
      end
      8'ha1: begin
        outvalue = 8'hae;
      end
      8'ha2: begin
        outvalue = 8'had;
      end
      8'ha3: begin
        outvalue = 8'hac;
      end
      8'ha4: begin
        outvalue = 8'hab;
      end
      8'ha5: begin
        outvalue = 8'haa;
      end
      8'ha6: begin
        outvalue = 8'ha9;
      end
      8'ha7: begin
        outvalue = 8'ha8;
      end
      8'ha8: begin
        outvalue = 8'ha7;
      end
      8'ha9: begin
        outvalue = 8'ha6;
      end
      8'haa: begin
        outvalue = 8'ha5;
      end
      8'hab: begin
        outvalue = 8'ha4;
      end
      8'hac: begin
        outvalue = 8'ha3;
      end
      8'had: begin
        outvalue = 8'ha2;
      end
      8'hae: begin
        outvalue = 8'ha1;
      end
      8'haf: begin
        outvalue = 8'ha0;
      end
      8'hc0: begin
        outvalue = 8'hcf;
      end
      8'hc1: begin
        outvalue = 8'hce;
      end
      8'hc2: begin
        outvalue = 8'hcd;
      end
      8'hc3: begin
        outvalue = 8'hcc;
      end
      8'hc4: begin
        outvalue = 8'hcb;
      end
      8'hc5: begin
        outvalue = 8'hca;
      end
      8'hc6: begin
        outvalue = 8'hc9;
      end
      8'hc7: begin
        outvalue = 8'hc8;
      end
      8'hc8: begin
        outvalue = 8'hc7;
      end
      8'hc9: begin
        outvalue = 8'hc6;
      end
      8'hca: begin
        outvalue = 8'hc5;
      end
      8'hcb: begin
        outvalue = 8'hc4;
      end
      8'hcc: begin
        outvalue = 8'hc3;
      end
      8'hcd: begin
        outvalue = 8'hc2;
      end
      8'hce: begin
        outvalue = 8'hc1;
      end
      8'hcf: begin
        outvalue = 8'hc0;
      end
      8'he0: begin
        outvalue = 8'hef;
      end
      8'he1: begin
        outvalue = 8'hee;
      end
      8'he2: begin
        outvalue = 8'hed;
      end
      8'he3: begin
        outvalue = 8'hec;
      end
      8'he4: begin
        outvalue = 8'heb;
      end
      8'he5: begin
        outvalue = 8'hea;
      end
      8'he6: begin
        outvalue = 8'he9;
      end
      8'he7: begin
        outvalue = 8'he8;
      end
      8'he8: begin
        outvalue = 8'he7;
      end
      8'he9: begin
        outvalue = 8'he6;
      end
      8'hea: begin
        outvalue = 8'he5;
      end
      8'heb: begin
        outvalue = 8'he4;
      end
      8'hec: begin
        outvalue = 8'he3;
      end
      8'hed: begin
        outvalue = 8'he2;
      end
      8'hee: begin
        outvalue = 8'he1;
      end
      8'hef: begin
        outvalue = 8'he0;
      end
      default: begin
        outvalue = value;
      end
    endcase
  end
endmodule