data/full_repos/permissive/143278/ivltests/vvp_recv_vec4_pv.v
 line:45: before: "i"
1: b'%Error: data/full_repos/permissive/143278/ivltests/vvp_recv_vec4_pv.v:28: syntax error, unexpected \'@\'\n    @(clk); wait(clk == 1\'b1);\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/vvp_recv_vec4_pv.v:28: Unsupported: wait statements\n    @(clk); wait(clk == 1\'b1);\n            ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vvp_recv_vec4_pv.v:42: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vvp_recv_vec4_pv.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vvp_recv_vec4_pv.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #10 inp = src[i];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vvp_recv_vec4_pv.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #5;  \n    ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module vvp_recv_vec4_pv (input wire logic clk, input wire logic inp,
                         output wire logic[16:0] arr_out);
logic[16:0] arr;

always begin
    arr[15:0] <= arr[16:1];
    @(clk); wait(clk == 1'b1);
end

assign arr[16] = inp;
assign arr_out = arr;

endmodule
module vvp_recv_vec4_pv (input wire logic clk, input wire logic inp,
                         output wire logic[16:0] arr_out);

logic[16:0] arr;

always begin
    arr[15:0] <= arr[16:1];
    @(clk); wait(clk == 1'b1);
end

assign arr[16] = inp;
assign arr_out = arr;

endmodule