data/full_repos/permissive/143278/ivltests/pr1795005b.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1795005b.v:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                          : ... In instance test\nk = $signed(i) < $signed(j);\n  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1795005b.v:13: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTES generates 1 bits.\n                                                                          : ... In instance test\nl = $signed(i) <= $signed(j);\n  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1795005b.v:14: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s GTS generates 1 bits.\n                                                                          : ... In instance test\nm = $signed(i) > $signed(j);\n  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1795005b.v:15: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s GTES generates 1 bits.\n                                                                          : ... In instance test\nn = $signed(i) >= $signed(j);\n  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1795005b.v:17: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'k\' generates 32 bits.\n                                                                          : ... In instance test\n$display("< : %s", k? "Y":"N");\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1795005b.v:18: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'l\' generates 32 bits.\n                                                                          : ... In instance test\n$display("<=: %s", l? "Y":"N");\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1795005b.v:19: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'m\' generates 32 bits.\n                                                                          : ... In instance test\n$display("> : %s", m? "Y":"N");\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1795005b.v:20: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'n\' generates 32 bits.\n                                                                          : ... In instance test\n$display(">=: %s", n? "Y":"N");\n                    ^\n%Error: Exiting due to 8 warning(s)\n'
module test;
reg [63:0] i, j;

initial
main;
task main;
integer k, l, m, n;
begin
i = 64'hffff_ffff_ffff_ffff;
j = 64'hffff_ffff_ffff_fffe;

k = $signed(i) < $signed(j);
l = $signed(i) <= $signed(j);
m = $signed(i) > $signed(j);
n = $signed(i) >= $signed(j);

$display("< : %s", k? "Y":"N");
$display("<=: %s", l? "Y":"N");
$display("> : %s", m? "Y":"N");
$display(">=: %s", n? "Y":"N");
end
endtask
endmodule
module test;

reg [63:0] i, j;

initial
main;
task main;
integer k, l, m, n;
begin
i = 64'hffff_ffff_ffff_ffff;
j = 64'hffff_ffff_ffff_fffe;

k = $signed(i) < $signed(j);
l = $signed(i) <= $signed(j);
m = $signed(i) > $signed(j);
n = $signed(i) >= $signed(j);

$display("< : %s", k? "Y":"N");
$display("<=: %s", l? "Y":"N");
$display("> : %s", m? "Y":"N");
$display(">=: %s", n? "Y":"N");
end
endtask
endmodule