data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/user_fifos_tb.v
 line:58: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/user_fifos_tb.v:5: Unsupported: Ignoring delay on this delayed statement.\n always #5 clock <= ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/user_fifos_tb.v:25: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("fifos.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/user_fifos_tb.v:26: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/user_fifos_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/user_fifos_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/user_fifos_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/user_fifos_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/user_fifos_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/user_fifos_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/user_fifos_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module user_fifos_tb;
	
	reg	clock	= 1;
	always	#5	clock	<= ~clock;
	
	reg	reset	= 0;
	
	reg	rd_req		= 0;
	reg	[1:0]	rd_owner	= 0;
	reg	rd_block	= 0;
	reg	[22:0]	rd_addr	= 0;
	
	wire	raf_full;
	reg	raf_read	= 0;
	wire	raf_block;
	wire	raf_empty_n;
	wire	[1:0]	raf_owner;
	wire	[14:0]	raf_addr;
	
	
	initial begin : Sim

		$write ("%% ");
		$dumpfile ("fifos.vcd");
		$dumpvars;
		

		#5
		reset	<= 1;
		
		#10
		reset	<= 0;
		
		

		#10
		rd_req		<= 1;
		rd_owner	<= 2'b10;
		rd_block	<= 0;
		rd_addr		<= 10;
		
		#10
		rd_req		<= 'bx;
		rd_block	<= 'bx;
		rd_owner	<= 'bx;
		rd_addr		<= 57;
		
		#20
		raf_read	<= 1;
		
		#10
		raf_read	<= 0;
		
		#50
		$finish;
	end
	
	
	user_fifos UFIFO0 (
		.clock_i	(clock),
		.reset_i	(reset),
		

		.rd_req_i	(rd_req),
		.rd_block_i	(rd_block),
		.rd_busy_o	(raf_full),
		.rd_owner_i	(rd_owner),
		.rd_addr_i	(rd_addr),
		
		.wr_req_i	(0),
		.wr_busy_o	(),
		.wr_addr_i	(),
		.wr_bytes_i	(),
		.wr_data_i	(),
		

		.raf_read_i	(raf_read),
		.raf_block_o	(raf_block),
		.raf_empty_no	(raf_empty_n),
		.raf_owner_o	(raf_owner),
		.raf_addr_o	(raf_addr),
		

		.waf_read_i	(0),
		.waf_empty_no	(),
		.waf_addr_o	(),
		
		.wdf_read_i	(0),
		.wdf_bytes_o	(),
		.wdf_data_o	()
	);
	
endmodule
module user_fifos_tb;

	
	reg	clock	= 1;
	always	#5	clock	<= ~clock;
	
	reg	reset	= 0;
	
	reg	rd_req		= 0;
	reg	[1:0]	rd_owner	= 0;
	reg	rd_block	= 0;
	reg	[22:0]	rd_addr	= 0;
	
	wire	raf_full;
	reg	raf_read	= 0;
	wire	raf_block;
	wire	raf_empty_n;
	wire	[1:0]	raf_owner;
	wire	[14:0]	raf_addr;
	
	
	initial begin : Sim

		$write ("%% ");
		$dumpfile ("fifos.vcd");
		$dumpvars;
		

		#5
		reset	<= 1;
		
		#10
		reset	<= 0;
		
		

		#10
		rd_req		<= 1;
		rd_owner	<= 2'b10;
		rd_block	<= 0;
		rd_addr		<= 10;
		
		#10
		rd_req		<= 'bx;
		rd_block	<= 'bx;
		rd_owner	<= 'bx;
		rd_addr		<= 57;
		
		#20
		raf_read	<= 1;
		
		#10
		raf_read	<= 0;
		
		#50
		$finish;
	end
	
	
	user_fifos UFIFO0 (
		.clock_i	(clock),
		.reset_i	(reset),
		

		.rd_req_i	(rd_req),
		.rd_block_i	(rd_block),
		.rd_busy_o	(raf_full),
		.rd_owner_i	(rd_owner),
		.rd_addr_i	(rd_addr),
		
		.wr_req_i	(0),
		.wr_busy_o	(),
		.wr_addr_i	(),
		.wr_bytes_i	(),
		.wr_data_i	(),
		

		.raf_read_i	(raf_read),
		.raf_block_o	(raf_block),
		.raf_empty_no	(raf_empty_n),
		.raf_owner_o	(raf_owner),
		.raf_addr_o	(raf_addr),
		

		.waf_read_i	(0),
		.waf_empty_no	(),
		.waf_addr_o	(),
		
		.wdf_read_i	(0),
		.wdf_bytes_o	(),
		.wdf_data_o	()
	);
	
endmodule