data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:1: Cannot find include file: .\\\\src\\\\head_uart.v\n`include    ".\\\\src\\\\head_uart.v" \n            ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src,data/full_repos/permissive/166661632/.\\\\src\\\\head_uart.v\n             data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src,data/full_repos/permissive/166661632/.\\\\src\\\\head_uart.v.v\n             data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src,data/full_repos/permissive/166661632/.\\\\src\\\\head_uart.v.sv\n             .\\\\src\\\\head_uart.v\n             .\\\\src\\\\head_uart.v.v\n             .\\\\src\\\\head_uart.v.sv\n             obj_dir/.\\\\src\\\\head_uart.v\n             obj_dir/.\\\\src\\\\head_uart.v.v\n             obj_dir/.\\\\src\\\\head_uart.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #50 rst = 0 ;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:32: Define or directive not defined: \'`OFF_UART_LSR\'\n        WB_Read(`OFF_UART_LSR) ;                    \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:37: Define or directive not defined: \'`OFF_UART_DIVT\'\n        WB_Write(`OFF_UART_DIVT, `BAUD_SND_9600) ;   \n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:37: Define or directive not defined: \'`BAUD_SND_9600\'\n        WB_Write(`OFF_UART_DIVT, `BAUD_SND_9600) ;   \n                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:39: Define or directive not defined: \'`OFF_UART_DATA\'\n        WB_Write(`OFF_UART_DATA, 32\'h12) ;           \n                 ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #(1.2*1000000) ;\n        ^\n%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:47: Define or directive not defined: \'`CYCLE\'\n        #(`CYCLE/2) clk = ~clk ;\n          ^~~~~~\n%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:47: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n        #(`CYCLE/2) clk = ~clk ;\n                ^\n%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:56: syntax error, unexpected \'@\'\n            @(negedge clk) ;        \n            ^\n%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:60: syntax error, unexpected \'@\'\n            @(posedge clk)\n            ^\n%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:76: syntax error, unexpected \'@\'\n            @(negedge clk) ;        \n            ^\n%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/testbench.v:81: syntax error, unexpected \'@\'\n            @(negedge clk) ;\n            ^\n%Error: Exiting due to 11 error(s), 2 warning(s)\n'
module testbench_miniuart() ;

    reg             clk, rst ;
    reg             stb, we ;
    reg     [4:2]   off ;
    reg     [31:0]  din ;
    wire    [31:0]  dout ;
    reg     [31:0]  dsave ;
    wire            ack ;

    reg             rxd ;
    wire            txd ;
    

    MiniUART    U_MiniUART( off, din, dout, stb, we, clk, rst, ack, rxd, txd ) ;
    

    initial begin
        clk     = 0 ;
        rst     = 1 ;
        stb     = 0 ;
        we      = 0 ;
        off     = 0 ;
        din     = 32'h0 ;
        dsave   = 32'h0 ;
        rxd     = 1'b1 ;
        #50 rst = 0 ;

        WB_Read(`OFF_UART_LSR) ;

        WB_Write(`OFF_UART_DIVT, `BAUD_SND_9600) ;

        WB_Write(`OFF_UART_DATA, 32'h12) ;
        
        #(1.2*`DELAY_MS) ;
        $stop ;
    end
      

    always  
        #(`CYCLE/2) clk = ~clk ;


    task    WB_Read ;
        input   [3:0]   a ;
        
        begin

            @(negedge clk) ;        
            stb = 1 ;
            we  = 0 ;
            off = a ;
            @(posedge clk)
                dsave = dout ;
            @(negedge clk) ;
            stb = 0 ;
            off = 0 ;
        end
    endtask
    

    task    WB_Write ;
        input   [3:0]   a ;
        input   [31:0]  d ;

        begin    

            @(negedge clk) ;        
            stb = 1 ;
            we  = 1 ;
            off = a ;               
            din = d ;               
            @(negedge clk) ;
            stb = 0 ;
            we  = 0 ;
            off = 0 ;
            din = 0 ;
        end        
    endtask
    
endmodule
module testbench_miniuart() ;


    reg             clk, rst ;
    reg             stb, we ;
    reg     [4:2]   off ;
    reg     [31:0]  din ;
    wire    [31:0]  dout ;
    reg     [31:0]  dsave ;
    wire            ack ;

    reg             rxd ;
    wire            txd ;
    

    MiniUART    U_MiniUART( off, din, dout, stb, we, clk, rst, ack, rxd, txd ) ;
    

    initial begin
        clk     = 0 ;
        rst     = 1 ;
        stb     = 0 ;
        we      = 0 ;
        off     = 0 ;
        din     = 32'h0 ;
        dsave   = 32'h0 ;
        rxd     = 1'b1 ;
        #50 rst = 0 ;

        WB_Read(`OFF_UART_LSR) ;

        WB_Write(`OFF_UART_DIVT, `BAUD_SND_9600) ;

        WB_Write(`OFF_UART_DATA, 32'h12) ;
        
        #(1.2*`DELAY_MS) ;
        $stop ;
    end
      

    always  
        #(`CYCLE/2) clk = ~clk ;


    task    WB_Read ;
        input   [3:0]   a ;
        
        begin

            @(negedge clk) ;        
            stb = 1 ;
            we  = 0 ;
            off = a ;
            @(posedge clk)
                dsave = dout ;
            @(negedge clk) ;
            stb = 0 ;
            off = 0 ;
        end
    endtask
    

    task    WB_Write ;
        input   [3:0]   a ;
        input   [31:0]  d ;

        begin    

            @(negedge clk) ;        
            stb = 1 ;
            we  = 1 ;
            off = a ;               
            din = d ;               
            @(negedge clk) ;
            stb = 0 ;
            we  = 0 ;
            off = 0 ;
            din = 0 ;
        end        
    endtask
    
endmodule