data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:111: Cannot find file containing module: 'IDELAYCTRL'\n  IDELAYCTRL IDELAYCTRL_i0 (\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen,data/full_repos/permissive/214858095/IDELAYCTRL\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen,data/full_repos/permissive/214858095/IDELAYCTRL.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen,data/full_repos/permissive/214858095/IDELAYCTRL.sv\n             IDELAYCTRL\n             IDELAYCTRL.v\n             IDELAYCTRL.sv\n             obj_dir/IDELAYCTRL\n             obj_dir/IDELAYCTRL.v\n             obj_dir/IDELAYCTRL.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:123: Cannot find file containing module: 'IBUFDS'\n  IBUFDS #(\n  ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:134: Cannot find file containing module: 'IDELAYE2'\n      IDELAYE2 #(\n      ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:165: Cannot find file containing module: 'BUFIO'\n  BUFIO ddr_clk_bufio (.O(ddr_clk),.I(ddr_clk_dly));\n  ^~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:173: Cannot find file containing module: 'BUFR'\n  BUFR #(\n  ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:183: Cannot find file containing module: 'BUFR'\n  BUFR #(\n  ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:199: Cannot find file containing module: 'BUFG'\n      BUFG radio_clk_1x_bufg (.O(radio_clk), .I(sdr_clk));\n      ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:200: Cannot find file containing module: 'BUFG'\n      BUFG radio_clk_2x_bufg (.O(radio_clk_2x), .I(sdr_clk_2x));  \n      ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:328: Cannot find file containing module: 'IBUFDS'\n  IBUFDS #(\n  ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:339: Cannot find file containing module: 'IDELAYE2'\n      IDELAYE2 #(\n      ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:368: Cannot find file containing module: 'ISERDESE2'\n  ISERDESE2 #(\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:444: Cannot find file containing module: 'IBUFDS'\n      IBUFDS #(\n      ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:454: Cannot find file containing module: 'IDELAYE2'\n        IDELAYE2 #(\n        ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_input_lvds.v:482: Cannot find file containing module: 'ISERDESE2'\n      ISERDESE2 #(\n      ^~~~~~~~~\n%Error: Exiting due to 14 error(s)\n"
module cat_input_lvds #(
  parameter INVERT_FRAME_RX  = 0,
  parameter INVERT_DATA_RX   = 6'b00_0000,
  parameter USE_CLOCK_DELAY  = 1,
  parameter USE_DATA_DELAY   = 1,
  parameter CLOCK_DELAY_MODE = "VAR_LOAD",
  parameter DATA_DELAY_MODE  = "VAR_LOAD",
  parameter CLOCK_DELAY      = 0,
  parameter DATA_DELAY       = 0,
  parameter WIDTH            = 6,
  parameter GROUP            = "DEFAULT",
  parameter USE_BUFG         = 1
) (
  input clk200,
  input rst,


  input mimo,
  input frame_sample,


  output ddr_clk,
  output sdr_clk,


  input ddr_clk_p,
  input ddr_clk_n,


  input [WIDTH-1:0] ddr_data_p,
  input [WIDTH-1:0] ddr_data_n,
  input             ddr_frame_p,
  input             ddr_frame_n,


  input       ctrl_clk,
  input [4:0] ctrl_data_delay,
  input [4:0] ctrl_clk_delay,
  input       ctrl_ld_data_delay,
  input       ctrl_ld_clk_delay,


  output radio_clk,
  output radio_clk_2x,


  output reg [(WIDTH*2)-1:0] i0,
  output reg [(WIDTH*2)-1:0] q0,
  output reg [(WIDTH*2)-1:0] i1,
  output reg [(WIDTH*2)-1:0] q1,
  output reg                 rx_aligned

);





  (* ASYNC_REG = "TRUE" *) reg rst_sdr_sync, rst_sdr_sync_ms;

  always @(posedge sdr_clk or posedge rst)
    if (rst) begin
      rst_sdr_sync_ms <= 1'b1;
      rst_sdr_sync    <= 1'b1;
    end else begin
      rst_sdr_sync_ms <= 1'b0;
      rst_sdr_sync    <= rst_sdr_sync_ms;
    end







  (* IODELAY_GROUP = GROUP *)
  IDELAYCTRL IDELAYCTRL_i0 (
    .REFCLK (clk200),
    .RST    (rst_sdr_sync),
    .RDY    ()
  );





  wire ddr_clk_dly, ddr_clk_unbuf;

  IBUFDS #(
    .DIFF_TERM("TRUE")
  ) clk_ibufds (
    .O(ddr_clk_unbuf),
    .I(ddr_clk_p),
    .IB(ddr_clk_n)
  );

  generate
    if (USE_CLOCK_DELAY) begin : gen_clock_delay
      (* IODELAY_GROUP = GROUP *)
      IDELAYE2 #(
        .CINVCTRL_SEL          ("FALSE"),
        .DELAY_SRC             ("IDATAIN"),
        .HIGH_PERFORMANCE_MODE ("FALSE"),
        .IDELAY_TYPE           (CLOCK_DELAY_MODE),
        .IDELAY_VALUE          (CLOCK_DELAY),
        .PIPE_SEL              ("FALSE"),
        .REFCLK_FREQUENCY      (200.0),
        .SIGNAL_PATTERN        ("CLOCK")
      ) ddr_clk_idelaye2 (
        .CNTVALUEOUT (),
        .DATAOUT     (ddr_clk_dly),
        .C           (ctrl_clk),
        .CE          (1'b0),
        .CINVCTRL    (1'b0),
        .CNTVALUEIN  (ctrl_clk_delay),
        .DATAIN      (1'b0),
        .IDATAIN     (ddr_clk_unbuf),
        .INC         (1'b0),
        .LD          (ctrl_ld_clk_delay),
        .LDPIPEEN    (1'b0),
        .REGRST      (1'b0)
      ); 
    end
    else begin
      assign ddr_clk_dly = ddr_clk_unbuf;
    end

  endgenerate


  BUFIO ddr_clk_bufio (.O(ddr_clk),.I(ddr_clk_dly));





  wire sdr_clk_2x;

  BUFR #(
    .BUFR_DIVIDE ("2"),
    .SIM_DEVICE  ("7SERIES")
  ) sdr_clk_2x_bufr (
    .O   (sdr_clk_2x),
    .CE  (1'b1),
    .CLR (1'b0),
    .I   (ddr_clk_dly)
  );

  BUFR #(
    .BUFR_DIVIDE("4"),
    .SIM_DEVICE("7SERIES")
  ) sdr_clk_bufr (
    .O(sdr_clk),
    .CE(1'b1),
    .CLR(1'b0),
    .I(ddr_clk_dly)
  );

  generate
    if (USE_BUFG) begin : gen_BUFG




      BUFG radio_clk_1x_bufg (.O(radio_clk), .I(sdr_clk));
      BUFG radio_clk_2x_bufg (.O(radio_clk_2x), .I(sdr_clk_2x));  
    end else begin
      assign radio_clk = sdr_clk;
      assign radio_clk_2x = sdr_clk_2x;
    end
  endgenerate






  wire       ddr_frame, ddr_frame_dly;
  wire [7:0] des_frame;
  reg        bitslip;
  reg        aligned;








  localparam IDLE   = 0;
  localparam SEARCH = 1;
  localparam SLIP1  = 3;
  localparam SLIP2  = 2;
  localparam SLIP3  = 4;
  localparam SLIP4  = 5;
  localparam SYNC   = 6;


  reg [2:0] frame_state;










  wire frame_is_aligned = 
          (!frame_sample && (des_frame[7:0] == (INVERT_FRAME_RX ? 8'h0F : 8'hF0))) ||
          ( frame_sample && (des_frame[7:0] == (INVERT_FRAME_RX ? 8'h33 : 8'hCC)));

  reg [5:0] sync_delay;
  reg       run_sync;


  always @(posedge sdr_clk)
    if (rst_sdr_sync) begin
      sync_delay <= 6'h0;
      run_sync <= 1'b0;
    end else if (sync_delay == 6'h3F)
      run_sync <= 1'b1;
    else
      sync_delay <= sync_delay + 1'b1;

  always @(posedge sdr_clk)
  begin
    if (!run_sync) begin
      frame_state <= IDLE;
      bitslip <= 1'b0;
      aligned <= 1'b0;
    end else begin
      case (frame_state)
        IDLE: begin
          bitslip <= 1'b0;
          aligned <= 1'b0;
          frame_state <= SEARCH;
        end

        SEARCH: begin
          if (frame_is_aligned) begin
            frame_state <= SYNC;
            bitslip <= 1'b0;
            aligned <= 1'b1;
          end else begin

            bitslip <= 1'b1;
            frame_state <= SLIP1;
            aligned <= 1'b0;
          end
        end

        SLIP1: begin
          frame_state <= SLIP2;
          bitslip <= 1'b0;
          aligned <= 1'b0;
        end

        SLIP2: begin
          frame_state <= SLIP3;
          bitslip <= 1'b0;
          aligned <= 1'b0;
        end

        SLIP3: begin
          frame_state <= SLIP4;
          bitslip <= 1'b0;
          aligned <= 1'b0;
        end

        SLIP4: begin
          frame_state <= SEARCH;
          bitslip <= 1'b0;
          aligned <= 1'b0;
        end

        SYNC: begin
          if (frame_is_aligned) begin
            frame_state <= SYNC;
            aligned <= 1'b1;
          end else begin
            frame_state <= SEARCH;
            aligned <= 1'b0;
          end
        end

      endcase

    end
  end


  IBUFDS #(
    .DIFF_TERM ("TRUE")
  ) ddr_frame_ibufds (
    .O  (ddr_frame),
    .I  (ddr_frame_p),
    .IB (ddr_frame_n)
  );

  generate
    if (USE_DATA_DELAY) begin : gen_frame_delay
      (* IODELAY_GROUP = GROUP *)
      IDELAYE2 #(
        .CINVCTRL_SEL          ("FALSE"),
        .DELAY_SRC             ("IDATAIN"),
        .HIGH_PERFORMANCE_MODE ("FALSE"),
        .IDELAY_TYPE           (DATA_DELAY_MODE),
        .IDELAY_VALUE          (DATA_DELAY),
        .PIPE_SEL              ("FALSE"),
        .REFCLK_FREQUENCY      (200.0),
        .SIGNAL_PATTERN        ("DATA")
      ) ddr_frame_idelaye2 (
        .CNTVALUEOUT (),
        .DATAOUT     (ddr_frame_dly),
        .C           (ctrl_clk),
        .CE          (1'b0),
        .CINVCTRL    (1'b0),
        .CNTVALUEIN  (ctrl_data_delay),
        .DATAIN      (1'b0),
        .IDATAIN     (ddr_frame),
        .INC         (1'b0),
        .LD          (ctrl_ld_data_delay),
        .LDPIPEEN    (1'b0),
        .REGRST      (1'b0)
      );
    end
    else begin
      assign ddr_frame_dly = ddr_frame;
    end
  endgenerate

  ISERDESE2 #(
    .DATA_RATE         ("DDR"),
    .DATA_WIDTH        (8),
    .DYN_CLKDIV_INV_EN ("FALSE"),
    .DYN_CLK_INV_EN    ("FALSE"),

    .INIT_Q1           (1'b0),
    .INIT_Q2           (1'b0),
    .INIT_Q3           (1'b0),
    .INIT_Q4           (1'b0),
    .INTERFACE_TYPE    ("NETWORKING"),
    .IOBDELAY          ("BOTH"),
    .NUM_CE            (1),
    .OFB_USED          ("FALSE"),
    .SERDES_MODE       ("MASTER"),

    .SRVAL_Q1          (1'b0),
    .SRVAL_Q2          (1'b0),
    .SRVAL_Q3          (1'b0),
    .SRVAL_Q4          (1'b0)
  ) ddr_frame_serdese2 (
    .O            (),

    .Q1           (des_frame[0]),
    .Q2           (des_frame[1]),
    .Q3           (des_frame[2]),
    .Q4           (des_frame[3]),
    .Q5           (des_frame[4]),
    .Q6           (des_frame[5]),
    .Q7           (des_frame[6]),
    .Q8           (des_frame[7]),

    .SHIFTOUT1    (),
    .SHIFTOUT2    (),




    .BITSLIP      (bitslip),

    .CE1          (1'b1),
    .CE2          (1'b1),
    .CLKDIVP      (1'b0),

    .CLK          (ddr_clk),
    .CLKB         (~ddr_clk),
    .CLKDIV       (sdr_clk),
    .OCLK         (1'b0),

    .DYNCLKDIVSEL (1'b0),
    .DYNCLKSEL    (1'b0),

    .D            (1'b0),
    .DDLY         (ddr_frame_dly),
    .OFB          (1'b0),
    .OCLKB        (1'b0),
    .RST          (rst_sdr_sync),

    .SHIFTIN1     (1'b0),
    .SHIFTIN2     (1'b0)
  );





  wire [WIDTH-1:0] ddr_data;
  wire [WIDTH-1:0] ddr_data_dly;
  wire [(WIDTH*2)-1:0] data_i0, data_i1;
  wire [(WIDTH*2)-1:0] data_q0, data_q1;


  genvar i;
  generate
    for (i=0 ; i<WIDTH ; i=i+1) begin : generate_data_bus

      IBUFDS #(
        .DIFF_TERM ("TRUE")
      ) ddr_data_ibufds (
        .O  (ddr_data[i]),
        .I  (ddr_data_p[i]),
        .IB (ddr_data_n[i])
      );

      if (USE_DATA_DELAY) begin : gen_data_delay
        (* IODELAY_GROUP = GROUP *)
        IDELAYE2 #(
          .CINVCTRL_SEL          ("FALSE"),
          .DELAY_SRC             ("IDATAIN"),
          .HIGH_PERFORMANCE_MODE ("FALSE"),
          .IDELAY_TYPE           (DATA_DELAY_MODE),
          .IDELAY_VALUE          (DATA_DELAY),
          .PIPE_SEL              ("FALSE"),
          .REFCLK_FREQUENCY      (200.0),
          .SIGNAL_PATTERN        ("DATA")
        ) ddr_data_idelaye2 (
          .CNTVALUEOUT (),
          .DATAOUT     (ddr_data_dly[i]),
          .C           (ctrl_clk),
          .CE          (1'b0),
          .CINVCTRL    (1'b0),
          .CNTVALUEIN  (ctrl_data_delay),
          .DATAIN      (1'b0),
          .IDATAIN     (ddr_data[i]),
          .INC         (1'b0),
          .LD          (ctrl_ld_data_delay),
          .LDPIPEEN    (1'b0),
          .REGRST      (1'b0)
        );
      end
      else begin
        assign ddr_data_dly[i] = ddr_data[i];
      end

      ISERDESE2 #(
        .DATA_RATE         ("DDR"),
        .DATA_WIDTH        (8),
        .DYN_CLKDIV_INV_EN ("FALSE"),
        .DYN_CLK_INV_EN    ("FALSE"),

        .INIT_Q1           (1'b0),
        .INIT_Q2           (1'b0),
        .INIT_Q3           (1'b0),
        .INIT_Q4           (1'b0),
        .INTERFACE_TYPE    ("NETWORKING"),
        .IOBDELAY          ("BOTH"),
        .NUM_CE            (1),
        .OFB_USED          ("FALSE"),
        .SERDES_MODE       ("MASTER"),

        .SRVAL_Q1          (1'b0),
        .SRVAL_Q2          (1'b0),
        .SRVAL_Q3          (1'b0),
        .SRVAL_Q4          (1'b0)
      ) ddr_data_serdese2 (
        .O            (),

        .Q1           (data_q1[i]),
        .Q2           (data_i1[i]),
        .Q3           (data_q1[WIDTH+i]),
        .Q4           (data_i1[WIDTH+i]),
        .Q5           (data_q0[i]),
        .Q6           (data_i0[i]),
        .Q7           (data_q0[WIDTH+i]),
        .Q8           (data_i0[WIDTH+i]),

        .SHIFTOUT1    (),
        .SHIFTOUT2    (),




        .BITSLIP      (bitslip),

        .CE1          (1'b1),
        .CE2          (1'b1),
        .CLKDIVP      (1'b0),

        .CLK          (ddr_clk),
        .CLKB         (~ddr_clk),
        .CLKDIV       (sdr_clk),
        .OCLK         (1'b0),

        .DYNCLKDIVSEL (1'b0),
        .DYNCLKSEL    (1'b0),

        .D            (1'b0),
        .DDLY         (ddr_data_dly[i]),
        .OFB          (1'b0),
        .OCLKB        (1'b0),
        .RST          (rst_sdr_sync),

        .SHIFTIN1     (1'b0),
        .SHIFTIN2     (1'b0)
      );

    end
  endgenerate





  reg [(WIDTH*2)-1:0] radio_data_i0, radio_data_i1, radio_data_q0, radio_data_q1;
  reg                 radio_aligned;

  always @(negedge radio_clk)
    begin
      radio_data_i0[(WIDTH*2)-1:0] <= data_i0[(WIDTH*2)-1:0] ^ {INVERT_DATA_RX,INVERT_DATA_RX};
      radio_data_q0[(WIDTH*2)-1:0] <= data_q0[(WIDTH*2)-1:0] ^ {INVERT_DATA_RX,INVERT_DATA_RX};
      radio_data_i1[(WIDTH*2)-1:0] <= data_i1[(WIDTH*2)-1:0] ^ {INVERT_DATA_RX,INVERT_DATA_RX};
      radio_data_q1[(WIDTH*2)-1:0] <= data_q1[(WIDTH*2)-1:0] ^ {INVERT_DATA_RX,INVERT_DATA_RX};
      radio_aligned                <= aligned;
    end

  always @(posedge radio_clk)
    begin
      i0 <= radio_data_i0;
      q0 <= radio_data_q0;
      if (mimo) { i1, q1 } <= { radio_data_i1, radio_data_q1 };
      else { i1, q1 } <= { radio_data_i0, radio_data_q0 };
      rx_aligned <= radio_aligned;
    end




endmodule
module cat_input_lvds #(
  parameter INVERT_FRAME_RX  = 0,
  parameter INVERT_DATA_RX   = 6'b00_0000,
  parameter USE_CLOCK_DELAY  = 1,
  parameter USE_DATA_DELAY   = 1,
  parameter CLOCK_DELAY_MODE = "VAR_LOAD",
  parameter DATA_DELAY_MODE  = "VAR_LOAD",
  parameter CLOCK_DELAY      = 0,
  parameter DATA_DELAY       = 0,
  parameter WIDTH            = 6,
  parameter GROUP            = "DEFAULT",
  parameter USE_BUFG         = 1
) (
  input clk200,
  input rst,


  input mimo,
  input frame_sample,


  output ddr_clk,
  output sdr_clk,


  input ddr_clk_p,
  input ddr_clk_n,


  input [WIDTH-1:0] ddr_data_p,
  input [WIDTH-1:0] ddr_data_n,
  input             ddr_frame_p,
  input             ddr_frame_n,


  input       ctrl_clk,
  input [4:0] ctrl_data_delay,
  input [4:0] ctrl_clk_delay,
  input       ctrl_ld_data_delay,
  input       ctrl_ld_clk_delay,


  output radio_clk,
  output radio_clk_2x,


  output reg [(WIDTH*2)-1:0] i0,
  output reg [(WIDTH*2)-1:0] q0,
  output reg [(WIDTH*2)-1:0] i1,
  output reg [(WIDTH*2)-1:0] q1,
  output reg                 rx_aligned

);






  (* ASYNC_REG = "TRUE" *) reg rst_sdr_sync, rst_sdr_sync_ms;

  always @(posedge sdr_clk or posedge rst)
    if (rst) begin
      rst_sdr_sync_ms <= 1'b1;
      rst_sdr_sync    <= 1'b1;
    end else begin
      rst_sdr_sync_ms <= 1'b0;
      rst_sdr_sync    <= rst_sdr_sync_ms;
    end







  (* IODELAY_GROUP = GROUP *)
  IDELAYCTRL IDELAYCTRL_i0 (
    .REFCLK (clk200),
    .RST    (rst_sdr_sync),
    .RDY    ()
  );





  wire ddr_clk_dly, ddr_clk_unbuf;

  IBUFDS #(
    .DIFF_TERM("TRUE")
  ) clk_ibufds (
    .O(ddr_clk_unbuf),
    .I(ddr_clk_p),
    .IB(ddr_clk_n)
  );

  generate
    if (USE_CLOCK_DELAY) begin : gen_clock_delay
      (* IODELAY_GROUP = GROUP *)
      IDELAYE2 #(
        .CINVCTRL_SEL          ("FALSE"),
        .DELAY_SRC             ("IDATAIN"),
        .HIGH_PERFORMANCE_MODE ("FALSE"),
        .IDELAY_TYPE           (CLOCK_DELAY_MODE),
        .IDELAY_VALUE          (CLOCK_DELAY),
        .PIPE_SEL              ("FALSE"),
        .REFCLK_FREQUENCY      (200.0),
        .SIGNAL_PATTERN        ("CLOCK")
      ) ddr_clk_idelaye2 (
        .CNTVALUEOUT (),
        .DATAOUT     (ddr_clk_dly),
        .C           (ctrl_clk),
        .CE          (1'b0),
        .CINVCTRL    (1'b0),
        .CNTVALUEIN  (ctrl_clk_delay),
        .DATAIN      (1'b0),
        .IDATAIN     (ddr_clk_unbuf),
        .INC         (1'b0),
        .LD          (ctrl_ld_clk_delay),
        .LDPIPEEN    (1'b0),
        .REGRST      (1'b0)
      ); 
    end
    else begin
      assign ddr_clk_dly = ddr_clk_unbuf;
    end

  endgenerate


  BUFIO ddr_clk_bufio (.O(ddr_clk),.I(ddr_clk_dly));





  wire sdr_clk_2x;

  BUFR #(
    .BUFR_DIVIDE ("2"),
    .SIM_DEVICE  ("7SERIES")
  ) sdr_clk_2x_bufr (
    .O   (sdr_clk_2x),
    .CE  (1'b1),
    .CLR (1'b0),
    .I   (ddr_clk_dly)
  );

  BUFR #(
    .BUFR_DIVIDE("4"),
    .SIM_DEVICE("7SERIES")
  ) sdr_clk_bufr (
    .O(sdr_clk),
    .CE(1'b1),
    .CLR(1'b0),
    .I(ddr_clk_dly)
  );

  generate
    if (USE_BUFG) begin : gen_BUFG




      BUFG radio_clk_1x_bufg (.O(radio_clk), .I(sdr_clk));
      BUFG radio_clk_2x_bufg (.O(radio_clk_2x), .I(sdr_clk_2x));  
    end else begin
      assign radio_clk = sdr_clk;
      assign radio_clk_2x = sdr_clk_2x;
    end
  endgenerate






  wire       ddr_frame, ddr_frame_dly;
  wire [7:0] des_frame;
  reg        bitslip;
  reg        aligned;








  localparam IDLE   = 0;
  localparam SEARCH = 1;
  localparam SLIP1  = 3;
  localparam SLIP2  = 2;
  localparam SLIP3  = 4;
  localparam SLIP4  = 5;
  localparam SYNC   = 6;


  reg [2:0] frame_state;










  wire frame_is_aligned = 
          (!frame_sample && (des_frame[7:0] == (INVERT_FRAME_RX ? 8'h0F : 8'hF0))) ||
          ( frame_sample && (des_frame[7:0] == (INVERT_FRAME_RX ? 8'h33 : 8'hCC)));

  reg [5:0] sync_delay;
  reg       run_sync;


  always @(posedge sdr_clk)
    if (rst_sdr_sync) begin
      sync_delay <= 6'h0;
      run_sync <= 1'b0;
    end else if (sync_delay == 6'h3F)
      run_sync <= 1'b1;
    else
      sync_delay <= sync_delay + 1'b1;

  always @(posedge sdr_clk)
  begin
    if (!run_sync) begin
      frame_state <= IDLE;
      bitslip <= 1'b0;
      aligned <= 1'b0;
    end else begin
      case (frame_state)
        IDLE: begin
          bitslip <= 1'b0;
          aligned <= 1'b0;
          frame_state <= SEARCH;
        end

        SEARCH: begin
          if (frame_is_aligned) begin
            frame_state <= SYNC;
            bitslip <= 1'b0;
            aligned <= 1'b1;
          end else begin

            bitslip <= 1'b1;
            frame_state <= SLIP1;
            aligned <= 1'b0;
          end
        end

        SLIP1: begin
          frame_state <= SLIP2;
          bitslip <= 1'b0;
          aligned <= 1'b0;
        end

        SLIP2: begin
          frame_state <= SLIP3;
          bitslip <= 1'b0;
          aligned <= 1'b0;
        end

        SLIP3: begin
          frame_state <= SLIP4;
          bitslip <= 1'b0;
          aligned <= 1'b0;
        end

        SLIP4: begin
          frame_state <= SEARCH;
          bitslip <= 1'b0;
          aligned <= 1'b0;
        end

        SYNC: begin
          if (frame_is_aligned) begin
            frame_state <= SYNC;
            aligned <= 1'b1;
          end else begin
            frame_state <= SEARCH;
            aligned <= 1'b0;
          end
        end

      endcase

    end
  end


  IBUFDS #(
    .DIFF_TERM ("TRUE")
  ) ddr_frame_ibufds (
    .O  (ddr_frame),
    .I  (ddr_frame_p),
    .IB (ddr_frame_n)
  );

  generate
    if (USE_DATA_DELAY) begin : gen_frame_delay
      (* IODELAY_GROUP = GROUP *)
      IDELAYE2 #(
        .CINVCTRL_SEL          ("FALSE"),
        .DELAY_SRC             ("IDATAIN"),
        .HIGH_PERFORMANCE_MODE ("FALSE"),
        .IDELAY_TYPE           (DATA_DELAY_MODE),
        .IDELAY_VALUE          (DATA_DELAY),
        .PIPE_SEL              ("FALSE"),
        .REFCLK_FREQUENCY      (200.0),
        .SIGNAL_PATTERN        ("DATA")
      ) ddr_frame_idelaye2 (
        .CNTVALUEOUT (),
        .DATAOUT     (ddr_frame_dly),
        .C           (ctrl_clk),
        .CE          (1'b0),
        .CINVCTRL    (1'b0),
        .CNTVALUEIN  (ctrl_data_delay),
        .DATAIN      (1'b0),
        .IDATAIN     (ddr_frame),
        .INC         (1'b0),
        .LD          (ctrl_ld_data_delay),
        .LDPIPEEN    (1'b0),
        .REGRST      (1'b0)
      );
    end
    else begin
      assign ddr_frame_dly = ddr_frame;
    end
  endgenerate

  ISERDESE2 #(
    .DATA_RATE         ("DDR"),
    .DATA_WIDTH        (8),
    .DYN_CLKDIV_INV_EN ("FALSE"),
    .DYN_CLK_INV_EN    ("FALSE"),

    .INIT_Q1           (1'b0),
    .INIT_Q2           (1'b0),
    .INIT_Q3           (1'b0),
    .INIT_Q4           (1'b0),
    .INTERFACE_TYPE    ("NETWORKING"),
    .IOBDELAY          ("BOTH"),
    .NUM_CE            (1),
    .OFB_USED          ("FALSE"),
    .SERDES_MODE       ("MASTER"),

    .SRVAL_Q1          (1'b0),
    .SRVAL_Q2          (1'b0),
    .SRVAL_Q3          (1'b0),
    .SRVAL_Q4          (1'b0)
  ) ddr_frame_serdese2 (
    .O            (),

    .Q1           (des_frame[0]),
    .Q2           (des_frame[1]),
    .Q3           (des_frame[2]),
    .Q4           (des_frame[3]),
    .Q5           (des_frame[4]),
    .Q6           (des_frame[5]),
    .Q7           (des_frame[6]),
    .Q8           (des_frame[7]),

    .SHIFTOUT1    (),
    .SHIFTOUT2    (),




    .BITSLIP      (bitslip),

    .CE1          (1'b1),
    .CE2          (1'b1),
    .CLKDIVP      (1'b0),

    .CLK          (ddr_clk),
    .CLKB         (~ddr_clk),
    .CLKDIV       (sdr_clk),
    .OCLK         (1'b0),

    .DYNCLKDIVSEL (1'b0),
    .DYNCLKSEL    (1'b0),

    .D            (1'b0),
    .DDLY         (ddr_frame_dly),
    .OFB          (1'b0),
    .OCLKB        (1'b0),
    .RST          (rst_sdr_sync),

    .SHIFTIN1     (1'b0),
    .SHIFTIN2     (1'b0)
  );





  wire [WIDTH-1:0] ddr_data;
  wire [WIDTH-1:0] ddr_data_dly;
  wire [(WIDTH*2)-1:0] data_i0, data_i1;
  wire [(WIDTH*2)-1:0] data_q0, data_q1;


  genvar i;
  generate
    for (i=0 ; i<WIDTH ; i=i+1) begin : generate_data_bus

      IBUFDS #(
        .DIFF_TERM ("TRUE")
      ) ddr_data_ibufds (
        .O  (ddr_data[i]),
        .I  (ddr_data_p[i]),
        .IB (ddr_data_n[i])
      );

      if (USE_DATA_DELAY) begin : gen_data_delay
        (* IODELAY_GROUP = GROUP *)
        IDELAYE2 #(
          .CINVCTRL_SEL          ("FALSE"),
          .DELAY_SRC             ("IDATAIN"),
          .HIGH_PERFORMANCE_MODE ("FALSE"),
          .IDELAY_TYPE           (DATA_DELAY_MODE),
          .IDELAY_VALUE          (DATA_DELAY),
          .PIPE_SEL              ("FALSE"),
          .REFCLK_FREQUENCY      (200.0),
          .SIGNAL_PATTERN        ("DATA")
        ) ddr_data_idelaye2 (
          .CNTVALUEOUT (),
          .DATAOUT     (ddr_data_dly[i]),
          .C           (ctrl_clk),
          .CE          (1'b0),
          .CINVCTRL    (1'b0),
          .CNTVALUEIN  (ctrl_data_delay),
          .DATAIN      (1'b0),
          .IDATAIN     (ddr_data[i]),
          .INC         (1'b0),
          .LD          (ctrl_ld_data_delay),
          .LDPIPEEN    (1'b0),
          .REGRST      (1'b0)
        );
      end
      else begin
        assign ddr_data_dly[i] = ddr_data[i];
      end

      ISERDESE2 #(
        .DATA_RATE         ("DDR"),
        .DATA_WIDTH        (8),
        .DYN_CLKDIV_INV_EN ("FALSE"),
        .DYN_CLK_INV_EN    ("FALSE"),

        .INIT_Q1           (1'b0),
        .INIT_Q2           (1'b0),
        .INIT_Q3           (1'b0),
        .INIT_Q4           (1'b0),
        .INTERFACE_TYPE    ("NETWORKING"),
        .IOBDELAY          ("BOTH"),
        .NUM_CE            (1),
        .OFB_USED          ("FALSE"),
        .SERDES_MODE       ("MASTER"),

        .SRVAL_Q1          (1'b0),
        .SRVAL_Q2          (1'b0),
        .SRVAL_Q3          (1'b0),
        .SRVAL_Q4          (1'b0)
      ) ddr_data_serdese2 (
        .O            (),

        .Q1           (data_q1[i]),
        .Q2           (data_i1[i]),
        .Q3           (data_q1[WIDTH+i]),
        .Q4           (data_i1[WIDTH+i]),
        .Q5           (data_q0[i]),
        .Q6           (data_i0[i]),
        .Q7           (data_q0[WIDTH+i]),
        .Q8           (data_i0[WIDTH+i]),

        .SHIFTOUT1    (),
        .SHIFTOUT2    (),




        .BITSLIP      (bitslip),

        .CE1          (1'b1),
        .CE2          (1'b1),
        .CLKDIVP      (1'b0),

        .CLK          (ddr_clk),
        .CLKB         (~ddr_clk),
        .CLKDIV       (sdr_clk),
        .OCLK         (1'b0),

        .DYNCLKDIVSEL (1'b0),
        .DYNCLKSEL    (1'b0),

        .D            (1'b0),
        .DDLY         (ddr_data_dly[i]),
        .OFB          (1'b0),
        .OCLKB        (1'b0),
        .RST          (rst_sdr_sync),

        .SHIFTIN1     (1'b0),
        .SHIFTIN2     (1'b0)
      );

    end
  endgenerate





  reg [(WIDTH*2)-1:0] radio_data_i0, radio_data_i1, radio_data_q0, radio_data_q1;
  reg                 radio_aligned;

  always @(negedge radio_clk)
    begin
      radio_data_i0[(WIDTH*2)-1:0] <= data_i0[(WIDTH*2)-1:0] ^ {INVERT_DATA_RX,INVERT_DATA_RX};
      radio_data_q0[(WIDTH*2)-1:0] <= data_q0[(WIDTH*2)-1:0] ^ {INVERT_DATA_RX,INVERT_DATA_RX};
      radio_data_i1[(WIDTH*2)-1:0] <= data_i1[(WIDTH*2)-1:0] ^ {INVERT_DATA_RX,INVERT_DATA_RX};
      radio_data_q1[(WIDTH*2)-1:0] <= data_q1[(WIDTH*2)-1:0] ^ {INVERT_DATA_RX,INVERT_DATA_RX};
      radio_aligned                <= aligned;
    end

  always @(posedge radio_clk)
    begin
      i0 <= radio_data_i0;
      q0 <= radio_data_q0;
      if (mimo) { i1, q1 } <= { radio_data_i1, radio_data_q1 };
      else { i1, q1 } <= { radio_data_i0, radio_data_q0 };
      rx_aligned <= radio_aligned;
    end




endmodule