data/full_repos/permissive/129155059/proyecto-02/memory/memory_testbench.v
 line:99: before: "*"
1: b'%Error: data/full_repos/permissive/129155059/proyecto-02/memory/memory_testbench.v:2: Cannot find include file: memory_cond.v\n`include "memory_cond.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-02/memory,data/full_repos/permissive/129155059/memory_cond.v\n             data/full_repos/permissive/129155059/proyecto-02/memory,data/full_repos/permissive/129155059/memory_cond.v.v\n             data/full_repos/permissive/129155059/proyecto-02/memory,data/full_repos/permissive/129155059/memory_cond.v.sv\n             memory_cond.v\n             memory_cond.v.v\n             memory_cond.v.sv\n             obj_dir/memory_cond.v\n             obj_dir/memory_cond.v.v\n             obj_dir/memory_cond.v.sv\n%Error: data/full_repos/permissive/129155059/proyecto-02/memory/memory_testbench.v:3: Cannot find include file: memory_synth.v\n`include "memory_synth.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/memory/memory_testbench.v:4: Cannot find include file: memory_tester.v\n`include "memory_tester.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/memory/memory_testbench.v:5: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module memory_testbench;
  wire clock;
  wire enable;
  wire lectura;
  wire escritura;
  wire [2:0] dirLectura;
  wire [2:0] dicEscritura;
  wire [7:0] datoEntrada;
  wire [7:0] datoSalida;
  wire [7:0] datoSalida_synth;

  memory_cond memory_cond (
    .CLK          (clock),
    .ENB          (enable),
    .sRead        (lectura),
    .sWrite       (escritura),
    .addressRead  (dirLectura),
    .addressWrite (dicEscritura),
    .inputData    (datoEntrada),
    .outputData   (datoSalida)
    );
    memory_synth MEM_synth (
      .CLK          (clock),
      .ENB          (enable),
      .sRead        (lectura),
      .sWrite       (escritura),
      .addressRead  (dirLectura),
      .addressWrite (dicEscritura),
      .inputData    (datoEntrada),
      .outputData   (datoSalida_synth)
      );

    memory_tester MEM_tester (
      .CLK          (clock),
      .ENB          (enable),
      .sRead        (lectura),
      .sWrite       (escritura),
      .addressRead  (dirLectura),
      .addressWrite (dicEscritura),
      .inputData    (datoEntrada)
      );



endmodule
module memory_testbench;

  wire clock;
  wire enable;
  wire lectura;
  wire escritura;
  wire [2:0] dirLectura;
  wire [2:0] dicEscritura;
  wire [7:0] datoEntrada;
  wire [7:0] datoSalida;
  wire [7:0] datoSalida_synth;

  memory_cond memory_cond (
    .CLK          (clock),
    .ENB          (enable),
    .sRead        (lectura),
    .sWrite       (escritura),
    .addressRead  (dirLectura),
    .addressWrite (dicEscritura),
    .inputData    (datoEntrada),
    .outputData   (datoSalida)
    );
    memory_synth MEM_synth (
      .CLK          (clock),
      .ENB          (enable),
      .sRead        (lectura),
      .sWrite       (escritura),
      .addressRead  (dirLectura),
      .addressWrite (dicEscritura),
      .inputData    (datoEntrada),
      .outputData   (datoSalida_synth)
      );

    memory_tester MEM_tester (
      .CLK          (clock),
      .ENB          (enable),
      .sRead        (lectura),
      .sWrite       (escritura),
      .addressRead  (dirLectura),
      .addressWrite (dicEscritura),
      .inputData    (datoEntrada)
      );



endmodule