data/full_repos/permissive/169925025/hw3_2/rca_16b.v
data/verilator_xmls/072f0a62-db4d-4c99-98da-e1059aac6b3b.xml
module rca_16b(A, B, S, C_out);


    parameter   N = 16;

    input [N-1: 0] A, B;
    output [N-1:0] S;
    output         C_out;



endmodule
module rca_16b(A, B, S, C_out);



    parameter   N = 16;

    input [N-1: 0] A, B;
    output [N-1:0] S;
    output         C_out;



endmodule