data/full_repos/permissive/211316121/lab5_2/Top.v
1: b"%Error: data/full_repos/permissive/211316121/lab5_2/Top.v:27: syntax error, unexpected '(', expecting IDENTIFIER\n       clkdiv(.mclk(CLK100MHZ),.clk20(s[1]),.clk19(s[0]));\n              ^\n%Error: Exiting due to 1 error(s)\n"
module DigitalClock_Top(
    input   CLK100MHZ,
    input [12:0]SW,
    output [6:0] A2G,
    output [7:0] AN,
    output  DP);


    wire _1s;
    one_min U1(.clk(CLK100MHZ), .onemin(_1m));

    wire [7:0] m_count;
    wire m_out;   
    wire [9:0] m_BCD; 
    min_counter S1(.clk(CLK100MHZ), .clr(SW[0]),.E(SW[1]), .data(SW[7:2]),.time_in(_1m), 
                   .counter(m_count), .time_out(m_out));
   to_BCD S2(.n(m_count), .b(m_BCD));               
 
    wire [7:0] h_count;
    wire h_out;
    wire [9:0] h_BCD; 
    hour_counter M1(.clk(CLK100MHZ), .clr(SW[0]),.E(SW[1]),.data(SW[12:8]),.time_in(m_out), 
                   .counter(h_count), .time_out(h_out));
    to_BCD M2(.n(h_count), .b(h_BCD));
    
       wire [1:0]s;
       clkdiv(.mclk(CLK100MHZ),.clk20(s[1]),.clk19(s[0]));
               
    wire [15:0] x;  
    assign x = {h_BCD[7:0], m_BCD[7:0]};

    x7seg X7(.x(x), .clk(CLK100MHZ), .s(s),
             .a2g(A2G), .an(AN), .dp(DP)) ;                  
endmodule
module DigitalClock_Top(
    input   CLK100MHZ,
    input [12:0]SW,
    output [6:0] A2G,
    output [7:0] AN,
    output  DP);



    wire _1s;
    one_min U1(.clk(CLK100MHZ), .onemin(_1m));

    wire [7:0] m_count;
    wire m_out;   
    wire [9:0] m_BCD; 
    min_counter S1(.clk(CLK100MHZ), .clr(SW[0]),.E(SW[1]), .data(SW[7:2]),.time_in(_1m), 
                   .counter(m_count), .time_out(m_out));
   to_BCD S2(.n(m_count), .b(m_BCD));               
 
    wire [7:0] h_count;
    wire h_out;
    wire [9:0] h_BCD; 
    hour_counter M1(.clk(CLK100MHZ), .clr(SW[0]),.E(SW[1]),.data(SW[12:8]),.time_in(m_out), 
                   .counter(h_count), .time_out(h_out));
    to_BCD M2(.n(h_count), .b(h_BCD));
    
       wire [1:0]s;
       clkdiv(.mclk(CLK100MHZ),.clk20(s[1]),.clk19(s[0]));
               
    wire [15:0] x;  
    assign x = {h_BCD[7:0], m_BCD[7:0]};

    x7seg X7(.x(x), .clk(CLK100MHZ), .s(s),
             .a2g(A2G), .an(AN), .dp(DP)) ;                  
endmodule