data/full_repos/permissive/16552133/src/verilog/controller.v
data/verilator_xmls/b35daef9-4264-4bc1-926f-9796b775cd0c.xml
module controller(clk,clr,in_op,c0,c1,c2,c3,c4,en0,en1,en2,en3,en4,en5,en6,en7,s1,s2);

	input clk,clr;
	input [3:0]in_op;
	

	output reg c1,c2,c3;
	output reg [1:0] c0,c4;
	

	output en0,en1,en2,en3,en4,en5,en6,en7;
	reg en0,en1,en2,en3,en4,en5,en6,en7;
	

	output reg s2;
	output reg [2:0]s1;
	

	reg [3:0]opcode;
	reg [5:0]curr_state;
	reg [5:0]next_state;


	`define SIGNALS {c0,c1,c2,c3,c4,en0,en1,en2,en3,en4,en5,en6,en7,s1,s2}
	`define ENABLES {en0,en1,en2,en3,en4,en5,en6,en7}
	
	initial begin
		curr_state = 6'd0;
		next_state = 6'd0;
		opcode = 4'bZZZZ;
		`SIGNALS = 0;
	end
	
	always @(posedge clk) begin

		curr_state = next_state;
	end
	
	always @(posedge clk) begin
		if(clr) begin

			`SIGNALS = 0;
			next_state = 6'b0;
			opcode = 4'bZZZZ;
		end
		else begin
			opcode = in_op;

		case(curr_state)

			6'd0 : begin next_state = 6'd1;
				en3 = 1; c3 = 1;
			end
			6'd1 : begin next_state = 6'd2;
				en3 = 0;
				c0 = 1;
			end
			6'd2 : begin
				c3 = 0;
				c0 = 0;
				next_state = 6'd3;
			end
			

			6'd3 : begin
				case(opcode)
					4'b0000 : begin
					
					end
					4'b0001 : begin
						next_state = 6'd4;
						en3 = 0; c3 = 0;
						en5 = 1; c2 = 1; s2 = 0;
						s1 = 3'b000;
					end
					4'b0010 : begin
						next_state = 6'd4;
						en3 = 0; c3 = 0;
						en5 = 1; c2 = 1; s2 = 0;
						s1 = 3'b001;
					end
					4'b0011 : begin
						en3 = 0; c3 = 0;
						en5 = 1;c0 = 2'b10;
						next_state = 6'd7;
					end
					4'b0100 : begin
						next_state = 6'd15;
						en5 = 1; c2 = 1; s2 = 0;
					end
					4'b0101 : begin
					
					end
					4'bZZZZ : begin

					end
					default : begin

					end
				endcase
			end
			


			6'd4 : begin
				c2 = 0;
				c0 = 2'b00;
				en5 = 0;
				en7 = 1; c4 = 1; en6 = 1; c0 = 0;
				next_state = 6'd5;
			end
			6'd5 : begin
				en7 = 0;
				en4 = 1; c4 = 2;
				next_state = (next_state) + 1;
			end
			6'd6 : begin
				en4 = 0;
				next_state = 6'd63;
			end

			6'd7 : begin

				next_state = 6'd63;
			end
			

			6'd15 : begin
				next_state = 6'd16;
				en5 = 0;
				c2 = 0;
				en3 = 1;
			end
			6'd16 : begin

				en3 = 0;
				c4 = 0; en6 = 1;
				next_state = 6'd17;
			end
			6'd17 : begin next_state = 6'd63;
				c0 = 1;
				c4 = 3; en7 = 1; c1 = 1;
			end
				

			6'd63 : begin next_state = 6'd0;
				`SIGNALS = 0;
			end
			default: begin

			end
		endcase
		end
	end
endmodule
module controller(clk,clr,in_op,c0,c1,c2,c3,c4,en0,en1,en2,en3,en4,en5,en6,en7,s1,s2);


	input clk,clr;
	input [3:0]in_op;
	

	output reg c1,c2,c3;
	output reg [1:0] c0,c4;
	

	output en0,en1,en2,en3,en4,en5,en6,en7;
	reg en0,en1,en2,en3,en4,en5,en6,en7;
	

	output reg s2;
	output reg [2:0]s1;
	

	reg [3:0]opcode;
	reg [5:0]curr_state;
	reg [5:0]next_state;


	`define SIGNALS {c0,c1,c2,c3,c4,en0,en1,en2,en3,en4,en5,en6,en7,s1,s2}
	`define ENABLES {en0,en1,en2,en3,en4,en5,en6,en7}
	
	initial begin
		curr_state = 6'd0;
		next_state = 6'd0;
		opcode = 4'bZZZZ;
		`SIGNALS = 0;
	end
	
	always @(posedge clk) begin

		curr_state = next_state;
	end
	
	always @(posedge clk) begin
		if(clr) begin

			`SIGNALS = 0;
			next_state = 6'b0;
			opcode = 4'bZZZZ;
		end
		else begin
			opcode = in_op;

		case(curr_state)

			6'd0 : begin next_state = 6'd1;
				en3 = 1; c3 = 1;
			end
			6'd1 : begin next_state = 6'd2;
				en3 = 0;
				c0 = 1;
			end
			6'd2 : begin
				c3 = 0;
				c0 = 0;
				next_state = 6'd3;
			end
			

			6'd3 : begin
				case(opcode)
					4'b0000 : begin
					
					end
					4'b0001 : begin
						next_state = 6'd4;
						en3 = 0; c3 = 0;
						en5 = 1; c2 = 1; s2 = 0;
						s1 = 3'b000;
					end
					4'b0010 : begin
						next_state = 6'd4;
						en3 = 0; c3 = 0;
						en5 = 1; c2 = 1; s2 = 0;
						s1 = 3'b001;
					end
					4'b0011 : begin
						en3 = 0; c3 = 0;
						en5 = 1;c0 = 2'b10;
						next_state = 6'd7;
					end
					4'b0100 : begin
						next_state = 6'd15;
						en5 = 1; c2 = 1; s2 = 0;
					end
					4'b0101 : begin
					
					end
					4'bZZZZ : begin

					end
					default : begin

					end
				endcase
			end
			


			6'd4 : begin
				c2 = 0;
				c0 = 2'b00;
				en5 = 0;
				en7 = 1; c4 = 1; en6 = 1; c0 = 0;
				next_state = 6'd5;
			end
			6'd5 : begin
				en7 = 0;
				en4 = 1; c4 = 2;
				next_state = (next_state) + 1;
			end
			6'd6 : begin
				en4 = 0;
				next_state = 6'd63;
			end

			6'd7 : begin

				next_state = 6'd63;
			end
			

			6'd15 : begin
				next_state = 6'd16;
				en5 = 0;
				c2 = 0;
				en3 = 1;
			end
			6'd16 : begin

				en3 = 0;
				c4 = 0; en6 = 1;
				next_state = 6'd17;
			end
			6'd17 : begin next_state = 6'd63;
				c0 = 1;
				c4 = 3; en7 = 1; c1 = 1;
			end
				

			6'd63 : begin next_state = 6'd0;
				`SIGNALS = 0;
			end
			default: begin

			end
		endcase
		end
	end
endmodule