data/full_repos/permissive/166008742/src/spi_slave.v
data/verilator_xmls/33423f00-1462-45c8-9289-0dee0971ba65.xml
module spi_slave
(
    input            reset,

    input            ss,
    input            sclk,
    input            mosi,
    output           miso,

    input            msb_first,
    input            txen,
    input      [7:0] txdata,
    output reg [7:0] rxdata,
    output reg       done
);

    reg [7:0] treg, rreg;
    reg [3:0] nb;
    wire sout;
  
    assign sout = msb_first ? treg[7] : treg[0];
    assign miso = (!ss && txen) ? sout : 1'bz;



    always @(posedge sclk or posedge reset) begin
        if (reset) begin
            rreg   = 8'h00;
            rxdata = 8'h00;
            done   = 0;
            nb     = 0;
        end
        else if (!ss) begin 
            if(msb_first) begin
                rreg = {rreg[6:0], mosi};
            end
            else begin
                rreg = {mosi, rreg[7:1]};
            end  


            nb = nb + 1;
            if (nb != 8) begin
                done = 0;
            end
            else begin
                rxdata = rreg;
                done   = 1;
                nb     = 0;
            end
        end
    end


    always @(negedge sclk or posedge reset) begin
        if (reset) begin
            treg <= 8'hFF;
        end
        else if (!ss) begin			
            if (nb == 0) begin
                treg <= txdata;
            end
            else if (msb_first) begin
                treg <= {treg[6:0], 1'b1};
            end
            else begin
                treg <= {1'b1, treg[7:1]};
            end
        end
    end

endmodule
module spi_slave
(
    input            reset,

    input            ss,
    input            sclk,
    input            mosi,
    output           miso,

    input            msb_first,
    input            txen,
    input      [7:0] txdata,
    output reg [7:0] rxdata,
    output reg       done
);


    reg [7:0] treg, rreg;
    reg [3:0] nb;
    wire sout;
  
    assign sout = msb_first ? treg[7] : treg[0];
    assign miso = (!ss && txen) ? sout : 1'bz;



    always @(posedge sclk or posedge reset) begin
        if (reset) begin
            rreg   = 8'h00;
            rxdata = 8'h00;
            done   = 0;
            nb     = 0;
        end
        else if (!ss) begin 
            if(msb_first) begin
                rreg = {rreg[6:0], mosi};
            end
            else begin
                rreg = {mosi, rreg[7:1]};
            end  


            nb = nb + 1;
            if (nb != 8) begin
                done = 0;
            end
            else begin
                rxdata = rreg;
                done   = 1;
                nb     = 0;
            end
        end
    end


    always @(negedge sclk or posedge reset) begin
        if (reset) begin
            treg <= 8'hFF;
        end
        else if (!ss) begin			
            if (nb == 0) begin
                treg <= txdata;
            end
            else if (msb_first) begin
                treg <= {treg[6:0], 1'b1};
            end
            else begin
                treg <= {1'b1, treg[7:1]};
            end
        end
    end

endmodule