data/full_repos/permissive/210123090/code/fm_xmit.v
 line:91: before: "real"
1: b'%Warning-REALCVT: data/full_repos/permissive/210123090/code/fm_xmit.v:92: Implicit conversion of real to integer\n   localparam [12:0] aTHECENTER = fTHECENTER;\n                                  ^~~~~~~~~~\n                  ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:338: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf0ca)) cmbb( .O(b), .I3(a[1]), .I2(a[0]), .I1(d[1]), .I0(d[0]));\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210123090/code,data/full_repos/permissive/210123090/SB_LUT4\n             data/full_repos/permissive/210123090/code,data/full_repos/permissive/210123090/SB_LUT4.v\n             data/full_repos/permissive/210123090/code,data/full_repos/permissive/210123090/SB_LUT4.sv\n             SB_LUT4\n             SB_LUT4.v\n             SB_LUT4.sv\n             obj_dir/SB_LUT4\n             obj_dir/SB_LUT4.v\n             obj_dir/SB_LUT4.sv\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:339: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hcaf0)) cmbo( .O(o), .I3(a[1]), .I2(b),    .I1(d[3]), .I0(d[2]));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:311: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'h0f00)) cmb_tap0(.O(tap0),.I3(dummy),.I2(clk), .I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:312: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap1(.O(tap1),.I3(dummy),.I2(tap0),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:313: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap2(.O(tap2),.I3(dummy),.I2(tap1),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:314: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap3(.O(tap3),.I3(dummy),.I2(tap2),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:315: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap4(.O(tap4),.I3(dummy),.I2(tap3),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:316: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap5(.O(tap5),.I3(dummy),.I2(tap4),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:317: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap6(.O(tap6),.I3(dummy),.I2(tap5),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:318: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap7(.O(clk), .I3(dummy),.I2(tap6),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/210123090/code/fm_xmit.v:223: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'cy\' generates 1 bits.\n                                                                       : ... In instance top.i_acc\n      acc[12:7]     <= acc[12:7] + addend[12:7] + cy;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/210123090/code/fm_xmit.v:92: Operator VAR \'aTHECENTER\' expects 13 bits on the Initial value, but Initial value\'s CONST \'32\'hd07\' generates 32 bits.\n                                                                      : ... In instance top\n   localparam [12:0] aTHECENTER = fTHECENTER;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:145: Cannot find file containing module: \'SB_DFF\'\n   SB_DFF r_buffermsb( .Q(buffermsb), .C(clk), .D(msb)); \n   ^~~~~~\n%Error: Exiting due to 11 error(s), 3 warning(s)\n'
module top #
  ( parameter
    TIMING = 0,
    CLKFRQ  = 226000000,
    CENTER  =  92000000  
    )
   (
    input        dummy,
    input        CLK_I,
    output       antennae,
    output [3:0] led
    );
   wire          clk;
   wire          msb;
   wire          buffermsb;
   reg [14:0]    cnt;
   reg           doshift;
   reg [12:0]    addend;
   wire [7:0]    d;
   reg [6:0]     adr;
   reg           msg;
   

   always @(posedge CLK_I)
      {doshift,cnt} <= cnt + 1;
   
   m_messagerom i_messagerom(.d(d[7:0]),.adr(adr[6:3])); 

   wire          cmbmsg;
   m_mux8to1 i_mux8(.o(cmbmsg),.d(d), .a(adr[2:0]));
   always @(posedge CLK_I)
     msg <= cmbmsg;
   
   wire [6:0]    cmbadr;
   wire          reloadadr;
   assign {reloadadr,cmbadr} = adr + 1;
   
   always @(posedge CLK_I) 
     if ( doshift & reloadadr ) 
       adr <= 'ha;
     else if ( doshift ) 
       adr <= cmbadr;


   
   m_freeclock instclk (.clk(clk),.dummy(dummy)); 
   

   localparam real   fTHECENTER  = 8192.0 * CENTER / CLKFRQ;
   localparam [12:0] aTHECENTER = fTHECENTER;
   localparam [12:0] THECENTER  = (aTHECENTER & 13'h1ffc) + 1;
   localparam [12:0] THEHIGH    = THECENTER+1;

   localparam [12:0] THELOW     = THECENTER-1;


   generate
      if ( TIMING ) begin
         always @(posedge clk) begin
            addend <= 13'h1;
         end
      end else begin
         always @(posedge clk) begin 
            addend[1:0]  <= {(msg & cnt[8]),~msg};
            addend[12:2] <= THECENTER[12:2];
         end
      end
   endgenerate
   m_phaseaccumulator i_acc(.msb(msb), .clk(clk), .addend(addend)); 

   


   wire            calibrationaid;
   generate
      if ( TIMING ) begin
         reg [19:0] timingcnt;
         always @(posedge msb)
           timingcnt <= timingcnt + 1;
         assign calibrationaid = ~timingcnt[19];
      end else begin
         assign calibrationaid = 1'b0;
      end
   endgenerate
   
   SB_DFF r_buffermsb( .Q(buffermsb), .C(clk), .D(msb)); 
   assign antennae = buffermsb;   
   assign led[3]   = msg;
   assign led[2]   = 1'b0;
   assign led[1]   = calibrationaid;
   assign led[0]   = reloadadr;


endmodule
module top #
  ( parameter
    TIMING = 0,
    CLKFRQ  = 226000000,
    CENTER  =  92000000  
    )
   (
    input        dummy,
    input        CLK_I,
    output       antennae,
    output [3:0] led
    );

   wire          clk;
   wire          msb;
   wire          buffermsb;
   reg [14:0]    cnt;
   reg           doshift;
   reg [12:0]    addend;
   wire [7:0]    d;
   reg [6:0]     adr;
   reg           msg;
   

   always @(posedge CLK_I)
      {doshift,cnt} <= cnt + 1;
   
   m_messagerom i_messagerom(.d(d[7:0]),.adr(adr[6:3])); 

   wire          cmbmsg;
   m_mux8to1 i_mux8(.o(cmbmsg),.d(d), .a(adr[2:0]));
   always @(posedge CLK_I)
     msg <= cmbmsg;
   
   wire [6:0]    cmbadr;
   wire          reloadadr;
   assign {reloadadr,cmbadr} = adr + 1;
   
   always @(posedge CLK_I) 
     if ( doshift & reloadadr ) 
       adr <= 'ha;
     else if ( doshift ) 
       adr <= cmbadr;


   
   m_freeclock instclk (.clk(clk),.dummy(dummy)); 
   

   localparam real   fTHECENTER  = 8192.0 * CENTER / CLKFRQ;
   localparam [12:0] aTHECENTER = fTHECENTER;
   localparam [12:0] THECENTER  = (aTHECENTER & 13'h1ffc) + 1;
   localparam [12:0] THEHIGH    = THECENTER+1;

   localparam [12:0] THELOW     = THECENTER-1;


   generate
      if ( TIMING ) begin
         always @(posedge clk) begin
            addend <= 13'h1;
         end
      end else begin
         always @(posedge clk) begin 
            addend[1:0]  <= {(msg & cnt[8]),~msg};
            addend[12:2] <= THECENTER[12:2];
         end
      end
   endgenerate
   m_phaseaccumulator i_acc(.msb(msb), .clk(clk), .addend(addend)); 

   


   wire            calibrationaid;
   generate
      if ( TIMING ) begin
         reg [19:0] timingcnt;
         always @(posedge msb)
           timingcnt <= timingcnt + 1;
         assign calibrationaid = ~timingcnt[19];
      end else begin
         assign calibrationaid = 1'b0;
      end
   endgenerate
   
   SB_DFF r_buffermsb( .Q(buffermsb), .C(clk), .D(msb)); 
   assign antennae = buffermsb;   
   assign led[3]   = msg;
   assign led[2]   = 1'b0;
   assign led[1]   = calibrationaid;
   assign led[0]   = reloadadr;


endmodule