data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v
Syntax Error
1: b'%Error: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:34: Cannot find file containing module: \'LOD_N\'\nLOD_N #(.N(N)) uut (.in(LOD_in), .out(Lshift));\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/LOD_N\n             data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/LOD_N.v\n             data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor,data/full_repos/permissive/112176817/LOD_N.sv\n             LOD_N\n             LOD_N.v\n             LOD_N.sv\n             obj_dir/LOD_N\n             obj_dir/LOD_N.v\n             obj_dir/LOD_N.sv\n%Error: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:37: Cannot find file containing module: \'DSR_left_N_S\'\nDSR_left_N_S #(.N(N), .S(Bs)) ls (.a(LOD_in),.b(Lshift),.c(mant_tmp));\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:39: Operator SUB expects 32 or 6 bits on the RHS, but RHS\'s VARREF \'Lshift\' generates 4 bits.\n                                                                                                       : ... In instance FP_to_posit\nwire [E:0] exp = {exp_in[E-1:1], exp_in[0] | (~|exp_in)} - BIAS - Lshift;\n                                                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:44: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s COND generates 7 bits.\n                                                                                                       : ... In instance FP_to_posit\nwire [E-es-1:0] r_o = (~exp[E] || (exp[E] & |exp_N[es-1:0])) ? {{Bs{1\'b0}},exp_N[E-1:es]} + 1\'b1 : {{Bs{1\'b0}},exp_N[E-1:es]};\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:54: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_o\' generates 3 bits.\n                                                                                                       : ... In instance FP_to_posit\n else   assign diff_b = r_o;\n                      ^\n%Error: data/full_repos/permissive/112176817/Floating-Point_to_Posit_Convertor/FP_to_Posit.v:56: Cannot find file containing module: \'DSR_right_N_S\'\nDSR_right_N_S #(.N(2*N), .S(Bs)) dsr2 (.a(tmp_o), .b(diff_b), .c(tmp1_o));\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction
function [31:0] log2;

input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction