data/full_repos/permissive/161029703/src/clk_ctrl.v
data/verilator_xmls/044cc724-b485-4ef1-b634-0cff320fe061.xml
module clk_ctrl(

            rst_out_n,

            clk,
            rst_in_n);

input wire clk;
input wire rst_in_n;
output wire rst_out_n;

reg[2:0] shifter;
assign rst_out_n = shifter[2];
always @(posedge clk or negedge rst_in_n) begin
    if (!rst_in_n) begin
        shifter <= 3'b000;
    end
    else begin
        shifter <= {shifter[1:0], 1'b1};
    end
end

endmodule
module clk_ctrl(

            rst_out_n,

            clk,
            rst_in_n);


input wire clk;
input wire rst_in_n;
output wire rst_out_n;

reg[2:0] shifter;
assign rst_out_n = shifter[2];
always @(posedge clk or negedge rst_in_n) begin
    if (!rst_in_n) begin
        shifter <= 3'b000;
    end
    else begin
        shifter <= {shifter[1:0], 1'b1};
    end
end

endmodule