data/full_repos/permissive/173003307/src/RAM.v
1: b'%Warning-UNSIGNED: data/full_repos/permissive/173003307/src/RAM.v:54: Comparison is constant due to unsigned arithmetic\n                                                                    : ... In instance RAM\n        if((BUS_ADDR >= RAMBaseAddr) & (BUS_ADDR < RAMBaseAddr + RAMSize))  \n                     ^~\n                   ... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module RAM(

                input CLK,

                inout [7:0] BUS_DATA,
                input [7:0] BUS_ADDR,
                input BUS_WE
                );
                
    parameter RAMBaseAddr  = 0;
    parameter RAMAddrWidth = 7;
    parameter RAMSize      = 128;
    

    wire [7:0] BufferedBusData;
    reg [7:0] Out;
    reg RAMBusWE;
    

    assign BUS_DATA = (RAMBusWE) ? Out : 8'hZZ;
    assign BufferedBusData = BUS_DATA;
    

    reg [7:0] Mem [2**RAMAddrWidth-1:0];
    

        initial $readmemh("../additional_sources/full_ram.txt", Mem);
    

    always@(posedge CLK) 
    begin
        if((BUS_ADDR >= RAMBaseAddr) & (BUS_ADDR < RAMBaseAddr + RAMSize))  
        begin
            if(BUS_WE) 
            begin
                Mem[BUS_ADDR[6:0]] <= BufferedBusData;
                RAMBusWE <= 1'b0;
            end 
            else
                RAMBusWE <= 1'b1;
        end 
        
        else
            RAMBusWE <= 1'b0;
            
        Out <= Mem[BUS_ADDR[6:0]];
    end
    
    endmodule
module RAM(

                input CLK,

                inout [7:0] BUS_DATA,
                input [7:0] BUS_ADDR,
                input BUS_WE
                );

                
    parameter RAMBaseAddr  = 0;
    parameter RAMAddrWidth = 7;
    parameter RAMSize      = 128;
    

    wire [7:0] BufferedBusData;
    reg [7:0] Out;
    reg RAMBusWE;
    

    assign BUS_DATA = (RAMBusWE) ? Out : 8'hZZ;
    assign BufferedBusData = BUS_DATA;
    

    reg [7:0] Mem [2**RAMAddrWidth-1:0];
    

        initial $readmemh("../additional_sources/full_ram.txt", Mem);
    

    always@(posedge CLK) 
    begin
        if((BUS_ADDR >= RAMBaseAddr) & (BUS_ADDR < RAMBaseAddr + RAMSize))  
        begin
            if(BUS_WE) 
            begin
                Mem[BUS_ADDR[6:0]] <= BufferedBusData;
                RAMBusWE <= 1'b0;
            end 
            else
                RAMBusWE <= 1'b1;
        end 
        
        else
            RAMBusWE <= 1'b0;
            
        Out <= Mem[BUS_ADDR[6:0]];
    end
    
    endmodule