data/full_repos/permissive/119758565/CPU.v
1: b"%Error: data/full_repos/permissive/119758565/CPU.v:58: syntax error, unexpected '(', expecting IDENTIFIER\n  orGate(CtoAReg0, CtoAReg1, CtoAReg);\n         ^~~~~~~~\n%Error: data/full_repos/permissive/119758565/CPU.v:72: syntax error, unexpected '(', expecting IDENTIFIER\n  andGate(Cinst, instruction[12], CtoMuxALU);\n          ^~~~~\n%Error: data/full_repos/permissive/119758565/CPU.v:86: syntax error, unexpected '(', expecting IDENTIFIER\n  andGate(jmpEQ, zr, CtoPC0);\n          ^~~~~\n%Error: data/full_repos/permissive/119758565/CPU.v:89: syntax error, unexpected '(', expecting IDENTIFIER\n  notGate(ng, notNg);\n          ^~\n%Error: data/full_repos/permissive/119758565/CPU.v:94: syntax error, unexpected '(', expecting IDENTIFIER\n  orGate(CtoPC0, CtoPC1, Ctp01);\n         ^~~~~~\n%Error: Exiting due to 5 error(s)\n"
module CPU(
    input [15:0] instruction,
    input [15:0] inM,
    input rst,
    output [15:0] outM,
    output writeM,
    output [14:0] addressM,
    output [14:0] pc,
	 output [15:0] DOut,
	 output reg [15:0] OutR,
    input clk

    );
	 
	 wire CtoMuxAReg, CtoAReg, CtoDReg, CtoALU;
	 wire [15:0] MuxAReg;
	 wire [15:0] AM;
	 wire [15:0] D;
	 wire [15:0] A;
	 wire CtoPC, CtoMuxALU, Cinst;
	 wire jmpGT, jmpLT, jmpEQ, zr, ng;
	 
	 wire CtoAReg0, CtoAReg1;
	 orGate(CtoAReg0, CtoAReg1, CtoAReg);

	 notGate(instruction[15], CtoMuxAReg);
	 notGate(instruction[15], CtoAReg0);

	 andGate(instruction[15], instruction[14], Cinst);
	 
	 always @(negedge clk)
	 begin
	   if (~instruction[13] && Cinst)
		  OutR = D;
	 end
	 

	 andGate(Cinst, instruction[12], CtoMuxALU);

	 andGate(Cinst, instruction[5], CtoAReg1);

	 andGate(Cinst, instruction[4], CtoDReg);

	 andGate(Cinst, instruction[3], writeM);

	 andGate(Cinst, instruction[2], jmpLT);
	 andGate(Cinst, instruction[1], jmpEQ);
	 andGate(Cinst, instruction[0], jmpGT);
	 

	 wire CtoPC0, CtoPC1, CtoPC2;
	 andGate(jmpEQ, zr, CtoPC0);

	 wire notNg;
	 notGate(ng, notNg);
	 andGate(notNg, jmpGT, CtoPC1);

	 andGate(ng, jmpLT, CtoPC2);
	 wire Ctp01;
	 orGate(CtoPC0, CtoPC1, Ctp01);
	 orGate(Ctp01, CtoPC2, CtoPC);

	 ALU(.x(D), .y(AM), .control(instruction[11:6]), .out(outM), .zr(zr), .ng(ng));
	 

	 Register(.data(MuxAReg), .out(addressM), .clk(clk), .load(CtoAReg));
	 Register(.data(outM), .out(D), .clk(clk), .load(CtoDReg));
	 PC(.in(addressM), .load(CtoPC), .rst(rst), .clk(~clk), .inc(1), .out(pc));
	 

	 Mux16(outM, instruction, CtoMuxAReg, MuxAReg);
	 Mux16(addressM, inM, CtoMuxALU, AM);

    assign DOut = D;
endmodule
module CPU(
    input [15:0] instruction,
    input [15:0] inM,
    input rst,
    output [15:0] outM,
    output writeM,
    output [14:0] addressM,
    output [14:0] pc,
	 output [15:0] DOut,
	 output reg [15:0] OutR,
    input clk

    );

	 
	 wire CtoMuxAReg, CtoAReg, CtoDReg, CtoALU;
	 wire [15:0] MuxAReg;
	 wire [15:0] AM;
	 wire [15:0] D;
	 wire [15:0] A;
	 wire CtoPC, CtoMuxALU, Cinst;
	 wire jmpGT, jmpLT, jmpEQ, zr, ng;
	 
	 wire CtoAReg0, CtoAReg1;
	 orGate(CtoAReg0, CtoAReg1, CtoAReg);

	 notGate(instruction[15], CtoMuxAReg);
	 notGate(instruction[15], CtoAReg0);

	 andGate(instruction[15], instruction[14], Cinst);
	 
	 always @(negedge clk)
	 begin
	   if (~instruction[13] && Cinst)
		  OutR = D;
	 end
	 

	 andGate(Cinst, instruction[12], CtoMuxALU);

	 andGate(Cinst, instruction[5], CtoAReg1);

	 andGate(Cinst, instruction[4], CtoDReg);

	 andGate(Cinst, instruction[3], writeM);

	 andGate(Cinst, instruction[2], jmpLT);
	 andGate(Cinst, instruction[1], jmpEQ);
	 andGate(Cinst, instruction[0], jmpGT);
	 

	 wire CtoPC0, CtoPC1, CtoPC2;
	 andGate(jmpEQ, zr, CtoPC0);

	 wire notNg;
	 notGate(ng, notNg);
	 andGate(notNg, jmpGT, CtoPC1);

	 andGate(ng, jmpLT, CtoPC2);
	 wire Ctp01;
	 orGate(CtoPC0, CtoPC1, Ctp01);
	 orGate(Ctp01, CtoPC2, CtoPC);

	 ALU(.x(D), .y(AM), .control(instruction[11:6]), .out(outM), .zr(zr), .ng(ng));
	 

	 Register(.data(MuxAReg), .out(addressM), .clk(clk), .load(CtoAReg));
	 Register(.data(outM), .out(D), .clk(clk), .load(CtoDReg));
	 PC(.in(addressM), .load(CtoPC), .rst(rst), .clk(~clk), .inc(1), .out(pc));
	 

	 Mux16(outM, instruction, CtoMuxAReg, MuxAReg);
	 Mux16(addressM, inM, CtoMuxALU, AM);

    assign DOut = D;
endmodule