data/full_repos/permissive/135077285/if_id.v
 line:16: before: "&&"
1: b'%Warning-LITENDIAN: data/full_repos/permissive/135077285/if_id.v:7: Little bit endian vector: MSB < LSB of bit range: 0:31\n  output reg [0:31] outPc,\n             ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/135077285/if_id.v:8: Little bit endian vector: MSB < LSB of bit range: 0:31\n  output reg [0:31] outInstruction\n             ^\n%Error: Exiting due to 2 warning(s)\n'
module ifId(
  input wire clock,
  input hzdWrite,
  input [31:0] instruction,
  input [31:0] pc,

  output reg [0:31] outPc,
  output reg [0:31] outInstruction
);

  initial begin
    outPc <= 0;
    outInstruction <= 0;
  end

  always @(posedge clock && hzdWrite) begin
    outInstruction <= instruction;
    outPc <= pc;
  end
endmodule
module ifId(
  input wire clock,
  input hzdWrite,
  input [31:0] instruction,
  input [31:0] pc,

  output reg [0:31] outPc,
  output reg [0:31] outInstruction
);


  initial begin
    outPc <= 0;
    outInstruction <= 0;
  end

  always @(posedge clock && hzdWrite) begin
    outInstruction <= instruction;
    outPc <= pc;
  end
endmodule