data/full_repos/permissive/20101677/vcache.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/20101677/vcache.v:100: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'counter_line\' generates 17 bits.\n                                                                : ... In instance vcache\n assign wb_adr_o = vram_adr_base + (counter_line + counter) * 4;\n                                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20101677/vcache.v:100: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'counter\' generates 17 bits.\n                                                                : ... In instance vcache\n assign wb_adr_o = vram_adr_base + (counter_line + counter) * 4;\n                                                 ^\n%Error: data/full_repos/permissive/20101677/vcache.v:196: Cannot find file containing module: \'vcache_fifo\'\n vcache_fifo fifo0 (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20101677,data/full_repos/permissive/20101677/vcache_fifo\n             data/full_repos/permissive/20101677,data/full_repos/permissive/20101677/vcache_fifo.v\n             data/full_repos/permissive/20101677,data/full_repos/permissive/20101677/vcache_fifo.sv\n             vcache_fifo\n             vcache_fifo.v\n             vcache_fifo.sv\n             obj_dir/vcache_fifo\n             obj_dir/vcache_fifo.v\n             obj_dir/vcache_fifo.sv\n%Error: data/full_repos/permissive/20101677/vcache.v:215: Cannot find file containing module: \'vga\'\n   vga vga0(\n   ^~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module vcache(

   rgb, hsync, vsync, wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o,
   wb_sel_o, wb_dat_o,

   wb_clk_i, wb_rst_i, vga_clk, wb_ack_i, wb_err_i, wb_rty_i,
   wb_dat_i
   );
	
   input wire  wb_clk_i;
   input wire  wb_rst_i;

   input wire  vga_clk;
   output  [7:0] rgb;
   output      hsync;
   output      vsync;


   input wire  wb_ack_i;
   input wire  wb_err_i;
   input wire  wb_rty_i;
   input wire [31:0] wb_dat_i;
   output        wb_cyc_o;
   output  [31:0] wb_adr_o;
   output        wb_stb_o;
   output        wb_we_o;
   output  [3:0]  wb_sel_o;
   output  [31:0] wb_dat_o;
	
	wire  [9:0]    x;
   wire  [9:0]    y;
   wire     ve;

	parameter vram_adr_base = 'hf80000;
	



	wire [7:0] dout_rgb;
	assign rgb = ve ? dout_rgb : 0;



	assign wb_sel_o = 4'b1111;
	assign wb_we_o = 0;



	`define FILL  1
	`define IDLE  0
	reg state;
	reg [16:0] counter, counter_line;
	assign wb_adr_o = vram_adr_base + (counter_line + counter) * 4;
	assign wb_cyc_o = (state == `IDLE)? 0 : 1;
	assign wb_stb_o = ((state == `IDLE)? 0 : 1) & !wb_ack_i;

	always @(posedge wb_clk_i) begin
		if (wb_ack_i) begin
			if (counter_line == 159) begin
				state <= `IDLE;
				counter_line <= 0;
				counter <= counter + 160;
			end
			else begin
				counter_line <= counter_line + 1;
			end
		end
		if (y >= 0 && y < 480) begin
			case(state)
				`IDLE: begin 
					if (newline) state <= `FILL;
				end
				`FILL: begin
					
				end
			endcase
		end
		else begin
			counter <= 0;
			counter_line <= 0;
		end
	end


 wire line_rst = x == 'd640;
 wire newline, newfield;
	vcache_fifo fifo0 (
  .wr_clk(wb_clk_i),
  .rd_clk(vga_clk),
  .rst(x == 640 || newfield),

	.din(wb_dat_i),

  .wr_en(wb_ack_i),
  .rd_en(ve),
  .dout(dout_rgb)






	);

   wire clk_p = vga_clk;
   vga vga0(
	    .rst			(~wb_rst_i),


	    .hsync			(hsync),
	    .vsync			(vsync),
	    .x				(x[9:0]),
	    .y				(y[9:0]),
	    .ve				(ve),
		 .newline		(newline),
		 .newfield		(newfield),

	    .clk_p			(clk_p)
   );
	
endmodule
module vcache(

   rgb, hsync, vsync, wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o,
   wb_sel_o, wb_dat_o,

   wb_clk_i, wb_rst_i, vga_clk, wb_ack_i, wb_err_i, wb_rty_i,
   wb_dat_i
   );

	
   input wire  wb_clk_i;
   input wire  wb_rst_i;

   input wire  vga_clk;
   output  [7:0] rgb;
   output      hsync;
   output      vsync;


   input wire  wb_ack_i;
   input wire  wb_err_i;
   input wire  wb_rty_i;
   input wire [31:0] wb_dat_i;
   output        wb_cyc_o;
   output  [31:0] wb_adr_o;
   output        wb_stb_o;
   output        wb_we_o;
   output  [3:0]  wb_sel_o;
   output  [31:0] wb_dat_o;
	
	wire  [9:0]    x;
   wire  [9:0]    y;
   wire     ve;

	parameter vram_adr_base = 'hf80000;
	



	wire [7:0] dout_rgb;
	assign rgb = ve ? dout_rgb : 0;



	assign wb_sel_o = 4'b1111;
	assign wb_we_o = 0;



	`define FILL  1
	`define IDLE  0
	reg state;
	reg [16:0] counter, counter_line;
	assign wb_adr_o = vram_adr_base + (counter_line + counter) * 4;
	assign wb_cyc_o = (state == `IDLE)? 0 : 1;
	assign wb_stb_o = ((state == `IDLE)? 0 : 1) & !wb_ack_i;

	always @(posedge wb_clk_i) begin
		if (wb_ack_i) begin
			if (counter_line == 159) begin
				state <= `IDLE;
				counter_line <= 0;
				counter <= counter + 160;
			end
			else begin
				counter_line <= counter_line + 1;
			end
		end
		if (y >= 0 && y < 480) begin
			case(state)
				`IDLE: begin 
					if (newline) state <= `FILL;
				end
				`FILL: begin
					
				end
			endcase
		end
		else begin
			counter <= 0;
			counter_line <= 0;
		end
	end


 wire line_rst = x == 'd640;
 wire newline, newfield;
	vcache_fifo fifo0 (
  .wr_clk(wb_clk_i),
  .rd_clk(vga_clk),
  .rst(x == 640 || newfield),

	.din(wb_dat_i),

  .wr_en(wb_ack_i),
  .rd_en(ve),
  .dout(dout_rgb)






	);

   wire clk_p = vga_clk;
   vga vga0(
	    .rst			(~wb_rst_i),


	    .hsync			(hsync),
	    .vsync			(vsync),
	    .x				(x[9:0]),
	    .y				(y[9:0]),
	    .ve				(ve),
		 .newline		(newline),
		 .newfield		(newfield),

	    .clk_p			(clk_p)
   );
	
endmodule