data/full_repos/permissive/143278/ivltests/implicit_cast1.v
 line:7: before: "src_u2"
1: b'%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:53: Implicit conversion of real to integer\n  dst_u2s = src_r;  $display("%d", dst_u2s); if (dst_u2s !== 4\'d9) failed = 1;\n            ^~~~~\n                  ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:54: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u2\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u2s = src_u2; $display("%d", dst_u2s); if (dst_u2s !== 4\'d7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:55: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s2\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u2s = src_s2; $display("%d", dst_u2s); if (dst_u2s !== 4\'d9) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:56: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u4\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u2s = src_u4; $display("%d", dst_u2s); if (dst_u2s !== 4\'d7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:57: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s4\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u2s = src_s4; $display("%d", dst_u2s); if (dst_u2s !== 4\'d9) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:58: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_ux\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u2s = src_ux; $display("%d", dst_u2s); if (dst_u2s !== 4\'d7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:59: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_sx\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u2s = src_sx; $display("%d", dst_u2s); if (dst_u2s !== 4\'d7) failed = 1;\n          ^\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:62: Implicit conversion of real to integer\n  dst_s2s = src_r;  $display("%d", dst_s2s); if (dst_s2s !== -4\'sd7) failed = 1;\n            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:63: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u2\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s2s = src_u2; $display("%d", dst_s2s); if (dst_s2s !==  4\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:64: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s2\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s2s = src_s2; $display("%d", dst_s2s); if (dst_s2s !== -4\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:65: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u4\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s2s = src_u4; $display("%d", dst_s2s); if (dst_s2s !==  4\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:66: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s4\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s2s = src_s4; $display("%d", dst_s2s); if (dst_s2s !== -4\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:67: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_ux\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s2s = src_ux; $display("%d", dst_s2s); if (dst_s2s !==  4\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:68: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_sx\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s2s = src_sx; $display("%d", dst_s2s); if (dst_s2s !==  4\'sd7) failed = 1;\n          ^\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:71: Implicit conversion of real to integer\n  dst_u2l = src_r;  $display("%d", dst_u2l); if (dst_u2l !== 12\'d4089) failed = 1;\n            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:72: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u2\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u2l = src_u2; $display("%d", dst_u2l); if (dst_u2l !== 12\'d7)    failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:73: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s2\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u2l = src_s2; $display("%d", dst_u2l); if (dst_u2l !== 12\'d4089) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:74: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u4\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u2l = src_u4; $display("%d", dst_u2l); if (dst_u2l !== 12\'d7)    failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:75: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s4\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u2l = src_s4; $display("%d", dst_u2l); if (dst_u2l !== 12\'d4089) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:76: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_ux\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u2l = src_ux; $display("%b", dst_u2l); if (dst_u2l !== 12\'b000000000111) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:77: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_sx\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u2l = src_sx; $display("%b", dst_u2l); if (dst_u2l !== 12\'b000000000111) failed = 1;\n          ^\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:80: Implicit conversion of real to integer\n  dst_s2l = src_r;  $display("%d", dst_s2l); if (dst_s2l !== -12\'sd7) failed = 1;\n            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:81: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u2\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s2l = src_u2; $display("%d", dst_s2l); if (dst_s2l !==  12\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:82: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s2\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s2l = src_s2; $display("%d", dst_s2l); if (dst_s2l !== -12\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:83: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u4\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s2l = src_u4; $display("%d", dst_s2l); if (dst_s2l !==  12\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:84: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s4\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s2l = src_s4; $display("%d", dst_s2l); if (dst_s2l !== -12\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:85: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_ux\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s2l = src_ux; $display("%b", dst_s2l); if (dst_s2l !== 12\'b000000000111) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:86: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_sx\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s2l = src_sx; $display("%b", dst_s2l); if (dst_s2l !== 12\'b000000000111) failed = 1;\n          ^\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:89: Implicit conversion of real to integer\n  dst_u4s = src_r;  $display("%d", dst_u4s); if (dst_u4s !== 4\'d9) failed = 1;\n            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:90: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u2\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u4s = src_u2; $display("%d", dst_u4s); if (dst_u4s !== 4\'d7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:91: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s2\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u4s = src_s2; $display("%d", dst_u4s); if (dst_u4s !== 4\'d9) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:92: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u4\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u4s = src_u4; $display("%d", dst_u4s); if (dst_u4s !== 4\'d7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:93: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s4\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u4s = src_s4; $display("%d", dst_u4s); if (dst_u4s !== 4\'d9) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:94: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_ux\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u4s = src_ux; $display("%d", dst_u4s); if (dst_u4s !== 4\'d7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:95: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_sx\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_u4s = src_sx; $display("%d", dst_u4s); if (dst_u4s !== 4\'d7) failed = 1;\n          ^\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:98: Implicit conversion of real to integer\n  dst_s4s = src_r;  $display("%d", dst_s4s); if (dst_s4s !== -4\'sd7) failed = 1;\n            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:99: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u2\' generates 8 bits.\n                                                                              : ... In instance implicit_cast\n  dst_s4s = src_u2; $display("%d", dst_s4s); if (dst_s4s !==  4\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:100: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s2\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_s4s = src_s2; $display("%d", dst_s4s); if (dst_s4s !== -4\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:101: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u4\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_s4s = src_u4; $display("%d", dst_s4s); if (dst_s4s !==  4\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:102: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s4\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_s4s = src_s4; $display("%d", dst_s4s); if (dst_s4s !== -4\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:103: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_ux\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_s4s = src_ux; $display("%d", dst_s4s); if (dst_s4s !==  4\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:104: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_sx\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_s4s = src_sx; $display("%d", dst_s4s); if (dst_s4s !==  4\'sd7) failed = 1;\n          ^\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:107: Implicit conversion of real to integer\n  dst_u4l = src_r;  $display("%d", dst_u4l); if (dst_u4l !== 12\'d4089) failed = 1;\n            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:108: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u2\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_u4l = src_u2; $display("%d", dst_u4l); if (dst_u4l !== 12\'d7)    failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:109: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s2\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_u4l = src_s2; $display("%d", dst_u4l); if (dst_u4l !== 12\'d4089) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:110: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u4\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_u4l = src_u4; $display("%d", dst_u4l); if (dst_u4l !== 12\'d7)    failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:111: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s4\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_u4l = src_s4; $display("%d", dst_u4l); if (dst_u4l !== 12\'d4089) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:112: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_ux\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_u4l = src_ux; $display("%b", dst_u4l); if (dst_u4l !== 12\'b0000x0z00111) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:113: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_sx\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_u4l = src_sx; $display("%b", dst_u4l); if (dst_u4l !== 12\'bxxxxx0z00111) failed = 1;\n          ^\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:116: Implicit conversion of real to integer\n  dst_s4l = src_r;  $display("%d", dst_s4l); if (dst_s4l !== -12\'sd7) failed = 1;\n            ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:117: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u2\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_s4l = src_u2; $display("%d", dst_s4l); if (dst_s4l !==  12\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:118: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s2\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_s4l = src_s2; $display("%d", dst_s4l); if (dst_s4l !== -12\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:119: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_u4\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_s4l = src_u4; $display("%d", dst_s4l); if (dst_s4l !==  12\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:120: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_s4\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_s4l = src_s4; $display("%d", dst_s4l); if (dst_s4l !== -12\'sd7) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:121: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_ux\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_s4l = src_ux; $display("%b", dst_s4l); if (dst_s4l !==  12\'b0000x0z00111) failed = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/implicit_cast1.v:122: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'src_sx\' generates 8 bits.\n                                                                               : ... In instance implicit_cast\n  dst_s4l = src_sx; $display("%b", dst_s4l); if (dst_s4l !==  12\'bxxxxx0z00111) failed = 1;\n          ^\n%Error: Exiting due to 56 warning(s)\n'
module implicit_cast();

real                  src_r;

bit   unsigned  [7:0] src_u2;
bit   signed    [7:0] src_s2;

logic unsigned  [7:0] src_u4;
logic signed    [7:0] src_s4;

logic unsigned  [7:0] src_ux;
logic signed    [7:0] src_sx;

real                  dst_r;

bit   unsigned  [3:0] dst_u2s;
bit   signed    [3:0] dst_s2s;

bit   unsigned [11:0] dst_u2l;
bit   signed   [11:0] dst_s2l;

logic unsigned  [3:0] dst_u4s;
logic signed    [3:0] dst_s4s;

logic unsigned [11:0] dst_u4l;
logic signed   [11:0] dst_s4l;

bit failed;

initial begin
  failed = 0;

  src_r  = -7;
  src_u2 =  7;
  src_s2 = -7;
  src_u4 =  7;
  src_s4 = -7;
  src_ux = 8'bx0z00111;
  src_sx = 8'bx0z00111;

  $display("cast to real");
  dst_r = src_r;  $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
  dst_r = src_u2; $display("%g", dst_r); if (dst_r !=  7.0) failed = 1;
  dst_r = src_s2; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
  dst_r = src_u4; $display("%g", dst_r); if (dst_r !=  7.0) failed = 1;
  dst_r = src_s4; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
  dst_r = src_ux; $display("%g", dst_r); if (dst_r !=  7.0) failed = 1;
  dst_r = src_sx; $display("%g", dst_r); if (dst_r !=  7.0) failed = 1;

  $display("cast to small unsigned bit");
  dst_u2s = src_r;  $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
  dst_u2s = src_u2; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
  dst_u2s = src_s2; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
  dst_u2s = src_u4; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
  dst_u2s = src_s4; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
  dst_u2s = src_ux; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
  dst_u2s = src_sx; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;

  $display("cast to small signed bit");
  dst_s2s = src_r;  $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
  dst_s2s = src_u2; $display("%d", dst_s2s); if (dst_s2s !==  4'sd7) failed = 1;
  dst_s2s = src_s2; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
  dst_s2s = src_u4; $display("%d", dst_s2s); if (dst_s2s !==  4'sd7) failed = 1;
  dst_s2s = src_s4; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
  dst_s2s = src_ux; $display("%d", dst_s2s); if (dst_s2s !==  4'sd7) failed = 1;
  dst_s2s = src_sx; $display("%d", dst_s2s); if (dst_s2s !==  4'sd7) failed = 1;

  $display("cast to large unsigned bit");
  dst_u2l = src_r;  $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
  dst_u2l = src_u2; $display("%d", dst_u2l); if (dst_u2l !== 12'd7)    failed = 1;
  dst_u2l = src_s2; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
  dst_u2l = src_u4; $display("%d", dst_u2l); if (dst_u2l !== 12'd7)    failed = 1;
  dst_u2l = src_s4; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
  dst_u2l = src_ux; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
  dst_u2l = src_sx; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;

  $display("cast to large signed bit");
  dst_s2l = src_r;  $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
  dst_s2l = src_u2; $display("%d", dst_s2l); if (dst_s2l !==  12'sd7) failed = 1;
  dst_s2l = src_s2; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
  dst_s2l = src_u4; $display("%d", dst_s2l); if (dst_s2l !==  12'sd7) failed = 1;
  dst_s2l = src_s4; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
  dst_s2l = src_ux; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
  dst_s2l = src_sx; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;

  $display("cast to small unsigned logic");
  dst_u4s = src_r;  $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
  dst_u4s = src_u2; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
  dst_u4s = src_s2; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
  dst_u4s = src_u4; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
  dst_u4s = src_s4; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
  dst_u4s = src_ux; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
  dst_u4s = src_sx; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;

  $display("cast to small signed logic");
  dst_s4s = src_r;  $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
  dst_s4s = src_u2; $display("%d", dst_s4s); if (dst_s4s !==  4'sd7) failed = 1;
  dst_s4s = src_s2; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
  dst_s4s = src_u4; $display("%d", dst_s4s); if (dst_s4s !==  4'sd7) failed = 1;
  dst_s4s = src_s4; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
  dst_s4s = src_ux; $display("%d", dst_s4s); if (dst_s4s !==  4'sd7) failed = 1;
  dst_s4s = src_sx; $display("%d", dst_s4s); if (dst_s4s !==  4'sd7) failed = 1;

  $display("cast to large unsigned logic");
  dst_u4l = src_r;  $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
  dst_u4l = src_u2; $display("%d", dst_u4l); if (dst_u4l !== 12'd7)    failed = 1;
  dst_u4l = src_s2; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
  dst_u4l = src_u4; $display("%d", dst_u4l); if (dst_u4l !== 12'd7)    failed = 1;
  dst_u4l = src_s4; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
  dst_u4l = src_ux; $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1;
  dst_u4l = src_sx; $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1;

  $display("cast to large signed logic");
  dst_s4l = src_r;  $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
  dst_s4l = src_u2; $display("%d", dst_s4l); if (dst_s4l !==  12'sd7) failed = 1;
  dst_s4l = src_s2; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
  dst_s4l = src_u4; $display("%d", dst_s4l); if (dst_s4l !==  12'sd7) failed = 1;
  dst_s4l = src_s4; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
  dst_s4l = src_ux; $display("%b", dst_s4l); if (dst_s4l !==  12'b0000x0z00111) failed = 1;
  dst_s4l = src_sx; $display("%b", dst_s4l); if (dst_s4l !==  12'bxxxxx0z00111) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module implicit_cast();


real                  src_r;

bit   unsigned  [7:0] src_u2;
bit   signed    [7:0] src_s2;

logic unsigned  [7:0] src_u4;
logic signed    [7:0] src_s4;

logic unsigned  [7:0] src_ux;
logic signed    [7:0] src_sx;

real                  dst_r;

bit   unsigned  [3:0] dst_u2s;
bit   signed    [3:0] dst_s2s;

bit   unsigned [11:0] dst_u2l;
bit   signed   [11:0] dst_s2l;

logic unsigned  [3:0] dst_u4s;
logic signed    [3:0] dst_s4s;

logic unsigned [11:0] dst_u4l;
logic signed   [11:0] dst_s4l;

bit failed;

initial begin
  failed = 0;

  src_r  = -7;
  src_u2 =  7;
  src_s2 = -7;
  src_u4 =  7;
  src_s4 = -7;
  src_ux = 8'bx0z00111;
  src_sx = 8'bx0z00111;

  $display("cast to real");
  dst_r = src_r;  $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
  dst_r = src_u2; $display("%g", dst_r); if (dst_r !=  7.0) failed = 1;
  dst_r = src_s2; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
  dst_r = src_u4; $display("%g", dst_r); if (dst_r !=  7.0) failed = 1;
  dst_r = src_s4; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
  dst_r = src_ux; $display("%g", dst_r); if (dst_r !=  7.0) failed = 1;
  dst_r = src_sx; $display("%g", dst_r); if (dst_r !=  7.0) failed = 1;

  $display("cast to small unsigned bit");
  dst_u2s = src_r;  $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
  dst_u2s = src_u2; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
  dst_u2s = src_s2; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
  dst_u2s = src_u4; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
  dst_u2s = src_s4; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
  dst_u2s = src_ux; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
  dst_u2s = src_sx; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;

  $display("cast to small signed bit");
  dst_s2s = src_r;  $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
  dst_s2s = src_u2; $display("%d", dst_s2s); if (dst_s2s !==  4'sd7) failed = 1;
  dst_s2s = src_s2; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
  dst_s2s = src_u4; $display("%d", dst_s2s); if (dst_s2s !==  4'sd7) failed = 1;
  dst_s2s = src_s4; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
  dst_s2s = src_ux; $display("%d", dst_s2s); if (dst_s2s !==  4'sd7) failed = 1;
  dst_s2s = src_sx; $display("%d", dst_s2s); if (dst_s2s !==  4'sd7) failed = 1;

  $display("cast to large unsigned bit");
  dst_u2l = src_r;  $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
  dst_u2l = src_u2; $display("%d", dst_u2l); if (dst_u2l !== 12'd7)    failed = 1;
  dst_u2l = src_s2; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
  dst_u2l = src_u4; $display("%d", dst_u2l); if (dst_u2l !== 12'd7)    failed = 1;
  dst_u2l = src_s4; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
  dst_u2l = src_ux; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
  dst_u2l = src_sx; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;

  $display("cast to large signed bit");
  dst_s2l = src_r;  $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
  dst_s2l = src_u2; $display("%d", dst_s2l); if (dst_s2l !==  12'sd7) failed = 1;
  dst_s2l = src_s2; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
  dst_s2l = src_u4; $display("%d", dst_s2l); if (dst_s2l !==  12'sd7) failed = 1;
  dst_s2l = src_s4; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
  dst_s2l = src_ux; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
  dst_s2l = src_sx; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;

  $display("cast to small unsigned logic");
  dst_u4s = src_r;  $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
  dst_u4s = src_u2; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
  dst_u4s = src_s2; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
  dst_u4s = src_u4; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
  dst_u4s = src_s4; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
  dst_u4s = src_ux; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
  dst_u4s = src_sx; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;

  $display("cast to small signed logic");
  dst_s4s = src_r;  $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
  dst_s4s = src_u2; $display("%d", dst_s4s); if (dst_s4s !==  4'sd7) failed = 1;
  dst_s4s = src_s2; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
  dst_s4s = src_u4; $display("%d", dst_s4s); if (dst_s4s !==  4'sd7) failed = 1;
  dst_s4s = src_s4; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
  dst_s4s = src_ux; $display("%d", dst_s4s); if (dst_s4s !==  4'sd7) failed = 1;
  dst_s4s = src_sx; $display("%d", dst_s4s); if (dst_s4s !==  4'sd7) failed = 1;

  $display("cast to large unsigned logic");
  dst_u4l = src_r;  $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
  dst_u4l = src_u2; $display("%d", dst_u4l); if (dst_u4l !== 12'd7)    failed = 1;
  dst_u4l = src_s2; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
  dst_u4l = src_u4; $display("%d", dst_u4l); if (dst_u4l !== 12'd7)    failed = 1;
  dst_u4l = src_s4; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
  dst_u4l = src_ux; $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1;
  dst_u4l = src_sx; $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1;

  $display("cast to large signed logic");
  dst_s4l = src_r;  $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
  dst_s4l = src_u2; $display("%d", dst_s4l); if (dst_s4l !==  12'sd7) failed = 1;
  dst_s4l = src_s2; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
  dst_s4l = src_u4; $display("%d", dst_s4l); if (dst_s4l !==  12'sd7) failed = 1;
  dst_s4l = src_s4; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
  dst_s4l = src_ux; $display("%b", dst_s4l); if (dst_s4l !==  12'b0000x0z00111) failed = 1;
  dst_s4l = src_sx; $display("%b", dst_s4l); if (dst_s4l !==  12'bxxxxx0z00111) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule