data/full_repos/permissive/114943225/adc_control.v
1: b'%Error: data/full_repos/permissive/114943225/adc_control.v:149: syntax error, unexpected type\n .type(trig_type),   \n  ^~~~\n%Error: Exiting due to 1 error(s)\n'
module adc_control (

	clkin,
	divider_acq_clk,

	run_in,
	stop_in,

	state_runmode,
	state_trig,

	debug_led,

	trig_mode,
	trig_lvl,
	trig_type,
	trig_noiserej,

	adc_clkout_a,
	adc_clkout_b,
	adc_unlatched_data_a,
	adc_unlatched_data_b,
	adcoen_a,
	adcoen_b,

	clk_ramout,
	addr_ramout_a,
	addr_ramout_b,
	wr_en_ramout,
	data_wr_ramout_a,
	data_wr_ramout_b
);

parameter TRIG_NORM = 0;
parameter TRIG_AUTO = 1;
parameter TRIG_SINGLE = 2;					

parameter TRIG_STATE_WAIT = 0;
parameter TRIG_STATE_TRIGD = 1;
parameter TRIG_STATE_AUTO = 2;
parameter TRIG_STATE_DONE = 3;

parameter CLK_DIV_WIDTH = 24;
parameter ADC_WIDTH = 14;
parameter ACQ_MAX_SAMPLES = 1024;
parameter ACQ_COUNTER_WIDTH = 12;

parameter AUTO_MODE_DELAY = 60000000;
parameter AUTO_MODE_FAST = 2500000;
parameter NO_TRIG_DELAY = 50000;
parameter HOLD_OFF_DELAY = 4;


parameter STATE_STOPPED = 0;
parameter STATE_WAIT_FOR_TRIG = 1;
parameter STATE_ACQUIRE = 2;
parameter STATE_HOLD_OFF = 3;
parameter STATE_POST_TRIG = 4;


parameter HYST_NOISEREJ_ON = 200;
parameter HYST_NOISEREJ_OFF = 12;

input [CLK_DIV_WIDTH - 1:0] divider_acq_clk;
input [ADC_WIDTH - 1:0] adc_unlatched_data_a;
input [ADC_WIDTH - 1:0] adc_unlatched_data_b;
input clkin;
wire clktrig;
wire clkacq;


output adc_clkout_a;
output adc_clkout_b;
output adcoen_a;
output adcoen_b;


input run_in, stop_in;
output reg state_runmode;
output reg [2:0] state_trig;
input [1:0] trig_mode;
input [15:0] trig_lvl;
input [2:0] trig_type;
input trig_noiserej;


output reg [7:0] debug_led;


output wire clk_ramout;
output reg [ACQ_COUNTER_WIDTH - 1:0] addr_ramout_a;
output reg [ACQ_COUNTER_WIDTH - 1:0] addr_ramout_b;
output reg wr_en_ramout;
output reg [ADC_WIDTH - 1:0] data_wr_ramout_a;
output reg [ADC_WIDTH - 1:0] data_wr_ramout_b;





assign clk_ramout = clkin;


reg trig_en;
wire trig_out;


reg [15:0] hold_off;


reg [31:0] trig_timeout;
reg trig_auto_rapid;
reg auto_trig_gen;


reg [ACQ_COUNTER_WIDTH - 1:0] acq_index;


reg [2:0] acq_state;




adc_clock_gen cg1 (
	.clkin(clkin),
	.clkout(clkacq),
	.reset(0),
	.enable(1),
	.divider(divider_acq_clk)
);


edge_Trig tr0(
	.clkIn(clkin),
	.trigLvl(trig_lvl),
	.trigHyst((trig_noiserej) ? HYST_NOISEREJ_ON : HYST_NOISEREJ_OFF),
	.adc_data(adc_unlatched_data_a),
	.type(trig_type),			
	.enable(trig_en),
	.q(trig_out)
);


assign adcoen_a = 1'b0;
assign adcoen_b = 1'b0;


assign adc_clkout_a = clkacq;
assign adc_clkout_b = clkacq;


always @(negedge clkacq) begin



	if (acq_state == STATE_STOPPED) begin
		debug_led = 5'b00001;
		state_runmode <= 0;
		if (run_in) begin
			state_runmode <= 1;
			acq_state = STATE_WAIT_FOR_TRIG;
		end
	end
	

	if (acq_state == STATE_WAIT_FOR_TRIG) begin
		trig_en <= 1;
		debug_led = 5'b00010;
		


		if (stop_in) begin
			acq_state = STATE_STOPPED;
		end else if (trig_out || auto_trig_gen) begin 
			trig_en <= 0;
			acq_index <= 0;
			addr_ramout_a = 0;
			addr_ramout_b = 0;
			acq_state = STATE_ACQUIRE;
			if (!auto_trig_gen) begin
				state_trig <= TRIG_STATE_TRIGD;
			end;
			auto_trig_gen <= 0;
		end
		



		trig_timeout <= trig_timeout + divider_acq_clk + 1;
		
		if ((trig_mode == TRIG_AUTO) && (trig_timeout > AUTO_MODE_FAST) && (trig_auto_rapid == 1)) begin

			trig_timeout <= 0;
			state_trig <= TRIG_STATE_AUTO;
			auto_trig_gen <= 1;
			trig_auto_rapid <= 1;
		end else if ((trig_mode == TRIG_AUTO) && (trig_timeout > AUTO_MODE_DELAY) && (trig_auto_rapid == 0)) begin

			trig_timeout <= 0;
			state_trig <= TRIG_STATE_AUTO;
			trig_auto_rapid <= 1;
			auto_trig_gen <= 1;
		end else if ((trig_timeout > NO_TRIG_DELAY) && (trig_mode != TRIG_AUTO)) begin

			state_trig <= TRIG_STATE_WAIT;
		end
	end
	

	if (acq_state == STATE_ACQUIRE) begin
		trig_timeout <= 0;
		debug_led = 5'b00100;
		if (acq_index == ACQ_MAX_SAMPLES) begin
			acq_state = STATE_HOLD_OFF;
			hold_off <= HOLD_OFF_DELAY;
			wr_en_ramout = 0;
		end else begin



			addr_ramout_a = addr_ramout_a + 1;
			addr_ramout_b = addr_ramout_b + 1;
			acq_index <= acq_index + 1;
			

			wr_en_ramout = 1;
			data_wr_ramout_a = adc_unlatched_data_a;
			data_wr_ramout_b = adc_unlatched_data_b; 
		end
	end
	


	if (acq_state == STATE_HOLD_OFF) begin
		hold_off <= hold_off - 1;
		debug_led = 5'b01000;
		if (hold_off == 0) begin
			acq_state = STATE_POST_TRIG;
		end;
	end;
	




	if (acq_state == STATE_POST_TRIG) begin
		if (trig_mode == TRIG_SINGLE) begin
			state_trig <= TRIG_STATE_DONE;
			acq_state = STATE_STOPPED;
		end else begin
			debug_led = 5'b10000;
			if (stop_in) begin
				acq_state = STATE_STOPPED;
			end else begin
				acq_state = STATE_WAIT_FOR_TRIG;
			end
		end
	end

end

endmodule
module adc_control (

	clkin,
	divider_acq_clk,

	run_in,
	stop_in,

	state_runmode,
	state_trig,

	debug_led,

	trig_mode,
	trig_lvl,
	trig_type,
	trig_noiserej,

	adc_clkout_a,
	adc_clkout_b,
	adc_unlatched_data_a,
	adc_unlatched_data_b,
	adcoen_a,
	adcoen_b,

	clk_ramout,
	addr_ramout_a,
	addr_ramout_b,
	wr_en_ramout,
	data_wr_ramout_a,
	data_wr_ramout_b
);


parameter TRIG_NORM = 0;
parameter TRIG_AUTO = 1;
parameter TRIG_SINGLE = 2;					

parameter TRIG_STATE_WAIT = 0;
parameter TRIG_STATE_TRIGD = 1;
parameter TRIG_STATE_AUTO = 2;
parameter TRIG_STATE_DONE = 3;

parameter CLK_DIV_WIDTH = 24;
parameter ADC_WIDTH = 14;
parameter ACQ_MAX_SAMPLES = 1024;
parameter ACQ_COUNTER_WIDTH = 12;

parameter AUTO_MODE_DELAY = 60000000;
parameter AUTO_MODE_FAST = 2500000;
parameter NO_TRIG_DELAY = 50000;
parameter HOLD_OFF_DELAY = 4;


parameter STATE_STOPPED = 0;
parameter STATE_WAIT_FOR_TRIG = 1;
parameter STATE_ACQUIRE = 2;
parameter STATE_HOLD_OFF = 3;
parameter STATE_POST_TRIG = 4;


parameter HYST_NOISEREJ_ON = 200;
parameter HYST_NOISEREJ_OFF = 12;

input [CLK_DIV_WIDTH - 1:0] divider_acq_clk;
input [ADC_WIDTH - 1:0] adc_unlatched_data_a;
input [ADC_WIDTH - 1:0] adc_unlatched_data_b;
input clkin;
wire clktrig;
wire clkacq;


output adc_clkout_a;
output adc_clkout_b;
output adcoen_a;
output adcoen_b;


input run_in, stop_in;
output reg state_runmode;
output reg [2:0] state_trig;
input [1:0] trig_mode;
input [15:0] trig_lvl;
input [2:0] trig_type;
input trig_noiserej;


output reg [7:0] debug_led;


output wire clk_ramout;
output reg [ACQ_COUNTER_WIDTH - 1:0] addr_ramout_a;
output reg [ACQ_COUNTER_WIDTH - 1:0] addr_ramout_b;
output reg wr_en_ramout;
output reg [ADC_WIDTH - 1:0] data_wr_ramout_a;
output reg [ADC_WIDTH - 1:0] data_wr_ramout_b;





assign clk_ramout = clkin;


reg trig_en;
wire trig_out;


reg [15:0] hold_off;


reg [31:0] trig_timeout;
reg trig_auto_rapid;
reg auto_trig_gen;


reg [ACQ_COUNTER_WIDTH - 1:0] acq_index;


reg [2:0] acq_state;




adc_clock_gen cg1 (
	.clkin(clkin),
	.clkout(clkacq),
	.reset(0),
	.enable(1),
	.divider(divider_acq_clk)
);


edge_Trig tr0(
	.clkIn(clkin),
	.trigLvl(trig_lvl),
	.trigHyst((trig_noiserej) ? HYST_NOISEREJ_ON : HYST_NOISEREJ_OFF),
	.adc_data(adc_unlatched_data_a),
	.type(trig_type),			
	.enable(trig_en),
	.q(trig_out)
);


assign adcoen_a = 1'b0;
assign adcoen_b = 1'b0;


assign adc_clkout_a = clkacq;
assign adc_clkout_b = clkacq;


always @(negedge clkacq) begin



	if (acq_state == STATE_STOPPED) begin
		debug_led = 5'b00001;
		state_runmode <= 0;
		if (run_in) begin
			state_runmode <= 1;
			acq_state = STATE_WAIT_FOR_TRIG;
		end
	end
	

	if (acq_state == STATE_WAIT_FOR_TRIG) begin
		trig_en <= 1;
		debug_led = 5'b00010;
		


		if (stop_in) begin
			acq_state = STATE_STOPPED;
		end else if (trig_out || auto_trig_gen) begin 
			trig_en <= 0;
			acq_index <= 0;
			addr_ramout_a = 0;
			addr_ramout_b = 0;
			acq_state = STATE_ACQUIRE;
			if (!auto_trig_gen) begin
				state_trig <= TRIG_STATE_TRIGD;
			end;
			auto_trig_gen <= 0;
		end
		



		trig_timeout <= trig_timeout + divider_acq_clk + 1;
		
		if ((trig_mode == TRIG_AUTO) && (trig_timeout > AUTO_MODE_FAST) && (trig_auto_rapid == 1)) begin

			trig_timeout <= 0;
			state_trig <= TRIG_STATE_AUTO;
			auto_trig_gen <= 1;
			trig_auto_rapid <= 1;
		end else if ((trig_mode == TRIG_AUTO) && (trig_timeout > AUTO_MODE_DELAY) && (trig_auto_rapid == 0)) begin

			trig_timeout <= 0;
			state_trig <= TRIG_STATE_AUTO;
			trig_auto_rapid <= 1;
			auto_trig_gen <= 1;
		end else if ((trig_timeout > NO_TRIG_DELAY) && (trig_mode != TRIG_AUTO)) begin

			state_trig <= TRIG_STATE_WAIT;
		end
	end
	

	if (acq_state == STATE_ACQUIRE) begin
		trig_timeout <= 0;
		debug_led = 5'b00100;
		if (acq_index == ACQ_MAX_SAMPLES) begin
			acq_state = STATE_HOLD_OFF;
			hold_off <= HOLD_OFF_DELAY;
			wr_en_ramout = 0;
		end else begin



			addr_ramout_a = addr_ramout_a + 1;
			addr_ramout_b = addr_ramout_b + 1;
			acq_index <= acq_index + 1;
			

			wr_en_ramout = 1;
			data_wr_ramout_a = adc_unlatched_data_a;
			data_wr_ramout_b = adc_unlatched_data_b; 
		end
	end
	


	if (acq_state == STATE_HOLD_OFF) begin
		hold_off <= hold_off - 1;
		debug_led = 5'b01000;
		if (hold_off == 0) begin
			acq_state = STATE_POST_TRIG;
		end;
	end;
	




	if (acq_state == STATE_POST_TRIG) begin
		if (trig_mode == TRIG_SINGLE) begin
			state_trig <= TRIG_STATE_DONE;
			acq_state = STATE_STOPPED;
		end else begin
			debug_led = 5'b10000;
			if (stop_in) begin
				acq_state = STATE_STOPPED;
			end else begin
				acq_state = STATE_WAIT_FOR_TRIG;
			end
		end
	end

end

endmodule