data/full_repos/permissive/160794640/example/decoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160794640/example/decoder.v:10: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 21 bits.\n                                                                         : ... In instance decoder\n    { decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1\'b0});\n                                                                                                                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/160794640/example/decoder.v:12: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 12 bits.\n                                                                         : ... In instance decoder\n             decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1\'b0});\n                                                                                            ^~\n%Error: Exiting due to 2 warning(s)\n'
module decoder (
	input clk, resetn,
	input [31:0] mem_rdata_latched,
	output reg [31:0] decoded_imm_uj,
        output logic [31:0] mem_rdata_q);

always@(posedge clk) 
  begin
     mem_rdata_q[14:12] <= 3'h0;
	   { decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
           { decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6],
             decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
           end

endmodule
module decoder (
	input clk, resetn,
	input [31:0] mem_rdata_latched,
	output reg [31:0] decoded_imm_uj,
        output logic [31:0] mem_rdata_q);


always@(posedge clk) 
  begin
     mem_rdata_q[14:12] <= 3'h0;
	   { decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
           { decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6],
             decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
           end

endmodule