data/full_repos/permissive/20548509/rtl/verilog/dit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/20548509/rtl/verilog/dit.v:96: Operator ASSIGNW expects 192 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 172 bits.\n                                                                        : ... In instance dit\n wire [191:0] ch_stat = {{132{1\'b0}}, ch_stat_buf};\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module dit(
	  mck_i
	, bck_i
	, lrck_i
	, dat_i
	, mck_ratio_i
	, vbit_i
	, mute_i
	, ch_stat7_0_i
	, ch_stat15_8_i
	, ch_stat23_16_i
	, ch_stat31_24_i
	, ch_stat39_32_i

	, rst_i
	, spdif_o

);








	input mck_i;
	input bck_i;
	input lrck_i;
	input dat_i;
	input [1:0] mck_ratio_i;
	input vbit_i;
	input mute_i;
	input [7:0] ch_stat7_0_i;
	input [7:0] ch_stat15_8_i;
	input [7:0] ch_stat23_16_i;
	input [7:0] ch_stat31_24_i;
	input [7:0] ch_stat39_32_i;

	input rst_i;

	output spdif_o;

	



	wire [7:0] B_PREAMBLE = 8'b00010111;
	wire [7:0] M_PREAMBLE = 8'b01000111;
	wire [7:0] W_PREAMBLE = 8'b00100111;

	reg [39:0] ch_stat_buf;
	wire [191:0] ch_stat = {{132{1'b0}}, ch_stat_buf};
	reg [14:0] cnt;
	wire slot_state = cnt[0];
	wire [4:0] bit_cnt = cnt[5:1];
	wire [7:0] frame_cnt = cnt[14:7];
	wire subframe = cnt[6];

	reg p_bit;
	wire v_bit = vbit_i;
	
	reg [1:0] d_clk;
	wire s_clk = (mck_ratio_i==2'b00) ? mck_i :
					(mck_ratio_i==2'b01) ? d_clk[0] :
					(mck_ratio_i==2'b10) ? d_clk[1] : 1'b0;

	
	reg encdat;
	reg spdif;
	assign spdif_o = spdif;





	reg rst_int;
	wire rst = rst_i | rst_int;
	always @ (negedge lrck_i or posedge rst_i) begin
		if(rst_i) begin
			rst_int <= 1'b1;
		end
		else begin
			if(&bit_cnt[4:0]) begin
				rst_int <= 1'b0;
			end
			else begin
				rst_int <= 1'b1;
			end
		end
	end

	always @ (posedge mck_i or posedge rst) begin
		if(rst) begin
			d_clk <= 2'b0;
		end
		else begin
			d_clk <= d_clk + 1'b1;
		end
	end

	reg lrck_q0, lrck_q1;
	wire lrck_edge_flag = lrck_i ^ lrck_q1;
	always @ (posedge bck_i or posedge rst) begin
		if(rst) begin
			lrck_q0 <= 1'b0;
		end
		else begin
			lrck_q0 <= lrck_i;
		end
	end
	always @ (negedge bck_i or posedge rst) begin
		if(rst) begin
			lrck_q1 <= 1'b0;
		end
		else begin
			lrck_q1 <= lrck_q0;
		end
	end

	always @ (posedge s_clk or posedge rst) begin
		if(rst) begin
			cnt <= 15'b111111111111111;
		end
		else begin
			if({frame_cnt, subframe, bit_cnt, slot_state}=={8'd191, 1'b1, 5'b11111, 1'b1}) begin
				cnt <= 15'b0;
			end
			else begin
				cnt <= cnt + 1'b1;
			end
		end
	end

	reg [4:0] i2s_bit_cnt;
	reg lr;
	reg [23:0] dat_l, dat_r;
	reg mute;
	always @ (posedge bck_i or posedge rst) begin
		if(rst) begin
			i2s_bit_cnt <= 5'b11111;
			lr <= 1'b0;
			dat_l <= 24'b0;
			dat_r <= 24'b0;
			mute <= 1'b0;
		end
		else begin
			if(lrck_edge_flag) begin
				i2s_bit_cnt <= 5'b0;
				mute <= mute_i;
			end
			else begin
				if(i2s_bit_cnt!=5'd24) begin
					i2s_bit_cnt <= i2s_bit_cnt + 1'b1;
				end
			end
			if(~lr) begin
				dat_l[23-i2s_bit_cnt] <= dat_i & ~mute;
			end
			else begin
				dat_r[23-i2s_bit_cnt] <= dat_i & ~mute;
			end
			lr <= lrck_i;
		end
	end
	always @ (negedge lrck_edge_flag or posedge rst) begin
		if(rst) begin
			ch_stat_buf <= 40'b0;
		end
		else begin
			ch_stat_buf <= {ch_stat39_32_i, ch_stat31_24_i, ch_stat23_16_i, ch_stat15_8_i, ch_stat7_0_i};
		end
	end

	always @ (posedge s_clk or posedge rst) begin
		if(rst) begin
			spdif <= 1'b0;
			p_bit <= 1'b0;
		end
		else begin
			if(bit_cnt==5'd0) begin
				p_bit <= 1'b0;
			end
			if(bit_cnt<5'd4) begin

				if(subframe) begin

					spdif <= W_PREAMBLE[{bit_cnt[1:0], slot_state}];
				end
				else if(frame_cnt==8'b0) begin

					spdif <= B_PREAMBLE[{bit_cnt[1:0], slot_state}];
				end
				else begin

					spdif <= M_PREAMBLE[{bit_cnt[1:0], slot_state}];
				end
			end
			else begin
				spdif <= (!slot_state) ? ~spdif :
								(encdat) ? ~spdif : spdif;
				p_bit <= p_bit + (encdat & slot_state);
			end
		end
	end

	always @ (negedge s_clk or posedge rst) begin
		if(rst) begin
			encdat <= 1'b0;
		end
		else begin
			if(bit_cnt>5'd3 && bit_cnt<5'd28) begin
				if(lrck_i) begin
					encdat <= dat_l[bit_cnt-4];
				end
				else begin
					encdat <= dat_r[bit_cnt-4];
				end

			end
			else if(bit_cnt==5'd28) begin
				encdat <= v_bit;
			end
			else if(bit_cnt==5'd29) begin

				encdat <= 1'b0;
			end
			else if(bit_cnt==5'd30) begin
				encdat <= ch_stat[frame_cnt];
			end
			else if(bit_cnt==5'd31) begin
				encdat <= p_bit;
			end
		end
	end

	
endmodule
module dit(
	  mck_i
	, bck_i
	, lrck_i
	, dat_i
	, mck_ratio_i
	, vbit_i
	, mute_i
	, ch_stat7_0_i
	, ch_stat15_8_i
	, ch_stat23_16_i
	, ch_stat31_24_i
	, ch_stat39_32_i

	, rst_i
	, spdif_o

);









	input mck_i;
	input bck_i;
	input lrck_i;
	input dat_i;
	input [1:0] mck_ratio_i;
	input vbit_i;
	input mute_i;
	input [7:0] ch_stat7_0_i;
	input [7:0] ch_stat15_8_i;
	input [7:0] ch_stat23_16_i;
	input [7:0] ch_stat31_24_i;
	input [7:0] ch_stat39_32_i;

	input rst_i;

	output spdif_o;

	



	wire [7:0] B_PREAMBLE = 8'b00010111;
	wire [7:0] M_PREAMBLE = 8'b01000111;
	wire [7:0] W_PREAMBLE = 8'b00100111;

	reg [39:0] ch_stat_buf;
	wire [191:0] ch_stat = {{132{1'b0}}, ch_stat_buf};
	reg [14:0] cnt;
	wire slot_state = cnt[0];
	wire [4:0] bit_cnt = cnt[5:1];
	wire [7:0] frame_cnt = cnt[14:7];
	wire subframe = cnt[6];

	reg p_bit;
	wire v_bit = vbit_i;
	
	reg [1:0] d_clk;
	wire s_clk = (mck_ratio_i==2'b00) ? mck_i :
					(mck_ratio_i==2'b01) ? d_clk[0] :
					(mck_ratio_i==2'b10) ? d_clk[1] : 1'b0;

	
	reg encdat;
	reg spdif;
	assign spdif_o = spdif;





	reg rst_int;
	wire rst = rst_i | rst_int;
	always @ (negedge lrck_i or posedge rst_i) begin
		if(rst_i) begin
			rst_int <= 1'b1;
		end
		else begin
			if(&bit_cnt[4:0]) begin
				rst_int <= 1'b0;
			end
			else begin
				rst_int <= 1'b1;
			end
		end
	end

	always @ (posedge mck_i or posedge rst) begin
		if(rst) begin
			d_clk <= 2'b0;
		end
		else begin
			d_clk <= d_clk + 1'b1;
		end
	end

	reg lrck_q0, lrck_q1;
	wire lrck_edge_flag = lrck_i ^ lrck_q1;
	always @ (posedge bck_i or posedge rst) begin
		if(rst) begin
			lrck_q0 <= 1'b0;
		end
		else begin
			lrck_q0 <= lrck_i;
		end
	end
	always @ (negedge bck_i or posedge rst) begin
		if(rst) begin
			lrck_q1 <= 1'b0;
		end
		else begin
			lrck_q1 <= lrck_q0;
		end
	end

	always @ (posedge s_clk or posedge rst) begin
		if(rst) begin
			cnt <= 15'b111111111111111;
		end
		else begin
			if({frame_cnt, subframe, bit_cnt, slot_state}=={8'd191, 1'b1, 5'b11111, 1'b1}) begin
				cnt <= 15'b0;
			end
			else begin
				cnt <= cnt + 1'b1;
			end
		end
	end

	reg [4:0] i2s_bit_cnt;
	reg lr;
	reg [23:0] dat_l, dat_r;
	reg mute;
	always @ (posedge bck_i or posedge rst) begin
		if(rst) begin
			i2s_bit_cnt <= 5'b11111;
			lr <= 1'b0;
			dat_l <= 24'b0;
			dat_r <= 24'b0;
			mute <= 1'b0;
		end
		else begin
			if(lrck_edge_flag) begin
				i2s_bit_cnt <= 5'b0;
				mute <= mute_i;
			end
			else begin
				if(i2s_bit_cnt!=5'd24) begin
					i2s_bit_cnt <= i2s_bit_cnt + 1'b1;
				end
			end
			if(~lr) begin
				dat_l[23-i2s_bit_cnt] <= dat_i & ~mute;
			end
			else begin
				dat_r[23-i2s_bit_cnt] <= dat_i & ~mute;
			end
			lr <= lrck_i;
		end
	end
	always @ (negedge lrck_edge_flag or posedge rst) begin
		if(rst) begin
			ch_stat_buf <= 40'b0;
		end
		else begin
			ch_stat_buf <= {ch_stat39_32_i, ch_stat31_24_i, ch_stat23_16_i, ch_stat15_8_i, ch_stat7_0_i};
		end
	end

	always @ (posedge s_clk or posedge rst) begin
		if(rst) begin
			spdif <= 1'b0;
			p_bit <= 1'b0;
		end
		else begin
			if(bit_cnt==5'd0) begin
				p_bit <= 1'b0;
			end
			if(bit_cnt<5'd4) begin

				if(subframe) begin

					spdif <= W_PREAMBLE[{bit_cnt[1:0], slot_state}];
				end
				else if(frame_cnt==8'b0) begin

					spdif <= B_PREAMBLE[{bit_cnt[1:0], slot_state}];
				end
				else begin

					spdif <= M_PREAMBLE[{bit_cnt[1:0], slot_state}];
				end
			end
			else begin
				spdif <= (!slot_state) ? ~spdif :
								(encdat) ? ~spdif : spdif;
				p_bit <= p_bit + (encdat & slot_state);
			end
		end
	end

	always @ (negedge s_clk or posedge rst) begin
		if(rst) begin
			encdat <= 1'b0;
		end
		else begin
			if(bit_cnt>5'd3 && bit_cnt<5'd28) begin
				if(lrck_i) begin
					encdat <= dat_l[bit_cnt-4];
				end
				else begin
					encdat <= dat_r[bit_cnt-4];
				end

			end
			else if(bit_cnt==5'd28) begin
				encdat <= v_bit;
			end
			else if(bit_cnt==5'd29) begin

				encdat <= 1'b0;
			end
			else if(bit_cnt==5'd30) begin
				encdat <= ch_stat[frame_cnt];
			end
			else if(bit_cnt==5'd31) begin
				encdat <= p_bit;
			end
		end
	end

	
endmodule