data/full_repos/permissive/174642777/Experiments/Lab X6/1. TC_Moore/TC_Moore.v
1: b'%Error: Cannot find file containing module: X6/1.\n        ... Looked in:\n             data/full_repos/permissive/174642777/Experiments/Lab/X6/1.\n             data/full_repos/permissive/174642777/Experiments/Lab/X6/1..v\n             data/full_repos/permissive/174642777/Experiments/Lab/X6/1..sv\n             X6/1.\n             X6/1..v\n             X6/1..sv\n             obj_dir/X6/1.\n             obj_dir/X6/1..v\n             obj_dir/X6/1..sv\n%Error: Cannot find file containing module: TC_Moore,data/full_repos/permissive/174642777\n%Error: Cannot find file containing module: data/full_repos/permissive/174642777/Experiments/Lab\n%Error: Cannot find file containing module: TC_Moore/TC_Moore.v\n%Error: Exiting due to 4 error(s)\n'
module TC_Moore(
  input wire CLK,
  input wire R,
  input wire T_A, T_B,
  output wire[2:0] L_A,
  output wire[2:0] L_B
);

  reg[1:0] state;
  

  initial begin

    state <= 2'b00;
  end
  

  assign L_A[2] = (state == 2'b00);
  assign L_A[1] = (state == 2'b01);
  assign L_A[0] = (state[1] == 1'b1);
  assign L_B[2] = (state == 2'b10);
  assign L_B[1] = (state == 2'b11);
  assign L_B[0] = (state[1] == 1'b0);
  

  always@(posedge CLK, posedge R) begin
    if(R) state = 2'b00;
    else begin
      case(state)
        2'b00:   if(!T_A) state = 2'b01;
        2'b10:   if(!T_B) state = 2'b11;
        default: state = state + 2'b01;
      endcase
    end
  end

endmodule
module TC_Moore(
  input wire CLK,
  input wire R,
  input wire T_A, T_B,
  output wire[2:0] L_A,
  output wire[2:0] L_B
);


  reg[1:0] state;
  

  initial begin

    state <= 2'b00;
  end
  

  assign L_A[2] = (state == 2'b00);
  assign L_A[1] = (state == 2'b01);
  assign L_A[0] = (state[1] == 1'b1);
  assign L_B[2] = (state == 2'b10);
  assign L_B[1] = (state == 2'b11);
  assign L_B[0] = (state[1] == 1'b0);
  

  always@(posedge CLK, posedge R) begin
    if(R) state = 2'b00;
    else begin
      case(state)
        2'b00:   if(!T_A) state = 2'b01;
        2'b10:   if(!T_B) state = 2'b11;
        default: state = state + 2'b01;
      endcase
    end
  end

endmodule