data/full_repos/permissive/143278/fpga_tests/eqne_tb.v
 line:15: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/eqne_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #1 $display("x=%h, y=%h: ", x, y,\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/fpga_tests/eqne_tb.v:8: Cannot find file containing module: \'eqne\'\n   eqne dut(.eq1(eq1), .eq2(eq2), .eq5(eq5),\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/eqne\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/eqne.v\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/eqne.sv\n             eqne\n             eqne.v\n             eqne.sv\n             obj_dir/eqne\n             obj_dir/eqne.v\n             obj_dir/eqne.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire eq1, eq2, eq5;
   wire ne1, ne2, ne5;

   reg [7:0] x, y;

   eqne dut(.eq1(eq1), .eq2(eq2), .eq5(eq5),
	    .ne1(ne1), .ne2(ne2), .ne5(ne5),
	    .x(x), .y(y));

   initial begin
      for (x = 0 ;  x < 'h20 ;  x = x+1)
	for (y = 0 ;  y < 'h20 ;  y = y+1) begin
	   #1 $display("x=%h, y=%h: ", x, y,
		       "eq1=%b, eq2=%b, eq5=%b, ", eq1, eq2, eq5,
		       "ne1=%b, ne2=%b, ne5=%b", ne1, ne2, ne5);
	   if (eq1 !== (x[0] == y[0])) begin
	      $display("FAILED");
	      $finish;
	   end

	   if (eq2 !== (x[1:0] == y[1:0])) begin
	      $display("FAILED");
	      $finish;
	   end

	   if (eq5 !== (x[4:0] == y[4:0])) begin
	      $display("FAILED");
	      $finish;
	   end

	   if (ne1 !== (x[0] != y[0])) begin
	      $display("FAILED");
	      $finish;
	   end

	   if (ne2 !== (x[1:0] != y[1:0])) begin
	      $display("FAILED");
	      $finish;
	   end

	   if (ne5 !== (x[4:0] != y[4:0])) begin
	      $display("FAILED");
	      $finish;
	   end
	end

      $display("PASSED");
   end

endmodule
module main;


   wire eq1, eq2, eq5;
   wire ne1, ne2, ne5;

   reg [7:0] x, y;

   eqne dut(.eq1(eq1), .eq2(eq2), .eq5(eq5),
	    .ne1(ne1), .ne2(ne2), .ne5(ne5),
	    .x(x), .y(y));

   initial begin
      for (x = 0 ;  x < 'h20 ;  x = x+1)
	for (y = 0 ;  y < 'h20 ;  y = y+1) begin
	   #1 $display("x=%h, y=%h: ", x, y,
		       "eq1=%b, eq2=%b, eq5=%b, ", eq1, eq2, eq5,
		       "ne1=%b, ne2=%b, ne5=%b", ne1, ne2, ne5);
	   if (eq1 !== (x[0] == y[0])) begin
	      $display("FAILED");
	      $finish;
	   end

	   if (eq2 !== (x[1:0] == y[1:0])) begin
	      $display("FAILED");
	      $finish;
	   end

	   if (eq5 !== (x[4:0] == y[4:0])) begin
	      $display("FAILED");
	      $finish;
	   end

	   if (ne1 !== (x[0] != y[0])) begin
	      $display("FAILED");
	      $finish;
	   end

	   if (ne2 !== (x[1:0] != y[1:0])) begin
	      $display("FAILED");
	      $finish;
	   end

	   if (ne5 !== (x[4:0] != y[4:0])) begin
	      $display("FAILED");
	      $finish;
	   end
	end

      $display("PASSED");
   end

endmodule