data/full_repos/permissive/167274925/ALU32Bit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:64: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d2:  {ALUResulthi,ALUResultlo}<=A+B;\n                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:64: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d2:  {ALUResulthi,ALUResultlo}<=A+B;\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:65: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d6:  {ALUResulthi,ALUResultlo}<=A-B; \n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:65: Operator SUB expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d6:  {ALUResulthi,ALUResultlo}<=A-B; \n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:66: Operator AND expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d0:  {ALUResulthi,ALUResultlo}<=A&B; \n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:66: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d0:  {ALUResulthi,ALUResultlo}<=A&B; \n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:67: Operator AND expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d28:  {ALUResulthi,ALUResultlo}<=A&{16\'d0,B[15:0]};\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:67: Operator AND expects 64 bits on the RHS, but RHS\'s REPLICATE generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d28:  {ALUResulthi,ALUResultlo}<=A&{16\'d0,B[15:0]};\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:68: Operator OR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d1:  {ALUResulthi,ALUResultlo}<=A|B; \n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:68: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d1:  {ALUResulthi,ALUResultlo}<=A|B; \n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:69: Operator OR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d27: {ALUResulthi,ALUResultlo}<=A|{16\'d0,B[15:0]}; \n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:69: Operator OR expects 64 bits on the RHS, but RHS\'s REPLICATE generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d27: {ALUResulthi,ALUResultlo}<=A|{16\'d0,B[15:0]}; \n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:70: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d7:  {ALUResulthi,ALUResultlo}<=($signed (A)<$signed (B));\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:71: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d19: {ALUResulthi,ALUResultlo}<=(A<B);\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:73: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'B\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d10:  {ALUResulthi,ALUResultlo}<=B<<A;\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:74: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'B\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d11:  {ALUResulthi,ALUResultlo}<=B>>A;\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:75: Operator OR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d12:  {ALUResulthi,ALUResultlo}<=~(A|B);\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:75: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d12:  {ALUResulthi,ALUResultlo}<=~(A|B);\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:76: Operator XOR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d3:  {ALUResulthi,ALUResultlo}<=(A^B);\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:76: Operator XOR expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d3:  {ALUResulthi,ALUResultlo}<=(A^B);\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:77: Operator XOR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d22:  {ALUResulthi,ALUResultlo}<=A^{16\'d0,B[15:0]};\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:77: Operator XOR expects 64 bits on the RHS, but RHS\'s REPLICATE generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n      6\'d22:  {ALUResulthi,ALUResultlo}<=A^{16\'d0,B[15:0]};\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:99: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 32 bits.\n                                                                  : ... In instance ALU32Bit\n        {hi,lo}<=$signed (A*B);  \n               ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:100: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n        {ALUResulthi,ALUResultlo}<=32\'d0;\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:104: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n      {ALUResulthi,ALUResultlo}<=32\'d0;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:106: Operator ADD expects 64 bits on the RHS, but RHS\'s SIGNED generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n      6\'d16:begin {hi,lo}<=$signed({HI,LO})+$signed((A*B));  \n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:107: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n      {ALUResulthi,ALUResultlo}<=32\'d0;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:109: Operator SUB expects 64 bits on the RHS, but RHS\'s SIGNED generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n      6\'d17:begin {hi,lo}<=$signed({HI,LO})-$signed (A*B);  \n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:110: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n      {ALUResulthi,ALUResultlo}<=32\'d0;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:112: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'B\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n      6\'d5:{ALUResulthi,ALUResultlo}<=B<<A;  \n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:113: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'B\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n      6\'d9:{ALUResulthi,ALUResultlo}<=B>>A;  \n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:114: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'B\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n      6\'d13:{ALUResulthi,ALUResultlo}<=B>>>A;  \n                                        ^~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:116: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n      {ALUResulthi,ALUResultlo}<=32\'d0;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:119: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n      {ALUResulthi,ALUResultlo}<=32\'d0;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:121: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'HI\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n      6\'d31:{ALUResulthi,ALUResultlo}<=HI; \n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:122: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'LO\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n      6\'d23:{ALUResulthi,ALUResultlo}<=LO; \n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:125: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'A\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n         {ALUResulthi,ALUResultlo}<=A;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:129: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n          {ALUResulthi,ALUResultlo}<=32\'d0;\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:134: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'A\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n              {ALUResulthi,ALUResultlo}<=A;\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:138: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n            {ALUResulthi,ALUResultlo}<=32\'d0;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:143: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n              {ALUResulthi,ALUResultlo}<={{16{B[15]}},B[15:0]};\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:146: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n            {ALUResulthi,ALUResultlo}<={{24{B[7]}},B[7:0]};\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:150: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'B\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n       {ALUResulthi,ALUResultlo}<=B>>(A[4:0])|B<<(32-A[4:0]);\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:150: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'B\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n       {ALUResulthi,ALUResultlo}<=B>>(A[4:0])|B<<(32-A[4:0]);\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:153: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'B\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n            {ALUResulthi,ALUResultlo}<=B>>A|B<<(32-A);\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:153: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'B\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n            {ALUResulthi,ALUResultlo}<=B>>A|B<<(32-A);\n                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:155: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'B\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n        6\'d32:{ALUResulthi,ALUResultlo}<=B<<16;  \n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALU32Bit.v:158: Operator EQ expects 64 bits on the RHS, but RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                   : ... In instance ALU32Bit\n        if({ALUResulthi,ALUResultlo}==32\'d0)begin \n                                    ^~\n%Error: Exiting due to 48 warning(s)\n'
module ALU32Bit(Clk,en,ALUControl, A, B, ALUResultlo,ALUResulthi, Zero,move,HI,LO,gtzero,gezero,ltzero,lezero);
    input Clk,en;
	input [5:0] ALUControl;
	input [31:0] A, B;
    output reg move;
	output reg [31:0] ALUResultlo;
	output reg [31:0] ALUResulthi;
	output reg Zero;
	output reg [31:0]HI,LO;
	output reg gtzero;
	output reg gezero;
	output reg ltzero;
	output reg lezero;
	reg [31:0]hi,lo;
	initial begin 
	hi<=32'd0;
	lo<=32'd0;
	HI<=32'd0;
	LO<=32'd0;
	end 
   always@*begin 
    move<=0;
    gtzero<=0;
    gezero<=0;
    ltzero<=0;
    lezero<=0;
    case (ALUControl)
      6'd2:  {ALUResulthi,ALUResultlo}<=A+B;
      6'd6:  {ALUResulthi,ALUResultlo}<=A-B; 
      6'd0:  {ALUResulthi,ALUResultlo}<=A&B; 
      6'd28:  {ALUResulthi,ALUResultlo}<=A&{16'd0,B[15:0]};
      6'd1:  {ALUResulthi,ALUResultlo}<=A|B; 
      6'd27: {ALUResulthi,ALUResultlo}<=A|{16'd0,B[15:0]}; 
      6'd7:  {ALUResulthi,ALUResultlo}<=($signed (A)<$signed (B));
      6'd19: {ALUResulthi,ALUResultlo}<=(A<B);
      6'd8:  {ALUResulthi,ALUResultlo}<=A*B;
      6'd10:  {ALUResulthi,ALUResultlo}<=B<<A;
      6'd11:  {ALUResulthi,ALUResultlo}<=B>>A;
      6'd12:  {ALUResulthi,ALUResultlo}<=~(A|B);
      6'd3:  {ALUResulthi,ALUResultlo}<=(A^B);
      6'd22:  {ALUResulthi,ALUResultlo}<=A^{16'd0,B[15:0]};
      6'd33: begin
      if($signed(A)>$signed(32'd0))begin 
      gtzero<=1;
      end 
     end 
     6'd34: begin
           if(~($signed(A)<$signed(32'd0)))begin 
           gezero<=1;
           end
          end 
      6'd35: begin
                    if(($signed(A)<$signed(32'd0)))begin 
                    ltzero<=1;
                    end
                   end 
     6'd36: begin
               if(~($signed(A)>$signed(32'd0)))begin 
               lezero<=1;
               end
              end 
       6'd4: begin
        {hi,lo}<=$signed (A*B);
        {ALUResulthi,ALUResultlo}<=32'd0;
        end 
      6'd24: begin
      {hi,lo}<= (A*B);
      {ALUResulthi,ALUResultlo}<=32'd0;
     end 
      6'd16:begin {hi,lo}<=$signed({HI,LO})+$signed((A*B));
      {ALUResulthi,ALUResultlo}<=32'd0;
      end 
      6'd17:begin {hi,lo}<=$signed({HI,LO})-$signed (A*B);
      {ALUResulthi,ALUResultlo}<=32'd0;
      end 
      6'd5:{ALUResulthi,ALUResultlo}<=B<<A;
      6'd9:{ALUResulthi,ALUResultlo}<=B>>A;
      6'd13:{ALUResulthi,ALUResultlo}<=B>>>A;
      6'd30:begin hi<=$signed (A);
      {ALUResulthi,ALUResultlo}<=32'd0;
      end 
      6'd29:begin lo<=$signed (A);
      {ALUResulthi,ALUResultlo}<=32'd0;
      end 
      6'd31:{ALUResulthi,ALUResultlo}<=HI;
      6'd23:{ALUResulthi,ALUResultlo}<=LO;
      6'd14:begin 
      if(B!=32'b0)begin 
         {ALUResulthi,ALUResultlo}<=A;
         move<=1;
        end 
        else begin 
          {ALUResulthi,ALUResultlo}<=32'd0;
             end 
      end 
      6'd15:begin 
          if(B==32'b0)begin 
              {ALUResulthi,ALUResultlo}<=A;
              move<=1;
             end 
            else begin 
            {ALUResulthi,ALUResultlo}<=32'd0;
            end 
           end 
      6'd18:begin 
        if(A==32'd24)begin
              {ALUResulthi,ALUResultlo}<={{16{B[15]}},B[15:0]};
              end 
        else if(A==32'd16)begin
            {ALUResulthi,ALUResultlo}<={{24{B[7]}},B[7:0]};
               end 
         end 
      6'd20:begin
       {ALUResulthi,ALUResultlo}<=B>>(A[4:0])|B<<(32-A[4:0]);
      end 
       6'd21:begin
            {ALUResulthi,ALUResultlo}<=B>>A|B<<(32-A);
           end 
        6'd32:{ALUResulthi,ALUResultlo}<=B<<16;
    endcase 
    
        if({ALUResulthi,ALUResultlo}==32'd0)begin 
        Zero<=1;
        end 
        else begin 
        Zero<=0;
        end 
   end   
   always@(negedge Clk)begin
    if(en)begin
    {HI,LO}<={hi, lo};
    end  
   end 
endmodule
module ALU32Bit(Clk,en,ALUControl, A, B, ALUResultlo,ALUResulthi, Zero,move,HI,LO,gtzero,gezero,ltzero,lezero);

    input Clk,en;
	input [5:0] ALUControl;
	input [31:0] A, B;
    output reg move;
	output reg [31:0] ALUResultlo;
	output reg [31:0] ALUResulthi;
	output reg Zero;
	output reg [31:0]HI,LO;
	output reg gtzero;
	output reg gezero;
	output reg ltzero;
	output reg lezero;
	reg [31:0]hi,lo;
	initial begin 
	hi<=32'd0;
	lo<=32'd0;
	HI<=32'd0;
	LO<=32'd0;
	end 
   always@*begin 
    move<=0;
    gtzero<=0;
    gezero<=0;
    ltzero<=0;
    lezero<=0;
    case (ALUControl)
      6'd2:  {ALUResulthi,ALUResultlo}<=A+B;
      6'd6:  {ALUResulthi,ALUResultlo}<=A-B; 
      6'd0:  {ALUResulthi,ALUResultlo}<=A&B; 
      6'd28:  {ALUResulthi,ALUResultlo}<=A&{16'd0,B[15:0]};
      6'd1:  {ALUResulthi,ALUResultlo}<=A|B; 
      6'd27: {ALUResulthi,ALUResultlo}<=A|{16'd0,B[15:0]}; 
      6'd7:  {ALUResulthi,ALUResultlo}<=($signed (A)<$signed (B));
      6'd19: {ALUResulthi,ALUResultlo}<=(A<B);
      6'd8:  {ALUResulthi,ALUResultlo}<=A*B;
      6'd10:  {ALUResulthi,ALUResultlo}<=B<<A;
      6'd11:  {ALUResulthi,ALUResultlo}<=B>>A;
      6'd12:  {ALUResulthi,ALUResultlo}<=~(A|B);
      6'd3:  {ALUResulthi,ALUResultlo}<=(A^B);
      6'd22:  {ALUResulthi,ALUResultlo}<=A^{16'd0,B[15:0]};
      6'd33: begin
      if($signed(A)>$signed(32'd0))begin 
      gtzero<=1;
      end 
     end 
     6'd34: begin
           if(~($signed(A)<$signed(32'd0)))begin 
           gezero<=1;
           end
          end 
      6'd35: begin
                    if(($signed(A)<$signed(32'd0)))begin 
                    ltzero<=1;
                    end
                   end 
     6'd36: begin
               if(~($signed(A)>$signed(32'd0)))begin 
               lezero<=1;
               end
              end 
       6'd4: begin
        {hi,lo}<=$signed (A*B);
        {ALUResulthi,ALUResultlo}<=32'd0;
        end 
      6'd24: begin
      {hi,lo}<= (A*B);
      {ALUResulthi,ALUResultlo}<=32'd0;
     end 
      6'd16:begin {hi,lo}<=$signed({HI,LO})+$signed((A*B));
      {ALUResulthi,ALUResultlo}<=32'd0;
      end 
      6'd17:begin {hi,lo}<=$signed({HI,LO})-$signed (A*B);
      {ALUResulthi,ALUResultlo}<=32'd0;
      end 
      6'd5:{ALUResulthi,ALUResultlo}<=B<<A;
      6'd9:{ALUResulthi,ALUResultlo}<=B>>A;
      6'd13:{ALUResulthi,ALUResultlo}<=B>>>A;
      6'd30:begin hi<=$signed (A);
      {ALUResulthi,ALUResultlo}<=32'd0;
      end 
      6'd29:begin lo<=$signed (A);
      {ALUResulthi,ALUResultlo}<=32'd0;
      end 
      6'd31:{ALUResulthi,ALUResultlo}<=HI;
      6'd23:{ALUResulthi,ALUResultlo}<=LO;
      6'd14:begin 
      if(B!=32'b0)begin 
         {ALUResulthi,ALUResultlo}<=A;
         move<=1;
        end 
        else begin 
          {ALUResulthi,ALUResultlo}<=32'd0;
             end 
      end 
      6'd15:begin 
          if(B==32'b0)begin 
              {ALUResulthi,ALUResultlo}<=A;
              move<=1;
             end 
            else begin 
            {ALUResulthi,ALUResultlo}<=32'd0;
            end 
           end 
      6'd18:begin 
        if(A==32'd24)begin
              {ALUResulthi,ALUResultlo}<={{16{B[15]}},B[15:0]};
              end 
        else if(A==32'd16)begin
            {ALUResulthi,ALUResultlo}<={{24{B[7]}},B[7:0]};
               end 
         end 
      6'd20:begin
       {ALUResulthi,ALUResultlo}<=B>>(A[4:0])|B<<(32-A[4:0]);
      end 
       6'd21:begin
            {ALUResulthi,ALUResultlo}<=B>>A|B<<(32-A);
           end 
        6'd32:{ALUResulthi,ALUResultlo}<=B<<16;
    endcase 
    
        if({ALUResulthi,ALUResultlo}==32'd0)begin 
        Zero<=1;
        end 
        else begin 
        Zero<=0;
        end 
   end   
   always@(negedge Clk)begin
    if(en)begin
    {HI,LO}<={hi, lo};
    end  
   end 
endmodule