data/full_repos/permissive/138961980/powlib_std.v
 line:24: before: "if"
1: b'%Error: data/full_repos/permissive/138961980/powlib_std.v:195: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh.v\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh.sv\n             powlib_std.vh\n             powlib_std.vh.v\n             powlib_std.vh.sv\n             obj_dir/powlib_std.vh\n             obj_dir/powlib_std.vh.v\n             obj_dir/powlib_std.vh.sv\n%Error: data/full_repos/permissive/138961980/powlib_std.v:221: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:252: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:207: Define or directive not defined: \'`POWLIB_DW\'\n            wire [`POWLIB_DW-1:0] d0 = powlib_grayencode(d); \n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:233: Define or directive not defined: \'`POWLIB_DW\'\n            wire [`POWLIB_DW-1:0] d0 = powlib_graydecode(d); \n                  ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module powlib_ffsync(d,q,aclk,bclk,arst,brst,vld);



  parameter                W    = 1;
  parameter        [W-1:0] INIT = 0;
  parameter                EAR  = 0;
  parameter                EVLD = 0;
  parameter                S    = 2;
  input     wire   [W-1:0] d;
  input     wire           vld;
  input     wire           aclk, bclk;
  input     wire           arst, brst;
  output    wire   [W-1:0] q;
  
            genvar         i;
            wire   [W-1:0] ds [0:S];
            wire   [W-1:0] aq;
  
  powlib_flipflop #(.W(W),.INIT(INIT),.EAR(EAR),.EVLD(EVLD))  aff (.d(d),.q(aq),.clk(aclk),.rst(arst),.vld(vld));
  
  for (i=0; i<S; i=i+1) begin
    powlib_flipflop #(.W(W),.INIT(INIT),.EAR(EAR))  bffs (.d(ds[i]),.q(ds[i+1]),.clk(bclk),.rst(brst));
  end
  
  if (S<1) begin
    assign q     = aq;
  end else begin
    assign ds[0] = aq;
    assign q     = ds[S];
  end 
  
endmodule
module powlib_ffsync(d,q,aclk,bclk,arst,brst,vld);




  parameter                W    = 1;
  parameter        [W-1:0] INIT = 0;
  parameter                EAR  = 0;
  parameter                EVLD = 0;
  parameter                S    = 2;
  input     wire   [W-1:0] d;
  input     wire           vld;
  input     wire           aclk, bclk;
  input     wire           arst, brst;
  output    wire   [W-1:0] q;
  
            genvar         i;
            wire   [W-1:0] ds [0:S];
            wire   [W-1:0] aq;
  
  powlib_flipflop #(.W(W),.INIT(INIT),.EAR(EAR),.EVLD(EVLD))  aff (.d(d),.q(aq),.clk(aclk),.rst(arst),.vld(vld));
  
  for (i=0; i<S; i=i+1) begin
    powlib_flipflop #(.W(W),.INIT(INIT),.EAR(EAR))  bffs (.d(ds[i]),.q(ds[i+1]),.clk(bclk),.rst(brst));
  end
  
  if (S<1) begin
    assign q     = aq;
  end else begin
    assign ds[0] = aq;
    assign q     = ds[S];
  end 
  
endmodule