data/full_repos/permissive/148200700/Quartus/ip/axi_bridge_for_acp_128/axi_bridge_for_acp_128.v
data/verilator_xmls/a94efd4b-4ac3-470b-8d9f-4862fd25b80c.xml
module axi_bridge_for_acp_128 (
		input  wire         clk,
		input  wire         reset,
		
		output wire [31:0]  axm_m0_araddr,
		output wire [1:0]   axm_m0_arburst,
		output wire [3:0]   axm_m0_arcache,
		output wire [7:0]   axm_m0_arid,
		output wire [3:0]   axm_m0_arlen,
		output wire [1:0]   axm_m0_arlock,
		output wire [2:0]   axm_m0_arprot,
		input  wire         axm_m0_arready,
		output wire [2:0]   axm_m0_arsize,
		output wire [4:0]   axm_m0_aruser,
		output wire         axm_m0_arvalid,
		output wire [31:0]  axm_m0_awaddr,
		output wire [1:0]   axm_m0_awburst,
		output wire [3:0]   axm_m0_awcache,
		output wire [7:0]   axm_m0_awid,
		output wire [3:0]   axm_m0_awlen,
		output wire [1:0]   axm_m0_awlock,
		output wire [2:0]   axm_m0_awprot,
		input  wire         axm_m0_awready,
		output wire [2:0]   axm_m0_awsize,
		output wire [4:0]   axm_m0_awuser,
		output wire         axm_m0_awvalid,
		input  wire [7:0]   axm_m0_bid,
		output wire         axm_m0_bready,
		input  wire [1:0]   axm_m0_bresp,
		input  wire         axm_m0_bvalid,
		input  wire [127:0] axm_m0_rdata,
		input  wire [7:0]   axm_m0_rid,
		input  wire         axm_m0_rlast,
		output wire         axm_m0_rready,
		input  wire [1:0]   axm_m0_rresp,
		input  wire         axm_m0_rvalid,
		output wire [127:0] axm_m0_wdata,
		output wire [7:0]   axm_m0_wid,
		output wire         axm_m0_wlast,
		input  wire         axm_m0_wready,
		output wire [15:0]  axm_m0_wstrb,
		output wire         axm_m0_wvalid,
		
		input  wire [31:0]  axs_s0_araddr,
		input  wire [1:0]   axs_s0_arburst,
		input  wire [3:0]   axs_s0_arcache,
		input  wire [7:0]   axs_s0_arid,
		input  wire [3:0]   axs_s0_arlen,
		input  wire [1:0]   axs_s0_arlock,
		input  wire [2:0]   axs_s0_arprot,
		output wire         axs_s0_arready,
		input  wire [2:0]   axs_s0_arsize,
		input  wire [4:0]   axs_s0_aruser,
		input  wire         axs_s0_arvalid,
		input  wire [31:0]  axs_s0_awaddr,
		input  wire [1:0]   axs_s0_awburst,
		input  wire [3:0]   axs_s0_awcache,
		input  wire [7:0]   axs_s0_awid,
		input  wire [3:0]   axs_s0_awlen,
		input  wire [1:0]   axs_s0_awlock,
		input  wire [2:0]   axs_s0_awprot,
		output wire         axs_s0_awready,
		input  wire [2:0]   axs_s0_awsize,
		input  wire [4:0]   axs_s0_awuser,
		input  wire         axs_s0_awvalid,
		output wire [7:0]   axs_s0_bid,
		input  wire         axs_s0_bready,
		output wire [1:0]   axs_s0_bresp,
		output wire         axs_s0_bvalid,
		output wire [127:0] axs_s0_rdata,
		output wire [7:0]   axs_s0_rid,
		output wire         axs_s0_rlast,
		input  wire         axs_s0_rready,
		output wire [1:0]   axs_s0_rresp,
		output wire         axs_s0_rvalid,
		input  wire [127:0] axs_s0_wdata,
		input  wire [7:0]   axs_s0_wid,
		input  wire         axs_s0_wlast,
		output wire         axs_s0_wready,
		input  wire [15:0]  axs_s0_wstrb,
		input  wire         axs_s0_wvalid
	);

	assign axm_m0_araddr = axs_s0_araddr;
	assign axm_m0_arburst = axs_s0_arburst;
	assign axm_m0_arcache = 4'b1111;
	assign axm_m0_arid = axs_s0_arid;
	assign axm_m0_arlen = axs_s0_arlen;
	assign axm_m0_arlock = axs_s0_arlock;
	assign axm_m0_arprot = 3'b000;
	assign axm_m0_arsize = axs_s0_arsize;
	assign axm_m0_aruser = 5'b11111;
	assign axm_m0_arvalid = axs_s0_arvalid;
	assign axm_m0_awaddr = axs_s0_awaddr;
	assign axm_m0_awburst = axs_s0_awburst;
	assign axm_m0_awcache = 4'b1111;
	assign axm_m0_awid = axs_s0_awid;
	assign axm_m0_awlen = axs_s0_awlen;
	assign axm_m0_awlock = axs_s0_awlock;
	assign axm_m0_awprot = 3'b000;
	assign axm_m0_awsize = axs_s0_awsize;
	assign axm_m0_awuser = 5'b11111;
	assign axm_m0_awvalid = axs_s0_awvalid;
	assign axm_m0_bready = axs_s0_bready;
	assign axm_m0_rready = axs_s0_rready;
	assign axm_m0_wdata = axs_s0_wdata;
	assign axm_m0_wid = axs_s0_wid;
	assign axm_m0_wlast = axs_s0_wlast;
	assign axm_m0_wstrb = axs_s0_wstrb;
	assign axm_m0_wvalid = axs_s0_wvalid;
	assign axs_s0_arready = axm_m0_arready;
	assign axs_s0_awready = axm_m0_awready;
	assign axs_s0_bid = axm_m0_bid;
	assign axs_s0_bresp = axm_m0_bresp;
	assign axs_s0_bvalid = axm_m0_bvalid;
	assign axs_s0_rdata = axm_m0_rdata;
	assign axs_s0_rid = axm_m0_rid;
	assign axs_s0_rlast = axm_m0_rlast;
	assign axs_s0_rresp = axm_m0_rresp;
	assign axs_s0_rvalid = axm_m0_rvalid;
	assign axs_s0_wready = axm_m0_wready;
	
endmodule
module axi_bridge_for_acp_128 (
		input  wire         clk,
		input  wire         reset,
		
		output wire [31:0]  axm_m0_araddr,
		output wire [1:0]   axm_m0_arburst,
		output wire [3:0]   axm_m0_arcache,
		output wire [7:0]   axm_m0_arid,
		output wire [3:0]   axm_m0_arlen,
		output wire [1:0]   axm_m0_arlock,
		output wire [2:0]   axm_m0_arprot,
		input  wire         axm_m0_arready,
		output wire [2:0]   axm_m0_arsize,
		output wire [4:0]   axm_m0_aruser,
		output wire         axm_m0_arvalid,
		output wire [31:0]  axm_m0_awaddr,
		output wire [1:0]   axm_m0_awburst,
		output wire [3:0]   axm_m0_awcache,
		output wire [7:0]   axm_m0_awid,
		output wire [3:0]   axm_m0_awlen,
		output wire [1:0]   axm_m0_awlock,
		output wire [2:0]   axm_m0_awprot,
		input  wire         axm_m0_awready,
		output wire [2:0]   axm_m0_awsize,
		output wire [4:0]   axm_m0_awuser,
		output wire         axm_m0_awvalid,
		input  wire [7:0]   axm_m0_bid,
		output wire         axm_m0_bready,
		input  wire [1:0]   axm_m0_bresp,
		input  wire         axm_m0_bvalid,
		input  wire [127:0] axm_m0_rdata,
		input  wire [7:0]   axm_m0_rid,
		input  wire         axm_m0_rlast,
		output wire         axm_m0_rready,
		input  wire [1:0]   axm_m0_rresp,
		input  wire         axm_m0_rvalid,
		output wire [127:0] axm_m0_wdata,
		output wire [7:0]   axm_m0_wid,
		output wire         axm_m0_wlast,
		input  wire         axm_m0_wready,
		output wire [15:0]  axm_m0_wstrb,
		output wire         axm_m0_wvalid,
		
		input  wire [31:0]  axs_s0_araddr,
		input  wire [1:0]   axs_s0_arburst,
		input  wire [3:0]   axs_s0_arcache,
		input  wire [7:0]   axs_s0_arid,
		input  wire [3:0]   axs_s0_arlen,
		input  wire [1:0]   axs_s0_arlock,
		input  wire [2:0]   axs_s0_arprot,
		output wire         axs_s0_arready,
		input  wire [2:0]   axs_s0_arsize,
		input  wire [4:0]   axs_s0_aruser,
		input  wire         axs_s0_arvalid,
		input  wire [31:0]  axs_s0_awaddr,
		input  wire [1:0]   axs_s0_awburst,
		input  wire [3:0]   axs_s0_awcache,
		input  wire [7:0]   axs_s0_awid,
		input  wire [3:0]   axs_s0_awlen,
		input  wire [1:0]   axs_s0_awlock,
		input  wire [2:0]   axs_s0_awprot,
		output wire         axs_s0_awready,
		input  wire [2:0]   axs_s0_awsize,
		input  wire [4:0]   axs_s0_awuser,
		input  wire         axs_s0_awvalid,
		output wire [7:0]   axs_s0_bid,
		input  wire         axs_s0_bready,
		output wire [1:0]   axs_s0_bresp,
		output wire         axs_s0_bvalid,
		output wire [127:0] axs_s0_rdata,
		output wire [7:0]   axs_s0_rid,
		output wire         axs_s0_rlast,
		input  wire         axs_s0_rready,
		output wire [1:0]   axs_s0_rresp,
		output wire         axs_s0_rvalid,
		input  wire [127:0] axs_s0_wdata,
		input  wire [7:0]   axs_s0_wid,
		input  wire         axs_s0_wlast,
		output wire         axs_s0_wready,
		input  wire [15:0]  axs_s0_wstrb,
		input  wire         axs_s0_wvalid
	);


	assign axm_m0_araddr = axs_s0_araddr;
	assign axm_m0_arburst = axs_s0_arburst;
	assign axm_m0_arcache = 4'b1111;
	assign axm_m0_arid = axs_s0_arid;
	assign axm_m0_arlen = axs_s0_arlen;
	assign axm_m0_arlock = axs_s0_arlock;
	assign axm_m0_arprot = 3'b000;
	assign axm_m0_arsize = axs_s0_arsize;
	assign axm_m0_aruser = 5'b11111;
	assign axm_m0_arvalid = axs_s0_arvalid;
	assign axm_m0_awaddr = axs_s0_awaddr;
	assign axm_m0_awburst = axs_s0_awburst;
	assign axm_m0_awcache = 4'b1111;
	assign axm_m0_awid = axs_s0_awid;
	assign axm_m0_awlen = axs_s0_awlen;
	assign axm_m0_awlock = axs_s0_awlock;
	assign axm_m0_awprot = 3'b000;
	assign axm_m0_awsize = axs_s0_awsize;
	assign axm_m0_awuser = 5'b11111;
	assign axm_m0_awvalid = axs_s0_awvalid;
	assign axm_m0_bready = axs_s0_bready;
	assign axm_m0_rready = axs_s0_rready;
	assign axm_m0_wdata = axs_s0_wdata;
	assign axm_m0_wid = axs_s0_wid;
	assign axm_m0_wlast = axs_s0_wlast;
	assign axm_m0_wstrb = axs_s0_wstrb;
	assign axm_m0_wvalid = axs_s0_wvalid;
	assign axs_s0_arready = axm_m0_arready;
	assign axs_s0_awready = axm_m0_awready;
	assign axs_s0_bid = axm_m0_bid;
	assign axs_s0_bresp = axm_m0_bresp;
	assign axs_s0_bvalid = axm_m0_bvalid;
	assign axs_s0_rdata = axm_m0_rdata;
	assign axs_s0_rid = axm_m0_rid;
	assign axs_s0_rlast = axm_m0_rlast;
	assign axs_s0_rresp = axm_m0_rresp;
	assign axs_s0_rvalid = axm_m0_rvalid;
	assign axs_s0_wready = axm_m0_wready;
	
endmodule