data/full_repos/permissive/151904248/Triple Buffer/dummy_memory.v
1: b'%Error: Cannot find file containing module: Buffer,data/full_repos/permissive/151904248\n        ... Looked in:\n             data/full_repos/permissive/151904248/Triple/Buffer,data/full_repos/permissive/151904248\n             data/full_repos/permissive/151904248/Triple/Buffer,data/full_repos/permissive/151904248.v\n             data/full_repos/permissive/151904248/Triple/Buffer,data/full_repos/permissive/151904248.sv\n             Buffer,data/full_repos/permissive/151904248\n             Buffer,data/full_repos/permissive/151904248.v\n             Buffer,data/full_repos/permissive/151904248.sv\n             obj_dir/Buffer,data/full_repos/permissive/151904248\n             obj_dir/Buffer,data/full_repos/permissive/151904248.v\n             obj_dir/Buffer,data/full_repos/permissive/151904248.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/151904248/Triple\n%Error: Cannot find file containing module: Buffer/dummy_memory.v\n%Error: Exiting due to 3 error(s)\n'
module d_mem(

input wire clk,
input wire reset,
input wire oe,
input wire we,
input wire [15:0] addr,
inout wire [15:0] data_io

);


reg [15:0] data_out;


reg [15:0] mem [0:65535];
reg [15:0] i;

initial begin

	data_out <= 16'b0;





end

always @ (negedge we or negedge reset) begin

	if(reset == 1'b0) begin

		for (i = 0; i < 65535; i = i +1) begin   	  	
			mem[i] <= 8'b0;
		end
	
	end
	else begin
	
		mem[addr] <= data_io;
	
	
	end
	
end

always @ (negedge oe or negedge reset) begin
	
	if(reset == 1'b0) begin
		
		data_out <= 1'b0;
	
	end
	else begin
	
		data_out <= mem[addr];
	
	end
		
end

assign data_io =  (!oe) ? data_out : 16'bz;

endmodule
module d_mem(

input wire clk,
input wire reset,
input wire oe,
input wire we,
input wire [15:0] addr,
inout wire [15:0] data_io

);



reg [15:0] data_out;


reg [15:0] mem [0:65535];
reg [15:0] i;

initial begin

	data_out <= 16'b0;





end

always @ (negedge we or negedge reset) begin

	if(reset == 1'b0) begin

		for (i = 0; i < 65535; i = i +1) begin   	  	
			mem[i] <= 8'b0;
		end
	
	end
	else begin
	
		mem[addr] <= data_io;
	
	
	end
	
end

always @ (negedge oe or negedge reset) begin
	
	if(reset == 1'b0) begin
		
		data_out <= 1'b0;
	
	end
	else begin
	
		data_out <= mem[addr];
	
	end
		
end

assign data_io =  (!oe) ? data_out : 16'bz;

endmodule