data/full_repos/permissive/13111265/verilog/src/transmitters/TxUart.v
 line:65: before: "if"
1: b"%Error: data/full_repos/permissive/13111265/verilog/src/transmitters/TxUart.v:66: Cannot find file containing module: 'Fifo'\n    Fifo #(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/13111265/verilog/src/transmitters,data/full_repos/permissive/13111265/Fifo\n             data/full_repos/permissive/13111265/verilog/src/transmitters,data/full_repos/permissive/13111265/Fifo.v\n             data/full_repos/permissive/13111265/verilog/src/transmitters,data/full_repos/permissive/13111265/Fifo.sv\n             Fifo\n             Fifo.v\n             Fifo.sv\n             obj_dir/Fifo\n             obj_dir/Fifo.v\n             obj_dir/Fifo.sv\n%Error: Exiting due to 1 error(s)\n"
module TxUart #(
    parameter LOG2_DEPTH = 4
)
(

    input clk,
    input rst,
    input x16BaudStrobe,
    input [7:0] dataIn,
    input write,

    output reg  serialOut,
    output wire dataPresent,
    output wire halfFull,
    output wire full
);





localparam SM_IDLE  =   0;
localparam SM_START =   1;
localparam SM_STOP  =   2;
localparam SM_BIT0  =   8;
localparam SM_BIT1  =   9;
localparam SM_BIT2  =  10;
localparam SM_BIT3  =  11;
localparam SM_BIT4  =  12;
localparam SM_BIT5  =  13;
localparam SM_BIT6  =  14;
localparam SM_BIT7  =  15;





wire [7:0] fifoData;

reg [7:0] data;
reg [7:0] dataInReg;
reg [3:0] state;
reg [3:0] div;
reg read;
reg nextBit;
reg busy;





if (LOG2_DEPTH > 0) begin
    Fifo #(
        .WIDTH(8),
        .LOG2_DEPTH(LOG2_DEPTH)
    )
    txFifo (
        .clk(clk),
        .rst(rst),
        .write(write),
        .read(read),
        .dataIn(dataIn),

        .dataOut(fifoData),
        .dataPresent(dataPresent),
        .halfFull(halfFull),
        .full(full)
    );
end
else begin

    assign fifoData    = dataInReg;
    assign dataPresent = busy;
    assign halfFull    = busy;
    assign full        = busy;
    always @(posedge clk) begin
        if (write) begin
            dataInReg <= dataIn;
        end
        busy <= busy ? (~read & busy) : write;
    end
end

initial begin
    busy       = 1'b0;
    data       = 'd0;
    div        = 'd0;
    nextBit    = 1'b0;
    read       = 1'b0;
    serialOut  = 1'b1;
    state      = SM_IDLE;
end


always @(posedge clk) begin
    data <= fifoData;


    div     <= (x16BaudStrobe) ? div + 4'd1 : div;
    nextBit <= &div & x16BaudStrobe;
    read    <= &div & x16BaudStrobe & (state == SM_BIT7);


    if ((state == SM_IDLE) || (state == SM_STOP)) begin
        serialOut <= 1'b1;
    end
    else if (state == SM_START) begin
        serialOut <= 1'b0;
    end
    else begin
        serialOut <= data[state[2:0]];
    end


    if (nextBit && dataPresent) begin
        case (state)
            SM_IDLE  : state <= SM_START;
            SM_START : state <= SM_BIT0;
            SM_BIT0  : state <= SM_BIT1;
            SM_BIT1  : state <= SM_BIT2;
            SM_BIT2  : state <= SM_BIT3;
            SM_BIT3  : state <= SM_BIT4;
            SM_BIT4  : state <= SM_BIT5;
            SM_BIT5  : state <= SM_BIT6;
            SM_BIT6  : state <= SM_BIT7;
            SM_BIT7  : state <= SM_STOP;
            SM_STOP  : state <= SM_START;
            default  : state <= SM_IDLE;
        endcase
    end
    else if (nextBit) begin
        state <= SM_IDLE;
    end
end

endmodule
module TxUart #(
    parameter LOG2_DEPTH = 4
)
(

    input clk,
    input rst,
    input x16BaudStrobe,
    input [7:0] dataIn,
    input write,

    output reg  serialOut,
    output wire dataPresent,
    output wire halfFull,
    output wire full
);






localparam SM_IDLE  =   0;
localparam SM_START =   1;
localparam SM_STOP  =   2;
localparam SM_BIT0  =   8;
localparam SM_BIT1  =   9;
localparam SM_BIT2  =  10;
localparam SM_BIT3  =  11;
localparam SM_BIT4  =  12;
localparam SM_BIT5  =  13;
localparam SM_BIT6  =  14;
localparam SM_BIT7  =  15;





wire [7:0] fifoData;

reg [7:0] data;
reg [7:0] dataInReg;
reg [3:0] state;
reg [3:0] div;
reg read;
reg nextBit;
reg busy;





if (LOG2_DEPTH > 0) begin
    Fifo #(
        .WIDTH(8),
        .LOG2_DEPTH(LOG2_DEPTH)
    )
    txFifo (
        .clk(clk),
        .rst(rst),
        .write(write),
        .read(read),
        .dataIn(dataIn),

        .dataOut(fifoData),
        .dataPresent(dataPresent),
        .halfFull(halfFull),
        .full(full)
    );
end
else begin

    assign fifoData    = dataInReg;
    assign dataPresent = busy;
    assign halfFull    = busy;
    assign full        = busy;
    always @(posedge clk) begin
        if (write) begin
            dataInReg <= dataIn;
        end
        busy <= busy ? (~read & busy) : write;
    end
end

initial begin
    busy       = 1'b0;
    data       = 'd0;
    div        = 'd0;
    nextBit    = 1'b0;
    read       = 1'b0;
    serialOut  = 1'b1;
    state      = SM_IDLE;
end


always @(posedge clk) begin
    data <= fifoData;


    div     <= (x16BaudStrobe) ? div + 4'd1 : div;
    nextBit <= &div & x16BaudStrobe;
    read    <= &div & x16BaudStrobe & (state == SM_BIT7);


    if ((state == SM_IDLE) || (state == SM_STOP)) begin
        serialOut <= 1'b1;
    end
    else if (state == SM_START) begin
        serialOut <= 1'b0;
    end
    else begin
        serialOut <= data[state[2:0]];
    end


    if (nextBit && dataPresent) begin
        case (state)
            SM_IDLE  : state <= SM_START;
            SM_START : state <= SM_BIT0;
            SM_BIT0  : state <= SM_BIT1;
            SM_BIT1  : state <= SM_BIT2;
            SM_BIT2  : state <= SM_BIT3;
            SM_BIT3  : state <= SM_BIT4;
            SM_BIT4  : state <= SM_BIT5;
            SM_BIT5  : state <= SM_BIT6;
            SM_BIT6  : state <= SM_BIT7;
            SM_BIT7  : state <= SM_STOP;
            SM_STOP  : state <= SM_START;
            default  : state <= SM_IDLE;
        endcase
    end
    else if (nextBit) begin
        state <= SM_IDLE;
    end
end

endmodule