data/full_repos/permissive/169294490/FPGA/src/VGA/vga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169294490/FPGA/src/VGA/vga.v:41: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                          : ... In instance vga_controller.hs\n reg [10:0] count = 10\'b0000000000;\n                    ^~~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169294490/FPGA/src/VGA/vga.v:6: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance vga_controller.vs\n reg [10:0] count = 10\'b0000000000;\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169294490/FPGA/src/VGA/vga.v:102: Cannot find file containing module: \'framebuffer\'\n framebuffer   fb(clk50, rst, blank, red_out, green_out, blue_out, line_clk, vblank, fb_data, fb_addr, fb_we, framebuffer_addr_rd, framebuffer_data_rd, framebuffer_rd_en);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169294490/FPGA/src/VGA,data/full_repos/permissive/169294490/framebuffer\n             data/full_repos/permissive/169294490/FPGA/src/VGA,data/full_repos/permissive/169294490/framebuffer.v\n             data/full_repos/permissive/169294490/FPGA/src/VGA,data/full_repos/permissive/169294490/framebuffer.sv\n             framebuffer\n             framebuffer.v\n             framebuffer.sv\n             obj_dir/framebuffer\n             obj_dir/framebuffer.v\n             obj_dir/framebuffer.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module vsync(line_clk, vsync_out, blank_out);
	input line_clk;
	output vsync_out;
	output blank_out;

	reg [10:0] count = 10'b0000000000;
	reg vsync  = 0;
	reg blank  = 0;

	always @(posedge line_clk)
	if (count < 666)
		count <= count + 11'h1;
	else
		count <= 0;

	always @(posedge line_clk)
	if (count < 600)
		blank 		<= 0;
	else
		blank 		<= 1;

	always @(posedge line_clk)
	begin
		if (count < 637)
			vsync 	<= 1;
		else if (count >= 637 && count < 643)
			vsync 	<= 0;
		else if (count >= 643)
			vsync 	<= 1;
	end

	assign vsync_out  = vsync;
	assign blank_out  = blank;

endmodule
module vsync(line_clk, vsync_out, blank_out);

	input line_clk;
	output vsync_out;
	output blank_out;

	reg [10:0] count = 10'b0000000000;
	reg vsync  = 0;
	reg blank  = 0;

	always @(posedge line_clk)
	if (count < 666)
		count <= count + 11'h1;
	else
		count <= 0;

	always @(posedge line_clk)
	if (count < 600)
		blank 		<= 0;
	else
		blank 		<= 1;

	always @(posedge line_clk)
	begin
		if (count < 637)
			vsync 	<= 1;
		else if (count >= 637 && count < 643)
			vsync 	<= 0;
		else if (count >= 643)
			vsync 	<= 1;
	end

	assign vsync_out  = vsync;
	assign blank_out  = blank;

endmodule