data/full_repos/permissive/190755935/src/tutorial/rtl/add_accum.v
1: b'%Warning-WIDTH: data/full_repos/permissive/190755935/src/tutorial/rtl/add_accum.v:13: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'x\' generates 4 bits.\n                                                                                    : ... In instance add_accum\n                accumsum <= accumsum + x;\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module add_accum( clock, reset, x, valid, accumsum );
    input clock;
    input reset;
    input [3:0] x;
    input valid;
    output reg [7:0] accumsum;

    always @(posedge clock) begin
        if ( reset )
            accumsum <= 0;
        else
            if ( valid )
                accumsum <= accumsum + x;
    end
endmodule
module add_accum( clock, reset, x, valid, accumsum );

    input clock;
    input reset;
    input [3:0] x;
    input valid;
    output reg [7:0] accumsum;

    always @(posedge clock) begin
        if ( reset )
            accumsum <= 0;
        else
            if ( valid )
                accumsum <= accumsum + x;
    end
endmodule