data/full_repos/permissive/193530477/source codes/STATE_CONTROL.v
1: b'%Error: Cannot find file containing module: codes,data/full_repos/permissive/193530477\n        ... Looked in:\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.v\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.sv\n             codes,data/full_repos/permissive/193530477\n             codes,data/full_repos/permissive/193530477.v\n             codes,data/full_repos/permissive/193530477.sv\n             obj_dir/codes,data/full_repos/permissive/193530477\n             obj_dir/codes,data/full_repos/permissive/193530477.v\n             obj_dir/codes,data/full_repos/permissive/193530477.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/193530477/source\n%Error: Cannot find file containing module: codes/STATE_CONTROL.v\n%Error: Exiting due to 3 error(s)\n'
module STATE_CONTROL (
	input clk,
	input rst_n,
	input [3:0] switch,
	output reg[3:0] cstate,
	output reg[9:0] end_addr,
	output reg[9:0] start_addr
	);
	
	parameter K1 = 4'b0001;
	parameter K2 = 4'b0010;
	parameter STATE1 = 4'b0001;
	parameter STATE2 = 4'b0010;
	parameter STATE3 = 4'b0011;
	
	reg[3:0] nstate;
	

   always @ (posedge clk or negedge rst_n) begin
		if(!rst_n)	cstate <= STATE1;
		else			cstate <= nstate;
	end 

	always @ (cstate or switch) begin
		case(cstate)
			STATE1: if 	(switch == K1)  nstate <= STATE3;
				 else if(switch == K2)	 nstate <= STATE2;
				 else nstate <= STATE1;
			STATE2: if  (switch == K2)  nstate <= STATE1;
				 else if (switch == K1)  nstate <= STATE3;
				 else nstate <= STATE2;
			STATE3:if  (switch == K1)   nstate <= STATE1;
				 else if (switch == K2)  nstate <= STATE2;
				 else nstate <= STATE3;
			default: nstate <= STATE1;
		endcase
	end

	always @ (cstate or switch) begin
		case(cstate)
			STATE1: begin end_addr = 10'd138; start_addr = 10'd0;		end
			STATE2: begin end_addr = 10'd335; start_addr = 10'd139;	end
			STATE3: begin end_addr = 10'd138; start_addr = 10'd0;		end
			default: begin end_addr = 10'd138; start_addr = 10'd0;	end
		endcase	
	end
	
endmodule
module STATE_CONTROL (
	input clk,
	input rst_n,
	input [3:0] switch,
	output reg[3:0] cstate,
	output reg[9:0] end_addr,
	output reg[9:0] start_addr
	);

	
	parameter K1 = 4'b0001;
	parameter K2 = 4'b0010;
	parameter STATE1 = 4'b0001;
	parameter STATE2 = 4'b0010;
	parameter STATE3 = 4'b0011;
	
	reg[3:0] nstate;
	

   always @ (posedge clk or negedge rst_n) begin
		if(!rst_n)	cstate <= STATE1;
		else			cstate <= nstate;
	end 

	always @ (cstate or switch) begin
		case(cstate)
			STATE1: if 	(switch == K1)  nstate <= STATE3;
				 else if(switch == K2)	 nstate <= STATE2;
				 else nstate <= STATE1;
			STATE2: if  (switch == K2)  nstate <= STATE1;
				 else if (switch == K1)  nstate <= STATE3;
				 else nstate <= STATE2;
			STATE3:if  (switch == K1)   nstate <= STATE1;
				 else if (switch == K2)  nstate <= STATE2;
				 else nstate <= STATE3;
			default: nstate <= STATE1;
		endcase
	end

	always @ (cstate or switch) begin
		case(cstate)
			STATE1: begin end_addr = 10'd138; start_addr = 10'd0;		end
			STATE2: begin end_addr = 10'd335; start_addr = 10'd139;	end
			STATE3: begin end_addr = 10'd138; start_addr = 10'd0;		end
			default: begin end_addr = 10'd138; start_addr = 10'd0;	end
		endcase	
	end
	
endmodule