data/full_repos/permissive/123304708/src/common/mux2.v
data/verilator_xmls/1d21c929-6647-475e-920c-0ef719755790.xml
module mux2(
    input [31:0] data0,
    input [31:0] data1,
    input wire  signal,
    output reg [31:0] data
);

always @(*) 
begin
    case(signal)
        1'b0:
            data = data0;
        1'b1:
            data = data1;
        default:
            data = 32'b0;
    endcase
end
endmodule
module mux2(
    input [31:0] data0,
    input [31:0] data1,
    input wire  signal,
    output reg [31:0] data
);


always @(*) 
begin
    case(signal)
        1'b0:
            data = data0;
        1'b1:
            data = data1;
        default:
            data = 32'b0;
    endcase
end
endmodule