data/full_repos/permissive/205055389/test/tkgate/l2.v
 line:33: before: "."
1: b"%Error: data/full_repos/permissive/205055389/test/tkgate/l2.v:33: syntax error, unexpected '.', expecting '['\nmodule _GGREG8 #(.Dsetup(1), .Dhold(1), .Dck_q(1)) (Q, D, EN, CLR, CK);\n                 ^\n%Error: data/full_repos/permissive/205055389/test/tkgate/l2.v:39: syntax error, unexpected assign\n  assign #Dck_q Q = Qreg;\n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/test/tkgate/l2.v:53: syntax error, unexpected '.', expecting '['\nmodule _GGAND2 #(.Diz(1)) (I0, I1, Z);\n                 ^\n%Error: Exiting due to 3 error(s)\n"
module main;
wire [7:0] w6;
wire w7;
wire w4;
wire [7:0] w3;
wire w0;
wire w1;
wire w8;
wire w2;
wire w10;
wire w5;
wire w9;
wire FOOBAR;




  _GGREG8 #(10, 10, 20) g4 (.Q(w3), .D(w6), .EN(w8), .CLR(w9), .CK(w10));

  _GGAND2 #(6) g2 (.I0(w2), .I1(FOOBAR), .Z(w7));
  _GGAND2 #(6) g1 (.I0(FOOBAR), .I1(w4), .Z(w5));
  _GGAND2 #(6) g0 (.I0(w0), .I1(w1), .Z(FOOBAR));

endmodule
module main;

wire [7:0] w6;
wire w7;
wire w4;
wire [7:0] w3;
wire w0;
wire w1;
wire w8;
wire w2;
wire w10;
wire w5;
wire w9;
wire FOOBAR;




  _GGREG8 #(10, 10, 20) g4 (.Q(w3), .D(w6), .EN(w8), .CLR(w9), .CK(w10));

  _GGAND2 #(6) g2 (.I0(w2), .I1(FOOBAR), .Z(w7));
  _GGAND2 #(6) g1 (.I0(FOOBAR), .I1(w4), .Z(w5));
  _GGAND2 #(6) g0 (.I0(w0), .I1(w1), .Z(FOOBAR));

endmodule