data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial_2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial_2.v:21: Operator SUB expects 33 bits on the LHS, but LHS\'s VARREF \'a_r\' generates 16 bits.\n                                                                                                      : ... In instance complexmulttrial2\nassign temp_r_r=a_r-b_r;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial_2.v:21: Operator SUB expects 33 bits on the RHS, but RHS\'s VARREF \'b_r\' generates 16 bits.\n                                                                                                      : ... In instance complexmulttrial2\nassign temp_r_r=a_r-b_r;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial_2.v:22: Operator SUB expects 33 bits on the LHS, but LHS\'s VARREF \'a_i\' generates 16 bits.\n                                                                                                      : ... In instance complexmulttrial2\nassign temp_i_i=a_i-b_i;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial_2.v:22: Operator SUB expects 33 bits on the RHS, but RHS\'s VARREF \'b_i\' generates 16 bits.\n                                                                                                      : ... In instance complexmulttrial2\nassign temp_i_i=a_i-b_i;\n                   ^\n%Error: Exiting due to 4 warning(s)\n'
module complexmulttrial2(
input [15:0] a_r,
input [15:0] a_i,
input [15:0] b_r,
input [15:0] b_i,
input [15:0] w_r,
input [15:0] w_i,
output [15:0] x_r,
output [15:0] x_i,
output [15:0] y_r,
output [15:0] y_i,
output [32:0] temp_r,
output [32:0] temp_i);


wire [32:0] temp_r_r;
wire [32:0] temp_i_i;

assign x_r = a_r + b_r;
assign x_i = a_i + b_i;
assign temp_r_r=a_r-b_r;
assign temp_i_i=a_i-b_i;
assign temp_r=(temp_r_r)*(w_r) - (temp_i_i)*(w_i);
assign temp_i=(temp_i_i)*(w_r) - (temp_r_r)*(w_i);




assign y_r[15:0] = temp_r[32:17];
assign y_i[15:0] = temp_i[32:17];



endmodule
module complexmulttrial2(
input [15:0] a_r,
input [15:0] a_i,
input [15:0] b_r,
input [15:0] b_i,
input [15:0] w_r,
input [15:0] w_i,
output [15:0] x_r,
output [15:0] x_i,
output [15:0] y_r,
output [15:0] y_i,
output [32:0] temp_r,
output [32:0] temp_i);



wire [32:0] temp_r_r;
wire [32:0] temp_i_i;

assign x_r = a_r + b_r;
assign x_i = a_i + b_i;
assign temp_r_r=a_r-b_r;
assign temp_i_i=a_i-b_i;
assign temp_r=(temp_r_r)*(w_r) - (temp_i_i)*(w_i);
assign temp_i=(temp_i_i)*(w_r) - (temp_r_r)*(w_i);




assign y_r[15:0] = temp_r[32:17];
assign y_i[15:0] = temp_i[32:17];



endmodule