data/full_repos/permissive/159596577/src/instfetch.v
 line:13: before: "input"
1: b"%Error: data/full_repos/permissive/159596577/src/instfetch.v:13: syntax error, unexpected input, expecting ';'\n    input [31:0] pc_i;\n    ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module pc(
    pc_i,
    pc_o,
    clk
)
    input [31:0] pc_i;
    input clk;
    output pc_o;
    always @(posedg clk) begin
        pc_o<=pc_i;
    end
endmodule
module pc(
    pc_i,
    pc_o,
    clk
)
    input [31:0] pc_i;

    input clk;
    output pc_o;
    always @(posedg clk) begin
        pc_o<=pc_i;
    end
endmodule