data/full_repos/permissive/196851857/testbench/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/196851857/testbench/testbench.v:9: Unsupported: Ignoring delay on this delayed statement.\nalways #30 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/196851857/testbench/testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n     #9000 rst = ~rst;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/196851857/testbench/testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n     #20 rst = ~rst;\n     ^\n%Error: data/full_repos/permissive/196851857/testbench/testbench.v:3: Cannot find file containing module: \'mips\'\nmips mips(clk,rst);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/196851857/testbench,data/full_repos/permissive/196851857/mips\n             data/full_repos/permissive/196851857/testbench,data/full_repos/permissive/196851857/mips.v\n             data/full_repos/permissive/196851857/testbench,data/full_repos/permissive/196851857/mips.sv\n             mips\n             mips.v\n             mips.sv\n             obj_dir/mips\n             obj_dir/mips.v\n             obj_dir/mips.sv\n%Error: data/full_repos/permissive/196851857/testbench/testbench.v:16: Cannot find file containing module: \'mips\'\nmips lly_mips(.clk(clk), .rst(rst));\n^~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_mips();
reg clk,rst;
mips mips(clk,rst);
initial 
begin
    clk = 0;
    rst = 0;
end
always #30 clk = ~clk;
always
   begin
     #9000 rst = ~rst;
     #20 rst = ~rst;
   end

mips lly_mips(.clk(clk), .rst(rst));
endmodule
module test_mips();

reg clk,rst;
mips mips(clk,rst);
initial 
begin
    clk = 0;
    rst = 0;
end
always #30 clk = ~clk;
always
   begin
     #9000 rst = ~rst;
     #20 rst = ~rst;
   end

mips lly_mips(.clk(clk), .rst(rst));
endmodule