data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v:54: Multiple top level modules\n                                                                                                                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                                                                        : ... Top module \'DFFSRQ\'\nmodule DFFSRQ(SET,\n       ^~~~~~\n                                                                                                                                                                                        : ... Top module \'DFFR\'\nmodule DFFR(RST,\n       ^~~~\n                                                                                                                                                                                        : ... Top module \'GPIO\'\nmodule GPIO(PAD,\n       ^~~~\n                                                                                                                                                                                        : ... Top module \'ADDF\'\nmodule ADDF(A,\n       ^~~~\n%Error: Exiting due to 1 warning(s)\n'
module ADDF(A,
            B,
            CI,
            SUM,
            CO);

input [0:0] A;

input [0:0] B;

input [0:0] CI;

output [0:0] SUM;

output [0:0] CO;












endmodule
module ADDF(A,
            B,
            CI,
            SUM,
            CO);


input [0:0] A;

input [0:0] B;

input [0:0] CI;

output [0:0] SUM;

output [0:0] CO;












endmodule