data/full_repos/permissive/194847941/demo/2_Buttons&LED/switch_LED_tdread.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/2_Buttons&LED/switch_LED_tdread.v:55: Cell has missing pin: \'en\'\n  reg_ar_as_w16 reg0 (\n                ^~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/2_Buttons&LED/switch_LED_tdread.v:245: Cell has missing pin: \'en\'\n  reg_ar_as_w5 reg0 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/2_Buttons&LED/switch_LED_tdread.v:251: Cell has missing pin: \'en\'\n  reg_ar_as_w19 reg1 (\n                ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/2_Buttons&LED/switch_LED_tdread.v:257: Cell has missing pin: \'en\'\n  reg_ar_as_w5 reg2 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/2_Buttons&LED/switch_LED_tdread.v:263: Cell has missing pin: \'en\'\n  reg_ar_as_w5 reg3 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/2_Buttons&LED/switch_LED_tdread.v:269: Cell has missing pin: \'en\'\n  reg_ar_as_w5 reg4 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/2_Buttons&LED/switch_LED_tdread.v:330: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg0 (\n               ^~~~\n%Error: Exiting due to 7 warning(s)\n'
module \debounce(N=5)
  (
  clk,
  key,
  rst,
  key_pulse
  );

  input clk;
  input [4:0] key;
  input rst;
  output [4:0] key_pulse;

  parameter N = 5;
  wire [18:0] cnt;
  wire [4:0] key_edge;
  wire [4:0] key_rst;
  wire [4:0] key_rst_pre;
  wire [4:0] key_sec;
  wire [4:0] key_sec_pre;
  wire [4:0] n0;
  wire [4:0] n10;
  wire [18:0] n3;
  wire [18:0] n4;
  wire [4:0] n7;
  wire n1;
  wire n2;
  wire n5;
  wire n6;
  wire n8;
  wire n9;

  add_pu19_pu19_o19 add0 (
    .i0(cnt),
    .i1(19'b0000000000000000001),
    .o(n3));
  eq_w19 eq0 (
    .i0(cnt),
    .i1(19'b1110101011000000001),
    .o(n6));
  binary_mux_s1_w19 mux0 (
    .i0(n3),
    .i1(19'b0000000000000000000),
    .sel(n2),
    .o(n4));
  binary_mux_s1_w5 mux1 (
    .i0(key_sec),
    .i1(key),
    .sel(n6),
    .o(n7));
  reg_ar_as_w5 reg0 (
    .clk(clk),
    .d(key_rst),
    .reset(5'b00000),
    .set({n1,n1,n1,n1,n1}),
    .q(key_rst_pre));
  reg_ar_as_w19 reg1 (
    .clk(clk),
    .d(n4),
    .reset({n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1}),
    .set(19'b0000000000000000000),
    .q(cnt));
  reg_ar_as_w5 reg2 (
    .clk(clk),
    .d(n7),
    .reset(5'b00000),
    .set({n1,n1,n1,n1,n1}),
    .q(key_sec));
  reg_ar_as_w5 reg3 (
    .clk(clk),
    .d(key_sec),
    .reset(5'b00000),
    .set({n1,n1,n1,n1,n1}),
    .q(key_sec_pre));
  reg_ar_as_w5 reg4 (
    .clk(clk),
    .d(key),
    .reset(5'b00000),
    .set({n1,n1,n1,n1,n1}),
    .q(key_rst));
  not u10 (n10[1], key_sec[1]);
  and u11 (key_pulse[2], key_sec_pre[2], n10[2]);
  and u12 (key_pulse[4], key_sec_pre[4], n10[4]);
  and u13 (key_pulse[1], key_sec_pre[1], n10[1]);
  or u14 (n5, key_edge[2], n9);
  or u15 (n8, key_edge[0], key_edge[1]);
  not u16 (n10[0], key_sec[0]);
  and u17 (key_pulse[0], key_sec_pre[0], n10[0]);
  or u18 (n2, n8, n5);
  and u19 (key_edge[1], key_rst_pre[1], n0[1]);
  or u2 (n9, key_edge[3], key_edge[4]);
  and u20 (key_edge[2], key_rst_pre[2], n0[2]);
  and u21 (key_edge[3], key_rst_pre[3], n0[3]);
  and u22 (key_edge[4], key_rst_pre[4], n0[4]);
  not u23 (n0[1], key_rst[1]);
  not u24 (n0[2], key_rst[2]);
  not u25 (n0[3], key_rst[3]);
  not u26 (n0[4], key_rst[4]);
  not u3 (n10[4], key_sec[4]);
  not u4 (n10[3], key_sec[3]);
  not u5 (n1, rst);
  not u6 (n0[0], key_rst[0]);
  not u7 (n10[2], key_sec[2]);
  and u8 (key_pulse[3], key_sec_pre[3], n10[3]);
  and u9 (key_edge[0], key_rst_pre[0], n0[0]);

endmodule
module \debounce(N=5)
  (
  clk,
  key,
  rst,
  key_pulse
  );


  input clk;
  input [4:0] key;
  input rst;
  output [4:0] key_pulse;

  parameter N = 5;
  wire [18:0] cnt;
  wire [4:0] key_edge;
  wire [4:0] key_rst;
  wire [4:0] key_rst_pre;
  wire [4:0] key_sec;
  wire [4:0] key_sec_pre;
  wire [4:0] n0;
  wire [4:0] n10;
  wire [18:0] n3;
  wire [18:0] n4;
  wire [4:0] n7;
  wire n1;
  wire n2;
  wire n5;
  wire n6;
  wire n8;
  wire n9;

  add_pu19_pu19_o19 add0 (
    .i0(cnt),
    .i1(19'b0000000000000000001),
    .o(n3));
  eq_w19 eq0 (
    .i0(cnt),
    .i1(19'b1110101011000000001),
    .o(n6));
  binary_mux_s1_w19 mux0 (
    .i0(n3),
    .i1(19'b0000000000000000000),
    .sel(n2),
    .o(n4));
  binary_mux_s1_w5 mux1 (
    .i0(key_sec),
    .i1(key),
    .sel(n6),
    .o(n7));
  reg_ar_as_w5 reg0 (
    .clk(clk),
    .d(key_rst),
    .reset(5'b00000),
    .set({n1,n1,n1,n1,n1}),
    .q(key_rst_pre));
  reg_ar_as_w19 reg1 (
    .clk(clk),
    .d(n4),
    .reset({n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1,n1}),
    .set(19'b0000000000000000000),
    .q(cnt));
  reg_ar_as_w5 reg2 (
    .clk(clk),
    .d(n7),
    .reset(5'b00000),
    .set({n1,n1,n1,n1,n1}),
    .q(key_sec));
  reg_ar_as_w5 reg3 (
    .clk(clk),
    .d(key_sec),
    .reset(5'b00000),
    .set({n1,n1,n1,n1,n1}),
    .q(key_sec_pre));
  reg_ar_as_w5 reg4 (
    .clk(clk),
    .d(key),
    .reset(5'b00000),
    .set({n1,n1,n1,n1,n1}),
    .q(key_rst));
  not u10 (n10[1], key_sec[1]);
  and u11 (key_pulse[2], key_sec_pre[2], n10[2]);
  and u12 (key_pulse[4], key_sec_pre[4], n10[4]);
  and u13 (key_pulse[1], key_sec_pre[1], n10[1]);
  or u14 (n5, key_edge[2], n9);
  or u15 (n8, key_edge[0], key_edge[1]);
  not u16 (n10[0], key_sec[0]);
  and u17 (key_pulse[0], key_sec_pre[0], n10[0]);
  or u18 (n2, n8, n5);
  and u19 (key_edge[1], key_rst_pre[1], n0[1]);
  or u2 (n9, key_edge[3], key_edge[4]);
  and u20 (key_edge[2], key_rst_pre[2], n0[2]);
  and u21 (key_edge[3], key_rst_pre[3], n0[3]);
  and u22 (key_edge[4], key_rst_pre[4], n0[4]);
  not u23 (n0[1], key_rst[1]);
  not u24 (n0[2], key_rst[2]);
  not u25 (n0[3], key_rst[3]);
  not u26 (n0[4], key_rst[4]);
  not u3 (n10[4], key_sec[4]);
  not u4 (n10[3], key_sec[3]);
  not u5 (n1, rst);
  not u6 (n0[0], key_rst[0]);
  not u7 (n10[2], key_sec[2]);
  and u8 (key_pulse[3], key_sec_pre[3], n10[3]);
  and u9 (key_edge[0], key_rst_pre[0], n0[0]);

endmodule