data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen/vectorgen_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen/vectorgen_tb.v:1: Cannot find include file: common.vh\n`include "common.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen,data/full_repos/permissive/150133337/common.vh\n             data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen,data/full_repos/permissive/150133337/common.vh.v\n             data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen,data/full_repos/permissive/150133337/common.vh.sv\n             common.vh\n             common.vh.v\n             common.vh.sv\n             obj_dir/common.vh\n             obj_dir/common.vh.v\n             obj_dir/common.vh.sv\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen/vectorgen_tb.v:56: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen/vectorgen_tb.v:60: Unsupported: wait statements\n      wait (controller_dut.state == 1);\n      ^~~~\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen/vectorgen_tb.v:67: Unsupported: wait statements\n      wait (driver.data_in_counter == driver.max_data_in_count);\n      ^~~~\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen/vectorgen_tb.v:92: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("vectorgen_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen/vectorgen_tb.v:93: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,vectorgen_tb);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen/vectorgen_tb.v:138: Unsupported: wait statements\n  wait (read_ready);\n  ^~~~\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen/vectorgen_tb.v:140: Unsupported: wait statements\n  wait (ready);\n  ^~~~\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/vectorgen/vectorgen_tb.v:141: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Error: Exiting due to 9 error(s)\n'
module vectorgen_tb;




  localparam integer LAYER_PARAM_WIDTH         = 6;
  localparam integer NUM_PE     = 4;
  localparam integer OP_WIDTH   = 16;
  localparam integer DATA_WIDTH = NUM_PE * OP_WIDTH;
  localparam integer VECGEN_CTRL_W = 9;
  localparam integer TID_WIDTH         = 8;
  localparam integer PAD_WIDTH         = 3;
  localparam integer VECGEN_CFG_W      = TID_WIDTH + PAD_WIDTH;
  localparam integer WEIGHT_ADDR_WIDTH = 4;




  wire  [DATA_WIDTH-1:0]      read_data;
  wire  [DATA_WIDTH-1:0]      write_data;
  wire  [NUM_PE-1:0]          write_mask;
  wire  [VECGEN_CTRL_W-1:0]   vectorgen_ctrl;
  wire  [VECGEN_CFG_W -1:0]   cfg;
  reg                         start;

  vectorgen_tb_driver #(
    .OP_WIDTH     ( OP_WIDTH    ),
    .NUM_PE       ( NUM_PE      )
  ) driver (
    .clk          ( clk         ),
    .reset        ( reset       ),
    .ready        ( ready       ),


    .read_ready   ( read_ready  ),
    .read_data    ( read_data   ),
    .read_req     ( read_req    ),
    .write_valid  ( write_valid ),
    .write_data   ( write_data  ),
    .write_mask   ( write_mask  )
  );

  reg [LAYER_PARAM_WIDTH-1:0] _kw, _kh, _ks;
  reg [LAYER_PARAM_WIDTH-1:0] _iw, _ih, _ic, _batch, _oc;
  reg [LAYER_PARAM_WIDTH-1:0] _endrow_iw;
  reg                         _skip;
  reg [LAYER_PARAM_WIDTH-1:0] _ow;
  reg [PAD_WIDTH-1:0] _pad;
  reg [TID_WIDTH-1:0] _max_threads;

  integer layer_id, max_layers;

  initial begin
    driver.status.start;
    @(negedge clk);
    max_layers = controller_dut.max_layers+1;
    for (layer_id = 0; layer_id < max_layers; layer_id = layer_id+1)
    begin
      wait (controller_dut.state == 1);
      _ks = 1;
      {_max_threads, _pad, _skip, _endrow_iw, _ic, _ih, _iw, _oc, _kh, _kw} = controller_dut.cfg_rom[layer_id];
      driver.initialize_input(_ih+1, _ih+1, _ic+1, 1);
      driver.print_input;
      driver.initialize_expected_output(_ih+1, _ih+1, _ic, _batch, _kw+1, _kh+1, _ks, _oc, _pad);
      driver.generate_vectors;
      wait (driver.data_in_counter == driver.max_data_in_count);
    end


















    driver.pass = 1;
  end

  initial
  begin
    $dumpfile("vectorgen_tb.vcd");
    $dumpvars(0,vectorgen_tb);
  end

  vectorgen #(
     .OP_WIDTH      ( OP_WIDTH    ),
     .NUM_PE        ( NUM_PE      )
   ) u_vecgen (
     .clk           ( clk         ),
     .reset         ( reset       ),
     .ready         ( ready       ),
     .ctrl          ( vectorgen_ctrl        ),
     .cfg           ( cfg         ),
     .read_ready    ( read_ready  ),
     .read_data     ( read_data   ),
     .read_req      ( read_req    ),
     .write_valid   ( write_valid ),
     .write_data    ( write_data  ),
     .write_mask    ( write_mask  )
  );




  PU_controller
  #(
    .NUM_PE             ( NUM_PE            ),
    .WEIGHT_ADDR_WIDTH  ( WEIGHT_ADDR_WIDTH ),
    .PE_CTRL_WIDTH      ( 9                 ),
    .VECGEN_CTRL_W      ( VECGEN_CTRL_W     ),
    .TID_WIDTH          ( TID_WIDTH         ),
    .MAX_LAYERS         ( 5                 ),
    .PAD_WIDTH          ( PAD_WIDTH         )
  ) controller_dut (
    .clk                ( clk               ),
    .reset              ( reset             ),
    .start              ( start             ),
    .done               ( done              ),
    .vectorgen_ready    ( ready             ),
    .vectorgen_ctrl               ( vectorgen_ctrl              ),
    .cfg                ( cfg               )
  );


initial begin
  start = 0;
  wait (read_ready);
  start = 1;
  wait (ready);
  @(negedge clk);
  @(negedge clk);
  start = 0;

end

endmodule
module vectorgen_tb;





  localparam integer LAYER_PARAM_WIDTH         = 6;
  localparam integer NUM_PE     = 4;
  localparam integer OP_WIDTH   = 16;
  localparam integer DATA_WIDTH = NUM_PE * OP_WIDTH;
  localparam integer VECGEN_CTRL_W = 9;
  localparam integer TID_WIDTH         = 8;
  localparam integer PAD_WIDTH         = 3;
  localparam integer VECGEN_CFG_W      = TID_WIDTH + PAD_WIDTH;
  localparam integer WEIGHT_ADDR_WIDTH = 4;




  wire  [DATA_WIDTH-1:0]      read_data;
  wire  [DATA_WIDTH-1:0]      write_data;
  wire  [NUM_PE-1:0]          write_mask;
  wire  [VECGEN_CTRL_W-1:0]   vectorgen_ctrl;
  wire  [VECGEN_CFG_W -1:0]   cfg;
  reg                         start;

  vectorgen_tb_driver #(
    .OP_WIDTH     ( OP_WIDTH    ),
    .NUM_PE       ( NUM_PE      )
  ) driver (
    .clk          ( clk         ),
    .reset        ( reset       ),
    .ready        ( ready       ),


    .read_ready   ( read_ready  ),
    .read_data    ( read_data   ),
    .read_req     ( read_req    ),
    .write_valid  ( write_valid ),
    .write_data   ( write_data  ),
    .write_mask   ( write_mask  )
  );

  reg [LAYER_PARAM_WIDTH-1:0] _kw, _kh, _ks;
  reg [LAYER_PARAM_WIDTH-1:0] _iw, _ih, _ic, _batch, _oc;
  reg [LAYER_PARAM_WIDTH-1:0] _endrow_iw;
  reg                         _skip;
  reg [LAYER_PARAM_WIDTH-1:0] _ow;
  reg [PAD_WIDTH-1:0] _pad;
  reg [TID_WIDTH-1:0] _max_threads;

  integer layer_id, max_layers;

  initial begin
    driver.status.start;
    @(negedge clk);
    max_layers = controller_dut.max_layers+1;
    for (layer_id = 0; layer_id < max_layers; layer_id = layer_id+1)
    begin
      wait (controller_dut.state == 1);
      _ks = 1;
      {_max_threads, _pad, _skip, _endrow_iw, _ic, _ih, _iw, _oc, _kh, _kw} = controller_dut.cfg_rom[layer_id];
      driver.initialize_input(_ih+1, _ih+1, _ic+1, 1);
      driver.print_input;
      driver.initialize_expected_output(_ih+1, _ih+1, _ic, _batch, _kw+1, _kh+1, _ks, _oc, _pad);
      driver.generate_vectors;
      wait (driver.data_in_counter == driver.max_data_in_count);
    end


















    driver.pass = 1;
  end

  initial
  begin
    $dumpfile("vectorgen_tb.vcd");
    $dumpvars(0,vectorgen_tb);
  end

  vectorgen #(
     .OP_WIDTH      ( OP_WIDTH    ),
     .NUM_PE        ( NUM_PE      )
   ) u_vecgen (
     .clk           ( clk         ),
     .reset         ( reset       ),
     .ready         ( ready       ),
     .ctrl          ( vectorgen_ctrl        ),
     .cfg           ( cfg         ),
     .read_ready    ( read_ready  ),
     .read_data     ( read_data   ),
     .read_req      ( read_req    ),
     .write_valid   ( write_valid ),
     .write_data    ( write_data  ),
     .write_mask    ( write_mask  )
  );




  PU_controller
  #(
    .NUM_PE             ( NUM_PE            ),
    .WEIGHT_ADDR_WIDTH  ( WEIGHT_ADDR_WIDTH ),
    .PE_CTRL_WIDTH      ( 9                 ),
    .VECGEN_CTRL_W      ( VECGEN_CTRL_W     ),
    .TID_WIDTH          ( TID_WIDTH         ),
    .MAX_LAYERS         ( 5                 ),
    .PAD_WIDTH          ( PAD_WIDTH         )
  ) controller_dut (
    .clk                ( clk               ),
    .reset              ( reset             ),
    .start              ( start             ),
    .done               ( done              ),
    .vectorgen_ready    ( ready             ),
    .vectorgen_ctrl               ( vectorgen_ctrl              ),
    .cfg                ( cfg               )
  );


initial begin
  start = 0;
  wait (read_ready);
  start = 1;
  wait (ready);
  @(negedge clk);
  @(negedge clk);
  start = 0;

end

endmodule