data/full_repos/permissive/118895561/Project 3/dm.v
1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/118895561\n        ... Looked in:\n             data/full_repos/permissive/118895561/Project/3,data/full_repos/permissive/118895561\n             data/full_repos/permissive/118895561/Project/3,data/full_repos/permissive/118895561.v\n             data/full_repos/permissive/118895561/Project/3,data/full_repos/permissive/118895561.sv\n             3,data/full_repos/permissive/118895561\n             3,data/full_repos/permissive/118895561.v\n             3,data/full_repos/permissive/118895561.sv\n             obj_dir/3,data/full_repos/permissive/118895561\n             obj_dir/3,data/full_repos/permissive/118895561.v\n             obj_dir/3,data/full_repos/permissive/118895561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/118895561/Project\n%Error: Cannot find file containing module: 3/dm.v\n%Error: Exiting due to 3 error(s)\n'
module dm(
	 input  [31:0] PC,
    input  [31:0] Addr,
	 input  [3:0]  Bit_Type,
    input  [31:0] WriteData,
	 output [31:0] ReadData,
    input  WriteEnabled,
    input  clk, reset
    );
	 
	integer i;
	wire [11:0] A;
   reg [31:0] DM[2047:0];
	assign A = Addr[12:2];
	wire [31:0] Write_Data;

	assign ReadData = DM[A];
	assign Write_Data = (Bit_Type == 4'b1111) ? WriteData :
							  (Bit_Type == 4'b0011) ? {DM[A][31:16], WriteData[15:0]} :
							  (Bit_Type == 4'b1100) ? {WriteData[15:0], DM[A][15:0]} :
							  (Bit_Type == 4'b0001) ? {DM[A][31:8], WriteData[7:0]} :
							  (Bit_Type == 4'b0010) ? {DM[A][31:16], WriteData[7:0], DM[A][7:0]} :
							  (Bit_Type == 4'b0100) ? {DM[A][31:24], WriteData[7:0], DM[A][15:0]} :
							  (Bit_Type == 4'b1000) ? {WriteData[7:0], DM[A][23:0]} :
															  32'b0							;
															  
	always @(posedge clk) begin
		if(reset)
			for(i = 0 ; i < 2048 ; i = i + 1)
				DM[i] <= 0;
	   else if(WriteEnabled) begin
				DM[A][31:0]  <= Write_Data;

		end
	end
	
endmodule
module dm(
	 input  [31:0] PC,
    input  [31:0] Addr,
	 input  [3:0]  Bit_Type,
    input  [31:0] WriteData,
	 output [31:0] ReadData,
    input  WriteEnabled,
    input  clk, reset
    );

	 
	integer i;
	wire [11:0] A;
   reg [31:0] DM[2047:0];
	assign A = Addr[12:2];
	wire [31:0] Write_Data;

	assign ReadData = DM[A];
	assign Write_Data = (Bit_Type == 4'b1111) ? WriteData :
							  (Bit_Type == 4'b0011) ? {DM[A][31:16], WriteData[15:0]} :
							  (Bit_Type == 4'b1100) ? {WriteData[15:0], DM[A][15:0]} :
							  (Bit_Type == 4'b0001) ? {DM[A][31:8], WriteData[7:0]} :
							  (Bit_Type == 4'b0010) ? {DM[A][31:16], WriteData[7:0], DM[A][7:0]} :
							  (Bit_Type == 4'b0100) ? {DM[A][31:24], WriteData[7:0], DM[A][15:0]} :
							  (Bit_Type == 4'b1000) ? {WriteData[7:0], DM[A][23:0]} :
															  32'b0							;
															  
	always @(posedge clk) begin
		if(reset)
			for(i = 0 ; i < 2048 ; i = i + 1)
				DM[i] <= 0;
	   else if(WriteEnabled) begin
				DM[A][31:0]  <= Write_Data;

		end
	end
	
endmodule