data/full_repos/permissive/157049472/Verilog Test Benches/ALU_tb.v
1: b'%Error: Cannot find file containing module: Test\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Test\n             data/full_repos/permissive/157049472/Verilog/Test.v\n             data/full_repos/permissive/157049472/Verilog/Test.sv\n             Test\n             Test.v\n             Test.sv\n             obj_dir/Test\n             obj_dir/Test.v\n             obj_dir/Test.sv\n%Error: Cannot find file containing module: Benches,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Benches/ALU_tb.v\n%Error: Exiting due to 4 error(s)\n'
module ALU_tb;


	reg [31:0] a;
	reg [31:0] b;
	reg [3:0] control;


	wire [31:0] result;
	wire zero_flag;
	wire carry_flag;
	wire sign_flag;
	wire overflow_flag;


	ALU uut (
		.a(a), 
		.b(b), 
		.control(control), 
		.result(result), 
		.zero_flag(zero_flag), 
		.carry_flag(carry_flag), 
		.sign_flag(sign_flag), 
		.overflow_flag(overflow_flag)
	);

	initial begin

		a = 0;
		b = 0;
		control = 0;


		#100;
      


		#10;
		control = 0;
		a = 20;
		b = 10;

		#20;
		a = 32'h7fffffff;
		b = 32'h7fffffff;
		#20;
		a = 32'hffffffff;
		b = 32'hffffffff;

		#20;
		control = 3;
		a = 32'hffa47a78;
		b = 32'h0faeff12;
		
		#20;
		control = 4;
		a = 32'hffaaaa78;
		b = 32'h03a33f12;
	
		#20;
		control = 6;
		a = 32'h00a11a78;
		b = 32'h03aeff36;
	
		#20;
		control = 7;
		a = 32'h0faaaa78;
		b = 32'h03faeff14;	
	end
      
endmodule
module ALU_tb;



	reg [31:0] a;
	reg [31:0] b;
	reg [3:0] control;


	wire [31:0] result;
	wire zero_flag;
	wire carry_flag;
	wire sign_flag;
	wire overflow_flag;


	ALU uut (
		.a(a), 
		.b(b), 
		.control(control), 
		.result(result), 
		.zero_flag(zero_flag), 
		.carry_flag(carry_flag), 
		.sign_flag(sign_flag), 
		.overflow_flag(overflow_flag)
	);

	initial begin

		a = 0;
		b = 0;
		control = 0;


		#100;
      


		#10;
		control = 0;
		a = 20;
		b = 10;

		#20;
		a = 32'h7fffffff;
		b = 32'h7fffffff;
		#20;
		a = 32'hffffffff;
		b = 32'hffffffff;

		#20;
		control = 3;
		a = 32'hffa47a78;
		b = 32'h0faeff12;
		
		#20;
		control = 4;
		a = 32'hffaaaa78;
		b = 32'h03a33f12;
	
		#20;
		control = 6;
		a = 32'h00a11a78;
		b = 32'h03aeff36;
	
		#20;
		control = 7;
		a = 32'h0faaaa78;
		b = 32'h03faeff14;	
	end
      
endmodule