data/full_repos/permissive/117026779/src/VGA.v
1: b"%Error: data/full_repos/permissive/117026779/src/VGA.v:93: syntax error, unexpected '(', expecting IDENTIFIER\n    .clk(clk),\n    ^\n%Error: Exiting due to 1 error(s)\n"
module ConvertXYToAddress (
    input wire [31:0] hcount,
    input wire [31:0] vcount,
    output wire [11:0] address
);


assign address = (vcount[31:4] * `TERMINAL_COLUMNS) + hcount[31:3];

endmodule
module ConvertXYToAddress (
    input wire [31:0] hcount,
    input wire [31:0] vcount,
    output wire [11:0] address
);



assign address = (vcount[31:4] * `TERMINAL_COLUMNS) + hcount[31:3];

endmodule