data/full_repos/permissive/179227721/i2s_sinewav/i2s_sinewave.v
 line:12: before: ")"
1: b"%Error: data/full_repos/permissive/179227721/i2s_sinewav/i2s_sinewave.v:12: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/179227721/i2s_sinewav/i2s_sinewave.v:20: syntax error, unexpected IDENTIFIER\n   pll pll_module(refclk, clk, \n   ^~~\n%Error: Exiting due to 2 error(s)\n"
module top (
	input  refclk,
    input  RST,
	output LED0,
	output LED1,
	output LED2,
	output LED3,
	output LED4,
	output LED5,
	output LED6,
	output LED7,
);

   wire    clk;
   localparam CLKDIV = 21;

   reg [CLKDIV:0] clkdiv;
   reg [7:0]     counter;

   pll pll_module(refclk, clk, 
                  , 
                  RST,);
   
   always@(posedge clk)
     begin
        clkdiv <= clkdiv + 1;

        if (clkdiv[CLKDIV])
          begin
             clkdiv <= 0;
	         counter <= counter + 1;
          end

     end

   assign {LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7} = counter;
endmodule
module top (
	input  refclk,
    input  RST,
	output LED0,
	output LED1,
	output LED2,
	output LED3,
	output LED4,
	output LED5,
	output LED6,
	output LED7,
);


   wire    clk;
   localparam CLKDIV = 21;

   reg [CLKDIV:0] clkdiv;
   reg [7:0]     counter;

   pll pll_module(refclk, clk, 
                  , 
                  RST,);
   
   always@(posedge clk)
     begin
        clkdiv <= clkdiv + 1;

        if (clkdiv[CLKDIV])
          begin
             clkdiv <= 0;
	         counter <= counter + 1;
          end

     end

   assign {LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7} = counter;
endmodule