data/full_repos/permissive/174369527/ram/ram.v
data/verilator_xmls/3e5e77ea-80c7-4a8a-bf6d-0fc3c518d995.xml
module ram (
	Address,
	Data,
	CS,
	WE,
	OE
	);

parameter AddressSize = 11;
parameter WordSize = 9;

input [AddressSize-1:0] Address;
inout [WordSize-1:0] Data;
input CS, WE, OE;

reg [WordSize-1:0] Mem [0:(1<<AddressSize)-1];

assign Data = (!CS && !OE) ? Mem[Address] : {WordSize{1'bz}};

initial begin
	$display("Loading rom.");
	$readmemb("rom_image.mem", Mem);
end

always @(CS or WE)
	if (!CS && !WE)
		Mem[Address] = Data;

always @(WE or OE)
	if (!WE && !OE)
		$display("Operational error in RamChip: OE and WE both active");

endmodule
module ram (
	Address,
	Data,
	CS,
	WE,
	OE
	);


parameter AddressSize = 11;
parameter WordSize = 9;

input [AddressSize-1:0] Address;
inout [WordSize-1:0] Data;
input CS, WE, OE;

reg [WordSize-1:0] Mem [0:(1<<AddressSize)-1];

assign Data = (!CS && !OE) ? Mem[Address] : {WordSize{1'bz}};

initial begin
	$display("Loading rom.");
	$readmemb("rom_image.mem", Mem);
end

always @(CS or WE)
	if (!CS && !WE)
		Mem[Address] = Data;

always @(WE or OE)
	if (!WE && !OE)
		$display("Operational error in RamChip: OE and WE both active");

endmodule