data/full_repos/permissive/101171422/sim/hello_world.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/hello_world.v:7: Unsupported: Ignoring delay on this delayed statement.\n  #100 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/hello_world.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #5 clock = ~clock;\n  ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_hello_world();
	reg clock;

	initial begin
		clock = 1;
	end

	always begin
		#5 clock = ~clock;
	end

	hello_world test_hello(
		clock
	);
endmodule
module test_hello_world();

	reg clock;

	initial begin
		clock = 1;
	end

	always begin
		#5 clock = ~clock;
	end

	hello_world test_hello(
		clock
	);
endmodule