data/full_repos/permissive/140493787/src/hdl/vga_counter.v
 line:8: before: "TERMINAL_COUNT"
1: b'%Warning-STMTDLY: data/full_repos/permissive/140493787/src/hdl/vga_counter.v:52: Unsupported: Ignoring delay on this delayed statement.\n      forever #(CLK_PER / 2) clk <= ~clk;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/140493787/src/hdl/vga_counter.v:56: syntax error, unexpected \'@\'\n      reset <= 0; @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/140493787/src/hdl/vga_counter.v:57: syntax error, unexpected \'@\'\n      reset <= 1; @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/140493787/src/hdl/vga_counter.v:58: syntax error, unexpected \'@\'\n      reset <= 0; @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/140493787/src/hdl/vga_counter.v:59: syntax error, unexpected \'@\'\n      repeat (420100) @(posedge clk);\n                      ^\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vga_counter #(TERMINAL_COUNT = 799) (
   output reg  [9:0] q,
   output wire       tc,
   input  wire       en,
   input  wire       clk,
   input  wire       reset
);

   assign tc = q == TERMINAL_COUNT;

   always @ (posedge clk) begin
      if (reset)   q <= 10'b0;
      else if (en) q <= q + 1'b1;
   end
endmodule
module vga_counter #(TERMINAL_COUNT = 799) (
   output reg  [9:0] q,
   output wire       tc,
   input  wire       en,
   input  wire       clk,
   input  wire       reset
);


   assign tc = q == TERMINAL_COUNT;

   always @ (posedge clk) begin
      if (reset)   q <= 10'b0;
      else if (en) q <= q + 1'b1;
   end
endmodule