data/full_repos/permissive/117026779/sim/Test_Motherboard.v
 line:43: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Motherboard.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Motherboard.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Motherboard.v:34: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Motherboard.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Motherboard.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_Motherboard;
reg success_flag;
reg rst, clk;

initial begin
	success_flag = 1;
    rst = 0;
    clk = 0;
    #5
    rst = 1;
    #5
    rst = 0;
	#5

	if (success_flag == 0) begin
		$display("*FAILED* TEST!");
	end
	else begin
		$display("**PASSED** TEST!");
	end

    #10 $stop;
    #5 $finish;
end

endmodule
module Test_Motherboard;

reg success_flag;
reg rst, clk;

initial begin
	success_flag = 1;
    rst = 0;
    clk = 0;
    #5
    rst = 1;
    #5
    rst = 0;
	#5

	if (success_flag == 0) begin
		$display("*FAILED* TEST!");
	end
	else begin
		$display("**PASSED** TEST!");
	end

    #10 $stop;
    #5 $finish;
end

endmodule