data/full_repos/permissive/153414067/VGA.v
None: at end of input
1: b'%Warning-IMPLICIT: data/full_repos/permissive/153414067/VGA.v:37: Signal definition not found, creating implicitly: \'visible\'\n  assign visible = ((ver_cntr >= 10\'d1) && (ver_cntr <= 10\'d600) &&  \n         ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module VGA(
	input clk,
	input rst,
	input [5:0] data,
	output [8:0] io,
	output [6:0] hor_addr,
	output [7:0] ver_addr,
	output read,
	output write
    );
	 
	 reg [9:0] ver_cntr = 10'd1;
	 reg [10:0] hor_cntr = 11'd1;
	 
	 always @ (posedge clk)
	 begin
		if (rst) begin
			ver_cntr <= 10'd1;
			hor_cntr <= 11'd1;
		end
		else begin
			if (hor_cntr == 11'd1040) begin
				hor_cntr <= 11'd1;
				if (ver_cntr == 10'd666) ver_cntr <= 10'd1;
				else ver_cntr <= ver_cntr + 1'b1;
			end
			else hor_cntr <= hor_cntr + 1'b1;
		end
	 end
	 
	 assign visible = ((ver_cntr >= 10'd1) && (ver_cntr <= 10'd600) &&
							 (hor_cntr >= 11'd200) && (hor_cntr <= 11'd603));
	 




	 assign hor_addr = visible ? hor_cntr[8:2] : hor_cntr[6:0];
	 assign ver_addr = ver_cntr[9:2];
	 

	 assign read = visible;
	 



	 



	 assign write = ((ver_cntr >= 10'd1) && (ver_cntr <= 10'd600) &&
						  (hor_cntr >= 11'd690) && (hor_cntr <= 11'd790));
	 
	 assign io[0] = 1'b0;
	 assign io[1] = visible && data[0];
	 assign io[2] = visible && data[1];
	 assign io[3] = visible && data[2];
	 assign io[4] = visible && data[3];
	 assign io[5] = visible && data[4];
	 assign io[6] = visible && data[5];
	 assign io[7] = ((ver_cntr <= 10'd643) && (ver_cntr > 10'd637));
	 assign io[8] = ((hor_cntr <= 11'd976) && (hor_cntr > 11'd856));
	 
endmodule
module VGA(
	input clk,
	input rst,
	input [5:0] data,
	output [8:0] io,
	output [6:0] hor_addr,
	output [7:0] ver_addr,
	output read,
	output write
    );

	 
	 reg [9:0] ver_cntr = 10'd1;
	 reg [10:0] hor_cntr = 11'd1;
	 
	 always @ (posedge clk)
	 begin
		if (rst) begin
			ver_cntr <= 10'd1;
			hor_cntr <= 11'd1;
		end
		else begin
			if (hor_cntr == 11'd1040) begin
				hor_cntr <= 11'd1;
				if (ver_cntr == 10'd666) ver_cntr <= 10'd1;
				else ver_cntr <= ver_cntr + 1'b1;
			end
			else hor_cntr <= hor_cntr + 1'b1;
		end
	 end
	 
	 assign visible = ((ver_cntr >= 10'd1) && (ver_cntr <= 10'd600) &&
							 (hor_cntr >= 11'd200) && (hor_cntr <= 11'd603));
	 




	 assign hor_addr = visible ? hor_cntr[8:2] : hor_cntr[6:0];
	 assign ver_addr = ver_cntr[9:2];
	 

	 assign read = visible;
	 



	 



	 assign write = ((ver_cntr >= 10'd1) && (ver_cntr <= 10'd600) &&
						  (hor_cntr >= 11'd690) && (hor_cntr <= 11'd790));
	 
	 assign io[0] = 1'b0;
	 assign io[1] = visible && data[0];
	 assign io[2] = visible && data[1];
	 assign io[3] = visible && data[2];
	 assign io[4] = visible && data[3];
	 assign io[5] = visible && data[4];
	 assign io[6] = visible && data[5];
	 assign io[7] = ((ver_cntr <= 10'd643) && (ver_cntr > 10'd637));
	 assign io[8] = ((hor_cntr <= 11'd976) && (hor_cntr > 11'd856));
	 
endmodule