data/full_repos/permissive/132220215/clock_gen.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/132220215/clock_gen.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #period out = ~out;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/132220215/clock_gen.v:6: Duplicate declaration of signal: \'out\'\n                                                          : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg out;\n     ^~~\n        data/full_repos/permissive/132220215/clock_gen.v:4: ... Location of original declaration\n (output out);\n         ^~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock #(parameter period = 10) 
	(output out);

 reg out;
 initial
	 out = 1'b0;
 always
 begin
	 #period out = ~out;
 end
endmodule
module clock #(parameter period = 10) 
	(output out);


 reg out;
 initial
	 out = 1'b0;
 always
 begin
	 #period out = ~out;
 end
endmodule