data/full_repos/permissive/169522605/hw3_2/nand3.v
data/verilator_xmls/9ef90a87-0ca0-46f7-95a8-163c506ba8d3.xml
module nand3 (in1,in2,in3,out);
    input in1,in2,in3;
    output out;
    assign out = ~(in1 & in2 & in3);
endmodule
module nand3 (in1,in2,in3,out);

    input in1,in2,in3;
    output out;
    assign out = ~(in1 & in2 & in3);
endmodule