data/full_repos/permissive/120024308/src/cpu/output.v
 line:34: before: ")"
1: b"%Error: data/full_repos/permissive/120024308/src/cpu/output.v:34: Define or directive not defined: '`LED'\n  if ((operation == `LED) || (operation == `LEDI))begin\n                    ^~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/output.v:34: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n  if ((operation == `LED) || (operation == `LEDI))begin\n                        ^\n%Error: data/full_repos/permissive/120024308/src/cpu/output.v:34: Define or directive not defined: '`LEDI'\n  if ((operation == `LED) || (operation == `LEDI))begin\n                                           ^~~~~\n%Error: Cannot continue\n"
module Output(
	      input wire 	clk,
	      input wire 	reset,
	      input wire [5:0] 	operation,
	      input wire [31:0] in,
	      output reg [7:0] out
	      );
   
   always @(posedge clk) begin
      if (reset == 1)begin
	 out <= 8'b0;	 
      end
      else begin
	 if ((operation == `LED) || (operation == `LEDI))begin
	    out <= in[7:0];	    
	 end
	 else begin
	    out <= out;
	 end
      end
   end
endmodule
module Output(
	      input wire 	clk,
	      input wire 	reset,
	      input wire [5:0] 	operation,
	      input wire [31:0] in,
	      output reg [7:0] out
	      );

   
   always @(posedge clk) begin
      if (reset == 1)begin
	 out <= 8'b0;	 
      end
      else begin
	 if ((operation == `LED) || (operation == `LEDI))begin
	    out <= in[7:0];	    
	 end
	 else begin
	    out <= out;
	 end
      end
   end
endmodule