data/full_repos/permissive/100975158/ProcessadorQuartus/Memoria.v
data/verilator_xmls/fc52a8e9-914c-47a4-952b-7cbf9201a91d.xml
module Memoria (
	input wire[31:0] pc,
	output wire[31:0] instrucao
	);
	
	reg [31:0] memoria [0:63];
	
	initial begin
		$readmemb("c:/arquivo.txt", memoria);
	end
	
	assign instrucao = memoria[pc[7:2]][31:0];
endmodule
module Memoria (
	input wire[31:0] pc,
	output wire[31:0] instrucao
	);

	
	reg [31:0] memoria [0:63];
	
	initial begin
		$readmemb("c:/arquivo.txt", memoria);
	end
	
	assign instrucao = memoria[pc[7:2]][31:0];
endmodule