data/full_repos/permissive/164484080/rtl/uart.v
1: b'%Error: data/full_repos/permissive/164484080/rtl/uart.v:22: Cannot find include file: config.v\n`include "config.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164484080/rtl,data/full_repos/permissive/164484080/config.v\n             data/full_repos/permissive/164484080/rtl,data/full_repos/permissive/164484080/config.v.v\n             data/full_repos/permissive/164484080/rtl,data/full_repos/permissive/164484080/config.v.sv\n             config.v\n             config.v.v\n             config.v.sv\n             obj_dir/config.v\n             obj_dir/config.v.v\n             obj_dir/config.v.sv\n%Error: data/full_repos/permissive/164484080/rtl/uart.v:23: Cannot find include file: wishbone.v\n`include "wishbone.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/uart.v:47: Define or directive not defined: \'`WB_SLAVE_PORT_SIGNALS\'\n    `WB_SLAVE_PORT_SIGNALS(uart_),\n    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/uart.v:47: syntax error, unexpected \'(\', expecting \'[\'\n    `WB_SLAVE_PORT_SIGNALS(uart_),\n                           ^~~~~\n%Error: data/full_repos/permissive/164484080/rtl/uart.v:57: Define or directive not defined: \'`DAT_WIDTH\'\n    reg [`DAT_WIDTH-1:0] r_dat_i;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/uart.v:58: Define or directive not defined: \'`DAT_WIDTH\'\n    reg [`DAT_WIDTH-1:0] r_dat_o;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/uart.v:65: Define or directive not defined: \'`DAT_WIDTH\'\n    reg [`DAT_WIDTH-1:0] uart_ctrl;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/uart.v:115: syntax error, unexpected assign\n    assign uart_tx_transmitting_data =\n    ^~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/uart.v:121: syntax error, unexpected assign\n    assign uart_ack_o = uart_stb_i ? r_ack : 1\'b0;\n    ^~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/uart.v:130: syntax error, unexpected always\n    always @(posedge clk_i)\n    ^~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/uart.v:195: Define or directive not defined: \'`DAT_WIDTH\'\n            r_dat_o <= {`DAT_WIDTH{1\'h0}};\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/uart.v:272: syntax error, unexpected always\n    always @(posedge uart_rx_sample_clk)\n    ^~~~~~\n%Error: Exiting due to 12 error(s)\n'
module uart (
    input rst_i,
    input clk_i,

    `WB_SLAVE_PORT_SIGNALS(uart_),

    output [7:0] uart_out,


    input uart_rx_i,
    output uart_tx_o
);


    reg [`DAT_WIDTH-1:0] r_dat_i;
    reg [`DAT_WIDTH-1:0] r_dat_o;
    reg r_ack = 1'h0;
    reg r_err = 1'h0;




    reg [`DAT_WIDTH-1:0] uart_ctrl;


    reg [1:0] uart_state = `STATE_IDLE;






    reg [4:0] uart_rx_state = `STATE_RX_IDLE;


    reg uart_rx_sample_clk = 1'd0;

    reg [31:0] uart_rx_sample_counter = 32'd0;

    reg uart_rx_baud_clk = 1'd0;

    reg [31:0] uart_rx_baud_counter = 32'd0;
    reg uart_rx_baud_is_running = 1'd0;

    reg [7:0] uart_rx_buf = 8'h0;

    reg uart_rx_start = 1'b0;

    reg [3:0] uart_rx_bit_idx = 4'h0;

    reg uart_rx_data_ready = 1'b0;
    reg uart_last_rx = 1'b1;





    reg [4:0] uart_tx_state = `STATE_TX_IDLE;

    reg uart_tx_baud_clk = 1'd0;

    reg [31:0] uart_tx_baud_counter = 32'd0;

    reg [7:0] uart_tx_buf = 8'h0;

    reg [3:0] uart_tx_bit_idx = 4'h0;
    reg uart_tx_start = 1'd0;

    reg r_uart_tx = 1'd1;

    wire uart_tx_transmitting_data;

    assign uart_tx_transmitting_data =
        (uart_tx_state != `STATE_TX_IDLE) || uart_tx_start ? 1'b1 : 1'b0;

    reg [7:0] r_uart_out;


    assign uart_ack_o = uart_stb_i ? r_ack : 1'b0;
    assign uart_err_o = uart_stb_i ? r_err : 1'b0;
    assign uart_dat_o = r_dat_o;

    assign uart_tx_o = uart_tx_state == `STATE_TX_IDLE ? 1'h1 : r_uart_tx;

    assign uart_out = r_uart_out;

    reg uart_rx_start_last;
    always @(posedge clk_i)
        uart_rx_start_last <= uart_rx_start;


    always @(posedge clk_i) begin
        if (rst_i) begin
            uart_rx_sample_clk <= 1'h0;
            uart_rx_sample_counter <= 32'h0;
            uart_rx_baud_clk <= 1'h0;
            uart_rx_baud_counter <= 32'h0;
            uart_rx_baud_is_running <= 1'd0;
            uart_tx_baud_clk <= 1'h0;
            uart_tx_baud_counter <= 32'h0;
        end else begin



            if (uart_rx_sample_counter < (868 / 32 / 2) - 1) begin
                uart_rx_sample_counter <= uart_rx_sample_counter + 1;
            end else begin
                uart_rx_sample_counter <= 32'h0;
                uart_rx_sample_clk <= ~uart_rx_sample_clk;
            end




            if (uart_rx_start_last == 1'b0 && uart_rx_start == 1'b1) begin





                uart_rx_baud_counter <= 32'd64;
                uart_rx_baud_clk <= 1'd0;
                uart_rx_baud_is_running <= 1'd1;
            end else begin




                if (uart_rx_baud_counter < (868 / 2) - 1) begin
                    uart_rx_baud_counter <= uart_rx_baud_counter + 1;
                end else begin
                    uart_rx_baud_counter <= 32'h0;
                    uart_rx_baud_clk <= ~uart_rx_baud_clk;
                end
            end



            if (uart_tx_baud_counter < (868 / 2) - 1) begin
                uart_tx_baud_counter <= uart_tx_baud_counter + 1;
            end else begin
                uart_tx_baud_counter <= 32'h0;
                uart_tx_baud_clk <= ~uart_tx_baud_clk;
            end
        end
    end


    always @(posedge clk_i) begin
        if (rst_i) begin
            r_ack <= 1'b0;
            r_err <= 1'b0;
            r_dat_o <= {`DAT_WIDTH{1'h0}};
        end else begin
            case (uart_state)
                `STATE_IDLE: begin
                    if (uart_stb_i) begin
                        uart_state <= `STATE_WAIT_FOR_PHASE_END;

                        r_ack <= 1'b1;
                        r_err <= 1'b0;

                        if (uart_we_i) begin
                            case (uart_adr_i[7:0])
                                `UART_STAT: begin


                                end
                                `UART_CTRL: begin
                                    uart_ctrl <= uart_dat_i;
                                end
                                `UART_DATA: begin
                                    if (!uart_tx_transmitting_data) begin

                                        uart_tx_start <= 1'd1;

                                        uart_tx_buf <= uart_dat_i[7:0];
                                    end
                                end
                                default: begin


                                    r_ack <= 1'b0;
                                    r_err <= 1'b1;
                                end
                            endcase
                        end else begin
                            case (uart_adr_i[7:0])
                                `UART_STAT: begin
                                    r_dat_o <= {
                                        {62{1'h0}},
                                        uart_rx_data_ready,
                                        uart_tx_transmitting_data
                                    };
                                end
                                `UART_CTRL: begin
                                    r_dat_o <= uart_ctrl;
                                end
                                `UART_DATA: begin
                                    r_dat_o <= { {56{1'h0}}, uart_rx_buf };
                                end
                                default: begin


                                    r_ack <= 1'b0;
                                    r_err <= 1'b1;
                                end
                            endcase
                        end
                    end
                end
                `STATE_WAIT_FOR_PHASE_END: begin
                    if (~uart_stb_i) begin
                        uart_state <= `STATE_IDLE;
                        r_ack <= 1'h0;
                        r_err <= 1'h0;
                    end
                end
            endcase

            if (uart_tx_state != `STATE_TX_IDLE)


                uart_tx_start <= 1'd0;
        end
    end

    reg r_uart_rx, r_uart_rx_0;

    always @(posedge uart_rx_sample_clk)
        r_uart_rx_0 <= uart_rx_i;
    always @(posedge uart_rx_sample_clk)
        r_uart_rx <= r_uart_rx_0;


    always @(posedge uart_rx_sample_clk) begin
        if (uart_last_rx == 1'b1 && r_uart_rx == 1'b0) begin
            uart_rx_start <= 1'b1;
        end

        uart_last_rx <= r_uart_rx;


        if (uart_rx_state != `STATE_RX_IDLE)
            uart_rx_start <= 1'b0;
    end


    always @(posedge uart_rx_baud_clk) begin
        case (uart_rx_state)
            `STATE_RX_IDLE: begin
                if (uart_rx_start) begin
                    uart_rx_data_ready <= 1'b0;
                    uart_rx_state <= `STATE_RX_RECV_DATA;
                    uart_rx_bit_idx <= 4'h0;
                end
            end
            `STATE_RX_RECV_DATA: begin
                if (uart_rx_bit_idx < 8) begin
                    uart_rx_bit_idx <= uart_rx_bit_idx + 1;
                    uart_rx_buf <= { r_uart_rx, uart_rx_buf[7:1] };
                end else begin
                    uart_rx_state <= `STATE_RX_RECV_STOP;
                end
            end
            `STATE_RX_RECV_STOP: begin


                uart_rx_state <= `STATE_RX_IDLE;
                uart_rx_data_ready <= 1'b1;



                r_uart_out <= uart_rx_buf;
            end
        endcase
    end


    always @(posedge uart_tx_baud_clk) begin
        case (uart_tx_state)
            `STATE_TX_IDLE: begin
                if (uart_tx_start) begin
                    uart_tx_state <= `STATE_TX_SEND_DATA;

                    r_uart_tx <= 1'h0;
                    uart_tx_bit_idx <= 4'h0;
                end else begin

                    r_uart_tx <= 1'h1;
                end
            end
            `STATE_TX_SEND_DATA: begin
                if (uart_tx_bit_idx < 8) begin
                    r_uart_tx <= uart_tx_buf[uart_tx_bit_idx+:1];
                    uart_tx_bit_idx <= uart_tx_bit_idx + 1;
                end else begin
                    uart_tx_state <= `STATE_TX_SEND_STOP;

                    r_uart_tx <= 1'h1;
                end
            end
            `STATE_TX_SEND_STOP: begin

                uart_tx_state <= `STATE_TX_IDLE;
            end
        endcase
    end

endmodule
module uart (
    input rst_i,
    input clk_i,

    `WB_SLAVE_PORT_SIGNALS(uart_),

    output [7:0] uart_out,


    input uart_rx_i,
    output uart_tx_o
);



    reg [`DAT_WIDTH-1:0] r_dat_i;
    reg [`DAT_WIDTH-1:0] r_dat_o;
    reg r_ack = 1'h0;
    reg r_err = 1'h0;




    reg [`DAT_WIDTH-1:0] uart_ctrl;


    reg [1:0] uart_state = `STATE_IDLE;






    reg [4:0] uart_rx_state = `STATE_RX_IDLE;


    reg uart_rx_sample_clk = 1'd0;

    reg [31:0] uart_rx_sample_counter = 32'd0;

    reg uart_rx_baud_clk = 1'd0;

    reg [31:0] uart_rx_baud_counter = 32'd0;
    reg uart_rx_baud_is_running = 1'd0;

    reg [7:0] uart_rx_buf = 8'h0;

    reg uart_rx_start = 1'b0;

    reg [3:0] uart_rx_bit_idx = 4'h0;

    reg uart_rx_data_ready = 1'b0;
    reg uart_last_rx = 1'b1;





    reg [4:0] uart_tx_state = `STATE_TX_IDLE;

    reg uart_tx_baud_clk = 1'd0;

    reg [31:0] uart_tx_baud_counter = 32'd0;

    reg [7:0] uart_tx_buf = 8'h0;

    reg [3:0] uart_tx_bit_idx = 4'h0;
    reg uart_tx_start = 1'd0;

    reg r_uart_tx = 1'd1;

    wire uart_tx_transmitting_data;

    assign uart_tx_transmitting_data =
        (uart_tx_state != `STATE_TX_IDLE) || uart_tx_start ? 1'b1 : 1'b0;

    reg [7:0] r_uart_out;


    assign uart_ack_o = uart_stb_i ? r_ack : 1'b0;
    assign uart_err_o = uart_stb_i ? r_err : 1'b0;
    assign uart_dat_o = r_dat_o;

    assign uart_tx_o = uart_tx_state == `STATE_TX_IDLE ? 1'h1 : r_uart_tx;

    assign uart_out = r_uart_out;

    reg uart_rx_start_last;
    always @(posedge clk_i)
        uart_rx_start_last <= uart_rx_start;


    always @(posedge clk_i) begin
        if (rst_i) begin
            uart_rx_sample_clk <= 1'h0;
            uart_rx_sample_counter <= 32'h0;
            uart_rx_baud_clk <= 1'h0;
            uart_rx_baud_counter <= 32'h0;
            uart_rx_baud_is_running <= 1'd0;
            uart_tx_baud_clk <= 1'h0;
            uart_tx_baud_counter <= 32'h0;
        end else begin



            if (uart_rx_sample_counter < (868 / 32 / 2) - 1) begin
                uart_rx_sample_counter <= uart_rx_sample_counter + 1;
            end else begin
                uart_rx_sample_counter <= 32'h0;
                uart_rx_sample_clk <= ~uart_rx_sample_clk;
            end




            if (uart_rx_start_last == 1'b0 && uart_rx_start == 1'b1) begin





                uart_rx_baud_counter <= 32'd64;
                uart_rx_baud_clk <= 1'd0;
                uart_rx_baud_is_running <= 1'd1;
            end else begin




                if (uart_rx_baud_counter < (868 / 2) - 1) begin
                    uart_rx_baud_counter <= uart_rx_baud_counter + 1;
                end else begin
                    uart_rx_baud_counter <= 32'h0;
                    uart_rx_baud_clk <= ~uart_rx_baud_clk;
                end
            end



            if (uart_tx_baud_counter < (868 / 2) - 1) begin
                uart_tx_baud_counter <= uart_tx_baud_counter + 1;
            end else begin
                uart_tx_baud_counter <= 32'h0;
                uart_tx_baud_clk <= ~uart_tx_baud_clk;
            end
        end
    end


    always @(posedge clk_i) begin
        if (rst_i) begin
            r_ack <= 1'b0;
            r_err <= 1'b0;
            r_dat_o <= {`DAT_WIDTH{1'h0}};
        end else begin
            case (uart_state)
                `STATE_IDLE: begin
                    if (uart_stb_i) begin
                        uart_state <= `STATE_WAIT_FOR_PHASE_END;

                        r_ack <= 1'b1;
                        r_err <= 1'b0;

                        if (uart_we_i) begin
                            case (uart_adr_i[7:0])
                                `UART_STAT: begin


                                end
                                `UART_CTRL: begin
                                    uart_ctrl <= uart_dat_i;
                                end
                                `UART_DATA: begin
                                    if (!uart_tx_transmitting_data) begin

                                        uart_tx_start <= 1'd1;

                                        uart_tx_buf <= uart_dat_i[7:0];
                                    end
                                end
                                default: begin


                                    r_ack <= 1'b0;
                                    r_err <= 1'b1;
                                end
                            endcase
                        end else begin
                            case (uart_adr_i[7:0])
                                `UART_STAT: begin
                                    r_dat_o <= {
                                        {62{1'h0}},
                                        uart_rx_data_ready,
                                        uart_tx_transmitting_data
                                    };
                                end
                                `UART_CTRL: begin
                                    r_dat_o <= uart_ctrl;
                                end
                                `UART_DATA: begin
                                    r_dat_o <= { {56{1'h0}}, uart_rx_buf };
                                end
                                default: begin


                                    r_ack <= 1'b0;
                                    r_err <= 1'b1;
                                end
                            endcase
                        end
                    end
                end
                `STATE_WAIT_FOR_PHASE_END: begin
                    if (~uart_stb_i) begin
                        uart_state <= `STATE_IDLE;
                        r_ack <= 1'h0;
                        r_err <= 1'h0;
                    end
                end
            endcase

            if (uart_tx_state != `STATE_TX_IDLE)


                uart_tx_start <= 1'd0;
        end
    end

    reg r_uart_rx, r_uart_rx_0;

    always @(posedge uart_rx_sample_clk)
        r_uart_rx_0 <= uart_rx_i;
    always @(posedge uart_rx_sample_clk)
        r_uart_rx <= r_uart_rx_0;


    always @(posedge uart_rx_sample_clk) begin
        if (uart_last_rx == 1'b1 && r_uart_rx == 1'b0) begin
            uart_rx_start <= 1'b1;
        end

        uart_last_rx <= r_uart_rx;


        if (uart_rx_state != `STATE_RX_IDLE)
            uart_rx_start <= 1'b0;
    end


    always @(posedge uart_rx_baud_clk) begin
        case (uart_rx_state)
            `STATE_RX_IDLE: begin
                if (uart_rx_start) begin
                    uart_rx_data_ready <= 1'b0;
                    uart_rx_state <= `STATE_RX_RECV_DATA;
                    uart_rx_bit_idx <= 4'h0;
                end
            end
            `STATE_RX_RECV_DATA: begin
                if (uart_rx_bit_idx < 8) begin
                    uart_rx_bit_idx <= uart_rx_bit_idx + 1;
                    uart_rx_buf <= { r_uart_rx, uart_rx_buf[7:1] };
                end else begin
                    uart_rx_state <= `STATE_RX_RECV_STOP;
                end
            end
            `STATE_RX_RECV_STOP: begin


                uart_rx_state <= `STATE_RX_IDLE;
                uart_rx_data_ready <= 1'b1;



                r_uart_out <= uart_rx_buf;
            end
        endcase
    end


    always @(posedge uart_tx_baud_clk) begin
        case (uart_tx_state)
            `STATE_TX_IDLE: begin
                if (uart_tx_start) begin
                    uart_tx_state <= `STATE_TX_SEND_DATA;

                    r_uart_tx <= 1'h0;
                    uart_tx_bit_idx <= 4'h0;
                end else begin

                    r_uart_tx <= 1'h1;
                end
            end
            `STATE_TX_SEND_DATA: begin
                if (uart_tx_bit_idx < 8) begin
                    r_uart_tx <= uart_tx_buf[uart_tx_bit_idx+:1];
                    uart_tx_bit_idx <= uart_tx_bit_idx + 1;
                end else begin
                    uart_tx_state <= `STATE_TX_SEND_STOP;

                    r_uart_tx <= 1'h1;
                end
            end
            `STATE_TX_SEND_STOP: begin

                uart_tx_state <= `STATE_TX_IDLE;
            end
        endcase
    end

endmodule