data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/clock_scaler.v
data/verilator_xmls/cafeb626-ed23-4c8d-bb96-2a52497c5d6c.xml
module clock_scaler(
    input in,
    output reg out
    );
    
    reg [14:0] current;
    

    parameter load_value = 1302;
    initial begin
        current = load_value;
        out = in;
    end
    
    always @(posedge in) begin
        current = current - 1;
        if (current == 0) begin
            out = ~out;
            current = load_value;
        end
    end
    
endmodule
module clock_scaler(
    input in,
    output reg out
    );

    
    reg [14:0] current;
    

    parameter load_value = 1302;
    initial begin
        current = load_value;
        out = in;
    end
    
    always @(posedge in) begin
        current = current - 1;
        if (current == 0) begin
            out = ~out;
            current = load_value;
        end
    end
    
endmodule