data/full_repos/permissive/199632300/HDLBits/Verification/sim/sim/circuit1.v
data/verilator_xmls/e2fe1bdc-21bf-4ef0-96d5-ab5644cfa13b.xml
module top_module (
    input a,
    input b,
    output q );

    assign q = a&b;

endmodule
module top_module (
    input a,
    input b,
    output q );


    assign q = a&b;

endmodule