data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v
None: at end of input
1: b'%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:1: Cannot find include file: common.vh\n`include "common.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC,data/full_repos/permissive/150133337/common.vh\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC,data/full_repos/permissive/150133337/common.vh.v\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC,data/full_repos/permissive/150133337/common.vh.sv\n             common.vh\n             common.vh.v\n             common.vh.sv\n             obj_dir/common.vh\n             obj_dir/common.vh.v\n             obj_dir/common.vh.sv\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:13: Define or directive not defined: \'`PRECISION_OP\'\n    parameter OP_0_WIDTH  = `PRECISION_OP,\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:13: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter OP_0_WIDTH  = `PRECISION_OP,\n                                         ^\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:14: Define or directive not defined: \'`PRECISION_OP\'\n    parameter OP_1_WIDTH  = `PRECISION_OP,\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:14: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter OP_1_WIDTH  = `PRECISION_OP,\n                                         ^\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:15: Define or directive not defined: \'`PRECISION_ACC\'\n    parameter ACC_WIDTH   = `PRECISION_ACC,\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:15: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter ACC_WIDTH   = `PRECISION_ACC,\n                                          ^\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:16: Define or directive not defined: \'`PRECISION_OP\'\n    parameter OUT_WIDTH   = `PRECISION_OP,\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:16: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter OUT_WIDTH   = `PRECISION_OP,\n                                         ^\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:18: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter FRAC_BITS = `PRECISION_FRAC,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:18: Define or directive not defined: \'`PRECISION_FRAC\'\n    parameter FRAC_BITS = `PRECISION_FRAC,\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:18: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter FRAC_BITS = `PRECISION_FRAC,\n                                         ^\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:19: Define or directive not defined: \'`PRECISION_OP\'\n    parameter INT_BITS = `PRECISION_OP - 1 - `PRECISION_FRAC\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:19: Define or directive not defined: \'`PRECISION_FRAC\'\n    parameter INT_BITS = `PRECISION_OP - 1 - `PRECISION_FRAC\n                                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:20: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n) (\n^\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n  input  wire                                         reset,\n  ^~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n  input  wire                                         enable,\n  ^~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n  input  wire                                         clear,\n  ^~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n  input  wire   [ OP_CODE_WIDTH        -1 : 0 ]       op_code,\n  ^~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n  input  signed [ OP_0_WIDTH           -1 : 0 ]       op_0,\n  ^~~~~\n%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/MACC/macc.v:59: syntax error, unexpected generate\ngenerate\n^~~~~~~~\n%Error: Exiting due to 21 error(s)\n'
module macc #(
    parameter OP_0_WIDTH  = `PRECISION_OP,
    parameter OP_1_WIDTH  = `PRECISION_OP,
    parameter ACC_WIDTH   = `PRECISION_ACC,
    parameter OUT_WIDTH   = `PRECISION_OP,
    parameter TYPE = "FIXED_POINT",
    parameter FRAC_BITS = `PRECISION_FRAC,
    parameter INT_BITS = `PRECISION_OP - 1 - `PRECISION_FRAC
) (
  input  wire                                         clk,
  input  wire                                         reset,
  input  wire                                         enable,
  input  wire                                         clear,
  input  wire   [ OP_CODE_WIDTH        -1 : 0 ]       op_code,
  input  signed [ OP_0_WIDTH           -1 : 0 ]       op_0,
  input  signed [ OP_1_WIDTH           -1 : 0 ]       op_1,
  input  signed [ ACC_WIDTH            -1 : 0 ]       op_add,
  output signed [ OUT_WIDTH            -1 : 0 ]       out
);




    localparam integer OP_CODE_WIDTH = 3;



    reg  [OP_CODE_WIDTH-1:0] op_code_d;
    reg  [OP_CODE_WIDTH-1:0] op_code_dd;

    reg  signed [OP_0_WIDTH-1:0] op_0_d;
    reg  signed [OP_1_WIDTH-1:0] op_1_d;
    reg  signed [ACC_WIDTH-1:0]  op_add_d;
    reg  signed [ACC_WIDTH-1:0]  op_add_dd;
    reg  signed [ACC_WIDTH-1:0]  product;
    wire signed [ACC_WIDTH-1:0]  data_ADD;
    reg  signed [OUT_WIDTH-1:0]  out_reg;

    wire [255:0] GND = 256'd0;
    reg enable_d;
    reg enable_dd;
    reg clear_d;
    reg clear_dd;




generate
if (TYPE == "FLOATING_POINT") begin
    float_point
    float_point_i (
        .A_data     ( op_0      ),
        .A_valid    ( 1'b1      ),
        .B_data     ( op_1      ),
        .B_valid    ( 1'b1      ),
        .C          ( op_add    ),
        .C_valid    ( 1'b1      ),
        .Out_data   ( out       ),
        .Out_valid  (           ),
        .aclk       ( clk       ),
        .aclken     ( reset     )
    );

end else begin

    always @(posedge clk)
    begin
        if (reset) begin
            op_0_d <= 0;
            op_1_d <= 0;
            op_add_d <= 0;
            op_code_d <= 0;
        end else begin
            op_code_d <= op_code;
            if (enable) begin
                op_0_d <= op_0;
                op_1_d <= (op_code[0])? op_0 : op_1;
                op_add_d <= op_add;
            end else begin
                op_0_d <= 0;
                op_1_d <= 0;
                op_add_d <= 0;
            end
        end
    end

    always@(posedge clk)
      enable_d <= enable;
    always@(posedge clk)
      clear_d <= clear;


    always @(posedge clk)
    begin
        if (reset) begin
            product <= 0;
            op_code_dd <= 0;
        end else begin
            if (enable_d) begin
                product <= op_0_d * op_1_d;
            end else begin
                product <= 0;
            end
            op_code_dd <= op_code_d;
        end
    end

    always@(posedge clk)
      enable_dd <= enable_d;
    always@(posedge clk)
      clear_dd <= clear_d;

    always @(posedge clk)
      op_add_dd <= op_add_d;


    assign data_ADD = (op_code_dd[2:1] == 2'd0) ? GND[ACC_WIDTH-1:0] :
      (op_code_dd[1] == 2'd1) ? out_reg : op_add_dd;
    always @(posedge clk)
    begin
        if (reset || clear_dd) begin
            out_reg <= 0;
        end
        else if (enable_dd) begin
            out_reg <= product + (data_ADD <<< FRAC_BITS);
        end
    end

    assign out = out_reg >>> FRAC_BITS;













end
endgenerate

`ifdef TOPLEVEL_macc
  initial
  begin
    $dumpfile("macc.vcd");
    $dumpvars(0,macc);
  end
`endif

endmodule
module macc #(
    parameter OP_0_WIDTH  = `PRECISION_OP,
    parameter OP_1_WIDTH  = `PRECISION_OP,
    parameter ACC_WIDTH   = `PRECISION_ACC,
    parameter OUT_WIDTH   = `PRECISION_OP,
    parameter TYPE = "FIXED_POINT",
    parameter FRAC_BITS = `PRECISION_FRAC,
    parameter INT_BITS = `PRECISION_OP - 1 - `PRECISION_FRAC
) (
  input  wire                                         clk,
  input  wire                                         reset,
  input  wire                                         enable,
  input  wire                                         clear,
  input  wire   [ OP_CODE_WIDTH        -1 : 0 ]       op_code,
  input  signed [ OP_0_WIDTH           -1 : 0 ]       op_0,
  input  signed [ OP_1_WIDTH           -1 : 0 ]       op_1,
  input  signed [ ACC_WIDTH            -1 : 0 ]       op_add,
  output signed [ OUT_WIDTH            -1 : 0 ]       out
);





    localparam integer OP_CODE_WIDTH = 3;



    reg  [OP_CODE_WIDTH-1:0] op_code_d;
    reg  [OP_CODE_WIDTH-1:0] op_code_dd;

    reg  signed [OP_0_WIDTH-1:0] op_0_d;
    reg  signed [OP_1_WIDTH-1:0] op_1_d;
    reg  signed [ACC_WIDTH-1:0]  op_add_d;
    reg  signed [ACC_WIDTH-1:0]  op_add_dd;
    reg  signed [ACC_WIDTH-1:0]  product;
    wire signed [ACC_WIDTH-1:0]  data_ADD;
    reg  signed [OUT_WIDTH-1:0]  out_reg;

    wire [255:0] GND = 256'd0;
    reg enable_d;
    reg enable_dd;
    reg clear_d;
    reg clear_dd;




generate
if (TYPE == "FLOATING_POINT") begin
    float_point
    float_point_i (
        .A_data     ( op_0      ),
        .A_valid    ( 1'b1      ),
        .B_data     ( op_1      ),
        .B_valid    ( 1'b1      ),
        .C          ( op_add    ),
        .C_valid    ( 1'b1      ),
        .Out_data   ( out       ),
        .Out_valid  (           ),
        .aclk       ( clk       ),
        .aclken     ( reset     )
    );

end else begin

    always @(posedge clk)
    begin
        if (reset) begin
            op_0_d <= 0;
            op_1_d <= 0;
            op_add_d <= 0;
            op_code_d <= 0;
        end else begin
            op_code_d <= op_code;
            if (enable) begin
                op_0_d <= op_0;
                op_1_d <= (op_code[0])? op_0 : op_1;
                op_add_d <= op_add;
            end else begin
                op_0_d <= 0;
                op_1_d <= 0;
                op_add_d <= 0;
            end
        end
    end

    always@(posedge clk)
      enable_d <= enable;
    always@(posedge clk)
      clear_d <= clear;


    always @(posedge clk)
    begin
        if (reset) begin
            product <= 0;
            op_code_dd <= 0;
        end else begin
            if (enable_d) begin
                product <= op_0_d * op_1_d;
            end else begin
                product <= 0;
            end
            op_code_dd <= op_code_d;
        end
    end

    always@(posedge clk)
      enable_dd <= enable_d;
    always@(posedge clk)
      clear_dd <= clear_d;

    always @(posedge clk)
      op_add_dd <= op_add_d;


    assign data_ADD = (op_code_dd[2:1] == 2'd0) ? GND[ACC_WIDTH-1:0] :
      (op_code_dd[1] == 2'd1) ? out_reg : op_add_dd;
    always @(posedge clk)
    begin
        if (reset || clear_dd) begin
            out_reg <= 0;
        end
        else if (enable_dd) begin
            out_reg <= product + (data_ADD <<< FRAC_BITS);
        end
    end

    assign out = out_reg >>> FRAC_BITS;













end
endgenerate

`ifdef TOPLEVEL_macc
  initial
  begin
    $dumpfile("macc.vcd");
    $dumpvars(0,macc);
  end
`endif

endmodule