data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv
1: b"%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:112: Cannot find file containing module: 'VGA_LED_Emulator'\n VGA_LED_Emulator led_emulator(.clk50(clk), \n ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17877624/src/hardware,data/full_repos/permissive/17877624/VGA_LED_Emulator\n             data/full_repos/permissive/17877624/src/hardware,data/full_repos/permissive/17877624/VGA_LED_Emulator.v\n             data/full_repos/permissive/17877624/src/hardware,data/full_repos/permissive/17877624/VGA_LED_Emulator.sv\n             VGA_LED_Emulator\n             VGA_LED_Emulator.v\n             VGA_LED_Emulator.sv\n             obj_dir/VGA_LED_Emulator\n             obj_dir/VGA_LED_Emulator.v\n             obj_dir/VGA_LED_Emulator.sv\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:124: Cannot find file containing module: 'ninja1'\n ninja1 ninja1(.clock(VGA_CLK), .address(addr), .q(M_n1));    \n ^~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:125: Cannot find file containing module: 'ninja2'\n ninja2 ninja2(.clock(VGA_CLK), .address(addr), .q(M_n2));    \n ^~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:126: Cannot find file containing module: 'ninja3'\n ninja3 ninja3(.clock(VGA_CLK), .address(addr), .q(M_n3));    \n ^~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:128: Cannot find file containing module: 'reading'\n reading book1(.clock(VGA_CLK), .address(addr_b1), .q(M_b1));     \n ^~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:129: Cannot find file containing module: 'exam'\n exam book2(.clock(VGA_CLK), .address(addr_b2), .q(M_b2));        \n ^~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:130: Cannot find file containing module: 'homework'\n homework book3(.clock(VGA_CLK), .address(addr_b3), .q(M_b3));    \n ^~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:131: Cannot find file containing module: 'bomb'\n bomb book4(.clock(VGA_CLK), .address(addr_b4), .q(M_b4));    \n ^~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:132: Cannot find file containing module: 'pizza'\n pizza book5(.clock(VGA_CLK), .address(addr_b5), .q(M_b5));   \n ^~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:133: Cannot find file containing module: 'thesis_new'\n thesis_new book6(.clock(VGA_CLK), .address(addr_b6), .q(M_b6));  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:135: Cannot find file containing module: 'bg1_new'\n bg1_new  prom_bg1(.clock(VGA_CLK), .address(addr_bg), .q(M_bg1));    \n ^~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:136: Cannot find file containing module: 'bg2_new'\n bg2_new  prom_bg2(.clock(VGA_CLK), .address(addr_bg), .q(M_bg2));    \n ^~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:137: Cannot find file containing module: 'bg3_new'\n bg3_new  prom_bg3(.clock(VGA_CLK), .address(addr_bg), .q(M_bg3));    \n ^~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:138: Cannot find file containing module: 'bg4_new'\n bg4_new  prom_bg4(.clock(VGA_CLK), .address(addr_bg), .q(M_bg4));    \n ^~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:140: Cannot find file containing module: 'bach_new'\n bach_new level1(.clock(VGA_CLK), .address(addr_s), .q(M_s1));    \n ^~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:141: Cannot find file containing module: 'mast_new'\n mast_new level2(.clock(VGA_CLK), .address(addr_s), .q(M_s2));    \n ^~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:142: Cannot find file containing module: 'phd_new'\n phd_new level3(.clock(VGA_CLK), .address(addr_s), .q(M_s3));     \n ^~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:144: Cannot find file containing module: 'pass_new'\n    pass_new ps(.clock(VGA_CLK), .address(addr_s), .q(M_ps));    \n    ^~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:145: Cannot find file containing module: 'fail_new'\n    fail_new fl(.clock(VGA_CLK), .address(addr_s), .q(M_fl));    \n    ^~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:146: Cannot find file containing module: 'diploma_new'\n diploma_new dip0(.clock(VGA_CLK), .address(addr_s), .q(M_dp));   \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:148: Cannot find file containing module: 'zero_new2'\n    zero_new2 sc0(.clock(VGA_CLK), .address(addr_sc), .q(M_sc0));    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:149: Cannot find file containing module: 'one_new2'\n    one_new2 sc1(.clock(VGA_CLK), .address(addr_sc), .q(M_sc1));     \n    ^~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:150: Cannot find file containing module: 'two_new2'\n    two_new2 sc2(.clock(VGA_CLK), .address(addr_sc), .q(M_sc2));     \n    ^~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:151: Cannot find file containing module: 'three_new2'\n    three_new2 sc3(.clock(VGA_CLK), .address(addr_sc), .q(M_sc3));   \n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:152: Cannot find file containing module: 'four_new2'\n    four_new2 sc4(.clock(VGA_CLK), .address(addr_sc), .q(M_sc4));    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:153: Cannot find file containing module: 'five_new2'\n    five_new2 sc5(.clock(VGA_CLK), .address(addr_sc), .q(M_sc5));    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:154: Cannot find file containing module: 'six_new2'\n    six_new2 sc6(.clock(VGA_CLK), .address(addr_sc), .q(M_sc6));     \n    ^~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:155: Cannot find file containing module: 'seven_new2'\n    seven_new2 sc7(.clock(VGA_CLK), .address(addr_sc), .q(M_sc7));   \n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:156: Cannot find file containing module: 'eight_new2'\n    eight_new2 sc8(.clock(VGA_CLK), .address(addr_sc), .q(M_sc8));   \n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:157: Cannot find file containing module: 'nine_new2'\n    nine_new2 sc9(.clock(VGA_CLK), .address(addr_sc), .q(M_sc9));    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:159: Cannot find file containing module: 'life_new'\n life_new nl1(.clock(VGA_CLK), .address(addr_nl), .q(M_nl1));     \n ^~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:160: Cannot find file containing module: 'life_new'\n life_new nl2(.clock(VGA_CLK), .address(addr_nl), .q(M_nl2));\n ^~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:161: Cannot find file containing module: 'life_new'\n life_new nl3(.clock(VGA_CLK), .address(addr_nl), .q(M_nl3));\n ^~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:163: Cannot find file containing module: 'sun'\n sun sun0(.clock(VGA_CLK), .address(addr_t), .q(M_sun));  \n ^~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:164: Cannot find file containing module: 'moon'\n moon mn0(.clock(VGA_CLK), .address(addr_t), .q(M_mn));   \n ^~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:165: Cannot find file containing module: 'rain'\n rain rn0(.clock(VGA_CLK), .address(addr_t), .q(M_rn));   \n ^~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:167: Cannot find file containing module: 'nuny_new2'\n nuny_new2 nun0(.clock(VGA_CLK), .address(addr_nun), .q(M_nun));  \n ^~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:168: Cannot find file containing module: 'ninjasymbol'\n ninjasymbol sym0(.clock(VGA_CLK), .address(addr_sym), .q(M_sym));    \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:170: Cannot find file containing module: 'tryagain'\n tryagain try0(.clock(VGA_CLK), .address(addr_t), .q(M_try));     \n ^~~~~~~~\n%Error: data/full_repos/permissive/17877624/src/hardware/VGA_LED.sv:174: Cannot find file containing module: 'RGB_controller'\n RGB_controller controller_1(.clk(VGA_CLK),\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 40 error(s)\n"
module VGA_LED(

		   input logic clk,
	       input logic 	  reset,
	       input logic [15:0]  writedata,
	       input logic 	  write,
	       input 		  chipselect,
			 input logic [3:0] address,

	       output logic [7:0] VGA_R, VGA_G, VGA_B,
	       output logic 	  VGA_CLK, VGA_HS, VGA_VS, VGA_BLANK_n,
	       output logic 	  VGA_SYNC_n);



    logic [15:0] x,y;
	logic [15:0] x1,y1;
	logic [15:0] x2,y2;
	logic [15:0] x3,y3;
	logic [15:0] x4,y4;
	logic [15:0] x5,y5;

	

	wire [11:0] addr;
	wire [11:0] addr_b1;
	wire [11:0] addr_b2;
	wire [11:0] addr_b3;
	wire [11:0] addr_b4;
	wire [11:0] addr_b5;
	wire [11:0] addr_b6;
	wire [11:0] addr_s;
	wire [11:0] addr_ps;
	wire [11:0] addr_fl;
	wire [14:0] addr_bg;
	wire [11:0] addr_sc;
    wire [11:0] addr_nl;
    wire [14:0] addr_nun;
    wire [14:0] addr_sym;
    wire [14:0] addr_t;

	

	wire [11:0] M_bg1;
	wire [11:0] M_bg2;
	wire [11:0] M_bg3;
	wire [11:0] M_bg4;
	wire [11:0] M_n1;
	wire [11:0] M_n2;
	wire [11:0] M_n3;
	wire [11:0] M_b1;
	wire [11:0] M_b2;
	wire [11:0] M_b3;
	wire [11:0] M_b4;
	wire [11:0] M_b5;
	wire [11:0] M_b6;
	wire [11:0] M_s1;
	wire [11:0] M_s2;
	wire [11:0] M_s3;
	wire [11:0] M_ps;
	wire [11:0] M_dp;
	wire [11:0] M_fl;
    wire [11:0] M_sc0;
    wire [11:0] M_sc1;
    wire [11:0] M_sc2;
    wire [11:0] M_sc3;
    wire [11:0] M_sc4;
    wire [11:0] M_sc5;
    wire [11:0] M_sc6;
    wire [11:0] M_sc7;
    wire [11:0] M_sc8;
    wire [11:0] M_sc9;

    wire [11:0] M_nl1;
    wire [11:0] M_nl2;
    wire [11:0] M_nl3;

    wire[11:0] M_sun;
    wire[11:0] M_mn;
    wire[11:0] M_rn;
	
    wire[11:0] M_try;

    wire[11:0] M_nun;
    wire[11:0] M_sym;




    wire [10:0] hcount;
	wire [9:0] vcount;
	wire [10:0] xrow;
	wire [1:0] state;
	wire [2:0] screen;
	wire [2:0] level;
	wire result;

    wire [7:0] score;
    wire [3:0] one;
    wire [3:0] ten;
    wire [3:0] hun;

    reg [2:0] nin_life = 3'b000;



	VGA_LED_Emulator led_emulator(.clk50(clk), 
											.reset(reset),
											.hcount(hcount),
											.vcount(vcount),
											.VGA_CLK (VGA_CLK),
											.VGA_HS (VGA_HS),
											.VGA_VS (VGA_VS),
											.VGA_BLANK_n (VGA_BLANK_n),
											.VGA_SYNC_n (VGA_SYNC_n));

											

	ninja1 ninja1(.clock(VGA_CLK), .address(addr), .q(M_n1));
	ninja2 ninja2(.clock(VGA_CLK), .address(addr), .q(M_n2));
	ninja3 ninja3(.clock(VGA_CLK), .address(addr), .q(M_n3));
	
	reading book1(.clock(VGA_CLK), .address(addr_b1), .q(M_b1));
	exam book2(.clock(VGA_CLK), .address(addr_b2), .q(M_b2));
	homework book3(.clock(VGA_CLK), .address(addr_b3), .q(M_b3));
	bomb book4(.clock(VGA_CLK), .address(addr_b4), .q(M_b4));
	pizza book5(.clock(VGA_CLK), .address(addr_b5), .q(M_b5));
	thesis_new book6(.clock(VGA_CLK), .address(addr_b6), .q(M_b6));
	
	bg1_new  prom_bg1(.clock(VGA_CLK), .address(addr_bg), .q(M_bg1));
	bg2_new  prom_bg2(.clock(VGA_CLK), .address(addr_bg), .q(M_bg2));
	bg3_new  prom_bg3(.clock(VGA_CLK), .address(addr_bg), .q(M_bg3));
	bg4_new  prom_bg4(.clock(VGA_CLK), .address(addr_bg), .q(M_bg4));
	
	bach_new level1(.clock(VGA_CLK), .address(addr_s), .q(M_s1));
	mast_new level2(.clock(VGA_CLK), .address(addr_s), .q(M_s2));
	phd_new	level3(.clock(VGA_CLK), .address(addr_s), .q(M_s3));
	
    pass_new ps(.clock(VGA_CLK), .address(addr_s), .q(M_ps));
    fail_new fl(.clock(VGA_CLK), .address(addr_s), .q(M_fl));
	diploma_new dip0(.clock(VGA_CLK), .address(addr_s), .q(M_dp));

    zero_new2 sc0(.clock(VGA_CLK), .address(addr_sc), .q(M_sc0));
    one_new2 sc1(.clock(VGA_CLK), .address(addr_sc), .q(M_sc1));
    two_new2 sc2(.clock(VGA_CLK), .address(addr_sc), .q(M_sc2));
    three_new2 sc3(.clock(VGA_CLK), .address(addr_sc), .q(M_sc3));
    four_new2 sc4(.clock(VGA_CLK), .address(addr_sc), .q(M_sc4));
    five_new2 sc5(.clock(VGA_CLK), .address(addr_sc), .q(M_sc5));
    six_new2 sc6(.clock(VGA_CLK), .address(addr_sc), .q(M_sc6));
    seven_new2 sc7(.clock(VGA_CLK), .address(addr_sc), .q(M_sc7));
    eight_new2 sc8(.clock(VGA_CLK), .address(addr_sc), .q(M_sc8));
    nine_new2 sc9(.clock(VGA_CLK), .address(addr_sc), .q(M_sc9));
	
	life_new nl1(.clock(VGA_CLK), .address(addr_nl), .q(M_nl1));
	life_new nl2(.clock(VGA_CLK), .address(addr_nl), .q(M_nl2));
	life_new nl3(.clock(VGA_CLK), .address(addr_nl), .q(M_nl3));
    
	sun sun0(.clock(VGA_CLK), .address(addr_t), .q(M_sun));
	moon mn0(.clock(VGA_CLK), .address(addr_t), .q(M_mn));
	rain rn0(.clock(VGA_CLK), .address(addr_t), .q(M_rn));
    
	nuny_new2 nun0(.clock(VGA_CLK), .address(addr_nun), .q(M_nun));
	ninjasymbol sym0(.clock(VGA_CLK), .address(addr_sym), .q(M_sym));
    
	tryagain try0(.clock(VGA_CLK), .address(addr_t), .q(M_try));

    

	RGB_controller controller_1(.clk(VGA_CLK),
										.clk50(clk),
										.hcount(hcount),
										.vcount(vcount),
										.x(x), .y(y),
										.x1(x1), .y1(y1),
										.x2(x2), .y2(y2),
										.x3(x3), .y3(y3),
										.x4(x4), .y4(y4),
										.x5(x5), .y5(y5),
                                        .one(one),
                                        .ten(ten),
                                        .hun(hun),
										.addr(addr),
										.addr_b1(addr_b1),
										.addr_b2(addr_b2),
										.addr_b3(addr_b3),
										.addr_b4(addr_b4),
										.addr_b5(addr_b5),
										.addr_b6(addr_b6),
										.addr_s(addr_s),
										.addr_sc(addr_sc),
										.addr_nl(addr_nl),
										.addr_t(addr_t),




										.addr_nun(addr_nun),
										.addr_sym(addr_sym),
										.M_s1(M_s1),
										.M_s2(M_s2),
										.M_s3(M_s3),
										.M_n1(M_n1),
										.M_n2(M_n2),
										.M_n3(M_n3),
										.M_b1(M_b1),
										.M_b2(M_b2),
										.M_b3(M_b3),
										.M_b4(M_b4),
										.M_b5(M_b5),
										.M_b6(M_b6),
										.M_ps(M_ps),
										.M_dp(M_dp),
										.M_fl(M_fl),
                                        .M_sc0(M_sc0),
                                        .M_sc1(M_sc1),
                                        .M_sc2(M_sc2),
                                        .M_sc3(M_sc3),
                                        .M_sc4(M_sc4),
                                        .M_sc5(M_sc5),
                                        .M_sc6(M_sc6),
                                        .M_sc7(M_sc7),
                                        .M_sc8(M_sc8),
                                        .M_sc9(M_sc9),
                                        .M_nl1(M_nl1),
                                        .M_nl2(M_nl2),
                                        .M_nl3(M_nl3),
                                        .M_sun(M_sun),
                                        .M_mn(M_mn),
                                        .M_rn(M_rn),
                                        .M_try(M_try),
                                        .M_nun(M_nun),
                                        .M_sym(M_sym),
										.addr_bg(addr_bg), 
										.M_bg1(M_bg1),
										.M_bg2(M_bg2),
										.M_bg3(M_bg3),
										.M_bg4(M_bg4),
										.screen(screen),
                                        .level(level),
                                        .result(result),
										.nin_life(nin_life),

										.VGA_R(VGA_R),
					.VGA_G(VGA_G),
					.VGA_B(VGA_B)
										);




   always_ff @(posedge clk)
     if (reset) begin
	x <= 16'd300; 
	y <= 16'd200;
	x1 <= 16'd10;
	y1 <= 16'd300;
	x2 <= 16'd70;
	y2 <= 16'd300;
	x3 <= 16'd200;
	y3 <= 16'd300;
	x4 <= 16'd300;
	y4 <= 16'd300;
	x5 <= 16'd500;
	y5 <= 16'd300;
	state <= 2'b00;
	score <= 8'b0;
	nin_life <= 3'b0;
	level <= 3'b0;
	result <= 1'b0;

	end
	else if (chipselect && write)
	begin
		 
	case(address)
	4'b0000: x <= writedata;
	4'b0001: y <= writedata;
	4'b0010: x1 <= writedata; 
	4'b0011: y1 <= writedata;
	4'b0100: x2 <= writedata; 
	4'b0101: y2 <= writedata;
	4'b0110: x3 <= writedata; 
	4'b0111: y3 <= writedata;
	4'b1000: x4 <= writedata; 
	4'b1001: y4 <= writedata;
	4'b1010: x5 <= writedata; 
	4'b1011: y5 <= writedata;
	4'b1100:begin
            state <= writedata[1:0];
            level <= writedata[4:2];
            result <= writedata[5];
				end
	4'b1101: score <= writedata[7:0];
	4'b1110: nin_life <= writedata[2:0];
	4'b1111: state<= 2'b0;
	endcase
	end



	always_ff @(posedge clk) begin
	if (reset)
		screen = 3'b010;
	else case(state)
		2'b00: screen <= 3'b010;
		2'b01: screen <= 3'b001;
		2'b10: screen <= 3'b100;
		default: screen <=3'b010;
		endcase
	end




    integer i;
    always @(score) begin
        hun = 4'd0;
        ten = 4'd0;
        one = 4'd0;

        for (i = 7; i >= 0; i = i -1) begin
            if (hun >= 5)
                hun = hun + 3;
            if (ten >= 5)
                ten = ten + 3;
            if (one >= 5)
                one = one + 3;

            hun = hun << 1;
            hun[0] = ten[3];
            ten = ten << 1;
            ten[0] = one[3];
            one = one << 1;
            one[0] = score[i];
        end
    end

endmodule
module VGA_LED(

		   input logic clk,
	       input logic 	  reset,
	       input logic [15:0]  writedata,
	       input logic 	  write,
	       input 		  chipselect,
			 input logic [3:0] address,

	       output logic [7:0] VGA_R, VGA_G, VGA_B,
	       output logic 	  VGA_CLK, VGA_HS, VGA_VS, VGA_BLANK_n,
	       output logic 	  VGA_SYNC_n);




    logic [15:0] x,y;
	logic [15:0] x1,y1;
	logic [15:0] x2,y2;
	logic [15:0] x3,y3;
	logic [15:0] x4,y4;
	logic [15:0] x5,y5;

	

	wire [11:0] addr;
	wire [11:0] addr_b1;
	wire [11:0] addr_b2;
	wire [11:0] addr_b3;
	wire [11:0] addr_b4;
	wire [11:0] addr_b5;
	wire [11:0] addr_b6;
	wire [11:0] addr_s;
	wire [11:0] addr_ps;
	wire [11:0] addr_fl;
	wire [14:0] addr_bg;
	wire [11:0] addr_sc;
    wire [11:0] addr_nl;
    wire [14:0] addr_nun;
    wire [14:0] addr_sym;
    wire [14:0] addr_t;

	

	wire [11:0] M_bg1;
	wire [11:0] M_bg2;
	wire [11:0] M_bg3;
	wire [11:0] M_bg4;
	wire [11:0] M_n1;
	wire [11:0] M_n2;
	wire [11:0] M_n3;
	wire [11:0] M_b1;
	wire [11:0] M_b2;
	wire [11:0] M_b3;
	wire [11:0] M_b4;
	wire [11:0] M_b5;
	wire [11:0] M_b6;
	wire [11:0] M_s1;
	wire [11:0] M_s2;
	wire [11:0] M_s3;
	wire [11:0] M_ps;
	wire [11:0] M_dp;
	wire [11:0] M_fl;
    wire [11:0] M_sc0;
    wire [11:0] M_sc1;
    wire [11:0] M_sc2;
    wire [11:0] M_sc3;
    wire [11:0] M_sc4;
    wire [11:0] M_sc5;
    wire [11:0] M_sc6;
    wire [11:0] M_sc7;
    wire [11:0] M_sc8;
    wire [11:0] M_sc9;

    wire [11:0] M_nl1;
    wire [11:0] M_nl2;
    wire [11:0] M_nl3;

    wire[11:0] M_sun;
    wire[11:0] M_mn;
    wire[11:0] M_rn;
	
    wire[11:0] M_try;

    wire[11:0] M_nun;
    wire[11:0] M_sym;




    wire [10:0] hcount;
	wire [9:0] vcount;
	wire [10:0] xrow;
	wire [1:0] state;
	wire [2:0] screen;
	wire [2:0] level;
	wire result;

    wire [7:0] score;
    wire [3:0] one;
    wire [3:0] ten;
    wire [3:0] hun;

    reg [2:0] nin_life = 3'b000;



	VGA_LED_Emulator led_emulator(.clk50(clk), 
											.reset(reset),
											.hcount(hcount),
											.vcount(vcount),
											.VGA_CLK (VGA_CLK),
											.VGA_HS (VGA_HS),
											.VGA_VS (VGA_VS),
											.VGA_BLANK_n (VGA_BLANK_n),
											.VGA_SYNC_n (VGA_SYNC_n));

											

	ninja1 ninja1(.clock(VGA_CLK), .address(addr), .q(M_n1));
	ninja2 ninja2(.clock(VGA_CLK), .address(addr), .q(M_n2));
	ninja3 ninja3(.clock(VGA_CLK), .address(addr), .q(M_n3));
	
	reading book1(.clock(VGA_CLK), .address(addr_b1), .q(M_b1));
	exam book2(.clock(VGA_CLK), .address(addr_b2), .q(M_b2));
	homework book3(.clock(VGA_CLK), .address(addr_b3), .q(M_b3));
	bomb book4(.clock(VGA_CLK), .address(addr_b4), .q(M_b4));
	pizza book5(.clock(VGA_CLK), .address(addr_b5), .q(M_b5));
	thesis_new book6(.clock(VGA_CLK), .address(addr_b6), .q(M_b6));
	
	bg1_new  prom_bg1(.clock(VGA_CLK), .address(addr_bg), .q(M_bg1));
	bg2_new  prom_bg2(.clock(VGA_CLK), .address(addr_bg), .q(M_bg2));
	bg3_new  prom_bg3(.clock(VGA_CLK), .address(addr_bg), .q(M_bg3));
	bg4_new  prom_bg4(.clock(VGA_CLK), .address(addr_bg), .q(M_bg4));
	
	bach_new level1(.clock(VGA_CLK), .address(addr_s), .q(M_s1));
	mast_new level2(.clock(VGA_CLK), .address(addr_s), .q(M_s2));
	phd_new	level3(.clock(VGA_CLK), .address(addr_s), .q(M_s3));
	
    pass_new ps(.clock(VGA_CLK), .address(addr_s), .q(M_ps));
    fail_new fl(.clock(VGA_CLK), .address(addr_s), .q(M_fl));
	diploma_new dip0(.clock(VGA_CLK), .address(addr_s), .q(M_dp));

    zero_new2 sc0(.clock(VGA_CLK), .address(addr_sc), .q(M_sc0));
    one_new2 sc1(.clock(VGA_CLK), .address(addr_sc), .q(M_sc1));
    two_new2 sc2(.clock(VGA_CLK), .address(addr_sc), .q(M_sc2));
    three_new2 sc3(.clock(VGA_CLK), .address(addr_sc), .q(M_sc3));
    four_new2 sc4(.clock(VGA_CLK), .address(addr_sc), .q(M_sc4));
    five_new2 sc5(.clock(VGA_CLK), .address(addr_sc), .q(M_sc5));
    six_new2 sc6(.clock(VGA_CLK), .address(addr_sc), .q(M_sc6));
    seven_new2 sc7(.clock(VGA_CLK), .address(addr_sc), .q(M_sc7));
    eight_new2 sc8(.clock(VGA_CLK), .address(addr_sc), .q(M_sc8));
    nine_new2 sc9(.clock(VGA_CLK), .address(addr_sc), .q(M_sc9));
	
	life_new nl1(.clock(VGA_CLK), .address(addr_nl), .q(M_nl1));
	life_new nl2(.clock(VGA_CLK), .address(addr_nl), .q(M_nl2));
	life_new nl3(.clock(VGA_CLK), .address(addr_nl), .q(M_nl3));
    
	sun sun0(.clock(VGA_CLK), .address(addr_t), .q(M_sun));
	moon mn0(.clock(VGA_CLK), .address(addr_t), .q(M_mn));
	rain rn0(.clock(VGA_CLK), .address(addr_t), .q(M_rn));
    
	nuny_new2 nun0(.clock(VGA_CLK), .address(addr_nun), .q(M_nun));
	ninjasymbol sym0(.clock(VGA_CLK), .address(addr_sym), .q(M_sym));
    
	tryagain try0(.clock(VGA_CLK), .address(addr_t), .q(M_try));

    

	RGB_controller controller_1(.clk(VGA_CLK),
										.clk50(clk),
										.hcount(hcount),
										.vcount(vcount),
										.x(x), .y(y),
										.x1(x1), .y1(y1),
										.x2(x2), .y2(y2),
										.x3(x3), .y3(y3),
										.x4(x4), .y4(y4),
										.x5(x5), .y5(y5),
                                        .one(one),
                                        .ten(ten),
                                        .hun(hun),
										.addr(addr),
										.addr_b1(addr_b1),
										.addr_b2(addr_b2),
										.addr_b3(addr_b3),
										.addr_b4(addr_b4),
										.addr_b5(addr_b5),
										.addr_b6(addr_b6),
										.addr_s(addr_s),
										.addr_sc(addr_sc),
										.addr_nl(addr_nl),
										.addr_t(addr_t),




										.addr_nun(addr_nun),
										.addr_sym(addr_sym),
										.M_s1(M_s1),
										.M_s2(M_s2),
										.M_s3(M_s3),
										.M_n1(M_n1),
										.M_n2(M_n2),
										.M_n3(M_n3),
										.M_b1(M_b1),
										.M_b2(M_b2),
										.M_b3(M_b3),
										.M_b4(M_b4),
										.M_b5(M_b5),
										.M_b6(M_b6),
										.M_ps(M_ps),
										.M_dp(M_dp),
										.M_fl(M_fl),
                                        .M_sc0(M_sc0),
                                        .M_sc1(M_sc1),
                                        .M_sc2(M_sc2),
                                        .M_sc3(M_sc3),
                                        .M_sc4(M_sc4),
                                        .M_sc5(M_sc5),
                                        .M_sc6(M_sc6),
                                        .M_sc7(M_sc7),
                                        .M_sc8(M_sc8),
                                        .M_sc9(M_sc9),
                                        .M_nl1(M_nl1),
                                        .M_nl2(M_nl2),
                                        .M_nl3(M_nl3),
                                        .M_sun(M_sun),
                                        .M_mn(M_mn),
                                        .M_rn(M_rn),
                                        .M_try(M_try),
                                        .M_nun(M_nun),
                                        .M_sym(M_sym),
										.addr_bg(addr_bg), 
										.M_bg1(M_bg1),
										.M_bg2(M_bg2),
										.M_bg3(M_bg3),
										.M_bg4(M_bg4),
										.screen(screen),
                                        .level(level),
                                        .result(result),
										.nin_life(nin_life),

										.VGA_R(VGA_R),
					.VGA_G(VGA_G),
					.VGA_B(VGA_B)
										);




   always_ff @(posedge clk)
     if (reset) begin
	x <= 16'd300; 
	y <= 16'd200;
	x1 <= 16'd10;
	y1 <= 16'd300;
	x2 <= 16'd70;
	y2 <= 16'd300;
	x3 <= 16'd200;
	y3 <= 16'd300;
	x4 <= 16'd300;
	y4 <= 16'd300;
	x5 <= 16'd500;
	y5 <= 16'd300;
	state <= 2'b00;
	score <= 8'b0;
	nin_life <= 3'b0;
	level <= 3'b0;
	result <= 1'b0;

	end
	else if (chipselect && write)
	begin
		 
	case(address)
	4'b0000: x <= writedata;
	4'b0001: y <= writedata;
	4'b0010: x1 <= writedata; 
	4'b0011: y1 <= writedata;
	4'b0100: x2 <= writedata; 
	4'b0101: y2 <= writedata;
	4'b0110: x3 <= writedata; 
	4'b0111: y3 <= writedata;
	4'b1000: x4 <= writedata; 
	4'b1001: y4 <= writedata;
	4'b1010: x5 <= writedata; 
	4'b1011: y5 <= writedata;
	4'b1100:begin
            state <= writedata[1:0];
            level <= writedata[4:2];
            result <= writedata[5];
				end
	4'b1101: score <= writedata[7:0];
	4'b1110: nin_life <= writedata[2:0];
	4'b1111: state<= 2'b0;
	endcase
	end



	always_ff @(posedge clk) begin
	if (reset)
		screen = 3'b010;
	else case(state)
		2'b00: screen <= 3'b010;
		2'b01: screen <= 3'b001;
		2'b10: screen <= 3'b100;
		default: screen <=3'b010;
		endcase
	end




    integer i;
    always @(score) begin
        hun = 4'd0;
        ten = 4'd0;
        one = 4'd0;

        for (i = 7; i >= 0; i = i -1) begin
            if (hun >= 5)
                hun = hun + 3;
            if (ten >= 5)
                ten = ten + 3;
            if (one >= 5)
                one = one + 3;

            hun = hun << 1;
            hun[0] = ten[3];
            ten = ten << 1;
            ten[0] = one[3];
            one = one << 1;
            one[0] = score[i];
        end
    end

endmodule