data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc/rst_sync.v
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data/verilator_xmls/382a4403-0471-4163-93ec-cac8ce36d953.xml
module rst_sync(
  input      arst,
  input      clk,
  output reg rst);

  reg        rsync;
  always @(posedge clk, posedge arst) begin
    if (arst) {rst, rsync} <= 2'b11;
    else      {rst, rsync} <= {rsync, 1'b0};
  end

endmodule
module rst_sync(
  input      arst,
  input      clk,
  output reg rst);


  reg        rsync;
  always @(posedge clk, posedge arst) begin
    if (arst) {rst, rsync} <= 2'b11;
    else      {rst, rsync} <= {rsync, 1'b0};
  end

endmodule