data/full_repos/permissive/129918634/tb_new.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/129918634/tb_new.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = 1; \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129918634/tb_new.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #1 rst_n = 1;clk = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129918634/tb_new.v:32: Unsupported: Ignoring delay on this delayed statement.\n     #1 clk = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/129918634/tb_new.v:33: Unsupported: Ignoring delay on this delayed statement.\n     #1 clk = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/129918634/tb_new.v:40: Unsupported: Ignoring delay on this delayed statement.\n     #1 clk = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/129918634/tb_new.v:41: Unsupported: Ignoring delay on this delayed statement.\n     #1 clk = 0;\n     ^\n%Error: data/full_repos/permissive/129918634/tb_new.v:11: Cannot find file containing module: \'idct_top\'\n  idct_top idct_top(clk,rst_n,idct4,in,out);\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129918634,data/full_repos/permissive/129918634/idct_top\n             data/full_repos/permissive/129918634,data/full_repos/permissive/129918634/idct_top.v\n             data/full_repos/permissive/129918634,data/full_repos/permissive/129918634/idct_top.sv\n             idct_top\n             idct_top.v\n             idct_top.sv\n             obj_dir/idct_top\n             obj_dir/idct_top.v\n             obj_dir/idct_top.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestBench;

reg signed [15:0] in;
reg clk;
reg rst_n;
reg  [1:0] idct4;
wire signed [15:0] out;


	 idct_top idct_top(clk,rst_n,idct4,in,out);



reg [1:0] mode;
integer fp_r;
integer i;

initial begin
	clk = 0;
	rst_n= 0;
	idct4 = 2'b00;
    fp_r = $fopen("E:/important/it/digital_design/work/file_input.txt", "r");
    #1 clk = 1; 
    #1 rst_n = 1;clk = 0;
    while(!$feof(fp_r)) begin
	    $fscanf(fp_r,"%b",mode);
	    if (mode == 2'b00)begin
	        idct4=2'b01;
			 for(i = 0;i <= 15 ;i = i+1)begin
					$fscanf(fp_r,"%d",in); 
					#1 clk = 1;
					#1 clk = 0;
				end
	    end
	    else begin
	        idct4=2'b10;	
			 for(i = 0;i <= 63 ;i = i+1)begin
					$fscanf(fp_r,"%d",in); 
					#1 clk = 1;
					#1 clk = 0;
	    end
	end
	end
	$fclose(fp_r);
end
 
endmodule
module TestBench;


reg signed [15:0] in;
reg clk;
reg rst_n;
reg  [1:0] idct4;
wire signed [15:0] out;


	 idct_top idct_top(clk,rst_n,idct4,in,out);



reg [1:0] mode;
integer fp_r;
integer i;

initial begin
	clk = 0;
	rst_n= 0;
	idct4 = 2'b00;
    fp_r = $fopen("E:/important/it/digital_design/work/file_input.txt", "r");
    #1 clk = 1; 
    #1 rst_n = 1;clk = 0;
    while(!$feof(fp_r)) begin
	    $fscanf(fp_r,"%b",mode);
	    if (mode == 2'b00)begin
	        idct4=2'b01;
			 for(i = 0;i <= 15 ;i = i+1)begin
					$fscanf(fp_r,"%d",in); 
					#1 clk = 1;
					#1 clk = 0;
				end
	    end
	    else begin
	        idct4=2'b10;	
			 for(i = 0;i <= 63 ;i = i+1)begin
					$fscanf(fp_r,"%d",in); 
					#1 clk = 1;
					#1 clk = 0;
	    end
	end
	end
	$fclose(fp_r);
end
 
endmodule