data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v
 line:259: before: "("
1: b'%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:30: Cannot find include file: reg_defs.v\n`include "reg_defs.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21203606/wishbone_uart_tx,data/full_repos/permissive/21203606/reg_defs.v\n             data/full_repos/permissive/21203606/wishbone_uart_tx,data/full_repos/permissive/21203606/reg_defs.v.v\n             data/full_repos/permissive/21203606/wishbone_uart_tx,data/full_repos/permissive/21203606/reg_defs.v.sv\n             reg_defs.v\n             reg_defs.v.v\n             reg_defs.v.sv\n             obj_dir/reg_defs.v\n             obj_dir/reg_defs.v.v\n             obj_dir/reg_defs.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #5 tb_rst <= 1\'b1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #20 tb_rst <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #20 clka <= ~clka;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #40 clkb <= ~clkb;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #80 clkc <= ~clkc;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #160 clkd <= ~clkd;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #10 tb_clk <= ~tb_clk;\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:134: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:140: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:143: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:157: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:162: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:165: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:189: Define or directive not defined: \'`UART_STATUS\'\n  #1 wb_read(`UART_STATUS);\n             ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n  #1 wb_read(`UART_STATUS);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:186: Unsupported: wait statements\n  wait(tb_en)\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n  #1 if(read_data != 8\'h01) $stop;\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:192: Define or directive not defined: \'`UART_DATAREG\'\n  #1 wb_write(`UART_DATAREG, 8\'b10101010);\n              ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #1 wb_write(`UART_DATAREG, 8\'b10101010);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:193: Define or directive not defined: \'`UART_DATAREG\'\n  #1 wb_read(`UART_DATAREG);\n             ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n  #1 wb_read(`UART_DATAREG);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n  #1 if(read_data != 8\'b10101010) $stop;\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:196: Define or directive not defined: \'`UART_STATUS\'\n  #1 wb_write(`UART_STATUS, 8\'h01);\n              ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n  #1 wb_write(`UART_STATUS, 8\'h01);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:197: Define or directive not defined: \'`UART_STATUS\'\n  #1 wb_read(`UART_STATUS);\n             ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n  #1 wb_read(`UART_STATUS);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:199: Unsupported: wait statements\n  wait (krake_porti.tx_rdy == 1);\n  ^~~~\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:200: Define or directive not defined: \'`UART_STATUS\'\n  #1 wb_read(`UART_STATUS);\n             ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n  #1 wb_read(`UART_STATUS);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:201: Unsupported: Ignoring delay on this delayed statement.\n  #1 if(read_data != 8\'b00000001) $stop;\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:203: Define or directive not defined: \'`UART_DATAREG\'\n  #1 wb_write(`UART_DATAREG, 8\'b00001111);\n              ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n  #1 wb_write(`UART_DATAREG, 8\'b00001111);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:204: Define or directive not defined: \'`UART_STATUS\'\n  #1 wb_write(`UART_STATUS, 8\'b00000001);\n              ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:204: Unsupported: Ignoring delay on this delayed statement.\n  #1 wb_write(`UART_STATUS, 8\'b00000001);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:205: Define or directive not defined: \'`UART_STATUS\'\n  #1 wb_read(`UART_STATUS);\n             ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:205: Unsupported: Ignoring delay on this delayed statement.\n  #1 wb_read(`UART_STATUS);\n  ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:206: Unsupported: wait statements\n  wait (krake_porti.tx_rdy == 1);\n  ^~~~\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:207: Define or directive not defined: \'`UART_STATUS\'\n  #1 wb_read(`UART_STATUS);\n             ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:207: Unsupported: Ignoring delay on this delayed statement.\n  #1 wb_read(`UART_STATUS);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21203606/wishbone_uart_tx/krake_port_tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n  #1 if(read_data != 8\'b00000001) $stop;\n  ^\n%Error: Exiting due to 20 error(s), 21 warning(s)\n'
module krake_port_tb();

reg tb_clk;
reg tb_rst;
reg tb_en;

wire  tb_dout;

reg clka;
reg clkb;
reg clkc;
reg clkd;

reg        tb_we_o;
reg  [7:0] tb_dat_o;
reg  [4:0] tb_adr_o;
reg        tb_stb_o;
wire [7:0] tb_dat_i;
wire       tb_ack_i;

reg  [7:0] tb_cnt_a;
reg  [7:0] tb_cnt_d;

wire  [5:0] ch_in;
wire  [5:0] ch_out;
wire  [5:0] ch_oe;

krake_port_tx2 krake_porti(
    .clk_i(tb_clk),
    .rst_i(tb_rst),
    .ack_o(tb_ack_i),
    .dat_i(tb_dat_o),
    .adr_i(tb_adr_o),
    .dat_o(tb_dat_i),
    .stb_i(tb_stb_o),
    .we_i(tb_we_o),
    .ch_in(ch_in),
    .ch_out(ch_out),
    .ch_oe(ch_oe),
    .clka(clka),
    .clkb(clkb),
    .clkc(clkc),
    .clkd(clkd));

assign ch_in[0] = ch_oe[0] ? ch_out[0] : 1'bz;
assign ch_in[1] = ch_oe[1] ? ch_out[1] : 1'bz;
assign ch_in[2] = ch_oe[2] ? ch_out[2] : 1'bz;
assign ch_in[3] = ch_oe[3] ? ch_out[3] : 1'bz;
assign ch_in[4] = ch_oe[4] ? ch_out[4] : 1'bz;
assign ch_in[5] = ch_oe[5] ? ch_out[5] : 1'bz;


initial
begin
  tb_clk <= 1'b0;
  tb_rst <= 1'b0;
  tb_en <= 1'b0;
  clka <= 1'b0;
  clkb <= 1'b0;
  clkc <= 1'b0;
  clkd <= 1'b0;
  #5 tb_rst <= 1'b1;
  #20 tb_rst <= 1'b0;
  tb_en <= 1'b1;
end


always
begin
  #20 clka <= ~clka;
end


always
begin
  #40 clkb <= ~clkb;
end


always
begin
  #80 clkc <= ~clkc;
end


always
begin
  #160 clkd <= ~clkd;
end


always
begin
  #10 tb_clk <= ~tb_clk;
end


task wb_write;
input [7:0] adr_o;
input [7:0] dat_o;

begin
  @(posedge tb_clk);
  tb_stb_o <= 1'b1;
  tb_we_o <= 1'b1;
  tb_dat_o <= dat_o;
  tb_adr_o <= adr_o;

  @(posedge tb_clk);
  tb_stb_o <= 1'b0;

  @(posedge tb_clk);
  if(!tb_ack_i)
  begin
    $display("Write failed: 0x%02H, 0x%02H", tb_adr_o, tb_dat_o);
  end
end
endtask

reg [7:0] read_data;

task wb_read;
input [7:0] adr_o;

begin
  @(posedge tb_clk);
  tb_stb_o <= 1'b1;
  tb_we_o <= 1'b0;
  tb_adr_o <= adr_o;

  @(posedge tb_clk);
  tb_stb_o <= 1'b0;

  @(posedge tb_clk);
  read_data <= tb_dat_i;

  if(!tb_ack_i)
  begin
    $display("Read failed: 0x%02H, 0x%02H", tb_adr_o, tb_dat_i);
  end
end
endtask

always @(posedge tb_rst)
begin
  tb_dat_o <= 8'h00;
  tb_we_o <= 1'b0;
  tb_adr_o <= 4'd0;
  tb_cnt_a <= 8'd0;
  tb_cnt_d <= 8'd0;
end

initial
begin
  wait(tb_en)


  #1 wb_read(`UART_STATUS);
  #1 if(read_data != 8'h01) $stop;

  #1 wb_write(`UART_DATAREG, 8'b10101010);
  #1 wb_read(`UART_DATAREG);
  #1 if(read_data != 8'b10101010) $stop;
  
  #1 wb_write(`UART_STATUS, 8'h01);
  #1 wb_read(`UART_STATUS);
  
  wait (krake_porti.tx_rdy == 1);
  #1 wb_read(`UART_STATUS);
  #1 if(read_data != 8'b00000001) $stop;
  
  #1 wb_write(`UART_DATAREG, 8'b00001111);
  #1 wb_write(`UART_STATUS, 8'b00000001);
  #1 wb_read(`UART_STATUS);
  wait (krake_porti.tx_rdy == 1);
  #1 wb_read(`UART_STATUS);
  #1 if(read_data != 8'b00000001) $stop;
    


















































end
endmodule
module krake_port_tb();


reg tb_clk;
reg tb_rst;
reg tb_en;

wire  tb_dout;

reg clka;
reg clkb;
reg clkc;
reg clkd;

reg        tb_we_o;
reg  [7:0] tb_dat_o;
reg  [4:0] tb_adr_o;
reg        tb_stb_o;
wire [7:0] tb_dat_i;
wire       tb_ack_i;

reg  [7:0] tb_cnt_a;
reg  [7:0] tb_cnt_d;

wire  [5:0] ch_in;
wire  [5:0] ch_out;
wire  [5:0] ch_oe;

krake_port_tx2 krake_porti(
    .clk_i(tb_clk),
    .rst_i(tb_rst),
    .ack_o(tb_ack_i),
    .dat_i(tb_dat_o),
    .adr_i(tb_adr_o),
    .dat_o(tb_dat_i),
    .stb_i(tb_stb_o),
    .we_i(tb_we_o),
    .ch_in(ch_in),
    .ch_out(ch_out),
    .ch_oe(ch_oe),
    .clka(clka),
    .clkb(clkb),
    .clkc(clkc),
    .clkd(clkd));

assign ch_in[0] = ch_oe[0] ? ch_out[0] : 1'bz;
assign ch_in[1] = ch_oe[1] ? ch_out[1] : 1'bz;
assign ch_in[2] = ch_oe[2] ? ch_out[2] : 1'bz;
assign ch_in[3] = ch_oe[3] ? ch_out[3] : 1'bz;
assign ch_in[4] = ch_oe[4] ? ch_out[4] : 1'bz;
assign ch_in[5] = ch_oe[5] ? ch_out[5] : 1'bz;


initial
begin
  tb_clk <= 1'b0;
  tb_rst <= 1'b0;
  tb_en <= 1'b0;
  clka <= 1'b0;
  clkb <= 1'b0;
  clkc <= 1'b0;
  clkd <= 1'b0;
  #5 tb_rst <= 1'b1;
  #20 tb_rst <= 1'b0;
  tb_en <= 1'b1;
end


always
begin
  #20 clka <= ~clka;
end


always
begin
  #40 clkb <= ~clkb;
end


always
begin
  #80 clkc <= ~clkc;
end


always
begin
  #160 clkd <= ~clkd;
end


always
begin
  #10 tb_clk <= ~tb_clk;
end


task wb_write;
input [7:0] adr_o;
input [7:0] dat_o;

begin
  @(posedge tb_clk);
  tb_stb_o <= 1'b1;
  tb_we_o <= 1'b1;
  tb_dat_o <= dat_o;
  tb_adr_o <= adr_o;

  @(posedge tb_clk);
  tb_stb_o <= 1'b0;

  @(posedge tb_clk);
  if(!tb_ack_i)
  begin
    $display("Write failed: 0x%02H, 0x%02H", tb_adr_o, tb_dat_o);
  end
end
endtask

reg [7:0] read_data;

task wb_read;
input [7:0] adr_o;

begin
  @(posedge tb_clk);
  tb_stb_o <= 1'b1;
  tb_we_o <= 1'b0;
  tb_adr_o <= adr_o;

  @(posedge tb_clk);
  tb_stb_o <= 1'b0;

  @(posedge tb_clk);
  read_data <= tb_dat_i;

  if(!tb_ack_i)
  begin
    $display("Read failed: 0x%02H, 0x%02H", tb_adr_o, tb_dat_i);
  end
end
endtask

always @(posedge tb_rst)
begin
  tb_dat_o <= 8'h00;
  tb_we_o <= 1'b0;
  tb_adr_o <= 4'd0;
  tb_cnt_a <= 8'd0;
  tb_cnt_d <= 8'd0;
end

initial
begin
  wait(tb_en)


  #1 wb_read(`UART_STATUS);
  #1 if(read_data != 8'h01) $stop;

  #1 wb_write(`UART_DATAREG, 8'b10101010);
  #1 wb_read(`UART_DATAREG);
  #1 if(read_data != 8'b10101010) $stop;
  
  #1 wb_write(`UART_STATUS, 8'h01);
  #1 wb_read(`UART_STATUS);
  
  wait (krake_porti.tx_rdy == 1);
  #1 wb_read(`UART_STATUS);
  #1 if(read_data != 8'b00000001) $stop;
  
  #1 wb_write(`UART_DATAREG, 8'b00001111);
  #1 wb_write(`UART_STATUS, 8'b00000001);
  #1 wb_read(`UART_STATUS);
  wait (krake_porti.tx_rdy == 1);
  #1 wb_read(`UART_STATUS);
  #1 if(read_data != 8'b00000001) $stop;
    


















































end
endmodule