data/full_repos/permissive/125927162/COUNTER/counter_tb.v
 line:43: before: "$"
1: b'%Error: data/full_repos/permissive/125927162/COUNTER/counter_tb.v:28: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("counter.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/COUNTER/counter_tb.v:29: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, counter_tb);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/COUNTER/counter_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/COUNTER/counter_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/COUNTER/counter_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/COUNTER/counter_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/COUNTER/counter_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #150\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/COUNTER/counter_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk = ~clk;\n          ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_tb ();
   localparam WIDTH = 8;
   reg clk;
   reg updown;
   reg rst;
   wire [WIDTH-1:0] out;

   counter #(.WIDTH(WIDTH)) DUT(
	       .clk(clk),
	       .updown(updown),
	       .rst(rst),
	       .out(out)
	       );

   initial begin
      $dumpfile("counter.vcd");
      $dumpvars(0, counter_tb);
      clk = 0;
      updown = 1;
      rst = 0;
      #1
	rst = 1;
      #1
	clk = 1;
      #1
	rst = 0;
      clk = 0;
      #100
	updown = 0;
      #150
	$finish;
   end

   always #1 clk = ~clk;
endmodule
module counter_tb ();

   localparam WIDTH = 8;
   reg clk;
   reg updown;
   reg rst;
   wire [WIDTH-1:0] out;

   counter #(.WIDTH(WIDTH)) DUT(
	       .clk(clk),
	       .updown(updown),
	       .rst(rst),
	       .out(out)
	       );

   initial begin
      $dumpfile("counter.vcd");
      $dumpvars(0, counter_tb);
      clk = 0;
      updown = 1;
      rst = 0;
      #1
	rst = 1;
      #1
	clk = 1;
      #1
	rst = 0;
      clk = 0;
      #100
	updown = 0;
      #150
	$finish;
   end

   always #1 clk = ~clk;
endmodule