data/full_repos/permissive/136197078/hardware/ip/nt_gen_rate_ctrl/hdl/nt_gen_rate_ctrl.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_gen_rate_ctrl/hdl/nt_gen_rate_ctrl.v:149: Operator GT expects 64 bits on the RHS, but RHS\'s VARREF \'n_cycles_interpacket\' generates 32 bits.\n                                                                                                            : ... In instance nt_gen_rate_ctrl\n          if (cntr_cycles_interpacket > n_cycles_interpacket) begin\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_gen_rate_ctrl/hdl/nt_gen_rate_ctrl.v:171: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'n_cycles_interpacket\' generates 32 bits.\n                                                                                                            : ... In instance nt_gen_rate_ctrl\n          end if (cntr_cycles_interpacket >= (n_cycles_interpacket - 1)) begin\n                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_gen_rate_ctrl/hdl/nt_gen_rate_ctrl.v:190: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'n_cycles_interpacket\' generates 32 bits.\n                                                                                                            : ... In instance nt_gen_rate_ctrl\n        end if (cntr_cycles_interpacket == (n_cycles_interpacket - 1)) begin\n                                                                 ^\n%Error: Exiting due to 3 warning(s)\n'
module nt_gen_rate_ctrl (

  input wire          clk,
  input wire          rstn,
  input wire          rst_sw,


  input wire [63:0]   s_axis_tdata,
  input wire          s_axis_tvalid,
  input wire          s_axis_tlast,
  input wire [7:0]    s_axis_tkeep,
  input wire [31:0]   s_axis_tuser,
  output wire         s_axis_tready,


  output wire [63:0]  m_axis_tdata,
  output wire         m_axis_tvalid,
  output wire         m_axis_tlast,
  output wire [7:0]   m_axis_tkeep,
  input wire          m_axis_tready,


  input wire          ctrl_active_i,


  output wire         status_warn_timing_o
);

  localparam  RST           = 3'b000,
              IDLE          = 3'b001,
              TX_START      = 3'b010,
              TX            = 3'b011,
              WAIT          = 3'b100;

  reg [2:0] state, nxt_state;


  reg [31:0] n_cycles_interpacket, nxt_n_cycles_interpacket;



  reg [63:0] cntr_cycles_interpacket, nxt_cntr_cycles_interpacket;



  reg warn_timing, nxt_warn_timing;
  assign status_warn_timing_o = warn_timing;



  reg do_transfer, nxt_do_transfer;

  assign m_axis_tdata = s_axis_tdata;
  assign m_axis_tlast = s_axis_tlast;
  assign m_axis_tkeep = s_axis_tkeep;
  assign m_axis_tvalid = s_axis_tvalid & do_transfer;
  assign s_axis_tready = m_axis_tready & do_transfer;

  always @(posedge clk) begin
    if (~rstn | rst_sw) begin
      state <= RST;
    end else begin
      state <= nxt_state;
    end

    n_cycles_interpacket <= nxt_n_cycles_interpacket;
    cntr_cycles_interpacket <= nxt_cntr_cycles_interpacket;
    warn_timing <= nxt_warn_timing;
    do_transfer <= nxt_do_transfer;
  end

  always @(*) begin
    nxt_state = state;
    nxt_n_cycles_interpacket = n_cycles_interpacket;
    nxt_cntr_cycles_interpacket = cntr_cycles_interpacket + 1;
    nxt_warn_timing = warn_timing;
    nxt_do_transfer = 1'b0;

    case (state)

      RST: begin

        nxt_warn_timing = 1'b0;
        nxt_state = IDLE;
      end

      IDLE: begin
        if (ctrl_active_i) begin


          nxt_state = TX_START;
          nxt_n_cycles_interpacket = 1;
          nxt_cntr_cycles_interpacket = 1;
          nxt_do_transfer = 1'b1;
        end
      end

      TX_START: begin
        if (~ctrl_active_i) begin

          nxt_state = IDLE;
        end if (s_axis_tvalid) begin
          if (cntr_cycles_interpacket > n_cycles_interpacket) begin

            nxt_warn_timing = 1'b1;
          end

          if (s_axis_tready) begin

            nxt_state = TX;
            nxt_n_cycles_interpacket = s_axis_tuser;
            nxt_cntr_cycles_interpacket = 1;
          end
        end

        nxt_do_transfer = 1'b1;
      end

      TX: begin
        if (s_axis_tvalid & s_axis_tready & s_axis_tlast) begin

          if (~ctrl_active_i) begin

            nxt_state = IDLE;
          end if (cntr_cycles_interpacket >= (n_cycles_interpacket - 1)) begin

            nxt_state = TX_START;
            nxt_do_transfer = 1'b1;
          end else begin

            nxt_state = WAIT;
          end
        end else begin


          nxt_do_transfer = 1'b1;
        end
      end

      WAIT: begin
        if (~ctrl_active_i) begin

          nxt_state = IDLE;
        end if (cntr_cycles_interpacket == (n_cycles_interpacket - 1)) begin

          nxt_state = TX_START;
          nxt_do_transfer = 1'b1;
        end
      end

    endcase
  end

endmodule
module nt_gen_rate_ctrl (

  input wire          clk,
  input wire          rstn,
  input wire          rst_sw,


  input wire [63:0]   s_axis_tdata,
  input wire          s_axis_tvalid,
  input wire          s_axis_tlast,
  input wire [7:0]    s_axis_tkeep,
  input wire [31:0]   s_axis_tuser,
  output wire         s_axis_tready,


  output wire [63:0]  m_axis_tdata,
  output wire         m_axis_tvalid,
  output wire         m_axis_tlast,
  output wire [7:0]   m_axis_tkeep,
  input wire          m_axis_tready,


  input wire          ctrl_active_i,


  output wire         status_warn_timing_o
);


  localparam  RST           = 3'b000,
              IDLE          = 3'b001,
              TX_START      = 3'b010,
              TX            = 3'b011,
              WAIT          = 3'b100;

  reg [2:0] state, nxt_state;


  reg [31:0] n_cycles_interpacket, nxt_n_cycles_interpacket;



  reg [63:0] cntr_cycles_interpacket, nxt_cntr_cycles_interpacket;



  reg warn_timing, nxt_warn_timing;
  assign status_warn_timing_o = warn_timing;



  reg do_transfer, nxt_do_transfer;

  assign m_axis_tdata = s_axis_tdata;
  assign m_axis_tlast = s_axis_tlast;
  assign m_axis_tkeep = s_axis_tkeep;
  assign m_axis_tvalid = s_axis_tvalid & do_transfer;
  assign s_axis_tready = m_axis_tready & do_transfer;

  always @(posedge clk) begin
    if (~rstn | rst_sw) begin
      state <= RST;
    end else begin
      state <= nxt_state;
    end

    n_cycles_interpacket <= nxt_n_cycles_interpacket;
    cntr_cycles_interpacket <= nxt_cntr_cycles_interpacket;
    warn_timing <= nxt_warn_timing;
    do_transfer <= nxt_do_transfer;
  end

  always @(*) begin
    nxt_state = state;
    nxt_n_cycles_interpacket = n_cycles_interpacket;
    nxt_cntr_cycles_interpacket = cntr_cycles_interpacket + 1;
    nxt_warn_timing = warn_timing;
    nxt_do_transfer = 1'b0;

    case (state)

      RST: begin

        nxt_warn_timing = 1'b0;
        nxt_state = IDLE;
      end

      IDLE: begin
        if (ctrl_active_i) begin


          nxt_state = TX_START;
          nxt_n_cycles_interpacket = 1;
          nxt_cntr_cycles_interpacket = 1;
          nxt_do_transfer = 1'b1;
        end
      end

      TX_START: begin
        if (~ctrl_active_i) begin

          nxt_state = IDLE;
        end if (s_axis_tvalid) begin
          if (cntr_cycles_interpacket > n_cycles_interpacket) begin

            nxt_warn_timing = 1'b1;
          end

          if (s_axis_tready) begin

            nxt_state = TX;
            nxt_n_cycles_interpacket = s_axis_tuser;
            nxt_cntr_cycles_interpacket = 1;
          end
        end

        nxt_do_transfer = 1'b1;
      end

      TX: begin
        if (s_axis_tvalid & s_axis_tready & s_axis_tlast) begin

          if (~ctrl_active_i) begin

            nxt_state = IDLE;
          end if (cntr_cycles_interpacket >= (n_cycles_interpacket - 1)) begin

            nxt_state = TX_START;
            nxt_do_transfer = 1'b1;
          end else begin

            nxt_state = WAIT;
          end
        end else begin


          nxt_do_transfer = 1'b1;
        end
      end

      WAIT: begin
        if (~ctrl_active_i) begin

          nxt_state = IDLE;
        end if (cntr_cycles_interpacket == (n_cycles_interpacket - 1)) begin

          nxt_state = TX_START;
          nxt_do_transfer = 1'b1;
        end
      end

    endcase
  end

endmodule