data/full_repos/permissive/181665138/verilog/capitolo_v/Elemento_Contatore_Base_2.v
 line:28: before: "?"
1: b'%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/Elemento_Contatore_Base_2.v:28: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n                    ? \'B01;\n                    ^\n%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/Elemento_Contatore_Base_2.v:30: syntax error, unexpected ==, expecting \')\' or \',\' or or\n    always @(reset_ == 0) #1 OUTR <= 0;\n                    ^~\n%Warning-STMTDLY: data/full_repos/permissive/181665138/verilog/capitolo_v/Elemento_Contatore_Base_2.v:31: Unsupported: Ignoring delay on this delayed statement.\n    always @(posedge clock) if (reset_ == 1) #3 OUTR <= a;\n                                             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module Elemento_Contatore_Base_2(eu, q, ei, clock, reset_);
    input clock, reset_;
    input ei;
    output eu, q;
    
    reg OUTR;
    assign q=OUTR;

    wire a;

    assign {a, eu} = ({q, ei} == 'B00)? 'B00:
                     ({q, ei} == 'B10)? 'B10:
                     ({q, ei} == 'B01)? 'B10:
? 'B01;
    
    always @(reset_ == 0) #1 OUTR <= 0;
    always @(posedge clock) if (reset_ == 1) #3 OUTR <= a;
endmodule
module Elemento_Contatore_Base_2(eu, q, ei, clock, reset_);

    input clock, reset_;
    input ei;
    output eu, q;
    
    reg OUTR;
    assign q=OUTR;

    wire a;

    assign {a, eu} = ({q, ei} == 'B00)? 'B00:
                     ({q, ei} == 'B10)? 'B10:
                     ({q, ei} == 'B01)? 'B10:
? 'B01;
    
    always @(reset_ == 0) #1 OUTR <= 0;
    always @(posedge clock) if (reset_ == 1) #3 OUTR <= a;
endmodule