data/full_repos/permissive/170013753/src/alu.v
data/verilator_xmls/de5463ac-d08d-4c7a-844f-a948b0731995.xml
module alu(
  input [15:0] a,
  input [15:0] b,
  input  [2:0] op,

  output reg fZ,
  output reg fC,
  output reg fN,
  output reg fV,

  output reg [15:0] o
);

always @(*) begin
  case(op)
    

    3'b000: begin
      {fC, o} = a + b;

      fV = (~(a[15] ^ b[15])) & (a[15] ^ o[15]);
    end
    

    3'b001: begin
      {fC, o} = a - b;

      fV = (a[15] ^ b[15]) & (~(b[15] ^ o[15]));
    end


    3'b010: begin
      o = a & b;
      fC = 1'b0;
      fV = 1'b0;
    end


    3'b011: begin 
      o = a | b;
      fC = 1'b0;
      fV = 1'b0;
    end


    3'b100: begin  
      o = ~a;
      fC = 1'b0;
      fV = 1'b0;
    end


    3'b101: begin 
      o = a ^ b;
      fC = 1'b0;
      fV = 1'b0;
    end


    3'b110: begin 
      o = a >> 1;
      fC = 1'b0;
      fV = 1'b0;
    end


    3'b111: begin 
      o = a << 1;
      fC = 1'b0;
      fV = 1'b0;
    end


    default: begin
      {fC, o} = a + b;
      fV = (~(a[15] ^ b[15])) & (a[15] ^ o[15]);
    end

  endcase

  fZ = (o == 16'b0) ? 1'b1 : 1'b0;
  fN = o[15];
end

endmodule
module alu(
  input [15:0] a,
  input [15:0] b,
  input  [2:0] op,

  output reg fZ,
  output reg fC,
  output reg fN,
  output reg fV,

  output reg [15:0] o
);


always @(*) begin
  case(op)
    

    3'b000: begin
      {fC, o} = a + b;

      fV = (~(a[15] ^ b[15])) & (a[15] ^ o[15]);
    end
    

    3'b001: begin
      {fC, o} = a - b;

      fV = (a[15] ^ b[15]) & (~(b[15] ^ o[15]));
    end


    3'b010: begin
      o = a & b;
      fC = 1'b0;
      fV = 1'b0;
    end


    3'b011: begin 
      o = a | b;
      fC = 1'b0;
      fV = 1'b0;
    end


    3'b100: begin  
      o = ~a;
      fC = 1'b0;
      fV = 1'b0;
    end


    3'b101: begin 
      o = a ^ b;
      fC = 1'b0;
      fV = 1'b0;
    end


    3'b110: begin 
      o = a >> 1;
      fC = 1'b0;
      fV = 1'b0;
    end


    3'b111: begin 
      o = a << 1;
      fC = 1'b0;
      fV = 1'b0;
    end


    default: begin
      {fC, o} = a + b;
      fV = (~(a[15] ^ b[15])) & (a[15] ^ o[15]);
    end

  endcase

  fZ = (o == 16'b0) ? 1'b1 : 1'b0;
  fN = o[15];
end

endmodule