data/full_repos/permissive/141582589/src/common_rtl/video/demux.v
data/verilator_xmls/5fd1ce21-efba-4de0-8a44-1efcfe36530b.xml
module demux(
	input clk_108m,
	input clk_27m,
	input[7:0] vin_data,
	output reg[7:0] vout_data_ch0,
	output reg[7:0] vout_data_ch1,
	output reg[7:0] vout_data_ch2,
	output reg[7:0] vout_data_ch3
);
reg[1:0] vin_cnt;
reg[1:0] vin_cnt_d0;
reg[7:0] data0,data1,data2,data3;
reg[7:0] data0_d0;
reg[7:0] data1_d0;
reg[7:0] data2_d0;
reg[7:0] data3_d0;
reg[7:0] data0_d1;
reg[7:0] data0_d2;
reg[7:0] data0_d3;
reg[7:0] data0_d4;
reg[3:0] data0_id;

reg[7:0] vin_data_d0;
always@(posedge clk_108m)
begin
	vin_cnt <= vin_cnt + 2'd1;
	vin_data_d0 <= vin_data;
	vin_cnt_d0 <= vin_cnt;
end

always@(posedge clk_108m)
begin
	case(vin_cnt_d0)
		2'd0:
			begin
				data0 <= vin_data_d0;
				data1 <= data1;
				data2 <= data2;
				data3 <= data3;
			end
		2'd1:
			begin
				data0 <= data0;
				data1 <= vin_data_d0;
				data2 <= data2;
				data3 <= data3;
			end
		2'd2:
			begin
				data0 <= data0;
				data1 <= data1;
				data2 <= vin_data_d0;
				data3 <= data3;
			end
		2'd3:
			begin
				data0 <= data0;
				data1 <= data1;
				data2 <= data2;
				data3 <= vin_data_d0;
			end
		default:
			begin
				data0 <= data0;
				data1 <= data1;
				data2 <= data2;
				data3 <= data3;
			end
	endcase
end

always@(posedge clk_27m)
begin
	data0_d0 <= data0;
	data1_d0 <= data1;
	data2_d0 <= data2;
	data3_d0 <= data3;
	data0_d1 <= data0_d0;
	data0_d2 <= data0_d1;
	data0_d3 <= data0_d2;
	data0_d4 <= data0_d3;
end

always@(posedge clk_27m)
begin
	if(data0_d4 == 8'hff && data0_d3 == 8'h00 && data0_d2 == 8'h00)
		data0_id <= data0_d1[3:0];
	else
		data0_id <= data0_id;		
end

always@(posedge clk_27m)
begin
	case(data0_id)
		4'd0:
			begin
				vout_data_ch0 <= data0_d0;
				vout_data_ch1 <= data1_d0;
				vout_data_ch2 <= data2_d0;
				vout_data_ch3 <= data3_d0;
			end
		4'd1:
			begin
				vout_data_ch0 <= data3_d0;
				vout_data_ch1 <= data0_d0;
				vout_data_ch2 <= data1_d0;
				vout_data_ch3 <= data2_d0;
			end
		4'd2:
			begin
				vout_data_ch0 <= data2_d0;
				vout_data_ch1 <= data3_d0;
				vout_data_ch2 <= data0_d0;
				vout_data_ch3 <= data1_d0;
			end
		4'd3:
			begin
				vout_data_ch0 <= data1_d0;
				vout_data_ch1 <= data2_d0;
				vout_data_ch2 <= data3_d0;
				vout_data_ch3 <= data0_d0;
			end
		default:
			begin
				vout_data_ch0 <= data0_d0;
				vout_data_ch1 <= data1_d0;
				vout_data_ch2 <= data2_d0;
				vout_data_ch3 <= data3_d0;
			end
	endcase
end

endmodule
module demux(
	input clk_108m,
	input clk_27m,
	input[7:0] vin_data,
	output reg[7:0] vout_data_ch0,
	output reg[7:0] vout_data_ch1,
	output reg[7:0] vout_data_ch2,
	output reg[7:0] vout_data_ch3
);

reg[1:0] vin_cnt;
reg[1:0] vin_cnt_d0;
reg[7:0] data0,data1,data2,data3;
reg[7:0] data0_d0;
reg[7:0] data1_d0;
reg[7:0] data2_d0;
reg[7:0] data3_d0;
reg[7:0] data0_d1;
reg[7:0] data0_d2;
reg[7:0] data0_d3;
reg[7:0] data0_d4;
reg[3:0] data0_id;

reg[7:0] vin_data_d0;
always@(posedge clk_108m)
begin
	vin_cnt <= vin_cnt + 2'd1;
	vin_data_d0 <= vin_data;
	vin_cnt_d0 <= vin_cnt;
end

always@(posedge clk_108m)
begin
	case(vin_cnt_d0)
		2'd0:
			begin
				data0 <= vin_data_d0;
				data1 <= data1;
				data2 <= data2;
				data3 <= data3;
			end
		2'd1:
			begin
				data0 <= data0;
				data1 <= vin_data_d0;
				data2 <= data2;
				data3 <= data3;
			end
		2'd2:
			begin
				data0 <= data0;
				data1 <= data1;
				data2 <= vin_data_d0;
				data3 <= data3;
			end
		2'd3:
			begin
				data0 <= data0;
				data1 <= data1;
				data2 <= data2;
				data3 <= vin_data_d0;
			end
		default:
			begin
				data0 <= data0;
				data1 <= data1;
				data2 <= data2;
				data3 <= data3;
			end
	endcase
end

always@(posedge clk_27m)
begin
	data0_d0 <= data0;
	data1_d0 <= data1;
	data2_d0 <= data2;
	data3_d0 <= data3;
	data0_d1 <= data0_d0;
	data0_d2 <= data0_d1;
	data0_d3 <= data0_d2;
	data0_d4 <= data0_d3;
end

always@(posedge clk_27m)
begin
	if(data0_d4 == 8'hff && data0_d3 == 8'h00 && data0_d2 == 8'h00)
		data0_id <= data0_d1[3:0];
	else
		data0_id <= data0_id;		
end

always@(posedge clk_27m)
begin
	case(data0_id)
		4'd0:
			begin
				vout_data_ch0 <= data0_d0;
				vout_data_ch1 <= data1_d0;
				vout_data_ch2 <= data2_d0;
				vout_data_ch3 <= data3_d0;
			end
		4'd1:
			begin
				vout_data_ch0 <= data3_d0;
				vout_data_ch1 <= data0_d0;
				vout_data_ch2 <= data1_d0;
				vout_data_ch3 <= data2_d0;
			end
		4'd2:
			begin
				vout_data_ch0 <= data2_d0;
				vout_data_ch1 <= data3_d0;
				vout_data_ch2 <= data0_d0;
				vout_data_ch3 <= data1_d0;
			end
		4'd3:
			begin
				vout_data_ch0 <= data1_d0;
				vout_data_ch1 <= data2_d0;
				vout_data_ch2 <= data3_d0;
				vout_data_ch3 <= data0_d0;
			end
		default:
			begin
				vout_data_ch0 <= data0_d0;
				vout_data_ch1 <= data1_d0;
				vout_data_ch2 <= data2_d0;
				vout_data_ch3 <= data3_d0;
			end
	endcase
end

endmodule