data/full_repos/permissive/169615268/behav_srams.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/169615268/behav_srams.v:60: Multiple top level modules\n                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                        : ... Top module \'mem_ext\'\nmodule mem_ext(\n       ^~~~~~~\n                                                                        : ... Top module \'mem_0_ext\'\nmodule mem_0_ext(\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/169615268/behav_srams.v:86: Cannot find file containing module: \'simpleuart\'\n simpleuart uart (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169615268,data/full_repos/permissive/169615268/simpleuart\n             data/full_repos/permissive/169615268,data/full_repos/permissive/169615268/simpleuart.v\n             data/full_repos/permissive/169615268,data/full_repos/permissive/169615268/simpleuart.sv\n             simpleuart\n             simpleuart.v\n             simpleuart.sv\n             obj_dir/simpleuart\n             obj_dir/simpleuart.v\n             obj_dir/simpleuart.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module mem_0_ext(
	input         reset,
	input         uart_rx,
	output        uart_tx,
	output [ 7:0] led,

	input         W0_clk,
	input  [ 8:0] W0_addr,
	input         W0_en,
	input  [63:0] W0_data,
	input  [ 7:0] W0_mask,
	input         R0_clk,
	input  [ 8:0] R0_addr,
	input         R0_en,
	output [63:0] R0_data
);
	reg [8:0] reg_R0_addr;
	reg [7:0] reg_led;

	wire        uart_dat_we, uart_dat_wait;
	wire [ 3:0] uart_div_we;
	wire [31:0] uart_dat_do, uart_div_do;

	assign uart_dat_we = (W0_en && W0_addr == 9'h0 && W0_mask[7:4] != 4'h0);
	assign uart_div_we = (W0_en && W0_addr == 9'h0) ? W0_mask[3:0] : 4'h0;

	simpleuart uart (
		.clk(W0_clk),
		.resetn(~reset),

		.ser_rx(uart_rx),
		.ser_tx(uart_tx),

		.reg_div_we(uart_div_we),
		.reg_div_di(W0_data[31: 0]),
		.reg_div_do(uart_div_do),

		.reg_dat_we(uart_dat_we),
		.reg_dat_re(R0_en),
		.reg_dat_di(W0_data[63:32]),
		.reg_dat_do(uart_dat_do),
		.reg_dat_wait(uart_dat_wait)
	);

	always @(posedge R0_clk)
		if (R0_en)
			reg_R0_addr <= R0_addr;
	always @(posedge W0_clk)
		if (W0_en && W0_addr == 9'h1 && W0_mask[0])
			reg_led <= W0_data[7:0];
	`ifndef SYNTHESIS
	always @(posedge W0_clk)







		if (uart_dat_we && uart_dat_wait)
			$display("## WARNING: dropping UART data write!");
	`endif

	assign R0_data = (reg_R0_addr == 9'h0) ? {uart_dat_do, uart_div_do} :
			(reg_R0_addr == 9'h1) ? {56'h0, reg_led} : 64'h0;
	assign led = reg_led;
endmodule
module mem_0_ext(
	input         reset,
	input         uart_rx,
	output        uart_tx,
	output [ 7:0] led,

	input         W0_clk,
	input  [ 8:0] W0_addr,
	input         W0_en,
	input  [63:0] W0_data,
	input  [ 7:0] W0_mask,
	input         R0_clk,
	input  [ 8:0] R0_addr,
	input         R0_en,
	output [63:0] R0_data
);

	reg [8:0] reg_R0_addr;
	reg [7:0] reg_led;

	wire        uart_dat_we, uart_dat_wait;
	wire [ 3:0] uart_div_we;
	wire [31:0] uart_dat_do, uart_div_do;

	assign uart_dat_we = (W0_en && W0_addr == 9'h0 && W0_mask[7:4] != 4'h0);
	assign uart_div_we = (W0_en && W0_addr == 9'h0) ? W0_mask[3:0] : 4'h0;

	simpleuart uart (
		.clk(W0_clk),
		.resetn(~reset),

		.ser_rx(uart_rx),
		.ser_tx(uart_tx),

		.reg_div_we(uart_div_we),
		.reg_div_di(W0_data[31: 0]),
		.reg_div_do(uart_div_do),

		.reg_dat_we(uart_dat_we),
		.reg_dat_re(R0_en),
		.reg_dat_di(W0_data[63:32]),
		.reg_dat_do(uart_dat_do),
		.reg_dat_wait(uart_dat_wait)
	);

	always @(posedge R0_clk)
		if (R0_en)
			reg_R0_addr <= R0_addr;
	always @(posedge W0_clk)
		if (W0_en && W0_addr == 9'h1 && W0_mask[0])
			reg_led <= W0_data[7:0];
	`ifndef SYNTHESIS
	always @(posedge W0_clk)







		if (uart_dat_we && uart_dat_wait)
			$display("## WARNING: dropping UART data write!");
	`endif

	assign R0_data = (reg_R0_addr == 9'h0) ? {uart_dat_do, uart_div_do} :
			(reg_R0_addr == 9'h1) ? {56'h0, reg_led} : 64'h0;
	assign led = reg_led;
endmodule