data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/fifo2wave.v
1: b"%Error: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/fifo2wave.v:207: Cannot find file containing module: 'sine_table'\nsine_table t0(.idx_in(i_idx), .out(i_out));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog,data/full_repos/permissive/122125962/sine_table\n             data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog,data/full_repos/permissive/122125962/sine_table.v\n             data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog,data/full_repos/permissive/122125962/sine_table.sv\n             sine_table\n             sine_table.v\n             sine_table.sv\n             obj_dir/sine_table\n             obj_dir/sine_table.v\n             obj_dir/sine_table.sv\n%Error: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/fifo2wave.v:208: Cannot find file containing module: 'sine_table'\nsine_table t1(.idx_in(q_idx), .out(q_out));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/fifo2wave.v:209: Cannot find file containing module: 'chip_table'\nchip_table seq0(.in(fifo_din), .out(chip_seq));\n^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module fifo2wave(	HCLK, HRESETn,
					data_out, half_clk_out, fire, tx_cpl, fifo_din, fifo_RE, fifo_empty, stop_cnt);



parameter SMP_PER_CHIP = 48;

parameter HALF_CYCLE_DELAY = 24;


input			HCLK, HRESETn;
input			fire;
input	[3:0]	fifo_din;
input			fifo_empty;
output			fifo_RE;
output			tx_cpl;
output	[7:0]	data_out;
output			half_clk_out;
output			stop_cnt;





reg		[5:0]	counter, next_counter; 
wire	[31:0]	chip_seq;
reg		[4:0]	bit_pos, next_bit_pos;
reg		[7:0]	data_out_reg;
wire	[7:0]	next_data_out;
reg				half_clk_out_reg;
reg				q_buf, next_q_buf;
reg		[5:0]	i_idx, q_idx, next_i_idx, next_q_idx;
wire	[7:0]	i_out, q_out;
wire			i_bit, q_bit;
reg				stop_cnt, next_stop_cnt;
reg				tx_complete, next_tx_cpl;
reg				ready_to_go;


reg				fifo_RE, next_fifo_RE;



assign data_out = data_out_reg;
assign next_data_out = (stop_cnt==1)? 8'h80 : (counter[0]==0)? q_out : i_out;
assign half_clk_out = half_clk_out_reg;
assign i_bit = ((chip_seq & (1<<bit_pos))>0)? 1 : 0;
assign q_bit = ((chip_seq & (1<<(bit_pos-1)))>0)? 1 : 0;
assign tx_cpl = tx_complete;

always @ (posedge HCLK)
begin
	if (~HRESETn)
	begin
		fifo_RE			<= 0;
		counter			<= 0;
		bit_pos			<= 31;
		half_clk_out_reg<= 0;
		q_buf			<= 0;
		i_idx			<= 0;
		q_idx			<= 0;
		data_out_reg	<= 0;
		stop_cnt		<= 1;
	end
	else
	begin
		fifo_RE			<= next_fifo_RE;
		counter			<= next_counter;
		bit_pos			<= next_bit_pos;
		half_clk_out_reg<= ~half_clk_out_reg;
		q_buf			<= next_q_buf;
		i_idx			<= next_i_idx;
		q_idx			<= next_q_idx;
		data_out_reg	<= next_data_out;
		stop_cnt		<= next_stop_cnt;
	end
end

always @ (posedge HCLK)
begin
	if (~HRESETn)
	begin
		ready_to_go		<= 0;
		tx_complete		<= 0;
	end
	else
	begin
		tx_complete		<= next_tx_cpl;
		if (fire)
			ready_to_go		<= 1;
		else
			ready_to_go		<= 0;
	end
end


always @ (*)
begin
	next_bit_pos	= bit_pos;
	next_fifo_RE	= 0;
	next_q_buf		= q_buf;
	next_i_idx		= i_idx;
	next_q_idx		= q_idx;
	next_counter	= counter;
	next_stop_cnt	= stop_cnt;
	next_tx_cpl		= 0;


	if ((fifo_empty==1)&&(bit_pos==1)&&(counter==(SMP_PER_CHIP-1)))
	begin
		next_stop_cnt = 1;
		next_tx_cpl = 1;
	end


	if ((stop_cnt==1)&&(fifo_empty==0)&&(half_clk_out_reg==0)&&(ready_to_go==1))
	begin
		next_counter = (SMP_PER_CHIP - 3);
		next_stop_cnt = 0;
	end

	if (stop_cnt==0)
	begin
		if (counter<(SMP_PER_CHIP-1))
			next_counter = counter + 1;
		else
			next_counter = 0;
	end
	

	if (counter==(SMP_PER_CHIP-3))
	begin
		if ((bit_pos==1) && (fifo_empty==0))
		begin
			next_fifo_RE = 1;
			next_bit_pos = 31;
		end
		else
			next_bit_pos = bit_pos - 2;
	end
	
	if (counter==(HALF_CYCLE_DELAY-1))
		next_q_buf = q_bit;

	if (counter==HALF_CYCLE_DELAY)
	begin
		if (q_buf==1)
			next_q_idx = 0;
		else
			next_q_idx = HALF_CYCLE_DELAY;
	end
	else if (counter==(SMP_PER_CHIP-1))
	begin
		if (i_bit==1)
			next_i_idx = 0;
		else
			next_i_idx = HALF_CYCLE_DELAY;
	end
	else
	begin

		if (counter[0]==0)
			next_q_idx = q_idx + 1;

		else
			next_i_idx = i_idx + 1;
	end
		
end

sine_table	t0(.idx_in(i_idx), .out(i_out));
sine_table	t1(.idx_in(q_idx), .out(q_out));
chip_table	seq0(.in(fifo_din), .out(chip_seq));

endmodule
module fifo2wave(	HCLK, HRESETn,
					data_out, half_clk_out, fire, tx_cpl, fifo_din, fifo_RE, fifo_empty, stop_cnt);




parameter SMP_PER_CHIP = 48;

parameter HALF_CYCLE_DELAY = 24;


input			HCLK, HRESETn;
input			fire;
input	[3:0]	fifo_din;
input			fifo_empty;
output			fifo_RE;
output			tx_cpl;
output	[7:0]	data_out;
output			half_clk_out;
output			stop_cnt;





reg		[5:0]	counter, next_counter; 
wire	[31:0]	chip_seq;
reg		[4:0]	bit_pos, next_bit_pos;
reg		[7:0]	data_out_reg;
wire	[7:0]	next_data_out;
reg				half_clk_out_reg;
reg				q_buf, next_q_buf;
reg		[5:0]	i_idx, q_idx, next_i_idx, next_q_idx;
wire	[7:0]	i_out, q_out;
wire			i_bit, q_bit;
reg				stop_cnt, next_stop_cnt;
reg				tx_complete, next_tx_cpl;
reg				ready_to_go;


reg				fifo_RE, next_fifo_RE;



assign data_out = data_out_reg;
assign next_data_out = (stop_cnt==1)? 8'h80 : (counter[0]==0)? q_out : i_out;
assign half_clk_out = half_clk_out_reg;
assign i_bit = ((chip_seq & (1<<bit_pos))>0)? 1 : 0;
assign q_bit = ((chip_seq & (1<<(bit_pos-1)))>0)? 1 : 0;
assign tx_cpl = tx_complete;

always @ (posedge HCLK)
begin
	if (~HRESETn)
	begin
		fifo_RE			<= 0;
		counter			<= 0;
		bit_pos			<= 31;
		half_clk_out_reg<= 0;
		q_buf			<= 0;
		i_idx			<= 0;
		q_idx			<= 0;
		data_out_reg	<= 0;
		stop_cnt		<= 1;
	end
	else
	begin
		fifo_RE			<= next_fifo_RE;
		counter			<= next_counter;
		bit_pos			<= next_bit_pos;
		half_clk_out_reg<= ~half_clk_out_reg;
		q_buf			<= next_q_buf;
		i_idx			<= next_i_idx;
		q_idx			<= next_q_idx;
		data_out_reg	<= next_data_out;
		stop_cnt		<= next_stop_cnt;
	end
end

always @ (posedge HCLK)
begin
	if (~HRESETn)
	begin
		ready_to_go		<= 0;
		tx_complete		<= 0;
	end
	else
	begin
		tx_complete		<= next_tx_cpl;
		if (fire)
			ready_to_go		<= 1;
		else
			ready_to_go		<= 0;
	end
end


always @ (*)
begin
	next_bit_pos	= bit_pos;
	next_fifo_RE	= 0;
	next_q_buf		= q_buf;
	next_i_idx		= i_idx;
	next_q_idx		= q_idx;
	next_counter	= counter;
	next_stop_cnt	= stop_cnt;
	next_tx_cpl		= 0;


	if ((fifo_empty==1)&&(bit_pos==1)&&(counter==(SMP_PER_CHIP-1)))
	begin
		next_stop_cnt = 1;
		next_tx_cpl = 1;
	end


	if ((stop_cnt==1)&&(fifo_empty==0)&&(half_clk_out_reg==0)&&(ready_to_go==1))
	begin
		next_counter = (SMP_PER_CHIP - 3);
		next_stop_cnt = 0;
	end

	if (stop_cnt==0)
	begin
		if (counter<(SMP_PER_CHIP-1))
			next_counter = counter + 1;
		else
			next_counter = 0;
	end
	

	if (counter==(SMP_PER_CHIP-3))
	begin
		if ((bit_pos==1) && (fifo_empty==0))
		begin
			next_fifo_RE = 1;
			next_bit_pos = 31;
		end
		else
			next_bit_pos = bit_pos - 2;
	end
	
	if (counter==(HALF_CYCLE_DELAY-1))
		next_q_buf = q_bit;

	if (counter==HALF_CYCLE_DELAY)
	begin
		if (q_buf==1)
			next_q_idx = 0;
		else
			next_q_idx = HALF_CYCLE_DELAY;
	end
	else if (counter==(SMP_PER_CHIP-1))
	begin
		if (i_bit==1)
			next_i_idx = 0;
		else
			next_i_idx = HALF_CYCLE_DELAY;
	end
	else
	begin

		if (counter[0]==0)
			next_q_idx = q_idx + 1;

		else
			next_i_idx = i_idx + 1;
	end
		
end

sine_table	t0(.idx_in(i_idx), .out(i_out));
sine_table	t1(.idx_in(q_idx), .out(q_out));
chip_table	seq0(.in(fifo_din), .out(chip_seq));

endmodule