data/full_repos/permissive/143278/ivltests/br_gh315.v
 line:14: before: ">"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh315.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #50  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/br_gh315.v:72: Unsupported: wait statements\n    wait(B === 8\'b11111111);\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh315.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #50  \n    ^\n%Error: data/full_repos/permissive/143278/ivltests/br_gh315.v:90: Unsupported: wait statements\n    wait(B === 8\'b00000000);\n    ^~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

  tri [7:0]A;
  tri [7:0]B;

  tri [7:0]C;

  reg [7:0] Vb=8'b00000000;
  reg [7:0] Va=8'b11111111;

  reg dir;
  reg nOE;

  assign B=Vb;
  assign A=Va;

  hct74245 buf245(.A, .B, .dir, .nOE);

  integer timer;

  reg failed = 0;

  initial begin
    $display("disable output , set dir a->b");
    dir <= 1;
    nOE <= 1;
    Va=8'b11111111;
    Vb=8'bzzzzzzzz;

    #50





    $display("enable output - B will change immediately");

    timer=$time;
    nOE <= 0;
    wait(B === 8'b11111111);
    if ($time - timer < 16) begin
      $display("%6d", $time, " ERROR TOO QUICK - EXPECTED nOE->B = 16ns - BUT TOOK %-d", ($time - timer));
      failed = 1;
    end
    else
      $display("%6d", $time, " OK - TOOK %-d", ($time - timer));


    #50


    $display("change A - B will change immediately (but C is delayed as expected by 100)");

    Va=8'b00000000;

    timer=$time;
    nOE <= 0;
    wait(B === 8'b00000000);
    if ($time - timer < 10) begin
      $display("%6d", $time, " ERROR TOO QUICK - EXPECTED A->B = 10ns - BUT TOOK %-d", ($time - timer));
      failed = 1;
    end
    else
      $display("%6d", $time, " OK - TOOK %-d", ($time - timer));

    if (failed)
      $display("FAILED");
    else
      $display("PASSED");

  end
endmodule
module tb();


  tri [7:0]A;
  tri [7:0]B;

  tri [7:0]C;

  reg [7:0] Vb=8'b00000000;
  reg [7:0] Va=8'b11111111;

  reg dir;
  reg nOE;

  assign B=Vb;
  assign A=Va;

  hct74245 buf245(.A, .B, .dir, .nOE);

  integer timer;

  reg failed = 0;

  initial begin
    $display("disable output , set dir a->b");
    dir <= 1;
    nOE <= 1;
    Va=8'b11111111;
    Vb=8'bzzzzzzzz;

    #50





    $display("enable output - B will change immediately");

    timer=$time;
    nOE <= 0;
    wait(B === 8'b11111111);
    if ($time - timer < 16) begin
      $display("%6d", $time, " ERROR TOO QUICK - EXPECTED nOE->B = 16ns - BUT TOOK %-d", ($time - timer));
      failed = 1;
    end
    else
      $display("%6d", $time, " OK - TOOK %-d", ($time - timer));


    #50


    $display("change A - B will change immediately (but C is delayed as expected by 100)");

    Va=8'b00000000;

    timer=$time;
    nOE <= 0;
    wait(B === 8'b00000000);
    if ($time - timer < 10) begin
      $display("%6d", $time, " ERROR TOO QUICK - EXPECTED A->B = 10ns - BUT TOOK %-d", ($time - timer));
      failed = 1;
    end
    else
      $display("%6d", $time, " OK - TOOK %-d", ($time - timer));

    if (failed)
      $display("FAILED");
    else
      $display("PASSED");

  end
endmodule