data/full_repos/permissive/187199324/stannel/Heap_tb.v
 line:90: before: "begin"
1: b'%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Heap_tb.v:6: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = clk !== 1\'b1;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:12: Define or directive not defined: \'`ADDRESS_BITS\'\n  localparam addrBits = `ADDRESS_BITS;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:12: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam addrBits = `ADDRESS_BITS;\n                                     ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:13: Define or directive not defined: \'`DATA_BITS\'\n  localparam dataBits = `DATA_BITS;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:13: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam dataBits = `DATA_BITS;\n                                  ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:54: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:60: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:66: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:72: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:78: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:85: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:91: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:98: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:105: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:112: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:119: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:127: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:134: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:142: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:146: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("Heap_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:147: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, Heap_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Heap_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n    #3 reset <= 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Heap_tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n    #2 allocTest;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Heap_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n    #2 freeTest;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Heap_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n    #2 alloc1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Heap_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n    #2 alloc2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Heap_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n    #2 free1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Heap_tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n    #2 free2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Heap_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n    #2 allocWhenHeapEndIsAtMax;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Heap_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n    #2 $finish;\n    ^\n%Error: data/full_repos/permissive/187199324/stannel/Heap_tb.v:157: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n'
module Heap_tb();

  reg clk;
  always #1 clk = clk !== 1'b1;


  parameter srcFile = "../programs/hexes/resume_untested.hex";
  parameter dstFile = "zeroes.hex";

  localparam addrBits = `ADDRESS_BITS;
  localparam dataBits = `DATA_BITS;

  reg  [addrBits-1:0] address;
  reg  [dataBits-1:0] dataIn;
  wire [dataBits-1:0] dataOut;
  reg                 readWriteMode;

  IceRam #(.addrBits(addrBits), .dataBits(dataBits), .romFile(srcFile)) heapMemory (
    .clk(clk),
    .address(address),
    .readWriteMode(readWriteMode),
    .dataIn(dataIn),
    .dataOut(dataOut)
  );


  reg reset = 0;
  reg finished;

  reg alloc = 0;
  reg [addrBits-1:0] allocAddress;
  reg free = 0;
  reg [addrBits-1:0] freeAddress;

  Heap #(.addrBits(addrBits), .dataBits(dataBits)) heap0(
    .clk(clk),
    .reset(reset),
    .finished(finished),
    .address(address),
    .readWriteMode(readWriteMode),
    .dataIn(dataIn),
    .dataOut(dataOut),
    .alloc(alloc),
    .allocAddress(allocAddress),
    .free(free),
    .freeAddress(freeAddress)
  );

  task allocTest;
    begin
      alloc <= 1;
      @(posedge finished)
        begin
          alloc       <= 0;
          freeAddress <= allocAddress;
          if (heap0.heapEnd != 1) $error("Should have incremented heap end");
        end
    end
  endtask

  task freeTest;
    begin
      free  <= 1;
      @(posedge finished)
        begin
          free <= 0;
          if (heap0.heapFree != 0) $error("Heap free should be most recently freed address");
          if (heap0.heapEnd != 1) $error("Heap end changed");
        end
    end
  endtask

  task alloc1;
    begin
      alloc <= 1;
      @(posedge finished)
        begin
          alloc <= 0;
          if (allocAddress != 1) $error("Second address to be allocated should be 1");
          if (heap0.heapEnd != 2) $error("Heap end is not 2");
          if (heap0.heapFree != 0) $error("Heap free changed");
        end
    end
  endtask

  task alloc2;
    begin
      alloc <= 1;
      @(posedge finished)
        begin
          alloc <= 0;
          if (allocAddress != 2) $error("Third address to be allocated should be 2");
          if (heap0.heapEnd != 3) $error("Heap end is not 3");
          if (heap0.heapFree != 0) $error("Heap free changed");
        end
    end
  endtask

  task free1;
    begin
      free <= 1;
      freeAddress <= 1;
      @(posedge finished)
        begin
          free <= 0;
          if (heap0.heapFree != 1) $error("Pointer to start of free list should be 1");
          if (heap0.heapEnd != 3) $error("Heap end changed");
          if (heapMemory.ram[1] != 0) $error("1 should point to 0 in free list");
        end
    end
  endtask

  task free2;
    begin
      free <= 1;
      freeAddress <= 2;
      @(posedge finished)
        begin
          free <= 0;
          if (heap0.heapFree != 2) $error("Pointer to start of free list should be 1");
          if (heap0.heapEnd != 3) $error("Heap end changed");
          if (heapMemory.ram[2] != 1) $error("2 should point to 1 in free list");
          if (heapMemory.ram[1] != 0) $error("1 should point to 0 in free list");
        end
    end
  endtask

  task allocWhenHeapEndIsAtMax;
    begin
      heap0.heapEnd <= 8'hFF;
      alloc <= 1;
      @(posedge finished)
        begin
          alloc <= 0;
          if (allocAddress != 2) $error("Should have allocated from head of free list");
          if (heap0.heapFree != 1) $error("Heap free should be 1");
          if (heap0.heapEnd != 8'hFF) $error("Heap end changed");
          if (heapMemory.ram[1] != 0) $error("1 should point to 0 in free list");
        end
    end
  endtask

  initial begin
    $dumpfile("Heap_tb.vcd");
    $dumpvars(0, Heap_tb);
    #3 reset <= 1;
    #2 allocTest;
    #2 freeTest;
    #2 alloc1;
    #2 alloc2;
    #2 free1;
    #2 free2;
    #2 allocWhenHeapEndIsAtMax;
    #2 $finish;
  end
endmodule
module Heap_tb();


  reg clk;
  always #1 clk = clk !== 1'b1;


  parameter srcFile = "../programs/hexes/resume_untested.hex";
  parameter dstFile = "zeroes.hex";

  localparam addrBits = `ADDRESS_BITS;
  localparam dataBits = `DATA_BITS;

  reg  [addrBits-1:0] address;
  reg  [dataBits-1:0] dataIn;
  wire [dataBits-1:0] dataOut;
  reg                 readWriteMode;

  IceRam #(.addrBits(addrBits), .dataBits(dataBits), .romFile(srcFile)) heapMemory (
    .clk(clk),
    .address(address),
    .readWriteMode(readWriteMode),
    .dataIn(dataIn),
    .dataOut(dataOut)
  );


  reg reset = 0;
  reg finished;

  reg alloc = 0;
  reg [addrBits-1:0] allocAddress;
  reg free = 0;
  reg [addrBits-1:0] freeAddress;

  Heap #(.addrBits(addrBits), .dataBits(dataBits)) heap0(
    .clk(clk),
    .reset(reset),
    .finished(finished),
    .address(address),
    .readWriteMode(readWriteMode),
    .dataIn(dataIn),
    .dataOut(dataOut),
    .alloc(alloc),
    .allocAddress(allocAddress),
    .free(free),
    .freeAddress(freeAddress)
  );

  task allocTest;
    begin
      alloc <= 1;
      @(posedge finished)
        begin
          alloc       <= 0;
          freeAddress <= allocAddress;
          if (heap0.heapEnd != 1) $error("Should have incremented heap end");
        end
    end
  endtask

  task freeTest;
    begin
      free  <= 1;
      @(posedge finished)
        begin
          free <= 0;
          if (heap0.heapFree != 0) $error("Heap free should be most recently freed address");
          if (heap0.heapEnd != 1) $error("Heap end changed");
        end
    end
  endtask

  task alloc1;
    begin
      alloc <= 1;
      @(posedge finished)
        begin
          alloc <= 0;
          if (allocAddress != 1) $error("Second address to be allocated should be 1");
          if (heap0.heapEnd != 2) $error("Heap end is not 2");
          if (heap0.heapFree != 0) $error("Heap free changed");
        end
    end
  endtask

  task alloc2;
    begin
      alloc <= 1;
      @(posedge finished)
        begin
          alloc <= 0;
          if (allocAddress != 2) $error("Third address to be allocated should be 2");
          if (heap0.heapEnd != 3) $error("Heap end is not 3");
          if (heap0.heapFree != 0) $error("Heap free changed");
        end
    end
  endtask

  task free1;
    begin
      free <= 1;
      freeAddress <= 1;
      @(posedge finished)
        begin
          free <= 0;
          if (heap0.heapFree != 1) $error("Pointer to start of free list should be 1");
          if (heap0.heapEnd != 3) $error("Heap end changed");
          if (heapMemory.ram[1] != 0) $error("1 should point to 0 in free list");
        end
    end
  endtask

  task free2;
    begin
      free <= 1;
      freeAddress <= 2;
      @(posedge finished)
        begin
          free <= 0;
          if (heap0.heapFree != 2) $error("Pointer to start of free list should be 1");
          if (heap0.heapEnd != 3) $error("Heap end changed");
          if (heapMemory.ram[2] != 1) $error("2 should point to 1 in free list");
          if (heapMemory.ram[1] != 0) $error("1 should point to 0 in free list");
        end
    end
  endtask

  task allocWhenHeapEndIsAtMax;
    begin
      heap0.heapEnd <= 8'hFF;
      alloc <= 1;
      @(posedge finished)
        begin
          alloc <= 0;
          if (allocAddress != 2) $error("Should have allocated from head of free list");
          if (heap0.heapFree != 1) $error("Heap free should be 1");
          if (heap0.heapEnd != 8'hFF) $error("Heap end changed");
          if (heapMemory.ram[1] != 0) $error("1 should point to 0 in free list");
        end
    end
  endtask

  initial begin
    $dumpfile("Heap_tb.vcd");
    $dumpvars(0, Heap_tb);
    #3 reset <= 1;
    #2 allocTest;
    #2 freeTest;
    #2 alloc1;
    #2 alloc2;
    #2 free1;
    #2 free2;
    #2 allocWhenHeapEndIsAtMax;
    #2 $finish;
  end
endmodule