data/full_repos/permissive/210123090/code/fm_xmit.v
 line:91: before: "real"
1: b'%Warning-REALCVT: data/full_repos/permissive/210123090/code/fm_xmit.v:92: Implicit conversion of real to integer\n   localparam [12:0] aTHECENTER = fTHECENTER;\n                                  ^~~~~~~~~~\n                  ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:338: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf0ca)) cmbb( .O(b), .I3(a[1]), .I2(a[0]), .I1(d[1]), .I0(d[0]));\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210123090/code,data/full_repos/permissive/210123090/SB_LUT4\n             data/full_repos/permissive/210123090/code,data/full_repos/permissive/210123090/SB_LUT4.v\n             data/full_repos/permissive/210123090/code,data/full_repos/permissive/210123090/SB_LUT4.sv\n             SB_LUT4\n             SB_LUT4.v\n             SB_LUT4.sv\n             obj_dir/SB_LUT4\n             obj_dir/SB_LUT4.v\n             obj_dir/SB_LUT4.sv\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:339: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hcaf0)) cmbo( .O(o), .I3(a[1]), .I2(b),    .I1(d[3]), .I0(d[2]));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:311: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'h0f00)) cmb_tap0(.O(tap0),.I3(dummy),.I2(clk), .I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:312: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap1(.O(tap1),.I3(dummy),.I2(tap0),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:313: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap2(.O(tap2),.I3(dummy),.I2(tap1),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:314: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap3(.O(tap3),.I3(dummy),.I2(tap2),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:315: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap4(.O(tap4),.I3(dummy),.I2(tap3),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:316: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap5(.O(tap5),.I3(dummy),.I2(tap4),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:317: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap6(.O(tap6),.I3(dummy),.I2(tap5),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:318: Cannot find file containing module: \'SB_LUT4\'\n   SB_LUT4 #(.LUT_INIT(16\'hf000)) cmb_tap7(.O(clk), .I3(dummy),.I2(tap6),.I1(1\'b0),.I0(1\'b0));\n   ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/210123090/code/fm_xmit.v:223: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'cy\' generates 1 bits.\n                                                                       : ... In instance top.i_acc\n      acc[12:7]     <= acc[12:7] + addend[12:7] + cy;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/210123090/code/fm_xmit.v:92: Operator VAR \'aTHECENTER\' expects 13 bits on the Initial value, but Initial value\'s CONST \'32\'hd07\' generates 32 bits.\n                                                                      : ... In instance top\n   localparam [12:0] aTHECENTER = fTHECENTER;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/210123090/code/fm_xmit.v:145: Cannot find file containing module: \'SB_DFF\'\n   SB_DFF r_buffermsb( .Q(buffermsb), .C(clk), .D(msb)); \n   ^~~~~~\n%Error: Exiting due to 11 error(s), 3 warning(s)\n'
module m_phaseaccumulator #
  ( parameter HIGHLEVEL = 1
    )
   (
    input        clk,
    input [12:0] addend,
    output       msb
    );
   reg [12:0]    acc;
   reg           cy;
   always @(posedge clk) begin
      {cy,acc[6:0]} <= acc[ 6:0] + addend[ 6:0];
      acc[12:7]     <= acc[12:7] + addend[12:7] + cy;
   end
   



   assign msb = acc[12];
endmodule
module m_phaseaccumulator #
  ( parameter HIGHLEVEL = 1
    )
   (
    input        clk,
    input [12:0] addend,
    output       msb
    );

   reg [12:0]    acc;
   reg           cy;
   always @(posedge clk) begin
      {cy,acc[6:0]} <= acc[ 6:0] + addend[ 6:0];
      acc[12:7]     <= acc[12:7] + addend[12:7] + cy;
   end
   



   assign msb = acc[12];
endmodule