data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/i2s_output_apb.v
1: b'%Warning-WIDTH: data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/i2s_output_apb.v:98: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'wr_fifo_used\' generates 4 bits.\n                                                                                                 : ... In instance i2s_output_apb\n   sts_reg[12:8] <= wr_fifo_used;\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/i2s_output_apb.v:106: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'rd_fifo_used\' generates 4 bits.\n                                                                                                  : ... In instance i2s_output_apb\n   sts_reg[28:24] <= rd_fifo_used;\n                  ^~\n%Error: data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/i2s_output_apb.v:155: Cannot find file containing module: \'playback_fifo\'\n playback_fifo playback_fifo_inst (\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA,data/full_repos/permissive/182333580/playback_fifo\n             data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA,data/full_repos/permissive/182333580/playback_fifo.v\n             data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA,data/full_repos/permissive/182333580/playback_fifo.sv\n             playback_fifo\n             playback_fifo.v\n             playback_fifo.sv\n             obj_dir/playback_fifo\n             obj_dir/playback_fifo.v\n             obj_dir/playback_fifo.sv\n%Error: data/full_repos/permissive/182333580/software/ip/TERASIC_ALSA/i2s_output_apb.v:170: Cannot find file containing module: \'capture_fifo\'\n capture_fifo capture_fifo_inst (\n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module i2s_output_apb (
	input wire			clk,
	input wire			reset_n,

	input wire	[4:0]	paddr,
	input wire			penable,
	input wire			pwrite,
	input wire 	[31:0]	pwdata,
	input wire			psel,
	output reg	[31:0]	prdata,
	output wire			pready,

	output wire	[63:0]	playback_fifo_data,
	input wire			playback_fifo_read,
	output wire			playback_fifo_empty,
	output wire			playback_fifo_full,
	input wire			playback_fifo_clk,

	output reg			playback_dma_req,
	input wire			playback_dma_ack,
	output wire			playback_dma_enable,

	input wire	[63:0]	capture_fifo_data,
	input wire			capture_fifo_write,
	output wire			capture_fifo_empty,
	output wire			capture_fifo_full,
	input wire			capture_fifo_clk,

	output reg			capture_dma_req,
	input wire			capture_dma_ack,
	output wire			capture_dma_enable
);

	wire			wr_fifo_write;
	wire			wr_fifo_clear;
	reg		[31:0]	wr_fifo_data;
	wire			wr_fifo_empty;
	wire			wr_fifo_full;
	wire	[3:0]	wr_fifo_used;

	wire			rd_fifo_read;
	wire			rd_fifo_clear;
	wire	[31:0]	rd_fifo_data;
	wire			rd_fifo_empty;
	wire			rd_fifo_full;
	wire	[3:0]	rd_fifo_used;

	reg		[31:0]	cmd_reg;
	reg		[31:0]	sts_reg;

	wire			data_sel = psel && (paddr == 0);
	wire			sts_sel = psel && (paddr == 4);
	wire			cmd_sel = psel && (paddr == 8);


	always @(posedge clk or negedge reset_n)
	begin
		if (~reset_n)
		begin
			wr_fifo_data <= 0;
			cmd_reg <= 0;
		end
		else
		begin
			if (data_sel & pwrite & ~penable)
				wr_fifo_data <= pwdata;
			else if (data_sel & ~pwrite & ~penable)
				prdata <= rd_fifo_data;
			else if (sts_sel & ~pwrite & ~penable)
				prdata <= sts_reg;
			else if (cmd_sel & pwrite & penable)
				cmd_reg <= pwdata;
			else if (cmd_sel & ~pwrite & ~penable)
				prdata <= cmd_reg;
			else
			begin
				cmd_reg[0] <= 0;
				cmd_reg[2] <= 0;
			end
		end
	end


	always @(posedge clk or negedge reset_n)
	begin
		if (~reset_n)
		begin
			sts_reg <= 0;
		end
		else
		begin
			sts_reg[0] <= wr_fifo_empty;
			sts_reg[1] <= wr_fifo_full;
			sts_reg[2] <= playback_dma_enable;
			sts_reg[3] <= playback_dma_req;
			sts_reg[4] <= playback_dma_ack;
			sts_reg[7:5] <= 3'b0;
			sts_reg[12:8] <= wr_fifo_used;
			sts_reg[15:13] <= 3'b0;
			sts_reg[16] <= rd_fifo_empty;
			sts_reg[17] <= rd_fifo_full;
			sts_reg[18] <= capture_dma_enable;
			sts_reg[19] <= capture_dma_req;
			sts_reg[20] <= capture_dma_ack;
			sts_reg[23:21] <= 3'b0;
			sts_reg[28:24] <= rd_fifo_used;
			sts_reg[31:29] <= 3'b0;
		end
	end


	always @(posedge clk or negedge reset_n)
	begin
		if (~reset_n)
		begin
			playback_dma_req <= 0;
		end
		else
		begin
			if (playback_dma_ack)
				playback_dma_req <= 0;
			else
				playback_dma_req <= playback_dma_enable & ~wr_fifo_full;
		end
	end


	always @(posedge clk or negedge reset_n)
	begin
		if (~reset_n)
		begin
			capture_dma_req <= 0;
		end
		else
		begin
			if (capture_dma_ack)
				capture_dma_req <= 0;
			else
				capture_dma_req <= capture_dma_enable & ~rd_fifo_empty;
		end
	end


	assign wr_fifo_write = data_sel & pwrite & penable;
	assign wr_fifo_clear = cmd_reg[0];
	assign playback_dma_enable = cmd_reg[1];

	assign rd_fifo_read = data_sel & ~pwrite & penable;
	assign rd_fifo_clear = cmd_reg[2];
	assign capture_dma_enable = cmd_reg[3];


	assign pready = penable;

	playback_fifo	playback_fifo_inst (
		.wrclk		(clk),
		.wrreq		(wr_fifo_write),
		.data		(wr_fifo_data),
		.aclr		(wr_fifo_clear),
		.wrempty	(wr_fifo_empty),
		.wrfull		(wr_fifo_full),
		.wrusedw	(wr_fifo_used),
		.rdclk		(playback_fifo_clk),
		.rdreq		(playback_fifo_read),
		.q			(playback_fifo_data),
		.rdempty	(playback_fifo_empty),
		.rdfull		(playback_fifo_full),
		.rdusedw	()
	);
	capture_fifo	capture_fifo_inst (
		.wrclk			(capture_fifo_clk),
		.wrreq			(capture_fifo_write),
		.data			(capture_fifo_data),
		.aclr			(rd_fifo_clear),
		.wrempty		(capture_fifo_empty),
		.wrfull			(capture_fifo_full),
		.rdclk			(clk),
		.rdreq			(rd_fifo_read),
		.q				(rd_fifo_data),
		.rdempty		(rd_fifo_empty),
		.rdfull			(rd_fifo_full),
		.rdusedw		(rd_fifo_used)
	);

endmodule
module i2s_output_apb (
	input wire			clk,
	input wire			reset_n,

	input wire	[4:0]	paddr,
	input wire			penable,
	input wire			pwrite,
	input wire 	[31:0]	pwdata,
	input wire			psel,
	output reg	[31:0]	prdata,
	output wire			pready,

	output wire	[63:0]	playback_fifo_data,
	input wire			playback_fifo_read,
	output wire			playback_fifo_empty,
	output wire			playback_fifo_full,
	input wire			playback_fifo_clk,

	output reg			playback_dma_req,
	input wire			playback_dma_ack,
	output wire			playback_dma_enable,

	input wire	[63:0]	capture_fifo_data,
	input wire			capture_fifo_write,
	output wire			capture_fifo_empty,
	output wire			capture_fifo_full,
	input wire			capture_fifo_clk,

	output reg			capture_dma_req,
	input wire			capture_dma_ack,
	output wire			capture_dma_enable
);


	wire			wr_fifo_write;
	wire			wr_fifo_clear;
	reg		[31:0]	wr_fifo_data;
	wire			wr_fifo_empty;
	wire			wr_fifo_full;
	wire	[3:0]	wr_fifo_used;

	wire			rd_fifo_read;
	wire			rd_fifo_clear;
	wire	[31:0]	rd_fifo_data;
	wire			rd_fifo_empty;
	wire			rd_fifo_full;
	wire	[3:0]	rd_fifo_used;

	reg		[31:0]	cmd_reg;
	reg		[31:0]	sts_reg;

	wire			data_sel = psel && (paddr == 0);
	wire			sts_sel = psel && (paddr == 4);
	wire			cmd_sel = psel && (paddr == 8);


	always @(posedge clk or negedge reset_n)
	begin
		if (~reset_n)
		begin
			wr_fifo_data <= 0;
			cmd_reg <= 0;
		end
		else
		begin
			if (data_sel & pwrite & ~penable)
				wr_fifo_data <= pwdata;
			else if (data_sel & ~pwrite & ~penable)
				prdata <= rd_fifo_data;
			else if (sts_sel & ~pwrite & ~penable)
				prdata <= sts_reg;
			else if (cmd_sel & pwrite & penable)
				cmd_reg <= pwdata;
			else if (cmd_sel & ~pwrite & ~penable)
				prdata <= cmd_reg;
			else
			begin
				cmd_reg[0] <= 0;
				cmd_reg[2] <= 0;
			end
		end
	end


	always @(posedge clk or negedge reset_n)
	begin
		if (~reset_n)
		begin
			sts_reg <= 0;
		end
		else
		begin
			sts_reg[0] <= wr_fifo_empty;
			sts_reg[1] <= wr_fifo_full;
			sts_reg[2] <= playback_dma_enable;
			sts_reg[3] <= playback_dma_req;
			sts_reg[4] <= playback_dma_ack;
			sts_reg[7:5] <= 3'b0;
			sts_reg[12:8] <= wr_fifo_used;
			sts_reg[15:13] <= 3'b0;
			sts_reg[16] <= rd_fifo_empty;
			sts_reg[17] <= rd_fifo_full;
			sts_reg[18] <= capture_dma_enable;
			sts_reg[19] <= capture_dma_req;
			sts_reg[20] <= capture_dma_ack;
			sts_reg[23:21] <= 3'b0;
			sts_reg[28:24] <= rd_fifo_used;
			sts_reg[31:29] <= 3'b0;
		end
	end


	always @(posedge clk or negedge reset_n)
	begin
		if (~reset_n)
		begin
			playback_dma_req <= 0;
		end
		else
		begin
			if (playback_dma_ack)
				playback_dma_req <= 0;
			else
				playback_dma_req <= playback_dma_enable & ~wr_fifo_full;
		end
	end


	always @(posedge clk or negedge reset_n)
	begin
		if (~reset_n)
		begin
			capture_dma_req <= 0;
		end
		else
		begin
			if (capture_dma_ack)
				capture_dma_req <= 0;
			else
				capture_dma_req <= capture_dma_enable & ~rd_fifo_empty;
		end
	end


	assign wr_fifo_write = data_sel & pwrite & penable;
	assign wr_fifo_clear = cmd_reg[0];
	assign playback_dma_enable = cmd_reg[1];

	assign rd_fifo_read = data_sel & ~pwrite & penable;
	assign rd_fifo_clear = cmd_reg[2];
	assign capture_dma_enable = cmd_reg[3];


	assign pready = penable;

	playback_fifo	playback_fifo_inst (
		.wrclk		(clk),
		.wrreq		(wr_fifo_write),
		.data		(wr_fifo_data),
		.aclr		(wr_fifo_clear),
		.wrempty	(wr_fifo_empty),
		.wrfull		(wr_fifo_full),
		.wrusedw	(wr_fifo_used),
		.rdclk		(playback_fifo_clk),
		.rdreq		(playback_fifo_read),
		.q			(playback_fifo_data),
		.rdempty	(playback_fifo_empty),
		.rdfull		(playback_fifo_full),
		.rdusedw	()
	);
	capture_fifo	capture_fifo_inst (
		.wrclk			(capture_fifo_clk),
		.wrreq			(capture_fifo_write),
		.data			(capture_fifo_data),
		.aclr			(rd_fifo_clear),
		.wrempty		(capture_fifo_empty),
		.wrfull			(capture_fifo_full),
		.rdclk			(clk),
		.rdreq			(rd_fifo_read),
		.q				(rd_fifo_data),
		.rdempty		(rd_fifo_empty),
		.rdfull			(rd_fifo_full),
		.rdusedw		(rd_fifo_used)
	);

endmodule