data/full_repos/permissive/150331006/src/LFSR.v
data/verilator_xmls/f83bbb6b-2859-4a5e-9326-2d28f63eba53.xml
module LFSR(CLK,Q);
	input CLK;
	output [10:0] Q;
	reg [14:0] P;
	
	initial
		P = 15'b111011001001011;
	
	always @(posedge CLK)
		P = {P[13:0], P[14] ^ P[13]};
		
	assign Q = P[14:4];
endmodule
module LFSR(CLK,Q);

	input CLK;
	output [10:0] Q;
	reg [14:0] P;
	
	initial
		P = 15'b111011001001011;
	
	always @(posedge CLK)
		P = {P[13:0], P[14] ^ P[13]};
		
	assign Q = P[14:4];
endmodule