data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v
'utf-8' codec can't decode byte 0xd6 in position 1818: invalid continuation byte
1: b'%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\nalways #(t/2) clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #(t*8)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #(t*2)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #t\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #t\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #(t)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #(t*2000)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #(t)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #(t*2000)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #(t)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #(t*2000)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #(t)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #(t*2000)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #(t)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n #(t*2000)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n #(t)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #(t*2000)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n #(t)\n ^\n%Error: data/full_repos/permissive/141578247/TESTBENCH_simple/INS_top_tb.v:99: Cannot find file containing module: \'INS_top\'\nINS_top u1(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141578247/TESTBENCH_simple,data/full_repos/permissive/141578247/INS_top\n             data/full_repos/permissive/141578247/TESTBENCH_simple,data/full_repos/permissive/141578247/INS_top.v\n             data/full_repos/permissive/141578247/TESTBENCH_simple,data/full_repos/permissive/141578247/INS_top.sv\n             INS_top\n             INS_top.v\n             INS_top.sv\n             obj_dir/INS_top\n             obj_dir/INS_top.v\n             obj_dir/INS_top.sv\n%Error: Exiting due to 1 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module INS_top_tb;

reg clk, rst, in_data_en;
reg [31:0] in_accx, in_accy, in_accz;
reg [31:0] in_gyrox, in_gyroy, in_gyroz;
reg [31:0] in_magx, in_magy, in_magz;

parameter t = 20;

initial begin 
	clk = 1'b1;
	rst = 1'b1;
	in_data_en = 1'b0;
	in_accx = 32'h0;
	in_accy = 32'h0;
	in_accz = 32'h0;
	in_gyrox = 32'h0;
	in_gyroy = 32'h0;
	in_gyroz = 32'h0;
	in_magx = 32'h0;
	in_magy = 32'h0;
	in_magz = 32'h0;
end

always #(t/2) clk = ~clk;

initial begin
	#(t*8)
		rst = 1'b0;
	#(t*2)
		rst = 1'b1;
	#t
		in_accx = 32'h3f800000;
		in_accy = 32'h3f800000;
		in_accz = 32'h3f800000;
		in_gyrox = 32'h3f800000;
		in_gyroy = 32'h3f800000;
		in_gyroz = 32'h3f800000;
		in_magx = 32'h3f800000;
		in_magy = 32'h3f800000;
		in_magz = 32'h3f800000;
	#t
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;
	#(t*2000)
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;	
	#(t*2000)
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;
	#(t*2000)
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;
	#(t*2000)
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;
	#(t*2000)
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;
	#(t*2000)
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;
end


wire [31:0] out_pitch, out_roll, out_yaw;
wire [31:0] c_c11, c_c12, c_c13,
				c_c21, c_c22, c_c23,
				c_c31, c_c32, c_c33;
wire out_INS_finish;

INS_top u1(
	.clk(clk)										,
	.rst(rst)										,
	.in_accx(in_accx)								,
	.in_accy(in_accy)								,
	.in_accz(in_accz)								,
	.in_gyrox(in_gyrox)							,
	.in_gyroy(in_gyroy)							,
	.in_gyroz(in_gyroz)							,
	.in_magx(in_magx)								,
	.in_magy(in_magy)								,
	.in_magz(in_magz)								,
	.in_data_en(in_data_en)						,
	.out_pitch(out_pitch)						,
	.out_roll(out_roll)							,
	.out_yaw(out_yaw)								,
	.c_c11(c_c11)									, 
	.c_c12(c_c12)									, 
	.c_c13(c_c13)									,
	.c_c21(c_c21)									, 
	.c_c22(c_c22)									, 
	.c_c23(c_c23)									,
	.c_c31(c_c31)									, 
	.c_c32(c_c32)									, 
	.c_c33(c_c33)									,
	.out_INS_finish(out_INS_finish)
);



endmodule
module INS_top_tb;


reg clk, rst, in_data_en;
reg [31:0] in_accx, in_accy, in_accz;
reg [31:0] in_gyrox, in_gyroy, in_gyroz;
reg [31:0] in_magx, in_magy, in_magz;

parameter t = 20;

initial begin 
	clk = 1'b1;
	rst = 1'b1;
	in_data_en = 1'b0;
	in_accx = 32'h0;
	in_accy = 32'h0;
	in_accz = 32'h0;
	in_gyrox = 32'h0;
	in_gyroy = 32'h0;
	in_gyroz = 32'h0;
	in_magx = 32'h0;
	in_magy = 32'h0;
	in_magz = 32'h0;
end

always #(t/2) clk = ~clk;

initial begin
	#(t*8)
		rst = 1'b0;
	#(t*2)
		rst = 1'b1;
	#t
		in_accx = 32'h3f800000;
		in_accy = 32'h3f800000;
		in_accz = 32'h3f800000;
		in_gyrox = 32'h3f800000;
		in_gyroy = 32'h3f800000;
		in_gyroz = 32'h3f800000;
		in_magx = 32'h3f800000;
		in_magy = 32'h3f800000;
		in_magz = 32'h3f800000;
	#t
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;
	#(t*2000)
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;	
	#(t*2000)
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;
	#(t*2000)
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;
	#(t*2000)
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;
	#(t*2000)
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;
	#(t*2000)
		in_data_en = 1'b1;
	#(t)
		in_data_en = 1'b0;
end


wire [31:0] out_pitch, out_roll, out_yaw;
wire [31:0] c_c11, c_c12, c_c13,
				c_c21, c_c22, c_c23,
				c_c31, c_c32, c_c33;
wire out_INS_finish;

INS_top u1(
	.clk(clk)										,
	.rst(rst)										,
	.in_accx(in_accx)								,
	.in_accy(in_accy)								,
	.in_accz(in_accz)								,
	.in_gyrox(in_gyrox)							,
	.in_gyroy(in_gyroy)							,
	.in_gyroz(in_gyroz)							,
	.in_magx(in_magx)								,
	.in_magy(in_magy)								,
	.in_magz(in_magz)								,
	.in_data_en(in_data_en)						,
	.out_pitch(out_pitch)						,
	.out_roll(out_roll)							,
	.out_yaw(out_yaw)								,
	.c_c11(c_c11)									, 
	.c_c12(c_c12)									, 
	.c_c13(c_c13)									,
	.c_c21(c_c21)									, 
	.c_c22(c_c22)									, 
	.c_c23(c_c23)									,
	.c_c31(c_c31)									, 
	.c_c32(c_c32)									, 
	.c_c33(c_c33)									,
	.out_INS_finish(out_INS_finish)
);



endmodule