data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_buf_r.v
data/verilator_xmls/25ffe341-bb44-448f-bb21-2e7145baeb20.xml
module stream_buf_r #(
  parameter DataBits = 8)
  ( input                  clk,
    input                  rst,

    input                  in_valid,
    output reg             in_ready,
    input  [DataBits-1:0]  in_data,

    output                 out_valid,
    input                  out_ready,
    output  [DataBits-1:0] out_data
);

  reg [DataBits-1:0] data_r;

  always @(posedge clk) begin


    if (rst) begin
      in_ready <= 1'b1;
    end else begin
      in_ready <= ~out_valid | out_ready;
    end


    if (in_ready & in_valid & ~out_ready) begin
      data_r <= in_data;
    end

  end


  assign out_valid  = ~in_ready | in_valid;


  assign out_data = in_ready ? in_data : data_r;

endmodule
module stream_buf_r #(
  parameter DataBits = 8)
  ( input                  clk,
    input                  rst,

    input                  in_valid,
    output reg             in_ready,
    input  [DataBits-1:0]  in_data,

    output                 out_valid,
    input                  out_ready,
    output  [DataBits-1:0] out_data
);


  reg [DataBits-1:0] data_r;

  always @(posedge clk) begin


    if (rst) begin
      in_ready <= 1'b1;
    end else begin
      in_ready <= ~out_valid | out_ready;
    end


    if (in_ready & in_valid & ~out_ready) begin
      data_r <= in_data;
    end

  end


  assign out_valid  = ~in_ready | in_valid;


  assign out_data = in_ready ? in_data : data_r;

endmodule