data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v
 line:74: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v:61: Unsupported: Ignoring delay on this delayed statement.\n    forever #10 clk = ~clk;  \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v:65: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("VerilogDM-145-234.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v:66: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,Verilog_145_234);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v:68: Unsupported or unknown PLI call: $monitor\n  $monitor ("register 1=%d, register 2=%d, register 3=%d, register 4=%d register 7 = %d", reg1,reg2,reg3,reg4,reg7);  \n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #100;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/108010874/Verilog-145-234/Verilog-145-234.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #2000 $finish;\n  ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Verilog_145_234;  

	reg clk;  
	reg reset;  

	wire [15:0] pc_out;  
	wire [15:0] alu_result,reg1,reg2,reg3,reg4,reg7;  


	VerilogDM_145_234 uut (  
		.clk(clk),   
		.reset(reset),   
		.pc_out(pc_out),   
		.alu_result(alu_result), 
		.reg1(reg1),
		.reg2(reg2),
		.reg3(reg3),  
		.reg4(reg4),
		.reg7(reg7)
	);
	initial begin  
	   clk = 0;  
	   forever #10 clk = ~clk;  
	end  
	initial begin  

		$dumpfile("VerilogDM-145-234.vcd");
		$dumpvars(0,Verilog_145_234);

		$monitor ("register 1=%d, register 2=%d, register 3=%d, register 4=%d register 7 = %d", reg1,reg2,reg3,reg4,reg7);  
		reset = 1;  

		#100;  
		reset = 0;  

		#2000 $finish;
	end  
endmodule
module Verilog_145_234;
  

	reg clk;  
	reg reset;  

	wire [15:0] pc_out;  
	wire [15:0] alu_result,reg1,reg2,reg3,reg4,reg7;  


	VerilogDM_145_234 uut (  
		.clk(clk),   
		.reset(reset),   
		.pc_out(pc_out),   
		.alu_result(alu_result), 
		.reg1(reg1),
		.reg2(reg2),
		.reg3(reg3),  
		.reg4(reg4),
		.reg7(reg7)
	);
	initial begin  
	   clk = 0;  
	   forever #10 clk = ~clk;  
	end  
	initial begin  

		$dumpfile("VerilogDM-145-234.vcd");
		$dumpvars(0,Verilog_145_234);

		$monitor ("register 1=%d, register 2=%d, register 3=%d, register 4=%d register 7 = %d", reg1,reg2,reg3,reg4,reg7);  
		reset = 1;  

		#100;  
		reset = 0;  

		#2000 $finish;
	end  
endmodule