data/full_repos/permissive/143278/ivltests/types1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/types1.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (empty !== 1\'b0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/types1.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (empty !== 1\'b1) begin\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   parameter early_empty=1;

   reg	     re;

   reg	     rc_isEmpty, rc_willBeEmpty;
   wire      empty;

   assign    empty = (early_empty!=0) ?
			        rc_willBeEmpty && re || rc_isEmpty :
			        rc_isEmpty;


   initial begin
      rc_isEmpty <= 1'bx;
      rc_willBeEmpty <= 1'b1;
      re <= 1'b0;
      rc_isEmpty <= 1'b0;

      #1 if (empty !== 1'b0) begin
	 $display("FAILED -- empty == %b (s.b. 0)", empty);
	 $finish;
      end

      rc_isEmpty <= 1;
      #1 if (empty !== 1'b1) begin
	 $display("FAILED -- empty == %b (s.b. 1)", empty);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;


   parameter early_empty=1;

   reg	     re;

   reg	     rc_isEmpty, rc_willBeEmpty;
   wire      empty;

   assign    empty = (early_empty!=0) ?
			        rc_willBeEmpty && re || rc_isEmpty :
			        rc_isEmpty;


   initial begin
      rc_isEmpty <= 1'bx;
      rc_willBeEmpty <= 1'b1;
      re <= 1'b0;
      rc_isEmpty <= 1'b0;

      #1 if (empty !== 1'b0) begin
	 $display("FAILED -- empty == %b (s.b. 0)", empty);
	 $finish;
      end

      rc_isEmpty <= 1;
      #1 if (empty !== 1'b1) begin
	 $display("FAILED -- empty == %b (s.b. 1)", empty);
	 $finish;
      end

      $display("PASSED");
   end
endmodule