data/full_repos/permissive/181665138/verilog/capitolo_v/Elemento_Contatore_Base_3.v
 line:35: before: "=="
1: b'%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/Elemento_Contatore_Base_3.v:35: syntax error, unexpected ==, expecting \')\' or \',\' or or\n    always @(reset_ == 0) #1 OUTR<=\'B00;\n                    ^~\n%Warning-STMTDLY: data/full_repos/permissive/181665138/verilog/capitolo_v/Elemento_Contatore_Base_3.v:36: Unsupported: Ignoring delay on this delayed statement.\n    always @(posedge clock) if (reset_ == 1) #3 OUTR <= a1_a0;\n                                             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module Elemento_Contatore_Base_3(eu, q1_q0, ei, clock, reset_);
    input clock, reset_;
    input ei;
    output eu;
    output [1:0] q1_q0;

    reg [1:0] OUTR;
    assign q=OUTR;

    wire [1:0] a1_a0;

    assign {a1_a0, eu} = ({q1_q0, ei} == 'B000)?'B000:
                         ({q1_q0, ei} == 'B010)?'B010:
                         ({q1_q0, ei} == 'B100)?'B100:
                         ({q1_q0, ei} == 'B001)?'B010:
                         ({q1_q0, ei} == 'B011)?'B100:
                         ({q1_q0, ei} == 'B101)?'B001:
'BXXX;

    always @(reset_ == 0) #1 OUTR<='B00;
    always @(posedge clock) if (reset_ == 1) #3 OUTR <= a1_a0;
endmodule
module Elemento_Contatore_Base_3(eu, q1_q0, ei, clock, reset_);

    input clock, reset_;
    input ei;
    output eu;
    output [1:0] q1_q0;

    reg [1:0] OUTR;
    assign q=OUTR;

    wire [1:0] a1_a0;

    assign {a1_a0, eu} = ({q1_q0, ei} == 'B000)?'B000:
                         ({q1_q0, ei} == 'B010)?'B010:
                         ({q1_q0, ei} == 'B100)?'B100:
                         ({q1_q0, ei} == 'B001)?'B010:
                         ({q1_q0, ei} == 'B011)?'B100:
                         ({q1_q0, ei} == 'B101)?'B001:
'BXXX;

    always @(reset_ == 0) #1 OUTR<='B00;
    always @(posedge clock) if (reset_ == 1) #3 OUTR <= a1_a0;
endmodule