data/full_repos/permissive/192010622/src/rgb.v
 line:45: before: "."
1: b'%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/rgb.v:50: Signal definition not found, creating implicitly: \'clk\'\n   always @(posedge clk)\n                    ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/192010622/src/rgb.v:39: Cannot find file containing module: \'SB_HFOSC\'\n  SB_HFOSC OSC_i (                   \n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/192010622/src,data/full_repos/permissive/192010622/SB_HFOSC\n             data/full_repos/permissive/192010622/src,data/full_repos/permissive/192010622/SB_HFOSC.v\n             data/full_repos/permissive/192010622/src,data/full_repos/permissive/192010622/SB_HFOSC.sv\n             SB_HFOSC\n             SB_HFOSC.v\n             SB_HFOSC.sv\n             obj_dir/SB_HFOSC\n             obj_dir/SB_HFOSC.v\n             obj_dir/SB_HFOSC.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module two_msec (
       input  wire clk,
       input  wire ten_us,
       output reg  two_ms
   );

    reg [9:0] counter;

    always @ (posedge clk)
        if (ten_us)
       begin
            if (counter == 199)
              begin
                two_ms   <= 1'b1;
                counter  <=   'b0;
              end
           else
            counter  <= counter + 10'b1;
          end
        else
            two_ms   <= 1'b0;

   endmodule
module two_msec (
       input  wire clk,
       input  wire ten_us,
       output reg  two_ms
   );


    reg [9:0] counter;

    always @ (posedge clk)
        if (ten_us)
       begin
            if (counter == 199)
              begin
                two_ms   <= 1'b1;
                counter  <=   'b0;
              end
           else
            counter  <= counter + 10'b1;
          end
        else
            two_ms   <= 1'b0;

   endmodule