data/full_repos/permissive/212763527/school_project/14_memory/sources/RAM_sing.v
 line:29: before: "if"
1: b'%Warning-WIDTH: data/full_repos/permissive/212763527/school_project/14_memory/sources/RAM_sing.v:34: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                                                   : ... In instance RAM_sing\n        data_out <= {(WIDTH-1){1\'bx}};\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module RAM_sing #(parameter WIDTH = 8,
                  parameter Sync_Async = 0)
                 (input [WIDTH-1:0] data_in,
                  input [2:0] addr,
                  input clk,
                  input we,
                  output reg [WIDTH-1:0] data_out);

reg [WIDTH-1:0] mem[0:7];



always @(posedge clk) begin
    if (we)
        mem[addr] <= data_in;
end




if (Sync_Async == 0) begin


    always @(posedge clk) begin

        data_out <= {(WIDTH-1){1'bx}};
        if (!we)
            data_out <= mem[addr];

    end

end else begin


    always @(*) begin

        data_out <= {(WIDTH-1){1'bx}};
        if (!we)
            data_out <= mem[addr];

    end
    
end

endmodule
module RAM_sing #(parameter WIDTH = 8,
                  parameter Sync_Async = 0)
                 (input [WIDTH-1:0] data_in,
                  input [2:0] addr,
                  input clk,
                  input we,
                  output reg [WIDTH-1:0] data_out);


reg [WIDTH-1:0] mem[0:7];



always @(posedge clk) begin
    if (we)
        mem[addr] <= data_in;
end




if (Sync_Async == 0) begin


    always @(posedge clk) begin

        data_out <= {(WIDTH-1){1'bx}};
        if (!we)
            data_out <= mem[addr];

    end

end else begin


    always @(*) begin

        data_out <= {(WIDTH-1){1'bx}};
        if (!we)
            data_out <= mem[addr];

    end
    
end

endmodule