data/full_repos/permissive/168753118/rtl/modules/DECODE_UNIT.v
 line:183: before: "exec_uop_reg"
data/verilator_xmls/38505568-dec1-476a-a4f4-6c8368c64e80.xml
module DECODE_UNIT (

  input [6:0] dec_opcode_in,
  input [2:0] dec_funct3_in,
  input [6:0] dec_funct7_in,

  output dec_imm_mux_sel_out,
  output dec_pc_mux_sel_out,
  output dec_rd_write_enable_out,
  output dec_rd_data_sel_out,
  output dec_jump_sel_out,


  output dec_invalid_ins_exception,


  output [3:0] dec_exec_unit_sel_out,
  output [3:0] dec_exec_unit_uop_out

);


















parameter LOAD = 7'b0000011;
parameter OPIMM = 7'b0010011;
parameter AUIPC = 7'b0010111;
parameter STORE = 7'b0100011;
parameter OP = 7'b0110011;
parameter LUI = 7'b0110111;
parameter BRANCH = 7'b1100011;
parameter JALR = 7'b1100111;
parameter JAL = 7'b1101111;
parameter SYSTEM = 7'b1110011;
parameter OPV = 7'b1010111;


parameter INT_EXEC_SEL = 4'b0001;
parameter BRU_EXEC_SEL = 4'b0010;
parameter LSU_EXEC_SEL = 4'b0100;
parameter VEC_EXEC_SEL = 4'b1000;






reg [3:0] exec_sel_reg;
reg [3:0] exec_uop_reg;
reg pc_mux_sel_reg;
reg imm_mux_sel_reg;
reg rd_write_reg;
reg rd_data_sel_reg;
reg jump_sel_reg;
reg invalid_ins;





always@(*) begin


  case(dec_opcode_in)
    LOAD:     invalid_ins = 1'b0;
    STORE:    invalid_ins = 1'b0;
    OPV:      invalid_ins = 1'b0;
    OPIMM:    invalid_ins = 1'b0;
    AUIPC:    invalid_ins = 1'b0;
    OP:       invalid_ins = 1'b0;
    LUI:      invalid_ins = 1'b0;
    BRANCH:   invalid_ins = 1'b0;
    JAL:      invalid_ins = 1'b0;
    JALR:     invalid_ins = 1'b0;
    SYSTEM:   invalid_ins = 1'b0;
    default:  invalid_ins = 1'b1;
  endcase





  case(dec_opcode_in)
    LOAD:     exec_sel_reg = LSU_EXEC_SEL;
    STORE:    exec_sel_reg = LSU_EXEC_SEL;
    OPV:      exec_sel_reg = VEC_EXEC_SEL;
    OPIMM:    exec_sel_reg = INT_EXEC_SEL;
    AUIPC:    exec_sel_reg = INT_EXEC_SEL;
    OP:       exec_sel_reg = INT_EXEC_SEL;
    LUI:      exec_sel_reg = INT_EXEC_SEL;
    BRANCH:   exec_sel_reg = BRU_EXEC_SEL;
    JAL:      exec_sel_reg = INT_EXEC_SEL;
    JALR:     exec_sel_reg = INT_EXEC_SEL;
    SYSTEM:   exec_sel_reg = INT_EXEC_SEL;
    default:  begin
                exec_sel_reg = 4'b0000;

              end
  endcase


  case(dec_opcode_in)

    OP:       begin
                case(dec_funct3_in)
                  3'b000: if (dec_funct7_in == 7'b0000000)
                              exec_uop_reg = 4'b0000;
                          else if (dec_funct7_in == 7'b0100000)
                              exec_uop_reg = 4'b0001;
                  3'b001: exec_uop_reg = 4'b1111;
                  3'b010: exec_uop_reg = 4'b1010;
                  3'b011: exec_uop_reg = 4'b1011;
                  3'b100: exec_uop_reg = 4'b0100;
                  3'b101: if (dec_funct7_in == 7'b0000000)
                            exec_uop_reg = 4'b1110;
                          else
                            exec_uop_reg = 4'b1101;
                  3'b110: exec_uop_reg = 4'b0010;
                  3'b111: exec_uop_reg = 4'b0011;
                endcase
              end


    OPIMM:    case(dec_funct3_in)
                3'b000: exec_uop_reg = 4'b0000;
                3'b001: exec_uop_reg = 4'b1111;
                3'b010: exec_uop_reg = 4'b1010;
                3'b011: exec_uop_reg = 4'b1011;
                3'b100: exec_uop_reg = 4'b0100;
                3'b101: if (dec_funct7_in == 7'b0000000)
                          exec_uop_reg = 4'b1110;
                        else
                          exec_uop_reg = 4'b1101;
                3'b110: exec_uop_reg = 4'b0010;
                3'b111: exec_uop_reg = 4'b0011;
              endcase


    LOAD:     case(dec_funct3_in)
                3'b000:   exec_uop_reg = 4'b0001;
                3'b001:   exec_uop_reg = 4'b0010;
                3'b010:   exec_uop_reg = 4'b0011;
                3'b100:   exec_uop_reg = 4'b0101;
                3'b101:   exec_uop_reg = 4'b0110;
                default:  exec_uop_reg = 4'b0000;
              endcase


    STORE:    case(dec_funct3_in)
                3'b000:   exec_uop_reg = 4'b1001;
                3'b001:   exec_uop_reg = 4'b1010;
                3'b010:   exec_uop_reg = 4'b1100;
                default   exec_uop_reg = 4'b0000;
              endcase


    BRANCH:   case(dec_funct3_in)
                3'b000:   exec_uop_reg = 4'b0000;
                3'b001:   exec_uop_reg = 4'b0001;
                3'b100:   exec_uop_reg = 4'b0010;
                3'b101:   exec_uop_reg = 4'b0011;
                3'b110:   exec_uop_reg = 4'b0110;
                3'b111:   exec_uop_reg = 4'b0111;
                default:  exec_uop_reg = 4'b1111;
              endcase


    JAL:      exec_uop_reg = 4'b1000;


    JALR:     exec_uop_reg = 4'b0000;


    LUI:      exec_uop_reg = 4'b1001;


    AUIPC:    exec_uop_reg = 4'b0000;


    default: exec_uop_reg = 4'b0000;
  endcase



  case(dec_opcode_in)
    AUIPC:    pc_mux_sel_reg = 1'b1;
    JAL:      pc_mux_sel_reg = 1'b1;
    JALR:     pc_mux_sel_reg = 1'b0;
    BRANCH:   pc_mux_sel_reg = 1'b0;
    default:  pc_mux_sel_reg = 1'b0;
  endcase



  case(dec_opcode_in)
    LOAD:     imm_mux_sel_reg = 1'b1;
    STORE:    imm_mux_sel_reg = 1'b1;
    OPIMM:    imm_mux_sel_reg = 1'b1;
    JAL:      imm_mux_sel_reg = 1'b0;
    JALR:     imm_mux_sel_reg = 1'b1;
    AUIPC:    imm_mux_sel_reg = 1'b1;
    LUI:      imm_mux_sel_reg = 1'b1;
    BRANCH:   imm_mux_sel_reg = 1'b0;
    default:  imm_mux_sel_reg = 1'b0;
  endcase



  case (dec_opcode_in)
    LOAD:   rd_write_reg = 1'b1;
    OPV:    rd_write_reg = 1'b1;
    OPIMM:  rd_write_reg = 1'b1;
    AUIPC:  rd_write_reg = 1'b1;
    OP:     rd_write_reg = 1'b1;
    LUI:    rd_write_reg = 1'b1;
    JAL:    rd_write_reg = 1'b1;
    JALR:   rd_write_reg = 1'b1;
    BRANCH: rd_write_reg = 1'b0;
    default:rd_write_reg = 1'b0;
  endcase


  case(dec_opcode_in)
    JAL:    rd_data_sel_reg = 1'b1;
    JALR:   rd_data_sel_reg = 1'b1;
    default: rd_data_sel_reg = 1'b0;
  endcase


  case (dec_opcode_in)
    JALR: jump_sel_reg = 1'b1;
    default: jump_sel_reg = 1'b0;
  endcase

end






assign dec_exec_unit_sel_out = exec_sel_reg;
assign dec_exec_unit_uop_out = exec_uop_reg;


assign dec_pc_mux_sel_out = pc_mux_sel_reg;
assign dec_rd_write_enable_out = rd_write_reg;
assign dec_rd_data_sel_out = rd_data_sel_reg;
assign dec_jump_sel_out = jump_sel_reg;


assign dec_imm_mux_sel_out = imm_mux_sel_reg;


assign dec_invalid_ins_exception = invalid_ins;

endmodule
module DECODE_UNIT (

  input [6:0] dec_opcode_in,
  input [2:0] dec_funct3_in,
  input [6:0] dec_funct7_in,

  output dec_imm_mux_sel_out,
  output dec_pc_mux_sel_out,
  output dec_rd_write_enable_out,
  output dec_rd_data_sel_out,
  output dec_jump_sel_out,


  output dec_invalid_ins_exception,


  output [3:0] dec_exec_unit_sel_out,
  output [3:0] dec_exec_unit_uop_out

);



















parameter LOAD = 7'b0000011;
parameter OPIMM = 7'b0010011;
parameter AUIPC = 7'b0010111;
parameter STORE = 7'b0100011;
parameter OP = 7'b0110011;
parameter LUI = 7'b0110111;
parameter BRANCH = 7'b1100011;
parameter JALR = 7'b1100111;
parameter JAL = 7'b1101111;
parameter SYSTEM = 7'b1110011;
parameter OPV = 7'b1010111;


parameter INT_EXEC_SEL = 4'b0001;
parameter BRU_EXEC_SEL = 4'b0010;
parameter LSU_EXEC_SEL = 4'b0100;
parameter VEC_EXEC_SEL = 4'b1000;






reg [3:0] exec_sel_reg;
reg [3:0] exec_uop_reg;
reg pc_mux_sel_reg;
reg imm_mux_sel_reg;
reg rd_write_reg;
reg rd_data_sel_reg;
reg jump_sel_reg;
reg invalid_ins;





always@(*) begin


  case(dec_opcode_in)
    LOAD:     invalid_ins = 1'b0;
    STORE:    invalid_ins = 1'b0;
    OPV:      invalid_ins = 1'b0;
    OPIMM:    invalid_ins = 1'b0;
    AUIPC:    invalid_ins = 1'b0;
    OP:       invalid_ins = 1'b0;
    LUI:      invalid_ins = 1'b0;
    BRANCH:   invalid_ins = 1'b0;
    JAL:      invalid_ins = 1'b0;
    JALR:     invalid_ins = 1'b0;
    SYSTEM:   invalid_ins = 1'b0;
    default:  invalid_ins = 1'b1;
  endcase





  case(dec_opcode_in)
    LOAD:     exec_sel_reg = LSU_EXEC_SEL;
    STORE:    exec_sel_reg = LSU_EXEC_SEL;
    OPV:      exec_sel_reg = VEC_EXEC_SEL;
    OPIMM:    exec_sel_reg = INT_EXEC_SEL;
    AUIPC:    exec_sel_reg = INT_EXEC_SEL;
    OP:       exec_sel_reg = INT_EXEC_SEL;
    LUI:      exec_sel_reg = INT_EXEC_SEL;
    BRANCH:   exec_sel_reg = BRU_EXEC_SEL;
    JAL:      exec_sel_reg = INT_EXEC_SEL;
    JALR:     exec_sel_reg = INT_EXEC_SEL;
    SYSTEM:   exec_sel_reg = INT_EXEC_SEL;
    default:  begin
                exec_sel_reg = 4'b0000;

              end
  endcase


  case(dec_opcode_in)

    OP:       begin
                case(dec_funct3_in)
                  3'b000: if (dec_funct7_in == 7'b0000000)
                              exec_uop_reg = 4'b0000;
                          else if (dec_funct7_in == 7'b0100000)
                              exec_uop_reg = 4'b0001;
                  3'b001: exec_uop_reg = 4'b1111;
                  3'b010: exec_uop_reg = 4'b1010;
                  3'b011: exec_uop_reg = 4'b1011;
                  3'b100: exec_uop_reg = 4'b0100;
                  3'b101: if (dec_funct7_in == 7'b0000000)
                            exec_uop_reg = 4'b1110;
                          else
                            exec_uop_reg = 4'b1101;
                  3'b110: exec_uop_reg = 4'b0010;
                  3'b111: exec_uop_reg = 4'b0011;
                endcase
              end


    OPIMM:    case(dec_funct3_in)
                3'b000: exec_uop_reg = 4'b0000;
                3'b001: exec_uop_reg = 4'b1111;
                3'b010: exec_uop_reg = 4'b1010;
                3'b011: exec_uop_reg = 4'b1011;
                3'b100: exec_uop_reg = 4'b0100;
                3'b101: if (dec_funct7_in == 7'b0000000)
                          exec_uop_reg = 4'b1110;
                        else
                          exec_uop_reg = 4'b1101;
                3'b110: exec_uop_reg = 4'b0010;
                3'b111: exec_uop_reg = 4'b0011;
              endcase


    LOAD:     case(dec_funct3_in)
                3'b000:   exec_uop_reg = 4'b0001;
                3'b001:   exec_uop_reg = 4'b0010;
                3'b010:   exec_uop_reg = 4'b0011;
                3'b100:   exec_uop_reg = 4'b0101;
                3'b101:   exec_uop_reg = 4'b0110;
                default:  exec_uop_reg = 4'b0000;
              endcase


    STORE:    case(dec_funct3_in)
                3'b000:   exec_uop_reg = 4'b1001;
                3'b001:   exec_uop_reg = 4'b1010;
                3'b010:   exec_uop_reg = 4'b1100;
                default   exec_uop_reg = 4'b0000;
              endcase


    BRANCH:   case(dec_funct3_in)
                3'b000:   exec_uop_reg = 4'b0000;
                3'b001:   exec_uop_reg = 4'b0001;
                3'b100:   exec_uop_reg = 4'b0010;
                3'b101:   exec_uop_reg = 4'b0011;
                3'b110:   exec_uop_reg = 4'b0110;
                3'b111:   exec_uop_reg = 4'b0111;
                default:  exec_uop_reg = 4'b1111;
              endcase


    JAL:      exec_uop_reg = 4'b1000;


    JALR:     exec_uop_reg = 4'b0000;


    LUI:      exec_uop_reg = 4'b1001;


    AUIPC:    exec_uop_reg = 4'b0000;


    default: exec_uop_reg = 4'b0000;
  endcase



  case(dec_opcode_in)
    AUIPC:    pc_mux_sel_reg = 1'b1;
    JAL:      pc_mux_sel_reg = 1'b1;
    JALR:     pc_mux_sel_reg = 1'b0;
    BRANCH:   pc_mux_sel_reg = 1'b0;
    default:  pc_mux_sel_reg = 1'b0;
  endcase



  case(dec_opcode_in)
    LOAD:     imm_mux_sel_reg = 1'b1;
    STORE:    imm_mux_sel_reg = 1'b1;
    OPIMM:    imm_mux_sel_reg = 1'b1;
    JAL:      imm_mux_sel_reg = 1'b0;
    JALR:     imm_mux_sel_reg = 1'b1;
    AUIPC:    imm_mux_sel_reg = 1'b1;
    LUI:      imm_mux_sel_reg = 1'b1;
    BRANCH:   imm_mux_sel_reg = 1'b0;
    default:  imm_mux_sel_reg = 1'b0;
  endcase



  case (dec_opcode_in)
    LOAD:   rd_write_reg = 1'b1;
    OPV:    rd_write_reg = 1'b1;
    OPIMM:  rd_write_reg = 1'b1;
    AUIPC:  rd_write_reg = 1'b1;
    OP:     rd_write_reg = 1'b1;
    LUI:    rd_write_reg = 1'b1;
    JAL:    rd_write_reg = 1'b1;
    JALR:   rd_write_reg = 1'b1;
    BRANCH: rd_write_reg = 1'b0;
    default:rd_write_reg = 1'b0;
  endcase


  case(dec_opcode_in)
    JAL:    rd_data_sel_reg = 1'b1;
    JALR:   rd_data_sel_reg = 1'b1;
    default: rd_data_sel_reg = 1'b0;
  endcase


  case (dec_opcode_in)
    JALR: jump_sel_reg = 1'b1;
    default: jump_sel_reg = 1'b0;
  endcase

end






assign dec_exec_unit_sel_out = exec_sel_reg;
assign dec_exec_unit_uop_out = exec_uop_reg;


assign dec_pc_mux_sel_out = pc_mux_sel_reg;
assign dec_rd_write_enable_out = rd_write_reg;
assign dec_rd_data_sel_out = rd_data_sel_reg;
assign dec_jump_sel_out = jump_sel_reg;


assign dec_imm_mux_sel_out = imm_mux_sel_reg;


assign dec_invalid_ins_exception = invalid_ins;

endmodule