data/full_repos/permissive/199632300/HDLBits/Verification/sim/Bug/bugs_nand3.v
1: b"%Error: data/full_repos/permissive/199632300/HDLBits/Verification/sim/Bug/bugs_nand3.v:3: Cannot find file containing module: 'andgate'\n    andgate inst1 ( q,a,b,c,1,1 );\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/199632300/HDLBits/Verification/sim/Bug,data/full_repos/permissive/199632300/andgate\n             data/full_repos/permissive/199632300/HDLBits/Verification/sim/Bug,data/full_repos/permissive/199632300/andgate.v\n             data/full_repos/permissive/199632300/HDLBits/Verification/sim/Bug,data/full_repos/permissive/199632300/andgate.sv\n             andgate\n             andgate.v\n             andgate.sv\n             obj_dir/andgate\n             obj_dir/andgate.v\n             obj_dir/andgate.sv\n%Error: Exiting due to 1 error(s)\n"
module top_module (input a, input b, input c, output out);
	reg q;
    andgate inst1 ( q,a,b,c,1,1 );
	assign out = !q;
endmodule
module top_module (input a, input b, input c, output out);

	reg q;
    andgate inst1 ( q,a,b,c,1,1 );
	assign out = !q;
endmodule