data/full_repos/permissive/124844461/Lab1/pc.v
 line:34: before: "/"
data/verilator_xmls/30c06b5a-913d-4f6c-8737-6b84bf00c965.xml
module pc
 #(parameter DATA_WIDTH = 32)
 (
 	input clk,
 	input rst,
 	input en,
 	input [DATA_WIDTH-1:0] din,
 	output reg [DATA_WIDTH-1:0] dout
 );
	 initial begin
		dout={DATA_WIDTH{1'b0}};
	 end

 	always@ (posedge clk) begin
 		if(rst) begin
 			dout <= 0;
 		end else if (en) begin
 			dout <= din;
 		end else begin
 			dout <= dout;
 		end
 	end
 endmodule
module pc
 #(parameter DATA_WIDTH = 32)
 (
 	input clk,
 	input rst,
 	input en,
 	input [DATA_WIDTH-1:0] din,
 	output reg [DATA_WIDTH-1:0] dout
 );

	 initial begin
		dout={DATA_WIDTH{1'b0}};
	 end

 	always@ (posedge clk) begin
 		if(rst) begin
 			dout <= 0;
 		end else if (en) begin
 			dout <= din;
 		end else begin
 			dout <= dout;
 		end
 	end
 endmodule