data/full_repos/permissive/217768747/reduction_tb.v
 line:20: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/217768747/reduction_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/217768747/reduction_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/217768747/reduction_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/217768747/reduction_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #10000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/217768747/reduction_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/217768747/reduction_tb.v:11: Cannot find file containing module: \'Single_Reduction\'\nSingle_Reduction DUT(.sum(sum),.page_rank(page_rank),.out_deg(out_deg),.clk(clk),.new_sum(new_sum),.done(done));\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/Single_Reduction\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/Single_Reduction.v\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/Single_Reduction.sv\n             Single_Reduction\n             Single_Reduction.v\n             Single_Reduction.sv\n             obj_dir/Single_Reduction\n             obj_dir/Single_Reduction.v\n             obj_dir/Single_Reduction.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Single_Reduction_tb;

reg [31:0] sum;
reg [31:0] page_rank;
reg [31:0] out_deg;
reg clk;
reg reset;
wire [31:0] new_sum;
wire done;

Single_Reduction DUT(.sum(sum),.page_rank(page_rank),.out_deg(out_deg),.clk(clk),.new_sum(new_sum),.done(done));
initial begin
	reset<=1;
	clk<=1;

	page_rank<=32'b110;
	out_deg<=32'b10;
	sum<=32'b110;
	#20
	$display("%d",page_rank);
	$display("%d",out_deg);
	$display("%d",sum);
	$display("%d",new_sum);
	$display("%d",done);


	page_rank<=32'b110;
	out_deg<=32'b10;
	sum<=32'b10;
	#20
	$display("%d",page_rank);
	$display("%d",out_deg);
	$display("%d",sum);
	$display("%d",new_sum);
	$display("%d",done);


	page_rank<=32'b11111;
	out_deg<=32'b1;
	sum<=32'b1111101000;
	#100
	$display("%d",page_rank);
	$display("%d",out_deg);
	$display("%d",sum);
	$display("%d",new_sum);
	$display("%d",done);

	page_rank<=32'b101010111101011101110;
	out_deg<=32'b110101101;
	sum<=32'b1101011111111110101;
	#10000
	$display("%d",page_rank);
	$display("%d",out_deg);
	$display("%d",sum);
	$display("%d",new_sum);
	$display("%d",done);


	$finish;
end

always #1 clk=~clk;

endmodule
module Single_Reduction_tb;


reg [31:0] sum;
reg [31:0] page_rank;
reg [31:0] out_deg;
reg clk;
reg reset;
wire [31:0] new_sum;
wire done;

Single_Reduction DUT(.sum(sum),.page_rank(page_rank),.out_deg(out_deg),.clk(clk),.new_sum(new_sum),.done(done));
initial begin
	reset<=1;
	clk<=1;

	page_rank<=32'b110;
	out_deg<=32'b10;
	sum<=32'b110;
	#20
	$display("%d",page_rank);
	$display("%d",out_deg);
	$display("%d",sum);
	$display("%d",new_sum);
	$display("%d",done);


	page_rank<=32'b110;
	out_deg<=32'b10;
	sum<=32'b10;
	#20
	$display("%d",page_rank);
	$display("%d",out_deg);
	$display("%d",sum);
	$display("%d",new_sum);
	$display("%d",done);


	page_rank<=32'b11111;
	out_deg<=32'b1;
	sum<=32'b1111101000;
	#100
	$display("%d",page_rank);
	$display("%d",out_deg);
	$display("%d",sum);
	$display("%d",new_sum);
	$display("%d",done);

	page_rank<=32'b101010111101011101110;
	out_deg<=32'b110101101;
	sum<=32'b1101011111111110101;
	#10000
	$display("%d",page_rank);
	$display("%d",out_deg);
	$display("%d",sum);
	$display("%d",new_sum);
	$display("%d",done);


	$finish;
end

always #1 clk=~clk;

endmodule