data/full_repos/permissive/150482260/reg_file_32x32.v
 line:95: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #10 clear = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:57: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clock = ~clock;\n                ^\n%Error: data/full_repos/permissive/150482260/reg_file_32x32.v:61: Unsupported or unknown PLI call: $monitor\n        $monitor({\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #10 read_index1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #10 read_index1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #10 read_index1 = 7;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #10 read_index1 = 4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150482260/reg_file_32x32.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reg_file_32x32_tb;
    reg clear, clock, write1, write2;
    reg [4:0] read_index1, write_index1, write_index2;
    reg [31:0] write_data1, write_data2;
    wire [31:0] read_value;

    reg_file_32x32 uut (
        .clear(clear),
        .clock(clock),
        .read_index1(read_index1),
        .write1(write1),
        .write_index1(write_index1),
        .write_data1(write_data1),
        .write2(write2),
        .write_index2(write_index2),
        .write_data2(write_data2),
        .read_value(read_value)
    );

    initial begin
        clear = 1;
        #10 clear = 0;
    end

    initial begin
        clock = 1;
        forever #5 clock = ~clock;
    end

    initial begin
        $monitor({
            "%d clock=%b clear=%b\n",
            {21{" "}}, "read_index1=%0d -> read_value=%0d\n",
            {21{" "}}, "write1=%b, write_index1=%0d, write_data1=%0d\n",
            {21{" "}}, "write2=%b, write_index2=%0d, write_data2=%0d"
        }, $time, clock, clear, read_index1, read_value, write1, write_index1, write_data1, write2, write_index2, write_data2);

        #10 read_index1 = 0;
            write1 = 0;
            write_index1 = 0;
            write_data1 = 0;
            write2 = 0;
            write_index2 = 0;
            write_data2 = 0;

        #10 read_index1 = 1;
            write1 = 1;
            write_index1 = 1;
            write_data1 = 25;

        #10 read_index1 = 7;
            write1 = 0;
            write2 = 1;
            write_index2 = 7;
            write_data2 = 625;

        #10 read_index1 = 4;
            write1 = 1;
            write_index1 = 4;
            write_data1 = 3739;
            write2 = 1;
            write_index2 = 4;
            write_data2 = 4295;

        #10 $finish;
    end
endmodule
module reg_file_32x32_tb;

    reg clear, clock, write1, write2;
    reg [4:0] read_index1, write_index1, write_index2;
    reg [31:0] write_data1, write_data2;
    wire [31:0] read_value;

    reg_file_32x32 uut (
        .clear(clear),
        .clock(clock),
        .read_index1(read_index1),
        .write1(write1),
        .write_index1(write_index1),
        .write_data1(write_data1),
        .write2(write2),
        .write_index2(write_index2),
        .write_data2(write_data2),
        .read_value(read_value)
    );

    initial begin
        clear = 1;
        #10 clear = 0;
    end

    initial begin
        clock = 1;
        forever #5 clock = ~clock;
    end

    initial begin
        $monitor({
            "%d clock=%b clear=%b\n",
            {21{" "}}, "read_index1=%0d -> read_value=%0d\n",
            {21{" "}}, "write1=%b, write_index1=%0d, write_data1=%0d\n",
            {21{" "}}, "write2=%b, write_index2=%0d, write_data2=%0d"
        }, $time, clock, clear, read_index1, read_value, write1, write_index1, write_data1, write2, write_index2, write_data2);

        #10 read_index1 = 0;
            write1 = 0;
            write_index1 = 0;
            write_data1 = 0;
            write2 = 0;
            write_index2 = 0;
            write_data2 = 0;

        #10 read_index1 = 1;
            write1 = 1;
            write_index1 = 1;
            write_data1 = 25;

        #10 read_index1 = 7;
            write1 = 0;
            write2 = 1;
            write_index2 = 7;
            write_data2 = 625;

        #10 read_index1 = 4;
            write1 = 1;
            write_index1 = 4;
            write_data1 = 3739;
            write2 = 1;
            write_index2 = 4;
            write_data2 = 4295;

        #10 $finish;
    end
endmodule