data/full_repos/permissive/131358616/design/perceptron/perceptron_nexys2.v
1: b"%Error: data/full_repos/permissive/131358616/design/perceptron/perceptron_nexys2.v:27: Cannot find file containing module: 'perceptron_top'\nperceptron_top #(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131358616/design/perceptron,data/full_repos/permissive/131358616/perceptron_top\n             data/full_repos/permissive/131358616/design/perceptron,data/full_repos/permissive/131358616/perceptron_top.v\n             data/full_repos/permissive/131358616/design/perceptron,data/full_repos/permissive/131358616/perceptron_top.sv\n             perceptron_top\n             perceptron_top.v\n             perceptron_top.sv\n             obj_dir/perceptron_top\n             obj_dir/perceptron_top.v\n             obj_dir/perceptron_top.sv\n%Error: Exiting due to 1 error(s)\n"
module perceptron_nexys2 (

    input wire BTN0,
    input wire CLK50MHZ,
	
    input wire RS232_RX,
	output wire RS232_TX
);


parameter clock_frequency	= 12000000;
parameter uart_baud_rate	= 9600;

wire rst_n;

assign rst_n = !BTN0;

perceptron_top #(
	.clock_frequency(clock_frequency),
	.uart_baud_rate(uart_baud_rate)
) perceptron_top (
	.rst_n(rst_n),
	.clk(CLK50MHZ),
	.rx(RS232_RX),
	.tx(RS232_TX)
);

endmodule
module perceptron_nexys2 (

    input wire BTN0,
    input wire CLK50MHZ,
	
    input wire RS232_RX,
	output wire RS232_TX
);



parameter clock_frequency	= 12000000;
parameter uart_baud_rate	= 9600;

wire rst_n;

assign rst_n = !BTN0;

perceptron_top #(
	.clock_frequency(clock_frequency),
	.uart_baud_rate(uart_baud_rate)
) perceptron_top (
	.rst_n(rst_n),
	.clk(CLK50MHZ),
	.rx(RS232_RX),
	.tx(RS232_TX)
);

endmodule