data/full_repos/permissive/143278/ivltests/pr990.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr990.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bug();

reg [31:0] x;
wire y;

assign y = x == 0;

initial begin
  $display("y: %b", y);
  x = 0;
  #0;
  $display("y: %b", y);
  if (y === 1'b1)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module bug();


reg [31:0] x;
wire y;

assign y = x == 0;

initial begin
  $display("y: %b", y);
  x = 0;
  #0;
  $display("y: %b", y);
  if (y === 1'b1)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule