data/full_repos/permissive/104269513/pipeline.v
 line:135: before: "integer"
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline.v:410: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline.v:415: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 0;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/104269513/pipeline.v:352: Cell has missing pin: \'op_fifo_sel\'\npipeline PL  (\n         ^~\n%Warning-PINMISSING: data/full_repos/permissive/104269513/pipeline.v:352: Cell has missing pin: \'PL_done\'\npipeline PL  (\n         ^~\n%Error: data/full_repos/permissive/104269513/pipeline.v:145: Cannot find file containing module: \'datapath\'\ndatapath dp  (   \n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.v\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.sv\n             datapath\n             datapath.v\n             datapath.sv\n             obj_dir/datapath\n             obj_dir/datapath.v\n             obj_dir/datapath.sv\n%Error: data/full_repos/permissive/104269513/pipeline.v:191: Cannot find file containing module: \'ALU_ctrl\'\nALU_ctrl EX_ALU (\n^~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline.v:199: Cannot find file containing module: \'control\'\ncontrol ctrl (\n^~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline.v:215: Cannot find file containing module: \'convert_fifo\'\nconvert_fifo fifo_dm  ( \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline.v:393: Cannot find file containing module: \'regfile\'\nregfile op_reg(\n^~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pipeline #(
				parameter MAX_DEPTH = 256,
				parameter ADDR_WIDTH = 8,
				parameter DATA_WIDTH = 64,
				parameter CTRL_WIDTH = DATA_WIDTH/8,
				parameter Number_of_FIFO = 5
				)
				(

				input 	[DATA_WIDTH-1:0]			in_data,
				input 	[CTRL_WIDTH-1:0]			in_ctrl,
				output 	[DATA_WIDTH-1:0]			out_data,
				output 	[CTRL_WIDTH-1:0]			out_ctrl,


				input 								out_rdy,
				input 								in_wr,
				output 								in_rdy,
				output 								out_wr,
				

				input								IorD,
				input	[8:0]						Addr_in,
				input [DATA_WIDTH-1:0]				Data_In,
				

				output	[8:0]						Addr_DM,
				output	[8:0]						Addr_IM,		
				output	[31:0]						Data_out_IM,
				output	[DATA_WIDTH-1:0]			Data_out_DM,
				output 								full,
				output 								empty,			
				output								fifo_busy,			
				output 	[1:0]						packet_count,			
				output 	[ADDR_WIDTH-1:0]			FIFO_RD_addr,
				output 	[ADDR_WIDTH-1:0]			FIFO_WR_addr,
				output	[1:0] 						fifo_state,
				output	[ADDR_WIDTH:0]				DEPTH,
				output	reg							PL_EN,
				output	reg							SW_CTRL,
				output	reg							fifo_rd_en,
				output	reg							fifo_wr_en,
				
				output	[log2(Number_of_FIFO)-1:0]	op_fifo_sel,
				output 	reg							PL_done,
				

				input clk,
				input rst
				);

				




reg PL_EN_next;
reg SW_CTRL_next;
reg R_W_EN,R_W_EN_next;


wire DM_wea;
wire [DATA_WIDTH-1:0] PL_Data_mem_dina, PL_MEM_dout;
wire [ADDR_WIDTH-1:0] PL_Addr_DM;		
reg PL_done_next;
wire PL_done_raw;




wire [63:0] EX_ALU_in1,EX_ALU_in2;


wire [63:0] EX_ALU_out;



wire [3:0] ALUop,EX_ALUop;
wire RegWrite,MemWrite, MemtoReg, Jump, ble, PL_done_ctrl, FW_ld;




reg fifo_rd_en_next;
reg fifo_wr_en_next;


wire [ADDR_WIDTH-1:0] first_word; 
	

wire pckt_rd_wr_next;
reg pckt_rd_wr;


  function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction

   
datapath dp		(
				 .clk(clk),
				 .rst(rst),


				 .pipeline_en(PL_EN),
				 .sw_ctrl(SW_CTRL),
				 .IorD(IorD),
				 .WorR(R_W_EN),
				 .MEM_PL_done(PL_done_raw),
				 

				 .Addr_in(Addr_in),
				 .Data_in(Data_In),
				 .IM_Addr_out(Addr_IM),
				 .DM_Addr_out(Addr_DM),
				 .IM_Data_out(Data_out_IM),
				 .DM_Data_out(Data_out_DM),
				 

				 .Data_mem_wea (DM_wea),
				 .Data_mem_dina (PL_Data_mem_dina),
				 .Data_mem_addr (PL_Addr_DM), 
				 .MEM_Dout(PL_MEM_dout),
				 .first_word(first_word),

				 

				 .EX_ALU_in1(EX_ALU_in1),
				 .EX_ALU_in2(EX_ALU_in2),
				 .EX_ALU_out(EX_ALU_out),
				 .EX_ALUop(EX_ALUop),
				 

				 .RegWrite(RegWrite),
				 .ALUSrc(ALUSrc),
				 .MemWrite(MemWrite),
				 .MemtoReg(MemtoReg),	
				 .Jump(Jump),	
				 .ble(ble),	
				 .imme(imme),
				 .ALUop(ALUop),
				 .PL_done(PL_done_ctrl),
				 .FW_ld (FW_ld)
				);

ALU_ctrl EX_ALU (
				.A(EX_ALU_in1),
				.B(EX_ALU_in2),
				.cmd(EX_ALUop),					
				.psw(),
				.Data_out(EX_ALU_out)
				);
				
control ctrl	(
				.instruction(Data_out_IM),
				.RegWrite(RegWrite),
				.ALUSrc(ALUSrc),
				.MemWrite(MemWrite),
				.MemtoReg(MemtoReg),	
				.Jump(Jump),	
				.ble(ble),	
				.imme(imme), 
				.PL_done(PL_done_ctrl),
				.FW_ld (FW_ld),
				.ALUop(ALUop),
				.Master_reg(op_fifo_sel),
				.mem_sel()
				);				
				
convert_fifo fifo_dm 	(
				.fifo_rd_en(fifo_rd_en), 
				.fifo_wr_en(fifo_wr_en),
				.out_rdy(out_rdy), 
				.in_wr(in_wr),
				.out_wr(out_wr),
				.pckt_rd_wr(pckt_rd_wr_next),
				

				.in_rdy(in_rdy),
				.full(full),
				.empty(empty), 
				.nearly_full(), 
				.nearly_empty(),
				.packet_count(packet_count),
				.first_word(first_word),
				.last_word(),
				.fifo_busy(fifo_busy),
				


				.fifo_data_in(in_data),
				.fifo_data_out(out_data),
				.fifo_ctrl_in(in_ctrl),
				.fifo_ctrl_out(out_ctrl),
				

				.PL_A_DM(PL_Addr_DM),
				.PL_Data_mem_dina(PL_Data_mem_dina),
				.DM_wea(DM_wea),
				.PL_MEM_dout(PL_MEM_dout),
				

				.addrb(FIFO_RD_addr),
				.addra(FIFO_WR_addr),
				.state (fifo_state),
				.DEPTH (DEPTH),
								

				.clk(clk),
				.rst(rst)
				);

				
always @ * 
	begin

		PL_EN_next = 'b0;
		SW_CTRL_next = 'b0;
		R_W_EN_next = 'b1;
		fifo_rd_en_next = 'b0;	
		fifo_wr_en_next = 'b0;
		PL_done_next = PL_done;
									
		if (PL_done_raw & !pckt_rd_wr_next)
			PL_done_next = 1;
		if (PL_done_raw & !pckt_rd_wr_next)
			PL_done_next = 0;
			
		if (PL_done & pckt_rd_wr)
			begin
				fifo_wr_en_next = 'b1;
				PL_done_next = pckt_rd_wr_next;
			end

		if (!PL_done & !pckt_rd_wr)
			begin
				PL_EN_next = 'b1;				
				PL_done_next = PL_done_raw;
			end
			
		if (PL_done & !pckt_rd_wr)
			begin
				fifo_rd_en_next = 'b1;							
			end
	end

always @ (posedge clk, posedge rst)
	begin
		if (rst)
			begin
				PL_EN <= 0;
				SW_CTRL <= 0;
				R_W_EN <= 1;
				fifo_rd_en <= 0;
				fifo_wr_en <= 0;
				PL_done <= 'h1;
				pckt_rd_wr <= 'h1;
			end

		else
			begin
				PL_EN <= PL_EN_next;
				SW_CTRL <= SW_CTRL_next;
				R_W_EN <= R_W_EN_next;
				fifo_rd_en <= fifo_rd_en_next;
				fifo_wr_en <= fifo_wr_en_next;
				PL_done <= PL_done_next;
				pckt_rd_wr <= pckt_rd_wr_next;
			end
	end

endmodule
module pipeline #(
				parameter MAX_DEPTH = 256,
				parameter ADDR_WIDTH = 8,
				parameter DATA_WIDTH = 64,
				parameter CTRL_WIDTH = DATA_WIDTH/8,
				parameter Number_of_FIFO = 5
				)
				(

				input 	[DATA_WIDTH-1:0]			in_data,
				input 	[CTRL_WIDTH-1:0]			in_ctrl,
				output 	[DATA_WIDTH-1:0]			out_data,
				output 	[CTRL_WIDTH-1:0]			out_ctrl,


				input 								out_rdy,
				input 								in_wr,
				output 								in_rdy,
				output 								out_wr,
				

				input								IorD,
				input	[8:0]						Addr_in,
				input [DATA_WIDTH-1:0]				Data_In,
				

				output	[8:0]						Addr_DM,
				output	[8:0]						Addr_IM,		
				output	[31:0]						Data_out_IM,
				output	[DATA_WIDTH-1:0]			Data_out_DM,
				output 								full,
				output 								empty,			
				output								fifo_busy,			
				output 	[1:0]						packet_count,			
				output 	[ADDR_WIDTH-1:0]			FIFO_RD_addr,
				output 	[ADDR_WIDTH-1:0]			FIFO_WR_addr,
				output	[1:0] 						fifo_state,
				output	[ADDR_WIDTH:0]				DEPTH,
				output	reg							PL_EN,
				output	reg							SW_CTRL,
				output	reg							fifo_rd_en,
				output	reg							fifo_wr_en,
				
				output	[log2(Number_of_FIFO)-1:0]	op_fifo_sel,
				output 	reg							PL_done,
				

				input clk,
				input rst
				);


				




reg PL_EN_next;
reg SW_CTRL_next;
reg R_W_EN,R_W_EN_next;


wire DM_wea;
wire [DATA_WIDTH-1:0] PL_Data_mem_dina, PL_MEM_dout;
wire [ADDR_WIDTH-1:0] PL_Addr_DM;		
reg PL_done_next;
wire PL_done_raw;




wire [63:0] EX_ALU_in1,EX_ALU_in2;


wire [63:0] EX_ALU_out;



wire [3:0] ALUop,EX_ALUop;
wire RegWrite,MemWrite, MemtoReg, Jump, ble, PL_done_ctrl, FW_ld;




reg fifo_rd_en_next;
reg fifo_wr_en_next;


wire [ADDR_WIDTH-1:0] first_word; 
	

wire pckt_rd_wr_next;
reg pckt_rd_wr;


  function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction

   
datapath dp		(
				 .clk(clk),
				 .rst(rst),


				 .pipeline_en(PL_EN),
				 .sw_ctrl(SW_CTRL),
				 .IorD(IorD),
				 .WorR(R_W_EN),
				 .MEM_PL_done(PL_done_raw),
				 

				 .Addr_in(Addr_in),
				 .Data_in(Data_In),
				 .IM_Addr_out(Addr_IM),
				 .DM_Addr_out(Addr_DM),
				 .IM_Data_out(Data_out_IM),
				 .DM_Data_out(Data_out_DM),
				 

				 .Data_mem_wea (DM_wea),
				 .Data_mem_dina (PL_Data_mem_dina),
				 .Data_mem_addr (PL_Addr_DM), 
				 .MEM_Dout(PL_MEM_dout),
				 .first_word(first_word),

				 

				 .EX_ALU_in1(EX_ALU_in1),
				 .EX_ALU_in2(EX_ALU_in2),
				 .EX_ALU_out(EX_ALU_out),
				 .EX_ALUop(EX_ALUop),
				 

				 .RegWrite(RegWrite),
				 .ALUSrc(ALUSrc),
				 .MemWrite(MemWrite),
				 .MemtoReg(MemtoReg),	
				 .Jump(Jump),	
				 .ble(ble),	
				 .imme(imme),
				 .ALUop(ALUop),
				 .PL_done(PL_done_ctrl),
				 .FW_ld (FW_ld)
				);

ALU_ctrl EX_ALU (
				.A(EX_ALU_in1),
				.B(EX_ALU_in2),
				.cmd(EX_ALUop),					
				.psw(),
				.Data_out(EX_ALU_out)
				);
				
control ctrl	(
				.instruction(Data_out_IM),
				.RegWrite(RegWrite),
				.ALUSrc(ALUSrc),
				.MemWrite(MemWrite),
				.MemtoReg(MemtoReg),	
				.Jump(Jump),	
				.ble(ble),	
				.imme(imme), 
				.PL_done(PL_done_ctrl),
				.FW_ld (FW_ld),
				.ALUop(ALUop),
				.Master_reg(op_fifo_sel),
				.mem_sel()
				);				
				
convert_fifo fifo_dm 	(
				.fifo_rd_en(fifo_rd_en), 
				.fifo_wr_en(fifo_wr_en),
				.out_rdy(out_rdy), 
				.in_wr(in_wr),
				.out_wr(out_wr),
				.pckt_rd_wr(pckt_rd_wr_next),
				

				.in_rdy(in_rdy),
				.full(full),
				.empty(empty), 
				.nearly_full(), 
				.nearly_empty(),
				.packet_count(packet_count),
				.first_word(first_word),
				.last_word(),
				.fifo_busy(fifo_busy),
				


				.fifo_data_in(in_data),
				.fifo_data_out(out_data),
				.fifo_ctrl_in(in_ctrl),
				.fifo_ctrl_out(out_ctrl),
				

				.PL_A_DM(PL_Addr_DM),
				.PL_Data_mem_dina(PL_Data_mem_dina),
				.DM_wea(DM_wea),
				.PL_MEM_dout(PL_MEM_dout),
				

				.addrb(FIFO_RD_addr),
				.addra(FIFO_WR_addr),
				.state (fifo_state),
				.DEPTH (DEPTH),
								

				.clk(clk),
				.rst(rst)
				);

				
always @ * 
	begin

		PL_EN_next = 'b0;
		SW_CTRL_next = 'b0;
		R_W_EN_next = 'b1;
		fifo_rd_en_next = 'b0;	
		fifo_wr_en_next = 'b0;
		PL_done_next = PL_done;
									
		if (PL_done_raw & !pckt_rd_wr_next)
			PL_done_next = 1;
		if (PL_done_raw & !pckt_rd_wr_next)
			PL_done_next = 0;
			
		if (PL_done & pckt_rd_wr)
			begin
				fifo_wr_en_next = 'b1;
				PL_done_next = pckt_rd_wr_next;
			end

		if (!PL_done & !pckt_rd_wr)
			begin
				PL_EN_next = 'b1;				
				PL_done_next = PL_done_raw;
			end
			
		if (PL_done & !pckt_rd_wr)
			begin
				fifo_rd_en_next = 'b1;							
			end
	end

always @ (posedge clk, posedge rst)
	begin
		if (rst)
			begin
				PL_EN <= 0;
				SW_CTRL <= 0;
				R_W_EN <= 1;
				fifo_rd_en <= 0;
				fifo_wr_en <= 0;
				PL_done <= 'h1;
				pckt_rd_wr <= 'h1;
			end

		else
			begin
				PL_EN <= PL_EN_next;
				SW_CTRL <= SW_CTRL_next;
				R_W_EN <= R_W_EN_next;
				fifo_rd_en <= fifo_rd_en_next;
				fifo_wr_en <= fifo_wr_en_next;
				PL_done <= PL_done_next;
				pckt_rd_wr <= pckt_rd_wr_next;
			end
	end

endmodule