data/full_repos/permissive/197806087/matrix_multiplication/rtl/counter.v
 line:16: before: "dicate"
data/verilator_xmls/7c0923e2-3b84-4cb1-a6c4-8cc78fa5ae14.xml
module counter #(
    parameter MAX_COUNT = 3
) (
    input wire                              clk,
    input wire                              rst,
    output reg [$clog2(MAX_COUNT+1)-1:0]    count,
    output wire                             done
);


assign done = (count == MAX_COUNT);

always @(posedge clk or negedge rst) begin
    if (~rst) begin
        count <= 0;
    end
    else if (done) begin

        count <= 0;
    end
    else begin

        count <= count + 1;
    end
end

endmodule
module counter #(
    parameter MAX_COUNT = 3
) (
    input wire                              clk,
    input wire                              rst,
    output reg [$clog2(MAX_COUNT+1)-1:0]    count,
    output wire                             done
);



assign done = (count == MAX_COUNT);

always @(posedge clk or negedge rst) begin
    if (~rst) begin
        count <= 0;
    end
    else if (done) begin

        count <= 0;
    end
    else begin

        count <= count + 1;
    end
end

endmodule