data/full_repos/permissive/106492436/memory.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:25: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h38\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[0] = 9\'h038;\n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hc\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[1] = 9\'h00C;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:27: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[2] = 9\'h001;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h6\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[3] = 9\'h006;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:29: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h80\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[4] = 9\'h080;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:30: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[5] = 9\'h120;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h148\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[6] = 9\'h148;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:32: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h145\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[7] = 9\'h145;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:33: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h14c\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[8] = 9\'h14C;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:34: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h14c\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[9] = 9\'h14C;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:35: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h14f\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[10] = 9\'h14F;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:36: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[11] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[12] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:38: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[13] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:39: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[14] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:40: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[15] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:41: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[16] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:42: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[17] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:43: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[18] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:44: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[19] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:45: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[20] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:46: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hc0\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[21] = 9\'h0C0;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:47: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[22] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:48: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[23] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:49: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[24] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:50: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[25] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:51: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[26] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:52: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[27] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:53: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[28] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:54: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[29] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:55: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[30] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:56: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[31] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:57: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[32] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:58: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[33] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:59: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[34] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:60: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[35] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:61: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[36] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:62: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[37] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:63: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[38] = 9\'h120;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/106492436/memory.sv:64: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h120\' generates 9 bits.\n                                                                 : ... In instance memory\n   rf[39] = 9\'h120;\n          ^\n%Error: Exiting due to 40 warning(s)\n'
module memory 
#(
  parameter NUM_REGS = 64, 
  parameter SIZE = 32
)(
  input clk,
  input rst,
  input  [5:0]  wr_addr,
  input         wr_en,
  input  [31:0] wr_data,
  input  [5:0]  rd_addr,
  output [31:0] rd_data
);
  
    logic [SIZE-1:0] rf [NUM_REGS-1:0];
  
    integer i;
	 always_ff @ (posedge clk) begin
      if (rst)
			for (i = 0; i < NUM_REGS-1; i = i + 1)
				rf[i] <= 0;
		else if (wr_en) 
        rf[wr_addr] <= wr_data;
		else begin
			rf[0] = 9'h038;
			rf[1] = 9'h00C;
			rf[2] = 9'h001;
			rf[3] = 9'h006;
			rf[4] = 9'h080;
			rf[5] = 9'h120;
			rf[6] = 9'h148;
			rf[7] = 9'h145;
			rf[8] = 9'h14C;
			rf[9] = 9'h14C;
			rf[10] = 9'h14F;
			rf[11] = 9'h120;
			rf[12] = 9'h120;
			rf[13] = 9'h120;
			rf[14] = 9'h120;
			rf[15] = 9'h120;
			rf[16] = 9'h120;
			rf[17] = 9'h120;
			rf[18] = 9'h120;
			rf[19] = 9'h120;
			rf[20] = 9'h120;
			rf[21] = 9'h0C0;
			rf[22] = 9'h120;
			rf[23] = 9'h120;
			rf[24] = 9'h120;
			rf[25] = 9'h120;
			rf[26] = 9'h120;
			rf[27] = 9'h120;
			rf[28] = 9'h120;
			rf[29] = 9'h120;
			rf[30] = 9'h120;
			rf[31] = 9'h120;
			rf[32] = 9'h120;
			rf[33] = 9'h120;
			rf[34] = 9'h120;
			rf[35] = 9'h120;
			rf[36] = 9'h120;
			rf[37] = 9'h120;
			rf[38] = 9'h120;
			rf[39] = 9'h120;
		end
	end
	

    assign rd_data = rf[rd_addr];

endmodule
module memory 
#(
  parameter NUM_REGS = 64, 
  parameter SIZE = 32
)(
  input clk,
  input rst,
  input  [5:0]  wr_addr,
  input         wr_en,
  input  [31:0] wr_data,
  input  [5:0]  rd_addr,
  output [31:0] rd_data
);

  
    logic [SIZE-1:0] rf [NUM_REGS-1:0];
  
    integer i;
	 always_ff @ (posedge clk) begin
      if (rst)
			for (i = 0; i < NUM_REGS-1; i = i + 1)
				rf[i] <= 0;
		else if (wr_en) 
        rf[wr_addr] <= wr_data;
		else begin
			rf[0] = 9'h038;
			rf[1] = 9'h00C;
			rf[2] = 9'h001;
			rf[3] = 9'h006;
			rf[4] = 9'h080;
			rf[5] = 9'h120;
			rf[6] = 9'h148;
			rf[7] = 9'h145;
			rf[8] = 9'h14C;
			rf[9] = 9'h14C;
			rf[10] = 9'h14F;
			rf[11] = 9'h120;
			rf[12] = 9'h120;
			rf[13] = 9'h120;
			rf[14] = 9'h120;
			rf[15] = 9'h120;
			rf[16] = 9'h120;
			rf[17] = 9'h120;
			rf[18] = 9'h120;
			rf[19] = 9'h120;
			rf[20] = 9'h120;
			rf[21] = 9'h0C0;
			rf[22] = 9'h120;
			rf[23] = 9'h120;
			rf[24] = 9'h120;
			rf[25] = 9'h120;
			rf[26] = 9'h120;
			rf[27] = 9'h120;
			rf[28] = 9'h120;
			rf[29] = 9'h120;
			rf[30] = 9'h120;
			rf[31] = 9'h120;
			rf[32] = 9'h120;
			rf[33] = 9'h120;
			rf[34] = 9'h120;
			rf[35] = 9'h120;
			rf[36] = 9'h120;
			rf[37] = 9'h120;
			rf[38] = 9'h120;
			rf[39] = 9'h120;
		end
	end
	

    assign rd_data = rf[rd_addr];

endmodule