data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg/display_7_seg.v
1: b'%Error: data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg/display_7_seg.v:12: Cannot find file containing module: \'decoder_7_seg\'\ndecoder_7_seg decoder(.CLK (CLK), .SEG (SEG), .D (digit_data));   \n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg,data/full_repos/permissive/198548420/decoder_7_seg\n             data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg,data/full_repos/permissive/198548420/decoder_7_seg.v\n             data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg,data/full_repos/permissive/198548420/decoder_7_seg.sv\n             decoder_7_seg\n             decoder_7_seg.v\n             decoder_7_seg.sv\n             obj_dir/decoder_7_seg\n             obj_dir/decoder_7_seg.v\n             obj_dir/decoder_7_seg.sv\n%Warning-WIDTH: data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg/display_7_seg.v:21: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                    : ... In instance display_7_seg\n    case ( digit_posn )\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg/display_7_seg.v:21: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h1\' generates 3 bits.\n                                                                                                    : ... In instance display_7_seg\n    case ( digit_posn )\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg/display_7_seg.v:21: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h2\' generates 3 bits.\n                                                                                                    : ... In instance display_7_seg\n    case ( digit_posn )\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg/display_7_seg.v:21: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h3\' generates 3 bits.\n                                                                                                    : ... In instance display_7_seg\n    case ( digit_posn )\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg/display_7_seg.v:21: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                                    : ... In instance display_7_seg\n    case ( digit_posn )\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg/display_7_seg.v:21: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                                    : ... In instance display_7_seg\n    case ( digit_posn )\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg/display_7_seg.v:21: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                                    : ... In instance display_7_seg\n    case ( digit_posn )\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/198548420/nexys4ddr/ch05_counter_7_seg/display_7_seg.v:21: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                                    : ... In instance display_7_seg\n    case ( digit_posn )\n    ^~~~\n%Error: Exiting due to 1 error(s), 8 warning(s)\n'
module display_7_seg(
    input CLK,
    input [11:0] digits,
    output [7:0] SEG,
    output reg [7:0] DIGIT
    );
	 
reg [3:0] digit_data;
reg [3:0] digit_posn;
reg [23:0] prescaler;
	 
decoder_7_seg decoder(.CLK (CLK), .SEG	(SEG), .D (digit_data));   

always @(posedge CLK)
begin
  prescaler <= prescaler + 24'd1;
  if (prescaler == 24'd50000)
  begin
    prescaler <= 0;
    digit_posn <= digit_posn + 3'd1;
    case ( digit_posn )
      3'b000 : begin
        digit_data <= digits[3:0];
        DIGIT <= 8'b11111110;
      end
      3'b001 : begin
        digit_data <= digits[7:4];
        DIGIT <= 8'b11111101;
      end
      3'b010 : begin
        digit_data <= digits[11:8];
        DIGIT <= 8'b11111011;
      end
      3'b011 : begin
        digit_data <= digits[11:8];
        DIGIT <= 8'b11110111;
      end
      3'b100 : begin
        digit_data <= digits[11:8];
        DIGIT <= 8'b11101111;
      end
      3'b101 : begin
        digit_data <= digits[11:8];
        DIGIT <= 8'b11011111;
      end
      3'b110 : begin
        digit_data <= digits[11:8];
        DIGIT <= 8'b10111111;
      end
      3'b111 : begin
        digit_data <= digits[11:8];
        DIGIT <= 8'b01111111;
        digit_posn <= 0;
      end
      default: begin
      
      end
    endcase
  end
end
endmodule
module display_7_seg(
    input CLK,
    input [11:0] digits,
    output [7:0] SEG,
    output reg [7:0] DIGIT
    );

	 
reg [3:0] digit_data;
reg [3:0] digit_posn;
reg [23:0] prescaler;
	 
decoder_7_seg decoder(.CLK (CLK), .SEG	(SEG), .D (digit_data));   

always @(posedge CLK)
begin
  prescaler <= prescaler + 24'd1;
  if (prescaler == 24'd50000)
  begin
    prescaler <= 0;
    digit_posn <= digit_posn + 3'd1;
    case ( digit_posn )
      3'b000 : begin
        digit_data <= digits[3:0];
        DIGIT <= 8'b11111110;
      end
      3'b001 : begin
        digit_data <= digits[7:4];
        DIGIT <= 8'b11111101;
      end
      3'b010 : begin
        digit_data <= digits[11:8];
        DIGIT <= 8'b11111011;
      end
      3'b011 : begin
        digit_data <= digits[11:8];
        DIGIT <= 8'b11110111;
      end
      3'b100 : begin
        digit_data <= digits[11:8];
        DIGIT <= 8'b11101111;
      end
      3'b101 : begin
        digit_data <= digits[11:8];
        DIGIT <= 8'b11011111;
      end
      3'b110 : begin
        digit_data <= digits[11:8];
        DIGIT <= 8'b10111111;
      end
      3'b111 : begin
        digit_data <= digits[11:8];
        DIGIT <= 8'b01111111;
        digit_posn <= 0;
      end
      default: begin
      
      end
    endcase
  end
end
endmodule