data/full_repos/permissive/166008742/src/tb_buf_updater.v
 line:94: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_buf_updater.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PER/2);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/166008742/src/tb_buf_updater.v:94: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_buf_updater.v:96: syntax error, unexpected \'@\'\n        repeat (100) @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_buf_updater.v:102: syntax error, unexpected \'@\'\n            while (~buf_updated ) @(posedge clk);\n                                  ^\n%Error: data/full_repos/permissive/166008742/src/tb_buf_updater.v:105: syntax error, unexpected \'@\'\n            repeat (3) @(posedge clk);\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_buf_updater.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_buf_updater ();
    parameter ADDR_WIDTH = 16;
    parameter DATA_WIDTH = 32;
    parameter CLK_PER = 10;

    reg reset;
    reg clk;



    wire [ADDR_WIDTH-1:0] wbm_address;
    wire [DATA_WIDTH-1:0] wbm_writedata;
    wire wbm_strobe;
    wire wbm_cycle;
    wire wbm_write;


    wire wbm_ack;
    wire [DATA_WIDTH-1:0] wbm_readdata;



    reg [DATA_WIDTH-1:0] buf_id;
    reg update_buf;
    wire buf_updated;

    mem #(ADDR_WIDTH, DATA_WIDTH) wb_mem(
        .reset(reset),
        .clk(clk),


        .wbm_address(wbm_address),
        .wbm_writedata(wbm_writedata),
        .wbm_readdata(wbm_readdata),
        .wbm_strobe(wbm_strobe),
        .wbm_cycle(wbm_cycle),
        .wbm_write(wbm_write),
        .wbm_ack(wbm_ack)
    );


    buf_updater #(ADDR_WIDTH, DATA_WIDTH) dut
    (
        .reset(reset),
        .clk(clk),


        .wbm_address(wbm_address),
        .wbm_writedata(wbm_writedata),
        .wbm_readdata(wbm_readdata),
        .wbm_strobe(wbm_strobe),
        .wbm_cycle(wbm_cycle),
        .wbm_write(wbm_write),
        .wbm_ack(wbm_ack),


        .buf_id(buf_id),
        .update_buf(update_buf),
        .buf_updated(buf_updated)
    );




    always begin
        #(CLK_PER/2);
        clk <= ~clk;
    end

    initial begin
        clk <= 0;
        reset <= 1;

        buf_id <= 0;
        update_buf <= 0;

        repeat (100) @(posedge clk);
        reset <= 0;
        repeat (100) @(posedge clk);

        repeat (5) begin
            buf_id <= 0;
            update_buf <= 1;

            while (~buf_updated ) @(posedge clk);
            update_buf <= 0;

            repeat (3) @(posedge clk);

        end
            
        
        #100;
    end

endmodule
module tb_buf_updater ();

    parameter ADDR_WIDTH = 16;
    parameter DATA_WIDTH = 32;
    parameter CLK_PER = 10;

    reg reset;
    reg clk;



    wire [ADDR_WIDTH-1:0] wbm_address;
    wire [DATA_WIDTH-1:0] wbm_writedata;
    wire wbm_strobe;
    wire wbm_cycle;
    wire wbm_write;


    wire wbm_ack;
    wire [DATA_WIDTH-1:0] wbm_readdata;



    reg [DATA_WIDTH-1:0] buf_id;
    reg update_buf;
    wire buf_updated;

    mem #(ADDR_WIDTH, DATA_WIDTH) wb_mem(
        .reset(reset),
        .clk(clk),


        .wbm_address(wbm_address),
        .wbm_writedata(wbm_writedata),
        .wbm_readdata(wbm_readdata),
        .wbm_strobe(wbm_strobe),
        .wbm_cycle(wbm_cycle),
        .wbm_write(wbm_write),
        .wbm_ack(wbm_ack)
    );


    buf_updater #(ADDR_WIDTH, DATA_WIDTH) dut
    (
        .reset(reset),
        .clk(clk),


        .wbm_address(wbm_address),
        .wbm_writedata(wbm_writedata),
        .wbm_readdata(wbm_readdata),
        .wbm_strobe(wbm_strobe),
        .wbm_cycle(wbm_cycle),
        .wbm_write(wbm_write),
        .wbm_ack(wbm_ack),


        .buf_id(buf_id),
        .update_buf(update_buf),
        .buf_updated(buf_updated)
    );




    always begin
        #(CLK_PER/2);
        clk <= ~clk;
    end

    initial begin
        clk <= 0;
        reset <= 1;

        buf_id <= 0;
        update_buf <= 0;

        repeat (100) @(posedge clk);
        reset <= 0;
        repeat (100) @(posedge clk);

        repeat (5) begin
            buf_id <= 0;
            update_buf <= 1;

            while (~buf_updated ) @(posedge clk);
            update_buf <= 0;

            repeat (3) @(posedge clk);

        end
            
        
        #100;
    end

endmodule