data/full_repos/permissive/110151336/lab_09/src/06_counter/pmod_als.v
None: at end of input
1: b'%Error: data/full_repos/permissive/110151336/lab_09/src/06_counter/pmod_als.v:23: Cannot find file containing module: \'register\'\n    register #(.SIZE(CNTSIZE)) r_counter(clk, rst_n, cntNext, cnt);\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110151336/lab_09/src/06_counter,data/full_repos/permissive/110151336/register\n             data/full_repos/permissive/110151336/lab_09/src/06_counter,data/full_repos/permissive/110151336/register.v\n             data/full_repos/permissive/110151336/lab_09/src/06_counter,data/full_repos/permissive/110151336/register.sv\n             register\n             register.v\n             register.sv\n             obj_dir/register\n             obj_dir/register.v\n             obj_dir/register.sv\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_09/src/06_counter/pmod_als.v:32: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'sdo\' generates 1 bits.\n                                                                                        : ... In instance pmod_als\n    wire [7:0] shiftNext = (shift << 1) | sdo;\n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/110151336/lab_09/src/06_counter/pmod_als.v:33: Cannot find file containing module: \'register_we\'\n    register_we #(.SIZE(8)) r_shift(clk, rst_n, sampleBit, shiftNext, shift);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/110151336/lab_09/src/06_counter/pmod_als.v:36: Cannot find file containing module: \'register_we\'\n    register_we #(.SIZE(8))  r_value(clk, rst_n, valueDone, valueNext, value);\n    ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module pmod_als
#(
    parameter CNTSIZE = 11
)
(
    input             clk,
    input             rst_n,
    output            cs,
    output            sck,
    input             sdo,
    output      [7:0] value
);
    wire [ CNTSIZE - 1:0] cnt;
    wire [ CNTSIZE - 1:0] cntNext = cnt + 1;
    register #(.SIZE(CNTSIZE)) r_counter(clk, rst_n, cntNext, cnt);

    assign sck = cnt [3];
    assign cs  = ~(cnt[CNTSIZE - 1:8] == { (CNTSIZE - 8) { 1'b1 }});

    wire sampleBit = ( cs == 1'b0 && cnt [3:0] == 4'b1000     );
    wire valueDone = ( cs == 1'b0 && cnt [7:0] == 8'b10101001 );

    wire [7:0] shift;
    wire [7:0] shiftNext = (shift << 1) | sdo;
    register_we #(.SIZE(8)) r_shift(clk, rst_n, sampleBit, shiftNext, shift);

    wire [7:0] valueNext = shift;
    register_we #(.SIZE(8))  r_value(clk, rst_n, valueDone, valueNext, value);

endmodule
module pmod_als
#(
    parameter CNTSIZE = 11
)
(
    input             clk,
    input             rst_n,
    output            cs,
    output            sck,
    input             sdo,
    output      [7:0] value
);

    wire [ CNTSIZE - 1:0] cnt;
    wire [ CNTSIZE - 1:0] cntNext = cnt + 1;
    register #(.SIZE(CNTSIZE)) r_counter(clk, rst_n, cntNext, cnt);

    assign sck = cnt [3];
    assign cs  = ~(cnt[CNTSIZE - 1:8] == { (CNTSIZE - 8) { 1'b1 }});

    wire sampleBit = ( cs == 1'b0 && cnt [3:0] == 4'b1000     );
    wire valueDone = ( cs == 1'b0 && cnt [7:0] == 8'b10101001 );

    wire [7:0] shift;
    wire [7:0] shiftNext = (shift << 1) | sdo;
    register_we #(.SIZE(8)) r_shift(clk, rst_n, sampleBit, shiftNext, shift);

    wire [7:0] valueNext = shift;
    register_we #(.SIZE(8))  r_value(clk, rst_n, valueDone, valueNext, value);

endmodule