data/full_repos/permissive/170019407/hw3_1/mux2_1_bench.v
 line:19: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/170019407/hw3_1/mux2_1_bench.v:10: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/170019407/hw3_1/mux2_1_bench.v:18: syntax error, unexpected \'@\'\n @(negedge clk)\n ^\n%Error: data/full_repos/permissive/170019407/hw3_1/mux2_1_bench.v:23: syntax error, unexpected \'@\'\n @(negedge clk)\n ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux2_1_bench;
    
    reg A,B,S,clk;
    wire Y;
    
    mux2_1 a1(.InA(A) ,.InB(B), .S(S), .Out(Y));
    


    always #10 clk = ~clk;
    
    initial begin
        A =1'b0;
        B = 1'b0;
	S = 1'b0;
	clk = 1'b0;

	@(negedge clk)
		begin
			A=1'b1;
			S=1'b1;
		end
	@(negedge clk)
			A=1'b0;
	@(negedge clk)
		begin
			B=1'b1;
			S=1'b0;
		end
	@(negedge clk)
			B=1'b0;

    end
    
    always @(Y)
    $display( "time =%0t \tINPUT VALUES: \t InA=%b InB=%b Sel=%b \t output value Y  =%b",$time,A,B,S,Y);
endmodule
module mux2_1_bench;

    
    reg A,B,S,clk;
    wire Y;
    
    mux2_1 a1(.InA(A) ,.InB(B), .S(S), .Out(Y));
    


    always #10 clk = ~clk;
    
    initial begin
        A =1'b0;
        B = 1'b0;
	S = 1'b0;
	clk = 1'b0;

	@(negedge clk)
		begin
			A=1'b1;
			S=1'b1;
		end
	@(negedge clk)
			A=1'b0;
	@(negedge clk)
		begin
			B=1'b1;
			S=1'b0;
		end
	@(negedge clk)
			B=1'b0;

    end
    
    always @(Y)
    $display( "time =%0t \tINPUT VALUES: \t InA=%b InB=%b Sel=%b \t output value Y  =%b",$time,A,B,S,Y);
endmodule