data/full_repos/permissive/173003307/sim/vga_wrapper_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173003307/sim/vga_wrapper_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #10 CLK <= ~CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173003307/sim/vga_wrapper_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #10 RESET = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173003307/sim/vga_wrapper_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #20 RESET = 1\'b0;\n        ^\n%Error: data/full_repos/permissive/173003307/sim/vga_wrapper_tb.v:35: Cannot find file containing module: \'vga_wrapper\'\nvga_wrapper uut(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173003307/sim,data/full_repos/permissive/173003307/vga_wrapper\n             data/full_repos/permissive/173003307/sim,data/full_repos/permissive/173003307/vga_wrapper.v\n             data/full_repos/permissive/173003307/sim,data/full_repos/permissive/173003307/vga_wrapper.sv\n             vga_wrapper\n             vga_wrapper.v\n             vga_wrapper.sv\n             obj_dir/vga_wrapper\n             obj_dir/vga_wrapper.v\n             obj_dir/vga_wrapper.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vga_wrapper_tb(

    );
    
reg CLK;
reg RESET;


wire [7:0] VGA_COLOUR;
wire VGA_HS;
wire VGA_VS;    
    
vga_wrapper uut(
            .CLK(CLK),
            .RESET(RESET),

            .VGA_COLOUR(VGA_COLOUR),
            .VGA_HS(VGA_HS),
            .VGA_VS(VGA_VS)
            );



    initial
        CLK = 0;
        
    always
        #10 CLK <= ~CLK;
    
    initial
    begin

        RESET = 1'b0;
        #10 RESET = 1'b1;
        #20 RESET = 1'b0;
    end

endmodule
module vga_wrapper_tb(

    );

    
reg CLK;
reg RESET;


wire [7:0] VGA_COLOUR;
wire VGA_HS;
wire VGA_VS;    
    
vga_wrapper uut(
            .CLK(CLK),
            .RESET(RESET),

            .VGA_COLOUR(VGA_COLOUR),
            .VGA_HS(VGA_HS),
            .VGA_VS(VGA_VS)
            );



    initial
        CLK = 0;
        
    always
        #10 CLK <= ~CLK;
    
    initial
    begin

        RESET = 1'b0;
        #10 RESET = 1'b1;
        #20 RESET = 1'b0;
    end

endmodule