data/full_repos/permissive/114642806/dev/milestone1/counter.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/114642806/dev/milestone1/counter.v:59: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'counter\'\nmodule counter(CLOCK_50, enable);\n       ^~~~~~~\n                                                                                   : ... Top module \'backup_counter\'\nmodule backup_counter(CLOCK_50, enable_next);\n       ^~~~~~~~~~~~~~\n                                                                                   : ... Top module \'selector\'\nmodule selector(select, clock, enable, count1);\n       ^~~~~~~~\n                                                                                   : ... Top module \'displayHEX\'\nmodule displayHEX (s,h);\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/114642806/dev/milestone1/counter.v:100: Operator GTE expects 28 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                 : ... In instance selector\n   2\'b00: out = (count1 >= 1\'b1)? 1\'b1 : 1\'b0;\n                        ^~\n%Error: Exiting due to 2 warning(s)\n'
module selector(select, clock, enable, count1);
input [1:0] select;
input clock;
input [27:0]count1;
output enable;
reg out = 1'b0;
assign enable = out;
always @(posedge clock)
	begin
		if (out == 1)
			out = 0;
		else
			case (select)
			2'b00: out = (count1 >= 1'b1)? 1'b1 : 1'b0;
			2'b01: out = (count1 >= 28'd50000000)? 1'b1:1'b0;
			2'b10: out = (count1 >= 28'd100000000)? 1'b1:1'b0;
			2'b11: out = (count1 >= 28'd200000000)? 1'b1:1'b0;
			default: out = 1'b0;
			endcase
		end
endmodule
module selector(select, clock, enable, count1);

input [1:0] select;
input clock;
input [27:0]count1;
output enable;
reg out = 1'b0;
assign enable = out;
always @(posedge clock)
	begin
		if (out == 1)
			out = 0;
		else
			case (select)
			2'b00: out = (count1 >= 1'b1)? 1'b1 : 1'b0;
			2'b01: out = (count1 >= 28'd50000000)? 1'b1:1'b0;
			2'b10: out = (count1 >= 28'd100000000)? 1'b1:1'b0;
			2'b11: out = (count1 >= 28'd200000000)? 1'b1:1'b0;
			default: out = 1'b0;
			endcase
		end
endmodule