data/full_repos/permissive/115487336/mycode/Whac-A-Mole/delay.v
data/verilator_xmls/6dcd7cb6-b52c-4355-8f4f-d04bdde14604.xml
module delay(
	input clk,
	input rst_n,
	input [4:0] state,
	output reg [15:0] data,
	output delayover
);

reg [31:0] delaycount;
reg idelayover;

assign delayover=idelayover;

always@(posedge clk or posedge rst_n)
begin
	if(rst_n)
	begin
		delaycount <= 32'b0;
		idelayover <= 0;
		data <= 16'hFFFF;
	end
	else
	begin
		if(delaycount == 32'd0)
			data <= 16'h3FFF;
		else if(delaycount == 32'd1_0000_0000)
			data <= 16'h2FFF;
		else if(delaycount == 32'd2_0000_0000)
			data <= 16'h1FFF;
		else if(delaycount == 32'd3_0000_0000)
			data <= 16'h9AFF;
		else if(delaycount == 32'd4_0000_0000)
			idelayover <= 1;
		else
		begin
		end
		if(~idelayover)
			delaycount <= delaycount + 32'h1;
	end
end
endmodule
module delay(
	input clk,
	input rst_n,
	input [4:0] state,
	output reg [15:0] data,
	output delayover
);


reg [31:0] delaycount;
reg idelayover;

assign delayover=idelayover;

always@(posedge clk or posedge rst_n)
begin
	if(rst_n)
	begin
		delaycount <= 32'b0;
		idelayover <= 0;
		data <= 16'hFFFF;
	end
	else
	begin
		if(delaycount == 32'd0)
			data <= 16'h3FFF;
		else if(delaycount == 32'd1_0000_0000)
			data <= 16'h2FFF;
		else if(delaycount == 32'd2_0000_0000)
			data <= 16'h1FFF;
		else if(delaycount == 32'd3_0000_0000)
			data <= 16'h9AFF;
		else if(delaycount == 32'd4_0000_0000)
			idelayover <= 1;
		else
		begin
		end
		if(~idelayover)
			delaycount <= delaycount + 32'h1;
	end
end
endmodule