data/full_repos/permissive/108500919/proc.v
 line:74: before: "version"
data/verilator_xmls/4b00334f-c464-4a91-8a9c-a50bec7f2c42.xml
module proc(
    input [15:0] x,
    input [15:0] x_init,
    input [15:0] a,
    input reset,
    input clk,
    output[15:0] y
    );
    reg [15:0] cuenta;
    reg [15:0] suma;
    reg [15:0]ym;
    
    assign y = ym;
    always @ (posedge clk )
    begin
        if (reset == 1'b1)			
            cuenta <= 16'h0000;
        else
		begin
        if (cuenta < 16'h0003)
             cuenta <= cuenta + 16'h0001;
        else
        	cuenta <= 16'h0000; 
		end         
	end
	
    
    always @(posedge clk )
    begin
        if (reset == 1'b1)
        	begin
             ym <= x_init;
             suma <= 16'h0000;
        	end
		else
        begin   
        	if (cuenta < 16'h0003)
        		begin
             	ym <= x;
            	 suma <= suma + x * a;
        		end
       	 else
        		begin
            	ym <= suma + x * a;
             	suma <= 16'h0000; 
        		end
         end
     end
    
    
endmodule
module proc(
    input [15:0] x,
    input [15:0] x_init,
    input [15:0] a,
    input reset,
    input clk,
    output[15:0] y
    );

    reg [15:0] cuenta;
    reg [15:0] suma;
    reg [15:0]ym;
    
    assign y = ym;
    always @ (posedge clk )
    begin
        if (reset == 1'b1)			
            cuenta <= 16'h0000;
        else
		begin
        if (cuenta < 16'h0003)
             cuenta <= cuenta + 16'h0001;
        else
        	cuenta <= 16'h0000; 
		end         
	end
	
    
    always @(posedge clk )
    begin
        if (reset == 1'b1)
        	begin
             ym <= x_init;
             suma <= 16'h0000;
        	end
		else
        begin   
        	if (cuenta < 16'h0003)
        		begin
             	ym <= x;
            	 suma <= suma + x * a;
        		end
       	 else
        		begin
            	ym <= suma + x * a;
             	suma <= 16'h0000; 
        		end
         end
     end
    
    
endmodule