data/full_repos/permissive/143278/ivltests/pr1831724.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1831724.v:7: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'bxxx000000\' generates 9 bits.\n                                                                        : ... In instance test\n tmp1 = 9\'bxxx000000;\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1831724.v:8: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                        : ... In instance test\n tmp2 = {9\'bxxx000000};\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module test;
   reg [15:0] tmp1, tmp2;
   initial
     begin
	tmp1 = 9'bxxx000000;
	tmp2 = {9'bxxx000000};
	$display("tmp1: '%b'; tmp2: '%b'", tmp1, tmp2);
     end
endmodule
module test;

   reg [15:0] tmp1, tmp2;
   initial
     begin
	tmp1 = 9'bxxx000000;
	tmp2 = {9'bxxx000000};
	$display("tmp1: '%b'; tmp2: '%b'", tmp1, tmp2);
     end
endmodule