data/full_repos/permissive/143278/ivltests/br_gh220.v
 line:5 column:14: Illegal character "'"
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br_gh220.v:5: Operator ADD expects 5 bits on the LHS, but LHS\'s CONST \'3\'h7\' generates 3 bits.\n                                                                       : ... In instance Main\n      r5 = 5\'(3\'d7 + 3\'d6);\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br_gh220.v:5: Operator ADD expects 5 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n                                                                       : ... In instance Main\n      r5 = 5\'(3\'d7 + 3\'d6);\n                   ^\n%Error: Exiting due to 2 warning(s)\n'
module Main();
   logic[4:0] r5;

   initial begin
      r5 = 5'(3'd7 + 3'd6);
      $display("r5 = %b, %d", r5, r5);

      if (r5 === 5'b01101)
         $display("PASSED");
      else
         $display("FAILED");
   end

endmodule
module Main();

   logic[4:0] r5;

   initial begin
      r5 = 5'(3'd7 + 3'd6);
      $display("r5 = %b, %d", r5, r5);

      if (r5 === 5'b01101)
         $display("PASSED");
      else
         $display("FAILED");
   end

endmodule