data/full_repos/permissive/173419080/src/rtl/ca_prng.v
1: b"%Error: data/full_repos/permissive/173419080/src/rtl/ca_prng.v:112: Cannot find file containing module: 'ca_prng_core'\n  ca_prng_core core(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173419080/src/rtl,data/full_repos/permissive/173419080/ca_prng_core\n             data/full_repos/permissive/173419080/src/rtl,data/full_repos/permissive/173419080/ca_prng_core.v\n             data/full_repos/permissive/173419080/src/rtl,data/full_repos/permissive/173419080/ca_prng_core.sv\n             ca_prng_core\n             ca_prng_core.v\n             ca_prng_core.sv\n             obj_dir/ca_prng_core\n             obj_dir/ca_prng_core.v\n             obj_dir/ca_prng_core.sv\n%Error: Exiting due to 1 error(s)\n"
module ca_prng(
               input wire           clk,
               input wire           reset_n,

               input wire           cs,
               input wire           we,

               input wire  [7 : 0]  address,
               input wire  [31 : 0] write_data,
               output wire [31 : 0] read_data
              );





  localparam ADDR_NAME0     = 8'h00;
  localparam ADDR_NAME1     = 8'h01;
  localparam ADDR_VERSION   = 8'h02;

  localparam ADDR_CTRL      = 8'h08;
  localparam CTRL_NEXT_BIT  = 0;

  localparam ADDR_RULE      = 8'h0a;
  localparam RULE_LSB       = 0;
  localparam RULE_MSB       = 7;

  localparam ADDR_PATTERN   = 8'h10;

  localparam ADDR_PRNG_DATA = 8'h30;

  localparam CORE_NAME0     = 32'h63615f70;
  localparam CORE_NAME1     = 32'h726e6720;
  localparam CORE_VERSION   = 32'h302e3130;


  localparam [7 : 0] DEFAULT_RULE = 8'b00011110;





  reg          next_reg;
  reg          next_we;

  reg [7 : 0]  rule_reg;
  reg          load_rule_reg;
  reg          load_rule_new;

  reg [31 : 0] pattern_reg;
  reg          load_pattern_reg;
  reg          load_pattern_new;





  reg [31 : 0]   tmp_read_data;

  wire [31 : 0]  core_prng_data;





  assign read_data = tmp_read_data;





  ca_prng_core core(
                   .clk(clk),
                   .reset_n(reset_n),

                   .init_pattern_data(pattern_reg),
                   .load_init_pattern(load_pattern_reg),

                   .next_pattern(next_reg),

                   .update_rule(rule_reg),
                   .load_update_rule(load_rule_reg),

                   .prng_data(core_prng_data)
                  );








  always @ (posedge clk)
    begin : reg_update
      if (!reset_n)
        begin
          next_reg         <= 1'h0;
          load_rule_reg    <= 1'h0;
          rule_reg         <= DEFAULT_RULE;
          load_pattern_reg <= 1'h0;
          pattern_reg      <= 32'hffff_ffff;
        end
      else
        begin
          load_rule_reg    <= load_rule_new;
          load_pattern_reg <= load_pattern_new;

          if (next_we)
            begin
              next_reg <= write_data[CTRL_NEXT_BIT];
            end

          if (load_rule_new)
            rule_reg <= write_data[RULE_MSB : RULE_LSB];

          if (load_pattern_new)
            pattern_reg <= write_data;
        end
    end







  always @*
    begin : api
      next_we          = 1'h0;
      load_rule_new    = 1'h0;
      load_pattern_new = 1'h0;
      tmp_read_data    = 32'h0;

      if (cs)
        begin
          if (we)
            begin
              case (address)
                ADDR_CTRL :    next_we          = 1'h1;
                ADDR_RULE :    load_rule_new    = 1'h1;
                ADDR_PATTERN : load_pattern_new = 1'h1;
                default :;
              endcase
            end
          else
            begin
              case (address)
                ADDR_NAME0 :     tmp_read_data = CORE_NAME0;
                ADDR_NAME1 :     tmp_read_data = CORE_NAME1;
                ADDR_VERSION :   tmp_read_data = CORE_VERSION;
                ADDR_PRNG_DATA : tmp_read_data = core_prng_data;
                default :;
              endcase
            end
        end
    end
endmodule
module ca_prng(
               input wire           clk,
               input wire           reset_n,

               input wire           cs,
               input wire           we,

               input wire  [7 : 0]  address,
               input wire  [31 : 0] write_data,
               output wire [31 : 0] read_data
              );






  localparam ADDR_NAME0     = 8'h00;
  localparam ADDR_NAME1     = 8'h01;
  localparam ADDR_VERSION   = 8'h02;

  localparam ADDR_CTRL      = 8'h08;
  localparam CTRL_NEXT_BIT  = 0;

  localparam ADDR_RULE      = 8'h0a;
  localparam RULE_LSB       = 0;
  localparam RULE_MSB       = 7;

  localparam ADDR_PATTERN   = 8'h10;

  localparam ADDR_PRNG_DATA = 8'h30;

  localparam CORE_NAME0     = 32'h63615f70;
  localparam CORE_NAME1     = 32'h726e6720;
  localparam CORE_VERSION   = 32'h302e3130;


  localparam [7 : 0] DEFAULT_RULE = 8'b00011110;





  reg          next_reg;
  reg          next_we;

  reg [7 : 0]  rule_reg;
  reg          load_rule_reg;
  reg          load_rule_new;

  reg [31 : 0] pattern_reg;
  reg          load_pattern_reg;
  reg          load_pattern_new;





  reg [31 : 0]   tmp_read_data;

  wire [31 : 0]  core_prng_data;





  assign read_data = tmp_read_data;





  ca_prng_core core(
                   .clk(clk),
                   .reset_n(reset_n),

                   .init_pattern_data(pattern_reg),
                   .load_init_pattern(load_pattern_reg),

                   .next_pattern(next_reg),

                   .update_rule(rule_reg),
                   .load_update_rule(load_rule_reg),

                   .prng_data(core_prng_data)
                  );








  always @ (posedge clk)
    begin : reg_update
      if (!reset_n)
        begin
          next_reg         <= 1'h0;
          load_rule_reg    <= 1'h0;
          rule_reg         <= DEFAULT_RULE;
          load_pattern_reg <= 1'h0;
          pattern_reg      <= 32'hffff_ffff;
        end
      else
        begin
          load_rule_reg    <= load_rule_new;
          load_pattern_reg <= load_pattern_new;

          if (next_we)
            begin
              next_reg <= write_data[CTRL_NEXT_BIT];
            end

          if (load_rule_new)
            rule_reg <= write_data[RULE_MSB : RULE_LSB];

          if (load_pattern_new)
            pattern_reg <= write_data;
        end
    end







  always @*
    begin : api
      next_we          = 1'h0;
      load_rule_new    = 1'h0;
      load_pattern_new = 1'h0;
      tmp_read_data    = 32'h0;

      if (cs)
        begin
          if (we)
            begin
              case (address)
                ADDR_CTRL :    next_we          = 1'h1;
                ADDR_RULE :    load_rule_new    = 1'h1;
                ADDR_PATTERN : load_pattern_new = 1'h1;
                default :;
              endcase
            end
          else
            begin
              case (address)
                ADDR_NAME0 :     tmp_read_data = CORE_NAME0;
                ADDR_NAME1 :     tmp_read_data = CORE_NAME1;
                ADDR_VERSION :   tmp_read_data = CORE_VERSION;
                ADDR_PRNG_DATA : tmp_read_data = core_prng_data;
                default :;
              endcase
            end
        end
    end
endmodule