data/full_repos/permissive/218779832/junk/dualpreg1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/218779832/junk/dualpreg1.v:29: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance dualpreg1\n    regmemory[3\'b000] <= 1\'b0;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/dualpreg1.v:30: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance dualpreg1\n    regmemory[3\'b001] <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/dualpreg1.v:31: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance dualpreg1\n    regmemory[3\'b010] <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/dualpreg1.v:32: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance dualpreg1\n    regmemory[3\'b011] <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/dualpreg1.v:33: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance dualpreg1\n    regmemory[3\'b100] <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/dualpreg1.v:34: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance dualpreg1\n    regmemory[3\'b101] <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/dualpreg1.v:35: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance dualpreg1\n    regmemory[3\'b110] <= 1\'b0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/junk/dualpreg1.v:36: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance dualpreg1\n    regmemory[3\'b111] <= 1\'b0;\n                      ^~\n%Error: Exiting due to 8 warning(s)\n'
module dualpreg1 
(
  input clk,
  input  we,  
  input clr,  
  input [7:0] OR2,
  input [7:0] A_in ,
  input [7:0] B_in ,
  input [7:0] ALU_IN,
  input [7:0] SP,
  input [7:0] mem,
  input [2:0] mux_sel,
  input [2:0] read_seg ,
  input [2:0] write_seg,
  output reg [7:0] dataout_A,
  output reg [7:0] dataout_B
);

reg [7:0] regmemory [7:0] ;


always @(posedge clk) 
begin 

if (clr) begin

    regmemory[3'b000] <= 1'b0;
    regmemory[3'b001] <= 1'b0;
    regmemory[3'b010] <= 1'b0;
    regmemory[3'b011] <= 1'b0;
    regmemory[3'b100] <= 1'b0;
    regmemory[3'b101] <= 1'b0;
    regmemory[3'b110] <= 1'b0;
    regmemory[3'b111] <= 1'b0;
end


else if (we) begin

    if (mux_sel == 3'b000)
    begin
    regmemory[write_seg] = A_in;
    end

    else if (mux_sel == 3'b001)
    begin 
    regmemory[write_seg] = B_in;
    end

    else if (mux_sel == 3'b010)
    begin
    regmemory[write_seg] = OR2;
    end

    else if (mux_sel == 3'b011)
    begin
    regmemory[write_seg] = ALU_IN;
    end

    else if (mux_sel == 3'b100)
    begin 
    regmemory [3'b000] = SP ;
    end

    else if (mux_sel == 3'b101)
    begin
    regmemory[3'b000] = B_in;
    end

    else if (mux_sel == 3'b110)
    begin
    regmemory[write_seg] = mem;
    end
    
 end
end


  always @(posedge clk) 
  begin 
   dataout_A <= regmemory[3'b000];
   dataout_B <= regmemory[read_seg]; 
  end

endmodule
module dualpreg1 
(
  input clk,
  input  we,  
  input clr,  
  input [7:0] OR2,
  input [7:0] A_in ,
  input [7:0] B_in ,
  input [7:0] ALU_IN,
  input [7:0] SP,
  input [7:0] mem,
  input [2:0] mux_sel,
  input [2:0] read_seg ,
  input [2:0] write_seg,
  output reg [7:0] dataout_A,
  output reg [7:0] dataout_B
);


reg [7:0] regmemory [7:0] ;


always @(posedge clk) 
begin 

if (clr) begin

    regmemory[3'b000] <= 1'b0;
    regmemory[3'b001] <= 1'b0;
    regmemory[3'b010] <= 1'b0;
    regmemory[3'b011] <= 1'b0;
    regmemory[3'b100] <= 1'b0;
    regmemory[3'b101] <= 1'b0;
    regmemory[3'b110] <= 1'b0;
    regmemory[3'b111] <= 1'b0;
end


else if (we) begin

    if (mux_sel == 3'b000)
    begin
    regmemory[write_seg] = A_in;
    end

    else if (mux_sel == 3'b001)
    begin 
    regmemory[write_seg] = B_in;
    end

    else if (mux_sel == 3'b010)
    begin
    regmemory[write_seg] = OR2;
    end

    else if (mux_sel == 3'b011)
    begin
    regmemory[write_seg] = ALU_IN;
    end

    else if (mux_sel == 3'b100)
    begin 
    regmemory [3'b000] = SP ;
    end

    else if (mux_sel == 3'b101)
    begin
    regmemory[3'b000] = B_in;
    end

    else if (mux_sel == 3'b110)
    begin
    regmemory[write_seg] = mem;
    end
    
 end
end


  always @(posedge clk) 
  begin 
   dataout_A <= regmemory[3'b000];
   dataout_B <= regmemory[read_seg]; 
  end

endmodule