data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/xianshi_clk.v
data/verilator_xmls/b261e5e3-edf5-4ee8-873f-50d9df1b6b48.xml
module xianshi_clk(clk,show_clk);
input clk;
output reg show_clk;
reg [31:0]num;
initial
begin
    num=0;
    show_clk=0;
end
always@(posedge clk)
begin
    num=num+1;
    if(num==15000)
    begin
        show_clk=1;
    end
    else if(num==30000)
    begin
        show_clk=0;
        num=0;
    end
end
endmodule
module xianshi_clk(clk,show_clk);

input clk;
output reg show_clk;
reg [31:0]num;
initial
begin
    num=0;
    show_clk=0;
end
always@(posedge clk)
begin
    num=num+1;
    if(num==15000)
    begin
        show_clk=1;
    end
    else if(num==30000)
    begin
        show_clk=0;
        num=0;
    end
end
endmodule