data/full_repos/permissive/211316121/lab7_1/Traffic.v
data/verilator_xmls/d80df452-d447-43cb-b1a0-9552c0d2c2a2.xml
module clkdiv(
input clk,
input reset,
output clk15,
output clk45
);

    reg [5:0] value;
    always@(posedge clk,posedge reset)
        if(reset) value<=0;
        else if(value<45) value<=value+1;
             else              value<=45;
             
    assign clk15 = (value>=14);
    assign clk45 = (value>=44);
endmodule
module clkdiv(
input clk,
input reset,
output clk15,
output clk45
);


    reg [5:0] value;
    always@(posedge clk,posedge reset)
        if(reset) value<=0;
        else if(value<45) value<=value+1;
             else              value<=45;
             
    assign clk15 = (value>=14);
    assign clk45 = (value>=44);
endmodule