data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/capture/tart_capture.v
None: at end of input
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/capture/tart_capture.v:109: Cannot find include file: tartcfg.v\n`include "tartcfg.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/capture,data/full_repos/permissive/20430511/tartcfg.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/capture,data/full_repos/permissive/20430511/tartcfg.v.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/capture,data/full_repos/permissive/20430511/tartcfg.v.sv\n             tartcfg.v\n             tartcfg.v.v\n             tartcfg.v.sv\n             obj_dir/tartcfg.v\n             obj_dir/tartcfg.v.v\n             obj_dir/tartcfg.v.sv\n%Error: Exiting due to 1 error(s)\n'
module tart_capture
  #(
    parameter AXNUM = 24,
    parameter MSB   = AXNUM-1,
    parameter SBITS = 5,
    parameter SSB   = SBITS-1,
    parameter ABITS = 20,
    parameter ASB   = ABITS-2,


    parameter DEBUG = 1,
    parameter MULTI = 1,
    parameter RNG   = 1,
    parameter CONST = 0,
    parameter CDATA = 24'h0,


    parameter ALIGN = 1,
    parameter DRIFT = 1,
    parameter RATIO = 12,
    parameter RMAX  = RATIO-1,
    parameter RBITS = 4,
    parameter RSB   = RBITS-1,
    parameter TICKS = 3,


    parameter RESET = 1,
    parameter CHECK = 1,
    parameter PIPED = 1,


    parameter NOISY = 0,
    parameter DELAY = 3)
   (
    input          clock_e,
    input          clock_n,
    input          clock_i,
    input          reset_i,


    input          cyc_i,
    input          stb_i,
    input          we_i,
    output         ack_o,
    output         wat_o,
    output         rty_o,
    output         err_o,
    input [1:0]    adr_i,
    input [7:0]    dat_i,
    output [7:0]   dat_o,
    

    input [MSB:0]  signal_e_i,


    output         enabled_o,
    output         strobe_o,
    output         middle_o,
    output [MSB:0] signal_o,
    output         centred_o,
    output         debug_o
    );






   reg             reset_e, reset_n;
   reg             debug_e, shift_e, count_e;





   reg             en_capture = 1'b0, en_centre = 1'b0, en_debug = 1'b0;
   wire            en_source;
   reg             enabled = 1'b0;





   wire [MSB:0]    signal_p, signal_n;
   reg [MSB:0]     source, signal;
   wire [MSB:0]    signal_w, sig_ddr;



   wire            source_p, source_n;
   wire            ref_p, ref_n;
   wire            fake_p, fake_n;





   wire [MSB:0]    fake_e, sig_dbg;
   (* NOMERGE = "TRUE" *)
   reg [MSB:0]     fake_b_p, fake_b_n, fake_n_n;








   wire [7:0]      tc_system, tc_centre, tc_debug, tc_status;
   wire [4:0]      tc_number = AXNUM;
   reg [SSB:0]     tc_select = {SBITS{1'b0}};
   wire            tc_invalid, tc_locked, tc_strobe, tc_middle;
   wire [RSB:0]    tc_phase, tc_delta;
   reg [RSB:0]     tc_delay = {RBITS{1'b0}};
   reg             tc_invert = 1'b0, tc_restart = 1'b0;
   reg             tc_drift, tc_count, tc_shift;



   reg [7:0]       dat;
   reg             ack = 1'b0;
   wire            cyc_w, stb_w, fetch, store;









   assign tc_centre = {en_centre, tc_drift, tc_invert, 1'b0, tc_delay[3:0]};
   assign tc_status = {tc_delta[3:0], tc_phase[3:0]};
   assign tc_debug  = {en_debug, tc_count, tc_shift, tc_number};
   assign tc_system = {en_capture, tc_invalid, tc_locked, tc_select};



   assign cyc_w = CHECK ? cyc_i : 1'b1;
   assign stb_w = cyc_w && stb_i;

   assign fetch = PIPED ? stb_w && !we_i : stb_w && !we_i &&  ack;
   assign store = PIPED ? stb_w &&  we_i : stb_w &&  we_i && !ack;


   assign ack_o = ack;
   assign wat_o = 1'b0;
   assign rty_o = 1'b0;
   assign err_o = 1'b0;
   assign dat_o = dat;





   assign enabled_o = enabled;
   assign strobe_o  = tc_strobe;
   assign middle_o  = tc_middle;
   assign centred_o = tc_locked;
   assign debug_o   = en_debug;
   assign signal_o  = signal;



   assign sig_ddr = tc_delay[0] ? signal_n : signal_p;
   assign sig_dbg = tc_delay[0] ? fake_b_n : fake_b_p;




   assign fake_p    = fake_b_p[0];
   assign fake_n    = fake_b_n[0];









   always @(posedge clock_i)
     if (reset_i && RESET)
       ack <= #DELAY 1'b0;
     else
       ack <= #DELAY stb_w;



   always @(posedge clock_i)
     if (stb_w)
       case (adr_i)
         `CAP_CENTRE: dat <= #DELAY tc_centre;
         `CAP_STATUS: dat <= #DELAY tc_status;
         `CAP_DEBUG:  dat <= #DELAY tc_debug;
         `CAP_SYSTEM: dat <= #DELAY tc_system;
         default:     dat <= #DELAY 8'bx;
       endcase







   always @(posedge clock_i)
     if (reset_i)
       en_centre <= #DELAY 1'b0;
     else if (store && adr_i == `CAP_CENTRE)
       en_centre <= #DELAY dat_i[7];
     else
       en_centre <= #DELAY en_centre;

   always @(posedge clock_i)
     if (reset_i && RESET)
       {tc_drift, tc_invert} <= #DELAY 2'b00;
     else if (store && adr_i == `CAP_CENTRE)
       {tc_drift, tc_invert} <= #DELAY dat_i[6:5];
     else
       {tc_drift, tc_invert} <= #DELAY {tc_drift, tc_invert};


   always @(posedge clock_i)
     if (reset_i && RESET)
       tc_delay <= #DELAY {RBITS{1'b0}};
     else if (ALIGN && store && adr_i == `CAP_CENTRE)
       tc_delay <= #DELAY dat_i[RSB:0];
     else
       tc_delay <= #DELAY tc_delay;


   always @(posedge clock_i)
     if (reset_i && RESET)
       tc_restart <= #DELAY 1'b0;
     else if (store && adr_i == `CAP_CENTRE && en_centre)
       tc_restart <= #DELAY 1'b1;
     else
       tc_restart <= #DELAY 1'b0;



   always @(posedge clock_i)
     if (reset_i)
       {en_debug, tc_count, tc_shift} <= #DELAY 3'h0;
     else if (DEBUG && store && adr_i == `CAP_DEBUG)
       {en_debug, tc_count, tc_shift} <= #DELAY dat_i[7:5];
     else
       {en_debug, tc_count, tc_shift} <= #DELAY {en_debug, tc_count, tc_shift};



   always @(posedge clock_i)
     if (reset_i)
       en_capture <= #DELAY 1'b0;
     else if (store && adr_i == `CAP_SYSTEM)
       en_capture <= #DELAY dat_i[7];
     else
       en_capture <= #DELAY en_capture;

   always @(posedge clock_i)
     if (reset_i && RESET)
       tc_select <= #DELAY {SBITS{1'b0}};
     else if (store && adr_i == `CAP_SYSTEM)
       tc_select <= #DELAY dat_i[SSB:0];
     else
       tc_select <= #DELAY tc_select;






   always @(posedge clock_i)
     if (reset_i && RESET || !en_capture)
       enabled <= #DELAY 1'b0;
     else if (en_capture && tc_strobe)
       enabled <= #DELAY 1'b1;
     else
       enabled <= #DELAY enabled;







   always @(posedge clock_e or posedge reset_i)
     if (reset_i && DEBUG)
       reset_e <= #DELAY 1'b1;
     else if (reset_n || !DEBUG)
       reset_e <= #DELAY 1'b0;
     else
       reset_e <= #DELAY reset_e;



   always @(posedge clock_e)
     begin
        reset_n <= #DELAY reset_e;
        debug_e <= #DELAY en_debug;
        shift_e <= #DELAY tc_shift;
        count_e <= #DELAY tc_count;
     end












   always @(posedge clock_i) begin
     fake_b_p <= #DELAY DEBUG ? fake_e : {AXNUM{1'b0}};
     fake_b_n <= #DELAY fake_n_n;
   end



   always @(posedge clock_n)
     fake_n_n <= #DELAY DEBUG ? fake_e : {AXNUM{1'b0}};




   always @(posedge clock_i)
     source <= #DELAY en_debug ? sig_dbg : sig_ddr;




   always @(posedge clock_i)
     signal <= #DELAY tc_strobe ? signal_w : signal;






`ifdef __RELEASE_BUILD
   assign fake_e = {AXNUM{1'b0}};
`else
   (* AREA_GROUP = "fake" *)
   fake_telescope
     #(  .WIDTH(AXNUM),
         .MULTI(MULTI),
         .RNG  (RNG),
         .CONST(CONST),
         .CDATA(CDATA),
         .DELAY(DELAY)
         ) FAKE
       ( .clock_i (clock_e),
         .reset_i (reset_e),
         .enable_i(debug_e),
         .shift_i (shift_e),
         .count_i (count_e),
         .valid_o (),
         .data_o  (fake_e)
         );
`endif





   (* AREA_GROUP = "source" *)
   signal_source
     #( .WIDTH(AXNUM+2),
        .SBITS(SBITS),
        .RESET(0),
        .DELAY(DELAY)
        ) SOURCE
       (
        .clock_i (clock_i),
        .reset_i (reset_i),
        .enable_i(en_centre),
        .select_i(tc_select),
        .sig_p_i ({fake_p, ref_p, signal_p}),
        .sig_n_i ({fake_n, ref_n, signal_n}),
        .valid_o (en_source),
        .sig_p_o (source_p),
        .sig_n_o (source_n)
        );









   (* AREA_GROUP = "phase" *)
   signal_phase_DDR
     #( .RATIO(RATIO >> 1),
        .RBITS(RBITS - 1),
        .RESET(1),
        .TICKS(TICKS),
        .POLAR(1),
        .COUNT(7),
        .NOISY(NOISY),
        .DELAY(DELAY)
        ) PHASE
       (
        .clk_e_i (clock_e),
        .clk_n_i (clock_n),
        .clk_s_i (clock_i),
        .reset_i (reset_i),

        .enable_i(en_source),
        .invert_i(tc_invert),
        .strobe_o(tc_strobe),
        .middle_o(tc_middle),
        .sig_p_i (source_p),
        .sig_n_i (source_n),

        .phase_o (tc_phase),
        .delta_o (tc_delta),
        .locked_o(tc_locked),
        .error_o (tc_invalid),
        .retry_i (tc_restart),


        .ref_p_o (ref_p),
        .ref_n_o (ref_n)
        );





   wire [MSB:0] phased;

   assign signal_w = ALIGN ? phased : source;

   (* AREA_GROUP = "shreg" *)
   shift_reg
     #(  .DEPTH(8),
         .ABITS(3),
         .DELAY(DELAY)
         ) SHREG [MSB:0]
       ( .clk(clock_i),
         .ce (ALIGN && en_capture),
         .a  (ALIGN ? tc_delay[3:1] : 3'h0),
         .d  (source),
         .q  (phased)
         );










   IDDR2
     #( .DDR_ALIGNMENT("C0"),
        .SRTYPE("SYNC")
        ) IOBS [MSB:0]
     ( .C0(clock_i),
       .C1(clock_n),
       .R (reset_i && RESET),
       .CE(en_capture),
       .D (signal_e_i),
       .Q0(signal_p),
       .Q1(signal_n)
       );



endmodule
module tart_capture
  #(
    parameter AXNUM = 24,
    parameter MSB   = AXNUM-1,
    parameter SBITS = 5,
    parameter SSB   = SBITS-1,
    parameter ABITS = 20,
    parameter ASB   = ABITS-2,


    parameter DEBUG = 1,
    parameter MULTI = 1,
    parameter RNG   = 1,
    parameter CONST = 0,
    parameter CDATA = 24'h0,


    parameter ALIGN = 1,
    parameter DRIFT = 1,
    parameter RATIO = 12,
    parameter RMAX  = RATIO-1,
    parameter RBITS = 4,
    parameter RSB   = RBITS-1,
    parameter TICKS = 3,


    parameter RESET = 1,
    parameter CHECK = 1,
    parameter PIPED = 1,


    parameter NOISY = 0,
    parameter DELAY = 3)
   (
    input          clock_e,
    input          clock_n,
    input          clock_i,
    input          reset_i,


    input          cyc_i,
    input          stb_i,
    input          we_i,
    output         ack_o,
    output         wat_o,
    output         rty_o,
    output         err_o,
    input [1:0]    adr_i,
    input [7:0]    dat_i,
    output [7:0]   dat_o,
    

    input [MSB:0]  signal_e_i,


    output         enabled_o,
    output         strobe_o,
    output         middle_o,
    output [MSB:0] signal_o,
    output         centred_o,
    output         debug_o
    );







   reg             reset_e, reset_n;
   reg             debug_e, shift_e, count_e;





   reg             en_capture = 1'b0, en_centre = 1'b0, en_debug = 1'b0;
   wire            en_source;
   reg             enabled = 1'b0;





   wire [MSB:0]    signal_p, signal_n;
   reg [MSB:0]     source, signal;
   wire [MSB:0]    signal_w, sig_ddr;



   wire            source_p, source_n;
   wire            ref_p, ref_n;
   wire            fake_p, fake_n;





   wire [MSB:0]    fake_e, sig_dbg;
   (* NOMERGE = "TRUE" *)
   reg [MSB:0]     fake_b_p, fake_b_n, fake_n_n;








   wire [7:0]      tc_system, tc_centre, tc_debug, tc_status;
   wire [4:0]      tc_number = AXNUM;
   reg [SSB:0]     tc_select = {SBITS{1'b0}};
   wire            tc_invalid, tc_locked, tc_strobe, tc_middle;
   wire [RSB:0]    tc_phase, tc_delta;
   reg [RSB:0]     tc_delay = {RBITS{1'b0}};
   reg             tc_invert = 1'b0, tc_restart = 1'b0;
   reg             tc_drift, tc_count, tc_shift;



   reg [7:0]       dat;
   reg             ack = 1'b0;
   wire            cyc_w, stb_w, fetch, store;









   assign tc_centre = {en_centre, tc_drift, tc_invert, 1'b0, tc_delay[3:0]};
   assign tc_status = {tc_delta[3:0], tc_phase[3:0]};
   assign tc_debug  = {en_debug, tc_count, tc_shift, tc_number};
   assign tc_system = {en_capture, tc_invalid, tc_locked, tc_select};



   assign cyc_w = CHECK ? cyc_i : 1'b1;
   assign stb_w = cyc_w && stb_i;

   assign fetch = PIPED ? stb_w && !we_i : stb_w && !we_i &&  ack;
   assign store = PIPED ? stb_w &&  we_i : stb_w &&  we_i && !ack;


   assign ack_o = ack;
   assign wat_o = 1'b0;
   assign rty_o = 1'b0;
   assign err_o = 1'b0;
   assign dat_o = dat;





   assign enabled_o = enabled;
   assign strobe_o  = tc_strobe;
   assign middle_o  = tc_middle;
   assign centred_o = tc_locked;
   assign debug_o   = en_debug;
   assign signal_o  = signal;



   assign sig_ddr = tc_delay[0] ? signal_n : signal_p;
   assign sig_dbg = tc_delay[0] ? fake_b_n : fake_b_p;




   assign fake_p    = fake_b_p[0];
   assign fake_n    = fake_b_n[0];









   always @(posedge clock_i)
     if (reset_i && RESET)
       ack <= #DELAY 1'b0;
     else
       ack <= #DELAY stb_w;



   always @(posedge clock_i)
     if (stb_w)
       case (adr_i)
         `CAP_CENTRE: dat <= #DELAY tc_centre;
         `CAP_STATUS: dat <= #DELAY tc_status;
         `CAP_DEBUG:  dat <= #DELAY tc_debug;
         `CAP_SYSTEM: dat <= #DELAY tc_system;
         default:     dat <= #DELAY 8'bx;
       endcase







   always @(posedge clock_i)
     if (reset_i)
       en_centre <= #DELAY 1'b0;
     else if (store && adr_i == `CAP_CENTRE)
       en_centre <= #DELAY dat_i[7];
     else
       en_centre <= #DELAY en_centre;

   always @(posedge clock_i)
     if (reset_i && RESET)
       {tc_drift, tc_invert} <= #DELAY 2'b00;
     else if (store && adr_i == `CAP_CENTRE)
       {tc_drift, tc_invert} <= #DELAY dat_i[6:5];
     else
       {tc_drift, tc_invert} <= #DELAY {tc_drift, tc_invert};


   always @(posedge clock_i)
     if (reset_i && RESET)
       tc_delay <= #DELAY {RBITS{1'b0}};
     else if (ALIGN && store && adr_i == `CAP_CENTRE)
       tc_delay <= #DELAY dat_i[RSB:0];
     else
       tc_delay <= #DELAY tc_delay;


   always @(posedge clock_i)
     if (reset_i && RESET)
       tc_restart <= #DELAY 1'b0;
     else if (store && adr_i == `CAP_CENTRE && en_centre)
       tc_restart <= #DELAY 1'b1;
     else
       tc_restart <= #DELAY 1'b0;



   always @(posedge clock_i)
     if (reset_i)
       {en_debug, tc_count, tc_shift} <= #DELAY 3'h0;
     else if (DEBUG && store && adr_i == `CAP_DEBUG)
       {en_debug, tc_count, tc_shift} <= #DELAY dat_i[7:5];
     else
       {en_debug, tc_count, tc_shift} <= #DELAY {en_debug, tc_count, tc_shift};



   always @(posedge clock_i)
     if (reset_i)
       en_capture <= #DELAY 1'b0;
     else if (store && adr_i == `CAP_SYSTEM)
       en_capture <= #DELAY dat_i[7];
     else
       en_capture <= #DELAY en_capture;

   always @(posedge clock_i)
     if (reset_i && RESET)
       tc_select <= #DELAY {SBITS{1'b0}};
     else if (store && adr_i == `CAP_SYSTEM)
       tc_select <= #DELAY dat_i[SSB:0];
     else
       tc_select <= #DELAY tc_select;






   always @(posedge clock_i)
     if (reset_i && RESET || !en_capture)
       enabled <= #DELAY 1'b0;
     else if (en_capture && tc_strobe)
       enabled <= #DELAY 1'b1;
     else
       enabled <= #DELAY enabled;







   always @(posedge clock_e or posedge reset_i)
     if (reset_i && DEBUG)
       reset_e <= #DELAY 1'b1;
     else if (reset_n || !DEBUG)
       reset_e <= #DELAY 1'b0;
     else
       reset_e <= #DELAY reset_e;



   always @(posedge clock_e)
     begin
        reset_n <= #DELAY reset_e;
        debug_e <= #DELAY en_debug;
        shift_e <= #DELAY tc_shift;
        count_e <= #DELAY tc_count;
     end












   always @(posedge clock_i) begin
     fake_b_p <= #DELAY DEBUG ? fake_e : {AXNUM{1'b0}};
     fake_b_n <= #DELAY fake_n_n;
   end



   always @(posedge clock_n)
     fake_n_n <= #DELAY DEBUG ? fake_e : {AXNUM{1'b0}};




   always @(posedge clock_i)
     source <= #DELAY en_debug ? sig_dbg : sig_ddr;




   always @(posedge clock_i)
     signal <= #DELAY tc_strobe ? signal_w : signal;






`ifdef __RELEASE_BUILD
   assign fake_e = {AXNUM{1'b0}};
`else
   (* AREA_GROUP = "fake" *)
   fake_telescope
     #(  .WIDTH(AXNUM),
         .MULTI(MULTI),
         .RNG  (RNG),
         .CONST(CONST),
         .CDATA(CDATA),
         .DELAY(DELAY)
         ) FAKE
       ( .clock_i (clock_e),
         .reset_i (reset_e),
         .enable_i(debug_e),
         .shift_i (shift_e),
         .count_i (count_e),
         .valid_o (),
         .data_o  (fake_e)
         );
`endif





   (* AREA_GROUP = "source" *)
   signal_source
     #( .WIDTH(AXNUM+2),
        .SBITS(SBITS),
        .RESET(0),
        .DELAY(DELAY)
        ) SOURCE
       (
        .clock_i (clock_i),
        .reset_i (reset_i),
        .enable_i(en_centre),
        .select_i(tc_select),
        .sig_p_i ({fake_p, ref_p, signal_p}),
        .sig_n_i ({fake_n, ref_n, signal_n}),
        .valid_o (en_source),
        .sig_p_o (source_p),
        .sig_n_o (source_n)
        );









   (* AREA_GROUP = "phase" *)
   signal_phase_DDR
     #( .RATIO(RATIO >> 1),
        .RBITS(RBITS - 1),
        .RESET(1),
        .TICKS(TICKS),
        .POLAR(1),
        .COUNT(7),
        .NOISY(NOISY),
        .DELAY(DELAY)
        ) PHASE
       (
        .clk_e_i (clock_e),
        .clk_n_i (clock_n),
        .clk_s_i (clock_i),
        .reset_i (reset_i),

        .enable_i(en_source),
        .invert_i(tc_invert),
        .strobe_o(tc_strobe),
        .middle_o(tc_middle),
        .sig_p_i (source_p),
        .sig_n_i (source_n),

        .phase_o (tc_phase),
        .delta_o (tc_delta),
        .locked_o(tc_locked),
        .error_o (tc_invalid),
        .retry_i (tc_restart),


        .ref_p_o (ref_p),
        .ref_n_o (ref_n)
        );





   wire [MSB:0] phased;

   assign signal_w = ALIGN ? phased : source;

   (* AREA_GROUP = "shreg" *)
   shift_reg
     #(  .DEPTH(8),
         .ABITS(3),
         .DELAY(DELAY)
         ) SHREG [MSB:0]
       ( .clk(clock_i),
         .ce (ALIGN && en_capture),
         .a  (ALIGN ? tc_delay[3:1] : 3'h0),
         .d  (source),
         .q  (phased)
         );










   IDDR2
     #( .DDR_ALIGNMENT("C0"),
        .SRTYPE("SYNC")
        ) IOBS [MSB:0]
     ( .C0(clock_i),
       .C1(clock_n),
       .R (reset_i && RESET),
       .CE(en_capture),
       .D (signal_e_i),
       .Q0(signal_p),
       .Q1(signal_n)
       );



endmodule