data/full_repos/permissive/135622446/trig2_board_firmware/serialprocessor.v
 line:12: before: "]"
data/verilator_xmls/c69b13a9-5210-458b-863d-3f8ffe668acc.xml
module processor(clk, rxReady, rxData, txBusy, txStart, txData, readdata,
	deadticks, firingticks, enable_outputs);
	
	input clk;
	input[7:0] rxData;
	input rxReady;
	input txBusy;
	output reg txStart;
	output reg[7:0] txData;
	output reg[7:0] readdata;
	output reg enable_outputs=0;
	reg [7:0] extradata[10];
	localparam READ=0, SOLVING=1, WRITE1=3, WRITE2=4, READMORE=9;
	integer state=READ;
	integer bytesread, byteswanted;
	
	integer ioCount, ioCountToSend;
	reg[7:0] data[0:15];
	
	output reg[7:0] deadticks=10;
	output reg[7:0] firingticks=9;

	always @(posedge clk) begin
	case (state)
	READ: begin		  
		txStart<=0;
		bytesread<=0;
		byteswanted<=0;
      ioCount = 0;
      if (rxReady) begin
			readdata = rxData;
         state = SOLVING;
      end
	end
	READMORE: begin
		if (rxReady) begin
			extradata[bytesread] = rxData;
			bytesread = bytesread+1;
			if (bytesread>=byteswanted) state=SOLVING;
		end
	end
   SOLVING: begin
		if (readdata==0) begin
			ioCountToSend = 1;
			data[0]=2;
			state=WRITE1;				
		end
		else if (readdata==1) begin
			byteswanted=1; if (bytesread<byteswanted) state=READMORE;
			else begin
				deadticks=extradata[0];
				state=READ;
			end
		end
		else if (readdata==2) begin
			byteswanted=1; if (bytesread<byteswanted) state=READMORE;
			else begin
				firingticks=extradata[0];
				state=READ;
			end
		end
		else if (readdata==3) begin
			enable_outputs = ~enable_outputs;
			state=READ;
		end
		else state=READ;
	end		
	

	WRITE1: begin
		if (!txBusy) begin
			txData = data[ioCount];
         txStart = 1;
         state = WRITE2;
		end
	end
   WRITE2: begin
		txStart = 0;
      if (ioCount < ioCountToSend-1) begin
			ioCount = ioCount + 1;
         state = WRITE1;
      end
		else state = READ;
	end

	endcase
	end  
	
endmodule
module processor(clk, rxReady, rxData, txBusy, txStart, txData, readdata,
	deadticks, firingticks, enable_outputs);

	
	input clk;
	input[7:0] rxData;
	input rxReady;
	input txBusy;
	output reg txStart;
	output reg[7:0] txData;
	output reg[7:0] readdata;
	output reg enable_outputs=0;
	reg [7:0] extradata[10];
	localparam READ=0, SOLVING=1, WRITE1=3, WRITE2=4, READMORE=9;
	integer state=READ;
	integer bytesread, byteswanted;
	
	integer ioCount, ioCountToSend;
	reg[7:0] data[0:15];
	
	output reg[7:0] deadticks=10;
	output reg[7:0] firingticks=9;

	always @(posedge clk) begin
	case (state)
	READ: begin		  
		txStart<=0;
		bytesread<=0;
		byteswanted<=0;
      ioCount = 0;
      if (rxReady) begin
			readdata = rxData;
         state = SOLVING;
      end
	end
	READMORE: begin
		if (rxReady) begin
			extradata[bytesread] = rxData;
			bytesread = bytesread+1;
			if (bytesread>=byteswanted) state=SOLVING;
		end
	end
   SOLVING: begin
		if (readdata==0) begin
			ioCountToSend = 1;
			data[0]=2;
			state=WRITE1;				
		end
		else if (readdata==1) begin
			byteswanted=1; if (bytesread<byteswanted) state=READMORE;
			else begin
				deadticks=extradata[0];
				state=READ;
			end
		end
		else if (readdata==2) begin
			byteswanted=1; if (bytesread<byteswanted) state=READMORE;
			else begin
				firingticks=extradata[0];
				state=READ;
			end
		end
		else if (readdata==3) begin
			enable_outputs = ~enable_outputs;
			state=READ;
		end
		else state=READ;
	end		
	

	WRITE1: begin
		if (!txBusy) begin
			txData = data[ioCount];
         txStart = 1;
         state = WRITE2;
		end
	end
   WRITE2: begin
		txStart = 0;
      if (ioCount < ioCountToSend-1) begin
			ioCount = ioCount + 1;
         state = WRITE1;
      end
		else state = READ;
	end

	endcase
	end  
	
endmodule