data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v
None: at end of input
1: b'%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:38: Cannot find include file: timescale.v\n`include "timescale.v"\n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/152581089/Verilog/MSP430,data/full_repos/permissive/152581089/timescale.v\n             data/full_repos/permissive/152581089/Verilog/MSP430,data/full_repos/permissive/152581089/timescale.v.v\n             data/full_repos/permissive/152581089/Verilog/MSP430,data/full_repos/permissive/152581089/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:41: Cannot find include file: openMSP430_defines.v\n`include "openMSP430_defines.v"\n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:210: Cannot find include file: registers.v\n`include "registers.v"\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:213: Cannot find include file: dbg_uart_tasks.v\n`include "dbg_uart_tasks.v"\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:214: Cannot find include file: dbg_i2c_tasks.v\n`include "dbg_i2c_tasks.v"\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:51: Define or directive not defined: \'`DMEM_MSB\'\nwire [`DMEM_MSB:0] dmem_addr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:51: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`DMEM_MSB:0] dmem_addr;\n               ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:58: Define or directive not defined: \'`PMEM_MSB\'\nwire [`PMEM_MSB:0] pmem_addr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:58: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`PMEM_MSB:0] pmem_addr;\n               ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:147: Define or directive not defined: \'`IRQ_NR\'\nreg  [`IRQ_NR-3:0] irq;\n      ^~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:148: Define or directive not defined: \'`IRQ_NR\'\nwire [`IRQ_NR-3:0] irq_acc;\n      ^~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:149: Define or directive not defined: \'`IRQ_NR\'\nwire [`IRQ_NR-3:0] irq_in;\n      ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:228: Unsupported: Ignoring delay on this delayed statement.\n     #10 $readmemh("./random_long1.mem", pmem_0.mem);\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:241: Unsupported: Ignoring delay on this delayed statement.\n          #25;    \n          ^\n%Warning-STMTDLY: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:254: Unsupported: Ignoring delay on this delayed statement.\n          #763;   \n          ^\n%Warning-STMTDLY: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:264: Unsupported: Ignoring delay on this delayed statement.\n     #93;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:266: Unsupported: Ignoring delay on this delayed statement.\n     #593;\n     ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:274: Define or directive not defined: \'`IRQ_NR\'\n     irq                     = {`IRQ_NR-2{1\'b0}};\n                                ^~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:369: Define or directive not defined: \'`PMEM_MSB\'\nram #(`PMEM_MSB, `PMEM_SIZE) pmem_0 (\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:369: Define or directive not defined: \'`PMEM_SIZE\'\nram #(`PMEM_MSB, `PMEM_SIZE) pmem_0 (\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:387: Define or directive not defined: \'`DMEM_MSB\'\nram #(`DMEM_MSB, `DMEM_SIZE) dmem_0 (\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:387: Define or directive not defined: \'`DMEM_SIZE\'\nram #(`DMEM_MSB, `DMEM_SIZE) dmem_0 (\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:536: Define or directive not defined: \'`IRQ_NR\'\n    .irq_ta0_acc  (irq_acc[`IRQ_NR-7]), \n                           ^~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:603: Number is missing value digits: 15\'d\ntemplate_periph_16b #(.BASE_ADDR((15\'d`PER_SIZE-15\'h0070) & 15\'h7ff8)) template_periph_16b_0 (\n                                  ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:603: Define or directive not defined: \'`PER_SIZE\'\ntemplate_periph_16b #(.BASE_ADDR((15\'d`PER_SIZE-15\'h0070) & 15\'h7ff8)) template_periph_16b_0 (\n                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:646: Define or directive not defined: \'`IRQ_NR\'\n                         {`IRQ_NR-15{1\'b0}}};   \n                          ^~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:741: Unsupported or unknown PLI call: $dumpfile\n          $dumpfile("tb_openMSP430.vcd");\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:742: Unsupported or unknown PLI call: $dumpvars\n          $dumpvars(0, tb_openMSP430);\n          ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:762: Unsupported: Ignoring delay on this delayed statement.\n       #500000;\n       ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:775: syntax error, unexpected \'@\'\n     @(negedge stimulus_done);\n     ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/tb_openMSP430.v:776: Unsupported: wait statements\n     wait(inst_pc==\'hffff);\n     ^~~~\n%Error: Exiting due to 25 error(s), 6 warning(s)\n'
module  tb_openMSP430;






wire [`DMEM_MSB:0] dmem_addr;
wire               dmem_cen;
wire        [15:0] dmem_din;
wire         [1:0] dmem_wen;
wire        [15:0] dmem_dout;


wire [`PMEM_MSB:0] pmem_addr;
wire               pmem_cen;
wire        [15:0] pmem_din;
wire         [1:0] pmem_wen;
wire        [15:0] pmem_dout;


wire        [13:0] per_addr;
wire        [15:0] per_din;
wire        [15:0] per_dout;
wire         [1:0] per_we;
wire               per_en;


wire               irq_port1;
wire               irq_port2;
wire        [15:0] per_dout_dio;
wire         [7:0] p1_dout;
wire         [7:0] p1_dout_en;
wire         [7:0] p1_sel;
wire         [7:0] p2_dout;
wire         [7:0] p2_dout_en;
wire         [7:0] p2_sel;
wire         [7:0] p3_dout;
wire         [7:0] p3_dout_en;
wire         [7:0] p3_sel;
wire         [7:0] p4_dout;
wire         [7:0] p4_dout_en;
wire         [7:0] p4_sel;
wire         [7:0] p5_dout;
wire         [7:0] p5_dout_en;
wire         [7:0] p5_sel;
wire         [7:0] p6_dout;
wire         [7:0] p6_dout_en;
wire         [7:0] p6_sel;
reg          [7:0] p1_din;
reg          [7:0] p2_din;
reg          [7:0] p3_din;
reg          [7:0] p4_din;
reg          [7:0] p5_din;
reg          [7:0] p6_din;


wire        [15:0] per_dout_temp_8b;
wire        [15:0] per_dout_temp_16b;


wire        [15:0] per_dout_uart;
wire               irq_uart_rx;
wire               irq_uart_tx;
wire               uart_txd;
reg                uart_rxd;


wire               irq_ta0;
wire               irq_ta1;
wire        [15:0] per_dout_timerA;
reg                inclk;
reg                taclk;
reg                ta_cci0a;
reg                ta_cci0b;
reg                ta_cci1a;
reg                ta_cci1b;
reg                ta_cci2a;
reg                ta_cci2b;
wire               ta_out0;
wire               ta_out0_en;
wire               ta_out1;
wire               ta_out1_en;
wire               ta_out2;
wire               ta_out2_en;
   

reg                dco_clk;
wire               dco_enable;
wire               dco_wkup;
reg                dco_local_enable;
reg                lfxt_clk;
wire               lfxt_enable;
wire               lfxt_wkup;
reg                lfxt_local_enable;
wire               mclk;
wire               aclk;
wire               aclk_en;
wire               smclk;
wire               smclk_en;
reg                reset_n;
wire               puc_rst;
reg                nmi;
reg  [`IRQ_NR-3:0] irq;
wire [`IRQ_NR-3:0] irq_acc;
wire [`IRQ_NR-3:0] irq_in;
reg                cpu_en;
reg         [13:0] wkup;
wire        [13:0] wkup_in;
   

reg                scan_enable;
reg                scan_mode;


reg                dbg_en;
wire               dbg_freeze;
wire               dbg_uart_txd;
wire               dbg_uart_rxd;
reg                dbg_uart_rxd_sel;
reg                dbg_uart_rxd_dly;
reg                dbg_uart_rxd_pre;
reg                dbg_uart_rxd_meta;
reg         [15:0] dbg_uart_buf;
reg                dbg_uart_rx_busy;
reg                dbg_uart_tx_busy;


wire               dbg_scl;
wire               dbg_sda;
wire               dbg_scl_slave;
wire               dbg_scl_master;
reg                dbg_scl_master_sel;
reg                dbg_scl_master_dly;
reg                dbg_scl_master_pre;
reg                dbg_scl_master_meta;
wire               dbg_sda_slave_out;
wire               dbg_sda_slave_in;
wire               dbg_sda_master_out;
reg                dbg_sda_master_out_sel;
reg                dbg_sda_master_out_dly;
reg                dbg_sda_master_out_pre;
reg                dbg_sda_master_out_meta;
wire               dbg_sda_master_in;
reg         [15:0] dbg_i2c_buf;
reg     [8*32-1:0] dbg_i2c_string;


wire    [8*32-1:0] i_state;
wire    [8*32-1:0] e_state;
wire        [31:0] inst_cycle;
wire    [8*32-1:0] inst_full;
wire        [31:0] inst_number;
wire        [15:0] inst_pc;
wire    [8*32-1:0] inst_short;
   

integer            error;
reg                stimulus_done;







`include "registers.v"


`include "dbg_uart_tasks.v"
`include "dbg_i2c_tasks.v"







   



initial
  begin
     #10 $readmemh("./random_long1.mem", pmem_0.mem);

  end




initial
  begin
     dco_clk          = 1'b0;
     dco_local_enable = 1'b0;
     forever
       begin
          #25;
          dco_local_enable = (dco_enable===1) ? dco_enable : (dco_wkup===1);
          if (dco_local_enable)
            dco_clk = ~dco_clk;
       end
  end

initial
  begin
     lfxt_clk          = 1'b0;
     lfxt_local_enable = 1'b0;
     forever
       begin
          #763;
          lfxt_local_enable = (lfxt_enable===1) ? lfxt_enable : (lfxt_wkup===1);
          if (lfxt_local_enable)
            lfxt_clk = ~lfxt_clk;
       end
  end

initial
  begin
     reset_n       = 1'b1;
     #93;
     reset_n       = 1'b0;
     #593;
     reset_n       = 1'b1;
  end

initial
  begin
     error                   = 0;
     stimulus_done           = 1;
     irq                     = {`IRQ_NR-2{1'b0}};
     nmi                     = 1'b0;
     wkup                    = 14'h0000;
     cpu_en                  = 1'b1;
     dbg_en                  = 1'b0;
     dbg_uart_rxd_sel        = 1'b0;
     dbg_uart_rxd_dly        = 1'b1;
     dbg_uart_rxd_pre        = 1'b1;
     dbg_uart_rxd_meta       = 1'b0;
     dbg_uart_buf            = 16'h0000;
     dbg_uart_rx_busy        = 1'b0;
     dbg_uart_tx_busy        = 1'b0;
     dbg_scl_master_sel      = 1'b0;
     dbg_scl_master_dly      = 1'b1;
     dbg_scl_master_pre      = 1'b1;
     dbg_scl_master_meta     = 1'b0;
     dbg_sda_master_out_sel  = 1'b0;
     dbg_sda_master_out_dly  = 1'b1;
     dbg_sda_master_out_pre  = 1'b1;
     dbg_sda_master_out_meta = 1'b0;
     dbg_i2c_string          = "";
     p1_din                  = 8'h00;
     p2_din                  = 8'h00;
     p3_din                  = 8'h00;
     p4_din                  = 8'h00;
     p5_din                  = 8'h00;
     p6_din                  = 8'h00;
     inclk                   = 1'b0;
     taclk                   = 1'b0;
     ta_cci0a                = 1'b0;
     ta_cci0b                = 1'b0;
     ta_cci1a                = 1'b0;
     ta_cci1b                = 1'b0;
     ta_cci2a                = 1'b0;
     ta_cci2b                = 1'b0;
     uart_rxd                = 1'b1;
     scan_enable             = 1'b0;
     scan_mode               = 1'b0;
  end


































 





















ram #(`PMEM_MSB, `PMEM_SIZE) pmem_0 (


    .ram_dout    (pmem_dout),


    .ram_addr    (pmem_addr),
    .ram_cen     (pmem_cen),
    .ram_clk     (mclk),
    .ram_din     (pmem_din),
    .ram_wen     (pmem_wen)
);






ram #(`DMEM_MSB, `DMEM_SIZE) dmem_0 (


    .ram_dout    (dmem_dout),


    .ram_addr    (dmem_addr),
    .ram_cen     (dmem_cen),
    .ram_clk     (mclk),
    .ram_din     (dmem_din),
    .ram_wen     (dmem_wen)
);






openMSP430 dut (



    .aclk              (aclk),
    .aclk_en           (aclk_en),
    .dbg_freeze        (dbg_freeze),
    .dbg_i2c_sda_out   (dbg_sda_slave_out),
    .dbg_uart_txd      (dbg_uart_txd),
    .dco_enable        (dco_enable),
    .dco_wkup          (dco_wkup),
    .dmem_addr         (dmem_addr),
    .dmem_cen          (dmem_cen),
    .dmem_din          (dmem_din),
    .dmem_wen          (dmem_wen),
    .irq_acc           (irq_acc),
    .lfxt_enable       (lfxt_enable),
    .lfxt_wkup         (lfxt_wkup),
    .mclk              (mclk),
    .per_addr          (per_addr),
    .per_din           (per_din),
    .per_we            (per_we),
    .per_en            (per_en),
    .pmem_addr         (pmem_addr),
    .pmem_cen          (pmem_cen),
    .pmem_din          (pmem_din),
    .pmem_wen          (pmem_wen),
    .puc_rst           (puc_rst),
    .smclk             (smclk),
    .smclk_en          (smclk_en),


    .cpu_en            (cpu_en),
    .dbg_en            (dbg_en),
    .dbg_i2c_addr      (I2C_ADDR),
    .dbg_i2c_broadcast (I2C_BROADCAST),
    .dbg_i2c_scl       (dbg_scl_slave),
    .dbg_i2c_sda_in    (dbg_sda_slave_in),
    .dbg_uart_rxd      (dbg_uart_rxd),
    .dco_clk           (dco_clk),
    .dmem_dout         (dmem_dout),
    .irq               (irq_in),
    .lfxt_clk          (lfxt_clk),
    .nmi               (nmi),
    .per_dout          (per_dout),
    .pmem_dout         (pmem_dout),
    .reset_n           (reset_n),
    .scan_enable       (scan_enable),
    .scan_mode         (scan_mode),
    .wkup              (|wkup_in)
);





`ifdef CVER
omsp_gpio #(1,
            1,
            1,
            1,
            1,
            1)         gpio_0 (
`else
omsp_gpio #(.P1_EN(1),
            .P2_EN(1),
            .P3_EN(1),
            .P4_EN(1),
            .P5_EN(1),
            .P6_EN(1)) gpio_0 (
`endif


    .irq_port1    (irq_port1),
    .irq_port2    (irq_port2),
    .p1_dout      (p1_dout),
    .p1_dout_en   (p1_dout_en),
    .p1_sel       (p1_sel),
    .p2_dout      (p2_dout),
    .p2_dout_en   (p2_dout_en),
    .p2_sel       (p2_sel),
    .p3_dout      (p3_dout),
    .p3_dout_en   (p3_dout_en),
    .p3_sel       (p3_sel),
    .p4_dout      (p4_dout),
    .p4_dout_en   (p4_dout_en),
    .p4_sel       (p4_sel),
    .p5_dout      (p5_dout),
    .p5_dout_en   (p5_dout_en),
    .p5_sel       (p5_sel),
    .p6_dout      (p6_dout),
    .p6_dout_en   (p6_dout_en),
    .p6_sel       (p6_sel),
    .per_dout     (per_dout_dio),
                             

    .mclk         (mclk),
    .p1_din       (p1_din),
    .p2_din       (p2_din),
    .p3_din       (p3_din),
    .p4_din       (p4_din),
    .p5_din       (p5_din),
    .p6_din       (p6_din),
    .per_addr     (per_addr),
    .per_din      (per_din),
    .per_en       (per_en),
    .per_we       (per_we),
    .puc_rst      (puc_rst)
);





omsp_timerA timerA_0 (


    .irq_ta0      (irq_ta0),
    .irq_ta1      (irq_ta1),
    .per_dout     (per_dout_timerA),
    .ta_out0      (ta_out0),
    .ta_out0_en   (ta_out0_en),
    .ta_out1      (ta_out1),
    .ta_out1_en   (ta_out1_en),
    .ta_out2      (ta_out2),
    .ta_out2_en   (ta_out2_en),


    .aclk_en      (aclk_en),
    .dbg_freeze   (dbg_freeze),
    .inclk        (inclk),
    .irq_ta0_acc  (irq_acc[`IRQ_NR-7]),
    .mclk         (mclk),
    .per_addr     (per_addr),
    .per_din      (per_din),
    .per_en       (per_en),
    .per_we       (per_we),
    .puc_rst      (puc_rst),
    .smclk_en     (smclk_en),
    .ta_cci0a     (ta_cci0a),
    .ta_cci0b     (ta_cci0b),
    .ta_cci1a     (ta_cci1a),
    .ta_cci1b     (ta_cci1b),
    .ta_cci2a     (ta_cci2a),
    .ta_cci2b     (ta_cci2b),
    .taclk        (taclk)
);
   



`ifdef READY_FOR_PRIMETIME
omsp_uart #(.BASE_ADDR(15'h0080)) uart_0 (


    .irq_uart_rx  (irq_uart_rx),
    .irq_uart_tx  (irq_uart_tx),
    .per_dout     (per_dout_uart),
    .uart_txd     (uart_txd),


    .mclk         (mclk),
    .per_addr     (per_addr),
    .per_din      (per_din),
    .per_en       (per_en),
    .per_we       (per_we),
    .puc_rst      (puc_rst),
    .smclk_en     (smclk_en),
    .uart_rxd     (uart_rxd)
);
`else
    assign irq_uart_rx   =  1'b0;
    assign irq_uart_tx   =  1'b0;
    assign per_dout_uart = 16'h0000;
    assign uart_txd      =  1'b0;
`endif





template_periph_8b template_periph_8b_0 (


    .per_dout     (per_dout_temp_8b),


    .mclk         (mclk),
    .per_addr     (per_addr),
    .per_din      (per_din),
    .per_en       (per_en),
    .per_we       (per_we),
    .puc_rst      (puc_rst)
);

`ifdef CVER
template_periph_16b #(15'h0190)             template_periph_16b_0 (
`else
template_periph_16b #(.BASE_ADDR((15'd`PER_SIZE-15'h0070) & 15'h7ff8)) template_periph_16b_0 (
`endif

    .per_dout     (per_dout_temp_16b),


    .mclk         (mclk),
    .per_addr     (per_addr),
    .per_din      (per_din),
    .per_en       (per_en),
    .per_we       (per_we),
    .puc_rst      (puc_rst)
);






assign per_dout = per_dout_dio       |
                  per_dout_timerA    |
                  per_dout_uart      |
                  per_dout_temp_8b   |
                  per_dout_temp_16b;






assign irq_in  = irq  | {1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         irq_ta0,
                         irq_ta1,
                         irq_uart_rx,
                         irq_uart_tx,
                         1'b0,
                         1'b0,
                         irq_port2,
                         irq_port1,
                         1'b0,
                         {`IRQ_NR-15{1'b0}}};

assign wkup_in = wkup | {1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0};








pullup dbg_scl_inst (dbg_scl); 
pullup dbg_sda_inst (dbg_sda); 



io_cell scl_slave_inst (
  .pad         (dbg_scl),
  .data_in     (dbg_scl_slave),
  .data_out_en (1'b0),
  .data_out    (1'b0)
);
                                                           
io_cell sda_slave_inst (
  .pad         (dbg_sda),
  .data_in     (dbg_sda_slave_in),
  .data_out_en (!dbg_sda_slave_out),
  .data_out    (1'b0)
);



io_cell scl_master_inst (
  .pad         (dbg_scl),
  .data_in     (),
  .data_out_en (!dbg_scl_master),
  .data_out    (1'b0)
);
                                                                   
io_cell sda_master_inst (
  .pad         (dbg_sda),
  .data_in     (dbg_sda_master_in),
  .data_out_en (!dbg_sda_master_out),
  .data_out    (1'b0)
);





msp_debug msp_debug_0 (


    .e_state      (e_state),
    .i_state      (i_state),
    .inst_cycle   (inst_cycle),
    .inst_full    (inst_full),
    .inst_number  (inst_number),
    .inst_pc      (inst_pc),
    .inst_short   (inst_short),


    .mclk         (mclk),
    .puc_rst      (puc_rst)
);





initial
  begin
   `ifdef NODUMP
   `else
     `ifdef VPD_FILE
        $vcdplusfile("tb_openMSP430.vpd");
        $vcdpluson();
     `else
       `ifdef TRN_FILE
          $recordfile ("tb_openMSP430.trn");
          $recordvars;
       `else
          $dumpfile("tb_openMSP430.vcd");
          $dumpvars(0, tb_openMSP430);
       `endif
     `endif
   `endif
  end





initial
  begin
   `ifdef NO_TIMEOUT
   `else
     `ifdef VERY_LONG_TIMEOUT
       #500000000;
     `else     
     `ifdef LONG_TIMEOUT
       #5000000;
     `else     
       #500000;
     `endif
     `endif
       $display(" ===============================================");
       $display("|               SIMULATION FAILED               |");
       $display("|              (simulation Timeout)             |");
       $display(" ===============================================");
       $finish;
   `endif
  end

initial
  begin
     @(negedge stimulus_done);
     wait(inst_pc=='hffff);
     
     $display(" ===============================================");
     if (error!=0)
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|     (some verilog stimulus checks failed)     |");
       end
     else if (~stimulus_done)
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|     (the verilog stimulus didn't complete)    |");
       end
     else 
       begin
          $display("|               SIMULATION PASSED               |");
       end
     $display(" ===============================================");
     $finish;
  end






   task tb_error;
      input [65*8:0] error_string;
      begin
         $display("ERROR: %s %t", error_string, $time);
         error = error+1;
      end
   endtask


endmodule
module  tb_openMSP430;







wire [`DMEM_MSB:0] dmem_addr;
wire               dmem_cen;
wire        [15:0] dmem_din;
wire         [1:0] dmem_wen;
wire        [15:0] dmem_dout;


wire [`PMEM_MSB:0] pmem_addr;
wire               pmem_cen;
wire        [15:0] pmem_din;
wire         [1:0] pmem_wen;
wire        [15:0] pmem_dout;


wire        [13:0] per_addr;
wire        [15:0] per_din;
wire        [15:0] per_dout;
wire         [1:0] per_we;
wire               per_en;


wire               irq_port1;
wire               irq_port2;
wire        [15:0] per_dout_dio;
wire         [7:0] p1_dout;
wire         [7:0] p1_dout_en;
wire         [7:0] p1_sel;
wire         [7:0] p2_dout;
wire         [7:0] p2_dout_en;
wire         [7:0] p2_sel;
wire         [7:0] p3_dout;
wire         [7:0] p3_dout_en;
wire         [7:0] p3_sel;
wire         [7:0] p4_dout;
wire         [7:0] p4_dout_en;
wire         [7:0] p4_sel;
wire         [7:0] p5_dout;
wire         [7:0] p5_dout_en;
wire         [7:0] p5_sel;
wire         [7:0] p6_dout;
wire         [7:0] p6_dout_en;
wire         [7:0] p6_sel;
reg          [7:0] p1_din;
reg          [7:0] p2_din;
reg          [7:0] p3_din;
reg          [7:0] p4_din;
reg          [7:0] p5_din;
reg          [7:0] p6_din;


wire        [15:0] per_dout_temp_8b;
wire        [15:0] per_dout_temp_16b;


wire        [15:0] per_dout_uart;
wire               irq_uart_rx;
wire               irq_uart_tx;
wire               uart_txd;
reg                uart_rxd;


wire               irq_ta0;
wire               irq_ta1;
wire        [15:0] per_dout_timerA;
reg                inclk;
reg                taclk;
reg                ta_cci0a;
reg                ta_cci0b;
reg                ta_cci1a;
reg                ta_cci1b;
reg                ta_cci2a;
reg                ta_cci2b;
wire               ta_out0;
wire               ta_out0_en;
wire               ta_out1;
wire               ta_out1_en;
wire               ta_out2;
wire               ta_out2_en;
   

reg                dco_clk;
wire               dco_enable;
wire               dco_wkup;
reg                dco_local_enable;
reg                lfxt_clk;
wire               lfxt_enable;
wire               lfxt_wkup;
reg                lfxt_local_enable;
wire               mclk;
wire               aclk;
wire               aclk_en;
wire               smclk;
wire               smclk_en;
reg                reset_n;
wire               puc_rst;
reg                nmi;
reg  [`IRQ_NR-3:0] irq;
wire [`IRQ_NR-3:0] irq_acc;
wire [`IRQ_NR-3:0] irq_in;
reg                cpu_en;
reg         [13:0] wkup;
wire        [13:0] wkup_in;
   

reg                scan_enable;
reg                scan_mode;


reg                dbg_en;
wire               dbg_freeze;
wire               dbg_uart_txd;
wire               dbg_uart_rxd;
reg                dbg_uart_rxd_sel;
reg                dbg_uart_rxd_dly;
reg                dbg_uart_rxd_pre;
reg                dbg_uart_rxd_meta;
reg         [15:0] dbg_uart_buf;
reg                dbg_uart_rx_busy;
reg                dbg_uart_tx_busy;


wire               dbg_scl;
wire               dbg_sda;
wire               dbg_scl_slave;
wire               dbg_scl_master;
reg                dbg_scl_master_sel;
reg                dbg_scl_master_dly;
reg                dbg_scl_master_pre;
reg                dbg_scl_master_meta;
wire               dbg_sda_slave_out;
wire               dbg_sda_slave_in;
wire               dbg_sda_master_out;
reg                dbg_sda_master_out_sel;
reg                dbg_sda_master_out_dly;
reg                dbg_sda_master_out_pre;
reg                dbg_sda_master_out_meta;
wire               dbg_sda_master_in;
reg         [15:0] dbg_i2c_buf;
reg     [8*32-1:0] dbg_i2c_string;


wire    [8*32-1:0] i_state;
wire    [8*32-1:0] e_state;
wire        [31:0] inst_cycle;
wire    [8*32-1:0] inst_full;
wire        [31:0] inst_number;
wire        [15:0] inst_pc;
wire    [8*32-1:0] inst_short;
   

integer            error;
reg                stimulus_done;







`include "registers.v"


`include "dbg_uart_tasks.v"
`include "dbg_i2c_tasks.v"







   



initial
  begin
     #10 $readmemh("./random_long1.mem", pmem_0.mem);

  end




initial
  begin
     dco_clk          = 1'b0;
     dco_local_enable = 1'b0;
     forever
       begin
          #25;
          dco_local_enable = (dco_enable===1) ? dco_enable : (dco_wkup===1);
          if (dco_local_enable)
            dco_clk = ~dco_clk;
       end
  end

initial
  begin
     lfxt_clk          = 1'b0;
     lfxt_local_enable = 1'b0;
     forever
       begin
          #763;
          lfxt_local_enable = (lfxt_enable===1) ? lfxt_enable : (lfxt_wkup===1);
          if (lfxt_local_enable)
            lfxt_clk = ~lfxt_clk;
       end
  end

initial
  begin
     reset_n       = 1'b1;
     #93;
     reset_n       = 1'b0;
     #593;
     reset_n       = 1'b1;
  end

initial
  begin
     error                   = 0;
     stimulus_done           = 1;
     irq                     = {`IRQ_NR-2{1'b0}};
     nmi                     = 1'b0;
     wkup                    = 14'h0000;
     cpu_en                  = 1'b1;
     dbg_en                  = 1'b0;
     dbg_uart_rxd_sel        = 1'b0;
     dbg_uart_rxd_dly        = 1'b1;
     dbg_uart_rxd_pre        = 1'b1;
     dbg_uart_rxd_meta       = 1'b0;
     dbg_uart_buf            = 16'h0000;
     dbg_uart_rx_busy        = 1'b0;
     dbg_uart_tx_busy        = 1'b0;
     dbg_scl_master_sel      = 1'b0;
     dbg_scl_master_dly      = 1'b1;
     dbg_scl_master_pre      = 1'b1;
     dbg_scl_master_meta     = 1'b0;
     dbg_sda_master_out_sel  = 1'b0;
     dbg_sda_master_out_dly  = 1'b1;
     dbg_sda_master_out_pre  = 1'b1;
     dbg_sda_master_out_meta = 1'b0;
     dbg_i2c_string          = "";
     p1_din                  = 8'h00;
     p2_din                  = 8'h00;
     p3_din                  = 8'h00;
     p4_din                  = 8'h00;
     p5_din                  = 8'h00;
     p6_din                  = 8'h00;
     inclk                   = 1'b0;
     taclk                   = 1'b0;
     ta_cci0a                = 1'b0;
     ta_cci0b                = 1'b0;
     ta_cci1a                = 1'b0;
     ta_cci1b                = 1'b0;
     ta_cci2a                = 1'b0;
     ta_cci2b                = 1'b0;
     uart_rxd                = 1'b1;
     scan_enable             = 1'b0;
     scan_mode               = 1'b0;
  end


































 





















ram #(`PMEM_MSB, `PMEM_SIZE) pmem_0 (


    .ram_dout    (pmem_dout),


    .ram_addr    (pmem_addr),
    .ram_cen     (pmem_cen),
    .ram_clk     (mclk),
    .ram_din     (pmem_din),
    .ram_wen     (pmem_wen)
);






ram #(`DMEM_MSB, `DMEM_SIZE) dmem_0 (


    .ram_dout    (dmem_dout),


    .ram_addr    (dmem_addr),
    .ram_cen     (dmem_cen),
    .ram_clk     (mclk),
    .ram_din     (dmem_din),
    .ram_wen     (dmem_wen)
);






openMSP430 dut (



    .aclk              (aclk),
    .aclk_en           (aclk_en),
    .dbg_freeze        (dbg_freeze),
    .dbg_i2c_sda_out   (dbg_sda_slave_out),
    .dbg_uart_txd      (dbg_uart_txd),
    .dco_enable        (dco_enable),
    .dco_wkup          (dco_wkup),
    .dmem_addr         (dmem_addr),
    .dmem_cen          (dmem_cen),
    .dmem_din          (dmem_din),
    .dmem_wen          (dmem_wen),
    .irq_acc           (irq_acc),
    .lfxt_enable       (lfxt_enable),
    .lfxt_wkup         (lfxt_wkup),
    .mclk              (mclk),
    .per_addr          (per_addr),
    .per_din           (per_din),
    .per_we            (per_we),
    .per_en            (per_en),
    .pmem_addr         (pmem_addr),
    .pmem_cen          (pmem_cen),
    .pmem_din          (pmem_din),
    .pmem_wen          (pmem_wen),
    .puc_rst           (puc_rst),
    .smclk             (smclk),
    .smclk_en          (smclk_en),


    .cpu_en            (cpu_en),
    .dbg_en            (dbg_en),
    .dbg_i2c_addr      (I2C_ADDR),
    .dbg_i2c_broadcast (I2C_BROADCAST),
    .dbg_i2c_scl       (dbg_scl_slave),
    .dbg_i2c_sda_in    (dbg_sda_slave_in),
    .dbg_uart_rxd      (dbg_uart_rxd),
    .dco_clk           (dco_clk),
    .dmem_dout         (dmem_dout),
    .irq               (irq_in),
    .lfxt_clk          (lfxt_clk),
    .nmi               (nmi),
    .per_dout          (per_dout),
    .pmem_dout         (pmem_dout),
    .reset_n           (reset_n),
    .scan_enable       (scan_enable),
    .scan_mode         (scan_mode),
    .wkup              (|wkup_in)
);





`ifdef CVER
omsp_gpio #(1,
            1,
            1,
            1,
            1,
            1)         gpio_0 (
`else
omsp_gpio #(.P1_EN(1),
            .P2_EN(1),
            .P3_EN(1),
            .P4_EN(1),
            .P5_EN(1),
            .P6_EN(1)) gpio_0 (
`endif


    .irq_port1    (irq_port1),
    .irq_port2    (irq_port2),
    .p1_dout      (p1_dout),
    .p1_dout_en   (p1_dout_en),
    .p1_sel       (p1_sel),
    .p2_dout      (p2_dout),
    .p2_dout_en   (p2_dout_en),
    .p2_sel       (p2_sel),
    .p3_dout      (p3_dout),
    .p3_dout_en   (p3_dout_en),
    .p3_sel       (p3_sel),
    .p4_dout      (p4_dout),
    .p4_dout_en   (p4_dout_en),
    .p4_sel       (p4_sel),
    .p5_dout      (p5_dout),
    .p5_dout_en   (p5_dout_en),
    .p5_sel       (p5_sel),
    .p6_dout      (p6_dout),
    .p6_dout_en   (p6_dout_en),
    .p6_sel       (p6_sel),
    .per_dout     (per_dout_dio),
                             

    .mclk         (mclk),
    .p1_din       (p1_din),
    .p2_din       (p2_din),
    .p3_din       (p3_din),
    .p4_din       (p4_din),
    .p5_din       (p5_din),
    .p6_din       (p6_din),
    .per_addr     (per_addr),
    .per_din      (per_din),
    .per_en       (per_en),
    .per_we       (per_we),
    .puc_rst      (puc_rst)
);





omsp_timerA timerA_0 (


    .irq_ta0      (irq_ta0),
    .irq_ta1      (irq_ta1),
    .per_dout     (per_dout_timerA),
    .ta_out0      (ta_out0),
    .ta_out0_en   (ta_out0_en),
    .ta_out1      (ta_out1),
    .ta_out1_en   (ta_out1_en),
    .ta_out2      (ta_out2),
    .ta_out2_en   (ta_out2_en),


    .aclk_en      (aclk_en),
    .dbg_freeze   (dbg_freeze),
    .inclk        (inclk),
    .irq_ta0_acc  (irq_acc[`IRQ_NR-7]),
    .mclk         (mclk),
    .per_addr     (per_addr),
    .per_din      (per_din),
    .per_en       (per_en),
    .per_we       (per_we),
    .puc_rst      (puc_rst),
    .smclk_en     (smclk_en),
    .ta_cci0a     (ta_cci0a),
    .ta_cci0b     (ta_cci0b),
    .ta_cci1a     (ta_cci1a),
    .ta_cci1b     (ta_cci1b),
    .ta_cci2a     (ta_cci2a),
    .ta_cci2b     (ta_cci2b),
    .taclk        (taclk)
);
   



`ifdef READY_FOR_PRIMETIME
omsp_uart #(.BASE_ADDR(15'h0080)) uart_0 (


    .irq_uart_rx  (irq_uart_rx),
    .irq_uart_tx  (irq_uart_tx),
    .per_dout     (per_dout_uart),
    .uart_txd     (uart_txd),


    .mclk         (mclk),
    .per_addr     (per_addr),
    .per_din      (per_din),
    .per_en       (per_en),
    .per_we       (per_we),
    .puc_rst      (puc_rst),
    .smclk_en     (smclk_en),
    .uart_rxd     (uart_rxd)
);
`else
    assign irq_uart_rx   =  1'b0;
    assign irq_uart_tx   =  1'b0;
    assign per_dout_uart = 16'h0000;
    assign uart_txd      =  1'b0;
`endif





template_periph_8b template_periph_8b_0 (


    .per_dout     (per_dout_temp_8b),


    .mclk         (mclk),
    .per_addr     (per_addr),
    .per_din      (per_din),
    .per_en       (per_en),
    .per_we       (per_we),
    .puc_rst      (puc_rst)
);

`ifdef CVER
template_periph_16b #(15'h0190)             template_periph_16b_0 (
`else
template_periph_16b #(.BASE_ADDR((15'd`PER_SIZE-15'h0070) & 15'h7ff8)) template_periph_16b_0 (
`endif

    .per_dout     (per_dout_temp_16b),


    .mclk         (mclk),
    .per_addr     (per_addr),
    .per_din      (per_din),
    .per_en       (per_en),
    .per_we       (per_we),
    .puc_rst      (puc_rst)
);






assign per_dout = per_dout_dio       |
                  per_dout_timerA    |
                  per_dout_uart      |
                  per_dout_temp_8b   |
                  per_dout_temp_16b;






assign irq_in  = irq  | {1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         irq_ta0,
                         irq_ta1,
                         irq_uart_rx,
                         irq_uart_tx,
                         1'b0,
                         1'b0,
                         irq_port2,
                         irq_port1,
                         1'b0,
                         {`IRQ_NR-15{1'b0}}};

assign wkup_in = wkup | {1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0,
                         1'b0};








pullup dbg_scl_inst (dbg_scl); 
pullup dbg_sda_inst (dbg_sda); 



io_cell scl_slave_inst (
  .pad         (dbg_scl),
  .data_in     (dbg_scl_slave),
  .data_out_en (1'b0),
  .data_out    (1'b0)
);
                                                           
io_cell sda_slave_inst (
  .pad         (dbg_sda),
  .data_in     (dbg_sda_slave_in),
  .data_out_en (!dbg_sda_slave_out),
  .data_out    (1'b0)
);



io_cell scl_master_inst (
  .pad         (dbg_scl),
  .data_in     (),
  .data_out_en (!dbg_scl_master),
  .data_out    (1'b0)
);
                                                                   
io_cell sda_master_inst (
  .pad         (dbg_sda),
  .data_in     (dbg_sda_master_in),
  .data_out_en (!dbg_sda_master_out),
  .data_out    (1'b0)
);





msp_debug msp_debug_0 (


    .e_state      (e_state),
    .i_state      (i_state),
    .inst_cycle   (inst_cycle),
    .inst_full    (inst_full),
    .inst_number  (inst_number),
    .inst_pc      (inst_pc),
    .inst_short   (inst_short),


    .mclk         (mclk),
    .puc_rst      (puc_rst)
);





initial
  begin
   `ifdef NODUMP
   `else
     `ifdef VPD_FILE
        $vcdplusfile("tb_openMSP430.vpd");
        $vcdpluson();
     `else
       `ifdef TRN_FILE
          $recordfile ("tb_openMSP430.trn");
          $recordvars;
       `else
          $dumpfile("tb_openMSP430.vcd");
          $dumpvars(0, tb_openMSP430);
       `endif
     `endif
   `endif
  end





initial
  begin
   `ifdef NO_TIMEOUT
   `else
     `ifdef VERY_LONG_TIMEOUT
       #500000000;
     `else     
     `ifdef LONG_TIMEOUT
       #5000000;
     `else     
       #500000;
     `endif
     `endif
       $display(" ===============================================");
       $display("|               SIMULATION FAILED               |");
       $display("|              (simulation Timeout)             |");
       $display(" ===============================================");
       $finish;
   `endif
  end

initial
  begin
     @(negedge stimulus_done);
     wait(inst_pc=='hffff);
     
     $display(" ===============================================");
     if (error!=0)
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|     (some verilog stimulus checks failed)     |");
       end
     else if (~stimulus_done)
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|     (the verilog stimulus didn't complete)    |");
       end
     else 
       begin
          $display("|               SIMULATION PASSED               |");
       end
     $display(" ===============================================");
     $finish;
  end






   task tb_error;
      input [65*8:0] error_string;
      begin
         $display("ERROR: %s %t", error_string, $time);
         error = error+1;
      end
   endtask


endmodule