data/full_repos/permissive/181415525/danmaku_de2/dvi_input/sim/scdt_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/181415525/danmaku_de2/dvi_input/sim/scdt_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n#10 rst=1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/181415525/danmaku_de2/dvi_input/sim/scdt_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n#40000 inactive=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/181415525/danmaku_de2/dvi_input/sim/scdt_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #1600 de=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181415525/danmaku_de2/dvi_input/sim/scdt_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #1600 de=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/181415525/danmaku_de2/dvi_input/sim/scdt_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #1 odck = ~odck;\n    ^\n%Error: data/full_repos/permissive/181415525/danmaku_de2/dvi_input/sim/scdt_test.v:10: Cannot find file containing module: \'tfp401a\'\ntfp401a tfp401a_inst(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181415525/danmaku_de2/dvi_input/sim,data/full_repos/permissive/181415525/tfp401a\n             data/full_repos/permissive/181415525/danmaku_de2/dvi_input/sim,data/full_repos/permissive/181415525/tfp401a.v\n             data/full_repos/permissive/181415525/danmaku_de2/dvi_input/sim,data/full_repos/permissive/181415525/tfp401a.sv\n             tfp401a\n             tfp401a.v\n             tfp401a.sv\n             obj_dir/tfp401a\n             obj_dir/tfp401a.v\n             obj_dir/tfp401a.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module scdt_test(

);

wire scdt;
reg de,odck,rst;

tfp401a tfp401a_inst(
    .rst(rst),
    .odck_in(odck),
    .de_in(de),
    .scdt_o(scdt)
);

reg inactive;
initial begin
rst=0;
odck=0;
de=0;
inactive=0;
#10 rst=1;
#40000 inactive=1;
end

always begin
    if(!inactive) begin
        #1600 de=1;
        #1600 de=0;
    end
end

always begin
    #1 odck = ~odck;
end
endmodule
module scdt_test(

);


wire scdt;
reg de,odck,rst;

tfp401a tfp401a_inst(
    .rst(rst),
    .odck_in(odck),
    .de_in(de),
    .scdt_o(scdt)
);

reg inactive;
initial begin
rst=0;
odck=0;
de=0;
inactive=0;
#10 rst=1;
#40000 inactive=1;
end

always begin
    if(!inactive) begin
        #1600 de=1;
        #1600 de=0;
    end
end

always begin
    #1 odck = ~odck;
end
endmodule