data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite.v
1: b'%Warning-WIDTH: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite.v:47: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'counter\' generates 11 bits.\n                                                                                       : ... In instance PCA24S08A_bytewrite\nassign i2c_start = (~flag) ? bytewrite_start : (counter == DIV * 19);\n                                                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/206783267/I2C/CNTLR/PCA24S08A_bytewrite.v:57: Cannot find file containing module: \'i2c_master\'\ni2c_master\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206783267/I2C/CNTLR,data/full_repos/permissive/206783267/i2c_master\n             data/full_repos/permissive/206783267/I2C/CNTLR,data/full_repos/permissive/206783267/i2c_master.v\n             data/full_repos/permissive/206783267/I2C/CNTLR,data/full_repos/permissive/206783267/i2c_master.sv\n             i2c_master\n             i2c_master.v\n             i2c_master.sv\n             obj_dir/i2c_master\n             obj_dir/i2c_master.v\n             obj_dir/i2c_master.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module PCA24S08A_bytewrite
#(
	parameter	CLK_FREQ = 50_000_000,
				I2C_FREQ = 500_000
)
(
	input	clk, arstn,
	input	bytewrite_start,
	input	[2:0]	block_num, page_num,
	input	[3:0]	byte_addr,
	input	[7:0]	data_write,
	output	bytewrite_done,

	inout	sda,
	output	scl
);

parameter DIV = CLK_FREQ / I2C_FREQ;

reg	flag;
reg	[10:0]	counter;

wire	i2c_start;
wire	[6:0]	addr;
wire	rw;
wire	[7:0]	data_send;
wire	i2c_done;

always@(posedge clk or negedge arstn) begin
	if(~arstn)
		flag <= 1'b0;
	else if(i2c_start) begin
		flag <= ~flag;
	end
end

always@(posedge clk or negedge arstn) begin
	if(~arstn)
		counter <= 'd0;
	else if(flag) begin
		counter <= counter + 1'b1;
	end
end

assign i2c_start = (~flag) ? bytewrite_start : (counter == DIV * 19);

assign addr = {5'b10101, block_num[2:1]};

assign rw = 1'b0;

assign data_send = (flag) ? {block_num[0], page_num, byte_addr} : data_write;

assign bytewrite_done = i2c_done;

i2c_master
#(
	.CLK_FREQ(CLK_FREQ),
	.I2C_FREQ(I2C_FREQ)
)
i2c_ctrl(
	.clk(clk),
	.arstn(arstn),
	.i2c_start(i2c_start),
	.addr(addr),
	.rw(rw),
	.data_send(data_send),
	.i2c_done(i2c_done),
	.data_recv(),
	.data_recv_done(),
	.sda(sda),
	.scl(scl)
);

endmodule
module PCA24S08A_bytewrite
#(
	parameter	CLK_FREQ = 50_000_000,
				I2C_FREQ = 500_000
)
(
	input	clk, arstn,
	input	bytewrite_start,
	input	[2:0]	block_num, page_num,
	input	[3:0]	byte_addr,
	input	[7:0]	data_write,
	output	bytewrite_done,

	inout	sda,
	output	scl
);


parameter DIV = CLK_FREQ / I2C_FREQ;

reg	flag;
reg	[10:0]	counter;

wire	i2c_start;
wire	[6:0]	addr;
wire	rw;
wire	[7:0]	data_send;
wire	i2c_done;

always@(posedge clk or negedge arstn) begin
	if(~arstn)
		flag <= 1'b0;
	else if(i2c_start) begin
		flag <= ~flag;
	end
end

always@(posedge clk or negedge arstn) begin
	if(~arstn)
		counter <= 'd0;
	else if(flag) begin
		counter <= counter + 1'b1;
	end
end

assign i2c_start = (~flag) ? bytewrite_start : (counter == DIV * 19);

assign addr = {5'b10101, block_num[2:1]};

assign rw = 1'b0;

assign data_send = (flag) ? {block_num[0], page_num, byte_addr} : data_write;

assign bytewrite_done = i2c_done;

i2c_master
#(
	.CLK_FREQ(CLK_FREQ),
	.I2C_FREQ(I2C_FREQ)
)
i2c_ctrl(
	.clk(clk),
	.arstn(arstn),
	.i2c_start(i2c_start),
	.addr(addr),
	.rw(rw),
	.data_send(data_send),
	.i2c_done(i2c_done),
	.data_recv(),
	.data_recv_done(),
	.sda(sda),
	.scl(scl)
);

endmodule