data/full_repos/permissive/2084115/rtl/library/jelly_signal_transfer.v
1: b"%Error: data/full_repos/permissive/2084115/rtl/library/jelly_signal_transfer.v:38: Cannot find file containing module: 'jelly_signal_transfer_async'\n        jelly_signal_transfer_async\n        ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/library,data/full_repos/permissive/2084115/jelly_signal_transfer_async\n             data/full_repos/permissive/2084115/rtl/library,data/full_repos/permissive/2084115/jelly_signal_transfer_async.v\n             data/full_repos/permissive/2084115/rtl/library,data/full_repos/permissive/2084115/jelly_signal_transfer_async.sv\n             jelly_signal_transfer_async\n             jelly_signal_transfer_async.v\n             jelly_signal_transfer_async.sv\n             obj_dir/jelly_signal_transfer_async\n             obj_dir/jelly_signal_transfer_async.v\n             obj_dir/jelly_signal_transfer_async.sv\n%Error: Exiting due to 1 error(s)\n"
module jelly_signal_transfer
        #(
            parameter ASYNC          = 1,
            parameter PTR_WIDTH      = 6,
            parameter CAPACITY_WIDTH = 8
        )
        (
            input   wire    s_reset,
            input   wire    s_clk,
            input   wire    s_valid,
            
            input   wire    m_reset,
            input   wire    m_clk,
            output  wire    m_valid,
            input   wire    m_ready
        );
    
    
    generate
    if ( ASYNC ) begin : blk_async
        jelly_signal_transfer_async
                #(
                    .PTR_WIDTH      (PTR_WIDTH),
                    .CAPACITY_WIDTH (CAPACITY_WIDTH)
                )
            i_signal_transfer_async
                (
                    .s_reset        (s_reset),
                    .s_clk          (s_clk),
                    .s_valid        (s_valid),
                    
                    .m_reset        (m_reset),
                    .m_clk          (m_clk),
                    .m_valid        (m_valid),
                    .m_ready        (m_ready)
                );
    end
    else begin : blk_sync
        jelly_signal_transfer_sync
                #(
                    .CAPACITY_WIDTH (CAPACITY_WIDTH)
                )
            i_signal_transfer_sync
                (
                    .reset          (s_reset),
                    .clk            (s_clk),
                    .s_valid        (s_valid),
                    
                    .m_valid        (m_valid),
                    .m_ready        (m_ready)
                );
    end
    endgenerate
endmodule
module jelly_signal_transfer
        #(
            parameter ASYNC          = 1,
            parameter PTR_WIDTH      = 6,
            parameter CAPACITY_WIDTH = 8
        )
        (
            input   wire    s_reset,
            input   wire    s_clk,
            input   wire    s_valid,
            
            input   wire    m_reset,
            input   wire    m_clk,
            output  wire    m_valid,
            input   wire    m_ready
        );

    
    
    generate
    if ( ASYNC ) begin : blk_async
        jelly_signal_transfer_async
                #(
                    .PTR_WIDTH      (PTR_WIDTH),
                    .CAPACITY_WIDTH (CAPACITY_WIDTH)
                )
            i_signal_transfer_async
                (
                    .s_reset        (s_reset),
                    .s_clk          (s_clk),
                    .s_valid        (s_valid),
                    
                    .m_reset        (m_reset),
                    .m_clk          (m_clk),
                    .m_valid        (m_valid),
                    .m_ready        (m_ready)
                );
    end
    else begin : blk_sync
        jelly_signal_transfer_sync
                #(
                    .CAPACITY_WIDTH (CAPACITY_WIDTH)
                )
            i_signal_transfer_sync
                (
                    .reset          (s_reset),
                    .clk            (s_clk),
                    .s_valid        (s_valid),
                    
                    .m_valid        (m_valid),
                    .m_ready        (m_ready)
                );
    end
    endgenerate
endmodule