data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag/jtag_dmi_if.v
1: b"%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag/jtag_dmi_if.v:60: Cannot find file containing module: 'BSCANE2'\nBSCANE2 #(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag,data/full_repos/permissive/125344718/BSCANE2\n             data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag,data/full_repos/permissive/125344718/BSCANE2.v\n             data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag,data/full_repos/permissive/125344718/BSCANE2.sv\n             BSCANE2\n             BSCANE2.v\n             BSCANE2.sv\n             obj_dir/BSCANE2\n             obj_dir/BSCANE2.v\n             obj_dir/BSCANE2.sv\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag/jtag_dmi_if.v:86: Cannot find file containing module: 'jtag_dmi_dsif'\njtag_dmi_dsif jtag_dmi_dsif(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag/jtag_dmi_if.v:111: Cannot find file containing module: 'jtag_dmi_intc'\njtag_dmi_intc jtag_dmi_intc (\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module jtag_dmi_if#(
    parameter JTAG_CHAIN = 4,
    parameter DMI_ADDR_WIDTH = 7,
    parameter DMI_DATA_WIDTH = 32,
    parameter DMI_OP_WIDTH = 2,
    parameter JTAG_DATA_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH),
    parameter TX_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH),
    parameter RX_WIDTH = (DMI_DATA_WIDTH+DMI_OP_WIDTH)
)(


    output creq_vld,
    output [TX_WIDTH-1:0] creq_data,
    input creq_rdy,
    input cresp_vld,
    input [RX_WIDTH-1:0] cresp_data,
    output cresp_rdy,

    input reset,
    input clock
);

wire jreq_vld;
wire [TX_WIDTH-1:0] jreq_data;
wire jreq_rdy;
wire jresp_vld;
wire [RX_WIDTH-1:0] jresp_data;
wire jresp_rdy;









wire jcapture;
wire jreset;
wire jshift;
wire jupdate;
wire jtdo;
wire jtdi;
wire jtms;
wire jsel; 


wire xcapture;
wire xreset;
wire xshift;
wire xupdate;
wire xsel;
wire xtdo;
wire xtdi;
wire xtck;
wire xtms;

BSCANE2 #(
    .JTAG_CHAIN(JTAG_CHAIN)
)
bse2_inst (
    .CAPTURE(xcapture),
    .DRCK(),
    .RESET(xreset),
    .RUNTEST(),
    .SEL(xsel),
    .SHIFT(xshift),
    .TCK(xtck),
    .TDI(xtdi),
    .TMS(xtms),
    .UPDATE(xupdate),
    .TDO(xtdo)
);

assign jcapture = xcapture;
assign jreset = xreset;
assign jshift = xshift;
assign jupdate = xupdate;
assign xtdo = jtdo;
assign jtdi = xtdi;
assign jtms = xtms;
assign jsel = xsel;

jtag_dmi_dsif jtag_dmi_dsif(

    .jclk(xtck),
    

    .jcapture(jcapture),
    .jreset(jreset),
    .jshift(jshift),
    .jupdate(jupdate),
    .jtdo(jtdo),
    .jtdi(jtdi),
    .jtms(jtms),
    .jsel(jsel),
    

    .jreq_vld(jreq_vld),
    .jreq_data(jreq_data),
    .jreq_rdy(jreq_rdy),
    .jresp_vld(jresp_vld),
    .jresp_data(jresp_data),
    .jresp_rdy(jresp_rdy),
    
    .dev_rst(reset)
);

jtag_dmi_intc jtag_dmi_intc (


    .jclk(xtck),
    .jreq_vld(jreq_vld),
    .jreq_data(jreq_data),
    .jreq_rdy(jreq_rdy),
    .jresp_vld(jresp_vld),
    .jresp_data(jresp_data),
    .jresp_rdy(jresp_rdy),


    .cclk(clock),
    .creq_vld(creq_vld),
    .creq_data(creq_data),
    .creq_rdy(creq_rdy),
    .cresp_vld(cresp_vld),
    .cresp_data(cresp_data),
    .cresp_rdy(cresp_rdy),
    
    .dev_rst(reset)
);

endmodule
module jtag_dmi_if#(
    parameter JTAG_CHAIN = 4,
    parameter DMI_ADDR_WIDTH = 7,
    parameter DMI_DATA_WIDTH = 32,
    parameter DMI_OP_WIDTH = 2,
    parameter JTAG_DATA_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH),
    parameter TX_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH),
    parameter RX_WIDTH = (DMI_DATA_WIDTH+DMI_OP_WIDTH)
)(


    output creq_vld,
    output [TX_WIDTH-1:0] creq_data,
    input creq_rdy,
    input cresp_vld,
    input [RX_WIDTH-1:0] cresp_data,
    output cresp_rdy,

    input reset,
    input clock
);


wire jreq_vld;
wire [TX_WIDTH-1:0] jreq_data;
wire jreq_rdy;
wire jresp_vld;
wire [RX_WIDTH-1:0] jresp_data;
wire jresp_rdy;









wire jcapture;
wire jreset;
wire jshift;
wire jupdate;
wire jtdo;
wire jtdi;
wire jtms;
wire jsel; 


wire xcapture;
wire xreset;
wire xshift;
wire xupdate;
wire xsel;
wire xtdo;
wire xtdi;
wire xtck;
wire xtms;

BSCANE2 #(
    .JTAG_CHAIN(JTAG_CHAIN)
)
bse2_inst (
    .CAPTURE(xcapture),
    .DRCK(),
    .RESET(xreset),
    .RUNTEST(),
    .SEL(xsel),
    .SHIFT(xshift),
    .TCK(xtck),
    .TDI(xtdi),
    .TMS(xtms),
    .UPDATE(xupdate),
    .TDO(xtdo)
);

assign jcapture = xcapture;
assign jreset = xreset;
assign jshift = xshift;
assign jupdate = xupdate;
assign xtdo = jtdo;
assign jtdi = xtdi;
assign jtms = xtms;
assign jsel = xsel;

jtag_dmi_dsif jtag_dmi_dsif(

    .jclk(xtck),
    

    .jcapture(jcapture),
    .jreset(jreset),
    .jshift(jshift),
    .jupdate(jupdate),
    .jtdo(jtdo),
    .jtdi(jtdi),
    .jtms(jtms),
    .jsel(jsel),
    

    .jreq_vld(jreq_vld),
    .jreq_data(jreq_data),
    .jreq_rdy(jreq_rdy),
    .jresp_vld(jresp_vld),
    .jresp_data(jresp_data),
    .jresp_rdy(jresp_rdy),
    
    .dev_rst(reset)
);

jtag_dmi_intc jtag_dmi_intc (


    .jclk(xtck),
    .jreq_vld(jreq_vld),
    .jreq_data(jreq_data),
    .jreq_rdy(jreq_rdy),
    .jresp_vld(jresp_vld),
    .jresp_data(jresp_data),
    .jresp_rdy(jresp_rdy),


    .cclk(clock),
    .creq_vld(creq_vld),
    .creq_data(creq_data),
    .creq_rdy(creq_rdy),
    .cresp_vld(cresp_vld),
    .cresp_data(cresp_data),
    .cresp_rdy(cresp_rdy),
    
    .dev_rst(reset)
);

endmodule