data/full_repos/permissive/143278/ivltests/always3.1.5C.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.5C.v:28: Unsupported: Ignoring delay on this delayed statement.\n           # 5 ;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/always3.1.5C.v:37: Unsupported: Ignoring delay on this delayed statement.\n                   # 1;\n                   ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ;

reg [3:0] value1 ;

initial
	begin
           value1 = 0;
           # 5 ;
           if(value1 != 4'd4)
                $display("FAILED - always 3.1.5C always if ( constant) statementelse ;");
           else
                $display("PASSED");
	   $finish;
        end

always if( 1'b1) begin
                   # 1;
                   value1 = value1 + 1;
                 end
       else value1 = 0 ;

endmodule
module main ;


reg [3:0] value1 ;

initial
	begin
           value1 = 0;
           # 5 ;
           if(value1 != 4'd4)
                $display("FAILED - always 3.1.5C always if ( constant) statementelse ;");
           else
                $display("PASSED");
	   $finish;
        end

always if( 1'b1) begin
                   # 1;
                   value1 = value1 + 1;
                 end
       else value1 = 0 ;

endmodule