data/full_repos/permissive/151207731/rv32i/rtl/merlin_int_regs.v
None: at end of input
1: b'%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_int_regs.v:9: Cannot find include file: riscv_defs.v\n`include "riscv_defs.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v.v\n             data/full_repos/permissive/151207731/rv32i/rtl,data/full_repos/permissive/151207731/riscv_defs.v.sv\n             riscv_defs.v\n             riscv_defs.v.v\n             riscv_defs.v.sv\n             obj_dir/riscv_defs.v\n             obj_dir/riscv_defs.v.v\n             obj_dir/riscv_defs.v.sv\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_int_regs.v:19: Define or directive not defined: \'`RV_XLEN\'\n        input  wire [`RV_XLEN-1:0] wreg_a_data_i,\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_int_regs.v:22: Define or directive not defined: \'`RV_XLEN\'\n        input  wire [`RV_XLEN-1:0] wreg_b_data_i,\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_int_regs.v:26: Define or directive not defined: \'`RV_XLEN\'\n        output reg  [`RV_XLEN-1:0] rreg_a_data_o,\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_int_regs.v:29: Define or directive not defined: \'`RV_XLEN\'\n        output reg  [`RV_XLEN-1:0] rreg_b_data_o\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_int_regs.v:34: Define or directive not defined: \'`RV_XLEN\'\n    reg [`RV_XLEN-1:0] mem[1:31];\n         ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_int_regs.v:41: Define or directive not defined: \'`RV_SYNC_LOGIC_CLOCK\'\n    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin\n             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_int_regs.v:61: Define or directive not defined: \'`RV_XLEN\'\n            rreg_a_data_o = { `RV_XLEN {1\'b0} };\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/151207731/rv32i/rtl/merlin_int_regs.v:67: Define or directive not defined: \'`RV_XLEN\'\n            rreg_b_data_o = { `RV_XLEN {1\'b0} };\n                              ^~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module merlin_int_regs
    (

        input  wire                clk_i,
        input  wire                reset_i,

        input  wire                wreg_a_wr_i,
        input  wire          [4:0] wreg_a_addr_i,
        input  wire [`RV_XLEN-1:0] wreg_a_data_i,
        input  wire                wreg_b_wr_i,
        input  wire          [4:0] wreg_b_addr_i,
        input  wire [`RV_XLEN-1:0] wreg_b_data_i,

        input  wire                rreg_a_rd_i,
        input  wire          [4:0] rreg_a_addr_i,
        output reg  [`RV_XLEN-1:0] rreg_a_data_o,
        input  wire                rreg_b_rd_i,
        input  wire          [4:0] rreg_b_addr_i,
        output reg  [`RV_XLEN-1:0] rreg_b_data_o
    );



    reg [`RV_XLEN-1:0] mem[1:31];






    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin

        if (wreg_a_wr_i) begin
            mem[wreg_a_addr_i] <= wreg_a_data_i;
        end

        if (wreg_b_wr_i) begin
            mem[wreg_b_addr_i] <= wreg_b_data_i;
        end
    end





    always @ (*) begin

        if (rreg_a_rd_i && rreg_a_addr_i != 5'b0) begin
            rreg_a_data_o = mem[rreg_a_addr_i];
        end else begin
            rreg_a_data_o = { `RV_XLEN {1'b0} };
        end

        if (rreg_b_rd_i && rreg_b_addr_i != 5'b0) begin
            rreg_b_data_o = mem[rreg_b_addr_i];
        end else begin
            rreg_b_data_o = { `RV_XLEN {1'b0} };
        end
    end
endmodule
module merlin_int_regs
    (

        input  wire                clk_i,
        input  wire                reset_i,

        input  wire                wreg_a_wr_i,
        input  wire          [4:0] wreg_a_addr_i,
        input  wire [`RV_XLEN-1:0] wreg_a_data_i,
        input  wire                wreg_b_wr_i,
        input  wire          [4:0] wreg_b_addr_i,
        input  wire [`RV_XLEN-1:0] wreg_b_data_i,

        input  wire                rreg_a_rd_i,
        input  wire          [4:0] rreg_a_addr_i,
        output reg  [`RV_XLEN-1:0] rreg_a_data_o,
        input  wire                rreg_b_rd_i,
        input  wire          [4:0] rreg_b_addr_i,
        output reg  [`RV_XLEN-1:0] rreg_b_data_o
    );




    reg [`RV_XLEN-1:0] mem[1:31];






    always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin

        if (wreg_a_wr_i) begin
            mem[wreg_a_addr_i] <= wreg_a_data_i;
        end

        if (wreg_b_wr_i) begin
            mem[wreg_b_addr_i] <= wreg_b_data_i;
        end
    end





    always @ (*) begin

        if (rreg_a_rd_i && rreg_a_addr_i != 5'b0) begin
            rreg_a_data_o = mem[rreg_a_addr_i];
        end else begin
            rreg_a_data_o = { `RV_XLEN {1'b0} };
        end

        if (rreg_b_rd_i && rreg_b_addr_i != 5'b0) begin
            rreg_b_data_o = mem[rreg_b_addr_i];
        end else begin
            rreg_b_data_o = { `RV_XLEN {1'b0} };
        end
    end
endmodule