data/full_repos/permissive/132304455/src/thirty_bit_lfsr_tb.v
1: b'%Error: data/full_repos/permissive/132304455/src/thirty_bit_lfsr_tb.v:6: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("lfsr.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/132304455/src/thirty_bit_lfsr_tb.v:7: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, lfsr_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/132304455/src/thirty_bit_lfsr_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/132304455/src/thirty_bit_lfsr_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/132304455/src/thirty_bit_lfsr_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/132304455/src/thirty_bit_lfsr_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lfsr_tb;

    reg enable, clock, reset;

    initial begin
        $dumpfile("lfsr.vcd");
        $dumpvars(0, lfsr_tb);
        enable = 0; clock = 0; reset = 1;
        #10;
        clock = ~clock; enable = 1; reset = 0;
        #1;
        clock = ~clock; enable = 0; reset = 0;
        #10;
        clock = ~clock; enable = 1; reset = 0;
        #1;
        $finish;
    end

    wire [29:0] data;
    thirty_bit_lfsr lfsr(data, enable, clock, reset);
endmodule
module lfsr_tb;


    reg enable, clock, reset;

    initial begin
        $dumpfile("lfsr.vcd");
        $dumpvars(0, lfsr_tb);
        enable = 0; clock = 0; reset = 1;
        #10;
        clock = ~clock; enable = 1; reset = 0;
        #1;
        clock = ~clock; enable = 0; reset = 0;
        #10;
        clock = ~clock; enable = 1; reset = 0;
        #1;
        $finish;
    end

    wire [29:0] data;
    thirty_bit_lfsr lfsr(data, enable, clock, reset);
endmodule