data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:23: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("jeff-74x377-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:24: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, jeff_74x377_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = ~CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #15 EN_BAR = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #20 EN_BAR = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #20; D7 = 0; D6 = 0; D5 = 1; D4 = 1; D3 = 0; D2 = 0; D1 = 0; D0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #20; D7 = 0; D6 = 0; D5 = 1; D4 = 1; D3 = 0; D2 = 0; D1 = 0; D0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #20; D7 = 0; D6 = 0; D5 = 1; D4 = 1; D3 = 0; D2 = 1; D1 = 1; D0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #20; D7 = 1; D6 = 1; D5 = 0; D4 = 1; D3 = 0; D2 = 1; D1 = 1; D0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #20 EN_BAR = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #20; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 1; D2 = 1; D1 = 1; D0 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #20 EN_BAR = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/registers/jeff-74x377/jeff-74x377-tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Error: Exiting due to 2 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module jeff_74x377_tb;


reg        CLK;
reg        EN_BAR;
reg        D7, D6, D5, D4, D3, D2, D1, D0;
wire       Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0;


jeff_74x377 uut(
    .clk(CLK),
    .en_bar(EN_BAR),
    .d7(D7), .d6(D6), .d5(D5), .d4(D4), .d3(D3), .d2(D2), .d1(D1), .d0(D0),   
    .q7(Q7), .q6(Q6), .q5(Q5), .q4(Q4), .q3(Q3), .q2(Q2), .q1(Q1), .q0(Q0)
);


initial begin
    $dumpfile("jeff-74x377-tb.vcd");
    $dumpvars(0, jeff_74x377_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    EN_BAR = 1;
    D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;


    #15 EN_BAR = 1;
    #20 EN_BAR = 0;


    #20; D7 = 0; D6 = 0; D5 = 1; D4 = 1; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    #20; D7 = 0; D6 = 0; D5 = 1; D4 = 1; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    #100;
    #20; D7 = 0; D6 = 0; D5 = 1; D4 = 1; D3 = 0; D2 = 1; D1 = 1; D0 = 0;
    #20; D7 = 1; D6 = 1; D5 = 0; D4 = 1; D3 = 0; D2 = 1; D1 = 1; D0 = 0;
    #100


    #20 EN_BAR = 1;
    #20; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 1; D2 = 1; D1 = 1; D0 = 1;
    #20 EN_BAR = 0;


    #20

    $display("test complete");
    $finish;
end

endmodule
module jeff_74x377_tb;



reg        CLK;
reg        EN_BAR;
reg        D7, D6, D5, D4, D3, D2, D1, D0;
wire       Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0;


jeff_74x377 uut(
    .clk(CLK),
    .en_bar(EN_BAR),
    .d7(D7), .d6(D6), .d5(D5), .d4(D4), .d3(D3), .d2(D2), .d1(D1), .d0(D0),   
    .q7(Q7), .q6(Q6), .q5(Q5), .q4(Q4), .q3(Q3), .q2(Q2), .q1(Q1), .q0(Q0)
);


initial begin
    $dumpfile("jeff-74x377-tb.vcd");
    $dumpvars(0, jeff_74x377_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    EN_BAR = 1;
    D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 0; D2 = 0; D1 = 0; D0 = 0;


    #15 EN_BAR = 1;
    #20 EN_BAR = 0;


    #20; D7 = 0; D6 = 0; D5 = 1; D4 = 1; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    #20; D7 = 0; D6 = 0; D5 = 1; D4 = 1; D3 = 0; D2 = 0; D1 = 0; D0 = 0;
    #100;
    #20; D7 = 0; D6 = 0; D5 = 1; D4 = 1; D3 = 0; D2 = 1; D1 = 1; D0 = 0;
    #20; D7 = 1; D6 = 1; D5 = 0; D4 = 1; D3 = 0; D2 = 1; D1 = 1; D0 = 0;
    #100


    #20 EN_BAR = 1;
    #20; D7 = 0; D6 = 0; D5 = 0; D4 = 0; D3 = 1; D2 = 1; D1 = 1; D0 = 1;
    #20 EN_BAR = 0;


    #20

    $display("test complete");
    $finish;
end

endmodule