data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v
 line:118: before: "("
1: b'%Error: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:103: Cannot find file containing module: \'jelly_param_update_master\'\n    jelly_param_update_master\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/image,data/full_repos/permissive/2084115/jelly_param_update_master\n             data/full_repos/permissive/2084115/rtl/image,data/full_repos/permissive/2084115/jelly_param_update_master.v\n             data/full_repos/permissive/2084115/rtl/image,data/full_repos/permissive/2084115/jelly_param_update_master.sv\n             jelly_param_update_master\n             jelly_param_update_master.v\n             jelly_param_update_master.sv\n             obj_dir/jelly_param_update_master\n             obj_dir/jelly_param_update_master.v\n             obj_dir/jelly_param_update_master.sv\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:144: Operator FUNCREF \'write_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_ctl_control\' generates 3 bits.\n                                                                                        : ... In instance jelly_img_alpha_belnd\n                ADR_CTL_CONTROL:    reg_ctl_control <= write_mask(reg_ctl_control, s_wb_dat_i, s_wb_sel_i);\n                                                       ^~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:144: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'write_mask\' generates 32 bits.\n                                                                                        : ... In instance jelly_img_alpha_belnd\n                ADR_CTL_CONTROL:    reg_ctl_control <= write_mask(reg_ctl_control, s_wb_dat_i, s_wb_sel_i);\n                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:145: Operator FUNCREF \'write_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_alpha\' generates 8 bits.\n                                                                                        : ... In instance jelly_img_alpha_belnd\n                ADR_PARAM_ALPHA:    reg_param_alpha <= write_mask(reg_param_alpha, s_wb_dat_i, s_wb_sel_i);\n                                                       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:145: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'write_mask\' generates 32 bits.\n                                                                                        : ... In instance jelly_img_alpha_belnd\n                ADR_PARAM_ALPHA:    reg_param_alpha <= write_mask(reg_param_alpha, s_wb_dat_i, s_wb_sel_i);\n                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:154: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_ctl_control\' generates 3 bits.\n                                                                                        : ... In instance jelly_img_alpha_belnd\n                        (s_wb_adr_i == ADR_CTL_CONTROL)    ? reg_ctl_control     :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:155: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_current_control\' generates 1 bits.\n                                                                                        : ... In instance jelly_img_alpha_belnd\n                        (s_wb_adr_i == ADR_CTL_STATUS)     ? reg_current_control :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:156: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'ctl_index\' generates 1 bits.\n                                                                                        : ... In instance jelly_img_alpha_belnd\n                        (s_wb_adr_i == ADR_CTL_INDEX)      ? ctl_index           :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:157: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_param_alpha\' generates 8 bits.\n                                                                                        : ... In instance jelly_img_alpha_belnd\n                        (s_wb_adr_i == ADR_PARAM_ALPHA)    ? reg_param_alpha     :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:158: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_current_alpha\' generates 8 bits.\n                                                                                        : ... In instance jelly_img_alpha_belnd\n                        (s_wb_adr_i == ADR_CURRENT_ALPHA)  ? reg_current_alpha   :\n                                                           ^\n%Error: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:173: Cannot find file containing module: \'jelly_param_update_slave\'\n    jelly_param_update_slave\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:195: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'INIT_CTL_CONTROL\' generates 3 bits.\n                                                                                        : ... In instance jelly_img_alpha_belnd\n            reg_current_control <= INIT_CTL_CONTROL;\n                                ^~\n%Error: data/full_repos/permissive/2084115/rtl/image/jelly_img_alpha_belnd.v:215: Cannot find file containing module: \'jelly_img_alpha_blend_core\'\n    jelly_img_alpha_blend_core\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 10 warning(s)\n'
function [WB_DAT_WIDTH-1:0] write_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );
    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            write_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction
function [WB_DAT_WIDTH-1:0] write_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );

    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            write_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction