data/full_repos/permissive/197263932/main.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/197263932/main.v:18: syntax error, unexpected $end, expecting ',' or ':'\n6   b000000: controls <= 9   b110000010;  \n ^\n%Error: Cannot continue\n"
module mips(
	input logic clk, reset,
	output logic [31:0] pc,
	input logic [31:0] instr,
	output logic memwrite,
	output logic [31:0] aluout, writedata,
	input logic [31:0] readdata);

logic memtoreg, alusrc, regdst;
logic regwrite, jump, pcsrc, zero;
logic [2:0] alucontrol;

controller c(
	instr[31:26], 
	instr[5:0], 
	zero,
	memtoreg, 
	memwrite, 
	pcsrc,
	alusrc, 
	regdst, 
	regwrite, 
	jump,
	alucontrol);
	
datapath dp(
	clk, 
	reset, 
	memtoreg, 
	pcsrc,
	alusrc, 
	regdst, 
	regwrite, 
	jump,
	alucontrol,
	zero, 
	pc, 
	instr,
	aluout, 
	writedata, 
	readdata);
	
endmodule
module mips(
	input logic clk, reset,
	output logic [31:0] pc,
	input logic [31:0] instr,
	output logic memwrite,
	output logic [31:0] aluout, writedata,
	input logic [31:0] readdata);


logic memtoreg, alusrc, regdst;
logic regwrite, jump, pcsrc, zero;
logic [2:0] alucontrol;

controller c(
	instr[31:26], 
	instr[5:0], 
	zero,
	memtoreg, 
	memwrite, 
	pcsrc,
	alusrc, 
	regdst, 
	regwrite, 
	jump,
	alucontrol);
	
datapath dp(
	clk, 
	reset, 
	memtoreg, 
	pcsrc,
	alusrc, 
	regdst, 
	regwrite, 
	jump,
	alucontrol,
	zero, 
	pc, 
	instr,
	aluout, 
	writedata, 
	readdata);
	
endmodule