data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_top.v:90: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'StatusReg\' generates 32 bits.\n                                                                                            : ... In instance serial_top\n   address <= StatusReg;\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_top.v:99: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'StatusReg\' generates 32 bits.\n                                                                                            : ... In instance serial_top\n  next_address = StatusReg;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_top.v:109: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'RxDataReg\' generates 32 bits.\n                                                                                             : ... In instance serial_top\n     next_address = RxDataReg;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_top.v:114: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'StatusReg\' generates 32 bits.\n                                                                                             : ... In instance serial_top\n     next_address = StatusReg;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_top.v:120: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'RxDataReg\' generates 32 bits.\n                                                                                             : ... In instance serial_top\n    next_address = RxDataReg;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_top.v:127: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'StatusReg\' generates 32 bits.\n                                                                                             : ... In instance serial_top\n    next_address = StatusReg;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_top.v:135: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'TxDataReg\' generates 32 bits.\n                                                                                             : ... In instance serial_top\n     next_address = TxDataReg;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_top.v:140: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'StatusReg\' generates 32 bits.\n                                                                                             : ... In instance serial_top\n     next_address = StatusReg;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_top.v:146: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'TxDataReg\' generates 32 bits.\n                                                                                             : ... In instance serial_top\n    next_address = TxDataReg;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_top.v:152: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'StatusReg\' generates 32 bits.\n                                                                                             : ... In instance serial_top\n    next_address = StatusReg;\n                 ^\n%Error: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/serial_top.v:161: Cannot find file containing module: \'serial_port\'\n serial_port serial_port(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1,data/full_repos/permissive/172396252/serial_port\n             data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1,data/full_repos/permissive/172396252/serial_port.v\n             data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1,data/full_repos/permissive/172396252/serial_port.sv\n             serial_port\n             serial_port.v\n             serial_port.sv\n             obj_dir/serial_port\n             obj_dir/serial_port.v\n             obj_dir/serial_port.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n'
module serial_top(
    input clk100MHz,

    input [15:0] sw,
    output [15:0] led_out_hardware,
    input [4:0] buttons,
    output [7:0] seg,
    output [3:0] an,

    output Tx1,
    input Rx1,
    output Tx2,
    input Rx2
	);



	reg [3:0] clkc = 0; 
	always @(posedge clk100MHz) begin
		clkc = clkc + 1;
	end
	wire clk;
	assign clk = clkc[3];
	
	reg  [31:0] internal_data, next_internal_data;

	wire rst_n;
	assign rst_n = ~buttons[0];

	reg read_enable, next_rd_en;
	wire write_enable;
	assign write_enable = ~read_enable;

	wire [31:0] data_bus;
	assign data_bus = read_enable ? 32'hzzzzzzzz : internal_data;

	reg [19:0] address, next_address;

	wire serial_irq_n;
	wire [7:0] TxData;
	wire [7:0] RxData;

	parameter [31:0]
		RxDataReg = 1,
		TxDataReg = 0,
		StatusReg = 3;
		
	parameter [3:0]
		RxPoll_STATE = 0,
		RxRead_STATE = 1,
		Stall1_STATE = 2,
		TxPoll_STATE = 3,
		TxWrit_STATE = 4,
		Stall2_STATE = 5;
	reg [3:0] next_STATE, STATE;


	always @(posedge clk) begin

		STATE <= next_STATE;
		address <= next_address;
		read_enable <= next_rd_en;
		internal_data <= next_internal_data;

		if (~rst_n) begin
			STATE <= RxPoll_STATE;
			address <= StatusReg;
			read_enable <= 1;
			internal_data <= 0;
		end
	end


	always @(*) begin

		next_address = StatusReg;
		next_rd_en = 1;
		next_internal_data = internal_data;
		next_STATE = RxPoll_STATE;

		case(STATE)

			RxPoll_STATE: begin
				if (data_bus[0]) begin
					next_STATE = RxRead_STATE;
					next_address = RxDataReg;
					next_rd_en = 1;
				end
				else begin
					next_STATE = RxPoll_STATE;
					next_address = StatusReg;
					next_rd_en = 1;
				end
			end

			RxRead_STATE: begin
				next_address = RxDataReg;
				next_rd_en = 1;
				next_STATE = Stall1_STATE;
			end

			Stall1_STATE: begin
				next_internal_data = data_bus;
				next_address = StatusReg;
				next_rd_en = 1;
				next_STATE = TxPoll_STATE;
			end

			TxPoll_STATE: begin
				if (data_bus[1]) begin
					next_STATE = TxWrit_STATE;
					next_address = TxDataReg;
					next_rd_en = 0;
				end
				else begin
					next_STATE = TxPoll_STATE;
					next_address = StatusReg;
					next_rd_en = 1;
				end
			end

			TxWrit_STATE: begin
				next_address = TxDataReg;
				next_rd_en = 0;
				next_STATE = Stall2_STATE;
			end

			Stall2_STATE: begin
				next_address = StatusReg;
				next_rd_en = 1;
				next_STATE = RxPoll_STATE;
			end


		endcase
	end

	serial_port serial_port(
		rst_n,
		clk,
		read_enable,
		write_enable,
		data_bus,
		address,
		serial_irq_n,
		Tx1,
		Rx1
		); 


endmodule
module serial_top(
    input clk100MHz,

    input [15:0] sw,
    output [15:0] led_out_hardware,
    input [4:0] buttons,
    output [7:0] seg,
    output [3:0] an,

    output Tx1,
    input Rx1,
    output Tx2,
    input Rx2
	);




	reg [3:0] clkc = 0; 
	always @(posedge clk100MHz) begin
		clkc = clkc + 1;
	end
	wire clk;
	assign clk = clkc[3];
	
	reg  [31:0] internal_data, next_internal_data;

	wire rst_n;
	assign rst_n = ~buttons[0];

	reg read_enable, next_rd_en;
	wire write_enable;
	assign write_enable = ~read_enable;

	wire [31:0] data_bus;
	assign data_bus = read_enable ? 32'hzzzzzzzz : internal_data;

	reg [19:0] address, next_address;

	wire serial_irq_n;
	wire [7:0] TxData;
	wire [7:0] RxData;

	parameter [31:0]
		RxDataReg = 1,
		TxDataReg = 0,
		StatusReg = 3;
		
	parameter [3:0]
		RxPoll_STATE = 0,
		RxRead_STATE = 1,
		Stall1_STATE = 2,
		TxPoll_STATE = 3,
		TxWrit_STATE = 4,
		Stall2_STATE = 5;
	reg [3:0] next_STATE, STATE;


	always @(posedge clk) begin

		STATE <= next_STATE;
		address <= next_address;
		read_enable <= next_rd_en;
		internal_data <= next_internal_data;

		if (~rst_n) begin
			STATE <= RxPoll_STATE;
			address <= StatusReg;
			read_enable <= 1;
			internal_data <= 0;
		end
	end


	always @(*) begin

		next_address = StatusReg;
		next_rd_en = 1;
		next_internal_data = internal_data;
		next_STATE = RxPoll_STATE;

		case(STATE)

			RxPoll_STATE: begin
				if (data_bus[0]) begin
					next_STATE = RxRead_STATE;
					next_address = RxDataReg;
					next_rd_en = 1;
				end
				else begin
					next_STATE = RxPoll_STATE;
					next_address = StatusReg;
					next_rd_en = 1;
				end
			end

			RxRead_STATE: begin
				next_address = RxDataReg;
				next_rd_en = 1;
				next_STATE = Stall1_STATE;
			end

			Stall1_STATE: begin
				next_internal_data = data_bus;
				next_address = StatusReg;
				next_rd_en = 1;
				next_STATE = TxPoll_STATE;
			end

			TxPoll_STATE: begin
				if (data_bus[1]) begin
					next_STATE = TxWrit_STATE;
					next_address = TxDataReg;
					next_rd_en = 0;
				end
				else begin
					next_STATE = TxPoll_STATE;
					next_address = StatusReg;
					next_rd_en = 1;
				end
			end

			TxWrit_STATE: begin
				next_address = TxDataReg;
				next_rd_en = 0;
				next_STATE = Stall2_STATE;
			end

			Stall2_STATE: begin
				next_address = StatusReg;
				next_rd_en = 1;
				next_STATE = RxPoll_STATE;
			end


		endcase
	end

	serial_port serial_port(
		rst_n,
		clk,
		read_enable,
		write_enable,
		data_bus,
		address,
		serial_irq_n,
		Tx1,
		Rx1
		); 


endmodule