data/full_repos/permissive/162571337/adders/8_signed_extended/pareto_pwr_mre/add8se_90X.v
data/verilator_xmls/837a5216-cc03-422a-94e3-abb620fdc3c4.xml
module add8se_90X (
    A,
    B,
    O
);

input [7:0] A;
input [7:0] B;
output [8:0] O;

wire sig_30;

assign sig_30 = ~A[7];

assign O[8] = B[7];
assign O[7] = B[7];
assign O[6] = sig_30;
assign O[5] = sig_30;
assign O[4] = A[6];
assign O[3] = B[5];
assign O[2] = A[6];
assign O[1] = B[5];
assign O[0] = B[5];

endmodule
module add8se_90X (
    A,
    B,
    O
);


input [7:0] A;
input [7:0] B;
output [8:0] O;

wire sig_30;

assign sig_30 = ~A[7];

assign O[8] = B[7];
assign O[7] = B[7];
assign O[6] = sig_30;
assign O[5] = sig_30;
assign O[4] = A[6];
assign O[3] = B[5];
assign O[2] = A[6];
assign O[1] = B[5];
assign O[0] = B[5];

endmodule