data/full_repos/permissive/178052224/Tarea5/demux/with_delay/lib/cmos_cells.v
 line:6: before: ":"
1: b'%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea5/demux/with_delay/lib/cmos_cells.v:39: Unsupported: Ignoring delay on this delayed statement.\n#(0.5:0.7:0.7) Q <= D;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea5/demux/with_delay/lib/cmos_cells.v:48: Unsupported: Ignoring delay on this delayed statement.\n#(0.5:0.7:0.7)  Q <= 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea5/demux/with_delay/lib/cmos_cells.v:50: Unsupported: Ignoring delay on this delayed statement.\n#(0.5:0.7:0.7)  Q <= 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea5/demux/with_delay/lib/cmos_cells.v:52: Unsupported: Ignoring delay on this delayed statement.\n#(0.5:0.7:0.7) Q <= D;\n^\n%Warning-MULTITOP: data/full_repos/permissive/178052224/Tarea5/demux/with_delay/lib/cmos_cells.v:11: Multiple top level modules\n                                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                                   : ... Top module \'BUF\'\nmodule BUF(A, Y);\n       ^~~\n                                                                                                   : ... Top module \'NOT\'\nmodule NOT(A, Y);\n       ^~~\n                                                                                                   : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n       ^~~~\n                                                                                                   : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n       ^~~\n                                                                                                   : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n       ^~~\n                                                                                                   : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R);\n       ^~~~~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module NOR(A, B, Y);
input A, B;
output Y;
assign #(0.1:0.35:0.35) Y = ~(A | B);
endmodule
module NOR(A, B, Y);

input A, B;
output Y;
assign #(0.1:0.35:0.35) Y = ~(A | B);
endmodule