data/full_repos/permissive/156539908/delay/delay.v
 line:66: before: ")"
1: b'%Error: data/full_repos/permissive/156539908/delay/delay.v:3: Cannot find include file: ../include/led-delay.v\n`include "../include/led-delay.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156539908/delay,data/full_repos/permissive/156539908/../include/led-delay.v\n             data/full_repos/permissive/156539908/delay,data/full_repos/permissive/156539908/../include/led-delay.v.v\n             data/full_repos/permissive/156539908/delay,data/full_repos/permissive/156539908/../include/led-delay.v.sv\n             ../include/led-delay.v\n             ../include/led-delay.v.v\n             ../include/led-delay.v.sv\n             obj_dir/../include/led-delay.v\n             obj_dir/../include/led-delay.v.v\n             obj_dir/../include/led-delay.v.sv\n%Error: Exiting due to 1 error(s)\n'
module painter(
        input        clk,
        input        reset,
        input  [9:0] frame,
        input  [7:0] subframe,
        input  [5:0] x,
        input  [5:0] y,
        output [2:0] rgb);

    wire border, x_single_bit, y_single_bit;
    reg [2:0] rgb_r0, rgb_r1, rgb_r2;

    assign border = x == 0 || y == 0 || x == 63 || y == 63;
    assign x_single_bit = (| x) & (~|(x & (x - 1)));
    assign y_single_bit = (| y) & (~|(y & (y - 1)));

    always @(posedge clk) begin

        rgb_r2 <= rgb_r1;
        rgb_r1 <= rgb_r0;
        rgb_r0 <= {border, y_single_bit, x_single_bit};




    end

    assign rgb = rgb_r2;

endmodule
module painter(
        input        clk,
        input        reset,
        input  [9:0] frame,
        input  [7:0] subframe,
        input  [5:0] x,
        input  [5:0] y,
        output [2:0] rgb);


    wire border, x_single_bit, y_single_bit;
    reg [2:0] rgb_r0, rgb_r1, rgb_r2;

    assign border = x == 0 || y == 0 || x == 63 || y == 63;
    assign x_single_bit = (| x) & (~|(x & (x - 1)));
    assign y_single_bit = (| y) & (~|(y & (y - 1)));

    always @(posedge clk) begin

        rgb_r2 <= rgb_r1;
        rgb_r1 <= rgb_r0;
        rgb_r0 <= {border, y_single_bit, x_single_bit};




    end

    assign rgb = rgb_r2;

endmodule