data/full_repos/permissive/113002755/verilog/RNG/asteroid_timer.v
1: b"%Error: data/full_repos/permissive/113002755/verilog/RNG/asteroid_timer.v:28: Cannot find file containing module: 'rng'\nrng R1(random, clk, rst);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/113002755/verilog/RNG,data/full_repos/permissive/113002755/rng\n             data/full_repos/permissive/113002755/verilog/RNG,data/full_repos/permissive/113002755/rng.v\n             data/full_repos/permissive/113002755/verilog/RNG,data/full_repos/permissive/113002755/rng.sv\n             rng\n             rng.v\n             rng.sv\n             obj_dir/rng\n             obj_dir/rng.v\n             obj_dir/rng.sv\n%Error: Exiting due to 1 error(s)\n"
module asteroid_timer(clk, rst, delay, fire);

input clk, rst;
input [31:0] delay;


output reg fire;


reg [31:0] i;


wire [2:0] random;


rng R1(random, clk, rst);


always @(posedge clk or negedge rst) 
	begin
		if (rst == 1'b0) 
		begin
			i = 0;
			fire = 0;
		end
		else 
		begin
			i = i + 1;
			fire = 0;
			if (i >= delay) 
			begin
				i = 0;
				if (random < 2)
				begin
					fire = 1;
				end
				else
				begin
					fire = 0;
				end
			end
			else
			begin
			
			end
		end 
	end

endmodule
module asteroid_timer(clk, rst, delay, fire);


input clk, rst;
input [31:0] delay;


output reg fire;


reg [31:0] i;


wire [2:0] random;


rng R1(random, clk, rst);


always @(posedge clk or negedge rst) 
	begin
		if (rst == 1'b0) 
		begin
			i = 0;
			fire = 0;
		end
		else 
		begin
			i = i + 1;
			fire = 0;
			if (i >= delay) 
			begin
				i = 0;
				if (random < 2)
				begin
					fire = 1;
				end
				else
				begin
					fire = 0;
				end
			end
			else
			begin
			
			end
		end 
	end

endmodule