data/full_repos/permissive/133819542/src/hilo_reg.v
1: b'%Error: data/full_repos/permissive/133819542/src/hilo_reg.v:8: Cannot find include file: const.v\n`include "const.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v.v\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v.sv\n             const.v\n             const.v.v\n             const.v.sv\n             obj_dir/const.v\n             obj_dir/const.v.v\n             obj_dir/const.v.sv\n%Error: data/full_repos/permissive/133819542/src/hilo_reg.v:14: Define or directive not defined: \'`RegBus\'\n    input  wire  [`RegBus]      hi_i ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/hilo_reg.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input  wire  [`RegBus]      hi_i ,\n                         ^\n%Error: data/full_repos/permissive/133819542/src/hilo_reg.v:15: Define or directive not defined: \'`RegBus\'\n    input  wire  [`RegBus]      lo_i ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/hilo_reg.v:16: Define or directive not defined: \'`RegBus\'\n    output  reg  [`RegBus]      hi_o ,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/hilo_reg.v:17: Define or directive not defined: \'`RegBus\'\n    output  reg  [`RegBus]      lo_o  \n                  ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/hilo_reg.v:21: Define or directive not defined: \'`RESET_ENABLE\'\n        if(rst == `RESET_ENABLE) begin\n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/hilo_reg.v:24: Define or directive not defined: \'`WRITE_ENABLE\'\n        end else if(we == `WRITE_ENABLE) begin\n                          ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module hilo_reg (
    input  wire                 clk  ,
    input  wire                 rst  ,
    input  wire                 we   ,
    input  wire  [`RegBus]      hi_i ,
    input  wire  [`RegBus]      lo_i ,
    output  reg  [`RegBus]      hi_o ,
    output  reg  [`RegBus]      lo_o  
);

    always @(posedge clk) begin
        if(rst == `RESET_ENABLE) begin
            hi_o <= 0;
            lo_o <= 0;
        end else if(we == `WRITE_ENABLE) begin
            hi_o <= hi_i;
            lo_o <= lo_i;
        end
    end
endmodule
module hilo_reg (
    input  wire                 clk  ,
    input  wire                 rst  ,
    input  wire                 we   ,
    input  wire  [`RegBus]      hi_i ,
    input  wire  [`RegBus]      lo_i ,
    output  reg  [`RegBus]      hi_o ,
    output  reg  [`RegBus]      lo_o  
);


    always @(posedge clk) begin
        if(rst == `RESET_ENABLE) begin
            hi_o <= 0;
            lo_o <= 0;
        end else if(we == `WRITE_ENABLE) begin
            hi_o <= hi_i;
            lo_o <= lo_i;
        end
    end
endmodule