data/full_repos/permissive/154352170/Stall.v
1: b"%Error: data/full_repos/permissive/154352170/Stall.v:196: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\n  output [2:0] type\n               ^~~~\n%Error: data/full_repos/permissive/154352170/Stall.v:203: syntax error, unexpected assign\n  assign type = type_temp;\n  ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Stall(
    input [31:0] IR_D,
	 input [31:0] IR_E,
	 input [31:0] IR_M,
	 output PC_En,
    output IF_ID_En,
    output ID_EXE_Clr	 
    );
    
	 wire [2:0] D_type;
	 wire [2:0] E_type;
	 wire [2:0] M_type;

    Type_S D_Type_S(IR_D, D_type);
	 Type_S E_Type_S(IR_E, E_type);
	 Type_S M_Type_S(IR_M, M_type);
	 
	 reg stall_Beq_rs;
	 reg stall_Beq_rt;
	 reg stall_Cal_R_rs;
	 reg stall_Cal_R_rt;
	 reg stall_Cal_I_rs;
	 reg stall_Load_rs;
	 reg stall_Save_rs;
	 reg stall_Jr_rs;
	 
	 wire Stall_Beq_rs;
	 wire Stall_Beq_rt;
	 wire Stall_Cal_R_rs;
	 wire Stall_Cal_R_rt;
	 wire Stall_Cal_I_rs;
	 wire Stall_Load_rs;
	 wire Stall_Save_rs;
	 wire Stall_Jr_rs;
	 
	 initial begin
	    stall_Beq_rs <= 0;
	    stall_Beq_rt <= 0;
	    stall_Cal_R_rs <= 0;
	    stall_Cal_R_rt <= 0;
	    stall_Cal_I_rs <= 0;
	    stall_Load_rs <= 0;
	    stall_Save_rs <= 0;
	    stall_Jr_rs <= 0;
	 end
	 
	 always @ (*) begin
	    

		 if (D_type == 3'b011) begin
		    
			 if (E_type == 3'b001 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rd])
		       stall_Beq_rs <= 1;
			 
			 else if (E_type == 3'b010 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
			    stall_Beq_rs <= 1;
				 
			 else if (E_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
			    stall_Beq_rs <= 1;
				 
			 else if (M_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_M[`rt])
			    stall_Beq_rs <= 1;	 
				 
			 else if (E_type == 3'b111 & IR_D[`rs] != 0 & IR_D[`rs] == 5'b11111)
			    stall_Beq_rs <= 1;
				 
			 else
			    stall_Beq_rs <= 0;
		
		 end
		 
		 else
          stall_Beq_rs <= 0;	


		 if (D_type == 3'b011) begin
		    
			 if (E_type == 3'b001 & IR_D[`rt] != 0 & IR_D[`rt] == IR_E[`rd])
		       stall_Beq_rt <= 1;
			 
			 else if (E_type == 3'b010 & IR_D[`rt] != 0 & IR_D[`rt] == IR_E[`rt])
			    stall_Beq_rt <= 1;
				 
			 else if (E_type == 3'b100 & IR_D[`rt] != 0 & IR_D[`rt] == IR_E[`rt])
			    stall_Beq_rt <= 1;
				 
			 else if (M_type == 3'b100 & IR_D[`rt] != 0 & IR_D[`rt] == IR_M[`rt])
			    stall_Beq_rt <= 1;	 
				 
			 else if (E_type == 3'b111 & IR_D[`rt] != 0 & IR_D[`rt] == 5'b11111)
			    stall_Beq_rt <= 1;
				 
			 else
			    stall_Beq_rt <= 0;
		
		 end
		 
		 else
          stall_Beq_rt <= 0;
			 

		 if (D_type == 3'b001 & E_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
		    stall_Cal_R_rs <= 1;
		 else
		    stall_Cal_R_rs <= 0;
		

		 if (D_type == 3'b001 & E_type == 3'b100 & IR_D[`rt] != 0 & IR_D[`rt] == IR_E[`rt])
		    stall_Cal_R_rt <= 1;
		 else
		    stall_Cal_R_rt <= 0;
		 

		 if (D_type == 3'b010 & E_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
		    stall_Cal_I_rs <= 1;
		 else
		    stall_Cal_I_rs <= 0;
			 

		 if (D_type == 3'b100 & E_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
		    stall_Load_rs <= 1;
		 else
		    stall_Load_rs <= 0;
		 

		 if (D_type == 3'b101 & E_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
		    stall_Save_rs <= 1;
		 else
		    stall_Save_rs <= 0;
		 

		 if (D_type == 3'b110) begin
		    
			 if (E_type == 3'b001 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rd])
		       stall_Jr_rs <= 1;
			 
			 else if (E_type == 3'b010 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
			    stall_Jr_rs <= 1;
				 
			 else if (E_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
			    stall_Jr_rs <= 1;
				 
			 else if (M_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_M[`rt])
			    stall_Jr_rs <= 1;	 
				 
			 else if (E_type == 3'b111 & IR_D[`rs] != 0 & IR_D[`rs] == 5'b11111)
			    stall_Jr_rs <= 1;
				 
			 else
			    stall_Jr_rs <= 0;
		
		 end
		 
		 else
          stall_Jr_rs <= 0;	
			 
	 end
	 
	 wire stall;
	 assign stall = stall_Beq_rs | stall_Beq_rt | stall_Cal_R_rs | stall_Cal_R_rt | stall_Cal_I_rs | stall_Load_rs | stall_Save_rs | stall_Jr_rs;
	 
	 assign PC_En = !stall;
	 assign IF_ID_En = !stall;
	 assign ID_EXE_Clr = stall;
	 
endmodule
module Stall(
    input [31:0] IR_D,
	 input [31:0] IR_E,
	 input [31:0] IR_M,
	 output PC_En,
    output IF_ID_En,
    output ID_EXE_Clr	 
    );

    
	 wire [2:0] D_type;
	 wire [2:0] E_type;
	 wire [2:0] M_type;

    Type_S D_Type_S(IR_D, D_type);
	 Type_S E_Type_S(IR_E, E_type);
	 Type_S M_Type_S(IR_M, M_type);
	 
	 reg stall_Beq_rs;
	 reg stall_Beq_rt;
	 reg stall_Cal_R_rs;
	 reg stall_Cal_R_rt;
	 reg stall_Cal_I_rs;
	 reg stall_Load_rs;
	 reg stall_Save_rs;
	 reg stall_Jr_rs;
	 
	 wire Stall_Beq_rs;
	 wire Stall_Beq_rt;
	 wire Stall_Cal_R_rs;
	 wire Stall_Cal_R_rt;
	 wire Stall_Cal_I_rs;
	 wire Stall_Load_rs;
	 wire Stall_Save_rs;
	 wire Stall_Jr_rs;
	 
	 initial begin
	    stall_Beq_rs <= 0;
	    stall_Beq_rt <= 0;
	    stall_Cal_R_rs <= 0;
	    stall_Cal_R_rt <= 0;
	    stall_Cal_I_rs <= 0;
	    stall_Load_rs <= 0;
	    stall_Save_rs <= 0;
	    stall_Jr_rs <= 0;
	 end
	 
	 always @ (*) begin
	    

		 if (D_type == 3'b011) begin
		    
			 if (E_type == 3'b001 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rd])
		       stall_Beq_rs <= 1;
			 
			 else if (E_type == 3'b010 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
			    stall_Beq_rs <= 1;
				 
			 else if (E_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
			    stall_Beq_rs <= 1;
				 
			 else if (M_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_M[`rt])
			    stall_Beq_rs <= 1;	 
				 
			 else if (E_type == 3'b111 & IR_D[`rs] != 0 & IR_D[`rs] == 5'b11111)
			    stall_Beq_rs <= 1;
				 
			 else
			    stall_Beq_rs <= 0;
		
		 end
		 
		 else
          stall_Beq_rs <= 0;	


		 if (D_type == 3'b011) begin
		    
			 if (E_type == 3'b001 & IR_D[`rt] != 0 & IR_D[`rt] == IR_E[`rd])
		       stall_Beq_rt <= 1;
			 
			 else if (E_type == 3'b010 & IR_D[`rt] != 0 & IR_D[`rt] == IR_E[`rt])
			    stall_Beq_rt <= 1;
				 
			 else if (E_type == 3'b100 & IR_D[`rt] != 0 & IR_D[`rt] == IR_E[`rt])
			    stall_Beq_rt <= 1;
				 
			 else if (M_type == 3'b100 & IR_D[`rt] != 0 & IR_D[`rt] == IR_M[`rt])
			    stall_Beq_rt <= 1;	 
				 
			 else if (E_type == 3'b111 & IR_D[`rt] != 0 & IR_D[`rt] == 5'b11111)
			    stall_Beq_rt <= 1;
				 
			 else
			    stall_Beq_rt <= 0;
		
		 end
		 
		 else
          stall_Beq_rt <= 0;
			 

		 if (D_type == 3'b001 & E_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
		    stall_Cal_R_rs <= 1;
		 else
		    stall_Cal_R_rs <= 0;
		

		 if (D_type == 3'b001 & E_type == 3'b100 & IR_D[`rt] != 0 & IR_D[`rt] == IR_E[`rt])
		    stall_Cal_R_rt <= 1;
		 else
		    stall_Cal_R_rt <= 0;
		 

		 if (D_type == 3'b010 & E_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
		    stall_Cal_I_rs <= 1;
		 else
		    stall_Cal_I_rs <= 0;
			 

		 if (D_type == 3'b100 & E_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
		    stall_Load_rs <= 1;
		 else
		    stall_Load_rs <= 0;
		 

		 if (D_type == 3'b101 & E_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
		    stall_Save_rs <= 1;
		 else
		    stall_Save_rs <= 0;
		 

		 if (D_type == 3'b110) begin
		    
			 if (E_type == 3'b001 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rd])
		       stall_Jr_rs <= 1;
			 
			 else if (E_type == 3'b010 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
			    stall_Jr_rs <= 1;
				 
			 else if (E_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_E[`rt])
			    stall_Jr_rs <= 1;
				 
			 else if (M_type == 3'b100 & IR_D[`rs] != 0 & IR_D[`rs] == IR_M[`rt])
			    stall_Jr_rs <= 1;	 
				 
			 else if (E_type == 3'b111 & IR_D[`rs] != 0 & IR_D[`rs] == 5'b11111)
			    stall_Jr_rs <= 1;
				 
			 else
			    stall_Jr_rs <= 0;
		
		 end
		 
		 else
          stall_Jr_rs <= 0;	
			 
	 end
	 
	 wire stall;
	 assign stall = stall_Beq_rs | stall_Beq_rt | stall_Cal_R_rs | stall_Cal_R_rt | stall_Cal_I_rs | stall_Load_rs | stall_Save_rs | stall_Jr_rs;
	 
	 assign PC_En = !stall;
	 assign IF_ID_En = !stall;
	 assign ID_EXE_Clr = stall;
	 
endmodule