data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/testbench/RISC_testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/testbench/RISC_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n always#20 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/testbench/RISC_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #30 rst=0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/testbench/RISC_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #6000 $stop;       \n      ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/testbench/RISC_testbench.v:20: Cannot find file containing module: \'RISC_core_mem_top\'\nRISC_core_mem_top top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/testbench,data/full_repos/permissive/137416811/RISC_core_mem_top\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/testbench,data/full_repos/permissive/137416811/RISC_core_mem_top.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/testbench,data/full_repos/permissive/137416811/RISC_core_mem_top.sv\n             RISC_core_mem_top\n             RISC_core_mem_top.v\n             RISC_core_mem_top.sv\n             obj_dir/RISC_core_mem_top\n             obj_dir/RISC_core_mem_top.v\n             obj_dir/RISC_core_mem_top.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RISC_testbench;
   
wire	[7:0]bus_1_out;
reg	clk,rst;
wire	[7:0]Reg_R0_out;
wire	[7:0]Reg_R1_out;
wire	[7:0]Reg_R2_out;
wire	[7:0]Reg_R3_out;





RISC_core_mem_top top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);

 always#20 clk=~clk;
   
 initial
    begin
      clk=0;rst=1;
      #30 rst=0;
      #6000 $stop;       
      end


   
endmodule
module RISC_testbench;

   
wire	[7:0]bus_1_out;
reg	clk,rst;
wire	[7:0]Reg_R0_out;
wire	[7:0]Reg_R1_out;
wire	[7:0]Reg_R2_out;
wire	[7:0]Reg_R3_out;





RISC_core_mem_top top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);

 always#20 clk=~clk;
   
 initial
    begin
      clk=0;rst=1;
      #30 rst=0;
      #6000 $stop;       
      end


   
endmodule