data/full_repos/permissive/201488448/1_verilog/00_zero.v
 line:167: before: "/"
data/verilator_xmls/aeb546b5-6f9a-445b-ba98-eb2173a07243.xml
module top_module ( output zero );
	
	assign zero = 1'b0;
	
endmodule
module top_module ( output zero );

	
	assign zero = 1'b0;
	
endmodule