data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl/acquire/tart_acquire.v
None: at end of input
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl/acquire/tart_acquire.v:77: Cannot find include file: tartcfg.v\n `include "tartcfg.v" \n          ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl/acquire,data/full_repos/permissive/20430511/tartcfg.v\n             data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl/acquire,data/full_repos/permissive/20430511/tartcfg.v.v\n             data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl/acquire,data/full_repos/permissive/20430511/tartcfg.v.sv\n             tartcfg.v\n             tartcfg.v.v\n             tartcfg.v.sv\n             obj_dir/tartcfg.v\n             obj_dir/tartcfg.v.v\n             obj_dir/tartcfg.v.sv\n%Error: Exiting due to 1 error(s)\n'
module tart_acquire
#(
  parameter AXNUM = 24,
  parameter MSB   = AXNUM-1,


    parameter ABITS = 21,
    parameter ASB   = ABITS-1,


    parameter BBITS = 8,
    parameter BSB   = BBITS-1,
    parameter KBITS = BBITS*3,
    parameter KSB   = KBITS-1,
    parameter XBITS = 4,
    parameter XSB   = XBITS-1,


    parameter PIPED = 1,
    parameter CHECK = 1,
    parameter RESET = 0,


    parameter DELAY = 3,

    parameter integer C_M_AXIS_TDATA_WIDTH    = 32
  )
  (
    input          clock_i,
    input          reset_i,


    input          locked_i,
    input          strobe_i,
    input          middle_i,
    input [MSB:0]  signal_i,


    input          cyc_i,
    input          stb_i,
    input          we_i,
    output         ack_o,
    output         wat_o,
    output         rty_o,
    output         err_o,
    input [1:0]    adr_i,
    input [BSB:0]  dat_i,
    output [BSB:0] dat_o,

    input wire  M_AXIS_ACLK,
    input wire  M_AXIS_ARESETN,



    output wire  M_AXIS_TVALID,


    output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,



    output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,

    output wire  M_AXIS_TLAST,


    input wire  M_AXIS_TREADY,


    output         enabled_o,
    output         oflow_o,
    output [2:0]   state_o
  );





   wire            cyc_w, stb_w, ack_w;
   reg             ack = 1'b0;
   reg [BSB:0]     dat = {BBITS{1'b0}};
   wire [BSB:0]    dat_w;
   wire            fetch, store;



   wire [BSB:0]    aq_stream, aq_system;
   reg             en_acquire = 1'b0;



   wire [MSB:0]    data_in;
   wire            request;
   reg             mcb_err = 1'b0, mcb_wat = 1'b0, active = 1'b0;
   wire [2:0]      cap_state;



   reg             data_sent = 1'b0;
   reg [1:0]       index = 2'h0;
   wire            send, wrap_index, oflow;
   wire [2:0]      next_index;





   assign enabled_o  = en_acquire;
   assign oflow_o    = oflow;
   assign state_o    = cap_state;







   assign aq_stream  = index == 2'b00 ? data_in[23:16] :
   index == 2'b01 ? data_in[15: 8] :
   data_in[7:0];


   assign aq_system  = {en_acquire, axis_active, 0, 0, oflow, cap_state};




   assign ack_o      = ack;
   assign wat_o      = 1'b0;
   assign rty_o      = 1'b0;
   assign err_o      = 1'b0;
   assign dat_o      = dat;


   assign cyc_w      = CHECK ? cyc_i : 1'b1;
   assign stb_w      = cyc_w && stb_i;
   assign ack_w      = PIPED ? stb_w : stb_w && !ack;
   assign dat_w      = dat;


   assign fetch      = PIPED ? stb_w && !we_i : stb_w && !we_i &&  ack;
   assign store      = PIPED ? stb_w &&  we_i : stb_w &&  we_i && !ack;





   assign send       = fetch && adr_i == `AQ_STREAM && active;
   assign wrap_index = index == 2'b10;
   assign next_index = wrap_index ? 3'h0 : index + 1;









   always @(posedge clock_i)
   begin
     if (reset_i && RESET)
       ack <= #DELAY 1'b0;
     else
       ack <= #DELAY ack_w;
   end


   always @(posedge clock_i)
   begin
     if (stb_w)
     begin
       case (adr_i)
	 `AQ_STREAM: dat <= #DELAY 0;
	 `AQ_SYSTEM: dat <= #DELAY aq_system;
	 default:    dat <= #DELAY 8'bx;
       endcase
     end
   end

   always @(posedge clock_i)
   begin
     if (reset_i)
     begin
       en_acquire <= #DELAY 1'b0;
     end
     else if (store)
     begin
       case (adr_i)
	 `AQ_SYSTEM: en_acquire <= #DELAY dat_i[BSB];
       endcase
     end
   end

   wire fifo_empty;
   wire [MSB:0] fifo_data_o;

   afifo_gray 
   #( 
     .WIDTH(AXNUM),
     .ABITS(8),
     .DELAY(DELAY)
   ) fifo ( 
     .rst_i(reset_i),

     .wr_clk_i(clock_i),
     .wr_en_i(en_acquire),
     .wr_data_i(signal_i),
     .wfull_o(oflow),

     .rd_clk_i(M_AXIS_ACLK),
     .rd_en_i(axis_tvalid && M_AXIS_TREADY),
     .rd_data_o(fifo_data_o),
     .rempty_o(fifo_empty)
   );

   localparam NUMBER_OF_OUTPUT_WORDS = 31;

   reg [7 : 0]  read_pointer;

   wire  	axis_tvalid;
   reg  	axis_tlast;
   reg 	        axis_active;

   assign axis_tvalid   = axis_active && !fifo_empty;

   assign M_AXIS_TVALID	= axis_tvalid;
   assign M_AXIS_TDATA	= fifo_data_o;
   assign M_AXIS_TLAST	= axis_tlast;
   assign M_AXIS_TSTRB	= {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};

   always@(posedge M_AXIS_ACLK)
   begin
     if(!M_AXIS_ARESETN)
     begin
       axis_active <= 0;
       read_pointer <= 0;
       axis_tlast <= 0;
     end
     else
     begin
       if (!axis_active)
       begin
	 axis_active <= 1;
       end
       else if (axis_active && read_pointer < NUMBER_OF_OUTPUT_WORDS)
       begin
	 if (axis_tvalid && M_AXIS_TREADY)
	 begin
	   if (read_pointer == NUMBER_OF_OUTPUT_WORDS-1)
	     axis_tlast <= 1;

	   read_pointer <= read_pointer + 1;
	 end
       end
       else 
       begin
	 axis_active <= 0;
	 axis_tlast <= 0;
	 read_pointer <= 0;
       end
     end
   end

 endmodule
module tart_acquire
#(
  parameter AXNUM = 24,
  parameter MSB   = AXNUM-1,


    parameter ABITS = 21,
    parameter ASB   = ABITS-1,


    parameter BBITS = 8,
    parameter BSB   = BBITS-1,
    parameter KBITS = BBITS*3,
    parameter KSB   = KBITS-1,
    parameter XBITS = 4,
    parameter XSB   = XBITS-1,


    parameter PIPED = 1,
    parameter CHECK = 1,
    parameter RESET = 0,


    parameter DELAY = 3,

    parameter integer C_M_AXIS_TDATA_WIDTH    = 32
  )
  (
    input          clock_i,
    input          reset_i,


    input          locked_i,
    input          strobe_i,
    input          middle_i,
    input [MSB:0]  signal_i,


    input          cyc_i,
    input          stb_i,
    input          we_i,
    output         ack_o,
    output         wat_o,
    output         rty_o,
    output         err_o,
    input [1:0]    adr_i,
    input [BSB:0]  dat_i,
    output [BSB:0] dat_o,

    input wire  M_AXIS_ACLK,
    input wire  M_AXIS_ARESETN,



    output wire  M_AXIS_TVALID,


    output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,



    output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,

    output wire  M_AXIS_TLAST,


    input wire  M_AXIS_TREADY,


    output         enabled_o,
    output         oflow_o,
    output [2:0]   state_o
  );






   wire            cyc_w, stb_w, ack_w;
   reg             ack = 1'b0;
   reg [BSB:0]     dat = {BBITS{1'b0}};
   wire [BSB:0]    dat_w;
   wire            fetch, store;



   wire [BSB:0]    aq_stream, aq_system;
   reg             en_acquire = 1'b0;



   wire [MSB:0]    data_in;
   wire            request;
   reg             mcb_err = 1'b0, mcb_wat = 1'b0, active = 1'b0;
   wire [2:0]      cap_state;



   reg             data_sent = 1'b0;
   reg [1:0]       index = 2'h0;
   wire            send, wrap_index, oflow;
   wire [2:0]      next_index;





   assign enabled_o  = en_acquire;
   assign oflow_o    = oflow;
   assign state_o    = cap_state;







   assign aq_stream  = index == 2'b00 ? data_in[23:16] :
   index == 2'b01 ? data_in[15: 8] :
   data_in[7:0];


   assign aq_system  = {en_acquire, axis_active, 0, 0, oflow, cap_state};




   assign ack_o      = ack;
   assign wat_o      = 1'b0;
   assign rty_o      = 1'b0;
   assign err_o      = 1'b0;
   assign dat_o      = dat;


   assign cyc_w      = CHECK ? cyc_i : 1'b1;
   assign stb_w      = cyc_w && stb_i;
   assign ack_w      = PIPED ? stb_w : stb_w && !ack;
   assign dat_w      = dat;


   assign fetch      = PIPED ? stb_w && !we_i : stb_w && !we_i &&  ack;
   assign store      = PIPED ? stb_w &&  we_i : stb_w &&  we_i && !ack;





   assign send       = fetch && adr_i == `AQ_STREAM && active;
   assign wrap_index = index == 2'b10;
   assign next_index = wrap_index ? 3'h0 : index + 1;









   always @(posedge clock_i)
   begin
     if (reset_i && RESET)
       ack <= #DELAY 1'b0;
     else
       ack <= #DELAY ack_w;
   end


   always @(posedge clock_i)
   begin
     if (stb_w)
     begin
       case (adr_i)
	 `AQ_STREAM: dat <= #DELAY 0;
	 `AQ_SYSTEM: dat <= #DELAY aq_system;
	 default:    dat <= #DELAY 8'bx;
       endcase
     end
   end

   always @(posedge clock_i)
   begin
     if (reset_i)
     begin
       en_acquire <= #DELAY 1'b0;
     end
     else if (store)
     begin
       case (adr_i)
	 `AQ_SYSTEM: en_acquire <= #DELAY dat_i[BSB];
       endcase
     end
   end

   wire fifo_empty;
   wire [MSB:0] fifo_data_o;

   afifo_gray 
   #( 
     .WIDTH(AXNUM),
     .ABITS(8),
     .DELAY(DELAY)
   ) fifo ( 
     .rst_i(reset_i),

     .wr_clk_i(clock_i),
     .wr_en_i(en_acquire),
     .wr_data_i(signal_i),
     .wfull_o(oflow),

     .rd_clk_i(M_AXIS_ACLK),
     .rd_en_i(axis_tvalid && M_AXIS_TREADY),
     .rd_data_o(fifo_data_o),
     .rempty_o(fifo_empty)
   );

   localparam NUMBER_OF_OUTPUT_WORDS = 31;

   reg [7 : 0]  read_pointer;

   wire  	axis_tvalid;
   reg  	axis_tlast;
   reg 	        axis_active;

   assign axis_tvalid   = axis_active && !fifo_empty;

   assign M_AXIS_TVALID	= axis_tvalid;
   assign M_AXIS_TDATA	= fifo_data_o;
   assign M_AXIS_TLAST	= axis_tlast;
   assign M_AXIS_TSTRB	= {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};

   always@(posedge M_AXIS_ACLK)
   begin
     if(!M_AXIS_ARESETN)
     begin
       axis_active <= 0;
       read_pointer <= 0;
       axis_tlast <= 0;
     end
     else
     begin
       if (!axis_active)
       begin
	 axis_active <= 1;
       end
       else if (axis_active && read_pointer < NUMBER_OF_OUTPUT_WORDS)
       begin
	 if (axis_tvalid && M_AXIS_TREADY)
	 begin
	   if (read_pointer == NUMBER_OF_OUTPUT_WORDS-1)
	     axis_tlast <= 1;

	   read_pointer <= read_pointer + 1;
	 end
       end
       else 
       begin
	 axis_active <= 0;
	 axis_tlast <= 0;
	 read_pointer <= 0;
       end
     end
   end

 endmodule