data/full_repos/permissive/211891954/Finite States Machine/Maquina de Moore/Exemplo 1/moore.v
 line:9: before: ","
1: b'%Error: Cannot find file containing module: States\n        ... Looked in:\n             data/full_repos/permissive/211891954/Finite/States\n             data/full_repos/permissive/211891954/Finite/States.v\n             data/full_repos/permissive/211891954/Finite/States.sv\n             States\n             States.v\n             States.sv\n             obj_dir/States\n             obj_dir/States.v\n             obj_dir/States.sv\n%Error: Cannot find file containing module: Machine/Maquina\n%Error: Cannot find file containing module: de\n%Error: Cannot find file containing module: Moore/Exemplo\n%Error: Cannot find file containing module: 1,data/full_repos/permissive/211891954\n%Error: Cannot find file containing module: data/full_repos/permissive/211891954/Finite\n%Error: Cannot find file containing module: 1/moore.v\n%Error: Exiting due to 7 error(s)\n'
module odd_even(clk,rst,in,fim_impar,fim_par);
    input wire clk,rst,in;
    output reg fim_par,fim_impar;
    parameter  par = 1'b0,
              impar =1'b1;

    reg estados;
    reg proximo_estado;
    reg cont_impar = 0,cont_par = 0;

    always @(rst  or in or posedge clk) begin
        if(rst)begin
           estados = par; 
        end
        else begin
            case(estados)
                par:begin
                    if(in == 1'b1)begin
                        proximo_estado=impar;
                        cont_impar = cont_impar + 1'b1;
                    end  
                    else
                        proximo_estado=impar;
                end
                impar:begin
                    if(in == 1'b1)begin
                        proximo_estado=impar;
                        cont_par = cont_par + 1'b1;
                    end
                    else
                        proximo_estado=impar;
                end
            endcase 
        end
    end

    always @(estados)begin
        case (estados)
            fim_par:begin
                fim_par=cont_par;
            end
            fim_impar:begin
                fim_impar= cont_impar;
            end  
        endcase
    end
endmodule
module odd_even(clk,rst,in,fim_impar,fim_par);

    input wire clk,rst,in;
    output reg fim_par,fim_impar;
    parameter  par = 1'b0,
              impar =1'b1;

    reg estados;
    reg proximo_estado;
    reg cont_impar = 0,cont_par = 0;

    always @(rst  or in or posedge clk) begin
        if(rst)begin
           estados = par; 
        end
        else begin
            case(estados)
                par:begin
                    if(in == 1'b1)begin
                        proximo_estado=impar;
                        cont_impar = cont_impar + 1'b1;
                    end  
                    else
                        proximo_estado=impar;
                end
                impar:begin
                    if(in == 1'b1)begin
                        proximo_estado=impar;
                        cont_par = cont_par + 1'b1;
                    end
                    else
                        proximo_estado=impar;
                end
            endcase 
        end
    end

    always @(estados)begin
        case (estados)
            fim_par:begin
                fim_par=cont_par;
            end
            fim_impar:begin
                fim_impar= cont_impar;
            end  
        endcase
    end
endmodule