data/full_repos/permissive/125927162/7SEG/7seg_tb.v
 line:32: before: "$"
1: b'%Error: data/full_repos/permissive/125927162/7SEG/7seg_tb.v:27: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("sseg.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/7SEG/7seg_tb.v:28: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, sseg_tb);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/7SEG/7seg_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/7SEG/7seg_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n   always #5 in = in + 1;\n          ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sseg_tb ();
   reg [3:0] in;
   wire [6:0] out;
   reg 	      oe;

   sseg DUT(
	    .in(in),
	    .out_q(out),
	    .oe(oe)
	    );
   initial begin
      $dumpfile("sseg.vcd");
      $dumpvars(0, sseg_tb);
      in = 0;
      oe = 1;
      #100
	$finish;
   end
   always #5 in = in + 1;
endmodule
module sseg_tb ();

   reg [3:0] in;
   wire [6:0] out;
   reg 	      oe;

   sseg DUT(
	    .in(in),
	    .out_q(out),
	    .oe(oe)
	    );
   initial begin
      $dumpfile("sseg.vcd");
      $dumpvars(0, sseg_tb);
      in = 0;
      oe = 1;
      #100
	$finish;
   end
   always #5 in = in + 1;
endmodule