data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera/de1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera/de1.v:238: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'SW\' generates 10 bits.\n                                                                                                                                                : ... In instance de1\nassign x = SW;\n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera/de1.v:239: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'y\' generates 16 bits.\n                                                                                                                                                : ... In instance de1\nassign LEDR = y;\n            ^\n%Error: data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera/de1.v:241: Cannot find file containing module: \'isqrt\'\nisqrt isqrt\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera,data/full_repos/permissive/110151336/isqrt\n             data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera,data/full_repos/permissive/110151336/isqrt.v\n             data/full_repos/permissive/110151336/lab_10/src/lab_10_2_isqrt/old_yuri_panchul_example/007_pipelined_16_stages/altera,data/full_repos/permissive/110151336/isqrt.sv\n             isqrt\n             isqrt.v\n             isqrt.sv\n             obj_dir/isqrt\n             obj_dir/isqrt.v\n             obj_dir/isqrt.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module de1
	(

		CLOCK_24,
		CLOCK_27,
		CLOCK_50,
		EXT_CLOCK,

		KEY,

		SW,

		HEX0,
		HEX1,
		HEX2,
		HEX3,

		LEDG,
		LEDR,

		UART_TXD,
		UART_RXD,

		DRAM_DQ,
		DRAM_ADDR,
		DRAM_LDQM,
		DRAM_UDQM,
		DRAM_WE_N,
		DRAM_CAS_N,
		DRAM_RAS_N,
		DRAM_CS_N,
		DRAM_BA_0,
		DRAM_BA_1,
		DRAM_CLK,
		DRAM_CKE,

		FL_DQ,
		FL_ADDR,
		FL_WE_N,
		FL_RST_N,
		FL_OE_N,
		FL_CE_N,

		SRAM_DQ,
		SRAM_ADDR,
		SRAM_UB_N,
		SRAM_LB_N,
		SRAM_WE_N,
		SRAM_CE_N,
		SRAM_OE_N,

		SD_DAT,
		SD_DAT3,
		SD_CMD,
		SD_CLK,

		TDI,
		TCK,
		TCS,
	    TDO,

		I2C_SDAT,
		I2C_SCLK,

		PS2_DAT,
		PS2_CLK,

		VGA_HS,
		VGA_VS,
		VGA_R,
		VGA_G,
		VGA_B,

		AUD_ADCLRCK,
		AUD_ADCDAT,
		AUD_DACLRCK,
		AUD_DACDAT,
		AUD_BCLK,
		AUD_XCK,

		GPIO_0,
		GPIO_1
	);


input	[1:0]	CLOCK_24;
input	[1:0]	CLOCK_27;
input			CLOCK_50;
input			EXT_CLOCK;

input	[3:0]	KEY;

input	[9:0]	SW;

output	[6:0]	HEX0;
output	[6:0]	HEX1;
output	[6:0]	HEX2;
output	[6:0]	HEX3;

output	[7:0]	LEDG;
output	[9:0]	LEDR;

output			UART_TXD;
input			UART_RXD;

inout	[15:0]	DRAM_DQ;
output	[11:0]	DRAM_ADDR;
output			DRAM_LDQM;
output			DRAM_UDQM;
output			DRAM_WE_N;
output			DRAM_CAS_N;
output			DRAM_RAS_N;
output			DRAM_CS_N;
output			DRAM_BA_0;
output			DRAM_BA_1;
output			DRAM_CLK;
output			DRAM_CKE;

inout	[7:0]	FL_DQ;
output	[21:0]	FL_ADDR;
output			FL_WE_N;
output			FL_RST_N;
output			FL_OE_N;
output			FL_CE_N;

inout	[15:0]	SRAM_DQ;
output	[17:0]	SRAM_ADDR;
output			SRAM_UB_N;
output			SRAM_LB_N;
output			SRAM_WE_N;
output			SRAM_CE_N;
output			SRAM_OE_N;

inout			SD_DAT;
inout			SD_DAT3;
inout			SD_CMD;
output			SD_CLK;

inout			I2C_SDAT;
output			I2C_SCLK;

input		 	PS2_DAT;
input			PS2_CLK;

input  			TDI;
input  			TCK;
input  			TCS;
output 			TDO;

output			VGA_HS;
output			VGA_VS;
output	[3:0]	VGA_R;
output	[3:0]	VGA_G;
output	[3:0]	VGA_B;

inout			AUD_ADCLRCK;
input			AUD_ADCDAT;
inout			AUD_DACLRCK;
output			AUD_DACDAT;
inout			AUD_BCLK;
output			AUD_XCK;

inout	[35:0]	GPIO_0;
inout	[35:0]	GPIO_1;



`ifdef COMMENTED_OUT

assign	HEX0		=	7'h00;
assign	HEX1		=	7'h00;
assign	HEX2		=	7'h00;
assign	HEX3		=	7'h00;
assign	LEDG		=	8'hFF;
assign	LEDR		=	10'h3FF;

`endif


assign	DRAM_DQ		=	16'hzzzz;
assign	FL_DQ		=	8'hzz;
assign	SRAM_DQ		=	16'hzzzz;
assign	SD_DAT		=	1'bz;
assign	I2C_SDAT	=	1'bz;
assign	AUD_ADCLRCK	=	1'bz;
assign	AUD_DACLRCK	=	1'bz;
assign	AUD_BCLK	=	1'bz;
assign	GPIO_0		=	36'hzzzzzzzzz;
assign	GPIO_1		=	36'hzzzzzzzzz;



wire [31:0] x;
wire [15:0] y;

assign x = SW;
assign LEDR = y;

isqrt isqrt
(               
    .clock   ( CLOCK_50 ),
    .reset_n ( KEY [3]  ),
    .x       ( x        ),
    .y       ( y        )
);

endmodule
module de1
	(

		CLOCK_24,
		CLOCK_27,
		CLOCK_50,
		EXT_CLOCK,

		KEY,

		SW,

		HEX0,
		HEX1,
		HEX2,
		HEX3,

		LEDG,
		LEDR,

		UART_TXD,
		UART_RXD,

		DRAM_DQ,
		DRAM_ADDR,
		DRAM_LDQM,
		DRAM_UDQM,
		DRAM_WE_N,
		DRAM_CAS_N,
		DRAM_RAS_N,
		DRAM_CS_N,
		DRAM_BA_0,
		DRAM_BA_1,
		DRAM_CLK,
		DRAM_CKE,

		FL_DQ,
		FL_ADDR,
		FL_WE_N,
		FL_RST_N,
		FL_OE_N,
		FL_CE_N,

		SRAM_DQ,
		SRAM_ADDR,
		SRAM_UB_N,
		SRAM_LB_N,
		SRAM_WE_N,
		SRAM_CE_N,
		SRAM_OE_N,

		SD_DAT,
		SD_DAT3,
		SD_CMD,
		SD_CLK,

		TDI,
		TCK,
		TCS,
	    TDO,

		I2C_SDAT,
		I2C_SCLK,

		PS2_DAT,
		PS2_CLK,

		VGA_HS,
		VGA_VS,
		VGA_R,
		VGA_G,
		VGA_B,

		AUD_ADCLRCK,
		AUD_ADCDAT,
		AUD_DACLRCK,
		AUD_DACDAT,
		AUD_BCLK,
		AUD_XCK,

		GPIO_0,
		GPIO_1
	);



input	[1:0]	CLOCK_24;
input	[1:0]	CLOCK_27;
input			CLOCK_50;
input			EXT_CLOCK;

input	[3:0]	KEY;

input	[9:0]	SW;

output	[6:0]	HEX0;
output	[6:0]	HEX1;
output	[6:0]	HEX2;
output	[6:0]	HEX3;

output	[7:0]	LEDG;
output	[9:0]	LEDR;

output			UART_TXD;
input			UART_RXD;

inout	[15:0]	DRAM_DQ;
output	[11:0]	DRAM_ADDR;
output			DRAM_LDQM;
output			DRAM_UDQM;
output			DRAM_WE_N;
output			DRAM_CAS_N;
output			DRAM_RAS_N;
output			DRAM_CS_N;
output			DRAM_BA_0;
output			DRAM_BA_1;
output			DRAM_CLK;
output			DRAM_CKE;

inout	[7:0]	FL_DQ;
output	[21:0]	FL_ADDR;
output			FL_WE_N;
output			FL_RST_N;
output			FL_OE_N;
output			FL_CE_N;

inout	[15:0]	SRAM_DQ;
output	[17:0]	SRAM_ADDR;
output			SRAM_UB_N;
output			SRAM_LB_N;
output			SRAM_WE_N;
output			SRAM_CE_N;
output			SRAM_OE_N;

inout			SD_DAT;
inout			SD_DAT3;
inout			SD_CMD;
output			SD_CLK;

inout			I2C_SDAT;
output			I2C_SCLK;

input		 	PS2_DAT;
input			PS2_CLK;

input  			TDI;
input  			TCK;
input  			TCS;
output 			TDO;

output			VGA_HS;
output			VGA_VS;
output	[3:0]	VGA_R;
output	[3:0]	VGA_G;
output	[3:0]	VGA_B;

inout			AUD_ADCLRCK;
input			AUD_ADCDAT;
inout			AUD_DACLRCK;
output			AUD_DACDAT;
inout			AUD_BCLK;
output			AUD_XCK;

inout	[35:0]	GPIO_0;
inout	[35:0]	GPIO_1;



`ifdef COMMENTED_OUT

assign	HEX0		=	7'h00;
assign	HEX1		=	7'h00;
assign	HEX2		=	7'h00;
assign	HEX3		=	7'h00;
assign	LEDG		=	8'hFF;
assign	LEDR		=	10'h3FF;

`endif


assign	DRAM_DQ		=	16'hzzzz;
assign	FL_DQ		=	8'hzz;
assign	SRAM_DQ		=	16'hzzzz;
assign	SD_DAT		=	1'bz;
assign	I2C_SDAT	=	1'bz;
assign	AUD_ADCLRCK	=	1'bz;
assign	AUD_DACLRCK	=	1'bz;
assign	AUD_BCLK	=	1'bz;
assign	GPIO_0		=	36'hzzzzzzzzz;
assign	GPIO_1		=	36'hzzzzzzzzz;



wire [31:0] x;
wire [15:0] y;

assign x = SW;
assign LEDR = y;

isqrt isqrt
(               
    .clock   ( CLOCK_50 ),
    .reset_n ( KEY [3]  ),
    .x       ( x        ),
    .y       ( y        )
);

endmodule