data/full_repos/permissive/174155074/combinational-logic/decoders-and-encoders/decoder-3-8/decoder-3-8-tb.v
1: b'%Error: data/full_repos/permissive/174155074/combinational-logic/decoders-and-encoders/decoder-3-8/decoder-3-8-tb.v:20: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("decoder-3-8-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/combinational-logic/decoders-and-encoders/decoder-3-8/decoder-3-8-tb.v:21: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, decoder_3_8_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/decoders-and-encoders/decoder-3-8/decoder-3-8-tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decoder_3_8_tb;


reg     [2:0] IN;
wire    [7:0] OUT;
integer i;


decoder_3_8 uut(
    .in(IN),
    .out(OUT)
);


initial begin
    $dumpfile("decoder-3-8-tb.vcd");
    $dumpvars(0, decoder_3_8_tb);
end


initial begin
    $display("test start");
    IN = 3'b000;

    for (i = 0; i < 8; i = i + 1) begin
        IN = i;
        #10;
    end
    
    $display("test complete");
    $finish;
end

endmodule
module decoder_3_8_tb;



reg     [2:0] IN;
wire    [7:0] OUT;
integer i;


decoder_3_8 uut(
    .in(IN),
    .out(OUT)
);


initial begin
    $dumpfile("decoder-3-8-tb.vcd");
    $dumpvars(0, decoder_3_8_tb);
end


initial begin
    $display("test start");
    IN = 3'b000;

    for (i = 0; i < 8; i = i + 1) begin
        IN = i;
        #10;
    end
    
    $display("test complete");
    $finish;
end

endmodule