data/full_repos/permissive/214278225/1_LEDs/knightRider/knightRider.v
1: b'%Warning-WIDTH: data/full_repos/permissive/214278225/1_LEDs/knightRider/knightRider.v:27: Operator SUB expects 32 or 25 bits on the LHS, but LHS\'s VARREF \'COUNT\' generates 22 bits.\n                                                                                        : ... In instance knightRider\n end else if(counter == COUNT -1) begin\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module knightRider(clk, rst, dataOut);

input clk, rst;
output reg [7:0] dataOut;

reg [24:0] counter, counterNext;
reg [ 7:0] dataOutNext;
reg flag,flagNxt;
parameter COUNT = 22'h3FFFFF;


always @(posedge clk) begin
	counter <= #1 counterNext;
	dataOut <= #1 dataOutNext;
	flag <= #1 flagNxt;
end

always @(*) begin
	dataOutNext = dataOut;
	counterNext = counter +1;
	flagNxt = flag;
	if(rst) begin
		dataOutNext = 8'b0000_0001;
		counterNext = 0;
		flagNxt = 0;
	end else if(counter == COUNT -1) begin
		case(flag)
			0: dataOutNext = dataOut << 1;
			1: dataOutNext = dataOut >> 1;
		endcase
	end else begin
		if(dataOut== 8'b1000_0000)
			flagNxt = 1;
		else if (dataOut == 8'b000_0001)
			flagNxt = 0;
			
	end
	
end
endmodule
module knightRider(clk, rst, dataOut);


input clk, rst;
output reg [7:0] dataOut;

reg [24:0] counter, counterNext;
reg [ 7:0] dataOutNext;
reg flag,flagNxt;
parameter COUNT = 22'h3FFFFF;


always @(posedge clk) begin
	counter <= #1 counterNext;
	dataOut <= #1 dataOutNext;
	flag <= #1 flagNxt;
end

always @(*) begin
	dataOutNext = dataOut;
	counterNext = counter +1;
	flagNxt = flag;
	if(rst) begin
		dataOutNext = 8'b0000_0001;
		counterNext = 0;
		flagNxt = 0;
	end else if(counter == COUNT -1) begin
		case(flag)
			0: dataOutNext = dataOut << 1;
			1: dataOutNext = dataOut >> 1;
		endcase
	end else begin
		if(dataOut== 8'b1000_0000)
			flagNxt = 1;
		else if (dataOut == 8'b000_0001)
			flagNxt = 0;
			
	end
	
end
endmodule