data/full_repos/permissive/217697217/problems/04_hex_display/hex_display.v
data/verilator_xmls/f4a9ab16-4c9d-40a1-965b-847d150bbca3.xml
module hex_display(
    input clk,
    input [15:0]data,

    output [3:0]anodes,
    output [6:0]segments
);



reg [1:0]i = 0;

assign anodes = (4'b1 << i);

always @(posedge clk) begin
    i <= i + 2'b1;
end

wire [3:0]b = data[i * 4 +: 4];
hex_to_seg hex_to_seg(.data(b), .segments(segments));

endmodule
module hex_display(
    input clk,
    input [15:0]data,

    output [3:0]anodes,
    output [6:0]segments
);




reg [1:0]i = 0;

assign anodes = (4'b1 << i);

always @(posedge clk) begin
    i <= i + 2'b1;
end

wire [3:0]b = data[i * 4 +: 4];
hex_to_seg hex_to_seg(.data(b), .segments(segments));

endmodule