data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/MBE/testbench.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/MBE/testbench.sv:20: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/MBE/testbench.sv:20: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mbe_1x
(
input [2:0] x,
output single, double, neg
);

assign single = (x[1] & ~x[0]) | (~x[1] & x[0]);
assign double = (x[2] & ~x[1] & ~x[0]) | (~x[2] & x[1] & x[0]);
assign neg    = x[2];

endmodule
module mbe_1x
(
input [2:0] x,
output single, double, neg
);


assign single = (x[1] & ~x[0]) | (~x[1] & x[0]);
assign double = (x[2] & ~x[1] & ~x[0]) | (~x[2] & x[1] & x[0]);
assign neg    = x[2];

endmodule