data/full_repos/permissive/112626266/our_top_module.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/112626266/our_top_module.v:6: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112626266/our_top_module.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/112626266/our_top_module.v:75: Cannot find file containing module: \'PC\'\n PC pc1(clk , next_PC , PCWrite , current_PC);\n ^~\n        ... Looked in:\n             data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC\n             data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC.v\n             data/full_repos/permissive/112626266,data/full_repos/permissive/112626266/PC.sv\n             PC\n             PC.v\n             PC.sv\n             obj_dir/PC\n             obj_dir/PC.v\n             obj_dir/PC.sv\n%Error: data/full_repos/permissive/112626266/our_top_module.v:80: Cannot find file containing module: \'Instruction_Memory\'\n Instruction_Memory imem(current_PC , Instruction, addent);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:87: Cannot find file containing module: \'IFID\'\n IFID IFID1(clk , Instruction ,IFIDWrite , PC_from_Adder , Instruction_to_ID , PC_from_Adder_to_ID);\n ^~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:121: Cannot find file containing module: \'decode\'\n decode d1(clk , WBRegRd , WBreg2 , M , EXRegRt , Write_Data , PC_from_Adder_to_ID , Instruction_to_ID ,\n ^~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:176: Cannot find file containing module: \'EXMEM\'\n EXMEM emem1(clk,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);\n ^~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:192: Cannot find file containing module: \'Data_Memory\'\n Data_Memory dm1(.Clock(clk) , .Address(ALUreg) , .Write_Data(WriteDataOut) , .MemWrite(MemWrite) , .MemRead(MemRead) , \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:217: Cannot find file containing module: \'MEMWB\'\n MEMWB mwb(.clock(clk) , .WB(WBreg) , .Memout(Read_Data) , .ALUOut(ALUreg) , .RegRD(RegRDreg) , \n ^~~~~\n%Error: data/full_repos/permissive/112626266/our_top_module.v:223: Cannot find file containing module: \'ExBrunch\'\n ExBrunch EXBranch(.clock(clk),.datatowrite(Write_Data),.MEMALUOut(ALUreg),.DEXWB(DecodeWB) ,.DEXM(DecodeM),.DEXEX(EX),\n ^~~~~~~~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Adder(in1 , in2 , out);
	input[31:0] in1;
	input[31:0] in2;
	output[31:0] out;
	assign out = in1 + in2;
endmodule
module Adder(in1 , in2 , out);

	input[31:0] in1;
	input[31:0] in2;
	output[31:0] out;
	assign out = in1 + in2;
endmodule