data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/program_counter.v
data/verilator_xmls/18018ee8-1d27-4488-8aa5-531f1f54dfe3.xml
module program_counter(input wire clk, input wire reset, input wire [31:0] next_pc, output reg [31:0] pc);


initial begin
    pc = 32'b0;
end


always@(posedge clk or posedge reset) begin
    if(reset==1'b1) pc = 32'b0;
    else pc = next_pc;
end
endmodule
module program_counter(input wire clk, input wire reset, input wire [31:0] next_pc, output reg [31:0] pc);



initial begin
    pc = 32'b0;
end


always@(posedge clk or posedge reset) begin
    if(reset==1'b1) pc = 32'b0;
    else pc = next_pc;
end
endmodule