data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_Step.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_Step.v:63: Signal definition not found, creating implicitly: \'CLK_low\'\n        CLK_low_prev <= CLK_low;\n                        ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new/PMOD_Step.v:36: Cannot find file containing module: \'ClockDivider\'\n    ClockDivider #(\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new,data/full_repos/permissive/189468210/ClockDivider\n             data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new,data/full_repos/permissive/189468210/ClockDivider.v\n             data/full_repos/permissive/189468210/PMOD.srcs/sources_1/new,data/full_repos/permissive/189468210/ClockDivider.sv\n             ClockDivider\n             ClockDivider.v\n             ClockDivider.sv\n             obj_dir/ClockDivider\n             obj_dir/ClockDivider.v\n             obj_dir/ClockDivider.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module PMOD_Step (
    input CLK,
    input RST_N,

    input DIR,
    input ENB,
    
    output stepped,
    
    output SIG1,
    output SIG2,
    output SIG3,
    output SIG4
    );


    ClockDivider #(
        .TARGET_CLOCK_FREQ (1000)
        ) 
        step_clk_div (
        .CLK        (CLK),
        .RST_N      (RST_N),
        .CLK_Out    (CLK_low)
        );
        
    reg[3:0] signal;
    
    assign SIG1 = signal[0];
    assign SIG2 = signal[1];
    assign SIG3 = signal[2];
    assign SIG4 = signal[3];

    localparam st1 = 3'b000;
    localparam st2 = 3'b001;
    localparam st3 = 3'b011;
    localparam st4 = 3'b010;
    localparam st5 = 3'b110;
    localparam st6 = 3'b111;
    localparam st7 = 3'b101;
    localparam st8 = 3'b100;
    
    reg CLK_low_prev;
    always @(posedge CLK) begin
        CLK_low_prev <= CLK_low;
    end
    
    assign stepped = (CLK_low != CLK_low_prev) && ENB;
    
    reg [2:0] present_state, next_state;
    
    always @(present_state, DIR, ENB)
    begin
        if (ENB) begin
            case(present_state)
                st1: next_state = DIR ? st2 : st8;
                st2: next_state = DIR ? st3 : st1;
                st3: next_state = DIR ? st4 : st2;
                st4: next_state = DIR ? st5 : st3;
                st5: next_state = DIR ? st6 : st4;
                st6: next_state = DIR ? st7 : st5;
                st7: next_state = DIR ? st8 : st6;
                st8: next_state = DIR ? st1 : st7;
            endcase
        end
        else begin
            next_state = present_state;
        end
    end

    always @(posedge CLK_low)
    begin
        if (!RST_N) begin
            present_state = st1;
        end
        else begin 
            present_state = next_state;
        end
    end

    always @(posedge CLK_low)
    begin
        case (present_state)
            st1: signal <= 4'b1000;
            st2: signal <= 4'b1100;
            st3: signal <= 4'b0100;
            st4: signal <= 4'b0110;
            st5: signal <= 4'b0010;
            st6: signal <= 4'b0011;
            st7: signal <= 4'b0001;
            st8: signal <= 4'b1001;
        endcase
    end
    
endmodule
module PMOD_Step (
    input CLK,
    input RST_N,

    input DIR,
    input ENB,
    
    output stepped,
    
    output SIG1,
    output SIG2,
    output SIG3,
    output SIG4
    );



    ClockDivider #(
        .TARGET_CLOCK_FREQ (1000)
        ) 
        step_clk_div (
        .CLK        (CLK),
        .RST_N      (RST_N),
        .CLK_Out    (CLK_low)
        );
        
    reg[3:0] signal;
    
    assign SIG1 = signal[0];
    assign SIG2 = signal[1];
    assign SIG3 = signal[2];
    assign SIG4 = signal[3];

    localparam st1 = 3'b000;
    localparam st2 = 3'b001;
    localparam st3 = 3'b011;
    localparam st4 = 3'b010;
    localparam st5 = 3'b110;
    localparam st6 = 3'b111;
    localparam st7 = 3'b101;
    localparam st8 = 3'b100;
    
    reg CLK_low_prev;
    always @(posedge CLK) begin
        CLK_low_prev <= CLK_low;
    end
    
    assign stepped = (CLK_low != CLK_low_prev) && ENB;
    
    reg [2:0] present_state, next_state;
    
    always @(present_state, DIR, ENB)
    begin
        if (ENB) begin
            case(present_state)
                st1: next_state = DIR ? st2 : st8;
                st2: next_state = DIR ? st3 : st1;
                st3: next_state = DIR ? st4 : st2;
                st4: next_state = DIR ? st5 : st3;
                st5: next_state = DIR ? st6 : st4;
                st6: next_state = DIR ? st7 : st5;
                st7: next_state = DIR ? st8 : st6;
                st8: next_state = DIR ? st1 : st7;
            endcase
        end
        else begin
            next_state = present_state;
        end
    end

    always @(posedge CLK_low)
    begin
        if (!RST_N) begin
            present_state = st1;
        end
        else begin 
            present_state = next_state;
        end
    end

    always @(posedge CLK_low)
    begin
        case (present_state)
            st1: signal <= 4'b1000;
            st2: signal <= 4'b1100;
            st3: signal <= 4'b0100;
            st4: signal <= 4'b0110;
            st5: signal <= 4'b0010;
            st6: signal <= 4'b0011;
            st7: signal <= 4'b0001;
            st8: signal <= 4'b1001;
        endcase
    end
    
endmodule