data/full_repos/permissive/150266237/parte1.v
 line:157: before: "$"
1: b'%Error: data/full_repos/permissive/150266237/parte1.v:138: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile ("out.vcd"); \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/150266237/parte1.v:139: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars; \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/150266237/parte1.v:145: Unsupported or unknown PLI call: $monitor\n     $monitor($time," c %b res %b a %b s %d smem %d sporta %d",c,res,a,saida,saida1,saida2);\n     ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:146: Unsupported: Ignoring delay on this delayed statement.\n      #1 res=0; a=2\'b10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:147: Unsupported: Ignoring delay on this delayed statement.\n      #1 res=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:148: Unsupported: Ignoring delay on this delayed statement.\n      #1 a=2\'b10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:149: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b11;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:150: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b01;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:151: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b00;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:152: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b11;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:153: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b00;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:154: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b00;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:155: Unsupported: Ignoring delay on this delayed statement.\n      #4 a=2\'b01;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte1.v:156: Unsupported: Ignoring delay on this delayed statement.\n      #4\n      ^\n%Error: Exiting due to 3 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stateMem(input clk,input res, input[1:0] a, output [2:0] saida);
reg [5:0] StateMachine [0:31];
initial
begin

StateMachine[0] = 6'h01;   StateMachine[1] = 6'h02;
StateMachine[2] = 6'h01;   StateMachine[3] = 6'h05;
StateMachine[4] = 6'h0A;   StateMachine[5] = 6'h0A;
StateMachine[6] = 6'h0B;   StateMachine[7] = 6'h0B;
StateMachine[8] = 6'h10;   StateMachine[9] = 6'h14;
StateMachine[10] = 6'h17;  StateMachine[11] = 6'h13;
StateMachine[12] = 6'h1A;  StateMachine[13] = 6'h1A;
StateMachine[14] = 6'h1A;  StateMachine[15] = 6'h1D;
StateMachine[16] = 6'h20;  StateMachine[17] = 6'h23;
StateMachine[18] = 6'h23;  StateMachine[19] = 6'h23;
StateMachine[20] = 6'h28;  StateMachine[21] = 6'h2B;
StateMachine[22] = 6'h2B;  StateMachine[23] = 6'h2E;
StateMachine[24] = 6'h30;  StateMachine[25] = 6'h33;
StateMachine[26] = 6'h33;  StateMachine[27] = 6'h33;
StateMachine[28] = 6'h1A;  StateMachine[29] = 6'h1A;
StateMachine[30] = 6'h19;  StateMachine[31] = 6'h1B;
end
wire [4:0] address;
wire [5:0] dout;
assign address[0] = a[0];
assign address[1] = a[1];
assign dout = StateMachine[address];
assign saida = dout[5:3];

ff st0(dout[0],clk,res,address[2]);
ff st1(dout[1],clk,res,address[3]);
ff st2(dout[2],clk,res,address[4]);

endmodule
module stateMem(input clk,input res, input[1:0] a, output [2:0] saida);

reg [5:0] StateMachine [0:31];
initial
begin

StateMachine[0] = 6'h01;   StateMachine[1] = 6'h02;
StateMachine[2] = 6'h01;   StateMachine[3] = 6'h05;
StateMachine[4] = 6'h0A;   StateMachine[5] = 6'h0A;
StateMachine[6] = 6'h0B;   StateMachine[7] = 6'h0B;
StateMachine[8] = 6'h10;   StateMachine[9] = 6'h14;
StateMachine[10] = 6'h17;  StateMachine[11] = 6'h13;
StateMachine[12] = 6'h1A;  StateMachine[13] = 6'h1A;
StateMachine[14] = 6'h1A;  StateMachine[15] = 6'h1D;
StateMachine[16] = 6'h20;  StateMachine[17] = 6'h23;
StateMachine[18] = 6'h23;  StateMachine[19] = 6'h23;
StateMachine[20] = 6'h28;  StateMachine[21] = 6'h2B;
StateMachine[22] = 6'h2B;  StateMachine[23] = 6'h2E;
StateMachine[24] = 6'h30;  StateMachine[25] = 6'h33;
StateMachine[26] = 6'h33;  StateMachine[27] = 6'h33;
StateMachine[28] = 6'h1A;  StateMachine[29] = 6'h1A;
StateMachine[30] = 6'h19;  StateMachine[31] = 6'h1B;
end
wire [4:0] address;
wire [5:0] dout;
assign address[0] = a[0];
assign address[1] = a[1];
assign dout = StateMachine[address];
assign saida = dout[5:3];

ff st0(dout[0],clk,res,address[2]);
ff st1(dout[1],clk,res,address[3]);
ff st2(dout[2],clk,res,address[4]);

endmodule