data/full_repos/permissive/109594910/example-8k.v
 line:17: before: "("
1: b'%Error: data/full_repos/permissive/109594910/example-8k.v:51: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile("top_tb.vcd");\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/109594910/example-8k.v:52: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0,top_tb);\n     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:54: Unsupported: Ignoring delay on this delayed statement.\n     # 10000 sel = 1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:55: Unsupported: Ignoring delay on this delayed statement.\n     # 10000 sel = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:56: Unsupported: Ignoring delay on this delayed statement.\n     # 30000 $finish;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/109594910/example-8k.v:61: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = !clk;\n         ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top (
    input clk,
    input sel,
    output LED1,
    output LED2,
    output LED3,
    output LED4,
    output LED5,
    output LED6,
    output LED7,
    output LED8
);

    localparam BITS = 8;
    localparam LOG2DELAY = 22;
    
    function [BITS-1:0] bin2gray(input [BITS+1:0] in);
        integer i;
        reg [BITS+1:0] temp;
        begin
            temp = in;
            for (i=0; i<BITS; i=i+1)
                bin2gray[i] = ^temp[i +: 2];
        end
    endfunction
    

    reg [BITS+LOG2DELAY-1:0] counter = 0; 
    
    always@(posedge clk)
        counter <= counter + 1;
        
    
    reg [31:0] rng = 32'h00010000; 
    
    always@(posedge counter[LOG2DELAY-2]) rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});
        
        
    assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8} = sel ? rng[14:7] : bin2gray(counter >> LOG2DELAY-1);
    
    
    
endmodule
module top (
    input clk,
    input sel,
    output LED1,
    output LED2,
    output LED3,
    output LED4,
    output LED5,
    output LED6,
    output LED7,
    output LED8
);


    localparam BITS = 8;
    localparam LOG2DELAY = 22;
    
    function [BITS-1:0] bin2gray(input [BITS+1:0] in);
        integer i;
        reg [BITS+1:0] temp;
        begin
            temp = in;
            for (i=0; i<BITS; i=i+1)
                bin2gray[i] = ^temp[i +: 2];
        end
    endfunction
    

    reg [BITS+LOG2DELAY-1:0] counter = 0; 
    
    always@(posedge clk)
        counter <= counter + 1;
        
    
    reg [31:0] rng = 32'h00010000; 
    
    always@(posedge counter[LOG2DELAY-2]) rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});
        
        
    assign {LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8} = sel ? rng[14:7] : bin2gray(counter >> LOG2DELAY-1);
    
    
    
endmodule