data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/tb_CacheSim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/tb_CacheSim.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #CLOCK_WIDTH clk = FALSE;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/tb_CacheSim.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #CLOCK_WIDTH clk = TRUE;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/tb_CacheSim.v:72: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_WIDTH clk = FALSE;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/tb_CacheSim.v:80: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_WIDTH clk = TRUE;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/tb_CacheSim.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #CLOCK_WIDTH clk = FALSE;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/tb_CacheSim.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #CLOCK_WIDTH clk = TRUE;\n  ^\n%Error: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/tb_CacheSim.v:33: Cannot find file containing module: \'CACHE_SIMULATION\'\n CACHE_SIMULATION cache_sim(\n ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source,data/full_repos/permissive/153690221/CACHE_SIMULATION\n             data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source,data/full_repos/permissive/153690221/CACHE_SIMULATION.v\n             data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source,data/full_repos/permissive/153690221/CACHE_SIMULATION.sv\n             CACHE_SIMULATION\n             CACHE_SIMULATION.v\n             CACHE_SIMULATION.sv\n             obj_dir/CACHE_SIMULATION\n             obj_dir/CACHE_SIMULATION.v\n             obj_dir/CACHE_SIMULATION.sv\n%Warning-WIDTH: data/full_repos/permissive/153690221/dropbox/baddam_bourquin_ethakota_finalproject/Source/tb_CacheSim.v:65: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                                                          : ... In instance tb_CacheSim\n  address = 32\'b0;\n          ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_CacheSim();
	

	parameter CLOCK_CYCLE = 20;
	parameter CLOCK_WIDTH = CLOCK_CYCLE/2;

	parameter TRUE = 1'b1;
	parameter FALSE = 1'b0;
	parameter RESET = 4'd8;
	
	reg clk;
	integer fptr;
	reg done;
	reg [3:0] command;
	reg [`AddressBits-1:0] address;
	reg  [8*100:0] filename;
	reg mode;
	integer result; 

	CACHE_SIMULATION cache_sim(
		.clk(clk),
		.command(command),
		.address(address),
		.mode(mode),
		.done(done)
		);
		
	initial
	begin
		clk = FALSE;
		done = FALSE;


		if($value$plusargs("TRACE=%s", filename) == FALSE)
		begin
			$display("Please enter a valid trace file name on plusargs");
			$finish;
		end
		

		fptr = $fopen(filename , "r");	
		
		if($value$plusargs("MODE=%d",  mode) == FALSE)
		begin        
			$display("Please enter a valid mode on plusargs!");        
			$finish;
		end
		

		#CLOCK_WIDTH clk = FALSE;
		command = RESET;
		address = 32'b0;
		#CLOCK_WIDTH clk = TRUE;
		

		while(!$feof(fptr))
		begin

			#CLOCK_WIDTH clk = FALSE;
			result = $fscanf(fptr,"%d", command);
			

			if(command != 8 && command != 9)
			begin
				result = $fscanf(fptr,"%h", address);
			end
			#CLOCK_WIDTH clk = TRUE;
		end


		$fclose(fptr);
		
		#CLOCK_WIDTH clk = FALSE;
		done = TRUE;
		#CLOCK_WIDTH clk = TRUE;
		$stop;
	end
endmodule
module tb_CacheSim();

	

	parameter CLOCK_CYCLE = 20;
	parameter CLOCK_WIDTH = CLOCK_CYCLE/2;

	parameter TRUE = 1'b1;
	parameter FALSE = 1'b0;
	parameter RESET = 4'd8;
	
	reg clk;
	integer fptr;
	reg done;
	reg [3:0] command;
	reg [`AddressBits-1:0] address;
	reg  [8*100:0] filename;
	reg mode;
	integer result; 

	CACHE_SIMULATION cache_sim(
		.clk(clk),
		.command(command),
		.address(address),
		.mode(mode),
		.done(done)
		);
		
	initial
	begin
		clk = FALSE;
		done = FALSE;


		if($value$plusargs("TRACE=%s", filename) == FALSE)
		begin
			$display("Please enter a valid trace file name on plusargs");
			$finish;
		end
		

		fptr = $fopen(filename , "r");	
		
		if($value$plusargs("MODE=%d",  mode) == FALSE)
		begin        
			$display("Please enter a valid mode on plusargs!");        
			$finish;
		end
		

		#CLOCK_WIDTH clk = FALSE;
		command = RESET;
		address = 32'b0;
		#CLOCK_WIDTH clk = TRUE;
		

		while(!$feof(fptr))
		begin

			#CLOCK_WIDTH clk = FALSE;
			result = $fscanf(fptr,"%d", command);
			

			if(command != 8 && command != 9)
			begin
				result = $fscanf(fptr,"%h", address);
			end
			#CLOCK_WIDTH clk = TRUE;
		end


		$fclose(fptr);
		
		#CLOCK_WIDTH clk = FALSE;
		done = TRUE;
		#CLOCK_WIDTH clk = TRUE;
		$stop;
	end
endmodule