data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/chdr_resize.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/chdr_resize.v:148: syntax error, unexpected '(', expecting IDENTIFIER\n      ERROR__Invalid_CHDR_or_data_width_parameters();\n                                                   ^\n%Error: Exiting due to 1 error(s)\n"
module chdr_resize #(
  parameter I_CHDR_W = 64,
  parameter O_CHDR_W = 512,
  parameter I_DATA_W = I_CHDR_W,
  parameter O_DATA_W = O_CHDR_W,
  parameter USER_W   = 1,
  parameter PIPELINE = "NONE"
) (
  input wire clk,
  input wire rst,


  input  wire [I_DATA_W-1:0] i_chdr_tdata,
  input  wire [  USER_W-1:0] i_chdr_tuser,
  input  wire                i_chdr_tlast,
  input  wire                i_chdr_tvalid,
  output wire                i_chdr_tready,


  output wire [O_DATA_W-1:0] o_chdr_tdata,
  output wire [  USER_W-1:0] o_chdr_tuser,
  output wire                o_chdr_tlast,
  output wire                o_chdr_tvalid,
  input  wire                o_chdr_tready
);

  `define MIN(X, Y) ((X) < (Y) ? (X) : (Y))



  localparam CONVERT_W = `MIN(I_DATA_W, O_DATA_W);

  localparam DO_DOWNSIZE = (I_DATA_W > O_DATA_W);

  localparam DO_CONVERT = (I_CHDR_W != O_CHDR_W);

  localparam DO_UPSIZE = (I_DATA_W < O_DATA_W);









  localparam DOWNSIZE_PIPELINE =
    (PIPELINE == "IN"    &&  DO_CONVERT) ? "IN"    :
    (PIPELINE == "IN"    && !DO_CONVERT) ? "IN"    :
    (PIPELINE == "INOUT" &&  DO_CONVERT) ? "IN"    :
    (PIPELINE == "INOUT" && !DO_CONVERT) ? "INOUT" :
    (PIPELINE == "OUT"   &&  DO_CONVERT) ? "NONE"  :
    (PIPELINE == "OUT"   && !DO_CONVERT) ? "OUT"   :
                                           "NONE"  ;
  localparam CONVERT_PIPELINE =
    (PIPELINE == "IN"    &&  DO_DOWNSIZE) ? "IN"    :
    (PIPELINE == "IN"    &&  DO_UPSIZE  ) ? "INOUT" :
    (PIPELINE == "IN") ? "IN"    :
    (PIPELINE == "INOUT" &&  DO_DOWNSIZE) ? "INOUT" :
    (PIPELINE == "INOUT" &&  DO_UPSIZE  ) ? "INOUT" :
    (PIPELINE == "INOUT") ? "INOUT" :
    (PIPELINE == "OUT"   &&  DO_DOWNSIZE) ? "INOUT" :
    (PIPELINE == "OUT"   &&  DO_UPSIZE  ) ? "OUT"   :
    (PIPELINE == "OUT") ? "OUT"   :
                                            "NONE"  ;
  localparam UPSIZE_PIPELINE =
    (PIPELINE == "IN"    &&  DO_CONVERT) ? "NONE"  :
    (PIPELINE == "IN"    && !DO_CONVERT) ? "IN"    :
    (PIPELINE == "INOUT" &&  DO_CONVERT) ? "OUT"   :
    (PIPELINE == "INOUT" && !DO_CONVERT) ? "INOUT" :
    (PIPELINE == "OUT"   &&  DO_CONVERT) ? "OUT"   :
    (PIPELINE == "OUT"   && !DO_CONVERT) ? "OUT"   :
                                           "NONE"  ;


  generate





    if (!(

      (2**$clog2(I_CHDR_W) == I_CHDR_W) &&
      (2**$clog2(O_CHDR_W) == O_CHDR_W) &&
      (2**$clog2(I_DATA_W) == I_DATA_W) &&
      (2**$clog2(O_DATA_W) == O_DATA_W) &&
      (I_CHDR_W >= 64) &&
      (O_CHDR_W >= 64) &&
      (I_DATA_W >= 64) &&
      (O_DATA_W >= 64) &&


      (CONVERT_W == `MIN(I_CHDR_W, O_CHDR_W))
    )) begin : gen_error
      ERROR__Invalid_CHDR_or_data_width_parameters();
    end











    if (DO_DOWNSIZE || DO_UPSIZE || DO_CONVERT || PIPELINE == "INOUT") begin : gen_tuser_buffer
      if (!DO_DOWNSIZE && !DO_UPSIZE && DO_CONVERT && PIPELINE == "NONE") begin : gen_tuser_reg




        reg o_chdr_sop = 1;
        always @(posedge clk) begin
          if (rst) begin
            o_chdr_sop <= 1;
          end else if (o_chdr_tvalid && o_chdr_tready) begin
            o_chdr_sop <= o_chdr_tlast;
          end
        end

        reg [USER_W-1:0] o_tuser_reg;
        always @(posedge clk) begin
          if (rst) begin
            o_tuser_reg <= {USER_W{1'bX}};
          end else if (o_chdr_tvalid && o_chdr_tready && o_chdr_sop) begin
            o_tuser_reg <= i_chdr_tuser;
          end
        end



        assign o_chdr_tuser = (o_chdr_sop) ? i_chdr_tuser : o_tuser_reg;

      end else begin : gen_tuser_fifo



        reg i_chdr_sop = 1;
        always @(posedge clk) begin
          if (rst) begin
            i_chdr_sop <= 1;
          end else if (i_chdr_tvalid && i_chdr_tready) begin
            i_chdr_sop <= i_chdr_tlast;
          end
        end

        axi_fifo_short #(
          .WIDTH (USER_W)
        ) axi_fifo_short_i (
          .clk      (clk),
          .reset    (rst),
          .clear    (1'b0),
          .i_tdata  (i_chdr_tuser),
          .i_tvalid (i_chdr_tvalid && i_chdr_tready && i_chdr_sop),
          .i_tready (),
          .o_tdata  (o_chdr_tuser),
          .o_tvalid (),
          .o_tready (o_chdr_tready && o_chdr_tvalid && o_chdr_tlast),
          .space    (),
          .occupied ()
        );
      end
    end else begin : gen_tuser_pass_through


      assign o_chdr_tuser = i_chdr_tuser;
    end






    wire [CONVERT_W-1:0] resized_tdata;
    wire                 resized_tlast;
    wire                 resized_tvalid;
    wire                 resized_tready;

    if (DO_DOWNSIZE) begin : gen_bus_downsize
      axis_width_conv #(
        .WORD_W    (CONVERT_W),
        .IN_WORDS  (I_DATA_W / CONVERT_W),
        .OUT_WORDS (1),
        .SYNC_CLKS (1),
        .PIPELINE  (DOWNSIZE_PIPELINE)
      ) axis_width_conv_i (
        .s_axis_aclk   (clk),
        .s_axis_rst    (rst),
        .s_axis_tdata  (i_chdr_tdata),
        .s_axis_tkeep  ({(I_DATA_W / CONVERT_W){1'b1}}),
        .s_axis_tlast  (i_chdr_tlast),
        .s_axis_tvalid (i_chdr_tvalid),
        .s_axis_tready (i_chdr_tready),
        .m_axis_aclk   (clk),
        .m_axis_rst    (rst),
        .m_axis_tdata  (resized_tdata),
        .m_axis_tkeep  (),
        .m_axis_tlast  (resized_tlast),
        .m_axis_tvalid (resized_tvalid),
        .m_axis_tready (resized_tready)
      );
    end else begin : gen_no_bus_downsize
      assign resized_tdata  = i_chdr_tdata;
      assign resized_tlast  = i_chdr_tlast;
      assign resized_tvalid = i_chdr_tvalid;
      assign i_chdr_tready  = resized_tready;
    end






    wire [CONVERT_W-1:0] converted_tdata;
    wire                 converted_tlast;
    wire                 converted_tvalid;
    wire                 converted_tready;

    if (DO_CONVERT) begin : gen_convert
      if (I_CHDR_W > O_CHDR_W) begin : gen_chdr_convert_down
        chdr_convert_down #(
          .I_CHDR_W (I_CHDR_W),
          .DATA_W   (CONVERT_W),
          .PIPELINE (CONVERT_PIPELINE)
        ) chdr_convert_down_i (
          .clk           (clk),
          .rst           (rst),
          .i_chdr_tdata  (resized_tdata),
          .i_chdr_tlast  (resized_tlast),
          .i_chdr_tvalid (resized_tvalid),
          .i_chdr_tready (resized_tready),
          .o_chdr_tdata  (o_chdr_tdata),
          .o_chdr_tlast  (o_chdr_tlast),
          .o_chdr_tvalid (o_chdr_tvalid),
          .o_chdr_tready (o_chdr_tready)
        );
      end else if (I_CHDR_W < O_CHDR_W) begin : gen_chdr_convert_up
        chdr_convert_up #(
          .DATA_W   (CONVERT_W),
          .O_CHDR_W (O_CHDR_W),
          .PIPELINE (PIPELINE)
        ) chdr_convert_up_i (
          .clk           (clk),
          .rst           (rst),
          .i_chdr_tdata  (resized_tdata),
          .i_chdr_tlast  (resized_tlast),
          .i_chdr_tvalid (resized_tvalid),
          .i_chdr_tready (resized_tready),
          .o_chdr_tdata  (converted_tdata),
          .o_chdr_tlast  (converted_tlast),
          .o_chdr_tvalid (converted_tvalid),
          .o_chdr_tready (converted_tready)
        );
      end
    end else begin : gen_no_convert
      if (PIPELINE == "INOUT" && !DO_DOWNSIZE && !DO_UPSIZE) begin : gen_pipeline



        axi_fifo_flop2 #(
          .WIDTH (1 + CONVERT_W)
        ) axi_fifo_flop2_i (
          .clk      (clk),
          .reset    (rst),
          .clear    (1'b0),
          .i_tdata  ({ resized_tlast, resized_tdata }),
          .i_tvalid (resized_tvalid),
          .i_tready (resized_tready),
          .o_tdata  ({ converted_tlast, converted_tdata }),
          .o_tvalid (converted_tvalid),
          .o_tready (converted_tready),
          .space    (),
          .occupied ()
        );
      end else begin : gen_convert_bypass
        assign converted_tdata  = resized_tdata;
        assign converted_tlast  = resized_tlast;
        assign converted_tvalid = resized_tvalid;
        assign resized_tready   = converted_tready;
      end
    end






    if (DO_UPSIZE) begin : gen_bus_upsize
      axis_width_conv #(
        .WORD_W    (CONVERT_W),
        .IN_WORDS  (1),
        .OUT_WORDS (O_DATA_W / CONVERT_W),
        .SYNC_CLKS (1),
        .PIPELINE  (UPSIZE_PIPELINE)
      ) axis_width_conv_i (
        .s_axis_aclk   (clk),
        .s_axis_rst    (rst),
        .s_axis_tdata  (converted_tdata),
        .s_axis_tkeep  (1'b1),
        .s_axis_tlast  (converted_tlast),
        .s_axis_tvalid (converted_tvalid),
        .s_axis_tready (converted_tready),
        .m_axis_aclk   (clk),
        .m_axis_rst    (rst),
        .m_axis_tdata  (o_chdr_tdata),
        .m_axis_tkeep  (),
        .m_axis_tlast  (o_chdr_tlast),
        .m_axis_tvalid (o_chdr_tvalid),
        .m_axis_tready (o_chdr_tready)
      );
    end else begin : gen_no_bus_upsize
      assign o_chdr_tdata     = converted_tdata;
      assign o_chdr_tlast     = converted_tlast;
      assign o_chdr_tvalid    = converted_tvalid;
      assign converted_tready = o_chdr_tready;
    end

  endgenerate

endmodule
module chdr_resize #(
  parameter I_CHDR_W = 64,
  parameter O_CHDR_W = 512,
  parameter I_DATA_W = I_CHDR_W,
  parameter O_DATA_W = O_CHDR_W,
  parameter USER_W   = 1,
  parameter PIPELINE = "NONE"
) (
  input wire clk,
  input wire rst,


  input  wire [I_DATA_W-1:0] i_chdr_tdata,
  input  wire [  USER_W-1:0] i_chdr_tuser,
  input  wire                i_chdr_tlast,
  input  wire                i_chdr_tvalid,
  output wire                i_chdr_tready,


  output wire [O_DATA_W-1:0] o_chdr_tdata,
  output wire [  USER_W-1:0] o_chdr_tuser,
  output wire                o_chdr_tlast,
  output wire                o_chdr_tvalid,
  input  wire                o_chdr_tready
);


  `define MIN(X, Y) ((X) < (Y) ? (X) : (Y))



  localparam CONVERT_W = `MIN(I_DATA_W, O_DATA_W);

  localparam DO_DOWNSIZE = (I_DATA_W > O_DATA_W);

  localparam DO_CONVERT = (I_CHDR_W != O_CHDR_W);

  localparam DO_UPSIZE = (I_DATA_W < O_DATA_W);









  localparam DOWNSIZE_PIPELINE =
    (PIPELINE == "IN"    &&  DO_CONVERT) ? "IN"    :
    (PIPELINE == "IN"    && !DO_CONVERT) ? "IN"    :
    (PIPELINE == "INOUT" &&  DO_CONVERT) ? "IN"    :
    (PIPELINE == "INOUT" && !DO_CONVERT) ? "INOUT" :
    (PIPELINE == "OUT"   &&  DO_CONVERT) ? "NONE"  :
    (PIPELINE == "OUT"   && !DO_CONVERT) ? "OUT"   :
                                           "NONE"  ;
  localparam CONVERT_PIPELINE =
    (PIPELINE == "IN"    &&  DO_DOWNSIZE) ? "IN"    :
    (PIPELINE == "IN"    &&  DO_UPSIZE  ) ? "INOUT" :
    (PIPELINE == "IN") ? "IN"    :
    (PIPELINE == "INOUT" &&  DO_DOWNSIZE) ? "INOUT" :
    (PIPELINE == "INOUT" &&  DO_UPSIZE  ) ? "INOUT" :
    (PIPELINE == "INOUT") ? "INOUT" :
    (PIPELINE == "OUT"   &&  DO_DOWNSIZE) ? "INOUT" :
    (PIPELINE == "OUT"   &&  DO_UPSIZE  ) ? "OUT"   :
    (PIPELINE == "OUT") ? "OUT"   :
                                            "NONE"  ;
  localparam UPSIZE_PIPELINE =
    (PIPELINE == "IN"    &&  DO_CONVERT) ? "NONE"  :
    (PIPELINE == "IN"    && !DO_CONVERT) ? "IN"    :
    (PIPELINE == "INOUT" &&  DO_CONVERT) ? "OUT"   :
    (PIPELINE == "INOUT" && !DO_CONVERT) ? "INOUT" :
    (PIPELINE == "OUT"   &&  DO_CONVERT) ? "OUT"   :
    (PIPELINE == "OUT"   && !DO_CONVERT) ? "OUT"   :
                                           "NONE"  ;


  generate





    if (!(

      (2**$clog2(I_CHDR_W) == I_CHDR_W) &&
      (2**$clog2(O_CHDR_W) == O_CHDR_W) &&
      (2**$clog2(I_DATA_W) == I_DATA_W) &&
      (2**$clog2(O_DATA_W) == O_DATA_W) &&
      (I_CHDR_W >= 64) &&
      (O_CHDR_W >= 64) &&
      (I_DATA_W >= 64) &&
      (O_DATA_W >= 64) &&


      (CONVERT_W == `MIN(I_CHDR_W, O_CHDR_W))
    )) begin : gen_error
      ERROR__Invalid_CHDR_or_data_width_parameters();
    end











    if (DO_DOWNSIZE || DO_UPSIZE || DO_CONVERT || PIPELINE == "INOUT") begin : gen_tuser_buffer
      if (!DO_DOWNSIZE && !DO_UPSIZE && DO_CONVERT && PIPELINE == "NONE") begin : gen_tuser_reg




        reg o_chdr_sop = 1;
        always @(posedge clk) begin
          if (rst) begin
            o_chdr_sop <= 1;
          end else if (o_chdr_tvalid && o_chdr_tready) begin
            o_chdr_sop <= o_chdr_tlast;
          end
        end

        reg [USER_W-1:0] o_tuser_reg;
        always @(posedge clk) begin
          if (rst) begin
            o_tuser_reg <= {USER_W{1'bX}};
          end else if (o_chdr_tvalid && o_chdr_tready && o_chdr_sop) begin
            o_tuser_reg <= i_chdr_tuser;
          end
        end



        assign o_chdr_tuser = (o_chdr_sop) ? i_chdr_tuser : o_tuser_reg;

      end else begin : gen_tuser_fifo



        reg i_chdr_sop = 1;
        always @(posedge clk) begin
          if (rst) begin
            i_chdr_sop <= 1;
          end else if (i_chdr_tvalid && i_chdr_tready) begin
            i_chdr_sop <= i_chdr_tlast;
          end
        end

        axi_fifo_short #(
          .WIDTH (USER_W)
        ) axi_fifo_short_i (
          .clk      (clk),
          .reset    (rst),
          .clear    (1'b0),
          .i_tdata  (i_chdr_tuser),
          .i_tvalid (i_chdr_tvalid && i_chdr_tready && i_chdr_sop),
          .i_tready (),
          .o_tdata  (o_chdr_tuser),
          .o_tvalid (),
          .o_tready (o_chdr_tready && o_chdr_tvalid && o_chdr_tlast),
          .space    (),
          .occupied ()
        );
      end
    end else begin : gen_tuser_pass_through


      assign o_chdr_tuser = i_chdr_tuser;
    end






    wire [CONVERT_W-1:0] resized_tdata;
    wire                 resized_tlast;
    wire                 resized_tvalid;
    wire                 resized_tready;

    if (DO_DOWNSIZE) begin : gen_bus_downsize
      axis_width_conv #(
        .WORD_W    (CONVERT_W),
        .IN_WORDS  (I_DATA_W / CONVERT_W),
        .OUT_WORDS (1),
        .SYNC_CLKS (1),
        .PIPELINE  (DOWNSIZE_PIPELINE)
      ) axis_width_conv_i (
        .s_axis_aclk   (clk),
        .s_axis_rst    (rst),
        .s_axis_tdata  (i_chdr_tdata),
        .s_axis_tkeep  ({(I_DATA_W / CONVERT_W){1'b1}}),
        .s_axis_tlast  (i_chdr_tlast),
        .s_axis_tvalid (i_chdr_tvalid),
        .s_axis_tready (i_chdr_tready),
        .m_axis_aclk   (clk),
        .m_axis_rst    (rst),
        .m_axis_tdata  (resized_tdata),
        .m_axis_tkeep  (),
        .m_axis_tlast  (resized_tlast),
        .m_axis_tvalid (resized_tvalid),
        .m_axis_tready (resized_tready)
      );
    end else begin : gen_no_bus_downsize
      assign resized_tdata  = i_chdr_tdata;
      assign resized_tlast  = i_chdr_tlast;
      assign resized_tvalid = i_chdr_tvalid;
      assign i_chdr_tready  = resized_tready;
    end






    wire [CONVERT_W-1:0] converted_tdata;
    wire                 converted_tlast;
    wire                 converted_tvalid;
    wire                 converted_tready;

    if (DO_CONVERT) begin : gen_convert
      if (I_CHDR_W > O_CHDR_W) begin : gen_chdr_convert_down
        chdr_convert_down #(
          .I_CHDR_W (I_CHDR_W),
          .DATA_W   (CONVERT_W),
          .PIPELINE (CONVERT_PIPELINE)
        ) chdr_convert_down_i (
          .clk           (clk),
          .rst           (rst),
          .i_chdr_tdata  (resized_tdata),
          .i_chdr_tlast  (resized_tlast),
          .i_chdr_tvalid (resized_tvalid),
          .i_chdr_tready (resized_tready),
          .o_chdr_tdata  (o_chdr_tdata),
          .o_chdr_tlast  (o_chdr_tlast),
          .o_chdr_tvalid (o_chdr_tvalid),
          .o_chdr_tready (o_chdr_tready)
        );
      end else if (I_CHDR_W < O_CHDR_W) begin : gen_chdr_convert_up
        chdr_convert_up #(
          .DATA_W   (CONVERT_W),
          .O_CHDR_W (O_CHDR_W),
          .PIPELINE (PIPELINE)
        ) chdr_convert_up_i (
          .clk           (clk),
          .rst           (rst),
          .i_chdr_tdata  (resized_tdata),
          .i_chdr_tlast  (resized_tlast),
          .i_chdr_tvalid (resized_tvalid),
          .i_chdr_tready (resized_tready),
          .o_chdr_tdata  (converted_tdata),
          .o_chdr_tlast  (converted_tlast),
          .o_chdr_tvalid (converted_tvalid),
          .o_chdr_tready (converted_tready)
        );
      end
    end else begin : gen_no_convert
      if (PIPELINE == "INOUT" && !DO_DOWNSIZE && !DO_UPSIZE) begin : gen_pipeline



        axi_fifo_flop2 #(
          .WIDTH (1 + CONVERT_W)
        ) axi_fifo_flop2_i (
          .clk      (clk),
          .reset    (rst),
          .clear    (1'b0),
          .i_tdata  ({ resized_tlast, resized_tdata }),
          .i_tvalid (resized_tvalid),
          .i_tready (resized_tready),
          .o_tdata  ({ converted_tlast, converted_tdata }),
          .o_tvalid (converted_tvalid),
          .o_tready (converted_tready),
          .space    (),
          .occupied ()
        );
      end else begin : gen_convert_bypass
        assign converted_tdata  = resized_tdata;
        assign converted_tlast  = resized_tlast;
        assign converted_tvalid = resized_tvalid;
        assign resized_tready   = converted_tready;
      end
    end






    if (DO_UPSIZE) begin : gen_bus_upsize
      axis_width_conv #(
        .WORD_W    (CONVERT_W),
        .IN_WORDS  (1),
        .OUT_WORDS (O_DATA_W / CONVERT_W),
        .SYNC_CLKS (1),
        .PIPELINE  (UPSIZE_PIPELINE)
      ) axis_width_conv_i (
        .s_axis_aclk   (clk),
        .s_axis_rst    (rst),
        .s_axis_tdata  (converted_tdata),
        .s_axis_tkeep  (1'b1),
        .s_axis_tlast  (converted_tlast),
        .s_axis_tvalid (converted_tvalid),
        .s_axis_tready (converted_tready),
        .m_axis_aclk   (clk),
        .m_axis_rst    (rst),
        .m_axis_tdata  (o_chdr_tdata),
        .m_axis_tkeep  (),
        .m_axis_tlast  (o_chdr_tlast),
        .m_axis_tvalid (o_chdr_tvalid),
        .m_axis_tready (o_chdr_tready)
      );
    end else begin : gen_no_bus_upsize
      assign o_chdr_tdata     = converted_tdata;
      assign o_chdr_tlast     = converted_tlast;
      assign o_chdr_tvalid    = converted_tvalid;
      assign converted_tready = o_chdr_tready;
    end

  endgenerate

endmodule