data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v
 line:49: before: "cl"
1: b'%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:35: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("counter_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:36: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 ck = ~ck;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:48: syntax error, unexpected \'@\'\n        @(negedge ck)\n        ^\n%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:53: syntax error, unexpected \'@\'\n        repeat(20) @(negedge ck);\n                   ^\n%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:55: syntax error, unexpected \'@\'\n        repeat(8) @(negedge ck);\n                  ^\n%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:58: syntax error, unexpected \'@\'\n        @(negedge ck);\n        ^\n%Error: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-2_contador/counter_tb.v:60: syntax error, unexpected \'@\'\n        repeat(2) @(negedge ck);\n                  ^\n%Error: Exiting due to 7 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ();

    reg ck = 0;
    reg cl = 0;
    reg en = 0;
    reg ud = 0;
    wire [3:0] q;
    wire c;

    counter #(4) uut(.ck(ck), .cl(cl), .en(en), .ud(ud), .q(q), .c(c));


    initial    begin

        $dumpfile("counter_tb.vcd");
        $dumpvars(0, test);


    end



    always
        #10 ck = ~ck;


    initial begin
        @(negedge ck)
        cl = 1;
        @(negedge ck)
        cl = 0;
        en = 1;
        repeat(20) @(negedge ck);
        ud = 1;
        repeat(8) @(negedge ck);
        en = 0;
        cl = 1;
        @(negedge ck);
        cl = 0;
        repeat(2) @(negedge ck);
        $finish;
    end

endmodule
module test ();


    reg ck = 0;
    reg cl = 0;
    reg en = 0;
    reg ud = 0;
    wire [3:0] q;
    wire c;

    counter #(4) uut(.ck(ck), .cl(cl), .en(en), .ud(ud), .q(q), .c(c));


    initial    begin

        $dumpfile("counter_tb.vcd");
        $dumpvars(0, test);


    end



    always
        #10 ck = ~ck;


    initial begin
        @(negedge ck)
        cl = 1;
        @(negedge ck)
        cl = 0;
        en = 1;
        repeat(20) @(negedge ck);
        ud = 1;
        repeat(8) @(negedge ck);
        en = 0;
        cl = 1;
        @(negedge ck);
        cl = 0;
        repeat(2) @(negedge ck);
        $finish;
    end

endmodule