data/full_repos/permissive/211316121/lab5_2/TransFF.v
data/verilator_xmls/75e9f43b-e33a-4aff-85cf-98cd7b56ec35.xml
module DFF(
	input d,
	input clk,
	input clr,
	input set,
	output reg q,
	output nq
);

always@(posedge clk,posedge set,posedge clr)
begin
	if(set)
		q<=1;
	else if(clr)
		q<=0;
	else
		q<=d;
end

assign nq=~q;

endmodule
module DFF(
	input d,
	input clk,
	input clr,
	input set,
	output reg q,
	output nq
);


always@(posedge clk,posedge set,posedge clr)
begin
	if(set)
		q<=1;
	else if(clr)
		q<=0;
	else
		q<=d;
end

assign nq=~q;

endmodule