data/full_repos/permissive/114459345/srcCache/pc_reg.v
1: b'%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:10: Define or directive not defined: \'`CtrlWidth\'\n input wire[`CtrlWidth] stall,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`CtrlWidth] stall,\n                      ^\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`InstAddrBus] pc_i,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:14: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] pc_i,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:17: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus] pc,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:25: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:26: Define or directive not defined: \'`ChipDisable\'\n   ce <= `ChipDisable;    \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:29: Define or directive not defined: \'`ChipEnable\'\n   ce <= `ChipEnable;    \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:36: Define or directive not defined: \'`ChipDisable\'\n  if(ce == `ChipDisable) begin\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:37: Define or directive not defined: \'`ZeroWord\'\n   pc <= `ZeroWord;    \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:39: Define or directive not defined: \'`Jump\'\n  else if(jumpout == `Jump) begin\n                     ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:42: Define or directive not defined: \'`PC_BIT\'\n  else if(stall[`PC_BIT] == `Stop) begin\n                ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:42: Define or directive not defined: \'`Stop\'\n  else if(stall[`PC_BIT] == `Stop) begin\n                            ^~~~~\n%Error: Exiting due to 14 error(s)\n'
module pc_reg(

	input wire clk,
	input wire rst,
	

	input wire[`CtrlWidth] stall,
	

	input wire jumpout,
	input wire[`InstAddrBus] pc_i,
	

	output reg[`InstAddrBus] pc,
	

	output reg ce
);
	
	always @ (posedge clk) begin

		if(rst == `RstEnable) begin
			ce <= `ChipDisable;
		end
		else begin
			ce <= `ChipEnable;
		end
	end
	

	always @ (posedge clk) begin

		if(ce == `ChipDisable) begin
			pc <= `ZeroWord;
		end
		else if(jumpout == `Jump) begin
			pc <= pc_i;
		end
		else if(stall[`PC_BIT] == `Stop) begin

		end								
		else begin
			pc <= pc + 4'h4;
		end	
	end
	
endmodule
module pc_reg(

	input wire clk,
	input wire rst,
	

	input wire[`CtrlWidth] stall,
	

	input wire jumpout,
	input wire[`InstAddrBus] pc_i,
	

	output reg[`InstAddrBus] pc,
	

	output reg ce
);

	
	always @ (posedge clk) begin

		if(rst == `RstEnable) begin
			ce <= `ChipDisable;
		end
		else begin
			ce <= `ChipEnable;
		end
	end
	

	always @ (posedge clk) begin

		if(ce == `ChipDisable) begin
			pc <= `ZeroWord;
		end
		else if(jumpout == `Jump) begin
			pc <= pc_i;
		end
		else if(stall[`PC_BIT] == `Stop) begin

		end								
		else begin
			pc <= pc + 4'h4;
		end	
	end
	
endmodule