data/full_repos/permissive/21203606/ex3/uart_tx_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/21203606/ex3/uart_tx_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10 tb_clk <= ~tb_clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21203606/ex3/uart_tx_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #40 tb_rst <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/21203606/ex3/uart_tx_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #40 tb_rst <= 1\'b0;\n ^\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx_tb.v:13: Cannot find file containing module: \'uart_tx\'\nuart_tx txi(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21203606/ex3,data/full_repos/permissive/21203606/uart_tx\n             data/full_repos/permissive/21203606/ex3,data/full_repos/permissive/21203606/uart_tx.v\n             data/full_repos/permissive/21203606/ex3,data/full_repos/permissive/21203606/uart_tx.sv\n             uart_tx\n             uart_tx.v\n             uart_tx.sv\n             obj_dir/uart_tx\n             obj_dir/uart_tx.v\n             obj_dir/uart_tx.sv\n%Error: data/full_repos/permissive/21203606/ex3/uart_tx_tb.v:21: Cannot find file containing module: \'uart_rx\'\nuart_rx rxi(\n^~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ex3_tb ();


reg		 tb_clk, tb_rst, tb_en;
wire  rdy;
wire  tb_dout;
wire  tb_valid;
reg [7:0] tb_cnt;
wire [7:0] tb_data_in;


uart_tx txi(
		.clk(tb_clk),
		.rst(tb_rst),
		.data_out(tb_cnt),
		.en(tb_en),
		.rdy(rdy),
		.dout(tb_dout));

uart_rx rxi(
    .clk(tb_clk),
    .rst(tb_rst),
    .din(tb_dout),
    .valid(tb_valid),
    .data_in(tb_data_in));

initial
begin
	tb_clk <= 1'b0;
	tb_rst <= 1'b0;
	tb_en <= 1'b0;
	tb_cnt <= 8'd0;
end


always
begin
	#10 tb_clk <= ~tb_clk;
end


initial
begin
	#40 tb_rst <= 1'b1;
	#40 tb_rst <= 1'b0;
end

always @(posedge tb_clk)
begin
	tb_en <= 1'b0;

	if(tb_en == 1'b0 && rdy == 1'b1)
	begin
		tb_cnt <= tb_cnt + 1;
		tb_en <= 1'b1;
	end
end


endmodule
module ex3_tb ();



reg		 tb_clk, tb_rst, tb_en;
wire  rdy;
wire  tb_dout;
wire  tb_valid;
reg [7:0] tb_cnt;
wire [7:0] tb_data_in;


uart_tx txi(
		.clk(tb_clk),
		.rst(tb_rst),
		.data_out(tb_cnt),
		.en(tb_en),
		.rdy(rdy),
		.dout(tb_dout));

uart_rx rxi(
    .clk(tb_clk),
    .rst(tb_rst),
    .din(tb_dout),
    .valid(tb_valid),
    .data_in(tb_data_in));

initial
begin
	tb_clk <= 1'b0;
	tb_rst <= 1'b0;
	tb_en <= 1'b0;
	tb_cnt <= 8'd0;
end


always
begin
	#10 tb_clk <= ~tb_clk;
end


initial
begin
	#40 tb_rst <= 1'b1;
	#40 tb_rst <= 1'b0;
end

always @(posedge tb_clk)
begin
	tb_en <= 1'b0;

	if(tb_en == 1'b0 && rdy == 1'b1)
	begin
		tb_cnt <= tb_cnt + 1;
		tb_en <= 1'b1;
	end
end


endmodule