data/full_repos/permissive/120518070/main/source/locSafe.sv
data/verilator_xmls/75f4eb8c-2e7b-4c0b-afcd-3fa7be091106.xml
module locSafe(
	input wire clk,
	input wire [7:0] locEnd_i,
	input wire store_loc_i,
	output reg [7:0] locSafe_o
);



always_ff @(posedge clk)
begin
	if (store_loc_i == 1)
	begin
		locSafe_o <= locEnd_i;
	end
	else
	begin
		locSafe_o <= locSafe_o;
	end
end
endmodule
module locSafe(
	input wire clk,
	input wire [7:0] locEnd_i,
	input wire store_loc_i,
	output reg [7:0] locSafe_o
);




always_ff @(posedge clk)
begin
	if (store_loc_i == 1)
	begin
		locSafe_o <= locEnd_i;
	end
	else
	begin
		locSafe_o <= locSafe_o;
	end
end
endmodule