data/full_repos/permissive/122125962/hardware/SDRv2_src_asyn_rst/idx_ctl.v
1: b'%Warning-WIDTH: data/full_repos/permissive/122125962/hardware/SDRv2_src_asyn_rst/idx_ctl.v:129: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s XOR generates 2 bits.\n                                                                                              : ... In instance idx_control\n      if ((current_owner ^ 2\'b10) && (tx_fifo_empty))\n                                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/122125962/hardware/SDRv2_src_asyn_rst/idx_ctl.v:280: Cannot find file containing module: \'crc\'\ncrc   tx_crc( .clk(HCLK), .nreset(HRESETn), .clear(crc_clear), .data_in(tx_fifo_dout), \n^~~\n        ... Looked in:\n             data/full_repos/permissive/122125962/hardware/SDRv2_src_asyn_rst,data/full_repos/permissive/122125962/crc\n             data/full_repos/permissive/122125962/hardware/SDRv2_src_asyn_rst,data/full_repos/permissive/122125962/crc.v\n             data/full_repos/permissive/122125962/hardware/SDRv2_src_asyn_rst,data/full_repos/permissive/122125962/crc.sv\n             crc\n             crc.v\n             crc.sv\n             obj_dir/crc\n             obj_dir/crc.v\n             obj_dir/crc.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module idx_control(	

	input HSEL, HWRITE, HMASTLOCK, HREADY, HRESETn, HCLK,
	input [31:0] HADDR, HWDATA,
	input [2:0] HSIZE, HBURST,
	input [3:0] HPROT,
	input [1:0] HTRANS,
	
	output HREADYOUT,
	output [1:0] HRESP,
	output [31:0] HRDATA,
	

	input			tx_fifo_full, 
	input			tx_fifo_empty,
	output reg [7:0]	tx_fifo_dout,
	output reg		tx_fifo_we,

	input	[1:0]	current_owner
);





reg		[1:0]	fsm;
reg				hwrite_reg;





reg				hready_reg;
reg		[2:0]	zero_cnt;
reg		[1:0]	pkt_state;
reg		[7:0]	pkt_len, pkt_cnt;
reg		[1:0]	pkt_end_state;
reg				crc_clear, crc_start;
reg		[1:0]	crc_state;
reg		[1:0]	crc_cnt;
wire	[15:0]	crc_result;
wire			crc_ready;


localparam RESET =		2'b00;
localparam LOAD_SFD =	2'b01;
localparam AHB_TRANS =	2'b10;
localparam CRC_ADD =	2'b11;

localparam CRC_LSB =	2'b00;
localparam CRC_MSB =	2'b01;
localparam PKT_DONE =	2'b10;

localparam CRC_START =	2'b00;
localparam CRC_WAIT =	2'b01;
localparam CRC_IDLE =	2'b10;
localparam CRC_DISABLE =2'b11;


assign HRESP		= 2'b00;
assign HREADYOUT	= (~tx_fifo_full) & hready_reg;
assign HRDATA		= 0;


always @ (posedge HCLK or negedge HRESETn)
begin
    if (~HRESETn)
    begin
		fsm			<= 2'b00;
		tx_fifo_dout<= 0;
		hwrite_reg  <= 0;
		tx_fifo_we	<= 0;
		hready_reg	<= 0;
		zero_cnt	<= 0;
		pkt_state	<= RESET;
		pkt_len		<= 0;
		pkt_cnt		<= 0;
		pkt_end_state <= CRC_LSB;
		crc_start	<= 0;
		crc_clear	<= 0;
		crc_state	<= CRC_IDLE;
		crc_cnt		<= 0;
    end
    else
    begin
		case (fsm)
		    2'b00:
		    begin
				case (pkt_state)
					RESET:
					begin
						if ((current_owner ^ 2'b10) && (tx_fifo_empty))
							pkt_state <= LOAD_SFD;
						zero_cnt <= 0;
						pkt_end_state <= CRC_LSB;
						crc_clear <= 1;
					end

					LOAD_SFD:
					begin
						zero_cnt <= zero_cnt + 1;
						crc_clear <= 0;
						if (zero_cnt<4)
						begin
							tx_fifo_we  <= 1;
							tx_fifo_dout <= 0;
						end
						else if (zero_cnt==4)
						begin
							tx_fifo_we  <= 1;
							tx_fifo_dout <= 8'ha7;
						end
						else
						begin
							pkt_state <= AHB_TRANS;
							hready_reg <= 1;
							tx_fifo_we  <= 0;
						end
					end

					AHB_TRANS:
					begin
						if (((pkt_len-1)==pkt_cnt) && (pkt_len>0))
							pkt_state <= CRC_ADD;
						else
						begin
							if (HSEL && HREADY && HTRANS[1] && HSIZE==3'b010)
							begin
								hwrite_reg	<= HWRITE;
								fsm			<= 2'b01;
								hready_reg	<= 0;
							end
						end
					end

					CRC_ADD:
					begin
						hready_reg <= 0;

						case (pkt_end_state)
							CRC_LSB:
							begin
								tx_fifo_we <= 1;
								tx_fifo_dout <= crc_result[7:0];
								pkt_end_state <= CRC_MSB;
							end

							CRC_MSB:
							begin
								tx_fifo_we <= 1;
								tx_fifo_dout <= crc_result[15:8];
								pkt_end_state <= PKT_DONE;
								crc_clear <= 1;
							end

							PKT_DONE:
							begin
								crc_clear <= 0;
								tx_fifo_we	<= 0;
								pkt_state <= RESET;
								pkt_cnt	<= 0;
								pkt_len	<= 0;
							end
						endcase
					end

					default:
					begin
						pkt_state <= RESET;
						tx_fifo_we	<= 0;
					end
				endcase
		    end

			2'b01:
			begin

				fsm	<= 2'b10;
				crc_cnt <= 0;
				if (hwrite_reg)
				begin
					if (pkt_cnt==0)
					begin
						pkt_len <= HWDATA[7:0];
						crc_state <= CRC_IDLE;
					end
					else
						crc_state <= CRC_START;
					pkt_cnt <= pkt_cnt + 1;
					tx_fifo_we <= 1;
					tx_fifo_dout <= HWDATA[7:0];
				end
				else
					tx_fifo_we	<= 0;
			end
		    
		    2'b10:
		    begin
				tx_fifo_we <= 0;
				case (crc_state)
					CRC_START:
					begin
						crc_start <= 1;
						crc_state <= CRC_DISABLE;
					end

					CRC_DISABLE:
					begin
						crc_start <= 0;
						crc_cnt <= crc_cnt + 1;
						if (crc_cnt==2'b10)
							crc_state <= CRC_WAIT;
					end

					CRC_WAIT:
					begin
						if (crc_ready)
						begin
							fsm <= 2'b11;
							crc_state <= CRC_IDLE;
						end

					end

					CRC_IDLE:
					begin
						fsm	<= 2'b11;
					end
				endcase
			end

			2'b11:
			begin
				hready_reg <= 1;
				fsm <= 2'b00;
				zero_cnt <= 0;
			end
		endcase
    end
end


crc			tx_crc(	.clk(HCLK), .nreset(HRESETn), .clear(crc_clear), .data_in(tx_fifo_dout), 
					.crc_out(crc_result), .start(crc_start), .out_ready(crc_ready));

endmodule
module idx_control(	

	input HSEL, HWRITE, HMASTLOCK, HREADY, HRESETn, HCLK,
	input [31:0] HADDR, HWDATA,
	input [2:0] HSIZE, HBURST,
	input [3:0] HPROT,
	input [1:0] HTRANS,
	
	output HREADYOUT,
	output [1:0] HRESP,
	output [31:0] HRDATA,
	

	input			tx_fifo_full, 
	input			tx_fifo_empty,
	output reg [7:0]	tx_fifo_dout,
	output reg		tx_fifo_we,

	input	[1:0]	current_owner
);






reg		[1:0]	fsm;
reg				hwrite_reg;





reg				hready_reg;
reg		[2:0]	zero_cnt;
reg		[1:0]	pkt_state;
reg		[7:0]	pkt_len, pkt_cnt;
reg		[1:0]	pkt_end_state;
reg				crc_clear, crc_start;
reg		[1:0]	crc_state;
reg		[1:0]	crc_cnt;
wire	[15:0]	crc_result;
wire			crc_ready;


localparam RESET =		2'b00;
localparam LOAD_SFD =	2'b01;
localparam AHB_TRANS =	2'b10;
localparam CRC_ADD =	2'b11;

localparam CRC_LSB =	2'b00;
localparam CRC_MSB =	2'b01;
localparam PKT_DONE =	2'b10;

localparam CRC_START =	2'b00;
localparam CRC_WAIT =	2'b01;
localparam CRC_IDLE =	2'b10;
localparam CRC_DISABLE =2'b11;


assign HRESP		= 2'b00;
assign HREADYOUT	= (~tx_fifo_full) & hready_reg;
assign HRDATA		= 0;


always @ (posedge HCLK or negedge HRESETn)
begin
    if (~HRESETn)
    begin
		fsm			<= 2'b00;
		tx_fifo_dout<= 0;
		hwrite_reg  <= 0;
		tx_fifo_we	<= 0;
		hready_reg	<= 0;
		zero_cnt	<= 0;
		pkt_state	<= RESET;
		pkt_len		<= 0;
		pkt_cnt		<= 0;
		pkt_end_state <= CRC_LSB;
		crc_start	<= 0;
		crc_clear	<= 0;
		crc_state	<= CRC_IDLE;
		crc_cnt		<= 0;
    end
    else
    begin
		case (fsm)
		    2'b00:
		    begin
				case (pkt_state)
					RESET:
					begin
						if ((current_owner ^ 2'b10) && (tx_fifo_empty))
							pkt_state <= LOAD_SFD;
						zero_cnt <= 0;
						pkt_end_state <= CRC_LSB;
						crc_clear <= 1;
					end

					LOAD_SFD:
					begin
						zero_cnt <= zero_cnt + 1;
						crc_clear <= 0;
						if (zero_cnt<4)
						begin
							tx_fifo_we  <= 1;
							tx_fifo_dout <= 0;
						end
						else if (zero_cnt==4)
						begin
							tx_fifo_we  <= 1;
							tx_fifo_dout <= 8'ha7;
						end
						else
						begin
							pkt_state <= AHB_TRANS;
							hready_reg <= 1;
							tx_fifo_we  <= 0;
						end
					end

					AHB_TRANS:
					begin
						if (((pkt_len-1)==pkt_cnt) && (pkt_len>0))
							pkt_state <= CRC_ADD;
						else
						begin
							if (HSEL && HREADY && HTRANS[1] && HSIZE==3'b010)
							begin
								hwrite_reg	<= HWRITE;
								fsm			<= 2'b01;
								hready_reg	<= 0;
							end
						end
					end

					CRC_ADD:
					begin
						hready_reg <= 0;

						case (pkt_end_state)
							CRC_LSB:
							begin
								tx_fifo_we <= 1;
								tx_fifo_dout <= crc_result[7:0];
								pkt_end_state <= CRC_MSB;
							end

							CRC_MSB:
							begin
								tx_fifo_we <= 1;
								tx_fifo_dout <= crc_result[15:8];
								pkt_end_state <= PKT_DONE;
								crc_clear <= 1;
							end

							PKT_DONE:
							begin
								crc_clear <= 0;
								tx_fifo_we	<= 0;
								pkt_state <= RESET;
								pkt_cnt	<= 0;
								pkt_len	<= 0;
							end
						endcase
					end

					default:
					begin
						pkt_state <= RESET;
						tx_fifo_we	<= 0;
					end
				endcase
		    end

			2'b01:
			begin

				fsm	<= 2'b10;
				crc_cnt <= 0;
				if (hwrite_reg)
				begin
					if (pkt_cnt==0)
					begin
						pkt_len <= HWDATA[7:0];
						crc_state <= CRC_IDLE;
					end
					else
						crc_state <= CRC_START;
					pkt_cnt <= pkt_cnt + 1;
					tx_fifo_we <= 1;
					tx_fifo_dout <= HWDATA[7:0];
				end
				else
					tx_fifo_we	<= 0;
			end
		    
		    2'b10:
		    begin
				tx_fifo_we <= 0;
				case (crc_state)
					CRC_START:
					begin
						crc_start <= 1;
						crc_state <= CRC_DISABLE;
					end

					CRC_DISABLE:
					begin
						crc_start <= 0;
						crc_cnt <= crc_cnt + 1;
						if (crc_cnt==2'b10)
							crc_state <= CRC_WAIT;
					end

					CRC_WAIT:
					begin
						if (crc_ready)
						begin
							fsm <= 2'b11;
							crc_state <= CRC_IDLE;
						end

					end

					CRC_IDLE:
					begin
						fsm	<= 2'b11;
					end
				endcase
			end

			2'b11:
			begin
				hready_reg <= 1;
				fsm <= 2'b00;
				zero_cnt <= 0;
			end
		endcase
    end
end


crc			tx_crc(	.clk(HCLK), .nreset(HRESETn), .clear(crc_clear), .data_in(tx_fifo_dout), 
					.crc_out(crc_result), .start(crc_start), .out_ready(crc_ready));

endmodule