data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v
 line:32: before: "$"
1: b'%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:29: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("arbiter_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:30: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #180 $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10 ck = ~ck;\n        ^\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:48: Unsupported: fork statements\n    initial fork\n            ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #20    r1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #40    r1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #100    r1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #120    r1 = 0;\n        ^\n%Error: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:56: Unsupported: fork statements\n    initial fork\n            ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #60    r2 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #80    r2 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #100    r2 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111433415/verilog/06_secuenciales/06-5_arbitrador/arbiter_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #140    r2 = 0;\n        ^\n%Error: Exiting due to 4 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ();

    reg ck = 0;
    reg r1 = 0;
    reg r2 = 0;
    wire g1;
    wire g2;

    arbiter1 uut(ck, r1, r2, g1, g2);


    initial begin
        $dumpfile("arbiter_tb.vcd");
        $dumpvars(0, test);

        #180 $finish;
    end


    always
        #10 ck = ~ck;



    initial fork
        #20    r1 = 1;
        #40    r1 = 0;
        #100    r1 = 1;
        #120    r1 = 0;
    join


    initial fork
        #60    r2 = 1;
        #80    r2 = 0;
        #100    r2 = 1;
        #140    r2 = 0;
    join
endmodule
module test ();


    reg ck = 0;
    reg r1 = 0;
    reg r2 = 0;
    wire g1;
    wire g2;

    arbiter1 uut(ck, r1, r2, g1, g2);


    initial begin
        $dumpfile("arbiter_tb.vcd");
        $dumpvars(0, test);

        #180 $finish;
    end


    always
        #10 ck = ~ck;



    initial fork
        #20    r1 = 1;
        #40    r1 = 0;
        #100    r1 = 1;
        #120    r1 = 0;
    join


    initial fork
        #60    r2 = 1;
        #80    r2 = 0;
        #100    r2 = 1;
        #140    r2 = 0;
    join
endmodule