data/full_repos/permissive/19435930/uart_send.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/19435930/uart_send.v:32: Signal definition not found, creating implicitly: \'next_bit\'\nwire idle = counter+next_bit >= 10;\n                    ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/19435930/uart_send.v:12: Cannot find file containing module: \'counter\'\n counter #(5\'b11010) counter_txd_en(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19435930,data/full_repos/permissive/19435930/counter\n             data/full_repos/permissive/19435930,data/full_repos/permissive/19435930/counter.v\n             data/full_repos/permissive/19435930,data/full_repos/permissive/19435930/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Warning-LITENDIAN: data/full_repos/permissive/19435930/uart_send.v:21: Little bit endian vector: MSB < LSB of bit range: 0:10\nreg [0:10] shr;  \n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/19435930/uart_send.v:25: Little bit endian vector: MSB < LSB of bit range: 0:10\nwire [0:10] framed_data = {STOP_BIT, START_BIT, data_reversed, STOP_BIT};\n     ^\n%Warning-WIDTH: data/full_repos/permissive/19435930/uart_send.v:32: Operator ADD expects 32 or 4 bits on the RHS, but RHS\'s VARREF \'next_bit\' generates 1 bits.\n                                                                  : ... In instance uart_send\nwire idle = counter+next_bit >= 10;\n                   ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module uart_send(
	input RST,
	input CLK,
	input [7:0] DATA,
	input DATA_READY,
	output TXD,
	output IDLE
	);

	counter #(5'b11010) counter_txd_en(
		.CLK(CLK),
		.RST(RST),
		.MAXED(next_bit),
		.EN(1'b1),
		.VALUE()
	);

reg [3:0] counter;
reg [0:10] shr;

localparam START_BIT = 1'b0;
localparam STOP_BIT  = 1'b1;
wire [0:10] framed_data = {STOP_BIT, START_BIT, data_reversed, STOP_BIT};
wire [7:0] data_reversed = {DATA[0], DATA[1], DATA[2], DATA[3], DATA[4], DATA[5], DATA[6], DATA[7]};

wire data_sampling = DATA_READY&idle;

wire current_bit = shr[0];
assign TXD = current_bit;
wire idle = counter+next_bit >= 10;
assign IDLE = (idle && !DATA_READY);

always @(posedge CLK)
begin
	if(RST)
	begin
		shr[0] <= 1'b1;
		counter<=10;
	end
	else if(data_sampling)
	begin
		counter<=0;
		shr <= framed_data;
	end
	else if(next_bit && counter!==10)
	begin
		counter<=(counter + 1'b1);
		shr <= (shr<<1);
	end
end

endmodule
module uart_send(
	input RST,
	input CLK,
	input [7:0] DATA,
	input DATA_READY,
	output TXD,
	output IDLE
	);


	counter #(5'b11010) counter_txd_en(
		.CLK(CLK),
		.RST(RST),
		.MAXED(next_bit),
		.EN(1'b1),
		.VALUE()
	);

reg [3:0] counter;
reg [0:10] shr;

localparam START_BIT = 1'b0;
localparam STOP_BIT  = 1'b1;
wire [0:10] framed_data = {STOP_BIT, START_BIT, data_reversed, STOP_BIT};
wire [7:0] data_reversed = {DATA[0], DATA[1], DATA[2], DATA[3], DATA[4], DATA[5], DATA[6], DATA[7]};

wire data_sampling = DATA_READY&idle;

wire current_bit = shr[0];
assign TXD = current_bit;
wire idle = counter+next_bit >= 10;
assign IDLE = (idle && !DATA_READY);

always @(posedge CLK)
begin
	if(RST)
	begin
		shr[0] <= 1'b1;
		counter<=10;
	end
	else if(data_sampling)
	begin
		counter<=0;
		shr <= framed_data;
	end
	else if(next_bit && counter!==10)
	begin
		counter<=(counter + 1'b1);
		shr <= (shr<<1);
	end
end

endmodule