data/full_repos/permissive/166014265/src/Basic/Combiner.v
data/verilator_xmls/3cc5258a-0782-46cd-8f30-b8fa6142cba8.xml
module Combiner #
( parameter WIDTH0 = 32
, parameter WIDTH1 = 32
)
( input                      iValid_AS0
, output                     oReady_AS0
, input         [WIDTH0-1:0] iData_AS0
, input                      iValid_AS1
, output                     oReady_AS1
, input         [WIDTH1-1:0] iData_AS1
, output                     oValid_BM
, input                      iReady_BM
, output [WIDTH1+WIDTH0-1:0] oData_BM
);

wire wvld;
wire wrdy;

assign {oReady_AS1, oReady_AS0} = {wrdy, wrdy};
assign oValid_BM                = wvld;
assign oData_BM                 = {iData_AS1, iData_AS0};


assign wvld = iValid_AS0 && iValid_AS1;


assign wrdy = iReady_BM && wvld;

endmodule
module Combiner #
( parameter WIDTH0 = 32
, parameter WIDTH1 = 32
)
( input                      iValid_AS0
, output                     oReady_AS0
, input         [WIDTH0-1:0] iData_AS0
, input                      iValid_AS1
, output                     oReady_AS1
, input         [WIDTH1-1:0] iData_AS1
, output                     oValid_BM
, input                      iReady_BM
, output [WIDTH1+WIDTH0-1:0] oData_BM
);


wire wvld;
wire wrdy;

assign {oReady_AS1, oReady_AS0} = {wrdy, wrdy};
assign oValid_BM                = wvld;
assign oData_BM                 = {iData_AS1, iData_AS0};


assign wvld = iValid_AS0 && iValid_AS1;


assign wrdy = iReady_BM && wvld;

endmodule