data/full_repos/permissive/143278/ivltests/case3.8D.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.8D.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.8D.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.8D.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.8D.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.8D.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #1 ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.8D.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.8D.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #1 ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.8D.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.8D.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #1 ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/case3.8D.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ();

reg error;
reg [2:0] val1,val2;
reg [2:0] result ;

always @( val1 )
  case (val1)
    3'b000: result = 0;
    3'b001: result = 1 ;
    3'b010: result = 2;
    3'bx11: result = 4;
    3'bz11: result = 5;
  endcase

initial
  begin
    error = 0;
    #1;
    val1 = 3'b0;
    #1;
    if(result !== 0)
      begin
        $display("FAILED case 3.8D - case (expr) lab1: ");
        error = 1;
      end
    #1;
    val1 = 3'b001;
    #1;
    if(result !== 1)
      begin
        $display("FAILED case 3.8D - case (expr) lab2: ");
        error = 1;
      end

    #1 ;
    val1 = 3'b010;
    #1;
    if(result !== 2)
      begin
        $display("FAILED case 3.8D - case (expr) lab3: ");
        error = 1;
      end
    #1 ;
    val1 = 3'bz11;
    #1;
    if(result !== 5)
      begin
        $display("FAILED case 3.8D - case (expr) lab5: ");
        error = 1;
      end

    #1 ;
    val1 = 3'bx11;
    #1;
    if(result !== 4)
      begin
        $display("FAILED case 3.8D - case (expr) lab4: ");
        error = 1;
      end

    if(error == 0)
      $display("PASSED");
  end

endmodule
module main ();


reg error;
reg [2:0] val1,val2;
reg [2:0] result ;

always @( val1 )
  case (val1)
    3'b000: result = 0;
    3'b001: result = 1 ;
    3'b010: result = 2;
    3'bx11: result = 4;
    3'bz11: result = 5;
  endcase

initial
  begin
    error = 0;
    #1;
    val1 = 3'b0;
    #1;
    if(result !== 0)
      begin
        $display("FAILED case 3.8D - case (expr) lab1: ");
        error = 1;
      end
    #1;
    val1 = 3'b001;
    #1;
    if(result !== 1)
      begin
        $display("FAILED case 3.8D - case (expr) lab2: ");
        error = 1;
      end

    #1 ;
    val1 = 3'b010;
    #1;
    if(result !== 2)
      begin
        $display("FAILED case 3.8D - case (expr) lab3: ");
        error = 1;
      end
    #1 ;
    val1 = 3'bz11;
    #1;
    if(result !== 5)
      begin
        $display("FAILED case 3.8D - case (expr) lab5: ");
        error = 1;
      end

    #1 ;
    val1 = 3'bx11;
    #1;
    if(result !== 4)
      begin
        $display("FAILED case 3.8D - case (expr) lab4: ");
        error = 1;
      end

    if(error == 0)
      $display("PASSED");
  end

endmodule