data/full_repos/permissive/157005262/verilog/uart_hello.v
None: at end of input
1: b'%Error: data/full_repos/permissive/157005262/verilog/uart_hello.v:1: Cannot find include file: fpga-tools/components/uart.v\n`include "fpga-tools/components/uart.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/fpga-tools/components/uart.v\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/fpga-tools/components/uart.v.v\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/fpga-tools/components/uart.v.sv\n             fpga-tools/components/uart.v\n             fpga-tools/components/uart.v.v\n             fpga-tools/components/uart.v.sv\n             obj_dir/fpga-tools/components/uart.v\n             obj_dir/fpga-tools/components/uart.v.v\n             obj_dir/fpga-tools/components/uart.v.sv\n%Error: Exiting due to 1 error(s)\n'
module uart_node(input wire clk,
                 input wire is_receiving,
                 input wire is_transmitting,
                 output reg transmit = 0,
                 output reg [7:0] tx_byte,
                 input wire received,
                 input wire [7:0] rx_byte);

  parameter n = 13;
  parameter greeting = "Hello World!\n";
  wire [7:0] data[0:n-1];
  reg [3:0] idx;



  generate
    genvar i;
    for (i = 0; i < n; i = i + 1) begin
      assign data[i] = greeting[8*(n-i)-1 : 8*(n-i)-8];
    end
  endgenerate


  always @(posedge clk) begin

    if (transmit)
      transmit <= 0;

    if (!transmit && !is_transmitting) begin
      transmit <= 1;
      tx_byte <= data[idx];
      if (idx == n - 1)
        idx <= 0;
      else
        idx <= idx + 1;
    end
  end

endmodule
module uart_node(input wire clk,
                 input wire is_receiving,
                 input wire is_transmitting,
                 output reg transmit = 0,
                 output reg [7:0] tx_byte,
                 input wire received,
                 input wire [7:0] rx_byte);


  parameter n = 13;
  parameter greeting = "Hello World!\n";
  wire [7:0] data[0:n-1];
  reg [3:0] idx;



  generate
    genvar i;
    for (i = 0; i < n; i = i + 1) begin
      assign data[i] = greeting[8*(n-i)-1 : 8*(n-i)-8];
    end
  endgenerate


  always @(posedge clk) begin

    if (transmit)
      transmit <= 0;

    if (!transmit && !is_transmitting) begin
      transmit <= 1;
      tx_byte <= data[idx];
      if (idx == n - 1)
        idx <= 0;
      else
        idx <= idx + 1;
    end
  end

endmodule