data/full_repos/permissive/149079484/RISC-V_Cache-lab/Cache.v
1: b'%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_Cache-lab/Cache.v:105: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                 : ... In instance Cache\n      databank[idx][(2\'b00+1)*32-1 : 2\'b00*32] = D_MEM_DI;  \n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_Cache-lab/Cache.v:109: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                                 : ... In instance Cache\n      databank[idx][(2\'b01+1)*32-1 : 2\'b01*32] = D_MEM_DI;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_Cache-lab/Cache.v:113: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                 : ... In instance Cache\n      databank[idx][(2\'b10+1)*32-1 : 2\'b10*32] = D_MEM_DI;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_Cache-lab/Cache.v:117: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                 : ... In instance Cache\n      databank[idx][(2\'b11+1)*32-1 : 2\'b11*32] = D_MEM_DI;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_Cache-lab/Cache.v:157: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                 : ... In instance Cache\n      databank[idx][(2\'b00+1)*32-1 : 2\'b00*32] = D_MEM_DI;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_Cache-lab/Cache.v:162: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                                 : ... In instance Cache\n      databank[idx][(2\'b01+1)*32-1 : 2\'b01*32] = D_MEM_DI;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_Cache-lab/Cache.v:167: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                 : ... In instance Cache\n      databank[idx][(2\'b10+1)*32-1 : 2\'b10*32] = D_MEM_DI;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/149079484/RISC-V_Cache-lab/Cache.v:171: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                 : ... In instance Cache\n      databank[idx][(2\'b11+1)*32-1 : 2\'b11*32] = D_MEM_DI;  \n                          ^\n%Error: Exiting due to 8 warning(s)\n'
module Cache (
	input wire CLK,


	input wire Cache_CSN,
	input wire [31:0] D_MEM_DI,
	input wire [11:0] Cache_ADDR,
	input wire Cache_WEN,
	input wire [3:0] Cache_BE,
	input wire [31:0] Cache_DI,


	output reg D_MEM_CSN,
	output reg [31:0] D_MEM_DOUT,
	output reg [11:0] D_MEM_ADDR,
	output reg D_MEM_WEN,
	output reg [3:0] D_MEM_BE,
	output reg [31:0] Cache_DOUT,



	output reg RDY,
	output reg VALID
	);
	
	wire [6:0] tag;
	wire [2:0] idx;
	wire [1:0] g;
	assign tag = Cache_ADDR[11:5];
	assign idx = Cache_ADDR[4:2];
	assign g = Cache_ADDR[1:0];

	reg	[127:0]	databank[0:7];
	reg [6:0] tagbank[0:7];
	reg validbank[0:7];

	reg [31:0] timer;

	initial begin
		timer = 0;
		RDY = 1;
		VALID = 0;



		databank[0] = 0;
		databank[1] = 0;
		databank[2] = 0;
		databank[3] = 0;
		databank[4] = 0;
		databank[5] = 0;
		databank[6] = 0;
		databank[7] = 0;
		tagbank[0] = 0;
		tagbank[1] = 0;
		tagbank[2] = 0;
		tagbank[3] = 0;
		tagbank[4] = 0;
		tagbank[5] = 0;
		tagbank[6] = 0;
		tagbank[7] = 0;
		validbank[0] = 0;
		validbank[1] = 0;
		validbank[2] = 0;
		validbank[3] = 0;
		validbank[4] = 0;
		validbank[5] = 0;
		validbank[6] = 0;
		validbank[7] = 0;
	end


	always @(negedge CLK) begin
		if (RDY == 1) timer = 0;
		else timer = timer + 1;
	end


	reg tag_hit, valid, cache_hit;
	always @(*) begin
		tag_hit = tagbank[idx]==tag;
		valid = validbank[idx]==1;
		cache_hit = tag_hit && valid;
	end

	always @(negedge CLK) begin
		if (~Cache_CSN) begin

			if (Cache_WEN) begin

				if (cache_hit) begin
					Cache_DOUT = databank[idx][g*32 +: 32];
					RDY = 1;
					VALID = 1;
				end
				else if (~cache_hit) begin


					if (timer == 0) begin
						RDY = 0;
						VALID = 0;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b00};
					end
					else if (timer == 1) begin
						databank[idx][(2'b00+1)*32-1 : 2'b00*32] = D_MEM_DI;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b01};
					end
					else if (timer == 2) begin
						databank[idx][(2'b01+1)*32-1 : 2'b01*32] = D_MEM_DI;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b10};
					end
					else if (timer == 3) begin
						databank[idx][(2'b10+1)*32-1 : 2'b10*32] = D_MEM_DI;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b11};
					end
					else if (timer == 4) begin
						databank[idx][(2'b11+1)*32-1 : 2'b11*32] = D_MEM_DI;
						tagbank[idx] = tag;
						validbank[idx] = 1;
					end
					else if (timer == 5) begin
						Cache_DOUT = databank[idx][g*32 +: 32];
						RDY = 1;
						VALID = 1;
					end
				end
			end


			else if (~Cache_WEN) begin

				if (cache_hit) begin

					databank[idx][g*32 +: 32] = Cache_DI;
					validbank[idx] = 1;

					D_MEM_CSN = 0; D_MEM_WEN = 0; D_MEM_BE = 4'b1111; D_MEM_ADDR = Cache_ADDR;
					D_MEM_DOUT = Cache_DI;
					RDY = 1;
					VALID = 1;
				end
				else if (~cache_hit) begin
					if (timer == 0) begin
						RDY = 0;
						VALID = 0;



						D_MEM_CSN = 0; D_MEM_WEN = 0; D_MEM_BE = 4'b1111; D_MEM_ADDR = Cache_ADDR;
						D_MEM_DOUT = Cache_DI;
					end
					else if (timer == 1) begin

						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b00};
					end
					else if (timer == 2) begin
						databank[idx][(2'b00+1)*32-1 : 2'b00*32] = D_MEM_DI;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b01};
						
					end
					else if (timer == 3) begin
						databank[idx][(2'b01+1)*32-1 : 2'b01*32] = D_MEM_DI;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b10};
						
					end
					else if (timer == 4) begin
						databank[idx][(2'b10+1)*32-1 : 2'b10*32] = D_MEM_DI;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b11};
					end
					else if (timer == 5) begin
						databank[idx][(2'b11+1)*32-1 : 2'b11*32] = D_MEM_DI;
						Cache_DOUT = databank[idx][g*32 +: 32];
						tagbank[idx] = tag;
						validbank[idx] = 1;
						RDY = 1;
						VALID = 1;
					end
				end
			end

			else begin
				RDY = 1;
				VALID = 0;
			end
		end
	end

	

endmodule
module Cache (
	input wire CLK,


	input wire Cache_CSN,
	input wire [31:0] D_MEM_DI,
	input wire [11:0] Cache_ADDR,
	input wire Cache_WEN,
	input wire [3:0] Cache_BE,
	input wire [31:0] Cache_DI,


	output reg D_MEM_CSN,
	output reg [31:0] D_MEM_DOUT,
	output reg [11:0] D_MEM_ADDR,
	output reg D_MEM_WEN,
	output reg [3:0] D_MEM_BE,
	output reg [31:0] Cache_DOUT,



	output reg RDY,
	output reg VALID
	);

	
	wire [6:0] tag;
	wire [2:0] idx;
	wire [1:0] g;
	assign tag = Cache_ADDR[11:5];
	assign idx = Cache_ADDR[4:2];
	assign g = Cache_ADDR[1:0];

	reg	[127:0]	databank[0:7];
	reg [6:0] tagbank[0:7];
	reg validbank[0:7];

	reg [31:0] timer;

	initial begin
		timer = 0;
		RDY = 1;
		VALID = 0;



		databank[0] = 0;
		databank[1] = 0;
		databank[2] = 0;
		databank[3] = 0;
		databank[4] = 0;
		databank[5] = 0;
		databank[6] = 0;
		databank[7] = 0;
		tagbank[0] = 0;
		tagbank[1] = 0;
		tagbank[2] = 0;
		tagbank[3] = 0;
		tagbank[4] = 0;
		tagbank[5] = 0;
		tagbank[6] = 0;
		tagbank[7] = 0;
		validbank[0] = 0;
		validbank[1] = 0;
		validbank[2] = 0;
		validbank[3] = 0;
		validbank[4] = 0;
		validbank[5] = 0;
		validbank[6] = 0;
		validbank[7] = 0;
	end


	always @(negedge CLK) begin
		if (RDY == 1) timer = 0;
		else timer = timer + 1;
	end


	reg tag_hit, valid, cache_hit;
	always @(*) begin
		tag_hit = tagbank[idx]==tag;
		valid = validbank[idx]==1;
		cache_hit = tag_hit && valid;
	end

	always @(negedge CLK) begin
		if (~Cache_CSN) begin

			if (Cache_WEN) begin

				if (cache_hit) begin
					Cache_DOUT = databank[idx][g*32 +: 32];
					RDY = 1;
					VALID = 1;
				end
				else if (~cache_hit) begin


					if (timer == 0) begin
						RDY = 0;
						VALID = 0;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b00};
					end
					else if (timer == 1) begin
						databank[idx][(2'b00+1)*32-1 : 2'b00*32] = D_MEM_DI;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b01};
					end
					else if (timer == 2) begin
						databank[idx][(2'b01+1)*32-1 : 2'b01*32] = D_MEM_DI;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b10};
					end
					else if (timer == 3) begin
						databank[idx][(2'b10+1)*32-1 : 2'b10*32] = D_MEM_DI;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b11};
					end
					else if (timer == 4) begin
						databank[idx][(2'b11+1)*32-1 : 2'b11*32] = D_MEM_DI;
						tagbank[idx] = tag;
						validbank[idx] = 1;
					end
					else if (timer == 5) begin
						Cache_DOUT = databank[idx][g*32 +: 32];
						RDY = 1;
						VALID = 1;
					end
				end
			end


			else if (~Cache_WEN) begin

				if (cache_hit) begin

					databank[idx][g*32 +: 32] = Cache_DI;
					validbank[idx] = 1;

					D_MEM_CSN = 0; D_MEM_WEN = 0; D_MEM_BE = 4'b1111; D_MEM_ADDR = Cache_ADDR;
					D_MEM_DOUT = Cache_DI;
					RDY = 1;
					VALID = 1;
				end
				else if (~cache_hit) begin
					if (timer == 0) begin
						RDY = 0;
						VALID = 0;



						D_MEM_CSN = 0; D_MEM_WEN = 0; D_MEM_BE = 4'b1111; D_MEM_ADDR = Cache_ADDR;
						D_MEM_DOUT = Cache_DI;
					end
					else if (timer == 1) begin

						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b00};
					end
					else if (timer == 2) begin
						databank[idx][(2'b00+1)*32-1 : 2'b00*32] = D_MEM_DI;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b01};
						
					end
					else if (timer == 3) begin
						databank[idx][(2'b01+1)*32-1 : 2'b01*32] = D_MEM_DI;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b10};
						
					end
					else if (timer == 4) begin
						databank[idx][(2'b10+1)*32-1 : 2'b10*32] = D_MEM_DI;
						D_MEM_CSN = 0; D_MEM_WEN = 1; D_MEM_BE = 4'b1111; D_MEM_ADDR = {tag, idx, 2'b11};
					end
					else if (timer == 5) begin
						databank[idx][(2'b11+1)*32-1 : 2'b11*32] = D_MEM_DI;
						Cache_DOUT = databank[idx][g*32 +: 32];
						tagbank[idx] = tag;
						validbank[idx] = 1;
						RDY = 1;
						VALID = 1;
					end
				end
			end

			else begin
				RDY = 1;
				VALID = 0;
			end
		end
	end

	

endmodule