data/full_repos/permissive/143278/ivltests/pr1787423c.v
 line:10: before: "$"
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr1787423c.v:6: syntax error, unexpected \',\', expecting \')\'\n   buf bus_drv[1:0] (net1, net2, data);\n                               ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1787423c.v:10: Unsupported or unknown PLI call: $monitor\n      #1 $monitor(net1,,net2,,data);\n         ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1787423c.v:10: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      #1 $monitor(net1,,net2,,data);\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1787423c.v:10: Unsupported: Ignoring delay on this delayed statement.\n      #1 $monitor(net1,,net2,,data);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1787423c.v:11: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (net1 !== 1\'b0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1787423c.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (net1 !== 1\'b1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1787423c.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (net1 !== 1\'bx) begin\n      ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module top;

   wire net1, net2;
   reg [1:0] data;

   buf bus_drv[1:0] (net1, net2, data);

   initial begin
      data = 0;
      #1 $monitor(net1,,net2,,data);
      #1 if (net1 !== 1'b0) begin
	 $display("FAILED");
	 $finish;
      end

      data = 3;
      #1 if (net1 !== 1'b1) begin
	 $display("FAILED");
	 $finish;
      end

      data = 1;
      #1 if (net1 !== 1'bx) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module top;


   wire net1, net2;
   reg [1:0] data;

   buf bus_drv[1:0] (net1, net2, data);

   initial begin
      data = 0;
      #1 $monitor(net1,,net2,,data);
      #1 if (net1 !== 1'b0) begin
	 $display("FAILED");
	 $finish;
      end

      data = 3;
      #1 if (net1 !== 1'b1) begin
	 $display("FAILED");
	 $finish;
      end

      data = 1;
      #1 if (net1 !== 1'bx) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
   end

endmodule