data/full_repos/permissive/164484080/testbench/uart_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk_i = ~clk_i;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #4340;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #4340;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/164484080/testbench/uart_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #8680;\n  ^\n%Error: data/full_repos/permissive/164484080/testbench/uart_tb.v:33: Cannot find file containing module: \'uart\'\n uart uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/164484080/testbench,data/full_repos/permissive/164484080/uart\n             data/full_repos/permissive/164484080/testbench,data/full_repos/permissive/164484080/uart.v\n             data/full_repos/permissive/164484080/testbench,data/full_repos/permissive/164484080/uart.sv\n             uart\n             uart.v\n             uart.sv\n             obj_dir/uart\n             obj_dir/uart.v\n             obj_dir/uart.sv\n%Error: Exiting due to 1 error(s), 25 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_tb;


	reg rst_i;
	reg clk_i;
	reg uart_rx_i;


	uart uut (
		.rst_i(rst_i),
		.clk_i(clk_i),
		.uart_rx_i(uart_rx_i)
	);

	always begin
		#5 clk_i = ~clk_i;
	end

	initial begin

		rst_i = 0;
		clk_i = 0;

		uart_rx_i = 1;


		#4340;




		#8680;
		uart_rx_i = 0;

		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;
		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;
		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;
		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;

		#8680;
		uart_rx_i = 1;

		#8680;
		uart_rx_i = 1;

		#4340;




		#8680;
		uart_rx_i = 0;

		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;
		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;
		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;
		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;

		#8680;
		uart_rx_i = 1;

		#8680;
		uart_rx_i = 1;
	end

endmodule
module uart_tb;



	reg rst_i;
	reg clk_i;
	reg uart_rx_i;


	uart uut (
		.rst_i(rst_i),
		.clk_i(clk_i),
		.uart_rx_i(uart_rx_i)
	);

	always begin
		#5 clk_i = ~clk_i;
	end

	initial begin

		rst_i = 0;
		clk_i = 0;

		uart_rx_i = 1;


		#4340;




		#8680;
		uart_rx_i = 0;

		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;
		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;
		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;
		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;

		#8680;
		uart_rx_i = 1;

		#8680;
		uart_rx_i = 1;

		#4340;




		#8680;
		uart_rx_i = 0;

		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;
		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;
		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;
		#8680;
		uart_rx_i = 1;
		#8680;
		uart_rx_i = 0;

		#8680;
		uart_rx_i = 1;

		#8680;
		uart_rx_i = 1;
	end

endmodule