data/full_repos/permissive/141596082/voice_core/rtl/wb_conbus/conbus_arb.v
data/verilator_xmls/b50bf304-0dfd-49de-a0c2-addc7a165cbd.xml
module conbus_arb (
  input            sys_clk,
  input            sys_rst,
  input      [1:0] req    ,
  output reg [1:0] gnt
);

  parameter [1:0] grant0 = 2'b01;
  parameter [1:0] grant1 = 2'b10;

  reg [1:0] state     ;
  reg [1:0] next_state;

  initial begin
    state = grant0;
  end

  always @(posedge sys_clk or posedge sys_rst) begin
    if(sys_rst)
      state <= grant0;
    else
      case (state)
        grant0 : begin
          if (~req[0] & req[1])
            state <= grant1;
          else
            state <= grant0;
        end
        grant1 : begin
          if (~req[1] & req[0])
            state <= grant0;
          else
            state <= grant1;
        end
        default : state <= grant0;
      endcase
  end

  always @(state) begin
    case (state)
      grant0  : gnt[1:0] = 2'b01;
      grant1  : gnt[1:0] = 2'b10;
      default : gnt[1:0] = 2'b01;
    endcase
  end
endmodule
module conbus_arb (
  input            sys_clk,
  input            sys_rst,
  input      [1:0] req    ,
  output reg [1:0] gnt
);


  parameter [1:0] grant0 = 2'b01;
  parameter [1:0] grant1 = 2'b10;

  reg [1:0] state     ;
  reg [1:0] next_state;

  initial begin
    state = grant0;
  end

  always @(posedge sys_clk or posedge sys_rst) begin
    if(sys_rst)
      state <= grant0;
    else
      case (state)
        grant0 : begin
          if (~req[0] & req[1])
            state <= grant1;
          else
            state <= grant0;
        end
        grant1 : begin
          if (~req[1] & req[0])
            state <= grant0;
          else
            state <= grant1;
        end
        default : state <= grant0;
      endcase
  end

  always @(state) begin
    case (state)
      grant0  : gnt[1:0] = 2'b01;
      grant1  : gnt[1:0] = 2'b10;
      default : gnt[1:0] = 2'b01;
    endcase
  end
endmodule