data/full_repos/permissive/138443719/06-delays/src/delay.v
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data/verilator_xmls/e2c9d4a2-3552-48f9-8ea6-5ad90fcd74eb.xml
module delay(in, out);
input in;
output wire out;

assign #(2,3) out = in;

endmodule
module delay(in, out);

input in;
output wire out;

assign #(2,3) out = in;

endmodule