data/full_repos/permissive/143278/fpga_tests/ornor4_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/ornor4_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #1 if (o_or !== |val[3:0]) begin\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/143278/fpga_tests/ornor4_tb.v:10: Signal definition not found, creating implicitly: \'o_or\'\n  #1 if (o_or !== |val[3:0]) begin\n         ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/143278/fpga_tests/ornor4_tb.v:15: Signal definition not found, creating implicitly: \'o_nor\'\n                                                                              : ... Suggested alternative: \'o_or\'\n  if (o_nor !== ~|val[3:0]) begin\n      ^~~~~\n%Error: data/full_repos/permissive/143278/fpga_tests/ornor4_tb.v:5: Cannot find file containing module: \'ornor4\'\n   ornor4 dut (.O_OR(o_or), .O_NOR(o_nor),\n   ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/ornor4\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/ornor4.v\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/ornor4.sv\n             ornor4\n             ornor4.v\n             ornor4.sv\n             obj_dir/ornor4\n             obj_dir/ornor4.v\n             obj_dir/ornor4.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [4:0] val;

   ornor4 dut (.O_OR(o_or), .O_NOR(o_nor),
	       .I0(val[0]), .I1(val[1]), .I2(val[2]), .I3(val[3]));

   initial begin
      for (val = 0 ;  val[4] == 0 ;  val = val+1) begin
	 #1 if (o_or !== |val[3:0]) begin
	    $display("FAILED -- |%b --> %b", val[3:0], o_or);
	    $finish;
	 end

	 if (o_nor !== ~|val[3:0]) begin
	    $display("FAILED -- ~|%b --> %b", val[3:0], o_nor);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule
module main;


   reg [4:0] val;

   ornor4 dut (.O_OR(o_or), .O_NOR(o_nor),
	       .I0(val[0]), .I1(val[1]), .I2(val[2]), .I3(val[3]));

   initial begin
      for (val = 0 ;  val[4] == 0 ;  val = val+1) begin
	 #1 if (o_or !== |val[3:0]) begin
	    $display("FAILED -- |%b --> %b", val[3:0], o_or);
	    $finish;
	 end

	 if (o_nor !== ~|val[3:0]) begin
	    $display("FAILED -- ~|%b --> %b", val[3:0], o_nor);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule