data/full_repos/permissive/167161024/spi_send_only_tb.v
 line:60: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167161024/spi_send_only_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n   #10   clock = ~clock;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/167161024/spi_send_only_tb.v:35: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("spi_send_only_tb.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/spi_send_only_tb.v:36: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0, spi_send_only_tb);\n   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/167161024/spi_send_only_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n   #100 reset_n <= 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/spi_send_only_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n   #10 packs_to_send <= 10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/spi_send_only_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n   #10 trigger <= 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/spi_send_only_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n   #10 trigger <= 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/spi_send_only_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n   # 1000 trigger <= 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/spi_send_only_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n   # 10 trigger <= 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/spi_send_only_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n   #10000\n   ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spi_send_only_tb;
   wire busy;
   wire cs;
   wire sclk;
   wire [3:0] sdio;

   reg 		 clock;
   reg 		 reset_n;
   reg 		 trigger;
   reg [4:0] packs_to_send;
   reg [63:0] data_input;
   
   spi_send_only dut(

					 .busy				(busy),
					 .cs				(cs),
					 .sclk				(sclk),
					 .sdio				(sdio[3:0]),

					 .clock				(clock),
					 .reset_n			(reset_n),
					 .trigger			(trigger),
					 .packs_to_send		(packs_to_send[4:0]),
					 .data_input		(data_input[63:0]));

   always begin
	  #10 	 clock = ~clock;
   end
   integer 	   i;


   initial begin
	  $dumpfile("spi_send_only_tb.vcd");
	  $dumpvars(0, spi_send_only_tb);
	  data_input = 0;
	  for(i = 0;i < 10; i = i+1)begin

		 data_input = data_input | (i & 4'hF) << (i << 2);
	  end


	  
	  $display("START");
	  clock <= 0;
	  reset_n <= 0;
	  #100 reset_n <= 1;
	  #10 packs_to_send <= 10;

	  #10 trigger <= 1;

	  #10 trigger <= 0;
	  
	  # 1000 trigger <= 1;
	  packs_to_send <= 10;
	  # 10 trigger <= 0;
	  
	  #10000
		$display("END");
	  $finish;
	  
   end
   
   
endmodule
module spi_send_only_tb;

   wire busy;
   wire cs;
   wire sclk;
   wire [3:0] sdio;

   reg 		 clock;
   reg 		 reset_n;
   reg 		 trigger;
   reg [4:0] packs_to_send;
   reg [63:0] data_input;
   
   spi_send_only dut(

					 .busy				(busy),
					 .cs				(cs),
					 .sclk				(sclk),
					 .sdio				(sdio[3:0]),

					 .clock				(clock),
					 .reset_n			(reset_n),
					 .trigger			(trigger),
					 .packs_to_send		(packs_to_send[4:0]),
					 .data_input		(data_input[63:0]));

   always begin
	  #10 	 clock = ~clock;
   end
   integer 	   i;


   initial begin
	  $dumpfile("spi_send_only_tb.vcd");
	  $dumpvars(0, spi_send_only_tb);
	  data_input = 0;
	  for(i = 0;i < 10; i = i+1)begin

		 data_input = data_input | (i & 4'hF) << (i << 2);
	  end


	  
	  $display("START");
	  clock <= 0;
	  reset_n <= 0;
	  #100 reset_n <= 1;
	  #10 packs_to_send <= 10;

	  #10 trigger <= 1;

	  #10 trigger <= 0;
	  
	  # 1000 trigger <= 1;
	  packs_to_send <= 10;
	  # 10 trigger <= 0;
	  
	  #10000
		$display("END");
	  $finish;
	  
   end
   
   
endmodule