data/full_repos/permissive/137045072/fetch_unit.v
1: b'%Error: data/full_repos/permissive/137045072/fetch_unit.v:22: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/137045072/fetch_unit.v:30: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] write,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/fetch_unit.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`DATA_BUS] write,\n                    ^\n%Error: data/full_repos/permissive/137045072/fetch_unit.v:31: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] pc\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/fetch_unit.v:44: Define or directive not defined: \'`MEM_WRITE\'\n                if (rw == `MEM_WRITE)\n                          ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module fetch_unit #(parameter DATA_WIDTH = 32)(
    input clk,
    input rst_n,
    input stall,
    
    input rw,
    input [`DATA_BUS] write,
    output reg [`DATA_BUS] pc
    );

    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            pc <= 0;
        end
        else
        begin
            if (!stall)
            begin
                if (rw == `MEM_WRITE)
                begin
                    pc <= write;
                end
                else
                begin
                    pc <= pc + 4;
                end
            end
        end
    end
endmodule
module fetch_unit #(parameter DATA_WIDTH = 32)(
    input clk,
    input rst_n,
    input stall,
    
    input rw,
    input [`DATA_BUS] write,
    output reg [`DATA_BUS] pc
    );


    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            pc <= 0;
        end
        else
        begin
            if (!stall)
            begin
                if (rw == `MEM_WRITE)
                begin
                    pc <= write;
                end
                else
                begin
                    pc <= pc + 4;
                end
            end
        end
    end
endmodule