data/full_repos/permissive/181665138/verilog/capitolo_ii/Rete_Combinatoria_4.v
1: b'%Warning-WIDTH: data/full_repos/permissive/181665138/verilog/capitolo_ii/Rete_Combinatoria_4.v:36: Operator CASE expects 32 bits on the Case expression, but Case expression\'s REPLICATE generates 4 bits.\n                                                                                                 : ... In instance Rete_Combinatoria_4\n        casex({x3, x2, x1, x0})\n        ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Rete_Combinatoria_4(x3, x2, x1, x0, z);
    input x3, x2, x1, x0;
    output z;
    
    assign z = F(x3, x2, x1, x0);

    function F;
        input x3, x2, x1, x0;

        casex({x3, x2, x1, x0})
            'B?011  : F=0;
            'B11?0  : F=0;
            default : F=1;
        endcase
    endfunction
endmodule
module Rete_Combinatoria_4(x3, x2, x1, x0, z);

    input x3, x2, x1, x0;
    output z;
    
    assign z = F(x3, x2, x1, x0);

    function F;
        input x3, x2, x1, x0;

        casex({x3, x2, x1, x0})
            'B?011  : F=0;
            'B11?0  : F=0;
            default : F=1;
        endcase
    endfunction
endmodule