data/full_repos/permissive/143278/ivltests/pr2018235a.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2018235a.v:24: Unsupported: Ignoring delay on this delayed statement.\n         #26  \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2018235a.v:33: Unsupported: Ignoring delay on this delayed statement.\n   always #25 clk = ~clk;\n          ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();
   parameter N_CH = 1;

   reg pass = 1'b1;
   reg clk;
   reg [31:0] data[0: N_CH-1];

   generate
      genvar  i;
      for (i=0; i<N_CH; i = i + 1)
         begin: sdac
            always @ (posedge clk)
               data[i] <= 32'h0;
         end
   endgenerate

   initial
      begin
         clk = 0;
         if (data[0] != 32'bx) begin
            $display("FAILED: initial value, expected 32'bx, got %b", data[0]);
            pass = 1'b0;
         end
         #26
         if (data[0] != 32'b0) begin
            $display("FAILED: final value, expected 32'b0, got %b", data[0]);
            pass = 1'b0;
         end
         if (pass) $display("PASSED");
         $finish;
      end

   always #25 clk = ~clk;
endmodule
module test();

   parameter N_CH = 1;

   reg pass = 1'b1;
   reg clk;
   reg [31:0] data[0: N_CH-1];

   generate
      genvar  i;
      for (i=0; i<N_CH; i = i + 1)
         begin: sdac
            always @ (posedge clk)
               data[i] <= 32'h0;
         end
   endgenerate

   initial
      begin
         clk = 0;
         if (data[0] != 32'bx) begin
            $display("FAILED: initial value, expected 32'bx, got %b", data[0]);
            pass = 1'b0;
         end
         #26
         if (data[0] != 32'b0) begin
            $display("FAILED: final value, expected 32'b0, got %b", data[0]);
            pass = 1'b0;
         end
         if (pass) $display("PASSED");
         $finish;
      end

   always #25 clk = ~clk;
endmodule