data/full_repos/permissive/121470165/top.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:66: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'len\' generates 3 bits.\n                                                             : ... In instance top.model_test\n    data[31:16] = len;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:67: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'sound\' generates 16 bits.\n                                                             : ... In instance top.model_test\n    bell = sound;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:68: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'en1\' generates 16 bits.\n                                                             : ... In instance top.model_test\n    en = en1;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:81: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'sound\' generates 16 bits.\n                                                             : ... In instance top.model_test\n    bell = sound;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:82: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'en1\' generates 16 bits.\n                                                             : ... In instance top.model_test\n    en = en1;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:91: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_c\' generates 16 bits.\n                                                             : ... In instance top.model_test\n    data[31:18] = addr_c;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:93: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'sound\' generates 16 bits.\n                                                             : ... In instance top.model_test\n    bell = sound;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:94: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'en1\' generates 16 bits.\n                                                             : ... In instance top.model_test\n    en = en1;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:104: Operator DIV expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'speed\' generates 8 bits.\n                                                              : ... In instance top.model_test\n    data[15:0] = speed / 100 * 256 + speed % 100 /10 * 16 + speed % 100 % 10;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:104: Operator MODDIV expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'speed\' generates 8 bits.\n                                                              : ... In instance top.model_test\n    data[15:0] = speed / 100 * 256 + speed % 100 /10 * 16 + speed % 100 % 10;\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:104: Operator MODDIV expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'speed\' generates 8 bits.\n                                                              : ... In instance top.model_test\n    data[15:0] = speed / 100 * 256 + speed % 100 /10 * 16 + speed % 100 % 10;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:105: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'beat\' generates 16 bits.\n                                                              : ... In instance top.model_test\n    bell = beat;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:106: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'en2\' generates 16 bits.\n                                                              : ... In instance top.model_test\n    en = en2;\n       ^\n%Error: data/full_repos/permissive/121470165/top.v:151: Cannot find file containing module: \'no_fitter\'\n  no_fitter fit1(play, rst_n, clk, pause);\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/121470165,data/full_repos/permissive/121470165/no_fitter\n             data/full_repos/permissive/121470165,data/full_repos/permissive/121470165/no_fitter.v\n             data/full_repos/permissive/121470165,data/full_repos/permissive/121470165/no_fitter.sv\n             no_fitter\n             no_fitter.v\n             no_fitter.sv\n             obj_dir/no_fitter\n             obj_dir/no_fitter.v\n             obj_dir/no_fitter.sv\n%Error: data/full_repos/permissive/121470165/top.v:152: Cannot find file containing module: \'no_fitter\'\n  no_fitter fit2(left, rst_n, clk, dec);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/121470165/top.v:153: Cannot find file containing module: \'no_fitter\'\n  no_fitter fit3(right, rst_n, clk, inc);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/121470165/top.v:154: Cannot find file containing module: \'no_fitter\'\n  no_fitter fit4(mode, rst_n, clk, mode_chg);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/121470165/top.v:155: Cannot find file containing module: \'metronome\'\n  metronome metronome1(speed, clk, rst_n, SW, beat, rhythm, en2);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/121470165/top.v:156: Cannot find file containing module: \'freq\'\n  freq freq1(clk, redu, add, pause, rst_n, speed);\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:157: Input port connection \'beat\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'beat\' generates 1 bits.\n                                                              : ... In instance top\n  model_ctl model_test(clk, rst_n, mode_chg, SW, signal, inc, dec, band, speed, rhythm, beat, sound, en1, en2, sel_2, len, read, addr_c, wen_c, electone, music_box, writing, model, in, add, redu, pre, next, data, adj, uart_test, bell, en);\n                                                                                        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:157: Input port connection \'sound\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'sound\' generates 1 bits.\n                                                              : ... In instance top\n  model_ctl model_test(clk, rst_n, mode_chg, SW, signal, inc, dec, band, speed, rhythm, beat, sound, en1, en2, sel_2, len, read, addr_c, wen_c, electone, music_box, writing, model, in, add, redu, pre, next, data, adj, uart_test, bell, en);\n                                                                                              ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:157: Input port connection \'en1\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'en1\' generates 1 bits.\n                                                              : ... In instance top\n  model_ctl model_test(clk, rst_n, mode_chg, SW, signal, inc, dec, band, speed, rhythm, beat, sound, en1, en2, sel_2, len, read, addr_c, wen_c, electone, music_box, writing, model, in, add, redu, pre, next, data, adj, uart_test, bell, en);\n                                                                                                     ^~~\n%Warning-WIDTH: data/full_repos/permissive/121470165/top.v:157: Input port connection \'en2\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'en2\' generates 1 bits.\n                                                              : ... In instance top\n  model_ctl model_test(clk, rst_n, mode_chg, SW, signal, inc, dec, band, speed, rhythm, beat, sound, en1, en2, sel_2, len, read, addr_c, wen_c, electone, music_box, writing, model, in, add, redu, pre, next, data, adj, uart_test, bell, en);\n                                                                                                          ^~~\n%Error: data/full_repos/permissive/121470165/top.v:158: Cannot find file containing module: \'regfile\'\n  regfile reg1(clk, rst_n, addr_a, addr_b,  addr_c, data_c, wen_c, sel_2, q_a, q_b, len, addr);\n  ^~~~~~~\n%Error: data/full_repos/permissive/121470165/top.v:159: Cannot find file containing module: \'read\'\n  read read_box(q_a, clk, rst_n, addr, pause, pre, next, 3\'b011, signal, bandi, addr_a, en_2, sel_2);\n  ^~~~\n%Error: data/full_repos/permissive/121470165/top.v:160: Cannot find file containing module: \'musicbox\'\n  musicbox test(in, rst_n, pause, clk, redu, add, adj, bandi, sound, en1, band);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/121470165/top.v:162: Cannot find file containing module: \'seg\'\n  seg seg1(clk, rst_n, data, sel, segment);\n  ^~~\n%Error: data/full_repos/permissive/121470165/top.v:164: Cannot find file containing module: \'uart\'\n  uart recv(clk, rst_n, UART_RX, read, data_c, wen_c, addr_c);\n  ^~~~\n%Error: Exiting due to 11 error(s), 17 warning(s)\n'
module top(
    input [15:0] SW,
    input rst_n, clk, left, right, play,
		input mode,
		input UART_RX,
    output bell,
		output [15:0] LED,
		output en,
		output electone,
		output writing,
		output music_box,
		output [2:0] sel,
		output [6:0] segment,
		output en_2,
		output uart_test
    );
		wire [2:0] band;
		wire [2:0] bandi;
		wire [1:0] model;
		wire mode_chg;
		wire adj;

		wire [15:0] in;
		wire [2:0] len;
		wire [15:0] signal;
		wire [15:0] addr_a, addr_b;
		wire [15:0] addr_c;
		wire [15:0] rhythm;
		wire [15:0] addr;
		wire [11:0] data_c;
		wire [31:0] data;
		wire [7:0] read;
		wire [7:0] speed;
		wire beat, sound, en1, en2;
		wire [11:0] q_a, q_b;
		wire wen_c;

		wire pause, dec, inc, add, redu, pre, next;
		wire [2:0] sel_2;
		assign LED = in;
		no_fitter fit1(play, rst_n, clk, pause);
		no_fitter fit2(left, rst_n, clk, dec);
		no_fitter fit3(right, rst_n, clk, inc);
		no_fitter fit4(mode, rst_n, clk, mode_chg);
		metronome metronome1(speed, clk, rst_n, SW, beat, rhythm, en2);
		freq freq1(clk, redu, add, pause, rst_n, speed);
		model_ctl model_test(clk, rst_n, mode_chg, SW, signal, inc, dec, band, speed, rhythm, beat, sound, en1, en2, sel_2, len, read, addr_c, wen_c, electone, music_box, writing, model, in, add, redu, pre, next, data, adj, uart_test, bell, en);
		regfile reg1(clk, rst_n, addr_a, addr_b,  addr_c, data_c, wen_c, sel_2, q_a, q_b, len, addr);
		read read_box(q_a, clk, rst_n, addr, pause, pre, next, 3'b011, signal, bandi, addr_a, en_2, sel_2);
		musicbox test(in, rst_n, pause, clk, redu, add, adj, bandi, sound, en1, band);

		seg seg1(clk, rst_n, data, sel, segment);

		uart recv(clk, rst_n, UART_RX, read, data_c, wen_c, addr_c);
		endmodule
module top(
    input [15:0] SW,
    input rst_n, clk, left, right, play,
		input mode,
		input UART_RX,
    output bell,
		output [15:0] LED,
		output en,
		output electone,
		output writing,
		output music_box,
		output [2:0] sel,
		output [6:0] segment,
		output en_2,
		output uart_test
    );

		wire [2:0] band;
		wire [2:0] bandi;
		wire [1:0] model;
		wire mode_chg;
		wire adj;

		wire [15:0] in;
		wire [2:0] len;
		wire [15:0] signal;
		wire [15:0] addr_a, addr_b;
		wire [15:0] addr_c;
		wire [15:0] rhythm;
		wire [15:0] addr;
		wire [11:0] data_c;
		wire [31:0] data;
		wire [7:0] read;
		wire [7:0] speed;
		wire beat, sound, en1, en2;
		wire [11:0] q_a, q_b;
		wire wen_c;

		wire pause, dec, inc, add, redu, pre, next;
		wire [2:0] sel_2;
		assign LED = in;
		no_fitter fit1(play, rst_n, clk, pause);
		no_fitter fit2(left, rst_n, clk, dec);
		no_fitter fit3(right, rst_n, clk, inc);
		no_fitter fit4(mode, rst_n, clk, mode_chg);
		metronome metronome1(speed, clk, rst_n, SW, beat, rhythm, en2);
		freq freq1(clk, redu, add, pause, rst_n, speed);
		model_ctl model_test(clk, rst_n, mode_chg, SW, signal, inc, dec, band, speed, rhythm, beat, sound, en1, en2, sel_2, len, read, addr_c, wen_c, electone, music_box, writing, model, in, add, redu, pre, next, data, adj, uart_test, bell, en);
		regfile reg1(clk, rst_n, addr_a, addr_b,  addr_c, data_c, wen_c, sel_2, q_a, q_b, len, addr);
		read read_box(q_a, clk, rst_n, addr, pause, pre, next, 3'b011, signal, bandi, addr_a, en_2, sel_2);
		musicbox test(in, rst_n, pause, clk, redu, add, adj, bandi, sound, en1, band);

		seg seg1(clk, rst_n, data, sel, segment);

		uart recv(clk, rst_n, UART_RX, read, data_c, wen_c, addr_c);
		endmodule