data/full_repos/permissive/201196900/Verilog_32BitPriorityEncoder/Verilog/PriorityEncoderWithLadnerFischer.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/201196900/Verilog_32BitPriorityEncoder/Verilog/PriorityEncoderWithLadnerFischer.v:78: Cell has missing pin: \'A32N\'\nAND_A_NOT_GATE  AND_A_NOT_GATE(.A1N(orOut16_0_Q15), .B1(orOut16_0_Q16), .A2N(orOut16_0_Q14), .B2(orOut16_0_Q15), .A3N(orOut16_0_Q13), .B3(orOut16_0_Q14), .A4N(orOut16_0_Q12), .B4(orOut16_0_Q13),\n                ^~~~~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module OR9GATE( input AC, 
                input B1, input B2, input B3, input B4, 
                input B5, input B6, input B7, input B8,
                output Q1, output Q2, output Q3, output Q4,
                output Q5, output Q6, output Q7, output Q8);
assign Q1=AC|B1;
assign Q2=AC|B2;
assign Q3=AC|B3;
assign Q4=AC|B4;
assign Q5=AC|B5;
assign Q6=AC|B6;
assign Q7=AC|B7;
assign Q8=AC|B8;
endmodule
module OR9GATE( input AC, 
                input B1, input B2, input B3, input B4, 
                input B5, input B6, input B7, input B8,
                output Q1, output Q2, output Q3, output Q4,
                output Q5, output Q6, output Q7, output Q8);

assign Q1=AC|B1;
assign Q2=AC|B2;
assign Q3=AC|B3;
assign Q4=AC|B4;
assign Q5=AC|B5;
assign Q6=AC|B6;
assign Q7=AC|B7;
assign Q8=AC|B8;
endmodule