data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v
None: at end of input
1: b'%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:28: Cannot find include file: spio_spinnaker_link.h\n`include "spio_spinnaker_link.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.v\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.sv\n             spio_spinnaker_link.h\n             spio_spinnaker_link.h.v\n             spio_spinnaker_link.h.sv\n             obj_dir/spio_spinnaker_link.h\n             obj_dir/spio_spinnaker_link.h.v\n             obj_dir/spio_spinnaker_link.h.sv\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:49: Define or directive not defined: \'`PKT_BITS\'\n  output wire [`PKT_BITS - 1:0] PKT_DATA_OUT,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:510: Define or directive not defined: \'`PKT_BITS\'\n  output reg  [`PKT_BITS - 1:0] PKT_DATA_OUT,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:538: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] bad_pkt;        \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:550: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] pkt_buf;    \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:650: Define or directive not defined: \'`PKT_BITS\'\n      pkt_buf <= {flt_data_bin, pkt_buf[`PKT_BITS - 1:4]};\n                                        ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
function data_2of7 ;
    input [6:0] data;

    case (data)
      7'b0010001: data_2of7 = 1;
      7'b0010010: data_2of7 = 1;
      7'b0010100: data_2of7 = 1;
      7'b0011000: data_2of7 = 1;
      7'b0100001: data_2of7 = 1;
      7'b0100010: data_2of7 = 1;
      7'b0100100: data_2of7 = 1;
      7'b0101000: data_2of7 = 1;
      7'b1000001: data_2of7 = 1;
      7'b1000010: data_2of7 = 1;
      7'b1000100: data_2of7 = 1;
      7'b1001000: data_2of7 = 1;
      7'b0000011: data_2of7 = 1;
      7'b0000110: data_2of7 = 1;
      7'b0001100: data_2of7 = 1;
      7'b0001001: data_2of7 = 1;
      default:    data_2of7 = 0;
    endcase
  endfunction
function data_2of7 ;

    input [6:0] data;

    case (data)
      7'b0010001: data_2of7 = 1;
      7'b0010010: data_2of7 = 1;
      7'b0010100: data_2of7 = 1;
      7'b0011000: data_2of7 = 1;
      7'b0100001: data_2of7 = 1;
      7'b0100010: data_2of7 = 1;
      7'b0100100: data_2of7 = 1;
      7'b0101000: data_2of7 = 1;
      7'b1000001: data_2of7 = 1;
      7'b1000010: data_2of7 = 1;
      7'b1000100: data_2of7 = 1;
      7'b1001000: data_2of7 = 1;
      7'b0000011: data_2of7 = 1;
      7'b0000110: data_2of7 = 1;
      7'b0001100: data_2of7 = 1;
      7'b0001001: data_2of7 = 1;
      default:    data_2of7 = 0;
    endcase
  endfunction