data/full_repos/permissive/201488448/1_verilog/04_and.v
data/verilator_xmls/7e0c26bd-8ddb-41bf-81e2-6d70fc0b1a90.xml
module top_module( 
    input a, 
    input b, 
    output out );

   	assign	out = a&b;
    
endmodule
module top_module( 
    input a, 
    input b, 
    output out );


   	assign	out = a&b;
    
endmodule