data/full_repos/permissive/154199685/Cordic_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/154199685/Cordic_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n   forever #10 clk=~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/154199685/Cordic_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/154199685/Cordic_tb.v:38: Cannot find file containing module: \'Cordic\'\n Cordic uut (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154199685,data/full_repos/permissive/154199685/Cordic\n             data/full_repos/permissive/154199685,data/full_repos/permissive/154199685/Cordic.v\n             data/full_repos/permissive/154199685,data/full_repos/permissive/154199685/Cordic.sv\n             Cordic\n             Cordic.v\n             Cordic.sv\n             obj_dir/Cordic\n             obj_dir/Cordic.v\n             obj_dir/Cordic.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Cordic_tb;


	reg clk;
	reg [31:0] phase_step;
	reg [15:0] xin;
	reg [15:0] yin;


	wire [21:0] xout;
	wire [21:0] yout;


	Cordic uut (
		.clk(clk), 
		.phase_step(phase_step), 
		.xin(xin), 
		.yin(yin), 
		.xout(xout), 
		.yout(yout)
	);
	initial begin
			clk = 0;
			forever #10 clk=~clk;
	end
	initial begin

		phase_step = 32'b00110101_01010101_01010101_01010101;
		xin = 16'd10000;
		yin = 16'd0;


		#100;
      phase_step = 32'b00110101_01010101_01010101_01010101;
		xin = 16'd10000;
		yin = 16'd0;
  


	end
      
endmodule
module Cordic_tb;



	reg clk;
	reg [31:0] phase_step;
	reg [15:0] xin;
	reg [15:0] yin;


	wire [21:0] xout;
	wire [21:0] yout;


	Cordic uut (
		.clk(clk), 
		.phase_step(phase_step), 
		.xin(xin), 
		.yin(yin), 
		.xout(xout), 
		.yout(yout)
	);
	initial begin
			clk = 0;
			forever #10 clk=~clk;
	end
	initial begin

		phase_step = 32'b00110101_01010101_01010101_01010101;
		xin = 16'd10000;
		yin = 16'd0;


		#100;
      phase_step = 32'b00110101_01010101_01010101_01010101;
		xin = 16'd10000;
		yin = 16'd0;
  


	end
      
endmodule