data/full_repos/permissive/122125962/hardware/freq_compensate/tb_freq_correction.v
 line:257: before: "."
1: b'%Error: data/full_repos/permissive/122125962/hardware/freq_compensate/tb_freq_correction.v:18: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/122125962/hardware/freq_compensate/tb_freq_correction.v:22: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/122125962/hardware/freq_compensate/tb_freq_correction.v:29: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122125962/hardware/freq_compensate/tb_freq_correction.v:37: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module testbench();

reg		clk, resetn;
wire	[1:0]	direction;
reg	signed [7:0] I, Q;

freq_correction f0(.clk(clk), .resetn(resetn), .en(1'b1), .freq_mod(direction), .in_phase(I), .quad_phase(Q));

integer dat, cnt, ln_cnt;

`define SD 1

initial
begin
	dat = $fopen("IQ_deltaF.txt", "r");
	clk = 0;
	resetn = 0;
	@(negedge clk);
	@(negedge clk);
	@(negedge clk);
	resetn = 1;
	@(negedge clk);
	@(negedge clk);
	ln_cnt = 0;
	while (ln_cnt<8800)
	begin
		ln_cnt = ln_cnt + 1;
		cnt = $fscanf(dat, "%d %d", I, Q);
		@(negedge clk);
		@(negedge clk);
		@(negedge clk);
	end
	$fclose(dat);
	$finish;
end

always #5 clk = ~clk;


endmodule
module testbench();


reg		clk, resetn;
wire	[1:0]	direction;
reg	signed [7:0] I, Q;

freq_correction f0(.clk(clk), .resetn(resetn), .en(1'b1), .freq_mod(direction), .in_phase(I), .quad_phase(Q));

integer dat, cnt, ln_cnt;

`define SD 1

initial
begin
	dat = $fopen("IQ_deltaF.txt", "r");
	clk = 0;
	resetn = 0;
	@(negedge clk);
	@(negedge clk);
	@(negedge clk);
	resetn = 1;
	@(negedge clk);
	@(negedge clk);
	ln_cnt = 0;
	while (ln_cnt<8800)
	begin
		ln_cnt = ln_cnt + 1;
		cnt = $fscanf(dat, "%d %d", I, Q);
		@(negedge clk);
		@(negedge clk);
		@(negedge clk);
	end
	$fclose(dat);
	$finish;
end

always #5 clk = ~clk;


endmodule