data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_clock_cross.v
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_clock_cross.v:44: Cannot find file containing module: \'stream_buf_v\'\n  stream_buf_v #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream,data/full_repos/permissive/181738725/stream_buf_v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream,data/full_repos/permissive/181738725/stream_buf_v.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream,data/full_repos/permissive/181738725/stream_buf_v.sv\n             stream_buf_v\n             stream_buf_v.v\n             stream_buf_v.sv\n             obj_dir/stream_buf_v\n             obj_dir/stream_buf_v.v\n             obj_dir/stream_buf_v.sv\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_clock_cross.v:82: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                         : ... In instance stream_clock_cross\n    ready_toggle_sync <= {ready_toggle_sync, ready_toggle};\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_clock_cross.v:102: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                          : ... In instance stream_clock_cross\n    valid_toggle_sync <= {valid_toggle_sync, valid_toggle};\n                      ^~\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_clock_cross.v:129: Cannot find file containing module: \'stream_buf_v\'\n  stream_buf_v #(\n  ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module stream_clock_cross #(
  parameter DataBits = 8)
(
  input                 din_clk,
  input                 din_rst,
  output                din_ready,
  input                 din_valid,
  input [DataBits-1:0]  din_data,

  input                 dout_clk,
  input                 dout_rst,
  input                 dout_ready,
  output                dout_valid,
  output [DataBits-1:0] dout_data
);




  wire                  ibuf_valid, ibuf_ready;
  wire [DataBits-1:0]   ibuf_data;

  stream_buf_v #(
    .DataBits (DataBits))
  ibuf(
    .clk      (din_clk),
    .rst      (din_rst),

    .in_valid (din_valid),
    .in_ready (din_ready),
    .in_data  (din_data),

    .out_valid(ibuf_valid),
    .out_ready(ibuf_ready),
    .out_data (ibuf_data));




  localparam Idle      = 0,
             WaitReady = 1;

  reg       in_state, out_state;
  reg       valid_toggle,      ready_toggle;
  reg [2:0] valid_toggle_sync, ready_toggle_sync;

  always @(posedge din_clk) begin
    case (in_state)
      Idle:
        if (ibuf_valid) begin
          in_state     <= WaitReady;
          valid_toggle <= ~valid_toggle;
        end
      WaitReady:
        if (ibuf_ready) begin
          in_state <= Idle;
        end
    endcase


    ready_toggle_sync <= {ready_toggle_sync, ready_toggle};

    if (din_rst) begin
      in_state          <= Idle;
      valid_toggle      <= 0;
      ready_toggle_sync <= 0;
    end
  end


  assign ibuf_ready = ready_toggle_sync[2] ^ ready_toggle_sync[1];




  wire sync_valid, sync_ready;

  always @(posedge dout_clk) begin


    valid_toggle_sync <= {valid_toggle_sync, valid_toggle};

    case (out_state)
      Idle:

        if (valid_toggle_sync[2] ^ valid_toggle_sync[1]) begin
          out_state  <= WaitReady;
        end
      WaitReady:
        if (sync_ready) begin
          ready_toggle <= ~ready_toggle;
          out_state    <= Idle;
        end
    endcase

    if (dout_rst) begin
      out_state         <= Idle;
      ready_toggle      <= 0;
      valid_toggle_sync <= 0;
    end
  end

  assign sync_valid = (out_state == WaitReady);




  stream_buf_v #(
    .DataBits (DataBits))
  obuf(
    .clk      (dout_clk),
    .rst      (dout_rst),

    .in_valid (sync_valid),
    .in_ready (sync_ready),
    .in_data  (ibuf_data),

    .out_valid(dout_valid),
    .out_ready(dout_ready),
    .out_data (dout_data));

endmodule
module stream_clock_cross #(
  parameter DataBits = 8)
(
  input                 din_clk,
  input                 din_rst,
  output                din_ready,
  input                 din_valid,
  input [DataBits-1:0]  din_data,

  input                 dout_clk,
  input                 dout_rst,
  input                 dout_ready,
  output                dout_valid,
  output [DataBits-1:0] dout_data
);





  wire                  ibuf_valid, ibuf_ready;
  wire [DataBits-1:0]   ibuf_data;

  stream_buf_v #(
    .DataBits (DataBits))
  ibuf(
    .clk      (din_clk),
    .rst      (din_rst),

    .in_valid (din_valid),
    .in_ready (din_ready),
    .in_data  (din_data),

    .out_valid(ibuf_valid),
    .out_ready(ibuf_ready),
    .out_data (ibuf_data));




  localparam Idle      = 0,
             WaitReady = 1;

  reg       in_state, out_state;
  reg       valid_toggle,      ready_toggle;
  reg [2:0] valid_toggle_sync, ready_toggle_sync;

  always @(posedge din_clk) begin
    case (in_state)
      Idle:
        if (ibuf_valid) begin
          in_state     <= WaitReady;
          valid_toggle <= ~valid_toggle;
        end
      WaitReady:
        if (ibuf_ready) begin
          in_state <= Idle;
        end
    endcase


    ready_toggle_sync <= {ready_toggle_sync, ready_toggle};

    if (din_rst) begin
      in_state          <= Idle;
      valid_toggle      <= 0;
      ready_toggle_sync <= 0;
    end
  end


  assign ibuf_ready = ready_toggle_sync[2] ^ ready_toggle_sync[1];




  wire sync_valid, sync_ready;

  always @(posedge dout_clk) begin


    valid_toggle_sync <= {valid_toggle_sync, valid_toggle};

    case (out_state)
      Idle:

        if (valid_toggle_sync[2] ^ valid_toggle_sync[1]) begin
          out_state  <= WaitReady;
        end
      WaitReady:
        if (sync_ready) begin
          ready_toggle <= ~ready_toggle;
          out_state    <= Idle;
        end
    endcase

    if (dout_rst) begin
      out_state         <= Idle;
      ready_toggle      <= 0;
      valid_toggle_sync <= 0;
    end
  end

  assign sync_valid = (out_state == WaitReady);




  stream_buf_v #(
    .DataBits (DataBits))
  obuf(
    .clk      (dout_clk),
    .rst      (dout_rst),

    .in_valid (sync_valid),
    .in_ready (sync_ready),
    .in_data  (ibuf_data),

    .out_valid(dout_valid),
    .out_ready(dout_ready),
    .out_data (dout_data));

endmodule