data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v
 line:1: before: "$"
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v:1: Unsupported or unknown PLI call: $__MY_DPRAM_128x8\nmodule $__MY_DPRAM_128x8 (\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v:1: syntax error, unexpected ${ignored-bbox-sys}, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule $__MY_DPRAM_128x8 (\n                        ^\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module $__MY_DPRAM_128x8 (
  output [0:7] B1DATA,
  input CLK1,
  input [0:6] B1ADDR,
  input [0:6] A1ADDR,
  input [0:7] A1DATA,
  input A1EN,
  input B1EN );

  generate
    dpram_128x8 #() _TECHMAP_REPLACE_ (
      .clk    (CLK1),
      .wen    (A1EN),
      .waddr    (A1ADDR),
      .data_in    (A1DATA),
      .ren    (B1EN),
      .raddr    (B1ADDR),
      .data_out    (B1DATA) );
  endgenerate

endmodule
module $__MY_DPRAM_128x8 (
  output [0:7] B1DATA,
  input CLK1,
  input [0:6] B1ADDR,
  input [0:6] A1ADDR,
  input [0:7] A1DATA,
  input A1EN,
  input B1EN );


  generate
    dpram_128x8 #() _TECHMAP_REPLACE_ (
      .clk    (CLK1),
      .wen    (A1EN),
      .waddr    (A1ADDR),
      .data_in    (A1DATA),
      .ren    (B1EN),
      .raddr    (B1ADDR),
      .data_out    (B1DATA) );
  endgenerate

endmodule