data/full_repos/permissive/202776140/memory_bidi.v
data/verilator_xmls/403fa1b8-9c4e-473c-8d09-fc030ccb75c1.xml
module memory_bidi
(
    reset,
    clk,
    read_write,
    enable,
    address,
    data
);


parameter address_size = 16;
parameter memory_size = 2 ** address_size;


input wire reset, clk, read_write, enable;
input wire [address_size-1:0] address;                 
inout wire [15:0] data;


reg [15:0] memory_registers [memory_size-1:0];
reg [15:0] data_out;

always @ (negedge clk)
begin 
    if (!read_write) begin
        if (enable) begin
            memory_registers[address] <= data;
         end
    end 
    else begin
        data_out <= memory_registers[address];
    end
end

assign data = (enable && read_write) ? data_out : {16{1'bz}};

endmodule
module memory_bidi
(
    reset,
    clk,
    read_write,
    enable,
    address,
    data
);



parameter address_size = 16;
parameter memory_size = 2 ** address_size;


input wire reset, clk, read_write, enable;
input wire [address_size-1:0] address;                 
inout wire [15:0] data;


reg [15:0] memory_registers [memory_size-1:0];
reg [15:0] data_out;

always @ (negedge clk)
begin 
    if (!read_write) begin
        if (enable) begin
            memory_registers[address] <= data;
         end
    end 
    else begin
        data_out <= memory_registers[address];
    end
end

assign data = (enable && read_write) ? data_out : {16{1'bz}};

endmodule