data/full_repos/permissive/106492436/LCD_Controller_MIPS.sv
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data/verilator_xmls/72e8d362-1bb2-448f-8efb-f7095ca333bb.xml
module LCD_Controller_MIPS #(
	parameter	clk_wait	=	16) 
	(	
		input reset,clk, iRS, LCD_start,
		input [7:0] DATA,
		output [7:0] LCD_DATA,
		output logic LCD_EN, LCD_DONE,
		output LCD_RW, LCD_RS, LCD_ON 
	);


assign LCD_ON = 1;


assign	LCD_DATA	=	DATA; 
assign	LCD_RW		=	1'b0;
assign	LCD_RS		=	iRS;


enum {start, init, delay, done} state, next_state;
logic [4:0] counter;


always_ff @(posedge clk) begin
	state = (reset)? start : next_state;
end


always_ff @(posedge clk) begin
	unique case(state)
	start:begin
			LCD_DONE	=	1'b0;
			LCD_EN	=	1'b0;
			counter	=	0;
			next_state	=	init;
			end
	init:	begin
			LCD_EN	=	1'b1;
			next_state		=	delay;
			end
	delay:begin					
			if(counter<clk_wait)
			counter	=	counter+1;
			else
			next_state		=	done;
			end
	done:	begin
			LCD_EN	=	1'b0;
			LCD_DONE	=	1'b1;
			counter	=	0;
			if (LCD_start) begin
			next_state		=	start;
			end
			end
	endcase
end

endmodule
module LCD_Controller_MIPS #(
	parameter	clk_wait	=	16) 
	(	
		input reset,clk, iRS, LCD_start,
		input [7:0] DATA,
		output [7:0] LCD_DATA,
		output logic LCD_EN, LCD_DONE,
		output LCD_RW, LCD_RS, LCD_ON 
	);



assign LCD_ON = 1;


assign	LCD_DATA	=	DATA; 
assign	LCD_RW		=	1'b0;
assign	LCD_RS		=	iRS;


enum {start, init, delay, done} state, next_state;
logic [4:0] counter;


always_ff @(posedge clk) begin
	state = (reset)? start : next_state;
end


always_ff @(posedge clk) begin
	unique case(state)
	start:begin
			LCD_DONE	=	1'b0;
			LCD_EN	=	1'b0;
			counter	=	0;
			next_state	=	init;
			end
	init:	begin
			LCD_EN	=	1'b1;
			next_state		=	delay;
			end
	delay:begin					
			if(counter<clk_wait)
			counter	=	counter+1;
			else
			next_state		=	done;
			end
	done:	begin
			LCD_EN	=	1'b0;
			LCD_DONE	=	1'b1;
			counter	=	0;
			if (LCD_start) begin
			next_state		=	start;
			end
			end
	endcase
end

endmodule