data/full_repos/permissive/157005262/verilog/oled_play.v
None: at end of input
1: b'%Error: data/full_repos/permissive/157005262/verilog/oled_play.v:1: Cannot find include file: fpga-tools/components/uart.v\n`include "fpga-tools/components/uart.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/fpga-tools/components/uart.v\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/fpga-tools/components/uart.v.v\n             data/full_repos/permissive/157005262/verilog,data/full_repos/permissive/157005262/fpga-tools/components/uart.v.sv\n             fpga-tools/components/uart.v\n             fpga-tools/components/uart.v.v\n             fpga-tools/components/uart.v.sv\n             obj_dir/fpga-tools/components/uart.v\n             obj_dir/fpga-tools/components/uart.v.v\n             obj_dir/fpga-tools/components/uart.v.sv\n%Error: data/full_repos/permissive/157005262/verilog/oled_play.v:2: Cannot find include file: fpga-tools/components/oled.v\n`include "fpga-tools/components/oled.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module top(input wire  iCE_CLK,
           input wire  RS232_Rx_TTL,
           output wire PIO1_02,
           output wire PIO1_03,
           output wire PIO1_04,
           output wire PIO1_05,
           output wire PIO1_06);

  wire       d_read;


  wire [7:0] d_data;
  wire       d_ack;

  wire       uart_received;
  wire [7:0] uart_rx_byte;

  oled o(.clk(iCE_CLK),
         .pin_din(PIO1_02),
         .pin_clk(PIO1_03),
         .pin_cs(PIO1_04),
         .pin_dc(PIO1_05),
         .pin_res(PIO1_06),
         .read(d_read),


         .data(d_data),
         .ack(d_ack));

  uart #(.baud_rate(`BAUD_RATE), .sys_clk_freq(12000000))
  uart0(.clk(iCE_CLK),
        .rst(1'b0),
        .rx(RS232_Rx_TTL),

        .transmit(1'b0),

        .received(uart_received),
        .rx_byte(uart_rx_byte)



        );

  uart_display ud(.clk(iCE_CLK),
                  .d_read(d_read),
                  .d_data(d_data),
                  .d_ack(d_ack),
                  .uart_received(uart_received),
                  .uart_rx_byte(uart_rx_byte));

endmodule
module top(input wire  iCE_CLK,
           input wire  RS232_Rx_TTL,
           output wire PIO1_02,
           output wire PIO1_03,
           output wire PIO1_04,
           output wire PIO1_05,
           output wire PIO1_06);


  wire       d_read;


  wire [7:0] d_data;
  wire       d_ack;

  wire       uart_received;
  wire [7:0] uart_rx_byte;

  oled o(.clk(iCE_CLK),
         .pin_din(PIO1_02),
         .pin_clk(PIO1_03),
         .pin_cs(PIO1_04),
         .pin_dc(PIO1_05),
         .pin_res(PIO1_06),
         .read(d_read),


         .data(d_data),
         .ack(d_ack));

  uart #(.baud_rate(`BAUD_RATE), .sys_clk_freq(12000000))
  uart0(.clk(iCE_CLK),
        .rst(1'b0),
        .rx(RS232_Rx_TTL),

        .transmit(1'b0),

        .received(uart_received),
        .rx_byte(uart_rx_byte)



        );

  uart_display ud(.clk(iCE_CLK),
                  .d_read(d_read),
                  .d_data(d_data),
                  .d_ack(d_ack),
                  .uart_received(uart_received),
                  .uart_rx_byte(uart_rx_byte));

endmodule