data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v
1: b'%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:6: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:75: Define or directive not defined: \'`SERIAL_WCNT\'\n      end else if( waitnum >= `SERIAL_WCNT ) begin\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:75: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      end else if( waitnum >= `SERIAL_WCNT ) begin\n                                           ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:81: syntax error, unexpected else\n      end else begin\n          ^~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:192: Define or directive not defined: \'`SERIAL_WCNT\'\n   assign waitcnt = `SERIAL_WCNT;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:192: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   assign waitcnt = `SERIAL_WCNT;\n                                ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:283: Define or directive not defined: \'`APP_SIZE\'\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:283: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                               ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:287: Define or directive not defined: \'`APP_SIZE\'\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:287: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                               ^\n%Error: Exiting due to 10 error(s)\n'
module UartRx(CLK, RST_X, RXD, DATA, EN);
   input  wire       CLK, RST_X, RXD;
   output reg [7:0]  DATA;
   output reg        EN;

   reg [3:0] 	     stage;
   reg [12:0] 	     cnt;
   reg [11:0] 	     cnt_start;
   wire [12:0] 	     waitcnt;

   assign waitcnt = `SERIAL_WCNT;

   always @(posedge CLK or negedge RST_X)
     if (~RST_X) cnt_start <= 0;
     else        cnt_start <= (RXD) ? 0 : cnt_start + 1;

   always @(posedge CLK or negedge RST_X)
     if(~RST_X) begin
        EN     <= 0;
        stage  <= `SS_SER_WAIT;
        cnt    <= 1;
        DATA   <= 0;
     end else if (stage == `SS_SER_WAIT) begin
        EN <= 0;
        stage <= (cnt_start == (waitcnt >> 1)) ? `SS_SER_RCV0 : stage;
     end else begin
        if (cnt != waitcnt) begin
           cnt <= cnt + 1;
           EN <= 0;
        end else begin
           stage  <= (stage == `SS_SER_DONE) ? `SS_SER_WAIT : stage + 1;
           EN     <= (stage == 8)  ? 1 : 0;
           DATA   <= {RXD, DATA[7:1]};
           cnt <= 1;
        end
     end
endmodule
module UartRx(CLK, RST_X, RXD, DATA, EN);

   input  wire       CLK, RST_X, RXD;
   output reg [7:0]  DATA;
   output reg        EN;

   reg [3:0] 	     stage;
   reg [12:0] 	     cnt;
   reg [11:0] 	     cnt_start;
   wire [12:0] 	     waitcnt;

   assign waitcnt = `SERIAL_WCNT;

   always @(posedge CLK or negedge RST_X)
     if (~RST_X) cnt_start <= 0;
     else        cnt_start <= (RXD) ? 0 : cnt_start + 1;

   always @(posedge CLK or negedge RST_X)
     if(~RST_X) begin
        EN     <= 0;
        stage  <= `SS_SER_WAIT;
        cnt    <= 1;
        DATA   <= 0;
     end else if (stage == `SS_SER_WAIT) begin
        EN <= 0;
        stage <= (cnt_start == (waitcnt >> 1)) ? `SS_SER_RCV0 : stage;
     end else begin
        if (cnt != waitcnt) begin
           cnt <= cnt + 1;
           EN <= 0;
        end else begin
           stage  <= (stage == `SS_SER_DONE) ? `SS_SER_WAIT : stage + 1;
           EN     <= (stage == 8)  ? 1 : 0;
           DATA   <= {RXD, DATA[7:1]};
           cnt <= 1;
        end
     end
endmodule