data/full_repos/permissive/161329976/SLICE_WO.v
data/verilator_xmls/082bf441-1755-4fe7-98b8-bab1be17112f.xml
module SLICE_WO #(
    parameter win   = 64,
    parameter uout  = 31,
    parameter lout  = 18
    
    )(
    
    input                   clk_i,
    input   [win-1:0]       sig_i,
    output  [uout-lout:0]   sig_o
    );
        
    reg     [uout-lout:0]   sig;
    
    always @(posedge clk_i) begin
        if ({sig_i[win-1],|sig_i[win-3:uout]} == 2'b01)
            sig <= 14'h1FFF ;
        else if ({sig_i[win-1],&sig_i[win-2:uout]} == 2'b10)
            sig <= 14'h2000 ;
        else
            sig <= sig_i[uout:lout] ;
    end
    
    assign sig_o = sig;
    
endmodule
module SLICE_WO #(
    parameter win   = 64,
    parameter uout  = 31,
    parameter lout  = 18
    
    )(
    
    input                   clk_i,
    input   [win-1:0]       sig_i,
    output  [uout-lout:0]   sig_o
    );

        
    reg     [uout-lout:0]   sig;
    
    always @(posedge clk_i) begin
        if ({sig_i[win-1],|sig_i[win-3:uout]} == 2'b01)
            sig <= 14'h1FFF ;
        else if ({sig_i[win-1],&sig_i[win-2:uout]} == 2'b10)
            sig <= 14'h2000 ;
        else
            sig <= sig_i[uout:lout] ;
    end
    
    assign sig_o = sig;
    
endmodule