data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/MBE/testbench.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/MBE/testbench.sv:20: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/MBE/testbench.sv:20: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
    logic clk;
    logic [7:0] x;
	logic [3:0] single, double, neg;
    logic [7:0] vectors[256:0], currentvec;
    logic [8:0] vectornum, errors;
	integer out;
    

	mbe_4x dut(x, single, double, neg);
    

	initial begin
		$readmemb("input.txt", vectors);
		out = $fopen("output.txt","w");
		vectornum = 0; errors = 0;
	end

    always begin
       clk = 1; #10; clk = 0; #10;
    end
      

    always @(posedge clk) begin
       currentvec = vectors[vectornum];
	   x = currentvec;
       if (vectornum === 256) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);
                  $fclose(out);
         $stop;
       end
    end
    

    always @(negedge clk) begin

		$fwrite(out, "%b%h%h%h%h%h%h%h%h%h%h%h%h\n", 

		x,
		single[3], double[3], neg[3],
		single[2], double[2], neg[2],
		single[1], double[1], neg[1],
		single[0], double[0], neg[0]);
       vectornum = vectornum + 1;
    end
endmodule
module testbench();

    logic clk;
    logic [7:0] x;
	logic [3:0] single, double, neg;
    logic [7:0] vectors[256:0], currentvec;
    logic [8:0] vectornum, errors;
	integer out;
    

	mbe_4x dut(x, single, double, neg);
    

	initial begin
		$readmemb("input.txt", vectors);
		out = $fopen("output.txt","w");
		vectornum = 0; errors = 0;
	end

    always begin
       clk = 1; #10; clk = 0; #10;
    end
      

    always @(posedge clk) begin
       currentvec = vectors[vectornum];
	   x = currentvec;
       if (vectornum === 256) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);
                  $fclose(out);
         $stop;
       end
    end
    

    always @(negedge clk) begin

		$fwrite(out, "%b%h%h%h%h%h%h%h%h%h%h%h%h\n", 

		x,
		single[3], double[3], neg[3],
		single[2], double[2], neg[2],
		single[1], double[1], neg[1],
		single[0], double[0], neg[0]);
       vectornum = vectornum + 1;
    end
endmodule