data/full_repos/permissive/205055389/locale/en/examples/ex7/stdlogic.v
1: b"%Error: data/full_repos/permissive/205055389/locale/en/examples/ex7/stdlogic.v:372: Cannot find file containing module: 'H74181'\n  H74181 g8 (._A0(w26), ._A1(w25), ._A2(w24), ._A3(w23), ._B0(w22), ._B1(w21), ._B2(w20), ._B3(w19), .Cn(CI), .M(M), .S0(w115), .S1(w114), .S2(w113), .S3(w112), ._F0(w11), ._F1(w33), ._F2(w32), ._F3(w31), .AEB(w30), .CnP4(w29), ._G(w8), ._P(w4));    \n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205055389/locale/en/examples/ex7,data/full_repos/permissive/205055389/H74181\n             data/full_repos/permissive/205055389/locale/en/examples/ex7,data/full_repos/permissive/205055389/H74181.v\n             data/full_repos/permissive/205055389/locale/en/examples/ex7,data/full_repos/permissive/205055389/H74181.sv\n             H74181\n             H74181.v\n             H74181.sv\n             obj_dir/H74181\n             obj_dir/H74181.v\n             obj_dir/H74181.sv\n%Error: data/full_repos/permissive/205055389/locale/en/examples/ex7/stdlogic.v:381: Cannot find file containing module: 'H74181'\n  H74181 g10 (._A0(w45), ._A1(w27), ._A2(w28), ._A3(w35), ._B0(w39), ._B1(w15), ._B2(w17), ._B3(w18), .Cn(w37), .M(M), .S0(w3), .S1(w83), .S2(w84), .S3(w85), ._F0(w53), ._F1(w52), ._F2(w51), ._F3(w50), .AEB(w49), .CnP4(w48), ._G(w7), ._P(w46));    \n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/locale/en/examples/ex7/stdlogic.v:384: Cannot find file containing module: 'H74181'\n  H74181 g19 (.S3(w36), .S2(w47), .S1(w54), .S0(w82), .M(M), .Cn(w12), ._B3(w72), ._B2(w71), ._B1(w70), ._B0(w69), ._A3(w64), ._A2(w63), ._A1(w62), ._A0(w61), ._P(w2), ._G(w6), .CnP4(w91), .AEB(w90), ._F3(w89), ._F2(w88), ._F1(w87), ._F0(w86));    \n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/locale/en/examples/ex7/stdlogic.v:386: Cannot find file containing module: 'H74182'\n  H74182 g7 (._G0(w8), ._G1(w7), ._G2(w6), ._G3(w5), ._P0(w4), ._P1(w46), ._P2(w2), ._P3(w111), .Cn(CI), .CnPx(w37), .CnPy(w12), .CnPz(w99), ._G(w10), ._P(w9));    \n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/locale/en/examples/ex7/stdlogic.v:390: Cannot find file containing module: 'H74181'\n  H74181 g20 (.S3(w104), .S2(w103), .S1(w102), .S0(w101), .M(M), .Cn(w99), ._B3(w98), ._B2(w97), ._B1(w96), ._B0(w95), ._A3(w94), ._A2(w93), ._A1(w92), ._A0(w81), ._P(w111), ._G(w5), .CnP4(CO), .AEB(w109), ._F3(w108), ._F2(w107), ._F1(w106), ._F0(w105));    \n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/locale/en/examples/ex7/stdlogic.v:202: Cannot find file containing module: 'H74181'\n  H74181 g11 (._A0(w35), ._A1(w34), ._A2(w33), ._A3(w32), ._B0(w31), ._B1(w65), ._B2(w76), ._B3(w77), .Cn(w60), .M(M), .S0(w42), .S1(w44), .S2(w49), .S3(w54), ._F0(w106), ._F1(w94), ._F2(w103), ._F3(w98), .AEB(w39), .CnP4(w38), ._G(w37), ._P(w36));    \n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/locale/en/examples/ex7/stdlogic.v:205: Cannot find file containing module: 'H74181'\n  H74181 g10 (._A0(w57), ._A1(w56), ._A2(w55), ._A3(w41), ._B0(w27), ._B1(w52), ._B2(w51), ._B3(w24), .Cn(w16), .M(M), .S0(w68), .S1(w67), .S2(w66), .S3(w63), ._F0(w95), ._F1(w19), ._F2(w91), ._F3(w92), .AEB(w61), .CnP4(w60), ._G(w59), ._P(w58));    \n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/locale/en/examples/ex7/stdlogic.v:210: Cannot find file containing module: 'H74181'\n  H74181 g9 (._A0(w79), ._A1(w78), ._A2(w3), ._A3(w5), ._B0(w47), ._B1(w29), ._B2(w25), ._B3(w84), .Cn(w38), .M(M), .S0(w69), .S1(w70), .S2(w71), .S3(w82), ._F0(w99), ._F1(w104), ._F2(w101), ._F3(w105), .AEB(w83), .CnP4(CO), ._G(w81), ._P(w80));    \n  ^~~~~~\n%Error: data/full_repos/permissive/205055389/locale/en/examples/ex7/stdlogic.v:216: Cannot find file containing module: 'H74181'\n  H74181 g29 (._A0(w64), ._A1(w12), ._A2(w11), ._A3(w10), ._B0(w2), ._B1(w18), ._B2(w20), ._B3(w22), .Cn(CI), .M(M), .S0(w1), .S1(w46), .S2(w45), .S3(w0), ._F0(w48), ._F1(w85), ._F2(w86), ._F3(w87), .AEB(w17), .CnP4(w16), ._G(w15), ._P(w14));    \n  ^~~~~~\n%Error: Exiting due to 9 error(s)\n"
module ALU16_74181_74182(CI, F, OP, B, M, CO, A);

input M;





input [15:0] B;
output [15:0] F;
input [15:0] A;
output CO;
input [3:0] OP;





input CI;


wire w32;
wire w6;
wire w45;
wire w73;
wire w96;
wire w7;
wire w93;
wire w112;
wire w46;
wire w61;
wire w60;
wire w99;
wire [3:0] w16;
wire [3:0] w14;
wire w56;
wire w4;
wire w19;
wire w89;
wire w81;
wire w15;
wire w38;
wire w51;
wire w69;
wire w106;
wire w109;
wire w0;
wire w3;
wire w114;
wire w97;
wire w37;
wire w64;
wire w66;
wire w104;
wire w111;
wire w63;
wire w34;
wire w75;
wire w21;
wire w43;
wire w76;
wire w87;
wire w102;
wire w54;
wire w67;
wire w90;
wire [3:0] w100;
wire w31;
wire w58;
wire w28;
wire w36;
wire w20;
wire w23;
wire w41;
wire w24;
wire [3:0] w1;
wire w108;
wire w82;
wire w25;
wire w74;
wire w65;
wire w98;
wire [3:0] w116;
wire w35;
wire w8;
wire w91;
wire w103;
wire w18;
wire w40;
wire w92;
wire w71;
wire w101;
wire w30;
wire w68;
wire w17;
wire w22;
wire w53;
wire w84;
wire [3:0] w117;
wire w59;
wire w62;
wire w85;
wire w113;
wire w2;
wire w12;
wire w44;
wire w49;
wire w57;
wire w11;
wire w115;
wire w83;
wire w70;
wire w105;
wire w10;
wire w78;
wire w27;
wire w72;
wire w88;
wire w94;
wire w13;
wire w52;
wire w86;
wire w95;
wire w5;
wire w33;
wire w48;
wire w29;
wire w47;
wire w107;
wire w42;
wire w50;
wire w9;
wire w39;
wire w26;
wire w55;



  H74181 g8 (._A0(w26), ._A1(w25), ._A2(w24), ._A3(w23), ._B0(w22), ._B1(w21), ._B2(w20), ._B3(w19), .Cn(CI), .M(M), .S0(w115), .S1(w114), .S2(w113), .S3(w112), ._F0(w11), ._F1(w33), ._F2(w32), ._F3(w31), .AEB(w30), .CnP4(w29), ._G(w8), ._P(w4));
  assign w100 = {w38, w58, w40, w41};

  assign {w76, w75, w74, w73, w72, w71, w70, w69, w38, w58, w40, w41, w19, w20, w21, w22} = B;


  assign {w36, w47, w54, w82} = OP;
  assign {w68, w67, w66, w65, w64, w63, w62, w61, w42, w43, w44, w0, w23, w24, w25, w26} = A;
  assign {w35, w28, w27, w45} = w1;
  H74181 g10 (._A0(w45), ._A1(w27), ._A2(w28), ._A3(w35), ._B0(w39), ._B1(w15), ._B2(w17), ._B3(w18), .Cn(w37), .M(M), .S0(w3), .S1(w83), .S2(w84), .S3(w85), ._F0(w53), ._F1(w52), ._F2(w51), ._F3(w50), .AEB(w49), .CnP4(w48), ._G(w7), ._P(w46));
  assign {w98, w97, w96, w95} = w16;
  assign w1 = {w42, w43, w44, w0};
  H74181 g19 (.S3(w36), .S2(w47), .S1(w54), .S0(w82), .M(M), .Cn(w12), ._B3(w72), ._B2(w71), ._B1(w70), ._B0(w69), ._A3(w64), ._A2(w63), ._A1(w62), ._A0(w61), ._P(w2), ._G(w6), .CnP4(w91), .AEB(w90), ._F3(w89), ._F2(w88), ._F1(w87), ._F0(w86));

  H74182 g7 (._G0(w8), ._G1(w7), ._G2(w6), ._G3(w5), ._P0(w4), ._P1(w46), ._P2(w2), ._P3(w111), .Cn(CI), .CnPx(w37), .CnPy(w12), .CnPz(w99), ._G(w10), ._P(w9));


  assign w16 = {w76, w75, w74, w73};
  H74181 g20 (.S3(w104), .S2(w103), .S1(w102), .S0(w101), .M(M), .Cn(w99), ._B3(w98), ._B2(w97), ._B1(w96), ._B0(w95), ._A3(w94), ._A2(w93), ._A1(w92), ._A0(w81), ._P(w111), ._G(w5), .CnP4(CO), .AEB(w109), ._F3(w108), ._F2(w107), ._F1(w106), ._F0(w105));
  assign {w55, w13, w34, w78} = w116;
  assign {w85, w84, w83, w3} = OP;
  assign w14 = {w68, w67, w66, w65};
  assign {w112, w113, w114, w115} = OP;

  assign w117 = {w89, w88, w87, w86};
  assign {w104, w103, w102, w101} = OP;
  assign {w60, w59, w57, w56} = w117;
  assign w116 = {w31, w32, w33, w11};




  assign F = {w108, w107, w106, w105, w60, w59, w57, w56, w50, w51, w52, w53, w55, w13, w34, w78};
  assign {w18, w17, w15, w39} = w100;
  assign {w94, w93, w92, w81} = w14;

endmodule
module ALU16_74181_74182(CI, F, OP, B, M, CO, A);


input M;





input [15:0] B;
output [15:0] F;
input [15:0] A;
output CO;
input [3:0] OP;





input CI;


wire w32;
wire w6;
wire w45;
wire w73;
wire w96;
wire w7;
wire w93;
wire w112;
wire w46;
wire w61;
wire w60;
wire w99;
wire [3:0] w16;
wire [3:0] w14;
wire w56;
wire w4;
wire w19;
wire w89;
wire w81;
wire w15;
wire w38;
wire w51;
wire w69;
wire w106;
wire w109;
wire w0;
wire w3;
wire w114;
wire w97;
wire w37;
wire w64;
wire w66;
wire w104;
wire w111;
wire w63;
wire w34;
wire w75;
wire w21;
wire w43;
wire w76;
wire w87;
wire w102;
wire w54;
wire w67;
wire w90;
wire [3:0] w100;
wire w31;
wire w58;
wire w28;
wire w36;
wire w20;
wire w23;
wire w41;
wire w24;
wire [3:0] w1;
wire w108;
wire w82;
wire w25;
wire w74;
wire w65;
wire w98;
wire [3:0] w116;
wire w35;
wire w8;
wire w91;
wire w103;
wire w18;
wire w40;
wire w92;
wire w71;
wire w101;
wire w30;
wire w68;
wire w17;
wire w22;
wire w53;
wire w84;
wire [3:0] w117;
wire w59;
wire w62;
wire w85;
wire w113;
wire w2;
wire w12;
wire w44;
wire w49;
wire w57;
wire w11;
wire w115;
wire w83;
wire w70;
wire w105;
wire w10;
wire w78;
wire w27;
wire w72;
wire w88;
wire w94;
wire w13;
wire w52;
wire w86;
wire w95;
wire w5;
wire w33;
wire w48;
wire w29;
wire w47;
wire w107;
wire w42;
wire w50;
wire w9;
wire w39;
wire w26;
wire w55;



  H74181 g8 (._A0(w26), ._A1(w25), ._A2(w24), ._A3(w23), ._B0(w22), ._B1(w21), ._B2(w20), ._B3(w19), .Cn(CI), .M(M), .S0(w115), .S1(w114), .S2(w113), .S3(w112), ._F0(w11), ._F1(w33), ._F2(w32), ._F3(w31), .AEB(w30), .CnP4(w29), ._G(w8), ._P(w4));
  assign w100 = {w38, w58, w40, w41};

  assign {w76, w75, w74, w73, w72, w71, w70, w69, w38, w58, w40, w41, w19, w20, w21, w22} = B;


  assign {w36, w47, w54, w82} = OP;
  assign {w68, w67, w66, w65, w64, w63, w62, w61, w42, w43, w44, w0, w23, w24, w25, w26} = A;
  assign {w35, w28, w27, w45} = w1;
  H74181 g10 (._A0(w45), ._A1(w27), ._A2(w28), ._A3(w35), ._B0(w39), ._B1(w15), ._B2(w17), ._B3(w18), .Cn(w37), .M(M), .S0(w3), .S1(w83), .S2(w84), .S3(w85), ._F0(w53), ._F1(w52), ._F2(w51), ._F3(w50), .AEB(w49), .CnP4(w48), ._G(w7), ._P(w46));
  assign {w98, w97, w96, w95} = w16;
  assign w1 = {w42, w43, w44, w0};
  H74181 g19 (.S3(w36), .S2(w47), .S1(w54), .S0(w82), .M(M), .Cn(w12), ._B3(w72), ._B2(w71), ._B1(w70), ._B0(w69), ._A3(w64), ._A2(w63), ._A1(w62), ._A0(w61), ._P(w2), ._G(w6), .CnP4(w91), .AEB(w90), ._F3(w89), ._F2(w88), ._F1(w87), ._F0(w86));

  H74182 g7 (._G0(w8), ._G1(w7), ._G2(w6), ._G3(w5), ._P0(w4), ._P1(w46), ._P2(w2), ._P3(w111), .Cn(CI), .CnPx(w37), .CnPy(w12), .CnPz(w99), ._G(w10), ._P(w9));


  assign w16 = {w76, w75, w74, w73};
  H74181 g20 (.S3(w104), .S2(w103), .S1(w102), .S0(w101), .M(M), .Cn(w99), ._B3(w98), ._B2(w97), ._B1(w96), ._B0(w95), ._A3(w94), ._A2(w93), ._A1(w92), ._A0(w81), ._P(w111), ._G(w5), .CnP4(CO), .AEB(w109), ._F3(w108), ._F2(w107), ._F1(w106), ._F0(w105));
  assign {w55, w13, w34, w78} = w116;
  assign {w85, w84, w83, w3} = OP;
  assign w14 = {w68, w67, w66, w65};
  assign {w112, w113, w114, w115} = OP;

  assign w117 = {w89, w88, w87, w86};
  assign {w104, w103, w102, w101} = OP;
  assign {w60, w59, w57, w56} = w117;
  assign w116 = {w31, w32, w33, w11};




  assign F = {w108, w107, w106, w105, w60, w59, w57, w56, w50, w51, w52, w53, w55, w13, w34, w78};
  assign {w18, w17, w15, w39} = w100;
  assign {w94, w93, w92, w81} = w14;

endmodule