data/full_repos/permissive/114943225/ps2.v
data/verilator_xmls/d04a83ab-5624-446b-9147-a76fedf09d90.xml
module ps2key(
clk50,
kin,
kclk,
code
);

input kin, kclk, clk50;
output [7:0] code;
reg [7:0] code;
reg [3:0] i;
reg [10:0] ksr;
reg [15:0] cnt;
reg reset;

initial begin
 ksr = 0;
 i = 0;
 code = 0;
 cnt = 0;
 end 

always @ (posedge clk50) begin
  if (cnt > 3000)  begin
    reset <= 0;
    cnt <= 0;
    end
  else if (kclk == 1) begin
    reset <= 1;
    cnt <= cnt + 1;
    end
  else begin
    reset <= 1;
    cnt <= 0;
    end
  end
 
always @ (negedge kclk or negedge reset) begin
  if (reset == 0) begin
    ksr <= ksr;
    i <= 0;
    code <= code;
    end
  else if (i < 10) begin
    ksr[i] <= kin;
    i <= i + 1;
    code <= code;
    end
  else begin
    i <= 0;
    ksr[i] <= kin;
    code <= ksr[8:1];
    end
  end

endmodule
module ps2key(
clk50,
kin,
kclk,
code
);


input kin, kclk, clk50;
output [7:0] code;
reg [7:0] code;
reg [3:0] i;
reg [10:0] ksr;
reg [15:0] cnt;
reg reset;

initial begin
 ksr = 0;
 i = 0;
 code = 0;
 cnt = 0;
 end 

always @ (posedge clk50) begin
  if (cnt > 3000)  begin
    reset <= 0;
    cnt <= 0;
    end
  else if (kclk == 1) begin
    reset <= 1;
    cnt <= cnt + 1;
    end
  else begin
    reset <= 1;
    cnt <= 0;
    end
  end
 
always @ (negedge kclk or negedge reset) begin
  if (reset == 0) begin
    ksr <= ksr;
    i <= 0;
    code <= code;
    end
  else if (i < 10) begin
    ksr[i] <= kin;
    i <= i + 1;
    code <= code;
    end
  else begin
    i <= 0;
    ksr[i] <= kin;
    code <= ksr[8:1];
    end
  end

endmodule