data/full_repos/permissive/208741034/uart/rtl/uart_top.v
1: b"%Error: data/full_repos/permissive/208741034/uart/rtl/uart_top.v:20: Cannot find file containing module: 'ip_pll'\nip_pll ip_pll_inst (\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208741034/uart/rtl,data/full_repos/permissive/208741034/ip_pll\n             data/full_repos/permissive/208741034/uart/rtl,data/full_repos/permissive/208741034/ip_pll.v\n             data/full_repos/permissive/208741034/uart/rtl,data/full_repos/permissive/208741034/ip_pll.sv\n             ip_pll\n             ip_pll.v\n             ip_pll.sv\n             obj_dir/ip_pll\n             obj_dir/ip_pll.v\n             obj_dir/ip_pll.sv\n%Error: data/full_repos/permissive/208741034/uart/rtl/uart_top.v:27: Cannot find file containing module: 'uart_rx'\nuart_rx #(                           \n^~~~~~~\n%Error: data/full_repos/permissive/208741034/uart/rtl/uart_top.v:38: Cannot find file containing module: 'uart_tx'\nuart_tx  #(\n^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module uart_top(

  input clk,
  input rst_n,
  
  input  uart_rx,
  
  output uart_tx
   
);

parameter CLK_FREQ = 50000000;
parameter UART_BPS = 115200;


wire         uart_en_w;
wire [7 : 0] uart_data_w;
wire         clk_1m_w;

ip_pll	ip_pll_inst (
	.inclk0 ( clk ),
	.c0 ( clk_1m_w )
	);



uart_rx #(
    .CLK_FREQ       (CLK_FREQ),
    .UART_BPS       (UART_BPS))
u_uart_x(                 
    .clk        (clk), 
    .rst_n      (rst_n),
    
    .uart_rx_data       (uart_rx),
    .uart_rx_done       (uart_en_w),
    .uart_data          (uart_data_w)
    );
uart_tx  #(
    .CLK_FREQ  (CLK_FREQ),
    .UART_BPS  (UART_BPS))
 u_uart_tx(
    .clk          (clk),
    .rst_n        (rst_n),

    .uart_tx_flag (uart_en_w),
    .uart_data    (uart_data_w),
    .uart_tx_data (uart_tx)
);


endmodule
module uart_top(

  input clk,
  input rst_n,
  
  input  uart_rx,
  
  output uart_tx
   
);


parameter CLK_FREQ = 50000000;
parameter UART_BPS = 115200;


wire         uart_en_w;
wire [7 : 0] uart_data_w;
wire         clk_1m_w;

ip_pll	ip_pll_inst (
	.inclk0 ( clk ),
	.c0 ( clk_1m_w )
	);



uart_rx #(
    .CLK_FREQ       (CLK_FREQ),
    .UART_BPS       (UART_BPS))
u_uart_x(                 
    .clk        (clk), 
    .rst_n      (rst_n),
    
    .uart_rx_data       (uart_rx),
    .uart_rx_done       (uart_en_w),
    .uart_data          (uart_data_w)
    );
uart_tx  #(
    .CLK_FREQ  (CLK_FREQ),
    .UART_BPS  (UART_BPS))
 u_uart_tx(
    .clk          (clk),
    .rst_n        (rst_n),

    .uart_tx_flag (uart_en_w),
    .uart_data    (uart_data_w),
    .uart_tx_data (uart_tx)
);


endmodule