data/full_repos/permissive/201488448/1_verilog/25_cseladd.v
1: b"%Error: data/full_repos/permissive/201488448/1_verilog/25_cseladd.v:8: Cannot find file containing module: 'add16'\n    add16 a1(a[15:0], b[15:0], 1'b0, sum[15:0], sel);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/add16\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/add16.v\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/201488448/1_verilog/25_cseladd.v:9: Cannot find file containing module: 'add16'\n    add16 a2(a[31:16], b[31:16], 1'b0, sum2, bot2);\n    ^~~~~\n%Error: data/full_repos/permissive/201488448/1_verilog/25_cseladd.v:10: Cannot find file containing module: 'add16'\n    add16 a3(a[31:16], b[31:16], 1'b1, sum3, bot3);\n    ^~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire sel, bot2, bot3;
    wire [15:0]	sum2, sum3;
    add16 a1(a[15:0], b[15:0], 1'b0, sum[15:0], sel);
    add16 a2(a[31:16], b[31:16], 1'b0, sum2, bot2);
    add16 a3(a[31:16], b[31:16], 1'b1, sum3, bot3);
    assign	sum[31:16] = sel?sum3:sum2;
endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

    wire sel, bot2, bot3;
    wire [15:0]	sum2, sum3;
    add16 a1(a[15:0], b[15:0], 1'b0, sum[15:0], sel);
    add16 a2(a[31:16], b[31:16], 1'b0, sum2, bot2);
    add16 a3(a[31:16], b[31:16], 1'b1, sum3, bot3);
    assign	sum[31:16] = sel?sum3:sum2;
endmodule