data/full_repos/permissive/21370137/serial/slowClock.v
data/verilator_xmls/7df5d25b-df54-41d6-8742-d4483a744d74.xml
module slowClock (SYNC,CLK,SCLK);
	input SYNC;
	input CLK;
	output reg SCLK;
	
	reg [31:0] cnt;
	reg pSYNC;
	
	always @ (posedge CLK) begin
		if(!SYNC && pSYNC)begin
			cnt <= 32'd651;
		end else begin
			cnt <= cnt + 32'd1;
			if(cnt == 32'd1302)begin
				cnt <= 32'd0;
				SCLK <= ~SCLK;
			end
		end
		pSYNC <= SYNC;
	end
	
endmodule
module slowClock (SYNC,CLK,SCLK);

	input SYNC;
	input CLK;
	output reg SCLK;
	
	reg [31:0] cnt;
	reg pSYNC;
	
	always @ (posedge CLK) begin
		if(!SYNC && pSYNC)begin
			cnt <= 32'd651;
		end else begin
			cnt <= cnt + 32'd1;
			if(cnt == 32'd1302)begin
				cnt <= 32'd0;
				SCLK <= ~SCLK;
			end
		end
		pSYNC <= SYNC;
	end
	
endmodule