data/full_repos/permissive/18921956/HardwareLab/Lab3/bcd_counter.v
data/verilator_xmls/510fb0e8-6b3a-46e5-a252-6f0631814342.xml
module bcd_counter(reset, clk, en, co, out);
	output [3:0]out;
	output co;
	input clk, reset, en;
	reg [3:0]out;
	reg co;
	wire [3:0]tmp_out;
	initial begin
		co <= 0;
	end
	
	always @ (posedge clk or negedge reset) begin
		if (!reset) begin
			co <= 0;
			out <= 0;
		end
		else if (tmp_out == 10) begin
			out <= 0;
			co <= 0;
		end
		else if (tmp_out == 9) begin
			co <= 1;
			out <= tmp_out;
		end
		else begin
			out <= tmp_out;
		end
	end
	assign tmp_out = (en)?(out + 1):(out);

endmodule
module bcd_counter(reset, clk, en, co, out);

	output [3:0]out;
	output co;
	input clk, reset, en;
	reg [3:0]out;
	reg co;
	wire [3:0]tmp_out;
	initial begin
		co <= 0;
	end
	
	always @ (posedge clk or negedge reset) begin
		if (!reset) begin
			co <= 0;
			out <= 0;
		end
		else if (tmp_out == 10) begin
			out <= 0;
			co <= 0;
		end
		else if (tmp_out == 9) begin
			co <= 1;
			out <= tmp_out;
		end
		else begin
			out <= tmp_out;
		end
	end
	assign tmp_out = (en)?(out + 1):(out);

endmodule