data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v
None: at end of input
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:49: Cannot find include file: uart_defines.v\n`include "uart_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases,data/full_repos/permissive/17099167/uart_defines.v\n             data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases,data/full_repos/permissive/17099167/uart_defines.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases,data/full_repos/permissive/17099167/uart_defines.v.sv\n             uart_defines.v\n             uart_defines.v.v\n             uart_defines.v.sv\n             obj_dir/uart_defines.v\n             obj_dir/uart_defines.v.v\n             obj_dir/uart_defines.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:50: Cannot find include file: uart_testbench_defines.v\n`include "uart_testbench_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:51: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:61: Unsupported: event data types\n    event             severe_err_event;\n    ^~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:62: Unsupported: event data types\n    event             err_event;\n    ^~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:63: Unsupported: event data types\n    event             wrn_event;\n    ^~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:64: Unsupported: event data types\n    event             msg_event;\n    ^~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:65: Unsupported: event data types\n    event             val_event;\n    ^~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:66: Unsupported: event data types\n    event             testbench_log_written;\n    ^~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:72: Unsupported: event data types\n    event             testcase_log_written;\n    ^~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:73: Unsupported: event data types\n    event             test_end;\n    ^~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:83: Unsupported: fork statements\n  fork\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:91: Define or directive not defined: \'`SEVERE_ERROR\'\n      `SEVERE_ERROR("Failed to open log file(s)!");\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:91: syntax error, unexpected \';\'\n      `SEVERE_ERROR("Failed to open log file(s)!");\n                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:97: Unsupported: Ignoring delay on this delayed statement.\n    # 100;\n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:103: syntax error, unexpected \'@\'\n      @(test_name);\n      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:107: syntax error, unexpected ->\n      -> testcase_log_written;\n      ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:113: syntax error, unexpected \'@\'\n      @(test_end);\n      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:123: syntax error, unexpected ->\n      -> testcase_log_written;\n      ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:127: syntax error, unexpected \'@\'\n    @(severe_err_event);\n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:129: syntax error, unexpected ->\n    -> test_end;\n    ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:134: Unsupported: wait statements\n      wait (testcase.log.free);\n      ^~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:138: syntax error, unexpected ->\n    -> testbench_log_written;\n    ^~\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:139: Unsupported: Ignoring delay on this delayed statement.\n    # 100; $finish;\n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:144: syntax error, unexpected \'@\'\n      @(err_event);\n      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:146: syntax error, unexpected ->\n      -> test_end;\n      ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:151: Define or directive not defined: \'`SEVERE_ERROR\'\n        `SEVERE_ERROR("Failed to write to log file(s)!");\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:151: syntax error, unexpected \';\'\n        `SEVERE_ERROR("Failed to write to log file(s)!");\n                                                        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:154: syntax error, unexpected ->\n      -> testbench_log_written;\n      ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:155: Define or directive not defined: \'`PROMPT\'\n      `PROMPT;\n      ^~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:161: syntax error, unexpected \'@\'\n      @(wrn_event);\n      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:164: Define or directive not defined: \'`SEVERE_ERROR\'\n        `SEVERE_ERROR("Failed to write to log file(s)!");\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:164: syntax error, unexpected \';\'\n        `SEVERE_ERROR("Failed to write to log file(s)!");\n                                                        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:167: syntax error, unexpected ->\n      -> testbench_log_written;\n      ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:173: syntax error, unexpected \'@\'\n      @(msg_event);\n      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:176: Define or directive not defined: \'`SEVERE_ERROR\'\n        `SEVERE_ERROR("Failed to write to log file(s)!");\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:176: syntax error, unexpected \';\'\n        `SEVERE_ERROR("Failed to write to log file(s)!");\n                                                        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:179: syntax error, unexpected ->\n      -> testbench_log_written;\n      ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:185: syntax error, unexpected \'@\'\n      @(val_event);\n      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:188: Define or directive not defined: \'`SEVERE_ERROR\'\n        `SEVERE_ERROR("Failed to write to log file(s)!");\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:188: syntax error, unexpected \';\'\n        `SEVERE_ERROR("Failed to write to log file(s)!");\n                                                        ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:191: syntax error, unexpected ->\n      -> testbench_log_written;\n      ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:204: syntax error, unexpected \'@\'\n    @(testcase_log_written);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:211: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:229: syntax error, unexpected ->\n    -> test_end;\n    ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:238: syntax error, unexpected \'@\'\n    @(testcase_log_written);\n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:239: Unsupported: fork statements\n    fork\n    ^~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:242: syntax error, unexpected \'@\'\n      @(testbench.int_aserted);\n      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:243: Define or directive not defined: \'`TC_MSG\'\n      `TC_MSG("INT ASSERTED!");\n      ^~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:243: syntax error, unexpected \';\'\n      `TC_MSG("INT ASSERTED!");\n                              ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:245: syntax error, unexpected \'@\'\n      @(testbench.int_released);\n      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:246: Define or directive not defined: \'`TC_MSG\'\n      `TC_MSG("INT RELEASED!");\n      ^~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/uart16550/bench/verilog/test_cases/uart_int.v:246: syntax error, unexpected \';\'\n      `TC_MSG("INT RELEASED!");\n                              ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module testcase;







    event             severe_err_event;
    event             err_event;
    event             wrn_event;
    event             msg_event;
    event             val_event;
    event             testbench_log_written;
    reg     [7999: 0] tim;
    reg     [7999: 0] severe_err_msg;
    reg     [7999: 0] msg;
    integer           val;

    event             testcase_log_written;
    event             test_end;
    reg     [1599: 0] test_name;
    reg               error_detected;


  uart_log log ();
  defparam log.testcase_name = "uart_interrupts";


  initial
  fork
  begin: init_log
    reg               ok;

    #1;
    log.start_log(ok);
    if (ok !== 1'b1)
    begin
      `SEVERE_ERROR("Failed to open log file(s)!");
      disable init_log;
    end
    testcase_init;
    testcase_test;
    log.end_log;
    # 100;
    $finish;
  end
  begin
    forever
    begin
      @(test_name);
      error_detected = 1'b0;
      log.report_test_name(test_name);
      log.verbose_test_name(test_name);
      -> testcase_log_written;
    end
  end
  begin
    forever
    begin
      @(test_end);
      if (error_detected)
      begin
        log.tests_failed = log.tests_failed + 1'b1;
      end
      else
      begin
        log.tests_ok = log.tests_ok + 1'b1;
        log.report_test_ok;
      end
      -> testcase_log_written;
    end
  end
  begin
    @(severe_err_event);
    error_detected = 1'b1;
    -> test_end;
    @(testcase_log_written);
    log.report_test_failed(severe_err_msg);
    if (testcase.log.free == 0)
    begin
      wait (testcase.log.free);
      severe_err_msg = "Failed to write to log file(s)!";
    end
    log.verbose_severe_err(tim, severe_err_msg);
    -> testbench_log_written;
    # 100; $finish;
  end
  begin
    forever
    begin
      @(err_event);
      error_detected = 1'b1;
      -> test_end;
      @(testcase_log_written);
      log.report_test_failed(msg);
      if (testcase.log.free == 0)
      begin
        `SEVERE_ERROR("Failed to write to log file(s)!");
      end
      log.verbose_err(tim, msg);
      -> testbench_log_written;
      `PROMPT;
    end
  end
  begin
    forever
    begin
      @(wrn_event);
      if (testcase.log.free == 0)
      begin
        `SEVERE_ERROR("Failed to write to log file(s)!");
      end
      log.verbose_wrn(tim, msg);
      -> testbench_log_written;
    end
  end
  begin
    forever
    begin
      @(msg_event);
      if (testcase.log.free == 0)
      begin
        `SEVERE_ERROR("Failed to write to log file(s)!");
      end
      log.verbose_msg(tim, msg);
      -> testbench_log_written;
    end
  end
  begin
    forever
    begin
      @(val_event);
      if (testcase.log.free == 0)
      begin
        `SEVERE_ERROR("Failed to write to log file(s)!");
      end
      log.verbose_val(tim, msg, val);
      -> testbench_log_written;
    end
  end
  join
  





  task testcase_init;
  begin:init
    test_name = "Initialization of UART.";
    @(testcase_log_written);

    testbench_utilities.do_reset;
    testbench_utilities.disable_clk_generators(1, 1, 1, 1);
    testbench_utilities.set_device_tx_rx_clk_divisor(32'h1000);
    testbench_utilities.set_wb_clock_period(100);
    testbench_utilities.enable_clk_generators(1, 1, 1, 1);
    #100;
    testbench_utilities.release_reset;

    uart_wb_utilities.write_dlr(16'h1000);
    uart_wb_utilities.write_ier(8'h07);
    uart_wb_utilities.write_fcr(8'hC0);
    uart_wb_utilities.write_lcr(8'h03);

    uart_device_utilities.set_rx_length(8);
    uart_device_utilities.disable_rx_parity;
    uart_device_utilities.set_rx_second_stop_bit(0);

    uart_device_utilities.set_tx_length(8);
    uart_device_utilities.disable_tx_parity;
    uart_device_utilities.correct_tx_parity;
    uart_device_utilities.correct_tx_frame;
    uart_device_utilities.generate_tx_glitch(0);

    -> test_end;
    @(testcase_log_written);
  end
  endtask
  

  task testcase_test;
  begin:test
    test_name = "Interrupt test.";
    @(testcase_log_written);
    fork
    begin: test
      uart_wb_utilities.write_char(8'hAA);
      @(testbench.int_aserted);
      `TC_MSG("INT ASSERTED!");
      uart_wb_utilities.write_char(8'hAA);
      @(testbench.int_released);
      `TC_MSG("INT RELEASED!");
      @(testbench.int_aserted);
      `TC_MSG("INT ASSERTED!");
      uart_wb_utilities.read_iir;
      @(testbench.int_released);
      `TC_MSG("INT RELEASED!");
    end
    begin: wait_end
      @(testbench.i_uart_device.device_received_packet);
      @(testbench.i_uart_device.device_received_packet);
      repeat(2) @(testbench.i_uart_device.rx_clk);
      disable test;
      disable wait_clk;
    end
    begin: wait_clk
      testbench_utilities.wait_for_num_of_wb_clk(32'h450000);
      disable test;
      disable wait_end;
    end
    join
    repeat (4) @(posedge testbench.wb_clk);
    # 100;
  
    -> test_end;
    @(testcase_log_written);
  end
  endtask


endmodule
module testcase;








    event             severe_err_event;
    event             err_event;
    event             wrn_event;
    event             msg_event;
    event             val_event;
    event             testbench_log_written;
    reg     [7999: 0] tim;
    reg     [7999: 0] severe_err_msg;
    reg     [7999: 0] msg;
    integer           val;

    event             testcase_log_written;
    event             test_end;
    reg     [1599: 0] test_name;
    reg               error_detected;


  uart_log log ();
  defparam log.testcase_name = "uart_interrupts";


  initial
  fork
  begin: init_log
    reg               ok;

    #1;
    log.start_log(ok);
    if (ok !== 1'b1)
    begin
      `SEVERE_ERROR("Failed to open log file(s)!");
      disable init_log;
    end
    testcase_init;
    testcase_test;
    log.end_log;
    # 100;
    $finish;
  end
  begin
    forever
    begin
      @(test_name);
      error_detected = 1'b0;
      log.report_test_name(test_name);
      log.verbose_test_name(test_name);
      -> testcase_log_written;
    end
  end
  begin
    forever
    begin
      @(test_end);
      if (error_detected)
      begin
        log.tests_failed = log.tests_failed + 1'b1;
      end
      else
      begin
        log.tests_ok = log.tests_ok + 1'b1;
        log.report_test_ok;
      end
      -> testcase_log_written;
    end
  end
  begin
    @(severe_err_event);
    error_detected = 1'b1;
    -> test_end;
    @(testcase_log_written);
    log.report_test_failed(severe_err_msg);
    if (testcase.log.free == 0)
    begin
      wait (testcase.log.free);
      severe_err_msg = "Failed to write to log file(s)!";
    end
    log.verbose_severe_err(tim, severe_err_msg);
    -> testbench_log_written;
    # 100; $finish;
  end
  begin
    forever
    begin
      @(err_event);
      error_detected = 1'b1;
      -> test_end;
      @(testcase_log_written);
      log.report_test_failed(msg);
      if (testcase.log.free == 0)
      begin
        `SEVERE_ERROR("Failed to write to log file(s)!");
      end
      log.verbose_err(tim, msg);
      -> testbench_log_written;
      `PROMPT;
    end
  end
  begin
    forever
    begin
      @(wrn_event);
      if (testcase.log.free == 0)
      begin
        `SEVERE_ERROR("Failed to write to log file(s)!");
      end
      log.verbose_wrn(tim, msg);
      -> testbench_log_written;
    end
  end
  begin
    forever
    begin
      @(msg_event);
      if (testcase.log.free == 0)
      begin
        `SEVERE_ERROR("Failed to write to log file(s)!");
      end
      log.verbose_msg(tim, msg);
      -> testbench_log_written;
    end
  end
  begin
    forever
    begin
      @(val_event);
      if (testcase.log.free == 0)
      begin
        `SEVERE_ERROR("Failed to write to log file(s)!");
      end
      log.verbose_val(tim, msg, val);
      -> testbench_log_written;
    end
  end
  join
  





  task testcase_init;
  begin:init
    test_name = "Initialization of UART.";
    @(testcase_log_written);

    testbench_utilities.do_reset;
    testbench_utilities.disable_clk_generators(1, 1, 1, 1);
    testbench_utilities.set_device_tx_rx_clk_divisor(32'h1000);
    testbench_utilities.set_wb_clock_period(100);
    testbench_utilities.enable_clk_generators(1, 1, 1, 1);
    #100;
    testbench_utilities.release_reset;

    uart_wb_utilities.write_dlr(16'h1000);
    uart_wb_utilities.write_ier(8'h07);
    uart_wb_utilities.write_fcr(8'hC0);
    uart_wb_utilities.write_lcr(8'h03);

    uart_device_utilities.set_rx_length(8);
    uart_device_utilities.disable_rx_parity;
    uart_device_utilities.set_rx_second_stop_bit(0);

    uart_device_utilities.set_tx_length(8);
    uart_device_utilities.disable_tx_parity;
    uart_device_utilities.correct_tx_parity;
    uart_device_utilities.correct_tx_frame;
    uart_device_utilities.generate_tx_glitch(0);

    -> test_end;
    @(testcase_log_written);
  end
  endtask
  

  task testcase_test;
  begin:test
    test_name = "Interrupt test.";
    @(testcase_log_written);
    fork
    begin: test
      uart_wb_utilities.write_char(8'hAA);
      @(testbench.int_aserted);
      `TC_MSG("INT ASSERTED!");
      uart_wb_utilities.write_char(8'hAA);
      @(testbench.int_released);
      `TC_MSG("INT RELEASED!");
      @(testbench.int_aserted);
      `TC_MSG("INT ASSERTED!");
      uart_wb_utilities.read_iir;
      @(testbench.int_released);
      `TC_MSG("INT RELEASED!");
    end
    begin: wait_end
      @(testbench.i_uart_device.device_received_packet);
      @(testbench.i_uart_device.device_received_packet);
      repeat(2) @(testbench.i_uart_device.rx_clk);
      disable test;
      disable wait_clk;
    end
    begin: wait_clk
      testbench_utilities.wait_for_num_of_wb_clk(32'h450000);
      disable test;
      disable wait_end;
    end
    join
    repeat (4) @(posedge testbench.wb_clk);
    # 100;
  
    -> test_end;
    @(testcase_log_written);
  end
  endtask


endmodule