data/full_repos/permissive/140999934/CPU/sram_cpu/fetch.v
data/verilator_xmls/23700edb-e823-41e9-a74a-3f4b6ff4f6c2.xml
module fetch(
	input wire			clk,
	input wire			resetn,
	input wire			IF_valid,
	input wire			next_fetch,
	input wire 	[31:0]	inst,
	input wire	[32:0]	jbr_bus,
	output wire 		inst_en,
	output wire [ 3:0]	inst_wen,
	output wire	[31:0]	inst_addr,
	output reg			IF_over,
	output wire	[65:0]	IF_ID_bus,


	input wire	[32:0]	exc_bus,
	input wire          is_ds,
	input wire  [31:0]  ID_pc,     



	output wire	[31:0] 	IF_pc,
	output wire	[31:0]	IF_inst
);


	wire [31:0] next_pc;
	wire [31:0] seq_pc;
	reg  [31:0] pc;
    reg exc_flush_over;


	wire		jbr_taken;
	wire [31:0] jbr_target;
	assign {jbr_taken, jbr_target} = jbr_bus;


	wire		exc_valid;
	wire [31:0] exc_pc;
	assign {exc_valid, exc_pc} = exc_bus;


	assign seq_pc[31:2] = pc[31:2] + 1'b1;
	assign seq_pc[1:0] = pc[1:0];




	assign next_pc = exc_valid ? exc_pc : jbr_taken ? jbr_target : seq_pc;

	always @(posedge clk)
	begin
		if (!resetn)
		begin

			pc <= `STARTADDR;
			exc_flush_over <= 1'b0;	
		end
		else if (next_fetch)
		begin
			pc <= next_pc;
		end
	end



	assign inst_en   = IF_valid;
	assign inst_wen = 4'b0000;
	assign inst_addr = pc;









	always @(posedge clk)
	begin
		if (!resetn || next_fetch)
		begin

			IF_over <= 1'b0;	
		end
		else
		begin
			IF_over <= IF_valid;
		end
	end





	wire addr_exc;
	assign addr_exc = (pc[1:0]!=2'b00) ? 1'b1 : 1'b0;
	assign IF_ID_bus = {pc, inst, addr_exc, is_ds & (pc==(ID_pc + 32'd4))};



	assign IF_pc = pc;
	assign IF_inst = inst;

endmodule
module fetch(
	input wire			clk,
	input wire			resetn,
	input wire			IF_valid,
	input wire			next_fetch,
	input wire 	[31:0]	inst,
	input wire	[32:0]	jbr_bus,
	output wire 		inst_en,
	output wire [ 3:0]	inst_wen,
	output wire	[31:0]	inst_addr,
	output reg			IF_over,
	output wire	[65:0]	IF_ID_bus,


	input wire	[32:0]	exc_bus,
	input wire          is_ds,
	input wire  [31:0]  ID_pc,     



	output wire	[31:0] 	IF_pc,
	output wire	[31:0]	IF_inst
);



	wire [31:0] next_pc;
	wire [31:0] seq_pc;
	reg  [31:0] pc;
    reg exc_flush_over;


	wire		jbr_taken;
	wire [31:0] jbr_target;
	assign {jbr_taken, jbr_target} = jbr_bus;


	wire		exc_valid;
	wire [31:0] exc_pc;
	assign {exc_valid, exc_pc} = exc_bus;


	assign seq_pc[31:2] = pc[31:2] + 1'b1;
	assign seq_pc[1:0] = pc[1:0];




	assign next_pc = exc_valid ? exc_pc : jbr_taken ? jbr_target : seq_pc;

	always @(posedge clk)
	begin
		if (!resetn)
		begin

			pc <= `STARTADDR;
			exc_flush_over <= 1'b0;	
		end
		else if (next_fetch)
		begin
			pc <= next_pc;
		end
	end



	assign inst_en   = IF_valid;
	assign inst_wen = 4'b0000;
	assign inst_addr = pc;









	always @(posedge clk)
	begin
		if (!resetn || next_fetch)
		begin

			IF_over <= 1'b0;	
		end
		else
		begin
			IF_over <= IF_valid;
		end
	end





	wire addr_exc;
	assign addr_exc = (pc[1:0]!=2'b00) ? 1'b1 : 1'b0;
	assign IF_ID_bus = {pc, inst, addr_exc, is_ds & (pc==(ID_pc + 32'd4))};



	assign IF_pc = pc;
	assign IF_inst = inst;

endmodule