data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/micro_program_automate_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/micro_program_automate_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10000 tim <= 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/micro_program_automate_testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #60 clk <= ~clk;\n        ^\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/micro_program_automate_testbench.v:22: Cannot find file containing module: \'micro_program_automate\'\n    micro_program_automate uut(.reset(reset), .clk(clk), .a(a), .w(w), .sel(sel), .tim(tim),\n    ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/micro_program_automate\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/micro_program_automate.v\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/micro_program_automate.sv\n             micro_program_automate\n             micro_program_automate.v\n             micro_program_automate.sv\n             obj_dir/micro_program_automate\n             obj_dir/micro_program_automate.v\n             obj_dir/micro_program_automate.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module micro_program_automate_testbench();

    reg reset;
    reg clk;
    reg [1:0] a;
    reg w;
    reg sel;
    reg ie;
    reg cx1;
    reg tim;
    wire rdy;
    wire c1;
    wire c2;
    wire sel2;
    wire x0;
    wire x1;
    
    reg [31:0] counter;
    
    micro_program_automate uut(.reset(reset), .clk(clk), .a(a), .w(w), .sel(sel), .tim(tim),
                               .ie(ie), .cx1(cx1), .rdy(rdy), .c1(c1), .c2(c2), 
                               .sel2(sel2), .x0(x0), .x1(x1));
    
    initial
    begin
        reset <= 1;
        clk <= 0;
        a <= 0;
        w <= 0;
        sel <= 1;
        tim <= 0;
        ie <= 0;
        cx1 <= 1;
        counter <= 0;
        #10000 tim <= 1;
    end

    always
    begin
        #60 clk <= ~clk;
        counter <= counter + 1;
        if (counter == 20)
        begin
           reset <= 0;
        end
        if (counter > 0 && counter % 50 == 0)
        begin
            w <= ~w;
        end
        if (counter > 0 && counter % 10000 == 0)
            a <= a + 1;

        if (counter > 40000 && counter % 5000 == 0)
        begin

            ie <= ~ie;
        end
    end

endmodule
module micro_program_automate_testbench();


    reg reset;
    reg clk;
    reg [1:0] a;
    reg w;
    reg sel;
    reg ie;
    reg cx1;
    reg tim;
    wire rdy;
    wire c1;
    wire c2;
    wire sel2;
    wire x0;
    wire x1;
    
    reg [31:0] counter;
    
    micro_program_automate uut(.reset(reset), .clk(clk), .a(a), .w(w), .sel(sel), .tim(tim),
                               .ie(ie), .cx1(cx1), .rdy(rdy), .c1(c1), .c2(c2), 
                               .sel2(sel2), .x0(x0), .x1(x1));
    
    initial
    begin
        reset <= 1;
        clk <= 0;
        a <= 0;
        w <= 0;
        sel <= 1;
        tim <= 0;
        ie <= 0;
        cx1 <= 1;
        counter <= 0;
        #10000 tim <= 1;
    end

    always
    begin
        #60 clk <= ~clk;
        counter <= counter + 1;
        if (counter == 20)
        begin
           reset <= 0;
        end
        if (counter > 0 && counter % 50 == 0)
        begin
            w <= ~w;
        end
        if (counter > 0 && counter % 10000 == 0)
            a <= a + 1;

        if (counter > 40000 && counter % 5000 == 0)
        begin

            ie <= ~ie;
        end
    end

endmodule