data/full_repos/permissive/113344787/src/decimal/dec_to_seg.v
1: b"%Error: data/full_repos/permissive/113344787/src/decimal/dec_to_seg.v:6: Duplicate declaration of signal: 'seg'\n                                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    reg [6:0] seg;\n              ^~~\n        data/full_repos/permissive/113344787/src/decimal/dec_to_seg.v:3: ... Location of original declaration\n    output [6:0] seg\n                 ^~~\n%Error: Exiting due to 1 error(s)\n"
module dec_to_seg(
    input [3:0] dec_digit,
    output [6:0] seg
    );

    reg [6:0] seg;

    always @(dec_digit)
        case (dec_digit)
            4'h0: seg = 7'b0111111;
            4'h1: seg = 7'b0000110;
            4'h2: seg = 7'b1011011;
            4'h3: seg = 7'b1001111;
            4'h4: seg = 7'b1100110;
            4'h5: seg = 7'b1101101;
            4'h6: seg = 7'b1111101;
            4'h7: seg = 7'b0000111;
            4'h8: seg = 7'b1111111;
            4'h9: seg = 7'b1100111;

            default: seg = 7'b1111001;
        endcase
endmodule
module dec_to_seg(
    input [3:0] dec_digit,
    output [6:0] seg
    );


    reg [6:0] seg;

    always @(dec_digit)
        case (dec_digit)
            4'h0: seg = 7'b0111111;
            4'h1: seg = 7'b0000110;
            4'h2: seg = 7'b1011011;
            4'h3: seg = 7'b1001111;
            4'h4: seg = 7'b1100110;
            4'h5: seg = 7'b1101101;
            4'h6: seg = 7'b1111101;
            4'h7: seg = 7'b0000111;
            4'h8: seg = 7'b1111111;
            4'h9: seg = 7'b1100111;

            default: seg = 7'b1111001;
        endcase
endmodule