data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_write_back.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_write_back.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_write_back.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_write_back.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;   \n        ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_write_back.v:27: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h3\' generates 5 bits.\n                                                                                              : ... In instance tb_seg_write_back\n        i_read_data = 5\'b00011;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_write_back.v:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1c\' generates 5 bits.\n                                                                                              : ... In instance tb_seg_write_back\n        i_ALU_result = 5\'b11100;\n                     ^\n%Error: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_write_back.v:38: Cannot find file containing module: \'seg_write_back\'\n    seg_write_back \n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_write_back\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_write_back.v\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_write_back.sv\n             seg_write_back\n             seg_write_back.v\n             seg_write_back.sv\n             obj_dir/seg_write_back\n             obj_dir/seg_write_back.v\n             obj_dir/seg_write_back.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_seg_write_back();
    parameter   LEN          = 32;
    parameter   NB_ADDR      = 5;
    parameter   NB_CTRL_WB   = 2;
    

    reg [LEN-1 : 0]      i_read_data;
    reg [LEN-1 : 0]      i_ALU_result;
    reg [NB_ADDR-1:0]    i_write_register;

    reg [NB_CTRL_WB-1:0] i_ctrl_wb_bus;
    

    wire                 o_RegWrite;
    wire [LEN -1 : 0]    o_write_data;
    wire [NB_ADDR-1:0]   o_write_register;
    
    initial begin
        i_read_data = 0;
        i_ALU_result = 0;
        i_ctrl_wb_bus = 0;
        i_write_register = 0;
        
        #10
        i_read_data = 5'b00011;
        i_ALU_result = 5'b11100;
        i_ctrl_wb_bus = 2'b01;
        
        #10
        i_ctrl_wb_bus = 2'b00;
        
        #10 $finish;   
    end
    

    seg_write_back 
    #(
        .LEN        (LEN        ),
        .NB_ADDR    (NB_ADDR    ),
        .NB_CTRL_WB (NB_CTRL_WB )
    )
    u_seg_write_back(
    	.i_read_data      (i_read_data      ),
        .i_ALU_result     (i_ALU_result     ),
        .i_write_register (i_write_register ),
        .i_ctrl_wb_bus    (i_ctrl_wb_bus    ),
        .o_RegWrite       (o_RegWrite       ),
        .o_write_data     (o_write_data     ),
        .o_write_register (o_write_register )
    );
    
endmodule
module tb_seg_write_back();

    parameter   LEN          = 32;
    parameter   NB_ADDR      = 5;
    parameter   NB_CTRL_WB   = 2;
    

    reg [LEN-1 : 0]      i_read_data;
    reg [LEN-1 : 0]      i_ALU_result;
    reg [NB_ADDR-1:0]    i_write_register;

    reg [NB_CTRL_WB-1:0] i_ctrl_wb_bus;
    

    wire                 o_RegWrite;
    wire [LEN -1 : 0]    o_write_data;
    wire [NB_ADDR-1:0]   o_write_register;
    
    initial begin
        i_read_data = 0;
        i_ALU_result = 0;
        i_ctrl_wb_bus = 0;
        i_write_register = 0;
        
        #10
        i_read_data = 5'b00011;
        i_ALU_result = 5'b11100;
        i_ctrl_wb_bus = 2'b01;
        
        #10
        i_ctrl_wb_bus = 2'b00;
        
        #10 $finish;   
    end
    

    seg_write_back 
    #(
        .LEN        (LEN        ),
        .NB_ADDR    (NB_ADDR    ),
        .NB_CTRL_WB (NB_CTRL_WB )
    )
    u_seg_write_back(
    	.i_read_data      (i_read_data      ),
        .i_ALU_result     (i_ALU_result     ),
        .i_write_register (i_write_register ),
        .i_ctrl_wb_bus    (i_ctrl_wb_bus    ),
        .o_RegWrite       (o_RegWrite       ),
        .o_write_data     (o_write_data     ),
        .o_write_register (o_write_register )
    );
    
endmodule