data/full_repos/permissive/126689099/ip_multi_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/126689099/ip_multi_test.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/126689099/ip_multi_test.v:36: Cannot find file containing module: \'ip_multi\'\n ip_multi uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/126689099,data/full_repos/permissive/126689099/ip_multi\n             data/full_repos/permissive/126689099,data/full_repos/permissive/126689099/ip_multi.v\n             data/full_repos/permissive/126689099,data/full_repos/permissive/126689099/ip_multi.sv\n             ip_multi\n             ip_multi.v\n             ip_multi.sv\n             obj_dir/ip_multi\n             obj_dir/ip_multi.v\n             obj_dir/ip_multi.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ip_multi_test;


	reg clk;
	reg [13:0] a;
	reg [13:0] b;


	wire [14:0] p;


	ip_multi uut (
		.clk(clk), 
		.a(a), 
		.b(b), 
		.p(p)
	);

	initial begin

		clk = 0;
		a = 0;
		b = 0;


		#100;
        


	end
      
endmodule
module ip_multi_test;



	reg clk;
	reg [13:0] a;
	reg [13:0] b;


	wire [14:0] p;


	ip_multi uut (
		.clk(clk), 
		.a(a), 
		.b(b), 
		.p(p)
	);

	initial begin

		clk = 0;
		a = 0;
		b = 0;


		#100;
        


	end
      
endmodule