data/full_repos/permissive/175070965/lib/OPENCORES/ETH/eth_spram_256x32.v
1: b"%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/eth_spram_256x32.v:54: Cannot find file containing module: 'dftmem'\ndftmem #(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175070965/lib/OPENCORES/ETH,data/full_repos/permissive/175070965/dftmem\n             data/full_repos/permissive/175070965/lib/OPENCORES/ETH,data/full_repos/permissive/175070965/dftmem.v\n             data/full_repos/permissive/175070965/lib/OPENCORES/ETH,data/full_repos/permissive/175070965/dftmem.sv\n             dftmem\n             dftmem.v\n             dftmem.sv\n             obj_dir/dftmem\n             obj_dir/dftmem.v\n             obj_dir/dftmem.sv\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/eth_spram_256x32.v:89: Cannot find file containing module: 'ram_mem_sim'\n        ram_mem_sim #(\n        ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module eth_spram_256x32
#(
     parameter [31:0] DFT_MEM     = 32'd0,
     parameter [31:0] TARGET_FPGA = 32'd0,
     parameter [31:0] TARGET_ASIC = 32'd0
)(
    input wire           clk,
    input wire           rst,
    input wire           ce,
    input wire  [3:0]    we,
    input wire           oe,
    input wire  [7:0]    addr,
    input wire  [31:0]   di,
    output wire [31:0]   dato,
    input wire           test_mode
);





wire    [31:0]    dft_dato;
wire    [3:0]     dft_we;
wire              dft_ce;





dftmem #(
    .DWIDTH(32),
    .CWIDTH(14),
    .DFT_MEM(DFT_MEM),
    .WE_WIDTH(4))
dftmem_u (
    .clk(clk),
    .data_mem_in(di),
    .data_mem_out(dft_dato),
    .ctrl_in({ce,we,oe,addr}),
    .test_mode(test_mode),
    .en(test_mode|ce),
    .data_out(dato),
    .re_in(ce),
    .re_out(dft_ce),
    .we_in(we),
    .we_out(dft_we));

generate
    if (TARGET_FPGA == 1) begin : virtex6


        blk_sp_mem_1kB
        eth_bd_memory (
            .clka(clk),
            .ena(dft_ce),
            .wea(|dft_we),
            .addra(addr),
            .dina(di),
            .douta(dft_dato));

    end
    else if ((TARGET_ASIC == 0) && (TARGET_FPGA == 0)) begin : sim


        ram_mem_sim #(
            .SIZE(10))
        eth_bd_memory_sim (
            .clk(clk),
            .ren(dft_ce),
            .we(dft_we),
            .addr(addr),
            .din(di),
            .dout(dft_dato));

    end





    else begin : memory_error
        `ifndef GATE
            initial begin
                $display("CONFIG_ERROR: Not supported eth_bd memory technology!\n");
                $finish;
            end
        `endif
    end
endgenerate

endmodule
module eth_spram_256x32
#(
     parameter [31:0] DFT_MEM     = 32'd0,
     parameter [31:0] TARGET_FPGA = 32'd0,
     parameter [31:0] TARGET_ASIC = 32'd0
)(
    input wire           clk,
    input wire           rst,
    input wire           ce,
    input wire  [3:0]    we,
    input wire           oe,
    input wire  [7:0]    addr,
    input wire  [31:0]   di,
    output wire [31:0]   dato,
    input wire           test_mode
);






wire    [31:0]    dft_dato;
wire    [3:0]     dft_we;
wire              dft_ce;





dftmem #(
    .DWIDTH(32),
    .CWIDTH(14),
    .DFT_MEM(DFT_MEM),
    .WE_WIDTH(4))
dftmem_u (
    .clk(clk),
    .data_mem_in(di),
    .data_mem_out(dft_dato),
    .ctrl_in({ce,we,oe,addr}),
    .test_mode(test_mode),
    .en(test_mode|ce),
    .data_out(dato),
    .re_in(ce),
    .re_out(dft_ce),
    .we_in(we),
    .we_out(dft_we));

generate
    if (TARGET_FPGA == 1) begin : virtex6


        blk_sp_mem_1kB
        eth_bd_memory (
            .clka(clk),
            .ena(dft_ce),
            .wea(|dft_we),
            .addra(addr),
            .dina(di),
            .douta(dft_dato));

    end
    else if ((TARGET_ASIC == 0) && (TARGET_FPGA == 0)) begin : sim


        ram_mem_sim #(
            .SIZE(10))
        eth_bd_memory_sim (
            .clk(clk),
            .ren(dft_ce),
            .we(dft_we),
            .addr(addr),
            .din(di),
            .dout(dft_dato));

    end





    else begin : memory_error
        `ifndef GATE
            initial begin
                $display("CONFIG_ERROR: Not supported eth_bd memory technology!\n");
                $finish;
            end
        `endif
    end
endgenerate

endmodule