data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6.v
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data/verilator_xmls/8da96748-135e-4ee3-b6b2-309749f85b24.xml
module carrysave_4is2 (
input [4:0] in,
output c0,
output c1,
output sum
);
wire connection;
FullAdder FA0 (in[0],in[1],in[2],connection,c0);
FullAdder FA1 (connection,in[4],in[3],sum,c1);
endmodule
module carrysave_4is2 (
input [4:0] in,
output c0,
output c1,
output sum
);

wire connection;
FullAdder FA0 (in[0],in[1],in[2],connection,c0);
FullAdder FA1 (connection,in[4],in[3],sum,c1);
endmodule