data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:41: Unsupported: Ignoring delay on this delayed statement.\n                    #1;\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:49: Unsupported: Ignoring delay on this delayed statement.\n                    #1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:16: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h777\' generates 12 bits.\n                                                                                       : ... In instance doremi\n        8\'b10000000: limit = 12\'d1911;  \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h7e9\' generates 12 bits.\n                                                                                       : ... In instance doremi\n        8\'b01000000: limit = 12\'d2025;  \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:18: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h8e1\' generates 12 bits.\n                                                                                       : ... In instance doremi\n        8\'b00100000: limit = 12\'d2273;  \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:19: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h9f7\' generates 12 bits.\n                                                                                       : ... In instance doremi\n        8\'b00010000: limit = 12\'d2551;  \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:20: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'hb30\' generates 12 bits.\n                                                                                       : ... In instance doremi\n        8\'b00001000: limit = 12\'d2864;  \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:21: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'hbda\' generates 12 bits.\n                                                                                       : ... In instance doremi\n        8\'b00000100: limit = 12\'d3034;  \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:22: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'hd4d\' generates 12 bits.\n                                                                                       : ... In instance doremi\n        8\'b00000010: limit = 12\'d3405;  \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:23: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'heee\' generates 12 bits.\n                                                                                       : ... In instance doremi\n        8\'b00000001: limit = 12\'d3822;  \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:24: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance doremi\n        default : limit = 1\'b0;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:33: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance doremi\n            cnt <= 1\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:39: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance doremi\n                for(cnt= 1\'b0; cnt < limit/2; cnt = cnt +1)\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/202237519/verilog/digitalsystem9/doremi.v:47: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance doremi\n                for(cnt= 1\'b0; cnt < limit/2; cnt = cnt +1)\n                       ^\n%Error: Exiting due to 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module doremi (reset, clk, key, piezo);

input clk,reset;
input [7:0] key;
output piezo;
reg buff;
integer cnt, limit;
wire piezo;

assign piezo = buff;

always@(key)
begin
    case(key)
        8'b10000000: limit = 12'd1911;
        8'b01000000: limit = 12'd2025;
        8'b00100000: limit = 12'd2273;
        8'b00010000: limit = 12'd2551;
        8'b00001000: limit = 12'd2864;
        8'b00000100: limit = 12'd3034;
        8'b00000010: limit = 12'd3405;
        8'b00000001: limit = 12'd3822;
        default : limit = 1'b0;
    endcase
end

always@(posedge clk)
begin
    if(reset)
        begin
            buff <= 1'b0;
            cnt <= 1'b0;
        end
    else
        begin
            if(buff == 1'b0)
            begin
                for(cnt= 1'b0; cnt < limit/2; cnt = cnt +1)
                begin
                    #1;
                end
                buff <= 1'b1;
            end
            else 
            begin
                for(cnt= 1'b0; cnt < limit/2; cnt = cnt +1)
                begin
                    #1;
                end
                buff <= 1'b0;
            end
        end
end

endmodule
module doremi (reset, clk, key, piezo);


input clk,reset;
input [7:0] key;
output piezo;
reg buff;
integer cnt, limit;
wire piezo;

assign piezo = buff;

always@(key)
begin
    case(key)
        8'b10000000: limit = 12'd1911;
        8'b01000000: limit = 12'd2025;
        8'b00100000: limit = 12'd2273;
        8'b00010000: limit = 12'd2551;
        8'b00001000: limit = 12'd2864;
        8'b00000100: limit = 12'd3034;
        8'b00000010: limit = 12'd3405;
        8'b00000001: limit = 12'd3822;
        default : limit = 1'b0;
    endcase
end

always@(posedge clk)
begin
    if(reset)
        begin
            buff <= 1'b0;
            cnt <= 1'b0;
        end
    else
        begin
            if(buff == 1'b0)
            begin
                for(cnt= 1'b0; cnt < limit/2; cnt = cnt +1)
                begin
                    #1;
                end
                buff <= 1'b1;
            end
            else 
            begin
                for(cnt= 1'b0; cnt < limit/2; cnt = cnt +1)
                begin
                    #1;
                end
                buff <= 1'b0;
            end
        end
end

endmodule