data/full_repos/permissive/206547749/src/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/206547749/src/top.v:32: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 26 bits.\n                                                                 : ... In instance top\nreg [17:0] cntr = F_CLK/(4*16);\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/206547749/src/top.v:38: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 26 bits.\n                                                                 : ... In instance top\n    cntr <= F_CLK/4;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/206547749/src/top.v:43: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n                                                                 : ... In instance top\nassign p1 = \'bz;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/206547749/src/top.v:44: Operator ASSIGNW expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n                                                                 : ... In instance top\nassign p2 = \'bz;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/206547749/src/top.v:45: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n                                                                 : ... In instance top\nassign p3[16:0] = \'bz;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/206547749/src/top.v:48: Operator ASSIGNW expects 20 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n                                                                 : ... In instance top\nassign p4 = \'bz;\n          ^\n%Error: Exiting due to 6 warning(s)\n'
module top #(
  parameter F_CLK = 50000000
) (
  input wire clk_i,
  inout wire [16:0] p1,
  inout wire [19:0] p2,
  inout wire [18:0] p3,
  inout wire [19:0] p4
);


reg clk_div2 = 1'b0;
always @ (posedge clk_i)
  clk_div2 <= !clk_div2;

reg clk_div4 = 1'b0;
always @ (posedge clk_div2)
  clk_div4 <= !clk_div4;

reg clk_div8 = 1'b0;
always @ (posedge clk_div4)
  clk_div8 <= !clk_div8;

reg clk_div16 = 1'b0;
always @ (posedge clk_div8)
  clk_div16 <= !clk_div16;

reg [17:0] cntr = F_CLK/(4*16);
reg led = 0;
always @ (posedge clk_div16)
begin
  cntr <= cntr - 1;
  if (cntr == 'd0) begin
    cntr <= F_CLK/4;
    led <= !led;
  end
end

assign p1 = 'bz;
assign p2 = 'bz;
assign p3[16:0] = 'bz;
assign p3[17] = led;
assign p3[18] = !led;
assign p4 = 'bz;

endmodule
module top #(
  parameter F_CLK = 50000000
) (
  input wire clk_i,
  inout wire [16:0] p1,
  inout wire [19:0] p2,
  inout wire [18:0] p3,
  inout wire [19:0] p4
);



reg clk_div2 = 1'b0;
always @ (posedge clk_i)
  clk_div2 <= !clk_div2;

reg clk_div4 = 1'b0;
always @ (posedge clk_div2)
  clk_div4 <= !clk_div4;

reg clk_div8 = 1'b0;
always @ (posedge clk_div4)
  clk_div8 <= !clk_div8;

reg clk_div16 = 1'b0;
always @ (posedge clk_div8)
  clk_div16 <= !clk_div16;

reg [17:0] cntr = F_CLK/(4*16);
reg led = 0;
always @ (posedge clk_div16)
begin
  cntr <= cntr - 1;
  if (cntr == 'd0) begin
    cntr <= F_CLK/4;
    led <= !led;
  end
end

assign p1 = 'bz;
assign p2 = 'bz;
assign p3[16:0] = 'bz;
assign p3[17] = led;
assign p3[18] = !led;
assign p4 = 'bz;

endmodule