data/full_repos/permissive/143278/ivltests/udp_bufg.v
 line:20: before: "primitive"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_bufg.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (out != 0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_bufg.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (out != 1) begin\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
   wire out;
   reg in;

   BUFG bg(out, in);

   initial begin
      in = 0;
      #1 if (out != 0) begin
	 $display("FAILED -- %b != 0", out);
	 $finish;
      end
      in = 1;
      #1 if (out != 1) begin
	 $display("FAILED -- %b != 1", out);
	 $finish;
      end
      $display("PASSED");
   end
endmodule
module main;

   wire out;
   reg in;

   BUFG bg(out, in);

   initial begin
      in = 0;
      #1 if (out != 0) begin
	 $display("FAILED -- %b != 0", out);
	 $finish;
      end
      in = 1;
      #1 if (out != 1) begin
	 $display("FAILED -- %b != 1", out);
	 $finish;
      end
      $display("PASSED");
   end
endmodule