data/full_repos/permissive/188039952/Spartan 6/ROCounter.v
1: b'%Error: Cannot find file containing module: 6,data/full_repos/permissive/188039952\n        ... Looked in:\n             data/full_repos/permissive/188039952/Spartan/6,data/full_repos/permissive/188039952\n             data/full_repos/permissive/188039952/Spartan/6,data/full_repos/permissive/188039952.v\n             data/full_repos/permissive/188039952/Spartan/6,data/full_repos/permissive/188039952.sv\n             6,data/full_repos/permissive/188039952\n             6,data/full_repos/permissive/188039952.v\n             6,data/full_repos/permissive/188039952.sv\n             obj_dir/6,data/full_repos/permissive/188039952\n             obj_dir/6,data/full_repos/permissive/188039952.v\n             obj_dir/6,data/full_repos/permissive/188039952.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/188039952/Spartan\n%Error: Cannot find file containing module: 6/ROCounter.v\n%Error: Exiting due to 3 error(s)\n'
module ROCounter #(
		parameter 					length = 16
	)(
		input 						clk,
		input 						rst,
		input 						RO0In,
		input 						RO1In,
		output reg [length-1:0] RO0Cnt,
		output reg [length-1:0] RO1Cnt,
		output reg [length-1:0] ClkCnt
	);
	

	always @(posedge clk) begin
		if (rst) begin
			ClkCnt <= {length-1{1'b0}};
		end
		else begin
			ClkCnt <= ClkCnt + 1;
		end
	end


	always @(posedge RO0In) begin
		if (rst) begin
			RO0Cnt <= {length-1{1'b0}};
		end
		else begin
			RO0Cnt <= RO0Cnt + 1;
		end
	end
	

	always @(posedge RO1In) begin
		if (rst) begin
			RO1Cnt <= {length-1{1'b0}};
		end
		else begin
			RO1Cnt <= RO1Cnt + 1;
		end
	end
	
endmodule
module ROCounter #(
		parameter 					length = 16
	)(
		input 						clk,
		input 						rst,
		input 						RO0In,
		input 						RO1In,
		output reg [length-1:0] RO0Cnt,
		output reg [length-1:0] RO1Cnt,
		output reg [length-1:0] ClkCnt
	);

	

	always @(posedge clk) begin
		if (rst) begin
			ClkCnt <= {length-1{1'b0}};
		end
		else begin
			ClkCnt <= ClkCnt + 1;
		end
	end


	always @(posedge RO0In) begin
		if (rst) begin
			RO0Cnt <= {length-1{1'b0}};
		end
		else begin
			RO0Cnt <= RO0Cnt + 1;
		end
	end
	

	always @(posedge RO1In) begin
		if (rst) begin
			RO1Cnt <= {length-1{1'b0}};
		end
		else begin
			RO1Cnt <= RO1Cnt + 1;
		end
	end
	
endmodule