data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v:29: Signal definition not found, creating implicitly: \'switch_debounced\'\n                                                                                        : ... Suggested alternative: \'switch_debounced_d\'\n    switch_debounced_d <= switch_debounced;   \n                          ^~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v:46: Signal definition not found, creating implicitly: \'ten_ms\'\n      .sample_en(ten_ms),      \n                 ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v:56: Signal definition not found, creating implicitly: \'ten_us\'\n                                                                                        : ... Suggested alternative: \'ten_ms\'\n        .timer_pulse(ten_us));\n                     ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_blinky_exercise.v:18: Operator EQ expects 25 bits on the RHS, but RHS\'s REPLICATE generates 24 bits.\n                                                                                     : ... In instance fpga_top\n       if (counter == ( {blink_cnt, 20\'h42400} )) begin    \n                   ^~\n%Error: Exiting due to 4 warning(s)\n'
module WF_switch_debounce (
     input  wire clk,
     input  wire sample_en,
     input  wire switch_in,
     output reg  switch_out,
     output wire switch_pushed,
     output wire switch_released);

     reg  [2:0] switch;
     reg        switch_out_d;

     always @ (posedge clk)
       begin
         if ( sample_en)
           switch <= { switch[1:0],switch_in };

         if (switch == 3'b000)
           switch_out <= 1'b0;
         else if (switch == 3'b111)
           switch_out <= 1'b1;

         switch_out_d <= switch_out;
       end

     assign switch_pushed   = ~switch_out &&  switch_out_d;
     assign switch_released =  switch_out && ~switch_out_d;

   endmodule
module WF_switch_debounce (
     input  wire clk,
     input  wire sample_en,
     input  wire switch_in,
     output reg  switch_out,
     output wire switch_pushed,
     output wire switch_released);


     reg  [2:0] switch;
     reg        switch_out_d;

     always @ (posedge clk)
       begin
         if ( sample_en)
           switch <= { switch[1:0],switch_in };

         if (switch == 3'b000)
           switch_out <= 1'b0;
         else if (switch == 3'b111)
           switch_out <= 1'b1;

         switch_out_d <= switch_out;
       end

     assign switch_pushed   = ~switch_out &&  switch_out_d;
     assign switch_released =  switch_out && ~switch_out_d;

   endmodule