data/full_repos/permissive/208113388/afu/lpc/lpc_respfifo.v
 line:74: before: "("
data/verilator_xmls/c0d090ac-9351-4d67-8a8d-826d3559abcb.xml
module lpc_respfifo #(parameter integer WIDTH = 550) (
    input              clock
  , input              reset


  , input  [WIDTH-1:0] resp_in
  , input              resp_in_valid
  , output [4:0]       resp_buffers_available


  , input              resp_sent
  , output [WIDTH-1:0] resp_out
  , output             resp_out_valid
 

  , output             fifo_overflow
) ;






reg [WIDTH-1:0] respfifo [15:0];


reg       [3:0] wrptr;
reg       [3:0] rdptr;
reg      [15:0] respfifo_val;


always @(posedge(clock))
  begin
    if (reset == 1'b1) 
      wrptr <= 4'b0000;
    else if (resp_in_valid == 1'b1 && wrptr != 4'b1111)   
      wrptr <= wrptr + 4'b0001;
    else if (resp_in_valid == 1'b1 && wrptr == 4'b1111)   
      wrptr <= 4'b0000;
    else
      wrptr <= wrptr;
  end


always @(posedge(clock))
  begin
    if (reset == 1'b1)
      rdptr <= 4'b0000;
    else if (resp_sent == 1'b1 && rdptr != 4'b1111)
      rdptr <= rdptr + 4'b0001;
    else if (resp_sent == 1'b1 && rdptr == 4'b1111)
      rdptr <= 4'b0000;
    else
      rdptr <= rdptr;
  end


always @(posedge(clock))
  begin 
    if (reset == 1'b1)  
      respfifo_val <= 16'h0000;
    else if (resp_in_valid == 1'b1 && resp_sent == 1'b0)  
      respfifo_val <= respfifo_val | (16'h0001 << wrptr);
    else if (resp_in_valid == 1'b0 && resp_sent == 1'b1)
      respfifo_val <= respfifo_val & ~(16'h0001 << rdptr);
    else if (resp_in_valid == 1'b1 && resp_sent == 1'b1)
      respfifo_val <= (respfifo_val | (16'h0001 << wrptr)) & ~(16'h0001 << rdptr);
    else
      respfifo_val <= respfifo_val;
  end



always @(posedge(clock)) begin
  if (resp_in_valid) respfifo[wrptr] <= resp_in;
end





assign resp_out = (respfifo_val[rdptr] == 1'b1) ? respfifo[rdptr] : {WIDTH{1'b0}};  


assign resp_out_valid = respfifo_val[rdptr];  



assign fifo_overflow   = (resp_in_valid == 1'b1 && respfifo_val == 16'hFFFF) ? 1'b1 : 1'b0;




reg [4:0] resp_buffers_used;
always @(*)
  if (respfifo_val == 16'h0000)
    resp_buffers_used = 5'b00000; 
  else if (wrptr > rdptr)
    resp_buffers_used = {1'b0,wrptr} - {1'b0,rdptr};
  else if (wrptr < rdptr)
    resp_buffers_used = (5'b10000 + {1'b0,wrptr}) - {1'b0,rdptr};   
  else
    resp_buffers_used = 5'b10000; 
assign resp_buffers_available = 5'b10000 - resp_buffers_used;

endmodule
module lpc_respfifo #(parameter integer WIDTH = 550) (
    input              clock
  , input              reset


  , input  [WIDTH-1:0] resp_in
  , input              resp_in_valid
  , output [4:0]       resp_buffers_available


  , input              resp_sent
  , output [WIDTH-1:0] resp_out
  , output             resp_out_valid
 

  , output             fifo_overflow
) ;







reg [WIDTH-1:0] respfifo [15:0];


reg       [3:0] wrptr;
reg       [3:0] rdptr;
reg      [15:0] respfifo_val;


always @(posedge(clock))
  begin
    if (reset == 1'b1) 
      wrptr <= 4'b0000;
    else if (resp_in_valid == 1'b1 && wrptr != 4'b1111)   
      wrptr <= wrptr + 4'b0001;
    else if (resp_in_valid == 1'b1 && wrptr == 4'b1111)   
      wrptr <= 4'b0000;
    else
      wrptr <= wrptr;
  end


always @(posedge(clock))
  begin
    if (reset == 1'b1)
      rdptr <= 4'b0000;
    else if (resp_sent == 1'b1 && rdptr != 4'b1111)
      rdptr <= rdptr + 4'b0001;
    else if (resp_sent == 1'b1 && rdptr == 4'b1111)
      rdptr <= 4'b0000;
    else
      rdptr <= rdptr;
  end


always @(posedge(clock))
  begin 
    if (reset == 1'b1)  
      respfifo_val <= 16'h0000;
    else if (resp_in_valid == 1'b1 && resp_sent == 1'b0)  
      respfifo_val <= respfifo_val | (16'h0001 << wrptr);
    else if (resp_in_valid == 1'b0 && resp_sent == 1'b1)
      respfifo_val <= respfifo_val & ~(16'h0001 << rdptr);
    else if (resp_in_valid == 1'b1 && resp_sent == 1'b1)
      respfifo_val <= (respfifo_val | (16'h0001 << wrptr)) & ~(16'h0001 << rdptr);
    else
      respfifo_val <= respfifo_val;
  end



always @(posedge(clock)) begin
  if (resp_in_valid) respfifo[wrptr] <= resp_in;
end





assign resp_out = (respfifo_val[rdptr] == 1'b1) ? respfifo[rdptr] : {WIDTH{1'b0}};  


assign resp_out_valid = respfifo_val[rdptr];  



assign fifo_overflow   = (resp_in_valid == 1'b1 && respfifo_val == 16'hFFFF) ? 1'b1 : 1'b0;




reg [4:0] resp_buffers_used;
always @(*)
  if (respfifo_val == 16'h0000)
    resp_buffers_used = 5'b00000; 
  else if (wrptr > rdptr)
    resp_buffers_used = {1'b0,wrptr} - {1'b0,rdptr};
  else if (wrptr < rdptr)
    resp_buffers_used = (5'b10000 + {1'b0,wrptr}) - {1'b0,rdptr};   
  else
    resp_buffers_used = 5'b10000; 
assign resp_buffers_available = 5'b10000 - resp_buffers_used;

endmodule