data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v
1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                         ^~~~~~\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                               ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                      ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                 ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                            ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                       ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                                  ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                                             ^\n%Error: Exiting due to 8 warning(s)\n'
module digitalClock(
    input CLK100MHZ,
    input [2:0] SW,
    output CA,
    output CB,
    output CC,
    output CD,
    output CE,
    output CF,
    output CG,
    output [7:0] AN,
    output DP
    );
    assign DP=1;
    
    wire [6:0] SEG;
    assign SEG = { CG, CF, CE, CD, CC, CB, CA };
    
    wire [2:0] CP_seg;
    clkdiv div(CLK100MHZ,CP_seg);
    
    wire CP_clock;
    oneMinute min(CLK100MHZ,SW[2:1],CP_clock);
    
    wire CR=SW[0];
    
    wire [3:0] H1_load='b0000;
    wire [3:0] H2_load='b0000;
    wire [3:0] M1_load='b0000;
    wire [3:0] M2_load='b0000;
    wire [3:0] S1_load='b0000;
    wire [3:0] S2_load='b0000;
    
    wire [3:0] H1_display;
    wire [3:0] H2_display;
    wire [3:0] M1_display;
    wire [3:0] M2_display;
    wire [3:0] S1_display;
    wire [3:0] S2_display;
    wire [31:0] display={'b0000,'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};
    
    wire Full_H1=H1_display[1]&H2_display[1]&H2_display[0]&Full_M1&Full_S1;
    wire Full_H2=(H2_display[3]&H2_display[0]&Full_M1&Full_S1)|Full_H1;
    wire Full_M1=M1_display[2]&M1_display[0]&M2_display[3]&M2_display[0]&Full_S1;
    wire Full_M2=M2_display[3]&M2_display[0]&Full_S1;
    wire Full_S1=S1_display[2]&S1_display[0]&S2_display[3]&S2_display[0];
    wire Full_S2=S2_display[3]&S2_display[0];
    
    _74LS163 H1(CP_clock,~(CR|Full_H1),'b1,Full_H2,1,H1_load,H1_display);
    _74LS163 H2(CP_clock,~(CR|Full_H2),'b1,Full_M1,1,H2_load,H2_display);
    _74LS163 M1(CP_clock,~(CR|Full_M1),'b1,Full_M2,1,M1_load,M1_display);
    _74LS163 M2(CP_clock,~(CR|Full_M2),'b1,Full_S1,1,M2_load,M2_display);
    _74LS163 S1(CP_clock,~(CR|Full_S1),'b1,Full_S2,1,S1_load,S1_display);
    _74LS163 S2(CP_clock,~(CR|Full_S2),'b1,1,1,S2_load,S2_display);
    
    BCD_7Seg seg(display,CP_seg,SEG,AN);
    
endmodule
module digitalClock(
    input CLK100MHZ,
    input [2:0] SW,
    output CA,
    output CB,
    output CC,
    output CD,
    output CE,
    output CF,
    output CG,
    output [7:0] AN,
    output DP
    );

    assign DP=1;
    
    wire [6:0] SEG;
    assign SEG = { CG, CF, CE, CD, CC, CB, CA };
    
    wire [2:0] CP_seg;
    clkdiv div(CLK100MHZ,CP_seg);
    
    wire CP_clock;
    oneMinute min(CLK100MHZ,SW[2:1],CP_clock);
    
    wire CR=SW[0];
    
    wire [3:0] H1_load='b0000;
    wire [3:0] H2_load='b0000;
    wire [3:0] M1_load='b0000;
    wire [3:0] M2_load='b0000;
    wire [3:0] S1_load='b0000;
    wire [3:0] S2_load='b0000;
    
    wire [3:0] H1_display;
    wire [3:0] H2_display;
    wire [3:0] M1_display;
    wire [3:0] M2_display;
    wire [3:0] S1_display;
    wire [3:0] S2_display;
    wire [31:0] display={'b0000,'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};
    
    wire Full_H1=H1_display[1]&H2_display[1]&H2_display[0]&Full_M1&Full_S1;
    wire Full_H2=(H2_display[3]&H2_display[0]&Full_M1&Full_S1)|Full_H1;
    wire Full_M1=M1_display[2]&M1_display[0]&M2_display[3]&M2_display[0]&Full_S1;
    wire Full_M2=M2_display[3]&M2_display[0]&Full_S1;
    wire Full_S1=S1_display[2]&S1_display[0]&S2_display[3]&S2_display[0];
    wire Full_S2=S2_display[3]&S2_display[0];
    
    _74LS163 H1(CP_clock,~(CR|Full_H1),'b1,Full_H2,1,H1_load,H1_display);
    _74LS163 H2(CP_clock,~(CR|Full_H2),'b1,Full_M1,1,H2_load,H2_display);
    _74LS163 M1(CP_clock,~(CR|Full_M1),'b1,Full_M2,1,M1_load,M1_display);
    _74LS163 M2(CP_clock,~(CR|Full_M2),'b1,Full_S1,1,M2_load,M2_display);
    _74LS163 S1(CP_clock,~(CR|Full_S1),'b1,Full_S2,1,S1_load,S1_display);
    _74LS163 S2(CP_clock,~(CR|Full_S2),'b1,1,1,S2_load,S2_display);
    
    BCD_7Seg seg(display,CP_seg,SEG,AN);
    
endmodule