data/full_repos/permissive/154123726/3rdParty/simd/butterfly3r.v
1: b'%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/butterfly3r.v:32: Operator SUB expects 17 bits on the LHS, but LHS\'s VARREF \'ai\' generates 15 bits.\n                                                                                   : ... In instance butterfly3r\n assign buffer = ((ai-bi) << 6);\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/butterfly3r.v:32: Operator SUB expects 17 bits on the RHS, but RHS\'s VARREF \'bi\' generates 15 bits.\n                                                                                   : ... In instance butterfly3r\n assign buffer = ((ai-bi) << 6);\n                     ^\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/butterfly3r.v:33: Cannot find file containing module: \'do_reduce\'\n do_reduce bufReduce(buffer, bo);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/do_reduce\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/do_reduce.v\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/do_reduce.sv\n             do_reduce\n             do_reduce.v\n             do_reduce.sv\n             obj_dir/do_reduce\n             obj_dir/do_reduce.v\n             obj_dir/do_reduce.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module butterfly3r(ai, 
				   bi, 
				   ao, 
				   bo
				   );

	input signed [14:0] ai;
	input signed [14:0] bi;	
	

	output signed [14:0] ao;
	output signed [14:0] bo;
	wire signed [16:0] buffer;	
	assign ao = ai + bi;
	assign buffer = ((ai-bi) << 6);
	do_reduce bufReduce(buffer, bo);
endmodule
module butterfly3r(ai, 
				   bi, 
				   ao, 
				   bo
				   );


	input signed [14:0] ai;
	input signed [14:0] bi;	
	

	output signed [14:0] ao;
	output signed [14:0] bo;
	wire signed [16:0] buffer;	
	assign ao = ai + bi;
	assign buffer = ((ai-bi) << 6);
	do_reduce bufReduce(buffer, bo);
endmodule