data/full_repos/permissive/173943530/jt_gng/modules/jt12/jt49/hdl/filter/jt49_dcrm2.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/173943530/jt_gng/modules/jt12/jt49/hdl/filter/jt49_dcrm2.v:58: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'pre_dout\' generates 9 bits.\n                                                                                                        : ... In instance jt49_dcrm2\n        integ <= integ + pre_dout;  \n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module jt49_dcrm2 #(parameter sw=8) (
    input                clk,
    input                cen,
    input                rst,
    input         [sw-1:0]  din,
    output signed [sw-1:0]  dout
);

localparam dw=10;

reg  signed [sw+dw:0] integ, exact, error;


reg  signed [sw:0] pre_dout;

reg signed [sw:0] q;

always @(*) begin
    exact = integ+error;
    q = exact[sw+dw:dw];
    pre_dout  = { 1'b0, din } - q;


end

assign dout = pre_dout[sw-1:0];

always @(posedge clk)
    if( rst ) begin
        integ <= {sw+dw+1{1'b0}};
        error <= {sw+dw+1{1'b0}};
    end else if( cen ) begin
        integ <= integ + pre_dout;
        error <= exact-{q, {dw{1'b0}}};
    end

endmodule
module jt49_dcrm2 #(parameter sw=8) (
    input                clk,
    input                cen,
    input                rst,
    input         [sw-1:0]  din,
    output signed [sw-1:0]  dout
);


localparam dw=10;

reg  signed [sw+dw:0] integ, exact, error;


reg  signed [sw:0] pre_dout;

reg signed [sw:0] q;

always @(*) begin
    exact = integ+error;
    q = exact[sw+dw:dw];
    pre_dout  = { 1'b0, din } - q;


end

assign dout = pre_dout[sw-1:0];

always @(posedge clk)
    if( rst ) begin
        integ <= {sw+dw+1{1'b0}};
        error <= {sw+dw+1{1'b0}};
    end else if( cen ) begin
        integ <= integ + pre_dout;
        error <= exact-{q, {dw{1'b0}}};
    end

endmodule