data/full_repos/permissive/189158922/verilog_src/register_file.v
data/verilator_xmls/11cb1d68-240a-4c26-b001-6272b6f2cf03.xml
module top(full_rst, height, width, allowed_cycles, full_clk);
  (* src = "register_file.py:38" *)
  reg [23:0] \$next\allowed_cycles ;
  (* src = "register_file.py:52" *)
  reg [23:0] \$next\allowed_cycles_reg ;
  (* src = "clk_domains.py:5" *)
  reg \$next\clk ;
  (* src = "register_file.py:36" *)
  reg [15:0] \$next\height ;
  (* src = "register_file.py:51" *)
  reg [15:0] \$next\height_reg ;
  (* src = "register_file.py:37" *)
  reg [15:0] \$next\width ;
  (* src = "register_file.py:50" *)
  reg [15:0] \$next\width_reg ;
  (* src = "register_file.py:38" *)
  output [23:0] allowed_cycles;
  (* init = 24'h000000 *)
  (* src = "register_file.py:52" *)
  reg [23:0] allowed_cycles_reg = 24'h000000;
  (* src = "clk_domains.py:5" *)
  wire clk;
  (* src = "clk_domains.py:4" *)
  input full_clk;
  (* src = "clk_domains.py:4" *)
  input full_rst;
  (* src = "register_file.py:36" *)
  output [15:0] height;
  (* init = 16'h0000 *)
  (* src = "register_file.py:51" *)
  reg [15:0] height_reg = 16'h0000;
  (* src = "register_file.py:37" *)
  output [15:0] width;
  (* init = 16'h0000 *)
  (* src = "register_file.py:50" *)
  reg [15:0] width_reg = 16'h0000;
  always @(posedge full_clk)
      allowed_cycles_reg <= \$next\allowed_cycles_reg ;
  always @(posedge full_clk)
      height_reg <= \$next\height_reg ;
  always @(posedge full_clk)
      width_reg <= \$next\width_reg ;
  always @* begin
    \$next\clk  = 1'h0;
    \$next\clk  = full_clk;
  end
  always @* begin
    \$next\width_reg  = width_reg;
    \$next\width_reg  = 16'h1000;
    casez (full_rst)
      1'h1:
          \$next\width_reg  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\height_reg  = height_reg;
    \$next\height_reg  = 16'h0c00;
    casez (full_rst)
      1'h1:
          \$next\height_reg  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\allowed_cycles_reg  = allowed_cycles_reg;
    \$next\allowed_cycles_reg  = 24'h65b710;
    casez (full_rst)
      1'h1:
          \$next\allowed_cycles_reg  = 24'h000000;
    endcase
  end
  always @* begin
    \$next\width  = 16'h0000;
    \$next\width  = width_reg;
  end
  always @* begin
    \$next\height  = 16'h0000;
    \$next\height  = height_reg;
  end
  always @* begin
    \$next\allowed_cycles  = 24'h000000;
    \$next\allowed_cycles  = allowed_cycles_reg;
  end
  assign allowed_cycles = \$next\allowed_cycles ;
  assign height = \$next\height ;
  assign width = \$next\width ;
  assign clk = \$next\clk ;
endmodule
module top(full_rst, height, width, allowed_cycles, full_clk);

  (* src = "register_file.py:38" *)
  reg [23:0] \$next\allowed_cycles ;
  (* src = "register_file.py:52" *)
  reg [23:0] \$next\allowed_cycles_reg ;
  (* src = "clk_domains.py:5" *)
  reg \$next\clk ;
  (* src = "register_file.py:36" *)
  reg [15:0] \$next\height ;
  (* src = "register_file.py:51" *)
  reg [15:0] \$next\height_reg ;
  (* src = "register_file.py:37" *)
  reg [15:0] \$next\width ;
  (* src = "register_file.py:50" *)
  reg [15:0] \$next\width_reg ;
  (* src = "register_file.py:38" *)
  output [23:0] allowed_cycles;
  (* init = 24'h000000 *)
  (* src = "register_file.py:52" *)
  reg [23:0] allowed_cycles_reg = 24'h000000;
  (* src = "clk_domains.py:5" *)
  wire clk;
  (* src = "clk_domains.py:4" *)
  input full_clk;
  (* src = "clk_domains.py:4" *)
  input full_rst;
  (* src = "register_file.py:36" *)
  output [15:0] height;
  (* init = 16'h0000 *)
  (* src = "register_file.py:51" *)
  reg [15:0] height_reg = 16'h0000;
  (* src = "register_file.py:37" *)
  output [15:0] width;
  (* init = 16'h0000 *)
  (* src = "register_file.py:50" *)
  reg [15:0] width_reg = 16'h0000;
  always @(posedge full_clk)
      allowed_cycles_reg <= \$next\allowed_cycles_reg ;
  always @(posedge full_clk)
      height_reg <= \$next\height_reg ;
  always @(posedge full_clk)
      width_reg <= \$next\width_reg ;
  always @* begin
    \$next\clk  = 1'h0;
    \$next\clk  = full_clk;
  end
  always @* begin
    \$next\width_reg  = width_reg;
    \$next\width_reg  = 16'h1000;
    casez (full_rst)
      1'h1:
          \$next\width_reg  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\height_reg  = height_reg;
    \$next\height_reg  = 16'h0c00;
    casez (full_rst)
      1'h1:
          \$next\height_reg  = 16'h0000;
    endcase
  end
  always @* begin
    \$next\allowed_cycles_reg  = allowed_cycles_reg;
    \$next\allowed_cycles_reg  = 24'h65b710;
    casez (full_rst)
      1'h1:
          \$next\allowed_cycles_reg  = 24'h000000;
    endcase
  end
  always @* begin
    \$next\width  = 16'h0000;
    \$next\width  = width_reg;
  end
  always @* begin
    \$next\height  = 16'h0000;
    \$next\height  = height_reg;
  end
  always @* begin
    \$next\allowed_cycles  = 24'h000000;
    \$next\allowed_cycles  = allowed_cycles_reg;
  end
  assign allowed_cycles = \$next\allowed_cycles ;
  assign height = \$next\height ;
  assign width = \$next\width ;
  assign clk = \$next\clk ;
endmodule