data/full_repos/permissive/105152503/core/fifo_test.v
 line:92: before: "$"
1: b'%Error: data/full_repos/permissive/105152503/core/fifo_test.v:6: Cannot find include file: fifo.v\n`include "fifo.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105152503/core,data/full_repos/permissive/105152503/fifo.v\n             data/full_repos/permissive/105152503/core,data/full_repos/permissive/105152503/fifo.v.v\n             data/full_repos/permissive/105152503/core,data/full_repos/permissive/105152503/fifo.v.sv\n             fifo.v\n             fifo.v.v\n             fifo.v.sv\n             obj_dir/fifo.v\n             obj_dir/fifo.v.v\n             obj_dir/fifo.v.sv\n%Error: data/full_repos/permissive/105152503/core/fifo_test.v:17: Unsupported or unknown PLI call: $monitor\n  $monitor("%4g %4x %1b %1b %1b %1b %3x %3x %3x", $time, clk, full, empty, wr_en, rd_en, idata, odata, omem);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #10    rst= 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #20    wr_en= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #30    wr_en= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #100   rd_en= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #140   rd_en= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #148   rd_en= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #149   rd_en= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #200   wr_en= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #200   rd_en= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #1000  $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk=~ clk;\n  ^\n%Error: Exiting due to 2 error(s), 11 warning(s)\n'
module uart_test();
	
	reg clk, rst, wr_en, rd_en;
	reg  [7:0] idata;
	wire [7:0] odata;
	reg  [7:0] omem ;
	wire full, empty;

	initial begin
		$monitor("%4g %4x %1b %1b %1b %1b %3x %3x %3x", $time, clk, full, empty, wr_en, rd_en, idata, odata, omem);
		idata= 0;
		clk  = 1;
		rst  = 1;
		rd_en= 0;
		wr_en= 0;


		#10    rst= 0;
		#20    wr_en= 1;
		#30    wr_en= 0;
		#100   rd_en= 1;
		#140   rd_en= 0;
		#148   rd_en= 1;
		#149   rd_en= 0;


		#200   wr_en= 1;
		#200   rd_en= 1;
		#1000  $finish;
	end

	always begin
		#5 clk=~ clk;
	end

	always @ (posedge clk) begin
		idata<= idata+ 1'b1;
		if(idata> 8'hf) begin
			rd_en<= ~rd_en;
		end
		if(~empty) begin
			omem<= odata;
		end
	end

	fifo #(.WIDTH(8), .NCBIT(7)) f0(
		.rst(rst),
		.clk(clk),
		.idata(idata),
		.odata(odata),
		.next(rd_en),
		.wr_en(wr_en),
		.full(full),
		.empty(empty)
		);
endmodule
module uart_test();

	
	reg clk, rst, wr_en, rd_en;
	reg  [7:0] idata;
	wire [7:0] odata;
	reg  [7:0] omem ;
	wire full, empty;

	initial begin
		$monitor("%4g %4x %1b %1b %1b %1b %3x %3x %3x", $time, clk, full, empty, wr_en, rd_en, idata, odata, omem);
		idata= 0;
		clk  = 1;
		rst  = 1;
		rd_en= 0;
		wr_en= 0;


		#10    rst= 0;
		#20    wr_en= 1;
		#30    wr_en= 0;
		#100   rd_en= 1;
		#140   rd_en= 0;
		#148   rd_en= 1;
		#149   rd_en= 0;


		#200   wr_en= 1;
		#200   rd_en= 1;
		#1000  $finish;
	end

	always begin
		#5 clk=~ clk;
	end

	always @ (posedge clk) begin
		idata<= idata+ 1'b1;
		if(idata> 8'hf) begin
			rd_en<= ~rd_en;
		end
		if(~empty) begin
			omem<= odata;
		end
	end

	fifo #(.WIDTH(8), .NCBIT(7)) f0(
		.rst(rst),
		.clk(clk),
		.idata(idata),
		.odata(odata),
		.next(rd_en),
		.wr_en(wr_en),
		.full(full),
		.empty(empty)
		);
endmodule