data/full_repos/permissive/151548608/MHP2/work/planAhead/MHP2/MHP2.srcs/sources_1/imports/verilog/fsm_7.v
 line:34: before: "="
1: b'%Error: data/full_repos/permissive/151548608/MHP2/work/planAhead/MHP2/MHP2.srcs/sources_1/imports/verilog/fsm_7.v:29: Cannot find file containing module: \'edge_detector_2\'\n  edge_detector_2 start_stop_edge (\n  ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151548608/MHP2/work/planAhead/MHP2/MHP2.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/edge_detector_2\n             data/full_repos/permissive/151548608/MHP2/work/planAhead/MHP2/MHP2.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/edge_detector_2.v\n             data/full_repos/permissive/151548608/MHP2/work/planAhead/MHP2/MHP2.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/edge_detector_2.sv\n             edge_detector_2\n             edge_detector_2.v\n             edge_detector_2.sv\n             obj_dir/edge_detector_2\n             obj_dir/edge_detector_2.v\n             obj_dir/edge_detector_2.sv\n%Warning-WIDTH: data/full_repos/permissive/151548608/MHP2/work/planAhead/MHP2/MHP2.srcs/sources_1/imports/verilog/fsm_7.v:34: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                            : ... In instance f_s_m_7\n  reg [25:0] M_change_state_d, M_change_state_q = 1\'h0;\n                                                  ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/151548608/MHP2/work/planAhead/MHP2/MHP2.srcs/sources_1/imports/verilog/fsm_7.v:229: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                             : ... In instance f_s_m_7\n      M_change_state_q <= 1\'h0;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/151548608/MHP2/work/planAhead/MHP2/MHP2.srcs/sources_1/imports/verilog/fsm_7.v:230: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                             : ... In instance f_s_m_7\n      M_state_q <= 1\'h0;\n                ^~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module f_s_m_7 (
    input clk,
    input rst,
    output reg [3:0] seg_1,
    output reg [3:0] seg_2,
    output reg [3:0] seg_3,
    output reg [3:0] seg_4,
    output reg a,
    output reg b,
    output reg cin,
    input s,
    input cout,
    input start_stop,
    input reset,
    input manual,
    output reg [7:0] testcase
  );
  
  
  
  wire [1-1:0] M_start_stop_edge_out;
  reg [1-1:0] M_start_stop_edge_in;
  edge_detector_2 start_stop_edge (
    .clk(clk),
    .in(M_start_stop_edge_in),
    .out(M_start_stop_edge_out)
  );
  reg [25:0] M_change_state_d, M_change_state_q = 1'h0;
  localparam IDLE_state = 4'd0;
  localparam STATE1_state = 4'd1;
  localparam STATE2_state = 4'd2;
  localparam STATE3_state = 4'd3;
  localparam STATE4_state = 4'd4;
  localparam STATE5_state = 4'd5;
  localparam STATE6_state = 4'd6;
  localparam STATE7_state = 4'd7;
  localparam STATE8_state = 4'd8;
  localparam FAIL_state = 4'd9;
  localparam MANUAL_state = 4'd10;
  localparam DONE_state = 4'd11;
  
  reg [3:0] M_state_d, M_state_q = IDLE_state;
  
  always @* begin
    M_state_d = M_state_q;
    M_change_state_d = M_change_state_q;
    
    seg_1 = 4'h2;
    seg_2 = 4'h2;
    seg_3 = 4'h2;
    seg_4 = 4'h2;
    a = 1'h0;
    b = 1'h0;
    cin = 1'h0;
    testcase = 8'h00;
    M_start_stop_edge_in = M_change_state_q[25+0-:1];
    M_change_state_d = M_change_state_q + 1'h1;
    
    case (M_state_q)
      IDLE_state: begin
        if (start_stop) begin
          M_state_d = STATE1_state;
        end
        if (manual) begin
          M_state_d = MANUAL_state;
        end
      end
      STATE1_state: begin
        a = 1'h0;
        b = 1'h0;
        cin = 1'h0;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h0;
        seg_4 = 4'h0;
        testcase = 8'h00;
        if (M_start_stop_edge_out) begin
          if (s == 1'h0 && cout == 1'h0) begin
            M_state_d = STATE2_state;
          end else begin
            M_state_d = FAIL_state;
          end
        end
      end
      STATE2_state: begin
        a = 1'h0;
        b = 1'h0;
        cin = 1'h1;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h1;
        seg_4 = 4'h0;
        testcase = 8'h01;
        if (M_start_stop_edge_out) begin
          if (s == 1'h1 && cout == 1'h0) begin
            M_state_d = STATE3_state;
          end else begin
            M_state_d = FAIL_state;
          end
        end
      end
      STATE3_state: begin
        a = 1'h0;
        b = 1'h1;
        cin = 1'h0;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h1;
        seg_4 = 4'h0;
        testcase = 8'h02;
        if (s == 1'h1 && cout == 1'h0) begin
          M_state_d = STATE4_state;
        end else begin
          M_state_d = FAIL_state;
        end
      end
      STATE4_state: begin
        a = 1'h0;
        b = 1'h1;
        cin = 1'h1;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h0;
        seg_4 = 4'h1;
        testcase = 8'h03;
        if (M_start_stop_edge_out) begin
          if (s == 1'h0 && cout == 1'h1) begin
            M_state_d = STATE5_state;
          end else begin
            M_state_d = FAIL_state;
          end
        end
      end
      STATE5_state: begin
        a = 1'h1;
        b = 1'h0;
        cin = 1'h0;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h1;
        seg_4 = 4'h0;
        testcase = 8'h04;
        if (M_start_stop_edge_out) begin
          if (s == 1'h1 && cout == 1'h0) begin
            M_state_d = STATE6_state;
          end else begin
            M_state_d = FAIL_state;
          end
        end
      end
      STATE6_state: begin
        a = 1'h1;
        b = 1'h0;
        cin = 1'h1;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h0;
        seg_4 = 4'h1;
        testcase = 8'h05;
        if (M_start_stop_edge_out) begin
          if (s == 1'h0 && cout == 1'h1) begin
            M_state_d = STATE7_state;
          end else begin
            M_state_d = FAIL_state;
          end
        end
      end
      STATE7_state: begin
        a = 1'h1;
        b = 1'h1;
        cin = 1'h0;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h0;
        seg_4 = 4'h1;
        testcase = 8'h06;
        if (M_start_stop_edge_out) begin
          if (s == 1'h0 && cout == 1'h1) begin
            M_state_d = STATE8_state;
          end else begin
            M_state_d = FAIL_state;
          end
        end
      end
      STATE8_state: begin
        a = 1'h1;
        b = 1'h1;
        cin = 1'h1;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h1;
        seg_4 = 4'h1;
        testcase = 8'h07;
        if (M_start_stop_edge_out) begin
          if (s == 1'h1 && cout == 1'h1) begin
            M_state_d = DONE_state;
          end
        end
      end
      DONE_state: begin
        seg_1 = 4'h3;
        seg_2 = 4'h4;
        seg_3 = 4'h5;
        seg_4 = 4'h5;
        if (reset) begin
          M_state_d = IDLE_state;
        end
      end
      FAIL_state: begin
        seg_1 = 4'h7;
        seg_2 = 4'h4;
        seg_3 = 4'h8;
        seg_4 = 4'h9;
        if (reset) begin
          M_state_d = IDLE_state;
        end
      end
    endcase
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_change_state_q <= 1'h0;
      M_state_q <= 1'h0;
    end else begin
      M_change_state_q <= M_change_state_d;
      M_state_q <= M_state_d;
    end
  end
  
endmodule
module f_s_m_7 (
    input clk,
    input rst,
    output reg [3:0] seg_1,
    output reg [3:0] seg_2,
    output reg [3:0] seg_3,
    output reg [3:0] seg_4,
    output reg a,
    output reg b,
    output reg cin,
    input s,
    input cout,
    input start_stop,
    input reset,
    input manual,
    output reg [7:0] testcase
  );

  
  
  
  wire [1-1:0] M_start_stop_edge_out;
  reg [1-1:0] M_start_stop_edge_in;
  edge_detector_2 start_stop_edge (
    .clk(clk),
    .in(M_start_stop_edge_in),
    .out(M_start_stop_edge_out)
  );
  reg [25:0] M_change_state_d, M_change_state_q = 1'h0;
  localparam IDLE_state = 4'd0;
  localparam STATE1_state = 4'd1;
  localparam STATE2_state = 4'd2;
  localparam STATE3_state = 4'd3;
  localparam STATE4_state = 4'd4;
  localparam STATE5_state = 4'd5;
  localparam STATE6_state = 4'd6;
  localparam STATE7_state = 4'd7;
  localparam STATE8_state = 4'd8;
  localparam FAIL_state = 4'd9;
  localparam MANUAL_state = 4'd10;
  localparam DONE_state = 4'd11;
  
  reg [3:0] M_state_d, M_state_q = IDLE_state;
  
  always @* begin
    M_state_d = M_state_q;
    M_change_state_d = M_change_state_q;
    
    seg_1 = 4'h2;
    seg_2 = 4'h2;
    seg_3 = 4'h2;
    seg_4 = 4'h2;
    a = 1'h0;
    b = 1'h0;
    cin = 1'h0;
    testcase = 8'h00;
    M_start_stop_edge_in = M_change_state_q[25+0-:1];
    M_change_state_d = M_change_state_q + 1'h1;
    
    case (M_state_q)
      IDLE_state: begin
        if (start_stop) begin
          M_state_d = STATE1_state;
        end
        if (manual) begin
          M_state_d = MANUAL_state;
        end
      end
      STATE1_state: begin
        a = 1'h0;
        b = 1'h0;
        cin = 1'h0;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h0;
        seg_4 = 4'h0;
        testcase = 8'h00;
        if (M_start_stop_edge_out) begin
          if (s == 1'h0 && cout == 1'h0) begin
            M_state_d = STATE2_state;
          end else begin
            M_state_d = FAIL_state;
          end
        end
      end
      STATE2_state: begin
        a = 1'h0;
        b = 1'h0;
        cin = 1'h1;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h1;
        seg_4 = 4'h0;
        testcase = 8'h01;
        if (M_start_stop_edge_out) begin
          if (s == 1'h1 && cout == 1'h0) begin
            M_state_d = STATE3_state;
          end else begin
            M_state_d = FAIL_state;
          end
        end
      end
      STATE3_state: begin
        a = 1'h0;
        b = 1'h1;
        cin = 1'h0;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h1;
        seg_4 = 4'h0;
        testcase = 8'h02;
        if (s == 1'h1 && cout == 1'h0) begin
          M_state_d = STATE4_state;
        end else begin
          M_state_d = FAIL_state;
        end
      end
      STATE4_state: begin
        a = 1'h0;
        b = 1'h1;
        cin = 1'h1;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h0;
        seg_4 = 4'h1;
        testcase = 8'h03;
        if (M_start_stop_edge_out) begin
          if (s == 1'h0 && cout == 1'h1) begin
            M_state_d = STATE5_state;
          end else begin
            M_state_d = FAIL_state;
          end
        end
      end
      STATE5_state: begin
        a = 1'h1;
        b = 1'h0;
        cin = 1'h0;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h1;
        seg_4 = 4'h0;
        testcase = 8'h04;
        if (M_start_stop_edge_out) begin
          if (s == 1'h1 && cout == 1'h0) begin
            M_state_d = STATE6_state;
          end else begin
            M_state_d = FAIL_state;
          end
        end
      end
      STATE6_state: begin
        a = 1'h1;
        b = 1'h0;
        cin = 1'h1;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h0;
        seg_4 = 4'h1;
        testcase = 8'h05;
        if (M_start_stop_edge_out) begin
          if (s == 1'h0 && cout == 1'h1) begin
            M_state_d = STATE7_state;
          end else begin
            M_state_d = FAIL_state;
          end
        end
      end
      STATE7_state: begin
        a = 1'h1;
        b = 1'h1;
        cin = 1'h0;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h0;
        seg_4 = 4'h1;
        testcase = 8'h06;
        if (M_start_stop_edge_out) begin
          if (s == 1'h0 && cout == 1'h1) begin
            M_state_d = STATE8_state;
          end else begin
            M_state_d = FAIL_state;
          end
        end
      end
      STATE8_state: begin
        a = 1'h1;
        b = 1'h1;
        cin = 1'h1;
        seg_1 = 4'h2;
        seg_2 = 4'h2;
        seg_3 = 4'h1;
        seg_4 = 4'h1;
        testcase = 8'h07;
        if (M_start_stop_edge_out) begin
          if (s == 1'h1 && cout == 1'h1) begin
            M_state_d = DONE_state;
          end
        end
      end
      DONE_state: begin
        seg_1 = 4'h3;
        seg_2 = 4'h4;
        seg_3 = 4'h5;
        seg_4 = 4'h5;
        if (reset) begin
          M_state_d = IDLE_state;
        end
      end
      FAIL_state: begin
        seg_1 = 4'h7;
        seg_2 = 4'h4;
        seg_3 = 4'h8;
        seg_4 = 4'h9;
        if (reset) begin
          M_state_d = IDLE_state;
        end
      end
    endcase
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_change_state_q <= 1'h0;
      M_state_q <= 1'h0;
    end else begin
      M_change_state_q <= M_change_state_d;
      M_state_q <= M_state_d;
    end
  end
  
endmodule