data/full_repos/permissive/127519632/top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-LITENDIAN: data/full_repos/permissive/127519632/top.v:3: Little bit endian vector: MSB < LSB of bit range: 0:11\n input [0:11]instrution_bus;\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/127519632/top.v:5: Little bit endian vector: MSB < LSB of bit range: 0:3\n wire [0:3]ram_data_bus_c2r;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/127519632/top.v:6: Little bit endian vector: MSB < LSB of bit range: 0:3\n wire [0:3]ram_data_bus_r2c;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/127519632/top.v:7: Little bit endian vector: MSB < LSB of bit range: 0:7\n wire [0:7]ram_address_bus;\n      ^\n%Error: data/full_repos/permissive/127519632/top.v:12: Cannot find file containing module: \'cpu\'\n cpu U1(\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/cpu\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/cpu.v\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: data/full_repos/permissive/127519632/top.v:22: Cannot find file containing module: \'ram\'\n ram U2(\n ^~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module top(instrution_bus, rst_n, clk);
	input clk, rst_n;
	input [0:11]instrution_bus;

	wire [0:3]ram_data_bus_c2r;
	wire [0:3]ram_data_bus_r2c;
	wire [0:7]ram_address_bus;
	wire ram_RW;
	wire ram_EN;


	cpu U1(
    	ram_RW,
    	ram_EN,
    	ram_address_bus,
    	ram_data_bus_c2r,
    	ram_data_bus_r2c,
    	instrution_bus,
    	rst_n,
    	clk);

	ram U2(
		ram_data_bus_r2c,
		ram_data_bus_c2r,
		ram_address_bus,
		ram_RW,
		ram_EN,
		rst_n,
		clk);
endmodule
module top(instrution_bus, rst_n, clk);

	input clk, rst_n;
	input [0:11]instrution_bus;

	wire [0:3]ram_data_bus_c2r;
	wire [0:3]ram_data_bus_r2c;
	wire [0:7]ram_address_bus;
	wire ram_RW;
	wire ram_EN;


	cpu U1(
    	ram_RW,
    	ram_EN,
    	ram_address_bus,
    	ram_data_bus_c2r,
    	ram_data_bus_r2c,
    	instrution_bus,
    	rst_n,
    	clk);

	ram U2(
		ram_data_bus_r2c,
		ram_data_bus_c2r,
		ram_address_bus,
		ram_RW,
		ram_EN,
		rst_n,
		clk);
endmodule