data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v
 line:267: before: ";"
1: b'%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:312: Unsupported or unknown PLI call: $timeformat\n   $timeformat (-9,3, "ns", 1);\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:448: syntax error, unexpected \'!\', expecting TYPE-IDENTIFIER\n always @( !ceb or web or oeb or ubb or lbb or zzb or async_addr) begin\n           ^\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:461: syntax error, unexpected $display\n                $display("%t Error : tBW violation on UB#/LB# by %t", $realtime, tm_tbw + tBW - $realtime);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:465: syntax error, unexpected $display\n                $display("%t Error : tWP violation on WE# by %t", $realtime, tm_web + tWP - $realtime);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:470: syntax error, unexpected $display\n                $display("%t Error : tAW violation on Addr by %t", $realtime, tm_async_addr + tAW - $realtime);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:474: syntax error, unexpected $display\n                $display("%t Error : tDW violation on DQ by %t", $realtime, tm_dq_tdw + tDW - $realtime);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:479: syntax error, unexpected $display\n      $display("%t Error : tWC violation on ADDR", $realtime);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:485: syntax error, unexpected <=, expecting IDENTIFIER\n      2\'b00 : soft_reg <= CR;\n                       ^~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:487: syntax error, unexpected $display\n      default : $display ("%t Error : Async - illegal register select =%h", $realtime, dq_data[1:0]);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:493: syntax error, unexpected $display\n        $display("%t INFO : Async-software access = %d, Register select = %h", $realtime, cfg_reg_st, dq_data[1:0]);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:501: syntax error, unexpected $display\n       $display("%t INFO : Async-Software Access Write Data=%h", $realtime, dq_data);\n       ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:509: syntax error, unexpected \'(\', expecting IDENTIFIER\n      mem_write(async_addr, dq_data, ubb_w, lbb_w);\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:516: syntax error, unexpected $display\n       $display("%t INFO: Async-Write Data Latch  addr =%h, UB#=%h,LB#=%h, Data =%h",$realtime,async_addr, ubb_w,lbb_w, dq_data);\n       ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:520: syntax error, unexpected \'=\', expecting IDENTIFIER\n   state = idle;\n         ^\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:539: syntax error, unexpected $display\n                $display("%t Error : tBW violation on UB#/LB# by %t", $realtime, tm_tbw + tBW - $realtime);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:543: syntax error, unexpected $display\n                $display("%t Error : tWP violation on WE# by %t", $realtime, tm_web + tWP - $realtime);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:547: syntax error, unexpected $display\n                $display("%t Error : tAW violation on Addr by %t", $realtime, tm_async_addr + tAW - $realtime);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:551: syntax error, unexpected $display\n                $display("%t Error : tDW violation on DQ by %t", $realtime, tm_dq_tdw + tDW - $realtime);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:555: syntax error, unexpected $display\n                $display("%t Error : tWC violation on ADDR", $realtime);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:559: syntax error, unexpected $display\n   $display("%t INFO : Async- Configuration Register select =%h, Data= %h", $realtime, async_addr[19:18], async_addr[15:0]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:587: syntax error, unexpected $display\n      $display("%t Error : tPC violation on ADDR bit %d by %t",$realtime, i, tm_page_addr3 + tPC - $realtime);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:591: syntax error, unexpected $display\n      $display("%t Error : tPC violation on ADDR bit %d by %t",$realtime, i, tm_page_addr2 + tPC - $realtime);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:595: syntax error, unexpected $display\n      $display("%t Error : tPC violation on ADDR bit %d by %t",$realtime, i, tm_page_addr1 + tPC - $realtime);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:599: syntax error, unexpected $display\n      $display("%t Error : tPC violation on ADDR bit %d by %t",$realtime, i, tm_page_addr0 + tPC - $realtime);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:639: syntax error, unexpected $display\n        $display("%t INFO : Asynch - Configuration Register Write ", $realtime);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:653: syntax error, unexpected $display\n       $display("%t Error : Async - illegal or unintended Page Mode Read, Page mode is disabled in CR", $realtime);\n       ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:659: syntax error, unexpected \'=\', expecting IDENTIFIER\n       CR :  dq_temp_p = CR_reg;\n                       ^\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:665: syntax error, unexpected $display\n   $display("%t  INFO : Async-software access Read Data =%h", $realtime, dq_temp_p);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:671: syntax error, unexpected \'=\', expecting IDENTIFIER\n   dq_temp_p = mem_read(async_addr, ubb_w, lbb_w);\n             ^\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:676: syntax error, unexpected $display\n   $display("%t INFO : Async - READ ; ADDR = %h, DATA = %h", $realtime, async_addr, dq_temp_p);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:685: syntax error, unexpected $display\n      $display("%t INFO : Async  - software access unlock = %d", $realtime, cfg_reg_st);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:693: syntax error, unexpected <=, expecting IDENTIFIER\n   cfg_reg_st <= 2\'b0;\n              ^~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:700: syntax error, unexpected <=, expecting IDENTIFIER\n      ubb_ww <= #tOH ubb_w;\n             ^~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:708: syntax error, unexpected <=, expecting IDENTIFIER\n        dq_temp <=  #tAPA dq_temp_p;\n                ^~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:712: syntax error, unexpected <=, expecting IDENTIFIER\n        dq_temp <=  #tOE dq_temp_p;\n                ^~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:716: syntax error, unexpected \'=\', expecting IDENTIFIER\n   state = rd;\n         ^\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:781: syntax error, unexpected begin\n        begin\n        ^~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:818: syntax error, unexpected begin\n        begin\n        ^~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:857: syntax error, unexpected begin\n   begin\n   ^~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:869: syntax error, unexpected $display\n               $display("%t ERROR: DPD cannot be enable or disable using Software Access Sequence", $realtime);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:883: syntax error, unexpected <=, expecting IDENTIFIER\n               tm_power_up <= $realtime;\n                           ^~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:891: syntax error, unexpected $display\n                                   $display("%t INFO : DPD [Deep Power Down] EXIT", $realtime);\n                                   ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:895: syntax error, unexpected \'=\', expecting IDENTIFIER\n                              dpd       = opcode[4];\n                                        ^\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:918: syntax error, unexpected $display\n                  $display("%t INFO : Partial Array refresh = FULL Array", $realtime);\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:926: syntax error, unexpected $display\n                                                $display("%t INFO : Partial Array refresh = None of Array", $realtime);\n                                                ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:934: syntax error, unexpected $display\n                  $display("%t INFO : llegal", $realtime);\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:942: syntax error, unexpected $display\n                 1\'b0 : $display("%t INFO : Deep Power Down = DPD Enable", $realtime);\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:944: syntax error, unexpected $display\n                 1\'b1 : $display("%t INFO : Partial Array Refresh Enable[Default] ", $realtime);\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:949: syntax error, unexpected $display\n                                                $display("%t INFO : llegal", $realtime);\n                                                ^~~~~~~~\n%Error: data/full_repos/permissive/129602669/m3designstart/logical/testbench/verilog/IS66WVE409616BLL.v:956: syntax error, unexpected $display\n                                          2\'b00 : $display("%t INFO : TCR + 70C", $realtime);\n                                                  ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
function [no_of_data - 1 : 0] mem_read;

        input [no_of_addr - 1 : 0] addr;

        input                   ub_b, lb_b;

        begin

        if(!lb_b && !ub_b)

                mem_read = { mem_array1[addr], mem_array0[addr]};
        else
           begin

                if(!lb_b && ub_b)

                        mem_read = { 8'bz, mem_array0[addr]};

                else

                if(lb_b && !ub_b)

                        mem_read = { mem_array1[addr], 8'bz};

                else

                        mem_read = {16'bz};

           end

        end

   endfunction
function [no_of_data - 1 : 0] mem_read;


        input [no_of_addr - 1 : 0] addr;

        input                   ub_b, lb_b;

        begin

        if(!lb_b && !ub_b)

                mem_read = { mem_array1[addr], mem_array0[addr]};
        else
           begin

                if(!lb_b && ub_b)

                        mem_read = { 8'bz, mem_array0[addr]};

                else

                if(lb_b && !ub_b)

                        mem_read = { mem_array1[addr], 8'bz};

                else

                        mem_read = {16'bz};

           end

        end

   endfunction