data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v:38: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'sw\' generates 4 bits.\n                                                                                                           : ... In instance mc6800_controller.program_rom_inst\n            ((sw << 12) | 4\'h0): begin\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v:38: Operator OR expects 16 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                                           : ... In instance mc6800_controller.program_rom_inst\n            ((sw << 12) | 4\'h0): begin\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v:41: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'sw\' generates 4 bits.\n                                                                                                           : ... In instance mc6800_controller.program_rom_inst\n            ((sw << 12) | 4\'h1): begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v:41: Operator OR expects 16 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                                           : ... In instance mc6800_controller.program_rom_inst\n            ((sw << 12) | 4\'h1): begin\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v:44: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'sw\' generates 4 bits.\n                                                                                                           : ... In instance mc6800_controller.program_rom_inst\n            ((sw << 12) | 4\'h2): begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/139376178/arty_eth_000.srcs/sources_1/new/mc6800_controller.v:44: Operator OR expects 16 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                                                           : ... In instance mc6800_controller.program_rom_inst\n            ((sw << 12) | 4\'h2): begin\n                        ^\n%Error: Exiting due to 6 warning(s)\n'
module mc6800_controller(
    input CLK100MHZ,
    output [15:0] led,
    input [15:0] address,
    output [7:0] data_from_fpga,
    input [7:0] data_to_fpga,
    output data_from_fpga_enable_n,
    output [1:0] cpu_clock,
    output reset_n,
    output irq_n,
    output nmi_n,
    input write_n,
    input btn,
    input [3:0] sw
    );

    cpu_clock_gen cpu_clock_gen_inst(CLK100MHZ, cpu_clock);

    program_rom program_rom_inst(CLK100MHZ, sw, address, data_from_fpga);
    
    assign reset_n = !btn;
    assign irq_n = 1;
    assign nmi_n = 1;
    assign led = 1 << address[15:12];

    assign data_from_fpga_enable_n = !write_n;    
endmodule
module mc6800_controller(
    input CLK100MHZ,
    output [15:0] led,
    input [15:0] address,
    output [7:0] data_from_fpga,
    input [7:0] data_to_fpga,
    output data_from_fpga_enable_n,
    output [1:0] cpu_clock,
    output reset_n,
    output irq_n,
    output nmi_n,
    input write_n,
    input btn,
    input [3:0] sw
    );


    cpu_clock_gen cpu_clock_gen_inst(CLK100MHZ, cpu_clock);

    program_rom program_rom_inst(CLK100MHZ, sw, address, data_from_fpga);
    
    assign reset_n = !btn;
    assign irq_n = 1;
    assign nmi_n = 1;
    assign led = 1 << address[15:12];

    assign data_from_fpga_enable_n = !write_n;    
endmodule