data/full_repos/permissive/119715647/sim/BlockRandomizer/blockRandomizer_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/BlockRandomizer/blockRandomizer_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/BlockRandomizer/blockRandomizer_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/BlockRandomizer/blockRandomizer_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #100 rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/BlockRandomizer/blockRandomizer_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #100 rst = 1;\n    ^\n%Error: data/full_repos/permissive/119715647/sim/BlockRandomizer/blockRandomizer_tb.v:7: Cannot find file containing module: \'blockRandomizer\'\n  blockRandomizer DUT_blockRandomizer(clk, rst, out);\n  ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119715647/sim/BlockRandomizer,data/full_repos/permissive/119715647/blockRandomizer\n             data/full_repos/permissive/119715647/sim/BlockRandomizer,data/full_repos/permissive/119715647/blockRandomizer.v\n             data/full_repos/permissive/119715647/sim/BlockRandomizer,data/full_repos/permissive/119715647/blockRandomizer.sv\n             blockRandomizer\n             blockRandomizer.v\n             blockRandomizer.sv\n             obj_dir/blockRandomizer\n             obj_dir/blockRandomizer.v\n             obj_dir/blockRandomizer.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module blockRandomizer_tb();
  reg clk, rst;
  wire [4:0] out;

  blockRandomizer DUT_blockRandomizer(clk, rst, out);

  always begin
    #10 clk = 0;
    #10 clk = 1;
  end

  initial begin
    rst = 1;
    #100 rst = 0;
    #100 rst = 1;
  end
endmodule
module blockRandomizer_tb();

  reg clk, rst;
  wire [4:0] out;

  blockRandomizer DUT_blockRandomizer(clk, rst, out);

  always begin
    #10 clk = 0;
    #10 clk = 1;
  end

  initial begin
    rst = 1;
    #100 rst = 0;
    #100 rst = 1;
  end
endmodule