data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp
 line:9: before: ","
1: b"%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:8: Define or directive not defined: '`mname'\nmodule `mname` (\n       ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:8: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule `mname` (\n             ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:31: Unsupported or unknown PLI call: $cfg_bus_width\n  input [`$cfg_bus_width-1`:0] config_data_in;\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:34: syntax error, unexpected output\n  output reg write;\n  ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:35: syntax error, unexpected output\n  output reg [`$cfg_addr_width-1`:0] config_addr_out;\n  ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:35: Unsupported or unknown PLI call: $cfg_addr_width\n  output reg [`$cfg_addr_width-1`:0] config_addr_out;\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:36: Unsupported or unknown PLI call: $cfg_bus_width\n  output reg [`$cfg_bus_width-1`:0] config_data_out;\n               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:38: syntax error, unexpected output\n  output reg reset_out;\n  ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:39: syntax error, unexpected output\n  output reg [3:0] cgra_stalled;\n  ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:40: syntax error, unexpected output\n  output tdo;\n  ^~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:43: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  wire [`$cfg_addr_width-1`:0] config_addr_jtag_out;\n        ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:43: Unsupported or unknown PLI call: $cfg_addr_width\n  wire [`$cfg_addr_width-1`:0] config_addr_jtag_out;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:44: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  wire [`$cfg_bus_width-1`:0] config_data_jtag_out;\n        ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:44: Unsupported or unknown PLI call: $cfg_bus_width\n  wire [`$cfg_bus_width-1`:0] config_data_jtag_out;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:45: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  wire [`$cfg_op_width-1`:0] op;\n        ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:45: Unsupported or unknown PLI call: $cfg_op_width\n  wire [`$cfg_op_width-1`:0] op;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:46: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  reg [`$cfg_bus_width-1`:0] config_data_jtag_in;\n       ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:46: Unsupported or unknown PLI call: $cfg_bus_width\n  reg [`$cfg_bus_width-1`:0] config_data_jtag_in;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:56: syntax error, unexpected $undefined\n`$jtag_obj -> instantiate` (.ifc_trst_n(trst_n),\n^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:56: Unsupported or unknown PLI call: $jtag_obj\n`$jtag_obj -> instantiate` (.ifc_trst_n(trst_n),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:81: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter NOP = `$cfg_op_width`'d0;\n                  ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:81: Unsupported or unknown PLI call: $cfg_op_width\n  parameter NOP = `$cfg_op_width`'d0;\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:82: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter write_config =`$cfg_op_width`'d1;\n                          ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:82: Unsupported or unknown PLI call: $cfg_op_width\n  parameter write_config =`$cfg_op_width`'d1;\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:83: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter read_config = `$cfg_op_width`'d2;\n                          ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:83: Unsupported or unknown PLI call: $cfg_op_width\n  parameter read_config = `$cfg_op_width`'d2;\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:84: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter write_A050 = `$cfg_op_width`'d4;\n                         ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:84: Unsupported or unknown PLI call: $cfg_op_width\n  parameter write_A050 = `$cfg_op_width`'d4;\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:85: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter write_TST = `$cfg_op_width`'d5;\n                        ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:85: Unsupported or unknown PLI call: $cfg_op_width\n  parameter write_TST = `$cfg_op_width`'d5;\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:86: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter read_TST = `$cfg_op_width`'d6;\n                       ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:86: Unsupported or unknown PLI call: $cfg_op_width\n  parameter read_TST = `$cfg_op_width`'d6;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:87: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter global_reset = `$cfg_op_width`'d7;\n                           ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:87: Unsupported or unknown PLI call: $cfg_op_width\n  parameter global_reset = `$cfg_op_width`'d7;\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:88: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter write_stall = `$cfg_op_width`'d8;\n                          ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:88: Unsupported or unknown PLI call: $cfg_op_width\n  parameter write_stall = `$cfg_op_width`'d8;\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:89: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter read_stall = `$cfg_op_width`'d9;\n                         ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:89: Unsupported or unknown PLI call: $cfg_op_width\n  parameter read_stall = `$cfg_op_width`'d9;\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:90: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter advance_clk = `$cfg_op_width`'d10;\n                          ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:90: Unsupported or unknown PLI call: $cfg_op_width\n  parameter advance_clk = `$cfg_op_width`'d10;\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:91: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter read_clk_domain = `$cfg_op_width`'d11;\n                              ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:91: Unsupported or unknown PLI call: $cfg_op_width\n  parameter read_clk_domain = `$cfg_op_width`'d11;\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:92: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter switch_clk = `$cfg_op_width`'d12;\n                         ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:92: Unsupported or unknown PLI call: $cfg_op_width\n  parameter switch_clk = `$cfg_op_width`'d12;\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:93: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter wr_rd_delay_reg = `$cfg_op_width`'d13;\n                              ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:93: Unsupported or unknown PLI call: $cfg_op_width\n  parameter wr_rd_delay_reg = `$cfg_op_width`'d13;\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:94: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter rd_rd_delay_reg = `$cfg_op_width`'d14;\n                              ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:94: Unsupported or unknown PLI call: $cfg_op_width\n  parameter rd_rd_delay_reg = `$cfg_op_width`'d14;\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:95: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER\n  parameter wr_delay_sel_reg = `$cfg_op_width`'d15;\n                               ^\n%Error: data/full_repos/permissive/209644662/hardware/generator_z/global_controller/global_controller.svp:95: Unsupported or unknown PLI call: $cfg_op_width\n  parameter wr_delay_sel_reg = `$cfg_op_width`'d15;\n                                ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module `mname` (
clk_in, reset_in,
config_data_in,
config_addr_out,
config_data_out,
clk_out,
reset_out,
cgra_stalled,
read,
write,
tdi,
tdo,
tms,
tck,
trst_n
);
  
  input  tck;
  input  clk_in;
  input  reset_in;
  input  tdi;
  input  tms;
  input  trst_n;
  input [`$cfg_bus_width-1`:0] config_data_in;

  output reg read;
  output reg write;
  output reg [`$cfg_addr_width-1`:0] config_addr_out;
  output reg [`$cfg_bus_width-1`:0] config_data_out;
  output reg clk_out;
  output reg reset_out;
  output reg [3:0] cgra_stalled;
  output tdo;
  

  wire [`$cfg_addr_width-1`:0] config_addr_jtag_out;
  wire [`$cfg_bus_width-1`:0] config_data_jtag_out;
  wire [`$cfg_op_width-1`:0] op;
  reg [`$cfg_bus_width-1`:0] config_data_jtag_in;
  reg clk;
  reg clk_domain;
  reg sys_clk_activated;


  reg sys_clk_act_sync_1;
  reg sys_clk_act_sync_2;


`$jtag_obj -> instantiate` (.ifc_trst_n(trst_n),
			    .ifc_tck(tck),
			    .ifc_tms(tms),
			    .ifc_tdi(tdi),
			    .ifc_tdo(tdo),
			    .ifc_config_addr_to_gc(config_addr_jtag_out),
			    .ifc_config_data_from_gc(config_data_jtag_in),
			    .ifc_config_data_to_gc(config_data_jtag_out),
			    .ifc_config_op_to_gc(op),
		      	    .clk(clk),
			    .reset(reset_in),
			    .sys_clk_activated(sys_clk_activated),
			    .bsr_tdi(),
			    .bsr_sample(),
			    .bsr_intest(),
			    .bsr_extest(),
			    .bsr_update_en(),
			    .bsr_capture_en(),
		 	    .bsr_shift_dr(),
			    .bsr_tdo()
			    );




  parameter NOP = `$cfg_op_width`'d0;
  parameter write_config =`$cfg_op_width`'d1;
  parameter read_config = `$cfg_op_width`'d2;
  parameter write_A050 = `$cfg_op_width`'d4;
  parameter write_TST = `$cfg_op_width`'d5;
  parameter read_TST = `$cfg_op_width`'d6;
  parameter global_reset = `$cfg_op_width`'d7;
  parameter write_stall = `$cfg_op_width`'d8;
  parameter read_stall = `$cfg_op_width`'d9;
  parameter advance_clk = `$cfg_op_width`'d10;
  parameter read_clk_domain = `$cfg_op_width`'d11;
  parameter switch_clk = `$cfg_op_width`'d12;
  parameter wr_rd_delay_reg = `$cfg_op_width`'d13;
  parameter rd_rd_delay_reg = `$cfg_op_width`'d14;
  parameter wr_delay_sel_reg = `$cfg_op_width`'d15;
  parameter rd_delay_sel_reg = `$cfg_op_width`'d16;
  

  parameter ready = 3'd0;
  parameter reading = 3'd1;
  parameter resetting = 3'd2;
  parameter advancing_clk = 3'd3;
  parameter switching_clk = 3'd4;
  reg [2:0] state;
  

  reg [3:0] stall_restore;
 
  logic all_stalled_tck;
  logic all_stalled_tck_rise;
  logic all_stalled_tck_fall;

  logic all_stalled_sys;
  logic all_stalled_sys_rise;
  logic all_stalled_sys_fall;



  logic [1:0] delay_sel;

  logic clk_switch_request;


  logic clk_switch_request_sync_1_tck;
  logic clk_switch_request_sync_2_tck;

  logic clk_switch_request_sync_1_sys;
  logic clk_switch_request_sync_2_sys;
  
  logic [`$cfg_bus_width-1`:0] TST;
  logic [`$cfg_bus_width-1`:0] counter;
  logic [`$cfg_bus_width-1`:0] rd_delay_reg;
  logic [4:0] clk_switch_counter_tck;
  always_comb begin
    	clk_domain = (sys_clk_activated) ? clk_in : tck;
	all_stalled_tck = delay_sel[1] ? all_stalled_tck_fall : all_stalled_tck_rise;
	all_stalled_sys = delay_sel[0] ? all_stalled_sys_fall : all_stalled_sys_rise;
	clk = ((all_stalled_tck & !sys_clk_activated) | (all_stalled_sys & sys_clk_activated )) ? 0 : clk_domain;
	clk_out = clk;
   	reset_out = (state==resetting) ? 1 : reset_in;
  end

  always @ (posedge tck or posedge reset_in) begin
	if (reset_in==1) begin
		clk_switch_counter_tck <= 5'h1F;
		sys_clk_activated <= 0;
		all_stalled_tck_rise <= 0;
	end
	else if ((clk_switch_request_sync_2_tck != sys_clk_activated) & (clk_switch_counter_tck > 0)) begin
		all_stalled_tck_rise <= 1;
		clk_switch_counter_tck <= clk_switch_counter_tck - 1;	
	end
	else if ((clk_switch_request_sync_2_tck != sys_clk_activated) & clk_switch_counter_tck <= 0 ) begin
		sys_clk_activated <= clk_switch_request;
		clk_switch_counter_tck <= clk_switch_counter_tck-1;
	end
	else if ((clk_switch_request_sync_2_tck == 0) && (sys_clk_activated == 0)) begin
		all_stalled_tck_rise <= 0;
	end	
  end
	


  always @ (negedge tck or posedge reset_in) begin
	if (reset_in==1)
		all_stalled_tck_fall <= 0;
	else
		all_stalled_tck_fall <= all_stalled_tck_rise;
  end
  


  always @ (posedge clk_in or posedge reset_in) begin
	if(reset_in==1) begin
		sys_clk_act_sync_1 <= 0;
		sys_clk_act_sync_2 <= 0;
	end
	else begin	
		sys_clk_act_sync_1 <= sys_clk_activated;
		sys_clk_act_sync_2 <= sys_clk_act_sync_1;
	end
  end  

  always @ (posedge tck or posedge reset_in) begin
	if(reset_in==1) begin
		clk_switch_request_sync_1_tck <= 0;
		clk_switch_request_sync_2_tck <= 0;
	end
	else begin
		clk_switch_request_sync_1_tck <= clk_switch_request;
		clk_switch_request_sync_2_tck <= clk_switch_request_sync_1_tck;
	end	
  end

  always @ (posedge clk_in or posedge reset_in) begin
	if(reset_in==1) begin
		clk_switch_request_sync_1_sys <= 0;
		clk_switch_request_sync_2_sys <= 0;
	end
	else begin
		clk_switch_request_sync_1_sys <= clk_switch_request;
		clk_switch_request_sync_2_sys <= clk_switch_request_sync_1_sys;
	end	
  end


  always @ (posedge clk_in or posedge reset_in) begin 
	if (reset_in==1) begin
		all_stalled_sys_rise <= 1;
	end
	else if (sys_clk_act_sync_2 != clk_switch_request_sync_2_sys) begin
		all_stalled_sys_rise <= 1;
	end
	else if ((sys_clk_act_sync_2 == 1) && (clk_switch_request_sync_2_sys == 1)) begin
		all_stalled_sys_rise <= 0;
	end
  end


  always @ (negedge clk_in or posedge reset_in) begin
	if (reset_in==1)
		all_stalled_sys_fall <= 0;
	else
		all_stalled_sys_fall <= all_stalled_sys_rise;
  end

  always @ (posedge clk or posedge reset_in) begin
    	if (reset_in==1) begin
		cgra_stalled <= 0;
		stall_restore <= 0;
       		clk_switch_request <= 0;
		rd_delay_reg <= 2;
		TST <= 0;
		counter <= 0;
		config_addr_out <= 0;
		config_data_out <= 0;
		config_data_jtag_in <= 0;
		delay_sel <= 2'b0;
		read <= 0;
		write <= 0;
		state <= ready;
    	end

    	else begin
    		if (state==ready) begin
    			case(op)
			NOP: begin
				config_addr_out <= config_addr_out;
				config_data_out <= config_data_out;
				config_data_jtag_in <= config_data_jtag_in;	
				read <= 0;
				write <= 0;
			end
			write_config: begin
				config_addr_out <= config_addr_jtag_out;
				config_data_out <= config_data_jtag_out; 
				read <= 0;
				write <= 1;
			end
			read_config: begin
				config_addr_out <= config_addr_jtag_out;
				config_data_out <= config_data_jtag_out; 
				counter <= rd_delay_reg-1;
				state <= reading;
				read <= 1;
				write <= 0;
			end
			write_A050: begin
				config_data_jtag_in <= `$cfg_bus_width`'hA050;
				read <= 0;
				write <= 0;
			end
			write_TST: begin
				TST <= config_data_jtag_out;
				read <= 0;
				write <= 0;
			end
			read_TST: begin
				config_data_jtag_in <= TST;
				read <= 0;
				write <= 0;
			end
			global_reset: begin
				state <= resetting;
				counter <= (config_data_jtag_out > 0) ? config_data_jtag_out-1 : `$cfg_bus_width`'d19;
				read <= 0;
				write <= 0;
			end
			read_stall: begin
				read <= 0;
				write <= 0;
				config_data_jtag_in <= {`$cfg_bus_width-4`'b0, cgra_stalled};
			end
			write_stall: begin
				cgra_stalled <= config_data_jtag_out[3:0];
				read <= 0;
				write <= 0;
			end			
			advance_clk: begin
				if (config_data_jtag_out > 0) begin
					if (|(cgra_stalled & config_addr_jtag_out[3:0])) begin
						counter <= config_data_jtag_out-1;
						state <= advancing_clk;	
						stall_restore <= cgra_stalled;

						cgra_stalled[`$i`] <= config_addr_jtag_out[`$i`] ? 1'b0 : cgra_stalled[`$i`];

					end
				end
				read <= 0;
				write <= 0;
			end
			read_clk_domain: begin
				read <= 0;
				write <= 0;
				config_data_jtag_in <= {31'b0, sys_clk_activated};
			end
			switch_clk: begin
				if(config_data_jtag_out[0] != clk_switch_request) begin
					clk_switch_request <= config_data_jtag_out[0];
					state <= switching_clk;
					counter <= `$cfg_bus_width`'d20; 
				end
				read <= 0;
				write <= 0;
			end
			wr_rd_delay_reg: begin

				rd_delay_reg <= (config_data_jtag_out > 0) ? config_data_jtag_out : 1;
				read <= 0;
				write <= 0;
			end
			rd_rd_delay_reg: begin
				config_data_jtag_in <= rd_delay_reg;
				read <= 0;
				write <= 0;
			end
			wr_delay_sel_reg: begin
				delay_sel <= config_data_jtag_out[1:0];
				read <= 0;
				write <= 0;
			end
			rd_delay_sel_reg: begin
				config_data_jtag_in <= {`$cfg_bus_width-2`'b0,delay_sel};
				read <= 0;
				write <= 0;
			end
			default: begin
				config_addr_out <= config_addr_out;
				config_data_out <= config_data_out;
				config_data_jtag_in <= config_data_jtag_in;	
				read <= 0;
				write <= 0;
			end
			endcase
		end

		else begin
			config_addr_out <= config_addr_out;
			if (counter > 0) begin
				counter <= counter-1;
			end
			else begin
				state <= ready;
				if (state == reading) begin 
					config_data_jtag_in <= config_data_in;
					read <= 0;
				end
				else if (state == advancing_clk)
					cgra_stalled <= stall_restore;
			end
		end    	
  	end
  end
	

endmodule
module `mname` (
clk_in, reset_in,
config_data_in,
config_addr_out,
config_data_out,
clk_out,
reset_out,
cgra_stalled,
read,
write,
tdi,
tdo,
tms,
tck,
trst_n
);

  
  input  tck;
  input  clk_in;
  input  reset_in;
  input  tdi;
  input  tms;
  input  trst_n;
  input [`$cfg_bus_width-1`:0] config_data_in;

  output reg read;
  output reg write;
  output reg [`$cfg_addr_width-1`:0] config_addr_out;
  output reg [`$cfg_bus_width-1`:0] config_data_out;
  output reg clk_out;
  output reg reset_out;
  output reg [3:0] cgra_stalled;
  output tdo;
  

  wire [`$cfg_addr_width-1`:0] config_addr_jtag_out;
  wire [`$cfg_bus_width-1`:0] config_data_jtag_out;
  wire [`$cfg_op_width-1`:0] op;
  reg [`$cfg_bus_width-1`:0] config_data_jtag_in;
  reg clk;
  reg clk_domain;
  reg sys_clk_activated;


  reg sys_clk_act_sync_1;
  reg sys_clk_act_sync_2;


`$jtag_obj -> instantiate` (.ifc_trst_n(trst_n),
			    .ifc_tck(tck),
			    .ifc_tms(tms),
			    .ifc_tdi(tdi),
			    .ifc_tdo(tdo),
			    .ifc_config_addr_to_gc(config_addr_jtag_out),
			    .ifc_config_data_from_gc(config_data_jtag_in),
			    .ifc_config_data_to_gc(config_data_jtag_out),
			    .ifc_config_op_to_gc(op),
		      	    .clk(clk),
			    .reset(reset_in),
			    .sys_clk_activated(sys_clk_activated),
			    .bsr_tdi(),
			    .bsr_sample(),
			    .bsr_intest(),
			    .bsr_extest(),
			    .bsr_update_en(),
			    .bsr_capture_en(),
		 	    .bsr_shift_dr(),
			    .bsr_tdo()
			    );




  parameter NOP = `$cfg_op_width`'d0;
  parameter write_config =`$cfg_op_width`'d1;
  parameter read_config = `$cfg_op_width`'d2;
  parameter write_A050 = `$cfg_op_width`'d4;
  parameter write_TST = `$cfg_op_width`'d5;
  parameter read_TST = `$cfg_op_width`'d6;
  parameter global_reset = `$cfg_op_width`'d7;
  parameter write_stall = `$cfg_op_width`'d8;
  parameter read_stall = `$cfg_op_width`'d9;
  parameter advance_clk = `$cfg_op_width`'d10;
  parameter read_clk_domain = `$cfg_op_width`'d11;
  parameter switch_clk = `$cfg_op_width`'d12;
  parameter wr_rd_delay_reg = `$cfg_op_width`'d13;
  parameter rd_rd_delay_reg = `$cfg_op_width`'d14;
  parameter wr_delay_sel_reg = `$cfg_op_width`'d15;
  parameter rd_delay_sel_reg = `$cfg_op_width`'d16;
  

  parameter ready = 3'd0;
  parameter reading = 3'd1;
  parameter resetting = 3'd2;
  parameter advancing_clk = 3'd3;
  parameter switching_clk = 3'd4;
  reg [2:0] state;
  

  reg [3:0] stall_restore;
 
  logic all_stalled_tck;
  logic all_stalled_tck_rise;
  logic all_stalled_tck_fall;

  logic all_stalled_sys;
  logic all_stalled_sys_rise;
  logic all_stalled_sys_fall;



  logic [1:0] delay_sel;

  logic clk_switch_request;


  logic clk_switch_request_sync_1_tck;
  logic clk_switch_request_sync_2_tck;

  logic clk_switch_request_sync_1_sys;
  logic clk_switch_request_sync_2_sys;
  
  logic [`$cfg_bus_width-1`:0] TST;
  logic [`$cfg_bus_width-1`:0] counter;
  logic [`$cfg_bus_width-1`:0] rd_delay_reg;
  logic [4:0] clk_switch_counter_tck;
  always_comb begin
    	clk_domain = (sys_clk_activated) ? clk_in : tck;
	all_stalled_tck = delay_sel[1] ? all_stalled_tck_fall : all_stalled_tck_rise;
	all_stalled_sys = delay_sel[0] ? all_stalled_sys_fall : all_stalled_sys_rise;
	clk = ((all_stalled_tck & !sys_clk_activated) | (all_stalled_sys & sys_clk_activated )) ? 0 : clk_domain;
	clk_out = clk;
   	reset_out = (state==resetting) ? 1 : reset_in;
  end

  always @ (posedge tck or posedge reset_in) begin
	if (reset_in==1) begin
		clk_switch_counter_tck <= 5'h1F;
		sys_clk_activated <= 0;
		all_stalled_tck_rise <= 0;
	end
	else if ((clk_switch_request_sync_2_tck != sys_clk_activated) & (clk_switch_counter_tck > 0)) begin
		all_stalled_tck_rise <= 1;
		clk_switch_counter_tck <= clk_switch_counter_tck - 1;	
	end
	else if ((clk_switch_request_sync_2_tck != sys_clk_activated) & clk_switch_counter_tck <= 0 ) begin
		sys_clk_activated <= clk_switch_request;
		clk_switch_counter_tck <= clk_switch_counter_tck-1;
	end
	else if ((clk_switch_request_sync_2_tck == 0) && (sys_clk_activated == 0)) begin
		all_stalled_tck_rise <= 0;
	end	
  end
	


  always @ (negedge tck or posedge reset_in) begin
	if (reset_in==1)
		all_stalled_tck_fall <= 0;
	else
		all_stalled_tck_fall <= all_stalled_tck_rise;
  end
  


  always @ (posedge clk_in or posedge reset_in) begin
	if(reset_in==1) begin
		sys_clk_act_sync_1 <= 0;
		sys_clk_act_sync_2 <= 0;
	end
	else begin	
		sys_clk_act_sync_1 <= sys_clk_activated;
		sys_clk_act_sync_2 <= sys_clk_act_sync_1;
	end
  end  

  always @ (posedge tck or posedge reset_in) begin
	if(reset_in==1) begin
		clk_switch_request_sync_1_tck <= 0;
		clk_switch_request_sync_2_tck <= 0;
	end
	else begin
		clk_switch_request_sync_1_tck <= clk_switch_request;
		clk_switch_request_sync_2_tck <= clk_switch_request_sync_1_tck;
	end	
  end

  always @ (posedge clk_in or posedge reset_in) begin
	if(reset_in==1) begin
		clk_switch_request_sync_1_sys <= 0;
		clk_switch_request_sync_2_sys <= 0;
	end
	else begin
		clk_switch_request_sync_1_sys <= clk_switch_request;
		clk_switch_request_sync_2_sys <= clk_switch_request_sync_1_sys;
	end	
  end


  always @ (posedge clk_in or posedge reset_in) begin 
	if (reset_in==1) begin
		all_stalled_sys_rise <= 1;
	end
	else if (sys_clk_act_sync_2 != clk_switch_request_sync_2_sys) begin
		all_stalled_sys_rise <= 1;
	end
	else if ((sys_clk_act_sync_2 == 1) && (clk_switch_request_sync_2_sys == 1)) begin
		all_stalled_sys_rise <= 0;
	end
  end


  always @ (negedge clk_in or posedge reset_in) begin
	if (reset_in==1)
		all_stalled_sys_fall <= 0;
	else
		all_stalled_sys_fall <= all_stalled_sys_rise;
  end

  always @ (posedge clk or posedge reset_in) begin
    	if (reset_in==1) begin
		cgra_stalled <= 0;
		stall_restore <= 0;
       		clk_switch_request <= 0;
		rd_delay_reg <= 2;
		TST <= 0;
		counter <= 0;
		config_addr_out <= 0;
		config_data_out <= 0;
		config_data_jtag_in <= 0;
		delay_sel <= 2'b0;
		read <= 0;
		write <= 0;
		state <= ready;
    	end

    	else begin
    		if (state==ready) begin
    			case(op)
			NOP: begin
				config_addr_out <= config_addr_out;
				config_data_out <= config_data_out;
				config_data_jtag_in <= config_data_jtag_in;	
				read <= 0;
				write <= 0;
			end
			write_config: begin
				config_addr_out <= config_addr_jtag_out;
				config_data_out <= config_data_jtag_out; 
				read <= 0;
				write <= 1;
			end
			read_config: begin
				config_addr_out <= config_addr_jtag_out;
				config_data_out <= config_data_jtag_out; 
				counter <= rd_delay_reg-1;
				state <= reading;
				read <= 1;
				write <= 0;
			end
			write_A050: begin
				config_data_jtag_in <= `$cfg_bus_width`'hA050;
				read <= 0;
				write <= 0;
			end
			write_TST: begin
				TST <= config_data_jtag_out;
				read <= 0;
				write <= 0;
			end
			read_TST: begin
				config_data_jtag_in <= TST;
				read <= 0;
				write <= 0;
			end
			global_reset: begin
				state <= resetting;
				counter <= (config_data_jtag_out > 0) ? config_data_jtag_out-1 : `$cfg_bus_width`'d19;
				read <= 0;
				write <= 0;
			end
			read_stall: begin
				read <= 0;
				write <= 0;
				config_data_jtag_in <= {`$cfg_bus_width-4`'b0, cgra_stalled};
			end
			write_stall: begin
				cgra_stalled <= config_data_jtag_out[3:0];
				read <= 0;
				write <= 0;
			end			
			advance_clk: begin
				if (config_data_jtag_out > 0) begin
					if (|(cgra_stalled & config_addr_jtag_out[3:0])) begin
						counter <= config_data_jtag_out-1;
						state <= advancing_clk;	
						stall_restore <= cgra_stalled;

						cgra_stalled[`$i`] <= config_addr_jtag_out[`$i`] ? 1'b0 : cgra_stalled[`$i`];

					end
				end
				read <= 0;
				write <= 0;
			end
			read_clk_domain: begin
				read <= 0;
				write <= 0;
				config_data_jtag_in <= {31'b0, sys_clk_activated};
			end
			switch_clk: begin
				if(config_data_jtag_out[0] != clk_switch_request) begin
					clk_switch_request <= config_data_jtag_out[0];
					state <= switching_clk;
					counter <= `$cfg_bus_width`'d20; 
				end
				read <= 0;
				write <= 0;
			end
			wr_rd_delay_reg: begin

				rd_delay_reg <= (config_data_jtag_out > 0) ? config_data_jtag_out : 1;
				read <= 0;
				write <= 0;
			end
			rd_rd_delay_reg: begin
				config_data_jtag_in <= rd_delay_reg;
				read <= 0;
				write <= 0;
			end
			wr_delay_sel_reg: begin
				delay_sel <= config_data_jtag_out[1:0];
				read <= 0;
				write <= 0;
			end
			rd_delay_sel_reg: begin
				config_data_jtag_in <= {`$cfg_bus_width-2`'b0,delay_sel};
				read <= 0;
				write <= 0;
			end
			default: begin
				config_addr_out <= config_addr_out;
				config_data_out <= config_data_out;
				config_data_jtag_in <= config_data_jtag_in;	
				read <= 0;
				write <= 0;
			end
			endcase
		end

		else begin
			config_addr_out <= config_addr_out;
			if (counter > 0) begin
				counter <= counter-1;
			end
			else begin
				state <= ready;
				if (state == reading) begin 
					config_data_jtag_in <= config_data_in;
					read <= 0;
				end
				else if (state == advancing_clk)
					cgra_stalled <= stall_restore;
			end
		end    	
  	end
  end
	

endmodule