data/full_repos/permissive/146618947/compuertas/gate_tester.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/146618947/compuertas/gate_tester.v:24: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("gate_tester_result.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/146618947/compuertas/gate_tester.v:25: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/gate_tester.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/146618947/compuertas/gate_tester.v:34: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/146618947/compuertas/gate_tester.v:46: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/146618947/compuertas/gate_tester.v:49: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/146618947/compuertas/gate_tester.v:52: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/146618947/compuertas/gate_tester.v:63: syntax error, unexpected \'@\'\n        @(posedge clk);  \n        ^\n%Error: data/full_repos/permissive/146618947/compuertas/gate_tester.v:66: syntax error, unexpected \'@\'\n        @(posedge clk);  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/gate_tester.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #18.6 D_flop <= 0;  \n        ^\n%Error: data/full_repos/permissive/146618947/compuertas/gate_tester.v:71: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/gate_tester.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #0.4 D_flop <= 1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/gate_tester.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #24 Reset_L_mux <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/gate_tester.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #24 A_mux <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/gate_tester.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #24 S_mux <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/gate_tester.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #24 Reset_L_mux <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/gate_tester.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #24 Reset_L4 <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/gate_tester.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #24 A4 <= 4\'b0110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/gate_tester.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #24 S4 <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/gate_tester.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #24 Reset_L4 <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/gate_tester.v:115: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk <= ~clk;\n          ^\n%Error: Exiting due to 9 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gate_tester (
                    output reg in_not,
                    output reg in1_nand,
                    output reg in2_nand,
                    output reg D_flop,
                    output reg A_mux,
                    output reg B_mux,
                    output reg S_mux,
                    output reg Reset_L_mux,
                    input      out_not,
                    input      out_nand,
                    input      Q_flop,
                    input      Q_mux,
                    output reg clk,
                    input [3:0] Q4,
                    output reg [3:0] A4,
                    output reg [3:0] B4,
                    output reg Reset_L4,
                    output reg S4
                    );

   initial
     begin
        $dumpfile("gate_tester_result.vcd");
        $dumpvars;
        #100 $finish;
     end

   initial
     begin

        in_not <= 1'b0;

        @(posedge clk);
        in_not <= 1'b1;


     end

   initial
     begin

        in1_nand <= 1'b0;
        in2_nand <= 1'b0;

        @(posedge clk);
        in1_nand <= ~in1_nand;

        @(posedge clk);
        in2_nand <= ~in2_nand;

        @(posedge clk);
        in1_nand <= ~in1_nand;


     end

   initial
     begin

        D_flop <= 1'b0;

        @(posedge clk);
        D_flop <= D_flop;

        @(posedge clk);
        D_flop <= ~D_flop;

        #18.6 D_flop <= 0;

        @(posedge clk);
        #0.4 D_flop <= 1;

     end

   initial
     begin

        A_mux <= 1;
        B_mux <= 0;
        S_mux <= 0;
        Reset_L_mux <= 0;

        #24 Reset_L_mux <= 1;


        #24 A_mux <= 0;
        B_mux <= 1;

        #24 S_mux <= 1;
        #24 Reset_L_mux <= 0;

     end

   initial
     begin

        A4 <= 4'b1010;
        B4 <= 4'b0101;
        S4 <= 0;
        Reset_L4 <= 0;

        #24 Reset_L4 <= 1;


        #24 A4 <= 4'b0110;
        B4 <= 4'b1001;

        #24 S4 <= 1;
        #24 Reset_L4 <= 0;

     end

   initial clk <= 0;
   always #10 clk <= ~clk;

endmodule
module gate_tester (
                    output reg in_not,
                    output reg in1_nand,
                    output reg in2_nand,
                    output reg D_flop,
                    output reg A_mux,
                    output reg B_mux,
                    output reg S_mux,
                    output reg Reset_L_mux,
                    input      out_not,
                    input      out_nand,
                    input      Q_flop,
                    input      Q_mux,
                    output reg clk,
                    input [3:0] Q4,
                    output reg [3:0] A4,
                    output reg [3:0] B4,
                    output reg Reset_L4,
                    output reg S4
                    );


   initial
     begin
        $dumpfile("gate_tester_result.vcd");
        $dumpvars;
        #100 $finish;
     end

   initial
     begin

        in_not <= 1'b0;

        @(posedge clk);
        in_not <= 1'b1;


     end

   initial
     begin

        in1_nand <= 1'b0;
        in2_nand <= 1'b0;

        @(posedge clk);
        in1_nand <= ~in1_nand;

        @(posedge clk);
        in2_nand <= ~in2_nand;

        @(posedge clk);
        in1_nand <= ~in1_nand;


     end

   initial
     begin

        D_flop <= 1'b0;

        @(posedge clk);
        D_flop <= D_flop;

        @(posedge clk);
        D_flop <= ~D_flop;

        #18.6 D_flop <= 0;

        @(posedge clk);
        #0.4 D_flop <= 1;

     end

   initial
     begin

        A_mux <= 1;
        B_mux <= 0;
        S_mux <= 0;
        Reset_L_mux <= 0;

        #24 Reset_L_mux <= 1;


        #24 A_mux <= 0;
        B_mux <= 1;

        #24 S_mux <= 1;
        #24 Reset_L_mux <= 0;

     end

   initial
     begin

        A4 <= 4'b1010;
        B4 <= 4'b0101;
        S4 <= 0;
        Reset_L4 <= 0;

        #24 Reset_L4 <= 1;


        #24 A4 <= 4'b0110;
        B4 <= 4'b1001;

        #24 S4 <= 1;
        #24 Reset_L4 <= 0;

     end

   initial clk <= 0;
   always #10 clk <= ~clk;

endmodule