data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/IR.v
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data/verilator_xmls/8c9c358f-e5d6-4e26-a187-78194d1dc2cf.xml
module IR(
    IRWre, IDataOut, CLK, IRDataOut
);
    input  IRWre;
    input [31:0] IDataOut;
    input CLK;
    output reg [31:0] IRDataOut;
    
   always @(negedge CLK )begin 
        if(IRWre == 1)
            IRDataOut = IDataOut;
        else
            IRDataOut = IRDataOut;
   end 
endmodule
module IR(
    IRWre, IDataOut, CLK, IRDataOut
);

    input  IRWre;
    input [31:0] IDataOut;
    input CLK;
    output reg [31:0] IRDataOut;
    
   always @(negedge CLK )begin 
        if(IRWre == 1)
            IRDataOut = IDataOut;
        else
            IRDataOut = IRDataOut;
   end 
endmodule