data/full_repos/permissive/169373084/RomReader/tests/address_display_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/169373084/RomReader/tests/address_display_testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #200 reset = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169373084/RomReader/tests/address_display_testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #200 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/169373084/RomReader/tests/address_display_testbench.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk <= ~clk;\n        ^\n%Error: data/full_repos/permissive/169373084/RomReader/tests/address_display_testbench.v:37: Cannot find file containing module: \'address_display\'\n    address_display uut (\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169373084/RomReader/tests,data/full_repos/permissive/169373084/address_display\n             data/full_repos/permissive/169373084/RomReader/tests,data/full_repos/permissive/169373084/address_display.v\n             data/full_repos/permissive/169373084/RomReader/tests,data/full_repos/permissive/169373084/address_display.sv\n             address_display\n             address_display.v\n             address_display.sv\n             obj_dir/address_display\n             obj_dir/address_display.v\n             obj_dir/address_display.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module address_display_testbench;


    reg [8:0] address_line;
    reg clk;
    reg reset;


    wire [7:0] sseg_indicator;
    wire [3:0] digits;
    reg [9:0] counter;


    address_display uut (
        .address_line(address_line), 
        .clk(clk), 
        .reset(reset), 
        .sseg_indicator(sseg_indicator), 
        .digits(digits)
    );

    initial begin
          clk = 0;
        reset = 1;
        counter = 0;
          address_line = 0;


        #200 reset = 0;

        #200 reset = 1;
    end
    
    always 
    begin
        #10 clk <= ~clk;
        counter <= counter + 1;
          if(counter == 70)
              address_line <= 1;
          if(counter == 90)
              address_line <= 124;
          if(counter == 110)
              address_line <= 279;
    end
      
endmodule
module address_display_testbench;



    reg [8:0] address_line;
    reg clk;
    reg reset;


    wire [7:0] sseg_indicator;
    wire [3:0] digits;
    reg [9:0] counter;


    address_display uut (
        .address_line(address_line), 
        .clk(clk), 
        .reset(reset), 
        .sseg_indicator(sseg_indicator), 
        .digits(digits)
    );

    initial begin
          clk = 0;
        reset = 1;
        counter = 0;
          address_line = 0;


        #200 reset = 0;

        #200 reset = 1;
    end
    
    always 
    begin
        #10 clk <= ~clk;
        counter <= counter + 1;
          if(counter == 70)
              address_line <= 1;
          if(counter == 90)
              address_line <= 124;
          if(counter == 110)
              address_line <= 279;
    end
      
endmodule