data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:146: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:160: Unsupported: Ignoring delay on this delayed statement.\n   #8;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:162: Unsupported: Ignoring delay on this delayed statement.\n   #8;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:164: Unsupported: Ignoring delay on this delayed statement.\n   #8;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:183: Unsupported: Ignoring delay on this delayed statement.\n  #4;\n  ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'write_clock\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'read_clock\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'sync_read_address\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'channel\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'start_read_address\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'end_read_address\'\n ) fg (\n   ^~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:111: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                       : ... Top module \'sequencer_sync\'\nmodule sequencer_sync #(\n       ^~~~~~~~~~~~~~\n                                                                                       : ... Top module \'function_generator_tb\'\nmodule function_generator_tb;\n       ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:129: Pin not found: \'clock\'\n  .clock(clock),\n   ^~~~~\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module function_generator #(
	parameter DATA_BUS_WIDTH = 8,
	parameter ADDRESS_BUS_DEPTH = 11,
	parameter NUMBER_OF_CHANNELS = 1



) (
	input write_clock,
	input read_clock,
	input reset,
	input sync_read_address,

	input [$clog2(NUMBER_OF_CHANNELS)-1:0] channel,
	input [DATA_BUS_WIDTH-1:0] data_in,
	input [ADDRESS_BUS_DEPTH-1:0] write_address,
	input [ADDRESS_BUS_DEPTH-1:0] start_read_address,
	input [ADDRESS_BUS_DEPTH-1:0] end_read_address,
	input write_enable,
	output [DATA_BUS_WIDTH-1:0] data_out



);
	reg [ADDRESS_BUS_DEPTH-1:0] read_address = 0;
	reg [ADDRESS_BUS_DEPTH-1:0] last_read_address = ADDRESS_BUS_DEPTH*{1'b1};



	genvar ch;
	for (ch=0; ch<NUMBER_OF_CHANNELS; ch=ch+1) begin : chan









		RAM_s6_primitive #(.DATA_WIDTH_A(DATA_BUS_WIDTH), .DATA_WIDTH_B(DATA_BUS_WIDTH)) mem (.reset(reset),
			.write_clock(write_clock), .write_address(write_address), .data_in(data_in), .write_enable(write_enable),
			.read_clock(read_clock), .read_address(read_address), .read_enable(1'b1), .data_out(data_out));
		always @(posedge read_clock) begin
			if (reset || sync_read_address) begin
				read_address <= 0;




			end else begin
				if (read_address==last_read_address) begin
					read_address <= start_read_address;
					last_read_address <= end_read_address - 1'b1;
				end else begin
					read_address <= read_address + 1'b1;
				end



			end
		end
	end



endmodule
module function_generator #(
	parameter DATA_BUS_WIDTH = 8,
	parameter ADDRESS_BUS_DEPTH = 11,
	parameter NUMBER_OF_CHANNELS = 1



) (
	input write_clock,
	input read_clock,
	input reset,
	input sync_read_address,

	input [$clog2(NUMBER_OF_CHANNELS)-1:0] channel,
	input [DATA_BUS_WIDTH-1:0] data_in,
	input [ADDRESS_BUS_DEPTH-1:0] write_address,
	input [ADDRESS_BUS_DEPTH-1:0] start_read_address,
	input [ADDRESS_BUS_DEPTH-1:0] end_read_address,
	input write_enable,
	output [DATA_BUS_WIDTH-1:0] data_out



);

	reg [ADDRESS_BUS_DEPTH-1:0] read_address = 0;
	reg [ADDRESS_BUS_DEPTH-1:0] last_read_address = ADDRESS_BUS_DEPTH*{1'b1};



	genvar ch;
	for (ch=0; ch<NUMBER_OF_CHANNELS; ch=ch+1) begin : chan









		RAM_s6_primitive #(.DATA_WIDTH_A(DATA_BUS_WIDTH), .DATA_WIDTH_B(DATA_BUS_WIDTH)) mem (.reset(reset),
			.write_clock(write_clock), .write_address(write_address), .data_in(data_in), .write_enable(write_enable),
			.read_clock(read_clock), .read_address(read_address), .read_enable(1'b1), .data_out(data_out));
		always @(posedge read_clock) begin
			if (reset || sync_read_address) begin
				read_address <= 0;




			end else begin
				if (read_address==last_read_address) begin
					read_address <= start_read_address;
					last_read_address <= end_read_address - 1'b1;
				end else begin
					read_address <= read_address + 1'b1;
				end



			end
		end
	end



endmodule