data/full_repos/permissive/143278/ivltests/pr1704013.v
data/verilator_xmls/a0251657-2f89-4ca6-861a-ae27d24da7d2.xml
module test(clk, a, b);
input clk;
output a;
input [1:0] b;

reg [1:0] a;

always @(posedge clk) begin
  a <= b;
end
endmodule
module test(clk, a, b);

input clk;
output a;
input [1:0] b;

reg [1:0] a;

always @(posedge clk) begin
  a <= b;
end
endmodule