data/full_repos/permissive/108382235/Pipelined.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC,  SwitchClk_10, reset);\n       ^~~~~~~~~\n                                                                       : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_MEM.M_Dmemory\n  if (MemRead) ReadData=Dmemory[Address[31:2]];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_MEM.M_Dmemory\n  else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n                                                                    : ... In instance Pipelined\n   IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n                ^~\n%Error: Exiting due to 5 warning(s)\n'
module Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC,  SwitchClk_10, reset);
	input SwitchClk_10, reset;

	output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
	output [31:0] CurrentPC;
	
	wire [31:0] ShowNum, PCAddFour, Instruction, ReadData1, ReadData2, Immediate_32, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, WriteData;
	wire [31:0] BranchAddr, ALUResult, ReadData2toEXMEM, MemData;
	wire [27:0] JumpAddr_28; 
	wire PCWrite, BranchMuxSignal, RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc;
	wire IFIDWrite, IDEXFlush1, Zero, IFIDFlush, IDEXFlush2, EXMEMFlush; 
	wire [1:0] ALUOp; 
	wire [4:0] RegDstAddr;
	reg [31:0] IFID_PC, IFID_Instruction, IDEX_JumpAddr, IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32;
	reg [31:0] EXMEM_JumpAddr, EXMEM_BranchAddr, EXMEM_ALUResult, EXMEM_ReadData2, MEMWB_MemData, MEMWB_ALUData;
	reg [1:0] IDEX_WB, EXMEM_WB, MEMWB_WB;
	reg [4:0] IDEX_MEM, IDEX_Rt, IDEX_Rd, IDEX_Rs, EXMEM_MEM, EXMEM_RegDst, MEMWB_RegDst;
	reg [3:0] IDEX_EX;
	reg EXMEM_Zero;
	reg [31:0] CurrentPC;
	
	always @(PCAddFour)
		CurrentPC=PCAddFour-4;
	
	IFStage M_IF(PCAddFour, Instruction, PCWrite, EXMEM_MEM[0], EXMEM_JumpAddr, BranchMuxSignal, EXMEM_BranchAddr, SwitchClk_10, reset);
	IDStage M_ID(JumpAddr_28, RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, ALUOp, ReadData1, ReadData2, Immediate_32, PCWrite, IFIDWrite, IDEXFlush1, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, IFID_Instruction, MEMWB_RegDst, WriteData, MEMWB_WB[1], IDEX_Rt, IDEX_MEM[1], SwitchClk_10, reset);
	EXStage M_EX(BranchAddr, Zero, ALUResult, ReadData2toEXMEM, RegDstAddr, IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32, IDEX_Rt, IDEX_Rd, IDEX_Rs, WriteData, EXMEM_ALUResult, EXMEM_RegDst, EXMEM_WB[1], MEMWB_RegDst, MEMWB_WB[1], IDEX_EX);
	MEMStage M_MEM(IFIDFlush, IDEXFlush2, EXMEMFlush, MemData, BranchMuxSignal, EXMEM_MEM, EXMEM_Zero, EXMEM_ALUResult, EXMEM_ReadData2, WriteData, EXMEM_RegDst, MEMWB_WB[0], MEMWB_RegDst, SwitchClk_10, reset);
	WBStage M_WB(WriteData, MEMWB_MemData, MEMWB_ALUData, MEMWB_WB[0]);
	
	always @(posedge SwitchClk_10, posedge reset) begin
		if (reset==1) begin
			IFID_PC<=0;
			IFID_Instruction<=0;
		end
		else if (IFIDFlush==1) begin
			IFID_PC<=0;
			IFID_Instruction<=0;
		end
		else if (IFIDWrite==0) begin
			IFID_PC<=IFID_PC;
			IFID_Instruction<=IFID_Instruction;
		end
		else begin
			IFID_PC<=PCAddFour;
			IFID_Instruction<=Instruction;
		end
	end
	
	always @(posedge SwitchClk_10, posedge reset) begin
		if (reset==1) begin
			IDEX_JumpAddr<=0; 
			IDEX_PC<=0;
			IDEX_ReadData1<=0;
			IDEX_ReadData2<=0;
			IDEX_Immediate_32<=0;
			IDEX_WB<=0;
			IDEX_MEM<=0; 
			IDEX_Rt<=0; 
			IDEX_Rd<=0; 
			IDEX_Rs<=0;
			IDEX_EX<=0;
		end
		else if (IDEXFlush1==1) begin
			IDEX_JumpAddr<=0; 
			IDEX_PC<=0;
			IDEX_ReadData1<=0;
			IDEX_ReadData2<=0;
			IDEX_Immediate_32<=0;
			IDEX_WB<=0;
			IDEX_MEM<=0; 
			IDEX_Rt<=0; 
			IDEX_Rd<=0; 
			IDEX_Rs<=0;
			IDEX_EX<=0;
		end
		else if (IDEXFlush2==1) begin
			IDEX_JumpAddr<=0; 
			IDEX_PC<=0;
			IDEX_ReadData1<=0;
			IDEX_ReadData2<=0;
			IDEX_Immediate_32<=0;
			IDEX_WB<=0;
			IDEX_MEM<=0; 
			IDEX_Rt<=0; 
			IDEX_Rd<=0; 
			IDEX_Rs<=0;
			IDEX_EX<=0;
		end
		else begin
			IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; 
			IDEX_PC<=IFID_PC;
			IDEX_ReadData1<=ReadData1;
			IDEX_ReadData2<=ReadData2;
			IDEX_Immediate_32<=Immediate_32;
			IDEX_WB<={RegWrite, MemtoReg};
			IDEX_MEM<={Branch, BranchN, MemWrite, MemRead, Jump}; 
			IDEX_Rt<=IFID_Instruction[20:16]; 
			IDEX_Rd<=IFID_Instruction[15:11]; 
			IDEX_Rs<=IFID_Instruction[25:21];
			IDEX_EX<={RegDst, ALUSrc, ALUOp};
		end
	end
	
	always @(posedge SwitchClk_10, posedge reset) begin
		if (reset==1) begin
			EXMEM_JumpAddr<=0; 
			EXMEM_BranchAddr<=0; 
			EXMEM_ALUResult<=0; 
			EXMEM_ReadData2<=0;
			EXMEM_WB<=0;
			EXMEM_MEM<=0; 
			EXMEM_RegDst<=0;
			EXMEM_Zero<=0;
		end
		else if (EXMEMFlush==1) begin
			EXMEM_JumpAddr<=0; 
			EXMEM_BranchAddr<=0; 
			EXMEM_ALUResult<=0; 
			EXMEM_ReadData2<=0;
			EXMEM_WB<=0;
			EXMEM_MEM<=0; 
			EXMEM_RegDst<=0;
			EXMEM_Zero<=0;
		end
		else begin
			EXMEM_JumpAddr<=IDEX_JumpAddr;
			EXMEM_BranchAddr<=BranchAddr; 
			EXMEM_ALUResult<=ALUResult;
			EXMEM_ReadData2<=ReadData2toEXMEM;
			EXMEM_WB<=IDEX_WB;
			EXMEM_MEM<=IDEX_MEM; 
			EXMEM_RegDst<=RegDstAddr;
			EXMEM_Zero<=Zero; 
		end
	end
	
	always @(posedge SwitchClk_10, posedge reset) begin
		if (reset==1) begin
			MEMWB_MemData<=0;
			MEMWB_ALUData<=0;
			MEMWB_WB<=0;
			MEMWB_RegDst<=0;
		end
		else begin
			MEMWB_MemData<=MemData;
			MEMWB_ALUData<=EXMEM_ALUResult;
			MEMWB_WB<=EXMEM_WB;
			MEMWB_RegDst<=EXMEM_RegDst;
		end
	end
	

endmodule
module Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC,  SwitchClk_10, reset);

	input SwitchClk_10, reset;

	output [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
	output [31:0] CurrentPC;
	
	wire [31:0] ShowNum, PCAddFour, Instruction, ReadData1, ReadData2, Immediate_32, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, WriteData;
	wire [31:0] BranchAddr, ALUResult, ReadData2toEXMEM, MemData;
	wire [27:0] JumpAddr_28; 
	wire PCWrite, BranchMuxSignal, RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc;
	wire IFIDWrite, IDEXFlush1, Zero, IFIDFlush, IDEXFlush2, EXMEMFlush; 
	wire [1:0] ALUOp; 
	wire [4:0] RegDstAddr;
	reg [31:0] IFID_PC, IFID_Instruction, IDEX_JumpAddr, IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32;
	reg [31:0] EXMEM_JumpAddr, EXMEM_BranchAddr, EXMEM_ALUResult, EXMEM_ReadData2, MEMWB_MemData, MEMWB_ALUData;
	reg [1:0] IDEX_WB, EXMEM_WB, MEMWB_WB;
	reg [4:0] IDEX_MEM, IDEX_Rt, IDEX_Rd, IDEX_Rs, EXMEM_MEM, EXMEM_RegDst, MEMWB_RegDst;
	reg [3:0] IDEX_EX;
	reg EXMEM_Zero;
	reg [31:0] CurrentPC;
	
	always @(PCAddFour)
		CurrentPC=PCAddFour-4;
	
	IFStage M_IF(PCAddFour, Instruction, PCWrite, EXMEM_MEM[0], EXMEM_JumpAddr, BranchMuxSignal, EXMEM_BranchAddr, SwitchClk_10, reset);
	IDStage M_ID(JumpAddr_28, RegWrite, MemtoReg, Branch, BranchN, MemWrite, MemRead, Jump, RegDst, ALUSrc, ALUOp, ReadData1, ReadData2, Immediate_32, PCWrite, IFIDWrite, IDEXFlush1, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, IFID_Instruction, MEMWB_RegDst, WriteData, MEMWB_WB[1], IDEX_Rt, IDEX_MEM[1], SwitchClk_10, reset);
	EXStage M_EX(BranchAddr, Zero, ALUResult, ReadData2toEXMEM, RegDstAddr, IDEX_PC, IDEX_ReadData1, IDEX_ReadData2, IDEX_Immediate_32, IDEX_Rt, IDEX_Rd, IDEX_Rs, WriteData, EXMEM_ALUResult, EXMEM_RegDst, EXMEM_WB[1], MEMWB_RegDst, MEMWB_WB[1], IDEX_EX);
	MEMStage M_MEM(IFIDFlush, IDEXFlush2, EXMEMFlush, MemData, BranchMuxSignal, EXMEM_MEM, EXMEM_Zero, EXMEM_ALUResult, EXMEM_ReadData2, WriteData, EXMEM_RegDst, MEMWB_WB[0], MEMWB_RegDst, SwitchClk_10, reset);
	WBStage M_WB(WriteData, MEMWB_MemData, MEMWB_ALUData, MEMWB_WB[0]);
	
	always @(posedge SwitchClk_10, posedge reset) begin
		if (reset==1) begin
			IFID_PC<=0;
			IFID_Instruction<=0;
		end
		else if (IFIDFlush==1) begin
			IFID_PC<=0;
			IFID_Instruction<=0;
		end
		else if (IFIDWrite==0) begin
			IFID_PC<=IFID_PC;
			IFID_Instruction<=IFID_Instruction;
		end
		else begin
			IFID_PC<=PCAddFour;
			IFID_Instruction<=Instruction;
		end
	end
	
	always @(posedge SwitchClk_10, posedge reset) begin
		if (reset==1) begin
			IDEX_JumpAddr<=0; 
			IDEX_PC<=0;
			IDEX_ReadData1<=0;
			IDEX_ReadData2<=0;
			IDEX_Immediate_32<=0;
			IDEX_WB<=0;
			IDEX_MEM<=0; 
			IDEX_Rt<=0; 
			IDEX_Rd<=0; 
			IDEX_Rs<=0;
			IDEX_EX<=0;
		end
		else if (IDEXFlush1==1) begin
			IDEX_JumpAddr<=0; 
			IDEX_PC<=0;
			IDEX_ReadData1<=0;
			IDEX_ReadData2<=0;
			IDEX_Immediate_32<=0;
			IDEX_WB<=0;
			IDEX_MEM<=0; 
			IDEX_Rt<=0; 
			IDEX_Rd<=0; 
			IDEX_Rs<=0;
			IDEX_EX<=0;
		end
		else if (IDEXFlush2==1) begin
			IDEX_JumpAddr<=0; 
			IDEX_PC<=0;
			IDEX_ReadData1<=0;
			IDEX_ReadData2<=0;
			IDEX_Immediate_32<=0;
			IDEX_WB<=0;
			IDEX_MEM<=0; 
			IDEX_Rt<=0; 
			IDEX_Rd<=0; 
			IDEX_Rs<=0;
			IDEX_EX<=0;
		end
		else begin
			IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; 
			IDEX_PC<=IFID_PC;
			IDEX_ReadData1<=ReadData1;
			IDEX_ReadData2<=ReadData2;
			IDEX_Immediate_32<=Immediate_32;
			IDEX_WB<={RegWrite, MemtoReg};
			IDEX_MEM<={Branch, BranchN, MemWrite, MemRead, Jump}; 
			IDEX_Rt<=IFID_Instruction[20:16]; 
			IDEX_Rd<=IFID_Instruction[15:11]; 
			IDEX_Rs<=IFID_Instruction[25:21];
			IDEX_EX<={RegDst, ALUSrc, ALUOp};
		end
	end
	
	always @(posedge SwitchClk_10, posedge reset) begin
		if (reset==1) begin
			EXMEM_JumpAddr<=0; 
			EXMEM_BranchAddr<=0; 
			EXMEM_ALUResult<=0; 
			EXMEM_ReadData2<=0;
			EXMEM_WB<=0;
			EXMEM_MEM<=0; 
			EXMEM_RegDst<=0;
			EXMEM_Zero<=0;
		end
		else if (EXMEMFlush==1) begin
			EXMEM_JumpAddr<=0; 
			EXMEM_BranchAddr<=0; 
			EXMEM_ALUResult<=0; 
			EXMEM_ReadData2<=0;
			EXMEM_WB<=0;
			EXMEM_MEM<=0; 
			EXMEM_RegDst<=0;
			EXMEM_Zero<=0;
		end
		else begin
			EXMEM_JumpAddr<=IDEX_JumpAddr;
			EXMEM_BranchAddr<=BranchAddr; 
			EXMEM_ALUResult<=ALUResult;
			EXMEM_ReadData2<=ReadData2toEXMEM;
			EXMEM_WB<=IDEX_WB;
			EXMEM_MEM<=IDEX_MEM; 
			EXMEM_RegDst<=RegDstAddr;
			EXMEM_Zero<=Zero; 
		end
	end
	
	always @(posedge SwitchClk_10, posedge reset) begin
		if (reset==1) begin
			MEMWB_MemData<=0;
			MEMWB_ALUData<=0;
			MEMWB_WB<=0;
			MEMWB_RegDst<=0;
		end
		else begin
			MEMWB_MemData<=MemData;
			MEMWB_ALUData<=EXMEM_ALUResult;
			MEMWB_WB<=EXMEM_WB;
			MEMWB_RegDst<=EXMEM_RegDst;
		end
	end
	

endmodule