data/full_repos/permissive/197263932/main.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/197263932/main.v:18: syntax error, unexpected $end, expecting ',' or ':'\n6   b000000: controls <= 9   b110000010;  \n ^\n%Error: Cannot continue\n"
module controller(
	input logic [5:0] op, funct,
	input logic zero,
	output logic memtoreg, memwrite,
	output logic pcsrc, alusrc,
	output logic regdst, regwrite,
	output logic jump, 
	output logic [2:0] alucontrol);
logic [1:0] aluop;
logic branch;

maindec md(
	op, memtoreg, memwrite, branch,
	alusrc, regdst, regwrite, jump, aluop);
	
aludec ad(funct, aluop, alucontrol);

assign pcsrc = branch & zero;

endmodule
module controller(
	input logic [5:0] op, funct,
	input logic zero,
	output logic memtoreg, memwrite,
	output logic pcsrc, alusrc,
	output logic regdst, regwrite,
	output logic jump, 
	output logic [2:0] alucontrol);

logic [1:0] aluop;
logic branch;

maindec md(
	op, memtoreg, memwrite, branch,
	alusrc, regdst, regwrite, jump, aluop);
	
aludec ad(funct, aluop, alucontrol);

assign pcsrc = branch & zero;

endmodule