data/full_repos/permissive/167962127/amp_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167962127/amp_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10 r_clk = !r_clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167962127/amp_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #100 r_amp <= 16\'h3fff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167962127/amp_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #100 r_amp <= 16\'h0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167962127/amp_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #100 r_amp <= 16\'h7fff;\n    ^\n%Error: data/full_repos/permissive/167962127/amp_tb.v:11: Cannot find file containing module: \'amp\'\n  amp UUT(\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/amp\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/amp.v\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/amp.sv\n             amp\n             amp.v\n             amp.sv\n             obj_dir/amp\n             obj_dir/amp.v\n             obj_dir/amp.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module amp_tb();

  reg r_clk = 1'b0;
  reg [15:0] r_wave = 16'hffff;
  reg [15:0] r_amp = 16'h7fff;

  wire [15:0] w_data;

  amp UUT(
    .i_clk(r_clk),
    .i_wave(r_wave),
    .i_amp(r_amp),
    .o_data(w_data)
  );

  always begin
    #10 r_clk = !r_clk;
  end

  always begin
    #100 r_amp <= 16'h3fff;
    #100 r_amp <= 16'h0000;
    #100 r_amp <= 16'h7fff;
  end

endmodule
module amp_tb();


  reg r_clk = 1'b0;
  reg [15:0] r_wave = 16'hffff;
  reg [15:0] r_amp = 16'h7fff;

  wire [15:0] w_data;

  amp UUT(
    .i_clk(r_clk),
    .i_wave(r_wave),
    .i_amp(r_amp),
    .o_data(w_data)
  );

  always begin
    #10 r_clk = !r_clk;
  end

  always begin
    #100 r_amp <= 16'h3fff;
    #100 r_amp <= 16'h0000;
    #100 r_amp <= 16'h7fff;
  end

endmodule