data/full_repos/permissive/136510272/projects/05_nes/main.v
 line:10: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/05_nes/main.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/05_nes/main.v:10: Unsupported: Ignoring delay on this delayed statement.\ninitial begin clk = 1; #2000 $finish; end\n                       ^\n%Error: data/full_repos/permissive/136510272/projects/05_nes/main.v:11: Unsupported or unknown PLI call: $dumpfile\ninitial begin $dumpfile("nes.vcd"); $dumpvars(0, main); end\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/main.v:11: Unsupported or unknown PLI call: $dumpvars\ninitial begin $dumpfile("nes.vcd"); $dumpvars(0, main); end\n                                    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;



reg         clk;
always #0.5 clk = ~clk;

initial begin clk = 1; #2000 $finish; end
initial begin $dumpfile("nes.vcd"); $dumpvars(0, main); end

wire [4:0]  red;
wire [5:0]  green;
wire [4:0]  blue;
wire        hs;
wire        vs;
wire        rd;
wire [15:0] address;
wire [15:0] ea;

wire [7:0]  dout;
reg  [7:0]  i_data;
reg  [7:0]  spin;

wire        wreq;
wire        ppuclk;
wire        cpuclk;
wire        NMI;
wire [7:0]  DEBUG;
wire [7:0]  DEBUGPPU;
wire [1:0]  KEYS;
wire        reset = 1'b0;
wire        oamw;
wire [7:0]  sar;
reg  [7:0]  srd;
reg         DVRAM;



reg [ 7:0] sram[65536]; 
reg [ 7:0] vram[2048];
reg [ 7:0] crom[8192];
reg [ 7:0]  oam[256]; 


wire VWREN = {DVRAM, vwreq} == 2'b01;

always @(posedge clk) begin


    if (wreq)  sram[ ea ] <= dout;
    i_data  <= sram[ curaddr ];
    

    if (VWREN) vram[ waddr ] <= wdata;
    vin     <= vram[ waddr ];
    fin     <= crom[ waddr ];
    
    if (oamw)  oam[ waddr[7:0] ] <= wdata;
    spin    <= oam[ waddr[7:0] ];
    srd     <= oam[ sar ];

end


wire [15:0] curaddr = dma ? waddr : address;


wire [7:0] din = (curaddr[15:13] == 3'b001) ? ppu_dout : i_data;

initial begin $readmemh("init/ram.hex", sram, 16'h0000); end
initial begin $readmemh("init/rom.hex", sram, 16'h8000); end
initial begin $readmemh("init/oam.hex", oam,  16'h0000); end

initial begin 




    



    
end

always @(posedge clk) DVRAM <= vwreq;




cpu CPU( reset, cpuclk, !dma, address, din, dout, ea, wreq, rd, NMI, DEBUG, KEYS); 




wire [ 7:0] ppu_dout;
wire [10:0] vaddr; wire [7:0] vdata;
wire [12:0] faddr; wire [7:0] fdata;

reg  [ 7:0] vin;
reg  [ 7:0] fin;
wire [ 7:0] wdata;
wire [15:0] waddr;
wire        vwreq;
reg         dvram = 1'b0;

always @(posedge clk) dvram <= vwreq;

ppu PPU(


    clk,    
    reset,
    

    red, green, blue, hs, vs, 
    

    vaddr, vdata,
    vin, vwreq, waddr, wdata,
    

    faddr, fdata, fin,
    
    ppuclk,
    cpuclk,
    

ea, 
dout, 
rd, 
wreq, 
ppu_dout, 
dma,
oamw,
din,
spin,
sar,
srd,
    

    NMI, DEBUGPPU
);

endmodule
module main;




reg         clk;
always #0.5 clk = ~clk;

initial begin clk = 1; #2000 $finish; end
initial begin $dumpfile("nes.vcd"); $dumpvars(0, main); end

wire [4:0]  red;
wire [5:0]  green;
wire [4:0]  blue;
wire        hs;
wire        vs;
wire        rd;
wire [15:0] address;
wire [15:0] ea;

wire [7:0]  dout;
reg  [7:0]  i_data;
reg  [7:0]  spin;

wire        wreq;
wire        ppuclk;
wire        cpuclk;
wire        NMI;
wire [7:0]  DEBUG;
wire [7:0]  DEBUGPPU;
wire [1:0]  KEYS;
wire        reset = 1'b0;
wire        oamw;
wire [7:0]  sar;
reg  [7:0]  srd;
reg         DVRAM;



reg [ 7:0] sram[65536]; 
reg [ 7:0] vram[2048];
reg [ 7:0] crom[8192];
reg [ 7:0]  oam[256]; 


wire VWREN = {DVRAM, vwreq} == 2'b01;

always @(posedge clk) begin


    if (wreq)  sram[ ea ] <= dout;
    i_data  <= sram[ curaddr ];
    

    if (VWREN) vram[ waddr ] <= wdata;
    vin     <= vram[ waddr ];
    fin     <= crom[ waddr ];
    
    if (oamw)  oam[ waddr[7:0] ] <= wdata;
    spin    <= oam[ waddr[7:0] ];
    srd     <= oam[ sar ];

end


wire [15:0] curaddr = dma ? waddr : address;


wire [7:0] din = (curaddr[15:13] == 3'b001) ? ppu_dout : i_data;

initial begin $readmemh("init/ram.hex", sram, 16'h0000); end
initial begin $readmemh("init/rom.hex", sram, 16'h8000); end
initial begin $readmemh("init/oam.hex", oam,  16'h0000); end

initial begin 




    



    
end

always @(posedge clk) DVRAM <= vwreq;




cpu CPU( reset, cpuclk, !dma, address, din, dout, ea, wreq, rd, NMI, DEBUG, KEYS); 




wire [ 7:0] ppu_dout;
wire [10:0] vaddr; wire [7:0] vdata;
wire [12:0] faddr; wire [7:0] fdata;

reg  [ 7:0] vin;
reg  [ 7:0] fin;
wire [ 7:0] wdata;
wire [15:0] waddr;
wire        vwreq;
reg         dvram = 1'b0;

always @(posedge clk) dvram <= vwreq;

ppu PPU(


    clk,    
    reset,
    

    red, green, blue, hs, vs, 
    

    vaddr, vdata,
    vin, vwreq, waddr, wdata,
    

    faddr, fdata, fin,
    
    ppuclk,
    cpuclk,
    

ea, 
dout, 
rd, 
wreq, 
ppu_dout, 
dma,
oamw,
din,
spin,
sar,
srd,
    

    NMI, DEBUGPPU
);

endmodule