data/full_repos/permissive/2084115/projects/zybo_z7_bldc/sim/tb_sin_3phase_tbl/tb_sin_3phase_tbl.v
 line:20: before: "$"
1: b'%Error: data/full_repos/permissive/2084115/projects/zybo_z7_bldc/sim/tb_sin_3phase_tbl/tb_sin_3phase_tbl.v:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_sin_3phase_tbl.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_bldc/sim/tb_sin_3phase_tbl/tb_sin_3phase_tbl.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_sin_3phase_tbl);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/zybo_z7_bldc/sim/tb_sin_3phase_tbl/tb_sin_3phase_tbl.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #100000\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/zybo_z7_bldc/sim/tb_sin_3phase_tbl/tb_sin_3phase_tbl.v:24: Unsupported: Ignoring delay on this delayed statement.\n    initial #(RATE*100) reset = 1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/zybo_z7_bldc/sim/tb_sin_3phase_tbl/tb_sin_3phase_tbl.v:27: Unsupported: Ignoring delay on this delayed statement.\n    always #(RATE/2.0) clk = ~clk;\n           ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sin_3phase_tbl();
    localparam RATE = 1000.0/125.0;
    
    initial begin
        $dumpfile("tb_sin_3phase_tbl.vcd");
        $dumpvars(0, tb_sin_3phase_tbl);
        
    #100000
        $finish;
    end
    
    reg     reset = 1'b1;
    initial #(RATE*100) reset = 1'b0;
    
    reg     clk = 1'b1;
    always #(RATE/2.0) clk = ~clk;
    
    wire            cke = 1;
    
    reg     [9:0]   in_phase = 0;
    
    wire    [11:0]  out_x;
    wire    [11:0]  out_y;
    wire    [11:0]  out_z;
    
    sin_3phase_tbl
        i_sin_3phase_tbl
            (
                .reset      (reset),
                .clk        (clk),
                .cke        (cke),
                
                .in_phase   (in_phase),
                
                .out_x      (out_x),
                .out_y      (out_y),
                .out_z      (out_z)
            );
    
    always @(posedge clk) begin
        if ( reset ) begin
            in_phase <= 0;
        end
        else if ( cke ) begin
            in_phase <= in_phase + 1;
        end
    end
    
    
endmodule
module tb_sin_3phase_tbl();

    localparam RATE = 1000.0/125.0;
    
    initial begin
        $dumpfile("tb_sin_3phase_tbl.vcd");
        $dumpvars(0, tb_sin_3phase_tbl);
        
    #100000
        $finish;
    end
    
    reg     reset = 1'b1;
    initial #(RATE*100) reset = 1'b0;
    
    reg     clk = 1'b1;
    always #(RATE/2.0) clk = ~clk;
    
    wire            cke = 1;
    
    reg     [9:0]   in_phase = 0;
    
    wire    [11:0]  out_x;
    wire    [11:0]  out_y;
    wire    [11:0]  out_z;
    
    sin_3phase_tbl
        i_sin_3phase_tbl
            (
                .reset      (reset),
                .clk        (clk),
                .cke        (cke),
                
                .in_phase   (in_phase),
                
                .out_x      (out_x),
                .out_y      (out_y),
                .out_z      (out_z)
            );
    
    always @(posedge clk) begin
        if ( reset ) begin
            in_phase <= 0;
        end
        else if ( cke ) begin
            in_phase <= in_phase + 1;
        end
    end
    
    
endmodule