data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:3: Cannot find include file: ../../define/global_def.v\n`include "../../define/global_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v.v\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v.sv\n             ../../define/global_def.v\n             ../../define/global_def.v.v\n             ../../define/global_def.v.sv\n             obj_dir/../../define/global_def.v\n             obj_dir/../../define/global_def.v.v\n             obj_dir/../../define/global_def.v.sv\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:18: Define or directive not defined: \'`INST_OP_BUS\'\n    input   wire[`INST_OP_BUS]  inst_op_in,\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:18: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`INST_OP_BUS]  inst_op_in,\n                             ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:19: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     reg_data_2_in,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:20: Define or directive not defined: \'`FUNCT_BUS\'\n    input   wire[`FUNCT_BUS]    funct_in,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:21: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     operand_1_in,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:22: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     operand_2_in,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:23: Define or directive not defined: \'`SHAMT_BUS\'\n    input   wire[`SHAMT_BUS]    shamt_in,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`REG_ADDR_BUS] write_reg_addr_in,\n    ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:25: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input   wire[`REG_ADDR_BUS] write_reg_addr_in,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:29: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                ram_write_en_out,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                ram_read_flag_out,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:32: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire[`INST_OP_BUS]  inst_op_out,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:32: Define or directive not defined: \'`INST_OP_BUS\'\n    output  wire[`INST_OP_BUS]  inst_op_out,\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:33: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     reg_data_2_out,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:34: Define or directive not defined: \'`FUNCT_BUS\'\n    output  wire[`FUNCT_BUS]    funct_out,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:35: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     operand_1_out,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:36: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     operand_2_out,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:37: Define or directive not defined: \'`SHAMT_BUS\'\n    output  wire[`SHAMT_BUS]    shamt_out,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:39: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire[`REG_ADDR_BUS] write_reg_addr_out\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:39: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  wire[`REG_ADDR_BUS] write_reg_addr_out\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:69: Define or directive not defined: \'`INST_OP_BUS_WIDTH\'\n    PipelineDeliver #(`INST_OP_BUS_WIDTH)   ff_inst_op(\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:78: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_reg_data_2(\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:87: Define or directive not defined: \'`FUNCT_BUS_WIDTH\'\n    PipelineDeliver #(`FUNCT_BUS_WIDTH) ff_funct(\n                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:96: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_operand_1(\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:105: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_operand_2(\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:114: Define or directive not defined: \'`SHAMT_BUS_WIDTH\'\n    PipelineDeliver #(`SHAMT_BUS_WIDTH) ff_shamt(\n                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_EX.v:132: Define or directive not defined: \'`REG_ADDR_BUS_WIDTH\'\n    PipelineDeliver #(`REG_ADDR_BUS_WIDTH)  ff_write_reg_addr(\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 28 error(s)\n'
module  ID_EX(
    input   wire                clk,
    input   wire                rst,


    input   wire                stall_current_stage,
    input   wire                stall_next_stage,


    input   wire                ram_en_in,
    input   wire                ram_write_en_in,
    
    input   wire                ram_read_flag_in,
    input   wire[`INST_OP_BUS]  inst_op_in,
    input   wire[`DATA_BUS]     reg_data_2_in,
    input   wire[`FUNCT_BUS]    funct_in,
    input   wire[`DATA_BUS]     operand_1_in,
    input   wire[`DATA_BUS]     operand_2_in,
    input   wire[`SHAMT_BUS]    shamt_in,
    input   wire                write_reg_en_in,
    input   wire[`REG_ADDR_BUS] write_reg_addr_in,


    output  wire                ram_en_out,
    output  wire                ram_write_en_out,

    output  wire                ram_read_flag_out,
    output  wire[`INST_OP_BUS]  inst_op_out,
    output  wire[`DATA_BUS]     reg_data_2_out,
    output  wire[`FUNCT_BUS]    funct_out,
    output  wire[`DATA_BUS]     operand_1_out,
    output  wire[`DATA_BUS]     operand_2_out,
    output  wire[`SHAMT_BUS]    shamt_out,
    output  wire                write_reg_en_out,
    output  wire[`REG_ADDR_BUS] write_reg_addr_out
);

    PipelineDeliver #(1)    ff_ram_en(
        .clk                    (clk),
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (ram_en_in),
        .out                    (ram_en_out)
    );

    PipelineDeliver #(1)    ff_ram_write_en(
        .clk                    (clk),
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (ram_write_en_in),
        .out                    (ram_write_en_out)
    );

    PipelineDeliver #(1)    ff_ram_read_flag(
        .clk                    (clk),
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (ram_read_flag_in),
        .out                    (ram_read_flag_out)
    );

    PipelineDeliver #(`INST_OP_BUS_WIDTH)   ff_inst_op(
        .clk                    (clk),
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (inst_op_in),
        .out                    (inst_op_out)
    );

    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_reg_data_2(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (reg_data_2_in),          
        .out                    (reg_data_2_out)                  
    );

    PipelineDeliver #(`FUNCT_BUS_WIDTH) ff_funct(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (funct_in),          
        .out                    (funct_out)
    );

    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_operand_1(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (operand_1_in),      
        .out                    (operand_1_out)
    );

    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_operand_2(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (operand_2_in),      
        .out                    (operand_2_out)
    );

    PipelineDeliver #(`SHAMT_BUS_WIDTH) ff_shamt(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (shamt_in),          
        .out                    (shamt_out)
    );

    PipelineDeliver #(1)    ff_write_reg_en(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_reg_en_in),   
        .out                    (write_reg_en_out)
    );

    PipelineDeliver #(`REG_ADDR_BUS_WIDTH)  ff_write_reg_addr(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_reg_addr_in), 
        .out                    (write_reg_addr_out)
    );

endmodule
module  ID_EX(
    input   wire                clk,
    input   wire                rst,


    input   wire                stall_current_stage,
    input   wire                stall_next_stage,


    input   wire                ram_en_in,
    input   wire                ram_write_en_in,
    
    input   wire                ram_read_flag_in,
    input   wire[`INST_OP_BUS]  inst_op_in,
    input   wire[`DATA_BUS]     reg_data_2_in,
    input   wire[`FUNCT_BUS]    funct_in,
    input   wire[`DATA_BUS]     operand_1_in,
    input   wire[`DATA_BUS]     operand_2_in,
    input   wire[`SHAMT_BUS]    shamt_in,
    input   wire                write_reg_en_in,
    input   wire[`REG_ADDR_BUS] write_reg_addr_in,


    output  wire                ram_en_out,
    output  wire                ram_write_en_out,

    output  wire                ram_read_flag_out,
    output  wire[`INST_OP_BUS]  inst_op_out,
    output  wire[`DATA_BUS]     reg_data_2_out,
    output  wire[`FUNCT_BUS]    funct_out,
    output  wire[`DATA_BUS]     operand_1_out,
    output  wire[`DATA_BUS]     operand_2_out,
    output  wire[`SHAMT_BUS]    shamt_out,
    output  wire                write_reg_en_out,
    output  wire[`REG_ADDR_BUS] write_reg_addr_out
);


    PipelineDeliver #(1)    ff_ram_en(
        .clk                    (clk),
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (ram_en_in),
        .out                    (ram_en_out)
    );

    PipelineDeliver #(1)    ff_ram_write_en(
        .clk                    (clk),
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (ram_write_en_in),
        .out                    (ram_write_en_out)
    );

    PipelineDeliver #(1)    ff_ram_read_flag(
        .clk                    (clk),
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (ram_read_flag_in),
        .out                    (ram_read_flag_out)
    );

    PipelineDeliver #(`INST_OP_BUS_WIDTH)   ff_inst_op(
        .clk                    (clk),
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (inst_op_in),
        .out                    (inst_op_out)
    );

    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_reg_data_2(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (reg_data_2_in),          
        .out                    (reg_data_2_out)                  
    );

    PipelineDeliver #(`FUNCT_BUS_WIDTH) ff_funct(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (funct_in),          
        .out                    (funct_out)
    );

    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_operand_1(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (operand_1_in),      
        .out                    (operand_1_out)
    );

    PipelineDeliver #(`DATA_BUS_WIDTH)  ff_operand_2(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (operand_2_in),      
        .out                    (operand_2_out)
    );

    PipelineDeliver #(`SHAMT_BUS_WIDTH) ff_shamt(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (shamt_in),          
        .out                    (shamt_out)
    );

    PipelineDeliver #(1)    ff_write_reg_en(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_reg_en_in),   
        .out                    (write_reg_en_out)
    );

    PipelineDeliver #(`REG_ADDR_BUS_WIDTH)  ff_write_reg_addr(
        .clk                    (clk),              
        .rst                    (rst),
        .stall_current_stage    (stall_current_stage),
        .stall_next_stage       (stall_next_stage),
        .in                     (write_reg_addr_in), 
        .out                    (write_reg_addr_out)
    );

endmodule