data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sim_1/new/assign_deassign_testbench.v
 line:28: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sim_1/new/assign_deassign_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = ~CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sim_1/new/assign_deassign_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #25 D = ~D;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sim_1/new/assign_deassign_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #150 RESET=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sim_1/new/assign_deassign_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #50 RESET=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sim_1/new/assign_deassign_testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #200 $finish;\n    ^\n%Error: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sim_1/new/assign_deassign_testbench.v:28: Cannot find file containing module: \'assign_deassign\'\nassign_deassign d(Q,, D, CLK, RESET);\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sim_1/new,data/full_repos/permissive/169574047/assign_deassign\n             data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sim_1/new,data/full_repos/permissive/169574047/assign_deassign.v\n             data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sim_1/new,data/full_repos/permissive/169574047/assign_deassign.sv\n             assign_deassign\n             assign_deassign.v\n             assign_deassign.sv\n             obj_dir/assign_deassign\n             obj_dir/assign_deassign.v\n             obj_dir/assign_deassign.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module assign_deassign_testbench;

reg D,CLK,RESET;
wire Q;

assign_deassign d(Q,, D, CLK, RESET);

always
    #10 CLK = ~CLK;

always
    #25 D = ~D;
        
initial
begin
    D=1; CLK=0; RESET=0;
    #150 RESET=1;
    #50 RESET=0;
    #200 $finish;
end

endmodule
module assign_deassign_testbench;


reg D,CLK,RESET;
wire Q;

assign_deassign d(Q,, D, CLK, RESET);

always
    #10 CLK = ~CLK;

always
    #25 D = ~D;
        
initial
begin
    D=1; CLK=0; RESET=0;
    #150 RESET=1;
    #50 RESET=0;
    #200 $finish;
end

endmodule