data/full_repos/permissive/139213403/FPGA/fifo.v
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data/verilator_xmls/416980b3-eb1f-4a4b-9144-be66c07e7ae9.xml
module fifo
#(
	parameter B=8,
				 W=4
)
(
	input wire clk, reset,
	input wire rd, wr,
	input wire [B-1:0] w_data,
	output wire empty, full,
	output wire [B-1:0] r_data,
	output wire of, uf
);


reg [B-1:0] array_reg [(1'b1 << W)-1:0];
reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ;
reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ;
reg of_reg, of_next;
reg uf_reg, uf_next;



always @(posedge clk)
	begin
		if (wr)
			array_reg[w_ptr_reg] <= w_data;
	end



always @(posedge clk, posedge reset)
	if (reset)
		begin
			w_ptr_reg <= 0;
			r_ptr_reg <= 0;
			of_reg <= 0;
			uf_reg <= 0;
		end
	else
		begin
			w_ptr_reg <= w_ptr_next;
			r_ptr_reg <= r_ptr_next;
			of_reg <= of_next;
			uf_reg <= uf_next;
		end


always @*
	begin		
		w_ptr_succ = w_ptr_reg + 1'b1;
		r_ptr_succ = r_ptr_reg + 1'b1;
		r_ptr_next = r_ptr_reg;
		w_ptr_next = w_ptr_reg;
		of_next = of_reg;
		uf_next = uf_reg;
		
		if (rd && wr)
			begin
				r_ptr_next = r_ptr_succ;
				w_ptr_next = w_ptr_succ;
			end
		else if (rd)
			begin
				if (w_ptr_reg == r_ptr_reg)
					uf_next = 1'b1;
				r_ptr_next = r_ptr_succ;
			end
		else if (wr)
			begin
				if (w_ptr_reg == (r_ptr_reg - 1))
					of_next = 1'b1;
				w_ptr_next = w_ptr_succ;
			end
	end
	

	assign full = w_ptr_reg == (r_ptr_reg - 1);
	assign empty = w_ptr_reg == r_ptr_reg;
		

	assign r_data = array_reg[r_ptr_reg];
	

	assign of = of_reg;
	assign uf = uf_reg;
	
endmodule
module fifo
#(
	parameter B=8,
				 W=4
)
(
	input wire clk, reset,
	input wire rd, wr,
	input wire [B-1:0] w_data,
	output wire empty, full,
	output wire [B-1:0] r_data,
	output wire of, uf
);



reg [B-1:0] array_reg [(1'b1 << W)-1:0];
reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ;
reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ;
reg of_reg, of_next;
reg uf_reg, uf_next;



always @(posedge clk)
	begin
		if (wr)
			array_reg[w_ptr_reg] <= w_data;
	end



always @(posedge clk, posedge reset)
	if (reset)
		begin
			w_ptr_reg <= 0;
			r_ptr_reg <= 0;
			of_reg <= 0;
			uf_reg <= 0;
		end
	else
		begin
			w_ptr_reg <= w_ptr_next;
			r_ptr_reg <= r_ptr_next;
			of_reg <= of_next;
			uf_reg <= uf_next;
		end


always @*
	begin		
		w_ptr_succ = w_ptr_reg + 1'b1;
		r_ptr_succ = r_ptr_reg + 1'b1;
		r_ptr_next = r_ptr_reg;
		w_ptr_next = w_ptr_reg;
		of_next = of_reg;
		uf_next = uf_reg;
		
		if (rd && wr)
			begin
				r_ptr_next = r_ptr_succ;
				w_ptr_next = w_ptr_succ;
			end
		else if (rd)
			begin
				if (w_ptr_reg == r_ptr_reg)
					uf_next = 1'b1;
				r_ptr_next = r_ptr_succ;
			end
		else if (wr)
			begin
				if (w_ptr_reg == (r_ptr_reg - 1))
					of_next = 1'b1;
				w_ptr_next = w_ptr_succ;
			end
	end
	

	assign full = w_ptr_reg == (r_ptr_reg - 1);
	assign empty = w_ptr_reg == r_ptr_reg;
		

	assign r_data = array_reg[r_ptr_reg];
	

	assign of = of_reg;
	assign uf = uf_reg;
	
endmodule