data/full_repos/permissive/125592111/verilog/Forwarding_Unit.v
data/verilator_xmls/4405ed91-f4ac-4796-98f9-46aa55bf5ad3.xml
module ForwardingUnit(


	input [4:0] ID_EX_RegRs, ID_EX_RegRt, EX_MEM_RegRd, MEM_WB_RegRd,
    input MEM_WB_RegWrite, EX_MEM_RegWrite,
	

    output reg [1:0] Mux_ForwardA, Mux_ForwardB
);
	initial begin
		Mux_ForwardA <= 0;
		Mux_ForwardB <= 0;
	end

    always @(ID_EX_RegRs, ID_EX_RegRt, EX_MEM_RegRd, EX_MEM_RegWrite, MEM_WB_RegRd, MEM_WB_RegWrite ) begin

        if (EX_MEM_RegWrite == 1 && EX_MEM_RegRd == ID_EX_RegRs) begin
            Mux_ForwardA <= 2;
        end
        else if(MEM_WB_RegWrite == 1 && MEM_WB_RegRd == ID_EX_RegRs &&
        (EX_MEM_RegRd != ID_EX_RegRs || EX_MEM_RegWrite == 0)) begin
            Mux_ForwardA <= 1;
        end
        else begin
        	Mux_ForwardA <= 0;
        end


        if (EX_MEM_RegWrite == 1 && EX_MEM_RegRd == ID_EX_RegRt) begin
            Mux_ForwardB <= 2;
    	end
    	else if (MEM_WB_RegWrite == 1 && MEM_WB_RegRd == ID_EX_RegRt &&
        (EX_MEM_RegRd != ID_EX_RegRt || EX_MEM_RegWrite == 0)) begin
            Mux_ForwardB <= 1;
        end
        else begin
        	Mux_ForwardB <= 0;
        end

	end
endmodule
module ForwardingUnit(


	input [4:0] ID_EX_RegRs, ID_EX_RegRt, EX_MEM_RegRd, MEM_WB_RegRd,
    input MEM_WB_RegWrite, EX_MEM_RegWrite,
	

    output reg [1:0] Mux_ForwardA, Mux_ForwardB
);

	initial begin
		Mux_ForwardA <= 0;
		Mux_ForwardB <= 0;
	end

    always @(ID_EX_RegRs, ID_EX_RegRt, EX_MEM_RegRd, EX_MEM_RegWrite, MEM_WB_RegRd, MEM_WB_RegWrite ) begin

        if (EX_MEM_RegWrite == 1 && EX_MEM_RegRd == ID_EX_RegRs) begin
            Mux_ForwardA <= 2;
        end
        else if(MEM_WB_RegWrite == 1 && MEM_WB_RegRd == ID_EX_RegRs &&
        (EX_MEM_RegRd != ID_EX_RegRs || EX_MEM_RegWrite == 0)) begin
            Mux_ForwardA <= 1;
        end
        else begin
        	Mux_ForwardA <= 0;
        end


        if (EX_MEM_RegWrite == 1 && EX_MEM_RegRd == ID_EX_RegRt) begin
            Mux_ForwardB <= 2;
    	end
    	else if (MEM_WB_RegWrite == 1 && MEM_WB_RegRd == ID_EX_RegRt &&
        (EX_MEM_RegRd != ID_EX_RegRt || EX_MEM_RegWrite == 0)) begin
            Mux_ForwardB <= 1;
        end
        else begin
        	Mux_ForwardB <= 0;
        end

	end
endmodule