data/full_repos/permissive/107007139/Project/delay_voice.v
data/verilator_xmls/f6f25526-58c4-4e8c-a511-59872c89e7e6.xml
module delay_voice(
    input  wire clk_20k,
    input  wire [11:0] in_voice,
    output wire [11:0] out_voice
    );
    
    parameter MEM_SIZE = 5000;
    
    reg [11:0] memory [0:MEM_SIZE-1];
    reg [12:0] i;
    
    initial begin
        for (i = 0 ; i < MEM_SIZE ; i = i + 1) begin
           memory[i] <= 12'b0111_1111_1111;
        end
    end
    
    always @(posedge clk_20k) begin
        memory[0] <= in_voice;
        for (i = 0 ; i < MEM_SIZE - 1 ; i = i + 1) begin
            memory[i+1] <= memory[i];
        end
    end
    
    assign out_voice = memory[MEM_SIZE-1];
endmodule
module delay_voice(
    input  wire clk_20k,
    input  wire [11:0] in_voice,
    output wire [11:0] out_voice
    );

    
    parameter MEM_SIZE = 5000;
    
    reg [11:0] memory [0:MEM_SIZE-1];
    reg [12:0] i;
    
    initial begin
        for (i = 0 ; i < MEM_SIZE ; i = i + 1) begin
           memory[i] <= 12'b0111_1111_1111;
        end
    end
    
    always @(posedge clk_20k) begin
        memory[0] <= in_voice;
        for (i = 0 ; i < MEM_SIZE - 1 ; i = i + 1) begin
            memory[i+1] <= memory[i];
        end
    end
    
    assign out_voice = memory[MEM_SIZE-1];
endmodule