data/full_repos/permissive/181665138/verilog/capitolo_iii/Ram.v
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-WIDTH: data/full_repos/permissive/181665138/verilog/capitolo_iii/Ram.v:82: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s ARRAYSEL generates 4 bits.\n                                                                                  : ... In instance Ram\n    assign d3_d0 = (b == 1)? LOCATION[a22_a0]:\'HZ;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181665138/verilog/capitolo_iii/Ram.v:82: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                  : ... In instance Ram\n    assign d3_d0 = (b == 1)? LOCATION[a22_a0]:\'HZ;\n                 ^\n%Error: Exiting due to 2 warning(s)\n'
module Ram(d3_d0, a22_a0, s_, mr_, mw_);
    input [22:0] a22_a0;
    input s_, mr_, mw_;

    inout [3:0] d3_d0;
    reg [3:0] LOCATION[0:8388607];



    wire b;
    assign b = ({s_, mr_, mw_} == 'B001)?1:0;

    wire c;
    assign c = ({s_, mr_, mw_} == 'B010)?1:0;


    assign d3_d0 = (b == 1)? LOCATION[a22_a0]:'HZ;


    always @(c or d3_d0)
        LOCATION[a22_a0] <= (c == 1) ? d3_d0 : LOCATION[a22_a0];
endmodule
module Ram(d3_d0, a22_a0, s_, mr_, mw_);

    input [22:0] a22_a0;
    input s_, mr_, mw_;

    inout [3:0] d3_d0;
    reg [3:0] LOCATION[0:8388607];



    wire b;
    assign b = ({s_, mr_, mw_} == 'B001)?1:0;

    wire c;
    assign c = ({s_, mr_, mw_} == 'B010)?1:0;


    assign d3_d0 = (b == 1)? LOCATION[a22_a0]:'HZ;


    always @(c or d3_d0)
        LOCATION[a22_a0] <= (c == 1) ? d3_d0 : LOCATION[a22_a0];
endmodule