data/full_repos/permissive/14657119/stopwatch.v
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1: b'%Warning-LITENDIAN: data/full_repos/permissive/14657119/stopwatch.v:5: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/14657119/stopwatch.v:11: Cannot find file containing module: \'ms_clock\'\n ms_clock ms_clock1(CLOCK_50, clk);\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/14657119,data/full_repos/permissive/14657119/ms_clock\n             data/full_repos/permissive/14657119,data/full_repos/permissive/14657119/ms_clock.v\n             data/full_repos/permissive/14657119,data/full_repos/permissive/14657119/ms_clock.sv\n             ms_clock\n             ms_clock.v\n             ms_clock.sv\n             obj_dir/ms_clock\n             obj_dir/ms_clock.v\n             obj_dir/ms_clock.sv\n%Error: data/full_repos/permissive/14657119/stopwatch.v:13: Cannot find file containing module: \'ms_clock_switched\'\n ms_clock_switched ms_clock_switched1(clk, KEY[0], ms_clk);\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/14657119/stopwatch.v:15: Cannot find file containing module: \'bcd_counter\'\n bcd_counter bcd_counter_hundredths(ms_clk, KEY[1], hundredths_bcd[3:0], tenths_in);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/14657119/stopwatch.v:16: Cannot find file containing module: \'bcd_counter\'\n bcd_counter bcd_counter_tenths(tenths_in, KEY[1], tenths_bcd[3:0], ones_in);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/14657119/stopwatch.v:17: Cannot find file containing module: \'bcd_counter\'\n bcd_counter bcd_counter_ones(ones_in, KEY[1], ones_bcd[3:0], tens_in);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/14657119/stopwatch.v:18: Cannot find file containing module: \'bcd_counter\'\n bcd_counter bcd_counter_tens(tens_in, KEY[1], tens_bcd[3:0], );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/14657119/stopwatch.v:20: Cannot find file containing module: \'seven_segment_decoder\'\n seven_segment_decoder seven_segment_decoder_hundredths(hundredths_bcd[3:0], HEX4[0:6]);\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/14657119/stopwatch.v:21: Cannot find file containing module: \'seven_segment_decoder\'\n seven_segment_decoder seven_segment_decoder_tenths(tenths_bcd[3:0], HEX5[0:6]);\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/14657119/stopwatch.v:22: Cannot find file containing module: \'seven_segment_decoder\'\n seven_segment_decoder seven_segment_decoder_ones(ones_bcd[3:0], HEX6[0:6]);\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/14657119/stopwatch.v:23: Cannot find file containing module: \'seven_segment_decoder\'\n seven_segment_decoder seven_segment_decoder_tens(tens_bcd[3:0], HEX7[0:6]);\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s), 1 warning(s)\n'
module stopwatch(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);

	input CLOCK_50;
	input [1:0] KEY;
	output [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
	
	wire ms_clk;
	wire tenths_in, ones_in, tens_in;
	wire [3:0] hundredths_bcd, tenths_bcd, ones_bcd, tens_bcd;
	
	ms_clock ms_clock1(CLOCK_50, clk);
	
	ms_clock_switched ms_clock_switched1(clk, KEY[0], ms_clk);
	
	bcd_counter bcd_counter_hundredths(ms_clk, KEY[1], hundredths_bcd[3:0], tenths_in);
	bcd_counter bcd_counter_tenths(tenths_in, KEY[1], tenths_bcd[3:0], ones_in);
	bcd_counter bcd_counter_ones(ones_in, KEY[1], ones_bcd[3:0], tens_in);
	bcd_counter bcd_counter_tens(tens_in, KEY[1], tens_bcd[3:0], );
	
	seven_segment_decoder seven_segment_decoder_hundredths(hundredths_bcd[3:0], HEX4[0:6]);
	seven_segment_decoder seven_segment_decoder_tenths(tenths_bcd[3:0], HEX5[0:6]);
	seven_segment_decoder seven_segment_decoder_ones(ones_bcd[3:0], HEX6[0:6]);
	seven_segment_decoder seven_segment_decoder_tens(tens_bcd[3:0], HEX7[0:6]);
	

	assign HEX3[0:6] = 7'b0100100;
	assign HEX2[0:6] = 7'b0110000;
	assign HEX1[0:6] = 7'b0110001;
	assign HEX0[0:6] = 7'b0100100;
endmodule
module stopwatch(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);


	input CLOCK_50;
	input [1:0] KEY;
	output [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
	
	wire ms_clk;
	wire tenths_in, ones_in, tens_in;
	wire [3:0] hundredths_bcd, tenths_bcd, ones_bcd, tens_bcd;
	
	ms_clock ms_clock1(CLOCK_50, clk);
	
	ms_clock_switched ms_clock_switched1(clk, KEY[0], ms_clk);
	
	bcd_counter bcd_counter_hundredths(ms_clk, KEY[1], hundredths_bcd[3:0], tenths_in);
	bcd_counter bcd_counter_tenths(tenths_in, KEY[1], tenths_bcd[3:0], ones_in);
	bcd_counter bcd_counter_ones(ones_in, KEY[1], ones_bcd[3:0], tens_in);
	bcd_counter bcd_counter_tens(tens_in, KEY[1], tens_bcd[3:0], );
	
	seven_segment_decoder seven_segment_decoder_hundredths(hundredths_bcd[3:0], HEX4[0:6]);
	seven_segment_decoder seven_segment_decoder_tenths(tenths_bcd[3:0], HEX5[0:6]);
	seven_segment_decoder seven_segment_decoder_ones(ones_bcd[3:0], HEX6[0:6]);
	seven_segment_decoder seven_segment_decoder_tens(tens_bcd[3:0], HEX7[0:6]);
	

	assign HEX3[0:6] = 7'b0100100;
	assign HEX2[0:6] = 7'b0110000;
	assign HEX1[0:6] = 7'b0110001;
	assign HEX0[0:6] = 7'b0100100;
endmodule