data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/LedData_Pipeline.v
1: b"%Error: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/LedData_Pipeline.v:35: Cannot find file containing module: 'Counter'\n    Counter cycle_counter(.clk(clk), .rst(rst), .enable(pc_enable), .data_out(cycles));\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources,data/full_repos/permissive/171720620/Counter\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources,data/full_repos/permissive/171720620/Counter.v\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources,data/full_repos/permissive/171720620/Counter.sv\n             Counter\n             Counter.v\n             Counter.sv\n             obj_dir/Counter\n             obj_dir/Counter.v\n             obj_dir/Counter.sv\n%Error: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/LedData_Pipeline.v:37: Cannot find file containing module: 'Counter'\n    Counter jmp_counter(.clk(clk), .rst(rst), .enable(jmp), .data_out(jmp_clcyes));\n    ^~~~~~~\n%Error: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/LedData_Pipeline.v:39: Cannot find file containing module: 'Counter'\n    Counter branchif_counter(.clk(clk), .rst(rst), .enable(branchif), .data_out(branch_clcyes));\n    ^~~~~~~\n%Error: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/LedData_Pipeline.v:41: Cannot find file containing module: 'Counter'\n    Counter loaduse_counter(.clk(clk), .rst(rst), .enable(load_use_count), .data_out(loaduse_clcyes));\n    ^~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module LedData_Pipeline (
        input [31:0] leddata_in,
        input rst,
        input clk,
        input pc_enable,
        input jmp,
        input branchif,
        input stop1,
        input stop2,
        input load_use,
        input ShowLoadUse,
        input [1:0] select,
        output reg [31:0] leddata_out
    );
    wire load_use_count;
    wire [31:0] cycles;
    wire [31:0] jmp_clcyes;
    wire [31:0] branch_clcyes;
    wire [31:0] loaduse_clcyes;

    Counter cycle_counter(.clk(clk), .rst(rst), .enable(pc_enable), .data_out(cycles));

    Counter jmp_counter(.clk(clk), .rst(rst), .enable(jmp), .data_out(jmp_clcyes));

    Counter branchif_counter(.clk(clk), .rst(rst), .enable(branchif), .data_out(branch_clcyes));

    Counter loaduse_counter(.clk(clk), .rst(rst), .enable(load_use_count), .data_out(loaduse_clcyes));

    always @(*) begin
        if (ShowLoadUse == 1) begin
            leddata_out <= loaduse_clcyes;
        end
        else begin
            case (select)
                2'b00: leddata_out <= leddata_in;
                2'b01: leddata_out <= cycles;
                2'b10: leddata_out <= jmp_clcyes;
                2'b11: leddata_out <= branch_clcyes;
            endcase
        end
    end

    assign load_use_count = load_use & pc_enable & ~(stop1 | stop2);

endmodule
module LedData_Pipeline (
        input [31:0] leddata_in,
        input rst,
        input clk,
        input pc_enable,
        input jmp,
        input branchif,
        input stop1,
        input stop2,
        input load_use,
        input ShowLoadUse,
        input [1:0] select,
        output reg [31:0] leddata_out
    );

    wire load_use_count;
    wire [31:0] cycles;
    wire [31:0] jmp_clcyes;
    wire [31:0] branch_clcyes;
    wire [31:0] loaduse_clcyes;

    Counter cycle_counter(.clk(clk), .rst(rst), .enable(pc_enable), .data_out(cycles));

    Counter jmp_counter(.clk(clk), .rst(rst), .enable(jmp), .data_out(jmp_clcyes));

    Counter branchif_counter(.clk(clk), .rst(rst), .enable(branchif), .data_out(branch_clcyes));

    Counter loaduse_counter(.clk(clk), .rst(rst), .enable(load_use_count), .data_out(loaduse_clcyes));

    always @(*) begin
        if (ShowLoadUse == 1) begin
            leddata_out <= loaduse_clcyes;
        end
        else begin
            case (select)
                2'b00: leddata_out <= leddata_in;
                2'b01: leddata_out <= cycles;
                2'b10: leddata_out <= jmp_clcyes;
                2'b11: leddata_out <= branch_clcyes;
            endcase
        end
    end

    assign load_use_count = load_use & pc_enable & ~(stop1 | stop2);

endmodule