data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/instruction_memory.v
data/verilator_xmls/07e18472-159a-4ad9-9028-f41d168f13b2.xml
module instruction_memory(input wire clk, input wire [31:0] pc, output reg [31:0] instruction, input wire reset);

reg [31:0] instruction_mem [0:255];


initial begin






    instruction_mem[0]=32'h8C090004;
    instruction_mem[4]=32'h8C0A0010;
    instruction_mem[8]=32'h8C0C0014;
    instruction_mem[12]=32'h8C0D0018;
    instruction_mem[16]=32'h8C0E001C;
    instruction_mem[20]=32'h8C0F0020;
    instruction_mem[24]=32'h0149582A;
    instruction_mem[28]=32'h11600004;
    

    instruction_mem[32]=32'h018F4018;
    instruction_mem[36]=32'h010E4020;
    instruction_mem[40]=32'h010D401A;
    instruction_mem[44]=32'h0800000F;
    

    instruction_mem[48]=32'h018D4018;
    instruction_mem[52]=32'h010E4022;
    instruction_mem[56]=32'h010F4022;
    

    instruction_mem[60]=32'hAC080024;
end


always@(posedge clk or posedge reset) begin
    if(reset==1'b1) instruction=instruction_mem[0];
    else instruction = instruction_mem[pc];
end


endmodule
module instruction_memory(input wire clk, input wire [31:0] pc, output reg [31:0] instruction, input wire reset);


reg [31:0] instruction_mem [0:255];


initial begin






    instruction_mem[0]=32'h8C090004;
    instruction_mem[4]=32'h8C0A0010;
    instruction_mem[8]=32'h8C0C0014;
    instruction_mem[12]=32'h8C0D0018;
    instruction_mem[16]=32'h8C0E001C;
    instruction_mem[20]=32'h8C0F0020;
    instruction_mem[24]=32'h0149582A;
    instruction_mem[28]=32'h11600004;
    

    instruction_mem[32]=32'h018F4018;
    instruction_mem[36]=32'h010E4020;
    instruction_mem[40]=32'h010D401A;
    instruction_mem[44]=32'h0800000F;
    

    instruction_mem[48]=32'h018D4018;
    instruction_mem[52]=32'h010E4022;
    instruction_mem[56]=32'h010F4022;
    

    instruction_mem[60]=32'hAC080024;
end


always@(posedge clk or posedge reset) begin
    if(reset==1'b1) instruction=instruction_mem[0];
    else instruction = instruction_mem[pc];
end


endmodule