data/full_repos/permissive/160024456/day02/part1.v
 line:18: before: "["
1: b"%Error: data/full_repos/permissive/160024456/day02/part1.v:24: Unsupported: SystemVerilog 2009 reserved word not implemented: 'checker'\nchecker c (.data(temp), .pair(pair), .triplet(triplet));\n^~~~~~~\n%Error: data/full_repos/permissive/160024456/day02/part1.v:24: syntax error, unexpected '(', expecting IDENTIFIER\nchecker c (.data(temp), .pair(pair), .triplet(triplet));\n           ^\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module part1 (
  clk,
  en,
  pairs,
  triplets,
  product
);

input clk;
input en;
output [7:0] pairs;
output [7:0] triplets;
output [15:0] product;
reg [7:0] pairs;
reg [7:0] triplets;

reg [15:0] counter;
wire [25:0][7:0] temp;
wire pair;
wire triplet;

rom rom (.address(counter), .en(en), .data(temp));

checker c (.data(temp), .pair(pair), .triplet(triplet));

always @(posedge clk)
  begin
    if (en == 1)
      begin
      if (counter != 250)
        begin
          counter <= counter + 1;
          pairs <= pairs + pair;
          triplets <= triplets + triplet;
        end
      end
    else
      begin
        counter <= 0;
        pairs <= 0;
        triplets <= 0;
      end
  end

assign product = pairs * triplets;

endmodule
module part1 (
  clk,
  en,
  pairs,
  triplets,
  product
);


input clk;
input en;
output [7:0] pairs;
output [7:0] triplets;
output [15:0] product;
reg [7:0] pairs;
reg [7:0] triplets;

reg [15:0] counter;
wire [25:0][7:0] temp;
wire pair;
wire triplet;

rom rom (.address(counter), .en(en), .data(temp));

checker c (.data(temp), .pair(pair), .triplet(triplet));

always @(posedge clk)
  begin
    if (en == 1)
      begin
      if (counter != 250)
        begin
          counter <= counter + 1;
          pairs <= pairs + pair;
          triplets <= triplets + triplet;
        end
      end
    else
      begin
        counter <= 0;
        pairs <= 0;
        triplets <= 0;
      end
  end

assign product = pairs * triplets;

endmodule