data/full_repos/permissive/132220215/testbenches/nBitAdder_tb.v
 line:50: before: "."
1: b'%Error: data/full_repos/permissive/132220215/testbenches/nBitAdder_tb.v:3: Cannot find include file: ../n_bit_adder.v\n`include "../n_bit_adder.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../n_bit_adder.v\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../n_bit_adder.v.v\n             data/full_repos/permissive/132220215/testbenches,data/full_repos/permissive/132220215/../n_bit_adder.v.sv\n             ../n_bit_adder.v\n             ../n_bit_adder.v.v\n             ../n_bit_adder.v.sv\n             obj_dir/../n_bit_adder.v\n             obj_dir/../n_bit_adder.v.v\n             obj_dir/../n_bit_adder.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/nBitAdder_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #35 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/nBitAdder_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #5 b_sig <= 8\'d10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/nBitAdder_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10 b_sig <= 8\'d20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/nBitAdder_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #15 b_sig <= 8\'d30;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/nBitAdder_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #20 b_sig <= 8\'d40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/nBitAdder_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #25 b_sig <= 8\'d50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/132220215/testbenches/nBitAdder_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #30 b_sig <= 8\'d60;\n  ^\n%Error: data/full_repos/permissive/132220215/testbenches/nBitAdder_tb.v:37: Unsupported or unknown PLI call: $monitor\n  $monitor("Time: %g ---> %h + %h = %h",$time,a_sig,b_sig,res_sig);\n  ^~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n'
module nBitAdder_tb;
 
 parameter nbit = 8;
 output reg [nbit-1:0] a_sig;
 output reg [nbit-1:0] b_sig;
 output reg Cin_sig;
 input [nbit:0] res_sig;

 nBitAdder nA0(.cout(res_sig[nbit]),.sum(res_sig[nbit-1:0]),.a(a_sig),.b(b_sig),.cin(Cin_sig));

 defparam nA0.N = nbit; 

 initial
 begin
	 a_sig <= 8'd10;
	 b_sig <= 8'd0;
	 Cin_sig <= 0;
	 #35 $finish;
 end

 initial
 begin
	 #5 b_sig <= 8'd10;
	 #10 b_sig <= 8'd20;
	 #15 b_sig <= 8'd30;
	 #20 b_sig <= 8'd40;
	 #25 b_sig <= 8'd50;
	 #30 b_sig <= 8'd60;
 end 

 initial 
 begin
	 $monitor("Time: %g ---> %h + %h = %h",$time,a_sig,b_sig,res_sig);
 end

endmodule
module nBitAdder_tb;

 
 parameter nbit = 8;
 output reg [nbit-1:0] a_sig;
 output reg [nbit-1:0] b_sig;
 output reg Cin_sig;
 input [nbit:0] res_sig;

 nBitAdder nA0(.cout(res_sig[nbit]),.sum(res_sig[nbit-1:0]),.a(a_sig),.b(b_sig),.cin(Cin_sig));

 defparam nA0.N = nbit; 

 initial
 begin
	 a_sig <= 8'd10;
	 b_sig <= 8'd0;
	 Cin_sig <= 0;
	 #35 $finish;
 end

 initial
 begin
	 #5 b_sig <= 8'd10;
	 #10 b_sig <= 8'd20;
	 #15 b_sig <= 8'd30;
	 #20 b_sig <= 8'd40;
	 #25 b_sig <= 8'd50;
	 #30 b_sig <= 8'd60;
 end 

 initial 
 begin
	 $monitor("Time: %g ---> %h + %h = %h",$time,a_sig,b_sig,res_sig);
 end

endmodule