data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v
 line:26: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:14: Unsupported: Ignoring delay on this delayed statement.\n #0 clock = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:15: Unsupported: Ignoring delay on this delayed statement.\n forever #20 clock = ~clock;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:20: Unsupported: Ignoring delay on this delayed statement.\n #00 a = 8\'b0000_0000; b = 8\'b0000_0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:21: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b0000_0000; b = 8\'b0000_0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:22: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b1111_1111; b = 8\'b1111_1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:23: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b1111_0000; b = 8\'b0000_1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:24: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b1010_1010; b = 8\'b0101_0101;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:25: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b1111_0000; b = 8\'b0000_1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:26: Unsupported: Ignoring delay on this delayed statement.\n #20 $stop;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:31: Unsupported: Ignoring delay on this delayed statement.\n #00 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:32: Unsupported: Ignoring delay on this delayed statement.\n #90 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:33: Unsupported: Ignoring delay on this delayed statement.\n #95 reset = 1\'b0;\n ^\n%Error: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:38: Unsupported or unknown PLI call: $monitor\n $monitor("time=3d, prod=16b, eop=1b, a=8b,b=8b,clock=1b, reset=1b",$time, prod, eop, a, b, clock, reset);\n ^~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:43: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("u_multiplier_8bit.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW2/u_multiplier_8bit.v:44: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module u_multiplier_8bit(prod, eop, a, b, clock, reset);

output reg [15:0] prod;
output reg eop;

input wire [7:0] a,b;
input wire clock, reset;



always@(negedge clock, reset)
begin
	eop = 1'b0;
	prod = 16'b0000_0000_0000_0000;
	if (reset) 
	begin
		prod = 16'b0000_0000_0000_0000;
		eop = 1'b0;
	end
	else 
	begin
		prod = prod + (a[0] ? {8'b0000_0000, b} : 16'b0000_0000_0000_0000);
		prod = prod + (a[1] ? {7'b000_0000, b, 1'b0} : 16'b0000_0000_0000_0000);
		prod = prod + (a[2] ? {6'b00_0000, b, 2'b00} : 16'b0000_0000_0000_0000);
		prod = prod + (a[3] ? {5'b0_0000, b, 3'b000} : 16'b0000_0000_0000_0000);
		prod = prod + (a[4] ? {4'b0000, b, 4'b0000} : 16'b0000_0000_0000_0000);
		prod = prod + (a[5] ? {3'b000, b, 5'b0_0000} : 16'b0000_0000_0000_0000);
		prod = prod + (a[6] ? {2'b00, b, 6'b00_0000} : 16'b0000_0000_0000_0000);
		prod = prod + (a[7] ? {1'b0, b, 7'b000_0000} : 16'b0000_0000_0000_0000);
		eop = 1'b1;
	end
end

endmodule
module u_multiplier_8bit(prod, eop, a, b, clock, reset);


output reg [15:0] prod;
output reg eop;

input wire [7:0] a,b;
input wire clock, reset;



always@(negedge clock, reset)
begin
	eop = 1'b0;
	prod = 16'b0000_0000_0000_0000;
	if (reset) 
	begin
		prod = 16'b0000_0000_0000_0000;
		eop = 1'b0;
	end
	else 
	begin
		prod = prod + (a[0] ? {8'b0000_0000, b} : 16'b0000_0000_0000_0000);
		prod = prod + (a[1] ? {7'b000_0000, b, 1'b0} : 16'b0000_0000_0000_0000);
		prod = prod + (a[2] ? {6'b00_0000, b, 2'b00} : 16'b0000_0000_0000_0000);
		prod = prod + (a[3] ? {5'b0_0000, b, 3'b000} : 16'b0000_0000_0000_0000);
		prod = prod + (a[4] ? {4'b0000, b, 4'b0000} : 16'b0000_0000_0000_0000);
		prod = prod + (a[5] ? {3'b000, b, 5'b0_0000} : 16'b0000_0000_0000_0000);
		prod = prod + (a[6] ? {2'b00, b, 6'b00_0000} : 16'b0000_0000_0000_0000);
		prod = prod + (a[7] ? {1'b0, b, 7'b000_0000} : 16'b0000_0000_0000_0000);
		eop = 1'b1;
	end
end

endmodule