data/full_repos/permissive/164482394/Verilog/MIDI_ShiftReg.v
1: b"%Error: data/full_repos/permissive/164482394/Verilog/MIDI_ShiftReg.v:32: Cannot find file containing module: 'MIDI_rx'\n MIDI_rx MRX1(Clk, Rst_n, Rx_in, read_enable, Rx, State); \n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164482394/Verilog,data/full_repos/permissive/164482394/MIDI_rx\n             data/full_repos/permissive/164482394/Verilog,data/full_repos/permissive/164482394/MIDI_rx.v\n             data/full_repos/permissive/164482394/Verilog,data/full_repos/permissive/164482394/MIDI_rx.sv\n             MIDI_rx\n             MIDI_rx.v\n             MIDI_rx.sv\n             obj_dir/MIDI_rx\n             obj_dir/MIDI_rx.v\n             obj_dir/MIDI_rx.sv\n%Error: Exiting due to 1 error(s)\n"
module MIDI_ShiftReg(Clk, Rst_n, Rx, RxData, RxDone, State);
	input Clk, Rst_n, Rx;
	output reg [23:0] RxData;
	output reg RxDone;
	output State;

	wire [7:0] Rx_in;
	wire read_enable;
	reg [23:0] RxDataBuf;

	always @ (posedge Clk)
	begin
		RxDone <= read_enable;
	end


	always @ (negedge read_enable)
	begin
		RxDataBuf <= {RxDataBuf[15:0], Rx_in};
	end 
	


	always @ (posedge Clk)
	begin
		if ((RxDataBuf[23] == 1'b1) & (RxDataBuf[15] == 1'b0) & (RxDataBuf[7] == 1'b0))
		begin
			RxData <= RxDataBuf;
		end
	end

	MIDI_rx MRX1(Clk, Rst_n, Rx_in, read_enable, Rx, State);	

endmodule
module MIDI_ShiftReg(Clk, Rst_n, Rx, RxData, RxDone, State);

	input Clk, Rst_n, Rx;
	output reg [23:0] RxData;
	output reg RxDone;
	output State;

	wire [7:0] Rx_in;
	wire read_enable;
	reg [23:0] RxDataBuf;

	always @ (posedge Clk)
	begin
		RxDone <= read_enable;
	end


	always @ (negedge read_enable)
	begin
		RxDataBuf <= {RxDataBuf[15:0], Rx_in};
	end 
	


	always @ (posedge Clk)
	begin
		if ((RxDataBuf[23] == 1'b1) & (RxDataBuf[15] == 1'b0) & (RxDataBuf[7] == 1'b0))
		begin
			RxData <= RxDataBuf;
		end
	end

	MIDI_rx MRX1(Clk, Rst_n, Rx_in, read_enable, Rx, State);	

endmodule