data/full_repos/permissive/123850123/code_repo/verilog/down_counter.v
data/verilator_xmls/4149f35f-48ed-43c1-834a-274a047ba66f.xml
module down_counter(

     input clk,
     input nrst,
     input load,
     input divide_by_2,
     
     input      [7:0] preload_count,
     output reg [7:0] count_out,
  	 
     output zero
);

 always@(posedge clk or negedge nrst)
  begin
    if(nrst & !load)


  		count_out <= 8'hFF;
 	 else if(load)

  		count_out <= preload_count;
 	 else if(divide_by_2)

  		count_out <= count_out >> 1;
     else if (!zero)
  		count_out <= count_out - 1'b1;
  end

         assign zero = count_out == 0 ;

endmodule
module down_counter(

     input clk,
     input nrst,
     input load,
     input divide_by_2,
     
     input      [7:0] preload_count,
     output reg [7:0] count_out,
  	 
     output zero
);


 always@(posedge clk or negedge nrst)
  begin
    if(nrst & !load)


  		count_out <= 8'hFF;
 	 else if(load)

  		count_out <= preload_count;
 	 else if(divide_by_2)

  		count_out <= count_out >> 1;
     else if (!zero)
  		count_out <= count_out - 1'b1;
  end

         assign zero = count_out == 0 ;

endmodule