data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v
'utf-8' codec can't decode byte 0xc9 in position 1168: invalid continuation byte
1: b'%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #0 CLK_50M = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10000 RST_N = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10000 RST_N = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10000000 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\nalways #10000 \n       ^\n%Error: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:18: Cannot find file containing module: \'Cordic_Test\'\nCordic_Test                 uut \n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl,data/full_repos/permissive/117851934/Cordic_Test\n             data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl,data/full_repos/permissive/117851934/Cordic_Test.v\n             data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl,data/full_repos/permissive/117851934/Cordic_Test.sv\n             Cordic_Test\n             Cordic_Test.v\n             Cordic_Test.sv\n             obj_dir/Cordic_Test\n             obj_dir/Cordic_Test.v\n             obj_dir/Cordic_Test.sv\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:44: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                      : ... In instance Cordic_Test_tb\n        cnt <= 1\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:53: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                      : ... In instance Cordic_Test_tb\n        cnt_n = 1\'b0;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:62: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                      : ... In instance Cordic_Test_tb\n        Phase <= 1\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:70: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'cnt\' generates 25 bits.\n                                                                                                      : ... In instance Cordic_Test_tb\n        Phase_n = cnt;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:72: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 27 bits.\n                                                                                                      : ... In instance Cordic_Test_tb\n        Phase_n = {2\'b01,cnt - 25\'h5a0000};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:74: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 27 bits.\n                                                                                                      : ... In instance Cordic_Test_tb\n        Phase_n = {2\'b10,cnt - 25\'hb40000};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/wave_gen/hdl/cordic_test_tb.v:76: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 27 bits.\n                                                                                                      : ... In instance Cordic_Test_tb\n        Phase_n = {2\'b11,cnt - 25\'h10e0000};\n                ^\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Cordic_Test_tb;


reg                         CLK_50M;
reg                         RST_N;
reg             [24:0]      cnt;
reg             [24:0]      cnt_n;
reg             [31:0]      Phase;
reg             [31:0]      Phase_n;
wire            [31:0]      Sin;
wire            [31:0]      Cos;
wire            [31:0]      Error;
reg							[24:0]			step;


Cordic_Test                 uut 
(
    .CLK_50M                (CLK_50M    ),
    .RST_N                  (RST_N      ),
    .Phase                  (Phase      ),
    .Sin                    (Sin        ),
    .Cos                    (Cos        ),
    .Error                  (Error      )
);

initial
begin
    #0 CLK_50M = 1'b0;
    #10000 RST_N = 1'b0;
    #10000 RST_N = 1'b1;
    #10000000 $stop;
end 

always #10000 
begin
    CLK_50M = ~CLK_50M;
end

always @ (posedge CLK_50M or negedge RST_N)
begin
    if(!RST_N) begin
        cnt <= 1'b0;
        step <= 25'h10000;
    end else
        cnt <= cnt_n;
end

always @ (*)
begin
    if(cnt >= 25'h1680000)
        cnt_n = 1'b0;
    else
        cnt_n = cnt + step;
end


always @ (posedge CLK_50M or negedge RST_N)
begin
    if(!RST_N)
        Phase <= 1'b0;
    else
        Phase <= Phase_n;
end

always @ (*)
begin
    if(cnt <= 25'h5a0000)
        Phase_n = cnt;
    else if(cnt > 25'h5a0000 && cnt <= 25'hb40000)
        Phase_n = {2'b01,cnt - 25'h5a0000};
    else if(cnt > 25'hb40000 && cnt <= 25'h10e0000)
        Phase_n = {2'b10,cnt - 25'hb40000};
    else if(cnt > 25'h10e0000)
        Phase_n = {2'b11,cnt - 25'h10e0000};
end

endmodule
module Cordic_Test_tb;



reg                         CLK_50M;
reg                         RST_N;
reg             [24:0]      cnt;
reg             [24:0]      cnt_n;
reg             [31:0]      Phase;
reg             [31:0]      Phase_n;
wire            [31:0]      Sin;
wire            [31:0]      Cos;
wire            [31:0]      Error;
reg							[24:0]			step;


Cordic_Test                 uut 
(
    .CLK_50M                (CLK_50M    ),
    .RST_N                  (RST_N      ),
    .Phase                  (Phase      ),
    .Sin                    (Sin        ),
    .Cos                    (Cos        ),
    .Error                  (Error      )
);

initial
begin
    #0 CLK_50M = 1'b0;
    #10000 RST_N = 1'b0;
    #10000 RST_N = 1'b1;
    #10000000 $stop;
end 

always #10000 
begin
    CLK_50M = ~CLK_50M;
end

always @ (posedge CLK_50M or negedge RST_N)
begin
    if(!RST_N) begin
        cnt <= 1'b0;
        step <= 25'h10000;
    end else
        cnt <= cnt_n;
end

always @ (*)
begin
    if(cnt >= 25'h1680000)
        cnt_n = 1'b0;
    else
        cnt_n = cnt + step;
end


always @ (posedge CLK_50M or negedge RST_N)
begin
    if(!RST_N)
        Phase <= 1'b0;
    else
        Phase <= Phase_n;
end

always @ (*)
begin
    if(cnt <= 25'h5a0000)
        Phase_n = cnt;
    else if(cnt > 25'h5a0000 && cnt <= 25'hb40000)
        Phase_n = {2'b01,cnt - 25'h5a0000};
    else if(cnt > 25'hb40000 && cnt <= 25'h10e0000)
        Phase_n = {2'b10,cnt - 25'hb40000};
    else if(cnt > 25'h10e0000)
        Phase_n = {2'b11,cnt - 25'h10e0000};
end

endmodule