data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus/textbench74.v
 line:12: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus/textbench74.v:7: Unsupported: Ignoring delay on this delayed statement.\nalways#(clock_period/2)Clk=~Clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus/textbench74.v:13: Unsupported: Ignoring delay on this delayed statement.\n   #20 D=$random;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus/textbench74.v:17: Unsupported: Ignoring delay on this delayed statement.\n #400 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus/textbench74.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #20 SD=2\'b00;RD=2\'b11;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus/textbench74.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #20 SD=2\'b11;RD=2\'b00;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus/textbench74.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #20 SD=2\'b11;RD=2\'b11;\n  ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus/textbench74.v:4: Little bit endian vector: MSB < LSB of bit range: 1:2\nreg [1:2]D,Clk,SD,RD;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus/textbench74.v:5: Little bit endian vector: MSB < LSB of bit range: 1:2\nwire [1:2]Q,QN;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus/textbench74.v:13: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                  : ... In instance testbench\n   #20 D=$random;\n        ^\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus/textbench74.v:27: Cannot find file containing module: \'HC74\'\nHC74 u1(D,Clk,Q,SD,RD,QN);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus,data/full_repos/permissive/165160692/HC74\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus,data/full_repos/permissive/165160692/HC74.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC74/stimulus,data/full_repos/permissive/165160692/HC74.sv\n             HC74\n             HC74.v\n             HC74.sv\n             obj_dir/HC74\n             obj_dir/HC74.v\n             obj_dir/HC74.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
reg [1:2]D,Clk,SD,RD;
wire [1:2]Q,QN;
parameter clock_period=20;
always#(clock_period/2)Clk=~Clk;

initial
 begin
  D=0;Clk=0;
  repeat(20)
   #20 D=$random;
 end

initial
 #400 $finish;

initial
 begin
  SD=2'b00;RD=2'b00;
  #20 SD=2'b00;RD=2'b11;
  #20 SD=2'b11;RD=2'b00;
  #20 SD=2'b11;RD=2'b11;
 end

HC74 u1(D,Clk,Q,SD,RD,QN);
endmodule
module testbench;

reg [1:2]D,Clk,SD,RD;
wire [1:2]Q,QN;
parameter clock_period=20;
always#(clock_period/2)Clk=~Clk;

initial
 begin
  D=0;Clk=0;
  repeat(20)
   #20 D=$random;
 end

initial
 #400 $finish;

initial
 begin
  SD=2'b00;RD=2'b00;
  #20 SD=2'b00;RD=2'b11;
  #20 SD=2'b11;RD=2'b00;
  #20 SD=2'b11;RD=2'b11;
 end

HC74 u1(D,Clk,Q,SD,RD,QN);
endmodule