data/full_repos/permissive/114943225/comparator.v
data/verilator_xmls/6782b811-5f99-4567-bcd1-08b328c543bf.xml
module comparator (

	input clkIn,
	input[13:0] threshold,
	input[13:0] hysteresis,
	input[13:0] adc_data,
	output reg q,
	output reg z

);


	always @(posedge clkIn) begin

		if (adc_data > (threshold + hysteresis)) begin
		
			q <= 1;
			z <= 0;
		
		end
		
		else if (adc_data < (threshold - hysteresis)) begin
		
			q <= 0;
			z <= 0;
		
		end 
		
		else begin
		
			z <= 1;
		
		end;
	
	end


endmodule
module comparator (

	input clkIn,
	input[13:0] threshold,
	input[13:0] hysteresis,
	input[13:0] adc_data,
	output reg q,
	output reg z

);



	always @(posedge clkIn) begin

		if (adc_data > (threshold + hysteresis)) begin
		
			q <= 1;
			z <= 0;
		
		end
		
		else if (adc_data < (threshold - hysteresis)) begin
		
			q <= 0;
			z <= 0;
		
		end 
		
		else begin
		
			z <= 1;
		
		end;
	
	end


endmodule