data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v
'utf-8' codec can't decode byte 0xb5 in position 633: invalid start byte
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:1: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc,data/full_repos/permissive/131921633/Data/Control/Control.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc,data/full_repos/permissive/131921633/Data/Control/Control.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc,data/full_repos/permissive/131921633/Data/Control/Control.v.sv\n             Data/Control/Control.v\n             Data/Control/Control.v.v\n             Data/Control/Control.v.sv\n             obj_dir/Data/Control/Control.v\n             obj_dir/Data/Control/Control.v.v\n             obj_dir/Data/Control/Control.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:2: Cannot find include file: Data/Memory/rom.v\n`include "Data/Memory/rom.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:4: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:5: Cannot find include file: Mips/Instruction/Format/IFormat.v\n`include "Mips/Instruction/Format/IFormat.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:6: Cannot find include file: Mips/Instruction/Format/JFormat.v\n`include "Mips/Instruction/Format/JFormat.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:8: Cannot find include file: Mips/Datapath/Pc/pc.v\n`include "Mips/Datapath/Pc/pc.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:9: Cannot find include file: Mips/Datapath/Pc/action.v\n`include "Mips/Datapath/Pc/action.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:10: Cannot find include file: Mips/Control/Control.v\n`include "Mips/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:12: Cannot find include file: Mips/Control/Signal/Pc/Control.v\n`include "Mips/Control/Signal/Pc/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:20: Define or directive not defined: \'`Data_Control_Control_T\'\n ( `Data_Control_Control_T (input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:20: syntax error, unexpected \'(\', expecting \'[\'\n ( `Data_Control_Control_T (input) ctrl\n                            ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:21: Define or directive not defined: \'`Mips_Control_Control_T\'\n , `Mips_Control_Control_T (input) control\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:22: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (input)  regPort1\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:24: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (output) addrCurr\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:25: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (output) addrNext\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:26: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (output) instruction\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:29: Define or directive not defined: \'`Util_Math_log2_expr\'\n`Util_Math_log2_expr\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:42: Define or directive not defined: \'`Mips_Control_Signal_Pc_Control_T\'\n`Mips_Control_Signal_Pc_Control_T(wire) pcControl;\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:43: Define or directive not defined: \'`Mips_Control_Control_Pc\'\nassign pcControl = `Mips_Control_Control_Pc(control);\n                   ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:45: Define or directive not defined: \'`Mips_Control_Signal_Pc_Control_Action_T\'\n`Mips_Control_Signal_Pc_Control_Action_T(wire) action;\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:57: Define or directive not defined: \'`Mips_Instruction_Format_IFormat_Imm\'\n , .offset (`Mips_Instruction_Format_IFormat_Imm(instruction))\n            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Pc/datapath.v:58: Define or directive not defined: \'`Mips_Instruction_Format_JFormat_Target\'\n , .jump   (`Mips_Instruction_Format_JFormat_Target(instruction))\n            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n'
module Mips_Datapath_Pc_datapath #
	( parameter FILE   = "asm/test0.mif"
	, parameter ADDR_L = 64
	, parameter ADDR_W = Util_Math_log2(ADDR_L)
	, parameter DATA_W = 32
	)
	( `Data_Control_Control_T (input) ctrl
	, `Mips_Control_Control_T (input) control
	, `Mips_Type_Word_T (input)  regPort1
	,                    input   regPortEq
	, `Mips_Type_Word_T (output) addrCurr
	, `Mips_Type_Word_T (output) addrNext
	, `Mips_Type_Word_T (output) instruction
	);

`Util_Math_log2_expr

Data_Memory_rom #
	( .FILE    (FILE)
	, .ADDR_L  (ADDR_L)
	, .ADDR_W  (ADDR_W)
	, .DATA_W  (DATA_W)
	) ROM
	( .addr  (addrNext[ADDR_W+1:2])
	, .ctrl  (ctrl)
	, .out   (instruction)
	);

`Mips_Control_Signal_Pc_Control_T(wire) pcControl;
assign pcControl = `Mips_Control_Control_Pc(control);

`Mips_Control_Signal_Pc_Control_Action_T(wire) action;
Mips_Datapath_Pc_action ACT
	( .portEq  (regPortEq)
	, .control (pcControl)
	, .action  (action)
	);

Mips_Datapath_Pc_pc #
	( .ADDR_W (32)
	) PC
	( .ctrl   (ctrl)
	, .action (action)
	, .offset (`Mips_Instruction_Format_IFormat_Imm(instruction))
	, .jump   (`Mips_Instruction_Format_JFormat_Target(instruction))
	, .jumpr  (regPort1)
	, .addrNext (addrNext)
	, .addrCurr (addrCurr)
	);

endmodule
module Mips_Datapath_Pc_datapath #
	( parameter FILE   = "asm/test0.mif"
	, parameter ADDR_L = 64
	, parameter ADDR_W = Util_Math_log2(ADDR_L)
	, parameter DATA_W = 32
	)
	( `Data_Control_Control_T (input) ctrl
	, `Mips_Control_Control_T (input) control
	, `Mips_Type_Word_T (input)  regPort1
	,                    input   regPortEq
	, `Mips_Type_Word_T (output) addrCurr
	, `Mips_Type_Word_T (output) addrNext
	, `Mips_Type_Word_T (output) instruction
	);


`Util_Math_log2_expr

Data_Memory_rom #
	( .FILE    (FILE)
	, .ADDR_L  (ADDR_L)
	, .ADDR_W  (ADDR_W)
	, .DATA_W  (DATA_W)
	) ROM
	( .addr  (addrNext[ADDR_W+1:2])
	, .ctrl  (ctrl)
	, .out   (instruction)
	);

`Mips_Control_Signal_Pc_Control_T(wire) pcControl;
assign pcControl = `Mips_Control_Control_Pc(control);

`Mips_Control_Signal_Pc_Control_Action_T(wire) action;
Mips_Datapath_Pc_action ACT
	( .portEq  (regPortEq)
	, .control (pcControl)
	, .action  (action)
	);

Mips_Datapath_Pc_pc #
	( .ADDR_W (32)
	) PC
	( .ctrl   (ctrl)
	, .action (action)
	, .offset (`Mips_Instruction_Format_IFormat_Imm(instruction))
	, .jump   (`Mips_Instruction_Format_JFormat_Target(instruction))
	, .jumpr  (regPort1)
	, .addrNext (addrNext)
	, .addrCurr (addrCurr)
	);

endmodule