data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:39: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'addr\' generates 16 bits.\n                                                                                            : ... In instance processor\nassign o_addr = read ? {cs[15:0], 4\'h0} + addr :\n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:40: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'IP\' generates 16 bits.\n                                                                                            : ... In instance processor\n                       {CS[15:0], 4\'h0} + IP;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:76: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                            : ... In instance processor\nreg     [3:0]       state = 3\'h0;       \n                            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:100: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                             : ... In instance processor\nwire            state_decode = state == 3\'h0;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:101: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                             : ... In instance processor\nreg     [15:0]  opcode_cache = 8\'h00;\n                               ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:102: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'current_byte\' generates 8 bits.\n                                                                                             : ... In instance processor\nwire    [7:0]   opcode       = state_decode ? current_byte : opcode_cache;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:102: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 16 bits.\n                                                                                             : ... In instance processor\nwire    [7:0]   opcode       = state_decode ? current_byte : opcode_cache;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:181: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'seg_id\' generates 2 bits.\n                                                                                             : ... In instance processor\n    case (seg_id)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:229: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b000: op1t = opcode[0] ? AX : AX[7:0];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:230: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b001: op1t = opcode[0] ? CX : CX[7:0];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:231: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b010: op1t = opcode[0] ? DX : DX[7:0];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:232: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b011: op1t = opcode[0] ? BX : BX[7:0];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:233: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b100: op1t = opcode[0] ? SP : AX[15:8];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:234: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b101: op1t = opcode[0] ? BP : CX[15:8];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:235: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b110: op1t = opcode[0] ? SI : DX[15:8];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:236: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b111: op1t = opcode[0] ? DI : BX[15:8];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:243: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b000: op2t = opcode[0] ? AX : AX[7:0];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:244: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b001: op2t = opcode[0] ? CX : CX[7:0];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:245: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b010: op2t = opcode[0] ? DX : DX[7:0];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:246: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b011: op2t = opcode[0] ? BX : BX[7:0];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:247: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b100: op2t = opcode[0] ? SP : AX[15:8];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:248: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b101: op2t = opcode[0] ? BP : CX[15:8];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:249: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b110: op2t = opcode[0] ? SI : DX[15:8];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:250: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n        3\'b111: op2t = opcode[0] ? DI : BX[15:8];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:284: Operator OR expects 17 bits on the LHS, but LHS\'s VARREF \'op1\' generates 16 bits.\n                                                                                             : ... In instance processor\n        3\'h1:  alu_res = op1 | op2;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:284: Operator OR expects 17 bits on the RHS, but RHS\'s VARREF \'op2\' generates 16 bits.\n                                                                                             : ... In instance processor\n        3\'h1:  alu_res = op1 | op2;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:285: Operator ADD expects 17 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                             : ... In instance processor\n        3\'h2: alu_res = op1 + op2 + FLAGS[0];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:286: Operator SUB expects 17 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                             : ... In instance processor\n        3\'h3: alu_res = op1 - op2 - FLAGS[0];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:287: Operator AND expects 17 bits on the LHS, but LHS\'s VARREF \'op1\' generates 16 bits.\n                                                                                             : ... In instance processor\n        3\'h4: alu_res = op1 & op2;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:287: Operator AND expects 17 bits on the RHS, but RHS\'s VARREF \'op2\' generates 16 bits.\n                                                                                             : ... In instance processor\n        3\'h4: alu_res = op1 & op2;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:289: Operator XOR expects 17 bits on the LHS, but LHS\'s VARREF \'op1\' generates 16 bits.\n                                                                                             : ... In instance processor\n        3\'h6: alu_res = op1 ^ op2;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:289: Operator XOR expects 17 bits on the RHS, but RHS\'s VARREF \'op2\' generates 16 bits.\n                                                                                             : ... In instance processor\n        3\'h6: alu_res = op1 ^ op2;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:352: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance processor\n        micro   <= 1\'b0;       \n                ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:376: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                                             : ... In instance processor\n                        state <= 3\'h1;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:390: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                             : ... In instance processor\n                            state <= 3\'h6;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:395: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                                             : ... In instance processor\n                            2\'b01, 2\'b10: state <= 3\'h3;\n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:401: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                             : ... In instance processor\n                                state   <= 3\'h4;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:409: Operator ADD expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                             : ... In instance processor\n                    IP <= IP + 2\'h2;  \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:414: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                             : ... In instance processor\n                    state   <= 3\'h6;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:420: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'current_byte\' generates 8 bits.\n                                                                                             : ... In instance processor\n                opcode_cache <= current_byte;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:453: Operator ADD expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                             : ... In instance processor\n            IP   <= IP + 2\'h2;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:458: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                             : ... In instance processor\n        state <= 3\'h4;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:473: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                             : ... In instance processor\n            state <= 3\'h6;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:483: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                             : ... In instance processor\n                    state   <= 3\'h4;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:492: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'current_byte\' generates 8 bits.\n                                                                                             : ... In instance processor\n                    addr    <= addrx + current_byte;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:493: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                                             : ... In instance processor\n                    state   <= 3\'h2;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:494: Operator ADD expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                             : ... In instance processor\n                    IP      <= IP + 2\'h2;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:503: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                             : ... In instance processor\n                    state   <= 3\'h4;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:515: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                             : ... In instance processor\n        state       <= 3\'h4;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:528: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n                if (opcode[1]) op2 <= i_data[15:8];\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:529: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                             : ... In instance processor\n                          else op1 <= i_data[15:8];\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:532: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                             : ... In instance processor\n                state <= 3\'h5;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:539: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                             : ... In instance processor\n                state <= 3\'h6;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:545: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'current_byte\' generates 8 bits.\n                                                                                             : ... In instance processor\n            if (opcode[1]) op2 <= current_byte;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:546: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'current_byte\' generates 8 bits.\n                                                                                             : ... In instance processor\n                      else op1 <= current_byte;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:548: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                             : ... In instance processor\n            state <= 3\'h6;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:561: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                             : ... In instance processor\n        state <= 3\'h6;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:574: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'alu_res\' generates 17 bits.\n                                                                                             : ... In instance processor\n                wrdata   <= alu_res;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:575: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'alu_res\' generates 17 bits.\n                                                                                             : ... In instance processor\n                regdata  <= alu_res;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:579: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                             : ... In instance processor\n                begin read <= 1\'b0; state <= 3\'h0; end\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:582: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                             : ... In instance processor\n                begin wreg_num <= modrm[5:3]; wreg <= 1\'b1; read <= 1\'b0; state <= 3\'h0; end\n                                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:587: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                             : ... In instance processor\n                    begin wreg_num <= modrm[2:0]; wreg <= 1\'b1; read <= 1\'b0; state <= 3\'h0; end\n                                                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:588: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                             : ... In instance processor\n                    else   begin state <= 3\'h7; next_state <= 3\'h0; end\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:588: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                             : ... In instance processor\n                    else   begin state <= 3\'h7; next_state <= 3\'h0; end\n                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:600: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'current_byte\' generates 8 bits.\n                                                                                             : ... In instance processor\n                op2      <= current_byte;                \n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:345: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                             : ... In instance processor\n    case (state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:345: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h3\' generates 3 bits.\n                                                                                             : ... In instance processor\n    case (state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:345: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h1\' generates 3 bits.\n                                                                                             : ... In instance processor\n    case (state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:345: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h2\' generates 3 bits.\n                                                                                             : ... In instance processor\n    case (state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:345: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                             : ... In instance processor\n    case (state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:345: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                             : ... In instance processor\n    case (state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:345: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                             : ... In instance processor\n    case (state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.x8086/processor.v:345: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                             : ... In instance processor\n    case (state)\n    ^~~~\n%Error: Exiting due to 73 warning(s)\n'
module processor(

    input   wire            clock,
    input   wire            locked,
    input   wire            m_ready,
    output  wire    [19:0]  o_addr,
    input   wire    [15:0]  i_data,
    output  reg     [15:0]  o_data,
    output  reg             o_wr

);

`define DECODE              3'h0
`define FETCH_MODRM         3'h1
`define READ_UNALIGNED      3'h2
`define READ_ALIGNED_DISP   3'h3
`define READ_DATA           3'h4
`define READ_DATA_16        3'h5
`define EXECUTE             3'h6
`define WRITE               3'h7
`define WRITE_16            4'h8
`define WRITE_16E           4'h9
`define END_OPCODE          4'hA

`define ALU_ADD             3'h0
`define ALU_OR              3'h1
`define ALU_ADC             3'h2
`define ALU_SBB             3'h3
`define ALU_AND             3'h4
`define ALU_SUB             3'h5
`define ALU_XOR             3'h6
`define ALU_CMP             3'h7





assign o_addr = read ? {cs[15:0], 4'h0} + addr :
                       {CS[15:0], 4'h0} + IP;

initial o_data = 16'h0000;








reg     [15:0]    AX = 16'h3344;
reg     [15:0]    CX = 16'h2200;
reg     [15:0]    DX = 16'h0000;
reg     [15:0]    BX = 16'h0010;
reg     [15:0]    SP = 16'h0000;
reg     [15:0]    BP = 16'h0000;
reg     [15:0]    SI = 16'h2001;
reg     [15:0]    DI = 16'h0000;


reg     [15:0]    ES = 16'h0000;
reg     [15:0]    CS = 16'h0000;
reg     [15:0]    SS = 16'h0000;
reg     [15:0]    DS = 16'h0000;




reg     [11:0] FLAGS = 12'h000;
reg     [15:0]    IP = 16'h0000;





reg     [3:0]       state = `DECODE;
reg     [3:0]       next_state;
reg     [3:0]       micro;
reg     [15:0]      cs;
reg     [15:0]      addr;

reg         read = 1'b0;
reg         wreg = 1'b0;
reg         wreg_bit = 1'b0;
reg [2:0]   wreg_num = 3'h0;
reg [15:0]  wrdata = 16'h0000;
reg [15:0]  regdata = 16'h0000;









wire    [7:0]   current_byte = o_addr[0] ? i_data[15:8] : i_data[7:0];
wire    [7:0]   next_byte    = o_addr[0] ? i_data[7:0] : i_data[15:8];

wire            state_decode = state == `DECODE;
reg     [15:0]  opcode_cache = 8'h00;
wire    [7:0]   opcode       = state_decode ? current_byte : opcode_cache;


reg             opcode_modrm;



always @* begin




    casex (opcode)

        8'b00_xxx0xx,
        8'b10_00xxxx,
        8'b11_00000x,
        8'b11_0001xx,
        8'b11_0100xx,
        8'b11_011xxx,
        8'b11_11x11x:
            opcode_modrm = 1'b1;
        default:
            opcode_modrm = 1'b0;

    endcase

end




reg             seg_overlap;
reg             seg_overlap_cache;
reg     [1:0]   seg_number = 2'h3;
reg     [1:0]   seg_number_cache;

reg     [1:0]   disp;
reg     [1:0]   disp_cache;
reg     [7:0]   modrm;
reg     [15:0]  segp;
reg     [15:0]  sege;
reg     [15:0]  addrx;
reg     [15:0]  op1t;
reg     [15:0]  op1;
reg     [15:0]  op2t;
reg     [15:0]  op2;

wire    [15:0]  si_bx = SI + BX;
wire    [15:0]  di_bx = DI + BX;
wire    [15:0]  si_bp = SI + BP;
wire    [15:0]  di_bp = DI + BP;


wire            seg_override = (state_decode ? seg_overlap : seg_overlap_cache);
wire    [1:0]   seg_id       = (state_decode ? seg_number  : seg_number_cache);


always @* begin


    case (seg_id)

        3'h0: segp = ES;
        3'h1: segp = CS;
        3'h2: segp = SS;
        3'h3: segp = DS;

    endcase


    casex (next_byte)

        8'b00_xxx_11x: sege = seg_override ? segp : DS;
        8'bxx_xxx_x0x: sege = seg_override ? segp : DS;
        8'bxx_xxx_110: sege = seg_override ? segp : SS;
        8'bxx_xxx_01x: sege = seg_override ? segp : SS;
        default:       sege = DS;

    endcase


    casex (next_byte)

        8'bxx_xxx_000: addrx = si_bx;
        8'bxx_xxx_001: addrx = di_bx;
        8'bxx_xxx_010: addrx = si_bp;
        8'bxx_xxx_011: addrx = di_bp;
        8'bxx_xxx_100: addrx = SI;
        8'bxx_xxx_101: addrx = DI;
        8'b00_xxx_110: addrx = 16'h0000;
        8'bxx_xxx_110: addrx = BP;
        8'bxx_xxx_111: addrx = BX;

    endcase


    casex (next_byte)

        8'b01_xxx_xxx: disp = 2'b01;
        8'b00_xxx_110: disp = 2'b10;
        8'b10_xxx_xxx: disp = 2'b10;
        default:       disp = 2'b00;

    endcase


    case (opcode[1] ? next_byte[5:3] : next_byte[2:0])

        3'b000: op1t = opcode[0] ? AX : AX[7:0];
        3'b001: op1t = opcode[0] ? CX : CX[7:0];
        3'b010: op1t = opcode[0] ? DX : DX[7:0];
        3'b011: op1t = opcode[0] ? BX : BX[7:0];
        3'b100: op1t = opcode[0] ? SP : AX[15:8];
        3'b101: op1t = opcode[0] ? BP : CX[15:8];
        3'b110: op1t = opcode[0] ? SI : DX[15:8];
        3'b111: op1t = opcode[0] ? DI : BX[15:8];

    endcase


    case (opcode[1] ? next_byte[2:0] : next_byte[5:3])

        3'b000: op2t = opcode[0] ? AX : AX[7:0];
        3'b001: op2t = opcode[0] ? CX : CX[7:0];
        3'b010: op2t = opcode[0] ? DX : DX[7:0];
        3'b011: op2t = opcode[0] ? BX : BX[7:0];
        3'b100: op2t = opcode[0] ? SP : AX[15:8];
        3'b101: op2t = opcode[0] ? BP : CX[15:8];
        3'b110: op2t = opcode[0] ? SI : DX[15:8];
        3'b111: op2t = opcode[0] ? DI : BX[15:8];

    endcase

end





reg     [2:0]  alu_mode;
reg     [16:0] alu_res;
reg     [11:0] alu_flag;
reg            alu_bits;

wire    alu_parity = alu_res[7] ^ alu_res[6] ^ alu_res[5] ^
                            alu_res[4] ^ alu_res[3] ^ alu_res[2] ^
                            alu_res[1] ^ alu_res[0] ^ 1'b1;

wire    alu_zero8   = alu_res[7:0]  == 8'h00;
wire    alu_zero16  = alu_res[15:0] == 16'h0000;
wire    alu_aux_add = ((op1[3] | op2[3]) & !alu_res[3]) | (op1[3]*op2[3]*alu_res[3]);
wire    alu_aux_sub = ((op2[3] ^ alu_res[3]) & !op1[3]) | (op2[3] & alu_res[3]);
wire    alu_overflow_add8  = (op1[7]  ^ op2[7]   ^ 1'b1) & (op1[7]  ^ alu_res[7]);
wire    alu_overflow_sub8  = (op1[7]  ^ op2[7]         ) & (op1[7]  ^ alu_res[7]);
wire    alu_overflow_add16 = (op1[15] ^ op2[15]  ^ 1'b1) & (op1[15] ^ alu_res[15]);
wire    alu_overflow_sub16 = (op1[15] ^ op2[15]        ) & (op1[15] ^ alu_res[15]);

always @* begin


    case (alu_mode)

        `ALU_ADD: alu_res = op1 + op2;
        `ALU_OR:  alu_res = op1 | op2;
        `ALU_ADC: alu_res = op1 + op2 + FLAGS[0];
        `ALU_SBB: alu_res = op1 - op2 - FLAGS[0];
        `ALU_AND: alu_res = op1 & op2;
        `ALU_SUB, `ALU_CMP: alu_res = op1 - op2;
        `ALU_XOR: alu_res = op1 ^ op2;

    endcase


    case (alu_mode)

        `ALU_ADD, `ALU_ADC: alu_flag = {
alu_bits ? alu_overflow_add16 : alu_overflow_add8,
FLAGS[10:8],
alu_bits ? alu_res[15] : alu_res[7],
alu_bits ? alu_zero16 : alu_zero8,
1'b0,
alu_aux_add,
1'b0,
alu_parity,
1'b1,
alu_bits ? alu_res[16] : alu_res[8]
        };

        `ALU_SBB, `ALU_SUB, `ALU_CMP: alu_flag = {
alu_bits ? alu_overflow_sub16 : alu_overflow_sub8,
FLAGS[10:8],
alu_bits ? alu_res[15] : alu_res[7],
alu_bits ? alu_zero16 : alu_zero8,
1'b0,
alu_aux_sub,
1'b0,
alu_parity,
1'b1,
alu_bits ? alu_res[16] : alu_res[8]
        };

        `ALU_OR, `ALU_AND, `ALU_XOR: alu_flag = {
1'b0,
FLAGS[10:8],
alu_bits ? alu_res[15] : alu_res[7],
alu_bits ? alu_zero16 : alu_zero8,
1'b0,
FLAGS[4],
1'b0,
alu_parity,
1'b1,
1'b0
        };

    endcase

end





always @(posedge clock) begin

    case (state)


    `DECODE: begin

        wreg    <= 1'b0;
        o_wr    <= 1'b0;
        micro   <= 1'b0;

        casex (opcode)

            8'b001x_x110:begin

                seg_overlap <= 1'b1;
                seg_number  <= current_byte[4:3];
                IP          <= IP + 1'b1;

            end







            default:begin

                if(opcode_modrm) begin

                    if(IP[0]) begin

                        state <= `FETCH_MODRM;

                    end else begin


                        op1  <= op1t;
                        op2  <= op2t;
                        cs   <= sege;
                        addr <= addrx;
                        disp_cache <= disp;
                        modrm <= next_byte;

                        if(next_byte[7:6] == 2'b11) begin

                            state <= `EXECUTE;

                        end elsecase (disp)


                            2'b01, 2'b10: state <= `READ_ALIGNED_DISP;


                            default: begin

                                read    <= 1'b1;
                                state   <= `READ_DATA;

                            end

                        endcase

                    end

                    IP <= IP + 2'h2;


                end else begin

                    state   <= `EXECUTE;
                    IP      <= IP + 1'b1;

                end


                opcode_cache <= current_byte;


                seg_overlap_cache   <= seg_overlap;
                seg_number_cache    <= seg_number;


                seg_overlap         <= 1'b0;
                seg_number          <= 2'h3;


                alu_bits  <= opcode[0];
                alu_mode  <= opcode[5:3];

            end

        endcase

    end



    `READ_ALIGNED_DISP: begin

        if(disp_cache[0]) begin

            addr <= addr + {{8{current_byte[7]}}, current_byte};
            IP   <= IP + 1'b1;

        end
        elsebegin

            addr <= addr + {next_byte, current_byte};
            IP   <= IP + 2'h2;

        end

        read  <= 1'b1;
        state <= `READ_DATA;

    end


    `FETCH_MODRM: begin


        op1   <= op1t;
        op2   <= op2t;
        cs    <= sege;
        modrm <= next_byte;

        if(next_byte[7:6] == 2'b11) begin

            state <= `EXECUTE;

        end elsebegin

            case (disp)


                2'b01: begin

                    addr    <= addrx + {{8{current_byte[7]}}, current_byte};
                    state   <= `READ_DATA;
                    read    <= 1'b1;
                    IP      <= IP + 1'b1;

                end


                2'b10: begin

                    addr    <= addrx + current_byte;
                    state   <= `READ_UNALIGNED;
                    IP      <= IP + 2'h2;

                end


                default: begin

                    read    <= 1'b1;
                    addr    <= addrx;
                    state   <= `READ_DATA;

                end

            endcase

        end
    end


    `READ_UNALIGNED: begin

        state       <= `READ_DATA;
        read        <= 1'b1;
        addr[15:8]  <= addr[15:8] + next_byte;

    end


    `READ_DATA: begin

        if(opcode[0]) begin

            if(addr[0]) begin

                if (opcode[1]) op2 <= i_data[15:8];
                          else op1 <= i_data[15:8];

                addr  <= addr + 1'b1;
                state <= `READ_DATA_16;

            end elsebegin

                if (opcode[1]) op2 <= i_data[15:0];
                          else op1 <= i_data[15:0];

                state <= `EXECUTE;

            end

        end elsebegin

            if (opcode[1]) op2 <= current_byte;
                      else op1 <= current_byte;

            state <= `EXECUTE;

        end

    end


    `READ_DATA_16: begin

        if (opcode[1]) op2[15:8] <= i_data[7:0];
                  else op1[15:8] <= i_data[7:0];

        addr  <= addr - 1'b1;
        state <= `EXECUTE;

    end


    `EXECUTE: begin

        casex(opcode)


            8'b00_xxx0xx: begin

                wreg_bit <= alu_bits;
                wrdata   <= alu_res;
                regdata  <= alu_res;
                FLAGS    <= alu_flag;
                
                if(alu_mode == `ALU_CMP) 
                begin read <= 1'b0; state <= `DECODE; end
                
                else if(opcode[1])
                begin wreg_num <= modrm[5:3]; wreg <= 1'b1; read <= 1'b0; state <= `DECODE; end

                else begin

                    if(modrm[7:6] == 2'b11)
                    begin wreg_num <= modrm[2:0]; wreg <= 1'b1; read <= 1'b0; state <= `DECODE; end
                    elsebegin state <= `WRITE; next_state <= `DECODE; end

                end

            end
            

            8'b10_000_0xx: begin
            
                wreg_bit <= alu_bits;
                alu_mode <= modrm[5:3];
                op1      <= opcode[1] ? op2 : op1;
                op2      <= current_byte;
                read     <= 1'b0;

                
                
            
            end

        endcase

    end




    

    `WRITE: begin

        o_wr  <= 1'b1;
        wreg  <= 1'b0;

        if(wreg_bit) begin

             if(addr[0])
             begin o_data <= {wrdata[7:0], i_data[7:0]}; state <= `WRITE_16; end
             elsebegin o_data <= wrdata; state <= `END_OPCODE; end

        end
        else begin

            if (addr[0])o_data <= {wrdata[7:0],  i_data[7:0]};
                    elseo_data <= {i_data[15:8], wrdata[7:0]};

            state <= `END_OPCODE;

        end

    end


    `WRITE_16:  begin o_wr <= 1'b0; addr <= addr + 1'b1; state <= `WRITE_16E; end
    `WRITE_16E: begin o_wr <= 1'b1; o_data <= {i_data[15:8], wrdata[15:8]}; state <= `END_OPCODE; end    
    `END_OPCODE: begin o_wr <= 1'b0; read = 1'b0; state <= next_state; end

    endcase
end












always @(negedge clock) begin

    if (wreg) begin

        if (wreg_bit)

            case (wreg_num)

                3'b000: AX <= regdata;
                3'b001: CX <= regdata;
                3'b010: DX <= regdata;
                3'b011: BX <= regdata;
                3'b100: SP <= regdata;
                3'b101: BP <= regdata;
                3'b110: SI <= regdata;
                3'b111: DI <= regdata;

            endcase

        else

            case (wreg_num)

                3'b000: AX[7:0] <= regdata[7:0];
                3'b001: CX[7:0] <= regdata[7:0];
                3'b010: DX[7:0] <= regdata[7:0];
                3'b011: BX[7:0] <= regdata[7:0];
                3'b100: AX[15:8] <= regdata[7:0];
                3'b101: CX[15:8] <= regdata[7:0];
                3'b110: DX[15:8] <= regdata[7:0];
                3'b111: BX[15:8] <= regdata[7:0];

            endcase

    end

end

endmodule
module processor(

    input   wire            clock,
    input   wire            locked,
    input   wire            m_ready,
    output  wire    [19:0]  o_addr,
    input   wire    [15:0]  i_data,
    output  reg     [15:0]  o_data,
    output  reg             o_wr

);


`define DECODE              3'h0
`define FETCH_MODRM         3'h1
`define READ_UNALIGNED      3'h2
`define READ_ALIGNED_DISP   3'h3
`define READ_DATA           3'h4
`define READ_DATA_16        3'h5
`define EXECUTE             3'h6
`define WRITE               3'h7
`define WRITE_16            4'h8
`define WRITE_16E           4'h9
`define END_OPCODE          4'hA

`define ALU_ADD             3'h0
`define ALU_OR              3'h1
`define ALU_ADC             3'h2
`define ALU_SBB             3'h3
`define ALU_AND             3'h4
`define ALU_SUB             3'h5
`define ALU_XOR             3'h6
`define ALU_CMP             3'h7





assign o_addr = read ? {cs[15:0], 4'h0} + addr :
                       {CS[15:0], 4'h0} + IP;

initial o_data = 16'h0000;








reg     [15:0]    AX = 16'h3344;
reg     [15:0]    CX = 16'h2200;
reg     [15:0]    DX = 16'h0000;
reg     [15:0]    BX = 16'h0010;
reg     [15:0]    SP = 16'h0000;
reg     [15:0]    BP = 16'h0000;
reg     [15:0]    SI = 16'h2001;
reg     [15:0]    DI = 16'h0000;


reg     [15:0]    ES = 16'h0000;
reg     [15:0]    CS = 16'h0000;
reg     [15:0]    SS = 16'h0000;
reg     [15:0]    DS = 16'h0000;




reg     [11:0] FLAGS = 12'h000;
reg     [15:0]    IP = 16'h0000;





reg     [3:0]       state = `DECODE;
reg     [3:0]       next_state;
reg     [3:0]       micro;
reg     [15:0]      cs;
reg     [15:0]      addr;

reg         read = 1'b0;
reg         wreg = 1'b0;
reg         wreg_bit = 1'b0;
reg [2:0]   wreg_num = 3'h0;
reg [15:0]  wrdata = 16'h0000;
reg [15:0]  regdata = 16'h0000;









wire    [7:0]   current_byte = o_addr[0] ? i_data[15:8] : i_data[7:0];
wire    [7:0]   next_byte    = o_addr[0] ? i_data[7:0] : i_data[15:8];

wire            state_decode = state == `DECODE;
reg     [15:0]  opcode_cache = 8'h00;
wire    [7:0]   opcode       = state_decode ? current_byte : opcode_cache;


reg             opcode_modrm;



always @* begin




    casex (opcode)

        8'b00_xxx0xx,
        8'b10_00xxxx,
        8'b11_00000x,
        8'b11_0001xx,
        8'b11_0100xx,
        8'b11_011xxx,
        8'b11_11x11x:
            opcode_modrm = 1'b1;
        default:
            opcode_modrm = 1'b0;

    endcase

end




reg             seg_overlap;
reg             seg_overlap_cache;
reg     [1:0]   seg_number = 2'h3;
reg     [1:0]   seg_number_cache;

reg     [1:0]   disp;
reg     [1:0]   disp_cache;
reg     [7:0]   modrm;
reg     [15:0]  segp;
reg     [15:0]  sege;
reg     [15:0]  addrx;
reg     [15:0]  op1t;
reg     [15:0]  op1;
reg     [15:0]  op2t;
reg     [15:0]  op2;

wire    [15:0]  si_bx = SI + BX;
wire    [15:0]  di_bx = DI + BX;
wire    [15:0]  si_bp = SI + BP;
wire    [15:0]  di_bp = DI + BP;


wire            seg_override = (state_decode ? seg_overlap : seg_overlap_cache);
wire    [1:0]   seg_id       = (state_decode ? seg_number  : seg_number_cache);


always @* begin


    case (seg_id)

        3'h0: segp = ES;
        3'h1: segp = CS;
        3'h2: segp = SS;
        3'h3: segp = DS;

    endcase


    casex (next_byte)

        8'b00_xxx_11x: sege = seg_override ? segp : DS;
        8'bxx_xxx_x0x: sege = seg_override ? segp : DS;
        8'bxx_xxx_110: sege = seg_override ? segp : SS;
        8'bxx_xxx_01x: sege = seg_override ? segp : SS;
        default:       sege = DS;

    endcase


    casex (next_byte)

        8'bxx_xxx_000: addrx = si_bx;
        8'bxx_xxx_001: addrx = di_bx;
        8'bxx_xxx_010: addrx = si_bp;
        8'bxx_xxx_011: addrx = di_bp;
        8'bxx_xxx_100: addrx = SI;
        8'bxx_xxx_101: addrx = DI;
        8'b00_xxx_110: addrx = 16'h0000;
        8'bxx_xxx_110: addrx = BP;
        8'bxx_xxx_111: addrx = BX;

    endcase


    casex (next_byte)

        8'b01_xxx_xxx: disp = 2'b01;
        8'b00_xxx_110: disp = 2'b10;
        8'b10_xxx_xxx: disp = 2'b10;
        default:       disp = 2'b00;

    endcase


    case (opcode[1] ? next_byte[5:3] : next_byte[2:0])

        3'b000: op1t = opcode[0] ? AX : AX[7:0];
        3'b001: op1t = opcode[0] ? CX : CX[7:0];
        3'b010: op1t = opcode[0] ? DX : DX[7:0];
        3'b011: op1t = opcode[0] ? BX : BX[7:0];
        3'b100: op1t = opcode[0] ? SP : AX[15:8];
        3'b101: op1t = opcode[0] ? BP : CX[15:8];
        3'b110: op1t = opcode[0] ? SI : DX[15:8];
        3'b111: op1t = opcode[0] ? DI : BX[15:8];

    endcase


    case (opcode[1] ? next_byte[2:0] : next_byte[5:3])

        3'b000: op2t = opcode[0] ? AX : AX[7:0];
        3'b001: op2t = opcode[0] ? CX : CX[7:0];
        3'b010: op2t = opcode[0] ? DX : DX[7:0];
        3'b011: op2t = opcode[0] ? BX : BX[7:0];
        3'b100: op2t = opcode[0] ? SP : AX[15:8];
        3'b101: op2t = opcode[0] ? BP : CX[15:8];
        3'b110: op2t = opcode[0] ? SI : DX[15:8];
        3'b111: op2t = opcode[0] ? DI : BX[15:8];

    endcase

end





reg     [2:0]  alu_mode;
reg     [16:0] alu_res;
reg     [11:0] alu_flag;
reg            alu_bits;

wire    alu_parity = alu_res[7] ^ alu_res[6] ^ alu_res[5] ^
                            alu_res[4] ^ alu_res[3] ^ alu_res[2] ^
                            alu_res[1] ^ alu_res[0] ^ 1'b1;

wire    alu_zero8   = alu_res[7:0]  == 8'h00;
wire    alu_zero16  = alu_res[15:0] == 16'h0000;
wire    alu_aux_add = ((op1[3] | op2[3]) & !alu_res[3]) | (op1[3]*op2[3]*alu_res[3]);
wire    alu_aux_sub = ((op2[3] ^ alu_res[3]) & !op1[3]) | (op2[3] & alu_res[3]);
wire    alu_overflow_add8  = (op1[7]  ^ op2[7]   ^ 1'b1) & (op1[7]  ^ alu_res[7]);
wire    alu_overflow_sub8  = (op1[7]  ^ op2[7]         ) & (op1[7]  ^ alu_res[7]);
wire    alu_overflow_add16 = (op1[15] ^ op2[15]  ^ 1'b1) & (op1[15] ^ alu_res[15]);
wire    alu_overflow_sub16 = (op1[15] ^ op2[15]        ) & (op1[15] ^ alu_res[15]);

always @* begin


    case (alu_mode)

        `ALU_ADD: alu_res = op1 + op2;
        `ALU_OR:  alu_res = op1 | op2;
        `ALU_ADC: alu_res = op1 + op2 + FLAGS[0];
        `ALU_SBB: alu_res = op1 - op2 - FLAGS[0];
        `ALU_AND: alu_res = op1 & op2;
        `ALU_SUB, `ALU_CMP: alu_res = op1 - op2;
        `ALU_XOR: alu_res = op1 ^ op2;

    endcase


    case (alu_mode)

        `ALU_ADD, `ALU_ADC: alu_flag = {
alu_bits ? alu_overflow_add16 : alu_overflow_add8,
FLAGS[10:8],
alu_bits ? alu_res[15] : alu_res[7],
alu_bits ? alu_zero16 : alu_zero8,
1'b0,
alu_aux_add,
1'b0,
alu_parity,
1'b1,
alu_bits ? alu_res[16] : alu_res[8]
        };

        `ALU_SBB, `ALU_SUB, `ALU_CMP: alu_flag = {
alu_bits ? alu_overflow_sub16 : alu_overflow_sub8,
FLAGS[10:8],
alu_bits ? alu_res[15] : alu_res[7],
alu_bits ? alu_zero16 : alu_zero8,
1'b0,
alu_aux_sub,
1'b0,
alu_parity,
1'b1,
alu_bits ? alu_res[16] : alu_res[8]
        };

        `ALU_OR, `ALU_AND, `ALU_XOR: alu_flag = {
1'b0,
FLAGS[10:8],
alu_bits ? alu_res[15] : alu_res[7],
alu_bits ? alu_zero16 : alu_zero8,
1'b0,
FLAGS[4],
1'b0,
alu_parity,
1'b1,
1'b0
        };

    endcase

end





always @(posedge clock) begin

    case (state)


    `DECODE: begin

        wreg    <= 1'b0;
        o_wr    <= 1'b0;
        micro   <= 1'b0;

        casex (opcode)

            8'b001x_x110:begin

                seg_overlap <= 1'b1;
                seg_number  <= current_byte[4:3];
                IP          <= IP + 1'b1;

            end







            default:begin

                if(opcode_modrm) begin

                    if(IP[0]) begin

                        state <= `FETCH_MODRM;

                    end else begin


                        op1  <= op1t;
                        op2  <= op2t;
                        cs   <= sege;
                        addr <= addrx;
                        disp_cache <= disp;
                        modrm <= next_byte;

                        if(next_byte[7:6] == 2'b11) begin

                            state <= `EXECUTE;

                        end elsecase (disp)


                            2'b01, 2'b10: state <= `READ_ALIGNED_DISP;


                            default: begin

                                read    <= 1'b1;
                                state   <= `READ_DATA;

                            end

                        endcase

                    end

                    IP <= IP + 2'h2;


                end else begin

                    state   <= `EXECUTE;
                    IP      <= IP + 1'b1;

                end


                opcode_cache <= current_byte;


                seg_overlap_cache   <= seg_overlap;
                seg_number_cache    <= seg_number;


                seg_overlap         <= 1'b0;
                seg_number          <= 2'h3;


                alu_bits  <= opcode[0];
                alu_mode  <= opcode[5:3];

            end

        endcase

    end



    `READ_ALIGNED_DISP: begin

        if(disp_cache[0]) begin

            addr <= addr + {{8{current_byte[7]}}, current_byte};
            IP   <= IP + 1'b1;

        end
        elsebegin

            addr <= addr + {next_byte, current_byte};
            IP   <= IP + 2'h2;

        end

        read  <= 1'b1;
        state <= `READ_DATA;

    end


    `FETCH_MODRM: begin


        op1   <= op1t;
        op2   <= op2t;
        cs    <= sege;
        modrm <= next_byte;

        if(next_byte[7:6] == 2'b11) begin

            state <= `EXECUTE;

        end elsebegin

            case (disp)


                2'b01: begin

                    addr    <= addrx + {{8{current_byte[7]}}, current_byte};
                    state   <= `READ_DATA;
                    read    <= 1'b1;
                    IP      <= IP + 1'b1;

                end


                2'b10: begin

                    addr    <= addrx + current_byte;
                    state   <= `READ_UNALIGNED;
                    IP      <= IP + 2'h2;

                end


                default: begin

                    read    <= 1'b1;
                    addr    <= addrx;
                    state   <= `READ_DATA;

                end

            endcase

        end
    end


    `READ_UNALIGNED: begin

        state       <= `READ_DATA;
        read        <= 1'b1;
        addr[15:8]  <= addr[15:8] + next_byte;

    end


    `READ_DATA: begin

        if(opcode[0]) begin

            if(addr[0]) begin

                if (opcode[1]) op2 <= i_data[15:8];
                          else op1 <= i_data[15:8];

                addr  <= addr + 1'b1;
                state <= `READ_DATA_16;

            end elsebegin

                if (opcode[1]) op2 <= i_data[15:0];
                          else op1 <= i_data[15:0];

                state <= `EXECUTE;

            end

        end elsebegin

            if (opcode[1]) op2 <= current_byte;
                      else op1 <= current_byte;

            state <= `EXECUTE;

        end

    end


    `READ_DATA_16: begin

        if (opcode[1]) op2[15:8] <= i_data[7:0];
                  else op1[15:8] <= i_data[7:0];

        addr  <= addr - 1'b1;
        state <= `EXECUTE;

    end


    `EXECUTE: begin

        casex(opcode)


            8'b00_xxx0xx: begin

                wreg_bit <= alu_bits;
                wrdata   <= alu_res;
                regdata  <= alu_res;
                FLAGS    <= alu_flag;
                
                if(alu_mode == `ALU_CMP) 
                begin read <= 1'b0; state <= `DECODE; end
                
                else if(opcode[1])
                begin wreg_num <= modrm[5:3]; wreg <= 1'b1; read <= 1'b0; state <= `DECODE; end

                else begin

                    if(modrm[7:6] == 2'b11)
                    begin wreg_num <= modrm[2:0]; wreg <= 1'b1; read <= 1'b0; state <= `DECODE; end
                    elsebegin state <= `WRITE; next_state <= `DECODE; end

                end

            end
            

            8'b10_000_0xx: begin
            
                wreg_bit <= alu_bits;
                alu_mode <= modrm[5:3];
                op1      <= opcode[1] ? op2 : op1;
                op2      <= current_byte;
                read     <= 1'b0;

                
                
            
            end

        endcase

    end




    

    `WRITE: begin

        o_wr  <= 1'b1;
        wreg  <= 1'b0;

        if(wreg_bit) begin

             if(addr[0])
             begin o_data <= {wrdata[7:0], i_data[7:0]}; state <= `WRITE_16; end
             elsebegin o_data <= wrdata; state <= `END_OPCODE; end

        end
        else begin

            if (addr[0])o_data <= {wrdata[7:0],  i_data[7:0]};
                    elseo_data <= {i_data[15:8], wrdata[7:0]};

            state <= `END_OPCODE;

        end

    end


    `WRITE_16:  begin o_wr <= 1'b0; addr <= addr + 1'b1; state <= `WRITE_16E; end
    `WRITE_16E: begin o_wr <= 1'b1; o_data <= {i_data[15:8], wrdata[15:8]}; state <= `END_OPCODE; end    
    `END_OPCODE: begin o_wr <= 1'b0; read = 1'b0; state <= next_state; end

    endcase
end












always @(negedge clock) begin

    if (wreg) begin

        if (wreg_bit)

            case (wreg_num)

                3'b000: AX <= regdata;
                3'b001: CX <= regdata;
                3'b010: DX <= regdata;
                3'b011: BX <= regdata;
                3'b100: SP <= regdata;
                3'b101: BP <= regdata;
                3'b110: SI <= regdata;
                3'b111: DI <= regdata;

            endcase

        else

            case (wreg_num)

                3'b000: AX[7:0] <= regdata[7:0];
                3'b001: CX[7:0] <= regdata[7:0];
                3'b010: DX[7:0] <= regdata[7:0];
                3'b011: BX[7:0] <= regdata[7:0];
                3'b100: AX[15:8] <= regdata[7:0];
                3'b101: CX[15:8] <= regdata[7:0];
                3'b110: DX[15:8] <= regdata[7:0];
                3'b111: BX[15:8] <= regdata[7:0];

            endcase

    end

end

endmodule