data/full_repos/permissive/166661632/p5/p5/Dpipe.v
data/verilator_xmls/76199a3b-427f-472a-b7a1-a81f9460f9a1.xml
module Dpipe (clk,clr,en,
				instr_i,pc8_i,
				instr_d,pc8_d);
input clk,clr,en;
input [31:0] instr_i,pc8_i;
output reg [31:0]instr_d,pc8_d;

initial begin
	instr_d<=0; pc8_d<=0;
end

always@(posedge clk)
	begin
		if(clr)
			begin
				instr_d<=0; pc8_d<=0;
			end
		else if(en)
			begin
				instr_d<=instr_d; pc8_d<=pc8_d;
			end
		else 
			begin
				instr_d<=instr_i; pc8_d<=pc8_i;
			end
	end
endmodule
module Dpipe (clk,clr,en,
				instr_i,pc8_i,
				instr_d,pc8_d);

input clk,clr,en;
input [31:0] instr_i,pc8_i;
output reg [31:0]instr_d,pc8_d;

initial begin
	instr_d<=0; pc8_d<=0;
end

always@(posedge clk)
	begin
		if(clr)
			begin
				instr_d<=0; pc8_d<=0;
			end
		else if(en)
			begin
				instr_d<=instr_d; pc8_d<=pc8_d;
			end
		else 
			begin
				instr_d<=instr_i; pc8_d<=pc8_i;
			end
	end
endmodule