data/full_repos/permissive/104053853/digitron.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/104053853/digitron.v:22: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'frequency_divider\'\nmodule frequency_divider (input clock,\n       ^~~~~~~~~~~~~~~~~\n                                                                     : ... Top module \'hello_printer\'\nmodule hello_printer (input switch,\n       ^~~~~~~~~~~~~\n                                                                     : ... Top module \'fin_printer\'\nmodule fin_printer (input switch,\n       ^~~~~~~~~~~\n                                                                     : ... Top module \'digit_printer\'\nmodule digit_printer (input switch,\n       ^~~~~~~~~~~~~\n                                                                     : ... Top module \'bi_printer\'\nmodule bi_printer (input [7:0] seq1,\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module hello_printer (input switch,
                      input clock,
                      output reg [7:0] seq,
                      output reg [7:0] an);
parameter character_h = 8'b10010001,
          character_e = 8'b01100001,
          character_l = 8'b11100011,
          character_o = 8'b00000011;
parameter A0 = 8'b11111110,
          A1 = 8'b11111101,
          A2 = 8'b11111011,
          A3 = 8'b11110111,
          A4 = 8'b11101111;

reg [2:0] count;

initial
begin
    count = 0;
end

always @ (posedge clock)
begin
  if (switch)
  begin
    case (count)
    0: begin seq <= character_h; an <= A0; end
    1: begin seq <= character_e; an <= A1; end
    2: begin seq <= character_l; an <= A2; end
    3: begin seq <= character_l; an <= A3; end
    4: begin seq <= character_o; an <= A4; end
    default: begin seq <= character_h; an <= A0; end
    endcase
    if (count == 5) count <= 0; else count <= count + 1;


  end
  else
  begin
    seq <= 8'b11111111;
    an <= 8'b11111111;
  end
end
endmodule
module hello_printer (input switch,
                      input clock,
                      output reg [7:0] seq,
                      output reg [7:0] an);

parameter character_h = 8'b10010001,
          character_e = 8'b01100001,
          character_l = 8'b11100011,
          character_o = 8'b00000011;
parameter A0 = 8'b11111110,
          A1 = 8'b11111101,
          A2 = 8'b11111011,
          A3 = 8'b11110111,
          A4 = 8'b11101111;

reg [2:0] count;

initial
begin
    count = 0;
end

always @ (posedge clock)
begin
  if (switch)
  begin
    case (count)
    0: begin seq <= character_h; an <= A0; end
    1: begin seq <= character_e; an <= A1; end
    2: begin seq <= character_l; an <= A2; end
    3: begin seq <= character_l; an <= A3; end
    4: begin seq <= character_o; an <= A4; end
    default: begin seq <= character_h; an <= A0; end
    endcase
    if (count == 5) count <= 0; else count <= count + 1;


  end
  else
  begin
    seq <= 8'b11111111;
    an <= 8'b11111111;
  end
end
endmodule