data/full_repos/permissive/141582589/src/common_rtl/video/vout_pro.v
'utf-8' codec can't decode bytes in position 186-187: invalid continuation byte
1: b'%Error: data/full_repos/permissive/141582589/src/common_rtl/video/vout_pro.v:70: Cannot find file containing module: \'vout_frame_buffer_ctrl\'\nvout_frame_buffer_ctrl\n^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141582589/src/common_rtl/video,data/full_repos/permissive/141582589/vout_frame_buffer_ctrl\n             data/full_repos/permissive/141582589/src/common_rtl/video,data/full_repos/permissive/141582589/vout_frame_buffer_ctrl.v\n             data/full_repos/permissive/141582589/src/common_rtl/video,data/full_repos/permissive/141582589/vout_frame_buffer_ctrl.sv\n             vout_frame_buffer_ctrl\n             vout_frame_buffer_ctrl.v\n             vout_frame_buffer_ctrl.sv\n             obj_dir/vout_frame_buffer_ctrl\n             obj_dir/vout_frame_buffer_ctrl.v\n             obj_dir/vout_frame_buffer_ctrl.sv\n%Error: data/full_repos/permissive/141582589/src/common_rtl/video/vout_pro.v:104: Cannot find file containing module: \'scaler\'\nscaler#\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/141582589/src/common_rtl/video/vout_pro.v:125: Operator GT expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'out_buff0_wrusedw\' generates 9 bits.\n                                                                                        : ... In instance vout_pro\nassign scaler_fifo_afull = (out_buff0_wrusedw > buff0_depth  - C0);\n                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/141582589/src/common_rtl/video/vout_pro.v:133: Cannot find file containing module: \'lite_fifo\'\nlite_fifo#\n^~~~~~~~~\n%Error: data/full_repos/permissive/141582589/src/common_rtl/video/vout_pro.v:165: Cannot find file containing module: \'YUV422_2YUV444\'\nYUV422_2YUV444 YUV422_2YUV444_u1(\n^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module vout_pro
#(
	parameter MEM_DATA_BITS = 64,
	parameter WITDH_2K = 0
)
   (
	input rst_n,
	input pixel_clk,
	input vs,
	input pixel_rd_req,
	output[23:0] pixel_ycbcr,
	input mem_clk,
	output  rd_burst_req,
	output [9:0] rd_burst_len,

	output [26:0] rd_burst_addr,
	input rd_burst_data_valid,
	input[MEM_DATA_BITS - 1:0] rd_burst_data,
	input burst_finish,
	input scaler_clk,
	input[11:0] s_width,
	input[11:0] s_height,
	input[11:0] t_width,
	input[11:0] t_height,
	input[15:0] K_h,
	input[15:0] K_v,
	input[11:0] wr_max_line,
	input[1:0] base_addr,
	input[1:0] wr_frame_addr,
	input s_wr_done
);

localparam buff0_depth = 512;
localparam scaler_en = 1'b0;
localparam C0 = 60;

wire out_buff0_wrreq;
wire vout_rd_req;
wire fifo_rdempty;
wire out_buff0_wrfull;
wire[15:0] vout_data;
wire[15:0] out_buff0_data;
wire out_buff0_rdclk;
wire[15:0] out_buff0_q;
wire out_buff0_rdreq;
wire out_buff0_aclr;
wire[8 : 0] out_buff0_wrusedw;
reg pixel_rd_req_d0 = 1'b0;
reg vs_d0  = 1'b0 ;
reg vs_d1 = 1'b0;
reg frame_flag  = 1'b0;
wire scaler_rd_req;
wire scaler_wr_req;
wire scaler_fifo_afull;
wire scaler_fifo_aempty;
wire[15:0] scaler_yc_data_in;
wire[15:0] scaler_yc_data_out;
wire[23:0] scl_out_buf_q;
wire scl_out_buf_rdempty;
wire[4:0] scl_out_buf_wrusedw;
wire line_end;
wire out_buff0_wrclk;

assign vout_rd_req = scaler_rd_req;


vout_frame_buffer_ctrl
#
(
	.MEM_DATA_BITS(MEM_DATA_BITS),
	.WITDH_2K(WITDH_2K)
) vout_frame_buffer_ctrl_m0(
	.rst_n(rst_n),
	.vout_clk(scaler_clk),
	.vout_vs(vs),
	.vout_rd_req(vout_rd_req),
	.vout_data(vout_data),
	.vout_width(s_width),
	.vout_height(s_height),
	.fifo_rdempty(fifo_rdempty),
	.mem_clk(mem_clk),
	.rd_burst_req(rd_burst_req),
	.rd_burst_len(rd_burst_len),
	.rd_burst_addr(rd_burst_addr),
	.rd_burst_data_valid(rd_burst_data_valid),
	.rd_burst_data(rd_burst_data),
	.burst_finish(burst_finish),
	.wr_max_line(wr_max_line),
	.base_addr(base_addr),
	.wr_frame_addr(wr_frame_addr),

	.s_wr_done(s_wr_done)
);




assign scaler_fifo_aempty = fifo_rdempty;
assign scaler_yc_data_in = vout_data;

scaler#
(
	.WITDH_2K(WITDH_2K)
) scaler_m0(
	.sys_clk(scaler_clk),
	.rst_n(rst_n),
	.fifo_aempty(scaler_fifo_aempty),
	.rd_req(scaler_rd_req),
	.yc_data_in(scaler_yc_data_in),
	.frame_flag(frame_flag),
	.fifo_afull(scaler_fifo_afull),
	.wr_req(scaler_wr_req),
	.yc_data_out(scaler_yc_data_out),
	.s_width(s_width),
	.s_height(s_height),
	.t_width(t_width),
	.t_height(t_height),
	.K_h(K_h),
	.K_v(K_v)
);

assign scaler_fifo_afull = (out_buff0_wrusedw > buff0_depth  - C0);
assign out_buff0_wrreq = scaler_wr_req;
assign out_buff0_data = scaler_yc_data_out;
assign out_buff0_wrclk = scaler_clk;
assign out_buff0_rdclk = pixel_clk;
assign out_buff0_rdreq = pixel_rd_req;
assign out_buff0_aclr = frame_flag;

lite_fifo#
(
	.COMMON_CLOCK(0),
	.ADDR_WIDTH(9),
	.DATA_WIDTH(16)
) 	out_buff0 (
	.wrclk (out_buff0_wrclk),
	.rdreq (out_buff0_rdreq),
	.aclr (out_buff0_aclr),
	.rdclk (out_buff0_rdclk),
	.wrreq (out_buff0_wrreq),
	.data (out_buff0_data),
	.rdempty (),
	.wrusedw (out_buff0_wrusedw),
	.wrfull (),
	.q (out_buff0_q),
	.rdusedw ()
	); 



always@(posedge pixel_clk)
begin
	pixel_rd_req_d0 <= pixel_rd_req;
end
always@(posedge scaler_clk)
begin
	vs_d0 <= vs;
	vs_d1 <= vs_d0;
	frame_flag <= vs_d0 && ~vs_d1;
end

YUV422_2YUV444 YUV422_2YUV444_u1(
   .clk  (pixel_clk),
   .y_i  (out_buff0_q[15:8]  ),
   .cbcr_i (out_buff0_q[7:0]),
   .de_i  (pixel_rd_req_d0),
   .hs_i  (),
   .vs_i  (),
   .y_o  (pixel_ycbcr[23:16]), 
   .cb_o (pixel_ycbcr[15:8]),
   .cr_o (pixel_ycbcr[7:0]),
   .de_o (),
   .hs_o (),
   .vs_o ()
   );
   
endmodule
module vout_pro
#(
	parameter MEM_DATA_BITS = 64,
	parameter WITDH_2K = 0
)
   (
	input rst_n,
	input pixel_clk,
	input vs,
	input pixel_rd_req,
	output[23:0] pixel_ycbcr,
	input mem_clk,
	output  rd_burst_req,
	output [9:0] rd_burst_len,

	output [26:0] rd_burst_addr,
	input rd_burst_data_valid,
	input[MEM_DATA_BITS - 1:0] rd_burst_data,
	input burst_finish,
	input scaler_clk,
	input[11:0] s_width,
	input[11:0] s_height,
	input[11:0] t_width,
	input[11:0] t_height,
	input[15:0] K_h,
	input[15:0] K_v,
	input[11:0] wr_max_line,
	input[1:0] base_addr,
	input[1:0] wr_frame_addr,
	input s_wr_done
);


localparam buff0_depth = 512;
localparam scaler_en = 1'b0;
localparam C0 = 60;

wire out_buff0_wrreq;
wire vout_rd_req;
wire fifo_rdempty;
wire out_buff0_wrfull;
wire[15:0] vout_data;
wire[15:0] out_buff0_data;
wire out_buff0_rdclk;
wire[15:0] out_buff0_q;
wire out_buff0_rdreq;
wire out_buff0_aclr;
wire[8 : 0] out_buff0_wrusedw;
reg pixel_rd_req_d0 = 1'b0;
reg vs_d0  = 1'b0 ;
reg vs_d1 = 1'b0;
reg frame_flag  = 1'b0;
wire scaler_rd_req;
wire scaler_wr_req;
wire scaler_fifo_afull;
wire scaler_fifo_aempty;
wire[15:0] scaler_yc_data_in;
wire[15:0] scaler_yc_data_out;
wire[23:0] scl_out_buf_q;
wire scl_out_buf_rdempty;
wire[4:0] scl_out_buf_wrusedw;
wire line_end;
wire out_buff0_wrclk;

assign vout_rd_req = scaler_rd_req;


vout_frame_buffer_ctrl
#
(
	.MEM_DATA_BITS(MEM_DATA_BITS),
	.WITDH_2K(WITDH_2K)
) vout_frame_buffer_ctrl_m0(
	.rst_n(rst_n),
	.vout_clk(scaler_clk),
	.vout_vs(vs),
	.vout_rd_req(vout_rd_req),
	.vout_data(vout_data),
	.vout_width(s_width),
	.vout_height(s_height),
	.fifo_rdempty(fifo_rdempty),
	.mem_clk(mem_clk),
	.rd_burst_req(rd_burst_req),
	.rd_burst_len(rd_burst_len),
	.rd_burst_addr(rd_burst_addr),
	.rd_burst_data_valid(rd_burst_data_valid),
	.rd_burst_data(rd_burst_data),
	.burst_finish(burst_finish),
	.wr_max_line(wr_max_line),
	.base_addr(base_addr),
	.wr_frame_addr(wr_frame_addr),

	.s_wr_done(s_wr_done)
);




assign scaler_fifo_aempty = fifo_rdempty;
assign scaler_yc_data_in = vout_data;

scaler#
(
	.WITDH_2K(WITDH_2K)
) scaler_m0(
	.sys_clk(scaler_clk),
	.rst_n(rst_n),
	.fifo_aempty(scaler_fifo_aempty),
	.rd_req(scaler_rd_req),
	.yc_data_in(scaler_yc_data_in),
	.frame_flag(frame_flag),
	.fifo_afull(scaler_fifo_afull),
	.wr_req(scaler_wr_req),
	.yc_data_out(scaler_yc_data_out),
	.s_width(s_width),
	.s_height(s_height),
	.t_width(t_width),
	.t_height(t_height),
	.K_h(K_h),
	.K_v(K_v)
);

assign scaler_fifo_afull = (out_buff0_wrusedw > buff0_depth  - C0);
assign out_buff0_wrreq = scaler_wr_req;
assign out_buff0_data = scaler_yc_data_out;
assign out_buff0_wrclk = scaler_clk;
assign out_buff0_rdclk = pixel_clk;
assign out_buff0_rdreq = pixel_rd_req;
assign out_buff0_aclr = frame_flag;

lite_fifo#
(
	.COMMON_CLOCK(0),
	.ADDR_WIDTH(9),
	.DATA_WIDTH(16)
) 	out_buff0 (
	.wrclk (out_buff0_wrclk),
	.rdreq (out_buff0_rdreq),
	.aclr (out_buff0_aclr),
	.rdclk (out_buff0_rdclk),
	.wrreq (out_buff0_wrreq),
	.data (out_buff0_data),
	.rdempty (),
	.wrusedw (out_buff0_wrusedw),
	.wrfull (),
	.q (out_buff0_q),
	.rdusedw ()
	); 



always@(posedge pixel_clk)
begin
	pixel_rd_req_d0 <= pixel_rd_req;
end
always@(posedge scaler_clk)
begin
	vs_d0 <= vs;
	vs_d1 <= vs_d0;
	frame_flag <= vs_d0 && ~vs_d1;
end

YUV422_2YUV444 YUV422_2YUV444_u1(
   .clk  (pixel_clk),
   .y_i  (out_buff0_q[15:8]  ),
   .cbcr_i (out_buff0_q[7:0]),
   .de_i  (pixel_rd_req_d0),
   .hs_i  (),
   .vs_i  (),
   .y_o  (pixel_ycbcr[23:16]), 
   .cb_o (pixel_ycbcr[15:8]),
   .cr_o (pixel_ycbcr[7:0]),
   .de_o (),
   .hs_o (),
   .vs_o ()
   );
   
endmodule