data/full_repos/permissive/169155753/source/measure.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/169155753/source/measure.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169155753/source,data/full_repos/permissive/169155753/defines.v\n             data/full_repos/permissive/169155753/source,data/full_repos/permissive/169155753/defines.v.v\n             data/full_repos/permissive/169155753/source,data/full_repos/permissive/169155753/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/169155753/source/measure.v:23: Define or directive not defined: \'`MAX_BCDCOUNT\'\n    reg [19:0] bcdcount_out = `MAX_BCDCOUNT;\n                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/measure.v:23: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    reg [19:0] bcdcount_out = `MAX_BCDCOUNT;\n                                           ^\n%Error: data/full_repos/permissive/169155753/source/measure.v:24: Define or directive not defined: \'`MAX_BCDCOUNT\'\n    reg [19:0] bcdcount_min = `MAX_BCDCOUNT;\n                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/measure.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    reg [19:0] bcdcount_min = `MAX_BCDCOUNT;\n                                           ^\n%Error: data/full_repos/permissive/169155753/source/measure.v:29: Define or directive not defined: \'`MAX_BCDCOUNT\'\n    reg [19:0] avg_counter_bcd_reg = `MAX_BCDCOUNT;\n                                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/measure.v:29: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    reg [19:0] avg_counter_bcd_reg = `MAX_BCDCOUNT;\n                                                  ^\n%Error: data/full_repos/permissive/169155753/source/measure.v:31: Define or directive not defined: \'`AVERAGE_BITS\'\n    reg [`AVERAGE_BITS-1:0] avg_loop;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/measure.v:63: Define or directive not defined: \'`CLOCK_DIVIDER\'\n            if (counter < `CLOCK_DIVIDER - 1) begin\n                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/measure.v:89: Define or directive not defined: \'`MAX_BCDCOUNT\'\n            bcdcount_out <= `MAX_BCDCOUNT;\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/measure.v:89: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            bcdcount_out <= `MAX_BCDCOUNT;\n                                         ^\n%Error: data/full_repos/permissive/169155753/source/measure.v:91: Define or directive not defined: \'`MAX_BCDCOUNT\'\n            bcdcount_min <= `MAX_BCDCOUNT;\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/measure.v:91: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            bcdcount_min <= `MAX_BCDCOUNT;\n                                         ^\n%Error: data/full_repos/permissive/169155753/source/measure.v:95: Define or directive not defined: \'`MAX_BCDCOUNT\'\n            avg_counter_bcd_reg <= `MAX_BCDCOUNT;\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/measure.v:95: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            avg_counter_bcd_reg <= `MAX_BCDCOUNT;\n                                                ^\n%Error: data/full_repos/permissive/169155753/source/measure.v:111: Define or directive not defined: \'`AVERAGE_SIZE\'\n                if (avg_loop == (`AVERAGE_SIZE - 1)) begin\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/measure.v:112: Define or directive not defined: \'`AVERAGE_BITS\'\n                    avg_counter_reg_avg <= (avg_counter_reg + avg_counter) >> `AVERAGE_BITS;\n                                                                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169155753/source/measure.v:112: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    avg_counter_reg_avg <= (avg_counter_reg + avg_counter) >> `AVERAGE_BITS;\n                                                                                           ^\n%Error: Exiting due to 18 error(s)\n'
module measure(
    input clock,
    input reset_counter,
    input sensor_trigger,
    input reset_bcdoutput,

    output [19:0] bcd_current,
    output [19:0] bcd_minimum,
    output [19:0] bcd_maximum,
    output [19:0] bcd_average
);
    wire [23:0] bcdcount;
    wire [23:0] avg_counter_bcd;
    wire avg_counter_ready;

    reg waiting;
    reg [8:0] counter;
    reg [24:0] raw_counter;
    reg counter_trigger = 0;
    reg reset_bcdcounter = 0;
    reg [19:0] bcdcount_out = `MAX_BCDCOUNT;
    reg [19:0] bcdcount_min = `MAX_BCDCOUNT;
    reg [19:0] bcdcount_max = 0;
    reg [19:0] avg_counter;
    reg [31:0] avg_counter_reg;
    reg [31:0] avg_counter_reg_avg;
    reg [19:0] avg_counter_bcd_reg = `MAX_BCDCOUNT;
    reg avg_counter_start;
    reg [`AVERAGE_BITS-1:0] avg_loop;

    bcdcounter bcdcounter(
        .trigger(counter_trigger),
        .reset(reset_bcdcounter),
        .bcdcount(bcdcount)
    );

    Binary_to_BCD #(
        .INPUT_WIDTH(20),
        .DECIMAL_DIGITS(6)
    ) Binary_to_BCD (
        .i_Clock(clock),
        .i_Start(avg_counter_start),
        .i_Binary(avg_counter_reg_avg[19:0]),
        .o_BCD(avg_counter_bcd),
        .o_DV(avg_counter_ready)
    );


    always @(posedge clock) begin
        if (reset_counter) begin
            raw_counter <= 0;
            counter <= 0;
            counter_trigger <= 0;
            reset_bcdcounter <= 1;
        end else begin
            raw_counter <= raw_counter + 1'b1;
            reset_bcdcounter <= 0;
            if (counter < `CLOCK_DIVIDER - 1) begin
                counter <= counter + 1'b1;
                counter_trigger <= 0;
            end else begin
                counter <= 0;
                counter_trigger <= 1;
            end
        end
    end



    always @(posedge counter_trigger or posedge reset_bcdcounter) begin
        if (reset_bcdcounter) begin
            avg_counter <= 0;
        end else begin
            avg_counter <= avg_counter + 1'b1;
        end
    end



    always @(posedge clock) begin
        if (reset_counter) begin
            waiting <= 1;
        end else if (reset_bcdoutput) begin
            bcdcount_out <= `MAX_BCDCOUNT;
            bcdcount_max <= 0;
            bcdcount_min <= `MAX_BCDCOUNT;
            avg_counter_reg_avg <= 0;
            avg_counter_reg <= 0;
            avg_loop <= 0;
            avg_counter_bcd_reg <= `MAX_BCDCOUNT;
        end else if (waiting && sensor_trigger) begin
            bcdcount_out <= bcdcount[23:4];
            if (avg_loop == 0) begin

                bcdcount_max <= bcdcount[23:4];
                bcdcount_min <= bcdcount[23:4];
            end else begin             
                if (bcdcount[23:4] < bcdcount_min) begin
                    bcdcount_min <= bcdcount[23:4];
                end
                if (bcdcount[23:4] > bcdcount_max) begin
                    bcdcount_max <= bcdcount[23:4];
                end
            end
            if (avg_counter != 0) begin
                if (avg_loop == (`AVERAGE_SIZE - 1)) begin
                    avg_counter_reg_avg <= (avg_counter_reg + avg_counter) >> `AVERAGE_BITS;
                    avg_counter_reg <= 0;
                    avg_loop <= 0;
                    avg_counter_start <= 1'b1;
                end else begin
                    avg_counter_reg <= avg_counter_reg + avg_counter;
                    avg_loop <= avg_loop + 1'b1;
                    avg_counter_start <= 1'b0;
                end
            end
            waiting <= 0;
        end
        if (avg_counter_ready) begin
            avg_counter_bcd_reg <= avg_counter_bcd[23:4];
        end
    end

    assign bcd_current = bcdcount_out;
    assign bcd_minimum = bcdcount_min;
    assign bcd_maximum = bcdcount_max;
    assign bcd_average = avg_counter_bcd_reg;

endmodule
module measure(
    input clock,
    input reset_counter,
    input sensor_trigger,
    input reset_bcdoutput,

    output [19:0] bcd_current,
    output [19:0] bcd_minimum,
    output [19:0] bcd_maximum,
    output [19:0] bcd_average
);

    wire [23:0] bcdcount;
    wire [23:0] avg_counter_bcd;
    wire avg_counter_ready;

    reg waiting;
    reg [8:0] counter;
    reg [24:0] raw_counter;
    reg counter_trigger = 0;
    reg reset_bcdcounter = 0;
    reg [19:0] bcdcount_out = `MAX_BCDCOUNT;
    reg [19:0] bcdcount_min = `MAX_BCDCOUNT;
    reg [19:0] bcdcount_max = 0;
    reg [19:0] avg_counter;
    reg [31:0] avg_counter_reg;
    reg [31:0] avg_counter_reg_avg;
    reg [19:0] avg_counter_bcd_reg = `MAX_BCDCOUNT;
    reg avg_counter_start;
    reg [`AVERAGE_BITS-1:0] avg_loop;

    bcdcounter bcdcounter(
        .trigger(counter_trigger),
        .reset(reset_bcdcounter),
        .bcdcount(bcdcount)
    );

    Binary_to_BCD #(
        .INPUT_WIDTH(20),
        .DECIMAL_DIGITS(6)
    ) Binary_to_BCD (
        .i_Clock(clock),
        .i_Start(avg_counter_start),
        .i_Binary(avg_counter_reg_avg[19:0]),
        .o_BCD(avg_counter_bcd),
        .o_DV(avg_counter_ready)
    );


    always @(posedge clock) begin
        if (reset_counter) begin
            raw_counter <= 0;
            counter <= 0;
            counter_trigger <= 0;
            reset_bcdcounter <= 1;
        end else begin
            raw_counter <= raw_counter + 1'b1;
            reset_bcdcounter <= 0;
            if (counter < `CLOCK_DIVIDER - 1) begin
                counter <= counter + 1'b1;
                counter_trigger <= 0;
            end else begin
                counter <= 0;
                counter_trigger <= 1;
            end
        end
    end



    always @(posedge counter_trigger or posedge reset_bcdcounter) begin
        if (reset_bcdcounter) begin
            avg_counter <= 0;
        end else begin
            avg_counter <= avg_counter + 1'b1;
        end
    end



    always @(posedge clock) begin
        if (reset_counter) begin
            waiting <= 1;
        end else if (reset_bcdoutput) begin
            bcdcount_out <= `MAX_BCDCOUNT;
            bcdcount_max <= 0;
            bcdcount_min <= `MAX_BCDCOUNT;
            avg_counter_reg_avg <= 0;
            avg_counter_reg <= 0;
            avg_loop <= 0;
            avg_counter_bcd_reg <= `MAX_BCDCOUNT;
        end else if (waiting && sensor_trigger) begin
            bcdcount_out <= bcdcount[23:4];
            if (avg_loop == 0) begin

                bcdcount_max <= bcdcount[23:4];
                bcdcount_min <= bcdcount[23:4];
            end else begin             
                if (bcdcount[23:4] < bcdcount_min) begin
                    bcdcount_min <= bcdcount[23:4];
                end
                if (bcdcount[23:4] > bcdcount_max) begin
                    bcdcount_max <= bcdcount[23:4];
                end
            end
            if (avg_counter != 0) begin
                if (avg_loop == (`AVERAGE_SIZE - 1)) begin
                    avg_counter_reg_avg <= (avg_counter_reg + avg_counter) >> `AVERAGE_BITS;
                    avg_counter_reg <= 0;
                    avg_loop <= 0;
                    avg_counter_start <= 1'b1;
                end else begin
                    avg_counter_reg <= avg_counter_reg + avg_counter;
                    avg_loop <= avg_loop + 1'b1;
                    avg_counter_start <= 1'b0;
                end
            end
            waiting <= 0;
        end
        if (avg_counter_ready) begin
            avg_counter_bcd_reg <= avg_counter_bcd[23:4];
        end
    end

    assign bcd_current = bcdcount_out;
    assign bcd_minimum = bcdcount_min;
    assign bcd_maximum = bcdcount_max;
    assign bcd_average = avg_counter_bcd_reg;

endmodule