data/full_repos/permissive/143597583/rtl/verilog/support/dpram.v
1: b"%Error: data/full_repos/permissive/143597583/rtl/verilog/support/dpram.v:23: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n rclk, rrst, rce, oe, raddr, do,\n                             ^~\n%Error: data/full_repos/permissive/143597583/rtl/verilog/support/dpram.v:42: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n output [dw-1:0] do;     \n                 ^~\n%Error: data/full_repos/permissive/143597583/rtl/verilog/support/dpram.v:62: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = mem[ra];\n        ^~\n%Error: Exiting due to 3 error(s)\n"
module dpram(

	rclk, rrst, rce, oe, raddr, do,
	wclk, wrst, wce, we, waddr, di
);




	parameter aw = 5;
	parameter dw = 16;





	input           rclk;
	input           rrst;
	input           rce;
	input           oe;
	input  [aw-1:0] raddr;
	output [dw-1:0] do;


	input          wclk;
	input          wrst;
	input          wce;
	input          we;
	input [aw-1:0] waddr;
	input [dw-1:0] di;

	reg [dw-1:0] mem [(1<<aw) -1:0];
	reg [aw-1:0] ra;


	always @(posedge rclk) begin
		if (rce) begin
			ra <= raddr;
		end
	end

	assign do = mem[ra];


	always @(posedge wclk) begin
		if (we && wce) begin
			mem[waddr] <= di;
		end
	end

endmodule
module dpram(

	rclk, rrst, rce, oe, raddr, do,
	wclk, wrst, wce, we, waddr, di
);





	parameter aw = 5;
	parameter dw = 16;





	input           rclk;
	input           rrst;
	input           rce;
	input           oe;
	input  [aw-1:0] raddr;
	output [dw-1:0] do;


	input          wclk;
	input          wrst;
	input          wce;
	input          we;
	input [aw-1:0] waddr;
	input [dw-1:0] di;

	reg [dw-1:0] mem [(1<<aw) -1:0];
	reg [aw-1:0] ra;


	always @(posedge rclk) begin
		if (rce) begin
			ra <= raddr;
		end
	end

	assign do = mem[ra];


	always @(posedge wclk) begin
		if (we && wce) begin
			mem[waddr] <= di;
		end
	end

endmodule