data/full_repos/permissive/211316121/lab6_3/cnt_74ls163.v
data/verilator_xmls/aa09922e-4dd0-4592-af34-5743cc443297.xml
module cnt_74ls163(
    input [3:0] load_time,
    input CP,
    input CLR,
    input LOAD,
    input P,
    input T,
    output reg [3:0] dataOut,
    output RCO
    );
    
    assign RCO = P & T & LOAD & dataOut[0] & dataOut[1] & dataOut[2] & dataOut[3];
    
    always@(posedge CP)
    begin
        if(~CLR)
            dataOut <= 4'b0000;
        else if(~LOAD)
            dataOut <= load_time;
        else if(P & T)
            dataOut <= dataOut + 1'b1;
        else
            dataOut <= dataOut;
    end
endmodule
module cnt_74ls163(
    input [3:0] load_time,
    input CP,
    input CLR,
    input LOAD,
    input P,
    input T,
    output reg [3:0] dataOut,
    output RCO
    );

    
    assign RCO = P & T & LOAD & dataOut[0] & dataOut[1] & dataOut[2] & dataOut[3];
    
    always@(posedge CP)
    begin
        if(~CLR)
            dataOut <= 4'b0000;
        else if(~LOAD)
            dataOut <= load_time;
        else if(P & T)
            dataOut <= dataOut + 1'b1;
        else
            dataOut <= dataOut;
    end
endmodule