data/full_repos/permissive/117026779/sim/Test_Memory.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Memory.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Memory.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Memory.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Memory.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Error: data/full_repos/permissive/117026779/sim/Test_Memory.v:100: syntax error, unexpected return, expecting IDENTIFIER\n    output [7:0] return;\n                 ^~~~~~\n%Error: data/full_repos/permissive/117026779/sim/Test_Memory.v:108: syntax error, unexpected \'=\', expecting TYPE-IDENTIFIER\n    return = out;\n           ^\n%Error: data/full_repos/permissive/117026779/sim/Test_Memory.v:112: syntax error, unexpected return, expecting TYPE-IDENTIFIER\n    if(return !== check)\n       ^~~~~~\n%Error: data/full_repos/permissive/117026779/sim/Test_Memory.v:131: syntax error, unexpected \'=\', expecting TYPE-IDENTIFIER\n    return = out;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Memory.v:145: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Memory.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Memory.v:201: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Memory.v:202: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: Exiting due to 4 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_Memory;

reg clk;
reg rst;
reg wr_cs;
reg wr_en;
reg rd_cs;
reg rd_en;
reg [7:0] in;
wire [7:0] out;
wire full;
wire empty;
wire overflow;
wire underflow;

FIFO #(.LENGTH(4), .WIDTH(8)) fifo (
    .clk(clk),
    .rst(rst),
    .wr_cs(wr_cs),
    .wr_en(wr_en),
    .rd_cs(rd_cs),
    .rd_en(rd_en),
    .overflow(overflow),
    .full(full),
    .empty(empty),
    .underflow(underflow),
    .out(out),
    .in(in)
);

task RESET;
begin
    rst = 0;
    clk = 0;
    
    wr_cs = 0;
    wr_en = 0;
    rd_cs = 0;
    rd_en = 0;
    
    #5
    rst = 1;
    #5
    rst = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
	end
end
endtask

task FIFO_PUSH;
	input [7:0] send;
begin
    wr_cs = 1;
    wr_en = 1;
    rd_cs = 0;
    rd_en = 0;
    in = send;    
    CLOCK(1);
    wr_cs = 0;
    wr_en = 0;
    in = 0;
end
endtask

task FIFO_POP;
    output [7:0] return;
    input [7:0] check;
begin
    wr_cs = 0;
    wr_en = 0;
    rd_cs = 1;
    rd_en = 1;
    CLOCK(1);
    return = out;
    rd_cs = 0;
    rd_en = 0;

    if(return !== check)
    begin
        $display("Error returned (0x%X) != check (0x%X)", return, check);
    end
end
endtask


task FIFO_PUSH_POP;
    input [7:0] send;
    output [7:0] return;
    input [7:0] check;
begin
    wr_cs = 1;
    wr_en = 1;
    rd_cs = 1;
    rd_en = 1;
    in = send;
    CLOCK(1);
    return = out;
    rd_cs = 0;
    rd_en = 0;
    wr_cs = 0;
    wr_en = 0;
end
endtask

parameter FULL_CYCLE = 32'd10_000_000;

reg [7:0] test_value;

initial begin
    #10
    #10
	RESET;
    CLOCK(1);
    FIFO_PUSH(8'h11);
    FIFO_PUSH(8'h22);
    FIFO_PUSH(8'h33);
    FIFO_PUSH(8'h44);
    
    FIFO_POP(test_value, 8'h11);
    FIFO_POP(test_value, 8'h22);
    FIFO_POP(test_value, 8'h33);
    FIFO_POP(test_value, 8'h44);
    CLOCK(5);



    FIFO_PUSH_POP(8'h66, test_value, 8'h66);
    FIFO_PUSH_POP(8'h77, test_value, 8'h77);
    FIFO_PUSH_POP(8'h88, test_value, 8'h88);
    FIFO_PUSH_POP(8'h99, test_value, 8'h99);

    if(underflow != 1)
    begin
        $display("underflow no work!"); 
    end

    FIFO_PUSH(8'h55);
    FIFO_PUSH(8'h66);
    FIFO_PUSH(8'h77);
    FIFO_PUSH(8'h88);

    FIFO_PUSH(8'h99);
    FIFO_PUSH(8'hAA);
    FIFO_PUSH(8'hBB);
    FIFO_PUSH(8'hCC);

    FIFO_POP(test_value, 8'h55);
    FIFO_POP(test_value, 8'h66);
    FIFO_POP(test_value, 8'h77);
    FIFO_POP(test_value, 8'h88);

    FIFO_PUSH(8'h99);
    FIFO_PUSH(8'hAA);
    FIFO_PUSH(8'hBB);
    FIFO_POP(test_value, 8'h99);
    FIFO_POP(test_value, 8'hAA);

    FIFO_PUSH(8'hCC);
    FIFO_PUSH(8'hDD);
    FIFO_PUSH(8'hEE);
    FIFO_POP(test_value, 8'hBB);
    FIFO_POP(test_value, 8'hCC);
    FIFO_POP(test_value, 8'hDD);
    FIFO_POP(test_value, 8'hEE);

    CLOCK(10);
    #10 $stop;
    #5 $finish;
end

endmodule
module Test_Memory;


reg clk;
reg rst;
reg wr_cs;
reg wr_en;
reg rd_cs;
reg rd_en;
reg [7:0] in;
wire [7:0] out;
wire full;
wire empty;
wire overflow;
wire underflow;

FIFO #(.LENGTH(4), .WIDTH(8)) fifo (
    .clk(clk),
    .rst(rst),
    .wr_cs(wr_cs),
    .wr_en(wr_en),
    .rd_cs(rd_cs),
    .rd_en(rd_en),
    .overflow(overflow),
    .full(full),
    .empty(empty),
    .underflow(underflow),
    .out(out),
    .in(in)
);

task RESET;
begin
    rst = 0;
    clk = 0;
    
    wr_cs = 0;
    wr_en = 0;
    rd_cs = 0;
    rd_en = 0;
    
    #5
    rst = 1;
    #5
    rst = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
	end
end
endtask

task FIFO_PUSH;
	input [7:0] send;
begin
    wr_cs = 1;
    wr_en = 1;
    rd_cs = 0;
    rd_en = 0;
    in = send;    
    CLOCK(1);
    wr_cs = 0;
    wr_en = 0;
    in = 0;
end
endtask

task FIFO_POP;
    output [7:0] return;
    input [7:0] check;
begin
    wr_cs = 0;
    wr_en = 0;
    rd_cs = 1;
    rd_en = 1;
    CLOCK(1);
    return = out;
    rd_cs = 0;
    rd_en = 0;

    if(return !== check)
    begin
        $display("Error returned (0x%X) != check (0x%X)", return, check);
    end
end
endtask


task FIFO_PUSH_POP;
    input [7:0] send;
    output [7:0] return;
    input [7:0] check;
begin
    wr_cs = 1;
    wr_en = 1;
    rd_cs = 1;
    rd_en = 1;
    in = send;
    CLOCK(1);
    return = out;
    rd_cs = 0;
    rd_en = 0;
    wr_cs = 0;
    wr_en = 0;
end
endtask

parameter FULL_CYCLE = 32'd10_000_000;

reg [7:0] test_value;

initial begin
    #10
    #10
	RESET;
    CLOCK(1);
    FIFO_PUSH(8'h11);
    FIFO_PUSH(8'h22);
    FIFO_PUSH(8'h33);
    FIFO_PUSH(8'h44);
    
    FIFO_POP(test_value, 8'h11);
    FIFO_POP(test_value, 8'h22);
    FIFO_POP(test_value, 8'h33);
    FIFO_POP(test_value, 8'h44);
    CLOCK(5);



    FIFO_PUSH_POP(8'h66, test_value, 8'h66);
    FIFO_PUSH_POP(8'h77, test_value, 8'h77);
    FIFO_PUSH_POP(8'h88, test_value, 8'h88);
    FIFO_PUSH_POP(8'h99, test_value, 8'h99);

    if(underflow != 1)
    begin
        $display("underflow no work!"); 
    end

    FIFO_PUSH(8'h55);
    FIFO_PUSH(8'h66);
    FIFO_PUSH(8'h77);
    FIFO_PUSH(8'h88);

    FIFO_PUSH(8'h99);
    FIFO_PUSH(8'hAA);
    FIFO_PUSH(8'hBB);
    FIFO_PUSH(8'hCC);

    FIFO_POP(test_value, 8'h55);
    FIFO_POP(test_value, 8'h66);
    FIFO_POP(test_value, 8'h77);
    FIFO_POP(test_value, 8'h88);

    FIFO_PUSH(8'h99);
    FIFO_PUSH(8'hAA);
    FIFO_PUSH(8'hBB);
    FIFO_POP(test_value, 8'h99);
    FIFO_POP(test_value, 8'hAA);

    FIFO_PUSH(8'hCC);
    FIFO_PUSH(8'hDD);
    FIFO_PUSH(8'hEE);
    FIFO_POP(test_value, 8'hBB);
    FIFO_POP(test_value, 8'hCC);
    FIFO_POP(test_value, 8'hDD);
    FIFO_POP(test_value, 8'hEE);

    CLOCK(10);
    #10 $stop;
    #5 $finish;
end

endmodule