data/full_repos/permissive/131573849/fpga_verilog/top.v
1: b"%Error: data/full_repos/permissive/131573849/fpga_verilog/top.v:22: Cannot find file containing module: 'pll'\n  pll pll(.CLKI(input_clk), .CLKOP(clk));\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/131573849/fpga_verilog,data/full_repos/permissive/131573849/pll\n             data/full_repos/permissive/131573849/fpga_verilog,data/full_repos/permissive/131573849/pll.v\n             data/full_repos/permissive/131573849/fpga_verilog,data/full_repos/permissive/131573849/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Error: data/full_repos/permissive/131573849/fpga_verilog/top.v:24: Cannot find file containing module: 'uart'\n  uart uart(\n  ^~~~\n%Error: data/full_repos/permissive/131573849/fpga_verilog/top.v:34: Cannot find file containing module: 'logiana'\n logiana logiana(\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top (
  input wire input_clk,
  input wire rst,
  input wire serial_rx,
  output wire serial_tx,
  input [7:0] probe,
	output [16:0] sram_addr,
  inout [7:0] sram_data,
  output sram_ce_n,
  output sram_oe_n,
  output sram_we_n
  );

  wire clk;
	wire [7:0] send_data;
	wire send_ready;
	wire send_req;
	wire [7:0] recv_data;
	wire recv_valid;

  pll pll(.CLKI(input_clk), .CLKOP(clk));

  uart uart(
    .clk(clk),
    .rst(rst),
    .rx(serial_rx),
    .tx(serial_tx),
    .send_data(send_data),
    .send_req(send_req),
    .send_ready(send_ready),
    .recv_data(recv_data),
    .recv_valid(recv_valid));
	logiana logiana(
		.clk(clk),
		.rst(rst),
		.probe(probe),
		.send_data(send_data),
		.send_req(send_req),
		.send_ready(send_ready),
		.recv_data(recv_data),
		.recv_valid(recv_valid),
		.sram_addr(sram_addr),
		.sram_data(sram_data),
		.sram_ce_n(sram_ce_n),
		.sram_oe_n(sram_oe_n),
		.sram_we_n(sram_we_n));

endmodule
module top (
  input wire input_clk,
  input wire rst,
  input wire serial_rx,
  output wire serial_tx,
  input [7:0] probe,
	output [16:0] sram_addr,
  inout [7:0] sram_data,
  output sram_ce_n,
  output sram_oe_n,
  output sram_we_n
  );


  wire clk;
	wire [7:0] send_data;
	wire send_ready;
	wire send_req;
	wire [7:0] recv_data;
	wire recv_valid;

  pll pll(.CLKI(input_clk), .CLKOP(clk));

  uart uart(
    .clk(clk),
    .rst(rst),
    .rx(serial_rx),
    .tx(serial_tx),
    .send_data(send_data),
    .send_req(send_req),
    .send_ready(send_ready),
    .recv_data(recv_data),
    .recv_valid(recv_valid));
	logiana logiana(
		.clk(clk),
		.rst(rst),
		.probe(probe),
		.send_data(send_data),
		.send_req(send_req),
		.send_ready(send_ready),
		.recv_data(recv_data),
		.recv_valid(recv_valid),
		.sram_addr(sram_addr),
		.sram_data(sram_data),
		.sram_ce_n(sram_ce_n),
		.sram_oe_n(sram_oe_n),
		.sram_we_n(sram_we_n));

endmodule