data/full_repos/permissive/127519632/top_tb.sv
 line:15: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:15: Unsupported: Ignoring delay on this delayed statement.\n  #1 rst_n = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:16: Unsupported: Ignoring delay on this delayed statement.\n  #12 rst_n = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 instrution_bus = 12\'h000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:18: Unsupported: Ignoring delay on this delayed statement.\n  #10 instrution_bus = 12\'h430;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:19: Unsupported: Ignoring delay on this delayed statement.\n  #10 instrution_bus = 12\'h301;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:20: Unsupported: Ignoring delay on this delayed statement.\n  #10 instrution_bus = 12\'h440;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:21: Unsupported: Ignoring delay on this delayed statement.\n  #10 instrution_bus = 12\'h331;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:22: Unsupported: Ignoring delay on this delayed statement.\n  #10 instrution_bus = 12\'h100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:23: Unsupported: Ignoring delay on this delayed statement.\n  #10 instrution_bus = 12\'hA00;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:24: Unsupported: Ignoring delay on this delayed statement.\n  #10 instrution_bus = 12\'h600;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:25: Unsupported: Ignoring delay on this delayed statement.\n  #10 instrution_bus = 12\'h500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:26: Unsupported: Ignoring delay on this delayed statement.\n  #100 $stop;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/top_tb.sv:29: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/127519632/top_tb.sv:5: Little bit endian vector: MSB < LSB of bit range: 0:11\n reg [0:11]instrution_bus;\n     ^\n%Error: data/full_repos/permissive/127519632/top_tb.sv:8: Cannot find file containing module: \'top\'\n top UUU(instrution_bus, rst_n, clk);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/top\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/top.v\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb;
	reg clk;
	reg [0:11]instrution_bus;
	reg rst_n;

	top UUU(instrution_bus, rst_n, clk);


	initial
	begin
		rst_n = 1;
		clk = 0;
		#1 rst_n = 0;
		#12 rst_n = 1;
		#1 instrution_bus = 12'h000;
		#10 instrution_bus = 12'h430;
		#10 instrution_bus = 12'h301;
		#10 instrution_bus = 12'h440;
		#10 instrution_bus = 12'h331;
		#10 instrution_bus = 12'h100;
		#10 instrution_bus = 12'hA00;
		#10 instrution_bus = 12'h600;
		#10 instrution_bus = 12'h500;
		#100 $stop;
	end

	always #5 clk = ~clk;

endmodule
module top_tb;

	reg clk;
	reg [0:11]instrution_bus;
	reg rst_n;

	top UUU(instrution_bus, rst_n, clk);


	initial
	begin
		rst_n = 1;
		clk = 0;
		#1 rst_n = 0;
		#12 rst_n = 1;
		#1 instrution_bus = 12'h000;
		#10 instrution_bus = 12'h430;
		#10 instrution_bus = 12'h301;
		#10 instrution_bus = 12'h440;
		#10 instrution_bus = 12'h331;
		#10 instrution_bus = 12'h100;
		#10 instrution_bus = 12'hA00;
		#10 instrution_bus = 12'h600;
		#10 instrution_bus = 12'h500;
		#100 $stop;
	end

	always #5 clk = ~clk;

endmodule