data/full_repos/permissive/123796236/pipeline_control.v
1: b'%Error: data/full_repos/permissive/123796236/pipeline_control.v:91: Unsupported or unknown PLI call: $monitor\n  $monitor("opcode = %b\\n----\\nRegDst = %b\\nBranch = %b\\njump = %b\\nRegWrite = %b\\nALUSrc = %b\\nMemRead = %b\\nMemWrite = %b\\nMemtoReg = %b\\nALUOp = %b\\n****\\n",\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/123796236/pipeline_control.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123796236/pipeline_control.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/pipeline_control.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/pipeline_control.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_Control_Unit_sc();
	
	reg [5:0] opcode;
	wire RegDst, Branch, jump, RegWrite, ALUSrc,
			MemRead, MemWrite, MemtoReg;
	wire [1:0] ALUOp;
	control_unit cu(opcode, RegDst, Branch, jump, RegWrite, ALUSrc, ALUOp,
	MemRead, MemWrite, MemtoReg);
	initial 
		begin
		$monitor("opcode = %b\n----\nRegDst = %b\nBranch = %b\njump = %b\nRegWrite = %b\nALUSrc = %b\nMemRead = %b\nMemWrite = %b\nMemtoReg = %b\nALUOp = %b\n****\n",
		opcode, RegDst, Branch, jump, RegWrite, ALUSrc, MemRead, MemWrite, MemtoReg, ALUOp);
		#5
		opcode = 6'b000000;
		#5
		opcode = 6'b100011;
		#5
		opcode = 6'b101011; 
		#5
		opcode = 6'b000100;
		end
endmodule
module Test_Control_Unit_sc();

	
	reg [5:0] opcode;
	wire RegDst, Branch, jump, RegWrite, ALUSrc,
			MemRead, MemWrite, MemtoReg;
	wire [1:0] ALUOp;
	control_unit cu(opcode, RegDst, Branch, jump, RegWrite, ALUSrc, ALUOp,
	MemRead, MemWrite, MemtoReg);
	initial 
		begin
		$monitor("opcode = %b\n----\nRegDst = %b\nBranch = %b\njump = %b\nRegWrite = %b\nALUSrc = %b\nMemRead = %b\nMemWrite = %b\nMemtoReg = %b\nALUOp = %b\n****\n",
		opcode, RegDst, Branch, jump, RegWrite, ALUSrc, MemRead, MemWrite, MemtoReg, ALUOp);
		#5
		opcode = 6'b000000;
		#5
		opcode = 6'b100011;
		#5
		opcode = 6'b101011; 
		#5
		opcode = 6'b000100;
		end
endmodule