data/full_repos/permissive/157101210/adder.v
data/verilator_xmls/e7c95d2e-5b90-4fdb-b3e3-16c92e499139.xml
module Adder 
(
    output[31:0] result,
    output carryout,
    output overflow,
    input[31:0] operandA,
    input[31:0] operandB
);
    wire[32:0] carryOut;
    assign carryOut[0] = 0;

    generate
        genvar i;
        for (i=0; i<32; i=i+1)
        begin
            FullAdder1 FullAdder (
                .carryout (carryOut[i+1]),
                .a (operandA[i]),
                .b (operandB[i]),
                .carryin (carryOut[i]),
                .res (result[i])
            );
        end
    endgenerate

    didOverflow1 overflowCalc(
        .overflow (overflow),
        .a (operandA[31]),
        .b (operandB[31]),
        .s (result[31])
    );
endmodule
module Adder 
(
    output[31:0] result,
    output carryout,
    output overflow,
    input[31:0] operandA,
    input[31:0] operandB
);

    wire[32:0] carryOut;
    assign carryOut[0] = 0;

    generate
        genvar i;
        for (i=0; i<32; i=i+1)
        begin
            FullAdder1 FullAdder (
                .carryout (carryOut[i+1]),
                .a (operandA[i]),
                .b (operandB[i]),
                .carryin (carryOut[i]),
                .res (result[i])
            );
        end
    endgenerate

    didOverflow1 overflowCalc(
        .overflow (overflow),
        .a (operandA[31]),
        .b (operandB[31]),
        .s (result[31])
    );
endmodule