data/full_repos/permissive/15008590/adder/test_bench_tb.v
 line:14: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/15008590/adder/test_bench_tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n    #50 rst <= 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/15008590/adder/test_bench_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #2000000 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/15008590/adder/test_bench_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk <= ~clk;\n      ^\n%Error: data/full_repos/permissive/15008590/adder/test_bench_tb.v:26: Cannot find file containing module: \'test_bench\'\n  test_bench uut(\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/15008590/adder,data/full_repos/permissive/15008590/test_bench\n             data/full_repos/permissive/15008590/adder,data/full_repos/permissive/15008590/test_bench.v\n             data/full_repos/permissive/15008590/adder,data/full_repos/permissive/15008590/test_bench.sv\n             test_bench\n             test_bench.v\n             test_bench.sv\n             obj_dir/test_bench\n             obj_dir/test_bench.v\n             obj_dir/test_bench.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_bench_tb;
  reg  clk;
  reg  rst;
  
  initial
  begin
    rst <= 1'b1;
    #50 rst <= 1'b0;
  end

  
  initial
  begin
    #2000000 $finish;
  end

  
  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  test_bench uut(
    .clk(clk),
    .rst(rst));
endmodule
module test_bench_tb;

  reg  clk;
  reg  rst;
  
  initial
  begin
    rst <= 1'b1;
    #50 rst <= 1'b0;
  end

  
  initial
  begin
    #2000000 $finish;
  end

  
  initial
  begin
    clk <= 1'b0;
    while (1) begin
      #5 clk <= ~clk;
    end
  end

  test_bench uut(
    .clk(clk),
    .rst(rst));
endmodule