data/full_repos/permissive/113839829/Attempt/Chapter 4/regfile.v
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1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/113839829\n        ... Looked in:\n             data/full_repos/permissive/113839829/Attempt/Chapter/4,data/full_repos/permissive/113839829\n             data/full_repos/permissive/113839829/Attempt/Chapter/4,data/full_repos/permissive/113839829.v\n             data/full_repos/permissive/113839829/Attempt/Chapter/4,data/full_repos/permissive/113839829.sv\n             4,data/full_repos/permissive/113839829\n             4,data/full_repos/permissive/113839829.v\n             4,data/full_repos/permissive/113839829.sv\n             obj_dir/4,data/full_repos/permissive/113839829\n             obj_dir/4,data/full_repos/permissive/113839829.v\n             obj_dir/4,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Attempt/Chapter\n%Error: Cannot find file containing module: 4/regfile.v\n%Error: Exiting due to 3 error(s)\n'
module regfile(

	       input wire 		clk,
	       input wire 		rst,


	       input wire 		we,
	       input wire [`RegAddrBus] waddr,
	       input wire [`RegBus] 	wdata,


	       input wire 		re1,
	       input wire [`RegAddrBus] raddr1,
	       output reg [`RegBus] 	rdata1,


	       input wire 		re2,
	       input wire [`RegAddrBus] raddr2,
	       output reg [`RegBus] 	rdata2

	       );
   reg [`RegBus] 			regs[0:`RegNum-1];

   always @ (posedge clk) 
     begin
	if (rst == `RstDisable) 
	  if((we == `WriteEnable) && (waddr != `RegNumLog2'h0)) 
	    begin
	       regs[waddr] <= wdata;
	       $display(wdata);
	    end
     end



























   


 `define READ(re,raddr,rdata) \ 
   always @ (*) \ 
     begin \ 
   	if(rst == `RstEnable) \ 
   		rdata <= `ZeroWord; \ 
   		  else if(raddr == `RegNumLog2'h0) \ 
   				 rdata <= `ZeroWord; \ 
   				   else if((raddr == waddr) && (we == `WriteEnable) \ 
   	  				   && (re == `ReadEnable)) \ 
   						   rdata <= wdata; \ 
   						     else if(re == `ReadEnable) \ 
   								 rdata <= regs[raddr]; \ 
   								   else \ 
   								     rdata <= `ZeroWord; \ 
									      end

   `READ(re1,raddr1,rdata1)
   `READ(re2,raddr2,rdata2)
   
endmodule
module regfile(

	       input wire 		clk,
	       input wire 		rst,


	       input wire 		we,
	       input wire [`RegAddrBus] waddr,
	       input wire [`RegBus] 	wdata,


	       input wire 		re1,
	       input wire [`RegAddrBus] raddr1,
	       output reg [`RegBus] 	rdata1,


	       input wire 		re2,
	       input wire [`RegAddrBus] raddr2,
	       output reg [`RegBus] 	rdata2

	       );

   reg [`RegBus] 			regs[0:`RegNum-1];

   always @ (posedge clk) 
     begin
	if (rst == `RstDisable) 
	  if((we == `WriteEnable) && (waddr != `RegNumLog2'h0)) 
	    begin
	       regs[waddr] <= wdata;
	       $display(wdata);
	    end
     end



























   


 `define READ(re,raddr,rdata) \ 
   always @ (*) \ 
     begin \ 
   	if(rst == `RstEnable) \ 
   		rdata <= `ZeroWord; \ 
   		  else if(raddr == `RegNumLog2'h0) \ 
   				 rdata <= `ZeroWord; \ 
   				   else if((raddr == waddr) && (we == `WriteEnable) \ 
   	  				   && (re == `ReadEnable)) \ 
   						   rdata <= wdata; \ 
   						     else if(re == `ReadEnable) \ 
   								 rdata <= regs[raddr]; \ 
   								   else \ 
   								     rdata <= `ZeroWord; \ 
									      end

   `READ(re1,raddr1,rdata1)
   `READ(re2,raddr2,rdata2)
   
endmodule