data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation/ddr3_s4_uniphy_example_sim_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation/ddr3_s4_uniphy_example_sim_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\nalways #(10000/2) clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation/ddr3_s4_uniphy_example_sim_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #(50000) reset_n <= 1;\n        ^\n%Error: data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation/ddr3_s4_uniphy_example_sim_tb.v:10: Cannot find file containing module: \'ddr3_s4_uniphy_example_sim\'\nddr3_s4_uniphy_example_sim dut (\n^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation,data/full_repos/permissive/1122957/ddr3_s4_uniphy_example_sim\n             data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation,data/full_repos/permissive/1122957/ddr3_s4_uniphy_example_sim.v\n             data/full_repos/permissive/1122957/coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/simulation,data/full_repos/permissive/1122957/ddr3_s4_uniphy_example_sim.sv\n             ddr3_s4_uniphy_example_sim\n             ddr3_s4_uniphy_example_sim.v\n             ddr3_s4_uniphy_example_sim.sv\n             obj_dir/ddr3_s4_uniphy_example_sim\n             obj_dir/ddr3_s4_uniphy_example_sim.v\n             obj_dir/ddr3_s4_uniphy_example_sim.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ddr3_s4_uniphy_example_sim_tb();

reg clk;
reg reset_n;

ddr3_s4_uniphy_example_sim dut (

		.oct_rdn(),
		.oct_rup(),

        .pll_ref_clk(clk),
        .global_reset_n(reset_n),
        .soft_reset_n(1'b1)
);


always #(10000/2) clk <= ~clk;

initial
begin
        clk <= 1'b0;
        reset_n <= 0;
        #(50000) reset_n <= 1;
end



endmodule
module ddr3_s4_uniphy_example_sim_tb();


reg clk;
reg reset_n;

ddr3_s4_uniphy_example_sim dut (

		.oct_rdn(),
		.oct_rup(),

        .pll_ref_clk(clk),
        .global_reset_n(reset_n),
        .soft_reset_n(1'b1)
);


always #(10000/2) clk <= ~clk;

initial
begin
        clk <= 1'b0;
        reset_n <= 0;
        #(50000) reset_n <= 1;
end



endmodule