data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/idx_ctl.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/idx_ctl.v:38: Cannot find include file: sdr_def.v\n`include "sdr_def.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog,data/full_repos/permissive/122125962/sdr_def.v\n             data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog,data/full_repos/permissive/122125962/sdr_def.v.v\n             data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog,data/full_repos/permissive/122125962/sdr_def.v.sv\n             sdr_def.v\n             sdr_def.v.v\n             sdr_def.v.sv\n             obj_dir/sdr_def.v\n             obj_dir/sdr_def.v.v\n             obj_dir/sdr_def.v.sv\n%Error: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/idx_ctl.v:88: Define or directive not defined: \'`AUDIO_RECORD\'\nwire audio_rst = (audio_mode==`AUDIO_RECORD)? 1 : 0;\n                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/122125962/floodcasting/stream_vlc_verilog/idx_ctl.v:88: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire audio_rst = (audio_mode==`AUDIO_RECORD)? 1 : 0;\n                                           ^\n%Error: Exiting due to 3 error(s)\n'
module idx_control(

	input	HCLK,
	input	HRESETn, 
	input	[7:0] data_in,
	input	data_wr,

	input	audio_mode,
	output	ready,

	output	reg [7:0]	tx_fifo_dout,
	output	reg	tx_fifo_we,

	input	tx_fifo_full,
	input	tx_fifo_empty,
	input	[1:0] current_owner
);


reg		[1:0]	fsm;


reg				hready_reg;
reg		[2:0]	zero_cnt;
reg		[1:0]	pkt_state;
reg		[7:0]	pkt_len, pkt_cnt;
reg		[1:0]	pkt_end_state;
reg				crc_clear, crc_start;
reg		[1:0]	crc_state;
reg		[1:0]	crc_cnt;
wire	[15:0]	crc_result;
wire			crc_ready;


parameter RESET =		2'b00;
parameter LOAD_SFD =	2'b01;
parameter AHB_TRANS =	2'b10;
parameter CRC_ADD =		2'b11;
                             
parameter CRC_LSB =		2'b00;
parameter CRC_MSB =		2'b01;
parameter PKT_DONE =	2'b10;
                             
parameter CRC_START =	2'b00;
parameter CRC_WAIT =	2'b01;
parameter CRC_IDLE =	2'b10;
parameter CRC_DISABLE =	2'b11;

assign ready = (~tx_fifo_full) & hready_reg;
wire audio_rst = (audio_mode==`AUDIO_RECORD)? 1 : 0;

always @ (posedge HCLK)
begin
    if (~(HRESETn&audio_rst))
    begin
		fsm			<= 2'b00;
		tx_fifo_dout    <= 0;
		tx_fifo_we	    <= 0;
		hready_reg	<= 0;
		zero_cnt	<= 0;
		pkt_state	<= RESET;
		pkt_len		<= 0;
		pkt_cnt		<= 0;
		pkt_end_state <= CRC_LSB;
		crc_start	<= 0;
		crc_clear	<= 0;
		crc_state	<= CRC_IDLE;
		crc_cnt		<= 0;
    end
    else
    begin
		case (fsm)
		    2'b00:
		    begin
				case (pkt_state)
					RESET:
					begin
						if ((current_owner ^ 2'b10) && (tx_fifo_empty))
							pkt_state <= LOAD_SFD;
						zero_cnt <= 0;
						pkt_end_state <= CRC_LSB;
						crc_clear <= 1;
					end

					LOAD_SFD:
					begin
						zero_cnt <= zero_cnt + 1;
						crc_clear <= 0;
						if (zero_cnt<4)
						begin
							tx_fifo_we  <= 1;
							tx_fifo_dout <= 0;
						end
						else if (zero_cnt==4)
						begin
							tx_fifo_we  <= 1;
							tx_fifo_dout <= 8'ha7;
						end
						else
						begin
							pkt_state <= AHB_TRANS;
							hready_reg <= 1;
							tx_fifo_we  <= 0;
						end
					end

					AHB_TRANS:
					begin
						if (data_wr)
						begin
							fsm			<= 2'b01;
							hready_reg	<= 0;
						end
					end

					CRC_ADD:
					begin

						case (pkt_end_state)
							CRC_LSB:
							begin
								tx_fifo_we <= 1;
								tx_fifo_dout <= crc_result[7:0];
								pkt_end_state <= CRC_MSB;
							end

							CRC_MSB:
							begin
								tx_fifo_we <= 1;
								tx_fifo_dout <= crc_result[15:8];
								pkt_end_state <= PKT_DONE;
								crc_clear <= 1;
							end

							PKT_DONE:
							begin
								crc_clear <= 0;
								tx_fifo_we	<= 0;
								pkt_state <= RESET;
								pkt_cnt	<= 0;
								pkt_len	<= 0;
							end
						endcase
					end

					default:
					begin
						pkt_state <= RESET;
						tx_fifo_we	<= 0;
					end
				endcase
		    end

			2'b01:
			begin
				fsm	<= 2'b10;
				crc_cnt <= 0;
				if (pkt_cnt==0)
				begin
					pkt_len <= data_in[7:0];
					crc_state <= CRC_IDLE;
				end
				else
					crc_state <= CRC_START;
				pkt_cnt <= pkt_cnt + 1;
				tx_fifo_we <= 1;
				tx_fifo_dout <= data_in[7:0];
			end
		    
		    2'b10:
		    begin
				tx_fifo_we <= 0;
				case (crc_state)
					CRC_START:
					begin
						crc_start <= 1;
						crc_state <= CRC_DISABLE;
					end

					CRC_DISABLE:
					begin
						crc_start <= 0;
						crc_cnt <= crc_cnt + 1;
						if (crc_cnt==2'b10)
							crc_state <= CRC_WAIT;
					end

					CRC_WAIT:
					begin
						if (crc_ready)
						begin
							fsm <= 2'b11;
							crc_state <= CRC_IDLE;
						end

					end

					CRC_IDLE:
					begin
						fsm	<= 2'b11;
					end
				endcase
			end

			2'b11:
			begin
				if (((pkt_len-1)==pkt_cnt) && (pkt_len>0))
					pkt_state <= CRC_ADD;
				else
					hready_reg <= 1;

				fsm <= 2'b00;
				zero_cnt <= 0;
			end
		endcase
    end
end


crc			tx_crc(	.clk(HCLK), .nreset(HRESETn&audio_rst), .clear(crc_clear), .data_in(tx_fifo_dout), 
					.crc_out(crc_result), .start(crc_start), .out_ready(crc_ready));

endmodule
module idx_control(

	input	HCLK,
	input	HRESETn, 
	input	[7:0] data_in,
	input	data_wr,

	input	audio_mode,
	output	ready,

	output	reg [7:0]	tx_fifo_dout,
	output	reg	tx_fifo_we,

	input	tx_fifo_full,
	input	tx_fifo_empty,
	input	[1:0] current_owner
);



reg		[1:0]	fsm;


reg				hready_reg;
reg		[2:0]	zero_cnt;
reg		[1:0]	pkt_state;
reg		[7:0]	pkt_len, pkt_cnt;
reg		[1:0]	pkt_end_state;
reg				crc_clear, crc_start;
reg		[1:0]	crc_state;
reg		[1:0]	crc_cnt;
wire	[15:0]	crc_result;
wire			crc_ready;


parameter RESET =		2'b00;
parameter LOAD_SFD =	2'b01;
parameter AHB_TRANS =	2'b10;
parameter CRC_ADD =		2'b11;
                             
parameter CRC_LSB =		2'b00;
parameter CRC_MSB =		2'b01;
parameter PKT_DONE =	2'b10;
                             
parameter CRC_START =	2'b00;
parameter CRC_WAIT =	2'b01;
parameter CRC_IDLE =	2'b10;
parameter CRC_DISABLE =	2'b11;

assign ready = (~tx_fifo_full) & hready_reg;
wire audio_rst = (audio_mode==`AUDIO_RECORD)? 1 : 0;

always @ (posedge HCLK)
begin
    if (~(HRESETn&audio_rst))
    begin
		fsm			<= 2'b00;
		tx_fifo_dout    <= 0;
		tx_fifo_we	    <= 0;
		hready_reg	<= 0;
		zero_cnt	<= 0;
		pkt_state	<= RESET;
		pkt_len		<= 0;
		pkt_cnt		<= 0;
		pkt_end_state <= CRC_LSB;
		crc_start	<= 0;
		crc_clear	<= 0;
		crc_state	<= CRC_IDLE;
		crc_cnt		<= 0;
    end
    else
    begin
		case (fsm)
		    2'b00:
		    begin
				case (pkt_state)
					RESET:
					begin
						if ((current_owner ^ 2'b10) && (tx_fifo_empty))
							pkt_state <= LOAD_SFD;
						zero_cnt <= 0;
						pkt_end_state <= CRC_LSB;
						crc_clear <= 1;
					end

					LOAD_SFD:
					begin
						zero_cnt <= zero_cnt + 1;
						crc_clear <= 0;
						if (zero_cnt<4)
						begin
							tx_fifo_we  <= 1;
							tx_fifo_dout <= 0;
						end
						else if (zero_cnt==4)
						begin
							tx_fifo_we  <= 1;
							tx_fifo_dout <= 8'ha7;
						end
						else
						begin
							pkt_state <= AHB_TRANS;
							hready_reg <= 1;
							tx_fifo_we  <= 0;
						end
					end

					AHB_TRANS:
					begin
						if (data_wr)
						begin
							fsm			<= 2'b01;
							hready_reg	<= 0;
						end
					end

					CRC_ADD:
					begin

						case (pkt_end_state)
							CRC_LSB:
							begin
								tx_fifo_we <= 1;
								tx_fifo_dout <= crc_result[7:0];
								pkt_end_state <= CRC_MSB;
							end

							CRC_MSB:
							begin
								tx_fifo_we <= 1;
								tx_fifo_dout <= crc_result[15:8];
								pkt_end_state <= PKT_DONE;
								crc_clear <= 1;
							end

							PKT_DONE:
							begin
								crc_clear <= 0;
								tx_fifo_we	<= 0;
								pkt_state <= RESET;
								pkt_cnt	<= 0;
								pkt_len	<= 0;
							end
						endcase
					end

					default:
					begin
						pkt_state <= RESET;
						tx_fifo_we	<= 0;
					end
				endcase
		    end

			2'b01:
			begin
				fsm	<= 2'b10;
				crc_cnt <= 0;
				if (pkt_cnt==0)
				begin
					pkt_len <= data_in[7:0];
					crc_state <= CRC_IDLE;
				end
				else
					crc_state <= CRC_START;
				pkt_cnt <= pkt_cnt + 1;
				tx_fifo_we <= 1;
				tx_fifo_dout <= data_in[7:0];
			end
		    
		    2'b10:
		    begin
				tx_fifo_we <= 0;
				case (crc_state)
					CRC_START:
					begin
						crc_start <= 1;
						crc_state <= CRC_DISABLE;
					end

					CRC_DISABLE:
					begin
						crc_start <= 0;
						crc_cnt <= crc_cnt + 1;
						if (crc_cnt==2'b10)
							crc_state <= CRC_WAIT;
					end

					CRC_WAIT:
					begin
						if (crc_ready)
						begin
							fsm <= 2'b11;
							crc_state <= CRC_IDLE;
						end

					end

					CRC_IDLE:
					begin
						fsm	<= 2'b11;
					end
				endcase
			end

			2'b11:
			begin
				if (((pkt_len-1)==pkt_cnt) && (pkt_len>0))
					pkt_state <= CRC_ADD;
				else
					hready_reg <= 1;

				fsm <= 2'b00;
				zero_cnt <= 0;
			end
		endcase
    end
end


crc			tx_crc(	.clk(HCLK), .nreset(HRESETn&audio_rst), .clear(crc_clear), .data_in(tx_fifo_dout), 
					.crc_out(crc_result), .start(crc_start), .out_ready(crc_ready));

endmodule