data/full_repos/permissive/143278/ivltests/pr2829776.v
 line:6: before: "400"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2829776.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #100 in1 = 1\'b1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2829776.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #200 in2 = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2829776.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #199;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2829776.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2829776.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #198;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/pr2829776.v:52: Unsupported: fork statements\n    fork\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2829776.v:55: Unsupported: Ignoring delay on this delayed statement.\n          #2;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2829776.v:65: Unsupported: Ignoring delay on this delayed statement.\n          #2;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2829776.v:75: Unsupported: Ignoring delay on this delayed statement.\n          #2;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2829776.v:83: Unsupported: Ignoring delay on this delayed statement.\n      #2;  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2829776.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #399;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2829776.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg in1, in2, pass, checkc, checkg, checkp;
  wire outc, outg, outp;

  assign #400 outc = in1 | in2;
  or #400 g1(outg, in1, in2);
  my_or #400 g2(outp, in1, in2);

  initial begin

    pass = 1'b1;
    checkc = 1'b0;
    checkg = 1'b0;
    checkp = 1'b0;
    in1 = 1'b0;
    in2 = 1'b0;
    #100 in1 = 1'b1;
    #200 in2 = 1'b1;
    #199;

    if (outc !== 1'bz && outc !== 1'bx) begin
      $display("CA output changed early!");
      pass = 1'b0;
    end
    if (outg !== 1'bz && outg !== 1'bx) begin
      $display("Gate output changed early!");
      pass = 1'b0;
    end
    if (outp !== 1'bz && outp !== 1'bx) begin
      $display("UDP output changed early!");
      pass = 1'b0;
    end
    #2;

    if (outc !== 1'b1) begin
      $display("CA output changed late!");
      pass = 1'b0;
      checkc = 1'b1;
    end
    if (outg !== 1'b1) begin
      $display("Gate output changed late!");
      pass = 1'b0;
      checkg = 1'b1;
    end
    if (outp !== 1'b1) begin
      $display("UDP output changed late!");
      pass = 1'b0;
      checkp = 1'b1;
    end
    #198;

    fork
      if (checkc) begin
        if (outc === 1'bz || outc === 1'bx) begin
          #2;

          if (outc === 1'b1)
            $display("CA output triggered off of in2 change instead of in1.");
          else
            $display("CA output triggered very late.");
        end
      end
      if (checkg) begin
        if (outg === 1'bz || outg === 1'bx) begin
          #2;

          if (outg === 1'b1)
            $display("Gate output triggered off of in2 change instead of in1.");
          else
            $display("Gate output triggered very late.");
        end
      end
      if (checkp) begin
        if (outp === 1'bz || outp === 1'bx) begin
          #2;

          if (outp === 1'b1)
            $display("UDP output triggered off of in2 change instead of in1.");
          else
            $display("UDP output triggered very late.");
        end
      end
      #2;
    join


    in1 = 1'b0;
    in2 = 1'b0;
    #399;
    in1 = 1'b1;
    in2 = 1'b1;
    #2;

    if (outc !== 1'b1) begin
      $display("CA does not have inertial delay.");
      pass = 1'b0;
    end
    if (outg !== 1'b1) begin
      $display("Gate does not have inertial delay.");
      pass = 1'b0;
    end
    if (outp !== 1'b1) begin
      $display("UDP does not have inertial delay.");
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg in1, in2, pass, checkc, checkg, checkp;
  wire outc, outg, outp;

  assign #400 outc = in1 | in2;
  or #400 g1(outg, in1, in2);
  my_or #400 g2(outp, in1, in2);

  initial begin

    pass = 1'b1;
    checkc = 1'b0;
    checkg = 1'b0;
    checkp = 1'b0;
    in1 = 1'b0;
    in2 = 1'b0;
    #100 in1 = 1'b1;
    #200 in2 = 1'b1;
    #199;

    if (outc !== 1'bz && outc !== 1'bx) begin
      $display("CA output changed early!");
      pass = 1'b0;
    end
    if (outg !== 1'bz && outg !== 1'bx) begin
      $display("Gate output changed early!");
      pass = 1'b0;
    end
    if (outp !== 1'bz && outp !== 1'bx) begin
      $display("UDP output changed early!");
      pass = 1'b0;
    end
    #2;

    if (outc !== 1'b1) begin
      $display("CA output changed late!");
      pass = 1'b0;
      checkc = 1'b1;
    end
    if (outg !== 1'b1) begin
      $display("Gate output changed late!");
      pass = 1'b0;
      checkg = 1'b1;
    end
    if (outp !== 1'b1) begin
      $display("UDP output changed late!");
      pass = 1'b0;
      checkp = 1'b1;
    end
    #198;

    fork
      if (checkc) begin
        if (outc === 1'bz || outc === 1'bx) begin
          #2;

          if (outc === 1'b1)
            $display("CA output triggered off of in2 change instead of in1.");
          else
            $display("CA output triggered very late.");
        end
      end
      if (checkg) begin
        if (outg === 1'bz || outg === 1'bx) begin
          #2;

          if (outg === 1'b1)
            $display("Gate output triggered off of in2 change instead of in1.");
          else
            $display("Gate output triggered very late.");
        end
      end
      if (checkp) begin
        if (outp === 1'bz || outp === 1'bx) begin
          #2;

          if (outp === 1'b1)
            $display("UDP output triggered off of in2 change instead of in1.");
          else
            $display("UDP output triggered very late.");
        end
      end
      #2;
    join


    in1 = 1'b0;
    in2 = 1'b0;
    #399;
    in1 = 1'b1;
    in2 = 1'b1;
    #2;

    if (outc !== 1'b1) begin
      $display("CA does not have inertial delay.");
      pass = 1'b0;
    end
    if (outg !== 1'b1) begin
      $display("Gate does not have inertial delay.");
      pass = 1'b0;
    end
    if (outp !== 1'b1) begin
      $display("UDP does not have inertial delay.");
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule