data/full_repos/permissive/102564818/Transmitter.v
1: b"%Error: data/full_repos/permissive/102564818/Transmitter.v:22: Cannot find file containing module: 'BaudGeneratorTx'\n    BaudGeneratorTx B1(.CLK(CLK), .RST(RST), .BaudRate(BaudRate), .Pulse(BaudPulse));\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102564818,data/full_repos/permissive/102564818/BaudGeneratorTx\n             data/full_repos/permissive/102564818,data/full_repos/permissive/102564818/BaudGeneratorTx.v\n             data/full_repos/permissive/102564818,data/full_repos/permissive/102564818/BaudGeneratorTx.sv\n             BaudGeneratorTx\n             BaudGeneratorTx.v\n             BaudGeneratorTx.sv\n             obj_dir/BaudGeneratorTx\n             obj_dir/BaudGeneratorTx.v\n             obj_dir/BaudGeneratorTx.sv\n%Error: Exiting due to 1 error(s)\n"
module Transmitter(CLK, RST, BaudRate, ParityMode, StopBits, TxBegin, TxData, TxBusy, Tx);
    input CLK;
    input RST;
    input[1:0] BaudRate;
    input[1:0] ParityMode;
    input StopBits;
    input TxBegin;
    input[7:0] TxData;
    output reg TxBusy;
    output reg Tx;
    
    wire BaudPulse;
    reg[3:0] State;
    reg TxBeginPending;
    reg[7:0] TxDataS;
        
    BaudGeneratorTx B1(.CLK(CLK), .RST(RST), .BaudRate(BaudRate), .Pulse(BaudPulse));
    
    always @ (posedge CLK) begin
        if(TxBegin && ~TxBusy) TxDataS <= TxData;
        else TxDataS <= TxDataS;
    end
    
    always @ (posedge CLK or posedge RST) begin
        if(RST) begin
            State <= 4'b0000;
            TxBeginPending <= 1'b0;
        end else begin
            if(TxBegin) TxBeginPending <= 1'b1;
            case(State)
                4'b0000: if(TxBeginPending & BaudPulse) begin State <= 4'b0001; TxBeginPending <= 1'b0; end
                4'b0001: if(BaudPulse) State <= 4'b0010;
                4'b0010: if(BaudPulse) State <= 4'b0011;
                4'b0011: if(BaudPulse) State <= 4'b0100;
                4'b0100: if(BaudPulse) State <= 4'b0101;
                4'b0101: if(BaudPulse) State <= 4'b0110;
                4'b0110: if(BaudPulse) State <= 4'b0111;
                4'b0111: if(BaudPulse) State <= 4'b1000;
                4'b1000: if(BaudPulse) State <= 4'b1001;
                4'b1001: begin
                    if(BaudPulse) begin 
                        if(ParityMode[1] == 1'b1) State <= 4'b1010;
                        else State <= 4'b1100;
                    end
                end
                4'b1010: begin
                    if(BaudPulse) begin
                        if(StopBits == 1'b0) State <= 4'b0000;
                        if(StopBits == 1'b1) State <= 4'b1011;
                    end
                end
                4'b1011: if(BaudPulse) State <= 4'b0000;
                4'b1100: if(BaudPulse) State <= 4'b1010;
                default: State <= 4'b0000;
            endcase
        end
    end
    
    always @ (State or TxDataS or ParityMode) begin
        case(State)
            4'b0001: Tx <= 1'b0;
            4'b0010: Tx <= TxDataS[0];
            4'b0011: Tx <= TxDataS[1];
            4'b0100: Tx <= TxDataS[2];
            4'b0101: Tx <= TxDataS[3];
            4'b0110: Tx <= TxDataS[4];
            4'b0111: Tx <= TxDataS[5];
            4'b1000: Tx <= TxDataS[6];
            4'b1001: Tx <= TxDataS[7];
            4'b1010: Tx <= 1'b1;
            4'b1011: Tx <= 1'b1;
            4'b1100: begin
                if(ParityMode[0] == 1'b0) begin
                    Tx <= (TxDataS[7] ^ (TxDataS[6] ^ (TxDataS[5] ^ (TxDataS[4] ^ (TxDataS[3] ^ (TxDataS[2] ^ (TxDataS[1] ^ (TxDataS[0]))))))));
                end else begin
                    Tx <= ~(TxDataS[7] ^ (TxDataS[6] ^ (TxDataS[5] ^ (TxDataS[4] ^ (TxDataS[3] ^ (TxDataS[2] ^ (TxDataS[1] ^ (TxDataS[0]))))))));
                end
            end
            default: Tx <= 1'b1;
        endcase
    end
    
    always @ (State) begin
        case(State)
            4'b0000: TxBusy <= 1'b0;
            4'b1101: TxBusy <= 1'b0;
            4'b1110: TxBusy <= 1'b0;
            4'b1111: TxBusy <= 1'b0;
            default: TxBusy <= 1'b1;
        endcase
    end
endmodule
module Transmitter(CLK, RST, BaudRate, ParityMode, StopBits, TxBegin, TxData, TxBusy, Tx);

    input CLK;
    input RST;
    input[1:0] BaudRate;
    input[1:0] ParityMode;
    input StopBits;
    input TxBegin;
    input[7:0] TxData;
    output reg TxBusy;
    output reg Tx;
    
    wire BaudPulse;
    reg[3:0] State;
    reg TxBeginPending;
    reg[7:0] TxDataS;
        
    BaudGeneratorTx B1(.CLK(CLK), .RST(RST), .BaudRate(BaudRate), .Pulse(BaudPulse));
    
    always @ (posedge CLK) begin
        if(TxBegin && ~TxBusy) TxDataS <= TxData;
        else TxDataS <= TxDataS;
    end
    
    always @ (posedge CLK or posedge RST) begin
        if(RST) begin
            State <= 4'b0000;
            TxBeginPending <= 1'b0;
        end else begin
            if(TxBegin) TxBeginPending <= 1'b1;
            case(State)
                4'b0000: if(TxBeginPending & BaudPulse) begin State <= 4'b0001; TxBeginPending <= 1'b0; end
                4'b0001: if(BaudPulse) State <= 4'b0010;
                4'b0010: if(BaudPulse) State <= 4'b0011;
                4'b0011: if(BaudPulse) State <= 4'b0100;
                4'b0100: if(BaudPulse) State <= 4'b0101;
                4'b0101: if(BaudPulse) State <= 4'b0110;
                4'b0110: if(BaudPulse) State <= 4'b0111;
                4'b0111: if(BaudPulse) State <= 4'b1000;
                4'b1000: if(BaudPulse) State <= 4'b1001;
                4'b1001: begin
                    if(BaudPulse) begin 
                        if(ParityMode[1] == 1'b1) State <= 4'b1010;
                        else State <= 4'b1100;
                    end
                end
                4'b1010: begin
                    if(BaudPulse) begin
                        if(StopBits == 1'b0) State <= 4'b0000;
                        if(StopBits == 1'b1) State <= 4'b1011;
                    end
                end
                4'b1011: if(BaudPulse) State <= 4'b0000;
                4'b1100: if(BaudPulse) State <= 4'b1010;
                default: State <= 4'b0000;
            endcase
        end
    end
    
    always @ (State or TxDataS or ParityMode) begin
        case(State)
            4'b0001: Tx <= 1'b0;
            4'b0010: Tx <= TxDataS[0];
            4'b0011: Tx <= TxDataS[1];
            4'b0100: Tx <= TxDataS[2];
            4'b0101: Tx <= TxDataS[3];
            4'b0110: Tx <= TxDataS[4];
            4'b0111: Tx <= TxDataS[5];
            4'b1000: Tx <= TxDataS[6];
            4'b1001: Tx <= TxDataS[7];
            4'b1010: Tx <= 1'b1;
            4'b1011: Tx <= 1'b1;
            4'b1100: begin
                if(ParityMode[0] == 1'b0) begin
                    Tx <= (TxDataS[7] ^ (TxDataS[6] ^ (TxDataS[5] ^ (TxDataS[4] ^ (TxDataS[3] ^ (TxDataS[2] ^ (TxDataS[1] ^ (TxDataS[0]))))))));
                end else begin
                    Tx <= ~(TxDataS[7] ^ (TxDataS[6] ^ (TxDataS[5] ^ (TxDataS[4] ^ (TxDataS[3] ^ (TxDataS[2] ^ (TxDataS[1] ^ (TxDataS[0]))))))));
                end
            end
            default: Tx <= 1'b1;
        endcase
    end
    
    always @ (State) begin
        case(State)
            4'b0000: TxBusy <= 1'b0;
            4'b1101: TxBusy <= 1'b0;
            4'b1110: TxBusy <= 1'b0;
            4'b1111: TxBusy <= 1'b0;
            default: TxBusy <= 1'b1;
        endcase
    end
endmodule