data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/SGDMA_dispatcher/response_block.v
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1: b"%Error: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/SGDMA_dispatcher/response_block.v:143: Cannot find file containing module: 'scfifo'\n      scfifo the_response_FIFO (\n      ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/SGDMA_dispatcher,data/full_repos/permissive/205229557/scfifo\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/SGDMA_dispatcher,data/full_repos/permissive/205229557/scfifo.v\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/SGDMA_dispatcher,data/full_repos/permissive/205229557/scfifo.sv\n             scfifo\n             scfifo.v\n             scfifo.sv\n             obj_dir/scfifo\n             obj_dir/scfifo.v\n             obj_dir/scfifo.sv\n%Error: Exiting due to 1 error(s)\n"
module response_block (
  clk,
  reset,

  mm_response_readdata,
  mm_response_read,
  mm_response_address,
  mm_response_byteenable,
  mm_response_waitrequest,

  src_response_data,
  src_response_valid,
  src_response_ready,

  sw_reset,
  response_watermark,
  response_fifo_full,
  response_fifo_empty,
  done_strobe,
  actual_bytes_transferred,
  error,
  early_termination,
  transfer_complete_IRQ_mask,
  error_IRQ_mask,
  early_termination_IRQ_mask,
  descriptor_buffer_full
);


  parameter RESPONSE_PORT = 0;
  parameter FIFO_DEPTH = 256;
  parameter FIFO_DEPTH_LOG2 = 8;
  localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51;

  input clk;
  input reset;

  output wire [31:0] mm_response_readdata;
  input mm_response_read;
  input mm_response_address;
  input [3:0] mm_response_byteenable;
  output wire mm_response_waitrequest;

  output wire [255:0] src_response_data;
  output wire src_response_valid;
  input src_response_ready;

  input sw_reset;
  output wire [15:0] response_watermark;
  output wire response_fifo_full;
  output wire response_fifo_empty;
  input done_strobe;
  input [31:0] actual_bytes_transferred;
  input [7:0] error;
  input early_termination;

  input transfer_complete_IRQ_mask;
  input [7:0] error_IRQ_mask;
  input early_termination_IRQ_mask;
  input descriptor_buffer_full;



  wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
  wire fifo_full;
  wire fifo_empty;
  wire fifo_read;
  wire [FIFO_WIDTH-1:0] fifo_input;
  wire [FIFO_WIDTH-1:0] fifo_output;


  generate
    if (RESPONSE_PORT == 0)
    begin

      assign fifo_input = {early_termination, error, actual_bytes_transferred};  
      assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1);
      scfifo the_response_FIFO (
        .clock (clk),
        .aclr (reset),
        .sclr (sw_reset),
        .data (fifo_input),
        .wrreq (done_strobe),
        .rdreq (fifo_read),
        .q (fifo_output),
        .full (fifo_full),
        .empty (fifo_empty),
        .usedw (fifo_used)
      );
      defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
      defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
      defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
      defparam the_response_FIFO.lpm_showahead = "ON";
      defparam the_response_FIFO.use_eab = "ON";
      defparam the_response_FIFO.overflow_checking = "OFF";
      defparam the_response_FIFO.underflow_checking = "OFF";
      defparam the_response_FIFO.add_ram_output_register = "ON";
      defparam the_response_FIFO.lpm_type = "scfifo";


      assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
      assign mm_response_waitrequest = fifo_empty;
      assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used};
      assign response_fifo_full = fifo_full;
      assign response_fifo_empty = fifo_empty;


      assign src_response_data = 0;
      assign src_response_valid = 0;

    end
    else if (RESPONSE_PORT == 1)
    begin

      assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
      assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
      scfifo the_response_FIFO (
        .clock (clk),
        .aclr (reset | sw_reset),
        .data (fifo_input),
        .wrreq (done_strobe),
        .rdreq (fifo_read),
        .q (fifo_output),
        .full (fifo_full),
        .empty (fifo_empty),
        .usedw (fifo_used)
      );
      defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
      defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
      defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
      defparam the_response_FIFO.lpm_showahead = "ON";
      defparam the_response_FIFO.use_eab = "ON";
      defparam the_response_FIFO.overflow_checking = "OFF";
      defparam the_response_FIFO.underflow_checking = "OFF";
      defparam the_response_FIFO.add_ram_output_register = "ON";
      defparam the_response_FIFO.lpm_type = "scfifo";

      assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output};
      assign src_response_valid = (fifo_empty == 0);
      assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used};
      assign response_fifo_full = fifo_full;
      assign response_fifo_empty = fifo_empty;


      assign mm_response_readdata = 0;
      assign mm_response_waitrequest = 0;

    end
    else
    begin

      assign fifo_input = 0;
      assign fifo_output = 0;
      assign mm_response_readdata = 0;
      assign mm_response_waitrequest = 0;
      assign src_response_data = 0;
      assign src_response_valid = 0;
      assign response_watermark = 0;
      assign response_fifo_full = 0;
      assign response_fifo_empty = 0;

    end
  endgenerate

endmodule
module response_block (
  clk,
  reset,

  mm_response_readdata,
  mm_response_read,
  mm_response_address,
  mm_response_byteenable,
  mm_response_waitrequest,

  src_response_data,
  src_response_valid,
  src_response_ready,

  sw_reset,
  response_watermark,
  response_fifo_full,
  response_fifo_empty,
  done_strobe,
  actual_bytes_transferred,
  error,
  early_termination,
  transfer_complete_IRQ_mask,
  error_IRQ_mask,
  early_termination_IRQ_mask,
  descriptor_buffer_full
);



  parameter RESPONSE_PORT = 0;
  parameter FIFO_DEPTH = 256;
  parameter FIFO_DEPTH_LOG2 = 8;
  localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51;

  input clk;
  input reset;

  output wire [31:0] mm_response_readdata;
  input mm_response_read;
  input mm_response_address;
  input [3:0] mm_response_byteenable;
  output wire mm_response_waitrequest;

  output wire [255:0] src_response_data;
  output wire src_response_valid;
  input src_response_ready;

  input sw_reset;
  output wire [15:0] response_watermark;
  output wire response_fifo_full;
  output wire response_fifo_empty;
  input done_strobe;
  input [31:0] actual_bytes_transferred;
  input [7:0] error;
  input early_termination;

  input transfer_complete_IRQ_mask;
  input [7:0] error_IRQ_mask;
  input early_termination_IRQ_mask;
  input descriptor_buffer_full;



  wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
  wire fifo_full;
  wire fifo_empty;
  wire fifo_read;
  wire [FIFO_WIDTH-1:0] fifo_input;
  wire [FIFO_WIDTH-1:0] fifo_output;


  generate
    if (RESPONSE_PORT == 0)
    begin

      assign fifo_input = {early_termination, error, actual_bytes_transferred};  
      assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1);
      scfifo the_response_FIFO (
        .clock (clk),
        .aclr (reset),
        .sclr (sw_reset),
        .data (fifo_input),
        .wrreq (done_strobe),
        .rdreq (fifo_read),
        .q (fifo_output),
        .full (fifo_full),
        .empty (fifo_empty),
        .usedw (fifo_used)
      );
      defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
      defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
      defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
      defparam the_response_FIFO.lpm_showahead = "ON";
      defparam the_response_FIFO.use_eab = "ON";
      defparam the_response_FIFO.overflow_checking = "OFF";
      defparam the_response_FIFO.underflow_checking = "OFF";
      defparam the_response_FIFO.add_ram_output_register = "ON";
      defparam the_response_FIFO.lpm_type = "scfifo";


      assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
      assign mm_response_waitrequest = fifo_empty;
      assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used};
      assign response_fifo_full = fifo_full;
      assign response_fifo_empty = fifo_empty;


      assign src_response_data = 0;
      assign src_response_valid = 0;

    end
    else if (RESPONSE_PORT == 1)
    begin

      assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
      assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
      scfifo the_response_FIFO (
        .clock (clk),
        .aclr (reset | sw_reset),
        .data (fifo_input),
        .wrreq (done_strobe),
        .rdreq (fifo_read),
        .q (fifo_output),
        .full (fifo_full),
        .empty (fifo_empty),
        .usedw (fifo_used)
      );
      defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
      defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
      defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
      defparam the_response_FIFO.lpm_showahead = "ON";
      defparam the_response_FIFO.use_eab = "ON";
      defparam the_response_FIFO.overflow_checking = "OFF";
      defparam the_response_FIFO.underflow_checking = "OFF";
      defparam the_response_FIFO.add_ram_output_register = "ON";
      defparam the_response_FIFO.lpm_type = "scfifo";

      assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output};
      assign src_response_valid = (fifo_empty == 0);
      assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used};
      assign response_fifo_full = fifo_full;
      assign response_fifo_empty = fifo_empty;


      assign mm_response_readdata = 0;
      assign mm_response_waitrequest = 0;

    end
    else
    begin

      assign fifo_input = 0;
      assign fifo_output = 0;
      assign mm_response_readdata = 0;
      assign mm_response_waitrequest = 0;
      assign src_response_data = 0;
      assign src_response_valid = 0;
      assign response_watermark = 0;
      assign response_fifo_full = 0;
      assign response_fifo_empty = 0;

    end
  endgenerate

endmodule