data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0502/lab5.srcs/sources_1/imports/lab0401/lab0401.srcs/sources_1/new/registers.v
data/verilator_xmls/4e4e055e-b4d3-42d2-b15f-4ee4295746cc.xml
module registers(
    input [25:21] readReg1,
    input [20:16] readReg2,
    input [4:0] writeReg,
    input [31:0] writeData,
    input regWrite,
    input reset,
    
    output reg [31:0] readData1,
    output reg [31:0] readData2,
    
    input Clk,








	 output reg [31:0] R0,
	 output reg [31:0] R1,
	 output reg [31:0] R2,
	 output reg [31:0] R3,
	 output reg [31:0] R4,
	 output reg [31:0] R5,
	 output reg [31:0] R6,
	 output reg [31:0] R7    
    );
    
    reg [31:0] regFile [31:0];
    integer i=0;
    
    initial begin
            for(i=0; i<32; i=i+1)
            begin
                regFile[i]=0;
            end    
    end
    








	 
    always@ (readReg1 or readReg2 or writeReg)
        begin 
            readData1=regFile [readReg1];
            readData2=regFile [readReg2];
           	 R0=regFile[0];
	 R1=regFile[1];
	  R2=regFile[2];
	 R3=regFile[3];
	 R4=regFile[4];
	  R5=regFile[5];
	 R6=regFile[6];
	 R7=regFile[7];	 
        end
        
    always @ (negedge Clk)
        begin
            if(reset==1)
            begin
            for(i=0; i<32; i=i+1)
            begin
                regFile[i]=0;
            end
            end
            if(regWrite==1)
                begin
                    regFile[writeReg]=writeData;
                end
        end
        
        
endmodule
module registers(
    input [25:21] readReg1,
    input [20:16] readReg2,
    input [4:0] writeReg,
    input [31:0] writeData,
    input regWrite,
    input reset,
    
    output reg [31:0] readData1,
    output reg [31:0] readData2,
    
    input Clk,








	 output reg [31:0] R0,
	 output reg [31:0] R1,
	 output reg [31:0] R2,
	 output reg [31:0] R3,
	 output reg [31:0] R4,
	 output reg [31:0] R5,
	 output reg [31:0] R6,
	 output reg [31:0] R7    
    );

    
    reg [31:0] regFile [31:0];
    integer i=0;
    
    initial begin
            for(i=0; i<32; i=i+1)
            begin
                regFile[i]=0;
            end    
    end
    








	 
    always@ (readReg1 or readReg2 or writeReg)
        begin 
            readData1=regFile [readReg1];
            readData2=regFile [readReg2];
           	 R0=regFile[0];
	 R1=regFile[1];
	  R2=regFile[2];
	 R3=regFile[3];
	 R4=regFile[4];
	  R5=regFile[5];
	 R6=regFile[6];
	 R7=regFile[7];	 
        end
        
    always @ (negedge Clk)
        begin
            if(reset==1)
            begin
            for(i=0; i<32; i=i+1)
            begin
                regFile[i]=0;
            end
            end
            if(regWrite==1)
                begin
                    regFile[writeReg]=writeData;
                end
        end
        
        
endmodule