data/full_repos/permissive/135701568/flipflop.v
data/verilator_xmls/4d8ced5c-0770-4c9d-8f66-8b340b3ae1dd.xml
module flipflop(clk, rst, writeEn, in, out);
  input in, clk, rst, writeEn;
  output reg out;
  always @(posedge clk, posedge rst) begin
    if(rst) begin
      out <= 1'b0;
    end
    else begin
      if(writeEn) begin
        out <= in;
      end
    end
  end
endmodule
module flipflop(clk, rst, writeEn, in, out);

  input in, clk, rst, writeEn;
  output reg out;
  always @(posedge clk, posedge rst) begin
    if(rst) begin
      out <= 1'b0;
    end
    else begin
      if(writeEn) begin
        out <= in;
      end
    end
  end
endmodule