data/full_repos/permissive/102515926/Modules/CIRCUIT3.v
1: b"%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:18: Cannot find file containing module: 'ADD'\n    ADD #(16) ADD_1(a, b, l00);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.v\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.sv\n             ADD\n             ADD.v\n             ADD.sv\n             obj_dir/ADD\n             obj_dir/ADD.v\n             obj_dir/ADD.sv\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:19: Cannot find file containing module: 'ADD'\n    ADD #(16) ADD_2(c, d, l01);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:20: Cannot find file containing module: 'ADD'\n    ADD #(16) ADD_3(e, f, l02);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:21: Cannot find file containing module: 'ADD'\n    ADD #(16) ADD_4(g, h, l03);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:22: Cannot find file containing module: 'ADD'\n    ADD #(32) ADD_5(l00, l01, l10);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:23: Cannot find file containing module: 'ADD'\n    ADD #(32) ADD_6(l02, l03, l11);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:24: Cannot find file containing module: 'ADD'\n    ADD #(32) ADD_7(l10, l11, l2);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:25: Cannot find file containing module: 'SHR'\n    SHR #(32) SHR_1(l2, sa, l2div2);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:26: Cannot find file containing module: 'SHR'\n    SHR #(32) SHR_2(l2div2, sa, l2div4);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:27: Cannot find file containing module: 'SHR'\n    SHR #(32) SHR_3(l2div4, sa, l2div8);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT3.v:28: Cannot find file containing module: 'REG'\n    REG #(32) REG_1(l2div8, Clk, Rst, avg);\n    ^~~\n%Error: Exiting due to 11 error(s)\n"
module CIRCUIT3(a, b, c, d, e, f, g, h, sa, avg, Clk, Rst);
    input Clk, Rst;
    input [15:0] a, b, c, d, e, f, g, h;
    input [7:0] sa;
    
    output [15:0] avg;
    
    wire [31:0] l00, l01, l02, l03, l10, l11, l2, l2div2, l2div4, l2div8;
    
    ADD #(16) ADD_1(a, b, l00);
    ADD #(16) ADD_2(c, d, l01);
    ADD #(16) ADD_3(e, f, l02);
    ADD #(16) ADD_4(g, h, l03);
    ADD #(32) ADD_5(l00, l01, l10);
    ADD #(32) ADD_6(l02, l03, l11);
    ADD #(32) ADD_7(l10, l11, l2);
    SHR #(32) SHR_1(l2, sa, l2div2);
    SHR #(32) SHR_2(l2div2, sa, l2div4);
    SHR #(32) SHR_3(l2div4, sa, l2div8);
    REG #(32) REG_1(l2div8, Clk, Rst, avg);

endmodule
module CIRCUIT3(a, b, c, d, e, f, g, h, sa, avg, Clk, Rst);

    input Clk, Rst;
    input [15:0] a, b, c, d, e, f, g, h;
    input [7:0] sa;
    
    output [15:0] avg;
    
    wire [31:0] l00, l01, l02, l03, l10, l11, l2, l2div2, l2div4, l2div8;
    
    ADD #(16) ADD_1(a, b, l00);
    ADD #(16) ADD_2(c, d, l01);
    ADD #(16) ADD_3(e, f, l02);
    ADD #(16) ADD_4(g, h, l03);
    ADD #(32) ADD_5(l00, l01, l10);
    ADD #(32) ADD_6(l02, l03, l11);
    ADD #(32) ADD_7(l10, l11, l2);
    SHR #(32) SHR_1(l2, sa, l2div2);
    SHR #(32) SHR_2(l2div2, sa, l2div4);
    SHR #(32) SHR_3(l2div4, sa, l2div8);
    REG #(32) REG_1(l2div8, Clk, Rst, avg);

endmodule