data/full_repos/permissive/146399661/src/test.v
 line:158: before: "("
1: b'%Error: data/full_repos/permissive/146399661/src/test.v:12: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146399661/src,data/full_repos/permissive/146399661/constants.vh\n             data/full_repos/permissive/146399661/src,data/full_repos/permissive/146399661/constants.vh.v\n             data/full_repos/permissive/146399661/src,data/full_repos/permissive/146399661/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/test.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/test.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/test.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/test.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/test.v:125: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/test.v:127: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/test.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/test.v:155: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n'
module main;
`include "constants.vh"

reg clock,reset,enable;
reg [OPCODE_WIDTH-1:0] opcode;
reg [DATA_WIDTH-1:0] datain,addr;
wire [DATA_WIDTH-1:0] dataout;
wire cu_ready;
wire [STATUS_WIDTH-1:0] status;

fullsystem fs( clock,reset,enable,opcode,datain,addr,
               dataout,status,cu_ready
             );

initial begin

    $display("test >> Resetting Chakravyuh");

    addr = 0;
    opcode = 0;
    datain = 0;
    reset = 1'b1;
    enable = 0;
    #20;
    reset = 1'b0;



    if (cu_ready == 0) begin
        $display("test >> Chakravyuh is ready for authentication stage");
    end

    $display("test >> Performing authentication procedure");
    opcode = OPCODE_AUTH_START;
    enable = 1'b1;

    while (cu_ready != 1) begin
        #1;     
    end

    $display("test >> Received nonce {%d} from Chakravyuh",dataout);
    enable = 1'b0;

    while (cu_ready == 1) begin
        #1;
    end

    datain = 30;

    $display("test >> Sending encrypted nonce {%d} to Chakravyuh",datain);
    enable = 1'b1;

    while (cu_ready != 1) begin
        #1;
    end

    enable = 1'b0;


    $display("\n############ test >> Testing Memory write ############## \n");
    test_chakravyuh(OPCODE_MEM_WRITE,23,100);
    $display("\n############ test >> Testing Memory write ############## \n");
    test_chakravyuh(OPCODE_MEM_WRITE,123,121);
    $display("\n############ test >> Testing Memory write ############## \n");
    test_chakravyuh(OPCODE_MEM_WRITE,78,140);
    $display("\n############ test >> Testing Memory read ############## \n");
    test_chakravyuh(OPCODE_MEM_READ,23,100);
    $display("test >> Data read was %d", dataout);
    $display("\n############ test >> Testing Memory read ############## \n");
    test_chakravyuh(OPCODE_MEM_READ,23,121);
    $display("test >> Data read was %d", dataout);
    $display("\n############ test >> Testing Memory read ############## \n");
    test_chakravyuh(OPCODE_MEM_READ,23,140);
    $display("test >> Data read was %d", dataout);


    $display("\n############ test >> Testing RSA enc ############## \n");
    test_chakravyuh(OPCODE_RSA_ENC,9,140);
    $display("test >> Data read was %d", dataout);
    $display("\n############ test >> Testing RSA dec ############## \n");
    test_chakravyuh(OPCODE_RSA_DEC,48,140);
    $display("test >> Data read was %d", dataout);

    $display("\n############ test >> Testing RSA enc ############## \n");
    test_chakravyuh(OPCODE_RSA_ENC,54,140);
    $display("test >> Data read was %d", dataout);
    $display("\n############ test >> Testing RSA dec ############## \n");
    test_chakravyuh(OPCODE_RSA_DEC,76,140);
    $display("test >> Data read was %d", dataout);

    $display("\n############ test >> Testing RSA enc ############## \n");
    test_chakravyuh(OPCODE_RSA_ENC,96,140);
    $display("test >> Data read was %d", dataout);
    $display("\n############ test >> Testing RSA dec ############## \n");
    test_chakravyuh(OPCODE_RSA_DEC,112,140);
    $display("test >> Data read was %d", dataout);



end

always begin
    clock = 0;
    #5;
    clock = 1;
    #5;
end


task test_chakravyuh;
    input [OPCODE_WIDTH-1:0] temp_opcode;
    input [DATA_WIDTH-1:0] temp_datain,temp_addr;
begin

    $display("test >> Waiting for CU to get ready for next operation");

    enable = 1'b0;

    while (cu_ready != 1'b0) begin
        #1;
    end

    opcode = temp_opcode;
    datain = temp_datain;
    addr = temp_addr;

    $display("test >> Testing operation %d", opcode);

    enable = 1'b1;

    $display("test >> Waiting for ready signal");

    while (cu_ready == 1'b0) begin
        #1;
    end

    $display("test >> Got the ready signal, setting enable to zero");
    enable = 1'b0;

end
endtask

endmodule
module main;

`include "constants.vh"

reg clock,reset,enable;
reg [OPCODE_WIDTH-1:0] opcode;
reg [DATA_WIDTH-1:0] datain,addr;
wire [DATA_WIDTH-1:0] dataout;
wire cu_ready;
wire [STATUS_WIDTH-1:0] status;

fullsystem fs( clock,reset,enable,opcode,datain,addr,
               dataout,status,cu_ready
             );

initial begin

    $display("test >> Resetting Chakravyuh");

    addr = 0;
    opcode = 0;
    datain = 0;
    reset = 1'b1;
    enable = 0;
    #20;
    reset = 1'b0;



    if (cu_ready == 0) begin
        $display("test >> Chakravyuh is ready for authentication stage");
    end

    $display("test >> Performing authentication procedure");
    opcode = OPCODE_AUTH_START;
    enable = 1'b1;

    while (cu_ready != 1) begin
        #1;     
    end

    $display("test >> Received nonce {%d} from Chakravyuh",dataout);
    enable = 1'b0;

    while (cu_ready == 1) begin
        #1;
    end

    datain = 30;

    $display("test >> Sending encrypted nonce {%d} to Chakravyuh",datain);
    enable = 1'b1;

    while (cu_ready != 1) begin
        #1;
    end

    enable = 1'b0;


    $display("\n############ test >> Testing Memory write ############## \n");
    test_chakravyuh(OPCODE_MEM_WRITE,23,100);
    $display("\n############ test >> Testing Memory write ############## \n");
    test_chakravyuh(OPCODE_MEM_WRITE,123,121);
    $display("\n############ test >> Testing Memory write ############## \n");
    test_chakravyuh(OPCODE_MEM_WRITE,78,140);
    $display("\n############ test >> Testing Memory read ############## \n");
    test_chakravyuh(OPCODE_MEM_READ,23,100);
    $display("test >> Data read was %d", dataout);
    $display("\n############ test >> Testing Memory read ############## \n");
    test_chakravyuh(OPCODE_MEM_READ,23,121);
    $display("test >> Data read was %d", dataout);
    $display("\n############ test >> Testing Memory read ############## \n");
    test_chakravyuh(OPCODE_MEM_READ,23,140);
    $display("test >> Data read was %d", dataout);


    $display("\n############ test >> Testing RSA enc ############## \n");
    test_chakravyuh(OPCODE_RSA_ENC,9,140);
    $display("test >> Data read was %d", dataout);
    $display("\n############ test >> Testing RSA dec ############## \n");
    test_chakravyuh(OPCODE_RSA_DEC,48,140);
    $display("test >> Data read was %d", dataout);

    $display("\n############ test >> Testing RSA enc ############## \n");
    test_chakravyuh(OPCODE_RSA_ENC,54,140);
    $display("test >> Data read was %d", dataout);
    $display("\n############ test >> Testing RSA dec ############## \n");
    test_chakravyuh(OPCODE_RSA_DEC,76,140);
    $display("test >> Data read was %d", dataout);

    $display("\n############ test >> Testing RSA enc ############## \n");
    test_chakravyuh(OPCODE_RSA_ENC,96,140);
    $display("test >> Data read was %d", dataout);
    $display("\n############ test >> Testing RSA dec ############## \n");
    test_chakravyuh(OPCODE_RSA_DEC,112,140);
    $display("test >> Data read was %d", dataout);



end

always begin
    clock = 0;
    #5;
    clock = 1;
    #5;
end


task test_chakravyuh;
    input [OPCODE_WIDTH-1:0] temp_opcode;
    input [DATA_WIDTH-1:0] temp_datain,temp_addr;
begin

    $display("test >> Waiting for CU to get ready for next operation");

    enable = 1'b0;

    while (cu_ready != 1'b0) begin
        #1;
    end

    opcode = temp_opcode;
    datain = temp_datain;
    addr = temp_addr;

    $display("test >> Testing operation %d", opcode);

    enable = 1'b1;

    $display("test >> Waiting for ready signal");

    while (cu_ready == 1'b0) begin
        #1;
    end

    $display("test >> Got the ready signal, setting enable to zero");
    enable = 1'b0;

end
endtask

endmodule