data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fft_shift.v
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fft_shift.v:63: Cannot find file containing module: \'ram_2port\'\n  ram_2port #(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc,data/full_repos/permissive/214858095/ram_2port\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc,data/full_repos/permissive/214858095/ram_2port.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc,data/full_repos/permissive/214858095/ram_2port.sv\n             ram_2port\n             ram_2port.v\n             ram_2port.sv\n             obj_dir/ram_2port\n             obj_dir/ram_2port.v\n             obj_dir/ram_2port.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fft_shift.v:70: Cannot find file containing module: \'ram_2port\'\n  ram_2port #(\n  ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fft_shift.v:95: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 12 bits.\n                                                                                                                            : ... In instance fft_shift\n      fft_size_minus_1   <= fft_size-1;\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fft_shift.v:103: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 or 12 bits.\n                                                                                                                             : ... In instance fft_shift\n        fft_shift_mask   <= (fft_size-1) >> 1;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/fft_shift.v:105: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 12 bits.\n                                                                                                                             : ... In instance fft_shift\n        fft_shift_mask   <= fft_size >> 1;\n                         ^~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module fft_shift #(
  parameter MAX_FFT_SIZE_LOG2 = 11,
  parameter WIDTH = 32)
(
  input clk, input reset,
  input [1:0] config_tdata, input config_tvalid, output config_tready,
  input [$clog2(MAX_FFT_SIZE_LOG2+1)-1:0] fft_size_log2_tdata, input fft_size_log2_tvalid, output fft_size_log2_tready,
  input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, input [MAX_FFT_SIZE_LOG2-1:0] i_tuser,
  output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
);

  reg ping_pong;
  reg loading_pkt;
  reg [2:0] reconfig_stall;
  reg reverse, bypass;
  reg [$clog2(MAX_FFT_SIZE_LOG2+1)-1:0] fft_size_log2_reg;
  reg [MAX_FFT_SIZE_LOG2:0] fft_size;
  reg [MAX_FFT_SIZE_LOG2-1:0] fft_size_minus_1, fft_shift_mask;
  wire [WIDTH-1:0] ping_rd_data, pong_rd_data;
  reg [MAX_FFT_SIZE_LOG2-1:0] ping_rd_addr, pong_rd_addr;




  wire [MAX_FFT_SIZE_LOG2-1:0] ping_wr_addr = fft_shift_mask ^ i_tuser;
  wire [MAX_FFT_SIZE_LOG2-1:0] pong_wr_addr = fft_shift_mask ^ i_tuser;
  wire ping_wr_en = ping_pong ? i_tvalid & i_tready : 1'b0;
  wire pong_wr_en = ping_pong ? 1'b0                : i_tvalid & i_tready;

  wire ping_rd_en = ping_pong ? 1'b1                : o_tvalid & o_tready;
  wire pong_rd_en = ping_pong ? o_tvalid & o_tready : 1'b1;
  reg ping_loaded, pong_loaded;

  assign i_tready = (ping_pong ? ~ping_loaded       : ~pong_loaded) & ~reconfig_stall[2];
  reg ping_tlast, pong_tlast;

  assign o_tvalid = ping_pong ? pong_loaded         : ping_loaded;
  assign o_tlast = ping_pong ? pong_tlast           : ping_tlast;
  assign o_tdata = ping_pong ? pong_rd_data         : ping_rd_data;




  assign config_tready        = ~ping_loaded & ~pong_loaded & ~loading_pkt;
  assign fft_size_log2_tready = config_tready;

  ram_2port #(
    .DWIDTH(WIDTH),
    .AWIDTH(MAX_FFT_SIZE_LOG2))
  ping_ram_2port (
    .clka(clk),.ena(1'b1),.wea(ping_wr_en),.addra(ping_wr_addr),.dia(i_tdata),.doa(),
    .clkb(clk),.enb(ping_rd_en),.web(1'b0),.addrb(ping_rd_addr),.dib({WIDTH{1'b0}}),.dob(ping_rd_data));

  ram_2port #(
    .DWIDTH(WIDTH),
    .AWIDTH(MAX_FFT_SIZE_LOG2))
  pong_ram_2port (
    .clka(clk),.ena(1'b1),.wea(pong_wr_en),.addra(pong_wr_addr),.dia(i_tdata),.doa(),
    .clkb(clk),.enb(pong_rd_en),.web(1'b0),.addrb(pong_rd_addr),.dib({WIDTH{1'b0}}),.dob(pong_rd_data));

  always @(posedge clk) begin
    if (reset) begin
      ping_pong             <= 1'b1;
      ping_loaded           <= 1'b0;
      pong_loaded           <= 1'b0;
      ping_rd_addr          <= 0;
      pong_rd_addr          <= 0;
      ping_tlast            <= 1'b0;
      pong_tlast            <= 1'b0;
      fft_shift_mask        <= 0;
      fft_size_minus_1      <= 0;
      fft_size              <= 0;
      fft_size_log2_reg     <= 0;
      bypass                <= 1'b0;
      reverse               <= 1'b0;
      reconfig_stall        <= 3'd0;
      loading_pkt           <= 1'b0;
    end else begin
      fft_size_minus_1   <= fft_size-1;
      fft_size           <= 1 << fft_size_log2_reg;



      if (bypass) begin
        fft_shift_mask   <= 'd0;
      end else if (reverse) begin
        fft_shift_mask   <= (fft_size-1) >> 1;
      end else begin
        fft_shift_mask   <= fft_size >> 1;
      end


      if (config_tready & config_tvalid) begin
        reverse           <= config_tdata[0];
        bypass            <= config_tdata[1];
        reconfig_stall    <= 3'b100;
      end


      if (fft_size_log2_tready & fft_size_log2_tvalid) begin
        fft_size_log2_reg <= fft_size_log2_tdata[$clog2(MAX_FFT_SIZE_LOG2)-1:0];
        reconfig_stall    <= 3'b111;
      end
      if (~(config_tready & config_tvalid) & ~(fft_size_log2_tready & fft_size_log2_tvalid)) begin
        reconfig_stall[0] <= 1'b0;
        reconfig_stall[2:1] <= reconfig_stall[1:0];
      end


      if (i_tvalid & i_tready & ~i_tlast & ~loading_pkt) begin
        loading_pkt <= 1'b1;
      end else if (i_tvalid & i_tready & i_tlast & loading_pkt) begin
        loading_pkt <= 1'b0;
      end



      if (ping_pong) begin

        if (pong_loaded & o_tready & o_tvalid) begin

          if (pong_tlast) begin

            if (ping_loaded | (i_tvalid & i_tready & i_tlast)) begin
              ping_pong <= ~ping_pong;
            end
            pong_tlast   <= 1'b0;
            pong_loaded  <= 1'b0;
            pong_rd_addr <= 0;
          end else begin
            pong_rd_addr <= pong_rd_addr + 1;
          end
          if (pong_rd_addr == fft_size_minus_1) begin
            pong_tlast <= 1'b1;
          end
        end

        if (i_tvalid & i_tready & i_tlast) begin

          ping_rd_addr <= 1;
          ping_loaded  <= 1'b1;

          if (~pong_loaded) begin
            ping_pong <= ~ping_pong;
          end
        end

        if (ping_loaded & (pong_loaded & o_tvalid & o_tlast)) begin
          ping_pong <= ~ping_pong;
        end

      end else begin
        if (ping_loaded & o_tready & o_tvalid) begin
          if (ping_tlast) begin
            if (pong_loaded | (i_tvalid & i_tready & i_tlast)) begin
              ping_pong <= ~ping_pong;
            end
            ping_tlast   <= 1'b0;
            ping_loaded  <= 1'b0;
            ping_rd_addr <= 0;
          end else begin
            ping_rd_addr <= ping_rd_addr + 1;
          end
          if (ping_rd_addr == fft_size_minus_1) begin
            ping_tlast <= 1'b1;
          end
        end
        if (i_tvalid & i_tready & i_tlast) begin
          pong_rd_addr <= 1;
          pong_loaded  <= 1'b1;
          if (~ping_loaded | (ping_loaded & o_tvalid & o_tlast)) begin
            ping_pong <= ~ping_pong;
          end
        end
        if (pong_loaded & (ping_loaded & o_tvalid & o_tlast)) begin
          ping_pong <= ~ping_pong;
        end
      end
    end
  end

endmodule
module fft_shift #(
  parameter MAX_FFT_SIZE_LOG2 = 11,
  parameter WIDTH = 32)
(
  input clk, input reset,
  input [1:0] config_tdata, input config_tvalid, output config_tready,
  input [$clog2(MAX_FFT_SIZE_LOG2+1)-1:0] fft_size_log2_tdata, input fft_size_log2_tvalid, output fft_size_log2_tready,
  input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, input [MAX_FFT_SIZE_LOG2-1:0] i_tuser,
  output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
);


  reg ping_pong;
  reg loading_pkt;
  reg [2:0] reconfig_stall;
  reg reverse, bypass;
  reg [$clog2(MAX_FFT_SIZE_LOG2+1)-1:0] fft_size_log2_reg;
  reg [MAX_FFT_SIZE_LOG2:0] fft_size;
  reg [MAX_FFT_SIZE_LOG2-1:0] fft_size_minus_1, fft_shift_mask;
  wire [WIDTH-1:0] ping_rd_data, pong_rd_data;
  reg [MAX_FFT_SIZE_LOG2-1:0] ping_rd_addr, pong_rd_addr;




  wire [MAX_FFT_SIZE_LOG2-1:0] ping_wr_addr = fft_shift_mask ^ i_tuser;
  wire [MAX_FFT_SIZE_LOG2-1:0] pong_wr_addr = fft_shift_mask ^ i_tuser;
  wire ping_wr_en = ping_pong ? i_tvalid & i_tready : 1'b0;
  wire pong_wr_en = ping_pong ? 1'b0                : i_tvalid & i_tready;

  wire ping_rd_en = ping_pong ? 1'b1                : o_tvalid & o_tready;
  wire pong_rd_en = ping_pong ? o_tvalid & o_tready : 1'b1;
  reg ping_loaded, pong_loaded;

  assign i_tready = (ping_pong ? ~ping_loaded       : ~pong_loaded) & ~reconfig_stall[2];
  reg ping_tlast, pong_tlast;

  assign o_tvalid = ping_pong ? pong_loaded         : ping_loaded;
  assign o_tlast = ping_pong ? pong_tlast           : ping_tlast;
  assign o_tdata = ping_pong ? pong_rd_data         : ping_rd_data;




  assign config_tready        = ~ping_loaded & ~pong_loaded & ~loading_pkt;
  assign fft_size_log2_tready = config_tready;

  ram_2port #(
    .DWIDTH(WIDTH),
    .AWIDTH(MAX_FFT_SIZE_LOG2))
  ping_ram_2port (
    .clka(clk),.ena(1'b1),.wea(ping_wr_en),.addra(ping_wr_addr),.dia(i_tdata),.doa(),
    .clkb(clk),.enb(ping_rd_en),.web(1'b0),.addrb(ping_rd_addr),.dib({WIDTH{1'b0}}),.dob(ping_rd_data));

  ram_2port #(
    .DWIDTH(WIDTH),
    .AWIDTH(MAX_FFT_SIZE_LOG2))
  pong_ram_2port (
    .clka(clk),.ena(1'b1),.wea(pong_wr_en),.addra(pong_wr_addr),.dia(i_tdata),.doa(),
    .clkb(clk),.enb(pong_rd_en),.web(1'b0),.addrb(pong_rd_addr),.dib({WIDTH{1'b0}}),.dob(pong_rd_data));

  always @(posedge clk) begin
    if (reset) begin
      ping_pong             <= 1'b1;
      ping_loaded           <= 1'b0;
      pong_loaded           <= 1'b0;
      ping_rd_addr          <= 0;
      pong_rd_addr          <= 0;
      ping_tlast            <= 1'b0;
      pong_tlast            <= 1'b0;
      fft_shift_mask        <= 0;
      fft_size_minus_1      <= 0;
      fft_size              <= 0;
      fft_size_log2_reg     <= 0;
      bypass                <= 1'b0;
      reverse               <= 1'b0;
      reconfig_stall        <= 3'd0;
      loading_pkt           <= 1'b0;
    end else begin
      fft_size_minus_1   <= fft_size-1;
      fft_size           <= 1 << fft_size_log2_reg;



      if (bypass) begin
        fft_shift_mask   <= 'd0;
      end else if (reverse) begin
        fft_shift_mask   <= (fft_size-1) >> 1;
      end else begin
        fft_shift_mask   <= fft_size >> 1;
      end


      if (config_tready & config_tvalid) begin
        reverse           <= config_tdata[0];
        bypass            <= config_tdata[1];
        reconfig_stall    <= 3'b100;
      end


      if (fft_size_log2_tready & fft_size_log2_tvalid) begin
        fft_size_log2_reg <= fft_size_log2_tdata[$clog2(MAX_FFT_SIZE_LOG2)-1:0];
        reconfig_stall    <= 3'b111;
      end
      if (~(config_tready & config_tvalid) & ~(fft_size_log2_tready & fft_size_log2_tvalid)) begin
        reconfig_stall[0] <= 1'b0;
        reconfig_stall[2:1] <= reconfig_stall[1:0];
      end


      if (i_tvalid & i_tready & ~i_tlast & ~loading_pkt) begin
        loading_pkt <= 1'b1;
      end else if (i_tvalid & i_tready & i_tlast & loading_pkt) begin
        loading_pkt <= 1'b0;
      end



      if (ping_pong) begin

        if (pong_loaded & o_tready & o_tvalid) begin

          if (pong_tlast) begin

            if (ping_loaded | (i_tvalid & i_tready & i_tlast)) begin
              ping_pong <= ~ping_pong;
            end
            pong_tlast   <= 1'b0;
            pong_loaded  <= 1'b0;
            pong_rd_addr <= 0;
          end else begin
            pong_rd_addr <= pong_rd_addr + 1;
          end
          if (pong_rd_addr == fft_size_minus_1) begin
            pong_tlast <= 1'b1;
          end
        end

        if (i_tvalid & i_tready & i_tlast) begin

          ping_rd_addr <= 1;
          ping_loaded  <= 1'b1;

          if (~pong_loaded) begin
            ping_pong <= ~ping_pong;
          end
        end

        if (ping_loaded & (pong_loaded & o_tvalid & o_tlast)) begin
          ping_pong <= ~ping_pong;
        end

      end else begin
        if (ping_loaded & o_tready & o_tvalid) begin
          if (ping_tlast) begin
            if (pong_loaded | (i_tvalid & i_tready & i_tlast)) begin
              ping_pong <= ~ping_pong;
            end
            ping_tlast   <= 1'b0;
            ping_loaded  <= 1'b0;
            ping_rd_addr <= 0;
          end else begin
            ping_rd_addr <= ping_rd_addr + 1;
          end
          if (ping_rd_addr == fft_size_minus_1) begin
            ping_tlast <= 1'b1;
          end
        end
        if (i_tvalid & i_tready & i_tlast) begin
          pong_rd_addr <= 1;
          pong_loaded  <= 1'b1;
          if (~ping_loaded | (ping_loaded & o_tvalid & o_tlast)) begin
            ping_pong <= ~ping_pong;
          end
        end
        if (pong_loaded & (ping_loaded & o_tvalid & o_tlast)) begin
          ping_pong <= ~ping_pong;
        end
      end
    end
  end

endmodule