data/full_repos/permissive/194450802/draw_player.v
data/verilator_xmls/0ee1f1be-3870-4e24-ab9d-9a0546a01595.xml
module _draw_player_datapath(clock, reset,
                             x, y,
                             vga_x, vga_y, vga_colour,
                             load, reset_counter, increment_counter, add_offset, counter_at_max);
    input clock;
    input reset;


    input [13:0] x;
    input [12:0] y;


    output [7:0] vga_x;
    output [6:0] vga_y;
    output [17:0] vga_colour;


    input load;
    input reset_counter;
    input increment_counter;
    input add_offset;
    output counter_at_max;


    reg [7:0] x_base;
    reg [6:0] y_base;


    reg [7:0] vga_x;
    reg [6:0] vga_y;
    reg [17:0] vga_colour;


    reg [1:0] counter;
    wire x_offset;
    wire y_offset;
    assign x_offset = counter[0];
    assign y_offset = counter[1];


    always @(posedge clock) begin
        if (reset) begin
            x_base <= 8'b0;
            y_base <= 7'b0;
            vga_x <= 8'b0;
            vga_y <= 7'b0;
            vga_colour <= 18'b0;
        end
        else begin
            if (load) begin
              x_base <= x[13:6];
              y_base <= y[12:6];
              vga_colour <= 18'b000111000111000111;
            end
            if (add_offset) begin
                vga_x <= x_base + {7'b0, x_offset};
                vga_y <= y_base + {6'b0, y_offset};
            end
        end
    end


    always @(posedge clock) begin
        if (reset_counter | reset) begin
            counter <= 2'b0;
        end
        else if (increment_counter) begin
            counter <= counter + 1;
        end
    end
    assign counter_at_max = &counter;
endmodule
module _draw_player_datapath(clock, reset,
                             x, y,
                             vga_x, vga_y, vga_colour,
                             load, reset_counter, increment_counter, add_offset, counter_at_max);

    input clock;
    input reset;


    input [13:0] x;
    input [12:0] y;


    output [7:0] vga_x;
    output [6:0] vga_y;
    output [17:0] vga_colour;


    input load;
    input reset_counter;
    input increment_counter;
    input add_offset;
    output counter_at_max;


    reg [7:0] x_base;
    reg [6:0] y_base;


    reg [7:0] vga_x;
    reg [6:0] vga_y;
    reg [17:0] vga_colour;


    reg [1:0] counter;
    wire x_offset;
    wire y_offset;
    assign x_offset = counter[0];
    assign y_offset = counter[1];


    always @(posedge clock) begin
        if (reset) begin
            x_base <= 8'b0;
            y_base <= 7'b0;
            vga_x <= 8'b0;
            vga_y <= 7'b0;
            vga_colour <= 18'b0;
        end
        else begin
            if (load) begin
              x_base <= x[13:6];
              y_base <= y[12:6];
              vga_colour <= 18'b000111000111000111;
            end
            if (add_offset) begin
                vga_x <= x_base + {7'b0, x_offset};
                vga_y <= y_base + {6'b0, y_offset};
            end
        end
    end


    always @(posedge clock) begin
        if (reset_counter | reset) begin
            counter <= 2'b0;
        end
        else if (increment_counter) begin
            counter <= counter + 1;
        end
    end
    assign counter_at_max = &counter;
endmodule