data/full_repos/permissive/133043770/MIDIIn.v
data/verilator_xmls/dc251a9f-49e0-4dd5-aa7f-0e7683ef2b68.xml
module MIDIIn(
	input clock,
	input uartStream,
	output [7:0] byteOutput,
	output byteOutputReady
    );

	reg[10:0] clkCounter = 0;
	reg[3:0] bitCounter = 0;
	reg[7:0] byteInput = 0;
	reg byteReady = 0;
	reg startBit = 1;
	reg endBit = 0;
	reg readBit = 0;
	reg readByte = 0;

	


	





	always @(posedge clock) begin

		if (readByte == 0 && uartStream == 0) begin

			readByte <= 1;
			readBit <= 1;
			byteReady <= 0;
			clkCounter = 0;
			bitCounter = 0;
		end
		

		if (readByte == 1) begin
			clkCounter = clkCounter + 1;
			if (clkCounter == 200) begin

				readBit <= 1;
			end
			else if (clkCounter == 1600) begin

				clkCounter = 0;
				bitCounter = bitCounter + 1;
			end
		end
		

	    if (readBit == 1) begin
			if (startBit == 0) begin
				if (bitCounter == 9) begin
					endBit <= uartStream;
				end
				else if (bitCounter < 9) begin
					byteInput[bitCounter - 1] <= uartStream;
				end
			end
			else begin
				startBit <= uartStream;
			end

			readBit <= 0;
		end
		
		if (bitCounter == 9 && startBit == 0) begin


			if (endBit == 1) begin
				byteReady <= 1;
			end
		end
		else if (bitCounter == 10) begin

			readBit <= 0;
			readByte <= 0;
			startBit <= 1;
			endBit <= 0;
		end
	end

	assign byteOutput = byteInput;
	assign byteOutputReady = byteReady;
	
endmodule
module MIDIIn(
	input clock,
	input uartStream,
	output [7:0] byteOutput,
	output byteOutputReady
    );


	reg[10:0] clkCounter = 0;
	reg[3:0] bitCounter = 0;
	reg[7:0] byteInput = 0;
	reg byteReady = 0;
	reg startBit = 1;
	reg endBit = 0;
	reg readBit = 0;
	reg readByte = 0;

	


	





	always @(posedge clock) begin

		if (readByte == 0 && uartStream == 0) begin

			readByte <= 1;
			readBit <= 1;
			byteReady <= 0;
			clkCounter = 0;
			bitCounter = 0;
		end
		

		if (readByte == 1) begin
			clkCounter = clkCounter + 1;
			if (clkCounter == 200) begin

				readBit <= 1;
			end
			else if (clkCounter == 1600) begin

				clkCounter = 0;
				bitCounter = bitCounter + 1;
			end
		end
		

	    if (readBit == 1) begin
			if (startBit == 0) begin
				if (bitCounter == 9) begin
					endBit <= uartStream;
				end
				else if (bitCounter < 9) begin
					byteInput[bitCounter - 1] <= uartStream;
				end
			end
			else begin
				startBit <= uartStream;
			end

			readBit <= 0;
		end
		
		if (bitCounter == 9 && startBit == 0) begin


			if (endBit == 1) begin
				byteReady <= 1;
			end
		end
		else if (bitCounter == 10) begin

			readBit <= 0;
			readByte <= 0;
			startBit <= 1;
			endBit <= 0;
		end
	end

	assign byteOutput = byteInput;
	assign byteOutputReady = byteReady;
	
endmodule