data/full_repos/permissive/188795755/elec_design/beta1/src/motor.v
data/verilator_xmls/2c62b873-9adf-4e34-b119-65610efcc545.xml
module  motor(

        input                   sclk                    ,  
        input                   s_rst_n                 ,

        input                   direct                  ,
        input                   stepenable              ,

        output  reg     [ 3:0]  stepdrive
);





parameter       STEPLOCKOUT     =       32'd40_000             ;

reg     [ 2:0]          state                           ; 
reg     [31:0]          stepcounter                     ;





always @(posedge sclk or negedge s_rst_n) begin 
        if(!s_rst_n)
                stepcounter     <=      32'b0;
        else if(stepcounter >= STEPLOCKOUT)
                stepcounter     <=      32'b0; 
        else if(stepenable == 1'b1)
                stepcounter     <=      stepcounter + 31'b1;                
end

always @(posedge sclk or negedge s_rst_n) begin 
        if(!s_rst_n)
                state   <=      3'b0;
        else if(direct == 1'b1 && stepcounter >= STEPLOCKOUT)
                state   <=      state + 3'b001; 
        else if(direct == 1'b0 && stepcounter >= STEPLOCKOUT)
                state   <=      state - 3'b001; 
end

always @(posedge sclk or negedge s_rst_n) begin 
        if(!s_rst_n) 
                stepdrive       <=      4'b0;
        else case(state)
                3'b000: stepdrive       <=      4'b0001; 
                3'b001: stepdrive       <=      4'b0011; 
                3'b010: stepdrive       <=      4'b0010; 
                3'b011: stepdrive       <=      4'b0110; 
                3'b100: stepdrive       <=      4'b0100; 
                3'b101: stepdrive       <=      4'b1100; 
                3'b110: stepdrive       <=      4'b1000; 
                3'b111: stepdrive       <=      4'b1001; 
        endcase        
end

endmodule
module  motor(

        input                   sclk                    ,  
        input                   s_rst_n                 ,

        input                   direct                  ,
        input                   stepenable              ,

        output  reg     [ 3:0]  stepdrive
);






parameter       STEPLOCKOUT     =       32'd40_000             ;

reg     [ 2:0]          state                           ; 
reg     [31:0]          stepcounter                     ;





always @(posedge sclk or negedge s_rst_n) begin 
        if(!s_rst_n)
                stepcounter     <=      32'b0;
        else if(stepcounter >= STEPLOCKOUT)
                stepcounter     <=      32'b0; 
        else if(stepenable == 1'b1)
                stepcounter     <=      stepcounter + 31'b1;                
end

always @(posedge sclk or negedge s_rst_n) begin 
        if(!s_rst_n)
                state   <=      3'b0;
        else if(direct == 1'b1 && stepcounter >= STEPLOCKOUT)
                state   <=      state + 3'b001; 
        else if(direct == 1'b0 && stepcounter >= STEPLOCKOUT)
                state   <=      state - 3'b001; 
end

always @(posedge sclk or negedge s_rst_n) begin 
        if(!s_rst_n) 
                stepdrive       <=      4'b0;
        else case(state)
                3'b000: stepdrive       <=      4'b0001; 
                3'b001: stepdrive       <=      4'b0011; 
                3'b010: stepdrive       <=      4'b0010; 
                3'b011: stepdrive       <=      4'b0110; 
                3'b100: stepdrive       <=      4'b0100; 
                3'b101: stepdrive       <=      4'b1100; 
                3'b110: stepdrive       <=      4'b1000; 
                3'b111: stepdrive       <=      4'b1001; 
        endcase        
end

endmodule