data/full_repos/permissive/210844779/lab2/2.1.1/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.1.1/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/210844779/lab2/2.1.1/tb.v:6: Cannot find file containing module: \'decoder2x4\'\ndecoder2x4 u0(.A(A),.B(B),.En(En),.Y(Y));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab2/2.1.1,data/full_repos/permissive/210844779/decoder2x4\n             data/full_repos/permissive/210844779/lab2/2.1.1,data/full_repos/permissive/210844779/decoder2x4.v\n             data/full_repos/permissive/210844779/lab2/2.1.1,data/full_repos/permissive/210844779/decoder2x4.sv\n             decoder2x4\n             decoder2x4.v\n             decoder2x4.sv\n             obj_dir/decoder2x4\n             obj_dir/decoder2x4.v\n             obj_dir/decoder2x4.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab2/2.1.1/tb.v:11: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                       : ... In instance tb\nA= $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab2/2.1.1/tb.v:12: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                       : ... In instance tb\nB= $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab2/2.1.1/tb.v:13: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                       : ... In instance tb\nEn= $random;\n  ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

reg A,B,En;
wire [3:0]Y;

decoder2x4 u0(.A(A),.B(B),.En(En),.Y(Y));

always 
begin

A= $random;
B= $random;
En= $random;
 #10;
end

endmodule
module tb();


reg A,B,En;
wire [3:0]Y;

decoder2x4 u0(.A(A),.B(B),.En(En),.Y(Y));

always 
begin

A= $random;
B= $random;
En= $random;
 #10;
end

endmodule