data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v
1: b'%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:3: Cannot find include file: common.vh\n`include "common.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc,data/full_repos/permissive/200650987/common.vh\n             data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc,data/full_repos/permissive/200650987/common.vh.v\n             data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc,data/full_repos/permissive/200650987/common.vh.sv\n             common.vh\n             common.vh.v\n             common.vh.sv\n             obj_dir/common.vh\n             obj_dir/common.vh.v\n             obj_dir/common.vh.sv\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:17: Define or directive not defined: \'`I_ALU_ADD\'\n  wire alu_add    = ALUop[`I_ALU_ADD];\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:17: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire alu_add    = ALUop[`I_ALU_ADD];\n                                    ^\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:18: Define or directive not defined: \'`I_ALU_SUB\'\n  wire alu_sub    = ALUop[`I_ALU_SUB];\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:18: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire alu_sub    = ALUop[`I_ALU_SUB];\n                                    ^\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:19: Define or directive not defined: \'`I_ALU_AND\'\n  wire alu_and    = ALUop[`I_ALU_AND];\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire alu_and    = ALUop[`I_ALU_AND];\n                                    ^\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:20: Define or directive not defined: \'`I_ALU_OR\'\n  wire alu_or     = ALUop[`I_ALU_OR];\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire alu_or     = ALUop[`I_ALU_OR];\n                                   ^\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:21: Define or directive not defined: \'`I_ALU_XOR\'\n  wire alu_xor    = ALUop[`I_ALU_XOR];\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire alu_xor    = ALUop[`I_ALU_XOR];\n                                    ^\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:22: Define or directive not defined: \'`I_ALU_NOR\'\n  wire alu_nor    = ALUop[`I_ALU_NOR];\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire alu_nor    = ALUop[`I_ALU_NOR];\n                                    ^\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:23: Define or directive not defined: \'`I_ALU_SLT\'\n  wire alu_slt    = ALUop[`I_ALU_SLT];\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire alu_slt    = ALUop[`I_ALU_SLT];\n                                    ^\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:24: Define or directive not defined: \'`I_ALU_SLTU\'\n  wire alu_sltu   = ALUop[`I_ALU_SLTU];\n                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire alu_sltu   = ALUop[`I_ALU_SLTU];\n                                     ^\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:25: Define or directive not defined: \'`I_ALU_SLL\'\n  wire alu_sll    = ALUop[`I_ALU_SLL];\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire alu_sll    = ALUop[`I_ALU_SLL];\n                                    ^\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:26: Define or directive not defined: \'`I_ALU_SRL\'\n  wire alu_srl    = ALUop[`I_ALU_SRL];\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:26: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire alu_srl    = ALUop[`I_ALU_SRL];\n                                    ^\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:27: Define or directive not defined: \'`I_ALU_SRA\'\n  wire alu_sra    = ALUop[`I_ALU_SRA];\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/200650987/src/verilog/outdated/dcache_ready_soc/alu.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire alu_sra    = ALUop[`I_ALU_SRA];\n                                    ^\n%Error: Exiting due to 23 error(s)\n'
module alu(
  input [31:0] A,
  input [31:0] B,
  input [10:0] ALUop,
  output Overflow,
  output CarryOut,
  output Zero,
  output [31:0] Result
);


  wire alu_add    = ALUop[`I_ALU_ADD];
  wire alu_sub    = ALUop[`I_ALU_SUB];
  wire alu_and    = ALUop[`I_ALU_AND];
  wire alu_or     = ALUop[`I_ALU_OR];
  wire alu_xor    = ALUop[`I_ALU_XOR];
  wire alu_nor    = ALUop[`I_ALU_NOR];
  wire alu_slt    = ALUop[`I_ALU_SLT];
  wire alu_sltu   = ALUop[`I_ALU_SLTU];
  wire alu_sll    = ALUop[`I_ALU_SLL];
  wire alu_srl    = ALUop[`I_ALU_SRL];
  wire alu_sra    = ALUop[`I_ALU_SRA];


  wire invb = alu_sub | alu_slt | alu_sltu;

  wire [31:0] addend = invb ? (~B) : B;


  wire cf;

  wire [31:0] add_sub_res;

  assign {cf, add_sub_res} = A + addend + invb;

  wire of = A[31] ^ addend[31] ^ cf ^ add_sub_res[31];


  wire [31:0] and_res = A & B;

  wire [31:0] or_res = A | B;

  wire [31:0] xor_res = A ^ B;

  wire [31:0] nor_res = ~or_res;

  wire [31:0] slt_res = (add_sub_res[31] ^ of) ? 1 : 0;
  wire [31:0] sltu_res = (!cf) ? 1 : 0;

  wire [31:0] sll_res = B << A[4:0];

  wire [64:0] sr_res_64 = {{32{alu_sra&B[31]}}, B} >> A[4:0];
  wire [31:0] sr_res = sr_res_64[31:0]; 


  wire [31:0] res =
    {32{alu_and}} & and_res |
    {32{alu_or}} & or_res |
    {32{alu_xor}} & xor_res |
    {32{alu_nor}} & nor_res |
    {32{alu_add}} & add_sub_res |
    {32{alu_sub}} & add_sub_res |
    {32{alu_slt}} & slt_res |
    {32{alu_sltu}} & sltu_res |
    {32{alu_sll}} & sll_res |
    {32{alu_srl}} & sr_res |
    {32{alu_sra}} & sr_res;


  wire zf = (res == 0);


  assign Overflow = of;
  assign CarryOut = cf ^ invb;
  assign Zero = zf;
  assign Result = res;
  
endmodule
module alu(
  input [31:0] A,
  input [31:0] B,
  input [10:0] ALUop,
  output Overflow,
  output CarryOut,
  output Zero,
  output [31:0] Result
);



  wire alu_add    = ALUop[`I_ALU_ADD];
  wire alu_sub    = ALUop[`I_ALU_SUB];
  wire alu_and    = ALUop[`I_ALU_AND];
  wire alu_or     = ALUop[`I_ALU_OR];
  wire alu_xor    = ALUop[`I_ALU_XOR];
  wire alu_nor    = ALUop[`I_ALU_NOR];
  wire alu_slt    = ALUop[`I_ALU_SLT];
  wire alu_sltu   = ALUop[`I_ALU_SLTU];
  wire alu_sll    = ALUop[`I_ALU_SLL];
  wire alu_srl    = ALUop[`I_ALU_SRL];
  wire alu_sra    = ALUop[`I_ALU_SRA];


  wire invb = alu_sub | alu_slt | alu_sltu;

  wire [31:0] addend = invb ? (~B) : B;


  wire cf;

  wire [31:0] add_sub_res;

  assign {cf, add_sub_res} = A + addend + invb;

  wire of = A[31] ^ addend[31] ^ cf ^ add_sub_res[31];


  wire [31:0] and_res = A & B;

  wire [31:0] or_res = A | B;

  wire [31:0] xor_res = A ^ B;

  wire [31:0] nor_res = ~or_res;

  wire [31:0] slt_res = (add_sub_res[31] ^ of) ? 1 : 0;
  wire [31:0] sltu_res = (!cf) ? 1 : 0;

  wire [31:0] sll_res = B << A[4:0];

  wire [64:0] sr_res_64 = {{32{alu_sra&B[31]}}, B} >> A[4:0];
  wire [31:0] sr_res = sr_res_64[31:0]; 


  wire [31:0] res =
    {32{alu_and}} & and_res |
    {32{alu_or}} & or_res |
    {32{alu_xor}} & xor_res |
    {32{alu_nor}} & nor_res |
    {32{alu_add}} & add_sub_res |
    {32{alu_sub}} & add_sub_res |
    {32{alu_slt}} & slt_res |
    {32{alu_sltu}} & sltu_res |
    {32{alu_sll}} & sll_res |
    {32{alu_srl}} & sr_res |
    {32{alu_sra}} & sr_res;


  wire zf = (res == 0);


  assign Overflow = of;
  assign CarryOut = cf ^ invb;
  assign Zero = zf;
  assign Result = res;
  
endmodule