data/full_repos/permissive/131249673/MIPS_L_PipeLine/work/HazardDetector.v
data/verilator_xmls/b93f3713-d1cf-4b3a-b8ef-52bcc913c143.xml
module HazardDetector ( clk, rst, 
	rs_ID, rt_ID, 
	MemRead_EX, WriteDst_EX,
	PC_Write, Reg_ID_EX_Control_Mux,
	brSignal, EX_ctrl_regWr,
	stallSignal
	);

	
	input	clk, rst;
	input	[4:0]	rs_ID;
	input	[4:0]	rt_ID;
	input			MemRead_EX;
	input	[4:0]	WriteDst_EX;
	input    brSignal;
	input    EX_ctrl_regWr;

	output			PC_Write;
	output			stallSignal;
	output			Reg_ID_EX_Control_Mux;

	wire	[4:0]	WriteDst_EX;
	wire	[4:0]	rt_ID;
	wire	[4:0]	rs_ID;
	wire			MemRead_EX;
  
	reg PC_Write;
	reg	stallSignal;
	reg Reg_ID_EX_Control_Mux;
	reg lwH;
	reg	brH;
  
	always @(*) begin
		stallSignal = 0;
		Reg_ID_EX_Control_Mux = 0;
		PC_Write = 1;
		
		lwH = MemRead_EX & ((WriteDst_EX == rt_ID) || WriteDst_EX == rs_ID) & !((WriteDst_EX == 0) || (rt_ID == 0) || (rs_ID == 0));
		brH = brSignal & EX_ctrl_regWr & ((WriteDst_EX == rt_ID) || (WriteDst_EX == rs_ID));
		if (lwH || brH)
		begin

		stallSignal = 1;
		Reg_ID_EX_Control_Mux = 1;
		end
	end
endmodule
module HazardDetector ( clk, rst, 
	rs_ID, rt_ID, 
	MemRead_EX, WriteDst_EX,
	PC_Write, Reg_ID_EX_Control_Mux,
	brSignal, EX_ctrl_regWr,
	stallSignal
	);


	
	input	clk, rst;
	input	[4:0]	rs_ID;
	input	[4:0]	rt_ID;
	input			MemRead_EX;
	input	[4:0]	WriteDst_EX;
	input    brSignal;
	input    EX_ctrl_regWr;

	output			PC_Write;
	output			stallSignal;
	output			Reg_ID_EX_Control_Mux;

	wire	[4:0]	WriteDst_EX;
	wire	[4:0]	rt_ID;
	wire	[4:0]	rs_ID;
	wire			MemRead_EX;
  
	reg PC_Write;
	reg	stallSignal;
	reg Reg_ID_EX_Control_Mux;
	reg lwH;
	reg	brH;
  
	always @(*) begin
		stallSignal = 0;
		Reg_ID_EX_Control_Mux = 0;
		PC_Write = 1;
		
		lwH = MemRead_EX & ((WriteDst_EX == rt_ID) || WriteDst_EX == rs_ID) & !((WriteDst_EX == 0) || (rt_ID == 0) || (rs_ID == 0));
		brH = brSignal & EX_ctrl_regWr & ((WriteDst_EX == rt_ID) || (WriteDst_EX == rs_ID));
		if (lwH || brH)
		begin

		stallSignal = 1;
		Reg_ID_EX_Control_Mux = 1;
		end
	end
endmodule