data/full_repos/permissive/132304455/src/display_control.v
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1: b"%Error: data/full_repos/permissive/132304455/src/display_control.v:14: Cannot find file containing module: 'clock_divider'\n    clock_divider #(.rate(5000)) divider500(clk500, clk);\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132304455/src,data/full_repos/permissive/132304455/clock_divider\n             data/full_repos/permissive/132304455/src,data/full_repos/permissive/132304455/clock_divider.v\n             data/full_repos/permissive/132304455/src,data/full_repos/permissive/132304455/clock_divider.sv\n             clock_divider\n             clock_divider.v\n             clock_divider.sv\n             obj_dir/clock_divider\n             obj_dir/clock_divider.v\n             obj_dir/clock_divider.sv\n%Error: data/full_repos/permissive/132304455/src/display_control.v:17: Cannot find file containing module: 'clock_divider'\n    clock_divider #(.rate(10000)) divider250(clk250, clk);\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/132304455/src/display_control.v:22: Cannot find file containing module: 'DecimalDigitDecoder'\n    DecimalDigitDecoder ddd_input( , , , input_tens, input_ones, {10'b0, number});\n    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/132304455/src/display_control.v:26: Cannot find file containing module: 'DecimalDigitDecoder'\n    DecimalDigitDecoder ddd_score( , , , score_tens, score_ones, {10'b0, score});\n    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/132304455/src/display_control.v:29: Cannot find file containing module: 'mux4v'\n    mux4v #(.width(4)) seg_mux_input(digit_to_draw, input_ones, input_tens, score_ones, score_tens, {clk500, clk250});\n    ^~~~~\n%Error: data/full_repos/permissive/132304455/src/display_control.v:35: Cannot find file containing module: 'BCDToLED'\n    BCDToLED onesBCD(seg, digit_to_draw);\n    ^~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module display_control(seg,
                       an,
                       number,
                       score,
                       clk);

    output [6:0] seg;
    output [3:0] an;
    input  [5:0] number;
    input  [5:0] score;
    input        clk;

    wire clk500;
    clock_divider #(.rate(5000)) divider500(clk500, clk);

    wire clk250;
    clock_divider #(.rate(10000)) divider250(clk250, clk);


    wire [3:0] input_tens;
    wire [3:0] input_ones;
    DecimalDigitDecoder ddd_input( , , , input_tens, input_ones, {10'b0, number});
    
    wire [3:0] score_tens;
    wire [3:0] score_ones;
    DecimalDigitDecoder ddd_score( , , , score_tens, score_ones, {10'b0, score});
    
    wire [3:0] digit_to_draw;
    mux4v #(.width(4)) seg_mux_input(digit_to_draw, input_ones, input_tens, score_ones, score_tens, {clk500, clk250});




    
    BCDToLED onesBCD(seg, digit_to_draw);
    

    assign an[0] = ~(~clk500 & ~clk250);
    assign an[1] = ~(~clk500 & clk250);
    assign an[2] = ~(clk500 & ~clk250);
    assign an[3] = ~(clk500 & clk250);

endmodule
module display_control(seg,
                       an,
                       number,
                       score,
                       clk);


    output [6:0] seg;
    output [3:0] an;
    input  [5:0] number;
    input  [5:0] score;
    input        clk;

    wire clk500;
    clock_divider #(.rate(5000)) divider500(clk500, clk);

    wire clk250;
    clock_divider #(.rate(10000)) divider250(clk250, clk);


    wire [3:0] input_tens;
    wire [3:0] input_ones;
    DecimalDigitDecoder ddd_input( , , , input_tens, input_ones, {10'b0, number});
    
    wire [3:0] score_tens;
    wire [3:0] score_ones;
    DecimalDigitDecoder ddd_score( , , , score_tens, score_ones, {10'b0, score});
    
    wire [3:0] digit_to_draw;
    mux4v #(.width(4)) seg_mux_input(digit_to_draw, input_ones, input_tens, score_ones, score_tens, {clk500, clk250});




    
    BCDToLED onesBCD(seg, digit_to_draw);
    

    assign an[0] = ~(~clk500 & ~clk250);
    assign an[1] = ~(~clk500 & clk250);
    assign an[2] = ~(clk500 & ~clk250);
    assign an[3] = ~(clk500 & clk250);

endmodule