data/full_repos/permissive/160017776/windup_clock.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160017776/windup_clock.v:54: Operator GT expects 16 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                      : ... In instance windup_clock\n if (wr_en == 1\'b0 && counter > 1\'b0) begin\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module windup_clock




#(

	parameter BIT = 16
)




(
	input wire			clk_in,
	input wire			rst,
	input wire			wr_en,
	input wire	[BIT-1 : 0]	wind,
	output wire			clk_out
);





reg [BIT-1 : 0] counter;


assign clk_out = clk_in & |counter & ~wr_en;


always @ (posedge rst) begin : reset
	counter <= 0;
end


always @ (posedge wr_en) begin : winding
	counter <= wind;
end


always @ (posedge clk_in) begin : countdown
	if (wr_en == 1'b0 && counter > 1'b0) begin
		counter = counter - 1'b1;
	end
end


endmodule
module windup_clock




#(

	parameter BIT = 16
)




(
	input wire			clk_in,
	input wire			rst,
	input wire			wr_en,
	input wire	[BIT-1 : 0]	wind,
	output wire			clk_out
);






reg [BIT-1 : 0] counter;


assign clk_out = clk_in & |counter & ~wr_en;


always @ (posedge rst) begin : reset
	counter <= 0;
end


always @ (posedge wr_en) begin : winding
	counter <= wind;
end


always @ (posedge clk_in) begin : countdown
	if (wr_en == 1'b0 && counter > 1'b0) begin
		counter = counter - 1'b1;
	end
end


endmodule