data/full_repos/permissive/143278/ivltests/pr812.v
 line:47: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr812.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("tp = %f, tp2 = %f", tp, tp2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bot(a, b);
	input b;
	output a;

	real tp;
	real tp2;

	assign a = b;
	initial begin
		tp = 1 / `div;
		tp2 = 1 / `div;
		$display("tp = %f, tp2 = %f", tp, tp2);
		if (tp != 10.0)
			$display("tp != 10.0.  (tp = %f)", tp);
		else
			$display("tp == 10, (expected)");
		#1 $display("tp = %f, tp2 = %f", tp, tp2);
	end
endmodule
module bot(a, b);

	input b;
	output a;

	real tp;
	real tp2;

	assign a = b;
	initial begin
		tp = 1 / `div;
		tp2 = 1 / `div;
		$display("tp = %f, tp2 = %f", tp, tp2);
		if (tp != 10.0)
			$display("tp != 10.0.  (tp = %f)", tp);
		else
			$display("tp == 10, (expected)");
		#1 $display("tp = %f, tp2 = %f", tp, tp2);
	end
endmodule