data/full_repos/permissive/100796583/module/MBSsoc_apic.v
1: b'%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:2: Cannot find include file: ../cpu/MBScore_const.v\n`include "../cpu/MBScore_const.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v\n             data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.v\n             data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.sv\n             ../cpu/MBScore_const.v\n             ../cpu/MBScore_const.v.v\n             ../cpu/MBScore_const.v.sv\n             obj_dir/../cpu/MBScore_const.v\n             obj_dir/../cpu/MBScore_const.v.v\n             obj_dir/../cpu/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:6: Define or directive not defined: \'`INT_SEL_WIDTH\'\n    input  [`INT_SEL_WIDTH-1:0]     int_vec,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:7: Define or directive not defined: \'`CORE_NUM\'\n    input  [`CORE_NUM-1:0]          int_able,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:8: Define or directive not defined: \'`SYSCODE_WIDTH\'\n    input  [`SYSCODE_WIDTH-1:0]     syscall_code1,syscall_code0,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:10: Define or directive not defined: \'`DATA_WIDTH\'\n    input  [`DATA_WIDTH-1:0]        data_in,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:11: Define or directive not defined: \'`INT_SEL_WIDTH\'\n    output reg [`INT_SEL_WIDTH-1:0] int_num_out0,int_num_out1,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:12: Define or directive not defined: \'`INT_SEL_WIDTH\'\n    output reg [`INT_SEL_WIDTH-1:0] int_ack,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:13: Define or directive not defined: \'`ADDR_WIDTH\'\n    output [`ADDR_WIDTH-1:0]        cpu0_pc,cpu1_pc,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:17: Define or directive not defined: \'`INT_SEL_WIDTH\'\n    reg [`INT_SEL_WIDTH-1:0]        int_vec_r;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:19: Define or directive not defined: \'`DATA_WIDTH\'\n    reg [`DATA_WIDTH-1:0]           conf_r;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:20: Define or directive not defined: \'`ADDR_WIDTH\'\n    reg [`ADDR_WIDTH-1:0]           cpu0_pc_r = 32\'d0;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:21: Define or directive not defined: \'`ADDR_WIDTH\'\n    reg [`ADDR_WIDTH-1:0]           cpu1_pc_r = 32\'d0;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:26: Define or directive not defined: \'`SYSCODE_WIDTH\'\n    reg [`SYSCODE_WIDTH-1:0]        syscall_code1_r,syscall_code0_r;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:41: Define or directive not defined: \'`INT_SYSCALL0\'\n        if(int_vec_r[`INT_SYSCALL0] == 1\'b1)\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        if(int_vec_r[`INT_SYSCALL0] == 1\'b1)\n                                  ^\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:47: Define or directive not defined: \'`INT_SYSCALL1\'\n        if(int_vec_r[`INT_SYSCALL1] == 1\'b1)\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        if(int_vec_r[`INT_SYSCALL1] == 1\'b1)\n                                  ^\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:61: Define or directive not defined: \'`CHANGE_CPU1_PC\'\n            `CHANGE_CPU1_PC: \n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:72: Define or directive not defined: \'`INT_KEYBOARD\'\n            if(int_vec_r[`INT_KEYBOARD])\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:74: Define or directive not defined: \'`INT_KEYBOARD\'\n                int_num_out1            <= `INT_KEYBOARD;\n                                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:75: Define or directive not defined: \'`INT_KEYBOARD\'\n                int_ack[`INT_KEYBOARD]  <= 1\'b1;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:78: Define or directive not defined: \'`INT_MOUSE\'\n            if(int_vec_r[`INT_MOUSE])\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:80: Define or directive not defined: \'`INT_MOUSE\'\n                int_num_out1          <= `INT_MOUSE;\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:81: Define or directive not defined: \'`INT_MOUSE\'\n                int_ack[`INT_MOUSE]     <= 1\'b1;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:84: Define or directive not defined: \'`INT_UART\'\n            if(int_vec_r[`INT_UART])\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:86: Define or directive not defined: \'`INT_UART\'\n                int_num_out1          <= `INT_UART;\n                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:87: Define or directive not defined: \'`INT_UART\'\n                int_ack[`INT_UART]      <= 1\'b1;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:90: Define or directive not defined: \'`INT_STORAGE\'\n            if(int_vec_r[`INT_STORAGE])\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:92: Define or directive not defined: \'`INT_STORAGE\'\n                int_num_out1          <= `INT_STORAGE;\n                                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:93: Define or directive not defined: \'`INT_STORAGE\'\n                int_ack[`INT_STORAGE]   <= 1\'b1;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:96: Define or directive not defined: \'`INT_ETHERNET\'\n            if(int_vec_r[`INT_ETHERNET])\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:98: Define or directive not defined: \'`INT_ETHERNET\'\n                int_num_out1          <= `INT_ETHERNET;\n                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:99: Define or directive not defined: \'`INT_ETHERNET\'\n                int_ack[`INT_ETHERNET]  <= 1\'b1;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:105: Define or directive not defined: \'`INT_KEYBOARD\'\n            if(int_vec_r[`INT_KEYBOARD])\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:107: Define or directive not defined: \'`INT_KEYBOARD\'\n                int_num_out0          <= `INT_KEYBOARD;\n                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:108: Define or directive not defined: \'`INT_KEYBOARD\'\n                int_ack[`INT_KEYBOARD]  <= 1\'b1;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:111: Define or directive not defined: \'`INT_MOUSE\'\n            if(int_vec_r[`INT_MOUSE])\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:113: Define or directive not defined: \'`INT_MOUSE\'\n                int_num_out0          <= `INT_MOUSE;\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:114: Define or directive not defined: \'`INT_MOUSE\'\n                int_ack[`INT_MOUSE]     <= 1\'b1;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:117: Define or directive not defined: \'`INT_UART\'\n            if(int_vec_r[`INT_UART])\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:119: Define or directive not defined: \'`INT_UART\'\n                int_num_out0          <= `INT_UART;\n                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:120: Define or directive not defined: \'`INT_UART\'\n                int_ack[`INT_UART]      <= 1\'b1;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:123: Define or directive not defined: \'`INT_STORAGE\'\n            if(int_vec_r[`INT_STORAGE])\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:125: Define or directive not defined: \'`INT_STORAGE\'\n                int_num_out0          <= `INT_STORAGE;\n                                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:126: Define or directive not defined: \'`INT_STORAGE\'\n                int_ack[`INT_STORAGE]   <= 1\'b1;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:129: Define or directive not defined: \'`INT_ETHERNET\'\n            if(int_vec_r[`INT_ETHERNET])\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:131: Define or directive not defined: \'`INT_ETHERNET\'\n                int_num_out0          <= `INT_ETHERNET;\n                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:132: Define or directive not defined: \'`INT_ETHERNET\'\n                int_ack[`INT_ETHERNET]  <= 1\'b1;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:138: Define or directive not defined: \'`INT_SEL_WIDTH\'\n        int_num_out0    <= `INT_SEL_WIDTH\'d0;\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:139: Define or directive not defined: \'`INT_SEL_WIDTH\'\n        int_num_out1    <= `INT_SEL_WIDTH\'d0;\n                           ^~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module MBSsoc_apic(
    input                           clk,
    input                           rst_n,
    input  [`INT_SEL_WIDTH-1:0]     int_vec,
    input  [`CORE_NUM-1:0]          int_able,
    input  [`SYSCODE_WIDTH-1:0]     syscall_code1,syscall_code0,
    input  [2:0]                    ctrl_in,
    input  [`DATA_WIDTH-1:0]        data_in,
    output reg [`INT_SEL_WIDTH-1:0] int_num_out0,int_num_out1,
    output reg [`INT_SEL_WIDTH-1:0] int_ack,
    output [`ADDR_WIDTH-1:0]        cpu0_pc,cpu1_pc,
    output reg                      cpu1_en
);

    reg [`INT_SEL_WIDTH-1:0]        int_vec_r;

    reg [`DATA_WIDTH-1:0]           conf_r;
    reg [`ADDR_WIDTH-1:0]           cpu0_pc_r = 32'd0;
    reg [`ADDR_WIDTH-1:0]           cpu1_pc_r = 32'd0;
    assign cpu0_pc = cpu0_pc_r;
    assign cpu1_pc = cpu1_pc_r;

    reg                             syscall0,syscall1;
    reg [`SYSCODE_WIDTH-1:0]        syscall_code1_r,syscall_code0_r;

    always @(posedge clk)
    case (ctrl_in)
        3'b001: conf_r    <= data_in; 
        3'b010: cpu0_pc_r <= data_in;
        3'b100: cpu1_pc_r <= data_in;
        default: {conf_r,cpu0_pc_r,cpu1_pc_r} <= {conf_r,cpu0_pc_r,cpu1_pc_r};
    endcase



    always @(int_vec)
    begin
        int_vec_r <= int_vec;  
        if(int_vec_r[`INT_SYSCALL0] == 1'b1)
        begin
            syscall0 <= 1'b1;
            syscall_code0_r <= syscall0;
        end 

        if(int_vec_r[`INT_SYSCALL1] == 1'b1)
        begin 
            syscall1 <= 1'b1;  
            syscall_code1_r <= syscall1;
        end
    end
        

    always @(negedge clk)
    if(int_vec_r || syscall0 || syscall1)
    begin
        if(syscall0)
        begin
            case (syscall_code0)
            `CHANGE_CPU1_PC: 
            begin
                cpu1_en <= 1'b1;
            end
            endcase
            syscall0 <= 1'b0; 
        end


        if(int_able[1] && !conf_r[1])
        begin
            if(int_vec_r[`INT_KEYBOARD])
            begin
                int_num_out1            <= `INT_KEYBOARD;
                int_ack[`INT_KEYBOARD]  <= 1'b1;
            end
            else
            if(int_vec_r[`INT_MOUSE])
            begin
                int_num_out1          <= `INT_MOUSE;
                int_ack[`INT_MOUSE]     <= 1'b1;
            end
            else
            if(int_vec_r[`INT_UART])
            begin
                int_num_out1          <= `INT_UART;
                int_ack[`INT_UART]      <= 1'b1;
            end
            else
            if(int_vec_r[`INT_STORAGE])
            begin
                int_num_out1          <= `INT_STORAGE;
                int_ack[`INT_STORAGE]   <= 1'b1;
            end
            else
            if(int_vec_r[`INT_ETHERNET])
            begin
                int_num_out1          <= `INT_ETHERNET;
                int_ack[`INT_ETHERNET]  <= 1'b1;
            end
        end
        else
        if(int_able[0] && !conf_r[0])
        begin
            if(int_vec_r[`INT_KEYBOARD])
            begin
                int_num_out0          <= `INT_KEYBOARD;
                int_ack[`INT_KEYBOARD]  <= 1'b1;
            end
            else
            if(int_vec_r[`INT_MOUSE])
            begin
                int_num_out0          <= `INT_MOUSE;
                int_ack[`INT_MOUSE]     <= 1'b1;
            end
            else
            if(int_vec_r[`INT_UART])
            begin
                int_num_out0          <= `INT_UART;
                int_ack[`INT_UART]      <= 1'b1;
            end
            else
            if(int_vec_r[`INT_STORAGE])
            begin
                int_num_out0          <= `INT_STORAGE;
                int_ack[`INT_STORAGE]   <= 1'b1;
            end
            else
            if(int_vec_r[`INT_ETHERNET])
            begin
                int_num_out0          <= `INT_ETHERNET;
                int_ack[`INT_ETHERNET]  <= 1'b1;
            end
        end        
    end
    else
    begin
        int_num_out0    <= `INT_SEL_WIDTH'd0;
        int_num_out1    <= `INT_SEL_WIDTH'd0;
        int_ack         <= `INT_SEL_WIDTH'd0;
        cpu1_en         <= 1'b0;
    end

endmodule
module MBSsoc_apic(
    input                           clk,
    input                           rst_n,
    input  [`INT_SEL_WIDTH-1:0]     int_vec,
    input  [`CORE_NUM-1:0]          int_able,
    input  [`SYSCODE_WIDTH-1:0]     syscall_code1,syscall_code0,
    input  [2:0]                    ctrl_in,
    input  [`DATA_WIDTH-1:0]        data_in,
    output reg [`INT_SEL_WIDTH-1:0] int_num_out0,int_num_out1,
    output reg [`INT_SEL_WIDTH-1:0] int_ack,
    output [`ADDR_WIDTH-1:0]        cpu0_pc,cpu1_pc,
    output reg                      cpu1_en
);


    reg [`INT_SEL_WIDTH-1:0]        int_vec_r;

    reg [`DATA_WIDTH-1:0]           conf_r;
    reg [`ADDR_WIDTH-1:0]           cpu0_pc_r = 32'd0;
    reg [`ADDR_WIDTH-1:0]           cpu1_pc_r = 32'd0;
    assign cpu0_pc = cpu0_pc_r;
    assign cpu1_pc = cpu1_pc_r;

    reg                             syscall0,syscall1;
    reg [`SYSCODE_WIDTH-1:0]        syscall_code1_r,syscall_code0_r;

    always @(posedge clk)
    case (ctrl_in)
        3'b001: conf_r    <= data_in; 
        3'b010: cpu0_pc_r <= data_in;
        3'b100: cpu1_pc_r <= data_in;
        default: {conf_r,cpu0_pc_r,cpu1_pc_r} <= {conf_r,cpu0_pc_r,cpu1_pc_r};
    endcase



    always @(int_vec)
    begin
        int_vec_r <= int_vec;  
        if(int_vec_r[`INT_SYSCALL0] == 1'b1)
        begin
            syscall0 <= 1'b1;
            syscall_code0_r <= syscall0;
        end 

        if(int_vec_r[`INT_SYSCALL1] == 1'b1)
        begin 
            syscall1 <= 1'b1;  
            syscall_code1_r <= syscall1;
        end
    end
        

    always @(negedge clk)
    if(int_vec_r || syscall0 || syscall1)
    begin
        if(syscall0)
        begin
            case (syscall_code0)
            `CHANGE_CPU1_PC: 
            begin
                cpu1_en <= 1'b1;
            end
            endcase
            syscall0 <= 1'b0; 
        end


        if(int_able[1] && !conf_r[1])
        begin
            if(int_vec_r[`INT_KEYBOARD])
            begin
                int_num_out1            <= `INT_KEYBOARD;
                int_ack[`INT_KEYBOARD]  <= 1'b1;
            end
            else
            if(int_vec_r[`INT_MOUSE])
            begin
                int_num_out1          <= `INT_MOUSE;
                int_ack[`INT_MOUSE]     <= 1'b1;
            end
            else
            if(int_vec_r[`INT_UART])
            begin
                int_num_out1          <= `INT_UART;
                int_ack[`INT_UART]      <= 1'b1;
            end
            else
            if(int_vec_r[`INT_STORAGE])
            begin
                int_num_out1          <= `INT_STORAGE;
                int_ack[`INT_STORAGE]   <= 1'b1;
            end
            else
            if(int_vec_r[`INT_ETHERNET])
            begin
                int_num_out1          <= `INT_ETHERNET;
                int_ack[`INT_ETHERNET]  <= 1'b1;
            end
        end
        else
        if(int_able[0] && !conf_r[0])
        begin
            if(int_vec_r[`INT_KEYBOARD])
            begin
                int_num_out0          <= `INT_KEYBOARD;
                int_ack[`INT_KEYBOARD]  <= 1'b1;
            end
            else
            if(int_vec_r[`INT_MOUSE])
            begin
                int_num_out0          <= `INT_MOUSE;
                int_ack[`INT_MOUSE]     <= 1'b1;
            end
            else
            if(int_vec_r[`INT_UART])
            begin
                int_num_out0          <= `INT_UART;
                int_ack[`INT_UART]      <= 1'b1;
            end
            else
            if(int_vec_r[`INT_STORAGE])
            begin
                int_num_out0          <= `INT_STORAGE;
                int_ack[`INT_STORAGE]   <= 1'b1;
            end
            else
            if(int_vec_r[`INT_ETHERNET])
            begin
                int_num_out0          <= `INT_ETHERNET;
                int_ack[`INT_ETHERNET]  <= 1'b1;
            end
        end        
    end
    else
    begin
        int_num_out0    <= `INT_SEL_WIDTH'd0;
        int_num_out1    <= `INT_SEL_WIDTH'd0;
        int_ack         <= `INT_SEL_WIDTH'd0;
        cpu1_en         <= 1'b0;
    end

endmodule