data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C/salsa_piped.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C/salsa_piped.v:169: Cannot find include file: sgen.inc\n`include "sgen.inc"   // .inc so it does not accidentally get compiled separately as .v \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C,data/full_repos/permissive/11584509/sgen.inc\n             data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C,data/full_repos/permissive/11584509/sgen.inc.v\n             data/full_repos/permissive/11584509/experimental/LX150-EIGHT-C,data/full_repos/permissive/11584509/sgen.inc.sv\n             sgen.inc\n             sgen.inc.v\n             sgen.inc.sv\n             obj_dir/sgen.inc\n             obj_dir/sgen.inc.v\n             obj_dir/sgen.inc.sv\n%Error: Exiting due to 1 error(s)\n'
module salsa_core (clk, x, out, addr);

input clk;
input [511:0]x;
output [511:0]out;
output [9:0]addr;






wire [31:0] x00;
wire [31:0] x01;
wire [31:0] x02;
wire [31:0] x03;
wire [31:0] x04;
wire [31:0] x05;
wire [31:0] x06;
wire [31:0] x07;
wire [31:0] x08;
wire [31:0] x09;
wire [31:0] x10;
wire [31:0] x11;
wire [31:0] x12;
wire [31:0] x13;
wire [31:0] x14;
wire [31:0] x15;

assign x00 = x[`IDX(0)];
assign x01 = x[`IDX(1)];
assign x02 = x[`IDX(2)];
assign x03 = x[`IDX(3)];
assign x04 = x[`IDX(4)];
assign x05 = x[`IDX(5)];
assign x06 = x[`IDX(6)];
assign x07 = x[`IDX(7)];
assign x08 = x[`IDX(8)];
assign x09 = x[`IDX(9)];
assign x10 = x[`IDX(10)];
assign x11 = x[`IDX(11)];
assign x12 = x[`IDX(12)];
assign x13 = x[`IDX(13)];
assign x14 = x[`IDX(14)];
assign x15 = x[`IDX(15)];






`include "sgen.inc"


wire [31:0]c00s;
wire [31:0]c01s;
wire [31:0]c02s;
wire [31:0]c03s;
wire [31:0]c04s;
wire [31:0]c05s;
wire [31:0]c06s;
wire [31:0]c07s;
wire [31:0]c08s;
wire [31:0]c09s;
wire [31:0]c10s;
wire [31:0]c11s;
wire [31:0]c12s;
wire [31:0]c13s;
wire [31:0]c14s;
wire [31:0]c15s;

wire [31:0]r00s;
wire [31:0]r01s;
wire [31:0]r02s;
wire [31:0]r03s;
wire [31:0]r04s;
wire [31:0]r05s;
wire [31:0]r06s;
wire [31:0]r07s;
wire [31:0]r08s;
wire [31:0]r09s;
wire [31:0]r10s;
wire [31:0]r11s;
wire [31:0]r12s;
wire [31:0]r13s;
wire [31:0]r14s;
wire [31:0]r15s;

wire [31:0]r00sx;





assign c04s = x00 + x12;
assign c09s = x05 + x01;
assign c14s = x10 + x06;
assign c03s = x15 + x11;

assign c08s = c04 + x00d1;
assign c13s = c09 + x05d1;
assign c02s = c14 + x10d1;
assign c07s = c03 + x15d1;

assign c12s = c08 + c04d1;
assign c01s = c13 + c09d1;
assign c06s = c02 + c14d1;
assign c11s = c07 + c03d1;

assign c00s = c12 + c08d1;
assign c05s = c01 + c13d1;
assign c10s = c06 + c02d1;
assign c15s = c11 + c07d1;



assign r01s = c00 + c03d3;
assign r06s = c05 + c04d3;
assign r11s = c10 + c09d3;
assign r12s = c15 + c14d3;

assign r02s = r01 + c00d1;
assign r07s = r06 + c05d1;
assign r08s = r11 + c10d1;
assign r13s = r12 + c15d1;

assign r03s = r02 + r01d1;
assign r04s = r07 + r06d1;
assign r09s = r08 + r11d1;
assign r14s = r13 + r12d1;

assign r00s = r03 + r02d1;
assign r05s = r04 + r07d1;
assign r10s = r09 + r08d1;
assign r15s = r14 + r13d1;


assign r00sx = c00d3 ^ { r00s[13:0], r00s[31:14] };
assign addr = r00sx[9:0];

assign out = { r15, r14d1, r13d2, r12d3, r11d3, r10, r09d1, r08d2, r07d2, r06d3, r05, r04d1, r03d1, r02d2, r01d3, r00 };

always @ (posedge clk)
begin
	c04 <= x04 ^ { c04s[24:0], c04s[31:25] };
	c09 <= x09 ^ { c09s[24:0], c09s[31:25] };
	c14 <= x14 ^ { c14s[24:0], c14s[31:25] };
	c03 <= x03 ^ { c03s[24:0], c03s[31:25] };

	c08 <= x08d1 ^ { c08s[22:0], c08s[31:23] };
	c13 <= x13d1 ^ { c13s[22:0], c13s[31:23] };
	c02 <= x02d1 ^ { c02s[22:0], c02s[31:23] };
	c07 <= x07d1 ^ { c07s[22:0], c07s[31:23] };

	c12 <= x12d2 ^ { c12s[18:0], c12s[31:19] };
	c01 <= x01d2 ^ { c01s[18:0], c01s[31:19] };
	c06 <= x06d2 ^ { c06s[18:0], c06s[31:19] };
	c11 <= x11d2 ^ { c11s[18:0], c11s[31:19] };

	c00 <= x00d3 ^ { c00s[13:0], c00s[31:14] };
	c05 <= x05d3 ^ { c05s[13:0], c05s[31:14] };
	c10 <= x10d3 ^ { c10s[13:0], c10s[31:14] };
	c15 <= x15d3 ^ { c15s[13:0], c15s[31:14] };

	r01 <= c01d1 ^ { r01s[24:0], r01s[31:25] };
	r06 <= c06d1 ^ { r06s[24:0], r06s[31:25] };
	r11 <= c11d1 ^ { r11s[24:0], r11s[31:25] };
	r12 <= c12d1 ^ { r12s[24:0], r12s[31:25] };

	r02 <= c02d3 ^ { r02s[22:0], r02s[31:23] };
	r07 <= c07d3 ^ { r07s[22:0], r07s[31:23] };
	r08 <= c08d3 ^ { r08s[22:0], r08s[31:23] };
	r13 <= c13d3 ^ { r13s[22:0], r13s[31:23] };

	r03 <= c03d5 ^ { r03s[18:0], r03s[31:19] };
	r04 <= c04d5 ^ { r04s[18:0], r04s[31:19] };
	r09 <= c09d5 ^ { r09s[18:0], r09s[31:19] };
	r14 <= c14d5 ^ { r14s[18:0], r14s[31:19] };


	r00 <= r00sx;
	r05 <= c05d3 ^ { r05s[13:0], r05s[31:14] };
	r10 <= c10d3 ^ { r10s[13:0], r10s[31:14] };
	r15 <= c15d3 ^ { r15s[13:0], r15s[31:14] };
end
endmodule
module salsa_core (clk, x, out, addr);


input clk;
input [511:0]x;
output [511:0]out;
output [9:0]addr;






wire [31:0] x00;
wire [31:0] x01;
wire [31:0] x02;
wire [31:0] x03;
wire [31:0] x04;
wire [31:0] x05;
wire [31:0] x06;
wire [31:0] x07;
wire [31:0] x08;
wire [31:0] x09;
wire [31:0] x10;
wire [31:0] x11;
wire [31:0] x12;
wire [31:0] x13;
wire [31:0] x14;
wire [31:0] x15;

assign x00 = x[`IDX(0)];
assign x01 = x[`IDX(1)];
assign x02 = x[`IDX(2)];
assign x03 = x[`IDX(3)];
assign x04 = x[`IDX(4)];
assign x05 = x[`IDX(5)];
assign x06 = x[`IDX(6)];
assign x07 = x[`IDX(7)];
assign x08 = x[`IDX(8)];
assign x09 = x[`IDX(9)];
assign x10 = x[`IDX(10)];
assign x11 = x[`IDX(11)];
assign x12 = x[`IDX(12)];
assign x13 = x[`IDX(13)];
assign x14 = x[`IDX(14)];
assign x15 = x[`IDX(15)];






`include "sgen.inc"


wire [31:0]c00s;
wire [31:0]c01s;
wire [31:0]c02s;
wire [31:0]c03s;
wire [31:0]c04s;
wire [31:0]c05s;
wire [31:0]c06s;
wire [31:0]c07s;
wire [31:0]c08s;
wire [31:0]c09s;
wire [31:0]c10s;
wire [31:0]c11s;
wire [31:0]c12s;
wire [31:0]c13s;
wire [31:0]c14s;
wire [31:0]c15s;

wire [31:0]r00s;
wire [31:0]r01s;
wire [31:0]r02s;
wire [31:0]r03s;
wire [31:0]r04s;
wire [31:0]r05s;
wire [31:0]r06s;
wire [31:0]r07s;
wire [31:0]r08s;
wire [31:0]r09s;
wire [31:0]r10s;
wire [31:0]r11s;
wire [31:0]r12s;
wire [31:0]r13s;
wire [31:0]r14s;
wire [31:0]r15s;

wire [31:0]r00sx;





assign c04s = x00 + x12;
assign c09s = x05 + x01;
assign c14s = x10 + x06;
assign c03s = x15 + x11;

assign c08s = c04 + x00d1;
assign c13s = c09 + x05d1;
assign c02s = c14 + x10d1;
assign c07s = c03 + x15d1;

assign c12s = c08 + c04d1;
assign c01s = c13 + c09d1;
assign c06s = c02 + c14d1;
assign c11s = c07 + c03d1;

assign c00s = c12 + c08d1;
assign c05s = c01 + c13d1;
assign c10s = c06 + c02d1;
assign c15s = c11 + c07d1;



assign r01s = c00 + c03d3;
assign r06s = c05 + c04d3;
assign r11s = c10 + c09d3;
assign r12s = c15 + c14d3;

assign r02s = r01 + c00d1;
assign r07s = r06 + c05d1;
assign r08s = r11 + c10d1;
assign r13s = r12 + c15d1;

assign r03s = r02 + r01d1;
assign r04s = r07 + r06d1;
assign r09s = r08 + r11d1;
assign r14s = r13 + r12d1;

assign r00s = r03 + r02d1;
assign r05s = r04 + r07d1;
assign r10s = r09 + r08d1;
assign r15s = r14 + r13d1;


assign r00sx = c00d3 ^ { r00s[13:0], r00s[31:14] };
assign addr = r00sx[9:0];

assign out = { r15, r14d1, r13d2, r12d3, r11d3, r10, r09d1, r08d2, r07d2, r06d3, r05, r04d1, r03d1, r02d2, r01d3, r00 };

always @ (posedge clk)
begin
	c04 <= x04 ^ { c04s[24:0], c04s[31:25] };
	c09 <= x09 ^ { c09s[24:0], c09s[31:25] };
	c14 <= x14 ^ { c14s[24:0], c14s[31:25] };
	c03 <= x03 ^ { c03s[24:0], c03s[31:25] };

	c08 <= x08d1 ^ { c08s[22:0], c08s[31:23] };
	c13 <= x13d1 ^ { c13s[22:0], c13s[31:23] };
	c02 <= x02d1 ^ { c02s[22:0], c02s[31:23] };
	c07 <= x07d1 ^ { c07s[22:0], c07s[31:23] };

	c12 <= x12d2 ^ { c12s[18:0], c12s[31:19] };
	c01 <= x01d2 ^ { c01s[18:0], c01s[31:19] };
	c06 <= x06d2 ^ { c06s[18:0], c06s[31:19] };
	c11 <= x11d2 ^ { c11s[18:0], c11s[31:19] };

	c00 <= x00d3 ^ { c00s[13:0], c00s[31:14] };
	c05 <= x05d3 ^ { c05s[13:0], c05s[31:14] };
	c10 <= x10d3 ^ { c10s[13:0], c10s[31:14] };
	c15 <= x15d3 ^ { c15s[13:0], c15s[31:14] };

	r01 <= c01d1 ^ { r01s[24:0], r01s[31:25] };
	r06 <= c06d1 ^ { r06s[24:0], r06s[31:25] };
	r11 <= c11d1 ^ { r11s[24:0], r11s[31:25] };
	r12 <= c12d1 ^ { r12s[24:0], r12s[31:25] };

	r02 <= c02d3 ^ { r02s[22:0], r02s[31:23] };
	r07 <= c07d3 ^ { r07s[22:0], r07s[31:23] };
	r08 <= c08d3 ^ { r08s[22:0], r08s[31:23] };
	r13 <= c13d3 ^ { r13s[22:0], r13s[31:23] };

	r03 <= c03d5 ^ { r03s[18:0], r03s[31:19] };
	r04 <= c04d5 ^ { r04s[18:0], r04s[31:19] };
	r09 <= c09d5 ^ { r09s[18:0], r09s[31:19] };
	r14 <= c14d5 ^ { r14s[18:0], r14s[31:19] };


	r00 <= r00sx;
	r05 <= c05d3 ^ { r05s[13:0], r05s[31:14] };
	r10 <= c10d3 ^ { r10s[13:0], r10s[31:14] };
	r15 <= c15d3 ^ { r15s[13:0], r15s[31:14] };
end
endmodule