data/full_repos/permissive/136422019/src/regR0.v
data/verilator_xmls/1f732ec6-6bd0-4e6a-aa8e-ba4ad779e2a6.xml
module regR0 (
	output reg [31:0] q,
	input wire [31:0] d,
	input wire en, clk, clr, BAout
);

reg[31:0] data;


initial begin
	q <= 0;
	data <= 0;
end

always@(posedge clk, posedge clr, posedge BAout) begin
		if(clr == 1 || BAout == 1) begin
			q <= 0;
		end
		else if (en == 1) begin
			data <= d;
			q <= data;
		end
		else
			q <= data;
end
endmodule
module regR0 (
	output reg [31:0] q,
	input wire [31:0] d,
	input wire en, clk, clr, BAout
);


reg[31:0] data;


initial begin
	q <= 0;
	data <= 0;
end

always@(posedge clk, posedge clr, posedge BAout) begin
		if(clr == 1 || BAout == 1) begin
			q <= 0;
		end
		else if (en == 1) begin
			data <= d;
			q <= data;
		end
		else
			q <= data;
end
endmodule