data/full_repos/permissive/169225814/modules/uarts/rtl/uarts_rx.v
1: b'%Error: data/full_repos/permissive/169225814/modules/uarts/rtl/uarts_rx.v:58: Cannot find include file: uarts_params.v\n  `include "uarts_params.v" \n           ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169225814/modules/uarts/rtl,data/full_repos/permissive/169225814/uarts_params.v\n             data/full_repos/permissive/169225814/modules/uarts/rtl,data/full_repos/permissive/169225814/uarts_params.v.v\n             data/full_repos/permissive/169225814/modules/uarts/rtl,data/full_repos/permissive/169225814/uarts_params.v.sv\n             uarts_params.v\n             uarts_params.v.v\n             uarts_params.v.sv\n             obj_dir/uarts_params.v\n             obj_dir/uarts_params.v.v\n             obj_dir/uarts_params.v.sv\n%Error: Exiting due to 1 error(s)\n'
module uarts_rx (

  input  wire        hclk,
  input  wire        hresetn,


  input  wire [31:0] uarts_baud,
  input  wire [31:0] uarts_ctl,


  input  wire        sample_data_bit,
  input  wire [7:0]  bit_cnt,
  input  wire [7:0]  uarts_dw,
  input  wire [7:0]  uarts_plw,


  input  wire        RX,

  output reg [31:0]  rx_data,
  output reg         rx_irq
);





reg [31:0]  rx_reg;
reg [2:0]   rx_curr_st;
reg [2:0]   rx_nxt_st;

  `include "uarts_params.v"


   always @ (posedge hclk or negedge hresetn) begin
     if (hresetn == 1'b0) begin
       rx_reg = 32'b0;
     end
     else begin
       if ((sample_data_bit == 1'b1) && (bit_cnt <= uarts_dw)) begin
         rx_reg = {RX, rx_reg[31:1]};
       end
     end
   end
 









 
 always @* begin
   rx_nxt_st = rx_curr_st;
   case (rx_curr_st)
     RX_IDLE : begin
       if (bit_cnt == uarts_plw[7:0])  begin
         if (uarts_ctl[1:0] == 2'b10) begin
           rx_nxt_st = RX_CHECK;
         end
         else begin
           rx_nxt_st = RX_WAIT1;
         end
       end
     end
     RX_CHECK : begin
       rx_nxt_st = RX_IDLE;
     end
     RX_WAIT1 : begin
       if (bit_cnt == uarts_plw[7:0])  begin
         if (uarts_ctl[1:0] == 2'b01) begin
           rx_nxt_st = RX_CHECK;
         end
         else begin
           rx_nxt_st = RX_WAIT2;
         end
       end
     end
     RX_WAIT2 : begin
       if (bit_cnt == uarts_plw[7:0])  begin
         rx_nxt_st = RX_WAIT3;
       end
     end
     RX_WAIT3 : begin
       if (bit_cnt == uarts_plw[7:0])  begin
           rx_nxt_st = RX_CHECK;
       end
     end
     default : begin
       rx_nxt_st = RX_IDLE;
     end
   endcase
 end

 always @ (posedge hclk or negedge hresetn) begin
   if (hresetn == 1'b0) begin
     rx_curr_st <= 3'b0;
   end
   else begin
     rx_curr_st <= rx_nxt_st;
   end
 end
  
 always @ (posedge hclk or negedge hresetn) begin
   if (hresetn == 1'b0) begin
     rx_irq <= 1'b0;
   end
   else begin
     if ((rx_curr_st != RX_CHECK) && (rx_nxt_st == RX_CHECK)) begin
       rx_irq <= 1'b1;
     end
     else begin
       rx_irq <= 1'b0;
     end
   end
 end
  
 always @ (posedge hclk or negedge hresetn) begin
   if (hresetn == 1'b0) begin
     rx_data <= 32'b0;
   end
   else begin
    if ((rx_curr_st != RX_CHECK) && (rx_nxt_st == RX_CHECK)) begin
      rx_data <= rx_reg[31:0];
    end
   end
 end
 


 
endmodule
module uarts_rx (

  input  wire        hclk,
  input  wire        hresetn,


  input  wire [31:0] uarts_baud,
  input  wire [31:0] uarts_ctl,


  input  wire        sample_data_bit,
  input  wire [7:0]  bit_cnt,
  input  wire [7:0]  uarts_dw,
  input  wire [7:0]  uarts_plw,


  input  wire        RX,

  output reg [31:0]  rx_data,
  output reg         rx_irq
);






reg [31:0]  rx_reg;
reg [2:0]   rx_curr_st;
reg [2:0]   rx_nxt_st;

  `include "uarts_params.v"


   always @ (posedge hclk or negedge hresetn) begin
     if (hresetn == 1'b0) begin
       rx_reg = 32'b0;
     end
     else begin
       if ((sample_data_bit == 1'b1) && (bit_cnt <= uarts_dw)) begin
         rx_reg = {RX, rx_reg[31:1]};
       end
     end
   end
 









 
 always @* begin
   rx_nxt_st = rx_curr_st;
   case (rx_curr_st)
     RX_IDLE : begin
       if (bit_cnt == uarts_plw[7:0])  begin
         if (uarts_ctl[1:0] == 2'b10) begin
           rx_nxt_st = RX_CHECK;
         end
         else begin
           rx_nxt_st = RX_WAIT1;
         end
       end
     end
     RX_CHECK : begin
       rx_nxt_st = RX_IDLE;
     end
     RX_WAIT1 : begin
       if (bit_cnt == uarts_plw[7:0])  begin
         if (uarts_ctl[1:0] == 2'b01) begin
           rx_nxt_st = RX_CHECK;
         end
         else begin
           rx_nxt_st = RX_WAIT2;
         end
       end
     end
     RX_WAIT2 : begin
       if (bit_cnt == uarts_plw[7:0])  begin
         rx_nxt_st = RX_WAIT3;
       end
     end
     RX_WAIT3 : begin
       if (bit_cnt == uarts_plw[7:0])  begin
           rx_nxt_st = RX_CHECK;
       end
     end
     default : begin
       rx_nxt_st = RX_IDLE;
     end
   endcase
 end

 always @ (posedge hclk or negedge hresetn) begin
   if (hresetn == 1'b0) begin
     rx_curr_st <= 3'b0;
   end
   else begin
     rx_curr_st <= rx_nxt_st;
   end
 end
  
 always @ (posedge hclk or negedge hresetn) begin
   if (hresetn == 1'b0) begin
     rx_irq <= 1'b0;
   end
   else begin
     if ((rx_curr_st != RX_CHECK) && (rx_nxt_st == RX_CHECK)) begin
       rx_irq <= 1'b1;
     end
     else begin
       rx_irq <= 1'b0;
     end
   end
 end
  
 always @ (posedge hclk or negedge hresetn) begin
   if (hresetn == 1'b0) begin
     rx_data <= 32'b0;
   end
   else begin
    if ((rx_curr_st != RX_CHECK) && (rx_nxt_st == RX_CHECK)) begin
      rx_data <= rx_reg[31:0];
    end
   end
 end
 


 
endmodule