data/full_repos/permissive/163840441/project/CU.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/f16adaed-8f10-4caf-8066-4a4839d35712.xml
module CU(
            Busy,
            clk, reset,
            CO, Z, 
            CUconst,
            InMuxAdd,
            InsSel,
            OutMuxAdd, RegAdd,
            Start,
            WE
        );
        input clk, reset, CO, Z, Start; 
        (* DONT_TOUCH = "TRUE" *) output reg [1:0] InsSel;
        (* DONT_TOUCH = "TRUE" *) output reg [2:0] InMuxAdd;
        (* DONT_TOUCH = "TRUE" *) output reg [3:0] OutMuxAdd, RegAdd;
        (* DONT_TOUCH = "TRUE" *) output reg [7:0] CUconst;
        (* DONT_TOUCH = "TRUE" *) output reg Busy;
        (* DONT_TOUCH = "TRUE" *) output reg WE;
        reg [3:0] state;
        wire [3:0] next_state;
        assign next_state = state + 1;

        always @(posedge clk or posedge reset) begin
            if ( reset ) begin
                state <= 0;
            end else begin
                case(state)
                    4'h0:      state <= Start ? next_state : state;
                    4'h8:      state <= Z ? 4'hA: next_state;
                    4'h9:      state <= CO ? next_state : 4'hE;
                    4'hE,4'hF: state <= 0;
                    default:   state <= next_state;
                endcase
            end
        end

        always @(posedge clk or posedge reset) begin
            if ( reset ) begin
                {Busy,WE} = 0;
                {InsSel,CUconst,InMuxAdd,OutMuxAdd,RegAdd} = 0;
            end else begin
                case(state)
                    4'h0: {Busy,WE} = 0;
                    4'h1: Busy = 1;
                    4'h2: begin
                        InMuxAdd    <= 3'h0;
                        RegAdd      <= 4'h3;
                        WE          <= 1;
                    end
                    4'h3: begin
                        InMuxAdd    <= 3'h1;
                        RegAdd      <= 4'h1;
                    end
                    4'h4: begin
                        InMuxAdd    <= 3'h2;
                        RegAdd      <= 4'h1;
                        CUconst     <= 8'hFF;
                        InsSel      <= 2'h1;
                    end
                    4'h5: begin
                        InMuxAdd    <= 3'h3;
                        RegAdd      <= 4'h1;
                    end
                    4'h6: begin
                        InMuxAdd    <= 3'h2;
                        RegAdd      <= 4'h2;
                        CUconst     <= 8'h01;           
                        InsSel      <= 2'h2;
                    end
                    4'h7: begin
                        InMuxAdd    <= 3'h3;
                        RegAdd      <= 4'h1;
                    end
                    4'h8: begin
                        InMuxAdd    <= 3'h4;
                        RegAdd      <= 4'h2;
                        OutMuxAdd   <= 4'h3;
                        InsSel      <= 2'h2;
                    end
                    4'h9: begin end
                    4'hA: begin
                        InMuxAdd    <= 3'h3;
                        RegAdd      <= 4'h1;
                    end
                    4'hB: begin
                        InMuxAdd    <= 3'h2;
                        RegAdd      <= 4'h2;
                        CUconst     <= 8'hFF; 
                        InsSel      <= 2'h1;
                    end
                    4'hC: begin
                        InMuxAdd    <= 3'h3;
                        RegAdd      <= 4'h1;
                    end
                    4'hD: begin
                        InMuxAdd    <= 3'h2;
                        RegAdd      <= 4'h2;
                        CUconst     <= 8'h01;
                        InsSel      <= 2'h2;
                    end
                    4'hE: begin
                        InMuxAdd    <= 3'h3;
                        RegAdd      <= 4'h0;
                    end
                    4'hF: begin end
                endcase
            end
        end
endmodule
module CU(
            Busy,
            clk, reset,
            CO, Z, 
            CUconst,
            InMuxAdd,
            InsSel,
            OutMuxAdd, RegAdd,
            Start,
            WE
        );

        input clk, reset, CO, Z, Start; 
        (* DONT_TOUCH = "TRUE" *) output reg [1:0] InsSel;
        (* DONT_TOUCH = "TRUE" *) output reg [2:0] InMuxAdd;
        (* DONT_TOUCH = "TRUE" *) output reg [3:0] OutMuxAdd, RegAdd;
        (* DONT_TOUCH = "TRUE" *) output reg [7:0] CUconst;
        (* DONT_TOUCH = "TRUE" *) output reg Busy;
        (* DONT_TOUCH = "TRUE" *) output reg WE;
        reg [3:0] state;
        wire [3:0] next_state;
        assign next_state = state + 1;

        always @(posedge clk or posedge reset) begin
            if ( reset ) begin
                state <= 0;
            end else begin
                case(state)
                    4'h0:      state <= Start ? next_state : state;
                    4'h8:      state <= Z ? 4'hA: next_state;
                    4'h9:      state <= CO ? next_state : 4'hE;
                    4'hE,4'hF: state <= 0;
                    default:   state <= next_state;
                endcase
            end
        end

        always @(posedge clk or posedge reset) begin
            if ( reset ) begin
                {Busy,WE} = 0;
                {InsSel,CUconst,InMuxAdd,OutMuxAdd,RegAdd} = 0;
            end else begin
                case(state)
                    4'h0: {Busy,WE} = 0;
                    4'h1: Busy = 1;
                    4'h2: begin
                        InMuxAdd    <= 3'h0;
                        RegAdd      <= 4'h3;
                        WE          <= 1;
                    end
                    4'h3: begin
                        InMuxAdd    <= 3'h1;
                        RegAdd      <= 4'h1;
                    end
                    4'h4: begin
                        InMuxAdd    <= 3'h2;
                        RegAdd      <= 4'h1;
                        CUconst     <= 8'hFF;
                        InsSel      <= 2'h1;
                    end
                    4'h5: begin
                        InMuxAdd    <= 3'h3;
                        RegAdd      <= 4'h1;
                    end
                    4'h6: begin
                        InMuxAdd    <= 3'h2;
                        RegAdd      <= 4'h2;
                        CUconst     <= 8'h01;           
                        InsSel      <= 2'h2;
                    end
                    4'h7: begin
                        InMuxAdd    <= 3'h3;
                        RegAdd      <= 4'h1;
                    end
                    4'h8: begin
                        InMuxAdd    <= 3'h4;
                        RegAdd      <= 4'h2;
                        OutMuxAdd   <= 4'h3;
                        InsSel      <= 2'h2;
                    end
                    4'h9: begin end
                    4'hA: begin
                        InMuxAdd    <= 3'h3;
                        RegAdd      <= 4'h1;
                    end
                    4'hB: begin
                        InMuxAdd    <= 3'h2;
                        RegAdd      <= 4'h2;
                        CUconst     <= 8'hFF; 
                        InsSel      <= 2'h1;
                    end
                    4'hC: begin
                        InMuxAdd    <= 3'h3;
                        RegAdd      <= 4'h1;
                    end
                    4'hD: begin
                        InMuxAdd    <= 3'h2;
                        RegAdd      <= 4'h2;
                        CUconst     <= 8'h01;
                        InsSel      <= 2'h2;
                    end
                    4'hE: begin
                        InMuxAdd    <= 3'h3;
                        RegAdd      <= 4'h0;
                    end
                    4'hF: begin end
                endcase
            end
        end
endmodule