data/full_repos/permissive/176606610/ip_repo/dsm_order6/src/xb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/176606610/ip_repo/dsm_order6/src/xb.v:43: Cannot find file containing module: 'delay_integrator'\n    delay_integrator d1(\n    ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/176606610/ip_repo/dsm_order6/src,data/full_repos/permissive/176606610/delay_integrator\n             data/full_repos/permissive/176606610/ip_repo/dsm_order6/src,data/full_repos/permissive/176606610/delay_integrator.v\n             data/full_repos/permissive/176606610/ip_repo/dsm_order6/src,data/full_repos/permissive/176606610/delay_integrator.sv\n             delay_integrator\n             delay_integrator.v\n             delay_integrator.sv\n             obj_dir/delay_integrator\n             obj_dir/delay_integrator.v\n             obj_dir/delay_integrator.sv\n%Error: data/full_repos/permissive/176606610/ip_repo/dsm_order6/src/xb.v:51: Cannot find file containing module: 'gain'\n    gain #(.GAIN(CGAINB),.CG(1)) cb(\n    ^~~~\n%Error: data/full_repos/permissive/176606610/ip_repo/dsm_order6/src/xb.v:56: Cannot find file containing module: 'gain'\n     gain #(.GAIN(CGAING),.CG(0)) gi(\n     ^~~~\n%Error: Exiting due to 3 error(s)\n"
module xb
    #(parameter CGAINB = 0,
    parameter CGAING = 0)(
    input clk,
    input rst_n,
    input fs_enb,
    input [35:0] inpb,
    input [35:0] outa,
    input [35:0] csump,
    output [35:0] gsum,
    output [35:0] csum
    );
    
    wire [35:0] xin;
    wire [35:0] sum;

    assign xin = csump + inpb + outa;


            
    delay_integrator d1(
        .clk(clk),
        .rst_n(rst_n),
        .xin(xin),
        .sum(sum),
        .fs_enb(fs_enb)
        );
        
    gain #(.GAIN(CGAINB),.CG(1)) cb(
            .inp(sum),
            .out(csum)
            );
     
     gain #(.GAIN(CGAING),.CG(0)) gi(
            .inp(sum),
            .out(gsum)
            );
                   
endmodule
module xb
    #(parameter CGAINB = 0,
    parameter CGAING = 0)(
    input clk,
    input rst_n,
    input fs_enb,
    input [35:0] inpb,
    input [35:0] outa,
    input [35:0] csump,
    output [35:0] gsum,
    output [35:0] csum
    );

    
    wire [35:0] xin;
    wire [35:0] sum;

    assign xin = csump + inpb + outa;


            
    delay_integrator d1(
        .clk(clk),
        .rst_n(rst_n),
        .xin(xin),
        .sum(sum),
        .fs_enb(fs_enb)
        );
        
    gain #(.GAIN(CGAINB),.CG(1)) cb(
            .inp(sum),
            .out(csum)
            );
     
     gain #(.GAIN(CGAING),.CG(0)) gi(
            .inp(sum),
            .out(gsum)
            );
                   
endmodule