data/full_repos/permissive/199632300/HDLBits/Verification/tb/and.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/199632300/HDLBits/Verification/tb/and.v:6: Unsupported: Ignoring delay on this delayed statement.\n        #0 x=0;y=0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/199632300/HDLBits/Verification/tb/and.v:7: Unsupported: Ignoring delay on this delayed statement.\n        #10 y=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/199632300/HDLBits/Verification/tb/and.v:8: Unsupported: Ignoring delay on this delayed statement.\n        #10 x=1;y=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/199632300/HDLBits/Verification/tb/and.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #10 y=1;\n        ^\n%Error: data/full_repos/permissive/199632300/HDLBits/Verification/tb/and.v:12: Cannot find file containing module: \'andgate\'\n    andgate a({x,y},out);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/199632300/HDLBits/Verification/tb,data/full_repos/permissive/199632300/andgate\n             data/full_repos/permissive/199632300/HDLBits/Verification/tb,data/full_repos/permissive/199632300/andgate.v\n             data/full_repos/permissive/199632300/HDLBits/Verification/tb,data/full_repos/permissive/199632300/andgate.sv\n             andgate\n             andgate.v\n             andgate.sv\n             obj_dir/andgate\n             obj_dir/andgate.v\n             obj_dir/andgate.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_module();
	reg x,y,out;
    
    initial begin
       	#0	x=0;y=0;
        #10	y=1;
        #10	x=1;y=0;
        #10	y=1;
    end
    
    andgate a({x,y},out);
    
endmodule
module top_module();

	reg x,y,out;
    
    initial begin
       	#0	x=0;y=0;
        #10	y=1;
        #10	x=1;y=0;
        #10	y=1;
    end
    
    andgate a({x,y},out);
    
endmodule