data/full_repos/permissive/137213315/aes_cipher.v
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1: b'%Error: data/full_repos/permissive/137213315/aes_cipher.v:4: Cannot find include file: AddRoundKey.v\n`include "AddRoundKey.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137213315,data/full_repos/permissive/137213315/AddRoundKey.v\n             data/full_repos/permissive/137213315,data/full_repos/permissive/137213315/AddRoundKey.v.v\n             data/full_repos/permissive/137213315,data/full_repos/permissive/137213315/AddRoundKey.v.sv\n             AddRoundKey.v\n             AddRoundKey.v.v\n             AddRoundKey.v.sv\n             obj_dir/AddRoundKey.v\n             obj_dir/AddRoundKey.v.v\n             obj_dir/AddRoundKey.v.sv\n%Error: data/full_repos/permissive/137213315/aes_cipher.v:5: Cannot find include file: SubBytes.v\n`include "SubBytes.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/137213315/aes_cipher.v:6: Cannot find include file: ShiftRows.v\n`include "ShiftRows.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137213315/aes_cipher.v:7: Cannot find include file: MixColumns.v\n`include "MixColumns.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137213315/aes_cipher.v:8: Cannot find include file: KeyExpansion.v\n`include "KeyExpansion.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137213315/aes_cipher.v:9: Cannot find include file: FlipBytes.v\n`include "FlipBytes.v" \n         ^~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module aes_cipher #(parameter NB = 128, NC = 4, NK = 4, NR = 10, BYTE = 8, WORD = 32) 
                 (input clk, rstn, start, output reg done,
                  input [NB-1:0] plain_text, key,
                  output [NB-1:0] cipher_text);


  reg [NB-1:0] state, roundkey;
  reg [3:0] round;

  reg [NB-1:0] addroundkeyIN;
  wire [NB-1:0] subbytes_, shiftrows_, mixcolumns_, addroundkey_, keyexpansion_;
  
  SubBytes sbox(.in(state),.out(subbytes_));
  ShiftRows shiftrows(.in(subbytes_),.out(shiftrows_));
  MixColumns mixcolumns(.in(shiftrows_),.out(mixcolumns_));
  AddRoundKey addroundkey(.in(addroundkeyIN),.key(roundkey),.out(addroundkey_));
  KeyExpansion keyexpansion(.RoundNumber(round),.RoundKey(roundkey),.NextRoundKey(keyexpansion_));


  always@(*) begin
    case(round)
      0: addroundkeyIN = state;
      10: addroundkeyIN = shiftrows_;
      default: addroundkeyIN = mixcolumns_; 
    endcase
  end


  always@(posedge clk or negedge rstn) begin
    if(!rstn) begin
      state <= {NB{1'b0}};
      roundkey <= {NB{1'b0}};
      round <= {4{1'b0}};
      done <= 1;
    end
    else 
      if(!done) begin
        if(round == 10) begin
          done <= 1'b1;
        end
        round <= round + 1;
        state <= addroundkey_;
        roundkey <= keyexpansion_;
      end

      else
        if(start) begin
          done <= 1'b0;
          roundkey <= key_flipped;
          state <= plain_text_flipped;
        end 
        else begin
          roundkey <= {NB{1'b0}};
          round <= {4{1'b0}};
          done <= 1;
        end
  end
  
  wire [NB-1:0] plain_text_flipped;
  wire [NB-1:0] key_flipped;

  FlipBytes flipOUT (.in(state),.out(cipher_text));
  FlipBytes flipPLAIN_TEXT (.in(plain_text),.out(plain_text_flipped));
  FlipBytes flipKEY (.in(key),.out(key_flipped));


endmodule
module aes_cipher #(parameter NB = 128, NC = 4, NK = 4, NR = 10, BYTE = 8, WORD = 32) 
                 (input clk, rstn, start, output reg done,
                  input [NB-1:0] plain_text, key,
                  output [NB-1:0] cipher_text);



  reg [NB-1:0] state, roundkey;
  reg [3:0] round;

  reg [NB-1:0] addroundkeyIN;
  wire [NB-1:0] subbytes_, shiftrows_, mixcolumns_, addroundkey_, keyexpansion_;
  
  SubBytes sbox(.in(state),.out(subbytes_));
  ShiftRows shiftrows(.in(subbytes_),.out(shiftrows_));
  MixColumns mixcolumns(.in(shiftrows_),.out(mixcolumns_));
  AddRoundKey addroundkey(.in(addroundkeyIN),.key(roundkey),.out(addroundkey_));
  KeyExpansion keyexpansion(.RoundNumber(round),.RoundKey(roundkey),.NextRoundKey(keyexpansion_));


  always@(*) begin
    case(round)
      0: addroundkeyIN = state;
      10: addroundkeyIN = shiftrows_;
      default: addroundkeyIN = mixcolumns_; 
    endcase
  end


  always@(posedge clk or negedge rstn) begin
    if(!rstn) begin
      state <= {NB{1'b0}};
      roundkey <= {NB{1'b0}};
      round <= {4{1'b0}};
      done <= 1;
    end
    else 
      if(!done) begin
        if(round == 10) begin
          done <= 1'b1;
        end
        round <= round + 1;
        state <= addroundkey_;
        roundkey <= keyexpansion_;
      end

      else
        if(start) begin
          done <= 1'b0;
          roundkey <= key_flipped;
          state <= plain_text_flipped;
        end 
        else begin
          roundkey <= {NB{1'b0}};
          round <= {4{1'b0}};
          done <= 1;
        end
  end
  
  wire [NB-1:0] plain_text_flipped;
  wire [NB-1:0] key_flipped;

  FlipBytes flipOUT (.in(state),.out(cipher_text));
  FlipBytes flipPLAIN_TEXT (.in(plain_text),.out(plain_text_flipped));
  FlipBytes flipKEY (.in(key),.out(key_flipped));


endmodule