data/full_repos/permissive/104305228/code/ex.v
1: b'%Error: data/full_repos/permissive/104305228/code/ex.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/ex.v:8: syntax error, unexpected type, expecting IDENTIFIER or \'[\' or do or final\n input [2:0] type,\n             ^~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:15: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input [4:0] write_addr_i,\n ^~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:17: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n input [31:0] write_instr_i,\n ^~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:19: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg stallsignal\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:24: Define or directive not defined: \'`op_sub\'\n wire [31:0] reg_sum = reg1_i + (op_i == `op_sub || op_i == `op_subu || op_i == `op_slt ? reg2_comp : reg2_i);\n                                         ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:24: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n wire [31:0] reg_sum = reg1_i + (op_i == `op_sub || op_i == `op_subu || op_i == `op_slt ? reg2_comp : reg2_i);\n                                                 ^~\n%Error: data/full_repos/permissive/104305228/code/ex.v:24: Define or directive not defined: \'`op_subu\'\n wire [31:0] reg_sum = reg1_i + (op_i == `op_sub || op_i == `op_subu || op_i == `op_slt ? reg2_comp : reg2_i);\n                                                            ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:24: Define or directive not defined: \'`op_slt\'\n wire [31:0] reg_sum = reg1_i + (op_i == `op_sub || op_i == `op_subu || op_i == `op_slt ? reg2_comp : reg2_i);\n                                                                                ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:31: syntax error, unexpected always\n always @ (*) begin\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:32: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:37: Define or directive not defined: \'`op_and\'\n    `op_and : begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:40: Define or directive not defined: \'`op_or\'\n    `op_or : begin\n    ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:43: Define or directive not defined: \'`op_xor\'\n    `op_xor : begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:46: Define or directive not defined: \'`op_nor\'\n    `op_nor : begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:56: syntax error, unexpected always\n always @ (*) begin\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:57: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:62: Define or directive not defined: \'`op_slt\'\n    `op_slt : begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:65: Define or directive not defined: \'`op_sltu\'\n    `op_sltu : begin\n    ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:68: Define or directive not defined: \'`op_add\'\n    `op_add, `op_addu, `op_sub, `op_subu : begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:68: Define or directive not defined: \'`op_addu\'\n    `op_add, `op_addu, `op_sub, `op_subu : begin\n             ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:68: Define or directive not defined: \'`op_sub\'\n    `op_add, `op_addu, `op_sub, `op_subu : begin\n                       ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:68: Define or directive not defined: \'`op_subu\'\n    `op_add, `op_addu, `op_sub, `op_subu : begin\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:78: syntax error, unexpected always\n always @ (*) begin\n ^~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:79: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:88: Define or directive not defined: \'`op_add\'\n   `op_add : begin\n   ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:90: Define or directive not defined: \'`WriteDisable\'\n     we_o <= `WriteDisable;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:96: Define or directive not defined: \'`op_sub\'\n   `op_sub : begin\n   ^~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:98: Define or directive not defined: \'`WriteDisable\'\n     we_o <= `WriteDisable;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:110: Define or directive not defined: \'`type_logic\'\n   `type_logic : begin\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:113: Define or directive not defined: \'`type_arith\'\n   `type_arith : begin\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex.v:116: Define or directive not defined: \'`type_jmp\'\n   `type_jmp : begin\n   ^~~~~~~~~\n%Error: Exiting due to 32 error(s)\n'
module ex(
	input rst,
	input [31:0] instr_i,
	output [31:0] instr_o,
	input [7:0] op_i,
	output [7:0] op_o,
	input [2:0] type,
	input [31:0] reg1_i,
	output [31:0] reg1_o,
	input [31:0] reg2_i,
	output [31:0] reg2_o,
	input we_i,
	output reg we_o,
	input [4:0] write_addr_i,
	output reg[4:0] write_addr_o,
	input [31:0] write_instr_i,
	output reg[31:0] write_instr_o,
	output reg stallsignal
);

	wire [31:0] reg1_comp = ~reg1_i + 1;
	wire [31:0] reg2_comp = ~reg2_i + 1;
	wire [31:0] reg_sum = reg1_i + (op_i == `op_sub || op_i == `op_subu || op_i == `op_slt ? reg2_comp : reg2_i);
	assign instr_o = instr_i;
	assign op_o = op_i;
	assign reg1_o = reg1_i;
	assign reg2_o = reg2_i;

	reg [31:0] res_logic;
	always @ (*) begin
		if (rst == `RstEnable) begin
			res_logic <= 32'b0;
		end
		else begin
			case (op_i)
				`op_and : begin
					res_logic <= reg1_i & reg2_i;
				end
				`op_or : begin
					res_logic <= reg1_i | reg2_i;
				end
				`op_xor : begin
					res_logic <= reg1_i ^ reg2_i;
				end
				`op_nor : begin
					res_logic <= ~(reg1_i | reg2_i);
				end
				default : begin
					res_logic <= 32'b0;
				end
			endcase
		end
	end
	reg[63:0] res_arith;
	always @ (*) begin
		if (rst == `RstEnable) begin
			res_arith <= 32'b0;
		end
		else begin
			case (op_i)
				`op_slt : begin
					res_arith <= (reg1_i[31] == 1'b1 && reg2_i[31] == 1'b0) || (reg1_i[31] == reg2_i[31] && reg_sum[31] == 1'b1);
				end
				`op_sltu : begin
					res_arith <= reg1_i < reg2_i;
				end
				`op_add, `op_addu, `op_sub, `op_subu : begin
					res_arith <= reg_sum;
				end
				default : begin
					res_arith <= 32'b0;
				end
			endcase
		end
	end
	reg[31:0] res_jmp;
	always @ (*) begin
		if (rst == `RstEnable) begin
			res_jmp <= 32'b0;
		end
		else begin
			res_jmp <= write_instr_i;
		end
	end
	always @ (*) begin
		case (op_i)
			`op_add : begin
				if (reg1_i[31] == reg2_i[31] && reg_sum[31] != reg1_i[31]) begin
					we_o <= `WriteDisable;
				end
				else begin
					we_o <= we_i;
				end
			end
			`op_sub : begin
				if (reg1_i[31] == reg2_comp[31] && reg1_i != reg_sum[31]) begin
					we_o <= `WriteDisable;
				end
				else begin
					we_o <= we_i;
				end
			end
			default : begin
				we_o <= we_i;
			end
		endcase
		write_addr_o <= write_addr_i;
		case (type)
			`type_logic : begin
				write_instr_o <= res_logic;
			end
			`type_arith : begin
				write_instr_o <= res_arith[31:0];
			end
			`type_jmp : begin
				write_instr_o <= res_jmp;
			end
			default : begin
				write_instr_o <= 32'b0;
			end
		endcase
	end
endmodule
module ex(
	input rst,
	input [31:0] instr_i,
	output [31:0] instr_o,
	input [7:0] op_i,
	output [7:0] op_o,
	input [2:0] type,
	input [31:0] reg1_i,
	output [31:0] reg1_o,
	input [31:0] reg2_i,
	output [31:0] reg2_o,
	input we_i,
	output reg we_o,
	input [4:0] write_addr_i,
	output reg[4:0] write_addr_o,
	input [31:0] write_instr_i,
	output reg[31:0] write_instr_o,
	output reg stallsignal
);


	wire [31:0] reg1_comp = ~reg1_i + 1;
	wire [31:0] reg2_comp = ~reg2_i + 1;
	wire [31:0] reg_sum = reg1_i + (op_i == `op_sub || op_i == `op_subu || op_i == `op_slt ? reg2_comp : reg2_i);
	assign instr_o = instr_i;
	assign op_o = op_i;
	assign reg1_o = reg1_i;
	assign reg2_o = reg2_i;

	reg [31:0] res_logic;
	always @ (*) begin
		if (rst == `RstEnable) begin
			res_logic <= 32'b0;
		end
		else begin
			case (op_i)
				`op_and : begin
					res_logic <= reg1_i & reg2_i;
				end
				`op_or : begin
					res_logic <= reg1_i | reg2_i;
				end
				`op_xor : begin
					res_logic <= reg1_i ^ reg2_i;
				end
				`op_nor : begin
					res_logic <= ~(reg1_i | reg2_i);
				end
				default : begin
					res_logic <= 32'b0;
				end
			endcase
		end
	end
	reg[63:0] res_arith;
	always @ (*) begin
		if (rst == `RstEnable) begin
			res_arith <= 32'b0;
		end
		else begin
			case (op_i)
				`op_slt : begin
					res_arith <= (reg1_i[31] == 1'b1 && reg2_i[31] == 1'b0) || (reg1_i[31] == reg2_i[31] && reg_sum[31] == 1'b1);
				end
				`op_sltu : begin
					res_arith <= reg1_i < reg2_i;
				end
				`op_add, `op_addu, `op_sub, `op_subu : begin
					res_arith <= reg_sum;
				end
				default : begin
					res_arith <= 32'b0;
				end
			endcase
		end
	end
	reg[31:0] res_jmp;
	always @ (*) begin
		if (rst == `RstEnable) begin
			res_jmp <= 32'b0;
		end
		else begin
			res_jmp <= write_instr_i;
		end
	end
	always @ (*) begin
		case (op_i)
			`op_add : begin
				if (reg1_i[31] == reg2_i[31] && reg_sum[31] != reg1_i[31]) begin
					we_o <= `WriteDisable;
				end
				else begin
					we_o <= we_i;
				end
			end
			`op_sub : begin
				if (reg1_i[31] == reg2_comp[31] && reg1_i != reg_sum[31]) begin
					we_o <= `WriteDisable;
				end
				else begin
					we_o <= we_i;
				end
			end
			default : begin
				we_o <= we_i;
			end
		endcase
		write_addr_o <= write_addr_i;
		case (type)
			`type_logic : begin
				write_instr_o <= res_logic;
			end
			`type_arith : begin
				write_instr_o <= res_arith[31:0];
			end
			`type_jmp : begin
				write_instr_o <= res_jmp;
			end
			default : begin
				write_instr_o <= 32'b0;
			end
		endcase
	end
endmodule