data/full_repos/permissive/143278/ivltests/pr1695309.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1695309.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== (A|B)) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module OR2 (Z, A, B);
   output Z;
   input A;
   input B;

   or (Z, A, B);
endmodule
module OR2 (Z, A, B);

   output Z;
   input A;
   input B;

   or (Z, A, B);
endmodule