data/full_repos/permissive/202237519/verilog/digitalsystem project/rtb.v
1: b'%Error: Cannot find file containing module: project,data/full_repos/permissive/202237519\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem/project,data/full_repos/permissive/202237519\n             data/full_repos/permissive/202237519/verilog/digitalsystem/project,data/full_repos/permissive/202237519.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem/project,data/full_repos/permissive/202237519.sv\n             project,data/full_repos/permissive/202237519\n             project,data/full_repos/permissive/202237519.v\n             project,data/full_repos/permissive/202237519.sv\n             obj_dir/project,data/full_repos/permissive/202237519\n             obj_dir/project,data/full_repos/permissive/202237519.v\n             obj_dir/project,data/full_repos/permissive/202237519.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/202237519/verilog/digitalsystem\n%Error: Cannot find file containing module: project/rtb.v\n%Error: Exiting due to 3 error(s)\n'
module rtb;

reg menu1, menu2, back;
reg CLK, RESETN;
reg [7:0]key;
wire [7:0]led;
wire piezo;

wire LCD_E, LCD_RS, LCD_RW;
wire [7:0]LCD_DATA;

wire [3:0] R,G,B;

rhythm rhythm(menu1, menu2, back, CLK, piezo, led, key, RESETN, LCD_E,
            LCD_RS, LCD_RW, LCD_DATA, R, G, B);

always #1 CLK <= ~CLK;

initial 
    begin
        $dumpfile("rtb.vcd");
        $dumpvars(0,rtb);
        CLK <= 1'b0; back<= 1'b0; menu2 <= 1'b0; 
        key <= 0;
        RESETN <= 1'b1; #100;
        RESETN <= 1'b0; #10;
        menu1 <= 1'b1; #1000;
        menu1 <= 1'b0; back<= 1'b1; #1000;
        back <= 1'b0; menu2 <= 1'b1; #1000;
        menu2 <= 1'b0; back <= 1'b1; #1000;
        back <= 1'b0; menu1 <= 1'b1; #1000;
        key <= 8'b00000001; #1500;
        key <= 0; #100;
        key <= 8'b00000001; #1000;
        key <= 8'b00000010; #40000;
        back <= 1'b1; #1000;
        back <= 1'b0; #1000;
        key <= 8'b00000010; #4000;
        key <= 0; #40000;

        $finish;
    end
endmodule
module rtb;


reg menu1, menu2, back;
reg CLK, RESETN;
reg [7:0]key;
wire [7:0]led;
wire piezo;

wire LCD_E, LCD_RS, LCD_RW;
wire [7:0]LCD_DATA;

wire [3:0] R,G,B;

rhythm rhythm(menu1, menu2, back, CLK, piezo, led, key, RESETN, LCD_E,
            LCD_RS, LCD_RW, LCD_DATA, R, G, B);

always #1 CLK <= ~CLK;

initial 
    begin
        $dumpfile("rtb.vcd");
        $dumpvars(0,rtb);
        CLK <= 1'b0; back<= 1'b0; menu2 <= 1'b0; 
        key <= 0;
        RESETN <= 1'b1; #100;
        RESETN <= 1'b0; #10;
        menu1 <= 1'b1; #1000;
        menu1 <= 1'b0; back<= 1'b1; #1000;
        back <= 1'b0; menu2 <= 1'b1; #1000;
        menu2 <= 1'b0; back <= 1'b1; #1000;
        back <= 1'b0; menu1 <= 1'b1; #1000;
        key <= 8'b00000001; #1500;
        key <= 0; #100;
        key <= 8'b00000001; #1000;
        key <= 8'b00000010; #40000;
        back <= 1'b1; #1000;
        back <= 1'b0; #1000;
        key <= 8'b00000010; #4000;
        key <= 0; #40000;

        $finish;
    end
endmodule