data/full_repos/permissive/167274925/InstructionFetchUnit_tb.v
 line:40: before: "clkb"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167274925/InstructionFetchUnit_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167274925/InstructionFetchUnit_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/InstructionFetchUnit_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n   #200;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/InstructionFetchUnit_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: data/full_repos/permissive/167274925/InstructionFetchUnit_tb.v:26: Cannot find file containing module: \'InstructionFetchUnit\'\n   InstructionFetchUnit  m1(.Instruction(Instruction),.Reset(Reset),.Clk(Clk));\n   ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/InstructionFetchUnit\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/InstructionFetchUnit.v\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/InstructionFetchUnit.sv\n             InstructionFetchUnit\n             InstructionFetchUnit.v\n             InstructionFetchUnit.sv\n             obj_dir/InstructionFetchUnit\n             obj_dir/InstructionFetchUnit.v\n             obj_dir/InstructionFetchUnit.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module InstructionFetchUnit_tb( );
   reg Clk,Reset;
   wire [31:0] Instruction;
   InstructionFetchUnit  m1(.Instruction(Instruction),.Reset(Reset),.Clk(Clk));
   always begin 
   Clk<=0;
   #100;
   Clk<=1;
   #100;
   end 
   initial begin 
   Reset<=1;
   #200;
   Reset<=0;
   #100;
   end 
endmodule
module InstructionFetchUnit_tb( );

   reg Clk,Reset;
   wire [31:0] Instruction;
   InstructionFetchUnit  m1(.Instruction(Instruction),.Reset(Reset),.Clk(Clk));
   always begin 
   Clk<=0;
   #100;
   Clk<=1;
   #100;
   end 
   initial begin 
   Reset<=1;
   #200;
   Reset<=0;
   #100;
   end 
endmodule