data/full_repos/permissive/136056083/src/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136056083/src/ALU.v:51: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s OR generates 32 bits.\n                                                                 : ... In instance ALU\n                4\'b0101: result = ! (inOne | inTwo); \n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136056083/src/ALU.v:51: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGNOT generates 1 bits.\n                                                                 : ... In instance ALU\n                4\'b0101: result = ! (inOne | inTwo); \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/136056083/src/ALU.v:52: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s AND generates 32 bits.\n                                                                 : ... In instance ALU\n                4\'b1100: result = ! (inOne & inTwo); \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/136056083/src/ALU.v:52: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LOGNOT generates 1 bits.\n                                                                 : ... In instance ALU\n                4\'b1100: result = ! (inOne & inTwo); \n                                ^\n%Error: Exiting due to 4 warning(s)\n'
module ALU (inOne, inTwo, opcode,result, zeroFlag, clock, carryBit, invertZeroFlag);

 wire memReadFlag;
 input clock;
 input [31:0] inOne;
 input [31:0] inTwo;
 input [3:0] opcode;
 input invertZeroFlag;

 output reg [31:0] result;
 output reg zeroFlag;
 output reg carryBit;




 reg [3:0] syncALU;
 initial begin syncALU = 0; end
 
 always @(posedge clock) begin

        if (inTwo == 0) begin
            if (invertZeroFlag == 1) begin
                zeroFlag = 0;
            end
            else begin
                zeroFlag = 1;
            end
        end
        else begin
            if (invertZeroFlag == 1) begin
                zeroFlag = 1;
            end
            else begin
                zeroFlag = 0;
            end
        end
        syncALU = syncALU + 1;
        
        if (syncALU == 3) begin
            case(opcode)
                4'b0010: {carryBit,result} = inOne + inTwo;
                4'b0111: result = inTwo;
                4'b1010: {carryBit,result} = inOne - inTwo;
                4'b0110: result = inOne & inTwo;
                4'b0100: result = inOne | inTwo;
                4'b1001: result = inOne ^ inTwo;
                4'b0101: result = ! (inOne | inTwo);
                4'b1100: result = ! (inOne & inTwo);
                4'b1101: result = inOne;
                default: result = 0;
            endcase
        end
        else if (syncALU==5) begin
            syncALU = 0;
        end
	end
endmodule
module ALU (inOne, inTwo, opcode,result, zeroFlag, clock, carryBit, invertZeroFlag);


 wire memReadFlag;
 input clock;
 input [31:0] inOne;
 input [31:0] inTwo;
 input [3:0] opcode;
 input invertZeroFlag;

 output reg [31:0] result;
 output reg zeroFlag;
 output reg carryBit;




 reg [3:0] syncALU;
 initial begin syncALU = 0; end
 
 always @(posedge clock) begin

        if (inTwo == 0) begin
            if (invertZeroFlag == 1) begin
                zeroFlag = 0;
            end
            else begin
                zeroFlag = 1;
            end
        end
        else begin
            if (invertZeroFlag == 1) begin
                zeroFlag = 1;
            end
            else begin
                zeroFlag = 0;
            end
        end
        syncALU = syncALU + 1;
        
        if (syncALU == 3) begin
            case(opcode)
                4'b0010: {carryBit,result} = inOne + inTwo;
                4'b0111: result = inTwo;
                4'b1010: {carryBit,result} = inOne - inTwo;
                4'b0110: result = inOne & inTwo;
                4'b0100: result = inOne | inTwo;
                4'b1001: result = inOne ^ inTwo;
                4'b0101: result = ! (inOne | inTwo);
                4'b1100: result = ! (inOne & inTwo);
                4'b1101: result = inOne;
                default: result = 0;
            endcase
        end
        else if (syncALU==5) begin
            syncALU = 0;
        end
	end
endmodule