data/full_repos/permissive/19905110/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl/dbg_comm.v
 line:161: before: "negedge"
1: b'%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl/dbg_comm.v:124: Unsupported: Ignoring delay on this delayed statement.\n  forever #5 SYS_CLK = ~SYS_CLK; \n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl/dbg_comm.v:131: Unsupported: Ignoring delay on this delayed statement.\n   #200 SYS_RSTN = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl/dbg_comm.v:132: Unsupported: Ignoring delay on this delayed statement.\n   #5000 SYS_RSTN = 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl/dbg_comm.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #5500;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19905110/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl/dbg_comm.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #Tp;\n    ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl/dbg_comm.v:152: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n      handle1 = $fopen("e:/tmp/gdb_out.dat");\n                ^~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl/dbg_comm.v:163: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n  handle2 = $fopen("e:/tmp/gdb_in.dat");\n            ^~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dbg_comm(
   SYS_CLK,
   SYS_RSTN,
   P_TMS, 
   P_TCK, 
   P_TRST, 
   P_TDI, 
   P_TDO
   );

parameter Tp = 20;

output  SYS_CLK;
output  SYS_RSTN;
output		P_TMS;
output		P_TCK;
output		P_TRST;
output		P_TDI;
input		 P_TDO;


reg SYS_CLK;
reg SYS_RSTN;


integer handle1, handle2;
reg [4:0] memory[0:0];

wire P_TCK;
wire P_TRST;
wire P_TDI;
wire P_TMS;
wire P_TDO;


reg [3:0] in_word_r;




initial
begin
  SYS_CLK = 1'b0;
  forever #5 SYS_CLK = ~SYS_CLK; 
end


initial
begin
   SYS_RSTN = 1'b1;
   #200 SYS_RSTN = 1'b0;
   #5000 SYS_RSTN = 1'b1;
end


initial
begin
  in_word_r = 4'h0;
end


initial
begin
  #5500;
  while(1)
  begin
    #Tp;
    $readmemh(`GDB_OUT, memory);
    if(!(memory[0] & 5'b10000))
    begin
	   in_word_r = memory[0][3:0];
      handle1 = $fopen(`GDB_OUT);
      $fwrite(handle1, "%h", 5'b10000 | memory[0]);
      $fflush(handle1);
      $fclose(handle1);
    end
  end
end


always @ (P_TDO or negedge P_TCK)
begin
  handle2 = $fopen(`GDB_IN);
  $fdisplay(handle2, "%b", P_TDO);
  $fflush(handle2);
  $fclose(handle2);
end


assign P_TCK = in_word_r[0];
assign P_TRST = in_word_r[1];
assign P_TDI = in_word_r[2];
assign P_TMS = in_word_r[3];


endmodule
module dbg_comm(
   SYS_CLK,
   SYS_RSTN,
   P_TMS, 
   P_TCK, 
   P_TRST, 
   P_TDI, 
   P_TDO
   );


parameter Tp = 20;

output  SYS_CLK;
output  SYS_RSTN;
output		P_TMS;
output		P_TCK;
output		P_TRST;
output		P_TDI;
input		 P_TDO;


reg SYS_CLK;
reg SYS_RSTN;


integer handle1, handle2;
reg [4:0] memory[0:0];

wire P_TCK;
wire P_TRST;
wire P_TDI;
wire P_TMS;
wire P_TDO;


reg [3:0] in_word_r;




initial
begin
  SYS_CLK = 1'b0;
  forever #5 SYS_CLK = ~SYS_CLK; 
end


initial
begin
   SYS_RSTN = 1'b1;
   #200 SYS_RSTN = 1'b0;
   #5000 SYS_RSTN = 1'b1;
end


initial
begin
  in_word_r = 4'h0;
end


initial
begin
  #5500;
  while(1)
  begin
    #Tp;
    $readmemh(`GDB_OUT, memory);
    if(!(memory[0] & 5'b10000))
    begin
	   in_word_r = memory[0][3:0];
      handle1 = $fopen(`GDB_OUT);
      $fwrite(handle1, "%h", 5'b10000 | memory[0]);
      $fflush(handle1);
      $fclose(handle1);
    end
  end
end


always @ (P_TDO or negedge P_TCK)
begin
  handle2 = $fopen(`GDB_IN);
  $fdisplay(handle2, "%b", P_TDO);
  $fflush(handle2);
  $fclose(handle2);
end


assign P_TCK = in_word_r[0];
assign P_TRST = in_word_r[1];
assign P_TDI = in_word_r[2];
assign P_TMS = in_word_r[3];


endmodule