data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_writer.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/dma_writer.v:69: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module dma_writer #(
  parameter DataBits      = 64,
  parameter AddrBits      = 32,
  parameter LengthBits    = 16,
  parameter FifoUsedBits  = 7)
(
  input                     clk,
  input                     rst,

  input [AddrBits-1:0]      cfg_dest,
  input [LengthBits-1:0]    cfg_len,
  input [4:0]               cfg_burst,
  input                     cfg_valid,
  output                    cfg_busy,
  output reg                cfg_done,
  output [LengthBits-1:0]   cfg_remain,
  output reg [1:0]          cfg_err,

  input                     din_valid,
  output                    din_ready,
  input [DataBits-1:0]      din_data,
  input [FifoUsedBits-1:0]  din_fifo_used,

  output reg                mst_awvalid,
  input                     mst_awready,
  output [3:0]              mst_awid,
  output reg [AddrBits-1:0] mst_awaddr,
  output reg [3:0]          mst_awlen,
  output [2:0]              mst_awsize,
  output [1:0]              mst_awburst,
  output [1:0]              mst_awlock,

  output                    mst_wvalid,
  input                     mst_wready,
  output [3:0]              mst_wid,
  output [DataBits/8-1:0]   mst_wstrb,
  output                    mst_wlast,
  output [DataBits-1:0]     mst_wdata,

  input                     mst_bvalid,
  output                    mst_bready,
  input [3:0]               mst_bid,
  input [1:0]               mst_bresp);

`include "util.vh"

  localparam BurstBits = 5;
  localparam BytesPerWord = DataBits / 8;

  wire                mst_wvalid_i;
  wire                mst_wready_i;
  wire                mst_wlast_i;
  wire [DataBits-1:0] mst_wdata_i;




  localparam Idle        = 0,
             PrepBurst1  = 1,
             PrepBurst2  = 2,
             WaitFifo    = 3,
             DoBurst     = 4,
             WaitFinal   = 5,
             Done        = 6,
             NumStates   = 7;

  reg [clog2(NumStates)-1:0] state;
  reg [BurstBits-1:0]        burst_remain, burst_cand;
  reg [LengthBits-1:0]       total_remain;
  reg [AddrBits-1:0]         next_addr;
  reg [9:0]                 until_4k;
  always @(posedge clk) begin


    if (mst_awready) begin
      mst_awvalid <= 0;
    end

    case (state)

      Idle:
        if (cfg_valid) begin
          if (cfg_len >=1 ) begin
            total_remain <= cfg_len;
            next_addr    <= cfg_dest;
            state        <= PrepBurst1;
          end else begin
            cfg_done <= 1;
            state    <= Done;
          end
        end

      PrepBurst1:
        begin
          burst_cand <= min(total_remain, cfg_burst);
          until_4k   <= (13'h1000 - next_addr[11:0]) / BytesPerWord;
          state      <= PrepBurst2;
        end

      PrepBurst2:
        begin

          burst_remain <= min(burst_cand, until_4k);
          state        <= WaitFifo;
        end

      WaitFifo:
        if (din_fifo_used >= burst_remain) begin
          if (!mst_awvalid || mst_awready) begin
            mst_awvalid <= 1;
            mst_awlen   <= burst_remain - 1;
            mst_awaddr  <= next_addr;
            next_addr   <= next_addr + (burst_remain * BytesPerWord);
            state       <= DoBurst;
          end
        end

      DoBurst:
        if (mst_wready_i && mst_wvalid_i) begin
          burst_remain <= burst_remain - 1;
          total_remain <= total_remain - 1;
          if (total_remain == 1) begin
            state <= WaitFinal;
          end else if (burst_remain == 1) begin
            state <= PrepBurst1;
          end
        end

      WaitFinal:

        if (!mst_wvalid) begin
          cfg_done <= 1;
          state    <= Done;
        end

      Done:
        begin

          cfg_done <= 0;
          state    <= Idle;
        end
    endcase


    if (mst_bvalid && mst_bready) begin
      cfg_err <= mst_bresp;
    end

    if (rst) begin
      state        <= Idle;
      mst_awvalid  <= 0;
      cfg_done     <= 0;
      cfg_err      <= 0;
      total_remain <= 0;
    end

  end

  assign cfg_busy    = (state != Idle);
  assign cfg_remain  = total_remain;


  assign mst_wvalid_i  = (state == DoBurst) ? din_valid    : 0;
  assign din_ready     = (state == DoBurst) ? mst_wready_i : 0;
  assign mst_wdata_i   = din_data;
  assign mst_wlast_i   = (burst_remain == 1) ? 1 : 0;


  stream_buf_v #(
    .DataBits(DataBits+1))
  obuf (
    .clk       (clk),
    .rst       (rst),
    .in_valid  (mst_wvalid_i),
    .in_ready  (mst_wready_i),
    .in_data   ({mst_wlast_i, mst_wdata_i}),
    .out_valid (mst_wvalid),
    .out_ready (mst_wready),
    .out_data  ({mst_wlast, mst_wdata}));


  assign mst_bready  = 1'b1;


  assign mst_awid    = 4'b0;
  assign mst_awsize  = clog2(BytesPerWord);
  assign mst_awlock  = 2'b00;
  assign mst_awburst = 2'b01;
  assign mst_wid     = 4'b0;
  assign mst_wstrb   = {DataBits/8{1'b1}};

endmodule
module dma_writer #(
  parameter DataBits      = 64,
  parameter AddrBits      = 32,
  parameter LengthBits    = 16,
  parameter FifoUsedBits  = 7)
(
  input                     clk,
  input                     rst,

  input [AddrBits-1:0]      cfg_dest,
  input [LengthBits-1:0]    cfg_len,
  input [4:0]               cfg_burst,
  input                     cfg_valid,
  output                    cfg_busy,
  output reg                cfg_done,
  output [LengthBits-1:0]   cfg_remain,
  output reg [1:0]          cfg_err,

  input                     din_valid,
  output                    din_ready,
  input [DataBits-1:0]      din_data,
  input [FifoUsedBits-1:0]  din_fifo_used,

  output reg                mst_awvalid,
  input                     mst_awready,
  output [3:0]              mst_awid,
  output reg [AddrBits-1:0] mst_awaddr,
  output reg [3:0]          mst_awlen,
  output [2:0]              mst_awsize,
  output [1:0]              mst_awburst,
  output [1:0]              mst_awlock,

  output                    mst_wvalid,
  input                     mst_wready,
  output [3:0]              mst_wid,
  output [DataBits/8-1:0]   mst_wstrb,
  output                    mst_wlast,
  output [DataBits-1:0]     mst_wdata,

  input                     mst_bvalid,
  output                    mst_bready,
  input [3:0]               mst_bid,
  input [1:0]               mst_bresp);


`include "util.vh"

  localparam BurstBits = 5;
  localparam BytesPerWord = DataBits / 8;

  wire                mst_wvalid_i;
  wire                mst_wready_i;
  wire                mst_wlast_i;
  wire [DataBits-1:0] mst_wdata_i;




  localparam Idle        = 0,
             PrepBurst1  = 1,
             PrepBurst2  = 2,
             WaitFifo    = 3,
             DoBurst     = 4,
             WaitFinal   = 5,
             Done        = 6,
             NumStates   = 7;

  reg [clog2(NumStates)-1:0] state;
  reg [BurstBits-1:0]        burst_remain, burst_cand;
  reg [LengthBits-1:0]       total_remain;
  reg [AddrBits-1:0]         next_addr;
  reg [9:0]                 until_4k;
  always @(posedge clk) begin


    if (mst_awready) begin
      mst_awvalid <= 0;
    end

    case (state)

      Idle:
        if (cfg_valid) begin
          if (cfg_len >=1 ) begin
            total_remain <= cfg_len;
            next_addr    <= cfg_dest;
            state        <= PrepBurst1;
          end else begin
            cfg_done <= 1;
            state    <= Done;
          end
        end

      PrepBurst1:
        begin
          burst_cand <= min(total_remain, cfg_burst);
          until_4k   <= (13'h1000 - next_addr[11:0]) / BytesPerWord;
          state      <= PrepBurst2;
        end

      PrepBurst2:
        begin

          burst_remain <= min(burst_cand, until_4k);
          state        <= WaitFifo;
        end

      WaitFifo:
        if (din_fifo_used >= burst_remain) begin
          if (!mst_awvalid || mst_awready) begin
            mst_awvalid <= 1;
            mst_awlen   <= burst_remain - 1;
            mst_awaddr  <= next_addr;
            next_addr   <= next_addr + (burst_remain * BytesPerWord);
            state       <= DoBurst;
          end
        end

      DoBurst:
        if (mst_wready_i && mst_wvalid_i) begin
          burst_remain <= burst_remain - 1;
          total_remain <= total_remain - 1;
          if (total_remain == 1) begin
            state <= WaitFinal;
          end else if (burst_remain == 1) begin
            state <= PrepBurst1;
          end
        end

      WaitFinal:

        if (!mst_wvalid) begin
          cfg_done <= 1;
          state    <= Done;
        end

      Done:
        begin

          cfg_done <= 0;
          state    <= Idle;
        end
    endcase


    if (mst_bvalid && mst_bready) begin
      cfg_err <= mst_bresp;
    end

    if (rst) begin
      state        <= Idle;
      mst_awvalid  <= 0;
      cfg_done     <= 0;
      cfg_err      <= 0;
      total_remain <= 0;
    end

  end

  assign cfg_busy    = (state != Idle);
  assign cfg_remain  = total_remain;


  assign mst_wvalid_i  = (state == DoBurst) ? din_valid    : 0;
  assign din_ready     = (state == DoBurst) ? mst_wready_i : 0;
  assign mst_wdata_i   = din_data;
  assign mst_wlast_i   = (burst_remain == 1) ? 1 : 0;


  stream_buf_v #(
    .DataBits(DataBits+1))
  obuf (
    .clk       (clk),
    .rst       (rst),
    .in_valid  (mst_wvalid_i),
    .in_ready  (mst_wready_i),
    .in_data   ({mst_wlast_i, mst_wdata_i}),
    .out_valid (mst_wvalid),
    .out_ready (mst_wready),
    .out_data  ({mst_wlast, mst_wdata}));


  assign mst_bready  = 1'b1;


  assign mst_awid    = 4'b0;
  assign mst_awsize  = clog2(BytesPerWord);
  assign mst_awlock  = 2'b00;
  assign mst_awburst = 2'b01;
  assign mst_wid     = 4'b0;
  assign mst_wstrb   = {DataBits/8{1'b1}};

endmodule