data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi/axis_data_swap.v
1: b'%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi/axis_data_swap.v:33: Operator VAR \'STAGES_EN\' expects 8 bits on the Initial value, but Initial value\'s CONST \'?32?hffffffff\' generates 32 bits.\n                                                                                                                               : ... In instance axis_data_swap\n  parameter [$clog2(DATA_W)-1:0] STAGES_EN = \'hFFFFFFFF,  \n                                 ^~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi/axis_data_swap.v:96: Cannot find file containing module: \'axi_fifo_flop\'\n          axi_fifo_flop #(.WIDTH(DATA_W+SWAP_W+USER_W+1)) reg_i (\n          ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi,data/full_repos/permissive/214858095/axi_fifo_flop\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi,data/full_repos/permissive/214858095/axi_fifo_flop.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi,data/full_repos/permissive/214858095/axi_fifo_flop.sv\n             axi_fifo_flop\n             axi_fifo_flop.v\n             axi_fifo_flop.sv\n             obj_dir/axi_fifo_flop\n             obj_dir/axi_fifo_flop.v\n             obj_dir/axi_fifo_flop.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module axis_data_swap #(
  parameter integer              DATA_W    = 256,
  parameter integer              USER_W    = 1,
  parameter [$clog2(DATA_W)-1:0] STAGES_EN = 'hFFFFFFFF,
  parameter [0:0]                DYNAMIC   = 1
)(

  input  wire                      clk,
  input  wire                      rst,

  input  wire [DATA_W-1:0]         s_axis_tdata,
  input  wire [$clog2(DATA_W)-2:0] s_axis_tswap,
  input  wire [USER_W-1:0]         s_axis_tuser,
  input  wire                      s_axis_tlast,
  input  wire                      s_axis_tvalid,
  output wire                      s_axis_tready,

  output wire [DATA_W-1:0]         m_axis_tdata,
  output wire [USER_W-1:0]         m_axis_tuser,
  output wire                      m_axis_tlast,
  output wire                      m_axis_tvalid,
  input  wire                      m_axis_tready
);

  parameter SWAP_STAGES = $clog2(DATA_W);
  parameter SWAP_W      = $clog2(DATA_W)-1;
  genvar s, w;

  wire [DATA_W-1:0] stg_tdata [0:SWAP_STAGES], stg_tdata_swp[0:SWAP_STAGES], stg_tdata_res[0:SWAP_STAGES];
  wire [SWAP_W-1:0] stg_tswap [0:SWAP_STAGES];
  wire [USER_W-1:0] stg_tuser [0:SWAP_STAGES];
  wire              stg_tlast [0:SWAP_STAGES];
  wire              stg_tvalid[0:SWAP_STAGES];
  wire              stg_tready[0:SWAP_STAGES];


  generate
    assign stg_tdata [0] = s_axis_tdata;
    assign stg_tswap [0] = s_axis_tswap;
    assign stg_tuser [0] = s_axis_tuser;
    assign stg_tlast [0] = s_axis_tlast;
    assign stg_tvalid[0] = s_axis_tvalid;
    assign s_axis_tready = stg_tready[0];

    assign m_axis_tdata            = stg_tdata [SWAP_STAGES];
    assign m_axis_tuser            = stg_tuser [SWAP_STAGES];
    assign m_axis_tlast            = stg_tlast [SWAP_STAGES];
    assign m_axis_tvalid           = stg_tvalid[SWAP_STAGES];
    assign stg_tready[SWAP_STAGES] = m_axis_tready;
  endgenerate


  generate
    for (s = 0; s < SWAP_STAGES; s=s+1) begin
      if (STAGES_EN[SWAP_STAGES-s-1]) begin

        for (w = 0; w < (1<<s); w=w+1) begin
          assign stg_tdata_swp[s][(w*(DATA_W/(1<<s)))+:(DATA_W/(1<<s))] =
            stg_tdata[s][(((1<<s)-w-1)*(DATA_W/(1<<s)))+:(DATA_W/(1<<s))];
        end
        if (DYNAMIC) begin


          assign stg_tdata_res[s] = (s > 0 && stg_tswap[s][SWAP_W-s]) ?
            stg_tdata_swp[s] : stg_tdata[s];

          axi_fifo_flop #(.WIDTH(DATA_W+SWAP_W+USER_W+1)) reg_i (
            .clk(clk), .reset(rst), .clear(1'b0),
            .i_tdata({stg_tlast[s], stg_tuser[s], stg_tswap[s], stg_tdata_res[s]}),
            .i_tvalid(stg_tvalid[s]), .i_tready(stg_tready[s]),
            .o_tdata({stg_tlast[s+1], stg_tuser[s+1], stg_tswap[s+1], stg_tdata[s+1]}),
            .o_tvalid(stg_tvalid[s+1]), .o_tready(stg_tready[s+1]),
            .occupied(), .space()
          );
        end else begin

          assign stg_tdata [s+1] = stg_tdata_swp[s];
          assign stg_tswap [s+1] = stg_tswap    [s];
          assign stg_tuser [s+1] = stg_tuser    [s];
          assign stg_tlast [s+1] = stg_tlast    [s];
          assign stg_tvalid[s+1] = stg_tvalid   [s];
          assign stg_tready[s]   = stg_tready   [s+1];
        end
      end else begin

        assign stg_tdata [s+1] = stg_tdata [s];
        assign stg_tswap [s+1] = stg_tswap [s];
        assign stg_tuser [s+1] = stg_tuser [s];
        assign stg_tlast [s+1] = stg_tlast [s];
        assign stg_tvalid[s+1] = stg_tvalid[s];
        assign stg_tready[s]   = stg_tready[s+1];
      end
    end
  endgenerate

endmodule
module axis_data_swap #(
  parameter integer              DATA_W    = 256,
  parameter integer              USER_W    = 1,
  parameter [$clog2(DATA_W)-1:0] STAGES_EN = 'hFFFFFFFF,
  parameter [0:0]                DYNAMIC   = 1
)(

  input  wire                      clk,
  input  wire                      rst,

  input  wire [DATA_W-1:0]         s_axis_tdata,
  input  wire [$clog2(DATA_W)-2:0] s_axis_tswap,
  input  wire [USER_W-1:0]         s_axis_tuser,
  input  wire                      s_axis_tlast,
  input  wire                      s_axis_tvalid,
  output wire                      s_axis_tready,

  output wire [DATA_W-1:0]         m_axis_tdata,
  output wire [USER_W-1:0]         m_axis_tuser,
  output wire                      m_axis_tlast,
  output wire                      m_axis_tvalid,
  input  wire                      m_axis_tready
);


  parameter SWAP_STAGES = $clog2(DATA_W);
  parameter SWAP_W      = $clog2(DATA_W)-1;
  genvar s, w;

  wire [DATA_W-1:0] stg_tdata [0:SWAP_STAGES], stg_tdata_swp[0:SWAP_STAGES], stg_tdata_res[0:SWAP_STAGES];
  wire [SWAP_W-1:0] stg_tswap [0:SWAP_STAGES];
  wire [USER_W-1:0] stg_tuser [0:SWAP_STAGES];
  wire              stg_tlast [0:SWAP_STAGES];
  wire              stg_tvalid[0:SWAP_STAGES];
  wire              stg_tready[0:SWAP_STAGES];


  generate
    assign stg_tdata [0] = s_axis_tdata;
    assign stg_tswap [0] = s_axis_tswap;
    assign stg_tuser [0] = s_axis_tuser;
    assign stg_tlast [0] = s_axis_tlast;
    assign stg_tvalid[0] = s_axis_tvalid;
    assign s_axis_tready = stg_tready[0];

    assign m_axis_tdata            = stg_tdata [SWAP_STAGES];
    assign m_axis_tuser            = stg_tuser [SWAP_STAGES];
    assign m_axis_tlast            = stg_tlast [SWAP_STAGES];
    assign m_axis_tvalid           = stg_tvalid[SWAP_STAGES];
    assign stg_tready[SWAP_STAGES] = m_axis_tready;
  endgenerate


  generate
    for (s = 0; s < SWAP_STAGES; s=s+1) begin
      if (STAGES_EN[SWAP_STAGES-s-1]) begin

        for (w = 0; w < (1<<s); w=w+1) begin
          assign stg_tdata_swp[s][(w*(DATA_W/(1<<s)))+:(DATA_W/(1<<s))] =
            stg_tdata[s][(((1<<s)-w-1)*(DATA_W/(1<<s)))+:(DATA_W/(1<<s))];
        end
        if (DYNAMIC) begin


          assign stg_tdata_res[s] = (s > 0 && stg_tswap[s][SWAP_W-s]) ?
            stg_tdata_swp[s] : stg_tdata[s];

          axi_fifo_flop #(.WIDTH(DATA_W+SWAP_W+USER_W+1)) reg_i (
            .clk(clk), .reset(rst), .clear(1'b0),
            .i_tdata({stg_tlast[s], stg_tuser[s], stg_tswap[s], stg_tdata_res[s]}),
            .i_tvalid(stg_tvalid[s]), .i_tready(stg_tready[s]),
            .o_tdata({stg_tlast[s+1], stg_tuser[s+1], stg_tswap[s+1], stg_tdata[s+1]}),
            .o_tvalid(stg_tvalid[s+1]), .o_tready(stg_tready[s+1]),
            .occupied(), .space()
          );
        end else begin

          assign stg_tdata [s+1] = stg_tdata_swp[s];
          assign stg_tswap [s+1] = stg_tswap    [s];
          assign stg_tuser [s+1] = stg_tuser    [s];
          assign stg_tlast [s+1] = stg_tlast    [s];
          assign stg_tvalid[s+1] = stg_tvalid   [s];
          assign stg_tready[s]   = stg_tready   [s+1];
        end
      end else begin

        assign stg_tdata [s+1] = stg_tdata [s];
        assign stg_tswap [s+1] = stg_tswap [s];
        assign stg_tuser [s+1] = stg_tuser [s];
        assign stg_tlast [s+1] = stg_tlast [s];
        assign stg_tvalid[s+1] = stg_tvalid[s];
        assign stg_tready[s]   = stg_tready[s+1];
      end
    end
  endgenerate

endmodule