data/full_repos/permissive/133863909/Arithmetic Logic Unit/testbench.v
 line:20: before: "("
1: b'%Error: Cannot find file containing module: Logic\n        ... Looked in:\n             data/full_repos/permissive/133863909/Arithmetic/Logic\n             data/full_repos/permissive/133863909/Arithmetic/Logic.v\n             data/full_repos/permissive/133863909/Arithmetic/Logic.sv\n             Logic\n             Logic.v\n             Logic.sv\n             obj_dir/Logic\n             obj_dir/Logic.v\n             obj_dir/Logic.sv\n%Error: Cannot find file containing module: Unit,data/full_repos/permissive/133863909\n%Error: Cannot find file containing module: data/full_repos/permissive/133863909/Arithmetic\n%Error: Cannot find file containing module: Unit/testbench.v\n%Error: Exiting due to 4 error(s)\n'
module Testbench();

reg [4:0] X; 
reg [4:0] Y;
reg [1:0] S;
 
wire [4:0] F;
wire cout, overflow, zero, negative;

analysis a(F, cout, overflow, zero, negative, S, X, Y);

initial begin
    $dumpfile("TimingDiagram.vcd");
	$dumpvars(0, F, cout, overflow, zero, negative, S, X, Y);
	
	S = 2'b00;
	
	repeat (4) begin
	
		X = 5'b00000;
	
		repeat (32) begin
		
			Y = 5'b00000;
					
			repeat (32) begin

				Y = Y + 5'b00001;		
                #10;
			end
			
			X = X + 5'b00001;
			#10;
			
		end
		
		#10;	
		S = S + 2'b01;
		
	end
	
    $finish;
end

endmodule
module Testbench();


reg [4:0] X; 
reg [4:0] Y;
reg [1:0] S;
 
wire [4:0] F;
wire cout, overflow, zero, negative;

analysis a(F, cout, overflow, zero, negative, S, X, Y);

initial begin
    $dumpfile("TimingDiagram.vcd");
	$dumpvars(0, F, cout, overflow, zero, negative, S, X, Y);
	
	S = 2'b00;
	
	repeat (4) begin
	
		X = 5'b00000;
	
		repeat (32) begin
		
			Y = 5'b00000;
					
			repeat (32) begin

				Y = Y + 5'b00001;		
                #10;
			end
			
			X = X + 5'b00001;
			#10;
			
		end
		
		#10;	
		S = S + 2'b01;
		
	end
	
    $finish;
end

endmodule