data/full_repos/permissive/149912776/verilog_modules/arithmetic_and_logic/full_adder.v
data/verilator_xmls/b8c590f0-1b07-4ffa-80f3-79553ddcdbcd.xml
module full_adder(X, Y, Cin, Cout, Sum);
input X, Y, Cin;
output Cout, Sum;
    assign Sum = X ^ Y ^ Cin;
    assign Cout = (X && Y) || (X && Cin) || (X && Cin);
endmodule
module full_adder(X, Y, Cin, Cout, Sum);

input X, Y, Cin;
output Cout, Sum;
    assign Sum = X ^ Y ^ Cin;
    assign Cout = (X && Y) || (X && Cin) || (X && Cin);
endmodule