data/full_repos/permissive/212763527/others/testbenches/async_trigger_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/others/testbenches/async_trigger_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212763527/others/testbenches/async_trigger_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    always #20 clk = ~clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/others/testbenches/async_trigger_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    always #30 d   = ~d;\n           ^\n%Error: data/full_repos/permissive/212763527/others/testbenches/async_trigger_tb.v:9: Cannot find file containing module: \'async_trigger\'\n    async_trigger uut (\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/others/testbenches,data/full_repos/permissive/212763527/async_trigger\n             data/full_repos/permissive/212763527/others/testbenches,data/full_repos/permissive/212763527/async_trigger.v\n             data/full_repos/permissive/212763527/others/testbenches,data/full_repos/permissive/212763527/async_trigger.sv\n             async_trigger\n             async_trigger.v\n             async_trigger.sv\n             obj_dir/async_trigger\n             obj_dir/async_trigger.v\n             obj_dir/async_trigger.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

    reg clk;
    reg d;

    wire q;
    wire qb;

    async_trigger uut (
        .clk(clk),
        .d(d),
        .q(q),
        .qb(qb)
    );
    initial begin

        clk = 0;
        d   = 0;

        #100;

    end
    always #20 clk = ~clk;
    always #30 d   = ~d;
endmodule
module test;


    reg clk;
    reg d;

    wire q;
    wire qb;

    async_trigger uut (
        .clk(clk),
        .d(d),
        .q(q),
        .qb(qb)
    );
    initial begin

        clk = 0;
        d   = 0;

        #100;

    end
    always #20 clk = ~clk;
    always #30 d   = ~d;
endmodule