data/full_repos/permissive/143278/ivltests/pr2723712.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2723712.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg  [7:0] a;
  reg  [2:0] b;
  wire [7:0] y, z;

  assign y = a >> b;
  assign z = $signed(a) >> $signed(b);

  initial begin

    a = 8'b10101010;
    b = 3'b101;
    #1;


    if (y === z && y === 8'b00000101)
      $display("PASSED");
    else
      $display("FAILED, expected 8'b00000101, got %b/%b", y, z);
  end
endmodule
module top;

  reg  [7:0] a;
  reg  [2:0] b;
  wire [7:0] y, z;

  assign y = a >> b;
  assign z = $signed(a) >> $signed(b);

  initial begin

    a = 8'b10101010;
    b = 3'b101;
    #1;


    if (y === z && y === 8'b00000101)
      $display("PASSED");
    else
      $display("FAILED, expected 8'b00000101, got %b/%b", y, z);
  end
endmodule