data/full_repos/permissive/143278/ivltests/pr1903324.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1903324.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test(input [8:1] data_in) ;

  wire [7:0] data_in_array[4:3];

  assign data_in_array[3] = data_in;
  assign data_in_array[4] = 8'b0;
endmodule
module test(input [8:1] data_in) ;


  wire [7:0] data_in_array[4:3];

  assign data_in_array[3] = data_in;
  assign data_in_array[4] = 8'b0;
endmodule