data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_init_testbench.v
 line:27: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_init_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n  always #125 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_init_testbench.v:27: syntax error, unexpected \'@\'\n    repeat (1000) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_init_testbench.v:55: syntax error, unexpected \'@\'\n    @(posedge initialized);\n    ^\n%Error: data/full_repos/permissive/135295301/common/ip/oled_pc/sim/oled_init_testbench.v:56: syntax error, unexpected \'@\'\n    repeat (10) @(posedge clk);\n                ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module oled_init_testbench;
  reg clk;
  initial clk = 0;
  always #125 clk = ~clk;

  reg rst_n;
  initial begin
    rst_n = 0;
    repeat (1000) @(posedge clk);
    rst_n = 1;
  end

  wire initialized, oled_vdd, oled_vbat, oled_res, oled_sclk, oled_dc, oled_sdin, heartbeat;

  oled_init oled_init_i (
    .clk ( clk ),
    .rst_n ( rst_n ),
    .initialized ( initialized ),
    .oled_vdd ( oled_vdd ),
    .oled_vbat ( oled_vbat ),
    .oled_res ( oled_res ),
    .oled_sclk ( oled_sclk ),
    .oled_dc ( oled_dc ),
    .oled_sdin ( oled_sdin ),
    .heartbeat ( heartbeat )
  );

  spireceiver spireceiver_i (
    .clk ( clk ),
    .rst_n ( rst_n ),
    .sclk ( oled_sclk ),
    .sdc ( oled_dc ),
    .sdin ( oled_sdin )
  );

  initial begin
    @(posedge initialized);
    repeat (10) @(posedge clk);
    $finish;
  end
endmodule
module oled_init_testbench;

  reg clk;
  initial clk = 0;
  always #125 clk = ~clk;

  reg rst_n;
  initial begin
    rst_n = 0;
    repeat (1000) @(posedge clk);
    rst_n = 1;
  end

  wire initialized, oled_vdd, oled_vbat, oled_res, oled_sclk, oled_dc, oled_sdin, heartbeat;

  oled_init oled_init_i (
    .clk ( clk ),
    .rst_n ( rst_n ),
    .initialized ( initialized ),
    .oled_vdd ( oled_vdd ),
    .oled_vbat ( oled_vbat ),
    .oled_res ( oled_res ),
    .oled_sclk ( oled_sclk ),
    .oled_dc ( oled_dc ),
    .oled_sdin ( oled_sdin ),
    .heartbeat ( heartbeat )
  );

  spireceiver spireceiver_i (
    .clk ( clk ),
    .rst_n ( rst_n ),
    .sclk ( oled_sclk ),
    .sdc ( oled_dc ),
    .sdin ( oled_sdin )
  );

  initial begin
    @(posedge initialized);
    repeat (10) @(posedge clk);
    $finish;
  end
endmodule