data/full_repos/permissive/181665138/verilog/capitolo_ii/Rete_Combinatoria_5.v
data/verilator_xmls/63403ee5-69bf-4453-9d6d-8c01de569beb.xml
module Rete_Combinatoria_5(x3, x2, x1, x0, z);
    input x3, x2, x1, x0;
    output z;
    
    assign z = F(x3, x2, x1, x0);

    function F;
        input x3, x2, x1, x0;

        casex({x3, x2, x1, x0})
            'B00??  : F=0;
            'B1?00  : F=0;
            'B1001  : F=0;
            default : F=1;
        endcase
    endfunction
endmodule
module Rete_Combinatoria_5(x3, x2, x1, x0, z);

    input x3, x2, x1, x0;
    output z;
    
    assign z = F(x3, x2, x1, x0);

    function F;
        input x3, x2, x1, x0;

        casex({x3, x2, x1, x0})
            'B00??  : F=0;
            'B1?00  : F=0;
            'B1001  : F=0;
            default : F=1;
        endcase
    endfunction
endmodule