data/full_repos/permissive/172201645/src/test_streams/insert_main_stream_attrbutes_two_channels.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/172201645/src/test_streams/insert_main_stream_attrbutes_two_channels.v:110: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                                                     : ... In instance insert_main_stream_attrbutes_two_channels\n        count       <= 5\'b00000;\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/172201645/src/test_streams/insert_main_stream_attrbutes_two_channels.v:113: Operator ASSIGNDLY expects 73 bits on the Assign RHS, but Assign RHS\'s CONST \'72\'h0\' generates 72 bits.\n                                                                                                                     : ... In instance insert_main_stream_attrbutes_two_channels\n        out_data    <= 72\'b0;\n                    ^~\n%Error: Exiting due to 2 warning(s)\n'
module insert_main_stream_attrbutes_two_channels(
        input  clk,



        input  active,




        input  [23:0] M_value,
        input  [23:0] N_value,
        input  [11:0] H_visible,
        input  [11:0] V_visible,
        input  [11:0] H_total,
        input  [11:0] V_total,
        input  [11:0] H_sync_width,
        input  [11:0] V_sync_width,
        input  [11:0] H_start,
        input  [11:0] V_start,
        input         H_vsync_active_high,
        input         V_vsync_active_high,
        input         flag_sync_clock,
        input         flag_YCCnRGB,
        input         flag_422n444,
        input         flag_range_reduced,
        input         flag_interlaced_even,
        input         flag_YCC_colour_709,
        input   [1:0] flags_3d_Indicators,
        input   [4:0] bits_per_colour,



        input      [72:0] in_data,
        output reg [72:0] out_data);

    localparam [8:0] SS  = 9'b101011100;
    localparam [8:0] SE  = 9'b111111101;
    localparam [8:0] BS  = 9'b110111100;



    reg [7:0] misc0;
    reg [7:0] misc1;
    
    reg [3:0] count;

    reg [0:0] last_was_bs;
    reg [0:0] armed;

initial begin
        count       <= 5'b00000;
        armed       <= 1'b0;
        last_was_bs <= 1'b0;
        out_data    <= 72'b0;
    end


always @(*) begin
        case(bits_per_colour)
           5'b00110: misc0[7:5] = 3'b000;
           5'b01000: misc0[7:5] = 3'b001;
           5'b01010: misc0[7:5] = 3'b010;
           5'b01100: misc0[7:5] = 3'b011;
           5'b10000: misc0[7:5] = 3'b100;
           default:  misc0[7:5] = 3'b001;
        endcase
    
        misc0[4]          = flag_YCC_colour_709;
        misc0[3]          = flag_range_reduced;
        if(flag_YCCnRGB == 1'b0) begin
            misc0[2:1] = 2'b00;
        end else if(flag_422n444 == 1'b1) begin
            misc0[2:1] = 2'b01;
        end else begin
            misc0[2:1] = 2'b10;
        end 
        misc0[0]          = flag_sync_clock;   

        misc1 = {5'b00000, flags_3d_Indicators, flag_interlaced_even};
    end

always @(posedge clk) begin
    out_data[72] <= in_data[72];
    
    case(count)




        4'b0100: out_data[17:0] <= { SS,                                                    SS }; 
        4'b0101: out_data[17:0] <= { 1'b0, M_value[15:8],                                   1'b0, M_value[23:16] };
        4'b0110: out_data[17:0] <= { 1'b0, 4'b0000, H_total[11:8],                          1'b0, M_value[7:0] };
        4'b0111: out_data[17:0] <= { 1'b0, 4'b0000, V_total[11:8],                          1'b0, H_total[7:0] };
        4'b1000: out_data[17:0] <= { 1'b0, H_vsync_active_high, 3'b000, H_sync_width[11:8], 1'b0, V_total[7:0] };
        4'b1001: out_data[17:0] <= { 1'b0, M_value[23:16],                                  1'b0, H_sync_width[7:0] };
        4'b1010: out_data[17:0] <= { 1'b0, M_value[7:0],                                    1'b0, M_value[15:8] };
        4'b1011: out_data[17:0] <= { 1'b0, H_visible[7:0],                                  1'b0, 4'b0000, H_visible[11:8] };
        4'b1100: out_data[17:0] <= { 1'b0, V_visible[7:0],                                  1'b0, 4'b0000, V_visible[11:8] };
        4'b1101: out_data[17:0] <= { 1'b0, 8'b00000000,                                     1'b0, 8'b00000000 };
        4'b1110: out_data[17:0] <= { in_data[17:9],                                         SE };
        default:  out_data[17:0] <= { in_data[17:9],                                         in_data[8:0]};
    endcase

    case(count)




        4'b0100: out_data[35:18] <= { SS,                                                    SS};
        4'b0101: out_data[35:18] <= { 1'b0, M_value[15:8],                                   1'b0, M_value[23:16]};
        4'b0110: out_data[35:18] <= { 1'b0, 4'b0000, H_start[11:8],                          1'b0, M_value[7:0]};
        4'b0111: out_data[35:18] <= { 1'b0, 4'b0000, V_start[11:8],                          1'b0, H_start[7:0]};
        4'b1000: out_data[35:18] <= { 1'b0, V_vsync_active_high, 3'b000, V_sync_width[11:8], 1'b0, V_start[7:0]};
        4'b1001: out_data[35:18] <= { 1'b0, M_value[23:16],                                  1'b0, V_sync_width[7:0]};
        4'b1010: out_data[35:18] <= { 1'b0, M_value[7:0],                                    1'b0, M_value[15:8]};
        4'b1011: out_data[35:18] <= { 1'b0, N_value[15:8],                                   1'b0, N_value[23:16]}; 
        4'b1100: out_data[35:18] <= { 1'b0, misc0,                                           1'b0, N_value[7:0]};
        4'b1101: out_data[35:18] <= { 1'b0, 8'b00000000,                                     1'b0, misc1}; 
        4'b1110: out_data[35:18] <= { in_data[35:27],                                        SE};
        default:  out_data[35:18] <= { in_data[35:27],                                        in_data[26:18] };
    endcase
                



    if(count == 4'b1110) begin
        count <= 4'b0000;
    end else if(count != 4'b0000) begin
        count <= count + 1;
    end





    if(last_was_bs == 1'b1) begin





        if(in_data[0] == 1'b1) begin
            if(armed == 1'b1) begin
                count <= 4'b0001;
                armed <= 1'b0;
            end
        end else begin


            armed <= active;
        end
    end




    if(in_data[8:0] == BS) begin





        if(in_data[9] == 1'b1) begin
            if(armed == 1'b1) begin
                count <= 4'b0001;
                armed <= 1'b0;
            end
        end else begin


            armed <= 1'b1;
        end 
    end
    



    last_was_bs <= (in_data[17:9] == BS) ? 1'b1 : 1'b0;
end

endmodule
module insert_main_stream_attrbutes_two_channels(
        input  clk,



        input  active,




        input  [23:0] M_value,
        input  [23:0] N_value,
        input  [11:0] H_visible,
        input  [11:0] V_visible,
        input  [11:0] H_total,
        input  [11:0] V_total,
        input  [11:0] H_sync_width,
        input  [11:0] V_sync_width,
        input  [11:0] H_start,
        input  [11:0] V_start,
        input         H_vsync_active_high,
        input         V_vsync_active_high,
        input         flag_sync_clock,
        input         flag_YCCnRGB,
        input         flag_422n444,
        input         flag_range_reduced,
        input         flag_interlaced_even,
        input         flag_YCC_colour_709,
        input   [1:0] flags_3d_Indicators,
        input   [4:0] bits_per_colour,



        input      [72:0] in_data,
        output reg [72:0] out_data);


    localparam [8:0] SS  = 9'b101011100;
    localparam [8:0] SE  = 9'b111111101;
    localparam [8:0] BS  = 9'b110111100;



    reg [7:0] misc0;
    reg [7:0] misc1;
    
    reg [3:0] count;

    reg [0:0] last_was_bs;
    reg [0:0] armed;

initial begin
        count       <= 5'b00000;
        armed       <= 1'b0;
        last_was_bs <= 1'b0;
        out_data    <= 72'b0;
    end


always @(*) begin
        case(bits_per_colour)
           5'b00110: misc0[7:5] = 3'b000;
           5'b01000: misc0[7:5] = 3'b001;
           5'b01010: misc0[7:5] = 3'b010;
           5'b01100: misc0[7:5] = 3'b011;
           5'b10000: misc0[7:5] = 3'b100;
           default:  misc0[7:5] = 3'b001;
        endcase
    
        misc0[4]          = flag_YCC_colour_709;
        misc0[3]          = flag_range_reduced;
        if(flag_YCCnRGB == 1'b0) begin
            misc0[2:1] = 2'b00;
        end else if(flag_422n444 == 1'b1) begin
            misc0[2:1] = 2'b01;
        end else begin
            misc0[2:1] = 2'b10;
        end 
        misc0[0]          = flag_sync_clock;   

        misc1 = {5'b00000, flags_3d_Indicators, flag_interlaced_even};
    end

always @(posedge clk) begin
    out_data[72] <= in_data[72];
    
    case(count)




        4'b0100: out_data[17:0] <= { SS,                                                    SS }; 
        4'b0101: out_data[17:0] <= { 1'b0, M_value[15:8],                                   1'b0, M_value[23:16] };
        4'b0110: out_data[17:0] <= { 1'b0, 4'b0000, H_total[11:8],                          1'b0, M_value[7:0] };
        4'b0111: out_data[17:0] <= { 1'b0, 4'b0000, V_total[11:8],                          1'b0, H_total[7:0] };
        4'b1000: out_data[17:0] <= { 1'b0, H_vsync_active_high, 3'b000, H_sync_width[11:8], 1'b0, V_total[7:0] };
        4'b1001: out_data[17:0] <= { 1'b0, M_value[23:16],                                  1'b0, H_sync_width[7:0] };
        4'b1010: out_data[17:0] <= { 1'b0, M_value[7:0],                                    1'b0, M_value[15:8] };
        4'b1011: out_data[17:0] <= { 1'b0, H_visible[7:0],                                  1'b0, 4'b0000, H_visible[11:8] };
        4'b1100: out_data[17:0] <= { 1'b0, V_visible[7:0],                                  1'b0, 4'b0000, V_visible[11:8] };
        4'b1101: out_data[17:0] <= { 1'b0, 8'b00000000,                                     1'b0, 8'b00000000 };
        4'b1110: out_data[17:0] <= { in_data[17:9],                                         SE };
        default:  out_data[17:0] <= { in_data[17:9],                                         in_data[8:0]};
    endcase

    case(count)




        4'b0100: out_data[35:18] <= { SS,                                                    SS};
        4'b0101: out_data[35:18] <= { 1'b0, M_value[15:8],                                   1'b0, M_value[23:16]};
        4'b0110: out_data[35:18] <= { 1'b0, 4'b0000, H_start[11:8],                          1'b0, M_value[7:0]};
        4'b0111: out_data[35:18] <= { 1'b0, 4'b0000, V_start[11:8],                          1'b0, H_start[7:0]};
        4'b1000: out_data[35:18] <= { 1'b0, V_vsync_active_high, 3'b000, V_sync_width[11:8], 1'b0, V_start[7:0]};
        4'b1001: out_data[35:18] <= { 1'b0, M_value[23:16],                                  1'b0, V_sync_width[7:0]};
        4'b1010: out_data[35:18] <= { 1'b0, M_value[7:0],                                    1'b0, M_value[15:8]};
        4'b1011: out_data[35:18] <= { 1'b0, N_value[15:8],                                   1'b0, N_value[23:16]}; 
        4'b1100: out_data[35:18] <= { 1'b0, misc0,                                           1'b0, N_value[7:0]};
        4'b1101: out_data[35:18] <= { 1'b0, 8'b00000000,                                     1'b0, misc1}; 
        4'b1110: out_data[35:18] <= { in_data[35:27],                                        SE};
        default:  out_data[35:18] <= { in_data[35:27],                                        in_data[26:18] };
    endcase
                



    if(count == 4'b1110) begin
        count <= 4'b0000;
    end else if(count != 4'b0000) begin
        count <= count + 1;
    end





    if(last_was_bs == 1'b1) begin





        if(in_data[0] == 1'b1) begin
            if(armed == 1'b1) begin
                count <= 4'b0001;
                armed <= 1'b0;
            end
        end else begin


            armed <= active;
        end
    end




    if(in_data[8:0] == BS) begin





        if(in_data[9] == 1'b1) begin
            if(armed == 1'b1) begin
                count <= 4'b0001;
                armed <= 1'b0;
            end
        end else begin


            armed <= 1'b1;
        end 
    end
    



    last_was_bs <= (in_data[17:9] == BS) ? 1'b1 : 1'b0;
end

endmodule