data/full_repos/permissive/114943225/vga_vline.v
None: at end of input
1: b'%Error: data/full_repos/permissive/114943225/vga_vline.v:36: Cannot find file containing module: \'vga_colour\'\nvga_colour vgacol0(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114943225,data/full_repos/permissive/114943225/vga_colour\n             data/full_repos/permissive/114943225,data/full_repos/permissive/114943225/vga_colour.v\n             data/full_repos/permissive/114943225,data/full_repos/permissive/114943225/vga_colour.sv\n             vga_colour\n             vga_colour.v\n             vga_colour.sv\n             obj_dir/vga_colour\n             obj_dir/vga_colour.v\n             obj_dir/vga_colour.sv\n%Warning-WIDTH: data/full_repos/permissive/114943225/vga_vline.v:73: Operator AND expects 32 or 10 bits on the RHS, but RHS\'s CONST \'8\'h8\' generates 8 bits.\n                                                                   : ... In instance vga_vline\n     if ((yin & 8\'h08) == 0) begin\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module vga_vline(
	xin, yin,
	x, y0, y1, 
	colour,
	dot_mode,
	writeout_r, writeout_g, writeout_b
);


input [9:0] xin;
input [9:0] yin;
input [9:0] x;
input [9:0] y0;
input [9:0] y1;
input [1:0] dot_mode;
input [4:0] colour;


output reg [7:0] writeout_r;
output reg [7:0] writeout_g;
output reg [7:0] writeout_b;


wire [7:0] col_r_gen;
wire [7:0] col_g_gen;
wire [7:0] col_b_gen;
wire cm;

vga_colour vgacol0(
	.cin(colour),
	.cout_r(col_r_gen),
	.cout_g(col_g_gen),
	.cout_b(col_b_gen),
	.c_mask(cm)
);



always @(*) begin


	if ((yin >= y0) && (yin <= y1) && (x == xin)) begin
		if (cm) begin
			case (dot_mode)
				2'b00: begin
					writeout_r = col_r_gen;
					writeout_g = col_g_gen;
					writeout_b = col_b_gen;
				end
					
				2'b01: begin

					if ((yin & 3) == 0) begin
						writeout_r = col_r_gen;
						writeout_g = col_g_gen;
						writeout_b = col_b_gen;
					end else begin
						writeout_r = 8'bZZZZZZZZ;
						writeout_g = 8'bZZZZZZZZ;
						writeout_b = 8'bZZZZZZZZ;
					end
				end
					
				2'b10: begin

					if ((yin & 8'h08) == 0) begin
						writeout_r = col_r_gen;
						writeout_g = col_g_gen;
						writeout_b = col_b_gen;
					end else begin
						writeout_r = 8'bZZZZZZZZ;
						writeout_g = 8'bZZZZZZZZ;
						writeout_b = 8'bZZZZZZZZ;
					end
				end
			endcase
		end else begin
			writeout_r = 8'bZZZZZZZZ;
			writeout_g = 8'bZZZZZZZZ;
			writeout_b = 8'bZZZZZZZZ;
		end
	end else begin
		writeout_r = 8'bZZZZZZZZ;
		writeout_g = 8'bZZZZZZZZ;
		writeout_b = 8'bZZZZZZZZ;
	end 

end

endmodule
module vga_vline(
	xin, yin,
	x, y0, y1, 
	colour,
	dot_mode,
	writeout_r, writeout_g, writeout_b
);



input [9:0] xin;
input [9:0] yin;
input [9:0] x;
input [9:0] y0;
input [9:0] y1;
input [1:0] dot_mode;
input [4:0] colour;


output reg [7:0] writeout_r;
output reg [7:0] writeout_g;
output reg [7:0] writeout_b;


wire [7:0] col_r_gen;
wire [7:0] col_g_gen;
wire [7:0] col_b_gen;
wire cm;

vga_colour vgacol0(
	.cin(colour),
	.cout_r(col_r_gen),
	.cout_g(col_g_gen),
	.cout_b(col_b_gen),
	.c_mask(cm)
);



always @(*) begin


	if ((yin >= y0) && (yin <= y1) && (x == xin)) begin
		if (cm) begin
			case (dot_mode)
				2'b00: begin
					writeout_r = col_r_gen;
					writeout_g = col_g_gen;
					writeout_b = col_b_gen;
				end
					
				2'b01: begin

					if ((yin & 3) == 0) begin
						writeout_r = col_r_gen;
						writeout_g = col_g_gen;
						writeout_b = col_b_gen;
					end else begin
						writeout_r = 8'bZZZZZZZZ;
						writeout_g = 8'bZZZZZZZZ;
						writeout_b = 8'bZZZZZZZZ;
					end
				end
					
				2'b10: begin

					if ((yin & 8'h08) == 0) begin
						writeout_r = col_r_gen;
						writeout_g = col_g_gen;
						writeout_b = col_b_gen;
					end else begin
						writeout_r = 8'bZZZZZZZZ;
						writeout_g = 8'bZZZZZZZZ;
						writeout_b = 8'bZZZZZZZZ;
					end
				end
			endcase
		end else begin
			writeout_r = 8'bZZZZZZZZ;
			writeout_g = 8'bZZZZZZZZ;
			writeout_b = 8'bZZZZZZZZ;
		end
	end else begin
		writeout_r = 8'bZZZZZZZZ;
		writeout_g = 8'bZZZZZZZZ;
		writeout_b = 8'bZZZZZZZZ;
	end 

end

endmodule