data/full_repos/permissive/135795492/project/async.v
 line:77: before: "="
1: b'%Warning-MULTITOP: data/full_repos/permissive/135795492/project/async.v:74: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                          : ... Top module \'async_transmitter\'\nmodule async_transmitter(\n       ^~~~~~~~~~~~~~~~~\n                                                                          : ... Top module \'async_receiver\'\nmodule async_receiver(\n       ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/135795492/project/async.v:192: Logical Operator WHILE expects 1 bit on the For Test Condition, but For Test Condition\'s SHIFTR generates 32 bits.\n                                                                        : ... In instance async_transmitter.tickgen\nfunction integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction\n                                                      ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/135795492/project/async.v:131: Logical Operator WHILE expects 1 bit on the For Test Condition, but For Test Condition\'s SHIFTR generates 32 bits.\n                                                                        : ... In instance async_receiver\nfunction integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction\n                                                      ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/135795492/project/async.v:134: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance async_receiver\nalways @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1\'d0 : OversamplingCnt + 1\'d1;\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/135795492/project/async.v:135: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'OversamplingCnt\' generates 3 bits.\n                                                                        : ... In instance async_receiver\nwire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);\n                                                     ^~\n%Error: Exiting due to 5 warning(s)\n'
module async_transmitter(
	input clk,
	input TxD_start,
	input [7:0] TxD_data,
	output TxD,
	output TxD_busy
);




parameter ClkFrequency = 24000000;
parameter Baud = 9600;






`ifdef SIMULATION
wire BitTick = 1'b1;
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif

reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;

reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
	if(TxD_ready & TxD_start)
		TxD_shift <= TxD_data;
	else
	if(TxD_state[3] & BitTick)
		TxD_shift <= (TxD_shift >> 1);

	case(TxD_state)
		4'b0000: if(TxD_start) TxD_state <= 4'b0100;
		4'b0100: if(BitTick) TxD_state <= 4'b1000;
		4'b1000: if(BitTick) TxD_state <= 4'b1001;
		4'b1001: if(BitTick) TxD_state <= 4'b1010;
		4'b1010: if(BitTick) TxD_state <= 4'b1011;
		4'b1011: if(BitTick) TxD_state <= 4'b1100;
		4'b1100: if(BitTick) TxD_state <= 4'b1101;
		4'b1101: if(BitTick) TxD_state <= 4'b1110;
		4'b1110: if(BitTick) TxD_state <= 4'b1111;
		4'b1111: if(BitTick) TxD_state <= 4'b0010;
		4'b0010: if(BitTick) TxD_state <= 4'b0011;
		4'b0011: if(BitTick) TxD_state <= 4'b0000;
		default: if(BitTick) TxD_state <= 4'b0000;
	endcase
end

assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]);
endmodule
module async_transmitter(
	input clk,
	input TxD_start,
	input [7:0] TxD_data,
	output TxD,
	output TxD_busy
);





parameter ClkFrequency = 24000000;
parameter Baud = 9600;






`ifdef SIMULATION
wire BitTick = 1'b1;
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif

reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;

reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
	if(TxD_ready & TxD_start)
		TxD_shift <= TxD_data;
	else
	if(TxD_state[3] & BitTick)
		TxD_shift <= (TxD_shift >> 1);

	case(TxD_state)
		4'b0000: if(TxD_start) TxD_state <= 4'b0100;
		4'b0100: if(BitTick) TxD_state <= 4'b1000;
		4'b1000: if(BitTick) TxD_state <= 4'b1001;
		4'b1001: if(BitTick) TxD_state <= 4'b1010;
		4'b1010: if(BitTick) TxD_state <= 4'b1011;
		4'b1011: if(BitTick) TxD_state <= 4'b1100;
		4'b1100: if(BitTick) TxD_state <= 4'b1101;
		4'b1101: if(BitTick) TxD_state <= 4'b1110;
		4'b1110: if(BitTick) TxD_state <= 4'b1111;
		4'b1111: if(BitTick) TxD_state <= 4'b0010;
		4'b0010: if(BitTick) TxD_state <= 4'b0011;
		4'b0011: if(BitTick) TxD_state <= 4'b0000;
		default: if(BitTick) TxD_state <= 4'b0000;
	endcase
end

assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]);
endmodule