data/full_repos/permissive/147690299/lab/15_comb_demux_1bit/tb/testbench.sv
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/15_comb_demux_1bit/tb/testbench.sv:24: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/15_comb_demux_1bit/tb/testbench.sv:26: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/15_comb_demux_1bit/tb/testbench.sv:28: Unsupported: Ignoring delay on this delayed statement.\n            #10\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/15_comb_demux_1bit/tb/testbench.sv:30: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/15_comb_demux_1bit/tb/testbench.sv:32: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/15_comb_demux_1bit/tb/testbench.sv:34: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/15_comb_demux_1bit/tb/testbench.sv:36: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/15_comb_demux_1bit/tb/testbench.sv:38: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Error: data/full_repos/permissive/147690299/lab/15_comb_demux_1bit/tb/testbench.sv:44: Unsupported or unknown PLI call: $monitor\n        $monitor("sel=%b din=%b dout0=%b dout1=%b dout2=%b",\n        ^~~~~~~~\n%Error: data/full_repos/permissive/147690299/lab/15_comb_demux_1bit/tb/testbench.sv:45: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                  sel,   din,   dout0,   dout1,   dout2,   );\n                                                           ^\n%Error: data/full_repos/permissive/147690299/lab/15_comb_demux_1bit/tb/testbench.sv:48: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;   \n        ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

    reg  [2:0] din;
    reg  [1:0] sel;
    wire [2:0] dout0;
    wire [2:0] dout1;
    wire [2:0] dout2;

    lab_top lab_top
    (
        .din   ( din   ),
        .sel   ( sel   ),
        .dout0 ( dout0 ),
        .dout1 ( dout1 ),
        .dout2 ( dout2 ) 
    );

    initial
        begin
            din = 3'b111;
            #5;
            sel = 2'b00;
            #10;
            sel = 2'b01;
            #10
            sel = 2'b10;
            #10;
            sel = 2'b11;
            #10;
            sel = 2'b10;
            #10;
            din = 3'b101;
            #10;
            din = 3'b010;
            #10;
            $finish();
        end


    initial 
        $monitor("sel=%b din=%b dout0=%b dout1=%b dout2=%b",
                  sel,   din,   dout0,   dout1,   dout2,   );

    initial 
        $dumpvars;
endmodule
module testbench;


    reg  [2:0] din;
    reg  [1:0] sel;
    wire [2:0] dout0;
    wire [2:0] dout1;
    wire [2:0] dout2;

    lab_top lab_top
    (
        .din   ( din   ),
        .sel   ( sel   ),
        .dout0 ( dout0 ),
        .dout1 ( dout1 ),
        .dout2 ( dout2 ) 
    );

    initial
        begin
            din = 3'b111;
            #5;
            sel = 2'b00;
            #10;
            sel = 2'b01;
            #10
            sel = 2'b10;
            #10;
            sel = 2'b11;
            #10;
            sel = 2'b10;
            #10;
            din = 3'b101;
            #10;
            din = 3'b010;
            #10;
            $finish();
        end


    initial 
        $monitor("sel=%b din=%b dout0=%b dout1=%b dout2=%b",
                  sel,   din,   dout0,   dout1,   dout2,   );

    initial 
        $dumpvars;
endmodule