data/full_repos/permissive/109846502/testtb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/testtb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  forever #1 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/testtb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10 rst = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/109846502/testtb.v:35: Can\'t resolve module reference: \'test\'\n test uut (\n      ^~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testtb;


	reg clk;
	reg rst;


	wire out;


	test uut (
		.clk(clk), 
		.rst(rst), 
		.out(out)
	);

	initial begin

		clk = 1'b1;
		
		forever #1 clk = ~clk;

	end
	
	initial begin
	
		rst = 1'b1;
		#10 rst = 1'b0;
		end
      
endmodule
module testtb;



	reg clk;
	reg rst;


	wire out;


	test uut (
		.clk(clk), 
		.rst(rst), 
		.out(out)
	);

	initial begin

		clk = 1'b1;
		
		forever #1 clk = ~clk;

	end
	
	initial begin
	
		rst = 1'b1;
		#10 rst = 1'b0;
		end
      
endmodule