data/full_repos/permissive/167274925/DataMemory.v
None: at end of input
data/verilator_xmls/581fb35a-3bbb-49f5-a635-e13cf25b1377.xml
module DataMemory(load,Address, WriteData, Clk, MemWrite, MemRead, ReadData); 
    input [1:0]load;
    input [31:0] Address;
    input [31:0] WriteData;
    input Clk;
    input MemWrite;
    input MemRead;

    output reg [31:0] ReadData;
    reg [31:0]MEM[0:255];
    integer i;
    initial begin
    MEM[0] = 32'h64;
    MEM[1] = 32'hc8;
    MEM[2] = 32'h12c;
    MEM[3] = 32'h190;
    MEM[4] = 32'h1f4;
    MEM[5] = 32'h258;
    MEM[6] = 32'h2bc;
    MEM[7] = 32'h320;
    MEM[8] = 32'h384;
    MEM[9] = 32'h3e8;
    MEM[10] = 32'h44c;
    MEM[11] = 32'h4b0;

    for(i=12;i<256;i=i+1)begin 
       MEM[i]<=0;
       end 
    end 
  always@(posedge Clk)begin 
  if(load==2'd0)begin 
    if(MemWrite)begin
       MEM[Address/4]<=WriteData;
     end 
    end 
   else if(load==2'd1)begin 
    if(MemWrite)begin
     case(Address[1:0])
      2'd0:MEM[(Address)/4][7:0]=WriteData[7:0];
      2'd1:MEM[(Address)/4][15:8]=WriteData[7:0];
      2'd2:MEM[(Address)/4][23:16]=WriteData[7:0];
      2'd3:MEM[(Address)/4][31:24]=WriteData[7:0];
     endcase 
     end 
   end 
   
   else if(load==2'd2)begin 
       if(MemWrite)begin
        case(Address[1:0])
         2'd0:{MEM[Address/4][15:0]}<=WriteData[15:0];
         2'd2:{MEM[Address/4][31:16]}<=WriteData[15:0];
        endcase 
        end 
      end 
   
   
  end 
  always@(*)begin 
  if(load==2'd0)begin 
     if(MemRead)begin 
       ReadData<=MEM[Address/4];
      end 
     end 
   else if(load==2'd1)begin 
         if(MemRead)begin
            case(Address[1:0])
             2'd0:ReadData={{24{MEM[Address/4][7]}},MEM[Address/4][7:0]};
             2'd1:ReadData={{24{MEM[Address/4][15]}},MEM[Address/4][15:8]};
             2'd2:ReadData={{24{MEM[Address/4][23]}},MEM[Address/4][23:16]};
             2'd3:ReadData={{24{MEM[Address/4][31]}},MEM[Address/4][31:24]};
            endcase 
          end 
        end 
        
         else if(load==2'd2)begin 
               if(MemRead)begin
                  case(Address[1:0])
                   2'd0:ReadData<={{16{MEM[Address/4][15]}},MEM[Address/4][15:0]};
                   2'd2:ReadData<={{16{MEM[Address/4][31]}},MEM[Address/4][31:16]};
                  endcase 
                end 
              end  
        
  end 
  
endmodule
module DataMemory(load,Address, WriteData, Clk, MemWrite, MemRead, ReadData);
 
    input [1:0]load;
    input [31:0] Address;
    input [31:0] WriteData;
    input Clk;
    input MemWrite;
    input MemRead;

    output reg [31:0] ReadData;
    reg [31:0]MEM[0:255];
    integer i;
    initial begin
    MEM[0] = 32'h64;
    MEM[1] = 32'hc8;
    MEM[2] = 32'h12c;
    MEM[3] = 32'h190;
    MEM[4] = 32'h1f4;
    MEM[5] = 32'h258;
    MEM[6] = 32'h2bc;
    MEM[7] = 32'h320;
    MEM[8] = 32'h384;
    MEM[9] = 32'h3e8;
    MEM[10] = 32'h44c;
    MEM[11] = 32'h4b0;

    for(i=12;i<256;i=i+1)begin 
       MEM[i]<=0;
       end 
    end 
  always@(posedge Clk)begin 
  if(load==2'd0)begin 
    if(MemWrite)begin
       MEM[Address/4]<=WriteData;
     end 
    end 
   else if(load==2'd1)begin 
    if(MemWrite)begin
     case(Address[1:0])
      2'd0:MEM[(Address)/4][7:0]=WriteData[7:0];
      2'd1:MEM[(Address)/4][15:8]=WriteData[7:0];
      2'd2:MEM[(Address)/4][23:16]=WriteData[7:0];
      2'd3:MEM[(Address)/4][31:24]=WriteData[7:0];
     endcase 
     end 
   end 
   
   else if(load==2'd2)begin 
       if(MemWrite)begin
        case(Address[1:0])
         2'd0:{MEM[Address/4][15:0]}<=WriteData[15:0];
         2'd2:{MEM[Address/4][31:16]}<=WriteData[15:0];
        endcase 
        end 
      end 
   
   
  end 
  always@(*)begin 
  if(load==2'd0)begin 
     if(MemRead)begin 
       ReadData<=MEM[Address/4];
      end 
     end 
   else if(load==2'd1)begin 
         if(MemRead)begin
            case(Address[1:0])
             2'd0:ReadData={{24{MEM[Address/4][7]}},MEM[Address/4][7:0]};
             2'd1:ReadData={{24{MEM[Address/4][15]}},MEM[Address/4][15:8]};
             2'd2:ReadData={{24{MEM[Address/4][23]}},MEM[Address/4][23:16]};
             2'd3:ReadData={{24{MEM[Address/4][31]}},MEM[Address/4][31:24]};
            endcase 
          end 
        end 
        
         else if(load==2'd2)begin 
               if(MemRead)begin
                  case(Address[1:0])
                   2'd0:ReadData<={{16{MEM[Address/4][15]}},MEM[Address/4][15:0]};
                   2'd2:ReadData<={{16{MEM[Address/4][31]}},MEM[Address/4][31:16]};
                  endcase 
                end 
              end  
        
  end 
  
endmodule