data/full_repos/permissive/140976142/sim/rx_sim.v
1: b'%Error: data/full_repos/permissive/140976142/sim/rx_sim.v:13: Cannot find include file: ../rtl/util.vh\n `include "../rtl/util.vh" \n          ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/140976142/sim,data/full_repos/permissive/140976142/../rtl/util.vh\n             data/full_repos/permissive/140976142/sim,data/full_repos/permissive/140976142/../rtl/util.vh.v\n             data/full_repos/permissive/140976142/sim,data/full_repos/permissive/140976142/../rtl/util.vh.sv\n             ../rtl/util.vh\n             ../rtl/util.vh.v\n             ../rtl/util.vh.sv\n             obj_dir/../rtl/util.vh\n             obj_dir/../rtl/util.vh.v\n             obj_dir/../rtl/util.vh.sv\n%Error: data/full_repos/permissive/140976142/sim/rx_sim.v:49: syntax error, unexpected \'@\'\n   @(posedge eth_clkin); #0.001;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/140976142/sim/rx_sim.v:49: Unsupported: Ignoring delay on this delayed statement.\n   @(posedge eth_clkin); #0.001;\n                         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/140976142/sim/rx_sim.v:61: syntax error, unexpected \'@\'\n    @(posedge eth_clkin); #0.001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/140976142/sim/rx_sim.v:61: Unsupported: Ignoring delay on this delayed statement.\n    @(posedge eth_clkin); #0.001;\n                          ^\n%Error: data/full_repos/permissive/140976142/sim/rx_sim.v:65: syntax error, unexpected \'@\'\n   @(posedge eth_clkin); #0.001;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/140976142/sim/rx_sim.v:65: Unsupported: Ignoring delay on this delayed statement.\n   @(posedge eth_clkin); #0.001;\n                         ^\n%Error: data/full_repos/permissive/140976142/sim/rx_sim.v:73: syntax error, unexpected \'@\'\n    @(posedge eth_clkin); #0.001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/140976142/sim/rx_sim.v:73: Unsupported: Ignoring delay on this delayed statement.\n    @(posedge eth_clkin); #0.001;\n                          ^\n%Error: data/full_repos/permissive/140976142/sim/rx_sim.v:85: syntax error, unexpected \'@\'\n    @(posedge eth_clkin); #0.001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/140976142/sim/rx_sim.v:85: Unsupported: Ignoring delay on this delayed statement.\n    @(posedge eth_clkin); #0.001;\n                          ^\n%Error: data/full_repos/permissive/140976142/sim/rx_sim.v:99: syntax error, unexpected \'@\'\n    @(posedge eth_clkin); #0.001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/140976142/sim/rx_sim.v:99: Unsupported: Ignoring delay on this delayed statement.\n    @(posedge eth_clkin); #0.001;\n                          ^\n%Error: data/full_repos/permissive/140976142/sim/rx_sim.v:107: syntax error, unexpected \'@\'\n   @(posedge eth_clkin); #0.001;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/140976142/sim/rx_sim.v:107: Unsupported: Ignoring delay on this delayed statement.\n   @(posedge eth_clkin); #0.001;\n                         ^\n%Error: Exiting due to 8 error(s), 7 warning(s)\n'
module rx_sim
(   
	input            eth_rstn,
	input            eth_clkin,
	output reg       eth_crsdv,
	output reg       eth_rxerr,
	output reg [1:0] eth_rxd
	
);

	`include "../rtl/util.vh"
	
	reg         crc_rst;
	reg         crc_vld;
	reg  [7:0]  crc_dat;
	wire [31:0] crc_code;
	wire [31:0] crc_bswap = bswap32(crc_code);
	crc32 crc32_inst
	(
		.clk (eth_clkin),
		.rst (crc_rst),
		.vld (crc_vld),
		.data(crc_dat),
		.crc (crc_code)
	);
	
	initial begin
		eth_crsdv = 0;
		eth_rxd   = 0;
		eth_rxerr = 0;
	end
	
	reg verbose = 1;
	task set_verbose;
		input verbose_;
		begin
			verbose = verbose_;
		end
	endtask
	
	task send;
		input [8 * 1500 - 1 : 0] data;
		input [10:0]             len;
		
		integer i;
		begin
			@(posedge eth_clkin); #0.001;
			eth_crsdv = 1;
			eth_rxd   = 0;
			eth_rxerr = 0;
			crc_rst   = 1;
			crc_vld   = 0;
			crc_dat   = 0;
			
			
			if(verbose)
				$display("RX SOF");
			for(i = 0; i < (8 * 4 - 1); i = i + 1) begin
				@(posedge eth_clkin); #0.001;
				eth_rxd = 2'b01;
			end
			
			@(posedge eth_clkin); #0.001;
				eth_rxd = 2'b11;
			
			if(verbose)
				$display("RX SOD");
			
			crc_rst = 0;
			for(i = 0; i < 8 * len; i = i + 2) begin
				@(posedge eth_clkin); #0.001;
				eth_rxd = data[i + 1 -: 2];
				if(i % 8 == 0) begin
					crc_vld = 1;
					crc_dat = data[i +: 8];
					if(verbose)
						$display("RX SENT DATA[%d] %02h", i / 8, data[i +: 8]);
				end else
					crc_vld = 0;
			end
			
			while(i < 8 * 64) begin
				@(posedge eth_clkin); #0.001;
				eth_rxd = 2'b0;
				if(i % 8 == 0) begin
					crc_vld = 1;
					crc_dat = 0;
					if(verbose)
						$display("RX SENT PAD");
				end else
					crc_vld = 0;
				i = i + 2;
			end
			
			
			for(i = 0; i < (4 * 8); i = i + 2) begin
				@(posedge eth_clkin); #0.001;
				eth_rxd = crc_bswap[i + 1 -: 2];
				crc_vld = 0;
			end
			
			if(verbose)
				$display("RX SENT CRC32 %08h", crc_code);
			
			@(posedge eth_clkin); #0.001;
			eth_crsdv = 0;
			eth_rxd   = 0;
			
			if(verbose)
				$display("RX EOF");
		end
	endtask
	
endmodule
module rx_sim
(   
	input            eth_rstn,
	input            eth_clkin,
	output reg       eth_crsdv,
	output reg       eth_rxerr,
	output reg [1:0] eth_rxd
	
);


	`include "../rtl/util.vh"
	
	reg         crc_rst;
	reg         crc_vld;
	reg  [7:0]  crc_dat;
	wire [31:0] crc_code;
	wire [31:0] crc_bswap = bswap32(crc_code);
	crc32 crc32_inst
	(
		.clk (eth_clkin),
		.rst (crc_rst),
		.vld (crc_vld),
		.data(crc_dat),
		.crc (crc_code)
	);
	
	initial begin
		eth_crsdv = 0;
		eth_rxd   = 0;
		eth_rxerr = 0;
	end
	
	reg verbose = 1;
	task set_verbose;
		input verbose_;
		begin
			verbose = verbose_;
		end
	endtask
	
	task send;
		input [8 * 1500 - 1 : 0] data;
		input [10:0]             len;
		
		integer i;
		begin
			@(posedge eth_clkin); #0.001;
			eth_crsdv = 1;
			eth_rxd   = 0;
			eth_rxerr = 0;
			crc_rst   = 1;
			crc_vld   = 0;
			crc_dat   = 0;
			
			
			if(verbose)
				$display("RX SOF");
			for(i = 0; i < (8 * 4 - 1); i = i + 1) begin
				@(posedge eth_clkin); #0.001;
				eth_rxd = 2'b01;
			end
			
			@(posedge eth_clkin); #0.001;
				eth_rxd = 2'b11;
			
			if(verbose)
				$display("RX SOD");
			
			crc_rst = 0;
			for(i = 0; i < 8 * len; i = i + 2) begin
				@(posedge eth_clkin); #0.001;
				eth_rxd = data[i + 1 -: 2];
				if(i % 8 == 0) begin
					crc_vld = 1;
					crc_dat = data[i +: 8];
					if(verbose)
						$display("RX SENT DATA[%d] %02h", i / 8, data[i +: 8]);
				end else
					crc_vld = 0;
			end
			
			while(i < 8 * 64) begin
				@(posedge eth_clkin); #0.001;
				eth_rxd = 2'b0;
				if(i % 8 == 0) begin
					crc_vld = 1;
					crc_dat = 0;
					if(verbose)
						$display("RX SENT PAD");
				end else
					crc_vld = 0;
				i = i + 2;
			end
			
			
			for(i = 0; i < (4 * 8); i = i + 2) begin
				@(posedge eth_clkin); #0.001;
				eth_rxd = crc_bswap[i + 1 -: 2];
				crc_vld = 0;
			end
			
			if(verbose)
				$display("RX SENT CRC32 %08h", crc_code);
			
			@(posedge eth_clkin); #0.001;
			eth_crsdv = 0;
			eth_rxd   = 0;
			
			if(verbose)
				$display("RX EOF");
		end
	endtask
	
endmodule