data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/regfile.v
1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/regfile.v:53: Unsized numbers/parameters not allowed in replications.\n                                                                                                                                                    : ... In instance regfile\n        2\'b10:rd1<={{27{0}}, ra3};\n                        ^\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/regfile.v:53: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                                                                    : ... In instance regfile\n        2\'b10:rd1<={{27{0}}, ra3};\n                       ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/regfile.v:53: Unsized numbers/parameters not allowed in replications.\n                                                                                                                                                    : ... In instance regfile\n        2\'b10:rd1<={{27{0}}, ra3};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/regfile.v:58: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ra2\' generates 5 bits.\n                                                                                                                                              : ... In instance regfile\n    assign rd2=ra2?rf[ra2]:0;\n                  ^\n%Error: Exiting due to 4 warning(s)\n'
module regfile(
    input clk,
    input we3,
    input [4:0] ra1,ra2,wa3,ra3,
    input [31:0] wd3,
    output reg [31:0] rd1,
    output [31:0] rd2,
    input [1:0] alusrca,
    input [31:0] pc,
    input [9:0] swt,
    output reg [31:0] t,
    output reg [7:0] disop
    );
    
    reg [31:0] rf[31:0];
    initial
    rf[0]=32'b0;
    
    always@(posedge clk)
    if(we3)
        rf[wa3]<=wd3;
    



    always@(*)
    begin
        case(alusrca)
        2'b00:rd1<=pc;
        2'b01:rd1<=rf[ra1];
        2'b10:rd1<={{27{0}}, ra3};
        default:rd1<=rd1;
        endcase
    end

    assign rd2=ra2?rf[ra2]:0;
    
    always@(*)
    begin
    if(swt[5])
        begin t<=32'b0;disop<=8'b0; end
    else
        begin t<=rf[swt[4:0]];disop<=8'b11111111; end
    end
    
endmodule
module regfile(
    input clk,
    input we3,
    input [4:0] ra1,ra2,wa3,ra3,
    input [31:0] wd3,
    output reg [31:0] rd1,
    output [31:0] rd2,
    input [1:0] alusrca,
    input [31:0] pc,
    input [9:0] swt,
    output reg [31:0] t,
    output reg [7:0] disop
    );

    
    reg [31:0] rf[31:0];
    initial
    rf[0]=32'b0;
    
    always@(posedge clk)
    if(we3)
        rf[wa3]<=wd3;
    



    always@(*)
    begin
        case(alusrca)
        2'b00:rd1<=pc;
        2'b01:rd1<=rf[ra1];
        2'b10:rd1<={{27{0}}, ra3};
        default:rd1<=rd1;
        endcase
    end

    assign rd2=ra2?rf[ra2]:0;
    
    always@(*)
    begin
    if(swt[5])
        begin t<=32'b0;disop<=8'b0; end
    else
        begin t<=rf[swt[4:0]];disop<=8'b11111111; end
    end
    
endmodule