data/full_repos/permissive/175808891/verilog/prv32.v
 line:209: before: "("
1: b"%Error: data/full_repos/permissive/175808891/verilog/prv32.v:280: syntax error, unexpected type\n    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));\n                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/prv32.v:310: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    output reg [31:0] do\n                      ^~\n%Error: data/full_repos/permissive/175808891/verilog/prv32.v:315: syntax error, unexpected '='\n        3'b100  : do = {24'b0,di[7:0]};\n                     ^\n%Error: Cannot continue\n"
module shr(input [31:0] a, output [31:0] r, input [4:0] shamt, input ar);
    
    wire [31:0] r1, r2, r3, r4;
    
    wire fill = ar ? a[31] : 1'b0;
    assign r1 = shamt[0] ? {fill, a[31:1]} : a;
    assign r2 = shamt[1] ? {fill, fill, r1[31:2]} : r1;
    assign r3 = shamt[2] ? {{4{fill}}, r2[31:4]} : r2;
    assign r4 = shamt[3] ? {{8{fill}}, r3[31:8]} : r3;
    assign r = shamt[4] ? {{16{fill}}, r4[31:16]} : r4;
    
endmodule
module shr(input [31:0] a, output [31:0] r, input [4:0] shamt, input ar);

    
    wire [31:0] r1, r2, r3, r4;
    
    wire fill = ar ? a[31] : 1'b0;
    assign r1 = shamt[0] ? {fill, a[31:1]} : a;
    assign r2 = shamt[1] ? {fill, fill, r1[31:2]} : r1;
    assign r3 = shamt[2] ? {{4{fill}}, r2[31:4]} : r2;
    assign r4 = shamt[3] ? {{8{fill}}, r3[31:8]} : r3;
    assign r = shamt[4] ? {{16{fill}}, r4[31:16]} : r4;
    
endmodule