data/full_repos/permissive/136510272/projects/x8086/icarus.v
 line:11: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/x8086/icarus.v:9: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk         = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/x8086/icarus.v:11: Unsupported: Ignoring delay on this delayed statement.\ninitial begin clk = 0; #2000 $finish; end\n                       ^\n%Error: data/full_repos/permissive/136510272/projects/x8086/icarus.v:12: Unsupported or unknown PLI call: $dumpfile\ninitial begin $dumpfile("result.vcd"); $dumpvars(0, main); end\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/x8086/icarus.v:12: Unsupported or unknown PLI call: $dumpvars\ninitial begin $dumpfile("result.vcd"); $dumpvars(0, main); end\n                                       ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;




reg         clk;
always #0.5 clk         = ~clk;

initial begin clk = 0; #2000 $finish; end
initial begin $dumpfile("result.vcd"); $dumpvars(0, main); end




wire [19:0] o_addr;
wire [19:0] o_ip;
wire [19:0] o_mem_addr;
wire [ 7:0] i_data;
wire [ 7:0] o_data;
wire        o_write;
reg  [ 7:0] i_mem_data;
reg  [ 7:0] o_mem_data;
wire        o_mem_write;

reg [1:0] mhz = 2'b00;
always @(negedge clk) mhz <= mhz + 1'b1;








mem_cntrl InternalMemoryController(

    clk,
    o_addr,
    i_data,
    o_data,
    o_write,
    

    i_mem_data,
    o_mem_data,
    o_mem_write,
    o_mem_addr
        
);


reg [7:0] allmemory[1048575:0];
reg [7:0] casl2;

initial begin $readmemh("rom.hex", allmemory, 20'hFC000); end
initial begin $readmemh("ram.hex", allmemory, 20'h00000); end


always @(posedge clk) begin


    if ((o_mem_addr < 20'h02000) || (o_mem_addr >= 20'hFC000) || (o_mem_addr >= 20'hB8000 && o_mem_addr <= 20'hB92C0))
    begin
    
i_mem_data  <= casl2;
casl2  <= allmemory[ o_mem_addr[19:0] ];
        
        if (o_mem_write) begin
        
            allmemory[ o_mem_addr[19:0] ] <= o_mem_data;
        
        end
    
    end else begin
        i_mem_data <= 16'hFFFF;
    end

end




cpu CPUx8086(

    mhz[1],
    1'b0,
    o_addr,
    i_data,
    o_data,
    o_write
    
);







endmodule
module main;





reg         clk;
always #0.5 clk         = ~clk;

initial begin clk = 0; #2000 $finish; end
initial begin $dumpfile("result.vcd"); $dumpvars(0, main); end




wire [19:0] o_addr;
wire [19:0] o_ip;
wire [19:0] o_mem_addr;
wire [ 7:0] i_data;
wire [ 7:0] o_data;
wire        o_write;
reg  [ 7:0] i_mem_data;
reg  [ 7:0] o_mem_data;
wire        o_mem_write;

reg [1:0] mhz = 2'b00;
always @(negedge clk) mhz <= mhz + 1'b1;








mem_cntrl InternalMemoryController(

    clk,
    o_addr,
    i_data,
    o_data,
    o_write,
    

    i_mem_data,
    o_mem_data,
    o_mem_write,
    o_mem_addr
        
);


reg [7:0] allmemory[1048575:0];
reg [7:0] casl2;

initial begin $readmemh("rom.hex", allmemory, 20'hFC000); end
initial begin $readmemh("ram.hex", allmemory, 20'h00000); end


always @(posedge clk) begin


    if ((o_mem_addr < 20'h02000) || (o_mem_addr >= 20'hFC000) || (o_mem_addr >= 20'hB8000 && o_mem_addr <= 20'hB92C0))
    begin
    
i_mem_data  <= casl2;
casl2  <= allmemory[ o_mem_addr[19:0] ];
        
        if (o_mem_write) begin
        
            allmemory[ o_mem_addr[19:0] ] <= o_mem_data;
        
        end
    
    end else begin
        i_mem_data <= 16'hFFFF;
    end

end




cpu CPUx8086(

    mhz[1],
    1'b0,
    o_addr,
    i_data,
    o_data,
    o_write
    
);







endmodule