data/full_repos/permissive/161275071/video/linebuffer.v
1: b"%Error: data/full_repos/permissive/161275071/video/linebuffer.v:92: Cannot find file containing module: 'b1_ram'\n b1_ram UR(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161275071/video,data/full_repos/permissive/161275071/b1_ram\n             data/full_repos/permissive/161275071/video,data/full_repos/permissive/161275071/b1_ram.v\n             data/full_repos/permissive/161275071/video,data/full_repos/permissive/161275071/b1_ram.sv\n             b1_ram\n             b1_ram.v\n             b1_ram.sv\n             obj_dir/b1_ram\n             obj_dir/b1_ram.v\n             obj_dir/b1_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module linebuffer(


	input CLK,
	input CK,
	input WE,
	input LOAD,
	input CLEARING,
	input [3:0] COLOR_INDEX,
	input PCK2,
	input [7:0] SPR_PAL,
	input [7:0] ADDR_LOAD,
	output [11:0] DATA_OUT
);


	reg [7:0] PAL_REG;
	reg [7:0] ADDR_COUNTER;
	reg [7:0] ADDR_LATCH;
	wire [7:0] ADDR_MUX;
	wire [11:0] DATA_IN;
	wire [3:0] COLOR_GATED;
	





	assign COLOR_GATED = COLOR_INDEX | {4{CLEARING}};
	





	assign DATA_IN[3:0] = COLOR_GATED;
	





	always @(posedge PCK2)
		PAL_REG <= SPR_PAL;
	





	assign DATA_IN[11:4] = PAL_REG | {8{CLEARING}};
	





	assign ADDR_MUX = LOAD ? (ADDR_COUNTER + 1'b1) : ADDR_LOAD;






	always @(posedge CK)
		ADDR_COUNTER <= ADDR_MUX;
	





	always @(*)
		ADDR_LATCH <= WE ? ADDR_COUNTER : ADDR_LATCH;

	b1_ram UR(
		ADDR_LATCH,
		CLK,
		DATA_IN,
		~WE,
		DATA_OUT);
		
endmodule
module linebuffer(


	input CLK,
	input CK,
	input WE,
	input LOAD,
	input CLEARING,
	input [3:0] COLOR_INDEX,
	input PCK2,
	input [7:0] SPR_PAL,
	input [7:0] ADDR_LOAD,
	output [11:0] DATA_OUT
);



	reg [7:0] PAL_REG;
	reg [7:0] ADDR_COUNTER;
	reg [7:0] ADDR_LATCH;
	wire [7:0] ADDR_MUX;
	wire [11:0] DATA_IN;
	wire [3:0] COLOR_GATED;
	





	assign COLOR_GATED = COLOR_INDEX | {4{CLEARING}};
	





	assign DATA_IN[3:0] = COLOR_GATED;
	





	always @(posedge PCK2)
		PAL_REG <= SPR_PAL;
	





	assign DATA_IN[11:4] = PAL_REG | {8{CLEARING}};
	





	assign ADDR_MUX = LOAD ? (ADDR_COUNTER + 1'b1) : ADDR_LOAD;






	always @(posedge CK)
		ADDR_COUNTER <= ADDR_MUX;
	





	always @(*)
		ADDR_LATCH <= WE ? ADDR_COUNTER : ADDR_LATCH;

	b1_ram UR(
		ADDR_LATCH,
		CLK,
		DATA_IN,
		~WE,
		DATA_OUT);
		
endmodule