data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v
1: b'%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:3: Cannot find include file: ../../define/global_def.v\n`include "../../define/global_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v.v\n             data/full_repos/permissive/147520230/src/cpu/stage/ID,data/full_repos/permissive/147520230/../../define/global_def.v.sv\n             ../../define/global_def.v\n             ../../define/global_def.v.v\n             ../../define/global_def.v.sv\n             obj_dir/../../define/global_def.v\n             obj_dir/../../define/global_def.v.v\n             obj_dir/../../define/global_def.v.sv\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:4: Cannot find include file: ../../define/op_def.v\n`include "../../define/op_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:5: Cannot find include file: ../../define/funct_def.v\n`include "../../define/funct_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:6: Cannot find include file: ../../define/segpos_def.v\n`include "../../define/segpos_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:12: Define or directive not defined: \'`ADDR_BUS\'\n    input   wire[`ADDR_BUS]     pc,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`ADDR_BUS]     pc,\n                          ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`INST_BUS]     inst,\n    ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:18: Define or directive not defined: \'`INST_BUS\'\n    input   wire[`INST_BUS]     inst,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:22: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg [`ADDR_BUS]     branch_addr,\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:22: Define or directive not defined: \'`ADDR_BUS\'\n    output  reg [`ADDR_BUS]     branch_addr,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:25: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     operand_1,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:26: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     operand_2,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:28: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg [`REG_ADDR_BUS] write_reg_addr\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:28: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output  reg [`REG_ADDR_BUS] write_reg_addr\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:31: Define or directive not defined: \'`INST_OP_BUS\'\n    wire[`INST_OP_BUS]      inst_op     = inst[`SEG_OPCODE];\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`INST_OP_BUS]      inst_op     = inst[`SEG_OPCODE];\n                     ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:31: Define or directive not defined: \'`SEG_OPCODE\'\n    wire[`INST_OP_BUS]      inst_op     = inst[`SEG_OPCODE];\n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:32: Define or directive not defined: \'`INST_ADDR_BUS\'\n    wire[`INST_ADDR_BUS]    inst_addr   = inst[`SEG_ADDR];\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`INST_ADDR_BUS]    inst_addr   = inst[`SEG_ADDR];\n                       ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:32: Define or directive not defined: \'`SEG_ADDR\'\n    wire[`INST_ADDR_BUS]    inst_addr   = inst[`SEG_ADDR];\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:34: Define or directive not defined: \'`ADDR_BUS\'\n    wire[`ADDR_BUS] pc_plus_4   = pc + 4;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`ADDR_BUS] pc_plus_4   = pc + 4;\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:35: Define or directive not defined: \'`ADDR_BUS\'\n    wire[`ADDR_BUS] pc_plus_8   = pc + 8;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`ADDR_BUS] pc_plus_8   = pc + 8;\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:37: Define or directive not defined: \'`ADDR_BUS\'\n    reg [`ADDR_BUS] link_addr;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`ADDR_BUS] link_addr;\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:39: Define or directive not defined: \'`ZERO_WORD\'\n    assign  operand_2   = `ZERO_WORD;\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:41: Define or directive not defined: \'`OP_J\'\n    assign  inst_j  = (inst_op == `OP_J || inst_op == `OP_JAL) ? `TRUE : `FALSE;\n                                  ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:41: Define or directive not defined: \'`OP_JAL\'\n    assign  inst_j  = (inst_op == `OP_J || inst_op == `OP_JAL) ? `TRUE : `FALSE;\n                                                      ^~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:41: Define or directive not defined: \'`TRUE\'\n    assign  inst_j  = (inst_op == `OP_J || inst_op == `OP_JAL) ? `TRUE : `FALSE;\n                                                                 ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:41: Define or directive not defined: \'`FALSE\'\n    assign  inst_j  = (inst_op == `OP_J || inst_op == `OP_JAL) ? `TRUE : `FALSE;\n                                                                         ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:45: Define or directive not defined: \'`RST_ENABLE\'\n        if (rst == `RST_ENABLE) begin\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:46: Define or directive not defined: \'`ZERO_WORD\'\n            link_addr       <= `ZERO_WORD;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:47: Define or directive not defined: \'`FALSE\'\n            branch_flag     <= `FALSE;\n                               ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:48: Define or directive not defined: \'`ZERO_WORD\'\n            branch_addr     <= `ZERO_WORD;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:49: Define or directive not defined: \'`WRITE_DISABLE\'\n            write_reg_en    <= `WRITE_DISABLE;\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:50: Define or directive not defined: \'`ZERO_REG_ADDR\'\n            write_reg_addr  <= `ZERO_REG_ADDR;\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:54: Define or directive not defined: \'`OP_J\'\n                `OP_J:  begin\n                ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:55: Define or directive not defined: \'`ZERO_WORD\'\n                    link_addr       <= `ZERO_WORD;\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:56: Define or directive not defined: \'`TRUE\'\n                    branch_flag     <= `TRUE;\n                                       ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:58: Define or directive not defined: \'`WRITE_DISABLE\'\n                    write_reg_en    <= `WRITE_DISABLE;\n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:59: Define or directive not defined: \'`ZERO_REG_ADDR\'\n                    write_reg_addr  <= `ZERO_REG_ADDR;\n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:62: Define or directive not defined: \'`OP_JAL\'\n                `OP_JAL:    begin\n                ^~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:64: Define or directive not defined: \'`TRUE\'\n                    branch_flag     <= `TRUE;\n                                       ^~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:66: Define or directive not defined: \'`WRITE_ENABLE\'\n                    write_reg_en    <= `WRITE_ENABLE;\n                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:71: Define or directive not defined: \'`ZERO_WORD\'\n                    link_addr       <= `ZERO_WORD;\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:72: Define or directive not defined: \'`FALSE\'\n                    branch_flag     <= `FALSE;\n                                       ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:73: Define or directive not defined: \'`ZERO_WORD\'\n                    branch_addr     <= `ZERO_WORD;\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:74: Define or directive not defined: \'`WRITE_DISABLE\'\n                    write_reg_en    <= `WRITE_DISABLE;\n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/ID/ID_J.v:75: Define or directive not defined: \'`ZERO_REG_ADDR\'\n                    write_reg_addr  <= `ZERO_REG_ADDR;\n                                       ^~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module  ID_J(
    input   wire                rst,


    input   wire[`ADDR_BUS]     pc,
    

    output  wire                inst_j,


    input   wire[`INST_BUS]     inst,


    output  reg                 branch_flag,
    output  reg [`ADDR_BUS]     branch_addr,


    output  wire[`DATA_BUS]     operand_1,
    output  wire[`DATA_BUS]     operand_2,
    output  reg                 write_reg_en,
    output  reg [`REG_ADDR_BUS] write_reg_addr
);

    wire[`INST_OP_BUS]      inst_op     = inst[`SEG_OPCODE];
    wire[`INST_ADDR_BUS]    inst_addr   = inst[`SEG_ADDR];

    wire[`ADDR_BUS] pc_plus_4   = pc + 4;
    wire[`ADDR_BUS] pc_plus_8   = pc + 8;
    
    reg [`ADDR_BUS] link_addr;
    assign  operand_1   = link_addr;
    assign  operand_2   = `ZERO_WORD;

    assign  inst_j  = (inst_op == `OP_J || inst_op == `OP_JAL) ? `TRUE : `FALSE;


    always @ (*)    begin
        if (rst == `RST_ENABLE) begin
            link_addr       <= `ZERO_WORD;
            branch_flag     <= `FALSE;
            branch_addr     <= `ZERO_WORD;
            write_reg_en    <= `WRITE_DISABLE;
            write_reg_addr  <= `ZERO_REG_ADDR;
        end else    begin
            case (inst_op)

                `OP_J:  begin
                    link_addr       <= `ZERO_WORD;
                    branch_flag     <= `TRUE;
                    branch_addr     <= {pc_plus_4[31:28], inst_addr, 2'b00};
                    write_reg_en    <= `WRITE_DISABLE;
                    write_reg_addr  <= `ZERO_REG_ADDR;
                end

                `OP_JAL:    begin
                    link_addr       <= pc_plus_8;
                    branch_flag     <= `TRUE;
                    branch_addr     <= {pc_plus_4[31:28], inst_addr, 2'b00};
                    write_reg_en    <= `WRITE_ENABLE;
                    write_reg_addr  <= 5'b11111;
                end

                default:    begin
                    link_addr       <= `ZERO_WORD;
                    branch_flag     <= `FALSE;
                    branch_addr     <= `ZERO_WORD;
                    write_reg_en    <= `WRITE_DISABLE;
                    write_reg_addr  <= `ZERO_REG_ADDR;
                end

            endcase
        end
    end

endmodule
module  ID_J(
    input   wire                rst,


    input   wire[`ADDR_BUS]     pc,
    

    output  wire                inst_j,


    input   wire[`INST_BUS]     inst,


    output  reg                 branch_flag,
    output  reg [`ADDR_BUS]     branch_addr,


    output  wire[`DATA_BUS]     operand_1,
    output  wire[`DATA_BUS]     operand_2,
    output  reg                 write_reg_en,
    output  reg [`REG_ADDR_BUS] write_reg_addr
);


    wire[`INST_OP_BUS]      inst_op     = inst[`SEG_OPCODE];
    wire[`INST_ADDR_BUS]    inst_addr   = inst[`SEG_ADDR];

    wire[`ADDR_BUS] pc_plus_4   = pc + 4;
    wire[`ADDR_BUS] pc_plus_8   = pc + 8;
    
    reg [`ADDR_BUS] link_addr;
    assign  operand_1   = link_addr;
    assign  operand_2   = `ZERO_WORD;

    assign  inst_j  = (inst_op == `OP_J || inst_op == `OP_JAL) ? `TRUE : `FALSE;


    always @ (*)    begin
        if (rst == `RST_ENABLE) begin
            link_addr       <= `ZERO_WORD;
            branch_flag     <= `FALSE;
            branch_addr     <= `ZERO_WORD;
            write_reg_en    <= `WRITE_DISABLE;
            write_reg_addr  <= `ZERO_REG_ADDR;
        end else    begin
            case (inst_op)

                `OP_J:  begin
                    link_addr       <= `ZERO_WORD;
                    branch_flag     <= `TRUE;
                    branch_addr     <= {pc_plus_4[31:28], inst_addr, 2'b00};
                    write_reg_en    <= `WRITE_DISABLE;
                    write_reg_addr  <= `ZERO_REG_ADDR;
                end

                `OP_JAL:    begin
                    link_addr       <= pc_plus_8;
                    branch_flag     <= `TRUE;
                    branch_addr     <= {pc_plus_4[31:28], inst_addr, 2'b00};
                    write_reg_en    <= `WRITE_ENABLE;
                    write_reg_addr  <= 5'b11111;
                end

                default:    begin
                    link_addr       <= `ZERO_WORD;
                    branch_flag     <= `FALSE;
                    branch_addr     <= `ZERO_WORD;
                    write_reg_en    <= `WRITE_DISABLE;
                    write_reg_addr  <= `ZERO_REG_ADDR;
                end

            endcase
        end
    end

endmodule