data/full_repos/permissive/174369527/colorLight/button.v
data/verilator_xmls/2f6f95d3-3560-4bc3-ab1b-eccf7024939a.xml
module button (
	input wire i_clk,
	input wire i_btn,
	output wire o_led
	);

	reg [24:0] r_counter;
	initial
		r_counter <= 0;

	assign o_led = !r_counter[24];

	always @(posedge i_clk)
	begin
		if (i_btn == 1'b0)
			r_counter <= 0;
		else
			r_counter <= r_counter + 1;
	end
endmodule
module button (
	input wire i_clk,
	input wire i_btn,
	output wire o_led
	);


	reg [24:0] r_counter;
	initial
		r_counter <= 0;

	assign o_led = !r_counter[24];

	always @(posedge i_clk)
	begin
		if (i_btn == 1'b0)
			r_counter <= 0;
		else
			r_counter <= r_counter + 1;
	end
endmodule