data/full_repos/permissive/161517951/registrador.v
 line:10: before: "R1"
1: b'%Error: data/full_repos/permissive/161517951/registrador.v:10: syntax error, unexpected IDENTIFIER\n   resetar R1 (valReg,valReg);\n           ^~\n%Error: data/full_repos/permissive/161517951/registrador.v:13: syntax error, unexpected IDENTIFIER\n   setar S1 (valor,valReg);\n         ^~\n%Error: data/full_repos/permissive/161517951/registrador.v:19: syntax error, unexpected IDENTIFIER\n   divisao2 D1 (valReg, valReg);\n            ^~\n%Error: Exiting due to 3 error(s)\n'
module registrador(clock, valor, funcao, valReg);
input wire clock;
input wire [3:0]funcao;
input wire [3:0]valor;
output reg [3:0]valReg;

always @(posedge clock)begin
	case(funcao)
		4'b0000:begin
			resetar R1 (valReg,valReg);
		end
		4'b0001:begin
			setar S1 (valor,valReg);
		end
		4'b0010:begin
			
		end
		4'b0011:begin
			divisao2 D1 (valReg, valReg);
		end
	endcase
end

endmodule
module registrador(clock, valor, funcao, valReg);

input wire clock;
input wire [3:0]funcao;
input wire [3:0]valor;
output reg [3:0]valReg;

always @(posedge clock)begin
	case(funcao)
		4'b0000:begin
			resetar R1 (valReg,valReg);
		end
		4'b0001:begin
			setar S1 (valor,valReg);
		end
		4'b0010:begin
			
		end
		4'b0011:begin
			divisao2 D1 (valReg, valReg);
		end
	endcase
end

endmodule