data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/RamSel.v
 line:16: before: "ADDR_WIDTH"
data/verilator_xmls/9e64578f-50a8-4764-b688-ef5efbf1f549.xml
module RamSel #(
        ADDR_WIDTH = 10,
        RAM_SIZE = 1024
    )(
        input clk,
        input rst,
        input str,
        input [3:0] sel,
        input [ADDR_WIDTH - 1:0] addr,
        input [31:0] data,
        output [31:0] result
    );

    reg [31:0] memory[RAM_SIZE - 1:0];

    integer i;
    initial begin
        for(i = 0; i < RAM_SIZE; i = i + 1) begin
            memory[i] = 0;
        end
    end
  

    always @(posedge clk) begin
        if (str) begin
            if (sel[0] == 1'b1) begin
                memory[addr][7:0] <= data[7:0];
            end
            if (sel[1] == 1'b1) begin
                memory[addr][15:8] <= data[15:8];
            end
            if (sel[2] == 1'b1) begin
                memory[addr][23:16] <= data[23:16];
            end
            if (sel[3] == 1'b1) begin
                memory[addr][31:24] <= data[31:24];
            end
        end

        if (rst) begin
            for(i = 0; i < RAM_SIZE; i = i + 1) begin
                memory[i] = 0;
            end
        end
    end

    assign result = memory[addr];
    
endmodule
module RamSel #(
        ADDR_WIDTH = 10,
        RAM_SIZE = 1024
    )(
        input clk,
        input rst,
        input str,
        input [3:0] sel,
        input [ADDR_WIDTH - 1:0] addr,
        input [31:0] data,
        output [31:0] result
    );


    reg [31:0] memory[RAM_SIZE - 1:0];

    integer i;
    initial begin
        for(i = 0; i < RAM_SIZE; i = i + 1) begin
            memory[i] = 0;
        end
    end
  

    always @(posedge clk) begin
        if (str) begin
            if (sel[0] == 1'b1) begin
                memory[addr][7:0] <= data[7:0];
            end
            if (sel[1] == 1'b1) begin
                memory[addr][15:8] <= data[15:8];
            end
            if (sel[2] == 1'b1) begin
                memory[addr][23:16] <= data[23:16];
            end
            if (sel[3] == 1'b1) begin
                memory[addr][31:24] <= data[31:24];
            end
        end

        if (rst) begin
            for(i = 0; i < RAM_SIZE; i = i + 1) begin
                memory[i] = 0;
            end
        end
    end

    assign result = memory[addr];
    
endmodule