data/full_repos/permissive/143278/ivltests/edge.v
 line:99: before: "evt"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/edge.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg passed;
  reg pevt;
  reg evt;
  reg pedge;
  reg nedge;

  initial begin
    passed = 1'b1;

    #1;
    {pedge, nedge} = 2'b01;
    evt = 1'b0;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b10;
    evt = 1'bx;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b10;
    evt = 1'b1;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b01;
    evt = 1'bx;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b00;
    evt = 1'bz;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b00;
    evt = 1'bx;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b00;
    evt = 1'bz;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b01;
    evt = 1'b0;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b10;
    evt = 1'bz;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b10;
    evt = 1'b1;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b01;
    evt = 1'bz;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b10;
    evt = 1'b1;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b01;
    evt = 1'b0;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b10;
    evt = 1'b1;

    #1;

    if (passed) $display("PASSED");
  end

  always @(posedge evt) begin
    if (!pedge) begin
      $display("Error: posedge detected for %b -> %b", pevt, evt);
      passed = 1'b0;
    end
  end

  always @(negedge evt) begin
    if (!nedge) begin
      $display("Error: negedge detected for %b -> %b", pevt, evt);
      passed = 1'b0;
    end
  end

  always @(edge evt) begin
    if (!nedge && !pedge) begin
      $display("Error: edge detected for %b -> %b", pevt, evt);
      passed = 1'b0;
    end
  end

  always @(evt)
    $display("Checking the %b -> %b event", pevt, evt);
endmodule
module top;

  reg passed;
  reg pevt;
  reg evt;
  reg pedge;
  reg nedge;

  initial begin
    passed = 1'b1;

    #1;
    {pedge, nedge} = 2'b01;
    evt = 1'b0;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b10;
    evt = 1'bx;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b10;
    evt = 1'b1;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b01;
    evt = 1'bx;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b00;
    evt = 1'bz;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b00;
    evt = 1'bx;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b00;
    evt = 1'bz;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b01;
    evt = 1'b0;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b10;
    evt = 1'bz;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b10;
    evt = 1'b1;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b01;
    evt = 1'bz;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b10;
    evt = 1'b1;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b01;
    evt = 1'b0;

    #1;
    pevt = evt;
    {pedge, nedge} = 2'b10;
    evt = 1'b1;

    #1;

    if (passed) $display("PASSED");
  end

  always @(posedge evt) begin
    if (!pedge) begin
      $display("Error: posedge detected for %b -> %b", pevt, evt);
      passed = 1'b0;
    end
  end

  always @(negedge evt) begin
    if (!nedge) begin
      $display("Error: negedge detected for %b -> %b", pevt, evt);
      passed = 1'b0;
    end
  end

  always @(edge evt) begin
    if (!nedge && !pedge) begin
      $display("Error: edge detected for %b -> %b", pevt, evt);
      passed = 1'b0;
    end
  end

  always @(evt)
    $display("Checking the %b -> %b event", pevt, evt);
endmodule