data/full_repos/permissive/185301529/mux4.sv
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data/verilator_xmls/29617937-748e-424b-a48d-523e8a2a0b30.xml
module mux4 #(parameter width = 32)
(
	input logic [1:0] sel,
	input [width-1:0] a, b, c, d, 
	output logic [width-1:0] f
);
	always_comb
	begin
		if (sel == 0)
			f = a;
		else if (sel == 1)
			f = b;
		else if (sel == 2)
			f = c;
		else 
			f = d;		
	end
endmodule
module mux4 #(parameter width = 32)
(
	input logic [1:0] sel,
	input [width-1:0] a, b, c, d, 
	output logic [width-1:0] f
);

	always_comb
	begin
		if (sel == 0)
			f = a;
		else if (sel == 1)
			f = b;
		else if (sel == 2)
			f = c;
		else 
			f = d;		
	end
endmodule