data/full_repos/permissive/147645128/source/mm_con/mm_con.v
data/verilator_xmls/1b2b1b1b-ffaa-45c8-9670-ecc50287b097.xml
module mm_con(

clk_sys_i,
rst_n_i,


m_addr_i,
m_wdata_i,
m_rdata_o,
m_we_i,


s_addr_o,
s_wdata_o,
s_rdata0_i,
s_rdata1_i,
s_rdata2_i,
s_rdata3_i,
s_rdata4_i,
s_we_o
);


parameter MM_ADDR_WIDTH = 8;
parameter MM_DATA_WIDTH = 16;

parameter REG_ADDR_PID = 'h00;
parameter REG_ADDR_TST = 'h02;

parameter REG_ADDR_INT_PND = 'h04;
parameter REG_ADDR_INT_CLR = 'h06;
parameter REG_ADDR_INT_MSK = 'h08;

parameter REG_ADDR_SWDT_CTRL = 'h0A;
parameter REG_ADDR_SWDT_VAL = 'h0C;

parameter REG_ADDR_LED_CTRL = 'h0E;

parameter REG_ADDR_PWR_CTRL = 'h10;
parameter REG_ADDR_PSU_STA  = 'h12;
parameter REG_ADDR_PWR_STA  = 'h14;
parameter REG_ADDR_PWR_ERR  = 'h16;




input clk_sys_i, rst_n_i;



input[MM_ADDR_WIDTH-1:0] m_addr_i;
input[MM_DATA_WIDTH-1:0] m_wdata_i;
output[MM_DATA_WIDTH-1:0] m_rdata_o;

input m_we_i;



output[MM_ADDR_WIDTH-1:0] s_addr_o;
output[MM_DATA_WIDTH-1:0] s_wdata_o;
input[MM_DATA_WIDTH-1:0] s_rdata0_i, s_rdata1_i, s_rdata2_i, s_rdata3_i, s_rdata4_i;

output s_we_o;

wire[MM_ADDR_WIDTH-1:0] m_addr_i;
wire[MM_DATA_WIDTH-1:0] m_wdata_i;
reg[MM_DATA_WIDTH-1:0] m_rdata_o;
wire m_we_i;
wire[MM_ADDR_WIDTH-1:0] s_addr_o;
wire[MM_DATA_WIDTH-1:0] s_wdata_o;
wire[MM_DATA_WIDTH-1:0] s_rdata0_i, s_rdata1_i, s_rdata2_i, s_rdata3_i, s_rdata4_i;
wire s_we_o;

reg[MM_DATA_WIDTH-1:0] rdata_buff;



always @(m_addr_i, s_rdata0_i, s_rdata1_i, s_rdata2_i, s_rdata3_i, s_rdata4_i, rst_n_i)
begin
	if(!rst_n_i) begin
		rdata_buff <= 0;
	end
	else begin
		case(m_addr_i)		

			REG_ADDR_PID:
				rdata_buff <= s_rdata0_i;
			REG_ADDR_TST:
				rdata_buff <= s_rdata0_i;
				

			REG_ADDR_INT_PND:
				rdata_buff <= s_rdata1_i;
			REG_ADDR_INT_CLR:
				rdata_buff <= s_rdata1_i;
			REG_ADDR_INT_MSK:
				rdata_buff <= s_rdata1_i;
				

			REG_ADDR_SWDT_CTRL:
				rdata_buff <= s_rdata2_i;
			REG_ADDR_SWDT_VAL:
				rdata_buff <= s_rdata2_i;
				

			REG_ADDR_LED_CTRL:
				rdata_buff <= s_rdata3_i;
				

			REG_ADDR_PWR_CTRL:
				rdata_buff <= s_rdata4_i;
			REG_ADDR_PSU_STA:
				rdata_buff <= s_rdata4_i;
			REG_ADDR_PWR_STA:
				rdata_buff <= s_rdata4_i;
			REG_ADDR_PWR_ERR:
				rdata_buff <= s_rdata4_i;
			
			default:
				rdata_buff <= 0;
		endcase
	end
end



always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		m_rdata_o <= 0;
	end
	else begin
		m_rdata_o <= rdata_buff;
	end
end


assign s_addr_o[MM_ADDR_WIDTH-1:0] = m_addr_i[MM_ADDR_WIDTH-1:0];
assign s_wdata_o[MM_DATA_WIDTH-1:0] = m_wdata_i[MM_DATA_WIDTH-1:0];
assign s_we_o = m_we_i;

endmodule
module mm_con(

clk_sys_i,
rst_n_i,


m_addr_i,
m_wdata_i,
m_rdata_o,
m_we_i,


s_addr_o,
s_wdata_o,
s_rdata0_i,
s_rdata1_i,
s_rdata2_i,
s_rdata3_i,
s_rdata4_i,
s_we_o
);



parameter MM_ADDR_WIDTH = 8;
parameter MM_DATA_WIDTH = 16;

parameter REG_ADDR_PID = 'h00;
parameter REG_ADDR_TST = 'h02;

parameter REG_ADDR_INT_PND = 'h04;
parameter REG_ADDR_INT_CLR = 'h06;
parameter REG_ADDR_INT_MSK = 'h08;

parameter REG_ADDR_SWDT_CTRL = 'h0A;
parameter REG_ADDR_SWDT_VAL = 'h0C;

parameter REG_ADDR_LED_CTRL = 'h0E;

parameter REG_ADDR_PWR_CTRL = 'h10;
parameter REG_ADDR_PSU_STA  = 'h12;
parameter REG_ADDR_PWR_STA  = 'h14;
parameter REG_ADDR_PWR_ERR  = 'h16;




input clk_sys_i, rst_n_i;



input[MM_ADDR_WIDTH-1:0] m_addr_i;
input[MM_DATA_WIDTH-1:0] m_wdata_i;
output[MM_DATA_WIDTH-1:0] m_rdata_o;

input m_we_i;



output[MM_ADDR_WIDTH-1:0] s_addr_o;
output[MM_DATA_WIDTH-1:0] s_wdata_o;
input[MM_DATA_WIDTH-1:0] s_rdata0_i, s_rdata1_i, s_rdata2_i, s_rdata3_i, s_rdata4_i;

output s_we_o;

wire[MM_ADDR_WIDTH-1:0] m_addr_i;
wire[MM_DATA_WIDTH-1:0] m_wdata_i;
reg[MM_DATA_WIDTH-1:0] m_rdata_o;
wire m_we_i;
wire[MM_ADDR_WIDTH-1:0] s_addr_o;
wire[MM_DATA_WIDTH-1:0] s_wdata_o;
wire[MM_DATA_WIDTH-1:0] s_rdata0_i, s_rdata1_i, s_rdata2_i, s_rdata3_i, s_rdata4_i;
wire s_we_o;

reg[MM_DATA_WIDTH-1:0] rdata_buff;



always @(m_addr_i, s_rdata0_i, s_rdata1_i, s_rdata2_i, s_rdata3_i, s_rdata4_i, rst_n_i)
begin
	if(!rst_n_i) begin
		rdata_buff <= 0;
	end
	else begin
		case(m_addr_i)		

			REG_ADDR_PID:
				rdata_buff <= s_rdata0_i;
			REG_ADDR_TST:
				rdata_buff <= s_rdata0_i;
				

			REG_ADDR_INT_PND:
				rdata_buff <= s_rdata1_i;
			REG_ADDR_INT_CLR:
				rdata_buff <= s_rdata1_i;
			REG_ADDR_INT_MSK:
				rdata_buff <= s_rdata1_i;
				

			REG_ADDR_SWDT_CTRL:
				rdata_buff <= s_rdata2_i;
			REG_ADDR_SWDT_VAL:
				rdata_buff <= s_rdata2_i;
				

			REG_ADDR_LED_CTRL:
				rdata_buff <= s_rdata3_i;
				

			REG_ADDR_PWR_CTRL:
				rdata_buff <= s_rdata4_i;
			REG_ADDR_PSU_STA:
				rdata_buff <= s_rdata4_i;
			REG_ADDR_PWR_STA:
				rdata_buff <= s_rdata4_i;
			REG_ADDR_PWR_ERR:
				rdata_buff <= s_rdata4_i;
			
			default:
				rdata_buff <= 0;
		endcase
	end
end



always @(posedge clk_sys_i, negedge rst_n_i)
begin
	if(!rst_n_i) begin
		m_rdata_o <= 0;
	end
	else begin
		m_rdata_o <= rdata_buff;
	end
end


assign s_addr_o[MM_ADDR_WIDTH-1:0] = m_addr_i[MM_ADDR_WIDTH-1:0];
assign s_wdata_o[MM_DATA_WIDTH-1:0] = m_wdata_i[MM_DATA_WIDTH-1:0];
assign s_we_o = m_we_i;

endmodule