data/full_repos/permissive/128100618/SV/FP_operations_design.v
 line:6: before: "("
1: b'%Warning-MULTITOP: data/full_repos/permissive/128100618/SV/FP_operations_design.v:280: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                     : ... Top module \'DE2_Top\'\nmodule DE2_Top (\n       ^~~~~~~\n                                                                                     : ... Top module \'fpneg\'\nmodule fpneg(fout, f1) ;\n       ^~~~~\n                                                                                     : ... Top module \'int2fp\'\nmodule int2fp(fp_out, int_in, scale_in) ;\n       ^~~~~~\n                                                                                     : ... Top module \'fp2int\'\nmodule fp2int(int_out, fp_in, scale_in) ;\n       ^~~~~~\n                                                                                     : ... Top module \'fpinv\'\nmodule fpinv (fout, f1);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FP_operations_design.v:263: Input port connection \'num\' expects 4 bits on the pin connection, but pin connection\'s SEL generates 1 bits.\n                                                                                  : ... In instance DE2_Top\n HexDigit d2(HEX2, disp[8]);\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FP_operations_design.v:619: Operator SHIFTR expects 10 bits on the LHS, but LHS\'s VARREF \'m_in\' generates 9 bits.\n                                                                                  : ... In instance fp2int\n assign abs_int = (e_in>8\'h80)? (m_in >> (8\'h89 - e_in)) : 10\'d0 ;\n                                      ^~\n%Error: Exiting due to 3 warning(s)\n'
module fpneg(fout, f1) ;
	input [17:0] f1 ;
	output [17:0] fout ;
	assign fout = {~f1[17], f1[16:0]} ;
endmodule
module fpneg(fout, f1) ;

	input [17:0] f1 ;
	output [17:0] fout ;
	assign fout = {~f1[17], f1[16:0]} ;
endmodule