data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot2_alm.sv
 line:32: before: "DATA_WIDTH"
1: b'%Error: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot2_alm.sv:92: Cannot find file containing module: \'mBit_nMult\'\n   mBit_nMult # (\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl,data/full_repos/permissive/150152921/mBit_nMult\n             data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl,data/full_repos/permissive/150152921/mBit_nMult.v\n             data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl,data/full_repos/permissive/150152921/mBit_nMult.sv\n             mBit_nMult\n             mBit_nMult.v\n             mBit_nMult.sv\n             obj_dir/mBit_nMult\n             obj_dir/mBit_nMult.v\n             obj_dir/mBit_nMult.sv\n%Error: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot2_alm.sv:104: Cannot find file containing module: \'mBit_nMult\'\n   mBit_nMult # (\n   ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot2_alm.sv:123: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                                                 : ... In instance dot2_alm\n   assign a_res_e = $signed(a_res);\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot2_alm.sv:124: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                                                 : ... In instance dot2_alm\n   assign b_res_e = $signed(b_res);\n                  ^\n%Error: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot2_alm.sv:126: Cannot find file containing module: \'nBit_mLength_shiftRegister\'\n   nBit_mLength_shiftRegister # (DATA_WIDTH*2 + 1, TREE_DELAY) dotRes (clk, rst, ena, a_res_e + b_res_e, res_out);\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module dot2_alm # (
		   DATA_WIDTH = 8,
		   MULT_LATENCY= 4,
		   TREE_DELAY = 1
		   ) (
		      clk,
		      rst,
		      ena,

		      a1_in,
		      a2_in,

		      b1_in,
		      b2_in,

		      res_out
		      );



   input   wire                        clk;
   input   wire                        rst;
   input   wire                        ena;

   input   wire [DATA_WIDTH-1:0]       a1_in;
   input   wire [DATA_WIDTH-1:0]       a2_in;

   input   wire [DATA_WIDTH-1:0]       b1_in;
   input   wire [DATA_WIDTH-1:0]       b2_in;

   output  wire [DATA_WIDTH*2-1+1:0]   res_out;




   wire [DATA_WIDTH-1:0] 	       a1_in_q;
   wire [DATA_WIDTH-1:0] 	       a2_in_q;
   wire [DATA_WIDTH-1:0] 	       b1_in_q;
   wire [DATA_WIDTH-1:0] 	       b2_in_q;




`ifdef TERNARY

   wire [DATA_WIDTH-1:0] 	       a_res;


   wire [DATA_WIDTH-1:0] 	       b_res;
   
   nBit_mLength_shiftRegister # (DATA_WIDTH, MULT_LATENCY) (clk, rst, ena, $signed(b1_in), a_res); 
   nBit_mLength_shiftRegister # (DATA_WIDTH, MULT_LATENCY) (clk, rst, ena, $signed(b2_in), b_res); 
`else
   

   wire [DATA_WIDTH*2-1:0] 	       a_res;


   wire [DATA_WIDTH*2-1:0] 	       b_res;
   

   mBit_nMult # (
		 .DATA_WIDTH  (DATA_WIDTH),
		 .LATENCY     (MULT_LATENCY)
		 ) DOT1_0 (
			   .clk    (clk),
			   .rst    (rst), 
			   .ena    (ena), 
			   .a      (a1_in), 
			   .b      (b1_in), 
			   .m      (a_res)
			   );

   mBit_nMult # (
		 .DATA_WIDTH      (DATA_WIDTH),
		 .LATENCY         (MULT_LATENCY)
		 ) DOT1_1 (
			   .clk    (clk),
			   .rst    (rst), 
			   .ena    (ena), 
			   .a      (a2_in), 
			   .b      (b2_in), 
			   .m      (b_res)
			   );
`endif




   wire [DATA_WIDTH*2-1+1:0] 	       a_res_e;
   wire [DATA_WIDTH*2-1+1:0] 	       b_res_e;

   assign a_res_e = $signed(a_res);
   assign b_res_e = $signed(b_res);

   nBit_mLength_shiftRegister # (DATA_WIDTH*2 + 1, TREE_DELAY) dotRes (clk, rst, ena, a_res_e + b_res_e, res_out);

endmodule
module dot2_alm # (
		   DATA_WIDTH = 8,
		   MULT_LATENCY= 4,
		   TREE_DELAY = 1
		   ) (
		      clk,
		      rst,
		      ena,

		      a1_in,
		      a2_in,

		      b1_in,
		      b2_in,

		      res_out
		      );




   input   wire                        clk;
   input   wire                        rst;
   input   wire                        ena;

   input   wire [DATA_WIDTH-1:0]       a1_in;
   input   wire [DATA_WIDTH-1:0]       a2_in;

   input   wire [DATA_WIDTH-1:0]       b1_in;
   input   wire [DATA_WIDTH-1:0]       b2_in;

   output  wire [DATA_WIDTH*2-1+1:0]   res_out;




   wire [DATA_WIDTH-1:0] 	       a1_in_q;
   wire [DATA_WIDTH-1:0] 	       a2_in_q;
   wire [DATA_WIDTH-1:0] 	       b1_in_q;
   wire [DATA_WIDTH-1:0] 	       b2_in_q;




`ifdef TERNARY

   wire [DATA_WIDTH-1:0] 	       a_res;


   wire [DATA_WIDTH-1:0] 	       b_res;
   
   nBit_mLength_shiftRegister # (DATA_WIDTH, MULT_LATENCY) (clk, rst, ena, $signed(b1_in), a_res); 
   nBit_mLength_shiftRegister # (DATA_WIDTH, MULT_LATENCY) (clk, rst, ena, $signed(b2_in), b_res); 
`else
   

   wire [DATA_WIDTH*2-1:0] 	       a_res;


   wire [DATA_WIDTH*2-1:0] 	       b_res;
   

   mBit_nMult # (
		 .DATA_WIDTH  (DATA_WIDTH),
		 .LATENCY     (MULT_LATENCY)
		 ) DOT1_0 (
			   .clk    (clk),
			   .rst    (rst), 
			   .ena    (ena), 
			   .a      (a1_in), 
			   .b      (b1_in), 
			   .m      (a_res)
			   );

   mBit_nMult # (
		 .DATA_WIDTH      (DATA_WIDTH),
		 .LATENCY         (MULT_LATENCY)
		 ) DOT1_1 (
			   .clk    (clk),
			   .rst    (rst), 
			   .ena    (ena), 
			   .a      (a2_in), 
			   .b      (b2_in), 
			   .m      (b_res)
			   );
`endif




   wire [DATA_WIDTH*2-1+1:0] 	       a_res_e;
   wire [DATA_WIDTH*2-1+1:0] 	       b_res_e;

   assign a_res_e = $signed(a_res);
   assign b_res_e = $signed(b_res);

   nBit_mLength_shiftRegister # (DATA_WIDTH*2 + 1, TREE_DELAY) dotRes (clk, rst, ena, a_res_e + b_res_e, res_out);

endmodule