data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/FFEControlMemory_4k.v
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/FFEControlMemory_4k.v:12: Cannot find include file: ulpsh_rtl_defines.v\n`include "ulpsh_rtl_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src,data/full_repos/permissive/137416811/ulpsh_rtl_defines.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src,data/full_repos/permissive/137416811/ulpsh_rtl_defines.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src,data/full_repos/permissive/137416811/ulpsh_rtl_defines.v.sv\n             ulpsh_rtl_defines.v\n             ulpsh_rtl_defines.v.v\n             ulpsh_rtl_defines.v.sv\n             obj_dir/ulpsh_rtl_defines.v\n             obj_dir/ulpsh_rtl_defines.v.v\n             obj_dir/ulpsh_rtl_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module FFEControlMemory_4k (

	input			ResetIn,
	input			SPI_clk,
	input			TLC_FFE_clk2x_muxed,

	input			MemSelect_en,
	input	[2:0]	MemSelect,

	input			FFE_clock_halfperiod,

	input	[11:0]	Address_TLC,

	input	[35:0]	MemoryMux_in,
	output	[35:0]	MemoryMux_out,


	input	[11:0]	ReadAddress_FFE,
	output	[35:0]	ReadData,
	input			ReadEnable_TLC,
	input			ReadEnable_FFE,


	input	[35:0]	WriteData_TLC,
	input			WriteEnable_TLC,


	output			assp_lb_ram0_clk,
    output	[8:0]	assp_lb_ram0_addr,
    output	[35:0]	assp_lb_ram0_wr_data,
    input	[35:0]	assp_lb_ram0_rd_data,
    output			assp_lb_ram0_wr_en,
    output			assp_lb_ram0_rd_en,
    output	[3:0]	assp_lb_ram0_wr_be,


	output			assp_rb_ram1_clk,
    output	[8:0]	assp_rb_ram1_addr,
    output	[35:0]	assp_rb_ram1_wr_data,
    input	[35:0]	assp_rb_ram1_rd_data,
    output			assp_rb_ram1_wr_en,
    output			assp_rb_ram1_rd_en,
    output	[3:0]	assp_rb_ram1_wr_be,


	output			assp_lb_ram8k_clk,
    output	[11:0]	assp_lb_ram8k_addr,
    output	[16:0]	assp_lb_ram8k_wr_data,
    input	[16:0]	assp_lb_ram8k_rd_data,
    output			assp_lb_ram8k_wr_en,
    output			assp_lb_ram8k_rd_en,
    output	[1:0]	assp_lb_ram8k_wr_be,
	

	output  [8:0]   FFEControlMemory_4k_Address_TLC_o      ,		
	output  [8:0]  	FFEControlMemory_4k_ReadAddress_muxed_o ,
	output    		FFEControlMemory_4k_ram5_wr_en_o,  			
	output    		FFEControlMemory_4k_ram5_rd_en_o,			
	output    		FFEControlMemory_4k_SPI_clk_o, 				
	output    		FFEControlMemory_4k_TLC_FFE_clk2x_muxed_o, 	
	output  [35:0]  FFEControlMemory_4k_WriteData_TLC_o ,
	input   [35:0]  FFEControlMemory_4k_ram5_rd_data_i	,
	output    		FFEControlMemory_4k_ram4_wr_en_o	,	
	output    		FFEControlMemory_4k_ram4_rd_en_o,
	input  [35:0]  FFEControlMemory_4k_ram4_rd_data_i,
	output [9:0]    FFEControlMemory_4k_fabric_ram1Kx9_addr_o,
	output 			FFEControlMemory_4k_ram1_wr_en_o  ,		
	output 			FFEControlMemory_4k_ram1_rd_en_o ,		
	input  [8:0]    FFEControlMemory_4k_ram1_rd_data_i
	
	
	
);

wire	[11:0]	ReadAddress_muxed;

wire			Select_from_TLC;

wire			ram0_wr_en;
wire			ram1_wr_en;
wire			ram2_wr_en;
wire			ram3_wr_en;
wire			ram4_wr_en;
wire			ram5_wr_en;

wire			ram0_rd_en;
wire			ram1_rd_en;
wire			ram2_rd_en;
wire			ram3_rd_en;
wire			ram4_rd_en;
wire			ram5_rd_en;

wire	[11:0]	assp_ram8k_addr;
wire	[9:0]	fabric_ram1Kx9_addr;

wire	[16:0]	ram0_rd_data;
wire	[8:0]	ram1_rd_data;
wire	[35:0]	ram2_rd_data;
wire	[35:0]	ram3_rd_data;
wire	[35:0]	ram4_rd_data;
wire	[35:0]	ram5_rd_data;
reg		[35:0]	lower2k_rd_data;
reg		[16:0]	lower2k_rd_data_phase0, lower2k_rd_data_phase1;
reg				ReadAddress_muxed_bit0_r1;

reg		[2:0]	ram_rd_select;
reg		[35:0]	ram_rd_data;
wire	[8:0]	assp_ram_addr;









assign Select_from_TLC = (MemSelect_en && (MemSelect == 3'h0 || MemSelect == 3'h4 || MemSelect == 3'h5));


assign MemoryMux_out = Select_from_TLC ? ReadData : MemoryMux_in;



assign ReadAddress_muxed = Select_from_TLC ? Address_TLC : ReadAddress_FFE;
assign ReadEnable_muxed = Select_from_TLC ? ReadEnable_TLC : ReadEnable_FFE;



assign assp_ram8k_addr = Select_from_TLC ? Address_TLC : {ReadAddress_FFE[10:0], FFE_clock_halfperiod};


assign fabric_ram1Kx9_addr = Select_from_TLC ? Address_TLC : ReadAddress_FFE[10:1];



assign ram0_wr_en = (MemSelect_en && MemSelect == 3'h4 && WriteEnable_TLC);
assign ram1_wr_en = (MemSelect_en && MemSelect == 3'h5 && WriteEnable_TLC);
assign ram2_wr_en = (MemSelect_en && MemSelect == 3'h0 && WriteEnable_TLC && Address_TLC[10:9] == 2'b00);
assign ram3_wr_en = (MemSelect_en && MemSelect == 3'h0 && WriteEnable_TLC && Address_TLC[10:9] == 2'b01);
assign ram4_wr_en = (                MemSelect == 3'h0 && WriteEnable_TLC && Address_TLC[10:9] == 2'b10);
assign ram5_wr_en = (                MemSelect == 3'h0 && WriteEnable_TLC && Address_TLC[10:9] == 2'b11);


assign ram0_rd_en = (MemSelect_en && MemSelect == 3'h4) ? ReadEnable_TLC : (ReadEnable_FFE && ReadAddress_FFE[11] == 1'b0);
assign ram1_rd_en = (MemSelect_en && MemSelect == 3'h5) ? ReadEnable_TLC : (ReadEnable_FFE && ReadAddress_FFE[11] == 1'b0 && FFE_clock_halfperiod);
assign ram2_rd_en = (MemSelect_en && MemSelect == 3'h0) ? (ReadEnable_TLC && Address_TLC[10:9] == 2'b00) : (ReadEnable_FFE && FFE_clock_halfperiod && ReadAddress_FFE[11:9] == 3'b100 && FFE_clock_halfperiod);
assign ram3_rd_en = (MemSelect_en && MemSelect == 3'h0) ? (ReadEnable_TLC && Address_TLC[10:9] == 2'b01) : (ReadEnable_FFE && FFE_clock_halfperiod && ReadAddress_FFE[11:9] == 3'b101 && FFE_clock_halfperiod);
assign ram4_rd_en = (MemSelect_en && MemSelect == 3'h0) ? (ReadEnable_TLC && Address_TLC[10:9] == 2'b10) : (ReadEnable_FFE && FFE_clock_halfperiod && ReadAddress_FFE[11:9] == 3'b110 && FFE_clock_halfperiod);
assign ram5_rd_en = (MemSelect_en && MemSelect == 3'h0) ? (ReadEnable_TLC && Address_TLC[10:9] == 2'b11) : (ReadEnable_FFE && FFE_clock_halfperiod && ReadAddress_FFE[11:9] == 3'b111 && FFE_clock_halfperiod);



assign FFEControlMemory_4k_Address_TLC_o[8:0] 			= Address_TLC[8:0];
assign FFEControlMemory_4k_ReadAddress_muxed_o[8:0] 	= ReadAddress_muxed[8:0];
assign FFEControlMemory_4k_ram5_wr_en_o  				= ram5_wr_en ;
assign FFEControlMemory_4k_ram5_rd_en_o 				= ram5_rd_en;
assign FFEControlMemory_4k_SPI_clk_o 					= SPI_clk;
assign FFEControlMemory_4k_TLC_FFE_clk2x_muxed_o 		= TLC_FFE_clk2x_muxed;
assign FFEControlMemory_4k_WriteData_TLC_o 				= WriteData_TLC;
assign ram5_rd_data 									= FFEControlMemory_4k_ram5_rd_data_i;


assign FFEControlMemory_4k_ram4_wr_en_o  				= ram4_wr_en ;
assign FFEControlMemory_4k_ram4_rd_en_o 				= ram4_rd_en;
assign ram4_rd_data 									= FFEControlMemory_4k_ram4_rd_data_i;




assign assp_ram_addr = (MemSelect_en && MemSelect == 3'h0) ? Address_TLC[8:0] : ReadAddress_muxed[8:0];



assign assp_rb_ram1_clk		= TLC_FFE_clk2x_muxed;
assign assp_rb_ram1_addr	= assp_ram_addr;
assign assp_rb_ram1_wr_data	= WriteData_TLC;
assign ram3_rd_data			= assp_rb_ram1_rd_data;
assign assp_rb_ram1_wr_en	= ram3_wr_en;
assign assp_rb_ram1_rd_en	= ram3_rd_en;
assign assp_rb_ram1_wr_be	= 4'b1111;



assign assp_lb_ram0_clk		= TLC_FFE_clk2x_muxed;
assign assp_lb_ram0_addr	= assp_ram_addr;
assign assp_lb_ram0_wr_data	= WriteData_TLC;
assign ram2_rd_data			= assp_lb_ram0_rd_data;
assign assp_lb_ram0_wr_en	= ram2_wr_en;
assign assp_lb_ram0_rd_en	= ram2_rd_en;
assign assp_lb_ram0_wr_be	= 4'b1111;

assign FFEControlMemory_4k_fabric_ram1Kx9_addr_o		= fabric_ram1Kx9_addr;
assign FFEControlMemory_4k_ram1_wr_en_o  				= ram1_wr_en ;
assign FFEControlMemory_4k_ram1_rd_en_o 				= ram1_rd_en;
assign FFEControlMemory_4k_SPI_clk_o 					= SPI_clk;
assign ram1_rd_data 									= FFEControlMemory_4k_ram1_rd_data_i;



assign assp_lb_ram8k_clk		= TLC_FFE_clk2x_muxed;
assign assp_lb_ram8k_addr		= assp_ram8k_addr;
assign assp_lb_ram8k_wr_data	= WriteData_TLC;
assign ram0_rd_data				= assp_lb_ram8k_rd_data;
assign assp_lb_ram8k_wr_en		= ram0_wr_en;
assign assp_lb_ram8k_rd_en		= ram0_rd_en;
assign assp_lb_ram8k_wr_be		= 2'b11;



always @(posedge TLC_FFE_clk2x_muxed) begin
	if (FFE_clock_halfperiod)
		lower2k_rd_data_phase0 <= ram0_rd_data;
	if (!FFE_clock_halfperiod)
		lower2k_rd_data_phase1 <= ram0_rd_data;
	if (FFE_clock_halfperiod)
		ReadAddress_muxed_bit0_r1 <= ReadAddress_muxed[0];
end


always @(*)
	if (FFE_clock_halfperiod == 0)
		if (ReadAddress_muxed_bit0_r1 == 0)
			lower2k_rd_data <= {ram1_rd_data[1:0], ram0_rd_data[16:0], lower2k_rd_data_phase0[16:0]};
		else
			lower2k_rd_data <= {ram1_rd_data[3:2], ram0_rd_data[16:0], lower2k_rd_data_phase0[16:0]};
	else
		if (ReadAddress_muxed_bit0_r1 == 0)
			lower2k_rd_data <= {ram1_rd_data[1:0], lower2k_rd_data_phase1[16:0], lower2k_rd_data_phase0[16:0]};
		else
			lower2k_rd_data <= {ram1_rd_data[3:2], lower2k_rd_data_phase1[16:0], lower2k_rd_data_phase0[16:0]};




always @(posedge TLC_FFE_clk2x_muxed)
	if (FFE_clock_halfperiod)
		ram_rd_select <= ReadAddress_muxed[11:9];

always @(*)
	if (MemSelect_en)

		if (MemSelect == 3'h0)
			case (ram_rd_select[1:0])
				2'b00:	ram_rd_data <= ram2_rd_data;
				2'b01:	ram_rd_data <= ram3_rd_data;
				2'b10:	ram_rd_data <= ram4_rd_data;
				2'b11:	ram_rd_data <= ram5_rd_data;
			endcase
		else
			if (MemSelect == 3'h4)
				ram_rd_data <= ram0_rd_data;
			else



					ram_rd_data <= ram1_rd_data;


	else

		if (ram_rd_select[2])

			case(ram_rd_select[1:0])
				2'b00:	ram_rd_data <= ram2_rd_data;
				2'b01:	ram_rd_data <= ram3_rd_data;
				2'b10:	ram_rd_data <= ram4_rd_data;
				2'b11:	ram_rd_data <= ram5_rd_data;
			endcase
		else

			ram_rd_data <= lower2k_rd_data;

assign ReadData = ram_rd_data;


endmodule
module FFEControlMemory_4k (

	input			ResetIn,
	input			SPI_clk,
	input			TLC_FFE_clk2x_muxed,

	input			MemSelect_en,
	input	[2:0]	MemSelect,

	input			FFE_clock_halfperiod,

	input	[11:0]	Address_TLC,

	input	[35:0]	MemoryMux_in,
	output	[35:0]	MemoryMux_out,


	input	[11:0]	ReadAddress_FFE,
	output	[35:0]	ReadData,
	input			ReadEnable_TLC,
	input			ReadEnable_FFE,


	input	[35:0]	WriteData_TLC,
	input			WriteEnable_TLC,


	output			assp_lb_ram0_clk,
    output	[8:0]	assp_lb_ram0_addr,
    output	[35:0]	assp_lb_ram0_wr_data,
    input	[35:0]	assp_lb_ram0_rd_data,
    output			assp_lb_ram0_wr_en,
    output			assp_lb_ram0_rd_en,
    output	[3:0]	assp_lb_ram0_wr_be,


	output			assp_rb_ram1_clk,
    output	[8:0]	assp_rb_ram1_addr,
    output	[35:0]	assp_rb_ram1_wr_data,
    input	[35:0]	assp_rb_ram1_rd_data,
    output			assp_rb_ram1_wr_en,
    output			assp_rb_ram1_rd_en,
    output	[3:0]	assp_rb_ram1_wr_be,


	output			assp_lb_ram8k_clk,
    output	[11:0]	assp_lb_ram8k_addr,
    output	[16:0]	assp_lb_ram8k_wr_data,
    input	[16:0]	assp_lb_ram8k_rd_data,
    output			assp_lb_ram8k_wr_en,
    output			assp_lb_ram8k_rd_en,
    output	[1:0]	assp_lb_ram8k_wr_be,
	

	output  [8:0]   FFEControlMemory_4k_Address_TLC_o      ,		
	output  [8:0]  	FFEControlMemory_4k_ReadAddress_muxed_o ,
	output    		FFEControlMemory_4k_ram5_wr_en_o,  			
	output    		FFEControlMemory_4k_ram5_rd_en_o,			
	output    		FFEControlMemory_4k_SPI_clk_o, 				
	output    		FFEControlMemory_4k_TLC_FFE_clk2x_muxed_o, 	
	output  [35:0]  FFEControlMemory_4k_WriteData_TLC_o ,
	input   [35:0]  FFEControlMemory_4k_ram5_rd_data_i	,
	output    		FFEControlMemory_4k_ram4_wr_en_o	,	
	output    		FFEControlMemory_4k_ram4_rd_en_o,
	input  [35:0]  FFEControlMemory_4k_ram4_rd_data_i,
	output [9:0]    FFEControlMemory_4k_fabric_ram1Kx9_addr_o,
	output 			FFEControlMemory_4k_ram1_wr_en_o  ,		
	output 			FFEControlMemory_4k_ram1_rd_en_o ,		
	input  [8:0]    FFEControlMemory_4k_ram1_rd_data_i
	
	
	
);


wire	[11:0]	ReadAddress_muxed;

wire			Select_from_TLC;

wire			ram0_wr_en;
wire			ram1_wr_en;
wire			ram2_wr_en;
wire			ram3_wr_en;
wire			ram4_wr_en;
wire			ram5_wr_en;

wire			ram0_rd_en;
wire			ram1_rd_en;
wire			ram2_rd_en;
wire			ram3_rd_en;
wire			ram4_rd_en;
wire			ram5_rd_en;

wire	[11:0]	assp_ram8k_addr;
wire	[9:0]	fabric_ram1Kx9_addr;

wire	[16:0]	ram0_rd_data;
wire	[8:0]	ram1_rd_data;
wire	[35:0]	ram2_rd_data;
wire	[35:0]	ram3_rd_data;
wire	[35:0]	ram4_rd_data;
wire	[35:0]	ram5_rd_data;
reg		[35:0]	lower2k_rd_data;
reg		[16:0]	lower2k_rd_data_phase0, lower2k_rd_data_phase1;
reg				ReadAddress_muxed_bit0_r1;

reg		[2:0]	ram_rd_select;
reg		[35:0]	ram_rd_data;
wire	[8:0]	assp_ram_addr;









assign Select_from_TLC = (MemSelect_en && (MemSelect == 3'h0 || MemSelect == 3'h4 || MemSelect == 3'h5));


assign MemoryMux_out = Select_from_TLC ? ReadData : MemoryMux_in;



assign ReadAddress_muxed = Select_from_TLC ? Address_TLC : ReadAddress_FFE;
assign ReadEnable_muxed = Select_from_TLC ? ReadEnable_TLC : ReadEnable_FFE;



assign assp_ram8k_addr = Select_from_TLC ? Address_TLC : {ReadAddress_FFE[10:0], FFE_clock_halfperiod};


assign fabric_ram1Kx9_addr = Select_from_TLC ? Address_TLC : ReadAddress_FFE[10:1];



assign ram0_wr_en = (MemSelect_en && MemSelect == 3'h4 && WriteEnable_TLC);
assign ram1_wr_en = (MemSelect_en && MemSelect == 3'h5 && WriteEnable_TLC);
assign ram2_wr_en = (MemSelect_en && MemSelect == 3'h0 && WriteEnable_TLC && Address_TLC[10:9] == 2'b00);
assign ram3_wr_en = (MemSelect_en && MemSelect == 3'h0 && WriteEnable_TLC && Address_TLC[10:9] == 2'b01);
assign ram4_wr_en = (                MemSelect == 3'h0 && WriteEnable_TLC && Address_TLC[10:9] == 2'b10);
assign ram5_wr_en = (                MemSelect == 3'h0 && WriteEnable_TLC && Address_TLC[10:9] == 2'b11);


assign ram0_rd_en = (MemSelect_en && MemSelect == 3'h4) ? ReadEnable_TLC : (ReadEnable_FFE && ReadAddress_FFE[11] == 1'b0);
assign ram1_rd_en = (MemSelect_en && MemSelect == 3'h5) ? ReadEnable_TLC : (ReadEnable_FFE && ReadAddress_FFE[11] == 1'b0 && FFE_clock_halfperiod);
assign ram2_rd_en = (MemSelect_en && MemSelect == 3'h0) ? (ReadEnable_TLC && Address_TLC[10:9] == 2'b00) : (ReadEnable_FFE && FFE_clock_halfperiod && ReadAddress_FFE[11:9] == 3'b100 && FFE_clock_halfperiod);
assign ram3_rd_en = (MemSelect_en && MemSelect == 3'h0) ? (ReadEnable_TLC && Address_TLC[10:9] == 2'b01) : (ReadEnable_FFE && FFE_clock_halfperiod && ReadAddress_FFE[11:9] == 3'b101 && FFE_clock_halfperiod);
assign ram4_rd_en = (MemSelect_en && MemSelect == 3'h0) ? (ReadEnable_TLC && Address_TLC[10:9] == 2'b10) : (ReadEnable_FFE && FFE_clock_halfperiod && ReadAddress_FFE[11:9] == 3'b110 && FFE_clock_halfperiod);
assign ram5_rd_en = (MemSelect_en && MemSelect == 3'h0) ? (ReadEnable_TLC && Address_TLC[10:9] == 2'b11) : (ReadEnable_FFE && FFE_clock_halfperiod && ReadAddress_FFE[11:9] == 3'b111 && FFE_clock_halfperiod);



assign FFEControlMemory_4k_Address_TLC_o[8:0] 			= Address_TLC[8:0];
assign FFEControlMemory_4k_ReadAddress_muxed_o[8:0] 	= ReadAddress_muxed[8:0];
assign FFEControlMemory_4k_ram5_wr_en_o  				= ram5_wr_en ;
assign FFEControlMemory_4k_ram5_rd_en_o 				= ram5_rd_en;
assign FFEControlMemory_4k_SPI_clk_o 					= SPI_clk;
assign FFEControlMemory_4k_TLC_FFE_clk2x_muxed_o 		= TLC_FFE_clk2x_muxed;
assign FFEControlMemory_4k_WriteData_TLC_o 				= WriteData_TLC;
assign ram5_rd_data 									= FFEControlMemory_4k_ram5_rd_data_i;


assign FFEControlMemory_4k_ram4_wr_en_o  				= ram4_wr_en ;
assign FFEControlMemory_4k_ram4_rd_en_o 				= ram4_rd_en;
assign ram4_rd_data 									= FFEControlMemory_4k_ram4_rd_data_i;




assign assp_ram_addr = (MemSelect_en && MemSelect == 3'h0) ? Address_TLC[8:0] : ReadAddress_muxed[8:0];



assign assp_rb_ram1_clk		= TLC_FFE_clk2x_muxed;
assign assp_rb_ram1_addr	= assp_ram_addr;
assign assp_rb_ram1_wr_data	= WriteData_TLC;
assign ram3_rd_data			= assp_rb_ram1_rd_data;
assign assp_rb_ram1_wr_en	= ram3_wr_en;
assign assp_rb_ram1_rd_en	= ram3_rd_en;
assign assp_rb_ram1_wr_be	= 4'b1111;



assign assp_lb_ram0_clk		= TLC_FFE_clk2x_muxed;
assign assp_lb_ram0_addr	= assp_ram_addr;
assign assp_lb_ram0_wr_data	= WriteData_TLC;
assign ram2_rd_data			= assp_lb_ram0_rd_data;
assign assp_lb_ram0_wr_en	= ram2_wr_en;
assign assp_lb_ram0_rd_en	= ram2_rd_en;
assign assp_lb_ram0_wr_be	= 4'b1111;

assign FFEControlMemory_4k_fabric_ram1Kx9_addr_o		= fabric_ram1Kx9_addr;
assign FFEControlMemory_4k_ram1_wr_en_o  				= ram1_wr_en ;
assign FFEControlMemory_4k_ram1_rd_en_o 				= ram1_rd_en;
assign FFEControlMemory_4k_SPI_clk_o 					= SPI_clk;
assign ram1_rd_data 									= FFEControlMemory_4k_ram1_rd_data_i;



assign assp_lb_ram8k_clk		= TLC_FFE_clk2x_muxed;
assign assp_lb_ram8k_addr		= assp_ram8k_addr;
assign assp_lb_ram8k_wr_data	= WriteData_TLC;
assign ram0_rd_data				= assp_lb_ram8k_rd_data;
assign assp_lb_ram8k_wr_en		= ram0_wr_en;
assign assp_lb_ram8k_rd_en		= ram0_rd_en;
assign assp_lb_ram8k_wr_be		= 2'b11;



always @(posedge TLC_FFE_clk2x_muxed) begin
	if (FFE_clock_halfperiod)
		lower2k_rd_data_phase0 <= ram0_rd_data;
	if (!FFE_clock_halfperiod)
		lower2k_rd_data_phase1 <= ram0_rd_data;
	if (FFE_clock_halfperiod)
		ReadAddress_muxed_bit0_r1 <= ReadAddress_muxed[0];
end


always @(*)
	if (FFE_clock_halfperiod == 0)
		if (ReadAddress_muxed_bit0_r1 == 0)
			lower2k_rd_data <= {ram1_rd_data[1:0], ram0_rd_data[16:0], lower2k_rd_data_phase0[16:0]};
		else
			lower2k_rd_data <= {ram1_rd_data[3:2], ram0_rd_data[16:0], lower2k_rd_data_phase0[16:0]};
	else
		if (ReadAddress_muxed_bit0_r1 == 0)
			lower2k_rd_data <= {ram1_rd_data[1:0], lower2k_rd_data_phase1[16:0], lower2k_rd_data_phase0[16:0]};
		else
			lower2k_rd_data <= {ram1_rd_data[3:2], lower2k_rd_data_phase1[16:0], lower2k_rd_data_phase0[16:0]};




always @(posedge TLC_FFE_clk2x_muxed)
	if (FFE_clock_halfperiod)
		ram_rd_select <= ReadAddress_muxed[11:9];

always @(*)
	if (MemSelect_en)

		if (MemSelect == 3'h0)
			case (ram_rd_select[1:0])
				2'b00:	ram_rd_data <= ram2_rd_data;
				2'b01:	ram_rd_data <= ram3_rd_data;
				2'b10:	ram_rd_data <= ram4_rd_data;
				2'b11:	ram_rd_data <= ram5_rd_data;
			endcase
		else
			if (MemSelect == 3'h4)
				ram_rd_data <= ram0_rd_data;
			else



					ram_rd_data <= ram1_rd_data;


	else

		if (ram_rd_select[2])

			case(ram_rd_select[1:0])
				2'b00:	ram_rd_data <= ram2_rd_data;
				2'b01:	ram_rd_data <= ram3_rd_data;
				2'b10:	ram_rd_data <= ram4_rd_data;
				2'b11:	ram_rd_data <= ram5_rd_data;
			endcase
		else

			ram_rd_data <= lower2k_rd_data;

assign ReadData = ram_rd_data;


endmodule