data/full_repos/permissive/174369527/mul_pipelined/mul.v
1: b'%Warning-WIDTH: data/full_repos/permissive/174369527/mul_pipelined/mul.v:59: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 7 bits.\n                                                                           : ... In instance mult_piped_8x8_2sC\n   0: a_mag = a[6:0];\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/174369527/mul_pipelined/mul.v:63: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 7 bits.\n                                                                           : ... In instance mult_piped_8x8_2sC\n    0: b_mag = b[6:0];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/174369527/mul_pipelined/mul.v:70: Operator SUB expects 32 or 16 bits on the RHS, but RHS\'s SEL generates 14 bits.\n                                                                           : ... In instance mult_piped_8x8_2sC\n    y_neg = 32768 - y_mag[13:0];     \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/174369527/mul_pipelined/mul.v:70: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 16 bits.\n                                                                           : ... In instance mult_piped_8x8_2sC\n    y_neg = 32768 - y_mag[13:0];     \n          ^\n%Warning-WIDTH: data/full_repos/permissive/174369527/mul_pipelined/mul.v:74: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'y_mag\' generates 15 bits.\n                                                                           : ... In instance mult_piped_8x8_2sC\n   multiply_8x8_2sC = y_mag;\n                    ^\n%Error: Exiting due to 5 warning(s)\n'
module mult_piped_8x8_2sC (a, b, clk, reset, y);

input[7:0] a,b;
input clk,reset;
output[15:0] y;











reg[7:0] aR[8:0];
reg[7:0] bR[8:0];
reg[15:0] yR[8:0];

always @ (posedge clk)
  begin
   aR[7] = aR[6];
   bR[7] = bR[6];
   yR[7] = yR[6];
   aR[6] = aR[5];
   bR[6] = bR[5];
   yR[6] = yR[5];
   aR[5] = aR[4];
   bR[5] = bR[4];
   yR[5] = yR[4];
   aR[4] = aR[3];
   bR[4] = bR[3];
   yR[4] = yR[3];
   aR[3] = aR[2];
   bR[3] = bR[2];
   yR[3] = yR[2];
   aR[2] = aR[1];
   bR[2] = bR[1];
   yR[2] = yR[1];
   aR[1] = aR[0];
   bR[1] = bR[0];
   yR[1] = yR[0];

   aR[0] = a;
   bR[0] = b;
   yR[0] = multiply_8x8_2sC (aR[0],bR[0]);
  end

function[15:0] multiply_8x8_2sC;
input[7:0] a,b;
reg[7:0] a_mag,b_mag;
reg[14:0] y_mag;
reg[14:0] y_neg;
begin
  case (a[7])
   0: a_mag = a[6:0];
   1: a_mag = 128 - a[6:0];
  endcase
  case (b[7])
    0: b_mag = b[6:0];
    1: b_mag = 128 - b[6:0];
  endcase
  y_mag = a_mag * b_mag;
  if ((a[7] ^ b[7]) & (y_mag != 0))
  begin

    y_neg = 32768 - y_mag[13:0];
    multiply_8x8_2sC = {1'b1,y_neg};
  end
  else
   multiply_8x8_2sC = y_mag;
end
endfunction


assign y = yR[7];

endmodule
module mult_piped_8x8_2sC (a, b, clk, reset, y);


input[7:0] a,b;
input clk,reset;
output[15:0] y;











reg[7:0] aR[8:0];
reg[7:0] bR[8:0];
reg[15:0] yR[8:0];

always @ (posedge clk)
  begin
   aR[7] = aR[6];
   bR[7] = bR[6];
   yR[7] = yR[6];
   aR[6] = aR[5];
   bR[6] = bR[5];
   yR[6] = yR[5];
   aR[5] = aR[4];
   bR[5] = bR[4];
   yR[5] = yR[4];
   aR[4] = aR[3];
   bR[4] = bR[3];
   yR[4] = yR[3];
   aR[3] = aR[2];
   bR[3] = bR[2];
   yR[3] = yR[2];
   aR[2] = aR[1];
   bR[2] = bR[1];
   yR[2] = yR[1];
   aR[1] = aR[0];
   bR[1] = bR[0];
   yR[1] = yR[0];

   aR[0] = a;
   bR[0] = b;
   yR[0] = multiply_8x8_2sC (aR[0],bR[0]);
  end

function[15:0] multiply_8x8_2sC;
input[7:0] a,b;
reg[7:0] a_mag,b_mag;
reg[14:0] y_mag;
reg[14:0] y_neg;
begin
  case (a[7])
   0: a_mag = a[6:0];
   1: a_mag = 128 - a[6:0];
  endcase
  case (b[7])
    0: b_mag = b[6:0];
    1: b_mag = 128 - b[6:0];
  endcase
  y_mag = a_mag * b_mag;
  if ((a[7] ^ b[7]) & (y_mag != 0))
  begin

    y_neg = 32768 - y_mag[13:0];
    multiply_8x8_2sC = {1'b1,y_neg};
  end
  else
   multiply_8x8_2sC = y_mag;
end
endfunction


assign y = yR[7];

endmodule