data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v
 line:1 column:1: Illegal character '\x00'
1: b"%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:33: Define or directive not defined: '`CEILDIV_FUNC'\n   `CEILDIV_FUNC\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:94: Define or directive not defined: '`VLAN_CTRL_WORD'\n               if (fifo_ctrl_out == `VLAN_CTRL_WORD && fifo_data_out[31]==0) begin\n                                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:94: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n               if (fifo_ctrl_out == `VLAN_CTRL_WORD && fifo_data_out[31]==0) begin\n                                                    ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:99: Define or directive not defined: '`VLAN_CTRL_WORD'\n               else if(fifo_ctrl_out == `VLAN_CTRL_WORD && fifo_data_out[31]==1) begin\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:99: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n               else if(fifo_ctrl_out == `VLAN_CTRL_WORD && fifo_data_out[31]==1) begin\n                                                        ^~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:103: syntax error, unexpected else, expecting endcase\n               else begin\n               ^~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:113: Define or directive not defined: '`IO_QUEUE_STAGE_NUM'\n               if (fifo_ctrl_out == `IO_QUEUE_STAGE_NUM) begin\n                                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:113: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n               if (fifo_ctrl_out == `IO_QUEUE_STAGE_NUM) begin\n                                                       ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:115: Define or directive not defined: '`IOQ_BYTE_LEN_POS'\n                  out_data_nxt[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS]\n                               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:115: Define or directive not defined: '`IOQ_BYTE_LEN_POS'\n                  out_data_nxt[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS]\n                                                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:116: Define or directive not defined: '`IOQ_BYTE_LEN_POS'\n                     = fifo_data_out[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] + 4;\n                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:116: Define or directive not defined: '`IOQ_BYTE_LEN_POS'\n                     = fifo_data_out[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] + 4;\n                                                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:117: Define or directive not defined: '`IOQ_WORD_LEN_POS'\n                  out_data_nxt[`IOQ_WORD_LEN_POS+15:`IOQ_WORD_LEN_POS]\n                               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:117: Define or directive not defined: '`IOQ_WORD_LEN_POS'\n                  out_data_nxt[`IOQ_WORD_LEN_POS+15:`IOQ_WORD_LEN_POS]\n                                                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:118: Define or directive not defined: '`IOQ_BYTE_LEN_POS'\n                     = ceildiv((fifo_data_out[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] + 4), 8);\n                                              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:118: Define or directive not defined: '`IOQ_BYTE_LEN_POS'\n                     = ceildiv((fifo_data_out[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] + 4), 8);\n                                                                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:132: syntax error, unexpected '=', expecting IDENTIFIER\n                  out_data_nxt      = {fifo_data_out[63:32], `VLAN_ETHERTYPE, vlan_tag};\n                                    ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:132: Define or directive not defined: '`VLAN_ETHERTYPE'\n                  out_data_nxt      = {fifo_data_out[63:32], `VLAN_ETHERTYPE, vlan_tag};\n                                                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:141: syntax error, unexpected '=', expecting IDENTIFIER\n                  process_state_nxt = FIND_VLAN_HDR;\n                                    ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:154: syntax error, unexpected '=', expecting IDENTIFIER\n                  out_ctrl_nxt = (fifo_ctrl_out >> 4);\n                               ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v:158: syntax error, unexpected '=', expecting IDENTIFIER\n                  out_ctrl_nxt = 0;\n                               ^\n%Error: Cannot continue\n"
module vlan_adder
    #(parameter DATA_WIDTH = 64,
      parameter CTRL_WIDTH = DATA_WIDTH/8
      )
   (
    input  [DATA_WIDTH-1:0]                in_data,
    input  [CTRL_WIDTH-1:0]                in_ctrl,
    input                                  in_wr,
    output                                 in_rdy,


    output reg [DATA_WIDTH-1:0]            out_data,
    output reg [CTRL_WIDTH-1:0]            out_ctrl,
    output reg                             out_wr,
    input                                  out_rdy,


    input                                  reset,
    input                                  clk
   );

   `CEILDIV_FUNC


   localparam NUM_STATES         = 5;
   localparam FIND_VLAN_HDR      = 0,
              WAIT_SOP           = 1,
              ADD_VLAN           = 2,
              WRITE_MODIFIED_PKT = 3,
              WRITE_LAST_PKT     = 4;



   wire [DATA_WIDTH-1:0] fifo_data_out;
   wire [CTRL_WIDTH-1:0] fifo_ctrl_out;

   reg [15:0]            vlan_tag_nxt, vlan_tag;
   reg [31:0]            latch_data_nxt, latch_data;
   reg [7:0]             latch_ctrl_nxt, latch_ctrl;

   reg [NUM_STATES-1:0]  process_state_nxt, process_state;
   reg                   fifo_rd_en;
   reg                   out_wr_nxt;
   reg [DATA_WIDTH-1:0]  out_data_nxt;
   reg [CTRL_WIDTH-1:0]  out_ctrl_nxt;



   fallthrough_small_fifo
     #(.WIDTH(CTRL_WIDTH+DATA_WIDTH), .MAX_DEPTH_BITS(3))
     input_fifo
       (.din           ({in_ctrl, in_data}),
        .wr_en         (in_wr),
        .rd_en         (fifo_rd_en),
        .dout          ({fifo_ctrl_out, fifo_data_out}),
        .full          (),
        .prog_full     (),
        .nearly_full   (fifo_nearly_full),
        .empty         (fifo_empty),
        .reset         (reset),
        .clk           (clk)
        );



   assign in_rdy = !fifo_nearly_full;

   always @(*) begin
      process_state_nxt = process_state;
      fifo_rd_en        = 0;
      out_wr_nxt        = 0;
      out_data_nxt      = fifo_data_out;
      out_ctrl_nxt      = fifo_ctrl_out;
      vlan_tag_nxt      = vlan_tag;
      latch_data_nxt    = latch_data;
      latch_ctrl_nxt    = latch_ctrl;

      case (process_state)

         FIND_VLAN_HDR: begin
            if (out_rdy && !fifo_empty) begin
               fifo_rd_en = 1;
               if (fifo_ctrl_out == `VLAN_CTRL_WORD && fifo_data_out[31]==0) begin
                  out_wr_nxt        = 0;
                  vlan_tag_nxt      = fifo_data_out[15:0];
                  process_state_nxt = WAIT_SOP;
               end
               else if(fifo_ctrl_out == `VLAN_CTRL_WORD && fifo_data_out[31]==1) begin
                     out_wr_nxt        = 0;
                      vlan_tag_nxt      = 0;
               end
               else begin
                  out_wr_nxt = 1;
               end
            end
         end

         WAIT_SOP: begin
            if (out_rdy && !fifo_empty) begin
               fifo_rd_en = 1;
               out_wr_nxt = 1;
               if (fifo_ctrl_out == `IO_QUEUE_STAGE_NUM) begin

                  out_data_nxt[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS]
                     = fifo_data_out[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] + 4;
                  out_data_nxt[`IOQ_WORD_LEN_POS+15:`IOQ_WORD_LEN_POS]
                     = ceildiv((fifo_data_out[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] + 4), 8);
               end
               else if (fifo_ctrl_out == 0) begin
                  process_state_nxt = ADD_VLAN;
               end
            end
         end

         ADD_VLAN: begin
            if (out_rdy && !fifo_empty) begin

               fifo_rd_en        = 1;
               out_wr_nxt        = 1;
               if (fifo_ctrl_out == 0) begin
                  out_data_nxt      = {fifo_data_out[63:32], `VLAN_ETHERTYPE, vlan_tag};
                  latch_data_nxt    = fifo_data_out[31:0];
                  latch_ctrl_nxt    = fifo_ctrl_out;
                  process_state_nxt = WRITE_MODIFIED_PKT;
               end



               else begin
                  process_state_nxt = FIND_VLAN_HDR;
               end
            end
         end

         WRITE_MODIFIED_PKT: begin
            if (out_rdy && !fifo_empty) begin
               fifo_rd_en     = 1;
               out_wr_nxt     = 1;
               out_data_nxt   = {latch_data, fifo_data_out[63:32]};
               latch_data_nxt = fifo_data_out[31:0];
               latch_ctrl_nxt = fifo_ctrl_out;
               if (fifo_ctrl_out[7:4] != 0) begin
                  out_ctrl_nxt = (fifo_ctrl_out >> 4);
                  process_state_nxt = FIND_VLAN_HDR;
               end
               else if (fifo_ctrl_out[3:0] != 0) begin
                  out_ctrl_nxt = 0;
                  process_state_nxt = WRITE_LAST_PKT;
               end
            end
         end

         WRITE_LAST_PKT: begin
            if (out_rdy) begin
               out_wr_nxt     = 1;
               out_data_nxt   = {latch_data, 32'h0};
               out_ctrl_nxt   = latch_ctrl << 4;
               process_state_nxt = FIND_VLAN_HDR;
            end
         end
      default:process_state_nxt=FIND_VLAN_HDR;
      endcase
   end

   always @(posedge clk) begin
      if(reset) begin
         process_state    <= FIND_VLAN_HDR;
         out_wr           <= 0;
         out_data         <= 0;
         out_ctrl         <= 1;
         latch_data       <= 0;
         latch_ctrl       <= 0;
         vlan_tag         <= 0;
      end
      else begin
         process_state    <= process_state_nxt;
         out_wr           <= out_wr_nxt;
         out_data         <= out_data_nxt;
         out_ctrl         <= out_ctrl_nxt;
         latch_data       <= latch_data_nxt;
         latch_ctrl       <= latch_ctrl_nxt;
         vlan_tag         <= vlan_tag_nxt;
      end
   end

endmodule
module vlan_adder
    #(parameter DATA_WIDTH = 64,
      parameter CTRL_WIDTH = DATA_WIDTH/8
      )
   (
    input  [DATA_WIDTH-1:0]                in_data,
    input  [CTRL_WIDTH-1:0]                in_ctrl,
    input                                  in_wr,
    output                                 in_rdy,


    output reg [DATA_WIDTH-1:0]            out_data,
    output reg [CTRL_WIDTH-1:0]            out_ctrl,
    output reg                             out_wr,
    input                                  out_rdy,


    input                                  reset,
    input                                  clk
   );


   `CEILDIV_FUNC


   localparam NUM_STATES         = 5;
   localparam FIND_VLAN_HDR      = 0,
              WAIT_SOP           = 1,
              ADD_VLAN           = 2,
              WRITE_MODIFIED_PKT = 3,
              WRITE_LAST_PKT     = 4;



   wire [DATA_WIDTH-1:0] fifo_data_out;
   wire [CTRL_WIDTH-1:0] fifo_ctrl_out;

   reg [15:0]            vlan_tag_nxt, vlan_tag;
   reg [31:0]            latch_data_nxt, latch_data;
   reg [7:0]             latch_ctrl_nxt, latch_ctrl;

   reg [NUM_STATES-1:0]  process_state_nxt, process_state;
   reg                   fifo_rd_en;
   reg                   out_wr_nxt;
   reg [DATA_WIDTH-1:0]  out_data_nxt;
   reg [CTRL_WIDTH-1:0]  out_ctrl_nxt;



   fallthrough_small_fifo
     #(.WIDTH(CTRL_WIDTH+DATA_WIDTH), .MAX_DEPTH_BITS(3))
     input_fifo
       (.din           ({in_ctrl, in_data}),
        .wr_en         (in_wr),
        .rd_en         (fifo_rd_en),
        .dout          ({fifo_ctrl_out, fifo_data_out}),
        .full          (),
        .prog_full     (),
        .nearly_full   (fifo_nearly_full),
        .empty         (fifo_empty),
        .reset         (reset),
        .clk           (clk)
        );



   assign in_rdy = !fifo_nearly_full;

   always @(*) begin
      process_state_nxt = process_state;
      fifo_rd_en        = 0;
      out_wr_nxt        = 0;
      out_data_nxt      = fifo_data_out;
      out_ctrl_nxt      = fifo_ctrl_out;
      vlan_tag_nxt      = vlan_tag;
      latch_data_nxt    = latch_data;
      latch_ctrl_nxt    = latch_ctrl;

      case (process_state)

         FIND_VLAN_HDR: begin
            if (out_rdy && !fifo_empty) begin
               fifo_rd_en = 1;
               if (fifo_ctrl_out == `VLAN_CTRL_WORD && fifo_data_out[31]==0) begin
                  out_wr_nxt        = 0;
                  vlan_tag_nxt      = fifo_data_out[15:0];
                  process_state_nxt = WAIT_SOP;
               end
               else if(fifo_ctrl_out == `VLAN_CTRL_WORD && fifo_data_out[31]==1) begin
                     out_wr_nxt        = 0;
                      vlan_tag_nxt      = 0;
               end
               else begin
                  out_wr_nxt = 1;
               end
            end
         end

         WAIT_SOP: begin
            if (out_rdy && !fifo_empty) begin
               fifo_rd_en = 1;
               out_wr_nxt = 1;
               if (fifo_ctrl_out == `IO_QUEUE_STAGE_NUM) begin

                  out_data_nxt[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS]
                     = fifo_data_out[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] + 4;
                  out_data_nxt[`IOQ_WORD_LEN_POS+15:`IOQ_WORD_LEN_POS]
                     = ceildiv((fifo_data_out[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] + 4), 8);
               end
               else if (fifo_ctrl_out == 0) begin
                  process_state_nxt = ADD_VLAN;
               end
            end
         end

         ADD_VLAN: begin
            if (out_rdy && !fifo_empty) begin

               fifo_rd_en        = 1;
               out_wr_nxt        = 1;
               if (fifo_ctrl_out == 0) begin
                  out_data_nxt      = {fifo_data_out[63:32], `VLAN_ETHERTYPE, vlan_tag};
                  latch_data_nxt    = fifo_data_out[31:0];
                  latch_ctrl_nxt    = fifo_ctrl_out;
                  process_state_nxt = WRITE_MODIFIED_PKT;
               end



               else begin
                  process_state_nxt = FIND_VLAN_HDR;
               end
            end
         end

         WRITE_MODIFIED_PKT: begin
            if (out_rdy && !fifo_empty) begin
               fifo_rd_en     = 1;
               out_wr_nxt     = 1;
               out_data_nxt   = {latch_data, fifo_data_out[63:32]};
               latch_data_nxt = fifo_data_out[31:0];
               latch_ctrl_nxt = fifo_ctrl_out;
               if (fifo_ctrl_out[7:4] != 0) begin
                  out_ctrl_nxt = (fifo_ctrl_out >> 4);
                  process_state_nxt = FIND_VLAN_HDR;
               end
               else if (fifo_ctrl_out[3:0] != 0) begin
                  out_ctrl_nxt = 0;
                  process_state_nxt = WRITE_LAST_PKT;
               end
            end
         end

         WRITE_LAST_PKT: begin
            if (out_rdy) begin
               out_wr_nxt     = 1;
               out_data_nxt   = {latch_data, 32'h0};
               out_ctrl_nxt   = latch_ctrl << 4;
               process_state_nxt = FIND_VLAN_HDR;
            end
         end
      default:process_state_nxt=FIND_VLAN_HDR;
      endcase
   end

   always @(posedge clk) begin
      if(reset) begin
         process_state    <= FIND_VLAN_HDR;
         out_wr           <= 0;
         out_data         <= 0;
         out_ctrl         <= 1;
         latch_data       <= 0;
         latch_ctrl       <= 0;
         vlan_tag         <= 0;
      end
      else begin
         process_state    <= process_state_nxt;
         out_wr           <= out_wr_nxt;
         out_data         <= out_data_nxt;
         out_ctrl         <= out_ctrl_nxt;
         latch_data       <= latch_data_nxt;
         latch_ctrl       <= latch_ctrl_nxt;
         vlan_tag         <= vlan_tag_nxt;
      end
   end

endmodule