data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/generator/HalfAdder.v
None: at end of input
data/verilator_xmls/1d1fdb99-25f0-4119-90ca-7de4d49c3484.xml
module HalfAdder(
	A,
	Cin,
	Cout,
	Sum
);


input wire	A;
input wire	Cin;
output wire	Cout;
output wire	Sum;





assign	Cout = A & Cin;

assign	Sum = A ^ Cin;


endmodule
module HalfAdder(
	A,
	Cin,
	Cout,
	Sum
);



input wire	A;
input wire	Cin;
output wire	Cout;
output wire	Sum;





assign	Cout = A & Cin;

assign	Sum = A ^ Cin;


endmodule