data/full_repos/permissive/154590168/rtl_cpu/PmCont.v
1: b'%Error: data/full_repos/permissive/154590168/rtl_cpu/PmCont.v:40: Cannot find include file: OpNumber.v\n`include "OpNumber.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v.v\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v.sv\n             OpNumber.v\n             OpNumber.v.v\n             OpNumber.v.sv\n             obj_dir/OpNumber.v\n             obj_dir/OpNumber.v.v\n             obj_dir/OpNumber.v.sv\n%Error: Exiting due to 1 error(s)\n'
module  PmCont (
    input               clock,
    input               reset,
    input       [15:0]  pm_rdata,
    input       [15:0]  pc,
    input       [15:0]  pc_new,
    input               pc_new_en,
    input       [1:0]   cycle,
    input               skip_en,
    input               irq_det,
    input       [15:0]  rf_rdata,
    input       [0:82]  op_decode,
    input               tim_pm_re,
    output  reg [15:0]  pm_addr,
    output  reg         pm_re,
    output  reg         pm_we,
    output  reg [15:0]  pm_wdata,
    output      [7:0]   lpm_data,
    output              lpm_data_en
);




wire[15:0]  pm_addr_new;
wire[15:0]  pm_addr_xpm;
wire        pm_re_lpm;
wire        pm_wd_spm;
wire        pm_wa_spm;
wire        pm_pc_xpm;
wire        pm_re_new;
wire        pm_wd_new;
reg         lpm_re_l;
reg         lpm_re_h;


`include "OpNumber.v"
wire    op_lpm    = op_decode[B_LPM   ];
wire    op_lpmz   = op_decode[B_LPMZ  ];
wire    op_lpmzi  = op_decode[B_LPMZI ];
wire    op_spm    = op_decode[B_SPM   ];




always @(posedge clock or posedge reset) begin
    if (reset) begin
        pm_addr <= 16'h0000;
        pm_re <= 1'b0;
        pm_we <= 1'b0;
        pm_wdata <= 16'h0000;
    end else begin
        pm_addr <= (pm_re_new | pm_wa_spm) ? pm_addr_new : pm_addr;
        pm_re <= pm_re_new;
        pm_we <= pm_wa_spm;
        pm_wdata <= pm_wd_new ? rf_rdata : pm_wdata;
    end
end

assign  pm_addr_new = pc_new_en ? pc_new : pm_addr_xpm;

assign  pm_addr_xpm = (pm_re_lpm ? {1'b0, rf_rdata[15:1]} : 16'h0000)
                    | (pm_wa_spm ? rf_rdata               : 16'h0000)
                    | (pm_pc_xpm ? pc                     : 16'h0000);

assign  pm_re_lpm   = (op_lpm   & (cycle == 2'd0))
                    | (op_lpmz  & (cycle == 2'd0))
                    | (op_lpmzi & (cycle == 2'd0));

assign  pm_wd_spm   = (op_spm & (cycle == 2'd0));
assign  pm_wa_spm   = (op_spm & (cycle == 2'd1));

assign  pm_pc_xpm   = (op_lpm   & (cycle == 2'd1))
                    | (op_lpmz  & (cycle == 2'd1))
                    | (op_lpmzi & (cycle == 2'd1))
                    | (op_spm   & (cycle == 2'd2));

assign  pm_re_new = (tim_pm_re | skip_en) & ~irq_det;
assign  pm_wd_new = pm_wd_spm & ~skip_en;




always @(posedge clock) begin
    lpm_re_l <= pm_re_lpm & ~rf_rdata[0] & ~skip_en;
    lpm_re_h <= pm_re_lpm &  rf_rdata[0] & ~skip_en;
end

assign  lpm_data = (lpm_re_l ? pm_rdata[7:0]  : 8'h00)
                 | (lpm_re_h ? pm_rdata[15:8] : 8'h00);

assign  lpm_data_en = lpm_re_l | lpm_re_h;

endmodule
module  PmCont (
    input               clock,
    input               reset,
    input       [15:0]  pm_rdata,
    input       [15:0]  pc,
    input       [15:0]  pc_new,
    input               pc_new_en,
    input       [1:0]   cycle,
    input               skip_en,
    input               irq_det,
    input       [15:0]  rf_rdata,
    input       [0:82]  op_decode,
    input               tim_pm_re,
    output  reg [15:0]  pm_addr,
    output  reg         pm_re,
    output  reg         pm_we,
    output  reg [15:0]  pm_wdata,
    output      [7:0]   lpm_data,
    output              lpm_data_en
);





wire[15:0]  pm_addr_new;
wire[15:0]  pm_addr_xpm;
wire        pm_re_lpm;
wire        pm_wd_spm;
wire        pm_wa_spm;
wire        pm_pc_xpm;
wire        pm_re_new;
wire        pm_wd_new;
reg         lpm_re_l;
reg         lpm_re_h;


`include "OpNumber.v"
wire    op_lpm    = op_decode[B_LPM   ];
wire    op_lpmz   = op_decode[B_LPMZ  ];
wire    op_lpmzi  = op_decode[B_LPMZI ];
wire    op_spm    = op_decode[B_SPM   ];




always @(posedge clock or posedge reset) begin
    if (reset) begin
        pm_addr <= 16'h0000;
        pm_re <= 1'b0;
        pm_we <= 1'b0;
        pm_wdata <= 16'h0000;
    end else begin
        pm_addr <= (pm_re_new | pm_wa_spm) ? pm_addr_new : pm_addr;
        pm_re <= pm_re_new;
        pm_we <= pm_wa_spm;
        pm_wdata <= pm_wd_new ? rf_rdata : pm_wdata;
    end
end

assign  pm_addr_new = pc_new_en ? pc_new : pm_addr_xpm;

assign  pm_addr_xpm = (pm_re_lpm ? {1'b0, rf_rdata[15:1]} : 16'h0000)
                    | (pm_wa_spm ? rf_rdata               : 16'h0000)
                    | (pm_pc_xpm ? pc                     : 16'h0000);

assign  pm_re_lpm   = (op_lpm   & (cycle == 2'd0))
                    | (op_lpmz  & (cycle == 2'd0))
                    | (op_lpmzi & (cycle == 2'd0));

assign  pm_wd_spm   = (op_spm & (cycle == 2'd0));
assign  pm_wa_spm   = (op_spm & (cycle == 2'd1));

assign  pm_pc_xpm   = (op_lpm   & (cycle == 2'd1))
                    | (op_lpmz  & (cycle == 2'd1))
                    | (op_lpmzi & (cycle == 2'd1))
                    | (op_spm   & (cycle == 2'd2));

assign  pm_re_new = (tim_pm_re | skip_en) & ~irq_det;
assign  pm_wd_new = pm_wd_spm & ~skip_en;




always @(posedge clock) begin
    lpm_re_l <= pm_re_lpm & ~rf_rdata[0] & ~skip_en;
    lpm_re_h <= pm_re_lpm &  rf_rdata[0] & ~skip_en;
end

assign  lpm_data = (lpm_re_l ? pm_rdata[7:0]  : 8'h00)
                 | (lpm_re_h ? pm_rdata[15:8] : 8'h00);

assign  lpm_data_en = lpm_re_l | lpm_re_h;

endmodule