data/full_repos/permissive/188868339/src/register/REG_FILE.v
1: b"%Error: data/full_repos/permissive/188868339/src/register/REG_FILE.v:48: Cannot find file containing module: 'REG_EN_8bit'\n REG_EN_8bit U0_Reg_Acc(clk2, rst, ACC_EN, ACC_D, ACC_Q);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188868339/src/register,data/full_repos/permissive/188868339/REG_EN_8bit\n             data/full_repos/permissive/188868339/src/register,data/full_repos/permissive/188868339/REG_EN_8bit.v\n             data/full_repos/permissive/188868339/src/register,data/full_repos/permissive/188868339/REG_EN_8bit.sv\n             REG_EN_8bit\n             REG_EN_8bit.v\n             REG_EN_8bit.sv\n             obj_dir/REG_EN_8bit\n             obj_dir/REG_EN_8bit.v\n             obj_dir/REG_EN_8bit.sv\n%Error: data/full_repos/permissive/188868339/src/register/REG_FILE.v:51: Cannot find file containing module: 'REG_EN_8bit'\n REG_EN_8bit U1_Reg_IDX(clk2, rst, IDX_EN, IDX_D, IDX_Q);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/188868339/src/register/REG_FILE.v:54: Cannot find file containing module: 'REG_EN_8bit'\n REG_EN_8bit U2_Reg_IDY(clk2, rst, IDY_EN, IDY_D, IDY_Q);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/188868339/src/register/REG_FILE.v:57: Cannot find file containing module: 'REG_EN_8bit'\n REG_EN_8bit U3_Reg_SP(clk2, rst, SP_EN, SP_D, SP_Q[7:0]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/188868339/src/register/REG_FILE.v:66: Cannot find file containing module: 'REG_EN_8bit'\n REG_EN_8bit U4_Reg_PC(clk2, rst, PC_EN, PC_INPUT, PC_Q);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/188868339/src/register/REG_FILE.v:70: Cannot find file containing module: 'REG_EN_8bit'\n REG_EN_8bit U5_Reg_SR(clk2, rst, SR_EN, SR_D, SR_Q);\n ^~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module REG_FILE(
	input clk1,
	input clk2,
	input RDY,
	input rst,
	input ACC_EN,
	input IDX_EN,
	input IDY_EN,
	input SP_EN,
	input PC_EN,
	input SR_EN,
	input [7:0] ACC_D,
	input [7:0] IDX_D,
	input [7:0] IDY_D,
	input [7:0] SP_D,
	input [7:0] PC_D,
	input [7:0] SR_D,
	output [7:0] ACC_Q,
	output [7:0] IDX_Q,
	output [7:0] IDY_Q,
	output [15:0] SP_Q,
	output [7:0] PC_Q,
	output [7:0] SR_Q
	
);


	REG_EN_8bit U0_Reg_Acc(clk2, rst, ACC_EN, ACC_D, ACC_Q);
	

	REG_EN_8bit U1_Reg_IDX(clk2, rst, IDX_EN, IDX_D, IDX_Q);
	

	REG_EN_8bit U2_Reg_IDY(clk2, rst, IDY_EN, IDY_D, IDY_Q);
	

	REG_EN_8bit U3_Reg_SP(clk2, rst, SP_EN, SP_D, SP_Q[7:0]);
	assign SP_Q[15:8] = 8'b0000_0001;
	

	reg [7:0] PC_INPUT;
	always @(PC_EN or PC_Q or PC_D) begin
		if(PC_EN) PC_INPUT <= PC_D;
		else PC_INPUT <= PC_Q[7:0]+1'b1;
	end
	REG_EN_8bit U4_Reg_PC(clk2, rst, PC_EN, PC_INPUT, PC_Q);
	


	REG_EN_8bit U5_Reg_SR(clk2, rst, SR_EN, SR_D, SR_Q);
	
endmodule
module REG_FILE(
	input clk1,
	input clk2,
	input RDY,
	input rst,
	input ACC_EN,
	input IDX_EN,
	input IDY_EN,
	input SP_EN,
	input PC_EN,
	input SR_EN,
	input [7:0] ACC_D,
	input [7:0] IDX_D,
	input [7:0] IDY_D,
	input [7:0] SP_D,
	input [7:0] PC_D,
	input [7:0] SR_D,
	output [7:0] ACC_Q,
	output [7:0] IDX_Q,
	output [7:0] IDY_Q,
	output [15:0] SP_Q,
	output [7:0] PC_Q,
	output [7:0] SR_Q
	
);



	REG_EN_8bit U0_Reg_Acc(clk2, rst, ACC_EN, ACC_D, ACC_Q);
	

	REG_EN_8bit U1_Reg_IDX(clk2, rst, IDX_EN, IDX_D, IDX_Q);
	

	REG_EN_8bit U2_Reg_IDY(clk2, rst, IDY_EN, IDY_D, IDY_Q);
	

	REG_EN_8bit U3_Reg_SP(clk2, rst, SP_EN, SP_D, SP_Q[7:0]);
	assign SP_Q[15:8] = 8'b0000_0001;
	

	reg [7:0] PC_INPUT;
	always @(PC_EN or PC_Q or PC_D) begin
		if(PC_EN) PC_INPUT <= PC_D;
		else PC_INPUT <= PC_Q[7:0]+1'b1;
	end
	REG_EN_8bit U4_Reg_PC(clk2, rst, PC_EN, PC_INPUT, PC_Q);
	


	REG_EN_8bit U5_Reg_SR(clk2, rst, SR_EN, SR_D, SR_Q);
	
endmodule