data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc_demultiplexer_custom.sv
data/verilator_xmls/cfa750d8-18b6-4b82-8e5e-d87c2640d379.xml
module sonic_vc_demultiplexer_0_1stage_pipeline  
  #( parameter PAYLOAD_WIDTH = 8 )
   ( input                          clk,
     input 			    reset_n, 
     output reg 		    in_ready,
     input 			    in_valid, 
     input [PAYLOAD_WIDTH-1:0] 	    in_payload,
     input 			    out_ready, 
     output reg 		    out_valid,
     output reg [PAYLOAD_WIDTH-1:0] out_payload      
     );
   
   reg 				    in_ready1;
   
   always @* begin
      
      in_ready = out_ready || ~out_valid;
      



   end
   
   always @ (negedge reset_n, posedge clk) begin
      if (!reset_n) begin
         in_ready1 <= 0;
         out_valid <= 0;
         out_payload <= 0;
      end else begin
         in_ready1 <= out_ready || !out_valid;
         
         if (in_valid) begin
            out_valid <= 1;
         end else if (out_ready) begin
            out_valid <= 0;
         end
         
         if(in_valid && in_ready) begin
            out_payload <= in_payload;
         end
      end
   end

endmodule
module sonic_vc_demultiplexer_0_1stage_pipeline  
  #( parameter PAYLOAD_WIDTH = 8 )
   ( input                          clk,
     input 			    reset_n, 
     output reg 		    in_ready,
     input 			    in_valid, 
     input [PAYLOAD_WIDTH-1:0] 	    in_payload,
     input 			    out_ready, 
     output reg 		    out_valid,
     output reg [PAYLOAD_WIDTH-1:0] out_payload      
     );

   
   reg 				    in_ready1;
   
   always @* begin
      
      in_ready = out_ready || ~out_valid;
      



   end
   
   always @ (negedge reset_n, posedge clk) begin
      if (!reset_n) begin
         in_ready1 <= 0;
         out_valid <= 0;
         out_payload <= 0;
      end else begin
         in_ready1 <= out_ready || !out_valid;
         
         if (in_valid) begin
            out_valid <= 1;
         end else if (out_ready) begin
            out_valid <= 0;
         end
         
         if(in_valid && in_ready) begin
            out_payload <= in_payload;
         end
      end
   end

endmodule