data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v:5: Unsupported: Ignoring delay on this delayed statement.\n always #5 clock <= ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v:28: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("testdp.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v:29: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/datapath_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module datapath_tb;
	
	reg	clock	= 1;
	always	#5	clock	<= ~clock;
	
	reg	reset	= 0;
	
	reg	[31:0]	data_to;
	reg	[1:0]	owner_in;
	
	wire	[31:0]	data_from;
	wire	[1:0]	owner_out;
	wire	ready;
	
	reg	start	= 0;
	reg	suspend	= 0;
	reg	read	= 0;
	reg	write	= 0;
	
	wire	ddr_send;
	wire	[31:0]	ddr_data_to;
	reg	[31:0]	ddr_data_from;
	
	
	initial begin : Sim
		$write ("%% ");
		$dumpfile ("testdp.vcd");
		$dumpvars;
		
		#5

		owner_in	<= 1;
		start		<= 1;
		
		#10
		start		<= 0;
		
		#10
		read		<= 1;
		
		#10
		read		<= 0;
		
		#20
		start		<= 1;
		
		#10
		start		<= 0;
		
		#10
		write		<= 1;
		data_to		<= 1298;
		ddr_data_from	<= 2543;
		
		#10
		write		<= 0;
		data_to		<= 'bx;
		ddr_data_from	<= 'bx;
		
		#50
		$finish;
	end
	
	
	datapath DP0 (
		.clock_i	(clock),
		.reset_i	(reset),
		
		.usr_data_i	(data_to),
		.usr_owner_i	(owner_in),
		.usr_data_o	(data_from),
		.usr_owner_o	(owner_out),
		.usr_ready_o	(ready),
		
		.ctl_start_i	(start),
		.ctl_block_i	(block),
		.ctl_suspend_i	(suspend),
		.ctl_read_i	(read),
		.ctl_write_i	(write),
		
		.ddr_send_o	(ddr_send),
		.ddr_data_o	(ddr_data_to),
		.ddr_data_i	(ddr_data_from)
	);
	
endmodule
module datapath_tb;

	
	reg	clock	= 1;
	always	#5	clock	<= ~clock;
	
	reg	reset	= 0;
	
	reg	[31:0]	data_to;
	reg	[1:0]	owner_in;
	
	wire	[31:0]	data_from;
	wire	[1:0]	owner_out;
	wire	ready;
	
	reg	start	= 0;
	reg	suspend	= 0;
	reg	read	= 0;
	reg	write	= 0;
	
	wire	ddr_send;
	wire	[31:0]	ddr_data_to;
	reg	[31:0]	ddr_data_from;
	
	
	initial begin : Sim
		$write ("%% ");
		$dumpfile ("testdp.vcd");
		$dumpvars;
		
		#5

		owner_in	<= 1;
		start		<= 1;
		
		#10
		start		<= 0;
		
		#10
		read		<= 1;
		
		#10
		read		<= 0;
		
		#20
		start		<= 1;
		
		#10
		start		<= 0;
		
		#10
		write		<= 1;
		data_to		<= 1298;
		ddr_data_from	<= 2543;
		
		#10
		write		<= 0;
		data_to		<= 'bx;
		ddr_data_from	<= 'bx;
		
		#50
		$finish;
	end
	
	
	datapath DP0 (
		.clock_i	(clock),
		.reset_i	(reset),
		
		.usr_data_i	(data_to),
		.usr_owner_i	(owner_in),
		.usr_data_o	(data_from),
		.usr_owner_o	(owner_out),
		.usr_ready_o	(ready),
		
		.ctl_start_i	(start),
		.ctl_block_i	(block),
		.ctl_suspend_i	(suspend),
		.ctl_read_i	(read),
		.ctl_write_i	(write),
		
		.ddr_send_o	(ddr_send),
		.ddr_data_o	(ddr_data_to),
		.ddr_data_i	(ddr_data_from)
	);
	
endmodule