data/full_repos/permissive/157550807/src/idvr_shift.v
data/verilator_xmls/85bbd914-c47a-4b78-8341-a6372e34627b.xml
module idvr_shift #(
    parameter W=1,
    parameter TW=5
) (
    input  [W-1:0]  I,
    input  [TW-1:0] shamt,
    output [W-1:0]  O,
    output          Err,
    input  [1:0]    S
);


    reg [W-1:0] wO;
    always @(*) begin : switch
        case (S)
            2'b00 : wO = I << shamt;
            2'b01 : wO = I >> shamt;
            2'b10 : wO = I;
            2'b11 : wO = $signed(I) >>> shamt;
        endcase
    end
    assign O = wO;
    assign Err = (S == 2'b10);
    

endmodule
module idvr_shift #(
    parameter W=1,
    parameter TW=5
) (
    input  [W-1:0]  I,
    input  [TW-1:0] shamt,
    output [W-1:0]  O,
    output          Err,
    input  [1:0]    S
);



    reg [W-1:0] wO;
    always @(*) begin : switch
        case (S)
            2'b00 : wO = I << shamt;
            2'b01 : wO = I >> shamt;
            2'b10 : wO = I;
            2'b11 : wO = $signed(I) >>> shamt;
        endcase
    end
    assign O = wO;
    assign Err = (S == 2'b10);
    

endmodule