data/full_repos/permissive/136510272/projects/05_nes/nes.v
 line:214: before: ")"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/136510272/projects/05_nes/nes.v:99: Signal definition not found, creating implicitly: \'CLKCPU\'\nalways @(posedge clk) DSRAM <= CLKCPU;\n                               ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/136510272/projects/05_nes/nes.v:104: Cannot find file containing module: \'cpu\'\ncpu C6502(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/projects/05_nes,data/full_repos/permissive/136510272/cpu\n             data/full_repos/permissive/136510272/projects/05_nes,data/full_repos/permissive/136510272/cpu.v\n             data/full_repos/permissive/136510272/projects/05_nes,data/full_repos/permissive/136510272/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: data/full_repos/permissive/136510272/projects/05_nes/nes.v:137: Cannot find file containing module: \'ppu\'\nppu PPU(\n^~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/nes.v:199: Cannot find file containing module: \'pll\'\npll PLL(\n^~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/nes.v:209: Cannot find file containing module: \'uart\'\nuart UART(\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/nes.v:217: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance nes\nreg [7:0]  prg_idata    = 1\'b0;  \n                          ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/nes.v:218: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance nes\nreg [14:0] prg_addr     = 1\'b0;  \n                          ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/nes.v:235: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                              : ... In instance nes\n        prg_addr   <= 16\'h0000;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/nes.v:241: Operator EQ expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'prg_addr\' generates 15 bits.\n                                                                              : ... In instance nes\n        if (prg_addr == (prg_len - 2)) begin\n                     ^~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/nes.v:262: Cannot find file containing module: \'PS2_Controller\'\nPS2_Controller Keyboard(\n^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/05_nes/nes.v:300: Operator CASE expects 8 bits on the Case expression, but Case expression\'s SEL generates 7 bits.\n                                                                              : ... In instance nes\n            case (ps2_data[6:0])\n            ^~~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/nes.v:323: Cannot find file containing module: \'romchr\'\nromchr CHRROM(\n^~~~~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/nes.v:337: Cannot find file containing module: \'vram\'\nvram VRAM(\n^~~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/nes.v:353: Cannot find file containing module: \'rom\'\nrom ROM(\n^~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/nes.v:367: Cannot find file containing module: \'sram\'\nsram SRAM(\n^~~~\n%Error: data/full_repos/permissive/136510272/projects/05_nes/nes.v:382: Cannot find file containing module: \'oam\'\noam OAM(\n^~~\n%Error: Exiting due to 10 error(s), 6 warning(s)\n'
module nes(




    input   wire        clk,


    output  reg [3:0]   led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);


wire [7:0] DEBUGCPU;
wire [7:0] DEBUGPPU;
reg [31:0] Timer;

always @(posedge clk) led <= Joy1[7:4];





wire [15:0] address;
wire [15:0] eawr;
wire [ 7:0] dout;
wire        mreq;
wire        NMI;
wire        DMA;
wire        OAMW;


wire [7:0]  Dram;
wire [7:0]  Drom;
wire [7:0]  Dppu;
reg         DVRAM = 1'b0;
reg         DSRAM = 1'b0;
reg         prg_led;


   
wire [15:0] curaddr = DMA ? WADDR : address;

wire        sram_write = eawr     < 16'h2000;
wire        sram_route = curaddr  < 16'h2000;
wire        ppu_route  = curaddr >= 16'h2000 && curaddr <= 16'h4017;
wire        srom_route = curaddr >= 16'h8000;

wire [7:0]  din = sram_route ? Dram :
                  ppu_route  ? Dppu :
                  srom_route ? Drom : 8'h00;

always @(posedge clk) DSRAM <= CLKCPU;
always @(posedge clk) DVRAM <= WVREQ;
                  


cpu C6502(
    
    .RESET  ( prg_enable ),
    .CLK    ( CLKCPU ),
    .CE     ( !DMA ),
    .ADDR   ( address ),
    .DIN    ( din ),
    .DOUT   ( dout ),
    .EAWR   ( eawr ),
    .WREQ   ( wreq ),
    .RD     ( RD ),
    .NMI    ( NMI ),
    .DEBUG  ( DEBUGCPU ),
    .DKEY   ( keys[1:0] )
);



reg  [1:0]  div = 2'b00; always @(posedge clk) div <= div + 1'b1;

wire [10:0] addr_vrd;
wire [12:0] addr_frd;
wire [ 7:0] data_vrd;
wire [ 7:0] data_frd;
wire [ 7:0] FIN;
wire [ 7:0] VIN;
wire [ 7:0] WDATA;
wire [15:0] WADDR;
wire        WVREQ;
wire        RD;
wire [7:0]  SAR;
wire [7:0]  SRD;

ppu PPU(
    
    .CLK25  (div[1]),
    .RESET  (prg_enable),
    

    .red    (vga_red),
    .green  (vga_green),
    .blue   (vga_blue),
    .hs     (vga_hs),
    .vs     (vga_vs),
    

    .CLKPPU (CLKPPU),
    .CLKCPU (CLKCPU),
    

    .vaddr  (addr_vrd),
    .vdata  (data_vrd),
    

    .ea     (eawr),
    .din    (dout),
    .RD     (RD),
    .WREQ   (wreq),
    .DOUT   (Dppu),
    .VIN    (VIN),
    .WVREQ  (WVREQ),
    .WADDR  (WADDR),
    .WDATA  (WDATA),
    .NMI    (NMI),
    

    .DMA    (DMA),
    .OAMW   (OAMW),
    .DATAIN (din),
    .SPIN   (spin),
    .SAR    (SAR),
    .SRD    (SRD),
    

    .faddr  (addr_frd),
    .fdata  (data_frd),
    .FIN    (FIN),
    .DEBUG  (DEBUGPPU),
    

    .JOY1   (Joy1),
    .JOY2   (Joy2)
    
);




wire [7:0]  rx_byte;
wire        locked;
wire        clock_25;
wire        clock_12;
wire        clock_6;
wire        rx_ready;

pll PLL(

    .clk        (clk),
    .locked     (locked),
    .c0         (clock_25),
    .c1         (clock_12),
    .c2         (clock_6)

);

uart UART(
    .clk12      (clock_12),
    .rx         (ftdi_rx),
    .rx_byte    (rx_byte),
    .rx_ready   (rx_ready),
);

parameter  prg_len      = 32768;
reg [7:0]  prg_idata    = 1'b0;
reg [14:0] prg_addr     = 1'b0;
reg        prg_wren     = 1'b0;
reg        prg_enable   = 1'b0;
reg [1:0]  prg_negedge  = 2'b00;


always @(posedge clk) prg_negedge <= {prg_negedge[0], rx_ready};


always @(posedge rx_ready) begin

    prg_idata <= rx_byte;

    if (prg_enable == 1'b0) begin

        prg_enable <= 1'b1;
        prg_wren   <= 1'b1;
        prg_addr   <= 16'h0000;
        prg_led    <= 1'b1;

    end
    else begin

        if (prg_addr == (prg_len - 2)) begin
            prg_enable <= 1'b0;
            prg_wren   <= 1'b0;
            prg_led    <= 1'b0;
        end

        prg_addr <= prg_addr + 1'b1;

    end

end




reg         kbd_reset = 1'b0;
wire        ps2_command_was_sent;
wire        ps2_error_communication_timed_out;
wire [7:0]  ps2_data;
wire        ps2_data_clk;

PS2_Controller Keyboard(


    .CLOCK_50       (div[0]),
	.reset          (1'b0),
	.the_command    (1'b0),
	.send_command   (1'b0),


	.PS2_CLK(ps2_keyb[1]),
 	.PS2_DAT(ps2_keyb[0]),


	.command_was_sent  (ps2_command_was_sent),
	.error_communication_timed_out (ps2_error_communication_timed_out),


	.received_data      (ps2_data),
	.received_data_en   (ps2_data_clk)

);


reg [7:0] Joy1 = 8'h00;
reg [7:0] Joy2 = 8'h00;

reg key_press = 1'b1;

always @(posedge div[0]) begin

    if (ps2_data_clk) begin
    

        if (ps2_data == 8'hF0) begin               
            key_press <= 1'b0; 
            
        end else begin
            
            case (ps2_data[6:0])
            
8'h2D: Joy1[0] <= key_press;
8'h2C: Joy1[1] <= key_press; 
8'h2E: Joy1[2] <= key_press;
8'h2F: Joy1[3] <= key_press;                
8'h48: Joy1[4] <= key_press;
8'h50: Joy1[5] <= key_press;
8'h4B: Joy1[6] <= key_press;
8'h4D: Joy1[7] <= key_press;
                
            endcase
        
            key_press <= 1'b1;
        end
    
    end

end




romchr CHRROM(


    .clock   (clk),
    .addr_rd (addr_frd),
    .q       (data_frd),
    

    .addr_wr (WADDR[12:0]),
    .qw      (FIN)

);


vram VRAM(


    .clock   (clk),
    .addr_rd (addr_vrd),
    .q       (data_vrd),
    

    .addr_wr (WADDR[10:0]),
    .data_wr (WDATA),
    .wren    ({DVRAM, WVREQ} == 2'b11),
    .qw      (VIN),

);


rom ROM(

    .clock    (clk),
    .addr_rd  (curaddr[14:0]),
    .q        (Drom),
        

    .addr_wr  (prg_addr[14:0]),
    .data_wr  (prg_idata),
    .wren     (prg_wren && prg_negedge == 2'b10),

);


sram SRAM(


    .clock    (clk),
    .addr_rd  (curaddr[10:0]),
    .q        (Dram),
    

    .addr_wr  (eawr[10:0]),
    .data_wr  (dout),
    .wren     ({DSRAM, CLKCPU} == 2'b10 && wreq && sram_write),

);


oam OAM(


    .clock   (clk),
    .addr_rd (SAR),
    .q       (SRD),
    

    .addr_wr (WADDR[7:0]),
    .data_wr (WDATA),
    .wren    (OAMW),
    .qw      (spin)

);

endmodule
module nes(




    input   wire        clk,


    output  reg [3:0]   led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);



wire [7:0] DEBUGCPU;
wire [7:0] DEBUGPPU;
reg [31:0] Timer;

always @(posedge clk) led <= Joy1[7:4];





wire [15:0] address;
wire [15:0] eawr;
wire [ 7:0] dout;
wire        mreq;
wire        NMI;
wire        DMA;
wire        OAMW;


wire [7:0]  Dram;
wire [7:0]  Drom;
wire [7:0]  Dppu;
reg         DVRAM = 1'b0;
reg         DSRAM = 1'b0;
reg         prg_led;


   
wire [15:0] curaddr = DMA ? WADDR : address;

wire        sram_write = eawr     < 16'h2000;
wire        sram_route = curaddr  < 16'h2000;
wire        ppu_route  = curaddr >= 16'h2000 && curaddr <= 16'h4017;
wire        srom_route = curaddr >= 16'h8000;

wire [7:0]  din = sram_route ? Dram :
                  ppu_route  ? Dppu :
                  srom_route ? Drom : 8'h00;

always @(posedge clk) DSRAM <= CLKCPU;
always @(posedge clk) DVRAM <= WVREQ;
                  


cpu C6502(
    
    .RESET  ( prg_enable ),
    .CLK    ( CLKCPU ),
    .CE     ( !DMA ),
    .ADDR   ( address ),
    .DIN    ( din ),
    .DOUT   ( dout ),
    .EAWR   ( eawr ),
    .WREQ   ( wreq ),
    .RD     ( RD ),
    .NMI    ( NMI ),
    .DEBUG  ( DEBUGCPU ),
    .DKEY   ( keys[1:0] )
);



reg  [1:0]  div = 2'b00; always @(posedge clk) div <= div + 1'b1;

wire [10:0] addr_vrd;
wire [12:0] addr_frd;
wire [ 7:0] data_vrd;
wire [ 7:0] data_frd;
wire [ 7:0] FIN;
wire [ 7:0] VIN;
wire [ 7:0] WDATA;
wire [15:0] WADDR;
wire        WVREQ;
wire        RD;
wire [7:0]  SAR;
wire [7:0]  SRD;

ppu PPU(
    
    .CLK25  (div[1]),
    .RESET  (prg_enable),
    

    .red    (vga_red),
    .green  (vga_green),
    .blue   (vga_blue),
    .hs     (vga_hs),
    .vs     (vga_vs),
    

    .CLKPPU (CLKPPU),
    .CLKCPU (CLKCPU),
    

    .vaddr  (addr_vrd),
    .vdata  (data_vrd),
    

    .ea     (eawr),
    .din    (dout),
    .RD     (RD),
    .WREQ   (wreq),
    .DOUT   (Dppu),
    .VIN    (VIN),
    .WVREQ  (WVREQ),
    .WADDR  (WADDR),
    .WDATA  (WDATA),
    .NMI    (NMI),
    

    .DMA    (DMA),
    .OAMW   (OAMW),
    .DATAIN (din),
    .SPIN   (spin),
    .SAR    (SAR),
    .SRD    (SRD),
    

    .faddr  (addr_frd),
    .fdata  (data_frd),
    .FIN    (FIN),
    .DEBUG  (DEBUGPPU),
    

    .JOY1   (Joy1),
    .JOY2   (Joy2)
    
);




wire [7:0]  rx_byte;
wire        locked;
wire        clock_25;
wire        clock_12;
wire        clock_6;
wire        rx_ready;

pll PLL(

    .clk        (clk),
    .locked     (locked),
    .c0         (clock_25),
    .c1         (clock_12),
    .c2         (clock_6)

);

uart UART(
    .clk12      (clock_12),
    .rx         (ftdi_rx),
    .rx_byte    (rx_byte),
    .rx_ready   (rx_ready),
);

parameter  prg_len      = 32768;
reg [7:0]  prg_idata    = 1'b0;
reg [14:0] prg_addr     = 1'b0;
reg        prg_wren     = 1'b0;
reg        prg_enable   = 1'b0;
reg [1:0]  prg_negedge  = 2'b00;


always @(posedge clk) prg_negedge <= {prg_negedge[0], rx_ready};


always @(posedge rx_ready) begin

    prg_idata <= rx_byte;

    if (prg_enable == 1'b0) begin

        prg_enable <= 1'b1;
        prg_wren   <= 1'b1;
        prg_addr   <= 16'h0000;
        prg_led    <= 1'b1;

    end
    else begin

        if (prg_addr == (prg_len - 2)) begin
            prg_enable <= 1'b0;
            prg_wren   <= 1'b0;
            prg_led    <= 1'b0;
        end

        prg_addr <= prg_addr + 1'b1;

    end

end




reg         kbd_reset = 1'b0;
wire        ps2_command_was_sent;
wire        ps2_error_communication_timed_out;
wire [7:0]  ps2_data;
wire        ps2_data_clk;

PS2_Controller Keyboard(


    .CLOCK_50       (div[0]),
	.reset          (1'b0),
	.the_command    (1'b0),
	.send_command   (1'b0),


	.PS2_CLK(ps2_keyb[1]),
 	.PS2_DAT(ps2_keyb[0]),


	.command_was_sent  (ps2_command_was_sent),
	.error_communication_timed_out (ps2_error_communication_timed_out),


	.received_data      (ps2_data),
	.received_data_en   (ps2_data_clk)

);


reg [7:0] Joy1 = 8'h00;
reg [7:0] Joy2 = 8'h00;

reg key_press = 1'b1;

always @(posedge div[0]) begin

    if (ps2_data_clk) begin
    

        if (ps2_data == 8'hF0) begin               
            key_press <= 1'b0; 
            
        end else begin
            
            case (ps2_data[6:0])
            
8'h2D: Joy1[0] <= key_press;
8'h2C: Joy1[1] <= key_press; 
8'h2E: Joy1[2] <= key_press;
8'h2F: Joy1[3] <= key_press;                
8'h48: Joy1[4] <= key_press;
8'h50: Joy1[5] <= key_press;
8'h4B: Joy1[6] <= key_press;
8'h4D: Joy1[7] <= key_press;
                
            endcase
        
            key_press <= 1'b1;
        end
    
    end

end




romchr CHRROM(


    .clock   (clk),
    .addr_rd (addr_frd),
    .q       (data_frd),
    

    .addr_wr (WADDR[12:0]),
    .qw      (FIN)

);


vram VRAM(


    .clock   (clk),
    .addr_rd (addr_vrd),
    .q       (data_vrd),
    

    .addr_wr (WADDR[10:0]),
    .data_wr (WDATA),
    .wren    ({DVRAM, WVREQ} == 2'b11),
    .qw      (VIN),

);


rom ROM(

    .clock    (clk),
    .addr_rd  (curaddr[14:0]),
    .q        (Drom),
        

    .addr_wr  (prg_addr[14:0]),
    .data_wr  (prg_idata),
    .wren     (prg_wren && prg_negedge == 2'b10),

);


sram SRAM(


    .clock    (clk),
    .addr_rd  (curaddr[10:0]),
    .q        (Dram),
    

    .addr_wr  (eawr[10:0]),
    .data_wr  (dout),
    .wren     ({DSRAM, CLKCPU} == 2'b10 && wreq && sram_write),

);


oam OAM(


    .clock   (clk),
    .addr_rd (SAR),
    .q       (SRD),
    

    .addr_wr (WADDR[7:0]),
    .data_wr (WDATA),
    .wren    (OAMW),
    .qw      (spin)

);

endmodule