data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v
 line:189: before: "("
1: b'%Error: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:203: Cannot find file containing module: \'aes_core\'\n  aes_core aes(\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194918293/src/rtl,data/full_repos/permissive/194918293/aes_core\n             data/full_repos/permissive/194918293/src/rtl,data/full_repos/permissive/194918293/aes_core.v\n             data/full_repos/permissive/194918293/src/rtl,data/full_repos/permissive/194918293/aes_core.sv\n             aes_core\n             aes_core.v\n             aes_core.sv\n             obj_dir/aes_core\n             obj_dir/aes_core.v\n             obj_dir/aes_core.sv\n%Error: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:221: Cannot find file containing module: \'cmac_core\'\n  cmac_core cmac(\n  ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:255: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_IDLE\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n          core_ctrl_reg  <= CTRL_IDLE;\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:386: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_IDLE\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n      core_ctrl_new   = CTRL_IDLE;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:404: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_S2V_INIT1\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n                core_ctrl_new   = CTRL_S2V_INIT1;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:422: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_IDLE\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n                core_ctrl_new = CTRL_IDLE;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:434: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_S2V_FIRST1\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n                core_ctrl_new = CTRL_S2V_FIRST1;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:447: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_IDLE\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n                core_ctrl_new = CTRL_IDLE;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:457: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_S2V_NEXT1\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n            core_ctrl_new = CTRL_S2V_NEXT1;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:469: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_IDLE\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n                core_ctrl_new = CTRL_IDLE;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:482: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_S2V_FINAL1\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n            core_ctrl_new   = CTRL_S2V_FINAL1;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:497: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_IDLE\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n                core_ctrl_new = CTRL_IDLE;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:509: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_S2V_FINALIZE1\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n                core_ctrl_new   = CTRL_S2V_FINALIZE1;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:514: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_S2V_FINALIZE3\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n                core_ctrl_new = CTRL_S2V_FINALIZE3;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:528: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_S2V_FINALIZE2\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n                core_ctrl_new   = CTRL_S2V_FINALIZE2;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:544: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_IDLE\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n                core_ctrl_new = CTRL_IDLE;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:555: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_IDLE\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n            core_ctrl_new = CTRL_IDLE;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:563: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_CTR_INIT1\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n            core_ctrl_new = CTRL_CTR_INIT1;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:574: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_IDLE\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n                core_ctrl_new = CTRL_IDLE;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:582: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_CTR_NEXT1\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n            core_ctrl_new = CTRL_CTR_NEXT1;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:595: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'CTRL_IDLE\' generates 5 bits.\n                                                                               : ... In instance aes_siv_core\n                core_ctrl_new = CTRL_IDLE;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/194918293/src/rtl/aes_siv_core.v:389: Operator CASE expects 5 bits on the Case expression, but Case expression\'s VARREF \'core_ctrl_reg\' generates 4 bits.\n                                                                               : ... In instance aes_siv_core\n      case (core_ctrl_reg)\n      ^~~~\n%Error: Exiting due to 2 error(s), 20 warning(s)\n'
function [127 : 0] double(input [127 : 0] op);
    begin
      if (op[127])
        double = {op[126 : 0], 1'h0} ^ 128'h87;
      else
        double = {op[126 : 0], 1'h0};
    end
  endfunction
function [127 : 0] double(input [127 : 0] op);

    begin
      if (op[127])
        double = {op[126 : 0], 1'h0} ^ 128'h87;
      else
        double = {op[126 : 0], 1'h0};
    end
  endfunction