data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v
1: b"%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:22: Cannot find file containing module: 'NOT'\n  NOT _14_ (\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-02/wrr,data/full_repos/permissive/129155059/NOT\n             data/full_repos/permissive/129155059/proyecto-02/wrr,data/full_repos/permissive/129155059/NOT.v\n             data/full_repos/permissive/129155059/proyecto-02/wrr,data/full_repos/permissive/129155059/NOT.sv\n             NOT\n             NOT.v\n             NOT.sv\n             obj_dir/NOT\n             obj_dir/NOT.v\n             obj_dir/NOT.sv\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:26: Cannot find file containing module: 'NOR'\n  NOR _15_ (\n  ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:31: Cannot find file containing module: 'NOT'\n  NOT _16_ (\n  ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:35: Cannot find file containing module: 'NAND'\n  NAND _17_ (\n  ^~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:40: Cannot find file containing module: 'NAND'\n  NAND _18_ (\n  ^~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:45: Cannot find file containing module: 'NOR'\n  NOR _19_ (\n  ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:50: Cannot find file containing module: 'NOT'\n  NOT _20_ (\n  ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:54: Cannot find file containing module: 'NOT'\n  NOT _21_ (\n  ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:58: Cannot find file containing module: 'NOR'\n  NOR _22_ (\n  ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:63: Cannot find file containing module: 'NOT'\n  NOT _23_ (\n  ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:67: Cannot find file containing module: 'NOR'\n  NOR _24_ (\n  ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:72: Cannot find file containing module: 'NOR'\n  NOR _25_ (\n  ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:77: Cannot find file containing module: 'NOR'\n  NOR _26_ (\n  ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:82: Cannot find file containing module: 'NOR'\n  NOR _27_ (\n  ^~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/mux4_1_synth.v:87: Cannot find file containing module: 'NOR'\n  NOR _28_ (\n  ^~~\n%Error: Exiting due to 15 error(s)\n"
module mux4_1_synth(VC_id, Data_Word, reset, data_out);
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  input [3:0] Data_Word;
  input [1:0] VC_id;
  output data_out;
  input reset;
  NOT _14_ (
    .A(reset),
    .Y(_13_)
  );
  NOR _15_ (
    .A(Data_Word[2]),
    .B(VC_id[0]),
    .Y(_00_)
  );
  NOT _16_ (
    .A(Data_Word[3]),
    .Y(_01_)
  );
  NAND _17_ (
    .A(_01_),
    .B(VC_id[0]),
    .Y(_02_)
  );
  NAND _18_ (
    .A(_02_),
    .B(VC_id[1]),
    .Y(_03_)
  );
  NOR _19_ (
    .A(_03_),
    .B(_00_),
    .Y(_04_)
  );
  NOT _20_ (
    .A(VC_id[0]),
    .Y(_05_)
  );
  NOT _21_ (
    .A(Data_Word[1]),
    .Y(_06_)
  );
  NOR _22_ (
    .A(_06_),
    .B(_05_),
    .Y(_07_)
  );
  NOT _23_ (
    .A(Data_Word[0]),
    .Y(_08_)
  );
  NOR _24_ (
    .A(_08_),
    .B(VC_id[0]),
    .Y(_09_)
  );
  NOR _25_ (
    .A(_09_),
    .B(_07_),
    .Y(_10_)
  );
  NOR _26_ (
    .A(_10_),
    .B(VC_id[1]),
    .Y(_11_)
  );
  NOR _27_ (
    .A(_11_),
    .B(_04_),
    .Y(_12_)
  );
  NOR _28_ (
    .A(_12_),
    .B(_13_),
    .Y(data_out)
  );
endmodule
module mux4_1_synth(VC_id, Data_Word, reset, data_out);

  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  input [3:0] Data_Word;
  input [1:0] VC_id;
  output data_out;
  input reset;
  NOT _14_ (
    .A(reset),
    .Y(_13_)
  );
  NOR _15_ (
    .A(Data_Word[2]),
    .B(VC_id[0]),
    .Y(_00_)
  );
  NOT _16_ (
    .A(Data_Word[3]),
    .Y(_01_)
  );
  NAND _17_ (
    .A(_01_),
    .B(VC_id[0]),
    .Y(_02_)
  );
  NAND _18_ (
    .A(_02_),
    .B(VC_id[1]),
    .Y(_03_)
  );
  NOR _19_ (
    .A(_03_),
    .B(_00_),
    .Y(_04_)
  );
  NOT _20_ (
    .A(VC_id[0]),
    .Y(_05_)
  );
  NOT _21_ (
    .A(Data_Word[1]),
    .Y(_06_)
  );
  NOR _22_ (
    .A(_06_),
    .B(_05_),
    .Y(_07_)
  );
  NOT _23_ (
    .A(Data_Word[0]),
    .Y(_08_)
  );
  NOR _24_ (
    .A(_08_),
    .B(VC_id[0]),
    .Y(_09_)
  );
  NOR _25_ (
    .A(_09_),
    .B(_07_),
    .Y(_10_)
  );
  NOR _26_ (
    .A(_10_),
    .B(VC_id[1]),
    .Y(_11_)
  );
  NOR _27_ (
    .A(_11_),
    .B(_04_),
    .Y(_12_)
  );
  NOR _28_ (
    .A(_12_),
    .B(_13_),
    .Y(data_out)
  );
endmodule