data/full_repos/permissive/212947157/rtl/svga/PIXEL_DISPLAY.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-IMPLICIT: data/full_repos/permissive/212947157/rtl/svga/PIXEL_DISPLAY.v:273: Signal definition not found, creating implicitly: \'palette_bit_graph_bw\'\n                                                                                    : ... Suggested alternative: \'palette_bit_graph\'\nassign palette_bit_graph_bw  = pixel_2p_1bit_half;\n       ^~~~~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212947157/rtl/svga/PIXEL_DISPLAY.v:101: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 13 bits.\n                                                                                 : ... In instance PIXEL_DISPLAY\n    vram_addr <= {4\'b0,char_line[3:0], char_column[4:0]};\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/212947157/rtl/svga/PIXEL_DISPLAY.v:192: Operator ADD expects 14 bits on the RHS, but RHS\'s REPLICATE generates 11 bits.\n                                                                                 : ... In instance PIXEL_DISPLAY\n   vram_addr <= graph_line_a84 + {graph_pixel[9:3],4\'h0};\n                               ^\n%Error: data/full_repos/permissive/212947157/rtl/svga/PIXEL_DISPLAY.v:308: Cannot find file containing module: \'CHAR_GEN\'\nCHAR_GEN CHAR_GEN\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212947157/rtl/svga,data/full_repos/permissive/212947157/CHAR_GEN\n             data/full_repos/permissive/212947157/rtl/svga,data/full_repos/permissive/212947157/CHAR_GEN.v\n             data/full_repos/permissive/212947157/rtl/svga,data/full_repos/permissive/212947157/CHAR_GEN.sv\n             CHAR_GEN\n             CHAR_GEN.v\n             CHAR_GEN.sv\n             obj_dir/CHAR_GEN\n             obj_dir/CHAR_GEN.v\n             obj_dir/CHAR_GEN.sv\n%Error: data/full_repos/permissive/212947157/rtl/svga/PIXEL_DISPLAY.v:320: Cannot find file containing module: \'PIXEL_GEN\'\nPIXEL_GEN PIXEL_GEN\n^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module PIXEL_DISPLAY (
	pixel_clock,
	reset,

	show_border,


	ag,

	css,


	char_column,
	char_line,
	subchar_line,
	subchar_pixel,


	graph_pixel,
	graph_line_2x,
	graph_line_3x,
	graph_line_a84,


	vram_rd_enable,
	vram_addr,
	vram_data,


	vga_red,
	vga_green,
	vga_blue
);

input					pixel_clock;
input					reset;

input					show_border;


input					ag;

input					css;


input			[6:0]	char_column;
input			[6:0]	char_line;
input			[4:0]	subchar_line;
input			[3:0]	subchar_pixel;


input			[9:0]	graph_pixel;
input			[9:0]	graph_line_2x;
input			[9:0]	graph_line_3x;
input			[13:0]	graph_line_a84;

output					vram_rd_enable;
output	reg		[13:0]	vram_addr;
input			[7:0] 	vram_data;

output			[7:0]	vga_red;
output			[7:0]	vga_green;
output			[7:0]	vga_blue;









wire				pixel_on;





wire	[1:0]		pixel_8p_2bit;
wire	[1:0]		pixel_4p_2bit;
wire				pixel_4p_1bit;
wire				pixel_2p_1bit;
wire				pixel_2p_1bit_half;

reg		[7:0] 		latched_vram_data;


reg		[7:0] 		latched_palette_data;

assign vram_rd_enable = pixel_clock;

reg		[23:0] latched_vga_rgb;
wire	[23:0] vga_rgb;



always @ (posedge pixel_clock) begin
	if(ag==1'b0)
	begin
			if(subchar_pixel==4'b0001)
				vram_addr <= {4'b0,char_line[3:0], char_column[4:0]};

			if(subchar_pixel==4'b0011)
				latched_vram_data <= vram_data;
			if(graph_pixel[3:0]==4'b0110)
				latched_palette_data <= latched_vram_data;
	end
	else
	begin





		if(graph_pixel[2:0]==3'b001)
			vram_addr <= graph_line_a84 + {graph_pixel[9:3],4'h0};

		if(graph_pixel[2:0]==3'b011)
			latched_vram_data <= vram_data;

	end
	latched_vga_rgb <= vga_rgb;
end




wire [2:0]	palette_bit_graph;


wire [23:0]	palette_rgb_border =	(~ag)	?	24'h000000:
												24'h101010;

wire [23:0] palette_rgb_pixel = 24'h000000;
wire [23:0] palette_rgb_background = 24'h07ff00;














assign palette_bit_graph		=	(~ag)			?	latched_palette_data[6:4]				:
														{css, pixel_2p_1bit_half, pixel_2p_1bit_half	}	;

wire [23:0] palette_rgb_graph =	(palette_bit_graph==3'b000) ?	24'h07ff00 :
								(palette_bit_graph==3'b001) ?	24'hffff00 :
								(palette_bit_graph==3'b010) ?	24'h3b08ff :
								(palette_bit_graph==3'b011) ?	24'hcc003b :
								(palette_bit_graph==3'b100) ?	24'hffffff :
								(palette_bit_graph==3'b101) ?	24'h07e399 :
								(palette_bit_graph==3'b110) ?	24'hff1cff :
																24'hff8100 ;



assign palette_bit_graph_bw		=	pixel_2p_1bit_half;

wire [23:0] palette_rgb_graph_bw	=	(palette_bit_graph_bw) ?	24'h07ff00 :
																	24'h000000;








assign vga_rgb =	(show_border)	? palette_rgb_border :

					(ag)			? palette_rgb_graph_bw :
					(~pixel_on)		? palette_rgb_pixel :
					(latched_palette_data[7])	? palette_rgb_graph : palette_rgb_background;

assign vga_red = latched_vga_rgb[23:16];
assign vga_green = latched_vga_rgb[15:8];
assign vga_blue = latched_vga_rgb[7:0];




CHAR_GEN CHAR_GEN
(
	.reset(reset),

	.char_code(latched_vram_data),
	.subchar_line(subchar_line),
	.subchar_pixel(subchar_pixel),

	.pixel_clock(pixel_clock),
	.pixel_on(pixel_on)
);

PIXEL_GEN PIXEL_GEN
(
	.reset(reset),

	.pixel_code(latched_vram_data),
	.graph_pixel(graph_pixel),

	.pixel_clock(pixel_clock),

	.pixel_8p_2bit(pixel_8p_2bit),
	.pixel_4p_2bit(pixel_4p_2bit),
	.pixel_4p_1bit(pixel_4p_1bit),
	.pixel_2p_1bit(pixel_2p_1bit),
	.pixel_2p_1bit_half(pixel_2p_1bit_half)
);

endmodule
module PIXEL_DISPLAY (
	pixel_clock,
	reset,

	show_border,


	ag,

	css,


	char_column,
	char_line,
	subchar_line,
	subchar_pixel,


	graph_pixel,
	graph_line_2x,
	graph_line_3x,
	graph_line_a84,


	vram_rd_enable,
	vram_addr,
	vram_data,


	vga_red,
	vga_green,
	vga_blue
);


input					pixel_clock;
input					reset;

input					show_border;


input					ag;

input					css;


input			[6:0]	char_column;
input			[6:0]	char_line;
input			[4:0]	subchar_line;
input			[3:0]	subchar_pixel;


input			[9:0]	graph_pixel;
input			[9:0]	graph_line_2x;
input			[9:0]	graph_line_3x;
input			[13:0]	graph_line_a84;

output					vram_rd_enable;
output	reg		[13:0]	vram_addr;
input			[7:0] 	vram_data;

output			[7:0]	vga_red;
output			[7:0]	vga_green;
output			[7:0]	vga_blue;









wire				pixel_on;





wire	[1:0]		pixel_8p_2bit;
wire	[1:0]		pixel_4p_2bit;
wire				pixel_4p_1bit;
wire				pixel_2p_1bit;
wire				pixel_2p_1bit_half;

reg		[7:0] 		latched_vram_data;


reg		[7:0] 		latched_palette_data;

assign vram_rd_enable = pixel_clock;

reg		[23:0] latched_vga_rgb;
wire	[23:0] vga_rgb;



always @ (posedge pixel_clock) begin
	if(ag==1'b0)
	begin
			if(subchar_pixel==4'b0001)
				vram_addr <= {4'b0,char_line[3:0], char_column[4:0]};

			if(subchar_pixel==4'b0011)
				latched_vram_data <= vram_data;
			if(graph_pixel[3:0]==4'b0110)
				latched_palette_data <= latched_vram_data;
	end
	else
	begin





		if(graph_pixel[2:0]==3'b001)
			vram_addr <= graph_line_a84 + {graph_pixel[9:3],4'h0};

		if(graph_pixel[2:0]==3'b011)
			latched_vram_data <= vram_data;

	end
	latched_vga_rgb <= vga_rgb;
end




wire [2:0]	palette_bit_graph;


wire [23:0]	palette_rgb_border =	(~ag)	?	24'h000000:
												24'h101010;

wire [23:0] palette_rgb_pixel = 24'h000000;
wire [23:0] palette_rgb_background = 24'h07ff00;














assign palette_bit_graph		=	(~ag)			?	latched_palette_data[6:4]				:
														{css, pixel_2p_1bit_half, pixel_2p_1bit_half	}	;

wire [23:0] palette_rgb_graph =	(palette_bit_graph==3'b000) ?	24'h07ff00 :
								(palette_bit_graph==3'b001) ?	24'hffff00 :
								(palette_bit_graph==3'b010) ?	24'h3b08ff :
								(palette_bit_graph==3'b011) ?	24'hcc003b :
								(palette_bit_graph==3'b100) ?	24'hffffff :
								(palette_bit_graph==3'b101) ?	24'h07e399 :
								(palette_bit_graph==3'b110) ?	24'hff1cff :
																24'hff8100 ;



assign palette_bit_graph_bw		=	pixel_2p_1bit_half;

wire [23:0] palette_rgb_graph_bw	=	(palette_bit_graph_bw) ?	24'h07ff00 :
																	24'h000000;








assign vga_rgb =	(show_border)	? palette_rgb_border :

					(ag)			? palette_rgb_graph_bw :
					(~pixel_on)		? palette_rgb_pixel :
					(latched_palette_data[7])	? palette_rgb_graph : palette_rgb_background;

assign vga_red = latched_vga_rgb[23:16];
assign vga_green = latched_vga_rgb[15:8];
assign vga_blue = latched_vga_rgb[7:0];




CHAR_GEN CHAR_GEN
(
	.reset(reset),

	.char_code(latched_vram_data),
	.subchar_line(subchar_line),
	.subchar_pixel(subchar_pixel),

	.pixel_clock(pixel_clock),
	.pixel_on(pixel_on)
);

PIXEL_GEN PIXEL_GEN
(
	.reset(reset),

	.pixel_code(latched_vram_data),
	.graph_pixel(graph_pixel),

	.pixel_clock(pixel_clock),

	.pixel_8p_2bit(pixel_8p_2bit),
	.pixel_4p_2bit(pixel_4p_2bit),
	.pixel_4p_1bit(pixel_4p_1bit),
	.pixel_2p_1bit(pixel_2p_1bit),
	.pixel_2p_1bit_half(pixel_2p_1bit_half)
);

endmodule