data/full_repos/permissive/158984095/klinverter_tb.v
1: b'%Error: data/full_repos/permissive/158984095/klinverter_tb.v:7: Unsupported or unknown PLI call: $monitor\n$monitor($time,"Input = %b Output = %b\\n",in1,out1);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/158984095/klinverter_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/158984095/klinverter_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/klinverter_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#5; \n^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
reg in1,out1;
Inverter instance1 (in1,out1);

initial
begin
$monitor($time,"Input = %b Output = %b\n",in1,out1);
in1 = 0;
#5;
in1 = 1;
#5;
in1 = 0;
#5; 
in1 = 1;
end
endmodule
module testbench;

reg in1,out1;
Inverter instance1 (in1,out1);

initial
begin
$monitor($time,"Input = %b Output = %b\n",in1,out1);
in1 = 0;
#5;
in1 = 1;
#5;
in1 = 0;
#5; 
in1 = 1;
end
endmodule