data/full_repos/permissive/168753118/rtl/modules/PREDICTOR.v
 line:80: before: "integer"
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/PREDICTOR.v:52: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'imm_value_wire'\n                                                                                   : ... In instance PREDICTOR\n    BRANCH:   imm_value_wire = {{ 20{pred_ins_in[31]}},\n              ^~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/PREDICTOR.v:56: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'imm_value_wire'\n                                                                                   : ... In instance PREDICTOR\n    JAL:      imm_value_wire = {{ 21{pred_ins_in[31]}},\n              ^~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/PREDICTOR.v:58: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'imm_value_wire'\n                                                                                   : ... In instance PREDICTOR\n    default:  imm_value_wire = 32'h00000000;\n              ^~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/PREDICTOR.v:63: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'taken_pred_wire'\n                                                                                   : ... In instance PREDICTOR\n    BRANCH:   taken_pred_wire = branch_buffer[pred_addr_in[9:0]][1];\n              ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/PREDICTOR.v:64: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'taken_pred_wire'\n                                                                                   : ... In instance PREDICTOR\n    JAL:      taken_pred_wire = 1'b1;\n              ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/PREDICTOR.v:65: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'taken_pred_wire'\n                                                                                   : ... In instance PREDICTOR\n    default:  taken_pred_wire = 1'b0;\n              ^~~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/PREDICTOR.v:70: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'target_pc_wire'\n                                                                                   : ... In instance PREDICTOR\n    target_pc_wire = pred_addr_in + imm_value_wire;\n    ^~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/PREDICTOR.v:72: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'target_pc_wire'\n                                                                                   : ... In instance PREDICTOR\n    target_pc_wire = 32'h00000000;\n    ^~~~~~~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/168753118/rtl/modules/PREDICTOR.v:88: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'old_status_wire'\n                                                                                   : ... In instance PREDICTOR\n    old_status_wire = branch_buffer[pred_indx_in];\n    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module PREDICTOR (
  input pred_clock_in,
  input pred_reset_in,
  input pred_write_enable_in,
  input pred_taken_in,
  input [9:0] pred_indx_in,
  input [31:0] pred_addr_in,
  input [31:0] pred_ins_in,
  output pred_taken_out,
  output [31:0] pred_pc_out
);


parameter MEM_SIZE = 1024;


parameter BRANCH = 5'b11000;
parameter JAL = 5'b11011;


reg [1:0] branch_buffer [0:MEM_SIZE-1];


wire taken_pred_wire;
wire [1:0] status_wire;
wire [1:0] old_status_wire;
wire [31:0] imm_value_wire;
wire [31:0] target_pc_wire;



always @ ( * ) begin

  case(pred_ins_in[6:2])
    BRANCH:   imm_value_wire = {{ 20{pred_ins_in[31]}},
                                  pred_ins_in[7],
                                  pred_ins_in[30:25],
                                  pred_ins_in[11:8], 1'b0};
    JAL:      imm_value_wire = {{ 21{pred_ins_in[31]}},
                                  pred_ins_in[30:20]};
    default:  imm_value_wire = 32'h00000000;
  endcase


  case(pred_ins_in[6:2])
    BRANCH:   taken_pred_wire = branch_buffer[pred_addr_in[9:0]][1];
    JAL:      taken_pred_wire = 1'b1;
    default:  taken_pred_wire = 1'b0;
  endcase


  if(taken_pred_wire==1'b1)
    target_pc_wire = pred_addr_in + imm_value_wire;
  else
    target_pc_wire = 32'h00000000;
end



always @ ( posedge pred_clock_in, posedge pred_reset_in ) begin

  if(pred_reset_in == 1'b1) begin
    integer j;
    for (j=0; j<MEM_SIZE; j=j+1) begin
      branch_buffer[j] = 2'b00;
    end
  end


  if(pred_write_enable_in == 1'b1) begin
    old_status_wire = branch_buffer[pred_indx_in];
    branch_buffer[pred_indx_in] = {old_status_wire[0], pred_taken_in};
  end
end

assign pred_pc_out = target_pc_wire;
assign pred_taken_out = taken_pred_wire;


endmodule
module PREDICTOR (
  input pred_clock_in,
  input pred_reset_in,
  input pred_write_enable_in,
  input pred_taken_in,
  input [9:0] pred_indx_in,
  input [31:0] pred_addr_in,
  input [31:0] pred_ins_in,
  output pred_taken_out,
  output [31:0] pred_pc_out
);



parameter MEM_SIZE = 1024;


parameter BRANCH = 5'b11000;
parameter JAL = 5'b11011;


reg [1:0] branch_buffer [0:MEM_SIZE-1];


wire taken_pred_wire;
wire [1:0] status_wire;
wire [1:0] old_status_wire;
wire [31:0] imm_value_wire;
wire [31:0] target_pc_wire;



always @ ( * ) begin

  case(pred_ins_in[6:2])
    BRANCH:   imm_value_wire = {{ 20{pred_ins_in[31]}},
                                  pred_ins_in[7],
                                  pred_ins_in[30:25],
                                  pred_ins_in[11:8], 1'b0};
    JAL:      imm_value_wire = {{ 21{pred_ins_in[31]}},
                                  pred_ins_in[30:20]};
    default:  imm_value_wire = 32'h00000000;
  endcase


  case(pred_ins_in[6:2])
    BRANCH:   taken_pred_wire = branch_buffer[pred_addr_in[9:0]][1];
    JAL:      taken_pred_wire = 1'b1;
    default:  taken_pred_wire = 1'b0;
  endcase


  if(taken_pred_wire==1'b1)
    target_pc_wire = pred_addr_in + imm_value_wire;
  else
    target_pc_wire = 32'h00000000;
end



always @ ( posedge pred_clock_in, posedge pred_reset_in ) begin

  if(pred_reset_in == 1'b1) begin
    integer j;
    for (j=0; j<MEM_SIZE; j=j+1) begin
      branch_buffer[j] = 2'b00;
    end
  end


  if(pred_write_enable_in == 1'b1) begin
    old_status_wire = branch_buffer[pred_indx_in];
    branch_buffer[pred_indx_in] = {old_status_wire[0], pred_taken_in};
  end
end

assign pred_pc_out = target_pc_wire;
assign pred_taken_out = taken_pred_wire;


endmodule