data/full_repos/permissive/135077285/muxHazard.v
data/verilator_xmls/312bedbe-a483-4c7a-bc69-0598279aa510.xml
module muxHazard (

    input wire control,


    input wire regDest,
    input wire [1:0] aluOp,
    input wire aluSrc,

    input wire [2:0] memControlIdEx,

    input wire [1:0] wbControlIdEx,



    output reg hzdRegDest,
    output reg [1:0] hzdAluOp,
    output reg hzdAluSrc,

    output reg [2:0] hzdMemControlIdEx,

    output reg [1:0] hzdWbControlIdEx
);

    always @(*) begin
      case (control)
        1'b0: begin
          hzdRegDest <= regDest;
          hzdAluOp <= aluOp;
          hzdAluSrc <= aluSrc;
          hzdMemControlIdEx <= memControlIdEx;
          hzdWbControlIdEx <= wbControlIdEx;
      end
        1'b1: begin
          hzdRegDest <= 0;
          hzdAluOp <= 0;
          hzdAluSrc <= 0;
          hzdMemControlIdEx <= 0;
          hzdWbControlIdEx <= 0;
      end
    endcase
  end
endmodule
module muxHazard (

    input wire control,


    input wire regDest,
    input wire [1:0] aluOp,
    input wire aluSrc,

    input wire [2:0] memControlIdEx,

    input wire [1:0] wbControlIdEx,



    output reg hzdRegDest,
    output reg [1:0] hzdAluOp,
    output reg hzdAluSrc,

    output reg [2:0] hzdMemControlIdEx,

    output reg [1:0] hzdWbControlIdEx
);


    always @(*) begin
      case (control)
        1'b0: begin
          hzdRegDest <= regDest;
          hzdAluOp <= aluOp;
          hzdAluSrc <= aluSrc;
          hzdMemControlIdEx <= memControlIdEx;
          hzdWbControlIdEx <= wbControlIdEx;
      end
        1'b1: begin
          hzdRegDest <= 0;
          hzdAluOp <= 0;
          hzdAluSrc <= 0;
          hzdMemControlIdEx <= 0;
          hzdWbControlIdEx <= 0;
      end
    endcase
  end
endmodule