data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v
1: b'%Error: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:26: syntax error, unexpected \')\', expecting "\'{"\n    crt_sys ob_crt_sys( clk, _reset, db, ds, as, _wr, ma, md,  _mcs, _mrd, _mwr, med_res, pixel, sync, a, b, hsync, vsync, extsyncon, int);\n                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #20 _reset = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #200  dbi = 8\'b0000_0000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #400  dbi = 8\'b0000_0000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #400  dbi = 8\'b0110_0000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #400  dbi = 8\'bzzzz_zzzz;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 0;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 0;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 0;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:80: Unsupported: Ignoring delay on this delayed statement.\n            #30000 hsync = 1; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:81: Unsupported: Ignoring delay on this delayed statement.\n            #1000  hsync = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:90: Unsupported: Ignoring delay on this delayed statement.\n            #10000000 vsync = 0; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_measure_tst.v:91: Unsupported: Ignoring delay on this delayed statement.\n            #150000   vsync = 1;\n            ^\n%Error: Exiting due to 1 error(s), 21 warning(s)\n'
module crt_measure_test;

    reg             clk, _reset;
    wire            med_res;
    reg     [7:0]   dbi, mdi;
    reg             ds, as, _wr;
    wire    [3:0]   pixel;
	wire  	[7:0]	md;
	wire	[19:0]  ma;
	wire    [7:0]	db;
    reg     [3:0]   a, b;
    reg             hsync, vsync;
    wire            extsyncon;
    
    assign extsyncon = 1;
    assign med_res 	 = 1;  
	assign db = dbi;
    assign md = mdi;
    crt_sys ob_crt_sys( clk, _reset, db, ds, as, _wr, ma, md,  _mcs, _mrd, _mwr, med_res, pixel, sync, a, b, hsync, vsync, extsyncon, int);

    initial begin
        mdi <= 8'bzzzz_zzzz;
    end

    initial begin
        clk = 1'b0;
        forever clk = #33.9 ~clk;
    end

    initial begin
        _reset = 0;
        #20 _reset = 1;
    end

    initial begin
        dbi = 8'bzzzz_zzzz;
        #200  dbi = 8'b0000_0000;
        #400  dbi = 8'b0000_0000;
        #400  dbi = 8'b0110_0000;
        #400  dbi = 8'bzzzz_zzzz;

    end

    initial begin
        as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        forever as = #200 ~as;
    end

    initial begin
        _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
    end

    initial begin
        ds = 0;
    end

    initial begin
        hsync = 0;
        forever 
        begin 
            #30000 hsync = 1; 
            #1000  hsync = 0;
        end
    end


    initial begin
        vsync = 1;
        forever
        begin 
            #10000000 vsync = 0; 
            #150000   vsync = 1;
        end
    end
endmodule
module crt_measure_test;


    reg             clk, _reset;
    wire            med_res;
    reg     [7:0]   dbi, mdi;
    reg             ds, as, _wr;
    wire    [3:0]   pixel;
	wire  	[7:0]	md;
	wire	[19:0]  ma;
	wire    [7:0]	db;
    reg     [3:0]   a, b;
    reg             hsync, vsync;
    wire            extsyncon;
    
    assign extsyncon = 1;
    assign med_res 	 = 1;  
	assign db = dbi;
    assign md = mdi;
    crt_sys ob_crt_sys( clk, _reset, db, ds, as, _wr, ma, md,  _mcs, _mrd, _mwr, med_res, pixel, sync, a, b, hsync, vsync, extsyncon, int);

    initial begin
        mdi <= 8'bzzzz_zzzz;
    end

    initial begin
        clk = 1'b0;
        forever clk = #33.9 ~clk;
    end

    initial begin
        _reset = 0;
        #20 _reset = 1;
    end

    initial begin
        dbi = 8'bzzzz_zzzz;
        #200  dbi = 8'b0000_0000;
        #400  dbi = 8'b0000_0000;
        #400  dbi = 8'b0110_0000;
        #400  dbi = 8'bzzzz_zzzz;

    end

    initial begin
        as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        forever as = #200 ~as;
    end

    initial begin
        _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
    end

    initial begin
        ds = 0;
    end

    initial begin
        hsync = 0;
        forever 
        begin 
            #30000 hsync = 1; 
            #1000  hsync = 0;
        end
    end


    initial begin
        vsync = 1;
        forever
        begin 
            #10000000 vsync = 0; 
            #150000   vsync = 1;
        end
    end
endmodule