data/full_repos/permissive/132439949/sources_1/new/SSD2.v
data/verilator_xmls/6c097762-db8b-4e61-bc76-5a44441f8a29.xml
module SSD2(
    input CLK,
    input [3:0] score,
    
    output [3:0] ANODE,
    output reg [6:0] seg,
    output dp
    );
    
     parameter [3:0] enable_arr = 4'b1111;
     reg [3:0] CURRENT_PLACE_AN;
     reg [18:0] COUNT;
     
     assign ANODE = ~(enable_arr & CURRENT_PLACE_AN);
     assign dp = 1;
         
     initial begin
        COUNT = 0;
        seg = 7'b1111111;
     end
     
     always @ (posedge CLK) begin
        COUNT <= COUNT + 1;
     end
     
     always @(COUNT) begin
         case (COUNT[18:17])
             2'b00: begin CURRENT_PLACE_AN = 4'b1000; end  
             2'b01: begin CURRENT_PLACE_AN = 4'b0100; end
             2'b10: begin CURRENT_PLACE_AN = 4'b0010; end
             2'b11: begin CURRENT_PLACE_AN = 4'b0001; end
             default: CURRENT_PLACE_AN = 4'b0000;
         endcase  
     end
     
      always @(CURRENT_PLACE_AN, score) begin      
         if(score<10) begin
            case (score)
                0: begin
                    case (CURRENT_PLACE_AN)
                    4'b0001: seg = 7'b0000001;
                    default: seg = 7'b1111111;
                    endcase
                   end
                1: begin
                     case (CURRENT_PLACE_AN)
                     4'b0001: seg = 7'b1001111;
                     default: seg = 7'b1111111;
                     endcase
                   end
                2: begin
                     case (CURRENT_PLACE_AN)
                     4'b0001: seg = 7'b0010010;
                     default: seg = 7'b1111111;
                     endcase
                   end
                3: begin
                      case (CURRENT_PLACE_AN)
                      4'b0001: seg = 7'b0000110;
                      default: seg = 7'b1111111;
                      endcase
                   end
                   
                4:begin
                   case (CURRENT_PLACE_AN)
                   4'b0001: seg = 7'b1001100;
                   default: seg = 7'b1111111;
                   endcase
                   end
                5:begin
                  case (CURRENT_PLACE_AN)
                  4'b0001: seg = 7'b0100100;
                  default: seg = 7'b1111111;
                  endcase
                  end
                  
                6: begin
                   case (CURRENT_PLACE_AN)
                   4'b0001: seg = 7'b0100000;
                   default: seg = 7'b1111111;
                   endcase
                   end
                   
                7:begin
                  case (CURRENT_PLACE_AN)
                  4'b0001: seg = 7'b0001111;
                  default: seg = 7'b1111111;
                  endcase
                  end
                  
                8:begin
                  case (CURRENT_PLACE_AN)
                  4'b0001: seg = 7'b0000000;
                  default: seg = 7'b1111111;
                  endcase
                  end    
                              
                9:begin
                  case (CURRENT_PLACE_AN)
                  4'b0001: seg = 7'b0000100;
                  default: seg = 7'b1111111;
                  endcase
                  end   
             endcase
          end  
          else begin
            seg = 7'b1111111;
          end                 
        end
endmodule
module SSD2(
    input CLK,
    input [3:0] score,
    
    output [3:0] ANODE,
    output reg [6:0] seg,
    output dp
    );

    
     parameter [3:0] enable_arr = 4'b1111;
     reg [3:0] CURRENT_PLACE_AN;
     reg [18:0] COUNT;
     
     assign ANODE = ~(enable_arr & CURRENT_PLACE_AN);
     assign dp = 1;
         
     initial begin
        COUNT = 0;
        seg = 7'b1111111;
     end
     
     always @ (posedge CLK) begin
        COUNT <= COUNT + 1;
     end
     
     always @(COUNT) begin
         case (COUNT[18:17])
             2'b00: begin CURRENT_PLACE_AN = 4'b1000; end  
             2'b01: begin CURRENT_PLACE_AN = 4'b0100; end
             2'b10: begin CURRENT_PLACE_AN = 4'b0010; end
             2'b11: begin CURRENT_PLACE_AN = 4'b0001; end
             default: CURRENT_PLACE_AN = 4'b0000;
         endcase  
     end
     
      always @(CURRENT_PLACE_AN, score) begin      
         if(score<10) begin
            case (score)
                0: begin
                    case (CURRENT_PLACE_AN)
                    4'b0001: seg = 7'b0000001;
                    default: seg = 7'b1111111;
                    endcase
                   end
                1: begin
                     case (CURRENT_PLACE_AN)
                     4'b0001: seg = 7'b1001111;
                     default: seg = 7'b1111111;
                     endcase
                   end
                2: begin
                     case (CURRENT_PLACE_AN)
                     4'b0001: seg = 7'b0010010;
                     default: seg = 7'b1111111;
                     endcase
                   end
                3: begin
                      case (CURRENT_PLACE_AN)
                      4'b0001: seg = 7'b0000110;
                      default: seg = 7'b1111111;
                      endcase
                   end
                   
                4:begin
                   case (CURRENT_PLACE_AN)
                   4'b0001: seg = 7'b1001100;
                   default: seg = 7'b1111111;
                   endcase
                   end
                5:begin
                  case (CURRENT_PLACE_AN)
                  4'b0001: seg = 7'b0100100;
                  default: seg = 7'b1111111;
                  endcase
                  end
                  
                6: begin
                   case (CURRENT_PLACE_AN)
                   4'b0001: seg = 7'b0100000;
                   default: seg = 7'b1111111;
                   endcase
                   end
                   
                7:begin
                  case (CURRENT_PLACE_AN)
                  4'b0001: seg = 7'b0001111;
                  default: seg = 7'b1111111;
                  endcase
                  end
                  
                8:begin
                  case (CURRENT_PLACE_AN)
                  4'b0001: seg = 7'b0000000;
                  default: seg = 7'b1111111;
                  endcase
                  end    
                              
                9:begin
                  case (CURRENT_PLACE_AN)
                  4'b0001: seg = 7'b0000100;
                  default: seg = 7'b1111111;
                  endcase
                  end   
             endcase
          end  
          else begin
            seg = 7'b1111111;
          end                 
        end
endmodule