data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:4: Define or directive not defined: \'`DATA_BUS\'\n    input wire [`DATA_BUS] M_valE_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:4: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`DATA_BUS] M_valE_i,\n                         ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:5: Define or directive not defined: \'`DATA_BUS\'\n    input wire [`DATA_BUS] M_valA_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:6: Define or directive not defined: \'`ICODE_BUS\'\n    input wire [`ICODE_BUS] M_icode_i,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:8: Define or directive not defined: \'`ADDR_BUS\'\n    output reg [`ADDR_BUS] addr,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:14: Define or directive not defined: \'`RMMOVQ\'\n            if(M_icode_i == `RMMOVQ)\n                            ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:17: Define or directive not defined: \'`TRUE\'\n                    write = `TRUE;\n                            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:19: Define or directive not defined: \'`MRMOVQ\'\n            else if(M_icode_i == `MRMOVQ)\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:22: Define or directive not defined: \'`FALSE\'\n                    write = `FALSE;\n                            ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:24: Define or directive not defined: \'`CALL\'\n            else if(M_icode_i == `CALL || M_icode_i == `PUSHQ)\n                                 ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:24: Define or directive not defined: \'`PUSHQ\'\n            else if(M_icode_i == `CALL || M_icode_i == `PUSHQ)\n                                                       ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:27: Define or directive not defined: \'`TRUE\'\n                    write = `TRUE;\n                            ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:29: Define or directive not defined: \'`RET\'\n            else if(M_icode_i == `RET || M_icode_i == `POPQ)\n                                 ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:29: Define or directive not defined: \'`POPQ\'\n            else if(M_icode_i == `RET || M_icode_i == `POPQ)\n                                                      ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:32: Define or directive not defined: \'`FALSE\'\n                    write = `FALSE;\n                            ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:36: Define or directive not defined: \'`ADDR_ZERO\'\n                    addr = `ADDR_ZERO;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/mem.v:37: Define or directive not defined: \'`FALSE\'\n                    write = `FALSE;\n                            ^~~~~~\n%Error: Exiting due to 18 error(s)\n'
module mem(
    input wire [`DATA_BUS] M_valE_i,
    input wire [`DATA_BUS] M_valA_i,
    input wire [`ICODE_BUS] M_icode_i,
    
    output reg [`ADDR_BUS] addr,
    output reg write
    );
    
    always @(*)
        begin
            if(M_icode_i == `RMMOVQ)
                begin
                    addr = M_valE_i;
                    write = `TRUE;
                end
            else if(M_icode_i == `MRMOVQ)
                begin
                    addr = M_valE_i;
                    write = `FALSE;
                end
            else if(M_icode_i == `CALL || M_icode_i == `PUSHQ)
                begin
                    addr = M_valE_i;
                    write = `TRUE;
                end
            else if(M_icode_i == `RET || M_icode_i == `POPQ)
                begin
                    addr = M_valA_i;
                    write = `FALSE;
                end
            else
                begin
                    addr = `ADDR_ZERO;
                    write = `FALSE;
                end
        end
    
endmodule
module mem(
    input wire [`DATA_BUS] M_valE_i,
    input wire [`DATA_BUS] M_valA_i,
    input wire [`ICODE_BUS] M_icode_i,
    
    output reg [`ADDR_BUS] addr,
    output reg write
    );

    
    always @(*)
        begin
            if(M_icode_i == `RMMOVQ)
                begin
                    addr = M_valE_i;
                    write = `TRUE;
                end
            else if(M_icode_i == `MRMOVQ)
                begin
                    addr = M_valE_i;
                    write = `FALSE;
                end
            else if(M_icode_i == `CALL || M_icode_i == `PUSHQ)
                begin
                    addr = M_valE_i;
                    write = `TRUE;
                end
            else if(M_icode_i == `RET || M_icode_i == `POPQ)
                begin
                    addr = M_valA_i;
                    write = `FALSE;
                end
            else
                begin
                    addr = `ADDR_ZERO;
                    write = `FALSE;
                end
        end
    
endmodule