data/full_repos/permissive/131358616/test/uart_tb.v
 line:86: before: "("
1: b'%Error: data/full_repos/permissive/131358616/test/uart_tb.v:75: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, uart_1, uart_2);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/131358616/test/uart_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\nalways #(clk_pulse_width/2) clk = !clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/131358616/test/uart_tb.v:83: Unsupported or unknown PLI call: $monitor\n $monitor("Time %d", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/uart_tb.v:86: syntax error, unexpected \'@\'\n repeat (5) @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/131358616/test/uart_tb.v:99: Unsupported: wait statements\n wait( rst_n );\n ^~~~\n%Error: data/full_repos/permissive/131358616/test/uart_tb.v:100: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/131358616/test/uart_tb.v:101: Unsupported or unknown PLI call: $monitor\n $monitor("[Time %d]: Started testbench", $time);\n ^~~~~~~~\n%Error: data/full_repos/permissive/131358616/test/uart_tb.v:106: syntax error, unexpected \'@\'\n repeat (10) @(negedge clk);\n             ^\n%Error: data/full_repos/permissive/131358616/test/uart_tb.v:110: Unsupported: wait statements\n wait ( !tx_busy_1 & !rx_busy_1 & !tx_busy_2 & !rx_busy_2);\n ^~~~\n%Error: data/full_repos/permissive/131358616/test/uart_tb.v:111: syntax error, unexpected \'@\'\n repeat (500) @(negedge clk);\n              ^\n%Error: Exiting due to 9 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_tb;

reg clk, rst_n;

reg clear_1;
reg start_transmit_1;
reg [7:0] data_to_send_1;
wire [7:0] received_data_1;
wire error_1, new_value_1, tx_busy_1, rx_busy_1;

reg clear_2;
reg start_transmit_2;
reg [7:0] data_to_send_2;
wire [7:0] received_data_2;
wire error_2, new_value_2, tx_busy_2, rx_busy_2;

wire interface_send_1, interface_send_2;

localparam clock_frequency = 12000000;
localparam clk_pulse_width = 1000000000/clock_frequency;

localparam baud_rate = 9600;

uart #(
	.clock_frequency(clock_frequency),
	.baud_rate(baud_rate)
) uart_1(
    .rst_n(rst_n),
    .clk(clk),
    .rx(interface_send_2),
	.tx(interface_send_1),
    .clear(clear_1),
	.start_transmit(start_transmit_1),
    .rx_busy(rx_busy_1),
	.tx_busy(tx_busy_1),
    .error(error_1),
    .new_value(new_value_1),
	.data_to_send(data_to_send_1),
    .recvd_data(received_data_1)
);

uart #(
	.clock_frequency(clock_frequency),
	.baud_rate(baud_rate) 
) uart_2(
    .rst_n(rst_n),
    .clk(clk),
    .rx(interface_send_1),
	.tx(interface_send_2),
    .clear(clear_2),
	.start_transmit(start_transmit_2),
    .rx_busy(rx_busy_2),
	.tx_busy(tx_busy_2),
    .error(error_2),
    .new_value(new_value_2),
	.data_to_send(data_to_send_2),
    .recvd_data(received_data_2)
);


initial begin

    $dumpvars(0, uart_1, uart_2);
end


always #(clk_pulse_width/2) clk = !clk;


initial begin
	$monitor("Time %d", $time);
	clk = 0;
    rst_n = 0;
	repeat (5) @(negedge clk);
	rst_n = 1;
end


initial begin
	clear_1 = 0;
	start_transmit_1 = 0;
	data_to_send_1 = 0;
	clear_2 = 0;
	start_transmit_2 = 0;
	data_to_send_2 = 0;

	wait( rst_n );
	@(negedge clk);
	$monitor("[Time %d]: Started testbench", $time);

	data_to_send_1 = 8'b10101010;
	start_transmit_1 = 1;
	
	repeat (10) @(negedge clk);
	start_transmit_1 = 0;
	data_to_send_1 = 0;

	wait ( !tx_busy_1 & !rx_busy_1 & !tx_busy_2 & !rx_busy_2);
	repeat (500) @(negedge clk);
	$finish;
end

endmodule
module uart_tb;


reg clk, rst_n;

reg clear_1;
reg start_transmit_1;
reg [7:0] data_to_send_1;
wire [7:0] received_data_1;
wire error_1, new_value_1, tx_busy_1, rx_busy_1;

reg clear_2;
reg start_transmit_2;
reg [7:0] data_to_send_2;
wire [7:0] received_data_2;
wire error_2, new_value_2, tx_busy_2, rx_busy_2;

wire interface_send_1, interface_send_2;

localparam clock_frequency = 12000000;
localparam clk_pulse_width = 1000000000/clock_frequency;

localparam baud_rate = 9600;

uart #(
	.clock_frequency(clock_frequency),
	.baud_rate(baud_rate)
) uart_1(
    .rst_n(rst_n),
    .clk(clk),
    .rx(interface_send_2),
	.tx(interface_send_1),
    .clear(clear_1),
	.start_transmit(start_transmit_1),
    .rx_busy(rx_busy_1),
	.tx_busy(tx_busy_1),
    .error(error_1),
    .new_value(new_value_1),
	.data_to_send(data_to_send_1),
    .recvd_data(received_data_1)
);

uart #(
	.clock_frequency(clock_frequency),
	.baud_rate(baud_rate) 
) uart_2(
    .rst_n(rst_n),
    .clk(clk),
    .rx(interface_send_1),
	.tx(interface_send_2),
    .clear(clear_2),
	.start_transmit(start_transmit_2),
    .rx_busy(rx_busy_2),
	.tx_busy(tx_busy_2),
    .error(error_2),
    .new_value(new_value_2),
	.data_to_send(data_to_send_2),
    .recvd_data(received_data_2)
);


initial begin

    $dumpvars(0, uart_1, uart_2);
end


always #(clk_pulse_width/2) clk = !clk;


initial begin
	$monitor("Time %d", $time);
	clk = 0;
    rst_n = 0;
	repeat (5) @(negedge clk);
	rst_n = 1;
end


initial begin
	clear_1 = 0;
	start_transmit_1 = 0;
	data_to_send_1 = 0;
	clear_2 = 0;
	start_transmit_2 = 0;
	data_to_send_2 = 0;

	wait( rst_n );
	@(negedge clk);
	$monitor("[Time %d]: Started testbench", $time);

	data_to_send_1 = 8'b10101010;
	start_transmit_1 = 1;
	
	repeat (10) @(negedge clk);
	start_transmit_1 = 0;
	data_to_send_1 = 0;

	wait ( !tx_busy_1 & !rx_busy_1 & !tx_busy_2 & !rx_busy_2);
	repeat (500) @(negedge clk);
	$finish;
end

endmodule