data/full_repos/permissive/202237519/verilog/digitalsystem4/4bit_add_sub_tb.v
 line:55: before: "+"
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem4/4bit_add_sub_tb.v:1: Cannot find include file: 4bit_add_sub.v\n`include "4bit_add_sub.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem4,data/full_repos/permissive/202237519/4bit_add_sub.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem4,data/full_repos/permissive/202237519/4bit_add_sub.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem4,data/full_repos/permissive/202237519/4bit_add_sub.v.sv\n             4bit_add_sub.v\n             4bit_add_sub.v.v\n             4bit_add_sub.v.sv\n             obj_dir/4bit_add_sub.v\n             obj_dir/4bit_add_sub.v.v\n             obj_dir/4bit_add_sub.v.sv\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem4/4bit_add_sub_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("4bit_add_sub_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem4/4bit_add_sub_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,add_sub_4bit_tb);  \n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem4/4bit_add_sub_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n                A <= k; #10;\n                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module add_sub_4bit_tb;

reg [3:0]A,B;
reg cin;
wire [3:0]sum;
wire cout;
wire [4:0]sum_f;
integer i,j,k;

add_sub_4bit a_s0 (A,B,cin,cout,sum,sum_f);

initial begin
    $dumpfile("4bit_add_sub_tb.vcd");
    $dumpvars(0,add_sub_4bit_tb);
    for(i = 4'b0000; i <= 4'b0001; i++)
	begin
        cin <= i;
		for(j=4'b0000; j <=4'b1111; j++)
        begin
            B <= j;
            for(k=4'b0000; k<=4'b1111; k++)
            begin
                A <= k; #10;
            end
        end
	end
    $finish;
end

endmodule
module add_sub_4bit_tb;


reg [3:0]A,B;
reg cin;
wire [3:0]sum;
wire cout;
wire [4:0]sum_f;
integer i,j,k;

add_sub_4bit a_s0 (A,B,cin,cout,sum,sum_f);

initial begin
    $dumpfile("4bit_add_sub_tb.vcd");
    $dumpvars(0,add_sub_4bit_tb);
    for(i = 4'b0000; i <= 4'b0001; i++)
	begin
        cin <= i;
		for(j=4'b0000; j <=4'b1111; j++)
        begin
            B <= j;
            for(k=4'b0000; k<=4'b1111; k++)
            begin
                A <= k; #10;
            end
        end
	end
    $finish;
end

endmodule