data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v
 line:19: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:19: Unsupported: Ignoring delay on this delayed statement.\n  always #(HALF_STEP) begin  \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #(SERIAL_1BIT_TIME);\n      ^\n%Error: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:44: Unsupported: wait statements\n      wait(serial_tx == 0);  \n      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #(SERIAL_1BIT_TIME);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #(SERIAL_1BIT_TIME / 2);  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #(SERIAL_1BIT_TIME);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #(SERIAL_1BIT_TIME);  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP * 10); \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP * 10); \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:112: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP * 200000);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:114: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP * 2000);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:116: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP * 30);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:118: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP * 30);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:120: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP * 200000);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/131573849/fpga_verilog/test_logiana.v:129: Unsupported: Ignoring delay on this delayed statement.\n    #(STEP * 500000);\n    ^\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_logiana();

  reg clk = 0;
  reg rst = 0;
  reg serial_rx = 1;
  wire serial_tx;
  reg [7:0] probe = 0;
  wire [16:0] sram_addr;
  wire [7:0] sram_data;
  wire sram_ce_n;
  wire sram_oe_n;
  wire sram_we_n;

  parameter STEP = 20;
  parameter HALF_STEP = 10;
  parameter SERIAL_1BIT_TIME = 8680;

  always #(HALF_STEP) begin
    clk <= ~clk;
  end
  task send_bit;
    input data;
    begin
      serial_rx <= data;
      #(SERIAL_1BIT_TIME);
    end
  endtask
  task serial_send_byte;
    input [7:0] data;
    begin
      integer i;
      send_bit(0);
      for (i = 0; i < 8; i = i + 1) begin
        send_bit(data[i]);
      end
      send_bit(1);
    end
  endtask
  task serial_recv_byte;
    output [7:0] data;
    begin
      integer i;
      wait(serial_tx == 0);
      #(SERIAL_1BIT_TIME);
      #(SERIAL_1BIT_TIME / 2);
      for (i = 0; i < 8; i = i + 1) begin
        data[i] <= serial_tx;
        #(SERIAL_1BIT_TIME);
      end
      #(SERIAL_1BIT_TIME);
    end
  endtask


  async_128Kx8 sram(
    .CE_b(sram_ce_n),
    .WE_b(sram_we_n),
    .OE_b(sram_oe_n),
    .A(sram_addr),
    .DQ(sram_data));
  

  top top(
    .input_clk(clk),
    .rst(rst),
    .serial_rx(serial_rx),
    .serial_tx(serial_tx),
    .probe(probe),
    .sram_addr(sram_addr),
    .sram_data(sram_data),
    .sram_ce_n(sram_ce_n),
    .sram_oe_n(sram_oe_n),
    .sram_we_n(sram_we_n));

  initial begin
    reg [7:0] data;
    #(STEP * 10); 
    rst <= 0;     
    #(STEP * 10); 


    serial_send_byte(8'h81);
    serial_send_byte(8'h01);
    serial_send_byte(8'h82);
    serial_send_byte(8'hC0);
    serial_send_byte(8'h83);
    serial_send_byte({1'b1, 7'h3});


    serial_send_byte(8'h01);
    serial_recv_byte(data);
    $display("DIVIDE_SETTING_CMD = %x", data);
    serial_send_byte(8'h02);
    serial_recv_byte(data);
    $display("POS_SETTING_CMD = %x", data);
    serial_send_byte(8'h03);
    serial_recv_byte(data);
    $display("TRIGER_SETTING_CMD = %x", data);
    serial_send_byte(8'h04);
    serial_recv_byte(data);
    $display("CONTROL_CMD = %x", data);


    serial_send_byte(8'h84);
    serial_send_byte(8'hCC);
    serial_send_byte(8'h04);
    serial_recv_byte(data);
    $display("CONTROL_CMD = %x", data);


    #(STEP * 200000);
    probe[2] = 1;
    #(STEP * 2000);
    probe[3] = 1;
    #(STEP * 30);
    probe[4] = 1;
    #(STEP * 30);
    probe[5] = 1;
    #(STEP * 200000);


    serial_send_byte(8'h04);
    serial_recv_byte(data);
    $display("CONTROL_CMD = %x", data);


    serial_send_byte(8'h05);
    #(STEP * 500000);

    $finish;
  end
endmodule
module test_logiana();


  reg clk = 0;
  reg rst = 0;
  reg serial_rx = 1;
  wire serial_tx;
  reg [7:0] probe = 0;
  wire [16:0] sram_addr;
  wire [7:0] sram_data;
  wire sram_ce_n;
  wire sram_oe_n;
  wire sram_we_n;

  parameter STEP = 20;
  parameter HALF_STEP = 10;
  parameter SERIAL_1BIT_TIME = 8680;

  always #(HALF_STEP) begin
    clk <= ~clk;
  end
  task send_bit;
    input data;
    begin
      serial_rx <= data;
      #(SERIAL_1BIT_TIME);
    end
  endtask
  task serial_send_byte;
    input [7:0] data;
    begin
      integer i;
      send_bit(0);
      for (i = 0; i < 8; i = i + 1) begin
        send_bit(data[i]);
      end
      send_bit(1);
    end
  endtask
  task serial_recv_byte;
    output [7:0] data;
    begin
      integer i;
      wait(serial_tx == 0);
      #(SERIAL_1BIT_TIME);
      #(SERIAL_1BIT_TIME / 2);
      for (i = 0; i < 8; i = i + 1) begin
        data[i] <= serial_tx;
        #(SERIAL_1BIT_TIME);
      end
      #(SERIAL_1BIT_TIME);
    end
  endtask


  async_128Kx8 sram(
    .CE_b(sram_ce_n),
    .WE_b(sram_we_n),
    .OE_b(sram_oe_n),
    .A(sram_addr),
    .DQ(sram_data));
  

  top top(
    .input_clk(clk),
    .rst(rst),
    .serial_rx(serial_rx),
    .serial_tx(serial_tx),
    .probe(probe),
    .sram_addr(sram_addr),
    .sram_data(sram_data),
    .sram_ce_n(sram_ce_n),
    .sram_oe_n(sram_oe_n),
    .sram_we_n(sram_we_n));

  initial begin
    reg [7:0] data;
    #(STEP * 10); 
    rst <= 0;     
    #(STEP * 10); 


    serial_send_byte(8'h81);
    serial_send_byte(8'h01);
    serial_send_byte(8'h82);
    serial_send_byte(8'hC0);
    serial_send_byte(8'h83);
    serial_send_byte({1'b1, 7'h3});


    serial_send_byte(8'h01);
    serial_recv_byte(data);
    $display("DIVIDE_SETTING_CMD = %x", data);
    serial_send_byte(8'h02);
    serial_recv_byte(data);
    $display("POS_SETTING_CMD = %x", data);
    serial_send_byte(8'h03);
    serial_recv_byte(data);
    $display("TRIGER_SETTING_CMD = %x", data);
    serial_send_byte(8'h04);
    serial_recv_byte(data);
    $display("CONTROL_CMD = %x", data);


    serial_send_byte(8'h84);
    serial_send_byte(8'hCC);
    serial_send_byte(8'h04);
    serial_recv_byte(data);
    $display("CONTROL_CMD = %x", data);


    #(STEP * 200000);
    probe[2] = 1;
    #(STEP * 2000);
    probe[3] = 1;
    #(STEP * 30);
    probe[4] = 1;
    #(STEP * 30);
    probe[5] = 1;
    #(STEP * 200000);


    serial_send_byte(8'h04);
    serial_recv_byte(data);
    $display("CONTROL_CMD = %x", data);


    serial_send_byte(8'h05);
    #(STEP * 500000);

    $finish;
  end
endmodule