data/full_repos/permissive/114459345/srcCache/riscv.v
1: b'%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:3: Cannot find include file: ctrl.v\n`include "ctrl.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:4: Cannot find include file: pc_reg.v\n`include "pc_reg.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:5: Cannot find include file: if_id.v\n`include "if_id.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:6: Cannot find include file: id.v\n`include "id.v" \n         ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:7: Cannot find include file: id_ex.v\n`include "id_ex.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:8: Cannot find include file: ex.v\n`include "ex.v" \n         ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:9: Cannot find include file: ex_mem.v\n`include "ex_mem.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:10: Cannot find include file: mem.v\n`include "mem.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:11: Cannot find include file: mem_wb.v\n`include "mem_wb.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:12: Cannot find include file: regfile.v\n`include "regfile.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:21: Define or directive not defined: \'`InstBus\'\n input wire[`InstBus] rom_data_i,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstBus] rom_data_i,\n                    ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:22: Define or directive not defined: \'`InstAddrBus\'\n output wire[`InstAddrBus] rom_addr_o,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire ram_ce_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire ram_re_m,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:32: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[`ValidBitBus] ram_rvalid_bit,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:32: Define or directive not defined: \'`ValidBitBus\'\n output wire[`ValidBitBus] ram_rvalid_bit,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:33: Define or directive not defined: \'`MemAddrBus\'\n output wire[`MemAddrBus] ram_raddr_m,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:34: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] ram_rdata_m,   \n            ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:36: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[`ValidBitBus] ram_wvalid_bit,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:36: Define or directive not defined: \'`ValidBitBus\'\n output wire[`ValidBitBus] ram_wvalid_bit,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:37: Define or directive not defined: \'`MemAddrBus\'\n output wire[`MemAddrBus] ram_waddr_m,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:38: Define or directive not defined: \'`DataBus\'\n output wire[`DataBus] ram_wdata_m   \n             ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:41: Define or directive not defined: \'`CtrlWidth\'\n wire[`CtrlWidth] stall;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`CtrlWidth] stall;\n                ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:44: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus] pc; \n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] pc; \n                  ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:47: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus] id_pc_i;   \n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] id_pc_i;   \n                  ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:48: Define or directive not defined: \'`InstBus\'\n wire[`InstBus] id_inst_i; \n      ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:48: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstBus] id_inst_i; \n              ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:52: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] reg1_data;\n      ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] reg1_data;\n             ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:54: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] reg2_data;\n      ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:54: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] reg2_data;\n             ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:59: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] reg1_addr;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:59: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] reg1_addr;\n                 ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:60: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] reg2_addr;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:60: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] reg2_addr;\n                 ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:66: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus] id_pc_o;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:66: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] id_pc_o;\n                  ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:67: Define or directive not defined: \'`AluOpBus\'\n wire[`AluOpBus] id_aluop_o;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:67: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluOpBus] id_aluop_o;\n               ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:68: Define or directive not defined: \'`AluFunct3Bus\'\n wire[`AluFunct3Bus] id_alufunct3_o;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:68: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluFunct3Bus] id_alufunct3_o;\n                   ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:69: Define or directive not defined: \'`AluFunct7Bus\'\n wire[`AluFunct7Bus] id_alufunct7_o;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:69: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluFunct7Bus] id_alufunct7_o;\n                   ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:70: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] id_reg1_o;\n      ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:70: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] id_reg1_o;\n             ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module riscv(

	input wire clk,
	input wire rst,
	

	output wire rom_ce_o,
	input wire[`InstBus] rom_data_i,
	output wire[`InstAddrBus] rom_addr_o,


	input wire req_if,
	

	output wire ram_ce_o,
	

	output wire ram_re_m,
	output wire[`ValidBitBus] ram_rvalid_bit,
	output wire[`MemAddrBus] ram_raddr_m,
	input wire[`DataBus] ram_rdata_m,
	output wire ram_we_m,
	output wire[`ValidBitBus] ram_wvalid_bit,
	output wire[`MemAddrBus] ram_waddr_m,
	output wire[`DataBus] ram_wdata_m
);

	wire[`CtrlWidth] stall;
	

	wire[`InstAddrBus] pc;	
	

	wire[`InstAddrBus] id_pc_i;		 
	wire[`InstBus] id_inst_i;	
	

	wire reg1_suc;
	wire[`RegBus] reg1_data;
	wire reg2_suc;
	wire[`RegBus] reg2_data;
	

	wire reg1_read;
	wire reg2_read;
	wire[`RegAddrBus] reg1_addr;
	wire[`RegAddrBus] reg2_addr;
	

	wire req_id;


	wire[`InstAddrBus] id_pc_o;
	wire[`AluOpBus] id_aluop_o;
	wire[`AluFunct3Bus] id_alufunct3_o;
	wire[`AluFunct7Bus] id_alufunct7_o;
	wire[`RegBus] id_reg1_o;
	wire[`RegBus] id_reg2_o;
	wire[`RegBus] id_imm_o;
	wire id_wreg_o;
	wire[`RegAddrBus] id_wd_o;
	

	wire jump_o;
	wire[`InstAddrBus] jpc_o;
	

	wire[`InstAddrBus] ex_pc_i;
	wire[`AluOpBus] ex_aluop_i;
	wire[`AluFunct3Bus] ex_alufunct3_i;
	wire[`AluFunct7Bus] ex_alufunct7_i;
	wire[`RegBus] ex_reg1_i;
	wire[`RegBus] ex_reg2_i;
	wire[`RegBus] ex_imm_i;
	wire ex_wreg_i;
	wire[`RegAddrBus] ex_wd_i;


	wire[`AluOpBus] ex_aluop_o;
	wire[`AluFunct3Bus] ex_alufunct3_o;
	wire ex_me_o;
	wire[`MemAddrBus] ex_maddr_o;
	wire ex_wreg_o;
	wire[`RegAddrBus] ex_wd_o;
	wire[`RegBus] ex_wdata_o;	
	

	wire ex_wreg_f;
	wire[`RegAddrBus] ex_wd_f;
	wire[`RegBus] ex_wdata_f;
	

	wire[`AluOpBus] mem_aluop_i;
	wire[`AluFunct3Bus] mem_alufunct3_i;
	wire mem_me_i;				
	wire[`MemAddrBus] mem_maddr_i;
	wire mem_wreg_i;
	wire[`RegAddrBus] mem_wd_i;
	wire[`RegBus] mem_wdata_i;	


	wire mem_wreg_o;
	wire[`RegAddrBus] mem_wd_o;
	wire[`RegBus] mem_wdata_o;
	

	wire mem_wreg_f;
	wire[`RegAddrBus] mem_wd_f;
	wire[`RegBus] mem_wdata_f;
	

	wire[`RegAddrBus] wb_wd_o;
	wire wb_wreg_o;
	wire[`RegBus] wb_wdata_o;
	
	ctrl ctrl0(
		.rst(rst), 
		.req_id(req_id), .req_if(req_if),
		.stall(stall)		
	);

	pc_reg pc_reg0(
		.clk(clk), .rst(rst),
		.stall(stall),
		.jumpout(jump_o), .pc_i(jpc_o),
		.pc(pc), .ce(rom_ce_o)
	);	


	assign rom_addr_o = pc;
	
	if_id if_id0(
		.clk(clk), .rst(rst),
		.stall(stall), .jumpout(jump_o),
		.if_pc(pc),	.if_inst(rom_data_i),
		.id_pc(id_pc_i), .id_inst(id_inst_i)		
	);	
	
	id id0(
		.rst(rst),
		
		.pc_i(id_pc_i), .inst_i(id_inst_i),	
		
		.reg1_suc(reg1_suc), .reg2_suc(reg2_suc),
		.reg1_data_i(reg1_data), .reg2_data_i(reg2_data), 
		
		.reg1_read_o(reg1_read), .reg2_read_o(reg2_read),
		.reg1_addr_o(reg1_addr), .reg2_addr_o(reg2_addr),
		
		.pc_o(id_pc_o), .aluop_o(id_aluop_o),
		.alufunct3_o(id_alufunct3_o), .alufunct7_o(id_alufunct7_o),
		.reg1_o(id_reg1_o), .reg2_o(id_reg2_o), .imm_o(id_imm_o),
		.wd_o(id_wd_o), .wreg_o(id_wreg_o),
		
		.stall_req(req_id),
		
		.jump_o(jump_o), .jpc_o(jpc_o)

	);
	
	regfile regfile0(
		.clk(clk), .rst(rst),
		
		.we(wb_wreg_o), .waddr(wb_wd_o), .wdata(wb_wdata_o),
		.ex_we(ex_wreg_f), .ex_waddr(ex_wd_f), .ex_wdata(ex_wdata_f),
		.mem_we(mem_wreg_f), .mem_waddr(mem_wd_f), .mem_wdata(mem_wdata_f),
		
		.re1(reg1_read), .raddr1(reg1_addr), .rsuc1(reg1_suc), .rdata1(reg1_data),
		.re2(reg2_read), .raddr2(reg2_addr), .rsuc2(reg2_suc), .rdata2(reg2_data)
	
	);
	
	id_ex id_ex0(
		.clk(clk), .rst(rst),
		
		.id_pc(id_pc_o), .id_aluop(id_aluop_o), 
		.id_alufunct3(id_alufunct3_o), .id_alufunct7(id_alufunct7_o),
		.id_reg1(id_reg1_o), .id_reg2(id_reg2_o), .id_imm(id_imm_o), 
		.id_wreg(id_wreg_o), .id_wd(id_wd_o),
		
		.ex_pc(ex_pc_i), .ex_aluop(ex_aluop_i),
		.ex_alufunct3(ex_alufunct3_i), .ex_alufunct7(ex_alufunct7_i),
		.ex_reg1(ex_reg1_i), .ex_reg2(ex_reg2_i), .ex_imm(ex_imm_i),
		.ex_wreg(ex_wreg_i), .ex_wd(ex_wd_i),
		
		.stall(stall)
	);
	
	ex ex0(
		.rst(rst),
		
		.pc_i(ex_pc_i), .aluop_i(ex_aluop_i),
		.alufunct3_i(ex_alufunct3_i), .alufunct7_i(ex_alufunct7_i),
		.reg1_i(ex_reg1_i), .reg2_i(ex_reg2_i), .imm_i(ex_imm_i),
		.wreg_i(ex_wreg_i), .wd_i(ex_wd_i),
		
		.aluop_o(ex_aluop_o), .alufunct3_o(ex_alufunct3_o),
		.me_o(ex_me_o), .maddr_o(ex_maddr_o), 
		.wreg_o(ex_wreg_o), .wd_o(ex_wd_o), .wdata_o(ex_wdata_o),
		
		.wreg_f(ex_wreg_f), .wd_f(ex_wd_f), .wdata_f(ex_wdata_f)
		
	);
 
	ex_mem ex_mem0(
		.clk(clk), .rst(rst),
		
		.ce(ram_ce_o),
		
		.ex_aluop(ex_aluop_o), .ex_alufunct3(ex_alufunct3_o),
		.ex_me(ex_me_o), .ex_maddr(ex_maddr_o),
		.ex_wreg(ex_wreg_o), .ex_wd(ex_wd_o), .ex_wdata(ex_wdata_o),
		
		.mem_aluop(mem_aluop_i), .mem_alufunct3(mem_alufunct3_i),
		.mem_me(mem_me_i), .mem_maddr(mem_maddr_i),	
		.mem_wd(mem_wd_i), .mem_wreg(mem_wreg_i), .mem_wdata(mem_wdata_i)
	);
	
	mem mem0(
		.rst(rst),
		
		.aluop_i(mem_aluop_i), .alufunct3_i(mem_alufunct3_i), 
		.me_i(mem_me_i), .maddr_i(mem_maddr_i),
		.wreg_i(mem_wreg_i), .wd_i(mem_wd_i), .wdata_i(mem_wdata_i),
		
		.re_m(ram_re_m), .rvalid_bit(ram_rvalid_bit), .raddr_m(ram_raddr_m), .rdata_m(ram_rdata_m),
		.we_m(ram_we_m), .wvalid_bit(ram_wvalid_bit), .waddr_m(ram_waddr_m), .wdata_m(ram_wdata_m),
		
		.wreg_o(mem_wreg_o), .wd_o(mem_wd_o), .wdata_o(mem_wdata_o),
		.wreg_f(mem_wreg_f), .wd_f(mem_wd_f), .wdata_f(mem_wdata_f)
	);
	
	mem_wb mem_wb0(
		.clk(clk), .rst(rst),
		
		.mem_wd(mem_wd_o), .mem_wreg(mem_wreg_o), .mem_wdata(mem_wdata_o),
		.wb_wd(wb_wd_o), .wb_wreg(wb_wreg_o), .wb_wdata(wb_wdata_o)
	);
	
endmodule
module riscv(

	input wire clk,
	input wire rst,
	

	output wire rom_ce_o,
	input wire[`InstBus] rom_data_i,
	output wire[`InstAddrBus] rom_addr_o,


	input wire req_if,
	

	output wire ram_ce_o,
	

	output wire ram_re_m,
	output wire[`ValidBitBus] ram_rvalid_bit,
	output wire[`MemAddrBus] ram_raddr_m,
	input wire[`DataBus] ram_rdata_m,
	output wire ram_we_m,
	output wire[`ValidBitBus] ram_wvalid_bit,
	output wire[`MemAddrBus] ram_waddr_m,
	output wire[`DataBus] ram_wdata_m
);


	wire[`CtrlWidth] stall;
	

	wire[`InstAddrBus] pc;	
	

	wire[`InstAddrBus] id_pc_i;		 
	wire[`InstBus] id_inst_i;	
	

	wire reg1_suc;
	wire[`RegBus] reg1_data;
	wire reg2_suc;
	wire[`RegBus] reg2_data;
	

	wire reg1_read;
	wire reg2_read;
	wire[`RegAddrBus] reg1_addr;
	wire[`RegAddrBus] reg2_addr;
	

	wire req_id;


	wire[`InstAddrBus] id_pc_o;
	wire[`AluOpBus] id_aluop_o;
	wire[`AluFunct3Bus] id_alufunct3_o;
	wire[`AluFunct7Bus] id_alufunct7_o;
	wire[`RegBus] id_reg1_o;
	wire[`RegBus] id_reg2_o;
	wire[`RegBus] id_imm_o;
	wire id_wreg_o;
	wire[`RegAddrBus] id_wd_o;
	

	wire jump_o;
	wire[`InstAddrBus] jpc_o;
	

	wire[`InstAddrBus] ex_pc_i;
	wire[`AluOpBus] ex_aluop_i;
	wire[`AluFunct3Bus] ex_alufunct3_i;
	wire[`AluFunct7Bus] ex_alufunct7_i;
	wire[`RegBus] ex_reg1_i;
	wire[`RegBus] ex_reg2_i;
	wire[`RegBus] ex_imm_i;
	wire ex_wreg_i;
	wire[`RegAddrBus] ex_wd_i;


	wire[`AluOpBus] ex_aluop_o;
	wire[`AluFunct3Bus] ex_alufunct3_o;
	wire ex_me_o;
	wire[`MemAddrBus] ex_maddr_o;
	wire ex_wreg_o;
	wire[`RegAddrBus] ex_wd_o;
	wire[`RegBus] ex_wdata_o;	
	

	wire ex_wreg_f;
	wire[`RegAddrBus] ex_wd_f;
	wire[`RegBus] ex_wdata_f;
	

	wire[`AluOpBus] mem_aluop_i;
	wire[`AluFunct3Bus] mem_alufunct3_i;
	wire mem_me_i;				
	wire[`MemAddrBus] mem_maddr_i;
	wire mem_wreg_i;
	wire[`RegAddrBus] mem_wd_i;
	wire[`RegBus] mem_wdata_i;	


	wire mem_wreg_o;
	wire[`RegAddrBus] mem_wd_o;
	wire[`RegBus] mem_wdata_o;
	

	wire mem_wreg_f;
	wire[`RegAddrBus] mem_wd_f;
	wire[`RegBus] mem_wdata_f;
	

	wire[`RegAddrBus] wb_wd_o;
	wire wb_wreg_o;
	wire[`RegBus] wb_wdata_o;
	
	ctrl ctrl0(
		.rst(rst), 
		.req_id(req_id), .req_if(req_if),
		.stall(stall)		
	);

	pc_reg pc_reg0(
		.clk(clk), .rst(rst),
		.stall(stall),
		.jumpout(jump_o), .pc_i(jpc_o),
		.pc(pc), .ce(rom_ce_o)
	);	


	assign rom_addr_o = pc;
	
	if_id if_id0(
		.clk(clk), .rst(rst),
		.stall(stall), .jumpout(jump_o),
		.if_pc(pc),	.if_inst(rom_data_i),
		.id_pc(id_pc_i), .id_inst(id_inst_i)		
	);	
	
	id id0(
		.rst(rst),
		
		.pc_i(id_pc_i), .inst_i(id_inst_i),	
		
		.reg1_suc(reg1_suc), .reg2_suc(reg2_suc),
		.reg1_data_i(reg1_data), .reg2_data_i(reg2_data), 
		
		.reg1_read_o(reg1_read), .reg2_read_o(reg2_read),
		.reg1_addr_o(reg1_addr), .reg2_addr_o(reg2_addr),
		
		.pc_o(id_pc_o), .aluop_o(id_aluop_o),
		.alufunct3_o(id_alufunct3_o), .alufunct7_o(id_alufunct7_o),
		.reg1_o(id_reg1_o), .reg2_o(id_reg2_o), .imm_o(id_imm_o),
		.wd_o(id_wd_o), .wreg_o(id_wreg_o),
		
		.stall_req(req_id),
		
		.jump_o(jump_o), .jpc_o(jpc_o)

	);
	
	regfile regfile0(
		.clk(clk), .rst(rst),
		
		.we(wb_wreg_o), .waddr(wb_wd_o), .wdata(wb_wdata_o),
		.ex_we(ex_wreg_f), .ex_waddr(ex_wd_f), .ex_wdata(ex_wdata_f),
		.mem_we(mem_wreg_f), .mem_waddr(mem_wd_f), .mem_wdata(mem_wdata_f),
		
		.re1(reg1_read), .raddr1(reg1_addr), .rsuc1(reg1_suc), .rdata1(reg1_data),
		.re2(reg2_read), .raddr2(reg2_addr), .rsuc2(reg2_suc), .rdata2(reg2_data)
	
	);
	
	id_ex id_ex0(
		.clk(clk), .rst(rst),
		
		.id_pc(id_pc_o), .id_aluop(id_aluop_o), 
		.id_alufunct3(id_alufunct3_o), .id_alufunct7(id_alufunct7_o),
		.id_reg1(id_reg1_o), .id_reg2(id_reg2_o), .id_imm(id_imm_o), 
		.id_wreg(id_wreg_o), .id_wd(id_wd_o),
		
		.ex_pc(ex_pc_i), .ex_aluop(ex_aluop_i),
		.ex_alufunct3(ex_alufunct3_i), .ex_alufunct7(ex_alufunct7_i),
		.ex_reg1(ex_reg1_i), .ex_reg2(ex_reg2_i), .ex_imm(ex_imm_i),
		.ex_wreg(ex_wreg_i), .ex_wd(ex_wd_i),
		
		.stall(stall)
	);
	
	ex ex0(
		.rst(rst),
		
		.pc_i(ex_pc_i), .aluop_i(ex_aluop_i),
		.alufunct3_i(ex_alufunct3_i), .alufunct7_i(ex_alufunct7_i),
		.reg1_i(ex_reg1_i), .reg2_i(ex_reg2_i), .imm_i(ex_imm_i),
		.wreg_i(ex_wreg_i), .wd_i(ex_wd_i),
		
		.aluop_o(ex_aluop_o), .alufunct3_o(ex_alufunct3_o),
		.me_o(ex_me_o), .maddr_o(ex_maddr_o), 
		.wreg_o(ex_wreg_o), .wd_o(ex_wd_o), .wdata_o(ex_wdata_o),
		
		.wreg_f(ex_wreg_f), .wd_f(ex_wd_f), .wdata_f(ex_wdata_f)
		
	);
 
	ex_mem ex_mem0(
		.clk(clk), .rst(rst),
		
		.ce(ram_ce_o),
		
		.ex_aluop(ex_aluop_o), .ex_alufunct3(ex_alufunct3_o),
		.ex_me(ex_me_o), .ex_maddr(ex_maddr_o),
		.ex_wreg(ex_wreg_o), .ex_wd(ex_wd_o), .ex_wdata(ex_wdata_o),
		
		.mem_aluop(mem_aluop_i), .mem_alufunct3(mem_alufunct3_i),
		.mem_me(mem_me_i), .mem_maddr(mem_maddr_i),	
		.mem_wd(mem_wd_i), .mem_wreg(mem_wreg_i), .mem_wdata(mem_wdata_i)
	);
	
	mem mem0(
		.rst(rst),
		
		.aluop_i(mem_aluop_i), .alufunct3_i(mem_alufunct3_i), 
		.me_i(mem_me_i), .maddr_i(mem_maddr_i),
		.wreg_i(mem_wreg_i), .wd_i(mem_wd_i), .wdata_i(mem_wdata_i),
		
		.re_m(ram_re_m), .rvalid_bit(ram_rvalid_bit), .raddr_m(ram_raddr_m), .rdata_m(ram_rdata_m),
		.we_m(ram_we_m), .wvalid_bit(ram_wvalid_bit), .waddr_m(ram_waddr_m), .wdata_m(ram_wdata_m),
		
		.wreg_o(mem_wreg_o), .wd_o(mem_wd_o), .wdata_o(mem_wdata_o),
		.wreg_f(mem_wreg_f), .wd_f(mem_wd_f), .wdata_f(mem_wdata_f)
	);
	
	mem_wb mem_wb0(
		.clk(clk), .rst(rst),
		
		.mem_wd(mem_wd_o), .mem_wreg(mem_wreg_o), .mem_wdata(mem_wdata_o),
		.wb_wd(wb_wd_o), .wb_wreg(wb_wreg_o), .wb_wdata(wb_wdata_o)
	);
	
endmodule