data/full_repos/permissive/108561032/control3.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/dc7e414c-0691-4170-9f4b-cb8771ec7e24.xml
module control3(reset,Control,clk,MemaReg,EscrReg);

    input wire [9:0] Control;
    input clk;
    input reset;
    



    output reg MemaReg;



    output reg EscrReg;

    

  

always   @(posedge clk)
begin
if (reset == 1)
    begin


    end
else 
    begin


    end



MemaReg      = Control[6];


EscrReg      = Control[5];



end     
endmodule
module control3(reset,Control,clk,MemaReg,EscrReg);


    input wire [9:0] Control;
    input clk;
    input reset;
    



    output reg MemaReg;



    output reg EscrReg;

    

  

always   @(posedge clk)
begin
if (reset == 1)
    begin


    end
else 
    begin


    end



MemaReg      = Control[6];


EscrReg      = Control[5];



end     
endmodule