data/full_repos/permissive/174323821/hdl/cpu/jtframe_sys6809.v
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1: b"%Error: data/full_repos/permissive/174323821/hdl/cpu/jtframe_sys6809.v:73: Cannot find file containing module: 'jtframe_z80wait'\n    jtframe_z80wait #(1) u_wait(\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174323821/hdl/cpu,data/full_repos/permissive/174323821/jtframe_z80wait\n             data/full_repos/permissive/174323821/hdl/cpu,data/full_repos/permissive/174323821/jtframe_z80wait.v\n             data/full_repos/permissive/174323821/hdl/cpu,data/full_repos/permissive/174323821/jtframe_z80wait.sv\n             jtframe_z80wait\n             jtframe_z80wait.v\n             jtframe_z80wait.sv\n             obj_dir/jtframe_z80wait\n             obj_dir/jtframe_z80wait.v\n             obj_dir/jtframe_z80wait.sv\n%Error: data/full_repos/permissive/174323821/hdl/cpu/jtframe_sys6809.v:229: Cannot find file containing module: 'jtframe_dual_ram'\n            jtframe_dual_ram #(.aw(RAM_AW)) u_ram(\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/174323821/hdl/cpu/jtframe_sys6809.v:253: Cannot find file containing module: 'mc6809i'\n    mc6809i u_cpu(\n    ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module jtframe_6809wait(
    input           rstn,
    input           clk,
    input           cen,
    output          cpu_cen,
    input           dev_busy,
    input           rom_cs,
    input           rom_ok,
    output reg      cen_E,
    output reg      cen_Q
);
    parameter RECOVERY=1;


    wire        gate;
    reg         last_EQ;
    wire        EQ;
    reg  [ 1:0] cencnt=2'd0;
    reg         last_cen;
    reg  [ 3:0] misses;
    wire        catchup;

    assign cpu_cen = cen_Q;
    assign EQ      = cen_E | cen_Q;
    assign catchup = RECOVERY && misses>0;

    always @(posedge clk) if(cen) begin
        last_EQ   <= EQ;
        if( gate ) last_cen <= cencnt[1];
        if( gate || cencnt[1]==last_cen ) begin
            if( !catchup )
                cencnt <= cencnt+2'd1;
            else begin
                cencnt <= {~cencnt[1],1'b0};
                misses <= misses-4'd1;
            end
        end else if(!gate) begin
            if( !last_EQ && !EQ && !(&misses) && !dev_busy)
                misses <= misses+4'd1;
        end
        if( !rstn ) begin
            misses  <= 4'd0;
        end
    end

    always @(*) begin
        cen_E = cencnt==2'b00 && cen && gate;
        cen_Q = cencnt==2'b10 && cen && gate;
    end

    jtframe_z80wait #(1) u_wait(
        .rst_n      ( rstn      ),
        .clk        ( clk       ),
        .cen_in     ( cen       ),
        .cen_out    (           ),
        .gate       ( gate      ),

        .dev_busy   ( dev_busy  ),

        .mreq_n     ( 1'b0      ),
        .iorq_n     ( 1'b0      ),
        .busak_n    ( 1'b0      ),

        .rom_cs     ( rom_cs    ),
        .rom_ok     ( rom_ok    )
    );
endmodule
module jtframe_6809wait(
    input           rstn,
    input           clk,
    input           cen,
    output          cpu_cen,
    input           dev_busy,
    input           rom_cs,
    input           rom_ok,
    output reg      cen_E,
    output reg      cen_Q
);

    parameter RECOVERY=1;


    wire        gate;
    reg         last_EQ;
    wire        EQ;
    reg  [ 1:0] cencnt=2'd0;
    reg         last_cen;
    reg  [ 3:0] misses;
    wire        catchup;

    assign cpu_cen = cen_Q;
    assign EQ      = cen_E | cen_Q;
    assign catchup = RECOVERY && misses>0;

    always @(posedge clk) if(cen) begin
        last_EQ   <= EQ;
        if( gate ) last_cen <= cencnt[1];
        if( gate || cencnt[1]==last_cen ) begin
            if( !catchup )
                cencnt <= cencnt+2'd1;
            else begin
                cencnt <= {~cencnt[1],1'b0};
                misses <= misses-4'd1;
            end
        end else if(!gate) begin
            if( !last_EQ && !EQ && !(&misses) && !dev_busy)
                misses <= misses+4'd1;
        end
        if( !rstn ) begin
            misses  <= 4'd0;
        end
    end

    always @(*) begin
        cen_E = cencnt==2'b00 && cen && gate;
        cen_Q = cencnt==2'b10 && cen && gate;
    end

    jtframe_z80wait #(1) u_wait(
        .rst_n      ( rstn      ),
        .clk        ( clk       ),
        .cen_in     ( cen       ),
        .cen_out    (           ),
        .gate       ( gate      ),

        .dev_busy   ( dev_busy  ),

        .mreq_n     ( 1'b0      ),
        .iorq_n     ( 1'b0      ),
        .busak_n    ( 1'b0      ),

        .rom_cs     ( rom_cs    ),
        .rom_ok     ( rom_ok    )
    );
endmodule