data/full_repos/permissive/120669553/counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:57: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'first\' generates 4 bits.\n                                                                 : ... In instance counter\n                sseg = first;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:63: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'second\' generates 4 bits.\n                                                                 : ... In instance counter\n                sseg = second;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:75: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:75: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:75: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:75: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:75: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:75: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h5\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:75: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h6\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:75: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h7\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:75: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:75: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h5\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h6\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h7\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:89: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n                                                                 : ... In instance counter\n            case(sseg)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/120669553/counter.v:74: Operator EQ expects 7 bits on the RHS, but RHS\'s VARREF \'second\' generates 4 bits.\n                                                                 : ... In instance counter\n        if(sseg == second) begin\n                ^~\n%Error: Exiting due to 23 warning(s)\n'
module counter(
    input clock,
    input reset,
    output a1,
    output a2,
    output b1,
    output b2,
    output c1,
    output c2,
    output d1,
    output d2,
    output e1,
    output e2,
    output f1,
    output f2,
    output g1,
    output g2,
    output reg [3:0]first,
    output reg [3:0]second
);

wire [3:0]an;

always @ (posedge clock or posedge reset)
    begin
        if (reset) begin
            first <= 0;
            second <= 0;
    end else if (first==4'd9) begin
        first <= 0;
        if (second == 4'd9)
            second <= 0;
        else
            second <= second + 1;
    end else
    first <= first + 1;
  end

localparam N = 18;
reg [N-1:0]count;

always @ (posedge clock or posedge reset)
    begin
        if (reset)
            count <= 0;
        else
            count <= count + 1;
    end

reg [6:0]sseg;
reg [3:0]an_temp;
always @ (*)
    begin
        case(count[N-1:N-2])
            2'b00:
            begin
                sseg = first;
                an_temp = 4'b1110;
            end

            2'b01:
            begin
                sseg = second;
                an_temp = 4'b1101;
            end
        endcase
    end
assign an = an_temp;

reg [6:0] sseg_temp1;
reg [6:0] sseg_temp2;
always @ (*)
    begin
        if(sseg == second) begin
            case(sseg)
                4'd0 : sseg_temp1 = 7'b1000000;
                4'd1 : sseg_temp1 = 7'b1111001;
                4'd2 : sseg_temp1 = 7'b0100100;
                4'd3 : sseg_temp1 = 7'b0110000;
                4'd4 : sseg_temp1 = 7'b0011001;
                4'd5 : sseg_temp1 = 7'b0010010;
                4'd6 : sseg_temp1 = 7'b0000010;
                4'd7 : sseg_temp1 = 7'b1111000;
                4'd8 : sseg_temp1 = 7'b0000000;
                4'd9 : sseg_temp1 = 7'b0010000;
                default : sseg_temp1 = 7'b0111111;
            endcase
        end else begin
            case(sseg)
                4'd0 : sseg_temp2 = 7'b1000000;
                4'd1 : sseg_temp2 = 7'b1111001;
                4'd2 : sseg_temp2 = 7'b0100100;
                4'd3 : sseg_temp2 = 7'b0110000;
                4'd4 : sseg_temp2 = 7'b0011001;
                4'd5 : sseg_temp2 = 7'b0010010;
                4'd6 : sseg_temp2 = 7'b0000010;
                4'd7 : sseg_temp2 = 7'b1111000;
                4'd8 : sseg_temp2 = 7'b0000000;
                4'd9 : sseg_temp2 = 7'b0010000;
                default : sseg_temp2 = 7'b0111111;
            endcase
        end
    end

assign {g1, f1, e1, d1, c1, b1, a1} = sseg_temp1;
assign {g2, f2, e2, d2, c2, b2, a2} = sseg_temp2;

endmodule
module counter(
    input clock,
    input reset,
    output a1,
    output a2,
    output b1,
    output b2,
    output c1,
    output c2,
    output d1,
    output d2,
    output e1,
    output e2,
    output f1,
    output f2,
    output g1,
    output g2,
    output reg [3:0]first,
    output reg [3:0]second
);


wire [3:0]an;

always @ (posedge clock or posedge reset)
    begin
        if (reset) begin
            first <= 0;
            second <= 0;
    end else if (first==4'd9) begin
        first <= 0;
        if (second == 4'd9)
            second <= 0;
        else
            second <= second + 1;
    end else
    first <= first + 1;
  end

localparam N = 18;
reg [N-1:0]count;

always @ (posedge clock or posedge reset)
    begin
        if (reset)
            count <= 0;
        else
            count <= count + 1;
    end

reg [6:0]sseg;
reg [3:0]an_temp;
always @ (*)
    begin
        case(count[N-1:N-2])
            2'b00:
            begin
                sseg = first;
                an_temp = 4'b1110;
            end

            2'b01:
            begin
                sseg = second;
                an_temp = 4'b1101;
            end
        endcase
    end
assign an = an_temp;

reg [6:0] sseg_temp1;
reg [6:0] sseg_temp2;
always @ (*)
    begin
        if(sseg == second) begin
            case(sseg)
                4'd0 : sseg_temp1 = 7'b1000000;
                4'd1 : sseg_temp1 = 7'b1111001;
                4'd2 : sseg_temp1 = 7'b0100100;
                4'd3 : sseg_temp1 = 7'b0110000;
                4'd4 : sseg_temp1 = 7'b0011001;
                4'd5 : sseg_temp1 = 7'b0010010;
                4'd6 : sseg_temp1 = 7'b0000010;
                4'd7 : sseg_temp1 = 7'b1111000;
                4'd8 : sseg_temp1 = 7'b0000000;
                4'd9 : sseg_temp1 = 7'b0010000;
                default : sseg_temp1 = 7'b0111111;
            endcase
        end else begin
            case(sseg)
                4'd0 : sseg_temp2 = 7'b1000000;
                4'd1 : sseg_temp2 = 7'b1111001;
                4'd2 : sseg_temp2 = 7'b0100100;
                4'd3 : sseg_temp2 = 7'b0110000;
                4'd4 : sseg_temp2 = 7'b0011001;
                4'd5 : sseg_temp2 = 7'b0010010;
                4'd6 : sseg_temp2 = 7'b0000010;
                4'd7 : sseg_temp2 = 7'b1111000;
                4'd8 : sseg_temp2 = 7'b0000000;
                4'd9 : sseg_temp2 = 7'b0010000;
                default : sseg_temp2 = 7'b0111111;
            endcase
        end
    end

assign {g1, f1, e1, d1, c1, b1, a1} = sseg_temp1;
assign {g2, f2, e2, d2, c2, b2, a2} = sseg_temp2;

endmodule