data/full_repos/permissive/171930001/box/test.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/171930001/box/test.v:8: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("simulation/test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/171930001/box/test.v:9: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/171930001/box/test.v:11: Unsupported: Ignoring delay on this delayed statement.\n    # 40 rst = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/171930001/box/test.v:12: Unsupported: Ignoring delay on this delayed statement.\n    # 48000000 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/171930001/box/test.v:16: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = !clk;\n       ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

reg rst = 1;

initial begin
    $dumpfile("simulation/test.vcd");
    $dumpvars(0, test);

    # 40 rst = 0;
    # 48000000 $finish;
end

reg clk = 1;
always #10 clk = !clk;

wire blanking_wire;
wire vsync_wire;
wire [9:0] x;
wire [9:0] y;
wire[2:0] rgb_wire;

digital_video gpdi(
    .clk_25mhz(clk),
    .rst(rst),
    .red(8'd80),
    .green(8'd80),
    .blue(8'd80),
    .xout(x),
    .yout(y),
    .vsync_out(vsync_wire),
    .rgbout(rgb_wire)
);

endmodule
module test;


reg rst = 1;

initial begin
    $dumpfile("simulation/test.vcd");
    $dumpvars(0, test);

    # 40 rst = 0;
    # 48000000 $finish;
end

reg clk = 1;
always #10 clk = !clk;

wire blanking_wire;
wire vsync_wire;
wire [9:0] x;
wire [9:0] y;
wire[2:0] rgb_wire;

digital_video gpdi(
    .clk_25mhz(clk),
    .rst(rst),
    .red(8'd80),
    .green(8'd80),
    .blue(8'd80),
    .xout(x),
    .yout(y),
    .vsync_out(vsync_wire),
    .rgbout(rgb_wire)
);

endmodule