data/full_repos/permissive/131831582/MUX/muxDesign.v
data/verilator_xmls/87e8f73a-898f-4d6e-a16c-5f1c040db0e8.xml
module muxDesign(d0, d1, s, out);
input wire d0, d1, s;
output reg out;

always @ (d0 or d1 or s) begin
	if (s == 1'b0) begin
		out = d0;
	end else begin
		out = d1;
	end
end

endmodule
module muxDesign(d0, d1, s, out);

input wire d0, d1, s;
output reg out;

always @ (d0 or d1 or s) begin
	if (s == 1'b0) begin
		out = d0;
	end else begin
		out = d1;
	end
end

endmodule