data/full_repos/permissive/169266176/spiflash.v
1: b"%Error: data/full_repos/permissive/169266176/spiflash.v:220: Cannot find file containing module: 'ODDR2'\nODDR2 #(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/169266176,data/full_repos/permissive/169266176/ODDR2\n             data/full_repos/permissive/169266176,data/full_repos/permissive/169266176/ODDR2.v\n             data/full_repos/permissive/169266176,data/full_repos/permissive/169266176/ODDR2.sv\n             ODDR2\n             ODDR2.v\n             ODDR2.sv\n             obj_dir/ODDR2\n             obj_dir/ODDR2.v\n             obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s)\n"
module spiflash(
    input clk,
    input [7:0] din,
    output [7:0] dout,
    input [23:0] Addr,
    input [7:0] cmd,
    input active,
    input ack,
	 input reset,
    output busy,
    output flash_ck,
    output reg flash_cs,
    output flash_si,
    input wire flash_so
    );

initial 
begin
flash_cs=1'b1;	
end

reg [6:0] flash_state=IDLE;
reg [7:0] shiftreg;
reg [2:0] shiftcount=0;
reg flash_clken=1'b0;
reg flash_so_reg;


localparam IDLE= 7'b0000001;
localparam CMD = 7'b0000010;
localparam AH  = 7'b0000100;
localparam AM  = 7'b0001000;
localparam AL  = 7'b0010000;
localparam TX  = 7'b0100000;
localparam RX  = 7'b1000000;

localparam PP=8'h02;
localparam READ=8'h03;
localparam WRDI=8'h04;
localparam RDSR=8'h05;
localparam WREN=8'h06;
localparam SE=8'h20;
localparam RDSCUR=8'h2b;
localparam CLSR=8'h30;
localparam RDID=8'h9f;
localparam DP=8'hb9;
localparam RDP=8'hab;

always @(posedge clk)
	begin
	if(reset)
		flash_state<=IDLE;
	else
		case(flash_state)
			IDLE:	begin
					if(active & ack)
						begin
						flash_state<=CMD;
						flash_clken<=1'b1;
						flash_cs<=1'b0;
						shiftreg<=cmd;
						end
					else 
						begin 
						flash_clken<=1'b0;
						end
					end
			CMD:	begin
					shiftreg[7:0]<={shiftreg[6:0],flash_so_reg};	
					shiftcount<=shiftcount+3'b1;
					if(shiftcount==3'b111)
						begin
						if(cmd==READ || cmd==PP || cmd==SE)
							begin
							flash_state<=AH;
							shiftreg<=Addr[23:16];
							end
						else if(cmd==RDSR || cmd==RDSCUR || cmd==RDID)
							begin
							flash_state<=RX;
							end
						else
							begin
							flash_state<=IDLE;
							flash_clken<=1'b0;
							flash_cs<=1'b1;
							end
						end
					end
			AH:	begin
					shiftreg[7:0]<={shiftreg[6:0],flash_so_reg};	
					shiftcount<=shiftcount+3'b1;
					if(shiftcount==3'b111)
						begin
						flash_state<=AM;
						shiftreg<=Addr[15:8];
						end
					end
			AM:	begin
					shiftreg[7:0]<={shiftreg[6:0],flash_so_reg};	
					shiftcount<=shiftcount+3'b1;					
					if(shiftcount==3'b111)
						begin
						flash_state<=AL;
						shiftreg<=Addr[7:0];
						end
					end
			AL:	begin
					shiftreg[7:0]<={shiftreg[6:0],flash_so_reg};	
					shiftcount<=shiftcount+3'b1;					
					if(shiftcount==3'b111)
						begin
						if(cmd==PP)
							begin
							flash_state<=TX;
							shiftreg<=din;
							end
						if(cmd==READ)
							begin
							flash_state<=RX;
							end
						if(cmd==SE)
							begin
							flash_state<=IDLE;
							flash_clken<=1'b0;
							flash_cs<=1'b1;
							end
						end
					end
			TX:	begin
					if(flash_clken)
						begin
						shiftreg[7:0]<={shiftreg[6:0],flash_so_reg};	
						shiftcount<=shiftcount+3'b1;
						if(shiftcount==3'b111)
							begin
							flash_clken<=1'b0;
							end
						end
					else
						begin								
						if(active & ack)
							begin
							flash_clken<=1'b1;
							flash_state<=TX;
							shiftreg<=din;
							end
						if(~active & ack)
							begin
							flash_state<=IDLE;
							flash_cs<=1'b1;
							end
						end
					end
			RX:	begin
					if(flash_clken)
						begin
						shiftreg[7:0]<={shiftreg[6:0],flash_so_reg};	
						shiftcount<=shiftcount+3'b1;
						if(shiftcount==3'b111)
							begin
							flash_clken<=1'b0;
							end
						end
					else
						begin
						if(active & ack)
							begin
							flash_clken<=1'b1;
							flash_state<=RX;
							end
						if(~active & ack)
							begin
							flash_state<=IDLE;
							flash_cs<=1'b1;
							end
						end
					end
		endcase
 end
 

always @(negedge clk) begin
	if(flash_clken)
		flash_so_reg<=flash_so;
end

assign busy=flash_clken;
assign flash_si=shiftreg[7];
assign dout=shiftreg;


ODDR2 #(
      .DDR_ALIGNMENT("NONE"),
      .INIT(1'b0),
      .SRTYPE("SYNC")
   ) ODDR2_sdram (
      .Q(flash_ck),
      .C0(clk),
      .C1(~clk),
      .CE(flash_clken),
      .D0(1'b0),
      .D1(1'b1),
      .R(1'b0),
      .S(1'b0)
   );



endmodule
module spiflash(
    input clk,
    input [7:0] din,
    output [7:0] dout,
    input [23:0] Addr,
    input [7:0] cmd,
    input active,
    input ack,
	 input reset,
    output busy,
    output flash_ck,
    output reg flash_cs,
    output flash_si,
    input wire flash_so
    );


initial 
begin
flash_cs=1'b1;	
end

reg [6:0] flash_state=IDLE;
reg [7:0] shiftreg;
reg [2:0] shiftcount=0;
reg flash_clken=1'b0;
reg flash_so_reg;


localparam IDLE= 7'b0000001;
localparam CMD = 7'b0000010;
localparam AH  = 7'b0000100;
localparam AM  = 7'b0001000;
localparam AL  = 7'b0010000;
localparam TX  = 7'b0100000;
localparam RX  = 7'b1000000;

localparam PP=8'h02;
localparam READ=8'h03;
localparam WRDI=8'h04;
localparam RDSR=8'h05;
localparam WREN=8'h06;
localparam SE=8'h20;
localparam RDSCUR=8'h2b;
localparam CLSR=8'h30;
localparam RDID=8'h9f;
localparam DP=8'hb9;
localparam RDP=8'hab;

always @(posedge clk)
	begin
	if(reset)
		flash_state<=IDLE;
	else
		case(flash_state)
			IDLE:	begin
					if(active & ack)
						begin
						flash_state<=CMD;
						flash_clken<=1'b1;
						flash_cs<=1'b0;
						shiftreg<=cmd;
						end
					else 
						begin 
						flash_clken<=1'b0;
						end
					end
			CMD:	begin
					shiftreg[7:0]<={shiftreg[6:0],flash_so_reg};	
					shiftcount<=shiftcount+3'b1;
					if(shiftcount==3'b111)
						begin
						if(cmd==READ || cmd==PP || cmd==SE)
							begin
							flash_state<=AH;
							shiftreg<=Addr[23:16];
							end
						else if(cmd==RDSR || cmd==RDSCUR || cmd==RDID)
							begin
							flash_state<=RX;
							end
						else
							begin
							flash_state<=IDLE;
							flash_clken<=1'b0;
							flash_cs<=1'b1;
							end
						end
					end
			AH:	begin
					shiftreg[7:0]<={shiftreg[6:0],flash_so_reg};	
					shiftcount<=shiftcount+3'b1;
					if(shiftcount==3'b111)
						begin
						flash_state<=AM;
						shiftreg<=Addr[15:8];
						end
					end
			AM:	begin
					shiftreg[7:0]<={shiftreg[6:0],flash_so_reg};	
					shiftcount<=shiftcount+3'b1;					
					if(shiftcount==3'b111)
						begin
						flash_state<=AL;
						shiftreg<=Addr[7:0];
						end
					end
			AL:	begin
					shiftreg[7:0]<={shiftreg[6:0],flash_so_reg};	
					shiftcount<=shiftcount+3'b1;					
					if(shiftcount==3'b111)
						begin
						if(cmd==PP)
							begin
							flash_state<=TX;
							shiftreg<=din;
							end
						if(cmd==READ)
							begin
							flash_state<=RX;
							end
						if(cmd==SE)
							begin
							flash_state<=IDLE;
							flash_clken<=1'b0;
							flash_cs<=1'b1;
							end
						end
					end
			TX:	begin
					if(flash_clken)
						begin
						shiftreg[7:0]<={shiftreg[6:0],flash_so_reg};	
						shiftcount<=shiftcount+3'b1;
						if(shiftcount==3'b111)
							begin
							flash_clken<=1'b0;
							end
						end
					else
						begin								
						if(active & ack)
							begin
							flash_clken<=1'b1;
							flash_state<=TX;
							shiftreg<=din;
							end
						if(~active & ack)
							begin
							flash_state<=IDLE;
							flash_cs<=1'b1;
							end
						end
					end
			RX:	begin
					if(flash_clken)
						begin
						shiftreg[7:0]<={shiftreg[6:0],flash_so_reg};	
						shiftcount<=shiftcount+3'b1;
						if(shiftcount==3'b111)
							begin
							flash_clken<=1'b0;
							end
						end
					else
						begin
						if(active & ack)
							begin
							flash_clken<=1'b1;
							flash_state<=RX;
							end
						if(~active & ack)
							begin
							flash_state<=IDLE;
							flash_cs<=1'b1;
							end
						end
					end
		endcase
 end
 

always @(negedge clk) begin
	if(flash_clken)
		flash_so_reg<=flash_so;
end

assign busy=flash_clken;
assign flash_si=shiftreg[7];
assign dout=shiftreg;


ODDR2 #(
      .DDR_ALIGNMENT("NONE"),
      .INIT(1'b0),
      .SRTYPE("SYNC")
   ) ODDR2_sdram (
      .Q(flash_ck),
      .C0(clk),
      .C1(~clk),
      .CE(flash_clken),
      .D0(1'b0),
      .D1(1'b1),
      .R(1'b0),
      .S(1'b0)
   );



endmodule