data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_ADC.v
1: b'%Warning-WIDTH: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_ADC.v:73: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_WIDTH\' generates 32 or 6 bits.\n                                                                                                                      : ... In instance AUDIO_ADC\n  bit_index = DATA_WIDTH;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_ADC.v:89: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DATA_WIDTH\' generates 32 or 6 bits.\n                                                                                                                      : ... In instance AUDIO_ADC\n    bit_index = DATA_WIDTH;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_ADC.v:99: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'bit_index\' generates 5 bits.\n                                                                                                                      : ... In instance AUDIO_ADC\n   if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))\n                                      ^~\n%Error: data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules/AUDIO_ADC.v:122: Cannot find file containing module: \'audio_fifo\'\naudio_fifo adc_fifo(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules,data/full_repos/permissive/107757225/audio_fifo\n             data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules,data/full_repos/permissive/107757225/audio_fifo.v\n             data/full_repos/permissive/107757225/audio/audio-altera/audio_nios/synthesis/submodules,data/full_repos/permissive/107757225/audio_fifo.sv\n             audio_fifo\n             audio_fifo.v\n             audio_fifo.sv\n             obj_dir/audio_fifo\n             obj_dir/audio_fifo.v\n             obj_dir/audio_fifo.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module AUDIO_ADC(

	clk,
	reset,
	read,
	readdata,

	empty,
	clear,

	bclk,
	adclrc,
	adcdat
);


parameter	DATA_WIDTH = 32;


input							clk;
input							reset;
input							read;
output	[(DATA_WIDTH-1):0]		readdata;


output							empty;
input							clear;

input							bclk;
input							adclrc;
input							adcdat;






reg		[4:0]					bit_index;
reg								valid_bit;
reg								reg_adc_left;
reg		[(DATA_WIDTH-1):0]		reg_adc_serial_data;

reg		[(DATA_WIDTH-1):0]		adcfifo_writedata;
reg								adcfifo_write;
wire							adcfifo_full;
reg								wait_one_clk;








wire is_left_ch;
assign is_left_ch = ~adclrc;
always @ (posedge bclk) 
begin
	if (reset || clear)
	begin
		bit_index = DATA_WIDTH;
		reg_adc_left = is_left_ch;
		adcfifo_write = 1'b0;
		valid_bit = 0;
	end
	else
	begin
		if (adcfifo_write)
			adcfifo_write = 1'b0;

		if (reg_adc_left ^ is_left_ch)
		begin
			reg_adc_left = is_left_ch;
			valid_bit = 1'b1;
			wait_one_clk = 1'b1;
			if (reg_adc_left)
				bit_index = DATA_WIDTH;
		end


		if (valid_bit && wait_one_clk)  
				wait_one_clk = 1'b0;
		else if (valid_bit && !wait_one_clk)  		
		begin
			bit_index = bit_index - 1'b1;
			reg_adc_serial_data[bit_index] = adcdat;
			if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))
			begin	
				if (bit_index == 0 && !adcfifo_full)
				begin
					adcfifo_writedata = reg_adc_serial_data;
					adcfifo_write = 1'b1;
				end
				valid_bit = 0;
			end
		end			
	end
end







audio_fifo adc_fifo(

	.wrclk(bclk),
	.wrreq(adcfifo_write),
	.data(adcfifo_writedata),
	.wrfull(adcfifo_full),
	.aclr(clear),

	.rdclk(clk),
	.rdreq(read),
	.q(readdata),
	.rdempty(empty)
);	


endmodule
module AUDIO_ADC(

	clk,
	reset,
	read,
	readdata,

	empty,
	clear,

	bclk,
	adclrc,
	adcdat
);



parameter	DATA_WIDTH = 32;


input							clk;
input							reset;
input							read;
output	[(DATA_WIDTH-1):0]		readdata;


output							empty;
input							clear;

input							bclk;
input							adclrc;
input							adcdat;






reg		[4:0]					bit_index;
reg								valid_bit;
reg								reg_adc_left;
reg		[(DATA_WIDTH-1):0]		reg_adc_serial_data;

reg		[(DATA_WIDTH-1):0]		adcfifo_writedata;
reg								adcfifo_write;
wire							adcfifo_full;
reg								wait_one_clk;








wire is_left_ch;
assign is_left_ch = ~adclrc;
always @ (posedge bclk) 
begin
	if (reset || clear)
	begin
		bit_index = DATA_WIDTH;
		reg_adc_left = is_left_ch;
		adcfifo_write = 1'b0;
		valid_bit = 0;
	end
	else
	begin
		if (adcfifo_write)
			adcfifo_write = 1'b0;

		if (reg_adc_left ^ is_left_ch)
		begin
			reg_adc_left = is_left_ch;
			valid_bit = 1'b1;
			wait_one_clk = 1'b1;
			if (reg_adc_left)
				bit_index = DATA_WIDTH;
		end


		if (valid_bit && wait_one_clk)  
				wait_one_clk = 1'b0;
		else if (valid_bit && !wait_one_clk)  		
		begin
			bit_index = bit_index - 1'b1;
			reg_adc_serial_data[bit_index] = adcdat;
			if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))
			begin	
				if (bit_index == 0 && !adcfifo_full)
				begin
					adcfifo_writedata = reg_adc_serial_data;
					adcfifo_write = 1'b1;
				end
				valid_bit = 0;
			end
		end			
	end
end







audio_fifo adc_fifo(

	.wrclk(bclk),
	.wrreq(adcfifo_write),
	.data(adcfifo_writedata),
	.wrfull(adcfifo_full),
	.aclr(clear),

	.rdclk(clk),
	.rdreq(read),
	.q(readdata),
	.rdempty(empty)
);	


endmodule