data/full_repos/permissive/2084115/projects/ultra96v2_display_port_test/sim/design_1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_display_port_test/sim/design_1.v:59: Unsupported: Ignoring delay on this delayed statement.\n    initial #100 reset = 0;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/ultra96v2_display_port_test/sim/design_1.v:62: Unsupported: Ignoring delay on this delayed statement.\n    always #(RATE150/2.0) clk150 <= ~clk150;\n           ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module design_1
   (dp_video_ref_clk_0,
    dp_external_custom_event1_0,
    dp_external_custom_event2_0,
    dp_external_vsync_event_0,
    dp_live_gfx_alpha_in_0,
    dp_live_gfx_pixel1_in_0,
    dp_live_video_de_out_0,
    dp_live_video_in_de_0,
    dp_live_video_in_hsync_0,
    dp_live_video_in_pixel1_0,
    dp_live_video_in_vsync_0,
    dp_video_in_clk_0,
    dp_video_out_hsync_0,
    dp_video_out_pixel1_0,
    dp_video_out_vsync_0,
    pl_clk0_0);
  output dp_video_ref_clk_0;
  input dp_external_custom_event1_0;
  input dp_external_custom_event2_0;
  input dp_external_vsync_event_0;
  input [7:0]dp_live_gfx_alpha_in_0;
  input [35:0]dp_live_gfx_pixel1_in_0;
  output dp_live_video_de_out_0;
  input dp_live_video_in_de_0;
  input dp_live_video_in_hsync_0;
  input [35:0]dp_live_video_in_pixel1_0;
  input dp_live_video_in_vsync_0;
  input dp_video_in_clk_0;
  output dp_video_out_hsync_0;
  output [35:0]dp_video_out_pixel1_0;
  output dp_video_out_vsync_0;
  output pl_clk0_0;

  wire dp_external_custom_event1_0;
  wire dp_external_custom_event2_0;
  wire dp_external_vsync_event_0;
  wire [7:0]dp_live_gfx_alpha_in_0;
  wire [35:0]dp_live_gfx_pixel1_in_0;
  wire dp_live_video_de_out_0;
  wire dp_live_video_in_de_0;
  wire dp_live_video_in_hsync_0;
  wire [35:0]dp_live_video_in_pixel1_0;
  wire dp_live_video_in_vsync_0;
  wire dp_video_in_clk_0;
  wire dp_video_out_hsync_0;
  wire [35:0]dp_video_out_pixel1_0;
  wire dp_video_out_vsync_0;
  wire pl_clk0_0;
  
  
  
    localparam RATE150 = 1000.0/150.00;
    
    reg         reset = 1;
    initial #100 reset = 0;
    
    reg         clk150 = 1'b1;
    always #(RATE150/2.0) clk150 <= ~clk150;
    
    assign pl_clk0_0 = clk150;
    
    
endmodule
module design_1
   (dp_video_ref_clk_0,
    dp_external_custom_event1_0,
    dp_external_custom_event2_0,
    dp_external_vsync_event_0,
    dp_live_gfx_alpha_in_0,
    dp_live_gfx_pixel1_in_0,
    dp_live_video_de_out_0,
    dp_live_video_in_de_0,
    dp_live_video_in_hsync_0,
    dp_live_video_in_pixel1_0,
    dp_live_video_in_vsync_0,
    dp_video_in_clk_0,
    dp_video_out_hsync_0,
    dp_video_out_pixel1_0,
    dp_video_out_vsync_0,
    pl_clk0_0);

  output dp_video_ref_clk_0;
  input dp_external_custom_event1_0;
  input dp_external_custom_event2_0;
  input dp_external_vsync_event_0;
  input [7:0]dp_live_gfx_alpha_in_0;
  input [35:0]dp_live_gfx_pixel1_in_0;
  output dp_live_video_de_out_0;
  input dp_live_video_in_de_0;
  input dp_live_video_in_hsync_0;
  input [35:0]dp_live_video_in_pixel1_0;
  input dp_live_video_in_vsync_0;
  input dp_video_in_clk_0;
  output dp_video_out_hsync_0;
  output [35:0]dp_video_out_pixel1_0;
  output dp_video_out_vsync_0;
  output pl_clk0_0;

  wire dp_external_custom_event1_0;
  wire dp_external_custom_event2_0;
  wire dp_external_vsync_event_0;
  wire [7:0]dp_live_gfx_alpha_in_0;
  wire [35:0]dp_live_gfx_pixel1_in_0;
  wire dp_live_video_de_out_0;
  wire dp_live_video_in_de_0;
  wire dp_live_video_in_hsync_0;
  wire [35:0]dp_live_video_in_pixel1_0;
  wire dp_live_video_in_vsync_0;
  wire dp_video_in_clk_0;
  wire dp_video_out_hsync_0;
  wire [35:0]dp_video_out_pixel1_0;
  wire dp_video_out_vsync_0;
  wire pl_clk0_0;
  
  
  
    localparam RATE150 = 1000.0/150.00;
    
    reg         reset = 1;
    initial #100 reset = 0;
    
    reg         clk150 = 1'b1;
    always #(RATE150/2.0) clk150 <= ~clk150;
    
    assign pl_clk0_0 = clk150;
    
    
endmodule