data/full_repos/permissive/151863926/src/delay.v
1: b'%Error: data/full_repos/permissive/151863926/src/delay.v:40: [0:1] Range extract has backward bit ordering, perhaps you wanted [1:0]\n                                                           : ... In instance delay_reg.DELAY_REG[0].delay_reg_unit\n            shift_reg <= { data_in, shift_reg[DELAY-1:1]  };\n                                             ^\n%Error: data/full_repos/permissive/151863926/src/delay.v:40: Extracting 2 bits from only 1 bit number\n                                                           : ... In instance delay_reg.DELAY_REG[0].delay_reg_unit\n            shift_reg <= { data_in, shift_reg[DELAY-1:1]  };\n                                             ^\n%Warning-SELRANGE: data/full_repos/permissive/151863926/src/delay.v:40: Selection index out of range: 2:1 outside 0:0\n                                                                      : ... In instance delay_reg.DELAY_REG[0].delay_reg_unit\n            shift_reg <= { data_in, shift_reg[DELAY-1:1]  };\n                                             ^\n                   ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/151863926/src/delay.v:40: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                   : ... In instance delay_reg.DELAY_REG[0].delay_reg_unit\n            shift_reg <= { data_in, shift_reg[DELAY-1:1]  };\n                      ^~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module delay1( data_in, we, clk, data_out);
    parameter DELAY = 1;

    input data_in;
    input we;
    input clk;
    output data_out;

    reg [DELAY-1:0] shift_reg;

    always @(posedge clk)
        if(we)
            shift_reg <= { data_in, shift_reg[DELAY-1:1]  };

    assign data_out = shift_reg[0];
    
    initial begin
        shift_reg <= 0;
    end
    
endmodule
module delay1( data_in, we, clk, data_out);

    parameter DELAY = 1;

    input data_in;
    input we;
    input clk;
    output data_out;

    reg [DELAY-1:0] shift_reg;

    always @(posedge clk)
        if(we)
            shift_reg <= { data_in, shift_reg[DELAY-1:1]  };

    assign data_out = shift_reg[0];
    
    initial begin
        shift_reg <= 0;
    end
    
endmodule