data/full_repos/permissive/139213403/FPGA/edge_trigger_testbench.v
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/edge_trigger_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/edge_trigger_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/edge_trigger_testbench.v:22: syntax error, unexpected \'@\'\n   @(negedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/edge_trigger_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/edge_trigger_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #(T);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/edge_trigger_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n   #(T * 2);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/edge_trigger_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n   #(T);\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/edge_trigger_testbench.v:43: syntax error, unexpected \'@\'\n   @(negedge reset);\n   ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module edge_trigger_testbench;
	localparam T = 20;

	reg clk, reset;
	reg in, en;
	wire tick;
	
	edge_trigger uut(.clk(clk), .reset(reset), .in(in), .en(en), .tick(tick));
		

	always
		begin
			clk = 1'b1;
			#(T / 2);
			clk = 1'b0;
			#(T / 2);
		end
	

	initial
		begin
			@(negedge clk);
			reset = 1'b1;
			#(T / 2);
			reset = 1'b0;
		end
		
	task edge_test;
		input reg i_en;
		begin
			en = i_en;
			in = ~en;
			#(T);
			in = en;
			#(T * 2);
			in = ~en;
			#(T);
		end
	endtask
		
	initial
		begin
			@(negedge reset);
			
			edge_test(0);
			edge_test(1);
			edge_test(1);
			edge_test(0);
			edge_test(0);
			
			$stop;
		end
endmodule
module edge_trigger_testbench;

	localparam T = 20;

	reg clk, reset;
	reg in, en;
	wire tick;
	
	edge_trigger uut(.clk(clk), .reset(reset), .in(in), .en(en), .tick(tick));
		

	always
		begin
			clk = 1'b1;
			#(T / 2);
			clk = 1'b0;
			#(T / 2);
		end
	

	initial
		begin
			@(negedge clk);
			reset = 1'b1;
			#(T / 2);
			reset = 1'b0;
		end
		
	task edge_test;
		input reg i_en;
		begin
			en = i_en;
			in = ~en;
			#(T);
			in = en;
			#(T * 2);
			in = ~en;
			#(T);
		end
	endtask
		
	initial
		begin
			@(negedge reset);
			
			edge_test(0);
			edge_test(1);
			edge_test(1);
			edge_test(0);
			edge_test(0);
			
			$stop;
		end
endmodule