data/full_repos/permissive/106029354/verilog_source/mem_program.v
1: b'%Error: data/full_repos/permissive/106029354/verilog_source/mem_program.v:10: Cannot find include file: params_proc.v\n`include "params_proc.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n             params_proc.v\n             params_proc.v.v\n             params_proc.v.sv\n             obj_dir/params_proc.v\n             obj_dir/params_proc.v.v\n             obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n'
module mem_program(
	clk,
    we,
	addr,
    data_in,
	data_out
);


`include "params_proc.v"


input clk, we;
input [INSTR_WIDTH-1:0] data_in;
input [MEM_WIDTH-1:0] addr;

output reg [INSTR_WIDTH-1:0] data_out;


reg [INSTR_WIDTH-1:0] ram [0:(1<<MEM_WIDTH)-1];


always @(posedge clk) begin
	if (we) begin
        ram[addr] <= data_in;

        data_out  <= data_in;
    end else begin
        data_out <= ram[addr];
    end
end


initial begin
	$readmemb("../assembler/program.bin", ram);
end

endmodule
module mem_program(
	clk,
    we,
	addr,
    data_in,
	data_out
);



`include "params_proc.v"


input clk, we;
input [INSTR_WIDTH-1:0] data_in;
input [MEM_WIDTH-1:0] addr;

output reg [INSTR_WIDTH-1:0] data_out;


reg [INSTR_WIDTH-1:0] ram [0:(1<<MEM_WIDTH)-1];


always @(posedge clk) begin
	if (we) begin
        ram[addr] <= data_in;

        data_out  <= data_in;
    end else begin
        data_out <= ram[addr];
    end
end


initial begin
	$readmemb("../assembler/program.bin", ram);
end

endmodule