data/full_repos/permissive/143278/ivltests/unary_minus3.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/unary_minus3.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #1 if (neg_test !== (-test)) begin\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

   reg  [7:0]  test;
   wire [7:0]  neg_test = -test;

   initial begin
      for (test = 0 ;  test < 255 ;  test = test + 1) begin
	 #1 if (neg_test !== (-test)) begin
	    $display("FAILED -- %b !== -%b", neg_test, test);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule
module test();


   reg  [7:0]  test;
   wire [7:0]  neg_test = -test;

   initial begin
      for (test = 0 ;  test < 255 ;  test = test + 1) begin
	 #1 if (neg_test !== (-test)) begin
	    $display("FAILED -- %b !== -%b", neg_test, test);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule