data/full_repos/permissive/129989088/um.v
 line:285: before: "."
1: b'%Error: data/full_repos/permissive/129989088/um.v:90: Cannot find file containing module: \'L4_Parser\'\nL4_Parser L4parser(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129989088,data/full_repos/permissive/129989088/L4_Parser\n             data/full_repos/permissive/129989088,data/full_repos/permissive/129989088/L4_Parser.v\n             data/full_repos/permissive/129989088,data/full_repos/permissive/129989088/L4_Parser.sv\n             L4_Parser\n             L4_Parser.v\n             L4_Parser.sv\n             obj_dir/L4_Parser\n             obj_dir/L4_Parser.v\n             obj_dir/L4_Parser.sv\n%Error: data/full_repos/permissive/129989088/um.v:114: Cannot find file containing module: \'uniman_top\'\nuniman_top uniman(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/129989088/um.v:273: Cannot find file containing module: \'fifo\'\nfifo pkt_buffer(\n^~~~\n%Error: data/full_repos/permissive/129989088/um.v:289: Cannot find file containing module: \'fifo\'\nfifo action_buffer(\n^~~~\n%Error: data/full_repos/permissive/129989088/um.v:305: Cannot find file containing module: \'fifo\'\nfifo tag_buffer(\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/129989088/um.v:336: Operator CASE expects 2 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 1 bits.\n                                                             : ... In instance um\n  case(state)\n  ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/129989088/um.v:336: Operator CASE expects 2 bits on the Case Item, but Case Item\'s CONST \'1\'h0\' generates 1 bits.\n                                                             : ... In instance um\n  case(state)\n  ^~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
function [3:0] cal_egressPort;
input	[3:0]	ingressPort;
begin
	cal_egressPort = (ingressPort == 4'd0)? 4'd2:4'd1;
end
endfunction
function [3:0] cal_egressPort;

input	[3:0]	ingressPort;
begin
	cal_egressPort = (ingressPort == 4'd0)? 4'd2:4'd1;
end
endfunction