data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v
 line:13: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #8736 rx = data[0];\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #8736 rx = data[1];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n #8736 rx = data[2];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #8736 rx = data[3];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #8736 rx = data[4];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #8736 rx = data[5];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #8736 rx = data[6];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #8736 rx = data[7];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #8736 rx = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n forever #42 clk = ~clk;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #100 rst = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #100000 rx_task(8\'b10101010);\n ^\n%Error: data/full_repos/permissive/162106151/picorv32_cyc10/pico_tb.v:45: Cannot find file containing module: \'pico_cyc10_top\'\npico_cyc10_top uo(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162106151/picorv32_cyc10,data/full_repos/permissive/162106151/pico_cyc10_top\n             data/full_repos/permissive/162106151/picorv32_cyc10,data/full_repos/permissive/162106151/pico_cyc10_top.v\n             data/full_repos/permissive/162106151/picorv32_cyc10,data/full_repos/permissive/162106151/pico_cyc10_top.sv\n             pico_cyc10_top\n             pico_cyc10_top.v\n             pico_cyc10_top.sv\n             obj_dir/pico_cyc10_top\n             obj_dir/pico_cyc10_top.v\n             obj_dir/pico_cyc10_top.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pico_tb;

reg clk, rst, rx;
wire tx;
wire [7:0] led;
wire [8:0] seg;




task rx_task(input [7:0] data);
	begin
	rx = 0;
	#8736 rx = data[0];
	#8736 rx = data[1];
	#8736 rx = data[2];
	#8736 rx = data[3];
	#8736 rx = data[4];
	#8736 rx = data[5];
	#8736 rx = data[6];
	#8736 rx = data[7];
	#8736 rx = 1;
	end
endtask



initial begin
	clk = 0;
	forever #42 clk = ~clk;
end

initial begin
	rst = 0;
	#100 rst = 1;
end

initial begin
	rx = 1;
	#100000 rx_task(8'b10101010);
end

pico_cyc10_top uo(
	.clk(clk),
	.rst_n(rst),
	.rx(rx),
	.tx(tx),
	.led(led),
	.seg(seg)
);


endmodule
module pico_tb;


reg clk, rst, rx;
wire tx;
wire [7:0] led;
wire [8:0] seg;




task rx_task(input [7:0] data);
	begin
	rx = 0;
	#8736 rx = data[0];
	#8736 rx = data[1];
	#8736 rx = data[2];
	#8736 rx = data[3];
	#8736 rx = data[4];
	#8736 rx = data[5];
	#8736 rx = data[6];
	#8736 rx = data[7];
	#8736 rx = 1;
	end
endtask



initial begin
	clk = 0;
	forever #42 clk = ~clk;
end

initial begin
	rst = 0;
	#100 rst = 1;
end

initial begin
	rx = 1;
	#100000 rx_task(8'b10101010);
end

pico_cyc10_top uo(
	.clk(clk),
	.rst_n(rst),
	.rx(rx),
	.tx(tx),
	.led(led),
	.seg(seg)
);


endmodule