data/full_repos/permissive/190698744/7 - Sequential Logic/1 - Latches & Flipflops/7 - D Latch.v
1: b'%Error: Invalid Option: -\n'
module top_module (
    input d, 
    input ena,
    output q);
	




    always @ (*) begin
        if (ena) q<=d;
    end

endmodule
module top_module (
    input d, 
    input ena,
    output q);

	




    always @ (*) begin
        if (ena) q<=d;
    end

endmodule