data/full_repos/permissive/16507090/bus/bus.v
 line:19: before: "]"
1: b'%Error: data/full_repos/permissive/16507090/bus/bus.v:1: Cannot find include file: fifo/fifo.v\n`include "fifo/fifo.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/16507090/bus,data/full_repos/permissive/16507090/fifo/fifo.v\n             data/full_repos/permissive/16507090/bus,data/full_repos/permissive/16507090/fifo/fifo.v.v\n             data/full_repos/permissive/16507090/bus,data/full_repos/permissive/16507090/fifo/fifo.v.sv\n             fifo/fifo.v\n             fifo/fifo.v.v\n             fifo/fifo.v.sv\n             obj_dir/fifo/fifo.v\n             obj_dir/fifo/fifo.v.v\n             obj_dir/fifo/fifo.v.sv\n%Error: Exiting due to 1 error(s)\n'
module BusTester
#(

	parameter bus_width=32,
	parameter bus_max_devices=16,
	parameter bus_buffer_size=32,
	parameter device_id=1,
	parameter send_to=2
)
(

	input clk,
	inout [bus_width-1:0] bus_data,
	inout [bus_max_devices-1:0] bus_receiver,
	inout [bus_max_devices-1:0] bus_write_request,
	inout [bus_max_devices-1:0] bus_buffer_full,
	input [bus_max_devices-1:0] bus_voice
);
	wire [bus_width-1:0]		bus_in;
	wire [bus_max_devices-1:0]	bus_source;
	wire [bus_width-1:0]		bus_out;
	reg [bus_max_devices-1:0]	bus_target;
	wire bus_next;
	wire bus_send;
	wire bus_input_empty;
	wire bus_input_full;
	wire bus_output_empty;
	wire bus_output_full;

	BusClient
	#(
		.bus_width(bus_width),
		.bus_max_devices(bus_max_devices),
		.bus_buffer_size(bus_buffer_size),
		.device_id(device_id)
	) bus_client
	(
		clk,
		bus_data,
		bus_receiver,
		bus_write_request,
		bus_buffer_full,
		bus_voice,
		bus_in,
		bus_source,
		bus_out,
		bus_target,
		bus_next,
		bus_send,
		bus_input_empty,
		bus_input_full,
		bus_output_empty,
		bus_output_full
	);

	reg [31:0] counter;
	assign bus_out=counter;
	assign bus_target=1<<send_to;

	always @(negedge clk) begin
		if (device_id==2) begin
			bus_send<=1;
			bus_next<=0;
			counter<=counter+1;
			$display("BusTester %d: sending %d to %d",device_id,bus_out,bus_target);
		end
		else if (device_id==8) begin
			bus_send<=0;
			if (~bus_input_empty) begin
				bus_next<=1;
				$display("BusTester %d: received %d from %d",device_id,bus_in,bus_source);
			end
			else begin
				bus_next<=0;
				$display("BusTester %d: input buffer empty",device_id);
			end
		end
		else
			$display("BusTester: id==%d",device_id);
	end
endmodule
module BusTester
#(

	parameter bus_width=32,
	parameter bus_max_devices=16,
	parameter bus_buffer_size=32,
	parameter device_id=1,
	parameter send_to=2
)
(

	input clk,
	inout [bus_width-1:0] bus_data,
	inout [bus_max_devices-1:0] bus_receiver,
	inout [bus_max_devices-1:0] bus_write_request,
	inout [bus_max_devices-1:0] bus_buffer_full,
	input [bus_max_devices-1:0] bus_voice
);

	wire [bus_width-1:0]		bus_in;
	wire [bus_max_devices-1:0]	bus_source;
	wire [bus_width-1:0]		bus_out;
	reg [bus_max_devices-1:0]	bus_target;
	wire bus_next;
	wire bus_send;
	wire bus_input_empty;
	wire bus_input_full;
	wire bus_output_empty;
	wire bus_output_full;

	BusClient
	#(
		.bus_width(bus_width),
		.bus_max_devices(bus_max_devices),
		.bus_buffer_size(bus_buffer_size),
		.device_id(device_id)
	) bus_client
	(
		clk,
		bus_data,
		bus_receiver,
		bus_write_request,
		bus_buffer_full,
		bus_voice,
		bus_in,
		bus_source,
		bus_out,
		bus_target,
		bus_next,
		bus_send,
		bus_input_empty,
		bus_input_full,
		bus_output_empty,
		bus_output_full
	);

	reg [31:0] counter;
	assign bus_out=counter;
	assign bus_target=1<<send_to;

	always @(negedge clk) begin
		if (device_id==2) begin
			bus_send<=1;
			bus_next<=0;
			counter<=counter+1;
			$display("BusTester %d: sending %d to %d",device_id,bus_out,bus_target);
		end
		else if (device_id==8) begin
			bus_send<=0;
			if (~bus_input_empty) begin
				bus_next<=1;
				$display("BusTester %d: received %d from %d",device_id,bus_in,bus_source);
			end
			else begin
				bus_next<=0;
				$display("BusTester %d: input buffer empty",device_id);
			end
		end
		else
			$display("BusTester: id==%d",device_id);
	end
endmodule