data/full_repos/permissive/182333580/software/ip/TERASIC_IR_RX_FIFO/TERASIC_IR_RX_FIFO.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/182333580/software/ip/TERASIC_IR_RX_FIFO/TERASIC_IR_RX_FIFO.v:84: Signal definition not found, creating implicitly: \'read\'\n                                                                                                              : ... Suggested alternative: \'s_read\'\nassign   read= ( s_read && (s_address == 0) ) ?1:0;\n         ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/182333580/software/ip/TERASIC_IR_RX_FIFO/TERASIC_IR_RX_FIFO.v:90: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'use_dw\' generates 8 bits.\n                                                                                                           : ... In instance TERASIC_IR_RX_FIFO\n  s_readdata <= use_dw;\n             ^~\n%Error: data/full_repos/permissive/182333580/software/ip/TERASIC_IR_RX_FIFO/TERASIC_IR_RX_FIFO.v:114: Cannot find file containing module: \'ir_fifo\'\nir_fifo ir_fifo_inst(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/182333580/software/ip/TERASIC_IR_RX_FIFO,data/full_repos/permissive/182333580/ir_fifo\n             data/full_repos/permissive/182333580/software/ip/TERASIC_IR_RX_FIFO,data/full_repos/permissive/182333580/ir_fifo.v\n             data/full_repos/permissive/182333580/software/ip/TERASIC_IR_RX_FIFO,data/full_repos/permissive/182333580/ir_fifo.sv\n             ir_fifo\n             ir_fifo.v\n             ir_fifo.sv\n             obj_dir/ir_fifo\n             obj_dir/ir_fifo.v\n             obj_dir/ir_fifo.sv\n%Error: data/full_repos/permissive/182333580/software/ip/TERASIC_IR_RX_FIFO/TERASIC_IR_RX_FIFO.v:129: Cannot find file containing module: \'IRDA_RECEIVE_Terasic\'\nIRDA_RECEIVE_Terasic IRDA_RECEIVE_Terasic_inst(\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module TERASIC_IR_RX_FIFO(
	clk,
	reset_n,
	

	irq,
	

	s_address,
	s_cs_n,
	s_read,
	s_readdata,
	s_write,
	s_writedata,
	

	ir
	
);

`define IR_RX_DATA_REG 	0
`define IR_RX_CS_REG   	1

input                   s_address;
input			clk;
input			reset_n;
output	reg		irq;
input			s_cs_n;
input			s_read;
output 	[31:0]      	s_readdata;
input			s_write;
input	[31:0]	        s_writedata;
input			ir;

reg     [31:0] 	        s_readdata;
reg			fifo_clear;
wire    [7:0]           use_dw;
wire    [31:0]          writedata;
wire    [31:0]          readdata;



wire data_ready;

reg	pre_data_ready;
always @ (posedge clk or negedge reset_n)
begin
	if (~reset_n)
		pre_data_ready <= 1'b0;
	else
		pre_data_ready <= data_ready;
end



always @ (posedge clk or negedge reset_n)
begin
	if (~reset_n)
		irq <= 1'b0;
	else if (~pre_data_ready & data_ready )
		irq <= 1'b1;
	else if (s_write && (s_address == `IR_RX_CS_REG))
		irq <=~s_writedata[1]; 
end



always @ (clk)
begin
	if (~reset_n)
		fifo_clear <= 1'b0;
	else if (s_write && (s_address == `IR_RX_CS_REG))
		fifo_clear <= s_writedata[0];
	else if (fifo_clear)
		fifo_clear <= 1'b0;
end





assign   read= ( s_read && (s_address == `IR_RX_DATA_REG) ) ?1:0;
always @ (clk)
begin
	if (~reset_n)
		 s_readdata <=32'b0;
	else if (s_read && (s_address == `IR_RX_CS_REG))
		s_readdata <= use_dw;
	
	else if (read && (s_address == `IR_RX_DATA_REG ))
	   s_readdata <= readdata;
		
	else
		 s_readdata <=32'b0;


end

reg    write;
always @ (posedge clk or negedge reset_n)
begin
	if (~reset_n)
		write <= 1'b0;
	else if (~pre_data_ready & data_ready )
		write <= 1'b1;
	else if (write)
		write <=0; 
end



ir_fifo ir_fifo_inst(
	.aclr(fifo_clear),
	
	.data(writedata),
	.wrclk(clk),
	.wrreq(write),

   .rdclk(clk),
	.rdreq(read),
	.q(readdata),
	.rdusedw(use_dw),
	.rdempty()
	
);

IRDA_RECEIVE_Terasic IRDA_RECEIVE_Terasic_inst(
					.iCLK(clk),
					.iRST_n(reset_n),
					
					.iIRDA(ir),
					
				   .oDATA_REAY(data_ready),
					.oDATA(writedata)
					);


endmodule
module TERASIC_IR_RX_FIFO(
	clk,
	reset_n,
	

	irq,
	

	s_address,
	s_cs_n,
	s_read,
	s_readdata,
	s_write,
	s_writedata,
	

	ir
	
);


`define IR_RX_DATA_REG 	0
`define IR_RX_CS_REG   	1

input                   s_address;
input			clk;
input			reset_n;
output	reg		irq;
input			s_cs_n;
input			s_read;
output 	[31:0]      	s_readdata;
input			s_write;
input	[31:0]	        s_writedata;
input			ir;

reg     [31:0] 	        s_readdata;
reg			fifo_clear;
wire    [7:0]           use_dw;
wire    [31:0]          writedata;
wire    [31:0]          readdata;



wire data_ready;

reg	pre_data_ready;
always @ (posedge clk or negedge reset_n)
begin
	if (~reset_n)
		pre_data_ready <= 1'b0;
	else
		pre_data_ready <= data_ready;
end



always @ (posedge clk or negedge reset_n)
begin
	if (~reset_n)
		irq <= 1'b0;
	else if (~pre_data_ready & data_ready )
		irq <= 1'b1;
	else if (s_write && (s_address == `IR_RX_CS_REG))
		irq <=~s_writedata[1]; 
end



always @ (clk)
begin
	if (~reset_n)
		fifo_clear <= 1'b0;
	else if (s_write && (s_address == `IR_RX_CS_REG))
		fifo_clear <= s_writedata[0];
	else if (fifo_clear)
		fifo_clear <= 1'b0;
end





assign   read= ( s_read && (s_address == `IR_RX_DATA_REG) ) ?1:0;
always @ (clk)
begin
	if (~reset_n)
		 s_readdata <=32'b0;
	else if (s_read && (s_address == `IR_RX_CS_REG))
		s_readdata <= use_dw;
	
	else if (read && (s_address == `IR_RX_DATA_REG ))
	   s_readdata <= readdata;
		
	else
		 s_readdata <=32'b0;


end

reg    write;
always @ (posedge clk or negedge reset_n)
begin
	if (~reset_n)
		write <= 1'b0;
	else if (~pre_data_ready & data_ready )
		write <= 1'b1;
	else if (write)
		write <=0; 
end



ir_fifo ir_fifo_inst(
	.aclr(fifo_clear),
	
	.data(writedata),
	.wrclk(clk),
	.wrreq(write),

   .rdclk(clk),
	.rdreq(read),
	.q(readdata),
	.rdusedw(use_dw),
	.rdempty()
	
);

IRDA_RECEIVE_Terasic IRDA_RECEIVE_Terasic_inst(
					.iCLK(clk),
					.iRST_n(reset_n),
					
					.iIRDA(ir),
					
				   .oDATA_REAY(data_ready),
					.oDATA(writedata)
					);


endmodule