data/full_repos/permissive/187464337/five_stage_pipelined_computer/pipeline_registers.v
None: at end of input
1: b'%Warning-MULTITOP: data/full_repos/permissive/187464337/five_stage_pipelined_computer/pipeline_registers.v:20: Multiple top level modules\n                                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                             : ... Top module \'if_id_reg\'\nmodule if_id_reg(\n       ^~~~~~~~~\n                                                                                                             : ... Top module \'id_ex_reg\'\nmodule id_ex_reg(\n       ^~~~~~~~~\n                                                                                                             : ... Top module \'ex_mem_reg\'\nmodule ex_mem_reg(\n       ^~~~~~~~~~\n                                                                                                             : ... Top module \'mem_wb_reg\'\nmodule mem_wb_reg(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module mem_wb_reg(
   input clk, input wreg_in, input m2reg_in, input [31:0] alu_result_in,
   input [31:0] mem_data_in, input [4:0] write_reg_num_in,
   output reg wreg, output reg m2reg, output reg [31:0] alu_result,
   output reg [31:0] mem_data, output reg [4:0] write_reg_num
);
   always @(posedge clk) begin
      wreg <= wreg_in;
      m2reg <= m2reg_in;
      alu_result <= alu_result_in;
      mem_data <= mem_data_in;
      write_reg_num <= write_reg_num_in;
   end
endmodule
module mem_wb_reg(
   input clk, input wreg_in, input m2reg_in, input [31:0] alu_result_in,
   input [31:0] mem_data_in, input [4:0] write_reg_num_in,
   output reg wreg, output reg m2reg, output reg [31:0] alu_result,
   output reg [31:0] mem_data, output reg [4:0] write_reg_num
);

   always @(posedge clk) begin
      wreg <= wreg_in;
      m2reg <= m2reg_in;
      alu_result <= alu_result_in;
      mem_data <= mem_data_in;
      write_reg_num <= write_reg_num_in;
   end
endmodule