data/full_repos/permissive/143278/ivltests/undef_lval_select_SV.v
 line:7: before: "["
data/verilator_xmls/fd131d98-2696-4a97-b44c-90ee9c37ed4c.xml
module top;
  reg pass;
  reg [1:-1][3:0] vec;

  initial begin
    pass = 1'b1;

    vec[1] = 4'bxxxx;
    vec[0] = 4'bxxxx;
    vec[-1] = 4'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
    vec[1'bx] = 4'b1001;
`endif
    if ((vec[1] !== 4'bxxx) && (vec[0] !== 4'bxxxx) &&
        (vec[-1] !== 4'bxxxx)) begin
      $display("Failed vec[1'bx], expected 4'bxxxx, got %b, %b,%b",
               vec[1], vec[0], vec[-1]);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;
  reg [1:-1][3:0] vec;

  initial begin
    pass = 1'b1;

    vec[1] = 4'bxxxx;
    vec[0] = 4'bxxxx;
    vec[-1] = 4'bxxxx;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
    vec[1'bx] = 4'b1001;
`endif
    if ((vec[1] !== 4'bxxx) && (vec[0] !== 4'bxxxx) &&
        (vec[-1] !== 4'bxxxx)) begin
      $display("Failed vec[1'bx], expected 4'bxxxx, got %b, %b,%b",
               vec[1], vec[0], vec[-1]);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule