data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_register.v
None: at end of input
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_register.v:59: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/dbg_if,data/full_repos/permissive/17099167/timescale.v\n             data/full_repos/permissive/17099167/system/hardware/cores/dbg_if,data/full_repos/permissive/17099167/timescale.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/dbg_if,data/full_repos/permissive/17099167/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n'
module dbg_register (
                      data_in, 
                      data_out, 
                      write, 
                      clk, 
                      reset
                    );


parameter WIDTH = 8;
parameter RESET_VALUE = 0;


input   [WIDTH-1:0] data_in;
input               write;
input               clk;
input               reset;

output  [WIDTH-1:0] data_out;
reg     [WIDTH-1:0] data_out;



always @ (posedge clk or posedge reset)
begin
  if(reset)
    data_out[WIDTH-1:0] <=  RESET_VALUE;
  else if(write)
    data_out[WIDTH-1:0] <=  data_in[WIDTH-1:0];
end


endmodule
module dbg_register (
                      data_in, 
                      data_out, 
                      write, 
                      clk, 
                      reset
                    );



parameter WIDTH = 8;
parameter RESET_VALUE = 0;


input   [WIDTH-1:0] data_in;
input               write;
input               clk;
input               reset;

output  [WIDTH-1:0] data_out;
reg     [WIDTH-1:0] data_out;



always @ (posedge clk or posedge reset)
begin
  if(reset)
    data_out[WIDTH-1:0] <=  RESET_VALUE;
  else if(write)
    data_out[WIDTH-1:0] <=  data_in[WIDTH-1:0];
end


endmodule