data/full_repos/permissive/142810315/rtl/axil_crossbar_addr.v
 line:102: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/142810315/rtl/axil_crossbar_addr.v:138: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s SEL generates 32 bits.\n                                                                                 : ... In instance axil_crossbar_addr\n        if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin\n                                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/142810315/rtl/axil_crossbar_addr.v:146: Logical Operator IF expects 1 bit on the If, but If\'s SEL generates 32 bits.\n                                                                                 : ... In instance axil_crossbar_addr\n        if (M_ADDR_WIDTH[i*32 +: 32]) begin\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/142810315/rtl/axil_crossbar_addr.v:174: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s SEL generates 32 bits.\n                                                                                 : ... In instance axil_crossbar_addr\n            if (M_ADDR_WIDTH[i*32 +: 32] && M_ADDR_WIDTH[j*32 +: 32]) begin\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/142810315/rtl/axil_crossbar_addr.v:174: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s SEL generates 32 bits.\n                                                                                 : ... In instance axil_crossbar_addr\n            if (M_ADDR_WIDTH[i*32 +: 32] && M_ADDR_WIDTH[j*32 +: 32]) begin\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/142810315/rtl/axil_crossbar_addr.v:252: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                 : ... In instance axil_crossbar_addr\n                            m_select_next = i;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/142810315/rtl/axil_crossbar_addr.v:251: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s SEL generates 32 bits.\n                                                                                 : ... In instance axil_crossbar_addr\n                        if (M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32] && (!M_SECURE[i] || !s_axil_aprot[1]) && (M_CONNECT & (1 << (S+i*S_COUNT))) && (s_axil_aaddr >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32]) == (M_BASE_ADDR_INT[(i*M_REGIONS+j)*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32])) begin\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/142810315/rtl/axil_crossbar_addr.v:251: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s AND generates 32 or 16 bits.\n                                                                                 : ... In instance axil_crossbar_addr\n                        if (M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32] && (!M_SECURE[i] || !s_axil_aprot[1]) && (M_CONNECT & (1 << (S+i*S_COUNT))) && (s_axil_aaddr >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32]) == (M_BASE_ADDR_INT[(i*M_REGIONS+j)*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32])) begin\n                                                                                                         ^~\n%Error: Exiting due to 7 warning(s)\n'
function [M_COUNT*M_REGIONS*ADDR_WIDTH-1:0] calcBaseAddrs(input [31:0] dummy);
    integer i;
    reg [ADDR_WIDTH-1:0] base;
    reg [ADDR_WIDTH-1:0] width;
    reg [ADDR_WIDTH-1:0] size;
    reg [ADDR_WIDTH-1:0] mask;
    begin
        calcBaseAddrs = {M_COUNT*M_REGIONS*ADDR_WIDTH{1'b0}};
        base = 0;
        for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
            width = M_ADDR_WIDTH[i*32 +: 32];
            mask = {ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - width);
            size = mask + 1;
            if (width > 0) begin
                if ((base & mask) != 0) begin
                   base = base + size - (base & mask);
                end
                calcBaseAddrs[i * ADDR_WIDTH +: ADDR_WIDTH] = base;
                base = base + size;
            end
        end
    end
endfunction
function [M_COUNT*M_REGIONS*ADDR_WIDTH-1:0] calcBaseAddrs(input [31:0] dummy);

    integer i;
    reg [ADDR_WIDTH-1:0] base;
    reg [ADDR_WIDTH-1:0] width;
    reg [ADDR_WIDTH-1:0] size;
    reg [ADDR_WIDTH-1:0] mask;
    begin
        calcBaseAddrs = {M_COUNT*M_REGIONS*ADDR_WIDTH{1'b0}};
        base = 0;
        for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
            width = M_ADDR_WIDTH[i*32 +: 32];
            mask = {ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - width);
            size = mask + 1;
            if (width > 0) begin
                if ((base & mask) != 0) begin
                   base = base + size - (base & mask);
                end
                calcBaseAddrs[i * ADDR_WIDTH +: ADDR_WIDTH] = base;
                base = base + size;
            end
        end
    end
endfunction