data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_dump.v
None: at end of input
1: b'%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_dump.v:24: Cannot find include file: spio_spinnaker_link.h\n`include "spio_spinnaker_link.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if,data/full_repos/permissive/156407853/spio_spinnaker_link.h\n             data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if,data/full_repos/permissive/156407853/spio_spinnaker_link.h.v\n             data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if,data/full_repos/permissive/156407853/spio_spinnaker_link.h.sv\n             spio_spinnaker_link.h\n             spio_spinnaker_link.h.v\n             spio_spinnaker_link.h.sv\n             obj_dir/spio_spinnaker_link.h\n             obj_dir/spio_spinnaker_link.h.v\n             obj_dir/spio_spinnaker_link.h.sv\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_dump.v:44: Define or directive not defined: \'`PKT_BITS\'\n  input  wire [`PKT_BITS - 1:0] mpkt_data,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_dump.v:49: Define or directive not defined: \'`PKT_BITS\'\n  output wire [`PKT_BITS - 1:0] ipkt_data,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_dump.v:76: Define or directive not defined: \'`PKT_BITS\'\n    .PKT_BITS(`PKT_BITS),\n              ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module raggedstone_spinn_aer_if_dump
#(



  parameter DUMP_CNT = 31
)
(
  input  wire                   rst,
  input  wire                   clk,


  input  wire                   go,
  output wire                   dump_mode,


  input  wire [`PKT_BITS - 1:0] mpkt_data,
  input  wire                   mpkt_vld,
  output wire                   mpkt_rdy,


  output wire [`PKT_BITS - 1:0] ipkt_data,
  output wire                   ipkt_vld,
  input  wire                   ipkt_rdy
);




  localparam STATE_BITS = 1;
  localparam IDLE_ST    = 0;
  localparam DUMP_ST    = IDLE_ST + 1;





  reg [STATE_BITS - 1:0] state;

  wire                   busy;
  reg             [15:0] busy_ctr;





  spio_switch
  #(
    .PKT_BITS(`PKT_BITS),
    .NUM_PORTS(1)
  ) sw
  (
    .RESET_IN             (rst),
    .CLK_IN               (clk),
    .IN_DATA_IN           (mpkt_data),
    .IN_VLD_IN            (mpkt_vld),
    .IN_RDY_OUT           (mpkt_rdy),
    .IN_OUTPUT_SELECT_IN  (go),
    .OUT_DATA_OUT         (ipkt_data),
    .OUT_VLD_OUT          (ipkt_vld),
    .OUT_RDY_IN           (ipkt_rdy),
    .BLOCKED_OUTPUTS_OUT  (),
    .SELECTED_OUTPUTS_OUT (),
    .DROP_IN              (dump_mode),
    .DROPPED_DATA_OUT     (),
    .DROPPED_OUTPUTS_OUT  (),
    .DROPPED_VLD_OUT      ()
  );






  always @(posedge clk or posedge rst)
    if (rst)
      busy_ctr <= DUMP_CNT;
    else
      if (!busy)
        busy_ctr <= DUMP_CNT;
      else if (busy_ctr != 0)
        busy_ctr <= busy_ctr - 1;

 




  assign dump_mode = (state == DUMP_ST);






  assign busy = ipkt_vld && !ipkt_rdy;






  always @(posedge clk or posedge rst)
    if (rst)
      state <= IDLE_ST;
    else
      case (state)
        IDLE_ST:
          if (busy_ctr == 0)
            state <= DUMP_ST;

	DUMP_ST:
          if (!busy)
	    state <= IDLE_ST;
      endcase
endmodule
module raggedstone_spinn_aer_if_dump
#(



  parameter DUMP_CNT = 31
)
(
  input  wire                   rst,
  input  wire                   clk,


  input  wire                   go,
  output wire                   dump_mode,


  input  wire [`PKT_BITS - 1:0] mpkt_data,
  input  wire                   mpkt_vld,
  output wire                   mpkt_rdy,


  output wire [`PKT_BITS - 1:0] ipkt_data,
  output wire                   ipkt_vld,
  input  wire                   ipkt_rdy
);





  localparam STATE_BITS = 1;
  localparam IDLE_ST    = 0;
  localparam DUMP_ST    = IDLE_ST + 1;





  reg [STATE_BITS - 1:0] state;

  wire                   busy;
  reg             [15:0] busy_ctr;





  spio_switch
  #(
    .PKT_BITS(`PKT_BITS),
    .NUM_PORTS(1)
  ) sw
  (
    .RESET_IN             (rst),
    .CLK_IN               (clk),
    .IN_DATA_IN           (mpkt_data),
    .IN_VLD_IN            (mpkt_vld),
    .IN_RDY_OUT           (mpkt_rdy),
    .IN_OUTPUT_SELECT_IN  (go),
    .OUT_DATA_OUT         (ipkt_data),
    .OUT_VLD_OUT          (ipkt_vld),
    .OUT_RDY_IN           (ipkt_rdy),
    .BLOCKED_OUTPUTS_OUT  (),
    .SELECTED_OUTPUTS_OUT (),
    .DROP_IN              (dump_mode),
    .DROPPED_DATA_OUT     (),
    .DROPPED_OUTPUTS_OUT  (),
    .DROPPED_VLD_OUT      ()
  );






  always @(posedge clk or posedge rst)
    if (rst)
      busy_ctr <= DUMP_CNT;
    else
      if (!busy)
        busy_ctr <= DUMP_CNT;
      else if (busy_ctr != 0)
        busy_ctr <= busy_ctr - 1;

 




  assign dump_mode = (state == DUMP_ST);






  assign busy = ipkt_vld && !ipkt_rdy;






  always @(posedge clk or posedge rst)
    if (rst)
      state <= IDLE_ST;
    else
      case (state)
        IDLE_ST:
          if (busy_ctr == 0)
            state <= DUMP_ST;

	DUMP_ST:
          if (!busy)
	    state <= IDLE_ST;
      endcase
endmodule