data/full_repos/permissive/179439333/src/sound-module/Synthesizer.v
1: b'%Error: data/full_repos/permissive/179439333/src/sound-module/Synthesizer.v:28: Cannot find file containing module: \'WaveTable0Rom\'\nWaveTable0Rom waveTable0Rom(waveTableIndex, CLOCK_50, waveTableSample0);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179439333/src/sound-module,data/full_repos/permissive/179439333/WaveTable0Rom\n             data/full_repos/permissive/179439333/src/sound-module,data/full_repos/permissive/179439333/WaveTable0Rom.v\n             data/full_repos/permissive/179439333/src/sound-module,data/full_repos/permissive/179439333/WaveTable0Rom.sv\n             WaveTable0Rom\n             WaveTable0Rom.v\n             WaveTable0Rom.sv\n             obj_dir/WaveTable0Rom\n             obj_dir/WaveTable0Rom.v\n             obj_dir/WaveTable0Rom.sv\n%Error: data/full_repos/permissive/179439333/src/sound-module/Synthesizer.v:29: Cannot find file containing module: \'WaveTable1Rom\'\nWaveTable1Rom waveTable1Rom(waveTableIndex, CLOCK_50, waveTableSample1);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/179439333/src/sound-module/Synthesizer.v:30: Cannot find file containing module: \'WaveTable2Rom\'\nWaveTable2Rom waveTable2Rom(waveTableIndex, CLOCK_50, waveTableSample2);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/179439333/src/sound-module/Synthesizer.v:32: Cannot find file containing module: \'SampleMixer\'\nSampleMixer sampleMixer(waveTableSample0, waveTableSample1, waveTableSample2, modulation, renderedSample);\n^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179439333/src/sound-module/Synthesizer.v:40: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance Synthesizer\n   i2sCount <= 1\'b0;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/179439333/src/sound-module/Synthesizer.v:47: Bit extraction of var[15:0] requires 4 bit index, not 8 bits.\n                                                                                      : ... In instance Synthesizer\n      i2sSoundData <= renderedSample[bitCount +: 1];\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/179439333/src/sound-module/Synthesizer.v:38: Operator EQ expects 12 bits on the RHS, but RHS\'s VARREF \'i2sTicks\' generates 8 bits.\n                                                                                      : ... In instance Synthesizer\n if (i2sCount == i2sTicks)\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/179439333/src/sound-module/Synthesizer.v:72: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance Synthesizer\n   noteSampleCount <= 1\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/179439333/src/sound-module/Synthesizer.v:73: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance Synthesizer\n   sampleIndex <= isSamplePlaying ? sampleIndex + 1\'b1 : 1\'b0;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/179439333/src/sound-module/Synthesizer.v:77: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance Synthesizer\n   else if (sampleIndex == 1\'b0)\n                        ^~\n%Error: Exiting due to 4 error(s), 6 warning(s)\n'
module Synthesizer(
	input CLOCK_50,
	input isNoteOn,
	input [23:0] noteSampleTicks,
	input [7:0] modulationValue,
	output reg i2sBitClock,
	output reg i2sSoundData,
	output reg i2sLeftRightSelect
);


localparam i2sTicks = 8'd18;

reg [11:0] i2sCount = 0;
reg [23:0] noteSampleCount = 0;
reg [7:0] bitCount = 15;
reg [7:0] sampleIndex = 0;
reg [7:0] waveTableIndex = 0;
reg [7:0] modulation = 0;
reg isSamplePlaying = 0;
reg isSoundPlaying = 0;

wire [15:0] waveTableSample0;
wire [15:0] waveTableSample1;
wire [15:0] waveTableSample2;
wire [15:0] renderedSample;

WaveTable0Rom waveTable0Rom(waveTableIndex, CLOCK_50, waveTableSample0);
WaveTable1Rom waveTable1Rom(waveTableIndex, CLOCK_50, waveTableSample1);
WaveTable2Rom waveTable2Rom(waveTableIndex, CLOCK_50, waveTableSample2);

SampleMixer sampleMixer(waveTableSample0, waveTableSample1, waveTableSample2, modulation, renderedSample);

always @(posedge CLOCK_50)
begin
	i2sCount <= i2sCount + 1'b1;
	
	if (i2sCount == i2sTicks)
		begin
			i2sCount <= 1'b0;
			
			i2sBitClock <= ~i2sBitClock;
			
			if (i2sBitClock == 1'b1)
				begin
					if (isSoundPlaying)
						i2sSoundData <= renderedSample[bitCount +: 1];
					else
						i2sSoundData <= 1'b0;
	
					if (bitCount == 0)
						begin
							i2sLeftRightSelect <= ~i2sLeftRightSelect;
							bitCount <= 15;
							
							if (i2sLeftRightSelect == 1'b1)
								begin
									waveTableIndex <= sampleIndex;
									modulation <= modulationValue;
									isSoundPlaying <= isSamplePlaying;
								end
						end
					else
						bitCount <= bitCount - 1'b1;
				end
		end
		
	noteSampleCount <= noteSampleCount + 1'b1;
	
	if (noteSampleCount >= noteSampleTicks)
		begin
			noteSampleCount <= 1'b0;
			sampleIndex <= isSamplePlaying ? sampleIndex + 1'b1 : 1'b0;
					
			if (isNoteOn == 1'b1)
				isSamplePlaying <= 1'b1;	
			else if (sampleIndex == 1'b0)
				isSamplePlaying <= 1'b0;
		end
end

endmodule
module Synthesizer(
	input CLOCK_50,
	input isNoteOn,
	input [23:0] noteSampleTicks,
	input [7:0] modulationValue,
	output reg i2sBitClock,
	output reg i2sSoundData,
	output reg i2sLeftRightSelect
);



localparam i2sTicks = 8'd18;

reg [11:0] i2sCount = 0;
reg [23:0] noteSampleCount = 0;
reg [7:0] bitCount = 15;
reg [7:0] sampleIndex = 0;
reg [7:0] waveTableIndex = 0;
reg [7:0] modulation = 0;
reg isSamplePlaying = 0;
reg isSoundPlaying = 0;

wire [15:0] waveTableSample0;
wire [15:0] waveTableSample1;
wire [15:0] waveTableSample2;
wire [15:0] renderedSample;

WaveTable0Rom waveTable0Rom(waveTableIndex, CLOCK_50, waveTableSample0);
WaveTable1Rom waveTable1Rom(waveTableIndex, CLOCK_50, waveTableSample1);
WaveTable2Rom waveTable2Rom(waveTableIndex, CLOCK_50, waveTableSample2);

SampleMixer sampleMixer(waveTableSample0, waveTableSample1, waveTableSample2, modulation, renderedSample);

always @(posedge CLOCK_50)
begin
	i2sCount <= i2sCount + 1'b1;
	
	if (i2sCount == i2sTicks)
		begin
			i2sCount <= 1'b0;
			
			i2sBitClock <= ~i2sBitClock;
			
			if (i2sBitClock == 1'b1)
				begin
					if (isSoundPlaying)
						i2sSoundData <= renderedSample[bitCount +: 1];
					else
						i2sSoundData <= 1'b0;
	
					if (bitCount == 0)
						begin
							i2sLeftRightSelect <= ~i2sLeftRightSelect;
							bitCount <= 15;
							
							if (i2sLeftRightSelect == 1'b1)
								begin
									waveTableIndex <= sampleIndex;
									modulation <= modulationValue;
									isSoundPlaying <= isSamplePlaying;
								end
						end
					else
						bitCount <= bitCount - 1'b1;
				end
		end
		
	noteSampleCount <= noteSampleCount + 1'b1;
	
	if (noteSampleCount >= noteSampleTicks)
		begin
			noteSampleCount <= 1'b0;
			sampleIndex <= isSamplePlaying ? sampleIndex + 1'b1 : 1'b0;
					
			if (isNoteOn == 1'b1)
				isSamplePlaying <= 1'b1;	
			else if (sampleIndex == 1'b0)
				isSamplePlaying <= 1'b0;
		end
end

endmodule