data/full_repos/permissive/198139336/DDLab5_forStudent/structural example/DDLab5_structuralex_2019.v
1: b'%Error: Cannot find file containing module: example,data/full_repos/permissive/198139336\n        ... Looked in:\n             data/full_repos/permissive/198139336/DDLab5_forStudent/structural/example,data/full_repos/permissive/198139336\n             data/full_repos/permissive/198139336/DDLab5_forStudent/structural/example,data/full_repos/permissive/198139336.v\n             data/full_repos/permissive/198139336/DDLab5_forStudent/structural/example,data/full_repos/permissive/198139336.sv\n             example,data/full_repos/permissive/198139336\n             example,data/full_repos/permissive/198139336.v\n             example,data/full_repos/permissive/198139336.sv\n             obj_dir/example,data/full_repos/permissive/198139336\n             obj_dir/example,data/full_repos/permissive/198139336.v\n             obj_dir/example,data/full_repos/permissive/198139336.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/198139336/DDLab5_forStudent/structural\n%Error: Cannot find file containing module: example/DDLab5_structuralex_2019.v\n%Error: Exiting due to 3 error(s)\n'
module lab5(in, out);


	input [2:0]in;
	output  [3:0]out;
	wire nin2, nin1, nin0;
	wire w0, w1, w2, w3, w4, w5, w6;
	


	not n2(nin2, in[2]), 
		n1(nin1, in[1]), 
		n0(nin0, in[0]);
		

	and a0(w0, nin2, nin1, in[0]), 
		a1(w1, in[2], in[1], in[0]), 
		a2(out[2] , nin2, in[1]), 
		a3(w2, nin2, in[1]), 
		a4(w3, in[2], nin1, in[0]), 
		a5(w4 , nin2, nin1), 
		a6(w5, in[2], in[0]),
		a7(w6, in[1], nin0);
	

	or o0(out[3], w0, w1),
		o1(out[1], w2, w3),
		o2(out[0], w4, w5, w6);

endmodule
module lab5(in, out);



	input [2:0]in;
	output  [3:0]out;
	wire nin2, nin1, nin0;
	wire w0, w1, w2, w3, w4, w5, w6;
	


	not n2(nin2, in[2]), 
		n1(nin1, in[1]), 
		n0(nin0, in[0]);
		

	and a0(w0, nin2, nin1, in[0]), 
		a1(w1, in[2], in[1], in[0]), 
		a2(out[2] , nin2, in[1]), 
		a3(w2, nin2, in[1]), 
		a4(w3, in[2], nin1, in[0]), 
		a5(w4 , nin2, nin1), 
		a6(w5, in[2], in[0]),
		a7(w6, in[1], nin0);
	

	or o0(out[3], w0, w1),
		o1(out[1], w2, w3),
		o2(out[0], w4, w5, w6);

endmodule