data/full_repos/permissive/144902498/source/rtl/ff.v
data/verilator_xmls/0d2b524e-5992-46fc-a38e-08413fd19882.xml
module ff #(parameter WIDTH = 8) (
    input clk,
    input n_reset,
    input we,
    input [WIDTH-1:0] d,

    output reg [WIDTH-1:0] q
);

always @(posedge clk, negedge n_reset) begin
    if (n_reset == 1'b0)
        q <= {WIDTH{1'b0}};
    else if (we)
        q <= d;
end

endmodule
module ff #(parameter WIDTH = 8) (
    input clk,
    input n_reset,
    input we,
    input [WIDTH-1:0] d,

    output reg [WIDTH-1:0] q
);


always @(posedge clk, negedge n_reset) begin
    if (n_reset == 1'b0)
        q <= {WIDTH{1'b0}};
    else if (we)
        q <= d;
end

endmodule