data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/randomNumGen_20.v
None: at end of input
1: b'%Error: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/randomNumGen_20.v:18: Cannot find file containing module: \'counter_31\'\n  counter_31 slowclk (\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/counter_31\n             data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/counter_31.v\n             data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/counter_31.sv\n             counter_31\n             counter_31.v\n             counter_31.sv\n             obj_dir/counter_31\n             obj_dir/counter_31.v\n             obj_dir/counter_31.sv\n%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/randomNumGen_20.v:23: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                        : ... In instance randomNumGen_20\n  reg [3:0] M_temp_d, M_temp_q = 1\'h0;\n                                 ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/randomNumGen_20.v:28: Cannot find file containing module: \'pn_gen_32\'\n  pn_gen_32 rng (\n  ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/randomNumGen_20.v:40: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h14\' generates 5 bits.\n                                                                                                                                                        : ... In instance randomNumGen_20\n    M_rng_seed = 5\'h14;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/151548608/LEDdisplay/work/planAhead/LEDdisplay/LEDdisplay.srcs/sources_1/imports/verilog/randomNumGen_20.v:52: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                        : ... In instance randomNumGen_20\n      M_temp_q <= 1\'h0;\n               ^~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module randomNumGen_20 (
    input clk,
    input rst,
    output reg [3:0] out
  );
  
  
  
  reg sclk;
  
  wire [1-1:0] M_slowclk_value;
  counter_31 slowclk (
    .clk(clk),
    .rst(rst),
    .value(M_slowclk_value)
  );
  reg [3:0] M_temp_d, M_temp_q = 1'h0;
  
  wire [32-1:0] M_rng_num;
  reg [1-1:0] M_rng_next;
  reg [32-1:0] M_rng_seed;
  pn_gen_32 rng (
    .clk(clk),
    .rst(rst),
    .next(M_rng_next),
    .seed(M_rng_seed),
    .num(M_rng_num)
  );
  
  always @* begin
    M_temp_d = M_temp_q;
    
    sclk = M_slowclk_value;
    M_rng_seed = 5'h14;
    M_rng_next = 1'h1;
    if (M_slowclk_value == 1'h1) begin
      M_temp_d = M_rng_num[0+3-:4];
    end else begin
      M_temp_d = M_temp_q;
    end
    out = M_temp_q;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_temp_q <= 1'h0;
    end else begin
      M_temp_q <= M_temp_d;
    end
  end
  
endmodule
module randomNumGen_20 (
    input clk,
    input rst,
    output reg [3:0] out
  );

  
  
  
  reg sclk;
  
  wire [1-1:0] M_slowclk_value;
  counter_31 slowclk (
    .clk(clk),
    .rst(rst),
    .value(M_slowclk_value)
  );
  reg [3:0] M_temp_d, M_temp_q = 1'h0;
  
  wire [32-1:0] M_rng_num;
  reg [1-1:0] M_rng_next;
  reg [32-1:0] M_rng_seed;
  pn_gen_32 rng (
    .clk(clk),
    .rst(rst),
    .next(M_rng_next),
    .seed(M_rng_seed),
    .num(M_rng_num)
  );
  
  always @* begin
    M_temp_d = M_temp_q;
    
    sclk = M_slowclk_value;
    M_rng_seed = 5'h14;
    M_rng_next = 1'h1;
    if (M_slowclk_value == 1'h1) begin
      M_temp_d = M_rng_num[0+3-:4];
    end else begin
      M_temp_d = M_temp_q;
    end
    out = M_temp_q;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_temp_q <= 1'h0;
    end else begin
      M_temp_q <= M_temp_d;
    end
  end
  
endmodule