data/full_repos/permissive/161526648/SingleCycle.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:300: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                      : ... In instance SingleCycle.alu\n    result = ALUsrc1 < ALUsrc2;  \n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:227: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                      : ... In instance SingleCycle.ImExtend\n assign out = $signed(in);\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module control(opcode,RegDst,Jump,Branch,bne,MemRead,MemtoReg,ALUop,MemWrite,ALUsrc,RegWrite);
	input [5:0]opcode;
	output reg RegDst,Jump,Branch,bne,MemRead,MemtoReg,MemWrite,ALUsrc,RegWrite;
	output reg [1:0] ALUop;
	
	initial begin 
		RegDst=0;
		Jump=0;
		Branch=0;
		bne=0;
		MemRead=0;
		MemtoReg=0;
		ALUop=2'b00;
		MemWrite=0;
		ALUsrc=0;
		RegWrite=0;
	end

	always @(opcode) begin
		case(opcode)
			6'h0:begin
				RegDst=1;
				Jump=0;
				Branch=0;
				bne=0;
				MemRead=0;
				MemtoReg=0;
				ALUop=2'b10;
				MemWrite=0;
				ALUsrc=0;
				RegWrite=1;
			end
			6'h8:begin
				RegDst=0;
				Jump=0;
				Branch=0;
				bne=0;
				MemRead=0;
				MemtoReg=0;
				ALUop=2'b00;
				MemWrite=0;
				ALUsrc=1;
				RegWrite=1;
			end
			6'hc:begin
				RegDst=0;
				Jump=0;
				Branch=0;
				bne=0;
				MemRead=0;
				MemtoReg=0;
				ALUop=2'b11;
				MemWrite=0;
				ALUsrc=1;
				RegWrite=1;
			end
			6'h4:begin
				RegDst=0;
				Jump=0;
				Branch=1;
				bne=0;
				MemRead=0;
				MemtoReg=0;
				ALUop=2'b01;
				MemWrite=0;
				ALUsrc=0;
				RegWrite=0;
			end
			6'h5:begin
				RegDst=0;
				Jump=0;
				Branch=0;
				bne=1;
				MemRead=0;
				MemtoReg=0;
				ALUop=2'b01;
				MemWrite=0;
				ALUsrc=0;
				RegWrite=0;
			end
			6'h2:begin
				RegDst=0;
				Jump=1;
				Branch=0;
				bne=0;
				MemRead=0;
				MemtoReg=0;
				ALUop=2'b00;
				MemWrite=0;
				ALUsrc=0;
				RegWrite=0;
			end
			6'h23:begin
				RegDst=0;
				Jump=0;
				Branch=0;
				bne=0;
				MemRead=1;
				MemtoReg=1;
				ALUop=2'b00;
				MemWrite=0;
				ALUsrc=0;
				RegWrite=1;
			end
			6'h2b:begin
				RegDst=0;
				Jump=0;
				Branch=0;
				bne=0;
				MemRead=1;
				MemtoReg=0;
				ALUop=2'b00;
				MemWrite=1;
				ALUsrc=0;
				RegWrite=0;
			end
		endcase
	end
endmodule
module control(opcode,RegDst,Jump,Branch,bne,MemRead,MemtoReg,ALUop,MemWrite,ALUsrc,RegWrite);

	input [5:0]opcode;
	output reg RegDst,Jump,Branch,bne,MemRead,MemtoReg,MemWrite,ALUsrc,RegWrite;
	output reg [1:0] ALUop;
	
	initial begin 
		RegDst=0;
		Jump=0;
		Branch=0;
		bne=0;
		MemRead=0;
		MemtoReg=0;
		ALUop=2'b00;
		MemWrite=0;
		ALUsrc=0;
		RegWrite=0;
	end

	always @(opcode) begin
		case(opcode)
			6'h0:begin
				RegDst=1;
				Jump=0;
				Branch=0;
				bne=0;
				MemRead=0;
				MemtoReg=0;
				ALUop=2'b10;
				MemWrite=0;
				ALUsrc=0;
				RegWrite=1;
			end
			6'h8:begin
				RegDst=0;
				Jump=0;
				Branch=0;
				bne=0;
				MemRead=0;
				MemtoReg=0;
				ALUop=2'b00;
				MemWrite=0;
				ALUsrc=1;
				RegWrite=1;
			end
			6'hc:begin
				RegDst=0;
				Jump=0;
				Branch=0;
				bne=0;
				MemRead=0;
				MemtoReg=0;
				ALUop=2'b11;
				MemWrite=0;
				ALUsrc=1;
				RegWrite=1;
			end
			6'h4:begin
				RegDst=0;
				Jump=0;
				Branch=1;
				bne=0;
				MemRead=0;
				MemtoReg=0;
				ALUop=2'b01;
				MemWrite=0;
				ALUsrc=0;
				RegWrite=0;
			end
			6'h5:begin
				RegDst=0;
				Jump=0;
				Branch=0;
				bne=1;
				MemRead=0;
				MemtoReg=0;
				ALUop=2'b01;
				MemWrite=0;
				ALUsrc=0;
				RegWrite=0;
			end
			6'h2:begin
				RegDst=0;
				Jump=1;
				Branch=0;
				bne=0;
				MemRead=0;
				MemtoReg=0;
				ALUop=2'b00;
				MemWrite=0;
				ALUsrc=0;
				RegWrite=0;
			end
			6'h23:begin
				RegDst=0;
				Jump=0;
				Branch=0;
				bne=0;
				MemRead=1;
				MemtoReg=1;
				ALUop=2'b00;
				MemWrite=0;
				ALUsrc=0;
				RegWrite=1;
			end
			6'h2b:begin
				RegDst=0;
				Jump=0;
				Branch=0;
				bne=0;
				MemRead=1;
				MemtoReg=0;
				ALUop=2'b00;
				MemWrite=1;
				ALUsrc=0;
				RegWrite=0;
			end
		endcase
	end
endmodule