data/full_repos/permissive/101427397/v/SPIO_IO.v
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data/verilator_xmls/228ba020-8083-4295-9915-b354fbcd566c.xml
module 		 SPIO(input clk,
						input rst,
						input Start,
						input EN,
						input [31:0] P_Data,
						output reg[1:0] counter_set,
						output [15:0] LED_out,
						output wire led_clk,
						output wire led_sout,
						output wire led_clrn,
						output wire LED_PEN,
						output reg[13:0] GPIOf0
						);

endmodule
module 		 SPIO(input clk,
						input rst,
						input Start,
						input EN,
						input [31:0] P_Data,
						output reg[1:0] counter_set,
						output [15:0] LED_out,
						output wire led_clk,
						output wire led_sout,
						output wire led_clrn,
						output wire LED_PEN,
						output reg[13:0] GPIOf0
						);


endmodule