data/full_repos/permissive/193530477/source codes/FDIV.v
1: b'%Error: Cannot find file containing module: codes,data/full_repos/permissive/193530477\n        ... Looked in:\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.v\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.sv\n             codes,data/full_repos/permissive/193530477\n             codes,data/full_repos/permissive/193530477.v\n             codes,data/full_repos/permissive/193530477.sv\n             obj_dir/codes,data/full_repos/permissive/193530477\n             obj_dir/codes,data/full_repos/permissive/193530477.v\n             obj_dir/codes,data/full_repos/permissive/193530477.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/193530477/source\n%Error: Cannot find file containing module: codes/FDIV.v\n%Error: Exiting due to 3 error(s)\n'
module FDIV (CLK, PM);
	input CLK;
	output PM;
	reg[8:0] Q1;
	reg FULL;
	wire RST;
	
	always @ (posedge CLK or posedge RST) begin 
		if (RST) begin
			Q1 <= 0;
			FULL <= 1;
		end
		else begin
			Q1 <= Q1 + 1'b1;
			FULL <= 0;
		end
	end
	
	assign RST = (Q1 == 499);
	assign PM = FULL;

endmodule
module FDIV (CLK, PM);

	input CLK;
	output PM;
	reg[8:0] Q1;
	reg FULL;
	wire RST;
	
	always @ (posedge CLK or posedge RST) begin 
		if (RST) begin
			Q1 <= 0;
			FULL <= 1;
		end
		else begin
			Q1 <= Q1 + 1'b1;
			FULL <= 0;
		end
	end
	
	assign RST = (Q1 == 499);
	assign PM = FULL;

endmodule