data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/handshake.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/handshake.v:55: Cannot find file containing module: 'pulse_synchronizer'\n  pulse_synchronizer #(\n  ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/pulse_synchronizer\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/pulse_synchronizer.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control,data/full_repos/permissive/214858095/pulse_synchronizer.sv\n             pulse_synchronizer\n             pulse_synchronizer.v\n             pulse_synchronizer.sv\n             obj_dir/pulse_synchronizer\n             obj_dir/pulse_synchronizer.v\n             obj_dir/pulse_synchronizer.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/handshake.v:76: Cannot find file containing module: 'synchronizer'\n  synchronizer #(\n  ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module handshake #(
  parameter WIDTH = 32
) (

  input  wire             clk_a,
  input  wire             rst_a,
  input  wire             valid_a,
  input  wire [WIDTH-1:0] data_a,
  output wire             busy_a,


  input  wire             clk_b,
  output wire             valid_b,
  output wire [WIDTH-1:0] data_b
);



  pulse_synchronizer #(
    .MODE("PULSE"), .STAGES(4)
  ) push_sync_inst (
     .clk_a(clk_a), .rst_a(rst_a), .pulse_a(valid_a), .busy_a(busy_a),
     .clk_b(clk_b), .pulse_b(valid_b)
  );


  reg [WIDTH-1:0] data_a_lcl;
  always @(posedge clk_a) begin
    if (valid_a & ~busy_a) begin
      data_a_lcl <= data_a;
    end
  end







  synchronizer #(
    .WIDTH(WIDTH), .STAGES(2), .INITIAL_VAL({WIDTH {1'b0}}), .FALSE_PATH_TO_IN(1)
  ) data_sync_inst (
    .clk(clk_b), .rst(1'b0), .in(data_a_lcl), .out(data_b)
  );

endmodule
module handshake #(
  parameter WIDTH = 32
) (

  input  wire             clk_a,
  input  wire             rst_a,
  input  wire             valid_a,
  input  wire [WIDTH-1:0] data_a,
  output wire             busy_a,


  input  wire             clk_b,
  output wire             valid_b,
  output wire [WIDTH-1:0] data_b
);




  pulse_synchronizer #(
    .MODE("PULSE"), .STAGES(4)
  ) push_sync_inst (
     .clk_a(clk_a), .rst_a(rst_a), .pulse_a(valid_a), .busy_a(busy_a),
     .clk_b(clk_b), .pulse_b(valid_b)
  );


  reg [WIDTH-1:0] data_a_lcl;
  always @(posedge clk_a) begin
    if (valid_a & ~busy_a) begin
      data_a_lcl <= data_a;
    end
  end







  synchronizer #(
    .WIDTH(WIDTH), .STAGES(2), .INITIAL_VAL({WIDTH {1'b0}}), .FALSE_PATH_TO_IN(1)
  ) data_sync_inst (
    .clk(clk_b), .rst(1'b0), .in(data_a_lcl), .out(data_b)
  );

endmodule