data/full_repos/permissive/101171422/de2-115/vgaxor/vga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/101171422/de2-115/vgaxor/vga.v:38: Operator ASSIGNW expects 24 bits on the Assign RHS, but Assign RHS\'s OR generates 32 bits.\n                                                                            : ... In instance vga\n assign rgb = (x^y)<<16 | (x+y)<<8;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101171422/de2-115/vgaxor/vga.v:40: Cannot find file containing module: \'vsg\'\n vsg vg(~rst, clk, l_blank_n, l_hs, l_vs);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/101171422/de2-115/vgaxor,data/full_repos/permissive/101171422/vsg\n             data/full_repos/permissive/101171422/de2-115/vgaxor,data/full_repos/permissive/101171422/vsg.v\n             data/full_repos/permissive/101171422/de2-115/vgaxor,data/full_repos/permissive/101171422/vsg.sv\n             vsg\n             vsg.v\n             vsg.sv\n             obj_dir/vsg\n             obj_dir/vsg.v\n             obj_dir/vsg.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module vga
(
	input wire         rst,
	input wire         clk,
	output reg         blank_n,
	output reg         hs,
	output reg         sync_n,
	output reg         vs,
	output wire [23:0] rgb
);
	reg [31:0] x, y;
	wire       l_hs, l_vs, l_blank_n;

	always @ (posedge clk, negedge rst) begin
		if (!rst) begin
			x <= 0;
			y <= 0;
		end
		else if (l_hs == 0 && l_vs == 0) begin
			x <= 0;
			y <= 0;
		end
		else if (l_blank_n == 1) begin
			x = x + 1;
			if (x == 640) begin
				x = 0;
				y = y + 1;
			end
		end
	end
		
	always @ (negedge clk) begin
		hs <= l_hs;
		vs <= l_vs;
		blank_n <= l_blank_n;
	end
	
	assign rgb = (x^y)<<16 | (x+y)<<8;
	
	vsg vg(~rst, clk, l_blank_n, l_hs, l_vs);

endmodule
module vga
(
	input wire         rst,
	input wire         clk,
	output reg         blank_n,
	output reg         hs,
	output reg         sync_n,
	output reg         vs,
	output wire [23:0] rgb
);

	reg [31:0] x, y;
	wire       l_hs, l_vs, l_blank_n;

	always @ (posedge clk, negedge rst) begin
		if (!rst) begin
			x <= 0;
			y <= 0;
		end
		else if (l_hs == 0 && l_vs == 0) begin
			x <= 0;
			y <= 0;
		end
		else if (l_blank_n == 1) begin
			x = x + 1;
			if (x == 640) begin
				x = 0;
				y = y + 1;
			end
		end
	end
		
	always @ (negedge clk) begin
		hs <= l_hs;
		vs <= l_vs;
		blank_n <= l_blank_n;
	end
	
	assign rgb = (x^y)<<16 | (x+y)<<8;
	
	vsg vg(~rst, clk, l_blank_n, l_hs, l_vs);

endmodule