data/full_repos/permissive/17099167/system/hardware/cores/ethmac/eth_shiftreg.v
None: at end of input
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/ethmac/eth_shiftreg.v:75: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/ethmac,data/full_repos/permissive/17099167/timescale.v\n             data/full_repos/permissive/17099167/system/hardware/cores/ethmac,data/full_repos/permissive/17099167/timescale.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/ethmac,data/full_repos/permissive/17099167/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n'
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, 
                    LatchByte, ShiftedBit, Prsd, LinkFail);


parameter Tp=1;

input       Clk;
input       Reset;
input       MdcEn_n;
input       Mdi;
input [4:0] Fiad;
input [4:0] Rgad;
input [15:0]CtrlData;
input       WriteOp;
input [3:0] ByteSelect;
input [1:0] LatchByte;

output      ShiftedBit;
output[15:0]Prsd;
output      LinkFail;

reg   [7:0] ShiftReg;
reg   [15:0]Prsd;
reg         LinkFail;





always @ (posedge Clk or posedge Reset) 
begin
  if(Reset)
    begin
      ShiftReg[7:0] <=  8'h0;
      Prsd[15:0] <=  16'h0;
      LinkFail <=  1'b0;
    end
  else
    begin
      if(MdcEn_n)
        begin 
          if(|ByteSelect)
            begin

              case (ByteSelect[3:0])
                4'h1 :    ShiftReg[7:0] <=  {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
                4'h2 :    ShiftReg[7:0] <=  {Fiad[0], Rgad[4:0], 2'b10};
                4'h4 :    ShiftReg[7:0] <=  CtrlData[15:8];
                4'h8 :    ShiftReg[7:0] <=  CtrlData[7:0];
              endcase

            end 
          else
            begin
              ShiftReg[7:0] <=  {ShiftReg[6:0], Mdi};
              if(LatchByte[0])
                begin
                  Prsd[7:0] <=  {ShiftReg[6:0], Mdi};
                  if(Rgad == 5'h01)
                    LinkFail <=  ~ShiftReg[1];
                end
              else
                begin
                  if(LatchByte[1])
                    Prsd[15:8] <=  {ShiftReg[6:0], Mdi};
                end
            end
        end
    end
end


assign ShiftedBit = ShiftReg[7];


endmodule
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, 
                    LatchByte, ShiftedBit, Prsd, LinkFail);



parameter Tp=1;

input       Clk;
input       Reset;
input       MdcEn_n;
input       Mdi;
input [4:0] Fiad;
input [4:0] Rgad;
input [15:0]CtrlData;
input       WriteOp;
input [3:0] ByteSelect;
input [1:0] LatchByte;

output      ShiftedBit;
output[15:0]Prsd;
output      LinkFail;

reg   [7:0] ShiftReg;
reg   [15:0]Prsd;
reg         LinkFail;





always @ (posedge Clk or posedge Reset) 
begin
  if(Reset)
    begin
      ShiftReg[7:0] <=  8'h0;
      Prsd[15:0] <=  16'h0;
      LinkFail <=  1'b0;
    end
  else
    begin
      if(MdcEn_n)
        begin 
          if(|ByteSelect)
            begin

              case (ByteSelect[3:0])
                4'h1 :    ShiftReg[7:0] <=  {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
                4'h2 :    ShiftReg[7:0] <=  {Fiad[0], Rgad[4:0], 2'b10};
                4'h4 :    ShiftReg[7:0] <=  CtrlData[15:8];
                4'h8 :    ShiftReg[7:0] <=  CtrlData[7:0];
              endcase

            end 
          else
            begin
              ShiftReg[7:0] <=  {ShiftReg[6:0], Mdi};
              if(LatchByte[0])
                begin
                  Prsd[7:0] <=  {ShiftReg[6:0], Mdi};
                  if(Rgad == 5'h01)
                    LinkFail <=  ~ShiftReg[1];
                end
              else
                begin
                  if(LatchByte[1])
                    Prsd[15:8] <=  {ShiftReg[6:0], Mdi};
                end
            end
        end
    end
end


assign ShiftedBit = ShiftReg[7];


endmodule