data/full_repos/permissive/135077285/id_ex.v
data/verilator_xmls/28697a01-d6c4-434c-b967-8d5bf992db1b.xml
module idEx(
    input wire clock,



    input wire regDestInput,
    input wire [1:0] aluOpInput,
    input wire aluSrcInput,


    input wire [2:0] memControlInput,


    input wire [1:0] wbControlInput,


    input wire [31:0] readData1Input,
    input wire [31:0] readData2Input,
    input wire [31:0] signExtendWireInput,
    input wire [4:0] rdInput,
    input wire [4:0] rtInput,
    input wire [4:0] rsInput,
    input wire [31:0] ifIdInput,



    output reg regDest,
    output reg [1:0] aluOp,
    output reg aluSrc,


    output reg [2:0] memControlIdEx,


    output reg [1:0] wbControlIdEx,


    output reg [31:0] readData1,
    output reg [31:0] readData2,
    output reg [31:0] signExtendWire,
    output reg [4:0] rd,
    output reg [4:0] rt,
    output reg [4:0] rs,
    output reg [31:0] ifId
);

    initial begin

      regDest <= 0;
      aluOp <= 0;
      aluSrc <= 0;


      memControlIdEx <= 0;


      wbControlIdEx <= 0;


      readData1 <= 0;
      readData2 <= 0;
      signExtendWire <= 0;
      rd <= 0;
      rt <= 0;
      rs <= 0;
      ifId <= 0;
    end

    always @(posedge clock) begin

      regDest <= regDestInput;
      aluOp <= aluOpInput;
      aluSrc <= aluSrcInput;


      memControlIdEx <= memControlInput;


      wbControlIdEx <= wbControlInput;


      readData1 <= readData1Input;
      readData2 <= readData2Input;
      signExtendWire <= signExtendWireInput;
      rd <= rdInput;
      rt <= rtInput;
      rs <= rsInput;
      ifId <= ifIdInput;
    end

endmodule
module idEx(
    input wire clock,



    input wire regDestInput,
    input wire [1:0] aluOpInput,
    input wire aluSrcInput,


    input wire [2:0] memControlInput,


    input wire [1:0] wbControlInput,


    input wire [31:0] readData1Input,
    input wire [31:0] readData2Input,
    input wire [31:0] signExtendWireInput,
    input wire [4:0] rdInput,
    input wire [4:0] rtInput,
    input wire [4:0] rsInput,
    input wire [31:0] ifIdInput,



    output reg regDest,
    output reg [1:0] aluOp,
    output reg aluSrc,


    output reg [2:0] memControlIdEx,


    output reg [1:0] wbControlIdEx,


    output reg [31:0] readData1,
    output reg [31:0] readData2,
    output reg [31:0] signExtendWire,
    output reg [4:0] rd,
    output reg [4:0] rt,
    output reg [4:0] rs,
    output reg [31:0] ifId
);


    initial begin

      regDest <= 0;
      aluOp <= 0;
      aluSrc <= 0;


      memControlIdEx <= 0;


      wbControlIdEx <= 0;


      readData1 <= 0;
      readData2 <= 0;
      signExtendWire <= 0;
      rd <= 0;
      rt <= 0;
      rs <= 0;
      ifId <= 0;
    end

    always @(posedge clock) begin

      regDest <= regDestInput;
      aluOp <= aluOpInput;
      aluSrc <= aluSrcInput;


      memControlIdEx <= memControlInput;


      wbControlIdEx <= wbControlInput;


      readData1 <= readData1Input;
      readData2 <= readData2Input;
      signExtendWire <= signExtendWireInput;
      rd <= rdInput;
      rt <= rtInput;
      rs <= rsInput;
      ifId <= ifIdInput;
    end

endmodule