data/full_repos/permissive/181310803/cs.srcs/sources_1/new/mig_7series_v4_0_traffic_gen_top.v
 line:35: before: "reset"
1: b"%Error: data/full_repos/permissive/181310803/cs.srcs/sources_1/new/mig_7series_v4_0_traffic_gen_top.v:25: Duplicate declaration of signal: 'app_addr'\n                                                                                                        : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg                              app_addr;\n                                 ^~~~~~~~\n        data/full_repos/permissive/181310803/cs.srcs/sources_1/new/mig_7series_v4_0_traffic_gen_top.v:16: ... Location of original declaration\n   output   [31:0]                  app_addr,\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sources_1/new/mig_7series_v4_0_traffic_gen_top.v:26: Duplicate declaration of signal: 'app_wdf_data'\nreg                              app_wdf_data;\n                                 ^~~~~~~~~~~~\n        data/full_repos/permissive/181310803/cs.srcs/sources_1/new/mig_7series_v4_0_traffic_gen_top.v:18: ... Location of original declaration\n   output   [DATA_WIDTH-1:0]       app_wdf_data,\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sources_1/new/mig_7series_v4_0_traffic_gen_top.v:27: Duplicate declaration of signal: 'compare_error'\nwire                              compare_error;\n                                  ^~~~~~~~~~~~~\n        data/full_repos/permissive/181310803/cs.srcs/sources_1/new/mig_7series_v4_0_traffic_gen_top.v:21: ... Location of original declaration\n   output                          compare_error\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sources_1/new/mig_7series_v4_0_traffic_gen_top.v:28: Duplicate declaration of signal: 'app_rd_data_valid'\nreg                              app_rd_data_valid;\n                                 ^~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/181310803/cs.srcs/sources_1/new/mig_7series_v4_0_traffic_gen_top.v:13: ... Location of original declaration\n   output                          app_rd_data_valid,\n                                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/181310803/cs.srcs/sources_1/new/mig_7series_v4_0_traffic_gen_top.v:30: Duplicate declaration of signal: 'app_rd_data'\nreg                               app_rd_data;\n                                  ^~~~~~~~~~~\n        data/full_repos/permissive/181310803/cs.srcs/sources_1/new/mig_7series_v4_0_traffic_gen_top.v:12: ... Location of original declaration\n   output    [DATA_WIDTH-1:0]        app_rd_data, \n                                     ^~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/181310803/cs.srcs/sources_1/new/mig_7series_v4_0_traffic_gen_top.v:33: Assigning to input/const variable: 'app_wdf_end'\nassign app_wdf_end=app_wdf_wren;\n       ^~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module mig_7series_v4_0_traffic_gen_top #
(
  parameter   DATA_WIDTH=64
)
(
   input                           clk, 
   output                          app_en, 
   input                           app_rdy, 
   input    [DATA_WIDTH-1:0]        app_wdf_rdy,
   output    [DATA_WIDTH-1:0]        app_rd_data, 
   output                          app_rd_data_valid,
   input                           reset,
   output    [2:0]                   app_cmd,
   output   [31:0]                  app_addr,
   input   [DATA_WIDTH/8-1:0]      app_wdf_mask,
   output   [DATA_WIDTH-1:0]       app_wdf_data,
   input                           app_wdf_wren,
   input                           app_wdf_end,
   output                          compare_error
);


reg                              app_addr;
reg                              app_wdf_data;
wire                              compare_error;
reg                              app_rd_data_valid;
reg          [31:0]               mem [15:0];
reg                               app_rd_data;


assign app_wdf_end=app_wdf_wren;

always @ (posedge clk or reset)
begin
 if(reset)
begin
   app_addr<=0;
   app_wdf_data<=0;
   app_rd_data_valid<=0;
  end
else if(app_cmd==3'b000)
 begin
if(app_rdy&&!app_wdf_mask&&app_wdf_rdy&&app_en)
  app_addr<=app_addr+8;
if(app_wdf_wren)
  app_wdf_data<= app_wdf_data+64;
end

else if(app_cmd==3'b001)
 begin
if(app_rdy&&app_en)
  app_addr<=app_addr+8;
if(app_rd_data_valid)
  app_wdf_data<= app_wdf_data+64;
end
 else
  begin
   app_addr<=0;
   app_wdf_data<=0;
   app_rd_data_valid<=0;
     end
end

always @ (app_addr)
begin
 if(app_cmd==3'b000)
mem[app_addr]<=app_wdf_data;
 else if(app_cmd==3'b001)
app_rd_data<=mem[app_addr];
end

assign compare_error=(app_rd_data==app_wdf_data)?0:1;

endmodule
module mig_7series_v4_0_traffic_gen_top #
(
  parameter   DATA_WIDTH=64
)
(
   input                           clk, 
   output                          app_en, 
   input                           app_rdy, 
   input    [DATA_WIDTH-1:0]        app_wdf_rdy,
   output    [DATA_WIDTH-1:0]        app_rd_data, 
   output                          app_rd_data_valid,
   input                           reset,
   output    [2:0]                   app_cmd,
   output   [31:0]                  app_addr,
   input   [DATA_WIDTH/8-1:0]      app_wdf_mask,
   output   [DATA_WIDTH-1:0]       app_wdf_data,
   input                           app_wdf_wren,
   input                           app_wdf_end,
   output                          compare_error
);



reg                              app_addr;
reg                              app_wdf_data;
wire                              compare_error;
reg                              app_rd_data_valid;
reg          [31:0]               mem [15:0];
reg                               app_rd_data;


assign app_wdf_end=app_wdf_wren;

always @ (posedge clk or reset)
begin
 if(reset)
begin
   app_addr<=0;
   app_wdf_data<=0;
   app_rd_data_valid<=0;
  end
else if(app_cmd==3'b000)
 begin
if(app_rdy&&!app_wdf_mask&&app_wdf_rdy&&app_en)
  app_addr<=app_addr+8;
if(app_wdf_wren)
  app_wdf_data<= app_wdf_data+64;
end

else if(app_cmd==3'b001)
 begin
if(app_rdy&&app_en)
  app_addr<=app_addr+8;
if(app_rd_data_valid)
  app_wdf_data<= app_wdf_data+64;
end
 else
  begin
   app_addr<=0;
   app_wdf_data<=0;
   app_rd_data_valid<=0;
     end
end

always @ (app_addr)
begin
 if(app_cmd==3'b000)
mem[app_addr]<=app_wdf_data;
 else if(app_cmd==3'b001)
app_rd_data<=mem[app_addr];
end

assign compare_error=(app_rd_data==app_wdf_data)?0:1;

endmodule