data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary/TestMultS.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary/TestMultS.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary/TestMultS.v:65: Unsupported: Ignoring delay on this delayed statement.\n  forever #2 i_clk = ~i_clk;\n          ^\n%Error: data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary/TestMultS.v:39: Cannot find file containing module: \'qmults\'\n qmults uut (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary,data/full_repos/permissive/114714167/qmults\n             data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary,data/full_repos/permissive/114714167/qmults.v\n             data/full_repos/permissive/114714167/Source-Code/FixedPointLibrary,data/full_repos/permissive/114714167/qmults.sv\n             qmults\n             qmults.v\n             qmults.sv\n             obj_dir/qmults\n             obj_dir/qmults.v\n             obj_dir/qmults.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestMultS;


	reg [31:0] i_multiplicand;
	reg [31:0] i_multiplier;
	reg i_start;
	reg i_clk;


	wire [31:0] o_result_out;
	wire o_complete;
	wire o_overflow;


	qmults uut (
		.i_multiplicand(i_multiplicand), 
		.i_multiplier(i_multiplier), 
		.i_start(i_start), 
		.i_clk(i_clk), 
		.o_result_out(o_result_out), 
		.o_complete(o_complete), 
		.o_overflow(o_overflow)
	);

	reg [10:0]	count;

	initial begin

		i_multiplicand = 0;
		i_multiplier = 0;
		i_start = 0;
		i_clk = 0;
		
		count = 0;


		#100;
        


		forever #2 i_clk = ~i_clk;
		end
        
		always @(posedge i_clk) begin
			if (count == 47) begin
				count <= 0;
				i_start <= 1'b1;
				end
			else begin				
				count <= count + 1;
				i_start <= 1'b0;
				end
			end

		always @(count) begin
			if (count == 47) begin
				if ( i_multiplier > 32'h1FFFFFFF ) begin
					i_multiplier <= 1;
					i_multiplicand = (i_multiplicand << 1) + 3;
					end
				else
					i_multiplier = (i_multiplier << 1) + 1;
				end
			end
			
	always @(posedge o_complete)
		$display ("%b,%b,%b,%b", i_multiplicand, i_multiplier, o_result_out, o_overflow);


     
endmodule
module TestMultS;



	reg [31:0] i_multiplicand;
	reg [31:0] i_multiplier;
	reg i_start;
	reg i_clk;


	wire [31:0] o_result_out;
	wire o_complete;
	wire o_overflow;


	qmults uut (
		.i_multiplicand(i_multiplicand), 
		.i_multiplier(i_multiplier), 
		.i_start(i_start), 
		.i_clk(i_clk), 
		.o_result_out(o_result_out), 
		.o_complete(o_complete), 
		.o_overflow(o_overflow)
	);

	reg [10:0]	count;

	initial begin

		i_multiplicand = 0;
		i_multiplier = 0;
		i_start = 0;
		i_clk = 0;
		
		count = 0;


		#100;
        


		forever #2 i_clk = ~i_clk;
		end
        
		always @(posedge i_clk) begin
			if (count == 47) begin
				count <= 0;
				i_start <= 1'b1;
				end
			else begin				
				count <= count + 1;
				i_start <= 1'b0;
				end
			end

		always @(count) begin
			if (count == 47) begin
				if ( i_multiplier > 32'h1FFFFFFF ) begin
					i_multiplier <= 1;
					i_multiplicand = (i_multiplicand << 1) + 3;
					end
				else
					i_multiplier = (i_multiplier << 1) + 1;
				end
			end
			
	always @(posedge o_complete)
		$display ("%b,%b,%b,%b", i_multiplicand, i_multiplier, o_result_out, o_overflow);


     
endmodule