data/full_repos/permissive/20803096/module_2013210101.v
data/verilator_xmls/8c02b9b3-a271-4324-9226-8de58d8062dd.xml
module module_2013210101 (clk, reset, curpos, finish);
	input clk;
	input reset;
	output [5:0] curpos;
	output finish;



	always @ (posedge clk)
	begin
	end

endmodule
module module_2013210101 (clk, reset, curpos, finish);

	input clk;
	input reset;
	output [5:0] curpos;
	output finish;



	always @ (posedge clk)
	begin
	end

endmodule