data/full_repos/permissive/18770871/ShiftLeftThenAdd1s.v
data/verilator_xmls/6b9f728b-9297-481e-8eaa-a37b4367f067.xml
module ShiftLeftThenAdd1s(In, Out_L8_1);
    input [7:0] In;
    output [15:0] Out_L8_1;
    
    assign Out_L8_1 = {In[7:0], 8'b11111111};
    
endmodule
module ShiftLeftThenAdd1s(In, Out_L8_1);

    input [7:0] In;
    output [15:0] Out_L8_1;
    
    assign Out_L8_1 = {In[7:0], 8'b11111111};
    
endmodule