data/full_repos/permissive/177038316/project.v
1: b'%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:457: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'HUNDREDS\' generates 2 bits.\n                                                                  : ... In instance top.m3\n    case(HUNDREDS)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:344: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'data_y\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y - data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:344: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'data_x\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y - data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:349: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'data_y\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y + data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:349: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'data_x\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y + data_x;\n                  ^\n%Error: Exiting due to 5 warning(s)\n'
module ula(data_x, data_y, tula, data_ula, overflow, new_instruction);
		input signed [7:0] data_x, data_y;
		input tula, new_instruction;
		output reg signed [7:0] data_ula;
		output reg overflow;
		integer aux;
		
		initial aux = 0;
		
		always @ (negedge new_instruction)
		begin		
			if(aux < -128 || aux > 127)
				begin
					overflow <= 1'b1;
					end
				else
					begin
					overflow <= 1'b0;
					end
			
			if(tula)
				begin
				data_ula <= data_y - data_x;
				aux <= data_y - data_x;
				end
			else 
				begin
				data_ula <= data_y + data_x;
				aux <= data_y + data_x;
				end
			
		end
endmodule
module ula(data_x, data_y, tula, data_ula, overflow, new_instruction);

		input signed [7:0] data_x, data_y;
		input tula, new_instruction;
		output reg signed [7:0] data_ula;
		output reg overflow;
		integer aux;
		
		initial aux = 0;
		
		always @ (negedge new_instruction)
		begin		
			if(aux < -128 || aux > 127)
				begin
					overflow <= 1'b1;
					end
				else
					begin
					overflow <= 1'b0;
					end
			
			if(tula)
				begin
				data_ula <= data_y - data_x;
				aux <= data_y - data_x;
				end
			else 
				begin
				data_ula <= data_y + data_x;
				aux <= data_y + data_x;
				end
			
		end
endmodule