data/full_repos/permissive/162928820/main_con_new.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:115: Operator ADD expects 32 or 14 bits on the LHS, but LHS\'s VARREF \'num0_reg\' generates 4 bits.\n                                                                       : ... In instance main_con_new\n frequency <= num0_reg + num1_reg*10 + num2_reg*100 + num3_reg*1000;  \n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:123: Operator ADD expects 30 bits on the LHS, but LHS\'s REPLICATE generates 9 bits.\n                                                                       : ... In instance main_con_new\n  temp <= ({1\'b0,addr} + 1\'b1) * (yshang[28:8]) + ((({1\'b0,addr} + 1\'b1) * (yshang[7:0])) >> 8);\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:123: Operator ADD expects 30 bits on the LHS, but LHS\'s REPLICATE generates 9 bits.\n                                                                       : ... In instance main_con_new\n  temp <= ({1\'b0,addr} + 1\'b1) * (yshang[28:8]) + ((({1\'b0,addr} + 1\'b1) * (yshang[7:0])) >> 8);\n                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:137: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance main_con_new\n   addr <= 1\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:127: Operator EQ expects 30 bits on the LHS, but LHS\'s VARREF \'yshang_temp\' generates 29 bits.\n                                                                       : ... In instance main_con_new\n  if(yshang_temp == temp) begin\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:159: Operator ASSIGNW expects 29 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                       : ... In instance main_con_new\nassign default_frq = x[2]==1 ? (x[3]==1 ? 32\'h0007A120 : 32\'h1DCD6500) : (x[3]==1 ? 32\'h004C4B40 : 32\'h02FAF080);\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/162928820/main_con_new.v:164: Output port connection \'yshang\' expects 43 bits on the pin connection, but pin connection\'s VARREF \'yshang\' generates 29 bits.\n                                                                       : ... In instance main_con_new\ndiv_rill div(default_frq, frequency, yshang);\n                                     ^~~~~~\n%Error: Exiting due to 7 warning(s)\n'
module main_con_new(
	input wire clk,
	input wire aaa,
	input wire bbb,
	input wire ccc,
	input wire ddd,
	input wire [3:0] x,
	output wire [4:0] contro,
	output wire [3:0] num3_disp,
	output wire [3:0] num2_disp,
	output wire [3:0] num1_disp,
	output wire [3:0] num0_disp,
	output wire memclk,
	output wire [1:0] memmode
	);

reg [1:0] place;
reg [3:0] num3_reg;
reg [3:0] num2_reg;
reg [3:0] num1_reg;
reg [3:0] num0_reg;
reg is_bling;
reg [7:0] alex;
wire [7:0] alex_wire;

reg [20:0] bbb_delay_count;
reg [20:0] ccc_delay_count;
reg [20:0] aaa_delay_count;
reg [20:0] ddd_delay_count;

reg [13:0] frequency;
reg [28:0] yshang_temp;
reg [7:0] addr;
reg [29:0] temp = 0;



reg memclk_reg = 1'b0;
wire [28:0] yshang;


initial begin
	place = 'b00;
	num3_reg = 'b0000;
	num2_reg = 'b0000;
	num1_reg = 'b0000;
	num0_reg = 'b0000;
	alex = 'b0000;
	is_bling = 1;
	addr = 0;
end









always@(posedge clk) begin
	if(bbb) bbb_delay_count <= bbb_delay_count + 1; else bbb_delay_count <= 0;
	if(ccc) ccc_delay_count <= ccc_delay_count + 1; else ccc_delay_count <= 0;
	if(aaa) aaa_delay_count <= aaa_delay_count + 1; else aaa_delay_count <= 0;
	if(ddd) ddd_delay_count <= ddd_delay_count + 1; else ddd_delay_count <= 0;

	if(bbb & bbb_delay_count=='b1111010000100100000) begin alex[0] <= 1; yshang_temp <= 'b0; end
	if(ccc & ccc_delay_count=='b1111010000100100000) begin alex[2] <= 1; yshang_temp <= 'b0; end
	if(aaa & aaa_delay_count=='b1111010000100100000) begin alex[4] <= 1; yshang_temp <= 'b0; end
	if(ddd & ddd_delay_count=='b1111010000100100000) begin alex[6] <= 1; yshang_temp <= 'b0; end
	if(bbb==0) alex[0] <= 0;
	if(ccc==0) alex[2] <= 0;
	if(aaa==0) alex[4] <= 0;
	if(ddd==0) alex[6] <= 0;

	alex[1] <= alex_wire[0];
	alex[3] <= alex_wire[2];
	alex[5] <= alex_wire[4];
	alex[7] <= alex_wire[6];
	case(alex_wire[7:4])
		'b0001:begin if(is_bling) place <= place + 1; end
		'b0100:begin is_bling <= ~is_bling; end
	endcase
	case({alex_wire[3:0],contro[2:0]})
		'b0001100:begin num0_reg <= num0_reg==9 ? 0 : (num0_reg + 1); end
		'b0001101:begin num1_reg <= num1_reg==9 ? 0 : (num1_reg + 1); end
		'b0001110:begin num2_reg <= num2_reg==9 ? 0 : (num2_reg + 1); end
		'b0001111:begin num3_reg <= num3_reg==9 ? 0 : (num3_reg + 1); end
		'b0100100:begin num0_reg <= num0_reg==0 ? 9 : (num0_reg - 1); end
		'b0100101:begin num1_reg <= num1_reg==0 ? 9 : (num1_reg - 1); end
		'b0100110:begin num2_reg <= num2_reg==0 ? 9 : (num2_reg - 1); end
		'b0100111:begin num3_reg <= num3_reg==0 ? 9 : (num3_reg - 1); end
	endcase

	frequency <= num0_reg + num1_reg*10 + num2_reg*100 + num3_reg*1000;



	if(frequency != 0) begin

		yshang_temp <= yshang_temp + 1'b1;

		temp <= ({1'b0,addr} + 1'b1) * (yshang[28:8]) + ((({1'b0,addr} + 1'b1) * (yshang[7:0])) >> 8);



		if(yshang_temp == temp) begin
			memclk_reg <= 1'b1;
			addr <= addr + 1'b1;
			end




		else if(yshang_temp > yshang[28:0]) begin
		 	yshang_temp <= 'b0;
			addr <= 1'b0;
			end
		else
			memclk_reg <= 1'b0;
		end
	else begin
		yshang_temp <= 'b0;
		end
end

assign alex_wire = alex;
assign contro = {x[3:2],is_bling,place};

assign num3_disp = num3_reg;
assign num2_disp = num2_reg;
assign num1_disp = num1_reg;
assign num0_disp = num0_reg;
assign memclk = memclk_reg;
assign memmode = x[1:0];


wire [28:0] default_frq;
assign default_frq = x[2]==1 ? (x[3]==1 ? 32'h0007A120 : 32'h1DCD6500) : (x[3]==1 ? 32'h004C4B40 : 32'h02FAF080);




div_rill div(default_frq, frequency, yshang);




endmodule
module main_con_new(
	input wire clk,
	input wire aaa,
	input wire bbb,
	input wire ccc,
	input wire ddd,
	input wire [3:0] x,
	output wire [4:0] contro,
	output wire [3:0] num3_disp,
	output wire [3:0] num2_disp,
	output wire [3:0] num1_disp,
	output wire [3:0] num0_disp,
	output wire memclk,
	output wire [1:0] memmode
	);


reg [1:0] place;
reg [3:0] num3_reg;
reg [3:0] num2_reg;
reg [3:0] num1_reg;
reg [3:0] num0_reg;
reg is_bling;
reg [7:0] alex;
wire [7:0] alex_wire;

reg [20:0] bbb_delay_count;
reg [20:0] ccc_delay_count;
reg [20:0] aaa_delay_count;
reg [20:0] ddd_delay_count;

reg [13:0] frequency;
reg [28:0] yshang_temp;
reg [7:0] addr;
reg [29:0] temp = 0;



reg memclk_reg = 1'b0;
wire [28:0] yshang;


initial begin
	place = 'b00;
	num3_reg = 'b0000;
	num2_reg = 'b0000;
	num1_reg = 'b0000;
	num0_reg = 'b0000;
	alex = 'b0000;
	is_bling = 1;
	addr = 0;
end









always@(posedge clk) begin
	if(bbb) bbb_delay_count <= bbb_delay_count + 1; else bbb_delay_count <= 0;
	if(ccc) ccc_delay_count <= ccc_delay_count + 1; else ccc_delay_count <= 0;
	if(aaa) aaa_delay_count <= aaa_delay_count + 1; else aaa_delay_count <= 0;
	if(ddd) ddd_delay_count <= ddd_delay_count + 1; else ddd_delay_count <= 0;

	if(bbb & bbb_delay_count=='b1111010000100100000) begin alex[0] <= 1; yshang_temp <= 'b0; end
	if(ccc & ccc_delay_count=='b1111010000100100000) begin alex[2] <= 1; yshang_temp <= 'b0; end
	if(aaa & aaa_delay_count=='b1111010000100100000) begin alex[4] <= 1; yshang_temp <= 'b0; end
	if(ddd & ddd_delay_count=='b1111010000100100000) begin alex[6] <= 1; yshang_temp <= 'b0; end
	if(bbb==0) alex[0] <= 0;
	if(ccc==0) alex[2] <= 0;
	if(aaa==0) alex[4] <= 0;
	if(ddd==0) alex[6] <= 0;

	alex[1] <= alex_wire[0];
	alex[3] <= alex_wire[2];
	alex[5] <= alex_wire[4];
	alex[7] <= alex_wire[6];
	case(alex_wire[7:4])
		'b0001:begin if(is_bling) place <= place + 1; end
		'b0100:begin is_bling <= ~is_bling; end
	endcase
	case({alex_wire[3:0],contro[2:0]})
		'b0001100:begin num0_reg <= num0_reg==9 ? 0 : (num0_reg + 1); end
		'b0001101:begin num1_reg <= num1_reg==9 ? 0 : (num1_reg + 1); end
		'b0001110:begin num2_reg <= num2_reg==9 ? 0 : (num2_reg + 1); end
		'b0001111:begin num3_reg <= num3_reg==9 ? 0 : (num3_reg + 1); end
		'b0100100:begin num0_reg <= num0_reg==0 ? 9 : (num0_reg - 1); end
		'b0100101:begin num1_reg <= num1_reg==0 ? 9 : (num1_reg - 1); end
		'b0100110:begin num2_reg <= num2_reg==0 ? 9 : (num2_reg - 1); end
		'b0100111:begin num3_reg <= num3_reg==0 ? 9 : (num3_reg - 1); end
	endcase

	frequency <= num0_reg + num1_reg*10 + num2_reg*100 + num3_reg*1000;



	if(frequency != 0) begin

		yshang_temp <= yshang_temp + 1'b1;

		temp <= ({1'b0,addr} + 1'b1) * (yshang[28:8]) + ((({1'b0,addr} + 1'b1) * (yshang[7:0])) >> 8);



		if(yshang_temp == temp) begin
			memclk_reg <= 1'b1;
			addr <= addr + 1'b1;
			end




		else if(yshang_temp > yshang[28:0]) begin
		 	yshang_temp <= 'b0;
			addr <= 1'b0;
			end
		else
			memclk_reg <= 1'b0;
		end
	else begin
		yshang_temp <= 'b0;
		end
end

assign alex_wire = alex;
assign contro = {x[3:2],is_bling,place};

assign num3_disp = num3_reg;
assign num2_disp = num2_reg;
assign num1_disp = num1_reg;
assign num0_disp = num0_reg;
assign memclk = memclk_reg;
assign memmode = x[1:0];


wire [28:0] default_frq;
assign default_frq = x[2]==1 ? (x[3]==1 ? 32'h0007A120 : 32'h1DCD6500) : (x[3]==1 ? 32'h004C4B40 : 32'h02FAF080);




div_rill div(default_frq, frequency, yshang);




endmodule