data/full_repos/permissive/113780415/src/top_test.v
 line:1736: before: "&&"
1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(posedge clk && enable == 1'b1)\n                                   ^~\n%Error: Cannot continue\n"
module counter4Bit(clock, reset, enable, count, count_done);

	input clock;

	input reset, enable;

	

	output reg [3:0] count;

	output reg count_done;

	

	

	always@ (posedge clock) begin

		if(reset == 0) begin

			count<=0;

			count_done <= 1'b0;

			end

			

	        else if(count == 4'b1111) begin

	            count <= 4'b0000;

	            count_done <= 1'b1;

	            end

		else if(enable) begin

			count<= count+1;

			count_done <= 1'b0;

			end

	        else 

	            count_done <= 1'b0;

	end

endmodule
module counter4Bit(clock, reset, enable, count, count_done);


	input clock;

	input reset, enable;

	

	output reg [3:0] count;

	output reg count_done;

	

	

	always@ (posedge clock) begin

		if(reset == 0) begin

			count<=0;

			count_done <= 1'b0;

			end

			

	        else if(count == 4'b1111) begin

	            count <= 4'b0000;

	            count_done <= 1'b1;

	            end

		else if(enable) begin

			count<= count+1;

			count_done <= 1'b0;

			end

	        else 

	            count_done <= 1'b0;

	end

endmodule