data/full_repos/permissive/118800618/testtest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:151: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118800618/testtest.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Error: data/full_repos/permissive/118800618/testtest.v:36: Cannot find file containing module: \'microctrl\'\n microctrl uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/118800618,data/full_repos/permissive/118800618/microctrl\n             data/full_repos/permissive/118800618,data/full_repos/permissive/118800618/microctrl.v\n             data/full_repos/permissive/118800618,data/full_repos/permissive/118800618/microctrl.sv\n             microctrl\n             microctrl.v\n             microctrl.sv\n             obj_dir/microctrl\n             obj_dir/microctrl.v\n             obj_dir/microctrl.sv\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testtest;


	reg clk;
	reg rst;
	reg [5:0] opcode;


	wire [17:0] out;


	microctrl uut (
		.clk(clk), 
		.rst(rst), 
		.opcode(opcode), 
		.out(out)
	);

	initial begin
	   clk = 0;
		rst = 0;
		opcode = 6'b000010;


		#100;
		
		

		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;
      
		
		clk = 0;
		rst = 0;
		opcode = 6'b000010;




		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;




		#50;
		
		clk = 0;
		rst = 0;
		opcode =6'b000010;




		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 0;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;


		clk = 0;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 0;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;
	
	
	   clk = 0;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 0;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;

	end
      
endmodule
module testtest;



	reg clk;
	reg rst;
	reg [5:0] opcode;


	wire [17:0] out;


	microctrl uut (
		.clk(clk), 
		.rst(rst), 
		.opcode(opcode), 
		.out(out)
	);

	initial begin
	   clk = 0;
		rst = 0;
		opcode = 6'b000010;


		#100;
		
		

		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;
      
		
		clk = 0;
		rst = 0;
		opcode = 6'b000010;




		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;




		#50;
		
		clk = 0;
		rst = 0;
		opcode =6'b000010;




		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 0;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;


		clk = 0;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 0;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;
	
	
	   clk = 0;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 0;
		rst = 0;
		opcode = 6'b000010;


		#50;
		
		clk = 1;
		rst = 0;
		opcode = 6'b000010;


		#50;

	end
      
endmodule