data/full_repos/permissive/211316121/lab6_3/timeCounter24.v
1: b"%Error: data/full_repos/permissive/211316121/lab6_3/timeCounter24.v:44: Cannot find file containing module: 'cnt_74ls163'\n    cnt_74ls163 ctr1(.load_time(loadtime1), .CP(clk), .CLR(~(reach1 | reach2)), .LOAD(clr), \n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/lab6_3,data/full_repos/permissive/211316121/cnt_74ls163\n             data/full_repos/permissive/211316121/lab6_3,data/full_repos/permissive/211316121/cnt_74ls163.v\n             data/full_repos/permissive/211316121/lab6_3,data/full_repos/permissive/211316121/cnt_74ls163.sv\n             cnt_74ls163\n             cnt_74ls163.v\n             cnt_74ls163.sv\n             obj_dir/cnt_74ls163\n             obj_dir/cnt_74ls163.v\n             obj_dir/cnt_74ls163.sv\n%Error: data/full_repos/permissive/211316121/lab6_3/timeCounter24.v:46: Cannot find file containing module: 'cnt_74ls163'\n    cnt_74ls163 ctr2(.load_time(loadtime2), .CP(clk), .CLR(~reach2), .LOAD(clr), \n    ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module timeCounter24(
    input clk,
    input clr,
    input [5:0] init_time,
    input timeIn,
    output [3:0] tCounter1,
    output [3:0] tCounter2,
    output RCO
);
    
    wire rco1, rco2;
    wire [3:0] loadtime1;
    wire [3:0] loadtime2;
    wire reach1, reach2;

    assign loadtime1 = init_time[3:0];
    assign loadtime2 = { 2'b00, init_time[5:4]};

    assign reach1 = tCounter1[0] & ~tCounter1[1] & ~tCounter1[2] & tCounter1[3] & timeIn & clr;
    assign reach2 = ~tCounter2[0] & tCounter2[1] & tCounter1[0] & tCounter1[1] & ~tCounter1[2] & ~tCounter1[3] & timeIn & clr;
    assign RCO = reach2;
    cnt_74ls163 ctr1(.load_time(loadtime1), .CP(clk), .CLR(~(reach1 | reach2)), .LOAD(clr), 
                            .P(timeIn), .T(timeIn), .dataOut(tCounter1[3:0]), .RCO(rco1));
    cnt_74ls163 ctr2(.load_time(loadtime2), .CP(clk), .CLR(~reach2), .LOAD(clr), 
                            .P(reach1), .T(reach1), .dataOut(tCounter2[3:0]), .RCO(rco2));
    
endmodule
module timeCounter24(
    input clk,
    input clr,
    input [5:0] init_time,
    input timeIn,
    output [3:0] tCounter1,
    output [3:0] tCounter2,
    output RCO
);

    
    wire rco1, rco2;
    wire [3:0] loadtime1;
    wire [3:0] loadtime2;
    wire reach1, reach2;

    assign loadtime1 = init_time[3:0];
    assign loadtime2 = { 2'b00, init_time[5:4]};

    assign reach1 = tCounter1[0] & ~tCounter1[1] & ~tCounter1[2] & tCounter1[3] & timeIn & clr;
    assign reach2 = ~tCounter2[0] & tCounter2[1] & tCounter1[0] & tCounter1[1] & ~tCounter1[2] & ~tCounter1[3] & timeIn & clr;
    assign RCO = reach2;
    cnt_74ls163 ctr1(.load_time(loadtime1), .CP(clk), .CLR(~(reach1 | reach2)), .LOAD(clr), 
                            .P(timeIn), .T(timeIn), .dataOut(tCounter1[3:0]), .RCO(rco1));
    cnt_74ls163 ctr2(.load_time(loadtime2), .CP(clk), .CLR(~reach2), .LOAD(clr), 
                            .P(reach1), .T(reach1), .dataOut(tCounter2[3:0]), .RCO(rco2));
    
endmodule