data/full_repos/permissive/218779832/junk/InstructionRegister.v
data/verilator_xmls/cd3af172-8b4e-4ab2-858c-74c57a75598b.xml
module InstructionRegister(
    input             CLK,
    input             L_IR,
    input       [7:0] PM_in,
    output reg  [7:0] OC_out
    );
    
    initial     OC_out = 8'h00;

    always @(*)
    begin
        if(L_IR)
            OC_out = PM_in;
    end
endmodule
module InstructionRegister(
    input             CLK,
    input             L_IR,
    input       [7:0] PM_in,
    output reg  [7:0] OC_out
    );

    
    initial     OC_out = 8'h00;

    always @(*)
    begin
        if(L_IR)
            OC_out = PM_in;
    end
endmodule