data/full_repos/permissive/208358418/iverilog_tutorial/code_samples/simple.v
data/verilator_xmls/8b3ced6b-0c19-46b3-b6b6-011c81839efd.xml
module simple(A, B);

   input  [3:0] A;
   output [3:0] B;


   assign B = { A[0], A[2], A[1], A[3] };

endmodule
module simple(A, B);


   input  [3:0] A;
   output [3:0] B;


   assign B = { A[0], A[2], A[1], A[3] };

endmodule