data/full_repos/permissive/190426879/pipelined_cpu/pipelined_computer_sim.v
 line:114: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/190426879/pipelined_cpu/pipelined_computer_sim.v:77: Unsupported: Ignoring delay on this delayed statement.\n                #2  clock_50M_sim = ~clock_50M_sim;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/190426879/pipelined_cpu/pipelined_computer_sim.v:85: Unsupported: Ignoring delay on this delayed statement.\n                #2  mem_clk_sim = ~ mem_clk_sim;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/190426879/pipelined_cpu/pipelined_computer_sim.v:95: Unsupported: Ignoring delay on this delayed statement.\n                #5 resetn_sim = 1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/190426879/pipelined_cpu/pipelined_computer_sim.v:114: Unsupported: Ignoring delay on this delayed statement.\n    # 125000 $display($time,"out_port0 = %b  out_port1 = %b ", out_port0_sim,out_port1_sim,out_port2_sim,out_port3_sim,out_port4_sim,out_port5_sim );\n    ^\n%Error: data/full_repos/permissive/190426879/pipelined_cpu/pipelined_computer_sim.v:48: Cannot find file containing module: \'pipelined_computer\'\n    pipelined_computer    pipelined_computer_instance ( resetn_sim, clock_50M_sim, mem_clk_sim, pc_sim, inst_sim, ealuout_sim, maluout_sim, waluout_sim,\n    ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/190426879/pipelined_cpu,data/full_repos/permissive/190426879/pipelined_computer\n             data/full_repos/permissive/190426879/pipelined_cpu,data/full_repos/permissive/190426879/pipelined_computer.v\n             data/full_repos/permissive/190426879/pipelined_cpu,data/full_repos/permissive/190426879/pipelined_computer.sv\n             pipelined_computer\n             pipelined_computer.v\n             pipelined_computer.sv\n             obj_dir/pipelined_computer\n             obj_dir/pipelined_computer.v\n             obj_dir/pipelined_computer.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pipelined_computer_sim;

    reg           resetn_sim;
    reg           clock_50M_sim;
	 reg           mem_clk_sim;
	 reg    [3:0] in_port0_sim;
	 reg    [3:0] in_port1_sim;

	 

    wire   [6:0]  hex0_sim,hex1_sim,hex2_sim,hex3_sim,hex4_sim,hex5_sim;
	 wire   [9:0]  leds_sim;
	 
	       

	 
	 wire   [31:0]  pc_sim,inst_sim,ealuout_sim, maluout_sim, waluout_sim;
    wire   [31:0]  out_port0_sim,out_port1_sim,out_port2_sim,out_port3_sim,out_port4_sim,out_port5_sim;
    wire   [31:0]  data_sim;
   
    wire           wmem_sim;

    pipelined_computer    pipelined_computer_instance ( resetn_sim, clock_50M_sim, mem_clk_sim, pc_sim, inst_sim, ealuout_sim, maluout_sim, waluout_sim,
	                                      in_port0_sim, in_port1_sim, hex0_sim,hex1_sim,hex2_sim,hex3_sim,hex4_sim,hex5_sim,out_port0_sim,out_port1_sim,out_port2_sim,out_port3_sim,out_port4_sim,out_port5_sim);








										
						
	 initial
        begin
            clock_50M_sim = 1;
            while (1)
                #2  clock_50M_sim = ~clock_50M_sim;
        end

	   
	 initial
        begin
            mem_clk_sim = 0;
            while (1)
                #2  mem_clk_sim = ~ mem_clk_sim;
        end

	   	  
		  
		  
	 initial
        begin
            resetn_sim = 0;
            while (1)
                #5 resetn_sim = 1;
        end
	 
	 initial
	     begin
		      in_port0_sim = 5;
				in_port1_sim = 4;
		  end



	 
	 	  
		  
    initial
        begin
		  
          $display($time,"resetn=%b clock_50M=%b  mem_clk =%b", resetn_sim, clock_50M_sim, mem_clk_sim);
			 
			 # 125000 $display($time,"out_port0 = %b  out_port1 = %b ", out_port0_sim,out_port1_sim,out_port2_sim,out_port3_sim,out_port4_sim,out_port5_sim );

        end

endmodule
module pipelined_computer_sim;


    reg           resetn_sim;
    reg           clock_50M_sim;
	 reg           mem_clk_sim;
	 reg    [3:0] in_port0_sim;
	 reg    [3:0] in_port1_sim;

	 

    wire   [6:0]  hex0_sim,hex1_sim,hex2_sim,hex3_sim,hex4_sim,hex5_sim;
	 wire   [9:0]  leds_sim;
	 
	       

	 
	 wire   [31:0]  pc_sim,inst_sim,ealuout_sim, maluout_sim, waluout_sim;
    wire   [31:0]  out_port0_sim,out_port1_sim,out_port2_sim,out_port3_sim,out_port4_sim,out_port5_sim;
    wire   [31:0]  data_sim;
   
    wire           wmem_sim;

    pipelined_computer    pipelined_computer_instance ( resetn_sim, clock_50M_sim, mem_clk_sim, pc_sim, inst_sim, ealuout_sim, maluout_sim, waluout_sim,
	                                      in_port0_sim, in_port1_sim, hex0_sim,hex1_sim,hex2_sim,hex3_sim,hex4_sim,hex5_sim,out_port0_sim,out_port1_sim,out_port2_sim,out_port3_sim,out_port4_sim,out_port5_sim);








										
						
	 initial
        begin
            clock_50M_sim = 1;
            while (1)
                #2  clock_50M_sim = ~clock_50M_sim;
        end

	   
	 initial
        begin
            mem_clk_sim = 0;
            while (1)
                #2  mem_clk_sim = ~ mem_clk_sim;
        end

	   	  
		  
		  
	 initial
        begin
            resetn_sim = 0;
            while (1)
                #5 resetn_sim = 1;
        end
	 
	 initial
	     begin
		      in_port0_sim = 5;
				in_port1_sim = 4;
		  end



	 
	 	  
		  
    initial
        begin
		  
          $display($time,"resetn=%b clock_50M=%b  mem_clk =%b", resetn_sim, clock_50M_sim, mem_clk_sim);
			 
			 # 125000 $display($time,"out_port0 = %b  out_port1 = %b ", out_port0_sim,out_port1_sim,out_port2_sim,out_port3_sim,out_port4_sim,out_port5_sim );

        end

endmodule