data/full_repos/permissive/220229160/integrateinv-plugin/tests/toplevel/toplevel.v
 line:19: before: "("
1: b"%Error: data/full_repos/permissive/220229160/integrateinv-plugin/tests/toplevel/toplevel.v:31: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    output wire [2:0]  do\n                       ^~\n%Error: data/full_repos/permissive/220229160/integrateinv-plugin/tests/toplevel/toplevel.v:39: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n    box b0 (.A(d[0]), .Y(do[0]));\n                         ^~\n%Error: data/full_repos/permissive/220229160/integrateinv-plugin/tests/toplevel/toplevel.v:40: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n    box b1 (.A(d[1]), .Y(do[1]));\n                         ^~\n%Error: Exiting due to 3 error(s)\n"
module box(
    (* invertible_pin="INV_A" *)
    input  wire A,
    output wire Y
);

    parameter [0:0] INV_A = 1'b0;

endmodule
module box(
    (* invertible_pin="INV_A" *)
    input  wire A,
    output wire Y
);


    parameter [0:0] INV_A = 1'b0;

endmodule