data/full_repos/permissive/205055389/test/tkgate/error2.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/205055389/test/tkgate/error2.v:6: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'a'\n                                                                               : ... In instance top\n      a = 1;\n      ^\n%Error-PROCASSWIRE: data/full_repos/permissive/205055389/test/tkgate/error2.v:8: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'a'\n                                                                               : ... In instance top\n      a = 0;\n      ^\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top;
  wire a;

  initial
    begin
      a = 1;
      $display("a=%b",a);
      a = 0;
      $display("a=%b",a);
    end

endmodule
module top;

  wire a;

  initial
    begin
      a = 1;
      $display("a=%b",a);
      a = 0;
      $display("a=%b",a);
    end

endmodule