data/full_repos/permissive/177289247/ConditionCheck.v
data/verilator_xmls/ba9b0f23-e3ed-4246-8c6b-8a1ea3acd1dc.xml
module ConditionCheck (
    input[31:0] in0,
    input[31:0] in1,

    output reg  Equal
);

initial begin
    Equal <= 0;
end

always @(*) begin
    Equal <= (in0 == in1);
end

endmodule
module ConditionCheck (
    input[31:0] in0,
    input[31:0] in1,

    output reg  Equal
);


initial begin
    Equal <= 0;
end

always @(*) begin
    Equal <= (in0 == in1);
end

endmodule