data/full_repos/permissive/162696624/Traffic Light.v
 line:32: before: "["
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/162696624/Traffic\n        ... Looked in:\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.sv\n             data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624/Traffic.sv\n             obj_dir/data/full_repos/permissive/162696624/Traffic\n             obj_dir/data/full_repos/permissive/162696624/Traffic.v\n             obj_dir/data/full_repos/permissive/162696624/Traffic.sv\n%Error: Cannot find file containing module: Light.v\n%Error: Exiting due to 2 error(s)\n'
module test_counter;
  reg load,count,CLK,RST;
  reg [3:0]D0;
  reg [3:0]D1;
  wire [3:0]Q0;
  wire [3:0]Q1;
  
  two_bit_bcd tb(Q1,Q0,load,count,D1,D0,CLK,RST);
  
  initial 
  begin
    RST=0;
    CLK=0;
    #10
    RST=1;
    repeat(60)
  #5  CLK=~CLK;
    
  end
  
  
  initial 
  begin
    load=1;
    count=1;
    D0=4'b1001;
    D1=4'b0010;
    #10 load=0;
  end
endmodule
module test_counter;

  reg load,count,CLK,RST;
  reg [3:0]D0;
  reg [3:0]D1;
  wire [3:0]Q0;
  wire [3:0]Q1;
  
  two_bit_bcd tb(Q1,Q0,load,count,D1,D0,CLK,RST);
  
  initial 
  begin
    RST=0;
    CLK=0;
    #10
    RST=1;
    repeat(60)
  #5  CLK=~CLK;
    
  end
  
  
  initial 
  begin
    load=1;
    count=1;
    D0=4'b1001;
    D1=4'b0010;
    #10 load=0;
  end
endmodule