data/full_repos/permissive/149070951/examples/leds/leds_on/src/leds_on_tb.v
 line:32: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/149070951/examples/leds/leds_on/src/leds_on_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/149070951/examples/leds/leds_on/src/leds_on_tb.v:29: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("leds_on_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/149070951/examples/leds/leds_on/src/leds_on_tb.v:30: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, leds_on_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/149070951/examples/leds/leds_on/src/leds_on_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n   #(DURATION) $display("End of simulation");\n   ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module leds_on_tb();


parameter DURATION = 10;


reg clk = 0;
always #0.5 clk = ~clk;


wire [7:0] lport;


leds_on UUT (.LPORT(lport));


initial begin


  $dumpfile("leds_on_tb.vcd");
  $dumpvars(0, leds_on_tb);

   #(DURATION) $display("End of simulation");
  $finish;
end

endmodule
module leds_on_tb();



parameter DURATION = 10;


reg clk = 0;
always #0.5 clk = ~clk;


wire [7:0] lport;


leds_on UUT (.LPORT(lport));


initial begin


  $dumpfile("leds_on_tb.vcd");
  $dumpvars(0, leds_on_tb);

   #(DURATION) $display("End of simulation");
  $finish;
end

endmodule