data/full_repos/permissive/115920613/rtl/uart/uart.v
1: b"%Error: data/full_repos/permissive/115920613/rtl/uart/uart.v:47: Cannot find file containing module: 'async_transmitter'\n    async_transmitter #(ClkFrequency, Baud) my_tx (\n    ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115920613/rtl/uart,data/full_repos/permissive/115920613/async_transmitter\n             data/full_repos/permissive/115920613/rtl/uart,data/full_repos/permissive/115920613/async_transmitter.v\n             data/full_repos/permissive/115920613/rtl/uart,data/full_repos/permissive/115920613/async_transmitter.sv\n             async_transmitter\n             async_transmitter.v\n             async_transmitter.sv\n             obj_dir/async_transmitter\n             obj_dir/async_transmitter.v\n             obj_dir/async_transmitter.sv\n%Error: data/full_repos/permissive/115920613/rtl/uart/uart.v:61: Cannot find file containing module: 'async_receiver'\n    async_receiver #(ClkFrequency, Baud, Oversampling) my_rx(\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module uart(
    input clk,
    input enable,
    input rst,
    input [1:0] address,
    input w_en,
    input [7:0] din,
    output reg [7:0] dout,

    input uart_rx,
    output uart_tx,
    output uart_cts
    );

    parameter ClkFrequency = 25000000;
    parameter Baud = 115200;
    parameter Oversampling = 16;

    reg uart_tx_stb, uart_tx_init;
    reg [7:0] uart_tx_byte;
    wire uart_tx_status;

    async_transmitter #(ClkFrequency, Baud) my_tx (
        .clk(clk),
        .rst(rst),
        .TxD_start(uart_tx_stb),
        .TxD_data(uart_tx_byte),
        .TxD(uart_tx),
        .TxD_busy(uart_tx_status)
        );

    wire uart_rx_stb, rx_idle, rx_end;
    wire [7:0] rx_data;
    reg uart_rx_status, uart_rx_ack;
    reg [7:0] uart_rx_byte;

    async_receiver #(ClkFrequency, Baud, Oversampling) my_rx(
        .clk(clk),
        .rst(rst),
        .RxD(uart_rx),
        .RxD_data_ready(uart_rx_stb),
        .RxD_data(rx_data),
        .RxD_idle(rx_idle),
        .RxD_endofpacket(rx_end)
        );

    always @(posedge clk or posedge rst)
    begin
        if (rst)
        begin
            uart_rx_status <= 'b0;
            uart_rx_byte <= 8'd0;
        end
        else
        begin


            if (uart_rx_stb && ~uart_rx_status)
            begin
                uart_rx_status <= 'b1;
                uart_rx_byte <= rx_data;
            end


            if (uart_rx_ack)
                uart_rx_status <= 'b0;
        end
    end

    assign uart_cts = ~rx_idle || uart_rx_status;

    localparam UART_RX   = 2'b00;
    localparam UART_RXCR = 2'b01;
    localparam UART_TX   = 2'b10;
    localparam UART_TXCR = 2'b11;


    always @(posedge clk or posedge rst)
    begin
        if (rst)
        begin
            dout <= 8'd0;

            uart_tx_init <= 0;
            uart_tx_stb <= 0;
            uart_tx_byte <= 8'd0;
            uart_rx_ack <= 0;
        end
        else
        begin
            uart_tx_stb <= 0;
            uart_rx_ack <= 0;

            case (address)

            UART_RX:
            begin


                dout <= {1'b1, uart_rx_byte[6:0]};
                if (~w_en && ~uart_rx_ack && uart_rx_status && enable)
                    uart_rx_ack <= 1'b1;
            end

            UART_RXCR:
            begin

                dout <= {uart_rx_status, 7'b0};
            end

            UART_TX:
            begin

                dout <= {uart_tx_status, 7'd0};

                if (w_en)
                begin







                    if (~uart_tx_status && uart_tx_init)
                    begin
                        uart_tx_byte <= {1'b0, din[6:0]};
                        uart_tx_stb <= 1;
                    end
                    else if (~uart_tx_init)
                        uart_tx_init <= 1 && enable;
                end
            end

            UART_TXCR:
            begin


                dout <= 8'b0;
            end

            endcase
        end
    end
endmodule
module uart(
    input clk,
    input enable,
    input rst,
    input [1:0] address,
    input w_en,
    input [7:0] din,
    output reg [7:0] dout,

    input uart_rx,
    output uart_tx,
    output uart_cts
    );


    parameter ClkFrequency = 25000000;
    parameter Baud = 115200;
    parameter Oversampling = 16;

    reg uart_tx_stb, uart_tx_init;
    reg [7:0] uart_tx_byte;
    wire uart_tx_status;

    async_transmitter #(ClkFrequency, Baud) my_tx (
        .clk(clk),
        .rst(rst),
        .TxD_start(uart_tx_stb),
        .TxD_data(uart_tx_byte),
        .TxD(uart_tx),
        .TxD_busy(uart_tx_status)
        );

    wire uart_rx_stb, rx_idle, rx_end;
    wire [7:0] rx_data;
    reg uart_rx_status, uart_rx_ack;
    reg [7:0] uart_rx_byte;

    async_receiver #(ClkFrequency, Baud, Oversampling) my_rx(
        .clk(clk),
        .rst(rst),
        .RxD(uart_rx),
        .RxD_data_ready(uart_rx_stb),
        .RxD_data(rx_data),
        .RxD_idle(rx_idle),
        .RxD_endofpacket(rx_end)
        );

    always @(posedge clk or posedge rst)
    begin
        if (rst)
        begin
            uart_rx_status <= 'b0;
            uart_rx_byte <= 8'd0;
        end
        else
        begin


            if (uart_rx_stb && ~uart_rx_status)
            begin
                uart_rx_status <= 'b1;
                uart_rx_byte <= rx_data;
            end


            if (uart_rx_ack)
                uart_rx_status <= 'b0;
        end
    end

    assign uart_cts = ~rx_idle || uart_rx_status;

    localparam UART_RX   = 2'b00;
    localparam UART_RXCR = 2'b01;
    localparam UART_TX   = 2'b10;
    localparam UART_TXCR = 2'b11;


    always @(posedge clk or posedge rst)
    begin
        if (rst)
        begin
            dout <= 8'd0;

            uart_tx_init <= 0;
            uart_tx_stb <= 0;
            uart_tx_byte <= 8'd0;
            uart_rx_ack <= 0;
        end
        else
        begin
            uart_tx_stb <= 0;
            uart_rx_ack <= 0;

            case (address)

            UART_RX:
            begin


                dout <= {1'b1, uart_rx_byte[6:0]};
                if (~w_en && ~uart_rx_ack && uart_rx_status && enable)
                    uart_rx_ack <= 1'b1;
            end

            UART_RXCR:
            begin

                dout <= {uart_rx_status, 7'b0};
            end

            UART_TX:
            begin

                dout <= {uart_tx_status, 7'd0};

                if (w_en)
                begin







                    if (~uart_tx_status && uart_tx_init)
                    begin
                        uart_tx_byte <= {1'b0, din[6:0]};
                        uart_tx_stb <= 1;
                    end
                    else if (~uart_tx_init)
                        uart_tx_init <= 1 && enable;
                end
            end

            UART_TXCR:
            begin


                dout <= 8'b0;
            end

            endcase
        end
    end
endmodule