data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v:5: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v:10: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("system.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v:11: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0, system_tb);\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v:13: syntax error, unexpected \'@\'\n  repeat (100) @(posedge clk);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #88040 rxd = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #2070 rxd = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #19000 rxd = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #2070 rxd = 1;\n  ^\n%Error: data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v:40: Unsupported: $fflush of all handles does not map to C++.\n   $fflush;\n   ^~~~~~~\n%Error: data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v:48: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule regfile_dp(di, waddr, we, wclk, do, raddr);\n                                       ^~\n%Error: data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v:54: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n output reg [31:0] do;\n                   ^~\n%Error: data/full_repos/permissive/182791900/RISC-V/hardware/Picorv32/tb.v:67: syntax error, unexpected \'=\'\n  do = memory[raddr];\n     ^\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module system_tb;
	reg clk = 1;
	always #5 clk = ~clk;

	reg resetn = 0;
	initial begin

			$dumpfile("system.vcd");
			$dumpvars(0, system_tb);

		repeat (100) @(posedge clk);
		resetn <= 1;
	end

	wire trap;
	wire [7:0] out_byte;
	wire out_byte_en;
	reg rxd = 1;

	system uut (
		.clk        (clk        ),
		.resetn_i     (resetn     ),
		.trap       (trap       ),
		.out_byte   (out_byte   ),
		.out_byte_en(out_byte_en),
		.rxd	(rxd)
	);
	initial
	begin
		#88040 rxd = 0;
		#2070 rxd = 1;
		#19000 rxd = 0;
		#2070 rxd = 1;
	end
	always @(posedge clk) begin
		if (resetn && out_byte_en) begin
			$write("%c", out_byte);
			$fflush;
		end
		if (resetn && trap) begin
			$finish;
		end
	end
endmodule
module system_tb;

	reg clk = 1;
	always #5 clk = ~clk;

	reg resetn = 0;
	initial begin

			$dumpfile("system.vcd");
			$dumpvars(0, system_tb);

		repeat (100) @(posedge clk);
		resetn <= 1;
	end

	wire trap;
	wire [7:0] out_byte;
	wire out_byte_en;
	reg rxd = 1;

	system uut (
		.clk        (clk        ),
		.resetn_i     (resetn     ),
		.trap       (trap       ),
		.out_byte   (out_byte   ),
		.out_byte_en(out_byte_en),
		.rxd	(rxd)
	);
	initial
	begin
		#88040 rxd = 0;
		#2070 rxd = 1;
		#19000 rxd = 0;
		#2070 rxd = 1;
	end
	always @(posedge clk) begin
		if (resetn && out_byte_en) begin
			$write("%c", out_byte);
			$fflush;
		end
		if (resetn && trap) begin
			$finish;
		end
	end
endmodule