data/full_repos/permissive/150947952/scratch/fpga-md5/swedishhat/hardware/soc_ecp5_evn/attosoc_tb.v
 line:11: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/150947952/scratch/fpga-md5/swedishhat/hardware/soc_ecp5_evn/attosoc_tb.v:5: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = (clk === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/150947952/scratch/fpga-md5/swedishhat/hardware/soc_ecp5_evn/attosoc_tb.v:8: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("testbench.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/150947952/scratch/fpga-md5/swedishhat/hardware/soc_ecp5_evn/attosoc_tb.v:9: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, testbench);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/150947952/scratch/fpga-md5/swedishhat/hardware/soc_ecp5_evn/attosoc_tb.v:12: syntax error, unexpected \'@\'\n   repeat (50000) @(posedge clk);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/150947952/scratch/fpga-md5/swedishhat/hardware/soc_ecp5_evn/attosoc_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b", led);\n  ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

	reg clk;

	always #5 clk = (clk === 1'b0);

	initial begin
		$dumpfile("testbench.vcd");
		$dumpvars(0, testbench);

		repeat (10) begin
			repeat (50000) @(posedge clk);
			$display("+50000 cycles");
		end
		$finish;
	end

	wire [7:0] led;

	always @(led) begin
		#1 $display("%b", led);
	end

	attosoc uut (
		.clk      (clk      ),
		.led      (led      )
	);
endmodule
module testbench();


	reg clk;

	always #5 clk = (clk === 1'b0);

	initial begin
		$dumpfile("testbench.vcd");
		$dumpvars(0, testbench);

		repeat (10) begin
			repeat (50000) @(posedge clk);
			$display("+50000 cycles");
		end
		$finish;
	end

	wire [7:0] led;

	always @(led) begin
		#1 $display("%b", led);
	end

	attosoc uut (
		.clk      (clk      ),
		.led      (led      )
	);
endmodule