data/full_repos/permissive/165160692/04.FPGA/5932_extend_coder/stimulus/textbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_extend_coder/stimulus/textbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_extend_coder/stimulus/textbench.v:9: Cannot find file containing module: \'XYF\'\nXYF u1(.DataIn(datain),.DataIn_0(datain_0),.EI(ei),.Seg(seg));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_extend_coder/stimulus,data/full_repos/permissive/165160692/XYF\n             data/full_repos/permissive/165160692/04.FPGA/5932_extend_coder/stimulus,data/full_repos/permissive/165160692/XYF.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_extend_coder/stimulus,data/full_repos/permissive/165160692/XYF.sv\n             XYF\n             XYF.v\n             XYF.sv\n             obj_dir/XYF\n             obj_dir/XYF.v\n             obj_dir/XYF.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
reg[7:0]datain,datain_0;
reg ei;
reg[15:0]in,invec;
wire[7:0]seg;

XYF u1(.DataIn(datain),.DataIn_0(datain_0),.EI(ei),.Seg(seg));

initial
 begin
  ei=0;
  in=16'b0000000000000001;
  repeat(17)
   begin
    invec=~in;
    {datain,datain_0}=invec;
    #20;
    in=in<<1;
   end
  end
endmodule
module testbench();

reg[7:0]datain,datain_0;
reg ei;
reg[15:0]in,invec;
wire[7:0]seg;

XYF u1(.DataIn(datain),.DataIn_0(datain_0),.EI(ei),.Seg(seg));

initial
 begin
  ei=0;
  in=16'b0000000000000001;
  repeat(17)
   begin
    invec=~in;
    {datain,datain_0}=invec;
    #20;
    in=in<<1;
   end
  end
endmodule