data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v
 line:107: before: "begin"
1: b'%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:4: Define or directive not defined: \'`ADDRESS_BITS\'\n  localparam addrBits = `ADDRESS_BITS;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:4: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam addrBits = `ADDRESS_BITS;\n                                     ^\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:5: Define or directive not defined: \'`DATA_BITS\'\n  localparam dataBits = `DATA_BITS;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:5: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam dataBits = `DATA_BITS;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk <= ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:71: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:79: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:87: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:95: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:103: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:112: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:121: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:130: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:134: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("MessageDelivery_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:135: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, MessageDelivery_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n    #4 deliverToCore0Test;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n    #4 deliverToCore1Test;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n    #4 deliverToMemoryTest;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n    #4 deliverToMemoryAndJumpTest;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n    #4 $finish;\n    ^\n%Error: data/full_repos/permissive/187199324/stannel/MessageDelivery_tb.v:143: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n'
module MessageDelivery_tb();
  localparam addrBits = `ADDRESS_BITS;
  localparam dataBits = `DATA_BITS;

  reg clk = 0;
  always #1 clk <= ~clk;

  reg  [addrBits-1:0] address;
  reg  [dataBits-1:0] dataIn;
  wire [dataBits-1:0] dataOut;
  reg                 readWriteMode;



  IceRam #(.addrBits(addrBits), .dataBits(dataBits), .romFile("zeroes.hex")) ram0 (
    .clk          (clk),
    .address      (address),
    .readWriteMode(readWriteMode),
    .dataIn       (dataIn),
    .dataOut      (dataOut)
  );

  reg reset = 0;
  wire finished;

  reg [addrBits-1:0] core0Process;
  reg [addrBits-1:0] core1Process;

  reg  [addrBits-1:0] targetProcess;
  reg  [dataBits-1:0] message;
  reg  needsJump;
  reg  [8:0]          jumpDestination;

  wire deliverMessageToCore0;
  wire deliverMessageToCore1;

  MessageDelivery #(.addrBits(addrBits), .dataBits(dataBits)) msg (

    .clk                    (clk),
    .reset                  (reset),
    .finished               (finished),

    .memoryCellReadWriteMode(readWriteMode),
    .memoryCellAddress      (address),
    .memoryCellDataIn       (dataIn),
    .memoryCellDataOut      (dataOut),

    .core0Process           (core0Process),
    .core1Process           (core1Process),

    .targetProcess          (targetProcess),
    .message                (message),
    .needsJump              (needsJump),
    .jumpDestination        (jumpDestination),
    .deliverMessageToCore0  (deliverMessageToCore0),
    .deliverMessageToCore1  (deliverMessageToCore1)
  );

  task deliverToCore0Test;
    begin
      reset           <= 1;
      core0Process    <= 1;
      core1Process    <= 2;
      targetProcess   <= 1;
      message         <= 16'd42;
      needsJump       <= 0;
      jumpDestination <= 9'bx;

      @(posedge finished)
        begin
          reset <= 0;
          if (deliverMessageToCore0 != 1) $error("Expected to deliver to core 0");
          if (deliverMessageToCore1) $error("Not expecting to deliver to core 1");
          if (ram0.ram[0] != 0) $error("Modified stack pointers");
          if (ram0.ram[1] != 0) $error("Modified program counter");
        end
    end
  endtask

  task deliverToCore1Test;
    begin
      reset         <= 1;
      targetProcess <= 2;

      @(posedge finished)
        begin
          reset <= 0;
          if (deliverMessageToCore0) $error("Not expecting to deliver to core 0");
          if (!deliverMessageToCore1) $error("Expecting to deliver to core 1");
          if (ram0.ram[0] != 0) $error("Modified stack pointers");
          if (ram0.ram[1] != 0) $error("Modified program counter");
        end
    end
  endtask

  task deliverToMemoryTest;
    begin
      reset         <= 1;
      targetProcess <= 3;

      @(posedge finished)
        begin
          reset <= 0;
          if (deliverMessageToCore0) $error("Not expecting to deliver to core 0");
          if (deliverMessageToCore1) $error("Not expecting to deliver to core 1");
          if (ram0.ram[0] != 16'hFF00) $error("Incorrect stack pointers");
          if (ram0.ram[1] != 0) $error("Modified program counter");
          if (ram0.ram[8'hFF] != message) $error("Didn't deliver message");
        end
    end
  endtask

  task deliverToMemoryAndJumpTest;
    begin
      reset           <= 1;
      needsJump       <= 1;
      jumpDestination <= 9'd42;

      @(posedge finished)
        begin
          reset <= 0;
          if (deliverMessageToCore0) $error("Not expecting to deliver to core 0");
          if (deliverMessageToCore1) $error("Not expecting to deliver to core 1");
          if (ram0.ram[0] != 16'hFE00) $error("Incorrect stack pointers");
          if (ram0.ram[1] != 16'd42) $error("Modified program counter");
          if (ram0.ram[8'hFE] != message) $error("Didn't deliver message");
        end
    end
  endtask

  initial begin
    $dumpfile("MessageDelivery_tb.vcd");
    $dumpvars(0, MessageDelivery_tb);

    #4 deliverToCore0Test;
    #4 deliverToCore1Test;
    #4 deliverToMemoryTest;
    #4 deliverToMemoryAndJumpTest;

    #4 $finish;
  end

endmodule
module MessageDelivery_tb();

  localparam addrBits = `ADDRESS_BITS;
  localparam dataBits = `DATA_BITS;

  reg clk = 0;
  always #1 clk <= ~clk;

  reg  [addrBits-1:0] address;
  reg  [dataBits-1:0] dataIn;
  wire [dataBits-1:0] dataOut;
  reg                 readWriteMode;



  IceRam #(.addrBits(addrBits), .dataBits(dataBits), .romFile("zeroes.hex")) ram0 (
    .clk          (clk),
    .address      (address),
    .readWriteMode(readWriteMode),
    .dataIn       (dataIn),
    .dataOut      (dataOut)
  );

  reg reset = 0;
  wire finished;

  reg [addrBits-1:0] core0Process;
  reg [addrBits-1:0] core1Process;

  reg  [addrBits-1:0] targetProcess;
  reg  [dataBits-1:0] message;
  reg  needsJump;
  reg  [8:0]          jumpDestination;

  wire deliverMessageToCore0;
  wire deliverMessageToCore1;

  MessageDelivery #(.addrBits(addrBits), .dataBits(dataBits)) msg (

    .clk                    (clk),
    .reset                  (reset),
    .finished               (finished),

    .memoryCellReadWriteMode(readWriteMode),
    .memoryCellAddress      (address),
    .memoryCellDataIn       (dataIn),
    .memoryCellDataOut      (dataOut),

    .core0Process           (core0Process),
    .core1Process           (core1Process),

    .targetProcess          (targetProcess),
    .message                (message),
    .needsJump              (needsJump),
    .jumpDestination        (jumpDestination),
    .deliverMessageToCore0  (deliverMessageToCore0),
    .deliverMessageToCore1  (deliverMessageToCore1)
  );

  task deliverToCore0Test;
    begin
      reset           <= 1;
      core0Process    <= 1;
      core1Process    <= 2;
      targetProcess   <= 1;
      message         <= 16'd42;
      needsJump       <= 0;
      jumpDestination <= 9'bx;

      @(posedge finished)
        begin
          reset <= 0;
          if (deliverMessageToCore0 != 1) $error("Expected to deliver to core 0");
          if (deliverMessageToCore1) $error("Not expecting to deliver to core 1");
          if (ram0.ram[0] != 0) $error("Modified stack pointers");
          if (ram0.ram[1] != 0) $error("Modified program counter");
        end
    end
  endtask

  task deliverToCore1Test;
    begin
      reset         <= 1;
      targetProcess <= 2;

      @(posedge finished)
        begin
          reset <= 0;
          if (deliverMessageToCore0) $error("Not expecting to deliver to core 0");
          if (!deliverMessageToCore1) $error("Expecting to deliver to core 1");
          if (ram0.ram[0] != 0) $error("Modified stack pointers");
          if (ram0.ram[1] != 0) $error("Modified program counter");
        end
    end
  endtask

  task deliverToMemoryTest;
    begin
      reset         <= 1;
      targetProcess <= 3;

      @(posedge finished)
        begin
          reset <= 0;
          if (deliverMessageToCore0) $error("Not expecting to deliver to core 0");
          if (deliverMessageToCore1) $error("Not expecting to deliver to core 1");
          if (ram0.ram[0] != 16'hFF00) $error("Incorrect stack pointers");
          if (ram0.ram[1] != 0) $error("Modified program counter");
          if (ram0.ram[8'hFF] != message) $error("Didn't deliver message");
        end
    end
  endtask

  task deliverToMemoryAndJumpTest;
    begin
      reset           <= 1;
      needsJump       <= 1;
      jumpDestination <= 9'd42;

      @(posedge finished)
        begin
          reset <= 0;
          if (deliverMessageToCore0) $error("Not expecting to deliver to core 0");
          if (deliverMessageToCore1) $error("Not expecting to deliver to core 1");
          if (ram0.ram[0] != 16'hFE00) $error("Incorrect stack pointers");
          if (ram0.ram[1] != 16'd42) $error("Modified program counter");
          if (ram0.ram[8'hFE] != message) $error("Didn't deliver message");
        end
    end
  endtask

  initial begin
    $dumpfile("MessageDelivery_tb.vcd");
    $dumpvars(0, MessageDelivery_tb);

    #4 deliverToCore0Test;
    #4 deliverToCore1Test;
    #4 deliverToMemoryTest;
    #4 deliverToMemoryAndJumpTest;

    #4 $finish;
  end

endmodule