data/full_repos/permissive/118252043/rtl/rules.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/118252043/rtl/rules.v:12: Little bit endian vector: MSB < LSB of bit range: 0:19\n   reg [0:MAX_i] screen [0:MAX_j];\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/118252043/rtl/rules.v:13: Little bit endian vector: MSB < LSB of bit range: 0:19\n   reg [0:MAX_i] next_screen [0:MAX_j];\n       ^\n%Warning-WIDTH: data/full_repos/permissive/118252043/rtl/rules.v:27: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                   : ... In instance rules\n            case (sum_neighbours)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/118252043/rtl/rules.v:27: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                   : ... In instance rules\n            case (sum_neighbours)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/118252043/rtl/rules.v:27: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n                                                                   : ... In instance rules\n            case (sum_neighbours)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/118252043/rtl/rules.v:27: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n                                                                   : ... In instance rules\n            case (sum_neighbours)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/118252043/rtl/rules.v:39: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n                                                                   : ... In instance rules\n            case (sum_neighbours)\n            ^~~~\n%Error: Exiting due to 7 warning(s)\n'
module rules(
		input wire       clk,
		input wire       clr,
    input wire [4:0] sum_neighbours,
		input wire [9:0] VGAx,
		input wire [9:0] VGAy,
		output reg [2:0] rgb
		);

   parameter MAX_j = 14;
   parameter MAX_i = 19;
   reg [0:MAX_i] screen [0:MAX_j];
   reg [0:MAX_i] next_screen [0:MAX_j];
   reg [9:0] 	 i;
   reg [9:0] 	 j;

   wire [4:0] 			   x = VGAx[9:5];
   wire [3:0] 			   y = VGAy[8:5];



   always @(*)
     begin

	      if (screen[y][x] == 1)
	        begin
	           case (sum_neighbours)

	             4'b0000, 4'b0001: next_screen[y][x] = 0;

	             4'b0010, 4'b0011: next_screen[y][x] = 1;

	             default: next_screen[y][x] = 0;
	           endcase
	        end

	      else
	        begin
	           case (sum_neighbours)

	             4'b0011: next_screen[y][x] = 1;
	             default: next_screen[y][x] = 0;
	           endcase
	        end
     end
endmodule
module rules(
		input wire       clk,
		input wire       clr,
    input wire [4:0] sum_neighbours,
		input wire [9:0] VGAx,
		input wire [9:0] VGAy,
		output reg [2:0] rgb
		);


   parameter MAX_j = 14;
   parameter MAX_i = 19;
   reg [0:MAX_i] screen [0:MAX_j];
   reg [0:MAX_i] next_screen [0:MAX_j];
   reg [9:0] 	 i;
   reg [9:0] 	 j;

   wire [4:0] 			   x = VGAx[9:5];
   wire [3:0] 			   y = VGAy[8:5];



   always @(*)
     begin

	      if (screen[y][x] == 1)
	        begin
	           case (sum_neighbours)

	             4'b0000, 4'b0001: next_screen[y][x] = 0;

	             4'b0010, 4'b0011: next_screen[y][x] = 1;

	             default: next_screen[y][x] = 0;
	           endcase
	        end

	      else
	        begin
	           case (sum_neighbours)

	             4'b0011: next_screen[y][x] = 1;
	             default: next_screen[y][x] = 0;
	           endcase
	        end
     end
endmodule