data/full_repos/permissive/143278/ivltests/br995.v
data/verilator_xmls/8a85a7bb-559c-4475-9599-ffe19810583f.xml
module dpram #(
	parameter aw=8,
	parameter dw=8
) (input clka, clkb, wena,
	input [aw-1:0] addra, addrb,
	input [dw-1:0] dina,
	output [dw-1:0] doutb
);

localparam sz=(32'b1<<aw)-1;
reg [dw-1:0] mem[sz:0];
reg [aw-1:0] alb=0;
(* ivl_synthesis_on *)
always @(posedge clka) if (wena) mem[addra] <= dina;
always @(posedge clkb) alb <= addrb;
assign doutb = mem[alb];
(* ivl_synthesis_off *)
initial $display("PASSED");
endmodule
module dpram #(
	parameter aw=8,
	parameter dw=8
) (input clka, clkb, wena,
	input [aw-1:0] addra, addrb,
	input [dw-1:0] dina,
	output [dw-1:0] doutb
);


localparam sz=(32'b1<<aw)-1;
reg [dw-1:0] mem[sz:0];
reg [aw-1:0] alb=0;
(* ivl_synthesis_on *)
always @(posedge clka) if (wena) mem[addra] <= dina;
always @(posedge clkb) alb <= addrb;
assign doutb = mem[alb];
(* ivl_synthesis_off *)
initial $display("PASSED");
endmodule