data/full_repos/permissive/143278/ivltests/select3.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/143278/ivltests/select3.v:29: syntax error, unexpected \'.\', expecting \'=\'\n   defparam test.dut.INIT = 16\'h55aa;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/select3.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("dut[%h] = %b", a, o);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module RAM (O, A);

    parameter INIT = 16'h0000;

    output O;

    input [3:0] A;

    reg  mem [15:0];
    reg  [4:0] count;
    wire [3:0] adr;

    buf (O, mem[A]);

    initial
    begin
	for (count = 0; count < 16; count = count + 1)
	    mem[count] <= INIT[count];
    end

endmodule
module RAM (O, A);


    parameter INIT = 16'h0000;

    output O;

    input [3:0] A;

    reg  mem [15:0];
    reg  [4:0] count;
    wire [3:0] adr;

    buf (O, mem[A]);

    initial
    begin
	for (count = 0; count < 16; count = count + 1)
	    mem[count] <= INIT[count];
    end

endmodule