data/full_repos/permissive/155713836/src/fifos_interface.v
1: b"%Error: data/full_repos/permissive/155713836/src/fifos_interface.v:84: Cannot find file containing module: 'fifo'\n  fifo M_fifo_sreq (\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/155713836/src,data/full_repos/permissive/155713836/fifo\n             data/full_repos/permissive/155713836/src,data/full_repos/permissive/155713836/fifo.v\n             data/full_repos/permissive/155713836/src,data/full_repos/permissive/155713836/fifo.sv\n             fifo\n             fifo.v\n             fifo.sv\n             obj_dir/fifo\n             obj_dir/fifo.v\n             obj_dir/fifo.sv\n%Error: data/full_repos/permissive/155713836/src/fifos_interface.v:97: Cannot find file containing module: 'fifo'\n  fifo S_fifo_rreq (\n  ^~~~\n%Error: data/full_repos/permissive/155713836/src/fifos_interface.v:111: Cannot find file containing module: 'fifo'\n  fifo S_fifo_sresp (\n  ^~~~\n%Error: data/full_repos/permissive/155713836/src/fifos_interface.v:124: Cannot find file containing module: 'fifo'\n  fifo M_fifo_rresp (\n  ^~~~\n%Error: Exiting due to 4 error(s)\n"
module fifos_interface (
  clk,


  i_mc_sreq_inbits,
  i_mc_sreq_wen,
  o_mc_sreq_fifo_empty,
  o_mc_sreq_fifo_full,
  

  i_sc_rreq_ren,
  o_sc_rreq_outbits,


  i_sc_sresp_inbits,
  i_sc_sresp_wen,
  o_sc_sresp_fifo_empty,
  o_sc_sresp_fifo_full,



  i_mc_rresp_ren,
  o_mc_rresp_outbits,


  o_credits_m2s,
  o_credits_s2m

);

  parameter FIFO_DEPTH = 32;
  parameter LOG2_FIFO_DEPTH = 5;
  parameter DATA_LINE_WIDTH = 40;
  parameter CONTROL_LINE_WIDTH = 0;

  input clk;




  input [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_mc_sreq_inbits;
  input i_mc_sreq_wen;
  output o_mc_sreq_fifo_empty;
  output o_mc_sreq_fifo_full;

  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] w_req_bus;


  input i_sc_rreq_ren;
  output [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] o_sc_rreq_outbits;
  wire w_sc_rreq_fifo_empty;
  wire w_sc_rreq_fifo_full;


  input [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_sc_sresp_inbits;
  input i_sc_sresp_wen;
  output o_sc_sresp_fifo_empty;
  output o_sc_sresp_fifo_full;

  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] w_resp_bus;


  input i_mc_rresp_ren;
  output [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] o_mc_rresp_outbits;
  wire w_mc_rresp_fifo_empty;
  wire w_mc_rresp_fifo_full;


  output wire [LOG2_FIFO_DEPTH:0] o_credits_m2s;
  output wire [LOG2_FIFO_DEPTH:0] o_credits_s2m;

  reg [LOG2_FIFO_DEPTH:0] credits_m2s = FIFO_DEPTH;
  reg [LOG2_FIFO_DEPTH:0] credits_s2m = FIFO_DEPTH;


  fifo M_fifo_sreq (
    .clk(clk),

    .i_read_packet_en(!w_sc_rreq_fifo_full),
    .i_write_packet_en(i_mc_sreq_wen),
    .i_write_packet(i_mc_sreq_inbits),

    .o_read_packet(w_req_bus),
    .o_empty_flag(o_mc_data_sr_empty),
    .o_full_flag(o_mc_data_sr_full)
  );


  fifo S_fifo_rreq (
    .clk(clk),

    .i_read_packet_en(i_sc_rreq_ren),
    .i_write_packet_en(!w_sc_rreq_fifo_full),
    .i_write_packet(w_req_bus),

    .o_read_packet(o_sc_rreq_outbits),
    .o_empty_flag(w_sc_rreq_fifo_empty),
    .o_full_flag(w_sc_rreq_fifo_full)
  );



  fifo S_fifo_sresp (
    .clk(clk),

    .i_read_packet_en(!w_mc_rresp_fifo_full),
    .i_write_packet_en(i_sc_sresp_wen),
    .i_write_packet(i_sc_sresp_inbits),

    .o_read_packet(w_resp_bus),
    .o_empty_flag(o_sc_sresp_fifo_empty),
    .o_full_flag(o_sc_sresp_fifo_full)
  );


  fifo M_fifo_rresp (
    .clk(clk),

    .i_read_packet_en(i_mc_rresp_ren),
    .i_write_packet_en(!w_mc_rresp_fifo_full),
    .i_write_packet(w_resp_bus),

    .o_read_packet(o_mc_rresp_outbits),
    .o_empty_flag(w_mc_rresp_fifo_empty),
    .o_full_flag(w_mc_rresp_fifo_full)
  );





  always @ (posedge clk) begin
    if ((i_sc_rreq_ren) && (!w_sc_rreq_fifo_full)) begin
      credits_m2s <= credits_m2s;
    end else if ((i_sc_rreq_ren) && (credits_m2s < FIFO_DEPTH)) begin
      credits_m2s <= credits_m2s + 1'b1;
    end else if ((!w_sc_rreq_fifo_full) && (credits_m2s < FIFO_DEPTH)) begin
      credits_m2s <= credits_m2s - 1'b1;
    end

    if ((i_mc_rresp_ren) && (!w_mc_rresp_fifo_full)) begin
      credits_s2m <= credits_s2m;
    end else if ((i_mc_rresp_ren) && (credits_m2s < FIFO_DEPTH)) begin
      credits_s2m <= credits_s2m + 1'b1;
    end else if ((!w_mc_rresp_fifo_full) && (credits_m2s < FIFO_DEPTH)) begin
      credits_s2m <= credits_s2m - 1'b1;
    end

  end 
  
  assign o_credits_s2m = credits_s2m;
  assign o_credits_m2s = credits_m2s;



endmodule
module fifos_interface (
  clk,


  i_mc_sreq_inbits,
  i_mc_sreq_wen,
  o_mc_sreq_fifo_empty,
  o_mc_sreq_fifo_full,
  

  i_sc_rreq_ren,
  o_sc_rreq_outbits,


  i_sc_sresp_inbits,
  i_sc_sresp_wen,
  o_sc_sresp_fifo_empty,
  o_sc_sresp_fifo_full,



  i_mc_rresp_ren,
  o_mc_rresp_outbits,


  o_credits_m2s,
  o_credits_s2m

);


  parameter FIFO_DEPTH = 32;
  parameter LOG2_FIFO_DEPTH = 5;
  parameter DATA_LINE_WIDTH = 40;
  parameter CONTROL_LINE_WIDTH = 0;

  input clk;




  input [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_mc_sreq_inbits;
  input i_mc_sreq_wen;
  output o_mc_sreq_fifo_empty;
  output o_mc_sreq_fifo_full;

  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] w_req_bus;


  input i_sc_rreq_ren;
  output [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] o_sc_rreq_outbits;
  wire w_sc_rreq_fifo_empty;
  wire w_sc_rreq_fifo_full;


  input [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_sc_sresp_inbits;
  input i_sc_sresp_wen;
  output o_sc_sresp_fifo_empty;
  output o_sc_sresp_fifo_full;

  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] w_resp_bus;


  input i_mc_rresp_ren;
  output [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] o_mc_rresp_outbits;
  wire w_mc_rresp_fifo_empty;
  wire w_mc_rresp_fifo_full;


  output wire [LOG2_FIFO_DEPTH:0] o_credits_m2s;
  output wire [LOG2_FIFO_DEPTH:0] o_credits_s2m;

  reg [LOG2_FIFO_DEPTH:0] credits_m2s = FIFO_DEPTH;
  reg [LOG2_FIFO_DEPTH:0] credits_s2m = FIFO_DEPTH;


  fifo M_fifo_sreq (
    .clk(clk),

    .i_read_packet_en(!w_sc_rreq_fifo_full),
    .i_write_packet_en(i_mc_sreq_wen),
    .i_write_packet(i_mc_sreq_inbits),

    .o_read_packet(w_req_bus),
    .o_empty_flag(o_mc_data_sr_empty),
    .o_full_flag(o_mc_data_sr_full)
  );


  fifo S_fifo_rreq (
    .clk(clk),

    .i_read_packet_en(i_sc_rreq_ren),
    .i_write_packet_en(!w_sc_rreq_fifo_full),
    .i_write_packet(w_req_bus),

    .o_read_packet(o_sc_rreq_outbits),
    .o_empty_flag(w_sc_rreq_fifo_empty),
    .o_full_flag(w_sc_rreq_fifo_full)
  );



  fifo S_fifo_sresp (
    .clk(clk),

    .i_read_packet_en(!w_mc_rresp_fifo_full),
    .i_write_packet_en(i_sc_sresp_wen),
    .i_write_packet(i_sc_sresp_inbits),

    .o_read_packet(w_resp_bus),
    .o_empty_flag(o_sc_sresp_fifo_empty),
    .o_full_flag(o_sc_sresp_fifo_full)
  );


  fifo M_fifo_rresp (
    .clk(clk),

    .i_read_packet_en(i_mc_rresp_ren),
    .i_write_packet_en(!w_mc_rresp_fifo_full),
    .i_write_packet(w_resp_bus),

    .o_read_packet(o_mc_rresp_outbits),
    .o_empty_flag(w_mc_rresp_fifo_empty),
    .o_full_flag(w_mc_rresp_fifo_full)
  );





  always @ (posedge clk) begin
    if ((i_sc_rreq_ren) && (!w_sc_rreq_fifo_full)) begin
      credits_m2s <= credits_m2s;
    end else if ((i_sc_rreq_ren) && (credits_m2s < FIFO_DEPTH)) begin
      credits_m2s <= credits_m2s + 1'b1;
    end else if ((!w_sc_rreq_fifo_full) && (credits_m2s < FIFO_DEPTH)) begin
      credits_m2s <= credits_m2s - 1'b1;
    end

    if ((i_mc_rresp_ren) && (!w_mc_rresp_fifo_full)) begin
      credits_s2m <= credits_s2m;
    end else if ((i_mc_rresp_ren) && (credits_m2s < FIFO_DEPTH)) begin
      credits_s2m <= credits_s2m + 1'b1;
    end else if ((!w_mc_rresp_fifo_full) && (credits_m2s < FIFO_DEPTH)) begin
      credits_s2m <= credits_s2m - 1'b1;
    end

  end 
  
  assign o_credits_s2m = credits_s2m;
  assign o_credits_m2s = credits_m2s;



endmodule