data/full_repos/permissive/202237519/verilog/digitalsystem4/div_tb.v
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem4/div_tb.v:1: Cannot find include file: div.v\n`include "div.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem4,data/full_repos/permissive/202237519/div.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem4,data/full_repos/permissive/202237519/div.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem4,data/full_repos/permissive/202237519/div.v.sv\n             div.v\n             div.v.v\n             div.v.sv\n             obj_dir/div.v\n             obj_dir/div.v.v\n             obj_dir/div.v.sv\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem4/div_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("div_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem4/div_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,divier_tb);  \n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem4/div_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\nA <= 4\'b1010; B <= 4\'b0011; #10;\n                            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem4/div_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\nA <= 4\'b0101; B <= 4\'b0101; #10;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem4/div_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\nA <= 4\'b0111; B <= 4\'b0010; #10;\n                            ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module divier_tb;

reg[3:0]A,B;
wire [3:0]Q,R;

divider div0(A,B,Q,R);

initial begin
$dumpfile("div_tb.vcd");
$dumpvars(0,divier_tb);
A <= 4'b1010; B <= 4'b0011; #10;
A <= 4'b0101; B <= 4'b0101; #10;
A <= 4'b0111; B <= 4'b0010; #10;
$finish;
end




endmodule
module divier_tb;


reg[3:0]A,B;
wire [3:0]Q,R;

divider div0(A,B,Q,R);

initial begin
$dumpfile("div_tb.vcd");
$dumpvars(0,divier_tb);
A <= 4'b1010; B <= 4'b0011; #10;
A <= 4'b0101; B <= 4'b0101; #10;
A <= 4'b0111; B <= 4'b0010; #10;
$finish;
end




endmodule