data/full_repos/permissive/163446101/InstructionMemory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h6c\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h70\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h74\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h78\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h7c\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h80\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h84\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h88\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h8c\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h90\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h94\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h98\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h9c\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'ha0\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'ha4\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'ha8\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hac\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hb0\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hb4\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hb8\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hbc\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hc0\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hc4\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hc8\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hcc\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hd0\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hd4\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hd8\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hdc\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'he0\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'he4\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'he8\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hec\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hf0\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hf4\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hf8\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'hfc\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163446101/InstructionMemory.v:23: Operator CASE expects 64 bits on the Case Item, but Case Item\'s CONST \'63\'h100\' generates 63 bits.\n                                                                           : ... In instance InstructionMemory\n        case(Address)\n        ^~~~\n%Error: Exiting due to 38 warning(s)\n'
module InstructionMemory(Instruction, Address);
    input [63:0] Address;

    output [31:0] Instruction;

    reg [31:0] Instruction;
    
    always @ (Address) begin
        case(Address)
    	64'h000: Instruction = 32'hF84083EA;
    	64'h004: Instruction = 32'hF84103EB;
    	64'h008: Instruction = 32'hF84183EC;
		64'h00c: Instruction = 32'hF84003E9;
		64'h010: Instruction = 32'hF84203ED;
		64'h014: Instruction = 32'hAA0B014A;
		64'h018: Instruction = `NOP;
		64'h01c: Instruction = `NOP;
		64'h020: Instruction = 32'h8A0A018C;
		64'h024: Instruction = `NOP;
		64'h028: Instruction = `NOP;
		64'h02c: Instruction = 32'hB400014C;
		64'h030: Instruction = `NOP;
		64'h034: Instruction = `NOP;
		64'h038: Instruction = `NOP;
		64'h03c: Instruction = 32'h8B0901AD;
		64'h040: Instruction = 32'hCB09018C;
		64'h044: Instruction = 32'h17FFFFFA;
		64'h048: Instruction = `NOP;
		64'h04c: Instruction = `NOP;
		64'h050: Instruction = `NOP;
		64'h054: Instruction = 32'hF80203ED;
		64'h058: Instruction = 32'hF84203ED;
		64'h05c: Instruction = `NOP;
		64'h060: Instruction = `NOP;
		64'h064: Instruction = `NOP;
		64'h068: Instruction = `NOP;
		63'h06c: Instruction = 32'h8B1F03E9;
		63'h070: Instruction = `NOP;
		63'h074: Instruction = `NOP;
		63'h078: Instruction = 32'hB2048D29;
		63'h07c: Instruction = `NOP;
		63'h080: Instruction = `NOP;
		63'h084: Instruction = 32'hD37F3129;
		63'h088: Instruction = `NOP;
		63'h08c: Instruction = `NOP;
		63'h090: Instruction = 32'hB2115929;
		63'h094: Instruction = `NOP;
		63'h098: Instruction = `NOP;
		63'h09c: Instruction = 32'hD37F3129;
		63'h0a0: Instruction = `NOP;
		63'h0a4: Instruction = `NOP;
		63'h0a8: Instruction = 32'hB21E2529;
		63'h0ac: Instruction = `NOP;
		63'h0b0: Instruction = `NOP;
		63'h0b4: Instruction = 32'hD37F3129;
		63'h0b8: Instruction = `NOP;
		63'h0bc: Instruction = `NOP;
		63'h0c0: Instruction = 32'hB22AF129;
		63'h0c4: Instruction = `NOP;
		63'h0c8: Instruction = `NOP;
		63'h0cc: Instruction = 32'hD37F3129;
		63'h0d0: Instruction = `NOP;
		63'h0d4: Instruction = `NOP;
		63'h0d8: Instruction = 32'hB237BD29;
		63'h0dc: Instruction = `NOP;
		63'h0e0: Instruction = `NOP;
		63'h0e4: Instruction = 32'hD37F1129;
		63'h0e8: Instruction = `NOP;
		63'h0ec: Instruction = `NOP;
		63'h0f0: Instruction = 32'hF80283E9;
		63'h0f4: Instruction = `NOP;
		63'h0f8: Instruction = `NOP;
		63'h0fc: Instruction = `NOP;
		63'h100: Instruction = 32'hF84283EA;
		default: Instruction = `NOP;
        endcase
    end
endmodule
module InstructionMemory(Instruction, Address);

    input [63:0] Address;

    output [31:0] Instruction;

    reg [31:0] Instruction;
    
    always @ (Address) begin
        case(Address)
    	64'h000: Instruction = 32'hF84083EA;
    	64'h004: Instruction = 32'hF84103EB;
    	64'h008: Instruction = 32'hF84183EC;
		64'h00c: Instruction = 32'hF84003E9;
		64'h010: Instruction = 32'hF84203ED;
		64'h014: Instruction = 32'hAA0B014A;
		64'h018: Instruction = `NOP;
		64'h01c: Instruction = `NOP;
		64'h020: Instruction = 32'h8A0A018C;
		64'h024: Instruction = `NOP;
		64'h028: Instruction = `NOP;
		64'h02c: Instruction = 32'hB400014C;
		64'h030: Instruction = `NOP;
		64'h034: Instruction = `NOP;
		64'h038: Instruction = `NOP;
		64'h03c: Instruction = 32'h8B0901AD;
		64'h040: Instruction = 32'hCB09018C;
		64'h044: Instruction = 32'h17FFFFFA;
		64'h048: Instruction = `NOP;
		64'h04c: Instruction = `NOP;
		64'h050: Instruction = `NOP;
		64'h054: Instruction = 32'hF80203ED;
		64'h058: Instruction = 32'hF84203ED;
		64'h05c: Instruction = `NOP;
		64'h060: Instruction = `NOP;
		64'h064: Instruction = `NOP;
		64'h068: Instruction = `NOP;
		63'h06c: Instruction = 32'h8B1F03E9;
		63'h070: Instruction = `NOP;
		63'h074: Instruction = `NOP;
		63'h078: Instruction = 32'hB2048D29;
		63'h07c: Instruction = `NOP;
		63'h080: Instruction = `NOP;
		63'h084: Instruction = 32'hD37F3129;
		63'h088: Instruction = `NOP;
		63'h08c: Instruction = `NOP;
		63'h090: Instruction = 32'hB2115929;
		63'h094: Instruction = `NOP;
		63'h098: Instruction = `NOP;
		63'h09c: Instruction = 32'hD37F3129;
		63'h0a0: Instruction = `NOP;
		63'h0a4: Instruction = `NOP;
		63'h0a8: Instruction = 32'hB21E2529;
		63'h0ac: Instruction = `NOP;
		63'h0b0: Instruction = `NOP;
		63'h0b4: Instruction = 32'hD37F3129;
		63'h0b8: Instruction = `NOP;
		63'h0bc: Instruction = `NOP;
		63'h0c0: Instruction = 32'hB22AF129;
		63'h0c4: Instruction = `NOP;
		63'h0c8: Instruction = `NOP;
		63'h0cc: Instruction = 32'hD37F3129;
		63'h0d0: Instruction = `NOP;
		63'h0d4: Instruction = `NOP;
		63'h0d8: Instruction = 32'hB237BD29;
		63'h0dc: Instruction = `NOP;
		63'h0e0: Instruction = `NOP;
		63'h0e4: Instruction = 32'hD37F1129;
		63'h0e8: Instruction = `NOP;
		63'h0ec: Instruction = `NOP;
		63'h0f0: Instruction = 32'hF80283E9;
		63'h0f4: Instruction = `NOP;
		63'h0f8: Instruction = `NOP;
		63'h0fc: Instruction = `NOP;
		63'h100: Instruction = 32'hF84283EA;
		default: Instruction = `NOP;
        endcase
    end
endmodule