data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Multication/fixed_point/sMult.v
1: b'%Error: Cannot find file containing module: Project/SourceCode/Multication/fixed_point,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Multication/fixed_point,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Multication/fixed_point,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Multication/fixed_point,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Multication/fixed_point,data/full_repos/permissive/119107706\n             Project/SourceCode/Multication/fixed_point,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Multication/fixed_point,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Multication/fixed_point,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Multication/fixed_point,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Multication/fixed_point,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Multication/fixed_point/sMult.v\n%Error: Exiting due to 3 error(s)\n'
module sMult
		   # (parameter WI1 = 4,
							 WF1 = 3,
							 WI2 = 2,
							 WF2 = 5,


							 WIO = 1,		
							 WFO = 15
							 ) 		
	(input CLK, RST, input signed [WI1+WF1-1 : 0] in1, input signed [WI2+WF2-1 : 0] in2, output reg signed [WIO+WFO-1 : 0] out);
	
	
localparam intL = WI1+WI2;
localparam frcL = WF1+WF2;
		
wire [intL+frcL-1 : 0] tmp;
reg [WIO-1 : 0] outI;
reg [WFO-1 : 0] outF;

	assign tmp = in1 * in2;


always  @* begin

	if (WFO >= frcL)
			outF = {tmp[frcL-1:0] , {(WFO-frcL){1'b0}}};
	else
			outF = tmp[frcL-1 : frcL-WFO];
end



always @* begin
	if (WIO>=intL)
			outI = {{(WIO-intL){tmp[intL+frcL-1]}}, tmp[intL+frcL-1:frcL]};
	else	begin
		if (WIO==1)
			outI = tmp[intL+frcL-1];
		else
		    outI = {tmp[intL+frcL-1], tmp[`X_trc:frcL]};						
	end
end



always @*
	if (!RST) 
		out <= 0;
	else 		
		out <= {outI [WIO-1:0], outF [WFO-1:0]};
	
endmodule
module sMult
		   # (parameter WI1 = 4,
							 WF1 = 3,
							 WI2 = 2,
							 WF2 = 5,


							 WIO = 1,		
							 WFO = 15
							 ) 		
	(input CLK, RST, input signed [WI1+WF1-1 : 0] in1, input signed [WI2+WF2-1 : 0] in2, output reg signed [WIO+WFO-1 : 0] out);

	
	
localparam intL = WI1+WI2;
localparam frcL = WF1+WF2;
		
wire [intL+frcL-1 : 0] tmp;
reg [WIO-1 : 0] outI;
reg [WFO-1 : 0] outF;

	assign tmp = in1 * in2;


always  @* begin

	if (WFO >= frcL)
			outF = {tmp[frcL-1:0] , {(WFO-frcL){1'b0}}};
	else
			outF = tmp[frcL-1 : frcL-WFO];
end



always @* begin
	if (WIO>=intL)
			outI = {{(WIO-intL){tmp[intL+frcL-1]}}, tmp[intL+frcL-1:frcL]};
	else	begin
		if (WIO==1)
			outI = tmp[intL+frcL-1];
		else
		    outI = {tmp[intL+frcL-1], tmp[`X_trc:frcL]};						
	end
end



always @*
	if (!RST) 
		out <= 0;
	else 		
		out <= {outI [WIO-1:0], outF [WFO-1:0]};
	
endmodule