data/full_repos/permissive/159001439/src/reset_sync.v
1: b'%Warning-WIDTH: data/full_repos/permissive/159001439/src/reset_sync.v:37: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                        : ... In instance reset_sync\n  rst_sync <= {rst_sync,1\'b1};\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/reset_sync.v:47: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                        : ... In instance reset_sync\n  reset <= !rst_sync[SYNC_CYCLES-1:0];\n           ^\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/reset_sync.v:48: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                        : ... In instance reset_sync\n  resetn <= rst_sync[SYNC_CYCLES-1:0];\n         ^~\n%Error: Exiting due to 3 warning(s)\n'
module reset_sync(
	clk,
	rst_in,
	reset,
	resetn
);

parameter SYNC_CYCLES=2;
parameter IN_POLARITY=1;
parameter OUT_POLARITY=1;

(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input	clk;
input	rst_in;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST" *)
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH, ASSOCIATED_CLOCK clk" *)
output	reset;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 resetn RST" *)
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW, ASSOCIATED_CLOCK clk" *)
output	resetn;

reg reset;
reg resetn;

wire rst_a;

(* ASYNC_REG = "TRUE" *)
reg [SYNC_CYCLES-1:0] rst_sync;

assign rst_a = IN_POLARITY ? rst_in : !rst_in;

always @(posedge clk, posedge rst_a)
begin
	if(rst_a)
		rst_sync <= 'b0;
	else
		rst_sync <= {rst_sync,1'b1};
end

always @(posedge clk, posedge rst_a)
begin
	if(rst_a) begin
		reset <= 1'b1;
		resetn <= 1'b0;
	end
	else begin
		reset <= !rst_sync[SYNC_CYCLES-1:0];
		resetn <= rst_sync[SYNC_CYCLES-1:0];
	end
end

endmodule
module reset_sync(
	clk,
	rst_in,
	reset,
	resetn
);


parameter SYNC_CYCLES=2;
parameter IN_POLARITY=1;
parameter OUT_POLARITY=1;

(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input	clk;
input	rst_in;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST" *)
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH, ASSOCIATED_CLOCK clk" *)
output	reset;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 resetn RST" *)
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW, ASSOCIATED_CLOCK clk" *)
output	resetn;

reg reset;
reg resetn;

wire rst_a;

(* ASYNC_REG = "TRUE" *)
reg [SYNC_CYCLES-1:0] rst_sync;

assign rst_a = IN_POLARITY ? rst_in : !rst_in;

always @(posedge clk, posedge rst_a)
begin
	if(rst_a)
		rst_sync <= 'b0;
	else
		rst_sync <= {rst_sync,1'b1};
end

always @(posedge clk, posedge rst_a)
begin
	if(rst_a) begin
		reset <= 1'b1;
		resetn <= 1'b0;
	end
	else begin
		reset <= !rst_sync[SYNC_CYCLES-1:0];
		resetn <= rst_sync[SYNC_CYCLES-1:0];
	end
end

endmodule