data/full_repos/permissive/181665138/verilog/capitolo_iv/Rete_Sequenziale_Asincrona.v
 line:51: before: "."
1: b"%Error: data/full_repos/permissive/181665138/verilog/capitolo_iv/Rete_Sequenziale_Asincrona.v:51: syntax error, unexpected '.', expecting TYPE-IDENTIFIER\n            S0: A = ...\n                    ^\n%Error: data/full_repos/permissive/181665138/verilog/capitolo_iv/Rete_Sequenziale_Asincrona.v:60: syntax error, unexpected '.', expecting TYPE-IDENTIFIER\n            S0: Z = ...\n                    ^\n%Error: Cannot continue\n"
function [10:0] A;
        input [7:0] x7_x0;
        input [3:0] y3_y0;
        casex(y3_y0)
            S0: A = ...
                ...
            S3: A = ...
        endcase
    endfunction
function [10:0] A;

        input [7:0] x7_x0;
        input [3:0] y3_y0;
        casex(y3_y0)
            S0: A = ...
                ...
            S3: A = ...
        endcase
    endfunction