data/full_repos/permissive/174155074/sequential-logic/registers/simple-8-bit-register/simple-8-bit-register.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/0ecc60ac-0dfe-4559-95b6-10536fb6a33d.xml
module simple_8_bit_register (
    input       [7:0]   data_in,
    input               clk,
    input               ld_bar,
    input               clr_bar,
    output  reg [7:0]   data_out
);

always @ (posedge clk) begin
    if (~clr_bar) begin
        data_out <= 0;
    end else if (~ld_bar) begin
        data_out <= data_in;
    end
end

endmodule
module simple_8_bit_register (
    input       [7:0]   data_in,
    input               clk,
    input               ld_bar,
    input               clr_bar,
    output  reg [7:0]   data_out
);


always @ (posedge clk) begin
    if (~clr_bar) begin
        data_out <= 0;
    end else if (~ld_bar) begin
        data_out <= data_in;
    end
end

endmodule