data/full_repos/permissive/17877624/src/hardware/audio_effects.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:30: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                    : ... In instance audio_effects\nreg  [15:0]  index = 15\'d0;      \n                     ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                    : ... In instance audio_effects\nreg  [15:0]  index_who = 15\'d0;\n                         ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:32: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                    : ... In instance audio_effects\nreg  [15:0]  index_bell = 15\'d0;\n                          ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:33: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                    : ... In instance audio_effects\nreg  [15:0]  index_sw = 15\'d0;\n                        ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:34: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                    : ... In instance audio_effects\nreg [15:0] count = 15\'d0;\n                   ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:44: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'index_bell\' generates 16 bits.\n                                                                                    : ... In instance audio_effects\n    addr_bell <= index_bell;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:45: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'index\' generates 16 bits.\n                                                                                    : ... In instance audio_effects\n    addr_city <= index;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:46: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'index_who\' generates 16 bits.\n                                                                                    : ... In instance audio_effects\n    addr_who <= index_who;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:47: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'index_sw\' generates 16 bits.\n                                                                                    : ... In instance audio_effects\n    addr_sw <= index_sw;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:61: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                    : ... In instance audio_effects\n                index_sw <= 15\'d0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:62: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                    : ... In instance audio_effects\n                count <= 15\'d0;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:60: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'15\'h4099\' generates 15 bits.\n                                                                                    : ... In instance audio_effects\n      if (index_sw == 15\'d16537) begin\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:70: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                    : ... In instance audio_effects\n            index_sw <= 15\'b0;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:75: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                                    : ... In instance audio_effects\n            index <= 15\'d0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:74: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'15\'h5621\' generates 15 bits.\n                                                                                    : ... In instance audio_effects\n  if (index == 15\'d22049)\n            ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:44: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'addr_bell\'\n                                                                                        : ... In instance audio_effects\n    addr_bell <= index_bell;\n    ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:45: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'addr_city\'\n                                                                                        : ... In instance audio_effects\n    addr_city <= index;\n    ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:46: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'addr_who\'\n                                                                                        : ... In instance audio_effects\n    addr_who <= index_who;\n    ^~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/17877624/src/hardware/audio_effects.sv:47: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'addr_sw\'\n                                                                                        : ... In instance audio_effects\n    addr_sw <= index_sw;\n    ^~~~~~~\n%Error: Exiting due to 4 error(s), 15 warning(s)\n'
module audio_effects (
    input  clk,
    input  sample_end,
    input  sample_req,
	 input [15:0] audio_sample,
    output [15:0] audio_output,
    input [15:0] M_bell,
    input [15:0] M_city,
    input [15:0] M_who,
    input [15:0] M_sw,
    output [14:0] addr_bell,
    output [14:0] addr_city,
    output [14:0] addr_who,
    output [14:0] addr_sw,
    input  [3:0] control
);


reg  [15:0]  index = 15'd0;
reg  [15:0]  index_who = 15'd0;
reg  [15:0]  index_bell = 15'd0;
reg  [15:0]  index_sw = 15'd0;
reg [15:0] count = 15'd0;


reg [15:0] dat;

assign audio_output = dat;


always @(posedge clk) begin
    
    addr_bell <= index_bell;
    addr_city <= index;
    addr_who <= index_who;
    addr_sw <= index_sw;

end




always @(posedge clk) begin

    if (sample_req) begin
        if (control == 1 || count >= 1) begin
            if (index_sw <= 16537)
                dat <= M_sw;
		    if (index_sw == 15'd16537) begin
                index_sw <= 15'd0;
                count <= 15'd0;
            end
		    else begin
		        index_sw <= index_sw +1'b1;
                count <= count + 1'b1;
            end
        end
        if (control == 0 && count == 0) begin
            index_sw <= 15'b0;
            dat <= M_city;
        end
        
		if (index == 15'd22049)
            index <= 15'd0;
		else
		    index <= index +1'b1;
    
	end
	else
            dat <= 16'd0;
end

endmodule
module audio_effects (
    input  clk,
    input  sample_end,
    input  sample_req,
	 input [15:0] audio_sample,
    output [15:0] audio_output,
    input [15:0] M_bell,
    input [15:0] M_city,
    input [15:0] M_who,
    input [15:0] M_sw,
    output [14:0] addr_bell,
    output [14:0] addr_city,
    output [14:0] addr_who,
    output [14:0] addr_sw,
    input  [3:0] control
);



reg  [15:0]  index = 15'd0;
reg  [15:0]  index_who = 15'd0;
reg  [15:0]  index_bell = 15'd0;
reg  [15:0]  index_sw = 15'd0;
reg [15:0] count = 15'd0;


reg [15:0] dat;

assign audio_output = dat;


always @(posedge clk) begin
    
    addr_bell <= index_bell;
    addr_city <= index;
    addr_who <= index_who;
    addr_sw <= index_sw;

end




always @(posedge clk) begin

    if (sample_req) begin
        if (control == 1 || count >= 1) begin
            if (index_sw <= 16537)
                dat <= M_sw;
		    if (index_sw == 15'd16537) begin
                index_sw <= 15'd0;
                count <= 15'd0;
            end
		    else begin
		        index_sw <= index_sw +1'b1;
                count <= count + 1'b1;
            end
        end
        if (control == 0 && count == 0) begin
            index_sw <= 15'b0;
            dat <= M_city;
        end
        
		if (index == 15'd22049)
            index <= 15'd0;
		else
		    index <= index +1'b1;
    
	end
	else
            dat <= 16'd0;
end

endmodule