data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/PSR.v
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/PSR.v\n%Error: Exiting due to 4 error(s)\n'
module PSR(
    input SetC,
    input SetL,
    input SetF,
    input SetZ,
    input SetN,
    input [4:0] CLFZN,
    output reg [4:0] PState_CLFZN,
    input clk,
    input reset
    );

	always@(posedge clk)
		if (reset) PState_CLFZN  <= 0;
		else begin
			if (SetC)
				PState_CLFZN[4] <= CLFZN[4];
			if (SetL)
				PState_CLFZN[3] <= CLFZN[3];
			if (SetF)
				PState_CLFZN[2] <= CLFZN[2];
			if (SetZ)
				PState_CLFZN[1] <= CLFZN[1];
			if (SetN)
				PState_CLFZN[0] <= CLFZN[0];
		end

endmodule
module PSR(
    input SetC,
    input SetL,
    input SetF,
    input SetZ,
    input SetN,
    input [4:0] CLFZN,
    output reg [4:0] PState_CLFZN,
    input clk,
    input reset
    );


	always@(posedge clk)
		if (reset) PState_CLFZN  <= 0;
		else begin
			if (SetC)
				PState_CLFZN[4] <= CLFZN[4];
			if (SetL)
				PState_CLFZN[3] <= CLFZN[3];
			if (SetF)
				PState_CLFZN[2] <= CLFZN[2];
			if (SetZ)
				PState_CLFZN[1] <= CLFZN[1];
			if (SetN)
				PState_CLFZN[0] <= CLFZN[0];
		end

endmodule