data/full_repos/permissive/202237519/verilog/digitalsystem8/ram_tb.v
 line:12: before: "RD"
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem8/ram_tb.v:1: Cannot find include file: ram.v\n`include "ram.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem8,data/full_repos/permissive/202237519/ram.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem8,data/full_repos/permissive/202237519/ram.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem8,data/full_repos/permissive/202237519/ram.v.sv\n             ram.v\n             ram.v.v\n             ram.v.sv\n             obj_dir/ram.v\n             obj_dir/ram.v.v\n             obj_dir/ram.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem8/ram_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk <= ~clk; \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem8/ram_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("ram_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem8/ram_tb.v:19: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,ram_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem8/ram_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    Data <= 4\'b0011; #1.5;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem8/ram_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    Data <= 4\'b1001; #1.5;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem8/ram_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    Address <= 4\'b1010; #1.5;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem8/ram_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    Address <= 4\'b0111; #1.5;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem8/ram_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    Address <= 4\'b0011; #1.5;\n                        ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n'
module ram_tb;

reg [3:0]Data,Address;
reg WR,RD;
reg clk;
wire [3:0]Out;


ram  ram1(Data, Out, WR, RD, Address, clk);

always begin 
    #1 clk <= ~clk; 
    end

initial begin
    $dumpfile("ram_tb.vcd");
    $dumpvars(0,ram_tb);
    clk <= 1'b0;
    WR <= 1'b1; RD <= 1'b0;
    Address <= 4'b1010;
    Data <= 4'b0011; #1.5;

    WR <= 1'b1; RD <= 1'b0;
    Address <= 4'b0111;
    Data <= 4'b1001; #1.5;

    WR <= 1'b0; RD <= 1'b1;
    Address <= 4'b1010; #1.5;

    WR <= 1'b0; RD <= 1'b1;
    Address <= 4'b0111; #1.5;

    WR <= 1'b0; RD <= 1'b1;
    Address <= 4'b0011; #1.5;
    $finish;
    end

endmodule
module ram_tb;


reg [3:0]Data,Address;
reg WR,RD;
reg clk;
wire [3:0]Out;


ram  ram1(Data, Out, WR, RD, Address, clk);

always begin 
    #1 clk <= ~clk; 
    end

initial begin
    $dumpfile("ram_tb.vcd");
    $dumpvars(0,ram_tb);
    clk <= 1'b0;
    WR <= 1'b1; RD <= 1'b0;
    Address <= 4'b1010;
    Data <= 4'b0011; #1.5;

    WR <= 1'b1; RD <= 1'b0;
    Address <= 4'b0111;
    Data <= 4'b1001; #1.5;

    WR <= 1'b0; RD <= 1'b1;
    Address <= 4'b1010; #1.5;

    WR <= 1'b0; RD <= 1'b1;
    Address <= 4'b0111; #1.5;

    WR <= 1'b0; RD <= 1'b1;
    Address <= 4'b0011; #1.5;
    $finish;
    end

endmodule