data/full_repos/permissive/100597706/testing/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n   always # 5 clk = ~ clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[4] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[4] = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[14] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[14] = 1\'b0;\n    ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module AHBSLAVE_IO (
    input               HSEL,
    input               HCLK,
    input               HRST,
    input               HTRANS,
    input  [31:0]       HWDATA,
    input  [1:0]        HSIZE,
    input               HWRITE,
    input               HREADY,
    
    
    output              HREADYout,
    output  [31:0]      HRDATA,

    output reg [4:0]    strg
);
	 

  reg last_HSEL;
  reg last_HWRITE;
  reg last_HTRANS;

  always@ (posedge HCLK)
  begin
    if(HREADY)
    begin
      last_HSEL     <= HSEL;
      last_HWRITE   <= HWRITE;
      last_HTRANS   <= HTRANS;
    end
  end
    
  always@ (posedge HCLK, posedge HRST)
  begin
    if(HRST)
      strg <= 4'd0;
    else if(last_HSEL & last_HWRITE & last_HTRANS)
      strg <= HWDATA[4:0];
  end


  assign HREADYout = 1'b1;
  assign HRDATA = strg;

endmodule
module AHBSLAVE_IO (
    input               HSEL,
    input               HCLK,
    input               HRST,
    input               HTRANS,
    input  [31:0]       HWDATA,
    input  [1:0]        HSIZE,
    input               HWRITE,
    input               HREADY,
    
    
    output              HREADYout,
    output  [31:0]      HRDATA,

    output reg [4:0]    strg
);

	 

  reg last_HSEL;
  reg last_HWRITE;
  reg last_HTRANS;

  always@ (posedge HCLK)
  begin
    if(HREADY)
    begin
      last_HSEL     <= HSEL;
      last_HWRITE   <= HWRITE;
      last_HTRANS   <= HTRANS;
    end
  end
    
  always@ (posedge HCLK, posedge HRST)
  begin
    if(HRST)
      strg <= 4'd0;
    else if(last_HSEL & last_HWRITE & last_HTRANS)
      strg <= HWDATA[4:0];
  end


  assign HREADYout = 1'b1;
  assign HRDATA = strg;

endmodule