data/full_repos/permissive/110151336/lab_02/src/03_d_latch/d_latch.v
data/verilator_xmls/f155006d-12ca-43ff-af31-5a95192f3c89.xml
module d_latch
(
    input       clk,
    input       d,
    output reg  q
);

    always @ (clk or d)
        if(clk)
            q <= d;

endmodule
module d_latch
(
    input       clk,
    input       d,
    output reg  q
);


    always @ (clk or d)
        if(clk)
            q <= d;

endmodule