data/full_repos/permissive/113002755/verilog/RNG/divider.v
data/verilator_xmls/6994ad65-e7bc-4ab1-95b4-a64a0c039d96.xml
module divider(clk,rst,clk_out);
input clk,rst;

output reg clk_out;

reg [2:0] i;

always @(posedge clk or negedge rst) 
	begin
		if (rst == 1'b0) 
			begin
				i = 0;
				clk_out = 0;
			end
		else 
			begin
				i = i + 1;
				if (i >= 5) 
					begin
						clk_out = ~clk_out;
						i = 0;
					end
			end 
	end

endmodule
module divider(clk,rst,clk_out);

input clk,rst;

output reg clk_out;

reg [2:0] i;

always @(posedge clk or negedge rst) 
	begin
		if (rst == 1'b0) 
			begin
				i = 0;
				clk_out = 0;
			end
		else 
			begin
				i = i + 1;
				if (i >= 5) 
					begin
						clk_out = ~clk_out;
						i = 0;
					end
			end 
	end

endmodule