data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v
 line:434: before: ")"
1: b"%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:434: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:439: syntax error, unexpected input\ninput CLK, RST, EN, WE;\n^~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:450: syntax error, unexpected assign\nassign DO = mem[addr_reg][dw-1:0];\n^~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:522: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:527: syntax error, unexpected input\ninput CLK, RST, EN, WE;\n^~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:538: syntax error, unexpected assign\nassign DO = mem[addr_reg][dw-1:0];\n^~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:566: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:571: syntax error, unexpected input\ninput CLK, RST, EN, WE;\n^~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/bench/verilog/sim_lib/fpga_memory_primitives.v:582: syntax error, unexpected assign\nassign DO = mem[addr_reg][dw-1:0];\n^~~~~~\n%Error: Exiting due to 9 error(s)\n"
module RAM16X1D (
    DPO,
    SPO,
    A0,
    A1,
    A2,
    A3,
    D,
    DPRA0,
    DPRA1,
    DPRA2,
    DPRA3,
    WCLK,
    WE
);

parameter dw = 1;
parameter aw = 4;

output DPO, SPO;
input DPRA0, DPRA1, DPRA2, DPRA3;
input A0, A1, A2, A3;
input D;
input WCLK;
input WE;

reg	[dw-1:0]	mem [(1<<aw)-1:0];




assign DPO = mem[{DPRA3 , DPRA2 , DPRA1 , DPRA0}][dw-1:0];
assign SPO = mem[{A3 , A2 , A1 , A0}][dw-1:0];




always @(posedge WCLK)
	if (WE)
		mem[{A3 , A2 , A1 , A0}] <= #1 D;

endmodule
module RAM16X1D (
    DPO,
    SPO,
    A0,
    A1,
    A2,
    A3,
    D,
    DPRA0,
    DPRA1,
    DPRA2,
    DPRA3,
    WCLK,
    WE
);


parameter dw = 1;
parameter aw = 4;

output DPO, SPO;
input DPRA0, DPRA1, DPRA2, DPRA3;
input A0, A1, A2, A3;
input D;
input WCLK;
input WE;

reg	[dw-1:0]	mem [(1<<aw)-1:0];




assign DPO = mem[{DPRA3 , DPRA2 , DPRA1 , DPRA0}][dw-1:0];
assign SPO = mem[{A3 , A2 , A1 , A0}][dw-1:0];




always @(posedge WCLK)
	if (WE)
		mem[{A3 , A2 , A1 , A0}] <= #1 D;

endmodule