data/full_repos/permissive/130234582/demo_004/test_top.v
 line:35: before: "$"
1: b'%Error: data/full_repos/permissive/130234582/demo_004/test_top.v:27: Cannot find include file: ../src/dumpwave.v\n`include "../src/dumpwave.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/130234582/demo_004,data/full_repos/permissive/130234582/../src/dumpwave.v\n             data/full_repos/permissive/130234582/demo_004,data/full_repos/permissive/130234582/../src/dumpwave.v.v\n             data/full_repos/permissive/130234582/demo_004,data/full_repos/permissive/130234582/../src/dumpwave.v.sv\n             ../src/dumpwave.v\n             ../src/dumpwave.v.v\n             ../src/dumpwave.v.sv\n             obj_dir/../src/dumpwave.v\n             obj_dir/../src/dumpwave.v.v\n             obj_dir/../src/dumpwave.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/130234582/demo_004/test_top.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #1000ns\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/130234582/demo_004/test_top.v:42: syntax error, unexpected \'@\'\n    @(posedge tx_active);\n    ^\n%Error: data/full_repos/permissive/130234582/demo_004/test_top.v:44: Unsupported: wait statements\n    wait(tx_active == 0);\n    ^~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module test_top;

wire clk;
wire rst_n;

reg         enable;
reg [7:0]   tx_data;
wire        tx;
wire        tx_active;

clk_gen #(.PERIOD_PS(1000)) clk_1ns (.clk(clk));
rst_gen #(.RELEASE_PS(30000),.ASSERT_PS(10)) rst_gen (.rst_n(rst_n));

uart_tx dut_tx
(
    .rst_n      (rst_n),
    .clk        (clk),
    .enable     (enable),
    .data       (tx_data[7:0]),
    .clk_ratio  (8'h64),
    .tx_active  (tx_active),
    .tx         (tx)
);

`include "../src/dumpwave.v"
initial begin
    drive_tx(8'h01);
    drive_tx(8'h55);
    drive_tx(8'h99);
    drive_tx(8'hED);
    #1000ns
    $finish;
end

task drive_tx;
input [7:0] data;
begin
    tx_data = data;
    enable = 1;
    @(posedge tx_active);
    enable = 0;
    wait(tx_active == 0);
end
endtask


endmodule
module test_top;


wire clk;
wire rst_n;

reg         enable;
reg [7:0]   tx_data;
wire        tx;
wire        tx_active;

clk_gen #(.PERIOD_PS(1000)) clk_1ns (.clk(clk));
rst_gen #(.RELEASE_PS(30000),.ASSERT_PS(10)) rst_gen (.rst_n(rst_n));

uart_tx dut_tx
(
    .rst_n      (rst_n),
    .clk        (clk),
    .enable     (enable),
    .data       (tx_data[7:0]),
    .clk_ratio  (8'h64),
    .tx_active  (tx_active),
    .tx         (tx)
);

`include "../src/dumpwave.v"
initial begin
    drive_tx(8'h01);
    drive_tx(8'h55);
    drive_tx(8'h99);
    drive_tx(8'hED);
    #1000ns
    $finish;
end

task drive_tx;
input [7:0] data;
begin
    tx_data = data;
    enable = 1;
    @(posedge tx_active);
    enable = 0;
    wait(tx_active == 0);
end
endtask


endmodule