data/full_repos/permissive/143278/ivltests/vhdl_unbounded.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_unbounded.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1;    \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_unbounded.v:28: Can\'t find definition of \'sig_logic\' in dotted variable: \'dut.sig_logic\'\n    if(dut.sig_logic != \'b01010101) begin\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_unbounded.v:33: Can\'t find definition of \'sig_integer\' in dotted variable: \'dut.sig_integer\'\n    if(dut.sig_integer[2] != 1) begin\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_unbounded.v:38: Can\'t find definition of \'sig_real\' in dotted variable: \'dut.sig_real\'\n    if(dut.sig_real[1] != 2.5) begin\n           ^~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vhdl_unbounded_array_test;
  vhdl_unbounded_array dut();

  initial begin
    #1;

    if(dut.sig_logic != 'b01010101) begin
      $display("FAILED 1");
      $finish;
    end

    if(dut.sig_integer[2] != 1) begin
      $display("FAILED 2");
      $finish;
    end

    if(dut.sig_real[1] != 2.5) begin
      $display("FAILED 3");
      $finish;
    end

    $display("PASSED");
  end
endmodule
module vhdl_unbounded_array_test;

  vhdl_unbounded_array dut();

  initial begin
    #1;

    if(dut.sig_logic != 'b01010101) begin
      $display("FAILED 1");
      $finish;
    end

    if(dut.sig_integer[2] != 1) begin
      $display("FAILED 2");
      $finish;
    end

    if(dut.sig_real[1] != 2.5) begin
      $display("FAILED 3");
      $finish;
    end

    $display("PASSED");
  end
endmodule