data/full_repos/permissive/208556773/src/quad_enc.v
data/verilator_xmls/12f3a51c-438c-4b77-920c-bfe69e99fb04.xml
module quad_enc #(
    parameter encbits = 64,
    parameter enable_velocity = 1,
    parameter velocity_bits = 32
  )(
  input wire resetn,
  input wire  clk,
  input wire  a,
  input wire  b,
  output reg faultn,
  output reg signed [encbits-1:0] count,
  output reg signed [velocity_bits-1:0] velocity,
  output reg signed [velocity_bits-1:0] velocity_counter

  );



  reg [2:0] a_stable, b_stable, i_stable;

  wire step_a = a_stable[1] ^ a_stable[2];
  wire step_b = b_stable[1] ^ b_stable[2];
  wire step = step_a ^ step_b;
  wire direction = a_stable[1] ^ b_stable[2];

  always @(posedge clk) begin
    if (!resetn) begin
      count <= 0;
      velocity <= 0;
      velocity_counter <= 0;

      faultn <= 1'b1;
      a_stable <= 3'b0;
      b_stable <= 3'b0;
    end
    else begin
      a_stable <= {a_stable[1:0], a};
      b_stable <= {b_stable[1:0], b};
      velocity_counter <= velocity_counter + 1'b1;

      if (step_a & step_b)
        faultn <= 0;
      if (step) begin
        if (direction) begin
          count <= count + 1'b1;
          velocity <= velocity_counter;
        end
        else begin
          count <= count - 1'b1;
          velocity <= -velocity_counter;
        end
        velocity_counter <= 0;
      end
    end
  end
endmodule
module quad_enc #(
    parameter encbits = 64,
    parameter enable_velocity = 1,
    parameter velocity_bits = 32
  )(
  input wire resetn,
  input wire  clk,
  input wire  a,
  input wire  b,
  output reg faultn,
  output reg signed [encbits-1:0] count,
  output reg signed [velocity_bits-1:0] velocity,
  output reg signed [velocity_bits-1:0] velocity_counter

  );




  reg [2:0] a_stable, b_stable, i_stable;

  wire step_a = a_stable[1] ^ a_stable[2];
  wire step_b = b_stable[1] ^ b_stable[2];
  wire step = step_a ^ step_b;
  wire direction = a_stable[1] ^ b_stable[2];

  always @(posedge clk) begin
    if (!resetn) begin
      count <= 0;
      velocity <= 0;
      velocity_counter <= 0;

      faultn <= 1'b1;
      a_stable <= 3'b0;
      b_stable <= 3'b0;
    end
    else begin
      a_stable <= {a_stable[1:0], a};
      b_stable <= {b_stable[1:0], b};
      velocity_counter <= velocity_counter + 1'b1;

      if (step_a & step_b)
        faultn <= 0;
      if (step) begin
        if (direction) begin
          count <= count + 1'b1;
          velocity <= velocity_counter;
        end
        else begin
          count <= count - 1'b1;
          velocity <= -velocity_counter;
        end
        velocity_counter <= 0;
      end
    end
  end
endmodule