data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v
 line:68: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Error: data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v:51: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("vga_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v:52: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #50000000 $display("Stopping...");\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115920613/tools/iverilog/vga_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #20 clk25 = !clk25;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vga_tb;

    reg clk25, rst, address, w_en, blink_clken;
    reg [7:0] din;
    wire vga_h_sync, vga_v_sync, vga_red, vga_grn, vga_blu;




    initial begin

        clk25 = 1'b0;
        rst = 1'b0;
        address = 1'b0;
        w_en = 1'b0;
        blink_clken = 1'b0;
        din = 8'd0;

        #5
        rst = 1'b1;
        #5
        rst = 1'b0;

        $display("Starting...");
        $dumpfile("vga_tb.vcd");
        $dumpvars;













 

        #50000000 $display("Stopping...");
        $finish;
    end




    always
        #20 clk25 = !clk25;



    vga my_vga (
        .clk25(clk25),
        .enable(1'b1),
        .rst(rst),
        .vga_h_sync(vga_h_sync),
        .vga_v_sync(vga_v_sync),
        .vga_red(vga_red),
        .vga_grn(vga_grn),
        .vga_blu(vga_blu),
        .address(address),
        .w_en(w_en),
        .din(din)
    );

endmodule
module vga_tb;


    reg clk25, rst, address, w_en, blink_clken;
    reg [7:0] din;
    wire vga_h_sync, vga_v_sync, vga_red, vga_grn, vga_blu;




    initial begin

        clk25 = 1'b0;
        rst = 1'b0;
        address = 1'b0;
        w_en = 1'b0;
        blink_clken = 1'b0;
        din = 8'd0;

        #5
        rst = 1'b1;
        #5
        rst = 1'b0;

        $display("Starting...");
        $dumpfile("vga_tb.vcd");
        $dumpvars;













 

        #50000000 $display("Stopping...");
        $finish;
    end




    always
        #20 clk25 = !clk25;



    vga my_vga (
        .clk25(clk25),
        .enable(1'b1),
        .rst(rst),
        .vga_h_sync(vga_h_sync),
        .vga_v_sync(vga_v_sync),
        .vga_red(vga_red),
        .vga_grn(vga_grn),
        .vga_blu(vga_blu),
        .address(address),
        .w_en(w_en),
        .din(din)
    );

endmodule