data/full_repos/permissive/114811571/test/samples/sram/sram_512w_16b.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/114811571/test/samples/sram/sram_512w_16b.v:39: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q'\n                                                                                             : ... In instance sram_512w_16b\n            Q = data_array[A];\n            ^\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module sram_512w_16b (Q, CLK, CEN, WEN, A, D, EMA, EMAW, EMAS, TEN, BEN, RET1N, STOV);
   output [15:0] Q;
   input        CLK;
   input        CEN;
   input        WEN;
   input [8:0]  A;
   input [15:0] D;
   
   input [2:0]  EMA;
   input [1:0]  EMAW;
   input        EMAS;
   input        TEN;
   input        BEN;
   input        RET1N;
   input        STOV;
   
   reg [15:0]   data_array [0:511];

   always @(posedge CLK) begin


      if (| {EMA, EMAW, EMAS, TEN, BEN, RET1N, STOV}) begin
         if (CEN == 1'b0) begin
            Q = data_array[A];
            if (WEN == 1'b0) data_array[A] = D;
         end
      end
   end
endmodule
module sram_512w_16b (Q, CLK, CEN, WEN, A, D, EMA, EMAW, EMAS, TEN, BEN, RET1N, STOV);

   output [15:0] Q;
   input        CLK;
   input        CEN;
   input        WEN;
   input [8:0]  A;
   input [15:0] D;
   
   input [2:0]  EMA;
   input [1:0]  EMAW;
   input        EMAS;
   input        TEN;
   input        BEN;
   input        RET1N;
   input        STOV;
   
   reg [15:0]   data_array [0:511];

   always @(posedge CLK) begin


      if (| {EMA, EMAW, EMAS, TEN, BEN, RET1N, STOV}) begin
         if (CEN == 1'b0) begin
            Q = data_array[A];
            if (WEN == 1'b0) data_array[A] = D;
         end
      end
   end
endmodule