data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #5 clock <= ~clock;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #10 write_enable <= 1\'b1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10 chip_select <= 1\'b1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'h018; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #10 write_enable <= 1\'b0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'h019;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #10 output_enable <= 1\'b1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'h018;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'h0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10 chip_select <= 1\'b0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #10 chip_select <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10 write_enable <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #10 address <= 12\'h101;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #10 $stop;\n  ^\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:22: Can\'t find definition of \'mem\' in dotted variable: \'dut.mem\'\n  assign mem0 = dut.mem[0];\n                    ^~~\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:23: Can\'t find definition of \'mem\' in dotted variable: \'dut.mem\'\n  assign mem24 = dut.mem[24];\n                     ^~~\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:24: Can\'t find definition of \'mem\' in dotted variable: \'dut.mem\'\n  assign mem25 = dut.mem[25];\n                     ^~~\n%Error: data/full_repos/permissive/167489907/Memory/RAM/RAM_testbench.v:25: Can\'t find definition of \'mem\' in dotted variable: \'dut.mem\'\n  assign mem257 = dut.mem[257];\n                      ^~~\n%Error: Exiting due to 4 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram_sp_sr_sw_testbench();
	reg clock, chip_select, write_enable, output_enable;
	tri [63:0] data;
	reg [63:0] data_in;
	reg [11:0] address;
	
	assign data = chip_select & write_enable ? data_in : 64'bz;
	
	wire [63:0] mem0, mem24, mem25, mem257;

	ram_sp_sr_sw dut (
	 .clk(clock)        ,
	 .address(address)  ,
	 .data(data)        ,
	 .cs(chip_select)   ,
	 .we(write_enable)  ,
	 .oe(output_enable)
	 );
	defparam dut.DATA_WIDTH = 64;
	defparam dut.ADDR_WIDTH = 12;
	 
	 assign mem0 = dut.mem[0];
	 assign mem24 = dut.mem[24];
	 assign mem25 = dut.mem[25];
	 assign mem257 = dut.mem[257];
	 
	 initial begin
		clock <= 1'b0;
		chip_select <= 1'b0;
		write_enable <= 1'b0;
		output_enable <= 1'b0;
		address <= 12'h0;
		data_in <= 64'hA5;
	end
	
	always
		#5 clock <= ~clock;
		
	always begin
		#10 write_enable <= 1'b1;
		#10 chip_select <= 1'b1;
		#10 address <= 12'h018; 
		data_in <= 64'h1234;
		#10 write_enable <= 1'b0;
		#10 address <= 12'h019;
		#10 output_enable <= 1'b1;
		#10 address <= 12'h018;
		#10 address <= 12'h0;
		#10 chip_select <= 1'b0;
		#10 chip_select <= 1'b1;
		write_enable <= 1'b1;
		data_in <= 64'h123456789AB;
		address <= 12'h101;
		#10 write_enable <= 1'b0;
		output_enable <= 1'b1;
		address <= 12'h0;
		#10 address <= 12'h101;
		#10 $stop;
	end
	
endmodule
module ram_sp_sr_sw_testbench();

	reg clock, chip_select, write_enable, output_enable;
	tri [63:0] data;
	reg [63:0] data_in;
	reg [11:0] address;
	
	assign data = chip_select & write_enable ? data_in : 64'bz;
	
	wire [63:0] mem0, mem24, mem25, mem257;

	ram_sp_sr_sw dut (
	 .clk(clock)        ,
	 .address(address)  ,
	 .data(data)        ,
	 .cs(chip_select)   ,
	 .we(write_enable)  ,
	 .oe(output_enable)
	 );
	defparam dut.DATA_WIDTH = 64;
	defparam dut.ADDR_WIDTH = 12;
	 
	 assign mem0 = dut.mem[0];
	 assign mem24 = dut.mem[24];
	 assign mem25 = dut.mem[25];
	 assign mem257 = dut.mem[257];
	 
	 initial begin
		clock <= 1'b0;
		chip_select <= 1'b0;
		write_enable <= 1'b0;
		output_enable <= 1'b0;
		address <= 12'h0;
		data_in <= 64'hA5;
	end
	
	always
		#5 clock <= ~clock;
		
	always begin
		#10 write_enable <= 1'b1;
		#10 chip_select <= 1'b1;
		#10 address <= 12'h018; 
		data_in <= 64'h1234;
		#10 write_enable <= 1'b0;
		#10 address <= 12'h019;
		#10 output_enable <= 1'b1;
		#10 address <= 12'h018;
		#10 address <= 12'h0;
		#10 chip_select <= 1'b0;
		#10 chip_select <= 1'b1;
		write_enable <= 1'b1;
		data_in <= 64'h123456789AB;
		address <= 12'h101;
		#10 write_enable <= 1'b0;
		output_enable <= 1'b1;
		address <= 12'h0;
		#10 address <= 12'h101;
		#10 $stop;
	end
	
endmodule