data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v
1: b'%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:57: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v.v\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:59: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:80: Define or directive not defined: \'`OR1200_OPERAND_WIDTH\'\n   parameter dw = `OR1200_OPERAND_WIDTH;\n                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter dw = `OR1200_OPERAND_WIDTH;\n                                       ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:81: Define or directive not defined: \'`OR1200_OPERAND_WIDTH\'\n   parameter aw = `OR1200_OPERAND_WIDTH;\n                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter aw = `OR1200_OPERAND_WIDTH;\n                                       ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:191: Define or directive not defined: \'`OR1200_RST_EVENT\'\n   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin\n                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:192: Define or directive not defined: \'`OR1200_RST_VALUE\'\n      if (wb_rst_i == `OR1200_RST_VALUE) \n                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:192: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (wb_rst_i == `OR1200_RST_VALUE) \n                                       ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:201: Define or directive not defined: \'`OR1200_RST_EVENT\'\n   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin\n                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:202: Define or directive not defined: \'`OR1200_RST_VALUE\'\n      if (wb_rst_i == `OR1200_RST_VALUE) begin\n                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:202: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (wb_rst_i == `OR1200_RST_VALUE) begin\n                                       ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:228: syntax error, unexpected \'=\', expecting IDENTIFIER\n      wb_fsm_state_nxt = wb_fsm_trans;\n                       ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:230: syntax error, unexpected \'=\', expecting IDENTIFIER\n      wb_fsm_state_nxt = wb_fsm_idle;\n                       ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:245: syntax error, unexpected \'=\', expecting IDENTIFIER\n      wb_fsm_state_nxt = wb_fsm_last;\n                       ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:248: syntax error, unexpected \'=\', expecting IDENTIFIER\n      wb_fsm_state_nxt = wb_fsm_idle;\n                       ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:250: syntax error, unexpected \'=\', expecting IDENTIFIER\n      wb_fsm_state_nxt = wb_fsm_trans;\n                       ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:262: syntax error, unexpected \'=\', expecting IDENTIFIER\n      wb_fsm_state_nxt = wb_fsm_idle;\n                       ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:264: syntax error, unexpected \'=\', expecting IDENTIFIER\n      wb_fsm_state_nxt = wb_fsm_last;\n                       ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:279: Define or directive not defined: \'`OR1200_RST_EVENT\'\n   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin\n                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:280: Define or directive not defined: \'`OR1200_RST_VALUE\'\n      if (wb_rst_i == `OR1200_RST_VALUE) begin\n                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:299: syntax error, unexpected <=, expecting IDENTIFIER\n           wb_stb_o        <=  1\'b0;\n                           ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:301: syntax error, unexpected <=, expecting IDENTIFIER\n           wb_stb_o        <=  wb_stb_nxt;\n                           ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:311: syntax error, unexpected <=, expecting IDENTIFIER\n     wb_we_o  <=  biu_we_i;\n              ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:316: syntax error, unexpected <=, expecting IDENTIFIER\n     wb_adr_o <=  biu_adr_i;\n              ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:320: syntax error, unexpected \'[\', expecting IDENTIFIER\n        wb_adr_o[3:2] <=  wb_adr_o[3:2] + 1;\n                ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:323: syntax error, unexpected \'[\', expecting IDENTIFIER\n        wb_adr_o[4:2] <=  wb_adr_o[4:2] + 1;\n                ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:332: syntax error, unexpected end\n      end\n      ^~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:338: Define or directive not defined: \'`OR1200_RST_EVENT\'\n   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin\n                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:339: Define or directive not defined: \'`OR1200_RST_VALUE\'\n      if (wb_rst_i == `OR1200_RST_VALUE) begin\n                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:352: syntax error, unexpected <=, expecting IDENTIFIER\n    wb_err_cnt <=  1\'b0;\n               ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:354: syntax error, unexpected <=, expecting IDENTIFIER\n    wb_err_cnt <=  !wb_err_cnt;\n               ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:357: syntax error, unexpected <=, expecting IDENTIFIER\n    wb_rty_cnt <=  1\'b0;\n               ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:359: syntax error, unexpected <=, expecting IDENTIFIER\n    wb_rty_cnt <=  !wb_rty_cnt;\n               ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:363: Define or directive not defined: \'`OR1200_RST_EVENT\'\n   always @(posedge clk or `OR1200_RST_EVENT rst) begin\n                           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:364: Define or directive not defined: \'`OR1200_RST_VALUE\'\n      if (rst == `OR1200_RST_VALUE) begin\n                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:381: syntax error, unexpected <=, expecting IDENTIFIER\n    biu_ack_cnt <=  1\'b0 ;\n                ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:383: syntax error, unexpected <=, expecting IDENTIFIER\n    biu_ack_cnt <=  !biu_ack_cnt ;\n                ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:386: syntax error, unexpected <=, expecting IDENTIFIER\n    biu_err_cnt <=  1\'b0 ;\n                ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:388: syntax error, unexpected <=, expecting IDENTIFIER\n    biu_err_cnt <=  !biu_err_cnt ;\n                ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:391: syntax error, unexpected <=, expecting IDENTIFIER\n    biu_rty_cnt <=  1\'b0 ;\n                ^~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_wb_biu.v:393: syntax error, unexpected <=, expecting IDENTIFIER\n    biu_rty_cnt <=  !biu_rty_cnt ;\n                ^~\n%Error: Exiting due to 42 error(s)\n'
module or1200_wb_biu(

		     clk, rst, clmode,


		     wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
		     wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
`ifdef OR1200_WB_CAB
		     wb_cab_o,
`endif
`ifdef OR1200_WB_B3
		     wb_cti_o, wb_bte_o,
`endif


		     biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
		     biu_dat_o, biu_ack_o, biu_err_o
		     );

   parameter dw = `OR1200_OPERAND_WIDTH;
   parameter aw = `OR1200_OPERAND_WIDTH;
   parameter bl = 4;
		      
   



   input				clk;
   input				rst;
   input [1:0] 				clmode;




   input				wb_clk_i;
   input				wb_rst_i;
   input				wb_ack_i;
   input				wb_err_i;
   input				wb_rty_i;
   input [dw-1:0] 			wb_dat_i;
   output				wb_cyc_o;
   output [aw-1:0] 			wb_adr_o;
   output				wb_stb_o;
   output				wb_we_o;
   output [3:0] 			wb_sel_o;
   output [dw-1:0] 			wb_dat_o;
`ifdef OR1200_WB_CAB
   output				wb_cab_o;
`endif
`ifdef OR1200_WB_B3
   output [2:0] 			wb_cti_o;
   output [1:0] 			wb_bte_o;
`endif




   input [dw-1:0] 			biu_dat_i;
   input [aw-1:0] 			biu_adr_i;
   input				biu_cyc_i;
   input				biu_stb_i;
   input				biu_we_i;
   input				biu_cab_i;
   input [3:0] 				biu_sel_i;
   output [31:0] 			biu_dat_o;
   output				biu_ack_o;
   output				biu_err_o;




   wire 				wb_ack;
   reg [aw-1:0] 			wb_adr_o;
   reg 					wb_cyc_o;
   reg 					wb_stb_o;
   reg 					wb_we_o;
   reg [3:0] 				wb_sel_o;
`ifdef OR1200_WB_CAB
   reg 					wb_cab_o;
`endif
`ifdef OR1200_WB_B3
   reg [2:0] 				wb_cti_o;
   reg [1:0] 				wb_bte_o;
`endif
`ifdef OR1200_NO_DC   
   reg [dw-1:0] 			wb_dat_o;
`else   
   assign wb_dat_o = biu_dat_i;
`endif
   
`ifdef OR1200_WB_RETRY
   reg [`OR1200_WB_RETRY-1:0] 		retry_cnt;
`else
   wire 				retry_cnt;
   assign retry_cnt = 1'b0;
`endif
`ifdef OR1200_WB_B3
   reg [3:0] 				burst_len;
`endif

   reg  				biu_stb_reg;
   wire  				biu_stb;
   reg 					wb_cyc_nxt;
   reg 					wb_stb_nxt;
   reg [2:0] 				wb_cti_nxt;

   reg 					wb_ack_cnt;
   reg 					wb_err_cnt;
   reg 					wb_rty_cnt;
   reg 					biu_ack_cnt;
   reg 					biu_err_cnt;
   reg 					biu_rty_cnt;
   wire 				biu_rty;

   reg [1:0] 				wb_fsm_state_cur;
   reg [1:0] 				wb_fsm_state_nxt;
   wire [1:0] 				wb_fsm_idle	= 2'h0;
   wire [1:0] 				wb_fsm_trans	= 2'h1;
   wire [1:0] 				wb_fsm_last	= 2'h2;





   assign wb_ack = wb_ack_i & !wb_err_i & !wb_rty_i;




   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
      if (wb_rst_i == `OR1200_RST_VALUE) 
	wb_fsm_state_cur <=  wb_fsm_idle;
      else 
	wb_fsm_state_cur <=  wb_fsm_state_nxt;
   end




   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
      if (wb_rst_i == `OR1200_RST_VALUE) begin
	 burst_len <= 0;
      end
      else begin

	 if (wb_fsm_state_cur == wb_fsm_idle)
	   burst_len <=  bl[3:0] - 2;
	 else if (wb_stb_o & wb_ack)
	   burst_len <=  burst_len - 1;
      end
   end




   always @(wb_fsm_state_cur or burst_len or wb_err_i or wb_rty_i or wb_ack or 
	    wb_cti_o or wb_sel_o or wb_stb_o or wb_we_o or biu_cyc_i or 
	    biu_stb or biu_cab_i or biu_sel_i or biu_we_i) begin

      case(wb_fsm_state_cur)

	wb_fsm_idle : begin
	   wb_cyc_nxt = biu_cyc_i & biu_stb;
	   wb_stb_nxt = biu_cyc_i & biu_stb;
	   wb_cti_nxt = {!biu_cab_i, 1'b1, !biu_cab_i};
	   if (biu_cyc_i & biu_stb)
	     wb_fsm_state_nxt = wb_fsm_trans;
	   else
	     wb_fsm_state_nxt = wb_fsm_idle;
	end

	wb_fsm_trans : begin
	   wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & 
			!(wb_ack & wb_cti_o == 3'b111);
	   
	   wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack | 
			!wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 ;
	   wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
	   wb_cti_nxt[1] = 1'b1  ;
	   wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];

	   if ((!biu_cyc_i | !biu_stb | !biu_cab_i | biu_sel_i != wb_sel_o | 
		biu_we_i != wb_we_o) & wb_cti_o == 3'b010)
	     wb_fsm_state_nxt = wb_fsm_last;
	   else if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o==3'b111) & 
		    wb_stb_o)
	     wb_fsm_state_nxt = wb_fsm_idle;
	   else
	     wb_fsm_state_nxt = wb_fsm_trans;
	end

	wb_fsm_last : begin
	   wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & 
			!(wb_ack & wb_cti_o == 3'b111);
	   wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & 
			!(wb_ack & wb_cti_o == 3'b111);
	   wb_cti_nxt[2] = wb_ack & wb_stb_o | wb_cti_o[2];
	   wb_cti_nxt[1] = 1'b1                  ;
	   wb_cti_nxt[0] = wb_ack & wb_stb_o | wb_cti_o[0];
	   if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o == 3'b111) & wb_stb_o)
	     wb_fsm_state_nxt = wb_fsm_idle;
	   else
	     wb_fsm_state_nxt = wb_fsm_last;
	end

	default:begin
	   wb_cyc_nxt = 1'bx;
	   wb_stb_nxt = 1'bx;
	   wb_cti_nxt = 3'bxxx;
	   wb_fsm_state_nxt = 2'bxx;
	end
      endcase
   end




   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
      if (wb_rst_i == `OR1200_RST_VALUE) begin
	 wb_cyc_o	<=  1'b0;
	 wb_stb_o	<=  1'b0;
	 wb_cti_o	<=  3'b111;
	 wb_bte_o	<=  (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
`ifdef OR1200_WB_CAB
	 wb_cab_o	<=  1'b0;
`endif
	 wb_we_o		<=  1'b0;
	 wb_sel_o	<=  4'hf;
	 wb_adr_o	<=  {aw{1'b0}};
`ifdef OR1200_NO_DC	 
	 wb_dat_o	<=  {dw{1'b0}};
`endif	 
      end
      else begin
	 wb_cyc_o	<=  wb_cyc_nxt;

         if (wb_ack & wb_cti_o == 3'b111) 
           wb_stb_o        <=  1'b0;
         else
           wb_stb_o        <=  wb_stb_nxt;
`ifndef OR1200_NO_BURSTS
	 wb_cti_o	<=  wb_cti_nxt;
`endif	 
	 wb_bte_o	<=  (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
`ifdef OR1200_WB_CAB
	 wb_cab_o	<=  biu_cab_i;
`endif

	 if (wb_fsm_state_cur == wb_fsm_idle) begin
	    wb_we_o		<=  biu_we_i;
	    wb_sel_o	<=  biu_sel_i;
	 end

	 if (wb_fsm_state_cur == wb_fsm_idle) begin
	    wb_adr_o	<=  biu_adr_i;
	 end 
	 else if (wb_stb_o & wb_ack) begin
	    if (bl==4) begin
	       wb_adr_o[3:2]	<=  wb_adr_o[3:2] + 1;
	    end
	    if (bl==8) begin
	       wb_adr_o[4:2]	<=  wb_adr_o[4:2] + 1;
	    end
	 end
`ifdef OR1200_NO_DC	 

	 if (!wb_stb_o) begin
	    wb_dat_o 	<=  biu_dat_i;
	 end
`endif	 
      end
   end




   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
      if (wb_rst_i == `OR1200_RST_VALUE) begin
	 wb_ack_cnt	<=  1'b0;
	 wb_err_cnt	<=  1'b0;
	 wb_rty_cnt	<=  1'b0;
      end
      else begin

	 if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
	   wb_ack_cnt	<=  1'b0;
	 else if (wb_stb_o & wb_ack)
	   wb_ack_cnt	<=  !wb_ack_cnt;

	 if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
	   wb_err_cnt	<=  1'b0;
	 else if (wb_stb_o & wb_err_i)
	   wb_err_cnt	<=  !wb_err_cnt;

	 if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
	   wb_rty_cnt	<=  1'b0;
	 else if (wb_stb_o & wb_rty_i)
	   wb_rty_cnt	<=  !wb_rty_cnt;
      end
   end

   always @(posedge clk or `OR1200_RST_EVENT rst) begin
      if (rst == `OR1200_RST_VALUE) begin
         biu_stb_reg	<=  1'b0;
	 biu_ack_cnt	<=  1'b0;
	 biu_err_cnt	<=  1'b0;
	 biu_rty_cnt	<=  1'b0;
`ifdef OR1200_WB_RETRY
	 retry_cnt	<= {`OR1200_WB_RETRY{1'b0}};
`endif
      end
      else begin

	 if (biu_stb_i & !biu_cab_i & biu_ack_o)
	   biu_stb_reg	<=  1'b0;
	 else
	   biu_stb_reg	<=  biu_stb_i;

	 if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
	   biu_ack_cnt	<=  1'b0 ;
	 else if (biu_ack_o)
	   biu_ack_cnt	<=  !biu_ack_cnt ;

	 if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
	   biu_err_cnt	<=  1'b0 ;
	 else if (wb_err_i & biu_err_o)
	   biu_err_cnt	<=  !biu_err_cnt ;

	 if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
	   biu_rty_cnt	<=  1'b0 ;
	 else if (biu_rty)
	   biu_rty_cnt	<=  !biu_rty_cnt ;
`ifdef OR1200_WB_RETRY
	 if (biu_ack_o | biu_err_o)
	   retry_cnt	<=  {`OR1200_WB_RETRY{1'b0}};
	 else if (biu_rty)
	   retry_cnt	<=  retry_cnt + 1'b1;
`endif
      end
   end

   assign biu_stb = biu_stb_i & biu_stb_reg;




   assign	biu_dat_o	= wb_dat_i;




   assign	biu_rty		= (wb_fsm_state_cur == wb_fsm_trans) & wb_rty_i & wb_stb_o & (wb_rty_cnt ~^ biu_rty_cnt);
   assign	biu_ack_o	= (wb_fsm_state_cur == wb_fsm_trans) & wb_ack & wb_stb_o & (wb_ack_cnt ~^ biu_ack_cnt);
   assign	biu_err_o	= (wb_fsm_state_cur == wb_fsm_trans) & wb_err_i & wb_stb_o & (wb_err_cnt ~^ biu_err_cnt)
`ifdef OR1200_WB_RETRY
     | biu_rty & retry_cnt[`OR1200_WB_RETRY-1];
`else
   ;
`endif


endmodule
module or1200_wb_biu(

		     clk, rst, clmode,


		     wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
		     wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
`ifdef OR1200_WB_CAB
		     wb_cab_o,
`endif
`ifdef OR1200_WB_B3
		     wb_cti_o, wb_bte_o,
`endif


		     biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
		     biu_dat_o, biu_ack_o, biu_err_o
		     );


   parameter dw = `OR1200_OPERAND_WIDTH;
   parameter aw = `OR1200_OPERAND_WIDTH;
   parameter bl = 4;
		      
   



   input				clk;
   input				rst;
   input [1:0] 				clmode;




   input				wb_clk_i;
   input				wb_rst_i;
   input				wb_ack_i;
   input				wb_err_i;
   input				wb_rty_i;
   input [dw-1:0] 			wb_dat_i;
   output				wb_cyc_o;
   output [aw-1:0] 			wb_adr_o;
   output				wb_stb_o;
   output				wb_we_o;
   output [3:0] 			wb_sel_o;
   output [dw-1:0] 			wb_dat_o;
`ifdef OR1200_WB_CAB
   output				wb_cab_o;
`endif
`ifdef OR1200_WB_B3
   output [2:0] 			wb_cti_o;
   output [1:0] 			wb_bte_o;
`endif




   input [dw-1:0] 			biu_dat_i;
   input [aw-1:0] 			biu_adr_i;
   input				biu_cyc_i;
   input				biu_stb_i;
   input				biu_we_i;
   input				biu_cab_i;
   input [3:0] 				biu_sel_i;
   output [31:0] 			biu_dat_o;
   output				biu_ack_o;
   output				biu_err_o;




   wire 				wb_ack;
   reg [aw-1:0] 			wb_adr_o;
   reg 					wb_cyc_o;
   reg 					wb_stb_o;
   reg 					wb_we_o;
   reg [3:0] 				wb_sel_o;
`ifdef OR1200_WB_CAB
   reg 					wb_cab_o;
`endif
`ifdef OR1200_WB_B3
   reg [2:0] 				wb_cti_o;
   reg [1:0] 				wb_bte_o;
`endif
`ifdef OR1200_NO_DC   
   reg [dw-1:0] 			wb_dat_o;
`else   
   assign wb_dat_o = biu_dat_i;
`endif
   
`ifdef OR1200_WB_RETRY
   reg [`OR1200_WB_RETRY-1:0] 		retry_cnt;
`else
   wire 				retry_cnt;
   assign retry_cnt = 1'b0;
`endif
`ifdef OR1200_WB_B3
   reg [3:0] 				burst_len;
`endif

   reg  				biu_stb_reg;
   wire  				biu_stb;
   reg 					wb_cyc_nxt;
   reg 					wb_stb_nxt;
   reg [2:0] 				wb_cti_nxt;

   reg 					wb_ack_cnt;
   reg 					wb_err_cnt;
   reg 					wb_rty_cnt;
   reg 					biu_ack_cnt;
   reg 					biu_err_cnt;
   reg 					biu_rty_cnt;
   wire 				biu_rty;

   reg [1:0] 				wb_fsm_state_cur;
   reg [1:0] 				wb_fsm_state_nxt;
   wire [1:0] 				wb_fsm_idle	= 2'h0;
   wire [1:0] 				wb_fsm_trans	= 2'h1;
   wire [1:0] 				wb_fsm_last	= 2'h2;





   assign wb_ack = wb_ack_i & !wb_err_i & !wb_rty_i;




   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
      if (wb_rst_i == `OR1200_RST_VALUE) 
	wb_fsm_state_cur <=  wb_fsm_idle;
      else 
	wb_fsm_state_cur <=  wb_fsm_state_nxt;
   end




   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
      if (wb_rst_i == `OR1200_RST_VALUE) begin
	 burst_len <= 0;
      end
      else begin

	 if (wb_fsm_state_cur == wb_fsm_idle)
	   burst_len <=  bl[3:0] - 2;
	 else if (wb_stb_o & wb_ack)
	   burst_len <=  burst_len - 1;
      end
   end




   always @(wb_fsm_state_cur or burst_len or wb_err_i or wb_rty_i or wb_ack or 
	    wb_cti_o or wb_sel_o or wb_stb_o or wb_we_o or biu_cyc_i or 
	    biu_stb or biu_cab_i or biu_sel_i or biu_we_i) begin

      case(wb_fsm_state_cur)

	wb_fsm_idle : begin
	   wb_cyc_nxt = biu_cyc_i & biu_stb;
	   wb_stb_nxt = biu_cyc_i & biu_stb;
	   wb_cti_nxt = {!biu_cab_i, 1'b1, !biu_cab_i};
	   if (biu_cyc_i & biu_stb)
	     wb_fsm_state_nxt = wb_fsm_trans;
	   else
	     wb_fsm_state_nxt = wb_fsm_idle;
	end

	wb_fsm_trans : begin
	   wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & 
			!(wb_ack & wb_cti_o == 3'b111);
	   
	   wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack | 
			!wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 ;
	   wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
	   wb_cti_nxt[1] = 1'b1  ;
	   wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];

	   if ((!biu_cyc_i | !biu_stb | !biu_cab_i | biu_sel_i != wb_sel_o | 
		biu_we_i != wb_we_o) & wb_cti_o == 3'b010)
	     wb_fsm_state_nxt = wb_fsm_last;
	   else if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o==3'b111) & 
		    wb_stb_o)
	     wb_fsm_state_nxt = wb_fsm_idle;
	   else
	     wb_fsm_state_nxt = wb_fsm_trans;
	end

	wb_fsm_last : begin
	   wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & 
			!(wb_ack & wb_cti_o == 3'b111);
	   wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & 
			!(wb_ack & wb_cti_o == 3'b111);
	   wb_cti_nxt[2] = wb_ack & wb_stb_o | wb_cti_o[2];
	   wb_cti_nxt[1] = 1'b1                  ;
	   wb_cti_nxt[0] = wb_ack & wb_stb_o | wb_cti_o[0];
	   if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o == 3'b111) & wb_stb_o)
	     wb_fsm_state_nxt = wb_fsm_idle;
	   else
	     wb_fsm_state_nxt = wb_fsm_last;
	end

	default:begin
	   wb_cyc_nxt = 1'bx;
	   wb_stb_nxt = 1'bx;
	   wb_cti_nxt = 3'bxxx;
	   wb_fsm_state_nxt = 2'bxx;
	end
      endcase
   end




   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
      if (wb_rst_i == `OR1200_RST_VALUE) begin
	 wb_cyc_o	<=  1'b0;
	 wb_stb_o	<=  1'b0;
	 wb_cti_o	<=  3'b111;
	 wb_bte_o	<=  (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
`ifdef OR1200_WB_CAB
	 wb_cab_o	<=  1'b0;
`endif
	 wb_we_o		<=  1'b0;
	 wb_sel_o	<=  4'hf;
	 wb_adr_o	<=  {aw{1'b0}};
`ifdef OR1200_NO_DC	 
	 wb_dat_o	<=  {dw{1'b0}};
`endif	 
      end
      else begin
	 wb_cyc_o	<=  wb_cyc_nxt;

         if (wb_ack & wb_cti_o == 3'b111) 
           wb_stb_o        <=  1'b0;
         else
           wb_stb_o        <=  wb_stb_nxt;
`ifndef OR1200_NO_BURSTS
	 wb_cti_o	<=  wb_cti_nxt;
`endif	 
	 wb_bte_o	<=  (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
`ifdef OR1200_WB_CAB
	 wb_cab_o	<=  biu_cab_i;
`endif

	 if (wb_fsm_state_cur == wb_fsm_idle) begin
	    wb_we_o		<=  biu_we_i;
	    wb_sel_o	<=  biu_sel_i;
	 end

	 if (wb_fsm_state_cur == wb_fsm_idle) begin
	    wb_adr_o	<=  biu_adr_i;
	 end 
	 else if (wb_stb_o & wb_ack) begin
	    if (bl==4) begin
	       wb_adr_o[3:2]	<=  wb_adr_o[3:2] + 1;
	    end
	    if (bl==8) begin
	       wb_adr_o[4:2]	<=  wb_adr_o[4:2] + 1;
	    end
	 end
`ifdef OR1200_NO_DC	 

	 if (!wb_stb_o) begin
	    wb_dat_o 	<=  biu_dat_i;
	 end
`endif	 
      end
   end




   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
      if (wb_rst_i == `OR1200_RST_VALUE) begin
	 wb_ack_cnt	<=  1'b0;
	 wb_err_cnt	<=  1'b0;
	 wb_rty_cnt	<=  1'b0;
      end
      else begin

	 if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
	   wb_ack_cnt	<=  1'b0;
	 else if (wb_stb_o & wb_ack)
	   wb_ack_cnt	<=  !wb_ack_cnt;

	 if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
	   wb_err_cnt	<=  1'b0;
	 else if (wb_stb_o & wb_err_i)
	   wb_err_cnt	<=  !wb_err_cnt;

	 if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
	   wb_rty_cnt	<=  1'b0;
	 else if (wb_stb_o & wb_rty_i)
	   wb_rty_cnt	<=  !wb_rty_cnt;
      end
   end

   always @(posedge clk or `OR1200_RST_EVENT rst) begin
      if (rst == `OR1200_RST_VALUE) begin
         biu_stb_reg	<=  1'b0;
	 biu_ack_cnt	<=  1'b0;
	 biu_err_cnt	<=  1'b0;
	 biu_rty_cnt	<=  1'b0;
`ifdef OR1200_WB_RETRY
	 retry_cnt	<= {`OR1200_WB_RETRY{1'b0}};
`endif
      end
      else begin

	 if (biu_stb_i & !biu_cab_i & biu_ack_o)
	   biu_stb_reg	<=  1'b0;
	 else
	   biu_stb_reg	<=  biu_stb_i;

	 if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
	   biu_ack_cnt	<=  1'b0 ;
	 else if (biu_ack_o)
	   biu_ack_cnt	<=  !biu_ack_cnt ;

	 if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
	   biu_err_cnt	<=  1'b0 ;
	 else if (wb_err_i & biu_err_o)
	   biu_err_cnt	<=  !biu_err_cnt ;

	 if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
	   biu_rty_cnt	<=  1'b0 ;
	 else if (biu_rty)
	   biu_rty_cnt	<=  !biu_rty_cnt ;
`ifdef OR1200_WB_RETRY
	 if (biu_ack_o | biu_err_o)
	   retry_cnt	<=  {`OR1200_WB_RETRY{1'b0}};
	 else if (biu_rty)
	   retry_cnt	<=  retry_cnt + 1'b1;
`endif
      end
   end

   assign biu_stb = biu_stb_i & biu_stb_reg;




   assign	biu_dat_o	= wb_dat_i;




   assign	biu_rty		= (wb_fsm_state_cur == wb_fsm_trans) & wb_rty_i & wb_stb_o & (wb_rty_cnt ~^ biu_rty_cnt);
   assign	biu_ack_o	= (wb_fsm_state_cur == wb_fsm_trans) & wb_ack & wb_stb_o & (wb_ack_cnt ~^ biu_ack_cnt);
   assign	biu_err_o	= (wb_fsm_state_cur == wb_fsm_trans) & wb_err_i & wb_stb_o & (wb_err_cnt ~^ biu_err_cnt)
`ifdef OR1200_WB_RETRY
     | biu_rty & retry_cnt[`OR1200_WB_RETRY-1];
`else
   ;
`endif


endmodule