data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v
1: b'%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:2: Cannot find include file: Constants.v\n`include "Constants.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v\n             data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.v\n             data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.sv\n             Constants.v\n             Constants.v.v\n             Constants.v.sv\n             obj_dir/Constants.v\n             obj_dir/Constants.v.v\n             obj_dir/Constants.v.sv\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:24: Define or directive not defined: \'`ALUOP_ADD\'\n    assign AddSub = ( (operation == `ALUOP_ADD) | (operation == `ALUOP_ADDU));\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign AddSub = ( (operation == `ALUOP_ADD) | (operation == `ALUOP_ADDU));\n                                              ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:24: Define or directive not defined: \'`ALUOP_ADDU\'\n    assign AddSub = ( (operation == `ALUOP_ADD) | (operation == `ALUOP_ADDU));\n                                                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:34: Define or directive not defined: \'`ALUOP_ADD\'\n            `ALUOP_ADD  : result <= AddSub_Result;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:34: syntax error, unexpected \':\', expecting endcase\n            `ALUOP_ADD  : result <= AddSub_Result;\n                        ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:35: Define or directive not defined: \'`ALUOP_ADDU\'\n            `ALUOP_ADDU : result <= AddSub_Result;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:36: Define or directive not defined: \'`ALUOP_AND\'\n            `ALUOP_AND  : result <= (A & B);\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:37: Define or directive not defined: \'`ALUOP_MUL\'\n            `ALUOP_MUL  : result <= Mult_Result[31:0];\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:38: Define or directive not defined: \'`ALUOP_NOR\'\n            `ALUOP_NOR  : result <= ~(A | B);\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:39: Define or directive not defined: \'`ALUOP_OR\'\n            `ALUOP_OR   : result <= (A | B);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:40: Define or directive not defined: \'`ALUOP_SLL\'\n            `ALUOP_SLL  : result <= B << shamt;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:41: Define or directive not defined: \'`ALUOP_SLT\'\n            `ALUOP_SLT  : result <= (A_signed < B_signed) ? 32\'h00000001 : 32\'h00000000;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:42: Define or directive not defined: \'`ALUOP_SLTU\'\n            `ALUOP_SLTU : result <= (A < B)               ? 32\'h00000001 : 32\'h00000000;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:43: Define or directive not defined: \'`ALUOP_SRL\'\n            `ALUOP_SRL  : result <= B >> shamt;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:44: Define or directive not defined: \'`ALUOP_SUB\'\n            `ALUOP_SUB  : result <= AddSub_Result;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:45: Define or directive not defined: \'`ALUOP_SUBU\'\n            `ALUOP_SUBU : result <= AddSub_Result;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:46: Define or directive not defined: \'`ALUOP_XOR\'\n            `ALUOP_XOR  : result <= A ^ B;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:54: Define or directive not defined: \'`ALUOP_ADD\'\n            `ALUOP_ADD : overflow <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31]));\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:55: Define or directive not defined: \'`ALUOP_SUB\'\n            `ALUOP_SUB : overflow <= ((A[31]  ^ B[31]) & (A[31] ^ AddSub_Result[31]));\n            ^~~~~~~~~~\n%Error: Cannot continue\n'
module ArithmeticLogicUnit (
    input [31:0]        A,
    input [31:0]        B,
    input [4:0]         operation,
    input signed [4:0]  shamt,

    output reg signed [31:0]    result,
    output reg                  overflow
);

    wire               AddSub;
    wire signed [31:0] A_signed;
    wire signed [31:0] B_signed;
    wire signed [31:0] AddSub_Result;
    wire signed [31:0] Mult_Result;

    assign A_signed = A;
    assign B_signed = B;


    assign AddSub = ( (operation == `ALUOP_ADD) | (operation == `ALUOP_ADDU));

    assign AddSub_Result = (AddSub) ? (A + B) : (A - B);


    assign Mult_Result = A_signed * B_signed;


    always @ ( * ) begin
        case (operation)
            `ALUOP_ADD  : result <= AddSub_Result;
            `ALUOP_ADDU : result <= AddSub_Result;
            `ALUOP_AND  : result <= (A & B);
            `ALUOP_MUL  : result <= Mult_Result[31:0];
            `ALUOP_NOR  : result <= ~(A | B);
            `ALUOP_OR   : result <= (A | B);
            `ALUOP_SLL  : result <= B << shamt;
            `ALUOP_SLT  : result <= (A_signed < B_signed) ? 32'h00000001 : 32'h00000000;
            `ALUOP_SLTU : result <= (A < B)               ? 32'h00000001 : 32'h00000000;
            `ALUOP_SRL  : result <= B >> shamt;
            `ALUOP_SUB  : result <= AddSub_Result;
            `ALUOP_SUBU : result <= AddSub_Result;
            `ALUOP_XOR  : result <= A ^ B;
            default     : result <= 32'hxxxxxxxx;
        endcase
    end


    always @ ( * ) begin
        case (operation)
            `ALUOP_ADD : overflow <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31]));
            `ALUOP_SUB : overflow <= ((A[31]  ^ B[31]) & (A[31] ^ AddSub_Result[31]));
            default    : overflow <= 0;
        endcase
    end


endmodule
module ArithmeticLogicUnit (
    input [31:0]        A,
    input [31:0]        B,
    input [4:0]         operation,
    input signed [4:0]  shamt,

    output reg signed [31:0]    result,
    output reg                  overflow
);


    wire               AddSub;
    wire signed [31:0] A_signed;
    wire signed [31:0] B_signed;
    wire signed [31:0] AddSub_Result;
    wire signed [31:0] Mult_Result;

    assign A_signed = A;
    assign B_signed = B;


    assign AddSub = ( (operation == `ALUOP_ADD) | (operation == `ALUOP_ADDU));

    assign AddSub_Result = (AddSub) ? (A + B) : (A - B);


    assign Mult_Result = A_signed * B_signed;


    always @ ( * ) begin
        case (operation)
            `ALUOP_ADD  : result <= AddSub_Result;
            `ALUOP_ADDU : result <= AddSub_Result;
            `ALUOP_AND  : result <= (A & B);
            `ALUOP_MUL  : result <= Mult_Result[31:0];
            `ALUOP_NOR  : result <= ~(A | B);
            `ALUOP_OR   : result <= (A | B);
            `ALUOP_SLL  : result <= B << shamt;
            `ALUOP_SLT  : result <= (A_signed < B_signed) ? 32'h00000001 : 32'h00000000;
            `ALUOP_SLTU : result <= (A < B)               ? 32'h00000001 : 32'h00000000;
            `ALUOP_SRL  : result <= B >> shamt;
            `ALUOP_SUB  : result <= AddSub_Result;
            `ALUOP_SUBU : result <= AddSub_Result;
            `ALUOP_XOR  : result <= A ^ B;
            default     : result <= 32'hxxxxxxxx;
        endcase
    end


    always @ ( * ) begin
        case (operation)
            `ALUOP_ADD : overflow <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31]));
            `ALUOP_SUB : overflow <= ((A[31]  ^ B[31]) & (A[31] ^ AddSub_Result[31]));
            default    : overflow <= 0;
        endcase
    end


endmodule