data/full_repos/permissive/143278/ivltests/real_select_invalid.v
 line:2: before: "real"
1: b'%Error: data/full_repos/permissive/143278/ivltests/real_select_invalid.v:35: Unsupported: Verilog 1995 gate primitive: tran\n  tran(wrbstr[0], wrarr[1]);\n      ^\n%Error: data/full_repos/permissive/143278/ivltests/real_select_invalid.v:36: Unsupported: Verilog 1995 gate primitive: tran\n  tran(wrpstr[0:0], wrarr[1]);\n      ^\n%Error: data/full_repos/permissive/143278/ivltests/real_select_invalid.v:37: Unsupported: Verilog 1995 gate primitive: tran\n  tran(wruptr[0+:1], wrarr[1]);\n      ^\n%Error: data/full_repos/permissive/143278/ivltests/real_select_invalid.v:38: Unsupported: Verilog 1995 gate primitive: tran\n  tran(wrdotr[0-:1], wrarr[1]);\n      ^\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module submod1(arg1, arg2, arg3, arg4);
  input arg1, arg2, arg3, arg4;
  wire real arg1, arg2, arg3, arg4;

  initial $display("In submod1 with %g, %g, %g, %g", arg1, arg2, arg3, arg4);
endmodule
module submod1(arg1, arg2, arg3, arg4);

  input arg1, arg2, arg3, arg4;
  wire real arg1, arg2, arg3, arg4;

  initial $display("In submod1 with %g, %g, %g, %g", arg1, arg2, arg3, arg4);
endmodule