data/full_repos/permissive/143278/ivltests/pr2785294.v
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr2785294.v:13: Unsupported or unknown PLI call: $monitor\n    $monitor($time," BS = ", bs[1], ", PS = ", ps[2:1], ", AR = ", array[0][1]);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2785294.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #1 bs[idx] = 1\'b1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2785294.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #1 ps[idx] = 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2785294.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 array[0][idx] = 1\'b1;\n      ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;



  reg [7:0] array [1:0];
  reg [7:0] bs, ps;
  integer idx;

  initial begin
    bs = 8'b0;
    ps = 8'b0;
    array[0] = 8'b0;
    $monitor($time," BS = ", bs[1], ", PS = ", ps[2:1], ", AR = ", array[0][1]);


    for (idx = 0; idx < 8 ; idx = idx + 1) begin
      #1 bs[idx] = 1'b1;
    end


    for (idx = 0; idx < 8 ; idx = idx + 1) begin
      #1 ps[idx] = 1'b1;
    end


    for (idx = 0; idx < 8 ; idx = idx + 1) begin
      #1 array[0][idx] = 1'b1;
    end
  end
endmodule
module top;




  reg [7:0] array [1:0];
  reg [7:0] bs, ps;
  integer idx;

  initial begin
    bs = 8'b0;
    ps = 8'b0;
    array[0] = 8'b0;
    $monitor($time," BS = ", bs[1], ", PS = ", ps[2:1], ", AR = ", array[0][1]);


    for (idx = 0; idx < 8 ; idx = idx + 1) begin
      #1 bs[idx] = 1'b1;
    end


    for (idx = 0; idx < 8 ; idx = idx + 1) begin
      #1 ps[idx] = 1'b1;
    end


    for (idx = 0; idx < 8 ; idx = idx + 1) begin
      #1 array[0][idx] = 1'b1;
    end
  end
endmodule