data/full_repos/permissive/200104480/Processor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:440: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'singleBit\' generates 1 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.A.ze\n assign dataOut = 32\'b0 + singleBit;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:361: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'dataIn\' generates 16 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.ZE\n assign dataOut = 32\'b0 + dataIn;\n                        ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder32(input [31:0] A,
				input [31:0] B,
				input carryIn,
				output [31:0] sum,
				output carryOut);		
				
	wire [6:0] C;
	adder4 add0(A[3:0],   B[3:0], carryIn, sum[3:0],   C[0]);
	adder4 add1(A[7:4],   B[7:4],   C[0],  sum[7:4],   C[1]);
	adder4 add2(A[11:8],  B[11:8],  C[1],  sum[11:8],  C[2]);
	adder4 add3(A[15:12], B[15:12], C[2],  sum[15:12], C[3]);
	adder4 add4(A[19:16], B[19:16], C[3],  sum[19:16], C[4]);
	adder4 add5(A[23:20], B[23:20], C[4],  sum[23:20], C[5]);
	adder4 add6(A[27:24], B[27:24], C[5],  sum[27:24], C[6]);
	adder4 add7(A[31:28], B[31:28], C[6],  sum[31:28], carryOut);
endmodule
module adder32(input [31:0] A,
				input [31:0] B,
				input carryIn,
				output [31:0] sum,
				output carryOut);
		
				
	wire [6:0] C;
	adder4 add0(A[3:0],   B[3:0], carryIn, sum[3:0],   C[0]);
	adder4 add1(A[7:4],   B[7:4],   C[0],  sum[7:4],   C[1]);
	adder4 add2(A[11:8],  B[11:8],  C[1],  sum[11:8],  C[2]);
	adder4 add3(A[15:12], B[15:12], C[2],  sum[15:12], C[3]);
	adder4 add4(A[19:16], B[19:16], C[3],  sum[19:16], C[4]);
	adder4 add5(A[23:20], B[23:20], C[4],  sum[23:20], C[5]);
	adder4 add6(A[27:24], B[27:24], C[5],  sum[27:24], C[6]);
	adder4 add7(A[31:28], B[31:28], C[6],  sum[31:28], carryOut);
endmodule