data/full_repos/permissive/172201645/test_benches/tb_scrambler_reset_inserter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_scrambler_reset_inserter.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_scrambler_reset_inserter.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_scrambler_reset_inserter.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_scrambler_reset_inserter.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #4\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_scrambler_reset_inserter.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_scrambler_reset_inserter.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_scrambler_reset_inserter.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_scrambler_reset_inserter.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_scrambler_reset_inserter.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_scrambler_reset_inserter.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Error: data/full_repos/permissive/172201645/test_benches/tb_scrambler_reset_inserter.v:96: Cannot find file containing module: \'scrambler_reset_inserter\'\nscrambler_reset_inserter  i_scrambler_reset_inserter(\n^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/scrambler_reset_inserter\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/scrambler_reset_inserter.v\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/scrambler_reset_inserter.sv\n             scrambler_reset_inserter\n             scrambler_reset_inserter.v\n             scrambler_reset_inserter.sv\n             obj_dir/scrambler_reset_inserter\n             obj_dir/scrambler_reset_inserter.v\n             obj_dir/scrambler_reset_inserter.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_scrambler_reset_inserter;

    reg clk = 1'b1;

    reg  [71:0] in_data;
    wire [71:0] out_data;

    localparam [8:0] BS = 9'b110111100;

initial begin
    
    in_data      = 72'b0;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
   
    forever begin
        #1
        in_data[8:0] = BS;
        #3
        clk = ~clk;
        #4
        clk = ~clk;
        #1
        in_data      = 72'b0;
        #3
        clk = ~clk;
        #4
        clk = ~clk;
    end
end

scrambler_reset_inserter  i_scrambler_reset_inserter(
    .clk      (clk),
    .in_data  (in_data),
    .out_data (out_data)
);

endmodule
module tb_scrambler_reset_inserter;


    reg clk = 1'b1;

    reg  [71:0] in_data;
    wire [71:0] out_data;

    localparam [8:0] BS = 9'b110111100;

initial begin
    
    in_data      = 72'b0;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
   
    forever begin
        #1
        in_data[8:0] = BS;
        #3
        clk = ~clk;
        #4
        clk = ~clk;
        #1
        in_data      = 72'b0;
        #3
        clk = ~clk;
        #4
        clk = ~clk;
    end
end

scrambler_reset_inserter  i_scrambler_reset_inserter(
    .clk      (clk),
    .in_data  (in_data),
    .out_data (out_data)
);

endmodule