data/full_repos/permissive/143278/ivltests/sv_union3b.v
 line:3: before: "typedef"
data/verilator_xmls/44893018-c01c-4e3a-8c4b-e1b5e213fc94.xml
module main;

   bits_t foo;

   initial begin
      foo.bits = 'b1001;
      if (foo.bits !== 'b1001) begin
	 $display("FAILED -- foo.bits=%b", foo.bits);
	 $finish;
      end

      if (foo.words !== WORD9) begin
	 $display("FAILED -- foo.words=%b", foo.words);
	 $finish;
      end

      foo.words = WORDC;
      if (foo.words !== WORDC) begin
	 $display("FAILED -- foo.words=%b", foo.words);
	 $finish;
      end
      if (foo.bits !== 'b1100) begin
	 $display("FAILED -- foo.bits=%b", foo.bits);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   bits_t foo;

   initial begin
      foo.bits = 'b1001;
      if (foo.bits !== 'b1001) begin
	 $display("FAILED -- foo.bits=%b", foo.bits);
	 $finish;
      end

      if (foo.words !== WORD9) begin
	 $display("FAILED -- foo.words=%b", foo.words);
	 $finish;
      end

      foo.words = WORDC;
      if (foo.words !== WORDC) begin
	 $display("FAILED -- foo.words=%b", foo.words);
	 $finish;
      end
      if (foo.bits !== 'b1100) begin
	 $display("FAILED -- foo.bits=%b", foo.bits);
	 $finish;
      end

      $display("PASSED");
   end

endmodule