data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v
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1: b'%Error: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:87: Unsupported or unknown PLI call: $dumpvars\n           $dumpvars(0,A);\n           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:88: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:99: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:102: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:105: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:108: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:111: Unsupported: Ignoring delay on this delayed statement.\n           #40\n           ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TesteTriangulo (
    input [11:0] Ponto1X,
    input [11:0] Ponto1Y,

    input [11:0] Ponto2X,
    input [11:0] Ponto2Y,

    input [11:0] Ponto3X,
    input [11:0] Ponto3Y,

    input [11:0] PontoTX,
    input [11:0] PontoTY,

    output dentro
    );

    wire sinal1;
    wire sinal2;
    wire sinal3;

    assign dentro = (sinal1 == 1 && sinal2 == 1 && sinal3 == 1) ? 1:0;

    sinal S1(Ponto1X, Ponto1Y, Ponto2X, Ponto2Y, PontoTX, PontoTY, sinal1);
    sinal S2(Ponto2X, Ponto2Y, Ponto3X, Ponto3Y, PontoTX, PontoTY, sinal2);
    sinal S3(Ponto3X, Ponto3Y, Ponto1X, Ponto1Y, PontoTX, PontoTY, sinal3);

endmodule
module TesteTriangulo (
    input [11:0] Ponto1X,
    input [11:0] Ponto1Y,

    input [11:0] Ponto2X,
    input [11:0] Ponto2Y,

    input [11:0] Ponto3X,
    input [11:0] Ponto3Y,

    input [11:0] PontoTX,
    input [11:0] PontoTY,

    output dentro
    );


    wire sinal1;
    wire sinal2;
    wire sinal3;

    assign dentro = (sinal1 == 1 && sinal2 == 1 && sinal3 == 1) ? 1:0;

    sinal S1(Ponto1X, Ponto1Y, Ponto2X, Ponto2Y, PontoTX, PontoTY, sinal1);
    sinal S2(Ponto2X, Ponto2Y, Ponto3X, Ponto3Y, PontoTX, PontoTY, sinal2);
    sinal S3(Ponto3X, Ponto3Y, Ponto1X, Ponto1Y, PontoTX, PontoTY, sinal3);

endmodule