data/full_repos/permissive/174642777/Experiments/Lab X3/Lab 10 SHF_D4C3/SHF_D4C3.v
1: b'%Error: Cannot find file containing module: X3/Lab\n        ... Looked in:\n             data/full_repos/permissive/174642777/Experiments/Lab/X3/Lab\n             data/full_repos/permissive/174642777/Experiments/Lab/X3/Lab.v\n             data/full_repos/permissive/174642777/Experiments/Lab/X3/Lab.sv\n             X3/Lab\n             X3/Lab.v\n             X3/Lab.sv\n             obj_dir/X3/Lab\n             obj_dir/X3/Lab.v\n             obj_dir/X3/Lab.sv\n%Error: Cannot find file containing module: 10\n%Error: Cannot find file containing module: SHF_D4C3,data/full_repos/permissive/174642777\n%Error: Cannot find file containing module: data/full_repos/permissive/174642777/Experiments/Lab\n%Error: Cannot find file containing module: SHF_D4C3/SHF_D4C3.v\n%Error: Exiting due to 5 error(s)\n'
module SHF_D4C3(
  input wire[3:0] d,
  input wire[2:0] s,
  output wire[3:0] y
);

  reg[3:0] rd;
  reg[2:0] rs;
  reg[3:0] ry;
  
  assign y = ry;
  
  always@(*) begin
    rd = d;
    rs = s;
    
    if(rs == 0) begin
      ry = rd;
    end
    else if(rs == 1) begin
      ry[2:0] = rd[3:1];
      ry[3] = 0;
    end
    else if(rs == 2) begin
      ry[3:1] = rd[2:0];
      ry[0] = 0;
    end
    else if(rs == 3) begin
      ry[2:0] = rd[3:1];
      ry[3] = rd[0];
    end
    else if(rs == 4) begin
      ry[3:1] = rd[2:0];
      ry[0] = rd[3];
    end
    else if(rs == 5) begin
      ry[2:0] = rd[3:1];
      ry[3] = rd[3];
    end
    else if(rs == 6) begin
      ry[1:0] = rd[3:2];
      ry[3:2] = rd[1:0];
    end
    else if(rs == 7) begin
      ry = rd;
    end
  end

endmodule
module SHF_D4C3(
  input wire[3:0] d,
  input wire[2:0] s,
  output wire[3:0] y
);


  reg[3:0] rd;
  reg[2:0] rs;
  reg[3:0] ry;
  
  assign y = ry;
  
  always@(*) begin
    rd = d;
    rs = s;
    
    if(rs == 0) begin
      ry = rd;
    end
    else if(rs == 1) begin
      ry[2:0] = rd[3:1];
      ry[3] = 0;
    end
    else if(rs == 2) begin
      ry[3:1] = rd[2:0];
      ry[0] = 0;
    end
    else if(rs == 3) begin
      ry[2:0] = rd[3:1];
      ry[3] = rd[0];
    end
    else if(rs == 4) begin
      ry[3:1] = rd[2:0];
      ry[0] = rd[3];
    end
    else if(rs == 5) begin
      ry[2:0] = rd[3:1];
      ry[3] = rd[3];
    end
    else if(rs == 6) begin
      ry[1:0] = rd[3:2];
      ry[3:2] = rd[1:0];
    end
    else if(rs == 7) begin
      ry = rd;
    end
  end

endmodule