data/full_repos/permissive/192101253/testbench.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #3 clk_in = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #3 clk_in = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #13 clk_out = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #13 clk_out = 1;\n  ^\n%Error: data/full_repos/permissive/192101253/testbench.v:44: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("testbench.lxt");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/192101253/testbench.v:45: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #100 reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #6 din = 8\'hA5;\n  ^\n%Error: data/full_repos/permissive/192101253/testbench.v:60: Unsupported: wait statements\n  wait(!clk_in);\n  ^~~~\n%Error: data/full_repos/permissive/192101253/testbench.v:61: Unsupported: wait statements\n  wait(clk_in); #1 we = 1;\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:61: Unsupported: Ignoring delay on this delayed statement.\n  wait(clk_in); #1 we = 1;\n                ^\n%Error: data/full_repos/permissive/192101253/testbench.v:62: Unsupported: wait statements\n  wait(!clk_in);\n  ^~~~\n%Error: data/full_repos/permissive/192101253/testbench.v:63: Unsupported: wait statements\n  wait(clk_in); #1 we = 0;\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:63: Unsupported: Ignoring delay on this delayed statement.\n  wait(clk_in); #1 we = 0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #6 din = 8\'hx;\n  ^\n%Error: data/full_repos/permissive/192101253/testbench.v:67: Unsupported: wait statements\n  wait(ready); #78;\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:67: Unsupported: Ignoring delay on this delayed statement.\n  wait(ready); #78;\n               ^\n%Error: data/full_repos/permissive/192101253/testbench.v:70: Unsupported: wait statements\n  wait(!clk_out);\n  ^~~~\n%Error: data/full_repos/permissive/192101253/testbench.v:71: Unsupported: wait statements\n  wait(clk_out); #1 re = 1;\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:71: Unsupported: Ignoring delay on this delayed statement.\n  wait(clk_out); #1 re = 1;\n                 ^\n%Error: data/full_repos/permissive/192101253/testbench.v:72: Unsupported: wait statements\n  wait(!clk_out);\n  ^~~~\n%Error: data/full_repos/permissive/192101253/testbench.v:73: Unsupported: wait statements\n  wait(clk_out); #1 re = 0;\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:73: Unsupported: Ignoring delay on this delayed statement.\n  wait(clk_out); #1 re = 0;\n                 ^\n%Error: data/full_repos/permissive/192101253/testbench.v:76: Unsupported: wait statements\n  wait(!busy);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/192101253/testbench.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #100 $display("finished");\n  ^\n%Error: Exiting due to 12 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

	reg reset;

	reg clk_in;
	reg we;
	reg [7:0] din;
	wire busy;

	reg clk_out;
	reg re;
	wire [7:0] dout;
	wire ready;


	ccd_register uut (
		.reset,
		.clk_in,
		.we,
		.din,
		.busy,
		.clk_out,
		.re,
		.dout,
		.ready
	);



	always begin
		#3 clk_in = 0;
		#3 clk_in = 1;
	end

	always begin
		#13 clk_out = 0;
		#13 clk_out = 1;
	end

	initial begin

		$dumpfile("testbench.lxt");
		$dumpvars;


		reset = 1;
		clk_in = 1;
		we = 0;
		din = 8'hx;
		clk_out = 1;
		re = 0;


		#100 reset = 0;


		#6 din = 8'hA5;
		wait(!clk_in);
		wait(clk_in); #1 we = 1;
		wait(!clk_in);
		wait(clk_in); #1 we = 0;
		#6 din = 8'hx;


		wait(ready); #78;
		

		wait(!clk_out);
		wait(clk_out); #1 re = 1;
		wait(!clk_out);
		wait(clk_out); #1 re = 0;


		wait(!busy);


		#100 $display("finished");
		$finish;
	end

endmodule
module testbench;


	reg reset;

	reg clk_in;
	reg we;
	reg [7:0] din;
	wire busy;

	reg clk_out;
	reg re;
	wire [7:0] dout;
	wire ready;


	ccd_register uut (
		.reset,
		.clk_in,
		.we,
		.din,
		.busy,
		.clk_out,
		.re,
		.dout,
		.ready
	);



	always begin
		#3 clk_in = 0;
		#3 clk_in = 1;
	end

	always begin
		#13 clk_out = 0;
		#13 clk_out = 1;
	end

	initial begin

		$dumpfile("testbench.lxt");
		$dumpvars;


		reset = 1;
		clk_in = 1;
		we = 0;
		din = 8'hx;
		clk_out = 1;
		re = 0;


		#100 reset = 0;


		#6 din = 8'hA5;
		wait(!clk_in);
		wait(clk_in); #1 we = 1;
		wait(!clk_in);
		wait(clk_in); #1 we = 0;
		#6 din = 8'hx;


		wait(ready); #78;
		

		wait(!clk_out);
		wait(clk_out); #1 re = 1;
		wait(!clk_out);
		wait(clk_out); #1 re = 0;


		wait(!busy);


		#100 $display("finished");
		$finish;
	end

endmodule