data/full_repos/permissive/140572461/hdl/cpu_core.v
 line:134: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/140572461/hdl/cpu_core.v:133: Unsupported: Ignoring delay on this delayed statement.\n    #50 reset <= 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/140572461/hdl/cpu_core.v:134: Unsupported: Ignoring delay on this delayed statement.\n    #85 $display("addr %x: %s",\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/140572461/hdl/cpu_core.v:137: Unsupported: Ignoring delay on this delayed statement.\n    #10000000 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/140572461/hdl/cpu_core.v:140: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk <= ~clk;\n       ^\n%Error: data/full_repos/permissive/140572461/hdl/cpu_core.v:38: Cannot find file containing module: \'ram\'\nram #(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/140572461/hdl,data/full_repos/permissive/140572461/ram\n             data/full_repos/permissive/140572461/hdl,data/full_repos/permissive/140572461/ram.v\n             data/full_repos/permissive/140572461/hdl,data/full_repos/permissive/140572461/ram.sv\n             ram\n             ram.v\n             ram.sv\n             obj_dir/ram\n             obj_dir/ram.v\n             obj_dir/ram.sv\n%Error: data/full_repos/permissive/140572461/hdl/cpu_core.v:57: Cannot find file containing module: \'rom\'\nrom #(\n^~~\n%Error: data/full_repos/permissive/140572461/hdl/cpu_core.v:75: Cannot find file containing module: \'gpio\'\ngpio gpio1_device(\n^~~~\n%Error: data/full_repos/permissive/140572461/hdl/cpu_core.v:86: Cannot find file containing module: \'cpu\'\ncpu cpu(\n^~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_core #(parameter ROM_FILE = "foo.hex") (
    input           clk,
    input           reset,
    output  [7:0]   gpio1
);

wire [15:0] addr;
wire [7:0] cpu_do;
wire [7:0] cpu_di;
wire we;




wire [7:0] ram_do;
wire cs_ram = (addr[15:10]   == 6'b000000) ? 1'b1 : 1'b0;
reg cs_ram_prev = 1'b0;
always @(posedge clk) cs_ram_prev <= cs_ram;
ram #(
    .ADDR_WIDTH(10),
    .DEPTH(1024))
ram(
    .clk (clk),
    .cs (cs_ram),
    .we (we && cs_ram),
    .addr (addr[9:0]),
    .data_in (cpu_do),
    .data_out (ram_do)
);




wire [7:0] rom_do;
wire cs_rom = (addr[15:10]   == 6'b111111) ? 1'b1 : 1'b0;
reg cs_rom_prev = 1'b0;
always @(posedge clk) cs_rom_prev <= cs_rom;
rom #(
    .ADDR_WIDTH(10),
    .DEPTH(1024),
    .ROM_FILE(ROM_FILE))
rom(
    .clk (clk),
    .cs (cs_rom),
    .addr (addr[9:0]),
    .data_in (cpu_do),
    .data_out (rom_do)
);




wire cs_gpio1 = (addr[15:10] == 6'b000001) ? 1'b1 : 1'b0;
reg cs_gpio1_prev = 1'b0;
always @(posedge clk) cs_gpio1_prev <= cs_gpio1;
gpio gpio1_device(
    .clk (clk),
    .reset (reset),
    .cs (cs_gpio1),
    .data_in (cpu_do),
    .data_out (gpio1)
);




cpu cpu(
    .clk (clk),
    .reset (reset),
    .AB (addr),
    .DI (cpu_di),
    .DO (cpu_do),
    .WE (we),
    .IRQ (1'b0),
    .NMI (1'b0),
    .RDY (1'b1)
);


assign cpu_di =
    cs_ram_prev ? ram_do :
    cs_rom_prev ? rom_do :
    cs_gpio1_prev ? gpio1 :
    8'h00;

endmodule
module cpu_core #(parameter ROM_FILE = "foo.hex") (
    input           clk,
    input           reset,
    output  [7:0]   gpio1
);


wire [15:0] addr;
wire [7:0] cpu_do;
wire [7:0] cpu_di;
wire we;




wire [7:0] ram_do;
wire cs_ram = (addr[15:10]   == 6'b000000) ? 1'b1 : 1'b0;
reg cs_ram_prev = 1'b0;
always @(posedge clk) cs_ram_prev <= cs_ram;
ram #(
    .ADDR_WIDTH(10),
    .DEPTH(1024))
ram(
    .clk (clk),
    .cs (cs_ram),
    .we (we && cs_ram),
    .addr (addr[9:0]),
    .data_in (cpu_do),
    .data_out (ram_do)
);




wire [7:0] rom_do;
wire cs_rom = (addr[15:10]   == 6'b111111) ? 1'b1 : 1'b0;
reg cs_rom_prev = 1'b0;
always @(posedge clk) cs_rom_prev <= cs_rom;
rom #(
    .ADDR_WIDTH(10),
    .DEPTH(1024),
    .ROM_FILE(ROM_FILE))
rom(
    .clk (clk),
    .cs (cs_rom),
    .addr (addr[9:0]),
    .data_in (cpu_do),
    .data_out (rom_do)
);




wire cs_gpio1 = (addr[15:10] == 6'b000001) ? 1'b1 : 1'b0;
reg cs_gpio1_prev = 1'b0;
always @(posedge clk) cs_gpio1_prev <= cs_gpio1;
gpio gpio1_device(
    .clk (clk),
    .reset (reset),
    .cs (cs_gpio1),
    .data_in (cpu_do),
    .data_out (gpio1)
);




cpu cpu(
    .clk (clk),
    .reset (reset),
    .AB (addr),
    .DI (cpu_di),
    .DO (cpu_do),
    .WE (we),
    .IRQ (1'b0),
    .NMI (1'b0),
    .RDY (1'b1)
);


assign cpu_di =
    cs_ram_prev ? ram_do :
    cs_rom_prev ? rom_do :
    cs_gpio1_prev ? gpio1 :
    8'h00;

endmodule