data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:5: Cannot find include file: vc-TestRandDelaySource.v\n`include "vc-TestRandDelaySource.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/23713597/lab4/vc,data/full_repos/permissive/23713597/vc-TestRandDelaySource.v\n             data/full_repos/permissive/23713597/lab4/vc,data/full_repos/permissive/23713597/vc-TestRandDelaySource.v.v\n             data/full_repos/permissive/23713597/lab4/vc,data/full_repos/permissive/23713597/vc-TestRandDelaySource.v.sv\n             vc-TestRandDelaySource.v\n             vc-TestRandDelaySource.v.v\n             vc-TestRandDelaySource.v.sv\n             obj_dir/vc-TestRandDelaySource.v\n             obj_dir/vc-TestRandDelaySource.v.v\n             obj_dir/vc-TestRandDelaySource.v.sv\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:6: Cannot find include file: vc-TestRandDelaySink.v\n`include "vc-TestRandDelaySink.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:7: Cannot find include file: vc-TestRandDelayMem_1port.v\n`include "vc-TestRandDelayMem_1port.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:8: Cannot find include file: vc-test.v\n`include "vc-test.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:9: Cannot find include file: vc-trace.v\n`include "vc-trace.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:33: Define or directive not defined: \'`VC_MEM_REQ_MSG_NBITS\'\n  localparam c_req_nbits  = `VC_MEM_REQ_MSG_NBITS(c_opaque_nbits,c_addr_nbits,c_data_nbits);\n                            ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:33: syntax error, unexpected \',\'\n  localparam c_req_nbits  = `VC_MEM_REQ_MSG_NBITS(c_opaque_nbits,c_addr_nbits,c_data_nbits);\n                                                                ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:34: Define or directive not defined: \'`VC_MEM_RESP_MSG_NBITS\'\n  localparam c_resp_nbits = `VC_MEM_RESP_MSG_NBITS(c_opaque_nbits,c_data_nbits);\n                            ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:34: syntax error, unexpected \',\'\n  localparam c_resp_nbits = `VC_MEM_RESP_MSG_NBITS(c_opaque_nbits,c_data_nbits);\n                                                                 ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:107: Define or directive not defined: \'`VC_TRACE_BEGIN\'\n  `VC_TRACE_BEGIN\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:108: syntax error, unexpected begin\n  begin\n  ^~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:111: syntax error, unexpected \'(\', expecting IDENTIFIER\n    vc_trace.append_str( trace_str, " > " );\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:113: syntax error, unexpected \'(\', expecting IDENTIFIER\n    mem.trace( trace_str );\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:115: syntax error, unexpected \'(\', expecting IDENTIFIER\n    vc_trace.append_str( trace_str, " > " );\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:116: syntax error, unexpected \'(\', expecting IDENTIFIER\n    sink.trace( trace_str );\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:119: Define or directive not defined: \'`VC_TRACE_END\'\n  `VC_TRACE_END\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:128: Define or directive not defined: \'`VC_TEST_SUITE_BEGIN\'\n  `VC_TEST_SUITE_BEGIN( "vc-TestRandDelayMem_1port" )\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:169: Define or directive not defined: \'`VC_MEM_REQ_MSG_NBITS\'\n  reg [`VC_MEM_REQ_MSG_NBITS(8,16,32)-1:0] th_port_memreq;\n       ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:169: syntax error, unexpected \',\'\n  reg [`VC_MEM_REQ_MSG_NBITS(8,16,32)-1:0] th_port_memreq;\n                              ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:170: Define or directive not defined: \'`VC_MEM_RESP_MSG_NBITS\'\n  reg [`VC_MEM_RESP_MSG_NBITS(8,32)-1:0]   th_port_memresp;\n       ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:170: syntax error, unexpected \',\'\n  reg [`VC_MEM_RESP_MSG_NBITS(8,32)-1:0]   th_port_memresp;\n                               ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:176: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_NBITS\'\n    input [`VC_MEM_REQ_MSG_TYPE_NBITS(8,16,32)-1:0]   memreq_type,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:176: syntax error, unexpected \',\'\n    input [`VC_MEM_REQ_MSG_TYPE_NBITS(8,16,32)-1:0]   memreq_type,\n                                       ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:177: Define or directive not defined: \'`VC_MEM_REQ_MSG_OPAQUE_NBITS\'\n    input [`VC_MEM_REQ_MSG_OPAQUE_NBITS(8,16,32)-1:0] memreq_opaque,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:178: Define or directive not defined: \'`VC_MEM_REQ_MSG_ADDR_NBITS\'\n    input [`VC_MEM_REQ_MSG_ADDR_NBITS(8,16,32)-1:0]   memreq_addr,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:179: Define or directive not defined: \'`VC_MEM_REQ_MSG_LEN_NBITS\'\n    input [`VC_MEM_REQ_MSG_LEN_NBITS(8,16,32)-1:0]    memreq_len,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:180: Define or directive not defined: \'`VC_MEM_REQ_MSG_DATA_NBITS\'\n    input [`VC_MEM_REQ_MSG_DATA_NBITS(8,16,32)-1:0]   memreq_data,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:182: Define or directive not defined: \'`VC_MEM_RESP_MSG_TYPE_NBITS\'\n    input [`VC_MEM_RESP_MSG_TYPE_NBITS(8,32)-1:0]     memresp_type,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:183: Define or directive not defined: \'`VC_MEM_RESP_MSG_OPAQUE_NBITS\'\n    input [`VC_MEM_RESP_MSG_OPAQUE_NBITS(8,32)-1:0]   memresp_opaque,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:184: Define or directive not defined: \'`VC_MEM_RESP_MSG_LEN_NBITS\'\n    input [`VC_MEM_RESP_MSG_LEN_NBITS(8,32)-1:0]      memresp_len,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:185: Define or directive not defined: \'`VC_MEM_RESP_MSG_DATA_NBITS\'\n    input [`VC_MEM_RESP_MSG_DATA_NBITS(8,32)-1:0]     memresp_data\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:188: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_FIELD\'\n    th_port_memreq[`VC_MEM_REQ_MSG_TYPE_FIELD(8,16,32)]   = memreq_type;\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:189: Define or directive not defined: \'`VC_MEM_REQ_MSG_OPAQUE_FIELD\'\n    th_port_memreq[`VC_MEM_REQ_MSG_OPAQUE_FIELD(8,16,32)] = memreq_opaque;\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:190: Define or directive not defined: \'`VC_MEM_REQ_MSG_ADDR_FIELD\'\n    th_port_memreq[`VC_MEM_REQ_MSG_ADDR_FIELD(8,16,32)]   = memreq_addr;\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:191: Define or directive not defined: \'`VC_MEM_REQ_MSG_LEN_FIELD\'\n    th_port_memreq[`VC_MEM_REQ_MSG_LEN_FIELD(8,16,32)]    = memreq_len;\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:192: Define or directive not defined: \'`VC_MEM_REQ_MSG_DATA_FIELD\'\n    th_port_memreq[`VC_MEM_REQ_MSG_DATA_FIELD(8,16,32)]   = memreq_data;\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:194: Define or directive not defined: \'`VC_MEM_RESP_MSG_TYPE_FIELD\'\n    th_port_memresp[`VC_MEM_RESP_MSG_TYPE_FIELD(8,32)]    = memresp_type;\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:195: Define or directive not defined: \'`VC_MEM_RESP_MSG_OPAQUE_FIELD\'\n    th_port_memresp[`VC_MEM_RESP_MSG_OPAQUE_FIELD(8,32)]  = memresp_opaque;\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:196: Define or directive not defined: \'`VC_MEM_RESP_MSG_LEN_FIELD\'\n    th_port_memresp[`VC_MEM_RESP_MSG_LEN_FIELD(8,32)]     = memresp_len;\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:197: Define or directive not defined: \'`VC_MEM_RESP_MSG_DATA_FIELD\'\n    th_port_memresp[`VC_MEM_RESP_MSG_DATA_FIELD(8,32)]    = memresp_data;\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:199: syntax error, unexpected \'.\', expecting IDENTIFIER\n    th.src.src.m[index]   = th_port_memreq;\n          ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:200: syntax error, unexpected \'.\', expecting IDENTIFIER\n    th.sink.sink.m[index] = th_port_memresp;\n           ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:206: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_READ\'\n  localparam c_req_rd  = `VC_MEM_REQ_MSG_TYPE_READ;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:207: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_WRITE\'\n  localparam c_req_wr  = `VC_MEM_REQ_MSG_TYPE_WRITE;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:207: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam c_req_wr  = `VC_MEM_REQ_MSG_TYPE_WRITE;\n                                                   ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:208: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_WRITE_INIT\'\n  localparam c_req_wn  = `VC_MEM_REQ_MSG_TYPE_WRITE_INIT;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:208: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam c_req_wn  = `VC_MEM_REQ_MSG_TYPE_WRITE_INIT;\n                                                        ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:209: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_AMO_ADD\'\n  localparam c_req_ad  = `VC_MEM_REQ_MSG_TYPE_AMO_ADD;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:209: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam c_req_ad  = `VC_MEM_REQ_MSG_TYPE_AMO_ADD;\n                                                     ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:210: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_AMO_AND\'\n  localparam c_req_an  = `VC_MEM_REQ_MSG_TYPE_AMO_AND;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module TestHarness
(
  input         clk,
  input         reset,
  input         mem_clear,
  input  [31:0] src_max_delay,
  input  [31:0] mem_max_delay,
  input  [31:0] sink_max_delay,
  output        done
);



  localparam c_mem_nbytes   = 1024;
  localparam c_opaque_nbits = 8;
  localparam c_addr_nbits   = 16;
  localparam c_data_nbits   = 32;

  localparam c_req_nbits  = `VC_MEM_REQ_MSG_NBITS(c_opaque_nbits,c_addr_nbits,c_data_nbits);
  localparam c_resp_nbits = `VC_MEM_RESP_MSG_NBITS(c_opaque_nbits,c_data_nbits);



  wire                   src_val;
  wire                   src_rdy;
  wire [c_req_nbits-1:0] src_msg;
  wire                   src_done;

  vc_TestRandDelaySource#(c_req_nbits) src
  (
    .clk       (clk),
    .reset     (reset),
    .max_delay (src_max_delay),
    .val       (src_val),
    .rdy       (src_rdy),
    .msg       (src_msg),
    .done      (src_done)
  );



  wire                     sink_val;
  wire                     sink_rdy;
  wire [c_resp_nbits-1:0]  sink_msg;

  vc_TestRandDelayMem_1port
  #(
    .p_mem_nbytes   (c_mem_nbytes),
    .p_opaque_nbits (c_opaque_nbits),
    .p_addr_nbits   (c_addr_nbits),
    .p_data_nbits   (c_data_nbits)
  )
  mem
  (
    .clk          (clk),
    .reset        (reset),
    .mem_clear    (mem_clear),

    .max_delay    (mem_max_delay),

    .memreq_val  (src_val),
    .memreq_rdy  (src_rdy),
    .memreq_msg  (src_msg),

    .memresp_val (sink_val),
    .memresp_rdy (sink_rdy),
    .memresp_msg (sink_msg)
  );



  wire        sink_done;

  vc_TestRandDelaySink#(c_resp_nbits) sink
  (
    .clk        (clk),
    .reset      (reset),
    .max_delay  (sink_max_delay),
    .val        (sink_val),
    .rdy        (sink_rdy),
    .msg        (sink_msg),
    .done       (sink_done)
  );



  assign done = src_done & sink_done;





  `VC_TRACE_BEGIN
  begin

    src.trace( trace_str );
    vc_trace.append_str( trace_str, " > " );

    mem.trace( trace_str );

    vc_trace.append_str( trace_str, " > " );
    sink.trace( trace_str );

  end
  `VC_TRACE_END

endmodule
module TestHarness
(
  input         clk,
  input         reset,
  input         mem_clear,
  input  [31:0] src_max_delay,
  input  [31:0] mem_max_delay,
  input  [31:0] sink_max_delay,
  output        done
);




  localparam c_mem_nbytes   = 1024;
  localparam c_opaque_nbits = 8;
  localparam c_addr_nbits   = 16;
  localparam c_data_nbits   = 32;

  localparam c_req_nbits  = `VC_MEM_REQ_MSG_NBITS(c_opaque_nbits,c_addr_nbits,c_data_nbits);
  localparam c_resp_nbits = `VC_MEM_RESP_MSG_NBITS(c_opaque_nbits,c_data_nbits);



  wire                   src_val;
  wire                   src_rdy;
  wire [c_req_nbits-1:0] src_msg;
  wire                   src_done;

  vc_TestRandDelaySource#(c_req_nbits) src
  (
    .clk       (clk),
    .reset     (reset),
    .max_delay (src_max_delay),
    .val       (src_val),
    .rdy       (src_rdy),
    .msg       (src_msg),
    .done      (src_done)
  );



  wire                     sink_val;
  wire                     sink_rdy;
  wire [c_resp_nbits-1:0]  sink_msg;

  vc_TestRandDelayMem_1port
  #(
    .p_mem_nbytes   (c_mem_nbytes),
    .p_opaque_nbits (c_opaque_nbits),
    .p_addr_nbits   (c_addr_nbits),
    .p_data_nbits   (c_data_nbits)
  )
  mem
  (
    .clk          (clk),
    .reset        (reset),
    .mem_clear    (mem_clear),

    .max_delay    (mem_max_delay),

    .memreq_val  (src_val),
    .memreq_rdy  (src_rdy),
    .memreq_msg  (src_msg),

    .memresp_val (sink_val),
    .memresp_rdy (sink_rdy),
    .memresp_msg (sink_msg)
  );



  wire        sink_done;

  vc_TestRandDelaySink#(c_resp_nbits) sink
  (
    .clk        (clk),
    .reset      (reset),
    .max_delay  (sink_max_delay),
    .val        (sink_val),
    .rdy        (sink_rdy),
    .msg        (sink_msg),
    .done       (sink_done)
  );



  assign done = src_done & sink_done;





  `VC_TRACE_BEGIN
  begin

    src.trace( trace_str );
    vc_trace.append_str( trace_str, " > " );

    mem.trace( trace_str );

    vc_trace.append_str( trace_str, " > " );
    sink.trace( trace_str );

  end
  `VC_TRACE_END

endmodule