data/full_repos/permissive/210844779/lab6/6.4/tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab6/6.4/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab6/6.4/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab6/6.4/tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #5 rst=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab6/6.4/tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab6/6.4/tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab6/6.4/tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Error: data/full_repos/permissive/210844779/lab6/6.4/tb.v:7: Cannot find file containing module: \'fifo\'\n  fifo u0(din,clk,rst,we,re,full,emp,dout);\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab6/6.4,data/full_repos/permissive/210844779/fifo\n             data/full_repos/permissive/210844779/lab6/6.4,data/full_repos/permissive/210844779/fifo.v\n             data/full_repos/permissive/210844779/lab6/6.4,data/full_repos/permissive/210844779/fifo.sv\n             fifo\n             fifo.v\n             fifo.sv\n             obj_dir/fifo\n             obj_dir/fifo.v\n             obj_dir/fifo.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab6/6.4/tb.v:28: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n    begin  din=$random;  \n              ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  reg [7:0] din;
  reg clk,rst,we,re;
  wire full,emp;
  wire [7:0]dout;
  
  fifo u0(din,clk,rst,we,re,full,emp,dout);
  
  integer i;
  
  always
  begin
    clk=0;
    #5
    clk=1;
    #5;
  end
  
  initial
  begin
    rst=1;
    #5 rst=0;
  end
  
  always
    begin
    for(i=0;i<127;i=i+1)
    begin  din=$random;  
    we=1;
	#30
	we=0;re=1;
	#20;
	end
    re=1;we=0;
    #50
     re=0; 
   
    end
  
  
endmodule
module tb();

  reg [7:0] din;
  reg clk,rst,we,re;
  wire full,emp;
  wire [7:0]dout;
  
  fifo u0(din,clk,rst,we,re,full,emp,dout);
  
  integer i;
  
  always
  begin
    clk=0;
    #5
    clk=1;
    #5;
  end
  
  initial
  begin
    rst=1;
    #5 rst=0;
  end
  
  always
    begin
    for(i=0;i<127;i=i+1)
    begin  din=$random;  
    we=1;
	#30
	we=0;re=1;
	#20;
	end
    re=1;we=0;
    #50
     re=0; 
   
    end
  
  
endmodule