data/full_repos/permissive/159016511/src/component/work/sram_4Kx32/sram_4Kx32.v
1: b"%Error: data/full_repos/permissive/159016511/src/component/work/sram_4Kx32/sram_4Kx32.v:59: Cannot find file containing module: 'sram_4Kx32_sram_4Kx32_0_TPSRAM'\nsram_4Kx32_sram_4Kx32_0_TPSRAM sram_4Kx32_0(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159016511/src/component/work/sram_4Kx32,data/full_repos/permissive/159016511/sram_4Kx32_sram_4Kx32_0_TPSRAM\n             data/full_repos/permissive/159016511/src/component/work/sram_4Kx32,data/full_repos/permissive/159016511/sram_4Kx32_sram_4Kx32_0_TPSRAM.v\n             data/full_repos/permissive/159016511/src/component/work/sram_4Kx32,data/full_repos/permissive/159016511/sram_4Kx32_sram_4Kx32_0_TPSRAM.sv\n             sram_4Kx32_sram_4Kx32_0_TPSRAM\n             sram_4Kx32_sram_4Kx32_0_TPSRAM.v\n             sram_4Kx32_sram_4Kx32_0_TPSRAM.sv\n             obj_dir/sram_4Kx32_sram_4Kx32_0_TPSRAM\n             obj_dir/sram_4Kx32_sram_4Kx32_0_TPSRAM.v\n             obj_dir/sram_4Kx32_sram_4Kx32_0_TPSRAM.sv\n%Error: Exiting due to 1 error(s)\n"
module sram_4Kx32(

    CLK,
    RADDR,
    WADDR,
    WD,
    WEN,

    RD
);




input         CLK;
input  [11:0] RADDR;
input  [11:0] WADDR;
input  [31:0] WD;
input         WEN;



output [31:0] RD;



wire          CLK;
wire   [11:0] RADDR;
wire   [31:0] RD_0;
wire   [11:0] WADDR;
wire   [31:0] WD;
wire          WEN;
wire   [31:0] RD_0_net_0;



wire          GND_net;



assign GND_net = 1'b0;



assign RD_0_net_0 = RD_0;
assign RD[31:0]   = RD_0_net_0;




sram_4Kx32_sram_4Kx32_0_TPSRAM sram_4Kx32_0(

        .WD    ( WD ),
        .WADDR ( WADDR ),
        .RADDR ( RADDR ),
        .WEN   ( WEN ),
        .CLK   ( CLK ),

        .RD    ( RD_0 ) 
        );


endmodule
module sram_4Kx32(

    CLK,
    RADDR,
    WADDR,
    WD,
    WEN,

    RD
);





input         CLK;
input  [11:0] RADDR;
input  [11:0] WADDR;
input  [31:0] WD;
input         WEN;



output [31:0] RD;



wire          CLK;
wire   [11:0] RADDR;
wire   [31:0] RD_0;
wire   [11:0] WADDR;
wire   [31:0] WD;
wire          WEN;
wire   [31:0] RD_0_net_0;



wire          GND_net;



assign GND_net = 1'b0;



assign RD_0_net_0 = RD_0;
assign RD[31:0]   = RD_0_net_0;




sram_4Kx32_sram_4Kx32_0_TPSRAM sram_4Kx32_0(

        .WD    ( WD ),
        .WADDR ( WADDR ),
        .RADDR ( RADDR ),
        .WEN   ( WEN ),
        .CLK   ( CLK ),

        .RD    ( RD_0 ) 
        );


endmodule