data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_top.v
 line:47: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_top.v:43: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD/2) \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_top.v:49: Unsupported: Ignoring delay on this delayed statement.\n                repeat(5) #150 begin  \n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_top.v:48: Unsupported: Ignoring delay on this delayed statement.\n            repeat(2) #150 begin  \n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_top.v:47: Unsupported: Ignoring delay on this delayed statement.\n        repeat(2) #150 begin  \n                  ^\n%Error: data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches/tb_top.v:32: Cannot find file containing module: \'top\'\n    top #(1) utt\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches,data/full_repos/permissive/212763527/top\n             data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches,data/full_repos/permissive/212763527/top.v\n             data/full_repos/permissive/212763527/school_project/6_adder_subtractor/testbenches,data/full_repos/permissive/212763527/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top;

    reg clk;


    reg[3:0] a;
    reg[3:0] b;
    reg add_sub_signal;
    reg[1:0] operand_control;


    wire[11:0] DISP;

    initial begin
        clk = 0;
        a = 0;
        b = 0;
        add_sub_signal = 0;
        operand_control = 0;
    end
    
    top #(1) utt
    (
        .CLK (clk),
        .a(a),
        .b(b),
        .add_sub_signal(add_sub_signal),
        .operand_control(operand_control),
        .DISP(DISP)
    );

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;

    initial begin
        repeat(2) #150 begin
            repeat(2) #150 begin
                repeat(5) #150 begin
                    a = a + 5;
                    b = b + 1;
                end
                operand_control = operand_control + 1;
            end
            add_sub_signal = 1;
        end

        $finish;
    end

endmodule
module tb_top;


    reg clk;


    reg[3:0] a;
    reg[3:0] b;
    reg add_sub_signal;
    reg[1:0] operand_control;


    wire[11:0] DISP;

    initial begin
        clk = 0;
        a = 0;
        b = 0;
        add_sub_signal = 0;
        operand_control = 0;
    end
    
    top #(1) utt
    (
        .CLK (clk),
        .a(a),
        .b(b),
        .add_sub_signal(add_sub_signal),
        .operand_control(operand_control),
        .DISP(DISP)
    );

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;

    initial begin
        repeat(2) #150 begin
            repeat(2) #150 begin
                repeat(5) #150 begin
                    a = a + 5;
                    b = b + 1;
                end
                operand_control = operand_control + 1;
            end
            add_sub_signal = 1;
        end

        $finish;
    end

endmodule