data/full_repos/permissive/127511545/src/WriteBackForwardUnit.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/WriteBackForwardUnit.v:44: Signal definition not found, creating implicitly: \'OrAddress\'\n                                                                                     : ... Suggested alternative: \'XorAddress\'\n or #(50) o0(OrAddress, XorAddress[4], XorAddress[3], XorAddress[2], XorAddress[1], XorAddress[0]);\n             ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/127511545/src/WriteBackForwardUnit.v:17: Signal definition not found, creating implicitly: \'OrOutput1\'\n or #(50) o0(OrOutput1, WriteRegister[4], WriteRegister[3], WriteRegister[2], WriteRegister[1], WriteRegister[0]);\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/127511545/src/WriteBackForwardUnit.v:24: Cannot find file containing module: \'MUX2x32to32\'\n MUX2x32to32 mux0(ReadData1Output, ReadData1, WriteData, ReadSourceRs);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/MUX2x32to32\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/MUX2x32to32.v\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/MUX2x32to32.sv\n             MUX2x32to32\n             MUX2x32to32.v\n             MUX2x32to32.sv\n             obj_dir/MUX2x32to32\n             obj_dir/MUX2x32to32.v\n             obj_dir/MUX2x32to32.sv\n%Error: data/full_repos/permissive/127511545/src/WriteBackForwardUnit.v:25: Cannot find file containing module: \'MUX2x32to32\'\n MUX2x32to32 mux1(ReadData2Output, ReadData2, WriteData, ReadSourceRt);\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module WBForward(ReadData1Output, ReadData2Output, ReadData1, ReadData2, Rs, Rt, WriteRegister, WriteData, RegisterWrite);

	output[31:0] ReadData1Output, ReadData2Output;
	input[31:0] ReadData1, ReadData2, WriteData;
	input[4:0] Rs, Rt, WriteRegister;
	input RegisterWrite;
	wire ReadSourceRs, ReadSourceRt;
	wire CompareOutput1, CompareOutput2;


	or #(50) o0(OrOutput1, WriteRegister[4], WriteRegister[3], WriteRegister[2], WriteRegister[1], WriteRegister[0]);
	CompareAddress Compare1(CompareOutput1, WriteRegister, Rs);
	and #(50) a0(ReadSourceRs, RegisterWrite, OrOutput1, CompareOutput1);

	CompareAddress Compare2(CompareOutput2, WriteRegister, Rt);
	and #(50) a1(ReadSourceRt, RegisterWrite, OrOutput1, CompareOutput2);

	MUX2x32to32 mux0(ReadData1Output, ReadData1, WriteData, ReadSourceRs);
	MUX2x32to32 mux1(ReadData2Output, ReadData2, WriteData, ReadSourceRt);

endmodule
module WBForward(ReadData1Output, ReadData2Output, ReadData1, ReadData2, Rs, Rt, WriteRegister, WriteData, RegisterWrite);


	output[31:0] ReadData1Output, ReadData2Output;
	input[31:0] ReadData1, ReadData2, WriteData;
	input[4:0] Rs, Rt, WriteRegister;
	input RegisterWrite;
	wire ReadSourceRs, ReadSourceRt;
	wire CompareOutput1, CompareOutput2;


	or #(50) o0(OrOutput1, WriteRegister[4], WriteRegister[3], WriteRegister[2], WriteRegister[1], WriteRegister[0]);
	CompareAddress Compare1(CompareOutput1, WriteRegister, Rs);
	and #(50) a0(ReadSourceRs, RegisterWrite, OrOutput1, CompareOutput1);

	CompareAddress Compare2(CompareOutput2, WriteRegister, Rt);
	and #(50) a1(ReadSourceRt, RegisterWrite, OrOutput1, CompareOutput2);

	MUX2x32to32 mux0(ReadData1Output, ReadData1, WriteData, ReadSourceRs);
	MUX2x32to32 mux1(ReadData2Output, ReadData2, WriteData, ReadSourceRt);

endmodule