data/full_repos/permissive/120024308/src/LCDController/counter.v
data/verilator_xmls/8d8c1acb-4de8-4b84-a3fb-d32955ef8871.xml
module Counter(
               input wire clk,
               input wire reset,
               output reg [19:0] count
               );
   always @(posedge clk)
     begin
        if(reset)
          begin
             count <= 0;
          end
        else
          begin
             count <= count+1;
          end
     end
endmodule
module Counter(
               input wire clk,
               input wire reset,
               output reg [19:0] count
               );

   always @(posedge clk)
     begin
        if(reset)
          begin
             count <= 0;
          end
        else
          begin
             count <= count+1;
          end
     end
endmodule