data/full_repos/permissive/202032771/vmod/cnnip_v1_0_S00_AXI.v
 line:24: before: "."
1: b'%Warning-MULTITOP: data/full_repos/permissive/202032771/vmod/cnnip_v1_0_S00_AXI.v:24: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                    : ... Top module \'cnnip_v1_0_S00_AXI\'\nmodule cnnip_v1_0_S00_AXI #\n       ^~~~~~~~~~~~~~~~~~\n                                                                                    : ... Top module \'cnnip_mem_if\'\n  cnnip_mem_if.master int_mem_if,\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/202032771/vmod/cnnip_v1_0_S00_AXI.v:24: Unsupported: Interfaced port on top level module\n  cnnip_mem_if.master int_mem_if,\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/202032771/vmod/cnnip_v1_0_S00_AXI.v:24: Cannot find file containing interface: \'cnnip_mem_if\'\n  cnnip_mem_if.master int_mem_if,\n  ^~~~~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/202032771/vmod/cnnip_v1_0_S00_AXI.v:24: ../V3LinkDot.cpp:2055: Unlinked interface\n  cnnip_mem_if.master int_mem_if,\n  ^~~~~~~~~~~~\n'
module cnnip_v1_0_S00_AXI #
(






  parameter integer C_S_AXI_DATA_WIDTH	= 32,

  parameter integer C_S_AXI_ADDR_WIDTH	= 16
)
(

  cnnip_mem_if.master int_mem_if,




  input wire  S_AXI_ACLK,

  input wire  S_AXI_ARESETN,

  input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



  input wire [2 : 0] S_AXI_AWPROT,


  input wire  S_AXI_AWVALID,


  output wire  S_AXI_AWREADY,

  input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



  input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


  input wire  S_AXI_WVALID,


  output wire  S_AXI_WREADY,


  output wire [1 : 0] S_AXI_BRESP,


  output wire  S_AXI_BVALID,


  input wire  S_AXI_BREADY,

  input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



  input wire [2 : 0] S_AXI_ARPROT,


  input wire  S_AXI_ARVALID,


  output wire  S_AXI_ARREADY,

  output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


  output wire [1 : 0] S_AXI_RRESP,


  output wire  S_AXI_RVALID,


  input wire  S_AXI_RREADY
);


reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
reg  														axi_awready;
reg  														axi_wready;
reg [1 : 0] 										axi_bresp;
reg  														axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
reg  														axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
reg [1 : 0] 										axi_rresp;
reg  														axi_rvalid;

















wire	 slv_reg_rden;
wire	 slv_reg_wren;


reg	 aw_en;



assign S_AXI_AWREADY	= axi_awready;
assign S_AXI_WREADY  	= axi_wready;
assign S_AXI_BRESP	  = axi_bresp;
assign S_AXI_BVALID	  = axi_bvalid;
assign S_AXI_ARREADY	= axi_arready;
assign S_AXI_RDATA	  = axi_rdata;
assign S_AXI_RRESP	  = axi_rresp;
assign S_AXI_RVALID	  = axi_rvalid;











always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_awready <= 1'b0;
      aw_en <= 1'b1;
    end
  else
    begin
      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
      begin








        axi_awready <= 1'b1;
        aw_en <= 1'b0;
      end
      else if (S_AXI_BREADY && axi_bvalid)
      begin
        aw_en <= 1'b1;
        axi_awready <= 1'b0;
      end
      else
      begin
        axi_awready <= 1'b0;
      end
    end
end




always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_awaddr <= 0;
    end
  else
    begin
      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
        begin

          axi_awaddr <= S_AXI_AWADDR;
        end
    end
end





always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_wready <= 1'b0;
    end
  else
    begin
      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
        begin




          axi_wready <= 1'b1;
        end
      else
        begin
          axi_wready <= 1'b0;
        end
    end
end









assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;







always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_bvalid  <= 0;
      axi_bresp   <= 2'b0;
    end
  else
    begin
      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
        begin

          axi_bvalid <= 1'b1;
          axi_bresp  <= 2'b0;
        end
      else
        begin
          if (S_AXI_BREADY && axi_bvalid)


            begin
              axi_bvalid <= 1'b0;
            end
        end
    end
end








always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_arready <= 1'b0;
      axi_araddr  <= 32'b0;
    end
  else
    begin
      if (~axi_arready && S_AXI_ARVALID)
        begin

          axi_arready <= 1'b1;

          axi_araddr  <= S_AXI_ARADDR;
        end
      else
        begin
          axi_arready <= 1'b0;
        end
    end
end









always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_rvalid <= 0;
      axi_rresp  <= 0;
    end
  else
    begin
      if (int_mem_if.valid && ~axi_rvalid)
      begin

        axi_rvalid <= 1'b1;
        axi_rresp  <= 2'b0;
      end
      else if (axi_rvalid && S_AXI_RREADY)
      begin

        axi_rvalid <= 1'b0;
      end

    end
end




assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;

assign int_mem_if.en = slv_reg_wren | slv_reg_rden;
assign int_mem_if.we = (slv_reg_wren==1'b1) ? S_AXI_WSTRB : 4'b0;
assign int_mem_if.din = S_AXI_WDATA;

wire [1:0] select = {slv_reg_wren, slv_reg_rden};

always @ (*)
begin
  int_mem_if.addr = axi_araddr;
  case(select)
    1'b1 << 0: int_mem_if.addr = axi_araddr;
    1'b1 << 1: int_mem_if.addr = axi_awaddr;
  endcase
end


always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_rdata  <= 0;
    end
  else
    begin



      if (int_mem_if.valid)
        begin
          axi_rdata <= int_mem_if.dout;
        end
    end
end

endmodule
module cnnip_v1_0_S00_AXI #
(






  parameter integer C_S_AXI_DATA_WIDTH	= 32,

  parameter integer C_S_AXI_ADDR_WIDTH	= 16
)
(

  cnnip_mem_if.master int_mem_if,




  input wire  S_AXI_ACLK,

  input wire  S_AXI_ARESETN,

  input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



  input wire [2 : 0] S_AXI_AWPROT,


  input wire  S_AXI_AWVALID,


  output wire  S_AXI_AWREADY,

  input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



  input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


  input wire  S_AXI_WVALID,


  output wire  S_AXI_WREADY,


  output wire [1 : 0] S_AXI_BRESP,


  output wire  S_AXI_BVALID,


  input wire  S_AXI_BREADY,

  input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



  input wire [2 : 0] S_AXI_ARPROT,


  input wire  S_AXI_ARVALID,


  output wire  S_AXI_ARREADY,

  output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


  output wire [1 : 0] S_AXI_RRESP,


  output wire  S_AXI_RVALID,


  input wire  S_AXI_RREADY
);



reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
reg  														axi_awready;
reg  														axi_wready;
reg [1 : 0] 										axi_bresp;
reg  														axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
reg  														axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
reg [1 : 0] 										axi_rresp;
reg  														axi_rvalid;

















wire	 slv_reg_rden;
wire	 slv_reg_wren;


reg	 aw_en;



assign S_AXI_AWREADY	= axi_awready;
assign S_AXI_WREADY  	= axi_wready;
assign S_AXI_BRESP	  = axi_bresp;
assign S_AXI_BVALID	  = axi_bvalid;
assign S_AXI_ARREADY	= axi_arready;
assign S_AXI_RDATA	  = axi_rdata;
assign S_AXI_RRESP	  = axi_rresp;
assign S_AXI_RVALID	  = axi_rvalid;











always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_awready <= 1'b0;
      aw_en <= 1'b1;
    end
  else
    begin
      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
      begin








        axi_awready <= 1'b1;
        aw_en <= 1'b0;
      end
      else if (S_AXI_BREADY && axi_bvalid)
      begin
        aw_en <= 1'b1;
        axi_awready <= 1'b0;
      end
      else
      begin
        axi_awready <= 1'b0;
      end
    end
end




always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_awaddr <= 0;
    end
  else
    begin
      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
        begin

          axi_awaddr <= S_AXI_AWADDR;
        end
    end
end





always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_wready <= 1'b0;
    end
  else
    begin
      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
        begin




          axi_wready <= 1'b1;
        end
      else
        begin
          axi_wready <= 1'b0;
        end
    end
end









assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;







always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_bvalid  <= 0;
      axi_bresp   <= 2'b0;
    end
  else
    begin
      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
        begin

          axi_bvalid <= 1'b1;
          axi_bresp  <= 2'b0;
        end
      else
        begin
          if (S_AXI_BREADY && axi_bvalid)


            begin
              axi_bvalid <= 1'b0;
            end
        end
    end
end








always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_arready <= 1'b0;
      axi_araddr  <= 32'b0;
    end
  else
    begin
      if (~axi_arready && S_AXI_ARVALID)
        begin

          axi_arready <= 1'b1;

          axi_araddr  <= S_AXI_ARADDR;
        end
      else
        begin
          axi_arready <= 1'b0;
        end
    end
end









always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_rvalid <= 0;
      axi_rresp  <= 0;
    end
  else
    begin
      if (int_mem_if.valid && ~axi_rvalid)
      begin

        axi_rvalid <= 1'b1;
        axi_rresp  <= 2'b0;
      end
      else if (axi_rvalid && S_AXI_RREADY)
      begin

        axi_rvalid <= 1'b0;
      end

    end
end




assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;

assign int_mem_if.en = slv_reg_wren | slv_reg_rden;
assign int_mem_if.we = (slv_reg_wren==1'b1) ? S_AXI_WSTRB : 4'b0;
assign int_mem_if.din = S_AXI_WDATA;

wire [1:0] select = {slv_reg_wren, slv_reg_rden};

always @ (*)
begin
  int_mem_if.addr = axi_araddr;
  case(select)
    1'b1 << 0: int_mem_if.addr = axi_araddr;
    1'b1 << 1: int_mem_if.addr = axi_awaddr;
  endcase
end


always @( posedge S_AXI_ACLK )
begin
  if ( S_AXI_ARESETN == 1'b0 )
    begin
      axi_rdata  <= 0;
    end
  else
    begin



      if (int_mem_if.valid)
        begin
          axi_rdata <= int_mem_if.dout;
        end
    end
end

endmodule