data/full_repos/permissive/195073547/verilog_source/add_2_1/xpm_memory_tdpram_yosys.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/195073547/verilog_source/add_2_1/xpm_memory_tdpram_yosys.v:102: Cannot find file containing module: 'RAMB36E1'\nRAMB36E1 # (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/195073547/verilog_source/add_2_1,data/full_repos/permissive/195073547/RAMB36E1\n             data/full_repos/permissive/195073547/verilog_source/add_2_1,data/full_repos/permissive/195073547/RAMB36E1.v\n             data/full_repos/permissive/195073547/verilog_source/add_2_1,data/full_repos/permissive/195073547/RAMB36E1.sv\n             RAMB36E1\n             RAMB36E1.v\n             RAMB36E1.sv\n             obj_dir/RAMB36E1\n             obj_dir/RAMB36E1.v\n             obj_dir/RAMB36E1.sv\n%Error: Exiting due to 1 error(s)\n"
module xpm_memory_tdpram_yosys (sleep,
			  clka, rsta, 
			  ena,            
			  regcea,         
			  wea,            
			  addra,          
			  dina,           
			  injectsbiterra,
			  injectdbiterra, 
			  douta,
			  sbiterra,       
			  dbiterra,       
			  clkb,           
			  rstb,           
			  enb,            
			  regceb,         
			  web,            
			  addrb,          
			  dinb,           
			  injectsbiterrb, 
			  injectdbiterrb, 
			  doutb,          
			  sbiterrb,       
			  dbiterrb);       

parameter DWIDTH = 8;
parameter AWIDTH = 9;
parameter MEM_SIZE = 500;


parameter MEMORY_SIZE=512;
parameter MEMORY_PRIMITIVE="block";
parameter CLOCKING_MODE="independent_clock";
parameter MEMORY_INIT_FILE="none";
parameter MEMORY_INIT_PARAM  =""    ;
parameter USE_MEM_INIT       =1;
parameter WAKEUP_TIME        ="disable_sleep";
parameter MESSAGE_CONTROL    =0;
parameter ECC_MODE           ="no_ecc";
parameter AUTO_SLEEP_TIME    =0;


parameter WRITE_DATA_WIDTH_A =64;
parameter READ_DATA_WIDTH_A  =64;
parameter BYTE_WRITE_WIDTH_A =64;
parameter ADDR_WIDTH_A       =10;
parameter READ_RESET_VALUE_A ="0";
parameter READ_LATENCY_A     =1;
parameter WRITE_MODE_A       ="write_first";


parameter WRITE_DATA_WIDTH_B =64;
parameter READ_DATA_WIDTH_B  =64;
parameter BYTE_WRITE_WIDTH_B =64;
parameter ADDR_WIDTH_B       =10;
parameter READ_RESET_VALUE_B ="0";
parameter READ_LATENCY_B     =1;
parameter WRITE_MODE_B       ="write_first";




input sleep;

input clka;
input rsta;
input ena;
input regcea;
input wea;
input [ADDR_WIDTH_A-1:0] addra;
input [WRITE_DATA_WIDTH_A-1:0] dina;
input injectsbiterra;
input injectdbiterra;
output [READ_DATA_WIDTH_A-1:0] douta;
input sbiterra;
input dbiterra;

input clkb;
input rstb;
input enb; 
input regceb; 
input web;
input [ADDR_WIDTH_B-1:0] addrb;
input [WRITE_DATA_WIDTH_B-1:0] dinb;
input injectsbiterrb;
input injectdbiterrb;
output [READ_DATA_WIDTH_B-1:0] doutb;
input sbiterrb;
input dbiterrb;

wire [2:0] tmpa;
wire [2:0] tmpb;

RAMB36E1 # (

	    .IS_CLKARDCLK_INVERTED(0),
	    .IS_CLKBWRCLK_INVERTED(0),
	    .IS_ENARDEN_INVERTED(0),
	    .IS_ENBWREN_INVERTED(0),
	    .IS_RSTRAMARSTRAM_INVERTED(0),
	    .IS_RSTRAMB_INVERTED(0),
	    .IS_RSTREGARSTREG_INVERTED(0),
	    .IS_RSTREGB_INVERTED(0),
	    .DOA_REG(0),
	    .DOB_REG(0),
	    .RAM_MODE("TDP"),

	    .READ_WIDTH_A (READ_DATA_WIDTH_A),
	    .READ_WIDTH_B (READ_DATA_WIDTH_B),
	    .WRITE_WIDTH_A (WRITE_DATA_WIDTH_A),
	    .WRITE_WIDTH_B (WRITE_DATA_WIDTH_B)
	    )
RAMB36E1_inst0 (
		.CLKARDCLK(clka),
		.CLKBWRCLK(clkb),
		.ENARDEN(ena), 
		.ENBWREN(enb), 
		.REGCEAREGCE(regcea),
		.REGCEB(regceb),
		.RSTRAMARSTRAM (rsta),
		.RSTRAMB (rstb),
		.RSTREGARSTREG (rsta),
	        .RSTREGB(rstb),
		.ADDRARDADDR (addra),
		.ADDRBWRADDR (addrb),
		.DIADI (dina[WRITE_DATA_WIDTH_A-2:0]),
		.DIBDI (dinb[WRITE_DATA_WIDTH_B-2:0]),
		.DIPADIP ({3'b000,dina[WRITE_DATA_WIDTH_A-1]}),
		.DIPBDIP ({3'b000,dinb[WRITE_DATA_WIDTH_B-1]}),
		.WEA ({wea,wea,wea,wea}),
		.WEBWE ({web,web,web,web,web,web,web,web}),
		.DOADO (douta[READ_DATA_WIDTH_A-2:0]),
		.DOBDO (doutb[READ_DATA_WIDTH_B-2:0]),
		.DOPADOP ({tmpa[2:0],douta[READ_DATA_WIDTH_A-1]}),
		.DOPBDOP ({tmpb[2:0],doutb[READ_DATA_WIDTH_B-1]})
		);

endmodule
module xpm_memory_tdpram_yosys (sleep,
			  clka, rsta, 
			  ena,            
			  regcea,         
			  wea,            
			  addra,          
			  dina,           
			  injectsbiterra,
			  injectdbiterra, 
			  douta,
			  sbiterra,       
			  dbiterra,       
			  clkb,           
			  rstb,           
			  enb,            
			  regceb,         
			  web,            
			  addrb,          
			  dinb,           
			  injectsbiterrb, 
			  injectdbiterrb, 
			  doutb,          
			  sbiterrb,       
			  dbiterrb);
       

parameter DWIDTH = 8;
parameter AWIDTH = 9;
parameter MEM_SIZE = 500;


parameter MEMORY_SIZE=512;
parameter MEMORY_PRIMITIVE="block";
parameter CLOCKING_MODE="independent_clock";
parameter MEMORY_INIT_FILE="none";
parameter MEMORY_INIT_PARAM  =""    ;
parameter USE_MEM_INIT       =1;
parameter WAKEUP_TIME        ="disable_sleep";
parameter MESSAGE_CONTROL    =0;
parameter ECC_MODE           ="no_ecc";
parameter AUTO_SLEEP_TIME    =0;


parameter WRITE_DATA_WIDTH_A =64;
parameter READ_DATA_WIDTH_A  =64;
parameter BYTE_WRITE_WIDTH_A =64;
parameter ADDR_WIDTH_A       =10;
parameter READ_RESET_VALUE_A ="0";
parameter READ_LATENCY_A     =1;
parameter WRITE_MODE_A       ="write_first";


parameter WRITE_DATA_WIDTH_B =64;
parameter READ_DATA_WIDTH_B  =64;
parameter BYTE_WRITE_WIDTH_B =64;
parameter ADDR_WIDTH_B       =10;
parameter READ_RESET_VALUE_B ="0";
parameter READ_LATENCY_B     =1;
parameter WRITE_MODE_B       ="write_first";




input sleep;

input clka;
input rsta;
input ena;
input regcea;
input wea;
input [ADDR_WIDTH_A-1:0] addra;
input [WRITE_DATA_WIDTH_A-1:0] dina;
input injectsbiterra;
input injectdbiterra;
output [READ_DATA_WIDTH_A-1:0] douta;
input sbiterra;
input dbiterra;

input clkb;
input rstb;
input enb; 
input regceb; 
input web;
input [ADDR_WIDTH_B-1:0] addrb;
input [WRITE_DATA_WIDTH_B-1:0] dinb;
input injectsbiterrb;
input injectdbiterrb;
output [READ_DATA_WIDTH_B-1:0] doutb;
input sbiterrb;
input dbiterrb;

wire [2:0] tmpa;
wire [2:0] tmpb;

RAMB36E1 # (

	    .IS_CLKARDCLK_INVERTED(0),
	    .IS_CLKBWRCLK_INVERTED(0),
	    .IS_ENARDEN_INVERTED(0),
	    .IS_ENBWREN_INVERTED(0),
	    .IS_RSTRAMARSTRAM_INVERTED(0),
	    .IS_RSTRAMB_INVERTED(0),
	    .IS_RSTREGARSTREG_INVERTED(0),
	    .IS_RSTREGB_INVERTED(0),
	    .DOA_REG(0),
	    .DOB_REG(0),
	    .RAM_MODE("TDP"),

	    .READ_WIDTH_A (READ_DATA_WIDTH_A),
	    .READ_WIDTH_B (READ_DATA_WIDTH_B),
	    .WRITE_WIDTH_A (WRITE_DATA_WIDTH_A),
	    .WRITE_WIDTH_B (WRITE_DATA_WIDTH_B)
	    )
RAMB36E1_inst0 (
		.CLKARDCLK(clka),
		.CLKBWRCLK(clkb),
		.ENARDEN(ena), 
		.ENBWREN(enb), 
		.REGCEAREGCE(regcea),
		.REGCEB(regceb),
		.RSTRAMARSTRAM (rsta),
		.RSTRAMB (rstb),
		.RSTREGARSTREG (rsta),
	        .RSTREGB(rstb),
		.ADDRARDADDR (addra),
		.ADDRBWRADDR (addrb),
		.DIADI (dina[WRITE_DATA_WIDTH_A-2:0]),
		.DIBDI (dinb[WRITE_DATA_WIDTH_B-2:0]),
		.DIPADIP ({3'b000,dina[WRITE_DATA_WIDTH_A-1]}),
		.DIPBDIP ({3'b000,dinb[WRITE_DATA_WIDTH_B-1]}),
		.WEA ({wea,wea,wea,wea}),
		.WEBWE ({web,web,web,web,web,web,web,web}),
		.DOADO (douta[READ_DATA_WIDTH_A-2:0]),
		.DOBDO (doutb[READ_DATA_WIDTH_B-2:0]),
		.DOPADOP ({tmpa[2:0],douta[READ_DATA_WIDTH_A-1]}),
		.DOPBDOP ({tmpb[2:0],doutb[READ_DATA_WIDTH_B-1]})
		);

endmodule