data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v
 line:25: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:15: Unsupported: Ignoring delay on this delayed statement.\n #00 rst = 1\'b1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:16: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:21: Unsupported: Ignoring delay on this delayed statement.\n #00  C_DMRead = 1\'b1; C_DMWrite = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:22: Unsupported: Ignoring delay on this delayed statement.\n #200 C_DMRead = 1\'b0; C_DMWrite = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:23: Unsupported: Ignoring delay on this delayed statement.\n #200 C_DMRead = 1\'b0; C_DMWrite = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:24: Unsupported: Ignoring delay on this delayed statement.\n #200 C_DMRead = 1\'b1; C_DMWrite = 1\'b1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:25: Unsupported: Ignoring delay on this delayed statement.\n #200 $stop;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:30: Unsupported: Ignoring delay on this delayed statement.\n #00 A_DataAddress <= 16\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:31: Unsupported: Ignoring delay on this delayed statement.\n #50 A_DataAddress <= 16\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:32: Unsupported: Ignoring delay on this delayed statement.\n #50 A_DataAddress <= 16\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:33: Unsupported: Ignoring delay on this delayed statement.\n #50 A_DataAddress <= 16\'d2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:38: Unsupported: Ignoring delay on this delayed statement.\n #00  D_WriteData = 16\'d20;\n ^\n%Error: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:43: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dataMemory.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:44: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/126791278/testbenches/tb_dataMemory.v:49: Unsupported or unknown PLI call: $monitor\n $monitor("time=%3d, D_Data=%16h, D_WriteData=%16h, A_DataAddress=%16h", $time, D_Data, D_WriteData, A_DataAddress);\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_dataMemory();

reg [15:0] A_DataAddress;
reg [15:0] D_WriteData;
reg C_DMRead, C_DMWrite, rst;
wire [15:0] D_Data;

dataMemory uut (D_Data,	A_DataAddress,D_WriteData,C_DMRead, C_DMWrite, rst);



initial
begin
	#00 rst = 1'b1;
	#30 rst = 1'b0;
end

initial
begin
	#00  C_DMRead = 1'b1; C_DMWrite = 1'b0;
	#200 C_DMRead = 1'b0; C_DMWrite = 1'b1;
	#200 C_DMRead = 1'b0; C_DMWrite = 1'b0;
	#200 C_DMRead = 1'b1; C_DMWrite = 1'b1; 
	#200 $stop;
end

initial
begin
	#00 A_DataAddress <= 16'd0;
	#50 A_DataAddress <= 16'd1;
	#50 A_DataAddress <= 16'd1;
	#50 A_DataAddress <= 16'd2;
end

initial
begin
	#00  D_WriteData = 16'd20;
end

initial
begin
	$dumpfile("dataMemory.vcd");
	$dumpvars;
end

initial
begin
	$monitor("time=%3d, D_Data=%16h, D_WriteData=%16h, A_DataAddress=%16h", $time, D_Data, D_WriteData, A_DataAddress);
end

endmodule
module tb_dataMemory();


reg [15:0] A_DataAddress;
reg [15:0] D_WriteData;
reg C_DMRead, C_DMWrite, rst;
wire [15:0] D_Data;

dataMemory uut (D_Data,	A_DataAddress,D_WriteData,C_DMRead, C_DMWrite, rst);



initial
begin
	#00 rst = 1'b1;
	#30 rst = 1'b0;
end

initial
begin
	#00  C_DMRead = 1'b1; C_DMWrite = 1'b0;
	#200 C_DMRead = 1'b0; C_DMWrite = 1'b1;
	#200 C_DMRead = 1'b0; C_DMWrite = 1'b0;
	#200 C_DMRead = 1'b1; C_DMWrite = 1'b1; 
	#200 $stop;
end

initial
begin
	#00 A_DataAddress <= 16'd0;
	#50 A_DataAddress <= 16'd1;
	#50 A_DataAddress <= 16'd1;
	#50 A_DataAddress <= 16'd2;
end

initial
begin
	#00  D_WriteData = 16'd20;
end

initial
begin
	$dumpfile("dataMemory.vcd");
	$dumpvars;
end

initial
begin
	$monitor("time=%3d, D_Data=%16h, D_WriteData=%16h, A_DataAddress=%16h", $time, D_Data, D_WriteData, A_DataAddress);
end

endmodule