data/full_repos/permissive/14193640/fpga/binary_counter.v
data/verilator_xmls/124faaf5-0423-4f32-b3e0-8d4fe99f6a31.xml
module binary_counter
  #(parameter N=8, MAX_COUNT=255)
   (
    input clk,
    input reset_n,
    output [N-1:0] count
   );

   reg [N-1:0]     count_reg, next_count;

   always @(posedge clk, negedge reset_n)
     if (!reset_n) 
       count_reg <= 0;
     else
       count_reg <= next_count;

   always @(*)
     begin
        next_count = count_reg + 1'b1;
        if (next_count > MAX_COUNT)
          next_count = 0;
     end

   assign count = count_reg;

endmodule
module binary_counter
  #(parameter N=8, MAX_COUNT=255)
   (
    input clk,
    input reset_n,
    output [N-1:0] count
   );


   reg [N-1:0]     count_reg, next_count;

   always @(posedge clk, negedge reset_n)
     if (!reset_n) 
       count_reg <= 0;
     else
       count_reg <= next_count;

   always @(*)
     begin
        next_count = count_reg + 1'b1;
        if (next_count > MAX_COUNT)
          next_count = 0;
     end

   assign count = count_reg;

endmodule