data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/buf87.v
data/verilator_xmls/85c54373-5820-469c-b67f-c37e1decda10.xml
module buf87(
    input [31:0] a,
    input clk,
    output reg [31:0] a1
    );

always @(negedge clk) begin
a1<=a;
end
endmodule
module buf87(
    input [31:0] a,
    input clk,
    output reg [31:0] a1
    );


always @(negedge clk) begin
a1<=a;
end
endmodule