data/full_repos/permissive/179227721/mid/Cla.v
data/verilator_xmls/07e88310-fbcf-4a06-bf2c-902bd519f241.xml
module Cla(

           input        cin,
           input [3:0]  num1,
           input [3:0]  num2,
           output [3:0] out,
           output       car);
   wire [3:0] x1;
   wire [3:0] x2;
   wire [3:0] y;
   wire       c;
   wire       ci;

   wire [2:0] wc;
   wire [3:0] p;
   wire [3:0] g;

   assign c = g[3]||(p[3]&&wc[2]);
   assign y = {p[3]^wc[2], p[2]^wc[1], p[1]^wc[0], p[0]^ci};


   assign p = {x1[3]^x2[3], x1[2]^x2[2], x1[1]^x2[1], x1[0]^x2[0]};
   assign g = {x1[3]&&x2[3], x1[2]&&x2[2], x1[1]&&x2[1], x1[0]&&x2[0]};

   assign wc[0] = g[0]||(p[0]&&ci);
   assign wc[1] = g[1]||(p[1]&&wc[0]);
   assign wc[2] = g[2]||(p[2]&&wc[1]);

   assign x1[3:0] = num1[3:0];
   assign x2[3:0] = num2[3:0];
   assign out[3:0] = y[3:0];
   assign car = c;
   assign ci = cin;

`ifdef FORMAL
   assert property ( cin + num1 + num2 == {car, out});
`endif


endmodule
module Cla(

           input        cin,
           input [3:0]  num1,
           input [3:0]  num2,
           output [3:0] out,
           output       car);

   wire [3:0] x1;
   wire [3:0] x2;
   wire [3:0] y;
   wire       c;
   wire       ci;

   wire [2:0] wc;
   wire [3:0] p;
   wire [3:0] g;

   assign c = g[3]||(p[3]&&wc[2]);
   assign y = {p[3]^wc[2], p[2]^wc[1], p[1]^wc[0], p[0]^ci};


   assign p = {x1[3]^x2[3], x1[2]^x2[2], x1[1]^x2[1], x1[0]^x2[0]};
   assign g = {x1[3]&&x2[3], x1[2]&&x2[2], x1[1]&&x2[1], x1[0]&&x2[0]};

   assign wc[0] = g[0]||(p[0]&&ci);
   assign wc[1] = g[1]||(p[1]&&wc[0]);
   assign wc[2] = g[2]||(p[2]&&wc[1]);

   assign x1[3:0] = num1[3:0];
   assign x2[3:0] = num2[3:0];
   assign out[3:0] = y[3:0];
   assign car = c;
   assign ci = cin;

`ifdef FORMAL
   assert property ( cin + num1 + num2 == {car, out});
`endif


endmodule