data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/ddr_ctrl_wrapper.v
1: b'%Warning-WIDTH: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/ddr_ctrl_wrapper.v:68: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s SEL generates 23 bits.\n                                                                                                                                      : ... In instance ddr_ctrl_wrapper\n assign local_address_o = we_i ? adr_i[LOCAL_ADR_WIDTH+1:2] : adr_i[LOCAL_ADR_WIDTH+1:2] & ~get_mask(buf_width_i);\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/ddr_ctrl_wrapper.v:68: Operator AND expects 32 bits on the LHS, but LHS\'s SEL generates 23 bits.\n                                                                                                                                      : ... In instance ddr_ctrl_wrapper\n assign local_address_o = we_i ? adr_i[LOCAL_ADR_WIDTH+1:2] : adr_i[LOCAL_ADR_WIDTH+1:2] & ~get_mask(buf_width_i);\n                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/ddr_ctrl_wrapper.v:68: Operator ASSIGNW expects 23 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                                      : ... In instance ddr_ctrl_wrapper\n assign local_address_o = we_i ? adr_i[LOCAL_ADR_WIDTH+1:2] : adr_i[LOCAL_ADR_WIDTH+1:2] & ~get_mask(buf_width_i);\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/rtl/verilog/ddr_ctrl_wrapper.v:106: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h1\' generates 6 bits.\n                                                                                                                                       : ... In instance ddr_ctrl_wrapper\n   local_size  <= 6\'b1;\n               ^~\n%Error: Exiting due to 4 warning(s)\n'
function [31:0] get_mask;
	input [3:0] width;
		begin
			get_mask = ((1 << (width)) - 1);
		end
	endfunction
function [31:0] get_mask;

	input [3:0] width;
		begin
			get_mask = ((1 << (width)) - 1);
		end
	endfunction