data/full_repos/permissive/169526487/verilog-codes/array-multiplication.v
data/verilator_xmls/ad8e1edd-5799-49ba-8456-da96c37ad30f.xml
module ha(input e, input f,
output wire g, output wire h);

assign g=e^f; assign h=e*f; endmodule
module ha(input e, input f,
output wire g, output wire h);


assign g=e^f; assign h=e*f; endmodule