data/full_repos/permissive/167489907/Memory/ROM/rom_case_test.v
data/verilator_xmls/4c57f3ef-82fd-4e1a-ab09-e9e11852a1ec.xml
module rom_case(out, address);
	output reg [31:0] out;
	input  [15:0] address;
	always @(address) begin
		case (address)
			16'h0000:  out = 32'b11010010100000000000000000100001;
			16'h0001:  out = 32'b11010010100000000000000001000010;
			16'h0002:  out = 32'b10001011000000100000000000100100;
			16'h0003:  out = 32'b11111000000000010000001111100100;
			16'h0004:  out = 32'b11111000010000010000001111100101;
			16'h0005:  out = 32'b10010100000000000000000000001010;
			16'h0006:  out = 32'b10110101000000000000000000100010;
			16'h0007:  out = 32'b00010100000000000000000000000001;
			16'h0008:  out = 32'b00010111111111111111111111111001;
			16'h0009:  out = 32'b10110100000000000000000001100001;
			16'h000a:  out = 32'b11101011000000100000000000111111;
			16'h000b:  out = 32'b01010100000000000000000000100011;
			16'h000c:  out = 32'b11111000000000001000001111100001;
			16'h000d:  out = 32'b11111000010000001000001111100110;
			16'h000e:  out = 32'b11010010000000000000010011100111;
			16'h000f:  out = 32'b00010111111111111111111111111110;
			16'h0010:  out = 32'b10010001000000000000100000100001;
			16'h0011:  out = 32'b11010001000000000000010001000010;
			16'h0012:  out = 32'b11010110000000000000001111000000;
			default: out=32'hD60003E0;
		endcase
	end
endmodule
module rom_case(out, address);

	output reg [31:0] out;
	input  [15:0] address;
	always @(address) begin
		case (address)
			16'h0000:  out = 32'b11010010100000000000000000100001;
			16'h0001:  out = 32'b11010010100000000000000001000010;
			16'h0002:  out = 32'b10001011000000100000000000100100;
			16'h0003:  out = 32'b11111000000000010000001111100100;
			16'h0004:  out = 32'b11111000010000010000001111100101;
			16'h0005:  out = 32'b10010100000000000000000000001010;
			16'h0006:  out = 32'b10110101000000000000000000100010;
			16'h0007:  out = 32'b00010100000000000000000000000001;
			16'h0008:  out = 32'b00010111111111111111111111111001;
			16'h0009:  out = 32'b10110100000000000000000001100001;
			16'h000a:  out = 32'b11101011000000100000000000111111;
			16'h000b:  out = 32'b01010100000000000000000000100011;
			16'h000c:  out = 32'b11111000000000001000001111100001;
			16'h000d:  out = 32'b11111000010000001000001111100110;
			16'h000e:  out = 32'b11010010000000000000010011100111;
			16'h000f:  out = 32'b00010111111111111111111111111110;
			16'h0010:  out = 32'b10010001000000000000100000100001;
			16'h0011:  out = 32'b11010001000000000000010001000010;
			16'h0012:  out = 32'b11010110000000000000001111000000;
			default: out=32'hD60003E0;
		endcase
	end
endmodule