data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v
 line:86: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 rst = 1\'b1;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #160 bit_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #4000 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:89: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clock=~clock;  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #9 stick=~stick;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #1 stick=~stick;\n        ^\n%Error: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_rx.v:96: Cannot find file containing module: \'uart_rx\'\nuart_rx\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP2-UART-2019/Test,data/full_repos/permissive/206437232/uart_rx\n             data/full_repos/permissive/206437232/TP2-UART-2019/Test,data/full_repos/permissive/206437232/uart_rx.v\n             data/full_repos/permissive/206437232/TP2-UART-2019/Test,data/full_repos/permissive/206437232/uart_rx.sv\n             uart_rx\n             uart_rx.v\n             uart_rx.sv\n             obj_dir/uart_rx\n             obj_dir/uart_rx.v\n             obj_dir/uart_rx.sv\n%Error: Exiting due to 1 error(s), 29 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_rx();

    parameter DBIT_TEST     = 8;
    parameter SB_TICK_TEST  = 16;
    


    

    reg                         clock;
    reg                         stick;
    reg                         bit_rx;
    reg                         rst;
    wire    [DBIT_TEST - 1: 0 ] d_out;
    wire                        rx_done;

    initial begin
        clock = 1'b0;
        stick = 1'b0;
        rst = 1'b0;
        bit_rx = 1'b1;
        #10 rst = 1'b1;
        


        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        #160 bit_rx = 1'b0;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b1;


        #160 bit_rx = 1'b0;
        
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        #160 bit_rx = 1'b0;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        
        #160 bit_rx = 1'b1;


        



        
        
        #4000 $finish;
    end
    
    always #1 clock=~clock;
    always begin
        #9 stick=~stick;
        #1 stick=~stick;
    end
    

uart_rx
    #(
         .DBIT (DBIT_TEST),
         .SB_TICK(SB_TICK_TEST)
     ) 
    u_rx_1
    (
      .s_tick (stick),
      .rx (bit_rx),
      .i_reset (rst),
      .i_clk (clock),
      .rx_done_tick (rx_done),
      .o_data_out (d_out)
    );

endmodule
module tb_rx();


    parameter DBIT_TEST     = 8;
    parameter SB_TICK_TEST  = 16;
    


    

    reg                         clock;
    reg                         stick;
    reg                         bit_rx;
    reg                         rst;
    wire    [DBIT_TEST - 1: 0 ] d_out;
    wire                        rx_done;

    initial begin
        clock = 1'b0;
        stick = 1'b0;
        rst = 1'b0;
        bit_rx = 1'b1;
        #10 rst = 1'b1;
        


        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        #160 bit_rx = 1'b0;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b1;


        #160 bit_rx = 1'b0;
        
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        #160 bit_rx = 1'b0;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b1;
        #160 bit_rx = 1'b0;
        
        #160 bit_rx = 1'b1;


        



        
        
        #4000 $finish;
    end
    
    always #1 clock=~clock;
    always begin
        #9 stick=~stick;
        #1 stick=~stick;
    end
    

uart_rx
    #(
         .DBIT (DBIT_TEST),
         .SB_TICK(SB_TICK_TEST)
     ) 
    u_rx_1
    (
      .s_tick (stick),
      .rx (bit_rx),
      .i_reset (rst),
      .i_clk (clock),
      .rx_done_tick (rx_done),
      .o_data_out (d_out)
    );

endmodule