data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/satprotect.v
data/verilator_xmls/578ab853-b3ea-41b5-998f-a1debd8ed321.xml
module satprotect #(
   parameter     Ri  = 15, 
   parameter     Ro  = 14,
   parameter     SAT = 14
)
(

    input  signed [Ri-1:0] in,
    output signed [Ro-1:0] out
    );
    
    wire pos_sat, neg_sat;
    
    assign pos_sat = ( ~in[Ri-1] ) & (     |in[Ri-2:SAT-1]  );
    assign neg_sat = (  in[Ri-1] ) & ( ~ ( &in[Ri-2:SAT-1] ) );
    
    generate
      if (SAT<Ro)
        assign out = (pos_sat|neg_sat) ? { in[Ri-1] , {Ro-SAT+1{in[Ri-1]}} , {SAT-2{~in[Ri-1]}} }  :  in[Ro-1:0] ;
      else
        assign out = (pos_sat|neg_sat) ? { in[Ri-1] , {Ro-1{~in[Ri-1]}} }  :  in[Ro-1:0] ;
    endgenerate
    
endmodule
module satprotect #(
   parameter     Ri  = 15, 
   parameter     Ro  = 14,
   parameter     SAT = 14
)
(

    input  signed [Ri-1:0] in,
    output signed [Ro-1:0] out
    );

    
    wire pos_sat, neg_sat;
    
    assign pos_sat = ( ~in[Ri-1] ) & (     |in[Ri-2:SAT-1]  );
    assign neg_sat = (  in[Ri-1] ) & ( ~ ( &in[Ri-2:SAT-1] ) );
    
    generate
      if (SAT<Ro)
        assign out = (pos_sat|neg_sat) ? { in[Ri-1] , {Ro-SAT+1{in[Ri-1]}} , {SAT-2{~in[Ri-1]}} }  :  in[Ro-1:0] ;
      else
        assign out = (pos_sat|neg_sat) ? { in[Ri-1] , {Ro-1{~in[Ri-1]}} }  :  in[Ro-1:0] ;
    endgenerate
    
endmodule