data/full_repos/permissive/169225814/modules/ahb_ic/rtl/ahb_ic.v
 line:56: before: "["
1: b'%Warning-WIDTH: data/full_repos/permissive/169225814/modules/ahb_ic/rtl/ahb_ic.v:198: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                    : ... In instance ahb_ic\n        hsize_s[s]   = 1\'b0;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169225814/modules/ahb_ic/rtl/ahb_ic.v:263: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                    : ... In instance ahb_ic\n        hresp_m[m]  = 32\'b0;\n                    ^\n%Error: Exiting due to 2 warning(s)\n'
module ahb_ic #(
  parameter NUM_SLAVES   = 2,
  parameter NUM_MASTERS  = 2,
  parameter [31:0] SLAVE_BASE [NUM_SLAVES-1 :0]   ='{
                                                     32'h4003_0000,
                                                     32'h4002_0000}
)(  

  input  wire         hclk,
  input  wire         hresetn,

  input   wire [ 1:0] htrans_m[NUM_MASTERS-1 :0],
  input   wire [31:0] haddr_m[NUM_MASTERS-1 :0],
  input   wire [ 2:0] hsize_m[NUM_MASTERS-1 :0],
  input   wire [31:0] hwdata_m[NUM_MASTERS-1 :0],
  input   wire        hwrite_m[NUM_MASTERS-1 :0],
  output  reg  [31:0] hrdata_m[NUM_MASTERS-1 :0],
  output  reg         hready_m[NUM_MASTERS-1 :0],
  output  reg         hresp_m[NUM_MASTERS-1 :0],

  output  reg         hsel_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] haddr_s[NUM_SLAVES-1 :0],
  output  reg  [ 2:0] hsize_s[NUM_SLAVES-1 :0],
  output  reg         hwrite_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] hwdata_s[NUM_SLAVES-1 :0],
  input   wire [31:0] hrdata_s[NUM_SLAVES-1 :0],
  input   wire        hready_s[NUM_SLAVES-1 :0],
  input   wire        hresp_s[NUM_SLAVES-1 :0]
);


  wire [31 :0]            slave_base[NUM_SLAVES-1 :0];

  wire                    vlaid_trans_s_by_m[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  wire                    hsel_s_by_m[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  wire                    hsel_s_by_hpm[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  wire [31 :0]            haddr_s_by_m[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  wire [2 :0]             hsize_s_by_m[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  wire                    hwrite_s_by_m[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  wire [31 :0]            hwdata_s_by_m[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];

  wire                   latch_addr_ctl[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  reg                    hsel_s_by_lpm_lat[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  reg [31 :0]            haddr_s_by_lpm_lat[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  reg [2 :0]             hsize_s_by_lpm_lat[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  reg                    hwrite_s_by_lpm_lat[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];

  reg                     hsel_s_by_m_lat[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  reg  [31 :0]            hwdata_s_by_m_lat[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];


















  genvar s,m;




 
  assign slave_base  = SLAVE_BASE;
  generate
    for (s=0; s<NUM_SLAVES; s=s+1) begin
      assign vlaid_trans_s_by_m[s][0]   = (haddr_m[0][31:16] == slave_base[s][31:16]) & htrans_m[0][1] & hready_s[s];
      assign latch_addr_ctl[s][0]       = vlaid_trans_s_by_m[s][0] & ~hready_s[s];
      assign hsel_s_by_m[s][0]          = vlaid_trans_s_by_m[s][0];
      assign hsel_s_by_hpm[s][0]        = hsel_s_by_m[s][0];
      assign haddr_s_by_m[s][0]         = hsel_s_by_m[s][0] ? haddr_m[0]  : 32'b0;
      assign hsize_s_by_m[s][0]         = hsel_s_by_m[s][0] ? hsize_m[0]  : 3'b0;
      assign hwrite_s_by_m[s][0]        = hsel_s_by_m[s][0] ? hwrite_m[0] : 1'b0;
    end
  endgenerate




  generate
    for (m=1; m<NUM_MASTERS; m=m+1) begin
      for (s=0; s<NUM_SLAVES; s=s+1) begin
        assign vlaid_trans_s_by_m[s][m]    =   (haddr_m[m][31:16] == slave_base[s][31:16]) & htrans_m[m][1];
        assign latch_addr_ctl[s][m]        =   vlaid_trans_s_by_m[s][m] & (hsel_s_by_hpm[s][m-1] | ~hready_s[s]);
        assign hsel_s_by_m[s][m]           =   hsel_s_by_lpm_lat[s][m] | (~hsel_s_by_hpm[s][m-1] & vlaid_trans_s_by_m[s][m]);
        assign haddr_s_by_m[s][m]          =   hsel_s_by_m[s][m] ? (hsel_s_by_lpm_lat[s][m] ? haddr_s_by_lpm_lat[s][m]  : haddr_m[m] ): 32'b0;
        assign hsize_s_by_m[s][m]          =   hsel_s_by_m[s][m] ? (hsel_s_by_lpm_lat[s][m] ? hsize_s_by_lpm_lat[s][m]  : hsize_m[m] ): 3'b0;
        assign hwrite_s_by_m[s][m]         =   hsel_s_by_m[s][m] ? (hsel_s_by_lpm_lat[s][m] ? hwrite_s_by_lpm_lat[s][m] : hwrite_m[m]): 1'b0;

        assign hsel_s_by_hpm[s][m]         =   hsel_s_by_m[s][m] | hsel_s_by_hpm[s][m-1];
      end
    end
  endgenerate




  generate
    for (m=0; m<NUM_MASTERS; m=m+1) begin
      for (s=0; s<NUM_SLAVES; s=s+1) begin
        always @ (posedge hclk or negedge hresetn) begin
          if (hresetn == 1'b0) begin
            hsel_s_by_lpm_lat[s][m]   = 1'b0;
            haddr_s_by_lpm_lat[s][m]  = 32'b0;
            hsize_s_by_lpm_lat[s][m]  = 3'b0;
            hwrite_s_by_lpm_lat[s][m] = 1'b0;
          end
          else if (latch_addr_ctl[s][m]) begin
            hsel_s_by_lpm_lat[s][m]   = hsel_s_by_m[s][m];
            haddr_s_by_lpm_lat[s][m]  = haddr_s_by_m[s][m];
            hsize_s_by_lpm_lat[s][m]  = hsize_s_by_m[s][m];
            hwrite_s_by_lpm_lat[s][m] = hwrite_s_by_m[s][m];
          end
          else if (hsel_s_by_m[s][m]) begin
            hsel_s_by_lpm_lat[s][m]   = 1'b0;
            haddr_s_by_lpm_lat[s][m]  = 32'b0;
            hsize_s_by_lpm_lat[s][m]  = 3'b0;
            hwrite_s_by_lpm_lat[s][m] = 1'b0;
          end
        end
      end
    end
  endgenerate





  integer j;
  generate
    for (s=0; s<NUM_SLAVES; s=s+1) begin
      always@* begin
        hsel_s[s]    = 1'b0;
        haddr_s[s]   = 32'b0;
        hwrite_s[s]  = 1'b0;
        hsize_s[s]   = 1'b0;
        for (j=0; j<NUM_MASTERS; j=j+1) begin
          hsel_s[s]    = hsel_s[s]   | hsel_s_by_m[s][j];
          haddr_s[s]   = haddr_s[s]  | haddr_s_by_m[s][j];
          hsize_s[s]   = hsize_s[s]  | hsize_s_by_m[s][j];
          hwrite_s[s]  = hwrite_s[s] | hwrite_s_by_m[s][j];
        end
      end
    end
  endgenerate








  generate
    for (m=0; m<NUM_MASTERS; m=m+1) begin
      for (s=0; s<NUM_SLAVES; s=s+1) begin
        always @ (posedge hclk or negedge hresetn) begin
          if (hresetn == 1'b0) begin
            hsel_s_by_m_lat[s][m] = 1'b0;
          end
          else if (hsel_s_by_m_lat[s][m] & !hready_s[s]) begin
            hsel_s_by_m_lat[s][m] = 1'b1;
          end
          else begin
            hsel_s_by_m_lat[s][m] = hsel_s_by_m[s][m];
          end
        end
      end
    end
  endgenerate

  generate
    for (s=0; s<NUM_SLAVES; s=s+1) begin
      always@* begin
        hwdata_s[s]  = 32'b0;
        for (j=0; j<NUM_MASTERS; j=j+1) begin
          hwdata_s[s]  = hwdata_s[s] | (hwdata_m[j] & {32{hsel_s_by_m_lat[s][j]}});
        end
      end
    end
  endgenerate




  generate
    for (m=0; m<NUM_MASTERS; m=m+1) begin
      always@* begin
        hready_m[m]  = 1'b1;
        for (j=0; j<NUM_SLAVES; j=j+1) begin
          hready_m[m] = ~hsel_s_by_lpm_lat[j][m] & ~(hsel_s_by_m_lat[j][m] & ~hready_s[j]) & hready_m[m] ;
        end
      end
    end
  endgenerate

  generate
    for (m=0; m<NUM_MASTERS; m=m+1) begin
      always@* begin
        hrdata_m[m]  = 32'b0;
        hresp_m[m]  = 32'b0;
        for (j=0; j<NUM_SLAVES; j=j+1) begin
          hrdata_m[m] = ({32{hsel_s_by_m_lat[j][m]}} & hrdata_s[j]) | hrdata_m[m];
          hresp_m[m]  = (hsel_s_by_m_lat[j][m] & hresp_s[j]) | hresp_m[m];
        end
      end
    end
  endgenerate



endmodule
module ahb_ic #(
  parameter NUM_SLAVES   = 2,
  parameter NUM_MASTERS  = 2,
  parameter [31:0] SLAVE_BASE [NUM_SLAVES-1 :0]   ='{
                                                     32'h4003_0000,
                                                     32'h4002_0000}
)(  

  input  wire         hclk,
  input  wire         hresetn,

  input   wire [ 1:0] htrans_m[NUM_MASTERS-1 :0],
  input   wire [31:0] haddr_m[NUM_MASTERS-1 :0],
  input   wire [ 2:0] hsize_m[NUM_MASTERS-1 :0],
  input   wire [31:0] hwdata_m[NUM_MASTERS-1 :0],
  input   wire        hwrite_m[NUM_MASTERS-1 :0],
  output  reg  [31:0] hrdata_m[NUM_MASTERS-1 :0],
  output  reg         hready_m[NUM_MASTERS-1 :0],
  output  reg         hresp_m[NUM_MASTERS-1 :0],

  output  reg         hsel_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] haddr_s[NUM_SLAVES-1 :0],
  output  reg  [ 2:0] hsize_s[NUM_SLAVES-1 :0],
  output  reg         hwrite_s[NUM_SLAVES-1 :0],
  output  reg  [31:0] hwdata_s[NUM_SLAVES-1 :0],
  input   wire [31:0] hrdata_s[NUM_SLAVES-1 :0],
  input   wire        hready_s[NUM_SLAVES-1 :0],
  input   wire        hresp_s[NUM_SLAVES-1 :0]
);



  wire [31 :0]            slave_base[NUM_SLAVES-1 :0];

  wire                    vlaid_trans_s_by_m[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  wire                    hsel_s_by_m[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  wire                    hsel_s_by_hpm[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  wire [31 :0]            haddr_s_by_m[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  wire [2 :0]             hsize_s_by_m[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  wire                    hwrite_s_by_m[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  wire [31 :0]            hwdata_s_by_m[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];

  wire                   latch_addr_ctl[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  reg                    hsel_s_by_lpm_lat[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  reg [31 :0]            haddr_s_by_lpm_lat[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  reg [2 :0]             hsize_s_by_lpm_lat[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  reg                    hwrite_s_by_lpm_lat[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];

  reg                     hsel_s_by_m_lat[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];
  reg  [31 :0]            hwdata_s_by_m_lat[NUM_SLAVES-1 :0][NUM_MASTERS-1 :0];


















  genvar s,m;




 
  assign slave_base  = SLAVE_BASE;
  generate
    for (s=0; s<NUM_SLAVES; s=s+1) begin
      assign vlaid_trans_s_by_m[s][0]   = (haddr_m[0][31:16] == slave_base[s][31:16]) & htrans_m[0][1] & hready_s[s];
      assign latch_addr_ctl[s][0]       = vlaid_trans_s_by_m[s][0] & ~hready_s[s];
      assign hsel_s_by_m[s][0]          = vlaid_trans_s_by_m[s][0];
      assign hsel_s_by_hpm[s][0]        = hsel_s_by_m[s][0];
      assign haddr_s_by_m[s][0]         = hsel_s_by_m[s][0] ? haddr_m[0]  : 32'b0;
      assign hsize_s_by_m[s][0]         = hsel_s_by_m[s][0] ? hsize_m[0]  : 3'b0;
      assign hwrite_s_by_m[s][0]        = hsel_s_by_m[s][0] ? hwrite_m[0] : 1'b0;
    end
  endgenerate




  generate
    for (m=1; m<NUM_MASTERS; m=m+1) begin
      for (s=0; s<NUM_SLAVES; s=s+1) begin
        assign vlaid_trans_s_by_m[s][m]    =   (haddr_m[m][31:16] == slave_base[s][31:16]) & htrans_m[m][1];
        assign latch_addr_ctl[s][m]        =   vlaid_trans_s_by_m[s][m] & (hsel_s_by_hpm[s][m-1] | ~hready_s[s]);
        assign hsel_s_by_m[s][m]           =   hsel_s_by_lpm_lat[s][m] | (~hsel_s_by_hpm[s][m-1] & vlaid_trans_s_by_m[s][m]);
        assign haddr_s_by_m[s][m]          =   hsel_s_by_m[s][m] ? (hsel_s_by_lpm_lat[s][m] ? haddr_s_by_lpm_lat[s][m]  : haddr_m[m] ): 32'b0;
        assign hsize_s_by_m[s][m]          =   hsel_s_by_m[s][m] ? (hsel_s_by_lpm_lat[s][m] ? hsize_s_by_lpm_lat[s][m]  : hsize_m[m] ): 3'b0;
        assign hwrite_s_by_m[s][m]         =   hsel_s_by_m[s][m] ? (hsel_s_by_lpm_lat[s][m] ? hwrite_s_by_lpm_lat[s][m] : hwrite_m[m]): 1'b0;

        assign hsel_s_by_hpm[s][m]         =   hsel_s_by_m[s][m] | hsel_s_by_hpm[s][m-1];
      end
    end
  endgenerate




  generate
    for (m=0; m<NUM_MASTERS; m=m+1) begin
      for (s=0; s<NUM_SLAVES; s=s+1) begin
        always @ (posedge hclk or negedge hresetn) begin
          if (hresetn == 1'b0) begin
            hsel_s_by_lpm_lat[s][m]   = 1'b0;
            haddr_s_by_lpm_lat[s][m]  = 32'b0;
            hsize_s_by_lpm_lat[s][m]  = 3'b0;
            hwrite_s_by_lpm_lat[s][m] = 1'b0;
          end
          else if (latch_addr_ctl[s][m]) begin
            hsel_s_by_lpm_lat[s][m]   = hsel_s_by_m[s][m];
            haddr_s_by_lpm_lat[s][m]  = haddr_s_by_m[s][m];
            hsize_s_by_lpm_lat[s][m]  = hsize_s_by_m[s][m];
            hwrite_s_by_lpm_lat[s][m] = hwrite_s_by_m[s][m];
          end
          else if (hsel_s_by_m[s][m]) begin
            hsel_s_by_lpm_lat[s][m]   = 1'b0;
            haddr_s_by_lpm_lat[s][m]  = 32'b0;
            hsize_s_by_lpm_lat[s][m]  = 3'b0;
            hwrite_s_by_lpm_lat[s][m] = 1'b0;
          end
        end
      end
    end
  endgenerate





  integer j;
  generate
    for (s=0; s<NUM_SLAVES; s=s+1) begin
      always@* begin
        hsel_s[s]    = 1'b0;
        haddr_s[s]   = 32'b0;
        hwrite_s[s]  = 1'b0;
        hsize_s[s]   = 1'b0;
        for (j=0; j<NUM_MASTERS; j=j+1) begin
          hsel_s[s]    = hsel_s[s]   | hsel_s_by_m[s][j];
          haddr_s[s]   = haddr_s[s]  | haddr_s_by_m[s][j];
          hsize_s[s]   = hsize_s[s]  | hsize_s_by_m[s][j];
          hwrite_s[s]  = hwrite_s[s] | hwrite_s_by_m[s][j];
        end
      end
    end
  endgenerate








  generate
    for (m=0; m<NUM_MASTERS; m=m+1) begin
      for (s=0; s<NUM_SLAVES; s=s+1) begin
        always @ (posedge hclk or negedge hresetn) begin
          if (hresetn == 1'b0) begin
            hsel_s_by_m_lat[s][m] = 1'b0;
          end
          else if (hsel_s_by_m_lat[s][m] & !hready_s[s]) begin
            hsel_s_by_m_lat[s][m] = 1'b1;
          end
          else begin
            hsel_s_by_m_lat[s][m] = hsel_s_by_m[s][m];
          end
        end
      end
    end
  endgenerate

  generate
    for (s=0; s<NUM_SLAVES; s=s+1) begin
      always@* begin
        hwdata_s[s]  = 32'b0;
        for (j=0; j<NUM_MASTERS; j=j+1) begin
          hwdata_s[s]  = hwdata_s[s] | (hwdata_m[j] & {32{hsel_s_by_m_lat[s][j]}});
        end
      end
    end
  endgenerate




  generate
    for (m=0; m<NUM_MASTERS; m=m+1) begin
      always@* begin
        hready_m[m]  = 1'b1;
        for (j=0; j<NUM_SLAVES; j=j+1) begin
          hready_m[m] = ~hsel_s_by_lpm_lat[j][m] & ~(hsel_s_by_m_lat[j][m] & ~hready_s[j]) & hready_m[m] ;
        end
      end
    end
  endgenerate

  generate
    for (m=0; m<NUM_MASTERS; m=m+1) begin
      always@* begin
        hrdata_m[m]  = 32'b0;
        hresp_m[m]  = 32'b0;
        for (j=0; j<NUM_SLAVES; j=j+1) begin
          hrdata_m[m] = ({32{hsel_s_by_m_lat[j][m]}} & hrdata_s[j]) | hrdata_m[m];
          hresp_m[m]  = (hsel_s_by_m_lat[j][m] & hresp_s[j]) | hresp_m[m];
        end
      end
    end
  endgenerate



endmodule