data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/altera_virtual_jtag/altera_virtual_jtag.v
1: b"%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/altera_virtual_jtag/altera_virtual_jtag.v:69: Cannot find file containing module: 'sld_virtual_jtag'\nsld_virtual_jtag #(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/altera_virtual_jtag,data/full_repos/permissive/19905110/sld_virtual_jtag\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/altera_virtual_jtag,data/full_repos/permissive/19905110/sld_virtual_jtag.v\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/altera_virtual_jtag,data/full_repos/permissive/19905110/sld_virtual_jtag.sv\n             sld_virtual_jtag\n             sld_virtual_jtag.v\n             sld_virtual_jtag.sv\n             obj_dir/sld_virtual_jtag\n             obj_dir/sld_virtual_jtag.v\n             obj_dir/sld_virtual_jtag.sv\n%Error: Exiting due to 1 error(s)\n"
module altera_virtual_jtag (
	output	tck_o,
	input	debug_tdo_i,
	output	tdi_o,
	output	test_logic_reset_o,
	output	run_test_idle_o,
	output	shift_dr_o,
	output	capture_dr_o,
	output	pause_dr_o,
	output	update_dr_o,
	output	debug_select_o
);

localparam [3:0] CMD_DEBUG = 4'b1000;

wire	[3:0]	ir_value;
wire		exit1_dr;
wire		exit2_dr;
wire		capture_ir;
wire		update_ir;

sld_virtual_jtag #(
	.sld_auto_instance_index	("YES"),
	.sld_instance_index		(0),
	.sld_ir_width			(4),
	.sld_sim_action			(""),
	.sld_sim_n_scan			(0),
	.sld_sim_total_length		(0),
	.lpm_type			("sld_virtual_jtag")
) sld_virtual_jtag_component (
	.ir_out				(ir_value),
	.tdo				(debug_tdo_i),
	.tdi				(tdi_o),
	.jtag_state_rti			(run_test_idle_o),
	.tck				(tck_o),
	.ir_in				(ir_value),
	.jtag_state_tlr			(test_logic_reset_o),
	.virtual_state_cir		(capture_ir),
	.virtual_state_pdr		(pause_dr_o),
	.virtual_state_uir		(update_ir),
	.virtual_state_sdr		(shift_dr_o),
	.virtual_state_cdr		(capture_dr_o),
	.virtual_state_udr		(update_dr_o),
	.virtual_state_e1dr		(exit1_dr),
	.virtual_state_e2dr		(exit2_dr)
);

assign debug_select_o = (ir_value == CMD_DEBUG);

endmodule
module altera_virtual_jtag (
	output	tck_o,
	input	debug_tdo_i,
	output	tdi_o,
	output	test_logic_reset_o,
	output	run_test_idle_o,
	output	shift_dr_o,
	output	capture_dr_o,
	output	pause_dr_o,
	output	update_dr_o,
	output	debug_select_o
);


localparam [3:0] CMD_DEBUG = 4'b1000;

wire	[3:0]	ir_value;
wire		exit1_dr;
wire		exit2_dr;
wire		capture_ir;
wire		update_ir;

sld_virtual_jtag #(
	.sld_auto_instance_index	("YES"),
	.sld_instance_index		(0),
	.sld_ir_width			(4),
	.sld_sim_action			(""),
	.sld_sim_n_scan			(0),
	.sld_sim_total_length		(0),
	.lpm_type			("sld_virtual_jtag")
) sld_virtual_jtag_component (
	.ir_out				(ir_value),
	.tdo				(debug_tdo_i),
	.tdi				(tdi_o),
	.jtag_state_rti			(run_test_idle_o),
	.tck				(tck_o),
	.ir_in				(ir_value),
	.jtag_state_tlr			(test_logic_reset_o),
	.virtual_state_cir		(capture_ir),
	.virtual_state_pdr		(pause_dr_o),
	.virtual_state_uir		(update_ir),
	.virtual_state_sdr		(shift_dr_o),
	.virtual_state_cdr		(capture_dr_o),
	.virtual_state_udr		(update_dr_o),
	.virtual_state_e1dr		(exit1_dr),
	.virtual_state_e2dr		(exit2_dr)
);

assign debug_select_o = (ir_value == CMD_DEBUG);

endmodule