data/full_repos/permissive/20270692/labs/lab2/nor_with_nand_tb.v
 line:43: before: "$"
1: b'%Error: data/full_repos/permissive/20270692/labs/lab2/nor_with_nand_tb.v:7: Cannot find include file: nor_with_nand.v\n`include "nor_with_nand.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab2,data/full_repos/permissive/20270692/nor_with_nand.v\n             data/full_repos/permissive/20270692/labs/lab2,data/full_repos/permissive/20270692/nor_with_nand.v.v\n             data/full_repos/permissive/20270692/labs/lab2,data/full_repos/permissive/20270692/nor_with_nand.v.sv\n             nor_with_nand.v\n             nor_with_nand.v.v\n             nor_with_nand.v.sv\n             obj_dir/nor_with_nand.v\n             obj_dir/nor_with_nand.v.v\n             obj_dir/nor_with_nand.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab2/nor_with_nand_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n initial #1000 $finish;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab2/nor_with_nand_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  forever #5 t_clock=~t_clock;\n          ^\n%Error: data/full_repos/permissive/20270692/labs/lab2/nor_with_nand_tb.v:49: Unsupported or unknown PLI call: $monitor\n  $monitor("time=%0d", $time,, "A=%b B=%b F=%b", A, B, F);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/20270692/labs/lab2/nor_with_nand_tb.v:49: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  $monitor("time=%0d", $time,, "A=%b B=%b F=%b", A, B, F);\n                             ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module nor_with_nand_tb (A, B);

	output A, B;
	reg A, B;

	wire F;

	reg t_A [5000:0];
	reg t_B [5000:0];
	reg t_clock;
	reg [31:0] vectornum;

	nor_with_nand I1 (A, B, F);

	initial #1000 $finish;

	initial
	begin
		t_clock=0;
		forever #5 t_clock=~t_clock;
	end

	initial
	begin
		$readmemb("./bit_str_a_0.txt",t_A);
		$readmemb("./bit_str_a_1.txt",t_B);
		vectornum=0;
	end

	always @(negedge t_clock)
	begin
		A<=t_A[vectornum];
		B<=t_B[vectornum];
		vectornum<=vectornum+1;
	end

	initial
	begin
		$monitor("time=%0d", $time,, "A=%b B=%b F=%b", A, B, F);
	end

endmodule
module nor_with_nand_tb (A, B);


	output A, B;
	reg A, B;

	wire F;

	reg t_A [5000:0];
	reg t_B [5000:0];
	reg t_clock;
	reg [31:0] vectornum;

	nor_with_nand I1 (A, B, F);

	initial #1000 $finish;

	initial
	begin
		t_clock=0;
		forever #5 t_clock=~t_clock;
	end

	initial
	begin
		$readmemb("./bit_str_a_0.txt",t_A);
		$readmemb("./bit_str_a_1.txt",t_B);
		vectornum=0;
	end

	always @(negedge t_clock)
	begin
		A<=t_A[vectornum];
		B<=t_B[vectornum];
		vectornum<=vectornum+1;
	end

	initial
	begin
		$monitor("time=%0d", $time,, "A=%b B=%b F=%b", A, B, F);
	end

endmodule