data/full_repos/permissive/197614074/CONV2D.v
1: b'%Error: data/full_repos/permissive/197614074/CONV2D.v:55: Cannot find file containing module: \'conv_main\'\n   conv_main #(WIDTH,HEIGHT,CHANNEL )mid_conv (.clk(clk), .indata(indata),\n   ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197614074,data/full_repos/permissive/197614074/conv_main\n             data/full_repos/permissive/197614074,data/full_repos/permissive/197614074/conv_main.v\n             data/full_repos/permissive/197614074,data/full_repos/permissive/197614074/conv_main.sv\n             conv_main\n             conv_main.v\n             conv_main.sv\n             obj_dir/conv_main\n             obj_dir/conv_main.v\n             obj_dir/conv_main.sv\n%Warning-WIDTH: data/full_repos/permissive/197614074/CONV2D.v:59: Operator ADD expects 288 bits on the RHS, but RHS\'s VARREF \'xyadress\' generates 8 bits.\n                                                                : ... In instance CONV2D\n    address_out = Filter_adr * CHANNEL * HEIGHT * WIDTH + completedconv * HEIGHT * WIDTH + xyadress;\n                                                                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module CONV2D#(    
    parameter  WIDTH 	= 	3,
    parameter  HEIGHT 	= 	3,
    parameter  CHANNEL 	= 	1,
	 parameter 	FILTER 	=	32,
	 parameter  KERNELSIZE = 9
    )(
		input																												clk,
		input																												enable,
		input 			[8 * WIDTH 		* 	HEIGHT 		* 	CHANNEL 	- 	1 	: 0]							indata,
		input 			[8 * FILTER		*	KERNELSIZE	* 	CHANNEL  - 1 	: 0]							filterWeight,
		output	reg	[FILTER			*	WIDTH 		* 	HEIGHT 	- 1 	: 0]							address_out,
		output 	reg	  [7  : 0] 																					result,
		output	reg																									dataready,
		output   reg 																									finish
    );
		wire 	DSR;
		reg	[7:0]	Filter_adr;
		reg	[7:0] completedconv;
		wire  	[7:0] xyadress;
		wire 	[7:0] out;
		wire 	[20:0]	inaddress;
		initial begin result = 0; end
		initial begin
			Filter_adr	=	0;
			result=	0;
			address_out = 0;
			completedconv	=	0;

		end
		genvar i;



			conv_main #(WIDTH,HEIGHT,CHANNEL	)mid_conv (.clk(clk), .indata(indata),
			.filterWeight(filterWeight[72*(Filter_adr) +: 72]),
			.result(out),.res_address(xyadress),  .dataready(DSR));
		always @ (posedge clk) begin
				address_out	=	Filter_adr * CHANNEL * HEIGHT * WIDTH + completedconv * HEIGHT * WIDTH + xyadress;
				if (DSR) begin
					result	= out;
					dataready		=	1;
					completedconv	=	completedconv	+	1;
				end
				else begin dataready = 0; end
				if (completedconv == WIDTH * HEIGHT)begin
					Filter_adr = Filter_adr+1;
				end
				if (Filter_adr	==	FILTER)begin
					finish = 1;
					Filter_adr = 0;
				end
				else begin finish = 0; end 
		end
endmodule
module CONV2D#(    
    parameter  WIDTH 	= 	3,
    parameter  HEIGHT 	= 	3,
    parameter  CHANNEL 	= 	1,
	 parameter 	FILTER 	=	32,
	 parameter  KERNELSIZE = 9
    )(
		input																												clk,
		input																												enable,
		input 			[8 * WIDTH 		* 	HEIGHT 		* 	CHANNEL 	- 	1 	: 0]							indata,
		input 			[8 * FILTER		*	KERNELSIZE	* 	CHANNEL  - 1 	: 0]							filterWeight,
		output	reg	[FILTER			*	WIDTH 		* 	HEIGHT 	- 1 	: 0]							address_out,
		output 	reg	  [7  : 0] 																					result,
		output	reg																									dataready,
		output   reg 																									finish
    );

		wire 	DSR;
		reg	[7:0]	Filter_adr;
		reg	[7:0] completedconv;
		wire  	[7:0] xyadress;
		wire 	[7:0] out;
		wire 	[20:0]	inaddress;
		initial begin result = 0; end
		initial begin
			Filter_adr	=	0;
			result=	0;
			address_out = 0;
			completedconv	=	0;

		end
		genvar i;



			conv_main #(WIDTH,HEIGHT,CHANNEL	)mid_conv (.clk(clk), .indata(indata),
			.filterWeight(filterWeight[72*(Filter_adr) +: 72]),
			.result(out),.res_address(xyadress),  .dataready(DSR));
		always @ (posedge clk) begin
				address_out	=	Filter_adr * CHANNEL * HEIGHT * WIDTH + completedconv * HEIGHT * WIDTH + xyadress;
				if (DSR) begin
					result	= out;
					dataready		=	1;
					completedconv	=	completedconv	+	1;
				end
				else begin dataready = 0; end
				if (completedconv == WIDTH * HEIGHT)begin
					Filter_adr = Filter_adr+1;
				end
				if (Filter_adr	==	FILTER)begin
					finish = 1;
					Filter_adr = 0;
				end
				else begin finish = 0; end 
		end
endmodule