data/full_repos/permissive/150214807/lab4.v
 line:123: before: "$"
1: b'%Error: data/full_repos/permissive/150214807/lab4.v:114: Unsupported or unknown PLI call: $monitor\n$monitor(,$time,"a = %h, b =%h, bin = %b, op = %b, cin = %b, res = %h, cout = %b",a,b,Binvert,Operation,Carryin,Result,CarryOut);\n^~~~~~~~\n%Error: data/full_repos/permissive/150214807/lab4.v:114: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n$monitor(,$time,"a = %h, b =%h, bin = %b, op = %b, cin = %b, res = %h, cout = %b",a,b,Binvert,Operation,Carryin,Result,CarryOut);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab4.v:120: Unsupported: Ignoring delay on this delayed statement.\n#100 Operation=2\'b01;  \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab4.v:121: Unsupported: Ignoring delay on this delayed statement.\n#100 Operation=2\'b10;  \n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab4.v:122: Unsupported: Ignoring delay on this delayed statement.\n#100 Binvert=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab4.v:123: Unsupported: Ignoring delay on this delayed statement.\n#200 $finish;\n^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU(a,b,bin,cin,op,res,cout);
 input [31:0] a,b;
 input cin,bin;
 input [1:0] op;
 output [31:0] res;
 output cout;
 wire [31:0] bfin,negb,min0,min1,min2;
 bit32_not n1(negb,b);
 bit32_mux21 m1(bfin,bin,negb,b);
 bit32_and a1(min0,a,bfin);
 bit32_or a2(min1,a,bfin);
 bit32_FA a3(cout,min2,a,bfin,cin);
 bit32_mux3port fin(res,op,min2,min1,min0);
endmodule
module ALU(a,b,bin,cin,op,res,cout);

 input [31:0] a,b;
 input cin,bin;
 input [1:0] op;
 output [31:0] res;
 output cout;
 wire [31:0] bfin,negb,min0,min1,min2;
 bit32_not n1(negb,b);
 bit32_mux21 m1(bfin,bin,negb,b);
 bit32_and a1(min0,a,bfin);
 bit32_or a2(min1,a,bfin);
 bit32_FA a3(cout,min2,a,bfin,cin);
 bit32_mux3port fin(res,op,min2,min1,min0);
endmodule