data/full_repos/permissive/143278/ivltests/vardly.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vardly.v:8: Unsupported: Ignoring delay on this delayed statement.\n  #tdelay var2 = var1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vardly.v:14: Unsupported: Ignoring delay on this delayed statement.\n    # 1;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vardly.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1 ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vardly.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1 ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vardly.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vardly.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vardly.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vardly.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ();

reg [31:0] tdelay;
reg [3:0] var1,var2;
reg error;

always @(var1)
  #tdelay var2 = var1;

initial
  begin
    error = 0;
    tdelay = 5;
    # 1;
    var2 = 0;
    #1 ;
    var1 = 1;
    #1 ;
    if(var2 != 0)
      begin
        $display("FAILED at %t",$time);
        error = 1;
      end
    #1;
    if(var2 != 0)
      begin
        $display("FAILED at %t",$time);
        error = 1;
      end
    #1;
    if(var2 != 0)
      begin
        $display("FAILED at %t",$time);
        error = 1;
      end
    #1;
    if(var2 != 0)
      begin
        $display("FAILED at %t",$time);
        error = 1;
      end
    #1;
    if(var2 != 1)
      begin
        $display("FAILED at %t",$time);
        error = 1;
      end

    if(error == 0)
       $display("PASSED");
  end

endmodule
module main ();


reg [31:0] tdelay;
reg [3:0] var1,var2;
reg error;

always @(var1)
  #tdelay var2 = var1;

initial
  begin
    error = 0;
    tdelay = 5;
    # 1;
    var2 = 0;
    #1 ;
    var1 = 1;
    #1 ;
    if(var2 != 0)
      begin
        $display("FAILED at %t",$time);
        error = 1;
      end
    #1;
    if(var2 != 0)
      begin
        $display("FAILED at %t",$time);
        error = 1;
      end
    #1;
    if(var2 != 0)
      begin
        $display("FAILED at %t",$time);
        error = 1;
      end
    #1;
    if(var2 != 0)
      begin
        $display("FAILED at %t",$time);
        error = 1;
      end
    #1;
    if(var2 != 1)
      begin
        $display("FAILED at %t",$time);
        error = 1;
      end

    if(error == 0)
       $display("PASSED");
  end

endmodule