data/full_repos/permissive/142460685/Flip_Flop_TB.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/142460685/Flip_Flop_TB.v:23: Unsupported: Ignoring delay on this delayed statement.\nalways #3 clk =~ clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/142460685/Flip_Flop_TB.v:25: Unsupported: Ignoring delay on this delayed statement.\nalways #5 data =~ data;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/142460685/Flip_Flop_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\nalways #20 reset = ~reset;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/142460685/Flip_Flop_TB.v:30: Unsupported: Ignoring delay on this delayed statement.\ninitial                     #100 $stop;\n                            ^\n%Error: data/full_repos/permissive/142460685/Flip_Flop_TB.v:13: Pin is not an in/out/inout/param/interface: \'q\'\ndff_async_reset_tb uut (.q(q),.data(data), .clk(clk) );\n                         ^\n%Error: data/full_repos/permissive/142460685/Flip_Flop_TB.v:13: Pin is not an in/out/inout/param/interface: \'data\'\ndff_async_reset_tb uut (.q(q),.data(data), .clk(clk) );\n                               ^~~~\n%Error: data/full_repos/permissive/142460685/Flip_Flop_TB.v:13: Pin is not an in/out/inout/param/interface: \'clk\'\ndff_async_reset_tb uut (.q(q),.data(data), .clk(clk) );\n                                            ^~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dff_async_reset_tb;

reg data;

reg clk;

reg reset;

wire q;


dff_async_reset_tb uut (.q(q),.data(data), .clk(clk) );


initial begin
data = 0;
clk = 0;
reset = 1;
end


always #3 clk =~ clk;

always #5 data =~ data;

always #20 reset = ~reset;


initial                     #100 $stop;
endmodule
module dff_async_reset_tb;


reg data;

reg clk;

reg reset;

wire q;


dff_async_reset_tb uut (.q(q),.data(data), .clk(clk) );


initial begin
data = 0;
clk = 0;
reset = 1;
end


always #3 clk =~ clk;

always #5 data =~ data;

always #20 reset = ~reset;


initial                     #100 $stop;
endmodule