data/full_repos/permissive/152229899/sync_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152229899/sync_fifo.v:45: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                   : ... In instance sync_fifo.ram_top\n   data_out<=ram[rd_addr];\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/152229899/sync_fifo.v:53: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                   : ... In instance sync_fifo.ram_top\n  ram[wr_addr]<=data_in;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/152229899/sync_fifo.v:215: Operator GTE expects 8 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                    : ... In instance sync_fifo\n   else if (data_in >= 5\'d0 && data_in < 5\'d31)\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/152229899/sync_fifo.v:215: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'5\'h1f\' generates 5 bits.\n                                                                    : ... In instance sync_fifo\n   else if (data_in >= 5\'d0 && data_in < 5\'d31)\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/152229899/sync_fifo.v:213: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'5\'h1f\' generates 5 bits.\n                                                                    : ... In instance sync_fifo\n   else if (data_in == 5\'d31)\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/152229899/sync_fifo.v:219: Operator GTE expects 5 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance sync_fifo\nassign wr_en = (time_cnt >= 1\'b0 && time_cnt <= 5\'d15) ? 1\'b1:1\'b0;\n                         ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152229899/sync_fifo.v:205: Comparison is constant due to unsigned arithmetic\n                                                                       : ... In instance sync_fifo\n else if (data_in >= 8\'d0 && data_in < 8\'d15)\n                  ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152229899/sync_fifo.v:215: Comparison is constant due to unsigned arithmetic\n                                                                       : ... In instance sync_fifo\n   else if (data_in >= 5\'d0 && data_in < 5\'d31)\n                    ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152229899/sync_fifo.v:219: Comparison is constant due to unsigned arithmetic\n                                                                       : ... In instance sync_fifo\nassign wr_en = (time_cnt >= 1\'b0 && time_cnt <= 5\'d15) ? 1\'b1:1\'b0;\n                         ^~\n%Warning-CMPCONST: data/full_repos/permissive/152229899/sync_fifo.v:220: Comparison is constant due to limited range\n                                                                       : ... In instance sync_fifo\nassign rd_en = (time_cnt >= 5\'d16 && time_cnt <= 5\'d31) ? 1\'b1:1\'b0;\n                                              ^~\n%Error: Exiting due to 10 warning(s)\n'
module rd_addr_gen(input clk,
                   input rst,
                   input rd_en,
                   input empty,
                   output reg[3:0]rd_addr);
						 
always @(posedge clk or negedge rst)
begin
	if(!rst)
	begin
		rd_addr<=0;
	end  
	else
	begin
		if(empty==0&&rd_en==1)
		begin
			rd_addr<=rd_addr+1;
		end
	end
end
endmodule
module rd_addr_gen(input clk,
                   input rst,
                   input rd_en,
                   input empty,
                   output reg[3:0]rd_addr);

						 
always @(posedge clk or negedge rst)
begin
	if(!rst)
	begin
		rd_addr<=0;
	end  
	else
	begin
		if(empty==0&&rd_en==1)
		begin
			rd_addr<=rd_addr+1;
		end
	end
end
endmodule