data/full_repos/permissive/111973973/vgacg/vgaEngine.v
data/verilator_xmls/6bf4d99d-d84f-4543-8373-9bf6d9086e15.xml
module vgaEngine #(
    parameter H_WIDTH = 10,
    parameter V_WIDTH = 9,
    parameter H_ACTIVE = 640,
    parameter H_FP = 16,
    parameter H_SYN = 96,
    parameter H_BP = 48,
    parameter H_TOTAL = H_ACTIVE+H_FP+H_SYN+H_BP,
    parameter V_ACTIVE = 480,
    parameter V_FP = 10,
    parameter V_SYN = 2,
    parameter V_BP = 29,
    parameter V_TOTAL = V_ACTIVE+V_FP+V_SYN+V_BP,







    parameter EXT_PIPELINE_DELAY = 0)

   (input clk,
    input rst_p,
    input clk_en,
    input[3:0] r,
    input[3:0] g,
    input[3:0] b,
    output vertBlanking,
    output[H_WIDTH-1:0] horizPos,
    output[V_WIDTH-1:0] vertPos,
    output reg v_sync,
    output reg h_sync,
    output reg[3:0] redOut,
    output reg[3:0] greenOut,
    output reg[3:0] blueOut);

    integer i;
    reg[H_WIDTH-1:0] horiz_position_pipeline [0:EXT_PIPELINE_DELAY];
    reg[V_WIDTH-1:0] vert_position_pipeline [0:EXT_PIPELINE_DELAY];

    wire v_sync_pre;
    wire h_sync_pre;

    assign horizPos = horiz_position_pipeline[0];
    assign vertPos = vert_position_pipeline[0];




    always @(posedge clk, posedge rst_p) begin
        if(rst_p) begin
            for(i = 0; i<=EXT_PIPELINE_DELAY; i=i+1) begin
                horiz_position_pipeline[i] <= 0;
                vert_position_pipeline[i] <= 0;
            end
        end else begin


            for(i = 1; i<=EXT_PIPELINE_DELAY; i=i+1) begin
                horiz_position_pipeline[i] <= horiz_position_pipeline[i-1];
                vert_position_pipeline[i] <= vert_position_pipeline[i-1];
            end

            if (clk_en) begin
                if(horiz_position_pipeline[0] == H_TOTAL-1) begin
                    if(vert_position_pipeline[0] == V_TOTAL-1) begin
                        vert_position_pipeline[0] <= 0;
                    end else begin
                        vert_position_pipeline[0] <= vert_position_pipeline[0] + 1;
                    end
                    horiz_position_pipeline[0] <= 0;
                end else begin
                    horiz_position_pipeline[0] <= horiz_position_pipeline[0] + 1;
                end
            end
        end
    end

    always @(posedge clk) begin
        h_sync <= h_sync_pre;
        v_sync <= v_sync_pre;
    end



    assign h_sync_pre = ~((horiz_position_pipeline[EXT_PIPELINE_DELAY] >= H_ACTIVE+H_FP) &
                          (horiz_position_pipeline[EXT_PIPELINE_DELAY] < H_ACTIVE+H_FP+H_SYN));



    assign v_sync_pre = ~((vert_position_pipeline[EXT_PIPELINE_DELAY] >= V_ACTIVE+V_FP) &
                          (vert_position_pipeline[EXT_PIPELINE_DELAY] < V_ACTIVE+V_FP+V_SYN));




    assign vertBlanking = (vert_position_pipeline[0] >= V_ACTIVE);

    always @(posedge clk) begin
        if(horiz_position_pipeline[EXT_PIPELINE_DELAY] < H_ACTIVE & vert_position_pipeline[EXT_PIPELINE_DELAY] < V_ACTIVE) begin
            redOut <= r;
            greenOut <= g;
            blueOut <= b;
        end else begin

            redOut <= 0;
            greenOut <= 0;
            blueOut <= 0;
        end
    end

endmodule
module vgaEngine #(
    parameter H_WIDTH = 10,
    parameter V_WIDTH = 9,
    parameter H_ACTIVE = 640,
    parameter H_FP = 16,
    parameter H_SYN = 96,
    parameter H_BP = 48,
    parameter H_TOTAL = H_ACTIVE+H_FP+H_SYN+H_BP,
    parameter V_ACTIVE = 480,
    parameter V_FP = 10,
    parameter V_SYN = 2,
    parameter V_BP = 29,
    parameter V_TOTAL = V_ACTIVE+V_FP+V_SYN+V_BP,







    parameter EXT_PIPELINE_DELAY = 0)

   (input clk,
    input rst_p,
    input clk_en,
    input[3:0] r,
    input[3:0] g,
    input[3:0] b,
    output vertBlanking,
    output[H_WIDTH-1:0] horizPos,
    output[V_WIDTH-1:0] vertPos,
    output reg v_sync,
    output reg h_sync,
    output reg[3:0] redOut,
    output reg[3:0] greenOut,
    output reg[3:0] blueOut);


    integer i;
    reg[H_WIDTH-1:0] horiz_position_pipeline [0:EXT_PIPELINE_DELAY];
    reg[V_WIDTH-1:0] vert_position_pipeline [0:EXT_PIPELINE_DELAY];

    wire v_sync_pre;
    wire h_sync_pre;

    assign horizPos = horiz_position_pipeline[0];
    assign vertPos = vert_position_pipeline[0];




    always @(posedge clk, posedge rst_p) begin
        if(rst_p) begin
            for(i = 0; i<=EXT_PIPELINE_DELAY; i=i+1) begin
                horiz_position_pipeline[i] <= 0;
                vert_position_pipeline[i] <= 0;
            end
        end else begin


            for(i = 1; i<=EXT_PIPELINE_DELAY; i=i+1) begin
                horiz_position_pipeline[i] <= horiz_position_pipeline[i-1];
                vert_position_pipeline[i] <= vert_position_pipeline[i-1];
            end

            if (clk_en) begin
                if(horiz_position_pipeline[0] == H_TOTAL-1) begin
                    if(vert_position_pipeline[0] == V_TOTAL-1) begin
                        vert_position_pipeline[0] <= 0;
                    end else begin
                        vert_position_pipeline[0] <= vert_position_pipeline[0] + 1;
                    end
                    horiz_position_pipeline[0] <= 0;
                end else begin
                    horiz_position_pipeline[0] <= horiz_position_pipeline[0] + 1;
                end
            end
        end
    end

    always @(posedge clk) begin
        h_sync <= h_sync_pre;
        v_sync <= v_sync_pre;
    end



    assign h_sync_pre = ~((horiz_position_pipeline[EXT_PIPELINE_DELAY] >= H_ACTIVE+H_FP) &
                          (horiz_position_pipeline[EXT_PIPELINE_DELAY] < H_ACTIVE+H_FP+H_SYN));



    assign v_sync_pre = ~((vert_position_pipeline[EXT_PIPELINE_DELAY] >= V_ACTIVE+V_FP) &
                          (vert_position_pipeline[EXT_PIPELINE_DELAY] < V_ACTIVE+V_FP+V_SYN));




    assign vertBlanking = (vert_position_pipeline[0] >= V_ACTIVE);

    always @(posedge clk) begin
        if(horiz_position_pipeline[EXT_PIPELINE_DELAY] < H_ACTIVE & vert_position_pipeline[EXT_PIPELINE_DELAY] < V_ACTIVE) begin
            redOut <= r;
            greenOut <= g;
            blueOut <= b;
        end else begin

            redOut <= 0;
            greenOut <= 0;
            blueOut <= 0;
        end
    end

endmodule