data/full_repos/permissive/191707432/code/dds_out.v
1: b'%Warning-WIDTH: data/full_repos/permissive/191707432/code/dds_out.v:20: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 24 bits.\n                                                                      : ... In instance dds_out\nwire   half_counter=counter_in>>1;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/191707432/code/dds_out.v:25: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'23\'h0\' generates 23 bits.\n                                                                      : ... In instance dds_out\n counter<=23\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/191707432/code/dds_out.v:27: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'23\'h0\' generates 23 bits.\n                                                                      : ... In instance dds_out\n counter<=23\'b0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/191707432/code/dds_out.v:37: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                      : ... In instance dds_out\n  address_reg<=7\'d0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/191707432/code/dds_out.v:40: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s ADD generates 12 bits.\n                                                                      : ... In instance dds_out\n   address_reg<=address_reg+mult_in;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/191707432/code/dds_out.v:39: Operator LTE expects 12 bits on the LHS, but LHS\'s VARREF \'address_reg\' generates 11 bits.\n                                                                      : ... In instance dds_out\n  if(address_reg<=(11\'h07cf-mult_in))\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/191707432/code/dds_out.v:45: Operator EQ expects 24 bits on the RHS, but RHS\'s VARREF \'half_counter\' generates 1 bits.\n                                                                      : ... In instance dds_out\n else if(counter==half_counter)begin\n                ^~\n%Error: Exiting due to 7 warning(s)\n'
module dds_out
(
	input clk_400M,
	input rst_n,
	output [10:0] address,
	output adc_clock,
	output [13:0] dac_data_out,
	input [13:0] q,
	input [23:0] counter_in,
	input [11:0] mult_in
);

reg [23:0] counter;
reg [10:0] address_reg;
reg adc_clock_reg;

assign address=address_reg;
assign adc_clock=adc_clock_reg;
assign dac_data_out=(counter==(counter_in))?q:dac_data_out;
wire   half_counter=counter_in>>1;


always@(posedge clk_400M)
if(!rst_n)
	counter<=23'b0;
else if(counter>=(counter_in))begin
	counter<=23'b0;
end
else
	counter<=counter+1'b1;




always@(posedge clk_400M)
	if(!rst_n)
		address_reg<=7'd0;
	else if(counter==(counter_in))begin
		if(address_reg<=(11'h07cf-mult_in))
			address_reg<=address_reg+mult_in;
		else
			address_reg<=11'd0;
		adc_clock_reg<=1'b0;
	end
	else if(counter==half_counter)begin
		adc_clock_reg<=1'b1;
	end

endmodule
module dds_out
(
	input clk_400M,
	input rst_n,
	output [10:0] address,
	output adc_clock,
	output [13:0] dac_data_out,
	input [13:0] q,
	input [23:0] counter_in,
	input [11:0] mult_in
);


reg [23:0] counter;
reg [10:0] address_reg;
reg adc_clock_reg;

assign address=address_reg;
assign adc_clock=adc_clock_reg;
assign dac_data_out=(counter==(counter_in))?q:dac_data_out;
wire   half_counter=counter_in>>1;


always@(posedge clk_400M)
if(!rst_n)
	counter<=23'b0;
else if(counter>=(counter_in))begin
	counter<=23'b0;
end
else
	counter<=counter+1'b1;




always@(posedge clk_400M)
	if(!rst_n)
		address_reg<=7'd0;
	else if(counter==(counter_in))begin
		if(address_reg<=(11'h07cf-mult_in))
			address_reg<=address_reg+mult_in;
		else
			address_reg<=11'd0;
		adc_clock_reg<=1'b0;
	end
	else if(counter==half_counter)begin
		adc_clock_reg<=1'b1;
	end

endmodule