data/full_repos/permissive/104147155/player.v
 line:110: before: "."
1: b'%Warning-MULTITOP: data/full_repos/permissive/104147155/player.v:250: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'player\'\nmodule player\n       ^~~~~~\n                                                                    : ... Top module \'DelayCounter\'\nmodule DelayCounter (clock, resetn, enable, delay_out);\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/104147155/player.v:179: Operator SUB expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                 : ... In instance player.sizex\n     m <= m - 2\'b10;\n            ^\n%Error: data/full_repos/permissive/104147155/player.v:94: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter\n             data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.v\n             data/full_repos/permissive/104147155,data/full_repos/permissive/104147155/vga_adapter.sv\n             vga_adapter\n             vga_adapter.v\n             vga_adapter.sv\n             obj_dir/vga_adapter\n             obj_dir/vga_adapter.v\n             obj_dir/vga_adapter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module DelayCounter (clock, resetn, enable, delay_out);
	input clock;
	input resetn;
	input enable;
	output [19:0] delay_out;
	
	reg [19:0] m;
	always @(posedge clock)
	begin
		if (resetn == 1'b0)
			m <= 0;
		else if (enable == 1'b1)
			begin
				if (m == 20'd833400)
					m <= 0;
				else
				   m <= m + 1'b1;
			end
	end
	assign delay_out = m;
endmodule
module DelayCounter (clock, resetn, enable, delay_out);

	input clock;
	input resetn;
	input enable;
	output [19:0] delay_out;
	
	reg [19:0] m;
	always @(posedge clock)
	begin
		if (resetn == 1'b0)
			m <= 0;
		else if (enable == 1'b1)
			begin
				if (m == 20'd833400)
					m <= 0;
				else
				   m <= m + 1'b1;
			end
	end
	assign delay_out = m;
endmodule