data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Square_root/fp_Sqrt_tb.v
 line:47: before: "real"
1: b'%Error: Cannot find file containing module: Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Square_root/fp_Sqrt_tb.v\n%Error: Exiting due to 3 error(s)\n'
module fp_Sqrt_tb;

	parameter 
				WI = 4,
				WF = 4,
				WL = WI + WF,	 
				WIO = 4,
				WFO = 4,
				LUT_bits = 10,
				LUT_addWidth = 4;


	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din;


	wire [WL-1:0] dout;



	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction
	

	function real fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF-1; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		fixedToFloat = retVal - (in[WI+WF-1] * (2.0**(WI-1)));
		end
	endfunction



	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;



	real real_din;
	real real_dout;

	fp_Sqrt
	#
	(
		.WI(WI),
		.WF(WF),
		.WIO(WIO),
		.WFO(WFO),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth)
	)
	Fang_fp_Sqrt
	(
		.CLK(CLK), 
		.nRST(nRST), 
		.CE(CE), 
		.din(din), 
		.dout(dout)
	);

	initial begin
	



		


	





		




		$readmemb("LUT_sqrt_Hung_8bit.txt", fp_Sqrt_tb.Fang_fp_Sqrt.Fang_Square_Root_Hung.LUT);
		

		nRST = 0; CE = 0;
		@(posedge CLK); CE = 1; 
		nRST = 1;



		din = 10'b0001_1000; @(posedge CLK);
		din = 10'b0011_1100; @(posedge CLK);   
		din = 10'b0000_0011; @(posedge CLK);
		din = 10'b0000_0001; @(posedge CLK);
		din = 10'b0111_1111; @(posedge CLK);














		
		
		

		
		


		$finish;
        


	end


	always @ din real_din = fixedToFloat(din, WI, WF);


	always @ dout real_dout = fixedToFloat(dout, WIO, WFO);
      
endmodule
module fp_Sqrt_tb;


	parameter 
				WI = 4,
				WF = 4,
				WL = WI + WF,	 
				WIO = 4,
				WFO = 4,
				LUT_bits = 10,
				LUT_addWidth = 4;


	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din;


	wire [WL-1:0] dout;



	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction
	

	function real fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF-1; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		fixedToFloat = retVal - (in[WI+WF-1] * (2.0**(WI-1)));
		end
	endfunction



	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;



	real real_din;
	real real_dout;

	fp_Sqrt
	#
	(
		.WI(WI),
		.WF(WF),
		.WIO(WIO),
		.WFO(WFO),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth)
	)
	Fang_fp_Sqrt
	(
		.CLK(CLK), 
		.nRST(nRST), 
		.CE(CE), 
		.din(din), 
		.dout(dout)
	);

	initial begin
	



		


	





		




		$readmemb("LUT_sqrt_Hung_8bit.txt", fp_Sqrt_tb.Fang_fp_Sqrt.Fang_Square_Root_Hung.LUT);
		

		nRST = 0; CE = 0;
		@(posedge CLK); CE = 1; 
		nRST = 1;



		din = 10'b0001_1000; @(posedge CLK);
		din = 10'b0011_1100; @(posedge CLK);   
		din = 10'b0000_0011; @(posedge CLK);
		din = 10'b0000_0001; @(posedge CLK);
		din = 10'b0111_1111; @(posedge CLK);














		
		
		

		
		


		$finish;
        


	end


	always @ din real_din = fixedToFloat(din, WI, WF);


	always @ dout real_dout = fixedToFloat(dout, WIO, WFO);
      
endmodule