data/full_repos/permissive/106408053/verilog/gray.v
 line:47: before: "prototypes"
1: b"%Error: data/full_repos/permissive/106408053/verilog/gray.v:84: Can't find definition of variable: 'WIDTH'\nfunction [WIDTH-1:0] gray2bin;\n          ^~~~~\n%Error: Exiting due to 1 error(s)\n"
function [WIDTH-1:0] gray2bin;
input [WIDTH-1:0] gray;
integer i;
begin

  gray2bin[WIDTH-1] = gray[WIDTH-1];
  for (i=WIDTH-2; i>=0; i=i-1) gray2bin[i] = gray2bin[i+1]^gray[i];
end
endfunction
function [WIDTH-1:0] gray2bin;

input [WIDTH-1:0] gray;
integer i;
begin

  gray2bin[WIDTH-1] = gray[WIDTH-1];
  for (i=WIDTH-2; i>=0; i=i-1) gray2bin[i] = gray2bin[i+1]^gray[i];
end
endfunction