data/full_repos/permissive/125927162/MEMMUX/MEMMUX_tb.v
 line:73: before: "$"
1: b'%Error: data/full_repos/permissive/125927162/MEMMUX/MEMMUX_tb.v:49: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("MEMMUX.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/MEMMUX/MEMMUX_tb.v:50: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, DUT);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/MEMMUX/MEMMUX_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/MEMMUX/MEMMUX_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/MEMMUX/MEMMUX_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/MEMMUX/MEMMUX_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/MEMMUX/MEMMUX_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/MEMMUX/MEMMUX_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n   always #1 mADDR_M = mADDR_M + 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/MEMMUX/MEMMUX_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n   always #1 mADDR_V = mADDR_V + 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/MEMMUX/MEMMUX_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n   always #2 switch = !switch;\n          ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memmux_tb();
   localparam ADDR_WIDTH = 8;
   localparam DATA_WIDTH = 8;
   reg switch;
   reg [ADDR_WIDTH - 1:0] mADDR_M;
   reg [DATA_WIDTH - 1:0] mDATA_M;
   reg [ADDR_WIDTH - 1:0] mADDR_V;
   wire [DATA_WIDTH - 1:0] mDATA_V;

   wire [ADDR_WIDTH - 1:0] sADDR_A;
   wire [ADDR_WIDTH - 1:0] sADDR_B;
   
   wire [DATA_WIDTH - 1:0]  sDATA_A;
   wire [DATA_WIDTH - 1:0]  sDATA_B;

   reg 	[DATA_WIDTH - 1:0]  oDATA_A;
   reg 	[DATA_WIDTH - 1:0]  oDATA_B;
   
   memmux #(.ADDR_WIDTH(ADDR_WIDTH),
	    .DATA_WIDTH(DATA_WIDTH))
   DUT(
       .switch(switch),
       .mADDR_M(mADDR_M),
       .mDATA_M(mDATA_M),
       .mADDR_V(mADDR_V),
       .mDATA_V(mDATA_V),
       .sADDR_A(sADDR_A),
       .sDATA_A(sDATA_A),
       .sADDR_B(sADDR_B),
       .sDATA_B(sDATA_B)
       );
   
   initial begin
      $dumpfile("MEMMUX.vcd");
      $dumpvars(0, DUT);
      switch = 0;
      mADDR_M = 0;
      mDATA_M = 0;
      mADDR_V = 0;
      oDATA_A = 0;
      oDATA_B = 0;
      #1
      mADDR_M = {ADDR_WIDTH{1'b1}};
      mDATA_M = {DATA_WIDTH/4{4'b1010}};
      mADDR_V = {ADDR_WIDTH/2{2'b10}};
      oDATA_A = {DATA_WIDTH/2{2'b10}};
      oDATA_B = {DATA_WIDTH/2{2'b01}};
      #10
        switch = 1;
        oDATA_B = {DATA_WIDTH/2{2'b10}};
        oDATA_A = {DATA_WIDTH/2{2'b01}};
      #10
	mADDR_M = 0;
      mADDR_V = 0;
      #10
	switch = 0;
      #10
      $finish;   
   end

   assign sDATA_A = switch ? oDATA_A : {DATA_WIDTH{1'bZ}};
   assign sDATA_B = !switch ? oDATA_B : {DATA_WIDTH{1'bZ}};

   always #1 mADDR_M = mADDR_M + 1;
   always #1 mADDR_V = mADDR_V + 1;
   always #2 switch = !switch;

endmodule
module memmux_tb();

   localparam ADDR_WIDTH = 8;
   localparam DATA_WIDTH = 8;
   reg switch;
   reg [ADDR_WIDTH - 1:0] mADDR_M;
   reg [DATA_WIDTH - 1:0] mDATA_M;
   reg [ADDR_WIDTH - 1:0] mADDR_V;
   wire [DATA_WIDTH - 1:0] mDATA_V;

   wire [ADDR_WIDTH - 1:0] sADDR_A;
   wire [ADDR_WIDTH - 1:0] sADDR_B;
   
   wire [DATA_WIDTH - 1:0]  sDATA_A;
   wire [DATA_WIDTH - 1:0]  sDATA_B;

   reg 	[DATA_WIDTH - 1:0]  oDATA_A;
   reg 	[DATA_WIDTH - 1:0]  oDATA_B;
   
   memmux #(.ADDR_WIDTH(ADDR_WIDTH),
	    .DATA_WIDTH(DATA_WIDTH))
   DUT(
       .switch(switch),
       .mADDR_M(mADDR_M),
       .mDATA_M(mDATA_M),
       .mADDR_V(mADDR_V),
       .mDATA_V(mDATA_V),
       .sADDR_A(sADDR_A),
       .sDATA_A(sDATA_A),
       .sADDR_B(sADDR_B),
       .sDATA_B(sDATA_B)
       );
   
   initial begin
      $dumpfile("MEMMUX.vcd");
      $dumpvars(0, DUT);
      switch = 0;
      mADDR_M = 0;
      mDATA_M = 0;
      mADDR_V = 0;
      oDATA_A = 0;
      oDATA_B = 0;
      #1
      mADDR_M = {ADDR_WIDTH{1'b1}};
      mDATA_M = {DATA_WIDTH/4{4'b1010}};
      mADDR_V = {ADDR_WIDTH/2{2'b10}};
      oDATA_A = {DATA_WIDTH/2{2'b10}};
      oDATA_B = {DATA_WIDTH/2{2'b01}};
      #10
        switch = 1;
        oDATA_B = {DATA_WIDTH/2{2'b10}};
        oDATA_A = {DATA_WIDTH/2{2'b01}};
      #10
	mADDR_M = 0;
      mADDR_V = 0;
      #10
	switch = 0;
      #10
      $finish;   
   end

   assign sDATA_A = switch ? oDATA_A : {DATA_WIDTH{1'bZ}};
   assign sDATA_B = !switch ? oDATA_B : {DATA_WIDTH{1'bZ}};

   always #1 mADDR_M = mADDR_M + 1;
   always #1 mADDR_V = mADDR_V + 1;
   always #2 switch = !switch;

endmodule