data/full_repos/permissive/154352170/Forward.v
1: b"%Error: data/full_repos/permissive/154352170/Forward.v:207: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\n  output [2:0] type\n               ^~~~\n%Error: data/full_repos/permissive/154352170/Forward.v:214: syntax error, unexpected assign\n  assign type = type_temp;\n  ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Forward(
    input [31:0] IR_D,
	 input [31:0] IR_E,
	 input [31:0] IR_M,
	 input [31:0] IR_W,
	 output [1:0] ForwardRSD,
	 output [1:0] ForwardRTD,
	 output [1:0] ForwardRSE,
	 output [1:0] ForwardRTE,
	 output [1:0] ForwardRTM
    );
	 
	 wire [2:0] D_type;
	 wire [2:0] E_type;
	 wire [2:0] M_type;
	 wire [2:0] W_type;
	 
	 Type D_Type(IR_D, D_type);
	 Type E_Type(IR_E, E_type);
	 Type M_Type(IR_M, M_type);
	 Type W_Type(IR_W, W_type);
	 
	 reg [1:0] RSD;
	 reg [1:0] RTD;
	 reg [1:0] RSE;
	 reg [1:0] RTE;
	 reg [1:0] RTM;
	 
	 reg [2:0] test;
	 
	 assign ForwardRSD = RSD;
	 assign ForwardRTD = RTD;
	 assign ForwardRSE = RSE;
	 assign ForwardRTE = RTE;
	 assign ForwardRTM = RTM;
	 
	 initial begin
	    RSD <= 2'b00;
		 RTD <= 2'b00;
		 RSE <= 2'b00;
		 RTE <= 2'b00;
		 RTM <= 2'b00;
	 end
	  
	 always @ (*) begin
	    

		 if (D_type == 3'b011 | D_type == 3'b110) begin
		    
			 if (M_type == 3'b001 & IR_D[`rs] != 0 & IR_D[`rs] == IR_M[`rd])
				 RSD <= 2'b01;
	
			 else if (M_type == 3'b010 & IR_D[`rs] != 0 & IR_D[`rs] == IR_M[`rt])
				 RSD <= 2'b01;
							 
			 else if (M_type == 3'b111 & IR_D[`rs] != 0 & IR_D[`rs] == 5'b11111)
				 RSD <= 2'b10;

			 else
				 RSD <= 2'b00;

		 end
		
		 else 
		    RSD <= 2'b00;
			 

		 if (D_type == 3'b011) begin
		    
			 if (M_type == 3'b001 & IR_D[`rt] != 0 & IR_D[`rt] == IR_M[`rd])
			    RTD <= 2'b01;
			 
			 else if (M_type == 3'b010 & IR_D[`rt] != 0 & IR_D[`rt] == IR_M[`rt])
			    RTD <= 2'b01;
			 
			 else if (M_type == 3'b111 & IR_D[`rt] != 0 & IR_D[`rt] == 5'b11111)
			    RTD <= 2'b10;
		    
			 else
			    RTD <= 2'b00;
		 
		 end
		 
		 else
		    RTD <= 2'b00;
		

		  if (E_type == 3'b001 | E_type == 3'b010 | E_type == 3'b100 | E_type == 3'b101) begin
		     
			  if (M_type == 3'b001 & IR_E[`rs] != 0 & IR_E[`rs] == IR_M[`rd])
			     RSE <= 2'b01;
			  
			  else if (M_type == 3'b010 & IR_E[`rs] != 0 & IR_E[`rs] == IR_M[`rt])
			     RSE <= 2'b01;
				  
			  else if (W_type == 3'b001 & IR_E[`rs] != 0 & IR_E[`rs] == IR_W[`rd])
			     RSE <= 2'b10;
			  
			  else if (W_type == 3'b010 & IR_E[`rs] != 0 & IR_E[`rs] == IR_W[`rt])
			     RSE <= 2'b10;
			  
			  else if (W_type == 3'b111 & IR_E[`rs] != 0 & IR_E[`rs] == 5'b11111)
			     RSE <= 2'b10;
			  
			  else if (W_type == 3'b100 & IR_E[`rs] != 0 & IR_E[`rs] == IR_W[`rt])
			     RSE <= 2'b10;
			  
			  else if (M_type == 3'b111 & IR_E[`rs] != 0 & IR_E[`rs] == 5'b11111)
			     RSE <= 2'b11;
			  
			  else
		        RSE <= 2'b00;
				 
		  end
		  
		  else
		     RSE <= 2'b00;
			  

		 if (E_type == 3'b001 | E_type == 3'b101) begin
		    			 
          if (M_type == 3'b001 & IR_E[`rt] != 0 & IR_E[`rt] == IR_M[`rd])
			    RTE <= 2'b10;
			 
			 else if (M_type == 3'b010 & IR_E[`rt] != 0 & IR_E[`rt] == IR_M[`rt])
			    RTE <= 2'b10;
			 
			 else if (M_type == 3'b111 & IR_E[`rt] != 0 & IR_E[`rt] == 5'b11111)
			     RTE <= 2'b11;
			 
			 else if (W_type == 3'b001 & IR_E[`rt] != 0 & IR_E[`rt] == IR_W[`rd])
			     RTE <= 2'b01;
				 
			 else if (W_type == 3'b010 & IR_E[`rt] != 0 & IR_E[`rt] == IR_W[`rt])
			     RTE <= 2'b01;

			 else if (W_type == 3'b111 & IR_E[`rt] != 0 & IR_E[`rt] == 5'b11111)
			     RTE <= 2'b01;
				 
			 else if (W_type == 3'b100 & IR_E[`rt] != 0 & IR_E[`rt] == IR_W[`rt])
			     RTE <= 2'b01;
				  
			 else
			    RTE <= 2'b00;
			 
		 end
		 
		 else
		    RTE <= 2'b00;
			 		  

		 if (M_type == 3'b101) begin
          
			 if (W_type == 3'b001 & IR_M[`rt] != 0 & IR_M[`rt] == IR_W[`rd])
			    RTM <= 2'b01;
			 
			 else if (W_type == 3'b010 & IR_M[`rt] != 0 & IR_M[`rt] == IR_W[`rt])
			    RTM <= 2'b01;
				 
			 else if (W_type == 3'b100 & IR_M[`rt] != 0 & IR_M[`rt] == IR_W[`rt])
			    RTM <= 2'b01;
			 
			 else if (W_type == 3'b111 & IR_M[`rt] != 0 & IR_M[`rt] == 5'b11111)
			    RTM <= 2'b01;
				 
			 else
			    RTM <= 2'b00;
				 
		 end
		 
		 else
		    RTM <= 2'b00;
		    
	 end
	 

endmodule
module Forward(
    input [31:0] IR_D,
	 input [31:0] IR_E,
	 input [31:0] IR_M,
	 input [31:0] IR_W,
	 output [1:0] ForwardRSD,
	 output [1:0] ForwardRTD,
	 output [1:0] ForwardRSE,
	 output [1:0] ForwardRTE,
	 output [1:0] ForwardRTM
    );

	 
	 wire [2:0] D_type;
	 wire [2:0] E_type;
	 wire [2:0] M_type;
	 wire [2:0] W_type;
	 
	 Type D_Type(IR_D, D_type);
	 Type E_Type(IR_E, E_type);
	 Type M_Type(IR_M, M_type);
	 Type W_Type(IR_W, W_type);
	 
	 reg [1:0] RSD;
	 reg [1:0] RTD;
	 reg [1:0] RSE;
	 reg [1:0] RTE;
	 reg [1:0] RTM;
	 
	 reg [2:0] test;
	 
	 assign ForwardRSD = RSD;
	 assign ForwardRTD = RTD;
	 assign ForwardRSE = RSE;
	 assign ForwardRTE = RTE;
	 assign ForwardRTM = RTM;
	 
	 initial begin
	    RSD <= 2'b00;
		 RTD <= 2'b00;
		 RSE <= 2'b00;
		 RTE <= 2'b00;
		 RTM <= 2'b00;
	 end
	  
	 always @ (*) begin
	    

		 if (D_type == 3'b011 | D_type == 3'b110) begin
		    
			 if (M_type == 3'b001 & IR_D[`rs] != 0 & IR_D[`rs] == IR_M[`rd])
				 RSD <= 2'b01;
	
			 else if (M_type == 3'b010 & IR_D[`rs] != 0 & IR_D[`rs] == IR_M[`rt])
				 RSD <= 2'b01;
							 
			 else if (M_type == 3'b111 & IR_D[`rs] != 0 & IR_D[`rs] == 5'b11111)
				 RSD <= 2'b10;

			 else
				 RSD <= 2'b00;

		 end
		
		 else 
		    RSD <= 2'b00;
			 

		 if (D_type == 3'b011) begin
		    
			 if (M_type == 3'b001 & IR_D[`rt] != 0 & IR_D[`rt] == IR_M[`rd])
			    RTD <= 2'b01;
			 
			 else if (M_type == 3'b010 & IR_D[`rt] != 0 & IR_D[`rt] == IR_M[`rt])
			    RTD <= 2'b01;
			 
			 else if (M_type == 3'b111 & IR_D[`rt] != 0 & IR_D[`rt] == 5'b11111)
			    RTD <= 2'b10;
		    
			 else
			    RTD <= 2'b00;
		 
		 end
		 
		 else
		    RTD <= 2'b00;
		

		  if (E_type == 3'b001 | E_type == 3'b010 | E_type == 3'b100 | E_type == 3'b101) begin
		     
			  if (M_type == 3'b001 & IR_E[`rs] != 0 & IR_E[`rs] == IR_M[`rd])
			     RSE <= 2'b01;
			  
			  else if (M_type == 3'b010 & IR_E[`rs] != 0 & IR_E[`rs] == IR_M[`rt])
			     RSE <= 2'b01;
				  
			  else if (W_type == 3'b001 & IR_E[`rs] != 0 & IR_E[`rs] == IR_W[`rd])
			     RSE <= 2'b10;
			  
			  else if (W_type == 3'b010 & IR_E[`rs] != 0 & IR_E[`rs] == IR_W[`rt])
			     RSE <= 2'b10;
			  
			  else if (W_type == 3'b111 & IR_E[`rs] != 0 & IR_E[`rs] == 5'b11111)
			     RSE <= 2'b10;
			  
			  else if (W_type == 3'b100 & IR_E[`rs] != 0 & IR_E[`rs] == IR_W[`rt])
			     RSE <= 2'b10;
			  
			  else if (M_type == 3'b111 & IR_E[`rs] != 0 & IR_E[`rs] == 5'b11111)
			     RSE <= 2'b11;
			  
			  else
		        RSE <= 2'b00;
				 
		  end
		  
		  else
		     RSE <= 2'b00;
			  

		 if (E_type == 3'b001 | E_type == 3'b101) begin
		    			 
          if (M_type == 3'b001 & IR_E[`rt] != 0 & IR_E[`rt] == IR_M[`rd])
			    RTE <= 2'b10;
			 
			 else if (M_type == 3'b010 & IR_E[`rt] != 0 & IR_E[`rt] == IR_M[`rt])
			    RTE <= 2'b10;
			 
			 else if (M_type == 3'b111 & IR_E[`rt] != 0 & IR_E[`rt] == 5'b11111)
			     RTE <= 2'b11;
			 
			 else if (W_type == 3'b001 & IR_E[`rt] != 0 & IR_E[`rt] == IR_W[`rd])
			     RTE <= 2'b01;
				 
			 else if (W_type == 3'b010 & IR_E[`rt] != 0 & IR_E[`rt] == IR_W[`rt])
			     RTE <= 2'b01;

			 else if (W_type == 3'b111 & IR_E[`rt] != 0 & IR_E[`rt] == 5'b11111)
			     RTE <= 2'b01;
				 
			 else if (W_type == 3'b100 & IR_E[`rt] != 0 & IR_E[`rt] == IR_W[`rt])
			     RTE <= 2'b01;
				  
			 else
			    RTE <= 2'b00;
			 
		 end
		 
		 else
		    RTE <= 2'b00;
			 		  

		 if (M_type == 3'b101) begin
          
			 if (W_type == 3'b001 & IR_M[`rt] != 0 & IR_M[`rt] == IR_W[`rd])
			    RTM <= 2'b01;
			 
			 else if (W_type == 3'b010 & IR_M[`rt] != 0 & IR_M[`rt] == IR_W[`rt])
			    RTM <= 2'b01;
				 
			 else if (W_type == 3'b100 & IR_M[`rt] != 0 & IR_M[`rt] == IR_W[`rt])
			    RTM <= 2'b01;
			 
			 else if (W_type == 3'b111 & IR_M[`rt] != 0 & IR_M[`rt] == 5'b11111)
			    RTM <= 2'b01;
				 
			 else
			    RTM <= 2'b00;
				 
		 end
		 
		 else
		    RTM <= 2'b00;
		    
	 end
	 

endmodule