data/full_repos/permissive/107007139/Lab 2/my_4_bit_full_adder_simulation.v
1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/107007139\n        ... Looked in:\n             data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139\n             data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.v\n             data/full_repos/permissive/107007139/Lab/2,data/full_repos/permissive/107007139.sv\n             2,data/full_repos/permissive/107007139\n             2,data/full_repos/permissive/107007139.v\n             2,data/full_repos/permissive/107007139.sv\n             obj_dir/2,data/full_repos/permissive/107007139\n             obj_dir/2,data/full_repos/permissive/107007139.v\n             obj_dir/2,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 2/my_4_bit_full_adder_simulation.v\n%Error: Exiting due to 3 error(s)\n'
module my_4_bit_full_adder_simulation(

    );
    

    reg [3:0] A;
    reg [3:0] B;
    reg CIN;
    

    wire [3:0] S;
    wire COUT;
    

    my_4_bit_full_adder dut(A, B, CIN, S, COUT);
    
    initial begin
        A = 4'b0011; B = 4'b0011; CIN = 1'b0; #10;
        A = 4'b1011; B = 4'b0111; CIN = 1'b0; #10;
        A = 4'b1111; B = 4'b1111; CIN = 1'b0; #10;
    end
endmodule
module my_4_bit_full_adder_simulation(

    );

    

    reg [3:0] A;
    reg [3:0] B;
    reg CIN;
    

    wire [3:0] S;
    wire COUT;
    

    my_4_bit_full_adder dut(A, B, CIN, S, COUT);
    
    initial begin
        A = 4'b0011; B = 4'b0011; CIN = 1'b0; #10;
        A = 4'b1011; B = 4'b0111; CIN = 1'b0; #10;
        A = 4'b1111; B = 4'b1111; CIN = 1'b0; #10;
    end
endmodule