data/full_repos/permissive/156415315/FlashingLED/tb_FlashingLED.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/156415315/FlashingLED/tb_FlashingLED.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156415315/FlashingLED/tb_FlashingLED.v:61: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD/2) clk = 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156415315/FlashingLED/tb_FlashingLED.v:62: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD/2);\n      ^\n%Error: data/full_repos/permissive/156415315/FlashingLED/tb_FlashingLED.v:37: Cannot find file containing module: \'FlashingLED\'\n FlashingLED uut (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156415315/FlashingLED,data/full_repos/permissive/156415315/FlashingLED\n             data/full_repos/permissive/156415315/FlashingLED,data/full_repos/permissive/156415315/FlashingLED.v\n             data/full_repos/permissive/156415315/FlashingLED,data/full_repos/permissive/156415315/FlashingLED.sv\n             FlashingLED\n             FlashingLED.v\n             FlashingLED.sv\n             obj_dir/FlashingLED\n             obj_dir/FlashingLED.v\n             obj_dir/FlashingLED.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_FlashingLED;


	reg clk;
	reg rst;


   			

	wire led_out;


	FlashingLED uut (
		.clk(clk), 
		.rst(rst), 
		.led_out(led_out)
	);

	initial begin

		clk = 0;
		rst = 1;


		#100;
        

		rst = 0;
	end
	

	parameter PERIOD = 20;
	

	always begin
      clk = 1'b0;
      #(PERIOD/2) clk = 1'b1;
      #(PERIOD/2);
   end  
      
endmodule
module tb_FlashingLED;



	reg clk;
	reg rst;


   			

	wire led_out;


	FlashingLED uut (
		.clk(clk), 
		.rst(rst), 
		.led_out(led_out)
	);

	initial begin

		clk = 0;
		rst = 1;


		#100;
        

		rst = 0;
	end
	

	parameter PERIOD = 20;
	

	always begin
      clk = 1'b0;
      #(PERIOD/2) clk = 1'b1;
      #(PERIOD/2);
   end  
      
endmodule