data/full_repos/permissive/128426084/src/sim_1/imports/project_1/psx_clk_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/128426084/src/sim_1/imports/project_1/psx_clk_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/128426084/src/sim_1/imports/project_1/psx_clk_test.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: data/full_repos/permissive/128426084/src/sim_1/imports/project_1/psx_clk_test.v:36: Cannot find file containing module: \'psx_controller_clk_gen\'\npsx_controller_clk_gen myPsx\n^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128426084/src/sim_1/imports/project_1,data/full_repos/permissive/128426084/psx_controller_clk_gen\n             data/full_repos/permissive/128426084/src/sim_1/imports/project_1,data/full_repos/permissive/128426084/psx_controller_clk_gen.v\n             data/full_repos/permissive/128426084/src/sim_1/imports/project_1,data/full_repos/permissive/128426084/psx_controller_clk_gen.sv\n             psx_controller_clk_gen\n             psx_controller_clk_gen.v\n             psx_controller_clk_gen.sv\n             obj_dir/psx_controller_clk_gen\n             obj_dir/psx_controller_clk_gen.v\n             obj_dir/psx_controller_clk_gen.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module psx_clk_test;

reg clk;
wire [3:0] BytesExpected;
wire [3:0] c_counter;
wire c_clk,READY,gen,rst;
reg [32:0] counter =0 ; 
reg ack =1;
reg [3:0] mask_counter = 1;
reg[3:0] delay = 0;
wire err_f;
 

psx_controller_clk_gen myPsx
(
    .clk(clk),
    .gen(gen),
    .rst(!gen),
    .BytesExpected(BytesExpected),
    .c_clk(c_clk),
    .c_counter(c_counter),
    .READY(READY),
    .err_f(err_f),
    .ack(ack)
    
);

  always
  begin
    
    clk = 1'b0;
    #5;
    clk = 1'b1;
    #5;
    counter  = counter +1;
    
  end
  
  always @(posedge clk)
    if(mask_counter == c_counter)
        begin
            if(ack)
                    ack = 0;
            else if(ack == 0)
                if(delay == 3)
                    begin
                        ack = 1 ;
                        delay = 0;
                        mask_counter = mask_counter +1;
                    end
                else
                    delay = delay +1;              
        end
      else if(mask_counter == 4'ha)
        begin 
            mask_counter = 0;
            counter  = 0;
            delay = 0;
        end
        else if(mask_counter > 9)
            ack = 1;
        
  
  
  
assign gen = (counter > 25)? 1 :0;
assign BytesExpected = (c_counter >= 2)? 9  : 5;



endmodule
module psx_clk_test;


reg clk;
wire [3:0] BytesExpected;
wire [3:0] c_counter;
wire c_clk,READY,gen,rst;
reg [32:0] counter =0 ; 
reg ack =1;
reg [3:0] mask_counter = 1;
reg[3:0] delay = 0;
wire err_f;
 

psx_controller_clk_gen myPsx
(
    .clk(clk),
    .gen(gen),
    .rst(!gen),
    .BytesExpected(BytesExpected),
    .c_clk(c_clk),
    .c_counter(c_counter),
    .READY(READY),
    .err_f(err_f),
    .ack(ack)
    
);

  always
  begin
    
    clk = 1'b0;
    #5;
    clk = 1'b1;
    #5;
    counter  = counter +1;
    
  end
  
  always @(posedge clk)
    if(mask_counter == c_counter)
        begin
            if(ack)
                    ack = 0;
            else if(ack == 0)
                if(delay == 3)
                    begin
                        ack = 1 ;
                        delay = 0;
                        mask_counter = mask_counter +1;
                    end
                else
                    delay = delay +1;              
        end
      else if(mask_counter == 4'ha)
        begin 
            mask_counter = 0;
            counter  = 0;
            delay = 0;
        end
        else if(mask_counter > 9)
            ack = 1;
        
  
  
  
assign gen = (counter > 25)? 1 :0;
assign BytesExpected = (c_counter >= 2)? 9  : 5;



endmodule