data/full_repos/permissive/14432793/OLD/I2C/I2C_testbench.v
 line:16: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/I2C_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk = ~clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/I2C_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #1000\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/I2C_testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #2000\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/I2C_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #5000\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/I2C_testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #100000 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14432793/OLD/I2C/I2C_testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #30000\n      ^\n%Error: data/full_repos/permissive/14432793/OLD/I2C/I2C_testbench.v:24: Cannot find file containing module: \'master\'\n  master u1 (address, register, refresh_clk, sys_clk, mode, en, reset, Start, Stop, repeat_start, out, ack, sda, scl);\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/14432793/OLD/I2C,data/full_repos/permissive/14432793/master\n             data/full_repos/permissive/14432793/OLD/I2C,data/full_repos/permissive/14432793/master.v\n             data/full_repos/permissive/14432793/OLD/I2C,data/full_repos/permissive/14432793/master.sv\n             master\n             master.v\n             master.sv\n             obj_dir/master\n             obj_dir/master.v\n             obj_dir/master.sv\n%Error: data/full_repos/permissive/14432793/OLD/I2C/I2C_testbench.v:25: Cannot find file containing module: \'slave\'\n  slave u2 (address, measurement, en, reset, scl, sda);\n  ^~~~~\n%Error: data/full_repos/permissive/14432793/OLD/I2C/I2C_testbench.v:26: Cannot find file containing module: \'clock_divider\'\n  clock_divider u3 (clk, reset, en, refresh_clk, sys_clk); \n  ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module I2C_testbench();
  reg [6:0] address;
  reg [7:0] register; 
  reg clk;
  wire sys_clk;
  wire refresh_clk;
  reg mode;
  reg en;
  reg reset;
  reg Start;
  reg Stop;
  reg repeat_start;
  wire [7:0] out; 
  tri1 sda;
  tri1 scl;
  wire ack;
  
  wire sda_master, sda_slave;
  reg sda_master_reg, sda_slave_reg;
  reg[7:0] measurement;

  master u1 (address, register, refresh_clk, sys_clk, mode, en, reset, Start, Stop, repeat_start, out, ack, sda, scl);
  slave u2 (address, measurement, en, reset, scl, sda);
  clock_divider u3 (clk, reset, en, refresh_clk, sys_clk); 

  always
    begin
      #5 clk = ~clk;
    end

  initial
    begin
      address = 7'b1110001;
      register = 8'b11111111;
      measurement = 8'b11110000;
      clk = 1;
      mode = 1;
      en = 0;
      Stop = 0;
      Start = 0;
      reset = 1;
      repeat_start = 0;
      #1000
      reset = 0;
      #2000
      reset = 1;
      en = 1;
      #5000
      Start = 1;
      #100000 
      Stop = 1;
      #30000
      $finish;
    end
endmodule
module I2C_testbench();

  reg [6:0] address;
  reg [7:0] register; 
  reg clk;
  wire sys_clk;
  wire refresh_clk;
  reg mode;
  reg en;
  reg reset;
  reg Start;
  reg Stop;
  reg repeat_start;
  wire [7:0] out; 
  tri1 sda;
  tri1 scl;
  wire ack;
  
  wire sda_master, sda_slave;
  reg sda_master_reg, sda_slave_reg;
  reg[7:0] measurement;

  master u1 (address, register, refresh_clk, sys_clk, mode, en, reset, Start, Stop, repeat_start, out, ack, sda, scl);
  slave u2 (address, measurement, en, reset, scl, sda);
  clock_divider u3 (clk, reset, en, refresh_clk, sys_clk); 

  always
    begin
      #5 clk = ~clk;
    end

  initial
    begin
      address = 7'b1110001;
      register = 8'b11111111;
      measurement = 8'b11110000;
      clk = 1;
      mode = 1;
      en = 0;
      Stop = 0;
      Start = 0;
      reset = 1;
      repeat_start = 0;
      #1000
      reset = 0;
      #2000
      reset = 1;
      en = 1;
      #5000
      Start = 1;
      #100000 
      Stop = 1;
      #30000
      $finish;
    end
endmodule