data/full_repos/permissive/143278/ivltests/vhdl_case_multi.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_case_multi.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_case_multi.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_case_multi.v:24: Cannot find file containing module: \'vhdl_case_multi\'\n  vhdl_case_multi dut(test_vec, parity);\n  ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_case_multi\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_case_multi.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_case_multi.sv\n             vhdl_case_multi\n             vhdl_case_multi.v\n             vhdl_case_multi.sv\n             obj_dir/vhdl_case_multi\n             obj_dir/vhdl_case_multi.v\n             obj_dir/vhdl_case_multi.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vhdl_case_multi_test;
  reg [2:0] test_vec;
  reg parity;
  vhdl_case_multi dut(test_vec, parity);

  initial begin

    test_vec = 'b101;
    #1;
    if(parity !== 1'b0) begin
        $display("FAILED 1");
        $finish();
    end

    test_vec = 'b001;
    #1;
    if(parity !== 1'b1) begin
        $display("FAILED 2");
        $finish();
    end

    $display("PASSED");
  end
endmodule
module vhdl_case_multi_test;

  reg [2:0] test_vec;
  reg parity;
  vhdl_case_multi dut(test_vec, parity);

  initial begin

    test_vec = 'b101;
    #1;
    if(parity !== 1'b0) begin
        $display("FAILED 1");
        $finish();
    end

    test_vec = 'b001;
    #1;
    if(parity !== 1'b1) begin
        $display("FAILED 2");
        $finish();
    end

    $display("PASSED");
  end
endmodule