data/full_repos/permissive/132220215/tb.v
data/verilator_xmls/97b9d736-8276-45e5-b94f-a10d9fc23087.xml
module Full_Adder(
	output C_out,sum,
	input C_in,A,B);

assign sum = C_in ^ A ^ B;
assign C_out =( C_in & (A ^ B))|(A&B);
endmodule
module Full_Adder(
	output C_out,sum,
	input C_in,A,B);


assign sum = C_in ^ A ^ B;
assign C_out =( C_in & (A ^ B))|(A&B);
endmodule