data/full_repos/permissive/176628218/output.v
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data/verilator_xmls/f6322518-f25d-4d8c-ac08-a3cd912b0063.xml
module  FSM_output(
    input [2:0]status,
    output reg power_led,
    output reg money_led,
    output reg get_led,
    output reg back_led);
    
    always@ (status) begin
        case (status)
        3'b000: begin
            power_led = 0;
            money_led = 0;
            get_led = 0;
            back_led = 0;
        end
        3'b001: begin
            power_led = 1;
            money_led = 0;
            get_led = 0;
            back_led = 0;
        end
        3'b010: begin
            power_led = 1;
            money_led = 1;
            get_led = 0;
            back_led = 0;
        end
        
        3'b011: begin
            power_led = 1;
            money_led = 1;
            get_led = 0;
            back_led = 0;
        end
        
        3'b100: begin
            power_led = 1;
            money_led = 1;
            get_led = 0;
            back_led = 0;
        end
        
        3'b101: begin
            power_led = 1;
            money_led = 0;
            get_led = 1;
            back_led = 0;
        end
        
        3'b110: begin
            power_led = 1;
            money_led = 0;
            get_led = 0;
            back_led = 1;
        end
                
        default: begin
            power_led = 0;
            money_led = 0;
            get_led = 0;
            back_led = 0;
        end
        
        
        endcase
    end

endmodule
module  FSM_output(
    input [2:0]status,
    output reg power_led,
    output reg money_led,
    output reg get_led,
    output reg back_led);

    
    always@ (status) begin
        case (status)
        3'b000: begin
            power_led = 0;
            money_led = 0;
            get_led = 0;
            back_led = 0;
        end
        3'b001: begin
            power_led = 1;
            money_led = 0;
            get_led = 0;
            back_led = 0;
        end
        3'b010: begin
            power_led = 1;
            money_led = 1;
            get_led = 0;
            back_led = 0;
        end
        
        3'b011: begin
            power_led = 1;
            money_led = 1;
            get_led = 0;
            back_led = 0;
        end
        
        3'b100: begin
            power_led = 1;
            money_led = 1;
            get_led = 0;
            back_led = 0;
        end
        
        3'b101: begin
            power_led = 1;
            money_led = 0;
            get_led = 1;
            back_led = 0;
        end
        
        3'b110: begin
            power_led = 1;
            money_led = 0;
            get_led = 0;
            back_led = 1;
        end
                
        default: begin
            power_led = 0;
            money_led = 0;
            get_led = 0;
            back_led = 0;
        end
        
        
        endcase
    end

endmodule