data/full_repos/permissive/212495825/src/gaplus_io.v
1: b'%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:356: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'INP\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h0: out <= INP;  \n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:357: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h1: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'hF;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:357: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h1: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'hF;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'he\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:359: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h3: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'h1;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:359: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'h1\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h3: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'h1;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:276: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_add\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp1\n    regs[4\'h0] <= credit_add;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:277: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_sub\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp1\n    regs[4\'h1] <= credit_sub;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:144: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_add\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp0\n    regs[4\'h2] <= credit_add;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:145: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_sub\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp0\n    regs[4\'h3] <= credit_sub;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:46: Output port connection \'rd\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'iocust_rd\' generates 4 bits.\n                                                                       : ... In instance GAPLUS_IO\nGAPLUS_IO_CUS2 iocust( reset, clk, iocust_cs, cpu_ad[3:0], iocust_rd, cpu_wd, cpu_wr,  pcm_kick, INP2 );\n                                                           ^~~~~~~~~\n%Error: Exiting due to 13 warning(s)\n'
module add3(in,out);

input [3:0] in;
output [3:0] out;
reg [3:0] out;

always @ (in)
	case (in)
	4'b0000: out <= 4'b0000;
	4'b0001: out <= 4'b0001;
	4'b0010: out <= 4'b0010;
	4'b0011: out <= 4'b0011;
	4'b0100: out <= 4'b0100;
	4'b0101: out <= 4'b1000;
	4'b0110: out <= 4'b1001;
	4'b0111: out <= 4'b1010;
	4'b1000: out <= 4'b1011;
	4'b1001: out <= 4'b1100;
	default: out <= 4'b0000;
	endcase

endmodule
module add3(in,out);


input [3:0] in;
output [3:0] out;
reg [3:0] out;

always @ (in)
	case (in)
	4'b0000: out <= 4'b0000;
	4'b0001: out <= 4'b0001;
	4'b0010: out <= 4'b0010;
	4'b0011: out <= 4'b0011;
	4'b0100: out <= 4'b0100;
	4'b0101: out <= 4'b1000;
	4'b0110: out <= 4'b1001;
	4'b0111: out <= 4'b1010;
	4'b1000: out <= 4'b1011;
	4'b1001: out <= 4'b1100;
	default: out <= 4'b0000;
	endcase

endmodule