data/full_repos/permissive/119715647/sim/Timer/reconfigTmr8B_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/reconfigTmr8B_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/reconfigTmr8B_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119715647/sim/Timer/reconfigTmr8B_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #13;\n    ^\n%Error: data/full_repos/permissive/119715647/sim/Timer/reconfigTmr8B_tb.v:8: Cannot find file containing module: \'reconfigTmr8B\'\n  reconfigTmr8B DUT_rTmr(rst, pulseClk, timeAdj, pulseROut);\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119715647/sim/Timer,data/full_repos/permissive/119715647/reconfigTmr8B\n             data/full_repos/permissive/119715647/sim/Timer,data/full_repos/permissive/119715647/reconfigTmr8B.v\n             data/full_repos/permissive/119715647/sim/Timer,data/full_repos/permissive/119715647/reconfigTmr8B.sv\n             reconfigTmr8B\n             reconfigTmr8B.v\n             reconfigTmr8B.sv\n             obj_dir/reconfigTmr8B\n             obj_dir/reconfigTmr8B.v\n             obj_dir/reconfigTmr8B.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reconfigTmr8B_tb();
  reg pulseClk;
  reg rst;
  reg [7:0] timeAdj;
  wire pulseROut;

  reconfigTmr8B DUT_rTmr(rst, pulseClk, timeAdj, pulseROut);

  always begin
    pulseClk = 1;
    #10;
    pulseClk = 0;
    #10;
  end

  initial begin
    timeAdj = 8'b11001000;
    rst = 0;
    #13;
    rst = 1;
  end
endmodule
module reconfigTmr8B_tb();

  reg pulseClk;
  reg rst;
  reg [7:0] timeAdj;
  wire pulseROut;

  reconfigTmr8B DUT_rTmr(rst, pulseClk, timeAdj, pulseROut);

  always begin
    pulseClk = 1;
    #10;
    pulseClk = 0;
    #10;
  end

  initial begin
    timeAdj = 8'b11001000;
    rst = 0;
    #13;
    rst = 1;
  end
endmodule