data/full_repos/permissive/169522605/hw3_1/mux2_1.v
data/verilator_xmls/3f0c6ed5-c266-4aa9-bfaf-fcb8acbe4f0d.xml
module mux2_1(InA, InB, S, Out);
    input   InA, InB;
    input   S;
    output  Out;



endmodule
module mux2_1(InA, InB, S, Out);

    input   InA, InB;
    input   S;
    output  Out;



endmodule