data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v
 line:78: before: "@"
1: b'%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:68: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("FromCLBToChannelBusJunction_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:69: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_clb_out, w_ch_up_n, w_ch_dn_s, inst);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:78: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:83: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:86: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:91: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:95: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:100: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:104: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:109: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:113: syntax error, unexpected \'@\'\n  #50@(posedge r_clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #50@(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:117: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:122: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:126: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:131: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:135: syntax error, unexpected \'@\'\n  #50@(posedge r_clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #50@(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:139: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:144: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:148: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:153: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:157: syntax error, unexpected \'@\'\n  #50@(posedge r_clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n  #50@(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:161: syntax error, unexpected \'@\'\n  #100 @(posedge r_clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n  #100 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:166: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:170: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:175: syntax error, unexpected \'@\'\n  #50 @(posedge r_clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #50 @(posedge r_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #50 r_clk <= ~r_clk;\n  ^\n%Error: Exiting due to 25 error(s), 24 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FromCLBToChannelBusJunction_tb;

	reg r_clk;
	reg r_mode;
	reg [16:0] r_c_bus;
	reg [1:0] r_c_dimension;
	reg [1:0] r_ch_up_s;
	reg [1:0] r_ch_dn_n;
	reg r_clb_out;
	wire [1:0] w_ch_up_n;
	wire [1:0] w_ch_dn_s;
	
	FromCLBToChannelBusJunction#(4, 2, 2, 2) inst(
		.mode(r_mode),
		.c_bus(r_c_bus),
		.c_dimension(r_c_dimension),

		.ch_up_n(w_ch_up_n),
		.ch_up_s(r_ch_up_s),
		.ch_dn_n(r_ch_dn_n),
		.ch_dn_s(w_ch_dn_s),
		.clb_out(r_clb_out)
	);


















	initial begin
		$dumpfile("FromCLBToChannelBusJunction_tb.vcd");
		$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_clb_out, w_ch_up_n, w_ch_dn_s, inst);
		r_clk <= 'b1;
		r_mode <= 'b0;
		r_c_bus <= 'h0;
		r_c_dimension <= 'h0;
		r_ch_up_s <= 'h3;
		r_ch_dn_n <= 'h3;
		r_clb_out <= 'b0;

		#100 @(posedge r_clk);

		r_mode <= 'b1;


		#50 @(posedge r_clk);

		r_c_bus <= {1'b0, 8'b10000011, 8'b10000111};
		#50 @(posedge r_clk);



		r_c_bus <= {1'b1, 8'b10000011, 8'b10000111};
		#50 @(posedge r_clk);

		r_c_bus <= {1'b0, 8'b10000011, 8'b10000111};

		#100 @(posedge r_clk);

		r_mode <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b1;



		#100 @(posedge r_clk);

		r_mode <= 'b1;

		#50@(posedge r_clk);

		r_c_dimension <= 'h1;

		#100 @(posedge r_clk);

		r_mode <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b1;



		#100 @(posedge r_clk);

		r_mode <= 'b1;

		#50@(posedge r_clk);

		r_c_dimension <= 'h2;

		#100 @(posedge r_clk);

		r_mode <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b1;



		#100 @(posedge r_clk);

		r_mode <= 'b1;

		#50@(posedge r_clk);

		r_c_dimension <= 'h3;

		#100 @(posedge r_clk);

		r_mode <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b1;



		#50 @(posedge r_clk);
		$finish;
	end

	always begin
		#50 r_clk <= ~r_clk;
	end

endmodule
module FromCLBToChannelBusJunction_tb;


	reg r_clk;
	reg r_mode;
	reg [16:0] r_c_bus;
	reg [1:0] r_c_dimension;
	reg [1:0] r_ch_up_s;
	reg [1:0] r_ch_dn_n;
	reg r_clb_out;
	wire [1:0] w_ch_up_n;
	wire [1:0] w_ch_dn_s;
	
	FromCLBToChannelBusJunction#(4, 2, 2, 2) inst(
		.mode(r_mode),
		.c_bus(r_c_bus),
		.c_dimension(r_c_dimension),

		.ch_up_n(w_ch_up_n),
		.ch_up_s(r_ch_up_s),
		.ch_dn_n(r_ch_dn_n),
		.ch_dn_s(w_ch_dn_s),
		.clb_out(r_clb_out)
	);


















	initial begin
		$dumpfile("FromCLBToChannelBusJunction_tb.vcd");
		$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_clb_out, w_ch_up_n, w_ch_dn_s, inst);
		r_clk <= 'b1;
		r_mode <= 'b0;
		r_c_bus <= 'h0;
		r_c_dimension <= 'h0;
		r_ch_up_s <= 'h3;
		r_ch_dn_n <= 'h3;
		r_clb_out <= 'b0;

		#100 @(posedge r_clk);

		r_mode <= 'b1;


		#50 @(posedge r_clk);

		r_c_bus <= {1'b0, 8'b10000011, 8'b10000111};
		#50 @(posedge r_clk);



		r_c_bus <= {1'b1, 8'b10000011, 8'b10000111};
		#50 @(posedge r_clk);

		r_c_bus <= {1'b0, 8'b10000011, 8'b10000111};

		#100 @(posedge r_clk);

		r_mode <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b1;



		#100 @(posedge r_clk);

		r_mode <= 'b1;

		#50@(posedge r_clk);

		r_c_dimension <= 'h1;

		#100 @(posedge r_clk);

		r_mode <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b1;



		#100 @(posedge r_clk);

		r_mode <= 'b1;

		#50@(posedge r_clk);

		r_c_dimension <= 'h2;

		#100 @(posedge r_clk);

		r_mode <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b1;



		#100 @(posedge r_clk);

		r_mode <= 'b1;

		#50@(posedge r_clk);

		r_c_dimension <= 'h3;

		#100 @(posedge r_clk);

		r_mode <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b0;


		#50 @(posedge r_clk);
		r_clb_out <= 'b1;



		#50 @(posedge r_clk);
		$finish;
	end

	always begin
		#50 r_clk <= ~r_clk;
	end

endmodule