data/full_repos/permissive/202237519/verilog/digitalsystem7/dff.v
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem7/dff.v:1: Cannot find include file: sr.v\n`include"sr.v" \n        ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem7,data/full_repos/permissive/202237519/sr.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem7,data/full_repos/permissive/202237519/sr.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem7,data/full_repos/permissive/202237519/sr.v.sv\n             sr.v\n             sr.v.v\n             sr.v.sv\n             obj_dir/sr.v\n             obj_dir/sr.v.v\n             obj_dir/sr.v.sv\n%Error: Exiting due to 1 error(s)\n'
module D_FF(CLK, D, set, Q, nQ);
  input CLK, D, set;
  output Q, nQ;
  wire w1, w2, w3,  w4; 
  sr_latch L1(w4|set, CLK&(~set), w1, w2);
  sr_latch L2((CLK&w2)|set, D&(~set), w3,  w4);
  sr_latch L3(w2, w3, Q, nQ);
endmodule
module D_FF(CLK, D, set, Q, nQ);

  input CLK, D, set;
  output Q, nQ;
  wire w1, w2, w3,  w4; 
  sr_latch L1(w4|set, CLK&(~set), w1, w2);
  sr_latch L2((CLK&w2)|set, D&(~set), w3,  w4);
  sr_latch L3(w2, w3, Q, nQ);
endmodule