data/full_repos/permissive/220330507/rtl/fetch.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/220330507/rtl/fetch.v:123: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out_instr'\n                                                                        : ... In instance fetch\n            out_instr = 0;\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/220330507/rtl/fetch.v:125: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out_instr'\n                                                                        : ... In instance fetch\n            out_instr = instr_ff;\n            ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/220330507/rtl/fetch.v:127: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out_instr'\n                                                                        : ... In instance fetch\n            out_instr = in_instr;\n            ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module fetch #(parameter PC_WIDTH=12, PMEM_WIDTH=16, PC_INCREMENT=2)
           (
            input                        clock,
            input                        reset,
            input      [  PC_WIDTH-1:0]  in_branch_pc,
            input                        in_flush,
            input      [PMEM_WIDTH-1:0]  in_instr,
            input                        in_set_pc,
            input                        in_stall,
            output     [PMEM_WIDTH-1:0]  out_instr,
            output reg                   out_instr_is_bubble,
            output     [  PC_WIDTH-1:0]  out_pc,
            output     [  PC_WIDTH-1:0]  out_pmem_addr
           );

    reg  [PMEM_WIDTH-1:0]  instr_ff;
    
    reg  [  PC_WIDTH-1:0] pc_next;
    reg  [  PC_WIDTH-1:0] pc_next_int;
    wire [  PC_WIDTH-1:0] pc_next_ext;
    reg  [  PC_WIDTH-1:0] pc_ff;
    reg  [  PC_WIDTH-1:0] pc_ff2;
   
    localparam MAX_PC = ((1<<PC_WIDTH)-PC_INCREMENT);
    
    assign pc_next_ext   = in_branch_pc;
    assign out_pc        = in_stall ? pc_ff2 : pc_ff;
    assign out_pmem_addr = pc_next;
    



    always @(posedge clock or posedge reset)
    begin
        if (!reset) begin
            instr_ff <= in_instr;
            pc_ff    <= pc_next;
            pc_ff2   <= pc_ff;
        end
        else begin
            instr_ff <= 0;
            pc_ff    <= MAX_PC;
            pc_ff2   <= 0;
        end
    end




    always @(posedge clock or posedge reset)
    begin
        if (!reset) begin
            out_instr_is_bubble <= in_flush;
        end
        else begin
            out_instr_is_bubble <= 0;
        end
    end
    

    always @(*)
    begin
        pc_next_int = pc_ff + PC_INCREMENT;
    end





    always @(*)
    begin
        if (in_stall) begin
            pc_next = pc_ff;
        end
        else if (in_set_pc == 1) begin
            pc_next = pc_next_ext;
        end
        else begin
            pc_next = pc_next_int;
        end
    end


    always @(*)
    begin
        if (in_flush == 1)
            out_instr = 0;
        else if (in_stall == 1)
            out_instr = instr_ff;
        else
            out_instr = in_instr;
    end

endmodule
module fetch #(parameter PC_WIDTH=12, PMEM_WIDTH=16, PC_INCREMENT=2)
           (
            input                        clock,
            input                        reset,
            input      [  PC_WIDTH-1:0]  in_branch_pc,
            input                        in_flush,
            input      [PMEM_WIDTH-1:0]  in_instr,
            input                        in_set_pc,
            input                        in_stall,
            output     [PMEM_WIDTH-1:0]  out_instr,
            output reg                   out_instr_is_bubble,
            output     [  PC_WIDTH-1:0]  out_pc,
            output     [  PC_WIDTH-1:0]  out_pmem_addr
           );


    reg  [PMEM_WIDTH-1:0]  instr_ff;
    
    reg  [  PC_WIDTH-1:0] pc_next;
    reg  [  PC_WIDTH-1:0] pc_next_int;
    wire [  PC_WIDTH-1:0] pc_next_ext;
    reg  [  PC_WIDTH-1:0] pc_ff;
    reg  [  PC_WIDTH-1:0] pc_ff2;
   
    localparam MAX_PC = ((1<<PC_WIDTH)-PC_INCREMENT);
    
    assign pc_next_ext   = in_branch_pc;
    assign out_pc        = in_stall ? pc_ff2 : pc_ff;
    assign out_pmem_addr = pc_next;
    



    always @(posedge clock or posedge reset)
    begin
        if (!reset) begin
            instr_ff <= in_instr;
            pc_ff    <= pc_next;
            pc_ff2   <= pc_ff;
        end
        else begin
            instr_ff <= 0;
            pc_ff    <= MAX_PC;
            pc_ff2   <= 0;
        end
    end




    always @(posedge clock or posedge reset)
    begin
        if (!reset) begin
            out_instr_is_bubble <= in_flush;
        end
        else begin
            out_instr_is_bubble <= 0;
        end
    end
    

    always @(*)
    begin
        pc_next_int = pc_ff + PC_INCREMENT;
    end





    always @(*)
    begin
        if (in_stall) begin
            pc_next = pc_ff;
        end
        else if (in_set_pc == 1) begin
            pc_next = pc_next_ext;
        end
        else begin
            pc_next = pc_next_int;
        end
    end


    always @(*)
    begin
        if (in_flush == 1)
            out_instr = 0;
        else if (in_stall == 1)
            out_instr = instr_ff;
        else
            out_instr = in_instr;
    end

endmodule