data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:158: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'block_ram_sp\'\nmodule  block_ram_sp(\n        ^~~~~~~~~~~~\n                                                                                             : ... Top module \'block_ram_dp\'\nmodule  block_ram_dp(\n        ^~~~~~~~~~~~\n                                                                                             : ... Top module \'dist_ram_dp\'\nmodule  dist_ram_dp(\n        ^~~~~~~~~~~\n                                                                                             : ... Top module \'per_dp4_0_r\'\nmodule per_dp4_0_r(\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n16_p4_w8_idx0.v:1033: Output port connection \'counter_out\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 2 bits.\n                                                                                           : ... In instance per_dp4_0_r\n  counter_8 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n                                            ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n'
module wireCon_dp4_st1_L(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,                        
out_start,                       
clk,                             
rst                              
);                               
  parameter DATA_WIDTH = 8;                                
  input in_start, clk, rst;        
  input [DATA_WIDTH-1:0] inData_0,
      inData_1,
      inData_2,
      inData_3;
  output [DATA_WIDTH-1:0] outData_0,
      outData_1,
      outData_2,
      outData_3; 
  output out_start; 
  
  wire [DATA_WIDTH-1:0] wireIn [3:0];              
  wire [DATA_WIDTH-1:0] wireOut [3:0];              
  
  assign wireIn[0] = inData_0;    
  assign wireIn[1] = inData_1;    
  assign wireIn[2] = inData_2;    
  assign wireIn[3] = inData_3;    
  
  assign wireOut[0] = wireIn[0];    
  assign wireOut[1] = wireIn[1];    
  assign wireOut[2] = wireIn[2];    
  assign wireOut[3] = wireIn[3];    
  
  assign outData_0 = wireOut[0];    
  assign outData_1 = wireOut[1];    
  assign outData_2 = wireOut[2];    
  assign outData_3 = wireOut[3];    
  assign out_start = in_start;    
  
endmodule
module wireCon_dp4_st1_L(
inData_0,
inData_1,
inData_2,
inData_3,
outData_0,
outData_1,
outData_2,
outData_3,
in_start,                        
out_start,                       
clk,                             
rst                              
);
                               
  parameter DATA_WIDTH = 8;                                
  input in_start, clk, rst;        
  input [DATA_WIDTH-1:0] inData_0,
      inData_1,
      inData_2,
      inData_3;
  output [DATA_WIDTH-1:0] outData_0,
      outData_1,
      outData_2,
      outData_3; 
  output out_start; 
  
  wire [DATA_WIDTH-1:0] wireIn [3:0];              
  wire [DATA_WIDTH-1:0] wireOut [3:0];              
  
  assign wireIn[0] = inData_0;    
  assign wireIn[1] = inData_1;    
  assign wireIn[2] = inData_2;    
  assign wireIn[3] = inData_3;    
  
  assign wireOut[0] = wireIn[0];    
  assign wireOut[1] = wireIn[1];    
  assign wireOut[2] = wireIn[2];    
  assign wireOut[3] = wireIn[3];    
  
  assign outData_0 = wireOut[0];    
  assign outData_1 = wireOut[1];    
  assign outData_2 = wireOut[2];    
  assign outData_3 = wireOut[3];    
  assign out_start = in_start;    
  
endmodule