data/full_repos/permissive/136510272/projects/sdramvga/marsohod2.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/136510272/projects/sdramvga/marsohod2.v:110: Signal definition not found, creating implicitly: \'lock\'\n    if (!lock) begin\n         ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/136510272/projects/sdramvga/marsohod2.v:59: Cannot find file containing module: \'sdramvga640\'\nsdramvga640 SDRAM_VGA640x480(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/projects/sdramvga,data/full_repos/permissive/136510272/sdramvga640\n             data/full_repos/permissive/136510272/projects/sdramvga,data/full_repos/permissive/136510272/sdramvga640.v\n             data/full_repos/permissive/136510272/projects/sdramvga,data/full_repos/permissive/136510272/sdramvga640.sv\n             sdramvga640\n             sdramvga640.v\n             sdramvga640.sv\n             obj_dir/sdramvga640\n             obj_dir/sdramvga640.v\n             obj_dir/sdramvga640.sv\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/sdramvga/marsohod2.v:95: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                     : ... In instance marsohod2\nwire [15:0] rdwr = 1\'b1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/sdramvga/marsohod2.v:96: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                     : ... In instance marsohod2\nreg [15:0] io_clk = 1\'b1;\n                    ^~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module marsohod2(




    input   wire        clk,


    output  wire [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);


sdramvga640 SDRAM_VGA640x480(
	

	.clock      (clk),


    .clksdram   (sdram_clock),
    .addr       (sdram_addr),
    .bank       (sdram_bank),
    .dq         (sdram_dq),
    .ldqm       (sdram_ldqm),
    .udqm       (sdram_udqm),
    .ras        (sdram_ras),
    .cas        (sdram_cas),
    .we         (sdram_we),
    

    .vga_red    (vga_red),
    .vga_green  (vga_green),
    .vga_blue   (vga_blue),
    .vga_hs     (vga_hs),
    .vga_vs     (vga_vs),


    .address    (address),
    .i_data     (i_data),
    .o_data     (o_data),
    .rdwr       (rdwr),
    .clk        (io_clk),
    .lock       (lock)
);


reg  [21:0] address = 22'h0;
reg  [15:0] i_data  = 16'hFFFF;
wire [15:0] o_data;
wire [15:0] rdwr = 1'b1;
reg [15:0] io_clk = 1'b1;

reg [15:0] divt;
always @(posedge clk) begin
    divt <= divt + 1'b1;
end

reg [10:0] lx;
reg [15:0] lm;
reg ly;

always @(posedge divt[2]) begin

    io_clk <= io_clk + 1'b1;
    if (!lock) begin
    
        lx <= lx == 639 ? 0 : lx + 1; 
        ly <= lx == 639 ? ly ^ 1'b1 : ly;
        lm <= lx == 639 ? lm + 1 : lm;
        
        address <= address + 1'b1;
        i_data <= lx[0] ^ ly ? 16'hFFFF : lm;
    end
    
end

endmodule
module marsohod2(




    input   wire        clk,


    output  wire [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);



sdramvga640 SDRAM_VGA640x480(
	

	.clock      (clk),


    .clksdram   (sdram_clock),
    .addr       (sdram_addr),
    .bank       (sdram_bank),
    .dq         (sdram_dq),
    .ldqm       (sdram_ldqm),
    .udqm       (sdram_udqm),
    .ras        (sdram_ras),
    .cas        (sdram_cas),
    .we         (sdram_we),
    

    .vga_red    (vga_red),
    .vga_green  (vga_green),
    .vga_blue   (vga_blue),
    .vga_hs     (vga_hs),
    .vga_vs     (vga_vs),


    .address    (address),
    .i_data     (i_data),
    .o_data     (o_data),
    .rdwr       (rdwr),
    .clk        (io_clk),
    .lock       (lock)
);


reg  [21:0] address = 22'h0;
reg  [15:0] i_data  = 16'hFFFF;
wire [15:0] o_data;
wire [15:0] rdwr = 1'b1;
reg [15:0] io_clk = 1'b1;

reg [15:0] divt;
always @(posedge clk) begin
    divt <= divt + 1'b1;
end

reg [10:0] lx;
reg [15:0] lm;
reg ly;

always @(posedge divt[2]) begin

    io_clk <= io_clk + 1'b1;
    if (!lock) begin
    
        lx <= lx == 639 ? 0 : lx + 1; 
        ly <= lx == 639 ? ly ^ 1'b1 : ly;
        lm <= lx == 639 ? lm + 1 : lm;
        
        address <= address + 1'b1;
        i_data <= lx[0] ^ ly ? 16'hFFFF : lm;
    end
    
end

endmodule