data/full_repos/permissive/172201645/test_benches/tb_test_source.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_test_source.v:74: Unsupported: Ignoring delay on this delayed statement.\n             #4 \n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_test_source.v:81: Unsupported: Ignoring delay on this delayed statement.\n             #4 \n             ^\n%Error: data/full_repos/permissive/172201645/test_benches/tb_test_source.v:91: Cannot find file containing module: \'test_source\'\ntest_source i_test_source(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/test_source\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/test_source.v\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/test_source.sv\n             test_source\n             test_source.v\n             test_source.sv\n             obj_dir/test_source\n             obj_dir/test_source.v\n             obj_dir/test_source.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_test_source;

    reg clk = 1'b0;
    reg [8:0] ch1;
    reg [8:0] ch2;
    reg [8:0] ch3;
    reg [8:0] ch4;

        wire  [2:0] stream_channel_count;
        wire [72:0] data;
        wire        ready;
        
        
initial begin
        forever begin
             #4 
             clk = 1'b0;
             ch1 <= data[8:0];
             ch2 <= data[26:18];
             ch3 <= data[44:36];
             ch4 <= data[62:54];

             #4 
             clk = 1'b1;
             ch1 <= data[17:9];
             ch2 <= data[35:27];
             ch3 <= data[53:45];
             ch4 <= data[71:63];
         end
    end     


test_source i_test_source(
    .clk                  (clk),
    .stream_channel_count (stream_channel_count),
    .ready                (ready),
    .data                 (data)
);

endmodule
module tb_test_source;


    reg clk = 1'b0;
    reg [8:0] ch1;
    reg [8:0] ch2;
    reg [8:0] ch3;
    reg [8:0] ch4;

        wire  [2:0] stream_channel_count;
        wire [72:0] data;
        wire        ready;
        
        
initial begin
        forever begin
             #4 
             clk = 1'b0;
             ch1 <= data[8:0];
             ch2 <= data[26:18];
             ch3 <= data[44:36];
             ch4 <= data[62:54];

             #4 
             clk = 1'b1;
             ch1 <= data[17:9];
             ch2 <= data[35:27];
             ch3 <= data[53:45];
             ch4 <= data[71:63];
         end
    end     


test_source i_test_source(
    .clk                  (clk),
    .stream_channel_count (stream_channel_count),
    .ready                (ready),
    .data                 (data)
);

endmodule