data/full_repos/permissive/162672365/Adder.v
data/verilator_xmls/fbe7f381-9c5d-417b-8dbc-a02327e27a4f.xml
module oneBitFullAdder(sum, carry, in1, in2, cin);
	input in1, in2, cin;
	output sum, carry;
	wire s1, c1, c2;
	
	halfAdder ha1(s1, c1, in1, in2);
	halfAdder ha2(sum, c2, s1, cin);
	or o1(carry, c1, c2);
	
endmodule
module oneBitFullAdder(sum, carry, in1, in2, cin);

	input in1, in2, cin;
	output sum, carry;
	wire s1, c1, c2;
	
	halfAdder ha1(s1, c1, in1, in2);
	halfAdder ha2(sum, c2, s1, cin);
	or o1(carry, c1, c2);
	
endmodule