data/full_repos/permissive/154352170/mips.v
1: b"%Error: data/full_repos/permissive/154352170/mips.v:143: Cannot find file containing module: 'PC'\n  PC F_PC(\n  ^~\n        ... Looked in:\n             data/full_repos/permissive/154352170,data/full_repos/permissive/154352170/PC\n             data/full_repos/permissive/154352170,data/full_repos/permissive/154352170/PC.v\n             data/full_repos/permissive/154352170,data/full_repos/permissive/154352170/PC.sv\n             PC\n             PC.v\n             PC.sv\n             obj_dir/PC\n             obj_dir/PC.v\n             obj_dir/PC.sv\n%Error: data/full_repos/permissive/154352170/mips.v:151: Cannot find file containing module: 'NPC'\n  NPC F_NPC(\n  ^~~\n%Error: data/full_repos/permissive/154352170/mips.v:164: Cannot find file containing module: 'IM'\n  IM F_IM(\n  ^~\n%Error: data/full_repos/permissive/154352170/mips.v:169: Cannot find file containing module: 'IF_ID'\n  IF_ID IF_ID(\n  ^~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:181: Cannot find file containing module: 'Control'\n  Control D_Control(\n  ^~~~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:188: Cannot find file containing module: 'GRF'\n  GRF D_GRF(\n  ^~~\n%Error: data/full_repos/permissive/154352170/mips.v:200: Cannot find file containing module: 'EXT'\n  EXT D_EXT(\n  ^~~\n%Error: data/full_repos/permissive/154352170/mips.v:207: Cannot find file containing module: 'CMP'\n  CMP D_CMP(\n  ^~~\n%Error: data/full_repos/permissive/154352170/mips.v:214: Cannot find file containing module: 'MFRTD'\n  MFRTD D_MFRTD(\n  ^~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:222: Cannot find file containing module: 'MFRSD'\n  MFRSD D_MFRSD(\n  ^~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:230: Cannot find file containing module: 'ID_EX'\n    ID_EX ID_EX(\n    ^~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:248: Cannot find file containing module: 'Control'\n   Control E_Control(\n   ^~~~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:255: Cannot find file containing module: 'ALU'\n   ALU E_ALU(\n   ^~~\n%Error: data/full_repos/permissive/154352170/mips.v:262: Cannot find file containing module: 'ALU_MUX_A'\n   ALU_MUX_A E_ALUSrcA(\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:268: Cannot find file containing module: 'ALU_MUX_B'\n   ALU_MUX_B E_ALUSrcB(\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:275: Cannot find file containing module: 'MFRTE'\n   MFRTE E_MFRTE(\n   ^~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:284: Cannot find file containing module: 'MFRSE'\n   MFRSE E_MFRSE(\n   ^~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:293: Cannot find file containing module: 'EX_MEM'\n   EX_MEM EX_MEM(\n   ^~~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:309: Cannot find file containing module: 'Control'\n   Control M_Control(\n   ^~~~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:314: Cannot find file containing module: 'MFRTM'\n   MFRTM M_MFRTM(\n   ^~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:321: Cannot find file containing module: 'DM'\n   DM M_DM(\n   ^~\n%Error: data/full_repos/permissive/154352170/mips.v:332: Cannot find file containing module: 'MEM_WB'\n     MEM_WB MEM_WB(\n     ^~~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:348: Cannot find file containing module: 'Control'\n   Control W_Control(\n   ^~~~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:355: Cannot find file containing module: 'RegData_MUX'\n   RegData_MUX W_RegDataMUX(\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:364: Cannot find file containing module: 'WA_MUX'\n   WA_MUX W_WA_MUX(\n   ^~~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:370: Cannot find file containing module: 'Forward'\n   Forward Forward(\n   ^~~~~~~\n%Error: data/full_repos/permissive/154352170/mips.v:382: Cannot find file containing module: 'Stall'\n   Stall Stall(\n   ^~~~~\n%Error: Exiting due to 27 error(s)\n"
module mips(
    input clk,
    input reset
    );
	 

	 

	 wire [31:0] PC_Next;
    wire [31:0] PC_Out;
	 wire PC_En;
	 

	 wire Zero;
	 

	 wire [31:0] IR;
	 	 

	 wire IF_ID_En;
	 wire [31:0] IR_D;
	 wire [31:0] PC_D;
	 

	 

    wire Branch;
	 wire [1:0] Jump;
	 wire [2:0] EXTOp;
	 

	 wire [4:0] RegDataWriteAddr;
	 wire [31:0] RegDataIn;
	 wire [31:0] RegDataOut1;
	 wire [31:0] RegDataOut2;
	 

	 wire [31:0] EXT_Out;
	 

	 wire Bgezalr;
	 

	 

	 wire ID_EX_Clr;
	 wire [31:0] IR_E;
	 wire [31:0] PC_E;
	 wire [31:0] RegDataOut1_D_In;
	 wire [31:0] RegDataOut2_D_In;
 	 wire [31:0] RegDataOut1_E;
	 wire [31:0] RegDataOut2_E;
	 wire [31:0] EXT_Out_E;
	 

	 

	 wire [2:0] ALUOp;
	 wire ALUSrcA;
	 wire ALUSrcB;
	 

	 wire [31:0] ALU_In_A;
	 wire [31:0] ALU_In_B;
	 wire [31:0] ALU_Out;
	 

	 

	 

	 

	 wire [31:0] RegDataOut2_E_In;
	 wire [31:0] RegDataOut1_E_In;
	 wire [31:0] IR_M;
	 wire [31:0] RegDataOut2_M;
	 wire [31:0] PC_M;
	 wire [31:0] ALU_Out_M;
	 

	 

	 wire MemWrite;
	 

	 wire [31:0] WriteData;
	 wire [31:0] DM_Out;
	 

	 wire [31:0] IR_W;
	 wire [31:0] PC_W;
	 wire [31:0] ALU_Out_W;
	 wire [31:0] DM_Out_W;
	 

	 

	 wire MemToReg;
	 wire RegWrite;
	 wire RegDst;
	 

	 wire [1:0] ForwardRSD;
	 wire [1:0] ForwardRTD;
	 wire [1:0] ForwardRSE;
	 wire [1:0] ForwardRTE;
	 wire [1:0] ForwardRTM;
	 	 

	 

	 

	 PC F_PC(
	    .clk(clk),
		 .reset(reset),
		 .PC_En(PC_En),
		 .PC_Next(PC_Next),
		 .PC_Out(PC_Out));
		 

	 NPC F_NPC(
	    .Branch(Branch),
		 .Zero(Zero),
		 .Bgezalr(Bgezalr),
		 .Jump(Jump),
		 .EXT_Out(EXT_Out),
		 .PC_Out(PC_Out),
		 .PC_D(PC_D),
		 .PC_Next(PC_Next),
		 .RD1(RegDataOut1_D_In),
		 .RD2(RegDataOut2_D_In));
	 	 

	 IM F_IM(
	    .PC_Out(PC_Out),
		 .IM_Out(IR));
		 

	 IF_ID IF_ID(
	    .clk(clk),
		 .reset(reset),
		 .IF_ID_En(IF_ID_En),
		 .IR_In(IR),
		 .IR_Out(IR_D),
		 .PC_Out_In(PC_Out),
		 .PC_Out_Out(PC_D));
	 

		 

	 Control D_Control(
	    .IR_In(IR_D),
		 .Branch(Branch),
		 .EXTOp(EXTOp),
		 .Jump(Jump));
		 

	 GRF D_GRF(
	    .clk(clk),
		 .reset(reset),
		 .RegWrite(RegWrite),
		 .WA(RegDataWriteAddr),
		 .RegData(RegDataIn),
		 .PC_Out(PC_W),
		 .IR_In(IR_D),
		 .RD1(RegDataOut1),
		 .RD2(RegDataOut2));
		 		 

	 EXT D_EXT(
	    .IR_In(IR_D),
		 .RD2(RegDataOut2_D_In),
		 .EXTOp(EXTOp),
		 .EXT_Out(EXT_Out));
	 

	 CMP D_CMP(
	    .RD1(RegDataOut1_D_In),
		 .RD2(RegDataOut2_D_In),
		 .Bgezalr(Bgezalr),
		 .Zero(Zero));
		 

	 MFRTD D_MFRTD(
	     .ForwardRTD(ForwardRTD),
		  .RD2(RegDataOut2),
		  .ALU_Out_M(ALU_Out_M),
		  .PC_Out_M(PC_M),
		  .RT_D(RegDataOut2_D_In));
	 

	 MFRSD D_MFRSD(
	     .ForwardRSD(ForwardRSD),
		  .RD1(RegDataOut1),
		  .ALU_Out_M(ALU_Out_M),
		  .PC_Out_M(PC_M),
		  .RS_D(RegDataOut1_D_In));
		 	 

    ID_EX ID_EX(
       .clk(clk),
       .reset(reset),
       .ID_EX_Clr(ID_EX_Clr),
		 .IR_In(IR_D),
		 .IR_Out(IR_E),
		 .PC_Out_In(PC_D),
		 .PC_Out_Out(PC_E),
		 .RD1_In(RegDataOut1_D_In),
		 .RD1_Out(RegDataOut1_E),
		 .RD2_In(RegDataOut2_D_In),
		 .RD2_Out(RegDataOut2_E),
		 .EXT_In(EXT_Out),
		 .EXT_Out(EXT_Out_E));
	

	  

	  Control E_Control(
	     .IR_In(IR_E),
		  .ALUOp(ALUOp),
		  .ALUSrcA(ALUSrcA),
		  .ALUSrcB(ALUSrcB));
		  

	  ALU E_ALU(
	     .A(ALU_In_A),
		  .B(ALU_In_B),
		  .ALUOp(ALUOp),
		  .ALU_Out(ALU_Out));
		  

	  ALU_MUX_A E_ALUSrcA(
	     .ALUSrcA(ALUSrcA),
		  .RD1(RegDataOut1_E_In),
		  .ALU_A(ALU_In_A));
	  

	  ALU_MUX_B E_ALUSrcB(
	     .ALUSrcB(ALUSrcB),
		  .EXT_Out(EXT_Out_E),
		  .RD2(RegDataOut2_E_In),
		  .ALU_B(ALU_In_B));
		  

	  MFRTE E_MFRTE(
	     .ForwardRTE(ForwardRTE),
		  .RD2(RegDataOut2_E),
		  .ALU_Out_M(ALU_Out_M),
		  .PC_Out_M(PC_M),
		  .RegData(RegDataIn),
		  .RT_E(RegDataOut2_E_In));
		  

	  MFRSE E_MFRSE(
	     .ForwardRSE(ForwardRSE),
		  .RD1(RegDataOut1_E),
		  .ALU_Out(ALU_Out_M),
		  .RegData(RegDataIn),
		  .PC_Out_M(PC_M),
		  .RS_E(RegDataOut1_E_In));
		

	  EX_MEM EX_MEM(
	     .clk(clk),
		  .reset(reset),
		  .EX_MEM_En(EX_MEM_En),
		  .IR_In(IR_E),
		  .IR_Out(IR_M),
		  .RD2_In(RegDataOut2_E_In),
		  .RD2_Out(RegDataOut2_M),
		  .PC_Out_In(PC_E),
		  .PC_Out_Out(PC_M),
		  .ALU_Out_In(ALU_Out),
		  .ALU_Out_Out(ALU_Out_M));
	 

	  

	  Control M_Control(
	     .IR_In(IR_M),
		  .MemWrite(MemWrite));
		  

	  MFRTM M_MFRTM(
	     .ForwardRTM(ForwardRTM),
		  .RD2_M(RegDataOut2_M),
		  .RD2_W(RegDataIn),
		  .WriteData(WriteData));
	 

	  DM M_DM(
	     .clk(clk),
		  .reset(reset),
		  .IR_In(IR_M),
		  .MemWrite(MemWrite),
		  .PC_Out(PC_M),
		  .ALU_Out(ALU_Out_M),
		  .WD(WriteData),
		  .DM_Out(DM_Out));
		  

     MEM_WB MEM_WB(
        .clk(clk),
		  .reset(reset),
        .MEM_WB_En(MEM_WB_En),
		  .IR_In(IR_M),
		  .IR_Out(IR_W),
		  .ALU_Out_In(ALU_Out_M),
		  .ALU_Out_Out(ALU_Out_W),
		  .DM_Out_In(DM_Out),
		  .DM_Out_Out(DM_Out_W),
		  .PC_Out_In(PC_M),
		  .PC_Out_Out(PC_W));
		  

	  

	  Control W_Control(
	     .IR_In(IR_W),
		  .RegDst(RegDst),
		  .MemToReg(MemToReg),
		  .RegWrite(RegWrite));
	  

	  RegData_MUX W_RegDataMUX(
	     .MemToReg(MemToReg),
		  .ALU_Out(ALU_Out_W),
		  .DM_Out(DM_Out_W),
		  .PC(PC_W),
		  .IR(IR_W),
		  .RegData(RegDataIn));
		  

	  WA_MUX W_WA_MUX(
	     .IR_In(IR_W),
		  .RegDst(RegDst),
		  .WA(RegDataWriteAddr));
		  

	  Forward Forward(
        .IR_D(IR_D),
        .IR_E(IR_E),
        .IR_M(IR_M),
        .IR_W(IR_W),
        .ForwardRSD(ForwardRSD),
        .ForwardRSE(ForwardRSE),
        .ForwardRTD(ForwardRTD),
        .ForwardRTE(ForwardRTE),
        .ForwardRTM(ForwardRTM));
		  

	  Stall Stall(
	     .IR_D(IR_D),
        .IR_E(IR_E),
        .IR_M(IR_M),
        .PC_En(PC_En),
		  .IF_ID_En(IF_ID_En),
		  .ID_EXE_Clr(ID_EX_Clr));
	 
endmodule
module mips(
    input clk,
    input reset
    );

	 

	 

	 wire [31:0] PC_Next;
    wire [31:0] PC_Out;
	 wire PC_En;
	 

	 wire Zero;
	 

	 wire [31:0] IR;
	 	 

	 wire IF_ID_En;
	 wire [31:0] IR_D;
	 wire [31:0] PC_D;
	 

	 

    wire Branch;
	 wire [1:0] Jump;
	 wire [2:0] EXTOp;
	 

	 wire [4:0] RegDataWriteAddr;
	 wire [31:0] RegDataIn;
	 wire [31:0] RegDataOut1;
	 wire [31:0] RegDataOut2;
	 

	 wire [31:0] EXT_Out;
	 

	 wire Bgezalr;
	 

	 

	 wire ID_EX_Clr;
	 wire [31:0] IR_E;
	 wire [31:0] PC_E;
	 wire [31:0] RegDataOut1_D_In;
	 wire [31:0] RegDataOut2_D_In;
 	 wire [31:0] RegDataOut1_E;
	 wire [31:0] RegDataOut2_E;
	 wire [31:0] EXT_Out_E;
	 

	 

	 wire [2:0] ALUOp;
	 wire ALUSrcA;
	 wire ALUSrcB;
	 

	 wire [31:0] ALU_In_A;
	 wire [31:0] ALU_In_B;
	 wire [31:0] ALU_Out;
	 

	 

	 

	 

	 wire [31:0] RegDataOut2_E_In;
	 wire [31:0] RegDataOut1_E_In;
	 wire [31:0] IR_M;
	 wire [31:0] RegDataOut2_M;
	 wire [31:0] PC_M;
	 wire [31:0] ALU_Out_M;
	 

	 

	 wire MemWrite;
	 

	 wire [31:0] WriteData;
	 wire [31:0] DM_Out;
	 

	 wire [31:0] IR_W;
	 wire [31:0] PC_W;
	 wire [31:0] ALU_Out_W;
	 wire [31:0] DM_Out_W;
	 

	 

	 wire MemToReg;
	 wire RegWrite;
	 wire RegDst;
	 

	 wire [1:0] ForwardRSD;
	 wire [1:0] ForwardRTD;
	 wire [1:0] ForwardRSE;
	 wire [1:0] ForwardRTE;
	 wire [1:0] ForwardRTM;
	 	 

	 

	 

	 PC F_PC(
	    .clk(clk),
		 .reset(reset),
		 .PC_En(PC_En),
		 .PC_Next(PC_Next),
		 .PC_Out(PC_Out));
		 

	 NPC F_NPC(
	    .Branch(Branch),
		 .Zero(Zero),
		 .Bgezalr(Bgezalr),
		 .Jump(Jump),
		 .EXT_Out(EXT_Out),
		 .PC_Out(PC_Out),
		 .PC_D(PC_D),
		 .PC_Next(PC_Next),
		 .RD1(RegDataOut1_D_In),
		 .RD2(RegDataOut2_D_In));
	 	 

	 IM F_IM(
	    .PC_Out(PC_Out),
		 .IM_Out(IR));
		 

	 IF_ID IF_ID(
	    .clk(clk),
		 .reset(reset),
		 .IF_ID_En(IF_ID_En),
		 .IR_In(IR),
		 .IR_Out(IR_D),
		 .PC_Out_In(PC_Out),
		 .PC_Out_Out(PC_D));
	 

		 

	 Control D_Control(
	    .IR_In(IR_D),
		 .Branch(Branch),
		 .EXTOp(EXTOp),
		 .Jump(Jump));
		 

	 GRF D_GRF(
	    .clk(clk),
		 .reset(reset),
		 .RegWrite(RegWrite),
		 .WA(RegDataWriteAddr),
		 .RegData(RegDataIn),
		 .PC_Out(PC_W),
		 .IR_In(IR_D),
		 .RD1(RegDataOut1),
		 .RD2(RegDataOut2));
		 		 

	 EXT D_EXT(
	    .IR_In(IR_D),
		 .RD2(RegDataOut2_D_In),
		 .EXTOp(EXTOp),
		 .EXT_Out(EXT_Out));
	 

	 CMP D_CMP(
	    .RD1(RegDataOut1_D_In),
		 .RD2(RegDataOut2_D_In),
		 .Bgezalr(Bgezalr),
		 .Zero(Zero));
		 

	 MFRTD D_MFRTD(
	     .ForwardRTD(ForwardRTD),
		  .RD2(RegDataOut2),
		  .ALU_Out_M(ALU_Out_M),
		  .PC_Out_M(PC_M),
		  .RT_D(RegDataOut2_D_In));
	 

	 MFRSD D_MFRSD(
	     .ForwardRSD(ForwardRSD),
		  .RD1(RegDataOut1),
		  .ALU_Out_M(ALU_Out_M),
		  .PC_Out_M(PC_M),
		  .RS_D(RegDataOut1_D_In));
		 	 

    ID_EX ID_EX(
       .clk(clk),
       .reset(reset),
       .ID_EX_Clr(ID_EX_Clr),
		 .IR_In(IR_D),
		 .IR_Out(IR_E),
		 .PC_Out_In(PC_D),
		 .PC_Out_Out(PC_E),
		 .RD1_In(RegDataOut1_D_In),
		 .RD1_Out(RegDataOut1_E),
		 .RD2_In(RegDataOut2_D_In),
		 .RD2_Out(RegDataOut2_E),
		 .EXT_In(EXT_Out),
		 .EXT_Out(EXT_Out_E));
	

	  

	  Control E_Control(
	     .IR_In(IR_E),
		  .ALUOp(ALUOp),
		  .ALUSrcA(ALUSrcA),
		  .ALUSrcB(ALUSrcB));
		  

	  ALU E_ALU(
	     .A(ALU_In_A),
		  .B(ALU_In_B),
		  .ALUOp(ALUOp),
		  .ALU_Out(ALU_Out));
		  

	  ALU_MUX_A E_ALUSrcA(
	     .ALUSrcA(ALUSrcA),
		  .RD1(RegDataOut1_E_In),
		  .ALU_A(ALU_In_A));
	  

	  ALU_MUX_B E_ALUSrcB(
	     .ALUSrcB(ALUSrcB),
		  .EXT_Out(EXT_Out_E),
		  .RD2(RegDataOut2_E_In),
		  .ALU_B(ALU_In_B));
		  

	  MFRTE E_MFRTE(
	     .ForwardRTE(ForwardRTE),
		  .RD2(RegDataOut2_E),
		  .ALU_Out_M(ALU_Out_M),
		  .PC_Out_M(PC_M),
		  .RegData(RegDataIn),
		  .RT_E(RegDataOut2_E_In));
		  

	  MFRSE E_MFRSE(
	     .ForwardRSE(ForwardRSE),
		  .RD1(RegDataOut1_E),
		  .ALU_Out(ALU_Out_M),
		  .RegData(RegDataIn),
		  .PC_Out_M(PC_M),
		  .RS_E(RegDataOut1_E_In));
		

	  EX_MEM EX_MEM(
	     .clk(clk),
		  .reset(reset),
		  .EX_MEM_En(EX_MEM_En),
		  .IR_In(IR_E),
		  .IR_Out(IR_M),
		  .RD2_In(RegDataOut2_E_In),
		  .RD2_Out(RegDataOut2_M),
		  .PC_Out_In(PC_E),
		  .PC_Out_Out(PC_M),
		  .ALU_Out_In(ALU_Out),
		  .ALU_Out_Out(ALU_Out_M));
	 

	  

	  Control M_Control(
	     .IR_In(IR_M),
		  .MemWrite(MemWrite));
		  

	  MFRTM M_MFRTM(
	     .ForwardRTM(ForwardRTM),
		  .RD2_M(RegDataOut2_M),
		  .RD2_W(RegDataIn),
		  .WriteData(WriteData));
	 

	  DM M_DM(
	     .clk(clk),
		  .reset(reset),
		  .IR_In(IR_M),
		  .MemWrite(MemWrite),
		  .PC_Out(PC_M),
		  .ALU_Out(ALU_Out_M),
		  .WD(WriteData),
		  .DM_Out(DM_Out));
		  

     MEM_WB MEM_WB(
        .clk(clk),
		  .reset(reset),
        .MEM_WB_En(MEM_WB_En),
		  .IR_In(IR_M),
		  .IR_Out(IR_W),
		  .ALU_Out_In(ALU_Out_M),
		  .ALU_Out_Out(ALU_Out_W),
		  .DM_Out_In(DM_Out),
		  .DM_Out_Out(DM_Out_W),
		  .PC_Out_In(PC_M),
		  .PC_Out_Out(PC_W));
		  

	  

	  Control W_Control(
	     .IR_In(IR_W),
		  .RegDst(RegDst),
		  .MemToReg(MemToReg),
		  .RegWrite(RegWrite));
	  

	  RegData_MUX W_RegDataMUX(
	     .MemToReg(MemToReg),
		  .ALU_Out(ALU_Out_W),
		  .DM_Out(DM_Out_W),
		  .PC(PC_W),
		  .IR(IR_W),
		  .RegData(RegDataIn));
		  

	  WA_MUX W_WA_MUX(
	     .IR_In(IR_W),
		  .RegDst(RegDst),
		  .WA(RegDataWriteAddr));
		  

	  Forward Forward(
        .IR_D(IR_D),
        .IR_E(IR_E),
        .IR_M(IR_M),
        .IR_W(IR_W),
        .ForwardRSD(ForwardRSD),
        .ForwardRSE(ForwardRSE),
        .ForwardRTD(ForwardRTD),
        .ForwardRTE(ForwardRTE),
        .ForwardRTM(ForwardRTM));
		  

	  Stall Stall(
	     .IR_D(IR_D),
        .IR_E(IR_E),
        .IR_M(IR_M),
        .PC_En(PC_En),
		  .IF_ID_En(IF_ID_En),
		  .ID_EXE_Clr(ID_EX_Clr));
	 
endmodule