data/full_repos/permissive/171756809/debouncer.v
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data/verilator_xmls/61ee1cb3-d93a-4015-94db-6e055e3df124.xml
module debouncer(
	input wire clk,
	input wire in,
	output reg out = 0);

	parameter CLOCKED_EDGE_OUT = 0;
	parameter INPUT_WHEN_IDLE = 1;
	parameter DEBOUNCE_CYCLES = 1000;

	reg old = INPUT_WHEN_IDLE;
	reg running = 0;
	reg [$clog2(DEBOUNCE_CYCLES+1)-1 : 0] bounce_timeout = 0;

	always @(posedge clk) begin
		if(old != in) begin
			running <= 1;
			bounce_timeout <= DEBOUNCE_CYCLES;
		end else begin
			if(running) begin
				bounce_timeout <= bounce_timeout - 1;
				if(bounce_timeout == 0) begin
					running <= 0;
					if(CLOCKED_EDGE_OUT) begin
						out <= (INPUT_WHEN_IDLE) ? ~in : in;
					end else begin
						out <= in;
					end
				end else begin
					if(CLOCKED_EDGE_OUT) begin
						out <= 0;
					end
				end
			end else begin
				if(CLOCKED_EDGE_OUT) begin
					out <= 0;
				end
			end
		end

		old <= in;
	end

endmodule
module debouncer(
	input wire clk,
	input wire in,
	output reg out = 0);


	parameter CLOCKED_EDGE_OUT = 0;
	parameter INPUT_WHEN_IDLE = 1;
	parameter DEBOUNCE_CYCLES = 1000;

	reg old = INPUT_WHEN_IDLE;
	reg running = 0;
	reg [$clog2(DEBOUNCE_CYCLES+1)-1 : 0] bounce_timeout = 0;

	always @(posedge clk) begin
		if(old != in) begin
			running <= 1;
			bounce_timeout <= DEBOUNCE_CYCLES;
		end else begin
			if(running) begin
				bounce_timeout <= bounce_timeout - 1;
				if(bounce_timeout == 0) begin
					running <= 0;
					if(CLOCKED_EDGE_OUT) begin
						out <= (INPUT_WHEN_IDLE) ? ~in : in;
					end else begin
						out <= in;
					end
				end else begin
					if(CLOCKED_EDGE_OUT) begin
						out <= 0;
					end
				end
			end else begin
				if(CLOCKED_EDGE_OUT) begin
					out <= 0;
				end
			end
		end

		old <= in;
	end

endmodule