data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/memory_peripheral,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:17: Define or directive not defined: \'`ADDR_W\'\n  parameter WORD_COUNT = 1 << (`ADDR_W - 2);\n                               ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:26: Define or directive not defined: \'`ADDR_W\'\n  input [`ADDR_W - 1:0] i_req_addr;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:27: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_req_wr_data;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:29: Define or directive not defined: \'`MEM_COUNT_W\'\n  input [`MEM_COUNT_W - 1:0] i_req_count;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:32: Define or directive not defined: \'`WORD_W\'\n  output reg [`WORD_W - 1:0] o_res_rd_data;\n              ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:33: Define or directive not defined: \'`MEM_CODE_W\'\n  output reg [`MEM_CODE_W - 1:0] o_res_code;\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:36: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] r_mem [0:WORD_COUNT - 1];\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:39: Define or directive not defined: \'`ADDR_W\'\n  wire [`ADDR_W - 2 - 1:0] s_addr_aligned;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:42: Define or directive not defined: \'`ADDR_W\'\n  assign s_addr_aligned = i_req_addr[`ADDR_W - 1:2];\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:49: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile(DUMP_FILE);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:51: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, r_mem[i]);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:67: Define or directive not defined: \'`MEM_COUNT_NONE\'\n    end else if(i_req_count != `MEM_COUNT_NONE) begin\n                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:67: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    end else if(i_req_count != `MEM_COUNT_NONE) begin\n                                              ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:69: Define or directive not defined: \'`MEM_COUNT_HALF\'\n      if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||\n                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:70: Define or directive not defined: \'`MEM_COUNT_WORD\'\n        (i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin\n                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:73: Define or directive not defined: \'`MEM_CODE_MISALIGNED\'\n        o_res_code <= `MEM_CODE_MISALIGNED;\n                      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:73: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        o_res_code <= `MEM_CODE_MISALIGNED;\n                                          ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:78: Define or directive not defined: \'`MEM_CODE_OUT_OF_BOUNDS\'\n        o_res_code <= `MEM_CODE_OUT_OF_BOUNDS;\n                      ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:84: Define or directive not defined: \'`MEM_CODE_WRITE\'\n        o_res_code <= `MEM_CODE_WRITE;\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:88: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n          `MEM_COUNT_BYTE:\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:88: syntax error, unexpected \':\', expecting endcase\n          `MEM_COUNT_BYTE:\n                         ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:96: Define or directive not defined: \'`MEM_COUNT_HALF\'\n          `MEM_COUNT_HALF:\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:102: Define or directive not defined: \'`MEM_COUNT_WORD\'\n          `MEM_COUNT_WORD: r_mem[s_addr_aligned] <= i_req_wr_data;\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:104: Define or directive not defined: \'`MEM_CODE_INVALID\'\n          default: o_res_code <= `MEM_CODE_INVALID;\n                                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:111: Define or directive not defined: \'`MEM_CODE_READ\'\n        o_res_code <= `MEM_CODE_READ;\n                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:115: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n          `MEM_COUNT_BYTE:\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:115: syntax error, unexpected \':\', expecting endcase\n          `MEM_COUNT_BYTE:\n                         ^\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:124: Define or directive not defined: \'`MEM_COUNT_HALF\'\n          `MEM_COUNT_HALF:\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:131: Define or directive not defined: \'`MEM_COUNT_WORD\'\n          `MEM_COUNT_WORD: o_res_rd_data <= r_mem[s_addr_aligned];\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:133: Define or directive not defined: \'`MEM_CODE_INVALID\'\n          default: o_res_code <= `MEM_CODE_INVALID;\n                                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/memory_peripheral/memory_interface.v:141: Define or directive not defined: \'`MEM_CODE_INVALID\'\n      o_res_code <= `MEM_CODE_INVALID;\n                    ^~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module memory_interface(
  clk,
  aresetn,

  i_req_addr,
  i_req_wr_data,
  i_req_wr_en,
  i_req_count,

  o_res_rd_data,
  o_res_code
);
  parameter WORD_COUNT = 1 << (`ADDR_W - 2);

  parameter DUMP_VARS = 0;
  parameter DUMP_FILE = "a.vcd";


  input clk;
  input aresetn;

  input [`ADDR_W - 1:0] i_req_addr;
  input [`WORD_W - 1:0] i_req_wr_data;
  input i_req_wr_en;
  input [`MEM_COUNT_W - 1:0] i_req_count;


  output reg [`WORD_W - 1:0] o_res_rd_data;
  output reg [`MEM_CODE_W - 1:0] o_res_code;


  reg [`WORD_W - 1:0] r_mem [0:WORD_COUNT - 1];


  wire [`ADDR_W - 2 - 1:0] s_addr_aligned;
  wire [1:0] s_offset;

  assign s_addr_aligned = i_req_addr[`ADDR_W - 1:2];
  assign s_offset = i_req_addr[1:0];

  integer i;

  initial begin
    if(DUMP_VARS == 1) begin
      $dumpfile(DUMP_FILE);
      for(i = 0; i < WORD_COUNT; i = i + 1) begin
        $dumpvars(0, r_mem[i]);
      end
    end
  end

  always@(posedge clk, negedge aresetn) begin
    if(aresetn == 0) begin

      for(i = 0; i < WORD_COUNT; i = i + 1) begin
        r_mem[i] <= 0;
      end

      o_res_rd_data <= 0;
      o_res_code <= 0;


    end else if(i_req_count != `MEM_COUNT_NONE) begin

      if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||
        (i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin

        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_MISALIGNED;


      end else if(s_addr_aligned >= WORD_COUNT) begin
        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_OUT_OF_BOUNDS;


      end else if(i_req_wr_en == 1) begin

        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_WRITE;


        case(i_req_count)
          `MEM_COUNT_BYTE:
            case(s_offset)
              0: r_mem[s_addr_aligned][7:0] <= i_req_wr_data[7:0];
              1: r_mem[s_addr_aligned][15:8] <= i_req_wr_data[7:0];
              2: r_mem[s_addr_aligned][23:16] <= i_req_wr_data[7:0];
              3: r_mem[s_addr_aligned][31:24] <= i_req_wr_data[7:0];
            endcase

          `MEM_COUNT_HALF:
            case(s_offset)
              0: r_mem[s_addr_aligned][15:0] <= i_req_wr_data[15:0];
              2: r_mem[s_addr_aligned][31:16] <= i_req_wr_data[15:0];
            endcase

          `MEM_COUNT_WORD: r_mem[s_addr_aligned] <= i_req_wr_data;

          default: o_res_code <= `MEM_CODE_INVALID;
        endcase

      end else begin


        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_READ;


        case(i_req_count)
          `MEM_COUNT_BYTE:
            case(s_offset)
              0: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][7:0];
              1: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][15:8];
              2: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][23:16];
              3: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][31:24];
              default: o_res_rd_data <= 0;
            endcase

          `MEM_COUNT_HALF:
            case(s_offset)
              0: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][15:0];
              2: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][31:16];
              default: o_res_rd_data <= 0;
            endcase

          `MEM_COUNT_WORD: o_res_rd_data <= r_mem[s_addr_aligned];

          default: o_res_code <= `MEM_CODE_INVALID;
        endcase

      end

    end else begin

      o_res_rd_data <= 0;
      o_res_code <= `MEM_CODE_INVALID;

    end
  end

endmodule
module memory_interface(
  clk,
  aresetn,

  i_req_addr,
  i_req_wr_data,
  i_req_wr_en,
  i_req_count,

  o_res_rd_data,
  o_res_code
);

  parameter WORD_COUNT = 1 << (`ADDR_W - 2);

  parameter DUMP_VARS = 0;
  parameter DUMP_FILE = "a.vcd";


  input clk;
  input aresetn;

  input [`ADDR_W - 1:0] i_req_addr;
  input [`WORD_W - 1:0] i_req_wr_data;
  input i_req_wr_en;
  input [`MEM_COUNT_W - 1:0] i_req_count;


  output reg [`WORD_W - 1:0] o_res_rd_data;
  output reg [`MEM_CODE_W - 1:0] o_res_code;


  reg [`WORD_W - 1:0] r_mem [0:WORD_COUNT - 1];


  wire [`ADDR_W - 2 - 1:0] s_addr_aligned;
  wire [1:0] s_offset;

  assign s_addr_aligned = i_req_addr[`ADDR_W - 1:2];
  assign s_offset = i_req_addr[1:0];

  integer i;

  initial begin
    if(DUMP_VARS == 1) begin
      $dumpfile(DUMP_FILE);
      for(i = 0; i < WORD_COUNT; i = i + 1) begin
        $dumpvars(0, r_mem[i]);
      end
    end
  end

  always@(posedge clk, negedge aresetn) begin
    if(aresetn == 0) begin

      for(i = 0; i < WORD_COUNT; i = i + 1) begin
        r_mem[i] <= 0;
      end

      o_res_rd_data <= 0;
      o_res_code <= 0;


    end else if(i_req_count != `MEM_COUNT_NONE) begin

      if((i_req_count == `MEM_COUNT_HALF && s_offset[0] != 0) ||
        (i_req_count == `MEM_COUNT_WORD && s_offset != 0)) begin

        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_MISALIGNED;


      end else if(s_addr_aligned >= WORD_COUNT) begin
        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_OUT_OF_BOUNDS;


      end else if(i_req_wr_en == 1) begin

        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_WRITE;


        case(i_req_count)
          `MEM_COUNT_BYTE:
            case(s_offset)
              0: r_mem[s_addr_aligned][7:0] <= i_req_wr_data[7:0];
              1: r_mem[s_addr_aligned][15:8] <= i_req_wr_data[7:0];
              2: r_mem[s_addr_aligned][23:16] <= i_req_wr_data[7:0];
              3: r_mem[s_addr_aligned][31:24] <= i_req_wr_data[7:0];
            endcase

          `MEM_COUNT_HALF:
            case(s_offset)
              0: r_mem[s_addr_aligned][15:0] <= i_req_wr_data[15:0];
              2: r_mem[s_addr_aligned][31:16] <= i_req_wr_data[15:0];
            endcase

          `MEM_COUNT_WORD: r_mem[s_addr_aligned] <= i_req_wr_data;

          default: o_res_code <= `MEM_CODE_INVALID;
        endcase

      end else begin


        o_res_rd_data <= 0;
        o_res_code <= `MEM_CODE_READ;


        case(i_req_count)
          `MEM_COUNT_BYTE:
            case(s_offset)
              0: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][7:0];
              1: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][15:8];
              2: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][23:16];
              3: o_res_rd_data[7:0] <= r_mem[s_addr_aligned][31:24];
              default: o_res_rd_data <= 0;
            endcase

          `MEM_COUNT_HALF:
            case(s_offset)
              0: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][15:0];
              2: o_res_rd_data[15:0] <= r_mem[s_addr_aligned][31:16];
              default: o_res_rd_data <= 0;
            endcase

          `MEM_COUNT_WORD: o_res_rd_data <= r_mem[s_addr_aligned];

          default: o_res_code <= `MEM_CODE_INVALID;
        endcase

      end

    end else begin

      o_res_rd_data <= 0;
      o_res_code <= `MEM_CODE_INVALID;

    end
  end

endmodule