data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf/outputNetwork.v
1: b"%Error: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf/outputNetwork.v:14: Cannot find file containing module: 'xor_vec'\n    xor_vec #(.X(X)) XG(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf,data/full_repos/permissive/128781882/xor_vec\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf,data/full_repos/permissive/128781882/xor_vec.v\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf,data/full_repos/permissive/128781882/xor_vec.sv\n             xor_vec\n             xor_vec.v\n             xor_vec.sv\n             obj_dir/xor_vec\n             obj_dir/xor_vec.v\n             obj_dir/xor_vec.sv\n%Error: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf/outputNetwork.v:25: Cannot find file containing module: 'xor_vec'\n    xor_vec #(.X(X)) XG(\n    ^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module outputNetwork  #(parameter K=10,X=K-1,M=K-1,S=0) (in,out);

	input [K-1:0] in;
	output [M-1:0] out;
	
	genvar i;
	generate
		for(i=0; i<M; i=i+1) begin: OUT
		
			if( (i+S+X-1) < K ) begin
			
				(*KEEP_HIERARCHY="TRUE"*)
				xor_vec #(.X(X)) XG(
					.x(in[(i+S+X-1)%K:i]), 
					.y(out[i])
				);
				
				initial 
			  $display ("<in[%d:%d]>", (i+S+X-1)%K, i);
				
			end else begin
			
				(*KEEP_HIERARCHY="TRUE"*)
				xor_vec #(.X(X)) XG(
					.x({in[K-1:i],in[(i+S+X-1)%K:0]}), 
					.y(out[i])
				);
				
			  initial 
			  $display ("<in[%d:%d] in[%d:0]>",K-1,i,(i+S+X-1)%K);
			end
			
		end
	endgenerate


endmodule
module outputNetwork  #(parameter K=10,X=K-1,M=K-1,S=0) (in,out);


	input [K-1:0] in;
	output [M-1:0] out;
	
	genvar i;
	generate
		for(i=0; i<M; i=i+1) begin: OUT
		
			if( (i+S+X-1) < K ) begin
			
				(*KEEP_HIERARCHY="TRUE"*)
				xor_vec #(.X(X)) XG(
					.x(in[(i+S+X-1)%K:i]), 
					.y(out[i])
				);
				
				initial 
			  $display ("<in[%d:%d]>", (i+S+X-1)%K, i);
				
			end else begin
			
				(*KEEP_HIERARCHY="TRUE"*)
				xor_vec #(.X(X)) XG(
					.x({in[K-1:i],in[(i+S+X-1)%K:0]}), 
					.y(out[i])
				);
				
			  initial 
			  $display ("<in[%d:%d] in[%d:0]>",K-1,i,(i+S+X-1)%K);
			end
			
		end
	endgenerate


endmodule