data/full_repos/permissive/190595283/Modulos/ALU.v
data/verilator_xmls/f01d8b50-d5e3-45d9-a9e9-a55c7e09603e.xml
module ALU (controle,a,b,zero,saida);
  input wire [3:0]controle;
  input wire [31:0]a;
  input wire [31:0]b;
  output reg [31:0]saida;
  output zero;
  always @ (a or b or controle) begin
    case (controle)
      `ALU_ADD: saida <= a + b;
      `ALU_SUB: saida <= a - b;
      `ALU_AND: saida <= a & b;
      `ALU_OR:  saida <= a | b;
      `ALU_NOR: saida <= ~(a | b);
      `ALU_XOR: saida <= a ^ b;
      `ALU_SLT: saida <= a < b ? 1 : 0;
      default: saida <= 0;
    endcase
  end
  assign zero = (saida == 0);
endmodule
module ALU (controle,a,b,zero,saida);

  input wire [3:0]controle;
  input wire [31:0]a;
  input wire [31:0]b;
  output reg [31:0]saida;
  output zero;
  always @ (a or b or controle) begin
    case (controle)
      `ALU_ADD: saida <= a + b;
      `ALU_SUB: saida <= a - b;
      `ALU_AND: saida <= a & b;
      `ALU_OR:  saida <= a | b;
      `ALU_NOR: saida <= ~(a | b);
      `ALU_XOR: saida <= a ^ b;
      `ALU_SLT: saida <= a < b ? 1 : 0;
      default: saida <= 0;
    endcase
  end
  assign zero = (saida == 0);
endmodule