data/full_repos/permissive/112861986/src/examples/2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/112861986/src/examples/2.v:23: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance example_2\nreg [7:0] num = 7\'h00;\n                ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/112861986/src/examples/2.v:35: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance example_2\n  num = 7\'h00;\n      ^\n%Error: data/full_repos/permissive/112861986/src/examples/2.v:38: Cannot find file containing module: \'bin_to_7seg\'\nbin_to_7seg inst\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/112861986/src/examples,data/full_repos/permissive/112861986/bin_to_7seg\n             data/full_repos/permissive/112861986/src/examples,data/full_repos/permissive/112861986/bin_to_7seg.v\n             data/full_repos/permissive/112861986/src/examples,data/full_repos/permissive/112861986/bin_to_7seg.sv\n             bin_to_7seg\n             bin_to_7seg.v\n             bin_to_7seg.sv\n             obj_dir/bin_to_7seg\n             obj_dir/bin_to_7seg.v\n             obj_dir/bin_to_7seg.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module example_2
(
	input i_switch_1,
	input i_switch_2,
	input i_switch_3,
	input i_switch_4,
	output o_segment1_a,
	output o_segment1_b,
	output o_segment1_c,
	output o_segment1_d,
	output o_segment1_e,
	output o_segment1_f,
	output o_segment1_g,
	output o_segment2_a,
	output o_segment2_b,
	output o_segment2_c,
	output o_segment2_d,
	output o_segment2_e,
	output o_segment2_f,
	output o_segment2_g
);

reg [7:0] num = 7'h00;
reg [7:0] seg_1;
reg [7:0] seg_2;

always @(posedge i_switch_1)
begin
	num = num + 1;
	if (i_switch_2 == 1'b1)
		num = num ^ 1;
	if (i_switch_3 == 1'b1)
		num = num << 1;
	if (i_switch_4 == 1'b1)
		num = 7'h00;
end

bin_to_7seg inst
(
	.in_byte(num),
	.out_seg1(seg_1),
	.out_seg2(seg_2)
);


assign o_segment1_a = ~seg_2[6];
assign o_segment1_b = ~seg_2[5];
assign o_segment1_c = ~seg_2[4];
assign o_segment1_d = ~seg_2[3];
assign o_segment1_e = ~seg_2[2];
assign o_segment1_f = ~seg_2[1];
assign o_segment1_g = ~seg_2[0];
assign o_segment2_a = ~seg_1[6];
assign o_segment2_b = ~seg_1[5];
assign o_segment2_c = ~seg_1[4];
assign o_segment2_d = ~seg_1[3];
assign o_segment2_e = ~seg_1[2];
assign o_segment2_f = ~seg_1[1];
assign o_segment2_g = ~seg_1[0];

endmodule
module example_2
(
	input i_switch_1,
	input i_switch_2,
	input i_switch_3,
	input i_switch_4,
	output o_segment1_a,
	output o_segment1_b,
	output o_segment1_c,
	output o_segment1_d,
	output o_segment1_e,
	output o_segment1_f,
	output o_segment1_g,
	output o_segment2_a,
	output o_segment2_b,
	output o_segment2_c,
	output o_segment2_d,
	output o_segment2_e,
	output o_segment2_f,
	output o_segment2_g
);


reg [7:0] num = 7'h00;
reg [7:0] seg_1;
reg [7:0] seg_2;

always @(posedge i_switch_1)
begin
	num = num + 1;
	if (i_switch_2 == 1'b1)
		num = num ^ 1;
	if (i_switch_3 == 1'b1)
		num = num << 1;
	if (i_switch_4 == 1'b1)
		num = 7'h00;
end

bin_to_7seg inst
(
	.in_byte(num),
	.out_seg1(seg_1),
	.out_seg2(seg_2)
);


assign o_segment1_a = ~seg_2[6];
assign o_segment1_b = ~seg_2[5];
assign o_segment1_c = ~seg_2[4];
assign o_segment1_d = ~seg_2[3];
assign o_segment1_e = ~seg_2[2];
assign o_segment1_f = ~seg_2[1];
assign o_segment1_g = ~seg_2[0];
assign o_segment2_a = ~seg_1[6];
assign o_segment2_b = ~seg_1[5];
assign o_segment2_c = ~seg_1[4];
assign o_segment2_d = ~seg_1[3];
assign o_segment2_e = ~seg_1[2];
assign o_segment2_f = ~seg_1[1];
assign o_segment2_g = ~seg_1[0];

endmodule