data/full_repos/permissive/211866113/ACC_RAM_test.v
 line:242: before: "+"
1: b'%Error: data/full_repos/permissive/211866113/ACC_RAM_test.v:1: Cannot find include file: Accumulator.v\n`include "Accumulator.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/Accumulator.v\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/Accumulator.v.v\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/Accumulator.v.sv\n             Accumulator.v\n             Accumulator.v.v\n             Accumulator.v.sv\n             obj_dir/Accumulator.v\n             obj_dir/Accumulator.v.v\n             obj_dir/Accumulator.v.sv\n%Error: data/full_repos/permissive/211866113/ACC_RAM_test.v:2: Cannot find include file: word_gen.v\n`include "word_gen.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/211866113/ACC_RAM_test.v:3: Cannot find include file: RAM.v\n`include "RAM.v" \n         ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ACC_RAM_test.v:43: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/211866113/ACC_RAM_test.v:47: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("Accumulator_RAM_test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/211866113/ACC_RAM_test.v:48: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0);  \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ACC_RAM_test.v:61: Unsupported: Ignoring delay on this delayed statement.\n            #3 gen_next = FALSE;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ACC_RAM_test.v:64: Unsupported: Ignoring delay on this delayed statement.\n            #1 WE = FALSE;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ACC_RAM_test.v:66: Unsupported: Ignoring delay on this delayed statement.\n            #1 ADDRESS++;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ACC_RAM_test.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = TRUE;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ACC_RAM_test.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #5 reset = FALSE;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ACC_RAM_test.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #5 ADDRESS = 2\'b00;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ACC_RAM_test.v:79: Unsupported: Ignoring delay on this delayed statement.\n                #5 OE = FALSE;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ACC_RAM_test.v:78: Unsupported: Ignoring delay on this delayed statement.\n            #5 if(i == 3) begin\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ACC_RAM_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n            #5 ADDRESS++;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ACC_RAM_test.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #5 $finish;\n        ^\n%Error: Exiting due to 5 error(s), 11 warning(s)\n'
module Accumulator_for_RAM_tester ();
    parameter FALSE = 1'b0;
    parameter TRUE = 1'b1;

    integer i;

    reg     clk = 1'b0;


    reg     gen_next;


    wire [2:0] Output;
    wire       carry;
    reg        reset;


    reg [1:0]  ADDRESS;
    wire [2:0] DATA;
    wire [2:0] OUT;

    reg        CS, WE, OE;

    word_gen my_gen(gen_next, DATA);
    RAM_module my_RAM(ADDRESS, DATA, OUT, CS, WE, OE);
    accumulator my_acc(clk, reset, OUT, Output);

    always begin
	clk <= ~clk;
	#5;
    end

    initial begin
        $dumpfile("Accumulator_RAM_test.vcd");
        $dumpvars(0);


        i=0;
        OE = FALSE;
        WE = FALSE;
        CS = FALSE;
        gen_next = FALSE;
        reset = FALSE;

        ADDRESS = 2'b00;

        for (i = 0; i< 4; i = i + 1) begin
            #3 gen_next = FALSE;
            WE = TRUE;
            CS = TRUE;
            #1 WE = FALSE;
            CS = FALSE;
            #1 ADDRESS++;
            gen_next = TRUE;
        end


        #10 reset = TRUE;
        #5 reset = FALSE;
        #5 ADDRESS = 2'b00;
        OE = TRUE;
        CS = TRUE;

        for (i = 0; i< 4; i = i + 1) begin
            #5 if(i == 3) begin
                #5 OE = FALSE;
                CS = FALSE;
		        $finish;
            end
            #5 ADDRESS++;
            CS = FALSE;
            CS = TRUE;
        end
        #5 $finish;
    end

endmodule
module Accumulator_for_RAM_tester ();

    parameter FALSE = 1'b0;
    parameter TRUE = 1'b1;

    integer i;

    reg     clk = 1'b0;


    reg     gen_next;


    wire [2:0] Output;
    wire       carry;
    reg        reset;


    reg [1:0]  ADDRESS;
    wire [2:0] DATA;
    wire [2:0] OUT;

    reg        CS, WE, OE;

    word_gen my_gen(gen_next, DATA);
    RAM_module my_RAM(ADDRESS, DATA, OUT, CS, WE, OE);
    accumulator my_acc(clk, reset, OUT, Output);

    always begin
	clk <= ~clk;
	#5;
    end

    initial begin
        $dumpfile("Accumulator_RAM_test.vcd");
        $dumpvars(0);


        i=0;
        OE = FALSE;
        WE = FALSE;
        CS = FALSE;
        gen_next = FALSE;
        reset = FALSE;

        ADDRESS = 2'b00;

        for (i = 0; i< 4; i = i + 1) begin
            #3 gen_next = FALSE;
            WE = TRUE;
            CS = TRUE;
            #1 WE = FALSE;
            CS = FALSE;
            #1 ADDRESS++;
            gen_next = TRUE;
        end


        #10 reset = TRUE;
        #5 reset = FALSE;
        #5 ADDRESS = 2'b00;
        OE = TRUE;
        CS = TRUE;

        for (i = 0; i< 4; i = i + 1) begin
            #5 if(i == 3) begin
                #5 OE = FALSE;
                CS = FALSE;
		        $finish;
            end
            #5 ADDRESS++;
            CS = FALSE;
            CS = TRUE;
        end
        #5 $finish;
    end

endmodule