data/full_repos/permissive/131069375/uv-risc/verilog/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/131069375/uv-risc/verilog/testbench.v:8: Unsupported: Ignoring delay on this delayed statement.\n      #12 reset = 0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/131069375/uv-risc/verilog/testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/131069375/uv-risc/verilog/testbench.v:19: Cannot find file containing module: \'instr_mem\'\n   instr_mem imem (.clk(clk),.addr(pc),.data_out(instr));\n   ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131069375/uv-risc/verilog,data/full_repos/permissive/131069375/instr_mem\n             data/full_repos/permissive/131069375/uv-risc/verilog,data/full_repos/permissive/131069375/instr_mem.v\n             data/full_repos/permissive/131069375/uv-risc/verilog,data/full_repos/permissive/131069375/instr_mem.sv\n             instr_mem\n             instr_mem.v\n             instr_mem.sv\n             obj_dir/instr_mem\n             obj_dir/instr_mem.v\n             obj_dir/instr_mem.sv\n%Error: data/full_repos/permissive/131069375/uv-risc/verilog/testbench.v:24: Cannot find file containing module: \'data_mem\'\n   data_mem dmem (.clk(clk),.we(mem_we),\n   ^~~~~~~~\n%Error: data/full_repos/permissive/131069375/uv-risc/verilog/testbench.v:30: Cannot find file containing module: \'uvrisc\'\n   uvrisc uvrisc0 (.reset(reset),.clk(clk),.pc(pc),.instr(instr),\n   ^~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
   reg clk, reset;

   initial begin
      reset = 1;
      #12 reset = 0;
   end


   initial
     clk = 1;
   always #5 clk = ~clk;


   wire [15:0] 		   pc, instr;
   
   instr_mem imem (.clk(clk),.addr(pc),.data_out(instr));


   wire [15:0] 		   mem_in, mem_out, mem_addr;

   data_mem dmem (.clk(clk),.we(mem_we),
		  .addr(mem_addr),.data_in(mem_in),.data_out(mem_out));


   wire 		   halt;
   
   uvrisc uvrisc0 (.reset(reset),.clk(clk),.pc(pc),.instr(instr),
		   .mem_we(mem_we),.mem_addr(mem_addr),
		   .mem_in(mem_in),.mem_out(mem_out),
		   .halt(halt));

   always @(posedge clk)
     if (halt)
       $finish;
   
endmodule
module testbench;

   reg clk, reset;

   initial begin
      reset = 1;
      #12 reset = 0;
   end


   initial
     clk = 1;
   always #5 clk = ~clk;


   wire [15:0] 		   pc, instr;
   
   instr_mem imem (.clk(clk),.addr(pc),.data_out(instr));


   wire [15:0] 		   mem_in, mem_out, mem_addr;

   data_mem dmem (.clk(clk),.we(mem_we),
		  .addr(mem_addr),.data_in(mem_in),.data_out(mem_out));


   wire 		   halt;
   
   uvrisc uvrisc0 (.reset(reset),.clk(clk),.pc(pc),.instr(instr),
		   .mem_we(mem_we),.mem_addr(mem_addr),
		   .mem_in(mem_in),.mem_out(mem_out),
		   .halt(halt));

   always @(posedge clk)
     if (halt)
       $finish;
   
endmodule