data/full_repos/permissive/142990562/FPGA Image Process.v/LineBuffer.v
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1: b'%Error: Cannot find file containing module: Image\n        ... Looked in:\n             data/full_repos/permissive/142990562/FPGA/Image\n             data/full_repos/permissive/142990562/FPGA/Image.v\n             data/full_repos/permissive/142990562/FPGA/Image.sv\n             Image\n             Image.v\n             Image.sv\n             obj_dir/Image\n             obj_dir/Image.v\n             obj_dir/Image.sv\n%Error: Cannot find file containing module: Process.v,data/full_repos/permissive/142990562\n%Error: Cannot find file containing module: data/full_repos/permissive/142990562/FPGA\n%Error: Cannot find file containing module: Process.v/LineBuffer.v\n%Error: Exiting due to 4 error(s)\n'
module LineBuffer
   #(
   parameter DATA_WIDTH      =  8,
   parameter ADDR_WIDTH      = 11,
   parameter OPERATOR_HEIGHT =  3
   )
   (
    input                                               clk           ,
    input                                               DataEn        ,
    input  [DATA_WIDTH - 1                         : 0] PixelData     ,
    output [ADDR_WIDTH - 1                         : 0] addra         ,
    input  [(OPERATOR_HEIGHT - 1) * DATA_WIDTH - 1 : 0] douta         ,
    output                                              web           ,
    output [ADDR_WIDTH - 1                         : 0] addrb         ,
    output [(OPERATOR_HEIGHT - 1) * DATA_WIDTH - 1 : 0] dinb          ,
    output                                              OperatorDataEn,
    output [OPERATOR_HEIGHT * DATA_WIDTH - 1       : 0] OperatorData    
    );
    
    reg    [ADDR_WIDTH - 1                         : 0] FrogCount = 0  ;
    reg    [DATA_WIDTH - 1                         : 0] PixelDataReg   ;
    reg    [OPERATOR_HEIGHT * DATA_WIDTH - 1       : 0] OperatorDataReg;
    reg    [1                                      : 0] DataEnReg      ;
    
    assign addra          = FrogCount      ,
           OperatorData   = OperatorDataReg,
           OperatorDataEn = DataEnReg[1]   ,
           addrb          = FrogCount - 2  ,
           web            = DataEnReg[1]   ,
           dinb           = OperatorDataReg[OPERATOR_HEIGHT * DATA_WIDTH - 1 : DATA_WIDTH];  

    always@(posedge clk)
    begin
      if(DataEn || OperatorDataEn)
        FrogCount     <= FrogCount + 1;
      else            
        FrogCount     <= 0;
      PixelDataReg    <= PixelData;
      OperatorDataReg <= {PixelDataReg,douta};
      DataEnReg[0]    <= DataEn;
      DataEnReg[1]    <= DataEnReg[0];
    end 
    
endmodule
module LineBuffer
   #(
   parameter DATA_WIDTH      =  8,
   parameter ADDR_WIDTH      = 11,
   parameter OPERATOR_HEIGHT =  3
   )
   (
    input                                               clk           ,
    input                                               DataEn        ,
    input  [DATA_WIDTH - 1                         : 0] PixelData     ,
    output [ADDR_WIDTH - 1                         : 0] addra         ,
    input  [(OPERATOR_HEIGHT - 1) * DATA_WIDTH - 1 : 0] douta         ,
    output                                              web           ,
    output [ADDR_WIDTH - 1                         : 0] addrb         ,
    output [(OPERATOR_HEIGHT - 1) * DATA_WIDTH - 1 : 0] dinb          ,
    output                                              OperatorDataEn,
    output [OPERATOR_HEIGHT * DATA_WIDTH - 1       : 0] OperatorData    
    );

    
    reg    [ADDR_WIDTH - 1                         : 0] FrogCount = 0  ;
    reg    [DATA_WIDTH - 1                         : 0] PixelDataReg   ;
    reg    [OPERATOR_HEIGHT * DATA_WIDTH - 1       : 0] OperatorDataReg;
    reg    [1                                      : 0] DataEnReg      ;
    
    assign addra          = FrogCount      ,
           OperatorData   = OperatorDataReg,
           OperatorDataEn = DataEnReg[1]   ,
           addrb          = FrogCount - 2  ,
           web            = DataEnReg[1]   ,
           dinb           = OperatorDataReg[OPERATOR_HEIGHT * DATA_WIDTH - 1 : DATA_WIDTH];  

    always@(posedge clk)
    begin
      if(DataEn || OperatorDataEn)
        FrogCount     <= FrogCount + 1;
      else            
        FrogCount     <= 0;
      PixelDataReg    <= PixelData;
      OperatorDataReg <= {PixelDataReg,douta};
      DataEnReg[0]    <= DataEn;
      DataEnReg[1]    <= DataEnReg[0];
    end 
    
endmodule