data/full_repos/permissive/203650831/hd44780_ram_tb.v
 line:80: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_ram_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = (clk === 1\'b0);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/203650831/hd44780_ram_tb.v:58: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("hd44780_ram_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_ram_tb.v:59: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, hd44780_ram_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_ram_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #90 addr_w_reg = 8\'b0110_1101;             \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_ram_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #10 ram_wen = 1;                                     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_ram_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #170 ram_wen = 0;             \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_ram_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #500 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hd44780_ram_tb;


    reg clk = 1;


    always #5 clk = (clk === 1'b0);



    parameter address_bits = 8, data_bits = 16;

    reg [address_bits-1:0] start_addr = 0;
    reg [address_bits-1:0] addr_w_reg = 0;
    reg [address_bits-1:0] addr_r_reg = 0;
    reg [data_bits-1:0] data_w_reg = 0;
    reg [data_bits-1:0] data_r_reg = 0;
    wire [data_bits-1:0] data_r_wire;
    reg ram_wen = 0;

    hd44780_ram #(.initfile("settings/testmem.mem"),.filehex(0),.addr_width(address_bits),.data_width(data_bits)) rammy(
        .din(data_w_reg),
        .write_en(ram_wen),
        .waddr(addr_w_reg),
        .wclk(clk),
        .raddr(addr_r_reg),
        .rclk(clk),
        .dout(data_r_wire));


    always @(posedge clk) begin


        data_r_reg <= data_r_wire;
    end


    initial begin
        $dumpfile("hd44780_ram_tb.vcd");
        $dumpvars(0, hd44780_ram_tb);
    end

    initial begin









        #90 addr_w_reg = 8'b0110_1101;
        data_w_reg = 8'b1010_0101;
        addr_r_reg = 8'b0110_1101;
        #10 ram_wen = 1;
        #170 ram_wen = 0;



        #500 $finish;
    end

endmodule
module hd44780_ram_tb;



    reg clk = 1;


    always #5 clk = (clk === 1'b0);



    parameter address_bits = 8, data_bits = 16;

    reg [address_bits-1:0] start_addr = 0;
    reg [address_bits-1:0] addr_w_reg = 0;
    reg [address_bits-1:0] addr_r_reg = 0;
    reg [data_bits-1:0] data_w_reg = 0;
    reg [data_bits-1:0] data_r_reg = 0;
    wire [data_bits-1:0] data_r_wire;
    reg ram_wen = 0;

    hd44780_ram #(.initfile("settings/testmem.mem"),.filehex(0),.addr_width(address_bits),.data_width(data_bits)) rammy(
        .din(data_w_reg),
        .write_en(ram_wen),
        .waddr(addr_w_reg),
        .wclk(clk),
        .raddr(addr_r_reg),
        .rclk(clk),
        .dout(data_r_wire));


    always @(posedge clk) begin


        data_r_reg <= data_r_wire;
    end


    initial begin
        $dumpfile("hd44780_ram_tb.vcd");
        $dumpvars(0, hd44780_ram_tb);
    end

    initial begin









        #90 addr_w_reg = 8'b0110_1101;
        data_w_reg = 8'b1010_0101;
        addr_r_reg = 8'b0110_1101;
        #10 ram_wen = 1;
        #170 ram_wen = 0;



        #500 $finish;
    end

endmodule