data/full_repos/permissive/206783267/UART/DUT/uart_duplex.v
1: b"%Error: data/full_repos/permissive/206783267/UART/DUT/uart_duplex.v:22: Cannot find file containing module: 'uart_tx'\nuart_tx\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206783267/UART/DUT,data/full_repos/permissive/206783267/uart_tx\n             data/full_repos/permissive/206783267/UART/DUT,data/full_repos/permissive/206783267/uart_tx.v\n             data/full_repos/permissive/206783267/UART/DUT,data/full_repos/permissive/206783267/uart_tx.sv\n             uart_tx\n             uart_tx.v\n             uart_tx.sv\n             obj_dir/uart_tx\n             obj_dir/uart_tx.v\n             obj_dir/uart_tx.sv\n%Error: data/full_repos/permissive/206783267/UART/DUT/uart_duplex.v:38: Cannot find file containing module: 'uart_rx'\nuart_rx\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module uart_duplex
#(
	parameter	CLK_FREQ = 50_000_000,
				BAUD_RATE = 115200,
				PARITY = "NONE",
				DATA_WIDTH = 8
)
(
	input	clk, arstn,
	input	tx_start,
	input	[DATA_WIDTH-1:0]	tx_data,
	output	tx_done,
	output	[DATA_WIDTH-1:0]	rx_data,
	output	rx_done,
	output	rx_error
);

wire	serial;

uart_tx
#(
	.CLK_FREQ(CLK_FREQ),
	.BAUD_RATE(BAUD_RATE),
	.PARITY(PARITY),
	.DATA_WIDTH(DATA_WIDTH)
)
uart_tx_inst(
	.clk(clk), 
	.arstn(arstn),
	.tx_start(tx_start),
	.tx_done(tx_done),
	.tx_data(tx_data),
	.TXD(serial)
);

uart_rx
#(
	.CLK_FREQ(CLK_FREQ),
	.BAUD_RATE(BAUD_RATE),
	.PARITY(PARITY),
	.DATA_WIDTH(DATA_WIDTH)
)
uart_rx_inst(
	.clk(clk), 
	.arstn(arstn),
	.rx_error(rx_error),
	.rx_done(rx_done),
	.rx_data(rx_data),
	.RXD(serial)
);

endmodule
module uart_duplex
#(
	parameter	CLK_FREQ = 50_000_000,
				BAUD_RATE = 115200,
				PARITY = "NONE",
				DATA_WIDTH = 8
)
(
	input	clk, arstn,
	input	tx_start,
	input	[DATA_WIDTH-1:0]	tx_data,
	output	tx_done,
	output	[DATA_WIDTH-1:0]	rx_data,
	output	rx_done,
	output	rx_error
);


wire	serial;

uart_tx
#(
	.CLK_FREQ(CLK_FREQ),
	.BAUD_RATE(BAUD_RATE),
	.PARITY(PARITY),
	.DATA_WIDTH(DATA_WIDTH)
)
uart_tx_inst(
	.clk(clk), 
	.arstn(arstn),
	.tx_start(tx_start),
	.tx_done(tx_done),
	.tx_data(tx_data),
	.TXD(serial)
);

uart_rx
#(
	.CLK_FREQ(CLK_FREQ),
	.BAUD_RATE(BAUD_RATE),
	.PARITY(PARITY),
	.DATA_WIDTH(DATA_WIDTH)
)
uart_rx_inst(
	.clk(clk), 
	.arstn(arstn),
	.rx_error(rx_error),
	.rx_done(rx_done),
	.rx_data(rx_data),
	.RXD(serial)
);

endmodule