data/full_repos/permissive/143278/ivltests/vhdl_delay_assign.v
 line:24: before: "="
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_delay_assign.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #11;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_delay_assign.v:25: Cannot find file containing module: \'vhdl_delay_assign\'\nvhdl_delay_assign dut(a, b, c);\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_delay_assign\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_delay_assign.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_delay_assign.sv\n             vhdl_delay_assign\n             vhdl_delay_assign.v\n             vhdl_delay_assign.sv\n             obj_dir/vhdl_delay_assign\n             obj_dir/vhdl_delay_assign.v\n             obj_dir/vhdl_delay_assign.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vhdl_delay_assign_test;
logic a, b, c;
int passed = 0;
vhdl_delay_assign dut(a, b, c);

always @(b)
begin
    if($time == 10) begin
        passed = passed + 1;
    end else begin
        $display("FAILED 1");
        $finish();
    end
end

always @(c)
begin
    if($time == 10) begin
        passed = passed + 1;
    end else begin
        $display("FAILED 2");
        $finish();
    end
end

initial begin
    a = 1;
    #11;

    if(passed !== 2) begin
        $display("FAILED 3");
        $finish();
    end

    $display("PASSED");
end

endmodule
module vhdl_delay_assign_test;

logic a, b, c;
int passed = 0;
vhdl_delay_assign dut(a, b, c);

always @(b)
begin
    if($time == 10) begin
        passed = passed + 1;
    end else begin
        $display("FAILED 1");
        $finish();
    end
end

always @(c)
begin
    if($time == 10) begin
        passed = passed + 1;
    end else begin
        $display("FAILED 2");
        $finish();
    end
end

initial begin
    a = 1;
    #11;

    if(passed !== 2) begin
        $display("FAILED 3");
        $finish();
    end

    $display("PASSED");
end

endmodule