data/full_repos/permissive/105269489/src/TEST/All modules v0.0 2 iterations/modules/BRAM.v
None: at end of input
1: b'%Error: Cannot find file containing module: modules\n        ... Looked in:\n             data/full_repos/permissive/105269489/src/TEST/All/modules\n             data/full_repos/permissive/105269489/src/TEST/All/modules.v\n             data/full_repos/permissive/105269489/src/TEST/All/modules.sv\n             modules\n             modules.v\n             modules.sv\n             obj_dir/modules\n             obj_dir/modules.v\n             obj_dir/modules.sv\n%Error: Cannot find file containing module: v0.0\n%Error: Cannot find file containing module: 2\n%Error: Cannot find file containing module: iterations/modules,data/full_repos/permissive/105269489\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/TEST/All\n%Error: Cannot find file containing module: iterations/modules/BRAM.v\n%Error: Exiting due to 6 error(s)\n'
module BRAM( i_wrEnable, 
                  i_CLK, 
             i_writeAdd,
              i_readAdd, 
                 i_data,
                 o_data );
    
    parameter RAM_WIDTH = `RAM_WIDTH;    
    parameter NB_ADDRESS= 10;
    parameter INIT_FILE = "";
    localparam RAM_DEPTH=(2**NB_ADDRESS)-1;
    
    

    input                    i_wrEnable;
    input                i_CLK;
    input [NB_ADDRESS-1:0] i_writeAdd;
    input [NB_ADDRESS-1:0] i_readAdd;
    input [RAM_WIDTH - 1:0] i_data;
    
    output [RAM_WIDTH-1:0] o_data;


    
    reg [RAM_WIDTH-1:0]  BRAM [RAM_DEPTH:0];
    reg [RAM_WIDTH-1:0] dout_reg;
    integer        ram_index;
    
    generate
        if (INIT_FILE != "") begin: use_init_file
            initial
                $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH);
        end else begin: init_bram_to_zero
            integer ram_index;
            initial
                for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
                    BRAM[ram_index] = {RAM_WIDTH{1'b0}};
        end
    endgenerate

    always @(posedge i_CLK) begin
	      dout_reg<=BRAM[i_readAdd];
	      if(i_wrEnable) begin
			      BRAM[i_writeAdd]<=i_data;			
	      end
    end

    assign{o_data}=dout_reg;
    
endmodule
module BRAM( i_wrEnable, 
                  i_CLK, 
             i_writeAdd,
              i_readAdd, 
                 i_data,
                 o_data );

    
    parameter RAM_WIDTH = `RAM_WIDTH;    
    parameter NB_ADDRESS= 10;
    parameter INIT_FILE = "";
    localparam RAM_DEPTH=(2**NB_ADDRESS)-1;
    
    

    input                    i_wrEnable;
    input                i_CLK;
    input [NB_ADDRESS-1:0] i_writeAdd;
    input [NB_ADDRESS-1:0] i_readAdd;
    input [RAM_WIDTH - 1:0] i_data;
    
    output [RAM_WIDTH-1:0] o_data;


    
    reg [RAM_WIDTH-1:0]  BRAM [RAM_DEPTH:0];
    reg [RAM_WIDTH-1:0] dout_reg;
    integer        ram_index;
    
    generate
        if (INIT_FILE != "") begin: use_init_file
            initial
                $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH);
        end else begin: init_bram_to_zero
            integer ram_index;
            initial
                for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
                    BRAM[ram_index] = {RAM_WIDTH{1'b0}};
        end
    endgenerate

    always @(posedge i_CLK) begin
	      dout_reg<=BRAM[i_readAdd];
	      if(i_wrEnable) begin
			      BRAM[i_writeAdd]<=i_data;			
	      end
    end

    assign{o_data}=dout_reg;
    
endmodule