data/full_repos/permissive/143278/ivltests/udp_lfsr.v
 line:55: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:39: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:40: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:42: Unsupported: Ignoring delay on this delayed statement.\n   #5 cp = ~cp;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:46: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:47: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:48: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:50: Unsupported: Ignoring delay on this delayed statement.\n   #5 cp <= ~cp;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:52: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:55: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:61: syntax error, unexpected new, expecting IDENTIFIER or \'=\' or do or final\n   reg [7:0] new;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:67: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Error: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:82: syntax error, unexpected \'@\'\n @(posedge cp) old = {out, sr.s};\n ^\n%Error: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:84: syntax error, unexpected \'@\'\n @(negedge cp) new = {out, sr.s};\n ^\n%Error: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:85: syntax error, unexpected new, expecting TYPE-IDENTIFIER\n if (old != here || new !== next)\n                        ^~~\n%Error: data/full_repos/permissive/143278/ivltests/udp_lfsr.v:90: syntax error, unexpected else\n else\n ^~~~\n%Error: Exiting due to 5 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_lfsr;

   reg   cp;
   reg	 in;
   wire  out;
   reg	 reset;
   lfsr sr(cp, reset, in, out);

   reg	 errors;
   initial errors = 0;
   integer i;

   initial
     begin
        in = 0;
	cp = 0;
	#2 reset = 1;
	#2 reset = 0;
	#1;
	for (i=0; i<512; i=i+1)
	  #5 cp = ~cp;

        in = 0;
	cp = 0;
	#2 reset = 1;
	#2 reset = 0;
	#1;
	for (i=0; i<512; i=i+1)
	  #5 cp <= ~cp;

	#5;
	if (errors == 0)
	  $display("PASSED");
	#10 $finish;
     end

   reg [7:0] here;
   reg [7:0] next;
   reg [7:0] old;
   reg [7:0] new;

   always @(reset)
     if (reset)
       begin
	  here = 1;
	  #1;
	  old = {out, sr.s};
	  if (old === here)
	    begin
	       $display("%b RESET", old);
	    end
	  else
	    begin
	       $display("%b RESET FAILED: expect %b", old, here);
	       errors = 1;
	    end
       end

   always
     begin
	@(posedge cp) old = {out, sr.s};
	next = {here[6:0], ^(here & sr.P) ^ in};
	@(negedge cp) new = {out, sr.s};
	if (old != here || new !== next)
	  begin
	     $display("%b->%b FAILED: expect %b->%b", old, new, here, next);
	     errors = 1;
	  end
	else
	  begin
	     $display("%b->%b", old, new);
	  end
	here = next;
     end

endmodule
module test_lfsr;


   reg   cp;
   reg	 in;
   wire  out;
   reg	 reset;
   lfsr sr(cp, reset, in, out);

   reg	 errors;
   initial errors = 0;
   integer i;

   initial
     begin
        in = 0;
	cp = 0;
	#2 reset = 1;
	#2 reset = 0;
	#1;
	for (i=0; i<512; i=i+1)
	  #5 cp = ~cp;

        in = 0;
	cp = 0;
	#2 reset = 1;
	#2 reset = 0;
	#1;
	for (i=0; i<512; i=i+1)
	  #5 cp <= ~cp;

	#5;
	if (errors == 0)
	  $display("PASSED");
	#10 $finish;
     end

   reg [7:0] here;
   reg [7:0] next;
   reg [7:0] old;
   reg [7:0] new;

   always @(reset)
     if (reset)
       begin
	  here = 1;
	  #1;
	  old = {out, sr.s};
	  if (old === here)
	    begin
	       $display("%b RESET", old);
	    end
	  else
	    begin
	       $display("%b RESET FAILED: expect %b", old, here);
	       errors = 1;
	    end
       end

   always
     begin
	@(posedge cp) old = {out, sr.s};
	next = {here[6:0], ^(here & sr.P) ^ in};
	@(negedge cp) new = {out, sr.s};
	if (old != here || new !== next)
	  begin
	     $display("%b->%b FAILED: expect %b->%b", old, new, here, next);
	     errors = 1;
	  end
	else
	  begin
	     $display("%b->%b", old, new);
	  end
	here = next;
     end

endmodule