data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pwm.v
 line:5: before: "="
data/verilator_xmls/0498a9d4-1af0-42b6-8f30-95ebb731977c.xml
module pwm (
input wire clk, 
input wire [10:0] in,

output reg out = 0,
input wire rst);

	wire [10:0] local_input;
   reg [10:0] clk_count;
	assign local_input = in;
	



	
	always @(posedge clk)
	   clk_count <= clk_count+1'b1;
		
	always @(posedge clk)

		if(clk_count>local_input || rst==1) out<=0;
		else             out<=1;
		




endmodule
module pwm (
input wire clk, 
input wire [10:0] in,

output reg out = 0,
input wire rst);


	wire [10:0] local_input;
   reg [10:0] clk_count;
	assign local_input = in;
	



	
	always @(posedge clk)
	   clk_count <= clk_count+1'b1;
		
	always @(posedge clk)

		if(clk_count>local_input || rst==1) out<=0;
		else             out<=1;
		




endmodule