data/full_repos/permissive/140357212/Tomasulo/som_sub.v
data/verilator_xmls/c0624678-5823-419a-a107-aeac64765990.xml
module Count(clk,RUN,reset,q);
	input clk,RUN,reset;
	output reg [2:0]q;
	initial
		q = 0;
	always@(posedge clk) begin
		if(q == 3 || reset)
			q = 0;
		else if(RUN)	
			q = q + 1;
	end
endmodule
module Count(clk,RUN,reset,q);

	input clk,RUN,reset;
	output reg [2:0]q;
	initial
		q = 0;
	always@(posedge clk) begin
		if(q == 3 || reset)
			q = 0;
		else if(RUN)	
			q = q + 1;
	end
endmodule