data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_adder/adder_4_bit_data_flow_model.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_adder/adder_4_bit_data_flow_model.v:25: Unsupported: Ignoring delay on this delayed statement.\n     #100 A=4\'b0001;B=4\'b0010;cin=0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/117337560/Verilog_HDL_codes_of_basic_logic_circuits/4_bit_adder/adder_4_bit_data_flow_model.v:10: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                                                                           : ... In instance test_adder_4_bit.G\n    assign {cout,Sum}=A+B+cin;\n                         ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder_4_bit(cout,Sum,A,B,cin);
    output [3:0] Sum;
    output cout;
    input [3:0] A;
    input [3:0] B;
    input cin;
    assign {cout,Sum}=A+B+cin;
endmodule
module adder_4_bit(cout,Sum,A,B,cin);

    output [3:0] Sum;
    output cout;
    input [3:0] A;
    input [3:0] B;
    input cin;
    assign {cout,Sum}=A+B+cin;
endmodule