data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:89: Cannot find include file: bus_commands.v\n`include "bus_commands.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/bus_commands.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/bus_commands.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl,data/full_repos/permissive/137416811/bus_commands.v.sv\n             bus_commands.v\n             bus_commands.v.v\n             bus_commands.v.sv\n             obj_dir/bus_commands.v\n             obj_dir/bus_commands.v.v\n             obj_dir/bus_commands.v.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:90: Cannot find include file: pci_constants.v\n`include "pci_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:92: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:284: Define or directive not defined: \'`FF_DELAY\'\n        w_attempt <= #`FF_DELAY 1\'b0;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:288: Define or directive not defined: \'`FF_DELAY\'\n            w_attempt <= #`FF_DELAY 1\'b1;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:291: Define or directive not defined: \'`FF_DELAY\'\n                w_attempt <= #`FF_DELAY 1\'b0;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:311: Define or directive not defined: \'`FF_DELAY\'\n        last_data_from_pciw_fifo <= #`FF_DELAY 1\'b0 ;\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:315: Define or directive not defined: \'`LAST_CTRL_BIT\'\n            (pciw_fifo_control_in[`LAST_CTRL_BIT] || pciw_fifo_almost_empty_in))  \n                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:315: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n            (pciw_fifo_control_in[`LAST_CTRL_BIT] || pciw_fifo_almost_empty_in))  \n                                                ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:316: Define or directive not defined: \'`FF_DELAY\'\n            last_data_from_pciw_fifo <= #`FF_DELAY 1\'b1 ;  \n                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:318: Define or directive not defined: \'`FF_DELAY\'\n            last_data_from_pciw_fifo <= #`FF_DELAY 1\'b0 ;\n                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:325: Define or directive not defined: \'`PCIR_ADDR_LENGTH\'\n    reg [(`PCIR_ADDR_LENGTH - 1):0] max_read_count ;\n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:329: Define or directive not defined: \'`PCIR_DEPTH\'\n            if ( (pci_cache_line_size >= `PCIR_DEPTH) || (~pci_tar_cmd[1] && ~pci_tar_cmd[0]) )\n                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:329: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if ( (pci_cache_line_size >= `PCIR_DEPTH) || (~pci_tar_cmd[1] && ~pci_tar_cmd[0]) )\n                                                    ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:331: Define or directive not defined: \'`PCIR_DEPTH\'\n                max_read_count = `PCIR_DEPTH - 1\'b1;\n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:334: syntax error, unexpected else\n        else\n        ^~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:338: Define or directive not defined: \'`PCIR_ADDR_LENGTH\'\n    reg [(`PCIR_ADDR_LENGTH - 1):0] read_count ;\n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:341: Define or directive not defined: \'`PCIR_ADDR_LENGTH\'\n    wire read_bound_comb = ~|( { read_count[(`PCIR_ADDR_LENGTH - 1):2], read_count[0] } ) ;\n                                             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:347: Define or directive not defined: \'`FF_DELAY\'\n            read_bound <= #`FF_DELAY 1\'b0 ;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:349: Define or directive not defined: \'`FF_DELAY\'\n            read_bound <= #`FF_DELAY 1\'b0 ;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:351: Define or directive not defined: \'`FF_DELAY\'\n            read_bound <= #`FF_DELAY read_bound_comb ;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:351: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            read_bound <= #`FF_DELAY read_bound_comb ;\n                                                     ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:358: Define or directive not defined: \'`FF_DELAY\'\n            read_count <= #`FF_DELAY 0 ;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:358: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            read_count <= #`FF_DELAY 0 ;\n                                       ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:361: Define or directive not defined: \'`FF_DELAY\'\n            read_count <= #`FF_DELAY max_read_count ;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:361: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            read_count <= #`FF_DELAY max_read_count ;\n                                                    ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:364: Define or directive not defined: \'`FF_DELAY\'\n            read_count <= #`FF_DELAY read_count - 1\'b1 ;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:374: Define or directive not defined: \'`BC_MEM_READ\'\n    {`BC_MEM_READ, 1\'b1},\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:374: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    {`BC_MEM_READ, 1\'b1},\n                 ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:375: Define or directive not defined: \'`BC_MEM_READ_LN\'\n    {`BC_MEM_READ_LN, 1\'b1} :\n     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:382: Define or directive not defined: \'`BC_MEM_READ_MUL\'\n    {`BC_MEM_READ_MUL, 1\'b1} :\n     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:415: Define or directive not defined: \'`FF_DELAY\'\n        wb_no_response_cnt <= #`FF_DELAY 4\'h0 ; \n                               ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:417: Define or directive not defined: \'`FF_DELAY\'\n        wb_no_response_cnt <= #`FF_DELAY wb_response_value ;\n                               ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:417: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        wb_no_response_cnt <= #`FF_DELAY wb_response_value ;\n                                                           ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:449: Define or directive not defined: \'`FF_DELAY\'\n        reset_rty_cnt <= #`FF_DELAY 1\'b1 ;  \n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:451: Define or directive not defined: \'`FF_DELAY\'\n        reset_rty_cnt <= #`FF_DELAY wb_ack_i || wb_err_i || last_data_transferred ;  \n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:451: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n        reset_rty_cnt <= #`FF_DELAY wb_ack_i || wb_err_i || last_data_transferred ;  \n                                             ^~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:458: Define or directive not defined: \'`FF_DELAY\'\n        rty_counter <= #`FF_DELAY 8\'h00 ;\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:462: Define or directive not defined: \'`FF_DELAY\'\n            rty_counter <= #`FF_DELAY 8\'h00 ;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:464: Define or directive not defined: \'`FF_DELAY\'\n            rty_counter <= #`FF_DELAY rty_counter_in ;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:464: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            rty_counter <= #`FF_DELAY rty_counter_in ;\n                                                     ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:470: Define or directive not defined: \'`WB_RTY_CNT_MAX\'\n    if(rty_counter == `WB_RTY_CNT_MAX - 1\'b1)  \n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:494: Define or directive not defined: \'`FF_DELAY\'\n        addr_cnt_out <= #`FF_DELAY 32\'h0000_0000 ;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:495: Define or directive not defined: \'`FF_DELAY\'\n        bc_register  <= #`FF_DELAY 4\'h0 ;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:496: Define or directive not defined: \'`FF_DELAY\'\n        addr_into_cnt_reg <= #`FF_DELAY 1\'b0;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:500: Define or directive not defined: \'`FF_DELAY\'\n        addr_cnt_out <= #`FF_DELAY addr_cnt_in ;  \n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:500: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        addr_cnt_out <= #`FF_DELAY addr_cnt_in ;  \n                                               ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:501: Define or directive not defined: \'`FF_DELAY\'\n        addr_into_cnt_reg <= #`FF_DELAY addr_into_cnt;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:501: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        addr_into_cnt_reg <= #`FF_DELAY addr_into_cnt;\n                                                     ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v:503: Define or directive not defined: \'`FF_DELAY\'\n            bc_register  <= #`FF_DELAY pciw_fifo_cbe_in ;\n                             ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module pci_wb_master 
                 (  wb_clock_in,
                    reset_in,
                    
                    pci_tar_read_request,
                    pci_tar_address,
                    pci_tar_cmd,
                    pci_tar_be,
                    pci_tar_burst_ok,
                    pci_cache_line_size,
                    cache_lsize_not_zero,
                    wb_read_done_out,
                    w_attempt,

                    pcir_fifo_wenable_out, 
                    pcir_fifo_data_out,    
                    pcir_fifo_be_out, 
                    pcir_fifo_control_out,  












                    pciw_fifo_renable_out, 
                    pciw_fifo_addr_data_in,                              
                    pciw_fifo_cbe_in, 
                    pciw_fifo_control_in,                                   



                    pciw_fifo_almost_empty_in, 
                    pciw_fifo_empty_in, 
                    pciw_fifo_transaction_ready_in,

                    pci_error_sig_out,
                    pci_error_bc,
                    write_rty_cnt_exp_out,
                    error_source_out,
                    read_rty_cnt_exp_out,

                    wb_cyc_o,
                    wb_stb_o,
                    wb_we_o,
                    wb_cti_o,
                    wb_bte_o,
                    wb_sel_o,
                    wb_adr_o,
                    wb_dat_i,
                    wb_dat_o,
                    wb_ack_i,
                    wb_rty_i,
                    wb_err_i










                );


parameter       S_IDLE          = `WB_FSM_BITS'h0 ; 
parameter       S_WRITE         = `WB_FSM_BITS'h1 ;
parameter       S_WRITE_ERR_RTY = `WB_FSM_BITS'h2 ;
parameter       S_READ          = `WB_FSM_BITS'h3 ;
parameter       S_READ_RTY      = `WB_FSM_BITS'h4 ;
parameter       S_TURN_ARROUND  = `WB_FSM_BITS'h5 ;


input           wb_clock_in ; 
input           reset_in ;


input           pci_tar_read_request ;
input   [31:0]  pci_tar_address ;
input   [3:0]   pci_tar_cmd ;
input   [3:0]   pci_tar_be ;
input           pci_tar_burst_ok ;
input   [7:0]   pci_cache_line_size ;
input           cache_lsize_not_zero ;           
output          wb_read_done_out ;
output          w_attempt ;

reg             wb_read_done_out ;
reg             wb_read_done ;


output          pcir_fifo_wenable_out ;
output  [31:0]  pcir_fifo_data_out ;
output  [3:0]   pcir_fifo_be_out ;
output  [3:0]   pcir_fifo_control_out ;

reg     [31:0]  pcir_fifo_data_out ;
reg             pcir_fifo_wenable_out ;
reg             pcir_fifo_wenable ;
reg     [3:0]   pcir_fifo_control_out ;
reg     [3:0]   pcir_fifo_control ;


output          pciw_fifo_renable_out ;
input   [31:0]  pciw_fifo_addr_data_in ;
input   [3:0]   pciw_fifo_cbe_in ;
input   [3:0]   pciw_fifo_control_in ;
input           pciw_fifo_almost_empty_in ;
input           pciw_fifo_empty_in ;
input           pciw_fifo_transaction_ready_in ;

reg             pciw_fifo_renable_out ;
reg             pciw_fifo_renable ;


output          pci_error_sig_out ;
output  [3:0]   pci_error_bc ;
output          write_rty_cnt_exp_out ;
output          read_rty_cnt_exp_out ;


output          error_source_out ;

reg             pci_error_sig_out ;
reg             write_rty_cnt_exp_out ;
reg             read_rty_cnt_exp_out ;
reg             error_source_out ;


output          wb_cyc_o;
output          wb_stb_o;
output          wb_we_o;
output  [2:0]   wb_cti_o;
output  [1:0]   wb_bte_o;
output  [3:0]   wb_sel_o;
output  [31:0]  wb_adr_o;
input   [31:0]  wb_dat_i;
output  [31:0]  wb_dat_o;
input           wb_ack_i;
input           wb_rty_i;
input           wb_err_i;

reg             wb_cyc_o;
reg             wb_stb_o;
reg             wb_we_o;
reg     [2:0]   wb_cti_o;
reg     [1:0]   wb_bte_o;
reg     [3:0]   wb_sel_o;
reg     [31:0]  wb_dat_o;





reg             last_data_transferred ;


reg     w_attempt;
always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
        w_attempt <= #`FF_DELAY 1'b0;
    else
    begin
        if (pciw_fifo_transaction_ready_in && ~pciw_fifo_empty_in)
            w_attempt <= #`FF_DELAY 1'b1;
        else
            if (last_data_transferred)
                w_attempt <= #`FF_DELAY 1'b0;
    end
end




wire r_attempt = ( pci_tar_read_request && !w_attempt && pciw_fifo_empty_in ) ; 


reg             first_wb_data_access ;

reg             last_data_from_pciw_fifo ;
reg             last_data_from_pciw_fifo_reg ;
reg             last_data_to_pcir_fifo ;


always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
        last_data_from_pciw_fifo <= #`FF_DELAY 1'b0 ;
    else
    begin
        if ((pciw_fifo_renable_out) && 
            (pciw_fifo_control_in[`LAST_CTRL_BIT] || pciw_fifo_almost_empty_in))
            last_data_from_pciw_fifo <= #`FF_DELAY 1'b1 ;
        else
            last_data_from_pciw_fifo <= #`FF_DELAY 1'b0 ;
    end
end

    reg read_count_load;
    reg read_count_enable;
    
    reg [(`PCIR_ADDR_LENGTH - 1):0] max_read_count ;
    always@(pci_cache_line_size or cache_lsize_not_zero or pci_tar_cmd)
    begin 
        if (cache_lsize_not_zero) 
            if ( (pci_cache_line_size >= `PCIR_DEPTH) || (~pci_tar_cmd[1] && ~pci_tar_cmd[0]) )

                max_read_count = `PCIR_DEPTH - 1'b1;
            else
                max_read_count = pci_cache_line_size ;
        else
            max_read_count = 1'b1;
    end

    reg [(`PCIR_ADDR_LENGTH - 1):0] read_count ;


    wire read_bound_comb = ~|( { read_count[(`PCIR_ADDR_LENGTH - 1):2], read_count[0] } ) ;

    reg  read_bound ;
    always@(posedge wb_clock_in or posedge reset_in)
    begin
        if ( reset_in )
            read_bound <= #`FF_DELAY 1'b0 ;
        else if (read_count_load)
            read_bound <= #`FF_DELAY 1'b0 ;
        else if ( read_count_enable )
            read_bound <= #`FF_DELAY read_bound_comb ;
    end


    always@(posedge reset_in or posedge wb_clock_in)
    begin
        if (reset_in)
            read_count <= #`FF_DELAY 0 ;
        else
        if (read_count_load)
            read_count <= #`FF_DELAY max_read_count ;
        else
        if (read_count_enable)
            read_count <= #`FF_DELAY read_count - 1'b1 ;
    end



always@(pci_tar_cmd or pci_tar_burst_ok or read_bound)
begin


    case ({pci_tar_cmd, pci_tar_burst_ok})
    {`BC_MEM_READ, 1'b1},
    {`BC_MEM_READ_LN, 1'b1} :
    begin
        if (read_bound)
            last_data_to_pcir_fifo = 1'b1 ;
        else
            last_data_to_pcir_fifo = 1'b0 ;
    end
    {`BC_MEM_READ_MUL, 1'b1} :
    begin
        if (read_bound)
            last_data_to_pcir_fifo = 1'b1 ;
        else
            last_data_to_pcir_fifo = 1'b0 ;
    end
    default :





    begin
        last_data_to_pcir_fifo = 1'b1 ;
    end
    endcase
end

reg             wait_for_wb_response ;

`ifdef PCI_WBM_NO_RESPONSE_CNT_DISABLE
wire set_retry = 1'b0 ;

`else
reg     [3:0]   wb_no_response_cnt ;
reg     [3:0]   wb_response_value ;
reg             set_retry ;


always@(posedge reset_in or posedge wb_clock_in)
begin
    if (reset_in)
        wb_no_response_cnt <= #`FF_DELAY 4'h0 ; 
    else
        wb_no_response_cnt <= #`FF_DELAY wb_response_value ;
end

always@(wait_for_wb_response or wb_no_response_cnt)
begin
    if (wb_no_response_cnt == 4'h8)
    begin
        wb_response_value = 4'h0 ;
        set_retry = 1'b1 ;
    end
    else
    begin
        if (wait_for_wb_response)
            wb_response_value = wb_no_response_cnt + 1'h1 ;
        else
            wb_response_value = 4'h0 ;
        set_retry = 1'b0 ;
    end
end
`endif

wire    retry = wb_rty_i || set_retry ;
reg     [7:0]   rty_counter ;
reg     [7:0]   rty_counter_in ;
reg             rty_counter_almost_max_value ;
reg             reset_rty_cnt ;



always@(posedge reset_in or posedge wb_clock_in)
begin
    if (reset_in)
        reset_rty_cnt <= #`FF_DELAY 1'b1 ;
    else
        reset_rty_cnt <= #`FF_DELAY wb_ack_i || wb_err_i || last_data_transferred ;
end


always@(posedge reset_in or posedge wb_clock_in)
begin
    if (reset_in)
        rty_counter <= #`FF_DELAY 8'h00 ;
    else
    begin
        if (reset_rty_cnt)
            rty_counter <= #`FF_DELAY 8'h00 ;
        else if (retry)
            rty_counter <= #`FF_DELAY rty_counter_in ;
    end
end

always@(rty_counter)
begin
    if(rty_counter == `WB_RTY_CNT_MAX - 1'b1)
    begin
        rty_counter_in = rty_counter ;
        rty_counter_almost_max_value = 1'b1 ;
    end
    else
    begin
        rty_counter_in = rty_counter + 1'b1 ;
        rty_counter_almost_max_value = 1'b0 ;
    end
end     

reg     [31:0]  addr_cnt_out ;
reg     [31:0]  addr_cnt_in ;
reg             addr_into_cnt ;
reg             addr_into_cnt_reg ; 
reg             addr_count ;
reg     [3:0]   bc_register ;


always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
    begin
        addr_cnt_out <= #`FF_DELAY 32'h0000_0000 ;
        bc_register  <= #`FF_DELAY 4'h0 ;
        addr_into_cnt_reg <= #`FF_DELAY 1'b0;
    end
    else
    begin
        addr_cnt_out <= #`FF_DELAY addr_cnt_in ;
        addr_into_cnt_reg <= #`FF_DELAY addr_into_cnt;
        if (addr_into_cnt)
            bc_register  <= #`FF_DELAY pciw_fifo_cbe_in ;
    end
end


wire    io_memory_bus_command = !pci_tar_cmd[3] && !pci_tar_cmd[2] ;


always@(addr_into_cnt or r_attempt or addr_count or pciw_fifo_addr_data_in or pci_tar_address or addr_cnt_out or
        io_memory_bus_command)
begin
    if (addr_into_cnt)
    begin
        if (r_attempt)
        begin
            addr_cnt_in = {pci_tar_address[31:2], pci_tar_address[1] && io_memory_bus_command, 
                                                  pci_tar_address[0] && io_memory_bus_command} ; 
        end
        else
        begin
            addr_cnt_in = pciw_fifo_addr_data_in[31:0] ; 
        end
    end
    else
    if (addr_count)
    begin
        addr_cnt_in = addr_cnt_out + 3'h4 ;
    end
    else
    begin
        addr_cnt_in = addr_cnt_out ;
    end
end

reg retried ;
reg retried_d ;
reg retried_write;
reg rty_i_delayed;

reg     first_data_is_burst ;
reg     first_data_is_burst_reg ;
wire    burst_transfer ;
reg     burst_chopped;
reg     burst_chopped_delayed;



always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
    begin
        retried <= #`FF_DELAY 1'b0 ;
        retried_write <= #`FF_DELAY 1'b0 ;
        rty_i_delayed <= #`FF_DELAY 1'B0 ;
    end
    else
    begin
        retried <= #`FF_DELAY retried_d ;
        retried_write <= #`FF_DELAY retried ;
        rty_i_delayed <= #`FF_DELAY wb_rty_i ;
    end
end


always@(addr_into_cnt or r_attempt or pci_tar_burst_ok or max_read_count or 
        pciw_fifo_control_in or pciw_fifo_empty_in)
begin
    if (addr_into_cnt)
    begin
        if (r_attempt)
        begin


            if  (pci_tar_burst_ok && (max_read_count != 8'h1))
                first_data_is_burst = 1'b1 ; 
            else
                first_data_is_burst = 1'b0 ;
        end
        else
        begin
            first_data_is_burst = 1'b0 ;
        end
    end
    else
        first_data_is_burst = pciw_fifo_control_in[`BURST_BIT] && ~pciw_fifo_empty_in && 
                              ~pciw_fifo_control_in[`LAST_CTRL_BIT];
end


always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in) 
    begin
        burst_chopped         <= #`FF_DELAY 1'b0;
        burst_chopped_delayed <= #`FF_DELAY 1'b0;
        first_data_is_burst_reg <= #`FF_DELAY 1'b0 ;
    end
    else
    begin
        if (pciw_fifo_transaction_ready_in)
        begin
            if (pciw_fifo_control_in[`DATA_ERROR_CTRL_BIT])
                burst_chopped     <= #`FF_DELAY 1'b1;
            else if (wb_ack_i || wb_err_i || wb_rty_i)
                burst_chopped     <= #`FF_DELAY 1'b0;
        end
        else
            burst_chopped         <= #`FF_DELAY 1'b0;
        burst_chopped_delayed <= #`FF_DELAY burst_chopped;
        if (last_data_transferred || first_data_is_burst)
            first_data_is_burst_reg <= #`FF_DELAY ~last_data_transferred ;
    end
end
assign  burst_transfer = first_data_is_burst || first_data_is_burst_reg ;

reg [(`WB_FSM_BITS - 1):0]  c_state ;
reg [(`WB_FSM_BITS - 1):0]  n_state ;






always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
    begin
        c_state  <= #`FF_DELAY  S_IDLE;
        wb_cyc_o <= #`FF_DELAY  1'b0;
        wb_stb_o <= #`FF_DELAY  1'b0;
        wb_we_o  <= #`FF_DELAY  1'b0;
        wb_cti_o <= #`FF_DELAY  3'h2;
        wb_bte_o <= #`FF_DELAY  2'h0;
        wb_sel_o <= #`FF_DELAY  4'h0;
        wb_dat_o <= #`FF_DELAY 32'h0;
        pcir_fifo_data_out <= #`FF_DELAY 32'h0;
        pcir_fifo_control_out <= #`FF_DELAY 4'h0;
        pcir_fifo_wenable_out <= #`FF_DELAY 1'b0;
    end
    else
    begin
        c_state  <= #`FF_DELAY  n_state;
        wb_bte_o <= #`FF_DELAY  2'h0;
        case (n_state)
        S_WRITE:
        begin
            wb_cyc_o <= #`FF_DELAY  ~addr_into_cnt;
            wb_stb_o <= #`FF_DELAY  ~addr_into_cnt;
            wb_we_o  <= #`FF_DELAY  ~addr_into_cnt;


            if ((wb_stb_o && wb_ack_i) || addr_into_cnt_reg || (~wb_cyc_o && (retried || burst_chopped_delayed)))
            begin
                if (burst_transfer && ~pciw_fifo_control_in[`DATA_ERROR_CTRL_BIT] &&
                   ~(pciw_fifo_renable_out && (pciw_fifo_control_in[`LAST_CTRL_BIT] || pciw_fifo_almost_empty_in)))
                    wb_cti_o <= #`FF_DELAY  3'h2;
                else
                    wb_cti_o <= #`FF_DELAY  3'h7;
            end
            if ((pciw_fifo_renable_out && ~addr_into_cnt) || addr_into_cnt_reg)
            begin
                wb_sel_o <= #`FF_DELAY  ~pciw_fifo_cbe_in;
                wb_dat_o <= #`FF_DELAY  pciw_fifo_addr_data_in;
            end
        end
        S_WRITE_ERR_RTY:
        begin
            wb_cyc_o <= #`FF_DELAY  1'b0;
            wb_stb_o <= #`FF_DELAY  1'b0;
            wb_we_o  <= #`FF_DELAY  1'b0;
            wb_cti_o <= #`FF_DELAY  3'h2;



        end
        S_READ:
        begin
            wb_cyc_o <= #`FF_DELAY  ~addr_into_cnt;
            wb_stb_o <= #`FF_DELAY  ~addr_into_cnt;
            wb_we_o  <= #`FF_DELAY  1'b0;
            if ((wb_stb_o && wb_ack_i) || addr_into_cnt_reg || (~wb_cyc_o && retried))
            begin
                if (burst_transfer && ~read_bound_comb)
                    wb_cti_o <= #`FF_DELAY  3'h2;
                else
                    wb_cti_o <= #`FF_DELAY  3'h7;
            end
            if (burst_transfer)
                wb_sel_o <= #`FF_DELAY  4'hF;
            else
                wb_sel_o <= #`FF_DELAY  ~pci_tar_be;


        end
        S_READ_RTY:
        begin
            wb_cyc_o <= #`FF_DELAY  1'b0;
            wb_stb_o <= #`FF_DELAY  1'b0;
            wb_we_o  <= #`FF_DELAY  1'b0;
            wb_cti_o <= #`FF_DELAY  3'h2;



        end
        S_TURN_ARROUND:
        begin
            wb_cyc_o <= #`FF_DELAY  1'b0;
            wb_stb_o <= #`FF_DELAY  1'b0;
            wb_we_o  <= #`FF_DELAY  1'b0;
            wb_cti_o <= #`FF_DELAY  3'h2;



        end
        default:
        begin
            wb_cyc_o <= #`FF_DELAY  1'b0;
            wb_stb_o <= #`FF_DELAY  1'b0;
            wb_we_o  <= #`FF_DELAY  1'b0;
            wb_cti_o <= #`FF_DELAY  3'h2;



        end
        endcase
        pcir_fifo_data_out <= #`FF_DELAY  wb_dat_i;
        pcir_fifo_control_out <= #`FF_DELAY pcir_fifo_control ;
        pcir_fifo_wenable_out <= #`FF_DELAY pcir_fifo_wenable ;
    end
end

assign  wb_adr_o = addr_cnt_out ;


always@(c_state or
        wb_ack_i or 
        wb_rty_i or 
        wb_err_i or 
        w_attempt or
        r_attempt or
        retried or 
        burst_chopped or 
        burst_chopped_delayed or 
        rty_i_delayed or
        pci_tar_read_request or
        rty_counter_almost_max_value or 
        set_retry or 
        last_data_to_pcir_fifo or 
        first_wb_data_access or
        pciw_fifo_control_in or 
        pciw_fifo_empty_in or 
        burst_transfer or 
        last_data_from_pciw_fifo_reg
        )
begin
    case (c_state)
    S_IDLE:
        begin

            pcir_fifo_wenable = 1'b0 ;
            pcir_fifo_control = 4'h0 ;
            addr_count = 1'b0 ;
            read_count_enable = 1'b0 ;
            pci_error_sig_out = 1'b0 ;
            error_source_out = 1'b0 ;
            retried_d = 1'b0 ;
            last_data_transferred = 1'b0 ;
            wb_read_done = 1'b0 ;
            wait_for_wb_response = 1'b0 ;
            write_rty_cnt_exp_out = 1'b0 ;
            pci_error_sig_out = 1'b0 ;
            read_rty_cnt_exp_out = 1'b0 ;
            case ({w_attempt, r_attempt, retried})
            3'b101 :
            begin
                pciw_fifo_renable = 1'b0 ;
                addr_into_cnt = 1'b0 ;
                read_count_load = 1'b0 ;
                n_state = S_WRITE ;
            end
            3'b100 :
            begin
                if (burst_chopped_delayed)
                begin
                  addr_into_cnt = 1'b0 ;
                  pciw_fifo_renable = 1'b1 ;
                end
                else
                begin
                  if (pciw_fifo_control_in[`ADDR_CTRL_BIT])
                      addr_into_cnt = 1'b1 ;
                  else
                      addr_into_cnt = 1'b0 ;
                  pciw_fifo_renable = 1'b1 ;
                end
                read_count_load = 1'b0 ;
                n_state = S_WRITE ;
            end
            3'b011 :
            begin
                addr_into_cnt = 1'b0 ;
                read_count_load = 1'b0 ;
                pciw_fifo_renable = 1'b0 ;
                n_state = S_READ ;
            end
            3'b010 :
            begin
                addr_into_cnt = 1'b1 ;
                read_count_load = 1'b1 ;
                pciw_fifo_renable = 1'b0 ;
                n_state = S_READ ;
            end
            default :
            begin
                pciw_fifo_renable = 1'b0 ;
                addr_into_cnt = 1'b0 ;
                read_count_load = 1'b0 ;
                n_state = S_IDLE ;
            end
            endcase
        end
    S_WRITE:
        begin

            pcir_fifo_wenable = 1'b0 ;
            pcir_fifo_control = 4'h0 ;
            addr_into_cnt = 1'b0 ;
            read_count_load = 1'b0 ;
            read_count_enable = 1'b0 ;
            wb_read_done = 1'b0 ;
            read_rty_cnt_exp_out = 1'b0 ;
            case ({wb_ack_i, wb_err_i, wb_rty_i})
            3'b100 :
            begin
                addr_count = 1'b1 ;
                retried_d = 1'b0 ;
                pci_error_sig_out = 1'b0 ;
                error_source_out = 1'b0 ;
                write_rty_cnt_exp_out = 1'b0 ;
                wait_for_wb_response = 1'b0 ;

                if (last_data_from_pciw_fifo_reg) 
                begin                   
                    n_state = S_TURN_ARROUND;
                    if (~pciw_fifo_empty_in)
                        pciw_fifo_renable = 1'b0 ;
                    else
                        pciw_fifo_renable = 1'b0 ;
                    last_data_transferred = 1'b1 ;
                end

                else if (burst_transfer && burst_chopped) 
                begin                   
                    n_state = S_IDLE ;
                    pciw_fifo_renable = 1'b0 ;
                    last_data_transferred = 1'b0 ;
                end
                else
                begin
                    n_state = S_WRITE ;
                    pciw_fifo_renable = 1'b1 ;
                    last_data_transferred = 1'b0 ;
                end
            end
            3'b010 :
            begin
                if (~pciw_fifo_empty_in)
                    pciw_fifo_renable = 1'b1 ;
                else
                    pciw_fifo_renable = 1'b0 ;
                addr_count = 1'b0 ;
                retried_d = 1'b0 ;
                last_data_transferred = 1'b1 ;
                pci_error_sig_out = 1'b1 ;
                error_source_out = 1'b0 ;
                write_rty_cnt_exp_out = 1'b0 ;
                wait_for_wb_response = 1'b0 ;
                if (last_data_from_pciw_fifo_reg)
                    n_state = S_TURN_ARROUND ;
                else
                    n_state = S_WRITE_ERR_RTY ;
            end
            3'b001 :
            begin
                addr_count = 1'b0 ;
                last_data_transferred = 1'b0 ;
                retried_d = 1'b1 ;
                wait_for_wb_response = 1'b0 ;
                if(rty_counter_almost_max_value)
                begin
                    if (last_data_from_pciw_fifo_reg)
                        pciw_fifo_renable = 1'b0 ;
                    else
                        pciw_fifo_renable = 1'b1 ;
                    n_state = S_WRITE_ERR_RTY ;
                    write_rty_cnt_exp_out = 1'b1 ;
                    pci_error_sig_out = 1'b1 ;
                    error_source_out = 1'b1 ;
                end
                else
                begin
                    pciw_fifo_renable = 1'b0 ;
                    n_state = S_IDLE ;
                    write_rty_cnt_exp_out = 1'b0 ;
                    pci_error_sig_out = 1'b0 ;
                    error_source_out = 1'b0 ;
                end
            end
            default :
            begin
                addr_count = 1'b0 ;
                last_data_transferred = 1'b0 ;
                wait_for_wb_response = 1'b1 ;
                error_source_out = 1'b0 ;
                if((rty_counter_almost_max_value)&&(set_retry))
                begin
                    retried_d = 1'b1 ;
                    if (last_data_from_pciw_fifo_reg)
                        pciw_fifo_renable = 1'b0 ;
                    else
                        pciw_fifo_renable = 1'b1 ;
                    n_state = S_WRITE_ERR_RTY ;
                    write_rty_cnt_exp_out = 1'b1 ;
                    pci_error_sig_out = 1'b1 ;
                end
                else
                begin
               	    pciw_fifo_renable = 1'b0 ;
                    retried_d = 1'b0 ;
                    n_state = S_WRITE ;
                    write_rty_cnt_exp_out = 1'b0 ;
                    pci_error_sig_out = 1'b0 ;
                end
            end
            endcase
        end
    S_WRITE_ERR_RTY:
        begin
            pciw_fifo_renable = !last_data_from_pciw_fifo_reg ;
            last_data_transferred = 1'b1 ;

            pcir_fifo_wenable = 1'b0 ;
            pcir_fifo_control = 4'h0 ;
            addr_into_cnt = 1'b0 ;
            read_count_load = 1'b0 ;
            read_count_enable = 1'b0 ;
            addr_count = 1'b0 ;
            pci_error_sig_out = 1'b0 ;
            error_source_out = 1'b0 ;
            retried_d = 1'b0 ;
            wb_read_done = 1'b0 ;
            write_rty_cnt_exp_out = 1'b0 ;
            read_rty_cnt_exp_out = 1'b0 ;
            wait_for_wb_response = 1'b0 ;

            if (last_data_from_pciw_fifo_reg)
                n_state = S_IDLE ;
            else
                n_state = S_WRITE_ERR_RTY ;
        end
    S_READ:
        begin

            pciw_fifo_renable = 1'b0 ;
            addr_into_cnt = 1'b0 ;
            read_count_load = 1'b0 ;
            pci_error_sig_out = 1'b0 ;
            error_source_out = 1'b0 ;
            write_rty_cnt_exp_out = 1'b0 ;
            case ({wb_ack_i, wb_err_i, wb_rty_i})
            3'b100 :
            begin
                pcir_fifo_wenable = 1'b1 ;
                addr_count = 1'b1 ;
                read_count_enable = 1'b1 ;
                retried_d = 1'b0 ;
                read_rty_cnt_exp_out = 1'b0 ;
                wait_for_wb_response = 1'b0 ;

                if (last_data_to_pcir_fifo)
                begin
                    pcir_fifo_control[`LAST_CTRL_BIT]       = 1'b1 ;
                    pcir_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b0 ;
                    pcir_fifo_control[`UNUSED_CTRL_BIT]     = 1'b0 ;
                    pcir_fifo_control[`ADDR_CTRL_BIT]       = 1'b0 ;
                    last_data_transferred = 1'b1 ;
                    wb_read_done = 1'b1 ;
                    n_state = S_TURN_ARROUND ;
                end
                else
                begin
                    pcir_fifo_control = 4'h0 ;
                    last_data_transferred = 1'b0 ;
                    wb_read_done = 1'b0 ;
                    n_state = S_READ ;
                end
            end
            3'b010 :
            begin
                pcir_fifo_wenable = 1'b1 ;
                addr_count = 1'b0 ;
                pcir_fifo_control[`LAST_CTRL_BIT]       = 1'b0 ;
                pcir_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b1 ;
                pcir_fifo_control[`UNUSED_CTRL_BIT]     = 1'b0 ;
                pcir_fifo_control[`ADDR_CTRL_BIT]       = 1'b0 ;
                last_data_transferred = 1'b1 ;
                wb_read_done = 1'b1 ;
                read_count_enable = 1'b0 ;
                n_state = S_TURN_ARROUND ;
                retried_d = 1'b0 ;
                wait_for_wb_response = 1'b0 ;
                read_rty_cnt_exp_out = 1'b0 ;
            end
            3'b001 :
            begin
                pcir_fifo_wenable = 1'b0 ;
                pcir_fifo_control = 4'h0 ;
                addr_count = 1'b0 ;
                read_count_enable = 1'b0 ;
                wait_for_wb_response = 1'b0 ;
                case ({first_wb_data_access, rty_counter_almost_max_value})
                2'b10 :
                begin
                    n_state = S_IDLE ;
                    read_rty_cnt_exp_out = 1'b0 ;
                    last_data_transferred = 1'b0 ;
                    wb_read_done = 1'b0 ;
                    retried_d = 1'b1 ;
                end
                2'b11 :
                begin
                    n_state = S_READ_RTY ;
                    read_rty_cnt_exp_out = 1'b1 ;
                    last_data_transferred = 1'b0 ;
                    wb_read_done = 1'b0 ;
                    retried_d = 1'b1 ;
                end
                default :
                begin
                    n_state = S_TURN_ARROUND ;
                    read_rty_cnt_exp_out = 1'b0 ;
                    last_data_transferred = 1'b1 ;
                    wb_read_done = 1'b1 ;
                    retried_d = 1'b0 ;
                end
                endcase
            end
            default :
            begin
                addr_count = 1'b0 ;
                read_count_enable = 1'b0 ;
                read_rty_cnt_exp_out = 1'b0 ;
                wait_for_wb_response = 1'b1 ;
                if((rty_counter_almost_max_value)&&(set_retry))
                begin
                    retried_d = 1'b1 ;
                    n_state = S_TURN_ARROUND ;
                    pcir_fifo_wenable = 1'b1 ;
                    pcir_fifo_control[`LAST_CTRL_BIT]       = 1'b0 ;
                    pcir_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b1 ;
                    pcir_fifo_control[`UNUSED_CTRL_BIT]     = 1'b0 ;
                    pcir_fifo_control[`ADDR_CTRL_BIT]       = 1'b0 ;
                    last_data_transferred = 1'b1 ;
                    wb_read_done = 1'b1 ;
                end
                else
                begin
                    retried_d = 1'b0 ;
                    n_state = S_READ ;
                    pcir_fifo_wenable = 1'b0 ;
                    pcir_fifo_control = 4'h0 ;
                    last_data_transferred = 1'b0 ;
                    wb_read_done = 1'b0 ;
                end
            end
            endcase
        end
    S_READ_RTY:
        begin

            pciw_fifo_renable = 1'b0 ;
            pcir_fifo_wenable = 1'b0 ;
            pcir_fifo_control = 4'h0 ;
            addr_into_cnt = 1'b0 ;
            read_count_load = 1'b0 ;
            read_count_enable = 1'b0 ;
            addr_count = 1'b0 ;
            pci_error_sig_out = 1'b0 ;
            error_source_out = 1'b0 ;
            retried_d = 1'b0 ;
            wb_read_done = 1'b0 ;
            write_rty_cnt_exp_out = 1'b0 ;
            read_rty_cnt_exp_out = 1'b0 ;
            wait_for_wb_response = 1'b0 ;

            if (pci_tar_read_request)
            begin
                n_state = S_READ_RTY ;
                last_data_transferred = 1'b0 ;
            end
            else
            begin
                n_state = S_IDLE ;
                last_data_transferred = 1'b1 ;
            end
        end    

    default:
        begin

            pciw_fifo_renable = 1'b0 ;
            pcir_fifo_wenable = 1'b0 ;
            pcir_fifo_control = 4'h0 ;
            addr_into_cnt = 1'b0 ;
            read_count_load = 1'b0 ;
            read_count_enable = 1'b0 ;
            addr_count = 1'b0 ;
            pci_error_sig_out = 1'b0 ;
            error_source_out = 1'b0 ;
            retried_d = 1'b0 ;
            last_data_transferred = 1'b1 ;
            wb_read_done = 1'b0 ;
            write_rty_cnt_exp_out = 1'b0 ;
            read_rty_cnt_exp_out = 1'b0 ;
            wait_for_wb_response = 1'b0 ;
            n_state = S_IDLE ;
        end     
    endcase
end


wire ack_rty_response = wb_ack_i || wb_rty_i ;


always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
        first_wb_data_access = 1'b1 ;
    else
    begin
        if (~wb_cyc_o)
            first_wb_data_access = 1'b1 ;
        else if (ack_rty_response)
            first_wb_data_access = 1'b0 ;
    end
end


assign  pcir_fifo_be_out = 4'hf ;


assign  pci_error_bc = bc_register ;


always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
        wb_read_done_out <= #`FF_DELAY 1'b0 ;
    else
        wb_read_done_out <= #`FF_DELAY wb_read_done ;
end

always@(pciw_fifo_renable or addr_into_cnt_reg or pciw_fifo_control_in or pciw_fifo_empty_in)
begin
    pciw_fifo_renable_out           = pciw_fifo_renable || addr_into_cnt_reg ;
    last_data_from_pciw_fifo_reg    = pciw_fifo_control_in[`ADDR_CTRL_BIT] || pciw_fifo_empty_in ;
end


endmodule
module pci_wb_master 
                 (  wb_clock_in,
                    reset_in,
                    
                    pci_tar_read_request,
                    pci_tar_address,
                    pci_tar_cmd,
                    pci_tar_be,
                    pci_tar_burst_ok,
                    pci_cache_line_size,
                    cache_lsize_not_zero,
                    wb_read_done_out,
                    w_attempt,

                    pcir_fifo_wenable_out, 
                    pcir_fifo_data_out,    
                    pcir_fifo_be_out, 
                    pcir_fifo_control_out,  












                    pciw_fifo_renable_out, 
                    pciw_fifo_addr_data_in,                              
                    pciw_fifo_cbe_in, 
                    pciw_fifo_control_in,                                   



                    pciw_fifo_almost_empty_in, 
                    pciw_fifo_empty_in, 
                    pciw_fifo_transaction_ready_in,

                    pci_error_sig_out,
                    pci_error_bc,
                    write_rty_cnt_exp_out,
                    error_source_out,
                    read_rty_cnt_exp_out,

                    wb_cyc_o,
                    wb_stb_o,
                    wb_we_o,
                    wb_cti_o,
                    wb_bte_o,
                    wb_sel_o,
                    wb_adr_o,
                    wb_dat_i,
                    wb_dat_o,
                    wb_ack_i,
                    wb_rty_i,
                    wb_err_i










                );



parameter       S_IDLE          = `WB_FSM_BITS'h0 ; 
parameter       S_WRITE         = `WB_FSM_BITS'h1 ;
parameter       S_WRITE_ERR_RTY = `WB_FSM_BITS'h2 ;
parameter       S_READ          = `WB_FSM_BITS'h3 ;
parameter       S_READ_RTY      = `WB_FSM_BITS'h4 ;
parameter       S_TURN_ARROUND  = `WB_FSM_BITS'h5 ;


input           wb_clock_in ; 
input           reset_in ;


input           pci_tar_read_request ;
input   [31:0]  pci_tar_address ;
input   [3:0]   pci_tar_cmd ;
input   [3:0]   pci_tar_be ;
input           pci_tar_burst_ok ;
input   [7:0]   pci_cache_line_size ;
input           cache_lsize_not_zero ;           
output          wb_read_done_out ;
output          w_attempt ;

reg             wb_read_done_out ;
reg             wb_read_done ;


output          pcir_fifo_wenable_out ;
output  [31:0]  pcir_fifo_data_out ;
output  [3:0]   pcir_fifo_be_out ;
output  [3:0]   pcir_fifo_control_out ;

reg     [31:0]  pcir_fifo_data_out ;
reg             pcir_fifo_wenable_out ;
reg             pcir_fifo_wenable ;
reg     [3:0]   pcir_fifo_control_out ;
reg     [3:0]   pcir_fifo_control ;


output          pciw_fifo_renable_out ;
input   [31:0]  pciw_fifo_addr_data_in ;
input   [3:0]   pciw_fifo_cbe_in ;
input   [3:0]   pciw_fifo_control_in ;
input           pciw_fifo_almost_empty_in ;
input           pciw_fifo_empty_in ;
input           pciw_fifo_transaction_ready_in ;

reg             pciw_fifo_renable_out ;
reg             pciw_fifo_renable ;


output          pci_error_sig_out ;
output  [3:0]   pci_error_bc ;
output          write_rty_cnt_exp_out ;
output          read_rty_cnt_exp_out ;


output          error_source_out ;

reg             pci_error_sig_out ;
reg             write_rty_cnt_exp_out ;
reg             read_rty_cnt_exp_out ;
reg             error_source_out ;


output          wb_cyc_o;
output          wb_stb_o;
output          wb_we_o;
output  [2:0]   wb_cti_o;
output  [1:0]   wb_bte_o;
output  [3:0]   wb_sel_o;
output  [31:0]  wb_adr_o;
input   [31:0]  wb_dat_i;
output  [31:0]  wb_dat_o;
input           wb_ack_i;
input           wb_rty_i;
input           wb_err_i;

reg             wb_cyc_o;
reg             wb_stb_o;
reg             wb_we_o;
reg     [2:0]   wb_cti_o;
reg     [1:0]   wb_bte_o;
reg     [3:0]   wb_sel_o;
reg     [31:0]  wb_dat_o;





reg             last_data_transferred ;


reg     w_attempt;
always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
        w_attempt <= #`FF_DELAY 1'b0;
    else
    begin
        if (pciw_fifo_transaction_ready_in && ~pciw_fifo_empty_in)
            w_attempt <= #`FF_DELAY 1'b1;
        else
            if (last_data_transferred)
                w_attempt <= #`FF_DELAY 1'b0;
    end
end




wire r_attempt = ( pci_tar_read_request && !w_attempt && pciw_fifo_empty_in ) ; 


reg             first_wb_data_access ;

reg             last_data_from_pciw_fifo ;
reg             last_data_from_pciw_fifo_reg ;
reg             last_data_to_pcir_fifo ;


always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
        last_data_from_pciw_fifo <= #`FF_DELAY 1'b0 ;
    else
    begin
        if ((pciw_fifo_renable_out) && 
            (pciw_fifo_control_in[`LAST_CTRL_BIT] || pciw_fifo_almost_empty_in))
            last_data_from_pciw_fifo <= #`FF_DELAY 1'b1 ;
        else
            last_data_from_pciw_fifo <= #`FF_DELAY 1'b0 ;
    end
end

    reg read_count_load;
    reg read_count_enable;
    
    reg [(`PCIR_ADDR_LENGTH - 1):0] max_read_count ;
    always@(pci_cache_line_size or cache_lsize_not_zero or pci_tar_cmd)
    begin 
        if (cache_lsize_not_zero) 
            if ( (pci_cache_line_size >= `PCIR_DEPTH) || (~pci_tar_cmd[1] && ~pci_tar_cmd[0]) )

                max_read_count = `PCIR_DEPTH - 1'b1;
            else
                max_read_count = pci_cache_line_size ;
        else
            max_read_count = 1'b1;
    end

    reg [(`PCIR_ADDR_LENGTH - 1):0] read_count ;


    wire read_bound_comb = ~|( { read_count[(`PCIR_ADDR_LENGTH - 1):2], read_count[0] } ) ;

    reg  read_bound ;
    always@(posedge wb_clock_in or posedge reset_in)
    begin
        if ( reset_in )
            read_bound <= #`FF_DELAY 1'b0 ;
        else if (read_count_load)
            read_bound <= #`FF_DELAY 1'b0 ;
        else if ( read_count_enable )
            read_bound <= #`FF_DELAY read_bound_comb ;
    end


    always@(posedge reset_in or posedge wb_clock_in)
    begin
        if (reset_in)
            read_count <= #`FF_DELAY 0 ;
        else
        if (read_count_load)
            read_count <= #`FF_DELAY max_read_count ;
        else
        if (read_count_enable)
            read_count <= #`FF_DELAY read_count - 1'b1 ;
    end



always@(pci_tar_cmd or pci_tar_burst_ok or read_bound)
begin


    case ({pci_tar_cmd, pci_tar_burst_ok})
    {`BC_MEM_READ, 1'b1},
    {`BC_MEM_READ_LN, 1'b1} :
    begin
        if (read_bound)
            last_data_to_pcir_fifo = 1'b1 ;
        else
            last_data_to_pcir_fifo = 1'b0 ;
    end
    {`BC_MEM_READ_MUL, 1'b1} :
    begin
        if (read_bound)
            last_data_to_pcir_fifo = 1'b1 ;
        else
            last_data_to_pcir_fifo = 1'b0 ;
    end
    default :





    begin
        last_data_to_pcir_fifo = 1'b1 ;
    end
    endcase
end

reg             wait_for_wb_response ;

`ifdef PCI_WBM_NO_RESPONSE_CNT_DISABLE
wire set_retry = 1'b0 ;

`else
reg     [3:0]   wb_no_response_cnt ;
reg     [3:0]   wb_response_value ;
reg             set_retry ;


always@(posedge reset_in or posedge wb_clock_in)
begin
    if (reset_in)
        wb_no_response_cnt <= #`FF_DELAY 4'h0 ; 
    else
        wb_no_response_cnt <= #`FF_DELAY wb_response_value ;
end

always@(wait_for_wb_response or wb_no_response_cnt)
begin
    if (wb_no_response_cnt == 4'h8)
    begin
        wb_response_value = 4'h0 ;
        set_retry = 1'b1 ;
    end
    else
    begin
        if (wait_for_wb_response)
            wb_response_value = wb_no_response_cnt + 1'h1 ;
        else
            wb_response_value = 4'h0 ;
        set_retry = 1'b0 ;
    end
end
`endif

wire    retry = wb_rty_i || set_retry ;
reg     [7:0]   rty_counter ;
reg     [7:0]   rty_counter_in ;
reg             rty_counter_almost_max_value ;
reg             reset_rty_cnt ;



always@(posedge reset_in or posedge wb_clock_in)
begin
    if (reset_in)
        reset_rty_cnt <= #`FF_DELAY 1'b1 ;
    else
        reset_rty_cnt <= #`FF_DELAY wb_ack_i || wb_err_i || last_data_transferred ;
end


always@(posedge reset_in or posedge wb_clock_in)
begin
    if (reset_in)
        rty_counter <= #`FF_DELAY 8'h00 ;
    else
    begin
        if (reset_rty_cnt)
            rty_counter <= #`FF_DELAY 8'h00 ;
        else if (retry)
            rty_counter <= #`FF_DELAY rty_counter_in ;
    end
end

always@(rty_counter)
begin
    if(rty_counter == `WB_RTY_CNT_MAX - 1'b1)
    begin
        rty_counter_in = rty_counter ;
        rty_counter_almost_max_value = 1'b1 ;
    end
    else
    begin
        rty_counter_in = rty_counter + 1'b1 ;
        rty_counter_almost_max_value = 1'b0 ;
    end
end     

reg     [31:0]  addr_cnt_out ;
reg     [31:0]  addr_cnt_in ;
reg             addr_into_cnt ;
reg             addr_into_cnt_reg ; 
reg             addr_count ;
reg     [3:0]   bc_register ;


always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
    begin
        addr_cnt_out <= #`FF_DELAY 32'h0000_0000 ;
        bc_register  <= #`FF_DELAY 4'h0 ;
        addr_into_cnt_reg <= #`FF_DELAY 1'b0;
    end
    else
    begin
        addr_cnt_out <= #`FF_DELAY addr_cnt_in ;
        addr_into_cnt_reg <= #`FF_DELAY addr_into_cnt;
        if (addr_into_cnt)
            bc_register  <= #`FF_DELAY pciw_fifo_cbe_in ;
    end
end


wire    io_memory_bus_command = !pci_tar_cmd[3] && !pci_tar_cmd[2] ;


always@(addr_into_cnt or r_attempt or addr_count or pciw_fifo_addr_data_in or pci_tar_address or addr_cnt_out or
        io_memory_bus_command)
begin
    if (addr_into_cnt)
    begin
        if (r_attempt)
        begin
            addr_cnt_in = {pci_tar_address[31:2], pci_tar_address[1] && io_memory_bus_command, 
                                                  pci_tar_address[0] && io_memory_bus_command} ; 
        end
        else
        begin
            addr_cnt_in = pciw_fifo_addr_data_in[31:0] ; 
        end
    end
    else
    if (addr_count)
    begin
        addr_cnt_in = addr_cnt_out + 3'h4 ;
    end
    else
    begin
        addr_cnt_in = addr_cnt_out ;
    end
end

reg retried ;
reg retried_d ;
reg retried_write;
reg rty_i_delayed;

reg     first_data_is_burst ;
reg     first_data_is_burst_reg ;
wire    burst_transfer ;
reg     burst_chopped;
reg     burst_chopped_delayed;



always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
    begin
        retried <= #`FF_DELAY 1'b0 ;
        retried_write <= #`FF_DELAY 1'b0 ;
        rty_i_delayed <= #`FF_DELAY 1'B0 ;
    end
    else
    begin
        retried <= #`FF_DELAY retried_d ;
        retried_write <= #`FF_DELAY retried ;
        rty_i_delayed <= #`FF_DELAY wb_rty_i ;
    end
end


always@(addr_into_cnt or r_attempt or pci_tar_burst_ok or max_read_count or 
        pciw_fifo_control_in or pciw_fifo_empty_in)
begin
    if (addr_into_cnt)
    begin
        if (r_attempt)
        begin


            if  (pci_tar_burst_ok && (max_read_count != 8'h1))
                first_data_is_burst = 1'b1 ; 
            else
                first_data_is_burst = 1'b0 ;
        end
        else
        begin
            first_data_is_burst = 1'b0 ;
        end
    end
    else
        first_data_is_burst = pciw_fifo_control_in[`BURST_BIT] && ~pciw_fifo_empty_in && 
                              ~pciw_fifo_control_in[`LAST_CTRL_BIT];
end


always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in) 
    begin
        burst_chopped         <= #`FF_DELAY 1'b0;
        burst_chopped_delayed <= #`FF_DELAY 1'b0;
        first_data_is_burst_reg <= #`FF_DELAY 1'b0 ;
    end
    else
    begin
        if (pciw_fifo_transaction_ready_in)
        begin
            if (pciw_fifo_control_in[`DATA_ERROR_CTRL_BIT])
                burst_chopped     <= #`FF_DELAY 1'b1;
            else if (wb_ack_i || wb_err_i || wb_rty_i)
                burst_chopped     <= #`FF_DELAY 1'b0;
        end
        else
            burst_chopped         <= #`FF_DELAY 1'b0;
        burst_chopped_delayed <= #`FF_DELAY burst_chopped;
        if (last_data_transferred || first_data_is_burst)
            first_data_is_burst_reg <= #`FF_DELAY ~last_data_transferred ;
    end
end
assign  burst_transfer = first_data_is_burst || first_data_is_burst_reg ;

reg [(`WB_FSM_BITS - 1):0]  c_state ;
reg [(`WB_FSM_BITS - 1):0]  n_state ;






always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
    begin
        c_state  <= #`FF_DELAY  S_IDLE;
        wb_cyc_o <= #`FF_DELAY  1'b0;
        wb_stb_o <= #`FF_DELAY  1'b0;
        wb_we_o  <= #`FF_DELAY  1'b0;
        wb_cti_o <= #`FF_DELAY  3'h2;
        wb_bte_o <= #`FF_DELAY  2'h0;
        wb_sel_o <= #`FF_DELAY  4'h0;
        wb_dat_o <= #`FF_DELAY 32'h0;
        pcir_fifo_data_out <= #`FF_DELAY 32'h0;
        pcir_fifo_control_out <= #`FF_DELAY 4'h0;
        pcir_fifo_wenable_out <= #`FF_DELAY 1'b0;
    end
    else
    begin
        c_state  <= #`FF_DELAY  n_state;
        wb_bte_o <= #`FF_DELAY  2'h0;
        case (n_state)
        S_WRITE:
        begin
            wb_cyc_o <= #`FF_DELAY  ~addr_into_cnt;
            wb_stb_o <= #`FF_DELAY  ~addr_into_cnt;
            wb_we_o  <= #`FF_DELAY  ~addr_into_cnt;


            if ((wb_stb_o && wb_ack_i) || addr_into_cnt_reg || (~wb_cyc_o && (retried || burst_chopped_delayed)))
            begin
                if (burst_transfer && ~pciw_fifo_control_in[`DATA_ERROR_CTRL_BIT] &&
                   ~(pciw_fifo_renable_out && (pciw_fifo_control_in[`LAST_CTRL_BIT] || pciw_fifo_almost_empty_in)))
                    wb_cti_o <= #`FF_DELAY  3'h2;
                else
                    wb_cti_o <= #`FF_DELAY  3'h7;
            end
            if ((pciw_fifo_renable_out && ~addr_into_cnt) || addr_into_cnt_reg)
            begin
                wb_sel_o <= #`FF_DELAY  ~pciw_fifo_cbe_in;
                wb_dat_o <= #`FF_DELAY  pciw_fifo_addr_data_in;
            end
        end
        S_WRITE_ERR_RTY:
        begin
            wb_cyc_o <= #`FF_DELAY  1'b0;
            wb_stb_o <= #`FF_DELAY  1'b0;
            wb_we_o  <= #`FF_DELAY  1'b0;
            wb_cti_o <= #`FF_DELAY  3'h2;



        end
        S_READ:
        begin
            wb_cyc_o <= #`FF_DELAY  ~addr_into_cnt;
            wb_stb_o <= #`FF_DELAY  ~addr_into_cnt;
            wb_we_o  <= #`FF_DELAY  1'b0;
            if ((wb_stb_o && wb_ack_i) || addr_into_cnt_reg || (~wb_cyc_o && retried))
            begin
                if (burst_transfer && ~read_bound_comb)
                    wb_cti_o <= #`FF_DELAY  3'h2;
                else
                    wb_cti_o <= #`FF_DELAY  3'h7;
            end
            if (burst_transfer)
                wb_sel_o <= #`FF_DELAY  4'hF;
            else
                wb_sel_o <= #`FF_DELAY  ~pci_tar_be;


        end
        S_READ_RTY:
        begin
            wb_cyc_o <= #`FF_DELAY  1'b0;
            wb_stb_o <= #`FF_DELAY  1'b0;
            wb_we_o  <= #`FF_DELAY  1'b0;
            wb_cti_o <= #`FF_DELAY  3'h2;



        end
        S_TURN_ARROUND:
        begin
            wb_cyc_o <= #`FF_DELAY  1'b0;
            wb_stb_o <= #`FF_DELAY  1'b0;
            wb_we_o  <= #`FF_DELAY  1'b0;
            wb_cti_o <= #`FF_DELAY  3'h2;



        end
        default:
        begin
            wb_cyc_o <= #`FF_DELAY  1'b0;
            wb_stb_o <= #`FF_DELAY  1'b0;
            wb_we_o  <= #`FF_DELAY  1'b0;
            wb_cti_o <= #`FF_DELAY  3'h2;



        end
        endcase
        pcir_fifo_data_out <= #`FF_DELAY  wb_dat_i;
        pcir_fifo_control_out <= #`FF_DELAY pcir_fifo_control ;
        pcir_fifo_wenable_out <= #`FF_DELAY pcir_fifo_wenable ;
    end
end

assign  wb_adr_o = addr_cnt_out ;


always@(c_state or
        wb_ack_i or 
        wb_rty_i or 
        wb_err_i or 
        w_attempt or
        r_attempt or
        retried or 
        burst_chopped or 
        burst_chopped_delayed or 
        rty_i_delayed or
        pci_tar_read_request or
        rty_counter_almost_max_value or 
        set_retry or 
        last_data_to_pcir_fifo or 
        first_wb_data_access or
        pciw_fifo_control_in or 
        pciw_fifo_empty_in or 
        burst_transfer or 
        last_data_from_pciw_fifo_reg
        )
begin
    case (c_state)
    S_IDLE:
        begin

            pcir_fifo_wenable = 1'b0 ;
            pcir_fifo_control = 4'h0 ;
            addr_count = 1'b0 ;
            read_count_enable = 1'b0 ;
            pci_error_sig_out = 1'b0 ;
            error_source_out = 1'b0 ;
            retried_d = 1'b0 ;
            last_data_transferred = 1'b0 ;
            wb_read_done = 1'b0 ;
            wait_for_wb_response = 1'b0 ;
            write_rty_cnt_exp_out = 1'b0 ;
            pci_error_sig_out = 1'b0 ;
            read_rty_cnt_exp_out = 1'b0 ;
            case ({w_attempt, r_attempt, retried})
            3'b101 :
            begin
                pciw_fifo_renable = 1'b0 ;
                addr_into_cnt = 1'b0 ;
                read_count_load = 1'b0 ;
                n_state = S_WRITE ;
            end
            3'b100 :
            begin
                if (burst_chopped_delayed)
                begin
                  addr_into_cnt = 1'b0 ;
                  pciw_fifo_renable = 1'b1 ;
                end
                else
                begin
                  if (pciw_fifo_control_in[`ADDR_CTRL_BIT])
                      addr_into_cnt = 1'b1 ;
                  else
                      addr_into_cnt = 1'b0 ;
                  pciw_fifo_renable = 1'b1 ;
                end
                read_count_load = 1'b0 ;
                n_state = S_WRITE ;
            end
            3'b011 :
            begin
                addr_into_cnt = 1'b0 ;
                read_count_load = 1'b0 ;
                pciw_fifo_renable = 1'b0 ;
                n_state = S_READ ;
            end
            3'b010 :
            begin
                addr_into_cnt = 1'b1 ;
                read_count_load = 1'b1 ;
                pciw_fifo_renable = 1'b0 ;
                n_state = S_READ ;
            end
            default :
            begin
                pciw_fifo_renable = 1'b0 ;
                addr_into_cnt = 1'b0 ;
                read_count_load = 1'b0 ;
                n_state = S_IDLE ;
            end
            endcase
        end
    S_WRITE:
        begin

            pcir_fifo_wenable = 1'b0 ;
            pcir_fifo_control = 4'h0 ;
            addr_into_cnt = 1'b0 ;
            read_count_load = 1'b0 ;
            read_count_enable = 1'b0 ;
            wb_read_done = 1'b0 ;
            read_rty_cnt_exp_out = 1'b0 ;
            case ({wb_ack_i, wb_err_i, wb_rty_i})
            3'b100 :
            begin
                addr_count = 1'b1 ;
                retried_d = 1'b0 ;
                pci_error_sig_out = 1'b0 ;
                error_source_out = 1'b0 ;
                write_rty_cnt_exp_out = 1'b0 ;
                wait_for_wb_response = 1'b0 ;

                if (last_data_from_pciw_fifo_reg) 
                begin                   
                    n_state = S_TURN_ARROUND;
                    if (~pciw_fifo_empty_in)
                        pciw_fifo_renable = 1'b0 ;
                    else
                        pciw_fifo_renable = 1'b0 ;
                    last_data_transferred = 1'b1 ;
                end

                else if (burst_transfer && burst_chopped) 
                begin                   
                    n_state = S_IDLE ;
                    pciw_fifo_renable = 1'b0 ;
                    last_data_transferred = 1'b0 ;
                end
                else
                begin
                    n_state = S_WRITE ;
                    pciw_fifo_renable = 1'b1 ;
                    last_data_transferred = 1'b0 ;
                end
            end
            3'b010 :
            begin
                if (~pciw_fifo_empty_in)
                    pciw_fifo_renable = 1'b1 ;
                else
                    pciw_fifo_renable = 1'b0 ;
                addr_count = 1'b0 ;
                retried_d = 1'b0 ;
                last_data_transferred = 1'b1 ;
                pci_error_sig_out = 1'b1 ;
                error_source_out = 1'b0 ;
                write_rty_cnt_exp_out = 1'b0 ;
                wait_for_wb_response = 1'b0 ;
                if (last_data_from_pciw_fifo_reg)
                    n_state = S_TURN_ARROUND ;
                else
                    n_state = S_WRITE_ERR_RTY ;
            end
            3'b001 :
            begin
                addr_count = 1'b0 ;
                last_data_transferred = 1'b0 ;
                retried_d = 1'b1 ;
                wait_for_wb_response = 1'b0 ;
                if(rty_counter_almost_max_value)
                begin
                    if (last_data_from_pciw_fifo_reg)
                        pciw_fifo_renable = 1'b0 ;
                    else
                        pciw_fifo_renable = 1'b1 ;
                    n_state = S_WRITE_ERR_RTY ;
                    write_rty_cnt_exp_out = 1'b1 ;
                    pci_error_sig_out = 1'b1 ;
                    error_source_out = 1'b1 ;
                end
                else
                begin
                    pciw_fifo_renable = 1'b0 ;
                    n_state = S_IDLE ;
                    write_rty_cnt_exp_out = 1'b0 ;
                    pci_error_sig_out = 1'b0 ;
                    error_source_out = 1'b0 ;
                end
            end
            default :
            begin
                addr_count = 1'b0 ;
                last_data_transferred = 1'b0 ;
                wait_for_wb_response = 1'b1 ;
                error_source_out = 1'b0 ;
                if((rty_counter_almost_max_value)&&(set_retry))
                begin
                    retried_d = 1'b1 ;
                    if (last_data_from_pciw_fifo_reg)
                        pciw_fifo_renable = 1'b0 ;
                    else
                        pciw_fifo_renable = 1'b1 ;
                    n_state = S_WRITE_ERR_RTY ;
                    write_rty_cnt_exp_out = 1'b1 ;
                    pci_error_sig_out = 1'b1 ;
                end
                else
                begin
               	    pciw_fifo_renable = 1'b0 ;
                    retried_d = 1'b0 ;
                    n_state = S_WRITE ;
                    write_rty_cnt_exp_out = 1'b0 ;
                    pci_error_sig_out = 1'b0 ;
                end
            end
            endcase
        end
    S_WRITE_ERR_RTY:
        begin
            pciw_fifo_renable = !last_data_from_pciw_fifo_reg ;
            last_data_transferred = 1'b1 ;

            pcir_fifo_wenable = 1'b0 ;
            pcir_fifo_control = 4'h0 ;
            addr_into_cnt = 1'b0 ;
            read_count_load = 1'b0 ;
            read_count_enable = 1'b0 ;
            addr_count = 1'b0 ;
            pci_error_sig_out = 1'b0 ;
            error_source_out = 1'b0 ;
            retried_d = 1'b0 ;
            wb_read_done = 1'b0 ;
            write_rty_cnt_exp_out = 1'b0 ;
            read_rty_cnt_exp_out = 1'b0 ;
            wait_for_wb_response = 1'b0 ;

            if (last_data_from_pciw_fifo_reg)
                n_state = S_IDLE ;
            else
                n_state = S_WRITE_ERR_RTY ;
        end
    S_READ:
        begin

            pciw_fifo_renable = 1'b0 ;
            addr_into_cnt = 1'b0 ;
            read_count_load = 1'b0 ;
            pci_error_sig_out = 1'b0 ;
            error_source_out = 1'b0 ;
            write_rty_cnt_exp_out = 1'b0 ;
            case ({wb_ack_i, wb_err_i, wb_rty_i})
            3'b100 :
            begin
                pcir_fifo_wenable = 1'b1 ;
                addr_count = 1'b1 ;
                read_count_enable = 1'b1 ;
                retried_d = 1'b0 ;
                read_rty_cnt_exp_out = 1'b0 ;
                wait_for_wb_response = 1'b0 ;

                if (last_data_to_pcir_fifo)
                begin
                    pcir_fifo_control[`LAST_CTRL_BIT]       = 1'b1 ;
                    pcir_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b0 ;
                    pcir_fifo_control[`UNUSED_CTRL_BIT]     = 1'b0 ;
                    pcir_fifo_control[`ADDR_CTRL_BIT]       = 1'b0 ;
                    last_data_transferred = 1'b1 ;
                    wb_read_done = 1'b1 ;
                    n_state = S_TURN_ARROUND ;
                end
                else
                begin
                    pcir_fifo_control = 4'h0 ;
                    last_data_transferred = 1'b0 ;
                    wb_read_done = 1'b0 ;
                    n_state = S_READ ;
                end
            end
            3'b010 :
            begin
                pcir_fifo_wenable = 1'b1 ;
                addr_count = 1'b0 ;
                pcir_fifo_control[`LAST_CTRL_BIT]       = 1'b0 ;
                pcir_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b1 ;
                pcir_fifo_control[`UNUSED_CTRL_BIT]     = 1'b0 ;
                pcir_fifo_control[`ADDR_CTRL_BIT]       = 1'b0 ;
                last_data_transferred = 1'b1 ;
                wb_read_done = 1'b1 ;
                read_count_enable = 1'b0 ;
                n_state = S_TURN_ARROUND ;
                retried_d = 1'b0 ;
                wait_for_wb_response = 1'b0 ;
                read_rty_cnt_exp_out = 1'b0 ;
            end
            3'b001 :
            begin
                pcir_fifo_wenable = 1'b0 ;
                pcir_fifo_control = 4'h0 ;
                addr_count = 1'b0 ;
                read_count_enable = 1'b0 ;
                wait_for_wb_response = 1'b0 ;
                case ({first_wb_data_access, rty_counter_almost_max_value})
                2'b10 :
                begin
                    n_state = S_IDLE ;
                    read_rty_cnt_exp_out = 1'b0 ;
                    last_data_transferred = 1'b0 ;
                    wb_read_done = 1'b0 ;
                    retried_d = 1'b1 ;
                end
                2'b11 :
                begin
                    n_state = S_READ_RTY ;
                    read_rty_cnt_exp_out = 1'b1 ;
                    last_data_transferred = 1'b0 ;
                    wb_read_done = 1'b0 ;
                    retried_d = 1'b1 ;
                end
                default :
                begin
                    n_state = S_TURN_ARROUND ;
                    read_rty_cnt_exp_out = 1'b0 ;
                    last_data_transferred = 1'b1 ;
                    wb_read_done = 1'b1 ;
                    retried_d = 1'b0 ;
                end
                endcase
            end
            default :
            begin
                addr_count = 1'b0 ;
                read_count_enable = 1'b0 ;
                read_rty_cnt_exp_out = 1'b0 ;
                wait_for_wb_response = 1'b1 ;
                if((rty_counter_almost_max_value)&&(set_retry))
                begin
                    retried_d = 1'b1 ;
                    n_state = S_TURN_ARROUND ;
                    pcir_fifo_wenable = 1'b1 ;
                    pcir_fifo_control[`LAST_CTRL_BIT]       = 1'b0 ;
                    pcir_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b1 ;
                    pcir_fifo_control[`UNUSED_CTRL_BIT]     = 1'b0 ;
                    pcir_fifo_control[`ADDR_CTRL_BIT]       = 1'b0 ;
                    last_data_transferred = 1'b1 ;
                    wb_read_done = 1'b1 ;
                end
                else
                begin
                    retried_d = 1'b0 ;
                    n_state = S_READ ;
                    pcir_fifo_wenable = 1'b0 ;
                    pcir_fifo_control = 4'h0 ;
                    last_data_transferred = 1'b0 ;
                    wb_read_done = 1'b0 ;
                end
            end
            endcase
        end
    S_READ_RTY:
        begin

            pciw_fifo_renable = 1'b0 ;
            pcir_fifo_wenable = 1'b0 ;
            pcir_fifo_control = 4'h0 ;
            addr_into_cnt = 1'b0 ;
            read_count_load = 1'b0 ;
            read_count_enable = 1'b0 ;
            addr_count = 1'b0 ;
            pci_error_sig_out = 1'b0 ;
            error_source_out = 1'b0 ;
            retried_d = 1'b0 ;
            wb_read_done = 1'b0 ;
            write_rty_cnt_exp_out = 1'b0 ;
            read_rty_cnt_exp_out = 1'b0 ;
            wait_for_wb_response = 1'b0 ;

            if (pci_tar_read_request)
            begin
                n_state = S_READ_RTY ;
                last_data_transferred = 1'b0 ;
            end
            else
            begin
                n_state = S_IDLE ;
                last_data_transferred = 1'b1 ;
            end
        end    

    default:
        begin

            pciw_fifo_renable = 1'b0 ;
            pcir_fifo_wenable = 1'b0 ;
            pcir_fifo_control = 4'h0 ;
            addr_into_cnt = 1'b0 ;
            read_count_load = 1'b0 ;
            read_count_enable = 1'b0 ;
            addr_count = 1'b0 ;
            pci_error_sig_out = 1'b0 ;
            error_source_out = 1'b0 ;
            retried_d = 1'b0 ;
            last_data_transferred = 1'b1 ;
            wb_read_done = 1'b0 ;
            write_rty_cnt_exp_out = 1'b0 ;
            read_rty_cnt_exp_out = 1'b0 ;
            wait_for_wb_response = 1'b0 ;
            n_state = S_IDLE ;
        end     
    endcase
end


wire ack_rty_response = wb_ack_i || wb_rty_i ;


always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
        first_wb_data_access = 1'b1 ;
    else
    begin
        if (~wb_cyc_o)
            first_wb_data_access = 1'b1 ;
        else if (ack_rty_response)
            first_wb_data_access = 1'b0 ;
    end
end


assign  pcir_fifo_be_out = 4'hf ;


assign  pci_error_bc = bc_register ;


always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
        wb_read_done_out <= #`FF_DELAY 1'b0 ;
    else
        wb_read_done_out <= #`FF_DELAY wb_read_done ;
end

always@(pciw_fifo_renable or addr_into_cnt_reg or pciw_fifo_control_in or pciw_fifo_empty_in)
begin
    pciw_fifo_renable_out           = pciw_fifo_renable || addr_into_cnt_reg ;
    last_data_from_pciw_fifo_reg    = pciw_fifo_control_in[`ADDR_CTRL_BIT] || pciw_fifo_empty_in ;
end


endmodule