data/full_repos/permissive/206169433/pipeline/alu.v
data/verilator_xmls/a6f09225-a96c-426e-a536-ddfed52b4a44.xml
module alu(in1, in2, control, out, zero);
    input [31:0] in1, in2;
    input [3:0] control;
    output reg [31:0] out;
    output zero;


    assign zero = (out == 0);


    initial begin
      out = 32'b0;
    end

    always @ (control, in1, in2) begin
        case(control)
            4'b0000:
                out = in1 & in2;
            4'b0001:
                out = in1 | in2;
            4'b0010:
                out = in1 + in2;
            4'b0110:
                out = in1 - in2;
            4'b0111:
                out = in1<in2 ? 1:0;
            4'b1100:
                out = ~(in1|in2);
        endcase
    end

endmodule
module alu(in1, in2, control, out, zero);

    input [31:0] in1, in2;
    input [3:0] control;
    output reg [31:0] out;
    output zero;


    assign zero = (out == 0);


    initial begin
      out = 32'b0;
    end

    always @ (control, in1, in2) begin
        case(control)
            4'b0000:
                out = in1 & in2;
            4'b0001:
                out = in1 | in2;
            4'b0010:
                out = in1 + in2;
            4'b0110:
                out = in1 - in2;
            4'b0111:
                out = in1<in2 ? 1:0;
            4'b1100:
                out = ~(in1|in2);
        endcase
    end

endmodule