data/full_repos/permissive/202473002/Stereo.srcs/sources_1/imports/FPGA/decoders.v
 line:49: before: "/"
data/verilator_xmls/c4074185-c609-4696-925a-087345766ede.xml
module decoder8(out, in, enable);
    
    output [7:0] out;
    input [2:0] in;
    input enable;
    wire [1:0] w_enable;
    
    decoder2 d0(w_enable, in[2], enable);
    decoder4 d1(out[3:0], in[1:0], w_enable[0]);
    decoder4 d2(out[7:4], in[1:0], w_enable[1]);
    
endmodule
module decoder8(out, in, enable);

    
    output [7:0] out;
    input [2:0] in;
    input enable;
    wire [1:0] w_enable;
    
    decoder2 d0(w_enable, in[2], enable);
    decoder4 d1(out[3:0], in[1:0], w_enable[0]);
    decoder4 d2(out[7:4], in[1:0], w_enable[1]);
    
endmodule