data/full_repos/permissive/135701568/mux12bit.v
data/verilator_xmls/daafe136-e8a0-42ac-98d7-11b6f48fae68.xml
module mux12bit (in1, in2, control, out);
  input[11:0] in1,in2;
  output[11:0] out;
  input control;
  assign out = (control) ? in2 : in1;
endmodule
module mux12bit (in1, in2, control, out);

  input[11:0] in1,in2;
  output[11:0] out;
  input control;
  assign out = (control) ? in2 : in1;
endmodule