data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv
 line:11: before: "realtime"
1: b'%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:11: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  realtime  TP = 4.0ns,   \n                 ^~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:14: syntax error, unexpected bit, expecting IDENTIFIER or \'=\' or do or final\n  bit [CCW-1:0] CCE = 2**CCW-1   \n  ^~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:15: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:32: syntax error, unexpected initial\ninitial        clk = 1\'h0;\n^~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:43: syntax error, unexpected IDENTIFIER\n  for (int unsigned i=0; i<=CCE; i++) begin\n                         ^\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:77: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("pwm_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/113454857/lock_in+pid/fpga/tbn/pwm_tb.sv:78: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, pwm_tb);\n  ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module pwm_tb #(

  realtime  TP = 4.0ns,

  int unsigned  CCW = 4,
  bit [CCW-1:0] CCE = 2**CCW-1
);


logic clk ;
logic rstn;


logic [CCW-1:0] str_dat;
logic           str_rdy;


logic pwm;





initial        clk = 1'h0;
always #(TP/2) clk = ~clk;

initial begin

  rstn = 1'b0;
  str_dat = '0;
  repeat(4) @(posedge clk);

  rstn = 1'b1;

  for (int unsigned i=0; i<=CCE; i++) begin
    while (~str_rdy) @ (posedge clk);
    str_dat <= i[CCW-1:0];
    @ (posedge clk);
  end

  repeat(2*CCE+4) @(posedge clk);

  $finish();
end





pwm #(
  .CCW (CCW),
  .CCE (CCE)
) dut (

  .clk      (clk ),
  .rstn     (rstn),

  .str_dat  (str_dat), 
  .str_rdy  (str_rdy), 

  .pwm      (pwm)
);





initial begin
  $dumpfile("pwm_tb.vcd");
  $dumpvars(0, pwm_tb);
end

endmodule
module pwm_tb #(

  realtime  TP = 4.0ns,

  int unsigned  CCW = 4,
  bit [CCW-1:0] CCE = 2**CCW-1
);



logic clk ;
logic rstn;


logic [CCW-1:0] str_dat;
logic           str_rdy;


logic pwm;





initial        clk = 1'h0;
always #(TP/2) clk = ~clk;

initial begin

  rstn = 1'b0;
  str_dat = '0;
  repeat(4) @(posedge clk);

  rstn = 1'b1;

  for (int unsigned i=0; i<=CCE; i++) begin
    while (~str_rdy) @ (posedge clk);
    str_dat <= i[CCW-1:0];
    @ (posedge clk);
  end

  repeat(2*CCE+4) @(posedge clk);

  $finish();
end





pwm #(
  .CCW (CCW),
  .CCE (CCE)
) dut (

  .clk      (clk ),
  .rstn     (rstn),

  .str_dat  (str_dat), 
  .str_rdy  (str_rdy), 

  .pwm      (pwm)
);





initial begin
  $dumpfile("pwm_tb.vcd");
  $dumpvars(0, pwm_tb);
end

endmodule