data/full_repos/permissive/134057391/2020_sap/sap-1/testbench/pcounter_tb.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/134057391/2020_sap/sap-1/testbench/pcounter_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2020_sap/sap-1/testbench/pcounter_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2020_sap/sap-1/testbench/pcounter_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2) clk = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/2020_sap/sap-1/testbench/pcounter_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2);\n        ^\n%Error: data/full_repos/permissive/134057391/2020_sap/sap-1/testbench/pcounter_tb.v:48: Cannot find file containing module: \'pcounter\'\n pcounter uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/134057391/2020_sap/sap-1/testbench,data/full_repos/permissive/134057391/pcounter\n             data/full_repos/permissive/134057391/2020_sap/sap-1/testbench,data/full_repos/permissive/134057391/pcounter.v\n             data/full_repos/permissive/134057391/2020_sap/sap-1/testbench,data/full_repos/permissive/134057391/pcounter.sv\n             pcounter\n             pcounter.v\n             pcounter.sv\n             obj_dir/pcounter\n             obj_dir/pcounter.v\n             obj_dir/pcounter.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pcounter_tb;

    parameter PERIOD = 10;


	reg clk;
	reg cp;
	reg clr;


	wire [3:0] pc;


	pcounter uut (
		.clk(clk), 
		.cp(cp), 
		.clr(clr), 
		.pc(pc)
	);

	initial begin

		cp = 0;
		clr = 1;


		#100;


        clr = 0;
        #100;


        cp = 1;
	end

    always begin
        clk = 1'b0;
        #(PERIOD/2) clk = 1'b1;
        #(PERIOD/2);
    end  

endmodule
module pcounter_tb;


    parameter PERIOD = 10;


	reg clk;
	reg cp;
	reg clr;


	wire [3:0] pc;


	pcounter uut (
		.clk(clk), 
		.cp(cp), 
		.clr(clr), 
		.pc(pc)
	);

	initial begin

		cp = 0;
		clr = 1;


		#100;


        clr = 0;
        #100;


        cp = 1;
	end

    always begin
        clk = 1'b0;
        #(PERIOD/2) clk = 1'b1;
        #(PERIOD/2);
    end  

endmodule