data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:1: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Mips/Type/Word.v\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Mips/Type/Word.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Mips/Type/Word.v.sv\n             Mips/Type/Word.v\n             Mips/Type/Word.v.v\n             Mips/Type/Word.v.sv\n             obj_dir/Mips/Type/Word.v\n             obj_dir/Mips/Type/Word.v.v\n             obj_dir/Mips/Type/Word.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:2: Cannot find include file: Mips/Type/Bool.v\n`include "Mips/Type/Bool.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:3: Cannot find include file: Mips/Type/RegPorts.v\n`include "Mips/Type/RegPorts.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:5: Cannot find include file: Mips/Control/Control.v\n`include "Mips/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:6: Cannot find include file: Mips/Control/Signal/Register/Control.v\n`include "Mips/Control/Signal/Register/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:8: Cannot find include file: Mips/Pipeline/Ex/Haz.v\n`include "Mips/Pipeline/Ex/Haz.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:9: Cannot find include file: Mips/Pipeline/Reg/Haz.v\n`include "Mips/Pipeline/Reg/Haz.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:10: Cannot find include file: Mips/Pipeline/Haz/Reg.v\n`include "Mips/Pipeline/Haz/Reg.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:12: Cannot find include file: Mips/Hazard/hazard.v\n`include "Mips/Hazard/hazard.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:17: Define or directive not defined: \'`Mips_Pipeline_HazReg_T\'\n ( `Mips_Pipeline_HazReg_T (output) pipeHazReg\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:17: syntax error, unexpected \'(\', expecting \'[\'\n ( `Mips_Pipeline_HazReg_T (output) pipeHazReg\n                            ^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:18: Define or directive not defined: \'`Mips_Pipeline_ExHaz_T\'\n , `Mips_Pipeline_ExHaz_T (input) pipeExHaz\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:19: Define or directive not defined: \'`Mips_Pipeline_RegHaz_T\'\n , `Mips_Pipeline_RegHaz_T (input) pipeRegHaz\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:22: Define or directive not defined: \'`Mips_Control_Control_T\'\n`Mips_Control_Control_T (wire) pipeEx_Control;\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:23: Define or directive not defined: \'`Mips_Type_RegPorts_T\'\n`Mips_Type_RegPorts_T (wire) pipeEx_RegPorts;\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:29: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pipeReg_Instruction;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:30: Define or directive not defined: \'`Mips_Control_Control_T\'\n`Mips_Control_Control_T (wire) pipeReg_Control;\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:37: Define or directive not defined: \'`Mips_Type_RegPorts_T\'\n`Mips_Type_RegPorts_T (wire) pipeReg_RegPorts;\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:44: Define or directive not defined: \'`Mips_Control_Signal_Register_Control_T\'\n`Mips_Control_Signal_Register_Control_T (wire) pipeEx_RegControl;\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:46: Define or directive not defined: \'`Mips_Type_Bool_T\'\n`Mips_Type_Bool_T (wire) stallLwRead;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:49: Define or directive not defined: \'`Mips_Type_RegPorts_Read1Addr\'\n , .regRead1Addr (`Mips_Type_RegPorts_Read1Addr(pipeReg_RegPorts))\n                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:50: Define or directive not defined: \'`Mips_Type_RegPorts_Read2Addr\'\n , .regRead2Addr (`Mips_Type_RegPorts_Read2Addr(pipeReg_RegPorts))\n                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:51: Define or directive not defined: \'`Mips_Type_RegPorts_WriteData\'\n , .exWriteData (`Mips_Type_RegPorts_WriteData(pipeEx_RegPorts))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:52: Define or directive not defined: \'`Mips_Type_RegPorts_WriteAddr\'\n , .exWriteAddr (`Mips_Type_RegPorts_WriteAddr(pipeEx_RegPorts))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/haz.v:55: Define or directive not defined: \'`Mips_Type_Bool_T\'\n`Mips_Type_Bool_T (wire) stall;\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 25 error(s)\n'
module Mips_Stage_haz #
	( parameter ENABLE = 1
	)
	( `Mips_Pipeline_HazReg_T (output) pipeHazReg
	, `Mips_Pipeline_ExHaz_T (input) pipeExHaz
	, `Mips_Pipeline_RegHaz_T (input) pipeRegHaz
	);

`Mips_Control_Control_T (wire) pipeEx_Control;
`Mips_Type_RegPorts_T (wire) pipeEx_RegPorts;
Mips_Pipeline_ExHaz_unpack EXHAZ
	( .in (pipeExHaz)
	, .regPorts (pipeEx_RegPorts)
	);

`Mips_Type_Word_T (wire) pipeReg_Instruction;
`Mips_Control_Control_T (wire) pipeReg_Control;
Mips_Pipeline_RegHaz_unpack REGHAZ
	( .in (pipeRegHaz)
	, .control (pipeReg_Control)
	, .instruction (pipeReg_Instruction)
	);

`Mips_Type_RegPorts_T (wire) pipeReg_RegPorts;
Mips_Datapath_Register_ports PORTS
	( .ports (pipeReg_RegPorts)
	, .control (pipeReg_Control)
	, .instruction (pipeReg_Instruction)
	);

`Mips_Control_Signal_Register_Control_T (wire) pipeEx_RegControl;

`Mips_Type_Bool_T (wire) stallLwRead;
Mips_Hazard_hazard HAZ
	( .stallLwRead (stallLwRead)
	, .regRead1Addr (`Mips_Type_RegPorts_Read1Addr(pipeReg_RegPorts))
	, .regRead2Addr (`Mips_Type_RegPorts_Read2Addr(pipeReg_RegPorts))
	, .exWriteData (`Mips_Type_RegPorts_WriteData(pipeEx_RegPorts))
	, .exWriteAddr (`Mips_Type_RegPorts_WriteAddr(pipeEx_RegPorts))
	);

`Mips_Type_Bool_T (wire) stall;
assign stall = 1'(ENABLE) && stallLwRead;

Mips_Pipeline_HazReg_pack HAZREG
	( .out (pipeHazReg)
	, .stall (stall)
	);

endmodule
module Mips_Stage_haz #
	( parameter ENABLE = 1
	)
	( `Mips_Pipeline_HazReg_T (output) pipeHazReg
	, `Mips_Pipeline_ExHaz_T (input) pipeExHaz
	, `Mips_Pipeline_RegHaz_T (input) pipeRegHaz
	);


`Mips_Control_Control_T (wire) pipeEx_Control;
`Mips_Type_RegPorts_T (wire) pipeEx_RegPorts;
Mips_Pipeline_ExHaz_unpack EXHAZ
	( .in (pipeExHaz)
	, .regPorts (pipeEx_RegPorts)
	);

`Mips_Type_Word_T (wire) pipeReg_Instruction;
`Mips_Control_Control_T (wire) pipeReg_Control;
Mips_Pipeline_RegHaz_unpack REGHAZ
	( .in (pipeRegHaz)
	, .control (pipeReg_Control)
	, .instruction (pipeReg_Instruction)
	);

`Mips_Type_RegPorts_T (wire) pipeReg_RegPorts;
Mips_Datapath_Register_ports PORTS
	( .ports (pipeReg_RegPorts)
	, .control (pipeReg_Control)
	, .instruction (pipeReg_Instruction)
	);

`Mips_Control_Signal_Register_Control_T (wire) pipeEx_RegControl;

`Mips_Type_Bool_T (wire) stallLwRead;
Mips_Hazard_hazard HAZ
	( .stallLwRead (stallLwRead)
	, .regRead1Addr (`Mips_Type_RegPorts_Read1Addr(pipeReg_RegPorts))
	, .regRead2Addr (`Mips_Type_RegPorts_Read2Addr(pipeReg_RegPorts))
	, .exWriteData (`Mips_Type_RegPorts_WriteData(pipeEx_RegPorts))
	, .exWriteAddr (`Mips_Type_RegPorts_WriteAddr(pipeEx_RegPorts))
	);

`Mips_Type_Bool_T (wire) stall;
assign stall = 1'(ENABLE) && stallLwRead;

Mips_Pipeline_HazReg_pack HAZREG
	( .out (pipeHazReg)
	, .stall (stall)
	);

endmodule