data/full_repos/permissive/143278/ivltests/mult2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult2.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk <= 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult2.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult2.v:55: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult2.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult2.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/mult2.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk <= 0;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/mult2.v:64: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance main\n  a <= $random;\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/mult2.v:65: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance main\n  b <= $random;\n    ^~\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MULT18X18S (output reg [35:0] P,
		   input  [17:0] A,
		   input  [17:0] B,
		   input C, CE, R);

   wire [35:0] a_in = { {18{A[17]}}, A[17:0] };
   wire [35:0] b_in = { {18{B[17]}}, B[17:0] };
   wire [35:0] p_in;
   reg [35:0]  p_out;

   assign p_in = a_in * b_in;

   always @(posedge C)
     if (R)
       P <= 36'b0;
     else if (CE)
       P <= p_in;


endmodule
module MULT18X18S (output reg [35:0] P,
		   input  [17:0] A,
		   input  [17:0] B,
		   input C, CE, R);


   wire [35:0] a_in = { {18{A[17]}}, A[17:0] };
   wire [35:0] b_in = { {18{B[17]}}, B[17:0] };
   wire [35:0] p_in;
   reg [35:0]  p_out;

   assign p_in = a_in * b_in;

   always @(posedge C)
     if (R)
       P <= 36'b0;
     else if (CE)
       P <= p_in;


endmodule