data/full_repos/permissive/201025648/Verilog/3.2.v
 line:4: before: "wire"
1: b"%Error: data/full_repos/permissive/201025648/Verilog/3.2.v:4: syntax error, unexpected wire, expecting ',' or ';'\n wire y;  \n ^~~~\n%Error: data/full_repos/permissive/201025648/Verilog/3.2.v:14: syntax error, unexpected '.'\n ...\n ^\n%Error: Cannot continue\n"
module Test;

	reg a, b, c
	wire y;
	...
	logi_gates mylogic_gates(y, a, b,c);

endmodule
module Test;


	reg a, b, c
	wire y;
	...
	logi_gates mylogic_gates(y, a, b,c);

endmodule