data/full_repos/permissive/185301529/mux2.sv
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data/verilator_xmls/4ca2f668-07fc-4558-9276-1d342187b520.xml
module mux2 #(parameter width = 32)
(
	input sel,
	input [width-1:0] a, b,
	output logic [width-1:0] f
);
	always_comb
	begin
		if (sel == 0)
			f = a;
		else
			f = b;
	end
endmodule
module mux2 #(parameter width = 32)
(
	input sel,
	input [width-1:0] a, b,
	output logic [width-1:0] f
);

	always_comb
	begin
		if (sel == 0)
			f = a;
		else
			f = b;
	end
endmodule