data/full_repos/permissive/110143902/projects/reg_sync_reset/src/design/d_trig.v
data/verilator_xmls/e5c3669f-1894-497f-9292-c0585881c870.xml
module d_trig(
    D, C, R,
    Q, notQ
    );


    parameter INIT_VAL    = 0;
    parameter RESET_VAL   = 1;


    input wire D, C, R;
    output wire Q, notQ;


    reg Q_reg = INIT_VAL;



    always @(posedge C) begin
        if(R == RESET_VAL)
            Q_reg <= INIT_VAL;
        else
            Q_reg <= D;
    end

    assign Q    = Q_reg;
    assign notQ = !Q_reg;

endmodule
module d_trig(
    D, C, R,
    Q, notQ
    );



    parameter INIT_VAL    = 0;
    parameter RESET_VAL   = 1;


    input wire D, C, R;
    output wire Q, notQ;


    reg Q_reg = INIT_VAL;



    always @(posedge C) begin
        if(R == RESET_VAL)
            Q_reg <= INIT_VAL;
        else
            Q_reg <= D;
    end

    assign Q    = Q_reg;
    assign notQ = !Q_reg;

endmodule