data/full_repos/permissive/118928497/QE_M_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/118928497/QE_M_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #2.5 clk <= ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/118928497/QE_M_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #2.5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/118928497/QE_M_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #20 reset <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118928497/QE_M_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #1 {valid_in, last_input, mode, in_a, in_b, in_c, in_x, expected_result, expected_valid_out} <= testvectors[vectornum];\n  ^\n%Error: data/full_repos/permissive/118928497/QE_M_tb.v:24: Cannot find file containing module: \'QE_M\'\nQE_M QE_M (\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/118928497,data/full_repos/permissive/118928497/QE_M\n             data/full_repos/permissive/118928497,data/full_repos/permissive/118928497/QE_M.v\n             data/full_repos/permissive/118928497,data/full_repos/permissive/118928497/QE_M.sv\n             QE_M\n             QE_M.v\n             QE_M.sv\n             obj_dir/QE_M\n             obj_dir/QE_M.v\n             obj_dir/QE_M.sv\n%Warning-WIDTH: data/full_repos/permissive/118928497/QE_M_tb.v:95: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                 : ... In instance QE_M_tb\n  vectornum <= 3\'b0;  errors <= 3\'b0;      \n            ^~\n%Warning-WIDTH: data/full_repos/permissive/118928497/QE_M_tb.v:95: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                 : ... In instance QE_M_tb\n  vectornum <= 3\'b0;  errors <= 3\'b0;      \n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/118928497/QE_M_tb.v:115: Operator EQ expects 53 bits on the LHS, but LHS\'s ARRAYSEL generates 52 bits.\n                                                                  : ... In instance QE_M_tb\n        if (testvectors[vectornum] == 53\'bx) begin\n                                   ^~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module QE_M_tb ();

reg clk, reset;


reg valid_in, last_input, mode;
reg [7:0]in_a;
reg [7:0]in_x;
reg [7:0]in_b;
reg [7:0]in_c;
reg [15:0]expected_result;
reg expected_valid_out;

reg [31:0]vectornum;
reg [31:0]errors;
reg [51:0] testvectors[10000:0];



wire valid_out;
wire [15:0]result;


QE_M QE_M (
  .clk            (clk),
  .reset          (reset),
  .in_a           (in_a),
  .in_b           (in_b),
  .in_c           (in_c),
  .in_x           (in_x),
  .mode           (mode),
  .valid_in       (valid_in),
  .last_input     (last_input),
  .valid_out      (valid_out),
  .result         (result)
);
















































always begin

    clk <= 1'b1;
    #2.5 clk <= ~clk;
    #2.5;
end


initial begin
  $readmemb("example.tv", testvectors);
  vectornum <= 3'b0;  errors <= 3'b0;

  reset <= 1'b1;
  #20 reset <= 1'b0;
end


always @ (posedge clk) begin
  #1 {valid_in, last_input, mode, in_a, in_b, in_c, in_x, expected_result, expected_valid_out} <= testvectors[vectornum];
end


always @ (negedge clk) begin
    if (~reset) begin
        if (result != expected_result) begin
            $display("Error: inputs = %d", {valid_in, last_input, mode, in_a, in_b, in_c, in_x, expected_result, expected_valid_out});
            $display("  outputs = %d (%d exp)", result, expected_result);
            errors <= errors + 1;
        end
        vectornum = vectornum + 1;
        if (testvectors[vectornum] == 53'bx) begin
            $display("%d tests completed with %d errors", vectornum, errors);
            $finish;
        end
    end
end

endmodule
module QE_M_tb ();


reg clk, reset;


reg valid_in, last_input, mode;
reg [7:0]in_a;
reg [7:0]in_x;
reg [7:0]in_b;
reg [7:0]in_c;
reg [15:0]expected_result;
reg expected_valid_out;

reg [31:0]vectornum;
reg [31:0]errors;
reg [51:0] testvectors[10000:0];



wire valid_out;
wire [15:0]result;


QE_M QE_M (
  .clk            (clk),
  .reset          (reset),
  .in_a           (in_a),
  .in_b           (in_b),
  .in_c           (in_c),
  .in_x           (in_x),
  .mode           (mode),
  .valid_in       (valid_in),
  .last_input     (last_input),
  .valid_out      (valid_out),
  .result         (result)
);
















































always begin

    clk <= 1'b1;
    #2.5 clk <= ~clk;
    #2.5;
end


initial begin
  $readmemb("example.tv", testvectors);
  vectornum <= 3'b0;  errors <= 3'b0;

  reset <= 1'b1;
  #20 reset <= 1'b0;
end


always @ (posedge clk) begin
  #1 {valid_in, last_input, mode, in_a, in_b, in_c, in_x, expected_result, expected_valid_out} <= testvectors[vectornum];
end


always @ (negedge clk) begin
    if (~reset) begin
        if (result != expected_result) begin
            $display("Error: inputs = %d", {valid_in, last_input, mode, in_a, in_b, in_c, in_x, expected_result, expected_valid_out});
            $display("  outputs = %d (%d exp)", result, expected_result);
            errors <= errors + 1;
        end
        vectornum = vectornum + 1;
        if (testvectors[vectornum] == 53'bx) begin
            $display("%d tests completed with %d errors", vectornum, errors);
            $finish;
        end
    end
end

endmodule