data/full_repos/permissive/104305228/code/ex_mem.v
1: b'%Error: data/full_repos/permissive/104305228/code/ex_mem.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:22: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable || (stall[3] == `StallEnable && stall[4] == `StallDisable)) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:22: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n  if (rst == `RstEnable || (stall[3] == `StallEnable && stall[4] == `StallDisable)) begin\n                        ^~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:22: Define or directive not defined: \'`StallEnable\'\n  if (rst == `RstEnable || (stall[3] == `StallEnable && stall[4] == `StallDisable)) begin\n                                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:22: Define or directive not defined: \'`StallDisable\'\n  if (rst == `RstEnable || (stall[3] == `StallEnable && stall[4] == `StallDisable)) begin\n                                                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:24: Define or directive not defined: \'`op_null\'\n   mem_op <= `op_null;\n             ^~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   mem_op <= `op_null;\n                     ^\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:27: Define or directive not defined: \'`WriteDisable\'\n   mem_we <= `WriteDisable;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   mem_we <= `WriteDisable;\n                          ^\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:31: syntax error, unexpected else\n  else if (stall[3] == `StallDisable) begin\n  ^~~~\n%Error: data/full_repos/permissive/104305228/code/ex_mem.v:31: Define or directive not defined: \'`StallDisable\'\n  else if (stall[3] == `StallDisable) begin\n                       ^~~~~~~~~~~~~\n%Error: Cannot continue\n'
module ex_mem(
	input clk,
	input rst,
	input [5:0] stall,
	input [31:0] ex_instr,
	input [7:0] ex_op,
	input [31:0] ex_reg1,
	input [31:0] ex_reg2,
	input ex_we,
	input [4:0] ex_write_addr,
	input [31:0] ex_write_instr,
	output reg[31:0] mem_instr,
	output reg[7:0] mem_op,
	output reg[31:0] mem_reg1,
	output reg[31:0] mem_reg2,
	output reg mem_we,
	output reg[4:0] mem_write_addr,
	output reg[31:0] mem_write_instr
);
	always @ (posedge clk) begin
		if (rst == `RstEnable || (stall[3] == `StallEnable && stall[4] == `StallDisable)) begin
			mem_instr <= 32'b0;
			mem_op <= `op_null;
			mem_reg1 <= 32'b0;
			mem_reg2 <= 32'b0;
			mem_we <= `WriteDisable;
			mem_write_addr <= 5'b0;
			mem_write_instr <= 32'b0;
		end
		else if (stall[3] == `StallDisable) begin
			mem_instr <= ex_instr;
			mem_op <= ex_op;
			mem_reg1 <= ex_reg1;
			mem_reg2 <= ex_reg2;
			mem_we <= ex_we;
			mem_write_addr <= ex_write_addr;
			mem_write_instr <= ex_write_instr;
		end
	end
endmodule
module ex_mem(
	input clk,
	input rst,
	input [5:0] stall,
	input [31:0] ex_instr,
	input [7:0] ex_op,
	input [31:0] ex_reg1,
	input [31:0] ex_reg2,
	input ex_we,
	input [4:0] ex_write_addr,
	input [31:0] ex_write_instr,
	output reg[31:0] mem_instr,
	output reg[7:0] mem_op,
	output reg[31:0] mem_reg1,
	output reg[31:0] mem_reg2,
	output reg mem_we,
	output reg[4:0] mem_write_addr,
	output reg[31:0] mem_write_instr
);

	always @ (posedge clk) begin
		if (rst == `RstEnable || (stall[3] == `StallEnable && stall[4] == `StallDisable)) begin
			mem_instr <= 32'b0;
			mem_op <= `op_null;
			mem_reg1 <= 32'b0;
			mem_reg2 <= 32'b0;
			mem_we <= `WriteDisable;
			mem_write_addr <= 5'b0;
			mem_write_instr <= 32'b0;
		end
		else if (stall[3] == `StallDisable) begin
			mem_instr <= ex_instr;
			mem_op <= ex_op;
			mem_reg1 <= ex_reg1;
			mem_reg2 <= ex_reg2;
			mem_we <= ex_we;
			mem_write_addr <= ex_write_addr;
			mem_write_instr <= ex_write_instr;
		end
	end
endmodule