data/full_repos/permissive/113654920/hdl/PS2_DMA.v
data/verilator_xmls/6d27558d-a9f9-4764-8f6a-d0f5e118419c.xml
module PS2_DMA (

	input CLK4,
	input Phase3,

	output reg cDQ,
	input cDK,
	input cRd,
	input DWrite,

	input DMA_ARM		,
	input PS2WrIDE		,

	input PB_OD_Rdy  ,
	input PB_HvSpace  ,
	input WithinBBlock  ,
	input BBurstEnd	 ,

	output  reg IncAddrB  ,
	output  RegEB	 ,
	output  reg EnbB	 ,
	output  reg WrB
);

reg DTook;
reg DWrote;



parameter PIdle 	= 5'b00000;

parameter PR20 	= 5'b00100;
parameter PR21 	= 5'b00101;
parameter PR22 	= 5'b00110;
parameter PR23 	= 5'b00111;
parameter PR32 	= 5'b01000;
parameter PR37 	= 5'b01001;
parameter PR38 	= 5'b01010;
parameter PR38A 	= 5'b01011;
parameter PR38B 	= 5'b01100;

parameter PW01A	= 5'b10001;
parameter PW01B	= 5'b10010;
parameter PW01C	= 5'b10011;
parameter PW01D	= 5'b10100;
parameter PW32		= 5'b10101;
parameter PW35		= 5'b10110;
parameter PW36		= 5'b10111;
parameter PW37		= 5'b11000;
parameter PW38A	= 5'b11001;
parameter PW38B	= 5'b11010;
parameter PW38C	= 5'b11011;
parameter PW38D	= 5'b11100;
parameter PW40		= 5'b11101;

reg [4:0] PSST;
reg OPOvrRide;









assign RegEB = Phase3 & ( cRd | OPOvrRide );



always @(posedge CLK4) begin
if (DMA_ARM == 1'b0) begin
	cDQ			<= 1'b0;
	DTook			<= 1'b0;
	DWrote		<= 1'b0;
	IncAddrB		<= 1'b0;
	OPOvrRide	<= 1'b0;
	EnbB			<= 1'b0;
	WrB			<=	1'b0;
	PSST			<= PIdle;
end else begin

	case (PSST)
	PIdle: begin
		if (PS2WrIDE == 1'b0) begin
			cDQ	<= 1'b0;
			if ((PB_OD_Rdy == 1'b1) && (Phase3 == 1'b1)) begin
				PSST	<= PR38;
			end
		end else begin
			cDQ	<= PB_HvSpace;
			if ((cDK == 1'b1) && (Phase3 == 1'b1)) begin
				PSST	<= PW40;
			end
		end
	end

	PR38: begin
		cDQ		<= 1'b0;
		DTook		<= 1'b1;
		if (Phase3 == 1'b1) begin
			PSST <= PR38A;
		end
	end

	PR38A: begin
		EnbB		<= DTook;
		if (Phase3 == 1'b1) begin
			PSST	<= PR38B;
		end
	end

	PR38B: begin
		EnbB			<= 1'b0;
		OPOvrRide	<= 1'b1;
		cDQ			<= 1'b1;
		if ((Phase3 == 1'b1) && (cDK == 1'b1)) begin
			PSST 		<= PR20;
			DTook		<= cRd;
		end
	end

	PR20: begin
		OPOvrRide	<= 1'b0;
		IncAddrB		<= DTook;
		if ((DTook == 1'b1) && (BBurstEnd == 1'b1)) begin
			PSST		<= PR32;
		end else begin
			PSST		<= PR21;
		end
	end
	PR21: begin
		IncAddrB	<=	1'b0;
		EnbB		<= DTook;
		PSST		<= PR22;
	end
	PR22: begin
		EnbB		<= 1'b0;
		cDQ		<= cDQ & ~DTook;
		PSST		<= PR23;
	end
	PR23: begin
		DTook		<= cRd;
		if (cDK == 1'b1) begin
			PSST <= PR20;
		end else begin
			PSST <= PR37;
		end
	end











	PR32: begin
		IncAddrB	<=	1'b0;
		if (cDK == 1'b1) begin
			PSST		<= PR32;
		end else begin
			PSST 		<= PR37;
		end
	end

	PR37: begin
		if (WithinBBlock == 1'b1) begin
			if (Phase3 == 1'b1) begin
				PSST	<= PR38;
			end else begin
				PSST	<= PR37;
			end
		end else begin
			PSST <= PIdle;
		end
	end


	PW40: begin
		if ((Phase3 == 1'b1) && (cDK == 1'b1)) begin
			PSST	<= PW01A;
		end
	end

	PW01A: begin
		IncAddrB	<= 1'b0;
		PSST		<= PW01B;
	end
	PW01B: begin
		DWrote	<= DWrite;
		PSST		<= PW01C;
	end
	PW01C: begin
		EnbB		<= DWrote;
		WrB		<= DWrote;
		PSST		<= PW01D;
	end
	PW01D: begin
		EnbB		<= 1'b0;
		WrB		<= 1'b0;
		IncAddrB	<= DWrote;
		if (DWrote == 1'b1) begin
			if (BBurstEnd == 1'b1) begin
				PSST	<= PW32;
			end else begin
				PSST	<= PW01A;
			end
		end else begin
			PSST	<= PW01A;
		end
	end

	PW32: begin
		IncAddrB		<= 1'b0;
		if (cDK == 1'b1) begin
			PSST <= PW32;
		end else begin
			PSST <= PW35;
		end
	end

	PW35: begin
		if (Phase3 == 1'b1) begin
			PSST <= PW36;
		end
	end
	PW36: begin
		if (WithinBBlock == 1'b1) begin
			if (Phase3 == 1'b1) begin
				PSST <= PW37;
			end else begin
				PSST <= PW36;
			end
		end else begin
			PSST <= PIdle;
		end
	end

	PW37:	begin
		if (Phase3 == 1'b1) begin
				PSST <= PW38A;
		end
	end

	PW38A: begin
		PSST	<= PW38B;
	end
	PW38B: begin
		PSST	<= PW38C;
	end
	PW38C: begin
		cDQ <= 1'b1;
		PSST	<= PW38D;
	end
	PW38D: begin
		PSST <= PW40;
	end

	default: begin 
	   PSST <= PIdle;
	end
	endcase
end
end 

endmodule
module PS2_DMA (

	input CLK4,
	input Phase3,

	output reg cDQ,
	input cDK,
	input cRd,
	input DWrite,

	input DMA_ARM		,
	input PS2WrIDE		,

	input PB_OD_Rdy  ,
	input PB_HvSpace  ,
	input WithinBBlock  ,
	input BBurstEnd	 ,

	output  reg IncAddrB  ,
	output  RegEB	 ,
	output  reg EnbB	 ,
	output  reg WrB
);


reg DTook;
reg DWrote;



parameter PIdle 	= 5'b00000;

parameter PR20 	= 5'b00100;
parameter PR21 	= 5'b00101;
parameter PR22 	= 5'b00110;
parameter PR23 	= 5'b00111;
parameter PR32 	= 5'b01000;
parameter PR37 	= 5'b01001;
parameter PR38 	= 5'b01010;
parameter PR38A 	= 5'b01011;
parameter PR38B 	= 5'b01100;

parameter PW01A	= 5'b10001;
parameter PW01B	= 5'b10010;
parameter PW01C	= 5'b10011;
parameter PW01D	= 5'b10100;
parameter PW32		= 5'b10101;
parameter PW35		= 5'b10110;
parameter PW36		= 5'b10111;
parameter PW37		= 5'b11000;
parameter PW38A	= 5'b11001;
parameter PW38B	= 5'b11010;
parameter PW38C	= 5'b11011;
parameter PW38D	= 5'b11100;
parameter PW40		= 5'b11101;

reg [4:0] PSST;
reg OPOvrRide;









assign RegEB = Phase3 & ( cRd | OPOvrRide );



always @(posedge CLK4) begin
if (DMA_ARM == 1'b0) begin
	cDQ			<= 1'b0;
	DTook			<= 1'b0;
	DWrote		<= 1'b0;
	IncAddrB		<= 1'b0;
	OPOvrRide	<= 1'b0;
	EnbB			<= 1'b0;
	WrB			<=	1'b0;
	PSST			<= PIdle;
end else begin

	case (PSST)
	PIdle: begin
		if (PS2WrIDE == 1'b0) begin
			cDQ	<= 1'b0;
			if ((PB_OD_Rdy == 1'b1) && (Phase3 == 1'b1)) begin
				PSST	<= PR38;
			end
		end else begin
			cDQ	<= PB_HvSpace;
			if ((cDK == 1'b1) && (Phase3 == 1'b1)) begin
				PSST	<= PW40;
			end
		end
	end

	PR38: begin
		cDQ		<= 1'b0;
		DTook		<= 1'b1;
		if (Phase3 == 1'b1) begin
			PSST <= PR38A;
		end
	end

	PR38A: begin
		EnbB		<= DTook;
		if (Phase3 == 1'b1) begin
			PSST	<= PR38B;
		end
	end

	PR38B: begin
		EnbB			<= 1'b0;
		OPOvrRide	<= 1'b1;
		cDQ			<= 1'b1;
		if ((Phase3 == 1'b1) && (cDK == 1'b1)) begin
			PSST 		<= PR20;
			DTook		<= cRd;
		end
	end

	PR20: begin
		OPOvrRide	<= 1'b0;
		IncAddrB		<= DTook;
		if ((DTook == 1'b1) && (BBurstEnd == 1'b1)) begin
			PSST		<= PR32;
		end else begin
			PSST		<= PR21;
		end
	end
	PR21: begin
		IncAddrB	<=	1'b0;
		EnbB		<= DTook;
		PSST		<= PR22;
	end
	PR22: begin
		EnbB		<= 1'b0;
		cDQ		<= cDQ & ~DTook;
		PSST		<= PR23;
	end
	PR23: begin
		DTook		<= cRd;
		if (cDK == 1'b1) begin
			PSST <= PR20;
		end else begin
			PSST <= PR37;
		end
	end











	PR32: begin
		IncAddrB	<=	1'b0;
		if (cDK == 1'b1) begin
			PSST		<= PR32;
		end else begin
			PSST 		<= PR37;
		end
	end

	PR37: begin
		if (WithinBBlock == 1'b1) begin
			if (Phase3 == 1'b1) begin
				PSST	<= PR38;
			end else begin
				PSST	<= PR37;
			end
		end else begin
			PSST <= PIdle;
		end
	end


	PW40: begin
		if ((Phase3 == 1'b1) && (cDK == 1'b1)) begin
			PSST	<= PW01A;
		end
	end

	PW01A: begin
		IncAddrB	<= 1'b0;
		PSST		<= PW01B;
	end
	PW01B: begin
		DWrote	<= DWrite;
		PSST		<= PW01C;
	end
	PW01C: begin
		EnbB		<= DWrote;
		WrB		<= DWrote;
		PSST		<= PW01D;
	end
	PW01D: begin
		EnbB		<= 1'b0;
		WrB		<= 1'b0;
		IncAddrB	<= DWrote;
		if (DWrote == 1'b1) begin
			if (BBurstEnd == 1'b1) begin
				PSST	<= PW32;
			end else begin
				PSST	<= PW01A;
			end
		end else begin
			PSST	<= PW01A;
		end
	end

	PW32: begin
		IncAddrB		<= 1'b0;
		if (cDK == 1'b1) begin
			PSST <= PW32;
		end else begin
			PSST <= PW35;
		end
	end

	PW35: begin
		if (Phase3 == 1'b1) begin
			PSST <= PW36;
		end
	end
	PW36: begin
		if (WithinBBlock == 1'b1) begin
			if (Phase3 == 1'b1) begin
				PSST <= PW37;
			end else begin
				PSST <= PW36;
			end
		end else begin
			PSST <= PIdle;
		end
	end

	PW37:	begin
		if (Phase3 == 1'b1) begin
				PSST <= PW38A;
		end
	end

	PW38A: begin
		PSST	<= PW38B;
	end
	PW38B: begin
		PSST	<= PW38C;
	end
	PW38C: begin
		cDQ <= 1'b1;
		PSST	<= PW38D;
	end
	PW38D: begin
		PSST <= PW40;
	end

	default: begin 
	   PSST <= PIdle;
	end
	endcase
end
end 

endmodule