data/full_repos/permissive/21203606/ex3/uart_rx.v
 line:108: before: "Aclk"
1: b'%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:3: Cannot find include file: uart_params.v\n`include "uart_params.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21203606/ex3,data/full_repos/permissive/21203606/uart_params.v\n             data/full_repos/permissive/21203606/ex3,data/full_repos/permissive/21203606/uart_params.v.v\n             data/full_repos/permissive/21203606/ex3,data/full_repos/permissive/21203606/uart_params.v.sv\n             uart_params.v\n             uart_params.v.v\n             uart_params.v.sv\n             obj_dir/uart_params.v\n             obj_dir/uart_params.v.v\n             obj_dir/uart_params.v.sv\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:18: Define or directive not defined: \'`UART_FULL_ETU\'\n  wire etu_full = (etu_cnt == `UART_FULL_ETU);\n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:18: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  wire etu_full = (etu_cnt == `UART_FULL_ETU);\n                                            ^\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:19: Define or directive not defined: \'`UART_HALF_ETU\'\n  wire etu_half = (etu_cnt == `UART_HALF_ETU);\n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:19: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  wire etu_half = (etu_cnt == `UART_HALF_ETU);\n                                            ^\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:32: Define or directive not defined: \'`UART_START\'\n      state <= `UART_START;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      state <= `UART_START;\n                          ^\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:44: Define or directive not defined: \'`UART_START\'\n      `UART_START:\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:44: syntax error, unexpected \':\', expecting endcase\n      `UART_START:\n                 ^\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:60: Define or directive not defined: \'`UART_DATA\'\n              state <= `UART_DATA;\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:60: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n              state <= `UART_DATA;\n                                 ^\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:70: Define or directive not defined: \'`UART_DATA\'\n      `UART_DATA:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:71: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      begin \n      ^~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:79: Define or directive not defined: \'`UART_STOP\'\n            state <= `UART_STOP;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            state <= `UART_STOP;\n                               ^\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:85: Define or directive not defined: \'`UART_STOP\'\n      `UART_STOP:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:86: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      begin\n      ^~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:91: Define or directive not defined: \'`UART_START\'\n          state <= `UART_START;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/ex3/uart_rx.v:91: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n          state <= `UART_START;\n                              ^\n%Error: Cannot continue\n'
module uart_rx(
  input wire clk,
  input wire rst,
  input wire din,
  output reg valid,
  output reg [7:0] data_in);
  
  reg [8:0] etu_cnt;
  reg [2:0] bit_cnt;
  reg [7:0] data;
  reg [1:0] state;
  reg starting;
  
  wire etu_full = (etu_cnt == `UART_FULL_ETU);
  wire etu_half = (etu_cnt == `UART_HALF_ETU);
  
  always @(posedge clk) begin
    
    etu_cnt <= (etu_cnt + 1);
    bit_cnt <= bit_cnt;
    
    state <= state;
    valid <= valid;
    data <= data;
    starting <= starting;
    
    if (rst) begin
      state <= `UART_START;
      bit_cnt <= 2'd0;
      etu_cnt <= 9'd0;
      data <= 8'd0;
      valid <= 1'b0;    
      data_in <= 8'd0;
    end
    
    else
    begin
      
    case (state)
      `UART_START:
      begin
        valid <= 1'd0;
        


        if (~din) begin
          if (~starting) begin
            starting <= 1'd1;
            etu_cnt <= 9'd0;
          end
          else
          begin 
            if (etu_half) begin
              etu_cnt <= 0;
              bit_cnt <= 0;
              state <= `UART_DATA;
            end
          end
        end
        else
        begin
          starting <= 1'd0;
        end
      end
      
      `UART_DATA:
      begin 
        if (etu_full) begin
          etu_cnt <= 9'd0;
          bit_cnt <= (bit_cnt + 1);
          
          data <= {din, data[7:1]};
          
          if (bit_cnt == 7) begin
            state <= `UART_STOP;
          end
          
        end
      end
      
      `UART_STOP:
      begin
        if (etu_full) begin
          etu_cnt <= 9'd0;
          data_in <= data;
          valid <= din;
          state <= `UART_START;
        end
      end
      
    endcase
    
    end
  end 
  
endmodule
module uart_rx(
  input wire clk,
  input wire rst,
  input wire din,
  output reg valid,
  output reg [7:0] data_in);

  
  reg [8:0] etu_cnt;
  reg [2:0] bit_cnt;
  reg [7:0] data;
  reg [1:0] state;
  reg starting;
  
  wire etu_full = (etu_cnt == `UART_FULL_ETU);
  wire etu_half = (etu_cnt == `UART_HALF_ETU);
  
  always @(posedge clk) begin
    
    etu_cnt <= (etu_cnt + 1);
    bit_cnt <= bit_cnt;
    
    state <= state;
    valid <= valid;
    data <= data;
    starting <= starting;
    
    if (rst) begin
      state <= `UART_START;
      bit_cnt <= 2'd0;
      etu_cnt <= 9'd0;
      data <= 8'd0;
      valid <= 1'b0;    
      data_in <= 8'd0;
    end
    
    else
    begin
      
    case (state)
      `UART_START:
      begin
        valid <= 1'd0;
        


        if (~din) begin
          if (~starting) begin
            starting <= 1'd1;
            etu_cnt <= 9'd0;
          end
          else
          begin 
            if (etu_half) begin
              etu_cnt <= 0;
              bit_cnt <= 0;
              state <= `UART_DATA;
            end
          end
        end
        else
        begin
          starting <= 1'd0;
        end
      end
      
      `UART_DATA:
      begin 
        if (etu_full) begin
          etu_cnt <= 9'd0;
          bit_cnt <= (bit_cnt + 1);
          
          data <= {din, data[7:1]};
          
          if (bit_cnt == 7) begin
            state <= `UART_STOP;
          end
          
        end
      end
      
      `UART_STOP:
      begin
        if (etu_full) begin
          etu_cnt <= 9'd0;
          data_in <= data;
          valid <= din;
          state <= `UART_START;
        end
      end
      
    endcase
    
    end
  end 
  
endmodule