data/full_repos/permissive/107757225/audio/audio-uw/audio_driver.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/107757225/audio/audio-uw/audio_driver.sv:95: Unsupported: Ignoring delay on this delayed statement.\n   #(40690); \n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/107757225/audio/audio-uw/audio_driver.sv:119: Cannot find file containing module: \'audio_and_video_config\'\n audio_and_video_config cfg(\n ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/107757225/audio/audio-uw,data/full_repos/permissive/107757225/audio_and_video_config\n             data/full_repos/permissive/107757225/audio/audio-uw,data/full_repos/permissive/107757225/audio_and_video_config.v\n             data/full_repos/permissive/107757225/audio/audio-uw,data/full_repos/permissive/107757225/audio_and_video_config.sv\n             audio_and_video_config\n             audio_and_video_config.v\n             audio_and_video_config.sv\n             obj_dir/audio_and_video_config\n             obj_dir/audio_and_video_config.v\n             obj_dir/audio_and_video_config.sv\n%Error: data/full_repos/permissive/107757225/audio/audio-uw/audio_driver.sv:129: Cannot find file containing module: \'audio_codec\'\n audio_codec codec(\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module audio_driver (CLOCK_50, reset, dac_left, dac_right, adc_left, adc_right, advance, FPGA_I2C_SCLK, FPGA_I2C_SDAT, AUD_XCK, AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK, AUD_ADCDAT, AUD_DACDAT);
	input CLOCK_50;
	input reset;

	output FPGA_I2C_SCLK;
	inout FPGA_I2C_SDAT;

	output AUD_XCK;
	input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK;
	input AUD_ADCDAT;
	output AUD_DACDAT;

	input [23:0] dac_left, dac_right;
	output [23:0] adc_left, adc_right;
	output advance;
	

	wire read_ready, write_ready;
	reg write;
	wire read;
	


	reg w1, w2;
	
	assign read = write;
	assign advance = write;

	always @(posedge CLOCK_50) begin
		if (reset) begin
			w1 <= 0;
			w2 <= 0;
			write <= 0;
		end else begin
			w1 <= write_ready & read_ready & !w2;
			w2 <= w1;
			write <= w1 & !w2;
		end
	end
	
	wire locked;
	

	`ifdef DOING_SIMULATION
		reg AUD_XCK;
		initial AUD_XCK = 0; 
		always begin 
			#(40690); 
			AUD_XCK = ~AUD_XCK; 
		end
	`else


	`endif
	
	















	audio_and_video_config cfg(

		CLOCK_50,
		reset,


		FPGA_I2C_SDAT,
		FPGA_I2C_SCLK
	);

	audio_codec codec(

		CLOCK_50,
		reset,

		read,	write,
		dac_left, dac_right,

		AUD_ADCDAT,


		AUD_BCLK,
		AUD_ADCLRCK,
		AUD_DACLRCK,


		read_ready, write_ready,
		adc_left, adc_right,
		AUD_DACDAT
	);
endmodule
module audio_driver (CLOCK_50, reset, dac_left, dac_right, adc_left, adc_right, advance, FPGA_I2C_SCLK, FPGA_I2C_SDAT, AUD_XCK, AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK, AUD_ADCDAT, AUD_DACDAT);

	input CLOCK_50;
	input reset;

	output FPGA_I2C_SCLK;
	inout FPGA_I2C_SDAT;

	output AUD_XCK;
	input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK;
	input AUD_ADCDAT;
	output AUD_DACDAT;

	input [23:0] dac_left, dac_right;
	output [23:0] adc_left, adc_right;
	output advance;
	

	wire read_ready, write_ready;
	reg write;
	wire read;
	


	reg w1, w2;
	
	assign read = write;
	assign advance = write;

	always @(posedge CLOCK_50) begin
		if (reset) begin
			w1 <= 0;
			w2 <= 0;
			write <= 0;
		end else begin
			w1 <= write_ready & read_ready & !w2;
			w2 <= w1;
			write <= w1 & !w2;
		end
	end
	
	wire locked;
	

	`ifdef DOING_SIMULATION
		reg AUD_XCK;
		initial AUD_XCK = 0; 
		always begin 
			#(40690); 
			AUD_XCK = ~AUD_XCK; 
		end
	`else


	`endif
	
	















	audio_and_video_config cfg(

		CLOCK_50,
		reset,


		FPGA_I2C_SDAT,
		FPGA_I2C_SCLK
	);

	audio_codec codec(

		CLOCK_50,
		reset,

		read,	write,
		dac_left, dac_right,

		AUD_ADCDAT,


		AUD_BCLK,
		AUD_ADCLRCK,
		AUD_DACLRCK,


		read_ready, write_ready,
		adc_left, adc_right,
		AUD_DACDAT
	);
endmodule