data/full_repos/permissive/122811248/Question2.v
data/verilator_xmls/2e331625-78f7-4b91-a907-934d8a8cc01f.xml
module minority(input a, b, c, output y);

  assign y = ((~a & ~b & ~c) | (~a & ~b & c) | (~a & b & ~c) | (a & ~b & ~c));

endmodule
module minority(input a, b, c, output y);


  assign y = ((~a & ~b & ~c) | (~a & ~b & c) | (~a & b & ~c) | (a & ~b & ~c));

endmodule