data/full_repos/permissive/135295301/common/ip/oled_pc/sim/patgen.v
data/verilator_xmls/39e2f993-286f-4ca9-a07e-22b171b4d830.xml
module shift_pattern_generator #(
    parameter C_PATTERN_W = 64
  ) (
    input wire clk,
    input wire rst_n,
    output reg [C_PATTERN_W - 1 : 0] pattern
  );


  always @(posedge clk, negedge rst_n) begin
    if (rst_n == 1'b0 || pattern == 'd0) pattern <= 'd1;
    else                                 pattern <= (pattern << 1);
  end

endmodule
module shift_pattern_generator #(
    parameter C_PATTERN_W = 64
  ) (
    input wire clk,
    input wire rst_n,
    output reg [C_PATTERN_W - 1 : 0] pattern
  );



  always @(posedge clk, negedge rst_n) begin
    if (rst_n == 1'b0 || pattern == 'd0) pattern <= 'd1;
    else                                 pattern <= (pattern << 1);
  end

endmodule