data/full_repos/permissive/214278225/3_stateMachine/debounce/state.v
 line:21: before: "="
1: b"%Error: data/full_repos/permissive/214278225/3_stateMachine/debounce/state.v:18: Cannot find file containing module: 'debounce'\ndebounce db(btn,clk,validClean,rst);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214278225/3_stateMachine/debounce,data/full_repos/permissive/214278225/debounce\n             data/full_repos/permissive/214278225/3_stateMachine/debounce,data/full_repos/permissive/214278225/debounce.v\n             data/full_repos/permissive/214278225/3_stateMachine/debounce,data/full_repos/permissive/214278225/debounce.sv\n             debounce\n             debounce.v\n             debounce.sv\n             obj_dir/debounce\n             obj_dir/debounce.v\n             obj_dir/debounce.sv\n%Error: Exiting due to 1 error(s)\n"
module state_machine(btn, clk, ledOut, rst);
input btn, clk, rst;
output reg [2:0] ledOut;

reg [2:0] ledOutNxt;






wire dbBtn;
wire validClean;
reg validReg;
assign dbBtn = validClean &!validReg;

debounce db(btn,clk,validClean,rst);


reg [1:0] state,stateNxt = 0;

always@(posedge clk) begin

	ledOut  <= #1 ledOutNxt;
	state <= #1 stateNxt;
	validReg   <= #1 validClean;
end
always@(*)begin
	stateNxt = state;
	ledOutNxt = ledOut;
	
	if(rst)begin
		ledOutNxt = 3'b001;
		stateNxt = 0;
	end
	else begin
		case(state)
			0:begin
				if(dbBtn)begin
					stateNxt = state + 1;
					ledOutNxt = 3'b010;
				end 
			end
			1: begin
				if(dbBtn)begin
					stateNxt = state + 1;
					ledOutNxt = 3'b11;
				end 
			end
			2: begin
				if(dbBtn)begin
					stateNxt = state + 1;
					ledOutNxt = 3'b100;
				end 
			end
			3: begin
				if(dbBtn)begin
					stateNxt = 0;
					ledOutNxt = 3'b001;
				end 
			end
		endcase
	end
end
		
endmodule
module state_machine(btn, clk, ledOut, rst);

input btn, clk, rst;
output reg [2:0] ledOut;

reg [2:0] ledOutNxt;






wire dbBtn;
wire validClean;
reg validReg;
assign dbBtn = validClean &!validReg;

debounce db(btn,clk,validClean,rst);


reg [1:0] state,stateNxt = 0;

always@(posedge clk) begin

	ledOut  <= #1 ledOutNxt;
	state <= #1 stateNxt;
	validReg   <= #1 validClean;
end
always@(*)begin
	stateNxt = state;
	ledOutNxt = ledOut;
	
	if(rst)begin
		ledOutNxt = 3'b001;
		stateNxt = 0;
	end
	else begin
		case(state)
			0:begin
				if(dbBtn)begin
					stateNxt = state + 1;
					ledOutNxt = 3'b010;
				end 
			end
			1: begin
				if(dbBtn)begin
					stateNxt = state + 1;
					ledOutNxt = 3'b11;
				end 
			end
			2: begin
				if(dbBtn)begin
					stateNxt = state + 1;
					ledOutNxt = 3'b100;
				end 
			end
			3: begin
				if(dbBtn)begin
					stateNxt = 0;
					ledOutNxt = 3'b001;
				end 
			end
		endcase
	end
end
		
endmodule