data/full_repos/permissive/128100618/SV/fp_ops_modified_unused.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/128100618/SV/fp_ops_modified_unused.v:43: Multiple top level modules\n                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                      : ... Top module \'fp2int\'\nmodule fp2int(int_out, fp_in) ;\n       ^~~~~~\n                                                                                      : ... Top module \'fp2int_pos\'\nmodule fp2int_pos(\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/fp_ops_modified_unused.v:55: Operator ASSIGNW expects 54 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 24 bits.\n                                                                                   : ... In instance fp2int_pos\n    wire [53:0] mantissa = {1\'b1,binaryfraction};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/fp_ops_modified_unused.v:64: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 8 bits.\n                                                                                   : ... In instance fp2int_pos\n                cnt <= 23 - (exponent - 8\'d127);  \n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/fp_ops_modified_unused.v:65: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 55 bits.\n                                                                                   : ... In instance fp2int_pos\n                {vout,round} <= {mantissa,1\'b0};\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/fp_ops_modified_unused.v:24: Operator SHIFTR expects 10 bits on the LHS, but LHS\'s VARREF \'m_in\' generates 9 bits.\n                                                                                   : ... In instance fp2int\n assign abs_int = (e_in>8\'h80)? (m_in >> (8\'h89 - e_in)) : 10\'d0 ;\n                                      ^~\n%Error: Exiting due to 5 warning(s)\n'
module fp2int(int_out, fp_in) ;
	output signed  [9:0] int_out ;
	input wire [31:0] fp_in ; 
	
	wire [9:0] abs_int ;
	wire sign ;
	wire [8:0] m_in ;
	wire [7:0] e_in ;
	

	
	assign sign = (m_in[8])? fp_in[31] : 1'h0 ;
	assign m_in = fp_in[22:14] ;
	assign e_in = fp_in[30:23] ;

	assign abs_int = (e_in>8'h80)? (m_in >> (8'h89 - e_in)) : 10'd0 ;

	
	assign int_out = (sign? (~abs_int)+10'd1 : abs_int)  ;

endmodule
module fp2int(int_out, fp_in) ;

	output signed  [9:0] int_out ;
	input wire [31:0] fp_in ; 
	
	wire [9:0] abs_int ;
	wire sign ;
	wire [8:0] m_in ;
	wire [7:0] e_in ;
	

	
	assign sign = (m_in[8])? fp_in[31] : 1'h0 ;
	assign m_in = fp_in[22:14] ;
	assign e_in = fp_in[30:23] ;

	assign abs_int = (e_in>8'h80)? (m_in >> (8'h89 - e_in)) : 10'd0 ;

	
	assign int_out = (sign? (~abs_int)+10'd1 : abs_int)  ;

endmodule