data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new/dataMemory_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new/dataMemory_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2) Clk = 1\'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new/dataMemory_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new/dataMemory_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #185;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new/dataMemory_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new/dataMemory_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #185;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new/dataMemory_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #80\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new/dataMemory_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #80;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new/dataMemory_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #80;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new/dataMemory_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #80;\n    ^\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new/dataMemory_tb.v:33: Cannot find file containing module: \'dataMemory\'\n    dataMemory u0( \n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new,data/full_repos/permissive/194376374/dataMemory\n             data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new,data/full_repos/permissive/194376374/dataMemory.v\n             data/full_repos/permissive/194376374/0521_LJX_lab4/0521_LJX_lab0402/lab0402.srcs/sim_1/new,data/full_repos/permissive/194376374/dataMemory.sv\n             dataMemory\n             dataMemory.v\n             dataMemory.sv\n             obj_dir/dataMemory\n             obj_dir/dataMemory.v\n             obj_dir/dataMemory.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dataMemory_tb(    );

    reg Clk;
    
    reg [31:0] address;
    reg [31:0] writeData;
    reg memWrite;
    reg memRead;
    wire [31:0] readData;

    dataMemory u0( 
        .Clk(Clk),
        .address(address),
        .writeData(writeData),
        .memWrite(memWrite),
        .memRead(memRead),
        .readData(readData)
    );

    parameter PERIOD = 200;

    always begin
        Clk = 1'b0;
        #(PERIOD/2) Clk = 1'b1;
        #(PERIOD/2);
    end

    initial begin
    
    address=0;
    writeData=0;
    memWrite=0;
    memRead=0;

        

    #185;
    memWrite=1'b1;
    address=32'h00000007;
    writeData=32'hE0000000;
    

    #100;
    memWrite=1'b1;
    address=32'h00000006;    
    writeData=32'hffffffff;
   

    #185;
    memRead=1;
    memWrite=1;
    

    #80
    memRead=0;
    memWrite=1'b1;
    address=32'h00000008;    
    writeData=32'haaaaaaaa;   


    #80;
    memRead=1;
    memWrite=0;
    

    #80;
    address=32'h00000006;    
       

    #80;
    memWrite=1;
    writeData=32'h00000000;
    
    end

endmodule
module dataMemory_tb(    );


    reg Clk;
    
    reg [31:0] address;
    reg [31:0] writeData;
    reg memWrite;
    reg memRead;
    wire [31:0] readData;

    dataMemory u0( 
        .Clk(Clk),
        .address(address),
        .writeData(writeData),
        .memWrite(memWrite),
        .memRead(memRead),
        .readData(readData)
    );

    parameter PERIOD = 200;

    always begin
        Clk = 1'b0;
        #(PERIOD/2) Clk = 1'b1;
        #(PERIOD/2);
    end

    initial begin
    
    address=0;
    writeData=0;
    memWrite=0;
    memRead=0;

        

    #185;
    memWrite=1'b1;
    address=32'h00000007;
    writeData=32'hE0000000;
    

    #100;
    memWrite=1'b1;
    address=32'h00000006;    
    writeData=32'hffffffff;
   

    #185;
    memRead=1;
    memWrite=1;
    

    #80
    memRead=0;
    memWrite=1'b1;
    address=32'h00000008;    
    writeData=32'haaaaaaaa;   


    #80;
    memRead=1;
    memWrite=0;
    

    #80;
    address=32'h00000006;    
       

    #80;
    memWrite=1;
    writeData=32'h00000000;
    
    end

endmodule