data/full_repos/permissive/140493787/src/hdl/lfsr.v
 line:64: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/140493787/src/hdl/lfsr.v:58: Unsupported: Ignoring delay on this delayed statement.\n      forever #(CLK_PER / 2) clk <= ~clk;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:62: syntax error, unexpected \'@\'\n      reset <= 1; seed <= 32\'hAAAA_CCCC; @(posedge clk);\n                                         ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:63: syntax error, unexpected \'@\'\n      reset <= 0; enable <= 1;           @(posedge clk);\n                                         ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:64: syntax error, unexpected \'@\'\n      repeat(24)                         @(posedge clk);\n                                         ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:65: syntax error, unexpected \'@\'\n                  enable <= 0;           @(posedge clk);\n                                         ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:66: syntax error, unexpected \'@\'\n      repeat(3)                          @(posedge clk);\n                                         ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:67: syntax error, unexpected \'@\'\n                  enable <= 1;           @(posedge clk);\n                                         ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:68: syntax error, unexpected \'@\'\n      repeat(3)                          @(posedge clk);\n                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/140493787/src/hdl/lfsr.v:89: Unsupported: Ignoring delay on this delayed statement.\n      forever #(CLK_PER / 2) clk <= ~clk;\n              ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:93: syntax error, unexpected \'@\'\n      reset <= 1; seed <= 18\'h0_AACC; @(posedge clk);\n                                      ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:94: syntax error, unexpected \'@\'\n      reset <= 0; enable <= 1;        @(posedge clk);\n                                      ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:95: syntax error, unexpected \'@\'\n      repeat(24)                      @(posedge clk);\n                                      ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:96: syntax error, unexpected \'@\'\n                  enable <= 0;        @(posedge clk);\n                                      ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:97: syntax error, unexpected \'@\'\n      repeat(3)                       @(posedge clk);\n                                      ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:98: syntax error, unexpected \'@\'\n                  enable <= 1;        @(posedge clk);\n                                      ^\n%Error: data/full_repos/permissive/140493787/src/hdl/lfsr.v:99: syntax error, unexpected \'@\'\n      repeat(3)                       @(posedge clk);\n                                      ^\n%Error: Exiting due to 14 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lfsr_18 (
   output reg  [17:0] q,
   input  wire [17:0] seed,
   input  wire        enable,
   input  wire        clk,
   input  wire        reset
);

   wire [17:0] nextRand;
   xnor xn0 (nextRand[0], q[17], q[10]);
   assign nextRand[17:1] = q[16:0];
   always @ (posedge clk) begin
      if (reset)       q <= seed;
      else if (enable) q <= nextRand;
   end
endmodule
module lfsr_18 (
   output reg  [17:0] q,
   input  wire [17:0] seed,
   input  wire        enable,
   input  wire        clk,
   input  wire        reset
);


   wire [17:0] nextRand;
   xnor xn0 (nextRand[0], q[17], q[10]);
   assign nextRand[17:1] = q[16:0];
   always @ (posedge clk) begin
      if (reset)       q <= seed;
      else if (enable) q <= nextRand;
   end
endmodule