data/full_repos/permissive/129127690/mem_block.v
data/verilator_xmls/8e15cb56-0693-4877-a380-9af3f26a5ca4.xml
module mem_block
	(input [11:0]da,input [31:0] write_data,input clk,memwrite,memread,
	output reg [31:0] doa);

	reg [31:0] my_memory [0:4095];	
	


	always @(posedge clk) begin

	if (memread == 1'b1) begin
		doa <= my_memory[da];
	end
	end
	
	
	always @(negedge clk) begin
	if (memwrite == 1'b1) begin
		my_memory[da] <= write_data;
	end
	end

endmodule
module mem_block
	(input [11:0]da,input [31:0] write_data,input clk,memwrite,memread,
	output reg [31:0] doa);


	reg [31:0] my_memory [0:4095];	
	


	always @(posedge clk) begin

	if (memread == 1'b1) begin
		doa <= my_memory[da];
	end
	end
	
	
	always @(negedge clk) begin
	if (memwrite == 1'b1) begin
		my_memory[da] <= write_data;
	end
	end

endmodule