data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/lm32_testsys/main.sv
 line:11: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/lm32_testsys/main.sv:8: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk_sys <= ~clk_sys;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/ip_cores/general-cores/testbench/wishbone/lm32_testsys/main.sv:11: syntax error, unexpected \'@\'\n      repeat(3) @(posedge clk_sys);\n                ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg clk_sys  =0;
   reg rst_n    = 0;

   always #5 clk_sys <= ~clk_sys;
   
   initial begin
      repeat(3) @(posedge clk_sys);
      rst_n  = 1;
   end

   
   lm32_test_system
     DUT (
          .clk_sys_i (clk_sys),
          .rst_n_i   (rst_n),
          .gpio_b ()
          );
   
                            

endmodule
module main;


   reg clk_sys  =0;
   reg rst_n    = 0;

   always #5 clk_sys <= ~clk_sys;
   
   initial begin
      repeat(3) @(posedge clk_sys);
      rst_n  = 1;
   end

   
   lm32_test_system
     DUT (
          .clk_sys_i (clk_sys),
          .rst_n_i   (rst_n),
          .gpio_b ()
          );
   
                            

endmodule