data/full_repos/permissive/14593708/data/interstage-buffers/interstage-buffer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/14593708/data/interstage-buffers/interstage-buffer.v:18: Multiple top level modules\n                                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                     : ... Top module \'interstage_buffer_if_id\'\nmodule interstage_buffer_if_id(clock);\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                     : ... Top module \'interstage_buffer_id_ex\'\nmodule interstage_buffer_id_ex(clock);\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                     : ... Top module \'interstage_buffer_ex_mem\'\nmodule interstage_buffer_ex_mem(clock);\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                     : ... Top module \'interstage_buffer_mem_wb\'\nmodule interstage_buffer_mem_wb(clock);\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/14593708/data/interstage-buffers/interstage-buffer.v:1: Input/output/inout declaration not found for port: \'clock\'\nmodule interstage_buffer_if_id(clock);\n                               ^~~~~\n%Error: data/full_repos/permissive/14593708/data/interstage-buffers/interstage-buffer.v:18: Input/output/inout declaration not found for port: \'clock\'\nmodule interstage_buffer_id_ex(clock);\n                               ^~~~~\n%Error: data/full_repos/permissive/14593708/data/interstage-buffers/interstage-buffer.v:32: Input/output/inout declaration not found for port: \'clock\'\nmodule interstage_buffer_ex_mem(clock);\n                                ^~~~~\n%Error: data/full_repos/permissive/14593708/data/interstage-buffers/interstage-buffer.v:43: Input/output/inout declaration not found for port: \'clock\'\nmodule interstage_buffer_mem_wb(clock);\n                                ^~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module interstage_buffer_id_ex(clock);

    register#(4) ex_control_signals_buffer(id_control_signals,
                                           clock,
                                           ex_control_signals);
    register#(4) mem_control_signals_buffer(ex_control_signals,
                                           clock,
                                           mem_control_signals);
    register#(4) wb_control_signals_buffer(mem_control_signals,
                                           clock,
                                           wb_control_signals);

endmodule
module interstage_buffer_id_ex(clock);


    register#(4) ex_control_signals_buffer(id_control_signals,
                                           clock,
                                           ex_control_signals);
    register#(4) mem_control_signals_buffer(ex_control_signals,
                                           clock,
                                           mem_control_signals);
    register#(4) wb_control_signals_buffer(mem_control_signals,
                                           clock,
                                           wb_control_signals);

endmodule