data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf/i_xorpuf.v
1: b"%Error: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf/i_xorpuf.v:34: Cannot find file containing module: 'xor_apuf'\n xor_apuf #(.N(N1),.K(K1)) XAPUF_T(\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf,data/full_repos/permissive/128781882/xor_apuf\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf,data/full_repos/permissive/128781882/xor_apuf.v\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf,data/full_repos/permissive/128781882/xor_apuf.sv\n             xor_apuf\n             xor_apuf.v\n             xor_apuf.sv\n             obj_dir/xor_apuf\n             obj_dir/xor_apuf.v\n             obj_dir/xor_apuf.sv\n%Error: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/xorpuf/i_xorpuf.v:45: Cannot find file containing module: 'xor_apuf'\n xor_apuf #(.N(N2),.K(K2)) XAPUF_B(\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ixor_apuf #(parameter N1=16, N2=N1+1, K1=2, K2=2, POS=N1/2)(
	clk,
	tigSig_t,
	tigSig_b,
	c,
	respReady_t,
	respReady,
	respBitA,
	respBit
	);

	input clk;
	input tigSig_t;
	input tigSig_b;
	input [N1-1:0] c;
	output respReady_t;
	output respReady;
	output [K1+K2-1:0] respBitA;
	output respBit;

	
	wire [N2-1:0] c_b;
	wire [K1-1:0] respBitA_t;
	wire [K2-1:0] respBitA_b;
	
	wire respBit_t;
	   
	assign respBitA = {respBitA_t,respBitA_b}; 
	assign c_b = {c[N1-1:POS+1], respBit_t, c[POS:0]}; 	
	

	(*KEEP_HIERARCHY="TRUE"*)
	xor_apuf #(.N(N1),.K(K1)) XAPUF_T(
	   .clk(clk),
		.tigSignal(tigSig_t),
		.c(c),
		.respReady(respReady_t),
		.respBitA(respBitA_t),
		.respBit(respBit_t)
	);
	

	(*KEEP_HIERARCHY="TRUE"*)
	xor_apuf #(.N(N2),.K(K2)) XAPUF_B(
		.clk(clk),
		.tigSignal(tigSig_b),
		.c(c_b),
		.respReady(respReady),
		.respBitA(respBitA_b),
		.respBit(respBit)
	);
	
		
endmodule
module ixor_apuf #(parameter N1=16, N2=N1+1, K1=2, K2=2, POS=N1/2)(
	clk,
	tigSig_t,
	tigSig_b,
	c,
	respReady_t,
	respReady,
	respBitA,
	respBit
	);


	input clk;
	input tigSig_t;
	input tigSig_b;
	input [N1-1:0] c;
	output respReady_t;
	output respReady;
	output [K1+K2-1:0] respBitA;
	output respBit;

	
	wire [N2-1:0] c_b;
	wire [K1-1:0] respBitA_t;
	wire [K2-1:0] respBitA_b;
	
	wire respBit_t;
	   
	assign respBitA = {respBitA_t,respBitA_b}; 
	assign c_b = {c[N1-1:POS+1], respBit_t, c[POS:0]}; 	
	

	(*KEEP_HIERARCHY="TRUE"*)
	xor_apuf #(.N(N1),.K(K1)) XAPUF_T(
	   .clk(clk),
		.tigSignal(tigSig_t),
		.c(c),
		.respReady(respReady_t),
		.respBitA(respBitA_t),
		.respBit(respBit_t)
	);
	

	(*KEEP_HIERARCHY="TRUE"*)
	xor_apuf #(.N(N2),.K(K2)) XAPUF_B(
		.clk(clk),
		.tigSignal(tigSig_b),
		.c(c_b),
		.respReady(respReady),
		.respBitA(respBitA_b),
		.respBit(respBit)
	);
	
		
endmodule