data/full_repos/permissive/158984095/Homework1/CompresseHW/prob1_6.v
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data/verilator_xmls/8da96748-135e-4ee3-b6b2-309749f85b24.xml
module stage2_3is2 (
input [5:0] in4,
input [5:0] in5,
input [5:0] in6,
output [5:0] cout_stage2,
output [5:0] sum_stage2
);
FullAdder FA6 (in4[0],in5[0],in6[0],sum_stage2[0],cout_stage2[0]);
FullAdder FA7 (in4[1],in5[1],in6[1],sum_stage2[1],cout_stage2[1]);
FullAdder FA8 (in4[2],in5[2],in6[2],sum_stage2[2],cout_stage2[2]);
FullAdder FA9 (in4[3],in5[3],in6[3],sum_stage2[3],cout_stage2[3]);
FullAdder FA22 (in4[4],in5[4],in6[4],sum_stage2[4],cout_stage2[4]);
FullAdder FA23 (in4[5],in5[5],in6[5],sum_stage2[5],cout_stage2[5]);
endmodule
module stage2_3is2 (
input [5:0] in4,
input [5:0] in5,
input [5:0] in6,
output [5:0] cout_stage2,
output [5:0] sum_stage2
);

FullAdder FA6 (in4[0],in5[0],in6[0],sum_stage2[0],cout_stage2[0]);
FullAdder FA7 (in4[1],in5[1],in6[1],sum_stage2[1],cout_stage2[1]);
FullAdder FA8 (in4[2],in5[2],in6[2],sum_stage2[2],cout_stage2[2]);
FullAdder FA9 (in4[3],in5[3],in6[3],sum_stage2[3],cout_stage2[3]);
FullAdder FA22 (in4[4],in5[4],in6[4],sum_stage2[4],cout_stage2[4]);
FullAdder FA23 (in4[5],in5[5],in6[5],sum_stage2[5],cout_stage2[5]);
endmodule