data/full_repos/permissive/143278/ivltests/defparam3.5.v
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1: b'%Error: data/full_repos/permissive/143278/ivltests/defparam3.5.v:60: syntax error, unexpected \'.\', expecting \'=\'\ndefparam NameB.testmodA.ident0 = 5\'h4;\n                       ^\n%Error: data/full_repos/permissive/143278/ivltests/defparam3.5.v:61: syntax error, unexpected \'.\', expecting \'=\'\ndefparam NameB.testmodB.ident0 = 5\'h5;\n                       ^\n%Error: data/full_repos/permissive/143278/ivltests/defparam3.5.v:62: syntax error, unexpected \'.\', expecting \'=\'\ndefparam NameB.testmodB.ident1 = 5\'h6;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/defparam3.5.v:71: Unsupported: Ignoring delay on this delayed statement.\n     #1 ;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/defparam3.5.v:73: Unsupported: Ignoring delay on this delayed statement.\n     #1 ;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/defparam3.5.v:80: Unsupported: Ignoring delay on this delayed statement.\n     #1 ;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/defparam3.5.v:82: Unsupported: Ignoring delay on this delayed statement.\n     #1 ;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/defparam3.5.v:88: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/defparam3.5.v:90: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/defparam3.5.v:101: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/defparam3.5.v:103: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Error: Exiting due to 3 error(s), 8 warning(s)\n'
module main ();

reg        in0,in1;
reg	   error;
wire [5:0] out0,out1;

defparam NameB.testmodA.ident0 = 5'h4;
defparam NameB.testmodB.ident0 = 5'h5;
defparam NameB.testmodB.ident1 = 5'h6;

module_b NameB (.out0(out0),.out1(out1),
                .in0(in0),.in1(in1));


initial
  begin
     error = 0;
     #1 ;
     in0 = 0;
     #1 ;
     if(out0 != 5'h11)
       begin
          $display("FAILED - defparam3.5A - Defparam testmodA.ident0");
          $display("out0 = %h",out0);
          error = 1;
       end
     #1 ;
     in0 = 1;
     #1 ;
     if(out0 != 5'h4)
       begin
          $display("FAILED - defparam3.5A - Defparam testmodA.ident0");
          error = 1;
       end
     #1;
     in1 = 0;
     #1;
     if(out0 != 5'h4)
       begin
          $display("FAILED - defparam3.5A - Defparam testmodA.ident0");
          error = 1;
       end
     if(out1 != 5'h6)
       begin
          $display("FAILED - defparam3.5A - Defparam testmodB.ident1");
          error = 1;
       end
     #1;
     in1 = 1;
     #1;
     if(out1 != 5'h5)
       begin
          $display("FAILED - defparam3.5A - Defparam testmodB.ident0");
          error = 1;
       end


     if(error == 0)
       $display("PASSED");
  end
endmodule
module main ();


reg        in0,in1;
reg	   error;
wire [5:0] out0,out1;

defparam NameB.testmodA.ident0 = 5'h4;
defparam NameB.testmodB.ident0 = 5'h5;
defparam NameB.testmodB.ident1 = 5'h6;

module_b NameB (.out0(out0),.out1(out1),
                .in0(in0),.in1(in1));


initial
  begin
     error = 0;
     #1 ;
     in0 = 0;
     #1 ;
     if(out0 != 5'h11)
       begin
          $display("FAILED - defparam3.5A - Defparam testmodA.ident0");
          $display("out0 = %h",out0);
          error = 1;
       end
     #1 ;
     in0 = 1;
     #1 ;
     if(out0 != 5'h4)
       begin
          $display("FAILED - defparam3.5A - Defparam testmodA.ident0");
          error = 1;
       end
     #1;
     in1 = 0;
     #1;
     if(out0 != 5'h4)
       begin
          $display("FAILED - defparam3.5A - Defparam testmodA.ident0");
          error = 1;
       end
     if(out1 != 5'h6)
       begin
          $display("FAILED - defparam3.5A - Defparam testmodB.ident1");
          error = 1;
       end
     #1;
     in1 = 1;
     #1;
     if(out1 != 5'h5)
       begin
          $display("FAILED - defparam3.5A - Defparam testmodB.ident0");
          error = 1;
       end


     if(error == 0)
       $display("PASSED");
  end
endmodule