data/full_repos/permissive/143278/ivltests/pr1072.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1072.v:12: Unsupported: Ignoring delay on this delayed statement.\n      #1 bar = { 1<<WIDTH {1\'b1}};\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1072.v:8: Operator ASSIGNW expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                     : ... In instance main\n   wire [19:0] foo = { 1<<WIDTH {1\'b1}};\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1072.v:12: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                      : ... In instance main\n      #1 bar = { 1<<WIDTH {1\'b1}};\n             ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   parameter WIDTH = 4;

   wire [19:0] foo = { 1<<WIDTH {1'b1}};
   reg [19:0]  bar;

   initial begin
      #1 bar = { 1<<WIDTH {1'b1}};

      if (foo !== 20'h0ffff) begin
	 $display("FAILED -- foo = %b", foo);
	 $finish;
      end

      if (bar !== 20'h0ffff) begin
	 $display("FAILED -- bar = %b", bar);
	 $finish;
      end

      if (foo !== bar) begin
	 $display("FAILED -- foo !== bar (%h !== %h)", foo, bar);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   parameter WIDTH = 4;

   wire [19:0] foo = { 1<<WIDTH {1'b1}};
   reg [19:0]  bar;

   initial begin
      #1 bar = { 1<<WIDTH {1'b1}};

      if (foo !== 20'h0ffff) begin
	 $display("FAILED -- foo = %b", foo);
	 $finish;
      end

      if (bar !== 20'h0ffff) begin
	 $display("FAILED -- bar = %b", bar);
	 $finish;
      end

      if (foo !== bar) begin
	 $display("FAILED -- foo !== bar (%h !== %h)", foo, bar);
	 $finish;
      end

      $display("PASSED");
   end

endmodule