data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/control_unit.v
1: b"%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/control_unit.v:41: Cannot find file containing module: 'main_decoder'\n    main_decoder md(op, mem2reg, memwrite, branch, alusrca, alusrcb,regdst, regwrite, jump,aluop, extend,funct);\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/main_decoder\n             data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/main_decoder.v\n             data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/main_decoder.sv\n             main_decoder\n             main_decoder.v\n             main_decoder.sv\n             obj_dir/main_decoder\n             obj_dir/main_decoder.v\n             obj_dir/main_decoder.sv\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/control_unit.v:42: Cannot find file containing module: 'alu_decoder'\n    alu_decoder ad(funct, aluop, alucont);   \n    ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module control_unit(
    input [5:0] op, funct,
    input zero,
    output mem2reg,memwrite,
    output reg pcsrc,
    output [1:0] alusrca,
    output [1:0] alusrcb,
    output [1:0] regdst,
    output regwrite,
    output jump,
    output [3:0] alucont,
    output extend,
    output [15:0] discu
    );
    
    wire [2:0] aluop;
    wire branch;
    
    main_decoder md(op, mem2reg, memwrite, branch, alusrca, alusrcb,regdst, regwrite, jump,aluop, extend,funct);
    alu_decoder ad(funct, aluop, alucont);   
    
    always@(op, branch, zero)
    if(op==6'b000101)
        pcsrc<=branch&(~zero);
    else
        pcsrc<=branch&zero;
        

    assign discu={regwrite, regdst, alusrca,alusrcb, branch, memwrite, mem2reg, jump,extend,alucont};
                  
endmodule
module control_unit(
    input [5:0] op, funct,
    input zero,
    output mem2reg,memwrite,
    output reg pcsrc,
    output [1:0] alusrca,
    output [1:0] alusrcb,
    output [1:0] regdst,
    output regwrite,
    output jump,
    output [3:0] alucont,
    output extend,
    output [15:0] discu
    );

    
    wire [2:0] aluop;
    wire branch;
    
    main_decoder md(op, mem2reg, memwrite, branch, alusrca, alusrcb,regdst, regwrite, jump,aluop, extend,funct);
    alu_decoder ad(funct, aluop, alucont);   
    
    always@(op, branch, zero)
    if(op==6'b000101)
        pcsrc<=branch&(~zero);
    else
        pcsrc<=branch&zero;
        

    assign discu={regwrite, regdst, alusrca,alusrcb, branch, memwrite, mem2reg, jump,extend,alucont};
                  
endmodule