data/full_repos/permissive/117088385/fpga/fpga_tb_top/fpga_tb_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/117088385/fpga/fpga_tb_top/fpga_tb_top.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #15000 ck_rst <=1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117088385/fpga/fpga_tb_top/fpga_tb_top.v:16: Unsupported: Ignoring delay on this delayed statement.\n     #10 CLK100MHZ <= ~CLK100MHZ;\n     ^\n%Error: data/full_repos/permissive/117088385/fpga/fpga_tb_top/fpga_tb_top.v:20: Cannot find file containing module: \'system\'\nsystem u_system\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117088385/fpga/fpga_tb_top,data/full_repos/permissive/117088385/system\n             data/full_repos/permissive/117088385/fpga/fpga_tb_top,data/full_repos/permissive/117088385/system.v\n             data/full_repos/permissive/117088385/fpga/fpga_tb_top,data/full_repos/permissive/117088385/system.sv\n             system\n             system.v\n             system.sv\n             obj_dir/system\n             obj_dir/system.v\n             obj_dir/system.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fpga_tb_top();
  
  reg CLK100MHZ;
  reg ck_rst;

  initial begin
    CLK100MHZ   <=0;
    ck_rst      <=0;
    #15000 ck_rst <=1;
  end

  always
  begin 
     #10 CLK100MHZ <= ~CLK100MHZ;
  end


system u_system
(
  .CLK100MHZ(CLK100MHZ),
  .ck_rst(ck_rst),

  .led_0(),
  .led_1(),
  .led_2(),
  .led_3(),

  .led0_r(),
  .led0_g(),
  .led0_b(),
  .led1_r(),
  .led1_g(),
  .led1_b(),
  .led2_r(),
  .led2_g(),
  .led2_b(),

  .sw_0(),
  .sw_1(),
  .sw_2(),
  .sw_3(),

  .btn_0(),
  .btn_1(),
  .btn_2(),
  .btn_3(),

  .qspi_cs (),
  .qspi_sck(),
  .qspi_dq (),

  .uart_rxd_out(),
  .uart_txd_in (),

  .ja_0(),
  .ja_1(),

  .ck_io(),

  .ck_miso(),
  .ck_mosi(),
  .ck_ss  (),
  .ck_sck (),

  .jd_0(),
  .jd_1(),
  .jd_2(),
  .jd_4(),
  .jd_5(),
  .jd_6()
);


endmodule
module fpga_tb_top();

  
  reg CLK100MHZ;
  reg ck_rst;

  initial begin
    CLK100MHZ   <=0;
    ck_rst      <=0;
    #15000 ck_rst <=1;
  end

  always
  begin 
     #10 CLK100MHZ <= ~CLK100MHZ;
  end


system u_system
(
  .CLK100MHZ(CLK100MHZ),
  .ck_rst(ck_rst),

  .led_0(),
  .led_1(),
  .led_2(),
  .led_3(),

  .led0_r(),
  .led0_g(),
  .led0_b(),
  .led1_r(),
  .led1_g(),
  .led1_b(),
  .led2_r(),
  .led2_g(),
  .led2_b(),

  .sw_0(),
  .sw_1(),
  .sw_2(),
  .sw_3(),

  .btn_0(),
  .btn_1(),
  .btn_2(),
  .btn_3(),

  .qspi_cs (),
  .qspi_sck(),
  .qspi_dq (),

  .uart_rxd_out(),
  .uart_txd_in (),

  .ja_0(),
  .ja_1(),

  .ck_io(),

  .ck_miso(),
  .ck_mosi(),
  .ck_ss  (),
  .ck_sck (),

  .jd_0(),
  .jd_1(),
  .jd_2(),
  .jd_4(),
  .jd_5(),
  .jd_6()
);


endmodule