data/full_repos/permissive/184536406/src/Queue.v
1: b'%Warning-WIDTH: data/full_repos/permissive/184536406/src/Queue.v:21: Bit extraction of array[99:0] requires 7 bit index, not 24 bits.\n                                                                   : ... In instance Queue\n   q[q_in] <= write;\n    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/184536406/src/Queue.v:34: Bit extraction of array[99:0] requires 7 bit index, not 24 bits.\n                                                                   : ... In instance Queue\n   read <= q[q_out];\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module Queue #(parameter msg_bit_width = 24, parameter max_msg = 100) (read, read_en, write_ack, write, write_en, read_ack);
	localparam max_width = 1 << msg_bit_width;
	output reg [msg_bit_width - 1:0] read;
	output reg write_ack;
	output reg read_en;
	input [msg_bit_width - 1:0] write;
	input write_en;
	input read_ack;

	
	reg [msg_bit_width - 1:0] q_in;
	reg [msg_bit_width - 1:0] q_out;
	
	reg [msg_bit_width - 1:0] q [0:max_msg - 1];


	always @(posedge write_en) 
	begin
	if (q_in != q_out)
		begin
			q[q_in] <= write;
			q_in <= (q_in + 1) % max_msg;
			write_ack <= 1'b1;
		end
		else
			write_ack <= 1'b0;
	end
	

	always @(posedge read_ack)
	begin
		if (q_in != q_out)
		begin
			read <= q[q_out];
			q_out <= (q_out + 1) % max_msg;
			read_en <= 1'b1;
		end
		else 
			read_en <= 1'b0;
	end
	
	
endmodule
module Queue #(parameter msg_bit_width = 24, parameter max_msg = 100) (read, read_en, write_ack, write, write_en, read_ack);

	localparam max_width = 1 << msg_bit_width;
	output reg [msg_bit_width - 1:0] read;
	output reg write_ack;
	output reg read_en;
	input [msg_bit_width - 1:0] write;
	input write_en;
	input read_ack;

	
	reg [msg_bit_width - 1:0] q_in;
	reg [msg_bit_width - 1:0] q_out;
	
	reg [msg_bit_width - 1:0] q [0:max_msg - 1];


	always @(posedge write_en) 
	begin
	if (q_in != q_out)
		begin
			q[q_in] <= write;
			q_in <= (q_in + 1) % max_msg;
			write_ack <= 1'b1;
		end
		else
			write_ack <= 1'b0;
	end
	

	always @(posedge read_ack)
	begin
		if (q_in != q_out)
		begin
			read <= q[q_out];
			q_out <= (q_out + 1) % max_msg;
			read_en <= 1'b1;
		end
		else 
			read_en <= 1'b0;
	end
	
	
endmodule