data/full_repos/permissive/364057178/ch_unit/src/bramController.sv
 line:57: before: ":"
1: b"%Error: data/full_repos/permissive/364057178/ch_unit/src/bramController.sv:2: Expecting include filename. Found: SYMBOL\n`include dataSizes.sv \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/364057178/ch_unit/src/bramController.sv:3: Expecting include filename. Found: SYMBOL\n`include dataTypes.sv \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/364057178/ch_unit/src/bramController.sv:2: syntax error, unexpected '.'\n .sv\n ^\n%Error: data/full_repos/permissive/364057178/ch_unit/src/bramController.sv:57: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import dataTypes_pkg::*;\n        ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module bramController
	#(
		parameter integer BRAM_ADDR_SIZE = 15,
		parameter integer BRAM_DATA_SIZE = 32,
		parameter integer BRAM_DEPTH     = 32768
	)
	(

		input clk,
		input resetN,


		input logic advanceBuffer,
		input logic clear,


		input logic [15:0] requestAddr,
		input logic [15:0] numReads,
		output logic [BRAM_DATA_SIZE - 1: 0] requestData,
		output logic dataValid,




		input logic [BRAM_DATA_SIZE - 1: 0] readData,
		input logic resetBusy,
		output logic [BRAM_ADDR_SIZE - 1 : 0] addr,
		output logic [BRAM_DATA_SIZE - 1 : 0] writeData,
		output logic bramEnable,
		output logic bramWe

	);
	import dataTypes_pkg::*;




	typedef enum logic [3:0] {s_init, s_fifoReset, s_req, s_wait[0:3], s_insertInc, s_hold} bramControl_t;




	logic clearFIFO;
	logic read;
	logic wr_en;
	logic rd_rst_busy;
	logic wr_rst_busy;



	bramControl_t currState, nextState;
	logic wrAddr;
	logic wrNumReads;
	logic incAddr;
	logic incI;
	logic [15:0] i;
	logic [15:0] storedReads;




	oneshot readOS(.*, .pulse(advanceBuffer) , .oneshot(read));


	always_comb begin
		clearFIFO = ~clear | ~resetN;
	end


	




	always_ff @(posedge clk) begin

		if(wrAddr) begin
			addr <= requestAddr;
		end
		else begin
			if(incAddr) begin
				addr <= addr + 1;
			end
			else begin
				addr <= addr;
			end
		end

	end


	always_ff @(posedge clk) begin

		if(wrNumReads) begin
			storedReads <= numReads;
		end
		else begin
			storedReads <= storedReads;
		end
	end


	always_ff @(posedge clk) begin

		if(clearFIFO) begin
			i <= 0;
		end
		else begin
			if(incI) begin
				i <= i + 1;
			end
			else begin
				i <= i;
			end
		end

	end





	always_ff @(posedge clk) begin
		if(!resetN || !clear) begin
			currState <= s_init;
		end
		else begin
			currState <= nextState;
		end
	end
	always_comb begin
		unique case(currState)
			s_init:begin
				if(resetN) begin
					nextState = currState.next;
				end
				else begin
					nextState = currState.first;
				end
			end
			s_fifoReset:begin
				if(wr_rst_busy || rd_rst_busy) begin
					nextState = currState;
				end
				else begin
					nextState = currState.next;
				end
			end
			s_req,s_wait0,s_wait1,s_wait2,s_wait3:begin
				nextState = currState.next;
			end
			s_insertInc:begin
				if(i < storedReads) begin
					nextState = s_req;
				end
				else begin
					nextState = s_hold;
				end
			end
			s_hold: begin
				if(clear) begin
					nextState = currState;
				end
				else begin
					nextState = s_fifoReset;
				end
			end
		endcase
	end
	always_comb begin
		unique case(currState)
			s_init: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI}                        = 8'b00110000;
			s_fifoReset: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI}                   = 8'b00000000;
			s_req,s_wait0,s_wait1,s_wait2: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b00000010;
			s_wait3: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI}                       = 8'b00000011;
			s_insertInc: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI}                   = 8'b00001100;
			s_hold: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI}                        = 8'b01110000;
		endcase
	end

	






	xpm_fifo_sync #(
		.DOUT_RESET_VALUE("0"),
		.ECC_MODE("no_ecc"),
		.FIFO_MEMORY_TYPE("distributed"),
		.FIFO_READ_LATENCY(1),
		.FIFO_WRITE_DEPTH(256),
		.FULL_RESET_VALUE(0),
		.READ_DATA_WIDTH(32),
		.READ_MODE("fwft"),
		.SIM_ASSERT_CHK(0),
		.USE_ADV_FEATURES("0000"),
		.WAKEUP_TIME(0),
		.WRITE_DATA_WIDTH(32)
	)
	xpm_fifo_sync_inst (


		.dout(requestData),



		.rd_rst_busy(rd_rst_busy),



		.wr_rst_busy(wr_rst_busy),


		.din(readData),



		.rd_en(read),



		.rst(clearFIFO),




		.wr_clk(clk),


		.wr_en(wr_en)



	);









endmodule
module bramController
	#(
		parameter integer BRAM_ADDR_SIZE = 15,
		parameter integer BRAM_DATA_SIZE = 32,
		parameter integer BRAM_DEPTH     = 32768
	)
	(

		input clk,
		input resetN,


		input logic advanceBuffer,
		input logic clear,


		input logic [15:0] requestAddr,
		input logic [15:0] numReads,
		output logic [BRAM_DATA_SIZE - 1: 0] requestData,
		output logic dataValid,




		input logic [BRAM_DATA_SIZE - 1: 0] readData,
		input logic resetBusy,
		output logic [BRAM_ADDR_SIZE - 1 : 0] addr,
		output logic [BRAM_DATA_SIZE - 1 : 0] writeData,
		output logic bramEnable,
		output logic bramWe

	);

	import dataTypes_pkg::*;




	typedef enum logic [3:0] {s_init, s_fifoReset, s_req, s_wait[0:3], s_insertInc, s_hold} bramControl_t;




	logic clearFIFO;
	logic read;
	logic wr_en;
	logic rd_rst_busy;
	logic wr_rst_busy;



	bramControl_t currState, nextState;
	logic wrAddr;
	logic wrNumReads;
	logic incAddr;
	logic incI;
	logic [15:0] i;
	logic [15:0] storedReads;




	oneshot readOS(.*, .pulse(advanceBuffer) , .oneshot(read));


	always_comb begin
		clearFIFO = ~clear | ~resetN;
	end


	




	always_ff @(posedge clk) begin

		if(wrAddr) begin
			addr <= requestAddr;
		end
		else begin
			if(incAddr) begin
				addr <= addr + 1;
			end
			else begin
				addr <= addr;
			end
		end

	end


	always_ff @(posedge clk) begin

		if(wrNumReads) begin
			storedReads <= numReads;
		end
		else begin
			storedReads <= storedReads;
		end
	end


	always_ff @(posedge clk) begin

		if(clearFIFO) begin
			i <= 0;
		end
		else begin
			if(incI) begin
				i <= i + 1;
			end
			else begin
				i <= i;
			end
		end

	end





	always_ff @(posedge clk) begin
		if(!resetN || !clear) begin
			currState <= s_init;
		end
		else begin
			currState <= nextState;
		end
	end
	always_comb begin
		unique case(currState)
			s_init:begin
				if(resetN) begin
					nextState = currState.next;
				end
				else begin
					nextState = currState.first;
				end
			end
			s_fifoReset:begin
				if(wr_rst_busy || rd_rst_busy) begin
					nextState = currState;
				end
				else begin
					nextState = currState.next;
				end
			end
			s_req,s_wait0,s_wait1,s_wait2,s_wait3:begin
				nextState = currState.next;
			end
			s_insertInc:begin
				if(i < storedReads) begin
					nextState = s_req;
				end
				else begin
					nextState = s_hold;
				end
			end
			s_hold: begin
				if(clear) begin
					nextState = currState;
				end
				else begin
					nextState = s_fifoReset;
				end
			end
		endcase
	end
	always_comb begin
		unique case(currState)
			s_init: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI}                        = 8'b00110000;
			s_fifoReset: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI}                   = 8'b00000000;
			s_req,s_wait0,s_wait1,s_wait2: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI} = 8'b00000010;
			s_wait3: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI}                       = 8'b00000011;
			s_insertInc: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI}                   = 8'b00001100;
			s_hold: {bramWe,dataValid,wrAddr, wrNumReads,incAddr,wr_en,bramEnable,incI}                        = 8'b01110000;
		endcase
	end

	






	xpm_fifo_sync #(
		.DOUT_RESET_VALUE("0"),
		.ECC_MODE("no_ecc"),
		.FIFO_MEMORY_TYPE("distributed"),
		.FIFO_READ_LATENCY(1),
		.FIFO_WRITE_DEPTH(256),
		.FULL_RESET_VALUE(0),
		.READ_DATA_WIDTH(32),
		.READ_MODE("fwft"),
		.SIM_ASSERT_CHK(0),
		.USE_ADV_FEATURES("0000"),
		.WAKEUP_TIME(0),
		.WRITE_DATA_WIDTH(32)
	)
	xpm_fifo_sync_inst (


		.dout(requestData),



		.rd_rst_busy(rd_rst_busy),



		.wr_rst_busy(wr_rst_busy),


		.din(readData),



		.rd_en(read),



		.rst(clearFIFO),




		.wr_clk(clk),


		.wr_en(wr_en)



	);









endmodule