data/full_repos/permissive/159166357/tests/counter.v
1: b"%Error: data/full_repos/permissive/159166357/tests/counter.v:23: Can't find definition of variable: 'mtime'\n                                                               : ... Suggested alternative: 'mtimel'\n        mtime <= mtime + 32'b1;\n                 ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module counter
(
    input wire clk,
    input wire resetb,
    input wire wenl,
    input wire wenh,
    input wire sel,
    input wire [31:0] din,
    output wire cmp,
    output reg [31:0] mtimel,
    output reg [31:0] mtimeh,
    output reg [63:0] mtimecmp
);

wire [31:0] mtimeh1;
assign mtimeh1 = mtimeh + 32'b1;
always @ (posedge clk) begin : MTIME
    if (!resetb) begin
        mtimel <= 64'b0;
        mtimeh <= 64'b0;
    end
    else if (clk) begin
        mtime <= mtime + 32'b1;
        mtimeh <= &{mtime} ? mtimeh1 : mtimeh;
        if (wenl && !sel) begin
            mtimel <= din;
        end
        if (wenh && !sel) begin
            mtimeh <= din;
        end
    end
end

always @ (posedge clk) begin : MTIMECMP
    if (wenl && sel) mtimecmp[0+:32] <= din;
    if (wenh && sel) mtimecmp[32+:32] <= din;
end

  assign cmp = mtime == mtimecmp;
  endmodule
module counter
(
    input wire clk,
    input wire resetb,
    input wire wenl,
    input wire wenh,
    input wire sel,
    input wire [31:0] din,
    output wire cmp,
    output reg [31:0] mtimel,
    output reg [31:0] mtimeh,
    output reg [63:0] mtimecmp
);


wire [31:0] mtimeh1;
assign mtimeh1 = mtimeh + 32'b1;
always @ (posedge clk) begin : MTIME
    if (!resetb) begin
        mtimel <= 64'b0;
        mtimeh <= 64'b0;
    end
    else if (clk) begin
        mtime <= mtime + 32'b1;
        mtimeh <= &{mtime} ? mtimeh1 : mtimeh;
        if (wenl && !sel) begin
            mtimel <= din;
        end
        if (wenh && !sel) begin
            mtimeh <= din;
        end
    end
end

always @ (posedge clk) begin : MTIMECMP
    if (wenl && sel) mtimecmp[0+:32] <= din;
    if (wenh && sel) mtimecmp[32+:32] <= din;
end

  assign cmp = mtime == mtimecmp;
  endmodule