data/full_repos/permissive/157979234/Semester III/Digital Design and Computer Organization/Session 05/my_mods.v
1: b'%Error: Cannot find file containing module: III/Digital\n        ... Looked in:\n             data/full_repos/permissive/157979234/Semester/III/Digital\n             data/full_repos/permissive/157979234/Semester/III/Digital.v\n             data/full_repos/permissive/157979234/Semester/III/Digital.sv\n             III/Digital\n             III/Digital.v\n             III/Digital.sv\n             obj_dir/III/Digital\n             obj_dir/III/Digital.v\n             obj_dir/III/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Organization/Session\n%Error: Cannot find file containing module: 05,data/full_repos/permissive/157979234\n%Error: Cannot find file containing module: data/full_repos/permissive/157979234/Semester\n%Error: Cannot find file containing module: 05/my_mods.v\n%Error: Exiting due to 8 error(s)\n'
module reg16
(
  input wire
  clk,
  reset,
  load,
  input wire [15:0]
  d,
  output wire [15:0]
  q
);

dfrl d0(clk, reset, load, d[0], q[0]);
dfrl d1(clk, reset, load, d[1], q[1]);
dfrl d2(clk, reset, load, d[2], q[2]);
dfrl d3(clk, reset, load, d[3], q[3]);
dfrl d4(clk, reset, load, d[4], q[4]);
dfrl d5(clk, reset, load, d[5], q[5]);
dfrl d6(clk, reset, load, d[6], q[6]);
dfrl d7(clk, reset, load, d[7], q[7]);
dfrl d8(clk, reset, load, d[8], q[8]);
dfrl d9(clk, reset, load, d[9], q[9]);
dfrl d10(clk, reset, load, d[10], q[10]);
dfrl d11(clk, reset, load, d[11], q[11]);
dfrl d12(clk, reset, load, d[12], q[12]);
dfrl d13(clk, reset, load, d[13], q[13]);
dfrl d14(clk, reset, load, d[14], q[14]);
dfrl d15(clk, reset, load, d[15], q[15]);

endmodule
module reg16
(
  input wire
  clk,
  reset,
  load,
  input wire [15:0]
  d,
  output wire [15:0]
  q
);


dfrl d0(clk, reset, load, d[0], q[0]);
dfrl d1(clk, reset, load, d[1], q[1]);
dfrl d2(clk, reset, load, d[2], q[2]);
dfrl d3(clk, reset, load, d[3], q[3]);
dfrl d4(clk, reset, load, d[4], q[4]);
dfrl d5(clk, reset, load, d[5], q[5]);
dfrl d6(clk, reset, load, d[6], q[6]);
dfrl d7(clk, reset, load, d[7], q[7]);
dfrl d8(clk, reset, load, d[8], q[8]);
dfrl d9(clk, reset, load, d[9], q[9]);
dfrl d10(clk, reset, load, d[10], q[10]);
dfrl d11(clk, reset, load, d[11], q[11]);
dfrl d12(clk, reset, load, d[12], q[12]);
dfrl d13(clk, reset, load, d[13], q[13]);
dfrl d14(clk, reset, load, d[14], q[14]);
dfrl d15(clk, reset, load, d[15], q[15]);

endmodule