data/full_repos/permissive/179884651/examples/WF_audio_demo.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:55: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:57: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:63: Signal definition not found, creating implicitly: \'ten_ms\'\n                                                                                   : ... Suggested alternative: \'ten_us\'\n           .timer_pulse(ten_ms));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:69: Signal definition not found, creating implicitly: \'quarter_second\'\n           .timer_pulse(quarter_second));\n                        ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:78: Signal definition not found, creating implicitly: \'switch_pushed\'\n      .switch_pushed(switch_pushed),     \n                     ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:108: Signal definition not found, creating implicitly: \'sclk_fall\'\n  assign sclk_fall = sclk_d && ~SCK;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:48: Cannot find file containing module: \'SB_HFOSC\'\n  SB_HFOSC OSC_i (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.v\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_HFOSC.sv\n             SB_HFOSC\n             SB_HFOSC.v\n             SB_HFOSC.sv\n             obj_dir/SB_HFOSC\n             obj_dir/SB_HFOSC.v\n             obj_dir/SB_HFOSC.sv\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:214: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h1 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:216: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h3 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:219: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h6 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:220: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h7 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:222: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'h9 : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:223: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'ha : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:224: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'none\' generates 4 bits.\n                                                                                 : ... In instance fpga_top\n       4\'hb : note = none;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_audio_demo.v:244: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                                 : ... In instance fpga_top\n    assign sinlut = sine[phase_acc[15:8]];\n                  ^\n%Error: Exiting due to 1 error(s), 14 warning(s)\n'
module WF_i2s_pulses(
    input clk,
    output reg mclk_pulse,
    output reg lrck_pulse,
    output reg sclk_pulse
);










reg [7:0] mclk_cnt;
reg [9:0] lrck_cnt;
reg [7:0] sclk_cnt;


parameter MCLK_MAX = 1;
parameter LRCK_MAX = 511;
parameter SCLK_MAX = 7;


  always @(posedge clk)

    if (mclk_cnt < MCLK_MAX)
      begin
        mclk_pulse <= 0;
        mclk_cnt   <= mclk_cnt + 1;
      end
    else
      begin
        mclk_pulse <= 1;
        mclk_cnt   <= 0;
      end

  always @(posedge clk)
    if (lrck_cnt < LRCK_MAX)
      begin
        lrck_cnt <= lrck_cnt + 1;
        lrck_pulse <= 0;
      end
    else
      begin
        lrck_pulse <= 1;
        lrck_cnt <= 0;
      end


  always @(posedge clk)
    if (sclk_cnt < SCLK_MAX)
      begin
        sclk_pulse <= 0;
        sclk_cnt <= sclk_cnt + 1;
      end
    else
      begin
        sclk_pulse <= 1;
        sclk_cnt <= 0;
      end

endmodule
module WF_i2s_pulses(
    input clk,
    output reg mclk_pulse,
    output reg lrck_pulse,
    output reg sclk_pulse
);











reg [7:0] mclk_cnt;
reg [9:0] lrck_cnt;
reg [7:0] sclk_cnt;


parameter MCLK_MAX = 1;
parameter LRCK_MAX = 511;
parameter SCLK_MAX = 7;


  always @(posedge clk)

    if (mclk_cnt < MCLK_MAX)
      begin
        mclk_pulse <= 0;
        mclk_cnt   <= mclk_cnt + 1;
      end
    else
      begin
        mclk_pulse <= 1;
        mclk_cnt   <= 0;
      end

  always @(posedge clk)
    if (lrck_cnt < LRCK_MAX)
      begin
        lrck_cnt <= lrck_cnt + 1;
        lrck_pulse <= 0;
      end
    else
      begin
        lrck_pulse <= 1;
        lrck_cnt <= 0;
      end


  always @(posedge clk)
    if (sclk_cnt < SCLK_MAX)
      begin
        sclk_pulse <= 0;
        sclk_cnt <= sclk_cnt + 1;
      end
    else
      begin
        sclk_pulse <= 1;
        sclk_cnt <= 0;
      end

endmodule