data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:12: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h773593f\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b0000: max_count <= 27\'d124999999;  \n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:13: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h3b9ac9f\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b0001: max_count <= 27\'d62499999;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:14: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'hbebc1f\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b0010: max_count <= 27\'d12499999;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:15: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h5f5e0f\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b0011: max_count <= 27\'d6249999;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:16: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h26259f\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b0100: max_count <= 27\'d2499999;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:17: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h1312cf\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b0101: max_count <= 27\'d1249999;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:18: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h98967\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b0110: max_count <= 27\'d624999;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:19: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h3d08f\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b0111: max_count <= 27\'d249999;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:20: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h1e847\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b1000: max_count <= 27\'d124999;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:21: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'hf423\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b1001: max_count <= 27\'d62499;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:22: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h61a7\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b1010: max_count <= 27\'d24999;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:23: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h30d3\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b1011: max_count <= 27\'d12499;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:24: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h1869\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b1100: max_count <= 27\'d6249;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:25: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h9c3\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b1101: max_count <= 27\'d2499;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:26: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h4e1\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   4\'b1110: max_count <= 27\'d1249;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:27: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h1e\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n   default: max_count <= 27\'d30;  \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/max_count_gen.v:31: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h1e\' generates 27 bits.\n                                                                                                   : ... In instance max_count_gen\n  max_count <= 27\'d30;\n            ^~\n%Error: Exiting due to 17 warning(s)\n'
module max_count_gen (
	input wire [7:0] switches,
	output reg [27:0] max_count,
	output wire [15:0] segment_num_max,
	output wire [7:0] redundancy
);

reg [16:0] max_counter_samepacket = 17'd50;
always @(switches) begin
	if (switches[3:0] != 4'b0000) begin
		case (switches[3:0])
			4'b0000:	max_count <= 27'd124999999;
			4'b0001:	max_count <= 27'd62499999;
			4'b0010:	max_count <= 27'd12499999;
			4'b0011:	max_count <= 27'd6249999;
			4'b0100:	max_count <= 27'd2499999;
			4'b0101:	max_count <= 27'd1249999;
			4'b0110:	max_count <= 27'd624999;
			4'b0111:	max_count <= 27'd249999;
			4'b1000:	max_count <= 27'd124999;
			4'b1001:	max_count <= 27'd62499;
			4'b1010:	max_count <= 27'd24999;
			4'b1011:	max_count <= 27'd12499;
			4'b1100:	max_count <= 27'd6249;
			4'b1101:	max_count <= 27'd2499;
			4'b1110:	max_count <= 27'd1249;
			default:	max_count <= 27'd30;
		endcase
	end
	else begin
		max_count <= 27'd30;
	end

end

assign segment_num_max = (switches[7:6] == 2'b00) ? 1:
															switches[7:6] == 2'b01 ? 3:
															switches[7:6] == 2'b10 ? 100:
															switches[7:6] == 2'b11 ? 150 : 1;
assign redundancy = switches[5:4] == 2'b00 ? 1:
												switches[5:4] == 2'b01 ? 3:
												switches[5:4] == 2'b10 ? 5:
												switches[5:4] == 2'b11 ? 7 : 1;

endmodule
module max_count_gen (
	input wire [7:0] switches,
	output reg [27:0] max_count,
	output wire [15:0] segment_num_max,
	output wire [7:0] redundancy
);


reg [16:0] max_counter_samepacket = 17'd50;
always @(switches) begin
	if (switches[3:0] != 4'b0000) begin
		case (switches[3:0])
			4'b0000:	max_count <= 27'd124999999;
			4'b0001:	max_count <= 27'd62499999;
			4'b0010:	max_count <= 27'd12499999;
			4'b0011:	max_count <= 27'd6249999;
			4'b0100:	max_count <= 27'd2499999;
			4'b0101:	max_count <= 27'd1249999;
			4'b0110:	max_count <= 27'd624999;
			4'b0111:	max_count <= 27'd249999;
			4'b1000:	max_count <= 27'd124999;
			4'b1001:	max_count <= 27'd62499;
			4'b1010:	max_count <= 27'd24999;
			4'b1011:	max_count <= 27'd12499;
			4'b1100:	max_count <= 27'd6249;
			4'b1101:	max_count <= 27'd2499;
			4'b1110:	max_count <= 27'd1249;
			default:	max_count <= 27'd30;
		endcase
	end
	else begin
		max_count <= 27'd30;
	end

end

assign segment_num_max = (switches[7:6] == 2'b00) ? 1:
															switches[7:6] == 2'b01 ? 3:
															switches[7:6] == 2'b10 ? 100:
															switches[7:6] == 2'b11 ? 150 : 1;
assign redundancy = switches[5:4] == 2'b00 ? 1:
												switches[5:4] == 2'b01 ? 3:
												switches[5:4] == 2'b10 ? 5:
												switches[5:4] == 2'b11 ? 7 : 1;

endmodule