data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v
 line:60: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:28: Unsupported: Ignoring delay on this delayed statement.\n #0 PC <= 16\'hFFFF;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:29: Unsupported: Ignoring delay on this delayed statement.\n #0 D_ReadReg1RT <= 16\'hEEEE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:30: Unsupported: Ignoring delay on this delayed statement.\n #0 D_BT <= 16\'hDDDD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:31: Unsupported: Ignoring delay on this delayed statement.\n #0 D_Offset <= 16\'hCCCC;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:32: Unsupported: Ignoring delay on this delayed statement.\n #0 D_ReadReg2RT <= 16\'hBBBB;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:33: Unsupported: Ignoring delay on this delayed statement.\n #0 D_RegSW <= 16\'hAAAA;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:34: Unsupported: Ignoring delay on this delayed statement.\n #0 D_JUMP_SE_Out <= 16\'h9999;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:35: Unsupported: Ignoring delay on this delayed statement.\n #0 D_SE_Out <= 16\'h8888;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:36: Unsupported: Ignoring delay on this delayed statement.\n #0 D_USE_Out <= 16\'h7777;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 D_L1S_Out <= 16\'h6666;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:42: Unsupported: Ignoring delay on this delayed statement.\n #000 C_SignExtend = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:43: Unsupported: Ignoring delay on this delayed statement.\n #010 C_SignExtend = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:44: Unsupported: Ignoring delay on this delayed statement.\n #010 C_RegDstRead1R = 2\'b00;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:45: Unsupported: Ignoring delay on this delayed statement.\n #010 C_RegDstRead1R = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:46: Unsupported: Ignoring delay on this delayed statement.\n #010 C_RegDstRead1R = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:47: Unsupported: Ignoring delay on this delayed statement.\n #010 C_RegDstRead1R = 2\'b11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:48: Unsupported: Ignoring delay on this delayed statement.\n #010 C_RegDstRead2R = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:49: Unsupported: Ignoring delay on this delayed statement.\n #010 C_RegDstRead2R = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:50: Unsupported: Ignoring delay on this delayed statement.\n #010 C_ALUSrc_A = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:51: Unsupported: Ignoring delay on this delayed statement.\n #010 C_ALUSrc_A = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:52: Unsupported: Ignoring delay on this delayed statement.\n #010 C_ALUSrc_B = 3\'b000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:53: Unsupported: Ignoring delay on this delayed statement.\n #010 C_ALUSrc_B = 3\'b001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:54: Unsupported: Ignoring delay on this delayed statement.\n #010 C_ALUSrc_B = 3\'b010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:55: Unsupported: Ignoring delay on this delayed statement.\n #010 C_ALUSrc_B = 3\'b011;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:56: Unsupported: Ignoring delay on this delayed statement.\n #010 C_ALUSrc_B = 3\'b100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:57: Unsupported: Ignoring delay on this delayed statement.\n #010 C_ALUSrc_B = 3\'b101;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:58: Unsupported: Ignoring delay on this delayed statement.\n #010 C_ALUSrc_B = 3\'b110;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:59: Unsupported: Ignoring delay on this delayed statement.\n #010 C_ALUSrc_B = 3\'b111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:60: Unsupported: Ignoring delay on this delayed statement.\n #010 $stop;\n ^\n%Error: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:65: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("MUXpreALU.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:66: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/126791278/testbenches/tb_MUXpreALU.v:69: Unsupported or unknown PLI call: $monitor\ninitial $monitor("time=%3d, ALU_1_IN=%16h, ALU_2_IN=%16h", $time, ALU_1_IN, ALU_2_IN);\n        ^~~~~~~~\n%Error: Exiting due to 3 error(s), 29 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_MUXpreALU();

wire [15:0] ALU_1_IN, ALU_2_IN;

reg [15:0] PC;
reg [15:0] D_ReadReg1RT, D_BT, D_Offset;
reg [15:0] D_ReadReg2RT, D_RegSW;
reg [15:0] D_JUMP_SE_Out, D_SE_Out, D_USE_Out, D_L1S_Out;

reg C_SignExtend;
reg [1:0] C_RegDstRead1R;
reg C_RegDstRead2R;
reg C_ALUSrc_A;
reg [2:0] C_ALUSrc_B;

MUXpreALU uut (ALU_1_IN, ALU_2_IN,
				PC,
				D_ReadReg1RT, D_BT, D_Offset,
				D_ReadReg2RT, D_RegSW,
				D_JUMP_SE_Out , D_SE_Out, D_USE_Out, D_L1S_Out, 
				C_SignExtend,
				C_RegDstRead1R, C_RegDstRead2R,
				C_ALUSrc_A, C_ALUSrc_B);

initial
begin
	#0 PC <= 16'hFFFF;
	#0 D_ReadReg1RT <= 16'hEEEE;
	#0 D_BT <= 16'hDDDD;
	#0 D_Offset <= 16'hCCCC;
	#0 D_ReadReg2RT <= 16'hBBBB;
	#0 D_RegSW <= 16'hAAAA;
	#0 D_JUMP_SE_Out <= 16'h9999;
	#0 D_SE_Out <= 16'h8888;
	#0 D_USE_Out <= 16'h7777;
	#0 D_L1S_Out <= 16'h6666;
end

initial
begin
	#000 C_SignExtend = 1'b0;
	#010 C_SignExtend = 1'b1;
	#010 C_RegDstRead1R = 2'b00;
	#010 C_RegDstRead1R = 2'b01;
	#010 C_RegDstRead1R = 2'b10;
	#010 C_RegDstRead1R = 2'b11;
	#010 C_RegDstRead2R = 1'b0;
	#010 C_RegDstRead2R = 1'b1;
	#010 C_ALUSrc_A = 1'b0;
	#010 C_ALUSrc_A = 1'b1;
	#010 C_ALUSrc_B = 3'b000;
	#010 C_ALUSrc_B = 3'b001;
	#010 C_ALUSrc_B = 3'b010;
	#010 C_ALUSrc_B = 3'b011;
	#010 C_ALUSrc_B = 3'b100;
	#010 C_ALUSrc_B = 3'b101;
	#010 C_ALUSrc_B = 3'b110;
	#010 C_ALUSrc_B = 3'b111;
	#010 $stop;
end

initial
begin
	$dumpfile("MUXpreALU.vcd");
	$dumpvars;
end

initial $monitor("time=%3d, ALU_1_IN=%16h, ALU_2_IN=%16h", $time, ALU_1_IN, ALU_2_IN);


endmodule
module tb_MUXpreALU();


wire [15:0] ALU_1_IN, ALU_2_IN;

reg [15:0] PC;
reg [15:0] D_ReadReg1RT, D_BT, D_Offset;
reg [15:0] D_ReadReg2RT, D_RegSW;
reg [15:0] D_JUMP_SE_Out, D_SE_Out, D_USE_Out, D_L1S_Out;

reg C_SignExtend;
reg [1:0] C_RegDstRead1R;
reg C_RegDstRead2R;
reg C_ALUSrc_A;
reg [2:0] C_ALUSrc_B;

MUXpreALU uut (ALU_1_IN, ALU_2_IN,
				PC,
				D_ReadReg1RT, D_BT, D_Offset,
				D_ReadReg2RT, D_RegSW,
				D_JUMP_SE_Out , D_SE_Out, D_USE_Out, D_L1S_Out, 
				C_SignExtend,
				C_RegDstRead1R, C_RegDstRead2R,
				C_ALUSrc_A, C_ALUSrc_B);

initial
begin
	#0 PC <= 16'hFFFF;
	#0 D_ReadReg1RT <= 16'hEEEE;
	#0 D_BT <= 16'hDDDD;
	#0 D_Offset <= 16'hCCCC;
	#0 D_ReadReg2RT <= 16'hBBBB;
	#0 D_RegSW <= 16'hAAAA;
	#0 D_JUMP_SE_Out <= 16'h9999;
	#0 D_SE_Out <= 16'h8888;
	#0 D_USE_Out <= 16'h7777;
	#0 D_L1S_Out <= 16'h6666;
end

initial
begin
	#000 C_SignExtend = 1'b0;
	#010 C_SignExtend = 1'b1;
	#010 C_RegDstRead1R = 2'b00;
	#010 C_RegDstRead1R = 2'b01;
	#010 C_RegDstRead1R = 2'b10;
	#010 C_RegDstRead1R = 2'b11;
	#010 C_RegDstRead2R = 1'b0;
	#010 C_RegDstRead2R = 1'b1;
	#010 C_ALUSrc_A = 1'b0;
	#010 C_ALUSrc_A = 1'b1;
	#010 C_ALUSrc_B = 3'b000;
	#010 C_ALUSrc_B = 3'b001;
	#010 C_ALUSrc_B = 3'b010;
	#010 C_ALUSrc_B = 3'b011;
	#010 C_ALUSrc_B = 3'b100;
	#010 C_ALUSrc_B = 3'b101;
	#010 C_ALUSrc_B = 3'b110;
	#010 C_ALUSrc_B = 3'b111;
	#010 $stop;
end

initial
begin
	$dumpfile("MUXpreALU.vcd");
	$dumpvars;
end

initial $monitor("time=%3d, ALU_1_IN=%16h, ALU_2_IN=%16h", $time, ALU_1_IN, ALU_2_IN);


endmodule