data/full_repos/permissive/214823094/tutorials/simulation/lab1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/214823094/tutorials/simulation/lab1_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n            #50 switches=i;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214823094/tutorials/simulation/lab1_tb.v:12: Cannot find file containing module: \'lab1\'\n    lab1 dut(.LED(leds),.SW(switches));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/214823094/tutorials/simulation,data/full_repos/permissive/214823094/lab1\n             data/full_repos/permissive/214823094/tutorials/simulation,data/full_repos/permissive/214823094/lab1.v\n             data/full_repos/permissive/214823094/tutorials/simulation,data/full_repos/permissive/214823094/lab1.sv\n             lab1\n             lab1.v\n             lab1.sv\n             obj_dir/lab1\n             obj_dir/lab1.v\n             obj_dir/lab1.sv\n%Warning-WIDTH: data/full_repos/permissive/214823094/tutorials/simulation/lab1_tb.v:18: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                      : ... In instance lab1_tb\n            #50 switches=i;\n                        ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lab1_tb;
    
    reg [7:0] switches;
    wire [7:0] leds;
        
    integer i;
    
    lab1 dut(.LED(leds),.SW(switches));
     
    initial
    begin
        for (i=0; i < 255; i=i+2)
        begin
            #50 switches=i;
        end
    end
      
endmodule
module lab1_tb;

    
    reg [7:0] switches;
    wire [7:0] leds;
        
    integer i;
    
    lab1 dut(.LED(leds),.SW(switches));
     
    initial
    begin
        for (i=0; i < 255; i=i+2)
        begin
            #50 switches=i;
        end
    end
      
endmodule