data/full_repos/permissive/185824253/rtl/myCPU/IF.v
None: at end of input
1: b'%Error: data/full_repos/permissive/185824253/rtl/myCPU/IF.v:3: Cannot find include file: define.h\n`include "define.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/185824253/rtl/myCPU,data/full_repos/permissive/185824253/define.h\n             data/full_repos/permissive/185824253/rtl/myCPU,data/full_repos/permissive/185824253/define.h.v\n             data/full_repos/permissive/185824253/rtl/myCPU,data/full_repos/permissive/185824253/define.h.sv\n             define.h\n             define.h.v\n             define.h.sv\n             obj_dir/define.h\n             obj_dir/define.h.v\n             obj_dir/define.h.sv\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/IF.v:98: Define or directive not defined: \'`LS132R_EX_ADEL\'\n assign if_excode = {6{if_exc}} & `LS132R_EX_ADEL;\n                                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/185824253/rtl/myCPU/IF.v:98: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n assign if_excode = {6{if_exc}} & `LS132R_EX_ADEL;\n                                                 ^\n%Error: Exiting due to 3 error(s)\n'
module IF(
	input         clk,
	input         resetn,
	input         int_exc,

	input         stop,
	input         load_forward,
	input         j_token,
	input         op_eret,
	input         id_allowin,

	input  [31:0] irom_inst_i,
	input         inst_sram_ok,
	input  [31:0] id_next_pc_i,

	output        if_to_id_valid,
	output        if_id_stage_o,

	output        inst_ren,
	output [31:0] irom_pc_o,
	
	output [31:0] pc_add_4,

	output [31:0] if_pc_o,
	output [31:0] if_pc_add4_o,
	output [31:0] if_inst_o,

	output        if_exc_o,
	output [ 5:0] if_excode_o
);

	wire if_validin;
    assign if_validin = 1'b1;

	wire if_stage;
	assign if_stage = if_validin;

	reg  [31:0] pc;
	wire [31:0] next_pc;

	always @(posedge clk) begin
		if (!resetn)
			pc <= 32'hbfc0_0000;
		else if (int_exc)
			pc <= 32'hbfc00380;
		else if (pc_stall)
			pc <= pc;
		else if (if_stage)
			pc <= next_pc;
	end


	reg int_pc_ok;

	always@(posedge clk)
	begin
		if (!resetn) int_pc_ok <= 1'b1;
		else if (int_exc) int_pc_ok <= 1'b0;
		else if (inst_sram_ok) int_pc_ok <= 1'b1;
	end

	wire [31:0] inst_o;
	wire [31:0] pc_o;

	assign pc_add_4 = pc_o + 3'd4;

	wire pc_stall = stop | load_forward | !inst_sram_ok | !int_pc_ok | !if_allowin;
	wire inst_stall = int_exc | if_exc | op_eret | !inst_sram_ok | (inst_sram_ok & !int_pc_ok);

	assign next_pc = !resetn ? 32'hbfc00000 :
                     j_token ? id_next_pc_i : pc_add_4;


	assign irom_pc_o = pc;
	assign inst_o    = {32{!inst_stall}} & irom_inst_i;
	assign pc_o      = pc;
    assign inst_ren  = if_stage & !int_exc;

    wire if_exc_s;
	assign if_exc_s = (irom_pc_o[1:0] != 2'b00) & if_stage;

	wire if_exc;
	wire [5:0] if_excode;

	assign if_exc = (pc[1:0] != 2'b00) & if_stage;
	assign if_excode = {6{if_exc}} & `LS132R_EX_ADEL;



	reg  [31:0] if_inst_reg;
    reg  [31:0] if_pc_reg;
    reg  [31:0] if_pc_add4_reg; 
	reg         if_exc_reg;
	reg  [ 5:0] if_excode_reg;  

	reg  if_valid;
    wire if_allowin;
    wire if_ready_go;

    assign if_ready_go     = resetn & !load_forward & inst_sram_ok;
    assign if_allowin      = !if_valid | if_ready_go & id_allowin;
    assign if_to_id_valid  = if_valid & if_ready_go;

    always @(posedge clk) 
    begin
        if (!resetn || int_exc)
            if_valid     <= 1'b0;
        else if (if_allowin) 
            if_valid     <= if_validin;

        if (!resetn || int_exc)
        begin
            if_inst_reg      <= 32'd0;
            if_pc_reg        <= 32'hbfc00000;
            if_pc_add4_reg   <= 32'hbfc00004;
			if_exc_reg       <= 1'b0;
			if_excode_reg    <= 6'd0;
        end
        else if(if_validin & if_allowin)
        begin
            if_inst_reg      <= inst_o;
            if_pc_reg        <= pc_o;
            if_pc_add4_reg   <= pc_add_4;
			if_exc_reg       <= if_exc;
			if_excode_reg    <= if_excode;
        end
    end

    assign if_pc_o       = if_pc_reg;
    assign if_pc_add4_o  = if_pc_add4_reg;
    assign if_inst_o     = if_inst_reg;
	assign if_exc_o      = if_exc_reg;
	assign if_excode_o   = if_excode_reg;
	assign if_id_stage_o = if_valid;

endmodule
module IF(
	input         clk,
	input         resetn,
	input         int_exc,

	input         stop,
	input         load_forward,
	input         j_token,
	input         op_eret,
	input         id_allowin,

	input  [31:0] irom_inst_i,
	input         inst_sram_ok,
	input  [31:0] id_next_pc_i,

	output        if_to_id_valid,
	output        if_id_stage_o,

	output        inst_ren,
	output [31:0] irom_pc_o,
	
	output [31:0] pc_add_4,

	output [31:0] if_pc_o,
	output [31:0] if_pc_add4_o,
	output [31:0] if_inst_o,

	output        if_exc_o,
	output [ 5:0] if_excode_o
);


	wire if_validin;
    assign if_validin = 1'b1;

	wire if_stage;
	assign if_stage = if_validin;

	reg  [31:0] pc;
	wire [31:0] next_pc;

	always @(posedge clk) begin
		if (!resetn)
			pc <= 32'hbfc0_0000;
		else if (int_exc)
			pc <= 32'hbfc00380;
		else if (pc_stall)
			pc <= pc;
		else if (if_stage)
			pc <= next_pc;
	end


	reg int_pc_ok;

	always@(posedge clk)
	begin
		if (!resetn) int_pc_ok <= 1'b1;
		else if (int_exc) int_pc_ok <= 1'b0;
		else if (inst_sram_ok) int_pc_ok <= 1'b1;
	end

	wire [31:0] inst_o;
	wire [31:0] pc_o;

	assign pc_add_4 = pc_o + 3'd4;

	wire pc_stall = stop | load_forward | !inst_sram_ok | !int_pc_ok | !if_allowin;
	wire inst_stall = int_exc | if_exc | op_eret | !inst_sram_ok | (inst_sram_ok & !int_pc_ok);

	assign next_pc = !resetn ? 32'hbfc00000 :
                     j_token ? id_next_pc_i : pc_add_4;


	assign irom_pc_o = pc;
	assign inst_o    = {32{!inst_stall}} & irom_inst_i;
	assign pc_o      = pc;
    assign inst_ren  = if_stage & !int_exc;

    wire if_exc_s;
	assign if_exc_s = (irom_pc_o[1:0] != 2'b00) & if_stage;

	wire if_exc;
	wire [5:0] if_excode;

	assign if_exc = (pc[1:0] != 2'b00) & if_stage;
	assign if_excode = {6{if_exc}} & `LS132R_EX_ADEL;



	reg  [31:0] if_inst_reg;
    reg  [31:0] if_pc_reg;
    reg  [31:0] if_pc_add4_reg; 
	reg         if_exc_reg;
	reg  [ 5:0] if_excode_reg;  

	reg  if_valid;
    wire if_allowin;
    wire if_ready_go;

    assign if_ready_go     = resetn & !load_forward & inst_sram_ok;
    assign if_allowin      = !if_valid | if_ready_go & id_allowin;
    assign if_to_id_valid  = if_valid & if_ready_go;

    always @(posedge clk) 
    begin
        if (!resetn || int_exc)
            if_valid     <= 1'b0;
        else if (if_allowin) 
            if_valid     <= if_validin;

        if (!resetn || int_exc)
        begin
            if_inst_reg      <= 32'd0;
            if_pc_reg        <= 32'hbfc00000;
            if_pc_add4_reg   <= 32'hbfc00004;
			if_exc_reg       <= 1'b0;
			if_excode_reg    <= 6'd0;
        end
        else if(if_validin & if_allowin)
        begin
            if_inst_reg      <= inst_o;
            if_pc_reg        <= pc_o;
            if_pc_add4_reg   <= pc_add_4;
			if_exc_reg       <= if_exc;
			if_excode_reg    <= if_excode;
        end
    end

    assign if_pc_o       = if_pc_reg;
    assign if_pc_add4_o  = if_pc_add4_reg;
    assign if_inst_o     = if_inst_reg;
	assign if_exc_o      = if_exc_reg;
	assign if_excode_o   = if_excode_reg;
	assign if_id_stage_o = if_valid;

endmodule