data/full_repos/permissive/100918256/Tx_test_internal.v
 line:75: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/100918256/Tx_test_internal.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100918256/Tx_test_internal.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/Tx_test_internal.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #300000 $stop;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/Tx_test_internal.v:79: Unsupported: Ignoring delay on this delayed statement.\n always #1.25 clk=~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/Tx_test_internal.v:80: Unsupported: Ignoring delay on this delayed statement.\n always #1000 baud_clk=~baud_clk;\n        ^\n%Warning-IMPLICIT: data/full_repos/permissive/100918256/Tx_test_internal.v:35: Signal definition not found, creating implicitly: \'rx\'\n                                                                             : ... Suggested alternative: \'tx\'\n assign rx = tx;\n        ^~\n%Warning-IMPLICIT: data/full_repos/permissive/100918256/Tx_test_internal.v:36: Signal definition not found, creating implicitly: \'bitstuffed_output\'\n assign bitstuffed_output = tx;\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100918256/Tx_test_internal.v:44: Cannot find file containing module: \'can_tx\'\n can_tx uut (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/can_tx\n             data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/can_tx.v\n             data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/can_tx.sv\n             can_tx\n             can_tx.v\n             can_tx.sv\n             obj_dir/can_tx\n             obj_dir/can_tx.v\n             obj_dir/can_tx.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Tx_test_internal;


	reg [10:0] address;
	reg clk;
	reg baud_clk;
	reg rst;
	reg [63:0] data;
	reg send_data;
	reg clear_to_tx;
	assign rx = tx;
	assign bitstuffed_output = tx;


	wire tx;
	wire can_bitstuff;
	wire txing;


	can_tx uut (
		.tx(tx), 
		.can_bitstuff(can_bitstuff), 
		.txing(txing), 
		.rx(rx), 
		.address(address), 
		.clk(clk), 
		.baud_clk(baud_clk), 
		.rst(rst), 
		.data(data), 
		.send_data(send_data), 
		.bitstuffed_output(bitstuffed_output), 
		.clear_to_tx(clear_to_tx)
	);

	initial begin

		address = 11'h28;
		clk = 0;
		baud_clk = 0;
		rst = 1;
		data = 43;
		send_data = 0;
		clear_to_tx = 0;


		#100;
        rst = 0;
		#10;
		send_data = 1;
		clear_to_tx = 1;
		#300000 $stop;


	end
	always #1.25 clk=~clk;
	always #1000 baud_clk=~baud_clk;
      
endmodule
module Tx_test_internal;



	reg [10:0] address;
	reg clk;
	reg baud_clk;
	reg rst;
	reg [63:0] data;
	reg send_data;
	reg clear_to_tx;
	assign rx = tx;
	assign bitstuffed_output = tx;


	wire tx;
	wire can_bitstuff;
	wire txing;


	can_tx uut (
		.tx(tx), 
		.can_bitstuff(can_bitstuff), 
		.txing(txing), 
		.rx(rx), 
		.address(address), 
		.clk(clk), 
		.baud_clk(baud_clk), 
		.rst(rst), 
		.data(data), 
		.send_data(send_data), 
		.bitstuffed_output(bitstuffed_output), 
		.clear_to_tx(clear_to_tx)
	);

	initial begin

		address = 11'h28;
		clk = 0;
		baud_clk = 0;
		rst = 1;
		data = 43;
		send_data = 0;
		clear_to_tx = 0;


		#100;
        rst = 0;
		#10;
		send_data = 1;
		clear_to_tx = 1;
		#300000 $stop;


	end
	always #1.25 clk=~clk;
	always #1000 baud_clk=~baud_clk;
      
endmodule