data/full_repos/permissive/141596082/voice_core/rtl/wb_gpio/core_clk.v
data/verilator_xmls/fe758ee1-adb8-4a0c-ba5d-fef29d9139f3.xml
module core_clk#(
      parameter PRESCALER = 16
)(
      input clk,
      input rst,

      output reg [PRESCALER-1:0] core_clk);

initial begin
core_clk = 0;
end

always @(posedge clk or posedge rst ) begin
  if (rst) 
    core_clk <= 0;
  else 
    core_clk <= core_clk + 1;
end

endmodule
module core_clk#(
      parameter PRESCALER = 16
)(
      input clk,
      input rst,

      output reg [PRESCALER-1:0] core_clk);


initial begin
core_clk = 0;
end

always @(posedge clk or posedge rst ) begin
  if (rst) 
    core_clk <= 0;
  else 
    core_clk <= core_clk + 1;
end

endmodule