data/full_repos/permissive/134925232/src/top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/134925232/src/top.v:19: Cannot find file containing module: 'fdiv'\n    fdiv #(.clock_hz(12000000), .hz(250005)) clk0(.clock(clk), .reset(1'b0), .out_clock(dmxclk));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/134925232/src,data/full_repos/permissive/134925232/fdiv\n             data/full_repos/permissive/134925232/src,data/full_repos/permissive/134925232/fdiv.v\n             data/full_repos/permissive/134925232/src,data/full_repos/permissive/134925232/fdiv.sv\n             fdiv\n             fdiv.v\n             fdiv.sv\n             obj_dir/fdiv\n             obj_dir/fdiv.v\n             obj_dir/fdiv.sv\n%Error: data/full_repos/permissive/134925232/src/top.v:20: Cannot find file containing module: 'dmx'\n    dmx dmx0(.dmxclk(~dmxclk), .signal(dmx1));\n    ^~~\n%Error: Exiting due to 2 error(s)\n"
module top(
    input wire clk,
    output wire power_led,

    input wire rx,
    output wire tx,

    output wire dmx1,
    output wire dmx1n,
    output wire dmx1s
);
    wire dmxclk;

    assign power_led = 1;
    assign dmx1s = 1;
    assign dmx1n = ~dmx1;


    fdiv #(.clock_hz(12000000), .hz(250005)) clk0(.clock(clk), .reset(1'b0), .out_clock(dmxclk));
    dmx dmx0(.dmxclk(~dmxclk), .signal(dmx1));
endmodule
module top(
    input wire clk,
    output wire power_led,

    input wire rx,
    output wire tx,

    output wire dmx1,
    output wire dmx1n,
    output wire dmx1s
);

    wire dmxclk;

    assign power_led = 1;
    assign dmx1s = 1;
    assign dmx1n = ~dmx1;


    fdiv #(.clock_hz(12000000), .hz(250005)) clk0(.clock(clk), .reset(1'b0), .out_clock(dmxclk));
    dmx dmx0(.dmxclk(~dmxclk), .signal(dmx1));
endmodule