data/full_repos/permissive/140493787/src/hdl/pixel_memory.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:71: Unsupported: Ignoring delay on this delayed statement.\n      forever #(CLK_PER / 2) clk <= ~clk;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:76: syntax error, unexpected \'@\'\n      wrEnable <= 1; @(posedge clk);\n                     ^\n%Error: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:79: syntax error, unexpected \'@\'\n            writeX <= i; writeY <= j; @(posedge clk);\n                                      ^\n%Error: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:82: syntax error, unexpected \'@\'\n      wrEnable <= 0; @ (posedge clk);\n                     ^\n%Error: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:89: syntax error, unexpected \'@\'\n            readX <= i; readY <= j; @(posedge clk);\n                                    ^\n%Error: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:93: syntax error, unexpected \'@\'\n      readX <= 24; readY <= 24; @(posedge clk);\n                                ^\n%Error: data/full_repos/permissive/140493787/src/hdl/pixel_memory.v:94: syntax error, unexpected \'@\'\n      readX <= 12; readY <= 12; @(posedge clk);\n                                ^\n%Error: Exiting due to 6 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pixel_memory_testbench ();
   wire       color;
   reg  [9:0] readX, readY;
   reg  [8:0] writeX, writeY;
   reg        wrEnable;
   reg        clk;

   pixel_memory dut (
      .color(color),
      .readX(readX),
      .readY(readY),
      .writeX(writeX),
      .writeY(writeY),
      .wrEnable(wrEnable),
      .clk(clk)
   );

   parameter CLK_PER = 10;
   initial begin
      clk <= 1;
      forever #(CLK_PER / 2) clk <= ~clk;
   end

   integer i, j;
   initial begin
      wrEnable <= 1; @(posedge clk);
      for (i = 0; i < 12; i = i + 1) begin
         for (j = 0; j < 12; j = j + 1) begin
            writeX <= i; writeY <= j; @(posedge clk);
         end
      end
      wrEnable <= 0; @ (posedge clk);

      for (i = 0; i < 12; i = i + 1) begin
         if (i == 6) begin
            writeX <= 12; writeY <= 12; wrEnable <= 1;
         end
         for (j = 0; j < 12; j = j + 1) begin
            readX <= i; readY <= j; @(posedge clk);
         end
         wrEnable <= 0;
      end
      readX <= 24; readY <= 24; @(posedge clk);
      readX <= 12; readY <= 12; @(posedge clk);
      $stop;
   end
endmodule
module pixel_memory_testbench ();

   wire       color;
   reg  [9:0] readX, readY;
   reg  [8:0] writeX, writeY;
   reg        wrEnable;
   reg        clk;

   pixel_memory dut (
      .color(color),
      .readX(readX),
      .readY(readY),
      .writeX(writeX),
      .writeY(writeY),
      .wrEnable(wrEnable),
      .clk(clk)
   );

   parameter CLK_PER = 10;
   initial begin
      clk <= 1;
      forever #(CLK_PER / 2) clk <= ~clk;
   end

   integer i, j;
   initial begin
      wrEnable <= 1; @(posedge clk);
      for (i = 0; i < 12; i = i + 1) begin
         for (j = 0; j < 12; j = j + 1) begin
            writeX <= i; writeY <= j; @(posedge clk);
         end
      end
      wrEnable <= 0; @ (posedge clk);

      for (i = 0; i < 12; i = i + 1) begin
         if (i == 6) begin
            writeX <= 12; writeY <= 12; wrEnable <= 1;
         end
         for (j = 0; j < 12; j = j + 1) begin
            readX <= i; readY <= j; @(posedge clk);
         end
         wrEnable <= 0;
      end
      readX <= 24; readY <= 24; @(posedge clk);
      readX <= 12; readY <= 12; @(posedge clk);
      $stop;
   end
endmodule