data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/vlog_tb_utils/vlog_tb_utils.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/vlog_tb_utils/vlog_tb_utils.v:7: Unsupported: Ignoring delay on this delayed statement.\n #timeout $display("Timeout: Forcing end of simulation");\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/vlog_tb_utils/vlog_tb_utils.v:14: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("testlog.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/vlog_tb_utils/vlog_tb_utils.v:15: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0);\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vlog_tb_utils;


   reg [63:0] timeout;
   initial
     if($value$plusargs("timeout=%d", timeout)) begin
	#timeout $display("Timeout: Forcing end of simulation");
	$finish;
     end


   initial begin
      if($test$plusargs("vcd")) begin
	 $dumpfile("testlog.vcd");
	 $dumpvars(0);
      end
   end

endmodule
module vlog_tb_utils;



   reg [63:0] timeout;
   initial
     if($value$plusargs("timeout=%d", timeout)) begin
	#timeout $display("Timeout: Forcing end of simulation");
	$finish;
     end


   initial begin
      if($test$plusargs("vcd")) begin
	 $dumpfile("testlog.vcd");
	 $dumpvars(0);
      end
   end

endmodule