data/full_repos/permissive/104443190/complex_mult/complex_mult_dsp_impl.v
data/verilator_xmls/ea7b64bc-3ed7-4cca-bd96-15b10910ba4d.xml
module complex_mult_dsp_impl
#(
	parameter WIDTH=16
)(

	clk,

	ab_valid,
	ar,ai,
	br,bi,

	p_valid,
	pr,pi

    );

	input clk;
	input ab_valid;
	input signed [WIDTH-1:0] 	    ar, ai;
	input signed [WIDTH-1:0] 	    br, bi;
	output p_valid;
	output signed [WIDTH+WIDTH:0] pr, pi;


	reg signed [WIDTH-1:0]	ai_d, ai_dd, ai_ddd, ai_dddd;
	reg signed [WIDTH-1:0]	ar_d, ar_dd, ar_ddd, ar_dddd;
	reg signed [WIDTH-1:0]	bi_d, bi_dd, bi_ddd, br_d, br_dd, br_ddd;
	reg signed [WIDTH:0]		addcommon;
	reg signed [WIDTH:0]		addr, addi;
	reg signed [WIDTH+WIDTH:0]	mult0, multr, multi, pr_int, pi_int;
	reg signed [WIDTH+WIDTH:0]	common, commonr1, commonr2;


	reg [5:0] data_valid_reg;

	always@(posedge clk)
	begin
		data_valid_reg[0] <= ab_valid;
		data_valid_reg[5:1] <= data_valid_reg[4:0];
	end

	assign p_valid = data_valid_reg[5];

always @(posedge clk)
  begin
    ar_d   <= ar;
    ar_dd  <= ar_d;
    ai_d   <= ai;
    ai_dd  <= ai_d;
    br_d   <= br;
    br_dd  <= br_d;
    br_ddd <= br_dd;
    bi_d   <= bi;
    bi_dd  <= bi_d;
    bi_ddd <= bi_dd;
  end



always @(posedge clk)
 begin
	addcommon <= ar_d - ai_d;
	mult0     <= addcommon * bi_dd;
	common    <= mult0;
 end



always @(posedge clk)
 begin
	ar_ddd   <= ar_dd;
	ar_dddd  <= ar_ddd;
	addr     <= br_ddd - bi_ddd;
	multr    <= addr * ar_dddd;
	commonr1 <= common;
	pr_int   <= multr + commonr1;
 end



always @(posedge clk)
 begin
	ai_ddd   <= ai_dd;
	ai_dddd  <= ai_ddd;
	addi     <= br_ddd + bi_ddd;
	multi    <= addi * ai_dddd;
	commonr2 <= common;
	pi_int   <= multi + commonr2;
 end

assign pr = pr_int;
assign pi = pi_int;



endmodule
module complex_mult_dsp_impl
#(
	parameter WIDTH=16
)(

	clk,

	ab_valid,
	ar,ai,
	br,bi,

	p_valid,
	pr,pi

    );


	input clk;
	input ab_valid;
	input signed [WIDTH-1:0] 	    ar, ai;
	input signed [WIDTH-1:0] 	    br, bi;
	output p_valid;
	output signed [WIDTH+WIDTH:0] pr, pi;


	reg signed [WIDTH-1:0]	ai_d, ai_dd, ai_ddd, ai_dddd;
	reg signed [WIDTH-1:0]	ar_d, ar_dd, ar_ddd, ar_dddd;
	reg signed [WIDTH-1:0]	bi_d, bi_dd, bi_ddd, br_d, br_dd, br_ddd;
	reg signed [WIDTH:0]		addcommon;
	reg signed [WIDTH:0]		addr, addi;
	reg signed [WIDTH+WIDTH:0]	mult0, multr, multi, pr_int, pi_int;
	reg signed [WIDTH+WIDTH:0]	common, commonr1, commonr2;


	reg [5:0] data_valid_reg;

	always@(posedge clk)
	begin
		data_valid_reg[0] <= ab_valid;
		data_valid_reg[5:1] <= data_valid_reg[4:0];
	end

	assign p_valid = data_valid_reg[5];

always @(posedge clk)
  begin
    ar_d   <= ar;
    ar_dd  <= ar_d;
    ai_d   <= ai;
    ai_dd  <= ai_d;
    br_d   <= br;
    br_dd  <= br_d;
    br_ddd <= br_dd;
    bi_d   <= bi;
    bi_dd  <= bi_d;
    bi_ddd <= bi_dd;
  end



always @(posedge clk)
 begin
	addcommon <= ar_d - ai_d;
	mult0     <= addcommon * bi_dd;
	common    <= mult0;
 end



always @(posedge clk)
 begin
	ar_ddd   <= ar_dd;
	ar_dddd  <= ar_ddd;
	addr     <= br_ddd - bi_ddd;
	multr    <= addr * ar_dddd;
	commonr1 <= common;
	pr_int   <= multr + commonr1;
 end



always @(posedge clk)
 begin
	ai_ddd   <= ai_dd;
	ai_dddd  <= ai_ddd;
	addi     <= br_ddd + bi_ddd;
	multi    <= addi * ai_dddd;
	commonr2 <= common;
	pi_int   <= multi + commonr2;
 end

assign pr = pr_int;
assign pi = pi_int;



endmodule