data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v
1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                         ^~~~~~\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                               ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                      ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                 ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                            ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                       ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                                  ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/211316121/lab6_2_nexys4/digitalClock.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                          : ... In instance digitalClock\n    wire [31:0] display={\'b0000,\'b0000,H1_display,H2_display,M1_display,M2_display,S1_display,S2_display};\n                                                                                             ^\n%Error: Exiting due to 8 warning(s)\n'
module BCD_7Seg(
    input [31:0] bcd,
    input [2:0] clkcount,
    output [6:0] a2g,
    output reg [7:0] an
    );
    
    reg [3:0] digit;
    parameter aen = 8'b11000000;
    
    always @ (*)
    case(clkcount)
        3'b000:  digit = bcd[3:0];
        3'b001:  digit = bcd[7:4];
        3'b010:  digit = bcd[11:8];
        3'b011:  digit = bcd[15:12];
        3'b100:  digit = bcd[19:16];
        3'b101:  digit = bcd[23:20];
        3'b110:  digit = bcd[27:24];
        3'b111:  digit = bcd[31:28];
    endcase
    
    always @ (*)
    begin
        an = 8'b11111111;
        an[clkcount] = aen[clkcount];
    end
    
    seven_segment seg0(digit, a2g);
endmodule
module BCD_7Seg(
    input [31:0] bcd,
    input [2:0] clkcount,
    output [6:0] a2g,
    output reg [7:0] an
    );

    
    reg [3:0] digit;
    parameter aen = 8'b11000000;
    
    always @ (*)
    case(clkcount)
        3'b000:  digit = bcd[3:0];
        3'b001:  digit = bcd[7:4];
        3'b010:  digit = bcd[11:8];
        3'b011:  digit = bcd[15:12];
        3'b100:  digit = bcd[19:16];
        3'b101:  digit = bcd[23:20];
        3'b110:  digit = bcd[27:24];
        3'b111:  digit = bcd[31:28];
    endcase
    
    always @ (*)
    begin
        an = 8'b11111111;
        an[clkcount] = aen[clkcount];
    end
    
    seven_segment seg0(digit, a2g);
endmodule