data/full_repos/permissive/117026779/src/ServoController.v
1: b"%Error: data/full_repos/permissive/117026779/src/ServoController.v:53: Cannot find file containing module: 'ServoModule'\nServoModule U0(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/ServoModule\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/ServoModule.v\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/ServoModule.sv\n             ServoModule\n             ServoModule.v\n             ServoModule.sv\n             obj_dir/ServoModule\n             obj_dir/ServoModule.v\n             obj_dir/ServoModule.sv\n%Error: data/full_repos/permissive/117026779/src/ServoController.v:60: Cannot find file containing module: 'ServoModule'\nServoModule U1(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/117026779/src/ServoController.v:67: Cannot find file containing module: 'ServoModule'\nServoModule U2(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/117026779/src/ServoController.v:74: Cannot find file containing module: 'ServoModule'\nServoModule U3(\n^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module ServoController #(
    parameter SIGNAL_BIT_WIDTH  = 16,
    parameter ADDRESS_BIT_WIDTH = 2,
    parameter PWM_SIGNAL_COUNT  = 4
)
(
    input wire clk,
    input wire rst,
    input wire cs,
    input wire  [ADDRESS_BIT_WIDTH-1:0] addr,
    input wire  [SIGNAL_BIT_WIDTH-1:0]  data,
    output wire [PWM_SIGNAL_COUNT-1:0]  signal
);






wire [PWM_SIGNAL_COUNT-1:0] load_select;



assign load_select[0]  = (addr == 2'b00 && cs) ? 1 : 0;
assign load_select[1]  = (addr == 2'b01 && cs) ? 1 : 0;
assign load_select[2]  = (addr == 2'b10 && cs) ? 1 : 0;
assign load_select[3]  = (addr == 2'b11 && cs) ? 1 : 0;



ServoModule U0(
    .clk(clk),
    .rst(rst),
    .load(load_select[0]),
    .data(data),
    .signal(signal[0])
);
ServoModule U1(
    .clk(clk),
    .rst(rst),
    .load(load_select[1]),
    .data(data),
    .signal(signal[1])
);
ServoModule U2(
    .clk(clk),
    .rst(rst),
    .load(load_select[2]),
    .data(data),
    .signal(signal[2])
);
ServoModule U3(
    .clk(clk),
    .rst(rst),
    .load(load_select[3]),
    .data(data),
    .signal(signal[3])
);



endmodule
module ServoController #(
    parameter SIGNAL_BIT_WIDTH  = 16,
    parameter ADDRESS_BIT_WIDTH = 2,
    parameter PWM_SIGNAL_COUNT  = 4
)
(
    input wire clk,
    input wire rst,
    input wire cs,
    input wire  [ADDRESS_BIT_WIDTH-1:0] addr,
    input wire  [SIGNAL_BIT_WIDTH-1:0]  data,
    output wire [PWM_SIGNAL_COUNT-1:0]  signal
);







wire [PWM_SIGNAL_COUNT-1:0] load_select;



assign load_select[0]  = (addr == 2'b00 && cs) ? 1 : 0;
assign load_select[1]  = (addr == 2'b01 && cs) ? 1 : 0;
assign load_select[2]  = (addr == 2'b10 && cs) ? 1 : 0;
assign load_select[3]  = (addr == 2'b11 && cs) ? 1 : 0;



ServoModule U0(
    .clk(clk),
    .rst(rst),
    .load(load_select[0]),
    .data(data),
    .signal(signal[0])
);
ServoModule U1(
    .clk(clk),
    .rst(rst),
    .load(load_select[1]),
    .data(data),
    .signal(signal[1])
);
ServoModule U2(
    .clk(clk),
    .rst(rst),
    .load(load_select[2]),
    .data(data),
    .signal(signal[2])
);
ServoModule U3(
    .clk(clk),
    .rst(rst),
    .load(load_select[3]),
    .data(data),
    .signal(signal[3])
);



endmodule