data/full_repos/permissive/108561032/procesador_segmentado.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:107: Cannot find file containing module: 'memoriaintrucciones'\n memoriaintrucciones memoriainstru(.direinstru(direinstrux),\n ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/108561032,data/full_repos/permissive/108561032/memoriaintrucciones\n             data/full_repos/permissive/108561032,data/full_repos/permissive/108561032/memoriaintrucciones.v\n             data/full_repos/permissive/108561032,data/full_repos/permissive/108561032/memoriaintrucciones.sv\n             memoriaintrucciones\n             memoriaintrucciones.v\n             memoriaintrucciones.sv\n             obj_dir/memoriaintrucciones\n             obj_dir/memoriaintrucciones.v\n             obj_dir/memoriaintrucciones.sv\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:113: Cannot find file containing module: 'control'\n control control(.instru(instruD[31:26]),\n ^~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:122: Cannot find file containing module: 'bankregister'\n bankregister registros(.RegLe1(instruD[25:21]),\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:133: Cannot find file containing module: 'extension_signo'\n extension_signo extension(.instr(instru[15:0]),\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:138: Cannot find file containing module: 'alu32'\n alu32 alu(.data1(data1D),\n ^~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:147: Cannot find file containing module: 'memoria_datos'\n memoria_datos datos(.clk(clk),\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:154: Cannot find file containing module: 'pc'\n   pc pro_counter(\n   ^~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:169: Cannot find file containing module: 'controlALU'\n   controlALU contrALU(\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:180: Cannot find file containing module: 'control1'\ncontrol1 control1(.Control(Control),\n^~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:189: Cannot find file containing module: 'control2'\ncontrol2 control2(.Control(Controls1),\n^~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:197: Cannot find file containing module: 'control3'\ncontrol3 control3(.Control(Controls2),\n^~~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:206: Cannot find file containing module: 'Fetch'\nFetch Fetch(.clk(clk),\n^~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:214: Cannot find file containing module: 'Decode'\nDecode Decode(.clk(clk),\n^~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:230: Cannot find file containing module: 'Execute'\n Execute Execute(.clk(clk),\n ^~~~~~~\n%Error: data/full_repos/permissive/108561032/procesador_segmentado.v:244: Cannot find file containing module: 'Memory'\nMemory Memory(.clk(clk),\n^~~~~~\n%Error: Exiting due to 15 error(s)\n"
module procesador_segmentado(
clk,reset

);

input wire clk;
 reg [31:0] direinstru;
 wire [31:0] instru;
 
 wire RegDest;
 wire SaltoCond;
 wire Saltoincond;
 wire LeerMem;
 wire MemaReg;
 wire [1:0]ALUOp;
 wire  EscrMem;
 wire FuenteALU;
 wire EscrReg;
 wire [31:0] data1;
 wire [31:0] data2;
 wire [31:0] datain;
 wire [31:0] oinstru;
 wire [2:0] ctrl;
 wire oCarry;
 wire oZero;
 wire [31:0] out;
 wire [31:0] Dataout;
 

 wire [4:0] RegEscr1;
 wire [31:0] data21;
 wire [31:0] dataEscr;
 

  wire [31:0] ext2;
  wire [31:0] sum2sum;
  wire [31:0] salSum2;
  wire FuentePC;
  wire [31:0] toPC;
  wire [31:0]direinstrux;
 input wire reset;
 parameter varCuatro=3'b100;
 
 wire [9:0] Control;
 wire [9:0] Controls1;
 wire [9:0] Controls2;
 

 wire FFetch;
 wire FDecode;
 wire FExecute;
 wire FMemory;
 

 wire [31:0] instruD;
 wire [31:0] sum2sumOF;
 wire [31:0] sum2sumIF;
 

 
 wire [31:0] data1D;
 wire [31:0] data2D;
 wire [4:0] instru2016D;
 wire [4:0] instru1511D;
 wire [31:0] oinstruD;
 wire [31:0] sum2sumOF_D;
 

 
wire [31:0] outE;
wire oZeroD;
wire [31:0] data2D_E;
wire [31:0] RegEscr1E;
wire [31:0] salSum2out;
wire [31:0] salSum2E;



wire [31:0] outE_M;
wire [31:0] DataoutM;
wire [4:0] RegEscr1E_M;

 
 
 memoriaintrucciones memoriainstru(.direinstru(direinstrux),
                                   .instru(instru),
			                       .clk(clk),
			                       .reset(reset)			
                                   );
 
 control control(.instru(instruD[31:26]),
                 .clk(clk),
                 .Control(Control),
                 .FFetch(FFetch),
                 .FDecode(FDecode),
                 .FExecute(FExecute),
                 .FMemory(FMemory)       
                 );

 bankregister registros(.RegLe1(instruD[25:21]),
                        .RegLe2(instruD[20:16]),
                        .RegEscr(RegEscr1),
                        .EscrReg(EscrReg),
                        .clk(clk),
                        .datain(dataEscr),
                        .data1(data1),
                        .data2(data2),
                        .reset(reset)           
                        );
                        
 extension_signo extension(.instr(instru[15:0]),
                           .oinstr(oinstru),
                           .clk(clk)                        
                           ); 
   
 alu32 alu(.data1(data1D),
           .data2(data21),
           .ctrl(ctrl),
           .clk(clk),
           .oCarry(oCarry),
           .oZero(oZero),
           .out(out)  
           );
 
 memoria_datos datos(.clk(clk),
                     .EscrMem(EscrMem),
                     .Direc(outE), 
                     .Datain(data2D_E),
                     .LeerMem(LeerMem),
                     .Dataout(Dataout)
                     );
   pc pro_counter(
            .SaltoCond(SaltoCond),
			.Saltoincond(Saltoincond),
            .extSigno(oinstruD),
            .oZero(oZeroD),
            .direinstru(direinstrux),
            .clk(clk),   
            .reset(reset),
			.instru(instru),
			.sum2sumin(sum2sumOF_D),
			.sum2sumout(sum2sumIF),
			.salSum2out(salSum2out),
			.salSum2in(salSum2E)           
            );
   
   controlALU contrALU(
        .ALUop(ALUOp),
        .instru(instruD[5:0]),
        .clk(clk),
        .contALU(ctrl)   
        );





control1 control1(.Control(Control),
                .clk(clk),
                .RegDest(RegDest),
                .ALUOp(ALUOp),
                .FuenteALU(FuenteALU),
                .Controls1(Controls1),
                .Saltoincond(Saltoincond)

                );
control2 control2(.Control(Controls1),
                  .clk(clk),
                  .SaltoCond(SaltoCond),
                  .EscrMem(EscrMem),
                  .Controls2(Controls2),
                  .LeerMem(LeerMem),
                  .reset(reset)        
                  );
control3 control3(.Control(Controls2),
                  .clk(clk),
                  .MemaReg(MemaReg),
                  .EscrReg(EscrReg),
                  .reset(reset)        
                  );
 

    
Fetch Fetch(.clk(clk),
            .instru(instru),
            .instruD(instruD),
            .sum2sumIF(sum2sumIF),
            .sum2sumOF(sum2sumOF),
            .FFetch(FFetch)
            );
            
Decode Decode(.clk(clk),
              .data1R(data1),
              .data2R(data2),
              .data1D(data1D),
              .data2D(data2D),
              .instru2016(instru[20:16]),
              .instru1511(instru[15:11]),
              .instru2016D(instru2016D),
              .instru1511D(instru1511D),
              .oinstru(oinstru),
              .oinstruD(oinstruD),
              .sum2sumOF(sum2sumOF),
              .sum2sumOF_D(sum2sumOF_D),
              .FDecode(FDecode)                           
             );
             
 Execute Execute(.clk(clk),
                 .out(out),
                 .outE(outE),
                 .oZero(oZero),
                 .oZeroD(oZeroD),
                 .data2D(data2D),
                 .data2D_E(data2D_E),
                 .RegEscr1(RegEscr1),
                 .RegEscr1E(RegEscr1E),
                 .salSum2out(salSum2out),
                 .salSum2E(salSum2E),
                 .FExecute(FExecute),
                 .reset(reset)
                 );
Memory Memory(.clk(clk),
              .outE(outE),
              .outE_M(outE_M),
              .Dataout(Dataout),
              .DataoutM(DataoutM),
              .RegEscr1E(RegEscr1E),
              .RegEscr1E_M(RegEscr1E_M),
              .FMemory(FMemory)
              );
    

assign RegEscr1 = RegDest ? instru1511D: instru2016D;
assign data21 = FuenteALU ? oinstruD : data2D;                         
assign dataEscr = MemaReg ? DataoutM : outE_M;

endmodule
module procesador_segmentado(
clk,reset

);


input wire clk;
 reg [31:0] direinstru;
 wire [31:0] instru;
 
 wire RegDest;
 wire SaltoCond;
 wire Saltoincond;
 wire LeerMem;
 wire MemaReg;
 wire [1:0]ALUOp;
 wire  EscrMem;
 wire FuenteALU;
 wire EscrReg;
 wire [31:0] data1;
 wire [31:0] data2;
 wire [31:0] datain;
 wire [31:0] oinstru;
 wire [2:0] ctrl;
 wire oCarry;
 wire oZero;
 wire [31:0] out;
 wire [31:0] Dataout;
 

 wire [4:0] RegEscr1;
 wire [31:0] data21;
 wire [31:0] dataEscr;
 

  wire [31:0] ext2;
  wire [31:0] sum2sum;
  wire [31:0] salSum2;
  wire FuentePC;
  wire [31:0] toPC;
  wire [31:0]direinstrux;
 input wire reset;
 parameter varCuatro=3'b100;
 
 wire [9:0] Control;
 wire [9:0] Controls1;
 wire [9:0] Controls2;
 

 wire FFetch;
 wire FDecode;
 wire FExecute;
 wire FMemory;
 

 wire [31:0] instruD;
 wire [31:0] sum2sumOF;
 wire [31:0] sum2sumIF;
 

 
 wire [31:0] data1D;
 wire [31:0] data2D;
 wire [4:0] instru2016D;
 wire [4:0] instru1511D;
 wire [31:0] oinstruD;
 wire [31:0] sum2sumOF_D;
 

 
wire [31:0] outE;
wire oZeroD;
wire [31:0] data2D_E;
wire [31:0] RegEscr1E;
wire [31:0] salSum2out;
wire [31:0] salSum2E;



wire [31:0] outE_M;
wire [31:0] DataoutM;
wire [4:0] RegEscr1E_M;

 
 
 memoriaintrucciones memoriainstru(.direinstru(direinstrux),
                                   .instru(instru),
			                       .clk(clk),
			                       .reset(reset)			
                                   );
 
 control control(.instru(instruD[31:26]),
                 .clk(clk),
                 .Control(Control),
                 .FFetch(FFetch),
                 .FDecode(FDecode),
                 .FExecute(FExecute),
                 .FMemory(FMemory)       
                 );

 bankregister registros(.RegLe1(instruD[25:21]),
                        .RegLe2(instruD[20:16]),
                        .RegEscr(RegEscr1),
                        .EscrReg(EscrReg),
                        .clk(clk),
                        .datain(dataEscr),
                        .data1(data1),
                        .data2(data2),
                        .reset(reset)           
                        );
                        
 extension_signo extension(.instr(instru[15:0]),
                           .oinstr(oinstru),
                           .clk(clk)                        
                           ); 
   
 alu32 alu(.data1(data1D),
           .data2(data21),
           .ctrl(ctrl),
           .clk(clk),
           .oCarry(oCarry),
           .oZero(oZero),
           .out(out)  
           );
 
 memoria_datos datos(.clk(clk),
                     .EscrMem(EscrMem),
                     .Direc(outE), 
                     .Datain(data2D_E),
                     .LeerMem(LeerMem),
                     .Dataout(Dataout)
                     );
   pc pro_counter(
            .SaltoCond(SaltoCond),
			.Saltoincond(Saltoincond),
            .extSigno(oinstruD),
            .oZero(oZeroD),
            .direinstru(direinstrux),
            .clk(clk),   
            .reset(reset),
			.instru(instru),
			.sum2sumin(sum2sumOF_D),
			.sum2sumout(sum2sumIF),
			.salSum2out(salSum2out),
			.salSum2in(salSum2E)           
            );
   
   controlALU contrALU(
        .ALUop(ALUOp),
        .instru(instruD[5:0]),
        .clk(clk),
        .contALU(ctrl)   
        );





control1 control1(.Control(Control),
                .clk(clk),
                .RegDest(RegDest),
                .ALUOp(ALUOp),
                .FuenteALU(FuenteALU),
                .Controls1(Controls1),
                .Saltoincond(Saltoincond)

                );
control2 control2(.Control(Controls1),
                  .clk(clk),
                  .SaltoCond(SaltoCond),
                  .EscrMem(EscrMem),
                  .Controls2(Controls2),
                  .LeerMem(LeerMem),
                  .reset(reset)        
                  );
control3 control3(.Control(Controls2),
                  .clk(clk),
                  .MemaReg(MemaReg),
                  .EscrReg(EscrReg),
                  .reset(reset)        
                  );
 

    
Fetch Fetch(.clk(clk),
            .instru(instru),
            .instruD(instruD),
            .sum2sumIF(sum2sumIF),
            .sum2sumOF(sum2sumOF),
            .FFetch(FFetch)
            );
            
Decode Decode(.clk(clk),
              .data1R(data1),
              .data2R(data2),
              .data1D(data1D),
              .data2D(data2D),
              .instru2016(instru[20:16]),
              .instru1511(instru[15:11]),
              .instru2016D(instru2016D),
              .instru1511D(instru1511D),
              .oinstru(oinstru),
              .oinstruD(oinstruD),
              .sum2sumOF(sum2sumOF),
              .sum2sumOF_D(sum2sumOF_D),
              .FDecode(FDecode)                           
             );
             
 Execute Execute(.clk(clk),
                 .out(out),
                 .outE(outE),
                 .oZero(oZero),
                 .oZeroD(oZeroD),
                 .data2D(data2D),
                 .data2D_E(data2D_E),
                 .RegEscr1(RegEscr1),
                 .RegEscr1E(RegEscr1E),
                 .salSum2out(salSum2out),
                 .salSum2E(salSum2E),
                 .FExecute(FExecute),
                 .reset(reset)
                 );
Memory Memory(.clk(clk),
              .outE(outE),
              .outE_M(outE_M),
              .Dataout(Dataout),
              .DataoutM(DataoutM),
              .RegEscr1E(RegEscr1E),
              .RegEscr1E_M(RegEscr1E_M),
              .FMemory(FMemory)
              );
    

assign RegEscr1 = RegDest ? instru1511D: instru2016D;
assign data21 = FuenteALU ? oinstruD : data2D;                         
assign dataEscr = MemaReg ? DataoutM : outE_M;

endmodule