data/full_repos/permissive/201488448/2_circuits/1_combinational/12_combab.v
data/verilator_xmls/81939e3f-1b50-48b8-b952-3d8a278e3992.xml
module A (
	input x,
	input y,
	output z);

	assign z = (x^y) & x;
	
endmodule
module A (
	input x,
	input y,
	output z);


	assign z = (x^y) & x;
	
endmodule