data/full_repos/permissive/148200700/Quartus/designFiles/ip/KBandIPsubPro/KBandIPsubPro_pio_0/KBandIPsubPro_pio_0_bb.v
data/verilator_xmls/38413734-0d3e-48de-a46a-9575cda22de8.xml
module KBandIPsubPro_pio_0 (
		input  wire        clk,
		input  wire        reset_n,
		input  wire [1:0]  address,
		input  wire        write_n,
		input  wire [31:0] writedata,
		input  wire        chipselect,
		output wire [31:0] readdata,
		output wire [31:0] out_port
	);
endmodule
module KBandIPsubPro_pio_0 (
		input  wire        clk,
		input  wire        reset_n,
		input  wire [1:0]  address,
		input  wire        write_n,
		input  wire [31:0] writedata,
		input  wire        chipselect,
		output wire [31:0] readdata,
		output wire [31:0] out_port
	);

endmodule