data/full_repos/permissive/162672365/Mux.v
data/verilator_xmls/e3c1508f-1b12-4134-a21a-afcd103f3c3b.xml
module mux2to1(out, select, in1, in2);
	input in1, in2, select;
	output out;
	wire not_select, w1, w2;
	
	not (not_select, select);
	and (w1, select, in2);
	and (w2, not_select, in1);
	or(out, w1, w2);
	
endmodule
module mux2to1(out, select, in1, in2);

	input in1, in2, select;
	output out;
	wire not_select, w1, w2;
	
	not (not_select, select);
	and (w1, select, in2);
	and (w2, not_select, in1);
	or(out, w1, w2);
	
endmodule