data/full_repos/permissive/135701568/mux8bit.v
data/verilator_xmls/4a399807-2c16-4720-8d78-204856dafd43.xml
module mux8bit(in1, in2, control, out);
  input[7:0] in1,in2;
  output[7:0] out;
  input control;
  assign out = (control) ? in2 : in1;
endmodule
module mux8bit(in1, in2, control, out);

  input[7:0] in1,in2;
  output[7:0] out;
  input control;
  assign out = (control) ? in2 : in1;
endmodule