data/full_repos/permissive/129670804/final_top.sv
 line:508: before: ")"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/129670804/final_top.sv:463: Signal definition not found, creating implicitly: \'reset_h\'\n                                                                        : ... Suggested alternative: \'reset_n\'\nassign reset_h = 1\'b0;\n       ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/129670804/final_top.sv:465: Cannot find file containing module: \'DE2_115_SOPC\'\nDE2_115_SOPC DE2_115_SOPC_inst(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129670804,data/full_repos/permissive/129670804/DE2_115_SOPC\n             data/full_repos/permissive/129670804,data/full_repos/permissive/129670804/DE2_115_SOPC.v\n             data/full_repos/permissive/129670804,data/full_repos/permissive/129670804/DE2_115_SOPC.sv\n             DE2_115_SOPC\n             DE2_115_SOPC.v\n             DE2_115_SOPC.sv\n             obj_dir/DE2_115_SOPC\n             obj_dir/DE2_115_SOPC.v\n             obj_dir/DE2_115_SOPC.sv\n%Error: data/full_repos/permissive/129670804/final_top.sv:512: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_inst_0 (Mouse_data[3:0], HEX0);\n^~~~~~~~~\n%Error: data/full_repos/permissive/129670804/final_top.sv:513: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_inst_1 (Mouse_data[7:4], HEX1);\n^~~~~~~~~\n%Error: data/full_repos/permissive/129670804/final_top.sv:514: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_inst_2 (Mouse_data[19:16], HEX2);\n^~~~~~~~~\n%Error: data/full_repos/permissive/129670804/final_top.sv:515: Cannot find file containing module: \'HexDriver\'\nHexDriver hex_inst_3 (Mouse_data[23:20], HEX3);\n^~~~~~~~~\n%Error: data/full_repos/permissive/129670804/final_top.sv:518: Cannot find file containing module: \'vga_clk\'\nvga_clk vga_clk_instance( .*, .inclk0(CLOCK_50), .c0(VGA_CLK));\n^~~~~~~\n%Error: data/full_repos/permissive/129670804/final_top.sv:519: Cannot find file containing module: \'VGA_controller\'\nVGA_controller VC (.Clk(CLOCK_50), .Reset(reset_h), .*);\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129670804/final_top.sv:520: Cannot find file containing module: \'color_mapper\'\ncolor_mapper color_instance(.*);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/129670804/final_top.sv:521: Cannot find file containing module: \'ball\'\nball ball_instance(.Clk(CLOCK_50), .Reset(reset_h), .X(10\'d320), .Y(10\'d320), .*, .frame_clk(VGA_VS));\n^~~~\n%Error: Exiting due to 9 error(s), 1 warning(s)\n'
module final_top(


	CLOCK_50,
   CLOCK2_50,
   CLOCK3_50,
	ENETCLK_25,


	SMA_CLKIN,
	SMA_CLKOUT,


	LEDG,
	LEDR,


	KEY,


	SW,


	HEX0,
	HEX1,
	HEX2,
	HEX3,
	HEX4,
	HEX5,
	HEX6,
	HEX7,


	LCD_BLON,
	LCD_DATA,
	LCD_EN,
	LCD_ON,
	LCD_RS,
	LCD_RW,


	UART_CTS,
	UART_RTS,
	UART_RXD,
	UART_TXD,


	PS2_CLK,
	PS2_DAT,
	PS2_CLK2,
	PS2_DAT2,


	SD_CLK,
	SD_CMD,
	SD_DAT,
	SD_WP_N,


	VGA_B,
	VGA_BLANK_N,
	VGA_CLK,
	VGA_G,
	VGA_HS,
	VGA_R,
	VGA_SYNC_N,
	VGA_VS,


	AUD_ADCDAT,
	AUD_ADCLRCK,
	AUD_BCLK,
	AUD_DACDAT,
	AUD_DACLRCK,
	AUD_XCK,


	EEP_I2C_SCLK,
	EEP_I2C_SDAT,


	I2C_SCLK,
	I2C_SDAT,


	ENET0_GTX_CLK,
	ENET0_INT_N,
	ENET0_MDC,
	ENET0_MDIO,
	ENET0_RST_N,
	ENET0_RX_CLK,
	ENET0_RX_COL,
	ENET0_RX_CRS,
	ENET0_RX_DATA,
	ENET0_RX_DV,
	ENET0_RX_ER,
	ENET0_TX_CLK,
	ENET0_TX_DATA,
	ENET0_TX_EN,
	ENET0_TX_ER,
	ENET0_LINK100,


	ENET1_GTX_CLK,
	ENET1_INT_N,
	ENET1_MDC,
	ENET1_MDIO,
	ENET1_RST_N,
	ENET1_RX_CLK,
	ENET1_RX_COL,
	ENET1_RX_CRS,
	ENET1_RX_DATA,
	ENET1_RX_DV,
	ENET1_RX_ER,
	ENET1_TX_CLK,
	ENET1_TX_DATA,
	ENET1_TX_EN,
	ENET1_TX_ER,
	ENET1_LINK100,


	TD_CLK27,
	TD_DATA,
	TD_HS,
	TD_RESET_N,
	TD_VS,


   OTG_DATA,
   OTG_ADDR,
   OTG_CS_N,
   OTG_WR_N,
   OTG_RD_N,
   OTG_INT,
   OTG_RST_N,
	 

	IRDA_RXD,


	DRAM_ADDR,
	DRAM_BA,
	DRAM_CAS_N,
	DRAM_CKE,
	DRAM_CLK,
	DRAM_CS_N,
	DRAM_DQ,
	DRAM_DQM,
	DRAM_RAS_N,
	DRAM_WE_N,


	SRAM_ADDR,
	SRAM_CE_N,
	SRAM_DQ,
	SRAM_LB_N,
	SRAM_OE_N,
	SRAM_UB_N,
	SRAM_WE_N,


	FL_ADDR,
	FL_CE_N,
	FL_DQ,
	FL_OE_N,
	FL_RST_N,
	FL_RY,
	FL_WE_N,
	FL_WP_N,


	GPIO,




	HSMC_CLKIN_P1,
	HSMC_CLKIN_P2,
	HSMC_CLKIN0,


	HSMC_CLKOUT_P1,
	HSMC_CLKOUT_P2,
	HSMC_CLKOUT0,
	HSMC_D,

	HSMC_RX_D_P,

	HSMC_TX_D_P,

    EX_IO	
);











input		          		   CLOCK_50;
input		          		   CLOCK2_50;
input		          		   CLOCK3_50;
input		          		   ENETCLK_25;


input		          		   SMA_CLKIN;
output		          	   SMA_CLKOUT;


output		     [8:0]		LEDG;
output		    [17:0]		LEDR;


input		       [3:0]		KEY;


input		      [17:0]		SW;


output		     [6:0]		HEX0;
output		     [6:0]		HEX1;
output		     [6:0]		HEX2;
output		     [6:0]		HEX3;
output		     [6:0]		HEX4;
output		     [6:0]		HEX5;
output		     [6:0]		HEX6;
output		     [6:0]		HEX7;


output		          		LCD_BLON;
inout		       [7:0]		LCD_DATA;
output		          		LCD_EN;
output		          		LCD_ON;
output		          		LCD_RS;
output		          		LCD_RW;


output		          		UART_CTS;
input		          	   	UART_RTS;
input		          		   UART_RXD;
output		          		UART_TXD;


inout		          		   PS2_CLK;
inout		          		   PS2_DAT;
inout		          		   PS2_CLK2;
inout		          		   PS2_DAT2;


output		          		SD_CLK;
inout		          	    	SD_CMD;
inout		       [3:0]		SD_DAT;
input		          	   	SD_WP_N;


output		     [7:0]		VGA_B;
output		          		VGA_BLANK_N;
output		          		VGA_CLK;
output		     [7:0]		VGA_G;
output		          		VGA_HS;
output		     [7:0]		VGA_R;
output		          		VGA_SYNC_N;
output		          		VGA_VS;


input		          	   	AUD_ADCDAT;
inout		          		   AUD_ADCLRCK;
inout		          		   AUD_BCLK;
output		          		AUD_DACDAT;
inout		          		   AUD_DACLRCK;
output		          		AUD_XCK;


output		          		EEP_I2C_SCLK;
inout		          	   	EEP_I2C_SDAT;


output		          		I2C_SCLK;
inout		          		   I2C_SDAT;


output		          		ENET0_GTX_CLK;
input		          	   	ENET0_INT_N;
output		          		ENET0_MDC;
inout		          	   	ENET0_MDIO;
output		          	 	ENET0_RST_N;
input		          		   ENET0_RX_CLK;
input		          	    	ENET0_RX_COL;
input		             		ENET0_RX_CRS;
input		       [3:0]		ENET0_RX_DATA;
input		             		ENET0_RX_DV;
input		          		   ENET0_RX_ER;
input		          		   ENET0_TX_CLK;
output		    [3:0]		ENET0_TX_DATA;
output		          		ENET0_TX_EN;
output		          		ENET0_TX_ER;
input		          		   ENET0_LINK100;


output		          		ENET1_GTX_CLK;
input		          		   ENET1_INT_N;
output		          		ENET1_MDC;
inout		          		   ENET1_MDIO;
output		          		ENET1_RST_N;
input		          		   ENET1_RX_CLK;
input		          		   ENET1_RX_COL;
input		          		   ENET1_RX_CRS;
input		        [3:0]		ENET1_RX_DATA;
input		            		ENET1_RX_DV;
input		          	   	ENET1_RX_ER;
input		          	   	ENET1_TX_CLK;
output		     [3:0]		ENET1_TX_DATA;
output		          		ENET1_TX_EN;
output		          		ENET1_TX_ER;
input		          		   ENET1_LINK100;


input		          	   	TD_CLK27;
input		     [7:0]		   TD_DATA;
input		          		   TD_HS;
output		          		TD_RESET_N;
input		          	    	TD_VS;



inout           [15:0]     OTG_DATA;
output          [1:0]      OTG_ADDR;
output                     OTG_CS_N;
output                     OTG_WR_N;
output                     OTG_RD_N;
input            		      OTG_INT;
output                     OTG_RST_N;



input		          		   IRDA_RXD;


output		    [12:0]		DRAM_ADDR;
output		    [1:0]		DRAM_BA;
output		          		DRAM_CAS_N;
output		          		DRAM_CKE;
output		          		DRAM_CLK;
output		          		DRAM_CS_N;
inout		      [31:0]		DRAM_DQ;
output		    [3:0]		DRAM_DQM;
output		          		DRAM_RAS_N;
output		          		DRAM_WE_N;


output		    [19:0]		SRAM_ADDR;
output		          		SRAM_CE_N;
inout		      [15:0]		SRAM_DQ;
output		          		SRAM_LB_N;
output		          		SRAM_OE_N;
output		          		SRAM_UB_N;
output		          		SRAM_WE_N;


output		   [22:0]		FL_ADDR;
output		          		FL_CE_N;
inout		       [7:0]		FL_DQ;
output		          		FL_OE_N;
output		          		FL_RST_N;
input		          	   	FL_RY;
output		          		FL_WE_N;
output		          		FL_WP_N;


inout		      [35:0]		GPIO;





input		          	   	HSMC_CLKIN_P1;
input		          	   	HSMC_CLKIN_P2;
input		          		   HSMC_CLKIN0;


output		          		HSMC_CLKOUT_P1;
output		          		HSMC_CLKOUT_P2;
output		          		HSMC_CLKOUT0;
inout		        [3:0]		HSMC_D;

input		       [16:0]		HSMC_RX_D_P;

output		    [16:0]		HSMC_TX_D_P;


inout		       [6:0]		EX_IO;





wire        HEX0P;
wire        HEX1P;
wire        HEX2P;
wire        HEX3P;
wire        HEX4P;
wire        HEX5P;
wire        HEX6P;
wire        HEX7P;

wire        clk_25;

wire        reset_n;




assign reset_n = 1'b1;
assign reset_h = 1'b0;

DE2_115_SOPC DE2_115_SOPC_inst(

                       .clk_50(CLOCK_50),
                       .reset_n(reset_n),
                       .altpll_25(clk_25),
                       .altpll_io(),
                       .altpll_sdram(DRAM_CLK),
                       .altpll_sys(),                       
                      

                        

                       .zs_addr_from_the_sdram(DRAM_ADDR),
                       .zs_ba_from_the_sdram(DRAM_BA),
                       .zs_cas_n_from_the_sdram(DRAM_CAS_N),
                       .zs_cke_from_the_sdram(DRAM_CKE),
                       .zs_cs_n_from_the_sdram(DRAM_CS_N),
                       .zs_dq_to_and_from_the_sdram(DRAM_DQ),
                       .zs_dqm_from_the_sdram(DRAM_DQM),
                       .zs_ras_n_from_the_sdram(DRAM_RAS_N),
                       .zs_we_n_from_the_sdram(DRAM_WE_N),
                       


                       .SRAM_ADDR_from_the_sram(SRAM_ADDR),
                       .SRAM_CE_n_from_the_sram(SRAM_CE_N),
                       .SRAM_DQ_to_and_from_the_sram(SRAM_DQ),
                       .SRAM_LB_n_from_the_sram(SRAM_LB_N),
                       .SRAM_OE_n_from_the_sram(SRAM_OE_N),
                       .SRAM_UB_n_from_the_sram(SRAM_UB_N),
                       .SRAM_WE_n_from_the_sram(SRAM_WE_N),
                       
                       

							  .usb_conduit_end_DATA(OTG_DATA),
							  .usb_conduit_end_ADDR(OTG_ADDR),
							  .usb_conduit_end_RD_N(OTG_RD_N),
							  .usb_conduit_end_WR_N(OTG_WR_N),
							  .usb_conduit_end_CS_N(OTG_CS_N),
							  .usb_conduit_end_RST_N(OTG_RST_N),
							  .usb_conduit_end_INT(OTG_INT),
						
							  .mouse_data_EXPORT_DATA( Mouse_data),
                    );                    

logic[9:0] 	DrawX, DrawY;	
logic[31:0] Mouse_data;
HexDriver hex_inst_0 (Mouse_data[3:0], HEX0);
HexDriver hex_inst_1 (Mouse_data[7:4], HEX1);
HexDriver hex_inst_2 (Mouse_data[19:16], HEX2);
HexDriver hex_inst_3 (Mouse_data[23:20], HEX3);
	 
logic is_ball;
vga_clk vga_clk_instance( .*, .inclk0(CLOCK_50), .c0(VGA_CLK));
VGA_controller VC (.Clk(CLOCK_50), .Reset(reset_h), .*);
color_mapper color_instance(.*);
ball ball_instance(.Clk(CLOCK_50), .Reset(reset_h), .X(10'd320), .Y(10'd320), .*, .frame_clk(VGA_VS));

assign	FL_RST_N = reset_n;
assign	FL_WP_N = 1'b1;




assign LCD_BLON = 0;
assign LCD_ON = 1'b1;

wire io_dir;
wire action;
assign io_dir = KEY[0] & action;



assign GPIO[17:0] = (io_dir)?GPIO[35:18]:18'hz;
assign GPIO[35:18] = (io_dir)?GPIO[17:0]:18'hz;



assign HSMC_D[1:0] = (io_dir)?HSMC_D[3:2]:2'hz;
assign HSMC_D[3:2] = (io_dir)?HSMC_D[1:0]:2'hz;

assign HSMC_TX_D_P = HSMC_RX_D_P;




assign HSMC_CLKOUT_P1 = HSMC_CLKIN_P1;
assign HSMC_CLKOUT_P2 = HSMC_CLKIN_P2;
assign HSMC_CLKOUT0 = HSMC_CLKIN0;



assign ENET0_GTX_CLK = ENET0_INT_N;

assign ENET0_MDC = ENET0_RX_COL;
assign ENET0_RST_N = ENET0_RX_CRS;

assign ENET0_TX_DATA = ENET0_RX_DATA;
assign ENET0_TX_EN = ENET0_RX_ER;
assign ENET0_TX_ER = ENET0_TX_CLK;

assign ENET1_GTX_CLK = ENET1_INT_N;

assign ENET1_MDC = ENET1_RX_COL;
assign ENET1_RST_N = ENET1_RX_CRS;

assign ENET1_TX_DATA = ENET1_RX_DATA;
assign ENET1_TX_EN = ENET1_RX_ER;
assign ENET1_TX_ER = ENET1_TX_CLK;






assign TD_RESET_N = TD_VS;
assign action = FL_RY & TD_HS & TD_CLK27 & (TD_DATA == 8'hff);



assign PS2_CLK = PS2_DAT;
assign PS2_CLK2 = PS2_DAT2;

endmodule
module final_top(


	CLOCK_50,
   CLOCK2_50,
   CLOCK3_50,
	ENETCLK_25,


	SMA_CLKIN,
	SMA_CLKOUT,


	LEDG,
	LEDR,


	KEY,


	SW,


	HEX0,
	HEX1,
	HEX2,
	HEX3,
	HEX4,
	HEX5,
	HEX6,
	HEX7,


	LCD_BLON,
	LCD_DATA,
	LCD_EN,
	LCD_ON,
	LCD_RS,
	LCD_RW,


	UART_CTS,
	UART_RTS,
	UART_RXD,
	UART_TXD,


	PS2_CLK,
	PS2_DAT,
	PS2_CLK2,
	PS2_DAT2,


	SD_CLK,
	SD_CMD,
	SD_DAT,
	SD_WP_N,


	VGA_B,
	VGA_BLANK_N,
	VGA_CLK,
	VGA_G,
	VGA_HS,
	VGA_R,
	VGA_SYNC_N,
	VGA_VS,


	AUD_ADCDAT,
	AUD_ADCLRCK,
	AUD_BCLK,
	AUD_DACDAT,
	AUD_DACLRCK,
	AUD_XCK,


	EEP_I2C_SCLK,
	EEP_I2C_SDAT,


	I2C_SCLK,
	I2C_SDAT,


	ENET0_GTX_CLK,
	ENET0_INT_N,
	ENET0_MDC,
	ENET0_MDIO,
	ENET0_RST_N,
	ENET0_RX_CLK,
	ENET0_RX_COL,
	ENET0_RX_CRS,
	ENET0_RX_DATA,
	ENET0_RX_DV,
	ENET0_RX_ER,
	ENET0_TX_CLK,
	ENET0_TX_DATA,
	ENET0_TX_EN,
	ENET0_TX_ER,
	ENET0_LINK100,


	ENET1_GTX_CLK,
	ENET1_INT_N,
	ENET1_MDC,
	ENET1_MDIO,
	ENET1_RST_N,
	ENET1_RX_CLK,
	ENET1_RX_COL,
	ENET1_RX_CRS,
	ENET1_RX_DATA,
	ENET1_RX_DV,
	ENET1_RX_ER,
	ENET1_TX_CLK,
	ENET1_TX_DATA,
	ENET1_TX_EN,
	ENET1_TX_ER,
	ENET1_LINK100,


	TD_CLK27,
	TD_DATA,
	TD_HS,
	TD_RESET_N,
	TD_VS,


   OTG_DATA,
   OTG_ADDR,
   OTG_CS_N,
   OTG_WR_N,
   OTG_RD_N,
   OTG_INT,
   OTG_RST_N,
	 

	IRDA_RXD,


	DRAM_ADDR,
	DRAM_BA,
	DRAM_CAS_N,
	DRAM_CKE,
	DRAM_CLK,
	DRAM_CS_N,
	DRAM_DQ,
	DRAM_DQM,
	DRAM_RAS_N,
	DRAM_WE_N,


	SRAM_ADDR,
	SRAM_CE_N,
	SRAM_DQ,
	SRAM_LB_N,
	SRAM_OE_N,
	SRAM_UB_N,
	SRAM_WE_N,


	FL_ADDR,
	FL_CE_N,
	FL_DQ,
	FL_OE_N,
	FL_RST_N,
	FL_RY,
	FL_WE_N,
	FL_WP_N,


	GPIO,




	HSMC_CLKIN_P1,
	HSMC_CLKIN_P2,
	HSMC_CLKIN0,


	HSMC_CLKOUT_P1,
	HSMC_CLKOUT_P2,
	HSMC_CLKOUT0,
	HSMC_D,

	HSMC_RX_D_P,

	HSMC_TX_D_P,

    EX_IO	
);












input		          		   CLOCK_50;
input		          		   CLOCK2_50;
input		          		   CLOCK3_50;
input		          		   ENETCLK_25;


input		          		   SMA_CLKIN;
output		          	   SMA_CLKOUT;


output		     [8:0]		LEDG;
output		    [17:0]		LEDR;


input		       [3:0]		KEY;


input		      [17:0]		SW;


output		     [6:0]		HEX0;
output		     [6:0]		HEX1;
output		     [6:0]		HEX2;
output		     [6:0]		HEX3;
output		     [6:0]		HEX4;
output		     [6:0]		HEX5;
output		     [6:0]		HEX6;
output		     [6:0]		HEX7;


output		          		LCD_BLON;
inout		       [7:0]		LCD_DATA;
output		          		LCD_EN;
output		          		LCD_ON;
output		          		LCD_RS;
output		          		LCD_RW;


output		          		UART_CTS;
input		          	   	UART_RTS;
input		          		   UART_RXD;
output		          		UART_TXD;


inout		          		   PS2_CLK;
inout		          		   PS2_DAT;
inout		          		   PS2_CLK2;
inout		          		   PS2_DAT2;


output		          		SD_CLK;
inout		          	    	SD_CMD;
inout		       [3:0]		SD_DAT;
input		          	   	SD_WP_N;


output		     [7:0]		VGA_B;
output		          		VGA_BLANK_N;
output		          		VGA_CLK;
output		     [7:0]		VGA_G;
output		          		VGA_HS;
output		     [7:0]		VGA_R;
output		          		VGA_SYNC_N;
output		          		VGA_VS;


input		          	   	AUD_ADCDAT;
inout		          		   AUD_ADCLRCK;
inout		          		   AUD_BCLK;
output		          		AUD_DACDAT;
inout		          		   AUD_DACLRCK;
output		          		AUD_XCK;


output		          		EEP_I2C_SCLK;
inout		          	   	EEP_I2C_SDAT;


output		          		I2C_SCLK;
inout		          		   I2C_SDAT;


output		          		ENET0_GTX_CLK;
input		          	   	ENET0_INT_N;
output		          		ENET0_MDC;
inout		          	   	ENET0_MDIO;
output		          	 	ENET0_RST_N;
input		          		   ENET0_RX_CLK;
input		          	    	ENET0_RX_COL;
input		             		ENET0_RX_CRS;
input		       [3:0]		ENET0_RX_DATA;
input		             		ENET0_RX_DV;
input		          		   ENET0_RX_ER;
input		          		   ENET0_TX_CLK;
output		    [3:0]		ENET0_TX_DATA;
output		          		ENET0_TX_EN;
output		          		ENET0_TX_ER;
input		          		   ENET0_LINK100;


output		          		ENET1_GTX_CLK;
input		          		   ENET1_INT_N;
output		          		ENET1_MDC;
inout		          		   ENET1_MDIO;
output		          		ENET1_RST_N;
input		          		   ENET1_RX_CLK;
input		          		   ENET1_RX_COL;
input		          		   ENET1_RX_CRS;
input		        [3:0]		ENET1_RX_DATA;
input		            		ENET1_RX_DV;
input		          	   	ENET1_RX_ER;
input		          	   	ENET1_TX_CLK;
output		     [3:0]		ENET1_TX_DATA;
output		          		ENET1_TX_EN;
output		          		ENET1_TX_ER;
input		          		   ENET1_LINK100;


input		          	   	TD_CLK27;
input		     [7:0]		   TD_DATA;
input		          		   TD_HS;
output		          		TD_RESET_N;
input		          	    	TD_VS;



inout           [15:0]     OTG_DATA;
output          [1:0]      OTG_ADDR;
output                     OTG_CS_N;
output                     OTG_WR_N;
output                     OTG_RD_N;
input            		      OTG_INT;
output                     OTG_RST_N;



input		          		   IRDA_RXD;


output		    [12:0]		DRAM_ADDR;
output		    [1:0]		DRAM_BA;
output		          		DRAM_CAS_N;
output		          		DRAM_CKE;
output		          		DRAM_CLK;
output		          		DRAM_CS_N;
inout		      [31:0]		DRAM_DQ;
output		    [3:0]		DRAM_DQM;
output		          		DRAM_RAS_N;
output		          		DRAM_WE_N;


output		    [19:0]		SRAM_ADDR;
output		          		SRAM_CE_N;
inout		      [15:0]		SRAM_DQ;
output		          		SRAM_LB_N;
output		          		SRAM_OE_N;
output		          		SRAM_UB_N;
output		          		SRAM_WE_N;


output		   [22:0]		FL_ADDR;
output		          		FL_CE_N;
inout		       [7:0]		FL_DQ;
output		          		FL_OE_N;
output		          		FL_RST_N;
input		          	   	FL_RY;
output		          		FL_WE_N;
output		          		FL_WP_N;


inout		      [35:0]		GPIO;





input		          	   	HSMC_CLKIN_P1;
input		          	   	HSMC_CLKIN_P2;
input		          		   HSMC_CLKIN0;


output		          		HSMC_CLKOUT_P1;
output		          		HSMC_CLKOUT_P2;
output		          		HSMC_CLKOUT0;
inout		        [3:0]		HSMC_D;

input		       [16:0]		HSMC_RX_D_P;

output		    [16:0]		HSMC_TX_D_P;


inout		       [6:0]		EX_IO;





wire        HEX0P;
wire        HEX1P;
wire        HEX2P;
wire        HEX3P;
wire        HEX4P;
wire        HEX5P;
wire        HEX6P;
wire        HEX7P;

wire        clk_25;

wire        reset_n;




assign reset_n = 1'b1;
assign reset_h = 1'b0;

DE2_115_SOPC DE2_115_SOPC_inst(

                       .clk_50(CLOCK_50),
                       .reset_n(reset_n),
                       .altpll_25(clk_25),
                       .altpll_io(),
                       .altpll_sdram(DRAM_CLK),
                       .altpll_sys(),                       
                      

                        

                       .zs_addr_from_the_sdram(DRAM_ADDR),
                       .zs_ba_from_the_sdram(DRAM_BA),
                       .zs_cas_n_from_the_sdram(DRAM_CAS_N),
                       .zs_cke_from_the_sdram(DRAM_CKE),
                       .zs_cs_n_from_the_sdram(DRAM_CS_N),
                       .zs_dq_to_and_from_the_sdram(DRAM_DQ),
                       .zs_dqm_from_the_sdram(DRAM_DQM),
                       .zs_ras_n_from_the_sdram(DRAM_RAS_N),
                       .zs_we_n_from_the_sdram(DRAM_WE_N),
                       


                       .SRAM_ADDR_from_the_sram(SRAM_ADDR),
                       .SRAM_CE_n_from_the_sram(SRAM_CE_N),
                       .SRAM_DQ_to_and_from_the_sram(SRAM_DQ),
                       .SRAM_LB_n_from_the_sram(SRAM_LB_N),
                       .SRAM_OE_n_from_the_sram(SRAM_OE_N),
                       .SRAM_UB_n_from_the_sram(SRAM_UB_N),
                       .SRAM_WE_n_from_the_sram(SRAM_WE_N),
                       
                       

							  .usb_conduit_end_DATA(OTG_DATA),
							  .usb_conduit_end_ADDR(OTG_ADDR),
							  .usb_conduit_end_RD_N(OTG_RD_N),
							  .usb_conduit_end_WR_N(OTG_WR_N),
							  .usb_conduit_end_CS_N(OTG_CS_N),
							  .usb_conduit_end_RST_N(OTG_RST_N),
							  .usb_conduit_end_INT(OTG_INT),
						
							  .mouse_data_EXPORT_DATA( Mouse_data),
                    );                    

logic[9:0] 	DrawX, DrawY;	
logic[31:0] Mouse_data;
HexDriver hex_inst_0 (Mouse_data[3:0], HEX0);
HexDriver hex_inst_1 (Mouse_data[7:4], HEX1);
HexDriver hex_inst_2 (Mouse_data[19:16], HEX2);
HexDriver hex_inst_3 (Mouse_data[23:20], HEX3);
	 
logic is_ball;
vga_clk vga_clk_instance( .*, .inclk0(CLOCK_50), .c0(VGA_CLK));
VGA_controller VC (.Clk(CLOCK_50), .Reset(reset_h), .*);
color_mapper color_instance(.*);
ball ball_instance(.Clk(CLOCK_50), .Reset(reset_h), .X(10'd320), .Y(10'd320), .*, .frame_clk(VGA_VS));

assign	FL_RST_N = reset_n;
assign	FL_WP_N = 1'b1;




assign LCD_BLON = 0;
assign LCD_ON = 1'b1;

wire io_dir;
wire action;
assign io_dir = KEY[0] & action;



assign GPIO[17:0] = (io_dir)?GPIO[35:18]:18'hz;
assign GPIO[35:18] = (io_dir)?GPIO[17:0]:18'hz;



assign HSMC_D[1:0] = (io_dir)?HSMC_D[3:2]:2'hz;
assign HSMC_D[3:2] = (io_dir)?HSMC_D[1:0]:2'hz;

assign HSMC_TX_D_P = HSMC_RX_D_P;




assign HSMC_CLKOUT_P1 = HSMC_CLKIN_P1;
assign HSMC_CLKOUT_P2 = HSMC_CLKIN_P2;
assign HSMC_CLKOUT0 = HSMC_CLKIN0;



assign ENET0_GTX_CLK = ENET0_INT_N;

assign ENET0_MDC = ENET0_RX_COL;
assign ENET0_RST_N = ENET0_RX_CRS;

assign ENET0_TX_DATA = ENET0_RX_DATA;
assign ENET0_TX_EN = ENET0_RX_ER;
assign ENET0_TX_ER = ENET0_TX_CLK;

assign ENET1_GTX_CLK = ENET1_INT_N;

assign ENET1_MDC = ENET1_RX_COL;
assign ENET1_RST_N = ENET1_RX_CRS;

assign ENET1_TX_DATA = ENET1_RX_DATA;
assign ENET1_TX_EN = ENET1_RX_ER;
assign ENET1_TX_ER = ENET1_TX_CLK;






assign TD_RESET_N = TD_VS;
assign action = FL_RY & TD_HS & TD_CLK27 & (TD_DATA == 8'hff);



assign PS2_CLK = PS2_DAT;
assign PS2_CLK2 = PS2_DAT2;

endmodule