data/full_repos/permissive/218779832/pipeControl_old.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/218779832/pipeControl_old.v:42: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'CCG1\'\nmodule CCG1\n       ^~~~\n                                                                            : ... Top module \'CCG2\'\nmodule CCG2\n       ^~~~\n                                                                            : ... Top module \'CCG3\'\nmodule CCG3\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/218779832/pipeControl_old.v:67: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance CCG2\nwrite <= opcode_in_1[2:0];\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/pipeControl_old.v:71: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'flagCheck_1\' generates 1 bits.\n                                                                         : ... In instance CCG2\nflag1 <= flagCheck_1; \n      ^~\n%Warning-WIDTH: data/full_repos/permissive/218779832/pipeControl_old.v:75: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'flag1\' generates 8 bits.\n                                                                         : ... In instance CCG2\nassign flagCheck = flag1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/218779832/pipeControl_old.v:76: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'write\' generates 8 bits.\n                                                                         : ... In instance CCG2\nassign write_address = write;\n                     ^\n%Error: Exiting due to 5 warning(s)\n'
module CCG3
(
    input clk,
    input   [7:0]   opcode,
    input       flagCheck,
    input  [2:0]     write_address,
    input  [7:0]     NPC_in,
    input  [7:0]     OR2,
    output wire RD,  WR,
    output wire L_PC,
    output wire S_AL,
    output wire S11, S10,
    output wire S20,
    output wire S30, S40,
    output wire S50,

    output wire [1:0] rw,
    output wire [2:0] mux_sel,
    output wire clr , we
);

reg [10:0] controlBits;
reg [5:0] muxBits;


assign {RD, WR, clr , we , mux_sel , rw , L_PC,S_AL} = controlBits;
assign {S11, S10, S20, S30, S40, S50} = muxBits;


always @ (negedge clk)
begin
    casex (opcode)
    8'b0000_0_000 : begin

        controlBits <= 11'b00_00000_00_0_0;

        muxBits <= 6'b00_0000;
    end
    
    8'b0000_0_001 : begin

        controlBits <= 11'b00_10000_00_0_0;

       muxBits <= 6'b00_0001; 
    end

    8'b0000_0_010 : begin


        controlBits <= 11'b00_00000_00_0_1;

         muxBits <= 6'b00_0000;
    end

    8'b0000_0_011 : begin

         controlBits <= 11'b00_00000_00_1_0;

        muxBits <= 6'b01_0000;
    end

    8'b0000_0_100 : begin

         controlBits <= 11'b00_00000_00_1_0;

         muxBits <= 6'b11_0000;
    end

    8'b0000_0_101 : begin

        controlBits <= 11'b01_00000_01_1_0;

         muxBits <= 6'b01_1000;
    end
    8'b0000_0_110 : begin

         controlBits <= 11'b01_00000_01_1_0;

         muxBits <= 6'b11_1000;
    end
    8'b0000_0_111 : begin

         controlBits <= 11'b10_00000_10_1_0;

         muxBits <= 6'b10_1000;
    end
    8'b0000_1_xxx : begin
        if (flagCheck) begin

             controlBits <= 11'b00_00000_00_1_0; 
             muxBits <= 6'b01_0000;
        end else begin

             controlBits <= 11'b00_00000_00_0_0;
             muxBits <= 6'b00_0000;
        end
    end
    8'b0001_0_000 : begin

       controlBits <= 11'b00_00000_11_0_0;
       muxBits <= 6'b00_0000;
    end
    8'b0001_0_xxx : begin

        controlBits <= 11'b00_01000_00_0_0;
        muxBits <= 6'b00_0000;
    end
    8'b0001_1_000 : begin

         controlBits <= 11'b00_01100_00_0_0;
         muxBits <= 6'b00_0000;
    end
    8'b0001_1_xxx : begin

         controlBits <= 11'b00_01101_00_0_0;
         muxBits <= 6'b00_0000;
    end


    8'b0010_0_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0100;
    end


    8'b0010_1_xxx : begin
        if (flagCheck) begin

             controlBits <= 11'b00_00000_00_1_0;
             muxBits <= 6'b11_0000;
        end else begin
             controlBits <= 11'b00_00000_00_0_0;
             muxBits <= 6'b00_0000;
        end
    end

    8'b0011_0_xxx : begin
        if (flagCheck) begin

             controlBits <= 11'b01_00000_01_1_0;
             muxBits <= 6'b01_1000;
        end else begin
             controlBits <= 11'b00_00000_00_0_0;
             muxBits <= 6'b00_0000;
        end
    end

    8'b0011_1_xxx : begin
        if (flagCheck) begin

             controlBits <= 11'b01_00000_01_1_0;
             muxBits <= 6'b11_1000;
        end else begin
             controlBits <= 11'b00_00000_00_0_0;
             muxBits <= 6'b00_0000;
        end
    end

    8'b0100_0_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0100;
    end
    8'b0100_1_xxx : begin
        if (flagCheck) begin

             controlBits <= 11'b10_00000_10_1_0;
             muxBits <= 6'b10_1000;
        end else begin
             controlBits <= 11'b00_00000_00_0_0;
             muxBits <= 6'b00_0000;
        end
    end
    8'b0101_0_xxx : begin

         controlBits <= 11'b00_0111_00_0_1;
         muxBits <= 6'b00_0100;
    end
    8'b0101_1_xxx : begin

         controlBits <= 11'b00_01010_00_0_0;
         muxBits <= 6'b00_0000;
    end

    8'b0110_0_xxx : begin

        controlBits <= 11'b01_00000_00_0_0;
         muxBits <= 6'b00_0001;
    end
    8'b0110_1_xxx : begin

         controlBits <= 11'b01_00000_01_0_0;
         muxBits <= 6'b00_1001;
    end
    8'b0111_0_000 : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0000;
    end
    8'b0111_0_xxx : begin


         controlBits <= 11'b10_01110_00_0_0;
         muxBits <= 6'b00_0000;
    end
    8'b0111_1_xxx : begin

         controlBits <= 11'b10_01110_10_0_0;
         muxBits <= 6'b00_1000;
    end
    8'b1000_0_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0000;
    end
    8'b1000_1_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0110;
    end
    8'b1001_0_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0000;
    end
    8'b1001_1_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0110;
    end
    8'b1010_0_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0000;
    end
    8'b1010_1_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0110;
    end
    8'b1011_0_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0000;
    end
    8'b1011_1_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 6'b00_0110;
    end
    8'b1100_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <=6'b00_0000;
    end
    8'b1100_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1; 
        muxBits <= 6'b00_0110;
    end
    8'b1101_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1; 
        muxBits <= 6'b00_0000;
    end
    8'b1101_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;  
        muxBits <= 6'b00_0110;
    end
    8'b1110_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1; 
        muxBits <= 6'b00_0000;
    end
    8'b1110_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;  
        muxBits <= 6'b00_0110;
    end


    endcase
end

endmodule
module CCG3
(
    input clk,
    input   [7:0]   opcode,
    input       flagCheck,
    input  [2:0]     write_address,
    input  [7:0]     NPC_in,
    input  [7:0]     OR2,
    output wire RD,  WR,
    output wire L_PC,
    output wire S_AL,
    output wire S11, S10,
    output wire S20,
    output wire S30, S40,
    output wire S50,

    output wire [1:0] rw,
    output wire [2:0] mux_sel,
    output wire clr , we
);


reg [10:0] controlBits;
reg [5:0] muxBits;


assign {RD, WR, clr , we , mux_sel , rw , L_PC,S_AL} = controlBits;
assign {S11, S10, S20, S30, S40, S50} = muxBits;


always @ (negedge clk)
begin
    casex (opcode)
    8'b0000_0_000 : begin

        controlBits <= 11'b00_00000_00_0_0;

        muxBits <= 6'b00_0000;
    end
    
    8'b0000_0_001 : begin

        controlBits <= 11'b00_10000_00_0_0;

       muxBits <= 6'b00_0001; 
    end

    8'b0000_0_010 : begin


        controlBits <= 11'b00_00000_00_0_1;

         muxBits <= 6'b00_0000;
    end

    8'b0000_0_011 : begin

         controlBits <= 11'b00_00000_00_1_0;

        muxBits <= 6'b01_0000;
    end

    8'b0000_0_100 : begin

         controlBits <= 11'b00_00000_00_1_0;

         muxBits <= 6'b11_0000;
    end

    8'b0000_0_101 : begin

        controlBits <= 11'b01_00000_01_1_0;

         muxBits <= 6'b01_1000;
    end
    8'b0000_0_110 : begin

         controlBits <= 11'b01_00000_01_1_0;

         muxBits <= 6'b11_1000;
    end
    8'b0000_0_111 : begin

         controlBits <= 11'b10_00000_10_1_0;

         muxBits <= 6'b10_1000;
    end
    8'b0000_1_xxx : begin
        if (flagCheck) begin

             controlBits <= 11'b00_00000_00_1_0; 
             muxBits <= 6'b01_0000;
        end else begin

             controlBits <= 11'b00_00000_00_0_0;
             muxBits <= 6'b00_0000;
        end
    end
    8'b0001_0_000 : begin

       controlBits <= 11'b00_00000_11_0_0;
       muxBits <= 6'b00_0000;
    end
    8'b0001_0_xxx : begin

        controlBits <= 11'b00_01000_00_0_0;
        muxBits <= 6'b00_0000;
    end
    8'b0001_1_000 : begin

         controlBits <= 11'b00_01100_00_0_0;
         muxBits <= 6'b00_0000;
    end
    8'b0001_1_xxx : begin

         controlBits <= 11'b00_01101_00_0_0;
         muxBits <= 6'b00_0000;
    end


    8'b0010_0_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0100;
    end


    8'b0010_1_xxx : begin
        if (flagCheck) begin

             controlBits <= 11'b00_00000_00_1_0;
             muxBits <= 6'b11_0000;
        end else begin
             controlBits <= 11'b00_00000_00_0_0;
             muxBits <= 6'b00_0000;
        end
    end

    8'b0011_0_xxx : begin
        if (flagCheck) begin

             controlBits <= 11'b01_00000_01_1_0;
             muxBits <= 6'b01_1000;
        end else begin
             controlBits <= 11'b00_00000_00_0_0;
             muxBits <= 6'b00_0000;
        end
    end

    8'b0011_1_xxx : begin
        if (flagCheck) begin

             controlBits <= 11'b01_00000_01_1_0;
             muxBits <= 6'b11_1000;
        end else begin
             controlBits <= 11'b00_00000_00_0_0;
             muxBits <= 6'b00_0000;
        end
    end

    8'b0100_0_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0100;
    end
    8'b0100_1_xxx : begin
        if (flagCheck) begin

             controlBits <= 11'b10_00000_10_1_0;
             muxBits <= 6'b10_1000;
        end else begin
             controlBits <= 11'b00_00000_00_0_0;
             muxBits <= 6'b00_0000;
        end
    end
    8'b0101_0_xxx : begin

         controlBits <= 11'b00_0111_00_0_1;
         muxBits <= 6'b00_0100;
    end
    8'b0101_1_xxx : begin

         controlBits <= 11'b00_01010_00_0_0;
         muxBits <= 6'b00_0000;
    end

    8'b0110_0_xxx : begin

        controlBits <= 11'b01_00000_00_0_0;
         muxBits <= 6'b00_0001;
    end
    8'b0110_1_xxx : begin

         controlBits <= 11'b01_00000_01_0_0;
         muxBits <= 6'b00_1001;
    end
    8'b0111_0_000 : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0000;
    end
    8'b0111_0_xxx : begin


         controlBits <= 11'b10_01110_00_0_0;
         muxBits <= 6'b00_0000;
    end
    8'b0111_1_xxx : begin

         controlBits <= 11'b10_01110_10_0_0;
         muxBits <= 6'b00_1000;
    end
    8'b1000_0_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0000;
    end
    8'b1000_1_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0110;
    end
    8'b1001_0_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0000;
    end
    8'b1001_1_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0110;
    end
    8'b1010_0_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0000;
    end
    8'b1010_1_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0110;
    end
    8'b1011_0_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
         muxBits <= 6'b00_0000;
    end
    8'b1011_1_xxx : begin

         controlBits <= 11'b00_01011_00_0_1;
        muxBits <= 6'b00_0110;
    end
    8'b1100_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;
        muxBits <=6'b00_0000;
    end
    8'b1100_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1; 
        muxBits <= 6'b00_0110;
    end
    8'b1101_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1; 
        muxBits <= 6'b00_0000;
    end
    8'b1101_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;  
        muxBits <= 6'b00_0110;
    end
    8'b1110_0_xxx : begin

        controlBits <= 11'b00_01011_00_0_1; 
        muxBits <= 6'b00_0000;
    end
    8'b1110_1_xxx : begin

        controlBits <= 11'b00_01011_00_0_1;  
        muxBits <= 6'b00_0110;
    end


    endcase
end

endmodule