data/full_repos/permissive/185914332/wash_fsm.v
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data/verilator_xmls/de8b594e-f5ce-4828-ba10-9cf4fa40ead8.xml
module wash_fsm (clk,ready,water_in,wash,drain,speed,heat_r,reset,start,full,cold,empty);

	input clk, reset, start, full, cold, empty;
	output ready, water_in, wash,drain, speed, heat_r; 

	reg ready, water_in, wash, drain, speed, heat_r;  
	
	parameter state0=0, state1=1, state2=2, state3=3, state4=4;
	reg[2:0] nxt_st = state0, state = state0;
	

	

	reg[27:0] t = 0 ; 

	parameter st2_counter = 200000000 , st4_counter = 100000000 ;

	reg countdown_on = 0; 


	always @(posedge clk) 
		begin: state_change_countdown	
				if (countdown_on) t = t + 1;
				else t = 0;
		end 


	always @(*)
		begin : next_state_logic
			heat_r = 0;
			countdown_on = 0;
			nxt_st= state;
				case (state)		
				state0: begin
								countdown_on = 0;
								if (start) nxt_st = state1;
						  end
				state1: begin
								countdown_on = 0;
								if (full) nxt_st = state2;
						  end
				state2: begin
								if (cold) heat_r = 1;
								else heat_r = 0;
								countdown_on = 1;
								if (t == st2_counter-1) 
									begin
										nxt_st = state3;
										heat_r = 0;
									end							
						  end
				state3: begin
								countdown_on = 0;
								if (empty) nxt_st = state4;
						  end
				state4: begin
								countdown_on = 1;
								if (t == st4_counter-1) nxt_st = state0;
						  end
				
				default: nxt_st = state0;
			endcase 
		end 


	always @(posedge reset, posedge clk)
		begin : reset_detector
			if (reset) state <= state0;
			else state <= nxt_st;
		end


	always @(state)
		begin : output_logic
				case (state)
					state0: begin ready=1;water_in=0;wash=0;drain=0;speed=0;end 
					state1: begin ready=0;water_in=1;wash=0;drain=0;speed=0;end 
					state2: begin ready=0;water_in=0;wash=1;drain=0;speed=0;end 
					state3: begin ready=0;water_in=0;wash=0;drain=1;speed=0;end
					state4: begin ready=0;water_in=0;wash=0;drain=0;speed=1;end 
					default begin ready=1;water_in=0;wash=0;drain=0;speed=0;end
				endcase
		end		
		
endmodule
module wash_fsm (clk,ready,water_in,wash,drain,speed,heat_r,reset,start,full,cold,empty);


	input clk, reset, start, full, cold, empty;
	output ready, water_in, wash,drain, speed, heat_r; 

	reg ready, water_in, wash, drain, speed, heat_r;  
	
	parameter state0=0, state1=1, state2=2, state3=3, state4=4;
	reg[2:0] nxt_st = state0, state = state0;
	

	

	reg[27:0] t = 0 ; 

	parameter st2_counter = 200000000 , st4_counter = 100000000 ;

	reg countdown_on = 0; 


	always @(posedge clk) 
		begin: state_change_countdown	
				if (countdown_on) t = t + 1;
				else t = 0;
		end 


	always @(*)
		begin : next_state_logic
			heat_r = 0;
			countdown_on = 0;
			nxt_st= state;
				case (state)		
				state0: begin
								countdown_on = 0;
								if (start) nxt_st = state1;
						  end
				state1: begin
								countdown_on = 0;
								if (full) nxt_st = state2;
						  end
				state2: begin
								if (cold) heat_r = 1;
								else heat_r = 0;
								countdown_on = 1;
								if (t == st2_counter-1) 
									begin
										nxt_st = state3;
										heat_r = 0;
									end							
						  end
				state3: begin
								countdown_on = 0;
								if (empty) nxt_st = state4;
						  end
				state4: begin
								countdown_on = 1;
								if (t == st4_counter-1) nxt_st = state0;
						  end
				
				default: nxt_st = state0;
			endcase 
		end 


	always @(posedge reset, posedge clk)
		begin : reset_detector
			if (reset) state <= state0;
			else state <= nxt_st;
		end


	always @(state)
		begin : output_logic
				case (state)
					state0: begin ready=1;water_in=0;wash=0;drain=0;speed=0;end 
					state1: begin ready=0;water_in=1;wash=0;drain=0;speed=0;end 
					state2: begin ready=0;water_in=0;wash=1;drain=0;speed=0;end 
					state3: begin ready=0;water_in=0;wash=0;drain=1;speed=0;end
					state4: begin ready=0;water_in=0;wash=0;drain=0;speed=1;end 
					default begin ready=1;water_in=0;wash=0;drain=0;speed=0;end
				endcase
		end		
		
endmodule