data/full_repos/permissive/201488448/2_circuits/2_sequential/07_latch.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/07_latch.v:8: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                             : ... In instance top_module\n            q <= d;\n            ^\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input d, 
    input ena,
    output q);

    always@(ena) begin
        if(ena)
            q <= d;
    end
    
endmodule
module top_module (
    input d, 
    input ena,
    output q);


    always@(ena) begin
        if(ena)
            q <= d;
    end
    
endmodule