data/full_repos/permissive/197614074/top.v
1: b"%Error: data/full_repos/permissive/197614074/top.v:30: syntax error, unexpected class, expecting IDENTIFIER or '[' or do or final\n output   [10:0]   class\n                   ^~~~~\n%Error: data/full_repos/permissive/197614074/top.v:37: syntax error, unexpected initial\n  initial begin\n  ^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module top #(
		parameter  	WIDTH 			= 	32,
		parameter  	HEIGHT 			= 	32,
		parameter  	CHANNEL 			= 	3)(
	input 								clk,
	output 								hsync,
	output 								vsync,
	output 		[7:0] 				rgb,
	output    	        			done,
	output		 [10:0]			class
    );

	 reg 		[WIDTH*HEIGHT*CHANNEL*8-1:0] img;
	 wire												out;
	 reg enable1,enable2;
	 reg 		[20:0]		address;
		initial begin
			enable1=1;
		end
		ROM ROM1  (
			.clka(clk),
			.ena(enable1),
			.addra(address),
			.douta(out)
		);
		processing_element instance_name (
				.clk(clk), 
				.enable(enable2), 
				.reset(reset), 
				.pixel(img), 
				.done(done), 
				.decied(class)
			);
		vga_sync vga1 (
			.clk(clk),  
			.hsync(hsync), 
			.vsync(vsync), 
			.video_on(), 
			.h_video_on(h_video_on),
			.v_video_on(v_video_on),
			.pixel_x(pixel_x), 
			.pixel_y(pixel_y)
		);
		
		pixel_generator pixel(
			.clk(clk), 
			.pixel_x(pixel_x), 
			.pixel_y(pixel_y), 
			.pixel_in(pixel_in), 
			.h_video_on(h_video_on), 
			.v_video_on(v_video_on), 
			.rgb(rgb)
		);
		always @ (posedge clk)begin		
				if (address < WIDTH*HEIGHT*CHANNEL) begin			
					img[address*8 +: 8]=out;
					address = address + 1;
					enable1=1;
				end
				else if (address < WIDTH*HEIGHT*CHANNEL) begin
					enable2=1;enable1=0;
				end
				if (done)begin
					enable2=0;
				end
		end
endmodule
module top #(
		parameter  	WIDTH 			= 	32,
		parameter  	HEIGHT 			= 	32,
		parameter  	CHANNEL 			= 	3)(
	input 								clk,
	output 								hsync,
	output 								vsync,
	output 		[7:0] 				rgb,
	output    	        			done,
	output		 [10:0]			class
    );


	 reg 		[WIDTH*HEIGHT*CHANNEL*8-1:0] img;
	 wire												out;
	 reg enable1,enable2;
	 reg 		[20:0]		address;
		initial begin
			enable1=1;
		end
		ROM ROM1  (
			.clka(clk),
			.ena(enable1),
			.addra(address),
			.douta(out)
		);
		processing_element instance_name (
				.clk(clk), 
				.enable(enable2), 
				.reset(reset), 
				.pixel(img), 
				.done(done), 
				.decied(class)
			);
		vga_sync vga1 (
			.clk(clk),  
			.hsync(hsync), 
			.vsync(vsync), 
			.video_on(), 
			.h_video_on(h_video_on),
			.v_video_on(v_video_on),
			.pixel_x(pixel_x), 
			.pixel_y(pixel_y)
		);
		
		pixel_generator pixel(
			.clk(clk), 
			.pixel_x(pixel_x), 
			.pixel_y(pixel_y), 
			.pixel_in(pixel_in), 
			.h_video_on(h_video_on), 
			.v_video_on(v_video_on), 
			.rgb(rgb)
		);
		always @ (posedge clk)begin		
				if (address < WIDTH*HEIGHT*CHANNEL) begin			
					img[address*8 +: 8]=out;
					address = address + 1;
					enable1=1;
				end
				else if (address < WIDTH*HEIGHT*CHANNEL) begin
					enable2=1;enable1=0;
				end
				if (done)begin
					enable2=0;
				end
		end
endmodule