data/full_repos/permissive/155656868/src/cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/155656868/src/cpu.v:52: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s REPLICATE generates 31 bits.\n                                                                 : ... In instance cpu\n    assign offset = (instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH]) ? {13\'b111_11111_11111, instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH: 0]} : {13\'b000_00000_00000, instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH-1: 0]};\n                                                                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/155656868/src/cpu.v:54: Cannot find file containing module: \'control_unit\'\n    control_unit cu(.opcode(opcode),\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/155656868/src,data/full_repos/permissive/155656868/control_unit\n             data/full_repos/permissive/155656868/src,data/full_repos/permissive/155656868/control_unit.v\n             data/full_repos/permissive/155656868/src,data/full_repos/permissive/155656868/control_unit.sv\n             control_unit\n             control_unit.v\n             control_unit.sv\n             obj_dir/control_unit\n             obj_dir/control_unit.v\n             obj_dir/control_unit.sv\n%Error: data/full_repos/permissive/155656868/src/cpu.v:62: Cannot find file containing module: \'module_alu\'\n    module_alu alu(.a_in(a),\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/155656868/src/cpu.v:69: Cannot find file containing module: \'program_counter\'\n    program_counter pc(.clk(clk),\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/155656868/src/cpu.v:77: Cannot find file containing module: \'instruction_memory\'\n    instruction_memory im(.addr(pc_out),\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/155656868/src/cpu.v:80: Cannot find file containing module: \'register_bank\'\n    register_bank r_b(.ra(ra),\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/155656868/src/cpu.v:88: Cannot find file containing module: \'data_memory\'\n    data_memory dm(.addr({3\'b000, mem_addr}),\n    ^~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module cpu #(parameter WORD_SIZE=32, ADDR_WIDTH=32, OPCODE_WIDTH=3, REG_WIDTH=5)
            (input clk, rst);


    wire ld, st, beq, j, alu_en, zero, rb_wr_en;
    wire [OPCODE_WIDTH-1 : 0] alu_op, opcode;

    wire [WORD_SIZE-1 : 0] instruction, a, b, c, mem_out, alu_out, pc_out, offset;
    wire [WORD_SIZE-1-OPCODE_WIDTH : 0] mem_addr;
    wire [REG_WIDTH-1:0] ra, rb, rc;

    assign opcode = instruction[WORD_SIZE-1 : WORD_SIZE-OPCODE_WIDTH];
    assign c = (ld) ? mem_out : alu_out;
    assign rb_wr_en = ld || alu_en;
    assign mem_addr = 0;
    assign ra = instruction[WORD_SIZE-1-OPCODE_WIDTH: WORD_SIZE-OPCODE_WIDTH-REG_WIDTH];
    assign rb = instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH : WORD_SIZE-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH];
    assign rc = (ld) ? ra : instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH : WORD_SIZE-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH-REG_WIDTH];
    assign offset = (instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH]) ? {13'b111_11111_11111, instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH: 0]} : {13'b000_00000_00000, instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH-1: 0]};

    control_unit cu(.opcode(opcode),
                    .ld(ld),
                    .st(st),
                    .beq(beq),
                    .j(j),
                    .alu_en(alu_en),
                    .alu_op(alu_op));

    module_alu alu(.a_in(a),
                   .b_in(b),
                   .operation(alu_op),
                   .alu_en(alu_en),
                   .out(alu_out),
                   .zero(zero));

    program_counter pc(.clk(clk),
                       .rst(rst),
                       .beq(beq),
                       .zero(zero),
                       .j(j),
                       .offset(offset),
                       .pc_out(pc_out));

    instruction_memory im(.addr(pc_out),
                          .instruction(instruction));

    register_bank r_b(.ra(ra),
                      .rb(rb),
                      .rc(rc),
                      .wr(rb_wr_en),
                      .d_in(c),
                      .da_o(a),
                      .db_o(b));

    data_memory dm(.addr({3'b000, mem_addr}),
                   .d_in(a),
                   .wr(st),
                   .d_out(mem_out));

endmodule
module cpu #(parameter WORD_SIZE=32, ADDR_WIDTH=32, OPCODE_WIDTH=3, REG_WIDTH=5)
            (input clk, rst);



    wire ld, st, beq, j, alu_en, zero, rb_wr_en;
    wire [OPCODE_WIDTH-1 : 0] alu_op, opcode;

    wire [WORD_SIZE-1 : 0] instruction, a, b, c, mem_out, alu_out, pc_out, offset;
    wire [WORD_SIZE-1-OPCODE_WIDTH : 0] mem_addr;
    wire [REG_WIDTH-1:0] ra, rb, rc;

    assign opcode = instruction[WORD_SIZE-1 : WORD_SIZE-OPCODE_WIDTH];
    assign c = (ld) ? mem_out : alu_out;
    assign rb_wr_en = ld || alu_en;
    assign mem_addr = 0;
    assign ra = instruction[WORD_SIZE-1-OPCODE_WIDTH: WORD_SIZE-OPCODE_WIDTH-REG_WIDTH];
    assign rb = instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH : WORD_SIZE-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH];
    assign rc = (ld) ? ra : instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH : WORD_SIZE-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH-REG_WIDTH];
    assign offset = (instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH]) ? {13'b111_11111_11111, instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH: 0]} : {13'b000_00000_00000, instruction[WORD_SIZE-1-OPCODE_WIDTH-REG_WIDTH-REG_WIDTH-1: 0]};

    control_unit cu(.opcode(opcode),
                    .ld(ld),
                    .st(st),
                    .beq(beq),
                    .j(j),
                    .alu_en(alu_en),
                    .alu_op(alu_op));

    module_alu alu(.a_in(a),
                   .b_in(b),
                   .operation(alu_op),
                   .alu_en(alu_en),
                   .out(alu_out),
                   .zero(zero));

    program_counter pc(.clk(clk),
                       .rst(rst),
                       .beq(beq),
                       .zero(zero),
                       .j(j),
                       .offset(offset),
                       .pc_out(pc_out));

    instruction_memory im(.addr(pc_out),
                          .instruction(instruction));

    register_bank r_b(.ra(ra),
                      .rb(rb),
                      .rc(rc),
                      .wr(rb_wr_en),
                      .d_in(c),
                      .da_o(a),
                      .db_o(b));

    data_memory dm(.addr({3'b000, mem_addr}),
                   .d_in(a),
                   .wr(st),
                   .d_out(mem_out));

endmodule