data/full_repos/permissive/164569208/rtl/pulse_merge.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/164569208/rtl/pulse_merge.v:65: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance pulse_merge\n        count_next = count_next + pulse_in[i];\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pulse_merge #
(
    parameter INPUT_WIDTH = 2,
    parameter COUNT_WIDTH = 4
)
(
    input  wire                   clk,
    input  wire                   rst,

    input  wire [INPUT_WIDTH-1:0] pulse_in,
    output wire [COUNT_WIDTH-1:0] count_out,
    output wire                   pulse_out
);

reg [COUNT_WIDTH-1:0] count_reg = {COUNT_WIDTH{1'b0}}, count_next;
reg pulse_reg = 1'b0, pulse_next;

assign count_out = count_reg;
assign pulse_out = pulse_reg;

integer i;

always @* begin
    count_next = count_reg;
    pulse_next = count_reg > 0;

    if (count_reg > 0) begin
        count_next = count_reg - 1;
    end

    for (i = 0; i < INPUT_WIDTH; i = i + 1) begin
        count_next = count_next + pulse_in[i];
    end
end

always @(posedge clk) begin
    if (rst) begin
        count_reg <= {COUNT_WIDTH{1'b0}};
        pulse_reg <= 1'b0;
    end else begin
        count_reg <= count_next;
        pulse_reg <= pulse_next;
    end
end

endmodule
module pulse_merge #
(
    parameter INPUT_WIDTH = 2,
    parameter COUNT_WIDTH = 4
)
(
    input  wire                   clk,
    input  wire                   rst,

    input  wire [INPUT_WIDTH-1:0] pulse_in,
    output wire [COUNT_WIDTH-1:0] count_out,
    output wire                   pulse_out
);


reg [COUNT_WIDTH-1:0] count_reg = {COUNT_WIDTH{1'b0}}, count_next;
reg pulse_reg = 1'b0, pulse_next;

assign count_out = count_reg;
assign pulse_out = pulse_reg;

integer i;

always @* begin
    count_next = count_reg;
    pulse_next = count_reg > 0;

    if (count_reg > 0) begin
        count_next = count_reg - 1;
    end

    for (i = 0; i < INPUT_WIDTH; i = i + 1) begin
        count_next = count_next + pulse_in[i];
    end
end

always @(posedge clk) begin
    if (rst) begin
        count_reg <= {COUNT_WIDTH{1'b0}};
        pulse_reg <= 1'b0;
    end else begin
        count_reg <= count_next;
        pulse_reg <= pulse_next;
    end
end

endmodule