data/full_repos/permissive/195227969/work/cold_store/abandoned_m_inputmux.v
 line:501: before: "="
1: b"%Error: data/full_repos/permissive/195227969/work/cold_store/abandoned_m_inputmux.v:501: syntax error, unexpected '=', expecting ',' or ';'\n               genvar k = 0;\n                        ^\n%Error: Exiting due to 1 error(s)\n"
module m_inputmux_highlevel
  # ( parameter MULDIV = 1, 
      DAT_I_ZERO_WHEN_INACTIVE = 0, 
      IWIDTH = 8,  
      SRAMADRWIDTH = 0, 
      MTIMETAP = 0, 
      MTIMETAP_LOWLIM = 32 
      )
   (
    input              clk,
    input [31:0]       DAT_O, 
    input [IWIDTH-1:0] DAT_I, 
    input [31:0]       Dsram, 
    input [31:0]       ADR_O, 
    input              sra_msb, 
    input              sa00, 
    input              STB_O, 
    input              sram_ack, 
    input              mie, 
    input              mpie, 
    input              meie, 
    input              mrinstretie, 
    input              msie, 
    input              mtie, 
    input              mtimeincie, 
    input              mrinstretip, 
    input              msip, 
    input              mtip,
    input              mtimeincip, 
    input              meip, 
    input              qACK, 
    input              corerunning, 

    input [31:0]       MULDIVREG, 
    input              clrM,
    input              ceM,

    
    output             sysregack, 
    output [31:0]      Di, 
    output [31:0]      rDee, 
    output [31:0]      theio
    );
   wire [31:0]         shADR_O = {sra_msb,ADR_O[31:1]};
   
   generate
      



      reg              sa00mod;
      always @(posedge clk)
        sa00mod <=  ~(qACK | sram_ack | sa00 | ~corerunning);
      assign Di = sa00mod ? DAT_O : (DAT_O & rDee | ~DAT_O & shADR_O);
      
      wire [32:0]      zeros = 33'h0;
      



      if ( MTIMETAP < MTIMETAP_LOWLIM ) begin         

         if ( IWIDTH == 32 )
           assign theio = DAT_I[IWIDTH-1:0];
         else
           assign theio = {zeros[31:IWIDTH],DAT_I};
         assign sysregack = 1'b0;

      end else begin         

         wire [32:0] extDAT_I = {zeros[32:IWIDTH],DAT_I};

         wire [31:0] MIP     = {14'h0,mrinstretip,mtimeincip,4'b0000,meip,3'h0,mtip,3'h0,msip,3'h0};
         wire [31:0] MIE     = {14'h0,mrinstretie,mtimeincie,4'b0000,meie,3'h0,mtie,3'h0,msie,3'h0};
         wire [31:0] MSTATUS = {14'h0,1'b0,       1'b0,      4'b0001,1'b1,3'h0,mpie,3'h0,mie, 3'h0};

         reg         aaa;

         reg [31:0]  defeatlattice_theio;
         
         always @(ADR_O or MIE or MIP or MSTATUS or extDAT_I) 
           case ( ADR_O[29:27] )
             3'b000 : { aaa, defeatlattice_theio} = {1'b0, extDAT_I[31:0]};
             3'b001 : { aaa, defeatlattice_theio} = {1'b0, extDAT_I[31:0]};
             3'b010 : { aaa, defeatlattice_theio} = {1'b0, extDAT_I[31:0]};
             3'b011 : { aaa, defeatlattice_theio} = {1'b0, extDAT_I[31:0]};
             3'b100 : { aaa, defeatlattice_theio} = {1'b0, extDAT_I[31:0]};
             3'b101 : { aaa, defeatlattice_theio} = {1'b1, MIP};
             3'b110 : { aaa, defeatlattice_theio} = {1'b1, MIE};
             3'b111 : { aaa, defeatlattice_theio} = {1'b1, MSTATUS};
           endcase
         assign theio = defeatlattice_theio;
         assign sysregack = aaa & STB_O;         
      end




      if ( SRAMADRWIDTH == 0 ) begin

         reg [IWIDTH-1:0] r;
         wire [31:0]      eio;
         if ( IWIDTH == 32 )
           assign eio = theio[31:0];
         else
           assign eio = {zeros[31:IWIDTH],theio[IWIDTH-1:0]};
         
         always @(posedge clk)
           if ( corerunning )
             r <= STB_O ? eio : MULDIVREG;
         assign rDee = r;
         
      end else begin

         reg [31:0] r;
         wire [31:0] cmb;

         if ( MULDIV == 0 ) begin
            assign cmb = STB_O ? theio : Dsram;
         end else begin
            wire ReadM = clrM & ceM; 
            wire STB_O_or_ReadM;
            wire [31:0] theio_or_M;
            assign STB_O_or_ReadM = STB_O | ReadM;

            if ( DAT_I_ZERO_WHEN_INACTIVE ) begin
               assign theio_or_M = theio | MULDIVREG;
            end else begin
               assign theio_or_M = ReadM ? MULDIVREG : theio;
            end
            assign cmb = STB_O_or_ReadM ? theio_or_M : Dsram;

         end
         always @(posedge clk)
           if ( corerunning )
             r <= cmb;
         assign rDee = r;
      end
   endgenerate








endmodule
module m_inputmux_highlevel
  # ( parameter MULDIV = 1, 
      DAT_I_ZERO_WHEN_INACTIVE = 0, 
      IWIDTH = 8,  
      SRAMADRWIDTH = 0, 
      MTIMETAP = 0, 
      MTIMETAP_LOWLIM = 32 
      )
   (
    input              clk,
    input [31:0]       DAT_O, 
    input [IWIDTH-1:0] DAT_I, 
    input [31:0]       Dsram, 
    input [31:0]       ADR_O, 
    input              sra_msb, 
    input              sa00, 
    input              STB_O, 
    input              sram_ack, 
    input              mie, 
    input              mpie, 
    input              meie, 
    input              mrinstretie, 
    input              msie, 
    input              mtie, 
    input              mtimeincie, 
    input              mrinstretip, 
    input              msip, 
    input              mtip,
    input              mtimeincip, 
    input              meip, 
    input              qACK, 
    input              corerunning, 

    input [31:0]       MULDIVREG, 
    input              clrM,
    input              ceM,

    
    output             sysregack, 
    output [31:0]      Di, 
    output [31:0]      rDee, 
    output [31:0]      theio
    );

   wire [31:0]         shADR_O = {sra_msb,ADR_O[31:1]};
   
   generate
      



      reg              sa00mod;
      always @(posedge clk)
        sa00mod <=  ~(qACK | sram_ack | sa00 | ~corerunning);
      assign Di = sa00mod ? DAT_O : (DAT_O & rDee | ~DAT_O & shADR_O);
      
      wire [32:0]      zeros = 33'h0;
      



      if ( MTIMETAP < MTIMETAP_LOWLIM ) begin         

         if ( IWIDTH == 32 )
           assign theio = DAT_I[IWIDTH-1:0];
         else
           assign theio = {zeros[31:IWIDTH],DAT_I};
         assign sysregack = 1'b0;

      end else begin         

         wire [32:0] extDAT_I = {zeros[32:IWIDTH],DAT_I};

         wire [31:0] MIP     = {14'h0,mrinstretip,mtimeincip,4'b0000,meip,3'h0,mtip,3'h0,msip,3'h0};
         wire [31:0] MIE     = {14'h0,mrinstretie,mtimeincie,4'b0000,meie,3'h0,mtie,3'h0,msie,3'h0};
         wire [31:0] MSTATUS = {14'h0,1'b0,       1'b0,      4'b0001,1'b1,3'h0,mpie,3'h0,mie, 3'h0};

         reg         aaa;

         reg [31:0]  defeatlattice_theio;
         
         always @(ADR_O or MIE or MIP or MSTATUS or extDAT_I) 
           case ( ADR_O[29:27] )
             3'b000 : { aaa, defeatlattice_theio} = {1'b0, extDAT_I[31:0]};
             3'b001 : { aaa, defeatlattice_theio} = {1'b0, extDAT_I[31:0]};
             3'b010 : { aaa, defeatlattice_theio} = {1'b0, extDAT_I[31:0]};
             3'b011 : { aaa, defeatlattice_theio} = {1'b0, extDAT_I[31:0]};
             3'b100 : { aaa, defeatlattice_theio} = {1'b0, extDAT_I[31:0]};
             3'b101 : { aaa, defeatlattice_theio} = {1'b1, MIP};
             3'b110 : { aaa, defeatlattice_theio} = {1'b1, MIE};
             3'b111 : { aaa, defeatlattice_theio} = {1'b1, MSTATUS};
           endcase
         assign theio = defeatlattice_theio;
         assign sysregack = aaa & STB_O;         
      end




      if ( SRAMADRWIDTH == 0 ) begin

         reg [IWIDTH-1:0] r;
         wire [31:0]      eio;
         if ( IWIDTH == 32 )
           assign eio = theio[31:0];
         else
           assign eio = {zeros[31:IWIDTH],theio[IWIDTH-1:0]};
         
         always @(posedge clk)
           if ( corerunning )
             r <= STB_O ? eio : MULDIVREG;
         assign rDee = r;
         
      end else begin

         reg [31:0] r;
         wire [31:0] cmb;

         if ( MULDIV == 0 ) begin
            assign cmb = STB_O ? theio : Dsram;
         end else begin
            wire ReadM = clrM & ceM; 
            wire STB_O_or_ReadM;
            wire [31:0] theio_or_M;
            assign STB_O_or_ReadM = STB_O | ReadM;

            if ( DAT_I_ZERO_WHEN_INACTIVE ) begin
               assign theio_or_M = theio | MULDIVREG;
            end else begin
               assign theio_or_M = ReadM ? MULDIVREG : theio;
            end
            assign cmb = STB_O_or_ReadM ? theio_or_M : Dsram;

         end
         always @(posedge clk)
           if ( corerunning )
             r <= cmb;
         assign rDee = r;
      end
   endgenerate








endmodule