data/full_repos/permissive/117439233/hdl/src/FA.v
data/verilator_xmls/899a09a2-1d83-426b-8fc5-7b19e57afc97.xml
module FA(
    input A,
    input B,
    input Cin,
    output S,
    output Cout
);
assign S = A ^ B ^ Cin;
assign Cout = A&Cin | B&Cin | A&B; 

endmodule
module FA(
    input A,
    input B,
    input Cin,
    output S,
    output Cout
);

assign S = A ^ B ^ Cin;
assign Cout = A&Cin | B&Cin | A&B; 

endmodule