data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:31: Cannot find include file: spio_hss_multiplexer_common.h\n`include "spio_hss_multiplexer_common.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h.v\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h.sv\n             spio_hss_multiplexer_common.h\n             spio_hss_multiplexer_common.h.v\n             spio_hss_multiplexer_common.h.sv\n             obj_dir/spio_hss_multiplexer_common.h\n             obj_dir/spio_hss_multiplexer_common.h.v\n             obj_dir/spio_hss_multiplexer_common.h.sv\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:32: Cannot find include file: spio_hss_multiplexer_reg_bank.h\n`include "spio_hss_multiplexer_reg_bank.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:44: Define or directive not defined: \'`CRDT_BITS\'\n  input  wire [`CRDT_BITS - 1:0] reg_crdt,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:45: Define or directive not defined: \'`NUM_CHANS\'\n  input  wire [`NUM_CHANS - 1:0] reg_empt,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:46: Define or directive not defined: \'`NUM_CHANS\'\n  input  wire [`NUM_CHANS - 1:0] reg_full,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:50: Define or directive not defined: \'`IDLE_BITS\'\n  output reg  [`IDLE_BITS - 1:0] reg_idso,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:60: Define or directive not defined: \'`NUM_CHANS\'\n  input  wire [`NUM_CHANS - 1:0] reg_cfcr,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:61: Define or directive not defined: \'`IDLE_BITS\'\n  input  wire [`IDLE_BITS - 1:0] reg_idsi,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:68: Define or directive not defined: \'`NUM_CHANS\'\n  input  wire [`NUM_CHANS - 1:0] reg_cfcl,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:75: Define or directive not defined: \'`REGA_BITS\'\n  input  wire [`REGA_BITS - 1:0] reg_addr,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:76: Define or directive not defined: \'`REGD_BITS\'\n  output reg  [`REGD_BITS - 1:0] reg_read_data,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:77: Define or directive not defined: \'`REGD_BITS\'\n  input  wire [`REGD_BITS - 1:0] reg_write_data\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:88: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] looc_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:89: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] crce_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:90: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] frme_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:91: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] rfrm_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:92: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] dfrm_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:93: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] tfrm_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:94: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] sfrm_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:95: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] busy_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:96: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] lnak_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:97: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] rnak_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:98: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] lack_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:99: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] rack_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:100: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] rooc_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:101: Define or directive not defined: \'`REGD_BITS\'\n  reg  [`REGD_BITS - 1:0] reco_ctr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:246: Define or directive not defined: \'`IDLE_BITS\'\n        reg_idso <= {`IDLE_BITS{1\'b0}};\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:252: Define or directive not defined: \'`IDSO_REG\'\n          `IDSO_REG: reg_idso <= reg_write_data[`IDLE_BITS-1:0];\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:252: syntax error, unexpected \':\', expecting endcase\n          `IDSO_REG: reg_idso <= reg_write_data[`IDLE_BITS-1:0];\n                   ^\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:252: Define or directive not defined: \'`IDLE_BITS\'\n          `IDSO_REG: reg_idso <= reg_write_data[`IDLE_BITS-1:0];\n                                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:253: Define or directive not defined: \'`STOP_REG\'\n          `STOP_REG: reg_stop <= reg_write_data[0];\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:263: Define or directive not defined: \'`VERS_REG\'\n      `VERS_REG: reg_read_data = {`HSS_MULTIPLEXER_VERSION,`PROTOCOL_VERSION};\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:263: Define or directive not defined: \'`HSS_MULTIPLEXER_VERSION\'\n      `VERS_REG: reg_read_data = {`HSS_MULTIPLEXER_VERSION,`PROTOCOL_VERSION};\n                                  ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:263: Define or directive not defined: \'`PROTOCOL_VERSION\'\n      `VERS_REG: reg_read_data = {`HSS_MULTIPLEXER_VERSION,`PROTOCOL_VERSION};\n                                                           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:264: Define or directive not defined: \'`CRCE_REG\'\n      `CRCE_REG: reg_read_data = crce_ctr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:265: Define or directive not defined: \'`FRME_REG\'\n      `FRME_REG: reg_read_data = frme_ctr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:266: Define or directive not defined: \'`BUSY_REG\'\n      `BUSY_REG: reg_read_data = busy_ctr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:267: Define or directive not defined: \'`LNAK_REG\'\n      `LNAK_REG: reg_read_data = lnak_ctr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:268: Define or directive not defined: \'`RNAK_REG\'\n      `RNAK_REG: reg_read_data = rnak_ctr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:269: Define or directive not defined: \'`LACK_REG\'\n      `LACK_REG: reg_read_data = lack_ctr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:270: Define or directive not defined: \'`RACK_REG\'\n      `RACK_REG: reg_read_data = rack_ctr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:271: Define or directive not defined: \'`LOOC_REG\'\n      `LOOC_REG: reg_read_data = looc_ctr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:272: Define or directive not defined: \'`ROOC_REG\'\n      `ROOC_REG: reg_read_data = rooc_ctr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:273: Define or directive not defined: \'`CRDT_REG\'\n      `CRDT_REG: reg_read_data = {{(`REGD_BITS - `CRDT_BITS) {1\'b0}},\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:273: Define or directive not defined: \'`REGD_BITS\'\n      `CRDT_REG: reg_read_data = {{(`REGD_BITS - `CRDT_BITS) {1\'b0}},\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:273: Define or directive not defined: \'`CRDT_BITS\'\n      `CRDT_REG: reg_read_data = {{(`REGD_BITS - `CRDT_BITS) {1\'b0}},\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:276: Define or directive not defined: \'`SFRM_REG\'\n      `SFRM_REG: reg_read_data = sfrm_ctr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:277: Define or directive not defined: \'`TFRM_REG\'\n      `TFRM_REG: reg_read_data = tfrm_ctr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:278: Define or directive not defined: \'`DFRM_REG\'\n      `DFRM_REG: reg_read_data = dfrm_ctr;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_reg_bank.v:279: Define or directive not defined: \'`RFRM_REG\'\n      `RFRM_REG: reg_read_data = rfrm_ctr;\n      ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module spio_hss_multiplexer_reg_bank
(
  input  wire 			 clk,
  input  wire 			 rst,


  input  wire                    reg_sfrm,
  input  wire                    reg_looc,
  input  wire [`CRDT_BITS - 1:0] reg_crdt,
  input  wire [`NUM_CHANS - 1:0] reg_empt,
  input  wire [`NUM_CHANS - 1:0] reg_full,


  input  wire                    reg_tfrm,
  output reg  [`IDLE_BITS - 1:0] reg_idso,
  output reg                     reg_stop,


  input  wire                    reg_dfrm,
  input  wire                    reg_crce,
  input  wire                    reg_frme,
  input  wire                    reg_rnak,
  input  wire                    reg_rack,
  input  wire                    reg_rooc,
  input  wire [`NUM_CHANS - 1:0] reg_cfcr,
  input  wire [`IDLE_BITS - 1:0] reg_idsi,


  input  wire                    reg_rfrm,
  input  wire                    reg_busy,
  input  wire                    reg_lnak,
  input  wire                    reg_lack,
  input  wire [`NUM_CHANS - 1:0] reg_cfcl,
  

  input  wire [1:0]              reg_hand,


  input  wire                    reg_write,
  input  wire [`REGA_BITS - 1:0] reg_addr,
  output reg  [`REGD_BITS - 1:0] reg_read_data,
  input  wire [`REGD_BITS - 1:0] reg_write_data
);




   




  reg  [`REGD_BITS - 1:0] looc_ctr;
  reg  [`REGD_BITS - 1:0] crce_ctr;
  reg  [`REGD_BITS - 1:0] frme_ctr;
  reg  [`REGD_BITS - 1:0] rfrm_ctr;
  reg  [`REGD_BITS - 1:0] dfrm_ctr;
  reg  [`REGD_BITS - 1:0] tfrm_ctr;
  reg  [`REGD_BITS - 1:0] sfrm_ctr;
  reg  [`REGD_BITS - 1:0] busy_ctr;
  reg  [`REGD_BITS - 1:0] lnak_ctr;
  reg  [`REGD_BITS - 1:0] rnak_ctr;
  reg  [`REGD_BITS - 1:0] lack_ctr;
  reg  [`REGD_BITS - 1:0] rack_ctr;
  reg  [`REGD_BITS - 1:0] rooc_ctr;
  reg  [`REGD_BITS - 1:0] reco_ctr;

  reg  [1:0] last_reg_hand;
  reg        reg_reco;









  always @(posedge clk or posedge rst)
    if (rst)
      last_reg_hand <= 2'b00;
    else
      last_reg_hand <= reg_hand;

  always @ (*)
    reg_reco = last_reg_hand[0] == 1'b0 && reg_hand[0] == 1'b1;





  always @ (posedge clk or posedge rst)
    if (rst)
      crce_ctr <= 1'b0;
    else
      if (reg_crce)
        crce_ctr <= crce_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      frme_ctr <= 1'b0;
    else
      if (reg_frme)
        frme_ctr <= frme_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      busy_ctr <= 1'b0;
    else
      if (reg_busy)
        busy_ctr <= busy_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      rfrm_ctr <= 1'b0;
    else
      if (reg_rfrm)
        rfrm_ctr <= rfrm_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      dfrm_ctr <= 1'b0;
    else
      if (reg_dfrm)
        dfrm_ctr <= dfrm_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      tfrm_ctr <= 1'b0;
    else
      if (reg_tfrm)
        tfrm_ctr <= tfrm_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      sfrm_ctr <= 1'b0;
    else
      if (reg_sfrm)
        sfrm_ctr <= sfrm_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      lnak_ctr <= 1'b0;
    else
      if (reg_lnak)
        lnak_ctr <= lnak_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      rnak_ctr <= 1'b0;
    else
      if (reg_rnak)
        rnak_ctr <= rnak_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      lack_ctr <= 1'b0;
    else
      if (reg_lack)
        lack_ctr <= lack_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      rack_ctr <= 1'b0;
    else
      if (reg_rack)
        rack_ctr <= rack_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      looc_ctr <= 1'b0;
    else
      if (reg_looc)
        looc_ctr <= looc_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      rooc_ctr <= 1'b0;
    else
      if (reg_rooc)
        rooc_ctr <= rooc_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      reco_ctr <= 1'b0;
    else
      if (reg_reco)
        reco_ctr <= reco_ctr + 1;






  always @(posedge clk or posedge rst)
    if (rst)
      begin
        reg_idso <= {`IDLE_BITS{1'b0}};
        reg_stop <= 1'b0;
      end
    else
      if (reg_write)
        case (reg_addr)
          `IDSO_REG: reg_idso <= reg_write_data[`IDLE_BITS-1:0];
          `STOP_REG: reg_stop <= reg_write_data[0];
        endcase






  always @ (*)
    case (reg_addr)
      `VERS_REG: reg_read_data = {`HSS_MULTIPLEXER_VERSION,`PROTOCOL_VERSION};
      `CRCE_REG: reg_read_data = crce_ctr;
      `FRME_REG: reg_read_data = frme_ctr;
      `BUSY_REG: reg_read_data = busy_ctr;
      `LNAK_REG: reg_read_data = lnak_ctr;
      `RNAK_REG: reg_read_data = rnak_ctr;
      `LACK_REG: reg_read_data = lack_ctr;
      `RACK_REG: reg_read_data = rack_ctr;
      `LOOC_REG: reg_read_data = looc_ctr;
      `ROOC_REG: reg_read_data = rooc_ctr;
      `CRDT_REG: reg_read_data = {{(`REGD_BITS - `CRDT_BITS) {1'b0}},
                                    reg_crdt
                                  };
      `SFRM_REG: reg_read_data = sfrm_ctr;
      `TFRM_REG: reg_read_data = tfrm_ctr;
      `DFRM_REG: reg_read_data = dfrm_ctr;
      `RFRM_REG: reg_read_data = rfrm_ctr;
      `EMPT_REG: reg_read_data = {{(`REGD_BITS - `NUM_CHANS) {1'b0}},
                                    reg_empt
                                  };
      `FULL_REG: reg_read_data = {{(`REGD_BITS - `NUM_CHANS) {1'b0}},
                                    reg_full
                                  };
      `CFCL_REG: reg_read_data = {{(`REGD_BITS - `NUM_CHANS) {1'b0}},
                                    reg_cfcl
                                  };
      `CFCR_REG: reg_read_data = {{(`REGD_BITS - `NUM_CHANS) {1'b0}},
                               reg_cfcr
                             };
      `IDSO_REG: reg_read_data = {{(`REGD_BITS-`IDLE_BITS){1'b0}}, reg_idso};
      `IDSI_REG: reg_read_data = {{(`REGD_BITS-`IDLE_BITS){1'b0}}, reg_idsi};
      `HAND_REG: reg_read_data = {{(`REGD_BITS-2){1'b0}}, reg_hand};
      `RECO_REG: reg_read_data = reco_ctr;
      `STOP_REG: reg_read_data = {{(`REGD_BITS-1){1'b0}}, reg_stop};
      default:   reg_read_data = {`REGD_BITS {1'b1}};
    endcase



endmodule
module spio_hss_multiplexer_reg_bank
(
  input  wire 			 clk,
  input  wire 			 rst,


  input  wire                    reg_sfrm,
  input  wire                    reg_looc,
  input  wire [`CRDT_BITS - 1:0] reg_crdt,
  input  wire [`NUM_CHANS - 1:0] reg_empt,
  input  wire [`NUM_CHANS - 1:0] reg_full,


  input  wire                    reg_tfrm,
  output reg  [`IDLE_BITS - 1:0] reg_idso,
  output reg                     reg_stop,


  input  wire                    reg_dfrm,
  input  wire                    reg_crce,
  input  wire                    reg_frme,
  input  wire                    reg_rnak,
  input  wire                    reg_rack,
  input  wire                    reg_rooc,
  input  wire [`NUM_CHANS - 1:0] reg_cfcr,
  input  wire [`IDLE_BITS - 1:0] reg_idsi,


  input  wire                    reg_rfrm,
  input  wire                    reg_busy,
  input  wire                    reg_lnak,
  input  wire                    reg_lack,
  input  wire [`NUM_CHANS - 1:0] reg_cfcl,
  

  input  wire [1:0]              reg_hand,


  input  wire                    reg_write,
  input  wire [`REGA_BITS - 1:0] reg_addr,
  output reg  [`REGD_BITS - 1:0] reg_read_data,
  input  wire [`REGD_BITS - 1:0] reg_write_data
);





   




  reg  [`REGD_BITS - 1:0] looc_ctr;
  reg  [`REGD_BITS - 1:0] crce_ctr;
  reg  [`REGD_BITS - 1:0] frme_ctr;
  reg  [`REGD_BITS - 1:0] rfrm_ctr;
  reg  [`REGD_BITS - 1:0] dfrm_ctr;
  reg  [`REGD_BITS - 1:0] tfrm_ctr;
  reg  [`REGD_BITS - 1:0] sfrm_ctr;
  reg  [`REGD_BITS - 1:0] busy_ctr;
  reg  [`REGD_BITS - 1:0] lnak_ctr;
  reg  [`REGD_BITS - 1:0] rnak_ctr;
  reg  [`REGD_BITS - 1:0] lack_ctr;
  reg  [`REGD_BITS - 1:0] rack_ctr;
  reg  [`REGD_BITS - 1:0] rooc_ctr;
  reg  [`REGD_BITS - 1:0] reco_ctr;

  reg  [1:0] last_reg_hand;
  reg        reg_reco;









  always @(posedge clk or posedge rst)
    if (rst)
      last_reg_hand <= 2'b00;
    else
      last_reg_hand <= reg_hand;

  always @ (*)
    reg_reco = last_reg_hand[0] == 1'b0 && reg_hand[0] == 1'b1;





  always @ (posedge clk or posedge rst)
    if (rst)
      crce_ctr <= 1'b0;
    else
      if (reg_crce)
        crce_ctr <= crce_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      frme_ctr <= 1'b0;
    else
      if (reg_frme)
        frme_ctr <= frme_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      busy_ctr <= 1'b0;
    else
      if (reg_busy)
        busy_ctr <= busy_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      rfrm_ctr <= 1'b0;
    else
      if (reg_rfrm)
        rfrm_ctr <= rfrm_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      dfrm_ctr <= 1'b0;
    else
      if (reg_dfrm)
        dfrm_ctr <= dfrm_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      tfrm_ctr <= 1'b0;
    else
      if (reg_tfrm)
        tfrm_ctr <= tfrm_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      sfrm_ctr <= 1'b0;
    else
      if (reg_sfrm)
        sfrm_ctr <= sfrm_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      lnak_ctr <= 1'b0;
    else
      if (reg_lnak)
        lnak_ctr <= lnak_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      rnak_ctr <= 1'b0;
    else
      if (reg_rnak)
        rnak_ctr <= rnak_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      lack_ctr <= 1'b0;
    else
      if (reg_lack)
        lack_ctr <= lack_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      rack_ctr <= 1'b0;
    else
      if (reg_rack)
        rack_ctr <= rack_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      looc_ctr <= 1'b0;
    else
      if (reg_looc)
        looc_ctr <= looc_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      rooc_ctr <= 1'b0;
    else
      if (reg_rooc)
        rooc_ctr <= rooc_ctr + 1;


  always @ (posedge clk or posedge rst)
    if (rst)
      reco_ctr <= 1'b0;
    else
      if (reg_reco)
        reco_ctr <= reco_ctr + 1;






  always @(posedge clk or posedge rst)
    if (rst)
      begin
        reg_idso <= {`IDLE_BITS{1'b0}};
        reg_stop <= 1'b0;
      end
    else
      if (reg_write)
        case (reg_addr)
          `IDSO_REG: reg_idso <= reg_write_data[`IDLE_BITS-1:0];
          `STOP_REG: reg_stop <= reg_write_data[0];
        endcase






  always @ (*)
    case (reg_addr)
      `VERS_REG: reg_read_data = {`HSS_MULTIPLEXER_VERSION,`PROTOCOL_VERSION};
      `CRCE_REG: reg_read_data = crce_ctr;
      `FRME_REG: reg_read_data = frme_ctr;
      `BUSY_REG: reg_read_data = busy_ctr;
      `LNAK_REG: reg_read_data = lnak_ctr;
      `RNAK_REG: reg_read_data = rnak_ctr;
      `LACK_REG: reg_read_data = lack_ctr;
      `RACK_REG: reg_read_data = rack_ctr;
      `LOOC_REG: reg_read_data = looc_ctr;
      `ROOC_REG: reg_read_data = rooc_ctr;
      `CRDT_REG: reg_read_data = {{(`REGD_BITS - `CRDT_BITS) {1'b0}},
                                    reg_crdt
                                  };
      `SFRM_REG: reg_read_data = sfrm_ctr;
      `TFRM_REG: reg_read_data = tfrm_ctr;
      `DFRM_REG: reg_read_data = dfrm_ctr;
      `RFRM_REG: reg_read_data = rfrm_ctr;
      `EMPT_REG: reg_read_data = {{(`REGD_BITS - `NUM_CHANS) {1'b0}},
                                    reg_empt
                                  };
      `FULL_REG: reg_read_data = {{(`REGD_BITS - `NUM_CHANS) {1'b0}},
                                    reg_full
                                  };
      `CFCL_REG: reg_read_data = {{(`REGD_BITS - `NUM_CHANS) {1'b0}},
                                    reg_cfcl
                                  };
      `CFCR_REG: reg_read_data = {{(`REGD_BITS - `NUM_CHANS) {1'b0}},
                               reg_cfcr
                             };
      `IDSO_REG: reg_read_data = {{(`REGD_BITS-`IDLE_BITS){1'b0}}, reg_idso};
      `IDSI_REG: reg_read_data = {{(`REGD_BITS-`IDLE_BITS){1'b0}}, reg_idsi};
      `HAND_REG: reg_read_data = {{(`REGD_BITS-2){1'b0}}, reg_hand};
      `RECO_REG: reg_read_data = reco_ctr;
      `STOP_REG: reg_read_data = {{(`REGD_BITS-1){1'b0}}, reg_stop};
      default:   reg_read_data = {`REGD_BITS {1'b1}};
    endcase



endmodule