data/full_repos/permissive/214823094/lab_6/project_2/project_2.srcs/sources_1/new/traffic_lights_2.v
data/verilator_xmls/4e60f4d5-05cb-41f5-84ae-4a8cd8665f26.xml
module clkdiv(
    input inclk,
    output outclk
    );
    reg [35:0]q;
    always@(posedge inclk)
         q<=q+1;
    assign outclk=q[27];
endmodule
module clkdiv(
    input inclk,
    output outclk
    );

    reg [35:0]q;
    always@(posedge inclk)
         q<=q+1;
    assign outclk=q[27];
endmodule