data/full_repos/permissive/117436613/testbench/boot_test.sv
 line:4: before: ""DPI-C""
1: b'%Error: data/full_repos/permissive/117436613/testbench/boot_test.sv:4: syntax error, unexpected \')\', expecting IDENTIFIER\n import "DPI-C" function void mem_init(string);\n                                             ^\n%Error: data/full_repos/permissive/117436613/testbench/boot_test.sv:5: syntax error, unexpected \',\', expecting IDENTIFIER\n import "DPI-C" function longint mem_read(int, longint);\n                                             ^\n%Error: data/full_repos/permissive/117436613/testbench/boot_test.sv:6: syntax error, unexpected \',\', expecting IDENTIFIER\n import "DPI-C" function void mem_write(int, longint, longint);\n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/boot_test.sv:42: Unsupported: Ignoring delay on this delayed statement.\n always #20\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/117436613/testbench/boot_test.sv:47: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/117436613/testbench/boot_test.sv:66: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/boot_test.sv:74: Unsupported: Ignoring delay on this delayed statement.\n  #80 reset_n <= 1;\n  ^\n%Error: Internal Error: data/full_repos/permissive/117436613/testbench/boot_test.sv:1: ../V3ParseSym.h:114: Symbols suggest ending TASK \'mem_write\' but parser thinks ending MODULE \'boot_test\'\nmodule boot_test(\n       ^~~~~~~~~\n'
module boot_test(
	);
	
	import "DPI-C" function void mem_init(string);
	import "DPI-C" function longint mem_read(int, longint);
	import "DPI-C" function void mem_write(int, longint, longint);

	logic	[31:0] dbg_led;
	logic	[2:0]	 dbg_btn;
	logic [9:0]  dbg_ledg;
	logic [9:0]  dbg_sw;

	logic			clk;
	logic			reset_n;

	logic [63:0] mmix_address;
	logic [1:0]  mmix_datasize;
	logic			 mmix_read;
	logic [63:0] mmix_readdata;
	logic			 mmix_write;
	logic [63:0] mmix_writedata;
	logic			 mmix_done;
	
	cpu xxx(
		dbg_led,
		dbg_btn,
		dbg_ledg,
		dbg_sw,

		clk,
		reset_n,
	
		mmix_address,
		mmix_datasize,
		mmix_read,
		mmix_readdata,
		mmix_write,
		mmix_writedata,
		mmix_done
		);
		
	always #20
		clk <= ~clk;
	
	task wait_mem_access();
		while (1) begin
			@(posedge clk);
			if (mmix_read == 1) begin
				if (mmix_address == 'h58)
					$stop;
				mmix_readdata = mem_read(mmix_datasize, mmix_address);
				break;
			end else if (mmix_write == 1) begin
				mem_write(mmix_datasize, mmix_address, mmix_writedata);
				break;
			end
			



			
		end

		mmix_done <= 1;

		@(posedge clk);
		mmix_done <= 0;
	endtask

	initial begin
		clk <= 0;
		reset_n <= 0;
		mmix_done <= 0;
		#80 reset_n <= 1;

		mem_init("vmlinux.bin");

		while (1)
			wait_mem_access();
			


	end
	
endmodule
module boot_test(
	);

	
	import "DPI-C" function void mem_init(string);
	import "DPI-C" function longint mem_read(int, longint);
	import "DPI-C" function void mem_write(int, longint, longint);

	logic	[31:0] dbg_led;
	logic	[2:0]	 dbg_btn;
	logic [9:0]  dbg_ledg;
	logic [9:0]  dbg_sw;

	logic			clk;
	logic			reset_n;

	logic [63:0] mmix_address;
	logic [1:0]  mmix_datasize;
	logic			 mmix_read;
	logic [63:0] mmix_readdata;
	logic			 mmix_write;
	logic [63:0] mmix_writedata;
	logic			 mmix_done;
	
	cpu xxx(
		dbg_led,
		dbg_btn,
		dbg_ledg,
		dbg_sw,

		clk,
		reset_n,
	
		mmix_address,
		mmix_datasize,
		mmix_read,
		mmix_readdata,
		mmix_write,
		mmix_writedata,
		mmix_done
		);
		
	always #20
		clk <= ~clk;
	
	task wait_mem_access();
		while (1) begin
			@(posedge clk);
			if (mmix_read == 1) begin
				if (mmix_address == 'h58)
					$stop;
				mmix_readdata = mem_read(mmix_datasize, mmix_address);
				break;
			end else if (mmix_write == 1) begin
				mem_write(mmix_datasize, mmix_address, mmix_writedata);
				break;
			end
			



			
		end

		mmix_done <= 1;

		@(posedge clk);
		mmix_done <= 0;
	endtask

	initial begin
		clk <= 0;
		reset_n <= 0;
		mmix_done <= 0;
		#80 reset_n <= 1;

		mem_init("vmlinux.bin");

		while (1)
			wait_mem_access();
			


	end
	
endmodule