data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v
1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:10: Cannot find include file: ahb_lite.vh\n`include "ahb_lite.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.v\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.sv\n             ahb_lite.vh\n             ahb_lite.vh.v\n             ahb_lite.vh.sv\n             obj_dir/ahb_lite.vh\n             obj_dir/ahb_lite.vh.v\n             obj_dir/ahb_lite.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:11: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:32: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    input  [`SM_GPIO_WIDTH - 1:0] port_gpioIn,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:33: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    output [`SM_GPIO_WIDTH - 1:0] port_gpioOut\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:36: Define or directive not defined: \'`HTRANS_IDLE\'\n    wire request   = HREADY & HSEL & HTRANS != `HTRANS_IDLE;\n                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    wire request   = HREADY & HSEL & HTRANS != `HTRANS_IDLE;\n                                                           ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:92: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    input  [`SM_GPIO_WIDTH - 1:0] gpioInput,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:93: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    output [`SM_GPIO_WIDTH - 1:0] gpioOutput\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:95: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    wire   [`SM_GPIO_WIDTH - 1:0] gpioIn;     \n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:97: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    wire   [`SM_GPIO_WIDTH - 1:0] gpioOut;    \n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:99: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    assign gpioOut   = bWData [`SM_GPIO_WIDTH - 1:0];\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:102: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    sm_debouncer   #(`SM_GPIO_WIDTH) debounce(clk, gpioInput, gpioIn);\n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:103: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    sm_register_we #(`SM_GPIO_WIDTH) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);\n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:105: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;\n                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;\n                                                ^\n%Error: Exiting due to 15 error(s)\n'
module ahb_gpio
(

    input            HCLK,
    input            HRESETn,
    input            HSEL,
    input            HWRITE,
    input            HREADY,
    input     [ 1:0] HTRANS,
    input     [31:0] HADDR,
    output    [31:0] HRDATA,
    input     [31:0] HWDATA,
    output           HREADYOUT,
    output           HRESP,


    input  [`SM_GPIO_WIDTH - 1:0] port_gpioIn,
    output [`SM_GPIO_WIDTH - 1:0] port_gpioOut
);

    wire request   = HREADY & HSEL & HTRANS != `HTRANS_IDLE;
    wire request_r = request & !HWRITE;

    wire request_w;
    wire request_w_new = request & HWRITE;
    sm_register_c r_request_w (HCLK, HRESETn, request_w_new, request_w);

    wire [31:0] addr_w;
    wire [31:0] addr_r = HADDR;
    sm_register_we #(32) r_addr_w (HCLK, HRESETn, request, HADDR, addr_w);


    wire        pm_we    = request_w;
    wire [31:0] pm_wd    = HWDATA;
    wire [31:0] pm_addr  = request_w ? addr_w : addr_r;
    wire        pm_valid = request_r | request_w;
    wire [31:0] pm_rd;

    sm_gpio gpio
    (
        .clk        ( HCLK         ),
        .rst_n      ( HRESETn      ),
        .bSel       ( pm_valid     ),
        .bAddr      ( pm_addr      ),
        .bWrite     ( pm_we        ),
        .bWData     ( pm_wd        ),
        .bRData     ( pm_rd        ),
        .gpioInput  ( port_gpioIn  ),
        .gpioOutput ( port_gpioOut )
    );


    wire hz_raw;
    wire hz_raw_new = (request_r & request_w) | request_w_new;
    sm_register_c r_hz_raw (HCLK, HRESETn, hz_raw_new, hz_raw );


    assign HREADYOUT = ~hz_raw;
    assign HRDATA    = pm_rd;
    assign HRESP     = 1'b0;

endmodule
module ahb_gpio
(

    input            HCLK,
    input            HRESETn,
    input            HSEL,
    input            HWRITE,
    input            HREADY,
    input     [ 1:0] HTRANS,
    input     [31:0] HADDR,
    output    [31:0] HRDATA,
    input     [31:0] HWDATA,
    output           HREADYOUT,
    output           HRESP,


    input  [`SM_GPIO_WIDTH - 1:0] port_gpioIn,
    output [`SM_GPIO_WIDTH - 1:0] port_gpioOut
);


    wire request   = HREADY & HSEL & HTRANS != `HTRANS_IDLE;
    wire request_r = request & !HWRITE;

    wire request_w;
    wire request_w_new = request & HWRITE;
    sm_register_c r_request_w (HCLK, HRESETn, request_w_new, request_w);

    wire [31:0] addr_w;
    wire [31:0] addr_r = HADDR;
    sm_register_we #(32) r_addr_w (HCLK, HRESETn, request, HADDR, addr_w);


    wire        pm_we    = request_w;
    wire [31:0] pm_wd    = HWDATA;
    wire [31:0] pm_addr  = request_w ? addr_w : addr_r;
    wire        pm_valid = request_r | request_w;
    wire [31:0] pm_rd;

    sm_gpio gpio
    (
        .clk        ( HCLK         ),
        .rst_n      ( HRESETn      ),
        .bSel       ( pm_valid     ),
        .bAddr      ( pm_addr      ),
        .bWrite     ( pm_we        ),
        .bWData     ( pm_wd        ),
        .bRData     ( pm_rd        ),
        .gpioInput  ( port_gpioIn  ),
        .gpioOutput ( port_gpioOut )
    );


    wire hz_raw;
    wire hz_raw_new = (request_r & request_w) | request_w_new;
    sm_register_c r_hz_raw (HCLK, HRESETn, hz_raw_new, hz_raw );


    assign HREADYOUT = ~hz_raw;
    assign HRDATA    = pm_rd;
    assign HRESP     = 1'b0;

endmodule