data/full_repos/permissive/150499967/basic controller/sram_ctrl2.v
1: b'%Error: Cannot find file containing module: controller,data/full_repos/permissive/150499967\n        ... Looked in:\n             data/full_repos/permissive/150499967/basic/controller,data/full_repos/permissive/150499967\n             data/full_repos/permissive/150499967/basic/controller,data/full_repos/permissive/150499967.v\n             data/full_repos/permissive/150499967/basic/controller,data/full_repos/permissive/150499967.sv\n             controller,data/full_repos/permissive/150499967\n             controller,data/full_repos/permissive/150499967.v\n             controller,data/full_repos/permissive/150499967.sv\n             obj_dir/controller,data/full_repos/permissive/150499967\n             obj_dir/controller,data/full_repos/permissive/150499967.v\n             obj_dir/controller,data/full_repos/permissive/150499967.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/150499967/basic\n%Error: Cannot find file containing module: controller/sram_ctrl2.v\n%Error: Exiting due to 3 error(s)\n'
module sram_ctrl2(

  input wire clk,
  input wire reset,

  input wire rw,
  input wire [18:0] addr,
  input wire [7:0] data_f2s,
  
  output reg [7:0] data_s2f_r,
  output wire [18:0] ad,
  output wire we_n,
  output wire oe_n,

  inout wire [7:0] dio_a,
  output wire ce_a_n
  );

  assign ce_a_n = 1'b0;
  assign oe_n = 1'b0;
  assign we_n = rw;
  assign ad = addr;
  
  assign dio_a = (rw == 1'b1)? 8'hZZ : data_f2s;
  
  always @(posedge clk) begin
    if (rw == 1'b1)
      data_s2f_r <= dio_a;
  end
endmodule
module sram_ctrl2(

  input wire clk,
  input wire reset,

  input wire rw,
  input wire [18:0] addr,
  input wire [7:0] data_f2s,
  
  output reg [7:0] data_s2f_r,
  output wire [18:0] ad,
  output wire we_n,
  output wire oe_n,

  inout wire [7:0] dio_a,
  output wire ce_a_n
  );


  assign ce_a_n = 1'b0;
  assign oe_n = 1'b0;
  assign we_n = rw;
  assign ad = addr;
  
  assign dio_a = (rw == 1'b1)? 8'hZZ : data_f2s;
  
  always @(posedge clk) begin
    if (rw == 1'b1)
      data_s2f_r <= dio_a;
  end
endmodule