data/full_repos/permissive/174917352/RTL/MemChange.v
1: b"%Error: data/full_repos/permissive/174917352/RTL/MemChange.v:178: Cannot find file containing module: 'Memory'\nMemory Memory1(.clk(clk),\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174917352/RTL,data/full_repos/permissive/174917352/Memory\n             data/full_repos/permissive/174917352/RTL,data/full_repos/permissive/174917352/Memory.v\n             data/full_repos/permissive/174917352/RTL,data/full_repos/permissive/174917352/Memory.sv\n             Memory\n             Memory.v\n             Memory.sv\n             obj_dir/Memory\n             obj_dir/Memory.v\n             obj_dir/Memory.sv\n%Error: data/full_repos/permissive/174917352/RTL/MemChange.v:185: Cannot find file containing module: 'Memory'\nMemory Memory2(.clk(clk),\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module MemChange(clk,
                 rst_b,
                 data_in,
                 start,
                 mode_data_in,
                 data_out,
                 mode_data_out,
                 output_start_col);
input wire clk;
input wire rst_b;
input wire [15:0]data_in;
input wire mode_data_in;
input wire start;

output reg [15:0]data_out;
output reg mode_data_out;
output reg output_start_col;

reg output_start;

reg Mem1_mode;
reg Mem2_mode;

reg [5:0]Mem1_addr;
reg [5:0]Mem1_addr_temp;

reg write_read_Mem1;
wire [15:0]data_out_Mem1;

wire [15:0]data_out_Mem2;
reg write_read_Mem2;
reg [5:0]Mem2_addr;
reg [5:0]Mem2_addr_temp;





always @(posedge clk)
if(!rst_b)
    write_read_Mem1 <= 1'b0;
else if(start & Mem1_addr == 6'b111111)
    write_read_Mem1 <= !write_read_Mem1;
else 
    write_read_Mem1 <= write_read_Mem1;

always @(posedge clk)
if(!rst_b)
    write_read_Mem2 <= 1'b1;
else if(start & Mem2_addr == 6'b111111)
    write_read_Mem2 <= !write_read_Mem2;
else 
    write_read_Mem2 <= write_read_Mem2;

always @(posedge clk)
if(!rst_b)
    Mem1_mode <= 1'b1;
else if(start & !write_read_Mem1)
    Mem1_mode <= mode_data_in;
else 
    Mem1_mode <= Mem1_mode;

always @(posedge clk)
if(!rst_b)
    Mem2_mode <= 1'b1;
else if(start & !write_read_Mem2)
    Mem2_mode <= mode_data_in;
else 
    Mem2_mode <= Mem2_mode;

always @(posedge clk)
if(!rst_b)
    output_start <= 1'b0;
else if(Mem1_addr == 6'b111111)
    output_start <= 1'b1;
else 
    output_start <= output_start;

always @(posedge clk)
if(!rst_b)
    output_start_col <= 1'b0;
else output_start_col <= output_start;

always @(posedge clk)
if(!rst_b)
    mode_data_out <= 1'b1;
else
    mode_data_out <= write_read_Mem1 ? Mem1_mode : Mem2_mode;


always @(posedge clk)
if(!rst_b)
    data_out <= 16'b0;
else if(output_start)
    data_out <= write_read_Mem1 ? data_out_Mem1 : data_out_Mem2;
else 
    data_out <= 16'b0;

always @(posedge clk)
if(!rst_b)
    Mem1_addr_temp <= 6'b000001;
else if(start)
    Mem1_addr_temp <= Mem1_addr_temp + 1'b1;
else Mem1_addr_temp <= Mem1_addr_temp;

always @(posedge clk)
if(!rst_b)
    Mem2_addr_temp <= 6'b000001;
else if(start)
    Mem2_addr_temp <= Mem2_addr_temp + 1'b1;
else Mem2_addr_temp <= Mem2_addr_temp;

always @(posedge clk)
if(!rst_b)
    Mem1_addr <= 6'b0;
else if(start & !write_read_Mem1)
    Mem1_addr <= Mem1_addr + 1'b1;

else if(start & write_read_Mem1 & !Mem1_mode)
    Mem1_addr <= {Mem1_addr_temp[5:4],Mem1_addr_temp[1:0],Mem1_addr_temp[3:2]};

else if(start & write_read_Mem1 & Mem1_mode)
    Mem1_addr <= {Mem1_addr_temp[2:0],Mem1_addr_temp[5:3]};

else Mem1_addr <= Mem1_addr;

always @(posedge clk)
if(!rst_b)
    Mem2_addr <= 6'b0;
else if(start & !write_read_Mem2)
    Mem2_addr <= Mem2_addr + 1'b1;

else if(start & write_read_Mem2 & !Mem2_mode)
    Mem2_addr <= {Mem2_addr_temp[5:4],Mem2_addr_temp[1:0],Mem2_addr_temp[3:2]};

else if(start & write_read_Mem2 & Mem2_mode)
    Mem2_addr <= {Mem2_addr_temp[2:0],Mem2_addr_temp[5:3]};

else Mem2_addr <= Mem2_addr;



Memory Memory1(.clk(clk),
               .rst_b(rst_b),
               .addr(Mem1_addr),
               .data_in(data_in),
               .write_read(write_read_Mem1),
               .data_out(data_out_Mem1));

Memory Memory2(.clk(clk),
               .rst_b(rst_b),
               .addr(Mem2_addr),
               .data_in(data_in),
               .write_read(write_read_Mem2),
               .data_out(data_out_Mem2));

endmodule
module MemChange(clk,
                 rst_b,
                 data_in,
                 start,
                 mode_data_in,
                 data_out,
                 mode_data_out,
                 output_start_col);

input wire clk;
input wire rst_b;
input wire [15:0]data_in;
input wire mode_data_in;
input wire start;

output reg [15:0]data_out;
output reg mode_data_out;
output reg output_start_col;

reg output_start;

reg Mem1_mode;
reg Mem2_mode;

reg [5:0]Mem1_addr;
reg [5:0]Mem1_addr_temp;

reg write_read_Mem1;
wire [15:0]data_out_Mem1;

wire [15:0]data_out_Mem2;
reg write_read_Mem2;
reg [5:0]Mem2_addr;
reg [5:0]Mem2_addr_temp;





always @(posedge clk)
if(!rst_b)
    write_read_Mem1 <= 1'b0;
else if(start & Mem1_addr == 6'b111111)
    write_read_Mem1 <= !write_read_Mem1;
else 
    write_read_Mem1 <= write_read_Mem1;

always @(posedge clk)
if(!rst_b)
    write_read_Mem2 <= 1'b1;
else if(start & Mem2_addr == 6'b111111)
    write_read_Mem2 <= !write_read_Mem2;
else 
    write_read_Mem2 <= write_read_Mem2;

always @(posedge clk)
if(!rst_b)
    Mem1_mode <= 1'b1;
else if(start & !write_read_Mem1)
    Mem1_mode <= mode_data_in;
else 
    Mem1_mode <= Mem1_mode;

always @(posedge clk)
if(!rst_b)
    Mem2_mode <= 1'b1;
else if(start & !write_read_Mem2)
    Mem2_mode <= mode_data_in;
else 
    Mem2_mode <= Mem2_mode;

always @(posedge clk)
if(!rst_b)
    output_start <= 1'b0;
else if(Mem1_addr == 6'b111111)
    output_start <= 1'b1;
else 
    output_start <= output_start;

always @(posedge clk)
if(!rst_b)
    output_start_col <= 1'b0;
else output_start_col <= output_start;

always @(posedge clk)
if(!rst_b)
    mode_data_out <= 1'b1;
else
    mode_data_out <= write_read_Mem1 ? Mem1_mode : Mem2_mode;


always @(posedge clk)
if(!rst_b)
    data_out <= 16'b0;
else if(output_start)
    data_out <= write_read_Mem1 ? data_out_Mem1 : data_out_Mem2;
else 
    data_out <= 16'b0;

always @(posedge clk)
if(!rst_b)
    Mem1_addr_temp <= 6'b000001;
else if(start)
    Mem1_addr_temp <= Mem1_addr_temp + 1'b1;
else Mem1_addr_temp <= Mem1_addr_temp;

always @(posedge clk)
if(!rst_b)
    Mem2_addr_temp <= 6'b000001;
else if(start)
    Mem2_addr_temp <= Mem2_addr_temp + 1'b1;
else Mem2_addr_temp <= Mem2_addr_temp;

always @(posedge clk)
if(!rst_b)
    Mem1_addr <= 6'b0;
else if(start & !write_read_Mem1)
    Mem1_addr <= Mem1_addr + 1'b1;

else if(start & write_read_Mem1 & !Mem1_mode)
    Mem1_addr <= {Mem1_addr_temp[5:4],Mem1_addr_temp[1:0],Mem1_addr_temp[3:2]};

else if(start & write_read_Mem1 & Mem1_mode)
    Mem1_addr <= {Mem1_addr_temp[2:0],Mem1_addr_temp[5:3]};

else Mem1_addr <= Mem1_addr;

always @(posedge clk)
if(!rst_b)
    Mem2_addr <= 6'b0;
else if(start & !write_read_Mem2)
    Mem2_addr <= Mem2_addr + 1'b1;

else if(start & write_read_Mem2 & !Mem2_mode)
    Mem2_addr <= {Mem2_addr_temp[5:4],Mem2_addr_temp[1:0],Mem2_addr_temp[3:2]};

else if(start & write_read_Mem2 & Mem2_mode)
    Mem2_addr <= {Mem2_addr_temp[2:0],Mem2_addr_temp[5:3]};

else Mem2_addr <= Mem2_addr;



Memory Memory1(.clk(clk),
               .rst_b(rst_b),
               .addr(Mem1_addr),
               .data_in(data_in),
               .write_read(write_read_Mem1),
               .data_out(data_out_Mem1));

Memory Memory2(.clk(clk),
               .rst_b(rst_b),
               .addr(Mem2_addr),
               .data_in(data_in),
               .write_read(write_read_Mem2),
               .data_out(data_out_Mem2));

endmodule