data/full_repos/permissive/2084115/projects/cq-frk-s3e2/sim/tb_top.v
 line:28: before: "begin"
1: b'%Error: data/full_repos/permissive/2084115/projects/cq-frk-s3e2/sim/tb_top.v:12: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("tb_top.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/projects/cq-frk-s3e2/sim/tb_top.v:13: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, tb_top);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/cq-frk-s3e2/sim/tb_top.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #0   reset = 1\'b1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/cq-frk-s3e2/sim/tb_top.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #(RATE*10) reset = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/cq-frk-s3e2/sim/tb_top.v:28: Unsupported: Ignoring delay on this delayed statement.\n always #(RATE/2) begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/projects/cq-frk-s3e2/sim/tb_top.v:53: Unsupported: Ignoring delay on this delayed statement.\n #(RATE*100000);\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top;
	parameter	SIMULATION = 1'b1;

	parameter	RATE       = 20;
	parameter	UART_RATE  = (1000000000 / 115200);
	
	
	initial begin
		$dumpfile("tb_top.vcd");
		$dumpvars(0, tb_top);
	end
	

	reg		reset;
	initial begin
		#0			reset = 1'b1;
		#(RATE*10)	reset = 1'b0;
	end
	

	reg		clk;
	initial begin
		clk    = 1'b1;
	end
	always #(RATE/2) begin
		clk = ~clk;
	end
	
	top
			#(
				.SIMULATION			(SIMULATION)
			)
		i_top
			(
				.in_clk				(clk),
				.in_reset_n			(!reset),
				
				.uart0_tx			(),
				.uart0_rx			(1'b1),
				
				.uart1_tx			(),
				.uart1_rx			(1'b1),
				
				.led				()
			);
	
	
	initial begin
				$display("--- START ---");
	#(RATE*100000);
				$finish;
	end	
	
endmodule
module tb_top;

	parameter	SIMULATION = 1'b1;

	parameter	RATE       = 20;
	parameter	UART_RATE  = (1000000000 / 115200);
	
	
	initial begin
		$dumpfile("tb_top.vcd");
		$dumpvars(0, tb_top);
	end
	

	reg		reset;
	initial begin
		#0			reset = 1'b1;
		#(RATE*10)	reset = 1'b0;
	end
	

	reg		clk;
	initial begin
		clk    = 1'b1;
	end
	always #(RATE/2) begin
		clk = ~clk;
	end
	
	top
			#(
				.SIMULATION			(SIMULATION)
			)
		i_top
			(
				.in_clk				(clk),
				.in_reset_n			(!reset),
				
				.uart0_tx			(),
				.uart0_rx			(1'b1),
				
				.uart1_tx			(),
				.uart1_rx			(1'b1),
				
				.led				()
			);
	
	
	initial begin
				$display("--- START ---");
	#(RATE*100000);
				$finish;
	end	
	
endmodule