data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #5 i_rst    = 1\'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #5 i_instruction [31:26]   = 6\'b000000;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction [5 :0 ]   = 6\'b100100;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction [5 :0 ]   = 6\'b100101;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction [5 :0 ]   = 6\'b001000;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction [5 :0 ]   = 6\'b001001;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:75: Unsupported: Ignoring delay on this delayed statement.\n       #5  i_instruction [31:26]   = 6\'b100000;         \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:82: Unsupported: Ignoring delay on this delayed statement.\n       #5  i_instruction [31:26]   = 6\'b100001;         \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:86: Unsupported: Ignoring delay on this delayed statement.\n       #5  i_instruction [31:26]   = 6\'b100011;         \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:90: Unsupported: Ignoring delay on this delayed statement.\n       #5  i_instruction [31:26]   = 6\'b100111;         \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:94: Unsupported: Ignoring delay on this delayed statement.\n       #5  i_instruction [31:26]   = 6\'b100100;         \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:98: Unsupported: Ignoring delay on this delayed statement.\n       #5  i_instruction [31:26]   = 6\'b100101;         \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction [31:26]   = 6\'b101000;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction [31:26]   = 6\'b101001;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:111: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction [31:26]   = 6\'b101011;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:116: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction [31:26]   = 6\'b001000;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction [31:26]   = 6\'b000100;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:125: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction [31:26]   = 6\'b000101;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction [31:26]   = 6\'b000010;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:133: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction [31:26]   = 6\'b000011;         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:138: Unsupported: Ignoring delay on this delayed statement.\n        #5  i_instruction           = 32\'h01094020;      \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #5 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:143: Unsupported: Ignoring delay on this delayed statement.\n    always #2.5 i_clk = ~i_clk;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:51: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                      : ... In instance tb_seg_instruction_decode\n        i_PC[31:26]     = 6\'b111100; i_PC[25:0] = $random; \n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:63: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                      : ... In instance tb_seg_instruction_decode\n            i_instruction [25:6 ]   = $random;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:78: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                      : ... In instance tb_seg_instruction_decode\n           i_instruction [15:0 ]   = $random;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:87: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                      : ... In instance tb_seg_instruction_decode\n           i_instruction [25:0 ]   = $random;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:91: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                      : ... In instance tb_seg_instruction_decode\n           i_instruction [25:0 ]   = $random;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:95: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                      : ... In instance tb_seg_instruction_decode\n           i_instruction [25:0 ]   = $random;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:99: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                      : ... In instance tb_seg_instruction_decode\n           i_instruction [25:0 ]   = $random;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:104: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                       : ... In instance tb_seg_instruction_decode\n            i_instruction [25:0 ]   = $random;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:108: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                       : ... In instance tb_seg_instruction_decode\n            i_instruction [25:0 ]   = $random;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:112: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                       : ... In instance tb_seg_instruction_decode\n            i_instruction [25:0 ]   = $random;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:117: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                       : ... In instance tb_seg_instruction_decode\n            i_instruction [25:0 ]   = $random;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:122: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                       : ... In instance tb_seg_instruction_decode\n            i_instruction [25:0 ]   = $random;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:126: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                       : ... In instance tb_seg_instruction_decode\n            i_instruction [25:0 ]   = $random;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:130: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                       : ... In instance tb_seg_instruction_decode\n            i_instruction [25:0 ]   = $random;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:134: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                       : ... In instance tb_seg_instruction_decode\n            i_instruction [25:0 ]   = $random;\n                                    ^\n%Error: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_seg_instruction_decode.v:145: Cannot find file containing module: \'seg_instruction_decode\'\n    seg_instruction_decode \n    ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_instruction_decode\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_instruction_decode.v\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/seg_instruction_decode.sv\n             seg_instruction_decode\n             seg_instruction_decode.v\n             seg_instruction_decode.sv\n             obj_dir/seg_instruction_decode\n             obj_dir/seg_instruction_decode.v\n             obj_dir/seg_instruction_decode.sv\n%Error: Exiting due to 1 error(s), 38 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_seg_instruction_decode();
    localparam LEN           = 32;
    localparam NB_REG        = 32;
    localparam NB_ADDRESS    = 16;
    localparam NB_OPCODE     = 6;
    localparam NB_ADDR       = 5;
    localparam NB_CTRL_EX    = 6;
    localparam NB_CTRL_M     = 9;
    localparam NB_CTRL_WB    = 2;


    reg                     i_clk;
    reg                     i_rst;
    reg [LEN-1:0]           i_PC;
    reg [LEN-1:0]           i_instruction;
    reg [NB_ADDR-1:0]       i_write_reg;
    reg [LEN-1:0]           i_write_data;
    reg                     i_RegWrite;
    reg                     i_flush;
    reg [NB_ADDR-1:0]       i_rt_ex;       


    

    wire [NB_ADDR-1:0]      o_rs;
    wire [NB_ADDR-1:0]      o_rt;
    wire [NB_ADDR-1:0]      o_rd;
    wire [LEN-1:0]          o_PC;
    wire [LEN-1:0]          o_addr_ext;
    wire [LEN-1:0]          o_read_data_1;
    wire [LEN-1:0]          o_read_data_2;
    wire [LEN-1:0]          o_PC_dir_jump;
    wire                    o_jump_flag;
    wire                    o_stall_flag;


    

    wire [NB_CTRL_WB-1:0]   o_ctrl_wb_bus;
    wire [NB_CTRL_M-1:0]    o_ctrl_mem_bus;
    wire [NB_CTRL_EX-1:0]   o_ctrl_exc_bus;

    initial begin
        i_clk = 1'b0;
        i_rst = 1'b0;
        i_write_data    = 32'h0000abcd;
        i_PC[31:26]     = 6'b111100; i_PC[25:0] = $random; 
        i_instruction   = 32'b00000000;
        i_write_reg     = 5'b00010;
        i_rt_ex         = 5'b00001;
        i_RegWrite      = 1'b0;
        i_flush         = 1'b1;

        #5 i_rst    = 1'b1;
           i_flush  = 1'b0;
        

        #5 i_instruction [31:26]   = 6'b000000;
            i_instruction [25:6 ]   = $random;
            i_instruction [5 :0 ]   = 6'b100001;
            i_RegWrite              = 1'b1;        
        
        #5  i_instruction [5 :0 ]   = 6'b100100;
        #5  i_instruction [5 :0 ]   = 6'b100101;
  
        #5  i_instruction [5 :0 ]   = 6'b001000;
        #5  i_instruction [5 :0 ]   = 6'b001001;


       
       #5  i_instruction [31:26]   = 6'b100000;
           i_instruction [25:21]   = 5'b01011;
           i_instruction [20:16]   = 5'b00001;
           i_instruction [15:0 ]   = $random;
           i_RegWrite              = 1'b1;
           

       #5  i_instruction [31:26]   = 6'b100001;
           i_instruction [20:16]   = 5'b00010;
           i_RegWrite              = 1'b1;
        
       #5  i_instruction [31:26]   = 6'b100011;
           i_instruction [25:0 ]   = $random;
           i_RegWrite              = 1'b1;

       #5  i_instruction [31:26]   = 6'b100111;
           i_instruction [25:0 ]   = $random;
           i_RegWrite              = 1'b1;
        
       #5  i_instruction [31:26]   = 6'b100100;
           i_instruction [25:0 ]   = $random;
           i_RegWrite              = 1'b1;
        
       #5  i_instruction [31:26]   = 6'b100101;
           i_instruction [25:0 ]   = $random;
           i_RegWrite              = 1'b1;


        #5  i_instruction [31:26]   = 6'b101000;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;

        #5  i_instruction [31:26]   = 6'b101001;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;

        #5  i_instruction [31:26]   = 6'b101011;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;


        #5  i_instruction [31:26]   = 6'b001000;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b1;


        #5  i_instruction [31:26]   = 6'b000100;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;

        #5  i_instruction [31:26]   = 6'b000101;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;

        #5  i_instruction [31:26]   = 6'b000010;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;

        #5  i_instruction [31:26]   = 6'b000011;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;


        #5  i_instruction           = 32'h01094020;
                    
        #5 $finish;
    end

    always #2.5 i_clk = ~i_clk;

    seg_instruction_decode 
    #(
        .LEN        (LEN        ),
        .NB_REG     (NB_REG     ),
        .NB_ADDRESS (NB_ADDRESS ),
        .NB_OPCODE  (NB_OPCODE  ),
        .NB_ADDR    (NB_ADDR    ),
        .NB_CTRL_EX (NB_CTRL_EX ),
        .NB_CTRL_M  (NB_CTRL_M  ),
        .NB_CTRL_WB (NB_CTRL_WB )
    )
    u_seg_instruction_decode(
    	.i_clk          (i_clk          ),
        .i_rst          (i_rst          ),
        .i_PC           (i_PC           ),
        .i_instruction  (i_instruction  ),
        .i_write_reg    (i_write_reg    ),
        .i_write_data   (i_write_data   ),
        .i_RegWrite     (i_RegWrite     ),
        .i_flush        (i_flush        ),
        .i_rt_ex        (i_rt_ex        ),


        .o_rs           (o_rs           ),
        .o_rt           (o_rt           ),
        .o_rd           (o_rd           ),
        .o_PC           (o_PC           ),
        .o_addr_ext     (o_addr_ext     ),
        .o_read_data_1  (o_read_data_1  ),
        .o_read_data_2  (o_read_data_2  ),
        .o_PC_dir_jump  (o_PC_dir_jump  ),
        .o_jump_flag    (o_jump_flag    ),
        .o_stall_flag   (o_stall_flag   ),


        .o_ctrl_wb_bus  (o_ctrl_wb_bus  ),
        .o_ctrl_mem_bus (o_ctrl_mem_bus ),
        .o_ctrl_exc_bus (o_ctrl_exc_bus )
    );

endmodule
module tb_seg_instruction_decode();

    localparam LEN           = 32;
    localparam NB_REG        = 32;
    localparam NB_ADDRESS    = 16;
    localparam NB_OPCODE     = 6;
    localparam NB_ADDR       = 5;
    localparam NB_CTRL_EX    = 6;
    localparam NB_CTRL_M     = 9;
    localparam NB_CTRL_WB    = 2;


    reg                     i_clk;
    reg                     i_rst;
    reg [LEN-1:0]           i_PC;
    reg [LEN-1:0]           i_instruction;
    reg [NB_ADDR-1:0]       i_write_reg;
    reg [LEN-1:0]           i_write_data;
    reg                     i_RegWrite;
    reg                     i_flush;
    reg [NB_ADDR-1:0]       i_rt_ex;       


    

    wire [NB_ADDR-1:0]      o_rs;
    wire [NB_ADDR-1:0]      o_rt;
    wire [NB_ADDR-1:0]      o_rd;
    wire [LEN-1:0]          o_PC;
    wire [LEN-1:0]          o_addr_ext;
    wire [LEN-1:0]          o_read_data_1;
    wire [LEN-1:0]          o_read_data_2;
    wire [LEN-1:0]          o_PC_dir_jump;
    wire                    o_jump_flag;
    wire                    o_stall_flag;


    

    wire [NB_CTRL_WB-1:0]   o_ctrl_wb_bus;
    wire [NB_CTRL_M-1:0]    o_ctrl_mem_bus;
    wire [NB_CTRL_EX-1:0]   o_ctrl_exc_bus;

    initial begin
        i_clk = 1'b0;
        i_rst = 1'b0;
        i_write_data    = 32'h0000abcd;
        i_PC[31:26]     = 6'b111100; i_PC[25:0] = $random; 
        i_instruction   = 32'b00000000;
        i_write_reg     = 5'b00010;
        i_rt_ex         = 5'b00001;
        i_RegWrite      = 1'b0;
        i_flush         = 1'b1;

        #5 i_rst    = 1'b1;
           i_flush  = 1'b0;
        

        #5 i_instruction [31:26]   = 6'b000000;
            i_instruction [25:6 ]   = $random;
            i_instruction [5 :0 ]   = 6'b100001;
            i_RegWrite              = 1'b1;        
        
        #5  i_instruction [5 :0 ]   = 6'b100100;
        #5  i_instruction [5 :0 ]   = 6'b100101;
  
        #5  i_instruction [5 :0 ]   = 6'b001000;
        #5  i_instruction [5 :0 ]   = 6'b001001;


       
       #5  i_instruction [31:26]   = 6'b100000;
           i_instruction [25:21]   = 5'b01011;
           i_instruction [20:16]   = 5'b00001;
           i_instruction [15:0 ]   = $random;
           i_RegWrite              = 1'b1;
           

       #5  i_instruction [31:26]   = 6'b100001;
           i_instruction [20:16]   = 5'b00010;
           i_RegWrite              = 1'b1;
        
       #5  i_instruction [31:26]   = 6'b100011;
           i_instruction [25:0 ]   = $random;
           i_RegWrite              = 1'b1;

       #5  i_instruction [31:26]   = 6'b100111;
           i_instruction [25:0 ]   = $random;
           i_RegWrite              = 1'b1;
        
       #5  i_instruction [31:26]   = 6'b100100;
           i_instruction [25:0 ]   = $random;
           i_RegWrite              = 1'b1;
        
       #5  i_instruction [31:26]   = 6'b100101;
           i_instruction [25:0 ]   = $random;
           i_RegWrite              = 1'b1;


        #5  i_instruction [31:26]   = 6'b101000;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;

        #5  i_instruction [31:26]   = 6'b101001;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;

        #5  i_instruction [31:26]   = 6'b101011;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;


        #5  i_instruction [31:26]   = 6'b001000;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b1;


        #5  i_instruction [31:26]   = 6'b000100;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;

        #5  i_instruction [31:26]   = 6'b000101;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;

        #5  i_instruction [31:26]   = 6'b000010;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;

        #5  i_instruction [31:26]   = 6'b000011;
            i_instruction [25:0 ]   = $random;
            i_RegWrite              = 1'b0;


        #5  i_instruction           = 32'h01094020;
                    
        #5 $finish;
    end

    always #2.5 i_clk = ~i_clk;

    seg_instruction_decode 
    #(
        .LEN        (LEN        ),
        .NB_REG     (NB_REG     ),
        .NB_ADDRESS (NB_ADDRESS ),
        .NB_OPCODE  (NB_OPCODE  ),
        .NB_ADDR    (NB_ADDR    ),
        .NB_CTRL_EX (NB_CTRL_EX ),
        .NB_CTRL_M  (NB_CTRL_M  ),
        .NB_CTRL_WB (NB_CTRL_WB )
    )
    u_seg_instruction_decode(
    	.i_clk          (i_clk          ),
        .i_rst          (i_rst          ),
        .i_PC           (i_PC           ),
        .i_instruction  (i_instruction  ),
        .i_write_reg    (i_write_reg    ),
        .i_write_data   (i_write_data   ),
        .i_RegWrite     (i_RegWrite     ),
        .i_flush        (i_flush        ),
        .i_rt_ex        (i_rt_ex        ),


        .o_rs           (o_rs           ),
        .o_rt           (o_rt           ),
        .o_rd           (o_rd           ),
        .o_PC           (o_PC           ),
        .o_addr_ext     (o_addr_ext     ),
        .o_read_data_1  (o_read_data_1  ),
        .o_read_data_2  (o_read_data_2  ),
        .o_PC_dir_jump  (o_PC_dir_jump  ),
        .o_jump_flag    (o_jump_flag    ),
        .o_stall_flag   (o_stall_flag   ),


        .o_ctrl_wb_bus  (o_ctrl_wb_bus  ),
        .o_ctrl_mem_bus (o_ctrl_mem_bus ),
        .o_ctrl_exc_bus (o_ctrl_exc_bus )
    );

endmodule