data/full_repos/permissive/198139336/2019_DD_LAB10/example/32mpy.v
1: b'%Warning-WIDTH: data/full_repos/permissive/198139336/2019_DD_LAB10/example/32mpy.v:18: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                                     : ... In instance lab\n  Counter <=6\'b0;\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/198139336/2019_DD_LAB10/example/32mpy.v:57: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h20\' generates 6 bits.\n                                                                                     : ... In instance lab\n else if(Counter==6\'d32)\n                ^~\n%Error: Exiting due to 2 warning(s)\n'
module lab(CLK, RST, in_a, in_b, Product, Product_Valid);
input CLK, RST;
input [31:0]	in_a;
input [31:0]	in_b;
output reg [63:0] Product;
output reg Product_Valid;

reg [63:0] Mplicand;
reg [31:0] Mplier;
reg [6:0]	Counter ;
reg	sign;


always @(posedge CLK or posedge RST)
begin
	if(RST)
		Counter <=6'b0;
	else
		Counter <= Counter +6'b1;
end


always @(posedge CLK or posedge RST)
begin

	if(RST) begin
		Product  <= 64'b0;
		Mplicand <= 64'b0;
		Mplier   <= 32'b0;	
	end 
	

	else if(Counter == 7'd0) begin
		Mplicand <= {32'b0,in_a};
		Mplier <= in_b;
	end 
	


	else if(Counter <=7'd32)
	begin
		if(Mplier[0] == 1'b1)
			Product <= Mplicand + Product;
			
		Mplicand <= Mplicand << 1'b1;
		Mplier <= Mplier >> 1'b1;
	end 

end


always @(posedge CLK or posedge RST)
begin
	if(RST)
		Product_Valid <=1'b0;
	else if(Counter==6'd32)
		Product_Valid <=1'b1;
	else
		Product_Valid <=1'b0;
end

endmodule
module lab(CLK, RST, in_a, in_b, Product, Product_Valid);

input CLK, RST;
input [31:0]	in_a;
input [31:0]	in_b;
output reg [63:0] Product;
output reg Product_Valid;

reg [63:0] Mplicand;
reg [31:0] Mplier;
reg [6:0]	Counter ;
reg	sign;


always @(posedge CLK or posedge RST)
begin
	if(RST)
		Counter <=6'b0;
	else
		Counter <= Counter +6'b1;
end


always @(posedge CLK or posedge RST)
begin

	if(RST) begin
		Product  <= 64'b0;
		Mplicand <= 64'b0;
		Mplier   <= 32'b0;	
	end 
	

	else if(Counter == 7'd0) begin
		Mplicand <= {32'b0,in_a};
		Mplier <= in_b;
	end 
	


	else if(Counter <=7'd32)
	begin
		if(Mplier[0] == 1'b1)
			Product <= Mplicand + Product;
			
		Mplicand <= Mplicand << 1'b1;
		Mplier <= Mplier >> 1'b1;
	end 

end


always @(posedge CLK or posedge RST)
begin
	if(RST)
		Product_Valid <=1'b0;
	else if(Counter==6'd32)
		Product_Valid <=1'b1;
	else
		Product_Valid <=1'b0;
end

endmodule