data/full_repos/permissive/213361049/tbalu.v
1: b'%Error: data/full_repos/permissive/213361049/tbalu.v:11: Unsupported or unknown PLI call: $monitor\n$monitor("A: %d B: %d Aluop: %b Output: %d",a,b,aluop,o);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:15: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:19: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:21: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:23: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:25: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:27: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:29: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:31: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:33: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:35: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:37: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:39: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:41: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/213361049/tbalu.v:43: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb();
reg [7:0]a;
reg [7:0]b;
wire [7:0]o;
reg [3:0]aluop;

alu my(a,b,o,aluop);

initial
begin
$monitor("A: %d B: %d Aluop: %b Output: %d",a,b,aluop,o);
a=64;
b=2;
aluop=0;
#5
aluop=1;
#5
aluop=2;
#5
aluop=3;
#5
aluop=4;
#5
aluop=5;
#5
aluop=6;
#5
aluop=7;
#5
aluop=8;
#5
aluop=9;
#5
aluop=10;
#5
aluop=11;
#5
aluop=12;
#5
aluop=13;
#5
aluop=14;
#5
aluop=15;

end
endmodule
module alu_tb();

reg [7:0]a;
reg [7:0]b;
wire [7:0]o;
reg [3:0]aluop;

alu my(a,b,o,aluop);

initial
begin
$monitor("A: %d B: %d Aluop: %b Output: %d",a,b,aluop,o);
a=64;
b=2;
aluop=0;
#5
aluop=1;
#5
aluop=2;
#5
aluop=3;
#5
aluop=4;
#5
aluop=5;
#5
aluop=6;
#5
aluop=7;
#5
aluop=8;
#5
aluop=9;
#5
aluop=10;
#5
aluop=11;
#5
aluop=12;
#5
aluop=13;
#5
aluop=14;
#5
aluop=15;

end
endmodule