data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/des3.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/des3.v:71: Cannot find file containing module: 'des'\ndes u0( .desOut(stage1_out), .desIn(desIn),  .key(key_a), .decrypt(decrypt), .clk(clk) );\n^~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl,data/full_repos/permissive/137416811/des\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl,data/full_repos/permissive/137416811/des.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl,data/full_repos/permissive/137416811/des.sv\n             des\n             des.v\n             des.sv\n             obj_dir/des\n             obj_dir/des.v\n             obj_dir/des.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/des3.v:73: Cannot find file containing module: 'des'\ndes u1( .desOut(stage2_out), .desIn(stage1_out), .key(key_b_r[16]), .decrypt(!decrypt), .clk(clk) );\n^~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/des3.v:75: Cannot find file containing module: 'des'\ndes u2( .desOut(desOut), .desIn(stage2_out), .key(key_c_r[33]), .decrypt(decrypt), .clk(clk) );\n^~~\n%Error: Exiting due to 3 error(s)\n"
module des3(desOut, desIn, key1, key2, key3, decrypt, clk); 
output	[63:0]	desOut;
input	[63:0]	desIn;
input	[55:0]	key1;
input	[55:0]	key2;
input	[55:0]	key3;
input		decrypt;
input		clk;

wire	[55:0]	key_a;
wire	[55:0]	key_b;
wire	[55:0]	key_c;
wire	[63:0]	stage1_out, stage2_out;
reg	[55:0]	key_b_r [16:0];
reg	[55:0]	key_c_r [33:0];
integer		i;

assign key_a = decrypt ? key3 : key1;
assign key_b = key2;
assign key_c = decrypt ? key1 : key3;

always @(posedge clk)
	key_b_r[0] <= #1 key_b;

always @(posedge clk)
	for(i=0;i<16;i=i+1)
		key_b_r[i+1] <= #1 key_b_r[i];


always @(posedge clk)
	key_c_r[0] <= #1 key_c;

always @(posedge clk)
	for(i=0;i<33;i=i+1)
		key_c_r[i+1] <= #1 key_c_r[i];

des u0(	.desOut(stage1_out),	.desIn(desIn),		.key(key_a), .decrypt(decrypt), .clk(clk) );

des u1(	.desOut(stage2_out),	.desIn(stage1_out),	.key(key_b_r[16]), .decrypt(!decrypt), .clk(clk) );

des u2(	.desOut(desOut),	.desIn(stage2_out),	.key(key_c_r[33]), .decrypt(decrypt),	.clk(clk) );

endmodule
module des3(desOut, desIn, key1, key2, key3, decrypt, clk);
 
output	[63:0]	desOut;
input	[63:0]	desIn;
input	[55:0]	key1;
input	[55:0]	key2;
input	[55:0]	key3;
input		decrypt;
input		clk;

wire	[55:0]	key_a;
wire	[55:0]	key_b;
wire	[55:0]	key_c;
wire	[63:0]	stage1_out, stage2_out;
reg	[55:0]	key_b_r [16:0];
reg	[55:0]	key_c_r [33:0];
integer		i;

assign key_a = decrypt ? key3 : key1;
assign key_b = key2;
assign key_c = decrypt ? key1 : key3;

always @(posedge clk)
	key_b_r[0] <= #1 key_b;

always @(posedge clk)
	for(i=0;i<16;i=i+1)
		key_b_r[i+1] <= #1 key_b_r[i];


always @(posedge clk)
	key_c_r[0] <= #1 key_c;

always @(posedge clk)
	for(i=0;i<33;i=i+1)
		key_c_r[i+1] <= #1 key_c_r[i];

des u0(	.desOut(stage1_out),	.desIn(desIn),		.key(key_a), .decrypt(decrypt), .clk(clk) );

des u1(	.desOut(stage2_out),	.desIn(stage1_out),	.key(key_b_r[16]), .decrypt(!decrypt), .clk(clk) );

des u2(	.desOut(desOut),	.desIn(stage2_out),	.key(key_c_r[33]), .decrypt(decrypt),	.clk(clk) );

endmodule