data/full_repos/permissive/14193640/fpga/register_with_write_enable.v
data/verilator_xmls/b2d945d3-3b2e-40e2-934b-125f060c14af.xml
module register_with_write_enable
  #(parameter WIDTH = 1)
   (
    input                  clk,
    input                  reset_n,
    input                  write_enable,
    input      [WIDTH-1:0] d,
    output reg [WIDTH-1:0] q
    );

   always @(posedge clk, negedge reset_n)
     if (!reset_n)
       q <= {WIDTH {1'b0}};
     else
       if (write_enable)
         q <= d;

endmodule
module register_with_write_enable
  #(parameter WIDTH = 1)
   (
    input                  clk,
    input                  reset_n,
    input                  write_enable,
    input      [WIDTH-1:0] d,
    output reg [WIDTH-1:0] q
    );


   always @(posedge clk, negedge reset_n)
     if (!reset_n)
       q <= {WIDTH {1'b0}};
     else
       if (write_enable)
         q <= d;

endmodule