data/full_repos/permissive/189158787/div/posit_div.v
Syntax Error
1: b'%Warning-MULTITOP: data/full_repos/permissive/189158787/div/posit_div.v:205: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'posit_div\'\nmodule posit_div(in1, in2, start, out, inf, zero, done);\n       ^~~~~~~~~\n                                                                           : ... Top module \'add_1\'\nmodule add_1 (a,mant_ovf,c);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:327: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 or 5 bits.\n                                                                        : ... In instance posit_div.uut_de1.xinst_k.l1\n    else if (N & (N-1))\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:327: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 bits.\n                                                                        : ... In instance posit_div.uut_de1.xinst_k.l1.genblk2.genblk2.h\n    else if (N & (N-1))\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:192: Operator SUB expects 9 bits on the RHS, but RHS\'s VARREF \'bin\' generates 1 bits.\n                                                                        : ... In instance posit_div.uut_div_e\nassign c = a - b - bin;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:60: Operator NEGATE expects 6 bits on the LHS, but LHS\'s VARREF \'regime1\' generates 4 bits.\n                                                                       : ... In instance posit_div\nwire [Bs+1:0] r1 = rc1 ? {2\'b0,regime1} : -regime1;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:61: Operator NEGATE expects 6 bits on the LHS, but LHS\'s VARREF \'regime2\' generates 4 bits.\n                                                                       : ... In instance posit_div\nwire [Bs+1:0] r2 = rc2 ? {2\'b0,regime2} : -regime2;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:117: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                        : ... In instance posit_div\nDSR_right_N_S #(.N(3*N+3), .S(Bs+1)) dsr2 (.a({tmp_o,{N{1\'b0}}}), .b(r_o[Bs] ? {Bs{1\'b1}} : r_o), .c(tmp1_o));\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/189158787/div/posit_div.v:210: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'mant_ovf\' generates 1 bits.\n                                                                        : ... In instance add_1\nassign c = a + mant_ovf;\n             ^\n%Error: Exiting due to 8 warning(s)\n'
module data_extract_v1(in, rc, regime, exp, mant);
function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction

parameter N=16;
parameter Bs=log2(N);
parameter es = 2;

input [N-1:0] in;
output rc;
output [Bs-1:0] regime;
output [es-1:0] exp;
output [N-es-1:0] mant;

wire [N-1:0] xin = in;
assign rc = xin[N-2];

wire [N-1:0] xin_r = rc ? ~xin : xin;

wire [Bs-1:0] k;
LOD_N #(.N(N)) xinst_k(.in({xin_r[N-2:0],rc^1'b0}), .out(k));

assign regime = rc ? k-1 : k;

wire [N-1:0] xin_tmp;
DSR_left_N_S #(.N(N), .S(Bs)) ls (.a({xin[N-3:0],2'b0}),.b(k),.c(xin_tmp));

assign exp= xin_tmp[N-1:N-es];
assign mant= xin_tmp[N-es-1:0];

endmodule
module data_extract_v1(in, rc, regime, exp, mant);

function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction

parameter N=16;
parameter Bs=log2(N);
parameter es = 2;

input [N-1:0] in;
output rc;
output [Bs-1:0] regime;
output [es-1:0] exp;
output [N-es-1:0] mant;

wire [N-1:0] xin = in;
assign rc = xin[N-2];

wire [N-1:0] xin_r = rc ? ~xin : xin;

wire [Bs-1:0] k;
LOD_N #(.N(N)) xinst_k(.in({xin_r[N-2:0],rc^1'b0}), .out(k));

assign regime = rc ? k-1 : k;

wire [N-1:0] xin_tmp;
DSR_left_N_S #(.N(N), .S(Bs)) ls (.a({xin[N-3:0],2'b0}),.b(k),.c(xin_tmp));

assign exp= xin_tmp[N-1:N-es];
assign mant= xin_tmp[N-es-1:0];

endmodule