data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/sram/sram_controller.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/sram/sram_controller.v:26: Signal definition not found, creating implicitly: \'sram_pins_clk\'\n                                                                                                              : ... Suggested alternative: \'sram_pins_dq\'\n assign   sram_pins_clk = CLOCK;\n          ^~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/sram/sram_controller.v:59: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 21 bits.\n                                                                                                           : ... In instance sram_controller\n      sram_pins_addr <= {sram_avalon_address, 1\'B0};\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/sram/sram_controller.v:71: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 21 bits.\n                                                                                                           : ... In instance sram_controller\n      sram_pins_addr <= {sram_avalon_address, 1\'B0};\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/sram/sram_controller.v:90: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 21 bits.\n                                                                                                           : ... In instance sram_controller\n     sram_pins_addr <= {sram_avalon_address, 1\'B1};\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/sram/sram_controller.v:100: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 21 bits.\n                                                                                                            : ... In instance sram_controller\n     sram_pins_addr <= {sram_avalon_address, 1\'B1};\n                    ^~\n%Error: Exiting due to 5 warning(s)\n'
module sram_controller
(
	input	wire						CLOCK,
	input	wire						RESET_N,
	output	wire						sram_avalon_clock,
	output	reg							sram_avalon_reset_n,
	input	wire	[19:0]				sram_avalon_address,
	input	wire	[31:0]				sram_avalon_writedata,
	input	wire						sram_avalon_write_n,
	input	wire						sram_avalon_read_n,
	output	reg		[31:0]				sram_avalon_readdata,
	output	reg							sram_avalon_readdatavalid,
	output	wire						sram_avalon_waitrequest,
	

	output	reg		[19:0]				sram_pins_addr,
	inout			[15:0]				sram_pins_dq,
	output	reg							sram_pins_ce_n,
	output	reg							sram_pins_oe_n,
	output	reg							sram_pins_we_n,
	output	reg							sram_pins_ub_n,
	output	reg							sram_pins_lb_n
);

	wire			afi_phy_clk = CLOCK;
	assign			sram_pins_clk = CLOCK;
	
	always @(posedge afi_phy_clk)
		sram_avalon_reset_n <= RESET_N;


	always @(posedge afi_phy_clk)
	begin
		sram_pins_ce_n <= 0;
		sram_pins_ub_n <= 0;
		sram_pins_lb_n <= 0;
	end

	reg			[3:0]		cstate;
	reg			[15:0]		sram_pins_dq_reg;
	reg						wait_request;
	reg						read_valid;
	assign					sram_avalon_waitrequest = (!sram_avalon_write_n || !sram_avalon_read_n) && !wait_request;
	always @(posedge afi_phy_clk)
		if(!RESET_N)
		begin
			cstate <= 0;
			wait_request <= 0;
			read_valid <= 0;
		end
		else
		begin
			case(cstate)
				0: begin

					if(!sram_avalon_write_n)
					begin

						sram_pins_addr <= {sram_avalon_address, 1'B0};
						sram_pins_dq_reg <= sram_avalon_writedata[15:0];
						wait_request <= 1;
						sram_pins_we_n <= 0;
						sram_pins_oe_n <= 1;

						cstate <= 1;
					end

					else if(!sram_avalon_read_n)
					begin

						sram_pins_addr <= {sram_avalon_address, 1'B0};
						wait_request <= 1;
						sram_pins_we_n <= 1;
						sram_pins_oe_n <= 0;

						cstate <= 2;
					end

					else
					begin
						sram_pins_we_n <= 1;
						sram_pins_oe_n <= 1;
						wait_request <= 0;
					end

					read_valid <= 0;
				end

				1: begin
					sram_pins_addr <= {sram_avalon_address, 1'B1};
					sram_pins_dq_reg <= sram_avalon_writedata[31:16];
					wait_request <= 0;
					sram_pins_we_n <= 0;
					sram_pins_oe_n <= 1;

					cstate <= 0;
				end
				
				2: begin
					sram_pins_addr <= {sram_avalon_address, 1'B1};
					wait_request <= 0;
					sram_pins_we_n <= 1;
					sram_pins_oe_n <= 0;

					cstate <= 0;

					read_valid <= 1;
				end	

				default: begin
					wait_request <= 0;
					cstate <= 0;
					read_valid <= 0;
				end
				
			endcase
		end
	
	


	always @(posedge afi_phy_clk)
	begin
		sram_avalon_readdata <= {sram_pins_dq, sram_avalon_readdata[31:16]};
		sram_avalon_readdatavalid <= read_valid;
	end
		
	


	assign	sram_avalon_clock = afi_phy_clk;
	

	assign	sram_pins_dq = !sram_pins_we_n? sram_pins_dq_reg : 16'HZZZZ;

endmodule
module sram_controller
(
	input	wire						CLOCK,
	input	wire						RESET_N,
	output	wire						sram_avalon_clock,
	output	reg							sram_avalon_reset_n,
	input	wire	[19:0]				sram_avalon_address,
	input	wire	[31:0]				sram_avalon_writedata,
	input	wire						sram_avalon_write_n,
	input	wire						sram_avalon_read_n,
	output	reg		[31:0]				sram_avalon_readdata,
	output	reg							sram_avalon_readdatavalid,
	output	wire						sram_avalon_waitrequest,
	

	output	reg		[19:0]				sram_pins_addr,
	inout			[15:0]				sram_pins_dq,
	output	reg							sram_pins_ce_n,
	output	reg							sram_pins_oe_n,
	output	reg							sram_pins_we_n,
	output	reg							sram_pins_ub_n,
	output	reg							sram_pins_lb_n
);


	wire			afi_phy_clk = CLOCK;
	assign			sram_pins_clk = CLOCK;
	
	always @(posedge afi_phy_clk)
		sram_avalon_reset_n <= RESET_N;


	always @(posedge afi_phy_clk)
	begin
		sram_pins_ce_n <= 0;
		sram_pins_ub_n <= 0;
		sram_pins_lb_n <= 0;
	end

	reg			[3:0]		cstate;
	reg			[15:0]		sram_pins_dq_reg;
	reg						wait_request;
	reg						read_valid;
	assign					sram_avalon_waitrequest = (!sram_avalon_write_n || !sram_avalon_read_n) && !wait_request;
	always @(posedge afi_phy_clk)
		if(!RESET_N)
		begin
			cstate <= 0;
			wait_request <= 0;
			read_valid <= 0;
		end
		else
		begin
			case(cstate)
				0: begin

					if(!sram_avalon_write_n)
					begin

						sram_pins_addr <= {sram_avalon_address, 1'B0};
						sram_pins_dq_reg <= sram_avalon_writedata[15:0];
						wait_request <= 1;
						sram_pins_we_n <= 0;
						sram_pins_oe_n <= 1;

						cstate <= 1;
					end

					else if(!sram_avalon_read_n)
					begin

						sram_pins_addr <= {sram_avalon_address, 1'B0};
						wait_request <= 1;
						sram_pins_we_n <= 1;
						sram_pins_oe_n <= 0;

						cstate <= 2;
					end

					else
					begin
						sram_pins_we_n <= 1;
						sram_pins_oe_n <= 1;
						wait_request <= 0;
					end

					read_valid <= 0;
				end

				1: begin
					sram_pins_addr <= {sram_avalon_address, 1'B1};
					sram_pins_dq_reg <= sram_avalon_writedata[31:16];
					wait_request <= 0;
					sram_pins_we_n <= 0;
					sram_pins_oe_n <= 1;

					cstate <= 0;
				end
				
				2: begin
					sram_pins_addr <= {sram_avalon_address, 1'B1};
					wait_request <= 0;
					sram_pins_we_n <= 1;
					sram_pins_oe_n <= 0;

					cstate <= 0;

					read_valid <= 1;
				end	

				default: begin
					wait_request <= 0;
					cstate <= 0;
					read_valid <= 0;
				end
				
			endcase
		end
	
	


	always @(posedge afi_phy_clk)
	begin
		sram_avalon_readdata <= {sram_pins_dq, sram_avalon_readdata[31:16]};
		sram_avalon_readdatavalid <= read_valid;
	end
		
	


	assign	sram_avalon_clock = afi_phy_clk;
	

	assign	sram_pins_dq = !sram_pins_we_n? sram_pins_dq_reg : 16'HZZZZ;

endmodule