data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v
1: b'%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:15: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_1, net_2, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:16: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_1, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:17: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(gnd, y, net_2);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:18: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_2, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:19: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_2, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:20: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, vdd, net_2);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:32: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_3, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:33: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_4, ab);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:34: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_3, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:35: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(net_4, y, bb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:36: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(gnd, bb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:37: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, ab, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:38: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, net_7, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:39: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_7, vdd, ab);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:40: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, net_8, bb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:41: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_8, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:42: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(bb, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:43: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(ab, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:64: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, y, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:65: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:77: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_5, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:78: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_5, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:79: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:80: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:92: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, y, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:93: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:94: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, net_9, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:95: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_9, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:144: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_15, net_4, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:145: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(net_4, y, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:146: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(gnd, net_15, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:147: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:148: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(y, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPG/tester/PPGen_wordslice.v:149: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, vdd, a);\n          ^~~~~~\n%Error: Exiting due to 34 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module muddlib07__nand2_1x(a, b, y);
  input a;
  input b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_5;

  tranif1 nmos_0(net_5, y, b);
  tranif1 nmos_1(gnd, net_5, a);
  tranif0 pmos_0(y, vdd, b);
  tranif0 pmos_1(y, vdd, a);
endmodule
module muddlib07__nand2_1x(a, b, y);

  input a;
  input b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_5;

  tranif1 nmos_0(net_5, y, b);
  tranif1 nmos_1(gnd, net_5, a);
  tranif0 pmos_0(y, vdd, b);
  tranif0 pmos_1(y, vdd, a);
endmodule