data/full_repos/permissive/208113388/afu/afp/afp3_ram2048x032.v
data/verilator_xmls/f7c0cefa-e8f2-4bd9-91fc-dc0d50ce9faa.xml
module afp3_ram2048x032 (


    input              clk


  , input              wren
  , input       [10:0] wrad
  , input       [31:0] data


  , input              rden
  , input       [10:0] rdad
  , output      [31:0] q

  );

 (* ram_style = "block" *)

  reg    [31:0] ram [0:2047];
  reg    [31:0] q_int;

  always @(posedge clk)
   begin
     if ( wren == 1'b1 )
        ram [wrad] <= data[31:0];
    
     if ( rden == 1'b1)
       begin
          if (( rdad[10:0] != wrad[10:0] ) || ( wren == 1'b0 ))
             q_int[31:0] <= ram[rdad];
          else
             q_int[31:0] <= 32'bx; 
        end
   end

  assign q[31:0] =  q_int[31:0];

endmodule
module afp3_ram2048x032 (


    input              clk


  , input              wren
  , input       [10:0] wrad
  , input       [31:0] data


  , input              rden
  , input       [10:0] rdad
  , output      [31:0] q

  );


 (* ram_style = "block" *)

  reg    [31:0] ram [0:2047];
  reg    [31:0] q_int;

  always @(posedge clk)
   begin
     if ( wren == 1'b1 )
        ram [wrad] <= data[31:0];
    
     if ( rden == 1'b1)
       begin
          if (( rdad[10:0] != wrad[10:0] ) || ( wren == 1'b0 ))
             q_int[31:0] <= ram[rdad];
          else
             q_int[31:0] <= 32'bx; 
        end
   end

  assign q[31:0] =  q_int[31:0];

endmodule