data/full_repos/permissive/219219909/Radix-5/src/buf20.v
data/verilator_xmls/1e0fa10e-d37f-4835-a900-489687e7b293.xml
module buf20(
    input [31:0] a1_re,
    input [31:0] pc,
	 input [31:0] pd,
    input [31:0] a1_img,
    input [31:0] nc,
	 input [31:0] nd,
    output reg [31:0] a2_re,
    output reg [31:0] pbc,
	 output reg [31:0] pbd,
    output reg [31:0] a2_img,
    output reg [31:0] nbc,
	 output reg [31:0] nbd,
    input clk
    );
always @(posedge clk) begin
a2_re<=a1_re;
a2_img<=a1_img;
pbc<=pc;
nbc<=nc;
pbd<=pd;
nbd<=nd;
end

endmodule
module buf20(
    input [31:0] a1_re,
    input [31:0] pc,
	 input [31:0] pd,
    input [31:0] a1_img,
    input [31:0] nc,
	 input [31:0] nd,
    output reg [31:0] a2_re,
    output reg [31:0] pbc,
	 output reg [31:0] pbd,
    output reg [31:0] a2_img,
    output reg [31:0] nbc,
	 output reg [31:0] nbd,
    input clk
    );

always @(posedge clk) begin
a2_re<=a1_re;
a2_img<=a1_img;
pbc<=pc;
nbc<=nc;
pbd<=pd;
nbd<=nd;
end

endmodule