data/full_repos/permissive/119187354/DFF_1bit.v
data/verilator_xmls/014c5c18-035e-4b3f-828a-151b29fe7e58.xml
module DFF_1bit(
	input CLK,
	input IN,
	input RESET,
	output OUT
);
	
	reg Q;

	always @ (posedge CLK) begin
		if (RESET) begin
			Q <= 1'b0;
		end else begin
			Q <= IN;
		end
	end
	
	assign OUT = Q;
	
endmodule
module DFF_1bit(
	input CLK,
	input IN,
	input RESET,
	output OUT
);

	
	reg Q;

	always @ (posedge CLK) begin
		if (RESET) begin
			Q <= 1'b0;
		end else begin
			Q <= IN;
		end
	end
	
	assign OUT = Q;
	
endmodule