data/full_repos/permissive/143278/ivltests/pr1740476b.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1740476b.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #1 ;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1740476b.v:19: Operator NEQCASE expects 32 bits on the LHS, but LHS\'s ARRAYSEL generates 4 bits.\n                                                                          : ... In instance main\n  if (dst[idx] !== idx) begin\n               ^~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module buffer (input wire [3:0] in, output wire [3:0] out);

   assign out = in;

endmodule
module buffer (input wire [3:0] in, output wire [3:0] out);


   assign out = in;

endmodule