data/full_repos/permissive/189158922/verilog_src/b64_b32.v
 line:93: before: "*"
1: b'%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/b64_b32.v:327: Operator NEQ expects 2 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance top.fifo64\n  assign \\$4  = level != (* src = "nmigen/lib/fifo.py:145" *) 1\'h0;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/b64_b32.v:112: Operator NEQ expects 3 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance top.fifo32\n  assign \\$4  = level != (* src = "nmigen/lib/fifo.py:145" *) 1\'h0;\n                      ^~\n%Error: Exiting due to 2 warning(s)\n'
module fifo32(we, replace, re, rst, clk, writable, readable, dout, din);
  wire \$11 ;
  wire \$13 ;
  wire \$15 ;
  wire \$17 ;
  wire [2:0] \$19 ;
  wire \$2 ;
  wire [2:0] \$20 ;
  wire \$22 ;
  wire [2:0] \$24 ;
  wire [2:0] \$25 ;
  wire \$27 ;
  wire \$29 ;
  wire \$31 ;
  wire \$33 ;
  wire \$34 ;
  wire \$37 ;
  wire [3:0] \$39 ;
  wire \$4 ;
  wire [3:0] \$40 ;
  wire \$42 ;
  wire \$44 ;
  wire \$45 ;
  wire \$47 ;
  wire \$49 ;
  wire \$52 ;
  wire [3:0] \$54 ;
  wire [3:0] \$55 ;
  wire [2:0] \$6 ;
  wire [2:0] \$7 ;
  wire \$9 ;
  (* src = "nmigen/lib/fifo.py:156" *)
  reg [1:0] \$next\consume ;
  (* src = "nmigen/lib/fifo.py:69" *)
  reg [31:0] \$next\dout ;
  (* src = "nmigen/lib/fifo.py:138" *)
  reg [2:0] \$next\level ;
  (* src = "nmigen/lib/fifo.py:155" *)
  reg [1:0] \$next\produce ;
  (* src = "nmigen/hdl/mem.py:81" *)
  reg [1:0] \$next\rdport_storage_r_addr ;
  (* src = "nmigen/lib/fifo.py:70" *)
  reg \$next\readable ;
  (* src = "nmigen/lib/fifo.py:66" *)
  reg \$next\writable ;
  (* src = "nmigen/hdl/mem.py:146" *)
  reg [1:0] \$next\wrport_storage_w_addr ;
  (* src = "nmigen/hdl/mem.py:148" *)
  reg [31:0] \$next\wrport_storage_w_data ;
  (* src = "nmigen/hdl/mem.py:150" *)
  reg \$next\wrport_storage_w_en ;
  (* src = "nmigen/hdl/mem.py:160" *)
  input clk;
  (* init = 2'h0 *)
  (* src = "nmigen/lib/fifo.py:156" *)
  reg [1:0] consume = 2'h0;
  (* src = "nmigen/lib/fifo.py:65" *)
  input [31:0] din;
  (* src = "nmigen/lib/fifo.py:69" *)
  output [31:0] dout;
  (* init = 3'h0 *)
  (* src = "nmigen/lib/fifo.py:138" *)
  reg [2:0] level = 3'h0;
  (* init = 2'h0 *)
  (* src = "nmigen/lib/fifo.py:155" *)
  reg [1:0] produce = 2'h0;
  (* src = "nmigen/hdl/mem.py:81" *)
  wire [1:0] rdport_storage_r_addr;
  (* src = "nmigen/hdl/mem.py:83" *)
  wire [31:0] rdport_storage_r_data;
  (* src = "nmigen/lib/fifo.py:71" *)
  input re;
  (* src = "nmigen/lib/fifo.py:70" *)
  output readable;
  (* src = "nmigen/lib/fifo.py:139" *)
  input replace;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "nmigen/lib/fifo.py:67" *)
  input we;
  (* src = "nmigen/lib/fifo.py:66" *)
  output writable;
  (* src = "nmigen/hdl/mem.py:146" *)
  wire [1:0] wrport_storage_w_addr;
  (* src = "nmigen/hdl/mem.py:148" *)
  wire [31:0] wrport_storage_w_data;
  (* src = "nmigen/hdl/mem.py:150" *)
  wire wrport_storage_w_en;
  assign \$9  = writable | (* src = "nmigen/lib/fifo.py:161" *) replace;
  assign \$11  = we & (* src = "nmigen/lib/fifo.py:161" *) \$9 ;
  assign \$13  = writable & (* src = "nmigen/lib/fifo.py:149" *) we;
  assign \$15  = ~ (* src = "nmigen/lib/fifo.py:149" *) replace;
  assign \$17  = \$13  & (* src = "nmigen/lib/fifo.py:149" *) \$15 ;
  assign \$20  = produce + (* src = "nmigen/lib/fifo.py:93" *) 1'h1;
  assign \$22  = readable & (* src = "nmigen/lib/fifo.py:148" *) re;
  assign \$25  = consume + (* src = "nmigen/lib/fifo.py:93" *) 1'h1;
  assign \$27  = writable & (* src = "nmigen/lib/fifo.py:149" *) we;
  assign \$2  = level != (* src = "nmigen/lib/fifo.py:144" *) 3'h4;
  assign \$29  = ~ (* src = "nmigen/lib/fifo.py:149" *) replace;
  assign \$31  = \$27  & (* src = "nmigen/lib/fifo.py:149" *) \$29 ;
  assign \$34  = readable & (* src = "nmigen/lib/fifo.py:148" *) re;
  assign \$33  = ~ (* src = "nmigen/lib/fifo.py:177" *) \$34 ;
  assign \$37  = \$31  & (* src = "nmigen/lib/fifo.py:177" *) \$33 ;
  assign \$40  = level + (* src = "nmigen/lib/fifo.py:178" *) 1'h1;
  assign \$42  = readable & (* src = "nmigen/lib/fifo.py:148" *) re;
  assign \$45  = writable & (* src = "nmigen/lib/fifo.py:149" *) we;
  assign \$47  = ~ (* src = "nmigen/lib/fifo.py:149" *) replace;
  assign \$4  = level != (* src = "nmigen/lib/fifo.py:145" *) 1'h0;
  assign \$49  = \$45  & (* src = "nmigen/lib/fifo.py:149" *) \$47 ;
  assign \$44  = ~ (* src = "nmigen/lib/fifo.py:179" *) \$49 ;
  assign \$52  = \$42  & (* src = "nmigen/lib/fifo.py:179" *) \$44 ;
  assign \$55  = level - (* src = "nmigen/lib/fifo.py:180" *) 1'h1;
  assign \$7  = produce - (* src = "nmigen/lib/fifo.py:100" *) 1'h1;
  always @(posedge clk)
      level <= \$next\level ;
  always @(posedge clk)
      consume <= \$next\consume ;
  always @(posedge clk)
      produce <= \$next\produce ;
  reg [31:0] storage [3:0];
  initial begin
    storage[0] = 32'd0;
    storage[1] = 32'd0;
    storage[2] = 32'd0;
    storage[3] = 32'd0;
  end
  always @(posedge clk) begin
    if (\$next\wrport_storage_w_en ) storage[\$next\wrport_storage_w_addr ] <= \$next\wrport_storage_w_data ;
  end
  assign rdport_storage_r_data = storage[\$next\rdport_storage_r_addr ];
  always @* begin
    \$next\writable  = 1'h0;
    \$next\writable  = \$2 ;
  end
  always @* begin
    \$next\readable  = 1'h0;
    \$next\readable  = \$4 ;
  end
  always @* begin
    \$next\wrport_storage_w_addr  = 2'h0;
    \$next\wrport_storage_w_addr  = produce;
    casez (replace)
      1'h1:
          \$next\wrport_storage_w_addr  = \$6 [1:0];
    endcase
  end
  always @* begin
    \$next\wrport_storage_w_data  = 32'd0;
    \$next\wrport_storage_w_data  = din;
  end
  always @* begin
    \$next\wrport_storage_w_en  = 1'h0;
    \$next\wrport_storage_w_en  = \$11 ;
  end
  always @* begin
    \$next\produce  = produce;
    casez (\$17 )
      1'h1:
          \$next\produce  = \$19 [1:0];
    endcase
    casez (rst)
      1'h1:
          \$next\produce  = 2'h0;
    endcase
  end
  always @* begin
    \$next\rdport_storage_r_addr  = 2'h0;
    \$next\rdport_storage_r_addr  = consume;
  end
  always @* begin
    \$next\dout  = 32'd0;
    \$next\dout  = rdport_storage_r_data;
  end
  always @* begin
    \$next\consume  = consume;
    casez (\$22 )
      1'h1:
          \$next\consume  = \$24 [1:0];
    endcase
    casez (rst)
      1'h1:
          \$next\consume  = 2'h0;
    endcase
  end
  always @* begin
    \$next\level  = level;
    casez (\$37 )
      1'h1:
          \$next\level  = \$39 [2:0];
    endcase
    casez (\$52 )
      1'h1:
          \$next\level  = \$54 [2:0];
    endcase
    casez (rst)
      1'h1:
          \$next\level  = 3'h0;
    endcase
  end
  assign \$6  = \$7 ;
  assign \$19  = \$20 ;
  assign \$24  = \$25 ;
  assign \$39  = \$40 ;
  assign \$54  = \$55 ;
  assign dout = \$next\dout ;
  assign rdport_storage_r_addr = \$next\rdport_storage_r_addr ;
  assign wrport_storage_w_en = \$next\wrport_storage_w_en ;
  assign wrport_storage_w_data = \$next\wrport_storage_w_data ;
  assign wrport_storage_w_addr = \$next\wrport_storage_w_addr ;
  assign readable = \$next\readable ;
  assign writable = \$next\writable ;
endmodule
module fifo32(we, replace, re, rst, clk, writable, readable, dout, din);

  wire \$11 ;
  wire \$13 ;
  wire \$15 ;
  wire \$17 ;
  wire [2:0] \$19 ;
  wire \$2 ;
  wire [2:0] \$20 ;
  wire \$22 ;
  wire [2:0] \$24 ;
  wire [2:0] \$25 ;
  wire \$27 ;
  wire \$29 ;
  wire \$31 ;
  wire \$33 ;
  wire \$34 ;
  wire \$37 ;
  wire [3:0] \$39 ;
  wire \$4 ;
  wire [3:0] \$40 ;
  wire \$42 ;
  wire \$44 ;
  wire \$45 ;
  wire \$47 ;
  wire \$49 ;
  wire \$52 ;
  wire [3:0] \$54 ;
  wire [3:0] \$55 ;
  wire [2:0] \$6 ;
  wire [2:0] \$7 ;
  wire \$9 ;
  (* src = "nmigen/lib/fifo.py:156" *)
  reg [1:0] \$next\consume ;
  (* src = "nmigen/lib/fifo.py:69" *)
  reg [31:0] \$next\dout ;
  (* src = "nmigen/lib/fifo.py:138" *)
  reg [2:0] \$next\level ;
  (* src = "nmigen/lib/fifo.py:155" *)
  reg [1:0] \$next\produce ;
  (* src = "nmigen/hdl/mem.py:81" *)
  reg [1:0] \$next\rdport_storage_r_addr ;
  (* src = "nmigen/lib/fifo.py:70" *)
  reg \$next\readable ;
  (* src = "nmigen/lib/fifo.py:66" *)
  reg \$next\writable ;
  (* src = "nmigen/hdl/mem.py:146" *)
  reg [1:0] \$next\wrport_storage_w_addr ;
  (* src = "nmigen/hdl/mem.py:148" *)
  reg [31:0] \$next\wrport_storage_w_data ;
  (* src = "nmigen/hdl/mem.py:150" *)
  reg \$next\wrport_storage_w_en ;
  (* src = "nmigen/hdl/mem.py:160" *)
  input clk;
  (* init = 2'h0 *)
  (* src = "nmigen/lib/fifo.py:156" *)
  reg [1:0] consume = 2'h0;
  (* src = "nmigen/lib/fifo.py:65" *)
  input [31:0] din;
  (* src = "nmigen/lib/fifo.py:69" *)
  output [31:0] dout;
  (* init = 3'h0 *)
  (* src = "nmigen/lib/fifo.py:138" *)
  reg [2:0] level = 3'h0;
  (* init = 2'h0 *)
  (* src = "nmigen/lib/fifo.py:155" *)
  reg [1:0] produce = 2'h0;
  (* src = "nmigen/hdl/mem.py:81" *)
  wire [1:0] rdport_storage_r_addr;
  (* src = "nmigen/hdl/mem.py:83" *)
  wire [31:0] rdport_storage_r_data;
  (* src = "nmigen/lib/fifo.py:71" *)
  input re;
  (* src = "nmigen/lib/fifo.py:70" *)
  output readable;
  (* src = "nmigen/lib/fifo.py:139" *)
  input replace;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "nmigen/lib/fifo.py:67" *)
  input we;
  (* src = "nmigen/lib/fifo.py:66" *)
  output writable;
  (* src = "nmigen/hdl/mem.py:146" *)
  wire [1:0] wrport_storage_w_addr;
  (* src = "nmigen/hdl/mem.py:148" *)
  wire [31:0] wrport_storage_w_data;
  (* src = "nmigen/hdl/mem.py:150" *)
  wire wrport_storage_w_en;
  assign \$9  = writable | (* src = "nmigen/lib/fifo.py:161" *) replace;
  assign \$11  = we & (* src = "nmigen/lib/fifo.py:161" *) \$9 ;
  assign \$13  = writable & (* src = "nmigen/lib/fifo.py:149" *) we;
  assign \$15  = ~ (* src = "nmigen/lib/fifo.py:149" *) replace;
  assign \$17  = \$13  & (* src = "nmigen/lib/fifo.py:149" *) \$15 ;
  assign \$20  = produce + (* src = "nmigen/lib/fifo.py:93" *) 1'h1;
  assign \$22  = readable & (* src = "nmigen/lib/fifo.py:148" *) re;
  assign \$25  = consume + (* src = "nmigen/lib/fifo.py:93" *) 1'h1;
  assign \$27  = writable & (* src = "nmigen/lib/fifo.py:149" *) we;
  assign \$2  = level != (* src = "nmigen/lib/fifo.py:144" *) 3'h4;
  assign \$29  = ~ (* src = "nmigen/lib/fifo.py:149" *) replace;
  assign \$31  = \$27  & (* src = "nmigen/lib/fifo.py:149" *) \$29 ;
  assign \$34  = readable & (* src = "nmigen/lib/fifo.py:148" *) re;
  assign \$33  = ~ (* src = "nmigen/lib/fifo.py:177" *) \$34 ;
  assign \$37  = \$31  & (* src = "nmigen/lib/fifo.py:177" *) \$33 ;
  assign \$40  = level + (* src = "nmigen/lib/fifo.py:178" *) 1'h1;
  assign \$42  = readable & (* src = "nmigen/lib/fifo.py:148" *) re;
  assign \$45  = writable & (* src = "nmigen/lib/fifo.py:149" *) we;
  assign \$47  = ~ (* src = "nmigen/lib/fifo.py:149" *) replace;
  assign \$4  = level != (* src = "nmigen/lib/fifo.py:145" *) 1'h0;
  assign \$49  = \$45  & (* src = "nmigen/lib/fifo.py:149" *) \$47 ;
  assign \$44  = ~ (* src = "nmigen/lib/fifo.py:179" *) \$49 ;
  assign \$52  = \$42  & (* src = "nmigen/lib/fifo.py:179" *) \$44 ;
  assign \$55  = level - (* src = "nmigen/lib/fifo.py:180" *) 1'h1;
  assign \$7  = produce - (* src = "nmigen/lib/fifo.py:100" *) 1'h1;
  always @(posedge clk)
      level <= \$next\level ;
  always @(posedge clk)
      consume <= \$next\consume ;
  always @(posedge clk)
      produce <= \$next\produce ;
  reg [31:0] storage [3:0];
  initial begin
    storage[0] = 32'd0;
    storage[1] = 32'd0;
    storage[2] = 32'd0;
    storage[3] = 32'd0;
  end
  always @(posedge clk) begin
    if (\$next\wrport_storage_w_en ) storage[\$next\wrport_storage_w_addr ] <= \$next\wrport_storage_w_data ;
  end
  assign rdport_storage_r_data = storage[\$next\rdport_storage_r_addr ];
  always @* begin
    \$next\writable  = 1'h0;
    \$next\writable  = \$2 ;
  end
  always @* begin
    \$next\readable  = 1'h0;
    \$next\readable  = \$4 ;
  end
  always @* begin
    \$next\wrport_storage_w_addr  = 2'h0;
    \$next\wrport_storage_w_addr  = produce;
    casez (replace)
      1'h1:
          \$next\wrport_storage_w_addr  = \$6 [1:0];
    endcase
  end
  always @* begin
    \$next\wrport_storage_w_data  = 32'd0;
    \$next\wrport_storage_w_data  = din;
  end
  always @* begin
    \$next\wrport_storage_w_en  = 1'h0;
    \$next\wrport_storage_w_en  = \$11 ;
  end
  always @* begin
    \$next\produce  = produce;
    casez (\$17 )
      1'h1:
          \$next\produce  = \$19 [1:0];
    endcase
    casez (rst)
      1'h1:
          \$next\produce  = 2'h0;
    endcase
  end
  always @* begin
    \$next\rdport_storage_r_addr  = 2'h0;
    \$next\rdport_storage_r_addr  = consume;
  end
  always @* begin
    \$next\dout  = 32'd0;
    \$next\dout  = rdport_storage_r_data;
  end
  always @* begin
    \$next\consume  = consume;
    casez (\$22 )
      1'h1:
          \$next\consume  = \$24 [1:0];
    endcase
    casez (rst)
      1'h1:
          \$next\consume  = 2'h0;
    endcase
  end
  always @* begin
    \$next\level  = level;
    casez (\$37 )
      1'h1:
          \$next\level  = \$39 [2:0];
    endcase
    casez (\$52 )
      1'h1:
          \$next\level  = \$54 [2:0];
    endcase
    casez (rst)
      1'h1:
          \$next\level  = 3'h0;
    endcase
  end
  assign \$6  = \$7 ;
  assign \$19  = \$20 ;
  assign \$24  = \$25 ;
  assign \$39  = \$40 ;
  assign \$54  = \$55 ;
  assign dout = \$next\dout ;
  assign rdport_storage_r_addr = \$next\rdport_storage_r_addr ;
  assign wrport_storage_w_en = \$next\wrport_storage_w_en ;
  assign wrport_storage_w_data = \$next\wrport_storage_w_data ;
  assign wrport_storage_w_addr = \$next\wrport_storage_w_addr ;
  assign readable = \$next\readable ;
  assign writable = \$next\writable ;
endmodule