data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_2_lg_credit_to_token_decimation_p_4/top.v
 line:40: before: "t"
1: b'%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_2_lg_credit_to_token_decimation_p_4/top.v:61: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                          : ... In instance top.wrapper.bapg.ptr_sync.sync_p_z_blss\n                      (N1)? iclk_data_i : 1\'b0;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_2_lg_credit_to_token_decimation_p_4/top.v:154: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                           : ... In instance top.wrapper.bapg\n                        (N1)? w_ptr_gray_r_o : 1\'b0;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_2_lg_credit_to_token_decimation_p_4/top.v:214: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'r_dec_credit_i\' generates 1 bits.\n                                                                                                                                                                           : ... In instance top.wrapper\n  assign { N8, N7, N6, N5, N4, N3 } = r_counter_r + r_dec_credit_i;\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_2_lg_credit_to_token_decimation_p_4/top.v:216: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                           : ... In instance top.wrapper\n                                           (N1)? { N8, N7, N6, N5, N4, N3 } : 1\'b0;\n                                               ^\n%Error: Exiting due to 4 warning(s)\n'
module bsg_async_credit_counter
(
  w_clk_i,
  w_inc_token_i,
  w_reset_i,
  r_clk_i,
  r_reset_i,
  r_dec_credit_i,
  r_infinite_credits_i,
  r_credits_avail_o
);

  input w_clk_i;
  input w_inc_token_i;
  input w_reset_i;
  input r_clk_i;
  input r_reset_i;
  input r_dec_credit_i;
  input r_infinite_credits_i;
  output r_credits_avail_o;
  wire r_credits_avail_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,
  r_counter_r_lo_bits_nonzero,N15,N16,N17,N18,SYNOPSYS_UNCONNECTED_1,SYNOPSYS_UNCONNECTED_2;
  wire [1:0] w_counter_gray_r,w_counter_gray_r_rsync;
  wire [0:0] r_counter_r_hi_bits_gray;
  reg [5:0] r_counter_r;

  bsg_async_ptr_gray_lg_size_p2_use_negedge_for_launch_p0_use_async_reset_p0
  bapg
  (
    .w_clk_i(w_clk_i),
    .w_reset_i(w_reset_i),
    .w_inc_i(w_inc_token_i),
    .r_clk_i(r_clk_i),
    .w_ptr_binary_r_o({ SYNOPSYS_UNCONNECTED_1, SYNOPSYS_UNCONNECTED_2 }),
    .w_ptr_gray_r_o(w_counter_gray_r),
    .w_ptr_gray_r_rsync_o(w_counter_gray_r_rsync)
  );

  assign N15 = { r_counter_r[5:5], r_counter_r_hi_bits_gray[0:0] } != w_counter_gray_r_rsync;
  assign { N8, N7, N6, N5, N4, N3 } = r_counter_r + r_dec_credit_i;
  assign { N14, N13, N12, N11, N10, N9 } = (N0)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 
                                           (N1)? { N8, N7, N6, N5, N4, N3 } : 1'b0;
  assign N0 = r_reset_i;
  assign N1 = N2;
  assign N2 = ~r_reset_i;
  assign r_counter_r_lo_bits_nonzero = N17 | r_counter_r[0];
  assign N17 = N16 | r_counter_r[1];
  assign N16 = r_counter_r[3] | r_counter_r[2];
  assign r_counter_r_hi_bits_gray[0] = r_counter_r[5] ^ r_counter_r[4];
  assign r_credits_avail_o = N18 | N15;
  assign N18 = r_infinite_credits_i | r_counter_r_lo_bits_nonzero;

  always @(posedge r_clk_i) begin
    if(1'b1) begin
      { r_counter_r[5:0] } <= { N14, N13, N12, N11, N10, N9 };
    end 
  end


endmodule
module bsg_async_credit_counter
(
  w_clk_i,
  w_inc_token_i,
  w_reset_i,
  r_clk_i,
  r_reset_i,
  r_dec_credit_i,
  r_infinite_credits_i,
  r_credits_avail_o
);


  input w_clk_i;
  input w_inc_token_i;
  input w_reset_i;
  input r_clk_i;
  input r_reset_i;
  input r_dec_credit_i;
  input r_infinite_credits_i;
  output r_credits_avail_o;
  wire r_credits_avail_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,
  r_counter_r_lo_bits_nonzero,N15,N16,N17,N18,SYNOPSYS_UNCONNECTED_1,SYNOPSYS_UNCONNECTED_2;
  wire [1:0] w_counter_gray_r,w_counter_gray_r_rsync;
  wire [0:0] r_counter_r_hi_bits_gray;
  reg [5:0] r_counter_r;

  bsg_async_ptr_gray_lg_size_p2_use_negedge_for_launch_p0_use_async_reset_p0
  bapg
  (
    .w_clk_i(w_clk_i),
    .w_reset_i(w_reset_i),
    .w_inc_i(w_inc_token_i),
    .r_clk_i(r_clk_i),
    .w_ptr_binary_r_o({ SYNOPSYS_UNCONNECTED_1, SYNOPSYS_UNCONNECTED_2 }),
    .w_ptr_gray_r_o(w_counter_gray_r),
    .w_ptr_gray_r_rsync_o(w_counter_gray_r_rsync)
  );

  assign N15 = { r_counter_r[5:5], r_counter_r_hi_bits_gray[0:0] } != w_counter_gray_r_rsync;
  assign { N8, N7, N6, N5, N4, N3 } = r_counter_r + r_dec_credit_i;
  assign { N14, N13, N12, N11, N10, N9 } = (N0)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 
                                           (N1)? { N8, N7, N6, N5, N4, N3 } : 1'b0;
  assign N0 = r_reset_i;
  assign N1 = N2;
  assign N2 = ~r_reset_i;
  assign r_counter_r_lo_bits_nonzero = N17 | r_counter_r[0];
  assign N17 = N16 | r_counter_r[1];
  assign N16 = r_counter_r[3] | r_counter_r[2];
  assign r_counter_r_hi_bits_gray[0] = r_counter_r[5] ^ r_counter_r[4];
  assign r_credits_avail_o = N18 | N15;
  assign N18 = r_infinite_credits_i | r_counter_r_lo_bits_nonzero;

  always @(posedge r_clk_i) begin
    if(1'b1) begin
      { r_counter_r[5:0] } <= { N14, N13, N12, N11, N10, N9 };
    end 
  end


endmodule