data/full_repos/permissive/101423580/v/P2S_IO.v
data/verilator_xmls/bea80fb3-6f12-45ca-a4e1-6ecfff5c0036.xml
module  		  P2S(input wire clk,
						input wire rst,
						input wire Serial,
						input wire[DATA_BITS-1:0] P_Data,
						output reg  s_clk,
						output wire s_clrn,
						output wire sout,
						output reg  EN
						);
parameter
	DATA_BITS = 64,
	DATA_COUNT_BITS = 6; 	
	
endmodule
module  		  P2S(input wire clk,
						input wire rst,
						input wire Serial,
						input wire[DATA_BITS-1:0] P_Data,
						output reg  s_clk,
						output wire s_clrn,
						output wire sout,
						output reg  EN
						);

parameter
	DATA_BITS = 64,
	DATA_COUNT_BITS = 6; 	
	
endmodule