data/full_repos/permissive/195227969/work/code/m_ram.v
1: b"%Error: data/full_repos/permissive/195227969/work/code/m_ram.v:120: Cannot find file containing module: 'm_ram_a16'\n         m_ram_a16 #(.HIGHLEVEL(HIGHLEVEL))  \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/195227969/work/code,data/full_repos/permissive/195227969/m_ram_a16\n             data/full_repos/permissive/195227969/work/code,data/full_repos/permissive/195227969/m_ram_a16.v\n             data/full_repos/permissive/195227969/work/code,data/full_repos/permissive/195227969/m_ram_a16.sv\n             m_ram_a16\n             m_ram_a16.v\n             m_ram_a16.sv\n             obj_dir/m_ram_a16\n             obj_dir/m_ram_a16.v\n             obj_dir/m_ram_a16.sv\n%Error: Exiting due to 1 error(s)\n"
module m_ram
  # ( parameter HIGHLEVEL = 0, SRAMADRWIDTH = 16 )
   (
    input         CLK_I,
    input [31:0]  DAT_I,
    input [31:0]  ADR_I,
    input         STB_I,
    input         WE_I,
    input [3:0]   SEL_I,

    input [3:0]   bmask,

    output [31:0] DAT_O,
    output        ACK_O,
    output        m_ram_killwarnings
    );


   
   generate
      if ( SRAMADRWIDTH == 0 ) begin

         assign DAT_O = 32'h0;
         assign ACK_O = 1'b0;
         assign m_ram_killwarnings = CLK_I & STB_I & WE_I & &ADR_I & &DAT_I & &SEL_I;
      end else if ( SRAMADRWIDTH == 17 ) begin
         wire            m_ram_a17_killwarnings;

         m_ram_a17 #(.HIGHLEVEL(HIGHLEVEL))
         m_ram_inst
           (

            .DAT_O                      (DAT_O[31:0]),
            .ACK_O                      (ACK_O),
            .m_ram_a17_killwarnings     (m_ram_a17_killwarnings),

            .CLK_I                      (CLK_I),
            .DAT_I                      (DAT_I[31:0]),
            .ADR_I                      (ADR_I[16:0]),
            .STB_I                      (STB_I),
            .WE_I                       (WE_I),
            .SEL_I                      (SEL_I[3:0]));

         assign m_ram_killwarnings = &bmask & CLK_I & STB_I & WE_I & &ADR_I & &DAT_I & &SEL_I | m_ram_a17_killwarnings;

      end else if ( SRAMADRWIDTH == 16 ) begin

         wire            m_ram_a16_killwarnings;
         m_ram_a16 #(.HIGHLEVEL(HIGHLEVEL))
         m_ram_inst
           (

            .DAT_O                      (DAT_O[31:0]),
            .ACK_O                      (ACK_O),
            .m_ram_a16_killwarnings     (m_ram_a16_killwarnings),

            .CLK_I                      (CLK_I),
            .DAT_I                      (DAT_I[31:0]),
            .ADR_I                      (ADR_I[15:0]),
            .STB_I                      (STB_I),
            .WE_I                       (WE_I),
            .SEL_I                      (SEL_I[3:0]));
         assign m_ram_killwarnings = &bmask & CLK_I & STB_I & WE_I & &ADR_I & &DAT_I & &SEL_I | m_ram_a16_killwarnings;
         
      end else if ( SRAMADRWIDTH >= 10 && SRAMADRWIDTH <= 13 ) begin

         wire we;
         if ( HIGHLEVEL ) begin
            assign we  = STB_I & WE_I;
            reg  readack;
            wire cmb_readack = ~readack & STB_I & ~WE_I;
            always @(posedge CLK_I)
              readack <= cmb_readack;
            assign ACK_O = readack | we;
         end else begin
            wire readack;
            wire cmb_readack;
            SB_LUT4 #(.LUT_INIT(16'h8888)) we_l(.O(we), .I3(1'b0), .I2(1'b0), .I1(STB_I), .I0(WE_I));
            SB_LUT4 #(.LUT_INIT(16'h0404)) readack_l(.O(cmb_readack), .I3(1'b0), .I2(readack), .I1(STB_I), .I0(WE_I)); 
            SB_DFF readack_r(.Q(readack), .C(CLK_I), .D(cmb_readack));
            SB_LUT4 #(.LUT_INIT(16'hf8f8)) ACK_O_l(.O(ACK_O), .I3(1'b0), .I2(readack), .I1(STB_I), .I0(WE_I)); 
         end

         
         wire       next_readvalue_unknown;
         m_ebr #(.EBRAWIDTH(SRAMADRWIDTH))
         inst_ram (
                   .Rai                 (ADR_I[SRAMADRWIDTH-1:2]),
                   .Wai                 (ADR_I[SRAMADRWIDTH-1:2]),
                   .iwe                 (we),
                   .B                   (DAT_I[31:0]),
                   .clk                 (CLK_I),


                   .DAT_O               (DAT_O[31:0]),
                   .next_readvalue_unknown(next_readvalue_unknown),

                   .bmask               (bmask[3:0]));

         assign m_ram_killwarnings = &ADR_I | next_readvalue_unknown;
         
      end
`ifndef verilator
      else begin
         unsupported_sramwidth inst_can_not_have_this();
      end
`endif
   endgenerate
endmodule
module m_ram
  # ( parameter HIGHLEVEL = 0, SRAMADRWIDTH = 16 )
   (
    input         CLK_I,
    input [31:0]  DAT_I,
    input [31:0]  ADR_I,
    input         STB_I,
    input         WE_I,
    input [3:0]   SEL_I,

    input [3:0]   bmask,

    output [31:0] DAT_O,
    output        ACK_O,
    output        m_ram_killwarnings
    );



   
   generate
      if ( SRAMADRWIDTH == 0 ) begin

         assign DAT_O = 32'h0;
         assign ACK_O = 1'b0;
         assign m_ram_killwarnings = CLK_I & STB_I & WE_I & &ADR_I & &DAT_I & &SEL_I;
      end else if ( SRAMADRWIDTH == 17 ) begin
         wire            m_ram_a17_killwarnings;

         m_ram_a17 #(.HIGHLEVEL(HIGHLEVEL))
         m_ram_inst
           (

            .DAT_O                      (DAT_O[31:0]),
            .ACK_O                      (ACK_O),
            .m_ram_a17_killwarnings     (m_ram_a17_killwarnings),

            .CLK_I                      (CLK_I),
            .DAT_I                      (DAT_I[31:0]),
            .ADR_I                      (ADR_I[16:0]),
            .STB_I                      (STB_I),
            .WE_I                       (WE_I),
            .SEL_I                      (SEL_I[3:0]));

         assign m_ram_killwarnings = &bmask & CLK_I & STB_I & WE_I & &ADR_I & &DAT_I & &SEL_I | m_ram_a17_killwarnings;

      end else if ( SRAMADRWIDTH == 16 ) begin

         wire            m_ram_a16_killwarnings;
         m_ram_a16 #(.HIGHLEVEL(HIGHLEVEL))
         m_ram_inst
           (

            .DAT_O                      (DAT_O[31:0]),
            .ACK_O                      (ACK_O),
            .m_ram_a16_killwarnings     (m_ram_a16_killwarnings),

            .CLK_I                      (CLK_I),
            .DAT_I                      (DAT_I[31:0]),
            .ADR_I                      (ADR_I[15:0]),
            .STB_I                      (STB_I),
            .WE_I                       (WE_I),
            .SEL_I                      (SEL_I[3:0]));
         assign m_ram_killwarnings = &bmask & CLK_I & STB_I & WE_I & &ADR_I & &DAT_I & &SEL_I | m_ram_a16_killwarnings;
         
      end else if ( SRAMADRWIDTH >= 10 && SRAMADRWIDTH <= 13 ) begin

         wire we;
         if ( HIGHLEVEL ) begin
            assign we  = STB_I & WE_I;
            reg  readack;
            wire cmb_readack = ~readack & STB_I & ~WE_I;
            always @(posedge CLK_I)
              readack <= cmb_readack;
            assign ACK_O = readack | we;
         end else begin
            wire readack;
            wire cmb_readack;
            SB_LUT4 #(.LUT_INIT(16'h8888)) we_l(.O(we), .I3(1'b0), .I2(1'b0), .I1(STB_I), .I0(WE_I));
            SB_LUT4 #(.LUT_INIT(16'h0404)) readack_l(.O(cmb_readack), .I3(1'b0), .I2(readack), .I1(STB_I), .I0(WE_I)); 
            SB_DFF readack_r(.Q(readack), .C(CLK_I), .D(cmb_readack));
            SB_LUT4 #(.LUT_INIT(16'hf8f8)) ACK_O_l(.O(ACK_O), .I3(1'b0), .I2(readack), .I1(STB_I), .I0(WE_I)); 
         end

         
         wire       next_readvalue_unknown;
         m_ebr #(.EBRAWIDTH(SRAMADRWIDTH))
         inst_ram (
                   .Rai                 (ADR_I[SRAMADRWIDTH-1:2]),
                   .Wai                 (ADR_I[SRAMADRWIDTH-1:2]),
                   .iwe                 (we),
                   .B                   (DAT_I[31:0]),
                   .clk                 (CLK_I),


                   .DAT_O               (DAT_O[31:0]),
                   .next_readvalue_unknown(next_readvalue_unknown),

                   .bmask               (bmask[3:0]));

         assign m_ram_killwarnings = &ADR_I | next_readvalue_unknown;
         
      end
`ifndef verilator
      else begin
         unsupported_sramwidth inst_can_not_have_this();
      end
`endif
   endgenerate
endmodule