data/full_repos/permissive/200314387/verilog/ram/test.v
 line:41: before: ","
1: b'%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:5: Cannot find include file: ram.v\n`include "ram.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/ram,data/full_repos/permissive/200314387/ram.v\n             data/full_repos/permissive/200314387/verilog/ram,data/full_repos/permissive/200314387/ram.v.v\n             data/full_repos/permissive/200314387/verilog/ram,data/full_repos/permissive/200314387/ram.v.sv\n             ram.v\n             ram.v.v\n             ram.v.sv\n             obj_dir/ram.v\n             obj_dir/ram.v.v\n             obj_dir/ram.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:6: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:18: Cannot find include file: ../lib/display_snippet.sv\n `include "../lib/display_snippet.sv" \n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:28: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dumpfile.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:29: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, test);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:31: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("TEST: INITIAL STATE");\n    ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:31: syntax error, unexpected \';\'\n    `DISPLAY("TEST: INITIAL STATE");\n                                   ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:34: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("TEST: write 1 at 1");\n    ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:34: syntax error, unexpected \';\'\n    `DISPLAY("TEST: write 1 at 1");\n                                  ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:42: Define or directive not defined: \'`Equals\'\n    `Equals(RAM.Mem[1],1);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:42: syntax error, unexpected \',\'\n    `Equals(RAM.Mem[1],1);\n                      ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:44: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("TEST: write 2 at 2");\n    ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:44: syntax error, unexpected \';\'\n    `DISPLAY("TEST: write 2 at 2");\n                                  ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:52: Define or directive not defined: \'`Equals\'\n    `Equals(RAM.Mem[2],2);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:52: syntax error, unexpected \',\'\n    `Equals(RAM.Mem[2],2);\n                      ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:54: Define or directive not defined: \'`DISPLAY\'\n   `DISPLAY("TEST: READ at 2");\n   ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:54: syntax error, unexpected \';\'\n   `DISPLAY("TEST: READ at 2");\n                              ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:59: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'b00000010);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:59: syntax error, unexpected \',\'\n    `Equals(D, 8\'b00000010);\n             ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:61: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("TEST: NO READ OR WRITE");\n    ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:61: syntax error, unexpected \';\'\n    `DISPLAY("TEST: NO READ OR WRITE");\n                                      ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:65: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'bzzzzzzzz);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:65: syntax error, unexpected \',\'\n    `Equals(D, 8\'bzzzzzzzz);\n             ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:67: Define or directive not defined: \'`DISPLAY\'\n   `DISPLAY("TEST: READ at 2");\n   ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:67: syntax error, unexpected \';\'\n   `DISPLAY("TEST: READ at 2");\n                              ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:72: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'b00000010);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:72: syntax error, unexpected \',\'\n    `Equals(D, 8\'b00000010);\n             ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:74: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("TEST: Slide READ at 1");\n    ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:74: syntax error, unexpected \';\'\n    `DISPLAY("TEST: Slide READ at 1");\n                                     ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:78: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'b00000001);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:78: syntax error, unexpected \',\'\n    `Equals(D, 8\'b00000001);\n             ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:80: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("TEST: Slide READ at 0 is not defined");\n    ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:80: syntax error, unexpected \';\'\n    `DISPLAY("TEST: Slide READ at 0 is not defined");\n                                                    ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:84: Define or directive not defined: \'`Equals\'\n    `Equals(D, RAM.UNDEF);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:84: syntax error, unexpected \',\'\n    `Equals(D, RAM.UNDEF);\n             ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:86: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("TEST: READ at 3");\n    ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:86: syntax error, unexpected \';\'\n    `DISPLAY("TEST: READ at 3");\n                               ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:92: Define or directive not defined: \'`Equals\'\n    `Equals(D, RAM.UNDEF);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:92: syntax error, unexpected \',\'\n    `Equals(D, RAM.UNDEF);\n             ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:94: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("TEST: WRITE AT 3 with _OE override");\n    ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:94: syntax error, unexpected \';\'\n    `DISPLAY("TEST: WRITE AT 3 with _OE override");\n                                                  ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:101: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("TEST: READ BACK AT 3 and expect bus conflict");\n    ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:101: syntax error, unexpected \';\'\n    `DISPLAY("TEST: READ BACK AT 3 and expect bus conflict");\n                                                            ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:106: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'bxxxxxx11);  \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:106: syntax error, unexpected \',\'\n    `Equals(D, 8\'bxxxxxx11);  \n             ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:108: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("TEST: READ BACK AT 3");\n    ^~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:108: syntax error, unexpected \';\'\n    `DISPLAY("TEST: READ BACK AT 3");\n                                    ^\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:113: Define or directive not defined: \'`Equals\'\n    `Equals(D, 8\'b11);  \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/ram/test.v:113: syntax error, unexpected \',\'\n    `Equals(D, 8\'b11);  \n             ^\n%Error: Exiting due to 49 error(s)\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module test();

 logic _OE, _WE;
 logic [7:0] A;
 tri [7:0] D;
 
 logic [7:0] Vd;
 assign D=Vd;

 `include "../lib/display_snippet.sv"

 localparam PD=56;

  ram #(.AWIDTH(8), .LOG(1)) RAM(._OE, ._WE, .A, .D);

  always @*
      $display("%9t", $time, " MON : _OE=%1b, _WE=%1b, A=%8b, D=%8b - setup write 1 @ 1",_OE, _WE, A, D);

 initial begin
    $dumpfile("dumpfile.vcd");
    $dumpvars(0, test);

    `DISPLAY("TEST: INITIAL STATE");
    #PD

    `DISPLAY("TEST: write 1 at 1");
    A=8'b00000001;
    Vd=8'b00000001;
    _OE=1'b1;
    _WE=1'b0;
    #PD
    _WE=1'b1;
    #PD
    `Equals(RAM.Mem[1],1);
 
    `DISPLAY("TEST: write 2 at 2");
    A=8'b00000010;
    Vd=8'b00000010;
    _OE=1'b1;
    _WE=1'b0;
    #PD
    _WE=1'b1;
    #PD
    `Equals(RAM.Mem[2],2);

   `DISPLAY("TEST: READ at 2");
    A=8'b00000010;
    Vd=8'bz;
    _OE=1'b0;
    #PD
    `Equals(D, 8'b00000010);
 
    `DISPLAY("TEST: NO READ OR WRITE");
    Vd=8'bzzzzzzzz;
    _OE=1'b1;
    #PD
    `Equals(D, 8'bzzzzzzzz);

   `DISPLAY("TEST: READ at 2");
    Vd=8'bz;
    A=8'b00000010;
    _OE=1'b0;
    #PD
    `Equals(D, 8'b00000010);
 
    `DISPLAY("TEST: Slide READ at 1");
    Vd=8'bz;
    A=8'b00000001;
    #PD
    `Equals(D, 8'b00000001);
 
    `DISPLAY("TEST: Slide READ at 0 is not defined");
    Vd=8'bz;
    A=8'b00000000;
    #PD
    `Equals(D, RAM.UNDEF);

    `DISPLAY("TEST: READ at 3");
    Vd=8'bz;
    _WE=1'b1;
    _OE=1'b0;
    A=8'b00000011;
    #PD
    `Equals(D, RAM.UNDEF);
 
    `DISPLAY("TEST: WRITE AT 3 with _OE override");
    Vd=8'b00000011;
    A=8'b00000011;
    _WE=1'b0;
    _OE=1'b0;
    #PD

    `DISPLAY("TEST: READ BACK AT 3 and expect bus conflict");
    Vd=8'b11111111;
    _WE=1'b1;
    _OE=1'b0;
    #PD
    `Equals(D, 8'bxxxxxx11);
 
    `DISPLAY("TEST: READ BACK AT 3");
    Vd=8'bz;
    _WE=1'b1;
    _OE=1'b0;
    #PD
    `Equals(D, 8'b11);
 
 
 end

endmodule
module test();


 logic _OE, _WE;
 logic [7:0] A;
 tri [7:0] D;
 
 logic [7:0] Vd;
 assign D=Vd;

 `include "../lib/display_snippet.sv"

 localparam PD=56;

  ram #(.AWIDTH(8), .LOG(1)) RAM(._OE, ._WE, .A, .D);

  always @*
      $display("%9t", $time, " MON : _OE=%1b, _WE=%1b, A=%8b, D=%8b - setup write 1 @ 1",_OE, _WE, A, D);

 initial begin
    $dumpfile("dumpfile.vcd");
    $dumpvars(0, test);

    `DISPLAY("TEST: INITIAL STATE");
    #PD

    `DISPLAY("TEST: write 1 at 1");
    A=8'b00000001;
    Vd=8'b00000001;
    _OE=1'b1;
    _WE=1'b0;
    #PD
    _WE=1'b1;
    #PD
    `Equals(RAM.Mem[1],1);
 
    `DISPLAY("TEST: write 2 at 2");
    A=8'b00000010;
    Vd=8'b00000010;
    _OE=1'b1;
    _WE=1'b0;
    #PD
    _WE=1'b1;
    #PD
    `Equals(RAM.Mem[2],2);

   `DISPLAY("TEST: READ at 2");
    A=8'b00000010;
    Vd=8'bz;
    _OE=1'b0;
    #PD
    `Equals(D, 8'b00000010);
 
    `DISPLAY("TEST: NO READ OR WRITE");
    Vd=8'bzzzzzzzz;
    _OE=1'b1;
    #PD
    `Equals(D, 8'bzzzzzzzz);

   `DISPLAY("TEST: READ at 2");
    Vd=8'bz;
    A=8'b00000010;
    _OE=1'b0;
    #PD
    `Equals(D, 8'b00000010);
 
    `DISPLAY("TEST: Slide READ at 1");
    Vd=8'bz;
    A=8'b00000001;
    #PD
    `Equals(D, 8'b00000001);
 
    `DISPLAY("TEST: Slide READ at 0 is not defined");
    Vd=8'bz;
    A=8'b00000000;
    #PD
    `Equals(D, RAM.UNDEF);

    `DISPLAY("TEST: READ at 3");
    Vd=8'bz;
    _WE=1'b1;
    _OE=1'b0;
    A=8'b00000011;
    #PD
    `Equals(D, RAM.UNDEF);
 
    `DISPLAY("TEST: WRITE AT 3 with _OE override");
    Vd=8'b00000011;
    A=8'b00000011;
    _WE=1'b0;
    _OE=1'b0;
    #PD

    `DISPLAY("TEST: READ BACK AT 3 and expect bus conflict");
    Vd=8'b11111111;
    _WE=1'b1;
    _OE=1'b0;
    #PD
    `Equals(D, 8'bxxxxxx11);
 
    `DISPLAY("TEST: READ BACK AT 3");
    Vd=8'bz;
    _WE=1'b1;
    _OE=1'b0;
    #PD
    `Equals(D, 8'b11);
 
 
 end

endmodule