data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/processor_top_module_testbench.v
 line:16: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/processor_top_module_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/processor_top_module_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #400  \n    ^\n%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/processor_top_module_testbench.v:8: Cannot find file containing module: \'clock\'\nclock my_clock(.clk(clk));\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new,data/full_repos/permissive/133458123/clock\n             data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new,data/full_repos/permissive/133458123/clock.v\n             data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new,data/full_repos/permissive/133458123/clock.sv\n             clock\n             clock.v\n             clock.sv\n             obj_dir/clock\n             obj_dir/clock.v\n             obj_dir/clock.sv\n%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/processor_top_module_testbench.v:9: Cannot find file containing module: \'processor_top_module\'\nprocessor_top_module uut(.clk(clk), .reset(reset));\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module processor_top_module_testbench;

wire clk;
reg reset;

clock my_clock(.clk(clk));
processor_top_module uut(.clk(clk), .reset(reset));

initial begin
    reset=1'b1;
    #5
    reset=1'b0;
    #400
    $finish;
end
endmodule
module processor_top_module_testbench;


wire clk;
reg reset;

clock my_clock(.clk(clk));
processor_top_module uut(.clk(clk), .reset(reset));

initial begin
    reset=1'b1;
    #5
    reset=1'b0;
    #400
    $finish;
end
endmodule