data/full_repos/permissive/189158922/verilog_src/merge.v
 line:49: before: "*"
1: b'%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/merge.v:50: Operator SHIFTL expects 62 bits on the LHS, but LHS\'s VARREF \'enc_in1\' generates 31 bits.\n                                                                           : ... In instance top.__0249\n  assign \\$3  = enc_in1 <<< (* src = "merge.py:75" *) enc_in_ctr2;\n                        ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/merge.v:51: Operator OR expects 62 bits on the RHS, but RHS\'s VARREF \'enc_in2\' generates 31 bits.\n                                                                           : ... In instance top.__0249\n  assign \\$5  = \\$3  | (* src = "merge.py:75" *) enc_in2;\n                     ^\n%Error: Exiting due to 2 warning(s)\n'
module top(enc_in_ctr, valid_in, end_in, \enc_in$1 , \enc_in_ctr$2 , rst, clk, enc_out, enc_out_ctr, valid_out, end_out, enc_in);
  (* src = "merge.py:43" *)
  reg [30:0] \$next\enc_in1 ;
  (* src = "merge.py:46" *)
  reg [30:0] \$next\enc_in2 ;
  (* src = "merge.py:44" *)
  reg [4:0] \$next\enc_in_ctr1 ;
  (* src = "merge.py:47" *)
  reg [4:0] \$next\enc_in_ctr2 ;
  (* src = "merge.py:112" *)
  reg [61:0] \$next\enc_out ;
  (* src = "merge.py:113" *)
  reg [5:0] \$next\enc_out_ctr ;
  (* src = "merge.py:57" *)
  reg \$next\end_in$4 ;
  (* src = "merge.py:121" *)
  reg \$next\end_out ;
  (* src = "merge.py:53" *)
  reg \$next\valid_in$3 ;
  (* src = "merge.py:117" *)
  reg \$next\valid_out ;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* src = "merge.py:109" *)
  input [30:0] enc_in;
  (* src = "merge.py:109" *)
  input [30:0] \enc_in$1 ;
  (* src = "merge.py:43" *)
  wire [30:0] enc_in1;
  (* src = "merge.py:46" *)
  wire [30:0] enc_in2;
  (* src = "merge.py:110" *)
  input [4:0] enc_in_ctr;
  (* src = "merge.py:110" *)
  input [4:0] \enc_in_ctr$2 ;
  (* src = "merge.py:44" *)
  wire [4:0] enc_in_ctr1;
  (* src = "merge.py:47" *)
  wire [4:0] enc_in_ctr2;
  (* src = "merge.py:112" *)
  output [61:0] enc_out;
  (* src = "merge.py:49" *)
  wire [61:0] \enc_out$6 ;
  (* src = "merge.py:113" *)
  output [5:0] enc_out_ctr;
  (* src = "merge.py:50" *)
  wire [5:0] \enc_out_ctr$5 ;
  (* src = "merge.py:120" *)
  input end_in;
  (* src = "merge.py:57" *)
  wire \end_in$4 ;
  (* src = "merge.py:121" *)
  output end_out;
  (* src = "merge.py:58" *)
  wire \end_out$8 ;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "merge.py:116" *)
  input valid_in;
  (* src = "merge.py:53" *)
  wire \valid_in$3 ;
  (* src = "merge.py:117" *)
  output valid_out;
  (* src = "merge.py:54" *)
  wire \valid_out$7 ;
  anonymous \$9  (
    .clk(clk),
    .enc_in1(enc_in1),
    .enc_in2(enc_in2),
    .enc_in_ctr1(enc_in_ctr1),
    .enc_in_ctr2(enc_in_ctr2),
    .enc_out(\enc_out$6 ),
    .enc_out_ctr(\enc_out_ctr$5 ),
    .end_in(\end_in$4 ),
    .end_out(\end_out$8 ),
    .rst(rst),
    .valid_in(\valid_in$3 ),
    .valid_out(\valid_out$7 )
  );
  always @* begin
    \$next\enc_in1  = 31'h00000000;
    \$next\enc_in1  = enc_in;
  end
  always @* begin
    \$next\enc_in_ctr1  = 5'h00;
    \$next\enc_in_ctr1  = enc_in_ctr;
  end
  always @* begin
    \$next\valid_in$3  = 1'h0;
    \$next\valid_in$3  = valid_in;
  end
  always @* begin
    \$next\end_in$4  = 1'h0;
    \$next\end_in$4  = end_in;
  end
  always @* begin
    \$next\enc_in2  = 31'h00000000;
    \$next\enc_in2  = \enc_in$1 ;
  end
  always @* begin
    \$next\enc_in_ctr2  = 5'h00;
    \$next\enc_in_ctr2  = \enc_in_ctr$2 ;
  end
  always @* begin
    \$next\enc_out  = 62'h0000000000000000;
    \$next\enc_out  = \enc_out$6 ;
  end
  always @* begin
    \$next\enc_out_ctr  = 6'h00;
    \$next\enc_out_ctr  = \enc_out_ctr$5 ;
  end
  always @* begin
    \$next\valid_out  = 1'h0;
    \$next\valid_out  = \valid_out$7 ;
  end
  always @* begin
    \$next\end_out  = 1'h0;
    \$next\end_out  = \end_out$8 ;
  end
  assign end_out = \$next\end_out ;
  assign valid_out = \$next\valid_out ;
  assign enc_out_ctr = \$next\enc_out_ctr ;
  assign enc_out = \$next\enc_out ;
  assign enc_in_ctr2 = \$next\enc_in_ctr2 ;
  assign enc_in2 = \$next\enc_in2 ;
  assign \end_in$4  = \$next\end_in$4 ;
  assign \valid_in$3  = \$next\valid_in$3 ;
  assign enc_in_ctr1 = \$next\enc_in_ctr1 ;
  assign enc_in1 = \$next\enc_in1 ;
endmodule
module top(enc_in_ctr, valid_in, end_in, \enc_in$1 , \enc_in_ctr$2 , rst, clk, enc_out, enc_out_ctr, valid_out, end_out, enc_in);

  (* src = "merge.py:43" *)
  reg [30:0] \$next\enc_in1 ;
  (* src = "merge.py:46" *)
  reg [30:0] \$next\enc_in2 ;
  (* src = "merge.py:44" *)
  reg [4:0] \$next\enc_in_ctr1 ;
  (* src = "merge.py:47" *)
  reg [4:0] \$next\enc_in_ctr2 ;
  (* src = "merge.py:112" *)
  reg [61:0] \$next\enc_out ;
  (* src = "merge.py:113" *)
  reg [5:0] \$next\enc_out_ctr ;
  (* src = "merge.py:57" *)
  reg \$next\end_in$4 ;
  (* src = "merge.py:121" *)
  reg \$next\end_out ;
  (* src = "merge.py:53" *)
  reg \$next\valid_in$3 ;
  (* src = "merge.py:117" *)
  reg \$next\valid_out ;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* src = "merge.py:109" *)
  input [30:0] enc_in;
  (* src = "merge.py:109" *)
  input [30:0] \enc_in$1 ;
  (* src = "merge.py:43" *)
  wire [30:0] enc_in1;
  (* src = "merge.py:46" *)
  wire [30:0] enc_in2;
  (* src = "merge.py:110" *)
  input [4:0] enc_in_ctr;
  (* src = "merge.py:110" *)
  input [4:0] \enc_in_ctr$2 ;
  (* src = "merge.py:44" *)
  wire [4:0] enc_in_ctr1;
  (* src = "merge.py:47" *)
  wire [4:0] enc_in_ctr2;
  (* src = "merge.py:112" *)
  output [61:0] enc_out;
  (* src = "merge.py:49" *)
  wire [61:0] \enc_out$6 ;
  (* src = "merge.py:113" *)
  output [5:0] enc_out_ctr;
  (* src = "merge.py:50" *)
  wire [5:0] \enc_out_ctr$5 ;
  (* src = "merge.py:120" *)
  input end_in;
  (* src = "merge.py:57" *)
  wire \end_in$4 ;
  (* src = "merge.py:121" *)
  output end_out;
  (* src = "merge.py:58" *)
  wire \end_out$8 ;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "merge.py:116" *)
  input valid_in;
  (* src = "merge.py:53" *)
  wire \valid_in$3 ;
  (* src = "merge.py:117" *)
  output valid_out;
  (* src = "merge.py:54" *)
  wire \valid_out$7 ;
  anonymous \$9  (
    .clk(clk),
    .enc_in1(enc_in1),
    .enc_in2(enc_in2),
    .enc_in_ctr1(enc_in_ctr1),
    .enc_in_ctr2(enc_in_ctr2),
    .enc_out(\enc_out$6 ),
    .enc_out_ctr(\enc_out_ctr$5 ),
    .end_in(\end_in$4 ),
    .end_out(\end_out$8 ),
    .rst(rst),
    .valid_in(\valid_in$3 ),
    .valid_out(\valid_out$7 )
  );
  always @* begin
    \$next\enc_in1  = 31'h00000000;
    \$next\enc_in1  = enc_in;
  end
  always @* begin
    \$next\enc_in_ctr1  = 5'h00;
    \$next\enc_in_ctr1  = enc_in_ctr;
  end
  always @* begin
    \$next\valid_in$3  = 1'h0;
    \$next\valid_in$3  = valid_in;
  end
  always @* begin
    \$next\end_in$4  = 1'h0;
    \$next\end_in$4  = end_in;
  end
  always @* begin
    \$next\enc_in2  = 31'h00000000;
    \$next\enc_in2  = \enc_in$1 ;
  end
  always @* begin
    \$next\enc_in_ctr2  = 5'h00;
    \$next\enc_in_ctr2  = \enc_in_ctr$2 ;
  end
  always @* begin
    \$next\enc_out  = 62'h0000000000000000;
    \$next\enc_out  = \enc_out$6 ;
  end
  always @* begin
    \$next\enc_out_ctr  = 6'h00;
    \$next\enc_out_ctr  = \enc_out_ctr$5 ;
  end
  always @* begin
    \$next\valid_out  = 1'h0;
    \$next\valid_out  = \valid_out$7 ;
  end
  always @* begin
    \$next\end_out  = 1'h0;
    \$next\end_out  = \end_out$8 ;
  end
  assign end_out = \$next\end_out ;
  assign valid_out = \$next\valid_out ;
  assign enc_out_ctr = \$next\enc_out_ctr ;
  assign enc_out = \$next\enc_out ;
  assign enc_in_ctr2 = \$next\enc_in_ctr2 ;
  assign enc_in2 = \$next\enc_in2 ;
  assign \end_in$4  = \$next\end_in$4 ;
  assign \valid_in$3  = \$next\valid_in$3 ;
  assign enc_in_ctr1 = \$next\enc_in_ctr1 ;
  assign enc_in1 = \$next\enc_in1 ;
endmodule