data/full_repos/permissive/201488448/1_verilog/23_module_add.v
1: b"%Error: data/full_repos/permissive/201488448/1_verilog/23_module_add.v:7: Cannot find file containing module: 'add16'\n    add16 a1(a[15:0],b[15:0],1'b0,sum[15:0],mid);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/add16\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/add16.v\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/201488448/1_verilog/23_module_add.v:8: Cannot find file containing module: 'add16'\n    add16 a2(a[31:16],b[31:16],mid,sum[31:16],bot);\n    ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire mid,bot;
    add16 a1(a[15:0],b[15:0],1'b0,sum[15:0],mid);
    add16 a2(a[31:16],b[31:16],mid,sum[31:16],bot);
endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

    wire mid,bot;
    add16 a1(a[15:0],b[15:0],1'b0,sum[15:0],mid);
    add16 a2(a[31:16],b[31:16],mid,sum[31:16],bot);
endmodule