data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_router.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_router.v:18: Cannot find include file: raggedstone_spinn_aer_if_top.h\n`include "raggedstone_spinn_aer_if_top.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if,data/full_repos/permissive/19591557/raggedstone_spinn_aer_if_top.h\n             data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if,data/full_repos/permissive/19591557/raggedstone_spinn_aer_if_top.h.v\n             data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if,data/full_repos/permissive/19591557/raggedstone_spinn_aer_if_top.h.sv\n             raggedstone_spinn_aer_if_top.h\n             raggedstone_spinn_aer_if_top.h.v\n             raggedstone_spinn_aer_if_top.h.sv\n             obj_dir/raggedstone_spinn_aer_if_top.h\n             obj_dir/raggedstone_spinn_aer_if_top.h.v\n             obj_dir/raggedstone_spinn_aer_if_top.h.sv\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_router.v:19: Cannot find include file: ../../modules/spinnaker_link/spio_spinnaker_link.h\n`include "../../modules/spinnaker_link/spio_spinnaker_link.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_router.v:29: Define or directive not defined: \'`PKT_BITS\'\n  input  wire [`PKT_BITS - 1:0] spkt_data,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_router.v:34: Define or directive not defined: \'`PKT_BITS\'\n  output wire [`PKT_BITS - 1:0] opkt_data,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_router.v:39: Define or directive not defined: \'`PKT_BITS\'\n  output wire [`PKT_BITS - 1:0] cpkt_data,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_router.v:56: Define or directive not defined: \'`PKT_BITS\'\n    .PKT_BITS(`PKT_BITS),\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_router.v:83: Define or directive not defined: \'`PKT_KEY_RNG\'\n  assign ct_pkt = ((spkt_data[`PKT_KEY_RNG] & `CTRL_MSK) == `CTRL_KEY);\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_router.v:83: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign ct_pkt = ((spkt_data[`PKT_KEY_RNG] & `CTRL_MSK) == `CTRL_KEY);\n                                          ^\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_router.v:83: Define or directive not defined: \'`CTRL_MSK\'\n  assign ct_pkt = ((spkt_data[`PKT_KEY_RNG] & `CTRL_MSK) == `CTRL_KEY);\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/designs/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_router.v:83: Define or directive not defined: \'`CTRL_KEY\'\n  assign ct_pkt = ((spkt_data[`PKT_KEY_RNG] & `CTRL_MSK) == `CTRL_KEY);\n                                                            ^~~~~~~~~\n%Error: Exiting due to 10 error(s)\n'
module raggedstone_spinn_aer_if_router
(
  input  wire                   rst,
  input  wire                   clk,


  input  wire [`PKT_BITS - 1:0] spkt_data,
  input  wire                   spkt_vld,
  output wire                   spkt_rdy,


  output wire [`PKT_BITS - 1:0] opkt_data,
  output wire                   opkt_vld,
  input  wire                   opkt_rdy,


  output wire [`PKT_BITS - 1:0] cpkt_data,
  output wire                   cpkt_vld,
  input  wire                   cpkt_rdy
);



  wire [1:0] sw_sel;
  wire       mc_pkt;
  wire       ct_pkt;





  spio_switch
  #(
    .PKT_BITS(`PKT_BITS),
    .NUM_PORTS(2)
  ) sw
  (
    .RESET_IN             (rst),
    .CLK_IN               (clk),
    .IN_DATA_IN           (spkt_data),
    .IN_VLD_IN            (spkt_vld),
    .IN_RDY_OUT           (spkt_rdy),
    .IN_OUTPUT_SELECT_IN  (sw_sel),
    .OUT_DATA_OUT         ({cpkt_data, opkt_data}),
    .OUT_VLD_OUT          ({cpkt_vld,  opkt_vld}),
    .OUT_RDY_IN           ({cpkt_rdy,  opkt_rdy}),
    .BLOCKED_OUTPUTS_OUT  (),
    .SELECTED_OUTPUTS_OUT (),
    .DROP_IN              (1'b0),
    .DROPPED_DATA_OUT     (),
    .DROPPED_OUTPUTS_OUT  (),
    .DROPPED_VLD_OUT      ()
  );


  assign sw_sel[0] = spkt_vld & mc_pkt & ~ct_pkt;
  assign sw_sel[1] = spkt_vld & mc_pkt &  ct_pkt;


  assign mc_pkt = (spkt_data[7:6] == 2'b00);
  assign ct_pkt = ((spkt_data[`PKT_KEY_RNG] & `CTRL_MSK) == `CTRL_KEY);
endmodule
module raggedstone_spinn_aer_if_router
(
  input  wire                   rst,
  input  wire                   clk,


  input  wire [`PKT_BITS - 1:0] spkt_data,
  input  wire                   spkt_vld,
  output wire                   spkt_rdy,


  output wire [`PKT_BITS - 1:0] opkt_data,
  output wire                   opkt_vld,
  input  wire                   opkt_rdy,


  output wire [`PKT_BITS - 1:0] cpkt_data,
  output wire                   cpkt_vld,
  input  wire                   cpkt_rdy
);




  wire [1:0] sw_sel;
  wire       mc_pkt;
  wire       ct_pkt;





  spio_switch
  #(
    .PKT_BITS(`PKT_BITS),
    .NUM_PORTS(2)
  ) sw
  (
    .RESET_IN             (rst),
    .CLK_IN               (clk),
    .IN_DATA_IN           (spkt_data),
    .IN_VLD_IN            (spkt_vld),
    .IN_RDY_OUT           (spkt_rdy),
    .IN_OUTPUT_SELECT_IN  (sw_sel),
    .OUT_DATA_OUT         ({cpkt_data, opkt_data}),
    .OUT_VLD_OUT          ({cpkt_vld,  opkt_vld}),
    .OUT_RDY_IN           ({cpkt_rdy,  opkt_rdy}),
    .BLOCKED_OUTPUTS_OUT  (),
    .SELECTED_OUTPUTS_OUT (),
    .DROP_IN              (1'b0),
    .DROPPED_DATA_OUT     (),
    .DROPPED_OUTPUTS_OUT  (),
    .DROPPED_VLD_OUT      ()
  );


  assign sw_sel[0] = spkt_vld & mc_pkt & ~ct_pkt;
  assign sw_sel[1] = spkt_vld & mc_pkt &  ct_pkt;


  assign mc_pkt = (spkt_data[7:6] == 2'b00);
  assign ct_pkt = ((spkt_data[`PKT_KEY_RNG] & `CTRL_MSK) == `CTRL_KEY);
endmodule