data/full_repos/permissive/202032771/vmod/cnnip_ctrlr.sv
 line:15: before: "."
1: b'%Warning-MULTITOP: data/full_repos/permissive/202032771/vmod/cnnip_ctrlr.sv:15: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'cnnip_ctrlr\'\nmodule cnnip_ctrlr\n       ^~~~~~~~~~~\n                                                                              : ... Top module \'cnnip_mem_if\'\n  cnnip_mem_if.master to_input_mem,\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/202032771/vmod/cnnip_ctrlr.sv:15: Unsupported: Interfaced port on top level module\n  cnnip_mem_if.master to_input_mem,\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/202032771/vmod/cnnip_ctrlr.sv:16: Unsupported: Interfaced port on top level module\n  cnnip_mem_if.master to_weight_mem,\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/202032771/vmod/cnnip_ctrlr.sv:17: Unsupported: Interfaced port on top level module\n  cnnip_mem_if.master to_feature_mem,\n                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/202032771/vmod/cnnip_ctrlr.sv:15: Cannot find file containing interface: \'cnnip_mem_if\'\n  cnnip_mem_if.master to_input_mem,\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/202032771/vmod/cnnip_ctrlr.sv:16: Cannot find file containing interface: \'cnnip_mem_if\'\n  cnnip_mem_if.master to_weight_mem,\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/202032771/vmod/cnnip_ctrlr.sv:17: Cannot find file containing interface: \'cnnip_mem_if\'\n  cnnip_mem_if.master to_feature_mem,\n  ^~~~~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/202032771/vmod/cnnip_ctrlr.sv:15: ../V3LinkDot.cpp:2055: Unlinked interface\n  cnnip_mem_if.master to_input_mem,\n  ^~~~~~~~~~~~\n'
module cnnip_ctrlr
(

  input wire clk_a,
  input wire arstz_aq,


  cnnip_mem_if.master to_input_mem,
  cnnip_mem_if.master to_weight_mem,
  cnnip_mem_if.master to_feature_mem,


  input wire         CMD_START,
  input wire   [7:0] MODE_KERNEL_SIZE,
  input wire   [7:0] MODE_KERNEL_NUMS,
  input wire   [1:0] MODE_STRIDE,
  input wire         MODE_PADDING,

  output wire        CMD_DONE,
  output wire        CMD_DONE_VALID

);


  enum { IDLE, WAIT, DONE } state_aq, state_next;


  reg [15:0] cnt_aq;

  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) cnt_aq <= 16'b0;
    else if (state_aq == WAIT) cnt_aq <= cnt_aq + 1'b1;
    else cnt_aq <= 16'b0;


  wire wait_done = (cnt_aq == 16'b1000_1111_0000_0000);


  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) state_aq <= IDLE;
    else state_aq <= state_next;


  always @(*)
  begin
    state_next = state_aq;
    case (state_aq)
      IDLE:
        if (CMD_START) state_next = WAIT;

      WAIT:
        if (wait_done) state_next = DONE;

      DONE:
        state_next = IDLE;
    endcase
  end


  assign CMD_DONE = (state_aq == DONE);
  assign CMD_DONE_VALID = (state_aq == DONE);


  assign to_input_mem.en   = 0;
  assign to_input_mem.we   = 'b0;
  assign to_input_mem.addr = 'b0;
  assign to_input_mem.din  = 'b0;

  assign to_weight_mem.en   = 0;
  assign to_weight_mem.we   = 'b0;
  assign to_weight_mem.addr = 'b0;
  assign to_weight_mem.din  = 'b0;

  assign to_feature_mem.en   = 0;
  assign to_feature_mem.we   = 'b0;
  assign to_feature_mem.addr = 'b0;
  assign to_feature_mem.din  = 'b0;

endmodule
module cnnip_ctrlr
(

  input wire clk_a,
  input wire arstz_aq,


  cnnip_mem_if.master to_input_mem,
  cnnip_mem_if.master to_weight_mem,
  cnnip_mem_if.master to_feature_mem,


  input wire         CMD_START,
  input wire   [7:0] MODE_KERNEL_SIZE,
  input wire   [7:0] MODE_KERNEL_NUMS,
  input wire   [1:0] MODE_STRIDE,
  input wire         MODE_PADDING,

  output wire        CMD_DONE,
  output wire        CMD_DONE_VALID

);



  enum { IDLE, WAIT, DONE } state_aq, state_next;


  reg [15:0] cnt_aq;

  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) cnt_aq <= 16'b0;
    else if (state_aq == WAIT) cnt_aq <= cnt_aq + 1'b1;
    else cnt_aq <= 16'b0;


  wire wait_done = (cnt_aq == 16'b1000_1111_0000_0000);


  always @(posedge clk_a, negedge arstz_aq)
    if (arstz_aq == 1'b0) state_aq <= IDLE;
    else state_aq <= state_next;


  always @(*)
  begin
    state_next = state_aq;
    case (state_aq)
      IDLE:
        if (CMD_START) state_next = WAIT;

      WAIT:
        if (wait_done) state_next = DONE;

      DONE:
        state_next = IDLE;
    endcase
  end


  assign CMD_DONE = (state_aq == DONE);
  assign CMD_DONE_VALID = (state_aq == DONE);


  assign to_input_mem.en   = 0;
  assign to_input_mem.we   = 'b0;
  assign to_input_mem.addr = 'b0;
  assign to_input_mem.din  = 'b0;

  assign to_weight_mem.en   = 0;
  assign to_weight_mem.we   = 'b0;
  assign to_weight_mem.addr = 'b0;
  assign to_weight_mem.din  = 'b0;

  assign to_feature_mem.en   = 0;
  assign to_feature_mem.we   = 'b0;
  assign to_feature_mem.addr = 'b0;
  assign to_feature_mem.din  = 'b0;

endmodule