data/full_repos/permissive/124844461/Lab1/data_mem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/124844461/Lab1/data_mem.v:34: Bit extraction of array[1023:0] requires 10 bit index, not 1024 bits.\n                                                                       : ... In instance data_mem\n    RAM[i]=0;\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/124844461/Lab1/data_mem.v:45: Bit extraction of array[1023:0] requires 10 bit index, not 1024 bits.\n                                                                       : ... In instance data_mem\n     RAM[i] <= 0;\n        ^\n%Error: Exiting due to 2 warning(s)\n'
module data_mem
#(parameter DATA_WIDTH = 32, BUS_WIDTH = 10)
(
	input clk,
	input MEMread,
	input MEMwrite,
	input [3:0] address,
	input [BUS_WIDTH-1:0] A,
	input [DATA_WIDTH-1:0] D,
	input RST,
	output [DATA_WIDTH-1:0] rdata,
	output [DATA_WIDTH-1:0] display_data
);
	reg [DATA_WIDTH-1:0] RAM [0:(2**BUS_WIDTH)-1];
	reg [(2**BUS_WIDTH)-1:0] i;
	wire [9:0] ADDRESS_expand;
	initial begin
		for(i=0;i<2**BUS_WIDTH;i=i+1)
			begin
				RAM[i]=0;
			end
	end
	assign ADDRESS_expand = { {6'b0},address};
	always @(posedge clk) begin
		if(MEMwrite) begin
			RAM[A] <= D;
			end
		if(RST) begin
			for(i=0 ;i < 2**BUS_WIDTH;i = i + 1)
				begin
					RAM[i] <= 0;
				end
		end
	end
	assign rdata = MEMread ?RAM[A] : {(DATA_WIDTH){1'b0}};
	assign display_data = RAM[ADDRESS_expand];
endmodule
module data_mem
#(parameter DATA_WIDTH = 32, BUS_WIDTH = 10)
(
	input clk,
	input MEMread,
	input MEMwrite,
	input [3:0] address,
	input [BUS_WIDTH-1:0] A,
	input [DATA_WIDTH-1:0] D,
	input RST,
	output [DATA_WIDTH-1:0] rdata,
	output [DATA_WIDTH-1:0] display_data
);

	reg [DATA_WIDTH-1:0] RAM [0:(2**BUS_WIDTH)-1];
	reg [(2**BUS_WIDTH)-1:0] i;
	wire [9:0] ADDRESS_expand;
	initial begin
		for(i=0;i<2**BUS_WIDTH;i=i+1)
			begin
				RAM[i]=0;
			end
	end
	assign ADDRESS_expand = { {6'b0},address};
	always @(posedge clk) begin
		if(MEMwrite) begin
			RAM[A] <= D;
			end
		if(RST) begin
			for(i=0 ;i < 2**BUS_WIDTH;i = i + 1)
				begin
					RAM[i] <= 0;
				end
		end
	end
	assign rdata = MEMread ?RAM[A] : {(DATA_WIDTH){1'b0}};
	assign display_data = RAM[ADDRESS_expand];
endmodule