data/full_repos/permissive/170041316/hw3_2/fullAdder_1b_bench.v
 line:20: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/170041316/hw3_2/fullAdder_1b_bench.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #3200 $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/170041316/hw3_2/fullAdder_1b_bench.v:13: Cannot find file containing module: \'clkrst\'\n    clkrst my_clkrst( .clk(Clk), .rst(rst), .err(err));\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170041316/hw3_2,data/full_repos/permissive/170041316/clkrst\n             data/full_repos/permissive/170041316/hw3_2,data/full_repos/permissive/170041316/clkrst.v\n             data/full_repos/permissive/170041316/hw3_2,data/full_repos/permissive/170041316/clkrst.sv\n             clkrst\n             clkrst.v\n             clkrst.sv\n             obj_dir/clkrst\n             obj_dir/clkrst.v\n             obj_dir/clkrst.sv\n%Error: data/full_repos/permissive/170041316/hw3_2/fullAdder_1b_bench.v:14: Cannot find file containing module: \'fullAdder_1b\'\n    fullAdder_1b DUT (.A(A), .B(B), .C_in(C_in),.S(SUM), .C_out(CO));\n    ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/170041316/hw3_2/fullAdder_1b_bench.v:17: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                  : ... In instance fullAdder_1b_bench\n        A = 2\'b0;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/170041316/hw3_2/fullAdder_1b_bench.v:18: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                  : ... In instance fullAdder_1b_bench\n        B = 2\'b0;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/170041316/hw3_2/fullAdder_1b_bench.v:24: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                  : ... In instance fullAdder_1b_bench\n        A = $random;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/170041316/hw3_2/fullAdder_1b_bench.v:25: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                  : ... In instance fullAdder_1b_bench\n        B = $random;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/170041316/hw3_2/fullAdder_1b_bench.v:26: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                  : ... In instance fullAdder_1b_bench\n        C_in = $random;\n             ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fullAdder_1b_bench;

    reg A;
    reg B;
    reg[1:0] Sumcalc;
    reg C_in;
    wire        SUM;
    wire        CO;
    wire        Clk;

    wire rst;
    wire err;
    clkrst my_clkrst( .clk(Clk), .rst(rst), .err(err));
    fullAdder_1b DUT (.A(A), .B(B), .C_in(C_in),.S(SUM), .C_out(CO));
  
    initial begin
        A = 2'b0;
        B = 2'b0;
        C_in = 1'b0;
        #3200 $finish;
    end
   
    always@(posedge Clk) begin
        A = $random;
        B = $random;
        C_in = $random;
    end
   
    always@(negedge Clk) begin
        Sumcalc = A+B+C_in;
        $display("A: %x, B: %x, C_in: %x, Sum: %x", A, B, C_in, SUM);
    
        if (Sumcalc[0] !== SUM) $display ("ERRORCHECK Sum error");
        if (Sumcalc[1] !== CO) $display ("ERRORCHECK CO error");
    end
endmodule
module fullAdder_1b_bench;


    reg A;
    reg B;
    reg[1:0] Sumcalc;
    reg C_in;
    wire        SUM;
    wire        CO;
    wire        Clk;

    wire rst;
    wire err;
    clkrst my_clkrst( .clk(Clk), .rst(rst), .err(err));
    fullAdder_1b DUT (.A(A), .B(B), .C_in(C_in),.S(SUM), .C_out(CO));
  
    initial begin
        A = 2'b0;
        B = 2'b0;
        C_in = 1'b0;
        #3200 $finish;
    end
   
    always@(posedge Clk) begin
        A = $random;
        B = $random;
        C_in = $random;
    end
   
    always@(negedge Clk) begin
        Sumcalc = A+B+C_in;
        $display("A: %x, B: %x, C_in: %x, Sum: %x", A, B, C_in, SUM);
    
        if (Sumcalc[0] !== SUM) $display ("ERRORCHECK Sum error");
        if (Sumcalc[1] !== CO) $display ("ERRORCHECK CO error");
    end
endmodule