data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v
1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:10: Cannot find include file: ahb_lite.vh\n`include "ahb_lite.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.v\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.sv\n             ahb_lite.vh\n             ahb_lite.vh.v\n             ahb_lite.vh.sv\n             obj_dir/ahb_lite.vh\n             obj_dir/ahb_lite.vh.v\n             obj_dir/ahb_lite.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:11: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:32: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    input  [`SM_GPIO_WIDTH - 1:0] port_gpioIn,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:33: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    output [`SM_GPIO_WIDTH - 1:0] port_gpioOut\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:36: Define or directive not defined: \'`HTRANS_IDLE\'\n    wire request   = HREADY & HSEL & HTRANS != `HTRANS_IDLE;\n                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    wire request   = HREADY & HSEL & HTRANS != `HTRANS_IDLE;\n                                                           ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:92: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    input  [`SM_GPIO_WIDTH - 1:0] gpioInput,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:93: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    output [`SM_GPIO_WIDTH - 1:0] gpioOutput\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:95: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    wire   [`SM_GPIO_WIDTH - 1:0] gpioIn;     \n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:97: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    wire   [`SM_GPIO_WIDTH - 1:0] gpioOut;    \n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:99: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    assign gpioOut   = bWData [`SM_GPIO_WIDTH - 1:0];\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:102: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    sm_debouncer   #(`SM_GPIO_WIDTH) debounce(clk, gpioInput, gpioIn);\n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:103: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    sm_register_we #(`SM_GPIO_WIDTH) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);\n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:105: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n    localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;\n                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;\n                                                ^\n%Error: Exiting due to 15 error(s)\n'
module sm_gpio
(

    input             clk,
    input             rst_n,
    input             bSel,
    input      [31:0] bAddr,
    input             bWrite,
    input      [31:0] bWData,
    output reg [31:0] bRData,


    input  [`SM_GPIO_WIDTH - 1:0] gpioInput,
    output [`SM_GPIO_WIDTH - 1:0] gpioOutput
);
    wire   [`SM_GPIO_WIDTH - 1:0] gpioIn;
    wire                          gpioOutWe;
    wire   [`SM_GPIO_WIDTH - 1:0] gpioOut;

    assign gpioOut   = bWData [`SM_GPIO_WIDTH - 1:0];
    assign gpioOutWe = bSel & bWrite & (bAddr[3:0] == `SM_GPIO_REG_OUTPUT);

    sm_debouncer   #(`SM_GPIO_WIDTH) debounce(clk, gpioInput, gpioIn);
    sm_register_we #(`SM_GPIO_WIDTH) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);

    localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;

    always @ (*)
        case(bAddr[3:0])
            default              : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn  };
            `SM_GPIO_REG_INPUT   : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn  };
            `SM_GPIO_REG_OUTPUT  : bRData = { { BLANK_WIDTH {1'b0}}, gpioOut };
        endcase

endmodule
module sm_gpio
(

    input             clk,
    input             rst_n,
    input             bSel,
    input      [31:0] bAddr,
    input             bWrite,
    input      [31:0] bWData,
    output reg [31:0] bRData,


    input  [`SM_GPIO_WIDTH - 1:0] gpioInput,
    output [`SM_GPIO_WIDTH - 1:0] gpioOutput
);

    wire   [`SM_GPIO_WIDTH - 1:0] gpioIn;
    wire                          gpioOutWe;
    wire   [`SM_GPIO_WIDTH - 1:0] gpioOut;

    assign gpioOut   = bWData [`SM_GPIO_WIDTH - 1:0];
    assign gpioOutWe = bSel & bWrite & (bAddr[3:0] == `SM_GPIO_REG_OUTPUT);

    sm_debouncer   #(`SM_GPIO_WIDTH) debounce(clk, gpioInput, gpioIn);
    sm_register_we #(`SM_GPIO_WIDTH) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);

    localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;

    always @ (*)
        case(bAddr[3:0])
            default              : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn  };
            `SM_GPIO_REG_INPUT   : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn  };
            `SM_GPIO_REG_OUTPUT  : bRData = { { BLANK_WIDTH {1'b0}}, gpioOut };
        endcase

endmodule