data/full_repos/permissive/157696705/brainfuck computer/Program_counter.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: computer,data/full_repos/permissive/157696705\n        ... Looked in:\n             data/full_repos/permissive/157696705/brainfuck/computer,data/full_repos/permissive/157696705\n             data/full_repos/permissive/157696705/brainfuck/computer,data/full_repos/permissive/157696705.v\n             data/full_repos/permissive/157696705/brainfuck/computer,data/full_repos/permissive/157696705.sv\n             computer,data/full_repos/permissive/157696705\n             computer,data/full_repos/permissive/157696705.v\n             computer,data/full_repos/permissive/157696705.sv\n             obj_dir/computer,data/full_repos/permissive/157696705\n             obj_dir/computer,data/full_repos/permissive/157696705.v\n             obj_dir/computer,data/full_repos/permissive/157696705.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/157696705/brainfuck\n%Error: Cannot find file containing module: computer/Program_counter.v\n%Error: Exiting due to 3 error(s)\n'
module Program_counter(
    input               enable, clk, branch,
    input       [9:0]   B_ADR,
    output  reg [9:0]   ADR = 10'h000
);
always @(posedge clk)
begin
  if(enable)
  begin
    if(branch)
    begin
      ADR[9:0] <= B_ADR[9:0];
    end
    else
    begin
      ADR[9:0] <= ADR[9:0] + 10'h001;
    end
  end
end
endmodule
module Program_counter(
    input               enable, clk, branch,
    input       [9:0]   B_ADR,
    output  reg [9:0]   ADR = 10'h000
);

always @(posedge clk)
begin
  if(enable)
  begin
    if(branch)
    begin
      ADR[9:0] <= B_ADR[9:0];
    end
    else
    begin
      ADR[9:0] <= ADR[9:0] + 10'h001;
    end
  end
end
endmodule