data/full_repos/permissive/100796583/module/MBSsoc_ram.v
'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte
1: b'%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:1: Cannot find include file: ../cpu/MBScore_const.v\n`include "../cpu/MBScore_const.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v\n             data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.v\n             data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.sv\n             ../cpu/MBScore_const.v\n             ../cpu/MBScore_const.v.v\n             ../cpu/MBScore_const.v.sv\n             obj_dir/../cpu/MBScore_const.v\n             obj_dir/../cpu/MBScore_const.v.v\n             obj_dir/../cpu/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:5: Define or directive not defined: \'`ADDR_WIDTH\'\n    input [`ADDR_WIDTH-1:0]     addr,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:6: Define or directive not defined: \'`DATA_WIDTH\'\n    inout [`DATA_WIDTH-1:0]     data\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:9: Define or directive not defined: \'`DATA_WIDTH\'\n    reg [`DATA_WIDTH-1:0] ram [0:`MEM_LEN-1];\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:9: Define or directive not defined: \'`MEM_LEN\'\n    reg [`DATA_WIDTH-1:0] ram [0:`MEM_LEN-1];\n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:12: Define or directive not defined: \'`ADDR_WIDTH\'\n    reg [`ADDR_WIDTH-1:0] addr_r;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:14: Define or directive not defined: \'`DATA_WIDTH\'\n    assign data = (ram_re == 1\'b1) ? ram[addr_r] : `DATA_WIDTH\'bz;\n                                                   ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module MBSsoc_ram(
    input                       clk,
    input                       ram_we,ram_re,wr_invalid,
    input [`ADDR_WIDTH-1:0]     addr,
    inout [`DATA_WIDTH-1:0]     data
);

    reg [`DATA_WIDTH-1:0] ram [0:`MEM_LEN-1];
    initial $readmemb("D:/lijunyan/MBSsoc/module/mem.txt",ram);  

    reg [`ADDR_WIDTH-1:0] addr_r;

    assign data = (ram_re == 1'b1) ? ram[addr_r] : `DATA_WIDTH'bz;

    always @(posedge clk)
    addr_r = addr >> 2;

    always @(posedge clk)
    if(ram_we && ~wr_invalid)
    ram[addr >> 2] = data;

endmodule
module MBSsoc_ram(
    input                       clk,
    input                       ram_we,ram_re,wr_invalid,
    input [`ADDR_WIDTH-1:0]     addr,
    inout [`DATA_WIDTH-1:0]     data
);


    reg [`DATA_WIDTH-1:0] ram [0:`MEM_LEN-1];
    initial $readmemb("D:/lijunyan/MBSsoc/module/mem.txt",ram);  

    reg [`ADDR_WIDTH-1:0] addr_r;

    assign data = (ram_re == 1'b1) ? ram[addr_r] : `DATA_WIDTH'bz;

    always @(posedge clk)
    addr_r = addr >> 2;

    always @(posedge clk)
    if(ram_we && ~wr_invalid)
    ram[addr >> 2] = data;

endmodule