data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-IMPLICIT: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:353: Signal definition not found, creating implicitly: \'clksq_gt_sqp\'\n                                                                                                : ... Suggested alternative: \'clksq_equal_sqp\'\n    assign clksq_gt_sqp              = ( clk_sq_cnt>=sqp   );                    \n           ^~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:356: Signal definition not found, creating implicitly: \'clksq_equal_phas\'\n                                                                                                : ... Suggested alternative: \'clksq_equal_sqp\'\n    assign clksq_equal_phas          = ( clk_sq_cnt_next==phas_sq[32-1:0] ) ;         \n           ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:126: Operator COND expects 15 bits on the Conditional True, but Conditional True\'s CONST \'14\'h0\' generates 14 bits.\n                                                                                             : ... In instance gen_mod2\n    assign tau_tick_cnt_next = tau_tick_cnt_equal_hp ? 14\'b0 : tau_tick_cnt + 14\'b001;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:161: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'quad_bit_next\' generates 3 bits.\n                                                                                             : ... In instance gen_mod2\n            quad_bit  <=  quad_bit_next     ;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:178: Operator ADD expects 3 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n    assign quad_bit_next  = quad_add ? quad_bit + tau_tick : quad_bit ;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:178: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s VARREF \'quad_bit\' generates 2 bits.\n                                                                                             : ... In instance gen_mod2\n    assign quad_bit_next  = quad_add ? quad_bit + tau_tick : quad_bit ;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:180: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s VARREF \'cnt\' generates 10 bits.\n                                                                                             : ... In instance gen_mod2\n    assign cnt_next       = quad_add    ? cnt   :\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:181: Operator SUB expects 11 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n                            quad_bit[0] ? cnt - tau_tick  :  cnt + tau_tick  ;\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:181: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n                            quad_bit[0] ? cnt - tau_tick  :  cnt + tau_tick  ;\n                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:183: Operator COND expects 13 bits on the Conditional True, but Conditional True\'s CONST \'12\'h0\' generates 12 bits.\n                                                                                             : ... In instance gen_mod2\n    assign cntu_next      = cnt_next_zero ? 12\'b0 :  cntu + tau_tick  ;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:183: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n    assign cntu_next      = cnt_next_zero ? 12\'b0 :  cntu + tau_tick  ;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:206: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'quad_bit1_next\' generates 3 bits.\n                                                                                             : ... In instance gen_mod2\n            quad_bit1  <=  quad_bit1_next      ;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:215: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                             : ... In instance gen_mod2\n    assign quad_bit1_next = ( cntu == phase_b ) ? 2\'b00  : quad_bit1 + (tau_tick&quad_add1) ;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:215: Operator AND expects 3 bits on the LHS, but LHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n    assign quad_bit1_next = ( cntu == phase_b ) ? 2\'b00  : quad_bit1 + (tau_tick&quad_add1) ;\n                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:215: Operator AND expects 3 bits on the RHS, but RHS\'s VARREF \'quad_add1\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n    assign quad_bit1_next = ( cntu == phase_b ) ? 2\'b00  : quad_bit1 + (tau_tick&quad_add1) ;\n                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:217: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s CONST \'10\'h0\' generates 10 bits.\n                                                                                             : ... In instance gen_mod2\n    assign cnt1_next      = ( cntu == phase_b )  ? 10\'b0   :\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:218: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s VARREF \'cnt1\' generates 10 bits.\n                                                                                             : ... In instance gen_mod2\n                            quad_add1    ? cnt1             :\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:219: Operator SUB expects 11 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n                            quad_bit1[0] ? cnt1 - tau_tick  :  cnt1 + tau_tick  ;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:219: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n                            quad_bit1[0] ? cnt1 - tau_tick  :  cnt1 + tau_tick  ;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:244: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'quad_bit2_next\' generates 3 bits.\n                                                                                             : ... In instance gen_mod2\n            quad_bit2  <=  quad_bit2_next      ;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:253: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                             : ... In instance gen_mod2\n    assign quad_bit2_next = ( cntu == phase_b ) ? 2\'b00  : quad_bit2 + (tau_tick&quad_add2) ;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:253: Operator AND expects 3 bits on the LHS, but LHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n    assign quad_bit2_next = ( cntu == phase_b ) ? 2\'b00  : quad_bit2 + (tau_tick&quad_add2) ;\n                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:253: Operator AND expects 3 bits on the RHS, but RHS\'s VARREF \'quad_add2\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n    assign quad_bit2_next = ( cntu == phase_b ) ? 2\'b00  : quad_bit2 + (tau_tick&quad_add2) ;\n                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:256: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s VARREF \'cnt2\' generates 9 bits.\n                                                                                             : ... In instance gen_mod2\n                            quad_add2    ? cnt2             :\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:257: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n                            quad_bit2[0] ? cnt2 - tau_tick  :  cnt2 + tau_tick  ;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:257: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n                            quad_bit2[0] ? cnt2 - tau_tick  :  cnt2 + tau_tick  ;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:282: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'quad_bit3_next\' generates 3 bits.\n                                                                                             : ... In instance gen_mod2\n            quad_bit3  <=  quad_bit3_next      ;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:291: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                             : ... In instance gen_mod2\n    assign quad_bit3_next = ( cntu == phase_b ) ? 2\'b00  : quad_bit3 + (tau_tick&quad_add3) ;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:291: Operator AND expects 3 bits on the LHS, but LHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n    assign quad_bit3_next = ( cntu == phase_b ) ? 2\'b00  : quad_bit3 + (tau_tick&quad_add3) ;\n                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:291: Operator AND expects 3 bits on the RHS, but RHS\'s VARREF \'quad_add3\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n    assign quad_bit3_next = ( cntu == phase_b ) ? 2\'b00  : quad_bit3 + (tau_tick&quad_add3) ;\n                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:293: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                             : ... In instance gen_mod2\n    assign cnt3_next      = ( cntu == phase_b )   ? 8\'b0   :\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:294: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s VARREF \'cnt3\' generates 8 bits.\n                                                                                             : ... In instance gen_mod2\n                            quad_add3    ? cnt3   :\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:295: Operator SUB expects 9 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n                            quad_bit3[0] ? cnt3 - tau_tick  :  cnt3 + tau_tick  ;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:295: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'tau_tick\' generates 1 bits.\n                                                                                             : ... In instance gen_mod2\n                            quad_bit3[0] ? cnt3 - tau_tick  :  cnt3 + tau_tick  ;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:339: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'cnt_next\' generates 11 bits.\n                                                                                             : ... In instance gen_mod2\n            clk_sq_cnt <= sqp_off ? cnt_next : clk_sq_cnt_next[32-1:0];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:356: Operator EQ expects 33 bits on the RHS, but RHS\'s SEL generates 32 bits.\n                                                                                             : ... In instance gen_mod2\n    assign clksq_equal_phas          = ( clk_sq_cnt_next==phas_sq[32-1:0] ) ;         \n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/gen_mod2.v:362: Operator COND expects 33 bits on the Conditional True, but Conditional True\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                             : ... In instance gen_mod2\n    assign clk_sq_cnt_next = clksq_gt_sqp              ? 32\'b0 : clk_sq_cnt + 32\'b001;\n                                                       ^\n%Error: Exiting due to 37 warning(s)\n'
module gen_mod2
(
    input clk,rst,
    input           [12-1:0] phase,
    input           [32-1:0] phase_sq,
    input           [14-1:0] hp,
    input           [32-1:0] sqp,
    output signed   [14-1:0] sin_ref,
    output signed   [14-1:0] cos_ref, cos_1f, cos_2f, cos_3f,
    output          [12-1:0] cntu_w,
    output                   sq_ref, sq_quad, sq_phas,
    output                   harmonic_trig, square_trig
);








    reg  [12-1:0] phase_b;
    wire          cnt_next_zero;




    reg  sq_ref_r;
    wire sq_ref_next;

    reg  sq_quad_r;
    wire sq_quad_next;

    reg  sq_phas_r;
    wire sq_phas_next;

    wire clksq_equal_sqp, sqp_off;
    wire phas_less_than_sqp,clksq_equal_sqp_half;

    reg  [32-1:0] clk_sq_cnt;
    wire [33-1:0] clk_sq_cnt_next;
    wire [32-1:0] sqp_half;
    wire [33-1:0] sqp_plus_half;
    wire [33-1:0] phas_sq;




    wire tau_tick;
    wire tau_tick_cnt_equal_hp;
    reg  [14-1:0] tau_tick_cnt;
    wire [15-1:0] tau_tick_cnt_next;


    reg signed [14-1:0] memory_sin_r [630-1:0];
    initial
    begin
        $readmemb("data_sin_ss.dat", memory_sin_r);
    end

    reg signed [14-1:0] memory_cos_r [630-1:0];
    initial
    begin
        $readmemb("data_cos_ss.dat", memory_cos_r);
    end



    reg signed [14-1:0] memory_cos1_r [630-1:0];
    initial
    begin
        $readmemb("data_cos_ss.dat", memory_cos1_r);
    end

    reg signed [14-1:0] memory_cos2_r [315-1:0];
    initial
    begin
        $readmemb("data_cos2_ss.dat", memory_cos2_r);
    end

    reg signed [14-1:0] memory_cos3_r [210-1:0];
    initial
    begin
        $readmemb("data_cos3_ss.dat", memory_cos3_r);
    end



    always @(posedge clk)
	if (rst)
		tau_tick_cnt <= 0;
	else
		tau_tick_cnt <= tau_tick_cnt_next[14-1:0];

    assign tau_tick_cnt_equal_hp = (tau_tick_cnt==hp) ;
    assign tau_tick_cnt_next = tau_tick_cnt_equal_hp ? 14'b0 : tau_tick_cnt + 14'b001;
    assign tau_tick = (hp==14'b0) ? 1'b1 : tau_tick_cnt_equal_hp ;









    reg  [10-1:0]  cnt ;
    wire [11-1:0]  cnt_next ;
    reg  [12-1:0]  cntu ;
    wire [13-1:0]  cntu_next ;

    assign cntu_w = cntu;

    reg  [ 2-1:0]  quad_bit ;
    wire [ 3-1:0]  quad_bit_next ;
    wire           quad_add;


    always @(posedge clk)
        if (rst)
        begin
            cnt           <=   10'b0    ;
            quad_bit      <=    2'b0    ;
            cntu          <=   12'b0    ;
            phase_b       <=   12'd2519 ;

        end
        else
        begin
            cnt       <=  cnt_next[10-1:0]  ;
            quad_bit  <=  quad_bit_next     ;
            cntu      <=  cntu_next[12-1:0] ;
            if(phase==12'b0)
                phase_b  <= 12'd2519 ;
            else
                phase_b  <= phase[12-1:0] - 12'b1 ;

        end

    assign quad_add       = (cnt==10'd629 & quad_bit==2'b00 ) |
                            (cnt==10'd000 & quad_bit==2'b01 ) |
                            (cnt==10'd629 & quad_bit==2'b10 ) |
                            (cnt==10'd000 & quad_bit==2'b11 )   ;

    assign quad_bit_next  = quad_add ? quad_bit + tau_tick : quad_bit ;

    assign cnt_next       = quad_add    ? cnt   :
                            quad_bit[0] ? cnt - tau_tick  :  cnt + tau_tick  ;
    assign cnt_next_zero  = (quad_bit==2'b11)&(cnt==10'd000)&tau_tick ;
    assign cntu_next      = cnt_next_zero ? 12'b0 :  cntu + tau_tick  ;

    assign  harmonic_trig = cnt_next_zero ;




    reg  [10-1:0]  cnt1 ;
    wire [11-1:0]  cnt1_next ;
    reg  [ 2-1:0]  quad_bit1 ;
    wire [ 3-1:0]  quad_bit1_next ;
    wire           quad_add1;


    always @(posedge clk)
        if (rst)
        begin
            cnt1      <=   10'b0   ;
            quad_bit1 <=    2'b0   ;
        end
        else
        begin
            cnt1       <=  cnt1_next[10-1:0] ;
            quad_bit1  <=  quad_bit1_next      ;
        end

    assign quad_add1      = (cnt1==10'd629 & quad_bit1==2'b00 ) |
                            (cnt1==10'd000 & quad_bit1==2'b01 ) |
                            (cnt1==10'd629 & quad_bit1==2'b10 ) |
                            (cnt1==10'd000 & quad_bit1==2'b11 )   ;


    assign quad_bit1_next = ( cntu == phase_b ) ? 2'b00  : quad_bit1 + (tau_tick&quad_add1) ;

    assign cnt1_next      = ( cntu == phase_b )? 10'b0   :
                            quad_add1    ? cnt1             :
                            quad_bit1[0] ? cnt1 - tau_tick  :  cnt1 + tau_tick  ;








    reg  [ 9-1:0]  cnt2 ;
    wire [10-1:0]  cnt2_next ;
    reg  [ 2-1:0]  quad_bit2 ;
    wire [ 3-1:0]  quad_bit2_next ;
    wire           quad_add2;


    always @(posedge clk)
        if (rst)
        begin
            cnt2      <=    9'b0   ;
            quad_bit2 <=    2'b0   ;
        end
        else
        begin
            cnt2       <=  cnt2_next[ 9-1:0] ;
            quad_bit2  <=  quad_bit2_next      ;
        end

    assign quad_add2      = (cnt2==9'd314 & quad_bit2==2'b00 ) |
                            (cnt2==9'd000 & quad_bit2==2'b01 ) |
                            (cnt2==9'd314 & quad_bit2==2'b10 ) |
                            (cnt2==9'd000 & quad_bit2==2'b11 )   ;


    assign quad_bit2_next = ( cntu == phase_b ) ? 2'b00  : quad_bit2 + (tau_tick&quad_add2) ;

    assign cnt2_next      = ( cntu == phase_b )? 10'b0   :
                            quad_add2    ? cnt2             :
                            quad_bit2[0] ? cnt2 - tau_tick  :  cnt2 + tau_tick  ;








    reg  [ 8-1:0]  cnt3 ;
    wire [ 9-1:0]  cnt3_next ;
    reg  [ 2-1:0]  quad_bit3 ;
    wire [ 3-1:0]  quad_bit3_next ;
    wire           quad_add3;


    always @(posedge clk)
        if (rst)
        begin
            cnt3      <=    8'b0   ;
            quad_bit3 <=    2'b0   ;
        end
        else
        begin
            cnt3       <=  cnt3_next[ 8-1:0] ;
            quad_bit3  <=  quad_bit3_next      ;
        end

    assign quad_add3      = (cnt3==8'd209 & quad_bit3==2'b00 ) |
                            (cnt3==8'd000 & quad_bit3==2'b01 ) |
                            (cnt3==8'd209 & quad_bit3==2'b10 ) |
                            (cnt3==8'd000 & quad_bit3==2'b11 )   ;


    assign quad_bit3_next = ( cntu == phase_b ) ? 2'b00  : quad_bit3 + (tau_tick&quad_add3) ;

    assign cnt3_next      = ( cntu == phase_b )? 8'b0   :
                            quad_add3    ? cnt3   :
                            quad_bit3[0] ? cnt3 - tau_tick  :  cnt3 + tau_tick  ;










    assign cos_ref  =  quad_bit[1]^quad_bit[0] ?  $signed(-memory_cos_r[cnt]) : memory_cos_r[cnt] ;
    assign sin_ref  =  quad_bit[1]             ?  $signed(-memory_sin_r[cnt]) : memory_sin_r[cnt] ;



    assign cos_1f   =  quad_bit1[1]^quad_bit1[0]   ?  $signed(-memory_cos1_r[cnt1] ) : memory_cos1_r[cnt1] ;
    assign cos_2f   =  quad_bit2[1]^quad_bit2[0]   ?  $signed(-memory_cos2_r[cnt2])  : memory_cos2_r[cnt2] ;
    assign cos_3f   =  quad_bit3[1]^quad_bit3[0]   ?  $signed(-memory_cos3_r[cnt3])  : memory_cos3_r[cnt3] ;




    always @(posedge clk)
	if (rst)
        begin
            clk_sq_cnt <= 0;
            sq_ref_r   <= 0;
            sq_quad_r  <= 0;
            sq_phas_r  <= 0;
        end
	else
        begin
            clk_sq_cnt <= sqp_off ? cnt_next : clk_sq_cnt_next[32-1:0];
            sq_ref_r   <= sq_ref_next ;
            sq_quad_r  <= sq_quad_next;
            sq_phas_r  <= sq_phas_next;
        end




    assign sqp_half                  = sqp >> 1'b1 ;
    assign sqp_plus_half             = sqp + sqp_half ;
    assign phas_sq                   = phas_less_than_sqp ? {1'b0,phase_sq} : (phase_sq - sqp) ;

    assign clksq_equal_sqp           = ( clk_sq_cnt==sqp   );
    assign clksq_gt_sqp              = ( clk_sq_cnt>=sqp   );

    assign clksq_equal_sqp_half      = ( clk_sq_cnt==sqp_half ) ;
    assign clksq_equal_phas          = ( clk_sq_cnt_next==phas_sq[32-1:0] ) ;

    assign sqp_off                   = ( sqp==32'b00       );
    assign phas_less_than_sqp        = ( phase_sq < sqp + 1'b1 );


    assign clk_sq_cnt_next = clksq_gt_sqp              ? 32'b0 : clk_sq_cnt + 32'b001;
    assign sq_ref_next     = clksq_equal_sqp           ? ~sq_ref_r : sq_ref_r  ;
    assign sq_quad_next    = clksq_equal_sqp_half      ?  sq_ref_r : sq_quad_r ;
    assign sq_phas_next    = clksq_equal_phas          ? sq_ref_next^(~phas_less_than_sqp) : sq_phas_r ;


    assign sq_ref  = sqp_off ? (~cos_ref[13])  : sq_ref_r ;
    assign sq_quad = sqp_off ? (~sin_ref[13])  : sq_quad_r ;
    assign sq_phas = sqp_off ? (~cos_1f[13] )  : sq_phas_r ;


    assign square_trig = clksq_equal_sqp_half & sq_ref ;




endmodule
module gen_mod2
(
    input clk,rst,
    input           [12-1:0] phase,
    input           [32-1:0] phase_sq,
    input           [14-1:0] hp,
    input           [32-1:0] sqp,
    output signed   [14-1:0] sin_ref,
    output signed   [14-1:0] cos_ref, cos_1f, cos_2f, cos_3f,
    output          [12-1:0] cntu_w,
    output                   sq_ref, sq_quad, sq_phas,
    output                   harmonic_trig, square_trig
);









    reg  [12-1:0] phase_b;
    wire          cnt_next_zero;




    reg  sq_ref_r;
    wire sq_ref_next;

    reg  sq_quad_r;
    wire sq_quad_next;

    reg  sq_phas_r;
    wire sq_phas_next;

    wire clksq_equal_sqp, sqp_off;
    wire phas_less_than_sqp,clksq_equal_sqp_half;

    reg  [32-1:0] clk_sq_cnt;
    wire [33-1:0] clk_sq_cnt_next;
    wire [32-1:0] sqp_half;
    wire [33-1:0] sqp_plus_half;
    wire [33-1:0] phas_sq;




    wire tau_tick;
    wire tau_tick_cnt_equal_hp;
    reg  [14-1:0] tau_tick_cnt;
    wire [15-1:0] tau_tick_cnt_next;


    reg signed [14-1:0] memory_sin_r [630-1:0];
    initial
    begin
        $readmemb("data_sin_ss.dat", memory_sin_r);
    end

    reg signed [14-1:0] memory_cos_r [630-1:0];
    initial
    begin
        $readmemb("data_cos_ss.dat", memory_cos_r);
    end



    reg signed [14-1:0] memory_cos1_r [630-1:0];
    initial
    begin
        $readmemb("data_cos_ss.dat", memory_cos1_r);
    end

    reg signed [14-1:0] memory_cos2_r [315-1:0];
    initial
    begin
        $readmemb("data_cos2_ss.dat", memory_cos2_r);
    end

    reg signed [14-1:0] memory_cos3_r [210-1:0];
    initial
    begin
        $readmemb("data_cos3_ss.dat", memory_cos3_r);
    end



    always @(posedge clk)
	if (rst)
		tau_tick_cnt <= 0;
	else
		tau_tick_cnt <= tau_tick_cnt_next[14-1:0];

    assign tau_tick_cnt_equal_hp = (tau_tick_cnt==hp) ;
    assign tau_tick_cnt_next = tau_tick_cnt_equal_hp ? 14'b0 : tau_tick_cnt + 14'b001;
    assign tau_tick = (hp==14'b0) ? 1'b1 : tau_tick_cnt_equal_hp ;









    reg  [10-1:0]  cnt ;
    wire [11-1:0]  cnt_next ;
    reg  [12-1:0]  cntu ;
    wire [13-1:0]  cntu_next ;

    assign cntu_w = cntu;

    reg  [ 2-1:0]  quad_bit ;
    wire [ 3-1:0]  quad_bit_next ;
    wire           quad_add;


    always @(posedge clk)
        if (rst)
        begin
            cnt           <=   10'b0    ;
            quad_bit      <=    2'b0    ;
            cntu          <=   12'b0    ;
            phase_b       <=   12'd2519 ;

        end
        else
        begin
            cnt       <=  cnt_next[10-1:0]  ;
            quad_bit  <=  quad_bit_next     ;
            cntu      <=  cntu_next[12-1:0] ;
            if(phase==12'b0)
                phase_b  <= 12'd2519 ;
            else
                phase_b  <= phase[12-1:0] - 12'b1 ;

        end

    assign quad_add       = (cnt==10'd629 & quad_bit==2'b00 ) |
                            (cnt==10'd000 & quad_bit==2'b01 ) |
                            (cnt==10'd629 & quad_bit==2'b10 ) |
                            (cnt==10'd000 & quad_bit==2'b11 )   ;

    assign quad_bit_next  = quad_add ? quad_bit + tau_tick : quad_bit ;

    assign cnt_next       = quad_add    ? cnt   :
                            quad_bit[0] ? cnt - tau_tick  :  cnt + tau_tick  ;
    assign cnt_next_zero  = (quad_bit==2'b11)&(cnt==10'd000)&tau_tick ;
    assign cntu_next      = cnt_next_zero ? 12'b0 :  cntu + tau_tick  ;

    assign  harmonic_trig = cnt_next_zero ;




    reg  [10-1:0]  cnt1 ;
    wire [11-1:0]  cnt1_next ;
    reg  [ 2-1:0]  quad_bit1 ;
    wire [ 3-1:0]  quad_bit1_next ;
    wire           quad_add1;


    always @(posedge clk)
        if (rst)
        begin
            cnt1      <=   10'b0   ;
            quad_bit1 <=    2'b0   ;
        end
        else
        begin
            cnt1       <=  cnt1_next[10-1:0] ;
            quad_bit1  <=  quad_bit1_next      ;
        end

    assign quad_add1      = (cnt1==10'd629 & quad_bit1==2'b00 ) |
                            (cnt1==10'd000 & quad_bit1==2'b01 ) |
                            (cnt1==10'd629 & quad_bit1==2'b10 ) |
                            (cnt1==10'd000 & quad_bit1==2'b11 )   ;


    assign quad_bit1_next = ( cntu == phase_b ) ? 2'b00  : quad_bit1 + (tau_tick&quad_add1) ;

    assign cnt1_next      = ( cntu == phase_b )? 10'b0   :
                            quad_add1    ? cnt1             :
                            quad_bit1[0] ? cnt1 - tau_tick  :  cnt1 + tau_tick  ;








    reg  [ 9-1:0]  cnt2 ;
    wire [10-1:0]  cnt2_next ;
    reg  [ 2-1:0]  quad_bit2 ;
    wire [ 3-1:0]  quad_bit2_next ;
    wire           quad_add2;


    always @(posedge clk)
        if (rst)
        begin
            cnt2      <=    9'b0   ;
            quad_bit2 <=    2'b0   ;
        end
        else
        begin
            cnt2       <=  cnt2_next[ 9-1:0] ;
            quad_bit2  <=  quad_bit2_next      ;
        end

    assign quad_add2      = (cnt2==9'd314 & quad_bit2==2'b00 ) |
                            (cnt2==9'd000 & quad_bit2==2'b01 ) |
                            (cnt2==9'd314 & quad_bit2==2'b10 ) |
                            (cnt2==9'd000 & quad_bit2==2'b11 )   ;


    assign quad_bit2_next = ( cntu == phase_b ) ? 2'b00  : quad_bit2 + (tau_tick&quad_add2) ;

    assign cnt2_next      = ( cntu == phase_b )? 10'b0   :
                            quad_add2    ? cnt2             :
                            quad_bit2[0] ? cnt2 - tau_tick  :  cnt2 + tau_tick  ;








    reg  [ 8-1:0]  cnt3 ;
    wire [ 9-1:0]  cnt3_next ;
    reg  [ 2-1:0]  quad_bit3 ;
    wire [ 3-1:0]  quad_bit3_next ;
    wire           quad_add3;


    always @(posedge clk)
        if (rst)
        begin
            cnt3      <=    8'b0   ;
            quad_bit3 <=    2'b0   ;
        end
        else
        begin
            cnt3       <=  cnt3_next[ 8-1:0] ;
            quad_bit3  <=  quad_bit3_next      ;
        end

    assign quad_add3      = (cnt3==8'd209 & quad_bit3==2'b00 ) |
                            (cnt3==8'd000 & quad_bit3==2'b01 ) |
                            (cnt3==8'd209 & quad_bit3==2'b10 ) |
                            (cnt3==8'd000 & quad_bit3==2'b11 )   ;


    assign quad_bit3_next = ( cntu == phase_b ) ? 2'b00  : quad_bit3 + (tau_tick&quad_add3) ;

    assign cnt3_next      = ( cntu == phase_b )? 8'b0   :
                            quad_add3    ? cnt3   :
                            quad_bit3[0] ? cnt3 - tau_tick  :  cnt3 + tau_tick  ;










    assign cos_ref  =  quad_bit[1]^quad_bit[0] ?  $signed(-memory_cos_r[cnt]) : memory_cos_r[cnt] ;
    assign sin_ref  =  quad_bit[1]             ?  $signed(-memory_sin_r[cnt]) : memory_sin_r[cnt] ;



    assign cos_1f   =  quad_bit1[1]^quad_bit1[0]   ?  $signed(-memory_cos1_r[cnt1] ) : memory_cos1_r[cnt1] ;
    assign cos_2f   =  quad_bit2[1]^quad_bit2[0]   ?  $signed(-memory_cos2_r[cnt2])  : memory_cos2_r[cnt2] ;
    assign cos_3f   =  quad_bit3[1]^quad_bit3[0]   ?  $signed(-memory_cos3_r[cnt3])  : memory_cos3_r[cnt3] ;




    always @(posedge clk)
	if (rst)
        begin
            clk_sq_cnt <= 0;
            sq_ref_r   <= 0;
            sq_quad_r  <= 0;
            sq_phas_r  <= 0;
        end
	else
        begin
            clk_sq_cnt <= sqp_off ? cnt_next : clk_sq_cnt_next[32-1:0];
            sq_ref_r   <= sq_ref_next ;
            sq_quad_r  <= sq_quad_next;
            sq_phas_r  <= sq_phas_next;
        end




    assign sqp_half                  = sqp >> 1'b1 ;
    assign sqp_plus_half             = sqp + sqp_half ;
    assign phas_sq                   = phas_less_than_sqp ? {1'b0,phase_sq} : (phase_sq - sqp) ;

    assign clksq_equal_sqp           = ( clk_sq_cnt==sqp   );
    assign clksq_gt_sqp              = ( clk_sq_cnt>=sqp   );

    assign clksq_equal_sqp_half      = ( clk_sq_cnt==sqp_half ) ;
    assign clksq_equal_phas          = ( clk_sq_cnt_next==phas_sq[32-1:0] ) ;

    assign sqp_off                   = ( sqp==32'b00       );
    assign phas_less_than_sqp        = ( phase_sq < sqp + 1'b1 );


    assign clk_sq_cnt_next = clksq_gt_sqp              ? 32'b0 : clk_sq_cnt + 32'b001;
    assign sq_ref_next     = clksq_equal_sqp           ? ~sq_ref_r : sq_ref_r  ;
    assign sq_quad_next    = clksq_equal_sqp_half      ?  sq_ref_r : sq_quad_r ;
    assign sq_phas_next    = clksq_equal_phas          ? sq_ref_next^(~phas_less_than_sqp) : sq_phas_r ;


    assign sq_ref  = sqp_off ? (~cos_ref[13])  : sq_ref_r ;
    assign sq_quad = sqp_off ? (~sin_ref[13])  : sq_quad_r ;
    assign sq_phas = sqp_off ? (~cos_1f[13] )  : sq_phas_r ;


    assign square_trig = clksq_equal_sqp_half & sq_ref ;




endmodule