data/full_repos/permissive/109846502/test.v
data/verilator_xmls/1f90e7cb-155d-478f-b736-2026ab2a3170.xml
module test(
input clk,
input rst,
output reg out
    );
	 
always @(posedge clk, posedge rst)
	if(rst)
		out <= 1'b0;
	else
		out <= ~out;


endmodule
module test(
input clk,
input rst,
output reg out
    );

	 
always @(posedge clk, posedge rst)
	if(rst)
		out <= 1'b0;
	else
		out <= ~out;


endmodule