data/full_repos/permissive/189158787/div/posit_div_8bit_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/189158787/div/posit_div_8bit_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #100 i=0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/189158787/div/posit_div_8bit_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #20 start = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189158787/div/posit_div_8bit_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n                #652890 start = 0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/189158787/div/posit_div_8bit_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189158787/div/posit_div_8bit_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk=~clk;\n        ^\n%Error: data/full_repos/permissive/189158787/div/posit_div_8bit_tb.v:28: Cannot find file containing module: \'posit_div\'\nposit_div #(.N(N), .es(es), .N_Iter(N_Iter)) uut (in1, in2, start, out, inf, zero, done);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/189158787/div,data/full_repos/permissive/189158787/posit_div\n             data/full_repos/permissive/189158787/div,data/full_repos/permissive/189158787/posit_div.v\n             data/full_repos/permissive/189158787/div,data/full_repos/permissive/189158787/posit_div.sv\n             posit_div\n             posit_div.v\n             posit_div.sv\n             obj_dir/posit_div\n             obj_dir/posit_div.v\n             obj_dir/posit_div.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function [31:0] log2;
input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction
function [31:0] log2;

input reg [31:0] value;
	begin
	value = value-1;
	for (log2=0; value>0; log2=log2+1)
        	value = value>>1;
      	end
endfunction