data/full_repos/permissive/155004694/sim/alu_sim.v
 line:175: before: "tests_passed"
1: b'%Error: data/full_repos/permissive/155004694/sim/alu_sim.v:3: Cannot find include file: src/alu.v\n`include "src/alu.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/155004694/sim,data/full_repos/permissive/155004694/src/alu.v\n             data/full_repos/permissive/155004694/sim,data/full_repos/permissive/155004694/src/alu.v.v\n             data/full_repos/permissive/155004694/sim,data/full_repos/permissive/155004694/src/alu.v.sv\n             src/alu.v\n             src/alu.v.v\n             src/alu.v.sv\n             obj_dir/src/alu.v\n             obj_dir/src/alu.v.v\n             obj_dir/src/alu.v.sv\n%Error: data/full_repos/permissive/155004694/sim/alu_sim.v:33: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/155004694/sim/alu_sim.v:34: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:100: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:117: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:131: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:138: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:145: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:154: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:161: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:168: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:175: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:182: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:189: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:197: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:204: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:211: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:222: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:234: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:246: Unsupported: Ignoring delay on this delayed statement.\n            #1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:258: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:265: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:272: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:281: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:288: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/155004694/sim/alu_sim.v:295: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Error: Exiting due to 3 error(s), 33 warning(s)\n'
module alu_sim();

    reg [31:0] A;
    reg [31:0] B;
    reg [2:0] ctrl;

    wire [31:0] out;

    reg signed [31:0] Asigned;
    reg [31:0] temp;

    alu dut(
        .A(A),
        .B(B),
        .ctrl(ctrl),
        .out(out)
    );

    initial begin

        int tests_passed;
        int tests_total;

        tests_passed = 0;
        tests_total = 0;

        $dumpfile("test.vcd");
        $dumpvars;


        A = 'd0;
        B = 'd0;
        ctrl = 'd0;

        #1
        `CHECK(out, 'd0);

        A = 'd3;
        B = 'd8;
        ctrl = 'd0;

        #1
        `CHECK(out, 'd11);

        A = 'hFFFFFFFE;
        B = 'hFFFFFFFF;
        ctrl = 'd0;

        #1
        `CHECK(out, 'hFFFFFFFD);


        A = 'hAC98BC63;
        B = 'd0;
        ctrl = 'd1;

        #1
        `CHECK(out, 'hAC98BC63);

        A = 'hAC98BC63;
        B = 'd1;
        ctrl = 'd1;

        #1
        `CHECK(out, 'h593178c6);

        A = 'hAC98BC63;
        B = 'd2;
        ctrl = 'd1;

        #1
        `CHECK(out, 'hb262f18c);

        A = 'hAC98BC63;
        B = 'd3;
        ctrl = 'd1;

        #1
        `CHECK(out, 'h64c5e318);

        A = 'hAC98BC63;
        B = 'd4;
        ctrl = 'd1;

        #1
        `CHECK(out, 'hc98bc630);

        for (int i = 0; i < 32; i++) begin
            
            A = 'hAC98BC63;
            B = i;
            ctrl = 'd1;

            #1
            `CHECK(out, A << i);
        end



        A = 'd5;
        B = 'd8;
        ctrl = 'd2;

        #1
        `CHECK(out, 'd1);

        A = 'd9;
        B = 'd7;
        ctrl = 'd2;

        #1
        `CHECK(out, 'd0);

        A = -'d9;
        B = 'd1;
        ctrl = 'd2;

        #1
        `CHECK(out, 'd1);

        A = -'d5;
        B = -'d6;
        ctrl = 'd2;

        #1
        `CHECK(out, 'd0);

        A = -'d8;
        B = -'d2;
        ctrl = 'd2;

        #1
        `CHECK(out, 'd1);

        A = 'd2;
        B = -'d10;
        ctrl = 'd2;

        #1
        `CHECK(out, 'd0);
        


        A = 'd5;
        B = 'd8;
        ctrl = 'd3;

        #1
        `CHECK(out, 'd1);

        A = 'd9;
        B = 'd7;
        ctrl = 'd3;

        #1
        `CHECK(out, 'd0);

        A = -'d9;
        B = 'd1;
        ctrl = 'd3;

        #1
        `CHECK(out, 'd0);

        A = -'d5;
        B = -'d6;
        ctrl = 'd3;

        #1
        `CHECK(out, 'd0);

        A = -'d8;
        B = -'d2;
        ctrl = 'd3;

        #1
        `CHECK(out, 'd1);

        A = 'd2;
        B = -'d10;
        ctrl = 'd3;

        #1
        `CHECK(out, 'd1);


        A = 'hFFA5C600;
        B = 'hF0F0F0F0;
        ctrl = 'd4;

        #1
        `CHECK(out, 'h0F5536F0);

        A = 'hA5BC9B0E;
        B = 'hA5BC9B0E;
        ctrl = 'd4;

        #1
        `CHECK(out, 'd0);

        A = 'hA5A5A5A5;
        B = 'h5A5A5A5A;
        ctrl = 'd4;

        #1
        `CHECK(out, 'hFFFFFFFF);



        for (int i = 0; i < 32; i++) begin

            A = 'hAC98BC63;
            B = i;
            ctrl = 'd5;

            #1
            `CHECK(out, A >> i);
        end



        for (int i = 0; i < 32; i++) begin

            A = 'hAC98BC63;
            B = i | 'h400;
            ctrl = 'd5;

            #1
            Asigned = A;
            temp = Asigned >>> i;
            `CHECK(out, temp);
        end

        for (int i = 0; i < 32; i++) begin

            A = 'h2C98BC63;
            B = i | 'h400;
            ctrl = 'd5;

            #1
            Asigned = A;
            temp = Asigned >>> i;
            `CHECK(out, temp);
        end



        A = 'hFC84723B;
        B = 'hB97D3CE2;
        ctrl = 'd6;

        #1
        `CHECK(out, 'hFDFD7EFB);

        A = 'h00000000;
        B = 'hABCD4321;
        ctrl = 'd6;

        #1
        `CHECK(out, 'hABCD4321);

        A = 'hFFFFFFFF;
        B = 'h1234ABCD;
        ctrl = 'd6;

        #1
        `CHECK(out, 'hFFFFFFFF);



        A = 'hFC4592BE;
        B = 'hBEA65CA9;
        ctrl = 'd7;

        #1
        `CHECK(out, 'hBC0410A8);

        A = 'hFFFFFFFF;
        B = 'h1234CDEF;
        ctrl = 'd7;

        #1
        `CHECK(out, 'h1234CDEF);

        A = 'h00000000;
        B = 'h5642BDEA;
        ctrl = 'd7;

        #1
        `CHECK(out, 'h00000000);


        $display("%0d/%0d checks passed", tests_passed, tests_total);

        $finish;
    end
endmodule
module alu_sim();


    reg [31:0] A;
    reg [31:0] B;
    reg [2:0] ctrl;

    wire [31:0] out;

    reg signed [31:0] Asigned;
    reg [31:0] temp;

    alu dut(
        .A(A),
        .B(B),
        .ctrl(ctrl),
        .out(out)
    );

    initial begin

        int tests_passed;
        int tests_total;

        tests_passed = 0;
        tests_total = 0;

        $dumpfile("test.vcd");
        $dumpvars;


        A = 'd0;
        B = 'd0;
        ctrl = 'd0;

        #1
        `CHECK(out, 'd0);

        A = 'd3;
        B = 'd8;
        ctrl = 'd0;

        #1
        `CHECK(out, 'd11);

        A = 'hFFFFFFFE;
        B = 'hFFFFFFFF;
        ctrl = 'd0;

        #1
        `CHECK(out, 'hFFFFFFFD);


        A = 'hAC98BC63;
        B = 'd0;
        ctrl = 'd1;

        #1
        `CHECK(out, 'hAC98BC63);

        A = 'hAC98BC63;
        B = 'd1;
        ctrl = 'd1;

        #1
        `CHECK(out, 'h593178c6);

        A = 'hAC98BC63;
        B = 'd2;
        ctrl = 'd1;

        #1
        `CHECK(out, 'hb262f18c);

        A = 'hAC98BC63;
        B = 'd3;
        ctrl = 'd1;

        #1
        `CHECK(out, 'h64c5e318);

        A = 'hAC98BC63;
        B = 'd4;
        ctrl = 'd1;

        #1
        `CHECK(out, 'hc98bc630);

        for (int i = 0; i < 32; i++) begin
            
            A = 'hAC98BC63;
            B = i;
            ctrl = 'd1;

            #1
            `CHECK(out, A << i);
        end



        A = 'd5;
        B = 'd8;
        ctrl = 'd2;

        #1
        `CHECK(out, 'd1);

        A = 'd9;
        B = 'd7;
        ctrl = 'd2;

        #1
        `CHECK(out, 'd0);

        A = -'d9;
        B = 'd1;
        ctrl = 'd2;

        #1
        `CHECK(out, 'd1);

        A = -'d5;
        B = -'d6;
        ctrl = 'd2;

        #1
        `CHECK(out, 'd0);

        A = -'d8;
        B = -'d2;
        ctrl = 'd2;

        #1
        `CHECK(out, 'd1);

        A = 'd2;
        B = -'d10;
        ctrl = 'd2;

        #1
        `CHECK(out, 'd0);
        


        A = 'd5;
        B = 'd8;
        ctrl = 'd3;

        #1
        `CHECK(out, 'd1);

        A = 'd9;
        B = 'd7;
        ctrl = 'd3;

        #1
        `CHECK(out, 'd0);

        A = -'d9;
        B = 'd1;
        ctrl = 'd3;

        #1
        `CHECK(out, 'd0);

        A = -'d5;
        B = -'d6;
        ctrl = 'd3;

        #1
        `CHECK(out, 'd0);

        A = -'d8;
        B = -'d2;
        ctrl = 'd3;

        #1
        `CHECK(out, 'd1);

        A = 'd2;
        B = -'d10;
        ctrl = 'd3;

        #1
        `CHECK(out, 'd1);


        A = 'hFFA5C600;
        B = 'hF0F0F0F0;
        ctrl = 'd4;

        #1
        `CHECK(out, 'h0F5536F0);

        A = 'hA5BC9B0E;
        B = 'hA5BC9B0E;
        ctrl = 'd4;

        #1
        `CHECK(out, 'd0);

        A = 'hA5A5A5A5;
        B = 'h5A5A5A5A;
        ctrl = 'd4;

        #1
        `CHECK(out, 'hFFFFFFFF);



        for (int i = 0; i < 32; i++) begin

            A = 'hAC98BC63;
            B = i;
            ctrl = 'd5;

            #1
            `CHECK(out, A >> i);
        end



        for (int i = 0; i < 32; i++) begin

            A = 'hAC98BC63;
            B = i | 'h400;
            ctrl = 'd5;

            #1
            Asigned = A;
            temp = Asigned >>> i;
            `CHECK(out, temp);
        end

        for (int i = 0; i < 32; i++) begin

            A = 'h2C98BC63;
            B = i | 'h400;
            ctrl = 'd5;

            #1
            Asigned = A;
            temp = Asigned >>> i;
            `CHECK(out, temp);
        end



        A = 'hFC84723B;
        B = 'hB97D3CE2;
        ctrl = 'd6;

        #1
        `CHECK(out, 'hFDFD7EFB);

        A = 'h00000000;
        B = 'hABCD4321;
        ctrl = 'd6;

        #1
        `CHECK(out, 'hABCD4321);

        A = 'hFFFFFFFF;
        B = 'h1234ABCD;
        ctrl = 'd6;

        #1
        `CHECK(out, 'hFFFFFFFF);



        A = 'hFC4592BE;
        B = 'hBEA65CA9;
        ctrl = 'd7;

        #1
        `CHECK(out, 'hBC0410A8);

        A = 'hFFFFFFFF;
        B = 'h1234CDEF;
        ctrl = 'd7;

        #1
        `CHECK(out, 'h1234CDEF);

        A = 'h00000000;
        B = 'h5642BDEA;
        ctrl = 'd7;

        #1
        `CHECK(out, 'h00000000);


        $display("%0d/%0d checks passed", tests_passed, tests_total);

        $finish;
    end
endmodule