data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:165: Unsupported: Ignoring delay on this delayed statement.\n      #RESET_TIME;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:170: Unsupported: Ignoring delay on this delayed statement.\n      #CLOCK_HALF_PERIOD;\n      ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:214: Unsupported: wait statements\n  wait (reset_n == 1);\n  ^~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:215: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:222: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:226: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:229: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:231: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:235: syntax error, unexpected \'@\'\n  repeat (DEPTH-2) @(posedge clk);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:236: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:240: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:241: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:247: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:248: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:254: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:255: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:259: syntax error, unexpected \'@\'\n  repeat (DEPTH-2) @(posedge clk);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:260: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:264: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:265: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:281: syntax error, unexpected \'@\'\n     @(posedge clk);\n     ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:282: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n     in_valid  <= ($random(23) && 1);\n                   ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:282: ../V3Ast.cpp:358: Null item passed to setOp1p\n     in_valid  <= ($random(23) && 1);\n                               ^~\n                        ... See the manual and https://verilator.org for more assistance.\n'
module sonic_vc_timing_adapter_fifo (
   output reg  [ 3: 0] fill_level ,
    

      input              clk,
      input              reset_n,

      output reg         in_ready,
      input              in_valid,
      input      [132: 0] in_data,

      input              out_ready,
      output reg         out_valid,
      output reg [132: 0] out_data
);




   parameter DEPTH = 8;
   parameter DATA_WIDTH = 133;
   parameter ADDR_WIDTH = 3;
	       



   reg [ADDR_WIDTH-1:0] wr_addr;
   reg [ADDR_WIDTH-1:0] rd_addr;
   reg [ADDR_WIDTH-1:0] next_wr_addr;
   reg [ADDR_WIDTH-1:0] next_rd_addr;
   reg [ADDR_WIDTH-1:0] mem_rd_addr;
   reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];
   reg 			empty;
   reg 			full;
   reg [0:0] out_ready_vector;
   



   always @* begin

      out_ready_vector[0] = out_ready;
      in_ready  = !full;
      next_wr_addr = wr_addr + 1'b1;
      next_rd_addr = rd_addr + 1'b1;
	    fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
	    fill_level[ADDR_WIDTH] = 0;
	    if (full)
	       fill_level = DEPTH[ADDR_WIDTH:0];
   end
   



   always @ (negedge reset_n, posedge clk) begin
      if (!reset_n) begin
	 wr_addr  <= 0;
	 rd_addr  <= 0;
	 empty    <= 1;
	 rd_addr  <= 0;
	 full <= 0;
	 out_valid <= 0;
      end else begin
	 out_valid <= !empty;
	 if (in_ready && in_valid) begin
	    wr_addr <= next_wr_addr;
	    empty   <= 0;
	    if (next_wr_addr == rd_addr)
	      full <= 1;
	 end
	 
	 if (out_ready_vector[0] && out_valid) begin
	    rd_addr <= next_rd_addr;
	    full    <= 0;
	    if (next_rd_addr == wr_addr) begin
	       empty <= 1;
	       out_valid <= 0;
	    end
	 end
	 
	 if (out_ready_vector[0] && out_valid && in_ready && in_valid) begin
	    full  <= full;
	    empty <= empty;
	 end
      end
   end
   
   always @* begin
      mem_rd_addr = rd_addr;
      if (out_ready && out_valid) begin
	 mem_rd_addr = next_rd_addr;
      end
   end
   




   always @ (posedge clk) begin
      if (in_ready && in_valid)
         mem[wr_addr] <= in_data;
      out_data <= mem[mem_rd_addr];
   end
   
endmodule
module sonic_vc_timing_adapter_fifo (
   output reg  [ 3: 0] fill_level ,
    

      input              clk,
      input              reset_n,

      output reg         in_ready,
      input              in_valid,
      input      [132: 0] in_data,

      input              out_ready,
      output reg         out_valid,
      output reg [132: 0] out_data
);





   parameter DEPTH = 8;
   parameter DATA_WIDTH = 133;
   parameter ADDR_WIDTH = 3;
	       



   reg [ADDR_WIDTH-1:0] wr_addr;
   reg [ADDR_WIDTH-1:0] rd_addr;
   reg [ADDR_WIDTH-1:0] next_wr_addr;
   reg [ADDR_WIDTH-1:0] next_rd_addr;
   reg [ADDR_WIDTH-1:0] mem_rd_addr;
   reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];
   reg 			empty;
   reg 			full;
   reg [0:0] out_ready_vector;
   



   always @* begin

      out_ready_vector[0] = out_ready;
      in_ready  = !full;
      next_wr_addr = wr_addr + 1'b1;
      next_rd_addr = rd_addr + 1'b1;
	    fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
	    fill_level[ADDR_WIDTH] = 0;
	    if (full)
	       fill_level = DEPTH[ADDR_WIDTH:0];
   end
   



   always @ (negedge reset_n, posedge clk) begin
      if (!reset_n) begin
	 wr_addr  <= 0;
	 rd_addr  <= 0;
	 empty    <= 1;
	 rd_addr  <= 0;
	 full <= 0;
	 out_valid <= 0;
      end else begin
	 out_valid <= !empty;
	 if (in_ready && in_valid) begin
	    wr_addr <= next_wr_addr;
	    empty   <= 0;
	    if (next_wr_addr == rd_addr)
	      full <= 1;
	 end
	 
	 if (out_ready_vector[0] && out_valid) begin
	    rd_addr <= next_rd_addr;
	    full    <= 0;
	    if (next_rd_addr == wr_addr) begin
	       empty <= 1;
	       out_valid <= 0;
	    end
	 end
	 
	 if (out_ready_vector[0] && out_valid && in_ready && in_valid) begin
	    full  <= full;
	    empty <= empty;
	 end
      end
   end
   
   always @* begin
      mem_rd_addr = rd_addr;
      if (out_ready && out_valid) begin
	 mem_rd_addr = next_rd_addr;
      end
   end
   




   always @ (posedge clk) begin
      if (in_ready && in_valid)
         mem[wr_addr] <= in_data;
      out_data <= mem[mem_rd_addr];
   end
   
endmodule