data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v
 line:46: before: "("
1: b'%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:1: Cannot find include file: definitions.v\n`include"definitions.v" \n        ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/02-shift_register,data/full_repos/permissive/129155059/definitions.v\n             data/full_repos/permissive/129155059/02-shift_register,data/full_repos/permissive/129155059/definitions.v.v\n             data/full_repos/permissive/129155059/02-shift_register,data/full_repos/permissive/129155059/definitions.v.sv\n             definitions.v\n             definitions.v.v\n             definitions.v.sv\n             obj_dir/definitions.v\n             obj_dir/definitions.v.v\n             obj_dir/definitions.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n      repeat(4) #5 CLK = ~CLK;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n      forever #5 CLK = ~CLK;\n              ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:43: syntax error, unexpected \'@\'\n      @(posedge ENB);\n      ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:45: Define or directive not defined: \'`LOAD\'\n      MODO = `LOAD;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `LOAD;\n                  ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:48: syntax error, unexpected \'@\'\n      repeat(6) @(posedge CLK);\n                ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:52: Define or directive not defined: \'`PUSH\'\n      MODO = `PUSH;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:52: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `PUSH;\n                  ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:53: syntax error, unexpected \'@\'\n      repeat(34) @(posedge CLK);\n                 ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:57: Define or directive not defined: \'`PUSH\'\n      MODO = `PUSH;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:57: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `PUSH;\n                  ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:58: syntax error, unexpected \'@\'\n      repeat(34) @(posedge CLK);\n                 ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:61: Define or directive not defined: \'`LOAD\'\n      MODO = `LOAD;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:61: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `LOAD;\n                  ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:62: syntax error, unexpected \'@\'\n      repeat(6) @(posedge CLK);\n                ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:65: Define or directive not defined: \'`CYCLE\'\n      MODO = `CYCLE;\n             ^~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `CYCLE;\n                   ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:66: syntax error, unexpected \'@\'\n      repeat(34) @(posedge CLK);\n                 ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:69: Define or directive not defined: \'`LOAD\'\n      MODO = `LOAD;\n             ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:69: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `LOAD;\n                  ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:70: syntax error, unexpected \'@\'\n      repeat(6) @(posedge CLK);\n                ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:73: Define or directive not defined: \'`CYCLE\'\n      MODO = `CYCLE;\n             ^~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:73: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      MODO = `CYCLE;\n                   ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:74: syntax error, unexpected \'@\'\n      repeat(34) @(posedge CLK);\n                 ^\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:79: Unsupported or unknown PLI call: $monitor\n        $monitor("At time %t, Q = %h (%0d), S_OUT = %h (%0d)",\n        ^~~~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:83: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile ("registro32v2.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/registro32v2_tb.v:84: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(1, registro32v2_tb);\n        ^~~~~~~~~\n%Error: Exiting due to 26 error(s), 2 warning(s)\n'
module registro32v2_tb();


  parameter  WIDTH = 32;


    reg ENB;
    reg DIR;
    reg S_IN;
    reg [1 : 0]         MODO;
    reg [WIDTH - 1 : 0] D;
    reg CLK;

    wire [WIDTH - 1 : 0] Q;
    wire                 S_OUT;


    registro #(WIDTH) r0
    (
      .Q(Q),
      .S_OUT(S_OUT),
      .D(D),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_IN)
      );



    initial begin
      CLK = 1'b0;
      ENB = 1'b0;
      repeat(4) #5 CLK = ~CLK;
      ENB = 1'b1;
      forever #5 CLK = ~CLK;
    end

    initial begin

      @(posedge ENB);
      D = 32'b11110000100111011111000010011101;
      MODO = `LOAD;
      S_IN = 1'b0;
      DIR = 0;
      repeat(6) @(posedge CLK);

      S_IN = 1'b0;
      DIR = 0;
      MODO = `PUSH;
      repeat(34) @(posedge CLK);

      S_IN = 1'b1;
      DIR = 1;
      MODO = `PUSH;
      repeat(34) @(posedge CLK);

      D = 32'b10000010111110010101000001011111;
      MODO = `LOAD;
      repeat(6) @(posedge CLK);

      DIR = 0;
      MODO = `CYCLE;
      repeat(34) @(posedge CLK);

      D = 32'b11001010110101101111000010011101;
      MODO = `LOAD;
      repeat(6) @(posedge CLK);

      DIR = 1;
      MODO = `CYCLE;
      repeat(34) @(posedge CLK);
      $finish;
    end

    initial
        $monitor("At time %t, Q = %h (%0d), S_OUT = %h (%0d)",
                 $time, Q, Q, S_OUT, S_OUT);

    initial begin
        $dumpfile ("registro32v2.vcd");
        $dumpvars(1, registro32v2_tb);
    end

endmodule
module registro32v2_tb();



  parameter  WIDTH = 32;


    reg ENB;
    reg DIR;
    reg S_IN;
    reg [1 : 0]         MODO;
    reg [WIDTH - 1 : 0] D;
    reg CLK;

    wire [WIDTH - 1 : 0] Q;
    wire                 S_OUT;


    registro #(WIDTH) r0
    (
      .Q(Q),
      .S_OUT(S_OUT),
      .D(D),
      .MODO(MODO),
      .CLK(CLK),
      .ENB(ENB),
      .DIR(DIR),
      .S_IN(S_IN)
      );



    initial begin
      CLK = 1'b0;
      ENB = 1'b0;
      repeat(4) #5 CLK = ~CLK;
      ENB = 1'b1;
      forever #5 CLK = ~CLK;
    end

    initial begin

      @(posedge ENB);
      D = 32'b11110000100111011111000010011101;
      MODO = `LOAD;
      S_IN = 1'b0;
      DIR = 0;
      repeat(6) @(posedge CLK);

      S_IN = 1'b0;
      DIR = 0;
      MODO = `PUSH;
      repeat(34) @(posedge CLK);

      S_IN = 1'b1;
      DIR = 1;
      MODO = `PUSH;
      repeat(34) @(posedge CLK);

      D = 32'b10000010111110010101000001011111;
      MODO = `LOAD;
      repeat(6) @(posedge CLK);

      DIR = 0;
      MODO = `CYCLE;
      repeat(34) @(posedge CLK);

      D = 32'b11001010110101101111000010011101;
      MODO = `LOAD;
      repeat(6) @(posedge CLK);

      DIR = 1;
      MODO = `CYCLE;
      repeat(34) @(posedge CLK);
      $finish;
    end

    initial
        $monitor("At time %t, Q = %h (%0d), S_OUT = %h (%0d)",
                 $time, Q, Q, S_OUT, S_OUT);

    initial begin
        $dumpfile ("registro32v2.vcd");
        $dumpvars(1, registro32v2_tb);
    end

endmodule