data/full_repos/permissive/150012894/main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/150012894/main.v:13: Unsupported: Ignoring delay on this delayed statement.\n #3 rst = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150012894/main.v:17: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n%Warning-WIDTH: data/full_repos/permissive/150012894/main.v:39: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 13 bits.\n                                                              : ... In instance teste.m\nwire [11:0] b_imm = {command[31], command[7], command[30:25], command[11:8], 1\'b0};\n                  ^\n%Error: data/full_repos/permissive/150012894/main.v:57: Cannot find file containing module: \'memory_maneger\'\nmemory_maneger mem(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150012894,data/full_repos/permissive/150012894/memory_maneger\n             data/full_repos/permissive/150012894,data/full_repos/permissive/150012894/memory_maneger.v\n             data/full_repos/permissive/150012894,data/full_repos/permissive/150012894/memory_maneger.sv\n             memory_maneger\n             memory_maneger.v\n             memory_maneger.sv\n             obj_dir/memory_maneger\n             obj_dir/memory_maneger.v\n             obj_dir/memory_maneger.sv\n%Error: data/full_repos/permissive/150012894/main.v:78: Cannot find file containing module: \'registers_bank\'\nregisters_bank regs(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150012894/main.v:90: Cannot find file containing module: \'ALU\'\nALU alu (\n^~~\n%Warning-WIDTH: data/full_repos/permissive/150012894/main.v:220: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp_counter2\' generates 5 bits.\n                                                               : ... In instance teste.m\n  temp <= { {20{i_imm[11]}} , i_imm} + regs_out + temp_counter2;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/150012894/main.v:267: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'temp_counter2\' generates 5 bits.\n                                                               : ... In instance teste.m\n  temp <= { {20{s_imm[11]}} , s_imm} + regs_out + temp_counter2;\n                                                ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module teste();

reg clk, rst;
main m(clk, rst);

initial begin
	clk = 0;
	rst = 1;
	#3 rst = 0;
end

always begin
	#1 clk = ~clk;
	if(m.pc == 'ha4 && m.state == 0)
		$stop();
end



endmodule
module teste();


reg clk, rst;
main m(clk, rst);

initial begin
	clk = 0;
	rst = 1;
	#3 rst = 0;
end

always begin
	#1 clk = ~clk;
	if(m.pc == 'ha4 && m.state == 0)
		$stop();
end



endmodule