data/full_repos/permissive/15579276/Clock_Divider.v
data/verilator_xmls/95ae709c-cfad-438d-807d-08a37f8b1fe8.xml
module Clock_Divider(clock_in, clock_out);
	input clock_in;
	output reg clock_out;
	reg [14:0] count;
	
	always @ (posedge clock_in)
	begin
		count <= count + 1;
		if (count >= 25000)
			begin
				count <= 0;
				clock_out <= ~clock_out;
			end
	end
endmodule
module Clock_Divider(clock_in, clock_out);

	input clock_in;
	output reg clock_out;
	reg [14:0] count;
	
	always @ (posedge clock_in)
	begin
		count <= count + 1;
		if (count >= 25000)
			begin
				count <= 0;
				clock_out <= ~clock_out;
			end
	end
endmodule