data/full_repos/permissive/196257568/neural_net_verilog/neuron32.v
 line:32: before: "9"
1: b"%Error: data/full_repos/permissive/196257568/neural_net_verilog/neuron32.v:26: Too many digits for 32 bit number: 1__0000_0000_0000_0000_0000_0000\n        ... As that number was unsized ('d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)\n        ... Suggest adding a size to it.\n mult m (1__0000_0000_0000_0000_0000_0000-w1, w1, w2);\n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module neuron32(prev_activ, weights, bias, activ, sigma_prime);
	input  prev_activ [1023:0];
	input  weights	   [1023:0];
	input  bias		   [31:0];
	output activ		[31:0];
	output sigma_prime[31:0];
	
	wire [1023:0] wires;
	wire [31:0] w1, w2;
	
	had_mult32 hm (prev_activ, weights, wires);
	
	wire sum = 0;

	integer i;	
	always @*
	begin
		while(i < 32)
		begin
			sum = sum + wires[i +: 7];
		end
	end
	assign sum = sum + bias;

	sigmoid s (sum, w1);
	mult m (1__0000_0000_0000_0000_0000_0000-w1, w1, w2);

	assign activ = w1;
	assign sigma_prime = w2;

endmodule
module neuron32(prev_activ, weights, bias, activ, sigma_prime);

	input  prev_activ [1023:0];
	input  weights	   [1023:0];
	input  bias		   [31:0];
	output activ		[31:0];
	output sigma_prime[31:0];
	
	wire [1023:0] wires;
	wire [31:0] w1, w2;
	
	had_mult32 hm (prev_activ, weights, wires);
	
	wire sum = 0;

	integer i;	
	always @*
	begin
		while(i < 32)
		begin
			sum = sum + wires[i +: 7];
		end
	end
	assign sum = sum + bias;

	sigmoid s (sum, w1);
	mult m (1__0000_0000_0000_0000_0000_0000-w1, w1, w2);

	assign activ = w1;
	assign sigma_prime = w2;

endmodule