data/full_repos/permissive/143278/ivltests/br972.v
 line:12: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br972.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #1 in = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br972.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #0 $display("out = %b", out);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br972.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 in = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br972.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #0 $display("out = %b", out);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br972.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 in = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br972.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #0 $display("out = %b", out);\n  ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

reg  in;
wire out;

assign out = out | in;

reg failed;

initial begin
  #1 in = 0;
  #0 $display("out = %b", out);
  if (out !== 1'bx) failed = 1;
  #1 in = 1;
  #0 $display("out = %b", out);
  if (out !== 1'b1) failed = 1;
  #1 in = 0;
  #0 $display("out = %b", out);
  if (out !== 1'b1) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");

  $finish;
end

endmodule
module test();


reg  in;
wire out;

assign out = out | in;

reg failed;

initial begin
  #1 in = 0;
  #0 $display("out = %b", out);
  if (out !== 1'bx) failed = 1;
  #1 in = 1;
  #0 $display("out = %b", out);
  if (out !== 1'b1) failed = 1;
  #1 in = 0;
  #0 $display("out = %b", out);
  if (out !== 1'b1) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");

  $finish;
end

endmodule