data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v
 line:112: before: "$"
1: b'%Error: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:87: Unsupported or unknown PLI call: $dumpvars\n           $dumpvars(0,A);\n           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:88: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:99: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:102: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:105: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:108: Unsupported: Ignoring delay on this delayed statement.\n           #1\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:111: Unsupported: Ignoring delay on this delayed statement.\n           #40\n           ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Teste;
    reg [11:0] Ponto1X;
    reg [11:0] Ponto1Y;

    reg [11:0] Ponto2X;
    reg [11:0] Ponto2Y;

    reg [11:0] Ponto3X;
    reg [11:0] Ponto3Y;

    reg [11:0] PontoTX;
    reg [11:0] PontoTY;

    wire Dentro;

    TesteTriangulo A(Ponto1X, Ponto1Y, Ponto2X, Ponto2Y, Ponto3X, Ponto3Y, PontoTX, PontoTY, Dentro);

    initial
        begin
           $dumpvars(0,A);
           #1

           Ponto1X <= 10;
           Ponto1Y <= 10;
           Ponto2X <= 30;
           Ponto2Y <= 10;
           Ponto3X <= 20;
           Ponto3Y <= 30;
           PontoTX <= 15;
           PontoTY <= 15;

           #1
           PontoTX <= 15;
           PontoTY <= 15;
           #1
           PontoTX <= 9;
           PontoTY <= 15;
           #1
           PontoTX <= 10;
           PontoTY <= 11;
           #1
           PontoTX <= 30;
           PontoTY <= 11;
           #40
           $finish;
        end
endmodule
module Teste;

    reg [11:0] Ponto1X;
    reg [11:0] Ponto1Y;

    reg [11:0] Ponto2X;
    reg [11:0] Ponto2Y;

    reg [11:0] Ponto3X;
    reg [11:0] Ponto3Y;

    reg [11:0] PontoTX;
    reg [11:0] PontoTY;

    wire Dentro;

    TesteTriangulo A(Ponto1X, Ponto1Y, Ponto2X, Ponto2Y, Ponto3X, Ponto3Y, PontoTX, PontoTY, Dentro);

    initial
        begin
           $dumpvars(0,A);
           #1

           Ponto1X <= 10;
           Ponto1Y <= 10;
           Ponto2X <= 30;
           Ponto2Y <= 10;
           Ponto3X <= 20;
           Ponto3Y <= 30;
           PontoTX <= 15;
           PontoTY <= 15;

           #1
           PontoTX <= 15;
           PontoTY <= 15;
           #1
           PontoTX <= 9;
           PontoTY <= 15;
           #1
           PontoTX <= 10;
           PontoTY <= 11;
           #1
           PontoTX <= 30;
           PontoTY <= 11;
           #40
           $finish;
        end
endmodule