data/full_repos/permissive/143278/vhdl_tests/mux2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/mux2.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/mux2.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/mux2.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux2(c, a, b, s);
  input a, b, s;
  output c;
  wire s_bar, a_and_s_bar, b_and_s;

  not(s_bar, s);
  and(a_and_s_bar, a, s_bar);
  and(b_and_s, b, s);
  or(c, a_and_s_bar, b_and_s);

endmodule
module mux2(c, a, b, s);

  input a, b, s;
  output c;
  wire s_bar, a_and_s_bar, b_and_s;

  not(s_bar, s);
  and(a_and_s_bar, a, s_bar);
  and(b_and_s, b, s);
  or(c, a_and_s_bar, b_and_s);

endmodule