data/full_repos/permissive/11926732/rc4_tb.v
 line:28: before: "E_valB_o"
1: b'%Error: data/full_repos/permissive/11926732/rc4_tb.v:28: Cannot find include file: rc4.inc\n`include "rc4.inc" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/11926732,data/full_repos/permissive/11926732/rc4.inc\n             data/full_repos/permissive/11926732,data/full_repos/permissive/11926732/rc4.inc.v\n             data/full_repos/permissive/11926732,data/full_repos/permissive/11926732/rc4.inc.sv\n             rc4.inc\n             rc4.inc.v\n             rc4.inc.sv\n             obj_dir/rc4.inc\n             obj_dir/rc4.inc.v\n             obj_dir/rc4.inc.sv\n%Error: data/full_repos/permissive/11926732/rc4_tb.v:32: Define or directive not defined: \'`KEY_SIZE\'\nreg [7:0] password[0:`KEY_SIZE-1];\n                     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/11926732/rc4_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\nalways #(tck/2) \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11926732/rc4_tb.v:52: Define or directive not defined: \'`KEY_SIZE\'\n if (clkcount < `KEY_SIZE)\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/11926732/rc4_tb.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (clkcount < `KEY_SIZE)\n                         ^\n%Error: data/full_repos/permissive/11926732/rc4_tb.v:57: syntax error, unexpected else\n else $display ("--- clk %d --- K %08X --- valid: ",clkcount,K,output_ready);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/11926732/rc4_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n #(1*tck) \n ^\n%Warning-STMTDLY: data/full_repos/permissive/11926732/rc4_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n #(program_cycles*tck+100000) \n ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n'
module rc4_tb;

reg [7:0] password[0:`KEY_SIZE-1];

parameter tck = 10, program_cycles = `TEST_CYCLES;


reg clk, rst;
wire output_ready;
wire [7:0] K;
reg [7:0] password_input;


always #(tck/2) 
	clk = ~clk;



integer clkcount;
always @ (posedge clk)
	begin
	clkcount<=clkcount+1;
	if (clkcount < `KEY_SIZE)
		begin
		password_input<=password[clkcount];
		$display ("--- clk %d --- key[%x] = %08X",clkcount,clkcount,password[clkcount]);
		end
	else $display ("--- clk %d --- K %08X --- valid: ",clkcount,K,output_ready);
	end



rc4 rc4mod(
	.clk(clk),
	.rst(rst),
	.password_input(password_input),
	.output_ready(output_ready),
	.K(K)
);



integer q;
initial begin
	password[0] = 8'h01;
	password[1] = 8'h02;
	password[2] = 8'h03;
	password[3] = 8'h04;
	password[4] = 8'h05;
	password[5] = 8'h06;
	password[6] = 8'h07;





	$display ("Start...");
	clk = 0;
	rst = 1;
	clkcount =0;
	password_input=password[clkcount];
	#(1*tck) 
	rst = 0;
	#(program_cycles*tck+100000) 
	$display ("Finish.");
	$finish;
end


endmodule
module rc4_tb;


reg [7:0] password[0:`KEY_SIZE-1];

parameter tck = 10, program_cycles = `TEST_CYCLES;


reg clk, rst;
wire output_ready;
wire [7:0] K;
reg [7:0] password_input;


always #(tck/2) 
	clk = ~clk;



integer clkcount;
always @ (posedge clk)
	begin
	clkcount<=clkcount+1;
	if (clkcount < `KEY_SIZE)
		begin
		password_input<=password[clkcount];
		$display ("--- clk %d --- key[%x] = %08X",clkcount,clkcount,password[clkcount]);
		end
	else $display ("--- clk %d --- K %08X --- valid: ",clkcount,K,output_ready);
	end



rc4 rc4mod(
	.clk(clk),
	.rst(rst),
	.password_input(password_input),
	.output_ready(output_ready),
	.K(K)
);



integer q;
initial begin
	password[0] = 8'h01;
	password[1] = 8'h02;
	password[2] = 8'h03;
	password[3] = 8'h04;
	password[4] = 8'h05;
	password[5] = 8'h06;
	password[6] = 8'h07;





	$display ("Start...");
	clk = 0;
	rst = 1;
	clkcount =0;
	password_input=password[clkcount];
	#(1*tck) 
	rst = 0;
	#(program_cycles*tck+100000) 
	$display ("Finish.");
	$finish;
end


endmodule