data/full_repos/permissive/174263347/crtv10/hdl/quad_tmr.v
1: b"%Error: data/full_repos/permissive/174263347/crtv10/hdl/quad_tmr.v:26: Cannot find file containing module: 'fextractor'\n    fextractor fa_obj( clk, reset, ena, a, risea);\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174263347/crtv10/hdl,data/full_repos/permissive/174263347/fextractor\n             data/full_repos/permissive/174263347/crtv10/hdl,data/full_repos/permissive/174263347/fextractor.v\n             data/full_repos/permissive/174263347/crtv10/hdl,data/full_repos/permissive/174263347/fextractor.sv\n             fextractor\n             fextractor.v\n             fextractor.sv\n             obj_dir/fextractor\n             obj_dir/fextractor.v\n             obj_dir/fextractor.sv\n%Error: data/full_repos/permissive/174263347/crtv10/hdl/quad_tmr.v:27: Cannot find file containing module: 'fextractor'\n    fextractor fb_obj( clk, reset, ena, b, riseb);\n    ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module quad_tmr ( clk, reset, ena, a, b, q);

    input           clk, reset, ena;
    input           a, b;
    output  [3:0]   q;

    reg     [3:0]   count;
    wire            risea, riseb;
    wire            plus, plusin;
    wire            enacnt;

    fextractor fa_obj( clk, reset, ena, a, risea);
    fextractor fb_obj( clk, reset, ena, b, riseb);

    lcel lcel_obj(plusin, plus);
    assign plusin   = (risea & (a !=  b)) | (b & (a == b));
    assign enacnt   = (risea | riseb) & ena;

    always @ (posedge reset or posedge clk)
        if (reset)
                count <= 0;
        else if(enacnt)
            if (plus)
                count <= count + 1;
            else
                count <= count -1;

    assign q = count;

endmodule
module quad_tmr ( clk, reset, ena, a, b, q);


    input           clk, reset, ena;
    input           a, b;
    output  [3:0]   q;

    reg     [3:0]   count;
    wire            risea, riseb;
    wire            plus, plusin;
    wire            enacnt;

    fextractor fa_obj( clk, reset, ena, a, risea);
    fextractor fb_obj( clk, reset, ena, b, riseb);

    lcel lcel_obj(plusin, plus);
    assign plusin   = (risea & (a !=  b)) | (b & (a == b));
    assign enacnt   = (risea | riseb) & ena;

    always @ (posedge reset or posedge clk)
        if (reset)
                count <= 0;
        else if(enacnt)
            if (plus)
                count <= count + 1;
            else
                count <= count -1;

    assign q = count;

endmodule