data/full_repos/permissive/137213315/aes_cipher_tb.v
 line:13: before: "#"
1: b'%Error: data/full_repos/permissive/137213315/aes_cipher_tb.v:6: Cannot find include file: aes_cipher.v\n`include "aes_cipher.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137213315,data/full_repos/permissive/137213315/aes_cipher.v\n             data/full_repos/permissive/137213315,data/full_repos/permissive/137213315/aes_cipher.v.v\n             data/full_repos/permissive/137213315,data/full_repos/permissive/137213315/aes_cipher.v.sv\n             aes_cipher.v\n             aes_cipher.v.v\n             aes_cipher.v.sv\n             obj_dir/aes_cipher.v\n             obj_dir/aes_cipher.v.v\n             obj_dir/aes_cipher.v.sv\n%Error: data/full_repos/permissive/137213315/aes_cipher_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("aes_cipher_tb.vcp");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/137213315/aes_cipher_tb.v:19: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/137213315/aes_cipher_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #0.1\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/137213315/aes_cipher_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #1 start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137213315/aes_cipher_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #30\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137213315/aes_cipher_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module aes_cipher_tb;
    reg clk, rstn;
    reg [127:0] plain_text, key;
    reg start;
    wire [127:0] cipher_text;
    wire done;
    aes_cipher AES (.clk(clk),.rstn(rstn),.plain_text(plain_text),
                    .key(key),.cipher_text(cipher_text),.start(start),.done(done));
    integer i;
    initial begin
        $dumpfile("aes_cipher_tb.vcp");
        $dumpvars;
        clk = 0;
        rstn = 0;
        start = 1;
        #0.1
        rstn = 1;
        
        #1 start = 0;
        #30
        $finish;
    end

    always #1 clk = ~clk;

endmodule
module aes_cipher_tb;

    reg clk, rstn;
    reg [127:0] plain_text, key;
    reg start;
    wire [127:0] cipher_text;
    wire done;
    aes_cipher AES (.clk(clk),.rstn(rstn),.plain_text(plain_text),
                    .key(key),.cipher_text(cipher_text),.start(start),.done(done));
    integer i;
    initial begin
        $dumpfile("aes_cipher_tb.vcp");
        $dumpvars;
        clk = 0;
        rstn = 0;
        start = 1;
        #0.1
        rstn = 1;
        
        #1 start = 0;
        #30
        $finish;
    end

    always #1 clk = ~clk;

endmodule