data/full_repos/permissive/143278/ivltests/pr1861212b.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1861212b.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #1000 vint = 4.5776;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1861212b.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1000 vint = -4;\n    ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rcvr(input wire [63:0] vo);

  always @(vo)
    $display("Real value is %f at %g", $bitstoreal(vo), $time);
endmodule
module rcvr(input wire [63:0] vo);


  always @(vo)
    $display("Real value is %f at %g", $bitstoreal(vo), $time);
endmodule