data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v
1: b'%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v:55: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'hex_\' generates 4 bits.\n                                                                                        : ... In instance hex_8421BCD\nassign ystemp = hex_ + linshi;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v:55: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'linshi\' generates 4 bits.\n                                                                                        : ... In instance hex_8421BCD\nassign ystemp = hex_ + linshi;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v:61: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'hex_\' generates 4 bits.\n                                                                                        : ... In instance hex_8421BCD\nassign yunsuantemp = hex_ + linshi - 8\'d10;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v:61: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'linshi\' generates 4 bits.\n                                                                                        : ... In instance hex_8421BCD\nassign yunsuantemp = hex_ + linshi - 8\'d10;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v:79: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'jw1\' generates 1 bits.\n                                                                                        : ... In instance hex_8421BCD\n) + jw1 + jw2;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/115487336/mycode/Whac-A-Mole/hex_8421BCD.v:79: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'jw2\' generates 1 bits.\n                                                                                        : ... In instance hex_8421BCD\n) + jw1 + jw2;\n        ^\n%Error: Exiting due to 6 warning(s)\n'
module hex_8421BCD(
	input [7:0] hex,
	output [7:0] BCD
);

wire [3:0] gw;
wire [3:0] bw;

wire [3:0] linshi;

wire jw1;
wire jw2;

wire [3:0] hex_;
wire [3:0] _hex;

assign linshi = (
	hex[7:4] == 4'h1 ? 4'd6 :(
		hex[7:4] == 4'h2 ? 4'd2 : (
			hex[7:4] == 4'h3 ? 4'd8 : (
				hex[7:4] == 4'h4 ? 4'd4 : (
					hex[7:4] == 4'h5 ? 4'd0 : (
						hex[7:4] == 4'h6 ? 4'd6 : 4'd0
					)
				)
			)
		)
	)
);

assign jw1 = hex[3:0] > 4'd9 ? 1 : 0;
assign hex_ = (jw1 == 1 ? hex[3:0] - 4'd10 : hex[3:0]);

wire [7:0] ystemp;
assign ystemp = hex_ + linshi;

assign jw2 = ystemp > 8'd9 ? 1 : 0;

wire [7:0] yunsuantemp;

assign yunsuantemp = hex_ + linshi - 8'd10;

assign BCD[3:0] = (jw2 == 1 ? yunsuantemp[3:0] : hex_ + linshi);

assign _hex = (
	hex[7:4] == 4'h0 ? 4'd0 : (
		hex[7:4] == 4'h1 ? 4'd1 : (
			hex[7:4] == 4'h2 ? 4'd3 : (
				hex[7:4] == 4'h3 ? 4'd4: (
					hex[7:4] == 4'h4 ? 4'd6 : (
						hex[7:4] == 4'h5 ? 4'd8 : (
							hex[7:4] == 4'h6 ? 4'd9 : 4'd0
						)
					)
				)
			)
		)
	)
) + jw1 + jw2;

assign BCD[7:4] = _hex;
endmodule
module hex_8421BCD(
	input [7:0] hex,
	output [7:0] BCD
);


wire [3:0] gw;
wire [3:0] bw;

wire [3:0] linshi;

wire jw1;
wire jw2;

wire [3:0] hex_;
wire [3:0] _hex;

assign linshi = (
	hex[7:4] == 4'h1 ? 4'd6 :(
		hex[7:4] == 4'h2 ? 4'd2 : (
			hex[7:4] == 4'h3 ? 4'd8 : (
				hex[7:4] == 4'h4 ? 4'd4 : (
					hex[7:4] == 4'h5 ? 4'd0 : (
						hex[7:4] == 4'h6 ? 4'd6 : 4'd0
					)
				)
			)
		)
	)
);

assign jw1 = hex[3:0] > 4'd9 ? 1 : 0;
assign hex_ = (jw1 == 1 ? hex[3:0] - 4'd10 : hex[3:0]);

wire [7:0] ystemp;
assign ystemp = hex_ + linshi;

assign jw2 = ystemp > 8'd9 ? 1 : 0;

wire [7:0] yunsuantemp;

assign yunsuantemp = hex_ + linshi - 8'd10;

assign BCD[3:0] = (jw2 == 1 ? yunsuantemp[3:0] : hex_ + linshi);

assign _hex = (
	hex[7:4] == 4'h0 ? 4'd0 : (
		hex[7:4] == 4'h1 ? 4'd1 : (
			hex[7:4] == 4'h2 ? 4'd3 : (
				hex[7:4] == 4'h3 ? 4'd4: (
					hex[7:4] == 4'h4 ? 4'd6 : (
						hex[7:4] == 4'h5 ? 4'd8 : (
							hex[7:4] == 4'h6 ? 4'd9 : 4'd0
						)
					)
				)
			)
		)
	)
) + jw1 + jw2;

assign BCD[7:4] = _hex;
endmodule