data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/regFile_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/regFile_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clock = ~clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/regFile_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/regFile_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/regFile_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/regFile_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/regFile_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/regFile_tb.v:19: Cannot find file containing module: \'regFile\'\nregFile uut (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/regFile\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/regFile.v\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/regFile.sv\n             regFile\n             regFile.v\n             regFile.sv\n             obj_dir/regFile\n             obj_dir/regFile.v\n             obj_dir/regFile.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module regFile_tb();

reg clock, reset;


reg wEn;
reg [4:0]read_sel1, read_sel2, write_sel;
reg [31:0] write_data;

wire [31:0] read_data1, read_data2;


regFile uut (
  .clock(clock),
  .reset(reset),
  .wEn(wEn),
  .write_data(write_data),
  .read_sel1(read_sel1),
  .read_sel2(read_sel2),
  .write_sel(write_sel),
  .read_data1(read_data1),
  .read_data2(read_data2)
);


always #5 clock = ~clock;

initial begin
  clock = 1'b1;
  reset = 1'b1;
  #1;
  #20;
  reset = 1'b0;



	wEn = 1'b1;
	write_data = 32'd12;
   read_sel1 = 5'b00000;
	read_sel2 = 5'b00010;
	write_sel = 5'b00000;
	
	#20;
	wEn = 1'b1;
	write_data = 32'd11;
   read_sel1 = 5'b00001;
	read_sel2 = 5'b00010;
	write_sel = 5'b00001;
	
	#20;
	wEn = 1'b1;
	write_data = 32'd10;
   read_sel1 = 5'b00001;
	read_sel2 = 5'b00011;
	write_sel = 5'b00001;
	
	#20;
	wEn = 1'b1;
	write_data = 32'd9;
   read_sel1 = 5'b00001;
	read_sel2 = 5'b00010;
	write_sel = 5'b00010;
	
end
endmodule
module regFile_tb();


reg clock, reset;


reg wEn;
reg [4:0]read_sel1, read_sel2, write_sel;
reg [31:0] write_data;

wire [31:0] read_data1, read_data2;


regFile uut (
  .clock(clock),
  .reset(reset),
  .wEn(wEn),
  .write_data(write_data),
  .read_sel1(read_sel1),
  .read_sel2(read_sel2),
  .write_sel(write_sel),
  .read_data1(read_data1),
  .read_data2(read_data2)
);


always #5 clock = ~clock;

initial begin
  clock = 1'b1;
  reset = 1'b1;
  #1;
  #20;
  reset = 1'b0;



	wEn = 1'b1;
	write_data = 32'd12;
   read_sel1 = 5'b00000;
	read_sel2 = 5'b00010;
	write_sel = 5'b00000;
	
	#20;
	wEn = 1'b1;
	write_data = 32'd11;
   read_sel1 = 5'b00001;
	read_sel2 = 5'b00010;
	write_sel = 5'b00001;
	
	#20;
	wEn = 1'b1;
	write_data = 32'd10;
   read_sel1 = 5'b00001;
	read_sel2 = 5'b00011;
	write_sel = 5'b00001;
	
	#20;
	wEn = 1'b1;
	write_data = 32'd9;
   read_sel1 = 5'b00001;
	read_sel2 = 5'b00010;
	write_sel = 5'b00010;
	
end
endmodule