data/full_repos/permissive/146246005/RISC-y Processor/RISCY_CPU.sv
 line:3: before: "package"
1: b'%Error: Cannot find file containing module: Processor,data/full_repos/permissive/146246005\n        ... Looked in:\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.v\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.sv\n             Processor,data/full_repos/permissive/146246005\n             Processor,data/full_repos/permissive/146246005.v\n             Processor,data/full_repos/permissive/146246005.sv\n             obj_dir/Processor,data/full_repos/permissive/146246005\n             obj_dir/Processor,data/full_repos/permissive/146246005.v\n             obj_dir/Processor,data/full_repos/permissive/146246005.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/RISC-y\n%Error: Cannot find file containing module: Processor/RISCY_CPU.sv\n%Error: Exiting due to 3 error(s)\n'
module AASD(AASD_RST,CLOCK,RESET);
	output reg AASD_RST;
	input CLOCK,RESET;
	reg Out1;
always @ (posedge CLOCK or negedge RESET)
	if(!RESET)begin
		Out1 <= 1'b0;
		AASD_RST <= 1'b0;
	end
	else begin
		Out1 <= 1'b1;
		AASD_RST <= Out1;
	end
endmodule
module AASD(AASD_RST,CLOCK,RESET);

	output reg AASD_RST;
	input CLOCK,RESET;
	reg Out1;
always @ (posedge CLOCK or negedge RESET)
	if(!RESET)begin
		Out1 <= 1'b0;
		AASD_RST <= 1'b0;
	end
	else begin
		Out1 <= 1'b1;
		AASD_RST <= Out1;
	end
endmodule