data/full_repos/permissive/162251494/pattern.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/162251494/pattern.v:112: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'pattern\'\nmodule pattern(input clock, input [3:0] state,\n       ^~~~~~~\n                                                                     : ... Top module \'patterndatapath\'\nmodule patterndatapath(input [2:0] load_A, input [2:0] load_B, input [2:0] load_C, input [2:0] load_D,\n       ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/162251494/pattern.v:100: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'state\' generates 4 bits.\n                                                                  : ... In instance pattern\n  else if(state == 16) begin\n                ^~\n%Error: Exiting due to 2 warning(s)\n'
module pattern(input clock, input [3:0] state,
					  output reg [2:0] load_A,
					  output reg [2:0] load_B,
					  output reg [2:0] load_C,
					  output reg [2:0] load_D);
	
	always @(posedge clock) begin
	  if(state == 1) begin
			load_A <= 1;
			load_B <= 2;
			load_C <= 3;
			load_D <= 4;
		end
		else if(state == 2) begin
			load_A <= 2;
			load_B <= 3;
			load_C <= 4;
			load_D <= 5;
		end
		else if(state == 3) begin
			load_A <= 3;
			load_B <= 4;
			load_C <= 5;
			load_D <= 6;
		end
		else if(state == 4) begin
			load_A <= 4;
			load_B <= 5;
			load_C <= 6;
			load_D <= 1;
		end
		else if(state == 5) begin
			load_A <= 5;
			load_B <= 6;
			load_C <= 1;
			load_D <= 2;
		end
		else if(state == 6) begin
			load_A <= 6;
			load_B <= 1;
			load_C <= 2;
			load_D <= 3;
		end
		else if(state == 7) begin
			load_A <= 5;
			load_B <= 2;
			load_C <= 3;
			load_D <= 2;
		end
		else if(state == 8) begin
			load_A <= 4;
			load_B <= 3;
			load_C <= 4;
			load_D <= 1;
		end
		else if(state == 9) begin
			load_A <= 3;
			load_B <= 4;
			load_C <= 5;
			load_D <= 6;
		end
		else if(state == 10) begin
			load_A <= 2;
			load_B <= 5;
			load_C <= 6;
			load_D <= 5;
		end
		else if(state == 11) begin
			load_A <= 1;
			load_B <= 6;
			load_C <= 1;
			load_D <= 4;
		end
		else if(state == 12) begin
			load_A <= 2;
			load_B <= 5;
			load_C <= 2;
			load_D <= 3;
		end
		else if(state == 13) begin
			load_A <= 3;
			load_B <= 4;
			load_C <= 3;
			load_D <= 2;
		end
		else if(state == 14) begin
			load_A <= 4;
			load_B <= 3;
			load_C <= 2;
			load_D <= 1;
		end
		else if(state == 15) begin
			load_A <= 5;
			load_B <= 2;
			load_C <= 5;
			load_D <= 2;
		end
		else if(state == 16) begin
			load_A <= 6;
			load_B <= 1;
			load_C <= 6;
			load_D <= 3;
		end
	
	end


endmodule
module pattern(input clock, input [3:0] state,
					  output reg [2:0] load_A,
					  output reg [2:0] load_B,
					  output reg [2:0] load_C,
					  output reg [2:0] load_D);

	
	always @(posedge clock) begin
	  if(state == 1) begin
			load_A <= 1;
			load_B <= 2;
			load_C <= 3;
			load_D <= 4;
		end
		else if(state == 2) begin
			load_A <= 2;
			load_B <= 3;
			load_C <= 4;
			load_D <= 5;
		end
		else if(state == 3) begin
			load_A <= 3;
			load_B <= 4;
			load_C <= 5;
			load_D <= 6;
		end
		else if(state == 4) begin
			load_A <= 4;
			load_B <= 5;
			load_C <= 6;
			load_D <= 1;
		end
		else if(state == 5) begin
			load_A <= 5;
			load_B <= 6;
			load_C <= 1;
			load_D <= 2;
		end
		else if(state == 6) begin
			load_A <= 6;
			load_B <= 1;
			load_C <= 2;
			load_D <= 3;
		end
		else if(state == 7) begin
			load_A <= 5;
			load_B <= 2;
			load_C <= 3;
			load_D <= 2;
		end
		else if(state == 8) begin
			load_A <= 4;
			load_B <= 3;
			load_C <= 4;
			load_D <= 1;
		end
		else if(state == 9) begin
			load_A <= 3;
			load_B <= 4;
			load_C <= 5;
			load_D <= 6;
		end
		else if(state == 10) begin
			load_A <= 2;
			load_B <= 5;
			load_C <= 6;
			load_D <= 5;
		end
		else if(state == 11) begin
			load_A <= 1;
			load_B <= 6;
			load_C <= 1;
			load_D <= 4;
		end
		else if(state == 12) begin
			load_A <= 2;
			load_B <= 5;
			load_C <= 2;
			load_D <= 3;
		end
		else if(state == 13) begin
			load_A <= 3;
			load_B <= 4;
			load_C <= 3;
			load_D <= 2;
		end
		else if(state == 14) begin
			load_A <= 4;
			load_B <= 3;
			load_C <= 2;
			load_D <= 1;
		end
		else if(state == 15) begin
			load_A <= 5;
			load_B <= 2;
			load_C <= 5;
			load_D <= 2;
		end
		else if(state == 16) begin
			load_A <= 6;
			load_B <= 1;
			load_C <= 6;
			load_D <= 3;
		end
	
	end


endmodule