data/full_repos/permissive/194652065/.drl_src_code/filt_cicd/rtl/dff.v
data/verilator_xmls/e22b17e7-bfd5-4cde-8960-59e1f261c2fe.xml
module dff #(
  parameter gp_data_width = 8
) 
(
  input  wire                     i_rst_an,
  input  wire                     i_ena,
  input  wire                     i_clk,
  input  wire [gp_data_width-1:0] i_data,
  output wire [gp_data_width-1:0] o_data
);

  reg [gp_data_width-1:0] r_data;

  always @(posedge i_clk or negedge i_rst_an)
    begin: p_dff
      if (!i_rst_an)
        r_data <= 'd0;
      else if (i_ena)
        r_data <= i_data;  
    end
  
  assign o_data = r_data;
endmodule
module dff #(
  parameter gp_data_width = 8
) 
(
  input  wire                     i_rst_an,
  input  wire                     i_ena,
  input  wire                     i_clk,
  input  wire [gp_data_width-1:0] i_data,
  output wire [gp_data_width-1:0] o_data
);


  reg [gp_data_width-1:0] r_data;

  always @(posedge i_clk or negedge i_rst_an)
    begin: p_dff
      if (!i_rst_an)
        r_data <= 'd0;
      else if (i_ena)
        r_data <= i_data;  
    end
  
  assign o_data = r_data;
endmodule