data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_execute_monociclo.v
 line:65: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_execute_monociclo.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst= 1\'b1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_execute_monociclo.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #500 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_execute_monociclo.v:69: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_execute_monociclo.v:71: Cannot find file containing module: \'tl_execute\'\ntl_execute\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_execute\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_execute.v\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_execute.sv\n             tl_execute\n             tl_execute.v\n             tl_execute.sv\n             obj_dir/tl_execute\n             obj_dir/tl_execute.v\n             obj_dir/tl_execute.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_instruction_execute_monociclo();

localparam LEN=32;
localparam NB_ADDRESS_REGISTROS = 5;
localparam NB_ALU_CONTROL = 4;
localparam NB_CTRL_WB = 2;
localparam NB_CTRL_MEM = 3;
localparam NB_CTRL_EX = 7;

reg clk;
reg rst;
reg [LEN-1:0] adder_id;
reg [LEN-1:0] dato1_id;
reg [LEN-1:0] dato2_id;
reg [LEN-1:0] sign_extend_id;
reg [NB_CTRL_WB-1:0] ctrl_wb_id;
reg [NB_CTRL_MEM-1:0] ctrl_mem_id;
reg [NB_CTRL_EX-1:0] ctrl_ex_id;
reg [NB_ADDRESS_REGISTROS-1:0] rd_id;
reg [NB_ADDRESS_REGISTROS-1:0] rt_id;
wire alu_zero_ex;
wire [NB_ADDRESS_REGISTROS-1:0] write_reg_ex;
wire [NB_CTRL_WB-1:0] ctrl_wb_ex;
wire [NB_CTRL_MEM-1:0] ctrl_mem_ex; 
wire [LEN-1:0] branch_dir_ex;
wire [LEN-1:0] result_alu_ex;
wire [LEN-1:0] dato2_ex;

initial
begin
    clk = 1'b0;
    rst = 1'b0;
    adder_id = 32'b0;
    dato1_id = 32'b0;
    dato2_id = 32'b0;
    sign_extend_id = 32'b0;
    ctrl_wb_id = 2'b0;
    ctrl_mem_id = 3'b0;
    ctrl_ex_id = 7'b0;
    rd_id = 5'b0;
    rt_id = 5'b0;
    #10 rst= 1'b1;
    #500 $finish;
end


always #2.5 clk=~clk;

tl_execute
#(
    .LEN(LEN),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS),
    .NB_ALU_CONTROL(NB_ALU_CONTROL),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_CTRL_EX(NB_CTRL_EX)
)
    u_tl_execute
(
    .i_clk(clk),
    .i_rst(rst),
    .i_adder_id(adder_id),
    .i_dato1(dato1_id),
    .i_dato2(dato2_id),
    .i_sign_extend(sign_extend_id),
    .i_ctrl_wb(ctrl_wb_id),
    .i_ctrl_mem(ctrl_mem_id),
    .i_ctrl_ex(ctrl_ex_id),
    .i_rd(rd_id),
    .i_rt(rt_id),
    .o_alu_zero(alu_zero_ex),
    .o_write_reg(write_reg_ex),
    .o_ctrl_wb(ctrl_wb_ex),
    .o_ctrl_mem(ctrl_mem_ex),
    .o_add_execute(branch_dir_ex),
    .o_alu_result(result_alu_ex),
    .o_dato2(dato2_ex)
);

endmodule
module tb_instruction_execute_monociclo();


localparam LEN=32;
localparam NB_ADDRESS_REGISTROS = 5;
localparam NB_ALU_CONTROL = 4;
localparam NB_CTRL_WB = 2;
localparam NB_CTRL_MEM = 3;
localparam NB_CTRL_EX = 7;

reg clk;
reg rst;
reg [LEN-1:0] adder_id;
reg [LEN-1:0] dato1_id;
reg [LEN-1:0] dato2_id;
reg [LEN-1:0] sign_extend_id;
reg [NB_CTRL_WB-1:0] ctrl_wb_id;
reg [NB_CTRL_MEM-1:0] ctrl_mem_id;
reg [NB_CTRL_EX-1:0] ctrl_ex_id;
reg [NB_ADDRESS_REGISTROS-1:0] rd_id;
reg [NB_ADDRESS_REGISTROS-1:0] rt_id;
wire alu_zero_ex;
wire [NB_ADDRESS_REGISTROS-1:0] write_reg_ex;
wire [NB_CTRL_WB-1:0] ctrl_wb_ex;
wire [NB_CTRL_MEM-1:0] ctrl_mem_ex; 
wire [LEN-1:0] branch_dir_ex;
wire [LEN-1:0] result_alu_ex;
wire [LEN-1:0] dato2_ex;

initial
begin
    clk = 1'b0;
    rst = 1'b0;
    adder_id = 32'b0;
    dato1_id = 32'b0;
    dato2_id = 32'b0;
    sign_extend_id = 32'b0;
    ctrl_wb_id = 2'b0;
    ctrl_mem_id = 3'b0;
    ctrl_ex_id = 7'b0;
    rd_id = 5'b0;
    rt_id = 5'b0;
    #10 rst= 1'b1;
    #500 $finish;
end


always #2.5 clk=~clk;

tl_execute
#(
    .LEN(LEN),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS),
    .NB_ALU_CONTROL(NB_ALU_CONTROL),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM),
    .NB_CTRL_EX(NB_CTRL_EX)
)
    u_tl_execute
(
    .i_clk(clk),
    .i_rst(rst),
    .i_adder_id(adder_id),
    .i_dato1(dato1_id),
    .i_dato2(dato2_id),
    .i_sign_extend(sign_extend_id),
    .i_ctrl_wb(ctrl_wb_id),
    .i_ctrl_mem(ctrl_mem_id),
    .i_ctrl_ex(ctrl_ex_id),
    .i_rd(rd_id),
    .i_rt(rt_id),
    .o_alu_zero(alu_zero_ex),
    .o_write_reg(write_reg_ex),
    .o_ctrl_wb(ctrl_wb_ex),
    .o_ctrl_mem(ctrl_mem_ex),
    .o_add_execute(branch_dir_ex),
    .o_alu_result(result_alu_ex),
    .o_dato2(dato2_ex)
);

endmodule