data/full_repos/permissive/169266176/Plus4_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/169266176/Plus4_testbench.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #150000;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169266176/Plus4_testbench.v:489: Unsupported: Ignoring delay on this delayed statement.\n#17.675 CLK28<=~CLK28;\n^\n%Warning-IMPLICIT: data/full_repos/permissive/169266176/Plus4_testbench.v:212: Signal definition not found, creating implicitly: \'cfg_done\'\nassign ram_addr=(cfg_done)?plus4_addr:boot_addr;\n                 ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/169266176/Plus4_testbench.v:328: Signal definition not found, creating implicitly: \'KERN\'\nassign KERN=(plus4_addr[15:8]==8\'hfc)?1\'b1:1\'b0;\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/169266176/Plus4_testbench.v:333: Signal definition not found, creating implicitly: \'phi2\'\n                                                                             : ... Suggested alternative: \'phi0\'\nassign phi2=~RAS & pla_arm & phi0;                \n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/169266176/Plus4_testbench.v:334: Signal definition not found, creating implicitly: \'FD2x\'\n                                                                             : ... Suggested alternative: \'FD0x\'\nassign FD2x=((plus4_addr[15:4]==12\'hfd2) & phi0 & ~RAS);         \n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/169266176/Plus4_testbench.v:335: Signal definition not found, creating implicitly: \'FD9x\'\n                                                                             : ... Suggested alternative: \'FD0x\'\nassign FD9x=((plus4_addr[15:4]==12\'hfd9) & phi0 & ~RAS);         \n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/169266176/Plus4_testbench.v:370: Signal definition not found, creating implicitly: \'key_esc\'\n if(sreset&key_esc)      \n           ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/169266176/Plus4_testbench.v:133: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h7f\' generates 7 bits.\n                                                                          : ... In instance Plus4_testbench\n  keyscancode=7\'hff;\n             ^\n%Error: data/full_repos/permissive/169266176/Plus4_testbench.v:145: Cannot find file containing module: \'mos8501\'\n mos8501 cpu (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169266176,data/full_repos/permissive/169266176/mos8501\n             data/full_repos/permissive/169266176,data/full_repos/permissive/169266176/mos8501.v\n             data/full_repos/permissive/169266176,data/full_repos/permissive/169266176/mos8501.sv\n             mos8501\n             mos8501.v\n             mos8501.sv\n             obj_dir/mos8501\n             obj_dir/mos8501.v\n             obj_dir/mos8501.sv\n%Error: data/full_repos/permissive/169266176/Plus4_testbench.v:162: Cannot find file containing module: \'ted\'\n ted mos8360(\n ^~~\n%Error: data/full_repos/permissive/169266176/Plus4_testbench.v:187: Cannot find file containing module: \'sdram_controller\'\n sdram_controller ram_ctrl(\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169266176/Plus4_testbench.v:221: Cannot find file containing module: \'mt48lc4m16a2\'\nmt48lc4m16a2 sdram(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169266176/Plus4_testbench.v:235: Cannot find file containing module: \'kernal_rom\'\n kernal_rom kernal(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/169266176/Plus4_testbench.v:243: Cannot find file containing module: \'basic_rom\'\n basic_rom basic(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/169266176/Plus4_testbench.v:251: Cannot find file containing module: \'colors_to_rgb\'\ncolors_to_rgb colordecode(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169266176/Plus4_testbench.v:270: Cannot find file containing module: \'c16_keymatrix\'\nc16_keymatrix keyboard(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169266176/Plus4_testbench.v:282: Cannot find file containing module: \'mos6529\'\nmos6529 keyport(\n^~~~~~~\n%Error: data/full_repos/permissive/169266176/Plus4_testbench.v:294: Cannot find file containing module: \'bootstrap\'\n bootstrap boot(\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/169266176/Plus4_testbench.v:448: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'resetcounter\' generates 13 bits.\n                                                                          : ... In instance Plus4_testbench\n  if(resetcounter==24\'d5000) begin\n                 ^~\n%Error: Exiting due to 10 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Plus4_testbench;
	
	reg CLK28;
	wire phi0;
	reg phi0_prev;
	reg phi_prev;
	reg sreset=0;
	reg RESET=0;
	reg [7:0] port_in=0;
	wire [7:0] port_out;
	wire [7:0] datain;
	wire aec;
	wire rdy;
	reg enable=0;


	wire irq_n;
   wire [7:0] dataout;
	wire [15:0] addr;
	wire RW;
	wire [6:0] color;
	wire [3:0] red,green,blue;
	wire csync;
	wire RAS,CAS,mux,cs0,cs1;
	
	wire [15:0] plus4_addr,ted_addr,cpu_addr;
	wire [7:0]  plus4_data,ted_data,ram_data,A,cpu_data,basic_data,kernal_data,rom_data;
	wire [7:0] keyboard_row,keyport_data,key,kbus;
	reg [7:0] romreg_data;
	reg  [7:0] plus4_datalatch=0;
	reg [7:0] keyscancode;
	wire [6:0] plus4_color;
	reg [12:0] resetcounter=0;
	reg [15:0] plus4_addrlatch=0;
	wire keyreset;
	wire [4:0] joy0port,joy1port;
	wire [4:0] joy0emu,joy1emu;
	reg keyreceived=0;
	wire cpuenable;
	reg pla_arm;
	wire FD3x;
	wire FDDx;
	reg  FDDx_prev=0;
	wire FD1x;
	wire FD0x;
	reg [3:0] romselect=0;
	reg [3:0] Kernalver=4'h0;
	reg [3:0] Basicver=4'h0;
	reg [3:0] FunctionLver=4'h0;
	reg [3:0] FunctionHver=4'h0;
	reg [3:0] C1Lver=4'h0;
	reg [3:0] C1Hver=4'h0;
	reg [3:0] C2Lver=4'h0;
	reg [3:0] C2Hver=4'h0;
	reg [3:0] romversion;
	reg [5:0] romaddrext;
	reg [5:0] ramaddrext=6'b000000;
	wire [5:0] plus4_addrext;
	reg romconfig=0;
	reg romconfreset=0;
	reg FD9x_prev=0;
	wire boot_cs;
	
	wire [11:0] SDRAM_ADDR;
	wire [15:0] SDRAM_DATA;
	wire SDRAM_DQML;
	wire SDRAM_DQMH;
	wire [1:0] SDRAM_BA;
	wire SDRAM_nWE;
	wire SDRAM_nCAS;
	wire SDRAM_nRAS;
	wire SDRAM_CS;
	wire SDRAM_CKE;

	wire FLASH_SI;
	wire FLASH_SO;
	wire FLASH_CK;
	wire FLASH_CS;
	wire boot_cs0;
	wire boot_cs1;
	wire boot_rw;
	wire [15:0] boot_addr;
	wire [5:0] boot_addrext;
	wire [7:0] boot_data;
	wire [7:0] config_data;
	wire boot_done;
	
	wire sdram_cs0;
	wire sdram_cs1;
	wire sdram_rw;
	wire [15:0] ram_addr;
	wire [5:0] sdram_addrext;
	wire [7:0] sdram_datain;
	
	initial begin

		CLK28=0;
		keyscancode=7'hff;
		keyreceived=1;
		file=$fopen("fakerom.bin","rb");

		#150000;
		port_in=8'hff;
		

						
	end
	

	mos8501 cpu (
		.clk(CLK28), 
		.reset(sreset), 
		.enable(cpuenable),  
		.irq_n(irq_n), 
		.data_in(plus4_data), 
		.data_out(cpu_data), 
		.address(cpu_addr),
		.gate_in(mux),
		.rw(RW),
		.port_in(port_in),
		.port_out(port_out),
		.rdy(rdy),
		.aec(aec)
	);


	ted mos8360(
		.clk(CLK28),
		.addr_in(plus4_addr),
		.addr_out(ted_addr),
		.data_in(plus4_data),
		.data_out(ted_data),
		.rw(RW),
		.cpuclk(phi0),
		.color(color),
		.csync(csync),
		.irq(irq_n),
		.ba(rdy),
		.mux(mux),
		.ras(RAS),
		.cas(CAS),
		.cs0(cs0),
		.cs1(cs1),
		.aec(aec),
		.k(kbus),
		.snd(sound),
		.cpuenable(cpuenable)

		);


 sdram_controller ram_ctrl(
		.sdram_addr(SDRAM_ADDR),
		.sdram_data(SDRAM_DATA),
		.sdram_dqm({SDRAM_DQMH,SDRAM_DQML}),
		.sdram_ba(SDRAM_BA),
		.sdram_we(SDRAM_nWE),
		.sdram_ras(SDRAM_nRAS),
		.sdram_cas(SDRAM_nCAS),
		.sdram_cs(SDRAM_CS),
		.sdram_cke(SDRAM_CKE),
		.clk(CLK28),
		.plus4_addr(ram_addr),
		.plus4_addrext(sdram_addrext),								
		.plus4_ras(RAS),
		.plus4_cas(CAS),
		.plus4_rw(sdram_rw),
		.plus4_cs0(sdram_cs0),
		.plus4_cs1(sdram_cs1),
		.ram_datain(sdram_datain),
		.ram_dataout(ram_data),
		.initdone(raminitdone)
 );



assign ram_addr=(cfg_done)?plus4_addr:boot_addr;
assign sdram_addrext=(boot_done)?plus4_addrext:boot_addrext;
assign sdram_cs0=(boot_done)?cs0:boot_cs0;
assign sdram_cs1=(boot_done)?cs1:boot_cs1;
assign sdram_rw=(boot_done)?RW:boot_rw;
assign sdram_datain=(boot_done)?plus4_data:boot_data;

assign plus4_addrext=(~cs0|~cs1)?romaddrext:ramaddrext;

mt48lc4m16a2 sdram(
	.Dq(SDRAM_DATA),
	.Addr(SDRAM_ADDR),
	.Ba(SDRAM_BA),
	.Clk(~CLK28),
	.Cke(SDRAM_CKE),
	.Cs_n(SDRAM_CS),
	.Ras_n(SDRAM_nRAS),
	.Cas_n(SDRAM_nCAS),
	.We_n(SDRAM_nWE),
	.Dqm({SDRAM_DQMH,SDRAM_DQML})
	);	 


	kernal_rom kernal(
		.clk(CLK28),
		.address_in(plus4_addr[13:0]),
		.data_out(kernal_data),
		.cs(cs1)
		);


	basic_rom basic(
		.clk(CLK28),
		.address_in(plus4_addr[13:0]),
		.data_out(basic_data),
		.cs(cs0)
		);
	

colors_to_rgb colordecode(
		.clk(CLK28),
		.color(color),
		.red(red),
		.green(green),
		.blue(blue));





c16_keymatrix keyboard(
	 .clk(CLK28),
    .scancode(keyscancode),
    .receiveflag(keyreceived),
	 .row(keyboard_row),
    .kbus(key),
	 .keyreset(keyreset),
	 .joy0(joy0port),
	 .joy1(joy1port),
	 .esc(key_esc)
    );

mos6529 keyport(
	 .clk(CLK28),
    .data_in(plus4_data),
    .data_out(keyport_data),
    .port_in(8'hff),
    .port_out(keyboard_row),
    .rw(RW),
    .cs(FD3x)
    );



 bootstrap boot(

    .flash_cs(FLASH_CS),
	 .flash_ck(FLASH_CK),
	 .flash_si(FLASH_SI),
	 .flash_so(FLASH_SO),

	 .cs0(boot_cs0),
	 .cs1(boot_cs1),
	 .rw_out(boot_rw),
	 .addr_out(boot_addr),				
	 .addr_ext(boot_addrext),
	 .data_out(boot_data),
	 
	 .reset(1'b0),
	 .boot_enable(raminitdone),
	 .boot_done(boot_done),
	 .cfg_done(cfg_done),
	 .phi(phi0),
	 .clk(CLK28),

	 .cs(boot_cs),
	 .rw_in(RW),
	 .data_in(plus4_data),
	 .addr_in(plus4_addr[2:0])
    );




always @(posedge CLK28) begin
	pla_arm<=mux|(~RAS&phi0&pla_arm);
	end

assign KERN=(plus4_addr[15:8]==8'hfc)?1'b1:1'b0;
assign FD3x=((plus4_addr[15:4]==12'hfd3) & pla_arm & phi0 & ~RAS)?1'b1:1'b0;
assign FDDx=((plus4_addr[15:4]==12'hfdd) & pla_arm & phi0 & ~RAS)?1'b1:1'b0;
assign FD0x=((plus4_addr[15:4]==12'hfd0) & phi0)?1'b1:1'b0;
assign FD1x=((plus4_addr[15:4]==12'hfd1) & pla_arm & phi0 & ~RAS)?1'b1:1'b0;
assign phi2=~RAS & pla_arm & phi0;
assign FD2x=((plus4_addr[15:4]==12'hfd2) & phi0 & ~RAS);
assign FD9x=((plus4_addr[15:4]==12'hfd9) & phi0 & ~RAS);



always @(posedge CLK28) begin
	FDDx_prev<=FDDx;
	if(~FDDx_prev&FDDx&~RW)
		romselect<=plus4_addr[3:0];
	end

always @*	begin
		if(~cs0) begin
			case(romselect[1:0])
					2'b00:	romversion=Basicver;				
					2'b01:	romversion=FunctionLver;
					2'b10:	romversion=C1Lver;
					2'b11:	romversion=C2Lver;
			endcase
			romaddrext={romversion,romselect[1:0]};
		end
		else begin
				case(romselect[3:2])
					2'b00:	romversion=Kernalver;
					2'b01:	romversion=FunctionHver;
					2'b10:	romversion=C1Hver;
					2'b11:	romversion=C2Hver;
				endcase	
				romaddrext=(romconfig)?{4'hf,2'b00}:(KERN)?{Kernalver,2'b00}:{romversion,romselect[3:2]};
		end
end



always @(posedge CLK28)
	begin
	if(sreset&key_esc)
		romconfig<=1;
	else if(sreset)
		romconfig<=0;
	end
	




always @(posedge CLK28)
	begin
	FD9x_prev<=FD9x;
	phi0_prev<=phi0;
	end


always @(posedge CLK28) begin
	romreg_data<=8'hff;
	romconfreset<=1'b0;
	if(FD9x & RW) begin
			case(plus4_addr[3:0])
				4'h0:	romreg_data<={Kernalver,Basicver};
				4'h1:	romreg_data<={FunctionHver,FunctionLver};
				4'h2:	romreg_data<={C1Hver,C1Lver};
				4'h3:	romreg_data<={C2Hver,C2Lver};
				default:romreg_data<=8'hff;
			endcase
		end



	else if((FD9x_prev & ~FD9x & ~RW & romconfig) || (boot_done & ~cfg_done & phi0_prev & ~phi0 & ~boot_rw ))
		begin																				
			case(ram_addr[3:0])
				4'h0: begin
						Kernalver<=config_data[7:4];
						Basicver<=config_data[3:0];
						end
				4'h1:	begin
						FunctionHver<=config_data[7:4];
						FunctionLver<=config_data[3:0];
						end
				4'h2:	begin
						C1Hver<=config_data[7:4];
						C1Lver<=config_data[3:0];
						end
				4'h3:	begin
						C2Hver<=config_data[7:4];
						C2Lver<=config_data[3:0];
						end
				4'h4: begin

						end
				4'h5:	begin

						end
				4'h7: begin
						romconfreset<=1'b1;
						end
			endcase
		end
end

assign boot_cs=FD9x&plus4_addr[3]&(~cfg_done|romconfig);
assign config_data=(cfg_done)?plus4_datalatch:boot_data;




always @(posedge CLK28)
	begin
	if(RESET|keyreset|romconfreset)
		begin
		resetcounter<=0;
		sreset<=1;
		end
	else begin
		if(resetcounter==24'd5000) begin
			if(boot_done)
				sreset<=0;
			end
		else begin
			resetcounter<=resetcounter+1;
			sreset<=1;
			end
		end
	end	



assign rom_data=kernal_data&basic_data;


assign plus4_addr=(~mux)?plus4_addrlatch:cpu_addr&ted_addr;
assign plus4_data=(mux)?plus4_datalatch:cpu_data&ted_data&keyport_data&romreg_data&((~cs0|~cs1)?rom_data:ram_data)&boot_data;


always @(posedge CLK28)
	begin
	plus4_datalatch<=plus4_data;
	plus4_addrlatch<=plus4_addr;
	end



assign joy0emu=(~plus4_data[2])?joy0port:5'b11111;
assign joy1emu=(~plus4_data[1])?joy1port:5'b11111;

assign kbus={key[7]&joy1emu[4],key[6]&joy0emu[4],key[5:4],key[3]&joy0emu[3]&joy1emu[3],key[2]&joy0emu[2]&joy1emu[2],key[1]&joy0emu[1]&joy1emu[1],key[0]&joy0emu[0]&joy1emu[0]};






	
always
		begin
#17.675	CLK28<=~CLK28;
		end

always @(plus4_addr)
	begin
	if (plus4_addr == 16'he6e2)
		$finish;
	end




reg [2:0] bytecount=0;
reg [2:0] bitcount=7;
reg [2:0] cbitcount=0;
reg [7:0] flashreg=8'h03;
integer file;
reg command=1;

always @(negedge FLASH_CK) begin
	if (~FLASH_CS) begin
		if (~command) begin
			bitcount<=bitcount+1;
			if(bitcount==7)
				flashreg<=$fgetc(file);
			else flashreg[7:0]<={flashreg[6:0],1'b0};		
		end

	end
end

always @(posedge FLASH_CK) begin
	if(command) begin
		cbitcount<=cbitcount+1;
		if(cbitcount==7)
			if(bytecount==3)
				command<=0;
			else	bytecount=bytecount+1;
	end
end

assign FLASH_SO=flashreg[7];	
		
always @(posedge cfg_done) begin
	$fclose(file);
end
		


endmodule
module Plus4_testbench;

	
	reg CLK28;
	wire phi0;
	reg phi0_prev;
	reg phi_prev;
	reg sreset=0;
	reg RESET=0;
	reg [7:0] port_in=0;
	wire [7:0] port_out;
	wire [7:0] datain;
	wire aec;
	wire rdy;
	reg enable=0;


	wire irq_n;
   wire [7:0] dataout;
	wire [15:0] addr;
	wire RW;
	wire [6:0] color;
	wire [3:0] red,green,blue;
	wire csync;
	wire RAS,CAS,mux,cs0,cs1;
	
	wire [15:0] plus4_addr,ted_addr,cpu_addr;
	wire [7:0]  plus4_data,ted_data,ram_data,A,cpu_data,basic_data,kernal_data,rom_data;
	wire [7:0] keyboard_row,keyport_data,key,kbus;
	reg [7:0] romreg_data;
	reg  [7:0] plus4_datalatch=0;
	reg [7:0] keyscancode;
	wire [6:0] plus4_color;
	reg [12:0] resetcounter=0;
	reg [15:0] plus4_addrlatch=0;
	wire keyreset;
	wire [4:0] joy0port,joy1port;
	wire [4:0] joy0emu,joy1emu;
	reg keyreceived=0;
	wire cpuenable;
	reg pla_arm;
	wire FD3x;
	wire FDDx;
	reg  FDDx_prev=0;
	wire FD1x;
	wire FD0x;
	reg [3:0] romselect=0;
	reg [3:0] Kernalver=4'h0;
	reg [3:0] Basicver=4'h0;
	reg [3:0] FunctionLver=4'h0;
	reg [3:0] FunctionHver=4'h0;
	reg [3:0] C1Lver=4'h0;
	reg [3:0] C1Hver=4'h0;
	reg [3:0] C2Lver=4'h0;
	reg [3:0] C2Hver=4'h0;
	reg [3:0] romversion;
	reg [5:0] romaddrext;
	reg [5:0] ramaddrext=6'b000000;
	wire [5:0] plus4_addrext;
	reg romconfig=0;
	reg romconfreset=0;
	reg FD9x_prev=0;
	wire boot_cs;
	
	wire [11:0] SDRAM_ADDR;
	wire [15:0] SDRAM_DATA;
	wire SDRAM_DQML;
	wire SDRAM_DQMH;
	wire [1:0] SDRAM_BA;
	wire SDRAM_nWE;
	wire SDRAM_nCAS;
	wire SDRAM_nRAS;
	wire SDRAM_CS;
	wire SDRAM_CKE;

	wire FLASH_SI;
	wire FLASH_SO;
	wire FLASH_CK;
	wire FLASH_CS;
	wire boot_cs0;
	wire boot_cs1;
	wire boot_rw;
	wire [15:0] boot_addr;
	wire [5:0] boot_addrext;
	wire [7:0] boot_data;
	wire [7:0] config_data;
	wire boot_done;
	
	wire sdram_cs0;
	wire sdram_cs1;
	wire sdram_rw;
	wire [15:0] ram_addr;
	wire [5:0] sdram_addrext;
	wire [7:0] sdram_datain;
	
	initial begin

		CLK28=0;
		keyscancode=7'hff;
		keyreceived=1;
		file=$fopen("fakerom.bin","rb");

		#150000;
		port_in=8'hff;
		

						
	end
	

	mos8501 cpu (
		.clk(CLK28), 
		.reset(sreset), 
		.enable(cpuenable),  
		.irq_n(irq_n), 
		.data_in(plus4_data), 
		.data_out(cpu_data), 
		.address(cpu_addr),
		.gate_in(mux),
		.rw(RW),
		.port_in(port_in),
		.port_out(port_out),
		.rdy(rdy),
		.aec(aec)
	);


	ted mos8360(
		.clk(CLK28),
		.addr_in(plus4_addr),
		.addr_out(ted_addr),
		.data_in(plus4_data),
		.data_out(ted_data),
		.rw(RW),
		.cpuclk(phi0),
		.color(color),
		.csync(csync),
		.irq(irq_n),
		.ba(rdy),
		.mux(mux),
		.ras(RAS),
		.cas(CAS),
		.cs0(cs0),
		.cs1(cs1),
		.aec(aec),
		.k(kbus),
		.snd(sound),
		.cpuenable(cpuenable)

		);


 sdram_controller ram_ctrl(
		.sdram_addr(SDRAM_ADDR),
		.sdram_data(SDRAM_DATA),
		.sdram_dqm({SDRAM_DQMH,SDRAM_DQML}),
		.sdram_ba(SDRAM_BA),
		.sdram_we(SDRAM_nWE),
		.sdram_ras(SDRAM_nRAS),
		.sdram_cas(SDRAM_nCAS),
		.sdram_cs(SDRAM_CS),
		.sdram_cke(SDRAM_CKE),
		.clk(CLK28),
		.plus4_addr(ram_addr),
		.plus4_addrext(sdram_addrext),								
		.plus4_ras(RAS),
		.plus4_cas(CAS),
		.plus4_rw(sdram_rw),
		.plus4_cs0(sdram_cs0),
		.plus4_cs1(sdram_cs1),
		.ram_datain(sdram_datain),
		.ram_dataout(ram_data),
		.initdone(raminitdone)
 );



assign ram_addr=(cfg_done)?plus4_addr:boot_addr;
assign sdram_addrext=(boot_done)?plus4_addrext:boot_addrext;
assign sdram_cs0=(boot_done)?cs0:boot_cs0;
assign sdram_cs1=(boot_done)?cs1:boot_cs1;
assign sdram_rw=(boot_done)?RW:boot_rw;
assign sdram_datain=(boot_done)?plus4_data:boot_data;

assign plus4_addrext=(~cs0|~cs1)?romaddrext:ramaddrext;

mt48lc4m16a2 sdram(
	.Dq(SDRAM_DATA),
	.Addr(SDRAM_ADDR),
	.Ba(SDRAM_BA),
	.Clk(~CLK28),
	.Cke(SDRAM_CKE),
	.Cs_n(SDRAM_CS),
	.Ras_n(SDRAM_nRAS),
	.Cas_n(SDRAM_nCAS),
	.We_n(SDRAM_nWE),
	.Dqm({SDRAM_DQMH,SDRAM_DQML})
	);	 


	kernal_rom kernal(
		.clk(CLK28),
		.address_in(plus4_addr[13:0]),
		.data_out(kernal_data),
		.cs(cs1)
		);


	basic_rom basic(
		.clk(CLK28),
		.address_in(plus4_addr[13:0]),
		.data_out(basic_data),
		.cs(cs0)
		);
	

colors_to_rgb colordecode(
		.clk(CLK28),
		.color(color),
		.red(red),
		.green(green),
		.blue(blue));





c16_keymatrix keyboard(
	 .clk(CLK28),
    .scancode(keyscancode),
    .receiveflag(keyreceived),
	 .row(keyboard_row),
    .kbus(key),
	 .keyreset(keyreset),
	 .joy0(joy0port),
	 .joy1(joy1port),
	 .esc(key_esc)
    );

mos6529 keyport(
	 .clk(CLK28),
    .data_in(plus4_data),
    .data_out(keyport_data),
    .port_in(8'hff),
    .port_out(keyboard_row),
    .rw(RW),
    .cs(FD3x)
    );



 bootstrap boot(

    .flash_cs(FLASH_CS),
	 .flash_ck(FLASH_CK),
	 .flash_si(FLASH_SI),
	 .flash_so(FLASH_SO),

	 .cs0(boot_cs0),
	 .cs1(boot_cs1),
	 .rw_out(boot_rw),
	 .addr_out(boot_addr),				
	 .addr_ext(boot_addrext),
	 .data_out(boot_data),
	 
	 .reset(1'b0),
	 .boot_enable(raminitdone),
	 .boot_done(boot_done),
	 .cfg_done(cfg_done),
	 .phi(phi0),
	 .clk(CLK28),

	 .cs(boot_cs),
	 .rw_in(RW),
	 .data_in(plus4_data),
	 .addr_in(plus4_addr[2:0])
    );




always @(posedge CLK28) begin
	pla_arm<=mux|(~RAS&phi0&pla_arm);
	end

assign KERN=(plus4_addr[15:8]==8'hfc)?1'b1:1'b0;
assign FD3x=((plus4_addr[15:4]==12'hfd3) & pla_arm & phi0 & ~RAS)?1'b1:1'b0;
assign FDDx=((plus4_addr[15:4]==12'hfdd) & pla_arm & phi0 & ~RAS)?1'b1:1'b0;
assign FD0x=((plus4_addr[15:4]==12'hfd0) & phi0)?1'b1:1'b0;
assign FD1x=((plus4_addr[15:4]==12'hfd1) & pla_arm & phi0 & ~RAS)?1'b1:1'b0;
assign phi2=~RAS & pla_arm & phi0;
assign FD2x=((plus4_addr[15:4]==12'hfd2) & phi0 & ~RAS);
assign FD9x=((plus4_addr[15:4]==12'hfd9) & phi0 & ~RAS);



always @(posedge CLK28) begin
	FDDx_prev<=FDDx;
	if(~FDDx_prev&FDDx&~RW)
		romselect<=plus4_addr[3:0];
	end

always @*	begin
		if(~cs0) begin
			case(romselect[1:0])
					2'b00:	romversion=Basicver;				
					2'b01:	romversion=FunctionLver;
					2'b10:	romversion=C1Lver;
					2'b11:	romversion=C2Lver;
			endcase
			romaddrext={romversion,romselect[1:0]};
		end
		else begin
				case(romselect[3:2])
					2'b00:	romversion=Kernalver;
					2'b01:	romversion=FunctionHver;
					2'b10:	romversion=C1Hver;
					2'b11:	romversion=C2Hver;
				endcase	
				romaddrext=(romconfig)?{4'hf,2'b00}:(KERN)?{Kernalver,2'b00}:{romversion,romselect[3:2]};
		end
end



always @(posedge CLK28)
	begin
	if(sreset&key_esc)
		romconfig<=1;
	else if(sreset)
		romconfig<=0;
	end
	




always @(posedge CLK28)
	begin
	FD9x_prev<=FD9x;
	phi0_prev<=phi0;
	end


always @(posedge CLK28) begin
	romreg_data<=8'hff;
	romconfreset<=1'b0;
	if(FD9x & RW) begin
			case(plus4_addr[3:0])
				4'h0:	romreg_data<={Kernalver,Basicver};
				4'h1:	romreg_data<={FunctionHver,FunctionLver};
				4'h2:	romreg_data<={C1Hver,C1Lver};
				4'h3:	romreg_data<={C2Hver,C2Lver};
				default:romreg_data<=8'hff;
			endcase
		end



	else if((FD9x_prev & ~FD9x & ~RW & romconfig) || (boot_done & ~cfg_done & phi0_prev & ~phi0 & ~boot_rw ))
		begin																				
			case(ram_addr[3:0])
				4'h0: begin
						Kernalver<=config_data[7:4];
						Basicver<=config_data[3:0];
						end
				4'h1:	begin
						FunctionHver<=config_data[7:4];
						FunctionLver<=config_data[3:0];
						end
				4'h2:	begin
						C1Hver<=config_data[7:4];
						C1Lver<=config_data[3:0];
						end
				4'h3:	begin
						C2Hver<=config_data[7:4];
						C2Lver<=config_data[3:0];
						end
				4'h4: begin

						end
				4'h5:	begin

						end
				4'h7: begin
						romconfreset<=1'b1;
						end
			endcase
		end
end

assign boot_cs=FD9x&plus4_addr[3]&(~cfg_done|romconfig);
assign config_data=(cfg_done)?plus4_datalatch:boot_data;




always @(posedge CLK28)
	begin
	if(RESET|keyreset|romconfreset)
		begin
		resetcounter<=0;
		sreset<=1;
		end
	else begin
		if(resetcounter==24'd5000) begin
			if(boot_done)
				sreset<=0;
			end
		else begin
			resetcounter<=resetcounter+1;
			sreset<=1;
			end
		end
	end	



assign rom_data=kernal_data&basic_data;


assign plus4_addr=(~mux)?plus4_addrlatch:cpu_addr&ted_addr;
assign plus4_data=(mux)?plus4_datalatch:cpu_data&ted_data&keyport_data&romreg_data&((~cs0|~cs1)?rom_data:ram_data)&boot_data;


always @(posedge CLK28)
	begin
	plus4_datalatch<=plus4_data;
	plus4_addrlatch<=plus4_addr;
	end



assign joy0emu=(~plus4_data[2])?joy0port:5'b11111;
assign joy1emu=(~plus4_data[1])?joy1port:5'b11111;

assign kbus={key[7]&joy1emu[4],key[6]&joy0emu[4],key[5:4],key[3]&joy0emu[3]&joy1emu[3],key[2]&joy0emu[2]&joy1emu[2],key[1]&joy0emu[1]&joy1emu[1],key[0]&joy0emu[0]&joy1emu[0]};






	
always
		begin
#17.675	CLK28<=~CLK28;
		end

always @(plus4_addr)
	begin
	if (plus4_addr == 16'he6e2)
		$finish;
	end




reg [2:0] bytecount=0;
reg [2:0] bitcount=7;
reg [2:0] cbitcount=0;
reg [7:0] flashreg=8'h03;
integer file;
reg command=1;

always @(negedge FLASH_CK) begin
	if (~FLASH_CS) begin
		if (~command) begin
			bitcount<=bitcount+1;
			if(bitcount==7)
				flashreg<=$fgetc(file);
			else flashreg[7:0]<={flashreg[6:0],1'b0};		
		end

	end
end

always @(posedge FLASH_CK) begin
	if(command) begin
		cbitcount<=cbitcount+1;
		if(cbitcount==7)
			if(bytecount==3)
				command<=0;
			else	bytecount=bytecount+1;
	end
end

assign FLASH_SO=flashreg[7];	
		
always @(posedge cfg_done) begin
	$fclose(file);
end
		


endmodule