data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top_tb.v
 line:45: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clock = ~clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #16000  \n  ^\n%Error: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top_tb.v:26: Can\'t find definition of \'regFile_inst\' in dotted scope/variable: \'dut.regFile_inst\'\n      $display("Register %d: %h", x, dut.regFile_inst.reg_file[x]);\n                                         ^~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top_tb.v:40: Can\'t find definition of \'main_memory\' in dotted scope/variable: \'dut.main_memory\'\n  $readmemh("/home/nca/Desktop/U10490015_U16716991_project_part2/gcd.vmh", dut.main_memory.ram);  \n                                                                               ^~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/top_tb.v:43: Can\'t find definition of \'regFile_inst\' in dotted scope/variable: \'dut.regFile_inst\'\n    dut.regFile_inst.reg_file[x] = 32\'d0;\n        ^~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb();

reg clock;
reg reset;

wire [31:0] result;

integer x;

top dut (
  .clock(clock),
  .reset(reset),
  .wb_data(result)
);

always #5 clock = ~clock;

task print_state;
  begin
    $display("Time:\t%0d", $time);
    for( x=0; x<32; x=x+1) begin
      $display("Register %d: %h", x, dut.regFile_inst.reg_file[x]);
    end
    $display("--------------------------------------------------------------------------------");
    $display("\n\n");
  end
endtask

initial begin
  clock = 1'b1;
  reset = 1'b1;




  $readmemh("/home/nca/Desktop/U10490015_U16716991_project_part2/gcd.vmh", dut.main_memory.ram);

  for( x=0; x<32; x=x+1) begin
    dut.regFile_inst.reg_file[x] = 32'd0;
  end
  print_state();

  #1
  #20
  reset = 1'b0;
  
  
  #16000
  print_state();
  $stop();

end

endmodule
module top_tb();


reg clock;
reg reset;

wire [31:0] result;

integer x;

top dut (
  .clock(clock),
  .reset(reset),
  .wb_data(result)
);

always #5 clock = ~clock;

task print_state;
  begin
    $display("Time:\t%0d", $time);
    for( x=0; x<32; x=x+1) begin
      $display("Register %d: %h", x, dut.regFile_inst.reg_file[x]);
    end
    $display("--------------------------------------------------------------------------------");
    $display("\n\n");
  end
endtask

initial begin
  clock = 1'b1;
  reset = 1'b1;




  $readmemh("/home/nca/Desktop/U10490015_U16716991_project_part2/gcd.vmh", dut.main_memory.ram);

  for( x=0; x<32; x=x+1) begin
    dut.regFile_inst.reg_file[x] = 32'd0;
  end
  print_state();

  #1
  #20
  reset = 1'b0;
  
  
  #16000
  print_state();
  $stop();

end

endmodule