data/full_repos/permissive/143278/ivltests/land4.v
1: b'%Error: data/full_repos/permissive/143278/ivltests/land4.v:41: Unsupported or unknown PLI call: $monitor\n      $monitor("clk=%b: ena=%b, enb=%b, wea=%b, web=%b --> out=%b",\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/land4.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/land4.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/land4.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/land4.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/land4.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/land4.v:57: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg ena, wea;
   reg enb, web;

   reg clk;
   reg out = 0;

   always @(posedge clk) begin
      if ((ena == 1) && (wea == 1) &&
	  (enb == 1) && (web == 1))
	out <= 1;
   end

   initial begin
      clk = 0;
      ena = 0;
      enb = 0;
      wea = 0;
      web = 0;

      $monitor("clk=%b: ena=%b, enb=%b, wea=%b, web=%b --> out=%b",
	       clk, ena, enb, wea, web, out);

      #1 clk = 1;
      #1 clk = 0;

      ena = 1;
      enb = 1;

      #1 clk = 1;
      #1 clk = 0;

      wea = 1;
      web = 1;

      #1 clk = 1;
      #1 clk = 0;
   end

endmodule
module main;


   reg ena, wea;
   reg enb, web;

   reg clk;
   reg out = 0;

   always @(posedge clk) begin
      if ((ena == 1) && (wea == 1) &&
	  (enb == 1) && (web == 1))
	out <= 1;
   end

   initial begin
      clk = 0;
      ena = 0;
      enb = 0;
      wea = 0;
      web = 0;

      $monitor("clk=%b: ena=%b, enb=%b, wea=%b, web=%b --> out=%b",
	       clk, ena, enb, wea, web, out);

      #1 clk = 1;
      #1 clk = 0;

      ena = 1;
      enb = 1;

      #1 clk = 1;
      #1 clk = 0;

      wea = 1;
      web = 1;

      #1 clk = 1;
      #1 clk = 0;
   end

endmodule