data/full_repos/permissive/203165721/test_signal.v
data/verilator_xmls/a136b114-e91c-4c8a-92bf-ef8cb4459073.xml
module test_signal
(	
	input	       clk,
	input	[15:0] in,
	output  reg[15:0] out
);



always @ (posedge clk)
begin
	out <= in;
end


endmodule
module test_signal
(	
	input	       clk,
	input	[15:0] in,
	output  reg[15:0] out
);




always @ (posedge clk)
begin
	out <= in;
end


endmodule