data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/multi_bit_check.v
1: b'%Warning-WIDTH: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/multi_bit_check.v:67: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                : ... In instance multi_bit_check\n        sum = sum + data_in[j];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
function integer log2;
input [32:0] depth;
integer i;
begin
    log2 = 1;
    for (i=0; 2**i < depth; i=i+1)
        log2 = i + 1;
end
endfunction
function integer log2;

input [32:0] depth;
integer i;
begin
    log2 = 1;
    for (i=0; 2**i < depth; i=i+1)
        log2 = i + 1;
end
endfunction