data/full_repos/permissive/170365068/Splitted modules/Main modules/mips.v
1: b'%Error: Cannot find file containing module: modules/Main\n        ... Looked in:\n             data/full_repos/permissive/170365068/Splitted/modules/Main\n             data/full_repos/permissive/170365068/Splitted/modules/Main.v\n             data/full_repos/permissive/170365068/Splitted/modules/Main.sv\n             modules/Main\n             modules/Main.v\n             modules/Main.sv\n             obj_dir/modules/Main\n             obj_dir/modules/Main.v\n             obj_dir/modules/Main.sv\n%Error: Cannot find file containing module: modules,data/full_repos/permissive/170365068\n%Error: Cannot find file containing module: data/full_repos/permissive/170365068/Splitted\n%Error: Cannot find file containing module: modules/mips.v\n%Error: Exiting due to 4 error(s)\n'
module mips(input clk,reset,output[31:0] pc_out, alu_result);
	
	
	reg [31:0] PC;
	wire [31:0] pc_next,signExOut;
	wire [31:0] Instruction,WriteData,ReadData1,ReadData2,ALUin,ALUResult,MemoryData;
	wire RegDst,Branch,BranchTest,MemRead,Jump,MemtoReg,MemWrite,ALUSrc,RegWrite,zero;
	wire [1:0] ALUOp;
	wire [3:0] ALUCon;
	wire [4:0] WriteRegister;
	
	always @(posedge clk or posedge reset)  
	 begin   
		  if(reset)   
			   PC <= 0;  
		  else  
			   PC <= pc_next;  
	 end
	

	InstructionMemory InstructionMemory1(.ReadAddress(PC),.Instruction(Instruction));
	

	control control1(.reset(reset),.instruction5(Instruction[31:26]),.RegDst(RegDst),.Branch(Branch),
						.Jump(Jump),.MemRead(MemRead),.MemtoReg(MemtoReg),.ALUOp(ALUOp),
						.MemWrite(MemWrite),.ALUSrc(ALUSrc),.RegWrite(RegWrite),.BranchTest(BranchTest));
	

	assign WriteRegister=RegDst?Instruction[15:11]:Instruction[20:16];
	

	Registers registers1(.clk(clk),.ReadRegister1(Instruction[25:21]),.ReadRegister2(Instruction[20:16]),
						.WriteRegister(WriteRegister),.WriteData(WriteData),.ReadData1(ReadData1),
						.ReadData2(ReadData2),.RegWrite(RegWrite),.reset(reset));
	

	ALUControl ALUControl1(.instruction1(Instruction[5:0]),.ALUop(ALUOp),.ALUCon(ALUCon));
	

	assign signExOut={{16{1'b0}},Instruction[15:0]};
	

	mux32 mux32ALU(.D0(ReadData2),.D1(signExOut),.select(ALUSrc),.Out(ALUin));
	

	ALU ALU1(.A(ReadData1),.B(ALUin),.ALUCon(ALUCon),.Zero(zero),.ALUResult(ALUResult));
	

	DataMemory DataMemory1(.clk(clk),.Address(ALUResult),.WriteData(ReadData2),.ReadData(MemoryData),
							.MemRead(MemRead),.MemWrite(MemWrite),.reset(reset));
							

	mux32 mux32DataMem(.D0(ALUResult),.D1(MemoryData),.select(MemtoReg),.Out(WriteData));
	

	pcModule pcModule1(.Zero(zero),.Branch(Branch),.BranchTest(BranchTest),.Jump(Jump),.PC(PC),.instruction1(signExOut),.instruction6(Instruction[25:0]),.pc_next(pc_next));
	

	assign pc_out=pc_next;
	assign alu_result=ALUResult;

endmodule
module mips(input clk,reset,output[31:0] pc_out, alu_result);

	
	
	reg [31:0] PC;
	wire [31:0] pc_next,signExOut;
	wire [31:0] Instruction,WriteData,ReadData1,ReadData2,ALUin,ALUResult,MemoryData;
	wire RegDst,Branch,BranchTest,MemRead,Jump,MemtoReg,MemWrite,ALUSrc,RegWrite,zero;
	wire [1:0] ALUOp;
	wire [3:0] ALUCon;
	wire [4:0] WriteRegister;
	
	always @(posedge clk or posedge reset)  
	 begin   
		  if(reset)   
			   PC <= 0;  
		  else  
			   PC <= pc_next;  
	 end
	

	InstructionMemory InstructionMemory1(.ReadAddress(PC),.Instruction(Instruction));
	

	control control1(.reset(reset),.instruction5(Instruction[31:26]),.RegDst(RegDst),.Branch(Branch),
						.Jump(Jump),.MemRead(MemRead),.MemtoReg(MemtoReg),.ALUOp(ALUOp),
						.MemWrite(MemWrite),.ALUSrc(ALUSrc),.RegWrite(RegWrite),.BranchTest(BranchTest));
	

	assign WriteRegister=RegDst?Instruction[15:11]:Instruction[20:16];
	

	Registers registers1(.clk(clk),.ReadRegister1(Instruction[25:21]),.ReadRegister2(Instruction[20:16]),
						.WriteRegister(WriteRegister),.WriteData(WriteData),.ReadData1(ReadData1),
						.ReadData2(ReadData2),.RegWrite(RegWrite),.reset(reset));
	

	ALUControl ALUControl1(.instruction1(Instruction[5:0]),.ALUop(ALUOp),.ALUCon(ALUCon));
	

	assign signExOut={{16{1'b0}},Instruction[15:0]};
	

	mux32 mux32ALU(.D0(ReadData2),.D1(signExOut),.select(ALUSrc),.Out(ALUin));
	

	ALU ALU1(.A(ReadData1),.B(ALUin),.ALUCon(ALUCon),.Zero(zero),.ALUResult(ALUResult));
	

	DataMemory DataMemory1(.clk(clk),.Address(ALUResult),.WriteData(ReadData2),.ReadData(MemoryData),
							.MemRead(MemRead),.MemWrite(MemWrite),.reset(reset));
							

	mux32 mux32DataMem(.D0(ALUResult),.D1(MemoryData),.select(MemtoReg),.Out(WriteData));
	

	pcModule pcModule1(.Zero(zero),.Branch(Branch),.BranchTest(BranchTest),.Jump(Jump),.PC(PC),.instruction1(signExOut),.instruction6(Instruction[25:0]),.pc_next(pc_next));
	

	assign pc_out=pc_next;
	assign alu_result=ALUResult;

endmodule