data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-2_sumador_restador/sumsub_tb.v
1: b'%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-2_sumador_restador/sumsub_tb.v:56: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-2_sumador_restador/sumsub_tb.v:57: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-2_sumador_restador/sumsub_tb.v:65: Unsupported or unknown PLI call: $monitor\n        $monitor("%d %d  %d  %b",\n        ^~~~~~~~\n%Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-2_sumador_restador/sumsub_tb.v:77: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n        a = $random(seed);\n            ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/111433415/verilog/05_aritmeticos/05-2_sumador_restador/sumsub_tb.v:77: ../V3Ast.cpp:358: Null item passed to setOp1p\n        a = $random(seed);\n          ^\n                        ... See the manual and https://verilator.org for more assistance.\n'
module test ();

    reg signed [7:0] a;
    reg signed [7:0] b;
    reg op = `OP;
    wire signed [7:0] f;
    wire ov;
    integer np;
    integer seed = `SEED;



    sumsub1 #(.WIDTH(8)) uut(.a(a), .b(b), .op(op), .f(f), .ov(ov));

    initial begin

        np = `NP;


        $dumpfile("test.vcd");
        $dumpvars(0, test);


        if (op == 0)
            $display("Operacion: SUMA");
        else
            $display("Operacion: RESTA");
        $display("   A    B     f  ov");
        $monitor("%d %d  %d  %b",
                   a, b, f, ov);
    end



    always begin
        #20
        a = $random(seed);
        b = $random(seed);
        np = np - 1;
        if (np == 0)
            $finish;
    end
endmodule
module test ();


    reg signed [7:0] a;
    reg signed [7:0] b;
    reg op = `OP;
    wire signed [7:0] f;
    wire ov;
    integer np;
    integer seed = `SEED;



    sumsub1 #(.WIDTH(8)) uut(.a(a), .b(b), .op(op), .f(f), .ov(ov));

    initial begin

        np = `NP;


        $dumpfile("test.vcd");
        $dumpvars(0, test);


        if (op == 0)
            $display("Operacion: SUMA");
        else
            $display("Operacion: RESTA");
        $display("   A    B     f  ov");
        $monitor("%d %d  %d  %b",
                   a, b, f, ov);
    end



    always begin
        #20
        a = $random(seed);
        b = $random(seed);
        np = np - 1;
        if (np == 0)
            $finish;
    end
endmodule