data/full_repos/permissive/133819542/src/if_id.v
1: b'%Error: data/full_repos/permissive/133819542/src/if_id.v:7: Cannot find include file: const.v\n`include "const.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v.v\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v.sv\n             const.v\n             const.v.v\n             const.v.sv\n             obj_dir/const.v\n             obj_dir/const.v.v\n             obj_dir/const.v.sv\n%Error: data/full_repos/permissive/133819542/src/if_id.v:13: Define or directive not defined: \'`InstAddrBus\'\n    input wire  [`InstAddrBus]    if_pc    ,\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/if_id.v:13: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire  [`InstAddrBus]    if_pc    ,\n                             ^\n%Error: data/full_repos/permissive/133819542/src/if_id.v:14: Define or directive not defined: \'`InstBus\'\n    input wire  [`InstBus    ]    if_inst  ,\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/if_id.v:16: Define or directive not defined: \'`StallBus\'\n    input wire  [`StallBus   ]    stall    ,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/if_id.v:18: Define or directive not defined: \'`InstAddrBus\'\n    output reg  [`InstAddrBus]    id_pc    ,\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/if_id.v:19: Define or directive not defined: \'`InstBus\'\n    output reg  [`InstBus    ]    id_inst  \n                 ^~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/if_id.v:24: Define or directive not defined: \'`RESET_ENABLE\'\n        if(rst == `RESET_ENABLE || (stall[1] == `STOP && stall[2] == `NOSTOP)) begin\n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/if_id.v:24: Define or directive not defined: \'`STOP\'\n        if(rst == `RESET_ENABLE || (stall[1] == `STOP && stall[2] == `NOSTOP)) begin\n                                                ^~~~~\n%Error: data/full_repos/permissive/133819542/src/if_id.v:24: Define or directive not defined: \'`NOSTOP\'\n        if(rst == `RESET_ENABLE || (stall[1] == `STOP && stall[2] == `NOSTOP)) begin\n                                                                     ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/if_id.v:25: Define or directive not defined: \'`ZERO_WORD\'\n            id_pc   <=  `ZERO_WORD;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/if_id.v:26: Define or directive not defined: \'`ZERO_WORD\'\n            id_inst <=  `ZERO_WORD;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/if_id.v:27: Define or directive not defined: \'`NOSTOP\'\n        end else if (stall[1] == `NOSTOP) begin\n                                 ^~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module if_id (
    input wire                    clk      ,
    input wire                    rst      ,

    input wire  [`InstAddrBus]    if_pc    ,
    input wire  [`InstBus    ]    if_inst  ,

    input wire  [`StallBus   ]    stall    ,

    output reg  [`InstAddrBus]    id_pc    ,
    output reg  [`InstBus    ]    id_inst  
);
    

    always @(posedge clk) begin
        if(rst == `RESET_ENABLE || (stall[1] == `STOP && stall[2] == `NOSTOP)) begin
            id_pc   <=  `ZERO_WORD;
            id_inst <=  `ZERO_WORD;
        end else if (stall[1] == `NOSTOP) begin
            id_pc   <= if_pc;
            id_inst <= if_inst;
        end
    end

endmodule
module if_id (
    input wire                    clk      ,
    input wire                    rst      ,

    input wire  [`InstAddrBus]    if_pc    ,
    input wire  [`InstBus    ]    if_inst  ,

    input wire  [`StallBus   ]    stall    ,

    output reg  [`InstAddrBus]    id_pc    ,
    output reg  [`InstBus    ]    id_inst  
);

    

    always @(posedge clk) begin
        if(rst == `RESET_ENABLE || (stall[1] == `STOP && stall[2] == `NOSTOP)) begin
            id_pc   <=  `ZERO_WORD;
            id_inst <=  `ZERO_WORD;
        end else if (stall[1] == `NOSTOP) begin
            id_pc   <= if_pc;
            id_inst <= if_inst;
        end
    end

endmodule