data/full_repos/permissive/207111076/jt51/filter/jt51_interpol.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/207111076/jt51/filter/jt51_interpol.v:78: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                   : ... In instance jt51_interpol\n state <= 2\'b0;\n       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/207111076/jt51/filter/jt51_interpol.v:80: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                                   : ... In instance jt51_interpol\n cnt   <= 6\'d0;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/207111076/jt51/filter/jt51_interpol.v:84: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                                   : ... In instance jt51_interpol\n  cnt   <= 6\'d0;\n        ^~\n%Error: data/full_repos/permissive/207111076/jt51/filter/jt51_interpol.v:107: Cannot find file containing module: \'jt51_fir8\'\njt51_fir8 #(.data_width(16), .output_width(fir8_w)) u_fir8 (\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207111076/jt51/filter,data/full_repos/permissive/207111076/jt51_fir8\n             data/full_repos/permissive/207111076/jt51/filter,data/full_repos/permissive/207111076/jt51_fir8.v\n             data/full_repos/permissive/207111076/jt51/filter,data/full_repos/permissive/207111076/jt51_fir8.sv\n             jt51_fir8\n             jt51_fir8.v\n             jt51_fir8.sv\n             obj_dir/jt51_fir8\n             obj_dir/jt51_fir8.v\n             obj_dir/jt51_fir8.sv\n%Error: data/full_repos/permissive/207111076/jt51/filter/jt51_interpol.v:118: Cannot find file containing module: \'jt51_fir4\'\njt51_fir4 #(.data_width(16), .output_width(fir4_w)) u_fir4 (\n^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module jt51_interpol(
	input	clk,
	input	rst,
	input	sample_in,
	input	signed [15:0] left_in,
	input	signed [15:0] right_in,




	input	signed [15:0] left_other,
	input	signed [15:0] right_other,		
	
	output  signed [15:0] out_l,
	output  signed [15:0] out_r,
	output	sample_out
);


parameter max_clk_count = 7'd111;

reg [15:0] fir_left_in, fir_right_in, left_mux, right_mux;
reg	fir_sample_in;
reg fir4_sample_in;


reg [2:0] state;
reg [6:0] cnt;

always @(*)
	case( state )
		3'd0: { left_mux, right_mux } <= { left_in, right_in};
		3'd3: { left_mux, right_mux } <= { left_other, right_other};
		default: { left_mux, right_mux } <= 32'd0;
	endcase

always @(posedge clk)
if( rst ) begin
	state <= 2'b0;
	fir_sample_in <= 1'b0;
	cnt	  <= 6'd0;
end else begin
	fir4_sample_in <= ( cnt==0 || cnt==28 || cnt==56 || cnt==84 );
	if( cnt==max_clk_count ) begin
		cnt	  <= 6'd0;
		state <= state+1'b1;
		fir_sample_in <= 1'b1;
		{fir_left_in,fir_right_in} <= { left_mux, right_mux };
	end
	else begin
		cnt <= cnt + 1'b1;	
		fir_sample_in <= 1'b0;
	end
end

localparam fir8_w=16;
localparam fir4_w=16;
wire [fir8_w-1:0] fir8_out_l, fir8_out_r;
wire [fir4_w-1:0] fir4_out_l, fir4_out_r;

assign out_l = fir4_out_l[15:0];
assign out_r = fir4_out_r[15:0];





jt51_fir8 #(.data_width(16), .output_width(fir8_w)) u_fir8 (
	.clk		( clk 			),
	.rst		( rst  			),
	.sample		( fir_sample_in ),
	.left_in	( fir_left_in 	),
	.right_in	( fir_right_in 	),
	.left_out	( fir8_out_l	),
	.right_out	( fir8_out_r	)

);

jt51_fir4 #(.data_width(16), .output_width(fir4_w)) u_fir4 (
	.clk		( clk 			),
	.rst		( rst  			),
	.sample		( fir4_sample_in),
	.left_in	( fir8_out_l[fir8_w-1:fir8_w-16]	),
	.right_in	( fir8_out_r[fir8_w-1:fir8_w-16]	),
	.left_out	( fir4_out_l	),
	.right_out	( fir4_out_r	),
	.sample_out	( sample_out	)
);


endmodule
module jt51_interpol(
	input	clk,
	input	rst,
	input	sample_in,
	input	signed [15:0] left_in,
	input	signed [15:0] right_in,




	input	signed [15:0] left_other,
	input	signed [15:0] right_other,		
	
	output  signed [15:0] out_l,
	output  signed [15:0] out_r,
	output	sample_out
);



parameter max_clk_count = 7'd111;

reg [15:0] fir_left_in, fir_right_in, left_mux, right_mux;
reg	fir_sample_in;
reg fir4_sample_in;


reg [2:0] state;
reg [6:0] cnt;

always @(*)
	case( state )
		3'd0: { left_mux, right_mux } <= { left_in, right_in};
		3'd3: { left_mux, right_mux } <= { left_other, right_other};
		default: { left_mux, right_mux } <= 32'd0;
	endcase

always @(posedge clk)
if( rst ) begin
	state <= 2'b0;
	fir_sample_in <= 1'b0;
	cnt	  <= 6'd0;
end else begin
	fir4_sample_in <= ( cnt==0 || cnt==28 || cnt==56 || cnt==84 );
	if( cnt==max_clk_count ) begin
		cnt	  <= 6'd0;
		state <= state+1'b1;
		fir_sample_in <= 1'b1;
		{fir_left_in,fir_right_in} <= { left_mux, right_mux };
	end
	else begin
		cnt <= cnt + 1'b1;	
		fir_sample_in <= 1'b0;
	end
end

localparam fir8_w=16;
localparam fir4_w=16;
wire [fir8_w-1:0] fir8_out_l, fir8_out_r;
wire [fir4_w-1:0] fir4_out_l, fir4_out_r;

assign out_l = fir4_out_l[15:0];
assign out_r = fir4_out_r[15:0];





jt51_fir8 #(.data_width(16), .output_width(fir8_w)) u_fir8 (
	.clk		( clk 			),
	.rst		( rst  			),
	.sample		( fir_sample_in ),
	.left_in	( fir_left_in 	),
	.right_in	( fir_right_in 	),
	.left_out	( fir8_out_l	),
	.right_out	( fir8_out_r	)

);

jt51_fir4 #(.data_width(16), .output_width(fir4_w)) u_fir4 (
	.clk		( clk 			),
	.rst		( rst  			),
	.sample		( fir4_sample_in),
	.left_in	( fir8_out_l[fir8_w-1:fir8_w-16]	),
	.right_in	( fir8_out_r[fir8_w-1:fir8_w-16]	),
	.left_out	( fir4_out_l	),
	.right_out	( fir4_out_r	),
	.sample_out	( sample_out	)
);


endmodule