data/full_repos/permissive/185628295/hdl/delay_tb.v
 line:277: before: ";"
1: b'%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:18: Cannot find include file: delay.v\n`include "delay.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/185628295/hdl,data/full_repos/permissive/185628295/delay.v\n             data/full_repos/permissive/185628295/hdl,data/full_repos/permissive/185628295/delay.v.v\n             data/full_repos/permissive/185628295/hdl,data/full_repos/permissive/185628295/delay.v.sv\n             delay.v\n             delay.v.v\n             delay.v.sv\n             obj_dir/delay.v\n             obj_dir/delay.v.v\n             obj_dir/delay.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/185628295/hdl/delay_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:31: Unsupported: event data types\n    event end_trigger;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/185628295/hdl/delay_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    initial #1 display_header();\n            ^\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:122: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:130: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:148: syntax error, unexpected \'@\'\n        repeat(5) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:154: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:158: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:162: syntax error, unexpected \'@\'\n        repeat(5) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:169: syntax error, unexpected \'@\'\n        repeat(5) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:174: syntax error, unexpected \'@\'\n            @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:178: syntax error, unexpected \'@\'\n        repeat(5) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:184: syntax error, unexpected \'@\'\n            @(negedge clk);\n            ^\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:188: syntax error, unexpected \'@\'\n        repeat(15) @(negedge clk);\n                   ^\n%Error: data/full_repos/permissive/185628295/hdl/delay_tb.v:194: syntax error, unexpected ->\n        -> end_trigger;\n        ^~\n%Error: Exiting due to 14 error(s), 2 warning(s)\n'
module delay_tb;




    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam HEIGHT_NB    = 3;
    localparam IMG_WIDTH    = 8;

    localparam MEM_AWIDTH   = 8;
    localparam MEM_DEPTH    = 15;


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'delay'");
    end
`endif



    reg  [MEM_AWIDTH-1:0]           cfg_delay;
    reg                             cfg_set;

    reg  [IMG_WIDTH-1:0]            up_data;
    reg                             up_val;

    wire [IMG_WIDTH*HEIGHT_NB-1:0]  delay_bus;
    wire                            delay_val;




    delay #(
        .HEIGHT_NB  (HEIGHT_NB),
        .IMG_WIDTH  (IMG_WIDTH),

        .MEM_AWIDTH (MEM_AWIDTH),
        .MEM_DEPTH  (MEM_DEPTH))
    uut (
        .clk        (clk),

        .cfg_delay  (cfg_delay),
        .cfg_set    (cfg_set),

        .up_data    (up_data),
        .up_val     (up_val),

        .delay_bus  (delay_bus),
        .delay_val  (delay_val)
    );




    task display_signals;
        $display(
            "%d",
            $time,

            "\tup <data: %d, val: %b>",
            up_data,
            up_val,

            "\tdn <data: %d %d %d, val: %b>",
            delay_bus[(2*IMG_WIDTH) +: IMG_WIDTH],
            delay_bus[(1*IMG_WIDTH) +: IMG_WIDTH],
            delay_bus[(0*IMG_WIDTH) +: IMG_WIDTH],
            delay_val,
        );

    endtask

    task display_header;
        $display(
            "\t\ttime",

        );
    endtask




    initial begin

        cfg_delay   = 'b0;
        cfg_set     = 1'b0;

        up_data     = 'b0;
        up_val      = 1'b0;



        repeat(5) @(negedge clk);

`ifdef TB_VERBOSE
    $display("send cfg delay");
`endif

        @(negedge clk);

        cfg_delay   <= 'd10;
        cfg_set     <= 1'b1;
        @(negedge clk);

        cfg_delay   <= 'b0;
        cfg_set     <= 1'b0;
        repeat(5) @(negedge clk);


`ifdef TB_VERBOSE
    $display("send image data");
`endif

        repeat(5) @(negedge clk);

        repeat(30) begin
            up_data <= up_data + 1;
            up_val  <= 1'b1;
            @(negedge clk);
        end

        up_val  <= 1'b0;
        repeat(5) @(negedge clk);


        repeat(30) begin
            up_data <= up_data + 1;
            up_val  <= 1'b1;
            @(negedge clk);
        end
        up_data <= 'b0;
        up_val  <= 1'b0;
        repeat(15) @(negedge clk);


`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule
module delay_tb;





    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam HEIGHT_NB    = 3;
    localparam IMG_WIDTH    = 8;

    localparam MEM_AWIDTH   = 8;
    localparam MEM_DEPTH    = 15;


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'delay'");
    end
`endif



    reg  [MEM_AWIDTH-1:0]           cfg_delay;
    reg                             cfg_set;

    reg  [IMG_WIDTH-1:0]            up_data;
    reg                             up_val;

    wire [IMG_WIDTH*HEIGHT_NB-1:0]  delay_bus;
    wire                            delay_val;




    delay #(
        .HEIGHT_NB  (HEIGHT_NB),
        .IMG_WIDTH  (IMG_WIDTH),

        .MEM_AWIDTH (MEM_AWIDTH),
        .MEM_DEPTH  (MEM_DEPTH))
    uut (
        .clk        (clk),

        .cfg_delay  (cfg_delay),
        .cfg_set    (cfg_set),

        .up_data    (up_data),
        .up_val     (up_val),

        .delay_bus  (delay_bus),
        .delay_val  (delay_val)
    );




    task display_signals;
        $display(
            "%d",
            $time,

            "\tup <data: %d, val: %b>",
            up_data,
            up_val,

            "\tdn <data: %d %d %d, val: %b>",
            delay_bus[(2*IMG_WIDTH) +: IMG_WIDTH],
            delay_bus[(1*IMG_WIDTH) +: IMG_WIDTH],
            delay_bus[(0*IMG_WIDTH) +: IMG_WIDTH],
            delay_val,
        );

    endtask

    task display_header;
        $display(
            "\t\ttime",

        );
    endtask




    initial begin

        cfg_delay   = 'b0;
        cfg_set     = 1'b0;

        up_data     = 'b0;
        up_val      = 1'b0;



        repeat(5) @(negedge clk);

`ifdef TB_VERBOSE
    $display("send cfg delay");
`endif

        @(negedge clk);

        cfg_delay   <= 'd10;
        cfg_set     <= 1'b1;
        @(negedge clk);

        cfg_delay   <= 'b0;
        cfg_set     <= 1'b0;
        repeat(5) @(negedge clk);


`ifdef TB_VERBOSE
    $display("send image data");
`endif

        repeat(5) @(negedge clk);

        repeat(30) begin
            up_data <= up_data + 1;
            up_val  <= 1'b1;
            @(negedge clk);
        end

        up_val  <= 1'b0;
        repeat(5) @(negedge clk);


        repeat(30) begin
            up_data <= up_data + 1;
            up_val  <= 1'b1;
            @(negedge clk);
        end
        up_data <= 'b0;
        up_val  <= 1'b0;
        repeat(15) @(negedge clk);


`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule