data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v
None: at end of input
1: b'%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:28: Cannot find include file: spio_spinnaker_link.h\n`include "spio_spinnaker_link.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.v\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.sv\n             spio_spinnaker_link.h\n             spio_spinnaker_link.h.v\n             spio_spinnaker_link.h.sv\n             obj_dir/spio_spinnaker_link.h\n             obj_dir/spio_spinnaker_link.h.v\n             obj_dir/spio_spinnaker_link.h.sv\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:44: Define or directive not defined: \'`PKT_BITS\'\n  input      [`PKT_BITS - 1:0] PKT_DATA_IN,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:105: Define or directive not defined: \'`PKT_BITS\'\n  input       [`PKT_BITS - 1:0] PKT_DATA_IN,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_sender.v:129: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] pkt_buf;    \n         ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module pkt_serializer
(
  input                         CLK_IN,
  input                         RESET_IN,


  input       [`PKT_BITS - 1:0] PKT_DATA_IN,
  input                         PKT_VLD_IN,
  output reg                    PKT_RDY_OUT,


  output reg              [6:0] flt_data,
  output reg                    flt_vld,
  input                         flt_rdy
);





  localparam STATE_BITS = 2;
  localparam IDLE_ST    = 0;
  localparam PARK_ST    = IDLE_ST + 1;
  localparam TRAN_ST    = PARK_ST + 1;





  reg                     pkt_acpt;
  reg   [`PKT_BITS - 1:0] pkt_buf;
  reg                     pkt_long;

  reg                     flt_busy;
  reg               [4:0] flt_cnt;

  reg                     eop;

  reg  [STATE_BITS - 1:0] state;





  function [6:0] encode_nrz_2of7 ;
    input [4:0] din;
    input [6:0] old_din;

    casex (din)
      5'b00000 : encode_nrz_2of7 = old_din ^ 7'b0010001;
      5'b00001 : encode_nrz_2of7 = old_din ^ 7'b0010010;
      5'b00010 : encode_nrz_2of7 = old_din ^ 7'b0010100;
      5'b00011 : encode_nrz_2of7 = old_din ^ 7'b0011000;
      5'b00100 : encode_nrz_2of7 = old_din ^ 7'b0100001;
      5'b00101 : encode_nrz_2of7 = old_din ^ 7'b0100010;
      5'b00110 : encode_nrz_2of7 = old_din ^ 7'b0100100;
      5'b00111 : encode_nrz_2of7 = old_din ^ 7'b0101000;
      5'b01000 : encode_nrz_2of7 = old_din ^ 7'b1000001;
      5'b01001 : encode_nrz_2of7 = old_din ^ 7'b1000010;
      5'b01010 : encode_nrz_2of7 = old_din ^ 7'b1000100;
      5'b01011 : encode_nrz_2of7 = old_din ^ 7'b1001000;
      5'b01100 : encode_nrz_2of7 = old_din ^ 7'b0000011;
      5'b01101 : encode_nrz_2of7 = old_din ^ 7'b0000110;
      5'b01110 : encode_nrz_2of7 = old_din ^ 7'b0001100;
      5'b01111 : encode_nrz_2of7 = old_din ^ 7'b0001001;
      5'b1xxxx : encode_nrz_2of7 = old_din ^ 7'b1100000;
      default  : encode_nrz_2of7 = 7'bxxxxxxx;
    endcase
  endfunction





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      PKT_RDY_OUT <= 1'b0;
    else
      case (state)
        IDLE_ST: if (pkt_acpt)
                   PKT_RDY_OUT <= 1'b0;
                 else
                   PKT_RDY_OUT <= 1'b1;

        PARK_ST:   PKT_RDY_OUT <= 1'b0;

        default: if (eop && !flt_busy)
                   PKT_RDY_OUT <= 1'b1;
                 else
                   PKT_RDY_OUT <= 1'b0;
      endcase 





  always @ (*)
    pkt_acpt = (PKT_VLD_IN && PKT_RDY_OUT);





  always @(posedge CLK_IN)
    case (state)
      IDLE_ST:
        case ({pkt_acpt, flt_busy})
          2'b10:   pkt_buf <= PKT_DATA_IN >> 4;
          2'b11:   pkt_buf <= PKT_DATA_IN;
        endcase

      default: if (!flt_busy)
                   pkt_buf <= pkt_buf >> 4;
    endcase 





  always @(posedge CLK_IN)
    if ((state == IDLE_ST) && pkt_acpt)
      pkt_long <= PKT_DATA_IN[1];





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_data <= 7'd0;
    else
      case (state)
        IDLE_ST: if (pkt_acpt && !flt_busy)
                   flt_data <= encode_nrz_2of7 ({1'b0, PKT_DATA_IN[3:0]},
                                                 flt_data
                                               );

        default: if (!flt_busy)
                   flt_data <= encode_nrz_2of7 ({eop, pkt_buf[3:0]},
                                                 flt_data
                                               );

      endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_vld <= 1'b0;
    else
      case (state)
        IDLE_ST: if (!flt_busy)
                   if (pkt_acpt)
                     flt_vld <= 1'b1;
                   else
                     flt_vld <= 1'b0;

        default: flt_vld <= 1'b1;
      endcase 





  always @ (*)
    flt_busy = flt_vld && !flt_rdy;





  always @(posedge CLK_IN)
    case (state)
      IDLE_ST,
      PARK_ST:   flt_cnt <= 1;

      default: if (!flt_busy)
                 flt_cnt <= flt_cnt + 1;
    endcase 





  always @ (*)
    eop = (!pkt_long && (flt_cnt == 10)) || (flt_cnt == 18);





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      state <= IDLE_ST;
    else
      case (state)
        IDLE_ST:
          case ({pkt_acpt, flt_busy})
            2'b10:   state <= TRAN_ST;
	    2'b11:   state <= PARK_ST;
            default: state <= IDLE_ST;
          endcase

        PARK_ST: if (!flt_busy)
                     state <= TRAN_ST;   

        default: if (eop && !flt_busy)
                     state <= IDLE_ST;
      endcase 
endmodule
module pkt_serializer
(
  input                         CLK_IN,
  input                         RESET_IN,


  input       [`PKT_BITS - 1:0] PKT_DATA_IN,
  input                         PKT_VLD_IN,
  output reg                    PKT_RDY_OUT,


  output reg              [6:0] flt_data,
  output reg                    flt_vld,
  input                         flt_rdy
);






  localparam STATE_BITS = 2;
  localparam IDLE_ST    = 0;
  localparam PARK_ST    = IDLE_ST + 1;
  localparam TRAN_ST    = PARK_ST + 1;





  reg                     pkt_acpt;
  reg   [`PKT_BITS - 1:0] pkt_buf;
  reg                     pkt_long;

  reg                     flt_busy;
  reg               [4:0] flt_cnt;

  reg                     eop;

  reg  [STATE_BITS - 1:0] state;





  function [6:0] encode_nrz_2of7 ;
    input [4:0] din;
    input [6:0] old_din;

    casex (din)
      5'b00000 : encode_nrz_2of7 = old_din ^ 7'b0010001;
      5'b00001 : encode_nrz_2of7 = old_din ^ 7'b0010010;
      5'b00010 : encode_nrz_2of7 = old_din ^ 7'b0010100;
      5'b00011 : encode_nrz_2of7 = old_din ^ 7'b0011000;
      5'b00100 : encode_nrz_2of7 = old_din ^ 7'b0100001;
      5'b00101 : encode_nrz_2of7 = old_din ^ 7'b0100010;
      5'b00110 : encode_nrz_2of7 = old_din ^ 7'b0100100;
      5'b00111 : encode_nrz_2of7 = old_din ^ 7'b0101000;
      5'b01000 : encode_nrz_2of7 = old_din ^ 7'b1000001;
      5'b01001 : encode_nrz_2of7 = old_din ^ 7'b1000010;
      5'b01010 : encode_nrz_2of7 = old_din ^ 7'b1000100;
      5'b01011 : encode_nrz_2of7 = old_din ^ 7'b1001000;
      5'b01100 : encode_nrz_2of7 = old_din ^ 7'b0000011;
      5'b01101 : encode_nrz_2of7 = old_din ^ 7'b0000110;
      5'b01110 : encode_nrz_2of7 = old_din ^ 7'b0001100;
      5'b01111 : encode_nrz_2of7 = old_din ^ 7'b0001001;
      5'b1xxxx : encode_nrz_2of7 = old_din ^ 7'b1100000;
      default  : encode_nrz_2of7 = 7'bxxxxxxx;
    endcase
  endfunction





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      PKT_RDY_OUT <= 1'b0;
    else
      case (state)
        IDLE_ST: if (pkt_acpt)
                   PKT_RDY_OUT <= 1'b0;
                 else
                   PKT_RDY_OUT <= 1'b1;

        PARK_ST:   PKT_RDY_OUT <= 1'b0;

        default: if (eop && !flt_busy)
                   PKT_RDY_OUT <= 1'b1;
                 else
                   PKT_RDY_OUT <= 1'b0;
      endcase 





  always @ (*)
    pkt_acpt = (PKT_VLD_IN && PKT_RDY_OUT);





  always @(posedge CLK_IN)
    case (state)
      IDLE_ST:
        case ({pkt_acpt, flt_busy})
          2'b10:   pkt_buf <= PKT_DATA_IN >> 4;
          2'b11:   pkt_buf <= PKT_DATA_IN;
        endcase

      default: if (!flt_busy)
                   pkt_buf <= pkt_buf >> 4;
    endcase 





  always @(posedge CLK_IN)
    if ((state == IDLE_ST) && pkt_acpt)
      pkt_long <= PKT_DATA_IN[1];





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_data <= 7'd0;
    else
      case (state)
        IDLE_ST: if (pkt_acpt && !flt_busy)
                   flt_data <= encode_nrz_2of7 ({1'b0, PKT_DATA_IN[3:0]},
                                                 flt_data
                                               );

        default: if (!flt_busy)
                   flt_data <= encode_nrz_2of7 ({eop, pkt_buf[3:0]},
                                                 flt_data
                                               );

      endcase 





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_vld <= 1'b0;
    else
      case (state)
        IDLE_ST: if (!flt_busy)
                   if (pkt_acpt)
                     flt_vld <= 1'b1;
                   else
                     flt_vld <= 1'b0;

        default: flt_vld <= 1'b1;
      endcase 





  always @ (*)
    flt_busy = flt_vld && !flt_rdy;





  always @(posedge CLK_IN)
    case (state)
      IDLE_ST,
      PARK_ST:   flt_cnt <= 1;

      default: if (!flt_busy)
                 flt_cnt <= flt_cnt + 1;
    endcase 





  always @ (*)
    eop = (!pkt_long && (flt_cnt == 10)) || (flt_cnt == 18);





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      state <= IDLE_ST;
    else
      case (state)
        IDLE_ST:
          case ({pkt_acpt, flt_busy})
            2'b10:   state <= TRAN_ST;
	    2'b11:   state <= PARK_ST;
            default: state <= IDLE_ST;
          endcase

        PARK_ST: if (!flt_busy)
                     state <= TRAN_ST;   

        default: if (eop && !flt_busy)
                     state <= IDLE_ST;
      endcase 
endmodule