data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Counter.v
None: at end of input
data/verilator_xmls/621c7171-9b99-424e-a7c6-493afb5edf67.xml
module Counter(
input clk,
input incress_signal,
input rst,
output reg [31:0]count
    );
initial begin
    count=0;
end
    always @(posedge clk)
    begin
        if(incress_signal==1)
        begin
            count<=count+1;
        end
        else ;
        if(rst==1)
        begin
            count<=0;
        end
        else ;
    end
endmodule
module Counter(
input clk,
input incress_signal,
input rst,
output reg [31:0]count
    );

initial begin
    count=0;
end
    always @(posedge clk)
    begin
        if(incress_signal==1)
        begin
            count<=count+1;
        end
        else ;
        if(rst==1)
        begin
            count<=0;
        end
        else ;
    end
endmodule