data/full_repos/permissive/214823094/lab_7/project_1/project_1.srcs/sources_1/new/bus.v
data/verilator_xmls/7f7dd0f0-285f-46b7-bf12-d5571dcce98b.xml
module clkdiv(
    input mclk,
    output clk1_4hz
    );
    
    reg [27:0]q;
    always@(posedge mclk)
         q<=q+1;

    assign clk1_4hz=q[24];
         
endmodule
module clkdiv(
    input mclk,
    output clk1_4hz
    );

    
    reg [27:0]q;
    always@(posedge mclk)
         q<=q+1;

    assign clk1_4hz=q[24];
         
endmodule