data/full_repos/permissive/135820056/rtl/jt12/dac/jt12_dac2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/135820056/rtl/jt12/dac/jt12_dac2.v:49: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'undin\' generates 12 bits.\n                                                                                : ... In instance jt12_dac2\n y = undin + { error_1, 1\'b0} - error_2;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/135820056/rtl/jt12/dac/jt12_dac2.v:49: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s SUB generates 18 bits.\n                                                                                : ... In instance jt12_dac2\n y = undin + { error_1, 1\'b0} - error_2;\n   ^\n%Warning-WIDTH: data/full_repos/permissive/135820056/rtl/jt12/dac/jt12_dac2.v:51: Operator SUB expects 17 bits on the RHS, but RHS\'s REPLICATE generates 13 bits.\n                                                                                : ... In instance jt12_dac2\n error = y - {dout, {width{1\'b0}}};\n           ^\n%Error: Exiting due to 3 warning(s)\n'
module jt12_dac2 #(parameter width=12)
(
	input	clk,
    input	rst,
    input	signed [width-1:0] din,
    output	reg dout
);

localparam int_w = width+5;

reg [int_w-1:0] y, error, error_1, error_2;

wire [width-1:0] undin = { ~din[width-1], din[width-2:0] };

always @(*) begin
	y = undin + { error_1, 1'b0} - error_2;
	dout = ~y[int_w-1];
	error = y - {dout, {width{1'b0}}};
end

always @(posedge clk)
	if( rst ) begin
		error_1 <= {int_w{1'b0}};
		error_2 <= {int_w{1'b0}};
	end else begin
		error_1 <= error;
		error_2 <= error_1;
	end

endmodule
module jt12_dac2 #(parameter width=12)
(
	input	clk,
    input	rst,
    input	signed [width-1:0] din,
    output	reg dout
);


localparam int_w = width+5;

reg [int_w-1:0] y, error, error_1, error_2;

wire [width-1:0] undin = { ~din[width-1], din[width-2:0] };

always @(*) begin
	y = undin + { error_1, 1'b0} - error_2;
	dout = ~y[int_w-1];
	error = y - {dout, {width{1'b0}}};
end

always @(posedge clk)
	if( rst ) begin
		error_1 <= {int_w{1'b0}};
		error_2 <= {int_w{1'b0}};
	end else begin
		error_1 <= error;
		error_2 <= error_1;
	end

endmodule