data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v
None: at end of input
1: b'%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:22: Cannot find include file: common.h\n`include "common.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N,data/full_repos/permissive/191476706/common.h\n             data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N,data/full_repos/permissive/191476706/common.h.v\n             data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N,data/full_repos/permissive/191476706/common.h.sv\n             common.h\n             common.h.v\n             common.h.sv\n             obj_dir/common.h\n             obj_dir/common.h.v\n             obj_dir/common.h.sv\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:33: Define or directive not defined: \'`BW_DATA_IN\'\nparameter BW_DATA_IN = `BW_DATA_IN;\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:33: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DATA_IN = `BW_DATA_IN;\n                                  ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:35: Define or directive not defined: \'`BW_DIM_IN\'\nparameter BW_DIM_IN = `BW_DIM_IN;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:35: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DIM_IN = `BW_DIM_IN;\n                                ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:36: Define or directive not defined: \'`BW_DIM_EMB\'\nparameter BW_DIM_EMB = `BW_DIM_EMB;\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DIM_EMB = `BW_DIM_EMB;\n                                  ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:38: Define or directive not defined: \'`BW_DIM_IN\'\nparameter DIM_IN = `BW_DIM_IN;\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:38: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter DIM_IN = `BW_DIM_IN;\n                             ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:42: Define or directive not defined: \'`CLOG2\'\nparameter BW_ADDR = `CLOG2(BW_DIM_IN);         \n                    ^~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:44: Define or directive not defined: \'`NUM_MEM\'\nparameter NUM_MEM = `NUM_MEM;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:44: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter NUM_MEM = `NUM_MEM;\n                            ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:46: Define or directive not defined: \'`BW_DATA_EMB_W\'\nparameter BW_DATA_EMB_W = `BW_DATA_EMB_W;\n                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:46: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DATA_EMB_W = `BW_DATA_EMB_W;\n                                        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:48: Define or directive not defined: \'`BW_WORD_VEC\'\nparameter BW_WORD_VEC = `BW_WORD_VEC;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:48: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_WORD_VEC = `BW_WORD_VEC;\n                                    ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:50: Define or directive not defined: \'`NUM_ITR\'\nparameter NUM_ITR = `NUM_ITR;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:50: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter NUM_ITR = `NUM_ITR;\n                            ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:52: Define or directive not defined: \'`BW_DATA\'\nparameter BW_DATA =`BW_DATA;\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:52: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DATA =`BW_DATA;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:268: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:269: Define or directive not defined: \'`TYPE_CODE_DIN_EXP_SHIFT_BIT\'\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_DIN_EXP_SHIFT_BIT,4\'b0000,4\'b0000,4\'b0010};    \n                                        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:269: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_DIN_EXP_SHIFT_BIT,4\'b0000,4\'b0000,4\'b0010};    \n                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:270: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:272: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:279: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:283: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:352: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:354: Define or directive not defined: \'`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA\'\n            user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA}; \n                                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:354: Unsupported: empty queues ("{ }")\n            user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA}; \n                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:355: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:357: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:360: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:362: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:364: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:369: Unsupported: Ignoring delay on this delayed statement.\n                #10;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:371: Unsupported: Ignoring delay on this delayed statement.\n                #10;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:373: Unsupported: Ignoring delay on this delayed statement.\n                #10;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:383: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:387: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:402: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:404: Define or directive not defined: \'`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA\'\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA}; \n                                        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:404: Unsupported: empty queues ("{ }")\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA}; \n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:405: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:407: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:410: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:412: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:414: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:419: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:421: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:423: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:432: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:436: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:449: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:450: Define or directive not defined: \'`TYPE_CODE_SET_MODE_ON\'\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_ON,4\'b0000,4\'b0000,4\'b0000}; \n                                        ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:450: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_ON,4\'b0000,4\'b0000,4\'b0000}; \n                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:451: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:453: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:456: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:457: Define or directive not defined: \'`TYPE_CODE_SET_MODE_ON_1\'\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_ON_1}; \n                                        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:457: Unsupported: empty queues ("{ }")\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_ON_1}; \n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:458: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:460: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:463: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:464: Define or directive not defined: \'`TYPE_CODE_SET_MODE_ON_2\'\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_ON_2}; \n                                        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:464: Unsupported: empty queues ("{ }")\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_ON_2}; \n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:465: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:467: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:475: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:479: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:489: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:490: Define or directive not defined: \'`TYPE_CODE_SET_MODE_OFF\'\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_OFF,4\'b0000,4\'b0000,4\'b0000}; \n                                        ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:490: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_OFF,4\'b0000,4\'b0000,4\'b0000}; \n                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:491: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:493: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:496: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:497: Define or directive not defined: \'`TYPE_CODE_SET_MODE_OFF_1\'\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_OFF_1}; \n                                        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:497: Unsupported: empty queues ("{ }")\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_OFF_1}; \n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:498: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:500: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:503: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:504: Define or directive not defined: \'`TYPE_CODE_SET_MODE_OFF_2\'\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_OFF_2}; \n                                        ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:504: Unsupported: empty queues ("{ }")\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_OFF_2}; \n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:505: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:507: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:515: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:519: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:536: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:537: Define or directive not defined: \'`TYPE_CODE_SET_LR_L2\'\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_LR_L2,4\'b0000,4\'b0011,4\'b1001};    \n                                        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:537: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_LR_L2,4\'b0000,4\'b0011,4\'b1001};    \n                                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:538: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:540: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:547: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:551: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:561: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:562: Define or directive not defined: \'`TYPE_CODE_DUMMY\'\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_DUMMY,4\'b0000,4\'b0000,4\'b0000}; \n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:562: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n        user_w_write_16_data_fifo_in = {`TYPE_CODE_DUMMY,4\'b0000,4\'b0000,4\'b0000}; \n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:563: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:565: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:572: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:576: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:592: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:594: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:596: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:603: Unsupported: Ignoring delay on this delayed statement.\n                #10;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:609: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:619: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:746: Unsupported: Ignoring delay on this delayed statement.\n    #(20/2) clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:752: Unsupported: Ignoring delay on this delayed statement.\n    #(10/2) clk_pcie = ~clk_pcie;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:934: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:935: Unsupported: Verilog 1995 force\n        force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.we = 1\'b1;\n        ^~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:942: Unsupported: Verilog 1995 force\n                force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[31:24] = init_w_fc_w_sm[j+ind_w_fc_w_sm*DIM_EMB][7:0];\n                ^~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:943: Unsupported: Verilog 1995 force\n                force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[23:16] = init_w_fc_w_sm[j+ind_w_fc_w_sm*DIM_EMB][15:8];\n                ^~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:944: Unsupported: Verilog 1995 force\n                force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[15:8]  = init_w_fc_w_sm[j+ind_w_fc_w_sm*DIM_EMB][23:16];\n                ^~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:945: Unsupported: Verilog 1995 force\n                force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[7:0]   = init_w_fc_w_sm[j+ind_w_fc_w_sm*DIM_EMB][31:24];\n                ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:948: Unsupported: Ignoring delay on this delayed statement.\n            #100;\n            ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:956: Unsupported: Verilog 1995 force\n            force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.addr = ind_w_fc_w_sm;\n            ^~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:964: Unsupported: Verilog 1995 release\n        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[31:24];\n        ^~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/tb_MemN2N/imports/tb_MemN2N/tb_memory_network.v:965: Unsupported: Verilog 1995 release\n        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[23:16];\n        ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module tb_memory_network();   
parameter BW_DATA_IN = `BW_DATA_IN;

parameter BW_DIM_IN = `BW_DIM_IN;
parameter BW_DIM_EMB = `BW_DIM_EMB;

parameter DIM_IN = `BW_DIM_IN;
parameter DIM_EMB = 1<<BW_DIM_EMB;


parameter BW_ADDR = `CLOG2(BW_DIM_IN);

parameter NUM_MEM = `NUM_MEM;

parameter BW_DATA_EMB_W = `BW_DATA_EMB_W;

parameter BW_WORD_VEC = `BW_WORD_VEC;

parameter NUM_ITR = `NUM_ITR;

parameter BW_DATA =`BW_DATA;

parameter MAX_TEST_INPUT = 500000;


reg rst_sys;
wire en_init_cmd;
reg en_init_sys;
wire en_init_memn2n;



reg clk_pcie;
reg clk;
wire rst_n;
wire en;
wire en_init;


wire [BW_DATA_IN-1:0] data_in;

wire rb_n;
wire done_init_memn2n;
wire [BW_DATA_IN-1:0] data_out;


integer  k, num_words;
integer i;

genvar i_gen;

wire done_init;




integer file;
integer trained_model;

genvar j;

reg [16-1:0] memory_tb [0:MAX_TEST_INPUT-1];
reg [BW_DATA_EMB_W-1:0] init_w_fc_w_sm [0:DIM_IN*DIM_EMB-1];
reg [BW_DATA_EMB_W-1:0] init_w_fc [0:DIM_EMB*DIM_EMB-1];
reg [BW_DATA_EMB_W-1:0] init_emb_a [0:DIM_IN*DIM_EMB-1];
reg [BW_DATA_EMB_W-1:0] init_emb_c [0:DIM_IN*DIM_EMB-1];
reg [BW_DATA_EMB_W-1:0] init_emb_q [0:DIM_IN*DIM_EMB-1];

reg [BW_DATA-1:0] trained_model_w_fc_w_sm [0:DIM_IN*DIM_EMB-1];
reg [BW_DATA-1:0] trained_model_w_fc [0:DIM_EMB*DIM_EMB-1];
reg [BW_DATA-1:0] trained_model_emb_a [0:DIM_IN*DIM_EMB-1];
reg [BW_DATA-1:0] trained_model_emb_c [0:DIM_IN*DIM_EMB-1];
reg [BW_DATA-1:0] trained_model_emb_q [0:DIM_IN*DIM_EMB-1];




reg [8-1:0] user_w_write_8_data_fifo_in;
wire [8-1:0] user_r_read_8_data_fifo_in;
reg user_w_write_8_wren_fifo_in;
wire user_r_read_8_rden_fifo_in;
wire user_w_write_8_full_fifo_in;
wire user_r_read_8_empty_fifo_in;
wire user_r_read_8_val_fifo_in;

reg [16-1:0] user_w_write_16_data_fifo_in;
wire [16-1:0] user_r_read_16_data_fifo_in;
reg user_w_write_16_wren_fifo_in;
wire user_r_read_16_rden_fifo_in;
wire user_w_write_16_full_fifo_in;
wire user_r_read_16_empty_fifo_in;
wire user_r_read_16_val_fifo_in;

wire [16-1:0] user_w_write_16_data_fifo_out;
wire [16-1:0] user_r_read_16_data_fifo_out;
wire user_w_write_16_wren_fifo_out;
reg user_r_read_16_rden_fifo_out;
wire user_w_write_16_full_fifo_out;
wire user_r_read_16_empty_fifo_out;
wire user_r_read_16_val_fifo_out;







reg init_w_fc_w_sm_trig;
reg init_w_fc_trig;
reg init_emb_a_trig;
reg init_emb_c_trig;
reg init_emb_q_trig;

reg done_init_w;
reg done_init_emb_a;
reg done_init_emb_c;
reg done_init_emb_q;

reg done_init_sim;
reg done_init_memory_network;

integer itr_count;







wire rst_n_memn2n_cmd;


initial
begin
    user_w_write_16_data_fifo_in = 'b0;
    user_w_write_16_wren_fifo_in = 1'b0;

end

initial
begin
    file = $fopen("qa1_test.bin","rb");
    
    if(!file)
    begin
        $display("Couldn't open test file\n");
        $finish;
    end
    else
        num_words = $fread(memory_tb,file) / 2;

    $fclose(file);
end





`ifdef SIM_FORCE_W
initial
begin



    file = $fopen("model_qa1_single-supporting-fact_emb_a_fpga_fixed_q_7_24.bin","rb");
    if(!file)
    begin
        $display("Couldn't open w file\n");
        $finish;
    end
    else
        $fread(init_emb_a,file);
    $fclose(file);


    file = $fopen("model_qa1_single-supporting-fact_emb_c_fpga_fixed_q_7_24.bin","rb");
    if(!file)
    begin
        $display("Couldn't open w file\n");
        $finish;
    end
    else
        $fread(init_emb_c,file);
    $fclose(file);


    file = $fopen("model_qa1_single-supporting-fact_emb_q_fpga_fixed_q_7_24.bin","rb");
    if(!file)
    begin
        $display("Couldn't open w file\n");
        $finish;
    end
    else
        $fread(init_emb_q,file);
    $fclose(file);


    file = $fopen("model_qa1_single-supporting-fact_lin_map_fpga_fixed_q_7_24.bin","rb");
    if(!file)
    begin
        $display("Couldn't open w file\n");
        $finish;
    end
    else
        $fread(init_w_fc,file);
    $fclose(file);


    file = $fopen("model_qa1_single-supporting-fact_ds_ans_fpga_fixed_q_7_24.bin","rb");
    if(!file)
    begin
        $display("Couldn't open w file\n");
        $finish;
    end
    else
        $fread(init_w_fc_w_sm,file);
    $fclose(file);
end
`endif


task data_input_din_exp_shift_bit;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin
        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_DIN_EXP_SHIFT_BIT,4'b0000,4'b0000,4'b0010};
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;
    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask



task data_input_w_load_to_fpga;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin

        file = $fopen("model_qa1_single-supporting-fact_emb_a_fpga_fixed_q_7_24.hex","r");
        if(!file)
        begin
            $display("Couldn't open w file\n");
            $finish;
        end
        else
            $fread(trained_model_emb_a,file);
        $fclose(file);


        file = $fopen("model_qa1_single-supporting-fact_emb_c_fpga_fixed_q_7_24.hex","r");
        if(!file)
        begin
            $display("Couldn't open w file\n");
            $finish;
        end
        else
            $fread(trained_model_emb_c,file);
        $fclose(file);


        file = $fopen("model_qa1_single-supporting-fact_emb_q_fpga_fixed_q_7_24.hex","r");
        if(!file)
        begin
            $display("Couldn't open w file\n");
            $finish;
        end
        else
            $fread(trained_model_emb_q,file);
        $fclose(file);


        file = $fopen("model_qa1_single-supporting-fact_lin_map_fpga_fixed_q_7_24.hex","r");
        if(!file)
        begin
            $display("Couldn't open w file\n");
            $finish;
        end
        else
            $fread(trained_model_w_fc,file);
        $fclose(file);


        file = $fopen("model_qa1_single-supporting-fact_ds_ans_fpga_fixed_q_7_24.hex","r");
        if(!file)
        begin
            $display("Couldn't open w file\n");
            $finish;
        end
        else
            $fread(trained_model_w_fc_w_sm,file);
        $fclose(file);


        for(ind_emb_a=0;ind_emb_a<DIM_IN;ind_emb_a=ind_emb_a+1)
        begin
            #`PERIOD_CLK_PCIE;

            user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA}; 
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b1;
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b0;

            #`PERIOD_CLK_PCIE;
            user_w_write_16_data_fifo_in = ind_emb_a; 
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b1;
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b0;

            for(i=0;i<DIM_EMB*2;i=i+1)
            begin
                #`PERIOD_CLK_PCIE;
                user_w_write_16_data_fifo_in = trained_model_emb_a[i+ind_emb_a*DIM_EMB*2]; 
                #`PERIOD_CLK_PCIE;
                user_w_write_16_wren_fifo_in = 1'b1;
                #`PERIOD_CLK_PCIE;
                user_w_write_16_wren_fifo_in = 1'b0;
            end
        end

    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask





task data_input_w_load_to_fpga_test;
    input [15:0] addr;
    input integer data_init;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin
        #`PERIOD_CLK_PCIE;

        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = addr; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

        for(i=0;i<DIM_EMB*2;i=i+1)
        begin
            #`PERIOD_CLK_PCIE;
            user_w_write_16_data_fifo_in = (i+data_init); 
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b1;
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b0;
        end

    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask





task data_input_set_mode_on;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin
        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_ON,4'b0000,4'b0000,4'b0000}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_ON_1}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_ON_2}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask


task data_input_set_mode_off;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin
        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_OFF,4'b0000,4'b0000,4'b0000}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_OFF_1}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_OFF_2}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask









task data_input_set_lr_l2;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin
        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_LR_L2,4'b0000,4'b0011,4'b1001};
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;
    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask


task data_input_dummy;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin
        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_DUMMY,4'b0000,4'b0000,4'b0000}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;
    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask





integer ind_words;
task data_input;
begin
    for(ind_words=0;ind_words<num_words;ind_words=ind_words+1)
    begin
        if(user_w_write_16_full_fifo_in==1'b0)
        begin
            #`PERIOD_CLK_PCIE;
            user_w_write_16_data_fifo_in = memory_tb[ind_words];
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b1;
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b0;
        end
        else
        begin
            while(user_w_write_16_full_fifo_in==1'b1)
            begin
                #`PERIOD_CLK_PCIE;
            end
            ind_words = ind_words - 1;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask




initial
begin
    #1000;



    data_input_din_exp_shift_bit;

    data_input_set_lr_l2;

    data_input_dummy;

    for(itr_count=0;itr_count<NUM_ITR;itr_count=itr_count+1)
    begin
        data_input;
    end

end


wire user_w_write_8_open;
wire user_w_write_16_open;
wire user_r_read_16_open;

assign user_w_write_8_open = 1'b1;
assign user_w_write_16_open = 1'b1;
assign user_r_read_16_open = 1'b1;



(* DONT_TOUCH="yes" *) reg rst_fifo_in_8;
(* DONT_TOUCH="yes" *) reg rst_fifo_in_8_meta;

always@(posedge clk_pcie)
begin
    rst_fifo_in_8_meta <= !user_w_write_8_open;
end

always@(posedge clk_pcie)
begin
    rst_fifo_in_8 <= rst_fifo_in_8_meta;
end


(* DONT_TOUCH="yes" *) reg rst_fifo_in;
(* DONT_TOUCH="yes" *) reg rst_fifo_in_meta;

always@(posedge clk_pcie)
begin
    rst_fifo_in_meta <= !user_w_write_16_open;
end

always@(posedge clk_pcie)
begin
    rst_fifo_in <= rst_fifo_in_meta;
end


(* DONT_TOUCH="yes" *) reg rst_fifo_out;
(* DONT_TOUCH="yes" *) reg rst_fifo_out_meta;


always@(posedge clk)
begin
    rst_fifo_out_meta <= !user_w_write_16_open;
end

always@(posedge clk)
begin
    rst_fifo_out <= rst_fifo_out_meta;
end



fifo_host_to_fpga_8x512
fifo_in_8
(
    .srst(rst_fifo_in_8),
    .wr_clk(clk_pcie),
    .rd_clk(clk),
    .din(user_w_write_8_data_fifo_in),
    .wr_en(user_w_write_8_wren_fifo_in),
    .rd_en(user_r_read_8_rden_fifo_in),
    .dout(user_r_read_8_data_fifo_in),
    .full(user_w_write_8_full_fifo_in),
    .empty(user_r_read_8_empty_fifo_in),
    .valid(user_r_read_8_val_fifo_in)
);

fifo_host_to_fpga_16x1024
fifo_in_16
(
    .srst(rst_fifo_in),
    .wr_clk(clk_pcie),
    .rd_clk(clk),
    .din(user_w_write_16_data_fifo_in),
    .wr_en(user_w_write_16_wren_fifo_in),
    .rd_en(user_r_read_16_rden_fifo_in),
    .dout(user_r_read_16_data_fifo_in),
    .full(user_w_write_16_full_fifo_in),
    .empty(user_r_read_16_empty_fifo_in),
    .valid(user_r_read_16_val_fifo_in)
);

fifo_fpga_to_host_16x1024
fifo_out_16
(
    .srst(rst_fifo_out),
    .wr_clk(clk),
    .rd_clk(clk_pcie),
    .din(user_w_write_16_data_fifo_out),
    .wr_en(user_w_write_16_wren_fifo_out),
    .rd_en(user_r_read_16_rden_fifo_out),
    .dout(user_r_read_16_data_fifo_out),
    .full(user_w_write_16_full_fifo_out),
    .empty(user_r_read_16_empty_fifo_out),
    .valid(user_r_read_16_val_fifo_out)
);

integer ind_gen[15:0] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};

integer ind_w_fc_w_sm;
integer ind_w_fc;
integer ind_emb_a;
integer ind_emb_c;
integer ind_emb_q;
 
always
begin
    #(`PERIOD_CLK/2) clk = ~clk;
end
 

always
begin
    #(`PERIOD_CLK_PCIE/2) clk_pcie = ~clk_pcie;
end




   
initial
begin
    init_w_fc_w_sm_trig = 1'b0;
    init_w_fc_trig = 1'b0;
    init_emb_a_trig = 1'b0;
    init_emb_c_trig = 1'b0;
    init_emb_q_trig = 1'b0;

    done_init_w = 1'b0;
    done_init_emb_a = 1'b0;
    done_init_emb_c = 1'b0;
    done_init_emb_q = 1'b0;

    clk = 1'b0;
    clk_pcie = 1'b0;
    rst_sys = 1'b1;

    en_init_sys = 1'b0;


    done_init_sim = 1'b0;
    done_init_memory_network = 1'b0;

    ind_w_fc_w_sm = 0;
    ind_w_fc = 0;
    ind_emb_a = 0;
    ind_emb_c = 0;
    ind_emb_q = 0;



end




`ifdef WRITE_MEM
integer ind_f_mem;
integer file_w_fc_w_sm_q7_24[0:DIM_EMB-1];
integer file_w_fc_q7_24[0:DIM_EMB-1];
integer file_w_emb_a_q7_24[0:DIM_EMB-1];
integer file_w_emb_c_q7_24[0:DIM_EMB-1];
integer file_w_emb_q_q7_24[0:DIM_EMB-1];

integer file_w_fc_w_sm_q11_20[0:DIM_EMB-1];
integer file_w_fc_q11_20[0:DIM_EMB-1];
integer file_w_emb_a_q11_20[0:DIM_EMB-1];
integer file_w_emb_c_q11_20[0:DIM_EMB-1];
integer file_w_emb_q_q11_20[0:DIM_EMB-1];

reg[50*8:0] f_name;

initial
begin

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_fc_w_sm_init_q7_24_%02d.mem",ind_f_mem);
        file_w_fc_w_sm_q7_24[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_fc_w_sm_q7_24[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_fc_init_q7_24_%02d.mem",ind_f_mem);
        file_w_fc_q7_24[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_fc_q7_24[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_emb_a_init_q7_24_%02d.mem",ind_f_mem);
        file_w_emb_a_q7_24[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_emb_a_q7_24[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_emb_c_init_q7_24_%02d.mem",ind_f_mem);
        file_w_emb_c_q7_24[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_emb_c_q7_24[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_emb_q_init_q7_24_%02d.mem",ind_f_mem);
        file_w_emb_q_q7_24[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_emb_q_q7_24[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end


    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_fc_w_sm_init_q11_20_%02d.mem",ind_f_mem);
        file_w_fc_w_sm_q11_20[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_fc_w_sm_q11_20[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_fc_init_q11_20_%02d.mem",ind_f_mem);
        file_w_fc_q11_20[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_fc_q11_20[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_emb_a_init_q11_20_%02d.mem",ind_f_mem);
        file_w_emb_a_q11_20[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_emb_a_q11_20[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_emb_c_init_q11_20_%02d.mem",ind_f_mem);
        file_w_emb_c_q11_20[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_emb_c_q11_20[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_emb_q_init_q11_20_%02d.mem",ind_f_mem);
        file_w_emb_q_q11_20[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_emb_q_q11_20[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end
end
`endif


`ifdef SIM_FORCE_W
generate
for(j=0;j<DIM_EMB;j=j+1)
begin
    always@(posedge init_w_fc_w_sm_trig)
    begin
        #100;
        force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.we = 1'b1;


        for(ind_w_fc_w_sm=0;ind_w_fc_w_sm<(DIM_IN-1);)
        begin


                force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[31:24] = init_w_fc_w_sm[j+ind_w_fc_w_sm*DIM_EMB][7:0];
                force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[23:16] = init_w_fc_w_sm[j+ind_w_fc_w_sm*DIM_EMB][15:8];
                force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[15:8]  = init_w_fc_w_sm[j+ind_w_fc_w_sm*DIM_EMB][23:16];
                force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[7:0]   = init_w_fc_w_sm[j+ind_w_fc_w_sm*DIM_EMB][31:24];


            #100;

`ifdef WRITE_MEM
            $fwrite(file_w_fc_w_sm_q7_24[j], "%h \n" ,memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in);
            $fwrite(file_w_fc_w_sm_q11_20[j], "%h \n" ,$signed(memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in) >>> 4);
`endif


            force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.addr = ind_w_fc_w_sm;

            if(j==0)
            begin
                ind_w_fc_w_sm = ind_w_fc_w_sm+1;
            end
        end

        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[31:24];
        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[23:16];
        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[15:8];
        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[7:0];
        
        force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.we = 1'b0;

        #100;
    
        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.addr;
        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.we;   
        
        done_init_w = 1'b1;
    end
end
endgenerate

generate
for(j=0;j<DIM_EMB;j=j+1)
begin
    always@(posedge init_w_fc_trig)
    begin
        #100;
        force memory_network_top_module.memory_network_i.fc.weight[j].weight.we = 1'b1;


        for(ind_w_fc=0;ind_w_fc<(DIM_EMB);)
        begin


                force memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[31:24] = init_w_fc[j+ind_w_fc*DIM_EMB][7:0];
                force memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[23:16] = init_w_fc[j+ind_w_fc*DIM_EMB][15:8];
                force memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[15:8]  = init_w_fc[j+ind_w_fc*DIM_EMB][23:16];
                force memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[7:0]   = init_w_fc[j+ind_w_fc*DIM_EMB][31:24];


            #100;

`ifdef WRITE_MEM
            $fwrite(file_w_fc_q7_24[j], "%h \n" ,memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in);
            $fwrite(file_w_fc_q11_20[j], "%h \n" ,$signed(memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in) >>> 4);
`endif


            force memory_network_top_module.memory_network_i.fc.weight[j].weight.addr = ind_w_fc;

            if(j==0)
            begin
                ind_w_fc = ind_w_fc+1;
            end
        end

        release memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[31:24];
        release memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[23:16];
        release memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[15:8];
        release memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[7:0];
        
        force memory_network_top_module.memory_network_i.fc.weight[j].weight.we = 1'b0;

        #100;
    
        release memory_network_top_module.memory_network_i.fc.weight[j].weight.addr;
        release memory_network_top_module.memory_network_i.fc.weight[j].weight.we;   
        
        done_init_w = 1'b1;
    end
end
endgenerate

generate
for(j=0;j<DIM_EMB;j=j+1)
begin : init_weights_emb_a
    always@(posedge init_emb_a_trig)
    begin
        force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.we = 1'b1;
        #100;

        for(ind_emb_a=0;ind_emb_a<(DIM_IN-1);)
        begin


                force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[31:24] = init_emb_a[j+ind_emb_a*DIM_EMB][7:0];
                force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[23:16] = init_emb_a[j+ind_emb_a*DIM_EMB][15:8];
                force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[15:8]  = init_emb_a[j+ind_emb_a*DIM_EMB][23:16];
                force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[7:0]   = init_emb_a[j+ind_emb_a*DIM_EMB][31:24];


            #100;

`ifdef WRITE_MEM
            $fwrite(file_w_emb_a_q7_24[j], "%h \n" ,memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in);
            $fwrite(file_w_emb_a_q11_20[j], "%h \n" ,$signed(memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in) >>> 4);
`endif         


            force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.addr = ind_emb_a;

            if(j==0)
            begin
                ind_emb_a = ind_emb_a+1;
            end
        end


        
        release memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[31:24];
        release memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[23:16];
        release memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[15:8];
        release memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[7:0];

        force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.we = 1'b0;
        
        
        #100;

        release memory_network_top_module.memory_network_i.emb_a.weight[j].weight.addr;
        release memory_network_top_module.memory_network_i.emb_a.weight[j].weight.we;   
        
        done_init_emb_a = 1'b1;
    end
end
endgenerate


generate
for(j=0;j<DIM_EMB;j=j+1)
begin : init_weights_emb_c
    always@(posedge init_emb_c_trig)
    begin
        force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.we = 1'b1;
        #100;

        for(ind_emb_c=0;ind_emb_c<(DIM_IN-1);)
        begin


                force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[31:24] = init_emb_c[j+ind_emb_c*DIM_EMB][7:0];
                force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[23:16] = init_emb_c[j+ind_emb_c*DIM_EMB][15:8];
                force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[15:8]  = init_emb_c[j+ind_emb_c*DIM_EMB][23:16];
                force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[7:0]   = init_emb_c[j+ind_emb_c*DIM_EMB][31:24];

   
            #100;

`ifdef WRITE_MEM
            $fwrite(file_w_emb_c_q7_24[j], "%h \n" ,memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in);
            $fwrite(file_w_emb_c_q11_20[j], "%h \n" ,$signed(memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in) >>> 4);
`endif    


            force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.addr = ind_emb_c;

            if(j==0)
            begin
                ind_emb_c = ind_emb_c+1;
            end
        end

        release memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[31:24];
        release memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[23:16];
        release memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[15:8];
        release memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[7:0];
 
        force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.we = 1'b0;

        #100;
    
        release memory_network_top_module.memory_network_i.emb_c.weight[j].weight.addr;
        release memory_network_top_module.memory_network_i.emb_c.weight[j].weight.we;   
        
        done_init_emb_c = 1'b1;
    end
end
endgenerate


generate
for(j=0;j<DIM_EMB;j=j+1)
begin : init_weights_emb_q
    always@(posedge init_emb_q_trig)
    begin
        force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.we = 1'b1;
        #100;


        for(ind_emb_q=0;ind_emb_q<(DIM_IN-1);)
        begin


                force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[31:24] =  init_emb_q[j+ind_emb_q*DIM_EMB][7:0];
                force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[23:16] =  init_emb_q[j+ind_emb_q*DIM_EMB][15:8];
                force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[15:8]  =  init_emb_q[j+ind_emb_q*DIM_EMB][23:16];
                force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[7:0]   =  init_emb_q[j+ind_emb_q*DIM_EMB][31:24];

           
            #100;

`ifdef WRITE_MEM
            $fwrite(file_w_emb_q_q7_24[j], "%h \n" ,memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in);
            $fwrite(file_w_emb_q_q11_20[j], "%h \n" ,$signed(memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in) >>> 4);
`endif 


            force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.addr = ind_emb_q;

            if(j==0)
            begin
                ind_emb_q = ind_emb_q+1;
            end
        end

        release memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[31:24];
        release memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[23:16];
        release memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[15:8];
        release memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[7:0];
 
        force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.we = 1'b0;

        #100;
    
        release memory_network_top_module.memory_network_i.emb_q.weight[j].weight.addr;
        release memory_network_top_module.memory_network_i.emb_q.weight[j].weight.we;   

        done_init_emb_q = 1'b1;
    end
end
endgenerate
`endif



always@(posedge clk_pcie)
begin
    if(rst_sys==1'b1)
        user_r_read_16_rden_fifo_out <= 1'b0;
    else
        user_r_read_16_rden_fifo_out <= user_w_write_16_wren_fifo_out;
end

assign en_init_memn2n = en_init_sys | en_init_cmd;

memory_network_top
memory_network_top_module
(

    .clk(clk),

    .rst_sys(rst_sys),
    .en_init_sys(en_init_memn2n),


    .empty_fifo_in(user_r_read_16_empty_fifo_in),
    .valid_fifo_in(user_r_read_16_val_fifo_in),
    .valid_fifo_out(user_r_read_16_val_fifo_out),
    .dout_fifo_in(user_r_read_16_data_fifo_in),
    .done_init_memory_network(done_init_memory_network),




    .rd_en_fifo_in(user_r_read_16_rden_fifo_in),
    .wr_en_fifo_out(user_w_write_16_wren_fifo_out),
    .din_fifo_out(user_w_write_16_data_fifo_out)
);


global_controller
global_controller_module
(

    .clk(clk),

    .rst_n(!rst_sys),

    .empty_fifo_in(user_r_read_8_empty_fifo_in),
    .valid_fifo_in(user_r_read_8_val_fifo_in),
    .data_fifo_in(user_r_read_8_data_fifo_in),


    .re_fifo_in(user_r_read_8_rden_fifo_in),
    .en_init_cmd(en_init_cmd),
    .lr_l2(),
    .rst_n_memn2n_cmd(rst_n_memn2n_cmd)
);


initial
begin
    #30
    rst_sys= 1'b1;
    
    #200
    rst_sys= 1'b0;



    






    #21000;
    







    



    


`ifdef SIM_FORCE_W

    init_w_fc_w_sm_trig = 1'b1;
    init_w_fc_trig = 1'b1;
    init_emb_a_trig = 1'b1;
    init_emb_c_trig = 1'b1;
    init_emb_q_trig = 1'b1;

    #100;

    init_w_fc_w_sm_trig = 1'b0;
    init_w_fc_trig = 1'b0;
    init_emb_a_trig = 1'b0;
    init_emb_c_trig = 1'b0;
    init_emb_q_trig = 1'b0;


    #(23000);
    #(4000);


    done_init_sim = 1'b1;

    


    #100;
`ifdef WRITE_MEM
    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $fclose(file_w_fc_w_sm_q7_24[ind_f_mem]);
        $fclose(file_w_fc_q7_24[ind_f_mem]);
        $fclose(file_w_emb_a_q7_24[ind_f_mem]);
        $fclose(file_w_emb_c_q7_24[ind_f_mem]);
        $fclose(file_w_emb_q_q7_24[ind_f_mem]);

        $fclose(file_w_fc_w_sm_q11_20[ind_f_mem]);
        $fclose(file_w_fc_q11_20[ind_f_mem]);
        $fclose(file_w_emb_a_q11_20[ind_f_mem]);
        $fclose(file_w_emb_c_q11_20[ind_f_mem]);
        $fclose(file_w_emb_q_q11_20[ind_f_mem]);
    end
`endif

`endif
    
    #100;
    done_init_memory_network = 1'b1;


end






initial
begin
    $display("START TB MEMN2N");
end



integer ind_word;
integer ind_itr;


always@(negedge rb_n or negedge rst_n)
begin
    if(rst_n==1'b0)
        ind_word = 0;
    else
        ind_word = ind_word + 1;

    ind_itr = ind_word / num_words;

end




endmodule
module tb_memory_network();
   
parameter BW_DATA_IN = `BW_DATA_IN;

parameter BW_DIM_IN = `BW_DIM_IN;
parameter BW_DIM_EMB = `BW_DIM_EMB;

parameter DIM_IN = `BW_DIM_IN;
parameter DIM_EMB = 1<<BW_DIM_EMB;


parameter BW_ADDR = `CLOG2(BW_DIM_IN);

parameter NUM_MEM = `NUM_MEM;

parameter BW_DATA_EMB_W = `BW_DATA_EMB_W;

parameter BW_WORD_VEC = `BW_WORD_VEC;

parameter NUM_ITR = `NUM_ITR;

parameter BW_DATA =`BW_DATA;

parameter MAX_TEST_INPUT = 500000;


reg rst_sys;
wire en_init_cmd;
reg en_init_sys;
wire en_init_memn2n;



reg clk_pcie;
reg clk;
wire rst_n;
wire en;
wire en_init;


wire [BW_DATA_IN-1:0] data_in;

wire rb_n;
wire done_init_memn2n;
wire [BW_DATA_IN-1:0] data_out;


integer  k, num_words;
integer i;

genvar i_gen;

wire done_init;




integer file;
integer trained_model;

genvar j;

reg [16-1:0] memory_tb [0:MAX_TEST_INPUT-1];
reg [BW_DATA_EMB_W-1:0] init_w_fc_w_sm [0:DIM_IN*DIM_EMB-1];
reg [BW_DATA_EMB_W-1:0] init_w_fc [0:DIM_EMB*DIM_EMB-1];
reg [BW_DATA_EMB_W-1:0] init_emb_a [0:DIM_IN*DIM_EMB-1];
reg [BW_DATA_EMB_W-1:0] init_emb_c [0:DIM_IN*DIM_EMB-1];
reg [BW_DATA_EMB_W-1:0] init_emb_q [0:DIM_IN*DIM_EMB-1];

reg [BW_DATA-1:0] trained_model_w_fc_w_sm [0:DIM_IN*DIM_EMB-1];
reg [BW_DATA-1:0] trained_model_w_fc [0:DIM_EMB*DIM_EMB-1];
reg [BW_DATA-1:0] trained_model_emb_a [0:DIM_IN*DIM_EMB-1];
reg [BW_DATA-1:0] trained_model_emb_c [0:DIM_IN*DIM_EMB-1];
reg [BW_DATA-1:0] trained_model_emb_q [0:DIM_IN*DIM_EMB-1];




reg [8-1:0] user_w_write_8_data_fifo_in;
wire [8-1:0] user_r_read_8_data_fifo_in;
reg user_w_write_8_wren_fifo_in;
wire user_r_read_8_rden_fifo_in;
wire user_w_write_8_full_fifo_in;
wire user_r_read_8_empty_fifo_in;
wire user_r_read_8_val_fifo_in;

reg [16-1:0] user_w_write_16_data_fifo_in;
wire [16-1:0] user_r_read_16_data_fifo_in;
reg user_w_write_16_wren_fifo_in;
wire user_r_read_16_rden_fifo_in;
wire user_w_write_16_full_fifo_in;
wire user_r_read_16_empty_fifo_in;
wire user_r_read_16_val_fifo_in;

wire [16-1:0] user_w_write_16_data_fifo_out;
wire [16-1:0] user_r_read_16_data_fifo_out;
wire user_w_write_16_wren_fifo_out;
reg user_r_read_16_rden_fifo_out;
wire user_w_write_16_full_fifo_out;
wire user_r_read_16_empty_fifo_out;
wire user_r_read_16_val_fifo_out;







reg init_w_fc_w_sm_trig;
reg init_w_fc_trig;
reg init_emb_a_trig;
reg init_emb_c_trig;
reg init_emb_q_trig;

reg done_init_w;
reg done_init_emb_a;
reg done_init_emb_c;
reg done_init_emb_q;

reg done_init_sim;
reg done_init_memory_network;

integer itr_count;







wire rst_n_memn2n_cmd;


initial
begin
    user_w_write_16_data_fifo_in = 'b0;
    user_w_write_16_wren_fifo_in = 1'b0;

end

initial
begin
    file = $fopen("qa1_test.bin","rb");
    
    if(!file)
    begin
        $display("Couldn't open test file\n");
        $finish;
    end
    else
        num_words = $fread(memory_tb,file) / 2;

    $fclose(file);
end





`ifdef SIM_FORCE_W
initial
begin



    file = $fopen("model_qa1_single-supporting-fact_emb_a_fpga_fixed_q_7_24.bin","rb");
    if(!file)
    begin
        $display("Couldn't open w file\n");
        $finish;
    end
    else
        $fread(init_emb_a,file);
    $fclose(file);


    file = $fopen("model_qa1_single-supporting-fact_emb_c_fpga_fixed_q_7_24.bin","rb");
    if(!file)
    begin
        $display("Couldn't open w file\n");
        $finish;
    end
    else
        $fread(init_emb_c,file);
    $fclose(file);


    file = $fopen("model_qa1_single-supporting-fact_emb_q_fpga_fixed_q_7_24.bin","rb");
    if(!file)
    begin
        $display("Couldn't open w file\n");
        $finish;
    end
    else
        $fread(init_emb_q,file);
    $fclose(file);


    file = $fopen("model_qa1_single-supporting-fact_lin_map_fpga_fixed_q_7_24.bin","rb");
    if(!file)
    begin
        $display("Couldn't open w file\n");
        $finish;
    end
    else
        $fread(init_w_fc,file);
    $fclose(file);


    file = $fopen("model_qa1_single-supporting-fact_ds_ans_fpga_fixed_q_7_24.bin","rb");
    if(!file)
    begin
        $display("Couldn't open w file\n");
        $finish;
    end
    else
        $fread(init_w_fc_w_sm,file);
    $fclose(file);
end
`endif


task data_input_din_exp_shift_bit;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin
        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_DIN_EXP_SHIFT_BIT,4'b0000,4'b0000,4'b0010};
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;
    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask



task data_input_w_load_to_fpga;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin

        file = $fopen("model_qa1_single-supporting-fact_emb_a_fpga_fixed_q_7_24.hex","r");
        if(!file)
        begin
            $display("Couldn't open w file\n");
            $finish;
        end
        else
            $fread(trained_model_emb_a,file);
        $fclose(file);


        file = $fopen("model_qa1_single-supporting-fact_emb_c_fpga_fixed_q_7_24.hex","r");
        if(!file)
        begin
            $display("Couldn't open w file\n");
            $finish;
        end
        else
            $fread(trained_model_emb_c,file);
        $fclose(file);


        file = $fopen("model_qa1_single-supporting-fact_emb_q_fpga_fixed_q_7_24.hex","r");
        if(!file)
        begin
            $display("Couldn't open w file\n");
            $finish;
        end
        else
            $fread(trained_model_emb_q,file);
        $fclose(file);


        file = $fopen("model_qa1_single-supporting-fact_lin_map_fpga_fixed_q_7_24.hex","r");
        if(!file)
        begin
            $display("Couldn't open w file\n");
            $finish;
        end
        else
            $fread(trained_model_w_fc,file);
        $fclose(file);


        file = $fopen("model_qa1_single-supporting-fact_ds_ans_fpga_fixed_q_7_24.hex","r");
        if(!file)
        begin
            $display("Couldn't open w file\n");
            $finish;
        end
        else
            $fread(trained_model_w_fc_w_sm,file);
        $fclose(file);


        for(ind_emb_a=0;ind_emb_a<DIM_IN;ind_emb_a=ind_emb_a+1)
        begin
            #`PERIOD_CLK_PCIE;

            user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA}; 
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b1;
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b0;

            #`PERIOD_CLK_PCIE;
            user_w_write_16_data_fifo_in = ind_emb_a; 
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b1;
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b0;

            for(i=0;i<DIM_EMB*2;i=i+1)
            begin
                #`PERIOD_CLK_PCIE;
                user_w_write_16_data_fifo_in = trained_model_emb_a[i+ind_emb_a*DIM_EMB*2]; 
                #`PERIOD_CLK_PCIE;
                user_w_write_16_wren_fifo_in = 1'b1;
                #`PERIOD_CLK_PCIE;
                user_w_write_16_wren_fifo_in = 1'b0;
            end
        end

    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask





task data_input_w_load_to_fpga_test;
    input [15:0] addr;
    input integer data_init;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin
        #`PERIOD_CLK_PCIE;

        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_W_LOAD_TO_FPGA}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = addr; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

        for(i=0;i<DIM_EMB*2;i=i+1)
        begin
            #`PERIOD_CLK_PCIE;
            user_w_write_16_data_fifo_in = (i+data_init); 
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b1;
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b0;
        end

    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask





task data_input_set_mode_on;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin
        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_ON,4'b0000,4'b0000,4'b0000}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_ON_1}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_ON_2}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask


task data_input_set_mode_off;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin
        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_OFF,4'b0000,4'b0000,4'b0000}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_OFF_1}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_MODE_OFF_2}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;

    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask









task data_input_set_lr_l2;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin
        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_SET_LR_L2,4'b0000,4'b0011,4'b1001};
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;
    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask


task data_input_dummy;
begin
    if(user_w_write_16_full_fifo_in==1'b0)
    begin
        #`PERIOD_CLK_PCIE;
        user_w_write_16_data_fifo_in = {`TYPE_CODE_DUMMY,4'b0000,4'b0000,4'b0000}; 
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b1;
        #`PERIOD_CLK_PCIE;
        user_w_write_16_wren_fifo_in = 1'b0;
    end
    else
    begin
        while(user_w_write_16_full_fifo_in==1'b1)
        begin
            #`PERIOD_CLK_PCIE;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask





integer ind_words;
task data_input;
begin
    for(ind_words=0;ind_words<num_words;ind_words=ind_words+1)
    begin
        if(user_w_write_16_full_fifo_in==1'b0)
        begin
            #`PERIOD_CLK_PCIE;
            user_w_write_16_data_fifo_in = memory_tb[ind_words];
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b1;
            #`PERIOD_CLK_PCIE;
            user_w_write_16_wren_fifo_in = 1'b0;
        end
        else
        begin
            while(user_w_write_16_full_fifo_in==1'b1)
            begin
                #`PERIOD_CLK_PCIE;
            end
            ind_words = ind_words - 1;
        end
    end

    #`PERIOD_CLK_PCIE;
    user_w_write_16_data_fifo_in = 'b0;
end
endtask




initial
begin
    #1000;



    data_input_din_exp_shift_bit;

    data_input_set_lr_l2;

    data_input_dummy;

    for(itr_count=0;itr_count<NUM_ITR;itr_count=itr_count+1)
    begin
        data_input;
    end

end


wire user_w_write_8_open;
wire user_w_write_16_open;
wire user_r_read_16_open;

assign user_w_write_8_open = 1'b1;
assign user_w_write_16_open = 1'b1;
assign user_r_read_16_open = 1'b1;



(* DONT_TOUCH="yes" *) reg rst_fifo_in_8;
(* DONT_TOUCH="yes" *) reg rst_fifo_in_8_meta;

always@(posedge clk_pcie)
begin
    rst_fifo_in_8_meta <= !user_w_write_8_open;
end

always@(posedge clk_pcie)
begin
    rst_fifo_in_8 <= rst_fifo_in_8_meta;
end


(* DONT_TOUCH="yes" *) reg rst_fifo_in;
(* DONT_TOUCH="yes" *) reg rst_fifo_in_meta;

always@(posedge clk_pcie)
begin
    rst_fifo_in_meta <= !user_w_write_16_open;
end

always@(posedge clk_pcie)
begin
    rst_fifo_in <= rst_fifo_in_meta;
end


(* DONT_TOUCH="yes" *) reg rst_fifo_out;
(* DONT_TOUCH="yes" *) reg rst_fifo_out_meta;


always@(posedge clk)
begin
    rst_fifo_out_meta <= !user_w_write_16_open;
end

always@(posedge clk)
begin
    rst_fifo_out <= rst_fifo_out_meta;
end



fifo_host_to_fpga_8x512
fifo_in_8
(
    .srst(rst_fifo_in_8),
    .wr_clk(clk_pcie),
    .rd_clk(clk),
    .din(user_w_write_8_data_fifo_in),
    .wr_en(user_w_write_8_wren_fifo_in),
    .rd_en(user_r_read_8_rden_fifo_in),
    .dout(user_r_read_8_data_fifo_in),
    .full(user_w_write_8_full_fifo_in),
    .empty(user_r_read_8_empty_fifo_in),
    .valid(user_r_read_8_val_fifo_in)
);

fifo_host_to_fpga_16x1024
fifo_in_16
(
    .srst(rst_fifo_in),
    .wr_clk(clk_pcie),
    .rd_clk(clk),
    .din(user_w_write_16_data_fifo_in),
    .wr_en(user_w_write_16_wren_fifo_in),
    .rd_en(user_r_read_16_rden_fifo_in),
    .dout(user_r_read_16_data_fifo_in),
    .full(user_w_write_16_full_fifo_in),
    .empty(user_r_read_16_empty_fifo_in),
    .valid(user_r_read_16_val_fifo_in)
);

fifo_fpga_to_host_16x1024
fifo_out_16
(
    .srst(rst_fifo_out),
    .wr_clk(clk),
    .rd_clk(clk_pcie),
    .din(user_w_write_16_data_fifo_out),
    .wr_en(user_w_write_16_wren_fifo_out),
    .rd_en(user_r_read_16_rden_fifo_out),
    .dout(user_r_read_16_data_fifo_out),
    .full(user_w_write_16_full_fifo_out),
    .empty(user_r_read_16_empty_fifo_out),
    .valid(user_r_read_16_val_fifo_out)
);

integer ind_gen[15:0] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};

integer ind_w_fc_w_sm;
integer ind_w_fc;
integer ind_emb_a;
integer ind_emb_c;
integer ind_emb_q;
 
always
begin
    #(`PERIOD_CLK/2) clk = ~clk;
end
 

always
begin
    #(`PERIOD_CLK_PCIE/2) clk_pcie = ~clk_pcie;
end




   
initial
begin
    init_w_fc_w_sm_trig = 1'b0;
    init_w_fc_trig = 1'b0;
    init_emb_a_trig = 1'b0;
    init_emb_c_trig = 1'b0;
    init_emb_q_trig = 1'b0;

    done_init_w = 1'b0;
    done_init_emb_a = 1'b0;
    done_init_emb_c = 1'b0;
    done_init_emb_q = 1'b0;

    clk = 1'b0;
    clk_pcie = 1'b0;
    rst_sys = 1'b1;

    en_init_sys = 1'b0;


    done_init_sim = 1'b0;
    done_init_memory_network = 1'b0;

    ind_w_fc_w_sm = 0;
    ind_w_fc = 0;
    ind_emb_a = 0;
    ind_emb_c = 0;
    ind_emb_q = 0;



end




`ifdef WRITE_MEM
integer ind_f_mem;
integer file_w_fc_w_sm_q7_24[0:DIM_EMB-1];
integer file_w_fc_q7_24[0:DIM_EMB-1];
integer file_w_emb_a_q7_24[0:DIM_EMB-1];
integer file_w_emb_c_q7_24[0:DIM_EMB-1];
integer file_w_emb_q_q7_24[0:DIM_EMB-1];

integer file_w_fc_w_sm_q11_20[0:DIM_EMB-1];
integer file_w_fc_q11_20[0:DIM_EMB-1];
integer file_w_emb_a_q11_20[0:DIM_EMB-1];
integer file_w_emb_c_q11_20[0:DIM_EMB-1];
integer file_w_emb_q_q11_20[0:DIM_EMB-1];

reg[50*8:0] f_name;

initial
begin

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_fc_w_sm_init_q7_24_%02d.mem",ind_f_mem);
        file_w_fc_w_sm_q7_24[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_fc_w_sm_q7_24[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_fc_init_q7_24_%02d.mem",ind_f_mem);
        file_w_fc_q7_24[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_fc_q7_24[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_emb_a_init_q7_24_%02d.mem",ind_f_mem);
        file_w_emb_a_q7_24[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_emb_a_q7_24[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_emb_c_init_q7_24_%02d.mem",ind_f_mem);
        file_w_emb_c_q7_24[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_emb_c_q7_24[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_emb_q_init_q7_24_%02d.mem",ind_f_mem);
        file_w_emb_q_q7_24[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_emb_q_q7_24[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end


    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_fc_w_sm_init_q11_20_%02d.mem",ind_f_mem);
        file_w_fc_w_sm_q11_20[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_fc_w_sm_q11_20[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_fc_init_q11_20_%02d.mem",ind_f_mem);
        file_w_fc_q11_20[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_fc_q11_20[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_emb_a_init_q11_20_%02d.mem",ind_f_mem);
        file_w_emb_a_q11_20[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_emb_a_q11_20[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_emb_c_init_q11_20_%02d.mem",ind_f_mem);
        file_w_emb_c_q11_20[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_emb_c_q11_20[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end

    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $sformat(f_name,"w_emb_q_init_q11_20_%02d.mem",ind_f_mem);
        file_w_emb_q_q11_20[ind_f_mem] = $fopen(f_name,"w");
        if(!file_w_emb_q_q11_20[ind_f_mem])
        begin
            $display("Couldn't open file\n");
            $finish;
        end
    end
end
`endif


`ifdef SIM_FORCE_W
generate
for(j=0;j<DIM_EMB;j=j+1)
begin
    always@(posedge init_w_fc_w_sm_trig)
    begin
        #100;
        force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.we = 1'b1;


        for(ind_w_fc_w_sm=0;ind_w_fc_w_sm<(DIM_IN-1);)
        begin


                force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[31:24] = init_w_fc_w_sm[j+ind_w_fc_w_sm*DIM_EMB][7:0];
                force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[23:16] = init_w_fc_w_sm[j+ind_w_fc_w_sm*DIM_EMB][15:8];
                force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[15:8]  = init_w_fc_w_sm[j+ind_w_fc_w_sm*DIM_EMB][23:16];
                force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[7:0]   = init_w_fc_w_sm[j+ind_w_fc_w_sm*DIM_EMB][31:24];


            #100;

`ifdef WRITE_MEM
            $fwrite(file_w_fc_w_sm_q7_24[j], "%h \n" ,memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in);
            $fwrite(file_w_fc_w_sm_q11_20[j], "%h \n" ,$signed(memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in) >>> 4);
`endif


            force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.addr = ind_w_fc_w_sm;

            if(j==0)
            begin
                ind_w_fc_w_sm = ind_w_fc_w_sm+1;
            end
        end

        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[31:24];
        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[23:16];
        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[15:8];
        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.data_in[7:0];
        
        force memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.we = 1'b0;

        #100;
    
        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.addr;
        release memory_network_top_module.memory_network_i.fc_w_sm.weight[j].weight.we;   
        
        done_init_w = 1'b1;
    end
end
endgenerate

generate
for(j=0;j<DIM_EMB;j=j+1)
begin
    always@(posedge init_w_fc_trig)
    begin
        #100;
        force memory_network_top_module.memory_network_i.fc.weight[j].weight.we = 1'b1;


        for(ind_w_fc=0;ind_w_fc<(DIM_EMB);)
        begin


                force memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[31:24] = init_w_fc[j+ind_w_fc*DIM_EMB][7:0];
                force memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[23:16] = init_w_fc[j+ind_w_fc*DIM_EMB][15:8];
                force memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[15:8]  = init_w_fc[j+ind_w_fc*DIM_EMB][23:16];
                force memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[7:0]   = init_w_fc[j+ind_w_fc*DIM_EMB][31:24];


            #100;

`ifdef WRITE_MEM
            $fwrite(file_w_fc_q7_24[j], "%h \n" ,memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in);
            $fwrite(file_w_fc_q11_20[j], "%h \n" ,$signed(memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in) >>> 4);
`endif


            force memory_network_top_module.memory_network_i.fc.weight[j].weight.addr = ind_w_fc;

            if(j==0)
            begin
                ind_w_fc = ind_w_fc+1;
            end
        end

        release memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[31:24];
        release memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[23:16];
        release memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[15:8];
        release memory_network_top_module.memory_network_i.fc.weight[j].weight.data_in[7:0];
        
        force memory_network_top_module.memory_network_i.fc.weight[j].weight.we = 1'b0;

        #100;
    
        release memory_network_top_module.memory_network_i.fc.weight[j].weight.addr;
        release memory_network_top_module.memory_network_i.fc.weight[j].weight.we;   
        
        done_init_w = 1'b1;
    end
end
endgenerate

generate
for(j=0;j<DIM_EMB;j=j+1)
begin : init_weights_emb_a
    always@(posedge init_emb_a_trig)
    begin
        force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.we = 1'b1;
        #100;

        for(ind_emb_a=0;ind_emb_a<(DIM_IN-1);)
        begin


                force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[31:24] = init_emb_a[j+ind_emb_a*DIM_EMB][7:0];
                force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[23:16] = init_emb_a[j+ind_emb_a*DIM_EMB][15:8];
                force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[15:8]  = init_emb_a[j+ind_emb_a*DIM_EMB][23:16];
                force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[7:0]   = init_emb_a[j+ind_emb_a*DIM_EMB][31:24];


            #100;

`ifdef WRITE_MEM
            $fwrite(file_w_emb_a_q7_24[j], "%h \n" ,memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in);
            $fwrite(file_w_emb_a_q11_20[j], "%h \n" ,$signed(memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in) >>> 4);
`endif         


            force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.addr = ind_emb_a;

            if(j==0)
            begin
                ind_emb_a = ind_emb_a+1;
            end
        end


        
        release memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[31:24];
        release memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[23:16];
        release memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[15:8];
        release memory_network_top_module.memory_network_i.emb_a.weight[j].weight.data_in[7:0];

        force memory_network_top_module.memory_network_i.emb_a.weight[j].weight.we = 1'b0;
        
        
        #100;

        release memory_network_top_module.memory_network_i.emb_a.weight[j].weight.addr;
        release memory_network_top_module.memory_network_i.emb_a.weight[j].weight.we;   
        
        done_init_emb_a = 1'b1;
    end
end
endgenerate


generate
for(j=0;j<DIM_EMB;j=j+1)
begin : init_weights_emb_c
    always@(posedge init_emb_c_trig)
    begin
        force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.we = 1'b1;
        #100;

        for(ind_emb_c=0;ind_emb_c<(DIM_IN-1);)
        begin


                force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[31:24] = init_emb_c[j+ind_emb_c*DIM_EMB][7:0];
                force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[23:16] = init_emb_c[j+ind_emb_c*DIM_EMB][15:8];
                force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[15:8]  = init_emb_c[j+ind_emb_c*DIM_EMB][23:16];
                force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[7:0]   = init_emb_c[j+ind_emb_c*DIM_EMB][31:24];

   
            #100;

`ifdef WRITE_MEM
            $fwrite(file_w_emb_c_q7_24[j], "%h \n" ,memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in);
            $fwrite(file_w_emb_c_q11_20[j], "%h \n" ,$signed(memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in) >>> 4);
`endif    


            force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.addr = ind_emb_c;

            if(j==0)
            begin
                ind_emb_c = ind_emb_c+1;
            end
        end

        release memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[31:24];
        release memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[23:16];
        release memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[15:8];
        release memory_network_top_module.memory_network_i.emb_c.weight[j].weight.data_in[7:0];
 
        force memory_network_top_module.memory_network_i.emb_c.weight[j].weight.we = 1'b0;

        #100;
    
        release memory_network_top_module.memory_network_i.emb_c.weight[j].weight.addr;
        release memory_network_top_module.memory_network_i.emb_c.weight[j].weight.we;   
        
        done_init_emb_c = 1'b1;
    end
end
endgenerate


generate
for(j=0;j<DIM_EMB;j=j+1)
begin : init_weights_emb_q
    always@(posedge init_emb_q_trig)
    begin
        force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.we = 1'b1;
        #100;


        for(ind_emb_q=0;ind_emb_q<(DIM_IN-1);)
        begin


                force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[31:24] =  init_emb_q[j+ind_emb_q*DIM_EMB][7:0];
                force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[23:16] =  init_emb_q[j+ind_emb_q*DIM_EMB][15:8];
                force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[15:8]  =  init_emb_q[j+ind_emb_q*DIM_EMB][23:16];
                force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[7:0]   =  init_emb_q[j+ind_emb_q*DIM_EMB][31:24];

           
            #100;

`ifdef WRITE_MEM
            $fwrite(file_w_emb_q_q7_24[j], "%h \n" ,memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in);
            $fwrite(file_w_emb_q_q11_20[j], "%h \n" ,$signed(memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in) >>> 4);
`endif 


            force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.addr = ind_emb_q;

            if(j==0)
            begin
                ind_emb_q = ind_emb_q+1;
            end
        end

        release memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[31:24];
        release memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[23:16];
        release memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[15:8];
        release memory_network_top_module.memory_network_i.emb_q.weight[j].weight.data_in[7:0];
 
        force memory_network_top_module.memory_network_i.emb_q.weight[j].weight.we = 1'b0;

        #100;
    
        release memory_network_top_module.memory_network_i.emb_q.weight[j].weight.addr;
        release memory_network_top_module.memory_network_i.emb_q.weight[j].weight.we;   

        done_init_emb_q = 1'b1;
    end
end
endgenerate
`endif



always@(posedge clk_pcie)
begin
    if(rst_sys==1'b1)
        user_r_read_16_rden_fifo_out <= 1'b0;
    else
        user_r_read_16_rden_fifo_out <= user_w_write_16_wren_fifo_out;
end

assign en_init_memn2n = en_init_sys | en_init_cmd;

memory_network_top
memory_network_top_module
(

    .clk(clk),

    .rst_sys(rst_sys),
    .en_init_sys(en_init_memn2n),


    .empty_fifo_in(user_r_read_16_empty_fifo_in),
    .valid_fifo_in(user_r_read_16_val_fifo_in),
    .valid_fifo_out(user_r_read_16_val_fifo_out),
    .dout_fifo_in(user_r_read_16_data_fifo_in),
    .done_init_memory_network(done_init_memory_network),




    .rd_en_fifo_in(user_r_read_16_rden_fifo_in),
    .wr_en_fifo_out(user_w_write_16_wren_fifo_out),
    .din_fifo_out(user_w_write_16_data_fifo_out)
);


global_controller
global_controller_module
(

    .clk(clk),

    .rst_n(!rst_sys),

    .empty_fifo_in(user_r_read_8_empty_fifo_in),
    .valid_fifo_in(user_r_read_8_val_fifo_in),
    .data_fifo_in(user_r_read_8_data_fifo_in),


    .re_fifo_in(user_r_read_8_rden_fifo_in),
    .en_init_cmd(en_init_cmd),
    .lr_l2(),
    .rst_n_memn2n_cmd(rst_n_memn2n_cmd)
);


initial
begin
    #30
    rst_sys= 1'b1;
    
    #200
    rst_sys= 1'b0;



    






    #21000;
    







    



    


`ifdef SIM_FORCE_W

    init_w_fc_w_sm_trig = 1'b1;
    init_w_fc_trig = 1'b1;
    init_emb_a_trig = 1'b1;
    init_emb_c_trig = 1'b1;
    init_emb_q_trig = 1'b1;

    #100;

    init_w_fc_w_sm_trig = 1'b0;
    init_w_fc_trig = 1'b0;
    init_emb_a_trig = 1'b0;
    init_emb_c_trig = 1'b0;
    init_emb_q_trig = 1'b0;


    #(23000);
    #(4000);


    done_init_sim = 1'b1;

    


    #100;
`ifdef WRITE_MEM
    for(ind_f_mem=0;ind_f_mem<DIM_EMB;ind_f_mem=ind_f_mem+1)
    begin
        $fclose(file_w_fc_w_sm_q7_24[ind_f_mem]);
        $fclose(file_w_fc_q7_24[ind_f_mem]);
        $fclose(file_w_emb_a_q7_24[ind_f_mem]);
        $fclose(file_w_emb_c_q7_24[ind_f_mem]);
        $fclose(file_w_emb_q_q7_24[ind_f_mem]);

        $fclose(file_w_fc_w_sm_q11_20[ind_f_mem]);
        $fclose(file_w_fc_q11_20[ind_f_mem]);
        $fclose(file_w_emb_a_q11_20[ind_f_mem]);
        $fclose(file_w_emb_c_q11_20[ind_f_mem]);
        $fclose(file_w_emb_q_q11_20[ind_f_mem]);
    end
`endif

`endif
    
    #100;
    done_init_memory_network = 1'b1;


end






initial
begin
    $display("START TB MEMN2N");
end



integer ind_word;
integer ind_itr;


always@(negedge rb_n or negedge rst_n)
begin
    if(rst_n==1'b0)
        ind_word = 0;
    else
        ind_word = ind_word + 1;

    ind_itr = ind_word / num_words;

end




endmodule