data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v
 line:189: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD_BCLK/2) bclk = 1\'b1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD_BCLK/2);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD_CLK100/2) clk100 = 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD_CLK100/2);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n      #1000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n      #1000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:214: Unsupported: Ignoring delay on this delayed statement.\n      #200;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:219: Unsupported: Ignoring delay on this delayed statement.\n      #1000;\n      ^\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:55: Cannot find file containing module: \'nand_log\'\nnand_log uut(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports,data/full_repos/permissive/10301314/nand_log\n             data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports,data/full_repos/permissive/10301314/nand_log.v\n             data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports,data/full_repos/permissive/10301314/nand_log.sv\n             nand_log\n             nand_log.v\n             nand_log.sv\n             obj_dir/nand_log\n             obj_dir/nand_log.v\n             obj_dir/nand_log.sv\n%Error: Exiting due to 1 error(s), 28 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module nand_log_tb;
   reg bclk;
   reg clk100;

   reg nand_re;
   reg nand_we;
   reg nand_ale;
   reg nand_cle;
   reg nand_cs;
   reg nand_rb;
   reg [7:0] nand_din;
   reg [9:0] nand_uk;

   reg 	     log_reset;
   reg 	     log_run;
   wire      log_cmd_error;
   wire      log_data_error;
   wire [26:0] log_entries;
   
   wire [3:0]  ddr3_wr_mask;
   wire [31:0] ddr3_wr_data;
   wire        ddr3_wr_en;
   reg 	       ddr3_wr_full;
   reg [6:0]   ddr3_wr_count;
   wire        ddr3_cmd_clk;
   wire [2:0]  ddr3_cmd_instr;
   wire        ddr3_cmd_en;
   wire [5:0]  ddr3_cmd_burstlen;
   wire [29:0] ddr3_cmd_addr;
   reg 	       ddr3_cmd_full;

   wire [63:0] time_t_clk100;
   reg 	       reset;

nand_log uut(
		  bclk,
		  clk100,

		  nand_re,
		  nand_we,
		  nand_ale,
		  nand_cle,
		  nand_cs,
		  nand_rb,
		  nand_din,
		  nand_uk,

		  log_reset,
		  log_run,
		  log_cmd_error,
		  log_data_error,
		  log_entries,

		  ddr3_wr_mask,
		  ddr3_wr_data,
		  ddr3_wr_en,
		  ddr3_wr_full,
		  ddr3_wr_count,
		  ddr3_cmd_clk,
		  ddr3_cmd_instr,
		  ddr3_cmd_en,
		  ddr3_cmd_burstlen,
		  ddr3_cmd_addr,
		  ddr3_cmd_full,

		  time_t_clk100,
		  reset
		);

   parameter PERIOD_BCLK = 16'd8;
   always begin
      bclk = 1'b0;
      #(PERIOD_BCLK/2) bclk = 1'b1;
      #(PERIOD_BCLK/2);
   end

   parameter PERIOD_CLK100 = 16'd10;
   always begin
      clk100 = 1'b0;
      #(PERIOD_CLK100/2) clk100 = 1'b1;
      #(PERIOD_CLK100/2);
   end

   task nand_reset;
      begin
	 nand_we = 1'b1;
	 nand_re = 1'b1;
	 nand_ale = 1'b0;
	 nand_cle = 1'b0;
	 nand_cs = 1'b1;
	 nand_din = 8'hZZ;

	 log_reset = 1'b1;
	 log_run = 1'b0;
	 #1000;
	 log_reset = 1'b0;
	 log_run = 1'b1;
	 #1000;
      end
   endtask
   
   task nand_idle;
      begin
	 nand_we = 1'b1;
	 nand_re = 1'b1;
	 nand_ale = 1'b0;
	 nand_cle = 1'b0;
	 nand_cs = 1'b1;
	 nand_din = 8'hZZ;
      end
   endtask

   task nand_read_id;
      begin
	 nand_cs = 1'b0;
	 
	 nand_cle = 1'b1;
	 nand_we = 1'b0;
	 nand_din = 8'h90;
	 #25;
	 nand_we = 1'b1;
	 #5;
	 nand_cle = 1'b0;
	 nand_din = 8'h01;
	 #20;

	 nand_ale = 1'b1;
	 #25;

	 nand_we = 1'b0;
	 nand_din = 8'h00;
	 #25;
	 nand_we = 1'b1;
	 #5;
	 nand_din = 8'h23;
	 #20;

	 nand_ale = 1'b0;

	 #10;
	 nand_re = 1'b0;
	 nand_din = 8'h45;
	 #25;
	 nand_re = 1'b1;
	 #25;
	 nand_re = 1'b0;
	 nand_din = 8'h67;
	 #25;
	 nand_re = 1'b1;
	 #25;
	 nand_re = 1'b0;
	 nand_din = 8'h89;
	 #25;
	 nand_re = 1'b1;
	 #25;
	 nand_re = 1'b0;
	 nand_din = 8'hAB;
	 #25;
	 nand_re = 1'b1;
	 #25;
	 nand_re = 1'b0;
	 nand_din = 8'hCD;
	 #25;
	 nand_re = 1'b1;
	 #25;

	 nand_cs = 1'b1;
      end
   endtask;

   initial begin
      nand_re = 1;
      nand_we = 1;
      nand_ale = 0;
      nand_cle = 0;
      nand_rb = 1;
      nand_din = 8'h00;
      nand_uk[9:0] = 10'h0;
      nand_cs = 1;

      log_reset = 1'b0;
      log_run = 1'b0;
      ddr3_wr_full = 1'b0;
      ddr3_wr_count = 7'b0;
      ddr3_cmd_full = 1'b0;
      
      reset = 1;
      #1000;
      reset = 0;
      nand_reset();
      #1000;
      
      nand_idle();
      #200;
      nand_read_id();

      $stop;

      #1000;
      $stop;
   end
   
endmodule
module nand_log_tb;

   reg bclk;
   reg clk100;

   reg nand_re;
   reg nand_we;
   reg nand_ale;
   reg nand_cle;
   reg nand_cs;
   reg nand_rb;
   reg [7:0] nand_din;
   reg [9:0] nand_uk;

   reg 	     log_reset;
   reg 	     log_run;
   wire      log_cmd_error;
   wire      log_data_error;
   wire [26:0] log_entries;
   
   wire [3:0]  ddr3_wr_mask;
   wire [31:0] ddr3_wr_data;
   wire        ddr3_wr_en;
   reg 	       ddr3_wr_full;
   reg [6:0]   ddr3_wr_count;
   wire        ddr3_cmd_clk;
   wire [2:0]  ddr3_cmd_instr;
   wire        ddr3_cmd_en;
   wire [5:0]  ddr3_cmd_burstlen;
   wire [29:0] ddr3_cmd_addr;
   reg 	       ddr3_cmd_full;

   wire [63:0] time_t_clk100;
   reg 	       reset;

nand_log uut(
		  bclk,
		  clk100,

		  nand_re,
		  nand_we,
		  nand_ale,
		  nand_cle,
		  nand_cs,
		  nand_rb,
		  nand_din,
		  nand_uk,

		  log_reset,
		  log_run,
		  log_cmd_error,
		  log_data_error,
		  log_entries,

		  ddr3_wr_mask,
		  ddr3_wr_data,
		  ddr3_wr_en,
		  ddr3_wr_full,
		  ddr3_wr_count,
		  ddr3_cmd_clk,
		  ddr3_cmd_instr,
		  ddr3_cmd_en,
		  ddr3_cmd_burstlen,
		  ddr3_cmd_addr,
		  ddr3_cmd_full,

		  time_t_clk100,
		  reset
		);

   parameter PERIOD_BCLK = 16'd8;
   always begin
      bclk = 1'b0;
      #(PERIOD_BCLK/2) bclk = 1'b1;
      #(PERIOD_BCLK/2);
   end

   parameter PERIOD_CLK100 = 16'd10;
   always begin
      clk100 = 1'b0;
      #(PERIOD_CLK100/2) clk100 = 1'b1;
      #(PERIOD_CLK100/2);
   end

   task nand_reset;
      begin
	 nand_we = 1'b1;
	 nand_re = 1'b1;
	 nand_ale = 1'b0;
	 nand_cle = 1'b0;
	 nand_cs = 1'b1;
	 nand_din = 8'hZZ;

	 log_reset = 1'b1;
	 log_run = 1'b0;
	 #1000;
	 log_reset = 1'b0;
	 log_run = 1'b1;
	 #1000;
      end
   endtask
   
   task nand_idle;
      begin
	 nand_we = 1'b1;
	 nand_re = 1'b1;
	 nand_ale = 1'b0;
	 nand_cle = 1'b0;
	 nand_cs = 1'b1;
	 nand_din = 8'hZZ;
      end
   endtask

   task nand_read_id;
      begin
	 nand_cs = 1'b0;
	 
	 nand_cle = 1'b1;
	 nand_we = 1'b0;
	 nand_din = 8'h90;
	 #25;
	 nand_we = 1'b1;
	 #5;
	 nand_cle = 1'b0;
	 nand_din = 8'h01;
	 #20;

	 nand_ale = 1'b1;
	 #25;

	 nand_we = 1'b0;
	 nand_din = 8'h00;
	 #25;
	 nand_we = 1'b1;
	 #5;
	 nand_din = 8'h23;
	 #20;

	 nand_ale = 1'b0;

	 #10;
	 nand_re = 1'b0;
	 nand_din = 8'h45;
	 #25;
	 nand_re = 1'b1;
	 #25;
	 nand_re = 1'b0;
	 nand_din = 8'h67;
	 #25;
	 nand_re = 1'b1;
	 #25;
	 nand_re = 1'b0;
	 nand_din = 8'h89;
	 #25;
	 nand_re = 1'b1;
	 #25;
	 nand_re = 1'b0;
	 nand_din = 8'hAB;
	 #25;
	 nand_re = 1'b1;
	 #25;
	 nand_re = 1'b0;
	 nand_din = 8'hCD;
	 #25;
	 nand_re = 1'b1;
	 #25;

	 nand_cs = 1'b1;
      end
   endtask;

   initial begin
      nand_re = 1;
      nand_we = 1;
      nand_ale = 0;
      nand_cle = 0;
      nand_rb = 1;
      nand_din = 8'h00;
      nand_uk[9:0] = 10'h0;
      nand_cs = 1;

      log_reset = 1'b0;
      log_run = 1'b0;
      ddr3_wr_full = 1'b0;
      ddr3_wr_count = 7'b0;
      ddr3_cmd_full = 1'b0;
      
      reset = 1;
      #1000;
      reset = 0;
      nand_reset();
      #1000;
      
      nand_idle();
      #200;
      nand_read_id();

      $stop;

      #1000;
      $stop;
   end
   
endmodule