data/full_repos/permissive/160073872/fpga/hdl/soc.srcs/sources_1/new/mic_data_decimator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160073872/fpga/hdl/soc.srcs/sources_1/new/mic_data_decimator.v:56: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 11 bits.\n                                                                                                            : ... In instance mic_data_decimator\n            data_out <= (micCumSum - micCumSumPrev) >> 3;    \n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mic_data_decimator(
    input wire clk,
    
    input wire signed [7:0] data_in,
    input wire data_in_strobe,
    
    output reg signed [7:0] data_out,
    output reg data_out_strobe
);

    
    reg signed [10:0] micCumSum = 0;
    always @(posedge clk)
        if (data_in_strobe)
            micCumSum <= micCumSum + {{3{data_in[7]}}, data_in};
    
    reg signed [10:0] micCumSumPrev = 0;
    reg signed [15:0] strobe5KhzCounter = 0;
    reg strobe5Khz = 0;
    
    reg [7:0] micDataOn5Khz = 0;
    reg micDataOn5KhzStrobe = 0;
    always @(posedge clk) begin
        if (strobe5KhzCounter >= 16'd1999) begin
            strobe5KhzCounter <= 0;
            strobe5Khz <= 1;
        end else begin
            strobe5KhzCounter <= strobe5KhzCounter + 1;
            strobe5Khz <= 0;
        end
    
        if (strobe5Khz) begin
            micCumSumPrev <= micCumSum;
            data_out <= (micCumSum - micCumSumPrev) >> 3;    
        end
        data_out_strobe <= strobe5Khz;
    end

endmodule
module mic_data_decimator(
    input wire clk,
    
    input wire signed [7:0] data_in,
    input wire data_in_strobe,
    
    output reg signed [7:0] data_out,
    output reg data_out_strobe
);


    
    reg signed [10:0] micCumSum = 0;
    always @(posedge clk)
        if (data_in_strobe)
            micCumSum <= micCumSum + {{3{data_in[7]}}, data_in};
    
    reg signed [10:0] micCumSumPrev = 0;
    reg signed [15:0] strobe5KhzCounter = 0;
    reg strobe5Khz = 0;
    
    reg [7:0] micDataOn5Khz = 0;
    reg micDataOn5KhzStrobe = 0;
    always @(posedge clk) begin
        if (strobe5KhzCounter >= 16'd1999) begin
            strobe5KhzCounter <= 0;
            strobe5Khz <= 1;
        end else begin
            strobe5KhzCounter <= strobe5KhzCounter + 1;
            strobe5Khz <= 0;
        end
    
        if (strobe5Khz) begin
            micCumSumPrev <= micCumSum;
            data_out <= (micCumSum - micCumSumPrev) >> 3;    
        end
        data_out_strobe <= strobe5Khz;
    end

endmodule