data/full_repos/permissive/115837888/source-7400/74273-tb.v
 line:5: before: "tbassert"
1: b'%Error: data/full_repos/permissive/115837888/source-7400/74273-tb.v:5: Define or directive not defined: \'`TBASSERT_METHOD\'\n`TBASSERT_METHOD(tbassert)\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74273-tb.v:5: syntax error, unexpected \'(\'\n`TBASSERT_METHOD(tbassert)\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74273-tb.v:6: Define or directive not defined: \'`TBASSERT_2R_METHOD\'\n`TBASSERT_2R_METHOD(tbassert2R)\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74273-tb.v:32: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("74273-tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/115837888/source-7400/74273-tb.v:33: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n#65\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n#175\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n#4\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n#125\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n#140\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n#120\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n#150\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n#70\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n#2\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n#80\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n#15\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:215: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:217: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n#7\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:222: Unsupported: Ignoring delay on this delayed statement.\n#75\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n#0\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:226: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:228: Unsupported: Ignoring delay on this delayed statement.\n#25\n^\n%Warning-STMTDLY: data/full_repos/permissive/115837888/source-7400/74273-tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: Exiting due to 5 error(s), 67 warning(s)\n'
module test;

`TBASSERT_METHOD(tbassert)
`TBASSERT_2R_METHOD(tbassert2R)

localparam WIDTH = 3;


reg Clear_bar;
reg [WIDTH-1:0] D;
reg Clk;


wire [WIDTH-1:0] Q;


ttl_74273 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .Clear_bar(Clear_bar),
  .D(D),
  .Clk(Clk),
  .Q(Q)
);

initial
begin
  reg [WIDTH-1:0] D_next;
  reg [WIDTH-1:0] Q_expected;
  integer i;

  $dumpfile("74273-tb.vcd");
  $dumpvars;



#65

  tbassert(Q === 3'bxxx, "Test 1");
#0

  Clk = 1'b0;
#7
  tbassert(Q === 3'bxxx, "Test 1");
#0

  D = 3'b000;
#25
  tbassert(Q === 3'bxxx, "Test 1");
#0

  Clk = 1'b1;
#2
  tbassert(Q === 3'bxxx, "Test 1");
#2

  tbassert(Q == 3'b000, "Test 1");
#140

  Clk = 1'b0;
#175
  tbassert(Q == 3'b000, "Test 2");
#0

  D = 3'b111;
#125
  tbassert(Q == 3'b000, "Test 3");
#0

  Clk = 1'b1;
#4
  tbassert(Q == 3'b000, "Test 3");
#2

  tbassert(Q == 3'b111, "Test 3");
#50

  Clk = 1'b0;
#125
  tbassert(Q == 3'b111, "Test 4");
#0

  Clear_bar = 1'b1;
#50
  tbassert(Q == 3'b111, "Test 4");
#0

  D = 3'b101;
#15

  Clk = 1'b1;
#7
  tbassert(Q == 3'b101, "Test 5");
#140

  Clk = 1'b0;
#50
  tbassert(Q == 3'b101, "Test 6");
#0




  Clear_bar = 1'b0;
#2
  tbassert(Q == 3'b101, "Test 7");
#2

  tbassert(Q == 3'b000, "Test 7");
#150

  Clear_bar = 1'b1;
#120
  tbassert(Q == 3'b000, "Test 8");
#50

  D = 3'b011;
#15
  Clk = 1'b1;
#15
  Clk = 1'b0;
#15
  tbassert(Q == 3'b011, "Test 9");
#0

  D = 3'b010;
#15

  Clear_bar = 1'b0;
  Clk = 1'b1;
#2
  tbassert(Q == 3'b011, "Test 9");
#2

  tbassert(Q == 3'b000, "Test 9");
#150

  Clear_bar = 1'b1;
#70
  tbassert(Q == 3'b000, "Test 10");
#50




  D = 3'bxxx;
#15

  Clk = 1'b0;
#15
  Clk = 1'b1;
#15
  tbassert(Q === 3'bxxx, "Test 11");
#0

  Clear_bar = 1'bx;
  Clk = 1'bx;
#15

  Clear_bar = 1'b0;
#2
  tbassert(Q === 3'bxxx, "Test 11");
#2

  tbassert(Q == 3'b000, "Test 11");
#75

  Clear_bar = 1'b1;
#80
  tbassert(Q == 3'b000, "Test 12");
#0
  D = 3'b000;
#15

  Clk = 1'b1;
#15
  tbassert(Q == 3'b000, "Test 12");
#0
  Clk = 1'b0;
#15
  tbassert(Q == 3'b000, "Test 12");
#0



  D_next = 3'b000;

  for (i = 1; i <= 3; i++)
  begin
    Q_expected = D_next;

    case (i)
      1:
      begin
        D_next = 3'b110;
      end
      2:
      begin
        D_next = 3'b001;
      end
      3:
      begin
        D_next = 3'b111;
      end
    endcase
#20

    D = Q_expected;
#7
    Clk = 1'b1;
#20
    tbassert2R(Q == Q_expected, "Test", "1", (12 + i));
#0
    Clk = 1'b0;
#50
    tbassert2R(Q == Q_expected, "Test", "1", (12 + i));
#0

    Clk = 1'b1;
#7
    D = D_next;
#75
    tbassert2R(Q == Q_expected, "Test", "2", (12 + i));
#0
    Clk = 1'b0;
#25
    D = 3'bzzz;
#25
    tbassert2R(Q == Q_expected, "Test", "2", (12 + i));

  end



  tbassert2R(Q == 3'b001, "Test", "2", 15);
#50
  $finish;
end

endmodule
module test;


`TBASSERT_METHOD(tbassert)
`TBASSERT_2R_METHOD(tbassert2R)

localparam WIDTH = 3;


reg Clear_bar;
reg [WIDTH-1:0] D;
reg Clk;


wire [WIDTH-1:0] Q;


ttl_74273 #(.WIDTH(WIDTH), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
  .Clear_bar(Clear_bar),
  .D(D),
  .Clk(Clk),
  .Q(Q)
);

initial
begin
  reg [WIDTH-1:0] D_next;
  reg [WIDTH-1:0] Q_expected;
  integer i;

  $dumpfile("74273-tb.vcd");
  $dumpvars;



#65

  tbassert(Q === 3'bxxx, "Test 1");
#0

  Clk = 1'b0;
#7
  tbassert(Q === 3'bxxx, "Test 1");
#0

  D = 3'b000;
#25
  tbassert(Q === 3'bxxx, "Test 1");
#0

  Clk = 1'b1;
#2
  tbassert(Q === 3'bxxx, "Test 1");
#2

  tbassert(Q == 3'b000, "Test 1");
#140

  Clk = 1'b0;
#175
  tbassert(Q == 3'b000, "Test 2");
#0

  D = 3'b111;
#125
  tbassert(Q == 3'b000, "Test 3");
#0

  Clk = 1'b1;
#4
  tbassert(Q == 3'b000, "Test 3");
#2

  tbassert(Q == 3'b111, "Test 3");
#50

  Clk = 1'b0;
#125
  tbassert(Q == 3'b111, "Test 4");
#0

  Clear_bar = 1'b1;
#50
  tbassert(Q == 3'b111, "Test 4");
#0

  D = 3'b101;
#15

  Clk = 1'b1;
#7
  tbassert(Q == 3'b101, "Test 5");
#140

  Clk = 1'b0;
#50
  tbassert(Q == 3'b101, "Test 6");
#0




  Clear_bar = 1'b0;
#2
  tbassert(Q == 3'b101, "Test 7");
#2

  tbassert(Q == 3'b000, "Test 7");
#150

  Clear_bar = 1'b1;
#120
  tbassert(Q == 3'b000, "Test 8");
#50

  D = 3'b011;
#15
  Clk = 1'b1;
#15
  Clk = 1'b0;
#15
  tbassert(Q == 3'b011, "Test 9");
#0

  D = 3'b010;
#15

  Clear_bar = 1'b0;
  Clk = 1'b1;
#2
  tbassert(Q == 3'b011, "Test 9");
#2

  tbassert(Q == 3'b000, "Test 9");
#150

  Clear_bar = 1'b1;
#70
  tbassert(Q == 3'b000, "Test 10");
#50




  D = 3'bxxx;
#15

  Clk = 1'b0;
#15
  Clk = 1'b1;
#15
  tbassert(Q === 3'bxxx, "Test 11");
#0

  Clear_bar = 1'bx;
  Clk = 1'bx;
#15

  Clear_bar = 1'b0;
#2
  tbassert(Q === 3'bxxx, "Test 11");
#2

  tbassert(Q == 3'b000, "Test 11");
#75

  Clear_bar = 1'b1;
#80
  tbassert(Q == 3'b000, "Test 12");
#0
  D = 3'b000;
#15

  Clk = 1'b1;
#15
  tbassert(Q == 3'b000, "Test 12");
#0
  Clk = 1'b0;
#15
  tbassert(Q == 3'b000, "Test 12");
#0



  D_next = 3'b000;

  for (i = 1; i <= 3; i++)
  begin
    Q_expected = D_next;

    case (i)
      1:
      begin
        D_next = 3'b110;
      end
      2:
      begin
        D_next = 3'b001;
      end
      3:
      begin
        D_next = 3'b111;
      end
    endcase
#20

    D = Q_expected;
#7
    Clk = 1'b1;
#20
    tbassert2R(Q == Q_expected, "Test", "1", (12 + i));
#0
    Clk = 1'b0;
#50
    tbassert2R(Q == Q_expected, "Test", "1", (12 + i));
#0

    Clk = 1'b1;
#7
    D = D_next;
#75
    tbassert2R(Q == Q_expected, "Test", "2", (12 + i));
#0
    Clk = 1'b0;
#25
    D = 3'bzzz;
#25
    tbassert2R(Q == Q_expected, "Test", "2", (12 + i));

  end



  tbassert2R(Q == 3'b001, "Test", "2", 15);
#50
  $finish;
end

endmodule