data/full_repos/permissive/185658197/src/step-4/verilog/multiplier.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/185658197/src/step-4/verilog/multiplier.v:124: Cell has missing pin: \'c\'\n  Subtractor #(.bits(16)) final_subtractor (\n                          ^~~~~~~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-4/verilog/multiplier.v:30: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                       : ... In instance Multiplier.register1\n  reg [(bits-1):0] state = \'hX;\n                           ^~~\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-4/verilog/multiplier.v:30: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                       : ... In instance Multiplier.register2\n  reg [(bits-1):0] state = \'hX;\n                           ^~~\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-4/verilog/multiplier.v:30: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                       : ... In instance Multiplier.register3\n  reg [(bits-1):0] state = \'hX;\n                           ^~~\n%Error: Exiting due to 4 warning(s)\n'
module Multiplier  (
  input clk,
  input [7:0] a,
  input [7:0] b,
  input sgnd,
  output [15:0] p
);  
  wire [7:0] adder_s;
  wire adder_c;
  Adder #(.bits(8)) adder (
    .a(a),
    .b(b),
    .s(adder_s),
    .c(adder_c)
  );
  
  wire [7:0] subtractor_d;
  wire subtractor_c;
  Subtractor #(.bits(8)) subtractor (
    .a(a),
    .b(b),
    .d(subtractor_d),
    .c(subtractor_c)
  );
  
  wire invert_carry = (a[7] ^ b[7]) & sgnd;  
  
  wire [9:0] register1_input;
  assign register1_input[7:0] = adder_s;
  assign register1_input[8] = adder_c ^ invert_carry;
  assign register1_input[9] = sgnd;  
  
  wire [8:0] register2_input;  
  assign register2_input[7:0] = subtractor_d;
  assign register2_input[8] = subtractor_c ^ invert_carry;
  
  wire [9:0] rom1_address;  
  Register #(.bits(10)) register1 (
    .clk(clk),
    .d(register1_input),
    .q(rom1_address)
  ); 
  
  wire [8:0] rom2_address;  
  Register #(.bits(9)) register2 (
    .clk(clk),
    .d(register2_input),
    .q(rom2_address)
  ); 

  wire [15:0] rom1_data;
  ROM #(.address_bits(10), .file("rom1.hex")) rom1 (
    .address(rom1_address),
    .data(rom1_data)
  ); 

  wire [15:0] rom2_data;  
  ROM #(.address_bits(9), .file("rom2.hex")) rom2 (
    .address(rom2_address),
    .data(rom2_data)
  ); 
  
  wire [15:0] register_3_output;
  Register #(.bits(16)) register3 (
    .clk(clk),
    .d(rom1_data),
    .q(register_3_output)
  ); 
  
  wire [15:0] register_4_output;  
  Register #(.bits(16)) register4 (
    .clk(clk),
    .d(rom2_data),
    .q(register_4_output)
  );
  
  Subtractor #(.bits(16)) final_subtractor (
    .a(register_3_output),
    .b(register_4_output),
    .d(p)
  );
endmodule
module Multiplier  (
  input clk,
  input [7:0] a,
  input [7:0] b,
  input sgnd,
  output [15:0] p
);
  
  wire [7:0] adder_s;
  wire adder_c;
  Adder #(.bits(8)) adder (
    .a(a),
    .b(b),
    .s(adder_s),
    .c(adder_c)
  );
  
  wire [7:0] subtractor_d;
  wire subtractor_c;
  Subtractor #(.bits(8)) subtractor (
    .a(a),
    .b(b),
    .d(subtractor_d),
    .c(subtractor_c)
  );
  
  wire invert_carry = (a[7] ^ b[7]) & sgnd;  
  
  wire [9:0] register1_input;
  assign register1_input[7:0] = adder_s;
  assign register1_input[8] = adder_c ^ invert_carry;
  assign register1_input[9] = sgnd;  
  
  wire [8:0] register2_input;  
  assign register2_input[7:0] = subtractor_d;
  assign register2_input[8] = subtractor_c ^ invert_carry;
  
  wire [9:0] rom1_address;  
  Register #(.bits(10)) register1 (
    .clk(clk),
    .d(register1_input),
    .q(rom1_address)
  ); 
  
  wire [8:0] rom2_address;  
  Register #(.bits(9)) register2 (
    .clk(clk),
    .d(register2_input),
    .q(rom2_address)
  ); 

  wire [15:0] rom1_data;
  ROM #(.address_bits(10), .file("rom1.hex")) rom1 (
    .address(rom1_address),
    .data(rom1_data)
  ); 

  wire [15:0] rom2_data;  
  ROM #(.address_bits(9), .file("rom2.hex")) rom2 (
    .address(rom2_address),
    .data(rom2_data)
  ); 
  
  wire [15:0] register_3_output;
  Register #(.bits(16)) register3 (
    .clk(clk),
    .d(rom1_data),
    .q(register_3_output)
  ); 
  
  wire [15:0] register_4_output;  
  Register #(.bits(16)) register4 (
    .clk(clk),
    .d(rom2_data),
    .q(register_4_output)
  );
  
  Subtractor #(.bits(16)) final_subtractor (
    .a(register_3_output),
    .b(register_4_output),
    .d(p)
  );
endmodule