data/full_repos/permissive/210844779/lab5/5.2/tb.v
 line:26: before: "u0"
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.2/tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.2/tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Error: data/full_repos/permissive/210844779/lab5/5.2/tb.v:26: Unsupported: Verilog 1995 force\n   force u0.q=0;\n   ^~~~~\n%Error: data/full_repos/permissive/210844779/lab5/5.2/tb.v:27: Unsupported: Verilog 1995 release\n   #13 release u0.q;\n       ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.2/tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #13 release u0.q;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.2/tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n   #17\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.2/tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #16\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.2/tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #15\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.2/tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #17\n    ^\n%Error: data/full_repos/permissive/210844779/lab5/5.2/tb.v:39: Unsupported: Verilog 1995 force\n    force u0.q=0;\n    ^~~~~\n%Error: data/full_repos/permissive/210844779/lab5/5.2/tb.v:40: Unsupported: Verilog 1995 release\n    #20 release u0.q;\n        ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.2/tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #20 release u0.q;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.2/tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.2/tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.2/tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: Exiting due to 4 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  reg d,clk,clr,preset;
  wire q;
  
  dff u0(d,clk,clr,preset,q);
  
  always

 begin
  
clk=1;
  
#5
  
clk=0;
  
#5;

 end

 initial
  begin
   clr=0;
   preset=1;
   
   force u0.q=0;
   #13 release u0.q;
   clr=1;
   preset=0;
   #17
   
    d=0;
    #16
    d=0;
    #15
    d=1;
    #17
    d=0;
    force u0.q=0;
    #20 release u0.q;
    
    d=1;
    #20
    d=0;
    #20
    d=1;
    #20;
 end
   

 
endmodule
module tb();

  reg d,clk,clr,preset;
  wire q;
  
  dff u0(d,clk,clr,preset,q);
  
  always

 begin
  
clk=1;
  
#5
  
clk=0;
  
#5;

 end

 initial
  begin
   clr=0;
   preset=1;
   
   force u0.q=0;
   #13 release u0.q;
   clr=1;
   preset=0;
   #17
   
    d=0;
    #16
    d=0;
    #15
    d=1;
    #17
    d=0;
    force u0.q=0;
    #20 release u0.q;
    
    d=1;
    #20
    d=0;
    #20
    d=1;
    #20;
 end
   

 
endmodule