data/full_repos/permissive/177039499/instruction-fetch/inst-mem.v
data/verilator_xmls/865fcb98-877e-46c3-a7f3-f12f336caf09.xml
module instMem(
    input  wire        clk,
    input  wire        reset,
    input  wire [31:0] address,
    
    output wire [31:0] inst
);

    reg [31:0] instructionMemory [255:0];

    assign inst = instructionMemory[address[9:2]];

    always @(negedge clk) begin
        if (reset)
            $readmemb("instruction-fetch/program.txt",instructionMemory);
    end
    
endmodule
module instMem(
    input  wire        clk,
    input  wire        reset,
    input  wire [31:0] address,
    
    output wire [31:0] inst
);


    reg [31:0] instructionMemory [255:0];

    assign inst = instructionMemory[address[9:2]];

    always @(negedge clk) begin
        if (reset)
            $readmemb("instruction-fetch/program.txt",instructionMemory);
    end
    
endmodule