data/full_repos/permissive/161275071/mem/backup.v
1: b"%Error: data/full_repos/permissive/161275071/mem/backup.v:34: Cannot find file containing module: 'dpram'\n dpram #(.ADDRWIDTH(15)) SRAML(\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/161275071/mem,data/full_repos/permissive/161275071/dpram\n             data/full_repos/permissive/161275071/mem,data/full_repos/permissive/161275071/dpram.v\n             data/full_repos/permissive/161275071/mem,data/full_repos/permissive/161275071/dpram.sv\n             dpram\n             dpram.v\n             dpram.sv\n             obj_dir/dpram\n             obj_dir/dpram.v\n             obj_dir/dpram.sv\n%Error: data/full_repos/permissive/161275071/mem/backup.v:48: Cannot find file containing module: 'dpram'\n dpram #(.ADDRWIDTH(15)) SRAMU(\n ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module backup(
	input CLK_24M,
	input [15:1] M68K_ADDR,
	input nBWL, nBWU,
	input [15:0] M68K_DATA,
	output [15:0] SRAM_OUT,
	input clk_sys,
	input [14:0] sram_addr,
	input sram_wr,
	input [15:0] sd_buff_dout,
	output [15:0] sd_buff_din_sram
);

	dpram #(.ADDRWIDTH(15)) SRAML(
		.clock_a(CLK_24M),
		.address_a(M68K_ADDR[15:1]),
		.wren_a(~nBWL),
		.data_a(M68K_DATA[7:0]),
		.q_a(SRAM_OUT[7:0]),
		
		.clock_b(clk_sys),
		.address_b(sram_addr),
		.wren_b(sram_wr),
		.data_b(sd_buff_dout[7:0]),
		.q_b(sd_buff_din_sram[7:0])
	);
	
	dpram #(.ADDRWIDTH(15)) SRAMU(
		.clock_a(CLK_24M),
		.address_a(M68K_ADDR[15:1]),
		.wren_a(~nBWU),
		.data_a(M68K_DATA[15:8]),
		.q_a(SRAM_OUT[15:8]),
		
		.clock_b(clk_sys),
		.address_b(sram_addr),
		.wren_b(sram_wr),
		.data_b(sd_buff_dout[15:8]),
		.q_b(sd_buff_din_sram[15:8])
	);
	
endmodule
module backup(
	input CLK_24M,
	input [15:1] M68K_ADDR,
	input nBWL, nBWU,
	input [15:0] M68K_DATA,
	output [15:0] SRAM_OUT,
	input clk_sys,
	input [14:0] sram_addr,
	input sram_wr,
	input [15:0] sd_buff_dout,
	output [15:0] sd_buff_din_sram
);


	dpram #(.ADDRWIDTH(15)) SRAML(
		.clock_a(CLK_24M),
		.address_a(M68K_ADDR[15:1]),
		.wren_a(~nBWL),
		.data_a(M68K_DATA[7:0]),
		.q_a(SRAM_OUT[7:0]),
		
		.clock_b(clk_sys),
		.address_b(sram_addr),
		.wren_b(sram_wr),
		.data_b(sd_buff_dout[7:0]),
		.q_b(sd_buff_din_sram[7:0])
	);
	
	dpram #(.ADDRWIDTH(15)) SRAMU(
		.clock_a(CLK_24M),
		.address_a(M68K_ADDR[15:1]),
		.wren_a(~nBWU),
		.data_a(M68K_DATA[15:8]),
		.q_a(SRAM_OUT[15:8]),
		
		.clock_b(clk_sys),
		.address_b(sram_addr),
		.wren_b(sram_wr),
		.data_b(sd_buff_dout[15:8]),
		.q_b(sd_buff_din_sram[15:8])
	);
	
endmodule