data/full_repos/permissive/146618947/compuertas/libreria.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/146618947/compuertas/libreria.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #(1.4:3:4.6) Q <= D;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/146618947/compuertas/libreria.v:114: Multiple top level modules\n                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                 : ... Top module \'flip_flop_delay\'\nmodule flip_flop_delay (\n       ^~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'mux_21_4_delay\'\nmodule mux_21_4_delay (\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_21_4_delay (
                       output [3:0] Q,
                       input [3:0] A,
                       input [3:0] B,
                       input S,
                       input Reset_L
                       );

   parameter PwrC = 0.000015;

   mux_21_delay bit_0 (Q[0], A[0], B[0], S, Reset_L);
   mux_21_delay bit_1 (Q[1], A[1], B[1], S, Reset_L);
   mux_21_delay bit_2 (Q[2], A[2], B[2], S, Reset_L);
   mux_21_delay bit_3 (Q[3], A[3], B[3], S, Reset_L);

endmodule
module mux_21_4_delay (
                       output [3:0] Q,
                       input [3:0] A,
                       input [3:0] B,
                       input S,
                       input Reset_L
                       );


   parameter PwrC = 0.000015;

   mux_21_delay bit_0 (Q[0], A[0], B[0], S, Reset_L);
   mux_21_delay bit_1 (Q[1], A[1], B[1], S, Reset_L);
   mux_21_delay bit_2 (Q[2], A[2], B[2], S, Reset_L);
   mux_21_delay bit_3 (Q[3], A[3], B[3], S, Reset_L);

endmodule