data/full_repos/permissive/18921956/template/if-else_t.v
1: b'%Error: data/full_repos/permissive/18921956/template/if-else_t.v:19: Unsupported or unknown PLI call: $monitor\n        $monitor("en = %d, i_a = %d, i_b = %d, o_sum = %d", en, i_a, i_b, o_sum);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/18921956/template/if-else_t.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #10 en = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/18921956/template/if-else_t.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10 en = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/template/if-else_t.v:26: Unsupported: Ignoring delay on this delayed statement.\n            #10 i_a = ~i_a;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/template/if-else_t.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #20 i_a = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/template/if-else_t.v:32: Unsupported: Ignoring delay on this delayed statement.\n            #10 i_a = ~i_a;\n            ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestIfElse;
    reg i_a, i_b, en;
    wire o_sum;
    integer i;
    If_Else_Block ieb(
        .o_sum(o_sum),
        .i_a(i_a),
        .i_b(i_b),
        .en(en)
    );
    initial begin
        $monitor("en = %d, i_a = %d, i_b = %d, o_sum = %d", en, i_a, i_b, o_sum);
        #10 en = 0;
        i_a = 0;
        i_b = 0;
        #10 en = 1;
        i_a = 1;
        for (i = 0; i < 10; i = i + 1) begin
            #10 i_a = ~i_a;
            i_b = ~i_b;
        end
        #20 i_a = 1;
        i_b = 1;
        for (i = 0; i < 10; i = i + 1) begin
            #10 i_a = ~i_a;
            i_b = ~i_b;
        end
    end
    
endmodule
module TestIfElse;

    reg i_a, i_b, en;
    wire o_sum;
    integer i;
    If_Else_Block ieb(
        .o_sum(o_sum),
        .i_a(i_a),
        .i_b(i_b),
        .en(en)
    );
    initial begin
        $monitor("en = %d, i_a = %d, i_b = %d, o_sum = %d", en, i_a, i_b, o_sum);
        #10 en = 0;
        i_a = 0;
        i_b = 0;
        #10 en = 1;
        i_a = 1;
        for (i = 0; i < 10; i = i + 1) begin
            #10 i_a = ~i_a;
            i_b = ~i_b;
        end
        #20 i_a = 1;
        i_b = 1;
        for (i = 0; i < 10; i = i + 1) begin
            #10 i_a = ~i_a;
            i_b = ~i_b;
        end
    end
    
endmodule