data/full_repos/permissive/159001439/src/net_csum.v
 line:15: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/159001439/src/net_csum.v:19: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                      : ... In instance net_csum\n  cyclic_carry_add = sum[15:0] + sum[16];\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/net_csum.v:93: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                      : ... In instance net_csum\n  sum_2 <= 32\'b0;\n        ^~\n%Error: Exiting due to 2 warning(s)\n'
module net_csum(
	input clk,
	input rst,

	input clear,

	input [31:0] data,
	input [3:0] keep,
	input valid,

	output [15:0] csum,
	output csum_valid
);

function [15:0] cyclic_carry_add(input [15:0] a, input [15:0] b);
	reg [16:0] sum;
	begin
		sum = a + b;
		cyclic_carry_add = sum[15:0] + sum[16];
	end
endfunction

reg valid_0, valid_1, valid_2;
reg [31:0] data_0;
reg [15:0] sum_low_1;
reg [15:0] sum_high_1;
reg [15:0] sum_2;

assign csum = ~sum_2;
assign csum_valid = valid_2;


always @(posedge clk, posedge rst)
begin
	if(rst) begin
		valid_0 <= 1'b0;
		valid_1 <= 1'b0;
		valid_2 <= 1'b0;
	end
	else if(clear) begin
		valid_0 <= 1'b0;
		valid_1 <= 1'b0;
		valid_2 <= 1'b0;
	end
	else begin
		valid_0 <= valid;
		valid_1 <= valid_0;
		valid_2 <= valid_1;
	end
end




always @(posedge clk)
begin
	if(clear) begin
		data_0 <= 32'b0;
	end
	else if(valid) begin 
		data_0[31:24] <= keep[3]?data[31:24]:8'b0;
		data_0[23:16] <= keep[2]?data[23:16]:8'b0;
		data_0[15:8] <= keep[1]?data[15:8]:8'b0;
		data_0[7:0] <= keep[0]?data[7:0]:8'b0;
	end
end




always @(posedge clk, posedge rst)
begin
	if(rst) begin
		sum_low_1 <= 'b0;
		sum_high_1 <= 'b0;
	end
	else if(clear) begin
		sum_low_1 <= 'b0;
		sum_high_1 <= 'b0;
	end
	else if(valid_0) begin
		sum_low_1 <= cyclic_carry_add(sum_low_1, data_0[15:0]);
		sum_high_1 <= cyclic_carry_add(sum_high_1, data_0[31:16]);
	end
end




always @(posedge clk)
begin
	if(clear) begin
		sum_2 <= 32'b0;
	end
	else if(valid_1) begin
		sum_2 <= cyclic_carry_add(sum_low_1, sum_high_1);
	end
end

endmodule
module net_csum(
	input clk,
	input rst,

	input clear,

	input [31:0] data,
	input [3:0] keep,
	input valid,

	output [15:0] csum,
	output csum_valid
);


function [15:0] cyclic_carry_add(input [15:0] a, input [15:0] b);
	reg [16:0] sum;
	begin
		sum = a + b;
		cyclic_carry_add = sum[15:0] + sum[16];
	end
endfunction

reg valid_0, valid_1, valid_2;
reg [31:0] data_0;
reg [15:0] sum_low_1;
reg [15:0] sum_high_1;
reg [15:0] sum_2;

assign csum = ~sum_2;
assign csum_valid = valid_2;


always @(posedge clk, posedge rst)
begin
	if(rst) begin
		valid_0 <= 1'b0;
		valid_1 <= 1'b0;
		valid_2 <= 1'b0;
	end
	else if(clear) begin
		valid_0 <= 1'b0;
		valid_1 <= 1'b0;
		valid_2 <= 1'b0;
	end
	else begin
		valid_0 <= valid;
		valid_1 <= valid_0;
		valid_2 <= valid_1;
	end
end




always @(posedge clk)
begin
	if(clear) begin
		data_0 <= 32'b0;
	end
	else if(valid) begin 
		data_0[31:24] <= keep[3]?data[31:24]:8'b0;
		data_0[23:16] <= keep[2]?data[23:16]:8'b0;
		data_0[15:8] <= keep[1]?data[15:8]:8'b0;
		data_0[7:0] <= keep[0]?data[7:0]:8'b0;
	end
end




always @(posedge clk, posedge rst)
begin
	if(rst) begin
		sum_low_1 <= 'b0;
		sum_high_1 <= 'b0;
	end
	else if(clear) begin
		sum_low_1 <= 'b0;
		sum_high_1 <= 'b0;
	end
	else if(valid_0) begin
		sum_low_1 <= cyclic_carry_add(sum_low_1, data_0[15:0]);
		sum_high_1 <= cyclic_carry_add(sum_high_1, data_0[31:16]);
	end
end




always @(posedge clk)
begin
	if(clear) begin
		sum_2 <= 32'b0;
	end
	else if(valid_1) begin
		sum_2 <= cyclic_carry_add(sum_low_1, sum_high_1);
	end
end

endmodule