data/full_repos/permissive/107499099/mips_de2-115/MIPS/main_ctrl.v
'utf-8' codec can't decode byte 0xc4 in position 679: invalid continuation byte
data/verilator_xmls/6ad8b8b9-65ca-41c0-9bfd-a09cdbbba223.xml
module main_ctrl (instruction,
		  ram_write_enable,
		  alu_b_sel1_s,
		  alu_b_sel2_s,
		  alu_op,
                  is_branch_ctrl,
                  reg_write_enable,
                  alu_ram_sel_s,
		  reg_widx_sel1_s,
		  jp,
		  link,
		  jpr,
		  shiftv,
		  do_sign_ext
);
  input [31:0] instruction;

  output      ram_write_enable;
  output          alu_b_sel1_s;
  output          alu_b_sel2_s;
  output  [2:0]         alu_op;
  output  [2:0] is_branch_ctrl;
  output      reg_write_enable;
  output         alu_ram_sel_s;
  output       reg_widx_sel1_s;
  output                    jp;
  output                  link;
  output                   jpr;
  output                shiftv;
  output           do_sign_ext;



  wire  [5:0]        op_code;

  wire  [4:0]         Rrs;
  wire  [4:0]         Rrt;
  wire  [4:0]         Rrd;
  wire  [4:0]         Rshamt;
  wire  [5:0]         Rfunc;

  assign op_code = instruction[31:26];

  assign Rrs    = instruction[25:21];
  assign Rrt    = instruction[20:16];
  assign Rrd    = instruction[15:11];
  assign Rshamt = instruction[10:6];
  assign Rfunc  = instruction[5:0];

  wire  [4:0]         Irs;
  wire  [4:0]         Irt;
  wire [15:0]         Iaddr;

  assign Irs    = instruction[25:21];
  assign Irt    = instruction[20:16];
  assign Iaddr  = instruction[15:0];

  wire [25:0]         Jaddr;

  assign Jaddr  = instruction[25:0];

  reg    [2:0] is_branch_ctrl_tmp;
  reg            alu_b_sel1_s_tmp;
  reg    [2:0]         alu_op_tmp;
  reg        reg_write_enable_tmp;
  reg           alu_ram_sel_s_tmp;
  reg         reg_widx_sel1_s_tmp;
  reg 	                  link_tmp;
   
   









  assign  ram_write_enable = (op_code == `SW) ? 1'b1 : 1'b0;















  always @(op_code) begin
    case (op_code)
      `R:      is_branch_ctrl_tmp = 3'b110;



      `LW:     is_branch_ctrl_tmp = 3'b110;







      `SW:     is_branch_ctrl_tmp = 3'b110;



      `ADDI:   is_branch_ctrl_tmp = 3'b110;



      `ADDIU:  is_branch_ctrl_tmp = 3'b110;



      `ANDI:   is_branch_ctrl_tmp = 3'b110;
      `ORI:    is_branch_ctrl_tmp = 3'b110;
      `BEQ:    is_branch_ctrl_tmp = 3'b000;



      `BNE:    is_branch_ctrl_tmp = 3'b001;



      `BGEZ:   is_branch_ctrl_tmp = 3'b010;
      `BLEZ:   is_branch_ctrl_tmp = 3'b011;
      `BGTZ:   is_branch_ctrl_tmp = 3'b100;
      `BLTZ:   is_branch_ctrl_tmp = 3'b101;
      `BGEZAL: is_branch_ctrl_tmp = 3'b010;
      `BLTZAL: is_branch_ctrl_tmp = 3'b101;
      `XORI:   is_branch_ctrl_tmp = 3'b110;
      `SLTI:   is_branch_ctrl_tmp = 3'b110;



      `SLTIU:  is_branch_ctrl_tmp = 3'b110;



      `LUI:    is_branch_ctrl_tmp = 3'b110;
      default: is_branch_ctrl_tmp = 3'b110;
    endcase
  end

  assign  is_branch_ctrl = is_branch_ctrl_tmp;













  assign  jp = ((op_code == `J) || (op_code == `JAL)) ? 1'b1 : 1'b0;













  assign  jpr = (op_code == `R &&
                (Rfunc == 6'b001001



                  || Rfunc == 6'b001000)) ? 1'b1 : 1'b0;





  assign  shiftv = (op_code == `R &&
                (Rfunc == 6'b000000 || Rfunc == 6'b000010
                                    || Rfunc == 6'b000011)) ? 1'b1 : 1'b0;







  always @(op_code) begin
    case (op_code)
      `R:      alu_b_sel1_s_tmp = 1'b0;



      `LW:     alu_b_sel1_s_tmp = 1'b1;







      `SW:     alu_b_sel1_s_tmp = 1'b1;



      `ADDI:   alu_b_sel1_s_tmp = 1'b1;



      `ADDIU:  alu_b_sel1_s_tmp = 1'b1;



      `ANDI:   alu_b_sel1_s_tmp = 1'b1;
      `ORI:    alu_b_sel1_s_tmp = 1'b1;
      `BEQ:    alu_b_sel1_s_tmp = 1'b0;



      `BNE:    alu_b_sel1_s_tmp = 1'b0;




      `XORI:   alu_b_sel1_s_tmp = 1'b1;
      `SLTI:   alu_b_sel1_s_tmp = 1'b1;



      `SLTIU:  alu_b_sel1_s_tmp = 1'b1;



      `LUI:    alu_b_sel1_s_tmp = 1'b1;
      default: alu_b_sel1_s_tmp = 1'b0;
    endcase
  end
  assign  alu_b_sel1_s = alu_b_sel1_s_tmp;
   


  assign alu_b_sel2_s = (op_code == 6'b000001) ? 1'b1 : 1'b0;









  assign do_sign_ext = ((op_code == `ADDI)



                        || (op_code == `ADDIU)



                        || (op_code == `SW)


                        || (op_code == `LW)



                        || (op_code == `SLTI)
                        || (op_code == `BEQ)



                        || (op_code == `BNE)



                        || (op_code == `BGEZ) || (op_code == `BLEZ)
                        || (op_code == `BGTZ) || (op_code == `BLTZ)
                        || (op_code == `BGEZAL) || (op_code == `BLTZAL)) ? 1'b1 : 1'b0;













  always @(op_code) begin
    case (op_code)
      `R:      alu_op_tmp = 3'b010;



      `LW:     alu_op_tmp = 3'b000;







      `SW:     alu_op_tmp = 3'b000;



      `ADDI:   alu_op_tmp = 3'b000;



      `ADDIU:  alu_op_tmp = 3'b000;



      `ANDI:   alu_op_tmp = 3'b011;
      `ORI:    alu_op_tmp = 3'b100;
      `XORI:   alu_op_tmp = 3'b101;
      `SLTI:   alu_op_tmp = 3'b110;



      `SLTIU:  alu_op_tmp = 3'b111;



      `LUI:    alu_op_tmp = 3'b001;
      default: alu_op_tmp = 3'b000;
    endcase
  end
  assign  alu_op = alu_op_tmp;







  always @(op_code) begin
    case (op_code)
      `R: begin
            if (Rfunc == 6'b001000) begin



              reg_write_enable_tmp = 1'b0;



            end else begin
              reg_write_enable_tmp = 1'b1;
            end
          end




      `LW:     reg_write_enable_tmp = 1'b1;







      `SW:     reg_write_enable_tmp = 1'b0;



      `ADDI:   reg_write_enable_tmp = 1'b1;



      `ADDIU:  reg_write_enable_tmp = 1'b1;



      `ANDI:   reg_write_enable_tmp = 1'b1;
      `ORI:    reg_write_enable_tmp = 1'b1;
      `BEQ:    reg_write_enable_tmp = 1'b0;



      `BNE:    reg_write_enable_tmp = 1'b0;







      `J:      reg_write_enable_tmp = 1'b0;







      `JAL:    reg_write_enable_tmp = 1'b1;



      `XORI:   reg_write_enable_tmp = 1'b1;
      `SLTI:   reg_write_enable_tmp = 1'b1;



      `SLTIU:  reg_write_enable_tmp = 1'b1;



      `LUI:    reg_write_enable_tmp = 1'b1;
      default: reg_write_enable_tmp = 1'b0;
    endcase
  end
  assign  reg_write_enable = reg_write_enable_tmp;







  always @(op_code) begin
    case (op_code)
      `R:      alu_ram_sel_s_tmp = 1'b0;



      `LW:     alu_ram_sel_s_tmp = 1'b1;




      `ADDI:   alu_ram_sel_s_tmp = 1'b0;



      `ADDIU:  alu_ram_sel_s_tmp = 1'b0;



      `ANDI:   alu_ram_sel_s_tmp = 1'b0;
      `ORI:    alu_ram_sel_s_tmp = 1'b0;
      `BEQ:    alu_ram_sel_s_tmp = 1'b0;
      `XORI:   alu_ram_sel_s_tmp = 1'b0;
      `SLTI:   alu_ram_sel_s_tmp = 1'b0;



      `SLTIU:  alu_ram_sel_s_tmp = 1'b0;



      `LUI:    alu_ram_sel_s_tmp = 1'b0;
      default: alu_ram_sel_s_tmp = 1'b0;
    endcase
  end
  assign  alu_ram_sel_s = alu_ram_sel_s_tmp;







  always @(op_code) begin
    case (op_code)
      `R:      reg_widx_sel1_s_tmp = 1'b1;



      `LW:     reg_widx_sel1_s_tmp = 1'b0;




      `ADDI:   reg_widx_sel1_s_tmp = 1'b0;



      `ADDIU:  reg_widx_sel1_s_tmp = 1'b0;



      `ANDI:   reg_widx_sel1_s_tmp = 1'b0;
      `ORI:    reg_widx_sel1_s_tmp = 1'b0;
      `BEQ:    reg_widx_sel1_s_tmp = 1'b0;
      `XORI:   reg_widx_sel1_s_tmp = 1'b0;
      `SLTI:   reg_widx_sel1_s_tmp = 1'b0;



      `SLTIU:  reg_widx_sel1_s_tmp = 1'b0;



      `LUI:    reg_widx_sel1_s_tmp = 1'b0;
      default: reg_widx_sel1_s_tmp = 1'b0;
    endcase
  end
  assign  reg_widx_sel1_s = reg_widx_sel1_s_tmp;







  always @(op_code) begin
    case (op_code)
      `R: begin
            if (Rfunc == 6'b001001) begin
              link_tmp = 1'b1;
            end else begin
              link_tmp = 1'b0;
            end
          end



      `LW:     link_tmp = 1'b0;




      `ADDI:   link_tmp = 1'b0;



      `ADDIU:  link_tmp = 1'b0;



      `ANDI:   link_tmp = 1'b0;
      `ORI:    link_tmp = 1'b0;
      `BEQ:    link_tmp = 1'b0;
      `BGEZ:   link_tmp = 1'b0;
      `BLEZ:   link_tmp = 1'b0;
      `BGTZ:   link_tmp = 1'b0;
      `BLTZ:   link_tmp = 1'b0;
      `BGEZAL: link_tmp = 1'b1;
      `BLTZAL: link_tmp = 1'b1;




      `JAL:    link_tmp = 1'b1;



      `XORI:   link_tmp = 1'b0;
      `SLTI:   link_tmp = 1'b0;



      `SLTIU:  link_tmp = 1'b0;



      `LUI:    link_tmp = 1'b0;
      default: link_tmp = 1'b0;
    endcase
  end
  assign  link = link_tmp;

endmodule
module main_ctrl (instruction,
		  ram_write_enable,
		  alu_b_sel1_s,
		  alu_b_sel2_s,
		  alu_op,
                  is_branch_ctrl,
                  reg_write_enable,
                  alu_ram_sel_s,
		  reg_widx_sel1_s,
		  jp,
		  link,
		  jpr,
		  shiftv,
		  do_sign_ext
);

  input [31:0] instruction;

  output      ram_write_enable;
  output          alu_b_sel1_s;
  output          alu_b_sel2_s;
  output  [2:0]         alu_op;
  output  [2:0] is_branch_ctrl;
  output      reg_write_enable;
  output         alu_ram_sel_s;
  output       reg_widx_sel1_s;
  output                    jp;
  output                  link;
  output                   jpr;
  output                shiftv;
  output           do_sign_ext;



  wire  [5:0]        op_code;

  wire  [4:0]         Rrs;
  wire  [4:0]         Rrt;
  wire  [4:0]         Rrd;
  wire  [4:0]         Rshamt;
  wire  [5:0]         Rfunc;

  assign op_code = instruction[31:26];

  assign Rrs    = instruction[25:21];
  assign Rrt    = instruction[20:16];
  assign Rrd    = instruction[15:11];
  assign Rshamt = instruction[10:6];
  assign Rfunc  = instruction[5:0];

  wire  [4:0]         Irs;
  wire  [4:0]         Irt;
  wire [15:0]         Iaddr;

  assign Irs    = instruction[25:21];
  assign Irt    = instruction[20:16];
  assign Iaddr  = instruction[15:0];

  wire [25:0]         Jaddr;

  assign Jaddr  = instruction[25:0];

  reg    [2:0] is_branch_ctrl_tmp;
  reg            alu_b_sel1_s_tmp;
  reg    [2:0]         alu_op_tmp;
  reg        reg_write_enable_tmp;
  reg           alu_ram_sel_s_tmp;
  reg         reg_widx_sel1_s_tmp;
  reg 	                  link_tmp;
   
   









  assign  ram_write_enable = (op_code == `SW) ? 1'b1 : 1'b0;















  always @(op_code) begin
    case (op_code)
      `R:      is_branch_ctrl_tmp = 3'b110;



      `LW:     is_branch_ctrl_tmp = 3'b110;







      `SW:     is_branch_ctrl_tmp = 3'b110;



      `ADDI:   is_branch_ctrl_tmp = 3'b110;



      `ADDIU:  is_branch_ctrl_tmp = 3'b110;



      `ANDI:   is_branch_ctrl_tmp = 3'b110;
      `ORI:    is_branch_ctrl_tmp = 3'b110;
      `BEQ:    is_branch_ctrl_tmp = 3'b000;



      `BNE:    is_branch_ctrl_tmp = 3'b001;



      `BGEZ:   is_branch_ctrl_tmp = 3'b010;
      `BLEZ:   is_branch_ctrl_tmp = 3'b011;
      `BGTZ:   is_branch_ctrl_tmp = 3'b100;
      `BLTZ:   is_branch_ctrl_tmp = 3'b101;
      `BGEZAL: is_branch_ctrl_tmp = 3'b010;
      `BLTZAL: is_branch_ctrl_tmp = 3'b101;
      `XORI:   is_branch_ctrl_tmp = 3'b110;
      `SLTI:   is_branch_ctrl_tmp = 3'b110;



      `SLTIU:  is_branch_ctrl_tmp = 3'b110;



      `LUI:    is_branch_ctrl_tmp = 3'b110;
      default: is_branch_ctrl_tmp = 3'b110;
    endcase
  end

  assign  is_branch_ctrl = is_branch_ctrl_tmp;













  assign  jp = ((op_code == `J) || (op_code == `JAL)) ? 1'b1 : 1'b0;













  assign  jpr = (op_code == `R &&
                (Rfunc == 6'b001001



                  || Rfunc == 6'b001000)) ? 1'b1 : 1'b0;





  assign  shiftv = (op_code == `R &&
                (Rfunc == 6'b000000 || Rfunc == 6'b000010
                                    || Rfunc == 6'b000011)) ? 1'b1 : 1'b0;







  always @(op_code) begin
    case (op_code)
      `R:      alu_b_sel1_s_tmp = 1'b0;



      `LW:     alu_b_sel1_s_tmp = 1'b1;







      `SW:     alu_b_sel1_s_tmp = 1'b1;



      `ADDI:   alu_b_sel1_s_tmp = 1'b1;



      `ADDIU:  alu_b_sel1_s_tmp = 1'b1;



      `ANDI:   alu_b_sel1_s_tmp = 1'b1;
      `ORI:    alu_b_sel1_s_tmp = 1'b1;
      `BEQ:    alu_b_sel1_s_tmp = 1'b0;



      `BNE:    alu_b_sel1_s_tmp = 1'b0;




      `XORI:   alu_b_sel1_s_tmp = 1'b1;
      `SLTI:   alu_b_sel1_s_tmp = 1'b1;



      `SLTIU:  alu_b_sel1_s_tmp = 1'b1;



      `LUI:    alu_b_sel1_s_tmp = 1'b1;
      default: alu_b_sel1_s_tmp = 1'b0;
    endcase
  end
  assign  alu_b_sel1_s = alu_b_sel1_s_tmp;
   


  assign alu_b_sel2_s = (op_code == 6'b000001) ? 1'b1 : 1'b0;









  assign do_sign_ext = ((op_code == `ADDI)



                        || (op_code == `ADDIU)



                        || (op_code == `SW)


                        || (op_code == `LW)



                        || (op_code == `SLTI)
                        || (op_code == `BEQ)



                        || (op_code == `BNE)



                        || (op_code == `BGEZ) || (op_code == `BLEZ)
                        || (op_code == `BGTZ) || (op_code == `BLTZ)
                        || (op_code == `BGEZAL) || (op_code == `BLTZAL)) ? 1'b1 : 1'b0;













  always @(op_code) begin
    case (op_code)
      `R:      alu_op_tmp = 3'b010;



      `LW:     alu_op_tmp = 3'b000;







      `SW:     alu_op_tmp = 3'b000;



      `ADDI:   alu_op_tmp = 3'b000;



      `ADDIU:  alu_op_tmp = 3'b000;



      `ANDI:   alu_op_tmp = 3'b011;
      `ORI:    alu_op_tmp = 3'b100;
      `XORI:   alu_op_tmp = 3'b101;
      `SLTI:   alu_op_tmp = 3'b110;



      `SLTIU:  alu_op_tmp = 3'b111;



      `LUI:    alu_op_tmp = 3'b001;
      default: alu_op_tmp = 3'b000;
    endcase
  end
  assign  alu_op = alu_op_tmp;







  always @(op_code) begin
    case (op_code)
      `R: begin
            if (Rfunc == 6'b001000) begin



              reg_write_enable_tmp = 1'b0;



            end else begin
              reg_write_enable_tmp = 1'b1;
            end
          end




      `LW:     reg_write_enable_tmp = 1'b1;







      `SW:     reg_write_enable_tmp = 1'b0;



      `ADDI:   reg_write_enable_tmp = 1'b1;



      `ADDIU:  reg_write_enable_tmp = 1'b1;



      `ANDI:   reg_write_enable_tmp = 1'b1;
      `ORI:    reg_write_enable_tmp = 1'b1;
      `BEQ:    reg_write_enable_tmp = 1'b0;



      `BNE:    reg_write_enable_tmp = 1'b0;







      `J:      reg_write_enable_tmp = 1'b0;







      `JAL:    reg_write_enable_tmp = 1'b1;



      `XORI:   reg_write_enable_tmp = 1'b1;
      `SLTI:   reg_write_enable_tmp = 1'b1;



      `SLTIU:  reg_write_enable_tmp = 1'b1;



      `LUI:    reg_write_enable_tmp = 1'b1;
      default: reg_write_enable_tmp = 1'b0;
    endcase
  end
  assign  reg_write_enable = reg_write_enable_tmp;







  always @(op_code) begin
    case (op_code)
      `R:      alu_ram_sel_s_tmp = 1'b0;



      `LW:     alu_ram_sel_s_tmp = 1'b1;




      `ADDI:   alu_ram_sel_s_tmp = 1'b0;



      `ADDIU:  alu_ram_sel_s_tmp = 1'b0;



      `ANDI:   alu_ram_sel_s_tmp = 1'b0;
      `ORI:    alu_ram_sel_s_tmp = 1'b0;
      `BEQ:    alu_ram_sel_s_tmp = 1'b0;
      `XORI:   alu_ram_sel_s_tmp = 1'b0;
      `SLTI:   alu_ram_sel_s_tmp = 1'b0;



      `SLTIU:  alu_ram_sel_s_tmp = 1'b0;



      `LUI:    alu_ram_sel_s_tmp = 1'b0;
      default: alu_ram_sel_s_tmp = 1'b0;
    endcase
  end
  assign  alu_ram_sel_s = alu_ram_sel_s_tmp;







  always @(op_code) begin
    case (op_code)
      `R:      reg_widx_sel1_s_tmp = 1'b1;



      `LW:     reg_widx_sel1_s_tmp = 1'b0;




      `ADDI:   reg_widx_sel1_s_tmp = 1'b0;



      `ADDIU:  reg_widx_sel1_s_tmp = 1'b0;



      `ANDI:   reg_widx_sel1_s_tmp = 1'b0;
      `ORI:    reg_widx_sel1_s_tmp = 1'b0;
      `BEQ:    reg_widx_sel1_s_tmp = 1'b0;
      `XORI:   reg_widx_sel1_s_tmp = 1'b0;
      `SLTI:   reg_widx_sel1_s_tmp = 1'b0;



      `SLTIU:  reg_widx_sel1_s_tmp = 1'b0;



      `LUI:    reg_widx_sel1_s_tmp = 1'b0;
      default: reg_widx_sel1_s_tmp = 1'b0;
    endcase
  end
  assign  reg_widx_sel1_s = reg_widx_sel1_s_tmp;







  always @(op_code) begin
    case (op_code)
      `R: begin
            if (Rfunc == 6'b001001) begin
              link_tmp = 1'b1;
            end else begin
              link_tmp = 1'b0;
            end
          end



      `LW:     link_tmp = 1'b0;




      `ADDI:   link_tmp = 1'b0;



      `ADDIU:  link_tmp = 1'b0;



      `ANDI:   link_tmp = 1'b0;
      `ORI:    link_tmp = 1'b0;
      `BEQ:    link_tmp = 1'b0;
      `BGEZ:   link_tmp = 1'b0;
      `BLEZ:   link_tmp = 1'b0;
      `BGTZ:   link_tmp = 1'b0;
      `BLTZ:   link_tmp = 1'b0;
      `BGEZAL: link_tmp = 1'b1;
      `BLTZAL: link_tmp = 1'b1;




      `JAL:    link_tmp = 1'b1;



      `XORI:   link_tmp = 1'b0;
      `SLTI:   link_tmp = 1'b0;



      `SLTIU:  link_tmp = 1'b0;



      `LUI:    link_tmp = 1'b0;
      default: link_tmp = 1'b0;
    endcase
  end
  assign  link = link_tmp;

endmodule