data/full_repos/permissive/120851390/pod-dac-ad9116/hdl/syzygy-dds.v
 line:64 column:2: Illegal character '\x00'
data/verilator_xmls/aa841d27-68f5-4f83-8e1c-0bbe12ed1cfb.xml
module syzygy_dds (
	input  wire        clk,
	input  wire        reset,

	output wire [11:0] data
	);

reg [11:0] counter;
reg        count_up;
	
assign data = counter;

always @(posedge clk) begin
	if (reset == 1'b1) begin
		count_up <= 1'b1;
		counter <= 12'h0;
	end else begin
		if (count_up == 1'b1) begin
			counter <= counter + 12'd100;
		end else begin
			counter <= counter - 12'd100;
		end

		if (counter <= 12'd500) begin
			count_up <= 1'b1;
		end else if (counter >= 12'd3500) begin
			count_up <= 1'b0;
		end
	end
end

endmodule
module syzygy_dds (
	input  wire        clk,
	input  wire        reset,

	output wire [11:0] data
	);


reg [11:0] counter;
reg        count_up;
	
assign data = counter;

always @(posedge clk) begin
	if (reset == 1'b1) begin
		count_up <= 1'b1;
		counter <= 12'h0;
	end else begin
		if (count_up == 1'b1) begin
			counter <= counter + 12'd100;
		end else begin
			counter <= counter - 12'd100;
		end

		if (counter <= 12'd500) begin
			count_up <= 1'b1;
		end else if (counter >= 12'd3500) begin
			count_up <= 1'b0;
		end
	end
end

endmodule