data/full_repos/permissive/171756809/random.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/171756809/random.v:86: Multiple top level modules\n                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                   : ... Top module \'randomized_lfsr\'\nmodule randomized_lfsr(input wire clk, input wire rst, output wire bit_ready, output wire word_ready, output wire [WIDTH-1:0] out, output wire metastable);\n       ^~~~~~~~~~~~~~~\n                                                                   : ... Top module \'randomized_lfsr_weak\'\nmodule randomized_lfsr_weak(input wire clk, input wire rst, output wire [WIDTH-1:0] out, output wire metastable);\n       ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171756809/random.v:93: Cannot find file containing module: \'metastable_oscillator\'\n metastable_oscillator osci(metastable);\n ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/171756809,data/full_repos/permissive/171756809/metastable_oscillator\n             data/full_repos/permissive/171756809,data/full_repos/permissive/171756809/metastable_oscillator.v\n             data/full_repos/permissive/171756809,data/full_repos/permissive/171756809/metastable_oscillator.sv\n             metastable_oscillator\n             metastable_oscillator.v\n             metastable_oscillator.sv\n             obj_dir/metastable_oscillator\n             obj_dir/metastable_oscillator.v\n             obj_dir/metastable_oscillator.sv\n%Error: data/full_repos/permissive/171756809/random.v:94: Cannot find file containing module: \'lfsr\'\n lfsr #(.WIDTH(WIDTH), .INIT_VALUE(INIT_VALUE), .FEEDBACK(FEEDBACK)) shiftreg(clk, metastable, out, rst);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/171756809/random.v:57: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 5 bits.\n                                                                : ... In instance randomized_lfsr\n reg [$clog2(WIDTH)-1:0] bits_remaining = WIDTH-1;\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/171756809/random.v:62: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 5 bits.\n                                                                : ... In instance randomized_lfsr\n   bits_remaining <= WIDTH-1;\n                  ^~\n%Error: data/full_repos/permissive/171756809/random.v:74: Cannot find file containing module: \'metastable_oscillator_depth2\'\n metastable_oscillator_depth2 osci(metastable);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171756809/random.v:75: Cannot find file containing module: \'binary_debias\'\n binary_debias debias(clk, metastable, bit_ready, random);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/171756809/random.v:76: Cannot find file containing module: \'lfsr\'\n lfsr #(.WIDTH(WIDTH), .INIT_VALUE(INIT_VALUE), .FEEDBACK(FEEDBACK)) shiftreg(bit_ready, random, out, rst);\n ^~~~\n%Error: Exiting due to 5 error(s), 3 warning(s)\n'
module randomized_lfsr(input wire clk, input wire rst, output wire bit_ready, output wire word_ready, output wire [WIDTH-1:0] out, output wire metastable);

	parameter WIDTH = 'd16;
	parameter INIT_VALUE = 16'b1010_1100_1110_0001;
	parameter FEEDBACK = 16'b0000_0000_0010_1101;

	reg [$clog2(WIDTH)-1:0] bits_remaining = WIDTH-1;
	reg previous_bit_ready = 0;

	always @ (posedge clk) begin
		if(rst || word_ready) begin
			bits_remaining <= WIDTH-1;
		end else begin
			if(!previous_bit_ready && bit_ready) begin
				bits_remaining <= bits_remaining - 1;
			end
		end
		previous_bit_ready <= bit_ready;
	end

	assign word_ready = (bits_remaining == 0);

	wire random;
	metastable_oscillator_depth2 osci(metastable);
	binary_debias debias(clk, metastable, bit_ready, random);
	lfsr #(.WIDTH(WIDTH), .INIT_VALUE(INIT_VALUE), .FEEDBACK(FEEDBACK)) shiftreg(bit_ready, random, out, rst);

endmodule
module randomized_lfsr(input wire clk, input wire rst, output wire bit_ready, output wire word_ready, output wire [WIDTH-1:0] out, output wire metastable);


	parameter WIDTH = 'd16;
	parameter INIT_VALUE = 16'b1010_1100_1110_0001;
	parameter FEEDBACK = 16'b0000_0000_0010_1101;

	reg [$clog2(WIDTH)-1:0] bits_remaining = WIDTH-1;
	reg previous_bit_ready = 0;

	always @ (posedge clk) begin
		if(rst || word_ready) begin
			bits_remaining <= WIDTH-1;
		end else begin
			if(!previous_bit_ready && bit_ready) begin
				bits_remaining <= bits_remaining - 1;
			end
		end
		previous_bit_ready <= bit_ready;
	end

	assign word_ready = (bits_remaining == 0);

	wire random;
	metastable_oscillator_depth2 osci(metastable);
	binary_debias debias(clk, metastable, bit_ready, random);
	lfsr #(.WIDTH(WIDTH), .INIT_VALUE(INIT_VALUE), .FEEDBACK(FEEDBACK)) shiftreg(bit_ready, random, out, rst);

endmodule