data/full_repos/permissive/111393021/test/fifo_reader.v
 line:25: before: "="
1: b"%Error: data/full_repos/permissive/111393021/test/fifo_reader.v:39: Unsupported or unknown PLI call: $dist_uniform\n      randval = $dist_uniform(seed, 0, 1000) / 1000.0;\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111393021/test/fifo_reader.v:52: syntax error, unexpected '@'\n     @(posedge clk);\n     ^\n%Error: data/full_repos/permissive/111393021/test/fifo_reader.v:63: syntax error, unexpected '@'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module fifo_reader
  #(
    parameter WIDTH = 0,
    parameter MAX_BLOCK_SIZE = 1024)
   (
    input 	      clk,
    input [WIDTH-1:0] din,
    output reg	      rden = 1'b0,
    input 	      empty);

   real 	       rate = 0.5;
   integer 	       seed = 0;

   time 	       timeout = 0;
   reg 		       err_timeout = 0;

   reg 		       valid = 1'b0;

   real 	       randval;
   always @(posedge clk) begin
      valid <= rden & !empty;
      randval = $dist_uniform(seed, 0, 1000) / 1000.0;
      rden <= (randval <= rate) & !empty;
   end

   task read_word;
      output [WIDTH-1:0] data_o;

      reg 		 rd;
      time 		 t0;

      begin
	 t0 = $time;
	 while(!valid & !err_timeout) begin
	    @(posedge clk);

	    if(timeout > 0)
	      err_timeout = ($time-t0) > timeout;
	 end
	 if(err_timeout) begin
	    $display("%0d : Timeout in FIFO reader", $time);
            $finish;
         end
	 data_o = din;
	 err_timeout = 1'b0;
	 @(posedge clk);
      end
   endtask

endmodule
module fifo_reader
  #(
    parameter WIDTH = 0,
    parameter MAX_BLOCK_SIZE = 1024)
   (
    input 	      clk,
    input [WIDTH-1:0] din,
    output reg	      rden = 1'b0,
    input 	      empty);


   real 	       rate = 0.5;
   integer 	       seed = 0;

   time 	       timeout = 0;
   reg 		       err_timeout = 0;

   reg 		       valid = 1'b0;

   real 	       randval;
   always @(posedge clk) begin
      valid <= rden & !empty;
      randval = $dist_uniform(seed, 0, 1000) / 1000.0;
      rden <= (randval <= rate) & !empty;
   end

   task read_word;
      output [WIDTH-1:0] data_o;

      reg 		 rd;
      time 		 t0;

      begin
	 t0 = $time;
	 while(!valid & !err_timeout) begin
	    @(posedge clk);

	    if(timeout > 0)
	      err_timeout = ($time-t0) > timeout;
	 end
	 if(err_timeout) begin
	    $display("%0d : Timeout in FIFO reader", $time);
            $finish;
         end
	 data_o = din;
	 err_timeout = 1'b0;
	 @(posedge clk);
      end
   endtask

endmodule