data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v
'utf-8' codec can't decode byte 0xb3 in position 133: invalid start byte
1: b'%Warning-STMTDLY: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:52: Unsupported: Ignoring delay on this delayed statement.\n            #20 KEY[1] <= ~KEY[1];    \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:54: Unsupported: Ignoring delay on this delayed statement.\n            #300 KEY[0] <= ~KEY[0];    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:55: Unsupported: Ignoring delay on this delayed statement.\n            #300 KEY[0] <= ~KEY[0];    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:56: Unsupported: Ignoring delay on this delayed statement.\n            #300 KEY[0] <= ~KEY[0];    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:57: Unsupported: Ignoring delay on this delayed statement.\n            #300 KEY[0] <= ~KEY[0];    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:58: Unsupported: Ignoring delay on this delayed statement.\n            #200 KEY[1] <= ~KEY[1];    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:59: Unsupported: Ignoring delay on this delayed statement.\n            #300 KEY[0] <= ~KEY[0];    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:64: Unsupported: Ignoring delay on this delayed statement.\n            #10 CLOCK_50 <= ~CLOCK_50;  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #10 KEY[0] <= ~KEY[0];   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #10 KEY[1] <= ~KEY[1];   \n        ^\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:14: Can\'t find definition of \'CLOCK_100\' in dotted variable: \'uut.CLOCK_100\'\n    assign CLOCK_100 = uut.CLOCK_100;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:15: Can\'t find definition of \'CLOCK_SW\' in dotted variable: \'uut.CLOCK_SW\'\n    assign CLOCK_SW = uut.CLOCK_SW;\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:17: Can\'t find definition of \'HEX0\' in dotted variable: \'uut.HEX0\'\n    assign HEX0 = uut.HEX0;\n                      ^~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:18: Can\'t find definition of \'HEX1\' in dotted variable: \'uut.HEX1\'\n    assign HEX1 = uut.HEX1;\n                      ^~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:19: Can\'t find definition of \'HEX2\' in dotted variable: \'uut.HEX2\'\n    assign HEX2 = uut.HEX2;\n                      ^~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:20: Can\'t find definition of \'HEX3\' in dotted variable: \'uut.HEX3\'\n    assign HEX3 = uut.HEX3;\n                      ^~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:21: Can\'t find definition of \'HEX4\' in dotted variable: \'uut.HEX4\'\n    assign HEX4 = uut.HEX4;\n                      ^~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:22: Can\'t find definition of \'HEX5\' in dotted variable: \'uut.HEX5\'\n    assign HEX5 = uut.HEX5;\n                      ^~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:27: Can\'t find definition of \'ms_clock1\' in dotted scope/variable: \'uut.ms_clock1\'\n    assign count = uut.ms_clock1.count;\n                       ^~~~~~~~~\n        ... Known scopes under \'uut\': <no cells found>\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:33: Can\'t find definition of \'ms_clock_switched1\' in dotted scope/variable: \'uut.ms_clock_switched1\'\n    assign state = uut.ms_clock_switched1.state;\n                       ^~~~~~~~~~~~~~~~~~\n        ... Known scopes under \'uut\': <no cells found>\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:40: Can\'t find definition of \'hundredths_bcd\' in dotted variable: \'uut.hundredths_bcd\'\n    assign hundredths_bcd = uut.hundredths_bcd;\n                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:41: Can\'t find definition of \'tenths_bcd\' in dotted variable: \'uut.tenths_bcd\'\n    assign tenths_bcd = uut.tenths_bcd;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:42: Can\'t find definition of \'ones_bcd\' in dotted variable: \'uut.ones_bcd\'\n    assign ones_bcd = uut.ones_bcd;\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:43: Can\'t find definition of \'tens_bcd\' in dotted variable: \'uut.tens_bcd\'\n    assign tens_bcd = uut.tens_bcd;\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:44: Can\'t find definition of \'mins_bcd\' in dotted variable: \'uut.mins_bcd\'\n    assign mins_bcd = uut.mins_bcd;\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/189714993/Stoper.srcs/sim_1/new/test_bench.v:45: Can\'t find definition of \'tmins_bcd\' in dotted variable: \'uut.tmins_bcd\'\n    assign tmins_bcd = uut.tmins_bcd;\n                           ^~~~~~~~~\n%Error: Exiting due to 16 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_bench();

    reg CLOCK_50;
    reg [1:0] KEY;

    
    localparam speed_up = 1;

    stopwatch #(speed_up) uut(.CLOCK_50(CLOCK_50), .KEY(KEY));

    wire CLOCK_SW, CLOCK_100;
    assign CLOCK_100 = uut.CLOCK_100;
    assign CLOCK_SW = uut.CLOCK_SW;
    wire [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
    assign HEX0 = uut.HEX0;
    assign HEX1 = uut.HEX1;
    assign HEX2 = uut.HEX2;
    assign HEX3 = uut.HEX3;
    assign HEX4 = uut.HEX4;
    assign HEX5 = uut.HEX5;
    
    

    wire [0:17] count;
    assign count = uut.ms_clock1.count;
    



    wire state;
    assign state = uut.ms_clock_switched1.state;
    




    wire [3:0] hundredths_bcd, tenths_bcd, ones_bcd, tens_bcd, mins_bcd, tmins_bcd;
    assign hundredths_bcd = uut.hundredths_bcd;
    assign tenths_bcd = uut.tenths_bcd;
    assign ones_bcd = uut.ones_bcd;
    assign tens_bcd = uut.tens_bcd;
    assign mins_bcd = uut.mins_bcd;
    assign tmins_bcd = uut.tmins_bcd;
    
    initial
        begin
            CLOCK_50 = 1'b0;
            KEY = 2'b11;
            
            #20 KEY[1] <= ~KEY[1];

            #300 KEY[0] <= ~KEY[0];
            #300 KEY[0] <= ~KEY[0];
            #300 KEY[0] <= ~KEY[0];
            #300 KEY[0] <= ~KEY[0];
            #200 KEY[1] <= ~KEY[1];
            #300 KEY[0] <= ~KEY[0];
        end
    
    always
        begin
            #10 CLOCK_50 <= ~CLOCK_50;
        end
    always @(negedge KEY[0])
        #10 KEY[0] <= ~KEY[0];
    always @(negedge KEY[1])
        #10 KEY[1] <= ~KEY[1];
endmodule
module test_bench();


    reg CLOCK_50;
    reg [1:0] KEY;

    
    localparam speed_up = 1;

    stopwatch #(speed_up) uut(.CLOCK_50(CLOCK_50), .KEY(KEY));

    wire CLOCK_SW, CLOCK_100;
    assign CLOCK_100 = uut.CLOCK_100;
    assign CLOCK_SW = uut.CLOCK_SW;
    wire [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
    assign HEX0 = uut.HEX0;
    assign HEX1 = uut.HEX1;
    assign HEX2 = uut.HEX2;
    assign HEX3 = uut.HEX3;
    assign HEX4 = uut.HEX4;
    assign HEX5 = uut.HEX5;
    
    

    wire [0:17] count;
    assign count = uut.ms_clock1.count;
    



    wire state;
    assign state = uut.ms_clock_switched1.state;
    




    wire [3:0] hundredths_bcd, tenths_bcd, ones_bcd, tens_bcd, mins_bcd, tmins_bcd;
    assign hundredths_bcd = uut.hundredths_bcd;
    assign tenths_bcd = uut.tenths_bcd;
    assign ones_bcd = uut.ones_bcd;
    assign tens_bcd = uut.tens_bcd;
    assign mins_bcd = uut.mins_bcd;
    assign tmins_bcd = uut.tmins_bcd;
    
    initial
        begin
            CLOCK_50 = 1'b0;
            KEY = 2'b11;
            
            #20 KEY[1] <= ~KEY[1];

            #300 KEY[0] <= ~KEY[0];
            #300 KEY[0] <= ~KEY[0];
            #300 KEY[0] <= ~KEY[0];
            #300 KEY[0] <= ~KEY[0];
            #200 KEY[1] <= ~KEY[1];
            #300 KEY[0] <= ~KEY[0];
        end
    
    always
        begin
            #10 CLOCK_50 <= ~CLOCK_50;
        end
    always @(negedge KEY[0])
        #10 KEY[0] <= ~KEY[0];
    always @(negedge KEY[1])
        #10 KEY[1] <= ~KEY[1];
endmodule