data/full_repos/permissive/154371523/Code/rtl/xps2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/154371523/Code/rtl/xps2.v:42: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance xps2\n  downcounter <= 1\'b0;\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154371523/Code/rtl/xps2.v:55: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                       : ... In instance xps2\n   count <=1\'b0;\n         ^~\n%Error: Exiting due to 2 warning(s)\n'
module xps2 (
			input			clk,
			input			sel,
			input			rst,
			input			ps2_clk,
			input			ps2_data,
			output reg[8:0]	data_out
	      );

reg [9:0] scan_code = 10'b0;

reg [3:0] count = 4'b0;
reg previous_state;			
reg trigger;
reg trig_arr;
reg [7:0] downcounter= 8'b0;	
reg previous_sel;
reg  key_released;

always @(posedge clk) begin	
					
	if (rst) begin
		data_out <= 9'b0;
		scan_code = 10'b0;
		count <= 4'b0;
		trig_arr <= 1'b0;
		trigger <= 1'b0;
		downcounter <= 8'b0;
		previous_state <= 1'b0;
		previous_sel <=1'b0;
	end
	

	if (downcounter< 249) begin			 
		downcounter <= downcounter + 1;
		trigger <= 1'b0;
	end
	else begin
		downcounter <= 1'b0;
		trigger <= 1'b1;
	end
		
	if (trigger) begin						
		if (ps2_clk != previous_state) begin			
			if (!ps2_clk) begin				
				count <= count + 1;
				scan_code[9:0] = {ps2_data, scan_code[9:1]};
			end
		end
		else if (count == 11) begin
			trig_arr <= 1'b1;	
			count <=1'b0;
		end	
		else						
			trig_arr <= 1'b0;
			
		previous_state <= ps2_clk;					

	end
	
	if (trigger) begin					
		if (trig_arr) begin
			if (scan_code [7:0] == 8'hF0) key_released <= 1'b1;
			if (key_released == 1 && scan_code[7:0]!= 8'hF0) data_out[8] <= 1'b1;
			data_out[7:0] <= scan_code[7:0];
		end				
	end
	

	if (sel == 1 && previous_sel ==0 && data_out[8]==1) begin
		data_out[8] <= 1'b0;
		key_released <= 0;
	end
	previous_sel <= sel;
			
end
	
	
endmodule
module xps2 (
			input			clk,
			input			sel,
			input			rst,
			input			ps2_clk,
			input			ps2_data,
			output reg[8:0]	data_out
	      );


reg [9:0] scan_code = 10'b0;

reg [3:0] count = 4'b0;
reg previous_state;			
reg trigger;
reg trig_arr;
reg [7:0] downcounter= 8'b0;	
reg previous_sel;
reg  key_released;

always @(posedge clk) begin	
					
	if (rst) begin
		data_out <= 9'b0;
		scan_code = 10'b0;
		count <= 4'b0;
		trig_arr <= 1'b0;
		trigger <= 1'b0;
		downcounter <= 8'b0;
		previous_state <= 1'b0;
		previous_sel <=1'b0;
	end
	

	if (downcounter< 249) begin			 
		downcounter <= downcounter + 1;
		trigger <= 1'b0;
	end
	else begin
		downcounter <= 1'b0;
		trigger <= 1'b1;
	end
		
	if (trigger) begin						
		if (ps2_clk != previous_state) begin			
			if (!ps2_clk) begin				
				count <= count + 1;
				scan_code[9:0] = {ps2_data, scan_code[9:1]};
			end
		end
		else if (count == 11) begin
			trig_arr <= 1'b1;	
			count <=1'b0;
		end	
		else						
			trig_arr <= 1'b0;
			
		previous_state <= ps2_clk;					

	end
	
	if (trigger) begin					
		if (trig_arr) begin
			if (scan_code [7:0] == 8'hF0) key_released <= 1'b1;
			if (key_released == 1 && scan_code[7:0]!= 8'hF0) data_out[8] <= 1'b1;
			data_out[7:0] <= scan_code[7:0];
		end				
	end
	

	if (sel == 1 && previous_sel ==0 && data_out[8]==1) begin
		data_out[8] <= 1'b0;
		key_released <= 0;
	end
	previous_sel <= sel;
			
end
	
	
endmodule