data/full_repos/permissive/197102055/src/sdramc/sdram_init.v
 line:31: before: "="
data/verilator_xmls/05954cd2-fdf9-4675-b300-121d8a8b51fa.xml
module sdram_init (

    input       sdram_clk,
    input       sdram_rst_,




    output  reg PAA = 0,
    output  reg SET_MODE
);

parameter
    INIT_CNT        = 16'h4000,
    INIT_HALF_CNT   = INIT_CNT >> 1;
    



reg     [15:0]  init_counter;
wire    init_counter_done;

assign init_counter_done = (init_counter == INIT_CNT);

always @(posedge sdram_clk) begin
    if (!sdram_rst_)
        init_counter <= 'b0;
    else if (!init_counter_done)
        init_counter <= init_counter + 1'b1;
end








        


always @(posedge sdram_clk) begin
        PAA <= init_counter_done;
end        


always @(posedge sdram_clk) begin
        SET_MODE <= 1'b1;
end

        
endmodule
module sdram_init (

    input       sdram_clk,
    input       sdram_rst_,




    output  reg PAA = 0,
    output  reg SET_MODE
);


parameter
    INIT_CNT        = 16'h4000,
    INIT_HALF_CNT   = INIT_CNT >> 1;
    



reg     [15:0]  init_counter;
wire    init_counter_done;

assign init_counter_done = (init_counter == INIT_CNT);

always @(posedge sdram_clk) begin
    if (!sdram_rst_)
        init_counter <= 'b0;
    else if (!init_counter_done)
        init_counter <= init_counter + 1'b1;
end








        


always @(posedge sdram_clk) begin
        PAA <= init_counter_done;
end        


always @(posedge sdram_clk) begin
        SET_MODE <= 1'b1;
end

        
endmodule