data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v:17: Cannot find include file: spio_hss_multiplexer_common.h\n`include "spio_hss_multiplexer_common.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h.v\n             data/full_repos/permissive/19591557/modules/hss_multiplexer,data/full_repos/permissive/19591557/spio_hss_multiplexer_common.h.sv\n             spio_hss_multiplexer_common.h\n             spio_hss_multiplexer_common.h.v\n             spio_hss_multiplexer_common.h.sv\n             obj_dir/spio_hss_multiplexer_common.h\n             obj_dir/spio_hss_multiplexer_common.h.v\n             obj_dir/spio_hss_multiplexer_common.h.sv\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v:32: Define or directive not defined: \'`IDLE_BITS\'\n                                        , input wire [`IDLE_BITS - 1:0] REG_IDSO_IN\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v:114: Define or directive not defined: \'`KCH_CLKC\'\n    TXDATA_OUT    <= {4{`KCH_CLKC}};\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v:114: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    TXDATA_OUT    <= {4{`KCH_CLKC}};\n                                 ^\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v:119: Define or directive not defined: \'`KCH_COMMA\'\n    TXDATA_OUT    <= { `KCH_COMMA\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v:120: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                     , `KCH_HANDSHAKE\n                     ^\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v:120: Define or directive not defined: \'`KCH_HANDSHAKE\'\n                     , `KCH_HANDSHAKE\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v:122: Define or directive not defined: \'`PROTOCOL_VERSION\'\n                     , `PROTOCOL_VERSION\n                       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v:133: Define or directive not defined: \'`KCH_IDLE\'\n    TXDATA_OUT    <= {`KCH_IDLE, idle_data};\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v:133: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    TXDATA_OUT    <= {`KCH_IDLE, idle_data};\n                               ^\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v:134: Define or directive not defined: \'`IDLE_KBITS\'\n    TXCHARISK_OUT <= `IDLE_KBITS;\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/19591557/modules/hss_multiplexer/spio_hss_multiplexer_tx_control.v:134: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    TXCHARISK_OUT <= `IDLE_KBITS;\n                                ^\n%Error: Exiting due to 12 error(s)\n'
module spio_hss_multiplexer_tx_control #(

                                          parameter CLOCK_CORRECTION_INTERVAL = 1000

                                        , parameter CLOCK_CORRECTION_INTERVAL_BITS = 10
                                        )
                                        ( input wire  CLK_IN
                                        , input wire  RESET_IN
                                        

                                        , input wire  SCRMBL_IDL_DAT


                                        , input wire [`IDLE_BITS - 1:0] REG_IDSO_IN


                                        , input wire HANDSHAKE_COMPLETE_IN

                                        , input wire HANDSHAKE_PHASE_IN
                                        


                                        ,   output reg [31:0] TXDATA_OUT
                                        ,   output reg  [3:0] TXCHARISK_OUT
                                        


                                        ,   input wire [31:0] TXDATA_IN
                                        ,   input wire  [3:0] TXCHARISK_IN


                                        ,   input wire TXVLD_IN
                                        ,   output reg TXRDY_OUT
                                        );




wire [15:0] lfsr_out;
wire        send_lfsr;

spio_hss_multiplexer_lfsr lfsr_0
(
  .clk      (CLK_IN),
  .rst      (RESET_IN),
  .next     (send_lfsr),
  .data_out (lfsr_out)
);




reg [CLOCK_CORRECTION_INTERVAL_BITS-1:0] clock_correction_counter_i;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		clock_correction_counter_i <= 0;
	else
		if (clock_correction_counter_i < CLOCK_CORRECTION_INTERVAL)
			clock_correction_counter_i <= clock_correction_counter_i + 1;
		else
			clock_correction_counter_i <= 0;

wire clock_correction_sequence_due_i = clock_correction_counter_i == 0;




reg send_clock_correction_sequence_i;
reg send_handshake_i;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN) send_handshake_i <= 1'b1;
	else          send_handshake_i <= !HANDSHAKE_COMPLETE_IN;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN) send_clock_correction_sequence_i <= 1'b0;
	else          send_clock_correction_sequence_i <= clock_correction_sequence_due_i;



assign send_lfsr = HANDSHAKE_COMPLETE_IN
                 && !clock_correction_sequence_due_i
                 && !TXVLD_IN
                 && SCRMBL_IDL_DAT
                 ;
wire [15:0] idle_data = send_lfsr ? lfsr_out : REG_IDSO_IN;


always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			TXDATA_OUT    <= 32'h0;
			TXCHARISK_OUT <=  4'h0;
		end
	else
		if (send_clock_correction_sequence_i)
			begin
				TXDATA_OUT    <= {4{`KCH_CLKC}};
				TXCHARISK_OUT <=  4'b1111;
			end
		else if (send_handshake_i)
			begin
				TXDATA_OUT    <= { `KCH_COMMA
				                 , `KCH_HANDSHAKE
				                 , 7'b000000, HANDSHAKE_PHASE_IN
				                 , `PROTOCOL_VERSION
				                 };
				TXCHARISK_OUT <=  4'b1100;
			end
		else if (TXVLD_IN)
			begin
				TXDATA_OUT    <= TXDATA_IN;
				TXCHARISK_OUT <= TXCHARISK_IN;
			end
		else
			begin
				TXDATA_OUT    <= {`KCH_IDLE, idle_data};
				TXCHARISK_OUT <= `IDLE_KBITS;
			end






always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		TXRDY_OUT <= 1'b0;
	else
		TXRDY_OUT <= !clock_correction_sequence_due_i && HANDSHAKE_COMPLETE_IN;

endmodule
module spio_hss_multiplexer_tx_control #(

                                          parameter CLOCK_CORRECTION_INTERVAL = 1000

                                        , parameter CLOCK_CORRECTION_INTERVAL_BITS = 10
                                        )
                                        ( input wire  CLK_IN
                                        , input wire  RESET_IN
                                        

                                        , input wire  SCRMBL_IDL_DAT


                                        , input wire [`IDLE_BITS - 1:0] REG_IDSO_IN


                                        , input wire HANDSHAKE_COMPLETE_IN

                                        , input wire HANDSHAKE_PHASE_IN
                                        


                                        ,   output reg [31:0] TXDATA_OUT
                                        ,   output reg  [3:0] TXCHARISK_OUT
                                        


                                        ,   input wire [31:0] TXDATA_IN
                                        ,   input wire  [3:0] TXCHARISK_IN


                                        ,   input wire TXVLD_IN
                                        ,   output reg TXRDY_OUT
                                        );





wire [15:0] lfsr_out;
wire        send_lfsr;

spio_hss_multiplexer_lfsr lfsr_0
(
  .clk      (CLK_IN),
  .rst      (RESET_IN),
  .next     (send_lfsr),
  .data_out (lfsr_out)
);




reg [CLOCK_CORRECTION_INTERVAL_BITS-1:0] clock_correction_counter_i;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		clock_correction_counter_i <= 0;
	else
		if (clock_correction_counter_i < CLOCK_CORRECTION_INTERVAL)
			clock_correction_counter_i <= clock_correction_counter_i + 1;
		else
			clock_correction_counter_i <= 0;

wire clock_correction_sequence_due_i = clock_correction_counter_i == 0;




reg send_clock_correction_sequence_i;
reg send_handshake_i;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN) send_handshake_i <= 1'b1;
	else          send_handshake_i <= !HANDSHAKE_COMPLETE_IN;
always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN) send_clock_correction_sequence_i <= 1'b0;
	else          send_clock_correction_sequence_i <= clock_correction_sequence_due_i;



assign send_lfsr = HANDSHAKE_COMPLETE_IN
                 && !clock_correction_sequence_due_i
                 && !TXVLD_IN
                 && SCRMBL_IDL_DAT
                 ;
wire [15:0] idle_data = send_lfsr ? lfsr_out : REG_IDSO_IN;


always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		begin
			TXDATA_OUT    <= 32'h0;
			TXCHARISK_OUT <=  4'h0;
		end
	else
		if (send_clock_correction_sequence_i)
			begin
				TXDATA_OUT    <= {4{`KCH_CLKC}};
				TXCHARISK_OUT <=  4'b1111;
			end
		else if (send_handshake_i)
			begin
				TXDATA_OUT    <= { `KCH_COMMA
				                 , `KCH_HANDSHAKE
				                 , 7'b000000, HANDSHAKE_PHASE_IN
				                 , `PROTOCOL_VERSION
				                 };
				TXCHARISK_OUT <=  4'b1100;
			end
		else if (TXVLD_IN)
			begin
				TXDATA_OUT    <= TXDATA_IN;
				TXCHARISK_OUT <= TXCHARISK_IN;
			end
		else
			begin
				TXDATA_OUT    <= {`KCH_IDLE, idle_data};
				TXCHARISK_OUT <= `IDLE_KBITS;
			end






always @ (posedge CLK_IN, posedge RESET_IN)
	if (RESET_IN)
		TXRDY_OUT <= 1'b0;
	else
		TXRDY_OUT <= !clock_correction_sequence_due_i && HANDSHAKE_COMPLETE_IN;

endmodule