data/full_repos/permissive/129155059/04-struct_register/library.v
 line:27: before: ":"
1: b'%Error: data/full_repos/permissive/129155059/04-struct_register/library.v:5: Cannot find include file: definitions.v\n`include "definitions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/04-struct_register,data/full_repos/permissive/129155059/definitions.v\n             data/full_repos/permissive/129155059/04-struct_register,data/full_repos/permissive/129155059/definitions.v.v\n             data/full_repos/permissive/129155059/04-struct_register,data/full_repos/permissive/129155059/definitions.v.sv\n             definitions.v\n             definitions.v.v\n             definitions.v.sv\n             obj_dir/definitions.v\n             obj_dir/definitions.v.v\n             obj_dir/definitions.v.sv\n%Error: data/full_repos/permissive/129155059/04-struct_register/library.v:158: Define or directive not defined: \'`Ndir\'\n   input [`Ndir:0] dir;\n          ^~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/library.v:158: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   input [`Ndir:0] dir;\n               ^\n%Error: data/full_repos/permissive/129155059/04-struct_register/library.v:161: Define or directive not defined: \'`NumPwrCntr\'\n   reg [31:0]      PwrCntr [`NumPwrCntr:0];\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/04-struct_register/library.v:161: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   reg [31:0]      PwrCntr [`NumPwrCntr:0];\n                                       ^\n%Error: Exiting due to 5 error(s)\n'
module mid_mux( output oD,
                input Qleft,
                input Qright,
                input D,
                input DIR,
                input MODO1
                );

  parameter PwrC = 0;

  wire mDIR_o__mMODO1_A;

  mux_2a1 #(PwrC) mDIR( mDIR_o__mMODO1_A,
                        Qright,
                        Qleft,
                        DIR
                        );

  mux_2a1 #(PwrC) mMODO1( oD,
                          mDIR_o__mMODO1_A,
                          D,
                          MODO1
                          );

  always @(posedge oD or negedge oD) begin

    letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;

  end

endmodule
module mid_mux( output oD,
                input Qleft,
                input Qright,
                input D,
                input DIR,
                input MODO1
                );


  parameter PwrC = 0;

  wire mDIR_o__mMODO1_A;

  mux_2a1 #(PwrC) mDIR( mDIR_o__mMODO1_A,
                        Qright,
                        Qleft,
                        DIR
                        );

  mux_2a1 #(PwrC) mMODO1( oD,
                          mDIR_o__mMODO1_A,
                          D,
                          MODO1
                          );

  always @(posedge oD or negedge oD) begin

    letest.m1.PwrCntr[PwrC] = letest.m1.PwrCntr[PwrC] + 1;

  end

endmodule