data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/alu.v
'utf-8' codec can't decode byte 0x98 in position 1241: invalid start byte
1: b'%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/alu.v:2: Cannot find include file: instr_head.v\n`include "instr_head.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new,data/full_repos/permissive/206017343/instr_head.v\n             data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new,data/full_repos/permissive/206017343/instr_head.v.v\n             data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new,data/full_repos/permissive/206017343/instr_head.v.sv\n             instr_head.v\n             instr_head.v.v\n             instr_head.v.sv\n             obj_dir/instr_head.v\n             obj_dir/instr_head.v.v\n             obj_dir/instr_head.v.sv\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/alu.v:19: Define or directive not defined: \'`ALU_OP_ADD\'\n    assign alu_temp = (alu_op_ctrl == `ALU_OP_ADD) ? {alu_src_a[31], alu_src_a} + {alu_src_b[31], alu_src_b} :\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/alu.v:19: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign alu_temp = (alu_op_ctrl == `ALU_OP_ADD) ? {alu_src_a[31], alu_src_a} + {alu_src_b[31], alu_src_b} :\n                                                 ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/alu.v:20: Define or directive not defined: \'`ALU_OP_SUB\'\n                      (alu_op_ctrl == `ALU_OP_SUB) ? {alu_src_a[31], alu_src_a} - {alu_src_b[31], alu_src_b} : {alu_src_b[31], alu_src_b};\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/alu.v:21: Define or directive not defined: \'`ALU_ZERO_TRUE\'\n    assign alu_zero_signal = (alu_temp == 0) ? `ALU_ZERO_TRUE : `ALU_ZERO_FALSE;\n                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/alu.v:21: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign alu_zero_signal = (alu_temp == 0) ? `ALU_ZERO_TRUE : `ALU_ZERO_FALSE;\n                                                              ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/alu.v:21: Define or directive not defined: \'`ALU_ZERO_FALSE\'\n    assign alu_zero_signal = (alu_temp == 0) ? `ALU_ZERO_TRUE : `ALU_ZERO_FALSE;\n                                                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/alu.v:22: Define or directive not defined: \'`ALU_LESS_TRUE\'\n    assign alu_less_signal = (alu_temp[31] == 1) ? `ALU_LESS_TRUE : `ALU_LESS_FALSE;\n                                                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/alu.v:22: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign alu_less_signal = (alu_temp[31] == 1) ? `ALU_LESS_TRUE : `ALU_LESS_FALSE;\n                                                                  ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/alu.v:22: Define or directive not defined: \'`ALU_LESS_FALSE\'\n    assign alu_less_signal = (alu_temp[31] == 1) ? `ALU_LESS_TRUE : `ALU_LESS_FALSE;\n                                                                    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n'
module alu(
    input wire[31:0] alu_src_a,
    input wire[31:0] alu_src_b,
    input wire[1:0] alu_op_ctrl,

    output wire alu_zero_signal,
    output wire alu_less_signal,
    output wire[31:0] alu_result
    );


    wire[32:0] alu_temp;

    assign alu_result = alu_temp[31:0];

    assign alu_temp = (alu_op_ctrl == `ALU_OP_ADD) ? {alu_src_a[31], alu_src_a} + {alu_src_b[31], alu_src_b} :
                      (alu_op_ctrl == `ALU_OP_SUB) ? {alu_src_a[31], alu_src_a} - {alu_src_b[31], alu_src_b} : {alu_src_b[31], alu_src_b};
    assign alu_zero_signal = (alu_temp == 0) ? `ALU_ZERO_TRUE : `ALU_ZERO_FALSE;
    assign alu_less_signal = (alu_temp[31] == 1) ? `ALU_LESS_TRUE : `ALU_LESS_FALSE;
endmodule
module alu(
    input wire[31:0] alu_src_a,
    input wire[31:0] alu_src_b,
    input wire[1:0] alu_op_ctrl,

    output wire alu_zero_signal,
    output wire alu_less_signal,
    output wire[31:0] alu_result
    );



    wire[32:0] alu_temp;

    assign alu_result = alu_temp[31:0];

    assign alu_temp = (alu_op_ctrl == `ALU_OP_ADD) ? {alu_src_a[31], alu_src_a} + {alu_src_b[31], alu_src_b} :
                      (alu_op_ctrl == `ALU_OP_SUB) ? {alu_src_a[31], alu_src_a} - {alu_src_b[31], alu_src_b} : {alu_src_b[31], alu_src_b};
    assign alu_zero_signal = (alu_temp == 0) ? `ALU_ZERO_TRUE : `ALU_ZERO_FALSE;
    assign alu_less_signal = (alu_temp[31] == 1) ? `ALU_LESS_TRUE : `ALU_LESS_FALSE;
endmodule