data/full_repos/permissive/207835546/Multiplexer/Mux_cond/Mux_cond.v
data/verilator_xmls/52ec104d-e8e6-4ae1-bfe0-fc9a8a0b9920.xml
module mux_cond( select, d, q );

input[1:0] select;
input[3:0] d;
output q;

wire q;
wire[1:0] select;
wire[3:0] d;

assign q = ( select == 0 )? d[0] : ( select == 1 )? d[1] : ( select == 2 )? d[2] : d[3];

endmodule
module mux_cond( select, d, q );


input[1:0] select;
input[3:0] d;
output q;

wire q;
wire[1:0] select;
wire[3:0] d;

assign q = ( select == 0 )? d[0] : ( select == 1 )? d[1] : ( select == 2 )? d[2] : d[3];

endmodule