data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/mux-4x1/mux-4x1.v
1: b"%Error: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/mux-4x1/mux-4x1.v:8: Duplicate declaration of signal: 'y'\n                                                                                                                    : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg  y;\n     ^\n        data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/mux-4x1/mux-4x1.v:5: ... Location of original declaration\n    output y                 \n           ^\n%Error: Exiting due to 1 error(s)\n"
module mux_4x1(
    input  a, b, c, d,
    input  [1:0] sel,
    output y
);

reg  y;

always @ ( * ) begin
    case(sel)
        2'b00 : y <= a;
        2'b01 : y <= b;
        2'b10 : y <= c;
        2'b11 : y <= d;
    endcase
 end

endmodule
module mux_4x1(
    input  a, b, c, d,
    input  [1:0] sel,
    output y
);


reg  y;

always @ ( * ) begin
    case(sel)
        2'b00 : y <= a;
        2'b01 : y <= b;
        2'b10 : y <= c;
        2'b11 : y <= d;
    endcase
 end

endmodule