data/full_repos/permissive/127601528/rtl/mini_fir_mac.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/93693202-21b2-4858-9afb-446bd1f887b8.xml
module mini_fir_mac (
    input             clk,
    input             rst_n,
    input      [ 7:0] i_data,
    input      [ 7:0] i_coeff,
    input      [18:0] i_prev,
    output reg [18:0] o_next    
);


localparam MPY_BITS = 8+8;


localparam ACCU_BITS = MPY_BITS + 3;


wire [MPY_BITS-1:0] mult;

wire [ACCU_BITS-1:0] adder;


assign mult  = i_data * i_coeff;


assign adder = i_prev + {{(ACCU_BITS-MPY_BITS){1'b0}}, mult[MPY_BITS-1:0]};


always @(posedge clk or negedge rst_n) begin
    if(~rst_n) 
        o_next <= 'd0;
    else
        o_next <= adder;
end

endmodule
module mini_fir_mac (
    input             clk,
    input             rst_n,
    input      [ 7:0] i_data,
    input      [ 7:0] i_coeff,
    input      [18:0] i_prev,
    output reg [18:0] o_next    
);



localparam MPY_BITS = 8+8;


localparam ACCU_BITS = MPY_BITS + 3;


wire [MPY_BITS-1:0] mult;

wire [ACCU_BITS-1:0] adder;


assign mult  = i_data * i_coeff;


assign adder = i_prev + {{(ACCU_BITS-MPY_BITS){1'b0}}, mult[MPY_BITS-1:0]};


always @(posedge clk or negedge rst_n) begin
    if(~rst_n) 
        o_next <= 'd0;
    else
        o_next <= adder;
end

endmodule