data/full_repos/permissive/134057391/boards/qm_xc6slx16_sdram/sdram/sdram_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/134057391/boards/qm_xc6slx16_sdram/sdram/sdram_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/134057391/boards/qm_xc6slx16_sdram/sdram/sdram_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2) clk = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/boards/qm_xc6slx16_sdram/sdram/sdram_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD/2);\n        ^\n%Error: data/full_repos/permissive/134057391/boards/qm_xc6slx16_sdram/sdram/sdram_tb.v:56: Cannot find file containing module: \'sdram\'\n sdram #(\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/134057391/boards/qm_xc6slx16_sdram/sdram,data/full_repos/permissive/134057391/sdram\n             data/full_repos/permissive/134057391/boards/qm_xc6slx16_sdram/sdram,data/full_repos/permissive/134057391/sdram.v\n             data/full_repos/permissive/134057391/boards/qm_xc6slx16_sdram/sdram,data/full_repos/permissive/134057391/sdram.sv\n             sdram\n             sdram.v\n             sdram.sv\n             obj_dir/sdram\n             obj_dir/sdram.v\n             obj_dir/sdram.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sdram_tb;

    parameter PERIOD = 10;


	reg clk;
	reg reset;
	reg stb_i;
	reg we_i;
	reg [3:0] sel_i;
	reg cyc_i;
	reg [31:0] addr_i;
	reg [31:0] data_i;


	wire [31:0] data_o;
	wire stall_o;
	wire ack_o;
	wire sdram_clk_o;
	wire sdram_cke_o;
	wire sdram_cs_o;
	wire sdram_ras_o;
	wire sdram_cas_o;
	wire sdram_we_o;
	wire [1:0] sdram_dqm_o;
	wire [12:0] sdram_addr_o;
	wire [1:0] sdram_ba_o;


	wire [15:0] sdram_data_io;


	sdram #(
        .SDRAM_MHZ(100),
        .SDRAM_READ_LATENCY(3)
    )
    uut(
		.clk_i(clk), 
		.rst_i(reset), 
		.stb_i(stb_i), 
		.we_i(we_i), 
		.sel_i(sel_i), 
		.cyc_i(cyc_i), 
		.addr_i(addr_i), 
		.data_i(data_i), 
		.data_o(data_o), 
		.stall_o(stall_o), 
		.ack_o(ack_o), 
		.sdram_clk_o(sdram_clk_o), 
		.sdram_cke_o(sdram_cke_o), 
		.sdram_cs_o(sdram_cs_o), 
		.sdram_ras_o(sdram_ras_o), 
		.sdram_cas_o(sdram_cas_o), 
		.sdram_we_o(sdram_we_o), 
		.sdram_dqm_o(sdram_dqm_o), 
		.sdram_addr_o(sdram_addr_o), 
		.sdram_ba_o(sdram_ba_o), 
		.sdram_data_io(sdram_data_io)
	);

	initial begin

		reset = 1;
		stb_i = 0;
		we_i = 0;
		sel_i = 0;
		cyc_i = 0;
		addr_i = 0;
		data_i = 0;


		#100;
        reset = 1'b0;
	end

    always begin
        clk = 1'b1;
        #(PERIOD/2) clk = 1'b0;
        #(PERIOD/2);
    end  
      
endmodule
module sdram_tb;


    parameter PERIOD = 10;


	reg clk;
	reg reset;
	reg stb_i;
	reg we_i;
	reg [3:0] sel_i;
	reg cyc_i;
	reg [31:0] addr_i;
	reg [31:0] data_i;


	wire [31:0] data_o;
	wire stall_o;
	wire ack_o;
	wire sdram_clk_o;
	wire sdram_cke_o;
	wire sdram_cs_o;
	wire sdram_ras_o;
	wire sdram_cas_o;
	wire sdram_we_o;
	wire [1:0] sdram_dqm_o;
	wire [12:0] sdram_addr_o;
	wire [1:0] sdram_ba_o;


	wire [15:0] sdram_data_io;


	sdram #(
        .SDRAM_MHZ(100),
        .SDRAM_READ_LATENCY(3)
    )
    uut(
		.clk_i(clk), 
		.rst_i(reset), 
		.stb_i(stb_i), 
		.we_i(we_i), 
		.sel_i(sel_i), 
		.cyc_i(cyc_i), 
		.addr_i(addr_i), 
		.data_i(data_i), 
		.data_o(data_o), 
		.stall_o(stall_o), 
		.ack_o(ack_o), 
		.sdram_clk_o(sdram_clk_o), 
		.sdram_cke_o(sdram_cke_o), 
		.sdram_cs_o(sdram_cs_o), 
		.sdram_ras_o(sdram_ras_o), 
		.sdram_cas_o(sdram_cas_o), 
		.sdram_we_o(sdram_we_o), 
		.sdram_dqm_o(sdram_dqm_o), 
		.sdram_addr_o(sdram_addr_o), 
		.sdram_ba_o(sdram_ba_o), 
		.sdram_data_io(sdram_data_io)
	);

	initial begin

		reset = 1;
		stb_i = 0;
		we_i = 0;
		sel_i = 0;
		cyc_i = 0;
		addr_i = 0;
		data_i = 0;


		#100;
        reset = 1'b0;
	end

    always begin
        clk = 1'b1;
        #(PERIOD/2) clk = 1'b0;
        #(PERIOD/2);
    end  
      
endmodule