data/full_repos/permissive/135077285/pc.v
 line:12: before: "&&"
data/verilator_xmls/ec7a4dc6-28f4-4cf1-9a2f-e00c6624cc59.xml
module pc (
  input wire [31:0] nextAddress,
  input hzdWrite,
  input clock,
  output reg [31:0] readAddress
);

  initial begin
    readAddress <= 0;
  end

  always @(posedge clock && hzdWrite) begin
    readAddress <= nextAddress;
  end
endmodule
module pc (
  input wire [31:0] nextAddress,
  input hzdWrite,
  input clock,
  output reg [31:0] readAddress
);


  initial begin
    readAddress <= 0;
  end

  always @(posedge clock && hzdWrite) begin
    readAddress <= nextAddress;
  end
endmodule