data/full_repos/permissive/104053853/digitron.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/104053853/digitron.v:22: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'frequency_divider\'\nmodule frequency_divider (input clock,\n       ^~~~~~~~~~~~~~~~~\n                                                                     : ... Top module \'hello_printer\'\nmodule hello_printer (input switch,\n       ^~~~~~~~~~~~~\n                                                                     : ... Top module \'fin_printer\'\nmodule fin_printer (input switch,\n       ^~~~~~~~~~~\n                                                                     : ... Top module \'digit_printer\'\nmodule digit_printer (input switch,\n       ^~~~~~~~~~~~~\n                                                                     : ... Top module \'bi_printer\'\nmodule bi_printer (input [7:0] seq1,\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module bi_printer (input [7:0] seq1,
                  input [7:0] an1,
                  input [7:0] seq2,
                  input [7:0] an2,
                  input clock,
                  output reg [7:0] seq,
                  output reg [7:0] an);

reg [4:0] count;

always @ (posedge clock)
begin
  if (count < 9) begin seq <= seq1; an <= an1; end
  else if (count < 18) begin seq <= seq2; an <= an2; end
   if (count == 18) count <= 0; else count <= count + 1;
end
endmodule
module bi_printer (input [7:0] seq1,
                  input [7:0] an1,
                  input [7:0] seq2,
                  input [7:0] an2,
                  input clock,
                  output reg [7:0] seq,
                  output reg [7:0] an);


reg [4:0] count;

always @ (posedge clock)
begin
  if (count < 9) begin seq <= seq1; an <= an1; end
  else if (count < 18) begin seq <= seq2; an <= an2; end
   if (count == 18) count <= 0; else count <= count + 1;
end
endmodule