data/full_repos/permissive/203650831/hd44780_syscon.v
1: b"%Error: data/full_repos/permissive/203650831/hd44780_syscon.v:16: Duplicate declaration of signal: 'RST_O'\n                                                                : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire RST_O = ~rst_cnt[3];        \n     ^~~~~\n        data/full_repos/permissive/203650831/hd44780_syscon.v:5: ... Location of original declaration\n    output RST_O,\n           ^~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_syscon.v:17: Duplicate declaration of signal: 'CLK_O'\nwire CLK_O;                      \n     ^~~~~\n        data/full_repos/permissive/203650831/hd44780_syscon.v:6: ... Location of original declaration\n    output CLK_O\n           ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module hd44780_syscon(
    input i_clk,
    output RST_O,
    output CLK_O
);







reg [3:0] rst_cnt = 0;
wire RST_O = ~rst_cnt[3];
wire CLK_O;
always @(posedge CLK_O)
    if( RST_O )
        rst_cnt <= rst_cnt + 1;

assign CLK_O = i_clk;


endmodule
module hd44780_syscon(
    input i_clk,
    output RST_O,
    output CLK_O
);








reg [3:0] rst_cnt = 0;
wire RST_O = ~rst_cnt[3];
wire CLK_O;
always @(posedge CLK_O)
    if( RST_O )
        rst_cnt <= rst_cnt + 1;

assign CLK_O = i_clk;


endmodule