data/full_repos/permissive/2084115/rtl/math/jelly_linear_interpolation.v
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/math/jelly_linear_interpolation.v:241: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                            : ... In instance jelly_linear_interpolation.loop_rate[3].i_linear_interpolation_unit\n            reg_rate  <= (s_rate << 1) | s_rate[RATE_WIDTH-1];\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/2084115/rtl/math/jelly_linear_interpolation.v:62: Cannot find file containing module: \'jelly_data_expand\'\n    jelly_data_expand\n    ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/math,data/full_repos/permissive/2084115/jelly_data_expand\n             data/full_repos/permissive/2084115/rtl/math,data/full_repos/permissive/2084115/jelly_data_expand.v\n             data/full_repos/permissive/2084115/rtl/math,data/full_repos/permissive/2084115/jelly_data_expand.sv\n             jelly_data_expand\n             jelly_data_expand.v\n             jelly_data_expand.sv\n             obj_dir/jelly_data_expand\n             obj_dir/jelly_data_expand.v\n             obj_dir/jelly_data_expand.sv\n%Error: data/full_repos/permissive/2084115/rtl/math/jelly_linear_interpolation.v:78: Cannot find file containing module: \'jelly_data_expand\'\n    jelly_data_expand\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/2084115/rtl/math/jelly_linear_interpolation.v:129: Cannot find file containing module: \'jelly_data_expand\'\n    jelly_data_expand\n    ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module jelly_linear_interpolation_unsigned
        #(
            parameter   DATA_WIDTH = 8,
            parameter   COMPACT    = 0,
            parameter   BLENDING   = 0
        )
        (
            input   wire                        clk,
            input   wire                        cke,
            
            input   wire                        s_sel,
            input   wire    [DATA_WIDTH-1:0]    s_data0,
            input   wire    [DATA_WIDTH-1:0]    s_data1,
            
            output  wire    [DATA_WIDTH-1:0]    m_data0,
            output  wire    [DATA_WIDTH-1:0]    m_data1
        );

    reg     [DATA_WIDTH:0]      reg_data0;
    reg     [DATA_WIDTH:0]      reg_data1;
    wire    [DATA_WIDTH-1:0]    tmp_data = s_sel ? s_data1 : s_data0;
    
    always @(posedge clk) begin
        if ( cke ) begin
            if ( BLENDING ) begin
                reg_data0 <= s_data0 + tmp_data + s_sel;
                reg_data1 <= s_data1 + tmp_data + s_sel;
            end
            else begin
                reg_data0 <= s_data0 + tmp_data;
                reg_data1 <= s_data1 + tmp_data;
            end
        end
    end
    
    assign m_data0 = reg_data0[COMPACT +: DATA_WIDTH];
    assign m_data1 = reg_data1[COMPACT +: DATA_WIDTH];
    
endmodule
module jelly_linear_interpolation_unsigned
        #(
            parameter   DATA_WIDTH = 8,
            parameter   COMPACT    = 0,
            parameter   BLENDING   = 0
        )
        (
            input   wire                        clk,
            input   wire                        cke,
            
            input   wire                        s_sel,
            input   wire    [DATA_WIDTH-1:0]    s_data0,
            input   wire    [DATA_WIDTH-1:0]    s_data1,
            
            output  wire    [DATA_WIDTH-1:0]    m_data0,
            output  wire    [DATA_WIDTH-1:0]    m_data1
        );


    reg     [DATA_WIDTH:0]      reg_data0;
    reg     [DATA_WIDTH:0]      reg_data1;
    wire    [DATA_WIDTH-1:0]    tmp_data = s_sel ? s_data1 : s_data0;
    
    always @(posedge clk) begin
        if ( cke ) begin
            if ( BLENDING ) begin
                reg_data0 <= s_data0 + tmp_data + s_sel;
                reg_data1 <= s_data1 + tmp_data + s_sel;
            end
            else begin
                reg_data0 <= s_data0 + tmp_data;
                reg_data1 <= s_data1 + tmp_data;
            end
        end
    end
    
    assign m_data0 = reg_data0[COMPACT +: DATA_WIDTH];
    assign m_data1 = reg_data1[COMPACT +: DATA_WIDTH];
    
endmodule