data/full_repos/permissive/143278/ivltests/pr675.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr675.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #2\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bug;

wire a, b, c, d;
assign c = 1'bx;
assign a = 1'b1;
assign b = 1'b0;
assign d = 1'bx;

wire e = {c,d} == {a,b};

initial
  begin
    #2
    if ((e == 1'b1) || (e == 1'b0))
        $display("FAILED -- abcde=%b%b%b%b%b", a, b, c, d, e);
    else
        $display("PASSED");
    $finish;
  end

endmodule
module bug;


wire a, b, c, d;
assign c = 1'bx;
assign a = 1'b1;
assign b = 1'b0;
assign d = 1'bx;

wire e = {c,d} == {a,b};

initial
  begin
    #2
    if ((e == 1'b1) || (e == 1'b0))
        $display("FAILED -- abcde=%b%b%b%b%b", a, b, c, d, e);
    else
        $display("PASSED");
    $finish;
  end

endmodule