data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Reciprocal/fp_sRec_Hung.v
1: b'%Error: Cannot find file containing module: Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Reciprocal/fp_sRec_Hung.v\n%Error: Exiting due to 3 error(s)\n'
module fp_sRec_Hung
	#(parameter 
					WI = 8,
					WF = 8,
					WL = WI + WF,	 
					WIO = WF,
					WFO = WI,
					LUT_addWidth = 5,
					LUT_bits = 8
	 )
	 (input 		CLK,
					nRST,
					CE,
	  input     [WI+WF-1 : 0] 	 din,
	  output reg[WIO+WFO-1 : 0] dout
    );

	

	reg sym_np;
	reg [WL-1:0] in;
	always @ * begin
		if (din[WL-1]==1'b0) begin
			sym_np = 1'b0;
			in = din;
		end else begin 
			sym_np = 1'b1;
			in = (~din)+1;
		end
	end
	

	reg [WI+WF-1:0] e_b;
	reg [WI+WF-1:0] e;
	reg sym;
	
	integer counter_e;
	always @ * begin
		for (counter_e=WI+WF-1; counter_e >= 0; counter_e = counter_e-1)
			if (in[WI+WF-counter_e-1]) e = counter_e;
	end

	reg [WL-1:0] in_s;	
	always @* begin	
		in_s = in << e;
		if (WI>=(e+1)) begin
			sym = 1'b0;
			e_b = WI-(e+1);
		end else if ((e+1)> WI) begin
			sym = 1'b1;
			e_b = (e+1)-WI;
		end 
	end 

	wire [`WLO_tmp_1 : 0] out;
	reg  [`WIO_APP_1 : 0] app_zero;
	wire [`WLO_TOTAL_1 : 0] result_tmp;
	reg  [`WLO_TOTAL_1 : 0] result_tmp2;
	
	Reciprocal_Cascaded_Hung
	#(
		.WL(WI+WF),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth),
		.WLO(`WLO_tmp)
    )
	Fang_Reciprocal_Hung
	(
		.CLK(CLK), 
		.nRST(nRST),
		.CE(CE), 
		.din(in_s), 
		.dout(out)
	);
	

	assign result_tmp = {app_zero, out};
	

	always @ * begin
		app_zero = 0;
		if (sym==1'b0) 
			result_tmp2 = result_tmp >> e_b;
		else
			result_tmp2 = result_tmp << e_b;
	end
	

	reg [WIO-1 : 0] outI;
	reg [WFO-1 : 0] outF;
	always @ * begin
		outI = result_tmp2[`WLO_tmp_1_trim : `WLO_tmp_1];
		outF = result_tmp2[`WLO_tmp_2 : `WLO_tmp_trim_WFO];
	end

	wire [WIO+WFO-1 : 0] out_tmp;
	assign out_tmp = {outI,outF};
	
	always @* begin
		if (out_tmp==0)
			if (din[WL-1]==1'b0)
				dout = {{1'b0},{{WL-1}{1'b1}}}; 
			else
				dout = {{1'b1},{{WL-1}{1'b0}}};
		else if (sym_np==1'b0)
			dout = out_tmp;
		else
			dout = ~out_tmp+1;
	end

endmodule
module fp_sRec_Hung
	#(parameter 
					WI = 8,
					WF = 8,
					WL = WI + WF,	 
					WIO = WF,
					WFO = WI,
					LUT_addWidth = 5,
					LUT_bits = 8
	 )
	 (input 		CLK,
					nRST,
					CE,
	  input     [WI+WF-1 : 0] 	 din,
	  output reg[WIO+WFO-1 : 0] dout
    );


	

	reg sym_np;
	reg [WL-1:0] in;
	always @ * begin
		if (din[WL-1]==1'b0) begin
			sym_np = 1'b0;
			in = din;
		end else begin 
			sym_np = 1'b1;
			in = (~din)+1;
		end
	end
	

	reg [WI+WF-1:0] e_b;
	reg [WI+WF-1:0] e;
	reg sym;
	
	integer counter_e;
	always @ * begin
		for (counter_e=WI+WF-1; counter_e >= 0; counter_e = counter_e-1)
			if (in[WI+WF-counter_e-1]) e = counter_e;
	end

	reg [WL-1:0] in_s;	
	always @* begin	
		in_s = in << e;
		if (WI>=(e+1)) begin
			sym = 1'b0;
			e_b = WI-(e+1);
		end else if ((e+1)> WI) begin
			sym = 1'b1;
			e_b = (e+1)-WI;
		end 
	end 

	wire [`WLO_tmp_1 : 0] out;
	reg  [`WIO_APP_1 : 0] app_zero;
	wire [`WLO_TOTAL_1 : 0] result_tmp;
	reg  [`WLO_TOTAL_1 : 0] result_tmp2;
	
	Reciprocal_Cascaded_Hung
	#(
		.WL(WI+WF),
		.LUT_bits(LUT_bits),
		.LUT_addWidth(LUT_addWidth),
		.WLO(`WLO_tmp)
    )
	Fang_Reciprocal_Hung
	(
		.CLK(CLK), 
		.nRST(nRST),
		.CE(CE), 
		.din(in_s), 
		.dout(out)
	);
	

	assign result_tmp = {app_zero, out};
	

	always @ * begin
		app_zero = 0;
		if (sym==1'b0) 
			result_tmp2 = result_tmp >> e_b;
		else
			result_tmp2 = result_tmp << e_b;
	end
	

	reg [WIO-1 : 0] outI;
	reg [WFO-1 : 0] outF;
	always @ * begin
		outI = result_tmp2[`WLO_tmp_1_trim : `WLO_tmp_1];
		outF = result_tmp2[`WLO_tmp_2 : `WLO_tmp_trim_WFO];
	end

	wire [WIO+WFO-1 : 0] out_tmp;
	assign out_tmp = {outI,outF};
	
	always @* begin
		if (out_tmp==0)
			if (din[WL-1]==1'b0)
				dout = {{1'b0},{{WL-1}{1'b1}}}; 
			else
				dout = {{1'b1},{{WL-1}{1'b0}}};
		else if (sym_np==1'b0)
			dout = out_tmp;
		else
			dout = ~out_tmp+1;
	end

endmodule