data/full_repos/permissive/116468596/m8_le.v
data/verilator_xmls/f8faa2ca-38a0-4595-94d3-f87d88903f90.xml
module m8_le(
    input [7:0] in,
    input [2:0] sel,
    input e,
    output o
    );
    
    wire [7:0] c;
    
    assign c[0] = (~sel[2] & ~sel[1] & ~sel[0] * in[0]);
    assign c[1] = (~sel[2] & ~sel[1] & sel[0] * in[1]);
    assign c[2] = (~sel[2] & sel[1] & ~sel[0] * in[2]);
    assign c[3] = (~sel[2] & sel[1] & sel[0] * in[3]);
    assign c[4] = (sel[2] & ~sel[1] & ~sel[0] * in[4]);
    assign c[5] = (sel[2] & ~sel[1] & sel[0] * in[5]);
    assign c[6] = (sel[2] & sel[1] & ~sel[0] * in[6]);
    assign c[7] = (sel[2] & sel[1] & sel[0] * in[7]);
    assign o = e & (c[0] | c[1] | c[2] | c[3] | c[4] | c[5] | c[6] | c[7]);
    
endmodule
module m8_le(
    input [7:0] in,
    input [2:0] sel,
    input e,
    output o
    );

    
    wire [7:0] c;
    
    assign c[0] = (~sel[2] & ~sel[1] & ~sel[0] * in[0]);
    assign c[1] = (~sel[2] & ~sel[1] & sel[0] * in[1]);
    assign c[2] = (~sel[2] & sel[1] & ~sel[0] * in[2]);
    assign c[3] = (~sel[2] & sel[1] & sel[0] * in[3]);
    assign c[4] = (sel[2] & ~sel[1] & ~sel[0] * in[4]);
    assign c[5] = (sel[2] & ~sel[1] & sel[0] * in[5]);
    assign c[6] = (sel[2] & sel[1] & ~sel[0] * in[6]);
    assign c[7] = (sel[2] & sel[1] & sel[0] * in[7]);
    assign o = e & (c[0] | c[1] | c[2] | c[3] | c[4] | c[5] | c[6] | c[7]);
    
endmodule