data/full_repos/permissive/209997170/Sound/pwm_tutorial/source/music.v
data/verilator_xmls/50379963-634a-4c69-8333-6ba8f6b2e1e3.xml
module music(clk, speaker);
  input clk;
  output speaker;


reg [15:0] counter;
always @(posedge clk) counter <= counter+1;


assign speaker = counter[15];
endmodule
module music(clk, speaker);

  input clk;
  output speaker;


reg [15:0] counter;
always @(posedge clk) counter <= counter+1;


assign speaker = counter[15];
endmodule