data/full_repos/permissive/168395472/labs/06_rom/top.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/168395472/labs/06_rom/top.v:22: Signal definition not found, creating implicitly: \'clk3\'\nrom_fetcher rom_fetcher(.clk(clk3), .q(d));\n                             ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/168395472/labs/06_rom/top.v:35: Cannot find file containing module: \'rom\'\nrom #(.WIDTH(16)) rom(.clk(clk), .addr(pc), .q(q));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/168395472/labs/06_rom,data/full_repos/permissive/168395472/rom\n             data/full_repos/permissive/168395472/labs/06_rom,data/full_repos/permissive/168395472/rom.v\n             data/full_repos/permissive/168395472/labs/06_rom,data/full_repos/permissive/168395472/rom.sv\n             rom\n             rom.v\n             rom.sv\n             obj_dir/rom\n             obj_dir/rom.v\n             obj_dir/rom.sv\n%Error: data/full_repos/permissive/168395472/labs/06_rom/top.v:16: Cannot find file containing module: \'clk_div\'\nclk_div clk_div(.clk_in(CLK), .clk_out(clk2));\n^~~~~~~\n%Error: data/full_repos/permissive/168395472/labs/06_rom/top.v:18: Cannot find file containing module: \'clk_div\'\nclk_div #(.X(24)) clk_div2(.clk_in(CLK), .clk_out(clk3));\n^~~~~~~\n%Error: data/full_repos/permissive/168395472/labs/06_rom/top.v:20: Cannot find file containing module: \'hex_display\'\nhex_display hd(.clk(clk2), .data(d), .anodes(anodes), .segments(segments));\n^~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module top(
    input CLK,

    output DS_EN1, DS_EN2, DS_EN3, DS_EN4,
    output DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G
);

wire [15:0]d;

wire [3:0]anodes;
assign {DS_EN1, DS_EN2, DS_EN3, DS_EN4} = ~anodes;

wire [6:0]segments;
assign {DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G} = segments;

clk_div clk_div(.clk_in(CLK), .clk_out(clk2));

clk_div #(.X(24)) clk_div2(.clk_in(CLK), .clk_out(clk3));

hex_display hd(.clk(clk2), .data(d), .anodes(anodes), .segments(segments));

rom_fetcher rom_fetcher(.clk(clk3), .q(d));

endmodule
module top(
    input CLK,

    output DS_EN1, DS_EN2, DS_EN3, DS_EN4,
    output DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G
);


wire [15:0]d;

wire [3:0]anodes;
assign {DS_EN1, DS_EN2, DS_EN3, DS_EN4} = ~anodes;

wire [6:0]segments;
assign {DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G} = segments;

clk_div clk_div(.clk_in(CLK), .clk_out(clk2));

clk_div #(.X(24)) clk_div2(.clk_in(CLK), .clk_out(clk3));

hex_display hd(.clk(clk2), .data(d), .anodes(anodes), .segments(segments));

rom_fetcher rom_fetcher(.clk(clk3), .q(d));

endmodule