data/full_repos/permissive/146073027/Simple 32bit integer ALU.v
 line:28: before: "assign"
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/146073027/Simple\n        ... Looked in:\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple.v\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple.sv\n             data/full_repos/permissive/146073027/Simple\n             data/full_repos/permissive/146073027/Simple.v\n             data/full_repos/permissive/146073027/Simple.sv\n             obj_dir/data/full_repos/permissive/146073027/Simple\n             obj_dir/data/full_repos/permissive/146073027/Simple.v\n             obj_dir/data/full_repos/permissive/146073027/Simple.sv\n%Error: Cannot find file containing module: 32bit\n%Error: Cannot find file containing module: integer\n%Error: Cannot find file containing module: ALU.v\n%Error: Exiting due to 4 error(s)\n'
module subtractor(out,c_in,x,y);
  output [31:0]out;
  input [31:0]x,y;
  input c_in;
  wire c_out,c_dummy;
  wire [31:0]sum1,sum2,sum3,y_c;
  
  
  ones_complement oc0(y_c,y);
  thirtytwo_bit_fa thirtytwo_fa0(c_out,sum1,c_in,x,y_c);
  ones_complement oc1(sum2,sum1);
  thirtytwo_bit_fa thirtytwo_fa1(c_dummy,sum3,c_in,sum1,c_out);
  assign out=c_out?sum3:-sum2;
endmodule
module subtractor(out,c_in,x,y);

  output [31:0]out;
  input [31:0]x,y;
  input c_in;
  wire c_out,c_dummy;
  wire [31:0]sum1,sum2,sum3,y_c;
  
  
  ones_complement oc0(y_c,y);
  thirtytwo_bit_fa thirtytwo_fa0(c_out,sum1,c_in,x,y_c);
  ones_complement oc1(sum2,sum1);
  thirtytwo_bit_fa thirtytwo_fa1(c_dummy,sum3,c_in,sum1,c_out);
  assign out=c_out?sum3:-sum2;
endmodule