data/full_repos/permissive/156539908/circle-tunnel/circle-tunnel.v
 line:66: before: ")"
1: b'%Error: data/full_repos/permissive/156539908/circle-tunnel/circle-tunnel.v:3: Cannot find include file: ../include/led-delay.v\n`include "../include/led-delay.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156539908/circle-tunnel,data/full_repos/permissive/156539908/../include/led-delay.v\n             data/full_repos/permissive/156539908/circle-tunnel,data/full_repos/permissive/156539908/../include/led-delay.v.v\n             data/full_repos/permissive/156539908/circle-tunnel,data/full_repos/permissive/156539908/../include/led-delay.v.sv\n             ../include/led-delay.v\n             ../include/led-delay.v.v\n             ../include/led-delay.v.sv\n             obj_dir/../include/led-delay.v\n             obj_dir/../include/led-delay.v.v\n             obj_dir/../include/led-delay.v.sv\n%Error: Exiting due to 1 error(s)\n'
module painter(
        input        clk,
        input        reset,
        input  [6:0] frame,
        input  [7:0] subframe,
        input  [5:0] x,
        input  [5:0] y,
        output [2:0] rgb);

    reg [11:0] x2, y2;
    always @(posedge clk) begin
        x2 <= (6'd32 - x) * (6'd32 - x);
        y2 <= (6'd32 - y) * (6'd32 - y);
    end

    reg [11:0] r2;
    always @(posedge clk) begin
        r2 <= x2 + y2;
    end

    reg  [7:0] sqrt_table [0:2047];
    initial $readmemh("sqrt_table.hex", sqrt_table);

    reg  [5:0] r;
    always @(posedge clk) begin
        r <= sqrt_table[r2];
    end

    wire [4:0] color;
    wire red, green, blue;
    assign color = r - frame[2+:5];
    assign red = & color;
    assign green = 0;
    assign blue = & color[1:0];
    assign rgb = {blue, green, red};

endmodule
module painter(
        input        clk,
        input        reset,
        input  [6:0] frame,
        input  [7:0] subframe,
        input  [5:0] x,
        input  [5:0] y,
        output [2:0] rgb);


    reg [11:0] x2, y2;
    always @(posedge clk) begin
        x2 <= (6'd32 - x) * (6'd32 - x);
        y2 <= (6'd32 - y) * (6'd32 - y);
    end

    reg [11:0] r2;
    always @(posedge clk) begin
        r2 <= x2 + y2;
    end

    reg  [7:0] sqrt_table [0:2047];
    initial $readmemh("sqrt_table.hex", sqrt_table);

    reg  [5:0] r;
    always @(posedge clk) begin
        r <= sqrt_table[r2];
    end

    wire [4:0] color;
    wire red, green, blue;
    assign color = r - frame[2+:5];
    assign red = & color;
    assign green = 0;
    assign blue = & color[1:0];
    assign rgb = {blue, green, red};

endmodule