data/full_repos/permissive/156609923/final/probador.v
 line:131: before: "("
1: b'%Error: data/full_repos/permissive/156609923/final/probador.v:59: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("pcie.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/156609923/final/probador.v:60: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Error: data/full_repos/permissive/156609923/final/probador.v:61: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:64: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:68: syntax error, unexpected \'@\'\n   @(posedge clk);  \n   ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:77: syntax error, unexpected \'@\'\n   @(posedge clk);  \n   ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:85: syntax error, unexpected \'@\'\n     @(posedge clk); \n     ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:93: syntax error, unexpected \'@\'\n      @(posedge clk);  \n      ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:100: syntax error, unexpected \'@\'\n      @(posedge clk);  \n      ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:107: syntax error, unexpected \'@\'\n      @(posedge clk);  \n      ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:114: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:124: syntax error, unexpected \'@\'\n      @(posedge clk); \n      ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:132: syntax error, unexpected \'@\'\n      @(posedge clk); \n      ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:142: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:149: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:156: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:163: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/156609923/final/probador.v:170: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/final/probador.v:177: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156609923/final/probador.v:193: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk <= ~clk;\n          ^\n%Error: Exiting due to 18 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador #(
parameter ADDR_WIDTH = 3,
parameter BUS_SIZE = 5,
parameter MEM_LENGTH = 1 << ADDR_WIDTH)(

 output reg 		 clk,
 output reg 		 reset ,
 
 output reg [BUS_SIZE:0] data_p0,
 output reg 		 valid_p0,

 output reg [BUS_SIZE:0] data_p1,
 output reg 		 valid_p1,

 output reg [3:0] 	 umbralA,
 output reg [3:0] 	 umbralB,
 output reg 		 init,
 
 input [BUS_SIZE-1:0] 	 out_p1,
 input [BUS_SIZE-1:0] 	 out_p0,
					
 input 			 continue_VC0P0,
 input 			 continue_VC1P0,
 input 			 continue_VC0P1,
 input 			 continue_VC1P1, 
 
 input 			 pause_VC0P0,
 input 			 pause_VC1P0,
 input 			 pause_VC0P1,
 input 			 pause_VC1P1,
		   
 input [BUS_SIZE-1:0] 	 out_p1E,
 input [BUS_SIZE-1:0] 	 out_p0E,
					
 input 			 continue_VC0P0E,
 input 			 continue_VC1P0E,
 input 			 continue_VC0P1E,
 input 			 continue_VC1P1E, 
 
 input 			 pause_VC0P0E,
 input 			 pause_VC1P0E,
 input 			 pause_VC0P1E,
 input 			 pause_VC1P1E,

 input 			 active,
 input 			 idle,
 input 			 error,
 input [7:0] 		 umbrales_VCFC,
 
 input 			 activeE,
 input 			 idleE,
 input 			 errorE,
 input [7:0] 		 umbrales_VCFCE					
);
   
   

   initial begin
   $dumpfile("pcie.vcd");
	$dumpvars();
   @(posedge clk);
      init <=1;
      
   @(posedge clk);
      reset<=0;
        
   
   @(posedge clk);
      data_p0<=6'b011011;
      valid_p0<=1;
      
      data_p1<='b001101;
      valid_p1<=1;
      
      
   
   @(posedge clk);
      data_p0<='b000011;
      valid_p0<=1;
      
      data_p1<='b010001;
      valid_p1<=1;


     @(posedge clk);
      data_p0<='b011010;
      valid_p0<=1;
      
      data_p1<='b001100;
      valid_p1<=1;

      
      @(posedge clk);
      data_p0<='b001001;
      valid_p0<=1;
      
      data_p1<='b011001;
      valid_p1<=1;
      
      @(posedge clk);
      data_p0<='b011011;
      valid_p0<=1;
      
      data_p1<='b001101;
      valid_p1<=1;

      @(posedge clk);
      data_p0<='b011111;
      valid_p0<=1;
      
      data_p1<='b001111;
      valid_p1<=1;

       @(posedge clk);

      data_p0<='b010111;
      valid_p0<=1;
      
      data_p1<='b000111;
      valid_p1<=1;


      
      @(posedge clk); 
      data_p0<='b111001;
      valid_p0<=0;
      
      data_p1<='b101101;
      valid_p1<=0;

      repeat(7)begin
      @(posedge clk); 
      end
      
      @(posedge clk);
      data_p0<='b101011;
      valid_p0<=1;
      
      data_p1<='b111101;
      valid_p1<=1;

      @(posedge clk);
      data_p0<='b101001;
      valid_p0<=1;
      
      data_p1<='b110101;
      valid_p1<=1;

       @(posedge clk);
      data_p0<='b110011;
      valid_p0<=1;
      
      data_p1<='b100101;
      valid_p1<=1;

      @(posedge clk);
      data_p0<='b111001;
      valid_p0<=1;
      
      data_p1<='b101111;
      valid_p1<=1;

      @(posedge clk);
      data_p0<='b111111;
      valid_p0<=1;
      
      data_p1<='b100111;
      valid_p1<=1;

      @(posedge clk);
      data_p0<='b110000;
      valid_p0<=1;
      
      data_p1<='b100000;
      valid_p1<=1;

      #100
   $finish;
end  
   
   initial clk <= 0;
   initial reset<=1;
   initial valid_p0<=0;
   initial valid_p1<=0;
   initial data_p0<=0;
   initial data_p1<=0;
   initial umbralA<=4'd6;
   initial umbralB<=4'd3;
   initial init <=0 ;
   
   
      
   always #1 clk <= ~clk;
   

endmodule
module probador #(
parameter ADDR_WIDTH = 3,
parameter BUS_SIZE = 5,
parameter MEM_LENGTH = 1 << ADDR_WIDTH)(

 output reg 		 clk,
 output reg 		 reset ,
 
 output reg [BUS_SIZE:0] data_p0,
 output reg 		 valid_p0,

 output reg [BUS_SIZE:0] data_p1,
 output reg 		 valid_p1,

 output reg [3:0] 	 umbralA,
 output reg [3:0] 	 umbralB,
 output reg 		 init,
 
 input [BUS_SIZE-1:0] 	 out_p1,
 input [BUS_SIZE-1:0] 	 out_p0,
					
 input 			 continue_VC0P0,
 input 			 continue_VC1P0,
 input 			 continue_VC0P1,
 input 			 continue_VC1P1, 
 
 input 			 pause_VC0P0,
 input 			 pause_VC1P0,
 input 			 pause_VC0P1,
 input 			 pause_VC1P1,
		   
 input [BUS_SIZE-1:0] 	 out_p1E,
 input [BUS_SIZE-1:0] 	 out_p0E,
					
 input 			 continue_VC0P0E,
 input 			 continue_VC1P0E,
 input 			 continue_VC0P1E,
 input 			 continue_VC1P1E, 
 
 input 			 pause_VC0P0E,
 input 			 pause_VC1P0E,
 input 			 pause_VC0P1E,
 input 			 pause_VC1P1E,

 input 			 active,
 input 			 idle,
 input 			 error,
 input [7:0] 		 umbrales_VCFC,
 
 input 			 activeE,
 input 			 idleE,
 input 			 errorE,
 input [7:0] 		 umbrales_VCFCE					
);

   
   

   initial begin
   $dumpfile("pcie.vcd");
	$dumpvars();
   @(posedge clk);
      init <=1;
      
   @(posedge clk);
      reset<=0;
        
   
   @(posedge clk);
      data_p0<=6'b011011;
      valid_p0<=1;
      
      data_p1<='b001101;
      valid_p1<=1;
      
      
   
   @(posedge clk);
      data_p0<='b000011;
      valid_p0<=1;
      
      data_p1<='b010001;
      valid_p1<=1;


     @(posedge clk);
      data_p0<='b011010;
      valid_p0<=1;
      
      data_p1<='b001100;
      valid_p1<=1;

      
      @(posedge clk);
      data_p0<='b001001;
      valid_p0<=1;
      
      data_p1<='b011001;
      valid_p1<=1;
      
      @(posedge clk);
      data_p0<='b011011;
      valid_p0<=1;
      
      data_p1<='b001101;
      valid_p1<=1;

      @(posedge clk);
      data_p0<='b011111;
      valid_p0<=1;
      
      data_p1<='b001111;
      valid_p1<=1;

       @(posedge clk);

      data_p0<='b010111;
      valid_p0<=1;
      
      data_p1<='b000111;
      valid_p1<=1;


      
      @(posedge clk); 
      data_p0<='b111001;
      valid_p0<=0;
      
      data_p1<='b101101;
      valid_p1<=0;

      repeat(7)begin
      @(posedge clk); 
      end
      
      @(posedge clk);
      data_p0<='b101011;
      valid_p0<=1;
      
      data_p1<='b111101;
      valid_p1<=1;

      @(posedge clk);
      data_p0<='b101001;
      valid_p0<=1;
      
      data_p1<='b110101;
      valid_p1<=1;

       @(posedge clk);
      data_p0<='b110011;
      valid_p0<=1;
      
      data_p1<='b100101;
      valid_p1<=1;

      @(posedge clk);
      data_p0<='b111001;
      valid_p0<=1;
      
      data_p1<='b101111;
      valid_p1<=1;

      @(posedge clk);
      data_p0<='b111111;
      valid_p0<=1;
      
      data_p1<='b100111;
      valid_p1<=1;

      @(posedge clk);
      data_p0<='b110000;
      valid_p0<=1;
      
      data_p1<='b100000;
      valid_p1<=1;

      #100
   $finish;
end  
   
   initial clk <= 0;
   initial reset<=1;
   initial valid_p0<=0;
   initial valid_p1<=0;
   initial data_p0<=0;
   initial data_p1<=0;
   initial umbralA<=4'd6;
   initial umbralB<=4'd3;
   initial init <=0 ;
   
   
      
   always #1 clk <= ~clk;
   

endmodule