data/full_repos/permissive/179227721/led_counter_icestick/counter.v
data/verilator_xmls/38aaeb21-c2e5-4321-92d4-49794d4f6a53.xml
module counter (
                input        clk,
                input        rst,
                output [4:0] led
                );

   reg [4:0]                 counter;

   always@(posedge clk)
     begin
        if (!rst)
          begin
             counter <= 0;
          end
        counter <= counter + 1;
     end

   assign led = counter;
endmodule
module counter (
                input        clk,
                input        rst,
                output [4:0] led
                );


   reg [4:0]                 counter;

   always@(posedge clk)
     begin
        if (!rst)
          begin
             counter <= 0;
          end
        counter <= counter + 1;
     end

   assign led = counter;
endmodule