data/full_repos/permissive/143278/ivltests/tern8.v
 line:27: before: "real"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tern8.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a != 2.0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tern8.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a != 1.0) begin\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg b;
   real c, d;
   wire real a = b ? c : d;

   initial begin

      b <= 0;
      c <= 1.0;
      d <= 2.0;
      #1 if (a != 2.0) begin
	 $display("FAILED (1)");
	 $finish;
      end

      b <= 1;
      #1 if (a != 1.0) begin
	 $display("FAILED (2)");
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg b;
   real c, d;
   wire real a = b ? c : d;

   initial begin

      b <= 0;
      c <= 1.0;
      d <= 2.0;
      #1 if (a != 2.0) begin
	 $display("FAILED (1)");
	 $finish;
      end

      b <= 1;
      #1 if (a != 1.0) begin
	 $display("FAILED (2)");
	 $finish;
      end

      $display("PASSED");
   end

endmodule