data/full_repos/permissive/19478345/arbiter/arbiter_tb.v
 line:26: before: "for"
1: b'%Warning-STMTDLY: data/full_repos/permissive/19478345/arbiter/arbiter_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19478345/arbiter/arbiter_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #101 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/arbiter/arbiter_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n            #10 push[0] = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/arbiter/arbiter_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/arbiter/arbiter_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10 push[0] = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19478345/arbiter/arbiter_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/19478345/arbiter/arbiter_tb.v:4: Little bit endian vector: MSB < LSB of bit range: 0:7\n    reg [0:7] push;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/19478345/arbiter/arbiter_tb.v:6: Little bit endian vector: MSB < LSB of bit range: 0:7\n    wire [0:7] full;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/19478345/arbiter/arbiter_tb.v:7: Little bit endian vector: MSB < LSB of bit range: 0:7\n    wire [0:7] almost_full;\n         ^\n%Error: data/full_repos/permissive/19478345/arbiter/arbiter_tb.v:13: Cannot find file containing module: \'arbiter\'\n    arbiter dut(rst, clk, push, d, full, q, stall, valid, almost_full);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19478345/arbiter,data/full_repos/permissive/19478345/arbiter\n             data/full_repos/permissive/19478345/arbiter,data/full_repos/permissive/19478345/arbiter.v\n             data/full_repos/permissive/19478345/arbiter,data/full_repos/permissive/19478345/arbiter.sv\n             arbiter\n             arbiter.v\n             arbiter.sv\n             obj_dir/arbiter\n             obj_dir/arbiter.v\n             obj_dir/arbiter.sv\n%Warning-WIDTH: data/full_repos/permissive/19478345/arbiter/arbiter_tb.v:28: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                           : ... In instance arbiter_tb\n            d[63:56] = i;\n                     ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module arbiter_tb;

    reg rst, clk;
    reg [0:7] push;
    reg [63:0] d;
    wire [0:7] full;
    wire [0:7] almost_full;
    wire [7:0] q;
    reg stall;
    wire valid;


    arbiter dut(rst, clk, push, d, full, q, stall, valid, almost_full);
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end
    integer i;
    initial begin
        rst = 1;
        push = 0;
        d = 0;
        stall = 0;
        #101 rst = 0;
        #50
        for(i = 0; i < 8; i = i + 1) begin
            #10 push[0] = 1;
            d[63:56] = i;
        end
        #10 push[0] = 0;


        #100 $finish;
    end

    always @(posedge clk) begin
        if(valid)
            $display("valid: %d %d", q, $time);

    end

endmodule
module arbiter_tb;


    reg rst, clk;
    reg [0:7] push;
    reg [63:0] d;
    wire [0:7] full;
    wire [0:7] almost_full;
    wire [7:0] q;
    reg stall;
    wire valid;


    arbiter dut(rst, clk, push, d, full, q, stall, valid, almost_full);
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end
    integer i;
    initial begin
        rst = 1;
        push = 0;
        d = 0;
        stall = 0;
        #101 rst = 0;
        #50
        for(i = 0; i < 8; i = i + 1) begin
            #10 push[0] = 1;
            d[63:56] = i;
        end
        #10 push[0] = 0;


        #100 $finish;
    end

    always @(posedge clk) begin
        if(valid)
            $display("valid: %d %d", q, $time);

    end

endmodule