data/full_repos/permissive/160437780/Source/FreqDev.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160437780/Source/FreqDev.v:37: Operator DIV expects 32 or 18 bits on the LHS, but LHS\'s VARREF \'Clear\' generates 10 bits.\n                                                                        : ... In instance FreqDiv\n                    Num = (Freq * 100) + (Clear / 2);  \n                                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/FreqDev.v:45: Operator SUB expects 18 bits on the RHS, but RHS\'s VARREF \'Dem\' generates 10 bits.\n                                                                        : ... In instance FreqDiv\n                    Num = Num - Dem;  \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/FreqDev.v:43: Operator GTE expects 18 bits on the RHS, but RHS\'s VARREF \'Dem\' generates 10 bits.\n                                                                        : ... In instance FreqDiv\n                if (Num >= Dem)  \n                        ^~\n%Warning-UNSIGNED: data/full_repos/permissive/160437780/Source/FreqDev.v:34: Comparison is constant due to unsigned arithmetic\n                                                                           : ... In instance FreqDiv\n                if ((Freq >= 0) && (Clear >= 0))  \n                          ^~\n%Warning-UNSIGNED: data/full_repos/permissive/160437780/Source/FreqDev.v:34: Comparison is constant due to unsigned arithmetic\n                                                                           : ... In instance FreqDiv\n                if ((Freq >= 0) && (Clear >= 0))  \n                                          ^~\n%Error: Exiting due to 5 warning(s)\n'
module FreqDiv(
    input clk,
    input [9:0] Freq,
    input [9:0] Clear,
    input Start,
    output reg [7:0] Perc,
    output reg Done
    );
    
    reg [17:0] Num = 0;
    reg [9:0] Dem = 0;
    reg [7:0] Count = 0;
    reg [1:0] State = 2'b00;
    
    always @ (posedge clk)
    begin
        if (~Start)
        begin
            Num = 0;
            Dem = 0;
            Perc = 0;
            State = 2'b00;
            Count = 0;
            Done = 0;
        end
        else
        begin
        case (State)
            2'b00:
            begin
                if ((Freq >= 0) && (Clear >= 0))
                begin
                    Dem = Clear;
                    Num = (Freq * 100) + (Clear / 2);
                    State = 2'b01;
                end
            end
            2'b01:
            begin
                if (Num >= Dem)
                begin
                    Num = Num - Dem;
                    Count = Count + 1;
                end
                else 
                begin
                    State = 2'b10;
                end
            end
            2'b10:
            begin
                Perc = Count;
                Done = 1;
            end
       endcase 
       end    
    end
    
endmodule
module FreqDiv(
    input clk,
    input [9:0] Freq,
    input [9:0] Clear,
    input Start,
    output reg [7:0] Perc,
    output reg Done
    );

    
    reg [17:0] Num = 0;
    reg [9:0] Dem = 0;
    reg [7:0] Count = 0;
    reg [1:0] State = 2'b00;
    
    always @ (posedge clk)
    begin
        if (~Start)
        begin
            Num = 0;
            Dem = 0;
            Perc = 0;
            State = 2'b00;
            Count = 0;
            Done = 0;
        end
        else
        begin
        case (State)
            2'b00:
            begin
                if ((Freq >= 0) && (Clear >= 0))
                begin
                    Dem = Clear;
                    Num = (Freq * 100) + (Clear / 2);
                    State = 2'b01;
                end
            end
            2'b01:
            begin
                if (Num >= Dem)
                begin
                    Num = Num - Dem;
                    Count = Count + 1;
                end
                else 
                begin
                    State = 2'b10;
                end
            end
            2'b10:
            begin
                Perc = Count;
                Done = 1;
            end
       endcase 
       end    
    end
    
endmodule