data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params/sim_dsp_mult_r_cfg_params.v
None: at end of input
1: b'%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params/sim_dsp_mult_r_cfg_params.v:17: Cannot find include file: qlf_k6n10f/cells_sim.v\n`include "qlf_k6n10f/cells_sim.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params,data/full_repos/permissive/220229160/qlf_k6n10f/cells_sim.v\n             data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params,data/full_repos/permissive/220229160/qlf_k6n10f/cells_sim.v.v\n             data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params,data/full_repos/permissive/220229160/qlf_k6n10f/cells_sim.v.sv\n             qlf_k6n10f/cells_sim.v\n             qlf_k6n10f/cells_sim.v.v\n             qlf_k6n10f/cells_sim.v.sv\n             obj_dir/qlf_k6n10f/cells_sim.v\n             obj_dir/qlf_k6n10f/cells_sim.v.v\n             obj_dir/qlf_k6n10f/cells_sim.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params/sim_dsp_mult_r_cfg_params.v:24: Unsupported: Ignoring delay on this delayed statement.\n    always #0.5 clk <= ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params/sim_dsp_mult_r_cfg_params.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #1  rst <= 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params/sim_dsp_mult_r_cfg_params.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #2  rst <= 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params/sim_dsp_mult_r_cfg_params.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #1.5;\n        ^\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params/sim_dsp_mult_r_cfg_params.v:84: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile(`VCD_FILE);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params/sim_dsp_mult_r_cfg_params.v:84: Define or directive not defined: \'`VCD_FILE\'\n        $dumpfile(`VCD_FILE);\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params/sim_dsp_mult_r_cfg_params.v:85: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params/sim_dsp_mult_r_cfg_params.v:86: Unsupported or unknown PLI call: $finish_and_return\n        #100 $finish_and_return( (error_count == 0) ? 0 : -1 );\n             ^~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r_cfg_params/sim_dsp_mult_r_cfg_params.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish_and_return( (error_count == 0) ? 0 : -1 );\n        ^\n%Error: Exiting due to 5 error(s), 5 warning(s)\n'
module tb();


    reg clk;
    initial clk <= 1'b0;
    always #0.5 clk <= ~clk;


    reg rst;
    initial begin
            rst <= 1'b0;
        #1  rst <= 1'b1;
        #2  rst <= 1'b0;
    end


    reg signed [19:0] A;
    reg signed [17:0] B;
    reg signed [37:0] C;



    initial begin
        forever begin
            A = $random;
            B = $random;

            C <= A * B;
        #1.5;
        end
    end


    wire signed [37:0] Z;

    dsp_t1_sim_cfg_params # (
        .REGISTER_INPUTS    (1'h1),
        .OUTPUT_SELECT      (3'h0)
    ) uut (
        .a_i                (A),
        .b_i                (B),
        .unsigned_a_i       (1'h0),
        .unsigned_b_i       (1'h0),
        .feedback_i         (3'h0),
        .clock_i            (clk),
        .z_o                (Z)
    );


    reg [37:0] r_C;
    initial r_C <= 0;
    always @(posedge clk)
        r_C <= C;

    wire error = (Z !== r_C);


    integer error_count;
    initial error_count <= 0;
    always @(posedge clk) begin
        if (error) error_count <= error_count + 1;
    end


    initial begin
        $dumpfile(`VCD_FILE);
        $dumpvars(0, tb);
        #100 $finish_and_return( (error_count == 0) ? 0 : -1 );
    end

endmodule
module tb();



    reg clk;
    initial clk <= 1'b0;
    always #0.5 clk <= ~clk;


    reg rst;
    initial begin
            rst <= 1'b0;
        #1  rst <= 1'b1;
        #2  rst <= 1'b0;
    end


    reg signed [19:0] A;
    reg signed [17:0] B;
    reg signed [37:0] C;



    initial begin
        forever begin
            A = $random;
            B = $random;

            C <= A * B;
        #1.5;
        end
    end


    wire signed [37:0] Z;

    dsp_t1_sim_cfg_params # (
        .REGISTER_INPUTS    (1'h1),
        .OUTPUT_SELECT      (3'h0)
    ) uut (
        .a_i                (A),
        .b_i                (B),
        .unsigned_a_i       (1'h0),
        .unsigned_b_i       (1'h0),
        .feedback_i         (3'h0),
        .clock_i            (clk),
        .z_o                (Z)
    );


    reg [37:0] r_C;
    initial r_C <= 0;
    always @(posedge clk)
        r_C <= C;

    wire error = (Z !== r_C);


    integer error_count;
    initial error_count <= 0;
    always @(posedge clk) begin
        if (error) error_count <= error_count + 1;
    end


    initial begin
        $dumpfile(`VCD_FILE);
        $dumpvars(0, tb);
        #100 $finish_and_return( (error_count == 0) ? 0 : -1 );
    end

endmodule