data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/assign_deassign.v
'utf-8' codec can't decode byte 0xbe in position 480: invalid start byte
1: b'%Error: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/assign_deassign.v:45: Unsupported: Verilog 1995 deassign\n        deassign q;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/assign_deassign.v:46: Unsupported: Verilog 1995 deassign\n        deassign qbar;\n        ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module assign_deassign(q, qbar, d, clk, reset);


output q,qbar;
input d,clk,reset;
reg q, qbar;

always @(negedge clk)
begin
    q = d;
    qbar = ~d;
end

always @(reset)
    if(reset)
    begin
       assign q = 1'b0;
       assign qbar = 1'b1;
    end
    else
    begin

        deassign q;
        deassign qbar;
    end

endmodule
module assign_deassign(q, qbar, d, clk, reset);



output q,qbar;
input d,clk,reset;
reg q, qbar;

always @(negedge clk)
begin
    q = d;
    qbar = ~d;
end

always @(reset)
    if(reset)
    begin
       assign q = 1'b0;
       assign qbar = 1'b1;
    end
    else
    begin

        deassign q;
        deassign qbar;
    end

endmodule