data/full_repos/permissive/174155074/sequential-logic/shifters/left-shift-register/left-shift-register.v
1: b"%Error: data/full_repos/permissive/174155074/sequential-logic/shifters/left-shift-register/left-shift-register.v:9: Duplicate declaration of signal: 'out'\n                                                                                                                  : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg [3:0] out;\n          ^~~\n        data/full_repos/permissive/174155074/sequential-logic/shifters/left-shift-register/left-shift-register.v:6: ... Location of original declaration\n    output [3:0] out             \n                 ^~~\n%Error: Exiting due to 1 error(s)\n"
module left_shift_register(
    input        clk,
    input        rst,
    input        d,
    output [3:0] out
);

reg [3:0] out;

always @ (posedge clk) begin
    if (rst) begin
        out <= 4'b0000;      
    end else begin
        out <= {out[2:0], d};
    end
end

endmodule
module left_shift_register(
    input        clk,
    input        rst,
    input        d,
    output [3:0] out
);


reg [3:0] out;

always @ (posedge clk) begin
    if (rst) begin
        out <= 4'b0000;      
    end else begin
        out <= {out[2:0], d};
    end
end

endmodule