data/full_repos/permissive/115141190/LCD_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/115141190/LCD_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #500 reset = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115141190/LCD_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk <= ~clk;\n    ^\n%Error: data/full_repos/permissive/115141190/LCD_tb.v:8: Cannot find file containing module: \'LCD_controller\'\nLCD_controller LCD_controller (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115141190,data/full_repos/permissive/115141190/LCD_controller\n             data/full_repos/permissive/115141190,data/full_repos/permissive/115141190/LCD_controller.v\n             data/full_repos/permissive/115141190,data/full_repos/permissive/115141190/LCD_controller.sv\n             LCD_controller\n             LCD_controller.v\n             LCD_controller.sv\n             obj_dir/LCD_controller\n             obj_dir/LCD_controller.v\n             obj_dir/LCD_controller.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module LCD_tb ();

reg clk, reset;
wire LCD_E;
wire LCD_RS, LCD_RW;
wire SF_D11, SF_D10, SF_D9, SF_D8;

LCD_controller LCD_controller (
    .clk        (clk),
    .reset      (reset),
    .LCD_E      (LCD_E),
    .LCD_RS     (LCD_RS),
    .LCD_RW     (LCD_RW),
    .SF_D11     (SF_D11),
    .SF_D10     (SF_D10),
    .SF_D9     (SF_D9),
    .SF_D8     (SF_D8)
);

initial begin
    clk = 0;
    reset = 1;
    #500 reset = 0;
end

always begin
    #10 clk <= ~clk;
end

endmodule
module LCD_tb ();


reg clk, reset;
wire LCD_E;
wire LCD_RS, LCD_RW;
wire SF_D11, SF_D10, SF_D9, SF_D8;

LCD_controller LCD_controller (
    .clk        (clk),
    .reset      (reset),
    .LCD_E      (LCD_E),
    .LCD_RS     (LCD_RS),
    .LCD_RW     (LCD_RW),
    .SF_D11     (SF_D11),
    .SF_D10     (SF_D10),
    .SF_D9     (SF_D9),
    .SF_D8     (SF_D8)
);

initial begin
    clk = 0;
    reset = 1;
    #500 reset = 0;
end

always begin
    #10 clk <= ~clk;
end

endmodule