data/full_repos/permissive/146246005/Register- D Flip-Flop- SR Latch/MUX.v
1: b'%Error: Cannot find file containing module: D\n        ... Looked in:\n             data/full_repos/permissive/146246005/Register-/D\n             data/full_repos/permissive/146246005/Register-/D.v\n             data/full_repos/permissive/146246005/Register-/D.sv\n             D\n             D.v\n             D.sv\n             obj_dir/D\n             obj_dir/D.v\n             obj_dir/D.sv\n%Error: Cannot find file containing module: Flip-Flop-\n%Error: Cannot find file containing module: SR\n%Error: Cannot find file containing module: Latch,data/full_repos/permissive/146246005\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/Register-\n%Error: Cannot find file containing module: Latch/MUX.v\n%Error: Exiting due to 6 error(s)\n'
module MUX(OUT, A, B, SEL);
	
	parameter NOT1in = 1,
		  NOT1out = 0.5,
		  AND1in = 2,
		  AND1out = 0.8,
		  AND2in = 2,
		  AND2out = 0.8,
		  OR1in = 2,
		  OR1out = 0.5;

    input A, B, SEL;
    output OUT;


    wire A1, B1, SEL_N;


    not #(NOT1in+NOT1out) NOT1(SEL_N, SEL);
    and #(AND1in+AND1out) AND1(A1, A, SEL_N);
    and #(AND2in+AND2out) AND2(B1, B, SEL);
    or #(OR1in+OR1out) OR1(OUT, A1, B1);
endmodule
module MUX(OUT, A, B, SEL);

	
	parameter NOT1in = 1,
		  NOT1out = 0.5,
		  AND1in = 2,
		  AND1out = 0.8,
		  AND2in = 2,
		  AND2out = 0.8,
		  OR1in = 2,
		  OR1out = 0.5;

    input A, B, SEL;
    output OUT;


    wire A1, B1, SEL_N;


    not #(NOT1in+NOT1out) NOT1(SEL_N, SEL);
    and #(AND1in+AND1out) AND1(A1, A, SEL_N);
    and #(AND2in+AND2out) AND2(B1, B, SEL);
    or #(OR1in+OR1out) OR1(OUT, A1, B1);
endmodule