data/full_repos/permissive/143278/ivltests/concat_zero_wid_fail2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/concat_zero_wid_fail2.v:9: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (foo !== 4\'b1001) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

   reg [2:0] bar = 1;
   wire [3:0] foo;

   assign foo = { 1'b1, 0 ? 3'd0 : bar[2:0] };

   initial begin
      #1 if (foo !== 4'b1001) begin
	 $display("FAILED  bar=%b, foo=%b", bar, foo);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module top;


   reg [2:0] bar = 1;
   wire [3:0] foo;

   assign foo = { 1'b1, 0 ? 3'd0 : bar[2:0] };

   initial begin
      #1 if (foo !== 4'b1001) begin
	 $display("FAILED  bar=%b, foo=%b", bar, foo);
	 $finish;
      end

      $display("PASSED");
   end

endmodule