data/full_repos/permissive/127511545/src/JRControlUnit.v
data/verilator_xmls/bff7c22f-2375-403b-b43c-a48d0a13a442.xml
module JRControlUnit(JRControl, ALUOperation, Function);

	output JRControl;
	input[1:0] ALUOperation;
	input[5:0] Function;
	wire[7:0] Test;
	reg JRControl;

	assign Test = {ALUOperation, Function};
	always @(Test)
		case (Test)
			8'b10001000 : JRControl = 1'b1; 
			default: JRControl = 1'b0;
		endcase

endmodule
module JRControlUnit(JRControl, ALUOperation, Function);


	output JRControl;
	input[1:0] ALUOperation;
	input[5:0] Function;
	wire[7:0] Test;
	reg JRControl;

	assign Test = {ALUOperation, Function};
	always @(Test)
		case (Test)
			8'b10001000 : JRControl = 1'b1; 
			default: JRControl = 1'b0;
		endcase

endmodule