data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v
 line:318: before: "$"
1: b'%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:4: Cannot find include file: pulseGenerator.v\n`include "pulseGenerator.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/pulseGenerator,data/full_repos/permissive/200314387/pulseGenerator.v\n             data/full_repos/permissive/200314387/verilog/pulseGenerator,data/full_repos/permissive/200314387/pulseGenerator.v.v\n             data/full_repos/permissive/200314387/verilog/pulseGenerator,data/full_repos/permissive/200314387/pulseGenerator.v.sv\n             pulseGenerator.v\n             pulseGenerator.v.v\n             pulseGenerator.v.sv\n             obj_dir/pulseGenerator.v\n             obj_dir/pulseGenerator.v.v\n             obj_dir/pulseGenerator.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:5: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:21: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:22: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, gen);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #30;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:38: Define or directive not defined: \'`equals\'\n        `equals(pulse , 1\'b1, "t2");\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:38: syntax error, unexpected \',\'\n        `equals(pulse , 1\'b1, "t2");\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #11;\n        ^\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:43: Define or directive not defined: \'`equals\'\n        `equals(pulse , 1\'b0, "t4");   \n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:43: syntax error, unexpected \',\'\n        `equals(pulse , 1\'b0, "t4");   \n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #30;  \n        ^\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:46: Define or directive not defined: \'`equals\'\n        `equals(pulse , 1\'b1, "t6");\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:46: syntax error, unexpected \',\'\n        `equals(pulse , 1\'b1, "t6");\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #10;  \n        ^\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:52: Define or directive not defined: \'`equals\'\n        `equals(pulse , 1\'b1, "t2");\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:52: syntax error, unexpected \',\'\n        `equals(pulse , 1\'b1, "t2");\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #11;\n        ^\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:57: Define or directive not defined: \'`equals\'\n        `equals(pulse , 1\'b1, "t4");   \n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:57: syntax error, unexpected \',\'\n        `equals(pulse , 1\'b1, "t4");   \n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #30;  \n        ^\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:60: Define or directive not defined: \'`equals\'\n        `equals(pulse , 1\'b1, "t6");\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:60: syntax error, unexpected \',\'\n        `equals(pulse , 1\'b1, "t6");\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/pulseGenerator/test.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #400 $finish;\n        ^\n%Error: Exiting due to 16 error(s), 7 warning(s)\n'
module icarus_tb();
    
	logic clk;
	logic clk_en;

	wire pulse;

    
	pulseGenerator gen( clk, clk_en, pulse);
    
    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0, gen);
        
        $display ("");
        $display ($time, "   clk  clk_en pulse");
`ifndef verilator
        $monitor ($time, "   %b    %b      %b", clk, clk_en, pulse);
`endif 

    end

    initial begin
	clk=0;


	clk_en = 1;
        #30;
        `equals(pulse , 1'b1, "t2");


	clk=1;
        #11;
        `equals(pulse , 1'b0, "t4");

        #30;
        `equals(pulse , 1'b1, "t6");
	clk=0;
        

	clk_en = 0;
        #10;
        `equals(pulse , 1'b1, "t2");


	clk=1;
        #11;
        `equals(pulse , 1'b1, "t4");

        #30;
        `equals(pulse , 1'b1, "t6");
        
        #400 $finish;
    end

endmodule
module icarus_tb();

    
	logic clk;
	logic clk_en;

	wire pulse;

    
	pulseGenerator gen( clk, clk_en, pulse);
    
    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0, gen);
        
        $display ("");
        $display ($time, "   clk  clk_en pulse");
`ifndef verilator
        $monitor ($time, "   %b    %b      %b", clk, clk_en, pulse);
`endif 

    end

    initial begin
	clk=0;


	clk_en = 1;
        #30;
        `equals(pulse , 1'b1, "t2");


	clk=1;
        #11;
        `equals(pulse , 1'b0, "t4");

        #30;
        `equals(pulse , 1'b1, "t6");
	clk=0;
        

	clk_en = 0;
        #10;
        `equals(pulse , 1'b1, "t2");


	clk=1;
        #11;
        `equals(pulse , 1'b1, "t4");

        #30;
        `equals(pulse , 1'b1, "t6");
        
        #400 $finish;
    end

endmodule