data/full_repos/permissive/217937330/bch_encoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/217937330/bch_encoder.v:30: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'191\'h6ce707e26b6f9977\' generates 191 bits.\n                                                                     : ... In instance bch_encoder\n    wire [n-k-1:0]g=191\'b0110110011100111000001111110001001101011011011111001100101110111;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module bch_encoder(rst,clk,msg,bch_dataout);
    parameter n = 255;
    parameter k=191;
    input rst;
    input clk;
    input [k-1:0]msg;

    wire [n-k-1:0]g=191'b0110110011100111000001111110001001101011011011111001100101110111;
    output reg [n-1:0] bch_dataout;
    reg [n-k-1:0] D_register;
    reg ui;
    integer i,m,t;
    
    
    
    initial
    begin
        D_register=0;
        bch_dataout=0;
        i=k-1;
    end
    
    
    
    always@(posedge clk)
    begin
        if(rst)
        begin 
            D_register<=0;
            bch_dataout<=0;
            i<=k-1;
        end

        else if (i>-1)
        begin
            ui=msg[i];
            for (t=n-k-1;t>0;t=t-1)
            begin
                D_register[t] <= ( (D_register[n-k-1]^ui)&g[t])^D_register[t-1];
            end
            D_register[0] <= D_register[n-k-1]^ui;
            bch_dataout[i+64] <= ui;
            i=i-1;
        end
        else if(i==-1)
             bch_dataout[n-k-1:0]<= D_register[n-k-1:0];
    end    
endmodule
module bch_encoder(rst,clk,msg,bch_dataout);

    parameter n = 255;
    parameter k=191;
    input rst;
    input clk;
    input [k-1:0]msg;

    wire [n-k-1:0]g=191'b0110110011100111000001111110001001101011011011111001100101110111;
    output reg [n-1:0] bch_dataout;
    reg [n-k-1:0] D_register;
    reg ui;
    integer i,m,t;
    
    
    
    initial
    begin
        D_register=0;
        bch_dataout=0;
        i=k-1;
    end
    
    
    
    always@(posedge clk)
    begin
        if(rst)
        begin 
            D_register<=0;
            bch_dataout<=0;
            i<=k-1;
        end

        else if (i>-1)
        begin
            ui=msg[i];
            for (t=n-k-1;t>0;t=t-1)
            begin
                D_register[t] <= ( (D_register[n-k-1]^ui)&g[t])^D_register[t-1];
            end
            D_register[0] <= D_register[n-k-1]^ui;
            bch_dataout[i+64] <= ui;
            i=i-1;
        end
        else if(i==-1)
             bch_dataout[n-k-1:0]<= D_register[n-k-1:0];
    end    
endmodule