data/full_repos/permissive/207610706/src/uart/uart_top.v
1: b'%Error: data/full_repos/permissive/207610706/src/uart/uart_top.v:135: Cannot find include file: uart_defines.v\n`include "uart_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207610706/src/uart,data/full_repos/permissive/207610706/uart_defines.v\n             data/full_repos/permissive/207610706/src/uart,data/full_repos/permissive/207610706/uart_defines.v.v\n             data/full_repos/permissive/207610706/src/uart,data/full_repos/permissive/207610706/uart_defines.v.sv\n             uart_defines.v\n             uart_defines.v.v\n             uart_defines.v.sv\n             obj_dir/uart_defines.v\n             obj_dir/uart_defines.v.v\n             obj_dir/uart_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module uart_top	(
	wb_clk_i, 
	

	wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
	int_o,



	stx_pad_o, srx_pad_i,


	rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
`ifdef UART_HAS_BAUDRATE_OUTPUT
	, baud_o
`endif
	);
parameter SIM = 0;
parameter debug = 0;

input 								 wb_clk_i;


input 								 wb_rst_i;
input [2:0] 	 wb_adr_i;
input [7:0] 	 wb_dat_i;
output [7:0] 	 wb_dat_o;
input 								 wb_we_i;
input 								 wb_stb_i;
input 								 wb_cyc_i;
input [3:0]							 wb_sel_i;
output 								 wb_ack_o;
output 								 int_o;


input 								 srx_pad_i;
output 								 stx_pad_o;
output 								 rts_pad_o;
input 								 cts_pad_i;
output 								 dtr_pad_o;
input 								 dsr_pad_i;
input 								 ri_pad_i;
input 								 dcd_pad_i;


`ifdef UART_HAS_BAUDRATE_OUTPUT
output	baud_o;
`endif


wire 									 stx_pad_o;
wire 									 rts_pad_o;
wire 									 dtr_pad_o;

wire [2:0] 	 wb_adr_i;
wire [7:0] 	 wb_dat_i;
wire [7:0] 	 wb_dat_o;

wire [7:0] 							 wb_dat8_i;
wire [7:0] 							 wb_dat8_o;
wire [31:0] 						 wb_dat32_o;
wire [3:0] 							 wb_sel_i;
wire [2:0] 	 wb_adr_int;
wire 									 we_o;
wire		          	     re_o;





uart_wb		wb_interface(
		.clk(		wb_clk_i		),
		.wb_rst_i(	wb_rst_i	),
	.wb_dat_i(wb_dat_i),
	.wb_dat_o(wb_dat_o),
	.wb_dat8_i(wb_dat8_i),
	.wb_dat8_o(wb_dat8_o),
	 .wb_dat32_o(32'b0),								 
	 .wb_sel_i(4'b0),
		.wb_we_i(	wb_we_i		),
		.wb_stb_i(	wb_stb_i	),
		.wb_cyc_i(	wb_cyc_i	),
		.wb_ack_o(	wb_ack_o	),
	.wb_adr_i(wb_adr_i),
	.wb_adr_int(wb_adr_int),
		.we_o(		we_o		),
		.re_o(re_o)
		);


uart_regs #(.SIM (SIM))	regs(
	.clk(		wb_clk_i		),
	.wb_rst_i(	wb_rst_i	),
	.wb_addr_i(	wb_adr_int	),
	.wb_dat_i(	wb_dat8_i	),
	.wb_dat_o(	wb_dat8_o	),
	.wb_we_i(	we_o		),
   .wb_re_i(re_o),
	.modem_inputs(	{cts_pad_i, dsr_pad_i,
	ri_pad_i,  dcd_pad_i}	),
	.stx_pad_o(		stx_pad_o		),
	.srx_pad_i(		srx_pad_i		),
	.rts_pad_o(		rts_pad_o		),
	.dtr_pad_o(		dtr_pad_o		),
	.int_o(		int_o		)
`ifdef UART_HAS_BAUDRATE_OUTPUT
	, .baud_o(baud_o)
`endif

);

initial
begin
   if(debug) begin
	`ifdef UART_HAS_BAUDRATE_OUTPUT
		$display("(%m) UART INFO: Has baudrate output\n");
	`else
		$display("(%m) UART INFO: Doesn't have baudrate output\n");
	`endif
   end
end

endmodule
module uart_top	(
	wb_clk_i, 
	

	wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
	int_o,



	stx_pad_o, srx_pad_i,


	rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
`ifdef UART_HAS_BAUDRATE_OUTPUT
	, baud_o
`endif
	);

parameter SIM = 0;
parameter debug = 0;

input 								 wb_clk_i;


input 								 wb_rst_i;
input [2:0] 	 wb_adr_i;
input [7:0] 	 wb_dat_i;
output [7:0] 	 wb_dat_o;
input 								 wb_we_i;
input 								 wb_stb_i;
input 								 wb_cyc_i;
input [3:0]							 wb_sel_i;
output 								 wb_ack_o;
output 								 int_o;


input 								 srx_pad_i;
output 								 stx_pad_o;
output 								 rts_pad_o;
input 								 cts_pad_i;
output 								 dtr_pad_o;
input 								 dsr_pad_i;
input 								 ri_pad_i;
input 								 dcd_pad_i;


`ifdef UART_HAS_BAUDRATE_OUTPUT
output	baud_o;
`endif


wire 									 stx_pad_o;
wire 									 rts_pad_o;
wire 									 dtr_pad_o;

wire [2:0] 	 wb_adr_i;
wire [7:0] 	 wb_dat_i;
wire [7:0] 	 wb_dat_o;

wire [7:0] 							 wb_dat8_i;
wire [7:0] 							 wb_dat8_o;
wire [31:0] 						 wb_dat32_o;
wire [3:0] 							 wb_sel_i;
wire [2:0] 	 wb_adr_int;
wire 									 we_o;
wire		          	     re_o;





uart_wb		wb_interface(
		.clk(		wb_clk_i		),
		.wb_rst_i(	wb_rst_i	),
	.wb_dat_i(wb_dat_i),
	.wb_dat_o(wb_dat_o),
	.wb_dat8_i(wb_dat8_i),
	.wb_dat8_o(wb_dat8_o),
	 .wb_dat32_o(32'b0),								 
	 .wb_sel_i(4'b0),
		.wb_we_i(	wb_we_i		),
		.wb_stb_i(	wb_stb_i	),
		.wb_cyc_i(	wb_cyc_i	),
		.wb_ack_o(	wb_ack_o	),
	.wb_adr_i(wb_adr_i),
	.wb_adr_int(wb_adr_int),
		.we_o(		we_o		),
		.re_o(re_o)
		);


uart_regs #(.SIM (SIM))	regs(
	.clk(		wb_clk_i		),
	.wb_rst_i(	wb_rst_i	),
	.wb_addr_i(	wb_adr_int	),
	.wb_dat_i(	wb_dat8_i	),
	.wb_dat_o(	wb_dat8_o	),
	.wb_we_i(	we_o		),
   .wb_re_i(re_o),
	.modem_inputs(	{cts_pad_i, dsr_pad_i,
	ri_pad_i,  dcd_pad_i}	),
	.stx_pad_o(		stx_pad_o		),
	.srx_pad_i(		srx_pad_i		),
	.rts_pad_o(		rts_pad_o		),
	.dtr_pad_o(		dtr_pad_o		),
	.int_o(		int_o		)
`ifdef UART_HAS_BAUDRATE_OUTPUT
	, .baud_o(baud_o)
`endif

);

initial
begin
   if(debug) begin
	`ifdef UART_HAS_BAUDRATE_OUTPUT
		$display("(%m) UART INFO: Has baudrate output\n");
	`else
		$display("(%m) UART INFO: Doesn't have baudrate output\n");
	`endif
   end
end

endmodule