data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic/sum_bits.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic/sum_bits.v:24: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module sum_bits (clk, en, bits, sum);
`include "util.vh"
  parameter  InBits  = 32;

  localparam OutBits = clog2(InBits + 1);

  input               clk;
  input               en;

  input [InBits-1:0]  bits;

  output[OutBits-1:0] sum;



  function automatic [2:0] sum_bits_4(input [3:0] x);
    reg [2:0] r;
    begin
      case (x)
        4'b0000: r=0;
        4'b0001: r=1;
        4'b0010: r=1;
        4'b0011: r=2;
        4'b0100: r=1;
        4'b0101: r=2;
        4'b0110: r=2;
        4'b0111: r=3;
        4'b1000: r=1;
        4'b1001: r=2;
        4'b1010: r=2;
        4'b1011: r=3;
        4'b1100: r=2;
        4'b1101: r=3;
        4'b1110: r=3;
        4'b1111: r=4;
      endcase
      sum_bits_4 = r;
    end
  endfunction

  localparam AdderStages = clog2(InBits) - 2;


  reg [3*InBits/4-1:0] lut_sum;
  integer              i;
  always @(posedge clk) begin
    if (en) begin
      for (i=0; i < InBits/4; i=i+1) begin
        lut_sum[3*i +: 3] <= sum_bits_4(bits[i*4 +: 4]);
      end
    end
  end


  generate
    if (AdderStages < 1) begin: no_tree
      assign sum = lut_sum;
    end else begin: use_tree
      adder_tree #(
        .DataBits (3),
        .NumWords (InBits/4))
      add_tree (
        .clk       (clk),
        .en        (en),
        .din_data  (lut_sum),
        .dout_data (sum));
    end
  endgenerate

endmodule
module sum_bits (clk, en, bits, sum);

`include "util.vh"
  parameter  InBits  = 32;

  localparam OutBits = clog2(InBits + 1);

  input               clk;
  input               en;

  input [InBits-1:0]  bits;

  output[OutBits-1:0] sum;



  function automatic [2:0] sum_bits_4(input [3:0] x);
    reg [2:0] r;
    begin
      case (x)
        4'b0000: r=0;
        4'b0001: r=1;
        4'b0010: r=1;
        4'b0011: r=2;
        4'b0100: r=1;
        4'b0101: r=2;
        4'b0110: r=2;
        4'b0111: r=3;
        4'b1000: r=1;
        4'b1001: r=2;
        4'b1010: r=2;
        4'b1011: r=3;
        4'b1100: r=2;
        4'b1101: r=3;
        4'b1110: r=3;
        4'b1111: r=4;
      endcase
      sum_bits_4 = r;
    end
  endfunction

  localparam AdderStages = clog2(InBits) - 2;


  reg [3*InBits/4-1:0] lut_sum;
  integer              i;
  always @(posedge clk) begin
    if (en) begin
      for (i=0; i < InBits/4; i=i+1) begin
        lut_sum[3*i +: 3] <= sum_bits_4(bits[i*4 +: 4]);
      end
    end
  end


  generate
    if (AdderStages < 1) begin: no_tree
      assign sum = lut_sum;
    end else begin: use_tree
      adder_tree #(
        .DataBits (3),
        .NumWords (InBits/4))
      add_tree (
        .clk       (clk),
        .en        (en),
        .din_data  (lut_sum),
        .dout_data (sum));
    end
  endgenerate

endmodule