data/full_repos/permissive/206842334/testbenches/iter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/iter_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/iter_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/iter_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #period\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206842334/testbenches/iter_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #period\n    ^\n%Error: data/full_repos/permissive/206842334/testbenches/iter_tb.v:36: Cannot find file containing module: \'iterator\'\n    iterator iter(clk, en_ctrl, reset, i, j, k, l, m, n, en_sum, en_save, finish, in_row, in_col);\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/iterator\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/iterator.v\n             data/full_repos/permissive/206842334/testbenches,data/full_repos/permissive/206842334/iterator.sv\n             iterator\n             iterator.v\n             iterator.sv\n             obj_dir/iterator\n             obj_dir/iterator.v\n             obj_dir/iterator.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iter_tb;

    localparam period = 20;
    reg clk, reset, en_ctrl;
    wire en_sum, en_save, finish;
    wire signed [7:0] in_row, in_col;

    always begin
        clk = 1'b1;
        #period;
        clk = 1'b0;
        #period;
    end

    initial begin
    reset = 1;
    #period
    reset = 0;
    #period
    en_ctrl = 1;
    end

    always @(posedge clk) begin
        if (finish) begin
            $stop;
        end
    end

    wire [7:0] i;
	wire [7:0] j;
	wire [7:0] k;
	wire [7:0] m;
	wire [7:0] n;
    wire [1:0] l;

    iterator iter(clk, en_ctrl, reset, i, j, k, l, m, n, en_sum, en_save, finish, in_row, in_col);

endmodule
module iter_tb;


    localparam period = 20;
    reg clk, reset, en_ctrl;
    wire en_sum, en_save, finish;
    wire signed [7:0] in_row, in_col;

    always begin
        clk = 1'b1;
        #period;
        clk = 1'b0;
        #period;
    end

    initial begin
    reset = 1;
    #period
    reset = 0;
    #period
    en_ctrl = 1;
    end

    always @(posedge clk) begin
        if (finish) begin
            $stop;
        end
    end

    wire [7:0] i;
	wire [7:0] j;
	wire [7:0] k;
	wire [7:0] m;
	wire [7:0] n;
    wire [1:0] l;

    iterator iter(clk, en_ctrl, reset, i, j, k, l, m, n, en_sum, en_save, finish, in_row, in_col);

endmodule