data/full_repos/permissive/143278/ivltests/pr1693890.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1693890.v:7: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (w !== 1\'b1) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/143278/ivltests/pr1693890.v:4: Signal definition not found, creating implicitly: \'w\'\n   assign  w = 1\'b1;\n           ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ();


   assign  w = 1'b1;

   initial begin
      #1 if (w !== 1'b1) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module test ();



   assign  w = 1'b1;

   initial begin
      #1 if (w !== 1'b1) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
   end

endmodule