data/full_repos/permissive/210918583/rtl/bus_top.v
1: b"%Error: data/full_repos/permissive/210918583/rtl/bus_top.v:124: Cannot find file containing module: 'bus_delay'\nbus_delay DELAY(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210918583/rtl,data/full_repos/permissive/210918583/bus_delay\n             data/full_repos/permissive/210918583/rtl,data/full_repos/permissive/210918583/bus_delay.v\n             data/full_repos/permissive/210918583/rtl,data/full_repos/permissive/210918583/bus_delay.sv\n             bus_delay\n             bus_delay.v\n             bus_delay.sv\n             obj_dir/bus_delay\n             obj_dir/bus_delay.v\n             obj_dir/bus_delay.sv\n%Error: data/full_repos/permissive/210918583/rtl/bus_top.v:131: Cannot find file containing module: 'm6800'\nm6800 M6800BUS(\n^~~~~\n%Error: data/full_repos/permissive/210918583/rtl/bus_top.v:142: Cannot find file containing module: 'ata'\nata ATA (\n^~~\n%Error: Exiting due to 3 error(s)\n"
module bus_top(

           input 	CLKCPU,
           input 	CLK7M,

           input 	BG20,
           input 	AS20,
           input 	DS20,
           input 	RW20,
           output 	RW,


           input [2:0] 	FC,
           input [1:0] 	SIZ,

           input [23:0] A,

           input 	BGACK,
           input 	VPA,
           input 	DTACK,

           output 	BG,
           output 	LDS,
           output 	UDS,
           output 	VMA,
           output 	E,
           output 	AS,
           output 	BERR,

           input 	IDEWAIT,
           input 	INTCYCLE,
           input    SLOWCYCLE,
           input    INT2,
           output   BUSEN,

           output   DSACK1,
           output 	AVEC,
           output 	CPCS,
           input 	CPSENSE,

           output [2:1] IPL,

           output 	IOR,
           output 	IOW,
           output [1:0] IDECS
       );




reg AS20DLY = 1'b1;
reg BUSEN_D = 1'b1;

reg BG_INT;
reg BGACK_INT;

reg RW_INT = 1'b1;
reg AS_INT = 1'b1;
reg AS_INTD = 1'b1;

reg LDS_INT = 1'b1;
reg UDS_INT = 1'b1;

wire CPUSPACE = &FC;

wire GAYLE_IDE;
wire DTACK_IDE;

wire FPUOP = CPUSPACE & ({A[19:16]} === {4'b0010});
wire BKPT = CPUSPACE & ({A[19:16]} === {4'b0000});
wire IACK = CPUSPACE & ({A[19:16]} === {4'b1111});
wire BUS_BUSY = BGACK & BGACK_INT;
wire HIGHZ = ~BUS_BUSY | ~INTCYCLE | ~GAYLE_IDE;

`ifndef ATARI
reg INT2_ASSERT = 1'b0;
reg INT2_INT = 1'b0;
reg INT2_IACK_INT = 1'b0;
wire INT2_IACK = IACK & ({A[3:1]} == 3'b010) & ~AS20;
`endif

wire DSACK1_SYNC;
wire VMA_SYNC;

reg DTACK_LATCHED;
reg DTACK_S6;
reg DTACK_S7;
wire DTACK_S7D;
reg [1:0] DSACK_INT;

bus_delay DELAY(
              .AS     ( AS        ),
              .DTACK  ( DTACK_S7  ),
              .OUT    ( DTACK_S7D )
          );


m6800 M6800BUS(
          .CLK7M	( CLK7M			),
          .FC       ( FC            ),
          .AS20	    ( AS20		    ),
          .VPA		( VPA		    ),
          .VMA		( VMA_SYNC		),
          .E		( E				),
          .DSACK1	( DSACK1_SYNC 	)
      );


ata ATA (

        .CLK	( CLKCPU	),
        .AS	( AS20	),
        .RW	( RW20	),
        .A		( A		),
        .WAIT	( IDEWAIT),

        .IDECS( IDECS	),
        .IOR	( IOR		),
        .IOW	( IOW		),
        .DTACK( DTACK_IDE	),
        .ACCESS( GAYLE_IDE )

    );

reg CPCS_INT = 1'b1;
reg AVEC_INT = 1'b1;
reg CANSTART = 1'b1;




always @(negedge CLK7M or negedge AS) begin

    if (AS == 1'b0) begin

        CANSTART <= 1'b0;

    end else begin

        CANSTART <= BUS_BUSY;

    end

end

always @(posedge CLKCPU) begin

    BGACK_INT <= BGACK;

end

wire AS_AMIGA = AS20DLY | FPUOP | ~GAYLE_IDE | ~INTCYCLE | ~BUS_BUSY | (~CANSTART & AS_INT);

always @(posedge CLK7M or posedge AS20) begin

    if (AS20 == 1'b1) begin

        AS_INT <= 1'b1;
        AS_INTD <= 1'b1;
        
        RW_INT <= 1'b1;

        LDS_INT <= 1'b1;
        UDS_INT <= 1'b1;

        DTACK_S6 <= 1'b1;

    end else begin



        AS_INT <= AS_AMIGA;
        AS_INTD <= AS_INT;

        RW_INT <= RW20 | AS_AMIGA;

        if (RW20 == 1'b1) begin


            UDS_INT <= DS20 | A[0] | AS_AMIGA;
            LDS_INT <= DS20 | ({A[0], SIZ[1:0]} == 3'b001) | AS_AMIGA;

        end else begin


            UDS_INT <= DS20 | AS_INT | A[0] | AS_AMIGA;
            LDS_INT <= DS20 | AS_INT  | ({A[0], SIZ[1:0]} == 3'b001) | AS_AMIGA;

        end

        DTACK_S6 <= DTACK_LATCHED;

    end

end

always @(posedge CLKCPU or posedge BG20) begin

    if (BG20 == 1'b1) begin

        BG_INT <= 1'b1;

    end else begin 

        if (AS20 == AS_INT) begin

            BG_INT <= BG20;

        end 

    end

end


always @(negedge CLK7M or posedge AS20) begin

    if (AS20 == 1'b1) begin

        DTACK_LATCHED <= 1'b1;
        DTACK_S7 <= 1'b1;
        
    end else begin



        DTACK_LATCHED <= AS_INTD | DTACK;
        DTACK_S7 <= DTACK_S6;

    end

end

always @(posedge CLKCPU or posedge AS20) begin

    if (AS20 == 1'b1) begin

        DSACK_INT <= 2'b11;

    end else begin

        DSACK_INT <= {DSACK_INT[0], DTACK_S7D};
    
    end

end


always @(posedge CLKCPU or posedge AS20) begin

    if (AS20 == 1'b1) begin

        AS20DLY <= 1'b1;
        CPCS_INT <= 1'b1;
        AVEC_INT <= 1'b1;

    end else begin


        AS20DLY <= AS20 | FPUOP;
        CPCS_INT <= ~FPUOP | AS20;
        AVEC_INT <= ~IACK | VPA;
        
    end

end

`ifndef ATARI

always @(posedge CLKCPU) begin


    BUSEN_D <= ~INTCYCLE | AS_INT;
    INT2_INT <= INT2;
    INT2_IACK_INT <= INT2_IACK;

end

always @(negedge INT2_INT, posedge INT2_IACK_INT) begin 

    if (INT2_IACK_INT == 1'b1) begin 

        INT2_ASSERT <= 1'b0;

    end else begin 

        INT2_ASSERT <= 1'b1;

    end

end

`else

always @(posedge CLKCPU) begin


    BUSEN_D <= ~INTCYCLE | AS_INT;
end

`endif


wire VMA_INT = VMA_SYNC;

assign RW =   HIGHZ ? 1'bz : RW_INT;
assign AS =   HIGHZ ? 1'bz : AS_INT;
assign UDS =  HIGHZ ? 1'bz : UDS_INT;
assign LDS =  HIGHZ ? 1'bz : LDS_INT;
assign VMA =  HIGHZ ? 1'bz : VMA_INT;

assign DSACK1 = FPUOP | (~IDEWAIT | DSACK_INT[0]) & DSACK1_SYNC & DTACK_IDE & SLOWCYCLE;

assign BG = BG_INT ? 1'bz : 1'b0;
assign AVEC = AVEC_INT;

assign BERR = (CPCS_INT | ~CPSENSE) ? 1'bz : 1'b0;
assign CPCS = CPCS_INT;
assign BUSEN = BUSEN_D;

`ifndef ATARI
assign IPL[2:1] = INT2_ASSERT ? {2'b10} : {2'bzz};
`else
assign IPL[2:1] = {2'bzz};
`endif

endmodule
module bus_top(

           input 	CLKCPU,
           input 	CLK7M,

           input 	BG20,
           input 	AS20,
           input 	DS20,
           input 	RW20,
           output 	RW,


           input [2:0] 	FC,
           input [1:0] 	SIZ,

           input [23:0] A,

           input 	BGACK,
           input 	VPA,
           input 	DTACK,

           output 	BG,
           output 	LDS,
           output 	UDS,
           output 	VMA,
           output 	E,
           output 	AS,
           output 	BERR,

           input 	IDEWAIT,
           input 	INTCYCLE,
           input    SLOWCYCLE,
           input    INT2,
           output   BUSEN,

           output   DSACK1,
           output 	AVEC,
           output 	CPCS,
           input 	CPSENSE,

           output [2:1] IPL,

           output 	IOR,
           output 	IOW,
           output [1:0] IDECS
       );





reg AS20DLY = 1'b1;
reg BUSEN_D = 1'b1;

reg BG_INT;
reg BGACK_INT;

reg RW_INT = 1'b1;
reg AS_INT = 1'b1;
reg AS_INTD = 1'b1;

reg LDS_INT = 1'b1;
reg UDS_INT = 1'b1;

wire CPUSPACE = &FC;

wire GAYLE_IDE;
wire DTACK_IDE;

wire FPUOP = CPUSPACE & ({A[19:16]} === {4'b0010});
wire BKPT = CPUSPACE & ({A[19:16]} === {4'b0000});
wire IACK = CPUSPACE & ({A[19:16]} === {4'b1111});
wire BUS_BUSY = BGACK & BGACK_INT;
wire HIGHZ = ~BUS_BUSY | ~INTCYCLE | ~GAYLE_IDE;

`ifndef ATARI
reg INT2_ASSERT = 1'b0;
reg INT2_INT = 1'b0;
reg INT2_IACK_INT = 1'b0;
wire INT2_IACK = IACK & ({A[3:1]} == 3'b010) & ~AS20;
`endif

wire DSACK1_SYNC;
wire VMA_SYNC;

reg DTACK_LATCHED;
reg DTACK_S6;
reg DTACK_S7;
wire DTACK_S7D;
reg [1:0] DSACK_INT;

bus_delay DELAY(
              .AS     ( AS        ),
              .DTACK  ( DTACK_S7  ),
              .OUT    ( DTACK_S7D )
          );


m6800 M6800BUS(
          .CLK7M	( CLK7M			),
          .FC       ( FC            ),
          .AS20	    ( AS20		    ),
          .VPA		( VPA		    ),
          .VMA		( VMA_SYNC		),
          .E		( E				),
          .DSACK1	( DSACK1_SYNC 	)
      );


ata ATA (

        .CLK	( CLKCPU	),
        .AS	( AS20	),
        .RW	( RW20	),
        .A		( A		),
        .WAIT	( IDEWAIT),

        .IDECS( IDECS	),
        .IOR	( IOR		),
        .IOW	( IOW		),
        .DTACK( DTACK_IDE	),
        .ACCESS( GAYLE_IDE )

    );

reg CPCS_INT = 1'b1;
reg AVEC_INT = 1'b1;
reg CANSTART = 1'b1;




always @(negedge CLK7M or negedge AS) begin

    if (AS == 1'b0) begin

        CANSTART <= 1'b0;

    end else begin

        CANSTART <= BUS_BUSY;

    end

end

always @(posedge CLKCPU) begin

    BGACK_INT <= BGACK;

end

wire AS_AMIGA = AS20DLY | FPUOP | ~GAYLE_IDE | ~INTCYCLE | ~BUS_BUSY | (~CANSTART & AS_INT);

always @(posedge CLK7M or posedge AS20) begin

    if (AS20 == 1'b1) begin

        AS_INT <= 1'b1;
        AS_INTD <= 1'b1;
        
        RW_INT <= 1'b1;

        LDS_INT <= 1'b1;
        UDS_INT <= 1'b1;

        DTACK_S6 <= 1'b1;

    end else begin



        AS_INT <= AS_AMIGA;
        AS_INTD <= AS_INT;

        RW_INT <= RW20 | AS_AMIGA;

        if (RW20 == 1'b1) begin


            UDS_INT <= DS20 | A[0] | AS_AMIGA;
            LDS_INT <= DS20 | ({A[0], SIZ[1:0]} == 3'b001) | AS_AMIGA;

        end else begin


            UDS_INT <= DS20 | AS_INT | A[0] | AS_AMIGA;
            LDS_INT <= DS20 | AS_INT  | ({A[0], SIZ[1:0]} == 3'b001) | AS_AMIGA;

        end

        DTACK_S6 <= DTACK_LATCHED;

    end

end

always @(posedge CLKCPU or posedge BG20) begin

    if (BG20 == 1'b1) begin

        BG_INT <= 1'b1;

    end else begin 

        if (AS20 == AS_INT) begin

            BG_INT <= BG20;

        end 

    end

end


always @(negedge CLK7M or posedge AS20) begin

    if (AS20 == 1'b1) begin

        DTACK_LATCHED <= 1'b1;
        DTACK_S7 <= 1'b1;
        
    end else begin



        DTACK_LATCHED <= AS_INTD | DTACK;
        DTACK_S7 <= DTACK_S6;

    end

end

always @(posedge CLKCPU or posedge AS20) begin

    if (AS20 == 1'b1) begin

        DSACK_INT <= 2'b11;

    end else begin

        DSACK_INT <= {DSACK_INT[0], DTACK_S7D};
    
    end

end


always @(posedge CLKCPU or posedge AS20) begin

    if (AS20 == 1'b1) begin

        AS20DLY <= 1'b1;
        CPCS_INT <= 1'b1;
        AVEC_INT <= 1'b1;

    end else begin


        AS20DLY <= AS20 | FPUOP;
        CPCS_INT <= ~FPUOP | AS20;
        AVEC_INT <= ~IACK | VPA;
        
    end

end

`ifndef ATARI

always @(posedge CLKCPU) begin


    BUSEN_D <= ~INTCYCLE | AS_INT;
    INT2_INT <= INT2;
    INT2_IACK_INT <= INT2_IACK;

end

always @(negedge INT2_INT, posedge INT2_IACK_INT) begin 

    if (INT2_IACK_INT == 1'b1) begin 

        INT2_ASSERT <= 1'b0;

    end else begin 

        INT2_ASSERT <= 1'b1;

    end

end

`else

always @(posedge CLKCPU) begin


    BUSEN_D <= ~INTCYCLE | AS_INT;
end

`endif


wire VMA_INT = VMA_SYNC;

assign RW =   HIGHZ ? 1'bz : RW_INT;
assign AS =   HIGHZ ? 1'bz : AS_INT;
assign UDS =  HIGHZ ? 1'bz : UDS_INT;
assign LDS =  HIGHZ ? 1'bz : LDS_INT;
assign VMA =  HIGHZ ? 1'bz : VMA_INT;

assign DSACK1 = FPUOP | (~IDEWAIT | DSACK_INT[0]) & DSACK1_SYNC & DTACK_IDE & SLOWCYCLE;

assign BG = BG_INT ? 1'bz : 1'b0;
assign AVEC = AVEC_INT;

assign BERR = (CPCS_INT | ~CPSENSE) ? 1'bz : 1'b0;
assign CPCS = CPCS_INT;
assign BUSEN = BUSEN_D;

`ifndef ATARI
assign IPL[2:1] = INT2_ASSERT ? {2'b10} : {2'bzz};
`else
assign IPL[2:1] = {2'bzz};
`endif

endmodule