data/full_repos/permissive/164033466/Source/peripheral.v
data/verilator_xmls/1f128722-e7fb-4f61-b6b0-32695d51908c.xml
module fsmPeripheral (SEND, clk, rst, inputData, outACK);
	output reg outACK;

	input SEND;
  	input clk, rst;
  	input [31:0] inputData;


	reg currentState, nextState;
  	reg [31:0] data;



	always @ (posedge clk)
	begin
		if (rst == 1)
			currentState <= 0;
		else
			currentState <= nextState;
	end


	always @ (*)
	begin
		case ({currentState})
			0, 1:
				if (SEND == 1)
					nextState = 1;
				else
					nextState = 0;
		endcase
	end


	always @ (*)
	begin
		case ({currentState})	
			0:
				outACK = 0;
			1:
			begin
				data = inputData;
				outACK = 1;
			end
		endcase
	end

endmodule
module fsmPeripheral (SEND, clk, rst, inputData, outACK);

	output reg outACK;

	input SEND;
  	input clk, rst;
  	input [31:0] inputData;


	reg currentState, nextState;
  	reg [31:0] data;



	always @ (posedge clk)
	begin
		if (rst == 1)
			currentState <= 0;
		else
			currentState <= nextState;
	end


	always @ (*)
	begin
		case ({currentState})
			0, 1:
				if (SEND == 1)
					nextState = 1;
				else
					nextState = 0;
		endcase
	end


	always @ (*)
	begin
		case ({currentState})	
			0:
				outACK = 0;
			1:
			begin
				data = inputData;
				outACK = 1;
			end
		endcase
	end

endmodule