data/full_repos/permissive/20430511/hardware/FPGA/wishbone/rtl/wb_transfer.v
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data/verilator_xmls/2b74b62c-f640-47dc-a06d-cb8db05a9b01.xml
module wb_transfer
  #(
    parameter ASYNC = 1,
    parameter PIPED = 1,
    parameter CHECK = 1,
    parameter READ  = 1,
    parameter WRITE = 1,
    parameter FRAME = 0,
    parameter BURST = 0,


    parameter DELAY = 3)
   (
    input  clk_i,
    input  rst_i,

    output cyc_o,
    output stb_o,
    output we_o,
    input  ack_i,
    input  wat_i,
    input  rty_i,
    input  err_i,

    input  frame_i,
    input  read_i,
    input  write_i,
    output wait_o,
    output busy_o,
    output done_o,
    output fail_o
    );






   reg     cyc_r = 1'b0, stb_r = 1'b0, we_r  = 1'b0;
   reg     ack_r = 1'b0, err_r = 1'b0;


   wire    cyc_w, stb_w, we_w, ack_w, err_w;
   wire    cyc_a, stb_a, we_a, ack_a, err_a, stb_p;


   wire    read_w, rd_w, wr_w, rd_en, wr_en;


   wire    cycle, write, done_w;






   assign read_w = BURST ? read_i : !write_i;
   assign rd_w   = FRAME ? frame_i && read_w  : read_i;
   assign wr_w   = FRAME ? frame_i && write_i : write_i;

   assign rd_en  = READ  ? rd_w : 1'b0;
   assign wr_en  = WRITE ? wr_w : 1'b0;





   assign cyc_o  = ASYNC > 1 ? cyc_a : cyc_r;
   assign stb_o  = ASYNC > 1 ? stb_a : stb_r;
   assign we_o   = ASYNC > 1 ? we_a  : we_r ;



   assign cyc_a  = CHECK ? !rst_i && cyc_w : cyc_w;
   assign stb_a  = CHECK ? !rst_i && stb_w : stb_w;
   assign we_a   = CHECK ? we_w : wr_en || we_r;
   assign ack_a  = CHECK ? !rst_i && ack_w : ack_w;
   assign err_a  = CHECK ? !rst_i && err_w : err_w;


   assign stb_p  = PIPED ? cyc_r : stb_o;



   assign cyc_w  = rd_en || wr_en || cyc_r;
   assign stb_w  = PIPED ? rd_en || wr_en : cyc_w;
   assign we_w   = wr_en && !rd_en && !cyc_r || we_r;
   assign ack_w  = (CHECK ? stb_p : 1'b1) &&  ack_i;
   assign err_w  = (CHECK ? stb_p : 1'b1) && (rty_i || err_i);







   assign wait_o = BURST ? wat_i : 1'b0;
   assign busy_o = ASYNC > 1 ? cyc_o  : cyc_r;
   assign done_o = ASYNC > 0 ? done_w : ack_r;
   assign fail_o = err_r;



   assign done_w = BURST && FRAME ? cyc_r && !frame_i : ack_w;
   assign cycle  = (!cyc_r || !CHECK) && (rd_en || wr_en);
   assign write  = (!cyc_r || !CHECK) && wr_en;






   always @(posedge clk_i)
     if (rst_i)
       cyc_r <= #DELAY 1'b0;
     else if (cycle)
       cyc_r <= #DELAY 1'b1;
     else if (done_w || rty_i || err_i)
       cyc_r <= #DELAY 1'b0;
     else
       cyc_r <= #DELAY cyc_r;





   always @(posedge clk_i)
     if (rst_i || ASYNC > 1)
       stb_r <= #DELAY 1'b0;
     else if (BURST && FRAME)
       stb_r <= #DELAY frame_i && (rd_en || wr_en);
     else if (cycle)
       stb_r <= #DELAY 1'b1;
     else if (PIPED)
       stb_r <= #DELAY 1'b0;
     else if (ack_i || rty_i || err_i)
       stb_r <= #DELAY 1'b0;
     else
       stb_r <= #DELAY stb_r;


   always @(posedge clk_i)
     if (ack_i || err_i || rty_i)
       we_r  <= #DELAY 1'b0;
     else if (write)
       we_r  <= #DELAY 1'b1;
     else
       we_r  <= #DELAY we_r;


   always @(posedge clk_i) begin
      ack_r <= #DELAY ASYNC > 0 ? 1'b0 : ack_w;
      err_r <= #DELAY err_w;
   end


endmodule
module wb_transfer
  #(
    parameter ASYNC = 1,
    parameter PIPED = 1,
    parameter CHECK = 1,
    parameter READ  = 1,
    parameter WRITE = 1,
    parameter FRAME = 0,
    parameter BURST = 0,


    parameter DELAY = 3)
   (
    input  clk_i,
    input  rst_i,

    output cyc_o,
    output stb_o,
    output we_o,
    input  ack_i,
    input  wat_i,
    input  rty_i,
    input  err_i,

    input  frame_i,
    input  read_i,
    input  write_i,
    output wait_o,
    output busy_o,
    output done_o,
    output fail_o
    );







   reg     cyc_r = 1'b0, stb_r = 1'b0, we_r  = 1'b0;
   reg     ack_r = 1'b0, err_r = 1'b0;


   wire    cyc_w, stb_w, we_w, ack_w, err_w;
   wire    cyc_a, stb_a, we_a, ack_a, err_a, stb_p;


   wire    read_w, rd_w, wr_w, rd_en, wr_en;


   wire    cycle, write, done_w;






   assign read_w = BURST ? read_i : !write_i;
   assign rd_w   = FRAME ? frame_i && read_w  : read_i;
   assign wr_w   = FRAME ? frame_i && write_i : write_i;

   assign rd_en  = READ  ? rd_w : 1'b0;
   assign wr_en  = WRITE ? wr_w : 1'b0;





   assign cyc_o  = ASYNC > 1 ? cyc_a : cyc_r;
   assign stb_o  = ASYNC > 1 ? stb_a : stb_r;
   assign we_o   = ASYNC > 1 ? we_a  : we_r ;



   assign cyc_a  = CHECK ? !rst_i && cyc_w : cyc_w;
   assign stb_a  = CHECK ? !rst_i && stb_w : stb_w;
   assign we_a   = CHECK ? we_w : wr_en || we_r;
   assign ack_a  = CHECK ? !rst_i && ack_w : ack_w;
   assign err_a  = CHECK ? !rst_i && err_w : err_w;


   assign stb_p  = PIPED ? cyc_r : stb_o;



   assign cyc_w  = rd_en || wr_en || cyc_r;
   assign stb_w  = PIPED ? rd_en || wr_en : cyc_w;
   assign we_w   = wr_en && !rd_en && !cyc_r || we_r;
   assign ack_w  = (CHECK ? stb_p : 1'b1) &&  ack_i;
   assign err_w  = (CHECK ? stb_p : 1'b1) && (rty_i || err_i);







   assign wait_o = BURST ? wat_i : 1'b0;
   assign busy_o = ASYNC > 1 ? cyc_o  : cyc_r;
   assign done_o = ASYNC > 0 ? done_w : ack_r;
   assign fail_o = err_r;



   assign done_w = BURST && FRAME ? cyc_r && !frame_i : ack_w;
   assign cycle  = (!cyc_r || !CHECK) && (rd_en || wr_en);
   assign write  = (!cyc_r || !CHECK) && wr_en;






   always @(posedge clk_i)
     if (rst_i)
       cyc_r <= #DELAY 1'b0;
     else if (cycle)
       cyc_r <= #DELAY 1'b1;
     else if (done_w || rty_i || err_i)
       cyc_r <= #DELAY 1'b0;
     else
       cyc_r <= #DELAY cyc_r;





   always @(posedge clk_i)
     if (rst_i || ASYNC > 1)
       stb_r <= #DELAY 1'b0;
     else if (BURST && FRAME)
       stb_r <= #DELAY frame_i && (rd_en || wr_en);
     else if (cycle)
       stb_r <= #DELAY 1'b1;
     else if (PIPED)
       stb_r <= #DELAY 1'b0;
     else if (ack_i || rty_i || err_i)
       stb_r <= #DELAY 1'b0;
     else
       stb_r <= #DELAY stb_r;


   always @(posedge clk_i)
     if (ack_i || err_i || rty_i)
       we_r  <= #DELAY 1'b0;
     else if (write)
       we_r  <= #DELAY 1'b1;
     else
       we_r  <= #DELAY we_r;


   always @(posedge clk_i) begin
      ack_r <= #DELAY ASYNC > 0 ? 1'b0 : ack_w;
      err_r <= #DELAY err_w;
   end


endmodule