data/full_repos/permissive/163670715/cpu.v
None: at end of input
1: b'%Error: data/full_repos/permissive/163670715/cpu.v:21: Cannot find include file: states.i\n`include "states.i" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/163670715,data/full_repos/permissive/163670715/states.i\n             data/full_repos/permissive/163670715,data/full_repos/permissive/163670715/states.i.v\n             data/full_repos/permissive/163670715,data/full_repos/permissive/163670715/states.i.sv\n             states.i\n             states.i.v\n             states.i.sv\n             obj_dir/states.i\n             obj_dir/states.i.v\n             obj_dir/states.i.sv\n%Error: Exiting due to 1 error(s)\n'
module cpu( clk, RST, AB, DB, WE, IRQ, NMI );

`include "states.i"

input clk;
input RST;
output [15:0] AB;
inout  [7:0] DB;
output WE;
input IRQ;
input NMI;

wire tsx;
wire [7:0] SB;

wire [4:0] ab_op;
wire abl_co;
wire abl_pcl8;


wire [2:0] alu_op;
wire [2:0] alu_sel;
wire [2:0] alu_ld;


wire alu_ci;
wire alu_co;
wire alu_n;
wire alu_z;
wire alu_v;

wire RDY;

integer cycle;

always @( posedge clk )
    cycle <= cycle + 1;

always @( posedge clk )
      $display( "%d %8s AB:%04x [%d] DB:%02x PC:%02x%02x IR:%02x %d SEL:%d+%d OP:%d DST:%d DL:%02x BI:%02x ALU:%02x WE:%d PLP:%d AHL:%02x SB:%02x S:%02x A:%02x X:%02x Y:%02x %d:CNZDIV: %d%d%d%d%d%d (%d) IRQ:%h RDY:%h", 
        cycle,
        statename, AB, ab_op, DB, abh.PCH, abl.PCL, ctl.IR, ctl.load_ir, alu_sel, alu_ci, alu_op, alu_ld, alu.M, alu.BI, alu.ADD, WE, ctl.load_p,
        abl.AHL, SB, abl.SPL, alu.A, alu.X, alu.Y, ctl.load_p, 
        ctl.C, ctl.N, ctl.Z, ctl.D, ctl.I, ctl.V, ctl.cond_true, IRQ, RDY );


abh abh( 
    .clk(clk),
    .ABH(AB[15:8]),
    .op(ab_op),
    .PCL8(abl_pcl8),
    .SB7(SB[7]),
    .CI(abl_co),
    .RDY(RDY),
    .DB(DB) );


abl abl( 
    .clk(clk),
    .ABL(AB[7:0]),
    .op(ab_op),
    .PCL8(abl_pcl8),
    .CO(abl_co),
    .SB_DIR(tsx),
    .DB(DB),
    .RDY(RDY),
    .SB(SB) );


ctl ctl(
    .clk(clk),
    .RST(RST),
    .RDY(RDY),
    .IRQ(IRQ),
    .WE(WE),
    .ab_op(ab_op),
    .alu_sel(alu_sel),
    .alu_op(alu_op),
    .alu_ld(alu_ld),
    .alu_ci(alu_ci),
    .alu_co(alu_co),
    .alu_n(alu_n),
    .alu_v(alu_v),
    .alu_z(alu_z),
    .tsx(tsx),
    .DB(DB) );


alu alu(
    .clk(clk),
    .sel(alu_sel),
    .op(alu_op),
    .op_ld(alu_ld),
    .CI(alu_ci),
    .CO(alu_co),
    .N(alu_n),
    .V(alu_v),
    .Z(alu_z),
    .SB_DIR(tsx),
    .SB(SB),
    .RDY(RDY),
    .DB(DB) );



reg [8*6-1:0] statename;

always @*
    case( ctl.state )
            FETCH:  statename = "FETCH";
            DECODE: statename = "DECODE";
            DATA:   statename = "DATA";
            ABS0:   statename = "ABS0";
            IND0:   statename = "IND0";
            INDX0:  statename = "INDX0";
            STK0:   statename = "STK0";
            STK1:   statename = "STK1";
            STK2:   statename = "STK2";
            BRA0:   statename = "BRA0";
    endcase

endmodule
module cpu( clk, RST, AB, DB, WE, IRQ, NMI );


`include "states.i"

input clk;
input RST;
output [15:0] AB;
inout  [7:0] DB;
output WE;
input IRQ;
input NMI;

wire tsx;
wire [7:0] SB;

wire [4:0] ab_op;
wire abl_co;
wire abl_pcl8;


wire [2:0] alu_op;
wire [2:0] alu_sel;
wire [2:0] alu_ld;


wire alu_ci;
wire alu_co;
wire alu_n;
wire alu_z;
wire alu_v;

wire RDY;

integer cycle;

always @( posedge clk )
    cycle <= cycle + 1;

always @( posedge clk )
      $display( "%d %8s AB:%04x [%d] DB:%02x PC:%02x%02x IR:%02x %d SEL:%d+%d OP:%d DST:%d DL:%02x BI:%02x ALU:%02x WE:%d PLP:%d AHL:%02x SB:%02x S:%02x A:%02x X:%02x Y:%02x %d:CNZDIV: %d%d%d%d%d%d (%d) IRQ:%h RDY:%h", 
        cycle,
        statename, AB, ab_op, DB, abh.PCH, abl.PCL, ctl.IR, ctl.load_ir, alu_sel, alu_ci, alu_op, alu_ld, alu.M, alu.BI, alu.ADD, WE, ctl.load_p,
        abl.AHL, SB, abl.SPL, alu.A, alu.X, alu.Y, ctl.load_p, 
        ctl.C, ctl.N, ctl.Z, ctl.D, ctl.I, ctl.V, ctl.cond_true, IRQ, RDY );


abh abh( 
    .clk(clk),
    .ABH(AB[15:8]),
    .op(ab_op),
    .PCL8(abl_pcl8),
    .SB7(SB[7]),
    .CI(abl_co),
    .RDY(RDY),
    .DB(DB) );


abl abl( 
    .clk(clk),
    .ABL(AB[7:0]),
    .op(ab_op),
    .PCL8(abl_pcl8),
    .CO(abl_co),
    .SB_DIR(tsx),
    .DB(DB),
    .RDY(RDY),
    .SB(SB) );


ctl ctl(
    .clk(clk),
    .RST(RST),
    .RDY(RDY),
    .IRQ(IRQ),
    .WE(WE),
    .ab_op(ab_op),
    .alu_sel(alu_sel),
    .alu_op(alu_op),
    .alu_ld(alu_ld),
    .alu_ci(alu_ci),
    .alu_co(alu_co),
    .alu_n(alu_n),
    .alu_v(alu_v),
    .alu_z(alu_z),
    .tsx(tsx),
    .DB(DB) );


alu alu(
    .clk(clk),
    .sel(alu_sel),
    .op(alu_op),
    .op_ld(alu_ld),
    .CI(alu_ci),
    .CO(alu_co),
    .N(alu_n),
    .V(alu_v),
    .Z(alu_z),
    .SB_DIR(tsx),
    .SB(SB),
    .RDY(RDY),
    .DB(DB) );



reg [8*6-1:0] statename;

always @*
    case( ctl.state )
            FETCH:  statename = "FETCH";
            DECODE: statename = "DECODE";
            DATA:   statename = "DATA";
            ABS0:   statename = "ABS0";
            IND0:   statename = "IND0";
            INDX0:  statename = "INDX0";
            STK0:   statename = "STK0";
            STK1:   statename = "STK1";
            STK2:   statename = "STK2";
            BRA0:   statename = "BRA0";
    endcase

endmodule