data/full_repos/permissive/149769583/mac_macro.v
1: b"%Error: data/full_repos/permissive/149769583/mac_macro.v:11: Cannot find file containing module: 'MACC_MACRO'\n    MACC_MACRO #(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/MACC_MACRO\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/MACC_MACRO.v\n             data/full_repos/permissive/149769583,data/full_repos/permissive/149769583/MACC_MACRO.sv\n             MACC_MACRO\n             MACC_MACRO.v\n             MACC_MACRO.sv\n             obj_dir/MACC_MACRO\n             obj_dir/MACC_MACRO.v\n             obj_dir/MACC_MACRO.sv\n%Error: Exiting due to 1 error(s)\n"
module mac_macro (
    output reg [31:0] p_out,
    input [15:0] A,B,
    input CLK,CE,CARRYIN);

    reg [1:0] counter = 2'b11;
    reg LOAD, RST;
    wire [31:0] P;


    MACC_MACRO #(
        .DEVICE("7SERIES"),
        .LATENCY(1),
        .WIDTH_A(16),
        .WIDTH_B(16),
        .WIDTH_P(32)
    ) MACC_MACRO_inst (
        .P(P),
        .A(A),
        .ADDSUB(1'b1),
        .B(B),
        .CARRYIN(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .LOAD(LOAD),
        .LOAD_DATA(P),
        .RST(RST)
    );

    always @(posedge CLK) begin
        if (counter == 2'b11) begin
            RST = 0;
            LOAD = 0;
        end
        else begin
            LOAD = 1;
        end
        if(counter == 2'b10) begin
            p_out = P;
            RST = 1;
        end

        counter = counter + 1;
    end
endmodule
module mac_macro (
    output reg [31:0] p_out,
    input [15:0] A,B,
    input CLK,CE,CARRYIN);


    reg [1:0] counter = 2'b11;
    reg LOAD, RST;
    wire [31:0] P;


    MACC_MACRO #(
        .DEVICE("7SERIES"),
        .LATENCY(1),
        .WIDTH_A(16),
        .WIDTH_B(16),
        .WIDTH_P(32)
    ) MACC_MACRO_inst (
        .P(P),
        .A(A),
        .ADDSUB(1'b1),
        .B(B),
        .CARRYIN(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .LOAD(LOAD),
        .LOAD_DATA(P),
        .RST(RST)
    );

    always @(posedge CLK) begin
        if (counter == 2'b11) begin
            RST = 0;
            LOAD = 0;
        end
        else begin
            LOAD = 1;
        end
        if(counter == 2'b10) begin
            p_out = P;
            RST = 1;
        end

        counter = counter + 1;
    end
endmodule