data/full_repos/permissive/201488448/2_circuits/2_sequential/01_dff.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/986e85a1-1f8a-4691-a2dd-1886d4111fee.xml
module top_module(
	input clk,
	input d,
	output reg q);
	

	always @(posedge clk)
		q <= d;



	
endmodule
module top_module(
	input clk,
	input d,
	output reg q);

	

	always @(posedge clk)
		q <= d;



	
endmodule