data/full_repos/permissive/10003806/cpu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/10003806/cpu_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #101 data_available = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/10003806/cpu_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/10003806/cpu_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = 1;\n        ^\n%Error: data/full_repos/permissive/10003806/cpu_tb.v:36: Cannot find file containing module: \'cpu\'\n    cpu #(.INIT_RAM(1)) uut (\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/cpu\n             data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/cpu.v\n             data/full_repos/permissive/10003806,data/full_repos/permissive/10003806/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_tb;


    reg         clk;
    reg [7:0]   data_in;
    reg         data_available;


    wire [7:0]  data_out;
    wire        data_out_en;
    wire        data_read;


    cpu #(.INIT_RAM(1)) uut (
        .clk(clk),
        .data_in(data_in),
        .data_available(data_available),
        .data_out(data_out),
        .data_out_en(data_out_en),
        .data_read(data_read)
    );

    initial
    begin
        clk = 0;
        data_in = 0;
        data_available = 0;
        #101 data_available = 1;
    end


    always @(posedge clk)
    begin
        if (data_read)
        begin
            data_in <= data_in + 1'b1;
        end
    end
    

    always @(posedge clk)
    begin
        if (data_out_en)
        begin
            $write("%c", data_out);
        end
    end


    always
    begin
        #10 clk = 0;
        #10 clk = 1;
    end
endmodule
module cpu_tb;



    reg         clk;
    reg [7:0]   data_in;
    reg         data_available;


    wire [7:0]  data_out;
    wire        data_out_en;
    wire        data_read;


    cpu #(.INIT_RAM(1)) uut (
        .clk(clk),
        .data_in(data_in),
        .data_available(data_available),
        .data_out(data_out),
        .data_out_en(data_out_en),
        .data_read(data_read)
    );

    initial
    begin
        clk = 0;
        data_in = 0;
        data_available = 0;
        #101 data_available = 1;
    end


    always @(posedge clk)
    begin
        if (data_read)
        begin
            data_in <= data_in + 1'b1;
        end
    end
    

    always @(posedge clk)
    begin
        if (data_out_en)
        begin
            $write("%c", data_out);
        end
    end


    always
    begin
        #10 clk = 0;
        #10 clk = 1;
    end
endmodule