data/full_repos/permissive/111021593/VGA_controller_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/111021593/VGA_controller_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100 reset = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/111021593/VGA_controller_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/111021593/VGA_controller_tb.v:7: Cannot find file containing module: \'VGA_controller\'\nVGA_controller DUT(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/VGA_controller\n             data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/VGA_controller.v\n             data/full_repos/permissive/111021593,data/full_repos/permissive/111021593/VGA_controller.sv\n             VGA_controller\n             VGA_controller.v\n             VGA_controller.sv\n             obj_dir/VGA_controller\n             obj_dir/VGA_controller.v\n             obj_dir/VGA_controller.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module VGA_controller_tb();

reg clk, reset;
wire VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC;


VGA_controller DUT(
	.clk		(clk),
	.reset		(reset),
	.VGA_RED	(VGA_RED),
	.VGA_GREEN	(VGA_GREEN),
	.VGA_BLUE	(VGA_BLUE),
	.VGA_HSYNC	(VGA_HSYNC),
	.VGA_VSYNC	(VGA_VSYNC)
);

initial begin
	clk = 0;
	reset = 1;
	#100 reset = 0;
end

always begin
	#5 clk = ~clk;
end

endmodule
module VGA_controller_tb();


reg clk, reset;
wire VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC;


VGA_controller DUT(
	.clk		(clk),
	.reset		(reset),
	.VGA_RED	(VGA_RED),
	.VGA_GREEN	(VGA_GREEN),
	.VGA_BLUE	(VGA_BLUE),
	.VGA_HSYNC	(VGA_HSYNC),
	.VGA_VSYNC	(VGA_VSYNC)
);

initial begin
	clk = 0;
	reset = 1;
	#100 reset = 0;
end

always begin
	#5 clk = ~clk;
end

endmodule