data/full_repos/permissive/160024456/exp/counter.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/160024456/exp/counter.v:17: Signal definition not found, creating implicitly: \'counter1_overflow\'\n    if (counter1_overflow == 1) begin\n        ^~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/160024456/exp/counter.v:13: Cannot find file containing module: \'plain_counter\'\nplain_counter #(.WIDTH(23), .VAL(6000000)) plain_counter1 (.clk(clk), .en(ready), .inc(1\'b1), .v(counter1), .r(counter1_overflow));\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160024456/exp,data/full_repos/permissive/160024456/plain_counter\n             data/full_repos/permissive/160024456/exp,data/full_repos/permissive/160024456/plain_counter.v\n             data/full_repos/permissive/160024456/exp,data/full_repos/permissive/160024456/plain_counter.sv\n             plain_counter\n             plain_counter.v\n             plain_counter.sv\n             obj_dir/plain_counter\n             obj_dir/plain_counter.v\n             obj_dir/plain_counter.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module partx (
  input wire clk,
  output reg LED1,
  output reg LED2,
  output reg LED3
);

reg ready = 0;
wire [22:0] counter1;
wire counter1_done;
reg [19:0] result;

plain_counter #(.WIDTH(23), .VAL(6000000)) plain_counter1 (.clk(clk), .en(ready), .inc(1'b1), .v(counter1), .r(counter1_overflow));

always @(posedge clk) begin
  if (ready == 1) begin
    if (counter1_overflow == 1) begin
      LED1 <= ~LED1;
      result <= {result[0], result[19:1]};
    end
    if (result == 1) begin
      LED2 <= 1;
    end
    else begin
      LED2 <= 0;
    end
  end
  else begin
    ready <= 1;
    LED1 <= 0;
    LED2 <= 0;
    result <= 20'b00010;
  end
end

endmodule
module partx (
  input wire clk,
  output reg LED1,
  output reg LED2,
  output reg LED3
);


reg ready = 0;
wire [22:0] counter1;
wire counter1_done;
reg [19:0] result;

plain_counter #(.WIDTH(23), .VAL(6000000)) plain_counter1 (.clk(clk), .en(ready), .inc(1'b1), .v(counter1), .r(counter1_overflow));

always @(posedge clk) begin
  if (ready == 1) begin
    if (counter1_overflow == 1) begin
      LED1 <= ~LED1;
      result <= {result[0], result[19:1]};
    end
    if (result == 1) begin
      LED2 <= 1;
    end
    else begin
      LED2 <= 0;
    end
  end
  else begin
    ready <= 1;
    LED1 <= 0;
    LED2 <= 0;
    result <= 20'b00010;
  end
end

endmodule