data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v
'utf-8' codec can't decode byte 0xd6 in position 537: invalid continuation byte
1: b"%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:52: syntax error, unexpected ')', expecting '['\n         );   \n         ^\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:54: syntax error, unexpected output\n  output [31:0] DataOut;  \n  ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:58: syntax error, unexpected output\n  output [2:0] ALUOp;    \n  ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:60: syntax error, unexpected output\n        output [1:0] PCSrc;\n        ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:62: syntax error, unexpected output\n  output wire[31:0] IDataOut;  \n  ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:63: syntax error, unexpected output\n  output wire [31:0] WriteData;\n  ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:68: syntax error, unexpected output\n        output wire[31:0] ReadData1;   \n        ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:69: syntax error, unexpected output\n        output wire[31:0] ReadData2;   \n        ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:70: syntax error, unexpected output\n        output wire[31:0] CurrentAddress;   \n        ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:71: syntax error, unexpected output\n        output wire[31:0] ALUResult;    \n        ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:72: syntax error, unexpected output\n         output wire[31:0] ExtendResult;   \n         ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:74: syntax error, unexpected input\n      input wire[4:0] rs;\n      ^~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:75: syntax error, unexpected assign\n      assign rs = IRDataOut[25:21]; \n      ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:77: syntax error, unexpected assign\n   assign rt = IRDataOut[20:16];\n   ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:79: syntax error, unexpected assign\n   assign rd = IRDataOut[15:11];\n   ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:81: syntax error, unexpected assign\n   assign sa = {{26{1'b0}},IRDataOut[10:6]};      \n   ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:83: syntax error, unexpected assign\n   assign opcode = IRDataOut[31:26];\n   ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:85: syntax error, unexpected assign\n   assign toSignZeroExtend = IRDataOut[15:0];\n   ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:87: syntax error, unexpected assign\n   assign toExtendAddress = IRDataOut[25:0];\n   ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:89: syntax error, unexpected assign\n   assign immediate = IRDataOut[15:0];\n   ^~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:91: syntax error, unexpected input\n         input wire[31:0] PCPlusFourAddress;   \n         ^~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:92: syntax error, unexpected input\n         input wire[31:0] JumpAddress;   \n         ^~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:97: syntax error, unexpected IDENTIFIER\n PC _PC(PCWre, NextAddress, CLK, RST, CurrentAddress);\n ^~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:126: syntax error, unexpected IDENTIFIER\n    DataReg ADR(ReadData1, ADROut, CLK);  \n    ^~~~~~~\n%Error: data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/DataPath.v:140: syntax error, unexpected IDENTIFIER\n    Selector21_32bits ToDBDR(ALUResult, DataOut, DBDataSrc, DBDRIn);\n    ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 25 error(s)\n"
module DataPath(
	     CLK,
		 RST,
	     zero,
	     sign,
		 CurrentAddress,
		 NextAddress,
		 ALUOp,
		 ReadData1,
         ReadData2,
         dataA,
         dataB,
		 ALUResult,
	     IDataOut,
	     DataOut,
	     WriteData,
	     rs,        
	     rt,
	     rd,
	     sa,
	     opcode,
	     PCSrc,
         PCPlusFourAddress,
         immediate,
         ExtendResult,
         toExtendAddress,
         JumpAddress,
         WriteReg,
         IRDataOut,
         );
        input wire CLK, RST, zero, sign;
		output [31:0] DataOut;
		output [31:0] IRDataOut; 	
		output [31:0] NextAddress;
	    input wire [4:0] WriteReg;
		output [2:0] ALUOp;
        wire mRD, mWR;
        output [1:0] PCSrc;
	    wire InsMemRW;    
		output wire[31:0] IDataOut;  
		output wire [31:0] WriteData;
		

		wire ExtSel, PCWre, RegWre, ALUSrcA, ALUSrcB, DBDataSrc, IRWre, WrRegDSrc;
		wire [1:0] RegDst;
        output wire[31:0] ReadData1;
        output wire[31:0] ReadData2;
        output wire[31:0] CurrentAddress;
        output wire[31:0] ALUResult;
         output wire[31:0] ExtendResult;

	     input wire[4:0] rs;
	     assign rs = IRDataOut[25:21]; 
		 input wire[4:0] rt;
		 assign rt = IRDataOut[20:16];
		 input wire[4:0] rd;
		 assign rd = IRDataOut[15:11];
		 input wire[31:0] sa;
		 assign sa = {{26{1'b0}},IRDataOut[10:6]};
		 input wire[5:0] opcode;
		 assign opcode = IRDataOut[31:26];
		 wire[15:0] toSignZeroExtend;
		 assign toSignZeroExtend = IRDataOut[15:0];
		 input wire[25:0]toExtendAddress;
		 assign toExtendAddress = IRDataOut[25:0];
		 input wire[15:0] immediate;
		 assign immediate = IRDataOut[15:0];
         input wire[31:0] dataA, dataB;
         input wire[31:0] PCPlusFourAddress;
         input wire[31:0] JumpAddress;
                      
        
        

	PC _PC(PCWre, NextAddress, CLK, RST, CurrentAddress);

    PCPlusFour _PCplus4(CurrentAddress, PCPlusFourAddress);              


	InsMem _InsMem(InsMemRW, CurrentAddress, IDataOut);


    IR _IR(IRWre, IDataOut, CLK, IRDataOut);
    
	ControlUnit controlunit(
    zero,  RST,  CLK, mRD,  mWR, DBDataSrc,
    ExtSel, PCWre, IRWre, InsMemRW, opcode, WrRegDSrc,
    RegDst,  RegWre,  ALUOp,  PCSrc, sign,  ALUSrcA, ALUSrcB 
    );
	
	
    Selector31_5bits selectorWriteReg(rt, rd, RegDst, WriteReg);

	RegFile  _RegFile(RegWre, CLK, rs, rt, WriteReg, WriteData, ReadData1, ReadData2);

    SignZeroExtend _SignZeroExtend(immediate, ExtSel , ExtendResult);


    JumpAddressExtend _JumpAddressExtend(PCPlusFourAddress,toExtendAddress,JumpAddress);

     Selector41_32bits Selector41_32bits(PCPlusFourAddress, ExtendResult, ReadData1, JumpAddress, PCSrc, NextAddress);    

    wire [31:0] ADROut,BDROut,ALUOutDROut, DBDROut;
    DataReg ADR(ReadData1, ADROut, CLK);  
    DataReg BDR(ReadData2, BDROut, CLK);

     Selector21_32bits selector32_A(ADROut, sa, ALUSrcA, dataA);
     Selector21_32bits selector32_B(BDROut, ExtendResult, ALUSrcB,dataB);

    ALU _ALU(dataA, dataB,ALUOp, ALUResult, zero, sign);
    DataReg ALUOutDR(ALUResult,ALUOutDROut,CLK);

    DataMem _DataMem(CLK, mWR, mRD, ALUOutDROut, BDROut, DataOut);

    
    wire [31:0] DBDRIn; 

    Selector21_32bits ToDBDR(ALUResult, DataOut, DBDataSrc, DBDRIn);
    DataReg DBDR(DBDRIn, DBDROut, CLK);      
    Selector21_32bits ToRegFile(PCPlusFourAddress, DBDROut, WrRegDSrc, WriteData);
    
   

endmodule
module DataPath(
	     CLK,
		 RST,
	     zero,
	     sign,
		 CurrentAddress,
		 NextAddress,
		 ALUOp,
		 ReadData1,
         ReadData2,
         dataA,
         dataB,
		 ALUResult,
	     IDataOut,
	     DataOut,
	     WriteData,
	     rs,        
	     rt,
	     rd,
	     sa,
	     opcode,
	     PCSrc,
         PCPlusFourAddress,
         immediate,
         ExtendResult,
         toExtendAddress,
         JumpAddress,
         WriteReg,
         IRDataOut,
         );

        input wire CLK, RST, zero, sign;
		output [31:0] DataOut;
		output [31:0] IRDataOut; 	
		output [31:0] NextAddress;
	    input wire [4:0] WriteReg;
		output [2:0] ALUOp;
        wire mRD, mWR;
        output [1:0] PCSrc;
	    wire InsMemRW;    
		output wire[31:0] IDataOut;  
		output wire [31:0] WriteData;
		

		wire ExtSel, PCWre, RegWre, ALUSrcA, ALUSrcB, DBDataSrc, IRWre, WrRegDSrc;
		wire [1:0] RegDst;
        output wire[31:0] ReadData1;
        output wire[31:0] ReadData2;
        output wire[31:0] CurrentAddress;
        output wire[31:0] ALUResult;
         output wire[31:0] ExtendResult;

	     input wire[4:0] rs;
	     assign rs = IRDataOut[25:21]; 
		 input wire[4:0] rt;
		 assign rt = IRDataOut[20:16];
		 input wire[4:0] rd;
		 assign rd = IRDataOut[15:11];
		 input wire[31:0] sa;
		 assign sa = {{26{1'b0}},IRDataOut[10:6]};
		 input wire[5:0] opcode;
		 assign opcode = IRDataOut[31:26];
		 wire[15:0] toSignZeroExtend;
		 assign toSignZeroExtend = IRDataOut[15:0];
		 input wire[25:0]toExtendAddress;
		 assign toExtendAddress = IRDataOut[25:0];
		 input wire[15:0] immediate;
		 assign immediate = IRDataOut[15:0];
         input wire[31:0] dataA, dataB;
         input wire[31:0] PCPlusFourAddress;
         input wire[31:0] JumpAddress;
                      
        
        

	PC _PC(PCWre, NextAddress, CLK, RST, CurrentAddress);

    PCPlusFour _PCplus4(CurrentAddress, PCPlusFourAddress);              


	InsMem _InsMem(InsMemRW, CurrentAddress, IDataOut);


    IR _IR(IRWre, IDataOut, CLK, IRDataOut);
    
	ControlUnit controlunit(
    zero,  RST,  CLK, mRD,  mWR, DBDataSrc,
    ExtSel, PCWre, IRWre, InsMemRW, opcode, WrRegDSrc,
    RegDst,  RegWre,  ALUOp,  PCSrc, sign,  ALUSrcA, ALUSrcB 
    );
	
	
    Selector31_5bits selectorWriteReg(rt, rd, RegDst, WriteReg);

	RegFile  _RegFile(RegWre, CLK, rs, rt, WriteReg, WriteData, ReadData1, ReadData2);

    SignZeroExtend _SignZeroExtend(immediate, ExtSel , ExtendResult);


    JumpAddressExtend _JumpAddressExtend(PCPlusFourAddress,toExtendAddress,JumpAddress);

     Selector41_32bits Selector41_32bits(PCPlusFourAddress, ExtendResult, ReadData1, JumpAddress, PCSrc, NextAddress);    

    wire [31:0] ADROut,BDROut,ALUOutDROut, DBDROut;
    DataReg ADR(ReadData1, ADROut, CLK);  
    DataReg BDR(ReadData2, BDROut, CLK);

     Selector21_32bits selector32_A(ADROut, sa, ALUSrcA, dataA);
     Selector21_32bits selector32_B(BDROut, ExtendResult, ALUSrcB,dataB);

    ALU _ALU(dataA, dataB,ALUOp, ALUResult, zero, sign);
    DataReg ALUOutDR(ALUResult,ALUOutDROut,CLK);

    DataMem _DataMem(CLK, mWR, mRD, ALUOutDROut, BDROut, DataOut);

    
    wire [31:0] DBDRIn; 

    Selector21_32bits ToDBDR(ALUResult, DataOut, DBDataSrc, DBDRIn);
    DataReg DBDR(DBDRIn, DBDROut, CLK);      
    Selector21_32bits ToRegFile(PCPlusFourAddress, DBDROut, WrRegDSrc, WriteData);
    
   

endmodule