data/full_repos/permissive/159479522/water_in.v
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data/verilator_xmls/fddd2073-fabf-4f16-9880-9aa44bd2846c.xml
module water_in(reset,power_led,start_led,water_select,if_finish,water_level);
input wire reset,power_led,start_led,water_select,if_finish;
output reg [3:0] water_level;
initial begin
water_level=2;
end
 always@(posedge water_select or posedge if_finish )
   begin
   if(reset==0||if_finish==1)        
   water_level=2;
   else   begin
   if(power_led&&~start_led)   begin     
   if(water_level>=5)
   water_level=2;
   else water_level=water_level+1; 
     end
    end
   end  
endmodule
module water_in(reset,power_led,start_led,water_select,if_finish,water_level);

input wire reset,power_led,start_led,water_select,if_finish;
output reg [3:0] water_level;
initial begin
water_level=2;
end
 always@(posedge water_select or posedge if_finish )
   begin
   if(reset==0||if_finish==1)        
   water_level=2;
   else   begin
   if(power_led&&~start_led)   begin     
   if(water_level>=5)
   water_level=2;
   else water_level=water_level+1; 
     end
    end
   end  
endmodule