data/full_repos/permissive/143278/ivltests/pr1873146.v
 line:7: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1873146.v:7: Unsupported: Ignoring delay on this delayed statement.\n   initial#1 $display("PASSED");\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test (a, b);

  output [31 : 0] a;
  input b;

  buf bufd[31:0] (a, b);
   initial#1 $display("PASSED");
  specify
    specparam

    th = 0.9;


    if (!b)
      (b *> a[0]) = (0);
  endspecify

endmodule
module test (a, b);


  output [31 : 0] a;
  input b;

  buf bufd[31:0] (a, b);
   initial#1 $display("PASSED");
  specify
    specparam

    th = 0.9;


    if (!b)
      (b *> a[0]) = (0);
  endspecify

endmodule