data/full_repos/permissive/216615048/src/32_reg.v
'utf-8' codec can't decode byte 0x96 in position 613: invalid start byte
1: b"%Error: data/full_repos/permissive/216615048/src/32_reg.v:25: Cannot find file containing module: 'DFlipFlop'\n            DFlipFlop flip(clk, rst, muxer[i], out[i]);\n            ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216615048/src,data/full_repos/permissive/216615048/DFlipFlop\n             data/full_repos/permissive/216615048/src,data/full_repos/permissive/216615048/DFlipFlop.v\n             data/full_repos/permissive/216615048/src,data/full_repos/permissive/216615048/DFlipFlop.sv\n             DFlipFlop\n             DFlipFlop.v\n             DFlipFlop.sv\n             obj_dir/DFlipFlop\n             obj_dir/DFlipFlop.v\n             obj_dir/DFlipFlop.sv\n%Error: data/full_repos/permissive/216615048/src/32_reg.v:26: Cannot find file containing module: 'mux'\n            mux muxie(out[i], in[i], load, muxer[i]);\n            ^~~\n%Error: Exiting due to 2 error(s)\n"
module register #(parameter n = 32) (input clk, input [n-1:0]in, input rst, input load, output [n-1:0]out);
    
    wire [n-1:0]muxer;
    genvar i;
    generate
        for (i = 0; i < n; i = i + 1) begin
            DFlipFlop flip(clk, rst, muxer[i], out[i]);
            mux muxie(out[i], in[i], load, muxer[i]);
        end 
    endgenerate
endmodule
module register #(parameter n = 32) (input clk, input [n-1:0]in, input rst, input load, output [n-1:0]out);

    
    wire [n-1:0]muxer;
    genvar i;
    generate
        for (i = 0; i < n; i = i + 1) begin
            DFlipFlop flip(clk, rst, muxer[i], out[i]);
            mux muxie(out[i], in[i], load, muxer[i]);
        end 
    endgenerate
endmodule