data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:254: Unsupported: Ignoring delay on this delayed statement.\n        forever #50 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:45: Cannot find file containing module: \'instMemory\'\n    instMemory #(32, 4) myIMEM(.inst(instr32), .pcVal(PC16[3:0]), .sysCLK(mainCLOCK));    \n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191834901/VerilogHDL,data/full_repos/permissive/191834901/instMemory\n             data/full_repos/permissive/191834901/VerilogHDL,data/full_repos/permissive/191834901/instMemory.v\n             data/full_repos/permissive/191834901/VerilogHDL,data/full_repos/permissive/191834901/instMemory.sv\n             instMemory\n             instMemory.v\n             instMemory.sv\n             obj_dir/instMemory\n             obj_dir/instMemory.v\n             obj_dir/instMemory.sv\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:50: Cannot find file containing module: \'controlPathDriver\'\n    controlPathDriver #(16, 16) myCP(\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:72: Cannot find file containing module: \'registerFile\'\n    registerFile #(32, 5) riscRegisters(\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:86: Cannot find file containing module: \'mainALU\'\n    mainALU #(32) testALU(\n    ^~~~~~~\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:99: Cannot find file containing module: \'dataMemory\'\n    dataMemory #(32, 16) myDMEM(\n    ^~~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module immideateGen #(parameter instWidth = 32) (
    output reg [(instWidth-1):0] imm32,
    input  [(instWidth-1):0] instr,
    input  [2:0] immSelect
);

    wire [6:0] opcode;
    wire [4:0] rd, rs1, rs2;
    wire [2:0] funct3;
    wire [6:0] funct7;

    splitInstruction getParts(opcode, rd, rs1, rs2, funct3, funct7, instr);

    reg [31:0]imm_I, imm_S, imm_SB, immU;
    always@(*) begin
        case(immSelect)
            3'b000: imm32 = {20'b0, funct7, rs2};
            3'b001: imm32 = {20'b0, funct7, rd};
            3'b010: imm32 = {19'b0, funct7[6], rd[0], funct7[5:0], rd[4:1], 1'b0};
            3'b011: imm32 = {funct7, rs2, rs1, funct3, 12'b0};
            default: imm32 = 32'hAAAAAAAA;
        endcase
    end
endmodule
module immideateGen #(parameter instWidth = 32) (
    output reg [(instWidth-1):0] imm32,
    input  [(instWidth-1):0] instr,
    input  [2:0] immSelect
);


    wire [6:0] opcode;
    wire [4:0] rd, rs1, rs2;
    wire [2:0] funct3;
    wire [6:0] funct7;

    splitInstruction getParts(opcode, rd, rs1, rs2, funct3, funct7, instr);

    reg [31:0]imm_I, imm_S, imm_SB, immU;
    always@(*) begin
        case(immSelect)
            3'b000: imm32 = {20'b0, funct7, rs2};
            3'b001: imm32 = {20'b0, funct7, rd};
            3'b010: imm32 = {19'b0, funct7[6], rd[0], funct7[5:0], rd[4:1], 1'b0};
            3'b011: imm32 = {funct7, rs2, rs1, funct3, 12'b0};
            default: imm32 = 32'hAAAAAAAA;
        endcase
    end
endmodule