data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/multiplier.v
1: b'%Warning-WIDTH: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/multiplier.v:28: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                                    : ... In instance mul\n    assign result = C + S + cin;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module full_adder(
    input  wire A,
    input  wire B,
    input  wire Ci,
    output wire Co,
    output wire S
);
    assign S  = A ^ B ^ Ci;
    assign Co = A & B | A & Ci | B & Ci;
endmodule
module full_adder(
    input  wire A,
    input  wire B,
    input  wire Ci,
    output wire Co,
    output wire S
);

    assign S  = A ^ B ^ Ci;
    assign Co = A & B | A & Ci | B & Ci;
endmodule