data/full_repos/permissive/143278/ivltests/modparam.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:131: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:138: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:141: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:158: Unsupported: Ignoring delay on this delayed statement.\nalways #(5) clk = ~clk;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/modparam.v:134: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                         : ... In instance top\n    din = 32\'b0_00;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/modparam.v:137: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                         : ... In instance top\n    din = 32\'h1;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/modparam.v:140: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h2\' generates 32 bits.\n                                                                         : ... In instance top\n    din = 32\'h2;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/modparam.v:143: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3\' generates 32 bits.\n                                                                         : ... In instance top\n    din = 32\'h3;\n        ^\n%Error: Exiting due to 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reg32 (clk,we, din, dout);

parameter WIDTH=32;

input			we;
input			clk;
input [WIDTH-1:0]	din;

output [WIDTH-1:0]	dout;

reg [WIDTH-1:0] store;

always @(posedge clk)
  if(we)
    store <= din;

assign dout = store ;

endmodule
module reg32 (clk,we, din, dout);


parameter WIDTH=32;

input			we;
input			clk;
input [WIDTH-1:0]	din;

output [WIDTH-1:0]	dout;

reg [WIDTH-1:0] store;

always @(posedge clk)
  if(we)
    store <= din;

assign dout = store ;

endmodule