data/full_repos/permissive/160895047/ALU_Test.v
1: b'%Error: data/full_repos/permissive/160895047/ALU_Test.v:1: Cannot find include file: ALU.v\n`include "ALU.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160895047,data/full_repos/permissive/160895047/ALU.v\n             data/full_repos/permissive/160895047,data/full_repos/permissive/160895047/ALU.v.v\n             data/full_repos/permissive/160895047,data/full_repos/permissive/160895047/ALU.v.sv\n             ALU.v\n             ALU.v.v\n             ALU.v.sv\n             obj_dir/ALU.v\n             obj_dir/ALU.v.v\n             obj_dir/ALU.v.sv\n%Error: data/full_repos/permissive/160895047/ALU_Test.v:9: Too many digits for 32 bit number: 9534251256\n        ... As that number was unsized (\'d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)\n        ... Suggest adding a size to it.\ninteger seed = 9534251256;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/ALU_Test.v:14: Unsupported or unknown PLI call: $monitor\n $monitor("%b\\t%g\\t\\t%g\\t\\t%g\\t\\t%g\\n%b\\t%b\\t%b\\t%b\\t%b", \n ^~~~~~~~\n%Error: data/full_repos/permissive/160895047/ALU_Test.v:17: Define or directive not defined: \'`ALU_ADD\'\n Control = `ALU_ADD;\n           ^~~~~~~~\n%Error: data/full_repos/permissive/160895047/ALU_Test.v:17: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Control = `ALU_ADD;\n                   ^\n%Error: data/full_repos/permissive/160895047/ALU_Test.v:18: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n SrcA = $random(seed);\n        ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/160895047/ALU_Test.v:18: ../V3Ast.cpp:358: Null item passed to setOp1p\n SrcA = $random(seed);\n      ^\n'
module ALU_Test();
reg [2:0] Control;
reg [7:0] SrcA;
reg [7:0] SrcB;
wire [7:0] Result;
wire Zero;

integer seed = 9534251256;

initial
begin
	$display("C\tA\t\tB\t\tR\t");
	$monitor("%b\t%g\t\t%g\t\t%g\t\t%g\n%b\t%b\t%b\t%b\t%b", 
		Control, SrcA, SrcB, Result, Zero,
		Control, SrcA, SrcB, Result, Zero);
	Control = `ALU_ADD;
	SrcA = $random(seed);
	SrcB = $random(seed);
	#5 Control = `ALU_SUBTRACT;
	SrcA = $random(seed);
	SrcB = $random(seed);
	#5 Control = `ALU_AND;
	SrcA = $random(seed);
	SrcB = $random(seed);
	#5 Control = `ALU_OR;
	SrcA = $random(seed);
	SrcB = $random(seed);
	#5 Control = `ALU_SLT;
	SrcA = $random(seed);
	SrcB = $random(seed);
	#5 Control = `ALU_SUBTRACT;
	SrcA = 123;
	SrcB = 123;
	
end

ALU U0(
	Control,
	SrcA,
	SrcB,
	Result,
	Zero
);
endmodule
module ALU_Test();

reg [2:0] Control;
reg [7:0] SrcA;
reg [7:0] SrcB;
wire [7:0] Result;
wire Zero;

integer seed = 9534251256;

initial
begin
	$display("C\tA\t\tB\t\tR\t");
	$monitor("%b\t%g\t\t%g\t\t%g\t\t%g\n%b\t%b\t%b\t%b\t%b", 
		Control, SrcA, SrcB, Result, Zero,
		Control, SrcA, SrcB, Result, Zero);
	Control = `ALU_ADD;
	SrcA = $random(seed);
	SrcB = $random(seed);
	#5 Control = `ALU_SUBTRACT;
	SrcA = $random(seed);
	SrcB = $random(seed);
	#5 Control = `ALU_AND;
	SrcA = $random(seed);
	SrcB = $random(seed);
	#5 Control = `ALU_OR;
	SrcA = $random(seed);
	SrcB = $random(seed);
	#5 Control = `ALU_SLT;
	SrcA = $random(seed);
	SrcB = $random(seed);
	#5 Control = `ALU_SUBTRACT;
	SrcA = 123;
	SrcB = 123;
	
end

ALU U0(
	Control,
	SrcA,
	SrcB,
	Result,
	Zero
);
endmodule