data/full_repos/permissive/122560566/FPU.srcs/sources_1/new/reg_file.v
1: b'%Warning-WIDTH: data/full_repos/permissive/122560566/FPU.srcs/sources_1/new/reg_file.v:43: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance reg_file\n        O_dataA = 1\'d0;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/122560566/FPU.srcs/sources_1/new/reg_file.v:44: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance reg_file\n        O_dataB = 1\'d0;\n                ^\n%Error: Exiting due to 2 warning(s)\n'
module reg_file(
    input [2:0] I_selA,
    input [2:0] I_selB,
    input [2:0] I_selD,
    input [15:0] I_dataD,
    input I_clk,
    input I_en,
    input I_we,
    output reg [15:0] O_dataA,
    output reg [15:0] O_dataB
    );
    

    reg [15:0] regs[7:0];
    

    integer count;
  

    initial begin
        O_dataA = 1'd0;
        O_dataB = 1'd0;
        
        for(count = 0; count < 8; count = count + 1) begin
            regs[count] = 0;
        end
    end
    

    always @(negedge I_clk) begin
        if(I_en) begin

            if(I_we)
                regs[I_selD] = I_dataD;
                

            O_dataA <= regs[I_selA];
            O_dataB <= regs[I_selB];
        end
    end
endmodule
module reg_file(
    input [2:0] I_selA,
    input [2:0] I_selB,
    input [2:0] I_selD,
    input [15:0] I_dataD,
    input I_clk,
    input I_en,
    input I_we,
    output reg [15:0] O_dataA,
    output reg [15:0] O_dataB
    );

    

    reg [15:0] regs[7:0];
    

    integer count;
  

    initial begin
        O_dataA = 1'd0;
        O_dataB = 1'd0;
        
        for(count = 0; count < 8; count = count + 1) begin
            regs[count] = 0;
        end
    end
    

    always @(negedge I_clk) begin
        if(I_en) begin

            if(I_we)
                regs[I_selD] = I_dataD;
                

            O_dataA <= regs[I_selA];
            O_dataB <= regs[I_selB];
        end
    end
endmodule