data/full_repos/permissive/181665138/verilog/capitolo_iii/D_Latch.v
data/verilator_xmls/8e04647f-7248-49d9-a837-72906575653d.xml
module D_Latch(q, qN, s, r, preset_, preclear_, d, c);
    input preset_, preclear_;
    input d, c;
    output s, r;
    output q, qN;


    assign #1 s = d & c;
    assign #1 r = ~d & c;


    assign #2 q = ~((preset_ & r) | qN | ~preclear_);
    assign #2 qN = ~(~preset_ | (s & preclear_) | q);
endmodule
module D_Latch(q, qN, s, r, preset_, preclear_, d, c);

    input preset_, preclear_;
    input d, c;
    output s, r;
    output q, qN;


    assign #1 s = d & c;
    assign #1 r = ~d & c;


    assign #2 q = ~((preset_ & r) | qN | ~preclear_);
    assign #2 qN = ~(~preset_ | (s & preclear_) | q);
endmodule