data/full_repos/permissive/143278/ivltests/shiftl.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/shiftl.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/shiftl.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/shiftl.v:32: Operator SHIFTL expects 2 bits on the LHS, but LHS\'s VARREF \'a\' generates 1 bits.\n                                                                      : ... In instance main.dut\n    c <= (a << 1) | b;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/shiftl.v:32: Operator OR expects 2 bits on the RHS, but RHS\'s VARREF \'b\' generates 1 bits.\n                                                                      : ... In instance main.dut\n    c <= (a << 1) | b;\n                  ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg a, b, clk;
   wire [1:0] c;
   test dut (.clk(clk), .c(c), .a(a), .b(b));

   integer    x;
   (* ivl_synthesis_off *)
   initial begin
      clk = 0;
      for (x = 0 ;  x < 4 ;  x = x+1) begin
	 a = x[1];
	 b = x[0];
	 #1 clk = 1;
	 #1 clk = 0;
	 if (c !== x[1:0]) begin
	    $display("FAILED == x=%0d (ab=%b%b), c=%b", x, a, b, c);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule
module main;


   reg a, b, clk;
   wire [1:0] c;
   test dut (.clk(clk), .c(c), .a(a), .b(b));

   integer    x;
   (* ivl_synthesis_off *)
   initial begin
      clk = 0;
      for (x = 0 ;  x < 4 ;  x = x+1) begin
	 a = x[1];
	 b = x[0];
	 #1 clk = 1;
	 #1 clk = 0;
	 if (c !== x[1:0]) begin
	    $display("FAILED == x=%0d (ab=%b%b), c=%b", x, a, b, c);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule