data/full_repos/permissive/104443190/chen_div.v
 line:13: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:14: Unsupported: Ignoring delay on this delayed statement.\n initial #30 rst=1;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:15: Unsupported: Ignoring delay on this delayed statement.\n always#10 clk=~clk;\n       ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module chen_unsigned_div ( clk,rst_n,divide_en,dividend,divisor,divide_error,divide_done,quotient,remainde );  

	parameter width = 32;

	input clk;
	input rst_n;
	input divide_en;
	input[width-1:0] dividend;   
	input[width-1:0] divisor;  
	
	output divide_error;
	output divide_done;
	output [width-1:0] quotient;
	output [width-1:0] remainde;


	
	reg temp_en;
	reg[width*2-1:0] temp_a;  
	reg[width*2-1:0] temp_b; 

	reg divide_error_temp;

	always@(posedge clk)
	if(~rst_n)
		begin
			divide_error_temp <= 0;
			temp_en <= 0;
			temp_a <= 0;
			temp_b <= 0; 
		end
	else if(divide_en)
		begin
			if( divisor==0 )
				begin
					divide_error_temp <= 1;
					temp_en <= 0;
					temp_a <= 0;
					temp_b <= 0;
				end
			else 
				begin
					divide_error_temp <= 0;
					temp_en <= 1;
					temp_a <= {dividend>>width,dividend};
    				temp_b <= {divisor,divisor>>width};  
    			end
		end
	else 
		begin
			divide_error_temp <= 0;
			temp_en <= 0;
			temp_a <= 0;
			temp_b <= 0; 
		end



	wire [width*2-1:0] a_reg[0:width];
	wire [width*2-1:0] b_reg[0:width];

	assign a_reg[0] = temp_a;
	assign b_reg[0] = temp_b;

	generate
		genvar i;
		for (i = 0; i < width; i = i + 1)
		begin:shift_compute
			shift_compute#(
				 .width(width*2)
			) inst_shift_compute ( 
				.clk(clk),
				.a_i(a_reg[i]),
				.b_i(b_reg[i]),
				.a_o(a_reg[i+1]),
				.b_o(b_reg[i+1]) 
				);
		end
	endgenerate



	reg [width:0] divide_en_shift_reg;
	reg [width-1:0] divide_error_temp_shift_reg;

	reg divide_error;
	reg divide_done;
	reg [width-1:0] quotient;
	reg [width-1:0] remainde;

	always@(posedge clk)
	if(~rst_n)
		begin
			divide_en_shift_reg <= 0;
			divide_error_temp_shift_reg <= 0;

			divide_error <= 0;
			divide_done <= 0;
			quotient <= 0;
			remainde <= 0;
		end
	else 
		begin
			divide_en_shift_reg <= {divide_en_shift_reg[width-1:0],divide_en};
			divide_error_temp_shift_reg <= {divide_error_temp_shift_reg[width-2:0],divide_error_temp};

			divide_error <= divide_error_temp_shift_reg[width-1];
			divide_done <= divide_en_shift_reg[width];
			quotient <= divide_en_shift_reg[width]?a_reg[width][width-1:0]:0;  
			remainde <= divide_en_shift_reg[width]?a_reg[width][width*2-1:width]:0; 
		end

  
endmodule
module chen_unsigned_div ( clk,rst_n,divide_en,dividend,divisor,divide_error,divide_done,quotient,remainde );
  

	parameter width = 32;

	input clk;
	input rst_n;
	input divide_en;
	input[width-1:0] dividend;   
	input[width-1:0] divisor;  
	
	output divide_error;
	output divide_done;
	output [width-1:0] quotient;
	output [width-1:0] remainde;


	
	reg temp_en;
	reg[width*2-1:0] temp_a;  
	reg[width*2-1:0] temp_b; 

	reg divide_error_temp;

	always@(posedge clk)
	if(~rst_n)
		begin
			divide_error_temp <= 0;
			temp_en <= 0;
			temp_a <= 0;
			temp_b <= 0; 
		end
	else if(divide_en)
		begin
			if( divisor==0 )
				begin
					divide_error_temp <= 1;
					temp_en <= 0;
					temp_a <= 0;
					temp_b <= 0;
				end
			else 
				begin
					divide_error_temp <= 0;
					temp_en <= 1;
					temp_a <= {dividend>>width,dividend};
    				temp_b <= {divisor,divisor>>width};  
    			end
		end
	else 
		begin
			divide_error_temp <= 0;
			temp_en <= 0;
			temp_a <= 0;
			temp_b <= 0; 
		end



	wire [width*2-1:0] a_reg[0:width];
	wire [width*2-1:0] b_reg[0:width];

	assign a_reg[0] = temp_a;
	assign b_reg[0] = temp_b;

	generate
		genvar i;
		for (i = 0; i < width; i = i + 1)
		begin:shift_compute
			shift_compute#(
				 .width(width*2)
			) inst_shift_compute ( 
				.clk(clk),
				.a_i(a_reg[i]),
				.b_i(b_reg[i]),
				.a_o(a_reg[i+1]),
				.b_o(b_reg[i+1]) 
				);
		end
	endgenerate



	reg [width:0] divide_en_shift_reg;
	reg [width-1:0] divide_error_temp_shift_reg;

	reg divide_error;
	reg divide_done;
	reg [width-1:0] quotient;
	reg [width-1:0] remainde;

	always@(posedge clk)
	if(~rst_n)
		begin
			divide_en_shift_reg <= 0;
			divide_error_temp_shift_reg <= 0;

			divide_error <= 0;
			divide_done <= 0;
			quotient <= 0;
			remainde <= 0;
		end
	else 
		begin
			divide_en_shift_reg <= {divide_en_shift_reg[width-1:0],divide_en};
			divide_error_temp_shift_reg <= {divide_error_temp_shift_reg[width-2:0],divide_error_temp};

			divide_error <= divide_error_temp_shift_reg[width-1];
			divide_done <= divide_en_shift_reg[width];
			quotient <= divide_en_shift_reg[width]?a_reg[width][width-1:0]:0;  
			remainde <= divide_en_shift_reg[width]?a_reg[width][width*2-1:width]:0; 
		end

  
endmodule