data/full_repos/permissive/174783592/FloatAdd/Adder/kpgCmpTB.v
 line:40: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/174783592/FloatAdd/Adder/kpgCmpTB.v:34: Unsupported: Ignoring delay on this delayed statement.\n always #32 xi1[1]= ~xi1[1];\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174783592/FloatAdd/Adder/kpgCmpTB.v:35: Unsupported: Ignoring delay on this delayed statement.\n always #16 xi1[0] = ~xi1[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174783592/FloatAdd/Adder/kpgCmpTB.v:36: Unsupported: Ignoring delay on this delayed statement.\n always #8 xi[1] = ~xi[1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174783592/FloatAdd/Adder/kpgCmpTB.v:37: Unsupported: Ignoring delay on this delayed statement.\n always #4 xi[0] = ~xi[0]; \n        ^\n%Error: data/full_repos/permissive/174783592/FloatAdd/Adder/kpgCmpTB.v:39: Unsupported or unknown PLI call: $monitor\n initial $monitor ($time,"xi1=%b,xi=%b,out=%b",xi1,xi,out);\n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174783592/FloatAdd/Adder/kpgCmpTB.v:40: Unsupported: Ignoring delay on this delayed statement.\n initial #128 $finish;\n         ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module kgpCmpTB();
	reg [1:0] xi;
       	reg [1:0] xi1;
	wire [1:0]out;
	
	 kpgCmp cmp1(xi, xi1, out);
	initial
	begin
		xi= 2'b00;
		xi1= 2'b00;	
	end
	always	#32 xi1[1]= ~xi1[1];
	always #16 xi1[0] = ~xi1[0];
	always #8 xi[1] = ~xi[1];
	always #4 xi[0] = ~xi[0];	

	initial $monitor ($time,"xi1=%b,xi=%b,out=%b",xi1,xi,out);
	initial #128 $finish;
endmodule
module kgpCmpTB();

	reg [1:0] xi;
       	reg [1:0] xi1;
	wire [1:0]out;
	
	 kpgCmp cmp1(xi, xi1, out);
	initial
	begin
		xi= 2'b00;
		xi1= 2'b00;	
	end
	always	#32 xi1[1]= ~xi1[1];
	always #16 xi1[0] = ~xi1[0];
	always #8 xi[1] = ~xi[1];
	always #4 xi[0] = ~xi[0];	

	initial $monitor ($time,"xi1=%b,xi=%b,out=%b",xi1,xi,out);
	initial #128 $finish;
endmodule