data/full_repos/permissive/157494568/Part1/t_flip_flop.v
data/verilator_xmls/1c0c7287-aff9-40f4-ad58-e52aef37bb3d.xml
module t_flip_flop(clk, T, Q);

input T, clk;
output reg Q;

initial begin
	Q = 0;
end 

always @ (posedge clk) begin

	if (T == 1)
		Q = ~Q;
	else
		Q = Q;
end

endmodule
module t_flip_flop(clk, T, Q);


input T, clk;
output reg Q;

initial begin
	Q = 0;
end 

always @ (posedge clk) begin

	if (T == 1)
		Q = ~Q;
	else
		Q = Q;
end

endmodule