data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v
1: b'%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:3: Cannot find include file: ../../define/global_def.v\n`include "../../define/global_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147520230/src/cpu/stage/EX,data/full_repos/permissive/147520230/../../define/global_def.v\n             data/full_repos/permissive/147520230/src/cpu/stage/EX,data/full_repos/permissive/147520230/../../define/global_def.v.v\n             data/full_repos/permissive/147520230/src/cpu/stage/EX,data/full_repos/permissive/147520230/../../define/global_def.v.sv\n             ../../define/global_def.v\n             ../../define/global_def.v.v\n             ../../define/global_def.v.sv\n             obj_dir/../../define/global_def.v\n             obj_dir/../../define/global_def.v.v\n             obj_dir/../../define/global_def.v.sv\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:4: Cannot find include file: ../../define/funct_def.v\n`include "../../define/funct_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:7: Define or directive not defined: \'`FUNCT_BUS\'\n    input   wire[`FUNCT_BUS]    funct,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`FUNCT_BUS]    funct,\n                           ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:8: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     operand_1,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:9: Define or directive not defined: \'`DATA_BUS\'\n    input   wire[`DATA_BUS]     operand_2,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:10: Define or directive not defined: \'`DATA_BUS\'\n    output  wire[`DATA_BUS]     result_sum,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:12: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                operand_1_lt_operand_2\n    ^~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:17: Define or directive not defined: \'`DATA_BUS\'\n    wire[`DATA_BUS] operand_2_mux   = ((funct == `FUNCT_SUB)    ||\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:17: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`DATA_BUS] operand_2_mux   = ((funct == `FUNCT_SUB)    ||\n                  ^\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:17: Define or directive not defined: \'`FUNCT_SUB\'\n    wire[`DATA_BUS] operand_2_mux   = ((funct == `FUNCT_SUB)    ||\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:18: Define or directive not defined: \'`FUNCT_SUBU\'\n                                       (funct == `FUNCT_SUBU)   ||\n                                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:19: Define or directive not defined: \'`FUNCT_SLT\'\n                                       (funct == `FUNCT_SLT))   ?\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/147520230/src/cpu/stage/EX/Adder.v:30: Define or directive not defined: \'`FUNCT_SLT\'\n    assign  operand_1_lt_operand_2  = (funct == `FUNCT_SLT) ?\n                                                ^~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module  Adder(
    input   wire[`FUNCT_BUS]    funct,
    input   wire[`DATA_BUS]     operand_1,
    input   wire[`DATA_BUS]     operand_2,
    output  wire[`DATA_BUS]     result_sum,
    output  wire                overflow_sum,
    output  wire                operand_1_lt_operand_2
);

    

    wire[`DATA_BUS] operand_2_mux   = ((funct == `FUNCT_SUB)    ||
                                       (funct == `FUNCT_SUBU)   ||
                                       (funct == `FUNCT_SLT))   ?
                                       (~operand_2) + 1 : operand_2;
    

    assign  result_sum      = operand_1 + operand_2_mux;


    assign  overflow_sum    = (!operand_1[31] && !operand_2_mux[31] &&  result_sum[31]) ||
                              ( operand_1[31] &&  operand_2_mux[31] && !result_sum[31]);
    

    assign  operand_1_lt_operand_2  = (funct == `FUNCT_SLT) ?
                                      (( operand_1[31] && !operand_2[31])   ||
                                       (!operand_1[31] && !operand_2[31] && result_sum[31]) ||
                                       ( operand_1[31] &&  operand_2[31] && result_sum[31]))
                                      : (operand_1 < operand_2);

endmodule
module  Adder(
    input   wire[`FUNCT_BUS]    funct,
    input   wire[`DATA_BUS]     operand_1,
    input   wire[`DATA_BUS]     operand_2,
    output  wire[`DATA_BUS]     result_sum,
    output  wire                overflow_sum,
    output  wire                operand_1_lt_operand_2
);


    

    wire[`DATA_BUS] operand_2_mux   = ((funct == `FUNCT_SUB)    ||
                                       (funct == `FUNCT_SUBU)   ||
                                       (funct == `FUNCT_SLT))   ?
                                       (~operand_2) + 1 : operand_2;
    

    assign  result_sum      = operand_1 + operand_2_mux;


    assign  overflow_sum    = (!operand_1[31] && !operand_2_mux[31] &&  result_sum[31]) ||
                              ( operand_1[31] &&  operand_2_mux[31] && !result_sum[31]);
    

    assign  operand_1_lt_operand_2  = (funct == `FUNCT_SLT) ?
                                      (( operand_1[31] && !operand_2[31])   ||
                                       (!operand_1[31] && !operand_2[31] && result_sum[31]) ||
                                       ( operand_1[31] &&  operand_2[31] && result_sum[31]))
                                      : (operand_1 < operand_2);

endmodule