data/full_repos/permissive/189158922/verilog_src/axi_lite.v
data/verilator_xmls/12cdd878-f0bc-4b32-bee0-fb239650cfea.xml
module top(s_axi_ri__arid, s_axi_wi__awvalid, s_axi_wi__awid, s_axi_aclk, s_axi_areset_n, m_axi_ri__arready, m_axi_ri__rdata, m_axi_ri__rresp, m_axi_ri__rvalid, s_axi_ri__araddr, s_axi_ri__arprot, s_axi_ri__rready, m_axi_wi__awready, m_axi_wi__wready, m_axi_wi__bresp, m_axi_wi__bvalid, s_axi_wi__awaddr, s_axi_wi__awprot, s_axi_wi__wdata, s_axi_wi__wstrb, s_axi_wi__wvalid, s_axi_wi__bready, rst, clk, s_axi_ro__arready, s_axi_ro__rid, s_axi_ro__rdata, s_axi_ro__rlast, s_axi_ro__rresp, s_axi_ro__rvalid, s_axi_wo__awready, s_axi_wo__wready, s_axi_wo__bid, s_axi_wo__bresp, s_axi_wo__bvalid, m_axi_ro__araddr, m_axi_ro__arprot, m_axi_ro__arvalid, m_axi_ro__rready, m_axi_wo__awaddr, m_axi_wo__awprot, m_axi_wo__awvalid, m_axi_wo__wdata, m_axi_wo__wstrb, m_axi_wo__wvalid, m_axi_wo__bready, m_axi_aclk, m_axi_areset_n, s_axi_ri__arvalid);
  (* src = "axi_lite.py:53" *)
  reg \$next\m_axi_aclk ;
  (* src = "axi_lite.py:54" *)
  reg \$next\m_axi_areset_n ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [31:0] \$next\m_axi_ro__araddr ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [2:0] \$next\m_axi_ro__arprot ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_ro__arvalid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_ro__rready ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [31:0] \$next\m_axi_wo__awaddr ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [2:0] \$next\m_axi_wo__awprot ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__awvalid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__bready ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [31:0] \$next\m_axi_wo__wdata ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [3:0] \$next\m_axi_wo__wstrb ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__wvalid ;
  (* src = "axi_lite.py:97" *)
  reg [11:0] \$next\rwid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\s_axi_ro__arready ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [31:0] \$next\s_axi_ro__rdata ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [11:0] \$next\s_axi_ro__rid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\s_axi_ro__rlast ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [1:0] \$next\s_axi_ro__rresp ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\s_axi_ro__rvalid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\s_axi_wo__awready ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [11:0] \$next\s_axi_wo__bid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [1:0] \$next\s_axi_wo__bresp ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\s_axi_wo__bvalid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\s_axi_wo__wready ;
  (* init = 1'h0 *)
  reg \$verilog_initial_trigger  = 1'h0;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* src = "axi_lite.py:53" *)
  output m_axi_aclk;
  (* src = "axi_lite.py:54" *)
  output m_axi_areset_n;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_ri__arready;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [31:0] m_axi_ri__rdata;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [1:0] m_axi_ri__rresp;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_ri__rvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [31:0] m_axi_ro__araddr;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [2:0] m_axi_ro__arprot;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_ro__arvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_ro__rready;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_wi__awready;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [1:0] m_axi_wi__bresp;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_wi__bvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_wi__wready;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [31:0] m_axi_wo__awaddr;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [2:0] m_axi_wo__awprot;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__awvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__bready;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [31:0] m_axi_wo__wdata;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [3:0] m_axi_wo__wstrb;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__wvalid;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* init = 12'h000 *)
  (* src = "axi_lite.py:97" *)
  reg [11:0] rwid = 12'h000;
  (* src = "axi_lite.py:43" *)
  input s_axi_aclk;
  (* src = "axi_lite.py:44" *)
  input s_axi_areset_n;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [31:0] s_axi_ri__araddr;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [11:0] s_axi_ri__arid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [2:0] s_axi_ri__arprot;
  (* src = "nmigen/hdl/rec.py:84" *)
  input s_axi_ri__arvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input s_axi_ri__rready;
  (* src = "nmigen/hdl/rec.py:84" *)
  output s_axi_ro__arready;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [31:0] s_axi_ro__rdata;
  (* init = 12'h000 *)
  (* src = "nmigen/hdl/rec.py:84" *)
  output [11:0] s_axi_ro__rid;
  reg [11:0] s_axi_ro__rid = 12'h000;
  (* src = "nmigen/hdl/rec.py:84" *)
  output s_axi_ro__rlast;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [1:0] s_axi_ro__rresp;
  (* src = "nmigen/hdl/rec.py:84" *)
  output s_axi_ro__rvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [31:0] s_axi_wi__awaddr;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [11:0] s_axi_wi__awid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [2:0] s_axi_wi__awprot;
  (* src = "nmigen/hdl/rec.py:84" *)
  input s_axi_wi__awvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input s_axi_wi__bready;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [31:0] s_axi_wi__wdata;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [3:0] s_axi_wi__wstrb;
  (* src = "nmigen/hdl/rec.py:84" *)
  input s_axi_wi__wvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output s_axi_wo__awready;
  (* init = 12'h000 *)
  (* src = "nmigen/hdl/rec.py:84" *)
  output [11:0] s_axi_wo__bid;
  reg [11:0] s_axi_wo__bid = 12'h000;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [1:0] s_axi_wo__bresp;
  (* src = "nmigen/hdl/rec.py:84" *)
  output s_axi_wo__bvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output s_axi_wo__wready;
  always @(posedge clk)
      s_axi_wo__bid <= \$next\s_axi_wo__bid ;
  always @(posedge clk)
      s_axi_ro__rid <= \$next\s_axi_ro__rid ;
  always @(posedge clk)
      rwid <= \$next\rwid ;
  always @* begin
    \$next\rwid  = rwid;
    casez (s_axi_ri__arvalid)
      1'h1:
          \$next\rwid  = s_axi_ri__arid;
    endcase
    casez (s_axi_wi__awvalid)
      1'h1:
          \$next\rwid  = s_axi_wi__awid;
    endcase
    casez (rst)
      1'h1:
          \$next\rwid  = 12'h000;
    endcase
  end
  always @* begin
    \$next\s_axi_ro__rid  = s_axi_ro__rid;
    \$next\s_axi_ro__rid  = rwid;
    casez (rst)
      1'h1:
          \$next\s_axi_ro__rid  = 12'h000;
    endcase
  end
  always @* begin
    \$next\m_axi_ro__araddr  = 32'd0;
    \$next\m_axi_ro__araddr  = s_axi_ri__araddr;
  end
  always @* begin
    \$next\m_axi_ro__arprot  = 3'h0;
    \$next\m_axi_ro__arprot  = s_axi_ri__arprot;
  end
  always @* begin
    \$next\m_axi_ro__arvalid  = 1'h0;
    \$next\m_axi_ro__arvalid  = s_axi_ri__arvalid;
  end
  always @* begin
    \$next\m_axi_ro__rready  = 1'h0;
    \$next\m_axi_ro__rready  = s_axi_ri__rready;
  end
  always @* begin
    \$next\s_axi_wo__awready  = 1'h0;
    \$next\s_axi_wo__awready  = m_axi_wi__awready;
  end
  always @* begin
    \$next\s_axi_wo__wready  = 1'h0;
    \$next\s_axi_wo__wready  = m_axi_wi__wready;
  end
  always @* begin
    \$next\s_axi_wo__bresp  = 2'h0;
    \$next\s_axi_wo__bresp  = m_axi_wi__bresp;
  end
  always @* begin
    \$next\s_axi_wo__bvalid  = 1'h0;
    \$next\s_axi_wo__bvalid  = m_axi_wi__bvalid;
  end
  always @* begin
    \$next\m_axi_wo__awaddr  = 32'd0;
    \$next\m_axi_wo__awaddr  = s_axi_wi__awaddr;
  end
  always @* begin
    \$next\m_axi_wo__awprot  = 3'h0;
    \$next\m_axi_wo__awprot  = s_axi_wi__awprot;
  end
  always @* begin
    \$next\s_axi_wo__bid  = s_axi_wo__bid;
    \$next\s_axi_wo__bid  = rwid;
    casez (rst)
      1'h1:
          \$next\s_axi_wo__bid  = 12'h000;
    endcase
  end
  always @* begin
    \$next\m_axi_wo__awvalid  = 1'h0;
    \$next\m_axi_wo__awvalid  = s_axi_wi__awvalid;
  end
  always @* begin
    \$next\m_axi_wo__wdata  = 32'd0;
    \$next\m_axi_wo__wdata  = s_axi_wi__wdata;
  end
  always @* begin
    \$next\m_axi_wo__wstrb  = 4'h0;
    \$next\m_axi_wo__wstrb  = s_axi_wi__wstrb;
  end
  always @* begin
    \$next\m_axi_wo__wvalid  = 1'h0;
    \$next\m_axi_wo__wvalid  = s_axi_wi__wvalid;
  end
  always @* begin
    \$next\m_axi_wo__bready  = 1'h0;
    \$next\m_axi_wo__bready  = s_axi_wi__bready;
  end
  always @* begin
    \$next\m_axi_aclk  = 1'h0;
    \$next\m_axi_aclk  = s_axi_aclk;
  end
  always @* begin
    \$next\m_axi_areset_n  = 1'h0;
    \$next\m_axi_areset_n  = s_axi_areset_n;
  end
  always @* begin
    \$next\s_axi_ro__arready  = 1'h0;
    \$next\s_axi_ro__arready  = m_axi_ri__arready;
  end
  always @* begin
    \$next\s_axi_ro__rdata  = 32'd0;
    \$next\s_axi_ro__rdata  = m_axi_ri__rdata;
  end
  always @* begin
    \$next\s_axi_ro__rlast  = 1'h0;
    \$next\s_axi_ro__rlast  = 1'h1;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\s_axi_ro__rresp  = 2'h0;
    \$next\s_axi_ro__rresp  = m_axi_ri__rresp;
  end
  always @* begin
    \$next\s_axi_ro__rvalid  = 1'h0;
    \$next\s_axi_ro__rvalid  = m_axi_ri__rvalid;
  end
  assign m_axi_wo__bready = \$next\m_axi_wo__bready ;
  assign m_axi_wo__wvalid = \$next\m_axi_wo__wvalid ;
  assign m_axi_wo__wstrb = \$next\m_axi_wo__wstrb ;
  assign m_axi_wo__wdata = \$next\m_axi_wo__wdata ;
  assign m_axi_wo__awvalid = \$next\m_axi_wo__awvalid ;
  assign m_axi_wo__awprot = \$next\m_axi_wo__awprot ;
  assign m_axi_wo__awaddr = \$next\m_axi_wo__awaddr ;
  assign s_axi_wo__bvalid = \$next\s_axi_wo__bvalid ;
  assign s_axi_wo__bresp = \$next\s_axi_wo__bresp ;
  assign s_axi_wo__wready = \$next\s_axi_wo__wready ;
  assign s_axi_wo__awready = \$next\s_axi_wo__awready ;
  assign m_axi_ro__rready = \$next\m_axi_ro__rready ;
  assign m_axi_ro__arvalid = \$next\m_axi_ro__arvalid ;
  assign m_axi_ro__arprot = \$next\m_axi_ro__arprot ;
  assign m_axi_ro__araddr = \$next\m_axi_ro__araddr ;
  assign s_axi_ro__rvalid = \$next\s_axi_ro__rvalid ;
  assign s_axi_ro__rresp = \$next\s_axi_ro__rresp ;
  assign s_axi_ro__rlast = \$next\s_axi_ro__rlast ;
  assign s_axi_ro__rdata = \$next\s_axi_ro__rdata ;
  assign s_axi_ro__arready = \$next\s_axi_ro__arready ;
  assign m_axi_areset_n = \$next\m_axi_areset_n ;
  assign m_axi_aclk = \$next\m_axi_aclk ;
endmodule
module top(s_axi_ri__arid, s_axi_wi__awvalid, s_axi_wi__awid, s_axi_aclk, s_axi_areset_n, m_axi_ri__arready, m_axi_ri__rdata, m_axi_ri__rresp, m_axi_ri__rvalid, s_axi_ri__araddr, s_axi_ri__arprot, s_axi_ri__rready, m_axi_wi__awready, m_axi_wi__wready, m_axi_wi__bresp, m_axi_wi__bvalid, s_axi_wi__awaddr, s_axi_wi__awprot, s_axi_wi__wdata, s_axi_wi__wstrb, s_axi_wi__wvalid, s_axi_wi__bready, rst, clk, s_axi_ro__arready, s_axi_ro__rid, s_axi_ro__rdata, s_axi_ro__rlast, s_axi_ro__rresp, s_axi_ro__rvalid, s_axi_wo__awready, s_axi_wo__wready, s_axi_wo__bid, s_axi_wo__bresp, s_axi_wo__bvalid, m_axi_ro__araddr, m_axi_ro__arprot, m_axi_ro__arvalid, m_axi_ro__rready, m_axi_wo__awaddr, m_axi_wo__awprot, m_axi_wo__awvalid, m_axi_wo__wdata, m_axi_wo__wstrb, m_axi_wo__wvalid, m_axi_wo__bready, m_axi_aclk, m_axi_areset_n, s_axi_ri__arvalid);

  (* src = "axi_lite.py:53" *)
  reg \$next\m_axi_aclk ;
  (* src = "axi_lite.py:54" *)
  reg \$next\m_axi_areset_n ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [31:0] \$next\m_axi_ro__araddr ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [2:0] \$next\m_axi_ro__arprot ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_ro__arvalid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_ro__rready ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [31:0] \$next\m_axi_wo__awaddr ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [2:0] \$next\m_axi_wo__awprot ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__awvalid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__bready ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [31:0] \$next\m_axi_wo__wdata ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [3:0] \$next\m_axi_wo__wstrb ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__wvalid ;
  (* src = "axi_lite.py:97" *)
  reg [11:0] \$next\rwid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\s_axi_ro__arready ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [31:0] \$next\s_axi_ro__rdata ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [11:0] \$next\s_axi_ro__rid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\s_axi_ro__rlast ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [1:0] \$next\s_axi_ro__rresp ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\s_axi_ro__rvalid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\s_axi_wo__awready ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [11:0] \$next\s_axi_wo__bid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [1:0] \$next\s_axi_wo__bresp ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\s_axi_wo__bvalid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\s_axi_wo__wready ;
  (* init = 1'h0 *)
  reg \$verilog_initial_trigger  = 1'h0;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* src = "axi_lite.py:53" *)
  output m_axi_aclk;
  (* src = "axi_lite.py:54" *)
  output m_axi_areset_n;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_ri__arready;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [31:0] m_axi_ri__rdata;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [1:0] m_axi_ri__rresp;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_ri__rvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [31:0] m_axi_ro__araddr;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [2:0] m_axi_ro__arprot;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_ro__arvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_ro__rready;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_wi__awready;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [1:0] m_axi_wi__bresp;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_wi__bvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_wi__wready;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [31:0] m_axi_wo__awaddr;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [2:0] m_axi_wo__awprot;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__awvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__bready;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [31:0] m_axi_wo__wdata;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [3:0] m_axi_wo__wstrb;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__wvalid;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* init = 12'h000 *)
  (* src = "axi_lite.py:97" *)
  reg [11:0] rwid = 12'h000;
  (* src = "axi_lite.py:43" *)
  input s_axi_aclk;
  (* src = "axi_lite.py:44" *)
  input s_axi_areset_n;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [31:0] s_axi_ri__araddr;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [11:0] s_axi_ri__arid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [2:0] s_axi_ri__arprot;
  (* src = "nmigen/hdl/rec.py:84" *)
  input s_axi_ri__arvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input s_axi_ri__rready;
  (* src = "nmigen/hdl/rec.py:84" *)
  output s_axi_ro__arready;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [31:0] s_axi_ro__rdata;
  (* init = 12'h000 *)
  (* src = "nmigen/hdl/rec.py:84" *)
  output [11:0] s_axi_ro__rid;
  reg [11:0] s_axi_ro__rid = 12'h000;
  (* src = "nmigen/hdl/rec.py:84" *)
  output s_axi_ro__rlast;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [1:0] s_axi_ro__rresp;
  (* src = "nmigen/hdl/rec.py:84" *)
  output s_axi_ro__rvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [31:0] s_axi_wi__awaddr;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [11:0] s_axi_wi__awid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [2:0] s_axi_wi__awprot;
  (* src = "nmigen/hdl/rec.py:84" *)
  input s_axi_wi__awvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input s_axi_wi__bready;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [31:0] s_axi_wi__wdata;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [3:0] s_axi_wi__wstrb;
  (* src = "nmigen/hdl/rec.py:84" *)
  input s_axi_wi__wvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output s_axi_wo__awready;
  (* init = 12'h000 *)
  (* src = "nmigen/hdl/rec.py:84" *)
  output [11:0] s_axi_wo__bid;
  reg [11:0] s_axi_wo__bid = 12'h000;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [1:0] s_axi_wo__bresp;
  (* src = "nmigen/hdl/rec.py:84" *)
  output s_axi_wo__bvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output s_axi_wo__wready;
  always @(posedge clk)
      s_axi_wo__bid <= \$next\s_axi_wo__bid ;
  always @(posedge clk)
      s_axi_ro__rid <= \$next\s_axi_ro__rid ;
  always @(posedge clk)
      rwid <= \$next\rwid ;
  always @* begin
    \$next\rwid  = rwid;
    casez (s_axi_ri__arvalid)
      1'h1:
          \$next\rwid  = s_axi_ri__arid;
    endcase
    casez (s_axi_wi__awvalid)
      1'h1:
          \$next\rwid  = s_axi_wi__awid;
    endcase
    casez (rst)
      1'h1:
          \$next\rwid  = 12'h000;
    endcase
  end
  always @* begin
    \$next\s_axi_ro__rid  = s_axi_ro__rid;
    \$next\s_axi_ro__rid  = rwid;
    casez (rst)
      1'h1:
          \$next\s_axi_ro__rid  = 12'h000;
    endcase
  end
  always @* begin
    \$next\m_axi_ro__araddr  = 32'd0;
    \$next\m_axi_ro__araddr  = s_axi_ri__araddr;
  end
  always @* begin
    \$next\m_axi_ro__arprot  = 3'h0;
    \$next\m_axi_ro__arprot  = s_axi_ri__arprot;
  end
  always @* begin
    \$next\m_axi_ro__arvalid  = 1'h0;
    \$next\m_axi_ro__arvalid  = s_axi_ri__arvalid;
  end
  always @* begin
    \$next\m_axi_ro__rready  = 1'h0;
    \$next\m_axi_ro__rready  = s_axi_ri__rready;
  end
  always @* begin
    \$next\s_axi_wo__awready  = 1'h0;
    \$next\s_axi_wo__awready  = m_axi_wi__awready;
  end
  always @* begin
    \$next\s_axi_wo__wready  = 1'h0;
    \$next\s_axi_wo__wready  = m_axi_wi__wready;
  end
  always @* begin
    \$next\s_axi_wo__bresp  = 2'h0;
    \$next\s_axi_wo__bresp  = m_axi_wi__bresp;
  end
  always @* begin
    \$next\s_axi_wo__bvalid  = 1'h0;
    \$next\s_axi_wo__bvalid  = m_axi_wi__bvalid;
  end
  always @* begin
    \$next\m_axi_wo__awaddr  = 32'd0;
    \$next\m_axi_wo__awaddr  = s_axi_wi__awaddr;
  end
  always @* begin
    \$next\m_axi_wo__awprot  = 3'h0;
    \$next\m_axi_wo__awprot  = s_axi_wi__awprot;
  end
  always @* begin
    \$next\s_axi_wo__bid  = s_axi_wo__bid;
    \$next\s_axi_wo__bid  = rwid;
    casez (rst)
      1'h1:
          \$next\s_axi_wo__bid  = 12'h000;
    endcase
  end
  always @* begin
    \$next\m_axi_wo__awvalid  = 1'h0;
    \$next\m_axi_wo__awvalid  = s_axi_wi__awvalid;
  end
  always @* begin
    \$next\m_axi_wo__wdata  = 32'd0;
    \$next\m_axi_wo__wdata  = s_axi_wi__wdata;
  end
  always @* begin
    \$next\m_axi_wo__wstrb  = 4'h0;
    \$next\m_axi_wo__wstrb  = s_axi_wi__wstrb;
  end
  always @* begin
    \$next\m_axi_wo__wvalid  = 1'h0;
    \$next\m_axi_wo__wvalid  = s_axi_wi__wvalid;
  end
  always @* begin
    \$next\m_axi_wo__bready  = 1'h0;
    \$next\m_axi_wo__bready  = s_axi_wi__bready;
  end
  always @* begin
    \$next\m_axi_aclk  = 1'h0;
    \$next\m_axi_aclk  = s_axi_aclk;
  end
  always @* begin
    \$next\m_axi_areset_n  = 1'h0;
    \$next\m_axi_areset_n  = s_axi_areset_n;
  end
  always @* begin
    \$next\s_axi_ro__arready  = 1'h0;
    \$next\s_axi_ro__arready  = m_axi_ri__arready;
  end
  always @* begin
    \$next\s_axi_ro__rdata  = 32'd0;
    \$next\s_axi_ro__rdata  = m_axi_ri__rdata;
  end
  always @* begin
    \$next\s_axi_ro__rlast  = 1'h0;
    \$next\s_axi_ro__rlast  = 1'h1;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\s_axi_ro__rresp  = 2'h0;
    \$next\s_axi_ro__rresp  = m_axi_ri__rresp;
  end
  always @* begin
    \$next\s_axi_ro__rvalid  = 1'h0;
    \$next\s_axi_ro__rvalid  = m_axi_ri__rvalid;
  end
  assign m_axi_wo__bready = \$next\m_axi_wo__bready ;
  assign m_axi_wo__wvalid = \$next\m_axi_wo__wvalid ;
  assign m_axi_wo__wstrb = \$next\m_axi_wo__wstrb ;
  assign m_axi_wo__wdata = \$next\m_axi_wo__wdata ;
  assign m_axi_wo__awvalid = \$next\m_axi_wo__awvalid ;
  assign m_axi_wo__awprot = \$next\m_axi_wo__awprot ;
  assign m_axi_wo__awaddr = \$next\m_axi_wo__awaddr ;
  assign s_axi_wo__bvalid = \$next\s_axi_wo__bvalid ;
  assign s_axi_wo__bresp = \$next\s_axi_wo__bresp ;
  assign s_axi_wo__wready = \$next\s_axi_wo__wready ;
  assign s_axi_wo__awready = \$next\s_axi_wo__awready ;
  assign m_axi_ro__rready = \$next\m_axi_ro__rready ;
  assign m_axi_ro__arvalid = \$next\m_axi_ro__arvalid ;
  assign m_axi_ro__arprot = \$next\m_axi_ro__arprot ;
  assign m_axi_ro__araddr = \$next\m_axi_ro__araddr ;
  assign s_axi_ro__rvalid = \$next\s_axi_ro__rvalid ;
  assign s_axi_ro__rresp = \$next\s_axi_ro__rresp ;
  assign s_axi_ro__rlast = \$next\s_axi_ro__rlast ;
  assign s_axi_ro__rdata = \$next\s_axi_ro__rdata ;
  assign s_axi_ro__arready = \$next\s_axi_ro__arready ;
  assign m_axi_areset_n = \$next\m_axi_areset_n ;
  assign m_axi_aclk = \$next\m_axi_aclk ;
endmodule