data/full_repos/permissive/133651929/late_1_rx_TB.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #30;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #15 rst     = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #15 rst     = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #50 enable  = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10 wr_en   = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #15 rx     = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #15 rx     = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #15 rx     = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #15 rx     = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #15 rx     = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #15 rx     = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #15 rx     = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #15 rx     = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #20 rx     = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133651929/late_1_rx_TB.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #500 $finish;         \n  ^\n%Error: data/full_repos/permissive/133651929/late_1_rx_TB.v:16: Cannot find file containing module: \'late_1_rx\'\n late_1_rx uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133651929,data/full_repos/permissive/133651929/late_1_rx\n             data/full_repos/permissive/133651929,data/full_repos/permissive/133651929/late_1_rx.v\n             data/full_repos/permissive/133651929,data/full_repos/permissive/133651929/late_1_rx.sv\n             late_1_rx\n             late_1_rx.v\n             late_1_rx.sv\n             obj_dir/late_1_rx\n             obj_dir/late_1_rx.v\n             obj_dir/late_1_rx.sv\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module late_1_rx_TB;


	reg clk;
	reg rst;
	reg enable;
	reg wr_en;
	reg rx;


	wire [7:0]rx_data;


	late_1_rx uut (
		.clk(clk), 
		.rst(rst), 
		.enable(enable), 
		.wr_en(wr_en), 
		.rx(rx), 
		.rx_data(rx_data)
	);

	initial 
	begin
		clk = 0;
		forever 
		begin
		clk = #5! clk;
		end
	end

	initial
		begin
		rst = 0;
		enable = 0;
		wr_en = 0;
		rx = 0;


		#30;
        
		
		#15 rst     = 1'b1;
		#15 rst     = 1'b0;
		
		#50 enable  = 1'b1;
		#10 wr_en   = 1'b1;
		
		#15 rx	    = 1;
		#15 rx	    = 0;
		#15 rx	    = 0;
		#15 rx	    = 1;
		#15 rx	    = 1;
		#15 rx	    = 0;
		#15 rx	    = 0;
		#15 rx	    = 1;
		
		







		#20 rx	    = 0;







		
		
		#500 $finish;

	end
      
endmodule
module late_1_rx_TB;



	reg clk;
	reg rst;
	reg enable;
	reg wr_en;
	reg rx;


	wire [7:0]rx_data;


	late_1_rx uut (
		.clk(clk), 
		.rst(rst), 
		.enable(enable), 
		.wr_en(wr_en), 
		.rx(rx), 
		.rx_data(rx_data)
	);

	initial 
	begin
		clk = 0;
		forever 
		begin
		clk = #5! clk;
		end
	end

	initial
		begin
		rst = 0;
		enable = 0;
		wr_en = 0;
		rx = 0;


		#30;
        
		
		#15 rst     = 1'b1;
		#15 rst     = 1'b0;
		
		#50 enable  = 1'b1;
		#10 wr_en   = 1'b1;
		
		#15 rx	    = 1;
		#15 rx	    = 0;
		#15 rx	    = 0;
		#15 rx	    = 1;
		#15 rx	    = 1;
		#15 rx	    = 0;
		#15 rx	    = 0;
		#15 rx	    = 1;
		
		







		#20 rx	    = 0;







		
		
		#500 $finish;

	end
      
endmodule