data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v
 line:93: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n            #(T_clk / 2);\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n            #(T_clk / 2);\n            ^\n%Error: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:97: syntax error, unexpected \'@\'\n            @(posedge done);\n            ^\n%Error: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:108: syntax error, unexpected \'@\'\n            @(posedge mem);              \n            ^\n%Error: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:122: syntax error, unexpected \'@\'\n                    @(posedge clk);      \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n                    #(T_wp) sram[sram_ctrl_addr] = sram_ctrl_data2ram;\n                    ^\n%Error: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:126: syntax error, unexpected \'@\'\n                    @(posedge clk);      \n                    ^\n%Error: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:132: syntax error, unexpected \'@\'\n                    @(posedge clk);      \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n            #(T_clk / 2) rst = 0;\n            ^\n%Error: data/full_repos/permissive/138713719/sim/addr_bus_test_tb.v:168: syntax error, unexpected \'@\'\n            @(posedge clk) en = 1;\n            ^\n%Error: Exiting due to 6 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module addr_bus_test_tb;
    
    

    
    reg clk;
    reg rst;
    reg en;
    reg ready;
    reg [7:0] data2fpga;
    
    

    
    wire mem;
    wire rw;
    wire [19:0] addr;
    wire [7:0] data2ram;
    wire done;
    wire result;
    
    

    

    localparam T_clk = 20;
    

    localparam T_wp = 8;
    
    

    

    reg [7:0] sram [0:20];
    

    reg [4:0] sram_ctrl_addr;
    reg [7:0] sram_ctrl_data2ram;
    
    

    
    addr_bus_test uut
        (
        .clk(clk), 
        .rst(rst), 
        .en(en), 
        .mem(mem), 
        .rw(rw), 
        .ready(ready), 
        .addr(addr), 
        .data2ram(data2ram), 
        .data2fpga(data2fpga), 
        .done(done), 
        .result(result)
        );
    
    

    

    always
        begin
            clk = 1;
            #(T_clk / 2);
            
            clk = 0;
            #(T_clk / 2);
        end
    
    

    
    initial
        begin
            initialize();
            enable();
            

            @(posedge done);
            @(posedge clk) $stop;
        end
    
    

    

    always
        begin

            @(posedge mem);
            


            @(posedge clk) ready = 0;
            sram_ctrl_addr = bit2addr(addr);
            
            if(!rw)

                begin

                    sram_ctrl_data2ram = data2ram;
                    

                    @(posedge clk);
                    #(T_wp) sram[sram_ctrl_addr] = sram_ctrl_data2ram;
                    

                    @(posedge clk);
                end
            else

                begin

                    @(posedge clk);
                    @(posedge clk);
                    data2fpga = sram[sram_ctrl_addr];
                end
            
            ready = 1;
        end
    
    

    

    task initialize;
        begin
            rst = 0;
            en = 0;
            ready = 1;
            data2fpga = 0;
            sram_ctrl_addr = 0;
            sram_ctrl_data2ram = 0;
            
            reset_async();
        end
    endtask
    

    task reset_async;
        begin
            rst = 1;
            #(T_clk / 2) rst = 0;
        end
    endtask
    

    task enable;
        begin
            @(posedge clk) en = 1;
            @(posedge clk) en = 0;
        end
    endtask
    
    

    


    function [4:0] bit2addr(input [19:0] addr);
        integer a;
        begin            
            a = 0;
            
            while(addr)
                begin
                    addr = addr >> 1;
                    a = a + 1;
                end
            
            bit2addr = a;
        end
    endfunction
    
endmodule
module addr_bus_test_tb;

    
    

    
    reg clk;
    reg rst;
    reg en;
    reg ready;
    reg [7:0] data2fpga;
    
    

    
    wire mem;
    wire rw;
    wire [19:0] addr;
    wire [7:0] data2ram;
    wire done;
    wire result;
    
    

    

    localparam T_clk = 20;
    

    localparam T_wp = 8;
    
    

    

    reg [7:0] sram [0:20];
    

    reg [4:0] sram_ctrl_addr;
    reg [7:0] sram_ctrl_data2ram;
    
    

    
    addr_bus_test uut
        (
        .clk(clk), 
        .rst(rst), 
        .en(en), 
        .mem(mem), 
        .rw(rw), 
        .ready(ready), 
        .addr(addr), 
        .data2ram(data2ram), 
        .data2fpga(data2fpga), 
        .done(done), 
        .result(result)
        );
    
    

    

    always
        begin
            clk = 1;
            #(T_clk / 2);
            
            clk = 0;
            #(T_clk / 2);
        end
    
    

    
    initial
        begin
            initialize();
            enable();
            

            @(posedge done);
            @(posedge clk) $stop;
        end
    
    

    

    always
        begin

            @(posedge mem);
            


            @(posedge clk) ready = 0;
            sram_ctrl_addr = bit2addr(addr);
            
            if(!rw)

                begin

                    sram_ctrl_data2ram = data2ram;
                    

                    @(posedge clk);
                    #(T_wp) sram[sram_ctrl_addr] = sram_ctrl_data2ram;
                    

                    @(posedge clk);
                end
            else

                begin

                    @(posedge clk);
                    @(posedge clk);
                    data2fpga = sram[sram_ctrl_addr];
                end
            
            ready = 1;
        end
    
    

    

    task initialize;
        begin
            rst = 0;
            en = 0;
            ready = 1;
            data2fpga = 0;
            sram_ctrl_addr = 0;
            sram_ctrl_data2ram = 0;
            
            reset_async();
        end
    endtask
    

    task reset_async;
        begin
            rst = 1;
            #(T_clk / 2) rst = 0;
        end
    endtask
    

    task enable;
        begin
            @(posedge clk) en = 1;
            @(posedge clk) en = 0;
        end
    endtask
    
    

    


    function [4:0] bit2addr(input [19:0] addr);
        integer a;
        begin            
            a = 0;
            
            while(addr)
                begin
                    addr = addr >> 1;
                    a = a + 1;
                end
            
            bit2addr = a;
        end
    endfunction
    
endmodule