data/full_repos/permissive/123690745/Interpreter.v
data/verilator_xmls/fce1d3fb-5c0e-4351-8a95-46f2ab3d874a.xml
module Interpreter(
    input [31:0] Instruction,
    output [5:0] Opcode,
    output [5:0] Func,
    output [4:0] RS,
    output [4:0] RT,
    output [4:0] RD,
    output [4:0] Shift,
    output [25:0] InstrIndex,
	 output [15:0] Immediate
    );
	assign Opcode = 		Instruction[31:26];
	assign Func = 			Instruction[5:0];
	assign RS = 			Instruction[25:21];
	assign RT = 			Instruction[20:16];
	assign RD = 			Instruction[15:11];
	assign Shift = 		Instruction[10:6];
	assign InstrIndex = 	Instruction[25:0];
	assign Immediate = 	Instruction[15:0];

endmodule
module Interpreter(
    input [31:0] Instruction,
    output [5:0] Opcode,
    output [5:0] Func,
    output [4:0] RS,
    output [4:0] RT,
    output [4:0] RD,
    output [4:0] Shift,
    output [25:0] InstrIndex,
	 output [15:0] Immediate
    );

	assign Opcode = 		Instruction[31:26];
	assign Func = 			Instruction[5:0];
	assign RS = 			Instruction[25:21];
	assign RT = 			Instruction[20:16];
	assign RD = 			Instruction[15:11];
	assign Shift = 		Instruction[10:6];
	assign InstrIndex = 	Instruction[25:0];
	assign Immediate = 	Instruction[15:0];

endmodule