data/full_repos/permissive/163840441/project/ALU.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/163840441/project/ALU.v:32: Cannot find file containing module: \'AND\'\n    AND and_inst (.a(ALUinA), .b(ALUinB), .r(and_out));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/163840441/project,data/full_repos/permissive/163840441/AND\n             data/full_repos/permissive/163840441/project,data/full_repos/permissive/163840441/AND.v\n             data/full_repos/permissive/163840441/project,data/full_repos/permissive/163840441/AND.sv\n             AND\n             AND.v\n             AND.sv\n             obj_dir/AND\n             obj_dir/AND.v\n             obj_dir/AND.sv\n%Error: data/full_repos/permissive/163840441/project/ALU.v:33: Cannot find file containing module: \'XOR\'\n    XOR xor_inst (.a(ALUinA), .b(ALUinB), .r(xor_out));\n    ^~~\n%Error: data/full_repos/permissive/163840441/project/ALU.v:34: Cannot find file containing module: \'ADD\'\n    ADD add_inst (.a(ALUinA), .b(ALUinB), .r(add_out), .cout(add_cout));\n    ^~~\n%Error: data/full_repos/permissive/163840441/project/ALU.v:35: Cannot find file containing module: \'CircularLeftShift\'\n    CircularLeftShift shift_inst (.a(ALUinA), .r(shift_out));\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/163840441/project/ALU.v:36: Cannot find file containing module: \'ZeroComparator\'\n    ZeroComparator zero_inst (.a(ALUout), .Z(zero_out)); \n    ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/163840441/project/ALU.v:49: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_cout\' generates 1 bits.\n                                                                     : ... In instance ALU\n    assign CoutMux[2] = add_cout;\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/163840441/project/ALU.v:50: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'shift_cout\' generates 1 bits.\n                                                                     : ... In instance ALU\n    assign CoutMux[3] = shift_cout;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/163840441/project/ALU.v:52: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                     : ... In instance ALU\n    assign CO         = CoutMux[InsSel];\n                      ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n'
module ALU(
        input [7:0] ALUinA, ALUinB,
        input [1:0] InsSel,
        output [7:0] ALUout,
        output CO, Z
    );
    wire [7:0] and_out, xor_out, add_out, shift_out;
    wire add_cout, shift_cout, zero_out;
    
    AND and_inst (.a(ALUinA), .b(ALUinB), .r(and_out));
    XOR xor_inst (.a(ALUinA), .b(ALUinB), .r(xor_out));
    ADD add_inst (.a(ALUinA), .b(ALUinB), .r(add_out), .cout(add_cout));
    CircularLeftShift shift_inst (.a(ALUinA), .r(shift_out));
    ZeroComparator zero_inst (.a(ALUout), .Z(zero_out)); 
    
    wire [7:0] OutMux [3:0];
    assign OutMux[0] = and_out;
    assign OutMux[1] = xor_out;
    assign OutMux[2] = add_out;
    assign OutMux[3] = shift_out;
    assign ALUout    = OutMux[InsSel];
    
    wire [7:0] CoutMux [3:0];
    assign shift_cout = shift_out[0];
    assign CoutMux[0] = 0;
    assign CoutMux[1] = 0;
    assign CoutMux[2] = add_cout;
    assign CoutMux[3] = shift_cout;
    
    assign CO         = CoutMux[InsSel];
    assign Z          = zero_out;
endmodule
module ALU(
        input [7:0] ALUinA, ALUinB,
        input [1:0] InsSel,
        output [7:0] ALUout,
        output CO, Z
    );

    wire [7:0] and_out, xor_out, add_out, shift_out;
    wire add_cout, shift_cout, zero_out;
    
    AND and_inst (.a(ALUinA), .b(ALUinB), .r(and_out));
    XOR xor_inst (.a(ALUinA), .b(ALUinB), .r(xor_out));
    ADD add_inst (.a(ALUinA), .b(ALUinB), .r(add_out), .cout(add_cout));
    CircularLeftShift shift_inst (.a(ALUinA), .r(shift_out));
    ZeroComparator zero_inst (.a(ALUout), .Z(zero_out)); 
    
    wire [7:0] OutMux [3:0];
    assign OutMux[0] = and_out;
    assign OutMux[1] = xor_out;
    assign OutMux[2] = add_out;
    assign OutMux[3] = shift_out;
    assign ALUout    = OutMux[InsSel];
    
    wire [7:0] CoutMux [3:0];
    assign shift_cout = shift_out[0];
    assign CoutMux[0] = 0;
    assign CoutMux[1] = 0;
    assign CoutMux[2] = add_cout;
    assign CoutMux[3] = shift_cout;
    
    assign CO         = CoutMux[InsSel];
    assign Z          = zero_out;
endmodule