data/full_repos/permissive/211316121/lab3_3_module/Fulladder.v
data/verilator_xmls/d3934701-e6d5-4daa-b061-e2e133549c1c.xml
module Full_adder(
input A,
input B,
input Cin,
output wire S,
output wire P,
output wire G
    );


assign S=~A&~B&Cin | ~A&B&~Cin | A&~B&~Cin | A&B&Cin;
assign P=A^B;
assign G=A&B;


endmodule
module Full_adder(
input A,
input B,
input Cin,
output wire S,
output wire P,
output wire G
    );



assign S=~A&~B&Cin | ~A&B&~Cin | A&~B&~Cin | A&B&Cin;
assign P=A^B;
assign G=A&B;


endmodule