data/full_repos/permissive/211878730/atlys/practice/xorshift_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/xorshift_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n  forever #1 clk = !clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/xorshift_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/xorshift_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #3;\n  ^\n%Error: data/full_repos/permissive/211878730/atlys/practice/xorshift_test.v:14: Cannot find file containing module: \'xorshift\'\n xorshift uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/xorshift\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/xorshift.v\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/xorshift.sv\n             xorshift\n             xorshift.v\n             xorshift.sv\n             obj_dir/xorshift\n             obj_dir/xorshift.v\n             obj_dir/xorshift.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module xorshift_test;


	reg clk;
	reg reset;


	wire [31:0] q;


	xorshift uut (
		.clk(clk), 
		.reset(reset), 
		.q(q)
	);

	initial begin
		clk = 0;
		reset = 0;
		forever #1 clk = !clk;
	end

	initial begin
		reset = 0;
		#3;
		reset = 1;
		#3;
		reset = 0;
	end
endmodule
module xorshift_test;



	reg clk;
	reg reset;


	wire [31:0] q;


	xorshift uut (
		.clk(clk), 
		.reset(reset), 
		.q(q)
	);

	initial begin
		clk = 0;
		reset = 0;
		forever #1 clk = !clk;
	end

	initial begin
		reset = 0;
		#3;
		reset = 1;
		#3;
		reset = 0;
	end
endmodule