data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v
1: b'%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:22: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:30: Define or directive not defined: \'`ALU_OP_WIDTH\'\n    input [`ALU_OP_WIDTH-1:0] op,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:31: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] rs,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`DATA_BUS] rs,\n                    ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:32: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] rt,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:33: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] rd\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:39: Define or directive not defined: \'`ALU_OP_NOP\'\n            `ALU_OP_NOP: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:42: Define or directive not defined: \'`ALU_OP_SLL\'\n            `ALU_OP_SLL: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:49: Define or directive not defined: \'`ALU_OP_SRL\'\n            `ALU_OP_SRL: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:56: Define or directive not defined: \'`ALU_OP_SRA\'\n            `ALU_OP_SRA: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:63: Define or directive not defined: \'`ALU_OP_ADD\'\n            `ALU_OP_ADD: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:70: Define or directive not defined: \'`ALU_OP_SUB\'\n            `ALU_OP_SUB: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:77: Define or directive not defined: \'`ALU_OP_AND\'\n            `ALU_OP_AND: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:84: Define or directive not defined: \'`ALU_OP_OR\'\n            `ALU_OP_OR: begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:91: Define or directive not defined: \'`ALU_OP_XOR\'\n            `ALU_OP_XOR: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:98: Define or directive not defined: \'`ALU_OP_NOR\'\n            `ALU_OP_NOR: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:105: Define or directive not defined: \'`ALU_OP_LU\'\n            `ALU_OP_LU: begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:112: Define or directive not defined: \'`ALU_OP_EQ\'\n            `ALU_OP_EQ: begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:119: Define or directive not defined: \'`ALU_OP_NE\'\n            `ALU_OP_NE: begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:126: Define or directive not defined: \'`ALU_OP_LT\'\n            `ALU_OP_LT: begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:133: Define or directive not defined: \'`ALU_OP_LTU\'\n            `ALU_OP_LTU: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/arithmetic_logic_unit.v:140: Define or directive not defined: \'`ALU_OP_LE\'\n            `ALU_OP_LE: begin\n            ^~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n'
module arithmetic_logic_unit #(
    parameter DATA_WIDTH = 32
)(
    input stall,
    
    input [`ALU_OP_WIDTH-1:0] op,
    input [`DATA_BUS] rs,
    input [`DATA_BUS] rt,
    output reg [`DATA_BUS] rd
    );
    
    always @*
    begin
        case(op)
            `ALU_OP_NOP: begin
                rd = 0;
            end
            `ALU_OP_SLL: begin
                rd = rs << rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d << %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_SRL: begin
                rd = rs >> rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d >> %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_SRA: begin
                rd = $signed(rs) >>> $signed(rt);
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d >>> %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_ADD: begin
                rd = rs + rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d + %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_SUB: begin
                rd = rs - rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d - %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_AND: begin
                rd = rs & rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d & %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_OR: begin
                rd = rs | rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d | %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_XOR: begin
                rd = rs ^ rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d ^ %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_NOR: begin
                rd = ~(rs | rt);
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d ~| %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_LU: begin
                rd = rt << 16;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d << 16 = %d", $unsigned(rt), $unsigned(rd));
`endif
            end
            `ALU_OP_EQ: begin
                rd = rs == rt ? 1 : 0;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d == %d = %d", $signed(rs), $signed(rt), rd);
`endif
            end
            `ALU_OP_NE: begin
                rd = $signed(rs) != $signed(rt) ? 1 : 0;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d != %d = %d", $signed(rs), $signed(rt), rd);
`endif
            end
            `ALU_OP_LT: begin
                rd = $signed(rs) < $signed(rt) ? 1 : 0;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d < %d = %d", $signed(rs), $signed(rt), rd);
`endif
            end
            `ALU_OP_LTU: begin
                rd = $unsigned(rs) < $unsigned(rt) ? 1 : 0;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d < %d = %d", $unsigned(rs), $unsigned(rt), rd);
`endif
            end
            `ALU_OP_LE: begin
                rd = $signed(rs) <= $signed(rt) ? 1 : 0;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d < %d = %d", $signed(rs), $signed(rt), rd);
`endif
            end
            default: begin
                rd = 0;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: unknown op %b", op);
`endif
            end
        endcase
    end
endmodule
module arithmetic_logic_unit #(
    parameter DATA_WIDTH = 32
)(
    input stall,
    
    input [`ALU_OP_WIDTH-1:0] op,
    input [`DATA_BUS] rs,
    input [`DATA_BUS] rt,
    output reg [`DATA_BUS] rd
    );

    
    always @*
    begin
        case(op)
            `ALU_OP_NOP: begin
                rd = 0;
            end
            `ALU_OP_SLL: begin
                rd = rs << rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d << %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_SRL: begin
                rd = rs >> rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d >> %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_SRA: begin
                rd = $signed(rs) >>> $signed(rt);
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d >>> %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_ADD: begin
                rd = rs + rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d + %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_SUB: begin
                rd = rs - rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d - %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_AND: begin
                rd = rs & rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d & %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_OR: begin
                rd = rs | rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d | %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_XOR: begin
                rd = rs ^ rt;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d ^ %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_NOR: begin
                rd = ~(rs | rt);
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d ~| %d = %d", $signed(rs), $signed(rt), $signed(rd));
`endif
            end
            `ALU_OP_LU: begin
                rd = rt << 16;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d << 16 = %d", $unsigned(rt), $unsigned(rd));
`endif
            end
            `ALU_OP_EQ: begin
                rd = rs == rt ? 1 : 0;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d == %d = %d", $signed(rs), $signed(rt), rd);
`endif
            end
            `ALU_OP_NE: begin
                rd = $signed(rs) != $signed(rt) ? 1 : 0;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d != %d = %d", $signed(rs), $signed(rt), rd);
`endif
            end
            `ALU_OP_LT: begin
                rd = $signed(rs) < $signed(rt) ? 1 : 0;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d < %d = %d", $signed(rs), $signed(rt), rd);
`endif
            end
            `ALU_OP_LTU: begin
                rd = $unsigned(rs) < $unsigned(rt) ? 1 : 0;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d < %d = %d", $unsigned(rs), $unsigned(rt), rd);
`endif
            end
            `ALU_OP_LE: begin
                rd = $signed(rs) <= $signed(rt) ? 1 : 0;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: %d < %d = %d", $signed(rs), $signed(rt), rd);
`endif
            end
            default: begin
                rd = 0;
`ifdef DEBUG_ALU
                if (!stall)
                    $display("ALU: unknown op %b", op);
`endif
            end
        endcase
    end
endmodule