data/full_repos/permissive/20289584/StopWatch.v
 line:11: before: "~"
1: b"%Error: data/full_repos/permissive/20289584/StopWatch.v:11: syntax error, unexpected '~', expecting TYPE-IDENTIFIER\n always @(posedge clk or posedge ~rst)\n                                 ^\n%Error: data/full_repos/permissive/20289584/StopWatch.v:27: syntax error, unexpected '=', expecting IDENTIFIER\n    second = second+1;\n           ^\n%Error: data/full_repos/permissive/20289584/StopWatch.v:33: syntax error, unexpected '=', expecting IDENTIFIER\n    sCLK  = 0;\n          ^\n%Error: data/full_repos/permissive/20289584/StopWatch.v:37: syntax error, unexpected '=', expecting IDENTIFIER\n    second  = 0;\n            ^\n%Error: data/full_repos/permissive/20289584/StopWatch.v:43: syntax error, unexpected '=', expecting IDENTIFIER\n    mCLK  = 0;\n          ^\n%Error: data/full_repos/permissive/20289584/StopWatch.v:47: syntax error, unexpected '=', expecting IDENTIFIER\n    hCLK  = 1;\n          ^\n%Error: data/full_repos/permissive/20289584/StopWatch.v:52: syntax error, unexpected '=', expecting IDENTIFIER\n    hCLK  = 0;\n          ^\n%Error: Cannot continue\n"
module StopWatch(rst,clk,minute,second,msecond,sCLK,mCLK,hCLK);

	input rst,clk;
	output [7:0] minute,second,msecond;
	output sCLK,mCLK,hCLK;

	wire rst,clk;
	reg [7:0] minute,second,msecond;
	reg sCLK,mCLK,hCLK;

	always @(posedge clk or posedge ~rst)
	begin
		if(rst==0)
		begin
			minute =0;
			second =0;
			msecond =0;
			sCLK = 0;
			mCLK = 0;
			hCLK = 0;
		end
		else
		begin
			msecond = msecond+1;
			if(msecond ==100)
			begin
				second = second+1;
				msecond  = 0;
				sCLK  = 1;
			end
			else
			begin
				sCLK  = 0;
			end
			if(second == 60)
			begin
				second  = 0;
				minute = minute +1;
				mCLK  = 1;
			end
			else
			begin
				mCLK  = 0;
			end
			if(minute == 60)
			begin
				hCLK  = 1;
				minute =0;
			end
			else
			begin
				hCLK  = 0;
			end
		end
	end		
endmodule
module StopWatch(rst,clk,minute,second,msecond,sCLK,mCLK,hCLK);


	input rst,clk;
	output [7:0] minute,second,msecond;
	output sCLK,mCLK,hCLK;

	wire rst,clk;
	reg [7:0] minute,second,msecond;
	reg sCLK,mCLK,hCLK;

	always @(posedge clk or posedge ~rst)
	begin
		if(rst==0)
		begin
			minute =0;
			second =0;
			msecond =0;
			sCLK = 0;
			mCLK = 0;
			hCLK = 0;
		end
		else
		begin
			msecond = msecond+1;
			if(msecond ==100)
			begin
				second = second+1;
				msecond  = 0;
				sCLK  = 1;
			end
			else
			begin
				sCLK  = 0;
			end
			if(second == 60)
			begin
				second  = 0;
				minute = minute +1;
				mCLK  = 1;
			end
			else
			begin
				mCLK  = 0;
			end
			if(minute == 60)
			begin
				hCLK  = 1;
				minute =0;
			end
			else
			begin
				hCLK  = 0;
			end
		end
	end		
endmodule