data/full_repos/permissive/124591763/led/16_wide_led/led16_drv.v
data/verilator_xmls/1eec437b-d416-4ea4-8d6d-8ca2a55c92b3.xml
module led16_drv (
    input  wire        clk,

    input  wire        en,
    input  wire        mod,

    output wire [15:0] led
);


    reg         s_in;


    wire        tck;


    reg  [ 3:0] cnt_s = 4'h0;


    reg  [ 7:0] led_l = 8'h0;
    reg  [ 7:0] led_r = 8'h0;


    wire [15:0] led_f;


    reg  [`CNT_WIDTH - 1:0] cnt_t = `CNT_WIDTH'h0;


    assign tck   = &cnt_t;


    assign led_f = (mod == 1'b1) ? {led_r, led_l} : {led_l, led_r};

    assign led   = (en == 1'b1) ? led_f : 16'h0;


    always @ (posedge clk) begin
        if (en == 1'b1) begin
            cnt_t <= cnt_t + `CNT_WIDTH'h1;
        end else begin
            cnt_t <= `CNT_WIDTH'h0;
        end
    end


    always @ (posedge clk) begin
        if (en == 1'b0) begin
            cnt_s <= 4'h0;
        end else begin
            if (tck == 1'b1) begin
                cnt_s <= cnt_s + 4'h1;
            end
        end
    end


    always @ (*) begin
        if (cnt_s[3:0] < 4'h3) begin
            s_in = 1'b1;
        end else begin
            s_in = 1'b0;
        end
    end


    always @ (posedge clk) begin
        if (en == 1'b0) begin
            led_l <= 8'h0;
            led_r <= 8'h0;
        end else begin
            if (tck == 1'b1) begin
                led_l <= {led_l[6:0], s_in};
                led_r <= {s_in, led_r[7:1]};
            end
        end
    end

endmodule
module led16_drv (
    input  wire        clk,

    input  wire        en,
    input  wire        mod,

    output wire [15:0] led
);



    reg         s_in;


    wire        tck;


    reg  [ 3:0] cnt_s = 4'h0;


    reg  [ 7:0] led_l = 8'h0;
    reg  [ 7:0] led_r = 8'h0;


    wire [15:0] led_f;


    reg  [`CNT_WIDTH - 1:0] cnt_t = `CNT_WIDTH'h0;


    assign tck   = &cnt_t;


    assign led_f = (mod == 1'b1) ? {led_r, led_l} : {led_l, led_r};

    assign led   = (en == 1'b1) ? led_f : 16'h0;


    always @ (posedge clk) begin
        if (en == 1'b1) begin
            cnt_t <= cnt_t + `CNT_WIDTH'h1;
        end else begin
            cnt_t <= `CNT_WIDTH'h0;
        end
    end


    always @ (posedge clk) begin
        if (en == 1'b0) begin
            cnt_s <= 4'h0;
        end else begin
            if (tck == 1'b1) begin
                cnt_s <= cnt_s + 4'h1;
            end
        end
    end


    always @ (*) begin
        if (cnt_s[3:0] < 4'h3) begin
            s_in = 1'b1;
        end else begin
            s_in = 1'b0;
        end
    end


    always @ (posedge clk) begin
        if (en == 1'b0) begin
            led_l <= 8'h0;
            led_r <= 8'h0;
        end else begin
            if (tck == 1'b1) begin
                led_l <= {led_l[6:0], s_in};
                led_r <= {s_in, led_r[7:1]};
            end
        end
    end

endmodule