data/full_repos/permissive/162696624/Traffic Light.v
 line:32: before: "["
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/162696624/Traffic\n        ... Looked in:\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.sv\n             data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624/Traffic.sv\n             obj_dir/data/full_repos/permissive/162696624/Traffic\n             obj_dir/data/full_repos/permissive/162696624/Traffic.v\n             obj_dir/data/full_repos/permissive/162696624/Traffic.sv\n%Error: Cannot find file containing module: Light.v\n%Error: Exiting due to 2 error(s)\n'
module Moore_main(A,B,CLK,finished,AL,BL,D,RST);
  
  input A,B,finished,RST,CLK;
  output reg AL,BL,D;
  
  reg  [1:0]state;
  parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
  
   always @ (posedge CLK or negedge RST)
      if (~RST) state = S0;
      
   
       else
         case (state)
            S0: if (finished & ~A & ~B) state = S1;
                    else if(B & ~A) state = S2;
            S1: if (finished & ~A & ~B) state = S2;  
                    else if(A)  state = S0;
            S2: if (finished & ~A & ~B) state = S3;
                    else if(A)  state = S0;
            S3: if ((finished & ~A & ~B)| A) state = S0;  
                    else if(B & ~A) state = S2;
         endcase
  
   always @ (state )
         case (state)
            S0: #1 {AL,BL,D}=101;
            S1: #1 {AL,BL,D}=001;
            S2: #1 {AL,BL,D}=010;
            S3: #1 {AL,BL,D}=000;
         endcase
endmodule
module Moore_main(A,B,CLK,finished,AL,BL,D,RST);

  
  input A,B,finished,RST,CLK;
  output reg AL,BL,D;
  
  reg  [1:0]state;
  parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
  
   always @ (posedge CLK or negedge RST)
      if (~RST) state = S0;
      
   
       else
         case (state)
            S0: if (finished & ~A & ~B) state = S1;
                    else if(B & ~A) state = S2;
            S1: if (finished & ~A & ~B) state = S2;  
                    else if(A)  state = S0;
            S2: if (finished & ~A & ~B) state = S3;
                    else if(A)  state = S0;
            S3: if ((finished & ~A & ~B)| A) state = S0;  
                    else if(B & ~A) state = S2;
         endcase
  
   always @ (state )
         case (state)
            S0: #1 {AL,BL,D}=101;
            S1: #1 {AL,BL,D}=001;
            S2: #1 {AL,BL,D}=010;
            S3: #1 {AL,BL,D}=000;
         endcase
endmodule