data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:84: Unsupported: Ignoring delay on this delayed statement.\n #14 Q <= D;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #14 Q <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #14 Q <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #14 Q <= D;\n  ^\n%Warning-MULTITOP: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:12: Multiple top level modules\n                                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                                           : ... Top module \'BUF\'\nmodule BUF(A, Y);\n       ^~~\n                                                                                                           : ... Top module \'NOT\'\nmodule NOT(A, Y);\n       ^~~\n                                                                                                           : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n       ^~~~\n                                                                                                           : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n       ^~~\n                                                                                                           : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n       ^~~\n                                                                                                           : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R);\n       ^~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:86: Can\'t find definition of scope/variable: \'tester_\'\n tester_.m1.PwrCntr[0] = tester_.m1.PwrCntr[0] + 1;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:86: Can\'t find definition of scope/variable: \'m1\'\n tester_.m1.PwrCntr[0] = tester_.m1.PwrCntr[0] + 1;\n                                 ^~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:86: Can\'t find definition of scope/variable: \'tester_\'\n tester_.m1.PwrCntr[0] = tester_.m1.PwrCntr[0] + 1;\n ^~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:86: Can\'t find definition of scope/variable: \'m1\'\n tester_.m1.PwrCntr[0] = tester_.m1.PwrCntr[0] + 1;\n         ^~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:37: Can\'t find definition of scope/variable: \'tester_\'\n tester_.m1.PwrCntr[0] = tester_.m1.PwrCntr[0] + 1;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:37: Can\'t find definition of scope/variable: \'m1\'\n tester_.m1.PwrCntr[0] = tester_.m1.PwrCntr[0] + 1;\n                                 ^~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:37: Can\'t find definition of scope/variable: \'tester_\'\n tester_.m1.PwrCntr[0] = tester_.m1.PwrCntr[0] + 1;\n ^~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:37: Can\'t find definition of scope/variable: \'m1\'\n tester_.m1.PwrCntr[0] = tester_.m1.PwrCntr[0] + 1;\n         ^~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:27: Can\'t find definition of scope/variable: \'tester_\'\n tester_.m1.PwrCntr[0] = tester_.m1.PwrCntr[0] + 1;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:27: Can\'t find definition of scope/variable: \'m1\'\n tester_.m1.PwrCntr[0] = tester_.m1.PwrCntr[0] + 1;\n                                 ^~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:27: Can\'t find definition of scope/variable: \'tester_\'\n tester_.m1.PwrCntr[0] = tester_.m1.PwrCntr[0] + 1;\n ^~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:27: Can\'t find definition of scope/variable: \'m1\'\n tester_.m1.PwrCntr[0] = tester_.m1.PwrCntr[0] + 1;\n         ^~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:17: Can\'t find definition of scope/variable: \'tester_\'\n tester_.m1.PwrCntr[0] =  tester_.m1.PwrCntr[0] + 1;\n                          ^~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:17: Can\'t find definition of scope/variable: \'m1\'\n tester_.m1.PwrCntr[0] =  tester_.m1.PwrCntr[0] + 1;\n                                  ^~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:17: Can\'t find definition of scope/variable: \'tester_\'\n tester_.m1.PwrCntr[0] =  tester_.m1.PwrCntr[0] + 1;\n ^~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-01/byte_joining/cmos_cells_delay_cont.v:17: Can\'t find definition of scope/variable: \'m1\'\n tester_.m1.PwrCntr[0] =  tester_.m1.PwrCntr[0] + 1;\n         ^~\n%Error: Exiting due to 16 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module NOT(A, Y);
input A;
output Y;
assign #(1:1:4,1:1:4) Y = ~A;
always @(posedge Y) begin
	tester_.m1.PwrCntr[0] =  tester_.m1.PwrCntr[0] + 1;

end
endmodule
module NOT(A, Y);

input A;
output Y;
assign #(1:1:4,1:1:4) Y = ~A;
always @(posedge Y) begin
	tester_.m1.PwrCntr[0] =  tester_.m1.PwrCntr[0] + 1;

end
endmodule