data/full_repos/permissive/201699429/src/tb_csi_rx.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/201699429/src/tb_csi_rx.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/201699429/src/tb_csi_rx.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #(10/2) MIPI_CLK_P <= ~MIPI_CLK_P;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/201699429/src/tb_csi_rx.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #100000;\n  ^\n%Error: data/full_repos/permissive/201699429/src/tb_csi_rx.v:30: Cannot find file containing module: \'csi_rx\'\ncsi_rx u_csi_rx(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201699429/src,data/full_repos/permissive/201699429/csi_rx\n             data/full_repos/permissive/201699429/src,data/full_repos/permissive/201699429/csi_rx.v\n             data/full_repos/permissive/201699429/src,data/full_repos/permissive/201699429/csi_rx.sv\n             csi_rx\n             csi_rx.v\n             csi_rx.sv\n             obj_dir/csi_rx\n             obj_dir/csi_rx.v\n             obj_dir/csi_rx.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_csi_rx;

reg RST;
reg MIPI_CLK_P;
wire MIPI_CLK_N;

wire [3:0] LED;

initial begin
  MIPI_CLK_P = 0;
  RST = 1;
  #100;
  RST = 0;
end

always begin
  #(10/2)	MIPI_CLK_P <= ~MIPI_CLK_P;
end

assign MIPI_CLK_N = ~MIPI_CLK_P;

initial begin
  #100000;

  $finish();
end

csi_rx u_csi_rx(
  .RST(RST),

  .MIPI_CLK_P(MIPI_CLK_P),
  .MIPI_CLK_N(MIPI_CLK_N),

  .LED(LED)

);

endmodule
module tb_csi_rx;


reg RST;
reg MIPI_CLK_P;
wire MIPI_CLK_N;

wire [3:0] LED;

initial begin
  MIPI_CLK_P = 0;
  RST = 1;
  #100;
  RST = 0;
end

always begin
  #(10/2)	MIPI_CLK_P <= ~MIPI_CLK_P;
end

assign MIPI_CLK_N = ~MIPI_CLK_P;

initial begin
  #100000;

  $finish();
end

csi_rx u_csi_rx(
  .RST(RST),

  .MIPI_CLK_P(MIPI_CLK_P),
  .MIPI_CLK_N(MIPI_CLK_N),

  .LED(LED)

);

endmodule