data/full_repos/permissive/117436613/testbench/mm_test.sv
 line:156 column:34: Illegal character "'"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/mm_test.sv:150: Unsupported: Ignoring delay on this delayed statement.\n always #20\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/mm_test.sv:161: Unsupported: Ignoring delay on this delayed statement.\n  #80 rst_controller_reset_out_reset <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/mm_test.sv:162: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/mm_test.sv:164: syntax error, unexpected \'@\'\n  @(posedge clocks_sys_clk_clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/mm_test.sv:173: syntax error, unexpected \'@\'\n   @(posedge clocks_sys_clk_clk);\n   ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mm_test();

	logic         clocks_sys_clk_clk;
	logic         video_character_buffer_with_dma_0_avalon_char_source_endofpacket;
	logic         video_character_buffer_with_dma_0_avalon_char_source_valid;
	logic         video_character_buffer_with_dma_0_avalon_char_source_startofpacket;
	logic  [29:0] video_character_buffer_with_dma_0_avalon_char_source_data;
	logic         video_character_buffer_with_dma_0_avalon_char_source_ready;
	logic         video_dual_clock_buffer_0_avalon_dc_buffer_source_endofpacket;
	logic         video_dual_clock_buffer_0_avalon_dc_buffer_source_valid;
	logic         video_dual_clock_buffer_0_avalon_dc_buffer_source_startofpacket;
	logic  [29:0] video_dual_clock_buffer_0_avalon_dc_buffer_source_data;
	logic         video_dual_clock_buffer_0_avalon_dc_buffer_source_ready;
	logic         video_pll_0_vga_clk_clk;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_waitrequest;
	logic  [31:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_writedata;
	logic  [19:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_address;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_chipselect;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_write;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_read;
	logic  [31:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_readdata;
	logic   [3:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_byteenable;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest;
	logic   [7:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata;
	logic  [12:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_address;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_write;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_read;
	logic   [7:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata;
	logic   [0:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable;
	logic  [31:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_writedata;
	logic   [0:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_address;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_write;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_read;
	logic  [31:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_readdata;
	logic   [3:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable;
	logic         mmix_qsys_0_master_waitrequest;
	logic  [63:0] mmix_qsys_0_master_writedata;
	logic  [27:0] mmix_qsys_0_master_address;
	logic         mmix_qsys_0_master_write;
	logic         mmix_qsys_0_master_read;
	logic  [63:0] mmix_qsys_0_master_readdata;
	logic         mmix_qsys_0_master_readdatavalid;
	logic   [7:0] mmix_qsys_0_master_byteenable;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_waitrequest;
	logic  [31:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_writedata;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_chipselect;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_write;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_read;
	logic  [31:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_readdata;
	logic   [3:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_byteenable;
	logic         mm_interconnect_0_sdram_s1_waitrequest;
	logic  [15:0] mm_interconnect_0_sdram_s1_writedata;
	logic  [21:0] mm_interconnect_0_sdram_s1_address;
	logic         mm_interconnect_0_sdram_s1_chipselect;
	logic         mm_interconnect_0_sdram_s1_write;
	logic         mm_interconnect_0_sdram_s1_read;
	logic  [15:0] mm_interconnect_0_sdram_s1_readdata;
	logic         mm_interconnect_0_sdram_s1_readdatavalid;
	logic   [1:0] mm_interconnect_0_sdram_s1_byteenable;
	logic  [31:0] mmix_qsys_0_d_irq_irq;
	logic         rst_controller_reset_out_reset;
	logic         rst_controller_001_reset_out_reset;
	logic         rst_controller_002_reset_out_reset;
	logic         video_pll_0_reset_source_reset;

	reg  [15:0] sdram_dq;
	wire  [15:0] sdram_wire_dq;
	assign sdram_wire_dq = sdram_dq;

	MMIX_system_sdram sdram (
		.clk            (clocks_sys_clk_clk),
		.reset_n        (~rst_controller_reset_out_reset),
		.az_addr        (mm_interconnect_0_sdram_s1_address),
		.az_be_n        (~mm_interconnect_0_sdram_s1_byteenable),
		.az_cs          (mm_interconnect_0_sdram_s1_chipselect),
		.az_data        (mm_interconnect_0_sdram_s1_writedata),
		.az_rd_n        (~mm_interconnect_0_sdram_s1_read),
		.az_wr_n        (~mm_interconnect_0_sdram_s1_write),
		.za_data        (mm_interconnect_0_sdram_s1_readdata),
		.za_valid       (mm_interconnect_0_sdram_s1_readdatavalid),
		.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest),
		.zs_addr        (sdram_wire_addr),
		.zs_ba          (sdram_wire_ba),
		.zs_cas_n       (sdram_wire_cas_n),
		.zs_cke         (sdram_wire_cke),
		.zs_cs_n        (sdram_wire_cs_n),
		.zs_dq          (sdram_wire_dq),
		.zs_dqm         (sdram_wire_dqm),
		.zs_ras_n       (sdram_wire_ras_n),
		.zs_we_n        (sdram_wire_we_n)
	);

	MMIX_system_mm_interconnect_0 mm_interconnect_0 (
		.clocks_sys_clk_clk                                                                (clocks_sys_clk_clk),
		.mmix_qsys_0_reset_n_reset_bridge_in_reset_reset                                   (rst_controller_reset_out_reset),
		.sdram_reset_reset_bridge_in_reset_reset                                           (rst_controller_reset_out_reset),
		.mmix_qsys_0_master_address                                                        (mmix_qsys_0_master_address),
		.mmix_qsys_0_master_waitrequest                                                    (mmix_qsys_0_master_waitrequest),
		.mmix_qsys_0_master_byteenable                                                     (mmix_qsys_0_master_byteenable),
		.mmix_qsys_0_master_read                                                           (mmix_qsys_0_master_read),
		.mmix_qsys_0_master_readdata                                                       (mmix_qsys_0_master_readdata),
		.mmix_qsys_0_master_readdatavalid                                                  (mmix_qsys_0_master_readdatavalid),
		.mmix_qsys_0_master_write                                                          (mmix_qsys_0_master_write),
		.mmix_qsys_0_master_writedata                                                      (mmix_qsys_0_master_writedata),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_address              (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_address),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_write                (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_write),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_read                 (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_read),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_readdata             (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_readdata),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_writedata            (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_writedata),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_byteenable           (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_byteenable),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_waitrequest          (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_waitrequest),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_chipselect           (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_chipselect),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_write       (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_write),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_read        (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_read),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_readdata    (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_readdata),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_writedata   (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_writedata),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_byteenable  (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_byteenable),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_waitrequest (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_waitrequest),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_chipselect  (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_chipselect),
		.sdram_s1_address                                                                  (mm_interconnect_0_sdram_s1_address),
		.sdram_s1_write                                                                    (mm_interconnect_0_sdram_s1_write),
		.sdram_s1_read                                                                     (mm_interconnect_0_sdram_s1_read),
		.sdram_s1_readdata                                                                 (mm_interconnect_0_sdram_s1_readdata),
		.sdram_s1_writedata                                                                (mm_interconnect_0_sdram_s1_writedata),
		.sdram_s1_byteenable                                                               (mm_interconnect_0_sdram_s1_byteenable),
		.sdram_s1_readdatavalid                                                            (mm_interconnect_0_sdram_s1_readdatavalid),
		.sdram_s1_waitrequest                                                              (mm_interconnect_0_sdram_s1_waitrequest),
		.sdram_s1_chipselect                                                               (mm_interconnect_0_sdram_s1_chipselect),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_address                (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_address),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_write                  (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_write),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_read                   (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_read),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata               (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata              (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable             (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest            (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect             (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_address               (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_address),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_write                 (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_write),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_read                  (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_read),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_readdata              (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_readdata),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_writedata             (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_writedata),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable            (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect            (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect)
	);
	
	always #20
		clocks_sys_clk_clk <= ~clocks_sys_clk_clk;
	
	initial begin
		clocks_sys_clk_clk <= 0;
		rst_controller_reset_out_reset <= 1;
		mmix_qsys_0_master_address <= 'Z;
		mmix_qsys_0_master_byteenable <= 'Z;
		mmix_qsys_0_master_read <= 0;
		mmix_qsys_0_master_write <= 0;
		mmix_qsys_0_master_writedata <= 'Z;
		#80 rst_controller_reset_out_reset <= 0;
		#200;

		@(posedge clocks_sys_clk_clk);
		
		mmix_qsys_0_master_address <= 'h0000cafe;
		mmix_qsys_0_master_byteenable <= 'b11111111;
		mmix_qsys_0_master_read <= 1;
		
		sdram_dq <= 'hbeef;
		
		while (mmix_qsys_0_master_waitrequest)
			@(posedge clocks_sys_clk_clk);
		mmix_qsys_0_master_read <= 0;

		
	end
	
endmodule
module mm_test();


	logic         clocks_sys_clk_clk;
	logic         video_character_buffer_with_dma_0_avalon_char_source_endofpacket;
	logic         video_character_buffer_with_dma_0_avalon_char_source_valid;
	logic         video_character_buffer_with_dma_0_avalon_char_source_startofpacket;
	logic  [29:0] video_character_buffer_with_dma_0_avalon_char_source_data;
	logic         video_character_buffer_with_dma_0_avalon_char_source_ready;
	logic         video_dual_clock_buffer_0_avalon_dc_buffer_source_endofpacket;
	logic         video_dual_clock_buffer_0_avalon_dc_buffer_source_valid;
	logic         video_dual_clock_buffer_0_avalon_dc_buffer_source_startofpacket;
	logic  [29:0] video_dual_clock_buffer_0_avalon_dc_buffer_source_data;
	logic         video_dual_clock_buffer_0_avalon_dc_buffer_source_ready;
	logic         video_pll_0_vga_clk_clk;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_waitrequest;
	logic  [31:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_writedata;
	logic  [19:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_address;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_chipselect;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_write;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_read;
	logic  [31:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_readdata;
	logic   [3:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_byteenable;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest;
	logic   [7:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata;
	logic  [12:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_address;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_write;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_read;
	logic   [7:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata;
	logic   [0:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable;
	logic  [31:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_writedata;
	logic   [0:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_address;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_write;
	logic         mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_read;
	logic  [31:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_readdata;
	logic   [3:0] mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable;
	logic         mmix_qsys_0_master_waitrequest;
	logic  [63:0] mmix_qsys_0_master_writedata;
	logic  [27:0] mmix_qsys_0_master_address;
	logic         mmix_qsys_0_master_write;
	logic         mmix_qsys_0_master_read;
	logic  [63:0] mmix_qsys_0_master_readdata;
	logic         mmix_qsys_0_master_readdatavalid;
	logic   [7:0] mmix_qsys_0_master_byteenable;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_waitrequest;
	logic  [31:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_writedata;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_chipselect;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_write;
	logic         mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_read;
	logic  [31:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_readdata;
	logic   [3:0] mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_byteenable;
	logic         mm_interconnect_0_sdram_s1_waitrequest;
	logic  [15:0] mm_interconnect_0_sdram_s1_writedata;
	logic  [21:0] mm_interconnect_0_sdram_s1_address;
	logic         mm_interconnect_0_sdram_s1_chipselect;
	logic         mm_interconnect_0_sdram_s1_write;
	logic         mm_interconnect_0_sdram_s1_read;
	logic  [15:0] mm_interconnect_0_sdram_s1_readdata;
	logic         mm_interconnect_0_sdram_s1_readdatavalid;
	logic   [1:0] mm_interconnect_0_sdram_s1_byteenable;
	logic  [31:0] mmix_qsys_0_d_irq_irq;
	logic         rst_controller_reset_out_reset;
	logic         rst_controller_001_reset_out_reset;
	logic         rst_controller_002_reset_out_reset;
	logic         video_pll_0_reset_source_reset;

	reg  [15:0] sdram_dq;
	wire  [15:0] sdram_wire_dq;
	assign sdram_wire_dq = sdram_dq;

	MMIX_system_sdram sdram (
		.clk            (clocks_sys_clk_clk),
		.reset_n        (~rst_controller_reset_out_reset),
		.az_addr        (mm_interconnect_0_sdram_s1_address),
		.az_be_n        (~mm_interconnect_0_sdram_s1_byteenable),
		.az_cs          (mm_interconnect_0_sdram_s1_chipselect),
		.az_data        (mm_interconnect_0_sdram_s1_writedata),
		.az_rd_n        (~mm_interconnect_0_sdram_s1_read),
		.az_wr_n        (~mm_interconnect_0_sdram_s1_write),
		.za_data        (mm_interconnect_0_sdram_s1_readdata),
		.za_valid       (mm_interconnect_0_sdram_s1_readdatavalid),
		.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest),
		.zs_addr        (sdram_wire_addr),
		.zs_ba          (sdram_wire_ba),
		.zs_cas_n       (sdram_wire_cas_n),
		.zs_cke         (sdram_wire_cke),
		.zs_cs_n        (sdram_wire_cs_n),
		.zs_dq          (sdram_wire_dq),
		.zs_dqm         (sdram_wire_dqm),
		.zs_ras_n       (sdram_wire_ras_n),
		.zs_we_n        (sdram_wire_we_n)
	);

	MMIX_system_mm_interconnect_0 mm_interconnect_0 (
		.clocks_sys_clk_clk                                                                (clocks_sys_clk_clk),
		.mmix_qsys_0_reset_n_reset_bridge_in_reset_reset                                   (rst_controller_reset_out_reset),
		.sdram_reset_reset_bridge_in_reset_reset                                           (rst_controller_reset_out_reset),
		.mmix_qsys_0_master_address                                                        (mmix_qsys_0_master_address),
		.mmix_qsys_0_master_waitrequest                                                    (mmix_qsys_0_master_waitrequest),
		.mmix_qsys_0_master_byteenable                                                     (mmix_qsys_0_master_byteenable),
		.mmix_qsys_0_master_read                                                           (mmix_qsys_0_master_read),
		.mmix_qsys_0_master_readdata                                                       (mmix_qsys_0_master_readdata),
		.mmix_qsys_0_master_readdatavalid                                                  (mmix_qsys_0_master_readdatavalid),
		.mmix_qsys_0_master_write                                                          (mmix_qsys_0_master_write),
		.mmix_qsys_0_master_writedata                                                      (mmix_qsys_0_master_writedata),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_address              (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_address),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_write                (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_write),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_read                 (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_read),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_readdata             (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_readdata),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_writedata            (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_writedata),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_byteenable           (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_byteenable),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_waitrequest          (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_waitrequest),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_data_chipselect           (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_data_chipselect),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_write       (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_write),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_read        (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_read),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_readdata    (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_readdata),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_writedata   (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_writedata),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_byteenable  (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_byteenable),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_waitrequest (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_waitrequest),
		.Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_0_flash_erase_control_chipselect  (mm_interconnect_0_altera_up_flash_memory_ip_core_avalon_interface_0_flash_erase_control_chipselect),
		.sdram_s1_address                                                                  (mm_interconnect_0_sdram_s1_address),
		.sdram_s1_write                                                                    (mm_interconnect_0_sdram_s1_write),
		.sdram_s1_read                                                                     (mm_interconnect_0_sdram_s1_read),
		.sdram_s1_readdata                                                                 (mm_interconnect_0_sdram_s1_readdata),
		.sdram_s1_writedata                                                                (mm_interconnect_0_sdram_s1_writedata),
		.sdram_s1_byteenable                                                               (mm_interconnect_0_sdram_s1_byteenable),
		.sdram_s1_readdatavalid                                                            (mm_interconnect_0_sdram_s1_readdatavalid),
		.sdram_s1_waitrequest                                                              (mm_interconnect_0_sdram_s1_waitrequest),
		.sdram_s1_chipselect                                                               (mm_interconnect_0_sdram_s1_chipselect),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_address                (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_address),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_write                  (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_write),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_read                   (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_read),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata               (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata              (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable             (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest            (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest),
		.video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect             (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_address               (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_address),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_write                 (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_write),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_read                  (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_read),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_readdata              (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_readdata),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_writedata             (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_writedata),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable            (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable),
		.video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect            (mm_interconnect_0_video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect)
	);
	
	always #20
		clocks_sys_clk_clk <= ~clocks_sys_clk_clk;
	
	initial begin
		clocks_sys_clk_clk <= 0;
		rst_controller_reset_out_reset <= 1;
		mmix_qsys_0_master_address <= 'Z;
		mmix_qsys_0_master_byteenable <= 'Z;
		mmix_qsys_0_master_read <= 0;
		mmix_qsys_0_master_write <= 0;
		mmix_qsys_0_master_writedata <= 'Z;
		#80 rst_controller_reset_out_reset <= 0;
		#200;

		@(posedge clocks_sys_clk_clk);
		
		mmix_qsys_0_master_address <= 'h0000cafe;
		mmix_qsys_0_master_byteenable <= 'b11111111;
		mmix_qsys_0_master_read <= 1;
		
		sdram_dq <= 'hbeef;
		
		while (mmix_qsys_0_master_waitrequest)
			@(posedge clocks_sys_clk_clk);
		mmix_qsys_0_master_read <= 0;

		
	end
	
endmodule