data/full_repos/permissive/143278/ivltests/pr2138979.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2138979.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (y !== 16\'hff_ff || y !== z) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2138979.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (y !== 16\'hff_ff || y !== z) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2138979.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (y !== 16\'h00_7f || y !== z) begin\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2138979.v:14: Operator OR expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                         : ... In instance main\n   assign y = $signed(a) | $signed(b);\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2138979.v:14: Operator OR expects 16 bits on the RHS, but RHS\'s SIGNED generates 8 bits.\n                                                                         : ... In instance main\n   assign y = $signed(a) | $signed(b);\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2138979.v:19: Operator OR expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                         : ... In instance main\n      z = $signed(a) | $signed(b);\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2138979.v:19: Operator OR expects 16 bits on the RHS, but RHS\'s SIGNED generates 8 bits.\n                                                                         : ... In instance main\n      z = $signed(a) | $signed(b);\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2138979.v:28: Operator OR expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                         : ... In instance main\n      z = $signed(a) | $signed(b);\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2138979.v:28: Operator OR expects 16 bits on the RHS, but RHS\'s SIGNED generates 8 bits.\n                                                                         : ... In instance main\n      z = $signed(a) | $signed(b);\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2138979.v:37: Operator OR expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                         : ... In instance main\n      z = $signed(a) | $signed(b);\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2138979.v:37: Operator OR expects 16 bits on the RHS, but RHS\'s SIGNED generates 8 bits.\n                                                                         : ... In instance main\n      z = $signed(a) | $signed(b);\n                     ^\n%Error: Exiting due to 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg   [7:0] a, b;
   wire [15:0] y;
   reg [15:0]  z;



   assign y = $signed(a) | $signed(b);

   initial begin
      a = 8'h55;
      b = 8'haa;
      z = $signed(a) | $signed(b);

      #1 if (y !== 16'hff_ff || y !== z) begin
	 $display("FAILED -- a=%h, b=%h, y=%h, z=%h", a, b, y, z);
	 $finish;
      end

      a = 8'haa;
      b = 8'h55;
      z = $signed(a) | $signed(b);

      #1 if (y !== 16'hff_ff || y !== z) begin
	 $display("FAILED -- a=%h, b=%h, y=%h, z=%h", a, b, y, z);
	 $finish;
      end

      a = 8'h7f;
      b = 8'h00;
      z = $signed(a) | $signed(b);

      #1 if (y !== 16'h00_7f || y !== z) begin
	 $display("FAILED -- a=%h, b=%h, y=%h, z=%h", a, b, y, z);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   reg   [7:0] a, b;
   wire [15:0] y;
   reg [15:0]  z;



   assign y = $signed(a) | $signed(b);

   initial begin
      a = 8'h55;
      b = 8'haa;
      z = $signed(a) | $signed(b);

      #1 if (y !== 16'hff_ff || y !== z) begin
	 $display("FAILED -- a=%h, b=%h, y=%h, z=%h", a, b, y, z);
	 $finish;
      end

      a = 8'haa;
      b = 8'h55;
      z = $signed(a) | $signed(b);

      #1 if (y !== 16'hff_ff || y !== z) begin
	 $display("FAILED -- a=%h, b=%h, y=%h, z=%h", a, b, y, z);
	 $finish;
      end

      a = 8'h7f;
      b = 8'h00;
      z = $signed(a) | $signed(b);

      #1 if (y !== 16'h00_7f || y !== z) begin
	 $display("FAILED -- a=%h, b=%h, y=%h, z=%h", a, b, y, z);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule