data/full_repos/permissive/129797190/rtl/cpu/clk_div.v
data/verilator_xmls/7a3e2358-1fae-4be3-8a8f-77d9ff040e10.xml
module clk_div #(
    parameter LOG_DIVISOR = 1
) (
    input clk_in,
    output wire clk_out
);
    reg [LOG_DIVISOR-1:0] q;

    always @(posedge clk_in)
        q <= q + 1;

    assign clk_out = q[LOG_DIVISOR-1];
endmodule
module clk_div #(
    parameter LOG_DIVISOR = 1
) (
    input clk_in,
    output wire clk_out
);

    reg [LOG_DIVISOR-1:0] q;

    always @(posedge clk_in)
        q <= q + 1;

    assign clk_out = q[LOG_DIVISOR-1];
endmodule