data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:44: Operator EQ expects 2 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\nwire __sig = m == 1\'b0 && routine == 1\'b0;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:44: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\nwire __sig = m == 1\'b0 && routine == 1\'b0;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:46: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\ninitial begin o = 8\'h00; w = 1\'b0; port_addr = 1\'b0; port_out = 1\'b0; port_bit = 1\'b0; port_clk = 1\'b0; port_read = 1\'b0; end\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:46: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\ninitial begin o = 8\'h00; w = 1\'b0; port_addr = 1\'b0; port_out = 1\'b0; port_bit = 1\'b0; port_clk = 1\'b0; port_read = 1\'b0; end\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:50: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\nreg [1:0]  m  = 1\'b0;            \n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:55: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\nreg [ 2:0] modrm_stage = 1\'b0;   \n                         ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:56: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\nreg [ 3:0] routine = 1\'b0;       \n                     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:57: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\nreg [ 2:0] micro = 1\'b0;         \n                   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:66: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\nreg [2:0]  SMod = 1\'b0;      \n                  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:67: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\nreg [4:0]  SCnt = 1\'b0;      \n                  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:68: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\nreg [2:0]  CSel = 1\'b0;      \n                  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:70: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\nreg [15:0] WReg = 1\'b0;      \n                  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:73: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\nreg [15:0] op1 = 1\'b0;       \n                 ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:74: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance cpu\nreg [15:0] op2 = 1\'b0;       \n                 ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:141: Operator OR expects 17 bits on the LHS, but LHS\'s VARREF \'op1\' generates 16 bits.\n                                                                                    : ... In instance cpu\n           3\'h1: Ar = op1 | op2;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:141: Operator OR expects 17 bits on the RHS, but RHS\'s VARREF \'op2\' generates 16 bits.\n                                                                                    : ... In instance cpu\n           3\'h1: Ar = op1 | op2;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:142: Operator ADD expects 17 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                    : ... In instance cpu\n           3\'h2: Ar = op1 + op2 + flags[0];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:143: Operator SUB expects 17 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                    : ... In instance cpu\n           3\'h3: Ar = op1 - op2 - flags[0];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:144: Operator AND expects 17 bits on the LHS, but LHS\'s VARREF \'op1\' generates 16 bits.\n                                                                                    : ... In instance cpu\n           3\'h4: Ar = op1 & op2;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:144: Operator AND expects 17 bits on the RHS, but RHS\'s VARREF \'op2\' generates 16 bits.\n                                                                                    : ... In instance cpu\n           3\'h4: Ar = op1 & op2;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:146: Operator XOR expects 17 bits on the LHS, but LHS\'s VARREF \'op1\' generates 16 bits.\n                                                                                    : ... In instance cpu\n           3\'h6: Ar = op1 ^ op2;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:146: Operator XOR expects 17 bits on the RHS, but RHS\'s VARREF \'op2\' generates 16 bits.\n                                                                                    : ... In instance cpu\n           3\'h6: Ar = op1 ^ op2;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:163: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s SEL generates 1 bits.\n                                                                                    : ... In instance cpu\n                  op1[3:0] + op2[3:0] + (CAlu == 3\'h2   ? flags[0] : 1\'b0) >= 5\'h10,\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:163: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                    : ... In instance cpu\n                  op1[3:0] + op2[3:0] + (CAlu == 3\'h2   ? flags[0] : 1\'b0) >= 5\'h10,\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:180: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s SEL generates 1 bits.\n                                                                                    : ... In instance cpu\n                  op1[3:0] < op2[3:0] + (CAlu == 3\'h3   ? flags[0] : 1\'b0),\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:180: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                    : ... In instance cpu\n                  op1[3:0] < op2[3:0] + (CAlu == 3\'h3   ? flags[0] : 1\'b0),\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:228: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s REPLICATE generates 8 bits.\n                                                                                    : ... In instance cpu\n          3\'h0: Sr = CBit ? {op1[14:0], op1[15]}   : {op1[6:0], op1[7]};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:229: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s REPLICATE generates 8 bits.\n                                                                                    : ... In instance cpu\n          3\'h1: Sr = CBit ? {op1[0],    op1[15:1]} : {op1[0],   op1[7:1]};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:230: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s REPLICATE generates 8 bits.\n                                                                                    : ... In instance cpu\n          3\'h2: Sr = CBit ? {op1[14:0], flags[0]}  : {op1[6:0], flags[0]};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:231: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s REPLICATE generates 8 bits.\n                                                                                    : ... In instance cpu\n          3\'h3: Sr = CBit ? {flags[0],  op1[15:1]} : {flags[0], op1[7:1]};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:233: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s REPLICATE generates 8 bits.\n                                                                                    : ... In instance cpu\n                        Sr = CBit ? {op1[14:0], 1\'b0}      : {op1[6:0], 1\'b0};\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:234: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s REPLICATE generates 8 bits.\n                                                                                    : ... In instance cpu\n          3\'h5: Sr = CBit ? {1\'b0,      op1[15:1]} : {1\'b0,     op1[7:1]};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:235: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s REPLICATE generates 8 bits.\n                                                                                    : ... In instance cpu\n          3\'h7: Sr = CBit ? {op1[15],   op1[15:1]} : {op1[7],   op1[7:1]};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:261: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                    : ... In instance cpu\n        routine <= 1\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:262: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                    : ... In instance cpu\n        {sw, m} <= 2\'b00;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:288: Operator ADD expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                    : ... In instance cpu\n        6:  begin routine <= 7;   WReg <= sp + 2\'h2; ea <= sp;        WR <= 1\'b1; {CReg, sw, CBit} <= {3\'h4, 2\'b11}; end\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:299: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                    : ... In instance cpu\n                micro       <= 1\'b0;  \n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:300: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                    : ... In instance cpu\n                modrm_stage <= 1\'b0;  \n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:373: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                    : ... In instance cpu\n                        CSel <= i[4:1];\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:399: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                    : ... In instance cpu\n                        op2   <= 1\'b1;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:425: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'flags\' generates 12 bits.\n                                                                                    : ... In instance cpu\n                        WReg <= flags;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:484: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                    : ... In instance cpu\n                    8\'b1001_1110: flags <= ax[15:8];\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:488: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'flags\' generates 12 bits.\n                                                                                    : ... In instance cpu\n                        WReg <= flags;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:541: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                    op1 <= DBit ? DReg : i;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:542: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                    op2 <= DBit ? i : DReg;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:600: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                    op1 <= DBit ? op1 : i;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:601: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                    op2 <= DBit ? i : op2;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:635: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'Ar\' generates 17 bits.\n                                                                                    : ... In instance cpu\n                        WReg <= Ar;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:666: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                        op2   <= i;          \n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:676: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'Ar\' generates 17 bits.\n                                                                                    : ... In instance cpu\n                        WReg  <= Ar;                 \n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:677: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                    : ... In instance cpu\n                        ip    <= ip + opcode[0];     \n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:688: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'Ar\' generates 17 bits.\n                                                                                    : ... In instance cpu\n                        WReg  <= Ar;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:703: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                    3\'h1: begin op2 <= i; micro <= 3\'h2; ip <= ip + 1\'b1; CBitT <= opcode[0]; end\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:726: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'Ar\' generates 17 bits.\n                                                                                    : ... In instance cpu\n                            WReg  <= Ar;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:763: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                    3\'h0: begin WReg <= i; WR <= 1\'b1; micro <= 3\'h1; ip <= ip + 1\'b1; if (~CBit) m <= 0; end\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:783: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                            WReg <= opcode[0] ? {i, WReg[7:0]} : i;   \n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:792: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                        end else begin WReg <= i; CBit <= 1\'b0; end\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:810: Operator ADD expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                    : ... In instance cpu\n                        WReg     <= sp + 2\'h2;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:832: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                    3\'h2: begin WReg <= sp + i; ip <= ip + 1\'b1; micro <= 3\'h3; WR <= 1\'b1; end\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:845: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                        if (~opcode[1])   begin op1 <= ip + i; ip <= ip + 1\'b1; end\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:852: Operator ADD expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                    : ... In instance cpu\n                    3\'h1: begin ip <= {op1[15:8] + i, op1[7:0]} + 2\'h2; m <= 0; end\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:863: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                        op1     <= ip + i;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:865: Operator SUB expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                    : ... In instance cpu\n                        WReg    <= sp - 2\'h2;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:866: Operator SUB expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                    : ... In instance cpu\n                        ea      <= sp - 2\'h2;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:877: Operator ADD expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                    : ... In instance cpu\n                        ip   <= {op1[15:8] + i, op1[7:0]} + 2\'h2;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:892: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'cx\' generates 16 bits.\n                                                                                    : ... In instance cpu\n                        ip <= cx ? ip + 1\'b1 : ({{8{i[7]}}, i[7:0]} + ip + 1\'b1);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:902: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                    : ... In instance cpu\n                        if (cx == 1\'b1 || (!opcode[1] && (opcode[0] ^ flags[6]))) begin\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:919: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'Ar\' generates 17 bits.\n                                                                                    : ... In instance cpu\n                    3\'h1: begin WR <= 1\'b1; WReg <= Ar; flags <= Af; m <= 0; end  \n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:935: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                    : ... In instance cpu\n                    3\'h0: begin routine <= 6; micro <= 1\'b1; end\n                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:943: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                    : ... In instance cpu\n                    3\'h0: begin CReg <= 1\'b0; WR <= 1\'b1; WReg <= DReg; micro <= 1\'b1; end  \n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:943: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                    : ... In instance cpu\n                    3\'h0: begin CReg <= 1\'b0; WR <= 1\'b1; WReg <= DReg; micro <= 1\'b1; end  \n                                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:952: Operator ADD expects 16 bits on the RHS, but RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                                    : ... In instance cpu\n                    ip <= ip + ((condition ^ opcode[0]) ? {{8{i[7]}}, i[7:0]} + 2\'h1 : 1\'h1);\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:952: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                    : ... In instance cpu\n                    ip <= ip + ((condition ^ opcode[0]) ? {{8{i[7]}}, i[7:0]} + 2\'h1 : 1\'h1);\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:960: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'WReg\' generates 16 bits.\n                                                                                    : ... In instance cpu\n                    flags <= WReg;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:971: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 8 bits.\n                                                                                    : ... In instance cpu\n                        if (~opcode[3]) begin port_addr <= i; ip <= ip + 1\'b1; end\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:975: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                    : ... In instance cpu\n                        micro     <= 1\'b1;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:981: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                    : ... In instance cpu\n                    3\'h1: begin port_read <= 1\'b0; port_clk <= opcode[1]; micro <= opcode[1] ? 2\'h2 : 3\'h3; end\n                                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:984: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance cpu\n                    3\'h2: begin port_clk <= 1\'b0; CReg <= 4\'h0; WReg <= port_in; WR <= ~opcode[1]; m <= 0; end\n                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:1001: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                     : ... In instance cpu\n                            2\'b0x: SCnt <= 1\'b1;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:1002: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                     : ... In instance cpu\n                            2\'b10: begin SCnt <= cx[3:0]; if (cx[3:0] == 1\'b0) m <= 0; end\n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:1002: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                     : ... In instance cpu\n                            2\'b10: begin SCnt <= cx[3:0]; if (cx[3:0] == 1\'b0) m <= 0; end\n                                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:1003: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                     : ... In instance cpu\n                            2\'b11: begin SCnt <= cx[4:0]; if (cx[4:0] == 1\'b0) m <= 0; end\n                                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:1012: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'SCnt\' generates 5 bits.\n                                                                                     : ... In instance cpu\n                        if (SCnt) begin\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:1077: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 8 bits.\n                                                                                     : ... In instance cpu\n                    WReg <= i;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:1090: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s LTE generates 1 bits.\n                                                                                     : ... In instance cpu\n                    3\'h2: if (opcode[1]) begin WReg <= DReg; routine <= routine <= 1; end\n                                                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:1092: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 8 bits.\n                                                                                     : ... In instance cpu\n                          else begin micro <= 3\'h3; WReg <= i; WR <= 1\'b1; ea <= ea + 1\'b1; sw <= opcode[0];\n                                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:1112: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 8 bits.\n                                                                                     : ... In instance cpu\n                    3\'h0: begin micro <= 3\'h1; op1 <= DReg; op2 <= i; CBitT <= CBit; ip <= ip + 1\'b1; end\n                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/07_reduced86/cpu.v:1127: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 8 bits.\n                                                                                     : ... In instance cpu\n                            3\'h1: begin micro <= 3\'h2; op2 <= i; ip <= ip + 1\'b1; CBitT <= CBit; end\n                                                           ^~\n%Error: Exiting due to 88 warning(s)\n'
module cpu(

    input   wire        reset,


    input   wire        clk,
    input   wire        clk25,
    input   wire [7:0]  i,
    output  reg  [7:0]  o,
    output  wire [15:0] a,
    output  reg         w,


    output  reg  [15:0] port_addr,
    input   wire [15:0] port_in,
    output  reg  [15:0] port_out,
    output  reg         port_bit,
    output  reg         port_clk,
    output  reg         port_read

);

`define INIT         0
`define MODRM        1
`define EXEC         2


`define SUB_NORMAL      0

`define SUB_WRITE_MEM   1
`define SUB_WRITE_MEM2  2

`define SUB_PUSH        3
`define SUB_PUSH2       4
`define SUB_PUSH3       5

`define SUB_POP         6
`define SUB_POP2        7
`define SUB_POP3        8


assign a = sw ? ea : ip;

wire __sig = m == 1'b0 && routine == 1'b0;

initial begin o = 8'h00; w = 1'b0; port_addr = 1'b0; port_out = 1'b0; port_bit = 1'b0; port_clk = 1'b0; port_read = 1'b0; end



reg [1:0]  m  = 1'b0;
reg        sw = 1'b0;
reg [15:0] ea = 16'h0000;
reg [ 7:0] opcode = 8'h00;
reg [ 7:0] modrm  = 8'h00;
reg [ 2:0] modrm_stage = 1'b0;
reg [ 3:0] routine = 1'b0;
reg [ 2:0] micro = 1'b0;



reg [2:0]  CReg = 3'b000;
reg [2:0]  CAlu = 3'b000;
reg        CBit  = 1'b0;
reg        CBitT = 1'b0;
reg        DBit = 1'b0;
reg [2:0]  SMod = 1'b0;
reg [4:0]  SCnt = 1'b0;
reg [2:0]  CSel = 1'b0;
reg [15:0] DReg;
reg [15:0] WReg = 1'b0;
reg        WR   = 1'b0;

reg [15:0] op1 = 1'b0;
reg [15:0] op2 = 1'b0;


reg [15:0] ax    = 16'h2F3F;
reg [15:0] cx    = 16'h0002;
reg [15:0] dx    = 16'h64EA;
reg [15:0] bx    = 16'hB002;
reg [15:0] sp    = 16'hC000;
reg [15:0] bp    = 16'h0000;
reg [15:0] si    = 16'h1234;
reg [15:0] di    = 16'h0000;

reg [11:0] flags = 12'b0000_0000_0000;
reg [15:0] ip    = 16'hFFF0;


always @* begin
    case (CReg)
        3'h0: DReg = CBit ? ax : {8'h00, ax[7:0]};
        3'h1: DReg = CBit ? cx : {8'h00, cx[7:0]};
        3'h2: DReg = CBit ? dx : {8'h00, dx[7:0]};
        3'h3: DReg = CBit ? bx : {8'h00, bx[7:0]};
        3'h4: DReg = CBit ? sp : {8'h00, ax[15:8]};
        3'h5: DReg = CBit ? bp : {8'h00, cx[15:8]};
        3'h6: DReg = CBit ? si : {8'h00, dx[15:8]};
        3'h7: DReg = CBit ? di : {8'h00, bx[15:8]};
    endcase
end


always @(negedge clk25) if (WR)
case (CReg)
    3'h0: if (CBit) ax <= WReg; else ax[7:0] <= WReg[7:0];
    3'h1: if (CBit) cx <= WReg; else cx[7:0] <= WReg[7:0];
    3'h2: if (CBit) dx <= WReg; else dx[7:0] <= WReg[7:0];
    3'h3: if (CBit) bx <= WReg; else bx[7:0] <= WReg[7:0];
    3'h4: if (CBit) sp <= WReg; else ax[15:8] <= WReg[7:0];
    3'h5: if (CBit) bp <= WReg; else cx[15:8] <= WReg[7:0];
    3'h6: if (CBit) si <= WReg; else dx[15:8] <= WReg[7:0];
    3'h7: if (CBit) di <= WReg; else bx[15:8] <= WReg[7:0];
endcase





reg [16:0] Ar;
reg [11:0] Af;


wire Zero8  = ~|Ar[7:0];
wire Zero16 = ~|Ar[15:8] && Zero8;
wire Sign8  =   Ar[7];
wire Sign16 =   Ar[15];
wire Parity = ~^Ar[7:0];


wire ADD_Overflow8  = (op1[7]  ^ op2[7]  ^ 1'b1) & (op2[7]  ^ Ar[7]);
wire ADD_Overflow16 = (op1[15] ^ op2[15] ^ 1'b1) & (op2[15] ^ Ar[15]);
wire SUB_Overflow8  = (op1[7]  ^ op2[7]        ) & (op2[7]  ^ Ar[7]);
wire SUB_Overflow16 = (op1[15] ^ op2[15]       ) & (op2[15] ^ Ar[15]);

always @* begin

    case (CAlu)

3'h0: Ar = op1 + op2;
3'h1: Ar = op1 | op2;
3'h2: Ar = op1 + op2 + flags[0];
3'h3: Ar = op1 - op2 - flags[0];
3'h4: Ar = op1 & op2;
3'h5: Ar = op1 - op2;
3'h6: Ar = op1 ^ op2;
3'h7: Ar = op1 - op2;

    endcase

    case (CAlu)


        3'h0, 3'h2:
            Af = {
CBit ? ADD_Overflow16 : ADD_Overflow8,
flags[10],
flags[9],
flags[8],
CBit ? Sign16 : Sign8,
CBit ? Zero16 : Zero8,
1'b0,
op1[3:0] + op2[3:0] + (CAlu == 3'h2? flags[0] : 1'b0) >= 5'h10,
1'b0,
Parity,
1'b1,
CBit ? Ar[16] : Ar[8]
            };


        3'h3, 3'h5, 3'h7:
            Af = {
CBit ? SUB_Overflow16 : SUB_Overflow8,
flags[10],
flags[9],
flags[8],
CBit ? Sign16 : Sign8,
CBit ? Zero16 : Zero8,
1'b0,
op1[3:0] < op2[3:0] + (CAlu == 3'h3? flags[0] : 1'b0),
1'b0,
Parity,
1'b1,
CBit ? Ar[16] : Ar[8]
            };


        default:
            Af = {
1'b0,
flags[10],
flags[9],
flags[8],
CBit ? Sign16 : Sign8,
CBit ? Zero16 : Zero8,
1'b0,
Ar[4],
1'b0,
Parity,
1'b1,
1'b0
            };

    endcase

end


wire condition =
    CSel == 3'b000 ? flags[11] :
    CSel == 3'b001 ? flags[0] :
    CSel == 3'b010 ? flags[6] :
    CSel == 3'b011 ? (flags[0] | flags[6]) :
    CSel == 3'b100 ? flags[7] :
    CSel == 3'b101 ? flags[2] :
    CSel == 3'b110 ? (flags[7] ^ flags[11]) :
                     (flags[7] ^ flags[11]) | (flags[6]);


reg [15:0] Sr;
reg        Sc;


always @* begin

    case (SMod)

3'h0: Sr = CBit ? {op1[14:0], op1[15]}   : {op1[6:0], op1[7]};
3'h1: Sr = CBit ? {op1[0],    op1[15:1]} : {op1[0],   op1[7:1]};
3'h2: Sr = CBit ? {op1[14:0], flags[0]}  : {op1[6:0], flags[0]};
3'h3: Sr = CBit ? {flags[0],  op1[15:1]} : {flags[0], op1[7:1]};
3'h4, 3'h6:
                        Sr = CBit ? {op1[14:0], 1'b0}      : {op1[6:0], 1'b0};
3'h5: Sr = CBit ? {1'b0,      op1[15:1]} : {1'b0,     op1[7:1]};
3'h7: Sr = CBit ? {op1[15],   op1[15:1]} : {op1[7],   op1[7:1]};

    endcase

    case (SMod)


        3'h0, 3'h2, 3'h4, 3'h6: Sc = CBit ? op1[15] : op1[7];


        3'h1, 3'h3, 3'h5, 3'h7: Sc = op1[0];

    endcase

end





always @(posedge clk25) begin


    if (reset) begin

        ip <= 16'hFFF0;
        routine <= 1'b0;
        {sw, m} <= 2'b00;

    end
    

    else case (routine)


        `SUB_WRITE_MEM:  begin o <= WReg[7:0]; w <= 1'b1; routine <= `SUB_WRITE_MEM2; end
        `SUB_WRITE_MEM2: begin

            routine <= CBit? `SUB_WRITE_MEM2 : `SUB_NORMAL;
            o    <= WReg[15:8];
            ea   <= ea + 1'b1;
            w    <= CBit;
            sw   <= CBit;
            CBit <= 1'b0;

        end


        `SUB_PUSH:  begin routine <= `SUB_PUSH2;  o  <= WReg[7:0];    CBit <= 1'b1; ea <= sp - 2;    sw   <= 1'b1;   w <= 1'b1; end
        `SUB_PUSH2: begin routine <= `SUB_PUSH3;  o  <= WReg[15:8];   WR   <= 1'b1; ea <= ea + 1'b1; WReg <= sp - 2; CReg <= 3'h4; end
        `SUB_PUSH3: begin routine <= `SUB_NORMAL; {w, sw} <= {2'b00}; WR   <= 1'b0; end


        `SUB_POP:  begin routine <= `SUB_POP2;   WReg <= sp + 2'h2; ea <= sp;        WR <= 1'b1; {CReg, sw, CBit} <= {3'h4, 2'b11}; end
        `SUB_POP2: begin routine <= `SUB_POP3;   WReg[7:0]  <= i;   ea <= ea + 1'b1; WR <= 1'b0; end
        `SUB_POP3: begin routine <= `SUB_NORMAL; WReg[15:8] <= i;   sw <= 1'b0; end


        default: case (m)


            `INIT: begin

                opcode      <= i;
                micro       <= 1'b0;
                modrm_stage <= 1'b0;
                WR          <= 1'b0;
                ip     <= ip + 1'b1;

                casex (i)


                    8'b00_xxx_0xx: begin

                        CAlu <= i[5:3];
                        {DBit, CBit} <= i[1:0];
                        m    <= `MODRM;

                    end


                    8'b00_xxx_10x: begin

                        CReg <= 3'h0;
                        CAlu <= i[5:3];
                        {DBit, CBit} <= i[1:0];
                        m    <= `EXEC;

                    end
                    

                    8'b1000_0xxx,
                    8'b1111_011x: begin


                        {DBit, CBit} <= {1'b0, i[0]};
                        CAlu <= 3'h4;
                        m <= `MODRM;

                    end


                    8'b1000_10xx: begin

                        {DBit, CBit} <= i[1:0];
                        m <= `MODRM;

                    end


                    8'b1011_xxxx: begin


                        {CBit, CReg} <= i[3:0];
                        m <= `EXEC;

                    end


                    8'b1100_011x: begin

                        {DBit, CBit} <= {1'b0, i[0]};
                        m <= `MODRM;

                    end


                    8'b1100_001x: begin

                        ea <= sp;
                        sw <= 1'b1;
                        m  <= `EXEC;

                    end


                    8'b0111_xxxx: begin

                        CSel <= i[4:1];
                        m <= `EXEC;

                    end


                    8'b1111_0101: flags[0] <= ~flags[0];
                    8'b1111_100x: flags[0] <= i[0];
                    8'b1111_101x: flags[9] <= i[0];
                    8'b1111_110x: flags[10] <= i[0];
                    8'b1001_0000: beginend


                    8'b1001_100x: begin

                        WReg <= i[0] ? {16{ax[15]}} : {{8{ax[7]}}, ax[7:0]};
                        CBit <= 1'b1;
                        CReg <= i[0] ? 3'h2 : 3'h0;
                        m <= `EXEC;

                    end


                    8'b0100_xxxx: begin

                        {CReg, CBit} <= {i[2:0], 1'b1};
                        op2   <= 1'b1;
                        CAlu  <= i[3] ?3'h5 :3'h0;
                        m     <= `EXEC;

                    end


                    8'b0101_xxxx: begin

                        {CBit, CReg} <= {1'b1, i[2:0]};
                        m <= `EXEC;

                    end


                    8'b1001_0xxx: begin

                        {CBit, CReg} <= {1'b1, i[2:0]};
                        op1 <= ax;
                        m   <= `EXEC;

                    end


                    8'b1001_1100: begin

                        WReg <= flags;
                        routine <= `SUB_PUSH;

                    end


                    8'b1001_1101: begin

                        routine <= `SUB_POP;
                        m <= `EXEC;

                    end


                    8'b1110_x1xx: begin

                        CBit      <= i[0];
                        port_bit  <= i[0];
                        port_addr <= dx;
                        m <= `EXEC;

                    end


                    8'b1101_00xx: begin

                        {DBit, CBit} <= {1'b0, i[0]};
                        m <= `MODRM;

                    end


                    8'b1010_00xx: begin
                    
                        {CReg, CBit} <= {3'b000, i[0]};
                        m <= `EXEC;
                    
                    end


                    8'b1101_0111: begin
                    
                        ea <= bx + {8'h00, ax[7:0]};
                        {CReg, CBit} <= {3'h0, 1'b0};
                        sw <= 1'b1;                                        
                        m  <= `EXEC;                        
                    
                    end


                    8'b1010_100x: begin
                    
                        {CReg, CBit} <= {3'b000, i[0]};
                        CAlu <= 3'h4;
                        m <= `EXEC;
                    
                    end


                    8'b1001_1110: flags <= ax[15:8];
                    8'b1001_1111: begin 
                        
                        {CBit, CReg} <= {1'h0, 3'h4};
                        WReg <= flags;
                        WR <= 1'b1;
                        
                    end


                    default: m <= `EXEC;

                endcase

            end


            `MODRM: case (modrm_stage)


                3'h0: begin


                    modrm <= i;


                    case (i[2:0])
                        3'h0: ea <= bx + si;
                        3'h1: ea <= bx + di;
                        3'h2: ea <= bp + si;
                        3'h3: ea <= bp + di;
                        3'h4: ea <= si;
                        3'h5: ea <= di;
                        3'h6: ea <= (i[7:6] == 2'b00) ? 16'h0000 : bp;
                        3'h7: ea <= bx;
                    endcase




                    CReg <= i[5:3];


                    sw <= (i[7:6] == 2'b00) && (i[2:0] != 3'h6);


                    ip <= ip + 1'b1;


                    modrm_stage <= 3'h1;

                end


                3'h1: begin


                    op1 <= DBit ? DReg : i;
                    op2 <= DBit ? i : DReg;


                    CReg <= modrm[2:0];


                    case (modrm[7:6])


                        2'b00: begin


                            if (modrm[2:0] == 3'h6) begin ip <= ip + 1'b1; ea[7:0] <= i; modrm_stage <= 3'h3; end


                            else if (CBit) begin ea <= ea + 1'b1; modrm_stage <= 3'h5; end


                            else begin m <= `EXEC; end

                        end


                        2'b01: begin modrm_stage <= 3'h4; ip <= ip + 1'b1; ea <= ea + {{8{i[7]}}, i[7:0]}; sw <= 1'b1; end


                        2'b10: begin modrm_stage <= 3'h3; ip <= ip + 1'b1; ea <= ea + {8'h00, i[7:0]}; end


                        2'b11: begin modrm_stage <= 3'h2; end

                    endcase

                end


                3'h2: begin

                    op1 <= DBit ? op1 : DReg;
                    op2 <= DBit ? DReg : op2;
                    m <= `EXEC;

                end


                3'h3: begin

                   ea[15:8] <= ea[15:8] + i;
                   ip <= ip + 1'b1;
                   sw <= 1'b1;
                   modrm_stage <= 3'h4;

                end


                3'h4: begin


                    op1 <= DBit ? op1 : i;
                    op2 <= DBit ? i : op2;


                    if (CBit) begin modrm_stage <= 3'h5; ea <= ea + 1'b1; end


                    else m <= `EXEC;

                end


                3'h5: begin

                    op1[15:8] <= DBit ? op1[15:8] : i;
                    op2[15:8] <= DBit ? i : op2[15:8];


                    ea <= ea - 1'b1;
                    m <= `EXEC;

                end

            endcase


            `EXEC: casex (opcode)


                8'b00_xxx_0xx: begin


                    if (CAlu < 3'h7) begin


                        WReg <= Ar;



                        if (modrm[7:6] == 2'b11 || DBit) begin

                            CReg <= DBit ? modrm[5:3] : modrm[2:0];
                            WR   <= 1'b1;
                            sw   <= 1'b0;

                        end


                        else routine <= `SUB_WRITE_MEM;

                    end

                    flags <= Af;
                    m     <= `INIT;

                end


                8'b00_xxx_10x: case (micro)


                    3'h0: begin

                        micro <= 3'h1;
                        op1   <= DReg;
                        op2   <= i;
                        ip    <= ip + 1'b1;

                    end


                    3'h1: begin

                        micro <= 3'h2;
                        WR    <= CAlu != 3'h7;
                        WReg  <= Ar;
                        ip    <= ip + opcode[0];
                        flags <= Af;

                        if (~CBit) m <= `INIT;
                        op2[15:8] <= i;

                    end


                    3'h2: begin

                        WReg  <= Ar;
                        flags <= Af;
                        m     <= `INIT;

                    end

                endcase


                8'b1000_00xx: case (micro)


                    3'h0: begin sw <= 1'b0; micro <= 3'h1; CAlu <= modrm[5:3]; end


                    3'h1: begin op2 <= i; micro <= 3'h2; ip <= ip + 1'b1; CBitT <= opcode[0]; end


                    3'h2: begin


                        if (CBitT) begin


                            op2[15:8] <= opcode[1] ? {8{op2[7]}} : i;


                            if (opcode[1] == 1'b0)
                                ip <= ip + 1'b1;


                            CBitT     <= 1'b0;

                        end


                        else begin

                            WReg  <= Ar;
                            flags <= Af;
                            m     <= `INIT;


                            if (modrm[7:6] == 2'b11) begin WR <= (CAlu != 3'h7); end


                            else begin sw <= 1'b1; routine <= `SUB_WRITE_MEM; end

                        end

                    end

                endcase


                8'b1000_10xx: begin

                    WReg <= op2;
                    m    <= `INIT;

                    if (modrm[7:6] == 2'b11 || DBit) begin

                        CReg <= DBit ? modrm[5:3] : modrm[2:0];
                        WR   <= 1'b1;
                        sw   <= 1'b0;

                    end
                    else routine <= `SUB_WRITE_MEM;

                end


                8'b1011_xxxx: case (micro)


                    3'h0: begin WReg <= i; WR <= 1'b1; micro <= 3'h1; ip <= ip + 1'b1; if (~CBit) m <= `INIT; end


                    3'h1: begin WReg[15:8] <= i; m <= `INIT; ip <= ip + 1'b1; end

                endcase


                8'b1100_011x: case (micro)


                    3'h0: begin sw <= 1'b0; CReg <= modrm[2:0]; micro <= 3'h1; end


                    3'h1: begin


                        if (~CBit) begin

                            CBit <= opcode[0];
                            WReg <= opcode[0] ? {i, WReg[7:0]} : i;

                            if (modrm[7:6] == 2'b11)
                                 begin WR <= 1'b1; end
                            else begin sw <= 1'b1; routine <= `SUB_WRITE_MEM; end

                            m <= `INIT;


                        end else begin WReg <= i; CBit <= 1'b0; end

                        ip <= ip + 1'b1;

                    end

                endcase


                8'b1100_001x: case (micro)


                    3'h0: begin

                        micro    <= 3'h1;

                        CBit     <= 1'b1;
                        ea       <= ea + 1'b1;
                        WReg     <= sp + 2'h2;


                        {CBit, CReg, WR} <= {1'b1, 3'h4, 1'b1};

                        op1[ 7:0] <= i;

                    end


                    3'h1: begin

                        micro     <= 3'h2;
                        WR        <= 1'b0;
                        sw        <= 1'b0;
                        op1[15:8] <= i;

                        if (opcode[0]) begin m <= `INIT; ip <= {i, op1[7:0]}; end

                     end


                    3'h2: begin WReg <= sp + i; ip <= ip + 1'b1; micro <= 3'h3; WR <= 1'b1; end
                    3'h3: begin WReg[15:8] <= WReg[15:8] + i; m <= `INIT; ip <= op1; end

                endcase


                8'b1001_100x: begin WR <= 1'b1; m <= `INIT; end


                8'b1110_10x1: case (micro)

                    3'h0: begin

                        if (~opcode[1])begin op1 <= ip + i; ip <= ip + 1'b1; end
                        else begin ip <= ip + {{8{i[7]}}, i[7:0]} + 1'b1; m <= `INIT; end
                        micro <= 3'h1;

                    end


                    3'h1: begin ip <= {op1[15:8] + i, op1[7:0]} + 2'h2; m <= `INIT; end

                endcase


                8'b1110_1000: case (micro)


                    3'h0: begin

                        micro   <= 3'h1;
                        op1     <= ip + i;
                        ip      <= ip + 1'b1;
                        WReg    <= sp - 2'h2;
                        ea      <= sp - 2'h2;

                        {CBit, CReg, WR} <= { 1'b1, 3'h4, 1'b1 };

                    end


                    3'h1: begin

                        WR   <= 1'b0;
                        WReg <= ip + 1'b1;
                        ip   <= {op1[15:8] + i, op1[7:0]} + 2'h2;
                        sw   <= 1'b1;
                        routine <= `SUB_WRITE_MEM;
                        m    <= `INIT;

                    end

                endcase


                8'b1110_00xx: begin


                    if (opcode[1:0] == 2'b11) begin

                        ip <= cx ? ip + 1'b1 : ({{8{i[7]}}, i[7:0]} + ip + 1'b1);

                    end else begin

                        WReg <= cx - 1'b1;


                        {CReg, CBit, WR} <= {3'h1, 1'b1, 1'b1};


                        if (cx == 1'b1 || (!opcode[1] && (opcode[0] ^ flags[6]))) begin
                            ip <= ip + 1'b1;
                        end
                        else begin
                            ip <= ip + {{8{i[7]}}, i[7:0]} + 1'b1;
                        end

                    end

                    m <= `INIT;

                end


                8'b0100_xxxx: case (micro)

                    3'h0: begin op1 <= DReg; micro <= 3'h1; end
                    3'h1: begin WR <= 1'b1; WReg <= Ar; flags <= Af; m <= `INIT; end

                endcase


                8'b0101_0xxx: begin

                    WReg    <= DReg;
                    routine <= `SUB_PUSH;
                    m       <= `INIT;

                end


                8'b0101_1xxx: case (micro)

                    3'h0: begin routine <= `SUB_POP; micro <= 1'b1; end
                    3'h1: begin WR <= 1'b1; CReg <= opcode[2:0];  m <= `INIT; end

                endcase


                8'b1001_0xxx: case (micro)

                    3'h0: begin CReg <= 1'b0; WR <= 1'b1; WReg <= DReg; micro <= 1'b1; end
                    3'h1: begin CReg <= opcode[2:0]; WReg <= op1; m <= `INIT; end

                endcase


                8'b0111_xxxx: begin


                    ip <= ip + ((condition ^ opcode[0]) ? {{8{i[7]}}, i[7:0]} + 2'h1 : 1'h1);
                    m  <= `INIT;

                end


                8'b1001_1101: begin

                    flags <= WReg;
                    m <= `INIT;

                end


                8'b1110_x1xx: case (micro)

                    3'h0: begin


                        if (~opcode[3]) begin port_addr <= i; ip <= ip + 1'b1; end


                        port_out  <= ax;
                        micro     <= 1'b1;
                        port_read <= ~opcode[1];

                    end


                    3'h1: begin port_read <= 1'b0; port_clk <= opcode[1]; micro <= opcode[1] ? 2'h2 : 3'h3; end


                    3'h2: begin port_clk <= 1'b0; CReg <= 4'h0; WReg <= port_in; WR <= ~opcode[1]; m <= `INIT; end


                    3'h3: micro <= 3'h2;

                endcase


                8'b1101_00xx: case (micro)


                    3'h0: begin

                        micro <= 3'h1;
                        SMod  <= modrm[5:3];

                        casex (opcode[1:0])
                            2'b0x: SCnt <= 1'b1;
                            2'b10: begin SCnt <= cx[3:0]; if (cx[3:0] == 1'b0) m <= `INIT; end
                            2'b11: begin SCnt <= cx[4:0]; if (cx[4:0] == 1'b0) m <= `INIT; end
                        endcase

                    end


                    3'h1: begin


                        if (SCnt) begin

                            op1   <= Sr;
                            WReg  <= Sr;
                            flags <= {flags[11:1], Sc};
                            SCnt  <= SCnt - 1'b1;

                        end


                        else if (modrm[7:6] == 2'b11) begin

                            WR   <= 1'b1;
                            CReg <= modrm[2:0];
                            m    <= `INIT;
                            sw   <= 1'b0;

                        end


                        else routine <= `SUB_WRITE_MEM;

                    end

                endcase


                8'b1000_011x: case (micro)


                    3'h0: begin

                        WReg  <= op2;
                        op2   <= op1;
                        micro <= 3'h1;


                        if (modrm[7:6] == 2'b11) begin

                            CReg <= modrm[2:0];
                            WR   <= 1'b1;

                        end
                        else routine <= `SUB_WRITE_MEM;

                    end


                    3'h1: begin

                        CBit <= opcode[0];
                        CReg <= modrm[5:3];
                        WReg <= op2;
                        WR   <= 1'b1;
                        m    <= `INIT;

                    end

                endcase
                

                8'b1101_0111: begin
                
                    WR <= 1'b1;
                    sw <= 1'b0;
                    WReg <= i;
                    m <= `EXEC;
                
                end
                

                8'b1010_00xx: case (micro)
                

                    3'h0: begin micro <= 3'h1; ea[7:0]  <= i; ip <= ip + 1'b1; end
                    3'h1: begin micro <= 3'h2; ea[15:8] <= i; ip <= ip + 1'b1; sw <= 1'b1; end
                    

                    3'h2: if (opcode[1]) begin WReg <= DReg; routine <= routine <= `SUB_WRITE_MEM; end

                          else begin micro <= 3'h3; WReg <= i; WR <= 1'b1; ea <= ea + 1'b1; sw <= opcode[0];
                                     if (~opcode[0]) m <= `INIT; end
                                     

                    3'h3: begin WReg[15:8] <= i; sw <= 1'b0; m <= `INIT; end
                
                endcase
                

                8'b1000_010x: begin
                
                    flags <= Af;
                    sw <= 1'b0;
                    m <= `INIT;
                
                end
                

                8'b1010_100x: case (micro)

                    3'h0: begin micro <= 3'h1; op1 <= DReg; op2 <= i; CBitT <= CBit; ip <= ip + 1'b1; end
                    3'h1: if (CBitT) begin CBitT <= 1'b0; op2[15:8] <= i; ip <= ip + 1'b1; end
                          else       begin flags <= Af; m <= `INIT; end
                
                endcase
                

                8'b1111_011x: case (modrm[5:3])                
                

                    3'b000, 3'b001: begin
                    
                        case (micro)
                        
                            3'h0: begin micro <= 3'h1; sw  <= 1'b0;  end
                            3'h1: begin micro <= 3'h2; op2 <= i; ip <= ip + 1'b1; CBitT <= CBit; end
                            3'h2: if (CBitT) begin CBitT <= 1'b0; ip <= ip + 1'b1; op2[15:8] <= i; end
                                  else       begin flags <= Af; m <= `INIT; end

                        endcase
                    
                    end
                
                endcase
                
            endcase

        endcase

    endcase

end

endmodule
module cpu(

    input   wire        reset,


    input   wire        clk,
    input   wire        clk25,
    input   wire [7:0]  i,
    output  reg  [7:0]  o,
    output  wire [15:0] a,
    output  reg         w,


    output  reg  [15:0] port_addr,
    input   wire [15:0] port_in,
    output  reg  [15:0] port_out,
    output  reg         port_bit,
    output  reg         port_clk,
    output  reg         port_read

);


`define INIT         0
`define MODRM        1
`define EXEC         2


`define SUB_NORMAL      0

`define SUB_WRITE_MEM   1
`define SUB_WRITE_MEM2  2

`define SUB_PUSH        3
`define SUB_PUSH2       4
`define SUB_PUSH3       5

`define SUB_POP         6
`define SUB_POP2        7
`define SUB_POP3        8


assign a = sw ? ea : ip;

wire __sig = m == 1'b0 && routine == 1'b0;

initial begin o = 8'h00; w = 1'b0; port_addr = 1'b0; port_out = 1'b0; port_bit = 1'b0; port_clk = 1'b0; port_read = 1'b0; end



reg [1:0]  m  = 1'b0;
reg        sw = 1'b0;
reg [15:0] ea = 16'h0000;
reg [ 7:0] opcode = 8'h00;
reg [ 7:0] modrm  = 8'h00;
reg [ 2:0] modrm_stage = 1'b0;
reg [ 3:0] routine = 1'b0;
reg [ 2:0] micro = 1'b0;



reg [2:0]  CReg = 3'b000;
reg [2:0]  CAlu = 3'b000;
reg        CBit  = 1'b0;
reg        CBitT = 1'b0;
reg        DBit = 1'b0;
reg [2:0]  SMod = 1'b0;
reg [4:0]  SCnt = 1'b0;
reg [2:0]  CSel = 1'b0;
reg [15:0] DReg;
reg [15:0] WReg = 1'b0;
reg        WR   = 1'b0;

reg [15:0] op1 = 1'b0;
reg [15:0] op2 = 1'b0;


reg [15:0] ax    = 16'h2F3F;
reg [15:0] cx    = 16'h0002;
reg [15:0] dx    = 16'h64EA;
reg [15:0] bx    = 16'hB002;
reg [15:0] sp    = 16'hC000;
reg [15:0] bp    = 16'h0000;
reg [15:0] si    = 16'h1234;
reg [15:0] di    = 16'h0000;

reg [11:0] flags = 12'b0000_0000_0000;
reg [15:0] ip    = 16'hFFF0;


always @* begin
    case (CReg)
        3'h0: DReg = CBit ? ax : {8'h00, ax[7:0]};
        3'h1: DReg = CBit ? cx : {8'h00, cx[7:0]};
        3'h2: DReg = CBit ? dx : {8'h00, dx[7:0]};
        3'h3: DReg = CBit ? bx : {8'h00, bx[7:0]};
        3'h4: DReg = CBit ? sp : {8'h00, ax[15:8]};
        3'h5: DReg = CBit ? bp : {8'h00, cx[15:8]};
        3'h6: DReg = CBit ? si : {8'h00, dx[15:8]};
        3'h7: DReg = CBit ? di : {8'h00, bx[15:8]};
    endcase
end


always @(negedge clk25) if (WR)
case (CReg)
    3'h0: if (CBit) ax <= WReg; else ax[7:0] <= WReg[7:0];
    3'h1: if (CBit) cx <= WReg; else cx[7:0] <= WReg[7:0];
    3'h2: if (CBit) dx <= WReg; else dx[7:0] <= WReg[7:0];
    3'h3: if (CBit) bx <= WReg; else bx[7:0] <= WReg[7:0];
    3'h4: if (CBit) sp <= WReg; else ax[15:8] <= WReg[7:0];
    3'h5: if (CBit) bp <= WReg; else cx[15:8] <= WReg[7:0];
    3'h6: if (CBit) si <= WReg; else dx[15:8] <= WReg[7:0];
    3'h7: if (CBit) di <= WReg; else bx[15:8] <= WReg[7:0];
endcase





reg [16:0] Ar;
reg [11:0] Af;


wire Zero8  = ~|Ar[7:0];
wire Zero16 = ~|Ar[15:8] && Zero8;
wire Sign8  =   Ar[7];
wire Sign16 =   Ar[15];
wire Parity = ~^Ar[7:0];


wire ADD_Overflow8  = (op1[7]  ^ op2[7]  ^ 1'b1) & (op2[7]  ^ Ar[7]);
wire ADD_Overflow16 = (op1[15] ^ op2[15] ^ 1'b1) & (op2[15] ^ Ar[15]);
wire SUB_Overflow8  = (op1[7]  ^ op2[7]        ) & (op2[7]  ^ Ar[7]);
wire SUB_Overflow16 = (op1[15] ^ op2[15]       ) & (op2[15] ^ Ar[15]);

always @* begin

    case (CAlu)

3'h0: Ar = op1 + op2;
3'h1: Ar = op1 | op2;
3'h2: Ar = op1 + op2 + flags[0];
3'h3: Ar = op1 - op2 - flags[0];
3'h4: Ar = op1 & op2;
3'h5: Ar = op1 - op2;
3'h6: Ar = op1 ^ op2;
3'h7: Ar = op1 - op2;

    endcase

    case (CAlu)


        3'h0, 3'h2:
            Af = {
CBit ? ADD_Overflow16 : ADD_Overflow8,
flags[10],
flags[9],
flags[8],
CBit ? Sign16 : Sign8,
CBit ? Zero16 : Zero8,
1'b0,
op1[3:0] + op2[3:0] + (CAlu == 3'h2? flags[0] : 1'b0) >= 5'h10,
1'b0,
Parity,
1'b1,
CBit ? Ar[16] : Ar[8]
            };


        3'h3, 3'h5, 3'h7:
            Af = {
CBit ? SUB_Overflow16 : SUB_Overflow8,
flags[10],
flags[9],
flags[8],
CBit ? Sign16 : Sign8,
CBit ? Zero16 : Zero8,
1'b0,
op1[3:0] < op2[3:0] + (CAlu == 3'h3? flags[0] : 1'b0),
1'b0,
Parity,
1'b1,
CBit ? Ar[16] : Ar[8]
            };


        default:
            Af = {
1'b0,
flags[10],
flags[9],
flags[8],
CBit ? Sign16 : Sign8,
CBit ? Zero16 : Zero8,
1'b0,
Ar[4],
1'b0,
Parity,
1'b1,
1'b0
            };

    endcase

end


wire condition =
    CSel == 3'b000 ? flags[11] :
    CSel == 3'b001 ? flags[0] :
    CSel == 3'b010 ? flags[6] :
    CSel == 3'b011 ? (flags[0] | flags[6]) :
    CSel == 3'b100 ? flags[7] :
    CSel == 3'b101 ? flags[2] :
    CSel == 3'b110 ? (flags[7] ^ flags[11]) :
                     (flags[7] ^ flags[11]) | (flags[6]);


reg [15:0] Sr;
reg        Sc;


always @* begin

    case (SMod)

3'h0: Sr = CBit ? {op1[14:0], op1[15]}   : {op1[6:0], op1[7]};
3'h1: Sr = CBit ? {op1[0],    op1[15:1]} : {op1[0],   op1[7:1]};
3'h2: Sr = CBit ? {op1[14:0], flags[0]}  : {op1[6:0], flags[0]};
3'h3: Sr = CBit ? {flags[0],  op1[15:1]} : {flags[0], op1[7:1]};
3'h4, 3'h6:
                        Sr = CBit ? {op1[14:0], 1'b0}      : {op1[6:0], 1'b0};
3'h5: Sr = CBit ? {1'b0,      op1[15:1]} : {1'b0,     op1[7:1]};
3'h7: Sr = CBit ? {op1[15],   op1[15:1]} : {op1[7],   op1[7:1]};

    endcase

    case (SMod)


        3'h0, 3'h2, 3'h4, 3'h6: Sc = CBit ? op1[15] : op1[7];


        3'h1, 3'h3, 3'h5, 3'h7: Sc = op1[0];

    endcase

end





always @(posedge clk25) begin


    if (reset) begin

        ip <= 16'hFFF0;
        routine <= 1'b0;
        {sw, m} <= 2'b00;

    end
    

    else case (routine)


        `SUB_WRITE_MEM:  begin o <= WReg[7:0]; w <= 1'b1; routine <= `SUB_WRITE_MEM2; end
        `SUB_WRITE_MEM2: begin

            routine <= CBit? `SUB_WRITE_MEM2 : `SUB_NORMAL;
            o    <= WReg[15:8];
            ea   <= ea + 1'b1;
            w    <= CBit;
            sw   <= CBit;
            CBit <= 1'b0;

        end


        `SUB_PUSH:  begin routine <= `SUB_PUSH2;  o  <= WReg[7:0];    CBit <= 1'b1; ea <= sp - 2;    sw   <= 1'b1;   w <= 1'b1; end
        `SUB_PUSH2: begin routine <= `SUB_PUSH3;  o  <= WReg[15:8];   WR   <= 1'b1; ea <= ea + 1'b1; WReg <= sp - 2; CReg <= 3'h4; end
        `SUB_PUSH3: begin routine <= `SUB_NORMAL; {w, sw} <= {2'b00}; WR   <= 1'b0; end


        `SUB_POP:  begin routine <= `SUB_POP2;   WReg <= sp + 2'h2; ea <= sp;        WR <= 1'b1; {CReg, sw, CBit} <= {3'h4, 2'b11}; end
        `SUB_POP2: begin routine <= `SUB_POP3;   WReg[7:0]  <= i;   ea <= ea + 1'b1; WR <= 1'b0; end
        `SUB_POP3: begin routine <= `SUB_NORMAL; WReg[15:8] <= i;   sw <= 1'b0; end


        default: case (m)


            `INIT: begin

                opcode      <= i;
                micro       <= 1'b0;
                modrm_stage <= 1'b0;
                WR          <= 1'b0;
                ip     <= ip + 1'b1;

                casex (i)


                    8'b00_xxx_0xx: begin

                        CAlu <= i[5:3];
                        {DBit, CBit} <= i[1:0];
                        m    <= `MODRM;

                    end


                    8'b00_xxx_10x: begin

                        CReg <= 3'h0;
                        CAlu <= i[5:3];
                        {DBit, CBit} <= i[1:0];
                        m    <= `EXEC;

                    end
                    

                    8'b1000_0xxx,
                    8'b1111_011x: begin


                        {DBit, CBit} <= {1'b0, i[0]};
                        CAlu <= 3'h4;
                        m <= `MODRM;

                    end


                    8'b1000_10xx: begin

                        {DBit, CBit} <= i[1:0];
                        m <= `MODRM;

                    end


                    8'b1011_xxxx: begin


                        {CBit, CReg} <= i[3:0];
                        m <= `EXEC;

                    end


                    8'b1100_011x: begin

                        {DBit, CBit} <= {1'b0, i[0]};
                        m <= `MODRM;

                    end


                    8'b1100_001x: begin

                        ea <= sp;
                        sw <= 1'b1;
                        m  <= `EXEC;

                    end


                    8'b0111_xxxx: begin

                        CSel <= i[4:1];
                        m <= `EXEC;

                    end


                    8'b1111_0101: flags[0] <= ~flags[0];
                    8'b1111_100x: flags[0] <= i[0];
                    8'b1111_101x: flags[9] <= i[0];
                    8'b1111_110x: flags[10] <= i[0];
                    8'b1001_0000: beginend


                    8'b1001_100x: begin

                        WReg <= i[0] ? {16{ax[15]}} : {{8{ax[7]}}, ax[7:0]};
                        CBit <= 1'b1;
                        CReg <= i[0] ? 3'h2 : 3'h0;
                        m <= `EXEC;

                    end


                    8'b0100_xxxx: begin

                        {CReg, CBit} <= {i[2:0], 1'b1};
                        op2   <= 1'b1;
                        CAlu  <= i[3] ?3'h5 :3'h0;
                        m     <= `EXEC;

                    end


                    8'b0101_xxxx: begin

                        {CBit, CReg} <= {1'b1, i[2:0]};
                        m <= `EXEC;

                    end


                    8'b1001_0xxx: begin

                        {CBit, CReg} <= {1'b1, i[2:0]};
                        op1 <= ax;
                        m   <= `EXEC;

                    end


                    8'b1001_1100: begin

                        WReg <= flags;
                        routine <= `SUB_PUSH;

                    end


                    8'b1001_1101: begin

                        routine <= `SUB_POP;
                        m <= `EXEC;

                    end


                    8'b1110_x1xx: begin

                        CBit      <= i[0];
                        port_bit  <= i[0];
                        port_addr <= dx;
                        m <= `EXEC;

                    end


                    8'b1101_00xx: begin

                        {DBit, CBit} <= {1'b0, i[0]};
                        m <= `MODRM;

                    end


                    8'b1010_00xx: begin
                    
                        {CReg, CBit} <= {3'b000, i[0]};
                        m <= `EXEC;
                    
                    end


                    8'b1101_0111: begin
                    
                        ea <= bx + {8'h00, ax[7:0]};
                        {CReg, CBit} <= {3'h0, 1'b0};
                        sw <= 1'b1;                                        
                        m  <= `EXEC;                        
                    
                    end


                    8'b1010_100x: begin
                    
                        {CReg, CBit} <= {3'b000, i[0]};
                        CAlu <= 3'h4;
                        m <= `EXEC;
                    
                    end


                    8'b1001_1110: flags <= ax[15:8];
                    8'b1001_1111: begin 
                        
                        {CBit, CReg} <= {1'h0, 3'h4};
                        WReg <= flags;
                        WR <= 1'b1;
                        
                    end


                    default: m <= `EXEC;

                endcase

            end


            `MODRM: case (modrm_stage)


                3'h0: begin


                    modrm <= i;


                    case (i[2:0])
                        3'h0: ea <= bx + si;
                        3'h1: ea <= bx + di;
                        3'h2: ea <= bp + si;
                        3'h3: ea <= bp + di;
                        3'h4: ea <= si;
                        3'h5: ea <= di;
                        3'h6: ea <= (i[7:6] == 2'b00) ? 16'h0000 : bp;
                        3'h7: ea <= bx;
                    endcase




                    CReg <= i[5:3];


                    sw <= (i[7:6] == 2'b00) && (i[2:0] != 3'h6);


                    ip <= ip + 1'b1;


                    modrm_stage <= 3'h1;

                end


                3'h1: begin


                    op1 <= DBit ? DReg : i;
                    op2 <= DBit ? i : DReg;


                    CReg <= modrm[2:0];


                    case (modrm[7:6])


                        2'b00: begin


                            if (modrm[2:0] == 3'h6) begin ip <= ip + 1'b1; ea[7:0] <= i; modrm_stage <= 3'h3; end


                            else if (CBit) begin ea <= ea + 1'b1; modrm_stage <= 3'h5; end


                            else begin m <= `EXEC; end

                        end


                        2'b01: begin modrm_stage <= 3'h4; ip <= ip + 1'b1; ea <= ea + {{8{i[7]}}, i[7:0]}; sw <= 1'b1; end


                        2'b10: begin modrm_stage <= 3'h3; ip <= ip + 1'b1; ea <= ea + {8'h00, i[7:0]}; end


                        2'b11: begin modrm_stage <= 3'h2; end

                    endcase

                end


                3'h2: begin

                    op1 <= DBit ? op1 : DReg;
                    op2 <= DBit ? DReg : op2;
                    m <= `EXEC;

                end


                3'h3: begin

                   ea[15:8] <= ea[15:8] + i;
                   ip <= ip + 1'b1;
                   sw <= 1'b1;
                   modrm_stage <= 3'h4;

                end


                3'h4: begin


                    op1 <= DBit ? op1 : i;
                    op2 <= DBit ? i : op2;


                    if (CBit) begin modrm_stage <= 3'h5; ea <= ea + 1'b1; end


                    else m <= `EXEC;

                end


                3'h5: begin

                    op1[15:8] <= DBit ? op1[15:8] : i;
                    op2[15:8] <= DBit ? i : op2[15:8];


                    ea <= ea - 1'b1;
                    m <= `EXEC;

                end

            endcase


            `EXEC: casex (opcode)


                8'b00_xxx_0xx: begin


                    if (CAlu < 3'h7) begin


                        WReg <= Ar;



                        if (modrm[7:6] == 2'b11 || DBit) begin

                            CReg <= DBit ? modrm[5:3] : modrm[2:0];
                            WR   <= 1'b1;
                            sw   <= 1'b0;

                        end


                        else routine <= `SUB_WRITE_MEM;

                    end

                    flags <= Af;
                    m     <= `INIT;

                end


                8'b00_xxx_10x: case (micro)


                    3'h0: begin

                        micro <= 3'h1;
                        op1   <= DReg;
                        op2   <= i;
                        ip    <= ip + 1'b1;

                    end


                    3'h1: begin

                        micro <= 3'h2;
                        WR    <= CAlu != 3'h7;
                        WReg  <= Ar;
                        ip    <= ip + opcode[0];
                        flags <= Af;

                        if (~CBit) m <= `INIT;
                        op2[15:8] <= i;

                    end


                    3'h2: begin

                        WReg  <= Ar;
                        flags <= Af;
                        m     <= `INIT;

                    end

                endcase


                8'b1000_00xx: case (micro)


                    3'h0: begin sw <= 1'b0; micro <= 3'h1; CAlu <= modrm[5:3]; end


                    3'h1: begin op2 <= i; micro <= 3'h2; ip <= ip + 1'b1; CBitT <= opcode[0]; end


                    3'h2: begin


                        if (CBitT) begin


                            op2[15:8] <= opcode[1] ? {8{op2[7]}} : i;


                            if (opcode[1] == 1'b0)
                                ip <= ip + 1'b1;


                            CBitT     <= 1'b0;

                        end


                        else begin

                            WReg  <= Ar;
                            flags <= Af;
                            m     <= `INIT;


                            if (modrm[7:6] == 2'b11) begin WR <= (CAlu != 3'h7); end


                            else begin sw <= 1'b1; routine <= `SUB_WRITE_MEM; end

                        end

                    end

                endcase


                8'b1000_10xx: begin

                    WReg <= op2;
                    m    <= `INIT;

                    if (modrm[7:6] == 2'b11 || DBit) begin

                        CReg <= DBit ? modrm[5:3] : modrm[2:0];
                        WR   <= 1'b1;
                        sw   <= 1'b0;

                    end
                    else routine <= `SUB_WRITE_MEM;

                end


                8'b1011_xxxx: case (micro)


                    3'h0: begin WReg <= i; WR <= 1'b1; micro <= 3'h1; ip <= ip + 1'b1; if (~CBit) m <= `INIT; end


                    3'h1: begin WReg[15:8] <= i; m <= `INIT; ip <= ip + 1'b1; end

                endcase


                8'b1100_011x: case (micro)


                    3'h0: begin sw <= 1'b0; CReg <= modrm[2:0]; micro <= 3'h1; end


                    3'h1: begin


                        if (~CBit) begin

                            CBit <= opcode[0];
                            WReg <= opcode[0] ? {i, WReg[7:0]} : i;

                            if (modrm[7:6] == 2'b11)
                                 begin WR <= 1'b1; end
                            else begin sw <= 1'b1; routine <= `SUB_WRITE_MEM; end

                            m <= `INIT;


                        end else begin WReg <= i; CBit <= 1'b0; end

                        ip <= ip + 1'b1;

                    end

                endcase


                8'b1100_001x: case (micro)


                    3'h0: begin

                        micro    <= 3'h1;

                        CBit     <= 1'b1;
                        ea       <= ea + 1'b1;
                        WReg     <= sp + 2'h2;


                        {CBit, CReg, WR} <= {1'b1, 3'h4, 1'b1};

                        op1[ 7:0] <= i;

                    end


                    3'h1: begin

                        micro     <= 3'h2;
                        WR        <= 1'b0;
                        sw        <= 1'b0;
                        op1[15:8] <= i;

                        if (opcode[0]) begin m <= `INIT; ip <= {i, op1[7:0]}; end

                     end


                    3'h2: begin WReg <= sp + i; ip <= ip + 1'b1; micro <= 3'h3; WR <= 1'b1; end
                    3'h3: begin WReg[15:8] <= WReg[15:8] + i; m <= `INIT; ip <= op1; end

                endcase


                8'b1001_100x: begin WR <= 1'b1; m <= `INIT; end


                8'b1110_10x1: case (micro)

                    3'h0: begin

                        if (~opcode[1])begin op1 <= ip + i; ip <= ip + 1'b1; end
                        else begin ip <= ip + {{8{i[7]}}, i[7:0]} + 1'b1; m <= `INIT; end
                        micro <= 3'h1;

                    end


                    3'h1: begin ip <= {op1[15:8] + i, op1[7:0]} + 2'h2; m <= `INIT; end

                endcase


                8'b1110_1000: case (micro)


                    3'h0: begin

                        micro   <= 3'h1;
                        op1     <= ip + i;
                        ip      <= ip + 1'b1;
                        WReg    <= sp - 2'h2;
                        ea      <= sp - 2'h2;

                        {CBit, CReg, WR} <= { 1'b1, 3'h4, 1'b1 };

                    end


                    3'h1: begin

                        WR   <= 1'b0;
                        WReg <= ip + 1'b1;
                        ip   <= {op1[15:8] + i, op1[7:0]} + 2'h2;
                        sw   <= 1'b1;
                        routine <= `SUB_WRITE_MEM;
                        m    <= `INIT;

                    end

                endcase


                8'b1110_00xx: begin


                    if (opcode[1:0] == 2'b11) begin

                        ip <= cx ? ip + 1'b1 : ({{8{i[7]}}, i[7:0]} + ip + 1'b1);

                    end else begin

                        WReg <= cx - 1'b1;


                        {CReg, CBit, WR} <= {3'h1, 1'b1, 1'b1};


                        if (cx == 1'b1 || (!opcode[1] && (opcode[0] ^ flags[6]))) begin
                            ip <= ip + 1'b1;
                        end
                        else begin
                            ip <= ip + {{8{i[7]}}, i[7:0]} + 1'b1;
                        end

                    end

                    m <= `INIT;

                end


                8'b0100_xxxx: case (micro)

                    3'h0: begin op1 <= DReg; micro <= 3'h1; end
                    3'h1: begin WR <= 1'b1; WReg <= Ar; flags <= Af; m <= `INIT; end

                endcase


                8'b0101_0xxx: begin

                    WReg    <= DReg;
                    routine <= `SUB_PUSH;
                    m       <= `INIT;

                end


                8'b0101_1xxx: case (micro)

                    3'h0: begin routine <= `SUB_POP; micro <= 1'b1; end
                    3'h1: begin WR <= 1'b1; CReg <= opcode[2:0];  m <= `INIT; end

                endcase


                8'b1001_0xxx: case (micro)

                    3'h0: begin CReg <= 1'b0; WR <= 1'b1; WReg <= DReg; micro <= 1'b1; end
                    3'h1: begin CReg <= opcode[2:0]; WReg <= op1; m <= `INIT; end

                endcase


                8'b0111_xxxx: begin


                    ip <= ip + ((condition ^ opcode[0]) ? {{8{i[7]}}, i[7:0]} + 2'h1 : 1'h1);
                    m  <= `INIT;

                end


                8'b1001_1101: begin

                    flags <= WReg;
                    m <= `INIT;

                end


                8'b1110_x1xx: case (micro)

                    3'h0: begin


                        if (~opcode[3]) begin port_addr <= i; ip <= ip + 1'b1; end


                        port_out  <= ax;
                        micro     <= 1'b1;
                        port_read <= ~opcode[1];

                    end


                    3'h1: begin port_read <= 1'b0; port_clk <= opcode[1]; micro <= opcode[1] ? 2'h2 : 3'h3; end


                    3'h2: begin port_clk <= 1'b0; CReg <= 4'h0; WReg <= port_in; WR <= ~opcode[1]; m <= `INIT; end


                    3'h3: micro <= 3'h2;

                endcase


                8'b1101_00xx: case (micro)


                    3'h0: begin

                        micro <= 3'h1;
                        SMod  <= modrm[5:3];

                        casex (opcode[1:0])
                            2'b0x: SCnt <= 1'b1;
                            2'b10: begin SCnt <= cx[3:0]; if (cx[3:0] == 1'b0) m <= `INIT; end
                            2'b11: begin SCnt <= cx[4:0]; if (cx[4:0] == 1'b0) m <= `INIT; end
                        endcase

                    end


                    3'h1: begin


                        if (SCnt) begin

                            op1   <= Sr;
                            WReg  <= Sr;
                            flags <= {flags[11:1], Sc};
                            SCnt  <= SCnt - 1'b1;

                        end


                        else if (modrm[7:6] == 2'b11) begin

                            WR   <= 1'b1;
                            CReg <= modrm[2:0];
                            m    <= `INIT;
                            sw   <= 1'b0;

                        end


                        else routine <= `SUB_WRITE_MEM;

                    end

                endcase


                8'b1000_011x: case (micro)


                    3'h0: begin

                        WReg  <= op2;
                        op2   <= op1;
                        micro <= 3'h1;


                        if (modrm[7:6] == 2'b11) begin

                            CReg <= modrm[2:0];
                            WR   <= 1'b1;

                        end
                        else routine <= `SUB_WRITE_MEM;

                    end


                    3'h1: begin

                        CBit <= opcode[0];
                        CReg <= modrm[5:3];
                        WReg <= op2;
                        WR   <= 1'b1;
                        m    <= `INIT;

                    end

                endcase
                

                8'b1101_0111: begin
                
                    WR <= 1'b1;
                    sw <= 1'b0;
                    WReg <= i;
                    m <= `EXEC;
                
                end
                

                8'b1010_00xx: case (micro)
                

                    3'h0: begin micro <= 3'h1; ea[7:0]  <= i; ip <= ip + 1'b1; end
                    3'h1: begin micro <= 3'h2; ea[15:8] <= i; ip <= ip + 1'b1; sw <= 1'b1; end
                    

                    3'h2: if (opcode[1]) begin WReg <= DReg; routine <= routine <= `SUB_WRITE_MEM; end

                          else begin micro <= 3'h3; WReg <= i; WR <= 1'b1; ea <= ea + 1'b1; sw <= opcode[0];
                                     if (~opcode[0]) m <= `INIT; end
                                     

                    3'h3: begin WReg[15:8] <= i; sw <= 1'b0; m <= `INIT; end
                
                endcase
                

                8'b1000_010x: begin
                
                    flags <= Af;
                    sw <= 1'b0;
                    m <= `INIT;
                
                end
                

                8'b1010_100x: case (micro)

                    3'h0: begin micro <= 3'h1; op1 <= DReg; op2 <= i; CBitT <= CBit; ip <= ip + 1'b1; end
                    3'h1: if (CBitT) begin CBitT <= 1'b0; op2[15:8] <= i; ip <= ip + 1'b1; end
                          else       begin flags <= Af; m <= `INIT; end
                
                endcase
                

                8'b1111_011x: case (modrm[5:3])                
                

                    3'b000, 3'b001: begin
                    
                        case (micro)
                        
                            3'h0: begin micro <= 3'h1; sw  <= 1'b0;  end
                            3'h1: begin micro <= 3'h2; op2 <= i; ip <= ip + 1'b1; CBitT <= CBit; end
                            3'h2: if (CBitT) begin CBitT <= 1'b0; ip <= ip + 1'b1; op2[15:8] <= i; end
                                  else       begin flags <= Af; m <= `INIT; end

                        endcase
                    
                    end
                
                endcase
                
            endcase

        endcase

    endcase

end

endmodule