data/full_repos/permissive/179451217/lfsr.v
1: b"%Error: data/full_repos/permissive/179451217/lfsr.v:69: syntax error, unexpected bit, expecting IDENTIFIER or '=' or do or final\ninteger bit;\n        ^~~\n%Error: data/full_repos/permissive/179451217/lfsr.v:82: syntax error, unexpected '=', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\n        for(bit = 0; bit < Depth-1; bit = bit + 1) begin\n                ^\n%Error: data/full_repos/permissive/179451217/lfsr.v:88: syntax error, unexpected end\nend else begin \n^~~\n%Error: data/full_repos/permissive/179451217/lfsr.v:93: syntax error, unexpected '=', expecting IDENTIFIER\n        state_D = state_in;\n                ^\n%Error: data/full_repos/permissive/179451217/lfsr.v:96: syntax error, unexpected '=', expecting IDENTIFIER\n        state_D = {state[0], state[Depth-1:1]};\n                ^\n%Error: data/full_repos/permissive/179451217/lfsr.v:98: syntax error, unexpected bit, expecting IDENTIFIER or genvar\n        for(bit = 0; bit < Depth-1; bit = bit + 1) begin\n            ^~~\n%Error: data/full_repos/permissive/179451217/lfsr.v:98: syntax error, unexpected bit, expecting new or new-then-paren\n        for(bit = 0; bit < Depth-1; bit = bit + 1) begin\n                                          ^~~\n%Error: Cannot continue\n"
module lfsr #(
    parameter Depth = 8,
    parameter Coeffs = 8'hB8,
    parameter Galois = 1
)(
    input wire clk,
    input wire reset,
    input wire enable,
    output wire out,
    input wire set_state,
    input wire [Depth-1:0] state_in
);


reg [Depth-1:0] state, state_D;
assign out = state[0];

always @(posedge clk) begin
    if(reset == 1'b1) begin
        state <= 1;
    end else begin
        state <= state_D;
    end
end

integer bit;

generate
if(Galois == 0) begin 

always @* begin
    state_D = state;
    if(set_state == 1'b1) begin
        state_D = state_in;
    end else if(enable == 1'b1) begin

        state_D = {state[Depth-2:0],state[Depth-1]};

        for(bit = 0; bit < Depth-1; bit = bit + 1) begin
            if(Coeffs[bit] == 1'b1) state_D[0] = state_D[0] ^ state[bit];
        end
    end
end

end else begin 

always @* begin
    state_D = state;
    if(set_state == 1'b1) begin
        state_D = state_in;
    end else if(enable == 1'b1) begin

        state_D = {state[0], state[Depth-1:1]};

        for(bit = 0; bit < Depth-1; bit = bit + 1) begin
            if(Coeffs[bit] == 1'b1) state_D[bit] = state[0] ^ state[bit+1];
        end
    end
end

end
endgenerate

endmodule
module lfsr #(
    parameter Depth = 8,
    parameter Coeffs = 8'hB8,
    parameter Galois = 1
)(
    input wire clk,
    input wire reset,
    input wire enable,
    output wire out,
    input wire set_state,
    input wire [Depth-1:0] state_in
);



reg [Depth-1:0] state, state_D;
assign out = state[0];

always @(posedge clk) begin
    if(reset == 1'b1) begin
        state <= 1;
    end else begin
        state <= state_D;
    end
end

integer bit;

generate
if(Galois == 0) begin 

always @* begin
    state_D = state;
    if(set_state == 1'b1) begin
        state_D = state_in;
    end else if(enable == 1'b1) begin

        state_D = {state[Depth-2:0],state[Depth-1]};

        for(bit = 0; bit < Depth-1; bit = bit + 1) begin
            if(Coeffs[bit] == 1'b1) state_D[0] = state_D[0] ^ state[bit];
        end
    end
end

end else begin 

always @* begin
    state_D = state;
    if(set_state == 1'b1) begin
        state_D = state_in;
    end else if(enable == 1'b1) begin

        state_D = {state[0], state[Depth-1:1]};

        for(bit = 0; bit < Depth-1; bit = bit + 1) begin
            if(Coeffs[bit] == 1'b1) state_D[bit] = state[0] ^ state[bit+1];
        end
    end
end

end
endgenerate

endmodule