data/full_repos/permissive/170267528/state1/tclProject/impSRAM/basic_element.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/170267528/state1/tclProject/impSRAM/basic_element.v:96: Multiple top level modules\n                                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                    : ... Top module \'yj_basic_reg_clk_n\'\nmodule yj_basic_reg_clk_n # (\n       ^~~~~~~~~~~~~~~~~~\n                                                                                                    : ... Top module \'yj_basic_signal_2lever_sync\'\nmodule yj_basic_signal_2lever_sync # \n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module yj_basic_signal_2lever_sync # 
	(
		parameter DW = 32
	) 
	(
	input	CLK,
	input	RSTn, 
	input  [DW-1:0] din,
	output [DW-1:0] dout


);

	wire [DW-1:0] sync_dat [1:0];
    
    yj_basic_reg_clk_p #(.DW(DW),.RSTVAL(1'b0)) sync_1lever(CLK, RSTn, din, sync_dat[0]);
    yj_basic_reg_clk_p #(.DW(DW),.RSTVAL(1'b0)) sync_2lever(CLK, RSTn, sync_dat[0], sync_dat[1]);


	assign dout = sync_dat[1];
  
endmodule
module yj_basic_signal_2lever_sync # 
	(
		parameter DW = 32
	) 
	(
	input	CLK,
	input	RSTn, 
	input  [DW-1:0] din,
	output [DW-1:0] dout


);


	wire [DW-1:0] sync_dat [1:0];
    
    yj_basic_reg_clk_p #(.DW(DW),.RSTVAL(1'b0)) sync_1lever(CLK, RSTn, din, sync_dat[0]);
    yj_basic_reg_clk_p #(.DW(DW),.RSTVAL(1'b0)) sync_2lever(CLK, RSTn, sync_dat[0], sync_dat[1]);


	assign dout = sync_dat[1];
  
endmodule