data/full_repos/permissive/173059417/rtl/TP801_TOP.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:480: Signal definition not found, creating implicitly: \'CPU_M1_N\'\n                                                                           : ... Suggested alternative: \'CPU_M1\'\nassign CPU_M1 = ~CPU_M1_N;\n                 ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:481: Signal definition not found, creating implicitly: \'CPU_MREQ_N\'\n                                                                           : ... Suggested alternative: \'CPU_MREQ\'\nassign CPU_MREQ = ~CPU_MREQ_N;\n                   ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:482: Signal definition not found, creating implicitly: \'CPU_IORQ_N\'\n                                                                           : ... Suggested alternative: \'CPU_IORQ\'\nassign CPU_IORQ = ~CPU_IORQ_N;\n                   ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:483: Signal definition not found, creating implicitly: \'CPU_RD_N\'\n                                                                           : ... Suggested alternative: \'CPU_M1_N\'\nassign CPU_RD = ~CPU_RD_N;\n                 ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:484: Signal definition not found, creating implicitly: \'CPU_WR_N\'\n                                                                           : ... Suggested alternative: \'CPU_M1_N\'\nassign CPU_WR = ~CPU_WR_N;\n                 ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:485: Signal definition not found, creating implicitly: \'CPU_RFSH_N\'\n                                                                           : ... Suggested alternative: \'CPU_RFSH\'\nassign CPU_RFSH = ~CPU_RFSH_N;\n                   ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:486: Signal definition not found, creating implicitly: \'CPU_HALT_N\'\n                                                                           : ... Suggested alternative: \'CPU_HALT\'\nassign CPU_HALT= ~CPU_HALT_N;\n                  ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:487: Signal definition not found, creating implicitly: \'CPU_BUSAK_N\'\n                                                                           : ... Suggested alternative: \'CPU_BUSAK\'\nassign CPU_BUSAK = ~CPU_BUSAK_N;\n                    ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:489: Signal definition not found, creating implicitly: \'CPU_RESET_N\'\n                                                                           : ... Suggested alternative: \'CPU_RESET\'\nassign CPU_RESET_N = ~CPU_RESET;\n       ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:490: Signal definition not found, creating implicitly: \'CPU_WAIT_N\'\n                                                                           : ... Suggested alternative: \'CPU_HALT_N\'\nassign CPU_WAIT_N = ~CPU_WAIT;\n       ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:491: Signal definition not found, creating implicitly: \'CPU_INT_N\'\n                                                                           : ... Suggested alternative: \'CPU_INT\'\nassign CPU_INT_N = ~CPU_INT;  \n       ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:493: Signal definition not found, creating implicitly: \'CPU_NMI_N\'\n                                                                           : ... Suggested alternative: \'CPU_M1_N\'\nassign CPU_NMI_N = ~CPU_NMI;\n       ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:494: Signal definition not found, creating implicitly: \'CPU_BUSRQ_N\'\n                                                                           : ... Suggested alternative: \'CPU_BUSAK_N\'\nassign CPU_BUSRQ_N = ~CPU_BUSRQ;\n       ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:545: Signal definition not found, creating implicitly: \'ADDRESS_RAM_2\'\n                                                                           : ... Suggested alternative: \'ADDRESS_PROM2\'\nassign ADDRESS_RAM_2  = (CPU_A[15:12] == 4\'h2)?1\'b1:1\'b0;\n       ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:983: Signal definition not found, creating implicitly: \'AUD_CTRL_CLK\'\nassign AUD_XCK = AUD_CTRL_CLK;\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:311: Cannot find file containing module: \'RESET_DE\'\nRESET_DE RESET_DE(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173059417/rtl,data/full_repos/permissive/173059417/RESET_DE\n             data/full_repos/permissive/173059417/rtl,data/full_repos/permissive/173059417/RESET_DE.v\n             data/full_repos/permissive/173059417/rtl,data/full_repos/permissive/173059417/RESET_DE.sv\n             RESET_DE\n             RESET_DE.v\n             RESET_DE.sv\n             obj_dir/RESET_DE\n             obj_dir/RESET_DE.v\n             obj_dir/RESET_DE.sv\n%Error: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:333: Cannot find file containing module: \'VGA_Audio_PLL\'\nVGA_Audio_PLL  VGA_AUDIO_PLL(.inclk0(CLK27MHZ),.c0(),.c1(AUD_CTRL_CLK));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:503: Cannot find file containing module: \'tv80s\'\ntv80s Z80CPU (\n^~~~~\n%Error: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:588: Cannot find file containing module: \'sys_rom_altera\'\nsys_rom_altera sys_rom(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:606: Cannot find file containing module: \'ram_4k_altera\'\nram_4k_altera sys_ram_2(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:874: Cannot find file containing module: \'Z80PIO\'\nZ80PIO Z80PIO_IF(\n^~~~~~\n%Error: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:901: Cannot find file containing module: \'Z80CTC\'\nZ80CTC Z80CTC_IF(\n^~~~~~\n%Error: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:941: Cannot find file containing module: \'ps2_keyboard\'\nps2_keyboard KEYBOARD(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:956: Cannot find file containing module: \'AUDIO_IF\'\nAUDIO_IF AUD_IF(\n^~~~~~~~\n%Error: data/full_repos/permissive/173059417/rtl/TP801_TOP.v:974: Cannot find file containing module: \'I2C_AV_Config\'\nI2C_AV_Config AUD_I2C(\n^~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s), 15 warning(s)\n'
module TP801_TOP(
	CLK50MHZ,

`ifdef CLOCK_27MHZ
	CLK27MHZ,
`endif


	HEX0_D,
	HEX1_D,
	HEX2_D,
	HEX3_D,
	HEX4_D,
	HEX5_D,
	HEX6_D,
	HEX7_D,


	PS2_KBCLK,
	PS2_KBDAT,

	LED,

`ifdef AUDIO_WM8731

	AUD_ADCLRCK,
	AUD_ADCDAT,
	AUD_DACLRCK,
	AUD_DACDAT,
	AUD_BCLK,
	AUD_XCK,


	I2C_SDAT,
	I2C_SCLK,

`endif

`ifdef GPIO_PIN



`endif

	BUTTON_N
);


input				CLK50MHZ;

`ifdef CLOCK_27MHZ
input				CLK27MHZ;
`endif



output	[6:0]	HEX0_D;
output	[6:0]	HEX1_D;
output	[6:0]	HEX2_D;
output	[6:0]	HEX3_D;
output	[6:0]	HEX4_D;
output	[6:0]	HEX5_D;
output	[6:0]	HEX6_D;
output	[6:0]	HEX7_D;


input 			PS2_KBCLK;
input			PS2_KBDAT;


output	wire	[9:0]	LED;


`ifdef AUDIO_WM8731



inout			AUD_ADCLRCK;
input			AUD_ADCDAT;


inout			AUD_DACLRCK;
output	wire	AUD_DACDAT;

inout			AUD_BCLK;
output	wire	AUD_XCK;


inout			I2C_SDAT;
output			I2C_SCLK;

`endif


input	[3:0]		BUTTON_N;
wire	[3:0]		BUTTON;
assign	BUTTON	=	~BUTTON_N;


`ifdef GPIO_PIN





`endif


wire				BASE_CLK = CLK50MHZ;

reg		[4:0]		CLK;

reg					MEM_OP_WR;



reg					CPU_CLK;
(*keep*)wire	[15:0]		CPU_A;
(*keep*)wire	[7:0]		CPU_DI;
(*keep*)wire	[7:0]		CPU_DO;

wire				CPU_RESET;
wire				CPU_HALT;
wire				CPU_WAIT;

wire				CPU_MREQ;
wire				CPU_RD;
wire				CPU_WR;
wire				CPU_IORQ;

reg					CPU_INT;
wire				CPU_NMI;
wire				CPU_M1;


wire				CPU_BUSRQ;
wire				CPU_BUSAK;

wire				CPU_RFSH;

`ifdef NEXTZ80

wire				CPU_RESET_N;
wire				CPU_HALT_N;
wire				CPU_WAIT_N;

wire				CPU_MREQ_N;
wire				CPU_RD_N;
wire				CPU_WR_N;
wire				CPU_IORQ_N;

wire				CPU_INT_N;
wire				CPU_NMI_N;
wire				CPU_M1_N;

wire				CPU_BUSRQ_N;
wire				CPU_BUSAK_N;

wire				CPU_RFSH_N;

`endif



wire	[7:0]		SYS_ROM_DATA;

wire	[7:0]		PROM1_DATA;
wire	[7:0]		PROM2_DATA;

wire				RAM_2_WR;
wire	[7:0]		RAM_2_DATA_OUT;

wire				ADDRESS_ROM;
wire				ADDRESS_PROM1;
wire				ADDRESS_PROM2;
wire				ADDRESS_2;

wire				ADDRESS_IO_PIO;
wire				ADDRESS_IO_CTC;

wire				ADDRESS_IO_PIO_N;
wire				ADDRESS_IO_CTC_N;

wire				ADDRESS_IO_SEG;
wire				ADDRESS_IO_DIGT;
wire				ADDRESS_IO_KB;


wire	[7:0]		Z80PIO_DATA_OUT;
wire	[7:0]		Z80CTC_DATA_OUT;


reg		[7:0]		LATCHED_IO_SEG;
reg		[7:0]		LATCHED_IO_DIGT;


reg		[4:0]		KB_CLK;

wire	[7:0]		SCAN;
wire				PRESS;
wire				PRESS_N;
wire				EXTENDED;

reg		[29:0]		KEY;
reg		[9:0]		KEY_EX;
reg		[11:0]		KEY_Fxx;
wire	[7:0]		KB_DATA;



(*keep*)wire				A_KEY_PRESSED;



wire	[1:0]		CASS_OUT;
wire				CASS_IN;
wire				CASS_IN_L;
wire				CASS_IN_R;




wire				SYS_RESET_N;
wire				RESET_N;
wire				RESET_AHEAD_N;

reg		[16:0]		RESET_KEY_COUNT;
wire				RESET_KEY_N;







assign	I2C_SDAT	=	1'bz;
assign	AUD_ADCLRCK	=	1'bz;
assign	AUD_DACLRCK	=	1'bz;
assign	AUD_BCLK	=	1'bz;




assign SYS_RESET_N = !BUTTON[0];

RESET_DE RESET_DE(
	.CLK(CLK50MHZ),
	.SYS_RESET_N(SYS_RESET_N && RESET_KEY_N),
	.RESET_N(RESET_N),
	.RESET_AHEAD_N(RESET_AHEAD_N)
);



assign RESET_KEY_N = RESET_KEY_COUNT[16];


`ifdef SIMULATE
initial
	begin
		CLK = 5'b0;
	end
`endif


`ifdef CLOCK_27MHZ

VGA_Audio_PLL  VGA_AUDIO_PLL(.inclk0(CLK27MHZ),.c0(),.c1(AUD_CTRL_CLK));

`endif














`ifdef SIMULATE
initial
	begin
		CLK = 5'b0;
	end
`endif

always @(posedge BASE_CLK or negedge RESET_N)
	if(~RESET_N)
	begin
		CPU_CLK					<=	1'b0;

		MEM_OP_WR				<=	1'b0;

		LATCHED_IO_SEG			<=	8'b0;
		LATCHED_IO_DIGT			<=	8'b0;

		CLK						<=	5'd0;
	end
	else
	begin
		case (CLK[4:0])
		5'd0:
			begin

				CPU_CLK				<=	1'b1;

				MEM_OP_WR			<=	1'b1;

				CLK					<=	5'd1;
			end

		5'd1:
			begin

				CPU_CLK				<=	1'b0;
				MEM_OP_WR			<=	1'b0;

				if({CPU_IORQ,CPU_RD,CPU_WR,ADDRESS_IO_SEG}==4'b1011)
					LATCHED_IO_SEG		<=	CPU_DO;

				if({CPU_IORQ,CPU_RD,CPU_WR,ADDRESS_IO_DIGT}==4'b1011)
					LATCHED_IO_DIGT		<=	CPU_DO;

				CLK					<=	5'd2;
			end

		5'd2:
			begin

				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	5'd3;
			end


		5'd7:
			begin
				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	5'd8;
			end


		5'd24:
			begin
				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	5'd0;
			end
		default:
			begin
				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	CLK + 1'b1;
			end
		endcase
	end





wire [7:0] InPort;

assign	InPort	=	(ADDRESS_IO_KB)		?	KB_DATA			:
					(ADDRESS_IO_PIO)	?	Z80PIO_DATA_OUT	:
					(ADDRESS_IO_CTC)	?	Z80CTC_DATA_OUT	:
											8'hFF			;



`ifdef NEXTZ80



NextZ80 Z80CPU (
	.DI(CPU_IORQ ? (CPU_M1 ? 8'b00000000 : InPort) : CPU_DI),
	.DO(CPU_DO),
	.ADDR(CPU_A),
	.WR(CPU_WR),
	.MREQ(CPU_MREQ),
	.IORQ(CPU_IORQ),
	.HALT(CPU_HALT),
	.CLK(CPU_CLK),
	.RESET(CPU_RESET),
	.INT(CPU_INT),
	.NMI(CPU_NMI),
	.WAIT(CPU_WAIT),
	.M1(CPU_M1)
);

`endif


`ifdef TV80

assign CPU_M1 = ~CPU_M1_N;
assign CPU_MREQ = ~CPU_MREQ_N;
assign CPU_IORQ = ~CPU_IORQ_N;
assign CPU_RD = ~CPU_RD_N;
assign CPU_WR = ~CPU_WR_N;
assign CPU_RFSH = ~CPU_RFSH_N;
assign CPU_HALT= ~CPU_HALT_N;
assign CPU_BUSAK = ~CPU_BUSAK_N;

assign CPU_RESET_N = ~CPU_RESET;
assign CPU_WAIT_N = ~CPU_WAIT;
assign CPU_INT_N = ~CPU_INT;

assign CPU_NMI_N = ~CPU_NMI;
assign CPU_BUSRQ_N = ~CPU_BUSRQ;



tv80s Z80CPU (
	.m1_n(CPU_M1_N),
	.mreq_n(CPU_MREQ_N),
	.iorq_n(CPU_IORQ_N),
	.rd_n(CPU_RD_N),
	.wr_n(CPU_WR_N),
	.rfsh_n(CPU_RFSH_N),
	.halt_n(CPU_HALT_N),
	.busak_n(CPU_BUSAK_N),
	.A(CPU_A),
	.dout(CPU_DO),
	.reset_n(CPU_RESET_N),
	.clk(CPU_CLK),
	.wait_n(CPU_WAIT_N),
	.int_n(CPU_INT_N),
	.nmi_n(CPU_NMI_N),
	.busrq_n(CPU_BUSRQ_N),
	.di(CPU_IORQ_N ? CPU_DI : (CPU_M1_N ? InPort: 8'b0000_0000))
);

`endif

assign CPU_RESET = ~RESET_N;

assign CPU_NMI = 1'b0;


assign CPU_WAIT = 1'b0;









assign ADDRESS_ROM			=	(CPU_A[15:11] == 5'b00000)?1'b1:1'b0;
assign ADDRESS_PROM1		=	(CPU_A[15:11] == 5'b00001)?1'b1:1'b0;
assign ADDRESS_PROM2		=	(CPU_A[15:11] == 5'b00010)?1'b1:1'b0;


assign ADDRESS_RAM_2		=	(CPU_A[15:12] == 4'h2)?1'b1:1'b0;


assign ADDRESS_IO_PIO		=	(CPU_A[7:2] == 6'b1000_00)?1'b1:1'b0;
assign ADDRESS_IO_PIO_N		=	(CPU_A[7:2] == 6'b1000_00)?1'b0:1'b1;


assign ADDRESS_IO_CTC		=	(CPU_A[7:2] == 6'b1000_01)?1'b1:1'b0;
assign ADDRESS_IO_CTC_N		=	(CPU_A[7:2] == 6'b1000_01)?1'b0:1'b1;


assign ADDRESS_IO_SEG		=	(CPU_A[7:2] == 6'b1000_10)?1'b1:1'b0;


assign ADDRESS_IO_DIGT		=	(CPU_A[7:2] == 6'b1000_11)?1'b1:1'b0;


assign ADDRESS_IO_KB		=	(CPU_A[7:2] == 6'b1001_00)?1'b1:1'b0;



assign RAM_2_WR			= ({ADDRESS_RAM_2,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;


`ifdef	RAM_ON_FPGA

assign CPU_DI = 	ADDRESS_ROM			? SYS_ROM_DATA		:
					ADDRESS_PROM1		? PROM1_DATA		:
					ADDRESS_PROM2		? PROM2_DATA		:
					ADDRESS_RAM_2		? RAM_2_DATA_OUT	:
					8'hzz;

`endif


assign	PROM1_DATA	= 8'bz;
assign	PROM2_DATA	= 8'bz;


`ifdef BASE_SYS_ROM

`ifdef FPGA_ALTERA

sys_rom_altera sys_rom(
	.address(CPU_A[10:0]),
	.clock(BASE_CLK),
	.q(SYS_ROM_DATA)
);

`endif

`endif


`ifdef	RAM_ON_FPGA


`ifdef BASE_RAM_4K

`ifdef FPGA_ALTERA

ram_4k_altera sys_ram_2(
	.address(CPU_A[10:0]),
	.clock(BASE_CLK),
	.data(CPU_DO),
	.wren(CPU_MREQ & RAM_2_WR),
	.q(RAM_2_DATA_OUT)
);

`endif

`endif

`endif

























assign HEX0_D	= LATCHED_IO_DIGT[0]?	LATCHED_IO_SEG[6:0]	:	7'b111_1111;
assign HEX1_D	= LATCHED_IO_DIGT[1]?	LATCHED_IO_SEG[6:0]	:	7'b111_1111;
assign HEX2_D	= LATCHED_IO_DIGT[2]?	LATCHED_IO_SEG[6:0]	:	7'b111_1111;
assign HEX3_D	= LATCHED_IO_DIGT[3]?	LATCHED_IO_SEG[6:0]	:	7'b111_1111;
assign HEX4_D	= LATCHED_IO_DIGT[4]?	LATCHED_IO_SEG[6:0]	:	7'b111_1111;
assign HEX5_D	= LATCHED_IO_DIGT[5]?	LATCHED_IO_SEG[6:0]	:	7'b111_1111;

assign HEX6_D	= 7'b111_1111;
assign HEX7_D	= 7'b111_1111;


























wire	[29:0]	KEY_SEL		=	KEY|(~{5{LATCHED_IO_DIGT[5:0]}});

wire KB_DATA_BIT7 = 1'b1;
wire KB_DATA_BIT6 = 1'b1;
wire KB_DATA_BIT5 = 1'b1;
wire KB_DATA_BIT4 = (KEY_SEL[29:24]==6'b11_1111);
wire KB_DATA_BIT3 = (KEY_SEL[23:18]==6'b11_1111);
wire KB_DATA_BIT2 = (KEY_SEL[17:12]==6'b11_1111);
wire KB_DATA_BIT1 = (KEY_SEL[11: 6]==6'b11_1111);
wire KB_DATA_BIT0 = (KEY_SEL[ 5: 0]==6'b11_1111);






assign KB_DATA = { KB_DATA_BIT7, KB_DATA_BIT6, KB_DATA_BIT5, KB_DATA_BIT4, KB_DATA_BIT3, KB_DATA_BIT2, KB_DATA_BIT1, KB_DATA_BIT0 };

assign A_KEY_PRESSED = (KEY[29:0] == 30'h3FFF_FFFF) ? 1'b0:1'b1;

always @(posedge KB_CLK[3] or negedge SYS_RESET_N)
begin
	if(~SYS_RESET_N)
	begin
		KEY					<=	30'h3FFF_FFFF;
		KEY_EX				<=	10'h3FF;
		KEY_Fxx				<=	12'h000;

		RESET_KEY_COUNT		<=	17'h1FFFF;
	end
	else
	begin

		if(RESET_KEY_COUNT[16]==1'b0)
			RESET_KEY_COUNT <= RESET_KEY_COUNT+1;

		case(SCAN)
		8'h07:
		begin
			KEY_Fxx[11]	<= PRESS;
				if(PRESS && (KEY_EX[0]==PRESS_N))
				begin
					RESET_KEY_COUNT		<=	17'h0;
				end
		end












		8'h16:	KEY[25] <= PRESS_N;
		8'h1E:	KEY[19] <= PRESS_N;
		8'h26:	KEY[13] <= PRESS_N;
		8'h25:	KEY[26] <= PRESS_N;
		8'h2E:	KEY[20] <= PRESS_N;
		8'h36:	KEY[14] <= PRESS_N;
		8'h3D:	KEY[27] <= PRESS_N;
		8'h3E:	KEY[21] <= PRESS_N;
		8'h46:	KEY[15] <= PRESS_N;
		8'h45:	KEY[24] <= PRESS_N;
		8'h1C:	KEY[ 9] <= PRESS_N;
		8'h32:	KEY[ 8] <= PRESS_N;
		8'h21:	KEY[ 7] <= PRESS_N;
		8'h23:	KEY[ 6] <= PRESS_N;
		8'h24:	KEY[12] <= PRESS_N;
		8'h2B:	KEY[18] <= PRESS_N;
		8'h42:	KEY[28] <= PRESS_N;
		8'h4b:	KEY[22] <= PRESS_N;
		8'h3a:	KEY[ 2] <= PRESS_N;
		8'h31:	KEY[ 3] <= PRESS_N;
		8'h4D:	KEY[29] <= PRESS_N;

		8'h54:	KEY[23] <= PRESS_N;
		8'h5B:	KEY[17] <= PRESS_N;
		8'h5D:	KEY[11] <= PRESS_N;

		8'h4C:	KEY[16] <= PRESS_N;
		8'h52:	KEY[10] <= PRESS_N;

		8'h41:	KEY[ 1] <= PRESS_N;
		8'h49:	KEY[ 0] <= PRESS_N;




























		8'h14:	KEY_EX[0] <= PRESS_N;
		8'h12:	KEY_EX[1] <= PRESS_N;
		8'h59:	KEY_EX[2] <= PRESS_N;
		8'h11:
		begin
			if(~EXTENDED)
					KEY_EX[3] <= PRESS_N;
			else
					KEY_EX[4] <= PRESS_N;
		end
		8'h75:	KEY_EX[5] <= PRESS_N;
		8'h6B:	KEY_EX[6] <= PRESS_N;
		8'h74:	KEY_EX[7] <= PRESS_N;
		8'h72:	KEY_EX[8] <= PRESS_N;
		endcase
	end
end


wire	PIO_IEI, PIO_IEO;

Z80PIO Z80PIO_IF(
	CPU_CLK,
	PA,
	PB,

	CPU_DO,
	Z80PIO_DATA_OUT,
	CPU_A[1],
	CPU_A[0],
	CPU_M1_N,
	CPU_IORQ_N,
	RD_N,
	PIO_IEI,
	PIO_IEO,
	INT_N,
	ASTB_N,
	BSTB_N,
	ARDY,
	BRDY,
	ADDRESS_IO_PIO_N,
	CPU_RESET_N
);


wire	CTC_IEI, CTC_IEO;
wire	ZCTO0, ZCTO1, ZCTO2;

Z80CTC Z80CTC_IF(
	CPU_CLK,

	CPU_DO,
	Z80CTC_DATA_OUT,
	CPU_M1_N,
	CPU_IORQ_N,
	CPU_RD_N,
	CTC_IEI,
	CTC_IEO,
	INT_N,
	CPU_A[0],
	CPU_A[1],
	TRG0,
	TRG1,
	TRG2,
	TRG3,
	ZCTO0,
	ZCTO1,
	ZCTO2,
	ADDRESS_IO_CTC_N,
	CPU_RESET_N
);


assign	CTC_IEI		=	1'b1;
assign	PIO_IEI		=	CTC_IEO;
assign	CASS_OUT	=	{1'b0,ZCTO1};


`ifdef SIMULATE
initial
	begin
		KB_CLK = 5'b0;
	end
`endif

always @ (posedge CLK50MHZ)
	KB_CLK <= KB_CLK + 1'b1;

ps2_keyboard KEYBOARD(
		.RESET_N(RESET_N),
		.CLK(KB_CLK[4]),
		.PS2_CLK(PS2_KBCLK),
		.PS2_DATA(PS2_KBDAT),
		.RX_SCAN(SCAN),
		.RX_PRESSED(PRESS),
		.RX_EXTENDED(EXTENDED)
);

assign PRESS_N = ~PRESS;


`ifdef AUDIO_WM8731

AUDIO_IF AUD_IF(

	.oAUD_BCLK(AUD_BCLK),
	.oAUD_DACLRCK(AUD_DACLRCK),
	.oAUD_DACDAT(AUD_DACDAT),
	.oAUD_ADCLRCK(AUD_ADCLRCK),
	.iAUD_ADCDAT(AUD_ADCDAT),

	.iSPK_A(SPEAKER_A),
	.iSPK_B(SPEAKER_B),
	.iCASS_OUT(CASS_OUT),
	.oCASS_IN_L(CASS_IN_L),
	.oCASS_IN_R(CASS_IN_R),

	.iCLK_18_4(AUD_CTRL_CLK),
	.iRST_N(RESET_N)
);

I2C_AV_Config AUD_I2C(

	.iCLK(CLK50MHZ),
	.iRST_N(RESET_N),

	.I2C_SCLK(I2C_SCLK),
	.I2C_SDAT(I2C_SDAT)
);

assign	AUD_XCK = AUD_CTRL_CLK;

`endif


`ifdef AUDIO_WM8731
assign	CASS_IN			=	CASS_IN_L;
`endif


`ifdef GPIO_PIN


`endif





(*keep*)wire trap = CPU_IORQ && (CPU_WR||CPU_RD) && ADDRESS_IO_CTC && (CPU_A[1:0]==2'b01);


assign LED = {4'b0, trap, CASS_IN, CASS_OUT[0], A_KEY_PRESSED, CPU_CLK, CPU_RESET};

endmodule
module TP801_TOP(
	CLK50MHZ,

`ifdef CLOCK_27MHZ
	CLK27MHZ,
`endif


	HEX0_D,
	HEX1_D,
	HEX2_D,
	HEX3_D,
	HEX4_D,
	HEX5_D,
	HEX6_D,
	HEX7_D,


	PS2_KBCLK,
	PS2_KBDAT,

	LED,

`ifdef AUDIO_WM8731

	AUD_ADCLRCK,
	AUD_ADCDAT,
	AUD_DACLRCK,
	AUD_DACDAT,
	AUD_BCLK,
	AUD_XCK,


	I2C_SDAT,
	I2C_SCLK,

`endif

`ifdef GPIO_PIN



`endif

	BUTTON_N
);



input				CLK50MHZ;

`ifdef CLOCK_27MHZ
input				CLK27MHZ;
`endif



output	[6:0]	HEX0_D;
output	[6:0]	HEX1_D;
output	[6:0]	HEX2_D;
output	[6:0]	HEX3_D;
output	[6:0]	HEX4_D;
output	[6:0]	HEX5_D;
output	[6:0]	HEX6_D;
output	[6:0]	HEX7_D;


input 			PS2_KBCLK;
input			PS2_KBDAT;


output	wire	[9:0]	LED;


`ifdef AUDIO_WM8731



inout			AUD_ADCLRCK;
input			AUD_ADCDAT;


inout			AUD_DACLRCK;
output	wire	AUD_DACDAT;

inout			AUD_BCLK;
output	wire	AUD_XCK;


inout			I2C_SDAT;
output			I2C_SCLK;

`endif


input	[3:0]		BUTTON_N;
wire	[3:0]		BUTTON;
assign	BUTTON	=	~BUTTON_N;


`ifdef GPIO_PIN





`endif


wire				BASE_CLK = CLK50MHZ;

reg		[4:0]		CLK;

reg					MEM_OP_WR;



reg					CPU_CLK;
(*keep*)wire	[15:0]		CPU_A;
(*keep*)wire	[7:0]		CPU_DI;
(*keep*)wire	[7:0]		CPU_DO;

wire				CPU_RESET;
wire				CPU_HALT;
wire				CPU_WAIT;

wire				CPU_MREQ;
wire				CPU_RD;
wire				CPU_WR;
wire				CPU_IORQ;

reg					CPU_INT;
wire				CPU_NMI;
wire				CPU_M1;


wire				CPU_BUSRQ;
wire				CPU_BUSAK;

wire				CPU_RFSH;

`ifdef NEXTZ80

wire				CPU_RESET_N;
wire				CPU_HALT_N;
wire				CPU_WAIT_N;

wire				CPU_MREQ_N;
wire				CPU_RD_N;
wire				CPU_WR_N;
wire				CPU_IORQ_N;

wire				CPU_INT_N;
wire				CPU_NMI_N;
wire				CPU_M1_N;

wire				CPU_BUSRQ_N;
wire				CPU_BUSAK_N;

wire				CPU_RFSH_N;

`endif



wire	[7:0]		SYS_ROM_DATA;

wire	[7:0]		PROM1_DATA;
wire	[7:0]		PROM2_DATA;

wire				RAM_2_WR;
wire	[7:0]		RAM_2_DATA_OUT;

wire				ADDRESS_ROM;
wire				ADDRESS_PROM1;
wire				ADDRESS_PROM2;
wire				ADDRESS_2;

wire				ADDRESS_IO_PIO;
wire				ADDRESS_IO_CTC;

wire				ADDRESS_IO_PIO_N;
wire				ADDRESS_IO_CTC_N;

wire				ADDRESS_IO_SEG;
wire				ADDRESS_IO_DIGT;
wire				ADDRESS_IO_KB;


wire	[7:0]		Z80PIO_DATA_OUT;
wire	[7:0]		Z80CTC_DATA_OUT;


reg		[7:0]		LATCHED_IO_SEG;
reg		[7:0]		LATCHED_IO_DIGT;


reg		[4:0]		KB_CLK;

wire	[7:0]		SCAN;
wire				PRESS;
wire				PRESS_N;
wire				EXTENDED;

reg		[29:0]		KEY;
reg		[9:0]		KEY_EX;
reg		[11:0]		KEY_Fxx;
wire	[7:0]		KB_DATA;



(*keep*)wire				A_KEY_PRESSED;



wire	[1:0]		CASS_OUT;
wire				CASS_IN;
wire				CASS_IN_L;
wire				CASS_IN_R;




wire				SYS_RESET_N;
wire				RESET_N;
wire				RESET_AHEAD_N;

reg		[16:0]		RESET_KEY_COUNT;
wire				RESET_KEY_N;







assign	I2C_SDAT	=	1'bz;
assign	AUD_ADCLRCK	=	1'bz;
assign	AUD_DACLRCK	=	1'bz;
assign	AUD_BCLK	=	1'bz;




assign SYS_RESET_N = !BUTTON[0];

RESET_DE RESET_DE(
	.CLK(CLK50MHZ),
	.SYS_RESET_N(SYS_RESET_N && RESET_KEY_N),
	.RESET_N(RESET_N),
	.RESET_AHEAD_N(RESET_AHEAD_N)
);



assign RESET_KEY_N = RESET_KEY_COUNT[16];


`ifdef SIMULATE
initial
	begin
		CLK = 5'b0;
	end
`endif


`ifdef CLOCK_27MHZ

VGA_Audio_PLL  VGA_AUDIO_PLL(.inclk0(CLK27MHZ),.c0(),.c1(AUD_CTRL_CLK));

`endif














`ifdef SIMULATE
initial
	begin
		CLK = 5'b0;
	end
`endif

always @(posedge BASE_CLK or negedge RESET_N)
	if(~RESET_N)
	begin
		CPU_CLK					<=	1'b0;

		MEM_OP_WR				<=	1'b0;

		LATCHED_IO_SEG			<=	8'b0;
		LATCHED_IO_DIGT			<=	8'b0;

		CLK						<=	5'd0;
	end
	else
	begin
		case (CLK[4:0])
		5'd0:
			begin

				CPU_CLK				<=	1'b1;

				MEM_OP_WR			<=	1'b1;

				CLK					<=	5'd1;
			end

		5'd1:
			begin

				CPU_CLK				<=	1'b0;
				MEM_OP_WR			<=	1'b0;

				if({CPU_IORQ,CPU_RD,CPU_WR,ADDRESS_IO_SEG}==4'b1011)
					LATCHED_IO_SEG		<=	CPU_DO;

				if({CPU_IORQ,CPU_RD,CPU_WR,ADDRESS_IO_DIGT}==4'b1011)
					LATCHED_IO_DIGT		<=	CPU_DO;

				CLK					<=	5'd2;
			end

		5'd2:
			begin

				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	5'd3;
			end


		5'd7:
			begin
				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	5'd8;
			end


		5'd24:
			begin
				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	5'd0;
			end
		default:
			begin
				CPU_CLK				<=	1'b0;

				MEM_OP_WR			<=	1'b0;

				CLK					<=	CLK + 1'b1;
			end
		endcase
	end





wire [7:0] InPort;

assign	InPort	=	(ADDRESS_IO_KB)		?	KB_DATA			:
					(ADDRESS_IO_PIO)	?	Z80PIO_DATA_OUT	:
					(ADDRESS_IO_CTC)	?	Z80CTC_DATA_OUT	:
											8'hFF			;



`ifdef NEXTZ80



NextZ80 Z80CPU (
	.DI(CPU_IORQ ? (CPU_M1 ? 8'b00000000 : InPort) : CPU_DI),
	.DO(CPU_DO),
	.ADDR(CPU_A),
	.WR(CPU_WR),
	.MREQ(CPU_MREQ),
	.IORQ(CPU_IORQ),
	.HALT(CPU_HALT),
	.CLK(CPU_CLK),
	.RESET(CPU_RESET),
	.INT(CPU_INT),
	.NMI(CPU_NMI),
	.WAIT(CPU_WAIT),
	.M1(CPU_M1)
);

`endif


`ifdef TV80

assign CPU_M1 = ~CPU_M1_N;
assign CPU_MREQ = ~CPU_MREQ_N;
assign CPU_IORQ = ~CPU_IORQ_N;
assign CPU_RD = ~CPU_RD_N;
assign CPU_WR = ~CPU_WR_N;
assign CPU_RFSH = ~CPU_RFSH_N;
assign CPU_HALT= ~CPU_HALT_N;
assign CPU_BUSAK = ~CPU_BUSAK_N;

assign CPU_RESET_N = ~CPU_RESET;
assign CPU_WAIT_N = ~CPU_WAIT;
assign CPU_INT_N = ~CPU_INT;

assign CPU_NMI_N = ~CPU_NMI;
assign CPU_BUSRQ_N = ~CPU_BUSRQ;



tv80s Z80CPU (
	.m1_n(CPU_M1_N),
	.mreq_n(CPU_MREQ_N),
	.iorq_n(CPU_IORQ_N),
	.rd_n(CPU_RD_N),
	.wr_n(CPU_WR_N),
	.rfsh_n(CPU_RFSH_N),
	.halt_n(CPU_HALT_N),
	.busak_n(CPU_BUSAK_N),
	.A(CPU_A),
	.dout(CPU_DO),
	.reset_n(CPU_RESET_N),
	.clk(CPU_CLK),
	.wait_n(CPU_WAIT_N),
	.int_n(CPU_INT_N),
	.nmi_n(CPU_NMI_N),
	.busrq_n(CPU_BUSRQ_N),
	.di(CPU_IORQ_N ? CPU_DI : (CPU_M1_N ? InPort: 8'b0000_0000))
);

`endif

assign CPU_RESET = ~RESET_N;

assign CPU_NMI = 1'b0;


assign CPU_WAIT = 1'b0;









assign ADDRESS_ROM			=	(CPU_A[15:11] == 5'b00000)?1'b1:1'b0;
assign ADDRESS_PROM1		=	(CPU_A[15:11] == 5'b00001)?1'b1:1'b0;
assign ADDRESS_PROM2		=	(CPU_A[15:11] == 5'b00010)?1'b1:1'b0;


assign ADDRESS_RAM_2		=	(CPU_A[15:12] == 4'h2)?1'b1:1'b0;


assign ADDRESS_IO_PIO		=	(CPU_A[7:2] == 6'b1000_00)?1'b1:1'b0;
assign ADDRESS_IO_PIO_N		=	(CPU_A[7:2] == 6'b1000_00)?1'b0:1'b1;


assign ADDRESS_IO_CTC		=	(CPU_A[7:2] == 6'b1000_01)?1'b1:1'b0;
assign ADDRESS_IO_CTC_N		=	(CPU_A[7:2] == 6'b1000_01)?1'b0:1'b1;


assign ADDRESS_IO_SEG		=	(CPU_A[7:2] == 6'b1000_10)?1'b1:1'b0;


assign ADDRESS_IO_DIGT		=	(CPU_A[7:2] == 6'b1000_11)?1'b1:1'b0;


assign ADDRESS_IO_KB		=	(CPU_A[7:2] == 6'b1001_00)?1'b1:1'b0;



assign RAM_2_WR			= ({ADDRESS_RAM_2,MEM_OP_WR,CPU_WR,CPU_IORQ} == 4'b1110)?1'b1:1'b0;


`ifdef	RAM_ON_FPGA

assign CPU_DI = 	ADDRESS_ROM			? SYS_ROM_DATA		:
					ADDRESS_PROM1		? PROM1_DATA		:
					ADDRESS_PROM2		? PROM2_DATA		:
					ADDRESS_RAM_2		? RAM_2_DATA_OUT	:
					8'hzz;

`endif


assign	PROM1_DATA	= 8'bz;
assign	PROM2_DATA	= 8'bz;


`ifdef BASE_SYS_ROM

`ifdef FPGA_ALTERA

sys_rom_altera sys_rom(
	.address(CPU_A[10:0]),
	.clock(BASE_CLK),
	.q(SYS_ROM_DATA)
);

`endif

`endif


`ifdef	RAM_ON_FPGA


`ifdef BASE_RAM_4K

`ifdef FPGA_ALTERA

ram_4k_altera sys_ram_2(
	.address(CPU_A[10:0]),
	.clock(BASE_CLK),
	.data(CPU_DO),
	.wren(CPU_MREQ & RAM_2_WR),
	.q(RAM_2_DATA_OUT)
);

`endif

`endif

`endif

























assign HEX0_D	= LATCHED_IO_DIGT[0]?	LATCHED_IO_SEG[6:0]	:	7'b111_1111;
assign HEX1_D	= LATCHED_IO_DIGT[1]?	LATCHED_IO_SEG[6:0]	:	7'b111_1111;
assign HEX2_D	= LATCHED_IO_DIGT[2]?	LATCHED_IO_SEG[6:0]	:	7'b111_1111;
assign HEX3_D	= LATCHED_IO_DIGT[3]?	LATCHED_IO_SEG[6:0]	:	7'b111_1111;
assign HEX4_D	= LATCHED_IO_DIGT[4]?	LATCHED_IO_SEG[6:0]	:	7'b111_1111;
assign HEX5_D	= LATCHED_IO_DIGT[5]?	LATCHED_IO_SEG[6:0]	:	7'b111_1111;

assign HEX6_D	= 7'b111_1111;
assign HEX7_D	= 7'b111_1111;


























wire	[29:0]	KEY_SEL		=	KEY|(~{5{LATCHED_IO_DIGT[5:0]}});

wire KB_DATA_BIT7 = 1'b1;
wire KB_DATA_BIT6 = 1'b1;
wire KB_DATA_BIT5 = 1'b1;
wire KB_DATA_BIT4 = (KEY_SEL[29:24]==6'b11_1111);
wire KB_DATA_BIT3 = (KEY_SEL[23:18]==6'b11_1111);
wire KB_DATA_BIT2 = (KEY_SEL[17:12]==6'b11_1111);
wire KB_DATA_BIT1 = (KEY_SEL[11: 6]==6'b11_1111);
wire KB_DATA_BIT0 = (KEY_SEL[ 5: 0]==6'b11_1111);






assign KB_DATA = { KB_DATA_BIT7, KB_DATA_BIT6, KB_DATA_BIT5, KB_DATA_BIT4, KB_DATA_BIT3, KB_DATA_BIT2, KB_DATA_BIT1, KB_DATA_BIT0 };

assign A_KEY_PRESSED = (KEY[29:0] == 30'h3FFF_FFFF) ? 1'b0:1'b1;

always @(posedge KB_CLK[3] or negedge SYS_RESET_N)
begin
	if(~SYS_RESET_N)
	begin
		KEY					<=	30'h3FFF_FFFF;
		KEY_EX				<=	10'h3FF;
		KEY_Fxx				<=	12'h000;

		RESET_KEY_COUNT		<=	17'h1FFFF;
	end
	else
	begin

		if(RESET_KEY_COUNT[16]==1'b0)
			RESET_KEY_COUNT <= RESET_KEY_COUNT+1;

		case(SCAN)
		8'h07:
		begin
			KEY_Fxx[11]	<= PRESS;
				if(PRESS && (KEY_EX[0]==PRESS_N))
				begin
					RESET_KEY_COUNT		<=	17'h0;
				end
		end












		8'h16:	KEY[25] <= PRESS_N;
		8'h1E:	KEY[19] <= PRESS_N;
		8'h26:	KEY[13] <= PRESS_N;
		8'h25:	KEY[26] <= PRESS_N;
		8'h2E:	KEY[20] <= PRESS_N;
		8'h36:	KEY[14] <= PRESS_N;
		8'h3D:	KEY[27] <= PRESS_N;
		8'h3E:	KEY[21] <= PRESS_N;
		8'h46:	KEY[15] <= PRESS_N;
		8'h45:	KEY[24] <= PRESS_N;
		8'h1C:	KEY[ 9] <= PRESS_N;
		8'h32:	KEY[ 8] <= PRESS_N;
		8'h21:	KEY[ 7] <= PRESS_N;
		8'h23:	KEY[ 6] <= PRESS_N;
		8'h24:	KEY[12] <= PRESS_N;
		8'h2B:	KEY[18] <= PRESS_N;
		8'h42:	KEY[28] <= PRESS_N;
		8'h4b:	KEY[22] <= PRESS_N;
		8'h3a:	KEY[ 2] <= PRESS_N;
		8'h31:	KEY[ 3] <= PRESS_N;
		8'h4D:	KEY[29] <= PRESS_N;

		8'h54:	KEY[23] <= PRESS_N;
		8'h5B:	KEY[17] <= PRESS_N;
		8'h5D:	KEY[11] <= PRESS_N;

		8'h4C:	KEY[16] <= PRESS_N;
		8'h52:	KEY[10] <= PRESS_N;

		8'h41:	KEY[ 1] <= PRESS_N;
		8'h49:	KEY[ 0] <= PRESS_N;




























		8'h14:	KEY_EX[0] <= PRESS_N;
		8'h12:	KEY_EX[1] <= PRESS_N;
		8'h59:	KEY_EX[2] <= PRESS_N;
		8'h11:
		begin
			if(~EXTENDED)
					KEY_EX[3] <= PRESS_N;
			else
					KEY_EX[4] <= PRESS_N;
		end
		8'h75:	KEY_EX[5] <= PRESS_N;
		8'h6B:	KEY_EX[6] <= PRESS_N;
		8'h74:	KEY_EX[7] <= PRESS_N;
		8'h72:	KEY_EX[8] <= PRESS_N;
		endcase
	end
end


wire	PIO_IEI, PIO_IEO;

Z80PIO Z80PIO_IF(
	CPU_CLK,
	PA,
	PB,

	CPU_DO,
	Z80PIO_DATA_OUT,
	CPU_A[1],
	CPU_A[0],
	CPU_M1_N,
	CPU_IORQ_N,
	RD_N,
	PIO_IEI,
	PIO_IEO,
	INT_N,
	ASTB_N,
	BSTB_N,
	ARDY,
	BRDY,
	ADDRESS_IO_PIO_N,
	CPU_RESET_N
);


wire	CTC_IEI, CTC_IEO;
wire	ZCTO0, ZCTO1, ZCTO2;

Z80CTC Z80CTC_IF(
	CPU_CLK,

	CPU_DO,
	Z80CTC_DATA_OUT,
	CPU_M1_N,
	CPU_IORQ_N,
	CPU_RD_N,
	CTC_IEI,
	CTC_IEO,
	INT_N,
	CPU_A[0],
	CPU_A[1],
	TRG0,
	TRG1,
	TRG2,
	TRG3,
	ZCTO0,
	ZCTO1,
	ZCTO2,
	ADDRESS_IO_CTC_N,
	CPU_RESET_N
);


assign	CTC_IEI		=	1'b1;
assign	PIO_IEI		=	CTC_IEO;
assign	CASS_OUT	=	{1'b0,ZCTO1};


`ifdef SIMULATE
initial
	begin
		KB_CLK = 5'b0;
	end
`endif

always @ (posedge CLK50MHZ)
	KB_CLK <= KB_CLK + 1'b1;

ps2_keyboard KEYBOARD(
		.RESET_N(RESET_N),
		.CLK(KB_CLK[4]),
		.PS2_CLK(PS2_KBCLK),
		.PS2_DATA(PS2_KBDAT),
		.RX_SCAN(SCAN),
		.RX_PRESSED(PRESS),
		.RX_EXTENDED(EXTENDED)
);

assign PRESS_N = ~PRESS;


`ifdef AUDIO_WM8731

AUDIO_IF AUD_IF(

	.oAUD_BCLK(AUD_BCLK),
	.oAUD_DACLRCK(AUD_DACLRCK),
	.oAUD_DACDAT(AUD_DACDAT),
	.oAUD_ADCLRCK(AUD_ADCLRCK),
	.iAUD_ADCDAT(AUD_ADCDAT),

	.iSPK_A(SPEAKER_A),
	.iSPK_B(SPEAKER_B),
	.iCASS_OUT(CASS_OUT),
	.oCASS_IN_L(CASS_IN_L),
	.oCASS_IN_R(CASS_IN_R),

	.iCLK_18_4(AUD_CTRL_CLK),
	.iRST_N(RESET_N)
);

I2C_AV_Config AUD_I2C(

	.iCLK(CLK50MHZ),
	.iRST_N(RESET_N),

	.I2C_SCLK(I2C_SCLK),
	.I2C_SDAT(I2C_SDAT)
);

assign	AUD_XCK = AUD_CTRL_CLK;

`endif


`ifdef AUDIO_WM8731
assign	CASS_IN			=	CASS_IN_L;
`endif


`ifdef GPIO_PIN


`endif





(*keep*)wire trap = CPU_IORQ && (CPU_WR||CPU_RD) && ADDRESS_IO_CTC && (CPU_A[1:0]==2'b01);


assign LED = {4'b0, trap, CASS_IN, CASS_OUT[0], A_KEY_PRESSED, CPU_CLK, CPU_RESET};

endmodule