data/full_repos/permissive/141596082/voice_core/rtl/wb_dac/dac.v
1: b'%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_dac/dac.v:42: Operator SHIFTL expects 18 bits on the LHS, but LHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                   : ... In instance dac\n      delta = 2\'b11 << DATA_WIDTH;\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_dac/dac.v:59: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'dac_data\' generates 16 bits.\n                                                                                   : ... In instance dac\n  assign delta_add  = dac_data + delta;\n                               ^\n%Error: Exiting due to 2 warning(s)\n'
module dac #(parameter DATA_WIDTH = 16) (
  input                   clk        ,
  input                   resetn     ,
  input                   reset_sigma,
  input  [DATA_WIDTH-1:0] dac_data   ,
  input                   load_sigma ,
  inout                  dac_output
);

  wire [DATA_WIDTH+1:0] delta_add;
  wire [DATA_WIDTH+1:0] sigma_add;

  reg [DATA_WIDTH+1:0] sigma_reg;
  reg [DATA_WIDTH+1:0] delta    ;

  initial begin
    sigma_reg = 0;
  end

  always @(*) begin
    if(dac_output)
      delta = 2'b11 << DATA_WIDTH;
    else
      delta = 0;
  end

  always @(posedge clk or posedge resetn) begin
    if(resetn|reset_sigma) begin
      sigma_reg <= 0;
    end else begin
      if(load_sigma)
        sigma_reg <= sigma_add;
      else
        sigma_reg <= sigma_reg;
    end
  end

  assign dac_output = (reset_sigma) ? 1'bz : sigma_reg[DATA_WIDTH+1];
  assign delta_add  = dac_data + delta;
  assign sigma_add  = sigma_reg + delta_add;

endmodule
module dac #(parameter DATA_WIDTH = 16) (
  input                   clk        ,
  input                   resetn     ,
  input                   reset_sigma,
  input  [DATA_WIDTH-1:0] dac_data   ,
  input                   load_sigma ,
  inout                  dac_output
);


  wire [DATA_WIDTH+1:0] delta_add;
  wire [DATA_WIDTH+1:0] sigma_add;

  reg [DATA_WIDTH+1:0] sigma_reg;
  reg [DATA_WIDTH+1:0] delta    ;

  initial begin
    sigma_reg = 0;
  end

  always @(*) begin
    if(dac_output)
      delta = 2'b11 << DATA_WIDTH;
    else
      delta = 0;
  end

  always @(posedge clk or posedge resetn) begin
    if(resetn|reset_sigma) begin
      sigma_reg <= 0;
    end else begin
      if(load_sigma)
        sigma_reg <= sigma_add;
      else
        sigma_reg <= sigma_reg;
    end
  end

  assign dac_output = (reset_sigma) ? 1'bz : sigma_reg[DATA_WIDTH+1];
  assign delta_add  = dac_data + delta;
  assign sigma_add  = sigma_reg + delta_add;

endmodule