data/full_repos/permissive/135475029/lab_9/src/ALU.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/135475029/lab_9/src/ALU.v:49: Signal definition not found, creating implicitly: \'shiftout\'\n assign shiftout = b >> shAmt;\n        ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/135475029/lab_9/src/ALU.v:49: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                       : ... In instance ALU\n assign shiftout = b >> shAmt;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/135475029/lab_9/src/ALU.v:61: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                       : ... In instance ALU\n  assign addout = a + sel_b + aluop[1];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/135475029/lab_9/src/ALU.v:72: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'shiftout\' generates 1 bits.\n                                                                       : ... In instance ALU\n                  aluop[5:4] == 2\'b00 ? shiftout :\n                                      ^\n%Error: Exiting due to 4 warning(s)\n'
module ALU(
  input CLK,
  input RESET,
  input  [31:0] a,
  input  [31:0] b,
  input  [5:0] aluop,
  input  [4:0] shAmt,
  output [31:0] result,
  output zero
 );

  wire [31:0] logicout;
  wire [31:0] addout;
  wire [31:0] arithout;
  wire [31:0] n_b;
  wire [31:0] sel_b;
  wire [31:0] slt;

  wire [1:0] logicsel;


  assign logicsel = aluop[1:0];
  assign logicout = (logicsel == 2'b00) ? a & b :
                    (logicsel == 2'b01) ? a | b :
                    (logicsel == 2'b10) ? a ^ b :
                                        ~(a | b);


 assign shiftout = b >> shAmt;

 reg [31:0] Lo;

 always @(posedge CLK)
   if(aluop == 6'b011001)
        Lo <= a * b;



  assign n_b = ~b;
  assign sel_b = (aluop[1])? n_b : b;
  assign addout = a + sel_b + aluop[1];


  assign slt = { 31'b0,addout[31] };


  assign arithout = (aluop[3]) ? slt : addout;


  assign result = aluop == 6'b010010 ? Lo :
                  aluop[2] ? logicout :
                  aluop[5:4] == 2'b00 ? shiftout :
                  arithout;

  assign zero = (result == 32'b0) ? 1: 0;

endmodule
module ALU(
  input CLK,
  input RESET,
  input  [31:0] a,
  input  [31:0] b,
  input  [5:0] aluop,
  input  [4:0] shAmt,
  output [31:0] result,
  output zero
 );


  wire [31:0] logicout;
  wire [31:0] addout;
  wire [31:0] arithout;
  wire [31:0] n_b;
  wire [31:0] sel_b;
  wire [31:0] slt;

  wire [1:0] logicsel;


  assign logicsel = aluop[1:0];
  assign logicout = (logicsel == 2'b00) ? a & b :
                    (logicsel == 2'b01) ? a | b :
                    (logicsel == 2'b10) ? a ^ b :
                                        ~(a | b);


 assign shiftout = b >> shAmt;

 reg [31:0] Lo;

 always @(posedge CLK)
   if(aluop == 6'b011001)
        Lo <= a * b;



  assign n_b = ~b;
  assign sel_b = (aluop[1])? n_b : b;
  assign addout = a + sel_b + aluop[1];


  assign slt = { 31'b0,addout[31] };


  assign arithout = (aluop[3]) ? slt : addout;


  assign result = aluop == 6'b010010 ? Lo :
                  aluop[2] ? logicout :
                  aluop[5:4] == 2'b00 ? shiftout :
                  arithout;

  assign zero = (result == 32'b0) ? 1: 0;

endmodule