data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:57: Cell has missing pin: \'clk1_out\'\n  pll_test u_pll_test (\n           ^~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:57: Cell has missing pin: \'clk2_out\'\n  pll_test u_pll_test (\n           ^~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:225: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg0 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:231: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:237: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg2 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:439: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg0 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:445: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:569: Cell has missing pin: \'en\'\n  reg_ar_as_w13 reg0 (\n                ^~~~\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:601: Cannot find file containing module: \'EG_LOGIC_BUFG\'\n  EG_LOGIC_BUFG bufg_feedback (\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG.v\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG.sv\n             EG_LOGIC_BUFG\n             EG_LOGIC_BUFG.v\n             EG_LOGIC_BUFG.sv\n             obj_dir/EG_LOGIC_BUFG\n             obj_dir/EG_LOGIC_BUFG.v\n             obj_dir/EG_LOGIC_BUFG.sv\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:604: Cannot find file containing module: \'EG_PHY_PLL\'\n  EG_PHY_PLL #(\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module my_uart_tx
  (
  clk,
  clk_bps,
  rst_n,
  rx_data,
  rx_int,
  bps_start,
  uart_tx
  );

  input clk;
  input clk_bps;
  input rst_n;
  input [7:0] rx_data;
  input rx_int;
  output bps_start;
  output uart_tx;

  wire [3:0] n11;
  wire [3:0] n13;
  wire [3:0] n14;
  wire [3:0] n16;
  wire [7:0] n4;
  wire [3:0] num;
  wire [7:0] tx_data;
  wire bps_start_r;
  wire n0;
  wire n1;
  wire n10;
  wire n12;
  wire n15;
  wire n17;
  wire n2;
  wire n3;
  wire n5;
  wire n6;
  wire n7;
  wire n8;
  wire n9;
  wire neg_rx_int;
  wire rx_int0;
  wire rx_int1;
  wire rx_int2;
  wire tx_en;
  wire uart_tx_r;

  add_pu4_pu4_o4 add0 (
    .i0(num),
    .i1(4'b0001),
    .o(n11));
  AL_DFF bps_start_r_reg (
    .clk(clk),
    .d(n9),
    .reset(n1),
    .set(1'b0),
    .q(n6));
  eq_w4 eq0 (
    .i0(num),
    .i1(4'b1010),
    .o(n2));
  AL_DFF i28 (
    .clk(clk),
    .d(n10),
    .reset(n1),
    .set(1'b0),
    .q(n8));
  binary_mux_s1_w8 mux0 (
    .i0(tx_data),
    .i1(rx_data),
    .sel(neg_rx_int),
    .o(n4));
  binary_mux_s4_w1 mux1 (
    .i0(1'b0),
    .i1(tx_data[0]),
    .i10(1'b1),
    .i11(1'b1),
    .i12(1'b1),
    .i13(1'b1),
    .i14(1'b1),
    .i15(1'b1),
    .i2(tx_data[1]),
    .i3(tx_data[2]),
    .i4(tx_data[3]),
    .i5(tx_data[4]),
    .i6(tx_data[5]),
    .i7(tx_data[6]),
    .i8(tx_data[7]),
    .i9(1'b1),
    .sel(num),
    .o(n12));
  binary_mux_s1_w4 mux2 (
    .i0(num),
    .i1(4'b0000),
    .sel(n2),
    .o(n13));
  binary_mux_s1_w4 mux3 (
    .i0(n13),
    .i1(n11),
    .sel(clk_bps),
    .o(n14));
  binary_mux_s1_w4 mux4 (
    .i0(num),
    .i1(n14),
    .sel(tx_en),
    .o(n16));
  reg_ar_as_w8 reg0 (
    .clk(clk),
    .d(n4),
    .reset({n1,n1,n1,n1,n1,n1,n1,n1}),
    .set(8'b00000000),
    .q(tx_data));
  reg_ar_as_w4 reg1 (
    .clk(clk),
    .d(n16),
    .reset({n1,n1,n1,n1}),
    .set(4'b0000),
    .q(num));
  AL_DFF rx_int0_reg (
    .clk(clk),
    .d(rx_int),
    .reset(n1),
    .set(1'b0),
    .q(rx_int0));
  AL_DFF rx_int1_reg (
    .clk(clk),
    .d(rx_int0),
    .reset(n1),
    .set(1'b0),
    .q(rx_int1));
  AL_DFF rx_int2_reg (
    .clk(clk),
    .d(rx_int1),
    .reset(n1),
    .set(1'b0),
    .q(rx_int2));
  AL_DFF tx_en_reg (
    .clk(clk),
    .d(n5),
    .reset(n1),
    .set(1'b0),
    .q(tx_en));
  bufif1 u10 (bps_start_r, n6, n8);
  buf u11 (bps_start, bps_start_r);
  AL_MUX u12 (
    .i0(uart_tx_r),
    .i1(n12),
    .sel(clk_bps),
    .o(n15));
  AL_MUX u13 (
    .i0(uart_tx_r),
    .i1(n15),
    .sel(tx_en),
    .o(n17));
  buf u14 (uart_tx, uart_tx_r);
  not u2 (n1, rst_n);
  not u3 (n0, rx_int1);
  and u4 (neg_rx_int, n0, rx_int2);
  AL_MUX u5 (
    .i0(tx_en),
    .i1(1'b0),
    .sel(n2),
    .o(n3));
  AL_MUX u6 (
    .i0(n3),
    .i1(1'b1),
    .sel(neg_rx_int),
    .o(n5));
  or u7 (n7, neg_rx_int, n2);
  AL_MUX u8 (
    .i0(n6),
    .i1(neg_rx_int),
    .sel(n7),
    .o(n9));
  AL_MUX u9 (
    .i0(n8),
    .i1(1'b1),
    .sel(n7),
    .o(n10));
  AL_DFF uart_tx_r_reg (
    .clk(clk),
    .d(n17),
    .reset(1'b0),
    .set(n1),
    .q(uart_tx_r));

endmodule
module my_uart_tx
  (
  clk,
  clk_bps,
  rst_n,
  rx_data,
  rx_int,
  bps_start,
  uart_tx
  );


  input clk;
  input clk_bps;
  input rst_n;
  input [7:0] rx_data;
  input rx_int;
  output bps_start;
  output uart_tx;

  wire [3:0] n11;
  wire [3:0] n13;
  wire [3:0] n14;
  wire [3:0] n16;
  wire [7:0] n4;
  wire [3:0] num;
  wire [7:0] tx_data;
  wire bps_start_r;
  wire n0;
  wire n1;
  wire n10;
  wire n12;
  wire n15;
  wire n17;
  wire n2;
  wire n3;
  wire n5;
  wire n6;
  wire n7;
  wire n8;
  wire n9;
  wire neg_rx_int;
  wire rx_int0;
  wire rx_int1;
  wire rx_int2;
  wire tx_en;
  wire uart_tx_r;

  add_pu4_pu4_o4 add0 (
    .i0(num),
    .i1(4'b0001),
    .o(n11));
  AL_DFF bps_start_r_reg (
    .clk(clk),
    .d(n9),
    .reset(n1),
    .set(1'b0),
    .q(n6));
  eq_w4 eq0 (
    .i0(num),
    .i1(4'b1010),
    .o(n2));
  AL_DFF i28 (
    .clk(clk),
    .d(n10),
    .reset(n1),
    .set(1'b0),
    .q(n8));
  binary_mux_s1_w8 mux0 (
    .i0(tx_data),
    .i1(rx_data),
    .sel(neg_rx_int),
    .o(n4));
  binary_mux_s4_w1 mux1 (
    .i0(1'b0),
    .i1(tx_data[0]),
    .i10(1'b1),
    .i11(1'b1),
    .i12(1'b1),
    .i13(1'b1),
    .i14(1'b1),
    .i15(1'b1),
    .i2(tx_data[1]),
    .i3(tx_data[2]),
    .i4(tx_data[3]),
    .i5(tx_data[4]),
    .i6(tx_data[5]),
    .i7(tx_data[6]),
    .i8(tx_data[7]),
    .i9(1'b1),
    .sel(num),
    .o(n12));
  binary_mux_s1_w4 mux2 (
    .i0(num),
    .i1(4'b0000),
    .sel(n2),
    .o(n13));
  binary_mux_s1_w4 mux3 (
    .i0(n13),
    .i1(n11),
    .sel(clk_bps),
    .o(n14));
  binary_mux_s1_w4 mux4 (
    .i0(num),
    .i1(n14),
    .sel(tx_en),
    .o(n16));
  reg_ar_as_w8 reg0 (
    .clk(clk),
    .d(n4),
    .reset({n1,n1,n1,n1,n1,n1,n1,n1}),
    .set(8'b00000000),
    .q(tx_data));
  reg_ar_as_w4 reg1 (
    .clk(clk),
    .d(n16),
    .reset({n1,n1,n1,n1}),
    .set(4'b0000),
    .q(num));
  AL_DFF rx_int0_reg (
    .clk(clk),
    .d(rx_int),
    .reset(n1),
    .set(1'b0),
    .q(rx_int0));
  AL_DFF rx_int1_reg (
    .clk(clk),
    .d(rx_int0),
    .reset(n1),
    .set(1'b0),
    .q(rx_int1));
  AL_DFF rx_int2_reg (
    .clk(clk),
    .d(rx_int1),
    .reset(n1),
    .set(1'b0),
    .q(rx_int2));
  AL_DFF tx_en_reg (
    .clk(clk),
    .d(n5),
    .reset(n1),
    .set(1'b0),
    .q(tx_en));
  bufif1 u10 (bps_start_r, n6, n8);
  buf u11 (bps_start, bps_start_r);
  AL_MUX u12 (
    .i0(uart_tx_r),
    .i1(n12),
    .sel(clk_bps),
    .o(n15));
  AL_MUX u13 (
    .i0(uart_tx_r),
    .i1(n15),
    .sel(tx_en),
    .o(n17));
  buf u14 (uart_tx, uart_tx_r);
  not u2 (n1, rst_n);
  not u3 (n0, rx_int1);
  and u4 (neg_rx_int, n0, rx_int2);
  AL_MUX u5 (
    .i0(tx_en),
    .i1(1'b0),
    .sel(n2),
    .o(n3));
  AL_MUX u6 (
    .i0(n3),
    .i1(1'b1),
    .sel(neg_rx_int),
    .o(n5));
  or u7 (n7, neg_rx_int, n2);
  AL_MUX u8 (
    .i0(n6),
    .i1(neg_rx_int),
    .sel(n7),
    .o(n9));
  AL_MUX u9 (
    .i0(n8),
    .i1(1'b1),
    .sel(n7),
    .o(n10));
  AL_DFF uart_tx_r_reg (
    .clk(clk),
    .d(n17),
    .reset(1'b0),
    .set(n1),
    .q(uart_tx_r));

endmodule