data/full_repos/permissive/143278/ivltests/conditsynth3.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/conditsynth3.v:12: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/conditsynth3.v:13: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/conditsynth3.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/conditsynth3.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/conditsynth3.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/conditsynth3.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/conditsynth3.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/conditsynth3.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/conditsynth3.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/conditsynth3.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Error: Exiting due to 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [2:0] Q;
   reg	     clk, clr, up;

   (*ivl_synthesis_off *)
   initial begin
      clk = 0;
      up = 0;
      clr = 1;

      #1 clk = 1;
      #1 clk = 0;

      if (Q !== 0) begin
	 $display("FAILED");
	 $finish;
      end

      up = 1;
      clr = 0;

      #1 clk = 1;
      #1 clk = 0;

      #1 clk = 1;
      #1 clk = 0;

      if (Q !== 3'b010) begin
	 $display("FAILED");
	 $finish;
      end

      up = 0;

      #1 clk = 1;
      #1 clk = 0;

      if (Q !== 3'b010) begin
	 $display("FAILED");
	 $finish;
      end

      clr = 1;

      #1 clk = 1;
      #1 clk = 0;

      if (Q !== 0) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
      $finish;
   end


   (* ivl_synthesis_on *)
   always @(posedge clk, posedge clr) begin
      if (up)
	Q = Q + 1;
      if (clr)
	Q = 0;
   end

endmodule
module main;


   reg [2:0] Q;
   reg	     clk, clr, up;

   (*ivl_synthesis_off *)
   initial begin
      clk = 0;
      up = 0;
      clr = 1;

      #1 clk = 1;
      #1 clk = 0;

      if (Q !== 0) begin
	 $display("FAILED");
	 $finish;
      end

      up = 1;
      clr = 0;

      #1 clk = 1;
      #1 clk = 0;

      #1 clk = 1;
      #1 clk = 0;

      if (Q !== 3'b010) begin
	 $display("FAILED");
	 $finish;
      end

      up = 0;

      #1 clk = 1;
      #1 clk = 0;

      if (Q !== 3'b010) begin
	 $display("FAILED");
	 $finish;
      end

      clr = 1;

      #1 clk = 1;
      #1 clk = 0;

      if (Q !== 0) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
      $finish;
   end


   (* ivl_synthesis_on *)
   always @(posedge clk, posedge clr) begin
      if (up)
	Q = Q + 1;
      if (clr)
	Q = 0;
   end

endmodule