data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:20: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/sim,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/sim,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/sim,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:45: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:49: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:51: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:55: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:57: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:61: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:63: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:70: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:74: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:76: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:79: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:81: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:92: Unsupported: wait statements\n    wait(!rst);\n    ^~~~\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:93: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/sim/wavetrace_tb.v:109: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: Exiting due to 16 error(s)\n'
module wavetrace_tb;

`include "util.vh"

  localparam CaptDepth = 512;
  localparam DataBits = 32'd72;
  localparam TrigRegs = (DataBits + 31) / 32;
  localparam NumBanks = (DataBits + 31) / 32;
  localparam BankAddrBits = clog2(NumBanks);
  localparam CaptMemAddr = CaptDepth << BankAddrBits;
  



  wire clk, rst;
  clock_gen clkgen(
    .clk (clk),
    .rst (rst));




  reg [31:0] inst_data;
  reg        inst_valid;
  wire       inst_ready;

  task do_write(input [31:0] addr, input [31:0] data); begin
    @(posedge clk);
    inst_data  = 32'hABCD0001;
    inst_valid = 1'b1;

    @(posedge clk);
    while (!inst_ready)
      @(posedge clk);

    inst_data = addr;

    @(posedge clk);
    while (!inst_ready)
      @(posedge clk);

    inst_data = data;

    @(posedge clk);
    while (!inst_ready)
      @(posedge clk);

    inst_valid = 1'b0;

  end endtask

  task do_read(input [31:0] addr); begin
    @(posedge clk);
    inst_data = 32'hABCD0002;
    inst_valid = 1'b1;

    @(posedge clk);
    while (!inst_ready)
      @(posedge clk);
    inst_data = addr;

    @(posedge clk);
    while (!inst_ready)
      @(posedge clk);
    inst_valid = 1'b0;

  end endtask

  reg [31:0] count;

  initial begin
    inst_valid  = 0;
    inst_data   = 0;
    count       = 0;
    wait(!rst);
    @(posedge clk);

    do_write(5 << 2, 1);
    do_write(16               << 2, 128);
    do_write((16 +   TrigRegs) << 2, 128);
    do_write((16 + 2*TrigRegs) << 2, 0);
    do_write((16 + 3*TrigRegs) << 2, 128);




    do_read (16 << 2);
    do_write(8 << 2, 2);
    do_write(9 << 2, 1);

    while (count < 8000) begin
      @(posedge clk);
      count <= count + 1;
    end

    do_read((CaptMemAddr)     << 2);
    do_read((CaptMemAddr + 1) << 2);
    do_read((CaptMemAddr + 2) << 2);

    do_read((CaptMemAddr + 511) << 2);
    do_read((CaptMemAddr + 512) << 2);
    do_read((CaptMemAddr + 513) << 2);

    do_read((CaptMemAddr + 1023) << 2);
    do_read((CaptMemAddr + 1024) << 2);
    do_read((CaptMemAddr + 1025) << 2);


  end

  wire [7:0]  inst8_data;
  wire        inst8_valid, inst8_ready;
  stream_serializer #(
    .Ratio    (4),
    .DataBits (8))
  ser(
    .clk       (clk),
    .rst       (rst),

    .in_valid  (inst_valid),
    .in_ready  (inst_ready),
    .in_data   (inst_data),

    .out_valid (inst8_valid),
    .out_ready (inst8_ready),
    .out_data  (inst8_data));





  wire       host_uart_tx, host_uart_rx;
  wire       rx_valid, rx_ready;
  wire [7:0] rx_data;

  uart #(
    .ClockHz (1000000),
    .Baud    ( 115200))
  uart(
    .clk        (clk),
    .rst        (rst),

    .uart_rx    (host_uart_rx),
    .uart_tx    (host_uart_tx),

    .din_valid  (inst8_valid),
    .din_ready  (inst8_ready),
    .din_data   (inst8_data),

    .dout_valid (rx_valid),
    .dout_data  (rx_data),
    .dout_ready (rx_ready));



  wire temp_uart_rx = host_uart_tx;
  wire temp_uart_tx;
  wire temp_valid, temp_ready;
  wire [7:0] temp_data;
  uart #(
    .ClockHz (1000000),
    .Baud    ( 115200))
  uart_TEMP(
    .clk        (clk),
    .rst        (rst),

    .uart_rx    (temp_uart_rx),
    .uart_tx    (temp_uart_tx),

    .din_valid  (temp_valid),
    .din_ready  (temp_ready),
    .din_data   (temp_data),

    .dout_valid (temp_valid),
    .dout_data  (temp_data),
    .dout_ready (temp_ready));






  wire       din_valid, din_ready;
  wire [31:0] din_data;

  stream_source #(
    .FILENAME    ("in.dat"),
    .NUM_SYMBOLS (1),

    .SYMBOL_BITS ({32'd32}),
    .THROUGHPUT  (100))
  src (
    .clk       (clk),
    .rst       (rst),
    .dout_ready(din_ready),
    .dout_valid(din_valid),
    .dout_data (din_data)
    );


  reg [31:0] delay_count;
  reg        din_active;
  always @(posedge clk) begin

    if (delay_count < 5000)
      delay_count <= delay_count + 1;
    else
      din_active  <= 1;

    if (rst) begin
      din_active <= 0;
      delay_count <= 0;
    end
  end

  assign din_ready = (din_active) ? 1 : 0;

  wire [DataBits-1:0] din_data_wt = {3{din_data}};
  wavetrace #(
    .DataBits (DataBits),
    .CaptDepth(CaptDepth),
    .ClockHz  (1000000),
    .UartBaud ( 115200))
  dut (
    .clk     (clk),
    .rst     (rst),
    .uart_rx (host_uart_tx),
    .uart_tx (host_uart_rx),
    .din_data(din_data_wt)
    );

endmodule
module wavetrace_tb;


`include "util.vh"

  localparam CaptDepth = 512;
  localparam DataBits = 32'd72;
  localparam TrigRegs = (DataBits + 31) / 32;
  localparam NumBanks = (DataBits + 31) / 32;
  localparam BankAddrBits = clog2(NumBanks);
  localparam CaptMemAddr = CaptDepth << BankAddrBits;
  



  wire clk, rst;
  clock_gen clkgen(
    .clk (clk),
    .rst (rst));




  reg [31:0] inst_data;
  reg        inst_valid;
  wire       inst_ready;

  task do_write(input [31:0] addr, input [31:0] data); begin
    @(posedge clk);
    inst_data  = 32'hABCD0001;
    inst_valid = 1'b1;

    @(posedge clk);
    while (!inst_ready)
      @(posedge clk);

    inst_data = addr;

    @(posedge clk);
    while (!inst_ready)
      @(posedge clk);

    inst_data = data;

    @(posedge clk);
    while (!inst_ready)
      @(posedge clk);

    inst_valid = 1'b0;

  end endtask

  task do_read(input [31:0] addr); begin
    @(posedge clk);
    inst_data = 32'hABCD0002;
    inst_valid = 1'b1;

    @(posedge clk);
    while (!inst_ready)
      @(posedge clk);
    inst_data = addr;

    @(posedge clk);
    while (!inst_ready)
      @(posedge clk);
    inst_valid = 1'b0;

  end endtask

  reg [31:0] count;

  initial begin
    inst_valid  = 0;
    inst_data   = 0;
    count       = 0;
    wait(!rst);
    @(posedge clk);

    do_write(5 << 2, 1);
    do_write(16               << 2, 128);
    do_write((16 +   TrigRegs) << 2, 128);
    do_write((16 + 2*TrigRegs) << 2, 0);
    do_write((16 + 3*TrigRegs) << 2, 128);




    do_read (16 << 2);
    do_write(8 << 2, 2);
    do_write(9 << 2, 1);

    while (count < 8000) begin
      @(posedge clk);
      count <= count + 1;
    end

    do_read((CaptMemAddr)     << 2);
    do_read((CaptMemAddr + 1) << 2);
    do_read((CaptMemAddr + 2) << 2);

    do_read((CaptMemAddr + 511) << 2);
    do_read((CaptMemAddr + 512) << 2);
    do_read((CaptMemAddr + 513) << 2);

    do_read((CaptMemAddr + 1023) << 2);
    do_read((CaptMemAddr + 1024) << 2);
    do_read((CaptMemAddr + 1025) << 2);


  end

  wire [7:0]  inst8_data;
  wire        inst8_valid, inst8_ready;
  stream_serializer #(
    .Ratio    (4),
    .DataBits (8))
  ser(
    .clk       (clk),
    .rst       (rst),

    .in_valid  (inst_valid),
    .in_ready  (inst_ready),
    .in_data   (inst_data),

    .out_valid (inst8_valid),
    .out_ready (inst8_ready),
    .out_data  (inst8_data));





  wire       host_uart_tx, host_uart_rx;
  wire       rx_valid, rx_ready;
  wire [7:0] rx_data;

  uart #(
    .ClockHz (1000000),
    .Baud    ( 115200))
  uart(
    .clk        (clk),
    .rst        (rst),

    .uart_rx    (host_uart_rx),
    .uart_tx    (host_uart_tx),

    .din_valid  (inst8_valid),
    .din_ready  (inst8_ready),
    .din_data   (inst8_data),

    .dout_valid (rx_valid),
    .dout_data  (rx_data),
    .dout_ready (rx_ready));



  wire temp_uart_rx = host_uart_tx;
  wire temp_uart_tx;
  wire temp_valid, temp_ready;
  wire [7:0] temp_data;
  uart #(
    .ClockHz (1000000),
    .Baud    ( 115200))
  uart_TEMP(
    .clk        (clk),
    .rst        (rst),

    .uart_rx    (temp_uart_rx),
    .uart_tx    (temp_uart_tx),

    .din_valid  (temp_valid),
    .din_ready  (temp_ready),
    .din_data   (temp_data),

    .dout_valid (temp_valid),
    .dout_data  (temp_data),
    .dout_ready (temp_ready));






  wire       din_valid, din_ready;
  wire [31:0] din_data;

  stream_source #(
    .FILENAME    ("in.dat"),
    .NUM_SYMBOLS (1),

    .SYMBOL_BITS ({32'd32}),
    .THROUGHPUT  (100))
  src (
    .clk       (clk),
    .rst       (rst),
    .dout_ready(din_ready),
    .dout_valid(din_valid),
    .dout_data (din_data)
    );


  reg [31:0] delay_count;
  reg        din_active;
  always @(posedge clk) begin

    if (delay_count < 5000)
      delay_count <= delay_count + 1;
    else
      din_active  <= 1;

    if (rst) begin
      din_active <= 0;
      delay_count <= 0;
    end
  end

  assign din_ready = (din_active) ? 1 : 0;

  wire [DataBits-1:0] din_data_wt = {3{din_data}};
  wavetrace #(
    .DataBits (DataBits),
    .CaptDepth(CaptDepth),
    .ClockHz  (1000000),
    .UartBaud ( 115200))
  dut (
    .clk     (clk),
    .rst     (rst),
    .uart_rx (host_uart_tx),
    .uart_tx (host_uart_rx),
    .din_data(din_data_wt)
    );

endmodule