data/full_repos/permissive/138961980/powlib_std.v
 line:24: before: "if"
1: b'%Error: data/full_repos/permissive/138961980/powlib_std.v:195: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh.v\n             data/full_repos/permissive/138961980,data/full_repos/permissive/138961980/powlib_std.vh.sv\n             powlib_std.vh\n             powlib_std.vh.v\n             powlib_std.vh.sv\n             obj_dir/powlib_std.vh\n             obj_dir/powlib_std.vh.v\n             obj_dir/powlib_std.vh.sv\n%Error: data/full_repos/permissive/138961980/powlib_std.v:221: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:252: Cannot find include file: powlib_std.vh\n`include "powlib_std.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:207: Define or directive not defined: \'`POWLIB_DW\'\n            wire [`POWLIB_DW-1:0] d0 = powlib_grayencode(d); \n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/138961980/powlib_std.v:233: Define or directive not defined: \'`POWLIB_DW\'\n            wire [`POWLIB_DW-1:0] d0 = powlib_graydecode(d); \n                  ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module powlib_flag(q,set,clr,clk,rst);



  parameter      INIT = 0;
  parameter      EAR  = 0;
  output    wire q;
  input     wire set;
  input     wire clr;
  input     wire clk;
  input     wire rst;
  
  powlib_flipflop #(.W(1),.INIT(INIT),.EAR(EAR),.EVLD(1)) flag_inst (
    .d((clr) ? 1'd0 :
       (set) ? 1'd1 : 1'dz),
    .q(q),
    .clk(clk),
    .rst(rst),
    .vld(clr||set));
    
endmodule
module powlib_flag(q,set,clr,clk,rst);




  parameter      INIT = 0;
  parameter      EAR  = 0;
  output    wire q;
  input     wire set;
  input     wire clr;
  input     wire clk;
  input     wire rst;
  
  powlib_flipflop #(.W(1),.INIT(INIT),.EAR(EAR),.EVLD(1)) flag_inst (
    .d((clr) ? 1'd0 :
       (set) ? 1'd1 : 1'dz),
    .q(q),
    .clk(clk),
    .rst(rst),
    .vld(clr||set));
    
endmodule