data/full_repos/permissive/202237519/verilog/digitalsystem4/4bit_div_tb.v
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1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem4/4bit_div_tb.v:1: Cannot find include file: 4bit_div.v\n`include "4bit_div.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem4,data/full_repos/permissive/202237519/4bit_div.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem4,data/full_repos/permissive/202237519/4bit_div.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem4,data/full_repos/permissive/202237519/4bit_div.v.sv\n             4bit_div.v\n             4bit_div.v.v\n             4bit_div.v.sv\n             obj_dir/4bit_div.v\n             obj_dir/4bit_div.v.v\n             obj_dir/4bit_div.v.sv\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem4/4bit_div_tb.v:14: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("4bit_div_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem4/4bit_div_tb.v:15: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,div_4bit_tb);  \n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem4/4bit_div_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n            A <= j; #10;\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module div_4bit_tb;

reg [3:0] A,B;
reg cin;
wire [3:0] Q,R;
integer i,j;

div_4bit div0(A,B,Q,R,cin);

initial begin
    $dumpfile("4bit_div_tb.vcd");
    $dumpvars(0,div_4bit_tb);
    cin <= 1'b1;
    for(i=4'b0000; i<= 4'b1111; i++) begin
        B <= i;
        for(j=4'b0000; j<= 4'b1111; j++) begin
            A <= j; #10;
        end
    end
    $finish;
end

endmodule
module div_4bit_tb;


reg [3:0] A,B;
reg cin;
wire [3:0] Q,R;
integer i,j;

div_4bit div0(A,B,Q,R,cin);

initial begin
    $dumpfile("4bit_div_tb.vcd");
    $dumpvars(0,div_4bit_tb);
    cin <= 1'b1;
    for(i=4'b0000; i<= 4'b1111; i++) begin
        B <= i;
        for(j=4'b0000; j<= 4'b1111; j++) begin
            A <= j; #10;
        end
    end
    $finish;
end

endmodule