data/full_repos/permissive/161004496/serial.v
1: b'%Error: data/full_repos/permissive/161004496/serial.v:42: Cannot find file containing module: \'top\'\ntop ser(clk,~reset, rxD, s_in, sig, otxdata);  \n^~~\n        ... Looked in:\n             data/full_repos/permissive/161004496,data/full_repos/permissive/161004496/top\n             data/full_repos/permissive/161004496,data/full_repos/permissive/161004496/top.v\n             data/full_repos/permissive/161004496,data/full_repos/permissive/161004496/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Warning-WIDTH: data/full_repos/permissive/161004496/serial.v:51: Operator ASSIGNDLY expects 30 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 38 bits.\n                                                                : ... In instance serial\n        sout<={sout,s_in};   \n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module serial(clk, reset, rxD,sout,signal,counter);
input clk;
input reset;
input rxD;

parameter n = 30;

output reg [n-1:0]sout;
output reg signal;

parameter count = 4;
output reg [31:0]counter;


reg [1:0]delay;
wire [7:0]s_in;
wire sig;
wire otxdata;

top ser(clk,~reset, rxD, s_in, sig, otxdata);

always @(negedge sig, posedge reset)
    if(reset)
    begin
        counter <= 0;
    end
    else
    begin
        sout<={sout,s_in};
        if(counter < (count-1))
        begin
            counter <= counter+1;
        end
        else if(counter==(count-1))
        begin
            counter <= 0;
        end
     end
     
always @(posedge clk, posedge reset)
if(reset)
    delay<=0;
else if(sig==1 && counter==(count-1))
    delay<=1;
else if(delay==1)
    begin
    delay<=2;
    signal<=1;
    end
else if(delay==2)
    begin
    delay<=3;
    end
else if(delay==3)
    begin
        delay<=0;
        signal<=0;
    end
endmodule
module serial(clk, reset, rxD,sout,signal,counter);

input clk;
input reset;
input rxD;

parameter n = 30;

output reg [n-1:0]sout;
output reg signal;

parameter count = 4;
output reg [31:0]counter;


reg [1:0]delay;
wire [7:0]s_in;
wire sig;
wire otxdata;

top ser(clk,~reset, rxD, s_in, sig, otxdata);

always @(negedge sig, posedge reset)
    if(reset)
    begin
        counter <= 0;
    end
    else
    begin
        sout<={sout,s_in};
        if(counter < (count-1))
        begin
            counter <= counter+1;
        end
        else if(counter==(count-1))
        begin
            counter <= 0;
        end
     end
     
always @(posedge clk, posedge reset)
if(reset)
    delay<=0;
else if(sig==1 && counter==(count-1))
    delay<=1;
else if(delay==1)
    begin
    delay<=2;
    signal<=1;
    end
else if(delay==2)
    begin
    delay<=3;
    end
else if(delay==3)
    begin
        delay<=0;
        signal<=0;
    end
endmodule