data/full_repos/permissive/204486675/components/pwm/pwm_tb.v
 line:58: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/204486675/components/pwm/pwm_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/204486675/components/pwm/pwm_tb.v:44: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile(`VCD_OUTPUT".vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/204486675/components/pwm/pwm_tb.v:44: Define or directive not defined: \'`VCD_OUTPUT\'\n  $dumpfile(`VCD_OUTPUT".vcd");\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/204486675/components/pwm/pwm_tb.v:45: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, clockdiv_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/pwm/pwm_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #0 rst <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/pwm/pwm_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #1 rst <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/pwm/pwm_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #20 onperiod <= 16\'b0000000000000001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/pwm/pwm_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #20 onperiod <= 16\'b0000000000000111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/204486675/components/pwm/pwm_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n   #(DURATION) $display("End of simulation");\n   ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clockdiv_tb();


reg clk = 0;
always #0.5 clk = ~clk;

wire clkout;
reg rst;
reg [16:0] onperiod;
reg [16:0] offperiod;

parameter DURATION = 50;


pwm UUT (
	.rst(rst),
	.clkin(clk),
	.clkout(clkout),
	.onperiod(onperiod),
	.offperiod(offperiod)
);

initial begin

  $dumpfile(`DUMPSTR(`VCD_OUTPUT));
  $dumpvars(0, clockdiv_tb);

	#0	rst <= 1;
	#1	rst <= 0;
		onperiod <= 16'b0000000000000010;
		offperiod <= 16'b0000000000000001;
	#20	onperiod <= 16'b0000000000000001;
		offperiod <= 16'b0000000000000010;
	#20	onperiod <= 16'b0000000000000111;
		offperiod <= 16'b0000000000000001;



   #(DURATION) $display("End of simulation");
  $finish;
end

endmodule
module clockdiv_tb();



reg clk = 0;
always #0.5 clk = ~clk;

wire clkout;
reg rst;
reg [16:0] onperiod;
reg [16:0] offperiod;

parameter DURATION = 50;


pwm UUT (
	.rst(rst),
	.clkin(clk),
	.clkout(clkout),
	.onperiod(onperiod),
	.offperiod(offperiod)
);

initial begin

  $dumpfile(`DUMPSTR(`VCD_OUTPUT));
  $dumpvars(0, clockdiv_tb);

	#0	rst <= 1;
	#1	rst <= 0;
		onperiod <= 16'b0000000000000010;
		offperiod <= 16'b0000000000000001;
	#20	onperiod <= 16'b0000000000000001;
		offperiod <= 16'b0000000000000010;
	#20	onperiod <= 16'b0000000000000111;
		offperiod <= 16'b0000000000000001;



   #(DURATION) $display("End of simulation");
  $finish;
end

endmodule