data/full_repos/permissive/201267735/rtl/core/frv_rngif.v
1: b'%Error: data/full_repos/permissive/201267735/rtl/core/frv_rngif.v:37: Cannot find include file: frv_common.vh\n`include "frv_common.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201267735/rtl/core,data/full_repos/permissive/201267735/frv_common.vh\n             data/full_repos/permissive/201267735/rtl/core,data/full_repos/permissive/201267735/frv_common.vh.v\n             data/full_repos/permissive/201267735/rtl/core,data/full_repos/permissive/201267735/frv_common.vh.sv\n             frv_common.vh\n             frv_common.vh.v\n             frv_common.vh.sv\n             obj_dir/frv_common.vh\n             obj_dir/frv_common.vh.v\n             obj_dir/frv_common.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module frv_rngif (

input              g_clk            ,
input              g_resetn         ,

input  wire        flush            ,
input  wire        pipeline_progress,

input  wire        valid            ,
input  wire [XL:0] rs1              ,

output wire        rng_req_valid    ,
output wire [ 2:0] rng_req_op       ,
output wire [31:0] rng_req_data     ,
input  wire        rng_req_ready    ,

input  wire        rng_rsp_valid    ,
input  wire [ 2:0] rng_rsp_status   ,
input  wire [31:0] rng_rsp_data     ,
output wire        rng_rsp_ready    ,

input  wire        uop_test         ,
input  wire        uop_seed         ,
input  wire        uop_samp         ,

output wire [XL:0] result           ,
output wire        ready

);

`include "frv_common.vh"





assign rng_req_op       = {
    uop_test, uop_samp, uop_seed
};

assign rng_req_data     = rs1;


reg    req_done;
wire   n_req_done       = (req_done || (rng_req_valid && rng_req_ready)) &&
                         !(flush || pipeline_progress);

assign rng_req_valid    = valid && !req_done;

always @(posedge g_clk) begin
    if(!g_resetn) begin
        req_done <= 1'b0;
    end else begin
        req_done <= n_req_done;
    end
end






assign ready            = (valid && rng_rsp_valid) || req_done;

assign rng_rsp_ready    = pipeline_progress;

wire   status_healthy   = rng_rsp_status == RNG_IF_INIT_HEALTHY;

assign result           = uop_samp ? rng_rsp_data               :
                          uop_test ? {31'b0, status_healthy}    :
                                     32'b0                      ;

endmodule
module frv_rngif (

input              g_clk            ,
input              g_resetn         ,

input  wire        flush            ,
input  wire        pipeline_progress,

input  wire        valid            ,
input  wire [XL:0] rs1              ,

output wire        rng_req_valid    ,
output wire [ 2:0] rng_req_op       ,
output wire [31:0] rng_req_data     ,
input  wire        rng_req_ready    ,

input  wire        rng_rsp_valid    ,
input  wire [ 2:0] rng_rsp_status   ,
input  wire [31:0] rng_rsp_data     ,
output wire        rng_rsp_ready    ,

input  wire        uop_test         ,
input  wire        uop_seed         ,
input  wire        uop_samp         ,

output wire [XL:0] result           ,
output wire        ready

);


`include "frv_common.vh"





assign rng_req_op       = {
    uop_test, uop_samp, uop_seed
};

assign rng_req_data     = rs1;


reg    req_done;
wire   n_req_done       = (req_done || (rng_req_valid && rng_req_ready)) &&
                         !(flush || pipeline_progress);

assign rng_req_valid    = valid && !req_done;

always @(posedge g_clk) begin
    if(!g_resetn) begin
        req_done <= 1'b0;
    end else begin
        req_done <= n_req_done;
    end
end






assign ready            = (valid && rng_rsp_valid) || req_done;

assign rng_rsp_ready    = pipeline_progress;

wire   status_healthy   = rng_rsp_status == RNG_IF_INIT_HEALTHY;

assign result           = uop_samp ? rng_rsp_data               :
                          uop_test ? {31'b0, status_healthy}    :
                                     32'b0                      ;

endmodule