data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v
1: b"%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:170: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n  output [DATA_WIDTH_R-1:0] do,\n                            ^~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:206: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  output [DATA_WIDTH_R-1:0] do,\n                            ^~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:225: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  output [3:0]do\n              ^~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:759: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  input [3:0] do,\n              ^~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:893: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  output [7:0] do,\n               ^~\n%Error: Exiting due to 5 error(s)\n"
module EG_PHY_DDR_8M_16(
  input clk,
  input clk_n,
  input ras_n,
  input cas_n,
  input we_n,
  input cs_n,
  input [11:0] addr,
  input [1:0] ba,
  inout [15:0] dq,
  input ldqs,
  input udqs,
  input ldm,
  input udm,
  input cke
);
endmodule
module EG_PHY_DDR_8M_16(
  input clk,
  input clk_n,
  input ras_n,
  input cas_n,
  input we_n,
  input cs_n,
  input [11:0] addr,
  input [1:0] ba,
  inout [15:0] dq,
  input ldqs,
  input udqs,
  input ldm,
  input udm,
  input cke
);

endmodule