data/full_repos/permissive/21203606/ex2/foo_counter.v
data/verilator_xmls/a257d56d-2549-4494-826f-e3de72d3b364.xml
module foo_counter(
  input wire clk,
  input wire rst,
  input wire en,
  output reg [7:0] cnt);
  
always @(posedge clk)
begin

  if (rst)
  begin
    cnt <= 8'd0;
  end
  else
  begin
    if (en)
    begin
      cnt <= cnt + 1;
    end
    else
    begin
      cnt <= cnt;
    end
  end
end

endmodule
module foo_counter(
  input wire clk,
  input wire rst,
  input wire en,
  output reg [7:0] cnt);

  
always @(posedge clk)
begin

  if (rst)
  begin
    cnt <= 8'd0;
  end
  else
  begin
    if (en)
    begin
      cnt <= cnt + 1;
    end
    else
    begin
      cnt <= cnt;
    end
  end
end

endmodule