data/full_repos/permissive/102394571/clock_divisor.v
data/verilator_xmls/bb6e254b-2e9a-450f-92a4-28722a405921.xml
module clock_divisor(
    input clk_100MHz,
	 input reset,
    output reg clk_1Hz 
    );
	 

reg[25:0] contador = 0;
reg reset_last = 0;
initial clk_1Hz = 0 ;

always @(posedge clk_100MHz)
begin
	if (reset && reset != reset_last)
	begin
		contador = 0;
		clk_1Hz = 0;
		reset_last = reset;
	end
	else
	begin
		if(contador != 50000000)	
		begin
			contador = contador + 1 ; 
		end
		else
		begin
			contador = 0;
			clk_1Hz = ~clk_1Hz; 
		end
		reset_last = reset;
	end
end
endmodule
module clock_divisor(
    input clk_100MHz,
	 input reset,
    output reg clk_1Hz 
    );

	 

reg[25:0] contador = 0;
reg reset_last = 0;
initial clk_1Hz = 0 ;

always @(posedge clk_100MHz)
begin
	if (reset && reset != reset_last)
	begin
		contador = 0;
		clk_1Hz = 0;
		reset_last = reset;
	end
	else
	begin
		if(contador != 50000000)	
		begin
			contador = contador + 1 ; 
		end
		else
		begin
			contador = 0;
			clk_1Hz = ~clk_1Hz; 
		end
		reset_last = reset;
	end
end
endmodule