data/full_repos/permissive/181738725/wavetrace/verilog/lib/debug/stream_capture.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/debug/stream_capture.v:28: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/debug,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/debug,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/debug,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module stream_capture (clk, rst, din_data, din_valid, din_ready,
                       cfg_paddr, cfg_psel, cfg_penable, cfg_pwrite,
                       cfg_pwdata, cfg_pready, cfg_prdata, cfg_pslverr);
`include "util.vh"
  parameter  DataBits    = 8;
  parameter  MemDepth    = 1024;
  localparam MemAddrBits = clog2(MemDepth);

  input                   clk;
  input                   rst;

  input [DataBits-1:0]    din_data;
  input                   din_valid;
  input                   din_ready;

  input [2+MemAddrBits:0] cfg_paddr;
  input                   cfg_psel;
  input                   cfg_penable;
  input                   cfg_pwrite;
  input [31:0]            cfg_pwdata;
  output reg              cfg_pready;
  output reg [31:0]       cfg_prdata;
  output                  cfg_pslverr;






  localparam EnableAddr = 2**MemAddrBits + 0,
             ResetAddr  = 2**MemAddrBits + 1,
             CountAddr  = 2**MemAddrBits + 2,
             WPtrAddr   = 2**MemAddrBits + 3;




  assign cfg_pslverr = 0;

  wire [DataBits-1:0]    mem_data;

  reg                    enable, soft_rst, mem_rd;
  reg [15:0]             count;
  reg [MemAddrBits-1:0]  wptr;

  always @(posedge clk) begin :cfg
    integer addr_i;
    addr_i = cfg_paddr >> 2;


    mem_rd     <= 0;
    cfg_pready <= 0;

    if (cfg_psel && !cfg_penable) begin

      if (cfg_pwrite) begin
        cfg_pready <= 1;
        case (addr_i)
          EnableAddr:   enable   <= cfg_pwdata[0];
          ResetAddr:    soft_rst <= cfg_pwdata[0];
        endcase


      end else begin
        if (addr_i < MemDepth) begin
          mem_rd  <= 1;
        end else begin
          cfg_pready <= 1;
          case (addr_i)
            EnableAddr: cfg_prdata <= enable;
            ResetAddr:  cfg_prdata <= soft_rst;
            CountAddr:  cfg_prdata <= count;
            WPtrAddr:   cfg_prdata <= wptr;
          endcase
        end
      end
    end


    if (mem_rd) begin
      cfg_prdata <= mem_data;
      cfg_pready <= 1;
    end

    if (rst) begin
      enable   <= 0;
      soft_rst <= 0;
    end
  end




  wire wen  = enable & din_valid & din_ready;

  always @(posedge clk) begin
    if (wen) begin
      wptr  <= (wptr == MemDepth-1) ? 0 : wptr + 1;
      count <= count + 1;
    end
    if (rst | soft_rst) begin
      wptr  <= 0;
      count <= 0;
    end
  end

  ram_1r_1w #(
    .Width (DataBits),
    .Depth (MemDepth))
  mem(
    .clk     (clk),
    .wr_en   (wen),
    .wr_addr (wptr),
    .wr_data (din_data),
    .rd_addr (cfg_paddr[MemAddrBits+2-1:2]),
    .rd_data (mem_data));

endmodule
module stream_capture (clk, rst, din_data, din_valid, din_ready,
                       cfg_paddr, cfg_psel, cfg_penable, cfg_pwrite,
                       cfg_pwdata, cfg_pready, cfg_prdata, cfg_pslverr);

`include "util.vh"
  parameter  DataBits    = 8;
  parameter  MemDepth    = 1024;
  localparam MemAddrBits = clog2(MemDepth);

  input                   clk;
  input                   rst;

  input [DataBits-1:0]    din_data;
  input                   din_valid;
  input                   din_ready;

  input [2+MemAddrBits:0] cfg_paddr;
  input                   cfg_psel;
  input                   cfg_penable;
  input                   cfg_pwrite;
  input [31:0]            cfg_pwdata;
  output reg              cfg_pready;
  output reg [31:0]       cfg_prdata;
  output                  cfg_pslverr;






  localparam EnableAddr = 2**MemAddrBits + 0,
             ResetAddr  = 2**MemAddrBits + 1,
             CountAddr  = 2**MemAddrBits + 2,
             WPtrAddr   = 2**MemAddrBits + 3;




  assign cfg_pslverr = 0;

  wire [DataBits-1:0]    mem_data;

  reg                    enable, soft_rst, mem_rd;
  reg [15:0]             count;
  reg [MemAddrBits-1:0]  wptr;

  always @(posedge clk) begin :cfg
    integer addr_i;
    addr_i = cfg_paddr >> 2;


    mem_rd     <= 0;
    cfg_pready <= 0;

    if (cfg_psel && !cfg_penable) begin

      if (cfg_pwrite) begin
        cfg_pready <= 1;
        case (addr_i)
          EnableAddr:   enable   <= cfg_pwdata[0];
          ResetAddr:    soft_rst <= cfg_pwdata[0];
        endcase


      end else begin
        if (addr_i < MemDepth) begin
          mem_rd  <= 1;
        end else begin
          cfg_pready <= 1;
          case (addr_i)
            EnableAddr: cfg_prdata <= enable;
            ResetAddr:  cfg_prdata <= soft_rst;
            CountAddr:  cfg_prdata <= count;
            WPtrAddr:   cfg_prdata <= wptr;
          endcase
        end
      end
    end


    if (mem_rd) begin
      cfg_prdata <= mem_data;
      cfg_pready <= 1;
    end

    if (rst) begin
      enable   <= 0;
      soft_rst <= 0;
    end
  end




  wire wen  = enable & din_valid & din_ready;

  always @(posedge clk) begin
    if (wen) begin
      wptr  <= (wptr == MemDepth-1) ? 0 : wptr + 1;
      count <= count + 1;
    end
    if (rst | soft_rst) begin
      wptr  <= 0;
      count <= 0;
    end
  end

  ram_1r_1w #(
    .Width (DataBits),
    .Depth (MemDepth))
  mem(
    .clk     (clk),
    .wr_en   (wen),
    .wr_addr (wptr),
    .wr_data (din_data),
    .rd_addr (cfg_paddr[MemAddrBits+2-1:2]),
    .rd_data (mem_data));

endmodule