data/full_repos/permissive/209644662/hardware/generator_z/top/mdll_top.sv
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data/verilator_xmls/bf7dcc8b-7bd1-4156-b47e-c609ae43bcdd.xml
module mdll_top #(

) (

  input ext_cki,
  input ext_ckib,
  input ext_frefp,
  input ext_frefn,
  input ext_cki_jm,
  input ext_ckib_jm,
  input ext_frefp_jm,
  input ext_frefn_jm,
  input clk_ext_in,
  
  input ref_sel,
  input reset,
  input rstb,
  input en_inj,
  input en_osc,

  input sel_bb_in,
  input en_ext_tune,
  input bypass_dcdl,
  input loop_sel,

  input aux_sel,
  input en_aux,
  input aux_div,
  input [2:0] ndiv_aux,
  input [4:0] aux_tune,
 
  input [1:0] ndiv,
  input [3:0] ndiv_fref,
  
  input [1:0] gain_ratio,
  input [3:0] gain_ctrl,
  
  
  input [3:0] ctune0,
  
  input [3:0] ctune1,
  
  input [6:0] ext_mtune,
  
  input [2:0] m_str,
  
  
  input [1:0] en_dith,
  input dith_sel,
  input en_dsm_lsb_dith,
  input [2:0] ndiv_fout,
  
  input bypass_retimer,
  input [1:0] sel_ph,
  input [2:0] dith_retime,
  
  input bypass_bb,
  input bypass_tdc,
  input [3:0] add_off,
  
  input en_jm,
  input ref_sel_jm,
  input [5:0] ncycle_jm,

  input [31:0] mdll_reserved,

  output aux_div_pad,
  output fout_div_pad,
  output fref_off_pad,
  output ffeed_pad,
  
  output frefp_out_jm,
  output frefn_out_jm,

  output [3:0] mdllout_pad,
  output [19:0] jm_out,
  output [12:0] lf_out
);


wire frefp_buf, frefn_buf;
wire frefp_buf_jm, frefn_buf_jm;
wire ck_aux_osc;
wire dither_out;
wire dither_retime;
wire mdllout;
wire [6:0] dith_retime_thm;
wire [6:0] m_str_thm;
wire [14:0] add_off_thm;
wire start;
wire start_off;
wire stop;
wire stop_off;
wire [14:0]  ctune_thm0, ctune_thm1;
wire [6:0] mtune;
wire [6:0] str_thm;
wire clk_err;
wire mdllout_div;
wire dout_bb;
wire dout_1b_tdc;
wire mdllout_dither_out;
wire mdllout_div_out;
wire fref_dcdl_out;








endmodule
module mdll_top #(

) (

  input ext_cki,
  input ext_ckib,
  input ext_frefp,
  input ext_frefn,
  input ext_cki_jm,
  input ext_ckib_jm,
  input ext_frefp_jm,
  input ext_frefn_jm,
  input clk_ext_in,
  
  input ref_sel,
  input reset,
  input rstb,
  input en_inj,
  input en_osc,

  input sel_bb_in,
  input en_ext_tune,
  input bypass_dcdl,
  input loop_sel,

  input aux_sel,
  input en_aux,
  input aux_div,
  input [2:0] ndiv_aux,
  input [4:0] aux_tune,
 
  input [1:0] ndiv,
  input [3:0] ndiv_fref,
  
  input [1:0] gain_ratio,
  input [3:0] gain_ctrl,
  
  
  input [3:0] ctune0,
  
  input [3:0] ctune1,
  
  input [6:0] ext_mtune,
  
  input [2:0] m_str,
  
  
  input [1:0] en_dith,
  input dith_sel,
  input en_dsm_lsb_dith,
  input [2:0] ndiv_fout,
  
  input bypass_retimer,
  input [1:0] sel_ph,
  input [2:0] dith_retime,
  
  input bypass_bb,
  input bypass_tdc,
  input [3:0] add_off,
  
  input en_jm,
  input ref_sel_jm,
  input [5:0] ncycle_jm,

  input [31:0] mdll_reserved,

  output aux_div_pad,
  output fout_div_pad,
  output fref_off_pad,
  output ffeed_pad,
  
  output frefp_out_jm,
  output frefn_out_jm,

  output [3:0] mdllout_pad,
  output [19:0] jm_out,
  output [12:0] lf_out
);



wire frefp_buf, frefn_buf;
wire frefp_buf_jm, frefn_buf_jm;
wire ck_aux_osc;
wire dither_out;
wire dither_retime;
wire mdllout;
wire [6:0] dith_retime_thm;
wire [6:0] m_str_thm;
wire [14:0] add_off_thm;
wire start;
wire start_off;
wire stop;
wire stop_off;
wire [14:0]  ctune_thm0, ctune_thm1;
wire [6:0] mtune;
wire [6:0] str_thm;
wire clk_err;
wire mdllout_div;
wire dout_bb;
wire dout_1b_tdc;
wire mdllout_dither_out;
wire mdllout_div_out;
wire fref_dcdl_out;








endmodule