data/full_repos/permissive/205055389/primitives/ram.v
 line:2: before: "."
1: b"%Error: data/full_repos/permissive/205055389/primitives/ram.v:2: syntax error, unexpected '.', expecting '['\nmodule ram #(.Dout(1),   \n             ^\n%Error: data/full_repos/permissive/205055389/primitives/ram.v:17: syntax error, unexpected specify\n   specify\n   ^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ram #(.Dout(1),
	     .Dread(1),
	     .Dwrite(1),
	     .Daddr_setup(1),
	     .Daddr_hold(1),
	     .Ddata_hold(1))
	(A, D, WE, OE, CS);
	    
   input OE, WE, CS;
   input ${A_RANGE} A;
   inout ${D_RANGE} D;
   reg 	 ${D_RANGE} m${MEM_RANGE};
   wire  ${D_RANGE} X;
   wire  doRead, doWrite;

   specify
      $setup(A, posedge doWrite, Daddr_setup);
      $hold(negedge doWrite, A, Daddr_hold);
      $hold(negedge doWrite, D, Ddata_hold);
      $width(posedge doWrite, Dwrite);
   endspecify

   assign doRead = (!CS && !OE);
   assign doWrite = (!CS && !WE);




   assign #Dread X = m[A];




   assign #Dout D = doRead ? X : ${D_BITS}'bz;




   always @(doWrite or D or A)
     if (doWrite)
       m[A] <= #Dwrite D;

   always @(D)
     if (doWrite)
       $error("`RAMDCHG %m[%M]");

   always @(A)
     if (doWrite)
       $error("`RAMACHG %m[%M]");
   

endmodule
module ram #(.Dout(1),
	     .Dread(1),
	     .Dwrite(1),
	     .Daddr_setup(1),
	     .Daddr_hold(1),
	     .Ddata_hold(1))
	(A, D, WE, OE, CS);

	    
   input OE, WE, CS;
   input ${A_RANGE} A;
   inout ${D_RANGE} D;
   reg 	 ${D_RANGE} m${MEM_RANGE};
   wire  ${D_RANGE} X;
   wire  doRead, doWrite;

   specify
      $setup(A, posedge doWrite, Daddr_setup);
      $hold(negedge doWrite, A, Daddr_hold);
      $hold(negedge doWrite, D, Ddata_hold);
      $width(posedge doWrite, Dwrite);
   endspecify

   assign doRead = (!CS && !OE);
   assign doWrite = (!CS && !WE);




   assign #Dread X = m[A];




   assign #Dout D = doRead ? X : ${D_BITS}'bz;




   always @(doWrite or D or A)
     if (doWrite)
       m[A] <= #Dwrite D;

   always @(D)
     if (doWrite)
       $error("`RAMDCHG %m[%M]");

   always @(A)
     if (doWrite)
       $error("`RAMACHG %m[%M]");
   

endmodule