data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v
1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:5: Define or directive not defined: \'`ICODE_BUS\'\n    input wire [`ICODE_BUS] E_icode_i,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:5: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`ICODE_BUS] E_icode_i,\n                          ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:6: Define or directive not defined: \'`IFUN_BUS\'\n    input wire [`IFUN_BUS] E_ifun_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:7: Define or directive not defined: \'`REG_ADDR_BUS\'\n    input wire [`REG_ADDR_BUS] E_dstE_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire SF_i,\n    ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire OF_i,\n    ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:12: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg e_Cnd_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:13: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [`REG_ADDR_BUS] e_dstE_o\n    ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:13: Define or directive not defined: \'`REG_ADDR_BUS\'\n    output reg [`REG_ADDR_BUS] e_dstE_o\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:18: syntax error, unexpected initial\n    initial\n    ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:20: Define or directive not defined: \'`FALSE\'\n        ZF = `FALSE;\n             ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:21: Define or directive not defined: \'`FALSE\'\n        SF = `FALSE;\n             ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:22: Define or directive not defined: \'`FALSE\'\n        OF = `FALSE;\n             ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:27: Define or directive not defined: \'`TRUE\'\n        if(set_cc_i == `TRUE && (E_icode_i == `OPQ || (E_icode_i == `IXX && E_ifun_i != `IRMOVQ)))\n                       ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:27: Define or directive not defined: \'`OPQ\'\n        if(set_cc_i == `TRUE && (E_icode_i == `OPQ || (E_icode_i == `IXX && E_ifun_i != `IRMOVQ)))\n                                              ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:27: Define or directive not defined: \'`IXX\'\n        if(set_cc_i == `TRUE && (E_icode_i == `OPQ || (E_icode_i == `IXX && E_ifun_i != `IRMOVQ)))\n                                                                    ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:27: Define or directive not defined: \'`IRMOVQ\'\n        if(set_cc_i == `TRUE && (E_icode_i == `OPQ || (E_icode_i == `IXX && E_ifun_i != `IRMOVQ)))\n                                                                                        ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:39: Define or directive not defined: \'`JXX\'\n        if(E_icode_i == `JXX || E_icode_i == `CXX)\n                        ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:39: Define or directive not defined: \'`CXX\'\n        if(E_icode_i == `JXX || E_icode_i == `CXX)\n                                             ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:42: Define or directive not defined: \'`JLE\'\n                    `JLE:      e_Cnd_o = ZF || (!SF && OF) || SF;\n                    ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:43: Define or directive not defined: \'`JL\'\n                     `JL:      e_Cnd_o = (!SF && OF) || SF;\n                     ^~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:44: Define or directive not defined: \'`JE\'\n                     `JE:      e_Cnd_o = ZF;\n                     ^~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:45: Define or directive not defined: \'`JNE\'\n                    `JNE:      e_Cnd_o = !ZF;\n                    ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:46: Define or directive not defined: \'`JGE\'\n                    `JGE:      e_Cnd_o = ZF || (SF && OF) || !SF;\n                    ^~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:47: Define or directive not defined: \'`JG\'\n                     `JG:      e_Cnd_o = (SF && OF) || !SF;\n                     ^~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:48: Define or directive not defined: \'`TRUE\'\n                     default:  e_Cnd_o = `TRUE;\n                                         ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:51: Define or directive not defined: \'`TRUE\'\n                if(e_Cnd_o == `TRUE)\n                              ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:54: Define or directive not defined: \'`NREG\'\n                    e_dstE_o = `NREG;\n                               ^~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/set_cond.v:59: Define or directive not defined: \'`TRUE\'\n                e_Cnd_o = `TRUE;\n                          ^~~~~\n%Error: Exiting due to 30 error(s)\n'
module set_cond(
    input wire set_cc_i,
    input wire [`ICODE_BUS] E_icode_i,
    input wire [`IFUN_BUS] E_ifun_i,
    input wire [`REG_ADDR_BUS] E_dstE_i,
    input wire ZF_i,
    input wire SF_i,
    input wire OF_i,
    
    output reg e_Cnd_o,
    output reg [`REG_ADDR_BUS] e_dstE_o
    );
    
    reg ZF, SF, OF;
    
    initial
    begin
        ZF = `FALSE;
        SF = `FALSE;
        OF = `FALSE;
    end
    
    always @(*)
    begin
        if(set_cc_i == `TRUE && (E_icode_i == `OPQ || (E_icode_i == `IXX && E_ifun_i != `IRMOVQ)))
            begin
                ZF = ZF_i;
                SF = SF_i;
                OF = OF_i;
            end
        else
            begin
                ZF = ZF;
                SF = SF;
                OF = OF;
            end
        if(E_icode_i == `JXX || E_icode_i == `CXX)
            begin
                case(E_ifun_i)
                    `JLE:      e_Cnd_o = ZF || (!SF && OF) || SF;
                     `JL:      e_Cnd_o = (!SF && OF) || SF;
                     `JE:      e_Cnd_o = ZF;
                    `JNE:      e_Cnd_o = !ZF;
                    `JGE:      e_Cnd_o = ZF || (SF && OF) || !SF;
                     `JG:      e_Cnd_o = (SF && OF) || !SF;
                     default:  e_Cnd_o = `TRUE;
                endcase
                    
                if(e_Cnd_o == `TRUE)
                    e_dstE_o = E_dstE_i;
                else
                    e_dstE_o = `NREG;
            end
        else
            begin
                e_dstE_o = E_dstE_i;
                e_Cnd_o = `TRUE;
            end
    end
endmodule
module set_cond(
    input wire set_cc_i,
    input wire [`ICODE_BUS] E_icode_i,
    input wire [`IFUN_BUS] E_ifun_i,
    input wire [`REG_ADDR_BUS] E_dstE_i,
    input wire ZF_i,
    input wire SF_i,
    input wire OF_i,
    
    output reg e_Cnd_o,
    output reg [`REG_ADDR_BUS] e_dstE_o
    );

    
    reg ZF, SF, OF;
    
    initial
    begin
        ZF = `FALSE;
        SF = `FALSE;
        OF = `FALSE;
    end
    
    always @(*)
    begin
        if(set_cc_i == `TRUE && (E_icode_i == `OPQ || (E_icode_i == `IXX && E_ifun_i != `IRMOVQ)))
            begin
                ZF = ZF_i;
                SF = SF_i;
                OF = OF_i;
            end
        else
            begin
                ZF = ZF;
                SF = SF;
                OF = OF;
            end
        if(E_icode_i == `JXX || E_icode_i == `CXX)
            begin
                case(E_ifun_i)
                    `JLE:      e_Cnd_o = ZF || (!SF && OF) || SF;
                     `JL:      e_Cnd_o = (!SF && OF) || SF;
                     `JE:      e_Cnd_o = ZF;
                    `JNE:      e_Cnd_o = !ZF;
                    `JGE:      e_Cnd_o = ZF || (SF && OF) || !SF;
                     `JG:      e_Cnd_o = (SF && OF) || !SF;
                     default:  e_Cnd_o = `TRUE;
                endcase
                    
                if(e_Cnd_o == `TRUE)
                    e_dstE_o = E_dstE_i;
                else
                    e_dstE_o = `NREG;
            end
        else
            begin
                e_dstE_o = E_dstE_i;
                e_Cnd_o = `TRUE;
            end
    end
endmodule