data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_サンプル回路/FPGA/FPGA_stopwatch/stop_watch.v
1: b"%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA/FPGA_stopwatch/stop_watch.v:51: Cannot find file containing module: 'ctrg_rmv'\n ctrg_rmv    ctrg_rmv1(\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA/FPGA_stopwatch,data/full_repos/permissive/183580645/ctrg_rmv\n             data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA/FPGA_stopwatch,data/full_repos/permissive/183580645/ctrg_rmv.v\n             data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA/FPGA_stopwatch,data/full_repos/permissive/183580645/ctrg_rmv.sv\n             ctrg_rmv\n             ctrg_rmv.v\n             ctrg_rmv.sv\n             obj_dir/ctrg_rmv\n             obj_dir/ctrg_rmv.v\n             obj_dir/ctrg_rmv.sv\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA/FPGA_stopwatch/stop_watch.v:62: Cannot find file containing module: 'time_manager'\n time_manager    time_manager1(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA/FPGA_stopwatch/stop_watch.v:72: Cannot find file containing module: 'watch_body'\n watch_body    watch_body1(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA/FPGA_stopwatch/stop_watch.v:87: Cannot find file containing module: 'time_display'\n time_display    time_display1(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA/FPGA_stopwatch/stop_watch.v:104: Cannot find file containing module: 'dynamic_display'\n dynamic_display dynamic_display1(\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module stop_watch (

                    CLK,
                    RSTN,


                    PSW,


                    SEG_A,
                    SEG_SEL
                    );


	input         CLK;
	input         RSTN;

	input  [3:0]  PSW;


	output [7:0]  SEG_A;


	output	[3:0]  SEG_SEL;


	wire	[3:0] PSW_SIG;

	wire	[3:0]	SEG_A_VAL;
	wire	[3:0]	SEG_B_VAL;
	wire	[3:0]	SEG_C_VAL;
	wire	[3:0]	SEG_D_VAL;

	wire	[3:0]	SEG_SEL;
	wire	[7:0]	SEG_A_0;
	wire	[7:0]	SEG_B_0;
	wire	[7:0]	SEG_C_0;
	wire	[7:0]	SEG_D_0;

	wire	SEC_SIG;


	ctrg_rmv    ctrg_rmv1(

                        .CLK(CLK),
                        .RSTN(RSTN),
                        .PSW(PSW),


                        .PSW_SIG(PSW_SIG)
                        );


	time_manager    time_manager1(

                        .CLK(CLK),
                        .RSTN(RSTN),


                        .SEC_SIG(SEC_SIG)
                        );


	watch_body    watch_body1(

                        .CLK(CLK),
                        .RSTN(RSTN),
			.SEC_SIG(SEC_SIG),
                        .PSW_SIG(PSW_SIG),
 

                        .SEG_A_VAL(SEG_A_VAL),
                        .SEG_B_VAL(SEG_B_VAL),
                        .SEG_C_VAL(SEG_C_VAL),
                        .SEG_D_VAL(SEG_D_VAL)
                        );


	time_display    time_display1(

                        .CLK(CLK),
                        .RSTN(RSTN),
                        .SEG_A_VAL(SEG_A_VAL),
                        .SEG_B_VAL(SEG_B_VAL),
                        .SEG_C_VAL(SEG_C_VAL),
                        .SEG_D_VAL(SEG_D_VAL),


                        .SEG_A(SEG_A_0),
                        .SEG_B(SEG_B_0),
                        .SEG_C(SEG_C_0),
                        .SEG_D(SEG_D_0)
                        );


	dynamic_display	dynamic_display1(

			.CLK(CLK),
			.RSTN(RSTN),
			.SEG_A_0(SEG_A_0),
			.SEG_B_0(SEG_B_0),
			.SEG_C_0(SEG_C_0),
			.SEG_D_0(SEG_D_0),


			.SEG_A(SEG_A),
			.SEG_SEL(SEG_SEL)
			);

endmodule
module stop_watch (

                    CLK,
                    RSTN,


                    PSW,


                    SEG_A,
                    SEG_SEL
                    );



	input         CLK;
	input         RSTN;

	input  [3:0]  PSW;


	output [7:0]  SEG_A;


	output	[3:0]  SEG_SEL;


	wire	[3:0] PSW_SIG;

	wire	[3:0]	SEG_A_VAL;
	wire	[3:0]	SEG_B_VAL;
	wire	[3:0]	SEG_C_VAL;
	wire	[3:0]	SEG_D_VAL;

	wire	[3:0]	SEG_SEL;
	wire	[7:0]	SEG_A_0;
	wire	[7:0]	SEG_B_0;
	wire	[7:0]	SEG_C_0;
	wire	[7:0]	SEG_D_0;

	wire	SEC_SIG;


	ctrg_rmv    ctrg_rmv1(

                        .CLK(CLK),
                        .RSTN(RSTN),
                        .PSW(PSW),


                        .PSW_SIG(PSW_SIG)
                        );


	time_manager    time_manager1(

                        .CLK(CLK),
                        .RSTN(RSTN),


                        .SEC_SIG(SEC_SIG)
                        );


	watch_body    watch_body1(

                        .CLK(CLK),
                        .RSTN(RSTN),
			.SEC_SIG(SEC_SIG),
                        .PSW_SIG(PSW_SIG),
 

                        .SEG_A_VAL(SEG_A_VAL),
                        .SEG_B_VAL(SEG_B_VAL),
                        .SEG_C_VAL(SEG_C_VAL),
                        .SEG_D_VAL(SEG_D_VAL)
                        );


	time_display    time_display1(

                        .CLK(CLK),
                        .RSTN(RSTN),
                        .SEG_A_VAL(SEG_A_VAL),
                        .SEG_B_VAL(SEG_B_VAL),
                        .SEG_C_VAL(SEG_C_VAL),
                        .SEG_D_VAL(SEG_D_VAL),


                        .SEG_A(SEG_A_0),
                        .SEG_B(SEG_B_0),
                        .SEG_C(SEG_C_0),
                        .SEG_D(SEG_D_0)
                        );


	dynamic_display	dynamic_display1(

			.CLK(CLK),
			.RSTN(RSTN),
			.SEG_A_0(SEG_A_0),
			.SEG_B_0(SEG_B_0),
			.SEG_C_0(SEG_C_0),
			.SEG_D_0(SEG_D_0),


			.SEG_A(SEG_A),
			.SEG_SEL(SEG_SEL)
			);

endmodule