data/full_repos/permissive/173670949/gtkwave/pwm.v
data/verilator_xmls/961d8d3d-9b0d-4808-be6a-d486eddb89fa.xml
module PWM (
    input       clk,
    input [7:0] level,
    output      out
);
    localparam WIDTH = 24;
    reg [WIDTH-1:0] counter = 0;


    always @(posedge clk) begin
        counter <= counter + 1;
    end


    assign out = (counter[7:0] > level);
endmodule
module PWM (
    input       clk,
    input [7:0] level,
    output      out
);

    localparam WIDTH = 24;
    reg [WIDTH-1:0] counter = 0;


    always @(posedge clk) begin
        counter <= counter + 1;
    end


    assign out = (counter[7:0] > level);
endmodule