data/full_repos/permissive/124844461/Lab1/DemultFrequency.v
data/verilator_xmls/09150a15-835f-4c1a-a0b7-8f3d102e1b2c.xml
module DemultFrequency (
    input Sys_Clk,
    input Fre_Choice,
    input rst_n,
    input stop_button,
    input halt,
    output reg Fra_Freq,
    output reg display_Freq,
    output reg [15:0] Cycles
);
    reg [31:0] m;
    reg [31:0] n;
    reg [31:0] k;
    reg [15:0] op_num;
    reg flag;
    initial 
    begin
        m = 32'd0;
        n = 32'd0;
        k = 32'd0;
        Fra_Freq = 0;
        display_Freq = 0;
        Cycles = 16'b0; 
        op_num = 16'b0;
        flag = 0;
    end
 
    always @(posedge Fra_Freq) begin
         if(rst_n)begin
             op_num<=0;
             flag<=0;
         end
         else begin     
         if(halt)begin
              op_num<=op_num+1;
         end
         case(halt)
             1'b0:
             if(flag==0)begin
                 Cycles<=op_num+1;
                flag<=1;
             end
             1'b1:Cycles<=op_num;
         endcase
    end
    end




    always @(posedge Sys_Clk)
    begin




        
        if(n == 32'd50_000) begin
            n = 32'd0;
            display_Freq = ~display_Freq;
        end else begin
            n = n+1;
        end
        

        if(Fre_Choice)
        begin
            if(!stop_button)
            begin
                if(m == 32'd1048575)
                begin 
                    m = 32'd0;
                    Fra_Freq = ~Fra_Freq;

                end
                else
                    m=m+1;
            end
        end
        else
        begin
            if(!stop_button)
            begin
                if(k == 32'd1)
                begin
                    Fra_Freq = ~Fra_Freq;

                    k = 32'd0;
                end
                else
				    k = k+1;
            end
        end
    end
endmodule
module DemultFrequency (
    input Sys_Clk,
    input Fre_Choice,
    input rst_n,
    input stop_button,
    input halt,
    output reg Fra_Freq,
    output reg display_Freq,
    output reg [15:0] Cycles
);

    reg [31:0] m;
    reg [31:0] n;
    reg [31:0] k;
    reg [15:0] op_num;
    reg flag;
    initial 
    begin
        m = 32'd0;
        n = 32'd0;
        k = 32'd0;
        Fra_Freq = 0;
        display_Freq = 0;
        Cycles = 16'b0; 
        op_num = 16'b0;
        flag = 0;
    end
 
    always @(posedge Fra_Freq) begin
         if(rst_n)begin
             op_num<=0;
             flag<=0;
         end
         else begin     
         if(halt)begin
              op_num<=op_num+1;
         end
         case(halt)
             1'b0:
             if(flag==0)begin
                 Cycles<=op_num+1;
                flag<=1;
             end
             1'b1:Cycles<=op_num;
         endcase
    end
    end




    always @(posedge Sys_Clk)
    begin




        
        if(n == 32'd50_000) begin
            n = 32'd0;
            display_Freq = ~display_Freq;
        end else begin
            n = n+1;
        end
        

        if(Fre_Choice)
        begin
            if(!stop_button)
            begin
                if(m == 32'd1048575)
                begin 
                    m = 32'd0;
                    Fra_Freq = ~Fra_Freq;

                end
                else
                    m=m+1;
            end
        end
        else
        begin
            if(!stop_button)
            begin
                if(k == 32'd1)
                begin
                    Fra_Freq = ~Fra_Freq;

                    k = 32'd0;
                end
                else
				    k = k+1;
            end
        end
    end
endmodule