data/full_repos/permissive/135475029/lab_9/src/MIPS.v
1: b"%Error: data/full_repos/permissive/135475029/lab_9/src/MIPS.v:93: Cannot find file containing module: 'InstructionMemory'\n  InstructionMemory i_imem (\n  ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135475029/lab_9/src,data/full_repos/permissive/135475029/InstructionMemory\n             data/full_repos/permissive/135475029/lab_9/src,data/full_repos/permissive/135475029/InstructionMemory.v\n             data/full_repos/permissive/135475029/lab_9/src,data/full_repos/permissive/135475029/InstructionMemory.sv\n             InstructionMemory\n             InstructionMemory.v\n             InstructionMemory.sv\n             obj_dir/InstructionMemory\n             obj_dir/InstructionMemory.v\n             obj_dir/InstructionMemory.sv\n%Error: data/full_repos/permissive/135475029/lab_9/src/MIPS.v:106: Cannot find file containing module: 'RegisterFile'\n  RegisterFile i_regf (\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/135475029/lab_9/src/MIPS.v:125: Cannot find file containing module: 'ALU'\n  ALU i_alu (\n  ^~~\n%Error: data/full_repos/permissive/135475029/lab_9/src/MIPS.v:143: Cannot find file containing module: 'DataMemory'\n  DataMemory i_dmem (\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/135475029/lab_9/src/MIPS.v:156: Cannot find file containing module: 'ControlUnit'\n  ControlUnit i_cont (\n  ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module MIPS(
  input CLK,
  input RESET,
  output [31:0] DATA,
  output [31:0] ADDRESS
 );











  wire [31:0] Instr;
  wire [31:0] SignImm;
  wire  [4:0] WriteReg;


  reg  [31:0] PC;
  wire [31:0] PCbar;
  wire [31:0] PCCalc;
  wire [31:0] PCJump;
  wire [31:0] PCBranch;
  wire [31:0] PCPlus4;


  wire [31:0] SrcA;
  wire [31:0] SrcB;
  wire [31:0] ALUResult;
  wire        Zero;


  wire [31:0] WriteData;
  wire [31:0] ReadData;
  wire [31:0] Result;
  wire        MemWrite;


  wire        Jump;
  wire        MemtoReg;
  wire        Branch;
  wire        PCSrc;
  wire  [5:0] ALUControl;
  wire        ALUSrc;
  wire        RegDst;
  wire        RegWrite;







  always @ ( posedge CLK, posedge RESET )
    if(RESET == 1'b1)
      PC <= 32'h00002FFC;
    else
      PC <= PCbar;


  assign PCPlus4 = PC + 4;
  assign PCBranch = PCPlus4 + {SignImm[29:0],2'b00};
  assign PCCalc = PCSrc ? PCBranch : PCPlus4;
  assign PCJump = {PCPlus4[31:28], Instr[25:0], 2'b00};
  assign PCbar = Jump  ? PCJump   : PCCalc;



  InstructionMemory i_imem (
    .A(PC[7:2]),
    .RD(Instr)
   );


  assign SignImm = {{16{Instr[15]}},Instr[15:0]};


  assign WriteReg = RegDst ? Instr[15:11] : Instr[20:16];



  RegisterFile i_regf (
    .A1(Instr[25:21]),
    .A2(Instr[20:16]),
    .A3(WriteReg),
    .RD1(SrcA),
    .RD2(WriteData),
    .WD3(Result),
    .WE3(RegWrite),
    .CLK(CLK)
   );




  assign SrcB = ALUSrc ? SignImm : WriteData ;




  ALU i_alu (
    .CLK(CLK),
    .RESET(RESET),
    .a(SrcA),
    .b(SrcB),
    .aluop(ALUControl[5:0]),
    .shAmt(Instr[4:0]),
    .result(ALUResult),
    .zero(Zero)
   );




  assign PCSrc = Branch & Zero;



  DataMemory i_dmem (
    .CLK(CLK),
    .A(ALUResult[7:2]),
    .WE(MemWrite),
    .WD(WriteData),
    .RD(ReadData)
   );


  assign Result = MemtoReg ? ReadData : ALUResult;



  ControlUnit i_cont (
    .Op(Instr[31:26]),
    .Funct(Instr[5:0]),
    .Jump(Jump),
    .MemtoReg(MemtoReg),
    .MemWrite(MemWrite),
    .Branch(Branch),
    .ALUControl(ALUControl),
    .ALUSrc(ALUSrc),
    .RegDst(RegDst),
    .RegWrite(RegWrite)
   );


  assign ADDRESS = PC;
  assign DATA    = Result;

endmodule
module MIPS(
  input CLK,
  input RESET,
  output [31:0] DATA,
  output [31:0] ADDRESS
 );












  wire [31:0] Instr;
  wire [31:0] SignImm;
  wire  [4:0] WriteReg;


  reg  [31:0] PC;
  wire [31:0] PCbar;
  wire [31:0] PCCalc;
  wire [31:0] PCJump;
  wire [31:0] PCBranch;
  wire [31:0] PCPlus4;


  wire [31:0] SrcA;
  wire [31:0] SrcB;
  wire [31:0] ALUResult;
  wire        Zero;


  wire [31:0] WriteData;
  wire [31:0] ReadData;
  wire [31:0] Result;
  wire        MemWrite;


  wire        Jump;
  wire        MemtoReg;
  wire        Branch;
  wire        PCSrc;
  wire  [5:0] ALUControl;
  wire        ALUSrc;
  wire        RegDst;
  wire        RegWrite;







  always @ ( posedge CLK, posedge RESET )
    if(RESET == 1'b1)
      PC <= 32'h00002FFC;
    else
      PC <= PCbar;


  assign PCPlus4 = PC + 4;
  assign PCBranch = PCPlus4 + {SignImm[29:0],2'b00};
  assign PCCalc = PCSrc ? PCBranch : PCPlus4;
  assign PCJump = {PCPlus4[31:28], Instr[25:0], 2'b00};
  assign PCbar = Jump  ? PCJump   : PCCalc;



  InstructionMemory i_imem (
    .A(PC[7:2]),
    .RD(Instr)
   );


  assign SignImm = {{16{Instr[15]}},Instr[15:0]};


  assign WriteReg = RegDst ? Instr[15:11] : Instr[20:16];



  RegisterFile i_regf (
    .A1(Instr[25:21]),
    .A2(Instr[20:16]),
    .A3(WriteReg),
    .RD1(SrcA),
    .RD2(WriteData),
    .WD3(Result),
    .WE3(RegWrite),
    .CLK(CLK)
   );




  assign SrcB = ALUSrc ? SignImm : WriteData ;




  ALU i_alu (
    .CLK(CLK),
    .RESET(RESET),
    .a(SrcA),
    .b(SrcB),
    .aluop(ALUControl[5:0]),
    .shAmt(Instr[4:0]),
    .result(ALUResult),
    .zero(Zero)
   );




  assign PCSrc = Branch & Zero;



  DataMemory i_dmem (
    .CLK(CLK),
    .A(ALUResult[7:2]),
    .WE(MemWrite),
    .WD(WriteData),
    .RD(ReadData)
   );


  assign Result = MemtoReg ? ReadData : ALUResult;



  ControlUnit i_cont (
    .Op(Instr[31:26]),
    .Funct(Instr[5:0]),
    .Jump(Jump),
    .MemtoReg(MemtoReg),
    .MemWrite(MemWrite),
    .Branch(Branch),
    .ALUControl(ALUControl),
    .ALUSrc(ALUSrc),
    .RegDst(RegDst),
    .RegWrite(RegWrite)
   );


  assign ADDRESS = PC;
  assign DATA    = Result;

endmodule