data/full_repos/permissive/208556773/testbench/spi_tb.v
1: b"%Error: data/full_repos/permissive/208556773/testbench/spi_tb.v:56: Duplicate declaration of signal: 'COPI_tx'\n                                                                  : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire COPI_tx;\n       ^~~~~~~\n        data/full_repos/permissive/208556773/testbench/spi_tb.v:25: ... Location of original declaration\n    output COPI_tx,\n           ^~~~~~~\n%Error: data/full_repos/permissive/208556773/testbench/spi_tb.v:60: Duplicate declaration of signal: 'word_data_received'\n  reg [SPIBITS-1:0] word_data_received;\n                    ^~~~~~~~~~~~~~~~~~\n        data/full_repos/permissive/208556773/testbench/spi_tb.v:24: ... Location of original declaration\n    output reg [SPIBITS-1:0] word_data_received,\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/208556773/testbench/spi_tb.v:61: Duplicate declaration of signal: 'word_send_data'\n  reg [SPIBITS-1:0] word_send_data;\n                    ^~~~~~~~~~~~~~\n        data/full_repos/permissive/208556773/testbench/spi_tb.v:22: ... Location of original declaration\n    output reg [SPIBITS-1:0] word_send_data,\n                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/208556773/testbench/spi_tb.v:96: Duplicate declaration of signal: 'bit_count'\n  reg [3:0] bit_count = 4'b0;\n            ^~~~~~~~~\n        data/full_repos/permissive/208556773/testbench/spi_tb.v:26: ... Location of original declaration\n    output [3:0] bit_count,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/208556773/testbench/spi_tb.v:97: Duplicate declaration of signal: 'byte_count'\n  reg [3:0] byte_count = 4'b0;\n            ^~~~~~~~~~\n        data/full_repos/permissive/208556773/testbench/spi_tb.v:27: ... Location of original declaration\n    output [3:0] byte_count\n                 ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module testbench #(parameter SPIBITS = 32)(
    input             clk,
    output reg [SPIBITS-1:0] word_send_data,
    output            word_received,
    output reg [SPIBITS-1:0] word_data_received,
    output COPI_tx,
    output [3:0] bit_count,
    output [3:0] byte_count
  );

  parameter NUMWORDS = 3;
  localparam NUMBYTES = SPIBITS/8;

  reg CS = 0;
  wire CIPO;


  reg [1:0] SCK_r = 0;
  wire SCK;
  assign SCK = (SCK_r == 2'b11 || SCK_r == 2'b10);

  reg initialized = 0;
  wire resetn;
  reg [7:0] resetn_counter = 0;
  assign resetn = (resetn_counter == 8'hff);
  always @(posedge clk) begin
    if (!resetn) resetn_counter <= resetn_counter + 1'b1;
  end
  always @(posedge clk) begin
    if (resetn) begin
      SCK_r <= SCK_r + 1'b1;
      if(SCK_r == 2'b11) initialized <= 1;
    end
  end


  wire COPI_tx;
  assign COPI_tx = (SCK_r == 2'b01) && initialized;


  reg [SPIBITS-1:0] word_data_received;
  reg [SPIBITS-1:0] word_send_data;


  reg [SPIBITS-1:0] word_data_mem [NUMWORDS-1:0];
  reg [SPIBITS-1:0] word_data_tb;
  reg [7:0] tx_byte;


  SPIWord #(.bits(SPIBITS)) word_proc (
                .clk(clk),
                .resetn(resetn),
                .SCK(SCK),
                .CS(CS),
                .COPI(COPI),
                .CIPO(CIPO),
                .word_send_data(word_send_data),
                .word_received(word_received),
                .word_data_received(word_data_received));

  initial begin
    if (SPIBITS == 64) begin
      word_send_data = 64'h00000000005fffff;
      word_data_mem[0] = 64'hbeefdeaddeadbeef;
      word_data_mem[1] = 64'h00000000005fffff;
      word_data_mem[2] = 64'h00000110a0000000;
    end else if (SPIBITS == 32) begin
      word_send_data = 32'h005fffff;
      word_data_mem[0] = 32'hdeadbeef;
      word_data_mem[1] = 32'h005fffff;
      word_data_mem[2] = 32'ha0000000;
    end
    word_data_tb = word_data_mem[0];
    tx_byte = word_data_tb[7:0];
  end

  reg [3:0] bit_count = 4'b0;
  reg [3:0] byte_count = 4'b0;
  reg [3:0] word_count = 4'b0;
  wire COPI = tx_byte[7];


  always @(posedge COPI_tx) begin
    tx_byte = {tx_byte[6:0], 1'b0};
    bit_count = bit_count + 1'b1;
    if (bit_count == 4'b1000) begin
      word_data_tb = {8'b0, word_data_tb[SPIBITS-1:8]};
      tx_byte = word_data_tb[7:0];
      bit_count = 4'b0;
      byte_count = byte_count + 1'b1;
      if (byte_count == NUMBYTES) begin
        word_count = word_count + 1'b1;
        if (word_count <= NUMWORDS-1) begin
          word_data_tb = word_data_mem[word_count];
        end else begin
          CS <= 1;
        end
        byte_count = 8'b0;
      end
    end
  end

endmodule
module testbench #(parameter SPIBITS = 32)(
    input             clk,
    output reg [SPIBITS-1:0] word_send_data,
    output            word_received,
    output reg [SPIBITS-1:0] word_data_received,
    output COPI_tx,
    output [3:0] bit_count,
    output [3:0] byte_count
  );


  parameter NUMWORDS = 3;
  localparam NUMBYTES = SPIBITS/8;

  reg CS = 0;
  wire CIPO;


  reg [1:0] SCK_r = 0;
  wire SCK;
  assign SCK = (SCK_r == 2'b11 || SCK_r == 2'b10);

  reg initialized = 0;
  wire resetn;
  reg [7:0] resetn_counter = 0;
  assign resetn = (resetn_counter == 8'hff);
  always @(posedge clk) begin
    if (!resetn) resetn_counter <= resetn_counter + 1'b1;
  end
  always @(posedge clk) begin
    if (resetn) begin
      SCK_r <= SCK_r + 1'b1;
      if(SCK_r == 2'b11) initialized <= 1;
    end
  end


  wire COPI_tx;
  assign COPI_tx = (SCK_r == 2'b01) && initialized;


  reg [SPIBITS-1:0] word_data_received;
  reg [SPIBITS-1:0] word_send_data;


  reg [SPIBITS-1:0] word_data_mem [NUMWORDS-1:0];
  reg [SPIBITS-1:0] word_data_tb;
  reg [7:0] tx_byte;


  SPIWord #(.bits(SPIBITS)) word_proc (
                .clk(clk),
                .resetn(resetn),
                .SCK(SCK),
                .CS(CS),
                .COPI(COPI),
                .CIPO(CIPO),
                .word_send_data(word_send_data),
                .word_received(word_received),
                .word_data_received(word_data_received));

  initial begin
    if (SPIBITS == 64) begin
      word_send_data = 64'h00000000005fffff;
      word_data_mem[0] = 64'hbeefdeaddeadbeef;
      word_data_mem[1] = 64'h00000000005fffff;
      word_data_mem[2] = 64'h00000110a0000000;
    end else if (SPIBITS == 32) begin
      word_send_data = 32'h005fffff;
      word_data_mem[0] = 32'hdeadbeef;
      word_data_mem[1] = 32'h005fffff;
      word_data_mem[2] = 32'ha0000000;
    end
    word_data_tb = word_data_mem[0];
    tx_byte = word_data_tb[7:0];
  end

  reg [3:0] bit_count = 4'b0;
  reg [3:0] byte_count = 4'b0;
  reg [3:0] word_count = 4'b0;
  wire COPI = tx_byte[7];


  always @(posedge COPI_tx) begin
    tx_byte = {tx_byte[6:0], 1'b0};
    bit_count = bit_count + 1'b1;
    if (bit_count == 4'b1000) begin
      word_data_tb = {8'b0, word_data_tb[SPIBITS-1:8]};
      tx_byte = word_data_tb[7:0];
      bit_count = 4'b0;
      byte_count = byte_count + 1'b1;
      if (byte_count == NUMBYTES) begin
        word_count = word_count + 1'b1;
        if (word_count <= NUMWORDS-1) begin
          word_data_tb = word_data_mem[word_count];
        end else begin
          CS <= 1;
        end
        byte_count = 8'b0;
      end
    end
  end

endmodule