data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/register_file.v
None: at end of input
data/verilator_xmls/7a8f1884-4ced-4bfc-b62f-64ea7e307dea.xml
module register_file(input clk, input [4:0] read_reg1, input [4:0] read_reg2, input [4:0] write_reg, input write_en,
                        input [31:0] write_data, output [31:0] read_data1, output [31:0] read_data2);
                    
    reg [31:0] registers [0:31];
    





    


    always@(posedge clk) begin
        registers[0]=32'b0;
        if(write_en) registers[write_reg] = write_data;
    end
    


    assign read_data1 = registers[read_reg1];
    assign read_data2 = registers[read_reg2];

endmodule
module register_file(input clk, input [4:0] read_reg1, input [4:0] read_reg2, input [4:0] write_reg, input write_en,
                        input [31:0] write_data, output [31:0] read_data1, output [31:0] read_data2);

                    
    reg [31:0] registers [0:31];
    





    


    always@(posedge clk) begin
        registers[0]=32'b0;
        if(write_en) registers[write_reg] = write_data;
    end
    


    assign read_data1 = registers[read_reg1];
    assign read_data2 = registers[read_reg2];

endmodule