data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/IPCore/AT510-MN-80001-r2p0-00rel0/systems/fpga_testbench/verilog/GS8160Z36DT.v
'utf-8' codec can't decode byte 0xa9 in position 14: invalid start byte
1: b'%Error: data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/IPCore/AT510-MN-80001-r2p0-00rel0/systems/fpga_testbench/verilog/GS8160Z36DT.v:61: Cannot find include file: core.v\n`include  "core.v" \n          ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/IPCore/AT510-MN-80001-r2p0-00rel0/systems/fpga_testbench/verilog,data/full_repos/permissive/194847941/core.v\n             data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/IPCore/AT510-MN-80001-r2p0-00rel0/systems/fpga_testbench/verilog,data/full_repos/permissive/194847941/core.v.v\n             data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/IPCore/AT510-MN-80001-r2p0-00rel0/systems/fpga_testbench/verilog,data/full_repos/permissive/194847941/core.v.sv\n             core.v\n             core.v.v\n             core.v.sv\n             obj_dir/core.v\n             obj_dir/core.v.v\n             obj_dir/core.v.sv\n%Error: Exiting due to 1 error(s)\n'
module GS8160Z36DT  #(
        parameter SPEED = 300,
                              A_bits = 19
)
(A, CK, nBa, nBb, nBc, nBd, nW, nE1, E2, nE3, nG, pADV,
      nCKE, DQa, DQb, DQc, DQd, ZZ, nFT, nLBO);


  parameter  A_size     = 19,
      DQ_size   = 9,
    bank_size   = 2**A_bits;

  input  [A_size-1:0]    A;
  input        CK;
  input        nBa;
  input        nBb;
  input        nBc;
  input        nBd;
  input        nW;
  input        nE1;
  input        E2;
  input        nE3;
  input        nG;
  input        pADV;
  input        nCKE;
  inout  [DQ_size-1:0]    DQa;
  inout  [DQ_size-1:0]    DQb;
  inout  [DQ_size-1:0]    DQc;
  inout  [DQ_size-1:0]    DQd;
  input        ZZ;
  input        nFT;
  input        nLBO;
  wire        TMS;
  wire        TDI;
  wire        TDO;
  wire        TCK;

  wire                      nBe = 1,
          nBf = 1,
          nBg = 1,
          nBh = 1;
  wire    [8:0]             DQe,
          DQf,
          DQg,
          DQh;

   parameter       tKQ_pipe  = (SPEED==400 | SPEED==375 | SPEED==333 | SPEED==250) ? 2.5 : SPEED==200 ? 3.0 : 3.8;
   parameter       tKQ_flow  = SPEED==400 ? 4.0 : SPEED==375 ? 4.2 : SPEED==333 ? 4.5: SPEED==250 ? 5.5 : SPEED==200 ? 6.5 : 7.5;
   parameter       tKQX_pipe = 1.5;
   parameter       tKQX_flow = 2.0;

   assign       tKQ  = nFT ? tKQ_pipe : tKQ_flow;
   assign       tKQX = nFT ? tKQX_pipe : tKQX_flow;
       
`include  "core.v"

endmodule
module GS8160Z36DT  #(
        parameter SPEED = 300,
                              A_bits = 19
)
(A, CK, nBa, nBb, nBc, nBd, nW, nE1, E2, nE3, nG, pADV,
      nCKE, DQa, DQb, DQc, DQd, ZZ, nFT, nLBO);



  parameter  A_size     = 19,
      DQ_size   = 9,
    bank_size   = 2**A_bits;

  input  [A_size-1:0]    A;
  input        CK;
  input        nBa;
  input        nBb;
  input        nBc;
  input        nBd;
  input        nW;
  input        nE1;
  input        E2;
  input        nE3;
  input        nG;
  input        pADV;
  input        nCKE;
  inout  [DQ_size-1:0]    DQa;
  inout  [DQ_size-1:0]    DQb;
  inout  [DQ_size-1:0]    DQc;
  inout  [DQ_size-1:0]    DQd;
  input        ZZ;
  input        nFT;
  input        nLBO;
  wire        TMS;
  wire        TDI;
  wire        TDO;
  wire        TCK;

  wire                      nBe = 1,
          nBf = 1,
          nBg = 1,
          nBh = 1;
  wire    [8:0]             DQe,
          DQf,
          DQg,
          DQh;

   parameter       tKQ_pipe  = (SPEED==400 | SPEED==375 | SPEED==333 | SPEED==250) ? 2.5 : SPEED==200 ? 3.0 : 3.8;
   parameter       tKQ_flow  = SPEED==400 ? 4.0 : SPEED==375 ? 4.2 : SPEED==333 ? 4.5: SPEED==250 ? 5.5 : SPEED==200 ? 6.5 : 7.5;
   parameter       tKQX_pipe = 1.5;
   parameter       tKQX_flow = 2.0;

   assign       tKQ  = nFT ? tKQ_pipe : tKQ_flow;
   assign       tKQX = nFT ? tKQX_pipe : tKQX_flow;
       
`include  "core.v"

endmodule