data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v:8: Cannot find include file: cpu.v\n`include "cpu.v"        // cpu.v            \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/cpu.v\n             data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/cpu.v.v\n             data/full_repos/permissive/107499099/mips_de2-115/MIPS,data/full_repos/permissive/107499099/cpu.v.sv\n             cpu.v\n             cpu.v.v\n             cpu.v.sv\n             obj_dir/cpu.v\n             obj_dir/cpu.v.v\n             obj_dir/cpu.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v:61: Unsupported: Ignoring delay on this delayed statement.\n       #20  reset = 0;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v:64: Unsupported: Ignoring delay on this delayed statement.\n       #20  reset = 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v:66: Unsupported: Ignoring delay on this delayed statement.\n       #100000 $finish;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v:70: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk = ! clk;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/107499099/mips_de2-115/MIPS/test_cpu.v:74: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk_ctrl_clk = ! clk_ctrl_clk;\n     ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module test_cpu ;

   reg clk;
   reg reset;
   reg clk_ctrl0;
   reg clk_ctrl1;
   reg clk_ctrl_clk;
   reg [12:0] i_ram_addr;
   reg [31:0] i_ram_wdata;
   reg        i_ram_wen;


   wire o_clock;
   wire [7:0] o_pc;
   wire [31:0] o_alu_y;
   wire [31:0]     o_alu_a;
   wire [31:0]     o_alu_b;
   wire [3:0]   o_alu_ctrl;
   wire [1:0]   o_alu_comp;
   wire [31:0] o_reg_data1;
   wire [4:0]   o_reg_idx1;
   wire [31:0] o_reg_data2;
   wire [4:0]   o_reg_idx2;
   wire [31:0] o_reg_wdata;
   wire [4:0]   o_reg_widx;
   wire          o_reg_wen;
   wire [12:0]  o_ram_addr;
   wire [31:0] o_ram_rdata;
   wire [31:0] o_ram_wdata;
   wire          o_ram_wen;


   cpu cpua (clk, reset,
            clk_ctrl0, clk_ctrl1, clk_ctrl_clk,
            o_clock, o_pc, o_alu_y, o_alu_a, o_alu_b, o_alu_ctrl, o_alu_comp,
            o_reg_data1, o_reg_idx1, o_reg_data2, o_reg_idx2, o_reg_wdata,
            o_reg_widx, o_reg_wen,
            o_ram_addr, o_ram_rdata, o_ram_wdata, o_ram_wen,
            i_ram_addr, i_ram_wdata, i_ram_wen
            );

   

   initial begin

       clk = 0; reset = 1;

       clk_ctrl0 = 1; clk_ctrl1 = 1;
       clk_ctrl_clk = 0;


       #20  reset = 0;


       #20  reset = 1;

       #100000 $finish;
   end

   always begin
     #10 clk = ! clk;
   end

   always begin
     #10 clk_ctrl_clk = ! clk_ctrl_clk;
   end

endmodule
module test_cpu ;


   reg clk;
   reg reset;
   reg clk_ctrl0;
   reg clk_ctrl1;
   reg clk_ctrl_clk;
   reg [12:0] i_ram_addr;
   reg [31:0] i_ram_wdata;
   reg        i_ram_wen;


   wire o_clock;
   wire [7:0] o_pc;
   wire [31:0] o_alu_y;
   wire [31:0]     o_alu_a;
   wire [31:0]     o_alu_b;
   wire [3:0]   o_alu_ctrl;
   wire [1:0]   o_alu_comp;
   wire [31:0] o_reg_data1;
   wire [4:0]   o_reg_idx1;
   wire [31:0] o_reg_data2;
   wire [4:0]   o_reg_idx2;
   wire [31:0] o_reg_wdata;
   wire [4:0]   o_reg_widx;
   wire          o_reg_wen;
   wire [12:0]  o_ram_addr;
   wire [31:0] o_ram_rdata;
   wire [31:0] o_ram_wdata;
   wire          o_ram_wen;


   cpu cpua (clk, reset,
            clk_ctrl0, clk_ctrl1, clk_ctrl_clk,
            o_clock, o_pc, o_alu_y, o_alu_a, o_alu_b, o_alu_ctrl, o_alu_comp,
            o_reg_data1, o_reg_idx1, o_reg_data2, o_reg_idx2, o_reg_wdata,
            o_reg_widx, o_reg_wen,
            o_ram_addr, o_ram_rdata, o_ram_wdata, o_ram_wen,
            i_ram_addr, i_ram_wdata, i_ram_wen
            );

   

   initial begin

       clk = 0; reset = 1;

       clk_ctrl0 = 1; clk_ctrl1 = 1;
       clk_ctrl_clk = 0;


       #20  reset = 0;


       #20  reset = 1;

       #100000 $finish;
   end

   always begin
     #10 clk = ! clk;
   end

   always begin
     #10 clk_ctrl_clk = ! clk_ctrl_clk;
   end

endmodule