data/full_repos/permissive/136009613/memory_tb.v
 line:98: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = !clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/memory_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Error: data/full_repos/permissive/136009613/memory_tb.v:7: Cannot find file containing module: \'memory\'\n memory memory1(clk, reset, address_dec, address_test, data_in, data_out, rwn, start);\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136009613,data/full_repos/permissive/136009613/memory\n             data/full_repos/permissive/136009613,data/full_repos/permissive/136009613/memory.v\n             data/full_repos/permissive/136009613,data/full_repos/permissive/136009613/memory.sv\n             memory\n             memory.v\n             memory.sv\n             obj_dir/memory\n             obj_dir/memory.v\n             obj_dir/memory.sv\n%Error: Exiting due to 1 error(s), 34 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_tb;
	reg [15:0] address_dec;
	reg [15:0] address_test;
	reg [31:0] data_in;
	reg start, clk, reset, rwn;
	wire [31:0] data_out;
	memory memory1(clk, reset, address_dec, address_test, data_in, data_out, rwn, start);
	initial begin
		start = 1;
		reset = 1;
		rwn = 0;
		clk = 0;
	end
	always #5 clk = !clk;
	initial begin
		#1
		address_dec = 16'h0000;
		data_in = 32'h00000000;
		#20
		address_dec = 16'h0001;
		data_in = 32'h11111111;
		#20
		address_dec = 16'h0002;
		data_in = 32'h22222222;
		#20
		address_dec = 16'h0003;
		data_in = 32'h33333333;
		#20
		address_dec = 16'h0004;
		data_in = 32'h44444444;
		#20
		address_dec = 16'h0005;
		data_in = 32'h55555555;
		#20
		address_dec = 16'h0006;
		data_in = 32'h66666666;
		#20
		address_dec = 16'h0007;
		data_in = 32'h77777777;
		#20
		address_dec = 16'h0008;
		data_in = 32'h88888888;
		#20
		address_dec = 16'h0009;
		data_in = 32'h99999999;
		#20
		address_dec = 16'h000A;
		data_in = 32'hAAAAAAAA;
		#20
		address_dec = 16'h000B;
		data_in = 32'hBBBBBBBB;
		#20
		address_dec = 16'h000C;
		data_in = 32'hCCCCCCCC;
		#20
		address_dec = 16'h000D;
		data_in = 32'hDDDDDDDD;
		#20
		address_dec = 16'h000E;
		data_in = 32'hEEEEEEEE;
		#20
		address_dec = 16'h000F;
		data_in = 32'hFFFFFFFF;
		#20
		rwn = 1;
		address_test = 16'h0000;
		#20
		address_test = 16'h0001;
		#20
		address_test = 16'h0002;
		#20
		address_test = 16'h0003;
		#20
		address_test = 16'h0004;
		#20
		address_test = 16'h0005;
		#20
		address_test = 16'h0006;
		#20
		address_test = 16'h0007;
		#20
		address_test = 16'h0008;
		#20
		address_test = 16'h0009;
		#20
		address_test = 16'h000A;
		#20
		address_test = 16'h000B;
		#20
		address_test = 16'h000C;
		#20
		address_test = 16'h000D;
		#20
		address_test = 16'h000E;
		#20
		address_test = 16'h000F;
		#20
		$stop;
	end
endmodule
module memory_tb;

	reg [15:0] address_dec;
	reg [15:0] address_test;
	reg [31:0] data_in;
	reg start, clk, reset, rwn;
	wire [31:0] data_out;
	memory memory1(clk, reset, address_dec, address_test, data_in, data_out, rwn, start);
	initial begin
		start = 1;
		reset = 1;
		rwn = 0;
		clk = 0;
	end
	always #5 clk = !clk;
	initial begin
		#1
		address_dec = 16'h0000;
		data_in = 32'h00000000;
		#20
		address_dec = 16'h0001;
		data_in = 32'h11111111;
		#20
		address_dec = 16'h0002;
		data_in = 32'h22222222;
		#20
		address_dec = 16'h0003;
		data_in = 32'h33333333;
		#20
		address_dec = 16'h0004;
		data_in = 32'h44444444;
		#20
		address_dec = 16'h0005;
		data_in = 32'h55555555;
		#20
		address_dec = 16'h0006;
		data_in = 32'h66666666;
		#20
		address_dec = 16'h0007;
		data_in = 32'h77777777;
		#20
		address_dec = 16'h0008;
		data_in = 32'h88888888;
		#20
		address_dec = 16'h0009;
		data_in = 32'h99999999;
		#20
		address_dec = 16'h000A;
		data_in = 32'hAAAAAAAA;
		#20
		address_dec = 16'h000B;
		data_in = 32'hBBBBBBBB;
		#20
		address_dec = 16'h000C;
		data_in = 32'hCCCCCCCC;
		#20
		address_dec = 16'h000D;
		data_in = 32'hDDDDDDDD;
		#20
		address_dec = 16'h000E;
		data_in = 32'hEEEEEEEE;
		#20
		address_dec = 16'h000F;
		data_in = 32'hFFFFFFFF;
		#20
		rwn = 1;
		address_test = 16'h0000;
		#20
		address_test = 16'h0001;
		#20
		address_test = 16'h0002;
		#20
		address_test = 16'h0003;
		#20
		address_test = 16'h0004;
		#20
		address_test = 16'h0005;
		#20
		address_test = 16'h0006;
		#20
		address_test = 16'h0007;
		#20
		address_test = 16'h0008;
		#20
		address_test = 16'h0009;
		#20
		address_test = 16'h000A;
		#20
		address_test = 16'h000B;
		#20
		address_test = 16'h000C;
		#20
		address_test = 16'h000D;
		#20
		address_test = 16'h000E;
		#20
		address_test = 16'h000F;
		#20
		$stop;
	end
endmodule