data/full_repos/permissive/128659832/verilog/IR.v
 line:16 column:20: Illegal character "'"
data/verilator_xmls/12598835-c102-4c6a-83ff-1c7d8b7c515d.xml
module IR (
        input clk,
        input [7:0] nIR,

        input wIR,
        input rst,

        output reg [7:0] rIR
    );

    always @(posedge clk) begin
        if(rst)
          rIR <= 8'b 0;
        else
          if(wIR) begin
            rIR <= nIR;
          end
    end

endmodule
module IR (
        input clk,
        input [7:0] nIR,

        input wIR,
        input rst,

        output reg [7:0] rIR
    );


    always @(posedge clk) begin
        if(rst)
          rIR <= 8'b 0;
        else
          if(wIR) begin
            rIR <= nIR;
          end
    end

endmodule