data/full_repos/permissive/19340845/src/DecodeUnitRegisterThree.v
data/verilator_xmls/d8753436-8768-463d-a2f0-5965819ec250.xml
module DecodeUnitRegisterThree(
   input        CLK,
   input [2:0]  writeAd_IN,
   input        ADR_MUX_IN, write_IN, PC_load_IN,
   output [2:0] writeAd_OUT,
   output       ADR_MUX_OUT, write_OUT, PC_load_OUT);

   reg [2:0]    writeAd;
   reg          adrmux, write, pcload;

   always @ (posedge CLK) begin
      writeAd <= writeAd_IN;
      adrmux <= ADR_MUX_IN;
      write <= write_IN;
      pcload <= PC_load_IN;
   end
   
   assign writeAd_OUT = writeAd;
   assign ADR_MUX_OUT = adrmux;
   assign write_OUT = write;
   assign PC_load_OUT = pcload;
   
   
endmodule
module DecodeUnitRegisterThree(
   input        CLK,
   input [2:0]  writeAd_IN,
   input        ADR_MUX_IN, write_IN, PC_load_IN,
   output [2:0] writeAd_OUT,
   output       ADR_MUX_OUT, write_OUT, PC_load_OUT);


   reg [2:0]    writeAd;
   reg          adrmux, write, pcload;

   always @ (posedge CLK) begin
      writeAd <= writeAd_IN;
      adrmux <= ADR_MUX_IN;
      write <= write_IN;
      pcload <= PC_load_IN;
   end
   
   assign writeAd_OUT = writeAd;
   assign ADR_MUX_OUT = adrmux;
   assign write_OUT = write;
   assign PC_load_OUT = pcload;
   
   
endmodule