data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/fixed_adder.v
None: at end of input
1: b'%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/fixed_adder.v:22: Cannot find include file: common.h\n`include "common.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h.v\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h.sv\n             common.h\n             common.h.v\n             common.h.sv\n             obj_dir/common.h\n             obj_dir/common.h.v\n             obj_dir/common.h.sv\n%Error: Exiting due to 1 error(s)\n'
module fixed_adder
(

    a,
    b,

    c,
    overflow,
    underflow
);

parameter WL = 32;
parameter IWL = 7;


input wire signed [WL-1:0] a;
input wire signed [WL-1:0] b;


output reg signed [WL-1:0] c;
output reg overflow;
output reg underflow;










always@(*)
begin
    c = a+b;
    overflow = 1'b0;
    underflow = 1'b0;

    if(a[WL-1]==0 && b[WL-1]==0 && c[WL-1]==1)
    begin
        overflow = 1'b1;

        c[WL-1] = 1'b0;
        c[WL-2:0] = {(WL-1){1'b1}};
    end

    if(a[WL-1]==1 && b[WL-1]==1 && c[WL-1]==0)
    begin
        underflow = 1'b1;
        
        c[WL-1] = 1'b1;
        c[WL-2:1] = {(WL-2){1'b0}};
        c[0] = 1'b1;
    end
end

endmodule
module fixed_adder
(

    a,
    b,

    c,
    overflow,
    underflow
);


parameter WL = 32;
parameter IWL = 7;


input wire signed [WL-1:0] a;
input wire signed [WL-1:0] b;


output reg signed [WL-1:0] c;
output reg overflow;
output reg underflow;










always@(*)
begin
    c = a+b;
    overflow = 1'b0;
    underflow = 1'b0;

    if(a[WL-1]==0 && b[WL-1]==0 && c[WL-1]==1)
    begin
        overflow = 1'b1;

        c[WL-1] = 1'b0;
        c[WL-2:0] = {(WL-1){1'b1}};
    end

    if(a[WL-1]==1 && b[WL-1]==1 && c[WL-1]==0)
    begin
        underflow = 1'b1;
        
        c[WL-1] = 1'b1;
        c[WL-2:1] = {(WL-2){1'b0}};
        c[0] = 1'b1;
    end
end

endmodule