data/full_repos/permissive/204736068/SoM/RTL/common/ice40_resetn.v
1: b'%Warning-WIDTH: data/full_repos/permissive/204736068/SoM/RTL/common/ice40_resetn.v:29: Operator ADD expects 8 bits on the RHS, but RHS\'s LOGNOT generates 1 bits.\n                                                                                     : ... In instance ice40_resetn\n      reset_cnt <= reset_cnt + !resetn;\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ice40_resetn(
                    input  clk, 
                    output resetn
                    );


   reg [7:0]               reset_cnt;
   initial 
     begin 
        reset_cnt = 0;
     end
   
   
   assign resetn = &reset_cnt;

   always @(posedge clk) begin
      reset_cnt <= reset_cnt + !resetn;
   end

   
endmodule
module ice40_resetn(
                    input  clk, 
                    output resetn
                    );



   reg [7:0]               reset_cnt;
   initial 
     begin 
        reset_cnt = 0;
     end
   
   
   assign resetn = &reset_cnt;

   always @(posedge clk) begin
      reset_cnt <= reset_cnt + !resetn;
   end

   
endmodule