data/full_repos/permissive/189468210/PMOD.srcs/sim_1/new/top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/189468210/PMOD.srcs/sim_1/new/top_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/189468210/PMOD.srcs/sim_1/new/top_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/189468210/PMOD.srcs/sim_1/new/top_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #40;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/189468210/PMOD.srcs/sim_1/new/top_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/189468210/PMOD.srcs/sim_1/new/top_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #100000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/189468210/PMOD.srcs/sim_1/new/top_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #5 CLK = ~CLK;\n        ^\n%Error: data/full_repos/permissive/189468210/PMOD.srcs/sim_1/new/top_tb.v:54: Cannot find file containing module: \'top\'\n    top dut (\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/189468210/PMOD.srcs/sim_1/new,data/full_repos/permissive/189468210/top\n             data/full_repos/permissive/189468210/PMOD.srcs/sim_1/new,data/full_repos/permissive/189468210/top.v\n             data/full_repos/permissive/189468210/PMOD.srcs/sim_1/new,data/full_repos/permissive/189468210/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb();

    reg CLK;
    reg BTNC, BTND, BTNU;
    
    wire JA3, JA4, JA9, JA10;
    
    pullup(JA3);
    pullup(JA4);
    pullup(JA9);
    pullup(JA10);
    
    initial begin
        CLK = 0;
        BTNC = 1;
        #10;
        #10;
        BTNC = 0;
        BTNU = 0;
        #40;
        BTNU = 1;
        #20;
        BTNU = 0;
        #100000;
        $stop();
    end
    
    always begin
        #5 CLK = ~CLK;
    end
    
    top dut (
        .GCLK(CLK),
        .BTNC(BTNC),
        .BTND(BTND),
        .BTNU(BTNU),
    
        .LD0(LD0),
        .LD1(LD1),
        .LD2(LD2),
        .LD3(LD3),
        .LD4(LD4),
        .LD5(LD5),
        .LD6(LD6),
        .LD7(LD7),
        

        
        .JA2(JA2),
        .JA3(JA3),
        .JA4(JA4),
        .JA9(JA9),
        .JA10(JA10),
    

        .JB1(JB1),
        .JB2(JB2),
        .JB3(JB3),
        .JB4(JB4),
        .JB7(JB7),
        .JB8(JB8),
        .JB9(JB9),
        .JB10(JB10),
        

        .JC1_N(JC1_N),
        .JC1_P(JC1_P),
        .JC2_N(JC2_N),
        .JC2_P(JC2_P),
        .JC3_N(JC3_N),
        .JC3_P(JC3_P),
        .JC4_N(JC4_N),
        .JC4_P(JC4_P)
        );

endmodule
module top_tb();


    reg CLK;
    reg BTNC, BTND, BTNU;
    
    wire JA3, JA4, JA9, JA10;
    
    pullup(JA3);
    pullup(JA4);
    pullup(JA9);
    pullup(JA10);
    
    initial begin
        CLK = 0;
        BTNC = 1;
        #10;
        #10;
        BTNC = 0;
        BTNU = 0;
        #40;
        BTNU = 1;
        #20;
        BTNU = 0;
        #100000;
        $stop();
    end
    
    always begin
        #5 CLK = ~CLK;
    end
    
    top dut (
        .GCLK(CLK),
        .BTNC(BTNC),
        .BTND(BTND),
        .BTNU(BTNU),
    
        .LD0(LD0),
        .LD1(LD1),
        .LD2(LD2),
        .LD3(LD3),
        .LD4(LD4),
        .LD5(LD5),
        .LD6(LD6),
        .LD7(LD7),
        

        
        .JA2(JA2),
        .JA3(JA3),
        .JA4(JA4),
        .JA9(JA9),
        .JA10(JA10),
    

        .JB1(JB1),
        .JB2(JB2),
        .JB3(JB3),
        .JB4(JB4),
        .JB7(JB7),
        .JB8(JB8),
        .JB9(JB9),
        .JB10(JB10),
        

        .JC1_N(JC1_N),
        .JC1_P(JC1_P),
        .JC2_N(JC2_N),
        .JC2_P(JC2_P),
        .JC3_N(JC3_N),
        .JC3_P(JC3_P),
        .JC4_N(JC4_N),
        .JC4_P(JC4_P)
        );

endmodule