data/full_repos/permissive/2084115/testbench/sim/library/tb_counter_async/tb_counter_async.v
1: b'%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_counter_async/tb_counter_async.v:11: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_counter_async.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/testbench/sim/library/tb_counter_async/tb_counter_async.v:12: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_counter_async);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_counter_async/tb_counter_async.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #100000;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_counter_async/tb_counter_async.v:19: Unsupported: Ignoring delay on this delayed statement.\n    always #(S_RATE/2.0)    s_clk = ~s_clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_counter_async/tb_counter_async.v:22: Unsupported: Ignoring delay on this delayed statement.\n    always #(M_RATE/2.0)    m_clk = ~m_clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_counter_async/tb_counter_async.v:25: Unsupported: Ignoring delay on this delayed statement.\n    initial #(S_RATE*100)   reset = 1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_counter_async/tb_counter_async.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #(S_RATE*200)   s_valid = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/library/tb_counter_async/tb_counter_async.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #(S_RATE*300)   s_valid = 1\'b0;\n        ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_counter_async();
    localparam S_RATE = 1000.0/20.0;
    localparam M_RATE = 1000.0/210.7;
    
    initial begin
        $dumpfile("tb_counter_async.vcd");
        $dumpvars(0, tb_counter_async);
        
        #100000;
            $finish;
    end
    
    reg     s_clk = 1'b1;
    always #(S_RATE/2.0)    s_clk = ~s_clk;
    
    reg     m_clk = 1'b1;
    always #(M_RATE/2.0)    m_clk = ~m_clk;
    
    reg     reset = 1'b1;
    initial #(S_RATE*100)   reset = 1'b0;
    
    
    localparam  COUNTER_WIDTH = 16;
    
    reg     [COUNTER_WIDTH-1:0] s_add   = 1;
    reg                         s_valid = 0;
    
    wire    [COUNTER_WIDTH-1:0] m_counter;
    wire                        m_valid;
    
    initial begin
        #(S_RATE*200)   s_valid = 1'b1;
        #(S_RATE*300)   s_valid = 1'b0;
    end
    
    integer s_c = 0;
    always @(posedge s_clk) begin
        if ( s_valid  ) begin
            s_c <= s_c + s_add;
        end
    end
    
    integer m_c = 0;
    always @(posedge m_clk) begin
        if ( !reset ) begin
            if ( m_valid ) begin
                m_c <= m_c + m_counter;
            end
        end
    end
    
    jelly_counter_async
            #(
                .ASYNC          (1),
                .COUNTER_WIDTH  (COUNTER_WIDTH)
            )
        i_count_async
            (
                .s_reset        (reset),
                .s_clk          (s_clk),
                .s_add          (s_add),
                .s_valid        (s_valid),
                
                .m_reset        (reset),
                .m_clk          (m_clk),
                .m_counter      (m_counter),
                .m_valid        (m_valid)
            );
    
    
endmodule
module tb_counter_async();

    localparam S_RATE = 1000.0/20.0;
    localparam M_RATE = 1000.0/210.7;
    
    initial begin
        $dumpfile("tb_counter_async.vcd");
        $dumpvars(0, tb_counter_async);
        
        #100000;
            $finish;
    end
    
    reg     s_clk = 1'b1;
    always #(S_RATE/2.0)    s_clk = ~s_clk;
    
    reg     m_clk = 1'b1;
    always #(M_RATE/2.0)    m_clk = ~m_clk;
    
    reg     reset = 1'b1;
    initial #(S_RATE*100)   reset = 1'b0;
    
    
    localparam  COUNTER_WIDTH = 16;
    
    reg     [COUNTER_WIDTH-1:0] s_add   = 1;
    reg                         s_valid = 0;
    
    wire    [COUNTER_WIDTH-1:0] m_counter;
    wire                        m_valid;
    
    initial begin
        #(S_RATE*200)   s_valid = 1'b1;
        #(S_RATE*300)   s_valid = 1'b0;
    end
    
    integer s_c = 0;
    always @(posedge s_clk) begin
        if ( s_valid  ) begin
            s_c <= s_c + s_add;
        end
    end
    
    integer m_c = 0;
    always @(posedge m_clk) begin
        if ( !reset ) begin
            if ( m_valid ) begin
                m_c <= m_c + m_counter;
            end
        end
    end
    
    jelly_counter_async
            #(
                .ASYNC          (1),
                .COUNTER_WIDTH  (COUNTER_WIDTH)
            )
        i_count_async
            (
                .s_reset        (reset),
                .s_clk          (s_clk),
                .s_add          (s_add),
                .s_valid        (s_valid),
                
                .m_reset        (reset),
                .m_clk          (m_clk),
                .m_counter      (m_counter),
                .m_valid        (m_valid)
            );
    
    
endmodule