data/full_repos/permissive/143278/blif/blif02c.v
data/verilator_xmls/db2d2cf7-d1c4-4cfd-be8d-bced4e006f29.xml
module addN
  #(parameter WID = 4)
   (input wire [WID-1:0] A,
    input wire [WID-1:0] B,
    output reg [WID:0]  Q
);

   always @* Q = A + B;

endmodule
module addN
  #(parameter WID = 4)
   (input wire [WID-1:0] A,
    input wire [WID-1:0] B,
    output reg [WID:0]  Q
);


   always @* Q = A + B;

endmodule