data/full_repos/permissive/125927162/4017/4017.v
data/verilator_xmls/ca1576f6-76c9-404b-8204-644466547d1d.xml
module ln4017 (cp0, cp1, mr, out_q, q59_n);
   input cp0;
   input cp1;
   input mr;
   output [9:0] out_q;
   reg [9:0] 	    out_d;
   output 	    q59_n;
   
   always @ (posedge mr)
     out_d <= 10'b1;

   always @ (posedge cp0) begin
     if (!cp1 & !mr) begin
	out_d[9:1] <= out_d[8:0];
	out_d[0] <= out_d[9];
     end
   end

   always @ (negedge cp0) begin
      if (cp1 & !mr) begin
	out_d[9:1] <= out_d[8:0];
	out_d[0] <= out_d[9];
     end
   end	 

   assign q59_n = ~|out_d[9:5];
   assign out_q = out_d;
endmodule
module ln4017 (cp0, cp1, mr, out_q, q59_n);

   input cp0;
   input cp1;
   input mr;
   output [9:0] out_q;
   reg [9:0] 	    out_d;
   output 	    q59_n;
   
   always @ (posedge mr)
     out_d <= 10'b1;

   always @ (posedge cp0) begin
     if (!cp1 & !mr) begin
	out_d[9:1] <= out_d[8:0];
	out_d[0] <= out_d[9];
     end
   end

   always @ (negedge cp0) begin
      if (cp1 & !mr) begin
	out_d[9:1] <= out_d[8:0];
	out_d[0] <= out_d[9];
     end
   end	 

   assign q59_n = ~|out_d[9:5];
   assign out_q = out_d;
endmodule