data/full_repos/permissive/143278/ivltests/select3.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/143278/ivltests/select3.v:29: syntax error, unexpected \'.\', expecting \'=\'\n   defparam test.dut.INIT = 16\'h55aa;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/select3.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("dut[%h] = %b", a, o);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module test;

   reg [4:0] a;
   wire      o;

   RAM dut(o, a[3:0]);
   defparam test.dut.INIT = 16'h55aa;

   initial begin
      for (a = 0 ;  a[4] == 0 ;  a = a + 1) begin
	 #1 $display("dut[%h] = %b", a, o);
      end
   end

endmodule
module test;


   reg [4:0] a;
   wire      o;

   RAM dut(o, a[3:0]);
   defparam test.dut.INIT = 16'h55aa;

   initial begin
      for (a = 0 ;  a[4] == 0 ;  a = a + 1) begin
	 #1 $display("dut[%h] = %b", a, o);
      end
   end

endmodule