data/full_repos/permissive/179451217/spi_slave.v
1: b'%Error: data/full_repos/permissive/179451217/spi_slave.v:114: syntax error, unexpected \';\', expecting IDENTIFIER\n    input bit;\n             ^\n%Error: data/full_repos/permissive/179451217/spi_slave.v:115: syntax error, unexpected \',\', expecting "\'{"\n    if(MSB_FIRST == 0) shift = {bit, word[WordWidth-1:1]};\n                                   ^\n%Error: data/full_repos/permissive/179451217/spi_slave.v:116: syntax error, unexpected \'}\', expecting "\'"\n    else shift = {word[WordWidth-2:0], bit};\n                                          ^\n%Error: Exiting due to 3 error(s)\n'
module spi_slave #(
    parameter WordWidth = 8,
    parameter IndexWidth = 3,
    parameter SyncStages = 2,
    parameter SPOL = 0,
    parameter CPOL = 0,
    parameter MOSI_PHA = 0,
    parameter MISO_PHA = 0,
    parameter MSB_FIRST = 1
)(
    input wire clk,
    input wire reset,

    output wire mosi_valid,
    output reg [WordWidth-1:0] mosi_word,
    input wire [WordWidth-1:0] miso_word_in,
    output wire miso_accepted,

    input wire ssel,
    input wire sclk,
    input wire mosi,
    output wire miso 
);



wire ssel_norm = (ssel == SPOL[0]);
wire sclk_norm = ~(ssel_norm && (sclk == CPOL));

wire ssel_sync, sclk_sync; 
synchronizer #(
    .Width(2), 
    .Stages(SyncStages),
    .Init(0),
    .InitValue(2'b01)
) ssel_sclk_sync (
    .clk(clk),
    .reset(reset),
    .in({ssel_norm, sclk_norm}),
    .out({ssel_sync, sclk_sync})
);


reg idle, idle_D;
reg last, last_D;
reg [IndexWidth-1:0] cycle, cycle_D;
reg skip, skip_D;



reg miso_ack, miso_ack_D;
reg miso_ack_gate, miso_ack_gate_D;
assign miso_accepted = miso_ack & miso_ack_gate;

reg mosi_val, mosi_val_D;
reg mosi_val_gate, mosi_val_gate_D;
assign mosi_valid = mosi_val & mosi_val_gate;

reg [WordWidth-1:0] miso_word, miso_word_D;
reg [WordWidth-1:0] mosi_word_D;

function [WordWidth-1:0] shift;
    input [WordWidth-1:0] word;
    input bit;
    if(MSB_FIRST == 0) shift = {bit, word[WordWidth-1:1]};
    else shift = {word[WordWidth-2:0], bit};
endfunction

generate
if(MSB_FIRST == 0) begin
    assign miso = miso_word[0];
end else begin
    assign miso = miso_word[WordWidth-1];
end
endgenerate


always @* begin

    mosi_word_D = mosi_word;
    miso_word_D = miso_word;
    
    miso_ack_D = 0;
    mosi_val_D = 0;
    miso_ack_gate_D = miso_ack_gate;
    mosi_val_gate_D = mosi_val_gate;

    idle_D = idle;
    if(cycle == 0) cycle_D = WordWidth - 1;
    else cycle_D = cycle - 1;
    
    skip_D = skip;
    if(mosi_val == 1) mosi_word_D = 0;


    if(miso_ack == 1'b1) begin
        miso_ack_gate_D = 1'b0;
        mosi_val_gate_D = 1'b1;
    end
    if(mosi_val == 1'b1) mosi_val_gate_D = 1'b0;

    if(idle == 1'b1) begin

        miso_ack_gate_D = 1'b1;
        miso_word_D = miso_word_in;
        mosi_word_D = 0;
        cycle_D = WordWidth-1;
        last_D = 0;
        if(MISO_PHA == 1) skip_D = 1;
        if(ssel_sync == 1'b1) begin

            idle_D = 1'b0;
            miso_ack_D = 1;
        end
    end else begin
        if(last == 1'b0) begin
            if(ssel_sync == 1'b1) begin
                mosi_word_D = shift(mosi_word, mosi);
                
                if(skip == 1)  begin
                    skip_D = 0;
                    miso_ack_D = 1;
                end
                else miso_word_D = shift(miso_word, 1'b0);

                if(cycle == 0) begin 
                    mosi_val_D = 1;
                    last_D = 1'b1;
                    cycle_D = WordWidth-1;
                    miso_ack_gate_D = 1'b1;
                    if(MISO_PHA == 0) begin
                        miso_word_D = miso_word_in;
                    end
                end
            end else begin


                idle_D = 1'b1;
            end
        end else begin

            miso_word_D = miso_word_in;
            if(ssel_sync == 1'b1) begin
                miso_ack_D = 1'b1;
                last_D = 1'b0;
                if(MOSI_PHA == 0) begin
                    mosi_word_D = shift(mosi_word, mosi);
                    if(cycle == 0) mosi_val_D = 1;
                end
            end else begin
                idle_D = 1'b1;
            end
        end
    end
end


always @(posedge clk) begin
    if(reset) begin
        idle <= 1'b1;
        mosi_val_gate <= 1'b0;
        miso_ack_gate <= 1'b0;
    end else begin
        idle <= idle_D;
        mosi_val_gate <= mosi_val_gate_D;
        miso_ack_gate <= miso_ack_gate_D;
    end
end


always @(posedge sclk_sync) begin
    if(MOSI_PHA == 0) begin
        mosi_word <= mosi_word_D;
        mosi_val <= mosi_val_D;
    end
    if(MISO_PHA == 1) begin
        miso_word <= miso_word_D;
        miso_ack <= miso_ack_D;
    end
end

always @(negedge sclk_sync) begin
    skip <= skip_D;
    cycle <= cycle_D;
    last <= last_D;
    if(MOSI_PHA == 1) begin
        mosi_word <= mosi_word_D;
        mosi_val <= mosi_val_D;
    end
    if(MISO_PHA == 0) begin
        miso_word <= miso_word_D;
        miso_ack <= miso_ack_D;
    end
end

endmodule
module spi_slave #(
    parameter WordWidth = 8,
    parameter IndexWidth = 3,
    parameter SyncStages = 2,
    parameter SPOL = 0,
    parameter CPOL = 0,
    parameter MOSI_PHA = 0,
    parameter MISO_PHA = 0,
    parameter MSB_FIRST = 1
)(
    input wire clk,
    input wire reset,

    output wire mosi_valid,
    output reg [WordWidth-1:0] mosi_word,
    input wire [WordWidth-1:0] miso_word_in,
    output wire miso_accepted,

    input wire ssel,
    input wire sclk,
    input wire mosi,
    output wire miso 
);




wire ssel_norm = (ssel == SPOL[0]);
wire sclk_norm = ~(ssel_norm && (sclk == CPOL));

wire ssel_sync, sclk_sync; 
synchronizer #(
    .Width(2), 
    .Stages(SyncStages),
    .Init(0),
    .InitValue(2'b01)
) ssel_sclk_sync (
    .clk(clk),
    .reset(reset),
    .in({ssel_norm, sclk_norm}),
    .out({ssel_sync, sclk_sync})
);


reg idle, idle_D;
reg last, last_D;
reg [IndexWidth-1:0] cycle, cycle_D;
reg skip, skip_D;



reg miso_ack, miso_ack_D;
reg miso_ack_gate, miso_ack_gate_D;
assign miso_accepted = miso_ack & miso_ack_gate;

reg mosi_val, mosi_val_D;
reg mosi_val_gate, mosi_val_gate_D;
assign mosi_valid = mosi_val & mosi_val_gate;

reg [WordWidth-1:0] miso_word, miso_word_D;
reg [WordWidth-1:0] mosi_word_D;

function [WordWidth-1:0] shift;
    input [WordWidth-1:0] word;
    input bit;
    if(MSB_FIRST == 0) shift = {bit, word[WordWidth-1:1]};
    else shift = {word[WordWidth-2:0], bit};
endfunction

generate
if(MSB_FIRST == 0) begin
    assign miso = miso_word[0];
end else begin
    assign miso = miso_word[WordWidth-1];
end
endgenerate


always @* begin

    mosi_word_D = mosi_word;
    miso_word_D = miso_word;
    
    miso_ack_D = 0;
    mosi_val_D = 0;
    miso_ack_gate_D = miso_ack_gate;
    mosi_val_gate_D = mosi_val_gate;

    idle_D = idle;
    if(cycle == 0) cycle_D = WordWidth - 1;
    else cycle_D = cycle - 1;
    
    skip_D = skip;
    if(mosi_val == 1) mosi_word_D = 0;


    if(miso_ack == 1'b1) begin
        miso_ack_gate_D = 1'b0;
        mosi_val_gate_D = 1'b1;
    end
    if(mosi_val == 1'b1) mosi_val_gate_D = 1'b0;

    if(idle == 1'b1) begin

        miso_ack_gate_D = 1'b1;
        miso_word_D = miso_word_in;
        mosi_word_D = 0;
        cycle_D = WordWidth-1;
        last_D = 0;
        if(MISO_PHA == 1) skip_D = 1;
        if(ssel_sync == 1'b1) begin

            idle_D = 1'b0;
            miso_ack_D = 1;
        end
    end else begin
        if(last == 1'b0) begin
            if(ssel_sync == 1'b1) begin
                mosi_word_D = shift(mosi_word, mosi);
                
                if(skip == 1)  begin
                    skip_D = 0;
                    miso_ack_D = 1;
                end
                else miso_word_D = shift(miso_word, 1'b0);

                if(cycle == 0) begin 
                    mosi_val_D = 1;
                    last_D = 1'b1;
                    cycle_D = WordWidth-1;
                    miso_ack_gate_D = 1'b1;
                    if(MISO_PHA == 0) begin
                        miso_word_D = miso_word_in;
                    end
                end
            end else begin


                idle_D = 1'b1;
            end
        end else begin

            miso_word_D = miso_word_in;
            if(ssel_sync == 1'b1) begin
                miso_ack_D = 1'b1;
                last_D = 1'b0;
                if(MOSI_PHA == 0) begin
                    mosi_word_D = shift(mosi_word, mosi);
                    if(cycle == 0) mosi_val_D = 1;
                end
            end else begin
                idle_D = 1'b1;
            end
        end
    end
end


always @(posedge clk) begin
    if(reset) begin
        idle <= 1'b1;
        mosi_val_gate <= 1'b0;
        miso_ack_gate <= 1'b0;
    end else begin
        idle <= idle_D;
        mosi_val_gate <= mosi_val_gate_D;
        miso_ack_gate <= miso_ack_gate_D;
    end
end


always @(posedge sclk_sync) begin
    if(MOSI_PHA == 0) begin
        mosi_word <= mosi_word_D;
        mosi_val <= mosi_val_D;
    end
    if(MISO_PHA == 1) begin
        miso_word <= miso_word_D;
        miso_ack <= miso_ack_D;
    end
end

always @(negedge sclk_sync) begin
    skip <= skip_D;
    cycle <= cycle_D;
    last <= last_D;
    if(MOSI_PHA == 1) begin
        mosi_word <= mosi_word_D;
        mosi_val <= mosi_val_D;
    end
    if(MISO_PHA == 0) begin
        miso_word <= miso_word_D;
        miso_ack <= miso_ack_D;
    end
end

endmodule