data/full_repos/permissive/161314640/RDC/testbench.v
1: b'%Error: data/full_repos/permissive/161314640/RDC/testbench.v:1: Cannot find include file: rdc.v\n`include "rdc.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161314640/RDC,data/full_repos/permissive/161314640/rdc.v\n             data/full_repos/permissive/161314640/RDC,data/full_repos/permissive/161314640/rdc.v.v\n             data/full_repos/permissive/161314640/RDC,data/full_repos/permissive/161314640/rdc.v.sv\n             rdc.v\n             rdc.v.v\n             rdc.v.sv\n             obj_dir/rdc.v\n             obj_dir/rdc.v.v\n             obj_dir/rdc.v.sv\n%Error: data/full_repos/permissive/161314640/RDC/testbench.v:10: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("rdc.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/161314640/RDC/testbench.v:11: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,testbench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/161314640/RDC/testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\nalways #1 Clk = ~Clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/161314640/RDC/testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #1;Load = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/RDC/testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #1;I0 = 0; I1=0; I2=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/RDC/testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #10;Load=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/RDC/testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #20;$finish;\n  ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module testbench();

  reg I0, I1, I2 ,Clk, Load;
  wire FF1, FF2, FF3;

rdc instancial(.Clk(Clk), .FF1(FF1), .FF2(FF2), .FF3(FF3), .I0(I0), .I1(I1), .I2(I2), .Load(Load));

initial begin
    $dumpfile("rdc.vcd");
    $dumpvars(0,testbench);
    Clk=0;
end

always #1 Clk = ~Clk;

initial begin
  #1;Load = 1;
  #1;I0 = 0; I1=0; I2=1;
  #10;Load=0;
  #20;$finish;
end

endmodule
module testbench();


  reg I0, I1, I2 ,Clk, Load;
  wire FF1, FF2, FF3;

rdc instancial(.Clk(Clk), .FF1(FF1), .FF2(FF2), .FF3(FF3), .I0(I0), .I1(I1), .I2(I2), .Load(Load));

initial begin
    $dumpfile("rdc.vcd");
    $dumpvars(0,testbench);
    Clk=0;
end

always #1 Clk = ~Clk;

initial begin
  #1;Load = 1;
  #1;I0 = 0; I1=0; I2=1;
  #10;Load=0;
  #20;$finish;
end

endmodule