data/full_repos/permissive/106408053/verilog/trigger_adv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n              ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module trigterm_range (dataIn, clock, wrenb, din, hit);
input [31:0] dataIn;
input clock, wrenb, din;
output hit;
trigterm_range_byte byte0 (dataIn[7:0], clock, wrenb, din, dout0, 1'b1, cout0);
trigterm_range_byte byte1 (dataIn[15:8], clock, wrenb, dout0, dout1, cout0, cout1);
trigterm_range_byte byte2 (dataIn[23:16], clock, wrenb, dout1, dout2, cout1, cout2);
trigterm_range_byte byte3 (dataIn[31:24], clock, wrenb, dout2, dout, cout2, hit);
endmodule
module trigterm_range (dataIn, clock, wrenb, din, hit);

input [31:0] dataIn;
input clock, wrenb, din;
output hit;
trigterm_range_byte byte0 (dataIn[7:0], clock, wrenb, din, dout0, 1'b1, cout0);
trigterm_range_byte byte1 (dataIn[15:8], clock, wrenb, dout0, dout1, cout0, cout1);
trigterm_range_byte byte2 (dataIn[23:16], clock, wrenb, dout1, dout2, cout1, cout2);
trigterm_range_byte byte3 (dataIn[31:24], clock, wrenb, dout2, dout, cout2, hit);
endmodule