data/full_repos/permissive/157608247/testbench/candy_if_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:1: Cannot find include file: candy_defines.v\n`include "candy_defines.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v.v\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v.sv\n             candy_defines.v\n             candy_defines.v.v\n             candy_defines.v.sv\n             obj_dir/candy_defines.v\n             obj_dir/candy_defines.v.v\n             obj_dir/candy_defines.v.sv\n%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:7: Define or directive not defined: \'`SRAMAddrWidth\'\nreg [`SRAMAddrWidth] pc;\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`SRAMAddrWidth] pc;\n                   ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:12: Define or directive not defined: \'`SRAMDataWidth\'\nreg [`SRAMDataWidth] sram_data;\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`SRAMDataWidth] sram_data;\n                   ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:14: Define or directive not defined: \'`SRAMDataWidth\'\nwire [`SRAMDataWidth] inst;\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`SRAMDataWidth] inst;\n                    ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:15: Define or directive not defined: \'`SRAMAddrWidth\'\nwire [`SRAMAddrWidth] sram_addr;\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`SRAMAddrWidth] sram_addr;\n                    ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:41: Define or directive not defined: \'`RstEnable\'\n        rst <= `RstEnable;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:41: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rst <= `RstEnable;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #0 begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:45: Define or directive not defined: \'`RstDisable\'\n        rst <= `RstDisable;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rst <= `RstDisable;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #25 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #10 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_if_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: Exiting due to 13 error(s), 5 warning(s)\n'
module candy_if_tb;

reg clk;
reg rst;
reg [`SRAMAddrWidth] pc;

reg if_enable;

reg data_ready;
reg [`SRAMDataWidth] sram_data;

wire [`SRAMDataWidth] inst;
wire [`SRAMAddrWidth] sram_addr;
wire sram_read_enable;
wire is_mem;



candy_if ifetch(
    .clk(clk),
    .rst(rst),

    .pc(pc),
    .if_enable(if_enable),

    .data_ready(data_ready),
    .sram_data(sram_data),

    .inst(inst),
    .sram_addr(sram_addr),
    .sram_read_enable(sram_read_enable),
    .is_mem(is_mem)
);


initial begin
    #0 begin
        clk <= 1'b0;
        rst <= `RstEnable;
        if_enable <= 1'b0;
    end
    #10 begin
        rst <= `RstDisable;
    end
    #25 begin
        if_enable <= 1'b1;

        pc <= 17'h012;
        if_enable <= 1'b1;
    end
    #10 begin

        data_ready <= 1'b1;
        sram_data <= 24'h027890;
    end
end

always #5 clk <= ~clk;

endmodule
module candy_if_tb;


reg clk;
reg rst;
reg [`SRAMAddrWidth] pc;

reg if_enable;

reg data_ready;
reg [`SRAMDataWidth] sram_data;

wire [`SRAMDataWidth] inst;
wire [`SRAMAddrWidth] sram_addr;
wire sram_read_enable;
wire is_mem;



candy_if ifetch(
    .clk(clk),
    .rst(rst),

    .pc(pc),
    .if_enable(if_enable),

    .data_ready(data_ready),
    .sram_data(sram_data),

    .inst(inst),
    .sram_addr(sram_addr),
    .sram_read_enable(sram_read_enable),
    .is_mem(is_mem)
);


initial begin
    #0 begin
        clk <= 1'b0;
        rst <= `RstEnable;
        if_enable <= 1'b0;
    end
    #10 begin
        rst <= `RstDisable;
    end
    #25 begin
        if_enable <= 1'b1;

        pc <= 17'h012;
        if_enable <= 1'b1;
    end
    #10 begin

        data_ready <= 1'b1;
        sram_data <= 24'h027890;
    end
end

always #5 clk <= ~clk;

endmodule