data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v
 line:110: before: "gned"
1: b'%Warning-MULTITOP: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v:61: Multiple top level modules\n                                                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                    : ... Top module \'$alu\'\nmodule \\$alu (A, B, CI, BI, X, Y, CO);\n       ^~~~~\n                                                                                                                    : ... Top module \'$fa\'\nmodule \\$fa (A, B, C, X, Y);\n       ^~~~\n                                                                                                                    : ... Top module \'$add\'\nmodule \\$add (A, B, Y);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v:128: Operator ASSIGNW expects 1025 bits on the Assign RHS, but Assign RHS\'s CONST \'176\'h73706c69746e6574732043415252593b20636c65616e\' generates 176 bits.\n                                                                                                                  : ... In instance __024add\nwire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v:75: Operator ASSIGNW expects 1025 bits on the Assign RHS, but Assign RHS\'s CONST \'176\'h73706c69746e6574732043415252593b20636c65616e\' generates 176 bits.\n                                                                                                                 : ... In instance __024fa\nwire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v:21: Operator ASSIGNW expects 1025 bits on the Assign RHS, but Assign RHS\'s CONST \'176\'h73706c69746e6574732043415252593b20636c65616e\' generates 176 bits.\n                                                                                                                 : ... In instance __024alu\nwire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";\n                           ^\n%Error: Exiting due to 4 warning(s)\n'
module \$alu (A, B, CI, BI, X, Y, CO);

parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;

input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH:0] X, Y;

input CI, BI;
output [Y_WIDTH:0] CO;

wire [Y_WIDTH-1:0] AA, BB;
wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";

generate
	if (A_SIGNED && B_SIGNED) begin:BLOCK1
		assign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);
	end else begin:BLOCK2
		assign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);
	end
endgenerate

   wire [Y_WIDTH: 0 ] CARRY;
   assign CARRY[0] = CI;

   genvar i;
   generate for (i = 0; i < Y_WIDTH - 1; i = i+1) begin:gen3
     adder my_adder (
       .cin		(CARRY[i]),
       .cout	(CARRY[i+1]),
       .a		(AA[i]),
       .b		(BB[i]),
       .sumout	(Y[i])
     );
   end endgenerate

   generate if ((Y_WIDTH -1) % 20 == 0) begin:gen4
     assign Y[Y_WIDTH-1] = CARRY[Y_WIDTH-1];
   end else begin:gen5
     adder my_adder (
       .cin		(CARRY[Y_WIDTH - 1]),
       .cout	(CARRY[Y_WIDTH]),
       .a		(1'b0),
       .b		(1'b0),
       .sumout	(Y[Y_WIDTH -1])
     );
   end
   endgenerate
 endmodule
module \$alu (A, B, CI, BI, X, Y, CO);


parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;

input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH:0] X, Y;

input CI, BI;
output [Y_WIDTH:0] CO;

wire [Y_WIDTH-1:0] AA, BB;
wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";

generate
	if (A_SIGNED && B_SIGNED) begin:BLOCK1
		assign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);
	end else begin:BLOCK2
		assign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);
	end
endgenerate

   wire [Y_WIDTH: 0 ] CARRY;
   assign CARRY[0] = CI;

   genvar i;
   generate for (i = 0; i < Y_WIDTH - 1; i = i+1) begin:gen3
     adder my_adder (
       .cin		(CARRY[i]),
       .cout	(CARRY[i+1]),
       .a		(AA[i]),
       .b		(BB[i]),
       .sumout	(Y[i])
     );
   end endgenerate

   generate if ((Y_WIDTH -1) % 20 == 0) begin:gen4
     assign Y[Y_WIDTH-1] = CARRY[Y_WIDTH-1];
   end else begin:gen5
     adder my_adder (
       .cin		(CARRY[Y_WIDTH - 1]),
       .cout	(CARRY[Y_WIDTH]),
       .a		(1'b0),
       .b		(1'b0),
       .sumout	(Y[Y_WIDTH -1])
     );
   end
   endgenerate
 endmodule