data/full_repos/permissive/108195533/PC.v
data/verilator_xmls/6242881e-fbe4-4c53-9b45-9de4e0dc3a04.xml
module PC#(parameter MEM_WIDTH=8)(clk, reset, PCOut, PCIn, load, en);
  input clk, reset, load, en;
  input [MEM_WIDTH-1:0] PCIn;
  output [MEM_WIDTH-1:0] PCOut;
  
  reg [MEM_WIDTH-1:0] count;
  
  assign PCOut = count;
  
  always@(posedge clk)
  begin  
   if(reset)
		count <= {MEM_WIDTH{1'b0}};
	else if(en) begin
		if(load)
			count <= count+PCIn;
		else
			count <= count + 1;
	end
  end
endmodule
module PC#(parameter MEM_WIDTH=8)(clk, reset, PCOut, PCIn, load, en);

  input clk, reset, load, en;
  input [MEM_WIDTH-1:0] PCIn;
  output [MEM_WIDTH-1:0] PCOut;
  
  reg [MEM_WIDTH-1:0] count;
  
  assign PCOut = count;
  
  always@(posedge clk)
  begin  
   if(reset)
		count <= {MEM_WIDTH{1'b0}};
	else if(en) begin
		if(load)
			count <= count+PCIn;
		else
			count <= count + 1;
	end
  end
endmodule