data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/fake_signal.v
1: b'%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/fake_signal.v:59: Operator ASSIGN expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n                                                                                                         : ... In instance fake_signal\n   reg [MSB:0]     raw = \'bz;    \n                         ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/fake_signal.v:85: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                         : ... In instance fake_signal\n       raw <= #DELAY $random;\n           ^~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/fake_signal.v:91: Cannot find file containing module: \'signal_stagger\'\n   signal_stagger\n   ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture,data/full_repos/permissive/20430511/signal_stagger\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture,data/full_repos/permissive/20430511/signal_stagger.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture,data/full_repos/permissive/20430511/signal_stagger.sv\n             signal_stagger\n             signal_stagger.v\n             signal_stagger.sv\n             obj_dir/signal_stagger\n             obj_dir/signal_stagger.v\n             obj_dir/signal_stagger.sv\n%Error: Internal Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/fake_signal.v:96: ../V3Width.cpp:3377: Visit function missing? Widthed expectation for this node: PARSEREF 0x564f4b985170 <e412> {c96}  MSB [TEXT]\n                                                                                                                 : ... In instance fake_signal\n        ) STAG [MSB:0]\n                ^~~\n'
module fake_signal
  #(parameter WIDTH = 24,
    parameter MSB   = WIDTH-1,
    parameter RATIO = 12,
    parameter RMAX  = RATIO-1,
    parameter RZERO = 0,
    parameter SHAKE = 1,
    parameter NOISY = 1,
    parameter DELAY = 3)
   (
    input          clock,
    input          reset,
    input          enable,
    output         strobe,
    output         locked,
    output [MSB:0] signal
    );


   reg [MSB:0]     raw = 'bz;
   wire [MSB:0]    valids, pulses;





   assign locked = &valids;
   assign strobe = &pulses;





   integer         count = 0;
   wire [31:0]     cnext = cwrap ? RZERO : count + 1;
   wire            cwrap = count == RMAX;
    
   always @(posedge clock)
     if (reset)
       count <= #DELAY RATIO-4;
     else
       count <= #DELAY cnext;

   always @(posedge clock)
     if (cwrap)
       raw <= #DELAY $random;





   signal_stagger
     #( .PHASE_JITTER(SHAKE),
        .PHASE_OFFSET(SHAKE > 0 ? SHAKE+1 : 0),
        .CYCLE_JITTER(0),
        .NOISY(NOISY)
        ) STAG [MSB:0]
     (  .clk(clock),
        .rst(reset),
        .ce (enable),
        .d  (raw),
        .stb(pulses),
        .vld(valids),
        .q  (signal)
        );





   always @(posedge clock)
     if (NOISY && ~&pulses && |pulses)
       $display("%12t: fake_signal: ERROR: strobes out of sync", $time);


endmodule
module fake_signal
  #(parameter WIDTH = 24,
    parameter MSB   = WIDTH-1,
    parameter RATIO = 12,
    parameter RMAX  = RATIO-1,
    parameter RZERO = 0,
    parameter SHAKE = 1,
    parameter NOISY = 1,
    parameter DELAY = 3)
   (
    input          clock,
    input          reset,
    input          enable,
    output         strobe,
    output         locked,
    output [MSB:0] signal
    );



   reg [MSB:0]     raw = 'bz;
   wire [MSB:0]    valids, pulses;





   assign locked = &valids;
   assign strobe = &pulses;





   integer         count = 0;
   wire [31:0]     cnext = cwrap ? RZERO : count + 1;
   wire            cwrap = count == RMAX;
    
   always @(posedge clock)
     if (reset)
       count <= #DELAY RATIO-4;
     else
       count <= #DELAY cnext;

   always @(posedge clock)
     if (cwrap)
       raw <= #DELAY $random;





   signal_stagger
     #( .PHASE_JITTER(SHAKE),
        .PHASE_OFFSET(SHAKE > 0 ? SHAKE+1 : 0),
        .CYCLE_JITTER(0),
        .NOISY(NOISY)
        ) STAG [MSB:0]
     (  .clk(clock),
        .rst(reset),
        .ce (enable),
        .d  (raw),
        .stb(pulses),
        .vld(valids),
        .q  (signal)
        );





   always @(posedge clock)
     if (NOISY && ~&pulses && |pulses)
       $display("%12t: fake_signal: ERROR: strobes out of sync", $time);


endmodule