data/full_repos/permissive/158984095/RippleFullAdder/RippleFA_testbench.v
1: b'%Error: data/full_repos/permissive/158984095/RippleFullAdder/RippleFA_testbench.v:8: Unsupported or unknown PLI call: $monitor\n$monitor($time,"input1 = %b \\t input2 = %b \\t cin = %b \\t sum = %b \\t cout = %b \\n",input1,input2,cinfinal,sumfinal,carryfinal);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/158984095/RippleFullAdder/RippleFA_testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n# 5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/158984095/RippleFullAdder/RippleFA_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n# 5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/RippleFullAdder/RippleFA_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n# 5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/RippleFullAdder/RippleFA_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n# 5;\n^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbenchFA;
reg input1,input2,cinfinal;
wire sumfinal,carryfinal;
RippleFA FAtest(input1,input2,cinfinal,sumfinal,carryfinal);

initial
begin
$monitor($time,"input1 = %b \t input2 = %b \t cin = %b \t sum = %b \t cout = %b \n",input1,input2,cinfinal,sumfinal,carryfinal);
input1 = 1'b0;
input2 = 1'b0;
cinfinal = 1'b0;
# 5;
input1 = 1'b1;
input2 = 1'b0;
cinfinal = 1'b0;
# 5;
input1 = 1'b1;
input2 = 1'b0;
cinfinal = 1'b1;
# 5;
input1 = 1'b1;
input2 = 1'b1;
cinfinal = 1'b1;
# 5;
end 
endmodule
module testbenchFA;

reg input1,input2,cinfinal;
wire sumfinal,carryfinal;
RippleFA FAtest(input1,input2,cinfinal,sumfinal,carryfinal);

initial
begin
$monitor($time,"input1 = %b \t input2 = %b \t cin = %b \t sum = %b \t cout = %b \n",input1,input2,cinfinal,sumfinal,carryfinal);
input1 = 1'b0;
input2 = 1'b0;
cinfinal = 1'b0;
# 5;
input1 = 1'b1;
input2 = 1'b0;
cinfinal = 1'b0;
# 5;
input1 = 1'b1;
input2 = 1'b0;
cinfinal = 1'b1;
# 5;
input1 = 1'b1;
input2 = 1'b1;
cinfinal = 1'b1;
# 5;
end 
endmodule