data/full_repos/permissive/116468596/updownTagger.v
1: b"%Error: data/full_repos/permissive/116468596/updownTagger.v:55: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b1)) ff_instance_0 (.C(clk), .CE(1'b1), .D(inD[0]), .Q(outQ[0]));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n             FDRE\n             FDRE.v\n             FDRE.sv\n             obj_dir/FDRE\n             obj_dir/FDRE.v\n             obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/updownTagger.v:56: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0)) ff_instance_1 (.C(clk), .CE(1'b1), .D(inD[1]), .Q(outQ[1]));\n    ^~~~\n%Error: data/full_repos/permissive/116468596/updownTagger.v:57: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0)) ff_instance_2 (.C(clk), .CE(1'b1), .D(inD[2]), .Q(outQ[2]));\n    ^~~~\n%Error: Exiting due to 3 error(s)\n"
module updownTagger(
    input clk, twoSec, top, bottom, up, down,
    output countUp, countDown, upDownLD, activeGreen
    );
    wire [14:0] con;
    wire [2:0] inD;
    wire [2:0] outQ;
    
    assign con[0] = 1'b0;
    assign con[1] = ~twoSec & outQ[0];
    assign con[2] = twoSec & outQ[0];
    assign con[3] = ~bottom & ~up & outQ[1];
    assign con[4] = bottom & down & outQ[1];
    assign con[5] = bottom & ~down & outQ[1];
    assign con[6] = ~bottom & up & outQ[1];
    assign con[7] = bottom & up & outQ[1];
    assign con[8] = ~top & ~down & outQ[2];
    assign con[9] = top & up & outQ[2];
    assign con[10] = top & ~up & outQ[2];
    assign con[11] = ~top & down & outQ[2];
    assign con[12] = top & down & outQ[2];
    assign con[13] = up & down & outQ[1];
    assign con[14] = up & down & outQ[2];
    
    assign inD[0] = con[1];
    assign inD[1] = con[2] | con[3] | con[4] | con[10] | con[11] | con[12];
    assign inD[2] = con[5] | con[6] | con[7] | con[8] | con[9];
    assign activeGreen = ~outQ[0];
    assign upDownLD = outQ[0];
    assign countUp = outQ[2] & ~con[9] & ~con[14];
    assign countDown = outQ[1] & ~con[4] & ~con[13];
   
    FDRE #(.INIT(1'b1)) ff_instance_0 (.C(clk), .CE(1'b1), .D(inD[0]), .Q(outQ[0]));
    FDRE #(.INIT(1'b0)) ff_instance_1 (.C(clk), .CE(1'b1), .D(inD[1]), .Q(outQ[1]));
    FDRE #(.INIT(1'b0)) ff_instance_2 (.C(clk), .CE(1'b1), .D(inD[2]), .Q(outQ[2]));


    
    
    
    
endmodule
module updownTagger(
    input clk, twoSec, top, bottom, up, down,
    output countUp, countDown, upDownLD, activeGreen
    );

    wire [14:0] con;
    wire [2:0] inD;
    wire [2:0] outQ;
    
    assign con[0] = 1'b0;
    assign con[1] = ~twoSec & outQ[0];
    assign con[2] = twoSec & outQ[0];
    assign con[3] = ~bottom & ~up & outQ[1];
    assign con[4] = bottom & down & outQ[1];
    assign con[5] = bottom & ~down & outQ[1];
    assign con[6] = ~bottom & up & outQ[1];
    assign con[7] = bottom & up & outQ[1];
    assign con[8] = ~top & ~down & outQ[2];
    assign con[9] = top & up & outQ[2];
    assign con[10] = top & ~up & outQ[2];
    assign con[11] = ~top & down & outQ[2];
    assign con[12] = top & down & outQ[2];
    assign con[13] = up & down & outQ[1];
    assign con[14] = up & down & outQ[2];
    
    assign inD[0] = con[1];
    assign inD[1] = con[2] | con[3] | con[4] | con[10] | con[11] | con[12];
    assign inD[2] = con[5] | con[6] | con[7] | con[8] | con[9];
    assign activeGreen = ~outQ[0];
    assign upDownLD = outQ[0];
    assign countUp = outQ[2] & ~con[9] & ~con[14];
    assign countDown = outQ[1] & ~con[4] & ~con[13];
   
    FDRE #(.INIT(1'b1)) ff_instance_0 (.C(clk), .CE(1'b1), .D(inD[0]), .Q(outQ[0]));
    FDRE #(.INIT(1'b0)) ff_instance_1 (.C(clk), .CE(1'b1), .D(inD[1]), .Q(outQ[1]));
    FDRE #(.INIT(1'b0)) ff_instance_2 (.C(clk), .CE(1'b1), .D(inD[2]), .Q(outQ[2]));


    
    
    
    
endmodule