data/full_repos/permissive/143278/ivltests/pr2924354.v
 line:7: before: "for"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2924354.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("foo=%b, bar=%b", foo, bar);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/143278/ivltests/pr2924354.v:3: Signal definition not found, creating implicitly: \'impl\'\n   assign impl = 1;\n          ^~~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test(input wire foo, bar);

   initial begin
      #1 $display("foo=%b, bar=%b", foo, bar);
   end
endmodule
module test(input wire foo, bar);


   initial begin
      #1 $display("foo=%b, bar=%b", foo, bar);
   end
endmodule