data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Clkn.v
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data/verilator_xmls/38d1dff1-b914-4bdd-87b1-ed369c6e75ff.xml
module Clkn(clk,frequence ,clk_N);
input clk;
input [1:0]frequence;
output reg clk_N;

parameter A = 1_000_000;
parameter B = 10_000_000;
parameter C = 1_000_000;
parameter D = 100_000;
reg [31:0] counter;
initial begin
    clk_N = 0;
    counter = 0;
end
always @(posedge clk)  begin
    if(frequence==0)
    begin
        if(counter >=  A/2 -1 )
        begin
            clk_N = ~clk_N;
            counter = 0;
        end
        else 
           counter = counter + 1;  
     end
     else if(frequence==1)
     begin
        if(counter >=  B/2 -1 )
             begin
                 clk_N = ~clk_N;
                 counter = 0;
             end
             else 
                counter = counter + 1;  
     end
     else if(frequence==2)
     begin
             if(counter >=  C/2 -1 )
                  begin
                      clk_N = ~clk_N;
                      counter = 0;
                  end
                  else 
                     counter = counter + 1;  
      end
      else if(frequence==3)
      begin
          if(counter >=  D/2 -1 )
          begin
             clk_N = ~clk_N;
             counter = 0;
          end
          else 
             counter = counter + 1;  
      end
end                           
endmodule
module Clkn(clk,frequence ,clk_N);

input clk;
input [1:0]frequence;
output reg clk_N;

parameter A = 1_000_000;
parameter B = 10_000_000;
parameter C = 1_000_000;
parameter D = 100_000;
reg [31:0] counter;
initial begin
    clk_N = 0;
    counter = 0;
end
always @(posedge clk)  begin
    if(frequence==0)
    begin
        if(counter >=  A/2 -1 )
        begin
            clk_N = ~clk_N;
            counter = 0;
        end
        else 
           counter = counter + 1;  
     end
     else if(frequence==1)
     begin
        if(counter >=  B/2 -1 )
             begin
                 clk_N = ~clk_N;
                 counter = 0;
             end
             else 
                counter = counter + 1;  
     end
     else if(frequence==2)
     begin
             if(counter >=  C/2 -1 )
                  begin
                      clk_N = ~clk_N;
                      counter = 0;
                  end
                  else 
                     counter = counter + 1;  
      end
      else if(frequence==3)
      begin
          if(counter >=  D/2 -1 )
          begin
             clk_N = ~clk_N;
             counter = 0;
          end
          else 
             counter = counter + 1;  
      end
end                           
endmodule