data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v
1: b"%Error: data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v:13: Duplicate declaration of signal: 'clk'\n                                                                                           : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire clk,enb,eclk;\n       ^~~\n        data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v:8: ... Location of original declaration\n  input clk,\n        ^~~\n%Error: data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v:13: Duplicate declaration of signal: 'enb'\n  wire clk,enb,eclk;\n           ^~~\n        data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v:9: ... Location of original declaration\n  input enb,\n        ^~~\n%Error: data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v:13: Duplicate declaration of signal: 'eclk'\n  wire clk,enb,eclk;\n               ^~~~\n        data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v:10: ... Location of original declaration\n  output eclk\n         ^~~~\n%Error: Exiting due to 3 error(s)\n"
module enabler(
  input clk,
  input enb,
  output eclk
);

  wire clk,enb,eclk;

  wire outNot;
  wire outNand;

  parameter notoe = 1'b0;

  nandGate modeNor(
	 .a(clk),
	 .b(enb),
	 .y(outNand)
);

  notGate inverter(
	  .a(outNand),
	  .y(outNot)
);

assign eclk = outNot;

endmodule
module enabler(
  input clk,
  input enb,
  output eclk
);


  wire clk,enb,eclk;

  wire outNot;
  wire outNand;

  parameter notoe = 1'b0;

  nandGate modeNor(
	 .a(clk),
	 .b(enb),
	 .y(outNand)
);

  notGate inverter(
	  .a(outNand),
	  .y(outNot)
);

assign eclk = outNot;

endmodule