data/full_repos/permissive/162533945/reg_32.v
data/verilator_xmls/28ba48ba-087a-4567-bd69-76860b851970.xml
module dffe_ref(q, d, clk, en, clr);
   

   input d, clk, en, clr;
   

   wire clr;


   output q;
   

   reg q;


   initial
   begin
       q = 1'b0;
   end


   always @(posedge clk or posedge clr) begin

       if (clr) begin
           q <= 1'b0;

       end else if (en) begin
           q <= d;
       end
   end
endmodule
module dffe_ref(q, d, clk, en, clr);

   

   input d, clk, en, clr;
   

   wire clr;


   output q;
   

   reg q;


   initial
   begin
       q = 1'b0;
   end


   always @(posedge clk or posedge clr) begin

       if (clr) begin
           q <= 1'b0;

       end else if (en) begin
           q <= d;
       end
   end
endmodule