data/full_repos/permissive/164102137/alu.v
None: at end of input
1: b'%Error: data/full_repos/permissive/164102137/alu.v:30: Cannot find include file: states.i\n`include "states.i" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164102137,data/full_repos/permissive/164102137/states.i\n             data/full_repos/permissive/164102137,data/full_repos/permissive/164102137/states.i.v\n             data/full_repos/permissive/164102137,data/full_repos/permissive/164102137/states.i.sv\n             states.i\n             states.i.v\n             states.i.sv\n             obj_dir/states.i\n             obj_dir/states.i.v\n             obj_dir/states.i.sv\n%Error: Exiting due to 1 error(s)\n'
module alu(
    input [7:0] AI,
    input [7:0] MI,
    input CI,
    output [7:0] OUT,
    input mem_bi,
    input inv_bi,
    input [2:0] op,
    output reg C,
    output N,
    output Z,
    output V,
    output adj_lsd,
    output adj_msd
    );

`include "states.i"



wire [7:0] MEM = {8{mem_bi}};
wire [7:0] INV = {8{inv_bi}};


wire [7:0] BI = (MI & MEM) ^ INV;


wire [7:0] AND = AI & BI;
wire [7:0] EOR = AI ^ BI;
wire [7:0] ORA = AI | BI;


wire C1 = (ORA[0] & CI) | AND[0];
wire C2 = (ORA[1] & C1) | AND[1];
wire C3 = (ORA[2] & C2) | AND[2];
wire C4 = (ORA[3] & C3) | AND[3];
wire C5 = (ORA[4] & C4) | AND[4];
wire C6 = (ORA[5] & C5) | AND[5];
wire C7 = (ORA[6] & C6) | AND[6];
wire C8 = (ORA[7] & C7) | AND[7];


wire [7:0] ADC = EOR ^ { C7, C6, C5, C4, C3, C2, C1, CI };


always @*
    case( op )
        ALU_AI:                         OUT = AI;
        ALU_BI:                         OUT = BI;
        ALU_ADC:                        OUT = ADC;
        ALU_ROL:                        OUT = { AI[6:0], CI };
        ALU_ROR:                        OUT = { CI, AI[7:1] };
        ALU_ORA:                        OUT = ORA;
        ALU_EOR:                        OUT = EOR;
        ALU_AND:                        OUT = AND;
    endcase


assign N = OUT[7];
assign Z = OUT[7:0] == 0;
assign V = C8 ^ C7;


always @*
    if( op == ALU_ROL )                 C = AI[7];
    else if( op == ALU_ROR )            C = AI[0];
    else                                C = C8;



wire HCB = C4 ^ inv_bi;


wire DHC = ADC[3] & (ADC[2] | ADC[1]);


assign adj_lsd = HCB | DHC;


wire DC  = ADC[7] & (ADC[6] | ADC[5] | (ADC[4] & DHC));



wire CB = C8 ^ inv_bi;


assign adj_msd = CB | DC;


endmodule
module alu(
    input [7:0] AI,
    input [7:0] MI,
    input CI,
    output [7:0] OUT,
    input mem_bi,
    input inv_bi,
    input [2:0] op,
    output reg C,
    output N,
    output Z,
    output V,
    output adj_lsd,
    output adj_msd
    );


`include "states.i"



wire [7:0] MEM = {8{mem_bi}};
wire [7:0] INV = {8{inv_bi}};


wire [7:0] BI = (MI & MEM) ^ INV;


wire [7:0] AND = AI & BI;
wire [7:0] EOR = AI ^ BI;
wire [7:0] ORA = AI | BI;


wire C1 = (ORA[0] & CI) | AND[0];
wire C2 = (ORA[1] & C1) | AND[1];
wire C3 = (ORA[2] & C2) | AND[2];
wire C4 = (ORA[3] & C3) | AND[3];
wire C5 = (ORA[4] & C4) | AND[4];
wire C6 = (ORA[5] & C5) | AND[5];
wire C7 = (ORA[6] & C6) | AND[6];
wire C8 = (ORA[7] & C7) | AND[7];


wire [7:0] ADC = EOR ^ { C7, C6, C5, C4, C3, C2, C1, CI };


always @*
    case( op )
        ALU_AI:                         OUT = AI;
        ALU_BI:                         OUT = BI;
        ALU_ADC:                        OUT = ADC;
        ALU_ROL:                        OUT = { AI[6:0], CI };
        ALU_ROR:                        OUT = { CI, AI[7:1] };
        ALU_ORA:                        OUT = ORA;
        ALU_EOR:                        OUT = EOR;
        ALU_AND:                        OUT = AND;
    endcase


assign N = OUT[7];
assign Z = OUT[7:0] == 0;
assign V = C8 ^ C7;


always @*
    if( op == ALU_ROL )                 C = AI[7];
    else if( op == ALU_ROR )            C = AI[0];
    else                                C = C8;



wire HCB = C4 ^ inv_bi;


wire DHC = ADC[3] & (ADC[2] | ADC[1]);


assign adj_lsd = HCB | DHC;


wire DC  = ADC[7] & (ADC[6] | ADC[5] | (ADC[4] & DHC));



wire CB = C8 ^ inv_bi;


assign adj_msd = CB | DC;


endmodule