data/full_repos/permissive/201488448/3_verification/1_sim/13_seq2.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/3_verification/1_sim/13_seq2.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'p'\n                                                                                         : ... In instance top_module\n            p <= a;\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/3_verification/1_sim/13_seq2.v:13: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                          : ... In instance top_module\n        q <= p; \n        ^\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clock,
    input a,
    output p,
    output q );

    always@(clock) begin
        if(clock)
            p <= a;
    end
    
    always@(negedge clock) begin
       	q <= p; 
    end
    
endmodule
module top_module (
    input clock,
    input a,
    output p,
    output q );


    always@(clock) begin
        if(clock)
            p <= a;
    end
    
    always@(negedge clock) begin
       	q <= p; 
    end
    
endmodule