data/full_repos/permissive/160976968/mc_adder.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/160976968/mc_adder.v:54: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6]disp;\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/160976968/mc_adder.v:28: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                  : ... In instance mc_adder.A\n assign {cout, O} = A + B + cin;\n                          ^\n%Warning-LITENDIAN: data/full_repos/permissive/160976968/mc_adder.v:3: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6]HEX0, HEX1, HEX3, HEX5;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/160976968/mc_adder.v:14: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 5 bits.\n                                                                  : ... In instance mc_adder\n  S0 = {Cout, O} - Z;\n     ^\n%Error: Exiting due to 4 warning(s)\n'
module adder(B, A, cin, cout, O);
   input [3:0] A, B;
	input cin;
	output cout;
	output [3:0]O;
	assign {cout, O} = A + B + cin;
endmodule
module adder(B, A, cin, cout, O);

   input [3:0] A, B;
	input cin;
	output cout;
	output [3:0]O;
	assign {cout, O} = A + B + cin;
endmodule