data/full_repos/permissive/127311496/src/v/CPU/Cp0Reg.v
data/verilator_xmls/1af94612-c8fc-4d29-9f72-c65207045bd1.xml
module Cp0Reg #(
	parameter SOFTWARE_MASK = 32'b0000_0000_0000_0000_0000_0000_0000_0000,
	parameter RESET_STATE = 32'b0000_0000_0000_0000_0000_0000_0000_0000
)
(
	input clk, input rst,
	input [31:0] sDin, input sWe,
	input [31:0] hDin, input [31:0] hWe,
	output [31:0] dout
);
	
	genvar i;
	generate
	for(i = 0; i < 32; i = i+1)
	begin: Cp0Reg_1b
		reg regBit = RESET_STATE[i];
		assign dout[i] = regBit;
		always @ (posedge clk)
		begin
			if(rst)
				regBit <= RESET_STATE[i];
			else
			begin
				if(SOFTWARE_MASK[i] & sWe)
					regBit <= sDin[i];
				else if(hWe[i])
					regBit <= hDin[i];
			end
		end
	end
	endgenerate
	
endmodule
module Cp0Reg #(
	parameter SOFTWARE_MASK = 32'b0000_0000_0000_0000_0000_0000_0000_0000,
	parameter RESET_STATE = 32'b0000_0000_0000_0000_0000_0000_0000_0000
)
(
	input clk, input rst,
	input [31:0] sDin, input sWe,
	input [31:0] hDin, input [31:0] hWe,
	output [31:0] dout
);

	
	genvar i;
	generate
	for(i = 0; i < 32; i = i+1)
	begin: Cp0Reg_1b
		reg regBit = RESET_STATE[i];
		assign dout[i] = regBit;
		always @ (posedge clk)
		begin
			if(rst)
				regBit <= RESET_STATE[i];
			else
			begin
				if(SOFTWARE_MASK[i] & sWe)
					regBit <= sDin[i];
				else if(hWe[i])
					regBit <= hDin[i];
			end
		end
	end
	endgenerate
	
endmodule