data/full_repos/permissive/189992891/low_counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/189992891/low_counter.v:14: Operator EQ expects 27 bits on the RHS, but RHS\'s VARREF \'DIV\' generates 25 bits.\n                                                                     : ... In instance low_counter\n if (gen2 == DIV) begin\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module low_counter
#(parameter N=26, DIV = 25'd25000000)
(input wire in,
output reg out);

reg [N:0] gen2;
wire [N:0] gen2_next;
wire counter_next;

always@(posedge in)
begin
	gen2 <= gen2_next;
	out <= out;
	if (gen2 == DIV) begin
	gen2 <= 0;
	out <= ~out;
	end
end

assign gen2_next=gen2 + 1'b1;
endmodule
module low_counter
#(parameter N=26, DIV = 25'd25000000)
(input wire in,
output reg out);


reg [N:0] gen2;
wire [N:0] gen2_next;
wire counter_next;

always@(posedge in)
begin
	gen2 <= gen2_next;
	out <= out;
	if (gen2 == DIV) begin
	gen2 <= 0;
	out <= ~out;
	end
end

assign gen2_next=gen2 + 1'b1;
endmodule