data/full_repos/permissive/174510456/vmodel/ifetch.v
1: b'%Error: data/full_repos/permissive/174510456/vmodel/ifetch.v:14: Cannot find include file: noobs_cpu_defines.vh\n`include "noobs_cpu_defines.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174510456/vmodel,data/full_repos/permissive/174510456/noobs_cpu_defines.vh\n             data/full_repos/permissive/174510456/vmodel,data/full_repos/permissive/174510456/noobs_cpu_defines.vh.v\n             data/full_repos/permissive/174510456/vmodel,data/full_repos/permissive/174510456/noobs_cpu_defines.vh.sv\n             noobs_cpu_defines.vh\n             noobs_cpu_defines.vh.v\n             noobs_cpu_defines.vh.sv\n             obj_dir/noobs_cpu_defines.vh\n             obj_dir/noobs_cpu_defines.vh.v\n             obj_dir/noobs_cpu_defines.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module ifetch(
    clk,
    reset_,
    branch,
    ret_addr,
    ret_addr_en,
    ifetch_en,
    inst_i,
    tgt_addr,
    inst_o,
    idecode_en,
    inst_addr,
    next_addr
);

    input           clk;
    input           reset_;

    input           branch;
    input           ifetch_en;

    input [7:0]     inst_i;
    input [11:0]    tgt_addr;
    input [11:0]    ret_addr;
    input           ret_addr_en;

    output [7:0]    inst_o;
    output [11:0]   inst_addr;
    output [11:0]   next_addr;

    output          idecode_en;
    

    reg [11:0]  PC;
    reg [7:0]   inst_reg;
    reg         idecode_en;


    wire [11:0] pc_addr_next;
    wire [7:0] inst;


    always @(posedge clk)   begin
        if(!reset_) begin
            PC[11:0]    <= 12'd0;
        end
        else begin
            PC[11:0]    <= pc_addr_next[11:0]; 
        end
    end

    wire [11:0] next_addr;
    assign next_addr = PC + 1'b1; 
    assign pc_addr_next = (ifetch_en) ? ((branch) ? (tgt_addr + 1'b1) : (ret_addr_en ? ret_addr : next_addr)) : PC;
    assign inst_addr = branch ? tgt_addr : PC;


    always @(posedge clk)   begin
        if(!reset_) begin
            inst_reg[7:0]   <= 8'd0;
            idecode_en      <= 1'b0;
        end
        else begin
            inst_reg[7:0]   <= inst;
            idecode_en      <= ifetch_en;
        end
    end

    assign inst[7:0] = (ifetch_en) ? inst_i[7:0] : inst_reg[7:0];

    assign inst_o[7:0] = inst_reg[7:0];
endmodule
module ifetch(
    clk,
    reset_,
    branch,
    ret_addr,
    ret_addr_en,
    ifetch_en,
    inst_i,
    tgt_addr,
    inst_o,
    idecode_en,
    inst_addr,
    next_addr
);


    input           clk;
    input           reset_;

    input           branch;
    input           ifetch_en;

    input [7:0]     inst_i;
    input [11:0]    tgt_addr;
    input [11:0]    ret_addr;
    input           ret_addr_en;

    output [7:0]    inst_o;
    output [11:0]   inst_addr;
    output [11:0]   next_addr;

    output          idecode_en;
    

    reg [11:0]  PC;
    reg [7:0]   inst_reg;
    reg         idecode_en;


    wire [11:0] pc_addr_next;
    wire [7:0] inst;


    always @(posedge clk)   begin
        if(!reset_) begin
            PC[11:0]    <= 12'd0;
        end
        else begin
            PC[11:0]    <= pc_addr_next[11:0]; 
        end
    end

    wire [11:0] next_addr;
    assign next_addr = PC + 1'b1; 
    assign pc_addr_next = (ifetch_en) ? ((branch) ? (tgt_addr + 1'b1) : (ret_addr_en ? ret_addr : next_addr)) : PC;
    assign inst_addr = branch ? tgt_addr : PC;


    always @(posedge clk)   begin
        if(!reset_) begin
            inst_reg[7:0]   <= 8'd0;
            idecode_en      <= 1'b0;
        end
        else begin
            inst_reg[7:0]   <= inst;
            idecode_en      <= ifetch_en;
        end
    end

    assign inst[7:0] = (ifetch_en) ? inst_i[7:0] : inst_reg[7:0];

    assign inst_o[7:0] = inst_reg[7:0];
endmodule