data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_サンプル回路/FPGA-CPU/FPGA_counter/stop_watch.v
1: b"%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter/stop_watch.v:92: Cannot find file containing module: 'ctrg_rmv'\n ctrg_rmv ctrg_rmv1(\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter,data/full_repos/permissive/183580645/ctrg_rmv\n             data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter,data/full_repos/permissive/183580645/ctrg_rmv.v\n             data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter,data/full_repos/permissive/183580645/ctrg_rmv.sv\n             ctrg_rmv\n             ctrg_rmv.v\n             ctrg_rmv.sv\n             obj_dir/ctrg_rmv\n             obj_dir/ctrg_rmv.v\n             obj_dir/ctrg_rmv.sv\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter/stop_watch.v:102: Cannot find file containing module: 'watch_body'\n watch_body watch_body1(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter/stop_watch.v:118: Cannot find file containing module: 'time_display'\n time_display time_display1(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter/stop_watch.v:141: Cannot find file containing module: 'dynamic_display'\n dynamic_display dynamic_display1(\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module stop_watch (

		CLK,
		RSTN,


		PSW,
		RSW,


		SEG_A,


		SEG_SEL,





		LED,

		CYCLONE_A_OUT,
		CYCLONE_A,
		CYCLONE_B
		);



	input	CLK;
	input	RSTN;

	input	[3:0]  PSW;
	input	[3:0]  RSW;



	input	[6:0]   CYCLONE_A;
	output	CYCLONE_A_OUT;
	output	[3:0]	CYCLONE_B;

	output	[7:0]  SEG_A;


	output	[3:0]  SEG_SEL;




	output	[4:0]  LED;


	wire     [3:0] SEG_A_VAL;
	wire     [3:0] SEG_B_VAL;
	wire     [3:0] SEG_C_VAL;
	wire     [3:0] SEG_D_VAL;

	wire     [2:0] PSW_SIG;


	wire	[3:0]  SEG_SEL;
	wire	[7:0]  SEG_A_0;
	wire	[7:0]  SEG_B_0;
	wire	[7:0]  SEG_C_0;
	wire	[7:0]  SEG_D_0;



	assign  LED[0] = CYCLONE_A[0];
	assign  LED[1] = CYCLONE_A[1];
	assign  LED[2] = CYCLONE_A[2];
	assign  LED[3] = CYCLONE_A[3];

	assign  LED[4] = CYCLONE_A_OUT;
	assign  CYCLONE_B[0] = PSW[0];
	assign  CYCLONE_B[1] = PSW[1];
	assign  CYCLONE_B[2] = PSW[2];
	assign  CYCLONE_B[3] = PSW[3];

	assign  CYCLONE_A_OUT = ~SEG_D_VAL[3] & ~SEG_D_VAL[2] & ~SEG_D_VAL[1] & ~SEG_D_VAL[0] ;



	ctrg_rmv	ctrg_rmv1(

			.CLK(CLK), 
			.RSTN(RSTN),
			.PSW(CYCLONE_A[6:4]),


			.PSW_SIG(PSW_SIG)
			);

	watch_body	watch_body1(

			.CLK(CLK),
			.RSTN(RSTN),
			.RST_PULS(PSW_SIG[0]),
			.INC_PULS(PSW_SIG[1]),
			.DEC_PULS(PSW_SIG[2]),


			.SEG_A_VAL(SEG_A_VAL),
			.SEG_B_VAL(SEG_B_VAL),
			.SEG_C_VAL(SEG_C_VAL),
			.SEG_D_VAL(SEG_D_VAL)
			);


	time_display	time_display1(

			.CLK(CLK),
			.RSTN(RSTN),
			.SEG_A_VAL(SEG_A_VAL),
			.SEG_B_VAL(SEG_B_VAL),
			.SEG_C_VAL(SEG_C_VAL),
			.SEG_D_VAL(SEG_D_VAL),



			.SEG_A(SEG_A_0),
			.SEG_B(SEG_B_0),
			.SEG_C(SEG_C_0),
			.SEG_D(SEG_D_0)




			);



	dynamic_display	dynamic_display1(

			.CLK(CLK),
			.RSTN(RSTN),
			.RSW(RSW),
			.SEG_A_0(SEG_A_0),
			.SEG_B_0(SEG_B_0),
			.SEG_C_0(SEG_C_0),
			.SEG_D_0(SEG_D_0),


			.SEG_A(SEG_A),
			.SEG_SEL(SEG_SEL)
			);

endmodule
module stop_watch (

		CLK,
		RSTN,


		PSW,
		RSW,


		SEG_A,


		SEG_SEL,





		LED,

		CYCLONE_A_OUT,
		CYCLONE_A,
		CYCLONE_B
		);




	input	CLK;
	input	RSTN;

	input	[3:0]  PSW;
	input	[3:0]  RSW;



	input	[6:0]   CYCLONE_A;
	output	CYCLONE_A_OUT;
	output	[3:0]	CYCLONE_B;

	output	[7:0]  SEG_A;


	output	[3:0]  SEG_SEL;




	output	[4:0]  LED;


	wire     [3:0] SEG_A_VAL;
	wire     [3:0] SEG_B_VAL;
	wire     [3:0] SEG_C_VAL;
	wire     [3:0] SEG_D_VAL;

	wire     [2:0] PSW_SIG;


	wire	[3:0]  SEG_SEL;
	wire	[7:0]  SEG_A_0;
	wire	[7:0]  SEG_B_0;
	wire	[7:0]  SEG_C_0;
	wire	[7:0]  SEG_D_0;



	assign  LED[0] = CYCLONE_A[0];
	assign  LED[1] = CYCLONE_A[1];
	assign  LED[2] = CYCLONE_A[2];
	assign  LED[3] = CYCLONE_A[3];

	assign  LED[4] = CYCLONE_A_OUT;
	assign  CYCLONE_B[0] = PSW[0];
	assign  CYCLONE_B[1] = PSW[1];
	assign  CYCLONE_B[2] = PSW[2];
	assign  CYCLONE_B[3] = PSW[3];

	assign  CYCLONE_A_OUT = ~SEG_D_VAL[3] & ~SEG_D_VAL[2] & ~SEG_D_VAL[1] & ~SEG_D_VAL[0] ;



	ctrg_rmv	ctrg_rmv1(

			.CLK(CLK), 
			.RSTN(RSTN),
			.PSW(CYCLONE_A[6:4]),


			.PSW_SIG(PSW_SIG)
			);

	watch_body	watch_body1(

			.CLK(CLK),
			.RSTN(RSTN),
			.RST_PULS(PSW_SIG[0]),
			.INC_PULS(PSW_SIG[1]),
			.DEC_PULS(PSW_SIG[2]),


			.SEG_A_VAL(SEG_A_VAL),
			.SEG_B_VAL(SEG_B_VAL),
			.SEG_C_VAL(SEG_C_VAL),
			.SEG_D_VAL(SEG_D_VAL)
			);


	time_display	time_display1(

			.CLK(CLK),
			.RSTN(RSTN),
			.SEG_A_VAL(SEG_A_VAL),
			.SEG_B_VAL(SEG_B_VAL),
			.SEG_C_VAL(SEG_C_VAL),
			.SEG_D_VAL(SEG_D_VAL),



			.SEG_A(SEG_A_0),
			.SEG_B(SEG_B_0),
			.SEG_C(SEG_C_0),
			.SEG_D(SEG_D_0)




			);



	dynamic_display	dynamic_display1(

			.CLK(CLK),
			.RSTN(RSTN),
			.RSW(RSW),
			.SEG_A_0(SEG_A_0),
			.SEG_B_0(SEG_B_0),
			.SEG_C_0(SEG_C_0),
			.SEG_D_0(SEG_D_0),


			.SEG_A(SEG_A),
			.SEG_SEL(SEG_SEL)
			);

endmodule