data/full_repos/permissive/115035459/verilog/src/lib/fifo.v
 line:304: before: "if"
1: b'%Error: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:6: Cannot find include file: generic.v\n`include "generic.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/generic.v\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/generic.v.v\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/generic.v.sv\n             generic.v\n             generic.v.v\n             generic.v.sv\n             obj_dir/generic.v\n             obj_dir/generic.v.v\n             obj_dir/generic.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:7: Cannot find include file: RAM8.v\n`include "RAM8.v" \n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:161: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d00; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d00; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d01; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d01; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d02; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d02; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:167: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d03; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:167: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d03; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:168: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d04; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:168: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d04; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:169: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d05; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:169: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d05; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:170: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d06; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:170: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d06; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d07; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d07; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:173: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d08; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:173: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d08; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d09; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d09; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d10; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d10; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:176: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d11; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:176: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d11; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:177: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d12; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:177: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d12; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d13; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d13; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d14; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d14; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d15; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d15; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:181: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:183: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d16; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:183: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d16; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:184: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d17; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d17; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:187: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:189: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:189: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:190: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:190: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:191: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:191: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:193: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:193: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:194: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:194: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:195: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:195: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:196: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:196: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:197: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:198: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:198: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:199: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:199: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:200: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:200: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:201: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:201: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:202: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:202: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:203: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:203: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:204: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:204: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:205: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:205: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:206: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:208: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:208: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:209: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:211: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d18; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:211: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d18; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:212: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d19; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:212: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d19; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:213: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d20; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:213: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d20; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:214: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d21; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:214: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d21; pre_write_enable <= 1; #4; pre_write_enable <= 0;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:215: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:217: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:217: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:218: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:218: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:219: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:219: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:220: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:220: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:221: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:223: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d22; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:223: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d22; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:224: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d23; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:224: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d23; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d24; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d24; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:226: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d25; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:226: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d25; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:227: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d26; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:227: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d26; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:228: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d27; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:228: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d27; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:229: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d28; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:229: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d28; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:230: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d29; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:230: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d29; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:231: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:232: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d31; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:232: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d31; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:233: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d32; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:233: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d32; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:234: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d33; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:234: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d33; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:235: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d34; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:235: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d34; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:236: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d35; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:236: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d35; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:237: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d36; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:237: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d36; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:238: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d37; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:238: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d37; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:239: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d38; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:239: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d38; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:240: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:241: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d39; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:241: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d39; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:242: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d40; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:242: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d40; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:243: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d41; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:243: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d41; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:244: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d42; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:244: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_data_in <= 8\'d42; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;\n                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:245: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:247: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:247: Unsupported: Ignoring delay on this delayed statement.\n  #40; pre_read_enable <= 1; #4; pre_read_enable <= 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:248: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/fifo.v:250: Unsupported: Ignoring delay on this delayed statement.\n  #100; $fclose(r); $fclose(w);\n  ^\n%Error: Exiting due to 2 error(s), 144 warning(s)\n'
module fifo_single_clock_tb;
	localparam DATA_WIDTH = 8;
	localparam LOG2_OF_DEPTH = 4;
	wire clock;
	wire full;
	wire empty;
	wire almost_full;
	wire almost_empty;
	wire full_or_almost_full;
	wire empty_or_almost_empty;
	wire [DATA_WIDTH-1:0] data_out;
	reg pre_reset = 1;
	reg reset = 1;
	reg [DATA_WIDTH-1:0] pre_data_in = 0;
	reg [DATA_WIDTH-1:0] data_in = 0;
	reg pre_write_enable = 0;
	reg write_enable = 0;
	reg pre_read_enable = 0;
	reg read_enable = 0;
	if (0) begin
		fifo_single_clock #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_DEPTH(LOG2_OF_DEPTH)) fsc (.clock(clock), .reset(reset),
			.data_in(data_in), .write_enable(write_enable), .full(full), .almost_full(almost_full), .full_or_almost_full(full_or_almost_full),
			.data_out(data_out), .read_enable(read_enable), .empty(empty), .almost_empty(almost_empty), .empty_or_almost_empty(empty_or_almost_empty));
	end else begin
		fifo_single_clock_using_single_bram #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_DEPTH(LOG2_OF_DEPTH)) fsc (.clock(clock), .reset(reset),
			.data_in(data_in), .write_enable(write_enable), .full(full), .almost_full(almost_full), .full_or_almost_full(full_or_almost_full),
			.data_out(data_out), .read_enable(read_enable), .empty(empty), .almost_empty(almost_empty), .empty_or_almost_empty(empty_or_almost_empty));
	end
	integer r;
	integer w;
	initial begin
		#40;
		r = $fopen("fifo-reads", "w");
		w = $fopen("fifo-writes", "w");
		#40;
		pre_reset <= 0;

		#40; pre_data_in <= 8'd00; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd01; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd02; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd03; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd04; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd05; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd06; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd07; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40;
		#40; pre_data_in <= 8'd08; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd09; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd10; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd11; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd12; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd13; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd14; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd15; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40;

		#40; pre_data_in <= 8'd16; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40;

		#40; pre_data_in <= 8'd17; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40;

		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40;

		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40;

		#40; pre_data_in <= 8'd18; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd19; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd20; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd21; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40;

		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40;

		#40; pre_data_in <= 8'd22; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd23; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd24; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd25; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd26; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd27; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd28; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd29; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40;
		#40; pre_data_in <= 8'd31; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd32; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd33; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd34; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd35; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd36; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd37; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd38; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40;
		#40; pre_data_in <= 8'd39; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd40; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd41; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd42; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40;

		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40;

		#100; $fclose(r); $fclose(w);
	end
	clock #(.FREQUENCY_OF_CLOCK_HZ(250000000)) c (.clock(clock));
	reg [31:0] write_counter = 0;
	reg [31:0] read_counter = 0;
	localparam CHECK_MEM_DEPTH = 256;
	reg [DATA_WIDTH-1:0] mem [CHECK_MEM_DEPTH-1:0];
	always @(posedge clock) begin
		if (write_enable && ~full) begin
			$display("[%4d] %d (write)", write_counter, data_in);
			$fwrite(w, "%d\n", data_in);
			write_counter <= write_counter + 1'd1;
		end
		if (read_enable && ~empty) begin
			$display("[%4d] %d (read)", read_counter, data_out);
			$fwrite(r, "%d\n", data_out);
			read_counter <= read_counter + 1'd1;
		end
		data_in <= pre_data_in;
		write_enable <= pre_write_enable;
		read_enable <= pre_read_enable;
		reset <= pre_reset;
	end
endmodule
module fifo_single_clock_tb;

	localparam DATA_WIDTH = 8;
	localparam LOG2_OF_DEPTH = 4;
	wire clock;
	wire full;
	wire empty;
	wire almost_full;
	wire almost_empty;
	wire full_or_almost_full;
	wire empty_or_almost_empty;
	wire [DATA_WIDTH-1:0] data_out;
	reg pre_reset = 1;
	reg reset = 1;
	reg [DATA_WIDTH-1:0] pre_data_in = 0;
	reg [DATA_WIDTH-1:0] data_in = 0;
	reg pre_write_enable = 0;
	reg write_enable = 0;
	reg pre_read_enable = 0;
	reg read_enable = 0;
	if (0) begin
		fifo_single_clock #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_DEPTH(LOG2_OF_DEPTH)) fsc (.clock(clock), .reset(reset),
			.data_in(data_in), .write_enable(write_enable), .full(full), .almost_full(almost_full), .full_or_almost_full(full_or_almost_full),
			.data_out(data_out), .read_enable(read_enable), .empty(empty), .almost_empty(almost_empty), .empty_or_almost_empty(empty_or_almost_empty));
	end else begin
		fifo_single_clock_using_single_bram #(.DATA_WIDTH(DATA_WIDTH), .LOG2_OF_DEPTH(LOG2_OF_DEPTH)) fsc (.clock(clock), .reset(reset),
			.data_in(data_in), .write_enable(write_enable), .full(full), .almost_full(almost_full), .full_or_almost_full(full_or_almost_full),
			.data_out(data_out), .read_enable(read_enable), .empty(empty), .almost_empty(almost_empty), .empty_or_almost_empty(empty_or_almost_empty));
	end
	integer r;
	integer w;
	initial begin
		#40;
		r = $fopen("fifo-reads", "w");
		w = $fopen("fifo-writes", "w");
		#40;
		pre_reset <= 0;

		#40; pre_data_in <= 8'd00; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd01; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd02; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd03; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd04; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd05; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd06; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd07; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40;
		#40; pre_data_in <= 8'd08; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd09; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd10; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd11; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd12; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd13; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd14; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd15; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40;

		#40; pre_data_in <= 8'd16; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40;

		#40; pre_data_in <= 8'd17; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40;

		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40;

		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40;

		#40; pre_data_in <= 8'd18; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd19; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd20; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40; pre_data_in <= 8'd21; pre_write_enable <= 1; #4; pre_write_enable <= 0;
		#40;

		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40;

		#40; pre_data_in <= 8'd22; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd23; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd24; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd25; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd26; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd27; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd28; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd29; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40;
		#40; pre_data_in <= 8'd31; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd32; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd33; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd34; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd35; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd36; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd37; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd38; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40;
		#40; pre_data_in <= 8'd39; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd40; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd41; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40; pre_data_in <= 8'd42; pre_write_enable <= 1; pre_read_enable <= 1; #4; pre_write_enable <= 0; pre_read_enable <= 0;
		#40;

		#40; pre_read_enable <= 1; #4; pre_read_enable <= 0;
		#40;

		#100; $fclose(r); $fclose(w);
	end
	clock #(.FREQUENCY_OF_CLOCK_HZ(250000000)) c (.clock(clock));
	reg [31:0] write_counter = 0;
	reg [31:0] read_counter = 0;
	localparam CHECK_MEM_DEPTH = 256;
	reg [DATA_WIDTH-1:0] mem [CHECK_MEM_DEPTH-1:0];
	always @(posedge clock) begin
		if (write_enable && ~full) begin
			$display("[%4d] %d (write)", write_counter, data_in);
			$fwrite(w, "%d\n", data_in);
			write_counter <= write_counter + 1'd1;
		end
		if (read_enable && ~empty) begin
			$display("[%4d] %d (read)", read_counter, data_out);
			$fwrite(r, "%d\n", data_out);
			read_counter <= read_counter + 1'd1;
		end
		data_in <= pre_data_in;
		write_enable <= pre_write_enable;
		read_enable <= pre_read_enable;
		reset <= pre_reset;
	end
endmodule