data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl/dual_dma_v1_0_S_AXI.v
1: b'%Error: data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl/dual_dma_v1_0_S_AXI.v:142: Cannot find include file: global_defs.vh\n `include "global_defs.vh" \n          ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl,data/full_repos/permissive/135295301/global_defs.vh\n             data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl,data/full_repos/permissive/135295301/global_defs.vh.v\n             data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl,data/full_repos/permissive/135295301/global_defs.vh.sv\n             global_defs.vh\n             global_defs.vh.v\n             global_defs.vh.sv\n             obj_dir/global_defs.vh\n             obj_dir/global_defs.vh.v\n             obj_dir/global_defs.vh.sv\n%Error: data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl/dual_dma_v1_0_S_AXI.v:886: Define or directive not defined: \'`CMD_READ\'\n        if ( cmd_read_m64_s_axis_tready == 1\'b1 && cmd_read_ul_s_axis_tready == 1\'b1 && S_AXI_WDATA == `CMD_READ )\n                                                                                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl/dual_dma_v1_0_S_AXI.v:886: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if ( cmd_read_m64_s_axis_tready == 1\'b1 && cmd_read_ul_s_axis_tready == 1\'b1 && S_AXI_WDATA == `CMD_READ )\n                                                                                                                 ^\n%Error: data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl/dual_dma_v1_0_S_AXI.v:891: Define or directive not defined: \'`CMD_WRITE\'\n        else if ( cmd_write_m64_s_axis_tready == 1\'b1 && cmd_write_ul_s_axis_tready == 1\'b1 && S_AXI_WDATA == `CMD_WRITE )\n                                                                                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl/dual_dma_v1_0_S_AXI.v:891: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        else if ( cmd_write_m64_s_axis_tready == 1\'b1 && cmd_write_ul_s_axis_tready == 1\'b1 && S_AXI_WDATA == `CMD_WRITE )\n                                                                                                                         ^\n%Error: data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl/dual_dma_v1_0_S_AXI.v:896: syntax error, unexpected else\n        else if ( S_AXI_WDATA == `CMD_ACK )\n        ^~~~\n%Error: data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl/dual_dma_v1_0_S_AXI.v:896: Define or directive not defined: \'`CMD_ACK\'\n        else if ( S_AXI_WDATA == `CMD_ACK )\n                                 ^~~~~~~~\n%Error: Cannot continue\n'
module dual_dma_v1_0_S_AXI #
	(


		parameter integer C_S_AXI_CMD_64_WIDTH	= 32,
		parameter integer C_S_AXI_CMD_UL_WIDTH	= 32,

		parameter integer C_S_AXI_STS_64_WIDTH	= 32,
		parameter integer C_S_AXI_STS_UL_WIDTH	= 32,





		parameter integer C_S_AXI_DATA_WIDTH	= 32,

		parameter integer C_S_AXI_ADDR_WIDTH	= 7
	)
	(


		output reg IRQ,


		output reg cmd_read_m64_s_axis_tvalid,
		input wire cmd_read_m64_s_axis_tready,
		output wire [C_S_AXI_CMD_64_WIDTH - 1 : 0] cmd_read_m64_s_axis_tdata,
		output reg cmd_write_m64_s_axis_tvalid,
		input wire cmd_write_m64_s_axis_tready,
		output wire [C_S_AXI_CMD_64_WIDTH - 1 : 0] cmd_write_m64_s_axis_tdata,


		input wire sts_read_m64_m_axis_tvalid,
		output reg sts_read_m64_m_axis_tready,
		input wire [C_S_AXI_STS_64_WIDTH - 1 : 0] sts_read_m64_m_axis_tdata,
		input wire sts_write_m64_m_axis_tvalid,
		output reg sts_write_m64_m_axis_tready,
		input wire [C_S_AXI_STS_64_WIDTH - 1 : 0] sts_write_m64_m_axis_tdata,


		output reg cmd_read_ul_s_axis_tvalid,
		input wire cmd_read_ul_s_axis_tready,
		output wire [C_S_AXI_CMD_UL_WIDTH - 1 : 0] cmd_read_ul_s_axis_tdata,
		output reg cmd_write_ul_s_axis_tvalid,
		input wire cmd_write_ul_s_axis_tready,
		output wire [C_S_AXI_CMD_UL_WIDTH - 1 : 0] cmd_write_ul_s_axis_tdata,


		input wire sts_read_ul_m_axis_tvalid,
		output reg sts_read_ul_m_axis_tready,
		input wire [C_S_AXI_STS_UL_WIDTH - 1 : 0] sts_read_ul_m_axis_tdata,
		input wire sts_write_ul_m_axis_tvalid,
		output reg sts_write_ul_m_axis_tready,
		input wire [C_S_AXI_STS_UL_WIDTH - 1 : 0] sts_write_ul_m_axis_tdata,





		input wire  S_AXI_ACLK,

		input wire  S_AXI_ARESETN,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



		input wire [2 : 0] S_AXI_AWPROT,


		input wire  S_AXI_AWVALID,


		output wire  S_AXI_AWREADY,

		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


		input wire  S_AXI_WVALID,


		output wire  S_AXI_WREADY,


		output wire [1 : 0] S_AXI_BRESP,


		output wire  S_AXI_BVALID,


		input wire  S_AXI_BREADY,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



		input wire [2 : 0] S_AXI_ARPROT,


		input wire  S_AXI_ARVALID,


		output wire  S_AXI_ARREADY,

		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


		output wire [1 : 0] S_AXI_RRESP,


		output wire  S_AXI_RVALID,


		input wire  S_AXI_RREADY
	);

	`include "global_defs.vh"



	reg toggle_irq;
	wire [7:0] cmd_offset;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] status;


	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;






	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 4 - (C_S_AXI_DATA_WIDTH/64);




	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg4;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg5;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg6;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg7;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg8;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg9;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg10;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg11;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg12;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg13;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg14;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg15;

	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;



	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin




	          axi_awready <= 1'b1;
	        end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin

	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
	        begin




	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      slv_reg0 <= 0;
	      slv_reg1 <= 0;
	      slv_reg2 <= 0;
	      slv_reg3 <= 0;
	      slv_reg4 <= 0;
	      slv_reg5 <= 0;
	      slv_reg6 <= 0;
	      slv_reg7 <= 0;
	      slv_reg8 <= 0;
	      slv_reg9 <= 0;
	      slv_reg10 <= 0;
	      slv_reg11 <= 0;
	      slv_reg12 <= 0;
	      slv_reg13 <= 0;
	      slv_reg14 <= 0;
	      slv_reg15 <= 0;

	    end 
	  else begin
	    if (slv_reg_wren)
	      begin
	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	          5'h00:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h01:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h02:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h03:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h04:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h05:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h06:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h07:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h08:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h09:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0A:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0B:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0C:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0D:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0E:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0F:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  

	          default : begin
	                      slv_reg0 <= slv_reg0;
	                      slv_reg1 <= slv_reg1;
	                      slv_reg2 <= slv_reg2;
	                      slv_reg3 <= slv_reg3;
	                      slv_reg4 <= slv_reg4;
	                      slv_reg5 <= slv_reg5;
	                      slv_reg6 <= slv_reg6;
	                      slv_reg7 <= slv_reg7;
	                      slv_reg8 <= slv_reg8;
	                      slv_reg9 <= slv_reg9;
	                      slv_reg10 <= slv_reg10;
	                      slv_reg11 <= slv_reg11;
	                      slv_reg12 <= slv_reg12;
	                      slv_reg13 <= slv_reg13;
	                      slv_reg14 <= slv_reg14;
	                      slv_reg15 <= slv_reg15;

	                    end
	        endcase
	      end
	  end
	end    







	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin

	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0;
	        end
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 


	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   








	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin

	          axi_arready <= 1'b1;

	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin

	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0;
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin

	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    




	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin

	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	        5'h00   : reg_data_out <= slv_reg0;
	        5'h01   : reg_data_out <= slv_reg1;
	        5'h02   : reg_data_out <= slv_reg2;
	        5'h03   : reg_data_out <= slv_reg3;
	        5'h04   : reg_data_out <= slv_reg4;
	        5'h05   : reg_data_out <= slv_reg5;
	        5'h06   : reg_data_out <= slv_reg6;
	        5'h07   : reg_data_out <= slv_reg7;
	        5'h08   : reg_data_out <= status;
	        5'h09   : reg_data_out <= slv_reg9;
	        5'h0A   : reg_data_out <= slv_reg10;
	        5'h0B   : reg_data_out <= slv_reg11;
	        5'h0C   : reg_data_out <= slv_reg12;
	        5'h0D   : reg_data_out <= slv_reg13;
	        5'h0E   : reg_data_out <= slv_reg14;
	        5'h0F   : reg_data_out <= slv_reg15;

	        default : reg_data_out <= 0;
	      endcase
	end


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    



	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;
	        end   
	    end
	end    















	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      IRQ  <= 1'b0;
	      status  <= 0;
	      sts_read_m64_m_axis_tready  <= 1'b0;
	      sts_write_m64_m_axis_tready <= 1'b0;
	      sts_read_ul_m_axis_tready  <= 1'b0;
	      sts_write_ul_m_axis_tready <= 1'b0;
	    end 
	  else
	    begin
	      if (toggle_irq == 1'b1)
	        begin
	          IRQ <= 1'b0;
	          sts_read_m64_m_axis_tready  <= 1'b0;
	          sts_write_m64_m_axis_tready <= 1'b0;
	          sts_read_ul_m_axis_tready  <= 1'b0;
	          sts_write_ul_m_axis_tready <= 1'b0;
	          status <= 0;
	        end
	      else if (sts_read_m64_m_axis_tvalid == 1'b1 && sts_read_ul_m_axis_tvalid == 1'b1 && IRQ == 1'b0)
	        begin
	          IRQ <= 1'b1;
	          sts_read_m64_m_axis_tready <= 1'b1;
	          sts_read_ul_m_axis_tready <= 1'b1;
	          status <= sts_read_m64_m_axis_tdata;
	        end
	      else if (sts_write_m64_m_axis_tvalid == 1'b1 && sts_write_ul_m_axis_tvalid == 1'b1 && IRQ == 1'b0)
	        begin
	          IRQ <= 1'b1;
	          sts_write_m64_m_axis_tready <= 1'b1;
	          sts_write_ul_m_axis_tready <= 1'b1;
	          status <= sts_write_m64_m_axis_tdata;
	        end
	      else
	        begin
	          sts_read_m64_m_axis_tready  <= 1'b0;
	          sts_write_m64_m_axis_tready <= 1'b0;
	          sts_read_ul_m_axis_tready  <= 1'b0;
	          sts_write_ul_m_axis_tready <= 1'b0;
	        end
	    end
	end 

	generate

	    wire [95:0] tmp;

	    if(C_S_AXI_DATA_WIDTH == 32)
	      begin
		assign cmd_read_m64_s_axis_tdata = {slv_reg1, slv_reg0, slv_reg4, slv_reg5};
		assign cmd_write_m64_s_axis_tdata = {slv_reg1, slv_reg0, slv_reg4, slv_reg5};

		assign tmp = {slv_reg2, slv_reg4, slv_reg5};
		assign cmd_read_ul_s_axis_tdata = tmp[C_S_AXI_CMD_UL_WIDTH-1:0];
		assign cmd_write_ul_s_axis_tdata = tmp[C_S_AXI_CMD_UL_WIDTH-1:0];
		assign cmd_offset = 8'h06;
	      end
	    else if(C_S_AXI_DATA_WIDTH == 64)
	      begin
		assign cmd_read_m64_s_axis_tdata = {slv_reg0, slv_reg2[31:0], slv_reg2[63:32]};
		assign cmd_write_m64_s_axis_tdata = {slv_reg0, slv_reg2[31:0], slv_reg2[63:32]};

		assign tmp = {slv_reg1[31:0], slv_reg2[31:0], slv_reg2[63:32]};
		assign cmd_read_ul_s_axis_tdata = tmp[C_S_AXI_CMD_UL_WIDTH-1:0];
		assign cmd_write_ul_s_axis_tdata = tmp[C_S_AXI_CMD_UL_WIDTH-1:0];
		assign cmd_offset = 8'h03;
	      end
	    else
	      begin
		assign tmp = 0;
		assign cmd_read_m64_s_axis_tdata = 0;
		assign cmd_write_m64_s_axis_tdata = 0;
		assign cmd_read_ul_s_axis_tdata = 0;
		assign cmd_write_ul_s_axis_tdata = 0;
		assign cmd_offset = 8'hFF;
	      end
	endgenerate


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      toggle_irq <= 1'b0;
	      cmd_read_m64_s_axis_tvalid <= 1'b0;
	      cmd_write_m64_s_axis_tvalid <= 1'b0;
	      cmd_read_ul_s_axis_tvalid <= 1'b0;
	      cmd_write_ul_s_axis_tvalid <= 1'b0;
	    end 
	  else
	    begin
	     if ( slv_reg_wren == 1'b1 && axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == cmd_offset )
	       begin
	      	if ( cmd_read_m64_s_axis_tready == 1'b1 && cmd_read_ul_s_axis_tready == 1'b1 && S_AXI_WDATA == `CMD_READ )
	           begin
	             cmd_read_m64_s_axis_tvalid <= 1'b1;
	             cmd_read_ul_s_axis_tvalid <= 1'b1;
	           end
	      	else if ( cmd_write_m64_s_axis_tready == 1'b1 && cmd_write_ul_s_axis_tready == 1'b1 && S_AXI_WDATA == `CMD_WRITE )
	           begin
	             cmd_write_m64_s_axis_tvalid <= 1'b1;
	             cmd_write_ul_s_axis_tvalid <= 1'b1;
	           end
	      	else if ( S_AXI_WDATA == `CMD_ACK )
	           begin
	             toggle_irq <= 1'b1;
	           end
	       end    
	     else
	       	begin
		  toggle_irq <= 1'b0;
		  cmd_read_m64_s_axis_tvalid  <= 1'b0;
		  cmd_write_m64_s_axis_tvalid <= 1'b0;
		  cmd_read_ul_s_axis_tvalid  <= 1'b0;
		  cmd_write_ul_s_axis_tvalid <= 1'b0;
		end 
	    end
	end



	endmodule
module dual_dma_v1_0_S_AXI #
	(


		parameter integer C_S_AXI_CMD_64_WIDTH	= 32,
		parameter integer C_S_AXI_CMD_UL_WIDTH	= 32,

		parameter integer C_S_AXI_STS_64_WIDTH	= 32,
		parameter integer C_S_AXI_STS_UL_WIDTH	= 32,





		parameter integer C_S_AXI_DATA_WIDTH	= 32,

		parameter integer C_S_AXI_ADDR_WIDTH	= 7
	)
	(


		output reg IRQ,


		output reg cmd_read_m64_s_axis_tvalid,
		input wire cmd_read_m64_s_axis_tready,
		output wire [C_S_AXI_CMD_64_WIDTH - 1 : 0] cmd_read_m64_s_axis_tdata,
		output reg cmd_write_m64_s_axis_tvalid,
		input wire cmd_write_m64_s_axis_tready,
		output wire [C_S_AXI_CMD_64_WIDTH - 1 : 0] cmd_write_m64_s_axis_tdata,


		input wire sts_read_m64_m_axis_tvalid,
		output reg sts_read_m64_m_axis_tready,
		input wire [C_S_AXI_STS_64_WIDTH - 1 : 0] sts_read_m64_m_axis_tdata,
		input wire sts_write_m64_m_axis_tvalid,
		output reg sts_write_m64_m_axis_tready,
		input wire [C_S_AXI_STS_64_WIDTH - 1 : 0] sts_write_m64_m_axis_tdata,


		output reg cmd_read_ul_s_axis_tvalid,
		input wire cmd_read_ul_s_axis_tready,
		output wire [C_S_AXI_CMD_UL_WIDTH - 1 : 0] cmd_read_ul_s_axis_tdata,
		output reg cmd_write_ul_s_axis_tvalid,
		input wire cmd_write_ul_s_axis_tready,
		output wire [C_S_AXI_CMD_UL_WIDTH - 1 : 0] cmd_write_ul_s_axis_tdata,


		input wire sts_read_ul_m_axis_tvalid,
		output reg sts_read_ul_m_axis_tready,
		input wire [C_S_AXI_STS_UL_WIDTH - 1 : 0] sts_read_ul_m_axis_tdata,
		input wire sts_write_ul_m_axis_tvalid,
		output reg sts_write_ul_m_axis_tready,
		input wire [C_S_AXI_STS_UL_WIDTH - 1 : 0] sts_write_ul_m_axis_tdata,





		input wire  S_AXI_ACLK,

		input wire  S_AXI_ARESETN,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



		input wire [2 : 0] S_AXI_AWPROT,


		input wire  S_AXI_AWVALID,


		output wire  S_AXI_AWREADY,

		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


		input wire  S_AXI_WVALID,


		output wire  S_AXI_WREADY,


		output wire [1 : 0] S_AXI_BRESP,


		output wire  S_AXI_BVALID,


		input wire  S_AXI_BREADY,

		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



		input wire [2 : 0] S_AXI_ARPROT,


		input wire  S_AXI_ARVALID,


		output wire  S_AXI_ARREADY,

		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


		output wire [1 : 0] S_AXI_RRESP,


		output wire  S_AXI_RVALID,


		input wire  S_AXI_RREADY
	);


	`include "global_defs.vh"



	reg toggle_irq;
	wire [7:0] cmd_offset;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] status;


	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;






	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 4 - (C_S_AXI_DATA_WIDTH/64);




	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg4;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg5;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg6;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg7;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg8;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg9;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg10;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg11;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg12;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg13;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg14;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg15;

	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;



	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin




	          axi_awready <= 1'b1;
	        end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin

	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
	        begin




	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      slv_reg0 <= 0;
	      slv_reg1 <= 0;
	      slv_reg2 <= 0;
	      slv_reg3 <= 0;
	      slv_reg4 <= 0;
	      slv_reg5 <= 0;
	      slv_reg6 <= 0;
	      slv_reg7 <= 0;
	      slv_reg8 <= 0;
	      slv_reg9 <= 0;
	      slv_reg10 <= 0;
	      slv_reg11 <= 0;
	      slv_reg12 <= 0;
	      slv_reg13 <= 0;
	      slv_reg14 <= 0;
	      slv_reg15 <= 0;

	    end 
	  else begin
	    if (slv_reg_wren)
	      begin
	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	          5'h00:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h01:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h02:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h03:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h04:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h05:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h06:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h07:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h08:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h09:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0A:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0B:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0C:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0D:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0E:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0F:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  

	          default : begin
	                      slv_reg0 <= slv_reg0;
	                      slv_reg1 <= slv_reg1;
	                      slv_reg2 <= slv_reg2;
	                      slv_reg3 <= slv_reg3;
	                      slv_reg4 <= slv_reg4;
	                      slv_reg5 <= slv_reg5;
	                      slv_reg6 <= slv_reg6;
	                      slv_reg7 <= slv_reg7;
	                      slv_reg8 <= slv_reg8;
	                      slv_reg9 <= slv_reg9;
	                      slv_reg10 <= slv_reg10;
	                      slv_reg11 <= slv_reg11;
	                      slv_reg12 <= slv_reg12;
	                      slv_reg13 <= slv_reg13;
	                      slv_reg14 <= slv_reg14;
	                      slv_reg15 <= slv_reg15;

	                    end
	        endcase
	      end
	  end
	end    







	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin

	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0;
	        end
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 


	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   








	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin

	          axi_arready <= 1'b1;

	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin

	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0;
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin

	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    




	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin

	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	        5'h00   : reg_data_out <= slv_reg0;
	        5'h01   : reg_data_out <= slv_reg1;
	        5'h02   : reg_data_out <= slv_reg2;
	        5'h03   : reg_data_out <= slv_reg3;
	        5'h04   : reg_data_out <= slv_reg4;
	        5'h05   : reg_data_out <= slv_reg5;
	        5'h06   : reg_data_out <= slv_reg6;
	        5'h07   : reg_data_out <= slv_reg7;
	        5'h08   : reg_data_out <= status;
	        5'h09   : reg_data_out <= slv_reg9;
	        5'h0A   : reg_data_out <= slv_reg10;
	        5'h0B   : reg_data_out <= slv_reg11;
	        5'h0C   : reg_data_out <= slv_reg12;
	        5'h0D   : reg_data_out <= slv_reg13;
	        5'h0E   : reg_data_out <= slv_reg14;
	        5'h0F   : reg_data_out <= slv_reg15;

	        default : reg_data_out <= 0;
	      endcase
	end


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    



	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;
	        end   
	    end
	end    















	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      IRQ  <= 1'b0;
	      status  <= 0;
	      sts_read_m64_m_axis_tready  <= 1'b0;
	      sts_write_m64_m_axis_tready <= 1'b0;
	      sts_read_ul_m_axis_tready  <= 1'b0;
	      sts_write_ul_m_axis_tready <= 1'b0;
	    end 
	  else
	    begin
	      if (toggle_irq == 1'b1)
	        begin
	          IRQ <= 1'b0;
	          sts_read_m64_m_axis_tready  <= 1'b0;
	          sts_write_m64_m_axis_tready <= 1'b0;
	          sts_read_ul_m_axis_tready  <= 1'b0;
	          sts_write_ul_m_axis_tready <= 1'b0;
	          status <= 0;
	        end
	      else if (sts_read_m64_m_axis_tvalid == 1'b1 && sts_read_ul_m_axis_tvalid == 1'b1 && IRQ == 1'b0)
	        begin
	          IRQ <= 1'b1;
	          sts_read_m64_m_axis_tready <= 1'b1;
	          sts_read_ul_m_axis_tready <= 1'b1;
	          status <= sts_read_m64_m_axis_tdata;
	        end
	      else if (sts_write_m64_m_axis_tvalid == 1'b1 && sts_write_ul_m_axis_tvalid == 1'b1 && IRQ == 1'b0)
	        begin
	          IRQ <= 1'b1;
	          sts_write_m64_m_axis_tready <= 1'b1;
	          sts_write_ul_m_axis_tready <= 1'b1;
	          status <= sts_write_m64_m_axis_tdata;
	        end
	      else
	        begin
	          sts_read_m64_m_axis_tready  <= 1'b0;
	          sts_write_m64_m_axis_tready <= 1'b0;
	          sts_read_ul_m_axis_tready  <= 1'b0;
	          sts_write_ul_m_axis_tready <= 1'b0;
	        end
	    end
	end 

	generate

	    wire [95:0] tmp;

	    if(C_S_AXI_DATA_WIDTH == 32)
	      begin
		assign cmd_read_m64_s_axis_tdata = {slv_reg1, slv_reg0, slv_reg4, slv_reg5};
		assign cmd_write_m64_s_axis_tdata = {slv_reg1, slv_reg0, slv_reg4, slv_reg5};

		assign tmp = {slv_reg2, slv_reg4, slv_reg5};
		assign cmd_read_ul_s_axis_tdata = tmp[C_S_AXI_CMD_UL_WIDTH-1:0];
		assign cmd_write_ul_s_axis_tdata = tmp[C_S_AXI_CMD_UL_WIDTH-1:0];
		assign cmd_offset = 8'h06;
	      end
	    else if(C_S_AXI_DATA_WIDTH == 64)
	      begin
		assign cmd_read_m64_s_axis_tdata = {slv_reg0, slv_reg2[31:0], slv_reg2[63:32]};
		assign cmd_write_m64_s_axis_tdata = {slv_reg0, slv_reg2[31:0], slv_reg2[63:32]};

		assign tmp = {slv_reg1[31:0], slv_reg2[31:0], slv_reg2[63:32]};
		assign cmd_read_ul_s_axis_tdata = tmp[C_S_AXI_CMD_UL_WIDTH-1:0];
		assign cmd_write_ul_s_axis_tdata = tmp[C_S_AXI_CMD_UL_WIDTH-1:0];
		assign cmd_offset = 8'h03;
	      end
	    else
	      begin
		assign tmp = 0;
		assign cmd_read_m64_s_axis_tdata = 0;
		assign cmd_write_m64_s_axis_tdata = 0;
		assign cmd_read_ul_s_axis_tdata = 0;
		assign cmd_write_ul_s_axis_tdata = 0;
		assign cmd_offset = 8'hFF;
	      end
	endgenerate


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      toggle_irq <= 1'b0;
	      cmd_read_m64_s_axis_tvalid <= 1'b0;
	      cmd_write_m64_s_axis_tvalid <= 1'b0;
	      cmd_read_ul_s_axis_tvalid <= 1'b0;
	      cmd_write_ul_s_axis_tvalid <= 1'b0;
	    end 
	  else
	    begin
	     if ( slv_reg_wren == 1'b1 && axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == cmd_offset )
	       begin
	      	if ( cmd_read_m64_s_axis_tready == 1'b1 && cmd_read_ul_s_axis_tready == 1'b1 && S_AXI_WDATA == `CMD_READ )
	           begin
	             cmd_read_m64_s_axis_tvalid <= 1'b1;
	             cmd_read_ul_s_axis_tvalid <= 1'b1;
	           end
	      	else if ( cmd_write_m64_s_axis_tready == 1'b1 && cmd_write_ul_s_axis_tready == 1'b1 && S_AXI_WDATA == `CMD_WRITE )
	           begin
	             cmd_write_m64_s_axis_tvalid <= 1'b1;
	             cmd_write_ul_s_axis_tvalid <= 1'b1;
	           end
	      	else if ( S_AXI_WDATA == `CMD_ACK )
	           begin
	             toggle_irq <= 1'b1;
	           end
	       end    
	     else
	       	begin
		  toggle_irq <= 1'b0;
		  cmd_read_m64_s_axis_tvalid  <= 1'b0;
		  cmd_write_m64_s_axis_tvalid <= 1'b0;
		  cmd_read_ul_s_axis_tvalid  <= 1'b0;
		  cmd_write_ul_s_axis_tvalid <= 1'b0;
		end 
	    end
	end



	endmodule