data/full_repos/permissive/180199545/DigitalSSD/object.v
1: b'%Warning-WIDTH: data/full_repos/permissive/180199545/DigitalSSD/object.v:41: Operator LTE expects 11 bits on the RHS, but RHS\'s VARREF \'PollX\' generates 10 bits.\n                                                                           : ... In instance object\n   hit_out <= (ObjectX <= PollX & PollX <= ObjectX+ObjectW)&(ObjectY <= PollY & PollY <= ObjectY+ObjectH);\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/180199545/DigitalSSD/object.v:41: Operator LTE expects 11 bits on the LHS, but LHS\'s VARREF \'PollX\' generates 10 bits.\n                                                                           : ... In instance object\n   hit_out <= (ObjectX <= PollX & PollX <= ObjectX+ObjectW)&(ObjectY <= PollY & PollY <= ObjectY+ObjectH);\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/180199545/DigitalSSD/object.v:41: Operator LTE expects 10 bits on the RHS, but RHS\'s VARREF \'PollY\' generates 9 bits.\n                                                                           : ... In instance object\n   hit_out <= (ObjectX <= PollX & PollX <= ObjectX+ObjectW)&(ObjectY <= PollY & PollY <= ObjectY+ObjectH);\n                                                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/180199545/DigitalSSD/object.v:41: Operator LTE expects 10 bits on the LHS, but LHS\'s VARREF \'PollY\' generates 9 bits.\n                                                                           : ... In instance object\n   hit_out <= (ObjectX <= PollX & PollX <= ObjectX+ObjectW)&(ObjectY <= PollY & PollY <= ObjectY+ObjectH);\n                                                                                      ^~\n%Error: Exiting due to 4 warning(s)\n'
module object (
	input clk,
	input reset,

	input [10:0] ObjectX,
	input [9:0] ObjectY,
	input [9:0] ObjectW,
	input [8:0] ObjectH,
	
	input [9:0] PollX,
	input [8:0] PollY,
	
	output Hit
	);
	
	reg hit_out;
	

	always @ (posedge clk)
	begin
		if(reset)
		begin
			hit_out <= 1'b0;
		end
		else
		begin
			hit_out <= (ObjectX <= PollX & PollX <= ObjectX+ObjectW)&(ObjectY <= PollY & PollY <= ObjectY+ObjectH);
		end
	end
	
	assign Hit = hit_out;

endmodule
module object (
	input clk,
	input reset,

	input [10:0] ObjectX,
	input [9:0] ObjectY,
	input [9:0] ObjectW,
	input [8:0] ObjectH,
	
	input [9:0] PollX,
	input [8:0] PollY,
	
	output Hit
	);

	
	reg hit_out;
	

	always @ (posedge clk)
	begin
		if(reset)
		begin
			hit_out <= 1'b0;
		end
		else
		begin
			hit_out <= (ObjectX <= PollX & PollX <= ObjectX+ObjectW)&(ObjectY <= PollY & PollY <= ObjectY+ObjectH);
		end
	end
	
	assign Hit = hit_out;

endmodule