data/full_repos/permissive/143278/ivltests/shift5.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/shift5.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ArithmeticShiftTest;
  reg signed [31:0] in;
  reg        [5:0]  shift;
  reg signed [31:0] out;


  always@(*) out = in >>> shift;

  initial begin

    in = 32'sh80000000;
    shift = 6'd32;

    #1;


    if(out === (32'sh80000000 >>> 6'd32)) begin
      $display("PASS: 32'sh80000000 >>> 6'd32 = 0x%h", out);
    end
    else begin
      $display("FAIL: 32'sh80000000 >>> 6'd32 != 0x%h,",
        (32'sh80000000 >>> 6'd32), " actual = 0x%h.", out);
    end
  end
endmodule
module ArithmeticShiftTest;

  reg signed [31:0] in;
  reg        [5:0]  shift;
  reg signed [31:0] out;


  always@(*) out = in >>> shift;

  initial begin

    in = 32'sh80000000;
    shift = 6'd32;

    #1;


    if(out === (32'sh80000000 >>> 6'd32)) begin
      $display("PASS: 32'sh80000000 >>> 6'd32 = 0x%h", out);
    end
    else begin
      $display("FAIL: 32'sh80000000 >>> 6'd32 != 0x%h,",
        (32'sh80000000 >>> 6'd32), " actual = 0x%h.", out);
    end
  end
endmodule