data/full_repos/permissive/143278/ivltests/ptest006.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ptest006.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ptest006.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
  reg c;
  reg [3:0] a,b;
  wire [3:0] d;

  assign d = c ? a : b;

  initial begin
    a = 4'd5;
    b = 4'd6;
    c = 0;
    #1;
    if (d!==4'd6) begin
      $display("FAILED");
      $finish;
    end
    c = 1;
    #1;
    if (d!==4'd5) begin
      $display("FAILED");
      $finish;
    end
    $display("PASSED");
  end
endmodule
module main;

  reg c;
  reg [3:0] a,b;
  wire [3:0] d;

  assign d = c ? a : b;

  initial begin
    a = 4'd5;
    b = 4'd6;
    c = 0;
    #1;
    if (d!==4'd6) begin
      $display("FAILED");
      $finish;
    end
    c = 1;
    #1;
    if (d!==4'd5) begin
      $display("FAILED");
      $finish;
    end
    $display("PASSED");
  end
endmodule