data/full_repos/permissive/201488448/1_verilog/05_nor.v
data/verilator_xmls/36899496-5d70-44fc-accf-c1ac1cc4174c.xml
module top_module( 
    input a, 
    input b, 
    output out );

    assign	out = ~(a|b);
    
endmodule
module top_module( 
    input a, 
    input b, 
    output out );


    assign	out = ~(a|b);
    
endmodule