data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:1: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Util/Counter,data/full_repos/permissive/131921633/Data/Control/Control.v\n             data/full_repos/permissive/131921633/tv/Util/Counter,data/full_repos/permissive/131921633/Data/Control/Control.v.v\n             data/full_repos/permissive/131921633/tv/Util/Counter,data/full_repos/permissive/131921633/Data/Control/Control.v.sv\n             Data/Control/Control.v\n             Data/Control/Control.v.v\n             Data/Control/Control.v.sv\n             obj_dir/Data/Control/Control.v\n             obj_dir/Data/Control/Control.v.v\n             obj_dir/Data/Control/Control.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:6: Define or directive not defined: \'`Data_Control_Control_T\'\n`Data_Control_Control_T(logic) ctrl;\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:6: syntax error, unexpected \'(\'\n`Data_Control_Control_T(logic) ctrl;\n                        ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:19: Define or directive not defined: \'`Data_Control_Control_Clock\'\ninitial `Data_Control_Control_Clock(ctrl) = 0;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:19: syntax error, unexpected \'=\'\ninitial `Data_Control_Control_Clock(ctrl) = 0;\n                                          ^\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:20: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways #1 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:20: syntax error, unexpected \'=\'\nalways #1 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n                                            ^\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:20: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways #1 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n                                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:20: Unsupported: Ignoring delay on this delayed statement.\nalways #1 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:22: Unsupported: Ignoring delay on this delayed statement.\nalways #2 d = d - 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:25: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:28: Define or directive not defined: \'`Data_Control_Control_Reset\'\n `Data_Control_Control_Reset(ctrl) = 1;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:28: syntax error, unexpected \'=\'\n `Data_Control_Control_Reset(ctrl) = 1;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:30: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:31: Define or directive not defined: \'`Data_Control_Control_Reset\'\n `Data_Control_Control_Reset(ctrl) = 0;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:31: syntax error, unexpected \'=\'\n `Data_Control_Control_Reset(ctrl) = 0;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:33: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:36: Unsupported: Ignoring delay on this delayed statement.\n #32;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:39: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:42: Unsupported: Ignoring delay on this delayed statement.\n #8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:45: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:46: Define or directive not defined: \'`Data_Control_Control_Reset\'\n `Data_Control_Control_Reset(ctrl) = 1;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:46: syntax error, unexpected \'=\'\n `Data_Control_Control_Reset(ctrl) = 1;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:48: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:49: Define or directive not defined: \'`Data_Control_Control_Reset\'\n `Data_Control_Control_Reset(ctrl) = 0;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.sv:49: syntax error, unexpected \'=\'\n `Data_Control_Control_Reset(ctrl) = 0;\n                                   ^\n%Error: Exiting due to 16 error(s), 10 warning(s)\n'
module Util_Counter_counter_tb;

logic [3:0] d, q;
`Data_Control_Control_T(logic) ctrl;
logic load, enable;

Counter_counter #
	( .MAX (12)
	) DUT
	( .d (d)
	, .q (q)
	, .ctrl (ctrl)
	, .load (load)
	, .enable (enable)
	);

initial `Data_Control_Control_Clock(ctrl) = 0;
always #1 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);
initial d = 4'b0;
always #2 d = d - 1;

initial begin
	#0;
	load = 0;
	enable = 0;
	`Data_Control_Control_Reset(ctrl) = 1;

	#4;
	`Data_Control_Control_Reset(ctrl) = 0;

	#4;
	enable = 1;

	#32;
	enable = 0;

	#4;
	load = 1;

	#8;
	enable = 1;

	#4;
	`Data_Control_Control_Reset(ctrl) = 1;

	#4;
	`Data_Control_Control_Reset(ctrl) = 0;
	load = 0;
	enable = 0;

	$finish;
end

endmodule
module Util_Counter_counter_tb;


logic [3:0] d, q;
`Data_Control_Control_T(logic) ctrl;
logic load, enable;

Counter_counter #
	( .MAX (12)
	) DUT
	( .d (d)
	, .q (q)
	, .ctrl (ctrl)
	, .load (load)
	, .enable (enable)
	);

initial `Data_Control_Control_Clock(ctrl) = 0;
always #1 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);
initial d = 4'b0;
always #2 d = d - 1;

initial begin
	#0;
	load = 0;
	enable = 0;
	`Data_Control_Control_Reset(ctrl) = 1;

	#4;
	`Data_Control_Control_Reset(ctrl) = 0;

	#4;
	enable = 1;

	#32;
	enable = 0;

	#4;
	load = 1;

	#8;
	enable = 1;

	#4;
	`Data_Control_Control_Reset(ctrl) = 1;

	#4;
	`Data_Control_Control_Reset(ctrl) = 0;
	load = 0;
	enable = 0;

	$finish;
end

endmodule