data/full_repos/permissive/100975158/MIPS32_Full/UART/UART.v
1: b"%Error: data/full_repos/permissive/100975158/MIPS32_Full/UART/UART.v:39: Cannot find file containing module: 'UART_Clock_Generator'\n    UART_Clock_Generator UART_Clock (\n    ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100975158/MIPS32_Full/UART,data/full_repos/permissive/100975158/UART_Clock_Generator\n             data/full_repos/permissive/100975158/MIPS32_Full/UART,data/full_repos/permissive/100975158/UART_Clock_Generator.v\n             data/full_repos/permissive/100975158/MIPS32_Full/UART,data/full_repos/permissive/100975158/UART_Clock_Generator.sv\n             UART_Clock_Generator\n             UART_Clock_Generator.v\n             UART_Clock_Generator.sv\n             obj_dir/UART_Clock_Generator\n             obj_dir/UART_Clock_Generator.v\n             obj_dir/UART_Clock_Generator.sv\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/UART/UART.v:66: Cannot find file containing module: 'RX'\n    RX RX_O_Rato (\n    ^~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/UART/UART.v:75: Cannot find file containing module: 'FIFO_Structure'\n    FIFO_Structure RX_Buffer (\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/UART/UART.v:86: Cannot find file containing module: 'FIFO_Structure_Ahead'\n    FIFO_Structure_Ahead TX_Buffer (\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/UART/UART.v:97: Cannot find file containing module: 'TX'\n    TX TX_O_Rato (\n    ^~\n%Error: Exiting due to 5 error(s)\n"
module UART (
    input        clock,
    input        reset,
    input        rx,
    output       tx,

    input        write,
    input [7:0]  data_write,
    input        read,
    output [7:0] data_read,
    output       data_ready,

    output       uart_clock,
    output       uart_clock_16,

    output [7:0] debug_data
);

    wire         uart_tick;
    wire         uart_tick_16;
    wire         tx_ready;
    wire         rx_ready;

    reg          tx_start = 0;
    reg          tx_fifo_read = 0;

    wire         tx_fifo_full;
    wire         tx_fifo_empty;
    wire [7:0]   tx_fifo_data;

    wire [7:0]   rx_data;
    wire         rx_fifo_full;
    wire         rx_fifo_empty;


    UART_Clock_Generator UART_Clock (
        .clock          (clock),
        .uart_tick      (uart_tick),
        .uart_tick_16   (uart_tick_16)
    );

    assign uart_clock    = (uart_tick);
    assign uart_clock_16 = (uart_tick_16);
    assign data_ready    = ~rx_fifo_empty;

    always @ (posedge clock) begin
        if (reset) begin
            tx_start     <= 0;
            tx_fifo_read <= 0;
        end
        else begin
            if (tx_ready & uart_tick & ~tx_fifo_empty) begin
                tx_start     <= 1;
                tx_fifo_read <= 1;
            end
            else begin
                tx_start     <= 0;
                tx_fifo_read <= 0;
            end
        end
    end

    RX RX_O_Rato (
        .clock          (clock),
        .reset          (reset),
        .uart_tick_16   (uart_tick_16),
        .rx_signal      (rx),
        .ready          (rx_ready),
        .rx_data        (rx_data)
    );

    FIFO_Structure RX_Buffer (
        .clock          (clock),
        .reset          (reset),
        .read           (read),
        .write          (rx_ready),
        .in_data        (rx_data),
        .full           (rx_fifo_full),
        .empty          (rx_fifo_empty),
        .out_data       (data_read)
    );

    FIFO_Structure_Ahead TX_Buffer (
        .clock          (clock),
        .reset          (reset),
        .read           (tx_fifo_read),
        .write          (write),
        .in_data        (data_write),
        .full           (tx_fifo_full),
        .empty          (tx_fifo_empty),
        .out_data       (tx_fifo_data)
    );

    TX TX_O_Rato (
        .clock          (clock),
        .reset          (reset),
        .uart_tick      (uart_tick),
        .tx_signal      (tx),
        .tx_start       (tx_start),
        .tx_data        (tx_fifo_data),
        .ready          (tx_ready)
    );


endmodule
module UART (
    input        clock,
    input        reset,
    input        rx,
    output       tx,

    input        write,
    input [7:0]  data_write,
    input        read,
    output [7:0] data_read,
    output       data_ready,

    output       uart_clock,
    output       uart_clock_16,

    output [7:0] debug_data
);


    wire         uart_tick;
    wire         uart_tick_16;
    wire         tx_ready;
    wire         rx_ready;

    reg          tx_start = 0;
    reg          tx_fifo_read = 0;

    wire         tx_fifo_full;
    wire         tx_fifo_empty;
    wire [7:0]   tx_fifo_data;

    wire [7:0]   rx_data;
    wire         rx_fifo_full;
    wire         rx_fifo_empty;


    UART_Clock_Generator UART_Clock (
        .clock          (clock),
        .uart_tick      (uart_tick),
        .uart_tick_16   (uart_tick_16)
    );

    assign uart_clock    = (uart_tick);
    assign uart_clock_16 = (uart_tick_16);
    assign data_ready    = ~rx_fifo_empty;

    always @ (posedge clock) begin
        if (reset) begin
            tx_start     <= 0;
            tx_fifo_read <= 0;
        end
        else begin
            if (tx_ready & uart_tick & ~tx_fifo_empty) begin
                tx_start     <= 1;
                tx_fifo_read <= 1;
            end
            else begin
                tx_start     <= 0;
                tx_fifo_read <= 0;
            end
        end
    end

    RX RX_O_Rato (
        .clock          (clock),
        .reset          (reset),
        .uart_tick_16   (uart_tick_16),
        .rx_signal      (rx),
        .ready          (rx_ready),
        .rx_data        (rx_data)
    );

    FIFO_Structure RX_Buffer (
        .clock          (clock),
        .reset          (reset),
        .read           (read),
        .write          (rx_ready),
        .in_data        (rx_data),
        .full           (rx_fifo_full),
        .empty          (rx_fifo_empty),
        .out_data       (data_read)
    );

    FIFO_Structure_Ahead TX_Buffer (
        .clock          (clock),
        .reset          (reset),
        .read           (tx_fifo_read),
        .write          (write),
        .in_data        (data_write),
        .full           (tx_fifo_full),
        .empty          (tx_fifo_empty),
        .out_data       (tx_fifo_data)
    );

    TX TX_O_Rato (
        .clock          (clock),
        .reset          (reset),
        .uart_tick      (uart_tick),
        .tx_signal      (tx),
        .tx_start       (tx_start),
        .tx_data        (tx_fifo_data),
        .ready          (tx_ready)
    );


endmodule