data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/axis_ctrlport_reg.v
 line:119: before: "if"
data/verilator_xmls/ad8e8515-dadb-4457-969e-d0d85b1b8e9e.xml
module axis_ctrlport_reg #(
  parameter ADDR           = 0,
  parameter USE_ADDR_LAST  = 0,
  parameter ADDR_LAST      = ADDR+1,
  parameter DWIDTH         = 32,
  parameter USE_FIFO       = 0,
  parameter FIFm_SIZE      = 5,
  parameter DATA_AT_RESET  = 0,
  parameter VALID_AT_RESET = 0,
  parameter LAST_AT_RESET  = 0
) (
  input clk,
  input reset,






  input  wire        s_ctrlport_req_wr,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,


  output reg         s_ctrlport_resp_ack,






  output [DWIDTH-1:0] m_tdata,
  output              m_tlast,
  output              m_tvalid,
  input               m_tready
);

  reg  [DWIDTH-1:0] m_tdata_int  = DATA_AT_RESET;
  reg               m_tlast_int  = VALID_AT_RESET;
  reg               m_tvalid_int = LAST_AT_RESET;
  wire              m_tready_int;






  always @(posedge clk) begin
    if (reset) begin
      m_tdata_int         <= DATA_AT_RESET;
      m_tvalid_int        <= VALID_AT_RESET;
      m_tlast_int         <= LAST_AT_RESET;
      s_ctrlport_resp_ack <= 1'b0;
    end else begin
      if (m_tvalid_int & m_tready_int) begin
        s_ctrlport_resp_ack <= 1'b1;
        m_tvalid_int        <= 1'b0;
        m_tlast_int         <= 1'b0;
      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end

      if (s_ctrlport_req_wr) begin
        if (s_ctrlport_req_addr == ADDR) begin
          m_tdata_int  <= s_ctrlport_req_data;
          m_tvalid_int <= 1'b1;
          m_tlast_int  <= 1'b0;
        end else if (USE_ADDR_LAST && ADDR_LAST == s_ctrlport_req_addr) begin
          m_tdata_int  <= s_ctrlport_req_data;
          m_tvalid_int <= 1'b1;
          m_tlast_int  <= 1'b1;
        end
      end
    end
  end






  if (USE_FIFO) begin : gen_fifo
    axi_fifo #(
      .DWIDTH (DWIDTH+1),
      .SIZE   (FIFm_SIZE)
    ) axi_fifo (
      .clk      (clk),
      .reset    (reset),
      .clear    (1'b0),
      .i_tdata  ({m_tlast_int, m_tdata_int}),
      .i_tvalid (m_tvalid_int),
      .i_tready (m_tready_int),
      .o_tdata  ({m_tlast, m_tdata}),
      .o_tvalid (m_tvalid),
      .o_tready (m_tready),
      .space    (),
      .occupied ()
    );
  end else begin : nm_gen_fifo
    assign m_tdata      = m_tdata_int;
    assign m_tlast      = m_tlast_int;
    assign m_tvalid     = m_tvalid_int;
    assign m_tready_int = m_tready;
  end

endmodule
module axis_ctrlport_reg #(
  parameter ADDR           = 0,
  parameter USE_ADDR_LAST  = 0,
  parameter ADDR_LAST      = ADDR+1,
  parameter DWIDTH         = 32,
  parameter USE_FIFO       = 0,
  parameter FIFm_SIZE      = 5,
  parameter DATA_AT_RESET  = 0,
  parameter VALID_AT_RESET = 0,
  parameter LAST_AT_RESET  = 0
) (
  input clk,
  input reset,






  input  wire        s_ctrlport_req_wr,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,


  output reg         s_ctrlport_resp_ack,






  output [DWIDTH-1:0] m_tdata,
  output              m_tlast,
  output              m_tvalid,
  input               m_tready
);


  reg  [DWIDTH-1:0] m_tdata_int  = DATA_AT_RESET;
  reg               m_tlast_int  = VALID_AT_RESET;
  reg               m_tvalid_int = LAST_AT_RESET;
  wire              m_tready_int;






  always @(posedge clk) begin
    if (reset) begin
      m_tdata_int         <= DATA_AT_RESET;
      m_tvalid_int        <= VALID_AT_RESET;
      m_tlast_int         <= LAST_AT_RESET;
      s_ctrlport_resp_ack <= 1'b0;
    end else begin
      if (m_tvalid_int & m_tready_int) begin
        s_ctrlport_resp_ack <= 1'b1;
        m_tvalid_int        <= 1'b0;
        m_tlast_int         <= 1'b0;
      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end

      if (s_ctrlport_req_wr) begin
        if (s_ctrlport_req_addr == ADDR) begin
          m_tdata_int  <= s_ctrlport_req_data;
          m_tvalid_int <= 1'b1;
          m_tlast_int  <= 1'b0;
        end else if (USE_ADDR_LAST && ADDR_LAST == s_ctrlport_req_addr) begin
          m_tdata_int  <= s_ctrlport_req_data;
          m_tvalid_int <= 1'b1;
          m_tlast_int  <= 1'b1;
        end
      end
    end
  end






  if (USE_FIFO) begin : gen_fifo
    axi_fifo #(
      .DWIDTH (DWIDTH+1),
      .SIZE   (FIFm_SIZE)
    ) axi_fifo (
      .clk      (clk),
      .reset    (reset),
      .clear    (1'b0),
      .i_tdata  ({m_tlast_int, m_tdata_int}),
      .i_tvalid (m_tvalid_int),
      .i_tready (m_tready_int),
      .o_tdata  ({m_tlast, m_tdata}),
      .o_tvalid (m_tvalid),
      .o_tready (m_tready),
      .space    (),
      .occupied ()
    );
  end else begin : nm_gen_fifo
    assign m_tdata      = m_tdata_int;
    assign m_tlast      = m_tlast_int;
    assign m_tvalid     = m_tvalid_int;
    assign m_tready_int = m_tready;
  end

endmodule