data/full_repos/permissive/143278/ivltests/pr587.v
 line:16: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr587.v:9: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk <= ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr587.v:16: Unsupported: Ignoring delay on this delayed statement.\n     # 2600 $display("PASSED");\n     ^\n%Error: data/full_repos/permissive/143278/ivltests/pr587.v:30: Unsupported: Verilog 1995 force\n      force x = 0;\n      ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr587.v:32: Unsupported: Verilog 1995 force\n      force x = 1;\n      ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr587.v:34: Unsupported: Verilog 1995 force\n      force x = 0;\n      ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr587.v:36: Unsupported: Verilog 1995 release\n      release x;\n      ^~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module foo();
  wire x;
  reg clk;
  reg [7:0] counter;

  always #5 clk <= ~clk;

  assign x = 0;

  initial begin
    clk  = 0;
    counter = 0;
     # 2600 $display("PASSED");
            $finish;
  end

   always @(negedge clk)
      if (x !== u_bar.x) begin
	 $display("FAILED -- x != u_bar.x");
	 $finish;
      end

  always @(posedge clk) begin
    counter <= counter + 1;

    if (counter == 32)
      force x = 0;
    else if (counter == 64)
      force x = 1;
    else if (counter == 96)
      force x = 0;
    else if (counter == 128)
      release x;

    $display("[foo %d] x = %d",counter, x);
  end

  bar u_bar( .clk(clk), .x(x));

endmodule
module foo();

  wire x;
  reg clk;
  reg [7:0] counter;

  always #5 clk <= ~clk;

  assign x = 0;

  initial begin
    clk  = 0;
    counter = 0;
     # 2600 $display("PASSED");
            $finish;
  end

   always @(negedge clk)
      if (x !== u_bar.x) begin
	 $display("FAILED -- x != u_bar.x");
	 $finish;
      end

  always @(posedge clk) begin
    counter <= counter + 1;

    if (counter == 32)
      force x = 0;
    else if (counter == 64)
      force x = 1;
    else if (counter == 96)
      force x = 0;
    else if (counter == 128)
      release x;

    $display("[foo %d] x = %d",counter, x);
  end

  bar u_bar( .clk(clk), .x(x));

endmodule