data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v
'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte
1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n             const_defination.v\n             const_defination.v.v\n             const_defination.v.sv\n             obj_dir/const_defination.v\n             obj_dir/const_defination.v.v\n             obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:25: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] predPC,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`digitsBus] predPC,\n                         ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:26: Define or directive not defined: \'`icodeBus\'\n    input wire[`icodeBus] M_icode,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`digitsBus] M_valA,\n    ^~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:28: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] M_valA,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:29: Define or directive not defined: \'`icodeBus\'\n    input wire[`icodeBus] W_icode,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:30: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] W_valM,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:31: Define or directive not defined: \'`digitsBus\'\n    output reg[`digitsBus] pc\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:35: Define or directive not defined: \'`jmp\'\n        if({M_icode,4\'h0}==`jmp)\n                           ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/selectPC.v:46: Define or directive not defined: \'`ret\'\n        else if({W_icode,4\'h0}==`ret)\n                                ^~~~\n%Error: Exiting due to 11 error(s)\n'
module selectPC(
    input wire[`digitsBus] predPC,
    input wire[`icodeBus] M_icode,
    input wire M_Cnd,
    input wire[`digitsBus] M_valA,
    input wire[`icodeBus] W_icode,
    input wire[`digitsBus] W_valM,
    output reg[`digitsBus] pc
);
    always@(*)
    begin
        if({M_icode,4'h0}==`jmp)
        begin
            if(M_Cnd==0)
            begin
                pc<=predPC;
            end
			else
			begin
				pc<=M_valA;
			end
        end
        else if({W_icode,4'h0}==`ret)
        begin
            pc<=W_valM;
        end
        else
        begin
            pc<=predPC;
        end
    end
    
    
endmodule
module selectPC(
    input wire[`digitsBus] predPC,
    input wire[`icodeBus] M_icode,
    input wire M_Cnd,
    input wire[`digitsBus] M_valA,
    input wire[`icodeBus] W_icode,
    input wire[`digitsBus] W_valM,
    output reg[`digitsBus] pc
);

    always@(*)
    begin
        if({M_icode,4'h0}==`jmp)
        begin
            if(M_Cnd==0)
            begin
                pc<=predPC;
            end
			else
			begin
				pc<=M_valA;
			end
        end
        else if({W_icode,4'h0}==`ret)
        begin
            pc<=W_valM;
        end
        else
        begin
            pc<=predPC;
        end
    end
    
    
endmodule