data/full_repos/permissive/217642438/rtl/fpga_gaplus.v
1: b"%Error: data/full_repos/permissive/217642438/rtl/fpga_gaplus.v:104: Cannot find file containing module: 'GAPLUS_SHAREMEM'\nGAPLUS_SHAREMEM smem\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/217642438/rtl,data/full_repos/permissive/217642438/GAPLUS_SHAREMEM\n             data/full_repos/permissive/217642438/rtl,data/full_repos/permissive/217642438/GAPLUS_SHAREMEM.v\n             data/full_repos/permissive/217642438/rtl,data/full_repos/permissive/217642438/GAPLUS_SHAREMEM.sv\n             GAPLUS_SHAREMEM\n             GAPLUS_SHAREMEM.v\n             GAPLUS_SHAREMEM.sv\n             obj_dir/GAPLUS_SHAREMEM\n             obj_dir/GAPLUS_SHAREMEM.v\n             obj_dir/GAPLUS_SHAREMEM.sv\n%Error: data/full_repos/permissive/217642438/rtl/fpga_gaplus.v:122: Cannot find file containing module: 'GAPLUS_VIDEO'\nGAPLUS_VIDEO video\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/217642438/rtl/fpga_gaplus.v:152: Cannot find file containing module: 'GAPLUS_MAIN'\nGAPLUS_MAIN main\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/217642438/rtl/fpga_gaplus.v:168: Cannot find file containing module: 'GAPLUS_SUB'\nGAPLUS_SUB sub\n^~~~~~~~~~\n%Error: data/full_repos/permissive/217642438/rtl/fpga_gaplus.v:181: Cannot find file containing module: 'GAPLUS_SOUND'\nGAPLUS_SOUND sound\n^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module FPGA_GAPLUS
(
	input				RESET,
	input				MCLK,

	input	  [8:0]	PH,
	input	  [8:0]	PV,
	output			PCLK,
	output [11:0]	POUT,

	output  [7:0]  SOUT,


	input	  [4:0]	INP0,
	input	  [4:0]	INP1,
	input   [2:0]  INP2,
										
	input	  [7:0]	DSW0,
	input	  [7:0]	DSW1,
	input	  [7:0] 	DSW2,


	input				ROMCL,
	input  [17:0]	ROMAD,
	input	  [7:0]	ROMDT,
	input				ROMEN
);




wire				CIN1 = INP2[2];
wire				ST1P = INP2[0];
wire				ST2P = INP2[1];

wire				TRG1 = INP0[4];
wire				TRG2 = INP1[4];

wire  [3:0]		P1   = INP0[3:0];
wire  [3:0]		P2   = INP1[3:0];
wire  [3:0]		BUTS = { ST2P, ST1P, TRG2, TRG1 };
wire  [3:0]		CINS = { 1'b0, 1'b0, 1'b0, CIN1 };

wire [31:0]		INTF0 = { 16'h0, BUTS, P2, P1, CINS };
wire [31:0]		INTF1 = {{DSW0[3:0],DSW1[7:4],DSW1[3:0],DSW0[7:4]},{DSW0[3:0],DSW1[7:4],DSW1[3:0],DSW0[7:4]}};
wire  [3:0]		INTF2 = { DSW2[1:0], 2'b11 };

						



reg [4:0] CLKS;
always @( posedge MCLK ) CLKS <= CLKS+1;

wire		CLK50M   = MCLK;
wire		CLK25M   = CLKS[0];
wire		CLK12M5  = CLKS[1];
wire		CLK6M25  = CLKS[2];
wire		CLK3M125 = CLKS[3];
wire		CLK1M60  = CLKS[4];

wire		VCLK_x4  = CLK25M;
wire		VCLK_x2  = CLK12M5;
wire		VCLK_x1  = CLK6M25;



wire		CPUCLKx4 = CLK6M25;
wire		CPUCLKx2 = CLK3M125;
wire		CPUCLK   = CLK1M60;

wire		MCPU_CLK =  CPUCLKx2;
wire		SCPU_CLK = ~CPUCLKx2;


assign PCLK = VCLK_x1;





wire [15:0] mcpu_ma;
wire	[7:0]	mcpu_mr;
wire  [7:0] mcpu_do;
wire			mcpu_we;

wire [15:0] scpu_ma;
wire  [7:0] scpu_mr;
wire  [7:0] scpu_do;
wire        scpu_we;

wire [10:0] vram_a;
wire [15:0] vram_d;

wire [ 6:0] spra_a;
wire [23:0] spra_d;


GAPLUS_SHAREMEM smem
(
	CPUCLKx4,
	CLK50M,
	MCPU_CLK,
	mcpu_ma, mcpu_mr, mcpu_do, mcpu_we,
	scpu_ma, scpu_mr, scpu_do, scpu_we,
	vram_a, vram_d,
	spra_a, spra_d
);





wire mcpu_star_cs;
wire oVB;

GAPLUS_VIDEO video
(
	.CLK50M(CLK50M),
	.VCLKx4(VCLK_x4),
	.VCLKx2(VCLK_x2),
	.VCLK(VCLK_x1),
	.RESET(RESET),

	.PH(PH),.PV(PV),
	.POUT(POUT),.VB(oVB),

	.VRAM_A(vram_a), .VRAM_D(vram_d),
	.SPRA_A(spra_a), .SPRA_D(spra_d),

	.STAR_AD(mcpu_ma[1:0]),
	.STAR_DT(mcpu_do),
	.STAR_WE(mcpu_star_cs),

	.ROMCL(ROMCL),.ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN)
);





wire 			SUB_RESET;
wire			kick_explode;
wire  [7:0] snd_rd;
wire        snd_we;

GAPLUS_MAIN main
(
	MCPU_CLK, RESET, oVB,
	INTF0, INTF1, INTF2,
	mcpu_ma, mcpu_we, mcpu_do, mcpu_mr,
	snd_we, snd_rd,
	mcpu_star_cs, 
	SUB_RESET, kick_explode,

	ROMCL,ROMAD,ROMDT,ROMEN
);





GAPLUS_SUB sub
(
	SCPU_CLK, SUB_RESET, oVB,
	scpu_mr,
	scpu_ma, scpu_we, scpu_do,

	ROMCL,ROMAD,ROMDT,ROMEN
);





GAPLUS_SOUND sound
(
	SUB_RESET,
	MCPU_CLK,
	VCLK_x4,
	oVB,
	CLK50M, { 1'b0, mcpu_ma[9:0] }, mcpu_do, snd_rd, snd_we,
	kick_explode,
	SOUT,
	~SUB_RESET,
	
	ROMCL,ROMAD,ROMDT,ROMEN
);


endmodule
module FPGA_GAPLUS
(
	input				RESET,
	input				MCLK,

	input	  [8:0]	PH,
	input	  [8:0]	PV,
	output			PCLK,
	output [11:0]	POUT,

	output  [7:0]  SOUT,


	input	  [4:0]	INP0,
	input	  [4:0]	INP1,
	input   [2:0]  INP2,
										
	input	  [7:0]	DSW0,
	input	  [7:0]	DSW1,
	input	  [7:0] 	DSW2,


	input				ROMCL,
	input  [17:0]	ROMAD,
	input	  [7:0]	ROMDT,
	input				ROMEN
);





wire				CIN1 = INP2[2];
wire				ST1P = INP2[0];
wire				ST2P = INP2[1];

wire				TRG1 = INP0[4];
wire				TRG2 = INP1[4];

wire  [3:0]		P1   = INP0[3:0];
wire  [3:0]		P2   = INP1[3:0];
wire  [3:0]		BUTS = { ST2P, ST1P, TRG2, TRG1 };
wire  [3:0]		CINS = { 1'b0, 1'b0, 1'b0, CIN1 };

wire [31:0]		INTF0 = { 16'h0, BUTS, P2, P1, CINS };
wire [31:0]		INTF1 = {{DSW0[3:0],DSW1[7:4],DSW1[3:0],DSW0[7:4]},{DSW0[3:0],DSW1[7:4],DSW1[3:0],DSW0[7:4]}};
wire  [3:0]		INTF2 = { DSW2[1:0], 2'b11 };

						



reg [4:0] CLKS;
always @( posedge MCLK ) CLKS <= CLKS+1;

wire		CLK50M   = MCLK;
wire		CLK25M   = CLKS[0];
wire		CLK12M5  = CLKS[1];
wire		CLK6M25  = CLKS[2];
wire		CLK3M125 = CLKS[3];
wire		CLK1M60  = CLKS[4];

wire		VCLK_x4  = CLK25M;
wire		VCLK_x2  = CLK12M5;
wire		VCLK_x1  = CLK6M25;



wire		CPUCLKx4 = CLK6M25;
wire		CPUCLKx2 = CLK3M125;
wire		CPUCLK   = CLK1M60;

wire		MCPU_CLK =  CPUCLKx2;
wire		SCPU_CLK = ~CPUCLKx2;


assign PCLK = VCLK_x1;





wire [15:0] mcpu_ma;
wire	[7:0]	mcpu_mr;
wire  [7:0] mcpu_do;
wire			mcpu_we;

wire [15:0] scpu_ma;
wire  [7:0] scpu_mr;
wire  [7:0] scpu_do;
wire        scpu_we;

wire [10:0] vram_a;
wire [15:0] vram_d;

wire [ 6:0] spra_a;
wire [23:0] spra_d;


GAPLUS_SHAREMEM smem
(
	CPUCLKx4,
	CLK50M,
	MCPU_CLK,
	mcpu_ma, mcpu_mr, mcpu_do, mcpu_we,
	scpu_ma, scpu_mr, scpu_do, scpu_we,
	vram_a, vram_d,
	spra_a, spra_d
);





wire mcpu_star_cs;
wire oVB;

GAPLUS_VIDEO video
(
	.CLK50M(CLK50M),
	.VCLKx4(VCLK_x4),
	.VCLKx2(VCLK_x2),
	.VCLK(VCLK_x1),
	.RESET(RESET),

	.PH(PH),.PV(PV),
	.POUT(POUT),.VB(oVB),

	.VRAM_A(vram_a), .VRAM_D(vram_d),
	.SPRA_A(spra_a), .SPRA_D(spra_d),

	.STAR_AD(mcpu_ma[1:0]),
	.STAR_DT(mcpu_do),
	.STAR_WE(mcpu_star_cs),

	.ROMCL(ROMCL),.ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN)
);





wire 			SUB_RESET;
wire			kick_explode;
wire  [7:0] snd_rd;
wire        snd_we;

GAPLUS_MAIN main
(
	MCPU_CLK, RESET, oVB,
	INTF0, INTF1, INTF2,
	mcpu_ma, mcpu_we, mcpu_do, mcpu_mr,
	snd_we, snd_rd,
	mcpu_star_cs, 
	SUB_RESET, kick_explode,

	ROMCL,ROMAD,ROMDT,ROMEN
);





GAPLUS_SUB sub
(
	SCPU_CLK, SUB_RESET, oVB,
	scpu_mr,
	scpu_ma, scpu_we, scpu_do,

	ROMCL,ROMAD,ROMDT,ROMEN
);





GAPLUS_SOUND sound
(
	SUB_RESET,
	MCPU_CLK,
	VCLK_x4,
	oVB,
	CLK50M, { 1'b0, mcpu_ma[9:0] }, mcpu_do, snd_rd, snd_we,
	kick_explode,
	SOUT,
	~SUB_RESET,
	
	ROMCL,ROMAD,ROMDT,ROMEN
);


endmodule