data/full_repos/permissive/123366832/fpga/cs_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/123366832/fpga/cs_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123366832/fpga/cs_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n    always #20 A = A+1;\n           ^\n%Error: data/full_repos/permissive/123366832/fpga/cs_tb.v:38: Cannot find file containing module: \'chip_select\'\n chip_select uut (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123366832/fpga,data/full_repos/permissive/123366832/chip_select\n             data/full_repos/permissive/123366832/fpga,data/full_repos/permissive/123366832/chip_select.v\n             data/full_repos/permissive/123366832/fpga,data/full_repos/permissive/123366832/chip_select.sv\n             chip_select\n             chip_select.v\n             chip_select.sv\n             obj_dir/chip_select\n             obj_dir/chip_select.v\n             obj_dir/chip_select.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cs_tb;


	reg PHI2;
	reg RW;
	reg [15:0] A;
	reg [15:0] mask;
	reg [15:0] bitPattern;


	wire ceN;


	chip_select uut (
		.PHI2(PHI2), 
		.RW(RW), 
		.A(A), 
		.mask(mask), 
		.bitPattern(bitPattern), 
		.ceN(ceN)
	);

	initial begin

		PHI2 = 1;
		RW = 0;
		A = 0;
		mask = 0;
		bitPattern = 0;


		#100;


        mask = 16'h8000;
        bitPattern = 16'h8000;
	end
    
    always #20 A = A+1;
      
endmodule
module cs_tb;



	reg PHI2;
	reg RW;
	reg [15:0] A;
	reg [15:0] mask;
	reg [15:0] bitPattern;


	wire ceN;


	chip_select uut (
		.PHI2(PHI2), 
		.RW(RW), 
		.A(A), 
		.mask(mask), 
		.bitPattern(bitPattern), 
		.ceN(ceN)
	);

	initial begin

		PHI2 = 1;
		RW = 0;
		A = 0;
		mask = 0;
		bitPattern = 0;


		#100;


        mask = 16'h8000;
        bitPattern = 16'h8000;
	end
    
    always #20 A = A+1;
      
endmodule