data/full_repos/permissive/156417892/hdl/WriteBack/WriteBack.v
 line:9: before: ")"
1: b"%Error: data/full_repos/permissive/156417892/hdl/WriteBack/WriteBack.v:9: syntax error, unexpected ')', expecting '['\n                  );\n                  ^\n%Error: Exiting due to 1 error(s)\n"
module WriteBack(
                  clk,
                  rstn,
                  iSig_regfile_write,
                  iSig_MemtoReg,
                  iread_from_ram,
                  ialu_result,
                  odata2write2regfile,
                  );

   input clk, rstn;
   input iSig_regfile_write, iSig_MemtoReg;
   input [31:0] iread_from_ram, ialu_result;

   output [31:0] odata2write2regfile;


   DataBranch dataBranch(.MemRead(iread_from_ram),
               .Addr(ialu_result),
               .SigMemToReg(iSig_MemtoReg),
               .Write2Reg(odata2write2regfile));

endmodule
module WriteBack(
                  clk,
                  rstn,
                  iSig_regfile_write,
                  iSig_MemtoReg,
                  iread_from_ram,
                  ialu_result,
                  odata2write2regfile,
                  );


   input clk, rstn;
   input iSig_regfile_write, iSig_MemtoReg;
   input [31:0] iread_from_ram, ialu_result;

   output [31:0] odata2write2regfile;


   DataBranch dataBranch(.MemRead(iread_from_ram),
               .Addr(ialu_result),
               .SigMemToReg(iSig_MemtoReg),
               .Write2Reg(odata2write2regfile));

endmodule