data/full_repos/permissive/143278/ivltests/vhdl_image_attr.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_image_attr.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1 start_test = 1\'b1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_image_attr.v:24: Cannot find file containing module: \'image_attr_entity\'\nimage_attr_entity dut(start_test);\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/image_attr_entity\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/image_attr_entity.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/image_attr_entity.sv\n             image_attr_entity\n             image_attr_entity.v\n             image_attr_entity.sv\n             obj_dir/image_attr_entity\n             obj_dir/image_attr_entity.v\n             obj_dir/image_attr_entity.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module image_attr_test;
logic start_test;
image_attr_entity dut(start_test);

initial begin
    start_test = 1'b0;
    #1 start_test = 1'b1;
end
endmodule
module image_attr_test;

logic start_test;
image_attr_entity dut(start_test);

initial begin
    start_test = 1'b0;
    #1 start_test = 1'b1;
end
endmodule