data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v
 line:34: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:35: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                  : ... In instance spi_master_7\n  reg [7:0] M_data_d, M_data_q = 1\'h0;\n                                 ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:36: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                  : ... In instance spi_master_7\n  reg [4:0] M_sck_reg_d, M_sck_reg_q = 1\'h0;\n                                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:38: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                  : ... In instance spi_master_7\n  reg [2:0] M_ctr_d, M_ctr_q = 1\'h0;\n                               ^~~~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:55: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                  : ... In instance spi_master_7\n        M_sck_reg_d = 1\'h0;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:56: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                  : ... In instance spi_master_7\n        M_ctr_d = 1\'h0;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:67: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                                                  : ... In instance spi_master_7\n          if (M_sck_reg_q == 4\'hf) begin\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/spi_master_7.v:64: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                  : ... In instance spi_master_7\n        if (M_sck_reg_q == 1\'h0) begin\n                        ^~\n%Error: Exiting due to 7 warning(s)\n'
module spi_master_7 (
    input clk,
    input rst,
    input miso,
    output reg mosi,
    output reg sck,
    input start,
    input [7:0] data_in,
    output reg [7:0] data_out,
    output reg new_data,
    output reg busy
  );
  
  localparam CLK_DIV = 3'h5;
  localparam CPOL = 1'h0;
  localparam CPHA = 1'h0;
  
  
  localparam IDLE_state = 1'd0;
  localparam TRANSFER_state = 1'd1;
  
  reg M_state_d, M_state_q = IDLE_state;
  reg [7:0] M_data_d, M_data_q = 1'h0;
  reg [4:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
  reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
  reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
  
  always @* begin
    M_state_d = M_state_q;
    M_mosi_reg_d = M_mosi_reg_q;
    M_sck_reg_d = M_sck_reg_q;
    M_data_d = M_data_q;
    M_ctr_d = M_ctr_q;
    
    new_data = 1'h0;
    busy = M_state_q != IDLE_state;
    data_out = M_data_q;
    sck = ((1'h0 ^ M_sck_reg_q[4+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
    mosi = M_mosi_reg_q;
    
    case (M_state_q)
      IDLE_state: begin
        M_sck_reg_d = 1'h0;
        M_ctr_d = 1'h0;
        if (start) begin
          M_data_d = data_in;
          M_state_d = TRANSFER_state;
        end
      end
      TRANSFER_state: begin
        M_sck_reg_d = M_sck_reg_q + 1'h1;
        if (M_sck_reg_q == 1'h0) begin
          M_mosi_reg_d = M_data_q[7+0-:1];
        end else begin
          if (M_sck_reg_q == 4'hf) begin
            M_data_d = {M_data_q[0+6-:7], miso};
          end else begin
            if (M_sck_reg_q == 5'h1f) begin
              M_ctr_d = M_ctr_q + 1'h1;
              if (M_ctr_q == 3'h7) begin
                M_state_d = IDLE_state;
                new_data = 1'h1;
              end
            end
          end
        end
      end
    endcase
  end
  
  always @(posedge clk) begin
    M_data_q <= M_data_d;
    M_sck_reg_q <= M_sck_reg_d;
    M_mosi_reg_q <= M_mosi_reg_d;
    M_ctr_q <= M_ctr_d;
    
    if (rst == 1'b1) begin
      M_state_q <= 1'h0;
    end else begin
      M_state_q <= M_state_d;
    end
  end
  
endmodule
module spi_master_7 (
    input clk,
    input rst,
    input miso,
    output reg mosi,
    output reg sck,
    input start,
    input [7:0] data_in,
    output reg [7:0] data_out,
    output reg new_data,
    output reg busy
  );

  
  localparam CLK_DIV = 3'h5;
  localparam CPOL = 1'h0;
  localparam CPHA = 1'h0;
  
  
  localparam IDLE_state = 1'd0;
  localparam TRANSFER_state = 1'd1;
  
  reg M_state_d, M_state_q = IDLE_state;
  reg [7:0] M_data_d, M_data_q = 1'h0;
  reg [4:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
  reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
  reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
  
  always @* begin
    M_state_d = M_state_q;
    M_mosi_reg_d = M_mosi_reg_q;
    M_sck_reg_d = M_sck_reg_q;
    M_data_d = M_data_q;
    M_ctr_d = M_ctr_q;
    
    new_data = 1'h0;
    busy = M_state_q != IDLE_state;
    data_out = M_data_q;
    sck = ((1'h0 ^ M_sck_reg_q[4+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
    mosi = M_mosi_reg_q;
    
    case (M_state_q)
      IDLE_state: begin
        M_sck_reg_d = 1'h0;
        M_ctr_d = 1'h0;
        if (start) begin
          M_data_d = data_in;
          M_state_d = TRANSFER_state;
        end
      end
      TRANSFER_state: begin
        M_sck_reg_d = M_sck_reg_q + 1'h1;
        if (M_sck_reg_q == 1'h0) begin
          M_mosi_reg_d = M_data_q[7+0-:1];
        end else begin
          if (M_sck_reg_q == 4'hf) begin
            M_data_d = {M_data_q[0+6-:7], miso};
          end else begin
            if (M_sck_reg_q == 5'h1f) begin
              M_ctr_d = M_ctr_q + 1'h1;
              if (M_ctr_q == 3'h7) begin
                M_state_d = IDLE_state;
                new_data = 1'h1;
              end
            end
          end
        end
      end
    endcase
  end
  
  always @(posedge clk) begin
    M_data_q <= M_data_d;
    M_sck_reg_q <= M_sck_reg_d;
    M_mosi_reg_q <= M_mosi_reg_d;
    M_ctr_q <= M_ctr_d;
    
    if (rst == 1'b1) begin
      M_state_q <= 1'h0;
    end else begin
      M_state_q <= M_state_d;
    end
  end
  
endmodule