data/full_repos/permissive/113839829/Source/CPU/ex_mem.v
'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte
1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:5: Cannot find include file: defines.v\n `include "defines.v" \n          ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:15: Define or directive not defined: \'`RegAddrBus\'\n   input wire [`RegAddrBus] ex_wd,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   input wire [`RegAddrBus] ex_wd,\n                          ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n   input wire [`RegBus]     ex_wdata, \n   ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:17: Define or directive not defined: \'`RegBus\'\n   input wire [`RegBus]     ex_wdata, \n               ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:19: Define or directive not defined: \'`AluOpBus\'\n   input wire [`AluOpBus]   ex_aluop,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:20: Define or directive not defined: \'`RegBus\'\n   input wire [`RegBus]     ex_mem_addr,\n               ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:21: Define or directive not defined: \'`RegBus\'\n   input wire [`RegBus]     ex_reg2,\n               ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:24: Define or directive not defined: \'`RegAddrBus\'\n   output reg [`RegAddrBus] mem_wd,\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:26: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n   output reg [`RegBus]     mem_wdata,\n   ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:26: Define or directive not defined: \'`RegBus\'\n   output reg [`RegBus]     mem_wdata,\n               ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:28: Define or directive not defined: \'`AluOpBus\'\n   output reg [`AluOpBus]   mem_aluop,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:29: Define or directive not defined: \'`RegBus\'\n   output reg [`RegBus]     mem_mem_addr,\n               ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:30: Define or directive not defined: \'`RegBus\'\n   output reg [`RegBus]     mem_reg2\n               ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:36: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:38: Define or directive not defined: \'`NOPRegAddr\'\n      mem_wd <= `NOPRegAddr;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:39: Define or directive not defined: \'`WriteDisable\'\n      mem_wreg <= `WriteDisable;\n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:40: Define or directive not defined: \'`ZeroWord\'\n      mem_wdata <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:41: Define or directive not defined: \'`EXE_NOP_OP\'\n      mem_aluop <= `EXE_NOP_OP;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:42: Define or directive not defined: \'`ZeroWord\'\n      mem_mem_addr <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:43: Define or directive not defined: \'`ZeroWord\'\n      mem_reg2 <= `ZeroWord;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:48: Define or directive not defined: \'`NOPRegAddr\'\n      mem_wd <= `NOPRegAddr;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:49: Define or directive not defined: \'`WriteDisable\'\n      mem_wreg <= `WriteDisable;\n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:50: Define or directive not defined: \'`ZeroWord\'\n      mem_wdata <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:51: Define or directive not defined: \'`EXE_NOP_OP\'\n      mem_aluop <= `EXE_NOP_OP;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:52: Define or directive not defined: \'`ZeroWord\'\n      mem_mem_addr <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:53: Define or directive not defined: \'`ZeroWord\'\n      mem_reg2 <= `ZeroWord;\n                  ^~~~~~~~~\n%Error: Exiting due to 27 error(s)\n'
module ex_mem
  (
   input wire 		    clk,
   input wire 		    rst,

   input wire [5:0] 	    stall,


   input wire [`RegAddrBus] ex_wd,
   input wire 		    ex_wreg,
   input wire [`RegBus]     ex_wdata, 

   input wire [`AluOpBus]   ex_aluop,
   input wire [`RegBus]     ex_mem_addr,
   input wire [`RegBus]     ex_reg2,
   

   output reg [`RegAddrBus] mem_wd,
   output reg 		    mem_wreg,
   output reg [`RegBus]     mem_wdata,

   output reg [`AluOpBus]   mem_aluop,
   output reg [`RegBus]     mem_mem_addr,
   output reg [`RegBus]     mem_reg2
   );

   always @ (posedge clk) 
     begin

	if(rst == `RstEnable) 
	  begin
	     mem_wd <= `NOPRegAddr;
	     mem_wreg <= `WriteDisable;
	     mem_wdata <= `ZeroWord;
	     mem_aluop <= `EXE_NOP_OP;
	     mem_mem_addr <= `ZeroWord;
	     mem_reg2 <= `ZeroWord;
	  end 

	if (stall[3] == 1'b1&&stall[4] == 1'b0)
	  begin
	     mem_wd <= `NOPRegAddr;
	     mem_wreg <= `WriteDisable;
	     mem_wdata <= `ZeroWord;
	     mem_aluop <= `EXE_NOP_OP;
	     mem_mem_addr <= `ZeroWord;
	     mem_reg2 <= `ZeroWord;
	  end
	
	else if (stall[3] == 1'b0)
	  begin
	     mem_wd <= ex_wd;
	     mem_wreg <= ex_wreg;
	     mem_wdata <= ex_wdata;	
	     mem_aluop <= ex_aluop;
	     mem_mem_addr <= ex_mem_addr;
	     mem_reg2 <= ex_reg2;
	  end

     end

endmodule
module ex_mem
  (
   input wire 		    clk,
   input wire 		    rst,

   input wire [5:0] 	    stall,


   input wire [`RegAddrBus] ex_wd,
   input wire 		    ex_wreg,
   input wire [`RegBus]     ex_wdata, 

   input wire [`AluOpBus]   ex_aluop,
   input wire [`RegBus]     ex_mem_addr,
   input wire [`RegBus]     ex_reg2,
   

   output reg [`RegAddrBus] mem_wd,
   output reg 		    mem_wreg,
   output reg [`RegBus]     mem_wdata,

   output reg [`AluOpBus]   mem_aluop,
   output reg [`RegBus]     mem_mem_addr,
   output reg [`RegBus]     mem_reg2
   );


   always @ (posedge clk) 
     begin

	if(rst == `RstEnable) 
	  begin
	     mem_wd <= `NOPRegAddr;
	     mem_wreg <= `WriteDisable;
	     mem_wdata <= `ZeroWord;
	     mem_aluop <= `EXE_NOP_OP;
	     mem_mem_addr <= `ZeroWord;
	     mem_reg2 <= `ZeroWord;
	  end 

	if (stall[3] == 1'b1&&stall[4] == 1'b0)
	  begin
	     mem_wd <= `NOPRegAddr;
	     mem_wreg <= `WriteDisable;
	     mem_wdata <= `ZeroWord;
	     mem_aluop <= `EXE_NOP_OP;
	     mem_mem_addr <= `ZeroWord;
	     mem_reg2 <= `ZeroWord;
	  end
	
	else if (stall[3] == 1'b0)
	  begin
	     mem_wd <= ex_wd;
	     mem_wreg <= ex_wreg;
	     mem_wdata <= ex_wdata;	
	     mem_aluop <= ex_aluop;
	     mem_mem_addr <= ex_mem_addr;
	     mem_reg2 <= ex_reg2;
	  end

     end

endmodule