data/full_repos/permissive/21408550/rtl/testbed.v
1: b'%Error: data/full_repos/permissive/21408550/rtl/testbed.v:4: Cannot find include file: system_include.v\n`include "system_include.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21408550/rtl,data/full_repos/permissive/21408550/system_include.v\n             data/full_repos/permissive/21408550/rtl,data/full_repos/permissive/21408550/system_include.v.v\n             data/full_repos/permissive/21408550/rtl,data/full_repos/permissive/21408550/system_include.v.sv\n             system_include.v\n             system_include.v.v\n             system_include.v.sv\n             obj_dir/system_include.v\n             obj_dir/system_include.v.v\n             obj_dir/system_include.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/21408550/rtl/testbed.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #0 areset = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21408550/rtl/testbed.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #1 areset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21408550/rtl/testbed.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #2 areset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21408550/rtl/testbed.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = !clk;\n  ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module testbed ();

	reg clk = 0;
	reg areset = 0;
	wire [7:0] LED;
	
	DE0_Comm uut(
		.CLOCK_50(clk),
`ifdef UNDER_TEST
		.areset( areset ),
`endif
		.LED( LED )
	);

	initial begin
		#0 areset = 0;
		#1 areset = 1;
		#2 areset = 0;
	end
	
	always begin
		#10 clk = !clk;
	end

endmodule
module testbed ();


	reg clk = 0;
	reg areset = 0;
	wire [7:0] LED;
	
	DE0_Comm uut(
		.CLOCK_50(clk),
`ifdef UNDER_TEST
		.areset( areset ),
`endif
		.LED( LED )
	);

	initial begin
		#0 areset = 0;
		#1 areset = 1;
		#2 areset = 0;
	end
	
	always begin
		#10 clk = !clk;
	end

endmodule