data/full_repos/permissive/141745123/Lab_6.srcs/sources_1/new/ALUct.v
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data/verilator_xmls/3e907e87-2804-4a1a-8613-fdf27db75489.xml
module ALUct(
    input rst,
    input[5:0] funct,
    input[7:0] alu_ct_op,
    output reg[3:0] alu_ct
    );
    always@(*)
        if(!rst)
            alu_ct <= 0;
        else begin
            case(alu_ct_op)
                8'b00000000: alu_ct = 4'b0010;
                8'b00000001: alu_ct = 4'b1000;
                8'b00000010: alu_ct = 4'b0110;
                8'b00000100: alu_ct = 4'b1001;
                8'b00001000: begin case(funct)
                    6'b100001: alu_ct = 4'b0010;
                    6'b000100: alu_ct = 4'b0111;
                    6'b100011: alu_ct = 4'b0110;
                    6'b011010: alu_ct = 4'b1011;
                    6'b100100: alu_ct = 4'b1100;
                    6'b100101: alu_ct = 4'b1001;
                    6'b100110: alu_ct = 4'b1101;
                    6'b100111: alu_ct = 4'b1110;
                    6'b101010: alu_ct = 4'b1111;
                    default:begin
                    end
                endcase end
                8'b00010000: begin case (funct)
                    6'b000010: alu_ct = 4'b1010;
                    default: begin
                    end
                endcase end
                8'b00100000: alu_ct = 4'b1100;
                8'b01000000: alu_ct = 4'b1101;
                8'b10000000: alu_ct = 4'b1111;
                default: begin
                end
            endcase
        end
endmodule
module ALUct(
    input rst,
    input[5:0] funct,
    input[7:0] alu_ct_op,
    output reg[3:0] alu_ct
    );

    always@(*)
        if(!rst)
            alu_ct <= 0;
        else begin
            case(alu_ct_op)
                8'b00000000: alu_ct = 4'b0010;
                8'b00000001: alu_ct = 4'b1000;
                8'b00000010: alu_ct = 4'b0110;
                8'b00000100: alu_ct = 4'b1001;
                8'b00001000: begin case(funct)
                    6'b100001: alu_ct = 4'b0010;
                    6'b000100: alu_ct = 4'b0111;
                    6'b100011: alu_ct = 4'b0110;
                    6'b011010: alu_ct = 4'b1011;
                    6'b100100: alu_ct = 4'b1100;
                    6'b100101: alu_ct = 4'b1001;
                    6'b100110: alu_ct = 4'b1101;
                    6'b100111: alu_ct = 4'b1110;
                    6'b101010: alu_ct = 4'b1111;
                    default:begin
                    end
                endcase end
                8'b00010000: begin case (funct)
                    6'b000010: alu_ct = 4'b1010;
                    default: begin
                    end
                endcase end
                8'b00100000: alu_ct = 4'b1100;
                8'b01000000: alu_ct = 4'b1101;
                8'b10000000: alu_ct = 4'b1111;
                default: begin
                end
            endcase
        end
endmodule