data/full_repos/permissive/101237473/lab8/Source Code/clk_500_Hz.v
1: b'%Error: Cannot find file containing module: Code,data/full_repos/permissive/101237473\n        ... Looked in:\n             data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473\n             data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.v\n             data/full_repos/permissive/101237473/lab8/Source/Code,data/full_repos/permissive/101237473.sv\n             Code,data/full_repos/permissive/101237473\n             Code,data/full_repos/permissive/101237473.v\n             Code,data/full_repos/permissive/101237473.sv\n             obj_dir/Code,data/full_repos/permissive/101237473\n             obj_dir/Code,data/full_repos/permissive/101237473.v\n             obj_dir/Code,data/full_repos/permissive/101237473.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/101237473/lab8/Source\n%Error: Cannot find file containing module: Code/clk_500_Hz.v\n%Error: Exiting due to 3 error(s)\n'
module clk_500_Hz( clk_in, reset, clk_out );
 
	input	 	clk_in, reset; 
	output 	clk_out; 
	reg 		clk_out; 
	integer 	i; 








		always@ (posedge clk_in or posedge reset) begin
		if (reset == 1'b1) begin 
			i = 0; 
			clk_out = 0; 
		end 


		else begin 
			i = i+1; 
			if (i >= ((100000000/500)/2)) begin 
				clk_out = ~clk_out; 
				i=0; 
			end
		end
	end
	
endmodule
module clk_500_Hz( clk_in, reset, clk_out );

 
	input	 	clk_in, reset; 
	output 	clk_out; 
	reg 		clk_out; 
	integer 	i; 








		always@ (posedge clk_in or posedge reset) begin
		if (reset == 1'b1) begin 
			i = 0; 
			clk_out = 0; 
		end 


		else begin 
			i = i+1; 
			if (i >= ((100000000/500)/2)) begin 
				clk_out = ~clk_out; 
				i=0; 
			end
		end
	end
	
endmodule