data/full_repos/permissive/104269513/ALU_final_smaller.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:416: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:422: Unsupported: Ignoring delay on this delayed statement.\n#99\n^\n%Error: data/full_repos/permissive/104269513/ALU_final_smaller.v:424: Too many digits for 32 bit number: \'hFFFF_FFFF_FFFF_FFFF\nA=\'hFFFF_FFFF_FFFF_FFFF;\n  ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:428: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:431: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:434: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:437: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:440: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:443: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:446: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module add_sub_64bit(input [63:0] A,
				input [63:0] B,
				input Cin,
				input add_sub,
				output Cout,
				output [63:0] Sum);
				
wire [62:0] carry_prop;
wire carry_out;
wire carry;
assign carry = add_sub ? 1 : Cin;

one_bit_add_Sub A0( .A(A[0]), .B(B[0]), .Cin(carry), .b_invert(add_sub), .Cout(carry_prop[0]), .Sum(Sum[0]));
genvar i;
generate
	for (i=1; i<=62; i=i+1)
	begin: adder
		one_bit_add_Sub A1( .A(A[i]), .B(B[i]), .Cin(carry_prop[i-1]), .b_invert(add_sub), .Cout(carry_prop[i]), .Sum(Sum[i]));
	end
endgenerate
one_bit_add_Sub A2( .A(A[63]), .B(B[63]), .Cin(carry_prop[62]), .b_invert(add_sub), .Cout(carry_out), .Sum(Sum[63]));

assign Cout = add_sub ? ~carry_out : carry_out;

endmodule
module add_sub_64bit(input [63:0] A,
				input [63:0] B,
				input Cin,
				input add_sub,
				output Cout,
				output [63:0] Sum);

				
wire [62:0] carry_prop;
wire carry_out;
wire carry;
assign carry = add_sub ? 1 : Cin;

one_bit_add_Sub A0( .A(A[0]), .B(B[0]), .Cin(carry), .b_invert(add_sub), .Cout(carry_prop[0]), .Sum(Sum[0]));
genvar i;
generate
	for (i=1; i<=62; i=i+1)
	begin: adder
		one_bit_add_Sub A1( .A(A[i]), .B(B[i]), .Cin(carry_prop[i-1]), .b_invert(add_sub), .Cout(carry_prop[i]), .Sum(Sum[i]));
	end
endgenerate
one_bit_add_Sub A2( .A(A[63]), .B(B[63]), .Cin(carry_prop[62]), .b_invert(add_sub), .Cout(carry_out), .Sum(Sum[63]));

assign Cout = add_sub ? ~carry_out : carry_out;

endmodule