data/full_repos/permissive/201488448/2_circuits/2_sequential/14_jk.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/14_jk.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q'\n                                                                                          : ... In instance top_module\n            2'b00: Q <= Q;\n                   ^\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/14_jk.v:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q'\n                                                                                           : ... In instance top_module\n            2'b01: Q <= 1'b0;\n                   ^\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/14_jk.v:11: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q'\n                                                                                           : ... In instance top_module\n            2'b10: Q <= 1'b1;\n                   ^\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/14_jk.v:12: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q'\n                                                                                           : ... In instance top_module\n            2'b11: Q <= ~Q;\n                   ^\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input j,
    input k,
    output Q); 

    always@(posedge clk) begin
        case({j,k})
            2'b00:	Q <= Q;
            2'b01:	Q <= 1'b0;
            2'b10:	Q <= 1'b1;
            2'b11:	Q <= ~Q;
        endcase
    end
    
endmodule
module top_module (
    input clk,
    input j,
    input k,
    output Q);
 

    always@(posedge clk) begin
        case({j,k})
            2'b00:	Q <= Q;
            2'b01:	Q <= 1'b0;
            2'b10:	Q <= 1'b1;
            2'b11:	Q <= ~Q;
        endcase
    end
    
endmodule