data/full_repos/permissive/20951436/Code/fpga code/advanced code/Advanced code.v
1: b'%Error: Cannot find file containing module: code/advanced\n        ... Looked in:\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.v\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.sv\n             code/advanced\n             code/advanced.v\n             code/advanced.sv\n             obj_dir/code/advanced\n             obj_dir/code/advanced.v\n             obj_dir/code/advanced.sv\n%Error: Cannot find file containing module: code,data/full_repos/permissive/20951436\n%Error: Cannot find file containing module: data/full_repos/permissive/20951436/Code/fpga\n%Error: Cannot find file containing module: code/Advanced\n%Error: Cannot find file containing module: code.v\n%Error: Exiting due to 5 error(s)\n'
module division(input clk, input sign, input [63:0] dividend, input [31:0] divisor, input en, output [63:0] quotient, output [31:0] remainder, output comp_sig);

	reg [63:0] quotient_temp;
	reg [95:0] divisor_copy; wire [95:0] diff;
	reg [95:0] dividend_copy; 
	wire negative_output;
	assign negative_output = ( sign && ((divisor[31] && !dividend[63]) || (!divisor[31] && dividend[63])) );
   
	assign remainder = (!negative_output) ? dividend_copy[31:0] : ~dividend_copy[31:0] + 1'b1;

	reg [6:0] bit_consumed;
	assign comp_sig = &(~bit_consumed);

	initial bit_consumed <= 0;

	assign quotient = (!negative_output) ? quotient_temp : ~quotient_temp + 1'b1;
	assign diff = dividend_copy - divisor_copy;
	
	reg en_hist;
	always @(negedge clk) begin
		en_hist<=en;
		if (en && (~en_hist)) begin

			bit_consumed <= 7'd64;
			quotient_temp <= 0;


			dividend_copy <= (!sign || !dividend[63]) ? {32'd0,dividend} : {32'd0,~dividend + 1'b1};
			divisor_copy <= (!sign || !divisor[31]) ? {1'b0,divisor,63'd0} : {1'b0,~divisor + 1'b1,63'd0};
		end else begin
			if (bit_consumed > 0) begin

				quotient_temp <= quotient_temp << 1;

				if(!diff[95]) begin
					dividend_copy <= diff;
					quotient_temp[0] <= 1'd1;
				end

				divisor_copy <= divisor_copy >> 1;
				bit_consumed <= bit_consumed - 1'b1;

			end
		end
	end

endmodule
module division(input clk, input sign, input [63:0] dividend, input [31:0] divisor, input en, output [63:0] quotient, output [31:0] remainder, output comp_sig);


	reg [63:0] quotient_temp;
	reg [95:0] divisor_copy; wire [95:0] diff;
	reg [95:0] dividend_copy; 
	wire negative_output;
	assign negative_output = ( sign && ((divisor[31] && !dividend[63]) || (!divisor[31] && dividend[63])) );
   
	assign remainder = (!negative_output) ? dividend_copy[31:0] : ~dividend_copy[31:0] + 1'b1;

	reg [6:0] bit_consumed;
	assign comp_sig = &(~bit_consumed);

	initial bit_consumed <= 0;

	assign quotient = (!negative_output) ? quotient_temp : ~quotient_temp + 1'b1;
	assign diff = dividend_copy - divisor_copy;
	
	reg en_hist;
	always @(negedge clk) begin
		en_hist<=en;
		if (en && (~en_hist)) begin

			bit_consumed <= 7'd64;
			quotient_temp <= 0;


			dividend_copy <= (!sign || !dividend[63]) ? {32'd0,dividend} : {32'd0,~dividend + 1'b1};
			divisor_copy <= (!sign || !divisor[31]) ? {1'b0,divisor,63'd0} : {1'b0,~divisor + 1'b1,63'd0};
		end else begin
			if (bit_consumed > 0) begin

				quotient_temp <= quotient_temp << 1;

				if(!diff[95]) begin
					dividend_copy <= diff;
					quotient_temp[0] <= 1'd1;
				end

				divisor_copy <= divisor_copy >> 1;
				bit_consumed <= bit_consumed - 1'b1;

			end
		end
	end

endmodule