data/full_repos/permissive/128659832/verilog/ALU_tb.v
1: b'%Error: data/full_repos/permissive/128659832/verilog/ALU_tb.v:28: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("ALU_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/128659832/verilog/ALU_tb.v:29: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, ALU_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ALU_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ALU_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n            #1 aluCtl[1:0] = count ;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ALU_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #1 inR = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ALU_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #1 aluCtl[2] = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ALU_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #1 inR = -3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ALU_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #1 aluCtl[2] = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ALU_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_tb();






    reg         [2:0] aluCtl = 0;
    reg  signed [7:0] inR = 0;
    reg  signed [7:0] inM = 0;
    wire signed [7:0] aluOut;
    wire              flag;

    ALU alu0 (
.aluCtl( aluCtl ),
.inR( inR ),
.inM( inM ),
.aluOut( aluOut ),
.flag( flag )
    );

    reg [2:0] count;


	initial begin


		$dumpfile("ALU_tb.vcd");
		$dumpvars(0, ALU_tb);

        #1;
        inR = -3;
        inM = 5;
        for ( count = 2'b0; count<4; count=count+1 ) begin
            #1 aluCtl[1:0] = count ;
        end

        #1 inR = 0;
           aluCtl[2] = 0;
        #1 aluCtl[2] = 1;

        #1 inR = -3;
           aluCtl[2] = 0;
        #1 aluCtl[2] = 1;
        #1;

	end

endmodule
module ALU_tb();







    reg         [2:0] aluCtl = 0;
    reg  signed [7:0] inR = 0;
    reg  signed [7:0] inM = 0;
    wire signed [7:0] aluOut;
    wire              flag;

    ALU alu0 (
.aluCtl( aluCtl ),
.inR( inR ),
.inM( inM ),
.aluOut( aluOut ),
.flag( flag )
    );

    reg [2:0] count;


	initial begin


		$dumpfile("ALU_tb.vcd");
		$dumpvars(0, ALU_tb);

        #1;
        inR = -3;
        inM = 5;
        for ( count = 2'b0; count<4; count=count+1 ) begin
            #1 aluCtl[1:0] = count ;
        end

        #1 inR = 0;
           aluCtl[2] = 0;
        #1 aluCtl[2] = 1;

        #1 inR = -3;
           aluCtl[2] = 0;
        #1 aluCtl[2] = 1;
        #1;

	end

endmodule