data/full_repos/permissive/186676986/clockdiv.v
data/verilator_xmls/77393373-ba7d-48bc-a4ff-7a7232ce3caa.xml
module clockdiv(
input clk,
    input reset,
    output reg slowclk
    );
	 
	 reg [25:0]count;
	always@(posedge clk)
	begin
	      if(reset)
			count<=26'b0;
			else
			count<=count+1;
			slowclk<=count[25];
	end

endmodule
module clockdiv(
input clk,
    input reset,
    output reg slowclk
    );

	 
	 reg [25:0]count;
	always@(posedge clk)
	begin
	      if(reset)
			count<=26'b0;
			else
			count<=count+1;
			slowclk<=count[25];
	end

endmodule