data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v:41: Little bit endian vector: MSB < LSB of bit range: 0:7\ninout [0:7] gfpga_pad_GPIO_PAD;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v:100: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb,data/full_repos/permissive/137416811/logical_tile_io_mode_io_\n             data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb,data/full_repos/permissive/137416811/logical_tile_io_mode_io_.v\n             data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb,data/full_repos/permissive/137416811/logical_tile_io_mode_io_.sv\n             logical_tile_io_mode_io_\n             logical_tile_io_mode_io_.v\n             logical_tile_io_mode_io_.sv\n             obj_dir/logical_tile_io_mode_io_\n             obj_dir/logical_tile_io_mode_io_.v\n             obj_dir/logical_tile_io_mode_io_.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v:109: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v:118: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v:127: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v:136: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v:145: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v:154: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v:163: Cannot find file containing module: \'logical_tile_io_mode_io_\'\n logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module grid_io_bottom(pReset,
                      prog_clk,
                      gfpga_pad_GPIO_PAD,
                      top_width_0_height_0_subtile_0__pin_outpad_0_,
                      top_width_0_height_0_subtile_1__pin_outpad_0_,
                      top_width_0_height_0_subtile_2__pin_outpad_0_,
                      top_width_0_height_0_subtile_3__pin_outpad_0_,
                      top_width_0_height_0_subtile_4__pin_outpad_0_,
                      top_width_0_height_0_subtile_5__pin_outpad_0_,
                      top_width_0_height_0_subtile_6__pin_outpad_0_,
                      top_width_0_height_0_subtile_7__pin_outpad_0_,
                      ccff_head,
                      top_width_0_height_0_subtile_0__pin_inpad_0_,
                      top_width_0_height_0_subtile_1__pin_inpad_0_,
                      top_width_0_height_0_subtile_2__pin_inpad_0_,
                      top_width_0_height_0_subtile_3__pin_inpad_0_,
                      top_width_0_height_0_subtile_4__pin_inpad_0_,
                      top_width_0_height_0_subtile_5__pin_inpad_0_,
                      top_width_0_height_0_subtile_6__pin_inpad_0_,
                      top_width_0_height_0_subtile_7__pin_inpad_0_,
                      ccff_tail);

input [0:0] pReset;

input [0:0] prog_clk;

inout [0:7] gfpga_pad_GPIO_PAD;

input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_1__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_2__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_3__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_4__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_5__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_6__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_7__pin_outpad_0_;

input [0:0] ccff_head;

output [0:0] top_width_0_height_0_subtile_0__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_1__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_2__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_3__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_4__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_5__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_6__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_7__pin_inpad_0_;

output [0:0] ccff_tail;









wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;






	logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
		.io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
		.ccff_head(ccff_head),
		.io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
		.io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
		.io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
		.io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
		.io_outpad(top_width_0_height_0_subtile_4__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_4__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
		.io_outpad(top_width_0_height_0_subtile_5__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_5__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
		.io_outpad(top_width_0_height_0_subtile_6__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_6__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
		.io_outpad(top_width_0_height_0_subtile_7__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_7__pin_inpad_0_),
		.ccff_tail(ccff_tail));

endmodule
module grid_io_bottom(pReset,
                      prog_clk,
                      gfpga_pad_GPIO_PAD,
                      top_width_0_height_0_subtile_0__pin_outpad_0_,
                      top_width_0_height_0_subtile_1__pin_outpad_0_,
                      top_width_0_height_0_subtile_2__pin_outpad_0_,
                      top_width_0_height_0_subtile_3__pin_outpad_0_,
                      top_width_0_height_0_subtile_4__pin_outpad_0_,
                      top_width_0_height_0_subtile_5__pin_outpad_0_,
                      top_width_0_height_0_subtile_6__pin_outpad_0_,
                      top_width_0_height_0_subtile_7__pin_outpad_0_,
                      ccff_head,
                      top_width_0_height_0_subtile_0__pin_inpad_0_,
                      top_width_0_height_0_subtile_1__pin_inpad_0_,
                      top_width_0_height_0_subtile_2__pin_inpad_0_,
                      top_width_0_height_0_subtile_3__pin_inpad_0_,
                      top_width_0_height_0_subtile_4__pin_inpad_0_,
                      top_width_0_height_0_subtile_5__pin_inpad_0_,
                      top_width_0_height_0_subtile_6__pin_inpad_0_,
                      top_width_0_height_0_subtile_7__pin_inpad_0_,
                      ccff_tail);


input [0:0] pReset;

input [0:0] prog_clk;

inout [0:7] gfpga_pad_GPIO_PAD;

input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_1__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_2__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_3__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_4__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_5__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_6__pin_outpad_0_;

input [0:0] top_width_0_height_0_subtile_7__pin_outpad_0_;

input [0:0] ccff_head;

output [0:0] top_width_0_height_0_subtile_0__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_1__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_2__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_3__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_4__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_5__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_6__pin_inpad_0_;

output [0:0] top_width_0_height_0_subtile_7__pin_inpad_0_;

output [0:0] ccff_tail;









wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;






	logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
		.io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
		.ccff_head(ccff_head),
		.io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
		.io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
		.io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
		.io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
		.io_outpad(top_width_0_height_0_subtile_4__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_4__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
		.io_outpad(top_width_0_height_0_subtile_5__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_5__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
		.io_outpad(top_width_0_height_0_subtile_6__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_6__pin_inpad_0_),
		.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));

	logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
		.pReset(pReset),
		.prog_clk(prog_clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
		.io_outpad(top_width_0_height_0_subtile_7__pin_outpad_0_),
		.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
		.io_inpad(top_width_0_height_0_subtile_7__pin_inpad_0_),
		.ccff_tail(ccff_tail));

endmodule