data/full_repos/permissive/169496369/output_ans.v
data/verilator_xmls/38ea9fdc-5b40-479c-ba3c-34e1230f189a.xml
module output_ans(clk, reset, out, sign, m, e, signout, eout, mout);
    input clk, reset, out, sign;
    input [22:0]m;
    input [7:0]e;
    
    output logic signout;
    output logic [22:0] mout;
    output logic [7:0] eout;

    
    always_ff@(posedge clk)
    begin
        if(reset)
        begin
            signout <= 0;
            mout <= 23'd0;
            eout <= 8'd0;
        end
        else if(out)
        begin
            signout <= sign;
            mout <= m;
            eout <= e;
        end
        else
        begin
            signout <= signout;
            mout <= mout;
            eout <= eout;
        end
    end
endmodule
module output_ans(clk, reset, out, sign, m, e, signout, eout, mout);

    input clk, reset, out, sign;
    input [22:0]m;
    input [7:0]e;
    
    output logic signout;
    output logic [22:0] mout;
    output logic [7:0] eout;

    
    always_ff@(posedge clk)
    begin
        if(reset)
        begin
            signout <= 0;
            mout <= 23'd0;
            eout <= 8'd0;
        end
        else if(out)
        begin
            signout <= sign;
            mout <= m;
            eout <= e;
        end
        else
        begin
            signout <= signout;
            mout <= mout;
            eout <= eout;
        end
    end
endmodule