data/full_repos/permissive/206261917/src/interleaver_stage_1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:40: Operator GT expects 15 bits on the LHS, but LHS\'s VARREF \'b_2_temp\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\nwire[14:0]    b_2 = (b_2_temp > K_mul_4) ? (b_2_temp - K_mul_4) : \n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:41: Operator GT expects 14 bits on the LHS, but LHS\'s VARREF \'b_2_temp\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\n      ((b_2_temp > K_mul_2) ? (b_2_temp - K_mul_2) : ((b_2_temp > K_i) ? b_2_temp - K_i : b_2_temp )); \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:40: Operator SUB expects 15 bits on the LHS, but LHS\'s VARREF \'b_2_temp\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\nwire[14:0]    b_2 = (b_2_temp > K_mul_4) ? (b_2_temp - K_mul_4) : \n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:41: Operator SUB expects 15 bits on the LHS, but LHS\'s VARREF \'b_2_temp\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\n      ((b_2_temp > K_mul_2) ? (b_2_temp - K_mul_2) : ((b_2_temp > K_i) ? b_2_temp - K_i : b_2_temp )); \n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:41: Operator SUB expects 15 bits on the LHS, but LHS\'s VARREF \'b_2_temp\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\n      ((b_2_temp > K_mul_2) ? (b_2_temp - K_mul_2) : ((b_2_temp > K_i) ? b_2_temp - K_i : b_2_temp )); \n                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:41: Operator SUB expects 15 bits on the RHS, but RHS\'s VARREF \'K_i\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\n      ((b_2_temp > K_mul_2) ? (b_2_temp - K_mul_2) : ((b_2_temp > K_i) ? b_2_temp - K_i : b_2_temp )); \n                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:41: Operator COND expects 15 bits on the Conditional False, but Conditional False\'s VARREF \'b_2_temp\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\n      ((b_2_temp > K_mul_2) ? (b_2_temp - K_mul_2) : ((b_2_temp > K_i) ? b_2_temp - K_i : b_2_temp )); \n                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:43: Operator ADD expects 11 bits on the LHS, but LHS\'s VARREF \'f1\' generates 9 bits.\n                                                                                 : ... In instance interleaver_stage_1\nwire[10:0]    Theta_1_0 = f1 + f2;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:44: Operator ADD expects 13 bits on the LHS, but LHS\'s REPLICATE generates 10 bits.\n                                                                                 : ... In instance interleaver_stage_1\nwire[12:0]    Theta_2_0_temp = {f1,1\'b0} + {f2,2\'b0};\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:45: Operator ADD expects 14 bits on the LHS, but LHS\'s REPLICATE generates 10 bits.\n                                                                                 : ... In instance interleaver_stage_1\nwire[13:0]    Theta_2_1_temp = {f1,1\'b0} + {f2,3\'b0};\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:46: Operator GT expects 14 bits on the LHS, but LHS\'s VARREF \'Theta_2_0_temp\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\nwire[13:0]    Theta_2_0 = (Theta_2_0_temp > K_mul_2) ? (Theta_2_0_temp - K_mul_2) : \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:47: Operator COND expects 14 bits on the Conditional False, but Conditional False\'s VARREF \'Theta_2_0_temp\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\n        ((Theta_2_0_temp > K_i) ? Theta_2_0_temp - K_i : Theta_2_0_temp );\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:49: Operator GT expects 15 bits on the LHS, but LHS\'s VARREF \'Theta_2_1_temp\' generates 14 bits.\n                                                                                 : ... In instance interleaver_stage_1\nwire[14:0]    Theta_2_1 = (Theta_2_1_temp > K_mul_4) ? (Theta_2_1_temp - K_mul_4) : \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:50: Operator GT expects 14 bits on the RHS, but RHS\'s VARREF \'K_i\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\n        ((Theta_2_1_temp > K_mul_2) ? (Theta_2_1_temp - K_mul_2) : ((Theta_2_1_temp > K_i) ? Theta_2_1_temp - K_i : Theta_2_1_temp ));\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:50: Operator SUB expects 15 bits on the RHS, but RHS\'s VARREF \'K_i\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\n        ((Theta_2_1_temp > K_mul_2) ? (Theta_2_1_temp - K_mul_2) : ((Theta_2_1_temp > K_i) ? Theta_2_1_temp - K_i : Theta_2_1_temp ));\n                                                                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:50: Operator COND expects 15 bits on the Conditional False, but Conditional False\'s VARREF \'Theta_2_1_temp\' generates 14 bits.\n                                                                                 : ... In instance interleaver_stage_1\n        ((Theta_2_1_temp > K_mul_2) ? (Theta_2_1_temp - K_mul_2) : ((Theta_2_1_temp > K_i) ? Theta_2_1_temp - K_i : Theta_2_1_temp ));\n                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:54: Operator LT expects 15 bits on the RHS, but RHS\'s VARREF \'K_i\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\n             (((Theta_0_previous + b_2) < K_i) ? Theta_0_previous + b_2 : Theta_0_previous + b_2 - K_i );\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:53: Operator COND expects 15 bits on the Conditional True, but Conditional True\'s VARREF \'Theta_2_0\' generates 14 bits.\n                                                                                 : ... In instance interleaver_stage_1\n        (counter_r == 1) ? Theta_2_0 :\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:54: Operator SUB expects 15 bits on the RHS, but RHS\'s VARREF \'K_i\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\n             (((Theta_0_previous + b_2) < K_i) ? Theta_0_previous + b_2 : Theta_0_previous + b_2 - K_i );\n                                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:58: Operator LT expects 15 bits on the RHS, but RHS\'s VARREF \'K_i\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\n             (((Theta_1_previous + b_2) < K_i) ? Theta_1_previous + b_2 : Theta_1_previous + b_2 - K_i );\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:58: Operator SUB expects 15 bits on the RHS, but RHS\'s VARREF \'K_i\' generates 13 bits.\n                                                                                 : ... In instance interleaver_stage_1\n             (((Theta_1_previous + b_2) < K_i) ? Theta_1_previous + b_2 : Theta_1_previous + b_2 - K_i );\n                                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:60: Operator SUB expects 13 bits on the RHS, but RHS\'s VARREF \'K_div_4\' generates 11 bits.\n                                                                                 : ... In instance interleaver_stage_1\nwire[12:0]   Pi2n_plus_K4_init = (flag == 1) ? {K_div_4,2\'b0} - K_div_4 : {2\'b0,K_div_4};\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:61: Operator SUB expects 13 bits on the RHS, but RHS\'s VARREF \'K_div_4\' generates 11 bits.\n                                                                                 : ... In instance interleaver_stage_1\nwire[12:0]   Pi2n_plus_3K4_init = (flag == 1) ? {2\'b0,K_div_4}  : {K_div_4,2\'b0} - K_div_4;\n                                                                                 ^\n%Error: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:68: Cannot find file containing module: \'generaldff\'\ngeneraldff #(.DW(10)) counter_dff ( .dnxt(counter_next), .qout(counter_r), .clk(clk),.rst_n(dff_clr));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206261917/src,data/full_repos/permissive/206261917/generaldff\n             data/full_repos/permissive/206261917/src,data/full_repos/permissive/206261917/generaldff.v\n             data/full_repos/permissive/206261917/src,data/full_repos/permissive/206261917/generaldff.sv\n             generaldff\n             generaldff.v\n             generaldff.sv\n             obj_dir/generaldff\n             obj_dir/generaldff.v\n             obj_dir/generaldff.sv\n%Error: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:69: Cannot find file containing module: \'generaldff\'\ngeneraldff #(.DW(15)) Theta_reg_0_dff (Theta_temp_0, Theta_0_to_stage_2, clk,dff_clr);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:70: Cannot find file containing module: \'generaldff\'\ngeneraldff #(.DW(15)) Theta_reg_1_dff (Theta_temp_1, Theta_1_to_stage_2, clk,dff_clr);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:71: Cannot find file containing module: \'generaldff\'\ngeneraldff #(.DW(11)) Theta_reg_1_0_dff (Theta_1_0, Theta_1_0_to_stage_2, clk,dff_clr);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:73: Cannot find file containing module: \'generaldff\'\ngeneraldff #(.DW(13)) Pi2n_plus_K4_init_dff (Pi2n_plus_K4_init, Pi2n_plus_K4_init_to_stage_2, clk,dff_clr);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:74: Cannot find file containing module: \'generaldff\'\ngeneraldff #(.DW(13)) Pi2n_plus_3K4_init_dff (Pi2n_plus_3K4_init, Pi2n_plus_3K4_init_to_stage_2, clk,dff_clr);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/206261917/src/interleaver_stage_1.v:75: Cannot find file containing module: \'generaldff\'\ngeneraldff #(.DW(13)) Pi2n_plus_K2_init_dff (Pi2n_plus_K2_init, Pi2n_plus_K2_init_to_stage_2, clk,dff_clr);\n^~~~~~~~~~\n%Error: Exiting due to 7 error(s), 23 warning(s)\n'
module interleaver_stage_1(
input[12:0] 	K_i,
input	    	clk,
input[8:0]  	f1,
input[9:0]  	f2,
input 			flag,
input[14:0]		Theta_0_previous,
input[14:0]		Theta_1_previous,
input			dff_clr,


output[9:0]     counter_r,
output[10:0]    Theta_1_0_to_stage_2,
output[14:0]	Theta_0_to_stage_2,
output[14:0]	Theta_1_to_stage_2,
output[12:0]	Pi2n_plus_K4_init_to_stage_2,
output[12:0]	Pi2n_plus_3K4_init_to_stage_2, 
output[12:0]	Pi2n_plus_K2_init_to_stage_2   
);






wire[13:0]	  K_mul_2 = {K_i , 1'b0};
wire[14:0]	  K_mul_4 = {K_i , 2'b0};
wire[10:0]    K_div_4 = K_i[12:2];


wire[12:0]    b_2_temp = {f2,3'b0};
wire[14:0]    b_2 = (b_2_temp > K_mul_4) ? (b_2_temp - K_mul_4) : 
						((b_2_temp > K_mul_2) ? (b_2_temp - K_mul_2) : ((b_2_temp > K_i) ? b_2_temp - K_i : b_2_temp )); 
						
wire[10:0]    Theta_1_0 = f1 + f2;
wire[12:0]    Theta_2_0_temp = {f1,1'b0} + {f2,2'b0};
wire[13:0]    Theta_2_1_temp = {f1,1'b0} + {f2,3'b0};
wire[13:0]    Theta_2_0 = (Theta_2_0_temp > K_mul_2) ? (Theta_2_0_temp - K_mul_2) : 
								((Theta_2_0_temp > K_i) ? Theta_2_0_temp - K_i : Theta_2_0_temp );
								
wire[14:0]    Theta_2_1 = (Theta_2_1_temp > K_mul_4) ? (Theta_2_1_temp - K_mul_4) : 
								((Theta_2_1_temp > K_mul_2) ? (Theta_2_1_temp - K_mul_2) : ((Theta_2_1_temp > K_i) ? Theta_2_1_temp - K_i : Theta_2_1_temp ));

wire[14:0]	  Theta_temp_0 = (counter_r == 0) ? 15'b000_0000_0000_0000 : 
								(counter_r == 1) ? Theta_2_0 :
													(((Theta_0_previous + b_2) < K_i) ? Theta_0_previous + b_2 : Theta_0_previous + b_2 - K_i );

wire[14:0]	  Theta_temp_1 = (counter_r == 0) ? 15'b000_0000_0000_0000 : 
								(counter_r == 1) ? Theta_2_1 :
													(((Theta_1_previous + b_2) < K_i) ? Theta_1_previous + b_2 : Theta_1_previous + b_2 - K_i );

wire[12:0]	  Pi2n_plus_K4_init = (flag == 1) ? {K_div_4,2'b0} - K_div_4 : {2'b0,K_div_4};
wire[12:0]	  Pi2n_plus_3K4_init = (flag == 1) ? {2'b0,K_div_4}  : {K_div_4,2'b0} - K_div_4;
wire[12:0]	  Pi2n_plus_K2_init = {1'b0,K_i[12:1]};

wire[9:0]     counter_next = counter_r + 1;



generaldff #(.DW(10)) counter_dff ( .dnxt(counter_next), .qout(counter_r), .clk(clk),.rst_n(dff_clr));
generaldff #(.DW(15)) Theta_reg_0_dff (Theta_temp_0, Theta_0_to_stage_2, clk,dff_clr);
generaldff #(.DW(15)) Theta_reg_1_dff (Theta_temp_1, Theta_1_to_stage_2, clk,dff_clr);
generaldff #(.DW(11)) Theta_reg_1_0_dff (Theta_1_0, Theta_1_0_to_stage_2, clk,dff_clr);

generaldff #(.DW(13)) Pi2n_plus_K4_init_dff (Pi2n_plus_K4_init, Pi2n_plus_K4_init_to_stage_2, clk,dff_clr);
generaldff #(.DW(13)) Pi2n_plus_3K4_init_dff (Pi2n_plus_3K4_init, Pi2n_plus_3K4_init_to_stage_2, clk,dff_clr);
generaldff #(.DW(13)) Pi2n_plus_K2_init_dff (Pi2n_plus_K2_init, Pi2n_plus_K2_init_to_stage_2, clk,dff_clr);

endmodule
module interleaver_stage_1(
input[12:0] 	K_i,
input	    	clk,
input[8:0]  	f1,
input[9:0]  	f2,
input 			flag,
input[14:0]		Theta_0_previous,
input[14:0]		Theta_1_previous,
input			dff_clr,


output[9:0]     counter_r,
output[10:0]    Theta_1_0_to_stage_2,
output[14:0]	Theta_0_to_stage_2,
output[14:0]	Theta_1_to_stage_2,
output[12:0]	Pi2n_plus_K4_init_to_stage_2,
output[12:0]	Pi2n_plus_3K4_init_to_stage_2, 
output[12:0]	Pi2n_plus_K2_init_to_stage_2   
);







wire[13:0]	  K_mul_2 = {K_i , 1'b0};
wire[14:0]	  K_mul_4 = {K_i , 2'b0};
wire[10:0]    K_div_4 = K_i[12:2];


wire[12:0]    b_2_temp = {f2,3'b0};
wire[14:0]    b_2 = (b_2_temp > K_mul_4) ? (b_2_temp - K_mul_4) : 
						((b_2_temp > K_mul_2) ? (b_2_temp - K_mul_2) : ((b_2_temp > K_i) ? b_2_temp - K_i : b_2_temp )); 
						
wire[10:0]    Theta_1_0 = f1 + f2;
wire[12:0]    Theta_2_0_temp = {f1,1'b0} + {f2,2'b0};
wire[13:0]    Theta_2_1_temp = {f1,1'b0} + {f2,3'b0};
wire[13:0]    Theta_2_0 = (Theta_2_0_temp > K_mul_2) ? (Theta_2_0_temp - K_mul_2) : 
								((Theta_2_0_temp > K_i) ? Theta_2_0_temp - K_i : Theta_2_0_temp );
								
wire[14:0]    Theta_2_1 = (Theta_2_1_temp > K_mul_4) ? (Theta_2_1_temp - K_mul_4) : 
								((Theta_2_1_temp > K_mul_2) ? (Theta_2_1_temp - K_mul_2) : ((Theta_2_1_temp > K_i) ? Theta_2_1_temp - K_i : Theta_2_1_temp ));

wire[14:0]	  Theta_temp_0 = (counter_r == 0) ? 15'b000_0000_0000_0000 : 
								(counter_r == 1) ? Theta_2_0 :
													(((Theta_0_previous + b_2) < K_i) ? Theta_0_previous + b_2 : Theta_0_previous + b_2 - K_i );

wire[14:0]	  Theta_temp_1 = (counter_r == 0) ? 15'b000_0000_0000_0000 : 
								(counter_r == 1) ? Theta_2_1 :
													(((Theta_1_previous + b_2) < K_i) ? Theta_1_previous + b_2 : Theta_1_previous + b_2 - K_i );

wire[12:0]	  Pi2n_plus_K4_init = (flag == 1) ? {K_div_4,2'b0} - K_div_4 : {2'b0,K_div_4};
wire[12:0]	  Pi2n_plus_3K4_init = (flag == 1) ? {2'b0,K_div_4}  : {K_div_4,2'b0} - K_div_4;
wire[12:0]	  Pi2n_plus_K2_init = {1'b0,K_i[12:1]};

wire[9:0]     counter_next = counter_r + 1;



generaldff #(.DW(10)) counter_dff ( .dnxt(counter_next), .qout(counter_r), .clk(clk),.rst_n(dff_clr));
generaldff #(.DW(15)) Theta_reg_0_dff (Theta_temp_0, Theta_0_to_stage_2, clk,dff_clr);
generaldff #(.DW(15)) Theta_reg_1_dff (Theta_temp_1, Theta_1_to_stage_2, clk,dff_clr);
generaldff #(.DW(11)) Theta_reg_1_0_dff (Theta_1_0, Theta_1_0_to_stage_2, clk,dff_clr);

generaldff #(.DW(13)) Pi2n_plus_K4_init_dff (Pi2n_plus_K4_init, Pi2n_plus_K4_init_to_stage_2, clk,dff_clr);
generaldff #(.DW(13)) Pi2n_plus_3K4_init_dff (Pi2n_plus_3K4_init, Pi2n_plus_3K4_init_to_stage_2, clk,dff_clr);
generaldff #(.DW(13)) Pi2n_plus_K2_init_dff (Pi2n_plus_K2_init, Pi2n_plus_K2_init_to_stage_2, clk,dff_clr);

endmodule