data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono1.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono1.v:107: Signal definition not found, creating implicitly: \'cnt\'\n    assign cnt = ~|dcount;\n           ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono1.v:175: Signal definition not found, creating implicitly: \'s1end\'\n                                                                                                                : ... Suggested alternative: \'c1end\'\n            if (s1end)\n                ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/111433415/verilog/07_subsistemas_sec/07-3_cronometro/chrono1.v:101: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 26 bits.\n                                                                                                             : ... In instance chrono1\n            dcount <= FDIV - 1;\n                   ^~\n%Error: Exiting due to 3 warning(s)\n'
module chrono1 #(


    parameter FREQ = 50000000
    )(
    input wire ck,
    input wire cl,
    input wire start,
    output reg [3:0] c0,
    output reg [3:0] c1,
    output reg [3:0] s0,
    output reg [3:0] s1
    );



    localparam FDIV = FREQ/100;


    reg [23:0] dcount;


    wire c0end;
    wire c1end;
    wire s0end;



    always @(posedge ck) begin
        if (start == 0 || cl == 1 || dcount == 0)
            dcount <= FDIV - 1;
        else
            dcount <= dcount - 1;
    end


    assign cnt = ~|dcount;



    always @(posedge ck) begin
        if (cl)

            c0 <= 0;
        else if (cnt) begin

            if (c0end)

                c0 <= 0;
            else

                c0 <= c0 + 1;
        end
    end


    assign c0end = (c0 == 9)? 1:0;



    always @(posedge ck) begin
        if (cl)
            c1 <= 0;
        else if (cnt & c0end) begin

            if (c1end)
                c1 <= 0;
            else
                c1 <= c1 + 1;
        end
    end


    assign c1end = (c1 == 9)? 1:0;


    always @(posedge ck) begin
        if (cl)
            s0 <= 0;
        else if (cnt & c1end & c0end) begin

            if (s0end)
                s0 <= 0;
            else
                s0 <= s0 + 1;
        end
    end


    assign s0end = (s0 == 9)? 1:0;


    always @(posedge ck) begin
        if (cl)
            s1 <= 0;
        else if (cnt & s0end & c1end & c0end) begin
            if (s1end)
                s1 <= 0;
            else
                s1 <= s1 + 1;
        end
    end

    assign s1end = (s1 == 5)? 1:0;

endmodule
module chrono1 #(


    parameter FREQ = 50000000
    )(
    input wire ck,
    input wire cl,
    input wire start,
    output reg [3:0] c0,
    output reg [3:0] c1,
    output reg [3:0] s0,
    output reg [3:0] s1
    );




    localparam FDIV = FREQ/100;


    reg [23:0] dcount;


    wire c0end;
    wire c1end;
    wire s0end;



    always @(posedge ck) begin
        if (start == 0 || cl == 1 || dcount == 0)
            dcount <= FDIV - 1;
        else
            dcount <= dcount - 1;
    end


    assign cnt = ~|dcount;



    always @(posedge ck) begin
        if (cl)

            c0 <= 0;
        else if (cnt) begin

            if (c0end)

                c0 <= 0;
            else

                c0 <= c0 + 1;
        end
    end


    assign c0end = (c0 == 9)? 1:0;



    always @(posedge ck) begin
        if (cl)
            c1 <= 0;
        else if (cnt & c0end) begin

            if (c1end)
                c1 <= 0;
            else
                c1 <= c1 + 1;
        end
    end


    assign c1end = (c1 == 9)? 1:0;


    always @(posedge ck) begin
        if (cl)
            s0 <= 0;
        else if (cnt & c1end & c0end) begin

            if (s0end)
                s0 <= 0;
            else
                s0 <= s0 + 1;
        end
    end


    assign s0end = (s0 == 9)? 1:0;


    always @(posedge ck) begin
        if (cl)
            s1 <= 0;
        else if (cnt & s0end & c1end & c0end) begin
            if (s1end)
                s1 <= 0;
            else
                s1 <= s1 + 1;
        end
    end

    assign s1end = (s1 == 5)? 1:0;

endmodule