data/full_repos/permissive/181665138/verilog/capitolo_iii/Clock.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/181665138/verilog/capitolo_iii/Clock.v:20: Unsupported: Ignoring delay on this delayed statement.\n    always #4 CLOCK = ~CLOCK;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Clock(clock);
    output clock;

    reg CLOCK;

    initial
        begin
            CLOCK = 0;
        end

    always #4 CLOCK = ~CLOCK;

    assign clock = CLOCK;
endmodule
module Clock(clock);

    output clock;

    reg CLOCK;

    initial
        begin
            CLOCK = 0;
        end

    always #4 CLOCK = ~CLOCK;

    assign clock = CLOCK;
endmodule