data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_CDMA_WT_sp_arb.v
1: b'%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_CDMA_WT_sp_arb.v:9: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/simulate_x_tick.vh\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/simulate_x_tick.vh.v\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/simulate_x_tick.vh.sv\n             simulate_x_tick.vh\n             simulate_x_tick.vh.v\n             simulate_x_tick.vh.sv\n             obj_dir/simulate_x_tick.vh\n             obj_dir/simulate_x_tick.vh.v\n             obj_dir/simulate_x_tick.vh.sv\n%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_CDMA_WT_sp_arb.v:60: Define or directive not defined: \'`x_or_0\'\n                        gnt_pre[1:0] = {2{`x_or_0}};\n                                          ^~~~~~~\n%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_CDMA_WT_sp_arb.v:60: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n                        gnt_pre[1:0] = {2{`x_or_0}};\n                                                 ^\n%Error: Exiting due to 3 error(s)\n'
module NV_NVDLA_CDMA_WT_sp_arb (
   req0
  ,req1
  ,gnt_busy
  ,gnt0
  ,gnt1
  );

input req0;
input req1;
input gnt_busy;
output gnt0;
output gnt1;

reg [1:0] gnt;
reg [1:0] gnt_pre;
wire [1:0] req;
assign req = {
 req1
,req0
};
assign {
 gnt1
,gnt0
} = gnt;
always @(
  gnt_busy
  or gnt_pre
  ) begin
    gnt = {2{!gnt_busy}} & gnt_pre;
end



always @(
  req
  ) begin
    gnt_pre = 2'd0;
    casez (req)
        2'b?1: begin
            gnt_pre[0] = 1'b1;
        end
        2'b10: begin
            gnt_pre[1] = 1'b1;
        end
        2'b00: begin
            gnt_pre = 2'd0;
        end

            default : begin
                        gnt_pre[1:0] = {2{`x_or_0}};
                      end

    endcase
end



endmodule
module NV_NVDLA_CDMA_WT_sp_arb (
   req0
  ,req1
  ,gnt_busy
  ,gnt0
  ,gnt1
  );


input req0;
input req1;
input gnt_busy;
output gnt0;
output gnt1;

reg [1:0] gnt;
reg [1:0] gnt_pre;
wire [1:0] req;
assign req = {
 req1
,req0
};
assign {
 gnt1
,gnt0
} = gnt;
always @(
  gnt_busy
  or gnt_pre
  ) begin
    gnt = {2{!gnt_busy}} & gnt_pre;
end



always @(
  req
  ) begin
    gnt_pre = 2'd0;
    casez (req)
        2'b?1: begin
            gnt_pre[0] = 1'b1;
        end
        2'b10: begin
            gnt_pre[1] = 1'b1;
        end
        2'b00: begin
            gnt_pre = 2'd0;
        end

            default : begin
                        gnt_pre[1:0] = {2{`x_or_0}};
                      end

    endcase
end



endmodule