data/full_repos/permissive/126689099/da2.v
data/verilator_xmls/d6c0d516-71ea-412b-95ad-286325f70507.xml
module da2(
	input clk,
	input rst_n,
	input[13:0] real_da1, 
	input[13:0] real_da2, 
	output[13:0] dadata1,	
	output[13:0] dadata2
    );
	 
reg[13:0] reg_dadata1;
reg[13:0] reg_dadata2;

assign dadata1 = reg_dadata1;
assign dadata2 = reg_dadata2;

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		reg_dadata1 <= 14'b0000_00000_00000;
	end
	else
	begin
		reg_dadata1 <= real_da1;
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		reg_dadata2 <= 14'b0000_00000_00000;
	end
	else
	begin
		reg_dadata2 <= real_da2;
	end
end

endmodule
module da2(
	input clk,
	input rst_n,
	input[13:0] real_da1, 
	input[13:0] real_da2, 
	output[13:0] dadata1,	
	output[13:0] dadata2
    );

	 
reg[13:0] reg_dadata1;
reg[13:0] reg_dadata2;

assign dadata1 = reg_dadata1;
assign dadata2 = reg_dadata2;

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		reg_dadata1 <= 14'b0000_00000_00000;
	end
	else
	begin
		reg_dadata1 <= real_da1;
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		reg_dadata2 <= 14'b0000_00000_00000;
	end
	else
	begin
		reg_dadata2 <= real_da2;
	end
end

endmodule