data/full_repos/permissive/115632823/code/Stream Multi-processor/SM.srcs/sources_1/new/MulticastNetwork.v
1: b'%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n        ... Looked in:\n             data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n             data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n             data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n             Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n             Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n             Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n             obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n             obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n             obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115632823/code/Stream\n%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new/MulticastNetwork.v\n%Error: Exiting due to 3 error(s)\n'
module MulticastNetwork(


    input wire [32*16-1:0] DataIn,
    input wire [8*16-1:0] RequestVector,
    input wire [7:0] ReturnIn,
    output reg [32*8-1:0] DataOut,

    output wire [7:0] ReturnOut
);

integer i;
integer j;

assign ReturnOut = ReturnIn;

reg [31:0]DataInReal[15:0];
reg [7:0] RequestVectorReal[15:0];
reg [31:0] DataOutReal[7:0];

always@(DataIn or RequestVector or ReturnIn) begin
    for(i = 0; i < 16; i = i + 1) begin
        for(j = 0; j < 32; j = j + 1) begin
            DataInReal[i][j] <= DataIn[i*32+j];
        end
    end
    for(i = 0; i < 8; i = i + 1) begin
        for(j = 0; j < 16; j = j + 1) begin
            RequestVectorReal[i][j] <= RequestVector[i*8+j];
        end
    end
    for(i = 0; i < 16; i = i + 1) begin
        for(j = 0; j < 8; j = j + 1) begin
            if(RequestVectorReal[j] == 1) begin
                DataOutReal[j] <= DataInReal[i];
            end
        end
    end
    for(i = 0; i < 8; i = i + 1) begin
        for(j = 0; j < 32; j = j + 1) begin
            DataOut[i*8+j] <= DataOutReal[i][j];
        end
    end
end

endmodule
module MulticastNetwork(


    input wire [32*16-1:0] DataIn,
    input wire [8*16-1:0] RequestVector,
    input wire [7:0] ReturnIn,
    output reg [32*8-1:0] DataOut,

    output wire [7:0] ReturnOut
);


integer i;
integer j;

assign ReturnOut = ReturnIn;

reg [31:0]DataInReal[15:0];
reg [7:0] RequestVectorReal[15:0];
reg [31:0] DataOutReal[7:0];

always@(DataIn or RequestVector or ReturnIn) begin
    for(i = 0; i < 16; i = i + 1) begin
        for(j = 0; j < 32; j = j + 1) begin
            DataInReal[i][j] <= DataIn[i*32+j];
        end
    end
    for(i = 0; i < 8; i = i + 1) begin
        for(j = 0; j < 16; j = j + 1) begin
            RequestVectorReal[i][j] <= RequestVector[i*8+j];
        end
    end
    for(i = 0; i < 16; i = i + 1) begin
        for(j = 0; j < 8; j = j + 1) begin
            if(RequestVectorReal[j] == 1) begin
                DataOutReal[j] <= DataInReal[i];
            end
        end
    end
    for(i = 0; i < 8; i = i + 1) begin
        for(j = 0; j < 32; j = j + 1) begin
            DataOut[i*8+j] <= DataOutReal[i][j];
        end
    end
end

endmodule