data/full_repos/permissive/200314387/verilog/reset/test.v
 line:82 column:2: Illegal character '\x00'
1: b'%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:3: Cannot find include file: ../pc/pc.v\n`include "../pc/pc.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/reset,data/full_repos/permissive/200314387/../pc/pc.v\n             data/full_repos/permissive/200314387/verilog/reset,data/full_repos/permissive/200314387/../pc/pc.v.v\n             data/full_repos/permissive/200314387/verilog/reset,data/full_repos/permissive/200314387/../pc/pc.v.sv\n             ../pc/pc.v\n             ../pc/pc.v.v\n             ../pc/pc.v.sv\n             obj_dir/../pc/pc.v\n             obj_dir/../pc/pc.v.v\n             obj_dir/../pc/pc.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:4: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:5: Cannot find include file: reset.v\n`include "reset.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:59: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:60: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:71: Define or directive not defined: \'`Equals\'\n        `Equals(pc, 16\'hffff);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:71: syntax error, unexpected \',\'\n        `Equals(pc, 16\'hffff);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:75: Define or directive not defined: \'`Equals\'\n        `Equals(_mrNeg, \'x);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:75: syntax error, unexpected \',\'\n        `Equals(_mrNeg, \'x);\n                      ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:76: Define or directive not defined: \'`Equals\'\n        `Equals(_phase_exec, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:76: syntax error, unexpected \',\'\n        `Equals(_phase_exec, 1\'b1);\n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:77: Define or directive not defined: \'`Equals\'\n        `Equals(pc, 16\'hffff);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:77: syntax error, unexpected \',\'\n        `Equals(pc, 16\'hffff);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:86: Define or directive not defined: \'`Equals\'\n        `Equals(_phase_exec, 1\'b0);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:86: syntax error, unexpected \',\'\n        `Equals(_phase_exec, 1\'b0);\n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:87: Define or directive not defined: \'`Equals\'\n        `Equals(_mrNeg, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:87: syntax error, unexpected \',\'\n        `Equals(_mrNeg, 1\'b1);\n                      ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:88: Define or directive not defined: \'`Equals\'\n        `Equals(pc, 16\'hffff);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:88: syntax error, unexpected \',\'\n        `Equals(pc, 16\'hffff);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:92: Define or directive not defined: \'`Equals\'\n        `Equals(_phase_exec, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:92: syntax error, unexpected \',\'\n        `Equals(_phase_exec, 1\'b1);\n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:93: Define or directive not defined: \'`Equals\'\n        `Equals(_mrNeg, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:93: syntax error, unexpected \',\'\n        `Equals(_mrNeg, 1\'b1);\n                      ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:94: Define or directive not defined: \'`Equals\'\n        `Equals(pc, 16\'h0000);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:94: syntax error, unexpected \',\'\n        `Equals(pc, 16\'h0000);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:100: Define or directive not defined: \'`Equals\'\n        `Equals(_phase_exec, 1\'b0);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:100: syntax error, unexpected \',\'\n        `Equals(_phase_exec, 1\'b0);\n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:101: Define or directive not defined: \'`Equals\'\n        `Equals(_mrNeg, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:101: syntax error, unexpected \',\'\n        `Equals(_mrNeg, 1\'b1);\n                      ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:102: Define or directive not defined: \'`Equals\'\n        `Equals(pc, 16\'h0000);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:102: syntax error, unexpected \',\'\n        `Equals(pc, 16\'h0000);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:106: Define or directive not defined: \'`Equals\'\n        `Equals(_phase_exec, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:106: syntax error, unexpected \',\'\n        `Equals(_phase_exec, 1\'b1);\n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:107: Define or directive not defined: \'`Equals\'\n        `Equals(_mrNeg, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:107: syntax error, unexpected \',\'\n        `Equals(_mrNeg, 1\'b1);\n                      ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:108: Define or directive not defined: \'`Equals\'\n        `Equals(pc, 16\'h0001);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:108: syntax error, unexpected \',\'\n        `Equals(pc, 16\'h0001);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:113: Define or directive not defined: \'`Equals\'\n        `Equals(_phase_exec, 1\'b0);  \n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:113: syntax error, unexpected \',\'\n        `Equals(_phase_exec, 1\'b0);  \n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:114: Define or directive not defined: \'`Equals\'\n        `Equals(_mrNeg, 1\'b0);  \n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:114: syntax error, unexpected \',\'\n        `Equals(_mrNeg, 1\'b0);  \n                      ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:115: Define or directive not defined: \'`Equals\'\n        `Equals(pc, 16\'h0001);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:115: syntax error, unexpected \',\'\n        `Equals(pc, 16\'h0001);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:122: Define or directive not defined: \'`Equals\'\n        `Equals(_phase_exec, 1\'b0);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:122: syntax error, unexpected \',\'\n        `Equals(_phase_exec, 1\'b0);\n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:123: Define or directive not defined: \'`Equals\'\n        `Equals(_mrNeg, 1\'b0);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:123: syntax error, unexpected \',\'\n        `Equals(_mrNeg, 1\'b0);\n                      ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:124: Define or directive not defined: \'`Equals\'\n        `Equals(pc, 16\'h0001);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:124: syntax error, unexpected \',\'\n        `Equals(pc, 16\'h0001);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/reset/test.v:128: Define or directive not defined: \'`Equals\'\n        `Equals(_phase_exec, 1\'b0);\n        ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module test(
);

    parameter LOG=0;
    parameter GAP=100;

    logic _RESET_SWITCH;
    logic system_clk;
    
    wire _mrPos, _mrNeg, _phase_exec;

    reset RESET(
        ._RESET_SWITCH,
        .system_clk,
        ._phase_exec(_phase_exec),
        ._mrNeg
    );



    wire [7:0] pc_din = 8'haa;
    wire [7:0] PCHI, PCLO;
    wire [15:0] pc = {PCHI, PCLO}; 

    logic _do_jmp = 1;
    logic _pclo_in = 1;
    logic _pchitmp_in = 1;
    

    pc #(.LOG(0))  PC (
        .clk(system_clk),
        ._MR(_mrNeg),
        ._long_jump(_do_jmp),
        ._local_jump(_pclo_in),
        ._pchitmp_in(_pchitmp_in),
        .D(pc_din),

        .PCLO(PCLO),
        .PCHI(PCHI)
    );


    integer count;

    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0, test);

        _RESET_SWITCH = 1;
        system_clk=1;
        #GAP

        PC.PCHI_7_4.count = 15;
        PC.PCHI_3_0.count = 15;
        PC.PCLO_7_4.count = 15;
        PC.PCLO_3_0.count = 15;
        #GAP
        `Equals(pc, 16'hffff);

        system_clk=1;
        #GAP
        `Equals(_mrNeg, 'x);
        `Equals(_phase_exec, 1'b1);
        `Equals(pc, 16'hffff);
    
        $display("RESET HIGH");
        _RESET_SWITCH = 1;
        #GAP


        system_clk=1'b0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b1);
        `Equals(pc, 16'hffff);

        system_clk=1;
        #GAP
        `Equals(_phase_exec, 1'b1);
        `Equals(_mrNeg, 1'b1);
        `Equals(pc, 16'h0000);



        system_clk=0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b1);
        `Equals(pc, 16'h0000);

        system_clk=1;
        #GAP
        `Equals(_phase_exec, 1'b1);
        `Equals(_mrNeg, 1'b1);
        `Equals(pc, 16'h0001);

        $display("SET RESET LOW => instant _mrNeg=0 without clock");
        _RESET_SWITCH = 0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0001);



        $display("RESET STILL LOW => pc reset on system clock +ve");
        system_clk=0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0001);

        system_clk=1;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0000);



        $display("RESET STILL LOW => no counting");
        system_clk=0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0000);

        system_clk=1;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0000);



        $display("RESET RELEASE => _mrNeg stays low and no counting yet");
        _RESET_SWITCH = 1;
        system_clk=0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0000);

        system_clk=1;
        #GAP
        `Equals(_phase_exec, 1'b1);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0000);



        $display("_mrNeg goes high and Counting starts");
        system_clk=0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b1);
        `Equals(pc, 16'h0000);

        system_clk=1;
        #GAP
        `Equals(_phase_exec, 1'b1);
        `Equals(_mrNeg, 1'b1);
        `Equals(pc, 16'h0001);

        #GAP
        $display("DONE");
    end

    always @* $display("%9t ", $time, "      _mrNeg %1b  ", _mrNeg);
    always @* $display("%9t ", $time, "       pc %04h ", pc);

endmodule
module test(
);


    parameter LOG=0;
    parameter GAP=100;

    logic _RESET_SWITCH;
    logic system_clk;
    
    wire _mrPos, _mrNeg, _phase_exec;

    reset RESET(
        ._RESET_SWITCH,
        .system_clk,
        ._phase_exec(_phase_exec),
        ._mrNeg
    );



    wire [7:0] pc_din = 8'haa;
    wire [7:0] PCHI, PCLO;
    wire [15:0] pc = {PCHI, PCLO}; 

    logic _do_jmp = 1;
    logic _pclo_in = 1;
    logic _pchitmp_in = 1;
    

    pc #(.LOG(0))  PC (
        .clk(system_clk),
        ._MR(_mrNeg),
        ._long_jump(_do_jmp),
        ._local_jump(_pclo_in),
        ._pchitmp_in(_pchitmp_in),
        .D(pc_din),

        .PCLO(PCLO),
        .PCHI(PCHI)
    );


    integer count;

    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0, test);

        _RESET_SWITCH = 1;
        system_clk=1;
        #GAP

        PC.PCHI_7_4.count = 15;
        PC.PCHI_3_0.count = 15;
        PC.PCLO_7_4.count = 15;
        PC.PCLO_3_0.count = 15;
        #GAP
        `Equals(pc, 16'hffff);

        system_clk=1;
        #GAP
        `Equals(_mrNeg, 'x);
        `Equals(_phase_exec, 1'b1);
        `Equals(pc, 16'hffff);
    
        $display("RESET HIGH");
        _RESET_SWITCH = 1;
        #GAP


        system_clk=1'b0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b1);
        `Equals(pc, 16'hffff);

        system_clk=1;
        #GAP
        `Equals(_phase_exec, 1'b1);
        `Equals(_mrNeg, 1'b1);
        `Equals(pc, 16'h0000);



        system_clk=0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b1);
        `Equals(pc, 16'h0000);

        system_clk=1;
        #GAP
        `Equals(_phase_exec, 1'b1);
        `Equals(_mrNeg, 1'b1);
        `Equals(pc, 16'h0001);

        $display("SET RESET LOW => instant _mrNeg=0 without clock");
        _RESET_SWITCH = 0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0001);



        $display("RESET STILL LOW => pc reset on system clock +ve");
        system_clk=0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0001);

        system_clk=1;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0000);



        $display("RESET STILL LOW => no counting");
        system_clk=0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0000);

        system_clk=1;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0000);



        $display("RESET RELEASE => _mrNeg stays low and no counting yet");
        _RESET_SWITCH = 1;
        system_clk=0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0000);

        system_clk=1;
        #GAP
        `Equals(_phase_exec, 1'b1);
        `Equals(_mrNeg, 1'b0);
        `Equals(pc, 16'h0000);



        $display("_mrNeg goes high and Counting starts");
        system_clk=0;
        #GAP
        `Equals(_phase_exec, 1'b0);
        `Equals(_mrNeg, 1'b1);
        `Equals(pc, 16'h0000);

        system_clk=1;
        #GAP
        `Equals(_phase_exec, 1'b1);
        `Equals(_mrNeg, 1'b1);
        `Equals(pc, 16'h0001);

        #GAP
        $display("DONE");
    end

    always @* $display("%9t ", $time, "      _mrNeg %1b  ", _mrNeg);
    always @* $display("%9t ", $time, "       pc %04h ", pc);

endmodule