data/full_repos/permissive/20985349/vlogpp2/test/m3.v
 line:7: before: "wildcard"
1: b'%Error: data/full_repos/permissive/20985349/vlogpp2/test/m3.v:12: syntax error, unexpected $display\n$display("left side: \\"right side\\"");\n^~~~~~~~\n%Error: data/full_repos/permissive/20985349/vlogpp2/test/m3.v:14: Unsupported: SystemVerilog 2005 reserved word not implemented: \'wildcard\'\nwildcard bins dog_zero = {0};\n^~~~~~~~\n%Error: data/full_repos/permissive/20985349/vlogpp2/test/m3.v:14: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nwildcard bins dog_zero = {0};\n         ^~~~\n%Error: data/full_repos/permissive/20985349/vlogpp2/test/m3.v:14: syntax error, unexpected \'=\', expecting \',\' or \';\'\nwildcard bins dog_zero = {0};\n                       ^\n%Error: data/full_repos/permissive/20985349/vlogpp2/test/m3.v:14: Unsupported: SystemVerilog 2005 reserved word not implemented: \'wildcard\'\nwildcard bins dog_two = {2};\n^~~~~~~~\n%Error: data/full_repos/permissive/20985349/vlogpp2/test/m3.v:14: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\nwildcard bins dog_two = {2};\n         ^~~~\n%Error: Exiting due to 6 error(s)\n'
module m3;
`PASTE
$display(`msg(left side,right side));
`append(clock)
`poobah(dog)
endmodule
module m3;

`PASTE
$display(`msg(left side,right side));
`append(clock)
`poobah(dog)
endmodule