data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-3_analisis/analisis.v
1: b"%Error: data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-3_analisis/analisis.v:60: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n    nand nand_1( );\n                 ^\n%Error: Exiting due to 1 error(s)\n"
module mux2 (
    input  wire [1:0] in,
    input  wire       sel,
    input  wire       en,
    output reg        out
    );



endmodule
module mux2 (
    input  wire [1:0] in,
    input  wire       sel,
    input  wire       en,
    output reg        out
    );




endmodule