data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.v
 line:23: before: ")"
1: b"%Error: data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.v:23: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.v:26: syntax error, unexpected always\n    always @(posedge CLK)\n    ^~~~~~\n%Error: data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.v:49: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.v:52: syntax error, unexpected always\n    always @(posedge CLK)\n    ^~~~~~\n%Error: data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.v:75: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.v:78: syntax error, unexpected always\n    always @(posedge CLK)\n    ^~~~~~\n%Error: data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.v:101: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/220229160/dsp-ff-plugin/tests/nexus_conn_share/nexus_conn_share.v:104: syntax error, unexpected always\n    always @(posedge CLK)\n    ^~~~~~\n%Error: Exiting due to 8 error(s)\n"
module conflict_inp_fanout (
    input  wire        CLK,
    input  wire [ 8:0] A,
    input  wire [ 8:0] B,
    output reg  [17:0] Z,
    output wire [ 3:0] X,
);

    wire [8:0] ra;
    always @(posedge CLK)
        ra <= A;

    MULT9X9 # (
        .REGINPUTA("BYPASS"),
        .REGINPUTB("BYPASS"),
        .REGOUTPUT("BYPASS")
    ) mult (
        .A (ra),
        .B (B),
        .Z (Z)
    );

    assign X = ~ra[3:0];

endmodule
module conflict_inp_fanout (
    input  wire        CLK,
    input  wire [ 8:0] A,
    input  wire [ 8:0] B,
    output reg  [17:0] Z,
    output wire [ 3:0] X,
);


    wire [8:0] ra;
    always @(posedge CLK)
        ra <= A;

    MULT9X9 # (
        .REGINPUTA("BYPASS"),
        .REGINPUTB("BYPASS"),
        .REGOUTPUT("BYPASS")
    ) mult (
        .A (ra),
        .B (B),
        .Z (Z)
    );

    assign X = ~ra[3:0];

endmodule