data/full_repos/permissive/136584400/lab02-Simple_combination_circuit/lab2-1/sources/lab2-1.v
None: at end of input
data/verilator_xmls/2fd5504c-26a9-4623-b14c-981ba89117c1.xml
module _7Seg_Driver_Direct(SW, CA, CB, CC, CD, CE, CF, CG, DP, AN, LED);
  input [15:0] SW;
	output CA, CB, CC, CD, CE, CF, CG, DP;
	output [7:0] AN;
	output [15:0] LED;

	assign {CA, CB, CC, CD, CE, CF, CG, DP} = SW[7:0];
	assign AN[7:0] = SW[15:8];
	assign LED[15:0] = SW[15:0];
endmodule
module _7Seg_Driver_Direct(SW, CA, CB, CC, CD, CE, CF, CG, DP, AN, LED);

  input [15:0] SW;
	output CA, CB, CC, CD, CE, CF, CG, DP;
	output [7:0] AN;
	output [15:0] LED;

	assign {CA, CB, CC, CD, CE, CF, CG, DP} = SW[7:0];
	assign AN[7:0] = SW[15:8];
	assign LED[15:0] = SW[15:0];
endmodule