data/full_repos/permissive/184916587/OLD/Test_Decoder.v
 line:32: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_Decoder.v:29: Unsupported: Ignoring delay on this delayed statement.\n   #0 instr=32\'b01000000000100010000000110110011;  \n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_Decoder.v:30: Unsupported: Ignoring delay on this delayed statement.\n   #5 instr=32\'b00000000001000001110010010110011;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_Decoder.v:31: Unsupported: Ignoring delay on this delayed statement.\n   #5 instr=32\'b00000000110000111010000010110011;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/OLD/Test_Decoder.v:32: Unsupported: Ignoring delay on this delayed statement.\n   #5 $finish;\n   ^\n%Error: data/full_repos/permissive/184916587/OLD/Test_Decoder.v:37: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("Decoder.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/184916587/OLD/Test_Decoder.v:38: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0,decode_test);\n   ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decode_test;
	reg[31:0] instr;

	wire[6:0] type_code;
	wire[9:0] alu_op;
	wire[4:0] rs1;
	wire[4:0] rs2;
	wire[4:0] rd;

	decoder dec_test(
		.instr(instr),
		.type_code(type_code),
		.alu_op(alu_op),
		.rs1(rs1),
		.rs2(rs2),
		.rd(rd)
	);
	
	initial
		begin
			#0 instr=32'b01000000000100010000000110110011;
			#5 instr=32'b00000000001000001110010010110011;
			#5 instr=32'b00000000110000111010000010110011;
			#5 $finish;
		end

	initial
		begin
			$dumpfile("Decoder.vcd");
			$dumpvars(0,decode_test);
		end
endmodule
module decode_test;

	reg[31:0] instr;

	wire[6:0] type_code;
	wire[9:0] alu_op;
	wire[4:0] rs1;
	wire[4:0] rs2;
	wire[4:0] rd;

	decoder dec_test(
		.instr(instr),
		.type_code(type_code),
		.alu_op(alu_op),
		.rs1(rs1),
		.rs2(rs2),
		.rd(rd)
	);
	
	initial
		begin
			#0 instr=32'b01000000000100010000000110110011;
			#5 instr=32'b00000000001000001110010010110011;
			#5 instr=32'b00000000110000111010000010110011;
			#5 $finish;
		end

	initial
		begin
			$dumpfile("Decoder.vcd");
			$dumpvars(0,decode_test);
		end
endmodule