data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:2: Multiple top level modules\n                                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                          : ... Top module \'$_DFF_N_\'\nmodule  \\$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1\'b0), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_P_\'\nmodule  \\$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1\'b0), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~\n                                                                                                          : ... Top module \'$_DFFE_NN_\'\nmodule  \\$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1\'b0), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFFE_PN_\'\nmodule  \\$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1\'b0), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFFE_NP_\'\nmodule  \\$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1\'b0), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFFE_PP_\'\nmodule  \\$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1\'b0), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_NN0_\'\nmodule  \\$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_NN1_\'\nmodule  \\$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_PN0_\'\nmodule  \\$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_PN1_\'\nmodule  \\$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_NP0_\'\nmodule  \\$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_NP1_\'\nmodule  \\$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_PP0_\'\nmodule  \\$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$_DFF_PP1_\'\nmodule  \\$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFS_NN0_\'\nmodule  \\$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFS_NN1_\'\nmodule  \\$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFS_PN0_\'\nmodule  \\$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFS_PN1_\'\nmodule  \\$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFS_NP0_\'\nmodule  \\$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFS_NP1_\'\nmodule  \\$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFS_PP0_\'\nmodule  \\$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFS_PP1_\'\nmodule  \\$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFE_NN0\'\nmodule  \\$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFE_NN1\'\nmodule  \\$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFE_PN0\'\nmodule  \\$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFE_PN1\'\nmodule  \\$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFE_NP0\'\nmodule  \\$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFE_NP1\'\nmodule  \\$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFE_PP0\'\nmodule  \\$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFE_PP1\'\nmodule  \\$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFSE_NN0\'\nmodule  \\$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFSE_NN1\'\nmodule  \\$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFSE_PN0\'\nmodule  \\$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFSE_PN1\'\nmodule  \\$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFSE_NP0\'\nmodule  \\$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFSE_NP1\'\nmodule  \\$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFSE_PP0\'\nmodule  \\$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'$__DFFSE_PP1\'\nmodule  \\$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n        ^~~~~~~~~~~~~\n                                                                                                          : ... Top module \'FD1S3BX\'\nmodule FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule\n       ^~~~~~~\n                                                                                                          : ... Top module \'$lut\'\nmodule \\$lut (A, Y);\n       ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:58: Little bit endian vector: MSB < LSB of bit range: -1:0\n    input [WIDTH-1:0] A;\n          ^\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:51: Cannot find file containing module: \'TRELLIS_FF\'\nmodule FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule\n                                           ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5,data/full_repos/permissive/200142067/TRELLIS_FF\n             data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5,data/full_repos/permissive/200142067/TRELLIS_FF.v\n             data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5,data/full_repos/permissive/200142067/TRELLIS_FF.sv\n             TRELLIS_FF\n             TRELLIS_FF.v\n             TRELLIS_FF.sv\n             obj_dir/TRELLIS_FF\n             obj_dir/TRELLIS_FF.v\n             obj_dir/TRELLIS_FF.sv\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:48: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:47: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:46: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:45: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:43: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:42: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:41: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:40: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:38: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:37: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:36: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:35: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:33: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:32: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:31: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:30: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:28: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:27: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:26: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:25: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:23: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:22: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:21: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:20: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:18: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:17: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:16: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:15: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:13: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:12: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:11: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:10: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:8: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1\'b0), .DI(D), .Q(Q)); endmodule\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:7: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1\'b0), .DI(D), .Q(Q)); endmodule\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:5: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1\'b0), .DI(D), .Q(Q)); endmodule\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:4: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1\'b0), .DI(D), .Q(Q)); endmodule\n                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:2: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1\'b0), .DI(D), .Q(Q)); endmodule\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/ecp5/cells_map.v:1: Cannot find file containing module: \'TRELLIS_FF\'\nmodule  \\$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1\'b0), .DI(D), .Q(Q)); endmodule\n                                          ^~~~~~~~~~\n%Error: Exiting due to 39 error(s), 2 warning(s)\n'
module  \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
module  \$__DFFS_PN1_ (input D, C, R, output Q);
 TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule