data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/top/b200/S6CLK2PIN.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/top/b200/S6CLK2PIN.v:7: Cannot find file containing module: 'ODDR2'\n    ODDR2 #(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/top/b200,data/full_repos/permissive/214858095/ODDR2\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/top/b200,data/full_repos/permissive/214858095/ODDR2.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/top/b200,data/full_repos/permissive/214858095/ODDR2.sv\n             ODDR2\n             ODDR2.v\n             ODDR2.sv\n             obj_dir/ODDR2\n             obj_dir/ODDR2.v\n             obj_dir/ODDR2.sv\n%Error: Exiting due to 1 error(s)\n"
module S6CLK2PIN
(
    input I,
    output O
);

    ODDR2 #(
           .DDR_ALIGNMENT("NONE"),
           .INIT(1'b0),
           .SRTYPE("ASYNC"))

         ODDR2_S6CLK2PIN
           (
        .Q(O),
        .C0(I),
        .C1(~I),
        .CE(1'b1),
        .D0(1'b1),
        .D1(1'b0),
        .R(1'b0),
        .S(1'b0) );

endmodule
module S6CLK2PIN
(
    input I,
    output O
);


    ODDR2 #(
           .DDR_ALIGNMENT("NONE"),
           .INIT(1'b0),
           .SRTYPE("ASYNC"))

         ODDR2_S6CLK2PIN
           (
        .Q(O),
        .C0(I),
        .C1(~I),
        .CE(1'b1),
        .D0(1'b1),
        .D1(1'b0),
        .R(1'b0),
        .S(1'b0) );

endmodule