data/full_repos/permissive/163115503/slow_loop/top.v
 line:4: before: ")"
1: b"%Error: data/full_repos/permissive/163115503/slow_loop/top.v:4: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/163115503/slow_loop/top.v:9: syntax error, unexpected always\n    always @(posedge CLK) begin\n    ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module top (
    input CLK,
    output LED,
);

    reg [23:0] count;
    reg led_state;

    always @(posedge CLK) begin
        count <= count + 1;

        if (count == 16000000) begin
            count <= 0;


            led_state = !led_state;
        end
    end

    assign LED = led_state;
endmodule
module top (
    input CLK,
    output LED,
);


    reg [23:0] count;
    reg led_state;

    always @(posedge CLK) begin
        count <= count + 1;

        if (count == 16000000) begin
            count <= 0;


            led_state = !led_state;
        end
    end

    assign LED = led_state;
endmodule