data/full_repos/permissive/211316121/lab6_3/digitalClock_top.v
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1: b"%Error: data/full_repos/permissive/211316121/lab6_3/digitalClock_top.v:39: Cannot find file containing module: 'clkdiv'\n    clkdiv clk0(CLK100MHZ, clkcount[0], clkcount[1]);    \n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/lab6_3,data/full_repos/permissive/211316121/clkdiv\n             data/full_repos/permissive/211316121/lab6_3,data/full_repos/permissive/211316121/clkdiv.v\n             data/full_repos/permissive/211316121/lab6_3,data/full_repos/permissive/211316121/clkdiv.sv\n             clkdiv\n             clkdiv.v\n             clkdiv.sv\n             obj_dir/clkdiv\n             obj_dir/clkdiv.v\n             obj_dir/clkdiv.sv\n%Error: data/full_repos/permissive/211316121/lab6_3/digitalClock_top.v:40: Cannot find file containing module: 'oneMinute'\n    oneMinute onem0(CLK100MHZ, oneMin);                 \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/211316121/lab6_3/digitalClock_top.v:45: Cannot find file containing module: 'timeCounter60'\n    timeCounter60 ctr1(oneMin, SW[13], SW[6:0], oneMin, m_bcd[3:0], m_bcd[7:4], m_out);\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/211316121/lab6_3/digitalClock_top.v:50: Cannot find file containing module: 'timeCounter24'\n    timeCounter24 ctr2(oneMin, SW[13], SW[12:7], m_out, h_bcd[3:0], h_bcd[7:4], h_out);\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/211316121/lab6_3/digitalClock_top.v:54: Cannot find file containing module: 'BCD_7Seg'\n    BCD_7Seg bcdseg0(bcd, clkcount, SEG, AN); \n    ^~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module digitalClock_top(
    input CLK100MHZ,
    input [13:0] SW,
    output CA,
    output CB,
    output CC,
    output CD,
    output CE,
    output CF,
    output CG,
    output [7:0] AN
    );
    wire [6:0] SEG;
    assign SEG = { CG, CF, CE, CD, CC, CB, CA };
    wire [1:0] clkcount;
    wire oneMin;
    clkdiv clk0(CLK100MHZ, clkcount[0], clkcount[1]);
    oneMinute onem0(CLK100MHZ, oneMin);                 
    
    wire m_out;

    wire [7:0] m_bcd; 
    timeCounter60 ctr1(oneMin, SW[13], SW[6:0], oneMin, m_bcd[3:0], m_bcd[7:4], m_out);
    
    wire h_out;

    wire [7:0] h_bcd; 
    timeCounter24 ctr2(oneMin, SW[13], SW[12:7], m_out, h_bcd[3:0], h_bcd[7:4], h_out);
    
    wire [15:0] bcd;
    assign bcd = {h_bcd[7:0], m_bcd[7:0]};
    BCD_7Seg bcdseg0(bcd, clkcount, SEG, AN); 
endmodule
module digitalClock_top(
    input CLK100MHZ,
    input [13:0] SW,
    output CA,
    output CB,
    output CC,
    output CD,
    output CE,
    output CF,
    output CG,
    output [7:0] AN
    );

    wire [6:0] SEG;
    assign SEG = { CG, CF, CE, CD, CC, CB, CA };
    wire [1:0] clkcount;
    wire oneMin;
    clkdiv clk0(CLK100MHZ, clkcount[0], clkcount[1]);
    oneMinute onem0(CLK100MHZ, oneMin);                 
    
    wire m_out;

    wire [7:0] m_bcd; 
    timeCounter60 ctr1(oneMin, SW[13], SW[6:0], oneMin, m_bcd[3:0], m_bcd[7:4], m_out);
    
    wire h_out;

    wire [7:0] h_bcd; 
    timeCounter24 ctr2(oneMin, SW[13], SW[12:7], m_out, h_bcd[3:0], h_bcd[7:4], h_out);
    
    wire [15:0] bcd;
    assign bcd = {h_bcd[7:0], m_bcd[7:0]};
    BCD_7Seg bcdseg0(bcd, clkcount, SEG, AN); 
endmodule