data/full_repos/permissive/167489907/Examples/4-to-1-Mux/Mux_4to1_tb.v
 line:15: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4-to-1-Mux/Mux_4to1_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n #10 i=4\'b1010;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4-to-1-Mux/Mux_4to1_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n #10 s=2\'b00;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4-to-1-Mux/Mux_4to1_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n #10 s=2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4-to-1-Mux/Mux_4to1_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n #10 s=2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4-to-1-Mux/Mux_4to1_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10 s=2\'b11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4-to-1-Mux/Mux_4to1_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #10 $stop;\n ^\n%Error: data/full_repos/permissive/167489907/Examples/4-to-1-Mux/Mux_4to1_tb.v:7: Cannot find file containing module: \'Mux_4to1\'\nMux_4to1 uut (.i(i), .s(s), .o(o));\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167489907/Examples/4-to-1-Mux,data/full_repos/permissive/167489907/Mux_4to1\n             data/full_repos/permissive/167489907/Examples/4-to-1-Mux,data/full_repos/permissive/167489907/Mux_4to1.v\n             data/full_repos/permissive/167489907/Examples/4-to-1-Mux,data/full_repos/permissive/167489907/Mux_4to1.sv\n             Mux_4to1\n             Mux_4to1.v\n             Mux_4to1.sv\n             obj_dir/Mux_4to1\n             obj_dir/Mux_4to1.v\n             obj_dir/Mux_4to1.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Mux_4to1_tb;

reg[3:0] i;
reg[1:0] s;
wire o;

Mux_4to1 uut (.i(i), .s(s), .o(o));
initial
begin
	#10 i=4'b1010;
	#10 s=2'b00;
	#10 s=2'b01;
	#10 s=2'b10;
	#10 s=2'b11;
	#10 $stop;
end
endmodule
module Mux_4to1_tb;


reg[3:0] i;
reg[1:0] s;
wire o;

Mux_4to1 uut (.i(i), .s(s), .o(o));
initial
begin
	#10 i=4'b1010;
	#10 s=2'b00;
	#10 s=2'b01;
	#10 s=2'b10;
	#10 s=2'b11;
	#10 $stop;
end
endmodule