data/full_repos/permissive/100975158/MIPS32_Full/Processor/SimpleAdder.v
data/verilator_xmls/262503ec-726d-4acc-a547-4a42eb461ea2.xml
module SimpleAdder (
    input   [31:0] A,
    input   [31:0] B,
    output  [31:0] C
);

    assign C = (A + B);
endmodule
module SimpleAdder (
    input   [31:0] A,
    input   [31:0] B,
    output  [31:0] C
);


    assign C = (A + B);
endmodule