data/full_repos/permissive/200314387/verilog/pc/test.v
 line:437: before: "if"
1: b'%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:6: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/pc,data/full_repos/permissive/200314387/../lib/assertion.v\n             data/full_repos/permissive/200314387/verilog/pc,data/full_repos/permissive/200314387/../lib/assertion.v.v\n             data/full_repos/permissive/200314387/verilog/pc,data/full_repos/permissive/200314387/../lib/assertion.v.sv\n             ../lib/assertion.v\n             ../lib/assertion.v.v\n             ../lib/assertion.v.sv\n             obj_dir/../lib/assertion.v\n             obj_dir/../lib/assertion.v.v\n             obj_dir/../lib/assertion.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:7: Cannot find include file: pc.v\n`include "pc.v" \n         ^~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:46: Define or directive not defined: \'`Equals\'\n  `Equals(PCLO, 8\'bxxxxxxxx);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:46: syntax error, unexpected \',\'\n  `Equals(PCLO, 8\'bxxxxxxxx);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:47: Define or directive not defined: \'`Equals\'\n  `Equals(PCHI, 8\'bxxxxxxxx);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:47: syntax error, unexpected \',\'\n  `Equals(PCHI, 8\'bxxxxxxxx);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:55: Define or directive not defined: \'`Equals\'\n  `Equals(PCLO, 8\'bxxxxxxxx);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:55: syntax error, unexpected \',\'\n  `Equals(PCLO, 8\'bxxxxxxxx);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:56: Define or directive not defined: \'`Equals\'\n  `Equals(PCHI, 8\'bxxxxxxxx);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:56: syntax error, unexpected \',\'\n  `Equals(PCHI, 8\'bxxxxxxxx);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:62: Define or directive not defined: \'`Equals\'\n  `Equals(PCLO, 8\'b0);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:62: syntax error, unexpected \',\'\n  `Equals(PCLO, 8\'b0);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:63: Define or directive not defined: \'`Equals\'\n  `Equals(PCHI, 8\'b0);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:63: syntax error, unexpected \',\'\n  `Equals(PCHI, 8\'b0);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:67: Define or directive not defined: \'`Equals\'\n  `Equals(PCLO, 8\'b0);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:67: syntax error, unexpected \',\'\n  `Equals(PCLO, 8\'b0);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:68: Define or directive not defined: \'`Equals\'\n  `Equals(PCHI, 8\'b0);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:68: syntax error, unexpected \',\'\n  `Equals(PCHI, 8\'b0);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:74: Define or directive not defined: \'`Equals\'\n  `Equals(PCLO, 8\'b0);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:74: syntax error, unexpected \',\'\n  `Equals(PCLO, 8\'b0);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:75: Define or directive not defined: \'`Equals\'\n  `Equals(PCHI, 8\'b0);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:75: syntax error, unexpected \',\'\n  `Equals(PCHI, 8\'b0);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:81: Define or directive not defined: \'`Equals\'\n  `Equals(PCLO, 8\'b0);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:81: syntax error, unexpected \',\'\n  `Equals(PCLO, 8\'b0);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:82: Define or directive not defined: \'`Equals\'\n  `Equals(PCHI, 8\'b0);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:82: syntax error, unexpected \',\'\n  `Equals(PCHI, 8\'b0);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:87: Define or directive not defined: \'`Equals\'\n  `Equals(PCLO, 8\'b00000001);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:87: syntax error, unexpected \',\'\n  `Equals(PCLO, 8\'b00000001);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:88: Define or directive not defined: \'`Equals\'\n  `Equals(PCHI, 8\'b00000000);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:88: syntax error, unexpected \',\'\n  `Equals(PCHI, 8\'b00000000);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:94: Define or directive not defined: \'`Equals\'\n  `Equals(PCLO, 8\'b00000010);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:94: syntax error, unexpected \',\'\n  `Equals(PCLO, 8\'b00000010);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:95: Define or directive not defined: \'`Equals\'\n  `Equals(PCHI, 8\'b00000000);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:95: syntax error, unexpected \',\'\n  `Equals(PCHI, 8\'b00000000);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:106: Define or directive not defined: \'`Equals\'\n  `Equals(PCLO, 8\'b00000010);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:106: syntax error, unexpected \',\'\n  `Equals(PCLO, 8\'b00000010);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:107: Define or directive not defined: \'`Equals\'\n  `Equals(PCHI, 8\'b00000000);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:107: syntax error, unexpected \',\'\n  `Equals(PCHI, 8\'b00000000);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:111: Define or directive not defined: \'`Equals\'\n  `Equals(PCLO, 8\'b00000011);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:111: syntax error, unexpected \',\'\n  `Equals(PCLO, 8\'b00000011);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:112: Define or directive not defined: \'`Equals\'\n  `Equals(PCHI, 8\'b00000000);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:112: syntax error, unexpected \',\'\n  `Equals(PCHI, 8\'b00000000);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:117: Define or directive not defined: \'`Equals\'\n  `Equals(PCLO, 8\'b00000011);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:117: syntax error, unexpected \',\'\n  `Equals(PCLO, 8\'b00000011);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:118: Define or directive not defined: \'`Equals\'\n  `Equals(PCHI, 8\'b00000000);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:118: syntax error, unexpected \',\'\n  `Equals(PCHI, 8\'b00000000);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:123: Define or directive not defined: \'`Equals\'\n  `Equals(PCLO, 8\'b00000100);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:123: syntax error, unexpected \',\'\n  `Equals(PCLO, 8\'b00000100);\n              ^\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:124: Define or directive not defined: \'`Equals\'\n  `Equals(PCHI, 8\'b00000000);\n  ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/pc/test.v:124: syntax error, unexpected \',\'\n  `Equals(PCHI, 8\'b00000000);\n              ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module test();
logic clk;
logic _MR;
logic _pclo_in;
logic _pc_in;
logic _pchitmp_in;
logic [7:0] D;
wire [7:0] PCHI, PCLO;

wire #8 _clk = ! clk;

localparam T=25;
localparam SETTLE=50;

pc PC ( .clk, ._MR, ._pc_in, ._pclo_in, ._pchitmp_in, .D, .PCLO, .PCHI);

task clkpulse;
  begin
  #T
  clk= 1'b0;
  #T
  clk= 1'b1;
  end
endtask

logic LOG=1;

  always @(*)
    if (LOG) $display("%8d TEST : clk=%1b    PC=%8b,%8b _pc_in=%1b _pclo_in=%1b _pchitmp_in=%1b ", $time, clk, PCHI, PCLO, _pc_in, _pclo_in, _pchitmp_in);

int c;

initial begin
  
  $display("initial undefined");
  `Equals(PCLO, 8'bxxxxxxxx);
  `Equals(PCHI, 8'bxxxxxxxx);
  _pc_in = 1'b1;
  _pchitmp_in = 1'b1;
  _pclo_in = 1'b1;
  _MR = 1'b0;
  D = 8'b0;
  clk = 1'b0;
  #T
  `Equals(PCLO, 8'bxxxxxxxx);
  `Equals(PCHI, 8'bxxxxxxxx);

  
  $display("resetting");
  clk = 1'b1;
  #T
  `Equals(PCLO, 8'b0);
  `Equals(PCHI, 8'b0);

  clk= 1'b1;
  #T
  `Equals(PCLO, 8'b0);
  `Equals(PCHI, 8'b0);


  $display("still reset because _ME is low");
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b0);
  `Equals(PCHI, 8'b0);


  $display("releasing _MR but no CLK yet so still 0x00");
  _MR = 1'b1;
  #SETTLE
  `Equals(PCLO, 8'b0);
  `Equals(PCHI, 8'b0);

  $display("clk incr to 0x01");
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b00000001);
  `Equals(PCHI, 8'b00000000);


  $display("clk incr to 0x02");
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b00000010);
  `Equals(PCHI, 8'b00000000);



  D = 8'b11111111;
  $display("load PCHITmp with %8b - PC should advance on +ve edge", D);
  _pc_in = 1'b1;
  _pchitmp_in = 1'b0;
  _pclo_in = 1'b1;
  clk= 1'b0;
  #SETTLE
  `Equals(PCLO, 8'b00000010);
  `Equals(PCHI, 8'b00000000);

  clk= 1'b1;
  #SETTLE
  `Equals(PCLO, 8'b00000011);
  `Equals(PCHI, 8'b00000000);

  $display("PC should NOT advance on -ve edge");
  clk= 1'b0;
  #SETTLE
  `Equals(PCLO, 8'b00000011);
  `Equals(PCHI, 8'b00000000);

  $display("PC should advance on +ve edge");
  clk= 1'b1;
  #SETTLE
  `Equals(PCLO, 8'b00000100);
  `Equals(PCHI, 8'b00000000);

  $display("PC should NOT advance on -ve edge");
  clk= 1'b0;
  #SETTLE
  `Equals(PCLO, 8'b00000100);
  `Equals(PCHI, 8'b00000000);




  D = 8'b10101010;
  $display("load PCLO with %8b - PCHI should load with PCHITMP and PC not advance", D);
  _pc_in = 1'b0;
  _pchitmp_in = 1'b1;
  _pclo_in = 1'b1;
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b10101010);
  `Equals(PCHI, 8'b11111111);


  D = 8'b11111110;
  $display("load PCLO with %8b - PCLO should load and PC not advance", D);
  _pc_in = 1'b1;
  _pchitmp_in = 1'b1;
  _pclo_in = 1'b0;
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b11111110);
  `Equals(PCHI, 8'b11111111);


  $display("count - Should count to ff:ff");
  _pc_in = 1'b1;
  _pchitmp_in = 1'b1;
  _pclo_in = 1'b1;
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b11111111);
  `Equals(PCHI, 8'b11111111);

  $display("count - Should count to 00:00");
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b00000000);
  `Equals(PCHI, 8'b00000000);

  $display("count - full range");
  _MR = 1'b0;
  clkpulse();
  #SETTLE
  `Equals({PCHI,PCLO}, 8'b0);

  _pc_in = 1'b1;
  _pchitmp_in = 1'b1;
  _pclo_in = 1'b1;
  _MR = 1'b1;
  LOG=0;
  #SETTLE

  `Equals({PCHI,PCLO}, 16'(c));

  for (c=0; c<3 * (2**16); c++) begin
      #SETTLE
      `Equals({PCHI,PCLO}, 16'(c));
      clkpulse();
  end

  $display("count - full range - completed at %d", c);


end

endmodule
module test();

logic clk;
logic _MR;
logic _pclo_in;
logic _pc_in;
logic _pchitmp_in;
logic [7:0] D;
wire [7:0] PCHI, PCLO;

wire #8 _clk = ! clk;

localparam T=25;
localparam SETTLE=50;

pc PC ( .clk, ._MR, ._pc_in, ._pclo_in, ._pchitmp_in, .D, .PCLO, .PCHI);

task clkpulse;
  begin
  #T
  clk= 1'b0;
  #T
  clk= 1'b1;
  end
endtask

logic LOG=1;

  always @(*)
    if (LOG) $display("%8d TEST : clk=%1b    PC=%8b,%8b _pc_in=%1b _pclo_in=%1b _pchitmp_in=%1b ", $time, clk, PCHI, PCLO, _pc_in, _pclo_in, _pchitmp_in);

int c;

initial begin
  
  $display("initial undefined");
  `Equals(PCLO, 8'bxxxxxxxx);
  `Equals(PCHI, 8'bxxxxxxxx);
  _pc_in = 1'b1;
  _pchitmp_in = 1'b1;
  _pclo_in = 1'b1;
  _MR = 1'b0;
  D = 8'b0;
  clk = 1'b0;
  #T
  `Equals(PCLO, 8'bxxxxxxxx);
  `Equals(PCHI, 8'bxxxxxxxx);

  
  $display("resetting");
  clk = 1'b1;
  #T
  `Equals(PCLO, 8'b0);
  `Equals(PCHI, 8'b0);

  clk= 1'b1;
  #T
  `Equals(PCLO, 8'b0);
  `Equals(PCHI, 8'b0);


  $display("still reset because _ME is low");
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b0);
  `Equals(PCHI, 8'b0);


  $display("releasing _MR but no CLK yet so still 0x00");
  _MR = 1'b1;
  #SETTLE
  `Equals(PCLO, 8'b0);
  `Equals(PCHI, 8'b0);

  $display("clk incr to 0x01");
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b00000001);
  `Equals(PCHI, 8'b00000000);


  $display("clk incr to 0x02");
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b00000010);
  `Equals(PCHI, 8'b00000000);



  D = 8'b11111111;
  $display("load PCHITmp with %8b - PC should advance on +ve edge", D);
  _pc_in = 1'b1;
  _pchitmp_in = 1'b0;
  _pclo_in = 1'b1;
  clk= 1'b0;
  #SETTLE
  `Equals(PCLO, 8'b00000010);
  `Equals(PCHI, 8'b00000000);

  clk= 1'b1;
  #SETTLE
  `Equals(PCLO, 8'b00000011);
  `Equals(PCHI, 8'b00000000);

  $display("PC should NOT advance on -ve edge");
  clk= 1'b0;
  #SETTLE
  `Equals(PCLO, 8'b00000011);
  `Equals(PCHI, 8'b00000000);

  $display("PC should advance on +ve edge");
  clk= 1'b1;
  #SETTLE
  `Equals(PCLO, 8'b00000100);
  `Equals(PCHI, 8'b00000000);

  $display("PC should NOT advance on -ve edge");
  clk= 1'b0;
  #SETTLE
  `Equals(PCLO, 8'b00000100);
  `Equals(PCHI, 8'b00000000);




  D = 8'b10101010;
  $display("load PCLO with %8b - PCHI should load with PCHITMP and PC not advance", D);
  _pc_in = 1'b0;
  _pchitmp_in = 1'b1;
  _pclo_in = 1'b1;
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b10101010);
  `Equals(PCHI, 8'b11111111);


  D = 8'b11111110;
  $display("load PCLO with %8b - PCLO should load and PC not advance", D);
  _pc_in = 1'b1;
  _pchitmp_in = 1'b1;
  _pclo_in = 1'b0;
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b11111110);
  `Equals(PCHI, 8'b11111111);


  $display("count - Should count to ff:ff");
  _pc_in = 1'b1;
  _pchitmp_in = 1'b1;
  _pclo_in = 1'b1;
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b11111111);
  `Equals(PCHI, 8'b11111111);

  $display("count - Should count to 00:00");
  clkpulse();
  #SETTLE
  `Equals(PCLO, 8'b00000000);
  `Equals(PCHI, 8'b00000000);

  $display("count - full range");
  _MR = 1'b0;
  clkpulse();
  #SETTLE
  `Equals({PCHI,PCLO}, 8'b0);

  _pc_in = 1'b1;
  _pchitmp_in = 1'b1;
  _pclo_in = 1'b1;
  _MR = 1'b1;
  LOG=0;
  #SETTLE

  `Equals({PCHI,PCLO}, 16'(c));

  for (c=0; c<3 * (2**16); c++) begin
      #SETTLE
      `Equals({PCHI,PCLO}, 16'(c));
      clkpulse();
  end

  $display("count - full range - completed at %d", c);


end

endmodule