data/full_repos/permissive/199399537/sdfifo_ctrl.v
1: b"%Error: data/full_repos/permissive/199399537/sdfifo_ctrl.v:86: Cannot find file containing module: 'wrfifo'\nwrfifo   uut_wrfifo(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/wrfifo\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/wrfifo.v\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/wrfifo.sv\n             wrfifo\n             wrfifo.v\n             wrfifo.sv\n             obj_dir/wrfifo\n             obj_dir/wrfifo.v\n             obj_dir/wrfifo.sv\n%Error: data/full_repos/permissive/199399537/sdfifo_ctrl.v:97: Cannot find file containing module: 'rdfifo'\nrdfifo   uut_rdfifo(\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module sdfifo_ctrl(
				clk_20m,
				clk_100m,
				
				wrf_din,
				wrf_wrreq,
				sdram_wr_ack,
				sys_data_in,
				sdram_wr_req,
				
				sys_data_out,
				rdf_rdreq,
				sdram_rd_ack,
				rdf_dout,
				sdram_rd_req,
				
				syswr_done,
				tx_start	,
				
				wrf_use,
				rdf_use
			);

input clk_20m;
input clk_100m;


input[15:0] 	wrf_din;
input 				wrf_wrreq;
input 				sdram_wr_ack;
output[15:0] sys_data_in;
output 			sdram_wr_req;



input[15:0] 	sys_data_out;
input 				rdf_rdreq;
input 				sdram_rd_ack;
output[15:0] rdf_dout;
output 			sdram_rd_req;


input syswr_done;
output tx_start;

output[8:0] wrf_use;
output[8:0] rdf_use; 



wire[8:0] wrf_use;
wire[8:0] rdf_use;




assign sdram_wr_req = ((wrf_use >= 9'd8) & ~syswr_done);



assign sdram_rd_req = ((rdf_use <= 9'd256) & syswr_done) && (!read_stop);


assign tx_start = ((rdf_use != 9'd0) & syswr_done);



reg		[3:0]read_counter	=4'd0;
reg		read_stop					=1'd0;
wire	__wire_read_stop	=read_stop;

always @ (posedge sdram_rd_ack)
begin
		if(read_counter==4'd3)
				read_stop	<=1'd1;
		else if(read_stop==1'd0)
				read_counter	<=	read_counter+1;
end


	


wrfifo			uut_wrfifo(
					.data(wrf_din),
					.rdclk(clk_100m),
					.rdreq(sdram_wr_ack),				
					.wrclk(clk_100m),
					.wrreq(wrf_wrreq),
					.q(sys_data_in),
					.wrusedw(wrf_use)
					);	


rdfifo			uut_rdfifo(
					.data(sys_data_out),
					.rdclk(clk_20m),
					.rdreq(rdf_rdreq),				
					.wrclk(clk_100m),
					.wrreq(sdram_rd_ack),
					.q(rdf_dout),
					.wrusedw(rdf_use)
					);	

endmodule
module sdfifo_ctrl(
				clk_20m,
				clk_100m,
				
				wrf_din,
				wrf_wrreq,
				sdram_wr_ack,
				sys_data_in,
				sdram_wr_req,
				
				sys_data_out,
				rdf_rdreq,
				sdram_rd_ack,
				rdf_dout,
				sdram_rd_req,
				
				syswr_done,
				tx_start	,
				
				wrf_use,
				rdf_use
			);


input clk_20m;
input clk_100m;


input[15:0] 	wrf_din;
input 				wrf_wrreq;
input 				sdram_wr_ack;
output[15:0] sys_data_in;
output 			sdram_wr_req;



input[15:0] 	sys_data_out;
input 				rdf_rdreq;
input 				sdram_rd_ack;
output[15:0] rdf_dout;
output 			sdram_rd_req;


input syswr_done;
output tx_start;

output[8:0] wrf_use;
output[8:0] rdf_use; 



wire[8:0] wrf_use;
wire[8:0] rdf_use;




assign sdram_wr_req = ((wrf_use >= 9'd8) & ~syswr_done);



assign sdram_rd_req = ((rdf_use <= 9'd256) & syswr_done) && (!read_stop);


assign tx_start = ((rdf_use != 9'd0) & syswr_done);



reg		[3:0]read_counter	=4'd0;
reg		read_stop					=1'd0;
wire	__wire_read_stop	=read_stop;

always @ (posedge sdram_rd_ack)
begin
		if(read_counter==4'd3)
				read_stop	<=1'd1;
		else if(read_stop==1'd0)
				read_counter	<=	read_counter+1;
end


	


wrfifo			uut_wrfifo(
					.data(wrf_din),
					.rdclk(clk_100m),
					.rdreq(sdram_wr_ack),				
					.wrclk(clk_100m),
					.wrreq(wrf_wrreq),
					.q(sys_data_in),
					.wrusedw(wrf_use)
					);	


rdfifo			uut_rdfifo(
					.data(sys_data_out),
					.rdclk(clk_20m),
					.rdreq(rdf_rdreq),				
					.wrclk(clk_100m),
					.wrreq(sdram_rd_ack),
					.q(rdf_dout),
					.wrusedw(rdf_use)
					);	

endmodule