data/full_repos/permissive/138473269/rtl/mano_reg.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/138473269/rtl/mano_reg.v:8: Cannot find include file: rtl/basic_params.v\n`include "rtl/basic_params.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/138473269/rtl,data/full_repos/permissive/138473269/rtl/basic_params.v\n             data/full_repos/permissive/138473269/rtl,data/full_repos/permissive/138473269/rtl/basic_params.v.v\n             data/full_repos/permissive/138473269/rtl,data/full_repos/permissive/138473269/rtl/basic_params.v.sv\n             rtl/basic_params.v\n             rtl/basic_params.v.v\n             rtl/basic_params.v.sv\n             obj_dir/rtl/basic_params.v\n             obj_dir/rtl/basic_params.v.v\n             obj_dir/rtl/basic_params.v.sv\n%Error: Exiting due to 1 error(s)\n'
module register #(parameter width = 8)(rst, clk, ld, inc, d, q);
	input rst, clk, ld, inc;
	input [width-1:0] d; 
	output [width-1:0]q;
	
	reg [width-1:0] temp;
	
	always @ ( posedge clk)
		if (rst) 
			temp = 0;
		else if (inc)
    		temp = temp + 1;
		else if (ld)
    		temp = d;
	
	assign q  = temp;
endmodule
module register #(parameter width = 8)(rst, clk, ld, inc, d, q);

	input rst, clk, ld, inc;
	input [width-1:0] d; 
	output [width-1:0]q;
	
	reg [width-1:0] temp;
	
	always @ ( posedge clk)
		if (rst) 
			temp = 0;
		else if (inc)
    		temp = temp + 1;
		else if (ld)
    		temp = d;
	
	assign q  = temp;
endmodule