data/full_repos/permissive/212008255/codes/1_bit_full_adder/bit_1_full_adder_tb.v
 line:18: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/212008255/codes/1_bit_full_adder/bit_1_full_adder_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n initial #stop_time $finish;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212008255/codes/1_bit_full_adder/bit_1_full_adder_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 a_i=~a_i;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/212008255/codes/1_bit_full_adder/bit_1_full_adder_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10 b_i=~b_i;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/212008255/codes/1_bit_full_adder/bit_1_full_adder_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #15 c_i_1=~c_i_1;\n ^\n%Error: data/full_repos/permissive/212008255/codes/1_bit_full_adder/bit_1_full_adder_tb.v:10: Cannot find file containing module: \'bit_1_full_adder\'\n bit_1_full_adder uut (\n ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212008255/codes/1_bit_full_adder,data/full_repos/permissive/212008255/bit_1_full_adder\n             data/full_repos/permissive/212008255/codes/1_bit_full_adder,data/full_repos/permissive/212008255/bit_1_full_adder.v\n             data/full_repos/permissive/212008255/codes/1_bit_full_adder,data/full_repos/permissive/212008255/bit_1_full_adder.sv\n             bit_1_full_adder\n             bit_1_full_adder.v\n             bit_1_full_adder.sv\n             obj_dir/bit_1_full_adder\n             obj_dir/bit_1_full_adder.v\n             obj_dir/bit_1_full_adder.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bit_1_full_adder_tb;
	reg a_i;
	reg b_i;
	reg c_i_1;
	wire s_i;
	wire c_i;
	parameter stop_time =2000;

	bit_1_full_adder uut (
		.a_i(a_i), 
		.b_i(b_i), 
		.c_i_1(c_i_1), 
		.s_i(s_i), 
		.c_i(c_i)
	);

	initial #stop_time $finish;
	initial begin
		a_i = 0;
		b_i = 0;
		c_i_1 = 0;
	end
	
	always begin
	#5 a_i=~a_i;
	end
	
	always begin
	#10 b_i=~b_i;
	end
	
	always begin
	#15 c_i_1=~c_i_1;
	end
	
      
endmodule
module bit_1_full_adder_tb;

	reg a_i;
	reg b_i;
	reg c_i_1;
	wire s_i;
	wire c_i;
	parameter stop_time =2000;

	bit_1_full_adder uut (
		.a_i(a_i), 
		.b_i(b_i), 
		.c_i_1(c_i_1), 
		.s_i(s_i), 
		.c_i(c_i)
	);

	initial #stop_time $finish;
	initial begin
		a_i = 0;
		b_i = 0;
		c_i_1 = 0;
	end
	
	always begin
	#5 a_i=~a_i;
	end
	
	always begin
	#10 b_i=~b_i;
	end
	
	always begin
	#15 c_i_1=~c_i_1;
	end
	
      
endmodule