data/full_repos/permissive/174155074/basic-code/combinational-logic/and-gate/and-gate-tb.v
 line:33: before: "$"
1: b'%Error: data/full_repos/permissive/174155074/basic-code/combinational-logic/and-gate/and-gate-tb.v:19: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("and-gate-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/basic-code/combinational-logic/and-gate/and-gate-tb.v:20: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, and_gate_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/basic-code/combinational-logic/and-gate/and-gate-tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10 X = 1; Y = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174155074/basic-code/combinational-logic/and-gate/and-gate-tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 X = 0; Y = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/basic-code/combinational-logic/and-gate/and-gate-tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 X = 1; Y = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/basic-code/combinational-logic/and-gate/and-gate-tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module and_gate_tb;


reg  X, Y;
wire XY;


and_gate uut(
    .x(X), .y(Y),
    .xy_1(XY_1), .xy_2(XY_2), .xy_3(XY_3), .xy_4(XY_4)
);


initial begin
    $dumpfile("and-gate-tb.vcd");
    $dumpvars(0, and_gate_tb);
end


initial begin
    $display("test start");
    X = 0; Y = 0;
    
    #10 X = 1; Y = 0;
    #10 X = 0; Y = 1;
    #10 X = 1; Y = 1;
    #10
    
    $display("test complete");
    $finish;
end

endmodule
module and_gate_tb;



reg  X, Y;
wire XY;


and_gate uut(
    .x(X), .y(Y),
    .xy_1(XY_1), .xy_2(XY_2), .xy_3(XY_3), .xy_4(XY_4)
);


initial begin
    $dumpfile("and-gate-tb.vcd");
    $dumpvars(0, and_gate_tb);
end


initial begin
    $display("test start");
    X = 0; Y = 0;
    
    #10 X = 1; Y = 0;
    #10 X = 0; Y = 1;
    #10 X = 1; Y = 1;
    #10
    
    $display("test complete");
    $finish;
end

endmodule