data/full_repos/permissive/115632823/code/Stream Multi-processor/SM.srcs/sources_1/new/FpMultiplier.v
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1: b'%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n        ... Looked in:\n             data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n             data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n             data/full_repos/permissive/115632823/code/Stream/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n             Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n             Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n             Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n             obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823\n             obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.v\n             obj_dir/Multi-processor/SM.srcs/sources_1/new,data/full_repos/permissive/115632823.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/115632823/code/Stream\n%Error: Cannot find file containing module: Multi-processor/SM.srcs/sources_1/new/FpMultiplier.v\n%Error: Exiting due to 3 error(s)\n'
module FpMultiplier(

    input wire [31:0] A,
    input wire [31:0] B,
    output reg [31:0] Result
    );

reg [1:0] overflow;



reg signA, signB, signR;
reg [7:0] expA, expB, expR;
reg [22:0] manA, manB, manR;
reg normalRight;
reg [7:0] tempExpA, tempExpB;
reg [8:0] tempExpR;
reg [23:0] tempMan;
reg [45:0] tempProduct;
reg [23:0] tempSum;
reg [1:0] intPart;


always@(A or B) begin
    signA = A[31];
    expA = A[30:23];
    manA = A[22:0];
    
    signB = B[31];
    expB = B[30:23];
    manB = B[22:0];


    tempProduct = manA * manB;
    tempSum = manA + manB;
    tempMan = tempProduct[45:23] + tempSum[22:0];
    intPart = 1 + tempMan[23] + tempSum[23];


    if(intPart[1] == 1) begin
        normalRight = 1'b1;
        manR = {intPart[0], tempMan[22:1]};
    end
    else begin
        normalRight = 1'b0;
        manR = tempMan;
    end

    tempExpR = tempExpA + tempExpB - 127 + normalRight;    
    case(tempExpR[8:7])
    2'b10: overflow = 2'b10;
    2'b01: overflow = 2'b01;
    endcase
    expR = tempExpR[7:0];


    signR = signA ^ signB;


    Result = {signR, expR, manR};
end

endmodule
module FpMultiplier(

    input wire [31:0] A,
    input wire [31:0] B,
    output reg [31:0] Result
    );


reg [1:0] overflow;



reg signA, signB, signR;
reg [7:0] expA, expB, expR;
reg [22:0] manA, manB, manR;
reg normalRight;
reg [7:0] tempExpA, tempExpB;
reg [8:0] tempExpR;
reg [23:0] tempMan;
reg [45:0] tempProduct;
reg [23:0] tempSum;
reg [1:0] intPart;


always@(A or B) begin
    signA = A[31];
    expA = A[30:23];
    manA = A[22:0];
    
    signB = B[31];
    expB = B[30:23];
    manB = B[22:0];


    tempProduct = manA * manB;
    tempSum = manA + manB;
    tempMan = tempProduct[45:23] + tempSum[22:0];
    intPart = 1 + tempMan[23] + tempSum[23];


    if(intPart[1] == 1) begin
        normalRight = 1'b1;
        manR = {intPart[0], tempMan[22:1]};
    end
    else begin
        normalRight = 1'b0;
        manR = tempMan;
    end

    tempExpR = tempExpA + tempExpB - 127 + normalRight;    
    case(tempExpR[8:7])
    2'b10: overflow = 2'b10;
    2'b01: overflow = 2'b01;
    endcase
    expR = tempExpR[7:0];


    signR = signA ^ signB;


    Result = {signR, expR, manR};
end

endmodule