data/full_repos/permissive/167274925/InstructionMemory_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167274925/InstructionMemory_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167274925/InstructionMemory_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/InstructionMemory_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167274925/InstructionMemory_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/167274925/InstructionMemory_tb.v:16: Cannot find file containing module: \'InstructionMemory\'\n InstructionMemory u0(\n ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/InstructionMemory\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/InstructionMemory.v\n             data/full_repos/permissive/167274925,data/full_repos/permissive/167274925/InstructionMemory.sv\n             InstructionMemory\n             InstructionMemory.v\n             InstructionMemory.sv\n             obj_dir/InstructionMemory\n             obj_dir/InstructionMemory.v\n             obj_dir/InstructionMemory.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module InstructionMemory_tb(); 
     reg[31:0] Address;
    wire [31:0] Instruction;

   

	InstructionMemory u0(
		.Address(Address),
        .Instruction(Instruction)
	);

	initial begin
	
    Address<=32'd0;
    #10;
    Address<=32'd4;
    #10;
    Address<=32'd8;
    #10;
    Address<=32'd12;
    #100;
	
	end

endmodule
module InstructionMemory_tb();
 
     reg[31:0] Address;
    wire [31:0] Instruction;

   

	InstructionMemory u0(
		.Address(Address),
        .Instruction(Instruction)
	);

	initial begin
	
    Address<=32'd0;
    #10;
    Address<=32'd4;
    #10;
    Address<=32'd8;
    #10;
    Address<=32'd12;
    #100;
	
	end

endmodule