data/full_repos/permissive/179227721/mid/calc_tb.v
 line:24: before: "+"
1: b'%Error: data/full_repos/permissive/179227721/mid/calc_tb.v:21: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("calc_wave.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/179227721/mid/calc_tb.v:22: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, as);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/179227721/mid/calc_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module calc_tb;
   wire [7:0] out;
   wire       cout;
   wire [7:0] a;
   wire [7:0] b;
   wire       cin;
   wire       operation;
   reg [17:0]  siminput;

   integer    i;

   assign {a, b, cin, operation} = siminput;

   top as(.out(out),
                    .flowIndicator(cout),
                    .num1(a),
                    .num2(b),
                    .sel(operation));

   initial begin
      $dumpfile("calc_wave.vcd");
      $dumpvars(0, as);

      for(i = 0; i < 1024; i++)
        begin
           siminput <= i;
           #500;
        end
   end
endmodule
module calc_tb;

   wire [7:0] out;
   wire       cout;
   wire [7:0] a;
   wire [7:0] b;
   wire       cin;
   wire       operation;
   reg [17:0]  siminput;

   integer    i;

   assign {a, b, cin, operation} = siminput;

   top as(.out(out),
                    .flowIndicator(cout),
                    .num1(a),
                    .num2(b),
                    .sel(operation));

   initial begin
      $dumpfile("calc_wave.vcd");
      $dumpvars(0, as);

      for(i = 0; i < 1024; i++)
        begin
           siminput <= i;
           #500;
        end
   end
endmodule