data/full_repos/permissive/129527056/cores/btiger/hdl/jtbtiger_mcu.v
1: b"%Error: data/full_repos/permissive/129527056/cores/btiger/hdl/jtbtiger_mcu.v:44: Cannot find file containing module: 'jtframe_frac_cen'\njtframe_frac_cen u_cen(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129527056/cores/btiger/hdl,data/full_repos/permissive/129527056/jtframe_frac_cen\n             data/full_repos/permissive/129527056/cores/btiger/hdl,data/full_repos/permissive/129527056/jtframe_frac_cen.v\n             data/full_repos/permissive/129527056/cores/btiger/hdl,data/full_repos/permissive/129527056/jtframe_frac_cen.sv\n             jtframe_frac_cen\n             jtframe_frac_cen.v\n             jtframe_frac_cen.sv\n             obj_dir/jtframe_frac_cen\n             obj_dir/jtframe_frac_cen.v\n             obj_dir/jtframe_frac_cen.sv\n%Error: data/full_repos/permissive/129527056/cores/btiger/hdl/jtbtiger_mcu.v:66: Cannot find file containing module: 'jtframe_8751mcu'\njtframe_8751mcu u_mcu(\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module jtbtiger_mcu(
    input                rst,
    input                clk,
    input                clk_rom,
    input                LVBL,

    output       [ 7:0]  mcu_dout,
    input        [ 7:0]  mcu_din,
    input                mcu_wr,
    input                mcu_rd,

    input        [11:0]  prog_addr,
    input        [ 7:0]  prom_din,
    input                prom_we
);

wire [ 7:0] p1_o, p2_o, p3_o;

reg  mcu_int1;
reg  last_mcu_wr;
wire nc, cen;

jtframe_frac_cen u_cen(
    .clk    ( clk       ),
    .n      ( 10'd1     ),
    .m      ( 10'd24    ),
    .cen    ( {nc, cen} ),
    .cenb   (           )
);









always @(posedge clk) begin
    last_mcu_wr <= mcu_wr;
    if( mcu_wr && !last_mcu_wr ) mcu_int1 <= 1'b0;
    if( !p3_o[1] || mcu_rd ) mcu_int1 <= 1'b1;
end

jtframe_8751mcu u_mcu(
    .rst        ( rst       ),
    .clk        ( clk       ),
    .cen        ( cen       ),

    .int0n      ( 1'b1      ),
    .int1n      ( mcu_int1  ),

    .p0_i       ( mcu_din   ),
    .p0_o       ( mcu_dout  ),

    .p1_i       ( p1_i      ),
    .p1_o       ( p1_o      ),

    .p2_i       ( p2_o      ),
    .p2_o       ( p2_o      ),

    .p3_i       ( {p3_o[7:5], LVBL, p3_o[3:0] } ),
    .p3_o       ( p3_o      ),


    .x_din      (           ),
    .x_dout     (           ),
    .x_addr     (           ),
    .x_wr       (           ),


    .clk_rom    ( clk_rom   ),
    .prog_addr  ( prog_addr ),
    .prom_din   ( prom_din  ),
    .prom_we    ( prom_we   )
);

endmodule
module jtbtiger_mcu(
    input                rst,
    input                clk,
    input                clk_rom,
    input                LVBL,

    output       [ 7:0]  mcu_dout,
    input        [ 7:0]  mcu_din,
    input                mcu_wr,
    input                mcu_rd,

    input        [11:0]  prog_addr,
    input        [ 7:0]  prom_din,
    input                prom_we
);


wire [ 7:0] p1_o, p2_o, p3_o;

reg  mcu_int1;
reg  last_mcu_wr;
wire nc, cen;

jtframe_frac_cen u_cen(
    .clk    ( clk       ),
    .n      ( 10'd1     ),
    .m      ( 10'd24    ),
    .cen    ( {nc, cen} ),
    .cenb   (           )
);









always @(posedge clk) begin
    last_mcu_wr <= mcu_wr;
    if( mcu_wr && !last_mcu_wr ) mcu_int1 <= 1'b0;
    if( !p3_o[1] || mcu_rd ) mcu_int1 <= 1'b1;
end

jtframe_8751mcu u_mcu(
    .rst        ( rst       ),
    .clk        ( clk       ),
    .cen        ( cen       ),

    .int0n      ( 1'b1      ),
    .int1n      ( mcu_int1  ),

    .p0_i       ( mcu_din   ),
    .p0_o       ( mcu_dout  ),

    .p1_i       ( p1_i      ),
    .p1_o       ( p1_o      ),

    .p2_i       ( p2_o      ),
    .p2_o       ( p2_o      ),

    .p3_i       ( {p3_o[7:5], LVBL, p3_o[3:0] } ),
    .p3_o       ( p3_o      ),


    .x_din      (           ),
    .x_dout     (           ),
    .x_addr     (           ),
    .x_wr       (           ),


    .clk_rom    ( clk_rom   ),
    .prog_addr  ( prog_addr ),
    .prom_din   ( prom_din  ),
    .prom_we    ( prom_we   )
);

endmodule