data/full_repos/permissive/212394344/RegisterBankBlock_TB.v
 line:129: before: "forever"
1: b'%Warning-STMTDLY: data/full_repos/permissive/212394344/RegisterBankBlock_TB.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212394344/RegisterBankBlock_TB.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/RegisterBankBlock_TB.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/RegisterBankBlock_TB.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/RegisterBankBlock_TB.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/RegisterBankBlock_TB.v:131: Unsupported: Ignoring delay on this delayed statement.\n   #500;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/212394344/RegisterBankBlock_TB.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #500\n  ^\n%Error: data/full_repos/permissive/212394344/RegisterBankBlock_TB.v:44: Cannot find file containing module: \'RegisterBankBlock\'\n RegisterBankBlock uut (\n ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/RegisterBankBlock\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/RegisterBankBlock.v\n             data/full_repos/permissive/212394344,data/full_repos/permissive/212394344/RegisterBankBlock.sv\n             RegisterBankBlock\n             RegisterBankBlock.v\n             RegisterBankBlock.sv\n             obj_dir/RegisterBankBlock\n             obj_dir/RegisterBankBlock.v\n             obj_dir/RegisterBankBlock.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegisterBankBlock_TB;


	reg [23:0] ins;
	reg [7:0] ans_ex;
	reg [7:0] ans_dm;
	reg [7:0] ans_wb;
	reg [7:0] imm;
	reg [4:0] RW_dm;
	reg [1:0] mux_sel_A;
	reg [1:0] mux_sel_B;
	reg imm_sel;
	reg clk;


	wire [7:0] A;
	wire [7:0] B;


	RegisterBankBlock uut (
		.A(A), 
		.B(B), 
		.ins(ins), 
		.ans_ex(ans_ex), 
		.ans_dm(ans_dm), 
		.ans_wb(ans_wb), 
		.imm(imm), 
		.RW_dm(RW_dm), 
		.mux_sel_A(mux_sel_A), 
		.mux_sel_B(mux_sel_B), 
		.imm_sel(imm_sel), 
		.clk(clk)
	);

	initial begin
		
		ins = 24'h014C50;
		ans_ex = 8'hC0;
		ans_dm = 8'hD0;
		ans_wb = 8'hE0;
		imm = 8'hFF;
		RW_dm = 5'b00111;
		mux_sel_A = 2'b00;
		mux_sel_B = 2'b00;
		imm_sel = 1;
		#500;
		
		ins = 24'h014C50;
		ans_ex = 8'hC0;
		ans_dm = 8'hD0;
		ans_wb = 8'hE0;
		imm = 8'hFF;
		RW_dm = 5'b00111;
		mux_sel_A = 2'b00;
		mux_sel_B = 2'b00;
		imm_sel = 1;
		#500;
		
		
		ins = 24'h014E50;
		ans_ex = 8'hC0;
		ans_dm = 8'hD0;
		ans_wb = 8'hE0;
		imm = 8'hFF;
		RW_dm = 5'b00111;
		mux_sel_A = 2'b00;
		mux_sel_B = 2'b01;
		imm_sel = 0;
		#500;
		
		
		ins = 24'h014E50;
		ans_ex = 8'hC0;
		ans_dm = 8'hD0;
		ans_wb = 8'hE0;
		imm = 8'hFF;
		RW_dm = 5'b00111;
		mux_sel_A = 2'b00;
		mux_sel_B = 2'b01;
		imm_sel = 0;
		#500;
		
		ins = 24'h014E50;
		ans_ex = 8'hC0;
		ans_dm = 8'hD0;
		ans_wb = 8'hE0;
		imm = 8'hFF;
		RW_dm = 5'b00111;
		mux_sel_A = 2'b11;
		mux_sel_B = 2'b10;
		imm_sel = 0;
		#500;
		
		
		
		
        
		

	end
	
	initial begin 
		clk=0;
		#500
		forever begin
			clk=~clk;
			#500;
		end
	end
      
endmodule
module RegisterBankBlock_TB;



	reg [23:0] ins;
	reg [7:0] ans_ex;
	reg [7:0] ans_dm;
	reg [7:0] ans_wb;
	reg [7:0] imm;
	reg [4:0] RW_dm;
	reg [1:0] mux_sel_A;
	reg [1:0] mux_sel_B;
	reg imm_sel;
	reg clk;


	wire [7:0] A;
	wire [7:0] B;


	RegisterBankBlock uut (
		.A(A), 
		.B(B), 
		.ins(ins), 
		.ans_ex(ans_ex), 
		.ans_dm(ans_dm), 
		.ans_wb(ans_wb), 
		.imm(imm), 
		.RW_dm(RW_dm), 
		.mux_sel_A(mux_sel_A), 
		.mux_sel_B(mux_sel_B), 
		.imm_sel(imm_sel), 
		.clk(clk)
	);

	initial begin
		
		ins = 24'h014C50;
		ans_ex = 8'hC0;
		ans_dm = 8'hD0;
		ans_wb = 8'hE0;
		imm = 8'hFF;
		RW_dm = 5'b00111;
		mux_sel_A = 2'b00;
		mux_sel_B = 2'b00;
		imm_sel = 1;
		#500;
		
		ins = 24'h014C50;
		ans_ex = 8'hC0;
		ans_dm = 8'hD0;
		ans_wb = 8'hE0;
		imm = 8'hFF;
		RW_dm = 5'b00111;
		mux_sel_A = 2'b00;
		mux_sel_B = 2'b00;
		imm_sel = 1;
		#500;
		
		
		ins = 24'h014E50;
		ans_ex = 8'hC0;
		ans_dm = 8'hD0;
		ans_wb = 8'hE0;
		imm = 8'hFF;
		RW_dm = 5'b00111;
		mux_sel_A = 2'b00;
		mux_sel_B = 2'b01;
		imm_sel = 0;
		#500;
		
		
		ins = 24'h014E50;
		ans_ex = 8'hC0;
		ans_dm = 8'hD0;
		ans_wb = 8'hE0;
		imm = 8'hFF;
		RW_dm = 5'b00111;
		mux_sel_A = 2'b00;
		mux_sel_B = 2'b01;
		imm_sel = 0;
		#500;
		
		ins = 24'h014E50;
		ans_ex = 8'hC0;
		ans_dm = 8'hD0;
		ans_wb = 8'hE0;
		imm = 8'hFF;
		RW_dm = 5'b00111;
		mux_sel_A = 2'b11;
		mux_sel_B = 2'b10;
		imm_sel = 0;
		#500;
		
		
		
		
        
		

	end
	
	initial begin 
		clk=0;
		#500
		forever begin
			clk=~clk;
			#500;
		end
	end
      
endmodule