data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Vectors/vector4.v
data/verilator_xmls/35b5d18b-c893-401b-826c-84fd4c9f29ab.xml
module top_module (
    input [7:0] in,
    output [31:0] out );


    assign out[31:0] = {{24{in[7]}},in[7:0]};
endmodule
module top_module (
    input [7:0] in,
    output [31:0] out );



    assign out[31:0] = {{24{in[7]}},in[7:0]};
endmodule