data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/counter.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/87f7a83e-6772-41d0-af0c-0bb325951ea9.xml
module counter (
		clock_i,
		reset_i,
		start_i,
		done_o
	);
	
	parameter	COUNT	= 200;
	parameter	BITS	= 8;
	
	input	clock_i;
	input	reset_i;
	input	start_i;
	
	output	done_o;
	
	reg	[BITS-1:0]	counter	= COUNT - 1;
	reg	started	= 0;
	
	
	always @(posedge clock_i)
	begin
		if (reset_i)
		begin
			started	<= 0;
			counter	<= COUNT - 1;
		end
		else
		begin
			if (start_i)
			begin
				counter	<= COUNT - 1;
				started	<= 1;
			end
			else if (counter == 0)
				started	<= 0;
			else if (started)
				counter	<= counter - 1;
		end
	end
	
	assign	done_o	= reset_i ? 0 : (counter == 0);
	
endmodule
module counter (
		clock_i,
		reset_i,
		start_i,
		done_o
	);

	
	parameter	COUNT	= 200;
	parameter	BITS	= 8;
	
	input	clock_i;
	input	reset_i;
	input	start_i;
	
	output	done_o;
	
	reg	[BITS-1:0]	counter	= COUNT - 1;
	reg	started	= 0;
	
	
	always @(posedge clock_i)
	begin
		if (reset_i)
		begin
			started	<= 0;
			counter	<= COUNT - 1;
		end
		else
		begin
			if (start_i)
			begin
				counter	<= COUNT - 1;
				started	<= 1;
			end
			else if (counter == 0)
				started	<= 0;
			else if (started)
				counter	<= counter - 1;
		end
	end
	
	assign	done_o	= reset_i ? 0 : (counter == 0);
	
endmodule