data/full_repos/permissive/143278/ivltests/pr312.v
data/verilator_xmls/c6b3c713-41f7-4348-b4ce-29194b490b8a.xml
module main;

   reg [1:0] x;
   reg [2:0] y;

   initial begin
      x = 1;
      y = {1'b0, x << 1};

      if (y !== 3'b010) begin
	 $display("FAILED -- y (%b) != 3'b010", y);
	 $finish;
      end

      y = {1'b0, x << 2};
      if (y !== 3'b000) begin
	 $display("FAILED -- y (%b) != 3'b000", y);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg [1:0] x;
   reg [2:0] y;

   initial begin
      x = 1;
      y = {1'b0, x << 1};

      if (y !== 3'b010) begin
	 $display("FAILED -- y (%b) != 3'b010", y);
	 $finish;
      end

      y = {1'b0, x << 2};
      if (y !== 3'b000) begin
	 $display("FAILED -- y (%b) != 3'b000", y);
	 $finish;
      end

      $display("PASSED");
   end

endmodule