data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v
 line:40: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n forever #(CLK_CYCLE/2) clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_CYCLE*75) arstn = 1\'b1;\n ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:39: syntax error, unexpected \'@\'\n @(posedge arstn)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE) i2c_start = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:48: syntax error, unexpected \'@\'\n @(posedge i2c_start)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE) i2c_start = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:56: syntax error, unexpected \'@\'\n @(posedge i2c_start)\n ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:65: syntax error, unexpected \'@\'\n @(posedge i2c_start)\n ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:73: syntax error, unexpected \'@\'\n @(posedge i2c_start)\n ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:82: syntax error, unexpected \'@\'\n @(posedge i2c_start)\n ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:97: syntax error, unexpected \'@\'\n @(posedge i2c_start)\n ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:105: syntax error, unexpected \'@\'\n @(posedge i2c_start)\n ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:112: syntax error, unexpected \'@\'\n @(negedge i2c_start)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in_en = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:129: syntax error, unexpected \'@\'\n @(negedge i2c_start)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in_en = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:146: syntax error, unexpected \'@\'\n @(negedge i2c_start)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in_en = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:162: syntax error, unexpected \'@\'\n @(negedge i2c_start);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV) sda_in_en = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:180: syntax error, unexpected \'@\'\n @(negedge i2c_start)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV*8)  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE*DIV)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_CYCLE*DIV*8)  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_CYCLE*DIV)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_CYCLE*DIV*9)  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_CYCLE*DIV)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_CYCLE*DIV*8)  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:216: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_CYCLE*DIV)\n ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:224: syntax error, unexpected \'@\'\n @(negedge i2c_start)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_CYCLE*DIV*(8+1+1+8+1))  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:247: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_CYCLE*DIV*9)  \n ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:257: syntax error, unexpected \'@\'\n @(negedge i2c_done)\n ^\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:263: Unsupported: fork statements\nfork\n^~~~\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:272: Unsupported: fork statements\nfork\n^~~~\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:282: Unsupported: fork statements\nfork\n^~~~\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:292: Unsupported: fork statements\nfork\n^~~~\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:301: Unsupported: fork statements\nfork\n^~~~\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:311: Unsupported: fork statements\nfork\n^~~~\n%Error: data/full_repos/permissive/206783267/I2C/TB/i2c_master_tb.v:321: Unsupported: fork statements\nfork\n^~~~\n%Error: Exiting due to 22 error(s), 47 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module i2c_master_tb();

parameter	CLK_FREQ = 50_000_000,
			I2C_FREQ = 500_000,
			CLK_CYCLE = 20,
			DIV = CLK_FREQ / I2C_FREQ;

reg	clk, arstn;
reg	i2c_start;
reg	[7-1:0]	addr;
reg	rw;
reg	[8-1:0]	data_send;
wire	i2c_done;
wire	[8-1:0]	data_recv;
wire	data_recv_done;
reg	sda_in, sda_in_en;

wire	sda, scl;

assign sda = sda_in_en ? sda_in : 1'bz;


initial begin
	clk = 0;
	forever	#(CLK_CYCLE/2)	clk = ~clk;
end


initial begin
	arstn = 1'b0;
	#(CLK_CYCLE*75)	arstn = 1'b1;
end

task gen_i2c_start_1st;
begin
	i2c_start = 1'b0;
	@(posedge arstn)
	@(posedge clk)
		#(CLK_CYCLE*10)	i2c_start = 1'b1;
		#(CLK_CYCLE)	i2c_start = 1'b0;
end
endtask

task gen_i2c_start_2nd;
begin
	@(posedge i2c_start)
		#(CLK_CYCLE*DIV*19)	i2c_start = 1'b1;
		#(CLK_CYCLE)	i2c_start = 1'b0;
end
endtask

task gen_addr_WR;
begin
	@(posedge i2c_start)
		addr = 7'b0100101;
		rw = 1'b0;
end
endtask

task gen_addr_WR_diff;
begin
	gen_addr_WR;
	@(posedge i2c_start)
		addr = 7'b1001100;
		rw = 1'b0;
end
endtask

task gen_addr_RD;
begin
	@(posedge i2c_start)
		addr = 7'b0100101;
		rw = 1'b1;
end
endtask

task gen_addr_RD_diff;
begin
	gen_addr_RD;
	@(posedge i2c_start)
		addr = 7'b1001100;
		rw = 1'b1;
end
endtask

task gen_addr_WR_RD;
begin
	gen_addr_WR;
	gen_addr_RD;
end
endtask

task gen_data_send_1;
begin
	@(posedge i2c_start)
		data_send = 8'b01100011;
end
endtask

task gen_data_send_2;
begin
	gen_data_send_1;
	@(posedge i2c_start)
		data_send = 8'b10011101;
end
endtask

task gen_data_recv_1;
begin
	@(negedge i2c_start)
		#(CLK_CYCLE*DIV*11)
		sda_in_en = 1'b1;	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in_en = 1'b0;
end
endtask

task gen_data_recv_2;
begin
	gen_data_recv_1;
	@(negedge i2c_start)
		#(CLK_CYCLE*DIV)
		sda_in_en = 1'b1;	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in_en = 1'b0;
end
endtask

task gen_data_recv_2_diff;
begin
	gen_data_recv_1;
	@(negedge i2c_start)
		#(CLK_CYCLE*DIV*11)
		sda_in_en = 1'b1;	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in_en = 1'b0;
end
endtask

task gen_data_recv_2nd;
begin
	@(negedge i2c_start);
	@(negedge i2c_start)
		#(CLK_CYCLE*DIV*11)
		sda_in_en = 1'b1;	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in_en = 1'b0;
end
endtask

task gen_ACK_WR_1;
begin
	sda_in_en = 1'b0;
	@(negedge i2c_start)
		#(CLK_CYCLE*DIV*10)
			sda_in_en = 1'b1;
			sda_in = 1'b0;
		#(CLK_CYCLE*DIV)
			sda_in_en = 1'b0;
		#(CLK_CYCLE*DIV*8)
			sda_in_en = 1'b1;
			sda_in = 1'b0;
		#(CLK_CYCLE*DIV)
			sda_in_en = 1'b0;
end
endtask

task gen_ACK_WR_2;
begin
	gen_ACK_WR_1;
	#(CLK_CYCLE*DIV*8)
		sda_in_en = 1'b1;
		sda_in = 1'b0;
	#(CLK_CYCLE*DIV)
		sda_in_en = 1'b0;
end
endtask

task gen_ACK_WR_2_diff;
begin
	gen_ACK_WR_1;
	#(CLK_CYCLE*DIV*9)
		sda_in_en = 1'b1;
		sda_in = 1'b0;
	#(CLK_CYCLE*DIV)
		sda_in_en = 1'b0;
	#(CLK_CYCLE*DIV*8)
		sda_in_en = 1'b1;
		sda_in = 1'b0;
	#(CLK_CYCLE*DIV)
		sda_in_en = 1'b0;
end
endtask

task gen_ACK_RD_1;
begin
	sda_in_en = 1'b0;
	@(negedge i2c_start)
		#(CLK_CYCLE*DIV*10)
			sda_in_en = 1'b1;
			sda_in = 1'b0;


end
endtask

task gen_ACK_RD_2;
begin
	gen_ACK_RD_1;
	#(CLK_CYCLE*DIV*(8+1+1+8+1))
		sda_in_en = 1'b1;
		sda_in = 1'b0;


end
endtask

task gen_ACK_WR_RD;
begin
	gen_ACK_WR_1;
	#(CLK_CYCLE*DIV*9)
		sda_in_en = 1'b1;
		sda_in = 1'b0;


end
endtask

task gen_finish;
begin
	@(negedge i2c_done)
		#(CLK_CYCLE*75)	$finish;
end
endtask

task test_WR_1;
fork
	gen_i2c_start_1st;
	gen_addr_WR;
	gen_data_send_1;
	gen_ACK_WR_1;
join
endtask

task test_WR_2_same;
fork
	gen_i2c_start_1st;
	gen_i2c_start_2nd;
	gen_addr_WR;
	gen_data_send_2;
	gen_ACK_WR_2;
join
endtask

task test_WR_2_diff;
fork
	gen_i2c_start_1st;
	gen_i2c_start_2nd;
	gen_addr_WR_diff;
	gen_data_send_2;
	gen_ACK_WR_2_diff;
join
endtask

task test_RD_1;
fork
	gen_i2c_start_1st;
	gen_addr_RD;
	gen_data_recv_1;
	gen_ACK_RD_1;
join
endtask

task test_RD_2_same;
fork
	gen_i2c_start_1st;
	gen_i2c_start_2nd;
	gen_addr_RD;
	gen_data_recv_2;
	gen_ACK_RD_1;
join
endtask

task test_RD_2_diff;
fork
	gen_i2c_start_1st;
	gen_i2c_start_2nd;
	gen_addr_RD_diff;
	gen_data_recv_2_diff;
	gen_ACK_RD_2;
join
endtask

task test_WR_RD;
fork
	gen_i2c_start_1st;
	gen_i2c_start_2nd;
	gen_addr_WR_RD;
	gen_data_send_1;
	gen_ACK_WR_RD;
	gen_data_recv_2nd;
join
endtask

initial begin






	test_WR_RD;
	gen_finish;
end

i2c_master
#(
	.CLK_FREQ(CLK_FREQ),
	.I2C_FREQ(I2C_FREQ)
)
DUT(
	.clk(clk),
	.arstn(arstn),
	.i2c_start(i2c_start),
	.addr(addr),
	.rw(rw),
	.data_send(data_send),
	.i2c_done(i2c_done),
	.data_recv(data_recv),
	.data_recv_done(data_recv_done),
	.sda(sda),
	.scl(scl)
);

endmodule
module i2c_master_tb();


parameter	CLK_FREQ = 50_000_000,
			I2C_FREQ = 500_000,
			CLK_CYCLE = 20,
			DIV = CLK_FREQ / I2C_FREQ;

reg	clk, arstn;
reg	i2c_start;
reg	[7-1:0]	addr;
reg	rw;
reg	[8-1:0]	data_send;
wire	i2c_done;
wire	[8-1:0]	data_recv;
wire	data_recv_done;
reg	sda_in, sda_in_en;

wire	sda, scl;

assign sda = sda_in_en ? sda_in : 1'bz;


initial begin
	clk = 0;
	forever	#(CLK_CYCLE/2)	clk = ~clk;
end


initial begin
	arstn = 1'b0;
	#(CLK_CYCLE*75)	arstn = 1'b1;
end

task gen_i2c_start_1st;
begin
	i2c_start = 1'b0;
	@(posedge arstn)
	@(posedge clk)
		#(CLK_CYCLE*10)	i2c_start = 1'b1;
		#(CLK_CYCLE)	i2c_start = 1'b0;
end
endtask

task gen_i2c_start_2nd;
begin
	@(posedge i2c_start)
		#(CLK_CYCLE*DIV*19)	i2c_start = 1'b1;
		#(CLK_CYCLE)	i2c_start = 1'b0;
end
endtask

task gen_addr_WR;
begin
	@(posedge i2c_start)
		addr = 7'b0100101;
		rw = 1'b0;
end
endtask

task gen_addr_WR_diff;
begin
	gen_addr_WR;
	@(posedge i2c_start)
		addr = 7'b1001100;
		rw = 1'b0;
end
endtask

task gen_addr_RD;
begin
	@(posedge i2c_start)
		addr = 7'b0100101;
		rw = 1'b1;
end
endtask

task gen_addr_RD_diff;
begin
	gen_addr_RD;
	@(posedge i2c_start)
		addr = 7'b1001100;
		rw = 1'b1;
end
endtask

task gen_addr_WR_RD;
begin
	gen_addr_WR;
	gen_addr_RD;
end
endtask

task gen_data_send_1;
begin
	@(posedge i2c_start)
		data_send = 8'b01100011;
end
endtask

task gen_data_send_2;
begin
	gen_data_send_1;
	@(posedge i2c_start)
		data_send = 8'b10011101;
end
endtask

task gen_data_recv_1;
begin
	@(negedge i2c_start)
		#(CLK_CYCLE*DIV*11)
		sda_in_en = 1'b1;	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in_en = 1'b0;
end
endtask

task gen_data_recv_2;
begin
	gen_data_recv_1;
	@(negedge i2c_start)
		#(CLK_CYCLE*DIV)
		sda_in_en = 1'b1;	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in_en = 1'b0;
end
endtask

task gen_data_recv_2_diff;
begin
	gen_data_recv_1;
	@(negedge i2c_start)
		#(CLK_CYCLE*DIV*11)
		sda_in_en = 1'b1;	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in_en = 1'b0;
end
endtask

task gen_data_recv_2nd;
begin
	@(negedge i2c_start);
	@(negedge i2c_start)
		#(CLK_CYCLE*DIV*11)
		sda_in_en = 1'b1;	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b0;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in = 1'b1;
		#(CLK_CYCLE*DIV)	sda_in_en = 1'b0;
end
endtask

task gen_ACK_WR_1;
begin
	sda_in_en = 1'b0;
	@(negedge i2c_start)
		#(CLK_CYCLE*DIV*10)
			sda_in_en = 1'b1;
			sda_in = 1'b0;
		#(CLK_CYCLE*DIV)
			sda_in_en = 1'b0;
		#(CLK_CYCLE*DIV*8)
			sda_in_en = 1'b1;
			sda_in = 1'b0;
		#(CLK_CYCLE*DIV)
			sda_in_en = 1'b0;
end
endtask

task gen_ACK_WR_2;
begin
	gen_ACK_WR_1;
	#(CLK_CYCLE*DIV*8)
		sda_in_en = 1'b1;
		sda_in = 1'b0;
	#(CLK_CYCLE*DIV)
		sda_in_en = 1'b0;
end
endtask

task gen_ACK_WR_2_diff;
begin
	gen_ACK_WR_1;
	#(CLK_CYCLE*DIV*9)
		sda_in_en = 1'b1;
		sda_in = 1'b0;
	#(CLK_CYCLE*DIV)
		sda_in_en = 1'b0;
	#(CLK_CYCLE*DIV*8)
		sda_in_en = 1'b1;
		sda_in = 1'b0;
	#(CLK_CYCLE*DIV)
		sda_in_en = 1'b0;
end
endtask

task gen_ACK_RD_1;
begin
	sda_in_en = 1'b0;
	@(negedge i2c_start)
		#(CLK_CYCLE*DIV*10)
			sda_in_en = 1'b1;
			sda_in = 1'b0;


end
endtask

task gen_ACK_RD_2;
begin
	gen_ACK_RD_1;
	#(CLK_CYCLE*DIV*(8+1+1+8+1))
		sda_in_en = 1'b1;
		sda_in = 1'b0;


end
endtask

task gen_ACK_WR_RD;
begin
	gen_ACK_WR_1;
	#(CLK_CYCLE*DIV*9)
		sda_in_en = 1'b1;
		sda_in = 1'b0;


end
endtask

task gen_finish;
begin
	@(negedge i2c_done)
		#(CLK_CYCLE*75)	$finish;
end
endtask

task test_WR_1;
fork
	gen_i2c_start_1st;
	gen_addr_WR;
	gen_data_send_1;
	gen_ACK_WR_1;
join
endtask

task test_WR_2_same;
fork
	gen_i2c_start_1st;
	gen_i2c_start_2nd;
	gen_addr_WR;
	gen_data_send_2;
	gen_ACK_WR_2;
join
endtask

task test_WR_2_diff;
fork
	gen_i2c_start_1st;
	gen_i2c_start_2nd;
	gen_addr_WR_diff;
	gen_data_send_2;
	gen_ACK_WR_2_diff;
join
endtask

task test_RD_1;
fork
	gen_i2c_start_1st;
	gen_addr_RD;
	gen_data_recv_1;
	gen_ACK_RD_1;
join
endtask

task test_RD_2_same;
fork
	gen_i2c_start_1st;
	gen_i2c_start_2nd;
	gen_addr_RD;
	gen_data_recv_2;
	gen_ACK_RD_1;
join
endtask

task test_RD_2_diff;
fork
	gen_i2c_start_1st;
	gen_i2c_start_2nd;
	gen_addr_RD_diff;
	gen_data_recv_2_diff;
	gen_ACK_RD_2;
join
endtask

task test_WR_RD;
fork
	gen_i2c_start_1st;
	gen_i2c_start_2nd;
	gen_addr_WR_RD;
	gen_data_send_1;
	gen_ACK_WR_RD;
	gen_data_recv_2nd;
join
endtask

initial begin






	test_WR_RD;
	gen_finish;
end

i2c_master
#(
	.CLK_FREQ(CLK_FREQ),
	.I2C_FREQ(I2C_FREQ)
)
DUT(
	.clk(clk),
	.arstn(arstn),
	.i2c_start(i2c_start),
	.addr(addr),
	.rw(rw),
	.data_send(data_send),
	.i2c_done(i2c_done),
	.data_recv(data_recv),
	.data_recv_done(data_recv_done),
	.sda(sda),
	.scl(scl)
);

endmodule