data/full_repos/permissive/211316121/lab5_4_nexys4/74LS194.v
data/verilator_xmls/72844cc1-2a5b-49c9-8cdc-211970544e33.xml
module Top_74LS194(
    input [8:0] sw,
    input clkstd,
    output [3:0] led
);

wire clk;

CLKDIV top_div(clkstd,clk);

LS194 top_194(sw[3:0],sw[4],sw[5],sw[6],sw[7],clk,sw[8],led[3:0]);

endmodule
module Top_74LS194(
    input [8:0] sw,
    input clkstd,
    output [3:0] led
);


wire clk;

CLKDIV top_div(clkstd,clk);

LS194 top_194(sw[3:0],sw[4],sw[5],sw[6],sw[7],clk,sw[8],led[3:0]);

endmodule