data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/hard_macros_ql/dff_pre_clr_ql.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/hard_macros_ql/dff_pre_clr_ql.v:13: Cannot find file containing module: 'dffpc'\ndffpc dffpc_0 ( .CLK(CLK) , .CLR(CLR), .D(D), .PRE(PRE), .Q(Q) ) ;\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/hard_macros_ql,data/full_repos/permissive/137416811/dffpc\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/hard_macros_ql,data/full_repos/permissive/137416811/dffpc.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/ULPSH_fabric/rtl/src/hard_macros_ql,data/full_repos/permissive/137416811/dffpc.sv\n             dffpc\n             dffpc.v\n             dffpc.sv\n             obj_dir/dffpc\n             obj_dir/dffpc.v\n             obj_dir/dffpc.sv\n%Error: Exiting due to 1 error(s)\n"
module dff_pre_clr (
	input	CLK,
	input	CLR,
	input	D,
	input	PRE,
	output	Q
);

dffpc dffpc_0 ( .CLK(CLK) , .CLR(CLR), .D(D), .PRE(PRE), .Q(Q) );


endmodule
module dff_pre_clr (
	input	CLK,
	input	CLR,
	input	D,
	input	PRE,
	output	Q
);


dffpc dffpc_0 ( .CLK(CLK) , .CLR(CLR), .D(D), .PRE(PRE), .Q(Q) );


endmodule