data/full_repos/permissive/143278/ivltests/uwire2.v
 line:5: before: "["
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/uwire2.v:11: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (foo !== \'h5555aaaa) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

   uwire [31:0] foo;

   assign foo[15:0] = 'haaaa;
   assign foo[31:16] = 'h5555;

   initial begin
      #1 if (foo !== 'h5555aaaa) begin
	 $display("FAILED -- foo=%h", foo);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module test;


   uwire [31:0] foo;

   assign foo[15:0] = 'haaaa;
   assign foo[31:16] = 'h5555;

   initial begin
      #1 if (foo !== 'h5555aaaa) begin
	 $display("FAILED -- foo=%h", foo);
	 $finish;
      end

      $display("PASSED");
   end

endmodule