data/full_repos/permissive/131249673/MIPS_L_PipeLine/work/ByPasser.v
1: b'%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/work/ByPasser.v:1: Cannot find include file: ctrl_encode_def.v\n`include "ctrl_encode_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine/work,data/full_repos/permissive/131249673/ctrl_encode_def.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine/work,data/full_repos/permissive/131249673/ctrl_encode_def.v.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine/work,data/full_repos/permissive/131249673/ctrl_encode_def.v.sv\n             ctrl_encode_def.v\n             ctrl_encode_def.v.v\n             ctrl_encode_def.v.sv\n             obj_dir/ctrl_encode_def.v\n             obj_dir/ctrl_encode_def.v.v\n             obj_dir/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/work/ByPasser.v:2: Cannot find include file: instruction_def.v\n`include "instruction_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module byPasser ( clk, rst,
	WriteDst_EX_MEM, WriteDst_MEM_WB,
	rs_ID_EX_r, rt_ID_EX_r,
	MEM_ctrl_RegWr, WB_ctrl_RegWr,
	byPasserSelA, byPasserSelB
	);

	input	clk, rst;
	input	[4:0]	WriteDst_EX_MEM;
	input	[4:0]	WriteDst_MEM_WB;
	input	[4:0]	rs_ID_EX_r;
	input	[4:0]	rt_ID_EX_r;
	input			MEM_ctrl_RegWr;
	input			WB_ctrl_RegWr;
	
	output	[1:0]	byPasserSelA;
	output	[1:0]	byPasserSelB;

	reg [1:0]	byPasserSelA;
	reg	[1:0]	byPasserSelB;
  	
	always @(*) begin
	byPasserSelA = 2'b00;
	byPasserSelB = 2'b00;
	

	if (WB_ctrl_RegWr && WriteDst_MEM_WB != 0)
		begin
		if (rs_ID_EX_r == WriteDst_MEM_WB)
			byPasserSelA = 2'b01;
		
		if (rt_ID_EX_r == WriteDst_MEM_WB)
			byPasserSelB = 2'b01;
		end

	if (MEM_ctrl_RegWr && WriteDst_EX_MEM != 0)
		begin
		if (rs_ID_EX_r == WriteDst_EX_MEM)
			byPasserSelA = 2'b10;

		if (rt_ID_EX_r == WriteDst_EX_MEM)
			byPasserSelB = 2'b10;
		end

	end
endmodule
module byPasser ( clk, rst,
	WriteDst_EX_MEM, WriteDst_MEM_WB,
	rs_ID_EX_r, rt_ID_EX_r,
	MEM_ctrl_RegWr, WB_ctrl_RegWr,
	byPasserSelA, byPasserSelB
	);


	input	clk, rst;
	input	[4:0]	WriteDst_EX_MEM;
	input	[4:0]	WriteDst_MEM_WB;
	input	[4:0]	rs_ID_EX_r;
	input	[4:0]	rt_ID_EX_r;
	input			MEM_ctrl_RegWr;
	input			WB_ctrl_RegWr;
	
	output	[1:0]	byPasserSelA;
	output	[1:0]	byPasserSelB;

	reg [1:0]	byPasserSelA;
	reg	[1:0]	byPasserSelB;
  	
	always @(*) begin
	byPasserSelA = 2'b00;
	byPasserSelB = 2'b00;
	

	if (WB_ctrl_RegWr && WriteDst_MEM_WB != 0)
		begin
		if (rs_ID_EX_r == WriteDst_MEM_WB)
			byPasserSelA = 2'b01;
		
		if (rt_ID_EX_r == WriteDst_MEM_WB)
			byPasserSelB = 2'b01;
		end

	if (MEM_ctrl_RegWr && WriteDst_EX_MEM != 0)
		begin
		if (rs_ID_EX_r == WriteDst_EX_MEM)
			byPasserSelA = 2'b10;

		if (rt_ID_EX_r == WriteDst_EX_MEM)
			byPasserSelB = 2'b10;
		end

	end
endmodule