data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
1: b'%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:83: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:85: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:107: Define or directive not defined: \'`OR1200_OPERAND_WIDTH\'\nparameter dw = `OR1200_OPERAND_WIDTH;\n               ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:107: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter dw = `OR1200_OPERAND_WIDTH;\n                                    ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:108: Define or directive not defined: \'`OR1200_OPERAND_WIDTH\'\nparameter aw = `OR1200_OPERAND_WIDTH;\n               ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter aw = `OR1200_OPERAND_WIDTH;\n                                    ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:126: Define or directive not defined: \'`OR1200_IMMU_PS\'\noutput [31:`OR1200_IMMU_PS] ppn;\n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:126: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\noutput [31:`OR1200_IMMU_PS] ppn;\n                          ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:152: Define or directive not defined: \'`OR1200_ITLB_TAG\'\nwire [`OR1200_ITLB_TAG] vpn;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:152: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`OR1200_ITLB_TAG] vpn;\n                      ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:154: Define or directive not defined: \'`OR1200_ITLB_INDXW\'\nwire [`OR1200_ITLB_INDXW-1:0] tlb_index;\n      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:157: Define or directive not defined: \'`OR1200_ITLBMRW\'\nwire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:158: Define or directive not defined: \'`OR1200_ITLBMRW\'\nwire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:161: Define or directive not defined: \'`OR1200_ITLBTRW\'\nwire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:162: Define or directive not defined: \'`OR1200_ITLBTRW\'\nwire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:188: Define or directive not defined: \'`OR1200_ITLB_TM_ADDR\'\nassign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);\n                                                ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:188: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);\n                                                                    ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:193: Define or directive not defined: \'`OR1200_ITLB_TM_ADDR\'\nassign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];\n                                                  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:193: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];\n                                                                      ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:198: Define or directive not defined: \'`OR1200_ITLB_TM_ADDR\'\nassign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);\n                                               ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:198: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);\n                                                                   ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:203: Define or directive not defined: \'`OR1200_ITLB_TM_ADDR\'\nassign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];\n                                                 ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:203: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];\n                                                                     ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:208: Define or directive not defined: \'`OR1200_ITLB_TM_ADDR\'\nassign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?\n                                           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:208: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?\n                                                               ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:209: Define or directive not defined: \'`OR1200_ITLB_INDXW\'\n   {vpn, tlb_index & {`OR1200_ITLB_INDXW{v}}, {`OR1200_ITLB_TAGW-7{1\'b0}}, 1\'b0, 5\'b00000, v} :\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:209: Define or directive not defined: \'`OR1200_ITLB_TAGW\'\n   {vpn, tlb_index & {`OR1200_ITLB_INDXW{v}}, {`OR1200_ITLB_TAGW-7{1\'b0}}, 1\'b0, 5\'b00000, v} :\n                                               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:210: Define or directive not defined: \'`OR1200_ITLB_TM_ADDR\'\n  (!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?\n                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:211: Define or directive not defined: \'`OR1200_IMMU_PS\'\n   {ppn, {`OR1200_IMMU_PS-8{1\'b0}}, uxe, sxe, {4{1\'b0}}, ci, 1\'b0} :\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:222: Define or directive not defined: \'`OR1200_ITLB_TAG\'\nassign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};\n                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:222: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};\n                                                  ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:222: Define or directive not defined: \'`OR1200_ITLBMR_V_BITS\'\nassign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};\n                                                               ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:232: Define or directive not defined: \'`OR1200_IMMU_PS\'\nassign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],\n                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:232: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],\n                                                    ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:233: Define or directive not defined: \'`OR1200_ITLBTR_UXE_BITS\'\n   spr_dat_i[`OR1200_ITLBTR_UXE_BITS],\n             ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:234: Define or directive not defined: \'`OR1200_ITLBTR_SXE_BITS\'\n   spr_dat_i[`OR1200_ITLBTR_SXE_BITS],\n             ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:235: Define or directive not defined: \'`OR1200_ITLBTR_CI_BITS\'\n   spr_dat_i[`OR1200_ITLBTR_CI_BITS]};\n             ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:240: Define or directive not defined: \'`OR1200_ITLB_TAG\'\nassign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;\n                           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:240: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;\n                                           ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:246: Define or directive not defined: \'`OR1200_ITLB_INDXW\'\nassign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];\n                                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:246: Define or directive not defined: \'`OR1200_ITLB_INDX\'\nassign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];\n                                                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v:246: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];\n                                                                                      ^\n%Error: Exiting due to 42 error(s)\n'
module or1200_immu_tlb(

	clk, rst,


	tlb_en, vaddr, hit, ppn, uxe, sxe, ci, 

`ifdef OR1200_BIST

	mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif


	spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);

parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;








input				clk;
input				rst;




input				tlb_en;
input	[aw-1:0]		vaddr;
output				hit;
output	[31:`OR1200_IMMU_PS]	ppn;
output				uxe;
output				sxe;
output				ci;

`ifdef OR1200_BIST



input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif




input				spr_cs;
input				spr_write;
input	[31:0]			spr_addr;
input	[31:0]			spr_dat_i;
output	[31:0]			spr_dat_o;




wire	[`OR1200_ITLB_TAG]	vpn;
wire				v;
wire	[`OR1200_ITLB_INDXW-1:0]	tlb_index;
wire				tlb_mr_en;
wire				tlb_mr_we;
wire	[`OR1200_ITLBMRW-1:0]	tlb_mr_ram_in;
wire	[`OR1200_ITLBMRW-1:0]	tlb_mr_ram_out;
wire				tlb_tr_en;
wire				tlb_tr_we;
wire	[`OR1200_ITLBTRW-1:0]	tlb_tr_ram_in;
wire	[`OR1200_ITLBTRW-1:0]	tlb_tr_ram_out;


`ifdef OR1200_BIST
wire                        itlb_mr_ram_si;
wire                        itlb_mr_ram_so;
wire                        itlb_tr_ram_si;
wire                        itlb_tr_ram_so;
`endif

















assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);




assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];




assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);




assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];




assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
			{vpn, tlb_index & {`OR1200_ITLB_INDXW{v}}, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
		(!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
			{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
			32'h00000000;




assign {vpn, v} = tlb_mr_ram_out;




assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};




assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;




assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
			spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
			spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
			spr_dat_i[`OR1200_ITLBTR_CI_BITS]};




assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;





assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];


`ifdef OR1200_BIST
assign itlb_mr_ram_si = mbist_si_i;
assign itlb_tr_ram_si = itlb_mr_ram_so;
assign mbist_so_o = itlb_tr_ram_so;
`endif





or1200_spram_64x14 itlb_mr_ram(
	.clk(clk),
	.rst(rst),
`ifdef OR1200_BIST

	.mbist_si_i(itlb_mr_ram_si),
	.mbist_so_o(itlb_mr_ram_so),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.ce(tlb_mr_en),
	.we(tlb_mr_we),
	.oe(1'b1),
	.addr(tlb_index),
	.di(tlb_mr_ram_in),
	.doq(tlb_mr_ram_out)
);




or1200_spram_64x22 itlb_tr_ram(
	.clk(clk),
	.rst(rst),
`ifdef OR1200_BIST

	.mbist_si_i(itlb_tr_ram_si),
	.mbist_so_o(itlb_tr_ram_so),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.ce(tlb_tr_en),
	.we(tlb_tr_we),
	.oe(1'b1),
	.addr(tlb_index),
	.di(tlb_tr_ram_in),
	.doq(tlb_tr_ram_out)
);

endmodule
module or1200_immu_tlb(

	clk, rst,


	tlb_en, vaddr, hit, ppn, uxe, sxe, ci, 

`ifdef OR1200_BIST

	mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif


	spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);


parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;








input				clk;
input				rst;




input				tlb_en;
input	[aw-1:0]		vaddr;
output				hit;
output	[31:`OR1200_IMMU_PS]	ppn;
output				uxe;
output				sxe;
output				ci;

`ifdef OR1200_BIST



input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif




input				spr_cs;
input				spr_write;
input	[31:0]			spr_addr;
input	[31:0]			spr_dat_i;
output	[31:0]			spr_dat_o;




wire	[`OR1200_ITLB_TAG]	vpn;
wire				v;
wire	[`OR1200_ITLB_INDXW-1:0]	tlb_index;
wire				tlb_mr_en;
wire				tlb_mr_we;
wire	[`OR1200_ITLBMRW-1:0]	tlb_mr_ram_in;
wire	[`OR1200_ITLBMRW-1:0]	tlb_mr_ram_out;
wire				tlb_tr_en;
wire				tlb_tr_we;
wire	[`OR1200_ITLBTRW-1:0]	tlb_tr_ram_in;
wire	[`OR1200_ITLBTRW-1:0]	tlb_tr_ram_out;


`ifdef OR1200_BIST
wire                        itlb_mr_ram_si;
wire                        itlb_mr_ram_so;
wire                        itlb_tr_ram_si;
wire                        itlb_tr_ram_so;
`endif

















assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);




assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];




assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);




assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];




assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
			{vpn, tlb_index & {`OR1200_ITLB_INDXW{v}}, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
		(!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
			{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
			32'h00000000;




assign {vpn, v} = tlb_mr_ram_out;




assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};




assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;




assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
			spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
			spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
			spr_dat_i[`OR1200_ITLBTR_CI_BITS]};




assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;





assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];


`ifdef OR1200_BIST
assign itlb_mr_ram_si = mbist_si_i;
assign itlb_tr_ram_si = itlb_mr_ram_so;
assign mbist_so_o = itlb_tr_ram_so;
`endif





or1200_spram_64x14 itlb_mr_ram(
	.clk(clk),
	.rst(rst),
`ifdef OR1200_BIST

	.mbist_si_i(itlb_mr_ram_si),
	.mbist_so_o(itlb_mr_ram_so),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.ce(tlb_mr_en),
	.we(tlb_mr_we),
	.oe(1'b1),
	.addr(tlb_index),
	.di(tlb_mr_ram_in),
	.doq(tlb_mr_ram_out)
);




or1200_spram_64x22 itlb_tr_ram(
	.clk(clk),
	.rst(rst),
`ifdef OR1200_BIST

	.mbist_si_i(itlb_tr_ram_si),
	.mbist_so_o(itlb_tr_ram_so),
	.mbist_ctrl_i(mbist_ctrl_i),
`endif
	.ce(tlb_tr_en),
	.we(tlb_tr_we),
	.oe(1'b1),
	.addr(tlb_index),
	.di(tlb_tr_ram_in),
	.doq(tlb_tr_ram_out)
);

endmodule