data/full_repos/permissive/174369527/simpleCPU/src/ram.v
data/verilator_xmls/0b218590-9ad3-4ca4-adfb-c654823454b7.xml
module ram (
	clk,
	addr,
	DO,
	DI,
	EN,
	WE,
	RE
	);

parameter AddrSize = 11;
parameter WordSize = 9;

input wire clk;
input wire [AddrSize-1:0] addr;
output reg [WordSize-1:0] DO;
input wire [WordSize-1:0] DI;
input wire EN, WE, RE;

reg [WordSize-1:0] Mem [0:(1<<AddrSize)-1];

always @ (posedge clk)
begin
	if (EN && RE)
		DO <= Mem[addr];
	else
		DO <= {WordSize{1'bx}};
end

initial begin
	$display("Loading ram.");
	$readmemb("ram.mem", Mem);
end

always @ (posedge clk)
	if (EN && WE)
		Mem[addr] <= DI;

always @(WE or RE)
	if (WE && RE)
		$display("Operational error in RamChip: RE and WE both active");
endmodule
module ram (
	clk,
	addr,
	DO,
	DI,
	EN,
	WE,
	RE
	);


parameter AddrSize = 11;
parameter WordSize = 9;

input wire clk;
input wire [AddrSize-1:0] addr;
output reg [WordSize-1:0] DO;
input wire [WordSize-1:0] DI;
input wire EN, WE, RE;

reg [WordSize-1:0] Mem [0:(1<<AddrSize)-1];

always @ (posedge clk)
begin
	if (EN && RE)
		DO <= Mem[addr];
	else
		DO <= {WordSize{1'bx}};
end

initial begin
	$display("Loading ram.");
	$readmemb("ram.mem", Mem);
end

always @ (posedge clk)
	if (EN && WE)
		Mem[addr] <= DI;

always @(WE or RE)
	if (WE && RE)
		$display("Operational error in RamChip: RE and WE both active");
endmodule