data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc/clock_gen.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc/clock_gen.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #5 forever clk = #5 ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/misc/clock_gen.v:35: syntax error, unexpected \'@\'\n      @(negedge clk);\n      ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock_gen (
  output reg clk,
  output reg rst);

  initial begin
    clk = 0;
    #5 forever clk = #5 ~clk;
  end

  integer i;
  initial begin
    rst <= 1;
    for (i=1; i<3; i=i+1)
      @(negedge clk);
    rst <= 0;
  end

endmodule
module clock_gen (
  output reg clk,
  output reg rst);


  initial begin
    clk = 0;
    #5 forever clk = #5 ~clk;
  end

  integer i;
  initial begin
    rst <= 1;
    for (i=1; i<3; i=i+1)
      @(negedge clk);
    rst <= 0;
  end

endmodule