data/full_repos/permissive/210844779/lab7/7.1/tb.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab7/7.1/tb.v:15: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab7/7.1/tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab7/7.1/tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab7/7.1/tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab7/7.1/tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: data/full_repos/permissive/210844779/lab7/7.1/tb.v:7: Cannot find file containing module: \'ram\'\nram u0(data,addr,clk,we,oe,ce1,ce2);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab7/7.1,data/full_repos/permissive/210844779/ram\n             data/full_repos/permissive/210844779/lab7/7.1,data/full_repos/permissive/210844779/ram.v\n             data/full_repos/permissive/210844779/lab7/7.1,data/full_repos/permissive/210844779/ram.sv\n             ram\n             ram.v\n             ram.sv\n             obj_dir/ram\n             obj_dir/ram.v\n             obj_dir/ram.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab7/7.1/tb.v:37: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  addr=$random;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab7/7.1/tb.v:38: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\n  din=$random;\n     ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;

reg[7:0]din;
wire[7:0]data;
reg clk=0,we,oe,ce1,ce2;
reg[12:0]addr;
ram u0(data,addr,clk,we,oe,ce1,ce2);




assign data=din;


always #5 clk=~clk;


always
begin
		we=0;
		oe=1;
		ce1=0;
		ce2=1;
		addr=$random;
		din=$random;
		#20
		we=1;
		oe=0;
		ce1=0;
		ce2=1;	
		din=8'bzzzzzzzz;
		#20;
		ce1=1;
		#20
		ce2=0;
		#20;
		
end
endmodule
module tb;


reg[7:0]din;
wire[7:0]data;
reg clk=0,we,oe,ce1,ce2;
reg[12:0]addr;
ram u0(data,addr,clk,we,oe,ce1,ce2);




assign data=din;


always #5 clk=~clk;


always
begin
		we=0;
		oe=1;
		ce1=0;
		ce2=1;
		addr=$random;
		din=$random;
		#20
		we=1;
		oe=0;
		ce1=0;
		ce2=1;	
		din=8'bzzzzzzzz;
		#20;
		ce1=1;
		#20
		ce2=0;
		#20;
		
end
endmodule