data/full_repos/permissive/161526648/SingleCycle.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:300: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                      : ... In instance SingleCycle.alu\n    result = ALUsrc1 < ALUsrc2;  \n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:227: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                      : ... In instance SingleCycle.ImExtend\n assign out = $signed(in);\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module SingleCycle(clock);
	input clock;
	reg [31:0]PC = 0;
	wire [31:0]instruction;
	InstructionMemory IM(PC,instruction);
	wire [5:0]opcode = instruction[31:26];
	wire [4:0]readReg1 = instruction[25:21];
	wire [4:0]readReg2 = instruction[20:16];
	wire [4:0]RegRd = instruction[15:11];
	wire [5:0]func = instruction[5:0];
	wire [15:0]immediate = instruction[15:0];
	wire [25:0]jumpaddr = instruction[25:0];
	
	wire [31:0]extendedIm;
	signExtension ImExtend(immediate,extendedIm);
	
	wire RegDst,Jump,Branch,bne,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite;
	wire [1:0]ALUop;
	control controlUnit(opcode,RegDst,Jump,Branch,bne,MemRead,MemtoReg,ALUop,MemWrite,ALUSrc,RegWrite);
		
	wire [31:0]ReadData1;
	wire [31:0]ReadData2;
	wire [4:0]WriteReg;
	wire [31:0]WriteData;
	
	mux5bit mux_writeReg(readReg2,RegRd,RegDst,WriteReg);
	RegFile RF(readReg1,readReg2,WriteReg,WriteData,RegWrite,ReadData1,ReadData2);
	
	wire [31:0] ALUsrc2;
	mux2_1 mux_alu(ReadData2,extendedIm,ALUSrc,ALUsrc2);
	
	wire [3:0]aluControl;
	ALUcontrol alucontrol(func,ALUop,aluControl);
	
	wire [31:0]ALUresult;
	wire ZERO;
	ALU alu(ReadData1,ALUsrc2,aluControl,ALUresult,ZERO);
	
	wire [31:0]ReadData;
	DataMem DM(ALUresult,ReadData2,MemWrite,MemRead,ReadData);
	
	mux2_1 mux_writeback(ALUresult,ReadData,MemtoReg,WriteData);
		
	wire[31:0]newPC = PC+4;
	wire[31:0]branchAddr = newPC + extendedIm*4; 
	wire[31:0]JumpAddress = {PC[31:28],jumpaddr,2'b00};
	wire[31:0]tempPC;
	wire[31:0]targetPC;
	




	
	wire ifbranch = (Branch && ZERO) || (bne &&(~ZERO));
	


	
	mux2_1 mux_ifbranch(newPC,branchAddr,ifbranch,tempPC);
	mux2_1 mux_ifjump(tempPC,JumpAddress,Jump,targetPC);
	
	always @(posedge clock) begin
		PC <= targetPC;
	end
endmodule
module SingleCycle(clock);

	input clock;
	reg [31:0]PC = 0;
	wire [31:0]instruction;
	InstructionMemory IM(PC,instruction);
	wire [5:0]opcode = instruction[31:26];
	wire [4:0]readReg1 = instruction[25:21];
	wire [4:0]readReg2 = instruction[20:16];
	wire [4:0]RegRd = instruction[15:11];
	wire [5:0]func = instruction[5:0];
	wire [15:0]immediate = instruction[15:0];
	wire [25:0]jumpaddr = instruction[25:0];
	
	wire [31:0]extendedIm;
	signExtension ImExtend(immediate,extendedIm);
	
	wire RegDst,Jump,Branch,bne,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite;
	wire [1:0]ALUop;
	control controlUnit(opcode,RegDst,Jump,Branch,bne,MemRead,MemtoReg,ALUop,MemWrite,ALUSrc,RegWrite);
		
	wire [31:0]ReadData1;
	wire [31:0]ReadData2;
	wire [4:0]WriteReg;
	wire [31:0]WriteData;
	
	mux5bit mux_writeReg(readReg2,RegRd,RegDst,WriteReg);
	RegFile RF(readReg1,readReg2,WriteReg,WriteData,RegWrite,ReadData1,ReadData2);
	
	wire [31:0] ALUsrc2;
	mux2_1 mux_alu(ReadData2,extendedIm,ALUSrc,ALUsrc2);
	
	wire [3:0]aluControl;
	ALUcontrol alucontrol(func,ALUop,aluControl);
	
	wire [31:0]ALUresult;
	wire ZERO;
	ALU alu(ReadData1,ALUsrc2,aluControl,ALUresult,ZERO);
	
	wire [31:0]ReadData;
	DataMem DM(ALUresult,ReadData2,MemWrite,MemRead,ReadData);
	
	mux2_1 mux_writeback(ALUresult,ReadData,MemtoReg,WriteData);
		
	wire[31:0]newPC = PC+4;
	wire[31:0]branchAddr = newPC + extendedIm*4; 
	wire[31:0]JumpAddress = {PC[31:28],jumpaddr,2'b00};
	wire[31:0]tempPC;
	wire[31:0]targetPC;
	




	
	wire ifbranch = (Branch && ZERO) || (bne &&(~ZERO));
	


	
	mux2_1 mux_ifbranch(newPC,branchAddr,ifbranch,tempPC);
	mux2_1 mux_ifjump(tempPC,JumpAddress,Jump,targetPC);
	
	always @(posedge clock) begin
		PC <= targetPC;
	end
endmodule