data/full_repos/permissive/192101253/ccd_register.v
data/verilator_xmls/d3f567d4-f612-4a7f-b01c-714fa83a737b.xml
module ccd_register (

	input reset,

	input clk_in,
	input we,
	input [7:0] din,
	output busy,

	input clk_out,
	input re,
	output [7:0] dout,
	output ready
);





	reg [7:0] data = 8'd0;
	always @(posedge clk_in) begin
		if (reset) data <= 8'd0;
		else if (we) data <= din;
	end
	assign dout = data;




	reg rdy = 1'b0;
	reg bsy = 1'b0;
	reg [2:0] rdy_q = 3'd0;
	reg [2:0] bsy_q = 3'd0;

	always @(posedge clk_in) rdy_q <= {rdy_q[1:0], rdy};
	wire read_event = rdy_q[2:1] == 2'b10;

	always @(posedge clk_in) begin
		if (reset || read_event) bsy <= 1'b0;
		else if (we) bsy <= 1'b1;
	end

	always @(posedge clk_out) bsy_q <= {bsy_q[1:0], bsy};
	wire write_event = bsy_q[2:1] == 2'b01;

	always @(posedge clk_out) begin
		if (reset || re) rdy <= 1'b0;
		else if (write_event) rdy <= 1'b1;
	end

	assign ready = rdy;
	assign busy = bsy;

endmodule
module ccd_register (

	input reset,

	input clk_in,
	input we,
	input [7:0] din,
	output busy,

	input clk_out,
	input re,
	output [7:0] dout,
	output ready
);






	reg [7:0] data = 8'd0;
	always @(posedge clk_in) begin
		if (reset) data <= 8'd0;
		else if (we) data <= din;
	end
	assign dout = data;




	reg rdy = 1'b0;
	reg bsy = 1'b0;
	reg [2:0] rdy_q = 3'd0;
	reg [2:0] bsy_q = 3'd0;

	always @(posedge clk_in) rdy_q <= {rdy_q[1:0], rdy};
	wire read_event = rdy_q[2:1] == 2'b10;

	always @(posedge clk_in) begin
		if (reset || read_event) bsy <= 1'b0;
		else if (we) bsy <= 1'b1;
	end

	always @(posedge clk_out) bsy_q <= {bsy_q[1:0], bsy};
	wire write_event = bsy_q[2:1] == 2'b01;

	always @(posedge clk_out) begin
		if (reset || re) rdy <= 1'b0;
		else if (write_event) rdy <= 1'b1;
	end

	assign ready = rdy;
	assign busy = bsy;

endmodule