data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:57: Cell has missing pin: \'clk1_out\'\n  pll_test u_pll_test (\n           ^~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:57: Cell has missing pin: \'clk2_out\'\n  pll_test u_pll_test (\n           ^~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:225: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg0 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:231: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:237: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg2 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:439: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg0 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:445: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:569: Cell has missing pin: \'en\'\n  reg_ar_as_w13 reg0 (\n                ^~~~\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:601: Cannot find file containing module: \'EG_LOGIC_BUFG\'\n  EG_LOGIC_BUFG bufg_feedback (\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG.v\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG.sv\n             EG_LOGIC_BUFG\n             EG_LOGIC_BUFG.v\n             EG_LOGIC_BUFG.sv\n             obj_dir/EG_LOGIC_BUFG\n             obj_dir/EG_LOGIC_BUFG.v\n             obj_dir/EG_LOGIC_BUFG.sv\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:604: Cannot find file containing module: \'EG_PHY_PLL\'\n  EG_PHY_PLL #(\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module speed_setting
  (
  bps_start,
  clk,
  rst_n,
  clk_bps
  );

  input bps_start;
  input clk;
  input rst_n;
  output clk_bps;

  parameter BPS_SET = 96;
  parameter CLK_PERIORD = 40;
  wire [12:0] cnt;
  wire [12:0] n4;
  wire [12:0] n5;
  wire clk_bps_r;
  wire n0;
  wire n1;
  wire n2;
  wire n3;
  wire n6;

  add_pu13_pu13_o13 add0 (
    .i0(cnt),
    .i1(13'b0000000000001),
    .o(n4));
  AL_DFF clk_bps_r_reg (
    .clk(clk),
    .d(n6),
    .reset(n0),
    .set(1'b0),
    .q(clk_bps_r));
  eq_w13 eq0 (
    .i0(cnt),
    .i1(13'b0101000101100),
    .o(n1));
  eq_w13 eq1 (
    .i0(cnt),
    .i1(13'b0010100010110),
    .o(n6));
  binary_mux_s1_w13 mux0 (
    .i0(n4),
    .i1(13'b0000000000000),
    .sel(n3),
    .o(n5));
  reg_ar_as_w13 reg0 (
    .clk(clk),
    .d(n5),
    .reset({n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0}),
    .set(13'b0000000000000),
    .q(cnt));
  not u2 (n0, rst_n);
  not u3 (n2, bps_start);
  or u4 (n3, n1, n2);
  buf u5 (clk_bps, clk_bps_r);

endmodule
module speed_setting
  (
  bps_start,
  clk,
  rst_n,
  clk_bps
  );


  input bps_start;
  input clk;
  input rst_n;
  output clk_bps;

  parameter BPS_SET = 96;
  parameter CLK_PERIORD = 40;
  wire [12:0] cnt;
  wire [12:0] n4;
  wire [12:0] n5;
  wire clk_bps_r;
  wire n0;
  wire n1;
  wire n2;
  wire n3;
  wire n6;

  add_pu13_pu13_o13 add0 (
    .i0(cnt),
    .i1(13'b0000000000001),
    .o(n4));
  AL_DFF clk_bps_r_reg (
    .clk(clk),
    .d(n6),
    .reset(n0),
    .set(1'b0),
    .q(clk_bps_r));
  eq_w13 eq0 (
    .i0(cnt),
    .i1(13'b0101000101100),
    .o(n1));
  eq_w13 eq1 (
    .i0(cnt),
    .i1(13'b0010100010110),
    .o(n6));
  binary_mux_s1_w13 mux0 (
    .i0(n4),
    .i1(13'b0000000000000),
    .sel(n3),
    .o(n5));
  reg_ar_as_w13 reg0 (
    .clk(clk),
    .d(n5),
    .reset({n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0}),
    .set(13'b0000000000000),
    .q(cnt));
  not u2 (n0, rst_n);
  not u3 (n2, bps_start);
  or u4 (n3, n1, n2);
  buf u5 (clk_bps, clk_bps_r);

endmodule