data/full_repos/permissive/175100691/gpu/sim/Main.v
 line:36: before: "+"
1: b'%Warning-WIDTH: data/full_repos/permissive/175100691/gpu/sim/Main.v:30: Operator ADD expects 30 bits on the LHS, but LHS\'s VARREF \'sdram_gpu_address\' generates 24 bits.\n                                                                      : ... In instance Main\n    assign sdram_address = (sdram_gpu_address + 30\'h3E000000) >> 2;\n                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/175100691/gpu/sim/Main.v:37: Cannot find file containing module: \'GPU\'\n            GPU #(.WORD_WIDTH(WORD_WIDTH), .ADDRESS_WIDTH(ADDRESS_WIDTH))\n            ^~~\n        ... Looked in:\n             data/full_repos/permissive/175100691/gpu/sim,data/full_repos/permissive/175100691/GPU\n             data/full_repos/permissive/175100691/gpu/sim,data/full_repos/permissive/175100691/GPU.v\n             data/full_repos/permissive/175100691/gpu/sim,data/full_repos/permissive/175100691/GPU.sv\n             GPU\n             GPU.v\n             GPU.sv\n             obj_dir/GPU\n             obj_dir/GPU.v\n             obj_dir/GPU.sv\n%Error: data/full_repos/permissive/175100691/gpu/sim/Main.v:86: Cannot find file containing module: \'MemArb\'\n    MemArb #(.COUNT(CORE_COUNT)) memArb(\n    ^~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module Main(
    input wire clock,
    input wire reset_n,

    input [31:0] h2f_value [0:CORE_COUNT-1],
    output [31:0] f2h_value [0:CORE_COUNT-1],

    output wire [29:0] sdram_address,
    input wire sdram_waitrequest,
    input wire [WORD_WIDTH-1:0] sdram_readdata,
    input wire sdram_readdatavalid,
    output wire sdram_read,
    output reg [WORD_WIDTH-1:0] sdram_writedata,
    output wire sdram_write
);

    localparam WORD_WIDTH = 32;
    localparam ADDRESS_WIDTH = 16;
    localparam SDRAM_ADDRESS_WIDTH = 24;
    localparam CORE_COUNT= 4;








    assign sdram_address = (sdram_gpu_address + 30'h3E000000) >> 2;
    reg [SDRAM_ADDRESS_WIDTH-1:0] sdram_gpu_address;

    generate
        genvar core;

        for (core = 0; core < CORE_COUNT; core++) begin
            GPU #(.WORD_WIDTH(WORD_WIDTH), .ADDRESS_WIDTH(ADDRESS_WIDTH))
                gpu(
                    .clock(clock),







                    .h2f_value(h2f_value[core]),
                    .f2h_value(f2h_value[core]),

                    .sdram_address(core_sdram_gpu_address[core]),
                    .sdram_waitrequest(sdram_waitrequest),
                    .sdram_readdata(sdram_readdata),
                    .sdram_readdatavalid(sdram_readdatavalid),
                    .sdram_read(core_sdram_read[core]),
                    .sdram_writedata(core_sdram_writedata[core]),
                    .sdram_write(core_sdram_write[core]),

                    .mem_request(mem_request[core]),
                    .mem_authorized(mem_authorized[core])
                    );
        end
    endgenerate


    wire [SDRAM_ADDRESS_WIDTH-1:0] core_sdram_gpu_address [0:CORE_COUNT-1];
    wire [CORE_COUNT-1:0] core_sdram_read;
    wire [CORE_COUNT-1:0] core_sdram_write;
    wire [WORD_WIDTH-1:0] core_sdram_writedata [0:CORE_COUNT-1];

    assign sdram_read = |core_sdram_read;
    assign sdram_write = |core_sdram_write;

    always @(*) begin
        sdram_writedata = {WORD_WIDTH{1'b0}};
        sdram_gpu_address = {SDRAM_ADDRESS_WIDTH{1'b0}};

        for (core = 0; core < CORE_COUNT; core++) begin
            sdram_writedata = sdram_writedata | core_sdram_writedata[core];
            sdram_gpu_address = sdram_gpu_address | core_sdram_gpu_address[core];
        end
    end


    wire [CORE_COUNT-1:0] mem_request;
    wire [CORE_COUNT-1:0] mem_authorized;
    MemArb #(.COUNT(CORE_COUNT)) memArb(
        .clock(clock),
        .reset_n(reset_n),
        .request(mem_request),
        .authorized(mem_authorized));

endmodule
module Main(
    input wire clock,
    input wire reset_n,

    input [31:0] h2f_value [0:CORE_COUNT-1],
    output [31:0] f2h_value [0:CORE_COUNT-1],

    output wire [29:0] sdram_address,
    input wire sdram_waitrequest,
    input wire [WORD_WIDTH-1:0] sdram_readdata,
    input wire sdram_readdatavalid,
    output wire sdram_read,
    output reg [WORD_WIDTH-1:0] sdram_writedata,
    output wire sdram_write
);


    localparam WORD_WIDTH = 32;
    localparam ADDRESS_WIDTH = 16;
    localparam SDRAM_ADDRESS_WIDTH = 24;
    localparam CORE_COUNT= 4;








    assign sdram_address = (sdram_gpu_address + 30'h3E000000) >> 2;
    reg [SDRAM_ADDRESS_WIDTH-1:0] sdram_gpu_address;

    generate
        genvar core;

        for (core = 0; core < CORE_COUNT; core++) begin
            GPU #(.WORD_WIDTH(WORD_WIDTH), .ADDRESS_WIDTH(ADDRESS_WIDTH))
                gpu(
                    .clock(clock),







                    .h2f_value(h2f_value[core]),
                    .f2h_value(f2h_value[core]),

                    .sdram_address(core_sdram_gpu_address[core]),
                    .sdram_waitrequest(sdram_waitrequest),
                    .sdram_readdata(sdram_readdata),
                    .sdram_readdatavalid(sdram_readdatavalid),
                    .sdram_read(core_sdram_read[core]),
                    .sdram_writedata(core_sdram_writedata[core]),
                    .sdram_write(core_sdram_write[core]),

                    .mem_request(mem_request[core]),
                    .mem_authorized(mem_authorized[core])
                    );
        end
    endgenerate


    wire [SDRAM_ADDRESS_WIDTH-1:0] core_sdram_gpu_address [0:CORE_COUNT-1];
    wire [CORE_COUNT-1:0] core_sdram_read;
    wire [CORE_COUNT-1:0] core_sdram_write;
    wire [WORD_WIDTH-1:0] core_sdram_writedata [0:CORE_COUNT-1];

    assign sdram_read = |core_sdram_read;
    assign sdram_write = |core_sdram_write;

    always @(*) begin
        sdram_writedata = {WORD_WIDTH{1'b0}};
        sdram_gpu_address = {SDRAM_ADDRESS_WIDTH{1'b0}};

        for (core = 0; core < CORE_COUNT; core++) begin
            sdram_writedata = sdram_writedata | core_sdram_writedata[core];
            sdram_gpu_address = sdram_gpu_address | core_sdram_gpu_address[core];
        end
    end


    wire [CORE_COUNT-1:0] mem_request;
    wire [CORE_COUNT-1:0] mem_authorized;
    MemArb #(.COUNT(CORE_COUNT)) memArb(
        .clock(clock),
        .reset_n(reset_n),
        .request(mem_request),
        .authorized(mem_authorized));

endmodule