data/full_repos/permissive/14636651/InstructionMemory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/14636651/InstructionMemory.v:25: Bit extraction of array[63:0] requires 6 bit index, not 16 bits.\n                                                                          : ... In instance InstructionMemory\n  dbus = mem[abus];\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module InstructionMemory(input [15:0] abus, output reg [15:0] dbus);
	reg [15:0] mem [0:63];
	
	initial
	begin
		mem[0] = 16'hC00A;
		mem[1] = 16'h2000;
		mem[2] = 16'hC003;
		mem[3] = 16'h2001;
		mem[4] = 16'hC001;
		mem[5] = 16'h2002;
		mem[6] = 16'h0000;
		mem[7] = 16'h4002;
		mem[8] = 16'h2000;
		mem[9] = 16'h0001;
		mem[10] = 16'h6002;
		mem[11] = 16'h2001;
		mem[12] = 16'hA00E;
		mem[13] = 16'h8006;
		mem[14] = 16'hE000;
	end
	
	always@(abus)
	begin
		dbus = mem[abus];
	end
endmodule
module InstructionMemory(input [15:0] abus, output reg [15:0] dbus);

	reg [15:0] mem [0:63];
	
	initial
	begin
		mem[0] = 16'hC00A;
		mem[1] = 16'h2000;
		mem[2] = 16'hC003;
		mem[3] = 16'h2001;
		mem[4] = 16'hC001;
		mem[5] = 16'h2002;
		mem[6] = 16'h0000;
		mem[7] = 16'h4002;
		mem[8] = 16'h2000;
		mem[9] = 16'h0001;
		mem[10] = 16'h6002;
		mem[11] = 16'h2001;
		mem[12] = 16'hA00E;
		mem[13] = 16'h8006;
		mem[14] = 16'hE000;
	end
	
	always@(abus)
	begin
		dbus = mem[abus];
	end
endmodule