data/full_repos/permissive/16157344/uart_tx_TB.v
 line:45: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/16157344/uart_tx_TB.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #50 rst = 0;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/16157344/uart_tx_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n   #1450 enable = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/16157344/uart_tx_TB.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #50 enable = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/16157344/uart_tx_TB.v:21: Unsupported: Ignoring delay on this delayed statement.\n   #1099950 enable = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/16157344/uart_tx_TB.v:23: Unsupported: Ignoring delay on this delayed statement.\n   #50 enable = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/16157344/uart_tx_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n   #1099950 enable = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/16157344/uart_tx_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #50 enable = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/16157344/uart_tx_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #1099950 enable = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/16157344/uart_tx_TB.v:29: Unsupported: Ignoring delay on this delayed statement.\n   #50 enable = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/16157344/uart_tx_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/16157344/uart_tx_TB.v:38: Unsupported: Ignoring delay on this delayed statement.\n     #10;\n     ^\n%Error: data/full_repos/permissive/16157344/uart_tx_TB.v:43: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("uart_tx_TB.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/16157344/uart_tx_TB.v:44: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(-1, uut);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/16157344/uart_tx_TB.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #4000000 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_tx_TB;
	reg clk, rst, enable;
	reg [7:0] data_o_bus;
	wire isDone, bit_out;

	uart_tx uut (.clk(clk), .rst(rst), .enable(enable),
							 .data_o_bus(data_o_bus), .isDone(isDone), .bit_out(bit_out));

	initial
		begin
			clk = 0;
			rst = 1;
			enable = 0;
			data_o_bus = 8'b0;
			#50 rst = 0;
			#1450 enable = 1;
			data_o_bus = 'h48;
			#50 enable = 0;
			#1099950 enable = 1;
			data_o_bus = 'h6F;
			#50 enable = 0;
			#1099950 enable = 1;
			data_o_bus = 'h6C;
			#50 enable = 0;
			#1099950 enable = 1;
			data_o_bus = 'h61;
			#50 enable = 0;
		end

	initial
		begin
			forever
				begin
					clk = 0;
					#10 clk = 1;
					#10;
				end
		end
	
	initial begin: TEST_CASE
		$dumpfile("uart_tx_TB.vcd");
		$dumpvars(-1, uut);
		#4000000 $finish;
	end  
endmodule
module uart_tx_TB;

	reg clk, rst, enable;
	reg [7:0] data_o_bus;
	wire isDone, bit_out;

	uart_tx uut (.clk(clk), .rst(rst), .enable(enable),
							 .data_o_bus(data_o_bus), .isDone(isDone), .bit_out(bit_out));

	initial
		begin
			clk = 0;
			rst = 1;
			enable = 0;
			data_o_bus = 8'b0;
			#50 rst = 0;
			#1450 enable = 1;
			data_o_bus = 'h48;
			#50 enable = 0;
			#1099950 enable = 1;
			data_o_bus = 'h6F;
			#50 enable = 0;
			#1099950 enable = 1;
			data_o_bus = 'h6C;
			#50 enable = 0;
			#1099950 enable = 1;
			data_o_bus = 'h61;
			#50 enable = 0;
		end

	initial
		begin
			forever
				begin
					clk = 0;
					#10 clk = 1;
					#10;
				end
		end
	
	initial begin: TEST_CASE
		$dumpfile("uart_tx_TB.vcd");
		$dumpvars(-1, uut);
		#4000000 $finish;
	end  
endmodule