data/full_repos/permissive/20101677/Coprocessor.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/20101677/Coprocessor.v:50: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'IntCause\' generates 2 bits.\n                                                                    : ... In instance Coprocessor\n            register[13] <= IntCause;\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Coprocessor(
    input clk,
    input rst,
    input [4:0] reg_R_addr,
    input [4:0] reg_W_addr,
    input [31:0] wdata,
    input [31:0] pc_i,
    input reg_we,
    input EPCWrite,
    input CauseWrite,
    input [1:0] IntCause,
    output [31:0] rdata,
    output [31:0] epc_o
    );

reg [31:0] register[12:14];
integer i;

assign rdata = register[reg_R_addr];
assign epc_o = register[14];

always @(posedge clk or posedge rst)
    if (rst == 1)begin
        for (i=12;i<14;i=i+1)
            register[i] <= 0;
    end else begin
        if (reg_we)
            register[reg_W_addr] <= wdata;
        if (EPCWrite == 1)
            register[14] <= pc_i;
        if (CauseWrite == 1)
            register[13] <= IntCause;
    end

endmodule
module Coprocessor(
    input clk,
    input rst,
    input [4:0] reg_R_addr,
    input [4:0] reg_W_addr,
    input [31:0] wdata,
    input [31:0] pc_i,
    input reg_we,
    input EPCWrite,
    input CauseWrite,
    input [1:0] IntCause,
    output [31:0] rdata,
    output [31:0] epc_o
    );


reg [31:0] register[12:14];
integer i;

assign rdata = register[reg_R_addr];
assign epc_o = register[14];

always @(posedge clk or posedge rst)
    if (rst == 1)begin
        for (i=12;i<14;i=i+1)
            register[i] <= 0;
    end else begin
        if (reg_we)
            register[reg_W_addr] <= wdata;
        if (EPCWrite == 1)
            register[14] <= pc_i;
        if (CauseWrite == 1)
            register[13] <= IntCause;
    end

endmodule