data/full_repos/permissive/185628295/hdl/clip.v
data/verilator_xmls/2d29e9e7-980a-47b2-8c67-9e2fb623a8a6.xml
module clip
  #(parameter
    WIDTH_NB    = 3,
    IMG_WIDTH   = 8,

    MEM_AWIDTH  = 12,
    MEM_DEPTH   = 1<<MEM_AWIDTH)
   (input  wire                     clk,
    input  wire                     rst,

    input  wire [MEM_AWIDTH-1:0]    cfg_delay,
    input  wire                     cfg_set,

    input  wire [IMG_WIDTH-1:0]     up_data,
    input  wire                     up_val,

    output reg  [IMG_WIDTH-1:0]     dn_data,
    output wire                     dn_val
);








    reg  [MEM_AWIDTH-1:0]   cfg_delay_r;
    reg  [MEM_AWIDTH-1:0]   cfg_clip;
    reg                     cfg_set_r;

    reg  [MEM_AWIDTH-1:0]   row_cnt;
    reg                     row_mask;
    reg                     dn_val_i;







    always @(posedge clk)
        if (cfg_set) begin
            cfg_delay_r <= (cfg_delay - {{MEM_AWIDTH-1{1'b0}}, 1'b1});
            cfg_clip    <= (cfg_delay - WIDTH_NB[MEM_AWIDTH-1:0]);
        end


    always @(posedge clk) begin
        cfg_set_r <= 1'b0;

        if (cfg_set) begin
            cfg_set_r <= 1'b1;
        end
    end




    always @(posedge clk)
        if (cfg_set_r) begin
            row_cnt <= 'b0;
        end
        else if (up_val) begin
            row_cnt <= row_cnt + {{MEM_AWIDTH-1{1'b0}}, 1'b1};

            if (row_cnt >= cfg_delay_r) begin
                row_cnt <= 'b0;
            end
        end



    always @(posedge clk) begin
        row_mask <= 1'b1;

        if (row_cnt > cfg_clip) begin
            row_mask <= 1'b0;
        end
    end




    always @(posedge clk)
        dn_data <= up_data;


    always @(posedge clk)
        if (rst)    dn_val_i <= 1'b0;
        else        dn_val_i <= up_val;



    assign dn_val = dn_val_i & row_mask;



endmodule
module clip
  #(parameter
    WIDTH_NB    = 3,
    IMG_WIDTH   = 8,

    MEM_AWIDTH  = 12,
    MEM_DEPTH   = 1<<MEM_AWIDTH)
   (input  wire                     clk,
    input  wire                     rst,

    input  wire [MEM_AWIDTH-1:0]    cfg_delay,
    input  wire                     cfg_set,

    input  wire [IMG_WIDTH-1:0]     up_data,
    input  wire                     up_val,

    output reg  [IMG_WIDTH-1:0]     dn_data,
    output wire                     dn_val
);









    reg  [MEM_AWIDTH-1:0]   cfg_delay_r;
    reg  [MEM_AWIDTH-1:0]   cfg_clip;
    reg                     cfg_set_r;

    reg  [MEM_AWIDTH-1:0]   row_cnt;
    reg                     row_mask;
    reg                     dn_val_i;







    always @(posedge clk)
        if (cfg_set) begin
            cfg_delay_r <= (cfg_delay - {{MEM_AWIDTH-1{1'b0}}, 1'b1});
            cfg_clip    <= (cfg_delay - WIDTH_NB[MEM_AWIDTH-1:0]);
        end


    always @(posedge clk) begin
        cfg_set_r <= 1'b0;

        if (cfg_set) begin
            cfg_set_r <= 1'b1;
        end
    end




    always @(posedge clk)
        if (cfg_set_r) begin
            row_cnt <= 'b0;
        end
        else if (up_val) begin
            row_cnt <= row_cnt + {{MEM_AWIDTH-1{1'b0}}, 1'b1};

            if (row_cnt >= cfg_delay_r) begin
                row_cnt <= 'b0;
            end
        end



    always @(posedge clk) begin
        row_mask <= 1'b1;

        if (row_cnt > cfg_clip) begin
            row_mask <= 1'b0;
        end
    end




    always @(posedge clk)
        dn_data <= up_data;


    always @(posedge clk)
        if (rst)    dn_val_i <= 1'b0;
        else        dn_val_i <= up_val;



    assign dn_val = dn_val_i & row_mask;



endmodule