data/full_repos/permissive/125742950/WavetableRAM.v
data/verilator_xmls/6cbcac0e-4d89-4b88-a0e0-c7a3adc7de7f.xml
module WavetableRAM(CLK, WE, Address, Data, Indices, Waveforms);
    input CLK;
    input WE;
    input[7:0] Address;
    input[5:0] Data;
    input[23:0] Indices;
    output[23:0] Waveforms;
    
    reg[3:0] BankWriteEnable;
    wire[5:0] Index[0:3];
    
    assign Index[0] = Indices[5:0];
    assign Index[1] = Indices[11:6];
    assign Index[2] = Indices[17:12];
    assign Index[3] = Indices[23:18];
    

    always @ (Address[7:6] or WE) begin
        case(Address[7:6])
            2'b00: BankWriteEnable = 4'b0001 & {4{WE}};
            2'b01: BankWriteEnable = 4'b0010 & {4{WE}};
            2'b10: BankWriteEnable = 4'b0100 & {4{WE}};
            2'b11: BankWriteEnable = 4'b1000 & {4{WE}};
        endcase
    end
    
    MemoryBank Bank0(.CLK(CLK), .WE(BankWriteEnable[0]), .Address(Address[5:0]), .Index(Index[0]), .DataIn(Data), .DataOut(Waveforms[5:0]));
    MemoryBank Bank1(.CLK(CLK), .WE(BankWriteEnable[1]), .Address(Address[5:0]), .Index(Index[1]), .DataIn(Data), .DataOut(Waveforms[11:6]));
    MemoryBank Bank2(.CLK(CLK), .WE(BankWriteEnable[2]), .Address(Address[5:0]), .Index(Index[2]), .DataIn(Data), .DataOut(Waveforms[17:12]));
    MemoryBank Bank3(.CLK(CLK), .WE(BankWriteEnable[3]), .Address(Address[5:0]), .Index(Index[3]), .DataIn(Data), .DataOut(Waveforms[23:18]));

endmodule
module WavetableRAM(CLK, WE, Address, Data, Indices, Waveforms);

    input CLK;
    input WE;
    input[7:0] Address;
    input[5:0] Data;
    input[23:0] Indices;
    output[23:0] Waveforms;
    
    reg[3:0] BankWriteEnable;
    wire[5:0] Index[0:3];
    
    assign Index[0] = Indices[5:0];
    assign Index[1] = Indices[11:6];
    assign Index[2] = Indices[17:12];
    assign Index[3] = Indices[23:18];
    

    always @ (Address[7:6] or WE) begin
        case(Address[7:6])
            2'b00: BankWriteEnable = 4'b0001 & {4{WE}};
            2'b01: BankWriteEnable = 4'b0010 & {4{WE}};
            2'b10: BankWriteEnable = 4'b0100 & {4{WE}};
            2'b11: BankWriteEnable = 4'b1000 & {4{WE}};
        endcase
    end
    
    MemoryBank Bank0(.CLK(CLK), .WE(BankWriteEnable[0]), .Address(Address[5:0]), .Index(Index[0]), .DataIn(Data), .DataOut(Waveforms[5:0]));
    MemoryBank Bank1(.CLK(CLK), .WE(BankWriteEnable[1]), .Address(Address[5:0]), .Index(Index[1]), .DataIn(Data), .DataOut(Waveforms[11:6]));
    MemoryBank Bank2(.CLK(CLK), .WE(BankWriteEnable[2]), .Address(Address[5:0]), .Index(Index[2]), .DataIn(Data), .DataOut(Waveforms[17:12]));
    MemoryBank Bank3(.CLK(CLK), .WE(BankWriteEnable[3]), .Address(Address[5:0]), .Index(Index[3]), .DataIn(Data), .DataOut(Waveforms[23:18]));

endmodule