data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/mojo_top_0.v
 line:64: before: "="
1: b'%Error: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/mojo_top_0.v:38: Cannot find file containing module: \'reset_conditioner_1\'\n  reset_conditioner_1 reset_cond (\n  ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/reset_conditioner_1\n             data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/reset_conditioner_1.v\n             data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog,data/full_repos/permissive/151548608/reset_conditioner_1.sv\n             reset_conditioner_1\n             reset_conditioner_1.v\n             reset_conditioner_1.sv\n             obj_dir/reset_conditioner_1\n             obj_dir/reset_conditioner_1.v\n             obj_dir/reset_conditioner_1.sv\n%Error: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/mojo_top_0.v:44: Cannot find file containing module: \'counter_2\'\n  counter_2 slowclock (\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/mojo_top_0.v:52: Cannot find file containing module: \'led_matrix_3\'\n  led_matrix_3 ld (\n  ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/mojo_top_0.v:65: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                            : ... In instance mojo_top_0\n  reg [15:0] M_cSignal_d, M_cSignal_q = 1\'h0;\n                                        ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/mojo_top_0.v:66: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                            : ... In instance mojo_top_0\n  reg [15:0] M_aSignal_d, M_aSignal_q = 1\'h0;\n                                        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/mojo_top_0.v:97: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                            : ... In instance mojo_top_0\n      M_cSignal_q <= 1\'h0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/151548608/testLEDMatrix/work/planAhead/testLEDMatrix/testLEDMatrix.srcs/sources_1/imports/verilog/mojo_top_0.v:105: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                             : ... In instance mojo_top_0\n      M_aSignal_q <= 1\'h0;\n                  ^~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module mojo_top_0 (
    input clk,
    input rst_n,
    output reg [7:0] led,
    input cclk,
    output reg spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,
    output reg [3:0] spi_channel,
    input avr_tx,
    output reg avr_rx,
    input avr_rx_busy,
    output reg [15:0] a,
    output reg [15:0] c
  );
  
  
  
  reg rst;
  
  reg [255:0] led_pattern;
  
  reg [15:0] tempRows;
  
  reg [15:0] tempColumns;
  
  integer i;
  
  wire [1-1:0] M_reset_cond_out;
  reg [1-1:0] M_reset_cond_in;
  reset_conditioner_1 reset_cond (
    .clk(clk),
    .in(M_reset_cond_in),
    .out(M_reset_cond_out)
  );
  wire [1-1:0] M_slowclock_value;
  counter_2 slowclock (
    .clk(clk),
    .rst(rst),
    .value(M_slowclock_value)
  );
  wire [16-1:0] M_ld_a;
  wire [16-1:0] M_ld_c;
  reg [256-1:0] M_ld_pattern;
  led_matrix_3 ld (
    .clk(clk),
    .rst(rst),
    .pattern(M_ld_pattern),
    .a(M_ld_a),
    .c(M_ld_c)
  );
  
  localparam ONE_state = 2'd0;
  localparam TWO_state = 2'd1;
  localparam THREE_state = 2'd2;
  
  reg [1:0] M_state_d, M_state_q = ONE_state;
  reg [15:0] M_cSignal_d, M_cSignal_q = 1'h0;
  reg [15:0] M_aSignal_d, M_aSignal_q = 1'h0;
  
  always @* begin
    M_reset_cond_in = ~rst_n;
    rst = M_reset_cond_out;
    led = 8'h00;
    spi_miso = 1'bz;
    spi_channel = 4'bzzzz;
    avr_rx = 1'bz;
    M_ld_pattern[240+15-:16] = 16'h9fff;
    M_ld_pattern[224+15-:16] = 16'h9fff;
    M_ld_pattern[208+15-:16] = 16'h9fff;
    M_ld_pattern[192+15-:16] = 16'h9fff;
    M_ld_pattern[176+15-:16] = 16'h9fff;
    M_ld_pattern[160+15-:16] = 16'h9fff;
    M_ld_pattern[144+15-:16] = 16'h9fff;
    M_ld_pattern[128+15-:16] = 16'h9fff;
    M_ld_pattern[112+15-:16] = 16'h6fff;
    M_ld_pattern[96+15-:16] = 16'h77ff;
    M_ld_pattern[80+15-:16] = 16'h7bff;
    M_ld_pattern[64+15-:16] = 16'h7dff;
    M_ld_pattern[48+15-:16] = 16'h7eff;
    M_ld_pattern[32+15-:16] = 16'h7f7f;
    M_ld_pattern[16+15-:16] = 16'h7fbf;
    M_ld_pattern[0+15-:16] = 16'h7fdf;
    a = M_ld_a;
    c = M_ld_c;
  end
  
  always @(posedge M_slowclock_value) begin
    if (rst == 1'b1) begin
      M_cSignal_q <= 1'h0;
    end else begin
      M_cSignal_q <= M_cSignal_d;
    end
    
    M_state_q <= M_state_d;
    
    if (rst == 1'b1) begin
      M_aSignal_q <= 1'h0;
    end else begin
      M_aSignal_q <= M_aSignal_d;
    end
  end
  
endmodule
module mojo_top_0 (
    input clk,
    input rst_n,
    output reg [7:0] led,
    input cclk,
    output reg spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,
    output reg [3:0] spi_channel,
    input avr_tx,
    output reg avr_rx,
    input avr_rx_busy,
    output reg [15:0] a,
    output reg [15:0] c
  );

  
  
  
  reg rst;
  
  reg [255:0] led_pattern;
  
  reg [15:0] tempRows;
  
  reg [15:0] tempColumns;
  
  integer i;
  
  wire [1-1:0] M_reset_cond_out;
  reg [1-1:0] M_reset_cond_in;
  reset_conditioner_1 reset_cond (
    .clk(clk),
    .in(M_reset_cond_in),
    .out(M_reset_cond_out)
  );
  wire [1-1:0] M_slowclock_value;
  counter_2 slowclock (
    .clk(clk),
    .rst(rst),
    .value(M_slowclock_value)
  );
  wire [16-1:0] M_ld_a;
  wire [16-1:0] M_ld_c;
  reg [256-1:0] M_ld_pattern;
  led_matrix_3 ld (
    .clk(clk),
    .rst(rst),
    .pattern(M_ld_pattern),
    .a(M_ld_a),
    .c(M_ld_c)
  );
  
  localparam ONE_state = 2'd0;
  localparam TWO_state = 2'd1;
  localparam THREE_state = 2'd2;
  
  reg [1:0] M_state_d, M_state_q = ONE_state;
  reg [15:0] M_cSignal_d, M_cSignal_q = 1'h0;
  reg [15:0] M_aSignal_d, M_aSignal_q = 1'h0;
  
  always @* begin
    M_reset_cond_in = ~rst_n;
    rst = M_reset_cond_out;
    led = 8'h00;
    spi_miso = 1'bz;
    spi_channel = 4'bzzzz;
    avr_rx = 1'bz;
    M_ld_pattern[240+15-:16] = 16'h9fff;
    M_ld_pattern[224+15-:16] = 16'h9fff;
    M_ld_pattern[208+15-:16] = 16'h9fff;
    M_ld_pattern[192+15-:16] = 16'h9fff;
    M_ld_pattern[176+15-:16] = 16'h9fff;
    M_ld_pattern[160+15-:16] = 16'h9fff;
    M_ld_pattern[144+15-:16] = 16'h9fff;
    M_ld_pattern[128+15-:16] = 16'h9fff;
    M_ld_pattern[112+15-:16] = 16'h6fff;
    M_ld_pattern[96+15-:16] = 16'h77ff;
    M_ld_pattern[80+15-:16] = 16'h7bff;
    M_ld_pattern[64+15-:16] = 16'h7dff;
    M_ld_pattern[48+15-:16] = 16'h7eff;
    M_ld_pattern[32+15-:16] = 16'h7f7f;
    M_ld_pattern[16+15-:16] = 16'h7fbf;
    M_ld_pattern[0+15-:16] = 16'h7fdf;
    a = M_ld_a;
    c = M_ld_c;
  end
  
  always @(posedge M_slowclock_value) begin
    if (rst == 1'b1) begin
      M_cSignal_q <= 1'h0;
    end else begin
      M_cSignal_q <= M_cSignal_d;
    end
    
    M_state_q <= M_state_d;
    
    if (rst == 1'b1) begin
      M_aSignal_q <= 1'h0;
    end else begin
      M_aSignal_q <= M_aSignal_d;
    end
  end
  
endmodule