data/full_repos/permissive/117880471/HW1/df_comparator_8b.v
 line:18: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/df_comparator_8b.v:13: Unsupported: Ignoring delay on this delayed statement.\n #00 A = 8\'b0000_0000; B = 8\'b0000_0000; s = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/df_comparator_8b.v:14: Unsupported: Ignoring delay on this delayed statement.\n #20 A = 8\'b0000_0001; B = 8\'b0000_0000; s = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/df_comparator_8b.v:15: Unsupported: Ignoring delay on this delayed statement.\n #20 A = 8\'b0000_0000; B = 8\'b0001_0000; s = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/df_comparator_8b.v:16: Unsupported: Ignoring delay on this delayed statement.\n #20 A = 8\'b1100_0000; B = 8\'b0100_0000; s = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/df_comparator_8b.v:17: Unsupported: Ignoring delay on this delayed statement.\n #20 A = 8\'b0001_0000; B = 8\'b1000_0000; s = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW1/df_comparator_8b.v:18: Unsupported: Ignoring delay on this delayed statement.\n #20 $stop;\n ^\n%Error: data/full_repos/permissive/117880471/HW1/df_comparator_8b.v:23: Unsupported or unknown PLI call: $monitor\n $monitor("time=%3d, AeqB=%b, AgtB=%b, AltB=%b, A=%b, B=%b. s=%b", $time, AeqB, AgtB, AltB, A, B, s);\n ^~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW1/df_comparator_8b.v:28: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("df_comparator_8b.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW1/df_comparator_8b.v:29: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module df_comparator_8b(AeqB, AgtB, AltB, A, B, s);

output wire AeqB, AgtB, AltB;
input wire [7:0] A, B;
input wire s;


wire sign_AeqB, sign_AgtB, sign_AltB; 
wire unsign_AeqB, unsign_AgtB, unsign_AltB;

wire signed [7:0] A_s, B_s;

assign A_s = A;
assign B_s = B;


assign unsign_AeqB = A==B?1'b1:1'b0;
assign unsign_AgtB = A>B?1'b1:1'b0;
assign unsign_AltB = A<B?1'b1:1'b0;

assign sign_AeqB = A_s==B_s?1'b1:1'b0;
assign sign_AgtB = A_s>B_s?1'b1:1'b0;
assign sign_AltB = A_s<B_s?1'b1:1'b0;

assign AeqB = (s&sign_AeqB)|((~s)&unsign_AeqB); 
assign AgtB = (s&sign_AgtB)|((~s)&unsign_AgtB); 
assign AltB = (s&sign_AltB)|((~s)&unsign_AltB); 

endmodule
module df_comparator_8b(AeqB, AgtB, AltB, A, B, s);


output wire AeqB, AgtB, AltB;
input wire [7:0] A, B;
input wire s;


wire sign_AeqB, sign_AgtB, sign_AltB; 
wire unsign_AeqB, unsign_AgtB, unsign_AltB;

wire signed [7:0] A_s, B_s;

assign A_s = A;
assign B_s = B;


assign unsign_AeqB = A==B?1'b1:1'b0;
assign unsign_AgtB = A>B?1'b1:1'b0;
assign unsign_AltB = A<B?1'b1:1'b0;

assign sign_AeqB = A_s==B_s?1'b1:1'b0;
assign sign_AgtB = A_s>B_s?1'b1:1'b0;
assign sign_AltB = A_s<B_s?1'b1:1'b0;

assign AeqB = (s&sign_AeqB)|((~s)&unsign_AeqB); 
assign AgtB = (s&sign_AgtB)|((~s)&unsign_AgtB); 
assign AltB = (s&sign_AltB)|((~s)&unsign_AltB); 

endmodule