data/full_repos/permissive/146689564/whac_a_mole_v3.v
 line:77: before: "."
1: b'%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:708: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'frame\' generates 4 bits.\n                                                                         : ... In instance whac_a_mole_v3.u1\nassign en = ((q == frame) & enable) ? 1:0;  \n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:716: Operator EQ expects 5 bits on the RHS, but RHS\'s VARREF \'frame\' generates 4 bits.\n                                                                         : ... In instance whac_a_mole_v3.u1\n    if(q == frame)  \n         ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:440: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_1\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d0: y_posi = mole_1;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:441: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_2\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d1: y_posi = mole_2;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:442: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_3\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d2: y_posi = mole_3;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:443: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_4\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      2\'d3: y_posi = mole_4;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:444: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_1\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n    default: y_posi = mole_1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:447: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'mole_1\' generates 8 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  else y_posi = mole_1;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:466: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n       mole_1 <= M_Y_S;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:467: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n      mole_2 <= M_Y_S;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:468: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     mole_3 <= M_Y_S;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:469: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     mole_4 <= M_Y_S;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:475: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S1\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence1 <= S1;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:476: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S2\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence2 <= S2;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:477: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S3\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence3 <= S3;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:478: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'S4\' generates 24 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n     sequence4 <= S4;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:492: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   score <= score + score_reg[0] + score_reg[1] + score_reg[2] + score_reg[3];\n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:501: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:496: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_1 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:509: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:504: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_2 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:517: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:512: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_3 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:525: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 == M_Y_E)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:520: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n  if(mole_4 == M_Y_S)begin\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:531: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:535: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:539: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:543: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:547: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:551: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:555: Operator GT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_E\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 > M_Y_E)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:559: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'M_Y_S\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 < M_Y_S)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:568: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h33\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_1 == 7\'d51) \n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:573: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h33\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_2 == 7\'d51)\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:578: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h34\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_3 < 7\'d52)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:583: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'7\'h34\' generates 7 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   if(mole_4 < 7\'d52)\n             ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:640: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   x <= x_posi + counter[5:3];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:641: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   y <= y_posi + counter [2:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:653: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   x <= x_posi + counter[3:2];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:654: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   y <= y_posi + counter [1:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:669: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   x <= x_posi + counter[2:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:670: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 5 bits.\n                                                                         : ... In instance whac_a_mole_v3.d0\n   y <= y_posi + counter[7:3];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:230: Operator CASE expects 2 bits on the Case expression, but Case expression\'s VARREF \'difficulty\' generates 1 bits.\n                                                                         : ... In instance whac_a_mole_v3.c0\n  case(difficulty)\n  ^~~~\n%Error: data/full_repos/permissive/146689564/whac_a_mole_v3.v:60: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146689564,data/full_repos/permissive/146689564/vga_adapter\n             data/full_repos/permissive/146689564,data/full_repos/permissive/146689564/vga_adapter.v\n             data/full_repos/permissive/146689564,data/full_repos/permissive/146689564/vga_adapter.sv\n             vga_adapter\n             vga_adapter.v\n             vga_adapter.sv\n             obj_dir/vga_adapter\n             obj_dir/vga_adapter.v\n             obj_dir/vga_adapter.sv\n%Error: data/full_repos/permissive/146689564/whac_a_mole_v3.v:88: Cannot find file containing module: \'keyboard_press_driver\'\n keyboard_press_driver KEYBOARD(\n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/146689564/whac_a_mole_v3.v:139: Input port connection \'difficulty\' expects 1 bits on the pin connection, but pin connection\'s SEL generates 2 bits.\n                                                                         : ... In instance whac_a_mole_v3\n   .difficulty(SW[9:8]),\n    ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 48 warning(s)\n'
module whac_a_mole_v3(
		CLOCK_50,

      KEY,
      SW,
		HEX0,
		HEX1,
		
		PS2_DAT,
		PS2_CLK,
		


		VGA_CLK,
		VGA_HS,
		VGA_VS,
		VGA_BLANK_N,
		VGA_SYNC_N,
		VGA_R,
		VGA_G,
		VGA_B
	);
	

	input	CLOCK_50;
	input   [9:0]   SW;
	input   [3:0]   KEY;
	output [6:0] HEX0, HEX1;
	
	input PS2_DAT;
	input PS2_CLK;
	

	output	VGA_CLK;
	output	VGA_HS;
	output	VGA_VS;
	output	VGA_BLANK_N;
	output	VGA_SYNC_N;
	output	[9:0]	VGA_R;
	output	[9:0]	VGA_G;
	output	[9:0]	VGA_B;
	
	

	wire resetn;
	assign resetn = SW[0];
	wire go;
	assign go = SW[1];
	

	wire [7:0] x;
	wire [6:0] y;
	wire writeEn;
	wire [2:0] rgb;




	vga_adapter VGA(
			.resetn(resetn),
			.clock(CLOCK_50),
			.colour(rgb),
			.x(x),
			.y(y),
			.plot(writeEn),

			.VGA_R(VGA_R),
			.VGA_G(VGA_G),
			.VGA_B(VGA_B),
			.VGA_HS(VGA_HS),
			.VGA_VS(VGA_VS),
			.VGA_BLANK(VGA_BLANK_N),
			.VGA_SYNC(VGA_SYNC_N),
			.VGA_CLK(VGA_CLK)
		);
		defparam VGA.RESOLUTION = "160x120";
		defparam VGA.MONOCHROME = "FALSE";
		defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
		defparam VGA.BACKGROUND_IMAGE = "black.mif";
			
	

   wire valid, makeBreak;
	wire [7:0]outCode;
 
	 
	keyboard_press_driver KEYBOARD(
		.CLOCK_50(CLOCK_50),
		.valid(valid),
		.makeBreak(makeBreak),
		.outCode(outCode[7:0]),
		.PS2DAT(PS2_DAT),
		.PS2CLK(PS2_CLK),
		.reset(~resetn)
		);
	
	wire  draw_mole, draw_hammer, clear, erase, update, count, m, f_en, f;
	assign writeEn = draw_mole || draw_hammer || clear || erase; 
	
	wire move;
	wire [1:0] mole_id;
	wire [5:0]current_state;
	wire [3:0] frame;
	wire [7:0] score;


        datapath d0(
			.resetn(resetn),
		   .clk(CLOCK_50),
			.h(KEY[3:0]),
			.update(update),
			.erase(erase),
			.clear(clear),
			.valid(valid),
			.outCode(outCode[7:0]),

			.draw_mole(draw_mole),
			.draw_hammer(draw_hammer),
			.mole_id(mole_id),
	

			.m(m),
			.x(x),
			.y(y),
			.move(move),
			.rgb(rgb),
			.score(score[7:0])

		);


        control c0(
			.resetn(resetn),
		   .clk(CLOCK_50),
			.go(go),
			.move(move),
			.count(count),
			.difficulty(SW[9:8]),
			
			.frame(frame),
			.f(f),
			.m(m),
			.update(update),
			.mole_id(mole_id),
			.erase(erase),
			.clear(clear),
			.draw_mole(draw_mole),
			.draw_hammer(draw_hammer),
			.current_state(current_state)
		);



  delaycounter u0(
    .clock(CLOCK_50), 
    .resetn(count), 
    .enable(1'b1), 
    .en(f_en)
);

  framecounter u1(
    .clock(CLOCK_50),
    .resetn(count),
	 .frame(frame),
    .enable(f_en),
    .en(f)
);

hex_decoder h0(
	.hex_digit(score[3:0]),
	.segments(HEX0)
	);

hex_decoder h1(
	.hex_digit(score[7:4]),
	.segments(HEX1)
);


endmodule
module whac_a_mole_v3(
		CLOCK_50,

      KEY,
      SW,
		HEX0,
		HEX1,
		
		PS2_DAT,
		PS2_CLK,
		


		VGA_CLK,
		VGA_HS,
		VGA_VS,
		VGA_BLANK_N,
		VGA_SYNC_N,
		VGA_R,
		VGA_G,
		VGA_B
	);

	

	input	CLOCK_50;
	input   [9:0]   SW;
	input   [3:0]   KEY;
	output [6:0] HEX0, HEX1;
	
	input PS2_DAT;
	input PS2_CLK;
	

	output	VGA_CLK;
	output	VGA_HS;
	output	VGA_VS;
	output	VGA_BLANK_N;
	output	VGA_SYNC_N;
	output	[9:0]	VGA_R;
	output	[9:0]	VGA_G;
	output	[9:0]	VGA_B;
	
	

	wire resetn;
	assign resetn = SW[0];
	wire go;
	assign go = SW[1];
	

	wire [7:0] x;
	wire [6:0] y;
	wire writeEn;
	wire [2:0] rgb;




	vga_adapter VGA(
			.resetn(resetn),
			.clock(CLOCK_50),
			.colour(rgb),
			.x(x),
			.y(y),
			.plot(writeEn),

			.VGA_R(VGA_R),
			.VGA_G(VGA_G),
			.VGA_B(VGA_B),
			.VGA_HS(VGA_HS),
			.VGA_VS(VGA_VS),
			.VGA_BLANK(VGA_BLANK_N),
			.VGA_SYNC(VGA_SYNC_N),
			.VGA_CLK(VGA_CLK)
		);
		defparam VGA.RESOLUTION = "160x120";
		defparam VGA.MONOCHROME = "FALSE";
		defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
		defparam VGA.BACKGROUND_IMAGE = "black.mif";
			
	

   wire valid, makeBreak;
	wire [7:0]outCode;
 
	 
	keyboard_press_driver KEYBOARD(
		.CLOCK_50(CLOCK_50),
		.valid(valid),
		.makeBreak(makeBreak),
		.outCode(outCode[7:0]),
		.PS2DAT(PS2_DAT),
		.PS2CLK(PS2_CLK),
		.reset(~resetn)
		);
	
	wire  draw_mole, draw_hammer, clear, erase, update, count, m, f_en, f;
	assign writeEn = draw_mole || draw_hammer || clear || erase; 
	
	wire move;
	wire [1:0] mole_id;
	wire [5:0]current_state;
	wire [3:0] frame;
	wire [7:0] score;


        datapath d0(
			.resetn(resetn),
		   .clk(CLOCK_50),
			.h(KEY[3:0]),
			.update(update),
			.erase(erase),
			.clear(clear),
			.valid(valid),
			.outCode(outCode[7:0]),

			.draw_mole(draw_mole),
			.draw_hammer(draw_hammer),
			.mole_id(mole_id),
	

			.m(m),
			.x(x),
			.y(y),
			.move(move),
			.rgb(rgb),
			.score(score[7:0])

		);


        control c0(
			.resetn(resetn),
		   .clk(CLOCK_50),
			.go(go),
			.move(move),
			.count(count),
			.difficulty(SW[9:8]),
			
			.frame(frame),
			.f(f),
			.m(m),
			.update(update),
			.mole_id(mole_id),
			.erase(erase),
			.clear(clear),
			.draw_mole(draw_mole),
			.draw_hammer(draw_hammer),
			.current_state(current_state)
		);



  delaycounter u0(
    .clock(CLOCK_50), 
    .resetn(count), 
    .enable(1'b1), 
    .en(f_en)
);

  framecounter u1(
    .clock(CLOCK_50),
    .resetn(count),
	 .frame(frame),
    .enable(f_en),
    .en(f)
);

hex_decoder h0(
	.hex_digit(score[3:0]),
	.segments(HEX0)
	);

hex_decoder h1(
	.hex_digit(score[7:4]),
	.segments(HEX1)
);


endmodule