data/full_repos/permissive/167489907/Memory/RAM/RAM_64bit.v
 line:185: before: "."
data/verilator_xmls/ad4fab92-a57c-4e71-9602-c1ffe0c6842d.xml
module address_select(out, byte_offset);


	input [2:0] byte_offset;
	output reg [7:0] out;
	
	always @(byte_offset)
		case(byte_offset)
			3'h0: out <= 8'b00000000;
			3'h1: out <= 8'b00000001;
			3'h2: out <= 8'b00000011;
			3'h3: out <= 8'b00000111;
			3'h4: out <= 8'b00001111;
			3'h5: out <= 8'b00011111;
			3'h6: out <= 8'b00111111;
			3'h7: out <= 8'b01111111;
		endcase
endmodule
module address_select(out, byte_offset);



	input [2:0] byte_offset;
	output reg [7:0] out;
	
	always @(byte_offset)
		case(byte_offset)
			3'h0: out <= 8'b00000000;
			3'h1: out <= 8'b00000001;
			3'h2: out <= 8'b00000011;
			3'h3: out <= 8'b00000111;
			3'h4: out <= 8'b00001111;
			3'h5: out <= 8'b00011111;
			3'h6: out <= 8'b00111111;
			3'h7: out <= 8'b01111111;
		endcase
endmodule