data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v
 line:32: before: "("
1: b"%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:14: Unsupported or unknown PLI call: $anyseq\nreg  [31:0] rs1      = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:15: Unsupported or unknown PLI call: $anyseq\nreg  [31:0] rs2      = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:16: Unsupported or unknown PLI call: $anyseq\nreg  [ 1:0] shamt    = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:19: Unsupported or unknown PLI call: $anyseq\nreg         f_xy     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:20: Unsupported or unknown PLI call: $anyseq\nreg         f_x1     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:21: Unsupported or unknown PLI call: $anyseq\nreg         f_x2     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:22: Unsupported or unknown PLI call: $anyseq\nreg         f_x4     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:23: Unsupported or unknown PLI call: $anyseq\nreg         f_yx     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/xc_sha3/xc_sha3_ftb.v:32: syntax error, unexpected '(', expecting property\n    restrict(onehot <= 1);\n             ^~~~~~\n%Error: Exiting due to 9 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module fml_xc_sha3_checker (

input  wire [31:0] rs1      ,
input  wire [31:0] rs2      ,
input  wire [ 1:0] shamt    ,


input  wire        f_xy     ,
input  wire        f_x1     ,
input  wire        f_x2     ,
input  wire        f_x4     ,
input  wire        f_yx     ,

output reg  [31:0] result

);

wire [2:0] x = rs1[2:0];
wire [2:0] y = rs2[2:0];


always @(*) begin

    result = 0;

    if(f_xy) begin

        result = (((x)%5) + 5*((y)%5)) << shamt;

    end else if (f_x1) begin
        
        result = (((x+1)%5) + 5*((y)%5)) << shamt;

    end else if (f_x2) begin
        
        result = (((x+2)%5) + 5*((y)%5)) << shamt;

    end else if (f_x4) begin
        
        result = (((x+4)%5) + 5*((y)%5)) << shamt;

    end else if (f_yx) begin
        
        result = (((y)%5) + 5*((2*x+3*y)%5)) << shamt;

    end

end


endmodule
module fml_xc_sha3_checker (

input  wire [31:0] rs1      ,
input  wire [31:0] rs2      ,
input  wire [ 1:0] shamt    ,


input  wire        f_xy     ,
input  wire        f_x1     ,
input  wire        f_x2     ,
input  wire        f_x4     ,
input  wire        f_yx     ,

output reg  [31:0] result

);


wire [2:0] x = rs1[2:0];
wire [2:0] y = rs2[2:0];


always @(*) begin

    result = 0;

    if(f_xy) begin

        result = (((x)%5) + 5*((y)%5)) << shamt;

    end else if (f_x1) begin
        
        result = (((x+1)%5) + 5*((y)%5)) << shamt;

    end else if (f_x2) begin
        
        result = (((x+2)%5) + 5*((y)%5)) << shamt;

    end else if (f_x4) begin
        
        result = (((x+4)%5) + 5*((y)%5)) << shamt;

    end else if (f_yx) begin
        
        result = (((y)%5) + 5*((2*x+3*y)%5)) << shamt;

    end

end


endmodule