data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v
1: b'%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:2: Cannot find include file: def.v\n`include "def.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.v\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.sv\n             def.v\n             def.v.v\n             def.v.sv\n             obj_dir/def.v\n             obj_dir/def.v.v\n             obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:36: Define or directive not defined: \'`False\'\n                                                                             : ... Suggested alternative: \'`else\'\n  if (ce == `False) begin\n            ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:36: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if (ce == `False) begin\n                  ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:39: Define or directive not defined: \'`DEBUG\'\n   if(`DEBUG == 1\'b1) $display("pc(%d)+4", pc);\n      ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:50: Define or directive not defined: \'`True\'\n  if (rst == `True) begin\n             ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:51: Define or directive not defined: \'`False\'\n                                                                             : ... Suggested alternative: \'`else\'\n   ce <= `False;\n         ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:53: Define or directive not defined: \'`True\'\n   ce <= `True;\n         ^~~~~\n%Error: Cannot continue\n'
module Reg_PC (
	clk, rst, stall,
	wIs, pcIn,
	pc, ce
	);
	input wire clk, rst, stall, wIs;
	input wire [31:0] pcIn;
	output reg [31:0] pc;
	output reg ce;
	reg [31:0] regs[31:0];

	always @ ( posedge clk ) begin
		if (ce == `False) begin
			pc <= 32'd0;
		end else if (!stall) begin
			if(`DEBUG == 1'b1)	$display("pc(%d)+4", pc);
			pc <= pc + 32'd4;
		end
	end
	always @ ( * ) begin
		if ({ce, wIs} == 2'b11) begin
			pc <= pcIn;
		end
	end
	always @ ( posedge clk ) begin

		if (rst == `True) begin
			ce <= `False;
		end else begin
			ce <= `True;
		end
	end

endmodule
module Reg_PC (
	clk, rst, stall,
	wIs, pcIn,
	pc, ce
	);

	input wire clk, rst, stall, wIs;
	input wire [31:0] pcIn;
	output reg [31:0] pc;
	output reg ce;
	reg [31:0] regs[31:0];

	always @ ( posedge clk ) begin
		if (ce == `False) begin
			pc <= 32'd0;
		end else if (!stall) begin
			if(`DEBUG == 1'b1)	$display("pc(%d)+4", pc);
			pc <= pc + 32'd4;
		end
	end
	always @ ( * ) begin
		if ({ce, wIs} == 2'b11) begin
			pc <= pcIn;
		end
	end
	always @ ( posedge clk ) begin

		if (rst == `True) begin
			ce <= `False;
		end else begin
			ce <= `True;
		end
	end

endmodule