data/full_repos/permissive/190755935/src/image/sim/image_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:13: Cannot find include file: ../../utils/sim/sim.v\n`include "../../utils/sim/sim.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/190755935/src/image/sim,data/full_repos/permissive/190755935/../../utils/sim/sim.v\n             data/full_repos/permissive/190755935/src/image/sim,data/full_repos/permissive/190755935/../../utils/sim/sim.v.v\n             data/full_repos/permissive/190755935/src/image/sim,data/full_repos/permissive/190755935/../../utils/sim/sim.v.sv\n             ../../utils/sim/sim.v\n             ../../utils/sim/sim.v.v\n             ../../utils/sim/sim.v.sv\n             obj_dir/../../utils/sim/sim.v\n             obj_dir/../../utils/sim/sim.v.v\n             obj_dir/../../utils/sim/sim.v.sv\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:15: Cannot find include file: ../../image/rtl/image_defs.v\n`include "../../image/rtl/image_defs.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:19: Define or directive not defined: \'`OutputDebug\'\n    parameter Output=`OutputDebug;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:19: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    parameter Output=`OutputDebug;\n                                 ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:21: Define or directive not defined: \'`I_w\'\n    reg [`I_w( IS )-1:0] pixel;\n         ^~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:23: Define or directive not defined: \'`I_w\'\n    reg [`I_w( IS )-1:0] v0;\n         ^~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:24: Define or directive not defined: \'`I_w\'\n    reg [`I_w( IS )-1:0] v1;\n         ^~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:25: Define or directive not defined: \'`I_w\'\n    reg [`I_w( IS )-1:0] vt;\n         ^~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:26: Define or directive not defined: \'`I_w\'\n    reg [`I_w( IS )-1:0] vf;\n         ^~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:35: Define or directive not defined: \'`InfoDo\'\n            `InfoDo $display( "    Test Pipe Values %x", IS );\n            ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:37: Define or directive not defined: \'`Info\'\n            `Info( "        Check Pipe Widths" );\n            ^~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:37: syntax error, unexpected \';\'\n            `Info( "        Check Pipe Widths" );\n                                                ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:39: Define or directive not defined: \'`I_w\'\n            ps_width = `I_w( IS );\n                       ^~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:40: Define or directive not defined: \'`P_w\'\n            ps_width_check = `P_w( `IS_PIPE_SPEC( IS ) );\n                             ^~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:40: Define or directive not defined: \'`IS_PIPE_SPEC\'\n            ps_width_check = `P_w( `IS_PIPE_SPEC( IS ) );\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:41: Define or directive not defined: \'`AssertEqual\'\n            `AssertEqual( ps_width, ps_width_check, "Overall Width" );\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:41: syntax error, unexpected \',\'\n            `AssertEqual( ps_width, ps_width_check, "Overall Width" );\n                                  ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:43: Define or directive not defined: \'`InfoDo\'\n            `InfoDo $display( "            I_w %3d", ps_width );\n            ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:44: Define or directive not defined: \'`InfoDo\'\n            `InfoDo $display( "            P_w %3d", ps_width_check );\n            ^~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:48: Define or directive not defined: \'`I_Data_l\'\n            ps_index = `I_Data_l( IS );\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:50: Define or directive not defined: \'`AssertEqual\'\n            `AssertEqual( ps_index, ps_index_check, "Data" );\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:50: syntax error, unexpected \',\'\n            `AssertEqual( ps_index, ps_index_check, "Data" );\n                                  ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:52: Define or directive not defined: \'`I_Start_w\'\n            ps_width = `I_Start_w( IS );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:53: Define or directive not defined: \'`AssertEqual\'\n            `AssertEqual( ps_width, 1, "Start Width" );\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:53: syntax error, unexpected \',\'\n            `AssertEqual( ps_width, 1, "Start Width" );\n                                  ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:55: Define or directive not defined: \'`I_Stop_w\'\n            ps_width = `I_Stop_w( IS );\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:56: Define or directive not defined: \'`AssertEqual\'\n            `AssertEqual( ps_width, 1, "Stop Width" );\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:56: syntax error, unexpected \',\'\n            `AssertEqual( ps_width, 1, "Stop Width" );\n                                  ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:58: Define or directive not defined: \'`I_Request_w\'\n            ps_width = `I_Request_w( IS );\n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:59: Define or directive not defined: \'`AssertEqual\'\n            `AssertEqual( ps_width, 1, "Request Width" );\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:59: syntax error, unexpected \',\'\n            `AssertEqual( ps_width, 1, "Request Width" );\n                                  ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:61: Define or directive not defined: \'`I_Cancel_w\'\n            ps_width = `I_Cancel_w( IS );\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:62: Define or directive not defined: \'`AssertEqual\'\n            `AssertEqual( ps_width, 1, "Cancel Width" );\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:62: syntax error, unexpected \',\'\n            `AssertEqual( ps_width, 1, "Cancel Width" );\n                                  ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:64: Define or directive not defined: \'`I_Error_w\'\n            ps_width = `I_Error_w( IS );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:65: Define or directive not defined: \'`AssertEqual\'\n            `AssertEqual( ps_width, 1, "Error Width" );\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:65: syntax error, unexpected \',\'\n            `AssertEqual( ps_width, 1, "Error Width" );\n                                  ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:67: Define or directive not defined: \'`I_Valid_w\'\n            ps_width = `I_Valid_w( IS );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:68: Define or directive not defined: \'`AssertEqual\'\n            `AssertEqual( ps_width, 1, "Valid Width" );\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:68: syntax error, unexpected \',\'\n            `AssertEqual( ps_width, 1, "Valid Width" );\n                                  ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:70: Define or directive not defined: \'`I_Ready_w\'\n            ps_width = `I_Ready_w( IS );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:71: Define or directive not defined: \'`AssertEqual\'\n            `AssertEqual( ps_width, 1, "Ready Width" );\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:71: syntax error, unexpected \',\'\n            `AssertEqual( ps_width, 1, "Ready Width" );\n                                  ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:73: Define or directive not defined: \'`Info\'\n            `Info( "        Check Pipe Read Writes" );\n            ^~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:73: syntax error, unexpected \';\'\n            `Info( "        Check Pipe Read Writes" );\n                                                     ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:77: Define or directive not defined: \'`I_Data_m\'\n            v0 = pixel[ `I_Data_m( IS ) : `I_Data_l( IS ) ];\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:77: Define or directive not defined: \'`I_Data_l\'\n            v0 = pixel[ `I_Data_m( IS ) : `I_Data_l( IS ) ];\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:78: Define or directive not defined: \'`AssertEqual\'\n            `AssertEqual( v0, 0, "Data Initial 0 Value" );\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:78: syntax error, unexpected \',\'\n            `AssertEqual( v0, 0, "Data Initial 0 Value" );\n                            ^\n%Error: data/full_repos/permissive/190755935/src/image/sim/image_tb.v:79: Define or directive not defined: \'`I_Data_w\'\n            vt = (1<<`I_Data_w( IS ))-1;\n                     ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module image_instance #( parameter IS = 0 )();

    parameter Output=`OutputDebug;

    reg [`I_w( IS )-1:0] pixel;

    reg [`I_w( IS )-1:0] v0;
    reg [`I_w( IS )-1:0] v1;
    reg [`I_w( IS )-1:0] vt;
    reg [`I_w( IS )-1:0] vf;
    integer ps_index;
    integer ps_index_check;
    integer ps_width;
    integer ps_width_check;


    task test_pipe_values(  inout integer AssertErrorCount, inout integer AssertTestCount );
        begin
            `InfoDo $display( "    Test Pipe Values %x", IS );

            `Info( "        Check Pipe Widths" );

            ps_width = `I_w( IS );
            ps_width_check = `P_w( `IS_PIPE_SPEC( IS ) );
            `AssertEqual( ps_width, ps_width_check, "Overall Width" );

            `InfoDo $display( "            I_w %3d", ps_width );
            `InfoDo $display( "            P_w %3d", ps_width_check );

            pixel = 0;

            ps_index = `I_Data_l( IS );
            ps_index_check = 0;
            `AssertEqual( ps_index, ps_index_check, "Data" );

            ps_width = `I_Start_w( IS );
            `AssertEqual( ps_width, 1, "Start Width" );

            ps_width = `I_Stop_w( IS );
            `AssertEqual( ps_width, 1, "Stop Width" );

            ps_width = `I_Request_w( IS );
            `AssertEqual( ps_width, 1, "Request Width" );

            ps_width = `I_Cancel_w( IS );
            `AssertEqual( ps_width, 1, "Cancel Width" );

            ps_width = `I_Error_w( IS );
            `AssertEqual( ps_width, 1, "Error Width" );

            ps_width = `I_Valid_w( IS );
            `AssertEqual( ps_width, 1, "Valid Width" );

            ps_width = `I_Ready_w( IS );
            `AssertEqual( ps_width, 1, "Ready Width" );

            `Info( "        Check Pipe Read Writes" );

            $display( "            Pre-Diddling     %b", pixel );

            v0 = pixel[ `I_Data_m( IS ) : `I_Data_l( IS ) ];
            `AssertEqual( v0, 0, "Data Initial 0 Value" );
            vt = (1<<`I_Data_w( IS ))-1;
            pixel[ `I_Data_m( IS ) : `I_Data_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Data_m( IS ) : `I_Data_l( IS ) ];
            `Assert( v0 != v1, "Change Data" );
            `AssertEqual( v1, vt, "Data Post Full Load" );
            vf = `I_Data( IS, pixel );
            `AssertEqual( vf, vt, "Data Accessor" );

            $display( "            Diddling Data    %b  m %2d l %2d", pixel, `I_Data_m( IS ), `I_Data_l( IS ) );





            v0 = pixel[ `I_Start_m( IS ) : `I_Start_l( IS ) ];
            `AssertEqual( v0, 0, "Start Initial 0 Value" );
            vt = 1;
            pixel[ `I_Start_m( IS ) : `I_Start_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Start_m( IS ) : `I_Start_l( IS ) ];
            `Assert( v0 != v1, "Change Start" );
            `AssertEqual( v1, vt, "Start Post Full Load" );
            vf = `I_Start( IS, pixel);
            `AssertEqual( vf, vt, "Start Accessor" );





            $display( "            Diddling Start   %b  m %2d l %2d", pixel, `I_Start_m( IS ), `I_Start_l( IS ) );

            v0 = pixel[ `I_Stop_m( IS ) : `I_Stop_l( IS ) ];
            `AssertEqual( v0, 0, "Stop Initial 0 Value" );
            vt = 1;
            pixel[ `I_Stop_m( IS ) : `I_Stop_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Stop_m( IS ) : `I_Stop_l( IS ) ];
            `Assert( v0 != v1, "Change Stop" );
            `AssertEqual( v1, vt, "Stop Post Full Load" );
            vf = `I_Stop( IS, pixel);
            `AssertEqual( vf, vt, "Stop Accessor" );

            $display( "            Diddling Stop    %b  m %2d l %2d", pixel, `I_Stop_m( IS ), `I_Stop_l( IS ) );

            v0 = pixel[ `I_Valid_m( IS ) : `I_Valid_l( IS ) ];
            `AssertEqual( v0, 0, "Valid Initial 0 Value" );
            vt = 1;
            pixel[ `I_Valid_m( IS ) : `I_Valid_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Valid_m( IS ) : `I_Valid_l( IS ) ];
            `Assert( v0 != v1, "Change Valid" );
            `AssertEqual( v1, vt, "Valid Post Full Load" );
            vf = `I_Valid( IS, pixel);
            `AssertEqual( vf, vt, "Valid Accessor" );
            $display( "            Diddling Valid   %b  m %2d l %2d", pixel, `I_Valid_m( IS ), `I_Valid_l( IS ) );






            v0 = pixel[ `I_Ready_m( IS ) : `I_Ready_l( IS ) ];
            `AssertEqual( v0, 0, "Ready Initial 0 Value" );
            vt = 1;
            pixel[ `I_Ready_m( IS ) : `I_Ready_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Ready_m( IS ) : `I_Ready_l( IS ) ];
            `Assert( v0 != v1, "Change Ready" );
            `AssertEqual( v1, vt, "Ready Post Full Load" );
            vf = `I_Ready( IS, pixel);
            `AssertEqual( vf, vt, "Ready Accessor" );

            $display( "            Diddling Ready   %b  m %2d l %2d", pixel, `I_Ready_m( IS ), `I_Ready_l( IS ) );






            v0 = pixel[ `I_Error_m( IS ) : `I_Error_l( IS ) ];
            `AssertEqual( v0, 0, "Error Initial 0 Value" );
            vt = 1;
            pixel[ `I_Error_m( IS ) : `I_Error_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Error_m( IS ) : `I_Error_l( IS ) ];
            `Assert( v0 != v1, "Change Error" );
            `AssertEqual( v1, vt, "Error Post Full Load" );
            vf = `I_Error( IS, pixel);
            `AssertEqual( vf, vt, "Error Accessor" );
            $display( "            Diddling Error   %b  m %2d l %2d", pixel, `I_Error_m( IS ), `I_Error_l( IS ) );

            v0 = pixel[ `I_Cancel_m( IS ) : `I_Cancel_l( IS ) ];
            `AssertEqual( v0, 0, "Cancel Initial 0 Value" );
            vt = 1;
            pixel[ `I_Cancel_m( IS ) : `I_Cancel_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Cancel_m( IS ) : `I_Cancel_l( IS ) ];
            `Assert( v0 != v1, "Change Cancel" );
            `AssertEqual( v1, vt, "Cancel Post Full Load" );
            vf = `I_Cancel( IS, pixel);
            `AssertEqual( vf, vt, "Cancel Accessor" );
            $display( "            Diddling Cancel  %b  m %2d l %2d", pixel, `I_Cancel_m( IS ), `I_Cancel_l( IS ) );

            v0 = pixel[ `I_Request_m( IS ) : `I_Request_l( IS ) ];
            `AssertEqual( v0, 0, "Request Initial 0 Value" );
            vt = 1;
            pixel[ `I_Request_m( IS ) : `I_Request_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Request_m( IS ) : `I_Request_l( IS ) ];
            `Assert( v0 != v1, "Change Request" );
            `AssertEqual( v1, vt, "Request Post Full Load" );
            vf = `I_Request( IS, pixel);
            `AssertEqual( vf, vt, "Request Accessor" );
            $display( "            Diddling Request %b  m %2d l %2d", pixel, `I_Request_m( IS ), `I_Request_l( IS ) );


            pixel = 0;

        end
    endtask

    integer i;

    integer i_data_width;
    integer i_plane_width;
    integer i_width;
    integer i_width_check;


    task test_image_values(  inout integer AssertErrorCount, inout integer AssertTestCount );
        begin
            `InfoDo $display( "    Test Image Values %x", IS );

            `Info( "        Check Image Widths" );

            i_data_width = `I_Data_w( IS );
            i_plane_width = `I_Plane_w( IS );
            i_width = i_plane_width * `IS_PLANES( IS );
            `AssertEqual( i_width, i_data_width, "Data Width" );
            `InfoDo $display( "            Data Width     %d", i_width  );

            i_width = `I_C0_w( IS );
            i_width_check = `IS_C0_WIDTH( IS );
            `AssertEqual( i_width, i_width_check, "C0" );
            `InfoDo $display( "            C0 Width       %d", i_width  );

            i_width = `I_C1_w( IS );
            i_width_check = `IS_C1_WIDTH( IS );
            `AssertEqual( i_width, i_width_check, "C1" );
            `InfoDo $display( "            C1 Width       %d", i_width  );

            i_width = `I_C2_w( IS );
            i_width_check = `IS_C2_WIDTH( IS );
            `AssertEqual( i_width, i_width_check, "C2" );
            `InfoDo $display( "            C2 Width       %d", i_width  );

            i_width = `I_Alpha_w( IS );
            i_width_check = `IS_ALPHA_WIDTH( IS );
            `AssertEqual( i_width, i_width_check, "Alpha" );
            `InfoDo $display( "            Alpha Width    %d", i_width  );

            i_width = `I_Z_w( IS );
            i_width_check = `IS_Z_WIDTH( IS );
            `AssertEqual( i_width, i_width_check, "Z" );
            `InfoDo $display( "            Z Width        %d", i_width  );

            `Info( "        Check Image Read Writes" );

            pixel = 0;

            `Info( "            Default Plane 0" );
            if ( `I_C0_w( IS ) > 0 ) begin
                v0 = pixel[ `I_C0_m( IS, 0 ) : `I_C0_l( IS, 0 ) ];
                `AssertEqual( v0, 0, "C0 Initial 0 Value" );
                vt = ( ( 1 << (`I_C0_w( IS )) ) - 1 );
                pixel[ `I_C0_m( IS, 0 ) : `I_C0_l( IS, 0 ) ] = v0 ^ vt;
                v1 = pixel[ `I_C0_m( IS, 0 ) : `I_C0_l( IS, 0 ) ];
                `AssertEqual( v1, vt, "C0 Post Full Load" );
                vf = `I_C0( IS, pixel );
                `AssertEqual( vf, vt, "C0 Accessor" );
                $display( "            Diddling C0      %b  m %2d l %2d", pixel, `I_C0_m( IS, 0 ), `I_C0_l( IS, 0 ) );
            end

            if ( `I_C1_w( IS ) > 0 ) begin
                v0 = pixel[ `I_C1_m( IS, 0 ) : `I_C1_l( IS, 0 ) ];
                `AssertEqual( v0, 0, "C1 Initial 0 Value" );
                vt = ( ( 1 << (`I_C1_w( IS )) ) - 1 );
                pixel[ `I_C1_m( IS, 0 ) : `I_C1_l( IS, 0 ) ] = v0 ^ vt;
                v1 = pixel[ `I_C1_m( IS, 0 ) : `I_C1_l( IS, 0 ) ];
                `AssertEqual( v1, vt, "C1 Post Full Load" );
                vf = `I_C1( IS, pixel );
                `AssertEqual( vf, vt, "C1 Accessor" );
                $display( "            Diddling C1      %b  m %2d l %2d", pixel, `I_C1_m( IS, 0 ), `I_C1_l( IS, 0 ) );
            end

            if ( `I_C2_w( IS ) > 0 ) begin
                v0 = pixel[ `I_C2_m( IS, 0 ) : `I_C2_l( IS, 0 ) ];
                `AssertEqual( v0, 0, "C2 Initial 0 Value" );
                vt = ( ( 1 << (`I_C2_w( IS )) ) - 1 );
                pixel[ `I_C2_m( IS, 0 ) : `I_C2_l( IS, 0 ) ] = v0 ^ vt;
                v1 = pixel[ `I_C2_m( IS, 0 ) : `I_C2_l( IS, 0 ) ];
                `AssertEqual( v1, vt, "C2 Post Full Load" );
                vf = `I_C2( IS, pixel );
                `AssertEqual( vf, vt, "C2 Accessor" );
                $display( "            Diddling C2      %b  m %2d l %2d", pixel, `I_C2_m( IS, 0 ), `I_C2_l( IS, 0 ) );
            end

            if ( `I_Alpha_w( IS ) > 0 ) begin
                v0 = pixel[ `I_Alpha_m( IS, 0 ) : `I_Alpha_l( IS, 0 ) ];
                `AssertEqual( v0, 0, "Alpha Initial 0 Value" );
                vt = ( ( 1 << (`I_Alpha_w( IS )) ) - 1 );
                pixel[ `I_Alpha_m( IS, 0 ) : `I_Alpha_l( IS, 0 ) ] = v0 ^ vt;
                v1 = pixel[ `I_Alpha_m( IS, 0 ) : `I_Alpha_l( IS, 0 ) ];
                `AssertEqual( v1, vt, "Alpha Post Full Load" );
                vf = `I_Alpha( IS, pixel );
                `AssertEqual( vf, vt, "Alpha Accessor" );
                $display( "            Diddling Alpha   %b  m %2d l %2d", pixel, `I_Alpha_m( IS, 0 ), `I_Alpha_l( IS, 0 ) );
            end

            if ( `I_Z_w( IS ) > 0 ) begin
                v0 = pixel[ `I_Z_m( IS, 0 ) : `I_Z_l( IS, 0 ) ];
                `AssertEqual( v0, 0, "Z Initial 0 Value" );
                vt = ( ( 1 << (`I_Z_w( IS )) ) - 1 );
                pixel[ `I_Z_m( IS, 0 ) : `I_Z_l( IS, 0 ) ] = v0 ^ vt;
                v1 = pixel[ `I_Z_m( IS, 0 ) : `I_Z_l( IS, 0 ) ];
                `AssertEqual( v1, vt, "Z Post Full Load" );
                vf = `I_Z( IS, pixel );
                `AssertEqual( vf, vt, "Z Accessor" );
                $display( "            Diddling Z       %b  m %2d l %2d", pixel, `I_Z_m( IS, 0 ), `I_Z_l( IS, 0 ) );
            end

            if ( `IS_PLANES( IS ) > 1 ) begin

                `Info( "            Trial Test Plane 1" );

                if ( `I_C0_w( IS ) > 0 ) begin
                    v0 = pixel[ `I_C0_m( IS, 1 ) : `I_C0_l( IS, 1 ) ];
                    `AssertEqual( v0, 0, "C0 Initial 0 Value" );
                    vt = ( ( 1 << (`I_C0_w( IS )) ) - 1 );
                    pixel[ `I_C0_m( IS, 1 ) : `I_C0_l( IS, 1 ) ] = v0 ^ vt;
                    v1 = pixel[ `I_C0_m( IS, 1 ) : `I_C0_l( IS, 1 ) ];
                    `AssertEqual( v1, vt, "C0 Post Full Load" );
                    vf = `I_C0_p( IS, pixel, 1  );
                    `AssertEqual( vf, vt, "C0 Accessor" );
                    $display( "            Diddling C0.1    %b  m %2d l %2d", pixel, `I_C0_m( IS, 1 ), `I_C0_l( IS, 1 ) );
                end

                if ( `I_C1_w( IS ) > 0 ) begin
                    v0 = pixel[ `I_C1_m( IS, 1 ) : `I_C1_l( IS, 1 ) ];
                    `AssertEqual( v0, 0, "C1 Initial 0 Value" );
                    vt = ( ( 1 << (`I_C1_w( IS )) ) - 1 );
                    pixel[ `I_C1_m( IS, 1 ) : `I_C1_l( IS, 1 ) ] = v0 ^ vt;
                    v1 = pixel[ `I_C1_m( IS, 1 ) : `I_C1_l( IS, 1 ) ];
                    `AssertEqual( v1, vt, "C1 Post Full Load" );
                    vf = `I_C1_p( IS, pixel, 1 );
                    `AssertEqual( vf, vt, "C1 Accessor" );
                    $display( "            Diddling C1.1    %b  m %2d l %2d", pixel, `I_C1_m( IS, 1 ), `I_C1_l( IS, 1 ) );
                end

                if ( `I_C2_w( IS ) > 0 ) begin
                    v0 = pixel[ `I_C2_m( IS, 1 ) : `I_C2_l( IS, 1 ) ];
                    `AssertEqual( v0, 0, "C2 Initial 0 Value" );
                    vt = ( ( 1 << (`I_C2_w( IS )) ) - 1 );
                    pixel[ `I_C2_m( IS, 1 ) : `I_C2_l( IS, 1 ) ] = v0 ^ vt;
                    v1 = pixel[ `I_C2_m( IS, 1 ) : `I_C2_l( IS, 1 ) ];
                    `AssertEqual( v1, vt, "C2 Post Full Load" );
                    vf = `I_C2_p( IS, pixel, 1 );
                    `AssertEqual( vf, vt, "C2 Accessor" );
                    $display( "            Diddling C0.2    %b  m %2d l %2d", pixel, `I_C2_m( IS, 1 ), `I_C2_l( IS, 1 ) );
                end

                if ( `I_Alpha_w( IS ) > 0 ) begin
                    v0 = pixel[ `I_Alpha_m( IS, 1 ) : `I_Alpha_l( IS, 1 ) ];
                    `AssertEqual( v0, 0, "Alpha Initial 0 Value" );
                    vt = ( ( 1 << (`I_Alpha_w( IS )) ) - 1 );
                    pixel[ `I_Alpha_m( IS, 1 ) : `I_Alpha_l( IS, 1 ) ] = v0 ^ vt;
                    v1 = pixel[ `I_Alpha_m( IS, 1 ) : `I_Alpha_l( IS, 1 ) ];
                    `AssertEqual( v1, vt, "Alpha Post Full Load" );
                    vf = `I_Alpha_p( IS, pixel, 1 );
                    `AssertEqual( vf, vt, "Alpha Accessor" );
                    $display( "            Diddling Alpha.2 %b  m %2d l %2d", pixel, `I_Alpha_m( IS, 1 ), `I_Alpha_l( IS, 1 ) );
                end

                if ( `I_Z_w( IS ) > 0 ) begin
                    v0 = pixel[ `I_Z_m( IS, 1 ) : `I_Z_l( IS, 1 ) ];
                    `AssertEqual( v0, 0, "Z Initial 0 Value" );
                    vt = ( ( 1 << (`I_Z_w( IS )) ) - 1 );
                    pixel[ `I_Z_m( IS, 1 ) : `I_Z_l( IS, 1 ) ] = v0 ^ vt;
                    v1 = pixel[ `I_Z_m( IS, 1 ) : `I_Z_l( IS, 1 ) ];
                    `AssertEqual( v1, vt, "Z Post Full Load" );
                    vf = `I_Z_p( IS, pixel, 1 );
                    `AssertEqual( vf, vt, "Z Accessor" );
                    $display( "            Diddling Z.2     %b  m %2d l %2d", pixel, `I_Z_m( IS, 1 ), `I_Z_l( IS, 1 ) );
                end

            end


        end
    endtask

endmodule
module image_instance #( parameter IS = 0 )();


    parameter Output=`OutputDebug;

    reg [`I_w( IS )-1:0] pixel;

    reg [`I_w( IS )-1:0] v0;
    reg [`I_w( IS )-1:0] v1;
    reg [`I_w( IS )-1:0] vt;
    reg [`I_w( IS )-1:0] vf;
    integer ps_index;
    integer ps_index_check;
    integer ps_width;
    integer ps_width_check;


    task test_pipe_values(  inout integer AssertErrorCount, inout integer AssertTestCount );
        begin
            `InfoDo $display( "    Test Pipe Values %x", IS );

            `Info( "        Check Pipe Widths" );

            ps_width = `I_w( IS );
            ps_width_check = `P_w( `IS_PIPE_SPEC( IS ) );
            `AssertEqual( ps_width, ps_width_check, "Overall Width" );

            `InfoDo $display( "            I_w %3d", ps_width );
            `InfoDo $display( "            P_w %3d", ps_width_check );

            pixel = 0;

            ps_index = `I_Data_l( IS );
            ps_index_check = 0;
            `AssertEqual( ps_index, ps_index_check, "Data" );

            ps_width = `I_Start_w( IS );
            `AssertEqual( ps_width, 1, "Start Width" );

            ps_width = `I_Stop_w( IS );
            `AssertEqual( ps_width, 1, "Stop Width" );

            ps_width = `I_Request_w( IS );
            `AssertEqual( ps_width, 1, "Request Width" );

            ps_width = `I_Cancel_w( IS );
            `AssertEqual( ps_width, 1, "Cancel Width" );

            ps_width = `I_Error_w( IS );
            `AssertEqual( ps_width, 1, "Error Width" );

            ps_width = `I_Valid_w( IS );
            `AssertEqual( ps_width, 1, "Valid Width" );

            ps_width = `I_Ready_w( IS );
            `AssertEqual( ps_width, 1, "Ready Width" );

            `Info( "        Check Pipe Read Writes" );

            $display( "            Pre-Diddling     %b", pixel );

            v0 = pixel[ `I_Data_m( IS ) : `I_Data_l( IS ) ];
            `AssertEqual( v0, 0, "Data Initial 0 Value" );
            vt = (1<<`I_Data_w( IS ))-1;
            pixel[ `I_Data_m( IS ) : `I_Data_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Data_m( IS ) : `I_Data_l( IS ) ];
            `Assert( v0 != v1, "Change Data" );
            `AssertEqual( v1, vt, "Data Post Full Load" );
            vf = `I_Data( IS, pixel );
            `AssertEqual( vf, vt, "Data Accessor" );

            $display( "            Diddling Data    %b  m %2d l %2d", pixel, `I_Data_m( IS ), `I_Data_l( IS ) );





            v0 = pixel[ `I_Start_m( IS ) : `I_Start_l( IS ) ];
            `AssertEqual( v0, 0, "Start Initial 0 Value" );
            vt = 1;
            pixel[ `I_Start_m( IS ) : `I_Start_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Start_m( IS ) : `I_Start_l( IS ) ];
            `Assert( v0 != v1, "Change Start" );
            `AssertEqual( v1, vt, "Start Post Full Load" );
            vf = `I_Start( IS, pixel);
            `AssertEqual( vf, vt, "Start Accessor" );





            $display( "            Diddling Start   %b  m %2d l %2d", pixel, `I_Start_m( IS ), `I_Start_l( IS ) );

            v0 = pixel[ `I_Stop_m( IS ) : `I_Stop_l( IS ) ];
            `AssertEqual( v0, 0, "Stop Initial 0 Value" );
            vt = 1;
            pixel[ `I_Stop_m( IS ) : `I_Stop_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Stop_m( IS ) : `I_Stop_l( IS ) ];
            `Assert( v0 != v1, "Change Stop" );
            `AssertEqual( v1, vt, "Stop Post Full Load" );
            vf = `I_Stop( IS, pixel);
            `AssertEqual( vf, vt, "Stop Accessor" );

            $display( "            Diddling Stop    %b  m %2d l %2d", pixel, `I_Stop_m( IS ), `I_Stop_l( IS ) );

            v0 = pixel[ `I_Valid_m( IS ) : `I_Valid_l( IS ) ];
            `AssertEqual( v0, 0, "Valid Initial 0 Value" );
            vt = 1;
            pixel[ `I_Valid_m( IS ) : `I_Valid_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Valid_m( IS ) : `I_Valid_l( IS ) ];
            `Assert( v0 != v1, "Change Valid" );
            `AssertEqual( v1, vt, "Valid Post Full Load" );
            vf = `I_Valid( IS, pixel);
            `AssertEqual( vf, vt, "Valid Accessor" );
            $display( "            Diddling Valid   %b  m %2d l %2d", pixel, `I_Valid_m( IS ), `I_Valid_l( IS ) );






            v0 = pixel[ `I_Ready_m( IS ) : `I_Ready_l( IS ) ];
            `AssertEqual( v0, 0, "Ready Initial 0 Value" );
            vt = 1;
            pixel[ `I_Ready_m( IS ) : `I_Ready_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Ready_m( IS ) : `I_Ready_l( IS ) ];
            `Assert( v0 != v1, "Change Ready" );
            `AssertEqual( v1, vt, "Ready Post Full Load" );
            vf = `I_Ready( IS, pixel);
            `AssertEqual( vf, vt, "Ready Accessor" );

            $display( "            Diddling Ready   %b  m %2d l %2d", pixel, `I_Ready_m( IS ), `I_Ready_l( IS ) );






            v0 = pixel[ `I_Error_m( IS ) : `I_Error_l( IS ) ];
            `AssertEqual( v0, 0, "Error Initial 0 Value" );
            vt = 1;
            pixel[ `I_Error_m( IS ) : `I_Error_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Error_m( IS ) : `I_Error_l( IS ) ];
            `Assert( v0 != v1, "Change Error" );
            `AssertEqual( v1, vt, "Error Post Full Load" );
            vf = `I_Error( IS, pixel);
            `AssertEqual( vf, vt, "Error Accessor" );
            $display( "            Diddling Error   %b  m %2d l %2d", pixel, `I_Error_m( IS ), `I_Error_l( IS ) );

            v0 = pixel[ `I_Cancel_m( IS ) : `I_Cancel_l( IS ) ];
            `AssertEqual( v0, 0, "Cancel Initial 0 Value" );
            vt = 1;
            pixel[ `I_Cancel_m( IS ) : `I_Cancel_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Cancel_m( IS ) : `I_Cancel_l( IS ) ];
            `Assert( v0 != v1, "Change Cancel" );
            `AssertEqual( v1, vt, "Cancel Post Full Load" );
            vf = `I_Cancel( IS, pixel);
            `AssertEqual( vf, vt, "Cancel Accessor" );
            $display( "            Diddling Cancel  %b  m %2d l %2d", pixel, `I_Cancel_m( IS ), `I_Cancel_l( IS ) );

            v0 = pixel[ `I_Request_m( IS ) : `I_Request_l( IS ) ];
            `AssertEqual( v0, 0, "Request Initial 0 Value" );
            vt = 1;
            pixel[ `I_Request_m( IS ) : `I_Request_l( IS ) ] = v0 ^ vt;
            v1 = pixel[ `I_Request_m( IS ) : `I_Request_l( IS ) ];
            `Assert( v0 != v1, "Change Request" );
            `AssertEqual( v1, vt, "Request Post Full Load" );
            vf = `I_Request( IS, pixel);
            `AssertEqual( vf, vt, "Request Accessor" );
            $display( "            Diddling Request %b  m %2d l %2d", pixel, `I_Request_m( IS ), `I_Request_l( IS ) );


            pixel = 0;

        end
    endtask

    integer i;

    integer i_data_width;
    integer i_plane_width;
    integer i_width;
    integer i_width_check;


    task test_image_values(  inout integer AssertErrorCount, inout integer AssertTestCount );
        begin
            `InfoDo $display( "    Test Image Values %x", IS );

            `Info( "        Check Image Widths" );

            i_data_width = `I_Data_w( IS );
            i_plane_width = `I_Plane_w( IS );
            i_width = i_plane_width * `IS_PLANES( IS );
            `AssertEqual( i_width, i_data_width, "Data Width" );
            `InfoDo $display( "            Data Width     %d", i_width  );

            i_width = `I_C0_w( IS );
            i_width_check = `IS_C0_WIDTH( IS );
            `AssertEqual( i_width, i_width_check, "C0" );
            `InfoDo $display( "            C0 Width       %d", i_width  );

            i_width = `I_C1_w( IS );
            i_width_check = `IS_C1_WIDTH( IS );
            `AssertEqual( i_width, i_width_check, "C1" );
            `InfoDo $display( "            C1 Width       %d", i_width  );

            i_width = `I_C2_w( IS );
            i_width_check = `IS_C2_WIDTH( IS );
            `AssertEqual( i_width, i_width_check, "C2" );
            `InfoDo $display( "            C2 Width       %d", i_width  );

            i_width = `I_Alpha_w( IS );
            i_width_check = `IS_ALPHA_WIDTH( IS );
            `AssertEqual( i_width, i_width_check, "Alpha" );
            `InfoDo $display( "            Alpha Width    %d", i_width  );

            i_width = `I_Z_w( IS );
            i_width_check = `IS_Z_WIDTH( IS );
            `AssertEqual( i_width, i_width_check, "Z" );
            `InfoDo $display( "            Z Width        %d", i_width  );

            `Info( "        Check Image Read Writes" );

            pixel = 0;

            `Info( "            Default Plane 0" );
            if ( `I_C0_w( IS ) > 0 ) begin
                v0 = pixel[ `I_C0_m( IS, 0 ) : `I_C0_l( IS, 0 ) ];
                `AssertEqual( v0, 0, "C0 Initial 0 Value" );
                vt = ( ( 1 << (`I_C0_w( IS )) ) - 1 );
                pixel[ `I_C0_m( IS, 0 ) : `I_C0_l( IS, 0 ) ] = v0 ^ vt;
                v1 = pixel[ `I_C0_m( IS, 0 ) : `I_C0_l( IS, 0 ) ];
                `AssertEqual( v1, vt, "C0 Post Full Load" );
                vf = `I_C0( IS, pixel );
                `AssertEqual( vf, vt, "C0 Accessor" );
                $display( "            Diddling C0      %b  m %2d l %2d", pixel, `I_C0_m( IS, 0 ), `I_C0_l( IS, 0 ) );
            end

            if ( `I_C1_w( IS ) > 0 ) begin
                v0 = pixel[ `I_C1_m( IS, 0 ) : `I_C1_l( IS, 0 ) ];
                `AssertEqual( v0, 0, "C1 Initial 0 Value" );
                vt = ( ( 1 << (`I_C1_w( IS )) ) - 1 );
                pixel[ `I_C1_m( IS, 0 ) : `I_C1_l( IS, 0 ) ] = v0 ^ vt;
                v1 = pixel[ `I_C1_m( IS, 0 ) : `I_C1_l( IS, 0 ) ];
                `AssertEqual( v1, vt, "C1 Post Full Load" );
                vf = `I_C1( IS, pixel );
                `AssertEqual( vf, vt, "C1 Accessor" );
                $display( "            Diddling C1      %b  m %2d l %2d", pixel, `I_C1_m( IS, 0 ), `I_C1_l( IS, 0 ) );
            end

            if ( `I_C2_w( IS ) > 0 ) begin
                v0 = pixel[ `I_C2_m( IS, 0 ) : `I_C2_l( IS, 0 ) ];
                `AssertEqual( v0, 0, "C2 Initial 0 Value" );
                vt = ( ( 1 << (`I_C2_w( IS )) ) - 1 );
                pixel[ `I_C2_m( IS, 0 ) : `I_C2_l( IS, 0 ) ] = v0 ^ vt;
                v1 = pixel[ `I_C2_m( IS, 0 ) : `I_C2_l( IS, 0 ) ];
                `AssertEqual( v1, vt, "C2 Post Full Load" );
                vf = `I_C2( IS, pixel );
                `AssertEqual( vf, vt, "C2 Accessor" );
                $display( "            Diddling C2      %b  m %2d l %2d", pixel, `I_C2_m( IS, 0 ), `I_C2_l( IS, 0 ) );
            end

            if ( `I_Alpha_w( IS ) > 0 ) begin
                v0 = pixel[ `I_Alpha_m( IS, 0 ) : `I_Alpha_l( IS, 0 ) ];
                `AssertEqual( v0, 0, "Alpha Initial 0 Value" );
                vt = ( ( 1 << (`I_Alpha_w( IS )) ) - 1 );
                pixel[ `I_Alpha_m( IS, 0 ) : `I_Alpha_l( IS, 0 ) ] = v0 ^ vt;
                v1 = pixel[ `I_Alpha_m( IS, 0 ) : `I_Alpha_l( IS, 0 ) ];
                `AssertEqual( v1, vt, "Alpha Post Full Load" );
                vf = `I_Alpha( IS, pixel );
                `AssertEqual( vf, vt, "Alpha Accessor" );
                $display( "            Diddling Alpha   %b  m %2d l %2d", pixel, `I_Alpha_m( IS, 0 ), `I_Alpha_l( IS, 0 ) );
            end

            if ( `I_Z_w( IS ) > 0 ) begin
                v0 = pixel[ `I_Z_m( IS, 0 ) : `I_Z_l( IS, 0 ) ];
                `AssertEqual( v0, 0, "Z Initial 0 Value" );
                vt = ( ( 1 << (`I_Z_w( IS )) ) - 1 );
                pixel[ `I_Z_m( IS, 0 ) : `I_Z_l( IS, 0 ) ] = v0 ^ vt;
                v1 = pixel[ `I_Z_m( IS, 0 ) : `I_Z_l( IS, 0 ) ];
                `AssertEqual( v1, vt, "Z Post Full Load" );
                vf = `I_Z( IS, pixel );
                `AssertEqual( vf, vt, "Z Accessor" );
                $display( "            Diddling Z       %b  m %2d l %2d", pixel, `I_Z_m( IS, 0 ), `I_Z_l( IS, 0 ) );
            end

            if ( `IS_PLANES( IS ) > 1 ) begin

                `Info( "            Trial Test Plane 1" );

                if ( `I_C0_w( IS ) > 0 ) begin
                    v0 = pixel[ `I_C0_m( IS, 1 ) : `I_C0_l( IS, 1 ) ];
                    `AssertEqual( v0, 0, "C0 Initial 0 Value" );
                    vt = ( ( 1 << (`I_C0_w( IS )) ) - 1 );
                    pixel[ `I_C0_m( IS, 1 ) : `I_C0_l( IS, 1 ) ] = v0 ^ vt;
                    v1 = pixel[ `I_C0_m( IS, 1 ) : `I_C0_l( IS, 1 ) ];
                    `AssertEqual( v1, vt, "C0 Post Full Load" );
                    vf = `I_C0_p( IS, pixel, 1  );
                    `AssertEqual( vf, vt, "C0 Accessor" );
                    $display( "            Diddling C0.1    %b  m %2d l %2d", pixel, `I_C0_m( IS, 1 ), `I_C0_l( IS, 1 ) );
                end

                if ( `I_C1_w( IS ) > 0 ) begin
                    v0 = pixel[ `I_C1_m( IS, 1 ) : `I_C1_l( IS, 1 ) ];
                    `AssertEqual( v0, 0, "C1 Initial 0 Value" );
                    vt = ( ( 1 << (`I_C1_w( IS )) ) - 1 );
                    pixel[ `I_C1_m( IS, 1 ) : `I_C1_l( IS, 1 ) ] = v0 ^ vt;
                    v1 = pixel[ `I_C1_m( IS, 1 ) : `I_C1_l( IS, 1 ) ];
                    `AssertEqual( v1, vt, "C1 Post Full Load" );
                    vf = `I_C1_p( IS, pixel, 1 );
                    `AssertEqual( vf, vt, "C1 Accessor" );
                    $display( "            Diddling C1.1    %b  m %2d l %2d", pixel, `I_C1_m( IS, 1 ), `I_C1_l( IS, 1 ) );
                end

                if ( `I_C2_w( IS ) > 0 ) begin
                    v0 = pixel[ `I_C2_m( IS, 1 ) : `I_C2_l( IS, 1 ) ];
                    `AssertEqual( v0, 0, "C2 Initial 0 Value" );
                    vt = ( ( 1 << (`I_C2_w( IS )) ) - 1 );
                    pixel[ `I_C2_m( IS, 1 ) : `I_C2_l( IS, 1 ) ] = v0 ^ vt;
                    v1 = pixel[ `I_C2_m( IS, 1 ) : `I_C2_l( IS, 1 ) ];
                    `AssertEqual( v1, vt, "C2 Post Full Load" );
                    vf = `I_C2_p( IS, pixel, 1 );
                    `AssertEqual( vf, vt, "C2 Accessor" );
                    $display( "            Diddling C0.2    %b  m %2d l %2d", pixel, `I_C2_m( IS, 1 ), `I_C2_l( IS, 1 ) );
                end

                if ( `I_Alpha_w( IS ) > 0 ) begin
                    v0 = pixel[ `I_Alpha_m( IS, 1 ) : `I_Alpha_l( IS, 1 ) ];
                    `AssertEqual( v0, 0, "Alpha Initial 0 Value" );
                    vt = ( ( 1 << (`I_Alpha_w( IS )) ) - 1 );
                    pixel[ `I_Alpha_m( IS, 1 ) : `I_Alpha_l( IS, 1 ) ] = v0 ^ vt;
                    v1 = pixel[ `I_Alpha_m( IS, 1 ) : `I_Alpha_l( IS, 1 ) ];
                    `AssertEqual( v1, vt, "Alpha Post Full Load" );
                    vf = `I_Alpha_p( IS, pixel, 1 );
                    `AssertEqual( vf, vt, "Alpha Accessor" );
                    $display( "            Diddling Alpha.2 %b  m %2d l %2d", pixel, `I_Alpha_m( IS, 1 ), `I_Alpha_l( IS, 1 ) );
                end

                if ( `I_Z_w( IS ) > 0 ) begin
                    v0 = pixel[ `I_Z_m( IS, 1 ) : `I_Z_l( IS, 1 ) ];
                    `AssertEqual( v0, 0, "Z Initial 0 Value" );
                    vt = ( ( 1 << (`I_Z_w( IS )) ) - 1 );
                    pixel[ `I_Z_m( IS, 1 ) : `I_Z_l( IS, 1 ) ] = v0 ^ vt;
                    v1 = pixel[ `I_Z_m( IS, 1 ) : `I_Z_l( IS, 1 ) ];
                    `AssertEqual( v1, vt, "Z Post Full Load" );
                    vf = `I_Z_p( IS, pixel, 1 );
                    `AssertEqual( vf, vt, "Z Accessor" );
                    $display( "            Diddling Z.2     %b  m %2d l %2d", pixel, `I_Z_m( IS, 1 ), `I_Z_l( IS, 1 ) );
                end

            end


        end
    endtask

endmodule