data/full_repos/permissive/146618947/sintestis_tarea5/mux_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/146618947/sintestis_tarea5/mux_tb.v:2: Cannot find include file: mux_estructural_ideal.v\n`include "mux_estructural_ideal.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146618947/sintestis_tarea5,data/full_repos/permissive/146618947/mux_estructural_ideal.v\n             data/full_repos/permissive/146618947/sintestis_tarea5,data/full_repos/permissive/146618947/mux_estructural_ideal.v.v\n             data/full_repos/permissive/146618947/sintestis_tarea5,data/full_repos/permissive/146618947/mux_estructural_ideal.v.sv\n             mux_estructural_ideal.v\n             mux_estructural_ideal.v.v\n             mux_estructural_ideal.v.sv\n             obj_dir/mux_estructural_ideal.v\n             obj_dir/mux_estructural_ideal.v.v\n             obj_dir/mux_estructural_ideal.v.sv\n%Error: data/full_repos/permissive/146618947/sintestis_tarea5/mux_tb.v:3: Cannot find include file: mux_estructural_real.v\n`include "mux_estructural_real.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/146618947/sintestis_tarea5/mux_tb.v:4: Cannot find include file: mux_tester.v\n`include "mux_tester.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/146618947/sintestis_tarea5/mux_tb.v:5: Cannot find include file: mux_conductual.v\n`include "mux_conductual.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/146618947/sintestis_tarea5/mux_tb.v:6: Cannot find include file: mycells.v\n`include "mycells.v" \n         ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module mux_tb;
   wire reset_L, clk;
   wire [3:0] data_0;
   wire [3:0] data_1;
   wire [3:0] data_out_estructural_ideal;
   wire [3:0] data_out_estructural_real;
   wire [3:0] data_out_conductual;

   mux_estructural_ideal mux_estructural_ideal_ (.reset_L (reset_L),
                                                 .clk (clk),
                                                 .data_0 (data_0),
                                                 .data_1 (data_1),
                                                 .data_out (data_out_estructural_ideal)
                                                 );

   mux_estructural_real mux_estructural_real_ (.reset_L (reset_L),
                                               .clk (clk),
                                               .data_0 (data_0),
                                               .data_1 (data_1),
                                               .data_out (data_out_estructural_real)
                                               );

   mux_conductual mux_conductual_ (.reset_L (reset_L),
                                   .clk (clk),
                                   .data_0 (data_0),
                                   .data_1 (data_1),
                                   .data_out (data_out_conductual)
                                   );

   mux_tester mux_tester_(.reset_L (reset_L),
                          .clk (clk),
                          .data_0 (data_0),
                          .data_1 (data_1),
                          .data_out_estructural_ideal (data_out_estructural_ideal),
                          .data_out_estructural_real (data_out_estructural_real),
                          .data_out_conductual (data_out_conductual)
                          );
endmodule
module mux_tb;

   wire reset_L, clk;
   wire [3:0] data_0;
   wire [3:0] data_1;
   wire [3:0] data_out_estructural_ideal;
   wire [3:0] data_out_estructural_real;
   wire [3:0] data_out_conductual;

   mux_estructural_ideal mux_estructural_ideal_ (.reset_L (reset_L),
                                                 .clk (clk),
                                                 .data_0 (data_0),
                                                 .data_1 (data_1),
                                                 .data_out (data_out_estructural_ideal)
                                                 );

   mux_estructural_real mux_estructural_real_ (.reset_L (reset_L),
                                               .clk (clk),
                                               .data_0 (data_0),
                                               .data_1 (data_1),
                                               .data_out (data_out_estructural_real)
                                               );

   mux_conductual mux_conductual_ (.reset_L (reset_L),
                                   .clk (clk),
                                   .data_0 (data_0),
                                   .data_1 (data_1),
                                   .data_out (data_out_conductual)
                                   );

   mux_tester mux_tester_(.reset_L (reset_L),
                          .clk (clk),
                          .data_0 (data_0),
                          .data_1 (data_1),
                          .data_out_estructural_ideal (data_out_estructural_ideal),
                          .data_out_estructural_real (data_out_estructural_real),
                          .data_out_conductual (data_out_conductual)
                          );
endmodule