data/full_repos/permissive/1840016/lab3/ALU16_LA.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/1840016/lab3/ALU16_LA.v:25: Signal definition not found, creating implicitly: \'less\'\n   assign less = 1\'b0;\n          ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/1840016/lab3/ALU16_LA.v:32: Cannot find file containing module: \'ALU4_LA\'\n    ALU4_LA a1(A[3:0],   B[3:0],   sel[2], C_NULL[0], overflow, sel, out[3:0], p[0], g[0]); \n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/1840016/lab3,data/full_repos/permissive/1840016/ALU4_LA\n             data/full_repos/permissive/1840016/lab3,data/full_repos/permissive/1840016/ALU4_LA.v\n             data/full_repos/permissive/1840016/lab3,data/full_repos/permissive/1840016/ALU4_LA.sv\n             ALU4_LA\n             ALU4_LA.v\n             ALU4_LA.sv\n             obj_dir/ALU4_LA\n             obj_dir/ALU4_LA.v\n             obj_dir/ALU4_LA.sv\n%Error: data/full_repos/permissive/1840016/lab3/ALU16_LA.v:33: Cannot find file containing module: \'ALU4_LA\'\n    ALU4_LA a2(A[7:4],   B[7:4],   c[0],  C_NULL[1], less,  sel,  out[7:4], p[1], g[1]); \n    ^~~~~~~\n%Error: data/full_repos/permissive/1840016/lab3/ALU16_LA.v:34: Cannot find file containing module: \'ALU4_LA\'\n    ALU4_LA a3(A[11:8],  B[11:8],  c[1],  C_NULL[2], less,  sel,  out[11:8], p[2], g[2]); \n    ^~~~~~~\n%Error: data/full_repos/permissive/1840016/lab3/ALU16_LA.v:35: Cannot find file containing module: \'ALU4_LA\'\n    ALU4_LA a4(A[15:12], B[15:12], c[2],  C_NULL[3], less,  sel,  out[15:12], p[3], g[3]); \n    ^~~~~~~\n%Error: data/full_repos/permissive/1840016/lab3/ALU16_LA.v:37: Cannot find file containing module: \'lookahead\'\n    lookahead l1(sel[2], c_out, c, p, g, P_NULL, G_NULL);\n    ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module ALU16_LA(A, B, sel, out);
   input [15:0] A, B;
   input [2:0] sel;
   wire [3:0] p, g;
   
   output [15:0] out;
   
   assign less = 1'b0;
   
   wire [2:0] c;
   wire P_NULL, G_NULL, overflow, c_out;
   wire C_NULL[3:0];
       

    ALU4_LA a1(A[3:0],   B[3:0],   sel[2], C_NULL[0], overflow, sel, out[3:0], p[0], g[0]); 
    ALU4_LA a2(A[7:4],   B[7:4],   c[0],  C_NULL[1], less,  sel,  out[7:4], p[1], g[1]); 
    ALU4_LA a3(A[11:8],  B[11:8],  c[1],  C_NULL[2], less,  sel,  out[11:8], p[2], g[2]); 
    ALU4_LA a4(A[15:12], B[15:12], c[2],  C_NULL[3], less,  sel,  out[15:12], p[3], g[3]); 
  
    lookahead l1(sel[2], c_out, c, p, g, P_NULL, G_NULL);
    
    assign overflow =~ out[15] ^ c_out;

endmodule
module ALU16_LA(A, B, sel, out);

   input [15:0] A, B;
   input [2:0] sel;
   wire [3:0] p, g;
   
   output [15:0] out;
   
   assign less = 1'b0;
   
   wire [2:0] c;
   wire P_NULL, G_NULL, overflow, c_out;
   wire C_NULL[3:0];
       

    ALU4_LA a1(A[3:0],   B[3:0],   sel[2], C_NULL[0], overflow, sel, out[3:0], p[0], g[0]); 
    ALU4_LA a2(A[7:4],   B[7:4],   c[0],  C_NULL[1], less,  sel,  out[7:4], p[1], g[1]); 
    ALU4_LA a3(A[11:8],  B[11:8],  c[1],  C_NULL[2], less,  sel,  out[11:8], p[2], g[2]); 
    ALU4_LA a4(A[15:12], B[15:12], c[2],  C_NULL[3], less,  sel,  out[15:12], p[3], g[3]); 
  
    lookahead l1(sel[2], c_out, c, p, g, P_NULL, G_NULL);
    
    assign overflow =~ out[15] ^ c_out;

endmodule