data/full_repos/permissive/143278/ivltests/pr1878909.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1878909.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_top();

  wire [3:0] test_val;

  test_mod test_mod0 [3:0](
   .in_0(1'b1),
   .out_0(test_val)
  );

  initial begin
    #1;
    if(test_val != 4'b0000) $display("Failed");
    else $display("PASSED");
  end
endmodule
module test_top();


  wire [3:0] test_val;

  test_mod test_mod0 [3:0](
   .in_0(1'b1),
   .out_0(test_val)
  );

  initial begin
    #1;
    if(test_val != 4'b0000) $display("Failed");
    else $display("PASSED");
  end
endmodule