data/full_repos/permissive/148200700/Quartus/ip/chip_id_read_mm/chip_id_read_mm.v
data/verilator_xmls/12c8c41a-6a8c-4eaf-91b5-1ed7d30c98e6.xml
module chip_id_read_mm (

		input  wire        clk,
		input  wire        reset,


		input  wire        avs_s0_read,
		output wire [63:0] avs_s0_readdata,


		input  wire [63:0] asi_in0_data,
		output wire        asi_in0_ready
	);

	assign avs_s0_readdata = asi_in0_data;
	assign asi_in0_ready = 1'b1;

endmodule
module chip_id_read_mm (

		input  wire        clk,
		input  wire        reset,


		input  wire        avs_s0_read,
		output wire [63:0] avs_s0_readdata,


		input  wire [63:0] asi_in0_data,
		output wire        asi_in0_ready
	);


	assign avs_s0_readdata = asi_in0_data;
	assign asi_in0_ready = 1'b1;

endmodule