data/full_repos/permissive/143278/ivltests/implicit-port4.v
 line:10: before: "*"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/implicit-port4.v:14: Unsupported: Ignoring delay on this delayed statement.\n   #1 if (b !== a || d !== ~a) begin\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/implicit-port4.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #1 a = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/implicit-port4.v:18: Unsupported: Ignoring delay on this delayed statement.\n   #1 if (b !== a || d !== ~a) begin\n   ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
reg a;
wire b, d;
m foo(.*, .c(d));

initial begin
   a = 0;
   #1 if (b !== a || d !== ~a) begin
      $display("FAILED -- a=%b, b=%b, d=%b", a, b, d);
   end
   #1 a = 1;
   #1 if (b !== a || d !== ~a) begin
      $display("FAILED -- a=%b, b=%b, d=%b", a, b, d);
   end
   $display("PASSED");
end
endmodule
module top;

reg a;
wire b, d;
m foo(.*, .c(d));

initial begin
   a = 0;
   #1 if (b !== a || d !== ~a) begin
      $display("FAILED -- a=%b, b=%b, d=%b", a, b, d);
   end
   #1 a = 1;
   #1 if (b !== a || d !== ~a) begin
      $display("FAILED -- a=%b, b=%b, d=%b", a, b, d);
   end
   $display("PASSED");
end
endmodule