data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/xxs_to_xxf.v
1: b'%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/xxs_to_xxf.v:56: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'leading_zero\' generates 4 bits.\n                                                                                                                                : ... In instance xxs_to_xxf\n  wire [QWIDTH-1:0] shift = QWIDTH-leading_zero;\n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/xxs_to_xxf.v:56: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                                                                : ... In instance xxs_to_xxf\n  wire [QWIDTH-1:0] shift = QWIDTH-leading_zero;\n                          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/xxs_to_xxf.v:65: Cannot find file containing module: \'priority_encoder\'\n  priority_encoder #\n  ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200,data/full_repos/permissive/214858095/priority_encoder\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200,data/full_repos/permissive/214858095/priority_encoder.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200,data/full_repos/permissive/214858095/priority_encoder.sv\n             priority_encoder\n             priority_encoder.v\n             priority_encoder.sv\n             obj_dir/priority_encoder\n             obj_dir/priority_encoder.v\n             obj_dir/priority_encoder.sv\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/xxs_to_xxf.v:85: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                                                                : ... In instance xxs_to_xxf\n  assign exponent = is_zero ? 8\'h0 : BIAS + QWIDTH - RADIX - shift;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/xxs_to_xxf.v:85: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'shift\' generates 16 bits.\n                                                                                                                                : ... In instance xxs_to_xxf\n  assign exponent = is_zero ? 8\'h0 : BIAS + QWIDTH - RADIX - shift;\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/xxs_to_xxf.v:85: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                                : ... In instance xxs_to_xxf\n  assign exponent = is_zero ? 8\'h0 : BIAS + QWIDTH - RADIX - shift;\n                  ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module xxs_to_xxf
#(
  parameter FBITS = 32,
  parameter integer QWIDTH = 16
)
(
  input  [QWIDTH-1:0] i_fixed,
  output [FBITS-1:0]  o_float
);


  parameter MBITS = 23;


  parameter integer EBITS = 8;


  parameter integer RADIX = 15;


  parameter integer BIAS = (1 << EBITS -1) - 1;


  parameter         PADDING = {(MBITS-QWIDTH){1'b0}};


  wire              is_neg   = i_fixed[QWIDTH-1];

  wire              is_zero  = i_fixed == 'h0;

  wire [QWIDTH-1:0] abs      = is_neg ? ~i_fixed + 1 : i_fixed;

  wire [`log2(QWIDTH)-1:0] leading_zero;

  wire [QWIDTH-1:0] shift = QWIDTH-leading_zero;

  wire [QWIDTH-1:0] abs_shifted = abs << shift;

  wire [MBITS-1:0]  mantissa;
  wire [EBITS-1:0]  exponent;



  priority_encoder #
  (
    .WIDTH(QWIDTH)
  )
  pe0
  (
    .in(abs),
    .out(leading_zero)
  );


  generate
  if (MBITS > QWIDTH) begin
    assign mantissa = is_zero ? 23'h0 : {abs_shifted, PADDING};
  end
  else begin
    assign mantissa = abs_shifted[QWIDTH-1:QWIDTH-MBITS];
  end
  endgenerate

  assign exponent = is_zero ? 8'h0 : BIAS + QWIDTH - RADIX - shift;

  assign o_float = {is_neg, exponent, mantissa};
endmodule
module xxs_to_xxf
#(
  parameter FBITS = 32,
  parameter integer QWIDTH = 16
)
(
  input  [QWIDTH-1:0] i_fixed,
  output [FBITS-1:0]  o_float
);



  parameter MBITS = 23;


  parameter integer EBITS = 8;


  parameter integer RADIX = 15;


  parameter integer BIAS = (1 << EBITS -1) - 1;


  parameter         PADDING = {(MBITS-QWIDTH){1'b0}};


  wire              is_neg   = i_fixed[QWIDTH-1];

  wire              is_zero  = i_fixed == 'h0;

  wire [QWIDTH-1:0] abs      = is_neg ? ~i_fixed + 1 : i_fixed;

  wire [`log2(QWIDTH)-1:0] leading_zero;

  wire [QWIDTH-1:0] shift = QWIDTH-leading_zero;

  wire [QWIDTH-1:0] abs_shifted = abs << shift;

  wire [MBITS-1:0]  mantissa;
  wire [EBITS-1:0]  exponent;



  priority_encoder #
  (
    .WIDTH(QWIDTH)
  )
  pe0
  (
    .in(abs),
    .out(leading_zero)
  );


  generate
  if (MBITS > QWIDTH) begin
    assign mantissa = is_zero ? 23'h0 : {abs_shifted, PADDING};
  end
  else begin
    assign mantissa = abs_shifted[QWIDTH-1:QWIDTH-MBITS];
  end
  endgenerate

  assign exponent = is_zero ? 8'h0 : BIAS + QWIDTH - RADIX - shift;

  assign o_float = {is_neg, exponent, mantissa};
endmodule