data/full_repos/permissive/119715647/sim/ScoreBoard/ScoreBoard.v
1: b'%Warning-WIDTH: data/full_repos/permissive/119715647/sim/ScoreBoard/ScoreBoard.v:44: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'SCOREBARD\' generates 32 or 2 bits.\n                                                                                   : ... In instance ScoreBoard\n      STATE <= SCOREBARD;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/119715647/sim/ScoreBoard/ScoreBoard.v:50: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'DELAY\' generates 32 or 3 bits.\n                                                                                   : ... In instance ScoreBoard\n      STATE <= DELAY; \n            ^~\n%Warning-WIDTH: data/full_repos/permissive/119715647/sim/ScoreBoard/ScoreBoard.v:71: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'DELAY\' generates 32 or 3 bits.\n                                                                                   : ... In instance ScoreBoard\n      STATE <= DELAY;  \n            ^~\n%Warning-WIDTH: data/full_repos/permissive/119715647/sim/ScoreBoard/ScoreBoard.v:78: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'DELAY1\' generates 32 or 3 bits.\n                                                                                   : ... In instance ScoreBoard\n     STATE <= DELAY1; \n           ^~\n%Warning-WIDTH: data/full_repos/permissive/119715647/sim/ScoreBoard/ScoreBoard.v:82: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'SCOREBARD\' generates 32 or 2 bits.\n                                                                                   : ... In instance ScoreBoard\n      STATE <= SCOREBARD;  \n            ^~\n%Warning-WIDTH: data/full_repos/permissive/119715647/sim/ScoreBoard/ScoreBoard.v:85: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'UPDATE\' generates 32 or 2 bits.\n                                                                                   : ... In instance ScoreBoard\n      STATE <= UPDATE;  \n            ^~\n%Warning-WIDTH: data/full_repos/permissive/119715647/sim/ScoreBoard/ScoreBoard.v:33: Operator CASE expects 32 or 3 bits on the Case expression, but Case expression\'s VARREF \'STATE\' generates 1 bits.\n                                                                                   : ... In instance ScoreBoard\n   case(STATE)\n   ^~~~\n%Error: Exiting due to 7 warning(s)\n'
module ScoreBoard(
	input [0:0] clk, 
	input [0:0] rst, 
	input [15:0] userid, 
	input [1:0] game_state, 
	input [15:0] score_data,
	input [15:0] ram_data,
	output reg [31:0] scoreboard_output, 
	output reg [0:0] scoreboard_parity,
	output reg [0:0] wren, 
	output reg [15:0] address,
	output reg [15:0] data
	); 


	reg [1:0] game_state_reg; 

	parameter INIT=1, 
			  UPDATE=2,
			  SCOREBARD=3,
			  DELAY  = 4, 
			  DELAY1 = 5; 


	reg [0:0] STATE; 
	always@(posedge clk) begin
		if(!rst) begin
			STATE <= INIT;
		end else begin
			case(STATE)
				INIT: begin
					scoreboard_output <= 0; 
					wren <= 0;  
					address <= 0; 
					data <= 0;
					game_state_reg <= game_state;
					if (game_state_reg === 2'b10) begin
						data <= 0; 
						wren <= 0; 
						address <= 0; 
						STATE <= SCOREBARD;
					end
					else if (game_state_reg === 2'b01) begin
						data <= score_data;
						address <= userid;  
						wren <=1; 
						STATE <= DELAY; 
					end
					else begin
						STATE <= INIT;
					end
				end
				UPDATE: begin
					address <=0; 
					data <= 0; 
					wren <= 0; 
					game_state_reg <= 0; 
					STATE <= INIT; 
				end
				SCOREBARD: begin
					address <=0; 
					data <= 0; 
					wren <= 0;
					if(address !== 16'hFFFF) begin
						scoreboard_output <= {address,ram_data};
						scoreboard_parity <= ~scoreboard_parity; 
						address <= address + 1'b1;
						STATE <= DELAY;  
					end else begin
						scoreboard_output <= {16'hFFFF,16'hFFFF};
						STATE <= INIT; 
					end
				end
				DELAY: begin
					STATE <= DELAY1; 
				end
				DELAY1: begin
					if (game_state === 2'b10) begin
						STATE <= SCOREBARD;
					end
					else if (game_state === 2'b01) begin
						STATE <= UPDATE;
					end
					else begin
						STATE <= INIT;
					end
				end
				default:begin
					STATE <= INIT;
				end
			endcase
		end
	end
endmodule
module ScoreBoard(
	input [0:0] clk, 
	input [0:0] rst, 
	input [15:0] userid, 
	input [1:0] game_state, 
	input [15:0] score_data,
	input [15:0] ram_data,
	output reg [31:0] scoreboard_output, 
	output reg [0:0] scoreboard_parity,
	output reg [0:0] wren, 
	output reg [15:0] address,
	output reg [15:0] data
	);
 


	reg [1:0] game_state_reg; 

	parameter INIT=1, 
			  UPDATE=2,
			  SCOREBARD=3,
			  DELAY  = 4, 
			  DELAY1 = 5; 


	reg [0:0] STATE; 
	always@(posedge clk) begin
		if(!rst) begin
			STATE <= INIT;
		end else begin
			case(STATE)
				INIT: begin
					scoreboard_output <= 0; 
					wren <= 0;  
					address <= 0; 
					data <= 0;
					game_state_reg <= game_state;
					if (game_state_reg === 2'b10) begin
						data <= 0; 
						wren <= 0; 
						address <= 0; 
						STATE <= SCOREBARD;
					end
					else if (game_state_reg === 2'b01) begin
						data <= score_data;
						address <= userid;  
						wren <=1; 
						STATE <= DELAY; 
					end
					else begin
						STATE <= INIT;
					end
				end
				UPDATE: begin
					address <=0; 
					data <= 0; 
					wren <= 0; 
					game_state_reg <= 0; 
					STATE <= INIT; 
				end
				SCOREBARD: begin
					address <=0; 
					data <= 0; 
					wren <= 0;
					if(address !== 16'hFFFF) begin
						scoreboard_output <= {address,ram_data};
						scoreboard_parity <= ~scoreboard_parity; 
						address <= address + 1'b1;
						STATE <= DELAY;  
					end else begin
						scoreboard_output <= {16'hFFFF,16'hFFFF};
						STATE <= INIT; 
					end
				end
				DELAY: begin
					STATE <= DELAY1; 
				end
				DELAY1: begin
					if (game_state === 2'b10) begin
						STATE <= SCOREBARD;
					end
					else if (game_state === 2'b01) begin
						STATE <= UPDATE;
					end
					else begin
						STATE <= INIT;
					end
				end
				default:begin
					STATE <= INIT;
				end
			endcase
		end
	end
endmodule