data/full_repos/permissive/196705942/src/conjugate.v
data/verilator_xmls/ede046f5-3241-4e98-a925-b5db813a587f.xml
module conj(ar,ai,br,bi);
    input [31:0] ar,ai;
    output [31:0] br,bi;
    wire [31:0] d;
    assign br=ar;
    assign d={~ai[31],ai[30:0]};
    assign bi=(ai==32'b0)? 32'b0 : d ;
endmodule
module conj(ar,ai,br,bi);

    input [31:0] ar,ai;
    output [31:0] br,bi;
    wire [31:0] d;
    assign br=ar;
    assign d={~ai[31],ai[30:0]};
    assign bi=(ai==32'b0)? 32'b0 : d ;
endmodule