data/full_repos/permissive/174242803/datapath/src/datapath_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:49: Unsupported or unknown PLI call: $monitor\n      $monitor ("CLK= %b, instruction= %b", clk, instr ) ;\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_P $display ("reset now clocked in" ) ; \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_P irwrite <=4\'b0010 ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_P irwrite <=4\'b0100 ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_P irwrite <=4\'b1000 ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n      regwrite = 1\'b1; #1; regwrite = 1\'b0;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n      alusrca = 1; alusrcb = 2\'b00; alucontrol = 3\'b010; #5;\n                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n      regdst = 1\'b1; regwrite = 1\'b1; #1;\n                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_P $finish ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_H clk = ~clk;\n      ^\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:109: Unsupported or unknown PLI call: $shm_open\n      $shm_open("shm.db");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:110: Unsupported or unknown PLI call: $shm_probe\n      $shm_probe(test, "AS");\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/174242803/datapath/src/datapath_tb.v:111: Unsupported or unknown PLI call: $shm_save\n      $shm_save;\n      ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test () ;

   parameter CLK_H = 20 ;
   parameter CLK_P = 40 ;


   reg  [2:0]  alucontrol ;
   reg         alusrca    ;
   reg  [1:0]  alusrcb    ;
   reg 	       iord       ;
   reg  [3:0]  irwrite    ;
   reg  [7:0]  memdata    ;
   reg 	       memtoreg   ;
   reg         pcen       ;
   reg 	       regdst     ;
   reg 	       regwrite   ;
   reg  [1:0]  pcsource   ;
   reg         clk, reset ;  


   wire [ 7:0] adr        ;
   wire [31:0] instr      ;
   wire [ 7:0] writedata  ;
   wire        zero       ;


   datapath myDatapath (.adr(adr),
                        .instr(instr), 
                        .writedata(writedata), 
                        .zero(zero), 
                        .alucontrol(alucontrol), 
                        .alusrca(alusrca), 
                        .alusrcb(alusrcb), 
                        .iord(iord), 
                        .irwrite(irwrite), 
                        .memdata(memdata), 
		                  .memtoreg(memtoreg), 
                        .pcen(pcen), 
                        .pcsource(pcsource), 
                        .regdst(regdst), 
                        .regwrite(regwrite),
		                  .clk(clk), 
                        .reset(reset)
                       );

   initial begin
      $monitor ("CLK= %b, instruction= %b", clk, instr ) ;

      clk <= 0 ; reset <= 1 ; alucontrol <=3'b0 ; alusrca <=0 ;  alusrcb <= 2'b0 ; iord <=0 ; irwrite <= 4'b0 ;
      memtoreg <=0 ; pcen <=0 ; regdst <=0 ; regwrite <=0 ; pcsource <=2'b0 ; memdata<=8'b0 ;


      #CLK_P $display ("reset now clocked in" ) ; 
      reset <= 0 ;



      irwrite <= 4'b0001 ;
      memdata <= 8'b00100000 ;


      #CLK_P irwrite <=4'b0010 ;
      memdata <= 8'b00001000 ;


      #CLK_P irwrite <=4'b0100 ;
      memdata <= 8'b01000011 ;


      #CLK_P irwrite <=4'b1000 ;
      memdata <= 8'b00000000 ;


      if (instr == 32'b00000000010000110000100000100000) begin
         $display("Instruction fully loaded!");
      end


      if (myDatapath.pc == myDatapath.nextpc) begin
         $display("PC set to next PC!");
      end




      regwrite = 1'b1; #1; regwrite = 1'b0;


      alusrca = 1; alusrcb = 2'b00; alucontrol = 3'b010; #5;
      alusrca = 0; alusrcb = 2'b00; alucontrol = 3'b000;


      regdst = 1'b1; regwrite = 1'b1; #1;



      #CLK_P $finish ;

   end


   always 
      #CLK_H clk = ~clk;


   initial begin
      $shm_open("shm.db");
      $shm_probe(test, "AS");
      $shm_save;
   end

endmodule
module test () ;


   parameter CLK_H = 20 ;
   parameter CLK_P = 40 ;


   reg  [2:0]  alucontrol ;
   reg         alusrca    ;
   reg  [1:0]  alusrcb    ;
   reg 	       iord       ;
   reg  [3:0]  irwrite    ;
   reg  [7:0]  memdata    ;
   reg 	       memtoreg   ;
   reg         pcen       ;
   reg 	       regdst     ;
   reg 	       regwrite   ;
   reg  [1:0]  pcsource   ;
   reg         clk, reset ;  


   wire [ 7:0] adr        ;
   wire [31:0] instr      ;
   wire [ 7:0] writedata  ;
   wire        zero       ;


   datapath myDatapath (.adr(adr),
                        .instr(instr), 
                        .writedata(writedata), 
                        .zero(zero), 
                        .alucontrol(alucontrol), 
                        .alusrca(alusrca), 
                        .alusrcb(alusrcb), 
                        .iord(iord), 
                        .irwrite(irwrite), 
                        .memdata(memdata), 
		                  .memtoreg(memtoreg), 
                        .pcen(pcen), 
                        .pcsource(pcsource), 
                        .regdst(regdst), 
                        .regwrite(regwrite),
		                  .clk(clk), 
                        .reset(reset)
                       );

   initial begin
      $monitor ("CLK= %b, instruction= %b", clk, instr ) ;

      clk <= 0 ; reset <= 1 ; alucontrol <=3'b0 ; alusrca <=0 ;  alusrcb <= 2'b0 ; iord <=0 ; irwrite <= 4'b0 ;
      memtoreg <=0 ; pcen <=0 ; regdst <=0 ; regwrite <=0 ; pcsource <=2'b0 ; memdata<=8'b0 ;


      #CLK_P $display ("reset now clocked in" ) ; 
      reset <= 0 ;



      irwrite <= 4'b0001 ;
      memdata <= 8'b00100000 ;


      #CLK_P irwrite <=4'b0010 ;
      memdata <= 8'b00001000 ;


      #CLK_P irwrite <=4'b0100 ;
      memdata <= 8'b01000011 ;


      #CLK_P irwrite <=4'b1000 ;
      memdata <= 8'b00000000 ;


      if (instr == 32'b00000000010000110000100000100000) begin
         $display("Instruction fully loaded!");
      end


      if (myDatapath.pc == myDatapath.nextpc) begin
         $display("PC set to next PC!");
      end




      regwrite = 1'b1; #1; regwrite = 1'b0;


      alusrca = 1; alusrcb = 2'b00; alucontrol = 3'b010; #5;
      alusrca = 0; alusrcb = 2'b00; alucontrol = 3'b000;


      regdst = 1'b1; regwrite = 1'b1; #1;



      #CLK_P $finish ;

   end


   always 
      #CLK_H clk = ~clk;


   initial begin
      $shm_open("shm.db");
      $shm_probe(test, "AS");
      $shm_save;
   end

endmodule