data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/byteEnable.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/byteEnable.v:1: Cannot find include file: Mips/Control/Signal/Memory/Signal/ByteEnable.v\n`include "Mips/Control/Signal/Memory/Signal/ByteEnable.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory,data/full_repos/permissive/131921633/Mips/Control/Signal/Memory/Signal/ByteEnable.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory,data/full_repos/permissive/131921633/Mips/Control/Signal/Memory/Signal/ByteEnable.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory,data/full_repos/permissive/131921633/Mips/Control/Signal/Memory/Signal/ByteEnable.v.sv\n             Mips/Control/Signal/Memory/Signal/ByteEnable.v\n             Mips/Control/Signal/Memory/Signal/ByteEnable.v.v\n             Mips/Control/Signal/Memory/Signal/ByteEnable.v.sv\n             obj_dir/Mips/Control/Signal/Memory/Signal/ByteEnable.v\n             obj_dir/Mips/Control/Signal/Memory/Signal/ByteEnable.v.v\n             obj_dir/Mips/Control/Signal/Memory/Signal/ByteEnable.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/byteEnable.v:4: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_T\'\n ( `Mips_Control_Signal_Memory_Signal_ByteEnable_T(input) control\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/byteEnable.v:4: syntax error, unexpected \'(\', expecting \'[\'\n ( `Mips_Control_Signal_Memory_Signal_ByteEnable_T(input) control\n                                                   ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/byteEnable.v:9: syntax error, unexpected always\nalways @(*)\n^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/byteEnable.v:11: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_None\'\n  `Mips_Control_Signal_Memory_Signal_ByteEnable_None : byteEnable$ = 4\'b0000;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/byteEnable.v:12: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_Byte\'\n  `Mips_Control_Signal_Memory_Signal_ByteEnable_Byte : byteEnable$ = 4\'b0001;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/byteEnable.v:13: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_Half\'\n  `Mips_Control_Signal_Memory_Signal_ByteEnable_Half : byteEnable$ = 4\'b0011;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/byteEnable.v:14: Define or directive not defined: \'`Mips_Control_Signal_Memory_Signal_ByteEnable_Word\'\n  `Mips_Control_Signal_Memory_Signal_ByteEnable_Word : byteEnable$ = 4\'b1111;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module Mips_Datapath_Memory_byteEnable
	( `Mips_Control_Signal_Memory_Signal_ByteEnable_T(input) control
	, output [3:0] byteEnable
	);

reg [3:0] byteEnable$;
always @(*)
	case(control)
		`Mips_Control_Signal_Memory_Signal_ByteEnable_None : byteEnable$ = 4'b0000;
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Byte : byteEnable$ = 4'b0001;
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Half : byteEnable$ = 4'b0011;
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Word : byteEnable$ = 4'b1111;
		default                                            : byteEnable$ = 4'b0000;
	endcase
assign byteEnable = byteEnable$;

endmodule
module Mips_Datapath_Memory_byteEnable
	( `Mips_Control_Signal_Memory_Signal_ByteEnable_T(input) control
	, output [3:0] byteEnable
	);


reg [3:0] byteEnable$;
always @(*)
	case(control)
		`Mips_Control_Signal_Memory_Signal_ByteEnable_None : byteEnable$ = 4'b0000;
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Byte : byteEnable$ = 4'b0001;
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Half : byteEnable$ = 4'b0011;
		`Mips_Control_Signal_Memory_Signal_ByteEnable_Word : byteEnable$ = 4'b1111;
		default                                            : byteEnable$ = 4'b0000;
	endcase
assign byteEnable = byteEnable$;

endmodule