data/full_repos/permissive/123690745/mips.v
1: b"%Error: data/full_repos/permissive/123690745/mips.v:72: Cannot find file containing module: 'core'\n core CPU (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/core\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/core.v\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/core.sv\n             core\n             core.v\n             core.sv\n             obj_dir/core\n             obj_dir/core.v\n             obj_dir/core.sv\n%Error: data/full_repos/permissive/123690745/mips.v:87: Cannot find file containing module: 'Bridge'\n Bridge Bridge (\n ^~~~~~\n%Error: data/full_repos/permissive/123690745/mips.v:109: Cannot find file containing module: 'TC'\n TC Timer0 (\n ^~\n%Error: data/full_repos/permissive/123690745/mips.v:119: Cannot find file containing module: 'TC'\n TC Timer1 (\n ^~\n%Error: data/full_repos/permissive/123690745/mips.v:134: Cannot find file containing module: 'TubeDriver'\n TubeDriver TubeDriver (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/123690745/mips.v:148: Cannot find file containing module: 'SwitchReceiver'\n SwitchReceiver SwitchReceiver (\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/123690745/mips.v:163: Cannot find file containing module: 'LEDDriver'\n LEDDriver LEDDriver (\n ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module mips
	(input clk,input clk2, input reset,
	 output [7:0] digital_tube0,
	 output [7:0] digital_tube1,
	 output [7:0] digital_tube2,
	 output [3:0] digital_tube_sel0,
	 output [3:0] digital_tube_sel1,
	 output digital_tube_sel2,
	 
	 output [31:0] led_light,
	 
	 input [7:0] dip_switch0,
	 input [7:0] dip_switch1,
	 input [7:0] dip_switch2,
	 input [7:0] dip_switch3,
	 
	 input [7:0] dip_switch4,
	 input [7:0] dip_switch5,
	 input [7:0] dip_switch6,
	 input [7:0] dip_switch7,
	 
	 input [7:0] user_key
	);


	
	wire MemWriteM;
	wire [31:0] CPUAddress;
	wire [31:0] DevAddress;
	
	wire [31:0] CPUWD;
	wire [31:0] DevWD;
	wire [5:0] DevWE;
	
	wire [31:0] DevRD;
	wire [31:0] CPURD;
	
	wire MemorySelectM;
	
	wire [7:2]DevInterruptRequest;
	wire [7:2]CP0InterruptRequest;
	
	wire WE0, WE1, WE2, WE3;
	
	wire [31:0] PCM;


	core CPU (
		.clk(clk),
		.clk2(clk2),
		.reset(reset),
		.MemWriteM(MemWriteM),
		.CPUAddress(CPUAddress),
		.CPUWD(CPUWD),
		.CPURD(CPURD),
		.MemorySelectM(MemorySelectM),
		.CP0InterruptRequest(CP0InterruptRequest),
		.PCM(PCM)
	);



	Bridge Bridge (
		.MemWriteM(MemWriteM),
		.CPUAddress(CPUAddress),
		.DevAddress(DevAddress),

		.CPUWD(CPUWD),
		.DevWD(DevWD),
		.DevWE(DevWE),
	 
		.DevRD(DevRD),
		.CPURD(CPURD),
	 
		.MemorySelectM(MemorySelectM),
	 
		.DevInterruptRequest(DevInterruptRequest),
		.CP0InterruptRequest(CP0InterruptRequest)
	 );
	 
	wire [31:0] DataRD0;
	wire [31:0] DataRD1;
	wire [31:0] DataRD2;

	TC Timer0 (
		.clk(clk), 
		.reset(reset), 
		.PrAddr(DevAddress[3:2]), 
		.WE(WE0), 
		.DataIn(DevWD), 
		.DataOut(DataRD0), 
		.InterruptRequest(DevInterruptRequest[2])
	);

	TC Timer1 (
		.clk(clk), 
		.reset(reset), 
		.PrAddr(DevAddress[3:2]), 
		.WE(WE1), 
		.DataIn(DevWD), 
		.DataOut(DataRD1), 
		.InterruptRequest(DevInterruptRequest[3])
	);
	

	
	TubeDriver TubeDriver (
    .clk(clk), 
    .reset(reset), 
    .Call(DevInterruptRequest[2]), 
    .WE(WE2), 
    .DataIn(DevWD), 
    .tube0sel(digital_tube_sel0), 
    .tube1sel(digital_tube_sel1), 
    .tube2sel(digital_tube_sel2), 
    .tube0(digital_tube0), 
    .tube1(digital_tube1), 
    .tube2(digital_tube2)
    );

	SwitchReceiver SwitchReceiver (
    .switch0(dip_switch0), 
    .switch1(dip_switch1), 
    .switch2(dip_switch2), 
    .switch3(dip_switch3), 
    .switch4(dip_switch4), 
    .switch5(dip_switch5), 
    .switch6(dip_switch6), 
    .switch7(dip_switch7),

	 .userkey(user_key),
    .Address(CPUAddress[7:0]), 
    .DataOut(DataRD2)
    );
	 
	LEDDriver LEDDriver (
    .clk(clk), 
    .reset(reset), 
    .DataIn(DevWD), 
    .Drive(led_light), 
    .WE(WE3)
    );


	
	assign {WE3,WE2,WE1,WE0} = DevWE[3:0];
	
	assign DevRD = DevAddress[7:4] == 0 ? DataRD0 : 
						DevAddress[7:4] == 1 ? DataRD1 :
						DataRD2;
		
	assign DevInterruptRequest[7:4] = 0;

endmodule
module mips
	(input clk,input clk2, input reset,
	 output [7:0] digital_tube0,
	 output [7:0] digital_tube1,
	 output [7:0] digital_tube2,
	 output [3:0] digital_tube_sel0,
	 output [3:0] digital_tube_sel1,
	 output digital_tube_sel2,
	 
	 output [31:0] led_light,
	 
	 input [7:0] dip_switch0,
	 input [7:0] dip_switch1,
	 input [7:0] dip_switch2,
	 input [7:0] dip_switch3,
	 
	 input [7:0] dip_switch4,
	 input [7:0] dip_switch5,
	 input [7:0] dip_switch6,
	 input [7:0] dip_switch7,
	 
	 input [7:0] user_key
	);



	
	wire MemWriteM;
	wire [31:0] CPUAddress;
	wire [31:0] DevAddress;
	
	wire [31:0] CPUWD;
	wire [31:0] DevWD;
	wire [5:0] DevWE;
	
	wire [31:0] DevRD;
	wire [31:0] CPURD;
	
	wire MemorySelectM;
	
	wire [7:2]DevInterruptRequest;
	wire [7:2]CP0InterruptRequest;
	
	wire WE0, WE1, WE2, WE3;
	
	wire [31:0] PCM;


	core CPU (
		.clk(clk),
		.clk2(clk2),
		.reset(reset),
		.MemWriteM(MemWriteM),
		.CPUAddress(CPUAddress),
		.CPUWD(CPUWD),
		.CPURD(CPURD),
		.MemorySelectM(MemorySelectM),
		.CP0InterruptRequest(CP0InterruptRequest),
		.PCM(PCM)
	);



	Bridge Bridge (
		.MemWriteM(MemWriteM),
		.CPUAddress(CPUAddress),
		.DevAddress(DevAddress),

		.CPUWD(CPUWD),
		.DevWD(DevWD),
		.DevWE(DevWE),
	 
		.DevRD(DevRD),
		.CPURD(CPURD),
	 
		.MemorySelectM(MemorySelectM),
	 
		.DevInterruptRequest(DevInterruptRequest),
		.CP0InterruptRequest(CP0InterruptRequest)
	 );
	 
	wire [31:0] DataRD0;
	wire [31:0] DataRD1;
	wire [31:0] DataRD2;

	TC Timer0 (
		.clk(clk), 
		.reset(reset), 
		.PrAddr(DevAddress[3:2]), 
		.WE(WE0), 
		.DataIn(DevWD), 
		.DataOut(DataRD0), 
		.InterruptRequest(DevInterruptRequest[2])
	);

	TC Timer1 (
		.clk(clk), 
		.reset(reset), 
		.PrAddr(DevAddress[3:2]), 
		.WE(WE1), 
		.DataIn(DevWD), 
		.DataOut(DataRD1), 
		.InterruptRequest(DevInterruptRequest[3])
	);
	

	
	TubeDriver TubeDriver (
    .clk(clk), 
    .reset(reset), 
    .Call(DevInterruptRequest[2]), 
    .WE(WE2), 
    .DataIn(DevWD), 
    .tube0sel(digital_tube_sel0), 
    .tube1sel(digital_tube_sel1), 
    .tube2sel(digital_tube_sel2), 
    .tube0(digital_tube0), 
    .tube1(digital_tube1), 
    .tube2(digital_tube2)
    );

	SwitchReceiver SwitchReceiver (
    .switch0(dip_switch0), 
    .switch1(dip_switch1), 
    .switch2(dip_switch2), 
    .switch3(dip_switch3), 
    .switch4(dip_switch4), 
    .switch5(dip_switch5), 
    .switch6(dip_switch6), 
    .switch7(dip_switch7),

	 .userkey(user_key),
    .Address(CPUAddress[7:0]), 
    .DataOut(DataRD2)
    );
	 
	LEDDriver LEDDriver (
    .clk(clk), 
    .reset(reset), 
    .DataIn(DevWD), 
    .Drive(led_light), 
    .WE(WE3)
    );


	
	assign {WE3,WE2,WE1,WE0} = DevWE[3:0];
	
	assign DevRD = DevAddress[7:4] == 0 ? DataRD0 : 
						DevAddress[7:4] == 1 ? DataRD1 :
						DataRD2;
		
	assign DevInterruptRequest[7:4] = 0;

endmodule