data/full_repos/permissive/176378198/src/control_logic.v
 line:1 column:1: Illegal character '\x00'
1: b'%Error: data/full_repos/permissive/176378198/src/control_logic.v:6: Cannot find include file: instruction_decoder.v\n`include "instruction_decoder.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/176378198/src,data/full_repos/permissive/176378198/instruction_decoder.v\n             data/full_repos/permissive/176378198/src,data/full_repos/permissive/176378198/instruction_decoder.v.v\n             data/full_repos/permissive/176378198/src,data/full_repos/permissive/176378198/instruction_decoder.v.sv\n             instruction_decoder.v\n             instruction_decoder.v.v\n             instruction_decoder.v.sv\n             obj_dir/instruction_decoder.v\n             obj_dir/instruction_decoder.v.v\n             obj_dir/instruction_decoder.v.sv\n%Error: Exiting due to 1 error(s)\n'
module control_logic (
    input clk,
    input rst,

    input [3 : 0] IR_MSB4,

    output HLT,
    output MI,
    output RI,
    output RO,
    output IO,
    output II,
    output AI,
    output AO,
    output EO,
    output SU,
    output BI,
    output OI,
    output CE,
    output CO,
    output J
);

    reg [2:0] microcode_count;
    always @(posedge clk) begin
        if (rst)
            microcode_count <= 0;
        else if (microcode_count == 3'b100)
            microcode_count <= 0;
        else
            microcode_count <= microcode_count + 1;
    end

    wire [7 : 0] instr_decoder_addr;
    assign instr_decoder_addr = {
        IR_MSB4[3 : 0],
        1'b0,
        microcode_count[2 : 0]
    };

    instruction_decoder instr_decoder_inst (
        .clk(control_clk),
        .address(instr_decoder_addr),
        .HLT(HLT),
        .MI(MI),
        .RI(RI),
        .RO(RO),
        .IO(IO),
        .II(II),
        .AI(AI),
        .AO(AO),
        .EO(EO),
        .SU(SU),
        .BI(BI),
        .OI(OI),
        .CE(CE),
        .CO(CO),
        .J(J)
    );

endmodule
module control_logic (
    input clk,
    input rst,

    input [3 : 0] IR_MSB4,

    output HLT,
    output MI,
    output RI,
    output RO,
    output IO,
    output II,
    output AI,
    output AO,
    output EO,
    output SU,
    output BI,
    output OI,
    output CE,
    output CO,
    output J
);


    reg [2:0] microcode_count;
    always @(posedge clk) begin
        if (rst)
            microcode_count <= 0;
        else if (microcode_count == 3'b100)
            microcode_count <= 0;
        else
            microcode_count <= microcode_count + 1;
    end

    wire [7 : 0] instr_decoder_addr;
    assign instr_decoder_addr = {
        IR_MSB4[3 : 0],
        1'b0,
        microcode_count[2 : 0]
    };

    instruction_decoder instr_decoder_inst (
        .clk(control_clk),
        .address(instr_decoder_addr),
        .HLT(HLT),
        .MI(MI),
        .RI(RI),
        .RO(RO),
        .IO(IO),
        .II(II),
        .AI(AI),
        .AO(AO),
        .EO(EO),
        .SU(SU),
        .BI(BI),
        .OI(OI),
        .CE(CE),
        .CO(CO),
        .J(J)
    );

endmodule