data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pid.v
 line:78: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pid.v:66: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pid.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #(stimDelay)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pid.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #(stimDelay);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pid.v:80: Unsupported: Ignoring delay on this delayed statement.\n   #(stimDelay) e_in = e_in + 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/159096530/HPS_CONTROL_FPGA_LED/pid.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #100;  \n  ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PID_testbench;
	reg clk, reset;
	reg [31:0] e_in;



	wire [31:0] u_out;
	
	parameter k1 = 1;
	parameter k2 = 0;
	parameter k3 = 0;
	
	parameter stimDelay = 10;
	
	PID myPID(	u_out,
	e_in,
	clk,
	reset,
	k1,
	k2,
	k3);

	always #1 clk = ~clk;

	initial
	begin
		clk = 0; e_in = 0; reset = 0;
		
		
		#(stimDelay)
		reset = 1;
		#(stimDelay);
		reset = 0;
		
		repeat(10)
		begin
			#(stimDelay) e_in = e_in + 1;
		end
		
		
		#100;
	end
endmodule
module PID_testbench;

	reg clk, reset;
	reg [31:0] e_in;



	wire [31:0] u_out;
	
	parameter k1 = 1;
	parameter k2 = 0;
	parameter k3 = 0;
	
	parameter stimDelay = 10;
	
	PID myPID(	u_out,
	e_in,
	clk,
	reset,
	k1,
	k2,
	k3);

	always #1 clk = ~clk;

	initial
	begin
		clk = 0; e_in = 0; reset = 0;
		
		
		#(stimDelay)
		reset = 1;
		#(stimDelay);
		reset = 0;
		
		repeat(10)
		begin
			#(stimDelay) e_in = e_in + 1;
		end
		
		
		#100;
	end
endmodule