data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/general/sim_file_io.svh
 line:11: before: "typedef"
data/verilator_xmls/9a97c5e6-126e-4508-894c-6f3081eab81f.xml
function logic [DWIDTH-1:0] readline();
    automatic logic [DWIDTH-1:0] word = 64'h0;
    automatic integer status;

    if (FORMAT == HEX)
      status = $fscanf(handle, "%x\n", word);
    else if (FORMAT == DEC)
      status = $fscanf(handle, "%d\n", word);
    else if (FORMAT == OCT)
      status = $fscanf(handle, "%o\n", word);
    else if (FORMAT == BIN)
      status = $fscanf(handle, "%b\n", word);
    else if (FORMAT == DEC)
      status = $fscanf(handle, "%g\n", word);
    else
      $error("Invalid format");

    return word;
  endfunction
function logic [DWIDTH-1:0] readline();

    automatic logic [DWIDTH-1:0] word = 64'h0;
    automatic integer status;

    if (FORMAT == HEX)
      status = $fscanf(handle, "%x\n", word);
    else if (FORMAT == DEC)
      status = $fscanf(handle, "%d\n", word);
    else if (FORMAT == OCT)
      status = $fscanf(handle, "%o\n", word);
    else if (FORMAT == BIN)
      status = $fscanf(handle, "%b\n", word);
    else if (FORMAT == DEC)
      status = $fscanf(handle, "%g\n", word);
    else
      $error("Invalid format");

    return word;
  endfunction