data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v
 line:119: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #5 rst  = 1\'b0; \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #5 valid = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #5 dato0 = 8\'b00100000;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #5dato0 = 8\'b00000000;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #5 valid = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #5 KI = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #5 valid = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #5dato0 = 8\'b01111111;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #5dato0 = 8\'b01111110;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #5 valid = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #5 valid = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #25dato0 = 8\'b01111111;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #45dato0 = 8\'b01111110;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #30dato0 = 8\'b01111111;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #20dato0 = 8\'b01111110;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #15dato0 = 8\'b01111101;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #10dato0 = 8\'b01111110;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #5dato0 = 8\'b01111111;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:108: Unsupported: Ignoring delay on this delayed statement.\n    #10 valid = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:119: Unsupported: Ignoring delay on this delayed statement.\n #20 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:122: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 CLK100MHZ = ~CLK100MHZ;\n       ^\n%Error: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:124: Cannot find file containing module: \'Conv\'\nConv\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test,data/full_repos/permissive/105269489/Conv\n             data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test,data/full_repos/permissive/105269489/Conv.v\n             data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test,data/full_repos/permissive/105269489/Conv.sv\n             Conv\n             Conv.v\n             Conv.sv\n             obj_dir/Conv\n             obj_dir/Conv.v\n             obj_dir/Conv.sv\n%Error: Exiting due to 1 error(s), 21 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_Conv #(
    parameter BIT_LEN =`BIT_LEN,
    parameter CONV_LEN =`CONV_LEN,
    parameter CONV_LPOS = `CONV_LPOS,
    parameter M_LEN = `M_LEN
    )();







    reg signed [BIT_LEN-1:0]dato0;
    reg signed [BIT_LEN-1:0]dato1;
    reg signed [BIT_LEN-1:0]dato2;
    reg CLK100MHZ;
    reg KI;
    reg rst;
    reg valid;
    wire [CONV_LPOS-1:0] data;
    
initial begin
    CLK100MHZ	= 1'b1;
    dato0 = 8'b00000000;
    dato1 = 8'b00100000;
    dato2 = 8'b00000000;
    rst = 1'b1;
    valid = 1'b0;
    KI = 1'b0;
    #5 rst	 = 1'b0;
    
    #5 valid = 1'b1;


    #5 dato0 = 8'b00100000;
    dato1 = 8'b10000000;
    dato2 = 8'b00100000;

    
    #5dato0 = 8'b00000000;
    dato1 = 8'b00100000;
    dato2 = 8'b00000000;


    #5 valid = 1'b0;
    

    #5 KI = 1'b1;
    #5 valid = 1'b1;
    dato0 = 8'b01111111;
    dato1 = 8'b01111111; 
    dato2 = 8'b01111111;

    
    #5dato0 = 8'b01111111;
    dato1 = 8'b01111111;
    dato2 = 8'b01111111;

    
    #5dato0 = 8'b01111110;
    dato1 = 8'b01111110;
    dato2 = 8'b01111110;


    #5 valid = 1'b0;


    #5 valid = 1'b1;

    #25dato0 = 8'b01111111;
    dato1 = 8'b01111111; 
    dato2 = 8'b01111111; 
    
    #45dato0 = 8'b01111110;
    dato1 = 8'b01111110;
    dato2 = 8'b01111110;

    #30dato0 = 8'b01111111;
    dato1 = 8'b01111111; 
    dato2 = 8'b01111111; 

    #20dato0 = 8'b01111110;
    dato1 = 8'b01111110;
    dato2 = 8'b01111110;

    #15dato0 = 8'b01111101;
    dato1 = 8'b01111101;
    dato2 = 8'b01111101;

    #10dato0 = 8'b01111110;
    dato1 = 8'b01111110;
    dato2 = 8'b01111110;

    #5dato0 = 8'b01111111;
    dato1 = 8'b01111111; 
    dato2 = 8'b01111111; 

    #10 valid = 1'b0;
    KI = 1'b0;


	#20	$finish;

end
always #2.5 CLK100MHZ = ~CLK100MHZ;

Conv
    u_conv(.i_dato0(dato0), 
           .i_dato1(dato1), 
           .i_dato2(dato2), 
           .i_selecK_I(KI), 
           .i_reset(rst), 
           .i_valid(valid),
           .CLK100MHZ(CLK100MHZ), 
           .o_data(data));


endmodule
module test_Conv #(
    parameter BIT_LEN =`BIT_LEN,
    parameter CONV_LEN =`CONV_LEN,
    parameter CONV_LPOS = `CONV_LPOS,
    parameter M_LEN = `M_LEN
    )();








    reg signed [BIT_LEN-1:0]dato0;
    reg signed [BIT_LEN-1:0]dato1;
    reg signed [BIT_LEN-1:0]dato2;
    reg CLK100MHZ;
    reg KI;
    reg rst;
    reg valid;
    wire [CONV_LPOS-1:0] data;
    
initial begin
    CLK100MHZ	= 1'b1;
    dato0 = 8'b00000000;
    dato1 = 8'b00100000;
    dato2 = 8'b00000000;
    rst = 1'b1;
    valid = 1'b0;
    KI = 1'b0;
    #5 rst	 = 1'b0;
    
    #5 valid = 1'b1;


    #5 dato0 = 8'b00100000;
    dato1 = 8'b10000000;
    dato2 = 8'b00100000;

    
    #5dato0 = 8'b00000000;
    dato1 = 8'b00100000;
    dato2 = 8'b00000000;


    #5 valid = 1'b0;
    

    #5 KI = 1'b1;
    #5 valid = 1'b1;
    dato0 = 8'b01111111;
    dato1 = 8'b01111111; 
    dato2 = 8'b01111111;

    
    #5dato0 = 8'b01111111;
    dato1 = 8'b01111111;
    dato2 = 8'b01111111;

    
    #5dato0 = 8'b01111110;
    dato1 = 8'b01111110;
    dato2 = 8'b01111110;


    #5 valid = 1'b0;


    #5 valid = 1'b1;

    #25dato0 = 8'b01111111;
    dato1 = 8'b01111111; 
    dato2 = 8'b01111111; 
    
    #45dato0 = 8'b01111110;
    dato1 = 8'b01111110;
    dato2 = 8'b01111110;

    #30dato0 = 8'b01111111;
    dato1 = 8'b01111111; 
    dato2 = 8'b01111111; 

    #20dato0 = 8'b01111110;
    dato1 = 8'b01111110;
    dato2 = 8'b01111110;

    #15dato0 = 8'b01111101;
    dato1 = 8'b01111101;
    dato2 = 8'b01111101;

    #10dato0 = 8'b01111110;
    dato1 = 8'b01111110;
    dato2 = 8'b01111110;

    #5dato0 = 8'b01111111;
    dato1 = 8'b01111111; 
    dato2 = 8'b01111111; 

    #10 valid = 1'b0;
    KI = 1'b0;


	#20	$finish;

end
always #2.5 CLK100MHZ = ~CLK100MHZ;

Conv
    u_conv(.i_dato0(dato0), 
           .i_dato1(dato1), 
           .i_dato2(dato2), 
           .i_selecK_I(KI), 
           .i_reset(rst), 
           .i_valid(valid),
           .CLK100MHZ(CLK100MHZ), 
           .o_data(data));


endmodule