data/full_repos/permissive/122560566/FPU.srcs/sources_1/new/inst_decoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/122560566/FPU.srcs/sources_1/new/inst_decoder.v:49: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                                             : ... In instance inst_decoder\n            O_selD <= I_inst[10:8];\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/122560566/FPU.srcs/sources_1/new/inst_decoder.v:50: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                                             : ... In instance inst_decoder\n            O_selA <= I_inst[7:5];\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/122560566/FPU.srcs/sources_1/new/inst_decoder.v:51: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                                             : ... In instance inst_decoder\n            O_selB <= I_inst[4:2];\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/122560566/FPU.srcs/sources_1/new/inst_decoder.v:52: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                             : ... In instance inst_decoder\n            O_Imm <= I_inst[7:0];\n                  ^~\n%Error: Exiting due to 4 warning(s)\n'
module inst_decoder(
    input [15:0] I_inst,
    input I_clk,
    input I_en,
    output reg [4:0] O_aluop,
    output reg [15:0] O_Imm,
    output reg [3:0] O_selA,
    output reg [3:0] O_selB,
    output reg [3:0] O_selD,
    output reg O_regwe
    );
    
    initial begin

        O_aluop = 0;
        O_Imm = 0;
        O_selA = 0;
        O_selB = 0;
        O_selD = 0;
        O_regwe = 0;
    end  
    
    always @(negedge I_clk) begin
        if(I_en) begin

            O_aluop <= I_inst[15:11];
            O_selD <= I_inst[10:8];
            O_selA <= I_inst[7:5];
            O_selB <= I_inst[4:2];
            O_Imm <= I_inst[7:0];
            
            case(I_inst[15:12])
                4'b0111 : O_regwe <= 0;
                4'b1100 : O_regwe <= 0;
                4'b1101 : O_regwe <= 0;
                default : O_regwe <= 1;
            endcase
            
        end
    end
    
    
endmodule
module inst_decoder(
    input [15:0] I_inst,
    input I_clk,
    input I_en,
    output reg [4:0] O_aluop,
    output reg [15:0] O_Imm,
    output reg [3:0] O_selA,
    output reg [3:0] O_selB,
    output reg [3:0] O_selD,
    output reg O_regwe
    );

    
    initial begin

        O_aluop = 0;
        O_Imm = 0;
        O_selA = 0;
        O_selB = 0;
        O_selD = 0;
        O_regwe = 0;
    end  
    
    always @(negedge I_clk) begin
        if(I_en) begin

            O_aluop <= I_inst[15:11];
            O_selD <= I_inst[10:8];
            O_selA <= I_inst[7:5];
            O_selB <= I_inst[4:2];
            O_Imm <= I_inst[7:0];
            
            case(I_inst[15:12])
                4'b0111 : O_regwe <= 0;
                4'b1100 : O_regwe <= 0;
                4'b1101 : O_regwe <= 0;
                default : O_regwe <= 1;
            endcase
            
        end
    end
    
    
endmodule