data/full_repos/permissive/143278/ivltests/pr1869769.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1869769.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1 if ({eq,ne,gt,ge,lt,le} != 6\'b100101) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1869769.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #1 rl2 = -1.0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1869769.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #1 if ({eq,ne,gt,ge,lt,le} != 6\'b010011) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1869769.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #1 rl2 = 1.0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1869769.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #1 if ({eq,ne,gt,ge,lt,le} != 6\'b011100) begin\n    ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  real rl1, rl2;
  wire eq, ne, gt, ge, lt, le;
  reg passed = 1'b1;


  assign eq = rl2 == 0;

  assign ne = rl2 != rl1;
  assign gt = rl2 > rl1;
  assign ge = rl2 >= rl1;
  assign lt = rl2 < rl1;
  assign le = rl2 <= rl1;

  initial begin
    rl1 = 0.0;
    rl2 = 0.0;
    #1 if ({eq,ne,gt,ge,lt,le} != 6'b100101) begin
      $display("Failed: expected %b, received %b", 6'b100101,
               {eq,ne,gt,ge,lt,le});
      passed = 1'b0;
    end
    #1 rl2 = -1.0;
    #1 if ({eq,ne,gt,ge,lt,le} != 6'b010011) begin
      $display("Failed: expected %b, received %b", 6'b010011,
               {eq,ne,gt,ge,lt,le});
      passed = 1'b0;
    end
    #1 rl2 = 1.0;
    #1 if ({eq,ne,gt,ge,lt,le} != 6'b011100) begin
      $display("Failed: expected %b, received %b", 6'b001100,
               {eq,ne,gt,ge,lt,le});
      passed = 1'b0;
    end
    if (passed) $display("PASSED");
  end
endmodule
module top;

  real rl1, rl2;
  wire eq, ne, gt, ge, lt, le;
  reg passed = 1'b1;


  assign eq = rl2 == 0;

  assign ne = rl2 != rl1;
  assign gt = rl2 > rl1;
  assign ge = rl2 >= rl1;
  assign lt = rl2 < rl1;
  assign le = rl2 <= rl1;

  initial begin
    rl1 = 0.0;
    rl2 = 0.0;
    #1 if ({eq,ne,gt,ge,lt,le} != 6'b100101) begin
      $display("Failed: expected %b, received %b", 6'b100101,
               {eq,ne,gt,ge,lt,le});
      passed = 1'b0;
    end
    #1 rl2 = -1.0;
    #1 if ({eq,ne,gt,ge,lt,le} != 6'b010011) begin
      $display("Failed: expected %b, received %b", 6'b010011,
               {eq,ne,gt,ge,lt,le});
      passed = 1'b0;
    end
    #1 rl2 = 1.0;
    #1 if ({eq,ne,gt,ge,lt,le} != 6'b011100) begin
      $display("Failed: expected %b, received %b", 6'b001100,
               {eq,ne,gt,ge,lt,le});
      passed = 1'b0;
    end
    if (passed) $display("PASSED");
  end
endmodule