data/full_repos/permissive/117736309/clk_pixel.v
data/verilator_xmls/998db363-1c83-4f28-83ce-7f1bde3f4320.xml
module clk_pixel(
    input wire clk,
    output reg clk_pixel
);

    reg cnt;

    initial begin
        cnt <= 0;
        clk_pixel <= 0;
    end

    always @(posedge clk)
    begin
        if (cnt == 1)
            begin
                cnt <= 0;
                clk_pixel <= ~clk_pixel;
            end
        else
            cnt <= 1;
    end

endmodule
module clk_pixel(
    input wire clk,
    output reg clk_pixel
);


    reg cnt;

    initial begin
        cnt <= 0;
        clk_pixel <= 0;
    end

    always @(posedge clk)
    begin
        if (cnt == 1)
            begin
                cnt <= 0;
                clk_pixel <= ~clk_pixel;
            end
        else
            cnt <= 1;
    end

endmodule