data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog/okWireIn.v
1: b'%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog/okWireIn.v:19: Cannot find include file: parameters.v\n`include "parameters.v"  \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog,data/full_repos/permissive/120539939/parameters.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog,data/full_repos/permissive/120539939/parameters.v.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog,data/full_repos/permissive/120539939/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog/okWireIn.v:20: Cannot find include file: mappings.v\n`include "mappings.v" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module okWireIn(
	input  wire [112:0] okHE,
	input  wire [7:0]   ep_addr,
	output reg  [31:0]  ep_dataout
	);

`include "parameters.v" 
`include "mappings.v"

reg  [31:0] ep_datahold;

always @(posedge ti_clk) begin
	if ((ti_write == 1'b1) && (ti_addr == ep_addr)) ep_datahold = ti_datain;
	if (ti_wireupdate == 1'b1) ep_dataout = #TDOUT_DELAY ep_datahold;
	if (ti_reset == 1'b1) begin
		ep_datahold = #TDOUT_DELAY 0;
		ep_dataout  = 0;
	end
end
	

endmodule
module okWireIn(
	input  wire [112:0] okHE,
	input  wire [7:0]   ep_addr,
	output reg  [31:0]  ep_dataout
	);


`include "parameters.v" 
`include "mappings.v"

reg  [31:0] ep_datahold;

always @(posedge ti_clk) begin
	if ((ti_write == 1'b1) && (ti_addr == ep_addr)) ep_datahold = ti_datain;
	if (ti_wireupdate == 1'b1) ep_dataout = #TDOUT_DELAY ep_datahold;
	if (ti_reset == 1'b1) begin
		ep_datahold = #TDOUT_DELAY 0;
		ep_dataout  = 0;
	end
end
	

endmodule