data/full_repos/permissive/120518070/main/source/tb_mcu.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:27: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2.0);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:29: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2.0);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:60: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:62: Unsupported: Ignoring delay on this delayed statement.\n         #(CHECK_DELAY);\n         ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:67: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:77: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:79: Unsupported: Ignoring delay on this delayed statement.\n         #(CHECK_DELAY);\n         ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:84: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:92: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:94: Unsupported: Ignoring delay on this delayed statement.\n         #(CHECK_DELAY);\n         ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:99: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:108: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:110: Unsupported: Ignoring delay on this delayed statement.\n         #(CHECK_DELAY);\n         ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:115: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:124: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:126: Unsupported: Ignoring delay on this delayed statement.\n  #(CHECK_DELAY);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_mcu.sv:131: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: Exiting due to 10 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mcu ();



	localparam	CLK_PERIOD  = 35;
	localparam	CHECK_DELAY = 30;


	reg tb_clk, tb_n_rst;
	integer tb_test_num;
	reg tb_start, tb_RC4_done, tb_ED_done, tb_RC4_start, tb_ED_start, tb_process_complete;


	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2.0);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2.0);
	end


	mcu DUT
	(
		.clk(tb_clk),
		.n_rst(tb_n_rst),
		.start(tb_start),
		.RC4_done(tb_RC4_done),
		.ED_done(tb_ED_done),
		.RC4_start(tb_RC4_start),
		.ED_start(tb_ED_start),
		.process_complete(tb_process_complete)
	);


	initial
	begin

		tb_n_rst	= 1'b1;
		tb_start	= 1'b0;
		tb_RC4_done 	= 1'b0;
		tb_ED_done	= 1'b0;


		tb_test_num 	= 0;
		tb_start 	= 1'b0;
		tb_RC4_done 	= 1'b0;
		tb_ED_done	= 1'b0;
		tb_n_rst	= 1'b0;
		@(posedge tb_clk);
		@(posedge tb_clk);
       		#(CHECK_DELAY);
		if((tb_RC4_start != 1'b0) && (tb_ED_start != 1'b0) && (tb_process_complete != 1'b0))
			$error("Test case: FAILED");
		else
			$info("Test case: PASSED");
		@(posedge tb_clk);
		@(posedge tb_clk);
		


		tb_test_num 	= 1;
		tb_n_rst	= 1'b1;
		tb_start 	= 1'b0;
		tb_RC4_done 	= 1'b0;
		tb_ED_done	= 1'b0;
		@(posedge tb_clk);
		@(posedge tb_clk);
       		#(CHECK_DELAY);
		if((tb_RC4_start != 1'b0) && (tb_ED_start != 1'b0) && (tb_process_complete != 1'b0))
			$error("Test case: FAILED");
		else
			$info("Test case: PASSED");
		@(posedge tb_clk);
		@(posedge tb_clk);


		tb_test_num 	= 2;
		tb_start 	= 1'b1;
		tb_RC4_done 	= 1'b0;
		tb_ED_done	= 1'b0;
		@(posedge tb_clk);
		@(posedge tb_clk);
       		#(CHECK_DELAY);
		if((tb_RC4_start != 1'b1) && (tb_ED_start != 1'b0) && (tb_process_complete != 1'b0))
			$error("Test case: FAILED");
		else
			$info("Test case: PASSED");
		@(posedge tb_clk);
		@(posedge tb_clk);



		tb_test_num 	= 3;
		tb_start 	= 1'b0;
		tb_RC4_done 	= 1'b1;
		tb_ED_done	= 1'b0;
		@(posedge tb_clk);
		@(posedge tb_clk);
       		#(CHECK_DELAY);
		if((tb_RC4_start != 1'b0) && (tb_ED_start != 1'b1) && (tb_process_complete != 1'b0))
			$error("Test case: FAILED");
		else
			$info("Test case: PASSED");
		@(posedge tb_clk);
		@(posedge tb_clk);



		tb_test_num 	= 4;
		tb_start 	= 1'b0;
		tb_RC4_done 	= 1'b1;
		tb_ED_done	= 1'b1;
		@(posedge tb_clk);
       		@(posedge tb_clk);
		#(CHECK_DELAY);
		if((tb_RC4_start != 1'b0) && (tb_ED_start != 1'b0) && (tb_process_complete != 1'b1))
			$error("Test case: FAILED");
		else
			$info("Test case: PASSED");
		@(posedge tb_clk);
		@(posedge tb_clk);

		
	end
endmodule
module tb_mcu ();




	localparam	CLK_PERIOD  = 35;
	localparam	CHECK_DELAY = 30;


	reg tb_clk, tb_n_rst;
	integer tb_test_num;
	reg tb_start, tb_RC4_done, tb_ED_done, tb_RC4_start, tb_ED_start, tb_process_complete;


	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2.0);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2.0);
	end


	mcu DUT
	(
		.clk(tb_clk),
		.n_rst(tb_n_rst),
		.start(tb_start),
		.RC4_done(tb_RC4_done),
		.ED_done(tb_ED_done),
		.RC4_start(tb_RC4_start),
		.ED_start(tb_ED_start),
		.process_complete(tb_process_complete)
	);


	initial
	begin

		tb_n_rst	= 1'b1;
		tb_start	= 1'b0;
		tb_RC4_done 	= 1'b0;
		tb_ED_done	= 1'b0;


		tb_test_num 	= 0;
		tb_start 	= 1'b0;
		tb_RC4_done 	= 1'b0;
		tb_ED_done	= 1'b0;
		tb_n_rst	= 1'b0;
		@(posedge tb_clk);
		@(posedge tb_clk);
       		#(CHECK_DELAY);
		if((tb_RC4_start != 1'b0) && (tb_ED_start != 1'b0) && (tb_process_complete != 1'b0))
			$error("Test case: FAILED");
		else
			$info("Test case: PASSED");
		@(posedge tb_clk);
		@(posedge tb_clk);
		


		tb_test_num 	= 1;
		tb_n_rst	= 1'b1;
		tb_start 	= 1'b0;
		tb_RC4_done 	= 1'b0;
		tb_ED_done	= 1'b0;
		@(posedge tb_clk);
		@(posedge tb_clk);
       		#(CHECK_DELAY);
		if((tb_RC4_start != 1'b0) && (tb_ED_start != 1'b0) && (tb_process_complete != 1'b0))
			$error("Test case: FAILED");
		else
			$info("Test case: PASSED");
		@(posedge tb_clk);
		@(posedge tb_clk);


		tb_test_num 	= 2;
		tb_start 	= 1'b1;
		tb_RC4_done 	= 1'b0;
		tb_ED_done	= 1'b0;
		@(posedge tb_clk);
		@(posedge tb_clk);
       		#(CHECK_DELAY);
		if((tb_RC4_start != 1'b1) && (tb_ED_start != 1'b0) && (tb_process_complete != 1'b0))
			$error("Test case: FAILED");
		else
			$info("Test case: PASSED");
		@(posedge tb_clk);
		@(posedge tb_clk);



		tb_test_num 	= 3;
		tb_start 	= 1'b0;
		tb_RC4_done 	= 1'b1;
		tb_ED_done	= 1'b0;
		@(posedge tb_clk);
		@(posedge tb_clk);
       		#(CHECK_DELAY);
		if((tb_RC4_start != 1'b0) && (tb_ED_start != 1'b1) && (tb_process_complete != 1'b0))
			$error("Test case: FAILED");
		else
			$info("Test case: PASSED");
		@(posedge tb_clk);
		@(posedge tb_clk);



		tb_test_num 	= 4;
		tb_start 	= 1'b0;
		tb_RC4_done 	= 1'b1;
		tb_ED_done	= 1'b1;
		@(posedge tb_clk);
       		@(posedge tb_clk);
		#(CHECK_DELAY);
		if((tb_RC4_start != 1'b0) && (tb_ED_start != 1'b0) && (tb_process_complete != 1'b1))
			$error("Test case: FAILED");
		else
			$info("Test case: PASSED");
		@(posedge tb_clk);
		@(posedge tb_clk);

		
	end
endmodule