data/full_repos/permissive/130390123/pratica2.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:3: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX0;\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:4: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX1;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:5: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX2;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:6: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX3;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:7: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX4;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:8: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX5;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:9: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX6;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:10: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] HEX7;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:14: Little bit endian vector: MSB < LSB of bit range: 0:6\n wire [0:6] display1;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:15: Little bit endian vector: MSB < LSB of bit range: 0:6\n wire [0:6] display2;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:16: Little bit endian vector: MSB < LSB of bit range: 0:6\n wire [0:6] display3;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:17: Little bit endian vector: MSB < LSB of bit range: 0:6\n wire [0:6] display4;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:18: Little bit endian vector: MSB < LSB of bit range: 0:6\n wire [0:6] display5;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:19: Little bit endian vector: MSB < LSB of bit range: 0:6\n wire [0:6] display6;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:20: Little bit endian vector: MSB < LSB of bit range: 0:6\n wire [0:6] display7;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/130390123/pratica2.v:21: Little bit endian vector: MSB < LSB of bit range: 0:6\n wire [0:6] display8;\n      ^\n%Error: data/full_repos/permissive/130390123/pratica2.v:45: Cannot find file containing module: \'proc\'\n proc process (DIN, 1\'b0, Clock, 1\'b1, Done, BusWires, State);\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/130390123,data/full_repos/permissive/130390123/proc\n             data/full_repos/permissive/130390123,data/full_repos/permissive/130390123/proc.v\n             data/full_repos/permissive/130390123,data/full_repos/permissive/130390123/proc.sv\n             proc\n             proc.v\n             proc.sv\n             obj_dir/proc\n             obj_dir/proc.v\n             obj_dir/proc.sv\n%Error: data/full_repos/permissive/130390123/pratica2.v:46: Cannot find file containing module: \'bcd_7seg\'\n bcd_7seg bcd1 (BusWires[3:0], display1[0:6]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/130390123/pratica2.v:47: Cannot find file containing module: \'bcd_7seg\'\n bcd_7seg bcd2 (BusWires[7:4], display2[0:6]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/130390123/pratica2.v:48: Cannot find file containing module: \'bcd_7seg\'\n bcd_7seg bcd3 (BusWires[11:8], display3[0:6]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/130390123/pratica2.v:49: Cannot find file containing module: \'bcd_7seg\'\n bcd_7seg bcd4 (BusWires[15:12], display4[0:6]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/130390123/pratica2.v:51: Cannot find file containing module: \'bcd_7seg\'\n bcd_7seg bcd5 (DIN[3:0], display5[0:6]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/130390123/pratica2.v:52: Cannot find file containing module: \'bcd_7seg\'\n bcd_7seg bcd6 (DIN[7:4], display6[0:6]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/130390123/pratica2.v:53: Cannot find file containing module: \'bcd_7seg\'\n bcd_7seg bcd7 (DIN[11:8], display7[0:6]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/130390123/pratica2.v:54: Cannot find file containing module: \'bcd_7seg\'\n bcd_7seg bcd8 (DIN[15:12], display8[0:6]);\n ^~~~~~~~\n%Error: Exiting due to 9 error(s), 16 warning(s)\n'
module pratica2 (SW, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, LEDR);
	input [17:0] SW;
	output [0:6] HEX0;
	output [0:6] HEX1;
	output [0:6] HEX2;
	output [0:6] HEX3;
	output [0:6] HEX4;
	output [0:6] HEX5;
	output [0:6] HEX6;
	output [0:6] HEX7;
	output [2:0] LEDR;
	

	wire [0:6] display1;
	wire [0:6] display2;
	wire [0:6] display3;
	wire [0:6] display4;
	wire [0:6] display5;
	wire [0:6] display6;
	wire [0:6] display7;
	wire [0:6] display8;
	

	wire Done;
	wire Clock;
	wire [15:0] BusWires;
	wire [15:0] DIN;
	wire [1:0] State;
	

	assign HEX0 = display1;
	assign HEX1 = display2;
	assign HEX2 = display3;
	assign HEX3 = display4;
	assign HEX4 = display5;
	assign HEX5 = display6;
	assign HEX6 = display7;
	assign HEX7 = display8;
	
	assign LEDR[0:0] = Done;	
	assign Clock = SW[17];
	assign DIN = SW[15:0];
	assign LEDR[2:1] = State[1:0];
	
	proc process (DIN, 1'b0, Clock, 1'b1, Done, BusWires, State);
	bcd_7seg bcd1 (BusWires[3:0], display1[0:6]);
	bcd_7seg bcd2 (BusWires[7:4], display2[0:6]);
	bcd_7seg bcd3 (BusWires[11:8], display3[0:6]);
	bcd_7seg bcd4 (BusWires[15:12], display4[0:6]);
	
	bcd_7seg bcd5 (DIN[3:0], display5[0:6]);
	bcd_7seg bcd6 (DIN[7:4], display6[0:6]);
	bcd_7seg bcd7 (DIN[11:8], display7[0:6]);
	bcd_7seg bcd8 (DIN[15:12], display8[0:6]);

endmodule
module pratica2 (SW, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, LEDR);

	input [17:0] SW;
	output [0:6] HEX0;
	output [0:6] HEX1;
	output [0:6] HEX2;
	output [0:6] HEX3;
	output [0:6] HEX4;
	output [0:6] HEX5;
	output [0:6] HEX6;
	output [0:6] HEX7;
	output [2:0] LEDR;
	

	wire [0:6] display1;
	wire [0:6] display2;
	wire [0:6] display3;
	wire [0:6] display4;
	wire [0:6] display5;
	wire [0:6] display6;
	wire [0:6] display7;
	wire [0:6] display8;
	

	wire Done;
	wire Clock;
	wire [15:0] BusWires;
	wire [15:0] DIN;
	wire [1:0] State;
	

	assign HEX0 = display1;
	assign HEX1 = display2;
	assign HEX2 = display3;
	assign HEX3 = display4;
	assign HEX4 = display5;
	assign HEX5 = display6;
	assign HEX6 = display7;
	assign HEX7 = display8;
	
	assign LEDR[0:0] = Done;	
	assign Clock = SW[17];
	assign DIN = SW[15:0];
	assign LEDR[2:1] = State[1:0];
	
	proc process (DIN, 1'b0, Clock, 1'b1, Done, BusWires, State);
	bcd_7seg bcd1 (BusWires[3:0], display1[0:6]);
	bcd_7seg bcd2 (BusWires[7:4], display2[0:6]);
	bcd_7seg bcd3 (BusWires[11:8], display3[0:6]);
	bcd_7seg bcd4 (BusWires[15:12], display4[0:6]);
	
	bcd_7seg bcd5 (DIN[3:0], display5[0:6]);
	bcd_7seg bcd6 (DIN[7:4], display6[0:6]);
	bcd_7seg bcd7 (DIN[11:8], display7[0:6]);
	bcd_7seg bcd8 (DIN[15:12], display8[0:6]);

endmodule