data/full_repos/permissive/218126213/memory.v
 line:80: before: ";"
1: b'%Error: data/full_repos/permissive/218126213/memory.v:1: Cannot find include file: global_memory_parameters.v\n`include "global_memory_parameters.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/218126213,data/full_repos/permissive/218126213/global_memory_parameters.v\n             data/full_repos/permissive/218126213,data/full_repos/permissive/218126213/global_memory_parameters.v.v\n             data/full_repos/permissive/218126213,data/full_repos/permissive/218126213/global_memory_parameters.v.sv\n             global_memory_parameters.v\n             global_memory_parameters.v.v\n             global_memory_parameters.v.sv\n             obj_dir/global_memory_parameters.v\n             obj_dir/global_memory_parameters.v.v\n             obj_dir/global_memory_parameters.v.sv\n%Error: data/full_repos/permissive/218126213/memory.v:30: Define or directive not defined: \'`man_id\'\nreg [23:0] mem_id={`man_id, `mem_typ, `mem_cap};  \n                   ^~~~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:30: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nreg [23:0] mem_id={`man_id, `mem_typ, `mem_cap};  \n                          ^\n%Error: data/full_repos/permissive/218126213/memory.v:30: Define or directive not defined: \'`mem_typ\'\nreg [23:0] mem_id={`man_id, `mem_typ, `mem_cap};  \n                            ^~~~~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:30: Define or directive not defined: \'`mem_cap\'\nreg [23:0] mem_id={`man_id, `mem_typ, `mem_cap};  \n                                      ^~~~~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:71: Define or directive not defined: \'`size\'\nreg [7:0] mem_content[(`size-1):0];  \n                       ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:74: Define or directive not defined: \'`size\'\n for(i=0;i<=`size-1;i=i+1)  \n            ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:80: Define or directive not defined: \'`page_size\'\nreg [7:0] page_content[(`page_size-1):0];  \n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:83: Define or directive not defined: \'`page_size\'\n for(i=0;i<=`page_size-1;i=i+1)  \n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:136: Define or directive not defined: \'`RDID\'\n     `RDID: \n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:136: syntax error, unexpected \':\', expecting endcase\n     `RDID: \n          ^\n%Error: data/full_repos/permissive/218126213/memory.v:141: Define or directive not defined: \'`READ\'\n     `READ:\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:142: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin \n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:146: Define or directive not defined: \'`FAST_READ\'\n     `FAST_READ:\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:147: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin \n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:151: Define or directive not defined: \'`WREN\'\n     `WREN:\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:152: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:156: Define or directive not defined: \'`WRDI\'\n     `WRDI:\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:157: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:161: Define or directive not defined: \'`DP\'\n     `DP:\n     ^~~\n%Error: data/full_repos/permissive/218126213/memory.v:162: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:166: Define or directive not defined: \'`RDP\'\n     `RDP:\n     ^~~~\n%Error: data/full_repos/permissive/218126213/memory.v:167: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:171: Define or directive not defined: \'`SE\'\n     `SE:\n     ^~~\n%Error: data/full_repos/permissive/218126213/memory.v:172: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:176: Define or directive not defined: \'`PE\'\n     `PE:\n     ^~~\n%Error: data/full_repos/permissive/218126213/memory.v:177: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:181: Define or directive not defined: \'`PW\'\n     `PW:\n     ^~~\n%Error: data/full_repos/permissive/218126213/memory.v:182: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:186: Define or directive not defined: \'`PP\'\n     `PP:\n     ^~~\n%Error: data/full_repos/permissive/218126213/memory.v:187: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:191: Define or directive not defined: \'`RDSR\'\n     `RDSR:\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:192: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n     begin\n     ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:196: syntax error, unexpected default\n     default :\n     ^~~~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:201: syntax error, unexpected endcase\n    endcase\n    ^~~~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:204: Define or directive not defined: \'`RDSR\'\n   else if(data_buff==`RDSR)\n                      ^~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:226: syntax error, unexpected \'[\', expecting IDENTIFIER\n   mem_add[23:16]<=data_buff;\n          ^\n%Error: data/full_repos/permissive/218126213/memory.v:231: syntax error, unexpected \'[\', expecting IDENTIFIER\n   mem_add[15:8]<=data_buff;\n          ^\n%Error: data/full_repos/permissive/218126213/memory.v:236: syntax error, unexpected \'[\', expecting IDENTIFIER\n   mem_add[7:0]<=data_buff;\n          ^\n%Error: data/full_repos/permissive/218126213/memory.v:242: syntax error, unexpected \'[\', expecting IDENTIFIER\n   page_content[cnt_byte-5]<=data_buff;\n               ^\n%Error: data/full_repos/permissive/218126213/memory.v:250: syntax error, unexpected <=, expecting IDENTIFIER\n   mem_add_page<=mem_add&`page_board;\n               ^~\n%Error: data/full_repos/permissive/218126213/memory.v:250: Define or directive not defined: \'`page_board\'\n   mem_add_page<=mem_add&`page_board;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:256: syntax error, unexpected <=, expecting IDENTIFIER\n   mem_add_sec<=mem_add&`sector_bord;\n              ^~\n%Error: data/full_repos/permissive/218126213/memory.v:256: Define or directive not defined: \'`sector_bord\'\n   mem_add_sec<=mem_add&`sector_bord;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/218126213/memory.v:266: syntax error, unexpected <=, expecting IDENTIFIER\n   q_buff<=mem_id[23:16];\n         ^~\n%Error: data/full_repos/permissive/218126213/memory.v:270: syntax error, unexpected <=, expecting IDENTIFIER\n   q_buff<=mem_id[15:8];\n         ^~\n%Error: data/full_repos/permissive/218126213/memory.v:274: syntax error, unexpected <=, expecting IDENTIFIER\n   q_buff<=mem_id[7:0];\n         ^~\n%Error: data/full_repos/permissive/218126213/memory.v:279: syntax error, unexpected <=, expecting IDENTIFIER\n   q_buff<=8\'h00;\n         ^~\n%Error: data/full_repos/permissive/218126213/memory.v:283: syntax error, unexpected <=, expecting IDENTIFIER\n   rdid_cnt<=rdid_cnt+1;\n           ^~\n%Error: data/full_repos/permissive/218126213/memory.v:326: syntax error, unexpected <=, expecting IDENTIFIER\n    mem_add<=24\'h000000;\n           ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module memory(
output reg [7:0] Q,
input [7:0] D,
input SCK,
input S,
input RESET,
input W_ENABLE	,
input DATA_DONE
);

reg sck_val=1'b0;
reg s_flag=1'b0;
reg rst_flag=1'b0;
reg hpm_flag=1'b0;
reg busy_flag=1'b0;

reg [7:0] data_buff=8'h00;
reg [7:0] data_done=8'h00;
reg [7:0] q_buff=8'h00;

reg cnt_flag=1'b0;
reg [11:0] cnt_byte=12'h000;

time dp_time;
time rdp_time;

reg rdid_flag=1'b0;
reg [23:0] mem_id={`man_id, `mem_typ, `mem_cap};
reg [2:0]rdid_cnt=3'b000;

reg read_flag=1'b0;
reg fast_read_flag=1'b0;
reg page_erase_flag=1'b0;
reg section_erase_flag=1'b0;
reg page_write_flag=1'b0;
reg page_prog_flag=1'b0;
reg wren_flag=1'b0;
reg wrdi_flag=1'b0;
reg rdsr_flag=1'b0;
reg dp_flag=1'b0;
reg rdp_flag=1'b0;

reg [7:0] rdsr_reg=8'h00;

reg [23:0] mem_add=24'h000000;
reg [23:0] mem_add_sec=24'h000000;
reg [23:0] mem_add_page=24'h000000;
reg add_done_flag=1'b0;

reg [3:0] read_cnt=4'h0;
reg read_busy=1'b0;

reg section_erase_busy=1'b0;
reg page_erase_busy=1'b0;

reg page_prog_busy=1'b0;
integer page_cnt=0;

reg page_write_busy=1'b0;
reg pw_erase_busy=1'b0;

reg [7:0] read_data=8'h00;

reg dp_mode=1'b0;

integer i=0;
integer j=0;

reg [7:0] mem_content[(`size-1):0];
initial 
begin
	for(i=0;i<=`size-1;i=i+1)
	begin
		mem_content[i]<=8'hFF;
	end
end

reg [7:0] page_content[(`page_size-1):0];
initial 
begin
	for(i=0;i<=`page_size-1;i=i+1)
	begin
		page_content[i]<=8'hFF;
	end
end



always @ (SCK)
begin
	sck_val<=SCK;
end


always @ (W_ENABLE)
begin
	if(!W_ENABLE)
	begin
		hpm_flag<=1'b1;
	end
	else
	begin
		hpm_flag<=1'b0;
	end
end


always @ (negedge DATA_DONE)
begin
	if(s_flag && !rst_flag)
	begin
	data_buff<=D;
	cnt_byte<=cnt_byte+1;
	end
	
	if(!s_flag)
	begin
		data_buff<=8'h00;
		cnt_byte<=0;
	end
end

always @ (data_buff or cnt_byte or s_flag)
begin


	if(s_flag)
	begin
		if(cnt_byte==12'h001 && !busy_flag)
		begin
			if(!rdsr_reg[0])
			begin
				case(data_buff)
					`RDID: 
					begin 
						rdid_flag<=1'b1;
						$display("%t-RDID instruction",$realtime);
					end
					`READ:
					begin 
						read_flag<=1'b1;
						$display("%t-READ instruction",$realtime);
					end
					`FAST_READ:
					begin 
						fast_read_flag<=1'b1;
						$display("%t-FAST READ instruction",$realtime);
					end
					`WREN:
					begin
						wren_flag<=1'b1;
						$display("%t-WREN instruction",$realtime);
					end
					`WRDI:
					begin
						wrdi_flag<=1'b1;
						$display("%t-WRDI instruction",$realtime);
					end
					`DP:
					begin
						dp_flag<=1'b1;
						$display("%t-DP instruction",$realtime);
					end
					`RDP:
					begin
						rdp_flag<=1'b1;
						$display("%t-RDP instruction",$realtime);
					end
					`SE:
					begin
						section_erase_flag<=1'b1;
						$display("%t-SE instruction",$realtime);
					end
					`PE:
					begin
						page_erase_flag<=1'b1;
						$display("%t-PE instruction",$realtime);
					end
					`PW:
					begin
						page_write_flag<=1'b1;
						$display("%t-PW instruction",$realtime);
					end
					`PP:
					begin
						page_prog_flag<=1'b1;
						$display("%t-PP instruction",$realtime);
					end
					`RDSR:
					begin
						rdsr_flag<=1'b1;
						$display("%t-RDSR instruction",$realtime);
					end
					default :
					begin
						$display("%t-No such command 1",$realtime);
						q_buff<=1'bX;
					end
				endcase
			end
			
			else if(data_buff==`RDSR)
			begin
				rdsr_flag<=1'b1;

			end
			else if(busy_flag)
			begin
				$display("%t-Other process is running",$realtime);
			end
			else if(rdsr_reg[0])
			begin
				$display("%t-Other process is running, only RDSR instruction will be accepted",$realtime);
			end
			else
			begin
				$display("%t-No such command 2",$realtime);
				q_buff<=1'bX;
			end
		end

		if(cnt_byte==12'h002 && (fast_read_flag || read_flag || section_erase_flag || page_erase_flag || page_write_flag || page_prog_flag))
		begin
			mem_add[23:16]<=data_buff;
		end

		if(cnt_byte==12'h003 && (fast_read_flag || read_flag || section_erase_flag || page_erase_flag || page_write_flag || page_prog_flag))
		begin
			mem_add[15:8]<=data_buff;
		end

		if(cnt_byte==12'h004 && (fast_read_flag || read_flag || section_erase_flag || page_erase_flag || page_write_flag || page_prog_flag))
		begin
			mem_add[7:0]<=data_buff;
			add_done_flag<=1'b1;
		end

		if(cnt_byte>12'h004 && (page_write_flag || page_prog_flag))
		begin
			page_content[cnt_byte-5]<=data_buff;
			page_cnt=page_cnt+1;
		end
		
		

		if(add_done_flag && (page_erase_flag || page_write_flag || page_prog_flag))
		begin
			mem_add_page<=mem_add&`page_board;
		end


		if(add_done_flag && section_erase_flag)
		begin
			mem_add_sec<=mem_add&`sector_bord;
		end
	end
	

	if(rdid_flag && s_flag && !rst_flag && !dp_mode)
	begin
		busy_flag<=1'b1;
		if(rdid_cnt==3'b000)
		begin
			q_buff<=mem_id[23:16];
		end
		else if(rdid_cnt==3'b001)
		begin
			q_buff<=mem_id[15:8];
		end
		else if(rdid_cnt==3'b010)
		begin
			q_buff<=mem_id[7:0];
		end
		
		if(rdid_cnt>3'b010)
		begin
			q_buff<=8'h00;
		end
		else
		begin
			rdid_cnt<=rdid_cnt+1;
		end
	end
	else if(rdid_flag && (!s_flag || rst_flag))
	begin
		q_buff<=8'hZZ;
	end

	if(rdsr_flag && s_flag && !rst_flag && !dp_mode)
	begin
		busy_flag<=1'b1;
		q_buff<=rdsr_reg;
	end

	if(wren_flag && !s_flag && !rst_flag && !dp_mode)
	begin
		$display("%t-WEL register to TRUE",$realtime);
		rdsr_reg[1]<=1'b1;
		wren_flag<=1'b0;
	end

	if(wrdi_flag && !s_flag && !rst_flag && !dp_mode)
	begin
		$display("%t-WEL register to FALSE",$realtime);
		rdsr_reg[1]<=1'b0;
		wrdi_flag<=1'b0;
	end
	

	if(read_flag)
	begin
		if(!add_done_flag && !s_flag)
		begin

			read_flag<=1'b0;
		end
		else if(read_flag && add_done_flag && !rst_flag && !dp_mode && s_flag && !read_busy)
		begin
			busy_flag<=1'b1;
			read_busy<=1'b1;
			read_data<=mem_content[1];
			if(mem_add==24'h0FFFFF)
			begin
				mem_add<=24'h000000;
			end
			else
			begin
				mem_add<=mem_add+1;
			end

		end
	end

	if(read_flag && s_flag && !rst_flag && add_done_flag && read_busy && !dp_mode)
	begin
		q_buff<=#`t_clqv read_data[7-read_cnt];
		if(read_cnt>=4'h7)
		begin
			read_cnt<=4'h0;
			read_busy<=1'b0;
		end
		else
		begin
			read_cnt<=read_cnt+1;
		end
	end


	if(dp_flag && !dp_mode && !rst_flag && !s_flag)
	begin
		dp_time=10;
	end

	if(rdp_flag && dp_mode && !rst_flag && !s_flag)
	begin
		rdp_time=10;
	end


	if(section_erase_flag)
	begin
		if(!s_flag)
		begin
			if(!add_done_flag)
			begin

				section_erase_flag<=1'b0;
			end
			else if(add_done_flag && hpm_flag && mem_add_sec<=`protect_board)
			begin

				add_done_flag<=1'b0;
				section_erase_flag<=1'b0;
			end
			else if (add_done_flag && !rdsr_reg[1])
			begin

				add_done_flag<=1'b0;
				section_erase_flag<=1'b0;
			end
		end
	end

	if(section_erase_flag && add_done_flag && !rst_flag && !dp_mode && !s_flag)
	begin
		section_erase_busy<=1'b1;
		$display("%t-Sector Erase - Start",$realtime);
		rdsr_reg[0]<=1'b1;


		#5000;
		section_erase_flag<=1'b0;
	end


	if(!section_erase_busy)
	begin
		for(i=mem_add_sec;i<=mem_add_sec+`sector_size-1;i=i+1)
		begin
			mem_content[i]<=8'hFF;
		end
		add_done_flag<=1'b0;
		section_erase_flag<=1'b0;
		rdsr_reg[0]<=1'b0;
		$display("%t-Sector Erase - Stop",$realtime);
end


	if(page_erase_flag)
	begin
		if(!s_flag)
		begin
			if(!add_done_flag)
			begin
				$display("$t-Instruction was too early deselect",$realtime);
				page_erase_flag<=1'b0;
			end
			else if(add_done_flag && hpm_flag && mem_add_page<=`protect_board)
			begin
				$display("%t-This sector is under Hardware Protection Mode",$realtime);
				add_done_flag<=1'b0;
				section_erase_flag<=1'b0;
			end
			else if (add_done_flag && !rdsr_reg[1])
			begin
				$display("%t-WEL bit is turn off",$realtime);
				add_done_flag<=1'b0;
				page_erase_flag<=1'b0;
			end
		end
	end

	if(page_erase_flag && add_done_flag && !rst_flag && !dp_mode && !s_flag)
	begin
		page_erase_busy<=1'b1;
		$display("%t-Page Erase - Start",$realtime);
		rdsr_reg[0]<=1'b1;


		#5000;
		page_erase_busy<=1'b0;
	end


if(!page_erase_busy)
begin
	for(i=mem_add_page;i<=mem_add_page+`page_size-1;i=i+1)
   begin
		mem_content[i]<=8'hFF;
	end
	add_done_flag<=1'b0;
	page_erase_flag<=1'b0;
	rdsr_reg[0]<=1'b0;
	$display("%t-Page Erase - Stop",$realtime);
end


	if(page_write_flag)
	begin
		if(!s_flag)
		begin
			if(!add_done_flag)
			begin
				$display("$t-Instruction was too early deselect",$realtime);
				page_write_flag<=1'b0;
			end
			else if(add_done_flag && hpm_flag && mem_add_page<=`protect_board)
			begin
				$display("%t-This sector is under Hardware Protection Mode",$realtime);
				add_done_flag<=1'b0;
				page_write_flag<=1'b0;
			end
			else if(add_done_flag && !rdsr_reg[1])
			begin
				$display("%t-WEL bit is turn off",$realtime);
				add_done_flag<=1'b0;
				page_write_flag<=1'b0;
			end
		end
	end

	if(page_write_flag && add_done_flag && !rst_flag && !dp_mode && !s_flag)
	begin
		rdsr_reg[0]<=1'b1;
		pw_erase_busy<=1'b1;
		$display("%t-Page Write- Erase Start",$realtime);


		#50;
		pw_erase_busy<=1'b0;
	end

if(!pw_erase_busy)
begin
	for(i=mem_add_page;i<=mem_add_page+`page_size-1;i=i+1)
   begin
		mem_content[i]<=8'hFF;
	end

	page_write_flag<=1'b1;
end



if (!pw_erase_busy)
begin
	begin
		for(j=0;j<=`page_size-1;j=j+1)
		begin
			mem_content[mem_add_page+j]<=mem_content[mem_add_page+j]&page_content[j];
		end
		add_done_flag<=1'b0;
		page_prog_flag<=1'b0;
		rdsr_reg[0]<=1'b0;
		page_cnt<=1'b0;
		for(i=0;i<=`page_size;i=i+1)
		begin
			page_content[i]<=8'hFF;
		end
		$display("%t-Page Programming - Stop",$realtime);
	end
end

	if(page_prog_flag)
	begin
		if(!s_flag)
		begin
			if(!add_done_flag)
			begin

				page_prog_flag<=1'b0;
			end
			else if(add_done_flag && hpm_flag && mem_add_page<=`protect_board)
			begin

				add_done_flag<=1'b0;
				page_prog_flag<=1'b0;
			end
			else if(add_done_flag && !rdsr_reg[1])
			begin

				add_done_flag<=1'b0;
				page_prog_flag<=1'b0;
			end
		end
	end

	if(page_prog_flag && add_done_flag && !rst_flag && !dp_mode && !s_flag)
	begin
		rdsr_reg[0]<=1'b1;
		page_prog_busy<=1'b1;



		#5000
		page_prog_busy<=1'b0;
	end


if(!page_prog_busy)
begin

	begin
		for(j=0;j<=`page_size-1;j=j+1)
		begin
			mem_content[mem_add_page+j]<=mem_content[mem_add_page+j]&page_content[j];
		end
		add_done_flag<=1'b0;
		page_prog_flag<=1'b0;
		rdsr_reg[0]<=1'b0;
		page_cnt<=1'b0;
		for(i=0;i<=`page_size;i=i+1)
		begin
			page_content[i]<=8'hFF;
		end

	end
end
	
	else if (!s_flag || rst_flag)
	begin
		rdid_cnt<=3'b000;
		q_buff<=8'hZZ;
		rdid_flag<=8'h00;
		rdsr_flag<=8'h00;
		busy_flag<=1'b0;
	end
end




always @ (S)
begin
	if(!S)
	begin
		s_flag<=1'b1;


	end
	else
	begin
		s_flag<=1'b0;
		if(dp_flag)
		begin
			if(10-dp_time<=`t_dp)
			begin

			end
			else
			begin

				dp_mode<=1'b1;
			end
		end
		
		if(rdp_flag)
		begin
			if(10-rdp_time<=`t_rdp)
			begin

			end
			else
			begin

				dp_mode<=1'b0;
			end
		end
	end
end


always @ (RESET)
begin
	if(RESET)
	begin
		rst_flag<=1'b0;
	end
	else
	begin
		rst_flag<=1'b1;

	end
end


always @ (q_buff)
begin
	Q<=q_buff;
end

endmodule
module memory(
output reg [7:0] Q,
input [7:0] D,
input SCK,
input S,
input RESET,
input W_ENABLE	,
input DATA_DONE
);


reg sck_val=1'b0;
reg s_flag=1'b0;
reg rst_flag=1'b0;
reg hpm_flag=1'b0;
reg busy_flag=1'b0;

reg [7:0] data_buff=8'h00;
reg [7:0] data_done=8'h00;
reg [7:0] q_buff=8'h00;

reg cnt_flag=1'b0;
reg [11:0] cnt_byte=12'h000;

time dp_time;
time rdp_time;

reg rdid_flag=1'b0;
reg [23:0] mem_id={`man_id, `mem_typ, `mem_cap};
reg [2:0]rdid_cnt=3'b000;

reg read_flag=1'b0;
reg fast_read_flag=1'b0;
reg page_erase_flag=1'b0;
reg section_erase_flag=1'b0;
reg page_write_flag=1'b0;
reg page_prog_flag=1'b0;
reg wren_flag=1'b0;
reg wrdi_flag=1'b0;
reg rdsr_flag=1'b0;
reg dp_flag=1'b0;
reg rdp_flag=1'b0;

reg [7:0] rdsr_reg=8'h00;

reg [23:0] mem_add=24'h000000;
reg [23:0] mem_add_sec=24'h000000;
reg [23:0] mem_add_page=24'h000000;
reg add_done_flag=1'b0;

reg [3:0] read_cnt=4'h0;
reg read_busy=1'b0;

reg section_erase_busy=1'b0;
reg page_erase_busy=1'b0;

reg page_prog_busy=1'b0;
integer page_cnt=0;

reg page_write_busy=1'b0;
reg pw_erase_busy=1'b0;

reg [7:0] read_data=8'h00;

reg dp_mode=1'b0;

integer i=0;
integer j=0;

reg [7:0] mem_content[(`size-1):0];
initial 
begin
	for(i=0;i<=`size-1;i=i+1)
	begin
		mem_content[i]<=8'hFF;
	end
end

reg [7:0] page_content[(`page_size-1):0];
initial 
begin
	for(i=0;i<=`page_size-1;i=i+1)
	begin
		page_content[i]<=8'hFF;
	end
end



always @ (SCK)
begin
	sck_val<=SCK;
end


always @ (W_ENABLE)
begin
	if(!W_ENABLE)
	begin
		hpm_flag<=1'b1;
	end
	else
	begin
		hpm_flag<=1'b0;
	end
end


always @ (negedge DATA_DONE)
begin
	if(s_flag && !rst_flag)
	begin
	data_buff<=D;
	cnt_byte<=cnt_byte+1;
	end
	
	if(!s_flag)
	begin
		data_buff<=8'h00;
		cnt_byte<=0;
	end
end

always @ (data_buff or cnt_byte or s_flag)
begin


	if(s_flag)
	begin
		if(cnt_byte==12'h001 && !busy_flag)
		begin
			if(!rdsr_reg[0])
			begin
				case(data_buff)
					`RDID: 
					begin 
						rdid_flag<=1'b1;
						$display("%t-RDID instruction",$realtime);
					end
					`READ:
					begin 
						read_flag<=1'b1;
						$display("%t-READ instruction",$realtime);
					end
					`FAST_READ:
					begin 
						fast_read_flag<=1'b1;
						$display("%t-FAST READ instruction",$realtime);
					end
					`WREN:
					begin
						wren_flag<=1'b1;
						$display("%t-WREN instruction",$realtime);
					end
					`WRDI:
					begin
						wrdi_flag<=1'b1;
						$display("%t-WRDI instruction",$realtime);
					end
					`DP:
					begin
						dp_flag<=1'b1;
						$display("%t-DP instruction",$realtime);
					end
					`RDP:
					begin
						rdp_flag<=1'b1;
						$display("%t-RDP instruction",$realtime);
					end
					`SE:
					begin
						section_erase_flag<=1'b1;
						$display("%t-SE instruction",$realtime);
					end
					`PE:
					begin
						page_erase_flag<=1'b1;
						$display("%t-PE instruction",$realtime);
					end
					`PW:
					begin
						page_write_flag<=1'b1;
						$display("%t-PW instruction",$realtime);
					end
					`PP:
					begin
						page_prog_flag<=1'b1;
						$display("%t-PP instruction",$realtime);
					end
					`RDSR:
					begin
						rdsr_flag<=1'b1;
						$display("%t-RDSR instruction",$realtime);
					end
					default :
					begin
						$display("%t-No such command 1",$realtime);
						q_buff<=1'bX;
					end
				endcase
			end
			
			else if(data_buff==`RDSR)
			begin
				rdsr_flag<=1'b1;

			end
			else if(busy_flag)
			begin
				$display("%t-Other process is running",$realtime);
			end
			else if(rdsr_reg[0])
			begin
				$display("%t-Other process is running, only RDSR instruction will be accepted",$realtime);
			end
			else
			begin
				$display("%t-No such command 2",$realtime);
				q_buff<=1'bX;
			end
		end

		if(cnt_byte==12'h002 && (fast_read_flag || read_flag || section_erase_flag || page_erase_flag || page_write_flag || page_prog_flag))
		begin
			mem_add[23:16]<=data_buff;
		end

		if(cnt_byte==12'h003 && (fast_read_flag || read_flag || section_erase_flag || page_erase_flag || page_write_flag || page_prog_flag))
		begin
			mem_add[15:8]<=data_buff;
		end

		if(cnt_byte==12'h004 && (fast_read_flag || read_flag || section_erase_flag || page_erase_flag || page_write_flag || page_prog_flag))
		begin
			mem_add[7:0]<=data_buff;
			add_done_flag<=1'b1;
		end

		if(cnt_byte>12'h004 && (page_write_flag || page_prog_flag))
		begin
			page_content[cnt_byte-5]<=data_buff;
			page_cnt=page_cnt+1;
		end
		
		

		if(add_done_flag && (page_erase_flag || page_write_flag || page_prog_flag))
		begin
			mem_add_page<=mem_add&`page_board;
		end


		if(add_done_flag && section_erase_flag)
		begin
			mem_add_sec<=mem_add&`sector_bord;
		end
	end
	

	if(rdid_flag && s_flag && !rst_flag && !dp_mode)
	begin
		busy_flag<=1'b1;
		if(rdid_cnt==3'b000)
		begin
			q_buff<=mem_id[23:16];
		end
		else if(rdid_cnt==3'b001)
		begin
			q_buff<=mem_id[15:8];
		end
		else if(rdid_cnt==3'b010)
		begin
			q_buff<=mem_id[7:0];
		end
		
		if(rdid_cnt>3'b010)
		begin
			q_buff<=8'h00;
		end
		else
		begin
			rdid_cnt<=rdid_cnt+1;
		end
	end
	else if(rdid_flag && (!s_flag || rst_flag))
	begin
		q_buff<=8'hZZ;
	end

	if(rdsr_flag && s_flag && !rst_flag && !dp_mode)
	begin
		busy_flag<=1'b1;
		q_buff<=rdsr_reg;
	end

	if(wren_flag && !s_flag && !rst_flag && !dp_mode)
	begin
		$display("%t-WEL register to TRUE",$realtime);
		rdsr_reg[1]<=1'b1;
		wren_flag<=1'b0;
	end

	if(wrdi_flag && !s_flag && !rst_flag && !dp_mode)
	begin
		$display("%t-WEL register to FALSE",$realtime);
		rdsr_reg[1]<=1'b0;
		wrdi_flag<=1'b0;
	end
	

	if(read_flag)
	begin
		if(!add_done_flag && !s_flag)
		begin

			read_flag<=1'b0;
		end
		else if(read_flag && add_done_flag && !rst_flag && !dp_mode && s_flag && !read_busy)
		begin
			busy_flag<=1'b1;
			read_busy<=1'b1;
			read_data<=mem_content[1];
			if(mem_add==24'h0FFFFF)
			begin
				mem_add<=24'h000000;
			end
			else
			begin
				mem_add<=mem_add+1;
			end

		end
	end

	if(read_flag && s_flag && !rst_flag && add_done_flag && read_busy && !dp_mode)
	begin
		q_buff<=#`t_clqv read_data[7-read_cnt];
		if(read_cnt>=4'h7)
		begin
			read_cnt<=4'h0;
			read_busy<=1'b0;
		end
		else
		begin
			read_cnt<=read_cnt+1;
		end
	end


	if(dp_flag && !dp_mode && !rst_flag && !s_flag)
	begin
		dp_time=10;
	end

	if(rdp_flag && dp_mode && !rst_flag && !s_flag)
	begin
		rdp_time=10;
	end


	if(section_erase_flag)
	begin
		if(!s_flag)
		begin
			if(!add_done_flag)
			begin

				section_erase_flag<=1'b0;
			end
			else if(add_done_flag && hpm_flag && mem_add_sec<=`protect_board)
			begin

				add_done_flag<=1'b0;
				section_erase_flag<=1'b0;
			end
			else if (add_done_flag && !rdsr_reg[1])
			begin

				add_done_flag<=1'b0;
				section_erase_flag<=1'b0;
			end
		end
	end

	if(section_erase_flag && add_done_flag && !rst_flag && !dp_mode && !s_flag)
	begin
		section_erase_busy<=1'b1;
		$display("%t-Sector Erase - Start",$realtime);
		rdsr_reg[0]<=1'b1;


		#5000;
		section_erase_flag<=1'b0;
	end


	if(!section_erase_busy)
	begin
		for(i=mem_add_sec;i<=mem_add_sec+`sector_size-1;i=i+1)
		begin
			mem_content[i]<=8'hFF;
		end
		add_done_flag<=1'b0;
		section_erase_flag<=1'b0;
		rdsr_reg[0]<=1'b0;
		$display("%t-Sector Erase - Stop",$realtime);
end


	if(page_erase_flag)
	begin
		if(!s_flag)
		begin
			if(!add_done_flag)
			begin
				$display("$t-Instruction was too early deselect",$realtime);
				page_erase_flag<=1'b0;
			end
			else if(add_done_flag && hpm_flag && mem_add_page<=`protect_board)
			begin
				$display("%t-This sector is under Hardware Protection Mode",$realtime);
				add_done_flag<=1'b0;
				section_erase_flag<=1'b0;
			end
			else if (add_done_flag && !rdsr_reg[1])
			begin
				$display("%t-WEL bit is turn off",$realtime);
				add_done_flag<=1'b0;
				page_erase_flag<=1'b0;
			end
		end
	end

	if(page_erase_flag && add_done_flag && !rst_flag && !dp_mode && !s_flag)
	begin
		page_erase_busy<=1'b1;
		$display("%t-Page Erase - Start",$realtime);
		rdsr_reg[0]<=1'b1;


		#5000;
		page_erase_busy<=1'b0;
	end


if(!page_erase_busy)
begin
	for(i=mem_add_page;i<=mem_add_page+`page_size-1;i=i+1)
   begin
		mem_content[i]<=8'hFF;
	end
	add_done_flag<=1'b0;
	page_erase_flag<=1'b0;
	rdsr_reg[0]<=1'b0;
	$display("%t-Page Erase - Stop",$realtime);
end


	if(page_write_flag)
	begin
		if(!s_flag)
		begin
			if(!add_done_flag)
			begin
				$display("$t-Instruction was too early deselect",$realtime);
				page_write_flag<=1'b0;
			end
			else if(add_done_flag && hpm_flag && mem_add_page<=`protect_board)
			begin
				$display("%t-This sector is under Hardware Protection Mode",$realtime);
				add_done_flag<=1'b0;
				page_write_flag<=1'b0;
			end
			else if(add_done_flag && !rdsr_reg[1])
			begin
				$display("%t-WEL bit is turn off",$realtime);
				add_done_flag<=1'b0;
				page_write_flag<=1'b0;
			end
		end
	end

	if(page_write_flag && add_done_flag && !rst_flag && !dp_mode && !s_flag)
	begin
		rdsr_reg[0]<=1'b1;
		pw_erase_busy<=1'b1;
		$display("%t-Page Write- Erase Start",$realtime);


		#50;
		pw_erase_busy<=1'b0;
	end

if(!pw_erase_busy)
begin
	for(i=mem_add_page;i<=mem_add_page+`page_size-1;i=i+1)
   begin
		mem_content[i]<=8'hFF;
	end

	page_write_flag<=1'b1;
end



if (!pw_erase_busy)
begin
	begin
		for(j=0;j<=`page_size-1;j=j+1)
		begin
			mem_content[mem_add_page+j]<=mem_content[mem_add_page+j]&page_content[j];
		end
		add_done_flag<=1'b0;
		page_prog_flag<=1'b0;
		rdsr_reg[0]<=1'b0;
		page_cnt<=1'b0;
		for(i=0;i<=`page_size;i=i+1)
		begin
			page_content[i]<=8'hFF;
		end
		$display("%t-Page Programming - Stop",$realtime);
	end
end

	if(page_prog_flag)
	begin
		if(!s_flag)
		begin
			if(!add_done_flag)
			begin

				page_prog_flag<=1'b0;
			end
			else if(add_done_flag && hpm_flag && mem_add_page<=`protect_board)
			begin

				add_done_flag<=1'b0;
				page_prog_flag<=1'b0;
			end
			else if(add_done_flag && !rdsr_reg[1])
			begin

				add_done_flag<=1'b0;
				page_prog_flag<=1'b0;
			end
		end
	end

	if(page_prog_flag && add_done_flag && !rst_flag && !dp_mode && !s_flag)
	begin
		rdsr_reg[0]<=1'b1;
		page_prog_busy<=1'b1;



		#5000
		page_prog_busy<=1'b0;
	end


if(!page_prog_busy)
begin

	begin
		for(j=0;j<=`page_size-1;j=j+1)
		begin
			mem_content[mem_add_page+j]<=mem_content[mem_add_page+j]&page_content[j];
		end
		add_done_flag<=1'b0;
		page_prog_flag<=1'b0;
		rdsr_reg[0]<=1'b0;
		page_cnt<=1'b0;
		for(i=0;i<=`page_size;i=i+1)
		begin
			page_content[i]<=8'hFF;
		end

	end
end
	
	else if (!s_flag || rst_flag)
	begin
		rdid_cnt<=3'b000;
		q_buff<=8'hZZ;
		rdid_flag<=8'h00;
		rdsr_flag<=8'h00;
		busy_flag<=1'b0;
	end
end




always @ (S)
begin
	if(!S)
	begin
		s_flag<=1'b1;


	end
	else
	begin
		s_flag<=1'b0;
		if(dp_flag)
		begin
			if(10-dp_time<=`t_dp)
			begin

			end
			else
			begin

				dp_mode<=1'b1;
			end
		end
		
		if(rdp_flag)
		begin
			if(10-rdp_time<=`t_rdp)
			begin

			end
			else
			begin

				dp_mode<=1'b0;
			end
		end
	end
end


always @ (RESET)
begin
	if(RESET)
	begin
		rst_flag<=1'b0;
	end
	else
	begin
		rst_flag<=1'b1;

	end
end


always @ (q_buff)
begin
	Q<=q_buff;
end

endmodule