data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/Dlatch.v
data/verilator_xmls/3e3b4bee-e516-44e0-bf56-29abb89f232a.xml
module Dlatch (G, D, Q, Q1);
input G, D;
output Q1, Q;

reg Q1, Q;

always @(D or G)
	if (G)
	  begin
	    Q <= D;
	    Q1 <= ~D;
	   end
endmodule
module Dlatch (G, D, Q, Q1);

input G, D;
output Q1, Q;

reg Q1, Q;

always @(D or G)
	if (G)
	  begin
	    Q <= D;
	    Q1 <= ~D;
	   end
endmodule