data/full_repos/permissive/117439411/Pacman_ACL_v1/format_data.v
1: b"%Error: data/full_repos/permissive/117439411/Pacman_ACL_v1/format_data.v:76: Cannot find file containing module: 'Div'\n   Div Division(\n   ^~~\n        ... Looked in:\n             data/full_repos/permissive/117439411/Pacman_ACL_v1,data/full_repos/permissive/117439411/Div\n             data/full_repos/permissive/117439411/Pacman_ACL_v1,data/full_repos/permissive/117439411/Div.v\n             data/full_repos/permissive/117439411/Pacman_ACL_v1,data/full_repos/permissive/117439411/Div.sv\n             Div\n             Div.v\n             Div.sv\n             obj_dir/Div\n             obj_dir/Div.v\n             obj_dir/Div.sv\n%Error: data/full_repos/permissive/117439411/Pacman_ACL_v1/format_data.v:88: Cannot find file containing module: 'Binary_To_BCD'\n   Binary_To_BCD BtoBCD(\n   ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Format_Data(
		CLK,
		DCLK,
		RST,
		DIN,
		BCDOUT
);





   input           CLK;
   input           DCLK;
   input           RST;
   input [8:0]     DIN;
   output [11:0]   BCDOUT;
   



   

   parameter [7:0] DIVISOR = 8'b10100011;
   parameter [6:0] SCALING = 7'b1000000;
   

   wire [15:0]     tmpDIVIDEND;
   wire [14:0]     quo;
   wire [7:0]      rmd;
   wire            rfd;
   

   wire [8:0]      inputBCD;
   wire [15:0]     outputBCD;
   



   

   assign tmpDIVIDEND = DIN * SCALING;
   

   assign inputBCD = quo[8:0];
   



   Div Division(
				.clk(CLK),
				.dividend(tmpDIVIDEND[14:0]),
				.divisor(DIVISOR),
				.rfd(rfd),
				.quotient(quo),
				.fractional(rmd)
	);
   



   Binary_To_BCD BtoBCD(
				.CLK(CLK),
				.RST(RST),
				.START(DCLK),
				.BIN(inputBCD),
				.BCDOUT(outputBCD)
	);
   

   assign BCDOUT[11:0] = {outputBCD[11:8], {outputBCD[7:4], outputBCD[3:0]}};
   
endmodule
module Format_Data(
		CLK,
		DCLK,
		RST,
		DIN,
		BCDOUT
);






   input           CLK;
   input           DCLK;
   input           RST;
   input [8:0]     DIN;
   output [11:0]   BCDOUT;
   



   

   parameter [7:0] DIVISOR = 8'b10100011;
   parameter [6:0] SCALING = 7'b1000000;
   

   wire [15:0]     tmpDIVIDEND;
   wire [14:0]     quo;
   wire [7:0]      rmd;
   wire            rfd;
   

   wire [8:0]      inputBCD;
   wire [15:0]     outputBCD;
   



   

   assign tmpDIVIDEND = DIN * SCALING;
   

   assign inputBCD = quo[8:0];
   



   Div Division(
				.clk(CLK),
				.dividend(tmpDIVIDEND[14:0]),
				.divisor(DIVISOR),
				.rfd(rfd),
				.quotient(quo),
				.fractional(rmd)
	);
   



   Binary_To_BCD BtoBCD(
				.CLK(CLK),
				.RST(RST),
				.START(DCLK),
				.BIN(inputBCD),
				.BCDOUT(outputBCD)
	);
   

   assign BCDOUT[11:0] = {outputBCD[11:8], {outputBCD[7:4], outputBCD[3:0]}};
   
endmodule