data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/nexys4.sv
1: b"%Error: data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/nexys4.sv:28: Cannot find file containing module: 'cpu'\ncpu \n^~~\n        ... Looked in:\n             data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl,data/full_repos/permissive/169639758/cpu\n             data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl,data/full_repos/permissive/169639758/cpu.v\n             data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl,data/full_repos/permissive/169639758/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s)\n"
module sram(
	input clk,
	input [15:0]waddr,
	input [15:0]wdata,
	input [15:0]raddr,
	output reg [15:0]rdata,
	input we,
	input re
	);

reg [15:0]mem[0:4095];

always @(posedge clk) begin
	if (we)
		mem[waddr[11:0]] <= wdata;
	if (re)
		rdata <= mem[raddr[11:0]];
end

endmodule
module sram(
	input clk,
	input [15:0]waddr,
	input [15:0]wdata,
	input [15:0]raddr,
	output reg [15:0]rdata,
	input we,
	input re
	);


reg [15:0]mem[0:4095];

always @(posedge clk) begin
	if (we)
		mem[waddr[11:0]] <= wdata;
	if (re)
		rdata <= mem[raddr[11:0]];
end

endmodule