data/full_repos/permissive/135852214/Verilog/inv.v
data/verilator_xmls/b6da0d21-7a61-41ec-bf9f-460caea7ee12.xml
module inv(
    input a,
    output out
    );
assign out = ~a;

endmodule
module inv(
    input a,
    output out
    );

assign out = ~a;

endmodule