data/full_repos/permissive/142844950/rtl/p_addsub/p_addsub_ftb.v
 line:455: before: "/"
1: b"%Error: data/full_repos/permissive/142844950/rtl/p_addsub/p_addsub_ftb.v:14: Unsupported or unknown PLI call: $anyseq\nreg  [31:0]  lhs     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/p_addsub/p_addsub_ftb.v:15: Unsupported or unknown PLI call: $anyseq\nreg  [31:0]  rhs     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/p_addsub/p_addsub_ftb.v:16: Unsupported or unknown PLI call: $anyseq\nreg  [ 4:0]  pw      = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/p_addsub/p_addsub_ftb.v:18: Unsupported or unknown PLI call: $anyseq\nreg          sub     = $anyseq;  \n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/p_addsub/p_addsub_ftb.v:35: syntax error, unexpected '(', expecting property\n    restrict(pw_sum == 1);\n             ^~~~~~\n%Error: Exiting due to 5 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module p_addsub_ftb (

input clock,
input reset

);

reg  [31:0]  lhs     = $anyseq;
reg  [31:0]  rhs     = $anyseq;
reg  [ 4:0]  pw      = $anyseq;
wire         cin     = 1'b0;
reg          sub     = $anyseq;

wire [31:0]  carry_out  ;
wire [31:0]  result     ;
wire [31:0]  expectation;
wire [31:0]  carry_exp  ;

wire         pw_32   = pw[0];
wire         pw_16   = pw[1];
wire         pw_8    = pw[2];
wire         pw_4    = pw[3];
wire         pw_2    = pw[4];

wire [4:0]   pw_sum  = pw_32 + pw_16 + pw_8 + pw_4 + pw_2;

always @(posedge clock) begin

    restrict(pw_sum == 1);

    if(pw_32) begin
        
        assert(result == expectation);

    end else if(pw_16) begin
        
        assert(result == expectation);

    end else if(pw_8 ) begin

        assert(result == expectation);

    end else if(pw_4 ) begin
        
        assert(result == expectation);

    end else if(pw_2 ) begin
        
        assert(result == expectation);

    end

end





p_addsub i_p_addsub (
.lhs   (lhs   ),
.rhs   (rhs   ),
.pw    (pw    ),
.sub   (sub   ),
.cin   (cin   ),
.c_en  (1'b1  ),
.c_out (c_out ),
.result(result)
);




fml_p_addsub_checker i_p_addsub_checker (
.lhs        (lhs         ),
.rhs        (rhs         ),
.pw         (pw          ),
.sub        (sub         ),
.expectation(expectation )
);


endmodule
module p_addsub_ftb (

input clock,
input reset

);


reg  [31:0]  lhs     = $anyseq;
reg  [31:0]  rhs     = $anyseq;
reg  [ 4:0]  pw      = $anyseq;
wire         cin     = 1'b0;
reg          sub     = $anyseq;

wire [31:0]  carry_out  ;
wire [31:0]  result     ;
wire [31:0]  expectation;
wire [31:0]  carry_exp  ;

wire         pw_32   = pw[0];
wire         pw_16   = pw[1];
wire         pw_8    = pw[2];
wire         pw_4    = pw[3];
wire         pw_2    = pw[4];

wire [4:0]   pw_sum  = pw_32 + pw_16 + pw_8 + pw_4 + pw_2;

always @(posedge clock) begin

    restrict(pw_sum == 1);

    if(pw_32) begin
        
        assert(result == expectation);

    end else if(pw_16) begin
        
        assert(result == expectation);

    end else if(pw_8 ) begin

        assert(result == expectation);

    end else if(pw_4 ) begin
        
        assert(result == expectation);

    end else if(pw_2 ) begin
        
        assert(result == expectation);

    end

end





p_addsub i_p_addsub (
.lhs   (lhs   ),
.rhs   (rhs   ),
.pw    (pw    ),
.sub   (sub   ),
.cin   (cin   ),
.c_en  (1'b1  ),
.c_out (c_out ),
.result(result)
);




fml_p_addsub_checker i_p_addsub_checker (
.lhs        (lhs         ),
.rhs        (rhs         ),
.pw         (pw          ),
.sub        (sub         ),
.expectation(expectation )
);


endmodule