data/full_repos/permissive/158845296/register.v
data/verilator_xmls/0219478d-e028-4d51-bffa-d8bebf27c8df.xml
module register #(parameter WIDTH = 32, INIT = 0)
(
    input  clock,
    input  reset,
    input  enable,
    input  [(WIDTH-1):0] D,
    output reg [(WIDTH-1):0] Q
);

    initial
        Q = INIT;

    always @(posedge clock) begin
        Q <= (reset) ? INIT : ((enable) ? D : Q);
    end

endmodule
module register #(parameter WIDTH = 32, INIT = 0)
(
    input  clock,
    input  reset,
    input  enable,
    input  [(WIDTH-1):0] D,
    output reg [(WIDTH-1):0] Q
);


    initial
        Q = INIT;

    always @(posedge clock) begin
        Q <= (reset) ? INIT : ((enable) ? D : Q);
    end

endmodule