data/full_repos/permissive/143278/ivltests/packeda2.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/packeda2.v:12: Unsupported: Ignoring delay on this delayed statement.\n      #0;  \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test (output logic[7:0] sum, input logic [7:0]a);

   assign sum = a + 8'd5;

endmodule
module test (output logic[7:0] sum, input logic [7:0]a);


   assign sum = a + 8'd5;

endmodule