data/full_repos/permissive/165160692/04.FPGA/5932_74HC08/stimulus/testbench08.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC08/stimulus/testbench08.v:10: Unsupported: Ignoring delay on this delayed statement.\n#10 b=b<<1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC08/stimulus/testbench08.v:11: Unsupported: Ignoring delay on this delayed statement.\n#10 b=b<<1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC08/stimulus/testbench08.v:12: Unsupported: Ignoring delay on this delayed statement.\n#10 b=b<<1;\n^\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC08/stimulus/testbench08.v:6: Cannot find file containing module: \'HC08\'\nHC08 u1(a,b,y);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC08/stimulus,data/full_repos/permissive/165160692/HC08\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC08/stimulus,data/full_repos/permissive/165160692/HC08.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC08/stimulus,data/full_repos/permissive/165160692/HC08.sv\n             HC08\n             HC08.v\n             HC08.sv\n             obj_dir/HC08\n             obj_dir/HC08.v\n             obj_dir/HC08.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
reg[4:1]a,b;
wire[4:1]y;
HC08 u1(a,b,y);
initial
begin
a=4'b1111;b=4'b0001;
#10 b=b<<1;
#10 b=b<<1;
#10 b=b<<1;
end
endmodule
module testbench();

reg[4:1]a,b;
wire[4:1]y;
HC08 u1(a,b,y);
initial
begin
a=4'b1111;b=4'b0001;
#10 b=b<<1;
#10 b=b<<1;
#10 b=b<<1;
end
endmodule