data/full_repos/permissive/122184933/FPGA/reset.v
data/verilator_xmls/a4c55a5c-3726-432d-a329-43dc0798d4b6.xml
module reset (

	input wire clk,

	output reg rst
);


reg [1:0] cnt = 0;


always @ (posedge clk)
begin

	if (cnt != 2'b11) begin

		cnt <= cnt + 1'b1;

		rst <= 1'b1;

	end else begin
		rst <= 1'b0;
	end
end

endmodule
module reset (

	input wire clk,

	output reg rst
);



reg [1:0] cnt = 0;


always @ (posedge clk)
begin

	if (cnt != 2'b11) begin

		cnt <= cnt + 1'b1;

		rst <= 1'b1;

	end else begin
		rst <= 1'b0;
	end
end

endmodule