data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v
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1: b'%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:22: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:41: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:60: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:89: Duplicate declaration of module: \'top_module\'\nmodule top_module ( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:113: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:138: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:165: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/VerilogLanguage/Procedure.v:2: ... Location of original declaration\nmodule top_module(\n       ^~~~~~~~~~\n%Error: Exiting due to 7 warning(s)\n'
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    always @(*)begin
        up = 1'b0;
        down = 1'b0;
        left = 1'b0;
        right = 1'b0;
        case(scancode)
            16'he06b: left = 1'b1;
            16'he072: down = 1'b1;
            16'he074: right = 1'b1;
            16'he075: up = 1'b1;
        endcase
    end
endmodule
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  );
 
    always @(*)begin
        up = 1'b0;
        down = 1'b0;
        left = 1'b0;
        right = 1'b0;
        case(scancode)
            16'he06b: left = 1'b1;
            16'he072: down = 1'b1;
            16'he074: right = 1'b1;
            16'he075: up = 1'b1;
        endcase
    end
endmodule