data/full_repos/permissive/127511545/src/MIPSStimulus.v
 line:22: before: "reg"
1: b'%Warning-STMTDLY: data/full_repos/permissive/127511545/src/MIPSStimulus.v:13: Unsupported: Ignoring delay on this delayed statement.\n always #(ClockDelay / 2) CLK = ~CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/127511545/src/MIPSStimulus.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #(ClockDelay / 4);\n   ^\n%Error: data/full_repos/permissive/127511545/src/MIPSStimulus.v:11: Cannot find file containing module: \'MIPSPipeline\'\n MIPSPipeline mips(CLK, Reset);\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/MIPSPipeline\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/MIPSPipeline.v\n             data/full_repos/permissive/127511545/src,data/full_repos/permissive/127511545/MIPSPipeline.sv\n             MIPSPipeline\n             MIPSPipeline.v\n             MIPSPipeline.sv\n             obj_dir/MIPSPipeline\n             obj_dir/MIPSPipeline.v\n             obj_dir/MIPSPipeline.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MIPSStimulus();

	parameter ClockDelay = 5000;
	reg CLK, Reset;

	MIPSPipeline mips(CLK, Reset);
	initial CLK = 0;
	always #(ClockDelay / 2) CLK = ~CLK;
	initial 
		begin
			Reset = 1;
			#(ClockDelay / 4);
			Reset = 0;
		end

endmodule
module MIPSStimulus();


	parameter ClockDelay = 5000;
	reg CLK, Reset;

	MIPSPipeline mips(CLK, Reset);
	initial CLK = 0;
	always #(ClockDelay / 2) CLK = ~CLK;
	initial 
		begin
			Reset = 1;
			#(ClockDelay / 4);
			Reset = 0;
		end

endmodule