data/full_repos/permissive/20688874/coding_theory/syn/netlist/spare/ee577bHw2q1tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/20688874/coding_theory/syn/netlist/spare/ee577bHw2q1tb.v:26: Cannot find include file: ee577bHw2q1.v\n`include "ee577bHw2q1.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/coding_theory/syn/netlist/spare,data/full_repos/permissive/20688874/ee577bHw2q1.v\n             data/full_repos/permissive/20688874/coding_theory/syn/netlist/spare,data/full_repos/permissive/20688874/ee577bHw2q1.v.v\n             data/full_repos/permissive/20688874/coding_theory/syn/netlist/spare,data/full_repos/permissive/20688874/ee577bHw2q1.v.sv\n             ee577bHw2q1.v\n             ee577bHw2q1.v.v\n             ee577bHw2q1.v.sv\n             obj_dir/ee577bHw2q1.v\n             obj_dir/ee577bHw2q1.v.v\n             obj_dir/ee577bHw2q1.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/netlist/spare/ee577bHw2q1tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n     #5 clk <= 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/netlist/spare/ee577bHw2q1tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n     #5 clk <= 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/netlist/spare/ee577bHw2q1tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/netlist/spare/ee577bHw2q1tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/coding_theory/syn/netlist/spare/ee577bHw2q1tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module tbfsm();

	

	wire disp_Q,disp_D,disp_N,disp_P,done;
	

	reg [6:0] money,price;
	reg start,clk,reset;
	

	fsmVendingMachine fsm (


		disp_Q,disp_D,disp_N,disp_P,done,money,price,start,clk,reset);
	
	

	always begin

    	#5 clk <= 0;
    	#5 clk <= 1;
    end	
	

	initial
	begin

		$display($time, " << Starting the simulation >>");
		

		money = 7'd75;
		price = 7'd64;
		reset = 1'b0;
		start = 1'b1;
		

		#50
		money = 7'd100;
		price = 7'd54;
		reset = 1'b0;
		start = 1'b1;
		

		#50
		money = 7'd50;
		price = 7'd27;
		reset = 1'b0;
		start = 1'b1;
		

		#50
		money = 7'd50;
		price = 7'd27;
		reset = 1'b0;
		start = 1'b1;
		

		
		$display($time, " << Finishing the simulation >>");
	end

endmodule
module tbfsm();


	

	wire disp_Q,disp_D,disp_N,disp_P,done;
	

	reg [6:0] money,price;
	reg start,clk,reset;
	

	fsmVendingMachine fsm (


		disp_Q,disp_D,disp_N,disp_P,done,money,price,start,clk,reset);
	
	

	always begin

    	#5 clk <= 0;
    	#5 clk <= 1;
    end	
	

	initial
	begin

		$display($time, " << Starting the simulation >>");
		

		money = 7'd75;
		price = 7'd64;
		reset = 1'b0;
		start = 1'b1;
		

		#50
		money = 7'd100;
		price = 7'd54;
		reset = 1'b0;
		start = 1'b1;
		

		#50
		money = 7'd50;
		price = 7'd27;
		reset = 1'b0;
		start = 1'b1;
		

		#50
		money = 7'd50;
		price = 7'd27;
		reset = 1'b0;
		start = 1'b1;
		

		
		$display($time, " << Finishing the simulation >>");
	end

endmodule