data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l.v
None: at end of input
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l.v:185: Cannot find file containing module: 'lfsr4'\n lfsr4 LFSR0 (\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo,data/full_repos/permissive/20430511/lfsr4\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo,data/full_repos/permissive/20430511/lfsr4.v\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo,data/full_repos/permissive/20430511/lfsr4.sv\n             lfsr4\n             lfsr4.v\n             lfsr4.sv\n             obj_dir/lfsr4\n             obj_dir/lfsr4.v\n             obj_dir/lfsr4.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l.v:190: Cannot find file containing module: 'lfsr4'\n lfsr4 LFSR1 (\n ^~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l.v:196: Cannot find file containing module: 'lfsr4'\n lfsr4 LFSR2 (\n ^~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15l.v:202: Cannot find file containing module: 'lfsr4'\n lfsr4 LFSR3 (\n ^~~~~\n%Error: Exiting due to 4 error(s)\n"
module fifo15l (
		reset_i,
		
		rd_clk_i,
		rd_en_i,
		rd_data_o,
		
		wr_clk_i,
		wr_en_i,
		wr_data_i,
		
		empty_no,
		full_o,
		one_o,
		
		empty_nro,
		full_ro,
		one_ro
	);
	
	parameter	WIDTH	= 16;
	
	input	reset_i;
	
	input	rd_clk_i;
	input	rd_en_i;
	output	[WIDTH-1:0]	rd_data_o;
	
	input	wr_clk_i;
	input	wr_en_i;
	input	[WIDTH-1:0]	wr_data_i;
	
	output	empty_no;
	output	full_o;
	output	one_o;
	
	output	empty_nro;
	output	full_ro;
	output	one_ro;
	
	reg	[WIDTH-1:0]	mem [0:15];
	

	reg	[3:0]	f_start	= 4'b0001;
	reg	[3:0]	f_end	= 4'b0001;
	wire	[3:0]	next_st, next_end;
	


	wire	empty_nw	= (f_start != f_end);
	wire	full_w		= (next_end == f_start);
	wire	one_w		= (next_st == f_end);
	
	assign	empty_no	= empty_nw;
	assign	full_o		= full_w;
	assign	one_o		= one_w;
	
	






	wire	[3:0]	next_next_end;
	wire	[3:0]	next_next_st;
	wire	sorta_gettin_full	= (next_next_end == f_start);
	wire	sorta_two_left		= (next_next_st == f_end);
	reg	empty_nro	= 0;
	reg	full_ro		= 0;
	reg	one_ro		= 0;
	always @(posedge rd_clk_i)
	begin
		if (reset_i)
		begin
			empty_nro	<= 0;
			one_ro		<= 0;
			full_ro		<= 0;
		end
		else
		begin
			case ({sorta_gettin_full, full_w, rd_en_i, wr_en_i})
			4'b1001:	full_ro	<= 1;
			4'b0111:	full_ro	<= 1;
			4'b0100:	full_ro	<= 1;
			default:	full_ro	<= 0;
			endcase
			
			if (!empty_nw && !rd_en_i && wr_en_i)
				empty_nro	<= 1;
			else if (empty_nw && !one_w)
				empty_nro	<= 1;
			else if (one_w && rd_en_i && wr_en_i)
				empty_nro	<= 1;
			else if (empty_nw && !rd_en_i && !wr_en_i)
				empty_nro	<= 1;
			else if (empty_nw && wr_en_i)
				empty_nro	<= 1;
			else
				empty_nro	<= 0;
			
			if (one_w && rd_en_i && wr_en_i)
				one_ro	<= 1;
			else if (one_w && !rd_en_i && !wr_en_i)
				one_ro	<= 1;
			else if (sorta_two_left && rd_en_i)
				one_ro	<= 1;
			else if (!empty_nw && wr_en_i)
				one_ro	<= 1;
			else
				one_ro	<= 0;
		end
	end
	
	

	always @(posedge rd_clk_i)
	begin
		if (reset_i)
			f_start	<= 4'b0001;
		else
		begin
			if (rd_en_i)
				f_start	<= next_st;
		end
	end
	

	always @(posedge wr_clk_i)
	begin
		if (reset_i)
			f_end	<= 4'b0001;
		else
		begin
			if (wr_en_i)
			begin
				mem [f_end]	<= wr_data_i;

				f_end		<= next_end;
			end
		end
	end
	
	

	assign	rd_data_o	= mem [f_start];
	
	
	wire	[WIDTH-1:0]	test1	= mem [1];
	wire	[WIDTH-1:0]	test2	= mem [2];
	wire	[WIDTH-1:0]	test4	= mem [4];
	


	lfsr4 LFSR0 (
		.count_i(f_start),
		.count_o(next_st)
	);
	
	lfsr4 LFSR1 (
		.count_i(f_end),
		.count_o(next_end)
	);
	

	lfsr4 LFSR2 (
		.count_i(next_end),
		.count_o(next_next_end)
	);
	

	lfsr4 LFSR3 (
		.count_i(next_st),
		.count_o(next_next_st)
	);
	
	



`ifdef __icarus
	initial begin : Init
		init_mem (0);
	end
	
	
	task init_mem;
		input	val;
		integer	val, n;
	begin : Init_Mem
		for (n = 0; n < 16; n = n + 1)
			mem [n]	= val;
	end
	endtask
`endif
	
endmodule
module fifo15l (
		reset_i,
		
		rd_clk_i,
		rd_en_i,
		rd_data_o,
		
		wr_clk_i,
		wr_en_i,
		wr_data_i,
		
		empty_no,
		full_o,
		one_o,
		
		empty_nro,
		full_ro,
		one_ro
	);

	
	parameter	WIDTH	= 16;
	
	input	reset_i;
	
	input	rd_clk_i;
	input	rd_en_i;
	output	[WIDTH-1:0]	rd_data_o;
	
	input	wr_clk_i;
	input	wr_en_i;
	input	[WIDTH-1:0]	wr_data_i;
	
	output	empty_no;
	output	full_o;
	output	one_o;
	
	output	empty_nro;
	output	full_ro;
	output	one_ro;
	
	reg	[WIDTH-1:0]	mem [0:15];
	

	reg	[3:0]	f_start	= 4'b0001;
	reg	[3:0]	f_end	= 4'b0001;
	wire	[3:0]	next_st, next_end;
	


	wire	empty_nw	= (f_start != f_end);
	wire	full_w		= (next_end == f_start);
	wire	one_w		= (next_st == f_end);
	
	assign	empty_no	= empty_nw;
	assign	full_o		= full_w;
	assign	one_o		= one_w;
	
	






	wire	[3:0]	next_next_end;
	wire	[3:0]	next_next_st;
	wire	sorta_gettin_full	= (next_next_end == f_start);
	wire	sorta_two_left		= (next_next_st == f_end);
	reg	empty_nro	= 0;
	reg	full_ro		= 0;
	reg	one_ro		= 0;
	always @(posedge rd_clk_i)
	begin
		if (reset_i)
		begin
			empty_nro	<= 0;
			one_ro		<= 0;
			full_ro		<= 0;
		end
		else
		begin
			case ({sorta_gettin_full, full_w, rd_en_i, wr_en_i})
			4'b1001:	full_ro	<= 1;
			4'b0111:	full_ro	<= 1;
			4'b0100:	full_ro	<= 1;
			default:	full_ro	<= 0;
			endcase
			
			if (!empty_nw && !rd_en_i && wr_en_i)
				empty_nro	<= 1;
			else if (empty_nw && !one_w)
				empty_nro	<= 1;
			else if (one_w && rd_en_i && wr_en_i)
				empty_nro	<= 1;
			else if (empty_nw && !rd_en_i && !wr_en_i)
				empty_nro	<= 1;
			else if (empty_nw && wr_en_i)
				empty_nro	<= 1;
			else
				empty_nro	<= 0;
			
			if (one_w && rd_en_i && wr_en_i)
				one_ro	<= 1;
			else if (one_w && !rd_en_i && !wr_en_i)
				one_ro	<= 1;
			else if (sorta_two_left && rd_en_i)
				one_ro	<= 1;
			else if (!empty_nw && wr_en_i)
				one_ro	<= 1;
			else
				one_ro	<= 0;
		end
	end
	
	

	always @(posedge rd_clk_i)
	begin
		if (reset_i)
			f_start	<= 4'b0001;
		else
		begin
			if (rd_en_i)
				f_start	<= next_st;
		end
	end
	

	always @(posedge wr_clk_i)
	begin
		if (reset_i)
			f_end	<= 4'b0001;
		else
		begin
			if (wr_en_i)
			begin
				mem [f_end]	<= wr_data_i;

				f_end		<= next_end;
			end
		end
	end
	
	

	assign	rd_data_o	= mem [f_start];
	
	
	wire	[WIDTH-1:0]	test1	= mem [1];
	wire	[WIDTH-1:0]	test2	= mem [2];
	wire	[WIDTH-1:0]	test4	= mem [4];
	


	lfsr4 LFSR0 (
		.count_i(f_start),
		.count_o(next_st)
	);
	
	lfsr4 LFSR1 (
		.count_i(f_end),
		.count_o(next_end)
	);
	

	lfsr4 LFSR2 (
		.count_i(next_end),
		.count_o(next_next_end)
	);
	

	lfsr4 LFSR3 (
		.count_i(next_st),
		.count_o(next_next_st)
	);
	
	



`ifdef __icarus
	initial begin : Init
		init_mem (0);
	end
	
	
	task init_mem;
		input	val;
		integer	val, n;
	begin : Init_Mem
		for (n = 0; n < 16; n = n + 1)
			mem [n]	= val;
	end
	endtask
`endif
	
endmodule