data/full_repos/permissive/199399537/uart_speed_select.v
data/verilator_xmls/d35c4d1d-afac-4fa0-a093-6ac1e3061cfc.xml
module uart_speed_select(
				clk,
				rst_n,
				bps_start,
				clk_bps
			);

input clk;
input rst_n;
input bps_start;
output clk_bps;




`define		BPS_PARA		5207
`define 	BPS_PARA_2		2603



reg[12:0] cnt;
reg clk_bps_r;
reg[2:0] uart_ctrl;


always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
		cnt <= 13'd0;
	else if(cnt == `BPS_PARA) 
		cnt <= 13'd0;
	else if(bps_start) 
		cnt <= cnt+1'b1;
	else 
		cnt <= 13'd0;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
			clk_bps_r <= 1'b0;
	else if(cnt == `BPS_PARA_2) 
			clk_bps_r <= 1'b1;
	else 
			clk_bps_r <= 1'b0;

assign clk_bps = clk_bps_r;

endmodule
module uart_speed_select(
				clk,
				rst_n,
				bps_start,
				clk_bps
			);


input clk;
input rst_n;
input bps_start;
output clk_bps;




`define		BPS_PARA		5207
`define 	BPS_PARA_2		2603



reg[12:0] cnt;
reg clk_bps_r;
reg[2:0] uart_ctrl;


always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
		cnt <= 13'd0;
	else if(cnt == `BPS_PARA) 
		cnt <= 13'd0;
	else if(bps_start) 
		cnt <= cnt+1'b1;
	else 
		cnt <= 13'd0;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
			clk_bps_r <= 1'b0;
	else if(cnt == `BPS_PARA_2) 
			clk_bps_r <= 1'b1;
	else 
			clk_bps_r <= 1'b0;

assign clk_bps = clk_bps_r;

endmodule