data/full_repos/permissive/20270692/labs/lab4/four_bit_adder_tb.v
 line:69: before: "output"
1: b'%Error: data/full_repos/permissive/20270692/labs/lab4/four_bit_adder_tb.v:7: Cannot find include file: four_bit_adder.v\n`include "four_bit_adder.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab4,data/full_repos/permissive/20270692/four_bit_adder.v\n             data/full_repos/permissive/20270692/labs/lab4,data/full_repos/permissive/20270692/four_bit_adder.v.v\n             data/full_repos/permissive/20270692/labs/lab4,data/full_repos/permissive/20270692/four_bit_adder.v.sv\n             four_bit_adder.v\n             four_bit_adder.v.v\n             four_bit_adder.v.sv\n             obj_dir/four_bit_adder.v\n             obj_dir/four_bit_adder.v.v\n             obj_dir/four_bit_adder.v.sv\n%Error: data/full_repos/permissive/20270692/labs/lab4/four_bit_adder_tb.v:13: syntax error, unexpected \';\', expecting \')\' or \',\'\n  output A0, A1, A2, A3, B0, B1, B2, B3, C0;\n                                           ^\n%Error: data/full_repos/permissive/20270692/labs/lab4/four_bit_adder_tb.v:33: syntax error, unexpected IDENTIFIER\n  four_bit_adder I1 (A0, A1, A2, A3, B0, B1, B2, B3, C0, D0, D1, D2, D3, D4);\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/20270692/labs/lab4/four_bit_adder_tb.v:75: Unsupported or unknown PLI call: $monitor\n    $monitor("time=%03d", $time,,\n    ^~~~~~~~\n%Error: data/full_repos/permissive/20270692/labs/lab4/four_bit_adder_tb.v:84: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("fulladder.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/20270692/labs/lab4/four_bit_adder_tb.v:85: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module four_bit_adder_tb (A0, A1, A2, A3, B0, B1, B2, B3,

  output A0, A1, A2, A3, B0, B1, B2, B3, C0;
  reg A0, A1, A2, A3, B0, B1, B2, B3, C0;

  wire D0, D1, D2, D3, D4;

  reg t_A0 [5000:0];
  reg t_A1 [5000:0];
  reg t_A2 [5000:0];
  reg t_A3 [5000:0];
  reg t_B0 [5000:0];
  reg t_B1 [5000:0];
  reg t_B2 [5000:0];
  reg t_B3 [5000:0];
  reg t_C0 [5000:0];

  reg t_clock;
  reg [31:0] vectornum;

  integer fp;

  four_bit_adder I1 (A0, A1, A2, A3, B0, B1, B2, B3, C0, D0, D1, D2, D3, D4);



  initial
  begin
    t_clock=0;
    forever #5 t_clock=~t_clock;
  end

  initial
  begin
    $readmemb("./bit_str_a_0.txt",t_A0);
    $readmemb("./bit_str_a_1.txt",t_A1);
    $readmemb("./bit_str_a_2.txt",t_A2);
    $readmemb("./bit_str_a_3.txt",t_A3);
    $readmemb("./bit_str_b_0.txt",t_B0);
    $readmemb("./bit_str_b_1.txt",t_B1);
    $readmemb("./bit_str_b_2.txt",t_B2);
    $readmemb("./bit_str_b_3.txt",t_B3);
    $readmemb("./bit_str_c_0.txt",t_C0);
    vectornum=0;
  end

  always @(posedge t_clock)
  begin
    A0<=t_A0[vectornum];
    A1<=t_A1[vectornum];
    A2<=t_A2[vectornum];
    A3<=t_A3[vectornum];
    B0<=t_B0[vectornum];
    B1<=t_B1[vectornum];
    B2<=t_B2[vectornum];
    B3<=t_B3[vectornum];
    C0<=t_C0[vectornum];
    vectornum<=vectornum+1;
  end

  initial
  begin


    $monitor("time=%03d", $time,,


      "A=%b%b%b%b B=%b%b%b%b, C=%b | D=%b%b%b%b%b",
      A3, A2, A1, A0,
      B3, B2, B1, B0,
      C0,
      D4, D3, D2, D1, D0,
      );
    $dumpfile("fulladder.vcd");
    $dumpvars;
    #1000

    $finish;
  end

endmodule
module four_bit_adder_tb (A0, A1, A2, A3, B0, B1, B2, B3,

  output A0, A1, A2, A3, B0, B1, B2, B3, C0;

  reg A0, A1, A2, A3, B0, B1, B2, B3, C0;

  wire D0, D1, D2, D3, D4;

  reg t_A0 [5000:0];
  reg t_A1 [5000:0];
  reg t_A2 [5000:0];
  reg t_A3 [5000:0];
  reg t_B0 [5000:0];
  reg t_B1 [5000:0];
  reg t_B2 [5000:0];
  reg t_B3 [5000:0];
  reg t_C0 [5000:0];

  reg t_clock;
  reg [31:0] vectornum;

  integer fp;

  four_bit_adder I1 (A0, A1, A2, A3, B0, B1, B2, B3, C0, D0, D1, D2, D3, D4);



  initial
  begin
    t_clock=0;
    forever #5 t_clock=~t_clock;
  end

  initial
  begin
    $readmemb("./bit_str_a_0.txt",t_A0);
    $readmemb("./bit_str_a_1.txt",t_A1);
    $readmemb("./bit_str_a_2.txt",t_A2);
    $readmemb("./bit_str_a_3.txt",t_A3);
    $readmemb("./bit_str_b_0.txt",t_B0);
    $readmemb("./bit_str_b_1.txt",t_B1);
    $readmemb("./bit_str_b_2.txt",t_B2);
    $readmemb("./bit_str_b_3.txt",t_B3);
    $readmemb("./bit_str_c_0.txt",t_C0);
    vectornum=0;
  end

  always @(posedge t_clock)
  begin
    A0<=t_A0[vectornum];
    A1<=t_A1[vectornum];
    A2<=t_A2[vectornum];
    A3<=t_A3[vectornum];
    B0<=t_B0[vectornum];
    B1<=t_B1[vectornum];
    B2<=t_B2[vectornum];
    B3<=t_B3[vectornum];
    C0<=t_C0[vectornum];
    vectornum<=vectornum+1;
  end

  initial
  begin


    $monitor("time=%03d", $time,,


      "A=%b%b%b%b B=%b%b%b%b, C=%b | D=%b%b%b%b%b",
      A3, A2, A1, A0,
      B3, B2, B1, B0,
      C0,
      D4, D3, D2, D1, D0,
      );
    $dumpfile("fulladder.vcd");
    $dumpvars;
    #1000

    $finish;
  end

endmodule