data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v
1: b'%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:6: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:75: Define or directive not defined: \'`SERIAL_WCNT\'\n      end else if( waitnum >= `SERIAL_WCNT ) begin\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:75: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      end else if( waitnum >= `SERIAL_WCNT ) begin\n                                           ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:81: syntax error, unexpected else\n      end else begin\n          ^~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:192: Define or directive not defined: \'`SERIAL_WCNT\'\n   assign waitcnt = `SERIAL_WCNT;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:192: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   assign waitcnt = `SERIAL_WCNT;\n                                ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:283: Define or directive not defined: \'`APP_SIZE\'\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:283: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                               ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:287: Define or directive not defined: \'`APP_SIZE\'\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:287: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                               ^\n%Error: Exiting due to 10 error(s)\n'
module PLOADER(CLK, RST_X, RXD, ADDR, DATA, WE_32, WE_128, DONE);
   input  wire       CLK, RST_X, RXD;
   output reg [31:0] ADDR;
   output reg [127:0] DATA;
   output reg        WE_32;
   output reg 	     WE_128;
   output reg        DONE;

   reg [31:0] 	     waddr;

   wire 	     SER_EN;
   wire [7:0] 	     SER_DATA;
   
   UartRx recv(CLK, RST_X, RXD, SER_DATA, SER_EN);

   always @(posedge CLK or negedge RST_X) begin
      if(~RST_X) begin
         {ADDR, DATA, WE_32, WE_128, waddr, DONE} <= 0;
      end else begin
         if(DONE==0 && SER_EN) begin
            ADDR   <= waddr;            
            DATA   <= {SER_DATA, DATA[127:8]};
            WE_32  <= (waddr[1:0]==3) ? 1'b1 : 1'b0;
	    WE_128 <= (waddr[3:0]==15) ? 1'b1 : 1'b0;
            waddr <= waddr + 1;
            if(waddr>=`APP_SIZE) DONE <= 1;
         end else begin
            WE_32 <= 0;
	    WE_128 <= 0;
            if(waddr>=`APP_SIZE) DONE <= 1;
         end
      end
   end
endmodule
module PLOADER(CLK, RST_X, RXD, ADDR, DATA, WE_32, WE_128, DONE);

   input  wire       CLK, RST_X, RXD;
   output reg [31:0] ADDR;
   output reg [127:0] DATA;
   output reg        WE_32;
   output reg 	     WE_128;
   output reg        DONE;

   reg [31:0] 	     waddr;

   wire 	     SER_EN;
   wire [7:0] 	     SER_DATA;
   
   UartRx recv(CLK, RST_X, RXD, SER_DATA, SER_EN);

   always @(posedge CLK or negedge RST_X) begin
      if(~RST_X) begin
         {ADDR, DATA, WE_32, WE_128, waddr, DONE} <= 0;
      end else begin
         if(DONE==0 && SER_EN) begin
            ADDR   <= waddr;            
            DATA   <= {SER_DATA, DATA[127:8]};
            WE_32  <= (waddr[1:0]==3) ? 1'b1 : 1'b0;
	    WE_128 <= (waddr[3:0]==15) ? 1'b1 : 1'b0;
            waddr <= waddr + 1;
            if(waddr>=`APP_SIZE) DONE <= 1;
         end else begin
            WE_32 <= 0;
	    WE_128 <= 0;
            if(waddr>=`APP_SIZE) DONE <= 1;
         end
      end
   end
endmodule