data/full_repos/permissive/117880471/HW3/piso_8bit.v
 line:29: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/piso_8bit.v:13: Unsupported: Ignoring delay on this delayed statement.\n #00 clock = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/piso_8bit.v:14: Unsupported: Ignoring delay on this delayed statement.\n forever #20 clock = ~clock;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/piso_8bit.v:19: Unsupported: Ignoring delay on this delayed statement.\n #00 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/piso_8bit.v:20: Unsupported: Ignoring delay on this delayed statement.\n #50 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/piso_8bit.v:21: Unsupported: Ignoring delay on this delayed statement.\n #500 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/piso_8bit.v:26: Unsupported: Ignoring delay on this delayed statement.\n #10 a = 8\'b0101_1100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/piso_8bit.v:27: Unsupported: Ignoring delay on this delayed statement.\n #110 a = 8\'b0000_0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/piso_8bit.v:28: Unsupported: Ignoring delay on this delayed statement.\n #110 a = 8\'b1100_1100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/piso_8bit.v:29: Unsupported: Ignoring delay on this delayed statement.\n #110 $stop;\n ^\n%Error: data/full_repos/permissive/117880471/HW3/piso_8bit.v:34: Unsupported or unknown PLI call: $monitor\n $monitor("time=%3d, piso_out=%b, a=%8b, clock=%1b, reset=%1b", $time, piso_out, a, clock, reset);\n ^~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/piso_8bit.v:39: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("piso_8bit.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/piso_8bit.v:40: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/piso_8bit.v:58: syntax error, unexpected \';\'\n  a >> 1;\n        ^\n%Error: Exiting due to 4 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module piso_8bit(piso_out, a, clock, reset);

output reg piso_out;
input wire [7:0] a;
input wire clock, reset;

always @(posedge clock or reset) begin
	if (reset) begin
		i = 0;
		piso_out = 1'b0;
	end
	else begin
		piso_out = a[0];
		a >> 1;
	end
end

endmodule
module piso_8bit(piso_out, a, clock, reset);


output reg piso_out;
input wire [7:0] a;
input wire clock, reset;

always @(posedge clock or reset) begin
	if (reset) begin
		i = 0;
		piso_out = 1'b0;
	end
	else begin
		piso_out = a[0];
		a >> 1;
	end
end

endmodule