data/full_repos/permissive/212981921/rtl/ls04.v
data/verilator_xmls/da68419c-5d25-4955-be52-c45927b25051.xml
module ls04
(
    input wire  a,
    output wire y
);

not(y, a);

endmodule
module ls04
(
    input wire  a,
    output wire y
);


not(y, a);

endmodule