data/full_repos/permissive/195227969/work/cold_store/decompressattempts/interresting_m_decompress.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/f1d18b1b-8ced-4516-b499-70677bb113bf.xml
module m_decompress
  (
   input [15:0]     c,
   output reg [31:0]    e
   );
   wire [4:0]       inx = {c[1:0],c[15:13]};

   wire [60:0]      cc;
   wire             rs1eq2 = c[11:7] == 5'b00010;
   wire             rs1eq0 = c[11:7] == 5'b00000;
   wire             rs2eq0 = c[6:2]  == 5'b00000;
   
   assign cc[15:0] = c[15:0];

   assign cc[60:53] = 0;
   assign cc[43:40] = 0;
   assign cc[35:27] = 0;
   assign cc[19:16] = 0;
   

   assign cc[36] = c[11:10] == 2'b10 ? c[12] : 0;
   assign cc[37] = c[11:10] == 2'b10 ? c[12] : ((c[11:10] == 2'b01) || ( {c[11:10],c[6:5]} == 4'b1100 )) ? 1 : 0;
   assign cc[38] = c[11:10] != 2'b11 ? c[6] : 0;
   assign cc[39] = c[11:10] != 2'b11 ? c[5] : 1;
                  

   assign cc[20] = rs1eq2 ? c[4] : c[12];
   assign cc[21] = rs1eq2 ? c[3] : c[12];
   assign cc[22] = rs1eq2 ? c[5] : c[12];
   assign cc[23] = rs1eq2 ? c[2] : c[12];
   assign cc[24] = rs1eq2 ? c[6] : c[12];
   assign cc[25] = rs1eq2 ? 0    : c[12];
   assign cc[26] = rs1eq2 ? 1    : c[6];
   

   wire [2:0]       jnx = {c[12],rs1eq0,rs2eq0};
   assign cc[44] = (jnx == 0 || jnx == 2 || jnx == 4 || jnx == 6 ) ? c[6] : 0;
   assign cc[45] = (jnx == 0 || jnx == 2 || jnx == 4 || jnx == 6 ) ? c[5] : 0;
   assign cc[46] = (jnx == 0 || jnx == 2 || jnx == 4 || jnx == 6 ) ? c[4] : 0;
   assign cc[47] = (jnx == 0 || jnx == 2 || jnx == 4 || jnx == 6 ) ? c[3] : 0;
   assign cc[48] = (jnx == 0 || jnx == 2 || jnx == 4 || jnx == 6 ) ? c[2] : (jnx == 7 ) ? 1 : 0;
   assign cc[49] = (jnx == 1 || jnx == 3 || jnx == 5 || jnx == 4 || jnx == 6 ) ? c[11] : 0;
   assign cc[50] = (jnx == 1 || jnx == 3 || jnx == 5 || jnx == 4 || jnx == 6 ) ? c[10] : 0;
   assign cc[51] = (jnx == 1 || jnx == 3 || jnx == 5 || jnx == 4 || jnx == 6 ) ? c[9] : 0;
   assign cc[52] = (jnx == 1 || jnx == 3 || jnx == 5 || jnx == 4 || jnx == 6 ) ? c[8] : 0;


































   always @(*) begin
      case (inx)
        5'h00  : e[31:24] ={  1'b0  , 1'b0  , cc[10], cc[9] , cc[8] , cc[7] , cc[12], cc[11]}; 
        5'h01  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h02  : e[31:24] ={  1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , cc[5] , cc[12], cc[11]};
        5'h03  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h04  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h05  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h06  : e[31:24] ={  1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , cc[5] , cc[12], 1'b0  };
        5'h07  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h08  : e[31:24] ={  cc[12], cc[12], cc[12], cc[12], cc[12], cc[12], cc[12], cc[6] };
        5'h09  : e[31:24] ={  cc[12], cc[8] , cc[10], cc[9] , cc[6] , cc[7] , cc[2] , cc[11]};
        5'h0a  : e[31:24] ={  cc[12], cc[12], cc[12], cc[12], cc[12], cc[12], cc[12], cc[6] };
        5'h0b  : e[31:24] ={  cc[12], cc[12], cc[12], cc[20], cc[21], cc[22], cc[23], cc[24]};
        5'h0c  : e[31:24] ={  cc[36], cc[37], cc[36], cc[36], cc[36], cc[36], cc[36], cc[38]};
        5'h0d  : e[31:24] ={  cc[12], cc[8] , cc[10], cc[9] , cc[6] , cc[7] , cc[2] , cc[11]};
        5'h0e  : e[31:24] ={  cc[12], cc[12], cc[12], cc[12], cc[6] , cc[5] , cc[2] , 1'b0  };
        5'h0f  : e[31:24] ={  cc[12], cc[12], cc[12], cc[12], cc[6] , cc[5] , cc[2] , 1'b0  };
        5'h10  : e[31:24] ={  1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , cc[6] };
        5'h11  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h12  : e[31:24] ={  1'b0  , 1'b0  , 1'b0  , 1'b0  , cc[3] , cc[2], cc[12] , cc[6] };
        5'h13  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h14  : e[31:24] ={  1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , cc[44]};
        5'h15  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h16  : e[31:24] ={  1'b0  , 1'b0  , 1'b0  , 1'b0  , cc[8] , cc[7] , cc[12], cc[6] };
        5'h17  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        default :e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
      endcase
   end










































































































































































































































































                  

   wire             e23_cc5  = ( inx == 0 || inx == 8 || inx == 9 || inx == 10 || inx == 13 || inx == 16 || inx == 18 || inx == 22 ) ? cc[5] : 0;
   wire             e23_cc10 = ( inx == 2 ) ? cc[10] : 0;
   wire             e23_1    = ( inx == 6 ) ? 1 : 0;
   wire             e23_cc25 = ( inx == 11 ) ? cc[25] : 0;
   wire             e23_cc39 = ( inx == 12 ) ? cc[39] : 0;
   wire             e23_cc45 = ( inx == 20 ) ? cc[45] : 0;
   always @(*) begin
      e[23] = e23_cc5 | e23_cc10 | e23_1 | e23_cc25 | e23_cc39 | e23_cc45;
   end
   

   wire             e22_cc6  = ( inx == 0 || inx == 2 ) ? cc[6] : 0;
   wire             e22_cc4  = ( inx == 6 || inx == 8 || inx == 9 || inx == 10 || inx == 12 || inx == 13 || inx == 16 || inx == 18 || inx == 22 ) ? cc[4] : 0;
   wire             e22_cc25 = e23_cc25;
   wire             e22_cc46 = ( inx == 20 ) ? cc[46] : 0;
   always @(*) begin
      e[22] = e22_cc6 | e22_cc4 | e22_cc25 | e22_cc46;
   end
   

   wire             e21_cc3  = ( inx == 6 || inx == 8 || inx == 9 || inx == 10 || inx == 12 || inx == 13 || inx == 16 || inx == 22 ) ? cc[3] : 0;
   wire             e21_cc25 = e23_cc25;
   wire             e21_cc47 = ( inx == 20 ) ? cc[47] : 0;
   always @(*) begin
      e[21] = e21_cc3 | e21_cc25 | e21_cc47;
   end
        

   wire             e20_cc2  = ( inx == 6 || inx == 8 || inx == 10 || inx == 12 || inx == 16 || inx == 22 ) ? cc[2] : 0;
   wire             e20_cc12 = ( inx == 9 || inx == 13 ) ? cc[12] : 0;
   wire             e20_cc25 = e23_cc25;
   wire             e20_cc48 = ( inx == 20 ) ? cc[48] : 0;
   always @(*) begin
      e[20] = e20_cc2 | e20_cc12 | e20_cc25 | e20_cc48;
   end
   

   wire             e19_cc11 = ( inx == 8 || inx == 16 ) ? cc[11] : 0;
   wire             e19_cc12 = e20_cc12;
   wire             e19_cc25 = e23_cc25;
   wire             e19_cc49 = ( inx == 20 ) ? cc[49] : 0;
   always @(*) begin
      e[19] = e19_cc11 | e19_cc12 | e19_cc25 | e19_cc49;
   end
           

   wire             e18_1    = (inx == 2 || inx == 6 || inx == 12 || inx == 14 || inx == 15 ) ? 1 : 0;
   wire             e18_cc10 = ( inx == 8 || inx == 16) ? cc[10] : 0;
   wire             e18_cc12 = e20_cc12;
   wire             e18_cc25 = e23_cc25;
   wire             e18_cc50 = ( inx == 20 ) ? cc[50] : 0;
   always @(*) begin
      e[18] = e18_1 | e18_cc10 | e18_cc12 | e18_cc25 | e18_cc50;
   end
   

   wire             e17_cc9  = ( inx == 2 || inx == 6 || inx == 8 || inx == 12 || inx == 14 || inx == 15 || inx == 16 ) ? cc[9] : 0;
   wire             e17_cc12 = e20_cc12;
   wire             e17_cc25 = e23_cc25;
   wire             c17_cc51 = ( inx == 20 ) ? cc[51] : 0;
   always @(*) begin
      e[17] = e17_cc9 | e17_cc12 | e17_cc25 | c17_cc51;
   end
              

   wire             e16_1    = ( inx == 0 || inx == 18 || inx == 22 ) ? 1 : 0;
   wire             e16_cc8  = ( inx == 2 || inx == 6 || inx == 8 || inx == 12 || inx == 14 || inx == 15 || inx == 16 ) ? cc[8] : 0;
   wire             e16_cc12 = e20_cc12;
   wire             e16_cc26 = ( inx == 11 ) ? cc[26] : 0;
   wire             e16_cc52 = ( inx == 20 ) ? cc[52] : 0;
   always @(*) begin
      e[16] = e16_1 | e16_cc8 | e16_cc12 | e16_cc26 | e16_cc52;
   end
   
   always @(*) begin
      e[15:0] = 0;
   end
   
endmodule
module m_decompress
  (
   input [15:0]     c,
   output reg [31:0]    e
   );

   wire [4:0]       inx = {c[1:0],c[15:13]};

   wire [60:0]      cc;
   wire             rs1eq2 = c[11:7] == 5'b00010;
   wire             rs1eq0 = c[11:7] == 5'b00000;
   wire             rs2eq0 = c[6:2]  == 5'b00000;
   
   assign cc[15:0] = c[15:0];

   assign cc[60:53] = 0;
   assign cc[43:40] = 0;
   assign cc[35:27] = 0;
   assign cc[19:16] = 0;
   

   assign cc[36] = c[11:10] == 2'b10 ? c[12] : 0;
   assign cc[37] = c[11:10] == 2'b10 ? c[12] : ((c[11:10] == 2'b01) || ( {c[11:10],c[6:5]} == 4'b1100 )) ? 1 : 0;
   assign cc[38] = c[11:10] != 2'b11 ? c[6] : 0;
   assign cc[39] = c[11:10] != 2'b11 ? c[5] : 1;
                  

   assign cc[20] = rs1eq2 ? c[4] : c[12];
   assign cc[21] = rs1eq2 ? c[3] : c[12];
   assign cc[22] = rs1eq2 ? c[5] : c[12];
   assign cc[23] = rs1eq2 ? c[2] : c[12];
   assign cc[24] = rs1eq2 ? c[6] : c[12];
   assign cc[25] = rs1eq2 ? 0    : c[12];
   assign cc[26] = rs1eq2 ? 1    : c[6];
   

   wire [2:0]       jnx = {c[12],rs1eq0,rs2eq0};
   assign cc[44] = (jnx == 0 || jnx == 2 || jnx == 4 || jnx == 6 ) ? c[6] : 0;
   assign cc[45] = (jnx == 0 || jnx == 2 || jnx == 4 || jnx == 6 ) ? c[5] : 0;
   assign cc[46] = (jnx == 0 || jnx == 2 || jnx == 4 || jnx == 6 ) ? c[4] : 0;
   assign cc[47] = (jnx == 0 || jnx == 2 || jnx == 4 || jnx == 6 ) ? c[3] : 0;
   assign cc[48] = (jnx == 0 || jnx == 2 || jnx == 4 || jnx == 6 ) ? c[2] : (jnx == 7 ) ? 1 : 0;
   assign cc[49] = (jnx == 1 || jnx == 3 || jnx == 5 || jnx == 4 || jnx == 6 ) ? c[11] : 0;
   assign cc[50] = (jnx == 1 || jnx == 3 || jnx == 5 || jnx == 4 || jnx == 6 ) ? c[10] : 0;
   assign cc[51] = (jnx == 1 || jnx == 3 || jnx == 5 || jnx == 4 || jnx == 6 ) ? c[9] : 0;
   assign cc[52] = (jnx == 1 || jnx == 3 || jnx == 5 || jnx == 4 || jnx == 6 ) ? c[8] : 0;


































   always @(*) begin
      case (inx)
        5'h00  : e[31:24] ={  1'b0  , 1'b0  , cc[10], cc[9] , cc[8] , cc[7] , cc[12], cc[11]}; 
        5'h01  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h02  : e[31:24] ={  1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , cc[5] , cc[12], cc[11]};
        5'h03  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h04  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h05  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h06  : e[31:24] ={  1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , cc[5] , cc[12], 1'b0  };
        5'h07  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h08  : e[31:24] ={  cc[12], cc[12], cc[12], cc[12], cc[12], cc[12], cc[12], cc[6] };
        5'h09  : e[31:24] ={  cc[12], cc[8] , cc[10], cc[9] , cc[6] , cc[7] , cc[2] , cc[11]};
        5'h0a  : e[31:24] ={  cc[12], cc[12], cc[12], cc[12], cc[12], cc[12], cc[12], cc[6] };
        5'h0b  : e[31:24] ={  cc[12], cc[12], cc[12], cc[20], cc[21], cc[22], cc[23], cc[24]};
        5'h0c  : e[31:24] ={  cc[36], cc[37], cc[36], cc[36], cc[36], cc[36], cc[36], cc[38]};
        5'h0d  : e[31:24] ={  cc[12], cc[8] , cc[10], cc[9] , cc[6] , cc[7] , cc[2] , cc[11]};
        5'h0e  : e[31:24] ={  cc[12], cc[12], cc[12], cc[12], cc[6] , cc[5] , cc[2] , 1'b0  };
        5'h0f  : e[31:24] ={  cc[12], cc[12], cc[12], cc[12], cc[6] , cc[5] , cc[2] , 1'b0  };
        5'h10  : e[31:24] ={  1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , cc[6] };
        5'h11  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h12  : e[31:24] ={  1'b0  , 1'b0  , 1'b0  , 1'b0  , cc[3] , cc[2], cc[12] , cc[6] };
        5'h13  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h14  : e[31:24] ={  1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , 1'b0  , cc[44]};
        5'h15  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        5'h16  : e[31:24] ={  1'b0  , 1'b0  , 1'b0  , 1'b0  , cc[8] , cc[7] , cc[12], cc[6] };
        5'h17  : e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
        default :e[31:24] ={  1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  , 1'bx  };
      endcase
   end










































































































































































































































































                  

   wire             e23_cc5  = ( inx == 0 || inx == 8 || inx == 9 || inx == 10 || inx == 13 || inx == 16 || inx == 18 || inx == 22 ) ? cc[5] : 0;
   wire             e23_cc10 = ( inx == 2 ) ? cc[10] : 0;
   wire             e23_1    = ( inx == 6 ) ? 1 : 0;
   wire             e23_cc25 = ( inx == 11 ) ? cc[25] : 0;
   wire             e23_cc39 = ( inx == 12 ) ? cc[39] : 0;
   wire             e23_cc45 = ( inx == 20 ) ? cc[45] : 0;
   always @(*) begin
      e[23] = e23_cc5 | e23_cc10 | e23_1 | e23_cc25 | e23_cc39 | e23_cc45;
   end
   

   wire             e22_cc6  = ( inx == 0 || inx == 2 ) ? cc[6] : 0;
   wire             e22_cc4  = ( inx == 6 || inx == 8 || inx == 9 || inx == 10 || inx == 12 || inx == 13 || inx == 16 || inx == 18 || inx == 22 ) ? cc[4] : 0;
   wire             e22_cc25 = e23_cc25;
   wire             e22_cc46 = ( inx == 20 ) ? cc[46] : 0;
   always @(*) begin
      e[22] = e22_cc6 | e22_cc4 | e22_cc25 | e22_cc46;
   end
   

   wire             e21_cc3  = ( inx == 6 || inx == 8 || inx == 9 || inx == 10 || inx == 12 || inx == 13 || inx == 16 || inx == 22 ) ? cc[3] : 0;
   wire             e21_cc25 = e23_cc25;
   wire             e21_cc47 = ( inx == 20 ) ? cc[47] : 0;
   always @(*) begin
      e[21] = e21_cc3 | e21_cc25 | e21_cc47;
   end
        

   wire             e20_cc2  = ( inx == 6 || inx == 8 || inx == 10 || inx == 12 || inx == 16 || inx == 22 ) ? cc[2] : 0;
   wire             e20_cc12 = ( inx == 9 || inx == 13 ) ? cc[12] : 0;
   wire             e20_cc25 = e23_cc25;
   wire             e20_cc48 = ( inx == 20 ) ? cc[48] : 0;
   always @(*) begin
      e[20] = e20_cc2 | e20_cc12 | e20_cc25 | e20_cc48;
   end
   

   wire             e19_cc11 = ( inx == 8 || inx == 16 ) ? cc[11] : 0;
   wire             e19_cc12 = e20_cc12;
   wire             e19_cc25 = e23_cc25;
   wire             e19_cc49 = ( inx == 20 ) ? cc[49] : 0;
   always @(*) begin
      e[19] = e19_cc11 | e19_cc12 | e19_cc25 | e19_cc49;
   end
           

   wire             e18_1    = (inx == 2 || inx == 6 || inx == 12 || inx == 14 || inx == 15 ) ? 1 : 0;
   wire             e18_cc10 = ( inx == 8 || inx == 16) ? cc[10] : 0;
   wire             e18_cc12 = e20_cc12;
   wire             e18_cc25 = e23_cc25;
   wire             e18_cc50 = ( inx == 20 ) ? cc[50] : 0;
   always @(*) begin
      e[18] = e18_1 | e18_cc10 | e18_cc12 | e18_cc25 | e18_cc50;
   end
   

   wire             e17_cc9  = ( inx == 2 || inx == 6 || inx == 8 || inx == 12 || inx == 14 || inx == 15 || inx == 16 ) ? cc[9] : 0;
   wire             e17_cc12 = e20_cc12;
   wire             e17_cc25 = e23_cc25;
   wire             c17_cc51 = ( inx == 20 ) ? cc[51] : 0;
   always @(*) begin
      e[17] = e17_cc9 | e17_cc12 | e17_cc25 | c17_cc51;
   end
              

   wire             e16_1    = ( inx == 0 || inx == 18 || inx == 22 ) ? 1 : 0;
   wire             e16_cc8  = ( inx == 2 || inx == 6 || inx == 8 || inx == 12 || inx == 14 || inx == 15 || inx == 16 ) ? cc[8] : 0;
   wire             e16_cc12 = e20_cc12;
   wire             e16_cc26 = ( inx == 11 ) ? cc[26] : 0;
   wire             e16_cc52 = ( inx == 20 ) ? cc[52] : 0;
   always @(*) begin
      e[16] = e16_1 | e16_cc8 | e16_cc12 | e16_cc26 | e16_cc52;
   end
   
   always @(*) begin
      e[15:0] = 0;
   end
   
endmodule