data/full_repos/permissive/102515926/Modules/SHR.v
data/verilator_xmls/010173d8-b660-45af-9f40-4daad532d567.xml
module SHR(a, sh_amt, d);

    parameter DATAWIDTH = 64;

    input [DATAWIDTH - 1:0] a;
    input [$clog2(DATAWIDTH) - 1:0] sh_amt;
    
    output reg [DATAWIDTH - 1:0] d;
    
    always @(*) begin
    
        d <= a >> sh_amt;
    
    end
    
endmodule
module SHR(a, sh_amt, d);


    parameter DATAWIDTH = 64;

    input [DATAWIDTH - 1:0] a;
    input [$clog2(DATAWIDTH) - 1:0] sh_amt;
    
    output reg [DATAWIDTH - 1:0] d;
    
    always @(*) begin
    
        d <= a >> sh_amt;
    
    end
    
endmodule