data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v
1: b'%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:110: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'h\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\x#  = h;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:112: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 64 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#case_alt_0  = $unsigned(\\#app_arg );\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:114: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'h1\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\y#  = h1;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:119: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#app_arg  = $unsigned(\\#w [31:0]);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:122: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'g\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#x#_0  = g;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:124: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 64 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#case_alt_1  = $unsigned(\\#app_arg_0 );\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:126: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'g1\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#y#_0  = g1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:131: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#app_arg_0  = $unsigned(\\#w_0 [31:0]);\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:134: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'f\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#x#_1  = f;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:136: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 64 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#case_alt_2  = $unsigned(\\#app_arg_1 );\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:138: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'f1\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#y#_1  = f1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:143: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#app_arg_1  = $unsigned(\\#w_1 [31:0]);\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:146: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'e\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#x#_2  = e;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:148: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 64 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#case_alt_3  = $unsigned(\\#app_arg_2 );\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:150: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'e2\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#y#_2  = e2;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:155: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#app_arg_2  = $unsigned(\\#w_2 [31:0]);\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:158: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'d\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#x#_3  = d;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:160: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 64 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#case_alt_4  = $unsigned(\\#app_arg_3 );\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:162: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'d1\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#y#_3  = d1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:167: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#app_arg_3  = $unsigned(\\#w_3 [31:0]);\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:170: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'c\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#x#_4  = c;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:172: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 64 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#case_alt_5  = $unsigned(\\#app_arg_4 );\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:174: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'c1\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#y#_4  = c1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:179: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#app_arg_4  = $unsigned(\\#w_4 [31:0]);\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:182: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'b\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#x#_5  = b;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:184: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 64 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#case_alt_6  = $unsigned(\\#app_arg_5 );\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:186: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'b1\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#y#_5  = b1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:191: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#app_arg_5  = $unsigned(\\#w_5 [31:0]);\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:194: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#x#_6  = a;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:196: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 64 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#case_alt_7  = $unsigned(\\#app_arg_6 );\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:198: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'a1\' generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#y#_6  = a1;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/154412777/hdl/verilog/Sha256/Sha256_addT8.v:203: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                          : ... In instance Sha256_addT8\n  assign \\#app_arg_6  = $unsigned(\\#w_6 [31:0]);\n                      ^\n%Error: Exiting due to 32 warning(s)\n'
module Sha256_addT8
    (
      input [255:0] ds 
    , input [255:0] ds1 


    , output wire [255:0] \#case_alt  
    );
  wire [31:0] a;
  wire [31:0] b;
  wire [31:0] c;
  wire [31:0] d;
  wire [31:0] e;
  wire [31:0] f;
  wire [31:0] g;
  wire [31:0] h;
  wire [31:0] a1;
  wire [31:0] b1;
  wire [31:0] c1;
  wire [31:0] d1;
  wire [31:0] e2;
  wire [31:0] f1;
  wire [31:0] g1;
  wire [31:0] h1;
  wire [63:0] \x# ;
  wire [31:0] \#case_alt_0 ;
  wire [63:0] \y# ;
  wire [63:0] \#app_arg ;
  wire [63:0] \#x#_0 ;
  wire [31:0] \#case_alt_1 ;
  wire [63:0] \#y#_0 ;
  wire [63:0] \#app_arg_0 ;
  wire [63:0] \#x#_1 ;
  wire [31:0] \#case_alt_2 ;
  wire [63:0] \#y#_1 ;
  wire [63:0] \#app_arg_1 ;
  wire [63:0] \#x#_2 ;
  wire [31:0] \#case_alt_3 ;
  wire [63:0] \#y#_2 ;
  wire [63:0] \#app_arg_2 ;
  wire [63:0] \#x#_3 ;
  wire [31:0] \#case_alt_4 ;
  wire [63:0] \#y#_3 ;
  wire [63:0] \#app_arg_3 ;
  wire [63:0] \#x#_4 ;
  wire [31:0] \#case_alt_5 ;
  wire [63:0] \#y#_4 ;
  wire [63:0] \#app_arg_4 ;
  wire [63:0] \#x#_5 ;
  wire [31:0] \#case_alt_6 ;
  wire [63:0] \#y#_5 ;
  wire [63:0] \#app_arg_5 ;
  wire [63:0] \#x#_6 ;
  wire [31:0] \#case_alt_7 ;
  wire [63:0] \#y#_6 ;
  wire [63:0] \#app_arg_6 ;
  wire [63:0] \#w ;
  wire [63:0] \#w_0 ;
  wire [63:0] \#w_1 ;
  wire [63:0] \#w_2 ;
  wire [63:0] \#w_3 ;
  wire [63:0] \#w_4 ;
  wire [63:0] \#w_5 ;
  wire [63:0] \#w_6 ;

  assign a = ds[255:224];

  assign b = ds[223:192];

  assign c = ds[191:160];

  assign d = ds[159:128];

  assign e = ds[127:96];

  assign f = ds[95:64];

  assign g = ds[63:32];

  assign h = ds[31:0];

  assign \#case_alt  = {\#case_alt_7 
                       ,\#case_alt_6 
                       ,\#case_alt_5 
                       ,\#case_alt_4 
                       ,\#case_alt_3 
                       ,\#case_alt_2 
                       ,\#case_alt_1 
                       ,\#case_alt_0 };

  assign a1 = ds1[255:224];

  assign b1 = ds1[223:192];

  assign c1 = ds1[191:160];

  assign d1 = ds1[159:128];

  assign e2 = ds1[127:96];

  assign f1 = ds1[95:64];

  assign g1 = ds1[63:32];

  assign h1 = ds1[31:0];

  assign \x#  = h;

  assign \#case_alt_0  = $unsigned(\#app_arg );

  assign \y#  = h1;

  assign \#w  = (\x#  + \y# );


  assign \#app_arg  = $unsigned(\#w [31:0]);


  assign \#x#_0  = g;

  assign \#case_alt_1  = $unsigned(\#app_arg_0 );

  assign \#y#_0  = g1;

  assign \#w_0  = (\#x#_0  + \#y#_0 );


  assign \#app_arg_0  = $unsigned(\#w_0 [31:0]);


  assign \#x#_1  = f;

  assign \#case_alt_2  = $unsigned(\#app_arg_1 );

  assign \#y#_1  = f1;

  assign \#w_1  = (\#x#_1  + \#y#_1 );


  assign \#app_arg_1  = $unsigned(\#w_1 [31:0]);


  assign \#x#_2  = e;

  assign \#case_alt_3  = $unsigned(\#app_arg_2 );

  assign \#y#_2  = e2;

  assign \#w_2  = (\#x#_2  + \#y#_2 );


  assign \#app_arg_2  = $unsigned(\#w_2 [31:0]);


  assign \#x#_3  = d;

  assign \#case_alt_4  = $unsigned(\#app_arg_3 );

  assign \#y#_3  = d1;

  assign \#w_3  = (\#x#_3  + \#y#_3 );


  assign \#app_arg_3  = $unsigned(\#w_3 [31:0]);


  assign \#x#_4  = c;

  assign \#case_alt_5  = $unsigned(\#app_arg_4 );

  assign \#y#_4  = c1;

  assign \#w_4  = (\#x#_4  + \#y#_4 );


  assign \#app_arg_4  = $unsigned(\#w_4 [31:0]);


  assign \#x#_5  = b;

  assign \#case_alt_6  = $unsigned(\#app_arg_5 );

  assign \#y#_5  = b1;

  assign \#w_5  = (\#x#_5  + \#y#_5 );


  assign \#app_arg_5  = $unsigned(\#w_5 [31:0]);


  assign \#x#_6  = a;

  assign \#case_alt_7  = $unsigned(\#app_arg_6 );

  assign \#y#_6  = a1;

  assign \#w_6  = (\#x#_6  + \#y#_6 );


  assign \#app_arg_6  = $unsigned(\#w_6 [31:0]);

endmodule
module Sha256_addT8
    (
      input [255:0] ds 
    , input [255:0] ds1 


    , output wire [255:0] \#case_alt  
    );

  wire [31:0] a;
  wire [31:0] b;
  wire [31:0] c;
  wire [31:0] d;
  wire [31:0] e;
  wire [31:0] f;
  wire [31:0] g;
  wire [31:0] h;
  wire [31:0] a1;
  wire [31:0] b1;
  wire [31:0] c1;
  wire [31:0] d1;
  wire [31:0] e2;
  wire [31:0] f1;
  wire [31:0] g1;
  wire [31:0] h1;
  wire [63:0] \x# ;
  wire [31:0] \#case_alt_0 ;
  wire [63:0] \y# ;
  wire [63:0] \#app_arg ;
  wire [63:0] \#x#_0 ;
  wire [31:0] \#case_alt_1 ;
  wire [63:0] \#y#_0 ;
  wire [63:0] \#app_arg_0 ;
  wire [63:0] \#x#_1 ;
  wire [31:0] \#case_alt_2 ;
  wire [63:0] \#y#_1 ;
  wire [63:0] \#app_arg_1 ;
  wire [63:0] \#x#_2 ;
  wire [31:0] \#case_alt_3 ;
  wire [63:0] \#y#_2 ;
  wire [63:0] \#app_arg_2 ;
  wire [63:0] \#x#_3 ;
  wire [31:0] \#case_alt_4 ;
  wire [63:0] \#y#_3 ;
  wire [63:0] \#app_arg_3 ;
  wire [63:0] \#x#_4 ;
  wire [31:0] \#case_alt_5 ;
  wire [63:0] \#y#_4 ;
  wire [63:0] \#app_arg_4 ;
  wire [63:0] \#x#_5 ;
  wire [31:0] \#case_alt_6 ;
  wire [63:0] \#y#_5 ;
  wire [63:0] \#app_arg_5 ;
  wire [63:0] \#x#_6 ;
  wire [31:0] \#case_alt_7 ;
  wire [63:0] \#y#_6 ;
  wire [63:0] \#app_arg_6 ;
  wire [63:0] \#w ;
  wire [63:0] \#w_0 ;
  wire [63:0] \#w_1 ;
  wire [63:0] \#w_2 ;
  wire [63:0] \#w_3 ;
  wire [63:0] \#w_4 ;
  wire [63:0] \#w_5 ;
  wire [63:0] \#w_6 ;

  assign a = ds[255:224];

  assign b = ds[223:192];

  assign c = ds[191:160];

  assign d = ds[159:128];

  assign e = ds[127:96];

  assign f = ds[95:64];

  assign g = ds[63:32];

  assign h = ds[31:0];

  assign \#case_alt  = {\#case_alt_7 
                       ,\#case_alt_6 
                       ,\#case_alt_5 
                       ,\#case_alt_4 
                       ,\#case_alt_3 
                       ,\#case_alt_2 
                       ,\#case_alt_1 
                       ,\#case_alt_0 };

  assign a1 = ds1[255:224];

  assign b1 = ds1[223:192];

  assign c1 = ds1[191:160];

  assign d1 = ds1[159:128];

  assign e2 = ds1[127:96];

  assign f1 = ds1[95:64];

  assign g1 = ds1[63:32];

  assign h1 = ds1[31:0];

  assign \x#  = h;

  assign \#case_alt_0  = $unsigned(\#app_arg );

  assign \y#  = h1;

  assign \#w  = (\x#  + \y# );


  assign \#app_arg  = $unsigned(\#w [31:0]);


  assign \#x#_0  = g;

  assign \#case_alt_1  = $unsigned(\#app_arg_0 );

  assign \#y#_0  = g1;

  assign \#w_0  = (\#x#_0  + \#y#_0 );


  assign \#app_arg_0  = $unsigned(\#w_0 [31:0]);


  assign \#x#_1  = f;

  assign \#case_alt_2  = $unsigned(\#app_arg_1 );

  assign \#y#_1  = f1;

  assign \#w_1  = (\#x#_1  + \#y#_1 );


  assign \#app_arg_1  = $unsigned(\#w_1 [31:0]);


  assign \#x#_2  = e;

  assign \#case_alt_3  = $unsigned(\#app_arg_2 );

  assign \#y#_2  = e2;

  assign \#w_2  = (\#x#_2  + \#y#_2 );


  assign \#app_arg_2  = $unsigned(\#w_2 [31:0]);


  assign \#x#_3  = d;

  assign \#case_alt_4  = $unsigned(\#app_arg_3 );

  assign \#y#_3  = d1;

  assign \#w_3  = (\#x#_3  + \#y#_3 );


  assign \#app_arg_3  = $unsigned(\#w_3 [31:0]);


  assign \#x#_4  = c;

  assign \#case_alt_5  = $unsigned(\#app_arg_4 );

  assign \#y#_4  = c1;

  assign \#w_4  = (\#x#_4  + \#y#_4 );


  assign \#app_arg_4  = $unsigned(\#w_4 [31:0]);


  assign \#x#_5  = b;

  assign \#case_alt_6  = $unsigned(\#app_arg_5 );

  assign \#y#_5  = b1;

  assign \#w_5  = (\#x#_5  + \#y#_5 );


  assign \#app_arg_5  = $unsigned(\#w_5 [31:0]);


  assign \#x#_6  = a;

  assign \#case_alt_7  = $unsigned(\#app_arg_6 );

  assign \#y#_6  = a1;

  assign \#w_6  = (\#x#_6  + \#y#_6 );


  assign \#app_arg_6  = $unsigned(\#w_6 [31:0]);

endmodule