data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:57: Cell has missing pin: \'clk1_out\'\n  pll_test u_pll_test (\n           ^~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:57: Cell has missing pin: \'clk2_out\'\n  pll_test u_pll_test (\n           ^~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:225: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg0 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:231: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:237: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg2 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:439: Cell has missing pin: \'en\'\n  reg_ar_as_w8 reg0 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:445: Cell has missing pin: \'en\'\n  reg_ar_as_w4 reg1 (\n               ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:569: Cell has missing pin: \'en\'\n  reg_ar_as_w13 reg0 (\n                ^~~~\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:601: Cannot find file containing module: \'EG_LOGIC_BUFG\'\n  EG_LOGIC_BUFG bufg_feedback (\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG.v\n             data/full_repos/permissive/194847941/demo/6_uart_loopback,data/full_repos/permissive/194847941/EG_LOGIC_BUFG.sv\n             EG_LOGIC_BUFG\n             EG_LOGIC_BUFG.v\n             EG_LOGIC_BUFG.sv\n             obj_dir/EG_LOGIC_BUFG\n             obj_dir/EG_LOGIC_BUFG.v\n             obj_dir/EG_LOGIC_BUFG.sv\n%Error: data/full_repos/permissive/194847941/demo/6_uart_loopback/uart_top_tdread.v:604: Cannot find file containing module: \'EG_PHY_PLL\'\n  EG_PHY_PLL #(\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module uart_top
  (
  ext_clk_25m,
  ext_rst_n,
  uart_rx,
  uart_tx
  );

  input ext_clk_25m;
  input ext_rst_n;
  input uart_rx;
  output uart_tx;

  parameter BPS_SET = 96;
  parameter CLK_PERIORD = 40;
  wire [7:0] rx_data;
  wire bps_start1;
  wire bps_start2;
  wire clk_25m;
  wire clk_bps1;
  wire clk_bps2;
  wire n0;
  wire rx_int;
  wire sys_rst_n;

  my_uart_rx my_uart_rx (
    .clk(clk_25m),
    .clk_bps(clk_bps1),
    .rst_n(sys_rst_n),
    .uart_rx(uart_rx),
    .bps_start(bps_start1),
    .rx_data(rx_data),
    .rx_int(rx_int));
  my_uart_tx my_uart_tx (
    .clk(clk_25m),
    .clk_bps(clk_bps2),
    .rst_n(sys_rst_n),
    .rx_data(rx_data),
    .rx_int(rx_int),
    .bps_start(bps_start2),
    .uart_tx(uart_tx));
  speed_setting speed_rx (
    .bps_start(bps_start1),
    .clk(clk_25m),
    .rst_n(sys_rst_n),
    .clk_bps(clk_bps1));
  speed_setting speed_tx (
    .bps_start(bps_start2),
    .clk(clk_25m),
    .rst_n(sys_rst_n),
    .clk_bps(clk_bps2));
  not u0 (n0, ext_rst_n);
  pll_test u_pll_test (
    .refclk(ext_clk_25m),
    .reset(n0),
    .clk0_out(clk_25m),
    .extlock(sys_rst_n));

endmodule
module uart_top
  (
  ext_clk_25m,
  ext_rst_n,
  uart_rx,
  uart_tx
  );


  input ext_clk_25m;
  input ext_rst_n;
  input uart_rx;
  output uart_tx;

  parameter BPS_SET = 96;
  parameter CLK_PERIORD = 40;
  wire [7:0] rx_data;
  wire bps_start1;
  wire bps_start2;
  wire clk_25m;
  wire clk_bps1;
  wire clk_bps2;
  wire n0;
  wire rx_int;
  wire sys_rst_n;

  my_uart_rx my_uart_rx (
    .clk(clk_25m),
    .clk_bps(clk_bps1),
    .rst_n(sys_rst_n),
    .uart_rx(uart_rx),
    .bps_start(bps_start1),
    .rx_data(rx_data),
    .rx_int(rx_int));
  my_uart_tx my_uart_tx (
    .clk(clk_25m),
    .clk_bps(clk_bps2),
    .rst_n(sys_rst_n),
    .rx_data(rx_data),
    .rx_int(rx_int),
    .bps_start(bps_start2),
    .uart_tx(uart_tx));
  speed_setting speed_rx (
    .bps_start(bps_start1),
    .clk(clk_25m),
    .rst_n(sys_rst_n),
    .clk_bps(clk_bps1));
  speed_setting speed_tx (
    .bps_start(bps_start2),
    .clk(clk_25m),
    .rst_n(sys_rst_n),
    .clk_bps(clk_bps2));
  not u0 (n0, ext_rst_n);
  pll_test u_pll_test (
    .refclk(ext_clk_25m),
    .reset(n0),
    .clk0_out(clk_25m),
    .extlock(sys_rst_n));

endmodule