data/full_repos/permissive/156061594/i2c_master_TB.v
 line:50: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/156061594/i2c_master_TB.v:46: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk_in = !clk_in;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/156061594/i2c_master_TB.v:50: syntax error, unexpected \'@\'\n    repeat(1) @(posedge clk_in)\n              ^\n%Error: data/full_repos/permissive/156061594/i2c_master_TB.v:53: syntax error, unexpected \'@\'\n    repeat(2) @(posedge clk_in)\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/156061594/i2c_master_TB.v:65: Unsupported: Ignoring delay on this delayed statement.\n      #230  sda_en = \'b0;  \n      ^\n%Error: data/full_repos/permissive/156061594/i2c_master_TB.v:78: Unsupported or unknown PLI call: $monitor\n$monitor($time,"\\tsda line when read = %b",read_value);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/156061594/i2c_master_TB.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #500 $finish;\n    ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module i2c_master_TB();


  wire i2c_scl_inout;
  wire  i2c_sda_inout;
  reg [6:0]addr;
  reg [7:0]data;
  reg clk_in;
  reg rst_in;
  reg start;
  wire ready_out;
  reg read_write;
  wire read_value;
  reg sda_en;
  reg sda_in;


  i2c_master master(
                    .i2c_scl_inout      (i2c_scl_inout),
                    .i2c_sda_inout      (i2c_sda_inout),
                    .addr               (addr),
                    .data               (data),
                    .clk_in             (clk_in),
                    .rst_in             (rst_in),
                    .start              (start),
                    .ready_out          (ready_out),
                    .read_write         (read_write)
	           );


  initial begin

    addr  	  = 'b1010101;
    data	  = 'b11111111;
    clk_in	  = 'b0;
    rst_in	  = 'b0;

  end


  always #10 clk_in = !clk_in;


  initial begin
    repeat(1) @(posedge clk_in)
      rst_in = 'b1;

    repeat(2) @(posedge clk_in)
      rst_in = 'b0;
  end



  assign read_value = (!sda_en) ?sda_in : 'hz ;



  initial begin
      read_write = 'b0;
      #230  sda_en = 'b0;



$monitor($time,"\tsda line when read = %b",read_value);
    sda_in  = 'b0;
    #500 $finish;
  end

endmodule
module i2c_master_TB();



  wire i2c_scl_inout;
  wire  i2c_sda_inout;
  reg [6:0]addr;
  reg [7:0]data;
  reg clk_in;
  reg rst_in;
  reg start;
  wire ready_out;
  reg read_write;
  wire read_value;
  reg sda_en;
  reg sda_in;


  i2c_master master(
                    .i2c_scl_inout      (i2c_scl_inout),
                    .i2c_sda_inout      (i2c_sda_inout),
                    .addr               (addr),
                    .data               (data),
                    .clk_in             (clk_in),
                    .rst_in             (rst_in),
                    .start              (start),
                    .ready_out          (ready_out),
                    .read_write         (read_write)
	           );


  initial begin

    addr  	  = 'b1010101;
    data	  = 'b11111111;
    clk_in	  = 'b0;
    rst_in	  = 'b0;

  end


  always #10 clk_in = !clk_in;


  initial begin
    repeat(1) @(posedge clk_in)
      rst_in = 'b1;

    repeat(2) @(posedge clk_in)
      rst_in = 'b0;
  end



  assign read_value = (!sda_en) ?sda_in : 'hz ;



  initial begin
      read_write = 'b0;
      #230  sda_en = 'b0;



$monitor($time,"\tsda line when read = %b",read_value);
    sda_in  = 'b0;
    #500 $finish;
  end

endmodule