data/full_repos/permissive/141596082/thrid_party/unisims/ODDR2.v
1: b"%Error: data/full_repos/permissive/141596082/thrid_party/unisims/ODDR2.v:19: Cannot find file containing module: 'flip_flop_d'\nflip_flop_d ffD0(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141596082/thrid_party/unisims,data/full_repos/permissive/141596082/flip_flop_d\n             data/full_repos/permissive/141596082/thrid_party/unisims,data/full_repos/permissive/141596082/flip_flop_d.v\n             data/full_repos/permissive/141596082/thrid_party/unisims,data/full_repos/permissive/141596082/flip_flop_d.sv\n             flip_flop_d\n             flip_flop_d.v\n             flip_flop_d.sv\n             obj_dir/flip_flop_d\n             obj_dir/flip_flop_d.v\n             obj_dir/flip_flop_d.sv\n%Error: data/full_repos/permissive/141596082/thrid_party/unisims/ODDR2.v:28: Cannot find file containing module: 'flip_flop_d'\nflip_flop_d ffD1(\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ODDR2 #(
	parameter DDR_ALIGNMENT = "NONE",
	parameter INIT = 1'b0,
	parameter SRTYPE = "ASYNC"
)(
	input D0,
	input D1,
	input C0,
	input C1,
	input CE,
	input R,
	input S,
	output reg Q
);

wire Q0, Q1;

flip_flop_d ffD0(
	.D(D0),
	.clk(C0),
	.ce(CE),
	.reset(R),
	.set(S),
	.Q(Q0)
);

flip_flop_d ffD1(
	.D(D1),
	.clk(C1),
	.ce(CE),
	.reset(R),
	.set(S),
	.Q(Q1)
);

always @(*) begin
	if (C0 & ~C1) 
		Q <= Q0;
	else if(~C0 & C1)
		Q <= Q1;
end
endmodule
module ODDR2 #(
	parameter DDR_ALIGNMENT = "NONE",
	parameter INIT = 1'b0,
	parameter SRTYPE = "ASYNC"
)(
	input D0,
	input D1,
	input C0,
	input C1,
	input CE,
	input R,
	input S,
	output reg Q
);


wire Q0, Q1;

flip_flop_d ffD0(
	.D(D0),
	.clk(C0),
	.ce(CE),
	.reset(R),
	.set(S),
	.Q(Q0)
);

flip_flop_d ffD1(
	.D(D1),
	.clk(C1),
	.ce(CE),
	.reset(R),
	.set(S),
	.Q(Q1)
);

always @(*) begin
	if (C0 & ~C1) 
		Q <= Q0;
	else if(~C0 & C1)
		Q <= Q1;
end
endmodule