data/full_repos/permissive/215901856/Source/base_cell.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/215901856/Source/base_cell.v:17: Multiple top level modules\n                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                             : ... Top module \'basecell_ha\'\nmodule basecell_ha(f1_i, f2_i, b_i, sum_o, c_o);\n       ^~~~~~~~~~~\n                                                                             : ... Top module \'basecell_fa\'\nmodule basecell_fa(f1_i, f2_i, b_i, c_i, sum_o, c_o);\n       ^~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module basecell_fa(f1_i, f2_i, b_i, c_i, sum_o, c_o);
  input f1_i, f2_i, b_i, c_i;
  output sum_o, c_o;

  wire pp;

  assign pp = f1_i & f2_i;

  FA adder(pp, b_i, c_i, sum_o, c_o);

endmodule
module basecell_fa(f1_i, f2_i, b_i, c_i, sum_o, c_o);

  input f1_i, f2_i, b_i, c_i;
  output sum_o, c_o;

  wire pp;

  assign pp = f1_i & f2_i;

  FA adder(pp, b_i, c_i, sum_o, c_o);

endmodule