data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_ram/rtl/verilog/wb_funcs.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_ram/rtl/verilog/wb_funcs.v:8: Cannot find include file: wb_bfm_params.v\n   `include "wb_bfm_params.v" \n            ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_ram/rtl/verilog,data/full_repos/permissive/19905110/wb_bfm_params.v\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_ram/rtl/verilog,data/full_repos/permissive/19905110/wb_bfm_params.v.v\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/cores/wb_ram/rtl/verilog,data/full_repos/permissive/19905110/wb_bfm_params.v.sv\n             wb_bfm_params.v\n             wb_bfm_params.v.v\n             wb_bfm_params.v.sv\n             obj_dir/wb_bfm_params.v\n             obj_dir/wb_bfm_params.v.v\n             obj_dir/wb_bfm_params.v.sv\n%Error: Exiting due to 1 error(s)\n'
function [aw-1:0] next_adr;

      input [aw-1:0] addr_i;

      input [2:0]    cti_i;

      input [1:0]    bte_i;

      begin
	  if(cti_i == 3'b010)
	       case (bte_i)
		 LINEAR_BURST  : next_adr = addr_i + 4;

		 WRAP_4_BURST  : next_adr = {addr_i[aw-1:4], addr_i[3:0]+4'd4};

		 WRAP_8_BURST  : next_adr = {addr_i[aw-1:5], addr_i[4:0]+5'd4};

		 WRAP_16_BURST : next_adr = {addr_i[aw-1:6], addr_i[5:0]+6'd4};

	       endcase
	  else
	    next_adr = addr_i;


      end
   endfunction
function [aw-1:0] next_adr;


      input [aw-1:0] addr_i;

      input [2:0]    cti_i;

      input [1:0]    bte_i;

      begin
	  if(cti_i == 3'b010)
	       case (bte_i)
		 LINEAR_BURST  : next_adr = addr_i + 4;

		 WRAP_4_BURST  : next_adr = {addr_i[aw-1:4], addr_i[3:0]+4'd4};

		 WRAP_8_BURST  : next_adr = {addr_i[aw-1:5], addr_i[4:0]+5'd4};

		 WRAP_16_BURST : next_adr = {addr_i[aw-1:6], addr_i[5:0]+6'd4};

	       endcase
	  else
	    next_adr = addr_i;


      end
   endfunction