data/full_repos/permissive/162533945/adder.v
1: b"%Error: data/full_repos/permissive/162533945/adder.v:42: Cannot find file containing module: 'mux_2to1_1bit'\n mux_2to1_1bit mux0(p0, p1, c8, cout);\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/mux_2to1_1bit\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/mux_2to1_1bit.v\n             data/full_repos/permissive/162533945,data/full_repos/permissive/162533945/mux_2to1_1bit.sv\n             mux_2to1_1bit\n             mux_2to1_1bit.v\n             mux_2to1_1bit.sv\n             obj_dir/mux_2to1_1bit\n             obj_dir/mux_2to1_1bit.v\n             obj_dir/mux_2to1_1bit.sv\n%Error: data/full_repos/permissive/162533945/adder.v:47: Cannot find file containing module: 'mux_2to1_1bit'\n   mux_2to1_1bit mux1(t0[i], t1[i], c8, s[i+8]);\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162533945/adder.v:19: Cannot find file containing module: 'mux_2to1_1bit'\n   mux_2to1_1bit mux1(t0[i], t1[i], c16, out[i+16]);\n   ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module adder(x, y, sub, out);

	input [31:0] x, y;
	input sub;
	output [31:0] out;

	wire c16;
	
	csa_16bit csa0(.x(x[15:0]), .y(y[15:0]), .cin(sub), .s(out[15:0]), .cout(c16));
	
	wire [15:0] t0, t1;
	wire p0, p1;
	csa_16bit csa1(.x(x[31:16]), .y(y[31:16]), .cin(1'b0), .s(t0), .cout(p0));
	csa_16bit csa2(.x(x[31:16]), .y(y[31:16]), .cin(1'b1), .s(t1), .cout(p1));
	
	genvar i;
	generate
		for (i=0; i<16; i=i+1) begin: mux
			mux_2to1_1bit mux1(t0[i], t1[i], c16, out[i+16]);
		end
	endgenerate

endmodule
module adder(x, y, sub, out);


	input [31:0] x, y;
	input sub;
	output [31:0] out;

	wire c16;
	
	csa_16bit csa0(.x(x[15:0]), .y(y[15:0]), .cin(sub), .s(out[15:0]), .cout(c16));
	
	wire [15:0] t0, t1;
	wire p0, p1;
	csa_16bit csa1(.x(x[31:16]), .y(y[31:16]), .cin(1'b0), .s(t0), .cout(p0));
	csa_16bit csa2(.x(x[31:16]), .y(y[31:16]), .cin(1'b1), .s(t1), .cout(p1));
	
	genvar i;
	generate
		for (i=0; i<16; i=i+1) begin: mux
			mux_2to1_1bit mux1(t0[i], t1[i], c16, out[i+16]);
		end
	endgenerate

endmodule