data/full_repos/permissive/143278/ivltests/pr581.v
 line:26: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr581.v:18: Unsupported: Ignoring delay on this delayed statement.\nalways #50 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr581.v:21: Unsupported or unknown PLI call: $monitor\n$monitor($time,"clk=%b,reset=%b,%b%b%b",clk,reset,data[1],data[2],data\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr581.v:25: Unsupported: Ignoring delay on this delayed statement.\n   #200 reset = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr581.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #200 $display("driver timeout"); $finish;\n   ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module module1(clock,reset,result);
input clock,reset;
output result;
reg result;
always @ (posedge clock)
if (reset) result <= 0; else result <= 1;
endmodule
module module1(clock,reset,result);

input clock,reset;
output result;
reg result;
always @ (posedge clock)
if (reset) result <= 0; else result <= 1;
endmodule