data/full_repos/permissive/161526648/IF_ID.v
data/verilator_xmls/47bfa215-af0f-4bd2-8378-0458704d0c09.xml
module IF_ID (clock,reset,IFFlush,NextPC_temp,Instruction_temp,Instruction_id,NextPC_id);
	input clock,reset,IFFlush;
	input[31:0] NextPC_temp,Instruction_temp;
	output reg[31:0] Instruction_id,NextPC_id;
	
	always @(posedge clock or posedge reset) begin
	if (reset==1'b1)
		begin
			Instruction_id <= 32'b0;
			NextPC_id <= 32'b0;
		end
	else if (IFFlush)
	   begin
			Instruction_id <= 32'b0;
			NextPC_id <= 32'b0;
		end
	else
		begin 
			Instruction_id <= Instruction_temp;
			NextPC_id <= NextPC_temp;
		end
	end
endmodule
module IF_ID (clock,reset,IFFlush,NextPC_temp,Instruction_temp,Instruction_id,NextPC_id);

	input clock,reset,IFFlush;
	input[31:0] NextPC_temp,Instruction_temp;
	output reg[31:0] Instruction_id,NextPC_id;
	
	always @(posedge clock or posedge reset) begin
	if (reset==1'b1)
		begin
			Instruction_id <= 32'b0;
			NextPC_id <= 32'b0;
		end
	else if (IFFlush)
	   begin
			Instruction_id <= 32'b0;
			NextPC_id <= 32'b0;
		end
	else
		begin 
			Instruction_id <= Instruction_temp;
			NextPC_id <= NextPC_temp;
		end
	end
endmodule