data/full_repos/permissive/107007139/Project/square_node_generator.v
data/verilator_xmls/ae5648e6-6916-4ab4-ba11-ee2b2b305d34.xml
module square_node_generator(
    input clk,
    input [4:0] select,
    output reg [11:0] out
    );
    

    reg [17:0] doi = 190839;
    reg [17:0] re = 170067;
    reg [17:0] mi = 151514;
    reg [17:0] fa = 143265;
    reg [17:0] so = 127550;
    
    wire [17:0] count_until;
    

    assign count_until = select[0] ? doi
                      : (select[1] ? re
                      : (select[2] ? mi
                      : (select[3] ? fa
                      : so)));
    

    reg [17:0] count = 0;
    reg slow_clock = 0;
    
    always @(posedge clk) begin

        count <= (count == count_until) ? 0 : count + 1;
        slow_clock <= (select == 0) ? 1'bz
                                    : ((count == 0) ? ~slow_clock
                                                    : slow_clock);
        
        out = {12{slow_clock}};
    end
endmodule
module square_node_generator(
    input clk,
    input [4:0] select,
    output reg [11:0] out
    );

    

    reg [17:0] doi = 190839;
    reg [17:0] re = 170067;
    reg [17:0] mi = 151514;
    reg [17:0] fa = 143265;
    reg [17:0] so = 127550;
    
    wire [17:0] count_until;
    

    assign count_until = select[0] ? doi
                      : (select[1] ? re
                      : (select[2] ? mi
                      : (select[3] ? fa
                      : so)));
    

    reg [17:0] count = 0;
    reg slow_clock = 0;
    
    always @(posedge clk) begin

        count <= (count == count_until) ? 0 : count + 1;
        slow_clock <= (select == 0) ? 1'bz
                                    : ((count == 0) ? ~slow_clock
                                                    : slow_clock);
        
        out = {12{slow_clock}};
    end
endmodule