data/full_repos/permissive/118895292/peripheral/uart/byte_transmitter.v
 line:1 column:1: Illegal character '\x00'
data/verilator_xmls/8eed54c5-a33a-4946-abec-456969acd8df.xml
module byte_transmitter(
	clk,
	baud_clk,
	byte_to_transmit,
	begin_tx,
	uart_tx_pin);
	



input clk;
input baud_clk;
input [7:0] byte_to_transmit;
input begin_tx;
output reg uart_tx_pin = 0;

reg [3:0] current_state = 0;

always @(posedge clk)
begin
	case (current_state)
	0: begin

		uart_tx_pin <= 1;
		if (begin_tx)
			current_state <= 1;
	end
	1: begin

		uart_tx_pin <= 1;
		if (baud_clk)
			current_state <= 2;
	end
	2: begin

		uart_tx_pin <= 0;
		if (baud_clk)
			current_state <= 3;
	end
	3, 4, 5, 6, 7, 8, 9, 10: begin

		uart_tx_pin <= byte_to_transmit[current_state - 3];
		if (baud_clk)
			current_state <= current_state + 1;
	end
	11: begin

		uart_tx_pin <= 1;
		if (baud_clk)
			current_state <= 0;
	end
	default: begin

		current_state <= 0;
	end
	endcase
end

endmodule
module byte_transmitter(
	clk,
	baud_clk,
	byte_to_transmit,
	begin_tx,
	uart_tx_pin);

	



input clk;
input baud_clk;
input [7:0] byte_to_transmit;
input begin_tx;
output reg uart_tx_pin = 0;

reg [3:0] current_state = 0;

always @(posedge clk)
begin
	case (current_state)
	0: begin

		uart_tx_pin <= 1;
		if (begin_tx)
			current_state <= 1;
	end
	1: begin

		uart_tx_pin <= 1;
		if (baud_clk)
			current_state <= 2;
	end
	2: begin

		uart_tx_pin <= 0;
		if (baud_clk)
			current_state <= 3;
	end
	3, 4, 5, 6, 7, 8, 9, 10: begin

		uart_tx_pin <= byte_to_transmit[current_state - 3];
		if (baud_clk)
			current_state <= current_state + 1;
	end
	11: begin

		uart_tx_pin <= 1;
		if (baud_clk)
			current_state <= 0;
	end
	default: begin

		current_state <= 0;
	end
	endcase
end

endmodule