data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/vector_iir.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/vector_iir.v:93: Cannot find file containing module: \'axis_shift_register\'\n  axis_shift_register #(\n  ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc,data/full_repos/permissive/214858095/axis_shift_register\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc,data/full_repos/permissive/214858095/axis_shift_register.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc,data/full_repos/permissive/214858095/axis_shift_register.sv\n             axis_shift_register\n             axis_shift_register.v\n             axis_shift_register.sv\n             obj_dir/axis_shift_register\n             obj_dir/axis_shift_register.v\n             obj_dir/axis_shift_register.sv\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/vector_iir.v:147: Operator SHIFTL expects 40 bits on the LHS, but LHS\'s VARREF \'ff_prod_i_reg\' generates 31 bits.\n                                                                                                                              : ... In instance vector_iir\n        fb_sum_i_reg <= fb_sum_scaled_i_reg + (ff_prod_i_reg <<< (FB_PROD_W - FF_PROD_W - ACCUM_HEADROOM));\n                                                             ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/vector_iir.v:148: Operator SHIFTL expects 40 bits on the LHS, but LHS\'s VARREF \'ff_prod_q_reg\' generates 31 bits.\n                                                                                                                              : ... In instance vector_iir\n        fb_sum_q_reg <= fb_sum_scaled_q_reg + (ff_prod_q_reg <<< (FB_PROD_W - FF_PROD_W - ACCUM_HEADROOM));\n                                                             ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/vector_iir.v:164: Cannot find file containing module: \'variable_delay_line\'\n  variable_delay_line #(\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/vector_iir.v:176: Cannot find file containing module: \'round\'\n  round #(\n  ^~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/vector_iir.v:181: Cannot find file containing module: \'round\'\n  round #(\n  ^~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module vector_iir #(
  parameter MAX_VECTOR_LEN  = 1023,
  parameter IN_W            = 16,
  parameter OUT_W           = 16,
  parameter ALPHA_W         = 16,
  parameter BETA_W          = 16,
  parameter FEEDBACK_W      = 25,
  parameter ACCUM_HEADROOM  = 4
)(
  input  wire                                clk,
  input  wire                                reset,
  input  wire [$clog2(MAX_VECTOR_LEN+1)-1:0] set_vector_len,
  input  wire [BETA_W-1:0]                   set_beta,
  input  wire [ALPHA_W-1:0]                  set_alpha,
  input  wire [IN_W*2-1:0]                   i_tdata,
  input  wire                                i_tlast,
  input  wire                                i_tvalid,
  output wire                                i_tready,
  output wire [OUT_W*2-1:0]                  o_tdata,
  output wire                                o_tlast,
  output wire                                o_tvalid,
  input  wire                                o_tready
);






  localparam IN_TO_OUT_LATENCY = 4;





  localparam MIN_FB_DELAY = 4;


  reg        [$clog2(MAX_VECTOR_LEN-MIN_FB_DELAY)-1:0] reg_fb_delay;
  reg signed [                             BETA_W-1:0] reg_beta;
  reg signed [                            ALPHA_W-1:0] reg_alpha;

  always @(posedge clk) begin
    reg_fb_delay <= set_vector_len - MIN_FB_DELAY - 1;
    reg_beta     <= set_beta;
    reg_alpha    <= set_alpha;
  end




  wire [(IN_W*2)-1:0]           dsp_data_in;
  reg  [(OUT_W*2)-1:0]          dsp_data_out = 0;
  wire [IN_TO_OUT_LATENCY-1:0]  chain_en;




  axis_shift_register #(
    .WIDTH(IN_W*2), .NSPC(1), .LATENCY(IN_TO_OUT_LATENCY),
    .SIDEBAND_DATAPATH(1), .PIPELINE("NONE")
  ) axis_shreg_i (
    .clk(clk), .reset(reset),
    .s_axis_tdata(i_tdata), .s_axis_tkeep(1'b1), .s_axis_tlast(i_tlast),
    .s_axis_tvalid(i_tvalid), .s_axis_tready(i_tready),
    .m_axis_tdata(o_tdata), .m_axis_tkeep(), .m_axis_tlast(o_tlast),
    .m_axis_tvalid(o_tvalid), .m_axis_tready(o_tready),
    .stage_stb(chain_en), .stage_eop(),
    .m_sideband_data(dsp_data_in), .m_sideband_keep(),
    .s_sideband_data(dsp_data_out)
  );




  localparam FF_PROD_W = IN_W + BETA_W - 1;
  localparam FB_PROD_W = FEEDBACK_W + ALPHA_W - 1;

  reg  signed [IN_W-1:0]        in_i_reg = 0, in_q_reg = 0;
  reg  signed [FF_PROD_W-1:0]   ff_prod_i_reg = 0, ff_prod_q_reg = 0;
  reg  signed [FB_PROD_W-1:0]   fb_sum_i_reg = 0, fb_sum_q_reg = 0;
  wire signed [FB_PROD_W-1:0]   fb_trunc_i, fb_trunc_q;
  wire signed [FEEDBACK_W-1:0]  fb_sum_del_i, fb_sum_del_q;
  reg  signed [FB_PROD_W-1:0]   fb_sum_scaled_i_reg = 0, fb_sum_scaled_q_reg = 0;
  wire signed [OUT_W-1:0]       out_i_rnd, out_q_rnd;

  always @(posedge clk) begin
    if (reset) begin
      {in_i_reg, in_q_reg} <= 0;
      ff_prod_i_reg <= 0;
      ff_prod_q_reg <= 0;
      fb_sum_i_reg <= 0;
      fb_sum_q_reg <= 0;
      fb_sum_scaled_i_reg <= 0;
      fb_sum_scaled_q_reg <= 0;
      dsp_data_out <= 0;
    end else begin
      if (chain_en[0]) begin

        {in_i_reg, in_q_reg} <= dsp_data_in;
      end
      if (chain_en[1]) begin

        ff_prod_i_reg <= in_i_reg * reg_beta;
        ff_prod_q_reg <= in_q_reg * reg_beta;

        fb_sum_scaled_i_reg <= fb_sum_del_i * reg_alpha;
        fb_sum_scaled_q_reg <= fb_sum_del_q * reg_alpha;
      end
      if (chain_en[2]) begin


        fb_sum_i_reg <= fb_sum_scaled_i_reg + (ff_prod_i_reg <<< (FB_PROD_W - FF_PROD_W - ACCUM_HEADROOM));
        fb_sum_q_reg <= fb_sum_scaled_q_reg + (ff_prod_q_reg <<< (FB_PROD_W - FF_PROD_W - ACCUM_HEADROOM));
      end
      if (chain_en[3]) begin

        dsp_data_out <= {out_i_rnd, out_q_rnd};
      end
    end
  end


  assign fb_trunc_i = (fb_sum_i_reg >>> (FB_PROD_W - FEEDBACK_W));
  assign fb_trunc_q = (fb_sum_q_reg >>> (FB_PROD_W - FEEDBACK_W));




  variable_delay_line #(
    .WIDTH(FEEDBACK_W * 2), .DEPTH(MAX_VECTOR_LEN - MIN_FB_DELAY),
    .DYNAMIC_DELAY(1), .DEFAULT_DATA(0), .OUT_REG(1)
  ) delay_line_inst (
    .clk(clk), .clk_en(chain_en[1]), .reset(reset),
    .stb_in(1'b1),
    .data_in({fb_trunc_i[FEEDBACK_W-1:0], fb_trunc_q[FEEDBACK_W-1:0]}),
    .delay(reg_fb_delay),
    .data_out({fb_sum_del_i, fb_sum_del_q})
  );


  round #(
    .bits_in(FB_PROD_W-ACCUM_HEADROOM), .bits_out(OUT_W)
  ) out_round_i_inst (
    .in(fb_sum_i_reg[FB_PROD_W-ACCUM_HEADROOM-1:0]), .out(out_i_rnd), .err()
  );
  round #(
    .bits_in(FB_PROD_W-ACCUM_HEADROOM), .bits_out(OUT_W)
  ) out_round_q_inst (
    .in(fb_sum_q_reg[FB_PROD_W-ACCUM_HEADROOM-1:0]), .out(out_q_rnd), .err()
  );

endmodule
module vector_iir #(
  parameter MAX_VECTOR_LEN  = 1023,
  parameter IN_W            = 16,
  parameter OUT_W           = 16,
  parameter ALPHA_W         = 16,
  parameter BETA_W          = 16,
  parameter FEEDBACK_W      = 25,
  parameter ACCUM_HEADROOM  = 4
)(
  input  wire                                clk,
  input  wire                                reset,
  input  wire [$clog2(MAX_VECTOR_LEN+1)-1:0] set_vector_len,
  input  wire [BETA_W-1:0]                   set_beta,
  input  wire [ALPHA_W-1:0]                  set_alpha,
  input  wire [IN_W*2-1:0]                   i_tdata,
  input  wire                                i_tlast,
  input  wire                                i_tvalid,
  output wire                                i_tready,
  output wire [OUT_W*2-1:0]                  o_tdata,
  output wire                                o_tlast,
  output wire                                o_tvalid,
  input  wire                                o_tready
);







  localparam IN_TO_OUT_LATENCY = 4;





  localparam MIN_FB_DELAY = 4;


  reg        [$clog2(MAX_VECTOR_LEN-MIN_FB_DELAY)-1:0] reg_fb_delay;
  reg signed [                             BETA_W-1:0] reg_beta;
  reg signed [                            ALPHA_W-1:0] reg_alpha;

  always @(posedge clk) begin
    reg_fb_delay <= set_vector_len - MIN_FB_DELAY - 1;
    reg_beta     <= set_beta;
    reg_alpha    <= set_alpha;
  end




  wire [(IN_W*2)-1:0]           dsp_data_in;
  reg  [(OUT_W*2)-1:0]          dsp_data_out = 0;
  wire [IN_TO_OUT_LATENCY-1:0]  chain_en;




  axis_shift_register #(
    .WIDTH(IN_W*2), .NSPC(1), .LATENCY(IN_TO_OUT_LATENCY),
    .SIDEBAND_DATAPATH(1), .PIPELINE("NONE")
  ) axis_shreg_i (
    .clk(clk), .reset(reset),
    .s_axis_tdata(i_tdata), .s_axis_tkeep(1'b1), .s_axis_tlast(i_tlast),
    .s_axis_tvalid(i_tvalid), .s_axis_tready(i_tready),
    .m_axis_tdata(o_tdata), .m_axis_tkeep(), .m_axis_tlast(o_tlast),
    .m_axis_tvalid(o_tvalid), .m_axis_tready(o_tready),
    .stage_stb(chain_en), .stage_eop(),
    .m_sideband_data(dsp_data_in), .m_sideband_keep(),
    .s_sideband_data(dsp_data_out)
  );




  localparam FF_PROD_W = IN_W + BETA_W - 1;
  localparam FB_PROD_W = FEEDBACK_W + ALPHA_W - 1;

  reg  signed [IN_W-1:0]        in_i_reg = 0, in_q_reg = 0;
  reg  signed [FF_PROD_W-1:0]   ff_prod_i_reg = 0, ff_prod_q_reg = 0;
  reg  signed [FB_PROD_W-1:0]   fb_sum_i_reg = 0, fb_sum_q_reg = 0;
  wire signed [FB_PROD_W-1:0]   fb_trunc_i, fb_trunc_q;
  wire signed [FEEDBACK_W-1:0]  fb_sum_del_i, fb_sum_del_q;
  reg  signed [FB_PROD_W-1:0]   fb_sum_scaled_i_reg = 0, fb_sum_scaled_q_reg = 0;
  wire signed [OUT_W-1:0]       out_i_rnd, out_q_rnd;

  always @(posedge clk) begin
    if (reset) begin
      {in_i_reg, in_q_reg} <= 0;
      ff_prod_i_reg <= 0;
      ff_prod_q_reg <= 0;
      fb_sum_i_reg <= 0;
      fb_sum_q_reg <= 0;
      fb_sum_scaled_i_reg <= 0;
      fb_sum_scaled_q_reg <= 0;
      dsp_data_out <= 0;
    end else begin
      if (chain_en[0]) begin

        {in_i_reg, in_q_reg} <= dsp_data_in;
      end
      if (chain_en[1]) begin

        ff_prod_i_reg <= in_i_reg * reg_beta;
        ff_prod_q_reg <= in_q_reg * reg_beta;

        fb_sum_scaled_i_reg <= fb_sum_del_i * reg_alpha;
        fb_sum_scaled_q_reg <= fb_sum_del_q * reg_alpha;
      end
      if (chain_en[2]) begin


        fb_sum_i_reg <= fb_sum_scaled_i_reg + (ff_prod_i_reg <<< (FB_PROD_W - FF_PROD_W - ACCUM_HEADROOM));
        fb_sum_q_reg <= fb_sum_scaled_q_reg + (ff_prod_q_reg <<< (FB_PROD_W - FF_PROD_W - ACCUM_HEADROOM));
      end
      if (chain_en[3]) begin

        dsp_data_out <= {out_i_rnd, out_q_rnd};
      end
    end
  end


  assign fb_trunc_i = (fb_sum_i_reg >>> (FB_PROD_W - FEEDBACK_W));
  assign fb_trunc_q = (fb_sum_q_reg >>> (FB_PROD_W - FEEDBACK_W));




  variable_delay_line #(
    .WIDTH(FEEDBACK_W * 2), .DEPTH(MAX_VECTOR_LEN - MIN_FB_DELAY),
    .DYNAMIC_DELAY(1), .DEFAULT_DATA(0), .OUT_REG(1)
  ) delay_line_inst (
    .clk(clk), .clk_en(chain_en[1]), .reset(reset),
    .stb_in(1'b1),
    .data_in({fb_trunc_i[FEEDBACK_W-1:0], fb_trunc_q[FEEDBACK_W-1:0]}),
    .delay(reg_fb_delay),
    .data_out({fb_sum_del_i, fb_sum_del_q})
  );


  round #(
    .bits_in(FB_PROD_W-ACCUM_HEADROOM), .bits_out(OUT_W)
  ) out_round_i_inst (
    .in(fb_sum_i_reg[FB_PROD_W-ACCUM_HEADROOM-1:0]), .out(out_i_rnd), .err()
  );
  round #(
    .bits_in(FB_PROD_W-ACCUM_HEADROOM), .bits_out(OUT_W)
  ) out_round_q_inst (
    .in(fb_sum_q_reg[FB_PROD_W-ACCUM_HEADROOM-1:0]), .out(out_q_rnd), .err()
  );

endmodule