data/full_repos/permissive/161526648/pipeline.v
1: b"%Error: data/full_repos/permissive/161526648/pipeline.v:76: Cannot find file containing module: 'mux2_1'\n mux2_1 mux_pc2(NextPC_if,targetPC,CHmux,targetPC1);\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161526648,data/full_repos/permissive/161526648/mux2_1\n             data/full_repos/permissive/161526648,data/full_repos/permissive/161526648/mux2_1.v\n             data/full_repos/permissive/161526648,data/full_repos/permissive/161526648/mux2_1.sv\n             mux2_1\n             mux2_1.v\n             mux2_1.sv\n             obj_dir/mux2_1\n             obj_dir/mux2_1.v\n             obj_dir/mux2_1.sv\n%Error: data/full_repos/permissive/161526648/pipeline.v:77: Cannot find file containing module: 'mux2_1'\n mux2_1 mux_pc1(targetPC1,PC_if,PCWrite,targetPC2);\n ^~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:78: Cannot find file containing module: 'pc'\n pc PC_counter(targetPC2,reset,clock,PC_if);\n ^~\n%Error: data/full_repos/permissive/161526648/pipeline.v:79: Cannot find file containing module: 'InstructionMemory'\n InstructionMemory IM(PC_if,Instruction_if);\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:80: Cannot find file containing module: 'mux2_1'\n mux2_1 mux_Ins(Instruction_if,Instruction_id,IFIDWrite,Instruction_temp);\n ^~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:81: Cannot find file containing module: 'Adder_32b'\n Adder_32b adder1(PC_if,4,NextPC_if);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:82: Cannot find file containing module: 'mux2_1'\n mux2_1 mux_Next(NextPC_if,NextPC_id,IFIDWrite,NextPC_temp);\n ^~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:85: Cannot find file containing module: 'IF_ID'\n IF_ID II(clock,reset,IFFlush,NextPC_temp,Instruction_temp,Instruction_id,NextPC_id);\n ^~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:86: Cannot find file containing module: 'Hazard_Detection'\n Hazard_Detection HD(rt_ex,Instruction_id[25:21],Instruction_id[20:16],MemRead_ex,IDFlush,PCWrite,IFIDWrite);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:87: Cannot find file containing module: 'control'\n control controlUnit(Instruction_id[31:26],RegDst,Jump,Branch,bne,MemRead,MemtoReg,ALUop,MemWrite,ALUSrc,RegWrite);\n ^~~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:88: Cannot find file containing module: 'RegFile'\n RegFile RF(clock,Instruction_id[25:21],Instruction_id[20:16],WriteReg_wb,WriteData,RegWrite_wb,ReadData1,ReadData2);\n ^~~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:89: Cannot find file containing module: 'signExtension'\n signExtension ImExtend(Instruction_id[15:0],extendedIm);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:92: Cannot find file containing module: 'mux2_1'\n mux2_1 mux_Branch_Jump(BranchAddr,JumpAddress,Jump,targetPC);\n ^~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:93: Cannot find file containing module: 'Control_Hazard'\n Control_Hazard CH(Jump,Branch,bne,WriteReg,WriteReg_mem,MemRead_ex,MemRead_mem,RegWrite_ex,RegWrite_mem,Instruction_id,ReadData1,ReadData2,ReadData,ALUresult,ALUresult_mem,CHmux,IFFlush);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:97: Cannot find file containing module: 'ID_EX'\n ID_EX IE(clock,reset,IDFlush,Instruction_id,ReadData1,ReadData2,extendedIm,RegDst,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite,ALUop,RegDst_ex,MemRead_ex,MemtoReg_ex,MemWrite_ex,ALUSrc_ex,RegWrite_ex,ALUop_ex,Instuction_ex,ReadData1_ex,ReadData2_ex,Extended_ex,rt_ex,rs_ex,rd_ex);\n ^~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:98: Cannot find file containing module: 'ALUcontrol'\n ALUcontrol alu_control(Extended_ex[5:0],ALUop_ex,aluControl);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:100: Cannot find file containing module: 'mux3_1'\n mux3_1 mux_alu3_rs(ReadData1_ex,WriteData,ALUresult_mem,forward1,ALUsrc1);\n ^~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:102: Cannot find file containing module: 'mux3_1'\n mux3_1 mux_alu3_rt(ReadData2_ex,WriteData,ALUresult_mem,forward2,ReadData2_temp);\n ^~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:104: Cannot find file containing module: 'mux2_1'\n mux2_1 mux_alu(ReadData2_temp,Extended_ex,ALUSrc_ex,ALUsrc2);\n ^~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:106: Cannot find file containing module: 'mux5bit'\n mux5bit mux_writeReg(rt_ex,rd_ex,RegDst_ex,WriteReg);\n ^~~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:108: Cannot find file containing module: 'ALU'\n ALU alu_1(ALUsrc1,ALUsrc2,aluControl,ALUresult);\n ^~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:110: Cannot find file containing module: 'ForwardUnit'\n ForwardUnit FU(rt_ex,rs_ex,WriteReg_mem,WriteReg_wb,RegWrite_mem,RegWrite_wb,forward1,forward2);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:113: Cannot find file containing module: 'EX_MEM'\n EX_MEM EM(clock,reset,MemRead_ex,MemtoReg_ex,MemWrite_ex,RegWrite_ex,ALUresult,ReadData2_temp,WriteReg,MemRead_mem,MemtoReg_mem,MemWrite_mem,RegWrite_mem,ALUresult_mem,ReadData2_mem,WriteReg_mem);\n ^~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:115: Cannot find file containing module: 'DataMem'\n DataMem DM(clock,ALUresult_mem,ReadData2_mem,MemWrite_mem,MemRead_mem,ReadData);\n ^~~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:118: Cannot find file containing module: 'MEM_WB'\n MEM_WB MW(clock,reset,MemtoReg_mem,RegWrite_mem,ALUresult_mem,ReadData,WriteReg_mem,MemtoReg_wb,RegWrite_wb,ALUresult_wb,WriteReg_wb,ReadData_wb);\n ^~~~~~\n%Error: data/full_repos/permissive/161526648/pipeline.v:120: Cannot find file containing module: 'mux2_1'\n mux2_1 mux_writeback(ALUresult_wb,ReadData_wb,MemtoReg_wb,WriteData);\n ^~~~~~\n%Error: Exiting due to 26 error(s)\n"
module pipeline(clock,reset);
	input clock;
	input reset;

	wire [31:0]PC_if;
	wire RegDst,Jump,Branch,bne,MemRead,MemtoReg,ALUop,MemWrite,ALUSrc,RegWrite;
	wire IFIDWrite,PCWrite,IDFlush;
	wire [31:0]ReadData1;
	wire [31:0]ReadData2;
	wire [31:0]ReadData;

	wire [31:0]WriteData;
	wire [31:0]extendedIm;
	wire [31:0]ALUsrc2,ALUsrc1;
	wire [3:0]aluControl;
	wire [31:0]ALUresult;
	wire [4:0] WriteReg;
	wire [31:0]targetPC1,targetPC2;
	wire [31:0]targetPC;
	wire [31:0] ReadData2_temp;


	wire[31:0] NextPC_if;
	wire[31:0] Instruction_if;
	

	wire[31:0] NextPC_id;
	wire[31:0] Instruction_id;
	wire[31:0] NextPC_temp;


	wire RegDst_ex,MemRead_ex,MemtoReg_ex,MemWrite_ex,ALUSrc_ex,RegWrite_ex;
	wire[1:0] ALUop_ex;
	wire[31:0] Instuction_ex;
	wire[31:0] ReadData1_ex;
	wire[31:0] ReadData2_ex;
	wire[31:0] Extended_ex;
	wire[4:0] rs_ex;
	wire[4:0] rt_ex;
	wire[4:0] rd_ex;
	wire[1:0] forward1,forward2;


	wire MemRead_mem,MemtoReg_mem,MemWrite_mem,RegWrite_mem;
	wire[31:0] ALUresult_mem;
	wire[31:0] ReadData2_mem;
	wire[4:0] WriteReg_mem;


	wire MemtoReg_wb,RegWrite_wb;
	wire[31:0] ALUresult_wb;
	wire[4:0] WriteReg_wb;
	wire[31:0] ReadData_wb;

	mux2_1 mux_pc2(NextPC_if,targetPC,CHmux,targetPC1);
	mux2_1 mux_pc1(targetPC1,PC_if,PCWrite,targetPC2);
	pc PC_counter(targetPC2,reset,clock,PC_if);
	InstructionMemory IM(PC_if,Instruction_if);
	mux2_1 mux_Ins(Instruction_if,Instruction_id,IFIDWrite,Instruction_temp);
	Adder_32b adder1(PC_if,4,NextPC_if);
	mux2_1 mux_Next(NextPC_if,NextPC_id,IFIDWrite,NextPC_temp);


	IF_ID II(clock,reset,IFFlush,NextPC_temp,Instruction_temp,Instruction_id,NextPC_id);
	Hazard_Detection HD(rt_ex,Instruction_id[25:21],Instruction_id[20:16],MemRead_ex,IDFlush,PCWrite,IFIDWrite);
	control controlUnit(Instruction_id[31:26],RegDst,Jump,Branch,bne,MemRead,MemtoReg,ALUop,MemWrite,ALUSrc,RegWrite);
	RegFile RF(clock,Instruction_id[25:21],Instruction_id[20:16],WriteReg_wb,WriteData,RegWrite_wb,ReadData1,ReadData2);
	signExtension ImExtend(Instruction_id[15:0],extendedIm);
	wire [31:0] JumpAddress = {NextPC_id[31:28],Instruction_id[25:0],2'b00};
	wire [31:0] BranchAddr = NextPC_id + extendedIm*4;
	mux2_1 mux_Branch_Jump(BranchAddr,JumpAddress,Jump,targetPC);
	Control_Hazard CH(Jump,Branch,bne,WriteReg,WriteReg_mem,MemRead_ex,MemRead_mem,RegWrite_ex,RegWrite_mem,Instruction_id,ReadData1,ReadData2,ReadData,ALUresult,ALUresult_mem,CHmux,IFFlush);



	ID_EX IE(clock,reset,IDFlush,Instruction_id,ReadData1,ReadData2,extendedIm,RegDst,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite,ALUop,RegDst_ex,MemRead_ex,MemtoReg_ex,MemWrite_ex,ALUSrc_ex,RegWrite_ex,ALUop_ex,Instuction_ex,ReadData1_ex,ReadData2_ex,Extended_ex,rt_ex,rs_ex,rd_ex);
	ALUcontrol alu_control(Extended_ex[5:0],ALUop_ex,aluControl);
	
	mux3_1 mux_alu3_rs(ReadData1_ex,WriteData,ALUresult_mem,forward1,ALUsrc1);
	
	mux3_1 mux_alu3_rt(ReadData2_ex,WriteData,ALUresult_mem,forward2,ReadData2_temp);
	
	mux2_1 mux_alu(ReadData2_temp,Extended_ex,ALUSrc_ex,ALUsrc2);

	mux5bit mux_writeReg(rt_ex,rd_ex,RegDst_ex,WriteReg);
	
	ALU alu_1(ALUsrc1,ALUsrc2,aluControl,ALUresult);
	
	ForwardUnit FU(rt_ex,rs_ex,WriteReg_mem,WriteReg_wb,RegWrite_mem,RegWrite_wb,forward1,forward2);


	EX_MEM EM(clock,reset,MemRead_ex,MemtoReg_ex,MemWrite_ex,RegWrite_ex,ALUresult,ReadData2_temp,WriteReg,MemRead_mem,MemtoReg_mem,MemWrite_mem,RegWrite_mem,ALUresult_mem,ReadData2_mem,WriteReg_mem);
	
	DataMem DM(clock,ALUresult_mem,ReadData2_mem,MemWrite_mem,MemRead_mem,ReadData);


	MEM_WB MW(clock,reset,MemtoReg_mem,RegWrite_mem,ALUresult_mem,ReadData,WriteReg_mem,MemtoReg_wb,RegWrite_wb,ALUresult_wb,WriteReg_wb,ReadData_wb);
	
	mux2_1 mux_writeback(ALUresult_wb,ReadData_wb,MemtoReg_wb,WriteData);
	
endmodule
module pipeline(clock,reset);

	input clock;
	input reset;

	wire [31:0]PC_if;
	wire RegDst,Jump,Branch,bne,MemRead,MemtoReg,ALUop,MemWrite,ALUSrc,RegWrite;
	wire IFIDWrite,PCWrite,IDFlush;
	wire [31:0]ReadData1;
	wire [31:0]ReadData2;
	wire [31:0]ReadData;

	wire [31:0]WriteData;
	wire [31:0]extendedIm;
	wire [31:0]ALUsrc2,ALUsrc1;
	wire [3:0]aluControl;
	wire [31:0]ALUresult;
	wire [4:0] WriteReg;
	wire [31:0]targetPC1,targetPC2;
	wire [31:0]targetPC;
	wire [31:0] ReadData2_temp;


	wire[31:0] NextPC_if;
	wire[31:0] Instruction_if;
	

	wire[31:0] NextPC_id;
	wire[31:0] Instruction_id;
	wire[31:0] NextPC_temp;


	wire RegDst_ex,MemRead_ex,MemtoReg_ex,MemWrite_ex,ALUSrc_ex,RegWrite_ex;
	wire[1:0] ALUop_ex;
	wire[31:0] Instuction_ex;
	wire[31:0] ReadData1_ex;
	wire[31:0] ReadData2_ex;
	wire[31:0] Extended_ex;
	wire[4:0] rs_ex;
	wire[4:0] rt_ex;
	wire[4:0] rd_ex;
	wire[1:0] forward1,forward2;


	wire MemRead_mem,MemtoReg_mem,MemWrite_mem,RegWrite_mem;
	wire[31:0] ALUresult_mem;
	wire[31:0] ReadData2_mem;
	wire[4:0] WriteReg_mem;


	wire MemtoReg_wb,RegWrite_wb;
	wire[31:0] ALUresult_wb;
	wire[4:0] WriteReg_wb;
	wire[31:0] ReadData_wb;

	mux2_1 mux_pc2(NextPC_if,targetPC,CHmux,targetPC1);
	mux2_1 mux_pc1(targetPC1,PC_if,PCWrite,targetPC2);
	pc PC_counter(targetPC2,reset,clock,PC_if);
	InstructionMemory IM(PC_if,Instruction_if);
	mux2_1 mux_Ins(Instruction_if,Instruction_id,IFIDWrite,Instruction_temp);
	Adder_32b adder1(PC_if,4,NextPC_if);
	mux2_1 mux_Next(NextPC_if,NextPC_id,IFIDWrite,NextPC_temp);


	IF_ID II(clock,reset,IFFlush,NextPC_temp,Instruction_temp,Instruction_id,NextPC_id);
	Hazard_Detection HD(rt_ex,Instruction_id[25:21],Instruction_id[20:16],MemRead_ex,IDFlush,PCWrite,IFIDWrite);
	control controlUnit(Instruction_id[31:26],RegDst,Jump,Branch,bne,MemRead,MemtoReg,ALUop,MemWrite,ALUSrc,RegWrite);
	RegFile RF(clock,Instruction_id[25:21],Instruction_id[20:16],WriteReg_wb,WriteData,RegWrite_wb,ReadData1,ReadData2);
	signExtension ImExtend(Instruction_id[15:0],extendedIm);
	wire [31:0] JumpAddress = {NextPC_id[31:28],Instruction_id[25:0],2'b00};
	wire [31:0] BranchAddr = NextPC_id + extendedIm*4;
	mux2_1 mux_Branch_Jump(BranchAddr,JumpAddress,Jump,targetPC);
	Control_Hazard CH(Jump,Branch,bne,WriteReg,WriteReg_mem,MemRead_ex,MemRead_mem,RegWrite_ex,RegWrite_mem,Instruction_id,ReadData1,ReadData2,ReadData,ALUresult,ALUresult_mem,CHmux,IFFlush);



	ID_EX IE(clock,reset,IDFlush,Instruction_id,ReadData1,ReadData2,extendedIm,RegDst,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite,ALUop,RegDst_ex,MemRead_ex,MemtoReg_ex,MemWrite_ex,ALUSrc_ex,RegWrite_ex,ALUop_ex,Instuction_ex,ReadData1_ex,ReadData2_ex,Extended_ex,rt_ex,rs_ex,rd_ex);
	ALUcontrol alu_control(Extended_ex[5:0],ALUop_ex,aluControl);
	
	mux3_1 mux_alu3_rs(ReadData1_ex,WriteData,ALUresult_mem,forward1,ALUsrc1);
	
	mux3_1 mux_alu3_rt(ReadData2_ex,WriteData,ALUresult_mem,forward2,ReadData2_temp);
	
	mux2_1 mux_alu(ReadData2_temp,Extended_ex,ALUSrc_ex,ALUsrc2);

	mux5bit mux_writeReg(rt_ex,rd_ex,RegDst_ex,WriteReg);
	
	ALU alu_1(ALUsrc1,ALUsrc2,aluControl,ALUresult);
	
	ForwardUnit FU(rt_ex,rs_ex,WriteReg_mem,WriteReg_wb,RegWrite_mem,RegWrite_wb,forward1,forward2);


	EX_MEM EM(clock,reset,MemRead_ex,MemtoReg_ex,MemWrite_ex,RegWrite_ex,ALUresult,ReadData2_temp,WriteReg,MemRead_mem,MemtoReg_mem,MemWrite_mem,RegWrite_mem,ALUresult_mem,ReadData2_mem,WriteReg_mem);
	
	DataMem DM(clock,ALUresult_mem,ReadData2_mem,MemWrite_mem,MemRead_mem,ReadData);


	MEM_WB MW(clock,reset,MemtoReg_mem,RegWrite_mem,ALUresult_mem,ReadData,WriteReg_mem,MemtoReg_wb,RegWrite_wb,ALUresult_wb,WriteReg_wb,ReadData_wb);
	
	mux2_1 mux_writeback(ALUresult_wb,ReadData_wb,MemtoReg_wb,WriteData);
	
endmodule