data/full_repos/permissive/168753118/testbench/modules/PREDICTOR/PREDICTOR_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/168753118/testbench/modules/PREDICTOR/PREDICTOR_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n    #period;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/168753118/testbench/modules/PREDICTOR/PREDICTOR_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Error: data/full_repos/permissive/168753118/testbench/modules/PREDICTOR/PREDICTOR_tb.v:159: syntax error, unexpected \'@\'\n   @eachvec;\n   ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PREDICTOR_tb;


	parameter XLEN = 32;


	reg eachvec;


	reg predictor_clock_in;
  reg predictor_reset_in;
	reg [XLEN-1:0] predictor_pred_addr_in;
  reg predictor_feedback_result_in;
  reg predictor_feedback_write_enable_in;
  reg [XLEN-1:0] predictor_feedback_addr_in;
  reg [XLEN-1:0] predictor_feedback_return_in;


	reg predictor_pred_enable_golden;
  reg [XLEN-1:0] predictor_pred_addr_golden;


	reg predictor_pred_enable_result;
  reg predictor_pred_addr_result;


  wire predictor_pred_enable_out;
	wire [XLEN-1:0] predictor_pred_addr_out;


	localparam period = 5;


	integer golden, inputs, results, status;


	PREDICTOR predictor0 (
    .predictor_clock_in(predictor_clock_in),
    .predictor_reset_in(predictor_reset_in),
    .predictor_pred_addr_in(predictor_pred_addr_in),
    .predictor_pred_enable_out(predictor_pred_enable_out),
    .predictor_pred_addr_out(predictor_pred_addr_out),
    .predictor_feedback_result_in(predictor_feedback_result_in),
    .predictor_feedback_write_enable_in(predictor_feedback_write_enable_in),
    .predictor_feedback_addr_in(predictor_feedback_addr_in),
    .predictor_feedback_return_in(predictor_feedback_return_in)
	);


	initial begin


			$display("Opening golden file");
			golden = $fopen("./out/PREDICTOR_outputs.txt", "r");


			$display("Opening inputs file");
			inputs = $fopen("./out/PREDICTOR_inputs.txt", "r");


			$display("Opening results file");
			results = $fopen("./out/PREDICTOR_results.txt", "w");


			if (golden == `NULL) begin
				$display("Golden file was NULL");
				$finish;
			end


			if(inputs == `NULL) begin
				$display("Inputs file was NULL");
			end


			if(results == `NULL) begin
				$display("Results file was NULL");
			end


      predictor_clock_in = 1'b1;


			while(!$feof(inputs)) begin


				status = $fscanf(
					inputs,
					"%d %d %d %d %d %d",
					predictor_reset_in,
          predictor_pred_addr_in,
          predictor_feedback_result_in,
          predictor_feedback_write_enable_in,
          predictor_feedback_addr_in,
          predictor_feedback_return_in
				);


				status = $fscanf(
					golden,
					"%d %d",
					predictor_pred_enable_golden,
          predictor_pred_addr_golden
				);


				#period;

        predictor_clock_in = ~predictor_clock_in;


				if (predictor_pred_enable_out == predictor_pred_enable_golden)
					predictor_pred_enable_result = 1'b1;
				else
					predictor_pred_enable_result = 1'b0;

        if (predictor_pred_addr_out == predictor_pred_addr_golden)
					predictor_pred_addr_result = 1'b1;
				else
					predictor_pred_addr_result = 1'b0;

        if (!predictor_pred_enable_result | !predictor_pred_addr_result) begin
          $display("========================");
          $display("%d, %d", predictor_pred_enable_out, predictor_pred_addr_out);
          $display("%d, %d", predictor_pred_enable_golden, predictor_pred_addr_golden);
        end

        #period;

        predictor_clock_in = ~predictor_clock_in;


				$fwrite(
					results,
					"%d %d\n",
					predictor_pred_enable_result,
          predictor_pred_addr_result
				);

			end

			$display("Simulation has ended");

			$fclose(golden);
			$fclose(inputs);
			$fclose(results);

			@eachvec;
			$finish;

		end
endmodule
module PREDICTOR_tb;



	parameter XLEN = 32;


	reg eachvec;


	reg predictor_clock_in;
  reg predictor_reset_in;
	reg [XLEN-1:0] predictor_pred_addr_in;
  reg predictor_feedback_result_in;
  reg predictor_feedback_write_enable_in;
  reg [XLEN-1:0] predictor_feedback_addr_in;
  reg [XLEN-1:0] predictor_feedback_return_in;


	reg predictor_pred_enable_golden;
  reg [XLEN-1:0] predictor_pred_addr_golden;


	reg predictor_pred_enable_result;
  reg predictor_pred_addr_result;


  wire predictor_pred_enable_out;
	wire [XLEN-1:0] predictor_pred_addr_out;


	localparam period = 5;


	integer golden, inputs, results, status;


	PREDICTOR predictor0 (
    .predictor_clock_in(predictor_clock_in),
    .predictor_reset_in(predictor_reset_in),
    .predictor_pred_addr_in(predictor_pred_addr_in),
    .predictor_pred_enable_out(predictor_pred_enable_out),
    .predictor_pred_addr_out(predictor_pred_addr_out),
    .predictor_feedback_result_in(predictor_feedback_result_in),
    .predictor_feedback_write_enable_in(predictor_feedback_write_enable_in),
    .predictor_feedback_addr_in(predictor_feedback_addr_in),
    .predictor_feedback_return_in(predictor_feedback_return_in)
	);


	initial begin


			$display("Opening golden file");
			golden = $fopen("./out/PREDICTOR_outputs.txt", "r");


			$display("Opening inputs file");
			inputs = $fopen("./out/PREDICTOR_inputs.txt", "r");


			$display("Opening results file");
			results = $fopen("./out/PREDICTOR_results.txt", "w");


			if (golden == `NULL) begin
				$display("Golden file was NULL");
				$finish;
			end


			if(inputs == `NULL) begin
				$display("Inputs file was NULL");
			end


			if(results == `NULL) begin
				$display("Results file was NULL");
			end


      predictor_clock_in = 1'b1;


			while(!$feof(inputs)) begin


				status = $fscanf(
					inputs,
					"%d %d %d %d %d %d",
					predictor_reset_in,
          predictor_pred_addr_in,
          predictor_feedback_result_in,
          predictor_feedback_write_enable_in,
          predictor_feedback_addr_in,
          predictor_feedback_return_in
				);


				status = $fscanf(
					golden,
					"%d %d",
					predictor_pred_enable_golden,
          predictor_pred_addr_golden
				);


				#period;

        predictor_clock_in = ~predictor_clock_in;


				if (predictor_pred_enable_out == predictor_pred_enable_golden)
					predictor_pred_enable_result = 1'b1;
				else
					predictor_pred_enable_result = 1'b0;

        if (predictor_pred_addr_out == predictor_pred_addr_golden)
					predictor_pred_addr_result = 1'b1;
				else
					predictor_pred_addr_result = 1'b0;

        if (!predictor_pred_enable_result | !predictor_pred_addr_result) begin
          $display("========================");
          $display("%d, %d", predictor_pred_enable_out, predictor_pred_addr_out);
          $display("%d, %d", predictor_pred_enable_golden, predictor_pred_addr_golden);
        end

        #period;

        predictor_clock_in = ~predictor_clock_in;


				$fwrite(
					results,
					"%d %d\n",
					predictor_pred_enable_result,
          predictor_pred_addr_result
				);

			end

			$display("Simulation has ended");

			$fclose(golden);
			$fclose(inputs);
			$fclose(results);

			@eachvec;
			$finish;

		end
endmodule