data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_data_tb.v
 line:29: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_data_tb.v:5: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clock <= ~clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_data_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("iobstb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_data_tb.v:19: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_data_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #19\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_data_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/ddrmem/iobs_data_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iobs_data_tb;

reg	clock	= 1;
always	#5	clock	<= ~clock;

reg	capture	= 0;
reg	send	= 0;

reg	[31:0]	data_to;
wire	[31:0]	data_from;

wire	[15:0]	dq_iobs;


initial begin : Sim
	$write ("%% ");
	$dumpfile ("iobstb.vcd");
	$dumpvars;
	
	#19
	data_to	<= 32'hFFAA_0033;
	send	<= 1;
	
	#10
	send	<= 0;
	
	#100
	$finish;
end


iobs_data DATAIOBS (
	.clock_i	(clock),
	
	.send_i		(send),
	.capture_i	({capture, capture}),
	.data_i		(data_to),
	.data_o		(data_from),
	
	.ddr_dq_io	(dq_iobs)
);


endmodule
module iobs_data_tb;


reg	clock	= 1;
always	#5	clock	<= ~clock;

reg	capture	= 0;
reg	send	= 0;

reg	[31:0]	data_to;
wire	[31:0]	data_from;

wire	[15:0]	dq_iobs;


initial begin : Sim
	$write ("%% ");
	$dumpfile ("iobstb.vcd");
	$dumpvars;
	
	#19
	data_to	<= 32'hFFAA_0033;
	send	<= 1;
	
	#10
	send	<= 0;
	
	#100
	$finish;
end


iobs_data DATAIOBS (
	.clock_i	(clock),
	
	.send_i		(send),
	.capture_i	({capture, capture}),
	.data_i		(data_to),
	.data_o		(data_from),
	
	.ddr_dq_io	(dq_iobs)
);


endmodule