data/full_repos/permissive/114553631/test/test_D_reg.v
 line:79: before: "$"
1: b'%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:6: Cannot find include file: ../src/def.v\n`include "../src/def.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/def.v\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/def.v.v\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/def.v.sv\n             ../src/def.v\n             ../src/def.v.v\n             ../src/def.v.sv\n             obj_dir/../src/def.v\n             obj_dir/../src/def.v.v\n             obj_dir/../src/def.v.sv\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:8: Cannot find include file: ../src/D_reg.v\n`include "../src/D_reg.v" \n         ^~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:30: Unsupported: Ignoring delay on this delayed statement.\n    initial #stop_time $finish;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:34: Define or directive not defined: \'`IROP\'\n        f_op = `IROP;\n               ^~~~~\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:34: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        f_op = `IROP;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:42: Define or directive not defined: \'`IROP\'\n        f_op = `IROP;\n               ^~~~~\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        f_op = `IROP;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:52: Define or directive not defined: \'`IORI\'\n        f_op = `IORI;\n               ^~~~~\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:52: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        f_op = `IORI;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:66: Unsupported: Ignoring delay on this delayed statement.\n            #10 clk = ~clk;\n            ^\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:70: Unsupported or unknown PLI call: $monitor\n       $monitor("time = ", $time, " op=%b func=%b rs=%d rt=%d rd=%d valC=%d", D_op, D_func, D_rs, D_rt, D_rd, D_valC);\n       ^~~~~~~~\n%Error: Exiting due to 9 error(s), 8 warning(s)\n'
module test_D_reg;
    reg clk = 0;
    reg D_stall = 0;
    reg [5:0] f_op = 0;
    reg [5:0] f_func = 0;
    reg [4:0] f_rs = 0;
    reg [4:0] f_rt = 0;
    reg [4:0] f_rd = 0;
    reg [31:0] f_valC = 0;
    wire [5:0] D_op;
    wire [5:0] D_func;
    wire [4:0] D_rs;
    wire [4:0] D_rt;
    wire [4:0] D_rd;
    wire [31:0] D_valC;

    parameter stop_time = 100;

    D_reg DREG(D_op, D_func, D_rs, D_rt, D_rd, D_valC, clk, D_stall, f_op, f_func, f_rs, f_rd, f_rt, f_valC);

    initial #stop_time $finish;

    initial begin
        #10;
        f_op = `IROP;
        f_func = 6'b100111;
        f_rs = 5'b10011;
        f_rt = 5'b11110;
        f_rd = 5'b11101;
        f_valC = 66;
        #20;
        D_stall = 1;
        f_op = `IROP;
        f_func = 6'b100100;
        f_rs = 5'b10010;
        f_rt = 5'b10110;
        f_rd = 5'b10101;
        f_valC = 77;
        #20;
        D_stall = 0;
        #20;
        D_stall = 0;        
        f_op = `IORI;
        f_func = 6'b100000;
        f_rs = 5'b10111;
        f_rt = 5'b10000;
        f_rd = 5'b10100;
        f_valC = 88;
        #20;
        D_stall = 1;
        f_valC = 99;
        #20;
    end

    initial begin
        repeat(10)
            #10 clk = ~clk;
    end

    initial begin
      	$monitor("time = ", $time, " op=%b func=%b rs=%d rt=%d rd=%d valC=%d", D_op, D_func, D_rs, D_rt, D_rd, D_valC);
    end

endmodule
module test_D_reg;

    reg clk = 0;
    reg D_stall = 0;
    reg [5:0] f_op = 0;
    reg [5:0] f_func = 0;
    reg [4:0] f_rs = 0;
    reg [4:0] f_rt = 0;
    reg [4:0] f_rd = 0;
    reg [31:0] f_valC = 0;
    wire [5:0] D_op;
    wire [5:0] D_func;
    wire [4:0] D_rs;
    wire [4:0] D_rt;
    wire [4:0] D_rd;
    wire [31:0] D_valC;

    parameter stop_time = 100;

    D_reg DREG(D_op, D_func, D_rs, D_rt, D_rd, D_valC, clk, D_stall, f_op, f_func, f_rs, f_rd, f_rt, f_valC);

    initial #stop_time $finish;

    initial begin
        #10;
        f_op = `IROP;
        f_func = 6'b100111;
        f_rs = 5'b10011;
        f_rt = 5'b11110;
        f_rd = 5'b11101;
        f_valC = 66;
        #20;
        D_stall = 1;
        f_op = `IROP;
        f_func = 6'b100100;
        f_rs = 5'b10010;
        f_rt = 5'b10110;
        f_rd = 5'b10101;
        f_valC = 77;
        #20;
        D_stall = 0;
        #20;
        D_stall = 0;        
        f_op = `IORI;
        f_func = 6'b100000;
        f_rs = 5'b10111;
        f_rt = 5'b10000;
        f_rd = 5'b10100;
        f_valC = 88;
        #20;
        D_stall = 1;
        f_valC = 99;
        #20;
    end

    initial begin
        repeat(10)
            #10 clk = ~clk;
    end

    initial begin
      	$monitor("time = ", $time, " op=%b func=%b rs=%d rt=%d rd=%d valC=%d", D_op, D_func, D_rs, D_rt, D_rd, D_valC);
    end

endmodule