data/full_repos/permissive/194007311/encoder_interface.v
data/verilator_xmls/dd34716c-649d-4179-90b6-da966f028022.xml
module encoder_in(
	clk,
	rst, 
	phaseA, 
	phaseB, 
	pulse_count,
	pulse_diff
    );



parameter REG_MAX = 64;




input 						clk;
input 						rst;
input 						phaseA;
input 						phaseB;



output 	reg signed[REG_MAX-1:0] 	pulse_count = 0;
output 	reg signed[REG_MAX-1:0] 	pulse_diff = 0;







reg 	[15:0]			count = 0;
reg 	[2:0] 			phaseA_del = 0;
reg 	[2:0] 			phaseB_del = 0;
reg 	signed [REG_MAX-1:0] 	pulse_count_prev = 0;







always @(posedge clk) 
	begin
		phaseA_del <= {phaseA_del[1:0],phaseA};
		phaseB_del <= {phaseB_del[1:0],phaseB};
		if ( rst ) 
			begin
				phaseA_del <= 0;
				phaseB_del <= 0;
				pulse_count <= 0;
				pulse_count_prev <= 0;
				pulse_diff <= 0;
				count <= 0;
			end	
		if (~rst) 
			begin
				count <= count + 1'b1;
				if(enable) 
					begin						
						if(direction) 
							begin
								if(count == 10000)
									begin
										pulse_diff <= pulse_count - pulse_count_prev;
										pulse_count <= pulse_count + 1'b1;
										pulse_count_prev <= pulse_count;	
										count <= 0;
									end
								else
									pulse_count <= pulse_count + 1'b1;
							end
						if (~direction) 
							begin
								if(count == 10000)
									begin
										pulse_diff <= pulse_count - pulse_count_prev;										
										pulse_count <= pulse_count - 1'b1;
										pulse_count_prev <= pulse_count;	
										count <= 0;
									end
								else
									pulse_count <= pulse_count - 1'b1;
							end
					end
				if(~enable)
					begin
						if(count == 10000)
							begin
								pulse_diff <= pulse_count - pulse_count_prev;
								pulse_count_prev <= pulse_count;	
								count <= 0;
							end
					end				
			end		
	end
	

wire enable = phaseA_del[1] ^ phaseA_del[2] ^ phaseB_del[1] ^ phaseB_del[2];
wire direction = phaseA_del[1] ^ phaseB_del[2];

	
endmodule
module encoder_in(
	clk,
	rst, 
	phaseA, 
	phaseB, 
	pulse_count,
	pulse_diff
    );




parameter REG_MAX = 64;




input 						clk;
input 						rst;
input 						phaseA;
input 						phaseB;



output 	reg signed[REG_MAX-1:0] 	pulse_count = 0;
output 	reg signed[REG_MAX-1:0] 	pulse_diff = 0;







reg 	[15:0]			count = 0;
reg 	[2:0] 			phaseA_del = 0;
reg 	[2:0] 			phaseB_del = 0;
reg 	signed [REG_MAX-1:0] 	pulse_count_prev = 0;







always @(posedge clk) 
	begin
		phaseA_del <= {phaseA_del[1:0],phaseA};
		phaseB_del <= {phaseB_del[1:0],phaseB};
		if ( rst ) 
			begin
				phaseA_del <= 0;
				phaseB_del <= 0;
				pulse_count <= 0;
				pulse_count_prev <= 0;
				pulse_diff <= 0;
				count <= 0;
			end	
		if (~rst) 
			begin
				count <= count + 1'b1;
				if(enable) 
					begin						
						if(direction) 
							begin
								if(count == 10000)
									begin
										pulse_diff <= pulse_count - pulse_count_prev;
										pulse_count <= pulse_count + 1'b1;
										pulse_count_prev <= pulse_count;	
										count <= 0;
									end
								else
									pulse_count <= pulse_count + 1'b1;
							end
						if (~direction) 
							begin
								if(count == 10000)
									begin
										pulse_diff <= pulse_count - pulse_count_prev;										
										pulse_count <= pulse_count - 1'b1;
										pulse_count_prev <= pulse_count;	
										count <= 0;
									end
								else
									pulse_count <= pulse_count - 1'b1;
							end
					end
				if(~enable)
					begin
						if(count == 10000)
							begin
								pulse_diff <= pulse_count - pulse_count_prev;
								pulse_count_prev <= pulse_count;	
								count <= 0;
							end
					end				
			end		
	end
	

wire enable = phaseA_del[1] ^ phaseA_del[2] ^ phaseB_del[1] ^ phaseB_del[2];
wire direction = phaseA_del[1] ^ phaseB_del[2];

	
endmodule