data/full_repos/permissive/143278/ivltests/vhdl_reduce.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_reduce.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #1 if(and_reduced !== 1\'b0 || or_reduced !== 1\'b0) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_reduce.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1 if(and_reduced !== 1\'b0 || or_reduced !== 1\'b1) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_reduce.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #1 if(and_reduced !== 1\'b1 || or_reduced !== 1\'b1) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_reduce.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #1 if(and_reduced !== 1\'bx || or_reduced !== 1\'b1) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_reduce.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #1 if(and_reduced !== 1\'b0 || or_reduced !== 1\'bx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_reduce.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #1 if(and_reduced !== 1\'bx || or_reduced !== 1\'bx) begin\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_reduce.v:26: Cannot find file containing module: \'vhdl_reduce\'\nvhdl_reduce test(inp, and_reduced, or_reduced);\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_reduce\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_reduce.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_reduce.sv\n             vhdl_reduce\n             vhdl_reduce.v\n             vhdl_reduce.sv\n             obj_dir/vhdl_reduce\n             obj_dir/vhdl_reduce.v\n             obj_dir/vhdl_reduce.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vhdl_reduce_test;
logic [4:0] inp;
logic and_reduced, or_reduced;

vhdl_reduce test(inp, and_reduced, or_reduced);

initial begin
    inp = 5'b00000;
    #1 if(and_reduced !== 1'b0 || or_reduced !== 1'b0) begin
        $display("FAILED 1");
        $finish();
    end

    inp = 5'b00010;
    #1 if(and_reduced !== 1'b0 || or_reduced !== 1'b1) begin
        $display("FAILED 2");
        $finish();
    end

    inp = 5'b11111;
    #1 if(and_reduced !== 1'b1 || or_reduced !== 1'b1) begin
        $display("FAILED 3");
        $finish();
    end

    inp = 5'bzz1xx;
    #1 if(and_reduced !== 1'bx || or_reduced !== 1'b1) begin
        $display(and_reduced);
        $display(or_reduced);
        $display("FAILED 4");
        $finish();
    end

    inp = 5'bzz0xx;
    #1 if(and_reduced !== 1'b0 || or_reduced !== 1'bx) begin
        $display(and_reduced);
        $display(or_reduced);
        $display("FAILED 5");
        $finish();
    end

    inp = 5'bzzzxx;
    #1 if(and_reduced !== 1'bx || or_reduced !== 1'bx) begin
        $display(and_reduced);
        $display(or_reduced);
        $display("FAILED 6");
        $finish();
    end

    $display("PASSED");
end
endmodule
module vhdl_reduce_test;

logic [4:0] inp;
logic and_reduced, or_reduced;

vhdl_reduce test(inp, and_reduced, or_reduced);

initial begin
    inp = 5'b00000;
    #1 if(and_reduced !== 1'b0 || or_reduced !== 1'b0) begin
        $display("FAILED 1");
        $finish();
    end

    inp = 5'b00010;
    #1 if(and_reduced !== 1'b0 || or_reduced !== 1'b1) begin
        $display("FAILED 2");
        $finish();
    end

    inp = 5'b11111;
    #1 if(and_reduced !== 1'b1 || or_reduced !== 1'b1) begin
        $display("FAILED 3");
        $finish();
    end

    inp = 5'bzz1xx;
    #1 if(and_reduced !== 1'bx || or_reduced !== 1'b1) begin
        $display(and_reduced);
        $display(or_reduced);
        $display("FAILED 4");
        $finish();
    end

    inp = 5'bzz0xx;
    #1 if(and_reduced !== 1'b0 || or_reduced !== 1'bx) begin
        $display(and_reduced);
        $display(or_reduced);
        $display("FAILED 5");
        $finish();
    end

    inp = 5'bzzzxx;
    #1 if(and_reduced !== 1'bx || or_reduced !== 1'bx) begin
        $display(and_reduced);
        $display(or_reduced);
        $display("FAILED 6");
        $finish();
    end

    $display("PASSED");
end
endmodule