data/full_repos/permissive/159891569/waveChannel.t.v
 line:23: before: "["
1: b'%Error: data/full_repos/permissive/159891569/waveChannel.t.v:1: Cannot find include file: waveChannel.v\n`include "waveChannel.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/waveChannel.v\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/waveChannel.v.v\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/waveChannel.v.sv\n             waveChannel.v\n             waveChannel.v.v\n             waveChannel.v.sv\n             obj_dir/waveChannel.v\n             obj_dir/waveChannel.v.v\n             obj_dir/waveChannel.v.sv\n%Error: data/full_repos/permissive/159891569/waveChannel.t.v:2: Cannot find include file: swDac.v\n`include "swDac.v" \n         ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159891569/waveChannel.t.v:25: Unsupported: Ignoring delay on this delayed statement.\n  trigger = 0; #10; trigger = 1; #10; trigger = 0;\n               ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159891569/waveChannel.t.v:25: Unsupported: Ignoring delay on this delayed statement.\n  trigger = 0; #10; trigger = 1; #10; trigger = 0;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/waveChannel.t.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #10000;\n  ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module testWaveChannel();

	wire clk; baseClk baseclk(clk);
	wire clk256; fixedTimer #(16384) tmr256(clk, clk256);

	reg trigger;
	reg [1:0] vol;
	reg [10:0] freq;
	reg [31:0] [3:0] samples;
	wire [3:0] signal;

	waveChannel dut(clk, clk256, 1'd1, vol, 6'd31, trigger, 1'd0, freq, samples, signal);
	swDac dac(signal, signal);

	initial begin
		reg [5:0] ii;
		for (ii = 0; ii < 32; ii++) samples[ii] = ii;
		vol = 2'b01;
		freq = 11'd2000;

		
		trigger = 0; #10; trigger = 1; #10; trigger = 0;

		#10000;

		$finish;

	end
endmodule
module testWaveChannel();


	wire clk; baseClk baseclk(clk);
	wire clk256; fixedTimer #(16384) tmr256(clk, clk256);

	reg trigger;
	reg [1:0] vol;
	reg [10:0] freq;
	reg [31:0] [3:0] samples;
	wire [3:0] signal;

	waveChannel dut(clk, clk256, 1'd1, vol, 6'd31, trigger, 1'd0, freq, samples, signal);
	swDac dac(signal, signal);

	initial begin
		reg [5:0] ii;
		for (ii = 0; ii < 32; ii++) samples[ii] = ii;
		vol = 2'b01;
		freq = 11'd2000;

		
		trigger = 0; #10; trigger = 1; #10; trigger = 0;

		#10000;

		$finish;

	end
endmodule