data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Datamem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Datamem.v:43: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                                       : ... In instance Memory\n          while((loop < 10\'b1111111111)|| (loop == 10\'b1111111111))\n                                                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Datamem.v:54: Bit extraction of array[1023:0] requires 10 bit index, not 20 bits.\n                                                                                       : ... In instance Memory\n          4\'b0001:mem[addr][7:0] = data_in[7:0];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Datamem.v:55: Bit extraction of array[1023:0] requires 10 bit index, not 20 bits.\n                                                                                       : ... In instance Memory\n          4\'b0010:mem[addr][15:8] = data_in[7:0];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Datamem.v:56: Bit extraction of array[1023:0] requires 10 bit index, not 20 bits.\n                                                                                       : ... In instance Memory\n          4\'b0100:mem[addr][23:16] = data_in[7:0];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Datamem.v:57: Bit extraction of array[1023:0] requires 10 bit index, not 20 bits.\n                                                                                       : ... In instance Memory\n          4\'b1000:mem[addr][31:24] = data_in[7:0];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Datamem.v:58: Bit extraction of array[1023:0] requires 10 bit index, not 20 bits.\n                                                                                       : ... In instance Memory\n          4\'b0011:mem[addr][15:0] = data_in[15:0];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Datamem.v:59: Bit extraction of array[1023:0] requires 10 bit index, not 20 bits.\n                                                                                       : ... In instance Memory\n          4\'b1100:mem[addr][31:16] = data_in[15:0];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Datamem.v:60: Bit extraction of array[1023:0] requires 10 bit index, not 20 bits.\n                                                                                       : ... In instance Memory\n          4\'b1111:mem[addr][31:0] = data_in[31:0];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Datamem.v:79: Bit extraction of array[1023:0] requires 10 bit index, not 20 bits.\n                                                                                       : ... In instance Memory\n  assign data_out[31:0] = (mem[addr][31:0])&({32{ld}});\n                              ^\n%Error: Exiting due to 9 warning(s)\n'
module Memory(
input clk,
input str,
input [3:0]sel,
input ld,
input clr,
input [19:0]addr,
input [31:0]data_in,
output  [31:0]data_out   
    );  
    reg [31:0]mem[1023:0];
integer loop;
  reg pre_clr;
  initial pre_clr = 0;
  
  always@(posedge clk or posedge clr)
  begin
      if(pre_clr == 0 && clr == 1)
      begin
          loop = 0;
          while((loop < 10'b1111111111)|| (loop == 10'b1111111111))
          begin
              mem[loop] = 0;
              loop = loop + 1;
          end
      end
      else if(clr == 1)
      ;
      else if(str == 1)
      begin
          case(sel)
          4'b0001:mem[addr][7:0] = data_in[7:0];
          4'b0010:mem[addr][15:8] = data_in[7:0];
          4'b0100:mem[addr][23:16] = data_in[7:0];
          4'b1000:mem[addr][31:24] = data_in[7:0];
          4'b0011:mem[addr][15:0] = data_in[15:0];
          4'b1100:mem[addr][31:16] = data_in[15:0];
          4'b1111:mem[addr][31:0] = data_in[31:0];
          endcase
      end












      else
      ;
      pre_clr = clr;
  end
  assign data_out[31:0] = (mem[addr][31:0])&({32{ld}});

endmodule
module Memory(
input clk,
input str,
input [3:0]sel,
input ld,
input clr,
input [19:0]addr,
input [31:0]data_in,
output  [31:0]data_out   
    );
  
    reg [31:0]mem[1023:0];
integer loop;
  reg pre_clr;
  initial pre_clr = 0;
  
  always@(posedge clk or posedge clr)
  begin
      if(pre_clr == 0 && clr == 1)
      begin
          loop = 0;
          while((loop < 10'b1111111111)|| (loop == 10'b1111111111))
          begin
              mem[loop] = 0;
              loop = loop + 1;
          end
      end
      else if(clr == 1)
      ;
      else if(str == 1)
      begin
          case(sel)
          4'b0001:mem[addr][7:0] = data_in[7:0];
          4'b0010:mem[addr][15:8] = data_in[7:0];
          4'b0100:mem[addr][23:16] = data_in[7:0];
          4'b1000:mem[addr][31:24] = data_in[7:0];
          4'b0011:mem[addr][15:0] = data_in[15:0];
          4'b1100:mem[addr][31:16] = data_in[15:0];
          4'b1111:mem[addr][31:0] = data_in[31:0];
          endcase
      end












      else
      ;
      pre_clr = clr;
  end
  assign data_out[31:0] = (mem[addr][31:0])&({32{ld}});

endmodule