data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v
 line:29: before: ","
1: b'%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:96: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'WOFS\' generates 4 bits.\n                                                                             : ... In instance NINJAKUN_SP.eng\nassign     WPAD = {1\'b0,XPOS}-{XPOSH,8\'h0}+WOFS-1\'d1;\n                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:96: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 9 bits.\n                                                                             : ... In instance NINJAKUN_SP.eng\nassign     WPAD = {1\'b0,XPOS}-{XPOSH,8\'h0}+WOFS-1\'d1;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:142: Operator ADD expects 9 bits on the RHS, but RHS\'s CONST \'5\'h11\' generates 5 bits.\n                                                                              : ... In instance NINJAKUN_SP.eng\n    NV <= PV+5\'d17;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:142: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 9 bits.\n                                                                              : ... In instance NINJAKUN_SP.eng\n    NV <= PV+5\'d17;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:176: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s VARREF \'SPADT\' generates 8 bits.\n                                                                              : ... In instance NINJAKUN_SP.eng\n   PTNO  <= RAIDERS5 ? { PTNO[8:6], SPADT[7:2] } : SPADT;\n                     ^\n%Error: data/full_repos/permissive/217518118/rtl/ninjakun_sprite.v:32: Cannot find file containing module: \'dpram\'\ndpram #(8,10) ldbuf(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/217518118/rtl,data/full_repos/permissive/217518118/dpram\n             data/full_repos/permissive/217518118/rtl,data/full_repos/permissive/217518118/dpram.v\n             data/full_repos/permissive/217518118/rtl,data/full_repos/permissive/217518118/dpram.sv\n             dpram\n             dpram.v\n             dpram.sv\n             obj_dir/dpram\n             obj_dir/dpram.v\n             obj_dir/dpram.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
function [3:0] XOUT;
input  [2:0] N;
input [31:0] CDT;
	case(N)
	 0: XOUT = CDT[7:4];
	 1: XOUT = CDT[3:0];
	 2: XOUT = CDT[15:12];
	 3: XOUT = CDT[11:8];
	 4: XOUT = CDT[23:20];
	 5: XOUT = CDT[19:16];
	 6: XOUT = CDT[31:28];
	 7: XOUT = CDT[27:24];
	endcase
endfunction
function [3:0] XOUT;

input  [2:0] N;
input [31:0] CDT;
	case(N)
	 0: XOUT = CDT[7:4];
	 1: XOUT = CDT[3:0];
	 2: XOUT = CDT[15:12];
	 3: XOUT = CDT[11:8];
	 4: XOUT = CDT[23:20];
	 5: XOUT = CDT[19:16];
	 6: XOUT = CDT[31:28];
	 7: XOUT = CDT[27:24];
	endcase
endfunction