data/full_repos/permissive/143278/vhdl_tests/pr2554124.v
data/verilator_xmls/82e86d3d-4e9e-4de8-8469-9a35439f9f41.xml
module a(output b_buf, input b);
  assign b_buf = 1'b0;
endmodule
module a(output b_buf, input b);

  assign b_buf = 1'b0;
endmodule