data/full_repos/permissive/134867890/testfixture.v
 line:70: before: "reset"
1: b'%Warning-STMTDLY: data/full_repos/permissive/134867890/testfixture.v:56: Unsupported: Ignoring delay on this delayed statement.\nalways begin #(10/2) clk=~clk ; end   \n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/134867890/testfixture.v:70: syntax error, unexpected \'@\'\n@(negedge clk) reset=1\'b1 ;\n^\n%Warning-STMTDLY: data/full_repos/permissive/134867890/testfixture.v:71: Unsupported: Ignoring delay on this delayed statement.\n#(10*2) reset=1\'b0 ;\n^\n%Error: data/full_repos/permissive/134867890/testfixture.v:73: syntax error, unexpected \'@\'\n@(negedge clk) ;\n^\n%Error: data/full_repos/permissive/134867890/testfixture.v:78: syntax error, unexpected \'@\'\n    @(negedge clk) ;\n    ^\n%Error: data/full_repos/permissive/134867890/testfixture.v:96: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("alu.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/134867890/testfixture.v:97: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars;\n   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/134867890/testfixture.v:103: Unsupported: Ignoring delay on this delayed statement.\n#(10*100) \n^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testfixture ;

reg [2:0] opcode;

reg [3:0] src_a ,src_b ; 

reg clk,reset ;

wire [3:0]alu_out ;

wire overflow,zero ;

reg [10:0]pattern_in[0:`DATA_NUM-1] ;

reg [5:0]ans[0:`DATA_NUM-1] ;


reg overflow_exp,zero_exp ;

reg [3:0] alu_out_exp ;

alu u_alu (	.overflow(overflow),
			.alu_out(alu_out),
			.zero(zero),
			.src_a(src_a),
			.src_b(src_b),
			.opcode(opcode),
			.clk(clk),
			.reset(reset)
) ;

always begin #(`CYCLE/2) clk=~clk ; end

initial begin
$readmemb(`PATTERN,pattern_in) ;
$readmemb(`EXPECT,ans) ;
end


integer i ,err ,check;

initial begin
clk=1'b0 ;
err=0 ;
check=0;
@(negedge clk) reset=1'b1 ;
#(`CYCLE*2) reset=1'b0 ;

@(negedge clk) ;

  for(i=0;i<`DATA_NUM;i=i+1) begin
    {opcode,src_a,src_b}=pattern_in[i] ;
    {alu_out_exp,overflow_exp,zero_exp}=ans[i] ;
    @(negedge clk) ;

    if(alu_out!=alu_out_exp||overflow!=overflow_exp||zero!=zero_exp) begin
    err=err+1 ;
    $display($time,"Error at opcode=%b, src_a=%b, src_b=%b",opcode,src_a,src_b) ;
    $display($time,"Expect   : alu_out=%b, overflow=%b, zero=%b",alu_out_exp,overflow_exp,zero_exp) ;
    $display($time,"Your ans : alu_out=%b, overflow=%b, zero=%b\n\n",alu_out,overflow,zero) ;	
	

    end
    else if(alu_out==alu_out_exp&&overflow==overflow_exp&&zero==zero_exp) check=check+1;
  end
end



initial
begin
   $dumpfile("alu.vcd");
   $dumpvars;
end


initial begin

#(`CYCLE*100) 
if((err==0)&&(check==96)) begin
$display("-------------------   ALU check successfully   -------------------");
$display("            $$              ");
$display("           $  $");
$display("           $  $");
$display("          $   $");
$display("         $    $");
$display("$$$$$$$$$     $$$$$$$$");
$display("$$$$$$$              $");
$display("$$$$$$$              $");
$display("$$$$$$$              $");
$display("$$$$$$$              $");
$display("$$$$$$$              $");
$display("$$$$$$$$$$$$         $$");
$display("$$$$$      $$$$$$$$$$");
end
else if((err==0)&&(check!=96)) begin
$display("-----------   Oops! Something wrong with your code!   ------------");
end
else $display("-------------------   There are %d errors   -------------------", err);
$finish ;

end

endmodule
module testfixture ;


reg [2:0] opcode;

reg [3:0] src_a ,src_b ; 

reg clk,reset ;

wire [3:0]alu_out ;

wire overflow,zero ;

reg [10:0]pattern_in[0:`DATA_NUM-1] ;

reg [5:0]ans[0:`DATA_NUM-1] ;


reg overflow_exp,zero_exp ;

reg [3:0] alu_out_exp ;

alu u_alu (	.overflow(overflow),
			.alu_out(alu_out),
			.zero(zero),
			.src_a(src_a),
			.src_b(src_b),
			.opcode(opcode),
			.clk(clk),
			.reset(reset)
) ;

always begin #(`CYCLE/2) clk=~clk ; end

initial begin
$readmemb(`PATTERN,pattern_in) ;
$readmemb(`EXPECT,ans) ;
end


integer i ,err ,check;

initial begin
clk=1'b0 ;
err=0 ;
check=0;
@(negedge clk) reset=1'b1 ;
#(`CYCLE*2) reset=1'b0 ;

@(negedge clk) ;

  for(i=0;i<`DATA_NUM;i=i+1) begin
    {opcode,src_a,src_b}=pattern_in[i] ;
    {alu_out_exp,overflow_exp,zero_exp}=ans[i] ;
    @(negedge clk) ;

    if(alu_out!=alu_out_exp||overflow!=overflow_exp||zero!=zero_exp) begin
    err=err+1 ;
    $display($time,"Error at opcode=%b, src_a=%b, src_b=%b",opcode,src_a,src_b) ;
    $display($time,"Expect   : alu_out=%b, overflow=%b, zero=%b",alu_out_exp,overflow_exp,zero_exp) ;
    $display($time,"Your ans : alu_out=%b, overflow=%b, zero=%b\n\n",alu_out,overflow,zero) ;	
	

    end
    else if(alu_out==alu_out_exp&&overflow==overflow_exp&&zero==zero_exp) check=check+1;
  end
end



initial
begin
   $dumpfile("alu.vcd");
   $dumpvars;
end


initial begin

#(`CYCLE*100) 
if((err==0)&&(check==96)) begin
$display("-------------------   ALU check successfully   -------------------");
$display("            $$              ");
$display("           $  $");
$display("           $  $");
$display("          $   $");
$display("         $    $");
$display("$$$$$$$$$     $$$$$$$$");
$display("$$$$$$$              $");
$display("$$$$$$$              $");
$display("$$$$$$$              $");
$display("$$$$$$$              $");
$display("$$$$$$$              $");
$display("$$$$$$$$$$$$         $$");
$display("$$$$$      $$$$$$$$$$");
end
else if((err==0)&&(check!=96)) begin
$display("-----------   Oops! Something wrong with your code!   ------------");
end
else $display("-------------------   There are %d errors   -------------------", err);
$finish ;

end

endmodule