data/full_repos/permissive/157135695/cpu.v
1: b"%Error: data/full_repos/permissive/157135695/cpu.v:38: Cannot find file containing module: 'signExtend'\n  signExtend SE (\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157135695,data/full_repos/permissive/157135695/signExtend\n             data/full_repos/permissive/157135695,data/full_repos/permissive/157135695/signExtend.v\n             data/full_repos/permissive/157135695,data/full_repos/permissive/157135695/signExtend.sv\n             signExtend\n             signExtend.v\n             signExtend.sv\n             obj_dir/signExtend\n             obj_dir/signExtend.v\n             obj_dir/signExtend.sv\n%Error: data/full_repos/permissive/157135695/cpu.v:43: Cannot find file containing module: 'two_to_one_mux'\n  two_to_one_mux MBmux (\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157135695/cpu.v:50: Cannot find file containing module: 'two_to_one_mux'\n  two_to_one_mux MDmux (\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157135695/cpu.v:59: Cannot find file containing module: 'decoder'\n decoder d1( \n ^~~~~~~\n%Error: data/full_repos/permissive/157135695/cpu.v:81: Cannot find file containing module: 'alu'\n  alu alu1( \n  ^~~\n%Error: data/full_repos/permissive/157135695/cpu.v:93: Cannot find file containing module: 'registerFile'\n  registerFile regfile(\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/157135695/cpu.v:105: Cannot find file containing module: 'halt_logic'\nhalt_logic haltLogic (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/157135695/cpu.v:111: Cannot find file containing module: 'two_to_one_mux'\ntwo_to_one_mux doHalt (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module cpu(CLK, RESET, EN_L, Iin, Din, PC, NextPC, DataA, DataB, DataC, DataD, MW); 
  input         CLK; 
  input         RESET; 
  input         EN_L; 
  input  [15:0] Iin; 
  input  [7:0]  Din; 
   
  output [7:0]  PC; 
  output [7:0]  NextPC; 
  output [7:0]  DataA; 
  output [7:0]  DataB; 
  output [7:0]  DataC; 
  output [7:0]  DataD; 
  output        MW; 
  wire MB; 
  wire MD;
  wire LD;
  wire C;
  wire V;
  wire N;
  wire Z;
  wire [2:0] DR;
  wire [2:0] SA;
  wire [2:0] SB;
  wire [5:0] IMM;
  wire [2:0] FS;
  wire [7:0] SEXT;
  wire [7:0] MBmuxOUT;
  wire BS;
  wire OFF;
  wire HALT;
  reg [7:0] PC; 
  reg [7:0] NextPC; 
  wire H; 
  wire [7:0] whichPC; 

  
  signExtend SE (
  .IMM(IMM),
  .SEXT(SEXT)
  );
  
  two_to_one_mux MBmux (
  .INA(DataB),
  .INB(SEXT),
  .SEL(MB),
  .OUT(MBmuxOUT)
  );
  
  two_to_one_mux MDmux (
  .INA(DataD),
  .INB(Din),
  .SEL(MD),
  .OUT(DataC)  
  );
  
  
   
 decoder d1( 
 .INST(Iin),
 .DR(DR), 
 .SA(SA), 
 .SB(SB), 
 .IMM(IMM), 
 .MB(MB), 
 .FS(FS), 
 .MD(MD), 
 .LD(LD), 
 .MW(MW), 
 .BS(BS), 
 .OFF(OFF), 
 .HALT(HALT) 
 ); 
   

  

   

 
  alu alu1( 
   
  .A(DataA), 
  .B(MBmuxOUT), 
  .OP(FS), 
  .Y(DataD), 
  .C(C), 
  .V(V), 
  .N(N), 
  .Z(Z) 
  ); 
   
  registerFile regfile(
  .RESET(RESET),
  .LD(LD),
  .CLK(CLK),
  .SA(SA),
  .SB(SB),
  .DR(DR),
  .DataA(DataA),
  .DataB(DataB),
  .D_in(DataC)
  );
  
halt_logic haltLogic (
	.CLK (CLK),
	.HALT (HALT), 
	.EN_L (EN_L),
	.H (H)
);
two_to_one_mux doHalt (
	.INA((PC + 2)), 
	.INB(PC), 
	.SEL(H),
	.OUT(whichPC)
);
  always @(*) 
  begin  
    if (RESET) 
        NextPC = 8'd0; 
    else 
        NextPC =whichPC;          
	 end 

	always @ (posedge CLK)
	begin
		PC<=NextPC;
	end
   
   
      

 
endmodule
module cpu(CLK, RESET, EN_L, Iin, Din, PC, NextPC, DataA, DataB, DataC, DataD, MW);
 
  input         CLK; 
  input         RESET; 
  input         EN_L; 
  input  [15:0] Iin; 
  input  [7:0]  Din; 
   
  output [7:0]  PC; 
  output [7:0]  NextPC; 
  output [7:0]  DataA; 
  output [7:0]  DataB; 
  output [7:0]  DataC; 
  output [7:0]  DataD; 
  output        MW; 
  wire MB; 
  wire MD;
  wire LD;
  wire C;
  wire V;
  wire N;
  wire Z;
  wire [2:0] DR;
  wire [2:0] SA;
  wire [2:0] SB;
  wire [5:0] IMM;
  wire [2:0] FS;
  wire [7:0] SEXT;
  wire [7:0] MBmuxOUT;
  wire BS;
  wire OFF;
  wire HALT;
  reg [7:0] PC; 
  reg [7:0] NextPC; 
  wire H; 
  wire [7:0] whichPC; 

  
  signExtend SE (
  .IMM(IMM),
  .SEXT(SEXT)
  );
  
  two_to_one_mux MBmux (
  .INA(DataB),
  .INB(SEXT),
  .SEL(MB),
  .OUT(MBmuxOUT)
  );
  
  two_to_one_mux MDmux (
  .INA(DataD),
  .INB(Din),
  .SEL(MD),
  .OUT(DataC)  
  );
  
  
   
 decoder d1( 
 .INST(Iin),
 .DR(DR), 
 .SA(SA), 
 .SB(SB), 
 .IMM(IMM), 
 .MB(MB), 
 .FS(FS), 
 .MD(MD), 
 .LD(LD), 
 .MW(MW), 
 .BS(BS), 
 .OFF(OFF), 
 .HALT(HALT) 
 ); 
   

  

   

 
  alu alu1( 
   
  .A(DataA), 
  .B(MBmuxOUT), 
  .OP(FS), 
  .Y(DataD), 
  .C(C), 
  .V(V), 
  .N(N), 
  .Z(Z) 
  ); 
   
  registerFile regfile(
  .RESET(RESET),
  .LD(LD),
  .CLK(CLK),
  .SA(SA),
  .SB(SB),
  .DR(DR),
  .DataA(DataA),
  .DataB(DataB),
  .D_in(DataC)
  );
  
halt_logic haltLogic (
	.CLK (CLK),
	.HALT (HALT), 
	.EN_L (EN_L),
	.H (H)
);
two_to_one_mux doHalt (
	.INA((PC + 2)), 
	.INB(PC), 
	.SEL(H),
	.OUT(whichPC)
);
  always @(*) 
  begin  
    if (RESET) 
        NextPC = 8'd0; 
    else 
        NextPC =whichPC;          
	 end 

	always @ (posedge CLK)
	begin
		PC<=NextPC;
	end
   
   
      

 
endmodule