data/full_repos/permissive/135701568/adder12bit.v
data/verilator_xmls/5e22059f-e5d0-4b95-a38f-07be58bc962c.xml
module adder12bit (in1, in2, out);
  input [11:0] in1, in2;
  output[11:0] out;
  assign out = (in1[11]) ? in2 +(~(in1)+1) : in2 + in1;
endmodule
module adder12bit (in1, in2, out);

  input [11:0] in1, in2;
  output[11:0] out;
  assign out = (in1[11]) ? in2 +(~(in1)+1) : in2 + in1;
endmodule