data/full_repos/permissive/211316121/lab5_2/TransFF.v
data/verilator_xmls/75e9f43b-e33a-4aff-85cf-98cd7b56ec35.xml
module Top_FF(
    input [6:0] sw,
    input clkstd,
    output [3:0] led
);

wire clk;

CLKDIV top_div(clkstd,clk);

DtoJK top_jkff(sw[3],sw[2],clk,sw[1],sw[0],led[1],led[0]);
TtoD top_dff(sw[6],clk,sw[5],sw[4],led[3],led[2]);


endmodule
module Top_FF(
    input [6:0] sw,
    input clkstd,
    output [3:0] led
);


wire clk;

CLKDIV top_div(clkstd,clk);

DtoJK top_jkff(sw[3],sw[2],clk,sw[1],sw[0],led[1],led[0]);
TtoD top_dff(sw[6],clk,sw[5],sw[4],led[3],led[2]);


endmodule