data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:44: Unsupported: Ignoring delay on this delayed statement.\n  always #(MAIN_CLK_DELAY) r_Clk = ~r_Clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:92: syntax error, unexpected \'@\'\n    @(posedge r_Clk);\n    ^\n%Error: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:96: syntax error, unexpected \'@\'\n    @(posedge r_Clk);\n    ^\n%Error: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:98: syntax error, unexpected \'@\'\n    @(posedge w_Master_TX_Ready);\n    ^\n%Error: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:107: syntax error, unexpected \'@\'\n    @(posedge r_Clk);\n    ^\n%Error: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:112: syntax error, unexpected \'@\'\n      @(posedge r_Clk);\n      ^\n%Error: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:115: syntax error, unexpected \'@\'\n      @(posedge r_Clk);\n      ^\n%Error: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:117: syntax error, unexpected \'@\'\n      @(posedge w_Master_TX_Ready);\n      ^\n%Error: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:125: syntax error, unexpected \'@\'\n      repeat(10) @(posedge r_Clk);\n                 ^\n%Error: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:127: syntax error, unexpected \'@\'\n      repeat(10) @(posedge r_Clk);\n                 ^\n%Error: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:131: syntax error, unexpected \'@\'\n      repeat(10) @(posedge r_Clk);\n                 ^\n%Error: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:134: syntax error, unexpected \'@\'\n      repeat(100) @(posedge r_Clk);\n                  ^\n%Error: data/full_repos/permissive/174749554/Verilog/sim/SPI_Slave_TB.sv:143: syntax error, unexpected \'@\'\n      repeat(100) @(posedge r_Clk);\n                  ^\n%Error: Exiting due to 12 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SPI_Slave_TB ();
  
  parameter SPI_MODE = 1;
  parameter SPI_CLK_DELAY = 20;
  parameter MAIN_CLK_DELAY = 2;

  logic w_CPOL;
  logic w_CPHA;

  assign w_CPOL = (SPI_MODE == 2) | (SPI_MODE == 3);
  assign w_CPHA = (SPI_MODE == 1) | (SPI_MODE == 3);

  logic r_Rst_L     = 1'b0;

  logic [7:0] dataPayload[0:255]; 
  logic [7:0] dataLength;
  


  logic w_SPI_Clk;
  logic r_SPI_En    = 1'b0;
  logic r_Clk       = 1'b0;
  logic w_SPI_CS_n;
  logic w_SPI_MOSI;
  logic w_SPI_MISO;


  logic [7:0] r_Master_TX_Byte = 0;
  logic r_Master_TX_DV = 1'b0;
  logic r_Master_CS_n = 1'b1;
  logic w_Master_TX_Ready;
  logic r_Master_RX_DV;
  logic [7:0] r_Master_RX_Byte;


  logic       w_Slave_RX_DV, r_Slave_TX_DV;
  logic [7:0] w_Slave_RX_Byte, r_Slave_TX_Byte;


  always #(MAIN_CLK_DELAY) r_Clk = ~r_Clk;


  SPI_Slave #(.SPI_MODE(SPI_MODE)) SPI_Slave_UUT
  (

   .i_Rst_L(r_Rst_L),
   .i_Clk(r_Clk),
   .o_RX_DV(w_Slave_RX_DV),
   .o_RX_Byte(w_Slave_RX_Byte),
   .i_TX_DV(w_Slave_RX_DV),
   .i_TX_Byte(w_Slave_RX_Byte),


   .i_SPI_Clk(w_SPI_Clk),
   .o_SPI_MISO(w_SPI_MISO),
   .i_SPI_MOSI(w_SPI_MOSI),
   .i_SPI_CS_n(r_Master_CS_n)
   );


  SPI_Master 
  #(.SPI_MODE(SPI_MODE),
    .CLKS_PER_HALF_BIT(2),
    .NUM_SLAVES(1)) SPI_Master_UUT
  (

   .i_Rst_L(r_Rst_L),
   .i_Clk(r_Clk),
   

   .i_TX_Byte(r_Master_TX_Byte),
   .i_TX_DV(r_Master_TX_DV),
   .o_TX_Ready(w_Master_TX_Ready),
   

   .o_RX_DV(r_Master_RX_DV),
   .o_RX_Byte(r_Master_RX_Byte),


   .o_SPI_Clk(w_SPI_Clk),
   .i_SPI_MISO(w_SPI_MISO),
   .o_SPI_MOSI(w_SPI_MOSI)
   );



  task SendSingleByte(input [7:0] data);
    @(posedge r_Clk);
    r_Master_TX_Byte <= data;
    r_Master_TX_DV   <= 1'b1;
    r_Master_CS_n    <= 1'b0;
    @(posedge r_Clk);
    r_Master_TX_DV <= 1'b0;
    @(posedge w_Master_TX_Ready);
    r_Master_CS_n    <= 1'b1;    
  endtask



  task SendMultiByte(input [7:0] data[0:255], input [7:0] length);
    integer ii;

    @(posedge r_Clk);
    r_Master_CS_n    <= 1'b0;

    for (ii=0; ii<length; ii++)
    begin
      @(posedge r_Clk);
      r_Master_TX_Byte <= data[ii];
      r_Master_TX_DV   <= 1'b1;
      @(posedge r_Clk);
      r_Master_TX_DV <= 1'b0;
      @(posedge w_Master_TX_Ready);
    end
    r_Master_CS_n <= 1'b1;
  endtask

    
  initial
    begin
      repeat(10) @(posedge r_Clk);
      r_Rst_L  = 1'b0;
      repeat(10) @(posedge r_Clk);
      r_Rst_L          = 1'b1;
      r_Slave_TX_Byte <= 8'h5A;
      r_Slave_TX_DV   <= 1'b1;
      repeat(10) @(posedge r_Clk);
      r_Slave_TX_DV   <= 1'b0;
      SendSingleByte(8'hC1);
      repeat(100) @(posedge r_Clk);
      dataPayload[0]  = 8'h00;
      dataPayload[1]  = 8'h01;
      dataPayload[2]  = 8'h80;
      dataPayload[3]  = 8'hFF;
      dataPayload[4]  = 8'h55;
      dataPayload[5]  = 8'hAA;
      dataLength      = 6;
      SendMultiByte(dataPayload, dataLength);
      repeat(100) @(posedge r_Clk);
      $finish();      
    end

endmodule
module SPI_Slave_TB ();

  
  parameter SPI_MODE = 1;
  parameter SPI_CLK_DELAY = 20;
  parameter MAIN_CLK_DELAY = 2;

  logic w_CPOL;
  logic w_CPHA;

  assign w_CPOL = (SPI_MODE == 2) | (SPI_MODE == 3);
  assign w_CPHA = (SPI_MODE == 1) | (SPI_MODE == 3);

  logic r_Rst_L     = 1'b0;

  logic [7:0] dataPayload[0:255]; 
  logic [7:0] dataLength;
  


  logic w_SPI_Clk;
  logic r_SPI_En    = 1'b0;
  logic r_Clk       = 1'b0;
  logic w_SPI_CS_n;
  logic w_SPI_MOSI;
  logic w_SPI_MISO;


  logic [7:0] r_Master_TX_Byte = 0;
  logic r_Master_TX_DV = 1'b0;
  logic r_Master_CS_n = 1'b1;
  logic w_Master_TX_Ready;
  logic r_Master_RX_DV;
  logic [7:0] r_Master_RX_Byte;


  logic       w_Slave_RX_DV, r_Slave_TX_DV;
  logic [7:0] w_Slave_RX_Byte, r_Slave_TX_Byte;


  always #(MAIN_CLK_DELAY) r_Clk = ~r_Clk;


  SPI_Slave #(.SPI_MODE(SPI_MODE)) SPI_Slave_UUT
  (

   .i_Rst_L(r_Rst_L),
   .i_Clk(r_Clk),
   .o_RX_DV(w_Slave_RX_DV),
   .o_RX_Byte(w_Slave_RX_Byte),
   .i_TX_DV(w_Slave_RX_DV),
   .i_TX_Byte(w_Slave_RX_Byte),


   .i_SPI_Clk(w_SPI_Clk),
   .o_SPI_MISO(w_SPI_MISO),
   .i_SPI_MOSI(w_SPI_MOSI),
   .i_SPI_CS_n(r_Master_CS_n)
   );


  SPI_Master 
  #(.SPI_MODE(SPI_MODE),
    .CLKS_PER_HALF_BIT(2),
    .NUM_SLAVES(1)) SPI_Master_UUT
  (

   .i_Rst_L(r_Rst_L),
   .i_Clk(r_Clk),
   

   .i_TX_Byte(r_Master_TX_Byte),
   .i_TX_DV(r_Master_TX_DV),
   .o_TX_Ready(w_Master_TX_Ready),
   

   .o_RX_DV(r_Master_RX_DV),
   .o_RX_Byte(r_Master_RX_Byte),


   .o_SPI_Clk(w_SPI_Clk),
   .i_SPI_MISO(w_SPI_MISO),
   .o_SPI_MOSI(w_SPI_MOSI)
   );



  task SendSingleByte(input [7:0] data);
    @(posedge r_Clk);
    r_Master_TX_Byte <= data;
    r_Master_TX_DV   <= 1'b1;
    r_Master_CS_n    <= 1'b0;
    @(posedge r_Clk);
    r_Master_TX_DV <= 1'b0;
    @(posedge w_Master_TX_Ready);
    r_Master_CS_n    <= 1'b1;    
  endtask



  task SendMultiByte(input [7:0] data[0:255], input [7:0] length);
    integer ii;

    @(posedge r_Clk);
    r_Master_CS_n    <= 1'b0;

    for (ii=0; ii<length; ii++)
    begin
      @(posedge r_Clk);
      r_Master_TX_Byte <= data[ii];
      r_Master_TX_DV   <= 1'b1;
      @(posedge r_Clk);
      r_Master_TX_DV <= 1'b0;
      @(posedge w_Master_TX_Ready);
    end
    r_Master_CS_n <= 1'b1;
  endtask

    
  initial
    begin
      repeat(10) @(posedge r_Clk);
      r_Rst_L  = 1'b0;
      repeat(10) @(posedge r_Clk);
      r_Rst_L          = 1'b1;
      r_Slave_TX_Byte <= 8'h5A;
      r_Slave_TX_DV   <= 1'b1;
      repeat(10) @(posedge r_Clk);
      r_Slave_TX_DV   <= 1'b0;
      SendSingleByte(8'hC1);
      repeat(100) @(posedge r_Clk);
      dataPayload[0]  = 8'h00;
      dataPayload[1]  = 8'h01;
      dataPayload[2]  = 8'h80;
      dataPayload[3]  = 8'hFF;
      dataPayload[4]  = 8'h55;
      dataPayload[5]  = 8'hAA;
      dataLength      = 6;
      SendMultiByte(dataPayload, dataLength);
      repeat(100) @(posedge r_Clk);
      $finish();      
    end

endmodule