data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Vectors/vectorr.v
data/verilator_xmls/aaa4efda-3807-4358-a2a5-3bd646bde847.xml
module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;
endmodule
module top_module( 
    input [7:0] in,
    output [7:0] out
);

    assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;
endmodule