data/full_repos/permissive/202237519/verilog/digitalsystem6/sr_tb.v
 line:17: before: "$"
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/sr_tb.v:1: Cannot find include file: sr.v\n`include "sr.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/sr.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/sr.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/sr.v.sv\n             sr.v\n             sr.v.v\n             sr.v.sv\n             obj_dir/sr.v\n             obj_dir/sr.v.v\n             obj_dir/sr.v.sv\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/sr_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("sr_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/sr_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,sr_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/sr_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/sr_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/sr_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/sr_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module sr_tb;

reg S,R;
wire Q,nQ;

sr_latch sr1 (S,R,Q,nQ);

initial begin
    $dumpfile("sr_tb.vcd");
    $dumpvars(0,sr_tb);
        S<= 0; R <= 0;
    #20;
        S<= 0; R <= 1;
    #20;
        S<= 1; R <= 0;
    #20;
        S<= 1; R <= 1;
    #20;
    $finish;
end 

endmodule
module sr_tb;


reg S,R;
wire Q,nQ;

sr_latch sr1 (S,R,Q,nQ);

initial begin
    $dumpfile("sr_tb.vcd");
    $dumpvars(0,sr_tb);
        S<= 0; R <= 0;
    #20;
        S<= 0; R <= 1;
    #20;
        S<= 1; R <= 0;
    #20;
        S<= 1; R <= 1;
    #20;
    $finish;
end 

endmodule