data/full_repos/permissive/10490967/src/timer.v
data/verilator_xmls/48d7408d-1ef8-42b8-80a4-a3c094f5ae53.xml
module timer
  #(parameter
    TIMEOUT = 100)
   (input       clk,
    input       rst,

    input       up_req,
    output      up_grant,
    input       up_ack,

    output      down_req,
    input       down_grant,
    output      down_ack
);




`ifdef VERBOSE
    initial $display("Bus timer with timeout %d", TIMEOUT);
`endif




    wire        timeout;
    reg  [31:0] counter;




    assign up_grant = down_grant;

    assign down_ack = up_ack;

    assign timeout = (TIMEOUT == counter);

    assign down_req = up_req & ~timeout;


    always @(posedge clk)
        if (rst) counter <= 'b0;
        else begin
            counter <= 'b0;

            if (down_grant & ~timeout) begin
                counter <= counter + 1'b1;
            end
        end


endmodule
module timer
  #(parameter
    TIMEOUT = 100)
   (input       clk,
    input       rst,

    input       up_req,
    output      up_grant,
    input       up_ack,

    output      down_req,
    input       down_grant,
    output      down_ack
);





`ifdef VERBOSE
    initial $display("Bus timer with timeout %d", TIMEOUT);
`endif




    wire        timeout;
    reg  [31:0] counter;




    assign up_grant = down_grant;

    assign down_ack = up_ack;

    assign timeout = (TIMEOUT == counter);

    assign down_req = up_req & ~timeout;


    always @(posedge clk)
        if (rst) counter <= 'b0;
        else begin
            counter <= 'b0;

            if (down_grant & ~timeout) begin
                counter <= counter + 1'b1;
            end
        end


endmodule