data/full_repos/permissive/118800618/REG32.v
data/verilator_xmls/d040dbde-aca7-4d51-b193-390f02776518.xml
module REG32(	input clk,
					input rst,
					input CE,
					input [31:0] D,
					output reg[31:0] Q
				);
	initial Q = 0;
	always @(posedge clk or posedge rst)
		if (rst == 1) Q <= 0;
		else if (CE == 1) Q <= D;

endmodule
module REG32(	input clk,
					input rst,
					input CE,
					input [31:0] D,
					output reg[31:0] Q
				);

	initial Q = 0;
	always @(posedge clk or posedge rst)
		if (rst == 1) Q <= 0;
		else if (CE == 1) Q <= D;

endmodule