data/full_repos/permissive/200314387/verilog/74574/hct74574.v
 line:27: before: ">"
data/verilator_xmls/9627ac71-871a-4046-8fc3-c6f3dfcf8eb1.xml
module hct74574 (
input CLK,
input _OE,
input [7:0] D,
output [7:0] Q
);
    parameter LOG=0;
    parameter SETUP_TIME=12;
    parameter PD_CLK_Q=15;
    parameter PD_OE_Q=19;

    reg [7:0] dSetup;
    reg [7:0] dCurrent;


    assign #(SETUP_TIME) dSetup = D;
    
    specify
        (CLK *> Q) = (PD_CLK_Q);
        (_OE *> Q) = (PD_OE_Q);
    endspecify

    always @(posedge CLK) begin

        dCurrent <= dSetup;
    end

    always @(Q) begin
        if (LOG) $display("%9t", $time, " REGISTER %m   updated Q=%08b   data=%08b", Q, dCurrent);
    end

    assign Q = _OE ? 8'bz: dCurrent;
    
endmodule
module hct74574 (
input CLK,
input _OE,
input [7:0] D,
output [7:0] Q
);

    parameter LOG=0;
    parameter SETUP_TIME=12;
    parameter PD_CLK_Q=15;
    parameter PD_OE_Q=19;

    reg [7:0] dSetup;
    reg [7:0] dCurrent;


    assign #(SETUP_TIME) dSetup = D;
    
    specify
        (CLK *> Q) = (PD_CLK_Q);
        (_OE *> Q) = (PD_OE_Q);
    endspecify

    always @(posedge CLK) begin

        dCurrent <= dSetup;
    end

    always @(Q) begin
        if (LOG) $display("%9t", $time, " REGISTER %m   updated Q=%08b   data=%08b", Q, dCurrent);
    end

    assign Q = _OE ? 8'bz: dCurrent;
    
endmodule