data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:3: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/src/cpu/core/stage/id,data/full_repos/permissive/201275379/bus.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/id,data/full_repos/permissive/201275379/bus.v.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/id,data/full_repos/permissive/201275379/bus.v.sv\n             bus.v\n             bus.v.v\n             bus.v.sv\n             obj_dir/bus.v\n             obj_dir/bus.v.v\n             obj_dir/bus.v.sv\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:4: Cannot find include file: branch.v\n`include "branch.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:5: Cannot find include file: opgen.v\n`include "opgen.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:14: Define or directive not defined: \'`REG_ADDR_BUS\'\n  input   [`REG_ADDR_BUS] reg_write_addr_in,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  input   [`REG_ADDR_BUS] reg_write_addr_in,\n                        ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:16: Define or directive not defined: \'`GHR_BUS\'\n  input   [`GHR_BUS]      pht_index_in,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:17: Define or directive not defined: \'`ADDR_BUS\'\n  input   [`ADDR_BUS]     inst_branch_target_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:22: Define or directive not defined: \'`DATA_BUS\'\n  input   [`DATA_BUS]     mem_offset_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:25: Define or directive not defined: \'`CP0_ADDR_BUS\'\n  input   [`CP0_ADDR_BUS] cp0_addr_in,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:26: Define or directive not defined: \'`EXC_TYPE_BUS\'\n  input   [`EXC_TYPE_BUS] exception_type_in,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:29: Define or directive not defined: \'`OPGEN_BUS\'\n  input   [`OPGEN_BUS]    opgen_in,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:30: Define or directive not defined: \'`SHAMT_BUS\'\n  input   [`SHAMT_BUS]    shamt_in,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:33: Define or directive not defined: \'`DATA_BUS\'\n  input   [`DATA_BUS]     operand_data_1_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:34: Define or directive not defined: \'`DATA_BUS\'\n  input   [`DATA_BUS]     operand_data_2_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:35: Define or directive not defined: \'`ADDR_BUS\'\n  input   [`ADDR_BUS]     pc_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:37: Define or directive not defined: \'`REG_ADDR_BUS\'\n  output  [`REG_ADDR_BUS] reg_write_addr_out,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:39: Define or directive not defined: \'`GHR_BUS\'\n  output  [`GHR_BUS]      pht_index_out,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:40: Define or directive not defined: \'`ADDR_BUS\'\n  output  [`ADDR_BUS]     inst_branch_target_out,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:45: Define or directive not defined: \'`DATA_BUS\'\n  output  [`DATA_BUS]     mem_offset_out,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:48: Define or directive not defined: \'`CP0_ADDR_BUS\'\n  output  [`CP0_ADDR_BUS] cp0_addr_out,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:49: Define or directive not defined: \'`EXC_TYPE_BUS\'\n  output  [`EXC_TYPE_BUS] exception_type_out,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:52: Define or directive not defined: \'`OPGEN_BUS\'\n  output  [`OPGEN_BUS]    opgen_out,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:53: Define or directive not defined: \'`SHAMT_BUS\'\n  output  [`SHAMT_BUS]    shamt_out,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:56: Define or directive not defined: \'`DATA_BUS\'\n  output  [`DATA_BUS]     operand_data_1_out,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:57: Define or directive not defined: \'`DATA_BUS\'\n  output  [`DATA_BUS]     operand_data_2_out,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:58: Define or directive not defined: \'`ADDR_BUS\'\n  output  [`ADDR_BUS]     pc_out\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:67: Define or directive not defined: \'`REG_ADDR_BUS_WIDTH\'\n  PipelineDeliver #(`REG_ADDR_BUS_WIDTH) ff_reg_write_addr(\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:79: Define or directive not defined: \'`GHR_WIDTH\'\n  PipelineDeliver #(`GHR_WIDTH) ff_pht_index(\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:85: Define or directive not defined: \'`ADDR_BUS_WIDTH\'\n  PipelineDeliver #(`ADDR_BUS_WIDTH) ff_inst_branch_target(\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:115: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n  PipelineDeliver #(`DATA_BUS_WIDTH) ff_mem_offset(\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:133: Define or directive not defined: \'`CP0_ADDR_BUS_WIDTH\'\n  PipelineDeliver #(`CP0_ADDR_BUS_WIDTH) ff_cp0_addr(\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:139: Define or directive not defined: \'`EXC_TYPE_BUS_WIDTH\'\n  PipelineDeliver #(`EXC_TYPE_BUS_WIDTH) ff_exception_type(\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:157: Define or directive not defined: \'`OPGEN_WIDTH\'\n  PipelineDeliver #(`OPGEN_WIDTH) ff_opgen(\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:163: Define or directive not defined: \'`SHAMT_BUS_WIDTH\'\n  PipelineDeliver #(`SHAMT_BUS_WIDTH) ff_shamt(\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:181: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n  PipelineDeliver #(`DATA_BUS_WIDTH) ff_operand_data_1(\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:187: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n  PipelineDeliver #(`DATA_BUS_WIDTH) ff_operand_data_2(\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/IDROB.v:193: Define or directive not defined: \'`ADDR_BUS_WIDTH\'\n  PipelineDeliver #(`ADDR_BUS_WIDTH) ff_pc(\n                    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 37 error(s)\n'
module IDROB(
  input                   clk,
  input                   rst,
  input                   flush,
  input                   stall_current_stage,
  input                   stall_next_stage,
  input                   reg_write_en_in,
  input   [`REG_ADDR_BUS] reg_write_addr_in,
  input                   is_branch_taken_in,
  input   [`GHR_BUS]      pht_index_in,
  input   [`ADDR_BUS]     inst_branch_target_in,
  input                   mem_write_flag_in,
  input                   mem_read_flag_in,
  input                   mem_sign_ext_flag_in,
  input   [3:0]           mem_sel_in,
  input   [`DATA_BUS]     mem_offset_in,
  input                   cp0_read_flag_in,
  input                   cp0_write_flag_in,
  input   [`CP0_ADDR_BUS] cp0_addr_in,
  input   [`EXC_TYPE_BUS] exception_type_in,
  input                   is_next_delayslot_in,
  input                   is_delayslot_in,
  input   [`OPGEN_BUS]    opgen_in,
  input   [`SHAMT_BUS]    shamt_in,
  input                   operand_is_ref_1_in,
  input                   operand_is_ref_2_in,
  input   [`DATA_BUS]     operand_data_1_in,
  input   [`DATA_BUS]     operand_data_2_in,
  input   [`ADDR_BUS]     pc_in,
  output                  reg_write_en_out,
  output  [`REG_ADDR_BUS] reg_write_addr_out,
  output                  is_branch_taken_out,
  output  [`GHR_BUS]      pht_index_out,
  output  [`ADDR_BUS]     inst_branch_target_out,
  output                  mem_write_flag_out,
  output                  mem_read_flag_out,
  output                  mem_sign_ext_flag_out,
  output  [3:0]           mem_sel_out,
  output  [`DATA_BUS]     mem_offset_out,
  output                  cp0_read_flag_out,
  output                  cp0_write_flag_out,
  output  [`CP0_ADDR_BUS] cp0_addr_out,
  output  [`EXC_TYPE_BUS] exception_type_out,
  output                  is_current_delayslot_out,
  output                  is_delayslot_out,
  output  [`OPGEN_BUS]    opgen_out,
  output  [`SHAMT_BUS]    shamt_out,
  output                  operand_is_ref_1_out,
  output                  operand_is_ref_2_out,
  output  [`DATA_BUS]     operand_data_1_out,
  output  [`DATA_BUS]     operand_data_2_out,
  output  [`ADDR_BUS]     pc_out
);

  PipelineDeliver #(1) ff_reg_write_en(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    reg_write_en_in, reg_write_en_out
  );

  PipelineDeliver #(`REG_ADDR_BUS_WIDTH) ff_reg_write_addr(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    reg_write_addr_in, reg_write_addr_out
  );

  PipelineDeliver #(1) ff_is_branch_taken(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    is_branch_taken_in, is_branch_taken_out
  );

  PipelineDeliver #(`GHR_WIDTH) ff_pht_index(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    pht_index_in, pht_index_out
  );

  PipelineDeliver #(`ADDR_BUS_WIDTH) ff_inst_branch_target(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    inst_branch_target_in, inst_branch_target_out
  );

  PipelineDeliver #(1) ff_mem_write_flag(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    mem_write_flag_in, mem_write_flag_out
  );

  PipelineDeliver #(1) ff_mem_read_flag(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    mem_read_flag_in, mem_read_flag_out
  );

  PipelineDeliver #(1) ff_mem_sign_ext_flag(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    mem_sign_ext_flag_in, mem_sign_ext_flag_out
  );

  PipelineDeliver #(4) ff_mem_sel(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    mem_sel_in, mem_sel_out
  );

  PipelineDeliver #(`DATA_BUS_WIDTH) ff_mem_offset(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    mem_offset_in, mem_offset_out
  );

  PipelineDeliver #(1) ff_cp0_read_flag(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    cp0_read_flag_in, cp0_read_flag_out
  );

  PipelineDeliver #(1) ff_cp0_write_flag(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    cp0_write_flag_in, cp0_write_flag_out
  );

  PipelineDeliver #(`CP0_ADDR_BUS_WIDTH) ff_cp0_addr(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    cp0_addr_in, cp0_addr_out
  );

  PipelineDeliver #(`EXC_TYPE_BUS_WIDTH) ff_exception_type(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    exception_type_in, exception_type_out
  );

  PipelineDeliver #(1) ff_is_current_delayslot(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    is_next_delayslot_in, is_current_delayslot_out
  );

  PipelineDeliver #(1) ff_is_delayslot(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    is_delayslot_in, is_delayslot_out
  );

  PipelineDeliver #(`OPGEN_WIDTH) ff_opgen(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    opgen_in, opgen_out
  );

  PipelineDeliver #(`SHAMT_BUS_WIDTH) ff_shamt(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    shamt_in, shamt_out
  );

  PipelineDeliver #(1) ff_operand_is_ref_1(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    operand_is_ref_1_in, operand_is_ref_1_out
  );

  PipelineDeliver #(1) ff_operand_is_ref_2(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    operand_is_ref_2_in, operand_is_ref_2_out
  );

  PipelineDeliver #(`DATA_BUS_WIDTH) ff_operand_data_1(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    operand_data_1_in, operand_data_1_out
  );

  PipelineDeliver #(`DATA_BUS_WIDTH) ff_operand_data_2(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    operand_data_2_in, operand_data_2_out
  );

  PipelineDeliver #(`ADDR_BUS_WIDTH) ff_pc(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    pc_in, pc_out
  );

endmodule
module IDROB(
  input                   clk,
  input                   rst,
  input                   flush,
  input                   stall_current_stage,
  input                   stall_next_stage,
  input                   reg_write_en_in,
  input   [`REG_ADDR_BUS] reg_write_addr_in,
  input                   is_branch_taken_in,
  input   [`GHR_BUS]      pht_index_in,
  input   [`ADDR_BUS]     inst_branch_target_in,
  input                   mem_write_flag_in,
  input                   mem_read_flag_in,
  input                   mem_sign_ext_flag_in,
  input   [3:0]           mem_sel_in,
  input   [`DATA_BUS]     mem_offset_in,
  input                   cp0_read_flag_in,
  input                   cp0_write_flag_in,
  input   [`CP0_ADDR_BUS] cp0_addr_in,
  input   [`EXC_TYPE_BUS] exception_type_in,
  input                   is_next_delayslot_in,
  input                   is_delayslot_in,
  input   [`OPGEN_BUS]    opgen_in,
  input   [`SHAMT_BUS]    shamt_in,
  input                   operand_is_ref_1_in,
  input                   operand_is_ref_2_in,
  input   [`DATA_BUS]     operand_data_1_in,
  input   [`DATA_BUS]     operand_data_2_in,
  input   [`ADDR_BUS]     pc_in,
  output                  reg_write_en_out,
  output  [`REG_ADDR_BUS] reg_write_addr_out,
  output                  is_branch_taken_out,
  output  [`GHR_BUS]      pht_index_out,
  output  [`ADDR_BUS]     inst_branch_target_out,
  output                  mem_write_flag_out,
  output                  mem_read_flag_out,
  output                  mem_sign_ext_flag_out,
  output  [3:0]           mem_sel_out,
  output  [`DATA_BUS]     mem_offset_out,
  output                  cp0_read_flag_out,
  output                  cp0_write_flag_out,
  output  [`CP0_ADDR_BUS] cp0_addr_out,
  output  [`EXC_TYPE_BUS] exception_type_out,
  output                  is_current_delayslot_out,
  output                  is_delayslot_out,
  output  [`OPGEN_BUS]    opgen_out,
  output  [`SHAMT_BUS]    shamt_out,
  output                  operand_is_ref_1_out,
  output                  operand_is_ref_2_out,
  output  [`DATA_BUS]     operand_data_1_out,
  output  [`DATA_BUS]     operand_data_2_out,
  output  [`ADDR_BUS]     pc_out
);


  PipelineDeliver #(1) ff_reg_write_en(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    reg_write_en_in, reg_write_en_out
  );

  PipelineDeliver #(`REG_ADDR_BUS_WIDTH) ff_reg_write_addr(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    reg_write_addr_in, reg_write_addr_out
  );

  PipelineDeliver #(1) ff_is_branch_taken(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    is_branch_taken_in, is_branch_taken_out
  );

  PipelineDeliver #(`GHR_WIDTH) ff_pht_index(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    pht_index_in, pht_index_out
  );

  PipelineDeliver #(`ADDR_BUS_WIDTH) ff_inst_branch_target(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    inst_branch_target_in, inst_branch_target_out
  );

  PipelineDeliver #(1) ff_mem_write_flag(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    mem_write_flag_in, mem_write_flag_out
  );

  PipelineDeliver #(1) ff_mem_read_flag(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    mem_read_flag_in, mem_read_flag_out
  );

  PipelineDeliver #(1) ff_mem_sign_ext_flag(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    mem_sign_ext_flag_in, mem_sign_ext_flag_out
  );

  PipelineDeliver #(4) ff_mem_sel(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    mem_sel_in, mem_sel_out
  );

  PipelineDeliver #(`DATA_BUS_WIDTH) ff_mem_offset(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    mem_offset_in, mem_offset_out
  );

  PipelineDeliver #(1) ff_cp0_read_flag(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    cp0_read_flag_in, cp0_read_flag_out
  );

  PipelineDeliver #(1) ff_cp0_write_flag(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    cp0_write_flag_in, cp0_write_flag_out
  );

  PipelineDeliver #(`CP0_ADDR_BUS_WIDTH) ff_cp0_addr(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    cp0_addr_in, cp0_addr_out
  );

  PipelineDeliver #(`EXC_TYPE_BUS_WIDTH) ff_exception_type(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    exception_type_in, exception_type_out
  );

  PipelineDeliver #(1) ff_is_current_delayslot(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    is_next_delayslot_in, is_current_delayslot_out
  );

  PipelineDeliver #(1) ff_is_delayslot(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    is_delayslot_in, is_delayslot_out
  );

  PipelineDeliver #(`OPGEN_WIDTH) ff_opgen(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    opgen_in, opgen_out
  );

  PipelineDeliver #(`SHAMT_BUS_WIDTH) ff_shamt(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    shamt_in, shamt_out
  );

  PipelineDeliver #(1) ff_operand_is_ref_1(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    operand_is_ref_1_in, operand_is_ref_1_out
  );

  PipelineDeliver #(1) ff_operand_is_ref_2(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    operand_is_ref_2_in, operand_is_ref_2_out
  );

  PipelineDeliver #(`DATA_BUS_WIDTH) ff_operand_data_1(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    operand_data_1_in, operand_data_1_out
  );

  PipelineDeliver #(`DATA_BUS_WIDTH) ff_operand_data_2(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    operand_data_2_in, operand_data_2_out
  );

  PipelineDeliver #(`ADDR_BUS_WIDTH) ff_pc(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    pc_in, pc_out
  );

endmodule