data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf/sw_dolut.v
1: b"%Error: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf/sw_dolut.v:29: Cannot find file containing module: 'LUT6_2'\n LUT6_2 #( \n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf,data/full_repos/permissive/128781882/LUT6_2\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf,data/full_repos/permissive/128781882/LUT6_2.v\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf,data/full_repos/permissive/128781882/LUT6_2.sv\n             LUT6_2\n             LUT6_2.v\n             LUT6_2.sv\n             obj_dir/LUT6_2\n             obj_dir/LUT6_2.v\n             obj_dir/LUT6_2.sv\n%Error: Exiting due to 1 error(s)\n"
module sw_dolut(iT,iB,c,vcc,oT,oB);

	input iT,iB;
	input vcc;
	input c;
	output oT,oB;
	
	LUT6_2 #( 
		.INIT(64'hccccaaaaaaaacccc)
	) SW(
		.O6(oT), 
		.O5(oB), 
		.I0(iT), 
		.I1(iB), 
		.I2(vcc), 
		.I3(vcc), 
		.I4(c), 
		.I5(vcc)
	);


endmodule
module sw_dolut(iT,iB,c,vcc,oT,oB);


	input iT,iB;
	input vcc;
	input c;
	output oT,oB;
	
	LUT6_2 #( 
		.INIT(64'hccccaaaaaaaacccc)
	) SW(
		.O6(oT), 
		.O5(oB), 
		.I0(iT), 
		.I1(iB), 
		.I2(vcc), 
		.I3(vcc), 
		.I4(c), 
		.I5(vcc)
	);


endmodule