data/full_repos/permissive/211316121/lab1/sources_1/new/decoder38.v
data/verilator_xmls/b3ee3aef-e911-4bec-99e7-8ec178b9a7a2.xml
module decoder38(
    input G1,
    input G2A,
    input G2B,
    input [2:0] S,
    output [7:0] Y
    );
    wire valid;
    assign valid=G1&~G2A&~G2B;
    assign Y[7]=~(valid &S[2]   &S[1]    &S[0]);
    assign Y[6]=~(valid &S[2]   &S[1]    &~S[0]);
    assign Y[5]=~(valid &S[2]   &~S[1]   &S[0]);
    assign Y[4]=~(valid &S[2]   &~S[1]   &~S[0]);
    assign Y[3]=~(valid &~S[2]  &S[1]    &S[0]);
    assign Y[2]=~(valid &~S[2]  &S[1]    &~S[0]);
    assign Y[1]=~(valid &~S[2]  &~S[1]   &S[0]);
    assign Y[0]=~(valid &~S[2]  &~S[1]   &~S[0]);
endmodule
module decoder38(
    input G1,
    input G2A,
    input G2B,
    input [2:0] S,
    output [7:0] Y
    );

    wire valid;
    assign valid=G1&~G2A&~G2B;
    assign Y[7]=~(valid &S[2]   &S[1]    &S[0]);
    assign Y[6]=~(valid &S[2]   &S[1]    &~S[0]);
    assign Y[5]=~(valid &S[2]   &~S[1]   &S[0]);
    assign Y[4]=~(valid &S[2]   &~S[1]   &~S[0]);
    assign Y[3]=~(valid &~S[2]  &S[1]    &S[0]);
    assign Y[2]=~(valid &~S[2]  &S[1]    &~S[0]);
    assign Y[1]=~(valid &~S[2]  &~S[1]   &S[0]);
    assign Y[0]=~(valid &~S[2]  &~S[1]   &~S[0]);
endmodule