data/full_repos/permissive/20951436/Code/fpga code/advanced code/Advanced code.v
1: b'%Error: Cannot find file containing module: code/advanced\n        ... Looked in:\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.v\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.sv\n             code/advanced\n             code/advanced.v\n             code/advanced.sv\n             obj_dir/code/advanced\n             obj_dir/code/advanced.v\n             obj_dir/code/advanced.sv\n%Error: Cannot find file containing module: code,data/full_repos/permissive/20951436\n%Error: Cannot find file containing module: data/full_repos/permissive/20951436/Code/fpga\n%Error: Cannot find file containing module: code/Advanced\n%Error: Cannot find file containing module: code.v\n%Error: Exiting due to 5 error(s)\n'
module motion (input clk, input en, input [3:0] pulses, input [31:0] obj_x, obj_y, obj_z, input PWM_en, output [3:0] sig_to_mot, dirp, dirn); 

	reg [3:0] en_controller; reg [3:0] en_len; reg [3:0] en_timer; 
	initial begin en_controller<=0; en_len<=0; en_timer<=0; end
	

	wire clk_calc, clk_PWM, clk_len; assign clk_calc = clk; assign clk_PWM = clk; assign clk_len = clk;
	wire [4:0] speed0, speed1, speed2, speed3; wire [3:0] comp_cont;
	wire [31:0] len0, len1, len2, len3; wire [3:0] comp_len; 


	reg [31:0] len_hist0, len_hist1, len_hist2, len_hist3; 
	initial begin
		len_hist0=32'd259; len_hist1<=32'd346; len_hist2<=32'd346; len_hist3<=32'd259;
	end
	


	

	wire [31:0] des_rot0_sign, des_rot1_sign, des_rot2_sign, des_rot3_sign;
	assign des_rot0_sign = len0 - len_hist0; assign des_rot1_sign = len1 - len_hist1;
	assign des_rot2_sign = len2 - len_hist2; assign des_rot3_sign = len3 - len_hist3;
	wire [3:0] dir;
	assign dir = {des_rot0_sign[31], des_rot1_sign[31], des_rot2_sign[31], des_rot3_sign[31]};
	
	wire [31:0] des_rot0, des_rot1, des_rot2, des_rot3;
	assign des_rot0 = (des_rot0_sign[31] ? ~des_rot0_sign + 1 : des_rot0_sign);
	assign des_rot1 = (des_rot1_sign[31] ? ~des_rot1_sign + 1 : des_rot1_sign);
	assign des_rot2 = (des_rot2_sign[31] ? ~des_rot2_sign + 1 : des_rot2_sign);
	assign des_rot3 = (des_rot3_sign[31] ? ~des_rot3_sign + 1 : des_rot3_sign);
	

	wire [31:0] mot_NE_x, mot_NE_y, mot_NE_z;	wire [31:0] mot_NW_x, mot_NW_y, mot_NW_z;
	wire [31:0] mot_SW_x, mot_SW_y, mot_SW_z;	wire [31:0] mot_SE_x, mot_SE_y, mot_SE_z;
	assign {mot_NE_x,mot_NE_y,mot_NE_z} = {32'h0,32'h3D4,32'h1AC};
	assign {mot_NW_x,mot_NW_y,mot_NW_z} = {32'h25D,32'h3D4,32'h1A9};
	assign {mot_SW_x,mot_SW_y,mot_SW_z} = {32'h244,32'h0,32'h18E};
	assign {mot_SE_x,mot_SE_y,mot_SE_z} = {32'h0,32'h0,32'h190};


	len_calc mot_len_NE(clk_len, en_len[0], mot_NE_x, mot_NE_y, mot_NE_z, obj_x, obj_y, obj_z, len0, comp_len[0]);
	len_calc mot_len_NW(clk_len, en_len[1], mot_NW_x, mot_NW_y, mot_NW_z, obj_x, obj_y, obj_z, len1, comp_len[1]);
	len_calc mot_len_SW(clk_len, en_len[2], mot_SW_x, mot_SW_y, mot_SW_z, obj_x, obj_y, obj_z, len2, comp_len[2]);
	len_calc mot_len_SE(clk_len, en_len[3], mot_SE_x, mot_SE_y, mot_SE_z, obj_x, obj_y, obj_z, len3, comp_len[3]);
	

	controller mot_control_mod_NE(clk_calc, en_controller[0], des_rot0, dir[0], pulses[0], speed0, comp_cont[0]);
	controller mot_control_mod_NW(clk_calc, en_controller[1], des_rot1, dir[1], pulses[1], speed1, comp_cont[1]);
	controller mot_control_mod_SW(clk_calc, en_controller[2], des_rot2, dir[2], pulses[2], speed2, comp_cont[2]);
	controller mot_control_mod_SE(clk_calc, en_controller[3], des_rot3, dir[3], pulses[3], speed3, comp_cont[3]);


	PWM_timer mot_timer_mod_NE(clk_PWM, speed0, (en_timer[0] & PWM_en), sig_to_mot[0], dirp[0], dirn[0]);
	PWM_timer mot_timer_mod_NW(clk_PWM, speed1, (en_timer[1] & PWM_en), sig_to_mot[1], dirp[1], dirn[1]);
	PWM_timer mot_timer_mod_SW(clk_PWM, speed2, (en_timer[2] & PWM_en), sig_to_mot[2], dirp[2], dirn[2]);
	PWM_timer mot_timer_mod_SE(clk_PWM, speed3, (en_timer[3] & PWM_en), sig_to_mot[3], dirp[3], dirn[3]);

	reg [1:0] state;
	initial state<=0;
	wire [3:0] len_diff = dir;
	reg state_en; initial state_en<=0;
	reg en_hist; initial en_hist<=1;
	reg [1:0] clk_fac0; initial clk_fac0<=0;
	reg clk_div0; initial clk_div0<=0;
	
	always @(negedge clk) begin
		clk_fac0<=clk_fac0+1;
		if (clk_fac0==0) clk_div0<=~clk_div0;
	end
	

	always @(negedge clk_div0) begin
		en_hist<=en;
		if (en) begin
			case (state)
				0: begin
					en_controller<=0; en_timer<=0;
					if (en & ~en_hist) begin
						en_len<=4'hF;
						state_en<=1;
					end else en_len<=4'h0;
					if (state_en==1 & ~|comp_len) state<=1;
				end
				1: begin
					if (&comp_len) begin
						en_controller<=4'hF; en_timer<=4'hF; en_len<=4'h0;
						state_en<=0;
					end
					if (state_en==0 & ~|comp_cont) state<=2;
				end
				2: begin
					if (&comp_cont) begin
						state<=0;
						len_hist0<=len0; len_hist1<=len1; len_hist2<=len2; len_hist3<=len3;
					end
				end
			endcase
		end else begin
			en_controller<=4'h0; en_len<=4'h0; en_timer<=4'h0; state<=0; state_en<=0;
		end
	end
	
endmodule
module motion (input clk, input en, input [3:0] pulses, input [31:0] obj_x, obj_y, obj_z, input PWM_en, output [3:0] sig_to_mot, dirp, dirn);
 

	reg [3:0] en_controller; reg [3:0] en_len; reg [3:0] en_timer; 
	initial begin en_controller<=0; en_len<=0; en_timer<=0; end
	

	wire clk_calc, clk_PWM, clk_len; assign clk_calc = clk; assign clk_PWM = clk; assign clk_len = clk;
	wire [4:0] speed0, speed1, speed2, speed3; wire [3:0] comp_cont;
	wire [31:0] len0, len1, len2, len3; wire [3:0] comp_len; 


	reg [31:0] len_hist0, len_hist1, len_hist2, len_hist3; 
	initial begin
		len_hist0=32'd259; len_hist1<=32'd346; len_hist2<=32'd346; len_hist3<=32'd259;
	end
	


	

	wire [31:0] des_rot0_sign, des_rot1_sign, des_rot2_sign, des_rot3_sign;
	assign des_rot0_sign = len0 - len_hist0; assign des_rot1_sign = len1 - len_hist1;
	assign des_rot2_sign = len2 - len_hist2; assign des_rot3_sign = len3 - len_hist3;
	wire [3:0] dir;
	assign dir = {des_rot0_sign[31], des_rot1_sign[31], des_rot2_sign[31], des_rot3_sign[31]};
	
	wire [31:0] des_rot0, des_rot1, des_rot2, des_rot3;
	assign des_rot0 = (des_rot0_sign[31] ? ~des_rot0_sign + 1 : des_rot0_sign);
	assign des_rot1 = (des_rot1_sign[31] ? ~des_rot1_sign + 1 : des_rot1_sign);
	assign des_rot2 = (des_rot2_sign[31] ? ~des_rot2_sign + 1 : des_rot2_sign);
	assign des_rot3 = (des_rot3_sign[31] ? ~des_rot3_sign + 1 : des_rot3_sign);
	

	wire [31:0] mot_NE_x, mot_NE_y, mot_NE_z;	wire [31:0] mot_NW_x, mot_NW_y, mot_NW_z;
	wire [31:0] mot_SW_x, mot_SW_y, mot_SW_z;	wire [31:0] mot_SE_x, mot_SE_y, mot_SE_z;
	assign {mot_NE_x,mot_NE_y,mot_NE_z} = {32'h0,32'h3D4,32'h1AC};
	assign {mot_NW_x,mot_NW_y,mot_NW_z} = {32'h25D,32'h3D4,32'h1A9};
	assign {mot_SW_x,mot_SW_y,mot_SW_z} = {32'h244,32'h0,32'h18E};
	assign {mot_SE_x,mot_SE_y,mot_SE_z} = {32'h0,32'h0,32'h190};


	len_calc mot_len_NE(clk_len, en_len[0], mot_NE_x, mot_NE_y, mot_NE_z, obj_x, obj_y, obj_z, len0, comp_len[0]);
	len_calc mot_len_NW(clk_len, en_len[1], mot_NW_x, mot_NW_y, mot_NW_z, obj_x, obj_y, obj_z, len1, comp_len[1]);
	len_calc mot_len_SW(clk_len, en_len[2], mot_SW_x, mot_SW_y, mot_SW_z, obj_x, obj_y, obj_z, len2, comp_len[2]);
	len_calc mot_len_SE(clk_len, en_len[3], mot_SE_x, mot_SE_y, mot_SE_z, obj_x, obj_y, obj_z, len3, comp_len[3]);
	

	controller mot_control_mod_NE(clk_calc, en_controller[0], des_rot0, dir[0], pulses[0], speed0, comp_cont[0]);
	controller mot_control_mod_NW(clk_calc, en_controller[1], des_rot1, dir[1], pulses[1], speed1, comp_cont[1]);
	controller mot_control_mod_SW(clk_calc, en_controller[2], des_rot2, dir[2], pulses[2], speed2, comp_cont[2]);
	controller mot_control_mod_SE(clk_calc, en_controller[3], des_rot3, dir[3], pulses[3], speed3, comp_cont[3]);


	PWM_timer mot_timer_mod_NE(clk_PWM, speed0, (en_timer[0] & PWM_en), sig_to_mot[0], dirp[0], dirn[0]);
	PWM_timer mot_timer_mod_NW(clk_PWM, speed1, (en_timer[1] & PWM_en), sig_to_mot[1], dirp[1], dirn[1]);
	PWM_timer mot_timer_mod_SW(clk_PWM, speed2, (en_timer[2] & PWM_en), sig_to_mot[2], dirp[2], dirn[2]);
	PWM_timer mot_timer_mod_SE(clk_PWM, speed3, (en_timer[3] & PWM_en), sig_to_mot[3], dirp[3], dirn[3]);

	reg [1:0] state;
	initial state<=0;
	wire [3:0] len_diff = dir;
	reg state_en; initial state_en<=0;
	reg en_hist; initial en_hist<=1;
	reg [1:0] clk_fac0; initial clk_fac0<=0;
	reg clk_div0; initial clk_div0<=0;
	
	always @(negedge clk) begin
		clk_fac0<=clk_fac0+1;
		if (clk_fac0==0) clk_div0<=~clk_div0;
	end
	

	always @(negedge clk_div0) begin
		en_hist<=en;
		if (en) begin
			case (state)
				0: begin
					en_controller<=0; en_timer<=0;
					if (en & ~en_hist) begin
						en_len<=4'hF;
						state_en<=1;
					end else en_len<=4'h0;
					if (state_en==1 & ~|comp_len) state<=1;
				end
				1: begin
					if (&comp_len) begin
						en_controller<=4'hF; en_timer<=4'hF; en_len<=4'h0;
						state_en<=0;
					end
					if (state_en==0 & ~|comp_cont) state<=2;
				end
				2: begin
					if (&comp_cont) begin
						state<=0;
						len_hist0<=len0; len_hist1<=len1; len_hist2<=len2; len_hist3<=len3;
					end
				end
			endcase
		end else begin
			en_controller<=4'h0; en_len<=4'h0; en_timer<=4'h0; state<=0; state_en<=0;
		end
	end
	
endmodule