data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_writeback_monociclo.v
 line:48: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_writeback_monociclo.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #10 read_data_memory=32\'h00000003;     \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_writeback_monociclo.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #500 $finish;\n    ^\n%Error: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_writeback_monociclo.v:51: Cannot find file containing module: \'tl_write_back\'\ntl_write_back\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_write_back\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_write_back.v\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_write_back.sv\n             tl_write_back\n             tl_write_back.v\n             tl_write_back.sv\n             obj_dir/tl_write_back\n             obj_dir/tl_write_back.v\n             obj_dir/tl_write_back.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_instruction_writeback_monociclo();

localparam len=32;
localparam NB_CTRL_WB = 2;
localparam NB_ADDRESS_REGISTROS = 5; 

reg [len-1:0] read_data_memory;
reg [len-1:0] result_alu;
reg [NB_CTRL_WB-1:0] ctrl_wb;
reg [NB_ADDRESS_REGISTROS-1:0] write_reg_mem;
wire [len-1:0] write_data_banco_reg;
wire [NB_ADDRESS_REGISTROS-1:0] write_reg_wb;
wire RegWrite;

initial
begin
    
  #10 read_data_memory=32'h00000003;
      result_alu=32'h00000010;
      ctrl_wb = 2'b0;
      write_reg_mem = 5'b0;



    
    #500 $finish;
end

tl_write_back
#(
    .len(len),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)
)
    u_tl_write_back
(
    .i_read_data(read_data_memory),
    .i_result_alu(result_alu),
    .i_ctrl_wb(ctrl_wb),
    .i_write_reg(write_reg_mem),
    .o_write_data(write_data_banco_reg),
    .o_write_reg(write_reg_wb),
    .o_RegWrite(RegWrite)
);


endmodule
module tb_instruction_writeback_monociclo();


localparam len=32;
localparam NB_CTRL_WB = 2;
localparam NB_ADDRESS_REGISTROS = 5; 

reg [len-1:0] read_data_memory;
reg [len-1:0] result_alu;
reg [NB_CTRL_WB-1:0] ctrl_wb;
reg [NB_ADDRESS_REGISTROS-1:0] write_reg_mem;
wire [len-1:0] write_data_banco_reg;
wire [NB_ADDRESS_REGISTROS-1:0] write_reg_wb;
wire RegWrite;

initial
begin
    
  #10 read_data_memory=32'h00000003;
      result_alu=32'h00000010;
      ctrl_wb = 2'b0;
      write_reg_mem = 5'b0;



    
    #500 $finish;
end

tl_write_back
#(
    .len(len),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS)
)
    u_tl_write_back
(
    .i_read_data(read_data_memory),
    .i_result_alu(result_alu),
    .i_ctrl_wb(ctrl_wb),
    .i_write_reg(write_reg_mem),
    .o_write_data(write_data_banco_reg),
    .o_write_reg(write_reg_wb),
    .o_RegWrite(RegWrite)
);


endmodule