data/full_repos/permissive/139881681/mixer/synthesis/submodules/delay_signal.v
data/verilator_xmls/4a908772-257e-4a54-af89-01c4ab981f68.xml
module delay_signal(output reg[23:0] out, input clk, input[23:0] data, input wren);
	always @(posedge clk)
	begin
		if(wren)
			out <= data;
	end
endmodule
module delay_signal(output reg[23:0] out, input clk, input[23:0] data, input wren);

	always @(posedge clk)
	begin
		if(wren)
			out <= data;
	end
endmodule