data/full_repos/permissive/21918028/high_throughput_core/rtl/padder.v
1: b"%Error: data/full_repos/permissive/21918028/high_throughput_core/rtl/padder.v:71: Cannot find file containing module: 'padder1'\n    padder1 p0 (in, byte_num, v0);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21918028/high_throughput_core/rtl,data/full_repos/permissive/21918028/padder1\n             data/full_repos/permissive/21918028/high_throughput_core/rtl,data/full_repos/permissive/21918028/padder1.v\n             data/full_repos/permissive/21918028/high_throughput_core/rtl,data/full_repos/permissive/21918028/padder1.sv\n             padder1\n             padder1.v\n             padder1.sv\n             obj_dir/padder1\n             obj_dir/padder1.v\n             obj_dir/padder1.sv\n%Error: Exiting due to 1 error(s)\n"
module padder(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready, f_ack);
    input              clk, reset;
    input      [63:0]  in;
    input              in_ready, is_last;
    input      [2:0]   byte_num;
    output             buffer_full;
    output reg [575:0] out;
    output             out_ready;
    input              f_ack;
    
    reg                state;
    reg                done;
    reg        [8:0]   i;
    wire       [63:0]  v0;
    reg        [63:0]  v1;
    wire               accept,
                       update;
    
    assign buffer_full = i[8];
    assign out_ready = buffer_full;
    assign accept = (~ state) & in_ready & (~ buffer_full);
    assign update = (accept | (state & (~ buffer_full))) & (~ done);

    always @ (posedge clk)
      if (reset)
        out <= 0;
      else if (update)
        out <= {out[575-64:0], v1};

    always @ (posedge clk)
      if (reset)
        i <= 0;
      else if (f_ack | update)
        i <= {i[7:0], 1'b1} & {9{~ f_ack}};



    always @ (posedge clk)
      if (reset)
        state <= 0;
      else if (is_last)
        state <= 1;

    always @ (posedge clk)
      if (reset)
        done <= 0;
      else if (state & out_ready)
        done <= 1;

    padder1 p0 (in, byte_num, v0);
    
    always @ (*)
      begin
        if (state)
          begin
            v1 = 0;
            v1[7] = v1[7] | i[7];
          end
        else if (is_last == 0)
          v1 = in;
        else
          begin
            v1 = v0;
            v1[7] = v1[7] | i[7];
          end
      end
endmodule
module padder(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready, f_ack);

    input              clk, reset;
    input      [63:0]  in;
    input              in_ready, is_last;
    input      [2:0]   byte_num;
    output             buffer_full;
    output reg [575:0] out;
    output             out_ready;
    input              f_ack;
    
    reg                state;
    reg                done;
    reg        [8:0]   i;
    wire       [63:0]  v0;
    reg        [63:0]  v1;
    wire               accept,
                       update;
    
    assign buffer_full = i[8];
    assign out_ready = buffer_full;
    assign accept = (~ state) & in_ready & (~ buffer_full);
    assign update = (accept | (state & (~ buffer_full))) & (~ done);

    always @ (posedge clk)
      if (reset)
        out <= 0;
      else if (update)
        out <= {out[575-64:0], v1};

    always @ (posedge clk)
      if (reset)
        i <= 0;
      else if (f_ack | update)
        i <= {i[7:0], 1'b1} & {9{~ f_ack}};



    always @ (posedge clk)
      if (reset)
        state <= 0;
      else if (is_last)
        state <= 1;

    always @ (posedge clk)
      if (reset)
        done <= 0;
      else if (state & out_ready)
        done <= 1;

    padder1 p0 (in, byte_num, v0);
    
    always @ (*)
      begin
        if (state)
          begin
            v1 = 0;
            v1[7] = v1[7] | i[7];
          end
        else if (is_last == 0)
          v1 = in;
        else
          begin
            v1 = v0;
            v1[7] = v1[7] | i[7];
          end
      end
endmodule