data/full_repos/permissive/105772342/tb/tb_conv8to24.v
 line:23: before: "("
1: b'%Error: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:25: syntax error, unexpected \'@\'\n  @(posedge clk) data8 <= _data8; valid8 <= _valid8; ready24 <= _ready24;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:29: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:32: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("tb_conv_8to24.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:33: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:34: syntax error, unexpected \'@\'\n  @(posedge clk) reset = 0;\n  ^\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:37: syntax error, unexpected \'@\'\n @(negedge clk) \n ^\n%Error: data/full_repos/permissive/105772342/tb/tb_conv8to24.v:38: syntax error, unexpected \'(\', expecting IDENTIFIER\n  stimulate(8\'h34, 1, 1);  \n            ^~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module tb_conv_8to24();
	reg clk = 0;
	reg reset = 1;
	reg [7:0] data8;
	reg valid8;
	wire ready8;
	wire [23:0] data24;
	wire valid24;
	reg ready24;

	task stimulate(input [7:0] _data8, input _valid8, input _ready24);
		begin
		@(posedge clk) data8 <= _data8; valid8 <= _valid8; ready24 <= _ready24;
		end
	endtask

	always #10 clk = ~clk;

	initial begin
		$dumpfile("tb_conv_8to24.vcd");
		$dumpvars;
		@(posedge clk) reset = 0;

		stimulate(8'h12, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h34, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h56, 1, 1);
		`expect(24'h123456, 1, 1);


		stimulate(8'h78, 0, 0);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h78, 1, 0);
		`expect(24'hXXXXXX, 0, 1);


		stimulate(8'h9A, 0, 0);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h9A, 1, 0);
		`expect(24'hXXXXXX, 0, 1);


		stimulate(8'hBC, 0, 0);
		`expect(24'h789ABC, 0, 0);
		stimulate(8'hBC, 0, 1);
		`expect(24'h789ABC, 0, 1);
		stimulate(8'hBC, 1, 0);
		`expect(24'h789ABC, 0, 0);
		stimulate(8'hBC, 1, 1);
		`expect(24'h789ABC, 1, 1);


		stimulate(8'h12, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h34, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h56, 1, 1);
		`expect(24'h123456, 1, 1);

		stimulate(8'h78, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h9A, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'hBC, 1, 1);
		`expect(24'h789ABC, 1, 1);

		stimulate(8'hDE, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'hF0, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h12, 1, 1);
		`expect(24'hDEF012, 1, 1);

		stimulate(8'h34, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h56, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h78, 1, 1);
		`expect(24'h345678, 1, 1);

		$finish;
	end

	CONV_8TO24 conv_8to24(
			.clk_in(clk),
			.reset_in(reset),
			.data8_in(data8),
			.valid8_in(valid8),
			.ready8_out(ready8),
			.data24_out(data24),
			.valid24_out(valid24),
			.ready24_in(ready24));

endmodule
module tb_conv_8to24();

	reg clk = 0;
	reg reset = 1;
	reg [7:0] data8;
	reg valid8;
	wire ready8;
	wire [23:0] data24;
	wire valid24;
	reg ready24;

	task stimulate(input [7:0] _data8, input _valid8, input _ready24);
		begin
		@(posedge clk) data8 <= _data8; valid8 <= _valid8; ready24 <= _ready24;
		end
	endtask

	always #10 clk = ~clk;

	initial begin
		$dumpfile("tb_conv_8to24.vcd");
		$dumpvars;
		@(posedge clk) reset = 0;

		stimulate(8'h12, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h34, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h56, 1, 1);
		`expect(24'h123456, 1, 1);


		stimulate(8'h78, 0, 0);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h78, 1, 0);
		`expect(24'hXXXXXX, 0, 1);


		stimulate(8'h9A, 0, 0);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h9A, 1, 0);
		`expect(24'hXXXXXX, 0, 1);


		stimulate(8'hBC, 0, 0);
		`expect(24'h789ABC, 0, 0);
		stimulate(8'hBC, 0, 1);
		`expect(24'h789ABC, 0, 1);
		stimulate(8'hBC, 1, 0);
		`expect(24'h789ABC, 0, 0);
		stimulate(8'hBC, 1, 1);
		`expect(24'h789ABC, 1, 1);


		stimulate(8'h12, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h34, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h56, 1, 1);
		`expect(24'h123456, 1, 1);

		stimulate(8'h78, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h9A, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'hBC, 1, 1);
		`expect(24'h789ABC, 1, 1);

		stimulate(8'hDE, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'hF0, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h12, 1, 1);
		`expect(24'hDEF012, 1, 1);

		stimulate(8'h34, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h56, 1, 1);
		`expect(24'hXXXXXX, 0, 1);
		stimulate(8'h78, 1, 1);
		`expect(24'h345678, 1, 1);

		$finish;
	end

	CONV_8TO24 conv_8to24(
			.clk_in(clk),
			.reset_in(reset),
			.data8_in(data8),
			.valid8_in(valid8),
			.ready8_out(ready8),
			.data24_out(data24),
			.valid24_out(valid24),
			.ready24_in(ready24));

endmodule