data/full_repos/permissive/143278/ivltests/undef_lval_select3c.v
 line:7: before: "assign"
1: b'%Error: data/full_repos/permissive/143278/ivltests/undef_lval_select3c.v:8: Unsupported: Verilog 1995 deassign\n    deassign vec[idx+:1];\n    ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg [2:-1] vec;
  integer idx;

  initial begin
    idx = 'bx;
    assign vec[idx+:1] = 1'b1;
    deassign vec[idx+:1];
  end
endmodule
module top;

  reg [2:-1] vec;
  integer idx;

  initial begin
    idx = 'bx;
    assign vec[idx+:1] = 1'b1;
    deassign vec[idx+:1];
  end
endmodule