data/full_repos/permissive/192346182/VGA_Signal_Generator.v
1: b"%Error: data/full_repos/permissive/192346182/VGA_Signal_Generator.v:51: Cannot find file containing module: 'VGA_PLL'\nVGA_PLL VGA_Clk_Generator_0\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/192346182,data/full_repos/permissive/192346182/VGA_PLL\n             data/full_repos/permissive/192346182,data/full_repos/permissive/192346182/VGA_PLL.v\n             data/full_repos/permissive/192346182,data/full_repos/permissive/192346182/VGA_PLL.sv\n             VGA_PLL\n             VGA_PLL.v\n             VGA_PLL.sv\n             obj_dir/VGA_PLL\n             obj_dir/VGA_PLL.v\n             obj_dir/VGA_PLL.sv\n%Error: Exiting due to 1 error(s)\n"
module VGA_Signal_Generator
(
	input Fast_Clock,
	input Reset,
	output reg VGA_HS,
	output reg VGA_VS,
	output reg VGA_Clk,
	output reg [9:0] Counter_X,
	output reg [9:0] Counter_Y,
	output reg VGA_Blank_N,
	output reg VGA_Sync_N
);

localparam VERT_VISIBLE_PIXELS = 10'd480;
localparam VERT_SYNC_START = 10'd493;
localparam VERT_SYNC_END = 10'd494;
localparam VERT_TOTAL_PIXELS = 10'd525;

localparam HORZ_VISIBLE_PIXELS = 10'd640;
localparam HORZ_SYNC_START = 10'd659;
localparam HORZ_SYNC_END = 10'd754;
localparam HORZ_TOTAL_PIXELS = 10'd800;

reg VGA_HS_D1;
reg VGA_VS_D1;
reg VGA_Blank_D1;
wire Counter_X_Clear;
wire Counter_Y_Clear;

initial
begin
	Counter_X <= 10'b0;
	Counter_Y <= 10'b0;
	VGA_Clk <= 0;
end

VGA_PLL VGA_Clk_Generator_0
(
	.inclk0(Fast_Clock),
	.c0(VGA_Clk)
);

assign VGA_Sync_N = 1'b1;
assign Counter_X_Clear = (Counter_X == (HORZ_TOTAL_PIXELS-1));
assign Counter_Y_Clear = (Counter_Y == (VERT_TOTAL_PIXELS-1));



always @(posedge VGA_Clk or posedge Reset)
begin
	if (Reset)
		Counter_X <= 10'd0;
	else if (Counter_X_Clear)
		Counter_X <= 10'd0;
	else
	begin
		Counter_X <= Counter_X + 1'b1;
	end
end

always @(posedge VGA_Clk or posedge Reset)
begin
	if (Reset)
		Counter_Y <= 10'd0;
	else if (Counter_X_Clear && Counter_Y_Clear)
		Counter_Y <= 10'd0;
	else if (Counter_X_Clear)
		Counter_Y <= Counter_Y + 1'b1;
end

always @(posedge VGA_Clk)
begin

	VGA_HS_D1 <= ~((Counter_X >= HORZ_SYNC_START) && (Counter_X <= HORZ_SYNC_END));
	VGA_VS_D1 <= ~((Counter_Y >= VERT_SYNC_START) && (Counter_Y <= VERT_SYNC_END));


	VGA_Blank_D1 <= ((Counter_X < HORZ_VISIBLE_PIXELS) && (Counter_Y < VERT_VISIBLE_PIXELS));


	VGA_HS <= VGA_HS_D1;
	VGA_VS <= VGA_VS_D1;
	VGA_Blank_N <= VGA_Blank_D1;
end

endmodule
module VGA_Signal_Generator
(
	input Fast_Clock,
	input Reset,
	output reg VGA_HS,
	output reg VGA_VS,
	output reg VGA_Clk,
	output reg [9:0] Counter_X,
	output reg [9:0] Counter_Y,
	output reg VGA_Blank_N,
	output reg VGA_Sync_N
);


localparam VERT_VISIBLE_PIXELS = 10'd480;
localparam VERT_SYNC_START = 10'd493;
localparam VERT_SYNC_END = 10'd494;
localparam VERT_TOTAL_PIXELS = 10'd525;

localparam HORZ_VISIBLE_PIXELS = 10'd640;
localparam HORZ_SYNC_START = 10'd659;
localparam HORZ_SYNC_END = 10'd754;
localparam HORZ_TOTAL_PIXELS = 10'd800;

reg VGA_HS_D1;
reg VGA_VS_D1;
reg VGA_Blank_D1;
wire Counter_X_Clear;
wire Counter_Y_Clear;

initial
begin
	Counter_X <= 10'b0;
	Counter_Y <= 10'b0;
	VGA_Clk <= 0;
end

VGA_PLL VGA_Clk_Generator_0
(
	.inclk0(Fast_Clock),
	.c0(VGA_Clk)
);

assign VGA_Sync_N = 1'b1;
assign Counter_X_Clear = (Counter_X == (HORZ_TOTAL_PIXELS-1));
assign Counter_Y_Clear = (Counter_Y == (VERT_TOTAL_PIXELS-1));



always @(posedge VGA_Clk or posedge Reset)
begin
	if (Reset)
		Counter_X <= 10'd0;
	else if (Counter_X_Clear)
		Counter_X <= 10'd0;
	else
	begin
		Counter_X <= Counter_X + 1'b1;
	end
end

always @(posedge VGA_Clk or posedge Reset)
begin
	if (Reset)
		Counter_Y <= 10'd0;
	else if (Counter_X_Clear && Counter_Y_Clear)
		Counter_Y <= 10'd0;
	else if (Counter_X_Clear)
		Counter_Y <= Counter_Y + 1'b1;
end

always @(posedge VGA_Clk)
begin

	VGA_HS_D1 <= ~((Counter_X >= HORZ_SYNC_START) && (Counter_X <= HORZ_SYNC_END));
	VGA_VS_D1 <= ~((Counter_Y >= VERT_SYNC_START) && (Counter_Y <= VERT_SYNC_END));


	VGA_Blank_D1 <= ((Counter_X < HORZ_VISIBLE_PIXELS) && (Counter_Y < VERT_VISIBLE_PIXELS));


	VGA_HS <= VGA_HS_D1;
	VGA_VS <= VGA_VS_D1;
	VGA_Blank_N <= VGA_Blank_D1;
end

endmodule