data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/sort_cell.v
 line:125: before: "/"
1: b"%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/sort_cell.v:51: Cannot find file containing module: 'float_cmp'\nfloat_cmp fcomp (\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0,data/full_repos/permissive/13196823/float_cmp\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0,data/full_repos/permissive/13196823/float_cmp.v\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0,data/full_repos/permissive/13196823/float_cmp.sv\n             float_cmp\n             float_cmp.v\n             float_cmp.sv\n             obj_dir/float_cmp\n             obj_dir/float_cmp.v\n             obj_dir/float_cmp.sv\n%Error: Exiting due to 1 error(s)\n"
module sort_cell #(
	parameter SORT_WIDTH=32,
	parameter SHIFT_INPUT_WIDTH=8,
	parameter PRI_POS_START=0,
	parameter PRI_POS_END=32
) (
	input clk,
	input reset,


	input [SORT_WIDTH-1:0] prev_data,
	output [SORT_WIDTH-1:0] data_out,

	input [SORT_WIDTH-1:0] datain,
	input		       place_en,
	input		       wren,
	input		       order,


	input left_is_lower, 
	output i_am_lower

);

reg [SORT_WIDTH-1:0] datain_stored;
reg [SORT_WIDTH-1:0] current;
assign data_out = current;


reg is_lower, is_lower_next;
wire aleb;

wire [31:0] current_priority;
wire [31:0] datain_priority;

assign current_priority = current[PRI_POS_END-1:PRI_POS_START];
assign datain_priority = datain[PRI_POS_END-1:PRI_POS_START];



assign i_am_lower = is_lower;







float_cmp fcomp (
        .clk_en 	(place_en),
        .clock  	(clk),
        .dataa	(current_priority),
        .datab	(datain_priority),
        .aleb	(aleb)
);


always@(posedge clk) 
begin
	if(reset) begin
		current <= 0;
		is_lower <= 0;
		datain_stored <= 0;
	end
	else begin
		if(wren) begin
			current <= current;
			is_lower <= (aleb)?1'b1:1'b0;
		end
		else if(order) begin
			is_lower <= is_lower;
			case({left_is_lower,i_am_lower})
				2'b01: 		current <= datain_stored;
				2'b11: 		current <= prev_data;
				default: 	current <= current;
			endcase
		end
		else begin
			current <= current;
			is_lower <= is_lower;
		end
		datain_stored <= datain;
	end
	

end

endmodule
module sort_cell #(
	parameter SORT_WIDTH=32,
	parameter SHIFT_INPUT_WIDTH=8,
	parameter PRI_POS_START=0,
	parameter PRI_POS_END=32
) (
	input clk,
	input reset,


	input [SORT_WIDTH-1:0] prev_data,
	output [SORT_WIDTH-1:0] data_out,

	input [SORT_WIDTH-1:0] datain,
	input		       place_en,
	input		       wren,
	input		       order,


	input left_is_lower, 
	output i_am_lower

);


reg [SORT_WIDTH-1:0] datain_stored;
reg [SORT_WIDTH-1:0] current;
assign data_out = current;


reg is_lower, is_lower_next;
wire aleb;

wire [31:0] current_priority;
wire [31:0] datain_priority;

assign current_priority = current[PRI_POS_END-1:PRI_POS_START];
assign datain_priority = datain[PRI_POS_END-1:PRI_POS_START];



assign i_am_lower = is_lower;







float_cmp fcomp (
        .clk_en 	(place_en),
        .clock  	(clk),
        .dataa	(current_priority),
        .datab	(datain_priority),
        .aleb	(aleb)
);


always@(posedge clk) 
begin
	if(reset) begin
		current <= 0;
		is_lower <= 0;
		datain_stored <= 0;
	end
	else begin
		if(wren) begin
			current <= current;
			is_lower <= (aleb)?1'b1:1'b0;
		end
		else if(order) begin
			is_lower <= is_lower;
			case({left_is_lower,i_am_lower})
				2'b01: 		current <= datain_stored;
				2'b11: 		current <= prev_data;
				default: 	current <= current;
			endcase
		end
		else begin
			current <= current;
			is_lower <= is_lower;
		end
		datain_stored <= datain;
	end
	

end

endmodule