data/full_repos/permissive/193148725/Timer/posedge_det.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/34b63020-2518-4c0b-a67f-b5bace3c09f7.xml
module posedge_det (i_clk, sig_in, sig_out);
input i_clk;
input sig_in;
output sig_out;

reg sig_reg;

always @(posedge i_clk) begin
sig_reg <= sig_in;
end

assign sig_out = ~sig_in & sig_reg;

endmodule
module posedge_det (i_clk, sig_in, sig_out);

input i_clk;
input sig_in;
output sig_out;

reg sig_reg;

always @(posedge i_clk) begin
sig_reg <= sig_in;
end

assign sig_out = ~sig_in & sig_reg;

endmodule