data/full_repos/permissive/139213403/FPGA/front_panel_interface.v
 line:9: before: ")"
1: b"%Error: data/full_repos/permissive/139213403/FPGA/front_panel_interface.v:9: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: Exiting due to 1 error(s)\n"
module front_panel_interface
(
	input wire clk, reset,
	input wire[9:0] disp_w,
	input wire disp_en,
	
	
	
);

endmodule
module front_panel_interface
(
	input wire clk, reset,
	input wire[9:0] disp_w,
	input wire disp_en,
	
	
	
);


endmodule