data/full_repos/permissive/212981921/rtl/timer.v
data/verilator_xmls/cf5206c2-cae6-4c0e-b3a4-0bc1d95170f6.xml
module timer
#(
	parameter CLK_FREQ 		= 0,
	parameter DURATION_MS 	= 0
)
(
    input wire  _clk, _trigger,
    output reg  out
);

localparam TIMEOUT = (CLK_FREQ / 1000) * DURATION_MS;

reg [31:0] counter;

initial counter = 32'd0;

always @(negedge _clk) begin
    if (counter > 0) begin
        counter <= counter - 32'd1;
        if (counter == 32'd1) begin
            out <= 1'b0;
        end
    end else if (counter == 32'd0 && !_trigger) begin
        counter <= TIMEOUT;
        out <= 1'b1;
    end
end

endmodule
module timer
#(
	parameter CLK_FREQ 		= 0,
	parameter DURATION_MS 	= 0
)
(
    input wire  _clk, _trigger,
    output reg  out
);


localparam TIMEOUT = (CLK_FREQ / 1000) * DURATION_MS;

reg [31:0] counter;

initial counter = 32'd0;

always @(negedge _clk) begin
    if (counter > 0) begin
        counter <= counter - 32'd1;
        if (counter == 32'd1) begin
            out <= 1'b0;
        end
    end else if (counter == 32'd0 && !_trigger) begin
        counter <= TIMEOUT;
        out <= 1'b1;
    end
end

endmodule