data/full_repos/permissive/143278/ivltests/signed_part.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/signed_part.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/signed_part.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass = 1'b1;
  reg [14:-1] big = 16'h0123;

  reg signed [15:0] a;

  wire [3:0] w_big = big[a+:4];

  initial begin
    #1;


    a = -2;
    #1;
    if (w_big !== 4'b011x) begin
      $display("Failed: .part/v check, expected 4'b011x, got %b.", w_big);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass = 1'b1;
  reg [14:-1] big = 16'h0123;

  reg signed [15:0] a;

  wire [3:0] w_big = big[a+:4];

  initial begin
    #1;


    a = -2;
    #1;
    if (w_big !== 4'b011x) begin
      $display("Failed: .part/v check, expected 4'b011x, got %b.", w_big);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule