data/full_repos/permissive/137317945/MipsCPU/mips.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:13: Cannot find file containing module: 'controller'\n  controller U_CTR(clk,reset,opcode[31:26],opcode[5:0],GPRWr,GPRSel,BSel,Branch,\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137317945/MipsCPU,data/full_repos/permissive/137317945/controller\n             data/full_repos/permissive/137317945/MipsCPU,data/full_repos/permissive/137317945/controller.v\n             data/full_repos/permissive/137317945/MipsCPU,data/full_repos/permissive/137317945/controller.sv\n             controller\n             controller.v\n             controller.sv\n             obj_dir/controller\n             obj_dir/controller.v\n             obj_dir/controller.sv\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:16: Cannot find file containing module: 'alu'\n  alu        U_ALU(rd1,alub,Aluctrl,zero,sign,Aluresult,clk,sll,srl,sra,sllv,srlv,srav,opcode[10:6]);\n  ^~~\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:17: Cannot find file containing module: 'dm'\n  dm         U_DM(clk,DMWr,Aluresult,rd2,bes,bel,DMreg_data);\n  ^~\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:18: Cannot find file containing module: 'sign_ext'\n  sign_ext   U_SEXT(opcode[15:0],sign_ext);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:19: Cannot find file containing module: 'zero_ext'\n  zero_ext   U_ZEXT(opcode[15:0],zero_ext);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:20: Cannot find file containing module: 'im'\n  im         U_IM(clk,pcout,opcode,IRWr); \n  ^~\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:21: Cannot find file containing module: 'npc'\n  npc        U_NPC(pcout,Branch,zero,Jump,Jr,Jal,pcp4,npc,Aluresult,opcode[25:0],bne,blez,bgtz,bltz,bgez,rd1);\n  ^~~\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:22: Cannot find file containing module: 'pc'\n  pc         U_PC(clk,reset,npc,pcout,PCWr);\n  ^~\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:23: Cannot find file containing module: 'gpr'\n  gpr        U_GPR(clk,GPRWr,opcode[25:21],opcode[20:16],GPRw_addr,GPRw_data,rd1,rd2);\n  ^~~\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:24: Cannot find file containing module: 'be_save'\n  be_save    U_BES(sw,sb,sh,Aluresult[1:0],bes);\n  ^~~~~~~\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:25: Cannot find file containing module: 'be_load'\n  be_load    U_BEL(lw,lh,lhu,lb,lbu,Aluresult[1:0],bel);\n  ^~~~~~~\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:26: Cannot find file containing module: 'mux32'\n  mux32      U_BSel(rd2,zero_ext,sign_ext,0,BSel,alub);   \n  ^~~~~\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:27: Cannot find file containing module: 'mux32'\n  mux32      U_WDSel(Aluresult,DMreg_data,pcp4,sign,WDSel,GPRw_data);\n  ^~~~~\n%Error: data/full_repos/permissive/137317945/MipsCPU/mips.v:28: Cannot find file containing module: 'mux5'\n  mux5       U_GPRSel(opcode[20:16],opcode[15:11],5'b11111,GPRSel,GPRw_addr);\n  ^~~~\n%Error: Exiting due to 14 error(s)\n"
module mips(clk,reset);
  input            clk,reset;
  
  wire    [31:0]   rd1,rd2,sign_ext,zero_ext,GPRw_data,opcode,pcout,Aluresult,DMreg_data,alub,sign,npc,pcp4;
  wire    [6:0]    bel;
  wire    [4:0]    GPRw_addr;
  wire    [3:0]    bes;
  wire    [2:0]    Aluctrl;
  wire    [1:0]    WDSel,GPRSel,BSel;
  wire             GPRWr,Branch,DMWr,Jump,Jal,Jr,zero,PCWr,IRWr,sb,sh,sw,lb,lh;
  wire             lbu,lhu,lw,bne,blez,bgtz,bltz,bgez,sll,srl,sra,sllv,srlv,srav;
  
  controller U_CTR(clk,reset,opcode[31:26],opcode[5:0],GPRWr,GPRSel,BSel,Branch,
                   DMWr,WDSel,Jump,Jal,Jr,Aluctrl,PCWr,IRWr,sb,sh,sw,lb,lh,lbu,lhu,lw,bne,
                   blez,bgtz,bltz,bgez,opcode[20:16],zero,rd1,sll,srl,sra,sllv,srlv,srav);
  alu        U_ALU(rd1,alub,Aluctrl,zero,sign,Aluresult,clk,sll,srl,sra,sllv,srlv,srav,opcode[10:6]);
  dm         U_DM(clk,DMWr,Aluresult,rd2,bes,bel,DMreg_data);
  sign_ext   U_SEXT(opcode[15:0],sign_ext);
  zero_ext   U_ZEXT(opcode[15:0],zero_ext);
  im         U_IM(clk,pcout,opcode,IRWr); 
  npc        U_NPC(pcout,Branch,zero,Jump,Jr,Jal,pcp4,npc,Aluresult,opcode[25:0],bne,blez,bgtz,bltz,bgez,rd1);
  pc         U_PC(clk,reset,npc,pcout,PCWr);
  gpr        U_GPR(clk,GPRWr,opcode[25:21],opcode[20:16],GPRw_addr,GPRw_data,rd1,rd2);
  be_save    U_BES(sw,sb,sh,Aluresult[1:0],bes);
  be_load    U_BEL(lw,lh,lhu,lb,lbu,Aluresult[1:0],bel);
  mux32      U_BSel(rd2,zero_ext,sign_ext,0,BSel,alub);   
  mux32      U_WDSel(Aluresult,DMreg_data,pcp4,sign,WDSel,GPRw_data);
  mux5       U_GPRSel(opcode[20:16],opcode[15:11],5'b11111,GPRSel,GPRw_addr);
  
 endmodule
module mips(clk,reset);

  input            clk,reset;
  
  wire    [31:0]   rd1,rd2,sign_ext,zero_ext,GPRw_data,opcode,pcout,Aluresult,DMreg_data,alub,sign,npc,pcp4;
  wire    [6:0]    bel;
  wire    [4:0]    GPRw_addr;
  wire    [3:0]    bes;
  wire    [2:0]    Aluctrl;
  wire    [1:0]    WDSel,GPRSel,BSel;
  wire             GPRWr,Branch,DMWr,Jump,Jal,Jr,zero,PCWr,IRWr,sb,sh,sw,lb,lh;
  wire             lbu,lhu,lw,bne,blez,bgtz,bltz,bgez,sll,srl,sra,sllv,srlv,srav;
  
  controller U_CTR(clk,reset,opcode[31:26],opcode[5:0],GPRWr,GPRSel,BSel,Branch,
                   DMWr,WDSel,Jump,Jal,Jr,Aluctrl,PCWr,IRWr,sb,sh,sw,lb,lh,lbu,lhu,lw,bne,
                   blez,bgtz,bltz,bgez,opcode[20:16],zero,rd1,sll,srl,sra,sllv,srlv,srav);
  alu        U_ALU(rd1,alub,Aluctrl,zero,sign,Aluresult,clk,sll,srl,sra,sllv,srlv,srav,opcode[10:6]);
  dm         U_DM(clk,DMWr,Aluresult,rd2,bes,bel,DMreg_data);
  sign_ext   U_SEXT(opcode[15:0],sign_ext);
  zero_ext   U_ZEXT(opcode[15:0],zero_ext);
  im         U_IM(clk,pcout,opcode,IRWr); 
  npc        U_NPC(pcout,Branch,zero,Jump,Jr,Jal,pcp4,npc,Aluresult,opcode[25:0],bne,blez,bgtz,bltz,bgez,rd1);
  pc         U_PC(clk,reset,npc,pcout,PCWr);
  gpr        U_GPR(clk,GPRWr,opcode[25:21],opcode[20:16],GPRw_addr,GPRw_data,rd1,rd2);
  be_save    U_BES(sw,sb,sh,Aluresult[1:0],bes);
  be_load    U_BEL(lw,lh,lhu,lb,lbu,Aluresult[1:0],bel);
  mux32      U_BSel(rd2,zero_ext,sign_ext,0,BSel,alub);   
  mux32      U_WDSel(Aluresult,DMreg_data,pcp4,sign,WDSel,GPRw_data);
  mux5       U_GPRSel(opcode[20:16],opcode[15:11],5'b11111,GPRSel,GPRw_addr);
  
 endmodule