data/full_repos/permissive/136510272/projects/version.1.x8086/marsohod2.v
1: b"%Error: data/full_repos/permissive/136510272/projects/version.1.x8086/marsohod2.v:108: syntax error, unexpected '(', expecting IDENTIFIER\n    .clock      (clock),\n    ^\n%Error: Exiting due to 1 error(s)\n"
module marsohod2(


    input   wire        clk,


    output  wire [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,






    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse   
);


assign sound_left = clk;
assign sound_right = clock;
assign sdram_addr = o_addr;

wire locked;
wire clock;

wire        m_ready = 1'b1;
wire [19:0] o_addr;
wire [15:0] o_data;
wire        o_wr;



wire [15:0] i_data = o_addr[19:16] == 4'hC ? i_data_rom : 1'b0;





wire [15:0] i_data_rom;

rom ROM(

    .clock (clk), 
    .addr_rd(o_addr[14:1]),
    .q(i_data_rom)

);



pll PLL(

    .clk        (clk),
    .locked     (locked),
    .clock      (clock)


);











processor(

    .clock      (clock),
    .locked     (locked),
    
    .m_ready    (m_ready),
    .o_addr     (o_addr),
    .i_data     (i_data),
    .o_data     (o_data),
    .o_wr       (o_wr)
        
);

endmodule
module marsohod2(


    input   wire        clk,


    output  wire [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,






    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse   
);



assign sound_left = clk;
assign sound_right = clock;
assign sdram_addr = o_addr;

wire locked;
wire clock;

wire        m_ready = 1'b1;
wire [19:0] o_addr;
wire [15:0] o_data;
wire        o_wr;



wire [15:0] i_data = o_addr[19:16] == 4'hC ? i_data_rom : 1'b0;





wire [15:0] i_data_rom;

rom ROM(

    .clock (clk), 
    .addr_rd(o_addr[14:1]),
    .q(i_data_rom)

);



pll PLL(

    .clk        (clk),
    .locked     (locked),
    .clock      (clock)


);











processor(

    .clock      (clock),
    .locked     (locked),
    
    .m_ready    (m_ready),
    .o_addr     (o_addr),
    .i_data     (i_data),
    .o_data     (o_data),
    .o_wr       (o_wr)
        
);

endmodule