data/full_repos/permissive/206783267/I2S/TB/i2s_master_tb.v
 line:27: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206783267/I2S/TB/i2s_master_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n forever #(CLK_CYCLE/2) clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/206783267/I2S/TB/i2s_master_tb.v:26: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: data/full_repos/permissive/206783267/I2S/TB/i2s_master_tb.v:32: syntax error, unexpected \'@\'\n @(negedge ws);\n ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module i2s_master_tb();

parameter	CLK_DIV = 256,
			WS_DIV = 64,
			DATA_WIDTH = 24,
			CLK_CYCLE = 20;

reg	clk, arstn;
wire	sck, ws;
reg	sdi;
wire	sdo;
reg	[DATA_WIDTH-1:0]	data_send_left, data_send_right;
wire	[DATA_WIDTH-1:0]	data_recv_left, data_recv_right;


initial begin
	clk = 0;
	forever	#(CLK_CYCLE/2)	clk = ~clk;
end


initial begin
	arstn = 1'b0;
	@(posedge clk)
		#(CLK_CYCLE*50)	arstn = 1'b1;
end


initial begin
	@(negedge ws);
	@(negedge ws)
		#(CLK_CYCLE*50)	$finish;
end


initial begin
	data_send_left = 24'h123456;
	data_send_right = 24'habcdef;
end


initial begin
	sdi = 1'b0;
end
always@(negedge sck) begin
	sdi = $random;
end

i2s_master
#(
	.CLK_DIV(CLK_DIV),
	.WS_DIV(WS_DIV),
	.DATA_WIDTH(DATA_WIDTH)
)
DUT(
	.clk(clk),
	.arstn(arstn),
	.sck(sck),
	.ws(ws),
	.sdi(sdi),
	.sdo(sdo),
	.data_send_left(data_send_left),
	.data_send_right(data_send_right),
	.data_recv_left(data_recv_left),
	.data_recv_right(data_recv_right)
);

endmodule
module i2s_master_tb();


parameter	CLK_DIV = 256,
			WS_DIV = 64,
			DATA_WIDTH = 24,
			CLK_CYCLE = 20;

reg	clk, arstn;
wire	sck, ws;
reg	sdi;
wire	sdo;
reg	[DATA_WIDTH-1:0]	data_send_left, data_send_right;
wire	[DATA_WIDTH-1:0]	data_recv_left, data_recv_right;


initial begin
	clk = 0;
	forever	#(CLK_CYCLE/2)	clk = ~clk;
end


initial begin
	arstn = 1'b0;
	@(posedge clk)
		#(CLK_CYCLE*50)	arstn = 1'b1;
end


initial begin
	@(negedge ws);
	@(negedge ws)
		#(CLK_CYCLE*50)	$finish;
end


initial begin
	data_send_left = 24'h123456;
	data_send_right = 24'habcdef;
end


initial begin
	sdi = 1'b0;
end
always@(negedge sck) begin
	sdi = $random;
end

i2s_master
#(
	.CLK_DIV(CLK_DIV),
	.WS_DIV(WS_DIV),
	.DATA_WIDTH(DATA_WIDTH)
)
DUT(
	.clk(clk),
	.arstn(arstn),
	.sck(sck),
	.ws(ws),
	.sdi(sdi),
	.sdo(sdo),
	.data_send_left(data_send_left),
	.data_send_right(data_send_right),
	.data_recv_left(data_recv_left),
	.data_recv_right(data_recv_right)
);

endmodule