data/full_repos/permissive/210844779/lab7/7.3/booth_multi.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/210844779/lab7/7.3/booth_multi.v:12: Cannot find file containing module: 'add_sub'\nadd_sub u0(ta,z,0,add);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab7/7.3,data/full_repos/permissive/210844779/add_sub\n             data/full_repos/permissive/210844779/lab7/7.3,data/full_repos/permissive/210844779/add_sub.v\n             data/full_repos/permissive/210844779/lab7/7.3,data/full_repos/permissive/210844779/add_sub.sv\n             add_sub\n             add_sub.v\n             add_sub.sv\n             obj_dir/add_sub\n             obj_dir/add_sub.v\n             obj_dir/add_sub.sv\n%Error: data/full_repos/permissive/210844779/lab7/7.3/booth_multi.v:13: Cannot find file containing module: 'add_sub'\nadd_sub u1(~ta,z,1,sub);\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module multi(a,b,clk,out,load);
  input [3:0] a,b;
  input clk,load;
  output [7:0]out;

reg [3:0]ta,tb,z;
reg q;
reg [3:0] count;

wire [3:0]add,sub;

add_sub u0(ta,z,0,add);
add_sub u1(~ta,z,1,sub);

always@(posedge clk)
begin
  if (load)
    begin
      ta<=a;
      tb<=b;
      z<=4'b0000;
      q<=0;
      count<=0;
  end
  
else
  begin
    if (count<4)
      begin
    case ({tb[0],q})
      2'b00 : {z,tb,q} <= {z[3],z,tb};
      2'b01 : {z,tb,q} <= {add[3],add,tb};
      2'b10 : {z,tb,q} <= {sub[3],sub,tb};
      2'b11 : {z,tb,q} <= {z[3],z,tb};
    endcase
    count<= count + 1'b1;
  end
end
end
assign out = {z,tb};

endmodule
module multi(a,b,clk,out,load);

  input [3:0] a,b;
  input clk,load;
  output [7:0]out;

reg [3:0]ta,tb,z;
reg q;
reg [3:0] count;

wire [3:0]add,sub;

add_sub u0(ta,z,0,add);
add_sub u1(~ta,z,1,sub);

always@(posedge clk)
begin
  if (load)
    begin
      ta<=a;
      tb<=b;
      z<=4'b0000;
      q<=0;
      count<=0;
  end
  
else
  begin
    if (count<4)
      begin
    case ({tb[0],q})
      2'b00 : {z,tb,q} <= {z[3],z,tb};
      2'b01 : {z,tb,q} <= {add[3],add,tb};
      2'b10 : {z,tb,q} <= {sub[3],sub,tb};
      2'b11 : {z,tb,q} <= {z[3],z,tb};
    endcase
    count<= count + 1'b1;
  end
end
end
assign out = {z,tb};

endmodule