data/full_repos/permissive/169258653/multicycle/MIPS_multi_cycle_32bit/MIPS_multi_cycle_32bit.srcs/sources_1/new/controller.v
1: b"%Error: data/full_repos/permissive/169258653/multicycle/MIPS_multi_cycle_32bit/MIPS_multi_cycle_32bit.srcs/sources_1/new/controller.v:48: Cannot find file containing module: 'maindec'\n    maindec md(clk,reset,op,pcwrite,memwrite,irwrite,regwrite,\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169258653/multicycle/MIPS_multi_cycle_32bit/MIPS_multi_cycle_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/maindec\n             data/full_repos/permissive/169258653/multicycle/MIPS_multi_cycle_32bit/MIPS_multi_cycle_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/maindec.v\n             data/full_repos/permissive/169258653/multicycle/MIPS_multi_cycle_32bit/MIPS_multi_cycle_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/maindec.sv\n             maindec\n             maindec.v\n             maindec.sv\n             obj_dir/maindec\n             obj_dir/maindec.v\n             obj_dir/maindec.sv\n%Error: data/full_repos/permissive/169258653/multicycle/MIPS_multi_cycle_32bit/MIPS_multi_cycle_32bit.srcs/sources_1/new/controller.v:54: Cannot find file containing module: 'aludec'\n    aludec ad(funct, aluop, alucontrol,lights[23:20]);\n    ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module controller(
    input clk,reset,
    input next,stop,lightsrc,
    input [5:0] op,funct,
    input zero,
    output iord,memwrite,irwrite,
    output [1:0] regdst,
    output memtoreg,regwrite,
    output [1:0] alusrca,
    output [1:0] alusrcb,
    output [3:0] alucontrol,
    output [1:0] pcsrc,
    output reg pcen,
    output reg [15:0] discu,
    output extend,
    output extsrc,
    input [9:0] swt,
    output [31:0] t,
    output [7:0] disop
    );
    
    wire pcwrite, branch;
    wire [2:0] aluop;
    wire [24:0] lights;
    
    maindec md(clk,reset,op,pcwrite,memwrite,irwrite,regwrite,
               alusrca,branch,iord,memtoreg,regdst,
               alusrcb,pcsrc,aluop,
               lights[19:0],extend,extsrc,funct,
               swt,t,disop);
        
    aludec ad(funct, aluop, alucontrol,lights[23:20]);
    

    always@(*)
    if(op==6'b000101)
        pcen<=(branch&(~zero))|pcwrite;
    else
        pcen<=(branch&zero)|pcwrite;
        
    assign lights[24]=pcen;
    
    always@(*)
    if(lightsrc)
        discu<={next,stop,lightsrc,reset,clk,2'b0,lights[24:16]};
    else
        discu<=lights[15:0];
        
endmodule
module controller(
    input clk,reset,
    input next,stop,lightsrc,
    input [5:0] op,funct,
    input zero,
    output iord,memwrite,irwrite,
    output [1:0] regdst,
    output memtoreg,regwrite,
    output [1:0] alusrca,
    output [1:0] alusrcb,
    output [3:0] alucontrol,
    output [1:0] pcsrc,
    output reg pcen,
    output reg [15:0] discu,
    output extend,
    output extsrc,
    input [9:0] swt,
    output [31:0] t,
    output [7:0] disop
    );

    
    wire pcwrite, branch;
    wire [2:0] aluop;
    wire [24:0] lights;
    
    maindec md(clk,reset,op,pcwrite,memwrite,irwrite,regwrite,
               alusrca,branch,iord,memtoreg,regdst,
               alusrcb,pcsrc,aluop,
               lights[19:0],extend,extsrc,funct,
               swt,t,disop);
        
    aludec ad(funct, aluop, alucontrol,lights[23:20]);
    

    always@(*)
    if(op==6'b000101)
        pcen<=(branch&(~zero))|pcwrite;
    else
        pcen<=(branch&zero)|pcwrite;
        
    assign lights[24]=pcen;
    
    always@(*)
    if(lightsrc)
        discu<={next,stop,lightsrc,reset,clk,2'b0,lights[24:16]};
    else
        discu<=lights[15:0];
        
endmodule