data/full_repos/permissive/143278/ivltests/memport_bs.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memport_bs.v:55: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/memport_bs.v:54: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 3 bits.\n                                                                          : ... In instance pr303\n for (a=0; a<7; a=a+1) mem[a] <= a;\n                              ^~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pr303;

   reg [3:0]  mem [2:5];

`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
   wire [3:0] m1 = mem[1];
`else
   wire [3:0] m1 = 4'bxxxx;
`endif
   wire [3:0] m2 = mem[2];
   wire [3:0] m3 = mem[3];
   wire [3:0] m4 = mem[4];
   wire [3:0] m5 = mem[5];
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
   wire [3:0] m6 = mem[6];
`else
   wire [3:0] m6 = 4'bxxxx;
`endif

   reg [2:0]  a;
   reg [3:0]  e;

   initial
     begin
	e = 0;
	for (a=0; a<7; a=a+1) mem[a] <= a;
	#1;
	if (   m1  !== 4'hx) begin e=e+1; $display("FAILED    m1=%b",     m1 ); end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
	if (mem[1] !== 4'hx) begin e=e+1; $display("FAILED mem[1]=%b", mem[1]); end
`endif
	if (   m2  !== 4'h2) begin e=e+1; $display("FAILED    m2=%b",     m2 ); end
	if (mem[2] !== 4'h2) begin e=e+1; $display("FAILED mem[2]=%b", mem[2]); end
	if (   m3  !== 4'h3) begin e=e+1; $display("FAILED    m3=%b",     m3 ); end
	if (mem[3] !== 4'h3) begin e=e+1; $display("FAILED mem[3]=%b", mem[3]); end
	if (   m4  !== 4'h4) begin e=e+1; $display("FAILED    m4=%b",     m4 ); end
	if (mem[4] !== 4'h4) begin e=e+1; $display("FAILED mem[4]=%b", mem[4]); end
	if (   m5  !== 4'h5) begin e=e+1; $display("FAILED    m5=%b",     m5 ); end
	if (mem[5] !== 4'h5) begin e=e+1; $display("FAILED mem[5]=%b", mem[5]); end
	if (   m6  !== 4'hx) begin e=e+1; $display("FAILED    m6=%b",     m6 ); end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
	if (mem[6] !== 4'hx) begin e=e+1; $display("FAILED mem[6]=%b", mem[6]); end
`endif
	if (e===0) $display("PASSED");
     end
endmodule
module pr303;


   reg [3:0]  mem [2:5];

`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
   wire [3:0] m1 = mem[1];
`else
   wire [3:0] m1 = 4'bxxxx;
`endif
   wire [3:0] m2 = mem[2];
   wire [3:0] m3 = mem[3];
   wire [3:0] m4 = mem[4];
   wire [3:0] m5 = mem[5];
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
   wire [3:0] m6 = mem[6];
`else
   wire [3:0] m6 = 4'bxxxx;
`endif

   reg [2:0]  a;
   reg [3:0]  e;

   initial
     begin
	e = 0;
	for (a=0; a<7; a=a+1) mem[a] <= a;
	#1;
	if (   m1  !== 4'hx) begin e=e+1; $display("FAILED    m1=%b",     m1 ); end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
	if (mem[1] !== 4'hx) begin e=e+1; $display("FAILED mem[1]=%b", mem[1]); end
`endif
	if (   m2  !== 4'h2) begin e=e+1; $display("FAILED    m2=%b",     m2 ); end
	if (mem[2] !== 4'h2) begin e=e+1; $display("FAILED mem[2]=%b", mem[2]); end
	if (   m3  !== 4'h3) begin e=e+1; $display("FAILED    m3=%b",     m3 ); end
	if (mem[3] !== 4'h3) begin e=e+1; $display("FAILED mem[3]=%b", mem[3]); end
	if (   m4  !== 4'h4) begin e=e+1; $display("FAILED    m4=%b",     m4 ); end
	if (mem[4] !== 4'h4) begin e=e+1; $display("FAILED mem[4]=%b", mem[4]); end
	if (   m5  !== 4'h5) begin e=e+1; $display("FAILED    m5=%b",     m5 ); end
	if (mem[5] !== 4'h5) begin e=e+1; $display("FAILED mem[5]=%b", mem[5]); end
	if (   m6  !== 4'hx) begin e=e+1; $display("FAILED    m6=%b",     m6 ); end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
	if (mem[6] !== 4'hx) begin e=e+1; $display("FAILED mem[6]=%b", mem[6]); end
`endif
	if (e===0) $display("PASSED");
     end
endmodule