data/full_repos/permissive/140976142/sim/tx_sim.v
Syntax Error
1: b'%Error: data/full_repos/permissive/140976142/sim/tx_sim.v:11: Cannot find include file: ../rtl/util.vh\n `include "../rtl/util.vh" \n          ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/140976142/sim,data/full_repos/permissive/140976142/../rtl/util.vh\n             data/full_repos/permissive/140976142/sim,data/full_repos/permissive/140976142/../rtl/util.vh.v\n             data/full_repos/permissive/140976142/sim,data/full_repos/permissive/140976142/../rtl/util.vh.sv\n             ../rtl/util.vh\n             ../rtl/util.vh.v\n             ../rtl/util.vh.sv\n             obj_dir/../rtl/util.vh\n             obj_dir/../rtl/util.vh.v\n             obj_dir/../rtl/util.vh.sv\n%Error: data/full_repos/permissive/140976142/sim/tx_sim.v:48: syntax error, unexpected \'@\'\n    @(posedge eth_clkin); #0.001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/140976142/sim/tx_sim.v:48: Unsupported: Ignoring delay on this delayed statement.\n    @(posedge eth_clkin); #0.001;\n                          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/140976142/sim/tx_sim.v:74: syntax error, unexpected \'@\'\n    @(posedge eth_clkin); #0.001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/140976142/sim/tx_sim.v:74: Unsupported: Ignoring delay on this delayed statement.\n    @(posedge eth_clkin); #0.001;\n                          ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module tx_sim
(   
	input       eth_rstn,
	input       eth_clkin,
	input       eth_txen,
	input [1:0] eth_txd
);

	`include "../rtl/util.vh"
	
	reg         crc_rst;
	reg         crc_vld;
	reg  [7:0]  crc_dat;
	wire [31:0] crc_code;
	wire [31:0] crc_bswap = bswap32(crc_code);
	crc32 crc32_inst
	(
		.clk (eth_clkin),
		.rst (crc_rst),
		.vld (crc_vld),
		.data(crc_dat),
		.crc (crc_code)
	);
	
	reg verbose = 1;
	task set_verbose;
		input verbose_;
		begin
			verbose = verbose_;
		end
	endtask
	
	reg [31:0] test;
	
	task recv;
		output [1522 * 8 - 1 : 0] data;
		output [10:0]             len;
		output                    err;
		integer i, b;
		reg [7:0]  byte_buf;
		reg [63:0] preamble_buffer;
		begin
			preamble_buffer = 0;
			while(preamble_buffer != 64'hd555555555555555) begin
				preamble_buffer = eth_txen ? {eth_txd, preamble_buffer[63:2]} : 0;
				@(posedge eth_clkin); #0.001;
			end
			
			if(verbose)
				$display("TX SOF");
			
			crc_rst = 1;
			crc_vld = 0;
			i       = 0;
			b       = 0;
			while(eth_txen) begin
				byte_buf = {eth_txd, byte_buf[7:2]};
				b = b + 1;
				
				if(b == 4) begin
					if(i >= 4) begin
						crc_vld = 1;
						crc_dat = data[(i - 4) * 8 +: 8];
					end
					data[i * 8 +: 8] = byte_buf;
					b = 0;
					if(verbose)
						$display("TX DATA[%d] = %h", i, byte_buf);
					i = i + 1;
				end
				
				@(posedge eth_clkin); #0.001;
				crc_rst = 0;
				crc_vld = 0;
			end
			
			len = i;
			err = 0;
			
			if(verbose) begin
				$display("TX CRC          = %h", data[(i - 4) * 8 +: 32]);
				$display("TX EXPECTED CRC = %h", crc_bswap);
			end
			
			if(b != 0) begin
				if(verbose) 
					$display("TX INCOMPLETE TRANSMIT");
				err = 1;
			end else if(i < 68) begin
				if(verbose)
					$display("TX FRAME TOO SHORT");
				err = 1;
			end else if(crc_bswap != data[(i - 4) * 8 +: 32]) begin
				if(verbose)
					$display("TX CRC FAIL");
				err = 1;
			end else begin
				if(verbose)
					$display("TX EOF");
			end
		end
	endtask
	
endmodule
module tx_sim
(   
	input       eth_rstn,
	input       eth_clkin,
	input       eth_txen,
	input [1:0] eth_txd
);


	`include "../rtl/util.vh"
	
	reg         crc_rst;
	reg         crc_vld;
	reg  [7:0]  crc_dat;
	wire [31:0] crc_code;
	wire [31:0] crc_bswap = bswap32(crc_code);
	crc32 crc32_inst
	(
		.clk (eth_clkin),
		.rst (crc_rst),
		.vld (crc_vld),
		.data(crc_dat),
		.crc (crc_code)
	);
	
	reg verbose = 1;
	task set_verbose;
		input verbose_;
		begin
			verbose = verbose_;
		end
	endtask
	
	reg [31:0] test;
	
	task recv;
		output [1522 * 8 - 1 : 0] data;
		output [10:0]             len;
		output                    err;
		integer i, b;
		reg [7:0]  byte_buf;
		reg [63:0] preamble_buffer;
		begin
			preamble_buffer = 0;
			while(preamble_buffer != 64'hd555555555555555) begin
				preamble_buffer = eth_txen ? {eth_txd, preamble_buffer[63:2]} : 0;
				@(posedge eth_clkin); #0.001;
			end
			
			if(verbose)
				$display("TX SOF");
			
			crc_rst = 1;
			crc_vld = 0;
			i       = 0;
			b       = 0;
			while(eth_txen) begin
				byte_buf = {eth_txd, byte_buf[7:2]};
				b = b + 1;
				
				if(b == 4) begin
					if(i >= 4) begin
						crc_vld = 1;
						crc_dat = data[(i - 4) * 8 +: 8];
					end
					data[i * 8 +: 8] = byte_buf;
					b = 0;
					if(verbose)
						$display("TX DATA[%d] = %h", i, byte_buf);
					i = i + 1;
				end
				
				@(posedge eth_clkin); #0.001;
				crc_rst = 0;
				crc_vld = 0;
			end
			
			len = i;
			err = 0;
			
			if(verbose) begin
				$display("TX CRC          = %h", data[(i - 4) * 8 +: 32]);
				$display("TX EXPECTED CRC = %h", crc_bswap);
			end
			
			if(b != 0) begin
				if(verbose) 
					$display("TX INCOMPLETE TRANSMIT");
				err = 1;
			end else if(i < 68) begin
				if(verbose)
					$display("TX FRAME TOO SHORT");
				err = 1;
			end else if(crc_bswap != data[(i - 4) * 8 +: 32]) begin
				if(verbose)
					$display("TX CRC FAIL");
				err = 1;
			end else begin
				if(verbose)
					$display("TX EOF");
			end
		end
	endtask
	
endmodule