data/full_repos/permissive/143278/ivltests/pr734.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr734.v:11: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 69120 bits.\n                                                                     : ... In instance test\n        r = mem >> idx;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module test;
    parameter idx = 3584;
    reg [69119:0] mem;
    reg r;
    initial begin
        mem[idx] = 1;
        r = mem >> idx;
        if (r !== 1)
            $display("FAILED r = %b", r);
        else
            $display("PASSED");
    end
endmodule
module test;

    parameter idx = 3584;
    reg [69119:0] mem;
    reg r;
    initial begin
        mem[idx] = 1;
        r = mem >> idx;
        if (r !== 1)
            $display("FAILED r = %b", r);
        else
            $display("PASSED");
    end
endmodule