data/full_repos/permissive/157049472/Verilog Test Benches/TopModule_tb.v
1: b'%Error: Cannot find file containing module: Test\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Test\n             data/full_repos/permissive/157049472/Verilog/Test.v\n             data/full_repos/permissive/157049472/Verilog/Test.sv\n             Test\n             Test.v\n             Test.sv\n             obj_dir/Test\n             obj_dir/Test.v\n             obj_dir/Test.sv\n%Error: Cannot find file containing module: Benches,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Benches/TopModule_tb.v\n%Error: Exiting due to 4 error(s)\n'
module TopModule_tb;


	reg clk;
	reg rst;


	wire instruction_bit;
	wire alu_result_bit;
	wire jump_offset_bit;
	wire pc_bit;


	TopModule uut (
		.clk(clk), 
		.rst(rst), 
		.instruction_bit(instruction_bit), 
		.alu_result_bit(alu_result_bit), 
		.jump_offset_bit(jump_offset_bit), 
		.pc_bit(pc_bit)
	);

	initial begin

		clk = 0;
		rst = 0;



		#1;		

        

		rst = 1;
		#2 rst = 0;

	end
	always begin
		#1 clk = ~clk;
	end
	
      
endmodule
module TopModule_tb;



	reg clk;
	reg rst;


	wire instruction_bit;
	wire alu_result_bit;
	wire jump_offset_bit;
	wire pc_bit;


	TopModule uut (
		.clk(clk), 
		.rst(rst), 
		.instruction_bit(instruction_bit), 
		.alu_result_bit(alu_result_bit), 
		.jump_offset_bit(jump_offset_bit), 
		.pc_bit(pc_bit)
	);

	initial begin

		clk = 0;
		rst = 0;



		#1;		

        

		rst = 1;
		#2 rst = 0;

	end
	always begin
		#1 clk = ~clk;
	end
	
      
endmodule