data/full_repos/permissive/129797190/rtl/cpu/regs.v
1: b'%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/regs.v:30: Bit extraction of array[63:0] requires 6 bit index, not 9 bits.\n                                                                      : ... In instance regs\n            rs1_value_out <= regs[rs1_in];\n                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/regs.v:31: Bit extraction of array[63:0] requires 6 bit index, not 9 bits.\n                                                                      : ... In instance regs\n            rs2_value_out <= regs[rs2_in];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/regs.v:35: Bit extraction of array[63:0] requires 6 bit index, not 9 bits.\n                                                                      : ... In instance regs\n            regs[rd_in] <= rd_value_in;\n                ^\n%Error: Exiting due to 3 warning(s)\n'
module regs (
    input clk,
    input stall_in,

    input [8:0] rs1_in,
    input [8:0] rs2_in,
    input [8:0] rd_in,
    input rd_write_in,

    input [63:0] rd_value_in,

    output reg [63:0] rs1_value_out,
    output reg [63:0] rs2_value_out
);
    reg [63:0] regs [63:0];

    generate
        genvar i;
        for (i = 0; i < 64; i = i+1) begin
            initial
                regs[i] <= 0;
        end
    endgenerate

    always @(posedge clk) begin
        if (!stall_in) begin
            rs1_value_out <= regs[rs1_in];
            rs2_value_out <= regs[rs2_in];
        end

        if (rd_write_in && |rd_in)
            regs[rd_in] <= rd_value_in;
    end
endmodule
module regs (
    input clk,
    input stall_in,

    input [8:0] rs1_in,
    input [8:0] rs2_in,
    input [8:0] rd_in,
    input rd_write_in,

    input [63:0] rd_value_in,

    output reg [63:0] rs1_value_out,
    output reg [63:0] rs2_value_out
);

    reg [63:0] regs [63:0];

    generate
        genvar i;
        for (i = 0; i < 64; i = i+1) begin
            initial
                regs[i] <= 0;
        end
    endgenerate

    always @(posedge clk) begin
        if (!stall_in) begin
            rs1_value_out <= regs[rs1_in];
            rs2_value_out <= regs[rs2_in];
        end

        if (rd_write_in && |rd_in)
            regs[rd_in] <= rd_value_in;
    end
endmodule