data/full_repos/permissive/196851857/control/ctrl.v
None: at end of input
1: b'%Error: data/full_repos/permissive/196851857/control/ctrl.v:1: Cannot find include file: ctrl_signals_def.v\n`include "ctrl_signals_def.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/196851857/control,data/full_repos/permissive/196851857/ctrl_signals_def.v\n             data/full_repos/permissive/196851857/control,data/full_repos/permissive/196851857/ctrl_signals_def.v.v\n             data/full_repos/permissive/196851857/control,data/full_repos/permissive/196851857/ctrl_signals_def.v.sv\n             ctrl_signals_def.v\n             ctrl_signals_def.v.v\n             ctrl_signals_def.v.sv\n             obj_dir/ctrl_signals_def.v\n             obj_dir/ctrl_signals_def.v.v\n             obj_dir/ctrl_signals_def.v.sv\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:24: Define or directive not defined: \'`Most_R_Type_op\'\n  if (opcode == `Most_R_Type_op) begin\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if (opcode == `Most_R_Type_op) begin\n                               ^\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:26: Define or directive not defined: \'`True\'\n    RegWrite = `True;\n               ^~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:30: Define or directive not defined: \'`RwIdSrc_rd\'\n    RwIdSrc = `RwIdSrc_rd;\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    RwIdSrc = `RwIdSrc_rd;\n                         ^\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:32: Define or directive not defined: \'`False\'\n                                                              : ... Suggested alternative: \'`else\'\n    MemRead = `False; MemWrite = `False;  \n              ^~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    MemRead = `False; MemWrite = `False;  \n                    ^\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:32: Define or directive not defined: \'`False\'\n                                                              : ... Suggested alternative: \'`else\'\n    MemRead = `False; MemWrite = `False;  \n                                 ^~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    MemRead = `False; MemWrite = `False;  \n                                       ^\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:34: Define or directive not defined: \'`no_branch\'\n    BranchType = `no_branch;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:34: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    BranchType = `no_branch;\n                           ^\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:36: Define or directive not defined: \'`funct_jr\'\n    if (funct == `funct_jr || funct == `funct_jalr) begin\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:36: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n    if (funct == `funct_jr || funct == `funct_jalr) begin\n                           ^~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:36: Define or directive not defined: \'`funct_jalr\'\n    if (funct == `funct_jr || funct == `funct_jalr) begin\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:37: Define or directive not defined: \'`RegTypeJump\'\n      JumpType = `RegTypeJump; RwDataSrc = `RwDataSrc_pc1;\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:37: Define or directive not defined: \'`RwDataSrc_pc1\'\n      JumpType = `RegTypeJump; RwDataSrc = `RwDataSrc_pc1;\n                                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:37: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      JumpType = `RegTypeJump; RwDataSrc = `RwDataSrc_pc1;\n                                                         ^\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:39: Define or directive not defined: \'`No_Jump\'\n      JumpType = `No_Jump; RwDataSrc =`RwDataSrc_alu;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:39: Define or directive not defined: \'`RwDataSrc_alu\'\n      JumpType = `No_Jump; RwDataSrc =`RwDataSrc_alu;\n                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:43: Define or directive not defined: \'`aluBsrc_rt\'\n    AluBSrc = `aluBsrc_rt;\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:45: Define or directive not defined: \'`funct_addu\'\n      `funct_addu : AluCtr = `alu_addu;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:45: syntax error, unexpected \':\', expecting endcase\n      `funct_addu : AluCtr = `alu_addu;\n                  ^\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:45: Define or directive not defined: \'`alu_addu\'\n      `funct_addu : AluCtr = `alu_addu;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:46: Define or directive not defined: \'`funct_subu\'\n      `funct_subu : AluCtr = `alu_subu;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:46: Define or directive not defined: \'`alu_subu\'\n      `funct_subu : AluCtr = `alu_subu;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:47: Define or directive not defined: \'`funct_slt\'\n      `funct_slt : AluCtr = `alu_slt;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:47: Define or directive not defined: \'`alu_slt\'\n      `funct_slt : AluCtr = `alu_slt;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:48: Define or directive not defined: \'`funct_and\'\n      `funct_and : AluCtr = `alu_and;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:48: Define or directive not defined: \'`alu_and\'\n      `funct_and : AluCtr = `alu_and;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:49: Define or directive not defined: \'`funct_nor\'\n      `funct_nor : AluCtr = `alu_nor;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:49: Define or directive not defined: \'`alu_nor\'\n      `funct_nor : AluCtr = `alu_nor;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:50: Define or directive not defined: \'`funct_or\'\n      `funct_or : AluCtr = `alu_or;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:50: Define or directive not defined: \'`alu_or\'\n      `funct_or : AluCtr = `alu_or;\n                           ^~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:51: Define or directive not defined: \'`funct_xor\'\n      `funct_xor : AluCtr = `alu_xor;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:51: Define or directive not defined: \'`alu_xor\'\n      `funct_xor : AluCtr = `alu_xor;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:52: Define or directive not defined: \'`funct_sltu\'\n      `funct_sltu : AluCtr = `alu_sltu;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:52: Define or directive not defined: \'`alu_sltu\'\n      `funct_sltu : AluCtr = `alu_sltu;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:53: Define or directive not defined: \'`funct_sllv\'\n      `funct_sllv : AluCtr = `alu_sllv;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:53: Define or directive not defined: \'`alu_sllv\'\n      `funct_sllv : AluCtr = `alu_sllv;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:54: Define or directive not defined: \'`funct_srav\'\n      `funct_srav : AluCtr = `alu_srav;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:54: Define or directive not defined: \'`alu_srav\'\n      `funct_srav : AluCtr = `alu_srav;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:55: Define or directive not defined: \'`funct_srlv\'\n      `funct_srlv : AluCtr = `alu_srlv;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:55: Define or directive not defined: \'`alu_srlv\'\n      `funct_srlv : AluCtr = `alu_srlv;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:56: Define or directive not defined: \'`funct_sll\'\n      `funct_sll : AluCtr = `alu_sll;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:56: Define or directive not defined: \'`alu_sll\'\n      `funct_sll : AluCtr = `alu_sll;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:57: Define or directive not defined: \'`funct_srl\'\n      `funct_srl : AluCtr = `alu_srl;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:57: Define or directive not defined: \'`alu_srl\'\n      `funct_srl : AluCtr = `alu_srl;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:58: Define or directive not defined: \'`funct_sra\'\n      `funct_sra : AluCtr = `alu_sra;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/control/ctrl.v:58: Define or directive not defined: \'`alu_sra\'\n      `funct_sra : AluCtr = `alu_sra;\n                            ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ctrl(
  input [5:0] opcode, funct,
  input bit16,

  output reg RegWrite,
  output reg [1:0] RwIdSrc, RwDataSrc,

  output reg MemRead, MemWrite, MemOpType,

  output reg [2:0] BranchType,
  output reg [1:0] JumpType,

  output reg [4:0] AluCtr,
  output reg [1:0] AluBSrc,
  
  output reg ExtType, MemDataExtType
);



always@(opcode or funct or bit16)
begin
  if (opcode == `Most_R_Type_op) begin

    RegWrite = `True;



    RwIdSrc = `RwIdSrc_rd;

    MemRead = `False; MemWrite = `False;

    BranchType = `no_branch;

    if (funct == `funct_jr || funct == `funct_jalr) begin
      JumpType = `RegTypeJump; RwDataSrc = `RwDataSrc_pc1;
    end else begin
      JumpType = `No_Jump; RwDataSrc =`RwDataSrc_alu;
    end


    AluBSrc = `aluBsrc_rt;
    case (funct)
      `funct_addu : AluCtr = `alu_addu;
      `funct_subu : AluCtr = `alu_subu;
      `funct_slt : AluCtr = `alu_slt;
      `funct_and : AluCtr = `alu_and;
      `funct_nor : AluCtr = `alu_nor;
      `funct_or : AluCtr = `alu_or;
      `funct_xor : AluCtr = `alu_xor;
      `funct_sltu : AluCtr = `alu_sltu;
      `funct_sllv : AluCtr = `alu_sllv;
      `funct_srav : AluCtr = `alu_srav;
      `funct_srlv : AluCtr = `alu_srlv;
      `funct_sll : AluCtr = `alu_sll;
      `funct_srl : AluCtr = `alu_srl;
      `funct_sra : AluCtr = `alu_sra;
      `funct_jr : AluCtr = `alu_nop;
      `funct_jalr : AluCtr = `alu_nop;
      default: AluCtr = `alu_nop;

    endcase

    ExtType = `ZeroExt;

  end else if (opcode == `bgez_bltz_op) begin


    RegWrite = `False;
    MemRead = `False; MemWrite = `False;
    BranchType = (bit16 == `bit16_bgez) ? `branch_bgez : `branch_bltz;
    JumpType = `OffsetTypeJump;
    AluBSrc = `aluBsrc_zero; AluCtr = `alu_subu;
    ExtType = `SignExt;
  end else begin

    case (opcode)
      `opcode_addiu:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_addu;
          AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt;
        end
      `opcode_lui:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_lui;
          AluBSrc = `aluBsrc_imm00;
          ExtType = `ZeroExt;
        end
      `opcode_slti:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt;  RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_slt;
          AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt;
        end
      `opcode_sltiu:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt;  RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_sltu;
          AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt;
        end
      `opcode_andi:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_and;
          AluBSrc = `aluBsrc_imm;
          ExtType = `ZeroExt;
        end
      `opcode_ori:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_or;
          AluBSrc = `aluBsrc_imm;
          ExtType = `ZeroExt;
        end
      `opcode_xori:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_xor;
          AluBSrc = `aluBsrc_imm;
          ExtType = `ZeroExt;
        end
      `opcode_beq:
        begin
          RegWrite = `False;
          MemWrite = `False; MemRead = `False;
          JumpType = `OffsetTypeJump;
          BranchType = `branch_beq;
          AluCtr = `alu_subu; AluBSrc = `aluBsrc_rt;
          ExtType = `SignExt;
        end
      `opcode_bne:
        begin
          RegWrite = `False;
          MemWrite = `False; MemRead = `False;
          JumpType = `OffsetTypeJump;
          BranchType = `branch_bne;
          AluCtr = `alu_subu; AluBSrc = `aluBsrc_rt;
          ExtType = `SignExt;
        end
      `opcode_bgtz:
        begin
          RegWrite = `False;
          MemWrite = `False; MemRead = `False;
          JumpType = `OffsetTypeJump;
          BranchType = `branch_bgtz;
          AluCtr = `alu_subu; AluBSrc = `aluBsrc_zero;
          ExtType = `SignExt;
        end
      `opcode_blez:
        begin
          RegWrite = `False;
          MemWrite = `False; MemRead = `False;
          JumpType = `OffsetTypeJump;
          BranchType = `branch_blez;
          AluCtr = `alu_subu; AluBSrc = `aluBsrc_zero;
          ExtType = `SignExt;
        end
      `opcode_lw:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_dm;
          MemRead = `True; MemWrite = `False; MemOpType = `MemByWord;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_addu; AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt;
        end
      `opcode_lb:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_dm;
          MemRead = `True; MemWrite = `False; MemOpType = `MemByByte;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_addu; AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt; MemDataExtType = `SignExt;
        end
      `opcode_lbu:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_dm;
          MemRead = `True; MemWrite = `False; MemOpType = `MemByByte;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_addu; AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt; MemDataExtType = `ZeroExt;
        end
      `opcode_sw:
        begin
          RegWrite = `False;
          MemRead = `False; MemWrite = `True; MemOpType = `MemByWord;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_addu; AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt;
        end
      `opcode_sb:
        begin
          RegWrite = `False;
          MemRead = `False; MemWrite = `True; MemOpType = `MemByByte;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_addu; AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt;



        end
      `opcode_j:
        begin
          RegWrite = `False;
          MemRead = `False; MemWrite = `False;
          JumpType = `PseudoTypeJump; BranchType = `no_branch;
          AluCtr = `alu_nop;

        end
      `opcode_jal:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_ra; RwDataSrc = `RwDataSrc_pc1;
          MemRead = `False; MemWrite = `False;
          JumpType = `PseudoTypeJump; BranchType = `no_branch;
          AluCtr = `alu_nop;

        end
    endcase
  end
end
endmodule
module ctrl(
  input [5:0] opcode, funct,
  input bit16,

  output reg RegWrite,
  output reg [1:0] RwIdSrc, RwDataSrc,

  output reg MemRead, MemWrite, MemOpType,

  output reg [2:0] BranchType,
  output reg [1:0] JumpType,

  output reg [4:0] AluCtr,
  output reg [1:0] AluBSrc,
  
  output reg ExtType, MemDataExtType
);




always@(opcode or funct or bit16)
begin
  if (opcode == `Most_R_Type_op) begin

    RegWrite = `True;



    RwIdSrc = `RwIdSrc_rd;

    MemRead = `False; MemWrite = `False;

    BranchType = `no_branch;

    if (funct == `funct_jr || funct == `funct_jalr) begin
      JumpType = `RegTypeJump; RwDataSrc = `RwDataSrc_pc1;
    end else begin
      JumpType = `No_Jump; RwDataSrc =`RwDataSrc_alu;
    end


    AluBSrc = `aluBsrc_rt;
    case (funct)
      `funct_addu : AluCtr = `alu_addu;
      `funct_subu : AluCtr = `alu_subu;
      `funct_slt : AluCtr = `alu_slt;
      `funct_and : AluCtr = `alu_and;
      `funct_nor : AluCtr = `alu_nor;
      `funct_or : AluCtr = `alu_or;
      `funct_xor : AluCtr = `alu_xor;
      `funct_sltu : AluCtr = `alu_sltu;
      `funct_sllv : AluCtr = `alu_sllv;
      `funct_srav : AluCtr = `alu_srav;
      `funct_srlv : AluCtr = `alu_srlv;
      `funct_sll : AluCtr = `alu_sll;
      `funct_srl : AluCtr = `alu_srl;
      `funct_sra : AluCtr = `alu_sra;
      `funct_jr : AluCtr = `alu_nop;
      `funct_jalr : AluCtr = `alu_nop;
      default: AluCtr = `alu_nop;

    endcase

    ExtType = `ZeroExt;

  end else if (opcode == `bgez_bltz_op) begin


    RegWrite = `False;
    MemRead = `False; MemWrite = `False;
    BranchType = (bit16 == `bit16_bgez) ? `branch_bgez : `branch_bltz;
    JumpType = `OffsetTypeJump;
    AluBSrc = `aluBsrc_zero; AluCtr = `alu_subu;
    ExtType = `SignExt;
  end else begin

    case (opcode)
      `opcode_addiu:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_addu;
          AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt;
        end
      `opcode_lui:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_lui;
          AluBSrc = `aluBsrc_imm00;
          ExtType = `ZeroExt;
        end
      `opcode_slti:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt;  RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_slt;
          AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt;
        end
      `opcode_sltiu:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt;  RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_sltu;
          AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt;
        end
      `opcode_andi:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_and;
          AluBSrc = `aluBsrc_imm;
          ExtType = `ZeroExt;
        end
      `opcode_ori:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_or;
          AluBSrc = `aluBsrc_imm;
          ExtType = `ZeroExt;
        end
      `opcode_xori:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_alu;
          MemWrite = `False; MemRead = `False;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_xor;
          AluBSrc = `aluBsrc_imm;
          ExtType = `ZeroExt;
        end
      `opcode_beq:
        begin
          RegWrite = `False;
          MemWrite = `False; MemRead = `False;
          JumpType = `OffsetTypeJump;
          BranchType = `branch_beq;
          AluCtr = `alu_subu; AluBSrc = `aluBsrc_rt;
          ExtType = `SignExt;
        end
      `opcode_bne:
        begin
          RegWrite = `False;
          MemWrite = `False; MemRead = `False;
          JumpType = `OffsetTypeJump;
          BranchType = `branch_bne;
          AluCtr = `alu_subu; AluBSrc = `aluBsrc_rt;
          ExtType = `SignExt;
        end
      `opcode_bgtz:
        begin
          RegWrite = `False;
          MemWrite = `False; MemRead = `False;
          JumpType = `OffsetTypeJump;
          BranchType = `branch_bgtz;
          AluCtr = `alu_subu; AluBSrc = `aluBsrc_zero;
          ExtType = `SignExt;
        end
      `opcode_blez:
        begin
          RegWrite = `False;
          MemWrite = `False; MemRead = `False;
          JumpType = `OffsetTypeJump;
          BranchType = `branch_blez;
          AluCtr = `alu_subu; AluBSrc = `aluBsrc_zero;
          ExtType = `SignExt;
        end
      `opcode_lw:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_dm;
          MemRead = `True; MemWrite = `False; MemOpType = `MemByWord;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_addu; AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt;
        end
      `opcode_lb:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_dm;
          MemRead = `True; MemWrite = `False; MemOpType = `MemByByte;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_addu; AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt; MemDataExtType = `SignExt;
        end
      `opcode_lbu:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_rt; RwDataSrc = `RwDataSrc_dm;
          MemRead = `True; MemWrite = `False; MemOpType = `MemByByte;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_addu; AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt; MemDataExtType = `ZeroExt;
        end
      `opcode_sw:
        begin
          RegWrite = `False;
          MemRead = `False; MemWrite = `True; MemOpType = `MemByWord;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_addu; AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt;
        end
      `opcode_sb:
        begin
          RegWrite = `False;
          MemRead = `False; MemWrite = `True; MemOpType = `MemByByte;
          JumpType = `No_Jump; BranchType = `no_branch;
          AluCtr = `alu_addu; AluBSrc = `aluBsrc_imm;
          ExtType = `SignExt;



        end
      `opcode_j:
        begin
          RegWrite = `False;
          MemRead = `False; MemWrite = `False;
          JumpType = `PseudoTypeJump; BranchType = `no_branch;
          AluCtr = `alu_nop;

        end
      `opcode_jal:
        begin
          RegWrite = `True; RwIdSrc = `RwIdSrc_ra; RwDataSrc = `RwDataSrc_pc1;
          MemRead = `False; MemWrite = `False;
          JumpType = `PseudoTypeJump; BranchType = `no_branch;
          AluCtr = `alu_nop;

        end
    endcase
  end
end
endmodule