data/full_repos/permissive/172189165/src/rtl/r5_regfile.v
data/verilator_xmls/f88e688c-10f1-4771-94a0-6e7b815498c2.xml
module r5_regfile (
                   input wire           clk,
                   input wire           reset_n,

                   input wire [4 : 0]   rs1,
                   output wire [31 : 0] rs1_data,

                   input wire [4 : 0]   rs2,
                   output wire [31 : 0] rs2_data,

                   input wire [4 : 0]   rd,
                   input wire           rd_we,
                   input wire [31 : 0]  rd_data
                  );





  reg [31 : 0] regs [1 : 31];





  reg [31 : 0] tmp_rs1_data;
  reg [31 : 0] tmp_rs2_data;





  assign rs1_data = tmp_rs1_data;
  assign rs2_data = tmp_rs2_data;








  always @ (posedge clk or negedge reset_n)
    begin : reg_update
      integer i;

      if (!reset_n)
        begin
          for (i = 1 ; i < 32 ; i = i + 1)
            regs[i] <= 32'h0;
        end
      else
        begin
          if (rd_we && (rd > 0))
            regs[rd] <= rd_data;
        end
    end




  always @*
    begin : rs1_mux
      if (rs1 > 0)
        tmp_rs1_data = regs[rs1];
      else
        tmp_rs1_data = 32'h0;
    end




  always @*
    begin :rs2_mux
      if (rs2 > 0)
        tmp_rs2_data = regs[rs2];
      else
        tmp_rs2_data = 32'h0;
    end

endmodule
module r5_regfile (
                   input wire           clk,
                   input wire           reset_n,

                   input wire [4 : 0]   rs1,
                   output wire [31 : 0] rs1_data,

                   input wire [4 : 0]   rs2,
                   output wire [31 : 0] rs2_data,

                   input wire [4 : 0]   rd,
                   input wire           rd_we,
                   input wire [31 : 0]  rd_data
                  );






  reg [31 : 0] regs [1 : 31];





  reg [31 : 0] tmp_rs1_data;
  reg [31 : 0] tmp_rs2_data;





  assign rs1_data = tmp_rs1_data;
  assign rs2_data = tmp_rs2_data;








  always @ (posedge clk or negedge reset_n)
    begin : reg_update
      integer i;

      if (!reset_n)
        begin
          for (i = 1 ; i < 32 ; i = i + 1)
            regs[i] <= 32'h0;
        end
      else
        begin
          if (rd_we && (rd > 0))
            regs[rd] <= rd_data;
        end
    end




  always @*
    begin : rs1_mux
      if (rs1 > 0)
        tmp_rs1_data = regs[rs1];
      else
        tmp_rs1_data = 32'h0;
    end




  always @*
    begin :rs2_mux
      if (rs2 > 0)
        tmp_rs2_data = regs[rs2];
      else
        tmp_rs2_data = 32'h0;
    end

endmodule