data/full_repos/permissive/117026779/src/Memory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/117026779/src/Memory.v:180: Multiple top level modules\n                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                        : ... Top module \'RAM\'\nmodule RAM #(\n       ^~~\n                                                                        : ... Top module \'ROM\'\nmodule ROM #(\n       ^~~\n                                                                        : ... Top module \'FIFO\'\nmodule FIFO #(\n       ^~~~\n                                                                        : ... Top module \'STACK\'\nmodule STACK #(\n       ^~~~~\n                                                                        : ... Top module \'SHIFTREGISTER\'\nmodule SHIFTREGISTER #(parameter WIDTH = 8)(\n       ^~~~~~~~~~~~~\n                                                                        : ... Top module \'REGISTER\'\nmodule REGISTER #(parameter WIDTH = 8)(\n       ^~~~~~~~\n                                                                        : ... Top module \'SHIFTLOADREG\'\nmodule SHIFTLOADREG #(parameter WIDTH = 8)(\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:366: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                     : ... In instance STACK\n        mem[write_position] = 0;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:384: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                     : ... In instance STACK\n            mem[write_position] = in;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:385: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'write_position\' generates 4 bits.\n                                                                     : ... In instance STACK\n            if(write_position == LENGTH-1)\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:399: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                     : ... In instance STACK\n            out = mem[read_position];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:400: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'read_position\' generates 4 bits.\n                                                                     : ... In instance STACK\n            if(read_position == LENGTH-1)\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:266: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                     : ... In instance FIFO\n        mem[write_position] = 0;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:285: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                     : ... In instance FIFO\n            mem[write_position] = in;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:286: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'write_position\' generates 4 bits.\n                                                                     : ... In instance FIFO\n            if(write_position == LENGTH-1)\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:300: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                     : ... In instance FIFO\n            out = mem[read_position];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:301: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'read_position\' generates 4 bits.\n                                                                     : ... In instance FIFO\n            if(read_position == LENGTH-1)\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:199: Bit extraction of array[4096:0] requires 13 bit index, not 12 bits.\n                                                                     : ... In instance ROM\nassign out = rom[a];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:199: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 33 bits.\n                                                                     : ... In instance ROM\nassign out = rom[a];\n           ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:121: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'we\' generates 4 bits.\n                                                                     : ... In instance RAM\nassign data = (cs && oe && !we) ? data_out : {(WIDTH){1\'bz}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:160: Bit extraction of array[4096:0] requires 13 bit index, not 12 bits.\n                                                                     : ... In instance RAM\n                memory_in[(MINIMUM_SECTIONAL_WIDTH*(c+1))-1 : MINIMUM_SECTIONAL_WIDTH*c] = ram[address][(MINIMUM_SECTIONAL_WIDTH*(c+1))-1 : MINIMUM_SECTIONAL_WIDTH*c];\n                                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:170: Bit extraction of array[4096:0] requires 13 bit index, not 12 bits.\n                                                                     : ... In instance RAM\n       ram[address] = memory_in;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:174: Bit extraction of array[4096:0] requires 13 bit index, not 12 bits.\n                                                                     : ... In instance RAM\n        data_out = ram[address];\n                      ^\n%Error: Exiting due to 17 warning(s)\n'
module STACK #(
    parameter LENGTH = 16,
    parameter WIDTH = 8
)
(
    input wire clk,
    input wire rst,
    input wire wr_cs,
    input wire wr_en,
    input wire rd_cs,
    input wire rd_en,
    output reg full,
    output reg empty,
    output reg [WIDTH-1:0] out,
    input wire [WIDTH-1:0] in
);



parameter ADDRESS_WIDTH = $clog2(LENGTH);



reg [ADDRESS_WIDTH-1:0] write_position;
reg [ADDRESS_WIDTH-1:0] read_position;
reg [ADDRESS_WIDTH:0] status_count;
reg [WIDTH-1:0] mem [0:LENGTH];














always @(posedge clk or posedge rst)
begin
    if(rst)
    begin
        write_position = 0;
        read_position = 0;
        status_count = 0;
        mem[write_position] = 0;
        write_position = 0;
        full = 0;
        empty = 1;
    end
    else
    begin
        if(status_count == 0)
        begin
            empty = 1;
        end
        if(status_count == LENGTH)
        begin
            full = 1;
        end

        if (wr_cs && wr_en && !full)
        begin
            mem[write_position] = in;
            if(write_position == LENGTH-1)
            begin
                write_position = 0;
            end
            else
            begin
                write_position = write_position + 1;
            end
            status_count = status_count + 1;
            empty = 0;
        end

        if (rd_cs && rd_en && !empty)
        begin
            out = mem[read_position];
            if(read_position == LENGTH-1)
            begin
                read_position = 0;
            end
            else
            begin
                read_position = read_position + 1;
            end
            status_count = status_count - 1;
            full = 0;
        end
    end
end

endmodule
module STACK #(
    parameter LENGTH = 16,
    parameter WIDTH = 8
)
(
    input wire clk,
    input wire rst,
    input wire wr_cs,
    input wire wr_en,
    input wire rd_cs,
    input wire rd_en,
    output reg full,
    output reg empty,
    output reg [WIDTH-1:0] out,
    input wire [WIDTH-1:0] in
);




parameter ADDRESS_WIDTH = $clog2(LENGTH);



reg [ADDRESS_WIDTH-1:0] write_position;
reg [ADDRESS_WIDTH-1:0] read_position;
reg [ADDRESS_WIDTH:0] status_count;
reg [WIDTH-1:0] mem [0:LENGTH];














always @(posedge clk or posedge rst)
begin
    if(rst)
    begin
        write_position = 0;
        read_position = 0;
        status_count = 0;
        mem[write_position] = 0;
        write_position = 0;
        full = 0;
        empty = 1;
    end
    else
    begin
        if(status_count == 0)
        begin
            empty = 1;
        end
        if(status_count == LENGTH)
        begin
            full = 1;
        end

        if (wr_cs && wr_en && !full)
        begin
            mem[write_position] = in;
            if(write_position == LENGTH-1)
            begin
                write_position = 0;
            end
            else
            begin
                write_position = write_position + 1;
            end
            status_count = status_count + 1;
            empty = 0;
        end

        if (rd_cs && rd_en && !empty)
        begin
            out = mem[read_position];
            if(read_position == LENGTH-1)
            begin
                read_position = 0;
            end
            else
            begin
                read_position = read_position + 1;
            end
            status_count = status_count - 1;
            full = 0;
        end
    end
end

endmodule