data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv:17: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv:17: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv:52: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_0, net_1, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv:53: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_0, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv:54: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, Y, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv:55: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(net_11, Y, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv:56: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_11, net_1);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv:57: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_1, vdd, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv:58: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_1, vdd, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv:59: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(Y, vdd, net_1);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv:60: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_28, vdd, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/xnor.sv:61: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(Y, net_28, A);\n          ^~~~~~\n%Error: Exiting due to 10 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbenchXNOR();
    logic clk;
    logic A, B, Y;
    logic [2:0] vectors[4:0], currentvec;
    logic [3:0] vectornum, errors;
    

    xnor_ds dut(A, B, Y);
    

    initial begin
       $readmemb("xnor-vectors.txt", vectors);
       vectornum = 0; errors = 0;
    end

    always begin
       clk = 1; #10; clk = 0; #10;
    end

    always @(posedge clk) begin
       currentvec = vectors[vectornum];
       A = currentvec[1];
       B = currentvec[2];
       if (currentvec[0] === 1'bx) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);
         $stop;
       end
    end

    always @(negedge clk) begin
       if ((Y !== currentvec[0])) begin
          $display("Error: inputs were a=%h b=%h", A, B);
          $display("       output mismatches as %h (%h expected)", 
                   currentvec[0], Y);
          errors = errors + 1;
       end
       vectornum = vectornum + 1;
    end
endmodule
module testbenchXNOR();

    logic clk;
    logic A, B, Y;
    logic [2:0] vectors[4:0], currentvec;
    logic [3:0] vectornum, errors;
    

    xnor_ds dut(A, B, Y);
    

    initial begin
       $readmemb("xnor-vectors.txt", vectors);
       vectornum = 0; errors = 0;
    end

    always begin
       clk = 1; #10; clk = 0; #10;
    end

    always @(posedge clk) begin
       currentvec = vectors[vectornum];
       A = currentvec[1];
       B = currentvec[2];
       if (currentvec[0] === 1'bx) begin
         $display("Completed %d tests with %d errors.", 
                  vectornum, errors);
         $stop;
       end
    end

    always @(negedge clk) begin
       if ((Y !== currentvec[0])) begin
          $display("Error: inputs were a=%h b=%h", A, B);
          $display("       output mismatches as %h (%h expected)", 
                   currentvec[0], Y);
          errors = errors + 1;
       end
       vectornum = vectornum + 1;
    end
endmodule