data/full_repos/permissive/161029703/src/cpu/stage_id/id_j.v
1: b'%Error: data/full_repos/permissive/161029703/src/cpu/stage_id/id_j.v:1: Cannot find include file: ../defs.v\n`include "../defs.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161029703/src/cpu/stage_id,data/full_repos/permissive/161029703/../defs.v\n             data/full_repos/permissive/161029703/src/cpu/stage_id,data/full_repos/permissive/161029703/../defs.v.v\n             data/full_repos/permissive/161029703/src/cpu/stage_id,data/full_repos/permissive/161029703/../defs.v.sv\n             ../defs.v\n             ../defs.v.v\n             ../defs.v.sv\n             obj_dir/../defs.v\n             obj_dir/../defs.v.v\n             obj_dir/../defs.v.sv\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_id/id_j.v:18: Define or directive not defined: \'`OP_J\'\n    6\'h02: op <= `OP_J;\n                 ^~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_id/id_j.v:18: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    6\'h02: op <= `OP_J;\n                      ^\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_id/id_j.v:19: Define or directive not defined: \'`OP_JAL\'\n    6\'h03: op <= `OP_JAL;\n                 ^~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_id/id_j.v:19: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    6\'h03: op <= `OP_JAL;\n                        ^\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_id/id_j.v:20: Define or directive not defined: \'`OP_INVAILD\'\n    default: op <= `OP_INVAILD;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161029703/src/cpu/stage_id/id_j.v:20: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    default: op <= `OP_INVAILD;\n                              ^\n%Error: Exiting due to 7 error(s)\n'
module id_j(

            op,
            address,

            inst);

input wire[31:0] inst;
output reg[7:0] op;
output wire[25:0] address;

assign address = inst[25:0];


always @(*) begin
    case(inst[31:26])
    6'h02: op <= `OP_J;
    6'h03: op <= `OP_JAL;
    default: op <= `OP_INVAILD;
    endcase
end


endmodule
module id_j(

            op,
            address,

            inst);


input wire[31:0] inst;
output reg[7:0] op;
output wire[25:0] address;

assign address = inst[25:0];


always @(*) begin
    case(inst[31:26])
    6'h02: op <= `OP_J;
    6'h03: op <= `OP_JAL;
    default: op <= `OP_INVAILD;
    endcase
end


endmodule