data/full_repos/permissive/15618617/src/hw_uart.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/15618617/src/hw_uart.v:61: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'Rs232Tx\'\nmodule Rs232Tx(input clk, output UART_TX, input [7:0] data, input send, output reg uart_ovf, output reg sending);\n       ^~~~~~~\n                                                                       : ... Top module \'UartDemux\'\nmodule UartDemux(input clk, input RESET, input UART_RX, output reg [7:0] data, output reg [7:0] addr, output reg write, output reg checksum_error);\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/15618617/src/hw_uart.v:5: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1\' generates 9 bits.\n                                                                   : ... In instance Rs232Tx\n  reg [9:0] sendbuf = 9\'b000000001;\n                      ^~~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n'
module Rs232Rx(input clk, input UART_RX, output [7:0] data, output send);
  reg [8:0] recvbuf;
  reg [5:0] timeout = 10/2 - 1;
  reg recving;
  reg data_valid = 0;
  assign data = recvbuf[7:0];
  assign send = data_valid;
  always @(posedge clk) begin
    data_valid <= 0;
    timeout <= timeout - 6'd1;
    if (timeout == 0) begin
      timeout <= 10 - 1;
      recvbuf <= (recving ? {UART_RX, recvbuf[8:1]} : 9'b100000000);
      recving <= 1;
      if (recving && recvbuf[0]) begin
        recving <= 0;
        data_valid <= UART_RX;
      end
    end


    if (!recving && UART_RX)
      timeout <= 10/2 - 1;
  end
endmodule
module Rs232Rx(input clk, input UART_RX, output [7:0] data, output send);

  reg [8:0] recvbuf;
  reg [5:0] timeout = 10/2 - 1;
  reg recving;
  reg data_valid = 0;
  assign data = recvbuf[7:0];
  assign send = data_valid;
  always @(posedge clk) begin
    data_valid <= 0;
    timeout <= timeout - 6'd1;
    if (timeout == 0) begin
      timeout <= 10 - 1;
      recvbuf <= (recving ? {UART_RX, recvbuf[8:1]} : 9'b100000000);
      recving <= 1;
      if (recving && recvbuf[0]) begin
        recving <= 0;
        data_valid <= UART_RX;
      end
    end


    if (!recving && UART_RX)
      timeout <= 10/2 - 1;
  end
endmodule