data/full_repos/permissive/152986713/ice40/cpu8.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:139: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'write'\n                                                                         : ... In instance CPU\n      write <= 0;\n      ^~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:145: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'write'\n                                                                         : ... In instance CPU\n          write <= 0;\n          ^~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:150: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'address'\n                                                                         : ... In instance CPU\n          address <= IP;\n          ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:152: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'write'\n                                                                         : ... In instance CPU\n          write <= 0;\n          ^~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:165: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'address'\n                                                                         : ... In instance CPU\n       address <= IP;\n       ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:171: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'address'\n                                                                         : ... In instance CPU\n              address <= B;\n              ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:176: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'address'\n                                                                         : ... In instance CPU\n              address <= {4'b0, data_in[3:0]};\n              ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:177: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_out'\n                                                                         : ... In instance CPU\n              data_out <= A;\n              ^~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:178: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'write'\n                                                                         : ... In instance CPU\n              write <= 1;\n              ^~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:193: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'address'\n                                                                         : ... In instance CPU\n                address <= IP;\n                ^~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:36: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h0:  Y = 0;\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:37: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h1: Y = {1'b0, A};\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:38: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h2:  Y = A + 1;\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:39: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h3:  Y = A - 1;\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:41: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h4:  Y = {A, 1'b0};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:42: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h5:  Y = {A[0], 1'b0, A[N-1:1]};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:43: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h6:  Y = {A, carry};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:44: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h7:  Y = {A[0], carry, A[N-1:1]};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:46: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h8:  Y = {1'b0, A | B};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:47: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'h9:  Y = {1'b0, A & B};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:48: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'ha:  Y = {1'b0, A ^ B};\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:49: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'hb: Y = {1'b0, B};\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:51: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'hc:  Y = A + B;\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:52: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'hd:  Y = A - B;\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:53: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'he:  Y = A + B + (carry?1:0);\n             ^\n%Error-PROCASSWIRE: data/full_repos/permissive/152986713/ice40/cpu8.v:54: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Y'\n                                                                        : ... In instance CPU.alu\n      4'hf:  Y = A - B - (carry?1:0);\n             ^\n%Error: Exiting due to 26 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module ALU(A, B, carry, aluop, Y);

  parameter N = 8;
  input  [N-1:0] A;
  input  [N-1:0] B;
  input  carry;
  input  [3:0] aluop;
  output [N:0] Y;
  
  always @(*)
    case (aluop)

      `OP_ZERO:		Y = 0;
      `OP_LOAD_A:	Y = {1'b0, A};
      `OP_INC:		Y = A + 1;
      `OP_DEC:		Y = A - 1;

      `OP_ASL:		Y = {A, 1'b0};
      `OP_LSR:		Y = {A[0], 1'b0, A[N-1:1]};
      `OP_ROL:		Y = {A, carry};
      `OP_ROR:		Y = {A[0], carry, A[N-1:1]};

      `OP_OR:		Y = {1'b0, A | B};
      `OP_AND:		Y = {1'b0, A & B};
      `OP_XOR:		Y = {1'b0, A ^ B};
      `OP_LOAD_B:	Y = {1'b0, B};

      `OP_ADD:		Y = A + B;
      `OP_SUB:		Y = A - B;
      `OP_ADC:		Y = A + B + (carry?1:0);
      `OP_SBB:		Y = A - B - (carry?1:0);
    endcase
  
endmodule
module ALU(A, B, carry, aluop, Y);


  parameter N = 8;
  input  [N-1:0] A;
  input  [N-1:0] B;
  input  carry;
  input  [3:0] aluop;
  output [N:0] Y;
  
  always @(*)
    case (aluop)

      `OP_ZERO:		Y = 0;
      `OP_LOAD_A:	Y = {1'b0, A};
      `OP_INC:		Y = A + 1;
      `OP_DEC:		Y = A - 1;

      `OP_ASL:		Y = {A, 1'b0};
      `OP_LSR:		Y = {A[0], 1'b0, A[N-1:1]};
      `OP_ROL:		Y = {A, carry};
      `OP_ROR:		Y = {A[0], carry, A[N-1:1]};

      `OP_OR:		Y = {1'b0, A | B};
      `OP_AND:		Y = {1'b0, A & B};
      `OP_XOR:		Y = {1'b0, A ^ B};
      `OP_LOAD_B:	Y = {1'b0, B};

      `OP_ADD:		Y = A + B;
      `OP_SUB:		Y = A - B;
      `OP_ADC:		Y = A + B + (carry?1:0);
      `OP_SBB:		Y = A - B - (carry?1:0);
    endcase
  
endmodule