data/full_repos/permissive/149848590/src/cpu/core/sim/CPU_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/149848590/src/cpu/core/sim/CPU_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #7 rst = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/149848590/src/cpu/core/sim/CPU_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/149848590/src/cpu/core/sim/CPU_tb.v:24: Cannot find file containing module: \'Core\'\n    Core cpu(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/149848590/src/cpu/core/sim,data/full_repos/permissive/149848590/Core\n             data/full_repos/permissive/149848590/src/cpu/core/sim,data/full_repos/permissive/149848590/Core.v\n             data/full_repos/permissive/149848590/src/cpu/core/sim,data/full_repos/permissive/149848590/Core.sv\n             Core\n             Core.v\n             Core.sv\n             obj_dir/Core\n             obj_dir/Core.v\n             obj_dir/Core.sv\n%Error: data/full_repos/permissive/149848590/src/cpu/core/sim/CPU_tb.v:45: Cannot find file containing module: \'RAM_tb\'\n    RAM_tb ram(\n    ^~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/sim/CPU_tb.v:55: Cannot find file containing module: \'ROM_tb\'\n    ROM_tb rom(\n    ^~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPU_tb();

    reg clk, rst;

    wire ram_en;
    wire[3:0] ram_write_en;
    wire[31:0] ram_addr;
    wire[31:0] ram_write_data;
    wire[31:0] ram_read_data;

    wire rom_en;

    wire[31:0] rom_addr;

    wire[31:0] rom_read_data;

    wire[31:0] debug_pc_addr;
    wire[3:0] debug_reg_write_en;
    wire[4:0] debug_reg_write_addr;
    wire[31:0] debug_reg_write_data;

    Core cpu(
        .clk(clk),
        .rst(rst),
        .halt(0),
        .interrupt(5'h00),
        .ram_en(ram_en),
        .ram_write_en(ram_write_en),
        .ram_addr(ram_addr),
        .ram_write_data(ram_write_data),
        .ram_read_data(ram_read_data),
        .rom_en(rom_en),

        .rom_addr(rom_addr),

        .rom_read_data(rom_read_data),
        .debug_pc_addr(debug_pc_addr),
        .debug_reg_write_en(debug_reg_write_en),
        .debug_reg_write_addr(debug_reg_write_addr),
        .debug_reg_write_data(debug_reg_write_data)
    );

    RAM_tb ram(
        .clk(clk),
        .rst(rst),
        .en(ram_en),
        .write_sel(ram_write_en),
        .addr(ram_addr),
        .data_in(ram_write_data),
        .data_out(ram_read_data)
    );

    ROM_tb rom(
        .clk(clk),
        .rst(rst),
        .en(rom_en),
        .addr(rom_addr),
        .inst(rom_read_data)
    );

    initial begin
        clk = 0;
        rst = 0;
        #7 rst = 1;
    end

    always begin
        #5 clk = ~clk;
    end

endmodule
module CPU_tb();


    reg clk, rst;

    wire ram_en;
    wire[3:0] ram_write_en;
    wire[31:0] ram_addr;
    wire[31:0] ram_write_data;
    wire[31:0] ram_read_data;

    wire rom_en;

    wire[31:0] rom_addr;

    wire[31:0] rom_read_data;

    wire[31:0] debug_pc_addr;
    wire[3:0] debug_reg_write_en;
    wire[4:0] debug_reg_write_addr;
    wire[31:0] debug_reg_write_data;

    Core cpu(
        .clk(clk),
        .rst(rst),
        .halt(0),
        .interrupt(5'h00),
        .ram_en(ram_en),
        .ram_write_en(ram_write_en),
        .ram_addr(ram_addr),
        .ram_write_data(ram_write_data),
        .ram_read_data(ram_read_data),
        .rom_en(rom_en),

        .rom_addr(rom_addr),

        .rom_read_data(rom_read_data),
        .debug_pc_addr(debug_pc_addr),
        .debug_reg_write_en(debug_reg_write_en),
        .debug_reg_write_addr(debug_reg_write_addr),
        .debug_reg_write_data(debug_reg_write_data)
    );

    RAM_tb ram(
        .clk(clk),
        .rst(rst),
        .en(ram_en),
        .write_sel(ram_write_en),
        .addr(ram_addr),
        .data_in(ram_write_data),
        .data_out(ram_read_data)
    );

    ROM_tb rom(
        .clk(clk),
        .rst(rst),
        .en(rom_en),
        .addr(rom_addr),
        .inst(rom_read_data)
    );

    initial begin
        clk = 0;
        rst = 0;
        #7 rst = 1;
    end

    always begin
        #5 clk = ~clk;
    end

endmodule