data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/impl/top_md5/ecp5_trellis_md5.v
 line:59: before: ")"
1: b'%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/impl/top_md5/ecp5_trellis_md5.v:24: Cannot find include file: pll.v\n`include "pll.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/impl/top_md5,data/full_repos/permissive/150947952/pll.v\n             data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/impl/top_md5,data/full_repos/permissive/150947952/pll.v.v\n             data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/impl/top_md5,data/full_repos/permissive/150947952/pll.v.sv\n             pll.v\n             pll.v.v\n             pll.v.sv\n             obj_dir/pll.v\n             obj_dir/pll.v.v\n             obj_dir/pll.v.sv\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/impl/top_md5/ecp5_trellis_md5.v:25: Cannot find include file: top_md5.v\n`include "top_md5.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/impl/top_md5/ecp5_trellis_md5.v:26: Cannot find include file: md5core.v\n`include "md5core.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/impl/top_md5/ecp5_trellis_md5.v:27: Cannot find include file: string_process_match.v\n`include "string_process_match.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/impl/top_md5/ecp5_trellis_md5.v:28: Cannot find include file: cmd_parser.v\n`include "cmd_parser.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/impl/top_md5/ecp5_trellis_md5.v:29: Cannot find include file: parallel_bus.v\n`include "parallel_bus.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/impl/top_md5/ecp5_trellis_md5.v:30: Cannot find include file: hash_op.v\n`include "hash_op.v" \n         ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module ecp5_trellis_md5 #
(
    parameter integer NUM_LEDS = 4
)
(
    input wire clk_12mhz,
    input wire reset_n,


    input wire bus_clk,
    inout wire [15:0] bus_data,
    input wire bus_rnw,

    output wire bus_done,
    output wire bus_match,
    output wire led0_g,
    output wire led0_r,
    output wire led0_b,
    output wire [NUM_LEDS-1:0] led
);



wire reset;

assign reset = ~reset_n;


wire locked;

assign led0_b = ~locked;



top_md5 #
(
    .NUM_LEDS(NUM_LEDS)
) top_md5_inst
(
    .clk(clk_12mhz),
    .reset(reset),
    .bus_clk(bus_clk),
    .bus_data(bus_data),
    .bus_rnw(bus_rnw),

    .bus_done(bus_done),
    .bus_match(bus_match),
    .match_led(led0_g),
    .led(led)
);

endmodule
module ecp5_trellis_md5 #
(
    parameter integer NUM_LEDS = 4
)
(
    input wire clk_12mhz,
    input wire reset_n,


    input wire bus_clk,
    inout wire [15:0] bus_data,
    input wire bus_rnw,

    output wire bus_done,
    output wire bus_match,
    output wire led0_g,
    output wire led0_r,
    output wire led0_b,
    output wire [NUM_LEDS-1:0] led
);




wire reset;

assign reset = ~reset_n;


wire locked;

assign led0_b = ~locked;



top_md5 #
(
    .NUM_LEDS(NUM_LEDS)
) top_md5_inst
(
    .clk(clk_12mhz),
    .reset(reset),
    .bus_clk(bus_clk),
    .bus_data(bus_data),
    .bus_rnw(bus_rnw),

    .bus_done(bus_done),
    .bus_match(bus_match),
    .match_led(led0_g),
    .led(led)
);

endmodule