data/full_repos/permissive/158606829/sys/audio_out.v
 line:39: before: "reg"
1: b"%Error: data/full_repos/permissive/158606829/sys/audio_out.v:72: Cannot find file containing module: 'i2s'\ni2s i2s\n^~~\n        ... Looked in:\n             data/full_repos/permissive/158606829/sys,data/full_repos/permissive/158606829/i2s\n             data/full_repos/permissive/158606829/sys,data/full_repos/permissive/158606829/i2s.v\n             data/full_repos/permissive/158606829/sys,data/full_repos/permissive/158606829/i2s.sv\n             i2s\n             i2s.v\n             i2s.sv\n             obj_dir/i2s\n             obj_dir/i2s.v\n             obj_dir/i2s.sv\n%Error: data/full_repos/permissive/158606829/sys/audio_out.v:87: Cannot find file containing module: 'spdif'\nspdif toslink\n^~~~~\n%Error: data/full_repos/permissive/158606829/sys/audio_out.v:98: Cannot find file containing module: 'sigma_delta_dac'\nsigma_delta_dac #(15) sd_l\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158606829/sys/audio_out.v:106: Cannot find file containing module: 'sigma_delta_dac'\nsigma_delta_dac #(15) sd_r\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module audio_out
#(
	parameter CLK_RATE = 50000000
)
(
	input        reset,
	input        clk,


	input        sample_rate,

	input [15:0] left_in,
	input [15:0] right_in,


	output       i2s_bclk,
	output       i2s_lrclk,
	output       i2s_data,


   output       spdif,


	output       dac_l,
	output       dac_r
);

localparam AUDIO_RATE = 48000;
localparam AUDIO_DW = 16;

localparam CE_RATE = AUDIO_RATE*AUDIO_DW*8;
localparam FILTER_DIV = (CE_RATE/(AUDIO_RATE*32))-1;

wire [31:0] real_ce = sample_rate ? {CE_RATE[30:0],1'b0} : CE_RATE[31:0];

reg mclk_ce;
always @(posedge clk) begin
	reg [31:0] cnt;

	mclk_ce <= 0;
	cnt = cnt + real_ce;
	if(cnt >= CLK_RATE) begin
		cnt = cnt - CLK_RATE;
		mclk_ce <= 1;
	end
end

reg i2s_ce;
always @(posedge clk) begin
	reg div;
	i2s_ce <= 0;
	if(mclk_ce) begin
		div <= ~div;
		i2s_ce <= div;
	end
end

reg lpf_ce;
always @(posedge clk) begin
	integer div;
	lpf_ce <= 0;
	if(mclk_ce) begin
		div <= div + 1;
		if(div == FILTER_DIV) begin
			div <= 0;
			lpf_ce <= 1;
		end
	end
end

i2s i2s
(
	.reset(reset),

	.clk(clk),
	.ce(i2s_ce),

	.sclk(i2s_bclk),
	.lrclk(i2s_lrclk),
	.sdata(i2s_data),

	.left_chan(al),
	.right_chan(ar)
);

spdif toslink
(
	.rst_i(reset),

	.clk_i(clk),
	.bit_out_en_i(mclk_ce),

	.sample_i({ar,al}),
	.spdif_o(spdif)
);

sigma_delta_dac #(15) sd_l
(
	.CLK(clk),
	.RESET(reset),
	.DACin({~al[15], al[14:0]}),
	.DACout(dac_l)
);

sigma_delta_dac #(15) sd_r
(
	.CLK(clk),
	.RESET(reset),
	.DACin({~ar[15], ar[14:0]}),
	.DACout(dac_r)
);

wire [15:0] al, ar;
lpf_aud lpf_l
(
   .CLK(clk),
   .CE(lpf_ce),
   .IDATA(left_in),
   .ODATA(al)
);

lpf_aud lpf_r
(
   .CLK(clk),
   .CE(lpf_ce),
   .IDATA(right_in),
   .ODATA(ar)
);

endmodule
module audio_out
#(
	parameter CLK_RATE = 50000000
)
(
	input        reset,
	input        clk,


	input        sample_rate,

	input [15:0] left_in,
	input [15:0] right_in,


	output       i2s_bclk,
	output       i2s_lrclk,
	output       i2s_data,


   output       spdif,


	output       dac_l,
	output       dac_r
);


localparam AUDIO_RATE = 48000;
localparam AUDIO_DW = 16;

localparam CE_RATE = AUDIO_RATE*AUDIO_DW*8;
localparam FILTER_DIV = (CE_RATE/(AUDIO_RATE*32))-1;

wire [31:0] real_ce = sample_rate ? {CE_RATE[30:0],1'b0} : CE_RATE[31:0];

reg mclk_ce;
always @(posedge clk) begin
	reg [31:0] cnt;

	mclk_ce <= 0;
	cnt = cnt + real_ce;
	if(cnt >= CLK_RATE) begin
		cnt = cnt - CLK_RATE;
		mclk_ce <= 1;
	end
end

reg i2s_ce;
always @(posedge clk) begin
	reg div;
	i2s_ce <= 0;
	if(mclk_ce) begin
		div <= ~div;
		i2s_ce <= div;
	end
end

reg lpf_ce;
always @(posedge clk) begin
	integer div;
	lpf_ce <= 0;
	if(mclk_ce) begin
		div <= div + 1;
		if(div == FILTER_DIV) begin
			div <= 0;
			lpf_ce <= 1;
		end
	end
end

i2s i2s
(
	.reset(reset),

	.clk(clk),
	.ce(i2s_ce),

	.sclk(i2s_bclk),
	.lrclk(i2s_lrclk),
	.sdata(i2s_data),

	.left_chan(al),
	.right_chan(ar)
);

spdif toslink
(
	.rst_i(reset),

	.clk_i(clk),
	.bit_out_en_i(mclk_ce),

	.sample_i({ar,al}),
	.spdif_o(spdif)
);

sigma_delta_dac #(15) sd_l
(
	.CLK(clk),
	.RESET(reset),
	.DACin({~al[15], al[14:0]}),
	.DACout(dac_l)
);

sigma_delta_dac #(15) sd_r
(
	.CLK(clk),
	.RESET(reset),
	.DACin({~ar[15], ar[14:0]}),
	.DACout(dac_r)
);

wire [15:0] al, ar;
lpf_aud lpf_l
(
   .CLK(clk),
   .CE(lpf_ce),
   .IDATA(left_in),
   .ODATA(al)
);

lpf_aud lpf_r
(
   .CLK(clk),
   .CE(lpf_ce),
   .IDATA(right_in),
   .ODATA(ar)
);

endmodule