data/full_repos/permissive/175808891/verilog/i2c_master.v
1: b'%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/i2c_master.v:137: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 16 bits.\n                                                                             : ... In instance i2cmaster.byte_controller.bit_controller\n      else if (~|filter_cnt) filter_cnt <= clk_cnt >> 2;  \n                                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module i2cmaster #(
	parameter base_addr = 6'h0
)
(

    input wire sys_clk,
    input wire sys_rst,

    input wire [5:0] io_a,
    input wire [7:0] io_di,
    output reg [7:0] io_do,
    input wire io_re,
    input wire io_we,

	output reg i2c_irq,

	input wire scl_i,
	output wire scl_o,
	output wire scl_oen_o,
	input wire sda_i,
	output wire sda_o,
	output wire sda_oen_o
);


	localparam prer_low_addr 	= base_addr;
	localparam prer_high_addr 	= base_addr + 6'd1;
	localparam ctr_addr  		= base_addr + 6'd2;
	localparam txr_addr  		= base_addr + 6'd3;
	localparam rxr_addr  		= base_addr + 6'd4;
	localparam cr_addr  			= base_addr + 6'd5;
	localparam sr_addr  			= base_addr + 6'd6;
	
	wire csr_selected = (io_a == prer_low_addr) | (io_a == prer_high_addr) |
						(io_a == ctr_addr) | (io_a == rxr_addr) |
						(io_a == sr_addr) | (io_a == txr_addr) |
						(io_a == cr_addr);
	





	reg  [15:0] prer;
	reg  [ 7:0] ctr;
	reg  [ 7:0] txr;
	wire [ 7:0] rxr;
	reg  [ 7:0] cr;
	wire [ 7:0] sr;


	wire done;


	wire core_en;
	wire ien;


	wire irxack;
	reg  rxack;
	reg  tip;
	reg  irq_flag;
	wire i2c_busy;
	wire i2c_al;
	reg  al;






	always @(posedge sys_clk)
	begin
	  io_do <= 8'd00;
	  if(io_re & csr_selected)
		case (io_a)
			prer_low_addr: 		io_do <= #1 prer[ 7:0];
			prer_high_addr: 	io_do <= #1 prer[15:8];
			ctr_addr: 			io_do <= #1 ctr;
			rxr_addr: 			io_do <= #1 rxr;
			sr_addr: 			io_do <= #1 sr;
			txr_addr: 			io_do <= #1 txr;
			cr_addr: 			io_do <= #1 cr;
			default: 			;
		endcase
	end


	always @(posedge sys_clk or posedge sys_rst)
	  if (sys_rst)
	    begin
	        prer <= #1 16'hffff;
	        ctr  <= #1  8'h0;
	        txr  <= #1  8'h0;
	    end
	  else
	    if (io_we & csr_selected)
	      case (io_a)
	         prer_low_addr : 	prer [ 7:0] <= #1 io_di;
	         prer_high_addr : 	prer [15:8] <= #1 io_di;
	         ctr_addr : 				ctr <= #1 io_di;
	         txr_addr : 				txr <= #1 io_di;
	         default: ;
	      endcase


	always @(posedge sys_clk or posedge sys_rst)
	  if (sys_rst)
	    cr <= #1 8'h0;
	  else if (io_we & (io_a == cr_addr))
	    begin
	        if (core_en)
	          cr <= #1 io_di;
	    end
	  else
	    begin
	        if (done | i2c_al)
	          cr[7:4] <= #1 4'h0;

	        cr[2:1] <= #1 2'b0;
	        cr[0]   <= #1 1'b0;
	    end



	wire sta  = cr[7];
	wire sto  = cr[6];
	wire rd   = cr[5];
	wire wr   = cr[4];
	wire ack  = cr[3];
	wire iack = cr[0];


	assign core_en = ctr[7];
	assign ien = ctr[6];


	i2c_master_byte_ctrl byte_controller (
		.clk      ( sys_clk     ),
		.rst      ( sys_rst     ),
		.ena      ( core_en      ),
		.clk_cnt  ( prer         ),
		.start    ( sta          ),
		.stop     ( sto          ),
		.read     ( rd           ),
		.write    ( wr           ),
		.ack_in   ( ack          ),
		.din      ( txr          ),
		.cmd_ack  ( done         ),
		.ack_out  ( irxack       ),
		.dout     ( rxr          ),
		.i2c_busy ( i2c_busy     ),
		.i2c_al   ( i2c_al       ),
		.scl_i    ( scl_i    ),
		.scl_o    ( scl_o    ),
		.scl_oen  ( scl_oen_o ),
		.sda_i    ( sda_i    ),
		.sda_o    ( sda_o    ),
		.sda_oen  ( sda_oen_o )
	);


	always @(posedge sys_clk or posedge sys_rst)
	  if (sys_rst)
	    begin
	        al       <= #1 1'b0;
	        rxack    <= #1 1'b0;
	        tip      <= #1 1'b0;
	        irq_flag <= #1 1'b0;
	    end
	  else
	    begin
	        al       <= #1 i2c_al | (al & ~sta);
	        rxack    <= #1 irxack;
	        tip      <= #1 (rd | wr);
	        irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack;
	    end


	always @(posedge sys_clk or posedge sys_rst)
	  if (sys_rst)
	    i2c_irq <= #1 1'b0;
	  else
	    i2c_irq <= #1 irq_flag && ien;


	assign sr[7]   = rxack;
	assign sr[6]   = i2c_busy;
	assign sr[5]   = al;
	assign sr[4:2] = 3'h0;
	assign sr[1]   = tip;
	assign sr[0]   = irq_flag;

endmodule
module i2cmaster #(
	parameter base_addr = 6'h0
)
(

    input wire sys_clk,
    input wire sys_rst,

    input wire [5:0] io_a,
    input wire [7:0] io_di,
    output reg [7:0] io_do,
    input wire io_re,
    input wire io_we,

	output reg i2c_irq,

	input wire scl_i,
	output wire scl_o,
	output wire scl_oen_o,
	input wire sda_i,
	output wire sda_o,
	output wire sda_oen_o
);



	localparam prer_low_addr 	= base_addr;
	localparam prer_high_addr 	= base_addr + 6'd1;
	localparam ctr_addr  		= base_addr + 6'd2;
	localparam txr_addr  		= base_addr + 6'd3;
	localparam rxr_addr  		= base_addr + 6'd4;
	localparam cr_addr  			= base_addr + 6'd5;
	localparam sr_addr  			= base_addr + 6'd6;
	
	wire csr_selected = (io_a == prer_low_addr) | (io_a == prer_high_addr) |
						(io_a == ctr_addr) | (io_a == rxr_addr) |
						(io_a == sr_addr) | (io_a == txr_addr) |
						(io_a == cr_addr);
	





	reg  [15:0] prer;
	reg  [ 7:0] ctr;
	reg  [ 7:0] txr;
	wire [ 7:0] rxr;
	reg  [ 7:0] cr;
	wire [ 7:0] sr;


	wire done;


	wire core_en;
	wire ien;


	wire irxack;
	reg  rxack;
	reg  tip;
	reg  irq_flag;
	wire i2c_busy;
	wire i2c_al;
	reg  al;






	always @(posedge sys_clk)
	begin
	  io_do <= 8'd00;
	  if(io_re & csr_selected)
		case (io_a)
			prer_low_addr: 		io_do <= #1 prer[ 7:0];
			prer_high_addr: 	io_do <= #1 prer[15:8];
			ctr_addr: 			io_do <= #1 ctr;
			rxr_addr: 			io_do <= #1 rxr;
			sr_addr: 			io_do <= #1 sr;
			txr_addr: 			io_do <= #1 txr;
			cr_addr: 			io_do <= #1 cr;
			default: 			;
		endcase
	end


	always @(posedge sys_clk or posedge sys_rst)
	  if (sys_rst)
	    begin
	        prer <= #1 16'hffff;
	        ctr  <= #1  8'h0;
	        txr  <= #1  8'h0;
	    end
	  else
	    if (io_we & csr_selected)
	      case (io_a)
	         prer_low_addr : 	prer [ 7:0] <= #1 io_di;
	         prer_high_addr : 	prer [15:8] <= #1 io_di;
	         ctr_addr : 				ctr <= #1 io_di;
	         txr_addr : 				txr <= #1 io_di;
	         default: ;
	      endcase


	always @(posedge sys_clk or posedge sys_rst)
	  if (sys_rst)
	    cr <= #1 8'h0;
	  else if (io_we & (io_a == cr_addr))
	    begin
	        if (core_en)
	          cr <= #1 io_di;
	    end
	  else
	    begin
	        if (done | i2c_al)
	          cr[7:4] <= #1 4'h0;

	        cr[2:1] <= #1 2'b0;
	        cr[0]   <= #1 1'b0;
	    end



	wire sta  = cr[7];
	wire sto  = cr[6];
	wire rd   = cr[5];
	wire wr   = cr[4];
	wire ack  = cr[3];
	wire iack = cr[0];


	assign core_en = ctr[7];
	assign ien = ctr[6];


	i2c_master_byte_ctrl byte_controller (
		.clk      ( sys_clk     ),
		.rst      ( sys_rst     ),
		.ena      ( core_en      ),
		.clk_cnt  ( prer         ),
		.start    ( sta          ),
		.stop     ( sto          ),
		.read     ( rd           ),
		.write    ( wr           ),
		.ack_in   ( ack          ),
		.din      ( txr          ),
		.cmd_ack  ( done         ),
		.ack_out  ( irxack       ),
		.dout     ( rxr          ),
		.i2c_busy ( i2c_busy     ),
		.i2c_al   ( i2c_al       ),
		.scl_i    ( scl_i    ),
		.scl_o    ( scl_o    ),
		.scl_oen  ( scl_oen_o ),
		.sda_i    ( sda_i    ),
		.sda_o    ( sda_o    ),
		.sda_oen  ( sda_oen_o )
	);


	always @(posedge sys_clk or posedge sys_rst)
	  if (sys_rst)
	    begin
	        al       <= #1 1'b0;
	        rxack    <= #1 1'b0;
	        tip      <= #1 1'b0;
	        irq_flag <= #1 1'b0;
	    end
	  else
	    begin
	        al       <= #1 i2c_al | (al & ~sta);
	        rxack    <= #1 irxack;
	        tip      <= #1 (rd | wr);
	        irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack;
	    end


	always @(posedge sys_clk or posedge sys_rst)
	  if (sys_rst)
	    i2c_irq <= #1 1'b0;
	  else
	    i2c_irq <= #1 irq_flag && ien;


	assign sr[7]   = rxack;
	assign sr[6]   = i2c_busy;
	assign sr[5]   = al;
	assign sr[4:2] = 3'h0;
	assign sr[1]   = tip;
	assign sr[0]   = irq_flag;

endmodule