data/full_repos/permissive/210428910/cpu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210428910/cpu.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #10  clk = ~clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/210428910/cpu.v:19: Cannot find file containing module: \'controller\'\n  controller c(clk, ins[15:12], C, Z, C, controll);\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210428910,data/full_repos/permissive/210428910/controller\n             data/full_repos/permissive/210428910,data/full_repos/permissive/210428910/controller.v\n             data/full_repos/permissive/210428910,data/full_repos/permissive/210428910/controller.sv\n             controller\n             controller.v\n             controller.sv\n             obj_dir/controller\n             obj_dir/controller.v\n             obj_dir/controller.sv\n%Error: data/full_repos/permissive/210428910/cpu.v:20: Cannot find file containing module: \'data_memory\'\n  data_memory dm(clk, ins[11:0], A[11:0], A, T, controll, data);\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/210428910/cpu.v:21: Cannot find file containing module: \'alu\'\n  alu al(clk, controll[7:5], A, data, C, C, Z, aluout);\n  ^~~\n%Warning-WIDTH: data/full_repos/permissive/210428910/cpu.v:39: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'data\' generates 16 bits.\n                                                             : ... In instance cpu\n      2\'b01: PC = data;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/210428910/cpu.v:43: Bit extraction of array[4096:0] requires 13 bit index, not 12 bits.\n                                                             : ... In instance cpu\n    ins = ins_mem[PC];\n                 ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu (output reg [15:0] A, T, ins, output reg [11:0] PC, output reg clk);

  reg [15:0] ins_mem [0:4096];
  wire [15:0] aluout;
  wire [11:0] controll;
  wire C, Z;
  wire [15:0] data;

  initial begin
    clk = 0;
    $readmemb("C:/Users/Mortaza/Desktop/untitled2/src/ins.txt", ins_mem);
    PC = 12'b0;
    ins = ins_mem[0];
    forever begin
      #10  clk = ~clk;
    end
  end

  controller c(clk, ins[15:12], C, Z, C, controll);
  data_memory dm(clk, ins[11:0], A[11:0], A, T, controll, data);
  alu al(clk, controll[7:5], A, data, C, C, Z, aluout);

  always @ (posedge clk) begin

    if (controll[3] == 0 && controll[2] == 1) begin
      A = aluout;
    end

    if (controll[3] == 1 && controll[2] == 1) begin
      A = data;
    end

    if (controll[4] == 1) begin
      T = A;
    end

    case (controll[1:0])
      2'b00: PC = PC + 1;
      2'b01: PC = data;
      2'b10: PC = ins[11:0];
    endcase

    ins = ins_mem[PC];

    if (^ins === 1'bx) begin
        $stop(2);
    end

  end

endmodule
module cpu (output reg [15:0] A, T, ins, output reg [11:0] PC, output reg clk);


  reg [15:0] ins_mem [0:4096];
  wire [15:0] aluout;
  wire [11:0] controll;
  wire C, Z;
  wire [15:0] data;

  initial begin
    clk = 0;
    $readmemb("C:/Users/Mortaza/Desktop/untitled2/src/ins.txt", ins_mem);
    PC = 12'b0;
    ins = ins_mem[0];
    forever begin
      #10  clk = ~clk;
    end
  end

  controller c(clk, ins[15:12], C, Z, C, controll);
  data_memory dm(clk, ins[11:0], A[11:0], A, T, controll, data);
  alu al(clk, controll[7:5], A, data, C, C, Z, aluout);

  always @ (posedge clk) begin

    if (controll[3] == 0 && controll[2] == 1) begin
      A = aluout;
    end

    if (controll[3] == 1 && controll[2] == 1) begin
      A = data;
    end

    if (controll[4] == 1) begin
      T = A;
    end

    case (controll[1:0])
      2'b00: PC = PC + 1;
      2'b01: PC = data;
      2'b10: PC = ins[11:0];
    endcase

    ins = ins_mem[PC];

    if (^ins === 1'bx) begin
        $stop(2);
    end

  end

endmodule