data/full_repos/permissive/177289247/EXMEMReg.v
data/verilator_xmls/758ff1a2-dd64-4927-a328-354292f3b713.xml
module EXMEMReg (
    input       clk,

    input       rst,

    input       Branch_in,
    input       MemRead_in,
    input       MemWrite_in,

    input       RegWrite_in,

    input       Zero_in,

    input[31:0] ALU_in,
    input[31:0] FwdBOut_in,
    input[4:0]  Rd_in,


    output      Branch_out,
    output      MemRead_out,
    output      MemWrite_out,

    output      RegWrite_out,

    output       Zero_out,

    output[31:0]ALU_out,
    output[31:0]FwdBOut_out,
    output[4:0] Rd_out
);


reg[73:0] StageReg;
assign {
    Branch_out            ,
    MemRead_out           ,
    MemWrite_out          ,
    RegWrite_out          ,
    Zero_out              ,
    ALU_out         [31:0],
    FwdBOut_out     [31:0],
    Rd_out          [4:0]
} = StageReg;

always @(posedge rst) begin
    StageReg <= 74'b0;
end

initial begin
    StageReg <= 74'b0;
end

always @(posedge clk) begin
    StageReg <= {
        Branch_in         ,
        MemRead_in        ,
        MemWrite_in       ,
        RegWrite_in       ,
        Zero_in           ,
        ALU_in      [31:0],
        FwdBOut_in  [31:0],
        Rd_in       [4:0]
    };
end



endmodule
module EXMEMReg (
    input       clk,

    input       rst,

    input       Branch_in,
    input       MemRead_in,
    input       MemWrite_in,

    input       RegWrite_in,

    input       Zero_in,

    input[31:0] ALU_in,
    input[31:0] FwdBOut_in,
    input[4:0]  Rd_in,


    output      Branch_out,
    output      MemRead_out,
    output      MemWrite_out,

    output      RegWrite_out,

    output       Zero_out,

    output[31:0]ALU_out,
    output[31:0]FwdBOut_out,
    output[4:0] Rd_out
);



reg[73:0] StageReg;
assign {
    Branch_out            ,
    MemRead_out           ,
    MemWrite_out          ,
    RegWrite_out          ,
    Zero_out              ,
    ALU_out         [31:0],
    FwdBOut_out     [31:0],
    Rd_out          [4:0]
} = StageReg;

always @(posedge rst) begin
    StageReg <= 74'b0;
end

initial begin
    StageReg <= 74'b0;
end

always @(posedge clk) begin
    StageReg <= {
        Branch_in         ,
        MemRead_in        ,
        MemWrite_in       ,
        RegWrite_in       ,
        Zero_in           ,
        ALU_in      [31:0],
        FwdBOut_in  [31:0],
        Rd_in       [4:0]
    };
end



endmodule