data/full_repos/permissive/13201424/vlog/eth_mac_rx_crc.v
1: b"%Error: data/full_repos/permissive/13201424/vlog/eth_mac_rx_crc.v:77: Can't find definition of variable: 'RX_STATE_PREAMBLE'\n                                                                    : ... Suggested alternative: 'STATE_PREAMBLE'\n      state <= RX_STATE_PREAMBLE;\n               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13201424/vlog/eth_mac_rx_crc.v:138: Can't find definition of variable: 'fifo_rd_empty'\n                                                                     : ... Suggested alternative: 'fifo_empty'\n wire fifo_rdy = !full_in && !fifo_rd_empty;\n                              ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module eth_mac_rx (
	input clk,
	input rst,
	
	input eth_rx_clk_in,
	input [7:0] eth_rx_d_in,
	input eth_rx_err_in,
	input eth_rx_dv_in,
	
	output reg wr_en_out,
	output reg [10:0] wr_addr_out,
	output [7:0] wr_d_out,

	output reg done_out,
	input full_in
);

	localparam STATE_IDLE = 2'd0;
	localparam STATE_PREAMBLE = 2'd1;
	localparam STATE_DATA = 2'd2;
	localparam STATE_ERR = 2'd3;
	
	reg [1:0] state;

	reg fifo_wr_en, fifo_rd_en;
	reg [8:0] fifo_wr_d;
	wire [8:0] fifo_rd_d;
	wire fifo_full, fifo_empty;
	
	fifo_9x16 eth_rx_fifo (
	  .rst(rst),
	  .wr_clk(eth_rx_clk_in),
	  .rd_clk(clk),
	  .din(fifo_wr_d),
	  .wr_en(fifo_wr_en),
	  .rd_en(fifo_rd_en),
	  .dout(fifo_rd_d),
	  .full(fifo_full),
	  .empty(fifo_empty)
  );
  


	always @ (posedge eth_rx_clk_in or posedge rst) begin
		if (rst) begin
			state <= STATE_IDLE;
			fifo_wr_en <= 0;
			fifo_wr_d <= 0;
		end else begin
			case (state)




				STATE_IDLE: begin
					fifo_wr_en <= 0;
					if (eth_rx_dv_in && !eth_rx_err_in && (eth_rx_d_in == 8'hAA))
						state <= RX_STATE_PREAMBLE;
				end
				



				STATE_PREAMBLE: begin
					if (eth_rx_err_in || !eth_rx_dv_in)
						state <= STATE_ERR;
					else if (eth_rx_d_in == 8'haa)
						state <= STATE_PREAMBLE;
					else if (eth_rx_d_in == 8'hab && !fifo_full) begin


						state <= STATE_DATA;

						fifo_wr_en <= 1;
						fifo_wr_d <= 9'h100;
					end else
						state <= STATE_ERR;
				end
				

				STATE_DATA: begin
					if (eth_rx_err_in || fifo_full) begin
						state <= STATE_ERR;
						fifo_wr_en <= 0;
					end else if (!eth_rx_dv_in) begin
						state <= STATE_IDLE;

						fifo_wr_d <= 9'h101;
						fifo_wr_en <= 1;
					end else begin
						fifo_wr_d <= {1'b0, eth_rx_d_in};
						fifo_wr_en <= 1;
					end
				end
				

				STATE_ERR: begin




					if (!eth_rx_dv_in && !eth_rx_err_in && !fifo_full) begin
						state <= STATE_IDLE;

						fifo_wr_d <= 9'h1ff;
						fifo_wr_en <= 1;
					end
				end
			endcase
		end
	end
	
	
	reg [31:0] crc;
	wire crc_ok_next = (crc == 32'hc704dd7b);
	reg crc_ok, error, eof;
	reg [7:0] length_lower;
	
	wire fifo_rdy = !full_in && !fifo_rd_empty;
	wire ctl_rdy = fifo_rdy && fifo_rd_d[8];
	wire data_rdy = fifo_rdy && !fifo_rd_d[8];



	always @ (posedge clk or posedge rst) begin

		if (rst) begin
			fifo_rd_en <= 0;
			done_out <= 0;
			wr_en_out <= 0;
			wr_addr_out <= 11'd2;
			wr_d_out <= 0;
			crc <= 32'hffffffff;
			crc_ok <= 0;
			error <= 0;
			length_lower <= 0;
			eof <= 0;
		
		end else begin
			



			if (eof) begin
				fifo_rd_en <= 0;
				done_out <= 1;
				
				wr_addr_out <= 11'd1;
				wr_d_out <= length_lower;
				eof <= 0;
				
			end else if (ctl_rdy) begin
				fifo_rd_en <= 1;
				done_out <= 0;
				
				case (fifo_rd_d[1:0])
				

					2'b00: begin
						done_out <= 0;
						wr_en_out <= 0;
						wr_addr_out <= 11'd2;
						wr_d_out <= 0;
						crc <= 32'hffffffff;
						crc_ok <= 0;
						error <= 0;
					end
					



					2'b01: begin
						if (!error && crc_ok) begin
							eof <= 1;
							wr_en_out <= 1;
							wr_addr_out <= 11'd0;
							wr_d_out[7:3] <= 5'h00;
							{wr_d_out[2:0], length_lower} <= wr_addr_out - 11'd16;
						end
					end
					

					default: begin
						error <= 1;
						wr_en_out <= 0;
					end
				endcase
			
			end else if (data_rdy) begin
				fifo_rd_en <= 1;
				done_out <= 0;
				



				
				wr_addr_out <= wr_addr_out + 11'd1;
				wr_d_out <= fifo_rd_d;
				wr_en_out <= 1;
				

				crc[0] <= fifo_rd_d[6] ^ fifo_rd_d[0] ^ crc[24] ^ crc[30];
				crc[1] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[24] ^ crc[25] ^ crc[30] ^ crc[31];
				crc[2] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[24] ^ crc[25] ^ crc[26] ^ crc[30] ^ crc[31];
				crc[3] <= fifo_rd_d[7] ^ fifo_rd_d[3] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ crc[25] ^ crc[26] ^ crc[27] ^ crc[31];
				crc[4] <= fifo_rd_d[6] ^ fifo_rd_d[4] ^ fifo_rd_d[3] ^ fifo_rd_d[2] ^ fifo_rd_d[0] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[28] ^ crc[30];
				crc[5] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[3] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28] ^ crc[29] ^ crc[30] ^ crc[31];
				crc[6] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ crc[30] ^ crc[31];
				crc[7] <= fifo_rd_d[7] ^ fifo_rd_d[5] ^ fifo_rd_d[3] ^ fifo_rd_d[2] ^ fifo_rd_d[0] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[29] ^ crc[31];
				crc[8] <= fifo_rd_d[4] ^ fifo_rd_d[3] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[0] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28];
				crc[9] <= fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ crc[1] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29];
				crc[10] <= fifo_rd_d[5] ^ fifo_rd_d[3] ^ fifo_rd_d[2] ^ fifo_rd_d[0] ^ crc[2] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[29];
				crc[11] <= fifo_rd_d[4] ^ fifo_rd_d[3] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[3] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28];
				crc[12] <= fifo_rd_d[6] ^ fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[4] ^ crc[24] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ crc[30];
				crc[13] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[5] ^ fifo_rd_d[3] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ crc[5] ^ crc[25] ^ crc[26] ^ crc[27] ^ crc[29] ^ crc[30] ^ crc[31];
				crc[14] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[4] ^ fifo_rd_d[3] ^ fifo_rd_d[2] ^ crc[6] ^ crc[26] ^ crc[27] ^ crc[28] ^ crc[30] ^ crc[31];
				crc[15] <= fifo_rd_d[7] ^ fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[3] ^ crc[7] ^ crc[27] ^ crc[28] ^ crc[29] ^ crc[31];
				crc[16] <= fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[0] ^ crc[8] ^ crc[24] ^ crc[28] ^ crc[29];
				crc[17] <= fifo_rd_d[6] ^ fifo_rd_d[5] ^ fifo_rd_d[1] ^ crc[9] ^ crc[25] ^ crc[29] ^ crc[30];
				crc[18] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[2] ^ crc[10] ^ crc[26] ^ crc[30] ^ crc[31];
				crc[19] <= fifo_rd_d[7] ^ fifo_rd_d[3] ^ crc[11] ^ crc[27] ^ crc[31];
				crc[20] <= fifo_rd_d[4] ^ crc[12] ^ crc[28];
				crc[21] <= fifo_rd_d[5] ^ crc[13] ^ crc[29];
				crc[22] <= fifo_rd_d[0] ^ crc[14] ^ crc[24];
				crc[23] <= fifo_rd_d[6] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[15] ^ crc[24] ^ crc[25] ^ crc[30];
				crc[24] <= fifo_rd_d[7] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ crc[16] ^ crc[25] ^ crc[26] ^ crc[31];
				crc[25] <= fifo_rd_d[3] ^ fifo_rd_d[2] ^ crc[17] ^ crc[26] ^ crc[27];
				crc[26] <= fifo_rd_d[6] ^ fifo_rd_d[4] ^ fifo_rd_d[3] ^ fifo_rd_d[0] ^ crc[18] ^ crc[24] ^ crc[27] ^ crc[28] ^ crc[30];
				crc[27] <= fifo_rd_d[7] ^ fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[1] ^ crc[19] ^ crc[25] ^ crc[28] ^ crc[29] ^ crc[31];
				crc[28] <= fifo_rd_d[6] ^ fifo_rd_d[5] ^ fifo_rd_d[2] ^ crc[20] ^ crc[26] ^ crc[29] ^ crc[30];
				crc[29] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[3] ^ crc[21] ^ crc[27] ^ crc[30] ^ crc[31];
				crc[30] <= fifo_rd_d[7] ^ fifo_rd_d[4] ^ crc[22] ^ crc[28] ^ crc[31];
				crc[31] <= fifo_rd_d[5] ^ crc[23] ^ crc[29];
				
				crc_ok <= crc_ok_next;
				
			end else begin

				fifo_rd_en <= 0;
				done_out <= 0;
			end
		end
	end
endmodule
module eth_mac_rx (
	input clk,
	input rst,
	
	input eth_rx_clk_in,
	input [7:0] eth_rx_d_in,
	input eth_rx_err_in,
	input eth_rx_dv_in,
	
	output reg wr_en_out,
	output reg [10:0] wr_addr_out,
	output [7:0] wr_d_out,

	output reg done_out,
	input full_in
);


	localparam STATE_IDLE = 2'd0;
	localparam STATE_PREAMBLE = 2'd1;
	localparam STATE_DATA = 2'd2;
	localparam STATE_ERR = 2'd3;
	
	reg [1:0] state;

	reg fifo_wr_en, fifo_rd_en;
	reg [8:0] fifo_wr_d;
	wire [8:0] fifo_rd_d;
	wire fifo_full, fifo_empty;
	
	fifo_9x16 eth_rx_fifo (
	  .rst(rst),
	  .wr_clk(eth_rx_clk_in),
	  .rd_clk(clk),
	  .din(fifo_wr_d),
	  .wr_en(fifo_wr_en),
	  .rd_en(fifo_rd_en),
	  .dout(fifo_rd_d),
	  .full(fifo_full),
	  .empty(fifo_empty)
  );
  


	always @ (posedge eth_rx_clk_in or posedge rst) begin
		if (rst) begin
			state <= STATE_IDLE;
			fifo_wr_en <= 0;
			fifo_wr_d <= 0;
		end else begin
			case (state)




				STATE_IDLE: begin
					fifo_wr_en <= 0;
					if (eth_rx_dv_in && !eth_rx_err_in && (eth_rx_d_in == 8'hAA))
						state <= RX_STATE_PREAMBLE;
				end
				



				STATE_PREAMBLE: begin
					if (eth_rx_err_in || !eth_rx_dv_in)
						state <= STATE_ERR;
					else if (eth_rx_d_in == 8'haa)
						state <= STATE_PREAMBLE;
					else if (eth_rx_d_in == 8'hab && !fifo_full) begin


						state <= STATE_DATA;

						fifo_wr_en <= 1;
						fifo_wr_d <= 9'h100;
					end else
						state <= STATE_ERR;
				end
				

				STATE_DATA: begin
					if (eth_rx_err_in || fifo_full) begin
						state <= STATE_ERR;
						fifo_wr_en <= 0;
					end else if (!eth_rx_dv_in) begin
						state <= STATE_IDLE;

						fifo_wr_d <= 9'h101;
						fifo_wr_en <= 1;
					end else begin
						fifo_wr_d <= {1'b0, eth_rx_d_in};
						fifo_wr_en <= 1;
					end
				end
				

				STATE_ERR: begin




					if (!eth_rx_dv_in && !eth_rx_err_in && !fifo_full) begin
						state <= STATE_IDLE;

						fifo_wr_d <= 9'h1ff;
						fifo_wr_en <= 1;
					end
				end
			endcase
		end
	end
	
	
	reg [31:0] crc;
	wire crc_ok_next = (crc == 32'hc704dd7b);
	reg crc_ok, error, eof;
	reg [7:0] length_lower;
	
	wire fifo_rdy = !full_in && !fifo_rd_empty;
	wire ctl_rdy = fifo_rdy && fifo_rd_d[8];
	wire data_rdy = fifo_rdy && !fifo_rd_d[8];



	always @ (posedge clk or posedge rst) begin

		if (rst) begin
			fifo_rd_en <= 0;
			done_out <= 0;
			wr_en_out <= 0;
			wr_addr_out <= 11'd2;
			wr_d_out <= 0;
			crc <= 32'hffffffff;
			crc_ok <= 0;
			error <= 0;
			length_lower <= 0;
			eof <= 0;
		
		end else begin
			



			if (eof) begin
				fifo_rd_en <= 0;
				done_out <= 1;
				
				wr_addr_out <= 11'd1;
				wr_d_out <= length_lower;
				eof <= 0;
				
			end else if (ctl_rdy) begin
				fifo_rd_en <= 1;
				done_out <= 0;
				
				case (fifo_rd_d[1:0])
				

					2'b00: begin
						done_out <= 0;
						wr_en_out <= 0;
						wr_addr_out <= 11'd2;
						wr_d_out <= 0;
						crc <= 32'hffffffff;
						crc_ok <= 0;
						error <= 0;
					end
					



					2'b01: begin
						if (!error && crc_ok) begin
							eof <= 1;
							wr_en_out <= 1;
							wr_addr_out <= 11'd0;
							wr_d_out[7:3] <= 5'h00;
							{wr_d_out[2:0], length_lower} <= wr_addr_out - 11'd16;
						end
					end
					

					default: begin
						error <= 1;
						wr_en_out <= 0;
					end
				endcase
			
			end else if (data_rdy) begin
				fifo_rd_en <= 1;
				done_out <= 0;
				



				
				wr_addr_out <= wr_addr_out + 11'd1;
				wr_d_out <= fifo_rd_d;
				wr_en_out <= 1;
				

				crc[0] <= fifo_rd_d[6] ^ fifo_rd_d[0] ^ crc[24] ^ crc[30];
				crc[1] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[24] ^ crc[25] ^ crc[30] ^ crc[31];
				crc[2] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[24] ^ crc[25] ^ crc[26] ^ crc[30] ^ crc[31];
				crc[3] <= fifo_rd_d[7] ^ fifo_rd_d[3] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ crc[25] ^ crc[26] ^ crc[27] ^ crc[31];
				crc[4] <= fifo_rd_d[6] ^ fifo_rd_d[4] ^ fifo_rd_d[3] ^ fifo_rd_d[2] ^ fifo_rd_d[0] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[28] ^ crc[30];
				crc[5] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[3] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28] ^ crc[29] ^ crc[30] ^ crc[31];
				crc[6] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ crc[30] ^ crc[31];
				crc[7] <= fifo_rd_d[7] ^ fifo_rd_d[5] ^ fifo_rd_d[3] ^ fifo_rd_d[2] ^ fifo_rd_d[0] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[29] ^ crc[31];
				crc[8] <= fifo_rd_d[4] ^ fifo_rd_d[3] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[0] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28];
				crc[9] <= fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ crc[1] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29];
				crc[10] <= fifo_rd_d[5] ^ fifo_rd_d[3] ^ fifo_rd_d[2] ^ fifo_rd_d[0] ^ crc[2] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[29];
				crc[11] <= fifo_rd_d[4] ^ fifo_rd_d[3] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[3] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28];
				crc[12] <= fifo_rd_d[6] ^ fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[4] ^ crc[24] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ crc[30];
				crc[13] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[5] ^ fifo_rd_d[3] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ crc[5] ^ crc[25] ^ crc[26] ^ crc[27] ^ crc[29] ^ crc[30] ^ crc[31];
				crc[14] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[4] ^ fifo_rd_d[3] ^ fifo_rd_d[2] ^ crc[6] ^ crc[26] ^ crc[27] ^ crc[28] ^ crc[30] ^ crc[31];
				crc[15] <= fifo_rd_d[7] ^ fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[3] ^ crc[7] ^ crc[27] ^ crc[28] ^ crc[29] ^ crc[31];
				crc[16] <= fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[0] ^ crc[8] ^ crc[24] ^ crc[28] ^ crc[29];
				crc[17] <= fifo_rd_d[6] ^ fifo_rd_d[5] ^ fifo_rd_d[1] ^ crc[9] ^ crc[25] ^ crc[29] ^ crc[30];
				crc[18] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[2] ^ crc[10] ^ crc[26] ^ crc[30] ^ crc[31];
				crc[19] <= fifo_rd_d[7] ^ fifo_rd_d[3] ^ crc[11] ^ crc[27] ^ crc[31];
				crc[20] <= fifo_rd_d[4] ^ crc[12] ^ crc[28];
				crc[21] <= fifo_rd_d[5] ^ crc[13] ^ crc[29];
				crc[22] <= fifo_rd_d[0] ^ crc[14] ^ crc[24];
				crc[23] <= fifo_rd_d[6] ^ fifo_rd_d[1] ^ fifo_rd_d[0] ^ crc[15] ^ crc[24] ^ crc[25] ^ crc[30];
				crc[24] <= fifo_rd_d[7] ^ fifo_rd_d[2] ^ fifo_rd_d[1] ^ crc[16] ^ crc[25] ^ crc[26] ^ crc[31];
				crc[25] <= fifo_rd_d[3] ^ fifo_rd_d[2] ^ crc[17] ^ crc[26] ^ crc[27];
				crc[26] <= fifo_rd_d[6] ^ fifo_rd_d[4] ^ fifo_rd_d[3] ^ fifo_rd_d[0] ^ crc[18] ^ crc[24] ^ crc[27] ^ crc[28] ^ crc[30];
				crc[27] <= fifo_rd_d[7] ^ fifo_rd_d[5] ^ fifo_rd_d[4] ^ fifo_rd_d[1] ^ crc[19] ^ crc[25] ^ crc[28] ^ crc[29] ^ crc[31];
				crc[28] <= fifo_rd_d[6] ^ fifo_rd_d[5] ^ fifo_rd_d[2] ^ crc[20] ^ crc[26] ^ crc[29] ^ crc[30];
				crc[29] <= fifo_rd_d[7] ^ fifo_rd_d[6] ^ fifo_rd_d[3] ^ crc[21] ^ crc[27] ^ crc[30] ^ crc[31];
				crc[30] <= fifo_rd_d[7] ^ fifo_rd_d[4] ^ crc[22] ^ crc[28] ^ crc[31];
				crc[31] <= fifo_rd_d[5] ^ crc[23] ^ crc[29];
				
				crc_ok <= crc_ok_next;
				
			end else begin

				fifo_rd_en <= 0;
				done_out <= 0;
			end
		end
	end
endmodule