data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v
1: b'%Warning-WIDTH: data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v:757: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'6\'h2a\' generates 6 bits.\n                                                                              : ... In instance pipeline_riscv.ALU\n    case (alu_code)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/202942112/rtl/pipeline_riscv0.v:526: Operator EQ expects 6 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                              : ... In instance pipeline_riscv.CTRL\n    if (rd[1]!=0 && ((J_type[1] && funct[1]==7\'h08) || S_type[1]==6\'h2B)) begin\n                                                                ^~\n%Error: Exiting due to 2 warning(s)\n'
module pipeline_riscv (
  input          clk,
  input          nrst,
  input  [31:0]  inst,
  input  [31:0]  data_in,
  output [31:0]  inst_addr,
  output [31:0]  data_addr,
  output [31:0]  data_out,
  output         data_wr,
  output [31:0]  pc_IF,
  output [31:0]  pc_ID,
  output [31:0]  pc_EXE,
  output [31:0]  pc_MEM,
  output [31:0]  pc_WB
  );
  


  wire [2:0] sel_pc;
  wire [31:0] inst_IF, pc_p4_IF;
  reg [31:0] next_pc, jr_pc;
  wire [2:0] fwd_jr;
  

  wire wr_rf, jal, jr, sw, use_imm;
  wire [31:0] inst_ID;
  wire [31:0] pc_p4_ID, bra_off_ID, opA_ID, mem_data_ID;
  wire [31:0] wr_data, rfA, rfB;
  wire [31:0] opB_ID;
  wire [4:0] reg_addr_ID, wr_addr;
  
  wire [5:0] op;
  wire [4:0] rd, rs1, rs2;
  wire [6:0] funct;
  wire [31:0] imm_alu, imm_bra, imm_j;
  

  wire zero;
  wire [6:0] alu_code;
  wire [31:0] inst_EXE;
  wire [31:0] pc_p4_EXE, bra_off_EXE, opA_EXE, opB_EXE, mem_data_EXE0;
  wire [4:0] reg_addr_EXE;
  wire [31:0] bra_pc;
  wire [31:0] alu_out_EXE;
  wire [2:0] fwd_opA, fwd_opB, fwd_sw;
  reg [31:0] opA, opB;
  reg [31:0] mem_data_EXE;
  wire [31:0] fwd0;
  

  wire wr_mem, load, jal_pc;
  wire [31:0] inst_MEM;
  wire [31:0] pc_p4_MEM, mem_data_MEM, alu_out_MEM;
  wire [31:0] fwd1;
  wire [4:0] reg_addr_MEM;
  wire [31:0] reg_data_MEM;
  

  wire [31:0] inst_WB;
  wire [31:0] pc_p4_WB, reg_data_WB;
  wire [31:0] fwd2, fwd3;
  wire [4:0] reg_addr_WB;
  

  wire stall;
  wire [1:0] flush;
  

  
  assign pc_p4_IF = inst_addr + 4;
  assign pc_IF = inst_addr;
  
  always@(*) begin
    casez (sel_pc)
      3'b1zz:   next_pc = bra_pc;
      3'b01z:   next_pc = imm_j;
      3'b001:   next_pc = jr_pc;
      default:  next_pc = pc_p4_IF;
    endcase
  end
  
  always@(*) begin
    casez (fwd_jr)
      3'b1zz:   jr_pc = fwd2;
      3'b01z:   jr_pc = fwd1;
      3'b001:   jr_pc = fwd0;
      default:  jr_pc = rfB;
    endcase
  end
  
  reg32 PC (
    .clk(clk),
    .nrst(nrst),
    .en(!stall),
    .data_in(next_pc),
    .data_out(inst_addr)
  );
    

  
  assign op       = inst_ID[5:0];
  assign rd       = inst_ID[10:6];
  assign rs1      = jal ? 0 : inst_ID[19:15];
  assign rs2      = (jr | sw) ? rd : inst_ID[24:20];
  assign funct    = inst_ID[31:25];
  assign imm_alu  = { {16{inst_ID[31]}}, inst_ID[31:20], inst_ID[14:11] };
  assign imm_bra  = { {16{inst_ID[31]}}, inst_ID[31:25], inst_ID[14:6] };
  assign imm_j    = { {6{inst_ID[31]}}, inst_ID[31:6] };
  
  assign bra_off_ID = imm_bra;
  assign opA_ID = rfA;
  assign opB_ID = jal ? pc_p4_ID : (use_imm ? imm_alu : rfB);
  assign mem_data_ID = rfB;
  assign reg_addr_ID = jal ? 1 : rd;
  
  if_id_reg IF_ID (
    .clk(clk),
    .nrst(nrst),
    .en(!stall),
    .flush(flush[1]),
    .cur_pc0(pc_IF),
    .cur_pc(pc_ID),
    .next_pc0(pc_p4_IF),
    .next_pc(pc_p4_ID)
  );
  
  rf RF (
    .clk(clk),
    .nrst(nrst),
    .rd_addrA(rs1),
    .rd_addrB(rs2),
    .wr_en(wr_rf),
    .wr_addr(reg_addr_WB),
    .wr_data(reg_data_WB),
    .rd_dataA(rfA),
    .rd_dataB(rfB)
  );
  

  
  assign bra_pc = pc_p4_EXE + bra_off_EXE;
  assign fwd0 = alu_out_EXE;
  
  always@(*) begin
    casez (fwd_opA)
      3'b1zz:   opA = fwd1;
      3'b01z:   opA = fwd2;
      3'b001:   opA = fwd3;
      default:  opA = opA_EXE;
    endcase
  end
  
  always@(*) begin
    casez (fwd_opB)
      3'b1zz:   opB = fwd1;
      3'b01z:   opB = fwd2;
      3'b001:   opB = fwd3;
      default:  opB = opB_EXE;
    endcase
  end
    
  always@(*) begin
    casez (fwd_sw)
      3'b1zz:   mem_data_EXE = fwd1;
      3'b01z:   mem_data_EXE = fwd2;
      3'b001:   mem_data_EXE = fwd3;
      default:  mem_data_EXE = mem_data_EXE0;
    endcase
  end
  
  id_exe_reg ID_EXE (
    .clk(clk),
    .nrst(nrst),
    .en(!stall),
    .flush(flush[0]),
    .cur_pc0(pc_ID),
    .cur_pc(pc_EXE),
    .next_pc0(pc_p4_ID),
    .next_pc(pc_p4_EXE),
    .bra_off0(bra_off_ID),
    .bra_off(bra_off_EXE),
    .opA0(opA_ID),
    .opA(opA_EXE),
    .opB0(opB_ID),
    .opB(opB_EXE),
    .mem_data0(mem_data_ID),
    .mem_data(mem_data_EXE0),
    .reg_addr0(reg_addr_ID),
    .reg_addr(reg_addr_EXE)
  );
  
  alu ALU (
    .opA(opA),
    .opB(opB),
    .res(alu_out_EXE),
    .alu_code(alu_code),
    .z(zero)
  );
  

  
  assign reg_data_MEM = load ? data_in : (jal_pc ? pc_p4_MEM : alu_out_MEM);
  assign data_addr = alu_out_MEM;
  assign data_out = mem_data_MEM;
  assign data_wr = wr_mem;
  
  assign fwd1 = alu_out_MEM;

  exe_mem_reg EXE_MEM (
    .clk(clk),
    .nrst(nrst),
    .cur_pc0(pc_EXE),
    .cur_pc(pc_MEM),
    .next_pc0(pc_p4_EXE),
    .next_pc(pc_p4_MEM),
    .alu_out0(alu_out_EXE),
    .alu_out(alu_out_MEM),
    .mem_data0(mem_data_EXE),
    .mem_data(mem_data_MEM),
    .reg_addr0(reg_addr_EXE),
    .reg_addr(reg_addr_MEM)
  );
  

  
  assign fwd2 = reg_data_WB;
  
  mem_wb_reg MEM_WB (
    .clk(clk),
    .nrst(nrst),
    .cur_pc0(pc_MEM),
    .cur_pc(pc_WB),
    .next_pc0(pc_p4_MEM),
    .next_pc(pc_p4_WB),
    .reg_data0(reg_data_MEM),
    .reg_data(reg_data_WB),
    .reg_addr0(reg_addr_MEM),
    .reg_addr(reg_addr_WB)
  );
  
  reg32 FWD_WB (
    .clk(clk),
    .nrst(nrst),
    .en(1'b1),
    .data_in(reg_data_WB),
    .data_out(fwd3)
  );
  

  
  assign data_wr = wr_mem;
  
  control CTRL (
    .clk(clk),
    .nrst(nrst),
    .zero(zero),
    .inst(inst),
    .debug_inst({ inst_WB, inst_MEM, inst_EXE, inst_ID, inst_IF }),
    .alu_code(alu_code),
    .sel_pc(sel_pc),
    .stall(stall),
    .flush(flush),
    .wr_rf(wr_rf),
    .wr_mem(wr_mem),
    .use_imm(use_imm),
    .load(load),
    .jal(jal),
    .jal_pc(jal_pc),
    .jr(jr),
    .fwd_opA(fwd_opA),
    .fwd_opB(fwd_opB),
    .fwd_sw(fwd_sw),
    .fwd_jr(fwd_jr),
    .sw(sw)
  );

endmodule
module pipeline_riscv (
  input          clk,
  input          nrst,
  input  [31:0]  inst,
  input  [31:0]  data_in,
  output [31:0]  inst_addr,
  output [31:0]  data_addr,
  output [31:0]  data_out,
  output         data_wr,
  output [31:0]  pc_IF,
  output [31:0]  pc_ID,
  output [31:0]  pc_EXE,
  output [31:0]  pc_MEM,
  output [31:0]  pc_WB
  );

  


  wire [2:0] sel_pc;
  wire [31:0] inst_IF, pc_p4_IF;
  reg [31:0] next_pc, jr_pc;
  wire [2:0] fwd_jr;
  

  wire wr_rf, jal, jr, sw, use_imm;
  wire [31:0] inst_ID;
  wire [31:0] pc_p4_ID, bra_off_ID, opA_ID, mem_data_ID;
  wire [31:0] wr_data, rfA, rfB;
  wire [31:0] opB_ID;
  wire [4:0] reg_addr_ID, wr_addr;
  
  wire [5:0] op;
  wire [4:0] rd, rs1, rs2;
  wire [6:0] funct;
  wire [31:0] imm_alu, imm_bra, imm_j;
  

  wire zero;
  wire [6:0] alu_code;
  wire [31:0] inst_EXE;
  wire [31:0] pc_p4_EXE, bra_off_EXE, opA_EXE, opB_EXE, mem_data_EXE0;
  wire [4:0] reg_addr_EXE;
  wire [31:0] bra_pc;
  wire [31:0] alu_out_EXE;
  wire [2:0] fwd_opA, fwd_opB, fwd_sw;
  reg [31:0] opA, opB;
  reg [31:0] mem_data_EXE;
  wire [31:0] fwd0;
  

  wire wr_mem, load, jal_pc;
  wire [31:0] inst_MEM;
  wire [31:0] pc_p4_MEM, mem_data_MEM, alu_out_MEM;
  wire [31:0] fwd1;
  wire [4:0] reg_addr_MEM;
  wire [31:0] reg_data_MEM;
  

  wire [31:0] inst_WB;
  wire [31:0] pc_p4_WB, reg_data_WB;
  wire [31:0] fwd2, fwd3;
  wire [4:0] reg_addr_WB;
  

  wire stall;
  wire [1:0] flush;
  

  
  assign pc_p4_IF = inst_addr + 4;
  assign pc_IF = inst_addr;
  
  always@(*) begin
    casez (sel_pc)
      3'b1zz:   next_pc = bra_pc;
      3'b01z:   next_pc = imm_j;
      3'b001:   next_pc = jr_pc;
      default:  next_pc = pc_p4_IF;
    endcase
  end
  
  always@(*) begin
    casez (fwd_jr)
      3'b1zz:   jr_pc = fwd2;
      3'b01z:   jr_pc = fwd1;
      3'b001:   jr_pc = fwd0;
      default:  jr_pc = rfB;
    endcase
  end
  
  reg32 PC (
    .clk(clk),
    .nrst(nrst),
    .en(!stall),
    .data_in(next_pc),
    .data_out(inst_addr)
  );
    

  
  assign op       = inst_ID[5:0];
  assign rd       = inst_ID[10:6];
  assign rs1      = jal ? 0 : inst_ID[19:15];
  assign rs2      = (jr | sw) ? rd : inst_ID[24:20];
  assign funct    = inst_ID[31:25];
  assign imm_alu  = { {16{inst_ID[31]}}, inst_ID[31:20], inst_ID[14:11] };
  assign imm_bra  = { {16{inst_ID[31]}}, inst_ID[31:25], inst_ID[14:6] };
  assign imm_j    = { {6{inst_ID[31]}}, inst_ID[31:6] };
  
  assign bra_off_ID = imm_bra;
  assign opA_ID = rfA;
  assign opB_ID = jal ? pc_p4_ID : (use_imm ? imm_alu : rfB);
  assign mem_data_ID = rfB;
  assign reg_addr_ID = jal ? 1 : rd;
  
  if_id_reg IF_ID (
    .clk(clk),
    .nrst(nrst),
    .en(!stall),
    .flush(flush[1]),
    .cur_pc0(pc_IF),
    .cur_pc(pc_ID),
    .next_pc0(pc_p4_IF),
    .next_pc(pc_p4_ID)
  );
  
  rf RF (
    .clk(clk),
    .nrst(nrst),
    .rd_addrA(rs1),
    .rd_addrB(rs2),
    .wr_en(wr_rf),
    .wr_addr(reg_addr_WB),
    .wr_data(reg_data_WB),
    .rd_dataA(rfA),
    .rd_dataB(rfB)
  );
  

  
  assign bra_pc = pc_p4_EXE + bra_off_EXE;
  assign fwd0 = alu_out_EXE;
  
  always@(*) begin
    casez (fwd_opA)
      3'b1zz:   opA = fwd1;
      3'b01z:   opA = fwd2;
      3'b001:   opA = fwd3;
      default:  opA = opA_EXE;
    endcase
  end
  
  always@(*) begin
    casez (fwd_opB)
      3'b1zz:   opB = fwd1;
      3'b01z:   opB = fwd2;
      3'b001:   opB = fwd3;
      default:  opB = opB_EXE;
    endcase
  end
    
  always@(*) begin
    casez (fwd_sw)
      3'b1zz:   mem_data_EXE = fwd1;
      3'b01z:   mem_data_EXE = fwd2;
      3'b001:   mem_data_EXE = fwd3;
      default:  mem_data_EXE = mem_data_EXE0;
    endcase
  end
  
  id_exe_reg ID_EXE (
    .clk(clk),
    .nrst(nrst),
    .en(!stall),
    .flush(flush[0]),
    .cur_pc0(pc_ID),
    .cur_pc(pc_EXE),
    .next_pc0(pc_p4_ID),
    .next_pc(pc_p4_EXE),
    .bra_off0(bra_off_ID),
    .bra_off(bra_off_EXE),
    .opA0(opA_ID),
    .opA(opA_EXE),
    .opB0(opB_ID),
    .opB(opB_EXE),
    .mem_data0(mem_data_ID),
    .mem_data(mem_data_EXE0),
    .reg_addr0(reg_addr_ID),
    .reg_addr(reg_addr_EXE)
  );
  
  alu ALU (
    .opA(opA),
    .opB(opB),
    .res(alu_out_EXE),
    .alu_code(alu_code),
    .z(zero)
  );
  

  
  assign reg_data_MEM = load ? data_in : (jal_pc ? pc_p4_MEM : alu_out_MEM);
  assign data_addr = alu_out_MEM;
  assign data_out = mem_data_MEM;
  assign data_wr = wr_mem;
  
  assign fwd1 = alu_out_MEM;

  exe_mem_reg EXE_MEM (
    .clk(clk),
    .nrst(nrst),
    .cur_pc0(pc_EXE),
    .cur_pc(pc_MEM),
    .next_pc0(pc_p4_EXE),
    .next_pc(pc_p4_MEM),
    .alu_out0(alu_out_EXE),
    .alu_out(alu_out_MEM),
    .mem_data0(mem_data_EXE),
    .mem_data(mem_data_MEM),
    .reg_addr0(reg_addr_EXE),
    .reg_addr(reg_addr_MEM)
  );
  

  
  assign fwd2 = reg_data_WB;
  
  mem_wb_reg MEM_WB (
    .clk(clk),
    .nrst(nrst),
    .cur_pc0(pc_MEM),
    .cur_pc(pc_WB),
    .next_pc0(pc_p4_MEM),
    .next_pc(pc_p4_WB),
    .reg_data0(reg_data_MEM),
    .reg_data(reg_data_WB),
    .reg_addr0(reg_addr_MEM),
    .reg_addr(reg_addr_WB)
  );
  
  reg32 FWD_WB (
    .clk(clk),
    .nrst(nrst),
    .en(1'b1),
    .data_in(reg_data_WB),
    .data_out(fwd3)
  );
  

  
  assign data_wr = wr_mem;
  
  control CTRL (
    .clk(clk),
    .nrst(nrst),
    .zero(zero),
    .inst(inst),
    .debug_inst({ inst_WB, inst_MEM, inst_EXE, inst_ID, inst_IF }),
    .alu_code(alu_code),
    .sel_pc(sel_pc),
    .stall(stall),
    .flush(flush),
    .wr_rf(wr_rf),
    .wr_mem(wr_mem),
    .use_imm(use_imm),
    .load(load),
    .jal(jal),
    .jal_pc(jal_pc),
    .jr(jr),
    .fwd_opA(fwd_opA),
    .fwd_opB(fwd_opB),
    .fwd_sw(fwd_sw),
    .fwd_jr(fwd_jr),
    .sw(sw)
  );

endmodule