data/full_repos/permissive/157608247/testbench/candy_sram_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:1: Cannot find include file: candy_defines.v\n`include "candy_defines.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v.v\n             data/full_repos/permissive/157608247/testbench,data/full_repos/permissive/157608247/candy_defines.v.sv\n             candy_defines.v\n             candy_defines.v.v\n             candy_defines.v.sv\n             obj_dir/candy_defines.v\n             obj_dir/candy_defines.v.v\n             obj_dir/candy_defines.v.sv\n%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:9: Define or directive not defined: \'`SRAMAddrWidth\'\nreg [`SRAMAddrWidth] waddr;\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`SRAMAddrWidth] waddr;\n                   ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:10: Define or directive not defined: \'`SRAMDataWidth\'\nreg [`SRAMDataWidth] wdata;\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`SRAMDataWidth] wdata;\n                   ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:13: Define or directive not defined: \'`SRAMAddrWidth\'\nreg [`SRAMAddrWidth] raddr;\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:13: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`SRAMAddrWidth] raddr;\n                   ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:15: Define or directive not defined: \'`SRAMDataWidth\'\nwire [`SRAMDataWidth] rdata;\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`SRAMDataWidth] rdata;\n                    ^\n%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:36: Define or directive not defined: \'`RstEnable\'\n        rst <= `RstEnable;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rst <= `RstEnable;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #0 begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:39: Define or directive not defined: \'`RstDisable\'\n        rst <= `RstDisable;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:39: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rst <= `RstDisable;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #10 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #10 begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157608247/testbench/candy_sram_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: Exiting due to 13 error(s), 7 warning(s)\n'
module candy_sram_tb;

reg clk;
reg rst;

reg write_enable;
reg [`SRAMAddrWidth] waddr;
reg [`SRAMDataWidth] wdata;

reg read_enable;
reg [`SRAMAddrWidth] raddr;

wire [`SRAMDataWidth] rdata;
wire rdata_ready;


candy_sram sram(
    .clk(clk),
    .rst(rst),
    .write_enable(write_enable),
    .waddr(waddr),
    .wdata(wdata),
    .read_enable(read_enable),
    .raddr(raddr),
    .rdata(rdata),
    .rdata_ready(rdata_ready)
);


initial begin

    #0 begin
        clk <= 1'b0;
        rst <= `RstEnable;
    end
    #10 begin
        rst <= `RstDisable;
        read_enable <= 1'b1;
        write_enable <= 1'b0;
        raddr <= 17'b0;
    end
    #10 begin
        raddr <= {16'b0 + 1'b1};
    end
    #10 begin
        raddr <= {15'b0 + 2'b10};
    end
    #10 begin
        read_enable <= 1'b0;
        write_enable <= 1'b1;
        waddr <= 17'b0;
        wdata <= 24'h1234;  
    end
    #10 begin
        read_enable <= 1'b1;
        write_enable <= 1'b0;
        raddr <= 17'b0;
    end
end


always #5 clk <= ~clk;

endmodule
module candy_sram_tb;


reg clk;
reg rst;

reg write_enable;
reg [`SRAMAddrWidth] waddr;
reg [`SRAMDataWidth] wdata;

reg read_enable;
reg [`SRAMAddrWidth] raddr;

wire [`SRAMDataWidth] rdata;
wire rdata_ready;


candy_sram sram(
    .clk(clk),
    .rst(rst),
    .write_enable(write_enable),
    .waddr(waddr),
    .wdata(wdata),
    .read_enable(read_enable),
    .raddr(raddr),
    .rdata(rdata),
    .rdata_ready(rdata_ready)
);


initial begin

    #0 begin
        clk <= 1'b0;
        rst <= `RstEnable;
    end
    #10 begin
        rst <= `RstDisable;
        read_enable <= 1'b1;
        write_enable <= 1'b0;
        raddr <= 17'b0;
    end
    #10 begin
        raddr <= {16'b0 + 1'b1};
    end
    #10 begin
        raddr <= {15'b0 + 2'b10};
    end
    #10 begin
        read_enable <= 1'b0;
        write_enable <= 1'b1;
        waddr <= 17'b0;
        wdata <= 24'h1234;  
    end
    #10 begin
        read_enable <= 1'b1;
        write_enable <= 1'b0;
        raddr <= 17'b0;
    end
end


always #5 clk <= ~clk;

endmodule