data/full_repos/permissive/14636651/ALU.v
data/verilator_xmls/1404fbec-737f-424d-b5de-fa1772aeb88d.xml
module ALU(input add, input sub, input [15:0] a,b, output reg [15:0] out);
	always@(a or b or add or sub)
	begin
		if(add)
		begin
			out = a+b;
		end
		else if(sub)
		begin
			out = a-b;
		end
	end
endmodule
module ALU(input add, input sub, input [15:0] a,b, output reg [15:0] out);

	always@(a or b or add or sub)
	begin
		if(add)
		begin
			out = a+b;
		end
		else if(sub)
		begin
			out = a-b;
		end
	end
endmodule