data/full_repos/permissive/169155753/source/misc/delayline.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/169155753/source/misc/delayline.v:13: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                   : ... In instance delayline\n        out <= buffer[CYCLES-1];\n        ^~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module delayline(
    input clock,
    input [WIDTH-1:0] in,
    output [WIDTH-1:0] out
);

    parameter WIDTH = 8;
    parameter CYCLES = 4;

    reg [WIDTH-1:0] buffer [CYCLES-1:0];

    always @(posedge clock) begin
        out <= buffer[CYCLES-1];
        buffer[CYCLES-1:1] <= buffer[CYCLES-2:0];
        buffer[0] <= in;
    end

endmodule
module delayline(
    input clock,
    input [WIDTH-1:0] in,
    output [WIDTH-1:0] out
);


    parameter WIDTH = 8;
    parameter CYCLES = 4;

    reg [WIDTH-1:0] buffer [CYCLES-1:0];

    always @(posedge clock) begin
        out <= buffer[CYCLES-1];
        buffer[CYCLES-1:1] <= buffer[CYCLES-2:0];
        buffer[0] <= in;
    end

endmodule