data/full_repos/permissive/161526648/SingleCycle.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:300: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                      : ... In instance SingleCycle.alu\n    result = ALUsrc1 < ALUsrc2;  \n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:227: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                      : ... In instance SingleCycle.ImExtend\n assign out = $signed(in);\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module ALUcontrol(func,ALUop,ALUControl);
	input [5:0]func;
	input [1:0]ALUop;
	output reg [3:0]ALUControl;

	always @(func or ALUop) begin
		case (ALUop)
			2'b00: ALUControl = 4'b0010;
			2'b01: ALUControl = 4'b0110;
			2'b10: 
				case(func)
					6'b100000: ALUControl = 4'b0010;
					6'b100010: ALUControl = 4'b0110;
					6'b100100: ALUControl = 4'b0000;
					6'b100101: ALUControl = 4'b0001;
					6'b101010: ALUControl = 4'b0111;
					default: ALUControl = 4'b0000;
				endcase
			2'b11: ALUControl = 4'b0000;
			default: ALUControl = 4'b0000;
		endcase
	end
endmodule
module ALUcontrol(func,ALUop,ALUControl);

	input [5:0]func;
	input [1:0]ALUop;
	output reg [3:0]ALUControl;

	always @(func or ALUop) begin
		case (ALUop)
			2'b00: ALUControl = 4'b0010;
			2'b01: ALUControl = 4'b0110;
			2'b10: 
				case(func)
					6'b100000: ALUControl = 4'b0010;
					6'b100010: ALUControl = 4'b0110;
					6'b100100: ALUControl = 4'b0000;
					6'b100101: ALUControl = 4'b0001;
					6'b101010: ALUControl = 4'b0111;
					default: ALUControl = 4'b0000;
				endcase
			2'b11: ALUControl = 4'b0000;
			default: ALUControl = 4'b0000;
		endcase
	end
endmodule