data/full_repos/permissive/179884651/library/WF_BL_7seg_if.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/05f0b5b9-b9ee-4705-89a9-77ee7eeda91a.xml
module WF_BL_7seg_if (

        input clk,
        input scan_enable,



        input [3:0] digit0,
        input [3:0] digit1,
        input [3:0] digit2,
        input [3:0] digit3,
    input [1:0] colon,

        output reg CLK_OUT,
        output     LOAD,
        output     DOUT
);

   reg [4:0] digit;

   reg       clk7_en;
   reg [4:0] seg_index;
   reg [3:0] current_digit;
   reg [7:0] segments;
   reg [7:0] data_out;








     always @ (posedge clk)
       begin
         if (digit == 5'h0)
           digit <= 5'h01;

         if (scan_enable)
           digit <= {digit[3:0],digit[4]};
       end


     always @ (posedge clk)
       begin
         if (scan_enable)
           begin
             clk7_en     <= 1'b1;
             seg_index   <= 5'b0;
           end

         if (clk7_en)
           if (seg_index == 5'd31)
             clk7_en <= 1'b0;
           else
             seg_index <= seg_index + 5'h1;

       end



     always @ (posedge clk)
       if (clk7_en )
         begin
           if (seg_index[0])
             data_out <= {data_out[6:0],1'b0};
           if (seg_index == 5'd16)
             data_out <= {digit[4],3'b000,digit[3:0]};
           end
       else
         data_out<= (digit[3]) ? {6'h0,2'b01} : segments;


     assign LOAD = ~clk7_en;
     assign DOUT = data_out[7];

     always @ (posedge clk)
       if (clk7_en)
         CLK_OUT <= ~CLK_OUT;
       else
         CLK_OUT <= 1'b0;





   always @(*)
      case (digit[4:0])
        5'h10: current_digit = digit0;
        5'h1 : current_digit = digit1;
        5'h2 : current_digit = digit2;
        5'h4 : current_digit = digit3;
     endcase




















   always @(*)
      case (current_digit)
        4'h0 : segments = {1'b1,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
        4'h1 : segments = {1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b1};
        4'h2 : segments = {1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,1'b0,1'b0};
        4'h3 : segments = {1'b1,1'b0,1'b1,1'b1,1'b0,1'b0,1'b0,1'b0};
        4'h4 : segments = {1'b1,1'b0,1'b0,1'b1,1'b1,1'b0,1'b0,1'b1};
        4'h5 : segments = {1'b1,1'b0,1'b0,1'b1,1'b0,1'b0,1'b1,1'b0};
        4'h6 : segments = {1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1};
        4'h7 : segments = {1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0};
        4'h8 : segments = {1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
        4'h9 : segments = {1'b1,1'b0,1'b0,1'b1,1'b1,1'b0,1'b0,1'b0};
        4'ha : segments = {1'b1,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0};
        4'hb : segments = {1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1};
        4'hc : segments = {1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,1'b1,1'b1};
        4'hd : segments = {1'b1,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1};
        4'he : segments = {1'b1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b0};
        4'hf : segments = {1'b1,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0};
     endcase

endmodule
module WF_BL_7seg_if (

        input clk,
        input scan_enable,



        input [3:0] digit0,
        input [3:0] digit1,
        input [3:0] digit2,
        input [3:0] digit3,
    input [1:0] colon,

        output reg CLK_OUT,
        output     LOAD,
        output     DOUT
);


   reg [4:0] digit;

   reg       clk7_en;
   reg [4:0] seg_index;
   reg [3:0] current_digit;
   reg [7:0] segments;
   reg [7:0] data_out;








     always @ (posedge clk)
       begin
         if (digit == 5'h0)
           digit <= 5'h01;

         if (scan_enable)
           digit <= {digit[3:0],digit[4]};
       end


     always @ (posedge clk)
       begin
         if (scan_enable)
           begin
             clk7_en     <= 1'b1;
             seg_index   <= 5'b0;
           end

         if (clk7_en)
           if (seg_index == 5'd31)
             clk7_en <= 1'b0;
           else
             seg_index <= seg_index + 5'h1;

       end



     always @ (posedge clk)
       if (clk7_en )
         begin
           if (seg_index[0])
             data_out <= {data_out[6:0],1'b0};
           if (seg_index == 5'd16)
             data_out <= {digit[4],3'b000,digit[3:0]};
           end
       else
         data_out<= (digit[3]) ? {6'h0,2'b01} : segments;


     assign LOAD = ~clk7_en;
     assign DOUT = data_out[7];

     always @ (posedge clk)
       if (clk7_en)
         CLK_OUT <= ~CLK_OUT;
       else
         CLK_OUT <= 1'b0;





   always @(*)
      case (digit[4:0])
        5'h10: current_digit = digit0;
        5'h1 : current_digit = digit1;
        5'h2 : current_digit = digit2;
        5'h4 : current_digit = digit3;
     endcase




















   always @(*)
      case (current_digit)
        4'h0 : segments = {1'b1,1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
        4'h1 : segments = {1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b1};
        4'h2 : segments = {1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,1'b0,1'b0};
        4'h3 : segments = {1'b1,1'b0,1'b1,1'b1,1'b0,1'b0,1'b0,1'b0};
        4'h4 : segments = {1'b1,1'b0,1'b0,1'b1,1'b1,1'b0,1'b0,1'b1};
        4'h5 : segments = {1'b1,1'b0,1'b0,1'b1,1'b0,1'b0,1'b1,1'b0};
        4'h6 : segments = {1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1};
        4'h7 : segments = {1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0};
        4'h8 : segments = {1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
        4'h9 : segments = {1'b1,1'b0,1'b0,1'b1,1'b1,1'b0,1'b0,1'b0};
        4'ha : segments = {1'b1,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0};
        4'hb : segments = {1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1};
        4'hc : segments = {1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,1'b1,1'b1};
        4'hd : segments = {1'b1,1'b0,1'b1,1'b0,1'b0,1'b0,1'b0,1'b1};
        4'he : segments = {1'b1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b0};
        4'hf : segments = {1'b1,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b0};
     endcase

endmodule