data/full_repos/permissive/143278/ivltests/pr973.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr973.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (foo != 1.5) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   real foo;

   initial begin
      foo = 1.0;
      if (foo != 1.0) begin
	 $display("FAILED: Simple assign works not. foo=%f", foo);
	 $finish;
      end

      foo <= 1.5;
      if (foo != 1.0) begin
	 $display("FAILED: nb assign works too fast. foo=%f", foo);
	 $finish;
      end

      #1 if (foo != 1.5) begin
	 $display("FAILED: nb assign works not. foo=%f", foo);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   real foo;

   initial begin
      foo = 1.0;
      if (foo != 1.0) begin
	 $display("FAILED: Simple assign works not. foo=%f", foo);
	 $finish;
      end

      foo <= 1.5;
      if (foo != 1.0) begin
	 $display("FAILED: nb assign works too fast. foo=%f", foo);
	 $finish;
      end

      #1 if (foo != 1.5) begin
	 $display("FAILED: nb assign works not. foo=%f", foo);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule