data/full_repos/permissive/210844779/lab4/4.1.2/state_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab4/4.1.2/state_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab4/4.1.2/state_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab4/4.1.2/state_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab4/4.1.2/state_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: data/full_repos/permissive/210844779/lab4/4.1.2/state_tb.v:6: Cannot find file containing module: \'state_over\'\n  state_over u0(ip,clk,rst,op);\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab4/4.1.2,data/full_repos/permissive/210844779/state_over\n             data/full_repos/permissive/210844779/lab4/4.1.2,data/full_repos/permissive/210844779/state_over.v\n             data/full_repos/permissive/210844779/lab4/4.1.2,data/full_repos/permissive/210844779/state_over.sv\n             state_over\n             state_over.v\n             state_over.sv\n             obj_dir/state_over\n             obj_dir/state_over.v\n             obj_dir/state_over.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab4/4.1.2/state_tb.v:25: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                             : ... In instance state_tb\n    ip=$random;\n      ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module state_tb();
  
  reg ip,clk,rst;
  wire op;
  
  state_over u0(ip,clk,rst,op);
  
  always
  begin
    clk=1;
    #5
    clk=0;
    #5;
  end
  
  initial
  begin
    rst=1;
    #10
    rst=0;
  end
  
  always
  begin  
    ip=$random;
    #10;
  end
  
endmodule
module state_tb();

  
  reg ip,clk,rst;
  wire op;
  
  state_over u0(ip,clk,rst,op);
  
  always
  begin
    clk=1;
    #5
    clk=0;
    #5;
  end
  
  initial
  begin
    rst=1;
    #10
    rst=0;
  end
  
  always
  begin  
    ip=$random;
    #10;
  end
  
endmodule