data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:254: Unsupported: Ignoring delay on this delayed statement.\n        forever #50 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:45: Cannot find file containing module: \'instMemory\'\n    instMemory #(32, 4) myIMEM(.inst(instr32), .pcVal(PC16[3:0]), .sysCLK(mainCLOCK));    \n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191834901/VerilogHDL,data/full_repos/permissive/191834901/instMemory\n             data/full_repos/permissive/191834901/VerilogHDL,data/full_repos/permissive/191834901/instMemory.v\n             data/full_repos/permissive/191834901/VerilogHDL,data/full_repos/permissive/191834901/instMemory.sv\n             instMemory\n             instMemory.v\n             instMemory.sv\n             obj_dir/instMemory\n             obj_dir/instMemory.v\n             obj_dir/instMemory.sv\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:50: Cannot find file containing module: \'controlPathDriver\'\n    controlPathDriver #(16, 16) myCP(\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:72: Cannot find file containing module: \'registerFile\'\n    registerFile #(32, 5) riscRegisters(\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:86: Cannot find file containing module: \'mainALU\'\n    mainALU #(32) testALU(\n    ^~~~~~~\n%Error: data/full_repos/permissive/191834901/VerilogHDL/mainProcessor.v:99: Cannot find file containing module: \'dataMemory\'\n    dataMemory #(32, 16) myDMEM(\n    ^~~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module comparatorNx #(parameter cW = 32) (
    output reg BrLt, BrEq,
    input  [(cW-1):0] A, B
);
    always@(*) begin
        BrLt = 0;
        BrEq = 0;
        if(A < B)
            BrLt = 1;
        if (A == B)
            BrEq = 1;
    end
endmodule
module comparatorNx #(parameter cW = 32) (
    output reg BrLt, BrEq,
    input  [(cW-1):0] A, B
);

    always@(*) begin
        BrLt = 0;
        BrEq = 0;
        if(A < B)
            BrLt = 1;
        if (A == B)
            BrEq = 1;
    end
endmodule