data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf/switchChain.v
1: b"%Error: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf/switchChain.v:41: Cannot find file containing module: 'sw_dolut'\n     sw_dolut SW(\n     ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf,data/full_repos/permissive/128781882/sw_dolut\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf,data/full_repos/permissive/128781882/sw_dolut.v\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf,data/full_repos/permissive/128781882/sw_dolut.sv\n             sw_dolut\n             sw_dolut.v\n             sw_dolut.sv\n             obj_dir/sw_dolut\n             obj_dir/sw_dolut.v\n             obj_dir/sw_dolut.sv\n%Error: Exiting due to 1 error(s)\n"
module switchChain #( parameter nStage = 16)(
      inT,
		inB,
		c,
		outT,
		outB
	);
	
	input inT,inB;
	input [nStage-1:0]  c;
	output outT;
	output outB;

	wire [nStage:0] netT;
	wire [nStage:0] netB;
	

	assign outT = netT[nStage];
	assign outB = netB[nStage];
	

	assign netT[0] = inT;
	assign netB[0] = inB;
	
	

	genvar i;
	generate 
		for(i = 0; i < nStage; i = i + 1) begin:STAGE 
		

					sw_dolut SW(
						.iT(netT[i]),
						.iB(netB[i]),
						.c(c[i]),
						.vcc(1'b1),
						.oT(netT[i+1]),
						.oB(netB[i+1])
					);
				
		end
	endgenerate
		
endmodule
module switchChain #( parameter nStage = 16)(
      inT,
		inB,
		c,
		outT,
		outB
	);

	
	input inT,inB;
	input [nStage-1:0]  c;
	output outT;
	output outB;

	wire [nStage:0] netT;
	wire [nStage:0] netB;
	

	assign outT = netT[nStage];
	assign outB = netB[nStage];
	

	assign netT[0] = inT;
	assign netB[0] = inB;
	
	

	genvar i;
	generate 
		for(i = 0; i < nStage; i = i + 1) begin:STAGE 
		

					sw_dolut SW(
						.iT(netT[i]),
						.iB(netB[i]),
						.c(c[i]),
						.vcc(1'b1),
						.oT(netT[i+1]),
						.oB(netB[i+1])
					);
				
		end
	endgenerate
		
endmodule