data/full_repos/permissive/131712122/bench/verilog/testbench_top.v
 line:199: before: "("
1: b'%Error: data/full_repos/permissive/131712122/bench/verilog/testbench_top.v:376: Cannot find include file: tests.v\n`include "tests.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131712122/bench/verilog,data/full_repos/permissive/131712122/tests.v\n             data/full_repos/permissive/131712122/bench/verilog,data/full_repos/permissive/131712122/tests.v.v\n             data/full_repos/permissive/131712122/bench/verilog,data/full_repos/permissive/131712122/tests.v.sv\n             tests.v\n             tests.v.v\n             tests.v.sv\n             obj_dir/tests.v\n             obj_dir/tests.v.v\n             obj_dir/tests.v.sv\n%Error: data/full_repos/permissive/131712122/bench/verilog/testbench_top.v:181: Unsupported or unknown PLI call: $timeformat\n $timeformat (-9, 1, " ns", 12);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/131712122/bench/verilog/testbench_top.v:199: syntax error, unexpected \'@\'\n    repeat(20) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/131712122/bench/verilog/testbench_top.v:201: syntax error, unexpected \'@\'\n    repeat(20) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/131712122/bench/verilog/testbench_top.v:210: syntax error, unexpected \'@\'\n    repeat(10) @(posedge clk);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/testbench_top.v:291: Unsupported: Ignoring delay on this delayed statement.\nalways #2.4 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/131712122/bench/verilog/testbench_top.v:292: Unsupported: Ignoring delay on this delayed statement.\nalways #(PCLK_C/2) pclk = ~pclk;\n       ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module testbench_top;

reg		clk;
reg		rst;

parameter	LINE_FIFO_AWIDTH = 7;

wire		interrupt;
wire	[31:0]	wb_addr_o;
wire	[31:0]	wb_data_i;
wire	[31:0]	wb_data_o;
wire	[3:0]	wb_sel_o;
wire		wb_we_o;
wire		wb_stb_o;
wire		wb_cyc_o;
wire	[2:0]	wb_cti_o;
wire	[1:0]	wb_bte_o;
wire		wb_ack_i;
wire		wb_err_i;
wire	[31:0]	wb_addr_i;
wire	[31:0]	wbm_data_i;
wire	[3:0]	wb_sel_i;
wire		wb_we_i;
wire		wb_stb_i;
wire		wb_cyc_i;
wire		wb_ack_o;
wire		wb_rty_o;
wire		wb_err_o;
reg 		pclk;
wire    	hsync;
wire		vsync;
wire		csync;
wire		blanc;
wire	[7:0]	red;
wire	[7:0]	green;
wire	[7:0]	blue;
wire		dvi_pclk_p_o;
wire		dvi_pclk_m_o;
wire		dvi_hsync_o;
wire		dvi_vsync_o;
wire		dvi_de_o;
wire	[11:0]	dvi_d_o;


wire vga_stb_i;
wire clut_stb_i;

reg		scen;


integer		wd_cnt;
integer		error_cnt;


reg	[31:0]	data;
reg	[31:0]	pattern;
reg		interrupt_warn;

integer		n;
integer		mode;

reg	[7:0]	thsync, thgdel;
reg	[15:0]	thgate, thlen;
reg	[7:0]	tvsync, tvgdel;
reg	[15:0]	tvgate, tvlen;
reg		hpol;
reg		vpol;
reg		cpol;
reg		bpol;
integer		p, l;
reg	[31:0]	pn;
reg	[31:0]	pra, paa, tmp;
reg	[23:0]	pd;
reg	[1:0]	cd;
reg		pc;
reg	[31:0]	vbase;
reg	[31:0]	cbase;
reg	[31:0]	vbara;
reg	[31:0]	vbarb;
reg	[7:0]	bank;





`define	CTRL   32'h0000_0000
`define	STAT   32'h0000_0004
`define	HTIM   32'h0000_0008
`define	VTIM   32'h0000_000c
`define	HVLEN  32'h0000_0010
`define	VBARA  32'h0000_0014
`define	VBARB  32'h0000_0018

`define USE_VC 1

parameter PCLK_C = 30;







initial
   begin
	$timeformat (-9, 1, " ns", 12);
	$display("\n\n");
	$display("------------------------------------------------------");
	$display("- VGA/LCD Controller Simulation started ...          -");
	$display("------------------------------------------------------");
	$display("\n");
`ifdef WAVES
  	$shm_open("waves");
	$shm_probe("AS",test,"AS");
	$display("INFO: Signal dump enabled ...\n\n");
`endif
	scen = 0;
	error_cnt = 0;
   	clk = 0;
	pclk = 0;
   	rst = 0;
	interrupt_warn=1;

   	repeat(20) @(posedge clk);
   	rst = 1;
   	repeat(20) @(posedge clk);


	reg_test;
	tim_test;
	pd1_test;
	pd2_test;
	ur_test;

   	repeat(10)	@(posedge clk);
   	$finish;
   end





sync_check #(PCLK_C) ucheck(
  .pclk   ( pclk   ),
  .rst    ( rst    ),
  .enable ( scen   ),
  .hsync  ( hsync  ),
  .vsync  ( vsync  ),
  .csync  ( csync  ),
  .blanc  ( blanc  ),
  .hpol   ( hpol   ),
  .vpol   ( vpol   ),
  .cpol   ( cpol   ),
  .bpol   ( bpol   ),
  .thsync ( thsync ),
  .thgdel ( thgdel ),
  .thgate ( thgate ),
  .thlen  ( thlen  ),
  .tvsync ( tvsync ),
  .tvgdel ( tvgdel ),
  .tvgate ( tvgate ),
  .tvlen  ( tvlen  ) );











wb_b3_check u_wb_check (
  .clk_i ( clk      ),
  .cyc_i ( wb_cyc_o ),
  .stb_i ( wb_stb_o ),
  .cti_i ( wb_cti_o ),
  .bte_i ( wb_bte_o ),
  .we_i  ( wb_we_o  ),
  .ack_i ( wb_ack_i ),
  .err_i ( wb_err_i ),
  .rty_i ( 1'b0     ) );







always @(posedge clk)
	if(wb_cyc_i | wb_cyc_o | wb_ack_i | wb_ack_o | hsync)
	  wd_cnt <= 0;
	else
	  wd_cnt <= wd_cnt + 1;


always @(wd_cnt)
	if(wd_cnt>9000)
	   begin
		$display("\n\n*************************************\n");
		$display("ERROR: Watch Dog Counter Expired\n");
		$display("*************************************\n\n\n");
		$finish;
	   end


always @(posedge interrupt)
  if(interrupt_warn)
   begin
	$display("\n\n*************************************\n");
	$display("WARNING: Recieved Interrupt (%0t)", $time);
	$display("*************************************\n\n\n");
   end

always #2.4 clk = ~clk;
always #(PCLK_C/2) pclk = ~pclk;







  vga_enh_top #(
    1'b0,
    LINE_FIFO_AWIDTH
  )
  dut (
    .wb_clk_i     ( clk             ),
    .wb_rst_i     ( 1'b0            ),
    .rst_i        ( rst             ),
    .wb_inta_o    ( interrupt       ),


    .wbs_adr_i    ( wb_addr_i[11:0] ),
    .wbs_dat_i    ( wb_data_i       ),
    .wbs_dat_o    ( wb_data_o       ),
    .wbs_sel_i    ( wb_sel_i        ),
    .wbs_we_i     ( wb_we_i         ),
    .wbs_stb_i    ( wb_stb_i        ),
    .wbs_cyc_i    ( wb_cyc_i        ),
    .wbs_ack_o    ( wb_ack_o        ),
    .wbs_rty_o    ( wb_rty_o        ),
    .wbs_err_o    ( wb_err_o        ),


    .wbm_adr_o    ( wb_addr_o[31:0] ),
    .wbm_dat_i    ( wbm_data_i      ),
    .wbm_sel_o    ( wb_sel_o        ),
    .wbm_we_o     ( wb_we_o         ),
    .wbm_stb_o    ( wb_stb_o        ),
    .wbm_cyc_o    ( wb_cyc_o        ),
    .wbm_cti_o    ( wb_cti_o        ),
    .wbm_bte_o    ( wb_bte_o        ),
    .wbm_ack_i    ( wb_ack_i        ),
    .wbm_err_i    ( wb_err_i        ),


    .clk_p_i      ( pclk            ),
    .hsync_pad_o  ( hsync           ),
    .vsync_pad_o  ( vsync           ),
    .csync_pad_o  ( csync           ),
    .blank_pad_o  ( blanc           ),
    .r_pad_o      ( red             ),
    .g_pad_o      ( green           ),
    .b_pad_o      ( blue            )
  );



wb_mast	m0(	.clk(		clk		),
		.rst(		rst		),
		.adr(		wb_addr_i	),
		.din(		wb_data_o	),
		.dout(		wb_data_i	),
		.cyc(		wb_cyc_i	),
		.stb(		wb_stb_i	),
		.sel(		wb_sel_i	),
		.we(		wb_we_i		),
		.ack(		wb_ack_o	),
		.err(		wb_err_o	),
		.rty(		1'b0		)
		);

wb_slv #(24) s0(.clk(		clk		),
		.rst(		rst		),
		.adr(		{1'b0, wb_addr_o[30:0]}	),
		.din(		32'h0		),
		.dout(		wbm_data_i	),
		.cyc(		wb_cyc_o	),
		.stb(		wb_stb_o	),
		.sel(		wb_sel_o	),
		.we(		wb_we_o		),
		.ack(		wb_ack_i	),
		.err(		wb_err_i	),
		.rty(				)
		);

`include "tests.v"

endmodule
module testbench_top;


reg		clk;
reg		rst;

parameter	LINE_FIFO_AWIDTH = 7;

wire		interrupt;
wire	[31:0]	wb_addr_o;
wire	[31:0]	wb_data_i;
wire	[31:0]	wb_data_o;
wire	[3:0]	wb_sel_o;
wire		wb_we_o;
wire		wb_stb_o;
wire		wb_cyc_o;
wire	[2:0]	wb_cti_o;
wire	[1:0]	wb_bte_o;
wire		wb_ack_i;
wire		wb_err_i;
wire	[31:0]	wb_addr_i;
wire	[31:0]	wbm_data_i;
wire	[3:0]	wb_sel_i;
wire		wb_we_i;
wire		wb_stb_i;
wire		wb_cyc_i;
wire		wb_ack_o;
wire		wb_rty_o;
wire		wb_err_o;
reg 		pclk;
wire    	hsync;
wire		vsync;
wire		csync;
wire		blanc;
wire	[7:0]	red;
wire	[7:0]	green;
wire	[7:0]	blue;
wire		dvi_pclk_p_o;
wire		dvi_pclk_m_o;
wire		dvi_hsync_o;
wire		dvi_vsync_o;
wire		dvi_de_o;
wire	[11:0]	dvi_d_o;


wire vga_stb_i;
wire clut_stb_i;

reg		scen;


integer		wd_cnt;
integer		error_cnt;


reg	[31:0]	data;
reg	[31:0]	pattern;
reg		interrupt_warn;

integer		n;
integer		mode;

reg	[7:0]	thsync, thgdel;
reg	[15:0]	thgate, thlen;
reg	[7:0]	tvsync, tvgdel;
reg	[15:0]	tvgate, tvlen;
reg		hpol;
reg		vpol;
reg		cpol;
reg		bpol;
integer		p, l;
reg	[31:0]	pn;
reg	[31:0]	pra, paa, tmp;
reg	[23:0]	pd;
reg	[1:0]	cd;
reg		pc;
reg	[31:0]	vbase;
reg	[31:0]	cbase;
reg	[31:0]	vbara;
reg	[31:0]	vbarb;
reg	[7:0]	bank;





`define	CTRL   32'h0000_0000
`define	STAT   32'h0000_0004
`define	HTIM   32'h0000_0008
`define	VTIM   32'h0000_000c
`define	HVLEN  32'h0000_0010
`define	VBARA  32'h0000_0014
`define	VBARB  32'h0000_0018

`define USE_VC 1

parameter PCLK_C = 30;







initial
   begin
	$timeformat (-9, 1, " ns", 12);
	$display("\n\n");
	$display("------------------------------------------------------");
	$display("- VGA/LCD Controller Simulation started ...          -");
	$display("------------------------------------------------------");
	$display("\n");
`ifdef WAVES
  	$shm_open("waves");
	$shm_probe("AS",test,"AS");
	$display("INFO: Signal dump enabled ...\n\n");
`endif
	scen = 0;
	error_cnt = 0;
   	clk = 0;
	pclk = 0;
   	rst = 0;
	interrupt_warn=1;

   	repeat(20) @(posedge clk);
   	rst = 1;
   	repeat(20) @(posedge clk);


	reg_test;
	tim_test;
	pd1_test;
	pd2_test;
	ur_test;

   	repeat(10)	@(posedge clk);
   	$finish;
   end





sync_check #(PCLK_C) ucheck(
  .pclk   ( pclk   ),
  .rst    ( rst    ),
  .enable ( scen   ),
  .hsync  ( hsync  ),
  .vsync  ( vsync  ),
  .csync  ( csync  ),
  .blanc  ( blanc  ),
  .hpol   ( hpol   ),
  .vpol   ( vpol   ),
  .cpol   ( cpol   ),
  .bpol   ( bpol   ),
  .thsync ( thsync ),
  .thgdel ( thgdel ),
  .thgate ( thgate ),
  .thlen  ( thlen  ),
  .tvsync ( tvsync ),
  .tvgdel ( tvgdel ),
  .tvgate ( tvgate ),
  .tvlen  ( tvlen  ) );











wb_b3_check u_wb_check (
  .clk_i ( clk      ),
  .cyc_i ( wb_cyc_o ),
  .stb_i ( wb_stb_o ),
  .cti_i ( wb_cti_o ),
  .bte_i ( wb_bte_o ),
  .we_i  ( wb_we_o  ),
  .ack_i ( wb_ack_i ),
  .err_i ( wb_err_i ),
  .rty_i ( 1'b0     ) );







always @(posedge clk)
	if(wb_cyc_i | wb_cyc_o | wb_ack_i | wb_ack_o | hsync)
	  wd_cnt <= 0;
	else
	  wd_cnt <= wd_cnt + 1;


always @(wd_cnt)
	if(wd_cnt>9000)
	   begin
		$display("\n\n*************************************\n");
		$display("ERROR: Watch Dog Counter Expired\n");
		$display("*************************************\n\n\n");
		$finish;
	   end


always @(posedge interrupt)
  if(interrupt_warn)
   begin
	$display("\n\n*************************************\n");
	$display("WARNING: Recieved Interrupt (%0t)", $time);
	$display("*************************************\n\n\n");
   end

always #2.4 clk = ~clk;
always #(PCLK_C/2) pclk = ~pclk;







  vga_enh_top #(
    1'b0,
    LINE_FIFO_AWIDTH
  )
  dut (
    .wb_clk_i     ( clk             ),
    .wb_rst_i     ( 1'b0            ),
    .rst_i        ( rst             ),
    .wb_inta_o    ( interrupt       ),


    .wbs_adr_i    ( wb_addr_i[11:0] ),
    .wbs_dat_i    ( wb_data_i       ),
    .wbs_dat_o    ( wb_data_o       ),
    .wbs_sel_i    ( wb_sel_i        ),
    .wbs_we_i     ( wb_we_i         ),
    .wbs_stb_i    ( wb_stb_i        ),
    .wbs_cyc_i    ( wb_cyc_i        ),
    .wbs_ack_o    ( wb_ack_o        ),
    .wbs_rty_o    ( wb_rty_o        ),
    .wbs_err_o    ( wb_err_o        ),


    .wbm_adr_o    ( wb_addr_o[31:0] ),
    .wbm_dat_i    ( wbm_data_i      ),
    .wbm_sel_o    ( wb_sel_o        ),
    .wbm_we_o     ( wb_we_o         ),
    .wbm_stb_o    ( wb_stb_o        ),
    .wbm_cyc_o    ( wb_cyc_o        ),
    .wbm_cti_o    ( wb_cti_o        ),
    .wbm_bte_o    ( wb_bte_o        ),
    .wbm_ack_i    ( wb_ack_i        ),
    .wbm_err_i    ( wb_err_i        ),


    .clk_p_i      ( pclk            ),
    .hsync_pad_o  ( hsync           ),
    .vsync_pad_o  ( vsync           ),
    .csync_pad_o  ( csync           ),
    .blank_pad_o  ( blanc           ),
    .r_pad_o      ( red             ),
    .g_pad_o      ( green           ),
    .b_pad_o      ( blue            )
  );



wb_mast	m0(	.clk(		clk		),
		.rst(		rst		),
		.adr(		wb_addr_i	),
		.din(		wb_data_o	),
		.dout(		wb_data_i	),
		.cyc(		wb_cyc_i	),
		.stb(		wb_stb_i	),
		.sel(		wb_sel_i	),
		.we(		wb_we_i		),
		.ack(		wb_ack_o	),
		.err(		wb_err_o	),
		.rty(		1'b0		)
		);

wb_slv #(24) s0(.clk(		clk		),
		.rst(		rst		),
		.adr(		{1'b0, wb_addr_o[30:0]}	),
		.din(		32'h0		),
		.dout(		wbm_data_i	),
		.cyc(		wb_cyc_o	),
		.stb(		wb_stb_o	),
		.sel(		wb_sel_o	),
		.we(		wb_we_o		),
		.ack(		wb_ack_i	),
		.err(		wb_err_i	),
		.rty(				)
		);

`include "tests.v"

endmodule