data/full_repos/permissive/157979234/Semester III/Digital Design and Computer Organization/Session 05/my_mods.v
1: b'%Error: Cannot find file containing module: III/Digital\n        ... Looked in:\n             data/full_repos/permissive/157979234/Semester/III/Digital\n             data/full_repos/permissive/157979234/Semester/III/Digital.v\n             data/full_repos/permissive/157979234/Semester/III/Digital.sv\n             III/Digital\n             III/Digital.v\n             III/Digital.sv\n             obj_dir/III/Digital\n             obj_dir/III/Digital.v\n             obj_dir/III/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Organization/Session\n%Error: Cannot find file containing module: 05,data/full_repos/permissive/157979234\n%Error: Cannot find file containing module: data/full_repos/permissive/157979234/Semester\n%Error: Cannot find file containing module: 05/my_mods.v\n%Error: Exiting due to 8 error(s)\n'
module reg16_8
(
  input wire
  clk,
  reset,
  input wire [7:0]
  load,
  input wire [15:0]
  d,
  output wire [15:0]
  q0,
  q1,
  q2,
  q3,
  q4,
  q5,
  q6,
  q7
);

reg16 rg0(clk, reset, load[0], d, q0);
reg16 rg1(clk, reset, load[1], d, q1);
reg16 rg2(clk, reset, load[2], d, q2);
reg16 rg3(clk, reset, load[3], d, q3);
reg16 rg4(clk, reset, load[4], d, q4);
reg16 rg5(clk, reset, load[5], d, q5);
reg16 rg6(clk, reset, load[6], d, q6);
reg16 rg7(clk, reset, load[7], d, q7);

endmodule
module reg16_8
(
  input wire
  clk,
  reset,
  input wire [7:0]
  load,
  input wire [15:0]
  d,
  output wire [15:0]
  q0,
  q1,
  q2,
  q3,
  q4,
  q5,
  q6,
  q7
);


reg16 rg0(clk, reset, load[0], d, q0);
reg16 rg1(clk, reset, load[1], d, q1);
reg16 rg2(clk, reset, load[2], d, q2);
reg16 rg3(clk, reset, load[3], d, q3);
reg16 rg4(clk, reset, load[4], d, q4);
reg16 rg5(clk, reset, load[5], d, q5);
reg16 rg6(clk, reset, load[6], d, q6);
reg16 rg7(clk, reset, load[7], d, q7);

endmodule