data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v
 line:15: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 CLOCK_50 = ~CLOCK_50;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:15: Define or directive not defined: \'`RstEnable\'\n        rst = `RstEnable;\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:15: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        rst = `RstEnable;\n                        ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:16: Define or directive not defined: \'`RstDisable\'\n        #195 rst = `RstDisable;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:16: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #195 rst = `RstDisable;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #195 rst = `RstDisable;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #100000 $stop;\n        ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_riscv_min_sopc_tb ();

    reg CLOCK_50;
    reg rst;


    initial begin
        CLOCK_50 = 1'b0;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    initial begin
        rst = `RstEnable;
        #195 rst = `RstDisable;
        #100000 $stop;
    end

    cpu_riscv_min_sopc cpu_riscv_min_sopc0(
            .clk(CLOCK_50),
            .rst(rst)
        );

endmodule
module cpu_riscv_min_sopc_tb ();


    reg CLOCK_50;
    reg rst;


    initial begin
        CLOCK_50 = 1'b0;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    initial begin
        rst = `RstEnable;
        #195 rst = `RstDisable;
        #100000 $stop;
    end

    cpu_riscv_min_sopc cpu_riscv_min_sopc0(
            .clk(CLOCK_50),
            .rst(rst)
        );

endmodule