data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/DLatch/d_latch_behavior.v
data/verilator_xmls/92a58cc8-1e56-48d7-94be-995a9968cd35.xml
module D_latch_behavior (G, D, Q, X);
input G, D;
output Q, X;

reg Q, X;

always @(D or G)
	begin
		Q <= D;
		X <= -D;
	end
endmodule
module D_latch_behavior (G, D, Q, X);

input G, D;
output Q, X;

reg Q, X;

always @(D or G)
	begin
		Q <= D;
		X <= -D;
	end
endmodule