data/full_repos/permissive/111393021/bs_adder.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/111393021/bs_adder.v:33: Signal definition not found, creating implicitly: \'cout_int\'\n   cin_int <= cout_int;\n              ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111393021/bs_adder.v:23: Cannot find file containing module: \'fa\'\n fa I0(.x(x), .y(y), .cin(cin_int), .cout(cout_int), .sum(sum_int));\n ^~\n        ... Looked in:\n             data/full_repos/permissive/111393021,data/full_repos/permissive/111393021/fa\n             data/full_repos/permissive/111393021,data/full_repos/permissive/111393021/fa.v\n             data/full_repos/permissive/111393021,data/full_repos/permissive/111393021/fa.sv\n             fa\n             fa.v\n             fa.sv\n             obj_dir/fa\n             obj_dir/fa.v\n             obj_dir/fa.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module bs_adder(x, y, clk, z, rst);
	input x, y, clk, rst;
	output reg z;
	reg cin_int;	
	wire sum_int;
	
	fa I0(.x(x), .y(y), .cin(cin_int), .cout(cout_int), .sum(sum_int));
	always @ (posedge clk)	
	begin
		if(rst)
		begin
			cin_int <= 1'b0;
			z <= 1'b0;
		end
		else
		begin
			cin_int <= cout_int;
			z <= sum_int;
		end
	end
endmodule
module bs_adder(x, y, clk, z, rst);

	input x, y, clk, rst;
	output reg z;
	reg cin_int;	
	wire sum_int;
	
	fa I0(.x(x), .y(y), .cin(cin_int), .cout(cout_int), .sum(sum_int));
	always @ (posedge clk)	
	begin
		if(rst)
		begin
			cin_int <= 1'b0;
			z <= 1'b0;
		end
		else
		begin
			cin_int <= cout_int;
			z <= sum_int;
		end
	end
endmodule