data/full_repos/permissive/175780824/6_branch_prediction/cpu_rtl/DataExt.v
'utf-8' codec can't decode byte 0xa3 in position 483: invalid start byte
1: b'%Error: data/full_repos/permissive/175780824/6_branch_prediction/cpu_rtl/DataExt.v:13: Cannot find include file: Parameters.v\n`include "Parameters.v"    \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175780824/6_branch_prediction/cpu_rtl,data/full_repos/permissive/175780824/Parameters.v\n             data/full_repos/permissive/175780824/6_branch_prediction/cpu_rtl,data/full_repos/permissive/175780824/Parameters.v.v\n             data/full_repos/permissive/175780824/6_branch_prediction/cpu_rtl,data/full_repos/permissive/175780824/Parameters.v.sv\n             Parameters.v\n             Parameters.v.v\n             Parameters.v.sv\n             obj_dir/Parameters.v\n             obj_dir/Parameters.v.v\n             obj_dir/Parameters.v.sv\n%Error: data/full_repos/permissive/175780824/6_branch_prediction/cpu_rtl/DataExt.v:27: Define or directive not defined: \'`LB\'\n            `LB: OUT<={{24{LB_IN[7]}},LB_IN[7:0]};\n            ^~~\n%Error: data/full_repos/permissive/175780824/6_branch_prediction/cpu_rtl/DataExt.v:27: syntax error, unexpected \':\', expecting endcase\n            `LB: OUT<={{24{LB_IN[7]}},LB_IN[7:0]};\n               ^\n%Error: data/full_repos/permissive/175780824/6_branch_prediction/cpu_rtl/DataExt.v:28: Define or directive not defined: \'`LH\'\n            `LH:    OUT<={{16{LH_IN[15]}},LH_IN[15:0]};\n            ^~~\n%Error: data/full_repos/permissive/175780824/6_branch_prediction/cpu_rtl/DataExt.v:29: Define or directive not defined: \'`LW\'\n            `LW:    OUT<=IN;\n            ^~~\n%Error: data/full_repos/permissive/175780824/6_branch_prediction/cpu_rtl/DataExt.v:30: Define or directive not defined: \'`LBU\'\n            `LBU:   OUT<={24\'b0,LB_IN[7:0]};\n            ^~~~\n%Error: data/full_repos/permissive/175780824/6_branch_prediction/cpu_rtl/DataExt.v:31: Define or directive not defined: \'`LHU\'\n            `LHU:   OUT<={16\'b0,LH_IN[15:0]};\n            ^~~~\n%Error: Cannot continue\n'
module DataExt(
    input wire [31:0] IN,
    input wire [1:0] LoadedBytesSelect,
    input wire [2:0] RegWriteW,
    output reg [31:0] OUT
    );
    wire [31:0] LB_IN;
    wire [31:0] LH_IN;
    assign LB_IN = (IN >> (LoadedBytesSelect * 32'h08)) & 32'h000000ff;
    assign LH_IN = (IN >> (LoadedBytesSelect * 32'h08)) & 32'h0000ffff;
    always @(*)
    begin
        case(RegWriteW)
            `LB:	OUT<={{24{LB_IN[7]}},LB_IN[7:0]};
            `LH:    OUT<={{16{LH_IN[15]}},LH_IN[15:0]};
            `LW:    OUT<=IN;
            `LBU:   OUT<={24'b0,LB_IN[7:0]};
            `LHU:   OUT<={16'b0,LH_IN[15:0]};
            default:OUT = 32'hxxxxxxxx;
        endcase
    end
    
endmodule
module DataExt(
    input wire [31:0] IN,
    input wire [1:0] LoadedBytesSelect,
    input wire [2:0] RegWriteW,
    output reg [31:0] OUT
    );

    wire [31:0] LB_IN;
    wire [31:0] LH_IN;
    assign LB_IN = (IN >> (LoadedBytesSelect * 32'h08)) & 32'h000000ff;
    assign LH_IN = (IN >> (LoadedBytesSelect * 32'h08)) & 32'h0000ffff;
    always @(*)
    begin
        case(RegWriteW)
            `LB:	OUT<={{24{LB_IN[7]}},LB_IN[7:0]};
            `LH:    OUT<={{16{LH_IN[15]}},LH_IN[15:0]};
            `LW:    OUT<=IN;
            `LBU:   OUT<={24'b0,LB_IN[7:0]};
            `LHU:   OUT<={16'b0,LH_IN[15:0]};
            default:OUT = 32'hxxxxxxxx;
        endcase
    end
    
endmodule