data/full_repos/permissive/131358616/design/perceptron/uart_rx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:28: Operator VAR \'WAIT_START_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                   : ... In instance uart_rx\n    WAIT_START_st   = 3\'d0,\n    ^~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:29: Operator VAR \'INIT_SYNC_START_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h1\' generates 3 bits.\n                                                                                   : ... In instance uart_rx\n    INIT_SYNC_START_st  = 3\'d1,\n    ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:30: Operator VAR \'WAIT_SYNC_START_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h2\' generates 3 bits.\n                                                                                   : ... In instance uart_rx\n    WAIT_SYNC_START_st  = 3\'d2,\n    ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:31: Operator VAR \'INIT_SYNC_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h3\' generates 3 bits.\n                                                                                   : ... In instance uart_rx\n    INIT_SYNC_st      = 3\'d3,\n    ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:32: Operator VAR \'WAIT_SYNC_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                   : ... In instance uart_rx\n    WAIT_SYNC_st    = 3\'d4,\n    ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:33: Operator VAR \'FETCH_BIT_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                   : ... In instance uart_rx\n    FETCH_BIT_st    = 3\'d5,\n    ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:34: Operator VAR \'ERROR_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                   : ... In instance uart_rx\n    ERROR_st        = 3\'d6,\n    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:35: Operator VAR \'SUCCESS_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                   : ... In instance uart_rx\n    SUCCESS_st      = 3\'d7;\n    ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:64: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'WAIT_START_st\' generates 32 bits.\n                                                                                   : ... In instance uart_rx\n        state <= WAIT_START_st;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:91: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                                   : ... In instance uart_rx\n            data_int[bit_cnt] <= rx_synced;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:145: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INIT_SYNC_START_st\' generates 32 bits.\n                                                                                    : ... In instance uart_rx\n                next_state = INIT_SYNC_START_st;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:149: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'WAIT_SYNC_START_st\' generates 32 bits.\n                                                                                    : ... In instance uart_rx\n            next_state = WAIT_SYNC_START_st;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:154: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'WAIT_START_st\' generates 32 bits.\n                                                                                    : ... In instance uart_rx\n                    next_state = WAIT_START_st;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:156: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INIT_SYNC_st\' generates 32 bits.\n                                                                                    : ... In instance uart_rx\n                    next_state = INIT_SYNC_st;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:161: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'WAIT_SYNC_st\' generates 32 bits.\n                                                                                    : ... In instance uart_rx\n            next_state = WAIT_SYNC_st;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:166: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'FETCH_BIT_st\' generates 32 bits.\n                                                                                    : ... In instance uart_rx\n                    next_state = FETCH_BIT_st;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:168: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'ERROR_st\' generates 32 bits.\n                                                                                    : ... In instance uart_rx\n                    next_state = ERROR_st;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:170: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'SUCCESS_st\' generates 32 bits.\n                                                                                    : ... In instance uart_rx\n                    next_state = SUCCESS_st;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:175: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INIT_SYNC_st\' generates 32 bits.\n                                                                                    : ... In instance uart_rx\n            next_state = INIT_SYNC_st;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:178: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'WAIT_START_st\' generates 32 bits.\n                                                                                    : ... In instance uart_rx\n            next_state = WAIT_START_st;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:181: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'WAIT_START_st\' generates 32 bits.\n                                                                                    : ... In instance uart_rx\n            next_state = WAIT_START_st;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:142: Operator CASE expects 32 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 4 bits.\n                                                                                    : ... In instance uart_rx\n    case (state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:205: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 24 bits.\n                                                                                    : ... In instance uart_rx\n            sync_cnt_val = clock_cycles_per_pulse/2;  \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:213: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'clock_cycles_per_pulse\' generates 32 or 24 bits.\n                                                                                    : ... In instance uart_rx\n            sync_cnt_val = clock_cycles_per_pulse;   \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/perceptron/uart_rx.v:200: Operator CASE expects 32 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 4 bits.\n                                                                                    : ... In instance uart_rx\n    case (state)\n    ^~~~\n%Error: Exiting due to 25 warning(s)\n'
module uart_rx (
    input wire rst_n,
    input wire clk,
    input wire rx,
    input wire clear,
    output reg [7:0] data,   
    output reg busy,
    output reg error,
    output reg new_value
);

parameter  clock_frequency        = 12000000;
parameter  baud_rate              = 9600;

localparam clock_cycles_per_pulse = clock_frequency / baud_rate;

localparam integer 
    WAIT_START_st   = 3'd0,
    INIT_SYNC_START_st  = 3'd1,
    WAIT_SYNC_START_st  = 3'd2,
    INIT_SYNC_st      = 3'd3,
    WAIT_SYNC_st    = 3'd4,
    FETCH_BIT_st    = 3'd5,
    ERROR_st        = 3'd6,
    SUCCESS_st      = 3'd7;

reg [3:0] state, next_state;

reg data_ld;


reg rx_1, rx_synced;


reg [7:0] data_int, data_int_val;
reg data_int_ld;


reg error_set;
reg new_value_set;


reg [3:0] bit_cnt;
reg bit_cnt_ld, bit_cnt_en;


reg [15:0] sync_cnt, sync_cnt_val;
reg sync_cnt_ld, sync_cnt_en;



always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        state <= WAIT_START_st;
    end else begin
        state <= next_state;
    end
end


always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        rx_1 <= 1;
        rx_synced <= 1;
    end else begin
        rx_1 <= rx;
        rx_synced <= rx_1;
    end
end


always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        data <= 0;
        data_int <= 0;
    end else begin
        if (data_ld) begin
            data <= data_int;
        end
        if (data_int_ld) begin
            data_int[bit_cnt] <= rx_synced;
        end
    end
end



always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        error <= 0;
        new_value <= 0;
    end else begin
        if (clear) begin
            error <= 0;
            new_value <= 0;
        end
        if (new_value_set) begin 
            new_value <= 1;
        end
        if (error_set) begin 
            error <= 1;
        end
    end
end


always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        sync_cnt <= 0;
    end else if (sync_cnt_ld) begin
        sync_cnt <= sync_cnt_val;
    end else if (sync_cnt_en) begin
        sync_cnt <= sync_cnt - 1;
    end
end


always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        bit_cnt <= 0;
    end else if (bit_cnt_ld) begin
        bit_cnt <= 0;
    end else if (bit_cnt_en) begin
        bit_cnt <= bit_cnt + 1;
    end
end



always @(*) begin
    next_state = state;
    case (state)
        WAIT_START_st:
            if (!rx_synced) begin
                next_state = INIT_SYNC_START_st;
            end

        INIT_SYNC_START_st:
            next_state = WAIT_SYNC_START_st;

        WAIT_SYNC_START_st:
            if (sync_cnt == 0) begin
                if (rx_synced) begin
                    next_state = WAIT_START_st;
                end else begin
                    next_state = INIT_SYNC_st;
                end
            end

        INIT_SYNC_st:
            next_state = WAIT_SYNC_st;
        
        WAIT_SYNC_st:
            if (sync_cnt == 0) begin
                if (bit_cnt < 8) begin
                    next_state = FETCH_BIT_st;
                end else if (bit_cnt == 8 & !rx_synced) begin
                    next_state = ERROR_st;
                end else if (bit_cnt == 8 & rx_synced) begin
                    next_state = SUCCESS_st;
                end
            end

        FETCH_BIT_st:
            next_state = INIT_SYNC_st;

        ERROR_st:
            next_state = WAIT_START_st;

        SUCCESS_st:
            next_state = WAIT_START_st;

    endcase 
end



always @(*) begin
    busy = 1;
    data_ld = 0;
    data_int_ld = 0;
    error_set = 0;
    new_value_set = 0;
    bit_cnt_ld = 0;
    bit_cnt_en = 0;
    sync_cnt_val = 0;
    sync_cnt_ld = 0;
    sync_cnt_en = 0;
    
    case (state)
        WAIT_START_st: begin
            busy = 0;
        end
        INIT_SYNC_START_st: begin
            sync_cnt_val = clock_cycles_per_pulse/2;
            sync_cnt_ld = 1;
            bit_cnt_ld = 1;
        end
        WAIT_SYNC_START_st: begin
            sync_cnt_en = 1;
        end
        INIT_SYNC_st: begin
            sync_cnt_val = clock_cycles_per_pulse;
            sync_cnt_ld = 1;
        end
        WAIT_SYNC_st: begin
            sync_cnt_en = 1;
        end
        FETCH_BIT_st: begin
            bit_cnt_en = 1;
            data_int_ld = 1;
        end
        ERROR_st: begin
            error_set = 1;
        end
        SUCCESS_st: begin
            new_value_set = 1;
            data_ld = 1;
        end
    endcase 
end

endmodule
module uart_rx (
    input wire rst_n,
    input wire clk,
    input wire rx,
    input wire clear,
    output reg [7:0] data,   
    output reg busy,
    output reg error,
    output reg new_value
);


parameter  clock_frequency        = 12000000;
parameter  baud_rate              = 9600;

localparam clock_cycles_per_pulse = clock_frequency / baud_rate;

localparam integer 
    WAIT_START_st   = 3'd0,
    INIT_SYNC_START_st  = 3'd1,
    WAIT_SYNC_START_st  = 3'd2,
    INIT_SYNC_st      = 3'd3,
    WAIT_SYNC_st    = 3'd4,
    FETCH_BIT_st    = 3'd5,
    ERROR_st        = 3'd6,
    SUCCESS_st      = 3'd7;

reg [3:0] state, next_state;

reg data_ld;


reg rx_1, rx_synced;


reg [7:0] data_int, data_int_val;
reg data_int_ld;


reg error_set;
reg new_value_set;


reg [3:0] bit_cnt;
reg bit_cnt_ld, bit_cnt_en;


reg [15:0] sync_cnt, sync_cnt_val;
reg sync_cnt_ld, sync_cnt_en;



always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        state <= WAIT_START_st;
    end else begin
        state <= next_state;
    end
end


always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        rx_1 <= 1;
        rx_synced <= 1;
    end else begin
        rx_1 <= rx;
        rx_synced <= rx_1;
    end
end


always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        data <= 0;
        data_int <= 0;
    end else begin
        if (data_ld) begin
            data <= data_int;
        end
        if (data_int_ld) begin
            data_int[bit_cnt] <= rx_synced;
        end
    end
end



always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        error <= 0;
        new_value <= 0;
    end else begin
        if (clear) begin
            error <= 0;
            new_value <= 0;
        end
        if (new_value_set) begin 
            new_value <= 1;
        end
        if (error_set) begin 
            error <= 1;
        end
    end
end


always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        sync_cnt <= 0;
    end else if (sync_cnt_ld) begin
        sync_cnt <= sync_cnt_val;
    end else if (sync_cnt_en) begin
        sync_cnt <= sync_cnt - 1;
    end
end


always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        bit_cnt <= 0;
    end else if (bit_cnt_ld) begin
        bit_cnt <= 0;
    end else if (bit_cnt_en) begin
        bit_cnt <= bit_cnt + 1;
    end
end



always @(*) begin
    next_state = state;
    case (state)
        WAIT_START_st:
            if (!rx_synced) begin
                next_state = INIT_SYNC_START_st;
            end

        INIT_SYNC_START_st:
            next_state = WAIT_SYNC_START_st;

        WAIT_SYNC_START_st:
            if (sync_cnt == 0) begin
                if (rx_synced) begin
                    next_state = WAIT_START_st;
                end else begin
                    next_state = INIT_SYNC_st;
                end
            end

        INIT_SYNC_st:
            next_state = WAIT_SYNC_st;
        
        WAIT_SYNC_st:
            if (sync_cnt == 0) begin
                if (bit_cnt < 8) begin
                    next_state = FETCH_BIT_st;
                end else if (bit_cnt == 8 & !rx_synced) begin
                    next_state = ERROR_st;
                end else if (bit_cnt == 8 & rx_synced) begin
                    next_state = SUCCESS_st;
                end
            end

        FETCH_BIT_st:
            next_state = INIT_SYNC_st;

        ERROR_st:
            next_state = WAIT_START_st;

        SUCCESS_st:
            next_state = WAIT_START_st;

    endcase 
end



always @(*) begin
    busy = 1;
    data_ld = 0;
    data_int_ld = 0;
    error_set = 0;
    new_value_set = 0;
    bit_cnt_ld = 0;
    bit_cnt_en = 0;
    sync_cnt_val = 0;
    sync_cnt_ld = 0;
    sync_cnt_en = 0;
    
    case (state)
        WAIT_START_st: begin
            busy = 0;
        end
        INIT_SYNC_START_st: begin
            sync_cnt_val = clock_cycles_per_pulse/2;
            sync_cnt_ld = 1;
            bit_cnt_ld = 1;
        end
        WAIT_SYNC_START_st: begin
            sync_cnt_en = 1;
        end
        INIT_SYNC_st: begin
            sync_cnt_val = clock_cycles_per_pulse;
            sync_cnt_ld = 1;
        end
        WAIT_SYNC_st: begin
            sync_cnt_en = 1;
        end
        FETCH_BIT_st: begin
            bit_cnt_en = 1;
            data_int_ld = 1;
        end
        ERROR_st: begin
            error_set = 1;
        end
        SUCCESS_st: begin
            new_value_set = 1;
            data_ld = 1;
        end
    endcase 
end

endmodule