data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v
 line:103: before: ")"
1: b"%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:31: Define or directive not defined: '`CEILDIV_FUNC'\n   `CEILDIV_FUNC\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:103: Define or directive not defined: '`VLAN_ETHERTYPE'\n                  if(in_data[31:16] == `VLAN_ETHERTYPE) begin\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:103: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n                  if(in_data[31:16] == `VLAN_ETHERTYPE) begin\n                                                      ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:113: syntax error, unexpected end, expecting endcase\n            end\n            ^~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:123: syntax error, unexpected begin, expecting assert or assume or cover or restrict\n            WAIT_EOP: begin\n                      ^~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:146: syntax error, unexpected '=', expecting IDENTIFIER\n                  process_state_nxt = ADD_MODULE_HEADER;\n                                    ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:149: syntax error, unexpected '=', expecting IDENTIFIER\n                  process_state_nxt = SEND_UNMODIFIED_PKT;\n                                    ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:156: syntax error, unexpected '=', expecting IDENTIFIER\n               fifo_rd_en          = 1;\n                                   ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:159: Define or directive not defined: '`VLAN_CTRL_WORD'\n               out_ctrl_nxt        = `VLAN_CTRL_WORD;\n                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:166: syntax error, unexpected '=', expecting IDENTIFIER\n               fifo_rd_en     = 1;\n                              ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:170: Define or directive not defined: '`IO_QUEUE_STAGE_NUM'\n               if(fifo_ctrl_out_d1 == `IO_QUEUE_STAGE_NUM) begin\n                                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:170: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n               if(fifo_ctrl_out_d1 == `IO_QUEUE_STAGE_NUM) begin\n                                                         ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:172: Define or directive not defined: '`IOQ_BYTE_LEN_POS'\n                  out_data_nxt[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS]\n                               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:172: Define or directive not defined: '`IOQ_BYTE_LEN_POS'\n                  out_data_nxt[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS]\n                                                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:173: Define or directive not defined: '`IOQ_BYTE_LEN_POS'\n                     = fifo_data_out_d1[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] - 4;\n                                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:173: Define or directive not defined: '`IOQ_BYTE_LEN_POS'\n                     = fifo_data_out_d1[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] - 4;\n                                                             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:174: Define or directive not defined: '`IOQ_WORD_LEN_POS'\n                  out_data_nxt[`IOQ_WORD_LEN_POS+15:`IOQ_WORD_LEN_POS]\n                               ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:174: Define or directive not defined: '`IOQ_WORD_LEN_POS'\n                  out_data_nxt[`IOQ_WORD_LEN_POS+15:`IOQ_WORD_LEN_POS]\n                                                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:175: Define or directive not defined: '`IOQ_BYTE_LEN_POS'\n                     = ceildiv((fifo_data_out_d1[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] - 4), 8);\n                                                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:175: Define or directive not defined: '`IOQ_BYTE_LEN_POS'\n                     = ceildiv((fifo_data_out_d1[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] - 4), 8);\n                                                                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:178: syntax error, unexpected '=', expecting IDENTIFIER\n                  process_state_nxt   = REMOVE_VLAN;\n                                      ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:181: syntax error, unexpected end, expecting endcase\n         end  \n         ^~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:201: syntax error, unexpected '=', expecting IDENTIFIER\n                     out_ctrl_nxt = (fifo_ctrl_out >> 4);\n                                  ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:204: syntax error, unexpected '=', expecting IDENTIFIER\n                  process_state_nxt = WRITE_LAST_WORD;\n                                    ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_remover.v:274: syntax error, unexpected <=, expecting IDENTIFIER\n            fifo_data_out_d1 <= fifo_data_out;\n                             ^~\n%Error: Cannot continue\n"
module vlan_remover
    #(parameter DATA_WIDTH = 64,
      parameter CTRL_WIDTH = DATA_WIDTH/8
      )
   (
    input  [DATA_WIDTH-1:0]                in_data,
    input  [CTRL_WIDTH-1:0]                in_ctrl,
    input                                  in_wr,
    output                                 in_rdy,


    output reg [DATA_WIDTH-1:0]            out_data,
    output reg [CTRL_WIDTH-1:0]            out_ctrl,
    output reg                             out_wr,
    input                                  out_rdy,


    input                                  reset,
    input                                  clk
   );

   `CEILDIV_FUNC


   localparam SKIP_HDRS              = 0,
              CHECK_VLAN             = 1,
              GET_VLAN_TAG           = 2,
              WAIT_EOP               = 3;

   localparam NUM_STATES             = 7;
   localparam WAIT_PREPROCESS        = 0,
              ADD_MODULE_HEADER      = 1,
              WRITE_MODULE_HEADERS   = 2,
              REMOVE_VLAN            = 3,
              WRITE_MODIFIED_PKT     = 4,
              WRITE_LAST_WORD        = 5,
              SEND_UNMODIFIED_PKT    = 6;


   wire [DATA_WIDTH-1:0] fifo_data_out;
   wire [CTRL_WIDTH-1:0] fifo_ctrl_out;

   reg [3:0]             preprocess_state;
   reg [15:0]            vlan_tag;
   reg                   tag_vld, tag_found;

   reg [NUM_STATES-1:0]  process_state_nxt, process_state;
   reg                   fifo_rd_en;
   reg                   out_wr_nxt;
   reg [DATA_WIDTH-1:0]  out_data_nxt;
   reg [CTRL_WIDTH-1:0]  out_ctrl_nxt;
   reg [DATA_WIDTH-1:0]  fifo_data_out_d1;
   reg [CTRL_WIDTH-1:0]  fifo_ctrl_out_d1;


   fallthrough_small_fifo
     #(.WIDTH(CTRL_WIDTH+DATA_WIDTH), .MAX_DEPTH_BITS(3))
     input_fifo
       (.din           ({in_ctrl, in_data}),
        .wr_en         (in_wr),
        .rd_en         (fifo_rd_en),
        .dout          ({fifo_ctrl_out, fifo_data_out}),
        .full          (),
        .prog_full     (),
        .nearly_full   (fifo_nearly_full),
        .empty         (fifo_empty),
        .reset         (reset),
        .clk           (clk)
        );




   assign in_rdy = !fifo_nearly_full;


   always @(posedge clk) begin
      if(reset) begin
         preprocess_state    <= SKIP_HDRS;
         vlan_tag            <= 0;
         tag_vld             <= 0;
         tag_found           <= 0;
      end
      else begin
         case (preprocess_state)
            SKIP_HDRS: begin
               if (in_wr && in_ctrl==0) begin
                  preprocess_state <= CHECK_VLAN;
               end
            end

            CHECK_VLAN: begin
               if(in_wr) begin
                  if(in_data[31:16] == `VLAN_ETHERTYPE) begin
                     vlan_tag            <= in_data[15:0];
                     preprocess_state    <= GET_VLAN_TAG;
                  end
                  else begin
                     preprocess_state    <= WAIT_EOP;
                     tag_vld             <= 1'b1;
                     tag_found           <= 1'b0;
                  end
               end
            end

            GET_VLAN_TAG: begin
               if(in_wr) begin
                  tag_vld             <= 1'b1;
                  tag_found           <= 1'b1;
                  preprocess_state    <= WAIT_EOP;
               end
            end

            WAIT_EOP: begin
               if(in_wr && in_ctrl != 0) begin
                  tag_vld             <= 0;
                  preprocess_state    <= SKIP_HDRS;
               end
            end
            default:preprocess_state <=SKIP_HDRS;
         endcase
      end
   end


   always @(*) begin
      process_state_nxt   = process_state;
      fifo_rd_en          = 0;
      out_wr_nxt          = 0;
      out_data_nxt        = fifo_data_out;
      out_ctrl_nxt        = fifo_ctrl_out;

      case (process_state)
         WAIT_PREPROCESS: begin
            if(tag_vld) begin
               if(tag_found) begin
                  process_state_nxt = ADD_MODULE_HEADER;
               end
               else begin
                  process_state_nxt = SEND_UNMODIFIED_PKT;
               end
            end
         end

         ADD_MODULE_HEADER: begin
            if(out_rdy) begin
               fifo_rd_en          = 1;
               out_wr_nxt          = 1;
               out_data_nxt        = {{(DATA_WIDTH-16){1'b0}}, vlan_tag};
               out_ctrl_nxt        = `VLAN_CTRL_WORD;
               process_state_nxt   = WRITE_MODULE_HEADERS;
            end
         end

         WRITE_MODULE_HEADERS: begin
            if(out_rdy) begin
               fifo_rd_en     = 1;
               out_wr_nxt     = 1;
               out_data_nxt   = fifo_data_out_d1;
               out_ctrl_nxt   = fifo_ctrl_out_d1;
               if(fifo_ctrl_out_d1 == `IO_QUEUE_STAGE_NUM) begin

                  out_data_nxt[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS]
                     = fifo_data_out_d1[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] - 4;
                  out_data_nxt[`IOQ_WORD_LEN_POS+15:`IOQ_WORD_LEN_POS]
                     = ceildiv((fifo_data_out_d1[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] - 4), 8);
               end
               if(fifo_ctrl_out_d1 == 0) begin
                  process_state_nxt   = REMOVE_VLAN;
               end
            end
         end

         REMOVE_VLAN: begin
            if(out_rdy) begin
               process_state_nxt   = WRITE_MODIFIED_PKT;
               fifo_rd_en          = 1;
               out_wr_nxt          = 1;
               out_data_nxt        = {fifo_data_out_d1[63:32], fifo_data_out[63:32]};
               out_ctrl_nxt        = fifo_ctrl_out_d1;
            end
         end

         WRITE_MODIFIED_PKT: begin
            if(out_rdy && !fifo_empty) begin
               fifo_rd_en          = 1;
               out_wr_nxt          = 1;
               out_data_nxt        = {fifo_data_out_d1[31:0], fifo_data_out[63:32]};
               out_ctrl_nxt        = fifo_ctrl_out_d1;
               if(fifo_ctrl_out != 0) begin
                  if(fifo_ctrl_out[7:4] != 0) begin
                     out_ctrl_nxt = (fifo_ctrl_out >> 4);
                  end

                  process_state_nxt = WRITE_LAST_WORD;
               end
            end
         end

         WRITE_LAST_WORD: begin
            if(out_rdy) begin
               
               if(fifo_ctrl_out_d1[3:0] != 0) begin
                  out_ctrl_nxt = (fifo_ctrl_out_d1 << 4);
                  out_wr_nxt          = 1;
                  out_data_nxt        = {fifo_data_out_d1[31:0], 32'h600d_f00d};
               end
               else begin


                  out_ctrl_nxt = 0;
                  out_wr_nxt=0;
                  out_data_nxt=0;
               end
               if(tag_vld && tag_found) begin
                  process_state_nxt = ADD_MODULE_HEADER;
               end
               else if(tag_vld && !tag_found) begin
                  process_state_nxt = SEND_UNMODIFIED_PKT;
               end
               else begin
                  process_state_nxt = WAIT_PREPROCESS;
               end
            end
         end

         SEND_UNMODIFIED_PKT: begin
            if(out_rdy && !fifo_empty) begin
               if(fifo_ctrl_out_d1 == 0 && fifo_ctrl_out != 0) begin
                  if(tag_vld && tag_found) begin
                     process_state_nxt = ADD_MODULE_HEADER;
                  end
                  else if(tag_vld && !tag_found) begin
                     process_state_nxt = SEND_UNMODIFIED_PKT;
                  end
                  else begin
                     process_state_nxt = WAIT_PREPROCESS;
                  end
               end
               fifo_rd_en          = 1;
               out_wr_nxt          = 1;
               out_data_nxt        = fifo_data_out;
               out_ctrl_nxt        = fifo_ctrl_out;
            end
         end
      default:process_state_nxt=WAIT_PREPROCESS;
      endcase
   end

   always @(posedge clk) begin
      if(reset) begin
         process_state    <= WAIT_PREPROCESS;
         out_wr           <= 0;
         out_data         <= 0;
         out_ctrl         <= 1;
         fifo_data_out_d1 <= 0;
         fifo_ctrl_out_d1 <= 1;
      end
      else begin
         process_state    <= process_state_nxt;
         out_wr           <= out_wr_nxt;
         out_data         <= out_data_nxt;
         out_ctrl         <= out_ctrl_nxt;
         if(fifo_rd_en) begin
            fifo_data_out_d1 <= fifo_data_out;
            fifo_ctrl_out_d1 <= fifo_ctrl_out;
         end
      end
   end

endmodule
module vlan_remover
    #(parameter DATA_WIDTH = 64,
      parameter CTRL_WIDTH = DATA_WIDTH/8
      )
   (
    input  [DATA_WIDTH-1:0]                in_data,
    input  [CTRL_WIDTH-1:0]                in_ctrl,
    input                                  in_wr,
    output                                 in_rdy,


    output reg [DATA_WIDTH-1:0]            out_data,
    output reg [CTRL_WIDTH-1:0]            out_ctrl,
    output reg                             out_wr,
    input                                  out_rdy,


    input                                  reset,
    input                                  clk
   );


   `CEILDIV_FUNC


   localparam SKIP_HDRS              = 0,
              CHECK_VLAN             = 1,
              GET_VLAN_TAG           = 2,
              WAIT_EOP               = 3;

   localparam NUM_STATES             = 7;
   localparam WAIT_PREPROCESS        = 0,
              ADD_MODULE_HEADER      = 1,
              WRITE_MODULE_HEADERS   = 2,
              REMOVE_VLAN            = 3,
              WRITE_MODIFIED_PKT     = 4,
              WRITE_LAST_WORD        = 5,
              SEND_UNMODIFIED_PKT    = 6;


   wire [DATA_WIDTH-1:0] fifo_data_out;
   wire [CTRL_WIDTH-1:0] fifo_ctrl_out;

   reg [3:0]             preprocess_state;
   reg [15:0]            vlan_tag;
   reg                   tag_vld, tag_found;

   reg [NUM_STATES-1:0]  process_state_nxt, process_state;
   reg                   fifo_rd_en;
   reg                   out_wr_nxt;
   reg [DATA_WIDTH-1:0]  out_data_nxt;
   reg [CTRL_WIDTH-1:0]  out_ctrl_nxt;
   reg [DATA_WIDTH-1:0]  fifo_data_out_d1;
   reg [CTRL_WIDTH-1:0]  fifo_ctrl_out_d1;


   fallthrough_small_fifo
     #(.WIDTH(CTRL_WIDTH+DATA_WIDTH), .MAX_DEPTH_BITS(3))
     input_fifo
       (.din           ({in_ctrl, in_data}),
        .wr_en         (in_wr),
        .rd_en         (fifo_rd_en),
        .dout          ({fifo_ctrl_out, fifo_data_out}),
        .full          (),
        .prog_full     (),
        .nearly_full   (fifo_nearly_full),
        .empty         (fifo_empty),
        .reset         (reset),
        .clk           (clk)
        );




   assign in_rdy = !fifo_nearly_full;


   always @(posedge clk) begin
      if(reset) begin
         preprocess_state    <= SKIP_HDRS;
         vlan_tag            <= 0;
         tag_vld             <= 0;
         tag_found           <= 0;
      end
      else begin
         case (preprocess_state)
            SKIP_HDRS: begin
               if (in_wr && in_ctrl==0) begin
                  preprocess_state <= CHECK_VLAN;
               end
            end

            CHECK_VLAN: begin
               if(in_wr) begin
                  if(in_data[31:16] == `VLAN_ETHERTYPE) begin
                     vlan_tag            <= in_data[15:0];
                     preprocess_state    <= GET_VLAN_TAG;
                  end
                  else begin
                     preprocess_state    <= WAIT_EOP;
                     tag_vld             <= 1'b1;
                     tag_found           <= 1'b0;
                  end
               end
            end

            GET_VLAN_TAG: begin
               if(in_wr) begin
                  tag_vld             <= 1'b1;
                  tag_found           <= 1'b1;
                  preprocess_state    <= WAIT_EOP;
               end
            end

            WAIT_EOP: begin
               if(in_wr && in_ctrl != 0) begin
                  tag_vld             <= 0;
                  preprocess_state    <= SKIP_HDRS;
               end
            end
            default:preprocess_state <=SKIP_HDRS;
         endcase
      end
   end


   always @(*) begin
      process_state_nxt   = process_state;
      fifo_rd_en          = 0;
      out_wr_nxt          = 0;
      out_data_nxt        = fifo_data_out;
      out_ctrl_nxt        = fifo_ctrl_out;

      case (process_state)
         WAIT_PREPROCESS: begin
            if(tag_vld) begin
               if(tag_found) begin
                  process_state_nxt = ADD_MODULE_HEADER;
               end
               else begin
                  process_state_nxt = SEND_UNMODIFIED_PKT;
               end
            end
         end

         ADD_MODULE_HEADER: begin
            if(out_rdy) begin
               fifo_rd_en          = 1;
               out_wr_nxt          = 1;
               out_data_nxt        = {{(DATA_WIDTH-16){1'b0}}, vlan_tag};
               out_ctrl_nxt        = `VLAN_CTRL_WORD;
               process_state_nxt   = WRITE_MODULE_HEADERS;
            end
         end

         WRITE_MODULE_HEADERS: begin
            if(out_rdy) begin
               fifo_rd_en     = 1;
               out_wr_nxt     = 1;
               out_data_nxt   = fifo_data_out_d1;
               out_ctrl_nxt   = fifo_ctrl_out_d1;
               if(fifo_ctrl_out_d1 == `IO_QUEUE_STAGE_NUM) begin

                  out_data_nxt[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS]
                     = fifo_data_out_d1[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] - 4;
                  out_data_nxt[`IOQ_WORD_LEN_POS+15:`IOQ_WORD_LEN_POS]
                     = ceildiv((fifo_data_out_d1[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] - 4), 8);
               end
               if(fifo_ctrl_out_d1 == 0) begin
                  process_state_nxt   = REMOVE_VLAN;
               end
            end
         end

         REMOVE_VLAN: begin
            if(out_rdy) begin
               process_state_nxt   = WRITE_MODIFIED_PKT;
               fifo_rd_en          = 1;
               out_wr_nxt          = 1;
               out_data_nxt        = {fifo_data_out_d1[63:32], fifo_data_out[63:32]};
               out_ctrl_nxt        = fifo_ctrl_out_d1;
            end
         end

         WRITE_MODIFIED_PKT: begin
            if(out_rdy && !fifo_empty) begin
               fifo_rd_en          = 1;
               out_wr_nxt          = 1;
               out_data_nxt        = {fifo_data_out_d1[31:0], fifo_data_out[63:32]};
               out_ctrl_nxt        = fifo_ctrl_out_d1;
               if(fifo_ctrl_out != 0) begin
                  if(fifo_ctrl_out[7:4] != 0) begin
                     out_ctrl_nxt = (fifo_ctrl_out >> 4);
                  end

                  process_state_nxt = WRITE_LAST_WORD;
               end
            end
         end

         WRITE_LAST_WORD: begin
            if(out_rdy) begin
               
               if(fifo_ctrl_out_d1[3:0] != 0) begin
                  out_ctrl_nxt = (fifo_ctrl_out_d1 << 4);
                  out_wr_nxt          = 1;
                  out_data_nxt        = {fifo_data_out_d1[31:0], 32'h600d_f00d};
               end
               else begin


                  out_ctrl_nxt = 0;
                  out_wr_nxt=0;
                  out_data_nxt=0;
               end
               if(tag_vld && tag_found) begin
                  process_state_nxt = ADD_MODULE_HEADER;
               end
               else if(tag_vld && !tag_found) begin
                  process_state_nxt = SEND_UNMODIFIED_PKT;
               end
               else begin
                  process_state_nxt = WAIT_PREPROCESS;
               end
            end
         end

         SEND_UNMODIFIED_PKT: begin
            if(out_rdy && !fifo_empty) begin
               if(fifo_ctrl_out_d1 == 0 && fifo_ctrl_out != 0) begin
                  if(tag_vld && tag_found) begin
                     process_state_nxt = ADD_MODULE_HEADER;
                  end
                  else if(tag_vld && !tag_found) begin
                     process_state_nxt = SEND_UNMODIFIED_PKT;
                  end
                  else begin
                     process_state_nxt = WAIT_PREPROCESS;
                  end
               end
               fifo_rd_en          = 1;
               out_wr_nxt          = 1;
               out_data_nxt        = fifo_data_out;
               out_ctrl_nxt        = fifo_ctrl_out;
            end
         end
      default:process_state_nxt=WAIT_PREPROCESS;
      endcase
   end

   always @(posedge clk) begin
      if(reset) begin
         process_state    <= WAIT_PREPROCESS;
         out_wr           <= 0;
         out_data         <= 0;
         out_ctrl         <= 1;
         fifo_data_out_d1 <= 0;
         fifo_ctrl_out_d1 <= 1;
      end
      else begin
         process_state    <= process_state_nxt;
         out_wr           <= out_wr_nxt;
         out_data         <= out_data_nxt;
         out_ctrl         <= out_ctrl_nxt;
         if(fifo_rd_en) begin
            fifo_data_out_d1 <= fifo_data_out;
            fifo_ctrl_out_d1 <= fifo_ctrl_out;
         end
      end
   end

endmodule