data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/im.v
data/verilator_xmls/65b11243-e829-4f1a-ba7d-afbdea6a9aee.xml
module im(
    input wire[31:0]        pc,

    output wire[31:0]       instr
    );


    reg[31:0]               im[1023:0];

    wire[9:0] im_ad;
    assign im_ad = pc[11:2];


    assign instr = im[im_ad];

endmodule
module im(
    input wire[31:0]        pc,

    output wire[31:0]       instr
    );



    reg[31:0]               im[1023:0];

    wire[9:0] im_ad;
    assign im_ad = pc[11:2];


    assign instr = im[im_ad];

endmodule