data/full_repos/permissive/20430511/hardware/FPGA/wishbone/legacy/wb_prefetch_classic.v
 line:53: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/wishbone/legacy/wb_prefetch_classic.v:87: Operator COND expects 32 or 6 bits on the Conditional True, but Conditional True\'s REPLICATE generates 5 bits.\n                                                                                                          : ... In instance wb_prefetch_classic\n   wire [BBITS:0]      wrd_nxt = blk_inc ? {BBITS{1\'b0}} : adr[BSB:0]+1;\n                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/wishbone/legacy/wb_prefetch_classic.v:137: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'count_nxt\' generates 11 bits.\n                                                                                                           : ... In instance wb_prefetch_classic\n       count <= #DELAY count_nxt;\n             ^~\n%Error: Exiting due to 2 warning(s)\n'
module wb_prefetch_classic
  #(parameter WIDTH = 32,
    parameter MSB   = WIDTH-1,
    parameter COUNT = 576,
    parameter SBITS = 10,
    parameter SIZE  = 1 << SBITS,
    parameter ASB   = SBITS-1,
    parameter BSIZE = 24,
    parameter BBITS = 5,
    parameter BSTEP = (1 << BBITS) - BSIZE,
    parameter BSB   = BBITS-1,
    parameter UBITS = SBITS-BBITS,
    parameter USB   = UBITS-1,
    parameter DELAY = 3)
   (
    input          rst_i,
    input          clk_i,


    input          begin_i,
    output reg     ready_o = 0,


    output         a_cyc_o,
    output         a_stb_o,
    output         a_we_o,
    output         a_bst_o,
    input          a_ack_i,
    input          a_wat_i,
    input          a_err_i,
    output [ASB:0] a_adr_o,
    input [MSB:0]  a_dat_i,
    output [MSB:0] a_dat_o,


    output         b_cyc_o,
    output         b_stb_o,
    output         b_we_o,
    output         b_bst_o,
    input          b_ack_i,
    input          b_wat_i,
    output [ASB:0] b_adr_o,
    input [MSB:0]  b_dat_i,
    output [MSB:0] b_dat_o
    );

   reg [ASB:0]         count = {SBITS{1'b0}};
   reg [SBITS:0]       count_nxt;
   reg                 count_end = 1'b0;

   reg [MSB:0]         dat;
   reg [ASB:0]         adr = {SBITS{1'b0}};

   wire                blk_inc = adr[BSB:0] == BSIZE-1;
   wire [BBITS:0]      wrd_nxt = blk_inc ? {BBITS{1'b0}} : adr[BSB:0]+1;
   wire [UBITS:0]      blk_nxt = adr[ASB:UBITS] + (blk_inc ? 1 : 0);
   wire [ASB:0]        adr_nxt = {blk_nxt[USB:0], wrd_nxt[BSB:0]};

   assign a_cyc_o = pc[0];
   assign a_stb_o = pc[0];
   assign a_we_o  = 1'b0;
   assign a_bst_o = 1'b0;
   assign a_adr_o = adr;
   assign a_dat_o = {WIDTH{1'bz}};

   assign b_cyc_o = pc[1];
   assign b_stb_o = pc[1];
   assign b_we_o  = pc[1];
   assign b_bst_o = 1'b0;
   assign b_adr_o = adr;
   assign b_dat_o = dat;

   parameter PC_IDLE  = 0;
   parameter PC_FETCH = 1;
   parameter PC_STORE = 2;

   reg [1:0]           pc = PC_IDLE;

   always @(posedge clk_i)
     if (rst_i)
       pc <= #DELAY PC_IDLE;
     else
       case (pc)
         PC_IDLE:  if (begin_i) pc <= #DELAY PC_FETCH;
         PC_FETCH: if (a_ack_i) pc <= #DELAY PC_STORE;
         PC_STORE: if (b_ack_i) pc <= #DELAY count_end ? PC_IDLE : PC_FETCH;
       endcase

   always @(posedge clk_i)
     if (rst_i || begin_i)
       adr <= #DELAY {SBITS{1'b0}};
     else
       begin
          if (pc[0] && a_ack_i) dat <= #DELAY a_dat_i;
          if (pc[1] && b_ack_i) adr <= #DELAY adr_nxt;
       end




   always @(posedge clk_i)
     if (rst_i || begin_i)
       count <= #DELAY {SBITS{1'b0}};
     else if (pc[0] && a_ack_i)
       count <= #DELAY count_nxt;


   always @(posedge clk_i)
     if (rst_i || begin_i) ready_o <= #DELAY 1'b0;
     else                  ready_o <= #DELAY count_end && pc[1] && b_ack_i;



   always @(posedge clk_i) begin
      count_nxt <= #DELAY count + 1;
      count_end <= #DELAY !begin_i && count_nxt >= COUNT;
   end


endmodule
module wb_prefetch_classic
  #(parameter WIDTH = 32,
    parameter MSB   = WIDTH-1,
    parameter COUNT = 576,
    parameter SBITS = 10,
    parameter SIZE  = 1 << SBITS,
    parameter ASB   = SBITS-1,
    parameter BSIZE = 24,
    parameter BBITS = 5,
    parameter BSTEP = (1 << BBITS) - BSIZE,
    parameter BSB   = BBITS-1,
    parameter UBITS = SBITS-BBITS,
    parameter USB   = UBITS-1,
    parameter DELAY = 3)
   (
    input          rst_i,
    input          clk_i,


    input          begin_i,
    output reg     ready_o = 0,


    output         a_cyc_o,
    output         a_stb_o,
    output         a_we_o,
    output         a_bst_o,
    input          a_ack_i,
    input          a_wat_i,
    input          a_err_i,
    output [ASB:0] a_adr_o,
    input [MSB:0]  a_dat_i,
    output [MSB:0] a_dat_o,


    output         b_cyc_o,
    output         b_stb_o,
    output         b_we_o,
    output         b_bst_o,
    input          b_ack_i,
    input          b_wat_i,
    output [ASB:0] b_adr_o,
    input [MSB:0]  b_dat_i,
    output [MSB:0] b_dat_o
    );


   reg [ASB:0]         count = {SBITS{1'b0}};
   reg [SBITS:0]       count_nxt;
   reg                 count_end = 1'b0;

   reg [MSB:0]         dat;
   reg [ASB:0]         adr = {SBITS{1'b0}};

   wire                blk_inc = adr[BSB:0] == BSIZE-1;
   wire [BBITS:0]      wrd_nxt = blk_inc ? {BBITS{1'b0}} : adr[BSB:0]+1;
   wire [UBITS:0]      blk_nxt = adr[ASB:UBITS] + (blk_inc ? 1 : 0);
   wire [ASB:0]        adr_nxt = {blk_nxt[USB:0], wrd_nxt[BSB:0]};

   assign a_cyc_o = pc[0];
   assign a_stb_o = pc[0];
   assign a_we_o  = 1'b0;
   assign a_bst_o = 1'b0;
   assign a_adr_o = adr;
   assign a_dat_o = {WIDTH{1'bz}};

   assign b_cyc_o = pc[1];
   assign b_stb_o = pc[1];
   assign b_we_o  = pc[1];
   assign b_bst_o = 1'b0;
   assign b_adr_o = adr;
   assign b_dat_o = dat;

   parameter PC_IDLE  = 0;
   parameter PC_FETCH = 1;
   parameter PC_STORE = 2;

   reg [1:0]           pc = PC_IDLE;

   always @(posedge clk_i)
     if (rst_i)
       pc <= #DELAY PC_IDLE;
     else
       case (pc)
         PC_IDLE:  if (begin_i) pc <= #DELAY PC_FETCH;
         PC_FETCH: if (a_ack_i) pc <= #DELAY PC_STORE;
         PC_STORE: if (b_ack_i) pc <= #DELAY count_end ? PC_IDLE : PC_FETCH;
       endcase

   always @(posedge clk_i)
     if (rst_i || begin_i)
       adr <= #DELAY {SBITS{1'b0}};
     else
       begin
          if (pc[0] && a_ack_i) dat <= #DELAY a_dat_i;
          if (pc[1] && b_ack_i) adr <= #DELAY adr_nxt;
       end




   always @(posedge clk_i)
     if (rst_i || begin_i)
       count <= #DELAY {SBITS{1'b0}};
     else if (pc[0] && a_ack_i)
       count <= #DELAY count_nxt;


   always @(posedge clk_i)
     if (rst_i || begin_i) ready_o <= #DELAY 1'b0;
     else                  ready_o <= #DELAY count_end && pc[1] && b_ack_i;



   always @(posedge clk_i) begin
      count_nxt <= #DELAY count + 1;
      count_end <= #DELAY !begin_i && count_nxt >= COUNT;
   end


endmodule