data/full_repos/permissive/12880408/counter.v
1: b"%Error: data/full_repos/permissive/12880408/counter.v:23: Input/output/inout declaration not found for port: 'countEn'\nmodule counter(clock, reset, countEn, load, loadVal, n);\n                             ^~~~~~~\n%Error: data/full_repos/permissive/12880408/counter.v:24: Input/output/inout does not appear in port list: 'enable'\n input clock, enable, load, reset;\n              ^~~~~~\n%Error: data/full_repos/permissive/12880408/counter.v:30: Can't find definition of variable: 'countEn'\n always @(posedge clock or negedge reset or posedge load or posedge countEn) \n                                                                    ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module counter(clock, reset, countEn, load, loadVal, n);
	input clock, enable, load, reset;
	input [8:0] loadVal;
	output reg [8:0] n;
	
	initial n = 9'b000000000;
	
	always @(posedge clock or negedge reset or posedge load or posedge countEn) 
	begin
		if(!reset) n = 9'b000000000;
		else if(clock) begin
			if(!load && countEn) begin
				n = n + 1;
			end
			else if(load && !countEn) begin
				n = loadVal;
			end	
			else if(load && countEn) begin
				$display("Load and countEn both high! They should not both be high at the same time! Loading loadVal+1\n");
				n = loadVal + 1;
			end
			else begin

			end
		end
	end
endmodule
module counter(clock, reset, countEn, load, loadVal, n);

	input clock, enable, load, reset;
	input [8:0] loadVal;
	output reg [8:0] n;
	
	initial n = 9'b000000000;
	
	always @(posedge clock or negedge reset or posedge load or posedge countEn) 
	begin
		if(!reset) n = 9'b000000000;
		else if(clock) begin
			if(!load && countEn) begin
				n = n + 1;
			end
			else if(load && !countEn) begin
				n = loadVal;
			end	
			else if(load && countEn) begin
				$display("Load and countEn both high! They should not both be high at the same time! Loading loadVal+1\n");
				n = loadVal + 1;
			end
			else begin

			end
		end
	end
endmodule