data/full_repos/permissive/17580831/center_pos.v
1: b'%Warning-WIDTH: data/full_repos/permissive/17580831/center_pos.v:42: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'x_row\' generates 16 bits.\n                                                                   : ... In instance center_pos\n  center_x_temp = center_x_temp + x_row ;\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/17580831/center_pos.v:43: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'y_col\' generates 16 bits.\n                                                                   : ... In instance center_pos\n  center_y_temp = center_y_temp + y_col ;\n                                ^\n%Error: data/full_repos/permissive/17580831/center_pos.v:53: Cannot find file containing module: \'alt_div\'\nalt_div div_x(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17580831,data/full_repos/permissive/17580831/alt_div\n             data/full_repos/permissive/17580831,data/full_repos/permissive/17580831/alt_div.v\n             data/full_repos/permissive/17580831,data/full_repos/permissive/17580831/alt_div.sv\n             alt_div\n             alt_div.v\n             alt_div.sv\n             obj_dir/alt_div\n             obj_dir/alt_div.v\n             obj_dir/alt_div.sv\n%Error: data/full_repos/permissive/17580831/center_pos.v:60: Cannot find file containing module: \'alt_div\'\nalt_div div_y(\n^~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module center_pos(x_row , y_col ,reset , clk ,center_x,center_y,valid);
 
 input [15:0] x_row; 
 input [15:0] y_col ;
 input  reset;
 input clk ;
 input [15:0] valid ;
 output [15:0] center_x;
 output [15:0] center_y;
 
 reg [15:0] center_x;
 reg [15:0] center_y; 

 reg [31:0] center_x_temp;
 reg [31:0] center_y_temp;
 reg [31:0]pixel_counter ;
 reg [31 : 0 ] dirty ;
 
 always @ (posedge clk)
 
 begin
	if (dirty >= 32'h00075300 )
		begin



		
		center_x = 16'h1111;

		center_y = 16'h1111;
		center_x_temp = 32'h00000000;
		center_y_temp = 32'h00000000;
		pixel_counter = 32'h0000FFFF;
		dirty = 32'h00000000;
		
		end

	 else
	  begin
		center_y = dirty[31:16];
		center_x = 16'hAAAA;
		center_x_temp = center_x_temp + x_row ;
		center_y_temp = center_y_temp + y_col ;
		pixel_counter = pixel_counter + 32'h00000001;
		dirty = dirty + 32'h00000001;
		end
	
 end

wire [31:0] result_x;
wire [31:0] result_y; 

alt_div div_x(
	.denom(pixel_counter),
	.numer(center_x_temp),
	.quotient(result_x),
	.remain());
 
 
alt_div div_y(
	.denom(pixel_counter),
	.numer(center_y_temp),
	.quotient(result_y),
	.remain());


	

endmodule
module center_pos(x_row , y_col ,reset , clk ,center_x,center_y,valid);

 
 input [15:0] x_row; 
 input [15:0] y_col ;
 input  reset;
 input clk ;
 input [15:0] valid ;
 output [15:0] center_x;
 output [15:0] center_y;
 
 reg [15:0] center_x;
 reg [15:0] center_y; 

 reg [31:0] center_x_temp;
 reg [31:0] center_y_temp;
 reg [31:0]pixel_counter ;
 reg [31 : 0 ] dirty ;
 
 always @ (posedge clk)
 
 begin
	if (dirty >= 32'h00075300 )
		begin



		
		center_x = 16'h1111;

		center_y = 16'h1111;
		center_x_temp = 32'h00000000;
		center_y_temp = 32'h00000000;
		pixel_counter = 32'h0000FFFF;
		dirty = 32'h00000000;
		
		end

	 else
	  begin
		center_y = dirty[31:16];
		center_x = 16'hAAAA;
		center_x_temp = center_x_temp + x_row ;
		center_y_temp = center_y_temp + y_col ;
		pixel_counter = pixel_counter + 32'h00000001;
		dirty = dirty + 32'h00000001;
		end
	
 end

wire [31:0] result_x;
wire [31:0] result_y; 

alt_div div_x(
	.denom(pixel_counter),
	.numer(center_x_temp),
	.quotient(result_x),
	.remain());
 
 
alt_div div_y(
	.denom(pixel_counter),
	.numer(center_y_temp),
	.quotient(result_y),
	.remain());


	

endmodule