data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/lfsr_throttle.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/lfsr_throttle.v:63: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'cfg_paddr\' generates 5 bits.\n                                                                                                     : ... In instance lfsr_throttle\n    addr_i = cfg_paddr >> 2;  \n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/lfsr_throttle.v:70: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_pwdata\' generates 32 bits.\n                                                                                                     : ... In instance lfsr_throttle\n          RateAddr:     cfg_rate <= cfg_pwdata;\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/lfsr_throttle.v:76: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                     : ... In instance lfsr_throttle\n          StatusAddr:   cfg_prdata <= {dout_ready, dout_valid,\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/lfsr_throttle.v:78: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'cfg_rate\' generates 8 bits.\n                                                                                                     : ... In instance lfsr_throttle\n          RateAddr:     cfg_prdata <= cfg_rate;\n                                   ^~\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern/lfsr_throttle.v:95: Cannot find file containing module: \'lfsr15_shift\'\n  lfsr15_shift #(\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern,data/full_repos/permissive/181738725/lfsr15_shift\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern,data/full_repos/permissive/181738725/lfsr15_shift.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/pattern,data/full_repos/permissive/181738725/lfsr15_shift.sv\n             lfsr15_shift\n             lfsr15_shift.v\n             lfsr15_shift.sv\n             obj_dir/lfsr15_shift\n             obj_dir/lfsr15_shift.v\n             obj_dir/lfsr15_shift.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module lfsr_throttle #(
  parameter Seed = 1,
  parameter RateDefault = 128)

(
  input             cfg_clk,
  input             cfg_rst,
  input [4:0]       cfg_paddr,
  input             cfg_pwrite,
  input [31:0]      cfg_pwdata,
  input             cfg_psel,
  input             cfg_penable,
  output            cfg_pready,
  output reg [31:0] cfg_prdata,
  output            cfg_pslverr,

  input             data_clk,
  input             data_rst,
  input             din_valid,
  output            din_ready,
  output            dout_valid,
  input             dout_ready
  );




  localparam StatusAddr = 0,
             RateAddr   = 1;




  assign cfg_pready  = 1;
  assign cfg_pslverr = 0;

  reg [7:0]           cfg_rate;

  always @(posedge cfg_clk) begin :cfg
    integer addr_i;
    addr_i = cfg_paddr >> 2;

    if (cfg_psel && !cfg_penable) begin


      if (cfg_pwrite) begin
        case (addr_i)
          RateAddr:     cfg_rate <= cfg_pwdata;
        endcase


      end else begin
        case (addr_i)
          StatusAddr:   cfg_prdata <= {dout_ready, dout_valid,
                                       din_ready,  din_valid};
          RateAddr:     cfg_prdata <= cfg_rate;
        endcase
      end
    end

    if (cfg_rst) begin
      cfg_rate <= RateDefault;
    end
  end




  wire       lfsr_en;
  wire [7:0] lfsr_data;
  reg        active;

  lfsr15_shift #(
    .DataBits (8),
    .LfsrSeed (Seed))
  lfsr (
    .clk       (data_clk),
    .rst       (data_rst),
    .seed      (Seed),
    .init      (1'b0),
    .shift     (lfsr_en),
    .lfsr_data (lfsr_data)
    );

  assign lfsr_en = (!active || (din_valid & din_ready));




  reg [7:0]  rate_r, rate_rr;

  always @(posedge data_clk) begin



    {rate_rr, rate_r}  <= {rate_r, cfg_rate};


    if (lfsr_en) begin
      if (rate_rr == 0) begin
        active <= 0;
      end else begin
        active <= (lfsr_data[7:0] <= rate_rr) ? 1 : 0;
      end
    end

    if (data_rst) begin
      active  <= 0;
      rate_r  <= RateDefault;
      rate_rr <= RateDefault;
    end
  end

  assign dout_valid = (active) ? din_valid  : 0;
  assign din_ready  = (active) ? dout_ready : 0;

endmodule
module lfsr_throttle #(
  parameter Seed = 1,
  parameter RateDefault = 128)

(
  input             cfg_clk,
  input             cfg_rst,
  input [4:0]       cfg_paddr,
  input             cfg_pwrite,
  input [31:0]      cfg_pwdata,
  input             cfg_psel,
  input             cfg_penable,
  output            cfg_pready,
  output reg [31:0] cfg_prdata,
  output            cfg_pslverr,

  input             data_clk,
  input             data_rst,
  input             din_valid,
  output            din_ready,
  output            dout_valid,
  input             dout_ready
  );





  localparam StatusAddr = 0,
             RateAddr   = 1;




  assign cfg_pready  = 1;
  assign cfg_pslverr = 0;

  reg [7:0]           cfg_rate;

  always @(posedge cfg_clk) begin :cfg
    integer addr_i;
    addr_i = cfg_paddr >> 2;

    if (cfg_psel && !cfg_penable) begin


      if (cfg_pwrite) begin
        case (addr_i)
          RateAddr:     cfg_rate <= cfg_pwdata;
        endcase


      end else begin
        case (addr_i)
          StatusAddr:   cfg_prdata <= {dout_ready, dout_valid,
                                       din_ready,  din_valid};
          RateAddr:     cfg_prdata <= cfg_rate;
        endcase
      end
    end

    if (cfg_rst) begin
      cfg_rate <= RateDefault;
    end
  end




  wire       lfsr_en;
  wire [7:0] lfsr_data;
  reg        active;

  lfsr15_shift #(
    .DataBits (8),
    .LfsrSeed (Seed))
  lfsr (
    .clk       (data_clk),
    .rst       (data_rst),
    .seed      (Seed),
    .init      (1'b0),
    .shift     (lfsr_en),
    .lfsr_data (lfsr_data)
    );

  assign lfsr_en = (!active || (din_valid & din_ready));




  reg [7:0]  rate_r, rate_rr;

  always @(posedge data_clk) begin



    {rate_rr, rate_r}  <= {rate_r, cfg_rate};


    if (lfsr_en) begin
      if (rate_rr == 0) begin
        active <= 0;
      end else begin
        active <= (lfsr_data[7:0] <= rate_rr) ? 1 : 0;
      end
    end

    if (data_rst) begin
      active  <= 0;
      rate_r  <= RateDefault;
      rate_rr <= RateDefault;
    end
  end

  assign dout_valid = (active) ? din_valid  : 0;
  assign din_ready  = (active) ? dout_ready : 0;

endmodule