data/full_repos/permissive/163494071/count_num/count_num_5/count_num_5.v
data/verilator_xmls/b0d3ab77-02b2-4a78-b575-0d817da0121e.xml
module debounce(clk, key, led);
input key,clk;
 
output led;
 
reg  led;
reg sysclk;
reg [18:0]cnt_20ms;
 
always @(posedge clk)
begin
    cnt_20ms <= cnt_20ms + 1;
if(cnt_20ms == 19'd500000 )
    sysclk <= ~sysclk;
end
 
reg key_low;
 
always @( posedge sysclk)
begin
key_low <= key; 
end
 
reg key_low_r;
 
always @( posedge clk)
begin
 
key_low_r <= key_low; 
end
 
wire led_ctrl;
assign led_ctrl = key_low_r & (!key_low);
 
always @( posedge clk)
begin
if( led_ctrl == 1)
led <= ~led;
end
 
endmodule
module debounce(clk, key, led);

input key,clk;
 
output led;
 
reg  led;
reg sysclk;
reg [18:0]cnt_20ms;
 
always @(posedge clk)
begin
    cnt_20ms <= cnt_20ms + 1;
if(cnt_20ms == 19'd500000 )
    sysclk <= ~sysclk;
end
 
reg key_low;
 
always @( posedge sysclk)
begin
key_low <= key; 
end
 
reg key_low_r;
 
always @( posedge clk)
begin
 
key_low_r <= key_low; 
end
 
wire led_ctrl;
assign led_ctrl = key_low_r & (!key_low);
 
always @( posedge clk)
begin
if( led_ctrl == 1)
led <= ~led;
end
 
endmodule