data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v
data/verilator_xmls/384b7a45-4d24-449b-aa32-ae8ea3249ed6.xml
module and2_pipelined(
  clk,
  a,
  b,
  c);

input wire clk;
input wire a;
input wire b;
output wire c;

reg a_reg;
reg b_reg;
reg c_reg;

always @(posedge clk) begin
  a_reg <= a;
  b_reg <= b;
end

always @(posedge clk) begin
  c_reg <= a_reg & b_reg;
end

assign c = c_reg;

endmodule
module and2_pipelined(
  clk,
  a,
  b,
  c);


input wire clk;
input wire a;
input wire b;
output wire c;

reg a_reg;
reg b_reg;
reg c_reg;

always @(posedge clk) begin
  a_reg <= a;
  b_reg <= b;
end

always @(posedge clk) begin
  c_reg <= a_reg & b_reg;
end

assign c = c_reg;

endmodule