data/full_repos/permissive/118895561/Project 3/led.v
1: b'%Error: Cannot find file containing module: 3,data/full_repos/permissive/118895561\n        ... Looked in:\n             data/full_repos/permissive/118895561/Project/3,data/full_repos/permissive/118895561\n             data/full_repos/permissive/118895561/Project/3,data/full_repos/permissive/118895561.v\n             data/full_repos/permissive/118895561/Project/3,data/full_repos/permissive/118895561.sv\n             3,data/full_repos/permissive/118895561\n             3,data/full_repos/permissive/118895561.v\n             3,data/full_repos/permissive/118895561.sv\n             obj_dir/3,data/full_repos/permissive/118895561\n             obj_dir/3,data/full_repos/permissive/118895561.v\n             obj_dir/3,data/full_repos/permissive/118895561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/118895561/Project\n%Error: Cannot find file containing module: 3/led.v\n%Error: Exiting due to 3 error(s)\n'
module led(
    input clk,
    input reset,
    input addr,
    output [15:0] digit0,
    output [15:0] digit1,
    output [3:0] digit2,
    input we,
	 input  [31:0] in,
    output [31:0] out
    );
	
	reg [31:0] Reg[1:0];
	
	assign out = (addr == 1'b0) ? Reg[0] :
											Reg[1] ;
	
	assign digit0 = Reg[0][15:0];
	
	assign digit1 = Reg[0][31:16];
	
	assign digit2 = Reg[1][3:0];
	
	always @(posedge clk) begin
		if(reset) begin
			Reg[0] <= 0;
			Reg[1] <= 0; 
		end
		else begin
			if(we) begin
				if(addr) begin
					Reg[1] <= in;
				end
				else begin
					Reg[0] <= in;
				end
			end
		end
	end
endmodule
module led(
    input clk,
    input reset,
    input addr,
    output [15:0] digit0,
    output [15:0] digit1,
    output [3:0] digit2,
    input we,
	 input  [31:0] in,
    output [31:0] out
    );

	
	reg [31:0] Reg[1:0];
	
	assign out = (addr == 1'b0) ? Reg[0] :
											Reg[1] ;
	
	assign digit0 = Reg[0][15:0];
	
	assign digit1 = Reg[0][31:16];
	
	assign digit2 = Reg[1][3:0];
	
	always @(posedge clk) begin
		if(reset) begin
			Reg[0] <= 0;
			Reg[1] <= 0; 
		end
		else begin
			if(we) begin
				if(addr) begin
					Reg[1] <= in;
				end
				else begin
					Reg[0] <= in;
				end
			end
		end
	end
endmodule