data/full_repos/permissive/164484080/rtl/ram.v
1: b'%Error: data/full_repos/permissive/164484080/rtl/ram.v:22: Cannot find include file: config.v\n`include "config.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164484080/rtl,data/full_repos/permissive/164484080/config.v\n             data/full_repos/permissive/164484080/rtl,data/full_repos/permissive/164484080/config.v.v\n             data/full_repos/permissive/164484080/rtl,data/full_repos/permissive/164484080/config.v.sv\n             config.v\n             config.v.v\n             config.v.sv\n             obj_dir/config.v\n             obj_dir/config.v.v\n             obj_dir/config.v.sv\n%Error: data/full_repos/permissive/164484080/rtl/ram.v:23: Cannot find include file: wishbone.v\n`include "wishbone.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/ram.v:24: Cannot find include file: utils.v\n`include "utils.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/ram.v:33: Define or directive not defined: \'`WB_SLAVE_PORT_SIGNALS\'\n    `WB_SLAVE_PORT_SIGNALS(ram_)\n    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/ram.v:33: syntax error, unexpected \'(\', expecting \'[\'\n    `WB_SLAVE_PORT_SIGNALS(ram_)\n                           ^~~~\n%Error: data/full_repos/permissive/164484080/rtl/ram.v:40: Define or directive not defined: \'`DAT_WIDTH\'\n    reg [`DAT_WIDTH-1:0] r_dat_o;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/ram.v:44: Define or directive not defined: \'`DAT_WIDTH\'\n    reg [`DAT_WIDTH-1:0] memory [0:WORDS-1];\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/ram.v:46: syntax error, unexpected assign\n    assign ram_ack_o = ram_stb_i ? r_ack : 1\'b0;\n    ^~~~~~\n%Error: Exiting due to 8 error(s)\n'
module ram (
    input rst_i,
    input clk_i,

    `WB_SLAVE_PORT_SIGNALS(ram_)
);


    parameter WORDS = 128;

    reg state = `STATE_IDLE;
    reg [`DAT_WIDTH-1:0] r_dat_o;
    reg r_ack = 1'h0;
    reg r_err = 1'h0;

    reg [`DAT_WIDTH-1:0] memory [0:WORDS-1];

    assign ram_ack_o = ram_stb_i ? r_ack : 1'b0;
    assign ram_err_o = ram_stb_i ? r_err : 1'b0;
    assign ram_dat_o = r_dat_o;

    always @(posedge clk_i) begin
        if (rst_i) begin
            state <= `STATE_IDLE;
            r_ack <= 1'h0;
            r_err <= 1'h0;
        end else begin
            case (state)
                `STATE_IDLE: begin
                    if (ram_stb_i) begin
                        state <= `STATE_WAIT_FOR_PHASE_END;

                        if ((ram_adr_i >> 3) >= WORDS) begin

                            r_ack <= 1'h0;
                            r_err <= 1'h1;
                        end else begin
                            if (ram_we_i) begin


                                memory[(ram_adr_i & 64'hffff) >> 3] <= ram_dat_i;
                            end else begin
                                r_dat_o <= memory[(ram_adr_i & 64'hffff) >> 3];
                            end

                            r_ack <= 1'h1;
                            r_err <= 1'h0;
                        end
                    end
                end
                `STATE_WAIT_FOR_PHASE_END: begin
                    if (~ram_stb_i) begin
                        state <= `STATE_IDLE;
                        r_ack <= 1'h0;
                        r_err <= 1'h0;
                    end
                end
            endcase
        end
    end

endmodule
module ram (
    input rst_i,
    input clk_i,

    `WB_SLAVE_PORT_SIGNALS(ram_)
);



    parameter WORDS = 128;

    reg state = `STATE_IDLE;
    reg [`DAT_WIDTH-1:0] r_dat_o;
    reg r_ack = 1'h0;
    reg r_err = 1'h0;

    reg [`DAT_WIDTH-1:0] memory [0:WORDS-1];

    assign ram_ack_o = ram_stb_i ? r_ack : 1'b0;
    assign ram_err_o = ram_stb_i ? r_err : 1'b0;
    assign ram_dat_o = r_dat_o;

    always @(posedge clk_i) begin
        if (rst_i) begin
            state <= `STATE_IDLE;
            r_ack <= 1'h0;
            r_err <= 1'h0;
        end else begin
            case (state)
                `STATE_IDLE: begin
                    if (ram_stb_i) begin
                        state <= `STATE_WAIT_FOR_PHASE_END;

                        if ((ram_adr_i >> 3) >= WORDS) begin

                            r_ack <= 1'h0;
                            r_err <= 1'h1;
                        end else begin
                            if (ram_we_i) begin


                                memory[(ram_adr_i & 64'hffff) >> 3] <= ram_dat_i;
                            end else begin
                                r_dat_o <= memory[(ram_adr_i & 64'hffff) >> 3];
                            end

                            r_ack <= 1'h1;
                            r_err <= 1'h0;
                        end
                    end
                end
                `STATE_WAIT_FOR_PHASE_END: begin
                    if (~ram_stb_i) begin
                        state <= `STATE_IDLE;
                        r_ack <= 1'h0;
                        r_err <= 1'h0;
                    end
                end
            endcase
        end
    end

endmodule