data/full_repos/permissive/106408053/verilog/trigger_adv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/trigger_adv.v:394: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/106408053/verilog/trigger_adv.v:546: syntax error, unexpected final, expecting IDENTIFIER\ntrigterm_4bit final ({2\'h0,mid1_sum,mid0_sum}, clock, wrenb, dout_mid1, dout_final, hit);\n              ^~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module trigstate (term_hits, clock, wrenb, wraddr, din, hit);
input [31:0] term_hits;
input clock;
input wrenb;
input [1:0] wraddr;
input din;
output [2:0] hit;

reg [3:0] wrenb_sum;
always @*
begin
  wrenb_sum = 0;
  wrenb_sum[wraddr] = wrenb;	
end

trigsum hit_sum (term_hits, clock, wrenb_sum[0], din, hit_term);
trigsum else_sum (term_hits, clock, wrenb_sum[1], din, else_term);
trigsum capture_sum (term_hits, clock, wrenb_sum[2], din, capture_term);


reg [2:0] hit, next_hit;
always @ (posedge clock) hit = next_hit;
always @* next_hit = {capture_term, else_term, hit_term};

endmodule
module trigstate (term_hits, clock, wrenb, wraddr, din, hit);

input [31:0] term_hits;
input clock;
input wrenb;
input [1:0] wraddr;
input din;
output [2:0] hit;

reg [3:0] wrenb_sum;
always @*
begin
  wrenb_sum = 0;
  wrenb_sum[wraddr] = wrenb;	
end

trigsum hit_sum (term_hits, clock, wrenb_sum[0], din, hit_term);
trigsum else_sum (term_hits, clock, wrenb_sum[1], din, else_term);
trigsum capture_sum (term_hits, clock, wrenb_sum[2], din, capture_term);


reg [2:0] hit, next_hit;
always @ (posedge clock) hit = next_hit;
always @* next_hit = {capture_term, else_term, hit_term};

endmodule