data/full_repos/permissive/131069375/nano-risc/verilog/data_mem.v
data/verilator_xmls/691d046b-bb01-46e3-b7ad-03f8cabcf6c7.xml
module data_mem
(
 input 	       clk,
 input [7:0]  data_in,
 input [7:0]  addr,
 input 	       we,
 output [7:0] data_out
);
   reg [7:0] 	ram[0:255];

   initial begin

      ram[0] = 0;

      ram[1] = 24;

      ram[2] = 7;

      ram[3] = 0;

      ram[4] = 0;

      ram[5] = 1;
   end
   
   always @(posedge clk)
     if (we)
       ram[addr] <= data_in;

   assign data_out = ram[addr];
   
endmodule
module data_mem
(
 input 	       clk,
 input [7:0]  data_in,
 input [7:0]  addr,
 input 	       we,
 output [7:0] data_out
);

   reg [7:0] 	ram[0:255];

   initial begin

      ram[0] = 0;

      ram[1] = 24;

      ram[2] = 7;

      ram[3] = 0;

      ram[4] = 0;

      ram[5] = 1;
   end
   
   always @(posedge clk)
     if (we)
       ram[addr] <= data_in;

   assign data_out = ram[addr];
   
endmodule