data/full_repos/permissive/131921633/tv/Mips/mips.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:1: Cannot find include file: Mips/mips_pipeline.v\n`include "Mips/mips_pipeline.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips,data/full_repos/permissive/131921633/Mips/mips_pipeline.v\n             data/full_repos/permissive/131921633/tv/Mips,data/full_repos/permissive/131921633/Mips/mips_pipeline.v.v\n             data/full_repos/permissive/131921633/tv/Mips,data/full_repos/permissive/131921633/Mips/mips_pipeline.v.sv\n             Mips/mips_pipeline.v\n             Mips/mips_pipeline.v.v\n             Mips/mips_pipeline.v.sv\n             obj_dir/Mips/mips_pipeline.v\n             obj_dir/Mips/mips_pipeline.v.v\n             obj_dir/Mips/mips_pipeline.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:2: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:8: Define or directive not defined: \'`Data_Control_Control_T\'\n`Data_Control_Control_T(reg) ctrl;\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:8: syntax error, unexpected \'(\'\n`Data_Control_Control_T(reg) ctrl;\n                        ^~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:17: Define or directive not defined: \'`Data_Control_Control_Clock\'\ninitial `Data_Control_Control_Clock(ctrl) = 1\'b0;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:17: syntax error, unexpected \'=\'\ninitial `Data_Control_Control_Clock(ctrl) = 1\'b0;\n                                          ^\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:18: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways #5 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:18: syntax error, unexpected \'=\'\nalways #5 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n                                            ^\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:18: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways #5 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n                                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Mips/mips.sv:18: Unsupported: Ignoring delay on this delayed statement.\nalways #5 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Mips/mips.sv:21: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:22: Define or directive not defined: \'`Data_Control_Control_Reset\'\n `Data_Control_Control_Reset(ctrl) = 1\'b1;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:22: syntax error, unexpected \'=\'\n `Data_Control_Control_Reset(ctrl) = 1\'b1;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Mips/mips.sv:23: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:24: Define or directive not defined: \'`Data_Control_Control_Reset\'\n `Data_Control_Control_Reset(ctrl) = 1\'b0;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/mips.sv:24: syntax error, unexpected \'=\'\n `Data_Control_Control_Reset(ctrl) = 1\'b0;\n                                   ^\n%Error: Exiting due to 13 error(s), 3 warning(s)\n'
module Mips_mips_tb #
	( parameter FILE = "asm/old/test0.mif"
	)();

`Data_Control_Control_T(reg) ctrl;

Mips_mips_pipeline #
	( .FILE (FILE)
	) DUT
	( .ctrl (ctrl)
	, .pcAddr ()
	);

initial `Data_Control_Control_Clock(ctrl) = 1'b0;
always #5 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);

initial begin
	#0;
	`Data_Control_Control_Reset(ctrl) = 1'b1;
	#20;
	`Data_Control_Control_Reset(ctrl) = 1'b0;
end

endmodule
module Mips_mips_tb #
	( parameter FILE = "asm/old/test0.mif"
	)();


`Data_Control_Control_T(reg) ctrl;

Mips_mips_pipeline #
	( .FILE (FILE)
	) DUT
	( .ctrl (ctrl)
	, .pcAddr ()
	);

initial `Data_Control_Control_Clock(ctrl) = 1'b0;
always #5 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);

initial begin
	#0;
	`Data_Control_Control_Reset(ctrl) = 1'b1;
	#20;
	`Data_Control_Control_Reset(ctrl) = 1'b0;
end

endmodule