data/full_repos/permissive/155217800/Part 5/Part5.v
1: b'%Error: Cannot find file containing module: 5,data/full_repos/permissive/155217800\n        ... Looked in:\n             data/full_repos/permissive/155217800/Part/5,data/full_repos/permissive/155217800\n             data/full_repos/permissive/155217800/Part/5,data/full_repos/permissive/155217800.v\n             data/full_repos/permissive/155217800/Part/5,data/full_repos/permissive/155217800.sv\n             5,data/full_repos/permissive/155217800\n             5,data/full_repos/permissive/155217800.v\n             5,data/full_repos/permissive/155217800.sv\n             obj_dir/5,data/full_repos/permissive/155217800\n             obj_dir/5,data/full_repos/permissive/155217800.v\n             obj_dir/5,data/full_repos/permissive/155217800.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/155217800/Part\n%Error: Cannot find file containing module: 5/Part5.v\n%Error: Exiting due to 3 error(s)\n'
module Part5(

	SW,
	HEX0,
	HEX1
);



input  [8:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;

wire [3:0] A;
wire [3:0] B;
wire c_0;
assign A = SW[3:0];
assign B = SW[7:4];
assign c_0 = SW[8];



reg [3:0] sum;
reg [3:0] z;
reg [3:0] s0;
reg c_1;

always @ (A or B or c_0) begin 
	sum = A + B + c_0;
end

always @ (sum or z or c_1) begin
	if (sum > 10) begin
		z = 10;
		c_1 = 1;
	end else begin
		z = 0;
		c_1 = 0;
	end
	s0 = sum - z;
end



wire [6:0] display0;
wire [6:0] display1;

full_display(s0, display0);
half_display(c_1, display1);

assign HEX1 = display1;
assign HEX0 = display0;

endmodule
module Part5(

	SW,
	HEX0,
	HEX1
);




input  [8:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;

wire [3:0] A;
wire [3:0] B;
wire c_0;
assign A = SW[3:0];
assign B = SW[7:4];
assign c_0 = SW[8];



reg [3:0] sum;
reg [3:0] z;
reg [3:0] s0;
reg c_1;

always @ (A or B or c_0) begin 
	sum = A + B + c_0;
end

always @ (sum or z or c_1) begin
	if (sum > 10) begin
		z = 10;
		c_1 = 1;
	end else begin
		z = 0;
		c_1 = 0;
	end
	s0 = sum - z;
end



wire [6:0] display0;
wire [6:0] display1;

full_display(s0, display0);
half_display(c_1, display1);

assign HEX1 = display1;
assign HEX0 = display0;

endmodule