data/full_repos/permissive/134757352/mojo-io-shield/src/led_dimmer.v
1: b"%Error: data/full_repos/permissive/134757352/mojo-io-shield/src/led_dimmer.v:18: Cannot find file containing module: 'pwm'\n  pwm #(PWM_LEN) pwm_ctrl (clk, rst, level_q, pwm_active);\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/134757352/mojo-io-shield/src,data/full_repos/permissive/134757352/pwm\n             data/full_repos/permissive/134757352/mojo-io-shield/src,data/full_repos/permissive/134757352/pwm.v\n             data/full_repos/permissive/134757352/mojo-io-shield/src,data/full_repos/permissive/134757352/pwm.sv\n             pwm\n             pwm.v\n             pwm.sv\n             obj_dir/pwm\n             obj_dir/pwm.v\n             obj_dir/pwm.sv\n%Error: Exiting due to 1 error(s)\n"
module led_dimmer #(
    parameter OUT_LEN = 8,
    parameter PWM_LEN = 4
  )(
    input clk,
    input rst,
    input up,
    input down,
    input [OUT_LEN-1:0] value,
    output [OUT_LEN-1:0] out
  );

  wire pwm_active;
  reg [PWM_LEN-1:0] level_d, level_q;

  assign out = value & {OUT_LEN{pwm_active}};

  pwm #(PWM_LEN) pwm_ctrl (clk, rst, level_q, pwm_active);

  always @(*) begin
    level_d = level_q;

    if (up) begin
      if (~&level_q)
        level_d = level_q + 1'b1;
    end else if (down) begin
      if (level_q > 1)
        level_d = level_q - 1'b1;
    end
  end

  always @(posedge clk) begin
    if (rst) begin
      level_q <= {PWM_LEN{1'b1}};
    end else begin
      level_q <= level_d;
    end
  end

endmodule
module led_dimmer #(
    parameter OUT_LEN = 8,
    parameter PWM_LEN = 4
  )(
    input clk,
    input rst,
    input up,
    input down,
    input [OUT_LEN-1:0] value,
    output [OUT_LEN-1:0] out
  );


  wire pwm_active;
  reg [PWM_LEN-1:0] level_d, level_q;

  assign out = value & {OUT_LEN{pwm_active}};

  pwm #(PWM_LEN) pwm_ctrl (clk, rst, level_q, pwm_active);

  always @(*) begin
    level_d = level_q;

    if (up) begin
      if (~&level_q)
        level_d = level_q + 1'b1;
    end else if (down) begin
      if (level_q > 1)
        level_d = level_q - 1'b1;
    end
  end

  always @(posedge clk) begin
    if (rst) begin
      level_q <= {PWM_LEN{1'b1}};
    end else begin
      level_q <= level_d;
    end
  end

endmodule