data/full_repos/permissive/208741034/flip_flop/rtl/flip_flop.v
data/verilator_xmls/848fc517-7a14-4caa-8ac7-f9b6a20aabd6.xml
module flip_flop(
    input  sys_clk,
	 input  sys_rst_n,
	 input  key_in,
    
	 output reg led_out
);










always @(posedge sys_clk or negedge sys_rst_n)begin
	if(sys_rst_n == 1'b0)
	   led_out <= 1'b0;
	else
	  led_out <= key_in;
end

endmodule
module flip_flop(
    input  sys_clk,
	 input  sys_rst_n,
	 input  key_in,
    
	 output reg led_out
);











always @(posedge sys_clk or negedge sys_rst_n)begin
	if(sys_rst_n == 1'b0)
	   led_out <= 1'b0;
	else
	  led_out <= key_in;
end

endmodule