data/full_repos/permissive/143278/ivltests/port-test2.v
 line:13: before: ","
1: b'%Error: data/full_repos/permissive/143278/ivltests/port-test2.v:13: syntax error, unexpected \',\', expecting \'[\'\n    ,\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test2.v:57: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/port-test2.v:72: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module port_test;

   reg [7:0] data;

`ifdef TEST3
   wire [7:0] out_3;
   reg	      pass_3;
   initial    pass_3 = 1;
   port_3 dut_3
     (,
`ifdef TEST3_X




      pass_3,
`else
      ,
`endif
      data[7:0],
      ,
      out_3[7:0],

      );
`endif

   initial
     begin
	data <= 1;
	#1;

	while (data != 0)
	  begin
	     $display ("%b", data);

`ifdef TEST3
	     if (out_3 != data)
	       begin
		  $display("data=%b, out_2=%b, FAILED", data, out_3);
		  pass_3 = 0;
	       end
`endif

	     data <= data << 1;
	     #1;
	  end

`ifdef TEST3
	if (pass_3)
	  $display("PASSED");
`endif

	$finish;
     end

endmodule
module port_test;


   reg [7:0] data;

`ifdef TEST3
   wire [7:0] out_3;
   reg	      pass_3;
   initial    pass_3 = 1;
   port_3 dut_3
     (,
`ifdef TEST3_X




      pass_3,
`else
      ,
`endif
      data[7:0],
      ,
      out_3[7:0],

      );
`endif

   initial
     begin
	data <= 1;
	#1;

	while (data != 0)
	  begin
	     $display ("%b", data);

`ifdef TEST3
	     if (out_3 != data)
	       begin
		  $display("data=%b, out_2=%b, FAILED", data, out_3);
		  pass_3 = 0;
	       end
`endif

	     data <= data << 1;
	     #1;
	  end

`ifdef TEST3
	if (pass_3)
	  $display("PASSED");
`endif

	$finish;
     end

endmodule