data/full_repos/permissive/148324174/FIFO/wptr_full.v
1: b'%Warning-WIDTH: data/full_repos/permissive/148324174/FIFO/wptr_full.v:26: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'winc\' generates 1 bits.\n                                                                        : ... In instance wptr_full\n    wbnext = (!wfull)? (wbin + winc) : wbin;\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module wptr_full #(
    parameter ADDRSIZE = 4
    )(
    output     [ADDRSIZE-1:0] waddr,
    output reg [ADDRSIZE:0]   wptr,
    output reg                wfull,
    input      [ADDRSIZE:0]   wrptr2,
    input                     winc, wclk, wrst
    );

reg [ADDRSIZE:0] wbin, wgnext, wbnext;


always @(posedge wclk or posedge wrst) begin
    if (wrst) begin
        wptr <= 0;
        wbin <= 0;
    end
    else begin
        wptr <= wgnext;
        wbin <= wbnext;
    end
end

always @(*) begin
    wbnext = (!wfull)? (wbin + winc) : wbin;
    wgnext = (wbnext>>1)^wbnext;
end


assign waddr = wbin[ADDRSIZE-1:0];


always @(posedge wclk or posedge wrst) begin
    if (wrst) wfull <= 1'b0;
    else wfull <= ((wgnext[ADDRSIZE]     != wrptr2[ADDRSIZE]  ) &&
                   (wgnext[ADDRSIZE-1]   != wrptr2[ADDRSIZE-1]) &&
                   (wgnext[ADDRSIZE-2:0] == wrptr2[ADDRSIZE-2:0]));
end

endmodule
module wptr_full #(
    parameter ADDRSIZE = 4
    )(
    output     [ADDRSIZE-1:0] waddr,
    output reg [ADDRSIZE:0]   wptr,
    output reg                wfull,
    input      [ADDRSIZE:0]   wrptr2,
    input                     winc, wclk, wrst
    );


reg [ADDRSIZE:0] wbin, wgnext, wbnext;


always @(posedge wclk or posedge wrst) begin
    if (wrst) begin
        wptr <= 0;
        wbin <= 0;
    end
    else begin
        wptr <= wgnext;
        wbin <= wbnext;
    end
end

always @(*) begin
    wbnext = (!wfull)? (wbin + winc) : wbin;
    wgnext = (wbnext>>1)^wbnext;
end


assign waddr = wbin[ADDRSIZE-1:0];


always @(posedge wclk or posedge wrst) begin
    if (wrst) wfull <= 1'b0;
    else wfull <= ((wgnext[ADDRSIZE]     != wrptr2[ADDRSIZE]  ) &&
                   (wgnext[ADDRSIZE-1]   != wrptr2[ADDRSIZE-1]) &&
                   (wgnext[ADDRSIZE-2:0] == wrptr2[ADDRSIZE-2:0]));
end

endmodule