data/full_repos/permissive/157049472/Verilog Source Files/InstructionDecoder.v
1: b'%Error: Cannot find file containing module: Source\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Source\n             data/full_repos/permissive/157049472/Verilog/Source.v\n             data/full_repos/permissive/157049472/Verilog/Source.sv\n             Source\n             Source.v\n             Source.sv\n             obj_dir/Source\n             obj_dir/Source.v\n             obj_dir/Source.sv\n%Error: Cannot find file containing module: Files,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Files/InstructionDecoder.v\n%Error: Exiting due to 4 error(s)\n'
module InstructionDecoder( input wire[31:0] instruction, output wire [5:0] opcode, 
									output wire [4:0] reg_addr_1, output wire [4:0] reg_addr_2,
									output wire [4:0] shift_amount, output wire [10:0] opcode_ext,
									output wire [20:0] immediate_const, output wire [25:0] offset);
								
assign opcode = instruction[31:26];
assign reg_addr_1 = instruction[25:21];
assign reg_addr_2 = instruction[20:16];
assign shift_amount = instruction[15:11];
assign opcode_ext = instruction[10:0];
assign immediate_const = instruction[20:0];
assign offset = instruction[25:0];

endmodule
module InstructionDecoder( input wire[31:0] instruction, output wire [5:0] opcode, 
									output wire [4:0] reg_addr_1, output wire [4:0] reg_addr_2,
									output wire [4:0] shift_amount, output wire [10:0] opcode_ext,
									output wire [20:0] immediate_const, output wire [25:0] offset);

								
assign opcode = instruction[31:26];
assign reg_addr_1 = instruction[25:21];
assign reg_addr_2 = instruction[20:16];
assign shift_amount = instruction[15:11];
assign opcode_ext = instruction[10:0];
assign immediate_const = instruction[20:0];
assign offset = instruction[25:0];

endmodule