data/full_repos/permissive/13953309/NW_vc_buffers.v
 line:49: before: "integer"
1: b'%Error: data/full_repos/permissive/13953309/NW_vc_buffers.v:33: Cannot find include file: NW_functions.v\n   `include "NW_functions.v" \n            ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/13953309,data/full_repos/permissive/13953309/NW_functions.v\n             data/full_repos/permissive/13953309,data/full_repos/permissive/13953309/NW_functions.v.v\n             data/full_repos/permissive/13953309,data/full_repos/permissive/13953309/NW_functions.v.sv\n             NW_functions.v\n             NW_functions.v.v\n             NW_functions.v.sv\n             obj_dir/NW_functions.v\n             obj_dir/NW_functions.v.v\n             obj_dir/NW_functions.v.sv\n%Error: data/full_repos/permissive/13953309/NW_vc_buffers.v:48: syntax error, unexpected IDENTIFIER, expecting \';\'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_vc_buffers.v:53: syntax error, unexpected IDENTIFIER, expecting \';\'\n   output    fifo_elements_t data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_vc_buffers.v:54: syntax error, unexpected IDENTIFIER, expecting \';\'\n   output    fifov_flags_t flags [n-1:0];\n                           ^~~~~\n%Error: data/full_repos/permissive/13953309/NW_vc_buffers.v:55: syntax error, unexpected IDENTIFIER, expecting \';\'\n   output    output_port_t output_port [n-1:0];\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_vc_buffers.v:56: syntax error, unexpected IDENTIFIER, expecting \';\'\n   output    flit_t data_in_reg;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_vc_buffers.v:57: syntax error, unexpected IDENTIFIER, expecting \';\'\n   output    fifo_elements_t flit_buffer_out [n-1:0];\n                             ^~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module NW_vc_buffers (push, pop, data_in, vc_id, select, 
		      data_out, output_port, data_in_reg, 
		      flags, buf_finished_empty,
		      head_is_tail, flit_buffer_out,
		      clk, rst_n);

   `include "NW_functions.v"
      

   parameter size = 3;

   parameter n = 4;



   parameter optimize_fifo_fields = 0;                         

   parameter output_all_head_flits = 0;

   input     push;
   input     [n-1:0] pop;
   input     fifo_elements_t data_in;
   input     [clogb2(n)-1:0] vc_id;

   input [n-1:0] 	     select;

   output    fifo_elements_t data_out;
   output    fifov_flags_t flags [n-1:0];
   output    output_port_t output_port [n-1:0];
   output    flit_t data_in_reg;
   output    fifo_elements_t flit_buffer_out [n-1:0];

   output [n-1:0] head_is_tail;
   



   output    [n-1:0] buf_finished_empty;
   
   input     clk, rst_n;


   fifo_elements_t sel_fifo_out;
   

   fifo_elements_t in_reg;

   fifo_elements_t fifo_out [n-1:0];

   logic [n-1:0] push_fifo, pop_fifo;

   logic [n-1:0] fifo_bypass;

   logic [n-1:0] fifo_bypass2;

   output_port_t op_fifo_out [n-1:0];
   control_flit_t control_fifo_out [n-1:0];
   
   genvar i;
   integer j;

   assign  data_in_reg = in_reg;
   assign  buf_finished_empty = fifo_bypass;


   
   generate
   for (i=0; i<n; i++) begin:vcbufs

      if (optimize_fifo_fields) begin











	 NW_fifo_v #(.init_fifo_contents(0), 

		     .size(size),
		     .output_reg(0),
		     .input_reg(1)
		     ) vc_fifo_c
	   (.push(push_fifo[i]), 
	    .pop(pop_fifo[i]), 
	    .data_in(in_reg.control), 
	    .data_out(control_fifo_out[i]), 
	    .flags(flags[i]),
	    .clk, .rst_n);


	 NW_fifo_v #(.init_fifo_contents(0), 

		     .size(size),
		     .output_reg(1),
		     .input_reg(1)
		     ) vc_fifo_op
	   (.push(push_fifo[i]), 
	    .pop(pop_fifo[i]), 
	    .data_in(in_reg.control.output_port), 
	    .data_out(op_fifo_out[i]), 

	    .clk, .rst_n);

	 always_comb
	   begin
	      fifo_out[i].control = control_fifo_out[i];
	      fifo_out[i].control.output_port = op_fifo_out[i];
	   end
	 

	 NW_fifo_v #(.init_fifo_contents(0), 

		     .size(size),
		     .output_reg(0),
		     .input_reg(1)
		     ) vc_fifo_d
	   (.push(push_fifo[i]), 
	    .pop(pop_fifo[i]), 
	    .data_in(in_reg.data), 
	    .data_out(fifo_out[i].data),

	    .clk, .rst_n);

   `ifdef DEBUG

	 NW_fifo_v #(.init_fifo_contents(0), 

		     .size(size),
		     .output_reg(1),
		     .input_reg(1)
		     ) vc_fifo
	   (.push(push_fifo[i]), 
	    .pop(pop_fifo[i]), 



	    .clk, .rst_n);
   `endif
	 
      end else begin




	 NW_fifo_v #(.init_fifo_contents(0), 

		     .size(size),
		     .output_reg(0),
		     .input_reg(1)
		     ) vc_fifo
	   (.push(push_fifo[i]), 
	    .pop(pop_fifo[i]), 
	    .data_in(in_reg), 
	    .data_out(fifo_out[i]),
	    .flags(flags[i]),
	    .clk, .rst_n);
      end
	 
      always@(posedge clk) begin
	 if (!rst_n) begin
	    fifo_bypass[i] <= 1'b1;
	    
	    fifo_bypass2[i] <= 1'b1;
	 end else begin
	    fifo_bypass[i] <= flags[i].empty || (flags[i].nearly_empty && pop_fifo[i]);

	    fifo_bypass2[i] <= flags[i].empty || (flags[i].nearly_empty && pop_fifo[i]);
	 end
      end

      assign push_fifo[i] = push & (vc_id==i);
      assign pop_fifo[i] = pop[i];

      assign head_is_tail[i] = fifo_out[i].control.tail;



   assign output_port[i] = 
	  fifo_bypass2[i] ? in_reg.control.output_port : fifo_out[i].control.output_port;
   
   end
   endgenerate




   NW_mux_oh_select #( .n(n)) 
     fifosel (.data_in(fifo_out), .select(select), .data_out(sel_fifo_out));
   assign sel_fifo_bypass = |(fifo_bypass & select);
   assign data_out = sel_fifo_bypass ? in_reg : sel_fifo_out;




   generate
      if (output_all_head_flits) begin
	 for (i=0; i<n; i++) begin:allvcs
	    assign flit_buffer_out[i] = (fifo_bypass[i]) ? in_reg : fifo_out[i];
	 end
      end
   endgenerate




   always@(posedge clk) begin

      if (!rst_n) begin
	 in_reg.control.valid <= 1'b0;
	 in_reg.control.tail <= 1'b1;
	 in_reg.control.output_port <='0;
      end else begin
	 if (push) begin
	    in_reg <= data_in;
	 end else begin
	    in_reg.control.valid<=1'b0;
	    in_reg.control.output_port<='0;
	 end
      end
   end

endmodule
module NW_vc_buffers (push, pop, data_in, vc_id, select, 
		      data_out, output_port, data_in_reg, 
		      flags, buf_finished_empty,
		      head_is_tail, flit_buffer_out,
		      clk, rst_n);


   `include "NW_functions.v"
      

   parameter size = 3;

   parameter n = 4;



   parameter optimize_fifo_fields = 0;                         

   parameter output_all_head_flits = 0;

   input     push;
   input     [n-1:0] pop;
   input     fifo_elements_t data_in;
   input     [clogb2(n)-1:0] vc_id;

   input [n-1:0] 	     select;

   output    fifo_elements_t data_out;
   output    fifov_flags_t flags [n-1:0];
   output    output_port_t output_port [n-1:0];
   output    flit_t data_in_reg;
   output    fifo_elements_t flit_buffer_out [n-1:0];

   output [n-1:0] head_is_tail;
   



   output    [n-1:0] buf_finished_empty;
   
   input     clk, rst_n;


   fifo_elements_t sel_fifo_out;
   

   fifo_elements_t in_reg;

   fifo_elements_t fifo_out [n-1:0];

   logic [n-1:0] push_fifo, pop_fifo;

   logic [n-1:0] fifo_bypass;

   logic [n-1:0] fifo_bypass2;

   output_port_t op_fifo_out [n-1:0];
   control_flit_t control_fifo_out [n-1:0];
   
   genvar i;
   integer j;

   assign  data_in_reg = in_reg;
   assign  buf_finished_empty = fifo_bypass;


   
   generate
   for (i=0; i<n; i++) begin:vcbufs

      if (optimize_fifo_fields) begin











	 NW_fifo_v #(.init_fifo_contents(0), 

		     .size(size),
		     .output_reg(0),
		     .input_reg(1)
		     ) vc_fifo_c
	   (.push(push_fifo[i]), 
	    .pop(pop_fifo[i]), 
	    .data_in(in_reg.control), 
	    .data_out(control_fifo_out[i]), 
	    .flags(flags[i]),
	    .clk, .rst_n);


	 NW_fifo_v #(.init_fifo_contents(0), 

		     .size(size),
		     .output_reg(1),
		     .input_reg(1)
		     ) vc_fifo_op
	   (.push(push_fifo[i]), 
	    .pop(pop_fifo[i]), 
	    .data_in(in_reg.control.output_port), 
	    .data_out(op_fifo_out[i]), 

	    .clk, .rst_n);

	 always_comb
	   begin
	      fifo_out[i].control = control_fifo_out[i];
	      fifo_out[i].control.output_port = op_fifo_out[i];
	   end
	 

	 NW_fifo_v #(.init_fifo_contents(0), 

		     .size(size),
		     .output_reg(0),
		     .input_reg(1)
		     ) vc_fifo_d
	   (.push(push_fifo[i]), 
	    .pop(pop_fifo[i]), 
	    .data_in(in_reg.data), 
	    .data_out(fifo_out[i].data),

	    .clk, .rst_n);

   `ifdef DEBUG

	 NW_fifo_v #(.init_fifo_contents(0), 

		     .size(size),
		     .output_reg(1),
		     .input_reg(1)
		     ) vc_fifo
	   (.push(push_fifo[i]), 
	    .pop(pop_fifo[i]), 



	    .clk, .rst_n);
   `endif
	 
      end else begin




	 NW_fifo_v #(.init_fifo_contents(0), 

		     .size(size),
		     .output_reg(0),
		     .input_reg(1)
		     ) vc_fifo
	   (.push(push_fifo[i]), 
	    .pop(pop_fifo[i]), 
	    .data_in(in_reg), 
	    .data_out(fifo_out[i]),
	    .flags(flags[i]),
	    .clk, .rst_n);
      end
	 
      always@(posedge clk) begin
	 if (!rst_n) begin
	    fifo_bypass[i] <= 1'b1;
	    
	    fifo_bypass2[i] <= 1'b1;
	 end else begin
	    fifo_bypass[i] <= flags[i].empty || (flags[i].nearly_empty && pop_fifo[i]);

	    fifo_bypass2[i] <= flags[i].empty || (flags[i].nearly_empty && pop_fifo[i]);
	 end
      end

      assign push_fifo[i] = push & (vc_id==i);
      assign pop_fifo[i] = pop[i];

      assign head_is_tail[i] = fifo_out[i].control.tail;



   assign output_port[i] = 
	  fifo_bypass2[i] ? in_reg.control.output_port : fifo_out[i].control.output_port;
   
   end
   endgenerate




   NW_mux_oh_select #( .n(n)) 
     fifosel (.data_in(fifo_out), .select(select), .data_out(sel_fifo_out));
   assign sel_fifo_bypass = |(fifo_bypass & select);
   assign data_out = sel_fifo_bypass ? in_reg : sel_fifo_out;




   generate
      if (output_all_head_flits) begin
	 for (i=0; i<n; i++) begin:allvcs
	    assign flit_buffer_out[i] = (fifo_bypass[i]) ? in_reg : fifo_out[i];
	 end
      end
   endgenerate




   always@(posedge clk) begin

      if (!rst_n) begin
	 in_reg.control.valid <= 1'b0;
	 in_reg.control.tail <= 1'b1;
	 in_reg.control.output_port <='0;
      end else begin
	 if (push) begin
	    in_reg <= data_in;
	 end else begin
	    in_reg.control.valid<=1'b0;
	    in_reg.control.output_port<='0;
	 end
      end
   end

endmodule