data/full_repos/permissive/219219909/Complex_Multiplier/adder_4bit.v
 line:41: before: "output"
data/verilator_xmls/5415f297-ab03-45f1-9df0-ed85b68fc94b.xml
module adder_4bit(
    input a,
    input b,
    input c,
    input d,
    output s,
    output c0,
    output c1
    );

wire s1,s2;

xor M1 (s1,a,b);
xor M2 (s2,c,d);
xor M3 (s,s1,s2);
assign c0=(~a&c&d)|(a&~c&d)|(a&b&~d)|(a&~b&c)|(~a&b&c&~d)|(~a&b&~c&d);
assign c1=a&b&c&d;

endmodule
module adder_4bit(
    input a,
    input b,
    input c,
    input d,
    output s,
    output c0,
    output c1
    );


wire s1,s2;

xor M1 (s1,a,b);
xor M2 (s2,c,d);
xor M3 (s,s1,s2);
assign c0=(~a&c&d)|(a&~c&d)|(a&b&~d)|(a&~b&c)|(~a&b&c&~d)|(~a&b&~c&d);
assign c1=a&b&c&d;

endmodule