data/full_repos/permissive/189013641/src/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:44: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk=~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #100 rst_n =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #80 rst_n =1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #120;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:58: Unsupported: Ignoring delay on this delayed statement.\n   #8681 rx=0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #8681 rx=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #8681 rx=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #8681 rx=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #8681 rx=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #8681 rx=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #8681 rx=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #8681 rx=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #8681 rx=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/189013641/src/test.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #8681 rx=1;\n  ^\n%Error: data/full_repos/permissive/189013641/src/test.v:37: Cannot find file containing module: \'uart_top\'\n uart_top uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/189013641/src,data/full_repos/permissive/189013641/uart_top\n             data/full_repos/permissive/189013641/src,data/full_repos/permissive/189013641/uart_top.v\n             data/full_repos/permissive/189013641/src,data/full_repos/permissive/189013641/uart_top.sv\n             uart_top\n             uart_top.v\n             uart_top.sv\n             obj_dir/uart_top\n             obj_dir/uart_top.v\n             obj_dir/uart_top.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_v;


	reg clk;
	reg rst_n;
	reg rx;
	


	wire tx;


	uart_top uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.rx(rx), 
		.tx(tx)
		);

  always #10 clk=~clk;
  
	initial begin

		clk = 0;
		rst_n = 1;
		rx = 1;



		#100 rst_n =0;
		#80 rst_n =1;
		#120;
		
			#8681 rx=0;
		
		#8681 rx=1;
		#8681 rx=0;
		#8681 rx=1;
		#8681 rx=1;
		#8681 rx=0;
		#8681 rx=1;
		#8681 rx=0;
		#8681 rx=0;
		
		#8681 rx=1;



	end
      
endmodule
module test_v;



	reg clk;
	reg rst_n;
	reg rx;
	


	wire tx;


	uart_top uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.rx(rx), 
		.tx(tx)
		);

  always #10 clk=~clk;
  
	initial begin

		clk = 0;
		rst_n = 1;
		rx = 1;



		#100 rst_n =0;
		#80 rst_n =1;
		#120;
		
			#8681 rx=0;
		
		#8681 rx=1;
		#8681 rx=0;
		#8681 rx=1;
		#8681 rx=1;
		#8681 rx=0;
		#8681 rx=1;
		#8681 rx=0;
		#8681 rx=0;
		
		#8681 rx=1;



	end
      
endmodule