data/full_repos/permissive/209534045/Arcade-DigDug.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/209534045/Arcade-DigDug.sv:72: Cannot find include file: build_id.v\n`include "build_id.v"  \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/209534045,data/full_repos/permissive/209534045/build_id.v\n             data/full_repos/permissive/209534045,data/full_repos/permissive/209534045/build_id.v.v\n             data/full_repos/permissive/209534045,data/full_repos/permissive/209534045/build_id.v.sv\n             build_id.v\n             build_id.v.v\n             build_id.v.sv\n             obj_dir/build_id.v\n             obj_dir/build_id.v.v\n             obj_dir/build_id.v.sv\n%Error: data/full_repos/permissive/209534045/Arcade-DigDug.sv:90: Define or directive not defined: \'`BUILD_DATE\'\n "V,v",`BUILD_DATE\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/209534045/Arcade-DigDug.sv:91: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n};\n^\n%Error: Exiting due to 3 error(s)\n'
module HVGEN
(
	output  [8:0]		HPOS,
	output  [8:0]		VPOS,
	input 				PCLK,
	input	 [11:0]		iRGB,

	output reg [11:0]	oRGB,
	output reg			HBLK = 1,
	output reg			VBLK = 1,
	output reg			HSYN = 1,
	output reg			VSYN = 1
);

reg [8:0] hcnt = 0;
reg [8:0] vcnt = 0;

assign HPOS = hcnt;
assign VPOS = vcnt;

always @(posedge PCLK) begin
	case (hcnt)
		288: begin HBLK <= 1; hcnt <= hcnt+1; end
		311: begin HSYN <= 0; hcnt <= hcnt+1; end
		342: begin HSYN <= 1; hcnt <= 471;    end
		511: begin HBLK <= 0; hcnt <= 0;
			case (vcnt)
				223: begin VBLK <= 1; vcnt <= vcnt+1; end
				226: begin VSYN <= 0; vcnt <= vcnt+1; end
				233: begin VSYN <= 1; vcnt <= 483;	  end
				511: begin VBLK <= 0; vcnt <= 0;		  end
				default: vcnt <= vcnt+1;
			endcase
		end
		default: hcnt <= hcnt+1;
	endcase
	oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
end

endmodule
module HVGEN
(
	output  [8:0]		HPOS,
	output  [8:0]		VPOS,
	input 				PCLK,
	input	 [11:0]		iRGB,

	output reg [11:0]	oRGB,
	output reg			HBLK = 1,
	output reg			VBLK = 1,
	output reg			HSYN = 1,
	output reg			VSYN = 1
);


reg [8:0] hcnt = 0;
reg [8:0] vcnt = 0;

assign HPOS = hcnt;
assign VPOS = vcnt;

always @(posedge PCLK) begin
	case (hcnt)
		288: begin HBLK <= 1; hcnt <= hcnt+1; end
		311: begin HSYN <= 0; hcnt <= hcnt+1; end
		342: begin HSYN <= 1; hcnt <= 471;    end
		511: begin HBLK <= 0; hcnt <= 0;
			case (vcnt)
				223: begin VBLK <= 1; vcnt <= vcnt+1; end
				226: begin VSYN <= 0; vcnt <= vcnt+1; end
				233: begin VSYN <= 1; vcnt <= 483;	  end
				511: begin VBLK <= 0; vcnt <= 0;		  end
				default: vcnt <= vcnt+1;
			endcase
		end
		default: hcnt <= hcnt+1;
	endcase
	oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
end

endmodule