data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:2: Cannot find include file: helpers.vh\n`include "helpers.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/180413071/nonpipelined/sources/tests,data/full_repos/permissive/180413071/helpers.vh\n             data/full_repos/permissive/180413071/nonpipelined/sources/tests,data/full_repos/permissive/180413071/helpers.vh.v\n             data/full_repos/permissive/180413071/nonpipelined/sources/tests,data/full_repos/permissive/180413071/helpers.vh.sv\n             helpers.vh\n             helpers.vh.v\n             helpers.vh.sv\n             obj_dir/helpers.vh\n             obj_dir/helpers.vh.v\n             obj_dir/helpers.vh.sv\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:3: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:4: Cannot find include file: files.vh\n`include "files.vh" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:11: Define or directive not defined: \'`WORD\'\n    reg  [`WORD-1:0] write_data;\n          ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:12: Define or directive not defined: \'`WORD\'\n    wire [`WORD-1:0] read_data1, read_data2;\n          ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:24: Define or directive not defined: \'`TB_BEGIN\'\n        `TB_BEGIN\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:33: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:33: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:37: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE assert(read_data1 == \'d31) else $error("[0] read_data1 != \'d31");\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:37: syntax error, unexpected assert, expecting IDENTIFIER\n        #`CYCLE assert(read_data1 == \'d31) else $error("[0] read_data1 != \'d31");\n                ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:40: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE assert(read_data1 == \'d20) else $error("[1] read_data1 != \'d20");\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:40: syntax error, unexpected assert, expecting IDENTIFIER\n        #`CYCLE assert(read_data1 == \'d20) else $error("[1] read_data1 != \'d20");\n                ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:43: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE assert(read_data1 == \'d0) else $error("[2] read_data1 != \'d0");\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:43: syntax error, unexpected assert, expecting IDENTIFIER\n        #`CYCLE assert(read_data1 == \'d0) else $error("[2] read_data1 != \'d0");\n                ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:46: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE assert(read_data2 == \'d5) else $error("[3] read_data2 != \'d5");\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:46: syntax error, unexpected assert, expecting IDENTIFIER\n        #`CYCLE assert(read_data2 == \'d5) else $error("[3] read_data2 != \'d5");\n                ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:49: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE assert(read_data2 == \'d17) else $error("[4] read_data2 != \'d17");\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:49: syntax error, unexpected assert, expecting IDENTIFIER\n        #`CYCLE assert(read_data2 == \'d17) else $error("[4] read_data2 != \'d17");\n                ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:52: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE assert(read_data2 == \'d7) else $error("[5] read_data2 != \'d7");\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:52: syntax error, unexpected assert, expecting IDENTIFIER\n        #`CYCLE assert(read_data2 == \'d7) else $error("[5] read_data2 != \'d7");\n                ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:57: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:57: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:62: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE assert(read_data1 == \'d100) else $error("[6] read_data1 != \'d100");\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:62: syntax error, unexpected assert, expecting IDENTIFIER\n        #`CYCLE assert(read_data1 == \'d100) else $error("[6] read_data1 != \'d100");\n                ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:67: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE;\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:67: syntax error, unexpected \';\', expecting IDENTIFIER\n        #`CYCLE;\n               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:72: Define or directive not defined: \'`CYCLE\'\n        #`CYCLE assert(read_data2 == \'d123456789) else $error("[6] read_data2 != \'d123456789");\n         ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:72: syntax error, unexpected assert, expecting IDENTIFIER\n        #`CYCLE assert(read_data2 == \'d123456789) else $error("[6] read_data2 != \'d123456789");\n                ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/tests/register_memory_tb.sv:74: Define or directive not defined: \'`TB_END\'\n        `TB_END\n        ^~~~~~~\n%Error: Exiting due to 29 error(s)\n'
module register_memory_tb;

    wire read_clk, write_clk;
    reg  reg_write;
    reg  [4:0] read_reg1, read_reg2, write_reg;
    reg  [`WORD-1:0] write_data;
    wire [`WORD-1:0] read_data1, read_data2;
    
    oscillator read_clk_gen(read_clk);
    
    delay #(4) write_clk_gen(
        .clk(read_clk),
        .clk_delayed(write_clk)
    );
    
    register_memory UUT(.*);

    initial begin
        `TB_BEGIN
        
        

        reg_write <= 0;
        read_reg1 <= 0;
        read_reg2 <= 0;
        write_reg <= 0;
        write_data <= 0;
        #`CYCLE;
        

        read_reg1 <= 'd31;
        #`CYCLE assert(read_data1 == 'd31) else $error("[0] read_data1 != 'd31");
        
        read_reg1 <= 'd20;
        #`CYCLE assert(read_data1 == 'd20) else $error("[1] read_data1 != 'd20");
        
        read_reg1 <= 'd0;
        #`CYCLE assert(read_data1 == 'd0) else $error("[2] read_data1 != 'd0");
        
        read_reg2 <= 'd5;
        #`CYCLE assert(read_data2 == 'd5) else $error("[3] read_data2 != 'd5");
        
        read_reg2 <= 'd17;
        #`CYCLE assert(read_data2 == 'd17) else $error("[4] read_data2 != 'd17");
        
        read_reg2 <= 'd7;
        #`CYCLE assert(read_data2 == 'd7) else $error("[5] read_data2 != 'd7");
        
        write_reg <= 'd11;
        write_data <= 'd100;
        reg_write <= 1;
        #`CYCLE;
        write_reg <= 'd0;
        write_data <= 'd0;
        reg_write <= 0;
        read_reg1 <= 'd11;
        #`CYCLE assert(read_data1 == 'd100) else $error("[6] read_data1 != 'd100");
        
        write_reg <= 'd1;
        write_data <= 'd123456789;
        reg_write <= 1;
        #`CYCLE;
        write_reg <= 'd0;
        write_data <= 'd0;
        reg_write <= 0;
        read_reg2 <= 'd1;
        #`CYCLE assert(read_data2 == 'd123456789) else $error("[6] read_data2 != 'd123456789");
        
        `TB_END
        $finish;
    end

endmodule
module register_memory_tb;


    wire read_clk, write_clk;
    reg  reg_write;
    reg  [4:0] read_reg1, read_reg2, write_reg;
    reg  [`WORD-1:0] write_data;
    wire [`WORD-1:0] read_data1, read_data2;
    
    oscillator read_clk_gen(read_clk);
    
    delay #(4) write_clk_gen(
        .clk(read_clk),
        .clk_delayed(write_clk)
    );
    
    register_memory UUT(.*);

    initial begin
        `TB_BEGIN
        
        

        reg_write <= 0;
        read_reg1 <= 0;
        read_reg2 <= 0;
        write_reg <= 0;
        write_data <= 0;
        #`CYCLE;
        

        read_reg1 <= 'd31;
        #`CYCLE assert(read_data1 == 'd31) else $error("[0] read_data1 != 'd31");
        
        read_reg1 <= 'd20;
        #`CYCLE assert(read_data1 == 'd20) else $error("[1] read_data1 != 'd20");
        
        read_reg1 <= 'd0;
        #`CYCLE assert(read_data1 == 'd0) else $error("[2] read_data1 != 'd0");
        
        read_reg2 <= 'd5;
        #`CYCLE assert(read_data2 == 'd5) else $error("[3] read_data2 != 'd5");
        
        read_reg2 <= 'd17;
        #`CYCLE assert(read_data2 == 'd17) else $error("[4] read_data2 != 'd17");
        
        read_reg2 <= 'd7;
        #`CYCLE assert(read_data2 == 'd7) else $error("[5] read_data2 != 'd7");
        
        write_reg <= 'd11;
        write_data <= 'd100;
        reg_write <= 1;
        #`CYCLE;
        write_reg <= 'd0;
        write_data <= 'd0;
        reg_write <= 0;
        read_reg1 <= 'd11;
        #`CYCLE assert(read_data1 == 'd100) else $error("[6] read_data1 != 'd100");
        
        write_reg <= 'd1;
        write_data <= 'd123456789;
        reg_write <= 1;
        #`CYCLE;
        write_reg <= 'd0;
        write_data <= 'd0;
        reg_write <= 0;
        read_reg2 <= 'd1;
        #`CYCLE assert(read_data2 == 'd123456789) else $error("[6] read_data2 != 'd123456789");
        
        `TB_END
        $finish;
    end

endmodule