data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB2-Verilog/First.v
1: b"%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB2-Verilog/First.v:42: Cannot find file containing module: 'okHost'\nokHost okHI(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB2-Verilog,data/full_repos/permissive/120539939/okHost\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB2-Verilog,data/full_repos/permissive/120539939/okHost.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB2-Verilog,data/full_repos/permissive/120539939/okHost.sv\n             okHost\n             okHost.v\n             okHost.sv\n             obj_dir/okHost\n             obj_dir/okHost.v\n             obj_dir/okHost.sv\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB2-Verilog/First.v:46: Cannot find file containing module: 'okWireOR'\nokWireOR # (.N(2)) wireOR (.ok2(ok2), .ok2s(ok2x));\n^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB2-Verilog/First.v:48: Cannot find file containing module: 'okWireIn'\nokWireIn     ep00 (.ok1(ok1),                          .ep_addr(8'h00), .ep_dataout(ep00wire));\n^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB2-Verilog/First.v:49: Cannot find file containing module: 'okWireIn'\nokWireIn     ep01 (.ok1(ok1),                          .ep_addr(8'h01), .ep_dataout(ep01wire));\n^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB2-Verilog/First.v:50: Cannot find file containing module: 'okWireIn'\nokWireIn     ep02 (.ok1(ok1),                          .ep_addr(8'h02), .ep_dataout(ep02wire));\n^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB2-Verilog/First.v:52: Cannot find file containing module: 'okWireOut'\nokWireOut    ep20 (.ok1(ok1), .ok2(ok2x[ 0*17 +: 17 ]), .ep_addr(8'h20), .ep_datain(ep20wire));\n^~~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/Simulation-USB2-Verilog/First.v:53: Cannot find file containing module: 'okWireOut'\nokWireOut    ep21 (.ok1(ok1), .ok2(ok2x[ 1*17 +: 17 ]), .ep_addr(8'h21), .ep_datain(ep21wire));\n^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module First(
	input  wire [7:0]  hi_in,
	output wire [1:0]  hi_out,
	inout  wire [15:0] hi_inout,
	output wire [7:0]  led,
	input  wire [3:0]  button
	);


wire        ti_clk;
wire [30:0] ok1;
wire [16:0] ok2;


wire [15:0]  ep00wire;
wire [15:0]  ep01wire;
wire [15:0]  ep02wire;
wire [15:0]  ep20wire;
wire [15:0]  ep21wire;

assign led      = ~ep00wire[7:0];
assign ep20wire = {12'b0000, ~button};
assign ep21wire = ep01wire + ep02wire;


wire [17*2-1:0]  ok2x;
okHost okHI(
  .hi_in(hi_in), .hi_out(hi_out), .hi_inout(hi_inout), .ti_clk(ti_clk),
  .ok1(ok1), .ok2(ok2));

okWireOR # (.N(2)) wireOR (.ok2(ok2), .ok2s(ok2x));

okWireIn     ep00 (.ok1(ok1),                          .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireIn     ep01 (.ok1(ok1),                          .ep_addr(8'h01), .ep_dataout(ep01wire));
okWireIn     ep02 (.ok1(ok1),                          .ep_addr(8'h02), .ep_dataout(ep02wire));

okWireOut    ep20 (.ok1(ok1), .ok2(ok2x[ 0*17 +: 17 ]), .ep_addr(8'h20), .ep_datain(ep20wire));
okWireOut    ep21 (.ok1(ok1), .ok2(ok2x[ 1*17 +: 17 ]), .ep_addr(8'h21), .ep_datain(ep21wire));

endmodule
module First(
	input  wire [7:0]  hi_in,
	output wire [1:0]  hi_out,
	inout  wire [15:0] hi_inout,
	output wire [7:0]  led,
	input  wire [3:0]  button
	);



wire        ti_clk;
wire [30:0] ok1;
wire [16:0] ok2;


wire [15:0]  ep00wire;
wire [15:0]  ep01wire;
wire [15:0]  ep02wire;
wire [15:0]  ep20wire;
wire [15:0]  ep21wire;

assign led      = ~ep00wire[7:0];
assign ep20wire = {12'b0000, ~button};
assign ep21wire = ep01wire + ep02wire;


wire [17*2-1:0]  ok2x;
okHost okHI(
  .hi_in(hi_in), .hi_out(hi_out), .hi_inout(hi_inout), .ti_clk(ti_clk),
  .ok1(ok1), .ok2(ok2));

okWireOR # (.N(2)) wireOR (.ok2(ok2), .ok2s(ok2x));

okWireIn     ep00 (.ok1(ok1),                          .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireIn     ep01 (.ok1(ok1),                          .ep_addr(8'h01), .ep_dataout(ep01wire));
okWireIn     ep02 (.ok1(ok1),                          .ep_addr(8'h02), .ep_dataout(ep02wire));

okWireOut    ep20 (.ok1(ok1), .ok2(ok2x[ 0*17 +: 17 ]), .ep_addr(8'h20), .ep_datain(ep20wire));
okWireOut    ep21 (.ok1(ok1), .ok2(ok2x[ 1*17 +: 17 ]), .ep_addr(8'h21), .ep_datain(ep21wire));

endmodule