data/full_repos/permissive/107007139/Project/triangle_node_generator.v
data/verilator_xmls/f41087f9-0659-4fc6-b225-5df25a87bdcd.xml
module triangle_node_generator(
    input clk,
    input [4:0] select,
    output reg [11:0] out
    );
    

    parameter doi_inc = 23;
    parameter re_inc = 21;
    parameter mi_inc = 18;
    parameter fa_inc = 17;
    parameter so_inc = 16;
    

    parameter max_out = 4095;    
    
    wire [7:0] increment_until;
    

    assign increment_until = select[0] ? doi_inc
                                       : (select[1] ? re_inc
                                                    : (select[2] ? mi_inc
                                                                 : (select[3] ? fa_inc : so_inc)));
    

    reg [7:0] increment_count = 0;
    

    reg increase_or_decrease = 1;
    
    initial begin
        out = 1;
    end
    
    always @(posedge clk) begin

        increment_count = (increment_count == increment_until) ? 0 : increment_count + 1;
        

        increase_or_decrease = (out == 0) ? 1
                                          : ((out == max_out) ? 0 : increase_or_decrease);
        

        if (select == 0) begin
            out = {12{1'b0}};
        end else begin
            out = (increment_count == 0) ? (increase_or_decrease ? out + 1 : out - 1)
                                         : out;
        end
    end
endmodule
module triangle_node_generator(
    input clk,
    input [4:0] select,
    output reg [11:0] out
    );

    

    parameter doi_inc = 23;
    parameter re_inc = 21;
    parameter mi_inc = 18;
    parameter fa_inc = 17;
    parameter so_inc = 16;
    

    parameter max_out = 4095;    
    
    wire [7:0] increment_until;
    

    assign increment_until = select[0] ? doi_inc
                                       : (select[1] ? re_inc
                                                    : (select[2] ? mi_inc
                                                                 : (select[3] ? fa_inc : so_inc)));
    

    reg [7:0] increment_count = 0;
    

    reg increase_or_decrease = 1;
    
    initial begin
        out = 1;
    end
    
    always @(posedge clk) begin

        increment_count = (increment_count == increment_until) ? 0 : increment_count + 1;
        

        increase_or_decrease = (out == 0) ? 1
                                          : ((out == max_out) ? 0 : increase_or_decrease);
        

        if (select == 0) begin
            out = {12{1'b0}};
        end else begin
            out = (increment_count == 0) ? (increase_or_decrease ? out + 1 : out - 1)
                                         : out;
        end
    end
endmodule