data/full_repos/permissive/143278/ivltests/br974b.v
 line:20: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br974b.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #0 $display("%b %b", i, o);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dut(i, o);

input  logic [3:0] i;
output logic [3:0] o;

always @* o = i;

endmodule
module dut(i, o);


input  logic [3:0] i;
output logic [3:0] o;

always @* o = i;

endmodule