data/full_repos/permissive/160924877/evaluate/e203/core/e203_ifu_ift2icb.v
1: b'%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_ifu_ift2icb.v:74: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160924877/evaluate/e203/core,data/full_repos/permissive/160924877/e203_defines.v\n             data/full_repos/permissive/160924877/evaluate/e203/core,data/full_repos/permissive/160924877/e203_defines.v.v\n             data/full_repos/permissive/160924877/evaluate/e203/core,data/full_repos/permissive/160924877/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_ifu_ift2icb.v:90: Define or directive not defined: \'`E203_PC_SIZE\'\n input  [`E203_PC_SIZE-1:0] ifu_req_pc,  \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_ifu_ift2icb.v:93: Define or directive not defined: \'`E203_PC_SIZE\'\n input  [`E203_PC_SIZE-1:0] ifu_req_last_pc,  \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_ifu_ift2icb.v:166: syntax error, unexpected \'!\'\n  !!! ERROR: There is no ITCM and no System interface, where to fetch the instructions? must be wrong configuration.\n  ^\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_ifu_ift2icb.v:183: Define or directive not defined: \'`E203_INSTR_SIZE\'\n wire [`E203_INSTR_SIZE-1:0] i_ifu_rsp_instr;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_ifu_ift2icb.v:184: Define or directive not defined: \'`E203_INSTR_SIZE\'\n wire [`E203_INSTR_SIZE+1-1:0]ifu_rsp_bypbuf_i_data;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_ifu_ift2icb.v:185: Define or directive not defined: \'`E203_INSTR_SIZE\'\n wire [`E203_INSTR_SIZE+1-1:0]ifu_rsp_bypbuf_o_data;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_ifu_ift2icb.v:198: Define or directive not defined: \'`E203_INSTR_SIZE\'\n  .DW(`E203_INSTR_SIZE+1) \n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/evaluate/e203/core/e203_ifu_ift2icb.v:425: Define or directive not defined: \'`E203_PC_SIZE\'\n wire [`E203_PC_SIZE-1:0] ifu_icb_cmd_addr;\n       ^~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module e203_ifu_ift2icb(


	input  itcm_nohold,




	input  ifu_req_valid,
	output ifu_req_ready,




	input  [`E203_PC_SIZE-1:0] ifu_req_pc,
	input  ifu_req_seq,
	input  ifu_req_seq_rv32,
	input  [`E203_PC_SIZE-1:0] ifu_req_last_pc,

														 

	output ifu_rsp_valid,
	input  ifu_rsp_ready,
	output ifu_rsp_err,





	output [32-1:0] ifu_rsp_instr,

	`ifdef E203_HAS_ITCM



	input [`E203_ADDR_SIZE-1:0] itcm_region_indic,


	output ifu2itcm_icb_cmd_valid,
	input  ifu2itcm_icb_cmd_ready,


	output [`E203_ITCM_ADDR_WIDTH-1:0]   ifu2itcm_icb_cmd_addr,


	input  ifu2itcm_icb_rsp_valid,
	output ifu2itcm_icb_rsp_ready,
	input  ifu2itcm_icb_rsp_err,

	input  [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata, 

	`endif


	`ifdef E203_HAS_MEM_ITF




	output ifu2biu_icb_cmd_valid,
	input  ifu2biu_icb_cmd_ready,


	output [`E203_ADDR_SIZE-1:0]   ifu2biu_icb_cmd_addr,


	input  ifu2biu_icb_rsp_valid,
	output ifu2biu_icb_rsp_ready,
	input  ifu2biu_icb_rsp_err,

	input  [`E203_SYSMEM_DATA_WIDTH-1:0] ifu2biu_icb_rsp_rdata, 
	

	`endif





	`ifdef E203_HAS_ITCM
	input  ifu2itcm_holdup,

	`endif

	input  clk,
	input  rst_n
	);

`ifndef E203_HAS_ITCM
	`ifndef E203_HAS_MEM_ITF
		!!! ERROR: There is no ITCM and no System interface, where to fetch the instructions? must be wrong configuration.
	`endif
`endif











	wire i_ifu_rsp_valid;
	wire i_ifu_rsp_ready;
	wire i_ifu_rsp_err;
	wire [`E203_INSTR_SIZE-1:0] i_ifu_rsp_instr;
	wire [`E203_INSTR_SIZE+1-1:0]ifu_rsp_bypbuf_i_data;
	wire [`E203_INSTR_SIZE+1-1:0]ifu_rsp_bypbuf_o_data;

	assign ifu_rsp_bypbuf_i_data = {
													i_ifu_rsp_err,
													i_ifu_rsp_instr
													};

	assign {ifu_rsp_err,
					ifu_rsp_instr
													} = ifu_rsp_bypbuf_o_data;

	sirv_gnrl_bypbuf # (
		.DP(1),
		.DW(`E203_INSTR_SIZE+1) 
	) u_e203_ifetch_rsp_bypbuf(
			.i_vld   (i_ifu_rsp_valid),
			.i_rdy   (i_ifu_rsp_ready),

			.o_vld   (ifu_rsp_valid),
			.o_rdy   (ifu_rsp_ready),

			.i_dat   (ifu_rsp_bypbuf_i_data),
			.o_dat   (ifu_rsp_bypbuf_o_data),
	
			.clk     (clk  ),
			.rst_n   (rst_n)
	);





















































































































 

















	
	wire ifu_req_hsked = ifu_req_valid & ifu_req_ready;
	wire i_ifu_rsp_hsked = i_ifu_rsp_valid & i_ifu_rsp_ready;
	wire ifu_icb_cmd_valid;
	wire ifu_icb_cmd_ready;
	wire ifu_icb_cmd_hsked = ifu_icb_cmd_valid & ifu_icb_cmd_ready;
	wire ifu_icb_rsp_valid;
	wire ifu_icb_rsp_ready;
	wire ifu_icb_rsp_hsked = ifu_icb_rsp_valid & ifu_icb_rsp_ready;








	localparam ICB_STATE_WIDTH  = 1;

	localparam ICB_STATE_IDLE = 1'd0;

	localparam ICB_STATE_1ST  = 1'd1;

	
	wire [ICB_STATE_WIDTH-1:0] icb_state_nxt;
	wire [ICB_STATE_WIDTH-1:0] icb_state_r;
	wire icb_state_ena;
	wire [ICB_STATE_WIDTH-1:0] state_idle_nxt   ;
	wire [ICB_STATE_WIDTH-1:0] state_1st_nxt    ;

	wire state_idle_exit_ena     ;
	wire state_1st_exit_ena      ;


	wire icb_sta_is_idle    = (icb_state_r == ICB_STATE_IDLE   );
	wire icb_sta_is_1st     = (icb_state_r == ICB_STATE_1ST    );



	assign state_idle_exit_ena = icb_sta_is_idle & ifu_req_hsked;
	assign state_idle_nxt      = ICB_STATE_1ST;



	assign state_1st_exit_ena  = icb_sta_is_1st & (i_ifu_rsp_hsked);
	assign state_1st_nxt     = 
								(




										ifu_req_hsked  ?  ICB_STATE_1ST 
																		: ICB_STATE_IDLE 
								) ;






	assign icb_state_ena = 
						state_idle_exit_ena | state_1st_exit_ena  ;


	assign icb_state_nxt = 
							({ICB_STATE_WIDTH{state_idle_exit_ena   }} & state_idle_nxt   )
						| ({ICB_STATE_WIDTH{state_1st_exit_ena    }} & state_1st_nxt    )
							;

	sirv_gnrl_dfflr #(ICB_STATE_WIDTH) icb_state_dfflr (icb_state_ena, icb_state_nxt, icb_state_r, clk, rst_n);







	wire [`E203_PC_SIZE-1:0] ifu_icb_cmd_addr;
	`ifdef E203_HAS_ITCM
	wire ifu_icb_cmd2itcm;
	wire icb_cmd2itcm_r;
	sirv_gnrl_dfflr #(1) icb2itcm_dfflr(ifu_icb_cmd_hsked, ifu_icb_cmd2itcm, icb_cmd2itcm_r, clk, rst_n);
	`endif
	`ifdef E203_HAS_MEM_ITF
	wire ifu_icb_cmd2biu ;
	wire icb_cmd2biu_r;
	sirv_gnrl_dfflr #(1) icb2mem_dfflr (ifu_icb_cmd_hsked, ifu_icb_cmd2biu , icb_cmd2biu_r,  clk, rst_n);
	`endif

	













	`ifdef E203_HAS_ITCM
	wire[31:0] ifu2itcm_icb_rsp_instr = 
										ifu2itcm_icb_rsp_rdata;
		 
	`endif

	`ifdef E203_HAS_MEM_ITF
	wire[31:0] ifu2biu_icb_rsp_instr = 
										ifu2biu_icb_rsp_rdata;  
	`endif

	wire [32-1:0] ifu_icb_rsp_instr = 32'b0
										 `ifdef E203_HAS_ITCM
											 | ({32{icb_cmd2itcm_r}} & ifu2itcm_icb_rsp_instr)
										 `endif
										 `ifdef E203_HAS_MEM_ITF
											 | ({32{icb_cmd2biu_r}}  & ifu2biu_icb_rsp_instr)
										 `endif
												;

	wire ifu_icb_rsp_err = 1'b0
										 `ifdef E203_HAS_ITCM
											 | (icb_cmd2itcm_r & ifu2itcm_icb_rsp_err)
										 `endif
										 `ifdef E203_HAS_MEM_ITF
											 | (icb_cmd2biu_r  & ifu2biu_icb_rsp_err)
										 `endif
												;

	assign i_ifu_rsp_instr = (ifu_icb_rsp_instr);
	assign i_ifu_rsp_err = (ifu_icb_rsp_err);




							








	wire ifu_icb_rsp2ir_ready;

	wire ifu_icb_rsp2ir_valid = ifu_icb_rsp_valid;
	assign ifu_icb_rsp_ready  = ifu_icb_rsp2ir_ready;


	assign i_ifu_rsp_valid = ifu_icb_rsp2ir_valid;
	assign ifu_icb_rsp2ir_ready = i_ifu_rsp_ready;








	assign ifu_icb_rsp_valid = 1'b0
										 `ifdef E203_HAS_ITCM
											 | (icb_cmd2itcm_r & ifu2itcm_icb_rsp_valid)
										 `endif
										 `ifdef E203_HAS_MEM_ITF
											 | (icb_cmd2biu_r  & ifu2biu_icb_rsp_valid)
										 `endif
												;
 





















	wire ifu_req_valid_pos;
	assign ifu_icb_cmd_valid = 
									 (ifu_req_valid_pos)
								 ;
										 
	assign ifu_icb_cmd_addr = ( ifu_req_pc);








	wire ifu_req_ready_condi = 
								(
										icb_sta_is_idle 
									| ( icb_sta_is_1st & i_ifu_rsp_hsked)
									);
	assign ifu_req_ready     = ifu_icb_cmd_ready & ifu_req_ready_condi; 
	assign ifu_req_valid_pos = ifu_req_valid     & ifu_req_ready_condi;







	`ifdef E203_HAS_ITCM
	assign ifu_icb_cmd2itcm = (ifu_icb_cmd_addr[`E203_ITCM_BASE_REGION] == itcm_region_indic[`E203_ITCM_BASE_REGION]);

	assign ifu2itcm_icb_cmd_valid = ifu_icb_cmd_valid & ifu_icb_cmd2itcm;
	assign ifu2itcm_icb_cmd_addr = ifu_icb_cmd_addr[`E203_ITCM_ADDR_WIDTH-1:0];

	assign ifu2itcm_icb_rsp_ready = ifu_icb_rsp_ready;
	`endif

	`ifdef E203_HAS_MEM_ITF
	assign ifu_icb_cmd2biu = 1'b1
						`ifdef E203_HAS_ITCM
							& ~(ifu_icb_cmd2itcm)
						`endif
							;
	wire ifu2biu_icb_cmd_valid_pre  = ifu_icb_cmd_valid & ifu_icb_cmd2biu;
	wire [`E203_ADDR_SIZE-1:0]   ifu2biu_icb_cmd_addr_pre = ifu_icb_cmd_addr[`E203_ADDR_SIZE-1:0];

	assign ifu2biu_icb_rsp_ready = ifu_icb_rsp_ready;

	wire ifu2biu_icb_cmd_ready_pre;
	`endif

	assign ifu_icb_cmd_ready = 1'b0
		`ifdef E203_HAS_ITCM
				| (ifu_icb_cmd2itcm & ifu2itcm_icb_cmd_ready) 
		`endif
		`ifdef E203_HAS_MEM_ITF
				| (ifu_icb_cmd2biu  & ifu2biu_icb_cmd_ready_pre ) 
		`endif
				;

		`ifdef E203_HAS_MEM_ITF 

		 assign ifu2biu_icb_cmd_addr      = ifu2biu_icb_cmd_addr_pre;
		 assign ifu2biu_icb_cmd_valid     = ifu2biu_icb_cmd_valid_pre;
		 assign ifu2biu_icb_cmd_ready_pre = ifu2biu_icb_cmd_ready;
		`endif


endmodule
module e203_ifu_ift2icb(


	input  itcm_nohold,




	input  ifu_req_valid,
	output ifu_req_ready,




	input  [`E203_PC_SIZE-1:0] ifu_req_pc,
	input  ifu_req_seq,
	input  ifu_req_seq_rv32,
	input  [`E203_PC_SIZE-1:0] ifu_req_last_pc,

														 

	output ifu_rsp_valid,
	input  ifu_rsp_ready,
	output ifu_rsp_err,





	output [32-1:0] ifu_rsp_instr,

	`ifdef E203_HAS_ITCM



	input [`E203_ADDR_SIZE-1:0] itcm_region_indic,


	output ifu2itcm_icb_cmd_valid,
	input  ifu2itcm_icb_cmd_ready,


	output [`E203_ITCM_ADDR_WIDTH-1:0]   ifu2itcm_icb_cmd_addr,


	input  ifu2itcm_icb_rsp_valid,
	output ifu2itcm_icb_rsp_ready,
	input  ifu2itcm_icb_rsp_err,

	input  [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata, 

	`endif


	`ifdef E203_HAS_MEM_ITF




	output ifu2biu_icb_cmd_valid,
	input  ifu2biu_icb_cmd_ready,


	output [`E203_ADDR_SIZE-1:0]   ifu2biu_icb_cmd_addr,


	input  ifu2biu_icb_rsp_valid,
	output ifu2biu_icb_rsp_ready,
	input  ifu2biu_icb_rsp_err,

	input  [`E203_SYSMEM_DATA_WIDTH-1:0] ifu2biu_icb_rsp_rdata, 
	

	`endif





	`ifdef E203_HAS_ITCM
	input  ifu2itcm_holdup,

	`endif

	input  clk,
	input  rst_n
	);


`ifndef E203_HAS_ITCM
	`ifndef E203_HAS_MEM_ITF
		!!! ERROR: There is no ITCM and no System interface, where to fetch the instructions? must be wrong configuration.
	`endif
`endif











	wire i_ifu_rsp_valid;
	wire i_ifu_rsp_ready;
	wire i_ifu_rsp_err;
	wire [`E203_INSTR_SIZE-1:0] i_ifu_rsp_instr;
	wire [`E203_INSTR_SIZE+1-1:0]ifu_rsp_bypbuf_i_data;
	wire [`E203_INSTR_SIZE+1-1:0]ifu_rsp_bypbuf_o_data;

	assign ifu_rsp_bypbuf_i_data = {
													i_ifu_rsp_err,
													i_ifu_rsp_instr
													};

	assign {ifu_rsp_err,
					ifu_rsp_instr
													} = ifu_rsp_bypbuf_o_data;

	sirv_gnrl_bypbuf # (
		.DP(1),
		.DW(`E203_INSTR_SIZE+1) 
	) u_e203_ifetch_rsp_bypbuf(
			.i_vld   (i_ifu_rsp_valid),
			.i_rdy   (i_ifu_rsp_ready),

			.o_vld   (ifu_rsp_valid),
			.o_rdy   (ifu_rsp_ready),

			.i_dat   (ifu_rsp_bypbuf_i_data),
			.o_dat   (ifu_rsp_bypbuf_o_data),
	
			.clk     (clk  ),
			.rst_n   (rst_n)
	);





















































































































 

















	
	wire ifu_req_hsked = ifu_req_valid & ifu_req_ready;
	wire i_ifu_rsp_hsked = i_ifu_rsp_valid & i_ifu_rsp_ready;
	wire ifu_icb_cmd_valid;
	wire ifu_icb_cmd_ready;
	wire ifu_icb_cmd_hsked = ifu_icb_cmd_valid & ifu_icb_cmd_ready;
	wire ifu_icb_rsp_valid;
	wire ifu_icb_rsp_ready;
	wire ifu_icb_rsp_hsked = ifu_icb_rsp_valid & ifu_icb_rsp_ready;








	localparam ICB_STATE_WIDTH  = 1;

	localparam ICB_STATE_IDLE = 1'd0;

	localparam ICB_STATE_1ST  = 1'd1;

	
	wire [ICB_STATE_WIDTH-1:0] icb_state_nxt;
	wire [ICB_STATE_WIDTH-1:0] icb_state_r;
	wire icb_state_ena;
	wire [ICB_STATE_WIDTH-1:0] state_idle_nxt   ;
	wire [ICB_STATE_WIDTH-1:0] state_1st_nxt    ;

	wire state_idle_exit_ena     ;
	wire state_1st_exit_ena      ;


	wire icb_sta_is_idle    = (icb_state_r == ICB_STATE_IDLE   );
	wire icb_sta_is_1st     = (icb_state_r == ICB_STATE_1ST    );



	assign state_idle_exit_ena = icb_sta_is_idle & ifu_req_hsked;
	assign state_idle_nxt      = ICB_STATE_1ST;



	assign state_1st_exit_ena  = icb_sta_is_1st & (i_ifu_rsp_hsked);
	assign state_1st_nxt     = 
								(




										ifu_req_hsked  ?  ICB_STATE_1ST 
																		: ICB_STATE_IDLE 
								) ;






	assign icb_state_ena = 
						state_idle_exit_ena | state_1st_exit_ena  ;


	assign icb_state_nxt = 
							({ICB_STATE_WIDTH{state_idle_exit_ena   }} & state_idle_nxt   )
						| ({ICB_STATE_WIDTH{state_1st_exit_ena    }} & state_1st_nxt    )
							;

	sirv_gnrl_dfflr #(ICB_STATE_WIDTH) icb_state_dfflr (icb_state_ena, icb_state_nxt, icb_state_r, clk, rst_n);







	wire [`E203_PC_SIZE-1:0] ifu_icb_cmd_addr;
	`ifdef E203_HAS_ITCM
	wire ifu_icb_cmd2itcm;
	wire icb_cmd2itcm_r;
	sirv_gnrl_dfflr #(1) icb2itcm_dfflr(ifu_icb_cmd_hsked, ifu_icb_cmd2itcm, icb_cmd2itcm_r, clk, rst_n);
	`endif
	`ifdef E203_HAS_MEM_ITF
	wire ifu_icb_cmd2biu ;
	wire icb_cmd2biu_r;
	sirv_gnrl_dfflr #(1) icb2mem_dfflr (ifu_icb_cmd_hsked, ifu_icb_cmd2biu , icb_cmd2biu_r,  clk, rst_n);
	`endif

	













	`ifdef E203_HAS_ITCM
	wire[31:0] ifu2itcm_icb_rsp_instr = 
										ifu2itcm_icb_rsp_rdata;
		 
	`endif

	`ifdef E203_HAS_MEM_ITF
	wire[31:0] ifu2biu_icb_rsp_instr = 
										ifu2biu_icb_rsp_rdata;  
	`endif

	wire [32-1:0] ifu_icb_rsp_instr = 32'b0
										 `ifdef E203_HAS_ITCM
											 | ({32{icb_cmd2itcm_r}} & ifu2itcm_icb_rsp_instr)
										 `endif
										 `ifdef E203_HAS_MEM_ITF
											 | ({32{icb_cmd2biu_r}}  & ifu2biu_icb_rsp_instr)
										 `endif
												;

	wire ifu_icb_rsp_err = 1'b0
										 `ifdef E203_HAS_ITCM
											 | (icb_cmd2itcm_r & ifu2itcm_icb_rsp_err)
										 `endif
										 `ifdef E203_HAS_MEM_ITF
											 | (icb_cmd2biu_r  & ifu2biu_icb_rsp_err)
										 `endif
												;

	assign i_ifu_rsp_instr = (ifu_icb_rsp_instr);
	assign i_ifu_rsp_err = (ifu_icb_rsp_err);




							








	wire ifu_icb_rsp2ir_ready;

	wire ifu_icb_rsp2ir_valid = ifu_icb_rsp_valid;
	assign ifu_icb_rsp_ready  = ifu_icb_rsp2ir_ready;


	assign i_ifu_rsp_valid = ifu_icb_rsp2ir_valid;
	assign ifu_icb_rsp2ir_ready = i_ifu_rsp_ready;








	assign ifu_icb_rsp_valid = 1'b0
										 `ifdef E203_HAS_ITCM
											 | (icb_cmd2itcm_r & ifu2itcm_icb_rsp_valid)
										 `endif
										 `ifdef E203_HAS_MEM_ITF
											 | (icb_cmd2biu_r  & ifu2biu_icb_rsp_valid)
										 `endif
												;
 





















	wire ifu_req_valid_pos;
	assign ifu_icb_cmd_valid = 
									 (ifu_req_valid_pos)
								 ;
										 
	assign ifu_icb_cmd_addr = ( ifu_req_pc);








	wire ifu_req_ready_condi = 
								(
										icb_sta_is_idle 
									| ( icb_sta_is_1st & i_ifu_rsp_hsked)
									);
	assign ifu_req_ready     = ifu_icb_cmd_ready & ifu_req_ready_condi; 
	assign ifu_req_valid_pos = ifu_req_valid     & ifu_req_ready_condi;







	`ifdef E203_HAS_ITCM
	assign ifu_icb_cmd2itcm = (ifu_icb_cmd_addr[`E203_ITCM_BASE_REGION] == itcm_region_indic[`E203_ITCM_BASE_REGION]);

	assign ifu2itcm_icb_cmd_valid = ifu_icb_cmd_valid & ifu_icb_cmd2itcm;
	assign ifu2itcm_icb_cmd_addr = ifu_icb_cmd_addr[`E203_ITCM_ADDR_WIDTH-1:0];

	assign ifu2itcm_icb_rsp_ready = ifu_icb_rsp_ready;
	`endif

	`ifdef E203_HAS_MEM_ITF
	assign ifu_icb_cmd2biu = 1'b1
						`ifdef E203_HAS_ITCM
							& ~(ifu_icb_cmd2itcm)
						`endif
							;
	wire ifu2biu_icb_cmd_valid_pre  = ifu_icb_cmd_valid & ifu_icb_cmd2biu;
	wire [`E203_ADDR_SIZE-1:0]   ifu2biu_icb_cmd_addr_pre = ifu_icb_cmd_addr[`E203_ADDR_SIZE-1:0];

	assign ifu2biu_icb_rsp_ready = ifu_icb_rsp_ready;

	wire ifu2biu_icb_cmd_ready_pre;
	`endif

	assign ifu_icb_cmd_ready = 1'b0
		`ifdef E203_HAS_ITCM
				| (ifu_icb_cmd2itcm & ifu2itcm_icb_cmd_ready) 
		`endif
		`ifdef E203_HAS_MEM_ITF
				| (ifu_icb_cmd2biu  & ifu2biu_icb_cmd_ready_pre ) 
		`endif
				;

		`ifdef E203_HAS_MEM_ITF 

		 assign ifu2biu_icb_cmd_addr      = ifu2biu_icb_cmd_addr_pre;
		 assign ifu2biu_icb_cmd_valid     = ifu2biu_icb_cmd_valid_pre;
		 assign ifu2biu_icb_cmd_ready_pre = ifu2biu_icb_cmd_ready;
		`endif


endmodule