data/full_repos/permissive/159970601/picosoc/attosoc.v
 line:34 column:39: Illegal character "'"
1: b'%Warning-MULTITOP: data/full_repos/permissive/159970601/picosoc/attosoc.v:104: Multiple top level modules\n                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                             : ... Top module \'attosoc\'\nmodule attosoc (\n       ^~~~~~~\n                                                                             : ... Top module \'picosoc_regs\'\nmodule picosoc_regs (\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/159970601/picosoc/attosoc.v:75: Cannot find file containing module: \'picorv32\'\n picorv32 #(\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159970601/picosoc,data/full_repos/permissive/159970601/picorv32\n             data/full_repos/permissive/159970601/picosoc,data/full_repos/permissive/159970601/picorv32.v\n             data/full_repos/permissive/159970601/picosoc,data/full_repos/permissive/159970601/picorv32.sv\n             picorv32\n             picorv32.v\n             picorv32.sv\n             obj_dir/picorv32\n             obj_dir/picorv32.v\n             obj_dir/picorv32.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module picosoc_regs (
	input clk, wen,
	input [5:0] waddr,
	input [5:0] raddr1,
	input [5:0] raddr2,
	input [31:0] wdata,
	output [31:0] rdata1,
	output [31:0] rdata2
);
	reg [31:0] regs [0:31];

	always @(posedge clk)
		if (wen) regs[waddr[4:0]] <= wdata;

	assign rdata1 = regs[raddr1[4:0]];
	assign rdata2 = regs[raddr2[4:0]];
endmodule
module picosoc_regs (
	input clk, wen,
	input [5:0] waddr,
	input [5:0] raddr1,
	input [5:0] raddr2,
	input [31:0] wdata,
	output [31:0] rdata1,
	output [31:0] rdata2
);

	reg [31:0] regs [0:31];

	always @(posedge clk)
		if (wen) regs[waddr[4:0]] <= wdata;

	assign rdata1 = regs[raddr1[4:0]];
	assign rdata2 = regs[raddr2[4:0]];
endmodule