data/full_repos/permissive/193419875/src/IFID.v
data/verilator_xmls/969903cf-b8eb-4e5a-9da1-1df5248bdbad.xml
module IFID
(
	input CLOCK,
	input IFID_Write,
	input [63:0] programCounter_in,
	input [31:0] CPUInstruction_in,
	output reg [63:0] programCounter_out,
	output reg [31:0] CPUInstruction_out
);

	always @(posedge CLOCK) begin
		if(IFID_Write) begin
			programCounter_out <= programCounter_in;
			CPUInstruction_out <= CPUInstruction_in;
		end
	end
endmodule
module IFID
(
	input CLOCK,
	input IFID_Write,
	input [63:0] programCounter_in,
	input [31:0] CPUInstruction_in,
	output reg [63:0] programCounter_out,
	output reg [31:0] CPUInstruction_out
);


	always @(posedge CLOCK) begin
		if(IFID_Write) begin
			programCounter_out <= programCounter_in;
			CPUInstruction_out <= CPUInstruction_in;
		end
	end
endmodule