data/full_repos/permissive/117026779/src/ServoTop.v
1: b'%Warning-WIDTH: data/full_repos/permissive/117026779/src/ServoTop.v:36: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_reg\' generates 16 bits.\n                                                                      : ... In instance ServoTop\nassign data = (cs) ? data_reg : 0;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/117026779/src/ServoTop.v:38: Cannot find file containing module: \'ServoController\'\nServoController servo(\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/ServoController\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/ServoController.v\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/ServoController.sv\n             ServoController\n             ServoController.v\n             ServoController.sv\n             obj_dir/ServoController\n             obj_dir/ServoController.v\n             obj_dir/ServoController.sv\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/ServoTop.v:57: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'init\' generates 3 bits.\n                                                                      : ... In instance ServoTop\n  addr = init;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/ServoTop.v:60: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1f4\' generates 32 bits.\n                                                                      : ... In instance ServoTop\n    data_reg = 32\'d500;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/ServoTop.v:63: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3e8\' generates 32 bits.\n                                                                      : ... In instance ServoTop\n    data_reg = 32\'d1000;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/ServoTop.v:66: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h5dc\' generates 32 bits.\n                                                                      : ... In instance ServoTop\n    data_reg = 32\'d1500;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/ServoTop.v:69: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h7d0\' generates 32 bits.\n                                                                      : ... In instance ServoTop\n    data_reg = 32\'d2000;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/ServoTop.v:58: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'addr\' generates 2 bits.\n                                                                      : ... In instance ServoTop\n  case(addr)\n  ^~~~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n'
module ServoTop(
	input wire clk,
	input wire rst,
	output wire [3:0] signal
);

wire [31:0] data;

reg cs;
reg [1:0] addr;
reg [15:0] data_reg;

assign data = (cs) ? data_reg : 0;

ServoController servo(
    .clk(clk),
    .rst(rst),
    .cs(cs),
    .addr(addr[1:0]),
    .data(data[15:0]),
    .signal(signal)
);

reg [2:0] init;

always @(posedge clk or posedge rst) begin
	if (rst)
	begin
		init = 0;
		cs = 1;
	end
	else if(init < 3'b100)
	begin
		addr = init;
		case(addr)
			3'b000: begin
				data_reg = 32'd500;
			end
			3'b001: begin
				data_reg = 32'd1000;
			end
			3'b010: begin
				data_reg = 32'd1500;
			end
			3'b011: begin
				data_reg = 32'd2000;
			end
		endcase
		init = init + 1;
	end
	else begin
		cs = 0;
	end
end

endmodule
module ServoTop(
	input wire clk,
	input wire rst,
	output wire [3:0] signal
);


wire [31:0] data;

reg cs;
reg [1:0] addr;
reg [15:0] data_reg;

assign data = (cs) ? data_reg : 0;

ServoController servo(
    .clk(clk),
    .rst(rst),
    .cs(cs),
    .addr(addr[1:0]),
    .data(data[15:0]),
    .signal(signal)
);

reg [2:0] init;

always @(posedge clk or posedge rst) begin
	if (rst)
	begin
		init = 0;
		cs = 1;
	end
	else if(init < 3'b100)
	begin
		addr = init;
		case(addr)
			3'b000: begin
				data_reg = 32'd500;
			end
			3'b001: begin
				data_reg = 32'd1000;
			end
			3'b010: begin
				data_reg = 32'd1500;
			end
			3'b011: begin
				data_reg = 32'd2000;
			end
		endcase
		init = init + 1;
	end
	else begin
		cs = 0;
	end
end

endmodule