data/full_repos/permissive/132304455/src/n_bit_dffe.v
data/verilator_xmls/c6c68d99-9839-48af-aaff-9ed013492c04.xml
module n_bit_dffe(q, d, clk, enable, reset);
   
    parameter
        width = 1,
        reset_value = 0;

    output reg [(width - 1):0] q;
    input      [(width - 1):0]  d;
    input      clk, enable, reset;


    always@(posedge clk or posedge reset)
    begin
        if (reset == 1'b1)
        begin
            q <= reset_value;
        end
        else if (enable == 1'b1)
        begin
            q <= d;
        end
    end
endmodule
module n_bit_dffe(q, d, clk, enable, reset);

   
    parameter
        width = 1,
        reset_value = 0;

    output reg [(width - 1):0] q;
    input      [(width - 1):0]  d;
    input      clk, enable, reset;


    always@(posedge clk or posedge reset)
    begin
        if (reset == 1'b1)
        begin
            q <= reset_value;
        end
        else if (enable == 1'b1)
        begin
            q <= d;
        end
    end
endmodule