data/full_repos/permissive/147265957/src/btnclkdiv.v
data/verilator_xmls/2e7c4caf-ecf7-477f-b833-7eecfce8499d.xml
module btnclkdiv(
    clk,divclk
    );
    input clk;
    output reg divclk;
    parameter interval = 1_000_000;
    reg [31:0] cnt;
    initial cnt = 0;
    initial divclk = 0;
    always @(posedge clk) begin
      cnt = cnt + 1;
      if (cnt == interval/2 - 1 ) begin
        divclk = ~divclk;
        cnt = 0;
      end
    end
endmodule
module btnclkdiv(
    clk,divclk
    );

    input clk;
    output reg divclk;
    parameter interval = 1_000_000;
    reg [31:0] cnt;
    initial cnt = 0;
    initial divclk = 0;
    always @(posedge clk) begin
      cnt = cnt + 1;
      if (cnt == interval/2 - 1 ) begin
        divclk = ~divclk;
        cnt = 0;
      end
    end
endmodule