data/full_repos/permissive/146246005/RISC-y Processor/RISCY_CPU.sv
 line:3: before: "package"
1: b'%Error: Cannot find file containing module: Processor,data/full_repos/permissive/146246005\n        ... Looked in:\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.v\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.sv\n             Processor,data/full_repos/permissive/146246005\n             Processor,data/full_repos/permissive/146246005.v\n             Processor,data/full_repos/permissive/146246005.sv\n             obj_dir/Processor,data/full_repos/permissive/146246005\n             obj_dir/Processor,data/full_repos/permissive/146246005.v\n             obj_dir/Processor,data/full_repos/permissive/146246005.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/RISC-y\n%Error: Cannot find file containing module: Processor/RISCY_CPU.sv\n%Error: Exiting due to 3 error(s)\n'
module phaser(CLOCK, RESET, EN, PHASE);
  import cycle_package::*;
  input CLOCK, RESET, EN;
  output CYCLE PHASE;
  
  always @(posedge CLOCK, negedge RESET) begin
    if(!RESET)
      PHASE <= PHASE.first();
    else if(!EN)
      PHASE <= PHASE.next();
    else
      PHASE <= PHASE;
  end
endmodule
module phaser(CLOCK, RESET, EN, PHASE);

  import cycle_package::*;
  input CLOCK, RESET, EN;
  output CYCLE PHASE;
  
  always @(posedge CLOCK, negedge RESET) begin
    if(!RESET)
      PHASE <= PHASE.first();
    else if(!EN)
      PHASE <= PHASE.next();
    else
      PHASE <= PHASE;
  end
endmodule