data/full_repos/permissive/179980995/FPU/workingv3.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/179980995/FPU/workingv3.v:35: Signal definition not found, creating implicitly: \'a_sign\'\n                                                                          : ... Suggested alternative: \'o_sign\'\n assign a_sign = A[31];\n        ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/179980995/FPU/workingv3.v:39: Signal definition not found, creating implicitly: \'b_sign\'\n                                                                          : ... Suggested alternative: \'a_sign\'\n assign b_sign = B[31];\n        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179980995/FPU/workingv3.v:43: Signal definition not found, creating implicitly: \'ADD\'\n assign ADD = !opcode[1] & !opcode[0];\n        ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/179980995/FPU/workingv3.v:44: Signal definition not found, creating implicitly: \'SUB\'\n assign SUB = !opcode[1] & opcode[0];\n        ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/179980995/FPU/workingv3.v:45: Signal definition not found, creating implicitly: \'DIV\'\n assign DIV = opcode[1] & !opcode[0];\n        ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/179980995/FPU/workingv3.v:46: Signal definition not found, creating implicitly: \'MUL\'\n assign MUL = opcode[1] & opcode[0];\n        ^~~\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1271: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[47]; div_a_in47 = r; r = div_out47; q[0] = div_cout47; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1271: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out47\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[47]; div_a_in47 = r; r = div_out47; q[0] = div_cout47; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1272: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[46]; div_a_in46 = r; r = div_out46; q[0] = div_cout46; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1272: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out46\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[46]; div_a_in46 = r; r = div_out46; q[0] = div_cout46; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1273: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[45]; div_a_in45 = r; r = div_out45; q[0] = div_cout45; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1273: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out45\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[45]; div_a_in45 = r; r = div_out45; q[0] = div_cout45; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1274: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[44]; div_a_in44 = r; r = div_out44; q[0] = div_cout44; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1274: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out44\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[44]; div_a_in44 = r; r = div_out44; q[0] = div_cout44; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1275: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[43]; div_a_in43 = r; r = div_out43; q[0] = div_cout43; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1275: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out43\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[43]; div_a_in43 = r; r = div_out43; q[0] = div_cout43; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1276: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[42]; div_a_in42 = r; r = div_out42; q[0] = div_cout42; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1276: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out42\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[42]; div_a_in42 = r; r = div_out42; q[0] = div_cout42; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1277: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[41]; div_a_in41 = r; r = div_out41; q[0] = div_cout41; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1277: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out41\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[41]; div_a_in41 = r; r = div_out41; q[0] = div_cout41; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1278: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[40]; div_a_in40 = r; r = div_out40; q[0] = div_cout40; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1278: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out40\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[40]; div_a_in40 = r; r = div_out40; q[0] = div_cout40; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1279: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[39]; div_a_in39 = r; r = div_out39; q[0] = div_cout39; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1279: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out39\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[39]; div_a_in39 = r; r = div_out39; q[0] = div_cout39; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1280: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[38]; div_a_in38 = r; r = div_out38; q[0] = div_cout38; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1280: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out38\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[38]; div_a_in38 = r; r = div_out38; q[0] = div_cout38; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1281: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[37]; div_a_in37 = r; r = div_out37; q[0] = div_cout37; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1281: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out37\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[37]; div_a_in37 = r; r = div_out37; q[0] = div_cout37; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1282: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[36]; div_a_in36 = r; r = div_out36; q[0] = div_cout36; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1282: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out36\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[36]; div_a_in36 = r; r = div_out36; q[0] = div_cout36; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1283: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[35]; div_a_in35 = r; r = div_out35; q[0] = div_cout35; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1283: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out35\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[35]; div_a_in35 = r; r = div_out35; q[0] = div_cout35; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1284: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[34]; div_a_in34 = r; r = div_out34; q[0] = div_cout34; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1284: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out34\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[34]; div_a_in34 = r; r = div_out34; q[0] = div_cout34; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1285: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[33]; div_a_in33 = r; r = div_out33; q[0] = div_cout33; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1285: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out33\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[33]; div_a_in33 = r; r = div_out33; q[0] = div_cout33; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1286: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[32]; div_a_in32 = r; r = div_out32; q[0] = div_cout32; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1286: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out32\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[32]; div_a_in32 = r; r = div_out32; q[0] = div_cout32; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1287: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[31]; div_a_in31 = r; r = div_out31; q[0] = div_cout31; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1287: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out31\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[31]; div_a_in31 = r; r = div_out31; q[0] = div_cout31; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1288: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[30]; div_a_in30 = r; r = div_out30; q[0] = div_cout30; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1288: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out30\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[30]; div_a_in30 = r; r = div_out30; q[0] = div_cout30; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1289: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[29]; div_a_in29 = r; r = div_out29; q[0] = div_cout29; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1289: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out29\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[29]; div_a_in29 = r; r = div_out29; q[0] = div_cout29; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1290: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[28]; div_a_in28 = r; r = div_out28; q[0] = div_cout28; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1290: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out28\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[28]; div_a_in28 = r; r = div_out28; q[0] = div_cout28; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1291: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[27]; div_a_in27 = r; r = div_out27; q[0] = div_cout27; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1291: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out27\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[27]; div_a_in27 = r; r = div_out27; q[0] = div_cout27; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1292: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[26]; div_a_in26 = r; r = div_out26; q[0] = div_cout26; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1292: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out26\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[26]; div_a_in26 = r; r = div_out26; q[0] = div_cout26; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1293: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[25]; div_a_in25 = r; r = div_out25; q[0] = div_cout25; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1293: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out25\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[25]; div_a_in25 = r; r = div_out25; q[0] = div_cout25; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1294: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[24]; div_a_in24 = r; r = div_out24; q[0] = div_cout24; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1294: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out24\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[24]; div_a_in24 = r; r = div_out24; q[0] = div_cout24; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1295: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[23]; div_a_in23 = r; r = div_out23; q[0] = div_cout23; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1295: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out23\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[23]; div_a_in23 = r; r = div_out23; q[0] = div_cout23; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1296: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[22]; div_a_in22 = r; r = div_out22; q[0] = div_cout22; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1296: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out22\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[22]; div_a_in22 = r; r = div_out22; q[0] = div_cout22; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1297: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[21]; div_a_in21 = r; r = div_out21; q[0] = div_cout21; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1297: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out21\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[21]; div_a_in21 = r; r = div_out21; q[0] = div_cout21; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1298: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[20]; div_a_in20 = r; r = div_out20; q[0] = div_cout20; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1298: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out20\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[20]; div_a_in20 = r; r = div_out20; q[0] = div_cout20; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1299: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[19]; div_a_in19 = r; r = div_out19; q[0] = div_cout19; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1299: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out19\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[19]; div_a_in19 = r; r = div_out19; q[0] = div_cout19; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1300: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[18]; div_a_in18 = r; r = div_out18; q[0] = div_cout18; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1300: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out18\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[18]; div_a_in18 = r; r = div_out18; q[0] = div_cout18; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1301: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[17]; div_a_in17 = r; r = div_out17; q[0] = div_cout17; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1301: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out17\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[17]; div_a_in17 = r; r = div_out17; q[0] = div_cout17; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1302: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[16]; div_a_in16 = r; r = div_out16; q[0] = div_cout16; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1302: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out16\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[16]; div_a_in16 = r; r = div_out16; q[0] = div_cout16; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1303: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[15]; div_a_in15 = r; r = div_out15; q[0] = div_cout15; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1303: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out15\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[15]; div_a_in15 = r; r = div_out15; q[0] = div_cout15; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1304: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[14]; div_a_in14 = r; r = div_out14; q[0] = div_cout14; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1304: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out14\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[14]; div_a_in14 = r; r = div_out14; q[0] = div_cout14; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1305: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[13]; div_a_in13 = r; r = div_out13; q[0] = div_cout13; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1305: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out13\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[13]; div_a_in13 = r; r = div_out13; q[0] = div_cout13; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1306: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[12]; div_a_in12 = r; r = div_out12; q[0] = div_cout12; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1306: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out12\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[12]; div_a_in12 = r; r = div_out12; q[0] = div_cout12; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1307: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[11]; div_a_in11 = r; r = div_out11; q[0] = div_cout11; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1307: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out11\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[11]; div_a_in11 = r; r = div_out11; q[0] = div_cout11; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1308: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[10]; div_a_in10 = r; r = div_out10; q[0] = div_cout10; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1308: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out10\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[10]; div_a_in10 = r; r = div_out10; q[0] = div_cout10; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1309: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[9]; div_a_in9 = r; r = div_out9; q[0] = div_cout9; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1309: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out9\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[9]; div_a_in9 = r; r = div_out9; q[0] = div_cout9; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1310: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[8]; div_a_in8 = r; r = div_out8; q[0] = div_cout8; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1310: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out8\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[8]; div_a_in8 = r; r = div_out8; q[0] = div_cout8; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1311: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[7]; div_a_in7 = r; r = div_out7; q[0] = div_cout7; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1311: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out7\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[7]; div_a_in7 = r; r = div_out7; q[0] = div_cout7; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1312: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[6]; div_a_in6 = r; r = div_out6; q[0] = div_cout6; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1312: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out6\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[6]; div_a_in6 = r; r = div_out6; q[0] = div_cout6; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1313: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[5]; div_a_in5 = r; r = div_out5; q[0] = div_cout5; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1313: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out5\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[5]; div_a_in5 = r; r = div_out5; q[0] = div_cout5; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1314: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[4]; div_a_in4 = r; r = div_out4; q[0] = div_cout4; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1314: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out4\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[4]; div_a_in4 = r; r = div_out4; q[0] = div_cout4; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1315: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[3]; div_a_in3 = r; r = div_out3; q[0] = div_cout3; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1315: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out3\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[3]; div_a_in3 = r; r = div_out3; q[0] = div_cout3; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1316: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[2]; div_a_in2 = r; r = div_out2; q[0] = div_cout2; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1316: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out2\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[2]; div_a_in2 = r; r = div_out2; q[0] = div_cout2; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1317: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[1]; div_a_in1 = r; r = div_out1; q[0] = div_cout1; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1317: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out1\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[1]; div_a_in1 = r; r = div_out1; q[0] = div_cout1; q = {q[47:0], 1\'b0}; r = {r[47:0], 1\'b0};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1318: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 49 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[0]; div_a_in0 = r; r = div_out0; q[0] = div_cout0;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1318: Operator ASSIGN expects 49 bits on the Assign RHS, but Assign RHS\'s VARREF \'div_out0\' generates 48 bits.\n                                                                         : ... In instance fpu.D1.div_mod\nr[0] = a[0]; div_a_in0 = r; r = div_out0; q[0] = div_cout0;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:1015: Operator ASSIGN expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_out_div0\' generates 25 bits.\n                                                                         : ... In instance fpu.D1\n  add_a_div1 = add_out_div0;\n             ^\n%Error: data/full_repos/permissive/179980995/FPU/workingv3.v:584: Cannot find file containing module: \'dadda24\'\n dadda24 mul0\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179980995/FPU,data/full_repos/permissive/179980995/dadda24\n             data/full_repos/permissive/179980995/FPU,data/full_repos/permissive/179980995/dadda24.v\n             data/full_repos/permissive/179980995/FPU,data/full_repos/permissive/179980995/dadda24.sv\n             dadda24\n             dadda24.v\n             dadda24.sv\n             obj_dir/dadda24\n             obj_dir/dadda24.v\n             obj_dir/dadda24.sv\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:613: Operator ASSIGN expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'add_out_norm0\' generates 25 bits.\n                                                                        : ... In instance fpu.M1\n add_a_norm1 = add_out_norm0;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:638: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s SEL generates 24 bits.\n                                                                        : ... In instance fpu.M1\n  o_mantissa = product[46:23];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:436: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'a_mantissa\' generates 24 bits.\n                                                                        : ... In instance fpu.A1\n  o_mantissa = a_mantissa;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:466: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'b_mantissa\' generates 24 bits.\n                                                                        : ... In instance fpu.A1\n  o_mantissa = b_mantissa;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:471: Operator ASSIGN expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'shift_out0\' generates 32 bits.\n                                                                        : ... In instance fpu.A1\n  tmp_mantissa = shift_out0;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:75: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'a_mantissa\' generates 24 bits.\n                                                                       : ... In instance fpu\n    o_mantissa = a_mantissa;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:80: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'b_mantissa\' generates 24 bits.\n                                                                       : ... In instance fpu\n    o_mantissa = b_mantissa;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:91: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n                                                                       : ... In instance fpu\n    o_mantissa = adder_out[22:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:98: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'a_mantissa\' generates 24 bits.\n                                                                       : ... In instance fpu\n    o_mantissa = a_mantissa;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:103: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'b_mantissa\' generates 24 bits.\n                                                                        : ... In instance fpu\n    o_mantissa = b_mantissa;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:114: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n                                                                        : ... In instance fpu\n    o_mantissa = adder_out[22:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:121: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'a_mantissa\' generates 24 bits.\n                                                                        : ... In instance fpu\n    o_mantissa = a_mantissa;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:168: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n                                                                        : ... In instance fpu\n    o_mantissa = divider_out[22:0];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:175: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'a_mantissa\' generates 24 bits.\n                                                                        : ... In instance fpu\n    o_mantissa = a_mantissa;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:180: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'b_mantissa\' generates 24 bits.\n                                                                        : ... In instance fpu\n    o_mantissa = b_mantissa;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/179980995/FPU/workingv3.v:196: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s SEL generates 23 bits.\n                                                                        : ... In instance fpu\n    o_mantissa = multiplier_out[22:0];\n               ^\n%Error: Exiting due to 1 error(s), 119 warning(s)\n'
module fpu(clk, A, B, opcode, O);
	input clk;
	input [31:0] A, B;
	input [1:0] opcode;
	output [31:0] O;

	wire [31:0] O;
	wire [7:0] a_exponent;
	wire [23:0] a_mantissa;
	wire [7:0] b_exponent;
	wire [23:0] b_mantissa;

	reg        o_sign;
	reg [7:0]  o_exponent;
	reg [24:0] o_mantissa;


	reg [31:0] adder_a_in;
	reg [31:0] adder_b_in;
	wire [31:0] adder_out;

	reg [31:0] multiplier_a_in;
	reg [31:0] multiplier_b_in;
	wire [31:0] multiplier_out;

	reg [31:0] divider_a_in;
	reg [31:0] divider_b_in;
	wire [31:0] divider_out;

	assign O[31] = o_sign;
	assign O[30:23] = o_exponent;
	assign O[22:0] = o_mantissa[22:0];

	assign a_sign = A[31];
	assign a_exponent[7:0] = A[30:23];
	assign a_mantissa[23:0] = {1'b1, A[22:0]};

	assign b_sign = B[31];
	assign b_exponent[7:0] = B[30:23];
	assign b_mantissa[23:0] = {1'b1, B[22:0]};

	assign ADD = !opcode[1] & !opcode[0];
	assign SUB = !opcode[1] & opcode[0];
	assign DIV = opcode[1] & !opcode[0];
	assign MUL = opcode[1] & opcode[0];

	adder A1
	(
		.a(adder_a_in),
		.b(adder_b_in),
		.out(adder_out)
	);

	multiplier M1
	(
		.a(multiplier_a_in),
		.b(multiplier_b_in),
		.out(multiplier_out)
	);

	divider D1
	(
		.a(divider_a_in),
		.b(divider_b_in),
		.out(divider_out)
	);

	always @ (posedge clk) begin
		if (ADD) begin

			if ((a_exponent == 255 && a_mantissa != 0) || (b_exponent == 0) && (b_mantissa == 0)) begin
				o_sign = a_sign;
				o_exponent = a_exponent;
				o_mantissa = a_mantissa;

			end else if ((b_exponent == 255 && b_mantissa != 0) || (a_exponent == 0) && (a_mantissa == 0)) begin
				o_sign = b_sign;
				o_exponent = b_exponent;
				o_mantissa = b_mantissa;

			end else if ((a_exponent == 255) || (b_exponent == 255)) begin
				o_sign = a_sign ^ b_sign;
				o_exponent = 255;
				o_mantissa = 0;
			end else begin
				adder_a_in = A;
				adder_b_in = B;
				o_sign = adder_out[31];
				o_exponent = adder_out[30:23];
				o_mantissa = adder_out[22:0];
			end
		end else if (SUB) begin

			if ((a_exponent == 255 && a_mantissa != 0) || (b_exponent == 0) && (b_mantissa == 0)) begin
				o_sign = a_sign;
				o_exponent = a_exponent;
				o_mantissa = a_mantissa;

			end else if ((b_exponent == 255 && b_mantissa != 0) || (a_exponent == 0) && (a_mantissa == 0)) begin
				o_sign = b_sign;
				o_exponent = b_exponent;
				o_mantissa = b_mantissa;

			end else if ((a_exponent == 255) || (b_exponent == 255)) begin
				o_sign = a_sign ^ b_sign;
				o_exponent = 255;
				o_mantissa = 0;
			end else begin
				adder_a_in = A;
				adder_b_in = {~B[31], B[30:0]};
				o_sign = adder_out[31];
				o_exponent = adder_out[30:23];
				o_mantissa = adder_out[22:0];
			end
		end else if (DIV) begin

			if ((a_exponent == 255 && a_mantissa != 0) || (b_exponent == 255 && b_mantissa != 0)) begin
				o_sign = a_sign;
				o_exponent = 255;
				o_mantissa = a_mantissa;

			end else if ((a_exponent == 255) && (b_exponent == 255)) begin
				o_sign = 1;
				o_exponent = 255;
				o_mantissa[22] = 1;
				o_mantissa[21:0] = 0;

			end else if (a_exponent == 255) begin
				o_sign = a_sign;
				o_exponent = 255;
				o_mantissa = 0;

				if ((b_exponent == 0) && (b_mantissa == 0)) begin
				o_sign = 1;
				o_exponent = 255;
				o_mantissa[22] = 1;
				o_mantissa[21:0] = 0;
				end

			end else if (b_exponent == 255) begin
				o_sign = b_sign;
				o_exponent = 0;
				o_mantissa = 0;

			end else if ((a_exponent == 0) && (a_mantissa == 0)) begin
				o_sign = a_sign;
				o_exponent = 0;
				o_mantissa = 0;

				if ((b_exponent == 0) && (b_mantissa == 0)) begin
				o_sign = 1;
				o_exponent = 255;
				o_mantissa[22] = 1;
				o_mantissa[21:0] = 0;
			end

			end else if ((b_exponent == 0) && (b_mantissa == 0)) begin
				o_sign = a_sign ^ b_sign;
				o_exponent = 255;
				o_mantissa = 0;
			end else begin

				divider_a_in = A;
				divider_b_in = B;
				o_sign = divider_out[31];
				o_exponent = divider_out[30:23];
				o_mantissa = divider_out[22:0];
			end
		end else begin

			if (a_exponent == 255 && a_mantissa != 0) begin
				o_sign = a_sign;
				o_exponent = 255;
				o_mantissa = a_mantissa;

			end else if (b_exponent == 255 && b_mantissa != 0) begin
				o_sign = b_sign;
				o_exponent = 255;
				o_mantissa = b_mantissa;

			end else if (((a_exponent == 0) && (a_mantissa == 0)) || ((b_exponent == 0) && (b_mantissa == 0))) begin
				o_sign = a_sign ^ b_sign;
				o_exponent = 0;
				o_mantissa = 0;

			end else if ((a_exponent == 255) || (b_exponent == 255)) begin
				o_sign = a_sign;
				o_exponent = 255;
				o_mantissa = 0;
			end else begin
				multiplier_a_in = A;
				multiplier_b_in = B;
				o_sign = multiplier_out[31];
				o_exponent = multiplier_out[30:23];
				o_mantissa = multiplier_out[22:0];
			end
		end
	end
endmodule
module fpu(clk, A, B, opcode, O);

	input clk;
	input [31:0] A, B;
	input [1:0] opcode;
	output [31:0] O;

	wire [31:0] O;
	wire [7:0] a_exponent;
	wire [23:0] a_mantissa;
	wire [7:0] b_exponent;
	wire [23:0] b_mantissa;

	reg        o_sign;
	reg [7:0]  o_exponent;
	reg [24:0] o_mantissa;


	reg [31:0] adder_a_in;
	reg [31:0] adder_b_in;
	wire [31:0] adder_out;

	reg [31:0] multiplier_a_in;
	reg [31:0] multiplier_b_in;
	wire [31:0] multiplier_out;

	reg [31:0] divider_a_in;
	reg [31:0] divider_b_in;
	wire [31:0] divider_out;

	assign O[31] = o_sign;
	assign O[30:23] = o_exponent;
	assign O[22:0] = o_mantissa[22:0];

	assign a_sign = A[31];
	assign a_exponent[7:0] = A[30:23];
	assign a_mantissa[23:0] = {1'b1, A[22:0]};

	assign b_sign = B[31];
	assign b_exponent[7:0] = B[30:23];
	assign b_mantissa[23:0] = {1'b1, B[22:0]};

	assign ADD = !opcode[1] & !opcode[0];
	assign SUB = !opcode[1] & opcode[0];
	assign DIV = opcode[1] & !opcode[0];
	assign MUL = opcode[1] & opcode[0];

	adder A1
	(
		.a(adder_a_in),
		.b(adder_b_in),
		.out(adder_out)
	);

	multiplier M1
	(
		.a(multiplier_a_in),
		.b(multiplier_b_in),
		.out(multiplier_out)
	);

	divider D1
	(
		.a(divider_a_in),
		.b(divider_b_in),
		.out(divider_out)
	);

	always @ (posedge clk) begin
		if (ADD) begin

			if ((a_exponent == 255 && a_mantissa != 0) || (b_exponent == 0) && (b_mantissa == 0)) begin
				o_sign = a_sign;
				o_exponent = a_exponent;
				o_mantissa = a_mantissa;

			end else if ((b_exponent == 255 && b_mantissa != 0) || (a_exponent == 0) && (a_mantissa == 0)) begin
				o_sign = b_sign;
				o_exponent = b_exponent;
				o_mantissa = b_mantissa;

			end else if ((a_exponent == 255) || (b_exponent == 255)) begin
				o_sign = a_sign ^ b_sign;
				o_exponent = 255;
				o_mantissa = 0;
			end else begin
				adder_a_in = A;
				adder_b_in = B;
				o_sign = adder_out[31];
				o_exponent = adder_out[30:23];
				o_mantissa = adder_out[22:0];
			end
		end else if (SUB) begin

			if ((a_exponent == 255 && a_mantissa != 0) || (b_exponent == 0) && (b_mantissa == 0)) begin
				o_sign = a_sign;
				o_exponent = a_exponent;
				o_mantissa = a_mantissa;

			end else if ((b_exponent == 255 && b_mantissa != 0) || (a_exponent == 0) && (a_mantissa == 0)) begin
				o_sign = b_sign;
				o_exponent = b_exponent;
				o_mantissa = b_mantissa;

			end else if ((a_exponent == 255) || (b_exponent == 255)) begin
				o_sign = a_sign ^ b_sign;
				o_exponent = 255;
				o_mantissa = 0;
			end else begin
				adder_a_in = A;
				adder_b_in = {~B[31], B[30:0]};
				o_sign = adder_out[31];
				o_exponent = adder_out[30:23];
				o_mantissa = adder_out[22:0];
			end
		end else if (DIV) begin

			if ((a_exponent == 255 && a_mantissa != 0) || (b_exponent == 255 && b_mantissa != 0)) begin
				o_sign = a_sign;
				o_exponent = 255;
				o_mantissa = a_mantissa;

			end else if ((a_exponent == 255) && (b_exponent == 255)) begin
				o_sign = 1;
				o_exponent = 255;
				o_mantissa[22] = 1;
				o_mantissa[21:0] = 0;

			end else if (a_exponent == 255) begin
				o_sign = a_sign;
				o_exponent = 255;
				o_mantissa = 0;

				if ((b_exponent == 0) && (b_mantissa == 0)) begin
				o_sign = 1;
				o_exponent = 255;
				o_mantissa[22] = 1;
				o_mantissa[21:0] = 0;
				end

			end else if (b_exponent == 255) begin
				o_sign = b_sign;
				o_exponent = 0;
				o_mantissa = 0;

			end else if ((a_exponent == 0) && (a_mantissa == 0)) begin
				o_sign = a_sign;
				o_exponent = 0;
				o_mantissa = 0;

				if ((b_exponent == 0) && (b_mantissa == 0)) begin
				o_sign = 1;
				o_exponent = 255;
				o_mantissa[22] = 1;
				o_mantissa[21:0] = 0;
			end

			end else if ((b_exponent == 0) && (b_mantissa == 0)) begin
				o_sign = a_sign ^ b_sign;
				o_exponent = 255;
				o_mantissa = 0;
			end else begin

				divider_a_in = A;
				divider_b_in = B;
				o_sign = divider_out[31];
				o_exponent = divider_out[30:23];
				o_mantissa = divider_out[22:0];
			end
		end else begin

			if (a_exponent == 255 && a_mantissa != 0) begin
				o_sign = a_sign;
				o_exponent = 255;
				o_mantissa = a_mantissa;

			end else if (b_exponent == 255 && b_mantissa != 0) begin
				o_sign = b_sign;
				o_exponent = 255;
				o_mantissa = b_mantissa;

			end else if (((a_exponent == 0) && (a_mantissa == 0)) || ((b_exponent == 0) && (b_mantissa == 0))) begin
				o_sign = a_sign ^ b_sign;
				o_exponent = 0;
				o_mantissa = 0;

			end else if ((a_exponent == 255) || (b_exponent == 255)) begin
				o_sign = a_sign;
				o_exponent = 255;
				o_mantissa = 0;
			end else begin
				multiplier_a_in = A;
				multiplier_b_in = B;
				o_sign = multiplier_out[31];
				o_exponent = multiplier_out[30:23];
				o_mantissa = multiplier_out[22:0];
			end
		end
	end
endmodule