data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv.v:22: Little bit endian vector: MSB < LSB of bit range: 0:6\n   reg [0:6]       bitcnt;\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv.v:24: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 8 bits.\n                                                                                   : ... In instance matrixdrv\n   assign pixelbitoff = clkcnt >> 1;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv.v:52: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'pixelbitoff\' generates 7 bits.\n                                                                                   : ... In instance matrixdrv\n                       r <= pixelbitoff;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv.v:53: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 7 bits.\n                                                                                   : ... In instance matrixdrv\n                       g <= pixelbitoff >> 2;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv.v:54: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 7 bits.\n                                                                                   : ... In instance matrixdrv\n                       b <= pixelbitoff >> 4;\n                         ^~\n%Warning-UNSIGNED: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv.v:50: Comparison is constant due to unsigned arithmetic\n                                                                                      : ... In instance matrixdrv\n                  if (pixelbitoff >= 0)\n                                  ^~\n%Error: Exiting due to 6 warning(s)\n'
module matrixdrv (
                  input clk,
                  input rst,
                  output [1:0] mat_r,
                  output [1:0] mat_g,
                  output [1:0] mat_b,
                  output [3:0] mat_row,
                  output mat_clk,
                  output mat_lat,
                  output mat_oe
);
   reg [1:0]       r;
   reg [1:0]       g;
   reg [1:0]       b;
   reg [7:0]       clkcnt;
   reg [3:0]       address;
   reg             matclk;
   reg             latch;
   reg             outputen;
   wire [6:0]      pixelbitoff;

   reg [0:6]       bitcnt;

   assign pixelbitoff = clkcnt >> 1;

   always@(posedge clk)
     begin
        if (!rst)
          begin
             r <= 0;
             g <= 0;
             b <= 0;
             clkcnt <= 0;
             matclk <= 0;
             latch <= 0;
             outputen <= 0;
             address <= 0;
             bitcnt <= 0;
          end

        if (clkcnt < 128)
          begin
             latch <= 0;
             outputen <= 0;
             bitcnt <= bitcnt + 1;

             matclk <= clkcnt[0];
             if (!matclk)
               begin
                  if (pixelbitoff >= 0)
                    begin
                       r <= pixelbitoff;
                       g <= pixelbitoff >> 2;
                       b <= pixelbitoff >> 4;
                    end
                  else
                    begin
                       r <= 0;
                       g <= 0;
                       b <= 0;
                    end
               end
             else
               begin

               end
          end
        else
          begin
             matclk <= 0;
             if (clkcnt[0])
               begin
                  latch <= 1;
                  outputen <= 1;
               end
             else
               begin
                  latch <= 0;
                  outputen <= 0;
               end
          end

        if (clkcnt == 130)
          begin
             address <= address + 1;
          end

        if (clkcnt <= 130)
          begin
             clkcnt <= clkcnt + 1;
          end
        else
          begin
             clkcnt <= 0;
          end
     end

   assign mat_r = r;
   assign mat_g = g;
   assign mat_b = b;
   assign mat_row = address;
   assign mat_clk = matclk;
   assign mat_lat = latch;
   assign mat_oe = outputen;
endmodule
module matrixdrv (
                  input clk,
                  input rst,
                  output [1:0] mat_r,
                  output [1:0] mat_g,
                  output [1:0] mat_b,
                  output [3:0] mat_row,
                  output mat_clk,
                  output mat_lat,
                  output mat_oe
);

   reg [1:0]       r;
   reg [1:0]       g;
   reg [1:0]       b;
   reg [7:0]       clkcnt;
   reg [3:0]       address;
   reg             matclk;
   reg             latch;
   reg             outputen;
   wire [6:0]      pixelbitoff;

   reg [0:6]       bitcnt;

   assign pixelbitoff = clkcnt >> 1;

   always@(posedge clk)
     begin
        if (!rst)
          begin
             r <= 0;
             g <= 0;
             b <= 0;
             clkcnt <= 0;
             matclk <= 0;
             latch <= 0;
             outputen <= 0;
             address <= 0;
             bitcnt <= 0;
          end

        if (clkcnt < 128)
          begin
             latch <= 0;
             outputen <= 0;
             bitcnt <= bitcnt + 1;

             matclk <= clkcnt[0];
             if (!matclk)
               begin
                  if (pixelbitoff >= 0)
                    begin
                       r <= pixelbitoff;
                       g <= pixelbitoff >> 2;
                       b <= pixelbitoff >> 4;
                    end
                  else
                    begin
                       r <= 0;
                       g <= 0;
                       b <= 0;
                    end
               end
             else
               begin

               end
          end
        else
          begin
             matclk <= 0;
             if (clkcnt[0])
               begin
                  latch <= 1;
                  outputen <= 1;
               end
             else
               begin
                  latch <= 0;
                  outputen <= 0;
               end
          end

        if (clkcnt == 130)
          begin
             address <= address + 1;
          end

        if (clkcnt <= 130)
          begin
             clkcnt <= clkcnt + 1;
          end
        else
          begin
             clkcnt <= 0;
          end
     end

   assign mat_r = r;
   assign mat_g = g;
   assign mat_b = b;
   assign mat_row = address;
   assign mat_clk = matclk;
   assign mat_lat = latch;
   assign mat_oe = outputen;
endmodule