data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Reciprocal/Reciprocal_Cascaded_tb.v
 line:70: before: "real"
1: b'%Error: Cannot find file containing module: Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Reciprocal,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Reciprocal/Reciprocal_Cascaded_tb.v\n%Error: Exiting due to 3 error(s)\n'
module tb_Division_GS_unsigned_rec_24bit;


	parameter WL = 24;
	parameter LUT_bits = 13;
	parameter LUT_addWidth = 13;
	parameter ITERATION = 1;
	parameter dWL = 27;		
	parameter WLO2 = 24;
	parameter address_bits = 6;
	

	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din;



	wire [dWL-1:0] d1;
	wire [dWL-1:0] p2;
	wire [dWL-1:0] d2, d2_s;
	wire [dWL-1:0] p3;
	wire [dWL-1:0] r3;
	wire [dWL-1:0] r2,r2_s;
	wire [WL-1:0] dout;
	wire [address_bits-1:0] reg_cmp;
	


	reg [WL-1:0] Testdata_vec_NR [`Testdata_Depth-1:0];

	reg [WL-1:0] Simu_Result_Matlab [`Testdata_Depth-1:0];



	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction

	

	Division_GS_unsigned_rec_24bit 
	#(
		.WL(WL),
		.WLO2(WLO2),
		.address_bits(address_bits),
		.LUT_bits(LUT_bits),
		.dWL(dWL)
	)
	Fang_Division_GS_rec 
	(
		.CLK(CLK), 
		.RST(nRST), 
		.CE(CE),
		.in(din), 
		.d1(d1), 
		.p2(p2), 
		.d2(d2),
		.d2_s(d2_s),
		.p3(p3), 
		.r3(r3), 
		.r2(r2), 
		.r2_s(r2_s),
		.result(dout), 
		.reg_cmp(reg_cmp)
	);


	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;



	real real_din, real_MATLAB_reuslt, real_Xilinx_result;
	real real_d1_net, real_p2, real_d2_net;

	integer count;
	real count_mismatched = 0;
	initial begin

		$readmemb("ini_input_binary_GS.txt", Testdata_vec_NR);		
	

		$readmemb("LUT_rec_GS_iter1.txt", tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.LUT);
		$readmemb("result_binary_GS.txt", Simu_Result_Matlab);

		nRST = 0; CE = 0;
		@(posedge CLK); nRST = 1; CE = 1;
		
		for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
			din = Testdata_vec_NR[count];
		   $display("MATLAB: %f, Xilinx: %f", unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1), unsigned_fixedToFloat(dout, 1, WL-1));
			@(posedge CLK);
			if (count==`Testdata_Depth) begin
				$finish;
			end
		end
	end	


	always @ din real_din = unsigned_fixedToFloat(din, 1, WL-1);



	always @ tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.d1_net
			   real_d1_net = unsigned_fixedToFloat(tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.d1_net, 2, dWL-2);
     

	always @ tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.p2
			   real_p2 = unsigned_fixedToFloat(tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.p2, 1, dWL-1);


	always @ tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.d2_net
			   real_d2_net = unsigned_fixedToFloat(tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.d2_net, 2, dWL-2);     
	  

	always @ dout real_Xilinx_result = unsigned_fixedToFloat(dout, 1, WL-1);
	always @ Simu_Result_Matlab[count] real_MATLAB_reuslt = unsigned_fixedToFloat(Simu_Result_Matlab[count], 1, WL-1);
	 
endmodule
module tb_Division_GS_unsigned_rec_24bit;



	parameter WL = 24;
	parameter LUT_bits = 13;
	parameter LUT_addWidth = 13;
	parameter ITERATION = 1;
	parameter dWL = 27;		
	parameter WLO2 = 24;
	parameter address_bits = 6;
	

	reg CLK;
	reg nRST;
	reg CE;
	reg [WL-1:0] din;



	wire [dWL-1:0] d1;
	wire [dWL-1:0] p2;
	wire [dWL-1:0] d2, d2_s;
	wire [dWL-1:0] p3;
	wire [dWL-1:0] r3;
	wire [dWL-1:0] r2,r2_s;
	wire [WL-1:0] dout;
	wire [address_bits-1:0] reg_cmp;
	


	reg [WL-1:0] Testdata_vec_NR [`Testdata_Depth-1:0];

	reg [WL-1:0] Simu_Result_Matlab [`Testdata_Depth-1:0];



	function real unsigned_fixedToFloat;
		input [2047:0] in;
		input integer WI;
		input integer WF;
		integer idx;
		real retVal;
		begin
			retVal = 0;
			for (idx = 0; idx < WI+WF; idx = idx + 1) begin
				if(in[idx] == 1'b1) begin
					retVal = retVal + (2.0**(idx-WF));
				end
			end
		unsigned_fixedToFloat = retVal;
		end
	endfunction

	

	Division_GS_unsigned_rec_24bit 
	#(
		.WL(WL),
		.WLO2(WLO2),
		.address_bits(address_bits),
		.LUT_bits(LUT_bits),
		.dWL(dWL)
	)
	Fang_Division_GS_rec 
	(
		.CLK(CLK), 
		.RST(nRST), 
		.CE(CE),
		.in(din), 
		.d1(d1), 
		.p2(p2), 
		.d2(d2),
		.d2_s(d2_s),
		.p3(p3), 
		.r3(r3), 
		.r2(r2), 
		.r2_s(r2_s),
		.result(dout), 
		.reg_cmp(reg_cmp)
	);


	parameter ClockPeriod = 2;
	initial 	 CLK = 0;
	always # (ClockPeriod/2) CLK = ~CLK;



	real real_din, real_MATLAB_reuslt, real_Xilinx_result;
	real real_d1_net, real_p2, real_d2_net;

	integer count;
	real count_mismatched = 0;
	initial begin

		$readmemb("ini_input_binary_GS.txt", Testdata_vec_NR);		
	

		$readmemb("LUT_rec_GS_iter1.txt", tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.LUT);
		$readmemb("result_binary_GS.txt", Simu_Result_Matlab);

		nRST = 0; CE = 0;
		@(posedge CLK); nRST = 1; CE = 1;
		
		for (count = 0; count <= `Testdata_Depth; count = count+1) begin		
			din = Testdata_vec_NR[count];
		   $display("MATLAB: %f, Xilinx: %f", unsigned_fixedToFloat(Simu_Result_Matlab[count-1], 1, WL-1), unsigned_fixedToFloat(dout, 1, WL-1));
			@(posedge CLK);
			if (count==`Testdata_Depth) begin
				$finish;
			end
		end
	end	


	always @ din real_din = unsigned_fixedToFloat(din, 1, WL-1);



	always @ tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.d1_net
			   real_d1_net = unsigned_fixedToFloat(tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.d1_net, 2, dWL-2);
     

	always @ tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.p2
			   real_p2 = unsigned_fixedToFloat(tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.p2, 1, dWL-1);


	always @ tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.d2_net
			   real_d2_net = unsigned_fixedToFloat(tb_Division_GS_unsigned_rec_24bit.Fang_Division_GS_rec.d2_net, 2, dWL-2);     
	  

	always @ dout real_Xilinx_result = unsigned_fixedToFloat(dout, 1, WL-1);
	always @ Simu_Result_Matlab[count] real_MATLAB_reuslt = unsigned_fixedToFloat(Simu_Result_Matlab[count], 1, WL-1);
	 
endmodule