data/full_repos/permissive/136422019/src/or32.v
data/verilator_xmls/6860b9ab-bfa9-456e-96a2-7cda9ccc5fb9.xml
module or32(
	output wire [31:0] out,
	input wire [31:0] in_a, in_b
);

	assign out = in_a | in_b;
	
endmodule
module or32(
	output wire [31:0] out,
	input wire [31:0] in_a, in_b
);


	assign out = in_a | in_b;
	
endmodule