data/full_repos/permissive/202237519/verilog/digitalsystem7/counter2_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem7/counter2_tb.v:2: Cannot find include file: counter2.v\n`include "counter2.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem7,data/full_repos/permissive/202237519/counter2.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem7,data/full_repos/permissive/202237519/counter2.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem7,data/full_repos/permissive/202237519/counter2.v.sv\n             counter2.v\n             counter2.v.v\n             counter2.v.sv\n             obj_dir/counter2.v\n             obj_dir/counter2.v.v\n             obj_dir/counter2.v.sv\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem7/counter2_tb.v:9: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("counter2_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem7/counter2_tb.v:10: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,RES_UPDNC_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem7/counter2_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1 RESETN<=0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem7/counter2_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #1 RESETN<=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem7/counter2_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n     #2 CLK<=~CLK;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem7/counter2_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n     #2 CLK<=~CLK;\n     ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module RES_UPDNC_tb;
  reg RESETN, CLK, UD;
  wire [3:0] Q;
  updncounter test(RESETN, CLK, UD, Q);
  integer i;  
  initial begin
    $dumpfile("counter2_tb.vcd");
    $dumpvars(0,RES_UPDNC_tb);
    RESETN<=1;  
    CLK <= 0;
    UD<=0;
    #1 RESETN<=0;
    #1 RESETN<=0;
    for(i=0; i<32; i=i+1)begin
     #2 CLK<=~CLK;
   end
    UD<=1;
    for(i=0; i<32; i=i+1)begin
     #2 CLK<=~CLK;
    end
    $finish;
  end
endmodule
module RES_UPDNC_tb;

  reg RESETN, CLK, UD;
  wire [3:0] Q;
  updncounter test(RESETN, CLK, UD, Q);
  integer i;  
  initial begin
    $dumpfile("counter2_tb.vcd");
    $dumpvars(0,RES_UPDNC_tb);
    RESETN<=1;  
    CLK <= 0;
    UD<=0;
    #1 RESETN<=0;
    #1 RESETN<=0;
    for(i=0; i<32; i=i+1)begin
     #2 CLK<=~CLK;
   end
    UD<=1;
    for(i=0; i<32; i=i+1)begin
     #2 CLK<=~CLK;
    end
    $finish;
  end
endmodule