data/full_repos/permissive/148200700/Quartus/designFiles/ip/KBandIPsubPro/KBandIPsubPro_KBandOutput/KBandIPsubPro_KBandOutput_bb.v
data/verilator_xmls/ff5fe5df-8eec-47a3-a70c-7aceffa7565e.xml
module KBandIPsubPro_KBandOutput (
		input  wire         clock_clk,
		input  wire         reset_n_reset_n,
		input  wire [31:0]  csr_writedata,
		input  wire         csr_write,
		input  wire [3:0]   csr_byteenable,
		output wire [31:0]  csr_readdata,
		input  wire         csr_read,
		input  wire [2:0]   csr_address,
		input  wire         descriptor_slave_write,
		output wire         descriptor_slave_waitrequest,
		input  wire [127:0] descriptor_slave_writedata,
		input  wire [15:0]  descriptor_slave_byteenable,
		output wire         csr_irq_irq,
		output wire [31:0]  mm_write_address,
		output wire         mm_write_write,
		output wire [15:0]  mm_write_byteenable,
		output wire [127:0] mm_write_writedata,
		input  wire         mm_write_waitrequest,
		input  wire [127:0] st_sink_data,
		input  wire         st_sink_valid,
		output wire         st_sink_ready
	);
endmodule
module KBandIPsubPro_KBandOutput (
		input  wire         clock_clk,
		input  wire         reset_n_reset_n,
		input  wire [31:0]  csr_writedata,
		input  wire         csr_write,
		input  wire [3:0]   csr_byteenable,
		output wire [31:0]  csr_readdata,
		input  wire         csr_read,
		input  wire [2:0]   csr_address,
		input  wire         descriptor_slave_write,
		output wire         descriptor_slave_waitrequest,
		input  wire [127:0] descriptor_slave_writedata,
		input  wire [15:0]  descriptor_slave_byteenable,
		output wire         csr_irq_irq,
		output wire [31:0]  mm_write_address,
		output wire         mm_write_write,
		output wire [15:0]  mm_write_byteenable,
		output wire [127:0] mm_write_writedata,
		input  wire         mm_write_waitrequest,
		input  wire [127:0] st_sink_data,
		input  wire         st_sink_valid,
		output wire         st_sink_ready
	);

endmodule