data/full_repos/permissive/182889635/branch_unit.v
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1: b'%Error: data/full_repos/permissive/182889635/branch_unit.v:3: syntax error, unexpected \';\', expecting \')\' or \',\'\n    input equal;\n               ^\n%Error: data/full_repos/permissive/182889635/branch_unit.v:7: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [1:0]muxpc,\n    ^~~~~~\n%Error: data/full_repos/permissive/182889635/branch_unit.v:8: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg Wrt,\n    ^~~~~~\n%Error: data/full_repos/permissive/182889635/branch_unit.v:9: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg Wrp\n    ^~~~~~\n%Error: data/full_repos/permissive/182889635/branch_unit.v:19: syntax error, unexpected assign\n    assign H = Hp[1];\n    ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:36: Value too large for 1 bit number: 2\n      end else if((b==1\'d0)&&(H==1\'d0)&&(P==1\'d2)||(P==1\'d3)) begin\n                                            ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:36: Value too large for 1 bit number: 3\n      end else if((b==1\'d0)&&(H==1\'d0)&&(P==1\'d2)||(P==1\'d3)) begin\n                                                       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:47: Value too large for 1 bit number: 3\n        muxpc<=1\'d3;\n               ^~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:58: Value too large for 1 bit number: 2\n      end else if((b==1\'d1)&&(H==1\'d0)&&(Hd==1\'d1)&&(c==1\'d1)&&(Pd==1\'d2)||(Pd==1\'d3)) begin\n                                                                    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:58: Value too large for 1 bit number: 3\n      end else if((b==1\'d1)&&(H==1\'d0)&&(Hd==1\'d1)&&(c==1\'d1)&&(Pd==1\'d2)||(Pd==1\'d3)) begin\n                                                                                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:63: Value too large for 1 bit number: 2\n        if(Pd==1\'d2)\n               ^~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:64: Value too large for 1 bit number: 3\n          Pd<=1\'d3;\n              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:66: Value too large for 1 bit number: 3\n        muxpc<=1\'d3;\n               ^~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:72: Value too large for 1 bit number: 2\n        else Pd<=1\'d2;\n                 ^~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:73: Value too large for 1 bit number: 2\n      end else if((b==1\'d1)&&(H==1\'d0)&&(Hd==1\'d1)&&(c==1\'d0)&&(Pd==1\'d2)||(Pd==1\'d3)) begin\n                                                                    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:73: Value too large for 1 bit number: 3\n      end else if((b==1\'d1)&&(H==1\'d0)&&(Hd==1\'d1)&&(c==1\'d0)&&(Pd==1\'d2)||(Pd==1\'d3)) begin\n                                                                                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:74: Value too large for 1 bit number: 2\n        muxpc<=1\'d2;\n               ^~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:78: Value too large for 1 bit number: 2\n        if(Pd==1\'d2)\n               ^~~~\n%Warning-WIDTH: data/full_repos/permissive/182889635/branch_unit.v:80: Value too large for 1 bit number: 2\n        else Pd<=1\'d2;\n                 ^~~~\n%Error: Exiting due to 5 error(s), 14 warning(s)\n'
module branch_unit(
    input branch_eq,
    input equal;
    input [1:0]Hp,
    input [1:0]Hpd,
    output reg flush,
    output reg [1:0]muxpc,
    output reg Wrt,
    output reg Wrp
);
    
    wire H;
    wire [3:0] P;
    wire Hd;
    wire Pd;
    wire c;
    wire b;

    assign H = Hp[1];
    assign Hd = Hpd[1];
    assign Pd = Hpd[0];
    assign c = equal;
    assign b = branch_eq;

    always @(*) begin
      if((b == 1'd0) && (H == 1'd0)) begin
        muxpc <= 2'd0;
        Wrt <= 1'd0;
        Wrp <= 1'd0;
        flush <= 1'd0;
      end else if((b==1'd0)&&(H==1'd1)&&(P==1'd0)||(P==1'd1)) begin
        muxpc<=2'd0;
        Wrt<=1'd0;
        Wrp<=1'd0;
        flush<=1'd0;
      end else if((b==1'd0)&&(H==1'd0)&&(P==1'd2)||(P==1'd3)) begin
        muxpc<=1'd1;
        Wrt<=1'd0;
        Wrp<=1'd0;
        flush<=1'd0;
      end else if((b==1'd1)&&(H==1'd0)&&(Hd==1'd0)&&(c==1'd0)) begin
        muxpc<=1'd0;
        Wrt<=1'd1;
        Wrp<=1'd1;
        flush<=1'd0;
      end else if((b==1'd1)&&(H==1'd0)&&(Hd==1'd0)&&(c==1'd1)) begin
        muxpc<=1'd3;
        Wrt<=1'd1;
        Wrp<=1'd1;
        flush<=1'd1;
      end else if((b==1'd1)&&(H==1'd0)&&(Hd==1'd1)&&(c==1'd0)&&(Pd==1'd0)||(Pd==1'd1)) begin
        muxpc<=1'd0;
        Wrt<=1'd0;
        Wrp<=1'd0;
        flush<=1'd0;
        if(Pd==1'd1)
          Pd<=1'd0;
      end else if((b==1'd1)&&(H==1'd0)&&(Hd==1'd1)&&(c==1'd1)&&(Pd==1'd2)||(Pd==1'd3)) begin
        muxpc<=1'd0;
        Wrt<=1'd0;
        Wrp<=1'd0;
        flush<=1'd0;
        if(Pd==1'd2)
          Pd<=1'd3;
      end else if((b==1'd1)&&(H==1'd0)&&(Hd==1'd1)&&(c==1'd1)&&(Pd==1'd0)||(Pd==1'd1)) begin
        muxpc<=1'd3;
        Wrt<=1'd0;
        Wrp<=1'd1;
        flush<=1'd1;
        if(Pd==1'd0)
          Pd<=1'd1;
        else Pd<=1'd2;
      end else if((b==1'd1)&&(H==1'd0)&&(Hd==1'd1)&&(c==1'd0)&&(Pd==1'd2)||(Pd==1'd3)) begin
        muxpc<=1'd2;
        Wrt<=1'd0;
        Wrp<=1'd1;
        flush<=1'd1;
        if(Pd==1'd2)
          Pd<=1'd1;
        else Pd<=1'd2;
      

    end



endmodule
module branch_unit(
    input branch_eq,
    input equal;

    input [1:0]Hp,
    input [1:0]Hpd,
    output reg flush,
    output reg [1:0]muxpc,
    output reg Wrt,
    output reg Wrp
);
    
    wire H;
    wire [3:0] P;
    wire Hd;
    wire Pd;
    wire c;
    wire b;

    assign H = Hp[1];
    assign Hd = Hpd[1];
    assign Pd = Hpd[0];
    assign c = equal;
    assign b = branch_eq;

    always @(*) begin
      if((b == 1'd0) && (H == 1'd0)) begin
        muxpc <= 2'd0;
        Wrt <= 1'd0;
        Wrp <= 1'd0;
        flush <= 1'd0;
      end else if((b==1'd0)&&(H==1'd1)&&(P==1'd0)||(P==1'd1)) begin
        muxpc<=2'd0;
        Wrt<=1'd0;
        Wrp<=1'd0;
        flush<=1'd0;
      end else if((b==1'd0)&&(H==1'd0)&&(P==1'd2)||(P==1'd3)) begin
        muxpc<=1'd1;
        Wrt<=1'd0;
        Wrp<=1'd0;
        flush<=1'd0;
      end else if((b==1'd1)&&(H==1'd0)&&(Hd==1'd0)&&(c==1'd0)) begin
        muxpc<=1'd0;
        Wrt<=1'd1;
        Wrp<=1'd1;
        flush<=1'd0;
      end else if((b==1'd1)&&(H==1'd0)&&(Hd==1'd0)&&(c==1'd1)) begin
        muxpc<=1'd3;
        Wrt<=1'd1;
        Wrp<=1'd1;
        flush<=1'd1;
      end else if((b==1'd1)&&(H==1'd0)&&(Hd==1'd1)&&(c==1'd0)&&(Pd==1'd0)||(Pd==1'd1)) begin
        muxpc<=1'd0;
        Wrt<=1'd0;
        Wrp<=1'd0;
        flush<=1'd0;
        if(Pd==1'd1)
          Pd<=1'd0;
      end else if((b==1'd1)&&(H==1'd0)&&(Hd==1'd1)&&(c==1'd1)&&(Pd==1'd2)||(Pd==1'd3)) begin
        muxpc<=1'd0;
        Wrt<=1'd0;
        Wrp<=1'd0;
        flush<=1'd0;
        if(Pd==1'd2)
          Pd<=1'd3;
      end else if((b==1'd1)&&(H==1'd0)&&(Hd==1'd1)&&(c==1'd1)&&(Pd==1'd0)||(Pd==1'd1)) begin
        muxpc<=1'd3;
        Wrt<=1'd0;
        Wrp<=1'd1;
        flush<=1'd1;
        if(Pd==1'd0)
          Pd<=1'd1;
        else Pd<=1'd2;
      end else if((b==1'd1)&&(H==1'd0)&&(Hd==1'd1)&&(c==1'd0)&&(Pd==1'd2)||(Pd==1'd3)) begin
        muxpc<=1'd2;
        Wrt<=1'd0;
        Wrp<=1'd1;
        flush<=1'd1;
        if(Pd==1'd2)
          Pd<=1'd1;
        else Pd<=1'd2;
      

    end



endmodule