data/full_repos/permissive/100597706/testing/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n   always # 5 clk = ~ clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[4] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[4] = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[14] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[14] = 1\'b0;\n    ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_tb_generic;

	reg clk, rst;


	wire[31:0] baddr, bdi, bdo;
	wire bwr;
	wire[1:0] bsz;

	wire[4:0] rfrd, rfrs1, rfrs2;
	wire rfwr;
	wire[31:0] rfD;
	wire[31:0] rfRS1, rfRS2;
	wire simdone;

	wire[31:0] extA, extB;
	wire[31:0] extR;
	wire extStart;
	wire extDone;
	wire[2:0] extFunc3;

	wire brdy;
	wire CS, CSM, CSQM;
	wire IRQ;
	wire [3:0] IRQnum;
	wire [15:0] IRQen;
	reg [15:0] INT;


	assign CS = ~(CSM | CSQM);
	assign brdy = (CS)? 1'b1 : 1'bz; 

	IntCtrl INTCU(
		.clk(clk), .rst(rst),
		.INT(INT), .IRQen(IRQen),
		.IRQ(IRQ), .IRQnum(IRQnum)
	);

	rv32_CPU_v2 CPU(
		.clk(clk),
		.rst(rst),
		.bdi(bdi), .bdo(bdo), .baddr(baddr), .bsz(bsz), .bwr(bwr),
		.rfwr(rfwr), .rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2), .rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2),
		.extA(extA), .extB(extB), .extR(extR), .extStart(extStart), .extDone(extDone), .extFunc3(extFunc3),
		.brdy(brdy),
		.IRQ(IRQ), .IRQnum(IRQnum), .IRQen(IRQen),
		.simdone(simdone)
	);

	m_wrapper #(12) M (
		.clk(clk),
		.baddr(baddr),
		.bdi(bdi),
		.bsz(bsz),
		.bwr(bwr),
		.bdo(bdo),
		.brdy(brdy),
		.CS(CSM)
	);

	qm_wrapper QM (
		.clk(clk),
		.rst(rst),
		.baddr(baddr),
		.bdi(bdi),
		.bsz(bsz),
		.bwr(bwr),
		.bdo(bdo),
		.brdy(brdy),
		.CS(CSQM)
	);

	mul MULEXT (
		.clk(clk),
		.rst(rst),
		.done(extDone),
		.start(extStart),
		.a(extA), .b(extB),
		.p(extR)
	);


    regFile RF (.clk(clk), .rst(rst),
               .rfwr(rfwr),	
               .rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2),
               .rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2)

			   ,.simdone(simdone)
   );

   integer i;


   initial begin clk = 0; end

   always # 5 clk = ~ clk;

   initial begin
	   rst = 0;
	   #50;
	   @(negedge clk);
	   rst = 1;
	   #50;
	   @(negedge clk);
	   rst = 0;
   end


   initial begin
	   INT = 16'd0;
	   #300    INT[4] = 1'b1;
	   #20     INT[4] = 1'b0;

	   #300    INT[14] = 1'b1;
	   #20     INT[14] = 1'b0;
   end

`ifdef _DBUG_
   always @ (posedge clk) begin
	   $display("baddr_tb = %h, brdy_tb: %b, CS_tb : %b, bdo_tb = %h", baddr, brdy, CS, bdo);
   end
`endif

endmodule
module cpu_tb_generic;


	reg clk, rst;


	wire[31:0] baddr, bdi, bdo;
	wire bwr;
	wire[1:0] bsz;

	wire[4:0] rfrd, rfrs1, rfrs2;
	wire rfwr;
	wire[31:0] rfD;
	wire[31:0] rfRS1, rfRS2;
	wire simdone;

	wire[31:0] extA, extB;
	wire[31:0] extR;
	wire extStart;
	wire extDone;
	wire[2:0] extFunc3;

	wire brdy;
	wire CS, CSM, CSQM;
	wire IRQ;
	wire [3:0] IRQnum;
	wire [15:0] IRQen;
	reg [15:0] INT;


	assign CS = ~(CSM | CSQM);
	assign brdy = (CS)? 1'b1 : 1'bz; 

	IntCtrl INTCU(
		.clk(clk), .rst(rst),
		.INT(INT), .IRQen(IRQen),
		.IRQ(IRQ), .IRQnum(IRQnum)
	);

	rv32_CPU_v2 CPU(
		.clk(clk),
		.rst(rst),
		.bdi(bdi), .bdo(bdo), .baddr(baddr), .bsz(bsz), .bwr(bwr),
		.rfwr(rfwr), .rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2), .rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2),
		.extA(extA), .extB(extB), .extR(extR), .extStart(extStart), .extDone(extDone), .extFunc3(extFunc3),
		.brdy(brdy),
		.IRQ(IRQ), .IRQnum(IRQnum), .IRQen(IRQen),
		.simdone(simdone)
	);

	m_wrapper #(12) M (
		.clk(clk),
		.baddr(baddr),
		.bdi(bdi),
		.bsz(bsz),
		.bwr(bwr),
		.bdo(bdo),
		.brdy(brdy),
		.CS(CSM)
	);

	qm_wrapper QM (
		.clk(clk),
		.rst(rst),
		.baddr(baddr),
		.bdi(bdi),
		.bsz(bsz),
		.bwr(bwr),
		.bdo(bdo),
		.brdy(brdy),
		.CS(CSQM)
	);

	mul MULEXT (
		.clk(clk),
		.rst(rst),
		.done(extDone),
		.start(extStart),
		.a(extA), .b(extB),
		.p(extR)
	);


    regFile RF (.clk(clk), .rst(rst),
               .rfwr(rfwr),	
               .rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2),
               .rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2)

			   ,.simdone(simdone)
   );

   integer i;


   initial begin clk = 0; end

   always # 5 clk = ~ clk;

   initial begin
	   rst = 0;
	   #50;
	   @(negedge clk);
	   rst = 1;
	   #50;
	   @(negedge clk);
	   rst = 0;
   end


   initial begin
	   INT = 16'd0;
	   #300    INT[4] = 1'b1;
	   #20     INT[4] = 1'b0;

	   #300    INT[14] = 1'b1;
	   #20     INT[14] = 1'b0;
   end

`ifdef _DBUG_
   always @ (posedge clk) begin
	   $display("baddr_tb = %h, brdy_tb: %b, CS_tb : %b, bdo_tb = %h", baddr, brdy, CS, bdo);
   end
`endif

endmodule