data/full_repos/permissive/161526648/SingleCycle.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:300: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                      : ... In instance SingleCycle.alu\n    result = ALUsrc1 < ALUsrc2;  \n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:227: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                      : ... In instance SingleCycle.ImExtend\n assign out = $signed(in);\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module mux2_1(src1,src2,sel,result);
	parameter N = 32;
	input [N-1:0] src1,src2;
	input sel;
	output reg [N-1:0] result;
	
	always @(sel,src1,src2) begin
		case (sel) 
			1'b0: result = src1;
			1'b1: result = src2;
		endcase
	end
endmodule
module mux2_1(src1,src2,sel,result);

	parameter N = 32;
	input [N-1:0] src1,src2;
	input sel;
	output reg [N-1:0] result;
	
	always @(sel,src1,src2) begin
		case (sel) 
			1'b0: result = src1;
			1'b1: result = src2;
		endcase
	end
endmodule