data/full_repos/permissive/177136805/6bit_ripple_adder.v
1: b"%Error: data/full_repos/permissive/177136805/6bit_ripple_adder.v:18: Cannot find file containing module: 'FullAdder'\n    FullAdder f1(.a(x[0]),.b((~sel&(y[0]))|(sel&(~y[0]))),.cin(sel),.s(sum[0]),.cout(w1));\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/177136805,data/full_repos/permissive/177136805/FullAdder\n             data/full_repos/permissive/177136805,data/full_repos/permissive/177136805/FullAdder.v\n             data/full_repos/permissive/177136805,data/full_repos/permissive/177136805/FullAdder.sv\n             FullAdder\n             FullAdder.v\n             FullAdder.sv\n             obj_dir/FullAdder\n             obj_dir/FullAdder.v\n             obj_dir/FullAdder.sv\n%Error: data/full_repos/permissive/177136805/6bit_ripple_adder.v:19: Cannot find file containing module: 'FullAdder'\n    FullAdder f2(.a(x[1]),.b((~sel&(y[1]))|(sel&(~y[1]))),.cin(w1),.s(sum[1]),.cout(w2));\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/177136805/6bit_ripple_adder.v:20: Cannot find file containing module: 'FullAdder'\n    FullAdder f3(.a(x[2]),.b((~sel&(y[2]))|(sel&(~y[2]))),.cin(w2),.s(sum[2]),.cout(w3));\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/177136805/6bit_ripple_adder.v:21: Cannot find file containing module: 'FullAdder'\n    FullAdder f4(.a(x[3]),.b((~sel&(y[3]))|(sel&(~y[3]))),.cin(w3),.s(sum[3]),.cout(w4));\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/177136805/6bit_ripple_adder.v:22: Cannot find file containing module: 'FullAdder'\n    FullAdder f5(.a(x[4]),.b((~sel&(y[4]))|(sel&(~y[4]))),.cin(w4),.s(sum[4]),.cout(w5));\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/177136805/6bit_ripple_adder.v:23: Cannot find file containing module: 'FullAdder'\n    FullAdder f6(.a(x[5]),.b((~sel&(y[5]))|(sel&(~y[5]))),.cin(w5),.s(sum[5]),.cout(c_out));\n    ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module bit_ripple_adder(
    input [5:0]x,
    input [5:0]y,
    input  sel,
    output overflow,
    output c_out,
    output [5:0]sum    

    );
    wire w1,w2,w3,w4,w5;

    



    FullAdder f1(.a(x[0]),.b((~sel&(y[0]))|(sel&(~y[0]))),.cin(sel),.s(sum[0]),.cout(w1));
    FullAdder f2(.a(x[1]),.b((~sel&(y[1]))|(sel&(~y[1]))),.cin(w1),.s(sum[1]),.cout(w2));
    FullAdder f3(.a(x[2]),.b((~sel&(y[2]))|(sel&(~y[2]))),.cin(w2),.s(sum[2]),.cout(w3));
    FullAdder f4(.a(x[3]),.b((~sel&(y[3]))|(sel&(~y[3]))),.cin(w3),.s(sum[3]),.cout(w4));
    FullAdder f5(.a(x[4]),.b((~sel&(y[4]))|(sel&(~y[4]))),.cin(w4),.s(sum[4]),.cout(w5));
    FullAdder f6(.a(x[5]),.b((~sel&(y[5]))|(sel&(~y[5]))),.cin(w5),.s(sum[5]),.cout(c_out));

    

    assign overflow=(c_out^w5);
endmodule
module bit_ripple_adder(
    input [5:0]x,
    input [5:0]y,
    input  sel,
    output overflow,
    output c_out,
    output [5:0]sum    

    );

    wire w1,w2,w3,w4,w5;

    



    FullAdder f1(.a(x[0]),.b((~sel&(y[0]))|(sel&(~y[0]))),.cin(sel),.s(sum[0]),.cout(w1));
    FullAdder f2(.a(x[1]),.b((~sel&(y[1]))|(sel&(~y[1]))),.cin(w1),.s(sum[1]),.cout(w2));
    FullAdder f3(.a(x[2]),.b((~sel&(y[2]))|(sel&(~y[2]))),.cin(w2),.s(sum[2]),.cout(w3));
    FullAdder f4(.a(x[3]),.b((~sel&(y[3]))|(sel&(~y[3]))),.cin(w3),.s(sum[3]),.cout(w4));
    FullAdder f5(.a(x[4]),.b((~sel&(y[4]))|(sel&(~y[4]))),.cin(w4),.s(sum[4]),.cout(w5));
    FullAdder f6(.a(x[5]),.b((~sel&(y[5]))|(sel&(~y[5]))),.cin(w5),.s(sum[5]),.cout(c_out));

    

    assign overflow=(c_out^w5);
endmodule