data/full_repos/permissive/105152503/core/fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/105152503/core/fifo.v:50: Operator ASSIGNDLY expects 1024 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                   : ... In instance fifo\n   mem<= { WIDTH {1\'b0} };\n      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105152503/core/fifo.v:53: Bit extraction of var[1023:0] requires 10 bit index, not 128 bits.\n                                                                   : ... In instance fifo\n   mem[ctr*WIDTH-1-:WIDTH]<= idata;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module fifo(
	input  wire              rst        ,
	input  wire              clk        ,
	input  wire [WIDTH-1:0]  idata      ,
	output wire [WIDTH-1:0]  odata      ,
	input  wire              next       ,
	input  wire              wr_en      ,
	output wire              full       ,
	output wire              empty
	);


	parameter WIDTH  = 8             ; 
	parameter NCBIT  = 7             ;
	parameter NWRD   = 1<<NCBIT      ;
	parameter SIZE   = WIDTH*NWRD    ;


	reg  [SIZE-1 :0]  mem            ;
	reg  [NWRD-1 :0]  ctr            ;


	assign empty = ctr== 0    ? 1'b1 : 1'b0;
	assign full  = ctr== NWRD ? 1'b1 : 1'b0;
	assign odata = mem[WIDTH-1-:WIDTH]     ;

	always @ (posedge next) begin
		if(~empty) begin
			mem<= mem>>WIDTH;
			ctr<= ctr- 1'b1;
		end
	end

	always @ (posedge clk) begin
		if(rst) begin
			mem<= { WIDTH {1'b0} };
			ctr<= { NWRD  {1'b0} };
		end else if(wr_en) begin
			mem[ctr*WIDTH-1-:WIDTH]<= idata;
			ctr<= ctr+ 1'b1;
		end
	end
endmodule
module fifo(
	input  wire              rst        ,
	input  wire              clk        ,
	input  wire [WIDTH-1:0]  idata      ,
	output wire [WIDTH-1:0]  odata      ,
	input  wire              next       ,
	input  wire              wr_en      ,
	output wire              full       ,
	output wire              empty
	);



	parameter WIDTH  = 8             ; 
	parameter NCBIT  = 7             ;
	parameter NWRD   = 1<<NCBIT      ;
	parameter SIZE   = WIDTH*NWRD    ;


	reg  [SIZE-1 :0]  mem            ;
	reg  [NWRD-1 :0]  ctr            ;


	assign empty = ctr== 0    ? 1'b1 : 1'b0;
	assign full  = ctr== NWRD ? 1'b1 : 1'b0;
	assign odata = mem[WIDTH-1-:WIDTH]     ;

	always @ (posedge next) begin
		if(~empty) begin
			mem<= mem>>WIDTH;
			ctr<= ctr- 1'b1;
		end
	end

	always @ (posedge clk) begin
		if(rst) begin
			mem<= { WIDTH {1'b0} };
			ctr<= { NWRD  {1'b0} };
		end else if(wr_en) begin
			mem[ctr*WIDTH-1-:WIDTH]<= idata;
			ctr<= ctr+ 1'b1;
		end
	end
endmodule