data/full_repos/permissive/211878730/atlys/practice/onehotcounter.v
data/verilator_xmls/d83ce22e-a4d5-4d94-8f51-7e94393b7cc8.xml
module onehotcounter(clk, reset, q);
    parameter width = 4;
    input  wire clk;
    input  wire reset;
    output wire [width-1:0] q;

    reg [width-1:0] data;

    assign q = data;

    always @(posedge clk) begin
        if (reset == 1) begin
            data [width-1:1] <= 0;
            data [0] <= 0;
        end else begin
            data <= {data[width-2:0], data[width-1]};
        end
    end
endmodule
module onehotcounter(clk, reset, q);

    parameter width = 4;
    input  wire clk;
    input  wire reset;
    output wire [width-1:0] q;

    reg [width-1:0] data;

    assign q = data;

    always @(posedge clk) begin
        if (reset == 1) begin
            data [width-1:1] <= 0;
            data [0] <= 0;
        end else begin
            data <= {data[width-2:0], data[width-1]};
        end
    end
endmodule