data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/reset_and_status/reset_and_status.v
1: b'%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/reset_and_status/reset_and_status.v:41: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                                                                                                          : ... In instance reset_and_status\n    reset_count <= reset_count + 2\'b01;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/reset_and_status/reset_and_status.v:57: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n                                                                                                                                                          : ... In instance reset_and_status\n  pio_in = {\n         ^\n%Error: Exiting due to 2 warning(s)\n'
module reset_and_status 
#( 
  parameter PIO_WIDTH=32
)
(
   input clk,
   input resetn,

   output reg [PIO_WIDTH-1 : 0 ]  pio_in,
   input      [PIO_WIDTH-1 : 0 ]  pio_out,

   input  lock_kernel_pll,
   input  fixedclk_locked,

   input  mem0_local_cal_success,
   input  mem0_local_cal_fail,
   input  mem0_local_init_done,

   input  mem1_local_cal_success,
   input  mem1_local_cal_fail,
   input  mem1_local_init_done,

   output reg [1:0] mem_organization,
   output     [1:0] mem_organization_export,
   output           pll_reset,
   output reg       sw_reset_n_out
);

reg   [1:0] pio_out_ddr_mode;
reg  pio_out_pll_reset;
reg  pio_out_sw_reset;


reg [9:0] reset_count;
always@(posedge clk or negedge resetn)
  if (!resetn)
    reset_count <= 10'b0;
  else if (pio_out_sw_reset)
    reset_count <= 10'b0;
  else if (!reset_count[9])
    reset_count <= reset_count + 2'b01;


(* altera_attribute  = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *)

always@(posedge clk)
begin
  pio_out_ddr_mode = pio_out[9:8];
  pio_out_pll_reset = pio_out[30];
  pio_out_sw_reset = pio_out[31];
end


(* altera_attribute  = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *)
always@(posedge clk)
begin
  pio_in = {
            lock_kernel_pll,
            fixedclk_locked,
            1'b0,
            1'b0,
            mem1_local_cal_fail,
            mem0_local_cal_fail,
            mem1_local_cal_success,
            mem1_local_init_done,
            mem0_local_cal_success,
            mem0_local_init_done};
end

(* altera_attribute  = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *)
always@(posedge clk)
  mem_organization = pio_out_ddr_mode;

assign mem_organization_export = mem_organization;

assign pll_reset = pio_out_pll_reset;


always@(posedge clk)
  sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0));

endmodule
module reset_and_status 
#( 
  parameter PIO_WIDTH=32
)
(
   input clk,
   input resetn,

   output reg [PIO_WIDTH-1 : 0 ]  pio_in,
   input      [PIO_WIDTH-1 : 0 ]  pio_out,

   input  lock_kernel_pll,
   input  fixedclk_locked,

   input  mem0_local_cal_success,
   input  mem0_local_cal_fail,
   input  mem0_local_init_done,

   input  mem1_local_cal_success,
   input  mem1_local_cal_fail,
   input  mem1_local_init_done,

   output reg [1:0] mem_organization,
   output     [1:0] mem_organization_export,
   output           pll_reset,
   output reg       sw_reset_n_out
);


reg   [1:0] pio_out_ddr_mode;
reg  pio_out_pll_reset;
reg  pio_out_sw_reset;


reg [9:0] reset_count;
always@(posedge clk or negedge resetn)
  if (!resetn)
    reset_count <= 10'b0;
  else if (pio_out_sw_reset)
    reset_count <= 10'b0;
  else if (!reset_count[9])
    reset_count <= reset_count + 2'b01;


(* altera_attribute  = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *)

always@(posedge clk)
begin
  pio_out_ddr_mode = pio_out[9:8];
  pio_out_pll_reset = pio_out[30];
  pio_out_sw_reset = pio_out[31];
end


(* altera_attribute  = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *)
always@(posedge clk)
begin
  pio_in = {
            lock_kernel_pll,
            fixedclk_locked,
            1'b0,
            1'b0,
            mem1_local_cal_fail,
            mem0_local_cal_fail,
            mem1_local_cal_success,
            mem1_local_init_done,
            mem0_local_cal_success,
            mem0_local_init_done};
end

(* altera_attribute  = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *)
always@(posedge clk)
  mem_organization = pio_out_ddr_mode;

assign mem_organization_export = mem_organization;

assign pll_reset = pio_out_pll_reset;


always@(posedge clk)
  sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0));

endmodule