data/full_repos/permissive/160510184/ALU.v
data/verilator_xmls/2b5188d8-4eae-48cd-827e-805ee1bd79a8.xml
module ALU(Out, R1, R2, Mode, Zero);

    input   [63:0] R1, R2;
	input   [3:0] Mode;

	output  [63:0] Out;
    reg     [63:0] Out;

	output  wire Zero; 
    
	always @(Mode or R1 or R2) 
        begin
		case(Mode)
			`AND: begin
			Out = R1 & R2;
			end
			`OR: begin
			Out = R1 | R2;
			end
			`ADD: begin
			Out = R1 + R2;
			end
			`LSL: begin
			Out = R1 << R2;
			end
			`LSR: begin
			Out = R1 >>> R2;
			end
			`SUB: begin
			Out = R1 - R2;
			end
			`PassB: begin
			Out = R2;
			end
		endcase
	end
	
	assign Zero = (Out == 64'b0);

endmodule
module ALU(Out, R1, R2, Mode, Zero);


    input   [63:0] R1, R2;
	input   [3:0] Mode;

	output  [63:0] Out;
    reg     [63:0] Out;

	output  wire Zero; 
    
	always @(Mode or R1 or R2) 
        begin
		case(Mode)
			`AND: begin
			Out = R1 & R2;
			end
			`OR: begin
			Out = R1 | R2;
			end
			`ADD: begin
			Out = R1 + R2;
			end
			`LSL: begin
			Out = R1 << R2;
			end
			`LSR: begin
			Out = R1 >>> R2;
			end
			`SUB: begin
			Out = R1 - R2;
			end
			`PassB: begin
			Out = R2;
			end
		endcase
	end
	
	assign Zero = (Out == 64'b0);

endmodule