data/full_repos/permissive/211866113/RippleCarryAdder.v
data/verilator_xmls/1566e309-2d70-4d78-a82a-39e516bebabc.xml
module full_adder(input X, input Y, input Cin, output  S, output  Cout);
    wire   w0,w1,w2;

    xor GX0(w0, X, Y);
    xor GX1(S, w0, Cin);
    and GA0(w1, w0, Cin);
    and GA1(w2, X, Y);
    or GO0(Cout, w1, w2);
endmodule
module full_adder(input X, input Y, input Cin, output  S, output  Cout);

    wire   w0,w1,w2;

    xor GX0(w0, X, Y);
    xor GX1(S, w0, Cin);
    and GA0(w1, w0, Cin);
    and GA1(w2, X, Y);
    or GO0(Cout, w1, w2);
endmodule