data/full_repos/permissive/147690299/lab/23_seq_dff_clr/rtl/dff_sync_clr.v
data/verilator_xmls/be58c092-90a6-4574-8b1f-3ef202a2236d.xml
module dff_sync_clr
(
    input       clk,
    input       clr,
    input       d,
    output  reg q
);

    always @ (posedge clk)
        if (clr)
            q <= 0;
        else
            q <= d;
 
endmodule
module dff_sync_clr
(
    input       clk,
    input       clr,
    input       d,
    output  reg q
);


    always @ (posedge clk)
        if (clr)
            q <= 0;
        else
            q <= d;
 
endmodule