data/full_repos/permissive/131249673/MIPS_L_PipeLine/PC.v
data/verilator_xmls/56f103a0-bcf5-4d21-a69a-c0eee22a57e1.xml
module PC( clk, rst, NPC, PC );
           
	input         clk;
	input         rst;
	input  [31:2] NPC;
	output [31:2] PC;
   
	reg [31:2] PC;
	reg [1:0] tmp;


	always @(posedge clk or posedge rst) begin
		if ( rst ) 
			{PC, tmp} <= 32'h0000_3000;   
		else 
			PC <= NPC;
	end
           
endmodule
module PC( clk, rst, NPC, PC );

           
	input         clk;
	input         rst;
	input  [31:2] NPC;
	output [31:2] PC;
   
	reg [31:2] PC;
	reg [1:0] tmp;


	always @(posedge clk or posedge rst) begin
		if ( rst ) 
			{PC, tmp} <= 32'h0000_3000;   
		else 
			PC <= NPC;
	end
           
endmodule