data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/arb_qualify_master.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-IMPLICIT: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/arb_qualify_master.v:44: Signal definition not found, creating implicitly: \'header_match\'\n                                                                                                                                          : ... Suggested alternative: \'header_valid\'\n   assign    header_match = ((header & slave_mask) == (slave_addr & slave_mask)) && slave_valid;\n             ^~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module arb_qualify_master
  #(
    parameter WIDTH=16
    )
    (  
       input clk,
       input reset,
       input clear,     

       input [WIDTH-1:0] header,
       input header_valid,

       input [WIDTH-1:0] slave_addr,
       input [WIDTH-1:0] slave_mask,
       input slave_valid,

       output reg master_valid,
       input master_ack
       );

   localparam WAIT_HEADER_VALID = 0;
   localparam MATCH = 1;
   localparam WAIT_HEADER_NOT_VALID = 2;
   
   
   reg [1:0] state, next_state;

   

   assign    header_match = ((header & slave_mask) == (slave_addr & slave_mask)) && slave_valid;
   
   
   always @(posedge clk)
     if (reset | clear) begin
        state <= WAIT_HEADER_VALID;
	master_valid <= 0;
     end else
       begin	  
	  case(state)



	    WAIT_HEADER_VALID: begin
	       if (header_valid)
		 if (header_match) begin
		    state <= MATCH;
		    master_valid <= 1;
		 end else
		   next_state <= WAIT_HEADER_NOT_VALID;
	    end







	    MATCH: begin
	       if (master_ack) begin
		  master_valid <= 0;
		  state <= WAIT_HEADER_NOT_VALID;
	       end
	    end



	    WAIT_HEADER_NOT_VALID: begin
	       if (!header_valid) begin
		  state <= WAIT_HEADER_VALID;
	       end
	    end
	  endcase
       end

endmodule
module arb_qualify_master
  #(
    parameter WIDTH=16
    )
    (  
       input clk,
       input reset,
       input clear,     

       input [WIDTH-1:0] header,
       input header_valid,

       input [WIDTH-1:0] slave_addr,
       input [WIDTH-1:0] slave_mask,
       input slave_valid,

       output reg master_valid,
       input master_ack
       );


   localparam WAIT_HEADER_VALID = 0;
   localparam MATCH = 1;
   localparam WAIT_HEADER_NOT_VALID = 2;
   
   
   reg [1:0] state, next_state;

   

   assign    header_match = ((header & slave_mask) == (slave_addr & slave_mask)) && slave_valid;
   
   
   always @(posedge clk)
     if (reset | clear) begin
        state <= WAIT_HEADER_VALID;
	master_valid <= 0;
     end else
       begin	  
	  case(state)



	    WAIT_HEADER_VALID: begin
	       if (header_valid)
		 if (header_match) begin
		    state <= MATCH;
		    master_valid <= 1;
		 end else
		   next_state <= WAIT_HEADER_NOT_VALID;
	    end







	    MATCH: begin
	       if (master_ack) begin
		  master_valid <= 0;
		  state <= WAIT_HEADER_NOT_VALID;
	       end
	    end



	    WAIT_HEADER_NOT_VALID: begin
	       if (!header_valid) begin
		  state <= WAIT_HEADER_VALID;
	       end
	    end
	  endcase
       end

endmodule