data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v
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1: b'%Error: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:196: Duplicate declaration of signal: \'scan_done\'\n                                                                             : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire scan_done = dotclk_done;\n       ^~~~~~~~~\n        data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:186: ... Location of original declaration\n   output scan_done,  \n          ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:52: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:54: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:60: Signal definition not found, creating implicitly: \'two_ms\'\n           .timer_pulse(two_ms));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:66: Signal definition not found, creating implicitly: \'one_second\'\n           .timer_pulse(one_second));\n                        ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:76: Signal definition not found, creating implicitly: \'switch_pushed\'\n      .switch_pushed(switch_pushed),     \n                     ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:105: Signal definition not found, creating implicitly: \'scan_done\'\n     .scan_done(scan_done),\n                ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module WF_switch_debounce (
     input  wire clk,
     input  wire sample_en,
     input  wire switch_in,
     output reg  switch_out,
     output wire switch_pushed,
     output wire switch_released);

     reg  [2:0] switch;
     reg        switch_out_d;

     always @ (posedge clk)
       begin
         if ( sample_en)
           switch <= { switch[1:0],switch_in };

         if (switch == 3'b000)
           switch_out <= 1'b1;
         else if (switch == 3'b111)
           switch_out <= 1'b0;
     
         switch_out_d <= switch_out;
       end

     assign switch_pushed   = ~switch_out &&  switch_out_d;
     assign switch_released =  switch_out && ~switch_out_d;

   endmodule
module WF_switch_debounce (
     input  wire clk,
     input  wire sample_en,
     input  wire switch_in,
     output reg  switch_out,
     output wire switch_pushed,
     output wire switch_released);


     reg  [2:0] switch;
     reg        switch_out_d;

     always @ (posedge clk)
       begin
         if ( sample_en)
           switch <= { switch[1:0],switch_in };

         if (switch == 3'b000)
           switch_out <= 1'b1;
         else if (switch == 3'b111)
           switch_out <= 1'b0;
     
         switch_out_d <= switch_out;
       end

     assign switch_pushed   = ~switch_out &&  switch_out_d;
     assign switch_released =  switch_out && ~switch_out_d;

   endmodule