data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag/jtag_info_if.v
1: b"%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag/jtag_info_if.v:41: Cannot find file containing module: 'BSCANE2'\nBSCANE2 #(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag,data/full_repos/permissive/125344718/BSCANE2\n             data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag,data/full_repos/permissive/125344718/BSCANE2.v\n             data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag,data/full_repos/permissive/125344718/BSCANE2.sv\n             BSCANE2\n             BSCANE2.v\n             BSCANE2.sv\n             obj_dir/BSCANE2\n             obj_dir/BSCANE2.v\n             obj_dir/BSCANE2.sv\n%Error: Exiting due to 1 error(s)\n"
module jtag_info_if#(
    parameter JTAG_CHAIN = 3,
    parameter JTAG_DATA_WIDTH = 32
)(

    output jsys_reset,


    input init_ddr3_done
);


wire jcapture;
wire jreset;
wire jshift;
wire jupdate;
wire jtdo;
wire jtdi;
wire jtms;
wire jsel; 
wire jclk;


wire xcapture;
wire xreset;
wire xshift;
wire xupdate;
wire xsel;
wire xtdo;
wire xtdi;
wire xtck;
wire xtms;

reg [JTAG_DATA_WIDTH-1:0] jinfo_buf;
reg [JTAG_DATA_WIDTH-1:0] jreq_buf;
reg [JTAG_DATA_WIDTH-1:0] jresp_buf;


BSCANE2 #(
    .JTAG_CHAIN(JTAG_CHAIN)
)
bse2_inst (
    .CAPTURE(xcapture),
    .DRCK(),
    .RESET(xreset),
    .RUNTEST(),
    .SEL(xsel),
    .SHIFT(xshift),
    .TCK(xtck),
    .TDI(xtdi),
    .TMS(xtms),
    .UPDATE(xupdate),
    .TDO(xtdo)
);

assign jcapture = xcapture;
assign jreset = xreset;
assign jshift = xshift;
assign jupdate = xupdate;
assign xtdo = jtdo;
assign jtdi = xtdi;
assign jtms = xtms;
assign jsel = xsel;

assign jclk = xtck;

assign jtdo = jresp_buf[0];

initial begin: assign_initial_value
    jreq_buf = {JTAG_DATA_WIDTH{1'b0}};
    jresp_buf = {JTAG_DATA_WIDTH{1'b0}};
    jinfo_buf = {JTAG_DATA_WIDTH{1'b0}};
end

always@(posedge jclk) begin
    if(jreset) begin
        jreq_buf <= {JTAG_DATA_WIDTH{1'b0}};
        jresp_buf <= {JTAG_DATA_WIDTH{1'b0}};
        jinfo_buf <= {JTAG_DATA_WIDTH{1'b0}};
    end
    else begin
        if(jsel) begin

            if(jcapture) begin
                jresp_buf <= {JTAG_DATA_WIDTH{1'b0}};


                jresp_buf[0] <= jsys_reset;
                jresp_buf[1] <= init_ddr3_done;

            end

            if(jshift) begin
                jreq_buf <= {jtdi, jreq_buf[JTAG_DATA_WIDTH-1:1]};
                jresp_buf <= {jresp_buf[0], jresp_buf[JTAG_DATA_WIDTH-1:1]};
            end

            if(jupdate) begin
                jinfo_buf <= jreq_buf;
            end
        
        end
    end
end


assign jsys_reset = jinfo_buf[0];

endmodule
module jtag_info_if#(
    parameter JTAG_CHAIN = 3,
    parameter JTAG_DATA_WIDTH = 32
)(

    output jsys_reset,


    input init_ddr3_done
);



wire jcapture;
wire jreset;
wire jshift;
wire jupdate;
wire jtdo;
wire jtdi;
wire jtms;
wire jsel; 
wire jclk;


wire xcapture;
wire xreset;
wire xshift;
wire xupdate;
wire xsel;
wire xtdo;
wire xtdi;
wire xtck;
wire xtms;

reg [JTAG_DATA_WIDTH-1:0] jinfo_buf;
reg [JTAG_DATA_WIDTH-1:0] jreq_buf;
reg [JTAG_DATA_WIDTH-1:0] jresp_buf;


BSCANE2 #(
    .JTAG_CHAIN(JTAG_CHAIN)
)
bse2_inst (
    .CAPTURE(xcapture),
    .DRCK(),
    .RESET(xreset),
    .RUNTEST(),
    .SEL(xsel),
    .SHIFT(xshift),
    .TCK(xtck),
    .TDI(xtdi),
    .TMS(xtms),
    .UPDATE(xupdate),
    .TDO(xtdo)
);

assign jcapture = xcapture;
assign jreset = xreset;
assign jshift = xshift;
assign jupdate = xupdate;
assign xtdo = jtdo;
assign jtdi = xtdi;
assign jtms = xtms;
assign jsel = xsel;

assign jclk = xtck;

assign jtdo = jresp_buf[0];

initial begin: assign_initial_value
    jreq_buf = {JTAG_DATA_WIDTH{1'b0}};
    jresp_buf = {JTAG_DATA_WIDTH{1'b0}};
    jinfo_buf = {JTAG_DATA_WIDTH{1'b0}};
end

always@(posedge jclk) begin
    if(jreset) begin
        jreq_buf <= {JTAG_DATA_WIDTH{1'b0}};
        jresp_buf <= {JTAG_DATA_WIDTH{1'b0}};
        jinfo_buf <= {JTAG_DATA_WIDTH{1'b0}};
    end
    else begin
        if(jsel) begin

            if(jcapture) begin
                jresp_buf <= {JTAG_DATA_WIDTH{1'b0}};


                jresp_buf[0] <= jsys_reset;
                jresp_buf[1] <= init_ddr3_done;

            end

            if(jshift) begin
                jreq_buf <= {jtdi, jreq_buf[JTAG_DATA_WIDTH-1:1]};
                jresp_buf <= {jresp_buf[0], jresp_buf[JTAG_DATA_WIDTH-1:1]};
            end

            if(jupdate) begin
                jinfo_buf <= jreq_buf;
            end
        
        end
    end
end


assign jsys_reset = jinfo_buf[0];

endmodule