data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips/mips.v
1: b"%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips/mips.v:22: Cannot find file containing module: 'datapath'\n    datapath dp (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips,data/full_repos/permissive/168234415/datapath\n             data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips,data/full_repos/permissive/168234415/datapath.v\n             data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips,data/full_repos/permissive/168234415/datapath.sv\n             datapath\n             datapath.v\n             datapath.sv\n             obj_dir/datapath\n             obj_dir/datapath.v\n             obj_dir/datapath.sv\n%Error: data/full_repos/permissive/168234415/A5_Processor_Design_I/Processor_Design_I/Processor_Design_I.srcs/sources_1/imports/single_cycle_mips_source_initial/mips/mips.v:41: Cannot find file containing module: 'controlunit'\n    controlunit cu (\n    ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mips (
        input  wire        clk,
        input  wire        rst,
        input  wire [4:0]  ra3,
        input  wire [31:0] instr,
        input  wire [31:0] rd_dm,
        output wire        we_dm,
        output wire [31:0] pc_current,
        output wire [31:0] alu_out,
        output wire [31:0] wd_dm,
        output wire [31:0] rd3
    );
    
    wire       branch;
    wire       jump;
    wire       reg_dst;
    wire       we_reg;
    wire       alu_src;
    wire       dm2reg;
    wire [2:0] alu_ctrl;

    datapath dp (
            .clk            (clk),
            .rst            (rst),
            .branch         (branch),
            .jump           (jump),
            .reg_dst        (reg_dst),
            .we_reg         (we_reg),
            .alu_src        (alu_src),
            .dm2reg         (dm2reg),
            .alu_ctrl       (alu_ctrl),
            .ra3            (ra3),
            .instr          (instr),
            .rd_dm          (rd_dm),
            .pc_current     (pc_current),
            .alu_out        (alu_out),
            .wd_dm          (wd_dm),
            .rd3            (rd3)
        );

    controlunit cu (
            .opcode         (instr[31:26]),
            .funct          (instr[5:0]),
            .branch         (branch),
            .jump           (jump),
            .reg_dst        (reg_dst),
            .we_reg         (we_reg),
            .alu_src        (alu_src),
            .we_dm          (we_dm),
            .dm2reg         (dm2reg),
            .alu_ctrl       (alu_ctrl)
        );

endmodule
module mips (
        input  wire        clk,
        input  wire        rst,
        input  wire [4:0]  ra3,
        input  wire [31:0] instr,
        input  wire [31:0] rd_dm,
        output wire        we_dm,
        output wire [31:0] pc_current,
        output wire [31:0] alu_out,
        output wire [31:0] wd_dm,
        output wire [31:0] rd3
    );

    
    wire       branch;
    wire       jump;
    wire       reg_dst;
    wire       we_reg;
    wire       alu_src;
    wire       dm2reg;
    wire [2:0] alu_ctrl;

    datapath dp (
            .clk            (clk),
            .rst            (rst),
            .branch         (branch),
            .jump           (jump),
            .reg_dst        (reg_dst),
            .we_reg         (we_reg),
            .alu_src        (alu_src),
            .dm2reg         (dm2reg),
            .alu_ctrl       (alu_ctrl),
            .ra3            (ra3),
            .instr          (instr),
            .rd_dm          (rd_dm),
            .pc_current     (pc_current),
            .alu_out        (alu_out),
            .wd_dm          (wd_dm),
            .rd3            (rd3)
        );

    controlunit cu (
            .opcode         (instr[31:26]),
            .funct          (instr[5:0]),
            .branch         (branch),
            .jump           (jump),
            .reg_dst        (reg_dst),
            .we_reg         (we_reg),
            .alu_src        (alu_src),
            .we_dm          (we_dm),
            .dm2reg         (dm2reg),
            .alu_ctrl       (alu_ctrl)
        );

endmodule