data/full_repos/permissive/13136965/alunit.v
1: b"%Error: data/full_repos/permissive/13136965/alunit.v:2: Duplicate declaration of signal: 'sub'\n                                                      : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg sub;\n    ^~~\n        data/full_repos/permissive/13136965/alunit.v:1: ... Location of original declaration\nmodule alucontroler(input [5:0] imemout,output sub,output select5,output select6,input AluOp);\n                                               ^~~\n%Error: data/full_repos/permissive/13136965/alunit.v:3: Duplicate declaration of signal: 'select5'\nreg select5;\n    ^~~~~~~\n        data/full_repos/permissive/13136965/alunit.v:1: ... Location of original declaration\nmodule alucontroler(input [5:0] imemout,output sub,output select5,output select6,input AluOp);\n                                                          ^~~~~~~\n%Error: data/full_repos/permissive/13136965/alunit.v:4: Duplicate declaration of signal: 'select6'\nreg select6;\n    ^~~~~~~\n        data/full_repos/permissive/13136965/alunit.v:1: ... Location of original declaration\nmodule alucontroler(input [5:0] imemout,output sub,output select5,output select6,input AluOp);\n                                                                         ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module alucontroler(input [5:0] imemout,output sub,output select5,output select6,input AluOp);
reg sub;
reg select5;
reg select6;

always @ (AluOp or imemout)
begin
	if(AluOp == 1'b1)
	begin
		if(imemout == 6'b100000)
		begin
			sub = 1'b0;
			select5 = 1'b0;
			select6 = 1'b1;
		end
		else
		if(imemout == 6'b100100)
		begin
			sub = 1'b0;
			select5 = 1'b0;
			select6 = 1'b0;
		end
		else
		if(imemout == 6'b100101)
		begin
			sub = 1'b0;
			select5 = 1'b1;
			select6 = 1'b0;
		end
		else
		if(imemout == 6'b100010)
		begin
			sub = 1'b1;
			select5 = 1'b0;
			select6 = 1'b1;
		end
		else
		begin
			sub = 1'b0;
			select5 = 1'b0;
			select6 = 1'b1;
		end
	end
	else
	if(AluOp == 1'b0)
	begin
		sub = 1'b0;
		select5 = 1'b0;
		select6 = 1'b1;
	end
end
endmodule
module alucontroler(input [5:0] imemout,output sub,output select5,output select6,input AluOp);

reg sub;
reg select5;
reg select6;

always @ (AluOp or imemout)
begin
	if(AluOp == 1'b1)
	begin
		if(imemout == 6'b100000)
		begin
			sub = 1'b0;
			select5 = 1'b0;
			select6 = 1'b1;
		end
		else
		if(imemout == 6'b100100)
		begin
			sub = 1'b0;
			select5 = 1'b0;
			select6 = 1'b0;
		end
		else
		if(imemout == 6'b100101)
		begin
			sub = 1'b0;
			select5 = 1'b1;
			select6 = 1'b0;
		end
		else
		if(imemout == 6'b100010)
		begin
			sub = 1'b1;
			select5 = 1'b0;
			select6 = 1'b1;
		end
		else
		begin
			sub = 1'b0;
			select5 = 1'b0;
			select6 = 1'b1;
		end
	end
	else
	if(AluOp == 1'b0)
	begin
		sub = 1'b0;
		select5 = 1'b0;
		select6 = 1'b1;
	end
end
endmodule