data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/const_sreg.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/const_sreg.v:17: Cannot find file containing module: 'setting_reg'\n   setting_reg #(.my_addr(BASE), .width(WIDTH)) reg_max\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc,data/full_repos/permissive/214858095/setting_reg\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc,data/full_repos/permissive/214858095/setting_reg.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc,data/full_repos/permissive/214858095/setting_reg.sv\n             setting_reg\n             setting_reg.v\n             setting_reg.sv\n             obj_dir/setting_reg\n             obj_dir/setting_reg.v\n             obj_dir/setting_reg.sv\n%Error: Exiting due to 1 error(s)\n"
module const_sreg
  #(parameter BASE=0,
    parameter WIDTH=32)
   (input clk, input reset,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);

   wire [WIDTH-1:0]     const_val;
   
   setting_reg #(.my_addr(BASE), .width(WIDTH)) reg_max
     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(const_val));

   assign o_tdata = const_val;
   assign o_tlast = 1'b0;
   assign o_tvalid = 1'b1;
   
endmodule
module const_sreg
  #(parameter BASE=0,
    parameter WIDTH=32)
   (input clk, input reset,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
    output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);


   wire [WIDTH-1:0]     const_val;
   
   setting_reg #(.my_addr(BASE), .width(WIDTH)) reg_max
     (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(const_val));

   assign o_tdata = const_val;
   assign o_tlast = 1'b0;
   assign o_tvalid = 1'b1;
   
endmodule