data/full_repos/permissive/106029354/verilog_source/mem_program_testbench.v
1: b'%Error: data/full_repos/permissive/106029354/verilog_source/mem_program_testbench.v:4: Cannot find include file: params_proc.v\n`include "params_proc.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n             params_proc.v\n             params_proc.v.v\n             params_proc.v.sv\n             obj_dir/params_proc.v\n             obj_dir/params_proc.v.v\n             obj_dir/params_proc.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/106029354/verilog_source/mem_program_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module mem_program_testbench();


`include "params_proc.v"


parameter N_TESTES = 6;


integer testes;


reg clk, we;
reg [MEM_WIDTH-1:0] addr;
reg [INSTR_WIDTH-1:0] data_in;
wire [INSTR_WIDTH-1:0] data_out;


mem_program mem_inst (
	.clk(clk), .we(we), .addr(addr),
	.data_in(data_in), .data_out(data_out));


initial begin
	testes = -1;

	clk  = 0;

	addr    = PC_INITIAL - 1;
	we      = 0;
	data_in = 0;
end


always begin

	#4;
	clk = !clk;
end


always @(negedge clk) begin

	testes = testes+1;

	case(testes)
	0: begin
		we = 1;
		addr = addr + 1;
		data_in = 32'h0050;
	end
	1: begin
		we = 1;
		addr = addr + 1;
		data_in = 32'h0850;
	end
	2: begin
		we = 1;
		addr = addr + 1;
		data_in = 32'h8152;
	end
	3: begin
		we = 0;
		addr = PC_INITIAL;
		data_in = 32'h1550;
	end
	4: begin
		we = 0;
		addr = addr+1;
		data_in = 32'h2875;
	end
	5: begin
		we = 0;
		addr = addr+1;
		data_in = 32'h1647;
	end

	default: begin

	end
	endcase
end


always @(posedge clk) begin

	if (testes >= 0 && testes  <= N_TESTES) begin
		if (testes > 0) begin

			$display("\t ------- SAIDAS -------  ");
		    $display("\t DATA_OUT (%3d): %h  ", INSTR_WIDTH, data_out);
		    $display(" ");
		end
		if (testes < N_TESTES) begin

			$display("  Teste # %2d  =>  ", testes);
			$display("\t ------- ENTRADAS -------  ");
			$display("\t WE: %6d  ", we);
			$display("\t ADDR: %6d ", addr);
		    $display("\t DATA_IN (%3d): %h  ", INSTR_WIDTH, data_in);
		    $display(" ");
	    end
	end
end

endmodule
module mem_program_testbench();



`include "params_proc.v"


parameter N_TESTES = 6;


integer testes;


reg clk, we;
reg [MEM_WIDTH-1:0] addr;
reg [INSTR_WIDTH-1:0] data_in;
wire [INSTR_WIDTH-1:0] data_out;


mem_program mem_inst (
	.clk(clk), .we(we), .addr(addr),
	.data_in(data_in), .data_out(data_out));


initial begin
	testes = -1;

	clk  = 0;

	addr    = PC_INITIAL - 1;
	we      = 0;
	data_in = 0;
end


always begin

	#4;
	clk = !clk;
end


always @(negedge clk) begin

	testes = testes+1;

	case(testes)
	0: begin
		we = 1;
		addr = addr + 1;
		data_in = 32'h0050;
	end
	1: begin
		we = 1;
		addr = addr + 1;
		data_in = 32'h0850;
	end
	2: begin
		we = 1;
		addr = addr + 1;
		data_in = 32'h8152;
	end
	3: begin
		we = 0;
		addr = PC_INITIAL;
		data_in = 32'h1550;
	end
	4: begin
		we = 0;
		addr = addr+1;
		data_in = 32'h2875;
	end
	5: begin
		we = 0;
		addr = addr+1;
		data_in = 32'h1647;
	end

	default: begin

	end
	endcase
end


always @(posedge clk) begin

	if (testes >= 0 && testes  <= N_TESTES) begin
		if (testes > 0) begin

			$display("\t ------- SAIDAS -------  ");
		    $display("\t DATA_OUT (%3d): %h  ", INSTR_WIDTH, data_out);
		    $display(" ");
		end
		if (testes < N_TESTES) begin

			$display("  Teste # %2d  =>  ", testes);
			$display("\t ------- ENTRADAS -------  ");
			$display("\t WE: %6d  ", we);
			$display("\t ADDR: %6d ", addr);
		    $display("\t DATA_IN (%3d): %h  ", INSTR_WIDTH, data_in);
		    $display(" ");
	    end
	end
end

endmodule