data/full_repos/permissive/163494071/seg_scan/seg_scan.v
data/verilator_xmls/38287c88-ed97-451d-b83e-92012a2c1dc2.xml
module seg_scan(clk_50M,rst_button, switch, digit_seg, digit_cath);
input clk_50M;
input rst_button;
input [7:0] switch;
output reg [7:0] digit_seg;
output [1:0] digit_cath;
wire reset;
assign reset = rst_button;


reg [31:0] div_count;
always @(posedge clk_50M,posedge reset)
begin
    if(reset)
        div_count <= 0;
    else
        div_count <= div_count + 1;
end


wire [7:0] digit_display;
assign digit_display = switch;

wire [3:0] digit;
always @(*)
begin
    case (digit)
        4'h0:  digit_seg <= 8'b11111100;
        4'h1:  digit_seg <= 8'b01100000;  
        4'h2:  digit_seg <= 8'b11011010;
        4'h3:  digit_seg <= 8'b11110010;
        4'h4:  digit_seg <= 8'b01100110;
        4'h5:  digit_seg <= 8'b10110110;
        4'h6:  digit_seg <= 8'b10111110;
        4'h7:  digit_seg <= 8'b11100000;
        4'h8:  digit_seg <= 8'b11111110;
        4'h9:  digit_seg <= 8'b11110110;
        4'hA:  digit_seg <= 8'b11101110;
        4'hB:  digit_seg <= 8'b00111110;
        4'hC:  digit_seg <= 8'b10011100;
        4'hD:  digit_seg <= 8'b01111010;
        4'hE:  digit_seg <= 8'b10011110;
        4'hF:  digit_seg <= 8'b10001110;
    endcase
end


reg segcath_holdtime;
always @(posedge div_count[10], posedge reset)
begin
if(reset)
     segcath_holdtime <= 0;
else
     segcath_holdtime <= ~segcath_holdtime;
end


assign digit_cath ={segcath_holdtime, ~segcath_holdtime};

assign digit =segcath_holdtime ? digit_display[7:4] : digit_display[3:0];

endmodule
module seg_scan(clk_50M,rst_button, switch, digit_seg, digit_cath);

input clk_50M;
input rst_button;
input [7:0] switch;
output reg [7:0] digit_seg;
output [1:0] digit_cath;
wire reset;
assign reset = rst_button;


reg [31:0] div_count;
always @(posedge clk_50M,posedge reset)
begin
    if(reset)
        div_count <= 0;
    else
        div_count <= div_count + 1;
end


wire [7:0] digit_display;
assign digit_display = switch;

wire [3:0] digit;
always @(*)
begin
    case (digit)
        4'h0:  digit_seg <= 8'b11111100;
        4'h1:  digit_seg <= 8'b01100000;  
        4'h2:  digit_seg <= 8'b11011010;
        4'h3:  digit_seg <= 8'b11110010;
        4'h4:  digit_seg <= 8'b01100110;
        4'h5:  digit_seg <= 8'b10110110;
        4'h6:  digit_seg <= 8'b10111110;
        4'h7:  digit_seg <= 8'b11100000;
        4'h8:  digit_seg <= 8'b11111110;
        4'h9:  digit_seg <= 8'b11110110;
        4'hA:  digit_seg <= 8'b11101110;
        4'hB:  digit_seg <= 8'b00111110;
        4'hC:  digit_seg <= 8'b10011100;
        4'hD:  digit_seg <= 8'b01111010;
        4'hE:  digit_seg <= 8'b10011110;
        4'hF:  digit_seg <= 8'b10001110;
    endcase
end


reg segcath_holdtime;
always @(posedge div_count[10], posedge reset)
begin
if(reset)
     segcath_holdtime <= 0;
else
     segcath_holdtime <= ~segcath_holdtime;
end


assign digit_cath ={segcath_holdtime, ~segcath_holdtime};

assign digit =segcath_holdtime ? digit_display[7:4] : digit_display[3:0];

endmodule