data/full_repos/permissive/129155059/02-shift_register/tester.v
 line:15: before: "initial"
1: b'%Error: data/full_repos/permissive/129155059/02-shift_register/tester.v:1: Cannot find include file: definitions.v\n`include"definitions.v" \n        ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/02-shift_register,data/full_repos/permissive/129155059/definitions.v\n             data/full_repos/permissive/129155059/02-shift_register,data/full_repos/permissive/129155059/definitions.v.v\n             data/full_repos/permissive/129155059/02-shift_register,data/full_repos/permissive/129155059/definitions.v.sv\n             definitions.v\n             definitions.v.v\n             definitions.v.sv\n             obj_dir/definitions.v\n             obj_dir/definitions.v.v\n             obj_dir/definitions.v.sv\n%Error: data/full_repos/permissive/129155059/02-shift_register/tester.v:5: syntax error, unexpected initial, expecting \';\'\n  initial begin\n  ^~~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/tester.v:6: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile ("registro.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/tester.v:7: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, registro_tb);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/tester.v:8: Unsupported or unknown PLI call: $monitor\n    $monitor("At time %t, Q = %h (%0d), S_OUT = %h (%0d)",\n    ^~~~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/tester.v:20: Define or directive not defined: \'`LOAD\'\n    MODO = `LOAD;\n           ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/tester.v:27: Define or directive not defined: \'`PUSH\'\n    MODO = `PUSH;\n           ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/tester.v:32: Define or directive not defined: \'`PUSH\'\n    MODO = `PUSH;\n           ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/tester.v:36: Define or directive not defined: \'`LOAD\'\n    MODO = `LOAD;\n           ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/tester.v:40: Define or directive not defined: \'`CYCLE\'\n    MODO = `CYCLE;\n           ^~~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/tester.v:44: Define or directive not defined: \'`LOAD\'\n    MODO = `LOAD;\n           ^~~~~\n%Error: data/full_repos/permissive/129155059/02-shift_register/tester.v:48: Define or directive not defined: \'`CYCLE\'\n    MODO = `CYCLE;\n           ^~~~~~\n%Error: Exiting due to 12 error(s)\n'
module tester()


  initial begin
    $dumpfile ("registro.vcd");
    $dumpvars(1, registro_tb);
    $monitor("At time %t, Q = %h (%0d), S_OUT = %h (%0d)",
             $time, Q, Q, S_OUT, S_OUT);

    CLK = 1'b0;
    ENB = 1'b0;
    repeat(4) #5 CLK = ~CLK;
    ENB = 1'b1;
    forever #5 CLK = ~CLK;


    @(posedge ENB);
    D = 4'b1101;
    MODO = `LOAD;
    S_IN = 1'b0;
    DIR = 0;
    repeat(6) @(posedge CLK);

    S_IN = 1'b0;
    DIR = 0;
    MODO = `PUSH;
    repeat(6) @(posedge CLK);

    S_IN = 1'b1;
    DIR = 1;
    MODO = `PUSH;
    repeat(6) @(posedge CLK);

    D = 4'b1010;
    MODO = `LOAD;
    repeat(6) @(posedge CLK);

    DIR = 0;
    MODO = `CYCLE;
    repeat(6) @(posedge CLK);

    D = 4'b0110;
    MODO = `LOAD;
    repeat(6) @(posedge CLK);

    DIR = 1;
    MODO = `CYCLE;
    repeat(6) @(posedge CLK);
    $finish;
  end

endmodule
module tester()


  initial begin
    $dumpfile ("registro.vcd");

    $dumpvars(1, registro_tb);
    $monitor("At time %t, Q = %h (%0d), S_OUT = %h (%0d)",
             $time, Q, Q, S_OUT, S_OUT);

    CLK = 1'b0;
    ENB = 1'b0;
    repeat(4) #5 CLK = ~CLK;
    ENB = 1'b1;
    forever #5 CLK = ~CLK;


    @(posedge ENB);
    D = 4'b1101;
    MODO = `LOAD;
    S_IN = 1'b0;
    DIR = 0;
    repeat(6) @(posedge CLK);

    S_IN = 1'b0;
    DIR = 0;
    MODO = `PUSH;
    repeat(6) @(posedge CLK);

    S_IN = 1'b1;
    DIR = 1;
    MODO = `PUSH;
    repeat(6) @(posedge CLK);

    D = 4'b1010;
    MODO = `LOAD;
    repeat(6) @(posedge CLK);

    DIR = 0;
    MODO = `CYCLE;
    repeat(6) @(posedge CLK);

    D = 4'b0110;
    MODO = `LOAD;
    repeat(6) @(posedge CLK);

    DIR = 1;
    MODO = `CYCLE;
    repeat(6) @(posedge CLK);
    $finish;
  end

endmodule