data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog/mem_data.v
 line:101: before: "integer"
data/verilator_xmls/28b9f3d2-c37b-4551-be1c-17a1c89f288a.xml
module mem_data #(
  parameter RAM_WIDTH       = 32,
  parameter RAM_DEPTH       = 2048,
  parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE",
  parameter INIT_FILE       = ""
) (
  input [RAM_WIDTH-1:0]     i_addr,
  input [RAM_WIDTH-1:0]     i_data,
  input                     i_clk,
  input                     i_wea,
  input                     i_ena,
  input                     i_rsta,
  input                     i_regcea,
  input                     i_SB_flag,
  input                     i_SH_flag,
  input                     i_LB_flag,
  input                     i_LH_flag,
  input                     i_Unsigned_flag,
  output [RAM_WIDTH-1:0]    o_data
);

  reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
  reg [RAM_WIDTH-1:0] ram_data = {RAM_WIDTH{1'b0}};


  generate
    if (INIT_FILE != "") begin: use_init_file
      initial
        $readmemb(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
    end else begin: init_bram_to_zero
      integer ram_index;
      initial
        for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
          BRAM[ram_index] = {RAM_WIDTH{1'b0}};
    end
  endgenerate

  always @(posedge i_clk) begin
    if (i_ena) begin
      if (i_wea) begin
        if (i_SB_flag) begin
          BRAM[i_addr] <= {BRAM[i_addr][RAM_WIDTH-1:8], i_data[7:0]};
        end else if (i_SH_flag) begin
          BRAM[i_addr] <= {BRAM[i_addr][RAM_WIDTH-1:16], i_data[15:0]};
        end else begin
          BRAM[i_addr] <= i_data;
        end
      end else begin
        if (i_LB_flag) begin
          if (i_Unsigned_flag) begin
            ram_data <= {{24{1'b0}}, BRAM[i_addr][7:0]};
          end else begin
            ram_data <= {{24{BRAM[i_addr][7]}}, BRAM[i_addr][7:0]};
          end
        end else if (i_LH_flag) begin
          if (i_Unsigned_flag) begin
            ram_data <= {{16{1'b0}}, BRAM[i_addr][15:0]};
          end else begin
            ram_data <= {{16{BRAM[i_addr][15]}}, BRAM[i_addr][15:0]};
          end
        end else begin
          ram_data <= BRAM[i_addr];
        end
      end
    end
  end
  

  generate
    if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register


       assign o_data = ram_data;

    end else begin: output_register



      reg [RAM_WIDTH-1:0] douta_reg = {RAM_WIDTH{1'b0}};

      always @(posedge i_clk)
        if (i_rsta)
          douta_reg <= {RAM_WIDTH{1'b0}};
        else if (i_regcea)
          douta_reg <= ram_data;

      assign o_data = douta_reg;

    end
  endgenerate


  function integer clogb2;
    input integer depth;
      for (clogb2=0; depth>0; clogb2=clogb2+1)
        depth = depth >> 1;
  endfunction

endmodule
module mem_data #(
  parameter RAM_WIDTH       = 32,
  parameter RAM_DEPTH       = 2048,
  parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE",
  parameter INIT_FILE       = ""
) (
  input [RAM_WIDTH-1:0]     i_addr,
  input [RAM_WIDTH-1:0]     i_data,
  input                     i_clk,
  input                     i_wea,
  input                     i_ena,
  input                     i_rsta,
  input                     i_regcea,
  input                     i_SB_flag,
  input                     i_SH_flag,
  input                     i_LB_flag,
  input                     i_LH_flag,
  input                     i_Unsigned_flag,
  output [RAM_WIDTH-1:0]    o_data
);


  reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
  reg [RAM_WIDTH-1:0] ram_data = {RAM_WIDTH{1'b0}};


  generate
    if (INIT_FILE != "") begin: use_init_file
      initial
        $readmemb(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
    end else begin: init_bram_to_zero
      integer ram_index;
      initial
        for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
          BRAM[ram_index] = {RAM_WIDTH{1'b0}};
    end
  endgenerate

  always @(posedge i_clk) begin
    if (i_ena) begin
      if (i_wea) begin
        if (i_SB_flag) begin
          BRAM[i_addr] <= {BRAM[i_addr][RAM_WIDTH-1:8], i_data[7:0]};
        end else if (i_SH_flag) begin
          BRAM[i_addr] <= {BRAM[i_addr][RAM_WIDTH-1:16], i_data[15:0]};
        end else begin
          BRAM[i_addr] <= i_data;
        end
      end else begin
        if (i_LB_flag) begin
          if (i_Unsigned_flag) begin
            ram_data <= {{24{1'b0}}, BRAM[i_addr][7:0]};
          end else begin
            ram_data <= {{24{BRAM[i_addr][7]}}, BRAM[i_addr][7:0]};
          end
        end else if (i_LH_flag) begin
          if (i_Unsigned_flag) begin
            ram_data <= {{16{1'b0}}, BRAM[i_addr][15:0]};
          end else begin
            ram_data <= {{16{BRAM[i_addr][15]}}, BRAM[i_addr][15:0]};
          end
        end else begin
          ram_data <= BRAM[i_addr];
        end
      end
    end
  end
  

  generate
    if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register


       assign o_data = ram_data;

    end else begin: output_register



      reg [RAM_WIDTH-1:0] douta_reg = {RAM_WIDTH{1'b0}};

      always @(posedge i_clk)
        if (i_rsta)
          douta_reg <= {RAM_WIDTH{1'b0}};
        else if (i_regcea)
          douta_reg <= ram_data;

      assign o_data = douta_reg;

    end
  endgenerate


  function integer clogb2;
    input integer depth;
      for (clogb2=0; depth>0; clogb2=clogb2+1)
        depth = depth >> 1;
  endfunction

endmodule