data/full_repos/permissive/187199324/stannel/Send_tb.v
 line:106: before: "begin"
1: b'%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Send_tb.v:6: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = clk !== 1\'b1;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:11: Define or directive not defined: \'`ADDRESS_BITS\'\n  localparam addrBits = `ADDRESS_BITS;\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:11: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam addrBits = `ADDRESS_BITS;\n                                     ^\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:12: Define or directive not defined: \'`DATA_BITS\'\n  localparam dataBits = `DATA_BITS;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:12: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam dataBits = `DATA_BITS;\n                                  ^\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:32: Define or directive not defined: \'`CELL_COUNT\'\n  reg [`CELL_COUNT:0] alternationSet = 17\'b1011;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:32: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  reg [`CELL_COUNT:0] alternationSet = 17\'b1011;\n                  ^\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:33: Define or directive not defined: \'`CELL_COUNT\'\n  reg [`CELL_COUNT:0]           alternationReadySet = 0;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:33: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  reg [`CELL_COUNT:0]           alternationReadySet = 0;\n                  ^\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:70: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:80: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:90: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:99: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:110: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:119: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:128: Define or directive not defined: \'`CELL_COUNT_CONST_1\'\n      alternationSet <= (`CELL_COUNT_CONST_1 << 9) | alternationSet;\n                         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:128: syntax error, unexpected <<, expecting TYPE-IDENTIFIER\n      alternationSet <= (`CELL_COUNT_CONST_1 << 9) | alternationSet;\n                                             ^~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:129: Define or directive not defined: \'`CELL_COUNT_CONST_1\'\n      alternationReadySet <= `CELL_COUNT_CONST_1 << 9;\n                             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:129: syntax error, unexpected <<, expecting TYPE-IDENTIFIER\n      alternationReadySet <= `CELL_COUNT_CONST_1 << 9;\n                                                 ^~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:132: syntax error, unexpected \'@\'\n      @(posedge finished)\n      ^\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:139: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:143: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("Send_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:144: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, Send_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Send_tb.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #3 noReceiverTest;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Send_tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #2 someReceiverTest;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Send_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n    #2 altReceiverTest;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Send_tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n    #2 altReceiverTest2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/187199324/stannel/Send_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n    #2 $finish;\n    ^\n%Error: data/full_repos/permissive/187199324/stannel/Send_tb.v:151: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n'
module Send_tb();

  reg clk;
  always #1 clk = clk !== 1'b1;


  parameter romFile = "zeroes.hex";

  localparam addrBits = `ADDRESS_BITS;
  localparam dataBits = `DATA_BITS;

  wire [addrBits-1:0] address;
  wire [dataBits-1:0] dataIn;
  wire [dataBits-1:0] dataOut;
  wire                readWriteMode;

  IceRam #(.addrBits(addrBits), .dataBits(dataBits), .romFile(romFile)) memory (
    .clk          (clk),
    .address      (address),
    .readWriteMode(readWriteMode),
    .dataIn       (dataIn),
    .dataOut      (dataOut)
  );


  reg                reset = 0;
  reg [addrBits-1:0] channel = 0;
  reg [dataBits-1:0] message;
  reg [addrBits-1:0] txPid;
  reg [`CELL_COUNT:0] alternationSet = 17'b1011;
  reg [`CELL_COUNT:0]           alternationReadySet = 0;

  reg                finished;
  reg                shouldScheduleReceiver;
  reg                shouldDescheduleSender;
  reg [addrBits-1:0] scheduleRxPid;
  reg [dataBits-1:0] deliveredMessage;
  reg                addToAlternationReadySet;

  Send #(.addrBits(addrBits), .dataBits(dataBits)) send0 (
    .clk                     (clk),
    .reset                   (reset),
    .finished                (finished),
    .address                 (address),
    .readWriteMode           (readWriteMode),
    .dataOut                 (dataOut),
    .dataIn                  (dataIn),
    .channel                 (channel),
    .message                 (message),
    .txPid                   (txPid),
    .alternationSet          (alternationSet),
    .alternationReadySet     (alternationReadySet),
    .shouldScheduleReceiver  (shouldScheduleReceiver),
    .shouldDescheduleSender  (shouldDescheduleSender),
    .scheduleRxPid           (scheduleRxPid),
    .deliveredMessage        (deliveredMessage),
    .addToAlternationReadySet(addToAlternationReadySet)
  );


  task noReceiverTest;
    begin
      reset   <= 1;
      channel <= 2;
      message <= 42;
      txPid   <= 12;

      @(posedge finished)
        begin
          reset <= 0;
          if (!shouldDescheduleSender) $error("Should deschedule sender");
          if (shouldScheduleReceiver) $error("Shouldn't schedule receiver");
          if (deliveredMessage != message) $error("Didn't deliver message");
          if (memory.ram[channel] != {8'b0, txPid}) $error("Didn't set sending process");
          if (memory.ram[channel+1] != message) $error("Didn't set sent message");
          if (addToAlternationReadySet) $error("Shouldn't add to alternation ready set");
        end
    end
  endtask


  task someReceiverTest;
    begin
      channel       <= 4;
      memory.ram[4] <= 7;
      reset         <= 1;

      @(posedge finished)
        begin
          reset <= 0;
          if (shouldDescheduleSender) $error("Shouldn't deschedule sender");
          if (!shouldScheduleReceiver) $error("Should schedule receiver");
          if (scheduleRxPid != 7) $error("Should have scheduled process 7");
          if (deliveredMessage != message) $error("Didn't deliver message");
          if (addToAlternationReadySet) $error("Shouldn't add to alternation ready set");
        end
    end
  endtask


  task altReceiverTest;
    begin
      channel        <= 8;
      memory.ram[8]  <= 9;
      alternationSet <= (17'b1 << 9) | alternationSet;
      reset          <= 1;

      @(posedge finished)
        begin
          reset <= 0;
          if (!shouldDescheduleSender) $error("Should deschedule receiver");
          if (!shouldScheduleReceiver) $error("Should schedule receiver");
          if (scheduleRxPid != 9) $error("Should have scheduled process 9");
          if (!addToAlternationReadySet) $error("Should have added to alternation ready set");
          if (deliveredMessage != message) $error("Didn't deliver message");
        end
    end
  endtask



  task altReceiverTest2;
    begin
      channel        <= 8;
      memory.ram[8]  <= 9;
      alternationSet <= (`CELL_COUNT_CONST_1 << 9) | alternationSet;
      alternationReadySet <= `CELL_COUNT_CONST_1 << 9;
      reset          <= 1;

      @(posedge finished)
        begin
          reset <= 0;
          if (!shouldDescheduleSender) $error("Should deschedule sender");
          if (shouldScheduleReceiver) $error("Shouldn't schedule receiver");
          if (addToAlternationReadySet) $error("Shouldn't have added to alternation ready set");
        end
    end
  endtask

  initial begin
    $dumpfile("Send_tb.vcd");
    $dumpvars(0, Send_tb);

    #3 noReceiverTest;
    #2 someReceiverTest;
    #2 altReceiverTest;
    #2 altReceiverTest2;
    #2 $finish;
  end
endmodule
module Send_tb();


  reg clk;
  always #1 clk = clk !== 1'b1;


  parameter romFile = "zeroes.hex";

  localparam addrBits = `ADDRESS_BITS;
  localparam dataBits = `DATA_BITS;

  wire [addrBits-1:0] address;
  wire [dataBits-1:0] dataIn;
  wire [dataBits-1:0] dataOut;
  wire                readWriteMode;

  IceRam #(.addrBits(addrBits), .dataBits(dataBits), .romFile(romFile)) memory (
    .clk          (clk),
    .address      (address),
    .readWriteMode(readWriteMode),
    .dataIn       (dataIn),
    .dataOut      (dataOut)
  );


  reg                reset = 0;
  reg [addrBits-1:0] channel = 0;
  reg [dataBits-1:0] message;
  reg [addrBits-1:0] txPid;
  reg [`CELL_COUNT:0] alternationSet = 17'b1011;
  reg [`CELL_COUNT:0]           alternationReadySet = 0;

  reg                finished;
  reg                shouldScheduleReceiver;
  reg                shouldDescheduleSender;
  reg [addrBits-1:0] scheduleRxPid;
  reg [dataBits-1:0] deliveredMessage;
  reg                addToAlternationReadySet;

  Send #(.addrBits(addrBits), .dataBits(dataBits)) send0 (
    .clk                     (clk),
    .reset                   (reset),
    .finished                (finished),
    .address                 (address),
    .readWriteMode           (readWriteMode),
    .dataOut                 (dataOut),
    .dataIn                  (dataIn),
    .channel                 (channel),
    .message                 (message),
    .txPid                   (txPid),
    .alternationSet          (alternationSet),
    .alternationReadySet     (alternationReadySet),
    .shouldScheduleReceiver  (shouldScheduleReceiver),
    .shouldDescheduleSender  (shouldDescheduleSender),
    .scheduleRxPid           (scheduleRxPid),
    .deliveredMessage        (deliveredMessage),
    .addToAlternationReadySet(addToAlternationReadySet)
  );


  task noReceiverTest;
    begin
      reset   <= 1;
      channel <= 2;
      message <= 42;
      txPid   <= 12;

      @(posedge finished)
        begin
          reset <= 0;
          if (!shouldDescheduleSender) $error("Should deschedule sender");
          if (shouldScheduleReceiver) $error("Shouldn't schedule receiver");
          if (deliveredMessage != message) $error("Didn't deliver message");
          if (memory.ram[channel] != {8'b0, txPid}) $error("Didn't set sending process");
          if (memory.ram[channel+1] != message) $error("Didn't set sent message");
          if (addToAlternationReadySet) $error("Shouldn't add to alternation ready set");
        end
    end
  endtask


  task someReceiverTest;
    begin
      channel       <= 4;
      memory.ram[4] <= 7;
      reset         <= 1;

      @(posedge finished)
        begin
          reset <= 0;
          if (shouldDescheduleSender) $error("Shouldn't deschedule sender");
          if (!shouldScheduleReceiver) $error("Should schedule receiver");
          if (scheduleRxPid != 7) $error("Should have scheduled process 7");
          if (deliveredMessage != message) $error("Didn't deliver message");
          if (addToAlternationReadySet) $error("Shouldn't add to alternation ready set");
        end
    end
  endtask


  task altReceiverTest;
    begin
      channel        <= 8;
      memory.ram[8]  <= 9;
      alternationSet <= (17'b1 << 9) | alternationSet;
      reset          <= 1;

      @(posedge finished)
        begin
          reset <= 0;
          if (!shouldDescheduleSender) $error("Should deschedule receiver");
          if (!shouldScheduleReceiver) $error("Should schedule receiver");
          if (scheduleRxPid != 9) $error("Should have scheduled process 9");
          if (!addToAlternationReadySet) $error("Should have added to alternation ready set");
          if (deliveredMessage != message) $error("Didn't deliver message");
        end
    end
  endtask



  task altReceiverTest2;
    begin
      channel        <= 8;
      memory.ram[8]  <= 9;
      alternationSet <= (`CELL_COUNT_CONST_1 << 9) | alternationSet;
      alternationReadySet <= `CELL_COUNT_CONST_1 << 9;
      reset          <= 1;

      @(posedge finished)
        begin
          reset <= 0;
          if (!shouldDescheduleSender) $error("Should deschedule sender");
          if (shouldScheduleReceiver) $error("Shouldn't schedule receiver");
          if (addToAlternationReadySet) $error("Shouldn't have added to alternation ready set");
        end
    end
  endtask

  initial begin
    $dumpfile("Send_tb.vcd");
    $dumpvars(0, Send_tb);

    #3 noReceiverTest;
    #2 someReceiverTest;
    #2 altReceiverTest;
    #2 altReceiverTest2;
    #2 $finish;
  end
endmodule