data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/stimulus_carry_select_adder_20b.v
 line:154: before: "+"
1: b'%Error: data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/stimulus_carry_select_adder_20b.v:1: Cannot find include file: CSA.v\n`include "CSA.v"  //                  CSA              . \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder,data/full_repos/permissive/202237519/CSA.v\n             data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder,data/full_repos/permissive/202237519/CSA.v.v\n             data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder,data/full_repos/permissive/202237519/CSA.v.sv\n             CSA.v\n             CSA.v.v\n             CSA.v.sv\n             obj_dir/CSA.v\n             obj_dir/CSA.v.v\n             obj_dir/CSA.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/stimulus_carry_select_adder_20b.v:18: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/stimulus_carry_select_adder_20b.v:22: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/stimulus_carry_select_adder_20b.v:31: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("stimulus_carry_select_adder_20b.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/stimulus_carry_select_adder_20b.v:32: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,stimulus_carry_select_adder_20b);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/stimulus_carry_select_adder_20b.v:36: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/stimulus_carry_select_adder_20b.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #(10);\n  ^\n%Error: data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/stimulus_carry_select_adder_20b.v:53: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("stimulus_carry_select_adder_20b.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/stimulus_carry_select_adder_20b.v:54: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,stimulus_carry_select_adder_20b);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/stimulus_carry_select_adder_20b.v:58: Unsupported: Ignoring delay on this delayed statement.\n #(20);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/20bits-carry-selector-adder/stimulus_carry_select_adder_20b.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #(10);\n  ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n'
module stimulus_carry_select_adder_20b;

wire [20:0] sum;
reg [19:0] a, b;
reg clk;
reg reset;

reg [19:0] mat_a_input [0:99];
reg [19:0] mat_b_input [0:99];
reg [20:0] mat_sum_output [0:99];

initial
begin
	clk <= 1;
	reset <= 0;
	#10
	reset <= 1;
end

always #5 clk <= ~clk;


CSA csa0 (.Out(sum), .A(a), .B(b), .clk(clk), .reset(reset));


integer i;
initial
begin
    $dumpfile("stimulus_carry_select_adder_20b.vcd");
    $dumpvars(0,stimulus_carry_select_adder_20b);
	$readmemh("a_input_20b.txt", mat_a_input);
	$readmemh("b_input_20b.txt", mat_b_input);
	i = 0;
	#(10);

	for(i = 0; i < 100; i++)
	begin
		a = mat_a_input[i];
		b = mat_b_input[i];
		#(10);
	end
	$finish;
end

integer k;
integer err;
reg [22:0] mat_sum;

initial
begin
    $dumpfile("stimulus_carry_select_adder_20b.vcd");
    $dumpvars(0,stimulus_carry_select_adder_20b);
	$readmemh("sum_output_20b.txt", mat_sum_output);
	err = 0;
	k = 0;
	#(20);

	for(k = 0; k < 100; k = k + 1)
	begin
		mat_sum <= mat_sum_output[k];
		if((sum != mat_sum))
			err = err + 1;
		#(10);
	end
$finish;

end


endmodule
module stimulus_carry_select_adder_20b;


wire [20:0] sum;
reg [19:0] a, b;
reg clk;
reg reset;

reg [19:0] mat_a_input [0:99];
reg [19:0] mat_b_input [0:99];
reg [20:0] mat_sum_output [0:99];

initial
begin
	clk <= 1;
	reset <= 0;
	#10
	reset <= 1;
end

always #5 clk <= ~clk;


CSA csa0 (.Out(sum), .A(a), .B(b), .clk(clk), .reset(reset));


integer i;
initial
begin
    $dumpfile("stimulus_carry_select_adder_20b.vcd");
    $dumpvars(0,stimulus_carry_select_adder_20b);
	$readmemh("a_input_20b.txt", mat_a_input);
	$readmemh("b_input_20b.txt", mat_b_input);
	i = 0;
	#(10);

	for(i = 0; i < 100; i++)
	begin
		a = mat_a_input[i];
		b = mat_b_input[i];
		#(10);
	end
	$finish;
end

integer k;
integer err;
reg [22:0] mat_sum;

initial
begin
    $dumpfile("stimulus_carry_select_adder_20b.vcd");
    $dumpvars(0,stimulus_carry_select_adder_20b);
	$readmemh("sum_output_20b.txt", mat_sum_output);
	err = 0;
	k = 0;
	#(20);

	for(k = 0; k < 100; k = k + 1)
	begin
		mat_sum <= mat_sum_output[k];
		if((sum != mat_sum))
			err = err + 1;
		#(10);
	end
$finish;

end


endmodule