data/full_repos/permissive/168395472/labs/01_adder/adder.v
'utf-8' codec can't decode byte 0xd2 in position 105: invalid continuation byte
1: b'%Warning-STMTDLY: data/full_repos/permissive/168395472/labs/01_adder/adder.v:50: Unsupported: Ignoring delay on this delayed statement.\n    a = 35; b = 62; #1 $display("a =%d, b =%d, sum =%d", a, b, s);\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/168395472/labs/01_adder/adder.v:51: Unsupported: Ignoring delay on this delayed statement.\n    a = 10; b = 16; #1 $display("a =%d, b =%d, sum =%d", a, b, s);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/168395472/labs/01_adder/adder.v:52: Unsupported: Ignoring delay on this delayed statement.\n    a = 19; b = 14; #1 $display("a =%d, b =%d, sum =%d", a, b, s);\n                    ^\n%Warning-PINMISSING: data/full_repos/permissive/168395472/labs/01_adder/adder.v:34: Cell has missing pin: \'carry_out\'\nadder adder7(.a(a[7]), .b(b[7]), .carry_in(c6), .sum(sum[7]));\n      ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/168395472/labs/01_adder/adder.v:27: Signal definition not found, creating implicitly: \'c0\'\nadder adder0(.a(a[0]), .b(b[0]), .carry_in(1\'b0), .sum(sum[0]), .carry_out(c0));\n                                                                           ^~\n%Warning-IMPLICIT: data/full_repos/permissive/168395472/labs/01_adder/adder.v:28: Signal definition not found, creating implicitly: \'c1\'\n                                                                                : ... Suggested alternative: \'c0\'\nadder adder1(.a(a[1]), .b(b[1]), .carry_in(c0), .sum(sum[1]), .carry_out(c1));\n                                                                         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/168395472/labs/01_adder/adder.v:29: Signal definition not found, creating implicitly: \'c2\'\n                                                                                : ... Suggested alternative: \'c0\'\nadder adder2(.a(a[2]), .b(b[2]), .carry_in(c1), .sum(sum[2]), .carry_out(c2));\n                                                                         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/168395472/labs/01_adder/adder.v:30: Signal definition not found, creating implicitly: \'c3\'\n                                                                                : ... Suggested alternative: \'c0\'\nadder adder3(.a(a[3]), .b(b[3]), .carry_in(c2), .sum(sum[3]), .carry_out(c3));\n                                                                         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/168395472/labs/01_adder/adder.v:31: Signal definition not found, creating implicitly: \'c4\'\n                                                                                : ... Suggested alternative: \'c0\'\nadder adder4(.a(a[4]), .b(b[4]), .carry_in(c3), .sum(sum[4]), .carry_out(c4));\n                                                                         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/168395472/labs/01_adder/adder.v:32: Signal definition not found, creating implicitly: \'c5\'\n                                                                                : ... Suggested alternative: \'c0\'\nadder adder5(.a(a[5]), .b(b[5]), .carry_in(c4), .sum(sum[5]), .carry_out(c5));\n                                                                         ^~\n%Warning-IMPLICIT: data/full_repos/permissive/168395472/labs/01_adder/adder.v:33: Signal definition not found, creating implicitly: \'c6\'\n                                                                                : ... Suggested alternative: \'c0\'\nadder adder6(.a(a[6]), .b(b[6]), .carry_in(c5), .sum(sum[6]), .carry_out(c6));\n                                                                         ^~\n%Error: Exiting due to 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder8(
    input [7:0]a,
    input [7:0]b,
    output [7:0]sum
);

adder adder0(.a(a[0]), .b(b[0]), .carry_in(1'b0), .sum(sum[0]), .carry_out(c0));
adder adder1(.a(a[1]), .b(b[1]), .carry_in(c0), .sum(sum[1]), .carry_out(c1));
adder adder2(.a(a[2]), .b(b[2]), .carry_in(c1), .sum(sum[2]), .carry_out(c2));
adder adder3(.a(a[3]), .b(b[3]), .carry_in(c2), .sum(sum[3]), .carry_out(c3));
adder adder4(.a(a[4]), .b(b[4]), .carry_in(c3), .sum(sum[4]), .carry_out(c4));
adder adder5(.a(a[5]), .b(b[5]), .carry_in(c4), .sum(sum[5]), .carry_out(c5));
adder adder6(.a(a[6]), .b(b[6]), .carry_in(c5), .sum(sum[6]), .carry_out(c6));
adder adder7(.a(a[7]), .b(b[7]), .carry_in(c6), .sum(sum[7]));

endmodule
module adder8(
    input [7:0]a,
    input [7:0]b,
    output [7:0]sum
);


adder adder0(.a(a[0]), .b(b[0]), .carry_in(1'b0), .sum(sum[0]), .carry_out(c0));
adder adder1(.a(a[1]), .b(b[1]), .carry_in(c0), .sum(sum[1]), .carry_out(c1));
adder adder2(.a(a[2]), .b(b[2]), .carry_in(c1), .sum(sum[2]), .carry_out(c2));
adder adder3(.a(a[3]), .b(b[3]), .carry_in(c2), .sum(sum[3]), .carry_out(c3));
adder adder4(.a(a[4]), .b(b[4]), .carry_in(c3), .sum(sum[4]), .carry_out(c4));
adder adder5(.a(a[5]), .b(b[5]), .carry_in(c4), .sum(sum[5]), .carry_out(c5));
adder adder6(.a(a[6]), .b(b[6]), .carry_in(c5), .sum(sum[6]), .carry_out(c6));
adder adder7(.a(a[7]), .b(b[7]), .carry_in(c6), .sum(sum[7]));

endmodule