data/full_repos/permissive/114553631/test/test_srcB.v
 line:49: before: "$"
1: b'%Error: data/full_repos/permissive/114553631/test/test_srcB.v:6: Cannot find include file: ../src/srcB.v\n`include "../src/srcB.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/srcB.v\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/srcB.v.v\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/srcB.v.sv\n             ../src/srcB.v\n             ../src/srcB.v.v\n             ../src/srcB.v.sv\n             obj_dir/../src/srcB.v\n             obj_dir/../src/srcB.v.v\n             obj_dir/../src/srcB.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:17: Unsupported: Ignoring delay on this delayed statement.\n initial #stop_time $finish;    \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:21: Define or directive not defined: \'`IROP\'\n        D_op = `IROP;\n               ^~~~~\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:21: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        D_op = `IROP;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:24: Define or directive not defined: \'`IJ\'\n        D_op = `IJ;\n               ^~~\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        D_op = `IJ;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:27: Define or directive not defined: \'`ISW\'\n        D_op = `ISW;\n               ^~~~\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        D_op = `ISW;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:31: Define or directive not defined: \'`IROP\'\n        D_op = `IROP;\n               ^~~~~\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:31: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        D_op = `IROP;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:37: Unsupported or unknown PLI call: $monitor\n    $monitor("time = ", $time, " op=%b rs=%d srcB=%d", D_op, D_rs, d_srcB);              \n    ^~~~~~~~\n%Error: Exiting due to 10 error(s), 7 warning(s)\n'
module test_srcB;
    reg [5:0] D_op = 0;
    reg [4:0] D_rs = 0;
    wire [4:0] d_srcB;

    parameter stop_time = 80;

    srcB SRCB(d_srcB, D_op, D_rs);

	initial #stop_time $finish;    
    
    initial begin
        #10;
        D_op = `IROP;
        D_rs = 5'b10011;
        #10;
        D_op = `IJ;
        D_rs = 5'b10000;
        #10;
        D_op = `ISW;
        #10;
        D_rs = 5'b10010;
        #10;
        D_op = `IROP;
        D_rs = 5'b01011;
        #10;
    end

    initial begin
	  	$monitor("time = ", $time, " op=%b rs=%d srcB=%d", D_op, D_rs, d_srcB);              
    end
endmodule
module test_srcB;

    reg [5:0] D_op = 0;
    reg [4:0] D_rs = 0;
    wire [4:0] d_srcB;

    parameter stop_time = 80;

    srcB SRCB(d_srcB, D_op, D_rs);

	initial #stop_time $finish;    
    
    initial begin
        #10;
        D_op = `IROP;
        D_rs = 5'b10011;
        #10;
        D_op = `IJ;
        D_rs = 5'b10000;
        #10;
        D_op = `ISW;
        #10;
        D_rs = 5'b10010;
        #10;
        D_op = `IROP;
        D_rs = 5'b01011;
        #10;
    end

    initial begin
	  	$monitor("time = ", $time, " op=%b rs=%d srcB=%d", D_op, D_rs, d_srcB);              
    end
endmodule