data/full_repos/permissive/119758565/HACK.v
1: b"%Error: data/full_repos/permissive/119758565/HACK.v:42: syntax error, unexpected '(', expecting IDENTIFIER\norGate(rst, ROMLoad, ResetCPU);\n       ^~~\n%Error: Exiting due to 1 error(s)\n"
module HACK(
    input [14:0] ROMAddressLineCtl,
	 input [15:0] ROMDataLine,
	 input ROMLoad,
	 input rst,
	 input clk,
	 output [14:0] PCout,
	 output [15:0] RAMOut,
	 output [15:0] DOut,
	 output CtoAReg
    );

reg [14:0] ROMAddressLine;
wire [15:0] ROMOut;
wire [14:0] PC;
wire [15:0] RAMDataLine;
wire [14:0] RAMAddressLine;
wire RAMLoad;
wire [15:0] RAMOut;
wire ResetCPU;

orGate(rst, ROMLoad, ResetCPU);
RAM16K ROM (.data(ROMDataLine), .clk(clk), .address(ROMAddressLine), .out(ROMOut), .load(ROMLoad));
RAM16K RAM (.data(RAMDataLine), .clk(~clk), .address(RAMAddressLine), .out(RAMOut), .load(RAMLoad));

CPU HACK (.clk(clk), .rst(ResetCPU), .inM(RAMOut), .outM(RAMDataLine), .writeM(RAMLoad),
 .instruction(ROMOut), .pc(PC), .OutR(DOut), .addressM(RAMAddressLine));
 
always @(PC or ROMLoad)
begin
  if (~ROMLoad)
  begin
    ROMAddressLine <= PC;
  end
  else
  begin
    ROMAddressLine <= ROMAddressLineCtl;
  end
end

assign PCout = ROMAddressLine;
endmodule
module HACK(
    input [14:0] ROMAddressLineCtl,
	 input [15:0] ROMDataLine,
	 input ROMLoad,
	 input rst,
	 input clk,
	 output [14:0] PCout,
	 output [15:0] RAMOut,
	 output [15:0] DOut,
	 output CtoAReg
    );


reg [14:0] ROMAddressLine;
wire [15:0] ROMOut;
wire [14:0] PC;
wire [15:0] RAMDataLine;
wire [14:0] RAMAddressLine;
wire RAMLoad;
wire [15:0] RAMOut;
wire ResetCPU;

orGate(rst, ROMLoad, ResetCPU);
RAM16K ROM (.data(ROMDataLine), .clk(clk), .address(ROMAddressLine), .out(ROMOut), .load(ROMLoad));
RAM16K RAM (.data(RAMDataLine), .clk(~clk), .address(RAMAddressLine), .out(RAMOut), .load(RAMLoad));

CPU HACK (.clk(clk), .rst(ResetCPU), .inM(RAMOut), .outM(RAMDataLine), .writeM(RAMLoad),
 .instruction(ROMOut), .pc(PC), .OutR(DOut), .addressM(RAMAddressLine));
 
always @(PC or ROMLoad)
begin
  if (~ROMLoad)
  begin
    ROMAddressLine <= PC;
  end
  else
  begin
    ROMAddressLine <= ROMAddressLineCtl;
  end
end

assign PCout = ROMAddressLine;
endmodule