data/full_repos/permissive/147265957/src/msubtractor.v
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data/verilator_xmls/85c60ac0-6911-44a2-888d-84488dfc59b0.xml
module msubtractor(
    moneyv, subsig, leftv
);
    input [7:0] moneyv;
    input subsig;
    output reg [7:0] leftv;
    always @(moneyv, subsig) begin
        if(subsig) leftv = moneyv - 10;
        else leftv = moneyv - 5;
    end
endmodule
module msubtractor(
    moneyv, subsig, leftv
);

    input [7:0] moneyv;
    input subsig;
    output reg [7:0] leftv;
    always @(moneyv, subsig) begin
        if(subsig) leftv = moneyv - 10;
        else leftv = moneyv - 5;
    end
endmodule