data/full_repos/permissive/143278/ivltests/sdw_lvalconcat2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdw_lvalconcat2.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1 if( (a !== 0) & (b !== 0))\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdw_lvalconcat2.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #1 if( (a !== 0) & (b !== 1))\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdw_lvalconcat2.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #1 if( (a !== 1) & (b !== 0))\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdw_lvalconcat2.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #1 if( (a !== 1) & (b !== 1))\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sdw_lvalconcat2.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #1 if(working)\n    ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ();
wire a, b;
reg [1:0] c;
reg working;

assign {a,b} = c;

initial
begin
    working = 1;
    c = 2'b00 ;

    #1 if( (a !== 0) & (b !== 0))
       begin
         $display("FAILED - {a,b} Expected 2'b00 - received %b%b",a,b);
          working = 0;
       end

    c = 2'b01 ;

    #1 if( (a !== 0) & (b !== 1))
       begin
         $display("FAILED {a,b} Expected 2'b01 - received %b%b",a,b);
         working = 0;
       end

    c = 2'b10 ;

    #1 if( (a !== 1) & (b !== 0))
       begin
         $display("FAILED {a,b} Expected 2'b10 - received %b%b",a,b);
         working = 0;
       end

    c = 2'b11 ;

    #1 if( (a !== 1) & (b !== 1))
       begin
         $display("FAILED {a,b} Expected 2'b11 - received %b%b",a,b);
         working = 0;
       end

    #1 if(working)
       $display("PASSED\n");

end

endmodule
module main ();

wire a, b;
reg [1:0] c;
reg working;

assign {a,b} = c;

initial
begin
    working = 1;
    c = 2'b00 ;

    #1 if( (a !== 0) & (b !== 0))
       begin
         $display("FAILED - {a,b} Expected 2'b00 - received %b%b",a,b);
          working = 0;
       end

    c = 2'b01 ;

    #1 if( (a !== 0) & (b !== 1))
       begin
         $display("FAILED {a,b} Expected 2'b01 - received %b%b",a,b);
         working = 0;
       end

    c = 2'b10 ;

    #1 if( (a !== 1) & (b !== 0))
       begin
         $display("FAILED {a,b} Expected 2'b10 - received %b%b",a,b);
         working = 0;
       end

    c = 2'b11 ;

    #1 if( (a !== 1) & (b !== 1))
       begin
         $display("FAILED {a,b} Expected 2'b11 - received %b%b",a,b);
         working = 0;
       end

    #1 if(working)
       $display("PASSED\n");

end

endmodule