data/full_repos/permissive/211316121/lab3_1/sim_1/new/sim_fullAdder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_1/sim_1/new/sim_fullAdder.v:31: Unsupported: Ignoring delay on this delayed statement.\n            #10  x=0;y=0;z=1;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_1/sim_1/new/sim_fullAdder.v:32: Unsupported: Ignoring delay on this delayed statement.\n            #10  x=0;y=1;z=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_1/sim_1/new/sim_fullAdder.v:33: Unsupported: Ignoring delay on this delayed statement.\n            #10  x=0;y=1;z=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_1/sim_1/new/sim_fullAdder.v:34: Unsupported: Ignoring delay on this delayed statement.\n            #10  x=1;y=0;z=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_1/sim_1/new/sim_fullAdder.v:35: Unsupported: Ignoring delay on this delayed statement.\n            #10  x=1;y=0;z=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_1/sim_1/new/sim_fullAdder.v:36: Unsupported: Ignoring delay on this delayed statement.\n            #10  x=1;y=1;z=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211316121/lab3_1/sim_1/new/sim_fullAdder.v:37: Unsupported: Ignoring delay on this delayed statement.\n            #10  x=1;y=1;z=1;\n            ^\n%Error: data/full_repos/permissive/211316121/lab3_1/sim_1/new/sim_fullAdder.v:39: Cannot find file containing module: \'fullAdder\'\n    fullAdder sim(x,y,z,s,c);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211316121/lab3_1/sim_1/new,data/full_repos/permissive/211316121/fullAdder\n             data/full_repos/permissive/211316121/lab3_1/sim_1/new,data/full_repos/permissive/211316121/fullAdder.v\n             data/full_repos/permissive/211316121/lab3_1/sim_1/new,data/full_repos/permissive/211316121/fullAdder.sv\n             fullAdder\n             fullAdder.v\n             fullAdder.sv\n             obj_dir/fullAdder\n             obj_dir/fullAdder.v\n             obj_dir/fullAdder.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_fullAdder(

    );
    reg x,y,z;
    wire s,c;
    initial
        begin
                 x=0;y=0;z=0;
            #10  x=0;y=0;z=1;
            #10  x=0;y=1;z=0;
            #10  x=0;y=1;z=1;
            #10  x=1;y=0;z=0;
            #10  x=1;y=0;z=1;
            #10  x=1;y=1;z=0;
            #10  x=1;y=1;z=1;
        end
    fullAdder sim(x,y,z,s,c);
endmodule
module sim_fullAdder(

    );

    reg x,y,z;
    wire s,c;
    initial
        begin
                 x=0;y=0;z=0;
            #10  x=0;y=0;z=1;
            #10  x=0;y=1;z=0;
            #10  x=0;y=1;z=1;
            #10  x=1;y=0;z=0;
            #10  x=1;y=0;z=1;
            #10  x=1;y=1;z=0;
            #10  x=1;y=1;z=1;
        end
    fullAdder sim(x,y,z,s,c);
endmodule