data/full_repos/permissive/125927162/PIPO/pipo.v
data/verilator_xmls/a8806969-a23d-44a8-a338-af447bdc515b.xml
module pipo (oe_n, le, in, out);
   parameter WIDTH = 8;
   input oe_n;
   input le;
   input [WIDTH-1:0] in;
   output [WIDTH-1:0] out;

   reg [WIDTH-1:0]    data;
   wire [WIDTH-1:0]   mux;
   
   assign mux = (le)? in : data;
   assign out = (~oe_n)? mux : {WIDTH {{1'bZ}}};
   
   always@(negedge le)
     data <= in;

endmodule
module pipo (oe_n, le, in, out);

   parameter WIDTH = 8;
   input oe_n;
   input le;
   input [WIDTH-1:0] in;
   output [WIDTH-1:0] out;

   reg [WIDTH-1:0]    data;
   wire [WIDTH-1:0]   mux;
   
   assign mux = (le)? in : data;
   assign out = (~oe_n)? mux : {WIDTH {{1'bZ}}};
   
   always@(negedge le)
     data <= in;

endmodule