data/full_repos/permissive/125927162/MEMMUX/MEMMUX.v
data/verilator_xmls/672e3557-d0d9-4abb-af5e-9b496a820a0a.xml
module memmux(switch, mADDR_M, mDATA_M, mADDR_V, mDATA_V, sADDR_A, sDATA_A, sADDR_B, sDATA_B);
   parameter ADDR_WIDTH = 8;
   parameter DATA_WIDTH = 8;


   input switch;
   input [ADDR_WIDTH - 1:0]  mADDR_M;
   input [DATA_WIDTH - 1:0]  mDATA_M;
   input [ADDR_WIDTH - 1:0]  mADDR_V;
   output [DATA_WIDTH - 1:0] mDATA_V;


   output [ADDR_WIDTH - 1:0] sADDR_A;
   inout [DATA_WIDTH - 1:0]  sDATA_A;
   output [ADDR_WIDTH - 1:0] sADDR_B;
   inout [DATA_WIDTH - 1:0]  sDATA_B;
   
   assign mDATA_V = switch ? sDATA_B : sDATA_A;

   assign sDATA_A = switch ? mDATA_M : {DATA_WIDTH{1'bZ}};
   assign sDATA_B = !switch ? mDATA_M : {DATA_WIDTH{1'bZ}};
   assign sADDR_A = switch ? mADDR_M : mADDR_V;
   assign sADDR_B = !switch ? mADDR_M : mADDR_V;


endmodule
module memmux(switch, mADDR_M, mDATA_M, mADDR_V, mDATA_V, sADDR_A, sDATA_A, sADDR_B, sDATA_B);

   parameter ADDR_WIDTH = 8;
   parameter DATA_WIDTH = 8;


   input switch;
   input [ADDR_WIDTH - 1:0]  mADDR_M;
   input [DATA_WIDTH - 1:0]  mDATA_M;
   input [ADDR_WIDTH - 1:0]  mADDR_V;
   output [DATA_WIDTH - 1:0] mDATA_V;


   output [ADDR_WIDTH - 1:0] sADDR_A;
   inout [DATA_WIDTH - 1:0]  sDATA_A;
   output [ADDR_WIDTH - 1:0] sADDR_B;
   inout [DATA_WIDTH - 1:0]  sDATA_B;
   
   assign mDATA_V = switch ? sDATA_B : sDATA_A;

   assign sDATA_A = switch ? mDATA_M : {DATA_WIDTH{1'bZ}};
   assign sDATA_B = !switch ? mDATA_M : {DATA_WIDTH{1'bZ}};
   assign sADDR_A = switch ? mADDR_M : mADDR_V;
   assign sADDR_B = !switch ? mADDR_M : mADDR_V;


endmodule