data/full_repos/permissive/159001439/src/net_csum.v
 line:15: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/159001439/src/net_csum.v:19: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                      : ... In instance net_csum\n  cyclic_carry_add = sum[15:0] + sum[16];\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/net_csum.v:93: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                      : ... In instance net_csum\n  sum_2 <= 32\'b0;\n        ^~\n%Error: Exiting due to 2 warning(s)\n'
function [15:0] cyclic_carry_add(input [15:0] a, input [15:0] b);
	reg [16:0] sum;
	begin
		sum = a + b;
		cyclic_carry_add = sum[15:0] + sum[16];
	end
endfunction
function [15:0] cyclic_carry_add(input [15:0] a, input [15:0] b);

	reg [16:0] sum;
	begin
		sum = a + b;
		cyclic_carry_add = sum[15:0] + sum[16];
	end
endfunction