data/full_repos/permissive/107499099/mips_de2-115/MIPS/registers.v
'utf-8' codec can't decode byte 0xc6 in position 590: invalid continuation byte
data/verilator_xmls/ea86482c-601b-4fb7-8c99-9489d1f140bb.xml
module registers (clock, reset,
		  reg_read_idx1, reg_read_idx2,
		  reg_write_idx, reg_write_enable, reg_write_data,
		  reg_read_data1, reg_read_data2);

  input               clock, reset;
  input   [4:0]       reg_read_idx1;
  input   [4:0]       reg_read_idx2;
  input   [4:0]       reg_write_idx;
  input               reg_write_enable;
  input  [31:0]       reg_write_data;
  output [31:0]       reg_read_data1;
  output [31:0]       reg_read_data2;



  reg [31:0] regs_1;
  reg [31:0] regs_2;
  reg [31:0] regs_3;
  reg [31:0] regs_4;
  reg [31:0] regs_5;
  reg [31:0] regs_6;
  reg [31:0] regs_7;
  reg [31:0] regs_8;
  reg [31:0] regs_9;
  reg [31:0] regs_10;
  reg [31:0] regs_11;
  reg [31:0] regs_12;
  reg [31:0] regs_13;
  reg [31:0] regs_14;
  reg [31:0] regs_15;
  reg [31:0] regs_16;
  reg [31:0] regs_17;
  reg [31:0] regs_18;
  reg [31:0] regs_19;
  reg [31:0] regs_20;
  reg [31:0] regs_21;
  reg [31:0] regs_22;
  reg [31:0] regs_23;
  reg [31:0] regs_24;
  reg [31:0] regs_25;
  reg [31:0] regs_26;
  reg [31:0] regs_27;
  reg [31:0] regs_28;
  reg [31:0] regs_29;
  reg [31:0] regs_30;
  reg [31:0] regs_31;





  assign reg_read_data1 = (reg_read_idx1 == 5'b00000) ? 0 : (
    (reg_read_idx1 == 5'b00001) ? regs_1 : (
    (reg_read_idx1 == 5'b00010) ? regs_2 : (
    (reg_read_idx1 == 5'b00011) ? regs_3 : (
    (reg_read_idx1 == 5'b00100) ? regs_4 : (
    (reg_read_idx1 == 5'b00101) ? regs_5 : (
    (reg_read_idx1 == 5'b00110) ? regs_6 : (
    (reg_read_idx1 == 5'b00111) ? regs_7 : (
    (reg_read_idx1 == 5'b01000) ? regs_8 : (
    (reg_read_idx1 == 5'b01001) ? regs_9 : (
    (reg_read_idx1 == 5'b01010) ? regs_10 : (
    (reg_read_idx1 == 5'b01011) ? regs_11 : (
    (reg_read_idx1 == 5'b01100) ? regs_12 : (
    (reg_read_idx1 == 5'b01101) ? regs_13 : (
    (reg_read_idx1 == 5'b01110) ? regs_14 : (
    (reg_read_idx1 == 5'b01111) ? regs_15 : (
    (reg_read_idx1 == 5'b10000) ? regs_16 : (
    (reg_read_idx1 == 5'b10001) ? regs_17 : (
    (reg_read_idx1 == 5'b10010) ? regs_18 : (
    (reg_read_idx1 == 5'b10011) ? regs_19 : (
    (reg_read_idx1 == 5'b10100) ? regs_20 : (
    (reg_read_idx1 == 5'b10101) ? regs_21 : (
    (reg_read_idx1 == 5'b10110) ? regs_22 : (
    (reg_read_idx1 == 5'b10111) ? regs_23 : (
    (reg_read_idx1 == 5'b11000) ? regs_24 : (
    (reg_read_idx1 == 5'b11001) ? regs_25 : (
    (reg_read_idx1 == 5'b11010) ? regs_26 : (
    (reg_read_idx1 == 5'b11011) ? regs_27 : (
    (reg_read_idx1 == 5'b11100) ? regs_28 : (
    (reg_read_idx1 == 5'b11101) ? regs_29 : (
    (reg_read_idx1 == 5'b11110) ? regs_30 : (regs_31)))))))))))))))
))))))))))))))));





  assign reg_read_data2 = (reg_read_idx2 == 5'b00000) ? 0 : (
    (reg_read_idx2 == 5'b00001) ? regs_1 : (
    (reg_read_idx2 == 5'b00010) ? regs_2 : (
    (reg_read_idx2 == 5'b00011) ? regs_3 : (
    (reg_read_idx2 == 5'b00100) ? regs_4 : (
    (reg_read_idx2 == 5'b00101) ? regs_5 : (
    (reg_read_idx2 == 5'b00110) ? regs_6 : (
    (reg_read_idx2 == 5'b00111) ? regs_7 : (
    (reg_read_idx2 == 5'b01000) ? regs_8 : (
    (reg_read_idx2 == 5'b01001) ? regs_9 : (
    (reg_read_idx2 == 5'b01010) ? regs_10 : (
    (reg_read_idx2 == 5'b01011) ? regs_11 : (
    (reg_read_idx2 == 5'b01100) ? regs_12 : (
    (reg_read_idx2 == 5'b01101) ? regs_13 : (
    (reg_read_idx2 == 5'b01110) ? regs_14 : (
    (reg_read_idx2 == 5'b01111) ? regs_15 : (
    (reg_read_idx2 == 5'b10000) ? regs_16 : (
    (reg_read_idx2 == 5'b10001) ? regs_17 : (
    (reg_read_idx2 == 5'b10010) ? regs_18 : (
    (reg_read_idx2 == 5'b10011) ? regs_19 : (
    (reg_read_idx2 == 5'b10100) ? regs_20 : (
    (reg_read_idx2 == 5'b10101) ? regs_21 : (
    (reg_read_idx2 == 5'b10110) ? regs_22 : (
    (reg_read_idx2 == 5'b10111) ? regs_23 : (
    (reg_read_idx2 == 5'b11000) ? regs_24 : (
    (reg_read_idx2 == 5'b11001) ? regs_25 : (
    (reg_read_idx2 == 5'b11010) ? regs_26 : (
    (reg_read_idx2 == 5'b11011) ? regs_27 : (
    (reg_read_idx2 == 5'b11100) ? regs_28 : (
    (reg_read_idx2 == 5'b11101) ? regs_29 : (
    (reg_read_idx2 == 5'b11110) ? regs_30 : (regs_31)))))))))))))))
))))))))))))))));





  always @(posedge clock or negedge reset) begin
    if (reset == 1'b0) begin
       regs_1 <= 0;
       regs_2 <= 0;
       regs_3 <= 0;
       regs_4 <= 0;
       regs_5 <= 0;
       regs_6 <= 0;
       regs_7 <= 0;
       regs_8 <= 0;
       regs_9 <= 0;
      regs_10 <= 0;
      regs_11 <= 0;
      regs_12 <= 0;
      regs_13 <= 0;
      regs_14 <= 0;
      regs_15 <= 0;
      regs_16 <= 0;
      regs_17 <= 0;
      regs_18 <= 0;
      regs_19 <= 0;
      regs_20 <= 0;
      regs_21 <= 0;
      regs_22 <= 0;
      regs_23 <= 0;
      regs_24 <= 0;
      regs_25 <= 0;
      regs_26 <= 0;
      regs_27 <= 0;
      regs_28 <= 0;
      regs_29 <= 0;
      regs_30 <= 0;
      regs_31 <= 0;
    end else begin
    if (reg_write_enable == 1'b1) begin




      if (reg_write_idx == 5'b00001) begin
        regs_1 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b00010) begin
        regs_2 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b00011) begin
        regs_3 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b00100) begin
        regs_4 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b00101) begin
        regs_5 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b00110) begin
        regs_6 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b00111) begin
        regs_7 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01000) begin
        regs_8 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01001) begin
        regs_9 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01010) begin
        regs_10 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01011) begin
        regs_11 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01100) begin
        regs_12 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01101) begin
        regs_13 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01110) begin
        regs_14 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01111) begin
        regs_15 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10000) begin
        regs_16 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10001) begin
        regs_17 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10010) begin
        regs_18 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10011) begin
        regs_19 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10100) begin
        regs_20 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10101) begin
        regs_21 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10110) begin
        regs_22 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10111) begin
        regs_23 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11000) begin
        regs_24 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11001) begin
        regs_25 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11010) begin
        regs_26 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11011) begin
        regs_27 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11100) begin
        regs_28 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11101) begin
        regs_29 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11110) begin
        regs_30 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11111) begin
        regs_31 <= reg_write_data;
      end    
      end    
    end
  end

endmodule
module registers (clock, reset,
		  reg_read_idx1, reg_read_idx2,
		  reg_write_idx, reg_write_enable, reg_write_data,
		  reg_read_data1, reg_read_data2);


  input               clock, reset;
  input   [4:0]       reg_read_idx1;
  input   [4:0]       reg_read_idx2;
  input   [4:0]       reg_write_idx;
  input               reg_write_enable;
  input  [31:0]       reg_write_data;
  output [31:0]       reg_read_data1;
  output [31:0]       reg_read_data2;



  reg [31:0] regs_1;
  reg [31:0] regs_2;
  reg [31:0] regs_3;
  reg [31:0] regs_4;
  reg [31:0] regs_5;
  reg [31:0] regs_6;
  reg [31:0] regs_7;
  reg [31:0] regs_8;
  reg [31:0] regs_9;
  reg [31:0] regs_10;
  reg [31:0] regs_11;
  reg [31:0] regs_12;
  reg [31:0] regs_13;
  reg [31:0] regs_14;
  reg [31:0] regs_15;
  reg [31:0] regs_16;
  reg [31:0] regs_17;
  reg [31:0] regs_18;
  reg [31:0] regs_19;
  reg [31:0] regs_20;
  reg [31:0] regs_21;
  reg [31:0] regs_22;
  reg [31:0] regs_23;
  reg [31:0] regs_24;
  reg [31:0] regs_25;
  reg [31:0] regs_26;
  reg [31:0] regs_27;
  reg [31:0] regs_28;
  reg [31:0] regs_29;
  reg [31:0] regs_30;
  reg [31:0] regs_31;





  assign reg_read_data1 = (reg_read_idx1 == 5'b00000) ? 0 : (
    (reg_read_idx1 == 5'b00001) ? regs_1 : (
    (reg_read_idx1 == 5'b00010) ? regs_2 : (
    (reg_read_idx1 == 5'b00011) ? regs_3 : (
    (reg_read_idx1 == 5'b00100) ? regs_4 : (
    (reg_read_idx1 == 5'b00101) ? regs_5 : (
    (reg_read_idx1 == 5'b00110) ? regs_6 : (
    (reg_read_idx1 == 5'b00111) ? regs_7 : (
    (reg_read_idx1 == 5'b01000) ? regs_8 : (
    (reg_read_idx1 == 5'b01001) ? regs_9 : (
    (reg_read_idx1 == 5'b01010) ? regs_10 : (
    (reg_read_idx1 == 5'b01011) ? regs_11 : (
    (reg_read_idx1 == 5'b01100) ? regs_12 : (
    (reg_read_idx1 == 5'b01101) ? regs_13 : (
    (reg_read_idx1 == 5'b01110) ? regs_14 : (
    (reg_read_idx1 == 5'b01111) ? regs_15 : (
    (reg_read_idx1 == 5'b10000) ? regs_16 : (
    (reg_read_idx1 == 5'b10001) ? regs_17 : (
    (reg_read_idx1 == 5'b10010) ? regs_18 : (
    (reg_read_idx1 == 5'b10011) ? regs_19 : (
    (reg_read_idx1 == 5'b10100) ? regs_20 : (
    (reg_read_idx1 == 5'b10101) ? regs_21 : (
    (reg_read_idx1 == 5'b10110) ? regs_22 : (
    (reg_read_idx1 == 5'b10111) ? regs_23 : (
    (reg_read_idx1 == 5'b11000) ? regs_24 : (
    (reg_read_idx1 == 5'b11001) ? regs_25 : (
    (reg_read_idx1 == 5'b11010) ? regs_26 : (
    (reg_read_idx1 == 5'b11011) ? regs_27 : (
    (reg_read_idx1 == 5'b11100) ? regs_28 : (
    (reg_read_idx1 == 5'b11101) ? regs_29 : (
    (reg_read_idx1 == 5'b11110) ? regs_30 : (regs_31)))))))))))))))
))))))))))))))));





  assign reg_read_data2 = (reg_read_idx2 == 5'b00000) ? 0 : (
    (reg_read_idx2 == 5'b00001) ? regs_1 : (
    (reg_read_idx2 == 5'b00010) ? regs_2 : (
    (reg_read_idx2 == 5'b00011) ? regs_3 : (
    (reg_read_idx2 == 5'b00100) ? regs_4 : (
    (reg_read_idx2 == 5'b00101) ? regs_5 : (
    (reg_read_idx2 == 5'b00110) ? regs_6 : (
    (reg_read_idx2 == 5'b00111) ? regs_7 : (
    (reg_read_idx2 == 5'b01000) ? regs_8 : (
    (reg_read_idx2 == 5'b01001) ? regs_9 : (
    (reg_read_idx2 == 5'b01010) ? regs_10 : (
    (reg_read_idx2 == 5'b01011) ? regs_11 : (
    (reg_read_idx2 == 5'b01100) ? regs_12 : (
    (reg_read_idx2 == 5'b01101) ? regs_13 : (
    (reg_read_idx2 == 5'b01110) ? regs_14 : (
    (reg_read_idx2 == 5'b01111) ? regs_15 : (
    (reg_read_idx2 == 5'b10000) ? regs_16 : (
    (reg_read_idx2 == 5'b10001) ? regs_17 : (
    (reg_read_idx2 == 5'b10010) ? regs_18 : (
    (reg_read_idx2 == 5'b10011) ? regs_19 : (
    (reg_read_idx2 == 5'b10100) ? regs_20 : (
    (reg_read_idx2 == 5'b10101) ? regs_21 : (
    (reg_read_idx2 == 5'b10110) ? regs_22 : (
    (reg_read_idx2 == 5'b10111) ? regs_23 : (
    (reg_read_idx2 == 5'b11000) ? regs_24 : (
    (reg_read_idx2 == 5'b11001) ? regs_25 : (
    (reg_read_idx2 == 5'b11010) ? regs_26 : (
    (reg_read_idx2 == 5'b11011) ? regs_27 : (
    (reg_read_idx2 == 5'b11100) ? regs_28 : (
    (reg_read_idx2 == 5'b11101) ? regs_29 : (
    (reg_read_idx2 == 5'b11110) ? regs_30 : (regs_31)))))))))))))))
))))))))))))))));





  always @(posedge clock or negedge reset) begin
    if (reset == 1'b0) begin
       regs_1 <= 0;
       regs_2 <= 0;
       regs_3 <= 0;
       regs_4 <= 0;
       regs_5 <= 0;
       regs_6 <= 0;
       regs_7 <= 0;
       regs_8 <= 0;
       regs_9 <= 0;
      regs_10 <= 0;
      regs_11 <= 0;
      regs_12 <= 0;
      regs_13 <= 0;
      regs_14 <= 0;
      regs_15 <= 0;
      regs_16 <= 0;
      regs_17 <= 0;
      regs_18 <= 0;
      regs_19 <= 0;
      regs_20 <= 0;
      regs_21 <= 0;
      regs_22 <= 0;
      regs_23 <= 0;
      regs_24 <= 0;
      regs_25 <= 0;
      regs_26 <= 0;
      regs_27 <= 0;
      regs_28 <= 0;
      regs_29 <= 0;
      regs_30 <= 0;
      regs_31 <= 0;
    end else begin
    if (reg_write_enable == 1'b1) begin




      if (reg_write_idx == 5'b00001) begin
        regs_1 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b00010) begin
        regs_2 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b00011) begin
        regs_3 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b00100) begin
        regs_4 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b00101) begin
        regs_5 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b00110) begin
        regs_6 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b00111) begin
        regs_7 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01000) begin
        regs_8 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01001) begin
        regs_9 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01010) begin
        regs_10 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01011) begin
        regs_11 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01100) begin
        regs_12 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01101) begin
        regs_13 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01110) begin
        regs_14 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b01111) begin
        regs_15 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10000) begin
        regs_16 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10001) begin
        regs_17 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10010) begin
        regs_18 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10011) begin
        regs_19 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10100) begin
        regs_20 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10101) begin
        regs_21 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10110) begin
        regs_22 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b10111) begin
        regs_23 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11000) begin
        regs_24 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11001) begin
        regs_25 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11010) begin
        regs_26 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11011) begin
        regs_27 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11100) begin
        regs_28 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11101) begin
        regs_29 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11110) begin
        regs_30 <= reg_write_data;
      end    
      if (reg_write_idx == 5'b11111) begin
        regs_31 <= reg_write_data;
      end    
      end    
    end
  end

endmodule