data/full_repos/permissive/189158922/verilog_src/axihp_writer.v
 line:221: before: "*"
1: b'%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/axihp_writer.v:235: Operator NEQ expects 4 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance top\n  assign \\$36  = active != (* src = "axihp_writer.py:139" *) 1\'h0;\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/axihp_writer.v:242: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance top\n  assign \\$48  = unconf == (* src = "axihp_writer.py:169" *) 1\'h0;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/axihp_writer.v:244: Operator NEQ expects 2 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance top\n  assign \\$52  = m_axi_wi__bresp != (* src = "axihp_writer.py:174" *) 1\'h0;\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/axihp_writer.v:264: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance top\n  assign \\$92  = active == (* src = "axihp_writer.py:200" *) 1\'h0;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/axihp_writer.v:265: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance top\n  assign \\$94  = unconf == (* src = "axihp_writer.py:200" *) 1\'h0;\n                        ^~\n%Error: Exiting due to 5 warning(s)\n'
module top(enable, addr_empty, addr_in, m_axi_wi__wready, data_empty, data_in, m_axi_wi__bvalid, m_axi_wi__bresp, write_strobe, m_axi_aclk, rst, clk, inactive, data_clk, data_enable, addr_clk, addr_enable, writer_error, writer_active, writer_unconf, m_axi_wo__awid, m_axi_wo__awaddr, m_axi_wo__awburst, m_axi_wo__awlen, m_axi_wo__awsize, m_axi_wo__awprot, m_axi_wo__awvalid, m_axi_wo__wid, m_axi_wo__wdata, m_axi_wo__wstrb, m_axi_wo__wlast, m_axi_wo__wvalid, m_axi_wo__bready, m_axi_wi__awready);
  wire \$1 ;
  wire \$11 ;
  wire \$13 ;
  wire \$15 ;
  wire \$17 ;
  wire \$19 ;
  wire [4:0] \$21 ;
  wire [4:0] \$22 ;
  wire \$24 ;
  wire \$26 ;
  wire \$28 ;
  wire \$3 ;
  wire \$30 ;
  wire \$32 ;
  wire \$34 ;
  wire \$36 ;
  wire \$38 ;
  wire \$40 ;
  wire \$42 ;
  wire \$44 ;
  wire \$46 ;
  wire \$48 ;
  wire \$5 ;
  wire \$50 ;
  wire \$52 ;
  wire \$54 ;
  wire \$56 ;
  wire \$58 ;
  wire \$60 ;
  wire \$62 ;
  wire \$64 ;
  wire \$66 ;
  wire [4:0] \$68 ;
  wire [4:0] \$69 ;
  wire \$7 ;
  wire [4:0] \$71 ;
  wire [4:0] \$72 ;
  wire \$74 ;
  wire \$76 ;
  wire \$78 ;
  wire \$80 ;
  wire \$82 ;
  wire \$84 ;
  wire [4:0] \$86 ;
  wire [4:0] \$87 ;
  wire [4:0] \$89 ;
  wire \$9 ;
  wire [4:0] \$90 ;
  wire \$92 ;
  wire \$94 ;
  wire \$96 ;
  (* src = "axihp_writer.py:79" *)
  reg [3:0] \$next\active ;
  (* src = "axihp_writer.py:20" *)
  reg \$next\addr_clk ;
  (* src = "axihp_writer.py:88" *)
  reg \$next\addr_en ;
  (* src = "axihp_writer.py:21" *)
  reg \$next\addr_enable ;
  (* src = "axihp_writer.py:76" *)
  reg [3:0] \$next\awlen_c ;
  (* src = "axihp_writer.py:82" *)
  reg \$next\awvalid ;
  (* src = "axihp_writer.py:85" *)
  reg \$next\bready ;
  (* src = "axihp_writer.py:121" *)
  reg [3:0] \$next\counter ;
  (* src = "axihp_writer.py:25" *)
  reg \$next\data_clk ;
  (* src = "axihp_writer.py:87" *)
  reg \$next\data_en ;
  (* src = "axihp_writer.py:26" *)
  reg \$next\data_enable ;
  (* src = "axihp_writer.py:15" *)
  reg \$next\inactive ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [31:0] \$next\m_axi_wo__awaddr ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [1:0] \$next\m_axi_wo__awburst ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [5:0] \$next\m_axi_wo__awid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [3:0] \$next\m_axi_wo__awlen ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [2:0] \$next\m_axi_wo__awprot ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [1:0] \$next\m_axi_wo__awsize ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__awvalid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__bready ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [63:0] \$next\m_axi_wo__wdata ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [5:0] \$next\m_axi_wo__wid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__wlast ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [7:0] \$next\m_axi_wo__wstrb ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__wvalid ;
  (* src = "axihp_writer.py:89" *)
  reg \$next\resp_en ;
  (* src = "axihp_writer.py:80" *)
  reg [3:0] \$next\unconf ;
  (* src = "axihp_writer.py:84" *)
  reg \$next\wlast ;
  (* src = "axihp_writer.py:33" *)
  reg [3:0] \$next\writer_active ;
  (* src = "axihp_writer.py:32" *)
  reg \$next\writer_error ;
  (* src = "axihp_writer.py:34" *)
  reg [3:0] \$next\writer_unconf ;
  (* src = "axihp_writer.py:83" *)
  reg \$next\wvalid ;
  (* init = 1'h0 *)
  reg \$verilog_initial_trigger  = 1'h0;
  (* init = 4'h0 *)
  (* src = "axihp_writer.py:79" *)
  reg [3:0] active = 4'h0;
  (* src = "axihp_writer.py:20" *)
  output addr_clk;
  (* src = "axihp_writer.py:23" *)
  input addr_empty;
  (* src = "axihp_writer.py:88" *)
  wire addr_en;
  (* src = "axihp_writer.py:21" *)
  output addr_enable;
  (* src = "axihp_writer.py:22" *)
  input [31:0] addr_in;
  (* src = "axihp_writer.py:76" *)
  wire [3:0] awlen_c;
  (* init = 1'h0 *)
  (* src = "axihp_writer.py:82" *)
  reg awvalid = 1'h0;
  (* init = 1'h0 *)
  (* src = "axihp_writer.py:85" *)
  reg bready = 1'h0;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* init = 4'h0 *)
  (* src = "axihp_writer.py:121" *)
  reg [3:0] counter = 4'h0;
  (* src = "axihp_writer.py:25" *)
  output data_clk;
  (* src = "axihp_writer.py:28" *)
  input data_empty;
  (* src = "axihp_writer.py:87" *)
  wire data_en;
  (* src = "axihp_writer.py:26" *)
  output data_enable;
  (* src = "axihp_writer.py:27" *)
  input [63:0] data_in;
  (* src = "axihp_writer.py:14" *)
  input enable;
  (* src = "axihp_writer.py:15" *)
  output inactive;
  (* src = "axihp_writer.py:12" *)
  input m_axi_aclk;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_wi__awready;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [1:0] m_axi_wi__bresp;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_wi__bvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_wi__wready;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [31:0] m_axi_wo__awaddr;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [1:0] m_axi_wo__awburst;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [5:0] m_axi_wo__awid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [3:0] m_axi_wo__awlen;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [2:0] m_axi_wo__awprot;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [1:0] m_axi_wo__awsize;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__awvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__bready;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [63:0] m_axi_wo__wdata;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [5:0] m_axi_wo__wid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__wlast;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [7:0] m_axi_wo__wstrb;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__wvalid;
  (* src = "axihp_writer.py:89" *)
  wire resp_en;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* init = 4'h0 *)
  (* src = "axihp_writer.py:80" *)
  reg [3:0] unconf = 4'h0;
  (* init = 1'h0 *)
  (* src = "axihp_writer.py:84" *)
  reg wlast = 1'h0;
  (* src = "axihp_writer.py:30" *)
  input [7:0] write_strobe;
  (* src = "axihp_writer.py:33" *)
  output [3:0] writer_active;
  (* src = "axihp_writer.py:32" *)
  output writer_error;
  (* src = "axihp_writer.py:34" *)
  output [3:0] writer_unconf;
  (* init = 1'h0 *)
  (* src = "axihp_writer.py:83" *)
  reg wvalid = 1'h0;
  assign \$9  = enable == (* src = "axihp_writer.py:101" *) 1'h1;
  assign \$11  = addr_empty == (* src = "axihp_writer.py:101" *) 1'h0;
  assign \$13  = \$9  & (* src = "axihp_writer.py:101" *) \$11 ;
  assign \$15  = active[3] == (* src = "axihp_writer.py:101" *) 1'h0;
  assign \$17  = \$13  & (* src = "axihp_writer.py:101" *) \$15 ;
  assign \$1  = awvalid == (* src = "axihp_writer.py:96" *) 1'h1;
  assign \$19  = counter == (* src = "axihp_writer.py:123" *) 4'hf;
  assign \$22  = counter + (* src = "axihp_writer.py:131" *) 1'h1;
  assign \$24  = counter == (* src = "axihp_writer.py:123" *) 4'hf;
  assign \$26  = wvalid == (* src = "axihp_writer.py:134" *) 1'h1;
  assign \$28  = m_axi_wi__wready == (* src = "axihp_writer.py:134" *) 1'h1;
  assign \$30  = \$26  & (* src = "axihp_writer.py:134" *) \$28 ;
  assign \$32  = wvalid == (* src = "axihp_writer.py:137" *) 1'h0;
  assign \$34  = data_empty == (* src = "axihp_writer.py:139" *) 1'h0;
  assign \$36  = active != (* src = "axihp_writer.py:139" *) 1'h0;
  assign \$38  = \$34  & (* src = "axihp_writer.py:139" *) \$36 ;
  assign \$3  = m_axi_wi__awready == (* src = "axihp_writer.py:96" *) 1'h1;
  assign \$40  = bready == (* src = "axihp_writer.py:159" *) 1'h1;
  assign \$42  = m_axi_wi__bvalid == (* src = "axihp_writer.py:159" *) 1'h1;
  assign \$44  = \$40  & (* src = "axihp_writer.py:159" *) \$42 ;
  assign \$46  = bready == (* src = "axihp_writer.py:162" *) 1'h0;
  assign \$48  = unconf == (* src = "axihp_writer.py:169" *) 1'h0;
  assign \$50  = resp_en == (* src = "axihp_writer.py:174" *) 1'h1;
  assign \$52  = m_axi_wi__bresp != (* src = "axihp_writer.py:174" *) 1'h0;
  assign \$54  = \$50  & (* src = "axihp_writer.py:174" *) \$52 ;
  assign \$56  = addr_en == (* src = "axihp_writer.py:183" *) 1'h1;
  assign \$58  = wlast == (* src = "axihp_writer.py:183" *) 1'h0;
  assign \$5  = \$1  & (* src = "axihp_writer.py:96" *) \$3 ;
  assign \$60  = \$56  & (* src = "axihp_writer.py:183" *) \$58 ;
  assign \$62  = addr_en == (* src = "axihp_writer.py:187" *) 1'h0;
  assign \$64  = wlast == (* src = "axihp_writer.py:187" *) 1'h1;
  assign \$66  = \$62  & (* src = "axihp_writer.py:187" *) \$64 ;
  assign \$69  = active + (* src = "axihp_writer.py:185" *) 1'h1;
  assign \$72  = active - (* src = "axihp_writer.py:189" *) 1'h1;
  assign \$74  = addr_en == (* src = "axihp_writer.py:192" *) 1'h1;
  assign \$76  = resp_en == (* src = "axihp_writer.py:192" *) 1'h0;
  assign \$78  = \$74  & (* src = "axihp_writer.py:192" *) \$76 ;
  assign \$7  = awvalid == (* src = "axihp_writer.py:99" *) 1'h0;
  assign \$80  = addr_en == (* src = "axihp_writer.py:196" *) 1'h0;
  assign \$82  = resp_en == (* src = "axihp_writer.py:196" *) 1'h1;
  assign \$84  = \$80  & (* src = "axihp_writer.py:196" *) \$82 ;
  assign \$87  = unconf + (* src = "axihp_writer.py:194" *) 1'h1;
  assign \$90  = unconf - (* src = "axihp_writer.py:198" *) 1'h1;
  assign \$92  = active == (* src = "axihp_writer.py:200" *) 1'h0;
  assign \$94  = unconf == (* src = "axihp_writer.py:200" *) 1'h0;
  assign \$96  = \$92  & (* src = "axihp_writer.py:200" *) \$94 ;
  always @(posedge clk)
      unconf <= \$next\unconf ;
  always @(posedge clk)
      active <= \$next\active ;
  always @(posedge clk)
      bready <= \$next\bready ;
  always @(posedge clk)
      wvalid <= \$next\wvalid ;
  always @(posedge clk)
      wlast <= \$next\wlast ;
  always @(posedge clk)
      counter <= \$next\counter ;
  always @(posedge clk)
      awvalid <= \$next\awvalid ;
  always @* begin
    \$next\awlen_c  = 4'h0;
    \$next\awlen_c  = 4'hf;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\addr_en  = 1'h0;
    \$next\addr_en  = \$5 ;
  end
  always @* begin
    \$next\m_axi_wo__wdata  = 64'h0000000000000000;
    \$next\m_axi_wo__wdata  = data_in;
  end
  always @* begin
    \$next\m_axi_wo__wvalid  = 1'h0;
    \$next\m_axi_wo__wvalid  = wvalid;
  end
  always @* begin
    \$next\m_axi_wo__wlast  = 1'h0;
    \$next\m_axi_wo__wlast  = wlast;
  end
  always @* begin
    \$next\data_enable  = 1'h0;
    \$next\data_enable  = data_en;
  end
  always @* begin
    \$next\resp_en  = 1'h0;
    \$next\resp_en  = \$44 ;
  end
  always @* begin
    \$next\bready  = bready;
    casez (\$46 )
      1'h1:
          casez (enable)
            1'h1:
                \$next\bready  = 1'h1;
          endcase
      1'hz:
          casez (\$48 )
            1'h1:
                \$next\bready  = 1'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\bready  = 1'h0;
    endcase
  end
  always @* begin
    \$next\m_axi_wo__bready  = 1'h0;
    \$next\m_axi_wo__bready  = bready;
  end
  always @* begin
    \$next\writer_error  = 1'h0;
    \$next\writer_error  = \$54 ;
  end
  always @* begin
    \$next\active  = active;
    casez ({ \$66 , \$60  })
      2'bz1:
          \$next\active  = \$68 [3:0];
      2'b1z:
          \$next\active  = \$71 [3:0];
    endcase
    casez (rst)
      1'h1:
          \$next\active  = 4'h0;
    endcase
  end
  always @* begin
    \$next\unconf  = unconf;
    casez ({ \$84 , \$78  })
      2'bz1:
          \$next\unconf  = \$86 [3:0];
      2'b1z:
          \$next\unconf  = \$89 [3:0];
    endcase
    casez (rst)
      1'h1:
          \$next\unconf  = 4'h0;
    endcase
  end
  always @* begin
    \$next\awvalid  = awvalid;
    casez (\$7 )
      1'h1:
          casez (\$17 )
            1'h1:
                \$next\awvalid  = 1'h1;
          endcase
    endcase
    casez (awvalid)
      1'h1:
          casez (m_axi_wi__awready)
            1'h1:
                \$next\awvalid  = 1'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\awvalid  = 1'h0;
    endcase
  end
  always @* begin
    \$next\inactive  = 1'h0;
    \$next\inactive  = \$96 ;
  end
  always @* begin
    \$next\m_axi_wo__awid  = 6'h00;
    \$next\m_axi_wo__awid  = 6'h00;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\m_axi_wo__wid  = 6'h00;
    \$next\m_axi_wo__wid  = 6'h00;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\m_axi_wo__awlen  = 4'h0;
    \$next\m_axi_wo__awlen  = awlen_c;
  end
  always @* begin
    \$next\m_axi_wo__awburst  = 2'h0;
    \$next\m_axi_wo__awburst  = 2'h1;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\m_axi_wo__awsize  = 2'h0;
    \$next\m_axi_wo__awsize  = 2'h3;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\m_axi_wo__wstrb  = 8'h00;
    \$next\m_axi_wo__wstrb  = write_strobe;
  end
  always @* begin
    \$next\m_axi_wo__awprot  = 3'h0;
    \$next\m_axi_wo__awprot  = 3'h0;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\data_clk  = 1'h0;
    \$next\data_clk  = m_axi_aclk;
  end
  always @* begin
    \$next\addr_clk  = 1'h0;
    \$next\addr_clk  = m_axi_aclk;
  end
  always @* begin
    \$next\m_axi_wo__awaddr  = 32'd0;
    \$next\m_axi_wo__awaddr  = addr_in;
  end
  always @* begin
    \$next\writer_active  = 4'h0;
    \$next\writer_active  = active;
  end
  always @* begin
    \$next\writer_unconf  = 4'h0;
    \$next\writer_unconf  = unconf;
  end
  always @* begin
    \$next\m_axi_wo__awvalid  = 1'h0;
    \$next\m_axi_wo__awvalid  = awvalid;
  end
  always @* begin
    \$next\addr_enable  = 1'h0;
    \$next\addr_enable  = addr_en;
  end
  always @* begin
    \$next\counter  = counter;
    casez (data_en)
      1'h1:
          casez (\$19 )
            1'h1:
                \$next\counter  = 4'h0;
            1'hz:
                \$next\counter  = \$21 [3:0];
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\counter  = 4'h0;
    endcase
  end
  always @* begin
    \$next\wlast  = wlast;
    casez (data_en)
      1'h1:
          casez (\$24 )
            1'h1:
                \$next\wlast  = 1'h1;
            1'hz:
                \$next\wlast  = 1'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\wlast  = 1'h0;
    endcase
  end
  always @* begin
    \$next\data_en  = 1'h0;
    \$next\data_en  = \$30 ;
  end
  always @* begin
    \$next\wvalid  = wvalid;
    casez (\$32 )
      1'h1:
          casez (\$38 )
            1'h1:
                \$next\wvalid  = 1'h1;
          endcase
      1'hz:
          casez (wlast)
            1'h1:
                \$next\wvalid  = 1'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\wvalid  = 1'h0;
    endcase
  end
  assign \$21  = \$22 ;
  assign \$68  = \$69 ;
  assign \$71  = \$72 ;
  assign \$86  = \$87 ;
  assign \$89  = \$90 ;
  assign writer_unconf = \$next\writer_unconf ;
  assign writer_active = \$next\writer_active ;
  assign addr_clk = \$next\addr_clk ;
  assign data_clk = \$next\data_clk ;
  assign m_axi_wo__awprot = \$next\m_axi_wo__awprot ;
  assign m_axi_wo__wstrb = \$next\m_axi_wo__wstrb ;
  assign m_axi_wo__awsize = \$next\m_axi_wo__awsize ;
  assign m_axi_wo__awburst = \$next\m_axi_wo__awburst ;
  assign m_axi_wo__awlen = \$next\m_axi_wo__awlen ;
  assign m_axi_wo__wid = \$next\m_axi_wo__wid ;
  assign m_axi_wo__awid = \$next\m_axi_wo__awid ;
  assign inactive = \$next\inactive ;
  assign writer_error = \$next\writer_error ;
  assign m_axi_wo__bready = \$next\m_axi_wo__bready ;
  assign resp_en = \$next\resp_en ;
  assign data_enable = \$next\data_enable ;
  assign m_axi_wo__wlast = \$next\m_axi_wo__wlast ;
  assign m_axi_wo__wvalid = \$next\m_axi_wo__wvalid ;
  assign m_axi_wo__wdata = \$next\m_axi_wo__wdata ;
  assign data_en = \$next\data_en ;
  assign addr_enable = \$next\addr_enable ;
  assign m_axi_wo__awvalid = \$next\m_axi_wo__awvalid ;
  assign m_axi_wo__awaddr = \$next\m_axi_wo__awaddr ;
  assign addr_en = \$next\addr_en ;
  assign awlen_c = \$next\awlen_c ;
endmodule
module top(enable, addr_empty, addr_in, m_axi_wi__wready, data_empty, data_in, m_axi_wi__bvalid, m_axi_wi__bresp, write_strobe, m_axi_aclk, rst, clk, inactive, data_clk, data_enable, addr_clk, addr_enable, writer_error, writer_active, writer_unconf, m_axi_wo__awid, m_axi_wo__awaddr, m_axi_wo__awburst, m_axi_wo__awlen, m_axi_wo__awsize, m_axi_wo__awprot, m_axi_wo__awvalid, m_axi_wo__wid, m_axi_wo__wdata, m_axi_wo__wstrb, m_axi_wo__wlast, m_axi_wo__wvalid, m_axi_wo__bready, m_axi_wi__awready);

  wire \$1 ;
  wire \$11 ;
  wire \$13 ;
  wire \$15 ;
  wire \$17 ;
  wire \$19 ;
  wire [4:0] \$21 ;
  wire [4:0] \$22 ;
  wire \$24 ;
  wire \$26 ;
  wire \$28 ;
  wire \$3 ;
  wire \$30 ;
  wire \$32 ;
  wire \$34 ;
  wire \$36 ;
  wire \$38 ;
  wire \$40 ;
  wire \$42 ;
  wire \$44 ;
  wire \$46 ;
  wire \$48 ;
  wire \$5 ;
  wire \$50 ;
  wire \$52 ;
  wire \$54 ;
  wire \$56 ;
  wire \$58 ;
  wire \$60 ;
  wire \$62 ;
  wire \$64 ;
  wire \$66 ;
  wire [4:0] \$68 ;
  wire [4:0] \$69 ;
  wire \$7 ;
  wire [4:0] \$71 ;
  wire [4:0] \$72 ;
  wire \$74 ;
  wire \$76 ;
  wire \$78 ;
  wire \$80 ;
  wire \$82 ;
  wire \$84 ;
  wire [4:0] \$86 ;
  wire [4:0] \$87 ;
  wire [4:0] \$89 ;
  wire \$9 ;
  wire [4:0] \$90 ;
  wire \$92 ;
  wire \$94 ;
  wire \$96 ;
  (* src = "axihp_writer.py:79" *)
  reg [3:0] \$next\active ;
  (* src = "axihp_writer.py:20" *)
  reg \$next\addr_clk ;
  (* src = "axihp_writer.py:88" *)
  reg \$next\addr_en ;
  (* src = "axihp_writer.py:21" *)
  reg \$next\addr_enable ;
  (* src = "axihp_writer.py:76" *)
  reg [3:0] \$next\awlen_c ;
  (* src = "axihp_writer.py:82" *)
  reg \$next\awvalid ;
  (* src = "axihp_writer.py:85" *)
  reg \$next\bready ;
  (* src = "axihp_writer.py:121" *)
  reg [3:0] \$next\counter ;
  (* src = "axihp_writer.py:25" *)
  reg \$next\data_clk ;
  (* src = "axihp_writer.py:87" *)
  reg \$next\data_en ;
  (* src = "axihp_writer.py:26" *)
  reg \$next\data_enable ;
  (* src = "axihp_writer.py:15" *)
  reg \$next\inactive ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [31:0] \$next\m_axi_wo__awaddr ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [1:0] \$next\m_axi_wo__awburst ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [5:0] \$next\m_axi_wo__awid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [3:0] \$next\m_axi_wo__awlen ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [2:0] \$next\m_axi_wo__awprot ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [1:0] \$next\m_axi_wo__awsize ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__awvalid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__bready ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [63:0] \$next\m_axi_wo__wdata ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [5:0] \$next\m_axi_wo__wid ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__wlast ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg [7:0] \$next\m_axi_wo__wstrb ;
  (* src = "nmigen/hdl/rec.py:84" *)
  reg \$next\m_axi_wo__wvalid ;
  (* src = "axihp_writer.py:89" *)
  reg \$next\resp_en ;
  (* src = "axihp_writer.py:80" *)
  reg [3:0] \$next\unconf ;
  (* src = "axihp_writer.py:84" *)
  reg \$next\wlast ;
  (* src = "axihp_writer.py:33" *)
  reg [3:0] \$next\writer_active ;
  (* src = "axihp_writer.py:32" *)
  reg \$next\writer_error ;
  (* src = "axihp_writer.py:34" *)
  reg [3:0] \$next\writer_unconf ;
  (* src = "axihp_writer.py:83" *)
  reg \$next\wvalid ;
  (* init = 1'h0 *)
  reg \$verilog_initial_trigger  = 1'h0;
  (* init = 4'h0 *)
  (* src = "axihp_writer.py:79" *)
  reg [3:0] active = 4'h0;
  (* src = "axihp_writer.py:20" *)
  output addr_clk;
  (* src = "axihp_writer.py:23" *)
  input addr_empty;
  (* src = "axihp_writer.py:88" *)
  wire addr_en;
  (* src = "axihp_writer.py:21" *)
  output addr_enable;
  (* src = "axihp_writer.py:22" *)
  input [31:0] addr_in;
  (* src = "axihp_writer.py:76" *)
  wire [3:0] awlen_c;
  (* init = 1'h0 *)
  (* src = "axihp_writer.py:82" *)
  reg awvalid = 1'h0;
  (* init = 1'h0 *)
  (* src = "axihp_writer.py:85" *)
  reg bready = 1'h0;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* init = 4'h0 *)
  (* src = "axihp_writer.py:121" *)
  reg [3:0] counter = 4'h0;
  (* src = "axihp_writer.py:25" *)
  output data_clk;
  (* src = "axihp_writer.py:28" *)
  input data_empty;
  (* src = "axihp_writer.py:87" *)
  wire data_en;
  (* src = "axihp_writer.py:26" *)
  output data_enable;
  (* src = "axihp_writer.py:27" *)
  input [63:0] data_in;
  (* src = "axihp_writer.py:14" *)
  input enable;
  (* src = "axihp_writer.py:15" *)
  output inactive;
  (* src = "axihp_writer.py:12" *)
  input m_axi_aclk;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_wi__awready;
  (* src = "nmigen/hdl/rec.py:84" *)
  input [1:0] m_axi_wi__bresp;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_wi__bvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  input m_axi_wi__wready;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [31:0] m_axi_wo__awaddr;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [1:0] m_axi_wo__awburst;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [5:0] m_axi_wo__awid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [3:0] m_axi_wo__awlen;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [2:0] m_axi_wo__awprot;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [1:0] m_axi_wo__awsize;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__awvalid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__bready;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [63:0] m_axi_wo__wdata;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [5:0] m_axi_wo__wid;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__wlast;
  (* src = "nmigen/hdl/rec.py:84" *)
  output [7:0] m_axi_wo__wstrb;
  (* src = "nmigen/hdl/rec.py:84" *)
  output m_axi_wo__wvalid;
  (* src = "axihp_writer.py:89" *)
  wire resp_en;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* init = 4'h0 *)
  (* src = "axihp_writer.py:80" *)
  reg [3:0] unconf = 4'h0;
  (* init = 1'h0 *)
  (* src = "axihp_writer.py:84" *)
  reg wlast = 1'h0;
  (* src = "axihp_writer.py:30" *)
  input [7:0] write_strobe;
  (* src = "axihp_writer.py:33" *)
  output [3:0] writer_active;
  (* src = "axihp_writer.py:32" *)
  output writer_error;
  (* src = "axihp_writer.py:34" *)
  output [3:0] writer_unconf;
  (* init = 1'h0 *)
  (* src = "axihp_writer.py:83" *)
  reg wvalid = 1'h0;
  assign \$9  = enable == (* src = "axihp_writer.py:101" *) 1'h1;
  assign \$11  = addr_empty == (* src = "axihp_writer.py:101" *) 1'h0;
  assign \$13  = \$9  & (* src = "axihp_writer.py:101" *) \$11 ;
  assign \$15  = active[3] == (* src = "axihp_writer.py:101" *) 1'h0;
  assign \$17  = \$13  & (* src = "axihp_writer.py:101" *) \$15 ;
  assign \$1  = awvalid == (* src = "axihp_writer.py:96" *) 1'h1;
  assign \$19  = counter == (* src = "axihp_writer.py:123" *) 4'hf;
  assign \$22  = counter + (* src = "axihp_writer.py:131" *) 1'h1;
  assign \$24  = counter == (* src = "axihp_writer.py:123" *) 4'hf;
  assign \$26  = wvalid == (* src = "axihp_writer.py:134" *) 1'h1;
  assign \$28  = m_axi_wi__wready == (* src = "axihp_writer.py:134" *) 1'h1;
  assign \$30  = \$26  & (* src = "axihp_writer.py:134" *) \$28 ;
  assign \$32  = wvalid == (* src = "axihp_writer.py:137" *) 1'h0;
  assign \$34  = data_empty == (* src = "axihp_writer.py:139" *) 1'h0;
  assign \$36  = active != (* src = "axihp_writer.py:139" *) 1'h0;
  assign \$38  = \$34  & (* src = "axihp_writer.py:139" *) \$36 ;
  assign \$3  = m_axi_wi__awready == (* src = "axihp_writer.py:96" *) 1'h1;
  assign \$40  = bready == (* src = "axihp_writer.py:159" *) 1'h1;
  assign \$42  = m_axi_wi__bvalid == (* src = "axihp_writer.py:159" *) 1'h1;
  assign \$44  = \$40  & (* src = "axihp_writer.py:159" *) \$42 ;
  assign \$46  = bready == (* src = "axihp_writer.py:162" *) 1'h0;
  assign \$48  = unconf == (* src = "axihp_writer.py:169" *) 1'h0;
  assign \$50  = resp_en == (* src = "axihp_writer.py:174" *) 1'h1;
  assign \$52  = m_axi_wi__bresp != (* src = "axihp_writer.py:174" *) 1'h0;
  assign \$54  = \$50  & (* src = "axihp_writer.py:174" *) \$52 ;
  assign \$56  = addr_en == (* src = "axihp_writer.py:183" *) 1'h1;
  assign \$58  = wlast == (* src = "axihp_writer.py:183" *) 1'h0;
  assign \$5  = \$1  & (* src = "axihp_writer.py:96" *) \$3 ;
  assign \$60  = \$56  & (* src = "axihp_writer.py:183" *) \$58 ;
  assign \$62  = addr_en == (* src = "axihp_writer.py:187" *) 1'h0;
  assign \$64  = wlast == (* src = "axihp_writer.py:187" *) 1'h1;
  assign \$66  = \$62  & (* src = "axihp_writer.py:187" *) \$64 ;
  assign \$69  = active + (* src = "axihp_writer.py:185" *) 1'h1;
  assign \$72  = active - (* src = "axihp_writer.py:189" *) 1'h1;
  assign \$74  = addr_en == (* src = "axihp_writer.py:192" *) 1'h1;
  assign \$76  = resp_en == (* src = "axihp_writer.py:192" *) 1'h0;
  assign \$78  = \$74  & (* src = "axihp_writer.py:192" *) \$76 ;
  assign \$7  = awvalid == (* src = "axihp_writer.py:99" *) 1'h0;
  assign \$80  = addr_en == (* src = "axihp_writer.py:196" *) 1'h0;
  assign \$82  = resp_en == (* src = "axihp_writer.py:196" *) 1'h1;
  assign \$84  = \$80  & (* src = "axihp_writer.py:196" *) \$82 ;
  assign \$87  = unconf + (* src = "axihp_writer.py:194" *) 1'h1;
  assign \$90  = unconf - (* src = "axihp_writer.py:198" *) 1'h1;
  assign \$92  = active == (* src = "axihp_writer.py:200" *) 1'h0;
  assign \$94  = unconf == (* src = "axihp_writer.py:200" *) 1'h0;
  assign \$96  = \$92  & (* src = "axihp_writer.py:200" *) \$94 ;
  always @(posedge clk)
      unconf <= \$next\unconf ;
  always @(posedge clk)
      active <= \$next\active ;
  always @(posedge clk)
      bready <= \$next\bready ;
  always @(posedge clk)
      wvalid <= \$next\wvalid ;
  always @(posedge clk)
      wlast <= \$next\wlast ;
  always @(posedge clk)
      counter <= \$next\counter ;
  always @(posedge clk)
      awvalid <= \$next\awvalid ;
  always @* begin
    \$next\awlen_c  = 4'h0;
    \$next\awlen_c  = 4'hf;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\addr_en  = 1'h0;
    \$next\addr_en  = \$5 ;
  end
  always @* begin
    \$next\m_axi_wo__wdata  = 64'h0000000000000000;
    \$next\m_axi_wo__wdata  = data_in;
  end
  always @* begin
    \$next\m_axi_wo__wvalid  = 1'h0;
    \$next\m_axi_wo__wvalid  = wvalid;
  end
  always @* begin
    \$next\m_axi_wo__wlast  = 1'h0;
    \$next\m_axi_wo__wlast  = wlast;
  end
  always @* begin
    \$next\data_enable  = 1'h0;
    \$next\data_enable  = data_en;
  end
  always @* begin
    \$next\resp_en  = 1'h0;
    \$next\resp_en  = \$44 ;
  end
  always @* begin
    \$next\bready  = bready;
    casez (\$46 )
      1'h1:
          casez (enable)
            1'h1:
                \$next\bready  = 1'h1;
          endcase
      1'hz:
          casez (\$48 )
            1'h1:
                \$next\bready  = 1'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\bready  = 1'h0;
    endcase
  end
  always @* begin
    \$next\m_axi_wo__bready  = 1'h0;
    \$next\m_axi_wo__bready  = bready;
  end
  always @* begin
    \$next\writer_error  = 1'h0;
    \$next\writer_error  = \$54 ;
  end
  always @* begin
    \$next\active  = active;
    casez ({ \$66 , \$60  })
      2'bz1:
          \$next\active  = \$68 [3:0];
      2'b1z:
          \$next\active  = \$71 [3:0];
    endcase
    casez (rst)
      1'h1:
          \$next\active  = 4'h0;
    endcase
  end
  always @* begin
    \$next\unconf  = unconf;
    casez ({ \$84 , \$78  })
      2'bz1:
          \$next\unconf  = \$86 [3:0];
      2'b1z:
          \$next\unconf  = \$89 [3:0];
    endcase
    casez (rst)
      1'h1:
          \$next\unconf  = 4'h0;
    endcase
  end
  always @* begin
    \$next\awvalid  = awvalid;
    casez (\$7 )
      1'h1:
          casez (\$17 )
            1'h1:
                \$next\awvalid  = 1'h1;
          endcase
    endcase
    casez (awvalid)
      1'h1:
          casez (m_axi_wi__awready)
            1'h1:
                \$next\awvalid  = 1'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\awvalid  = 1'h0;
    endcase
  end
  always @* begin
    \$next\inactive  = 1'h0;
    \$next\inactive  = \$96 ;
  end
  always @* begin
    \$next\m_axi_wo__awid  = 6'h00;
    \$next\m_axi_wo__awid  = 6'h00;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\m_axi_wo__wid  = 6'h00;
    \$next\m_axi_wo__wid  = 6'h00;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\m_axi_wo__awlen  = 4'h0;
    \$next\m_axi_wo__awlen  = awlen_c;
  end
  always @* begin
    \$next\m_axi_wo__awburst  = 2'h0;
    \$next\m_axi_wo__awburst  = 2'h1;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\m_axi_wo__awsize  = 2'h0;
    \$next\m_axi_wo__awsize  = 2'h3;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\m_axi_wo__wstrb  = 8'h00;
    \$next\m_axi_wo__wstrb  = write_strobe;
  end
  always @* begin
    \$next\m_axi_wo__awprot  = 3'h0;
    \$next\m_axi_wo__awprot  = 3'h0;
    \$verilog_initial_trigger  = \$verilog_initial_trigger ;
  end
  always @* begin
    \$next\data_clk  = 1'h0;
    \$next\data_clk  = m_axi_aclk;
  end
  always @* begin
    \$next\addr_clk  = 1'h0;
    \$next\addr_clk  = m_axi_aclk;
  end
  always @* begin
    \$next\m_axi_wo__awaddr  = 32'd0;
    \$next\m_axi_wo__awaddr  = addr_in;
  end
  always @* begin
    \$next\writer_active  = 4'h0;
    \$next\writer_active  = active;
  end
  always @* begin
    \$next\writer_unconf  = 4'h0;
    \$next\writer_unconf  = unconf;
  end
  always @* begin
    \$next\m_axi_wo__awvalid  = 1'h0;
    \$next\m_axi_wo__awvalid  = awvalid;
  end
  always @* begin
    \$next\addr_enable  = 1'h0;
    \$next\addr_enable  = addr_en;
  end
  always @* begin
    \$next\counter  = counter;
    casez (data_en)
      1'h1:
          casez (\$19 )
            1'h1:
                \$next\counter  = 4'h0;
            1'hz:
                \$next\counter  = \$21 [3:0];
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\counter  = 4'h0;
    endcase
  end
  always @* begin
    \$next\wlast  = wlast;
    casez (data_en)
      1'h1:
          casez (\$24 )
            1'h1:
                \$next\wlast  = 1'h1;
            1'hz:
                \$next\wlast  = 1'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\wlast  = 1'h0;
    endcase
  end
  always @* begin
    \$next\data_en  = 1'h0;
    \$next\data_en  = \$30 ;
  end
  always @* begin
    \$next\wvalid  = wvalid;
    casez (\$32 )
      1'h1:
          casez (\$38 )
            1'h1:
                \$next\wvalid  = 1'h1;
          endcase
      1'hz:
          casez (wlast)
            1'h1:
                \$next\wvalid  = 1'h0;
          endcase
    endcase
    casez (rst)
      1'h1:
          \$next\wvalid  = 1'h0;
    endcase
  end
  assign \$21  = \$22 ;
  assign \$68  = \$69 ;
  assign \$71  = \$72 ;
  assign \$86  = \$87 ;
  assign \$89  = \$90 ;
  assign writer_unconf = \$next\writer_unconf ;
  assign writer_active = \$next\writer_active ;
  assign addr_clk = \$next\addr_clk ;
  assign data_clk = \$next\data_clk ;
  assign m_axi_wo__awprot = \$next\m_axi_wo__awprot ;
  assign m_axi_wo__wstrb = \$next\m_axi_wo__wstrb ;
  assign m_axi_wo__awsize = \$next\m_axi_wo__awsize ;
  assign m_axi_wo__awburst = \$next\m_axi_wo__awburst ;
  assign m_axi_wo__awlen = \$next\m_axi_wo__awlen ;
  assign m_axi_wo__wid = \$next\m_axi_wo__wid ;
  assign m_axi_wo__awid = \$next\m_axi_wo__awid ;
  assign inactive = \$next\inactive ;
  assign writer_error = \$next\writer_error ;
  assign m_axi_wo__bready = \$next\m_axi_wo__bready ;
  assign resp_en = \$next\resp_en ;
  assign data_enable = \$next\data_enable ;
  assign m_axi_wo__wlast = \$next\m_axi_wo__wlast ;
  assign m_axi_wo__wvalid = \$next\m_axi_wo__wvalid ;
  assign m_axi_wo__wdata = \$next\m_axi_wo__wdata ;
  assign data_en = \$next\data_en ;
  assign addr_enable = \$next\addr_enable ;
  assign m_axi_wo__awvalid = \$next\m_axi_wo__awvalid ;
  assign m_axi_wo__awaddr = \$next\m_axi_wo__awaddr ;
  assign addr_en = \$next\addr_en ;
  assign awlen_c = \$next\awlen_c ;
endmodule