data/full_repos/permissive/179227721/led_counter_icestick/counter_tb.v
 line:30: before: "+"
1: b'%Error: data/full_repos/permissive/179227721/led_counter_icestick/counter_tb.v:14: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("counter_wave.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/179227721/led_counter_icestick/counter_tb.v:15: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, testbench);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/179227721/led_counter_icestick/counter_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/179227721/led_counter_icestick/counter_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/179227721/led_counter_icestick/counter_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #500;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/179227721/led_counter_icestick/counter_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n             #500;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/179227721/led_counter_icestick/counter_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n             #500;\n             ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
   reg clk;
   reg rst;
   wire [4:0] led;

   integer    i;

   counter counter1 (clk, rst, led);

   initial
     begin
        $dumpfile("counter_wave.vcd");
        $dumpvars(0, testbench);

        clk <= 0;
        rst <= 0;

        #500;
        clk <= 1;

        #500;

        rst <= 1;
        clk <= 0;

        #500;

        for (i = 0; i < 30; i++)
          begin
             clk <= 1;
             #500;
             clk <= 0;
             #500;
          end
     end
endmodule
module testbench;

   reg clk;
   reg rst;
   wire [4:0] led;

   integer    i;

   counter counter1 (clk, rst, led);

   initial
     begin
        $dumpfile("counter_wave.vcd");
        $dumpvars(0, testbench);

        clk <= 0;
        rst <= 0;

        #500;
        clk <= 1;

        #500;

        rst <= 1;
        clk <= 0;

        #500;

        for (i = 0; i < 30; i++)
          begin
             clk <= 1;
             #500;
             clk <= 0;
             #500;
          end
     end
endmodule