data/full_repos/permissive/131928535/rtl/Alorium_speaker.v
data/verilator_xmls/1c2116dc-9f92-4da1-bd2d-81f50a44eb7d.xml
module Alorium_speaker
	(

	input wire clk,
    input wire resetn,
	input wire spk_on,
	
	output wire spk1_pin,
	output wire spk2_pin	
	);
	
	reg [15:0] count1 = 0;
	reg [15:0] count2 = 0;

	reg [15:0] target2 = 20000;

	reg [15:0] target1 = 8000;
    


    reg [11:0] freq1 = 12'd400;
    reg [11:0] freq2 = 12'd800;










	
	reg spk1_temp = 0;
	assign spk1_pin = spk1_temp;
	reg spk2_temp = 0;
	assign spk2_pin = spk2_temp;
	
	

	always @(posedge clk)begin
        if (!resetn) begin
            spk1_temp <= 0;
        end
        else if (spk_on) begin
			if (target1 == count1) begin
				spk1_temp = ~spk1_temp;
				count1 = 0;
			end
			else begin
				count1 = count1 + 1;
			end
		end
		
		else begin
			count1 = 0;
		end
	end 
   



		integer i = 0;	

	

	






	


		always @(posedge clk)begin
            if(!resetn) begin
                spk2_temp <= 0;
            end
            else if (spk_on) begin
			    if (target2 == count2) begin
				    spk2_temp = 1;
				    count2 = 0;
			    end
			    else begin
				    count2 = count2 + 1;
			    end
		    end
		
		    else begin
		    	count2 = 0;
		    end
		end 
endmodule
module Alorium_speaker
	(

	input wire clk,
    input wire resetn,
	input wire spk_on,
	
	output wire spk1_pin,
	output wire spk2_pin	
	);

	
	reg [15:0] count1 = 0;
	reg [15:0] count2 = 0;

	reg [15:0] target2 = 20000;

	reg [15:0] target1 = 8000;
    


    reg [11:0] freq1 = 12'd400;
    reg [11:0] freq2 = 12'd800;










	
	reg spk1_temp = 0;
	assign spk1_pin = spk1_temp;
	reg spk2_temp = 0;
	assign spk2_pin = spk2_temp;
	
	

	always @(posedge clk)begin
        if (!resetn) begin
            spk1_temp <= 0;
        end
        else if (spk_on) begin
			if (target1 == count1) begin
				spk1_temp = ~spk1_temp;
				count1 = 0;
			end
			else begin
				count1 = count1 + 1;
			end
		end
		
		else begin
			count1 = 0;
		end
	end 
   



		integer i = 0;	

	

	






	


		always @(posedge clk)begin
            if(!resetn) begin
                spk2_temp <= 0;
            end
            else if (spk_on) begin
			    if (target2 == count2) begin
				    spk2_temp = 1;
				    count2 = 0;
			    end
			    else begin
				    count2 = count2 + 1;
			    end
		    end
		
		    else begin
		    	count2 = 0;
		    end
		end 
endmodule