data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v
 line:428: before: ";"
1: b"%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:162: Define or directive not defined: '`UDP_REG_ADDR_WIDTH'\n   wire [`UDP_REG_ADDR_WIDTH-1:0]   in_arb_in_reg_addr;\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:163: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n   wire [`CPCI_NF2_DATA_WIDTH-1:0]  in_arb_in_reg_data;\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:182: Define or directive not defined: '`UDP_REG_ADDR_WIDTH'\n   wire [`UDP_REG_ADDR_WIDTH-1:0]   op_lut_in_reg_addr;\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:183: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n   wire [`CPCI_NF2_DATA_WIDTH-1:0]  op_lut_in_reg_data;\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:195: Define or directive not defined: '`UDP_REG_ADDR_WIDTH'\n   wire [`UDP_REG_ADDR_WIDTH-1:0]   op_lut_in_reg_addr_2;\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:196: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n   wire [`CPCI_NF2_DATA_WIDTH-1:0]  op_lut_in_reg_data_2;\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:208: Define or directive not defined: '`UDP_REG_ADDR_WIDTH'\n   wire [`UDP_REG_ADDR_WIDTH-1:0]   op_lut_in_reg_addr_3;\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:209: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n   wire [`CPCI_NF2_DATA_WIDTH-1:0]  op_lut_in_reg_data_3;\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:226: Define or directive not defined: '`UDP_REG_ADDR_WIDTH'\n   wire [`UDP_REG_ADDR_WIDTH-1:0]   rate_limiter_in_reg_addr;\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:227: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n   wire [`CPCI_NF2_DATA_WIDTH-1:0]  rate_limiter_in_reg_data;\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:239: Define or directive not defined: '`UDP_REG_ADDR_WIDTH'\n   wire [`UDP_REG_ADDR_WIDTH-1:0]   oq_in_reg_addr;\n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:240: Define or directive not defined: '`CPCI_NF2_DATA_WIDTH'\n   wire [`CPCI_NF2_DATA_WIDTH-1:0]  oq_in_reg_data;\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:423: Define or directive not defined: '`TABLE_NUM'\n   wire [`TABLE_NUM-1:0]   ack_output_port_lookup_i_hub;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:424: Define or directive not defined: '`TABLE_NUM'\n   wire [31:0]            data_output_port_lookup_i_hub [`TABLE_NUM-1:0];\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:428: Define or directive not defined: '`TABLE_NUM'\n      for(i = 0; i < `TABLE_NUM; i = i + 1)\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:428: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      for(i = 0; i < `TABLE_NUM; i = i + 1)\n                               ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:435: Define or directive not defined: '`T0_OPENFLOW_ENTRY_WIDTH'\n            .OPENFLOW_ENTRY_WIDTH                     (`T0_OPENFLOW_ENTRY_WIDTH),\n                                                       ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:436: Define or directive not defined: '`T0_OPENFLOW_WILDCARD_TABLE_SIZE'\n            .OPENFLOW_WILDCARD_TABLE_SIZE             (`T0_OPENFLOW_WILDCARD_TABLE_SIZE),\n                                                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:438: Define or directive not defined: '`TABLE_NUM'\n            .TABLE_NUM                                (`TABLE_NUM-1)\n                                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:493: Define or directive not defined: '`TABLE_NUM'\n   reg [`TABLE_NUM-1:0]addr;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:523: Define or directive not defined: '`TABLE_ID_POS'\n        addr<=addr_output_port_lookup_o[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS];\n                                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:523: Define or directive not defined: '`TABLE_ID_WIDTH'\n        addr<=addr_output_port_lookup_o[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS];\n                                                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:523: Define or directive not defined: '`TABLE_ID_POS'\n        addr<=addr_output_port_lookup_o[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS];\n                                                                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:523: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n        addr<=addr_output_port_lookup_o[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS];\n                                                                                     ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:545: Define or directive not defined: '`TABLE_NUM'\n      .in_data            (op_lut_in_data[`TABLE_NUM]),\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:545: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n      .in_data            (op_lut_in_data[`TABLE_NUM]),\n                                                    ^\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:546: Define or directive not defined: '`TABLE_NUM'\n      .in_ctrl            (op_lut_in_ctrl[`TABLE_NUM]),\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:547: Define or directive not defined: '`TABLE_NUM'\n      .in_wr              (op_lut_in_wr  [`TABLE_NUM]),\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:548: Define or directive not defined: '`TABLE_NUM'\n      .in_rdy             (op_lut_in_rdy [`TABLE_NUM]),\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:669: Define or directive not defined: '`TABLE_NUM'\n      .TABLE_NUM  (`TABLE_NUM-1)\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/121277233/ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v:934: syntax error, unexpected endmodule\nendmodule  \n^~~~~~~~~\n%Error: Cannot continue\n"
module user_data_path
  #(parameter DATA_WIDTH = 64,
    parameter CTRL_WIDTH=DATA_WIDTH/8,
    parameter UDP_REG_SRC_WIDTH = 2,
    parameter NUM_OUTPUT_QUEUES = 8,
    parameter NUM_INPUT_QUEUES = 8
   )
   (
    input  [DATA_WIDTH-1:0]            in_data_0,
    input  [CTRL_WIDTH-1:0]            in_ctrl_0,
    input                              in_wr_0,
    output                             in_rdy_0,

    input  [DATA_WIDTH-1:0]            in_data_1,
    input  [CTRL_WIDTH-1:0]            in_ctrl_1,
    input                              in_wr_1,
    output                             in_rdy_1,

    input  [DATA_WIDTH-1:0]            in_data_2,
    input  [CTRL_WIDTH-1:0]            in_ctrl_2,
    input                              in_wr_2,
    output                             in_rdy_2,

    input  [DATA_WIDTH-1:0]            in_data_3,
    input  [CTRL_WIDTH-1:0]            in_ctrl_3,
    input                              in_wr_3,
    output                             in_rdy_3,

    input  [DATA_WIDTH-1:0]            in_data_4,
    input  [CTRL_WIDTH-1:0]            in_ctrl_4,
    input                              in_wr_4,
    output                             in_rdy_4,

    input  [DATA_WIDTH-1:0]            in_data_5,
    input  [CTRL_WIDTH-1:0]            in_ctrl_5,
    input                              in_wr_5,
    output                             in_rdy_5,

    input  [DATA_WIDTH-1:0]            in_data_6,
    input  [CTRL_WIDTH-1:0]            in_ctrl_6,
    input                              in_wr_6,
    output                             in_rdy_6,

    input  [DATA_WIDTH-1:0]            in_data_7,
    input  [CTRL_WIDTH-1:0]            in_ctrl_7,
    input                              in_wr_7,
    output                             in_rdy_7,

    output  [DATA_WIDTH-1:0]           out_data_0,
    output  [CTRL_WIDTH-1:0]           out_ctrl_0,
    output                             out_wr_0,
    input                              out_rdy_0,

    output  [DATA_WIDTH-1:0]           out_data_1,
    output  [CTRL_WIDTH-1:0]           out_ctrl_1,
    output                             out_wr_1,
    input                              out_rdy_1,

    output  [DATA_WIDTH-1:0]           out_data_2,
    output  [CTRL_WIDTH-1:0]           out_ctrl_2,
    output                             out_wr_2,
    input                              out_rdy_2,

    output  [DATA_WIDTH-1:0]           out_data_3,
    output  [CTRL_WIDTH-1:0]           out_ctrl_3,
    output                             out_wr_3,
    input                              out_rdy_3,

    output  [DATA_WIDTH-1:0]           out_data_4,
    output  [CTRL_WIDTH-1:0]           out_ctrl_4,
    output                             out_wr_4,
    input                              out_rdy_4,

    output  [DATA_WIDTH-1:0]           out_data_5,
    output  [CTRL_WIDTH-1:0]           out_ctrl_5,
    output                             out_wr_5,
    input                              out_rdy_5,

    output  [DATA_WIDTH-1:0]           out_data_6,
    output  [CTRL_WIDTH-1:0]           out_ctrl_6,
    output                             out_wr_6,
    input                              out_rdy_6,

    output  [DATA_WIDTH-1:0]           out_data_7,
    output  [CTRL_WIDTH-1:0]           out_ctrl_7,
    output                             out_wr_7,
    input                              out_rdy_7,


     input                              reg_req,
     output                             reg_ack,
     input                              reg_rd_wr_L,
     input  [31:0]                      reg_addr,
     output [31:0]                      reg_rd_data,
     input  [31:0]                      reg_wr_data,


     input                              reset,
     input                              clk,
     
     input                              sim_start
     );




   localparam IN_ARB_STAGE_NUM = 2;
   localparam OP_LUT_STAGE_NUM = 4;
   localparam OQ_STAGE_NUM     = 6;


   wire                             in_arb_in_reg_req;
   wire                             in_arb_in_reg_ack;
   wire                             in_arb_in_reg_rd_wr_L;
   wire [`UDP_REG_ADDR_WIDTH-1:0]   in_arb_in_reg_addr;
   wire [`CPCI_NF2_DATA_WIDTH-1:0]  in_arb_in_reg_data;
   wire [UDP_REG_SRC_WIDTH-1:0]     in_arb_in_reg_src;


   wire [CTRL_WIDTH-1:0]            vlan_rm_in_ctrl;
   wire [DATA_WIDTH-1:0]            vlan_rm_in_data;
   wire                             vlan_rm_in_wr;
   wire                             vlan_rm_in_rdy;


   wire [CTRL_WIDTH-1:0]            op_lut_in_ctrl[3:0];
   wire [DATA_WIDTH-1:0]            op_lut_in_data[3:0];
   wire                             op_lut_in_wr  [3:0];
   wire                             op_lut_in_rdy [3:0];


   wire                             op_lut_in_reg_req;
   wire                             op_lut_in_reg_ack;
   wire                             op_lut_in_reg_rd_wr_L;
   wire [`UDP_REG_ADDR_WIDTH-1:0]   op_lut_in_reg_addr;
   wire [`CPCI_NF2_DATA_WIDTH-1:0]  op_lut_in_reg_data;
   wire [UDP_REG_SRC_WIDTH-1:0]     op_lut_in_reg_src;


   wire [CTRL_WIDTH-1:0]            op_lut_in_ctrl_2;
   wire [DATA_WIDTH-1:0]            op_lut_in_data_2;
   wire                             op_lut_in_wr_2;
   wire                             op_lut_in_rdy_2;

   wire                             op_lut_in_reg_req_2;
   wire                             op_lut_in_reg_ack_2;
   wire                             op_lut_in_reg_rd_wr_L_2;
   wire [`UDP_REG_ADDR_WIDTH-1:0]   op_lut_in_reg_addr_2;
   wire [`CPCI_NF2_DATA_WIDTH-1:0]  op_lut_in_reg_data_2;
   wire [UDP_REG_SRC_WIDTH-1:0]     op_lut_in_reg_src_2;
   

   wire [CTRL_WIDTH-1:0]            op_lut_in_ctrl_3;
   wire [DATA_WIDTH-1:0]            op_lut_in_data_3;
   wire                             op_lut_in_wr_3;
   wire                             op_lut_in_rdy_3;

   wire                             op_lut_in_reg_req_3;
   wire                             op_lut_in_reg_ack_3;
   wire                             op_lut_in_reg_rd_wr_L_3;
   wire [`UDP_REG_ADDR_WIDTH-1:0]   op_lut_in_reg_addr_3;
   wire [`CPCI_NF2_DATA_WIDTH-1:0]  op_lut_in_reg_data_3;
   wire [UDP_REG_SRC_WIDTH-1:0]     op_lut_in_reg_src_3;
   

   wire [CTRL_WIDTH-1:0]            vlan_add_in_ctrl;
   wire [DATA_WIDTH-1:0]            vlan_add_in_data;
   wire                             vlan_add_in_wr;
   wire                             vlan_add_in_rdy;

   wire [CTRL_WIDTH-1:0]            rate_limiter_in_ctrl;
   wire [DATA_WIDTH-1:0]            rate_limiter_in_data;
   wire                             rate_limiter_in_wr;
   wire                             rate_limiter_in_rdy;

   wire                             rate_limiter_in_reg_req;
   wire                             rate_limiter_in_reg_ack;
   wire                             rate_limiter_in_reg_rd_wr_L;
   wire [`UDP_REG_ADDR_WIDTH-1:0]   rate_limiter_in_reg_addr;
   wire [`CPCI_NF2_DATA_WIDTH-1:0]  rate_limiter_in_reg_data;
   wire [UDP_REG_SRC_WIDTH-1:0]     rate_limiter_in_reg_src;


   wire [CTRL_WIDTH-1:0]            oq_in_ctrl;
   wire [DATA_WIDTH-1:0]            oq_in_data;
   wire                             oq_in_wr;
   wire                             oq_in_rdy;

   wire                             oq_in_reg_req;
   wire                             oq_in_reg_ack;
   wire                             oq_in_reg_rd_wr_L;
   wire [`UDP_REG_ADDR_WIDTH-1:0]   oq_in_reg_addr;
   wire [`CPCI_NF2_DATA_WIDTH-1:0]  oq_in_reg_data;
   wire [UDP_REG_SRC_WIDTH-1:0]     oq_in_reg_src;



   
   wire   [31:0]                    data_output_port_lookup_o ;
   wire   [31:0]                    addr_output_port_lookup_o ;
   wire                             req_output_port_lookup_o  ;
   wire                             rw_output_port_lookup_o   ; 


   wire   [31:0]                    data_output_port_lookup_0_o ;
   wire   [31:0]                    data_output_port_lookup_1_o ;
   wire   [31:0]                    data_output_port_lookup_2_o ;
   wire   [31:0]                    data_meter_o                ;
   wire   [31:0]                    data_output_queues_o        ;
   wire   [31:0]                    data_config_o               ;
   
   wire   [31:0]                    addr_output_port_lookup_0_o ;
   wire   [31:0]                    addr_output_port_lookup_1_o ;
   wire   [31:0]                    addr_output_port_lookup_2_o ;
   wire   [31:0]                    addr_meter_o                ;
   wire   [31:0]                    addr_output_queues_o        ;
   wire   [31:0]                    addr_config_o               ;
   
   wire                             req_output_port_lookup_0_o  ;
   wire                             req_output_port_lookup_1_o  ;
   wire                             req_output_port_lookup_2_o  ;
   wire                             req_meter_o                 ;
   wire                             req_output_queues_o         ;
   wire                             req_config_o                ;
   
   wire                             rw_output_port_lookup_0_o   ;
   wire                             rw_output_port_lookup_1_o   ;
   wire                             rw_output_port_lookup_2_o   ;
   wire                             rw_meter_o                  ;
   wire                             rw_output_queues_o          ;
   wire                             rw_config_o                 ;
         
   wire                             ack_output_port_lookup_0_i  ;
   wire                             ack_output_port_lookup_1_i  ;
   wire                             ack_output_port_lookup_2_i  ;
   wire                             ack_meter_i                 ;
   wire                             ack_output_queues_i         ;
   wire                             ack_config_i                ;     
   
   wire   [31:0]                     data_output_port_lookup_0_i;
   wire   [31:0]                     data_output_port_lookup_1_i;
   wire   [31:0]                     data_output_port_lookup_2_i;
   wire   [31:0]                     data_meter_i               ;
   wire   [31:0]                     data_output_queues_i       ;
   wire   [31:0]                     data_config_i              ;
   
   wire                              config_sw_ok; 
   


   input_arbiter
   #(.DATA_WIDTH(DATA_WIDTH),
     .CTRL_WIDTH(CTRL_WIDTH),
     .UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
     .STAGE_NUMBER(IN_ARB_STAGE_NUM))
   input_arbiter
     (
    .out_data             (vlan_rm_in_data),
    .out_ctrl             (vlan_rm_in_ctrl),
    .out_wr               (vlan_rm_in_wr),
    .out_rdy              (vlan_rm_in_rdy),


    .in_data_0            (in_data_0),
    .in_ctrl_0            (in_ctrl_0),
    .in_wr_0              (in_wr_0),
    .in_rdy_0             (in_rdy_0),

    .in_data_1            (in_data_1),
    .in_ctrl_1            (in_ctrl_1),
    .in_wr_1              (in_wr_1),
    .in_rdy_1             (in_rdy_1),

    .in_data_2            (in_data_2),
    .in_ctrl_2            (in_ctrl_2),
    .in_wr_2              (in_wr_2),
    .in_rdy_2             (in_rdy_2),

    .in_data_3            (in_data_3),
    .in_ctrl_3            (in_ctrl_3),
    .in_wr_3              (in_wr_3),
    .in_rdy_3             (in_rdy_3),

    .in_data_4            (in_data_4),
    .in_ctrl_4            (in_ctrl_4),
    .in_wr_4              (in_wr_4),
    .in_rdy_4             (in_rdy_4),

    .in_data_5            (in_data_5),
    .in_ctrl_5            (in_ctrl_5),
    .in_wr_5              (in_wr_5),
    .in_rdy_5             (in_rdy_5),

    .in_data_6            (in_data_6),
    .in_ctrl_6            (in_ctrl_6),
    .in_wr_6              (in_wr_6),
    .in_rdy_6             (in_rdy_6),

    .in_data_7            (in_data_7),
    .in_ctrl_7            (in_ctrl_7),
    .in_wr_7              (in_wr_7),
    .in_rdy_7             (in_rdy_7),





    .reset                (reset),
    .clk                  (clk)
    );

   vlan_remover
     #(.DATA_WIDTH(DATA_WIDTH),
       .CTRL_WIDTH(CTRL_WIDTH))
   vlan_remover
   (
    .in_data            (vlan_rm_in_data),
    .in_ctrl            (vlan_rm_in_ctrl),
    .in_wr              (vlan_rm_in_wr),
    .in_rdy             (vlan_rm_in_rdy),


    .out_data           (op_lut_in_data[0]),
    .out_ctrl           (op_lut_in_ctrl[0]),
    .out_wr             (op_lut_in_wr  [0]),
    .out_rdy            (op_lut_in_rdy [0]),



    .reset              (reset),
    .clk                (clk)
    );


   


   wire [`TABLE_NUM-1:0]   ack_output_port_lookup_i_hub;
   wire [31:0]            data_output_port_lookup_i_hub [`TABLE_NUM-1:0];
      
   generate 
      genvar i;
      for(i = 0; i < `TABLE_NUM; i = i + 1)
      begin : output_port_lookup
         output_port_lookup
         #(
            .DATA_WIDTH                               (DATA_WIDTH),
            .CTRL_WIDTH                               (CTRL_WIDTH),
            .NUM_OUTPUT_QUEUES                        (NUM_OUTPUT_QUEUES),
            .OPENFLOW_ENTRY_WIDTH                     (`T0_OPENFLOW_ENTRY_WIDTH),
            .OPENFLOW_WILDCARD_TABLE_SIZE             (`T0_OPENFLOW_WILDCARD_TABLE_SIZE),
            .CURRENT_TABLE_ID                         (i),
            .TABLE_NUM                                (`TABLE_NUM-1)
         )
         output_port_lookup
          (
           .out_data          (op_lut_in_data [i+1]),
           .out_ctrl          (op_lut_in_ctrl [i+1]),
           .out_wr            (op_lut_in_wr   [i+1]),
           .out_rdy           (op_lut_in_rdy  [i+1]),


           .in_data           (op_lut_in_data [i]),
           .in_ctrl           (op_lut_in_ctrl [i]),
           .in_wr             (op_lut_in_wr   [i]),
           .in_rdy            (op_lut_in_rdy  [i]),


           .data_output_port_lookup_i  (data_output_port_lookup_o) ,
           .addr_output_port_lookup_i  (addr_output_port_lookup_o) ,
           .req_output_port_lookup_i   (req_output_port_lookup_o ) ,
           .rw_output_port_lookup_i    (rw_output_port_lookup_o  ) ,
           .ack_output_port_lookup_o   (ack_output_port_lookup_i_hub[i] ) ,
           .data_output_port_lookup_o  (data_output_port_lookup_i_hub[i]) ,
           
           .config_sw_ok      (config_sw_ok),


           .table_flush       (1'b0),


           .clk               (clk),
           .reset             (reset)
         );         
      end
   endgenerate  


   reg ack_output_port_lookup_i;
   reg [31:0]data_output_port_lookup_i;
   reg [2:0]cur_st,nxt_st;
   reg [`TABLE_NUM-1:0]addr;
   
   localparam    IDLE=0,
                 WAIT_ACK=1,
                 ACK=2;
                 
   always@(posedge clk)
     if(reset)
        cur_st<=0;
     else cur_st<=nxt_st;
  
  
   always@(*)
   begin
     nxt_st=cur_st;
     case(cur_st)
        IDLE:
           if(req_output_port_lookup_o) nxt_st=WAIT_ACK;
        WAIT_ACK:
           if(ack_output_port_lookup_i_hub[addr]) nxt_st=ACK;
        ACK:
           nxt_st=IDLE;
        default:nxt_st=IDLE;
     endcase
  end
  
  always@(posedge clk)
     if(reset)
        addr<=0;
     else if(cur_st==IDLE && req_output_port_lookup_o)
        addr<=addr_output_port_lookup_o[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS];
           
  always@(posedge clk)
     if(reset)
        ack_output_port_lookup_i<=0;
     else if(cur_st==ACK)
        ack_output_port_lookup_i<=1;
     else ack_output_port_lookup_i<=0;
     
     
  always@(posedge clk)
     if(reset)
        data_output_port_lookup_i<=0;
     else if(cur_st==ACK)
        data_output_port_lookup_i<=data_output_port_lookup_i_hub[addr];
        
           
   vlan_adder
   #(.DATA_WIDTH(DATA_WIDTH),
     .CTRL_WIDTH(CTRL_WIDTH))
   vlan_adder
   (
      .in_data            (op_lut_in_data[`TABLE_NUM]),
      .in_ctrl            (op_lut_in_ctrl[`TABLE_NUM]),
      .in_wr              (op_lut_in_wr  [`TABLE_NUM]),
      .in_rdy             (op_lut_in_rdy [`TABLE_NUM]),
   

      .out_data             (rate_limiter_in_data),
      .out_ctrl             (rate_limiter_in_ctrl),
      .out_wr               (rate_limiter_in_wr),
      .out_rdy              (rate_limiter_in_rdy),
   

      .reset              (reset),
      .clk                (clk)
   );
          
   meter_lite meter_lite (

      .in_data                            (rate_limiter_in_data),
      .in_ctrl                            (rate_limiter_in_ctrl),
      .in_rdy                             (rate_limiter_in_rdy),
      .in_wr                              (rate_limiter_in_wr),
      
      .out_data                           (oq_in_data),
      .out_ctrl                           (oq_in_ctrl),
      .out_wr                             (oq_in_wr),
      .out_rdy                            (oq_in_rdy),
     
      .data_meter_i    (data_meter_o) ,
      .addr_meter_i    (addr_meter_o) ,
      .req_meter_i     (req_meter_o ) ,
      .rw_meter_i      (rw_meter_o  ) ,
      .ack_meter_o     (ack_meter_i ) ,
      .data_meter_o    (data_meter_i) ,
     

      .clk                                (clk),
      .reset                              (reset)

   );

   output_queues
   #(.DATA_WIDTH(DATA_WIDTH),
       .CTRL_WIDTH(CTRL_WIDTH),
       .UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
       .OP_LUT_STAGE_NUM(OP_LUT_STAGE_NUM),
       .NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES)
   )
   output_queues
     (
    .out_data_0       (out_data_0),
    .out_ctrl_0       (out_ctrl_0),
    .out_wr_0         (out_wr_0),
    .out_rdy_0        (out_rdy_0),

    .out_data_1       (out_data_1),
    .out_ctrl_1       (out_ctrl_1),
    .out_wr_1         (out_wr_1),
    .out_rdy_1        (out_rdy_1),

    .out_data_2       (out_data_2),
    .out_ctrl_2       (out_ctrl_2),
    .out_wr_2         (out_wr_2),
    .out_rdy_2        (out_rdy_2),

    .out_data_3       (out_data_3),
    .out_ctrl_3       (out_ctrl_3),
    .out_wr_3         (out_wr_3),
    .out_rdy_3        (out_rdy_3),

    .out_data_4       (out_data_4),
    .out_ctrl_4       (out_ctrl_4),
    .out_wr_4         (out_wr_4),
    .out_rdy_4        (out_rdy_4),

    .out_data_5       (out_data_5),
    .out_ctrl_5       (out_ctrl_5),
    .out_wr_5         (out_wr_5),
    .out_rdy_5        (out_rdy_5),

    .out_data_6       (out_data_6),
    .out_ctrl_6       (out_ctrl_6),
    .out_wr_6         (out_wr_6),
    .out_rdy_6        (out_rdy_6),

    .out_data_7       (out_data_7),
    .out_ctrl_7       (out_ctrl_7),
    .out_wr_7         (out_wr_7),
    .out_rdy_7        (out_rdy_7),


    .in_data          (oq_in_data),
    .in_ctrl          (oq_in_ctrl),
    .in_rdy           (oq_in_rdy),
    .in_wr            (oq_in_wr),


    .data_output_queues_i  (data_output_queues_o),
    .addr_output_queues_i  (addr_output_queues_o),
    .req_output_queues_i   (req_output_queues_o),
    .rw_output_queues_i    (rw_output_queues_o),
    .ack_output_queues_o   (ack_output_queues_i),
    .data_output_queues_o  (data_output_queues_i),


    .clk              (clk),
    .reset            (reset));















   udp_reg_master
   #(
      .TABLE_NUM  (`TABLE_NUM-1)
   )
    udp_reg_master 
   (
     .reg_req_in                            (reg_req),
     .reg_ack                               (reg_ack),
     .reg_rd_wr_L_in                        (reg_rd_wr_L),
     .reg_addr_in                           (reg_addr),
     .reg_data_in                           (reg_wr_data),
     .reg_rd_data                           (reg_rd_data),

     .data_output_port_lookup_o            (data_output_port_lookup_o) ,

     .data_meter_o                           (data_meter_o               ) ,
     .data_output_queues_o                   (data_output_queues_o       ) ,
     .data_config_o                          (data_config_o              ) ,
                                            
     .addr_output_port_lookup_o            (addr_output_port_lookup_o) ,

     .addr_meter_o                           (addr_meter_o               ) ,
     .addr_output_queues_o                   (addr_output_queues_o       ) ,
     .addr_config_o                          (addr_config_o              ) ,
                                            
     .req_output_port_lookup_o             (req_output_port_lookup_o ),

     .req_meter_o                            (req_meter_o                ) ,
     .req_output_queues_o                    (req_output_queues_o        ) ,
     .req_config_o                           (req_config_o               ) ,
                                            
     .rw_output_port_lookup_o              (rw_output_port_lookup_o  ) ,

     .rw_meter_o                             (rw_meter_o                 ) ,
     .rw_output_queues_o                     (rw_output_queues_o         ) ,
     .rw_config_o                            (rw_config_o                ) ,
                                            
     .ack_output_port_lookup_i             (ack_output_port_lookup_i ) ,

     .ack_meter_i                            (ack_meter_i                ) ,
     .ack_output_queues_i                    (ack_output_queues_i        ) ,
     .ack_config_i                           (ack_config_i               ) ,     
                                            
     .data_output_port_lookup_i            (data_output_port_lookup_i) ,

     .data_meter_i                           (data_meter_i               ) ,
     .data_output_queues_i                   (data_output_queues_i       ) ,
     .data_config_i                          (data_config_i              ) ,
    

     .clk                                   (clk),
     .reset                                 (reset)
     );
          

    configuration configuration
   (
      .data_config_i  (data_config_o),
      .addr_config_i  (addr_config_o),
      .req_config_i   (req_config_o),
      .rw_config_i    (rw_config_o),
      .ack_config_o   (ack_config_i),
      .data_config_o  (data_config_i),
   
      .clk     (clk),
      .reset   (reset),
      
      .config_sw_ok  (config_sw_ok)
   );
     

     
     

     



endmodule
module user_data_path
  #(parameter DATA_WIDTH = 64,
    parameter CTRL_WIDTH=DATA_WIDTH/8,
    parameter UDP_REG_SRC_WIDTH = 2,
    parameter NUM_OUTPUT_QUEUES = 8,
    parameter NUM_INPUT_QUEUES = 8
   )
   (
    input  [DATA_WIDTH-1:0]            in_data_0,
    input  [CTRL_WIDTH-1:0]            in_ctrl_0,
    input                              in_wr_0,
    output                             in_rdy_0,

    input  [DATA_WIDTH-1:0]            in_data_1,
    input  [CTRL_WIDTH-1:0]            in_ctrl_1,
    input                              in_wr_1,
    output                             in_rdy_1,

    input  [DATA_WIDTH-1:0]            in_data_2,
    input  [CTRL_WIDTH-1:0]            in_ctrl_2,
    input                              in_wr_2,
    output                             in_rdy_2,

    input  [DATA_WIDTH-1:0]            in_data_3,
    input  [CTRL_WIDTH-1:0]            in_ctrl_3,
    input                              in_wr_3,
    output                             in_rdy_3,

    input  [DATA_WIDTH-1:0]            in_data_4,
    input  [CTRL_WIDTH-1:0]            in_ctrl_4,
    input                              in_wr_4,
    output                             in_rdy_4,

    input  [DATA_WIDTH-1:0]            in_data_5,
    input  [CTRL_WIDTH-1:0]            in_ctrl_5,
    input                              in_wr_5,
    output                             in_rdy_5,

    input  [DATA_WIDTH-1:0]            in_data_6,
    input  [CTRL_WIDTH-1:0]            in_ctrl_6,
    input                              in_wr_6,
    output                             in_rdy_6,

    input  [DATA_WIDTH-1:0]            in_data_7,
    input  [CTRL_WIDTH-1:0]            in_ctrl_7,
    input                              in_wr_7,
    output                             in_rdy_7,

    output  [DATA_WIDTH-1:0]           out_data_0,
    output  [CTRL_WIDTH-1:0]           out_ctrl_0,
    output                             out_wr_0,
    input                              out_rdy_0,

    output  [DATA_WIDTH-1:0]           out_data_1,
    output  [CTRL_WIDTH-1:0]           out_ctrl_1,
    output                             out_wr_1,
    input                              out_rdy_1,

    output  [DATA_WIDTH-1:0]           out_data_2,
    output  [CTRL_WIDTH-1:0]           out_ctrl_2,
    output                             out_wr_2,
    input                              out_rdy_2,

    output  [DATA_WIDTH-1:0]           out_data_3,
    output  [CTRL_WIDTH-1:0]           out_ctrl_3,
    output                             out_wr_3,
    input                              out_rdy_3,

    output  [DATA_WIDTH-1:0]           out_data_4,
    output  [CTRL_WIDTH-1:0]           out_ctrl_4,
    output                             out_wr_4,
    input                              out_rdy_4,

    output  [DATA_WIDTH-1:0]           out_data_5,
    output  [CTRL_WIDTH-1:0]           out_ctrl_5,
    output                             out_wr_5,
    input                              out_rdy_5,

    output  [DATA_WIDTH-1:0]           out_data_6,
    output  [CTRL_WIDTH-1:0]           out_ctrl_6,
    output                             out_wr_6,
    input                              out_rdy_6,

    output  [DATA_WIDTH-1:0]           out_data_7,
    output  [CTRL_WIDTH-1:0]           out_ctrl_7,
    output                             out_wr_7,
    input                              out_rdy_7,


     input                              reg_req,
     output                             reg_ack,
     input                              reg_rd_wr_L,
     input  [31:0]                      reg_addr,
     output [31:0]                      reg_rd_data,
     input  [31:0]                      reg_wr_data,


     input                              reset,
     input                              clk,
     
     input                              sim_start
     );





   localparam IN_ARB_STAGE_NUM = 2;
   localparam OP_LUT_STAGE_NUM = 4;
   localparam OQ_STAGE_NUM     = 6;


   wire                             in_arb_in_reg_req;
   wire                             in_arb_in_reg_ack;
   wire                             in_arb_in_reg_rd_wr_L;
   wire [`UDP_REG_ADDR_WIDTH-1:0]   in_arb_in_reg_addr;
   wire [`CPCI_NF2_DATA_WIDTH-1:0]  in_arb_in_reg_data;
   wire [UDP_REG_SRC_WIDTH-1:0]     in_arb_in_reg_src;


   wire [CTRL_WIDTH-1:0]            vlan_rm_in_ctrl;
   wire [DATA_WIDTH-1:0]            vlan_rm_in_data;
   wire                             vlan_rm_in_wr;
   wire                             vlan_rm_in_rdy;


   wire [CTRL_WIDTH-1:0]            op_lut_in_ctrl[3:0];
   wire [DATA_WIDTH-1:0]            op_lut_in_data[3:0];
   wire                             op_lut_in_wr  [3:0];
   wire                             op_lut_in_rdy [3:0];


   wire                             op_lut_in_reg_req;
   wire                             op_lut_in_reg_ack;
   wire                             op_lut_in_reg_rd_wr_L;
   wire [`UDP_REG_ADDR_WIDTH-1:0]   op_lut_in_reg_addr;
   wire [`CPCI_NF2_DATA_WIDTH-1:0]  op_lut_in_reg_data;
   wire [UDP_REG_SRC_WIDTH-1:0]     op_lut_in_reg_src;


   wire [CTRL_WIDTH-1:0]            op_lut_in_ctrl_2;
   wire [DATA_WIDTH-1:0]            op_lut_in_data_2;
   wire                             op_lut_in_wr_2;
   wire                             op_lut_in_rdy_2;

   wire                             op_lut_in_reg_req_2;
   wire                             op_lut_in_reg_ack_2;
   wire                             op_lut_in_reg_rd_wr_L_2;
   wire [`UDP_REG_ADDR_WIDTH-1:0]   op_lut_in_reg_addr_2;
   wire [`CPCI_NF2_DATA_WIDTH-1:0]  op_lut_in_reg_data_2;
   wire [UDP_REG_SRC_WIDTH-1:0]     op_lut_in_reg_src_2;
   

   wire [CTRL_WIDTH-1:0]            op_lut_in_ctrl_3;
   wire [DATA_WIDTH-1:0]            op_lut_in_data_3;
   wire                             op_lut_in_wr_3;
   wire                             op_lut_in_rdy_3;

   wire                             op_lut_in_reg_req_3;
   wire                             op_lut_in_reg_ack_3;
   wire                             op_lut_in_reg_rd_wr_L_3;
   wire [`UDP_REG_ADDR_WIDTH-1:0]   op_lut_in_reg_addr_3;
   wire [`CPCI_NF2_DATA_WIDTH-1:0]  op_lut_in_reg_data_3;
   wire [UDP_REG_SRC_WIDTH-1:0]     op_lut_in_reg_src_3;
   

   wire [CTRL_WIDTH-1:0]            vlan_add_in_ctrl;
   wire [DATA_WIDTH-1:0]            vlan_add_in_data;
   wire                             vlan_add_in_wr;
   wire                             vlan_add_in_rdy;

   wire [CTRL_WIDTH-1:0]            rate_limiter_in_ctrl;
   wire [DATA_WIDTH-1:0]            rate_limiter_in_data;
   wire                             rate_limiter_in_wr;
   wire                             rate_limiter_in_rdy;

   wire                             rate_limiter_in_reg_req;
   wire                             rate_limiter_in_reg_ack;
   wire                             rate_limiter_in_reg_rd_wr_L;
   wire [`UDP_REG_ADDR_WIDTH-1:0]   rate_limiter_in_reg_addr;
   wire [`CPCI_NF2_DATA_WIDTH-1:0]  rate_limiter_in_reg_data;
   wire [UDP_REG_SRC_WIDTH-1:0]     rate_limiter_in_reg_src;


   wire [CTRL_WIDTH-1:0]            oq_in_ctrl;
   wire [DATA_WIDTH-1:0]            oq_in_data;
   wire                             oq_in_wr;
   wire                             oq_in_rdy;

   wire                             oq_in_reg_req;
   wire                             oq_in_reg_ack;
   wire                             oq_in_reg_rd_wr_L;
   wire [`UDP_REG_ADDR_WIDTH-1:0]   oq_in_reg_addr;
   wire [`CPCI_NF2_DATA_WIDTH-1:0]  oq_in_reg_data;
   wire [UDP_REG_SRC_WIDTH-1:0]     oq_in_reg_src;



   
   wire   [31:0]                    data_output_port_lookup_o ;
   wire   [31:0]                    addr_output_port_lookup_o ;
   wire                             req_output_port_lookup_o  ;
   wire                             rw_output_port_lookup_o   ; 


   wire   [31:0]                    data_output_port_lookup_0_o ;
   wire   [31:0]                    data_output_port_lookup_1_o ;
   wire   [31:0]                    data_output_port_lookup_2_o ;
   wire   [31:0]                    data_meter_o                ;
   wire   [31:0]                    data_output_queues_o        ;
   wire   [31:0]                    data_config_o               ;
   
   wire   [31:0]                    addr_output_port_lookup_0_o ;
   wire   [31:0]                    addr_output_port_lookup_1_o ;
   wire   [31:0]                    addr_output_port_lookup_2_o ;
   wire   [31:0]                    addr_meter_o                ;
   wire   [31:0]                    addr_output_queues_o        ;
   wire   [31:0]                    addr_config_o               ;
   
   wire                             req_output_port_lookup_0_o  ;
   wire                             req_output_port_lookup_1_o  ;
   wire                             req_output_port_lookup_2_o  ;
   wire                             req_meter_o                 ;
   wire                             req_output_queues_o         ;
   wire                             req_config_o                ;
   
   wire                             rw_output_port_lookup_0_o   ;
   wire                             rw_output_port_lookup_1_o   ;
   wire                             rw_output_port_lookup_2_o   ;
   wire                             rw_meter_o                  ;
   wire                             rw_output_queues_o          ;
   wire                             rw_config_o                 ;
         
   wire                             ack_output_port_lookup_0_i  ;
   wire                             ack_output_port_lookup_1_i  ;
   wire                             ack_output_port_lookup_2_i  ;
   wire                             ack_meter_i                 ;
   wire                             ack_output_queues_i         ;
   wire                             ack_config_i                ;     
   
   wire   [31:0]                     data_output_port_lookup_0_i;
   wire   [31:0]                     data_output_port_lookup_1_i;
   wire   [31:0]                     data_output_port_lookup_2_i;
   wire   [31:0]                     data_meter_i               ;
   wire   [31:0]                     data_output_queues_i       ;
   wire   [31:0]                     data_config_i              ;
   
   wire                              config_sw_ok; 
   


   input_arbiter
   #(.DATA_WIDTH(DATA_WIDTH),
     .CTRL_WIDTH(CTRL_WIDTH),
     .UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
     .STAGE_NUMBER(IN_ARB_STAGE_NUM))
   input_arbiter
     (
    .out_data             (vlan_rm_in_data),
    .out_ctrl             (vlan_rm_in_ctrl),
    .out_wr               (vlan_rm_in_wr),
    .out_rdy              (vlan_rm_in_rdy),


    .in_data_0            (in_data_0),
    .in_ctrl_0            (in_ctrl_0),
    .in_wr_0              (in_wr_0),
    .in_rdy_0             (in_rdy_0),

    .in_data_1            (in_data_1),
    .in_ctrl_1            (in_ctrl_1),
    .in_wr_1              (in_wr_1),
    .in_rdy_1             (in_rdy_1),

    .in_data_2            (in_data_2),
    .in_ctrl_2            (in_ctrl_2),
    .in_wr_2              (in_wr_2),
    .in_rdy_2             (in_rdy_2),

    .in_data_3            (in_data_3),
    .in_ctrl_3            (in_ctrl_3),
    .in_wr_3              (in_wr_3),
    .in_rdy_3             (in_rdy_3),

    .in_data_4            (in_data_4),
    .in_ctrl_4            (in_ctrl_4),
    .in_wr_4              (in_wr_4),
    .in_rdy_4             (in_rdy_4),

    .in_data_5            (in_data_5),
    .in_ctrl_5            (in_ctrl_5),
    .in_wr_5              (in_wr_5),
    .in_rdy_5             (in_rdy_5),

    .in_data_6            (in_data_6),
    .in_ctrl_6            (in_ctrl_6),
    .in_wr_6              (in_wr_6),
    .in_rdy_6             (in_rdy_6),

    .in_data_7            (in_data_7),
    .in_ctrl_7            (in_ctrl_7),
    .in_wr_7              (in_wr_7),
    .in_rdy_7             (in_rdy_7),





    .reset                (reset),
    .clk                  (clk)
    );

   vlan_remover
     #(.DATA_WIDTH(DATA_WIDTH),
       .CTRL_WIDTH(CTRL_WIDTH))
   vlan_remover
   (
    .in_data            (vlan_rm_in_data),
    .in_ctrl            (vlan_rm_in_ctrl),
    .in_wr              (vlan_rm_in_wr),
    .in_rdy             (vlan_rm_in_rdy),


    .out_data           (op_lut_in_data[0]),
    .out_ctrl           (op_lut_in_ctrl[0]),
    .out_wr             (op_lut_in_wr  [0]),
    .out_rdy            (op_lut_in_rdy [0]),



    .reset              (reset),
    .clk                (clk)
    );


   


   wire [`TABLE_NUM-1:0]   ack_output_port_lookup_i_hub;
   wire [31:0]            data_output_port_lookup_i_hub [`TABLE_NUM-1:0];
      
   generate 
      genvar i;
      for(i = 0; i < `TABLE_NUM; i = i + 1)
      begin : output_port_lookup
         output_port_lookup
         #(
            .DATA_WIDTH                               (DATA_WIDTH),
            .CTRL_WIDTH                               (CTRL_WIDTH),
            .NUM_OUTPUT_QUEUES                        (NUM_OUTPUT_QUEUES),
            .OPENFLOW_ENTRY_WIDTH                     (`T0_OPENFLOW_ENTRY_WIDTH),
            .OPENFLOW_WILDCARD_TABLE_SIZE             (`T0_OPENFLOW_WILDCARD_TABLE_SIZE),
            .CURRENT_TABLE_ID                         (i),
            .TABLE_NUM                                (`TABLE_NUM-1)
         )
         output_port_lookup
          (
           .out_data          (op_lut_in_data [i+1]),
           .out_ctrl          (op_lut_in_ctrl [i+1]),
           .out_wr            (op_lut_in_wr   [i+1]),
           .out_rdy           (op_lut_in_rdy  [i+1]),


           .in_data           (op_lut_in_data [i]),
           .in_ctrl           (op_lut_in_ctrl [i]),
           .in_wr             (op_lut_in_wr   [i]),
           .in_rdy            (op_lut_in_rdy  [i]),


           .data_output_port_lookup_i  (data_output_port_lookup_o) ,
           .addr_output_port_lookup_i  (addr_output_port_lookup_o) ,
           .req_output_port_lookup_i   (req_output_port_lookup_o ) ,
           .rw_output_port_lookup_i    (rw_output_port_lookup_o  ) ,
           .ack_output_port_lookup_o   (ack_output_port_lookup_i_hub[i] ) ,
           .data_output_port_lookup_o  (data_output_port_lookup_i_hub[i]) ,
           
           .config_sw_ok      (config_sw_ok),


           .table_flush       (1'b0),


           .clk               (clk),
           .reset             (reset)
         );         
      end
   endgenerate  


   reg ack_output_port_lookup_i;
   reg [31:0]data_output_port_lookup_i;
   reg [2:0]cur_st,nxt_st;
   reg [`TABLE_NUM-1:0]addr;
   
   localparam    IDLE=0,
                 WAIT_ACK=1,
                 ACK=2;
                 
   always@(posedge clk)
     if(reset)
        cur_st<=0;
     else cur_st<=nxt_st;
  
  
   always@(*)
   begin
     nxt_st=cur_st;
     case(cur_st)
        IDLE:
           if(req_output_port_lookup_o) nxt_st=WAIT_ACK;
        WAIT_ACK:
           if(ack_output_port_lookup_i_hub[addr]) nxt_st=ACK;
        ACK:
           nxt_st=IDLE;
        default:nxt_st=IDLE;
     endcase
  end
  
  always@(posedge clk)
     if(reset)
        addr<=0;
     else if(cur_st==IDLE && req_output_port_lookup_o)
        addr<=addr_output_port_lookup_o[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS];
           
  always@(posedge clk)
     if(reset)
        ack_output_port_lookup_i<=0;
     else if(cur_st==ACK)
        ack_output_port_lookup_i<=1;
     else ack_output_port_lookup_i<=0;
     
     
  always@(posedge clk)
     if(reset)
        data_output_port_lookup_i<=0;
     else if(cur_st==ACK)
        data_output_port_lookup_i<=data_output_port_lookup_i_hub[addr];
        
           
   vlan_adder
   #(.DATA_WIDTH(DATA_WIDTH),
     .CTRL_WIDTH(CTRL_WIDTH))
   vlan_adder
   (
      .in_data            (op_lut_in_data[`TABLE_NUM]),
      .in_ctrl            (op_lut_in_ctrl[`TABLE_NUM]),
      .in_wr              (op_lut_in_wr  [`TABLE_NUM]),
      .in_rdy             (op_lut_in_rdy [`TABLE_NUM]),
   

      .out_data             (rate_limiter_in_data),
      .out_ctrl             (rate_limiter_in_ctrl),
      .out_wr               (rate_limiter_in_wr),
      .out_rdy              (rate_limiter_in_rdy),
   

      .reset              (reset),
      .clk                (clk)
   );
          
   meter_lite meter_lite (

      .in_data                            (rate_limiter_in_data),
      .in_ctrl                            (rate_limiter_in_ctrl),
      .in_rdy                             (rate_limiter_in_rdy),
      .in_wr                              (rate_limiter_in_wr),
      
      .out_data                           (oq_in_data),
      .out_ctrl                           (oq_in_ctrl),
      .out_wr                             (oq_in_wr),
      .out_rdy                            (oq_in_rdy),
     
      .data_meter_i    (data_meter_o) ,
      .addr_meter_i    (addr_meter_o) ,
      .req_meter_i     (req_meter_o ) ,
      .rw_meter_i      (rw_meter_o  ) ,
      .ack_meter_o     (ack_meter_i ) ,
      .data_meter_o    (data_meter_i) ,
     

      .clk                                (clk),
      .reset                              (reset)

   );

   output_queues
   #(.DATA_WIDTH(DATA_WIDTH),
       .CTRL_WIDTH(CTRL_WIDTH),
       .UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
       .OP_LUT_STAGE_NUM(OP_LUT_STAGE_NUM),
       .NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES)
   )
   output_queues
     (
    .out_data_0       (out_data_0),
    .out_ctrl_0       (out_ctrl_0),
    .out_wr_0         (out_wr_0),
    .out_rdy_0        (out_rdy_0),

    .out_data_1       (out_data_1),
    .out_ctrl_1       (out_ctrl_1),
    .out_wr_1         (out_wr_1),
    .out_rdy_1        (out_rdy_1),

    .out_data_2       (out_data_2),
    .out_ctrl_2       (out_ctrl_2),
    .out_wr_2         (out_wr_2),
    .out_rdy_2        (out_rdy_2),

    .out_data_3       (out_data_3),
    .out_ctrl_3       (out_ctrl_3),
    .out_wr_3         (out_wr_3),
    .out_rdy_3        (out_rdy_3),

    .out_data_4       (out_data_4),
    .out_ctrl_4       (out_ctrl_4),
    .out_wr_4         (out_wr_4),
    .out_rdy_4        (out_rdy_4),

    .out_data_5       (out_data_5),
    .out_ctrl_5       (out_ctrl_5),
    .out_wr_5         (out_wr_5),
    .out_rdy_5        (out_rdy_5),

    .out_data_6       (out_data_6),
    .out_ctrl_6       (out_ctrl_6),
    .out_wr_6         (out_wr_6),
    .out_rdy_6        (out_rdy_6),

    .out_data_7       (out_data_7),
    .out_ctrl_7       (out_ctrl_7),
    .out_wr_7         (out_wr_7),
    .out_rdy_7        (out_rdy_7),


    .in_data          (oq_in_data),
    .in_ctrl          (oq_in_ctrl),
    .in_rdy           (oq_in_rdy),
    .in_wr            (oq_in_wr),


    .data_output_queues_i  (data_output_queues_o),
    .addr_output_queues_i  (addr_output_queues_o),
    .req_output_queues_i   (req_output_queues_o),
    .rw_output_queues_i    (rw_output_queues_o),
    .ack_output_queues_o   (ack_output_queues_i),
    .data_output_queues_o  (data_output_queues_i),


    .clk              (clk),
    .reset            (reset));















   udp_reg_master
   #(
      .TABLE_NUM  (`TABLE_NUM-1)
   )
    udp_reg_master 
   (
     .reg_req_in                            (reg_req),
     .reg_ack                               (reg_ack),
     .reg_rd_wr_L_in                        (reg_rd_wr_L),
     .reg_addr_in                           (reg_addr),
     .reg_data_in                           (reg_wr_data),
     .reg_rd_data                           (reg_rd_data),

     .data_output_port_lookup_o            (data_output_port_lookup_o) ,

     .data_meter_o                           (data_meter_o               ) ,
     .data_output_queues_o                   (data_output_queues_o       ) ,
     .data_config_o                          (data_config_o              ) ,
                                            
     .addr_output_port_lookup_o            (addr_output_port_lookup_o) ,

     .addr_meter_o                           (addr_meter_o               ) ,
     .addr_output_queues_o                   (addr_output_queues_o       ) ,
     .addr_config_o                          (addr_config_o              ) ,
                                            
     .req_output_port_lookup_o             (req_output_port_lookup_o ),

     .req_meter_o                            (req_meter_o                ) ,
     .req_output_queues_o                    (req_output_queues_o        ) ,
     .req_config_o                           (req_config_o               ) ,
                                            
     .rw_output_port_lookup_o              (rw_output_port_lookup_o  ) ,

     .rw_meter_o                             (rw_meter_o                 ) ,
     .rw_output_queues_o                     (rw_output_queues_o         ) ,
     .rw_config_o                            (rw_config_o                ) ,
                                            
     .ack_output_port_lookup_i             (ack_output_port_lookup_i ) ,

     .ack_meter_i                            (ack_meter_i                ) ,
     .ack_output_queues_i                    (ack_output_queues_i        ) ,
     .ack_config_i                           (ack_config_i               ) ,     
                                            
     .data_output_port_lookup_i            (data_output_port_lookup_i) ,

     .data_meter_i                           (data_meter_i               ) ,
     .data_output_queues_i                   (data_output_queues_i       ) ,
     .data_config_i                          (data_config_i              ) ,
    

     .clk                                   (clk),
     .reset                                 (reset)
     );
          

    configuration configuration
   (
      .data_config_i  (data_config_o),
      .addr_config_i  (addr_config_o),
      .req_config_i   (req_config_o),
      .rw_config_i    (rw_config_o),
      .ack_config_o   (ack_config_i),
      .data_config_o  (data_config_i),
   
      .clk     (clk),
      .reset   (reset),
      
      .config_sw_ok  (config_sw_ok)
   );
     

     
     

     



endmodule