data/full_repos/permissive/122125962/hardware/SDRv1_src/fm_demux.v
1: b"%Error: data/full_repos/permissive/122125962/hardware/SDRv1_src/fm_demux.v:122: Cannot find file containing module: 'signed_mult8x8'\nsigned_mult8x8 mult_0(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122125962/hardware/SDRv1_src,data/full_repos/permissive/122125962/signed_mult8x8\n             data/full_repos/permissive/122125962/hardware/SDRv1_src,data/full_repos/permissive/122125962/signed_mult8x8.v\n             data/full_repos/permissive/122125962/hardware/SDRv1_src,data/full_repos/permissive/122125962/signed_mult8x8.sv\n             signed_mult8x8\n             signed_mult8x8.v\n             signed_mult8x8.sv\n             obj_dir/signed_mult8x8\n             obj_dir/signed_mult8x8.v\n             obj_dir/signed_mult8x8.sv\n%Error: data/full_repos/permissive/122125962/hardware/SDRv1_src/fm_demux.v:128: Cannot find file containing module: 'signed_mult8x8'\nsigned_mult8x8 mult_1(\n^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module fx_demux(in_phase, quad_phase, adc_clock, resetn, bit_decode, signal_strength);

input			adc_clock, resetn;
input	[7:0]	in_phase, quad_phase;
output			bit_decode;
output	[7:0]	signal_strength;


reg		[7:0]	I_smp, Q_smp, I_pre_smp, Q_pre_smp;




wire signed	[15:0]	mult0, mult1;
wire signed	[16:0]	mult_result = mult1 - mult0;
reg	 signed	[16:0]	mult_pre_result;
`define	MSB_RES	16


wire signed	[`MSB_RES+1:0]	mult_result_avg = mult_result + mult_pre_result;
reg		[`MSB_RES+1:0]	mult_res0, mult_res1, mult_res2, mult_res3, mult_res4, mult_res5, mult_res6, mult_res7, mult_res8;
wire	[`MSB_RES+4:0]	mult_res0_extend = {{3{mult_res0[`MSB_RES+1]}}, mult_res0};
wire	[`MSB_RES+4:0]	mult_res8_extend = {{3{mult_res8[`MSB_RES+1]}}, mult_res8};
wire	[`MSB_RES+4:0]	mult_res8_extend_rev = (mult_res8_extend[`MSB_RES+4])? ~(mult_res8_extend - 1) : (~mult_res8_extend + 1);
reg		[`MSB_RES+4:0]	result_integ;

wire	[7:0]	I_smp_abs = (I_smp[7])? ~(I_smp) : I_smp;
wire	[7:0]	Q_smp_abs = (Q_smp[7])? ~(Q_smp) : Q_smp;
wire	[7:0]	signal_strength = I_smp_abs[6:0] + Q_smp_abs[6:0];
wire	bit_decode = (result_integ[`MSB_RES+4])? 0 : 1;


always @ (posedge adc_clock)
begin
	if (~resetn)
	begin
		mult_pre_result		<= 0;
		result_integ		<= 0;
		mult_res0			<= 0;
		mult_res1			<= 0;
		mult_res2			<= 0;
		mult_res3			<= 0;
		mult_res4			<= 0;
		mult_res5			<= 0;
		mult_res6			<= 0;
		mult_res7			<= 0;
		mult_res8			<= 0;
	end
	else
	begin
		mult_pre_result		<= mult_result;
		result_integ		<= result_integ + mult_res0_extend + mult_res8_extend_rev;
		mult_res0			<= mult_result_avg;
		mult_res1			<= mult_res0;
		mult_res2			<= mult_res1;
		mult_res3			<= mult_res2;
		mult_res4			<= mult_res3;
		mult_res5			<= mult_res4;
		mult_res6			<= mult_res5;
		mult_res7			<= mult_res6;
		mult_res8			<= mult_res7;
	end
end

always @ (posedge adc_clock)
begin
	if (~resetn)
	begin
		I_smp <= 0;
		Q_smp <= 0;
		I_pre_smp <= 0;
		Q_pre_smp <= 0;
	end
	else
	begin
		I_smp <= in_phase;
		Q_smp <= quad_phase;
		I_pre_smp <= I_smp;
		Q_pre_smp <= Q_smp;
	end
end

signed_mult8x8 mult_0(
	.DataA(I_smp),
	.DataB(Q_pre_smp),
	.Mult(mult0)
);

signed_mult8x8 mult_1(
	.DataA(Q_smp),
	.DataB(I_pre_smp),
	.Mult(mult1)
);


endmodule
module fx_demux(in_phase, quad_phase, adc_clock, resetn, bit_decode, signal_strength);


input			adc_clock, resetn;
input	[7:0]	in_phase, quad_phase;
output			bit_decode;
output	[7:0]	signal_strength;


reg		[7:0]	I_smp, Q_smp, I_pre_smp, Q_pre_smp;




wire signed	[15:0]	mult0, mult1;
wire signed	[16:0]	mult_result = mult1 - mult0;
reg	 signed	[16:0]	mult_pre_result;
`define	MSB_RES	16


wire signed	[`MSB_RES+1:0]	mult_result_avg = mult_result + mult_pre_result;
reg		[`MSB_RES+1:0]	mult_res0, mult_res1, mult_res2, mult_res3, mult_res4, mult_res5, mult_res6, mult_res7, mult_res8;
wire	[`MSB_RES+4:0]	mult_res0_extend = {{3{mult_res0[`MSB_RES+1]}}, mult_res0};
wire	[`MSB_RES+4:0]	mult_res8_extend = {{3{mult_res8[`MSB_RES+1]}}, mult_res8};
wire	[`MSB_RES+4:0]	mult_res8_extend_rev = (mult_res8_extend[`MSB_RES+4])? ~(mult_res8_extend - 1) : (~mult_res8_extend + 1);
reg		[`MSB_RES+4:0]	result_integ;

wire	[7:0]	I_smp_abs = (I_smp[7])? ~(I_smp) : I_smp;
wire	[7:0]	Q_smp_abs = (Q_smp[7])? ~(Q_smp) : Q_smp;
wire	[7:0]	signal_strength = I_smp_abs[6:0] + Q_smp_abs[6:0];
wire	bit_decode = (result_integ[`MSB_RES+4])? 0 : 1;


always @ (posedge adc_clock)
begin
	if (~resetn)
	begin
		mult_pre_result		<= 0;
		result_integ		<= 0;
		mult_res0			<= 0;
		mult_res1			<= 0;
		mult_res2			<= 0;
		mult_res3			<= 0;
		mult_res4			<= 0;
		mult_res5			<= 0;
		mult_res6			<= 0;
		mult_res7			<= 0;
		mult_res8			<= 0;
	end
	else
	begin
		mult_pre_result		<= mult_result;
		result_integ		<= result_integ + mult_res0_extend + mult_res8_extend_rev;
		mult_res0			<= mult_result_avg;
		mult_res1			<= mult_res0;
		mult_res2			<= mult_res1;
		mult_res3			<= mult_res2;
		mult_res4			<= mult_res3;
		mult_res5			<= mult_res4;
		mult_res6			<= mult_res5;
		mult_res7			<= mult_res6;
		mult_res8			<= mult_res7;
	end
end

always @ (posedge adc_clock)
begin
	if (~resetn)
	begin
		I_smp <= 0;
		Q_smp <= 0;
		I_pre_smp <= 0;
		Q_pre_smp <= 0;
	end
	else
	begin
		I_smp <= in_phase;
		Q_smp <= quad_phase;
		I_pre_smp <= I_smp;
		Q_pre_smp <= Q_smp;
	end
end

signed_mult8x8 mult_0(
	.DataA(I_smp),
	.DataB(Q_pre_smp),
	.Mult(mult0)
);

signed_mult8x8 mult_1(
	.DataA(Q_smp),
	.DataB(I_pre_smp),
	.Mult(mult1)
);


endmodule