data/full_repos/permissive/122492732/TestBench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/122492732/TestBench.v:25: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ! clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/122492732/TestBench.v:13: Cannot find file containing module: \'Master\'\n Master uut (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122492732,data/full_repos/permissive/122492732/Master\n             data/full_repos/permissive/122492732,data/full_repos/permissive/122492732/Master.v\n             data/full_repos/permissive/122492732,data/full_repos/permissive/122492732/Master.sv\n             Master\n             Master.v\n             Master.sv\n             obj_dir/Master\n             obj_dir/Master.v\n             obj_dir/Master.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestI2C;


	reg clk;


	wire scl;


	wire sda;


	Master uut (
		.sda(sda), 
		.scl(scl), 
		.clk(clk)
	);

	initial begin

		clk = 0;


	end
always #1 clk = ! clk;
      
endmodule
module TestI2C;



	reg clk;


	wire scl;


	wire sda;


	Master uut (
		.sda(sda), 
		.scl(scl), 
		.clk(clk)
	);

	initial begin

		clk = 0;


	end
always #1 clk = ! clk;
      
endmodule