data/full_repos/permissive/174546493/dispatch1.v
data/verilator_xmls/ecd59d0d-7751-4491-b3e7-0243f3c42dec.xml
module dispatch1(opcode,funct,next_state_DT1);

input[5:0] funct;
input[5:0] opcode;
output reg[4:0] next_state_DT1;

always@(*)
begin
if(opcode == 6'b000000)
begin
	case(funct)
	6'b100000 : next_state_DT1 = 5'd12;
	6'b011000 : next_state_DT1 = 5'd16;
	6'b010011 : next_state_DT1 = 5'd5;
	6'b000100 : next_state_DT1 = 5'd14;
	6'b001000 : next_state_DT1 = 5'd10;
	6'b001001 : next_state_DT1 = 5'd11;
	6'b000110 : next_state_DT1 = 5'd16;
	6'b000000 : next_state_DT1 = 5'd13;
	6'b010000 : next_state_DT1 = 5'd2;
	6'b010010 : next_state_DT1 = 5'd3;
	6'b010001 : next_state_DT1 = 5'd4;
	6'b011010 : next_state_DT1 = 5'd15;
	6'b000101 : next_state_DT1 = 5'd16;
	
	endcase
end

else
begin
	case(opcode)
	6'b001000 : next_state_DT1 = 5'd17;
	6'b100011 : next_state_DT1 = 5'd17;
	6'b101011 : next_state_DT1 = 5'd17;
	6'b000010 : next_state_DT1 = 5'd8;
	6'b000011 : next_state_DT1 = 5'd9;
	6'b001101 : next_state_DT1 = 5'd18;
	6'b001111 : next_state_DT1 = 5'd6;
	6'b000100 : next_state_DT1 = 5'd7;
	default : next_state_DT1 = 5'd31;
	endcase
end

end
endmodule
module dispatch1(opcode,funct,next_state_DT1);


input[5:0] funct;
input[5:0] opcode;
output reg[4:0] next_state_DT1;

always@(*)
begin
if(opcode == 6'b000000)
begin
	case(funct)
	6'b100000 : next_state_DT1 = 5'd12;
	6'b011000 : next_state_DT1 = 5'd16;
	6'b010011 : next_state_DT1 = 5'd5;
	6'b000100 : next_state_DT1 = 5'd14;
	6'b001000 : next_state_DT1 = 5'd10;
	6'b001001 : next_state_DT1 = 5'd11;
	6'b000110 : next_state_DT1 = 5'd16;
	6'b000000 : next_state_DT1 = 5'd13;
	6'b010000 : next_state_DT1 = 5'd2;
	6'b010010 : next_state_DT1 = 5'd3;
	6'b010001 : next_state_DT1 = 5'd4;
	6'b011010 : next_state_DT1 = 5'd15;
	6'b000101 : next_state_DT1 = 5'd16;
	
	endcase
end

else
begin
	case(opcode)
	6'b001000 : next_state_DT1 = 5'd17;
	6'b100011 : next_state_DT1 = 5'd17;
	6'b101011 : next_state_DT1 = 5'd17;
	6'b000010 : next_state_DT1 = 5'd8;
	6'b000011 : next_state_DT1 = 5'd9;
	6'b001101 : next_state_DT1 = 5'd18;
	6'b001111 : next_state_DT1 = 5'd6;
	6'b000100 : next_state_DT1 = 5'd7;
	default : next_state_DT1 = 5'd31;
	endcase
end

end
endmodule