data/full_repos/permissive/216210370/soc/rtc.v
1: b"%Error: data/full_repos/permissive/216210370/soc/rtc.v:892: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.v\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:510: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:469: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:409: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:197: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module rtc_pdu_top(
  aou_pdu_cnt,
  aou_pdu_cr_reg,
  aou_pdu_div_reg,
  aou_pdu_intr_mask,
  aou_pdu_mr_reg,
  int_flag,
  paddr,
  pclk,
  pdu_aou_clr_reg,
  pdu_aou_int_clr,
  pdu_aou_wen_clr_sync,
  pdu_aou_wen_cr,
  pdu_aou_wen_div,
  pdu_aou_wen_mr,
  penable,
  prdata,
  presetn,
  psel,
  pwdata,
  pwrite,
  rtc_clk,
  test_mode
);
input   [31:0]  aou_pdu_cnt;         
input   [3 :0]  aou_pdu_cr_reg;      
input   [19:0]  aou_pdu_div_reg;     
input           aou_pdu_intr_mask;   
input   [31:0]  aou_pdu_mr_reg;      
input           int_flag;            
input   [31:0]  paddr;               
input           pclk;                
input           penable;             
input           presetn;             
input           psel;                
input   [31:0]  pwdata;              
input           pwrite;              
input           rtc_clk;             
input           test_mode;           
output  [31:0]  pdu_aou_clr_reg;     
output          pdu_aou_int_clr;     
output          pdu_aou_wen_clr_sync; 
output          pdu_aou_wen_cr;      
output          pdu_aou_wen_div;     
output          pdu_aou_wen_mr;      
output  [31:0]  prdata;              
wire    [31:0]  aou_pdu_cnt;         
wire    [3 :0]  aou_pdu_cr_reg;      
wire    [19:0]  aou_pdu_div_reg;     
wire            aou_pdu_intr_mask;   
wire    [31:0]  aou_pdu_mr_reg;      
wire    [31:0]  cnt_sync;            
wire            int_flag;            
wire    [31:0]  paddr;               
wire            pclk;                
wire    [31:0]  pdu_aou_clr_reg;     
wire            pdu_aou_int_clr;     
wire            pdu_aou_wen_clr_sync; 
wire            pdu_aou_wen_cr;      
wire            pdu_aou_wen_div;     
wire            pdu_aou_wen_mr;      
wire            penable;             
wire    [31:0]  prdata;              
wire            presetn;             
wire            psel;                
wire    [31:0]  pwdata;              
wire            pwrite;              
wire            rtc_clk;             
wire            test_mode;           
wire            wen_clr;             
rtc_pdu_apbif  x_rtc_pdu_apbif (
  .aou_pdu_cr_reg    (aou_pdu_cr_reg   ),
  .aou_pdu_div_reg   (aou_pdu_div_reg  ),
  .aou_pdu_intr_mask (aou_pdu_intr_mask),
  .aou_pdu_mr_reg    (aou_pdu_mr_reg   ),
  .cnt_sync          (cnt_sync         ),
  .int_flag          (int_flag         ),
  .paddr             (paddr            ),
  .pclk              (pclk             ),
  .pdu_aou_clr_reg   (pdu_aou_clr_reg  ),
  .pdu_aou_int_clr   (pdu_aou_int_clr  ),
  .pdu_aou_wen_cr    (pdu_aou_wen_cr   ),
  .pdu_aou_wen_div   (pdu_aou_wen_div  ),
  .pdu_aou_wen_mr    (pdu_aou_wen_mr   ),
  .penable           (penable          ),
  .prdata            (prdata           ),
  .presetn           (presetn          ),
  .psel              (psel             ),
  .pwdata            (pwdata           ),
  .pwrite            (pwrite           ),
  .test_mode         (test_mode        ),
  .wen_clr           (wen_clr          )
);
rtc_cdr_sync  x_rtc_cdr_sync (
  .aou_pdu_cnt (aou_pdu_cnt),
  .cnt_sync    (cnt_sync   ),
  .pclk        (pclk       ),
  .presetn     (presetn    ),
  .test_mode   (test_mode  )
);
rtc_clr_sync  x_rtc_clr_sync (
  .pclk                 (pclk                ),
  .pdu_aou_wen_clr_sync (pdu_aou_wen_clr_sync),
  .presetn              (presetn             ),
  .rtc_clk              (rtc_clk             ),
  .test_mode            (test_mode           ),
  .wen_clr              (wen_clr             )
);
endmodule
module rtc_pdu_top(
  aou_pdu_cnt,
  aou_pdu_cr_reg,
  aou_pdu_div_reg,
  aou_pdu_intr_mask,
  aou_pdu_mr_reg,
  int_flag,
  paddr,
  pclk,
  pdu_aou_clr_reg,
  pdu_aou_int_clr,
  pdu_aou_wen_clr_sync,
  pdu_aou_wen_cr,
  pdu_aou_wen_div,
  pdu_aou_wen_mr,
  penable,
  prdata,
  presetn,
  psel,
  pwdata,
  pwrite,
  rtc_clk,
  test_mode
);

input   [31:0]  aou_pdu_cnt;         
input   [3 :0]  aou_pdu_cr_reg;      
input   [19:0]  aou_pdu_div_reg;     
input           aou_pdu_intr_mask;   
input   [31:0]  aou_pdu_mr_reg;      
input           int_flag;            
input   [31:0]  paddr;               
input           pclk;                
input           penable;             
input           presetn;             
input           psel;                
input   [31:0]  pwdata;              
input           pwrite;              
input           rtc_clk;             
input           test_mode;           
output  [31:0]  pdu_aou_clr_reg;     
output          pdu_aou_int_clr;     
output          pdu_aou_wen_clr_sync; 
output          pdu_aou_wen_cr;      
output          pdu_aou_wen_div;     
output          pdu_aou_wen_mr;      
output  [31:0]  prdata;              
wire    [31:0]  aou_pdu_cnt;         
wire    [3 :0]  aou_pdu_cr_reg;      
wire    [19:0]  aou_pdu_div_reg;     
wire            aou_pdu_intr_mask;   
wire    [31:0]  aou_pdu_mr_reg;      
wire    [31:0]  cnt_sync;            
wire            int_flag;            
wire    [31:0]  paddr;               
wire            pclk;                
wire    [31:0]  pdu_aou_clr_reg;     
wire            pdu_aou_int_clr;     
wire            pdu_aou_wen_clr_sync; 
wire            pdu_aou_wen_cr;      
wire            pdu_aou_wen_div;     
wire            pdu_aou_wen_mr;      
wire            penable;             
wire    [31:0]  prdata;              
wire            presetn;             
wire            psel;                
wire    [31:0]  pwdata;              
wire            pwrite;              
wire            rtc_clk;             
wire            test_mode;           
wire            wen_clr;             
rtc_pdu_apbif  x_rtc_pdu_apbif (
  .aou_pdu_cr_reg    (aou_pdu_cr_reg   ),
  .aou_pdu_div_reg   (aou_pdu_div_reg  ),
  .aou_pdu_intr_mask (aou_pdu_intr_mask),
  .aou_pdu_mr_reg    (aou_pdu_mr_reg   ),
  .cnt_sync          (cnt_sync         ),
  .int_flag          (int_flag         ),
  .paddr             (paddr            ),
  .pclk              (pclk             ),
  .pdu_aou_clr_reg   (pdu_aou_clr_reg  ),
  .pdu_aou_int_clr   (pdu_aou_int_clr  ),
  .pdu_aou_wen_cr    (pdu_aou_wen_cr   ),
  .pdu_aou_wen_div   (pdu_aou_wen_div  ),
  .pdu_aou_wen_mr    (pdu_aou_wen_mr   ),
  .penable           (penable          ),
  .prdata            (prdata           ),
  .presetn           (presetn          ),
  .psel              (psel             ),
  .pwdata            (pwdata           ),
  .pwrite            (pwrite           ),
  .test_mode         (test_mode        ),
  .wen_clr           (wen_clr          )
);
rtc_cdr_sync  x_rtc_cdr_sync (
  .aou_pdu_cnt (aou_pdu_cnt),
  .cnt_sync    (cnt_sync   ),
  .pclk        (pclk       ),
  .presetn     (presetn    ),
  .test_mode   (test_mode  )
);
rtc_clr_sync  x_rtc_clr_sync (
  .pclk                 (pclk                ),
  .pdu_aou_wen_clr_sync (pdu_aou_wen_clr_sync),
  .presetn              (presetn             ),
  .rtc_clk              (rtc_clk             ),
  .test_mode            (test_mode           ),
  .wen_clr              (wen_clr             )
);
endmodule