data/full_repos/permissive/153960117/hdl/group_add_tb.v
 line:55: before: "signed"
1: b'%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:18: Cannot find include file: group_add.v\n`include "group_add.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/153960117/hdl,data/full_repos/permissive/153960117/group_add.v\n             data/full_repos/permissive/153960117/hdl,data/full_repos/permissive/153960117/group_add.v.v\n             data/full_repos/permissive/153960117/hdl,data/full_repos/permissive/153960117/group_add.v.sv\n             group_add.v\n             group_add.v.v\n             group_add.v.sv\n             obj_dir/group_add.v\n             obj_dir/group_add.v.v\n             obj_dir/group_add.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/153960117/hdl/group_add_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:31: Unsupported: event data types\n    event end_trigger;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/153960117/hdl/group_add_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    initial #1 display_header();\n            ^\n%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:128: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:144: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        );\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:159: syntax error, unexpected \'@\'\n        repeat(5) @(negedge clk);\n                  ^\n%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:164: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:167: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:170: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:173: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:176: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:179: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:182: syntax error, unexpected \'@\'\n        repeat(10) @(negedge clk);\n                   ^\n%Error: data/full_repos/permissive/153960117/hdl/group_add_tb.v:188: syntax error, unexpected ->\n        -> end_trigger;\n        ^~\n%Error: Exiting due to 13 error(s), 2 warning(s)\n'
module group_add_tb;




    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam GROUP_NB     = 4;
    localparam NUM_WIDTH    = 16;
    localparam NUM_POINT    = 8;



    function real num_f2r;
        input signed [NUM_WIDTH-1:0] value;

        begin
            num_f2r = value / ((1<<NUM_POINT) * 1.0);
        end
    endfunction


    function signed [NUM_WIDTH-1:0] num_r2f;
        input real value;

        begin
            num_r2f = value * (1<<(NUM_POINT));
        end
    endfunction


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'group_add'");
    end
`endif




    reg         [NUM_WIDTH*GROUP_NB-1:0]    up_data;
    wire signed [NUM_WIDTH-1:0]             dn_data;




    group_add #(
        .GROUP_NB   (GROUP_NB),
        .NUM_WIDTH  (NUM_WIDTH))
    uut (
        .clk        (clk),

        .up_data    (up_data),
        .dn_data    (dn_data)
    );




    task display_signals;
        $display(
            "%d",
            $time,

            "\t%x",
            up_data,

            "\t%f %f %f %f",
            num_f2r(up_data[3*NUM_WIDTH +: NUM_WIDTH]),
            num_f2r(up_data[2*NUM_WIDTH +: NUM_WIDTH]),
            num_f2r(up_data[1*NUM_WIDTH +: NUM_WIDTH]),
            num_f2r(up_data[0*NUM_WIDTH +: NUM_WIDTH]),

            "\t%f",
            num_f2r(dn_data),

        );

    endtask

    task display_header;
        $display(
            "\t\ttime",

            "\t\tu",

            "\t\t\tu3",
            "\tu2",
            "\tu1",
            "\tu0",

            "\td",
        );
    endtask




    initial begin


        up_data = 'b0;



        repeat(5) @(negedge clk);

`ifdef TB_VERBOSE
    $display("send data");
`endif
        @(negedge clk);

        up_data <= {num_r2f( 4), num_r2f( 3), num_r2f( 2), num_r2f( 1)};
        @(negedge clk);

        up_data <= {num_r2f( 8), num_r2f( 7), num_r2f( 6), num_r2f( 5)};
        @(negedge clk);

        up_data <= {num_r2f(12), num_r2f(11), num_r2f(10), num_r2f( 9)};
        @(negedge clk);

        up_data <= {num_r2f(16), num_r2f(15), num_r2f(14), num_r2f(13)};
        @(negedge clk);

        up_data <= {num_r2f(20), num_r2f(19), num_r2f(18), num_r2f(17)};
        @(negedge clk);

        up_data <= 'b0;
        repeat(10) @(negedge clk);


`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule
module group_add_tb;





    reg clk = 0;
    always #1 clk = !clk;


    event end_trigger;
    always @(end_trigger) $finish;

`ifdef TB_VERBOSE

    initial #1 display_header();
    always @(end_trigger) display_header();


    always @(posedge clk) display_signals();
`endif









    localparam GROUP_NB     = 4;
    localparam NUM_WIDTH    = 16;
    localparam NUM_POINT    = 8;



    function real num_f2r;
        input signed [NUM_WIDTH-1:0] value;

        begin
            num_f2r = value / ((1<<NUM_POINT) * 1.0);
        end
    endfunction


    function signed [NUM_WIDTH-1:0] num_r2f;
        input real value;

        begin
            num_r2f = value * (1<<(NUM_POINT));
        end
    endfunction


`ifdef TB_VERBOSE
    initial begin
        $display("Testbench for 'group_add'");
    end
`endif




    reg         [NUM_WIDTH*GROUP_NB-1:0]    up_data;
    wire signed [NUM_WIDTH-1:0]             dn_data;




    group_add #(
        .GROUP_NB   (GROUP_NB),
        .NUM_WIDTH  (NUM_WIDTH))
    uut (
        .clk        (clk),

        .up_data    (up_data),
        .dn_data    (dn_data)
    );




    task display_signals;
        $display(
            "%d",
            $time,

            "\t%x",
            up_data,

            "\t%f %f %f %f",
            num_f2r(up_data[3*NUM_WIDTH +: NUM_WIDTH]),
            num_f2r(up_data[2*NUM_WIDTH +: NUM_WIDTH]),
            num_f2r(up_data[1*NUM_WIDTH +: NUM_WIDTH]),
            num_f2r(up_data[0*NUM_WIDTH +: NUM_WIDTH]),

            "\t%f",
            num_f2r(dn_data),

        );

    endtask

    task display_header;
        $display(
            "\t\ttime",

            "\t\tu",

            "\t\t\tu3",
            "\tu2",
            "\tu1",
            "\tu0",

            "\td",
        );
    endtask




    initial begin


        up_data = 'b0;



        repeat(5) @(negedge clk);

`ifdef TB_VERBOSE
    $display("send data");
`endif
        @(negedge clk);

        up_data <= {num_r2f( 4), num_r2f( 3), num_r2f( 2), num_r2f( 1)};
        @(negedge clk);

        up_data <= {num_r2f( 8), num_r2f( 7), num_r2f( 6), num_r2f( 5)};
        @(negedge clk);

        up_data <= {num_r2f(12), num_r2f(11), num_r2f(10), num_r2f( 9)};
        @(negedge clk);

        up_data <= {num_r2f(16), num_r2f(15), num_r2f(14), num_r2f(13)};
        @(negedge clk);

        up_data <= {num_r2f(20), num_r2f(19), num_r2f(18), num_r2f(17)};
        @(negedge clk);

        up_data <= 'b0;
        repeat(10) @(negedge clk);


`ifdef TB_VERBOSE
    $display("END");
`endif
        -> end_trigger;
    end

endmodule