data/full_repos/permissive/102515926/Modules/MAIN.v
1: b"%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:39: Cannot find file containing module: 'ADD'\n    ADD #(DATAWIDTH) ADD_1(a, b, a1);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.v\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.sv\n             ADD\n             ADD.v\n             ADD.sv\n             obj_dir/ADD\n             obj_dir/ADD.v\n             obj_dir/ADD.sv\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:40: Cannot find file containing module: 'COMP'\n    COMP #(DATAWIDTH) COMP_1(c, d, a2_gt, a2_lt, a2_eq);\n    ^~~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:41: Cannot find file containing module: 'DEC'\n    DEC #(DATAWIDTH) DEC_1(e, a3);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:42: Cannot find file containing module: 'DIV'\n    DIV #(DATAWIDTH) DIV_1(f, g, a4);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:43: Cannot find file containing module: 'INC'\n    INC #(DATAWIDTH) INC_1(h, a5);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:44: Cannot find file containing module: 'MOD'\n    MOD #(DATAWIDTH) MOD_1(i, j, a6);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:45: Cannot find file containing module: 'MUL'\n    MUL #(DATAWIDTH) MUL_1(k, l, a7);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:46: Cannot find file containing module: 'MUX2x1'\n    MUX2x1 #(DATAWIDTH) MUX2x1_1(m, n, a8_sel, a8);\n    ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:47: Cannot find file containing module: 'REG'\n    REG #(DATAWIDTH) REG_1(o, clk, rst, a9);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:48: Cannot find file containing module: 'SHL'\n    SHL #(DATAWIDTH) SHL_1(p, p_amt, a10);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:49: Cannot find file containing module: 'SHR'\n    SHR #(DATAWIDTH) SHR_1(q, q_amt, a11);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/MAIN.v:50: Cannot find file containing module: 'SUB'\n    SUB #(DATAWIDTH) SUB_1(r, s, a12);\n    ^~~\n%Error: Exiting due to 12 error(s)\n"
module MAIN(a, b, c, d, e, f, g, h, i, j, k, l, m, n, a8_sel, o, clk, rst, p, p_amt, q, q_amt, r, s, a1, a2_gt, a2_lt, a2_eq, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12);
    parameter DATAWIDTH = 2;
    
    input [DATAWIDTH - 1:0] a, b; output [DATAWIDTH - 1:0] a1;
    input [DATAWIDTH - 1:0] c, d; output a2_gt, a2_lt, a2_eq;
    input [DATAWIDTH - 1:0] e; output [DATAWIDTH - 1:0] a3;
    input [DATAWIDTH - 1:0] f, g; output [DATAWIDTH - 1:0] a4;
    input [DATAWIDTH - 1:0] h; output [DATAWIDTH - 1:0] a5;
    input [DATAWIDTH - 1:0] i, j; output [DATAWIDTH - 1:0] a6;
    input [DATAWIDTH - 1:0] k, l; output [DATAWIDTH - 1:0] a7;
    input [DATAWIDTH - 1:0] m, n; input a8_sel; output [DATAWIDTH - 1:0] a8;
    input [DATAWIDTH - 1:0] o; input clk, rst; output [DATAWIDTH - 1:0] a9;
    input [DATAWIDTH - 1:0] p; input [$clog2(DATAWIDTH) - 1:0] p_amt; output [DATAWIDTH - 1:0] a10;
    input [DATAWIDTH - 1:0] q; input [$clog2(DATAWIDTH) - 1:0] q_amt; output [DATAWIDTH - 1:0] a11;
    input [DATAWIDTH - 1:0] r, s; output [DATAWIDTH - 1:0] a12;
    
    ADD #(DATAWIDTH) ADD_1(a, b, a1);
    COMP #(DATAWIDTH) COMP_1(c, d, a2_gt, a2_lt, a2_eq);
    DEC #(DATAWIDTH) DEC_1(e, a3);
    DIV #(DATAWIDTH) DIV_1(f, g, a4);
    INC #(DATAWIDTH) INC_1(h, a5);
    MOD #(DATAWIDTH) MOD_1(i, j, a6);
    MUL #(DATAWIDTH) MUL_1(k, l, a7);
    MUX2x1 #(DATAWIDTH) MUX2x1_1(m, n, a8_sel, a8);
    REG #(DATAWIDTH) REG_1(o, clk, rst, a9);
    SHL #(DATAWIDTH) SHL_1(p, p_amt, a10);
    SHR #(DATAWIDTH) SHR_1(q, q_amt, a11);
    SUB #(DATAWIDTH) SUB_1(r, s, a12);
endmodule
module MAIN(a, b, c, d, e, f, g, h, i, j, k, l, m, n, a8_sel, o, clk, rst, p, p_amt, q, q_amt, r, s, a1, a2_gt, a2_lt, a2_eq, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12);

    parameter DATAWIDTH = 2;
    
    input [DATAWIDTH - 1:0] a, b; output [DATAWIDTH - 1:0] a1;
    input [DATAWIDTH - 1:0] c, d; output a2_gt, a2_lt, a2_eq;
    input [DATAWIDTH - 1:0] e; output [DATAWIDTH - 1:0] a3;
    input [DATAWIDTH - 1:0] f, g; output [DATAWIDTH - 1:0] a4;
    input [DATAWIDTH - 1:0] h; output [DATAWIDTH - 1:0] a5;
    input [DATAWIDTH - 1:0] i, j; output [DATAWIDTH - 1:0] a6;
    input [DATAWIDTH - 1:0] k, l; output [DATAWIDTH - 1:0] a7;
    input [DATAWIDTH - 1:0] m, n; input a8_sel; output [DATAWIDTH - 1:0] a8;
    input [DATAWIDTH - 1:0] o; input clk, rst; output [DATAWIDTH - 1:0] a9;
    input [DATAWIDTH - 1:0] p; input [$clog2(DATAWIDTH) - 1:0] p_amt; output [DATAWIDTH - 1:0] a10;
    input [DATAWIDTH - 1:0] q; input [$clog2(DATAWIDTH) - 1:0] q_amt; output [DATAWIDTH - 1:0] a11;
    input [DATAWIDTH - 1:0] r, s; output [DATAWIDTH - 1:0] a12;
    
    ADD #(DATAWIDTH) ADD_1(a, b, a1);
    COMP #(DATAWIDTH) COMP_1(c, d, a2_gt, a2_lt, a2_eq);
    DEC #(DATAWIDTH) DEC_1(e, a3);
    DIV #(DATAWIDTH) DIV_1(f, g, a4);
    INC #(DATAWIDTH) INC_1(h, a5);
    MOD #(DATAWIDTH) MOD_1(i, j, a6);
    MUL #(DATAWIDTH) MUL_1(k, l, a7);
    MUX2x1 #(DATAWIDTH) MUX2x1_1(m, n, a8_sel, a8);
    REG #(DATAWIDTH) REG_1(o, clk, rst, a9);
    SHL #(DATAWIDTH) SHL_1(p, p_amt, a10);
    SHR #(DATAWIDTH) SHR_1(q, q_amt, a11);
    SUB #(DATAWIDTH) SUB_1(r, s, a12);
endmodule