data/full_repos/permissive/160794640/example/master.sv
 line:20: before: "unsigned"
1: b"%Error: data/full_repos/permissive/160794640/example/master.sv:67: Cannot find file containing module: 'AXI_BUS'\n    AXI_BUS #(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160794640/example,data/full_repos/permissive/160794640/AXI_BUS\n             data/full_repos/permissive/160794640/example,data/full_repos/permissive/160794640/AXI_BUS.v\n             data/full_repos/permissive/160794640/example,data/full_repos/permissive/160794640/AXI_BUS.sv\n             AXI_BUS\n             AXI_BUS.v\n             AXI_BUS.sv\n             obj_dir/AXI_BUS\n             obj_dir/AXI_BUS.v\n             obj_dir/AXI_BUS.sv\n%Error: data/full_repos/permissive/160794640/example/master.sv:150: Cannot find file containing module: 'axi_adapter'\n    axi_adapter #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/160794640/example/master.sv:173: Cannot find file containing module: 'axi2mem'\n    axi2mem #(\n    ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module master #(
    parameter int unsigned AXI_ID_WIDTH      = 10,
    parameter int unsigned AXI_USER_WIDTH    = 1,
    parameter int unsigned AXI_ADDRESS_WIDTH = 64,
    parameter int unsigned AXI_DATA_WIDTH    = 64
)(
    input  logic          clk_i,
    input  logic          rst_ni,
    input  logic          dmactive_i,

    input  logic [63:0]   sbaddress_i,
    input  logic          sbaddress_write_valid_i,

    input  logic          sbreadonaddr_i,
    output logic [63:0]   sbaddress_o,
    input  logic          sbautoincrement_i,
    input  logic [2:0]    sbaccess_i,

    input  logic          sbreadondata_i,
    input  logic [63:0]   sbdata_i,
    input  logic          sbdata_read_valid_i,
    input  logic          sbdata_write_valid_i,

    output logic [63:0]   sbdata_o,
    output logic          sbdata_valid_o,

    output logic          sbbusy_o,
    output logic          sberror_valid_o,
    output logic [2:0]    sberror_o,
    output logic                         rom_req, rom_we,
    output logic [AXI_ADDRESS_WIDTH-1:0] rom_addr,
    output logic [AXI_DATA_WIDTH-1:0]    rom_wdata,
    output logic [AXI_DATA_WIDTH/8-1:0]  rom_be,
    input logic [AXI_DATA_WIDTH-1:0]     rom_rdata
);

    typedef enum logic { SINGLE_REQ, CACHE_LINE_REQ } req_t;
   
    enum logic [2:0] { Idle, Read, Write, WaitRead, WaitWrite } state_d, state_q;

    logic [63:0]      address;
    logic             req;
    logic             gnt;
    logic             we;
    logic [7:0]       be;

    assign sbbusy_o = (state_q != Idle) ? 1'b1 : 1'b0;

    AXI_BUS #(
        .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH   ),
        .AXI_DATA_WIDTH ( AXI_DATA_WIDTH      ),
        .AXI_ID_WIDTH   ( AXI_ID_WIDTH        ),
        .AXI_USER_WIDTH ( AXI_USER_WIDTH      )
    ) axi_master();
  
    always_comb begin
        req     = 1'b0;
        address = sbaddress_i;
        we      = 1'b0;
        be      = '0;

        sberror_o       = '0;
        sberror_valid_o = 1'b0;
        sbaddress_o     = sbaddress_i;

        state_d = state_q;

        case (state_q)
            Idle: begin

                if (sbaddress_write_valid_i && sbreadonaddr_i)  state_d = Read;

                if (sbdata_write_valid_i) state_d = Write;

                if (sbdata_read_valid_i && sbreadondata_i) state_d = Read;
            end

            Read: begin
                req = 1'b1;
                if (gnt) state_d = WaitRead;
            end

            Write: begin
                req = 1'b1;
                we  = 1'b1;

                case (sbaccess_i)
                    3'b000: be[ sbaddress_i[2:0]] = '1;
                    3'b001: be[{sbaddress_i[2:1], 1'b0} +: 2] = '1;
                    3'b010: be[{sbaddress_i[2:2], 2'b0} +: 4] = '1;
                    3'b011: be = '1;
                    default:;
                endcase
                if (gnt) state_d = WaitWrite;
            end

            WaitRead: begin
                if (sbdata_valid_o) begin
                    state_d = Idle;

                    if (sbautoincrement_i) sbaddress_o = sbaddress_i + (1 << sbaccess_i);
                end
            end

            WaitWrite: begin
                if (sbdata_valid_o) begin
                    state_d = Idle;

                    if (sbautoincrement_i) sbaddress_o = sbaddress_i + (1 << sbaccess_i);
                end
            end
        endcase

        if (sbaccess_i > 3 && state_q != Idle) begin
            req             = 1'b0;
            state_d         = Idle;
            sberror_valid_o = 1'b1;
            sberror_o       = 'd3;
        end

    end

    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (~rst_ni) begin
            state_q <= Idle;
        end else begin
            state_q <= state_d;
        end
    end


    axi_adapter #(
        .DATA_WIDTH            ( 128                       )
    ) i_axi_master (
        .clk_i                 ( clk_i                     ),
        .rst_ni                ( rst_ni                    ),
        .req_i                 ( req                       ),
        .type_i                ( SINGLE_REQ                ),
        .gnt_o                 ( gnt                       ),
        .gnt_id_o              (                           ),
        .addr_i                ( address                   ),
        .we_i                  ( we                        ),
        .wdata_i               ( sbdata_i                  ),
        .be_i                  ( be                        ),
        .size_i                ( sbaccess_i[1:0]           ),
        .id_i                  ( '0                        ),
        .valid_o               ( sbdata_valid_o            ),
        .rdata_o               ( sbdata_o                  ),
        .id_o                  (                           ),
        .critical_word_o       (                           ),
        .critical_word_valid_o (                           ),
        .axi                   ( axi_master                )
    );

    axi2mem #(
        .AXI_ID_WIDTH   ( AXI_ID_WIDTH        ),
        .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH   ),
        .AXI_DATA_WIDTH ( AXI_DATA_WIDTH      ),
        .AXI_USER_WIDTH ( AXI_USER_WIDTH      )
    ) i_axi2rom (
        .clk_i  ( clk_i      ),
        .rst_ni ( rst_ni     ),
        .slave  ( axi_master ),
        .req_o  ( rom_req    ),
        .we_o   ( rom_we     ),
        .addr_o ( rom_addr   ),
        .be_o   ( rom_be     ),
        .data_o ( rom_wdata  ),
        .data_i ( rom_rdata  )
    );

endmodule
module master #(
    parameter int unsigned AXI_ID_WIDTH      = 10,
    parameter int unsigned AXI_USER_WIDTH    = 1,
    parameter int unsigned AXI_ADDRESS_WIDTH = 64,
    parameter int unsigned AXI_DATA_WIDTH    = 64
)(
    input  logic          clk_i,
    input  logic          rst_ni,
    input  logic          dmactive_i,

    input  logic [63:0]   sbaddress_i,
    input  logic          sbaddress_write_valid_i,

    input  logic          sbreadonaddr_i,
    output logic [63:0]   sbaddress_o,
    input  logic          sbautoincrement_i,
    input  logic [2:0]    sbaccess_i,

    input  logic          sbreadondata_i,
    input  logic [63:0]   sbdata_i,
    input  logic          sbdata_read_valid_i,
    input  logic          sbdata_write_valid_i,

    output logic [63:0]   sbdata_o,
    output logic          sbdata_valid_o,

    output logic          sbbusy_o,
    output logic          sberror_valid_o,
    output logic [2:0]    sberror_o,
    output logic                         rom_req, rom_we,
    output logic [AXI_ADDRESS_WIDTH-1:0] rom_addr,
    output logic [AXI_DATA_WIDTH-1:0]    rom_wdata,
    output logic [AXI_DATA_WIDTH/8-1:0]  rom_be,
    input logic [AXI_DATA_WIDTH-1:0]     rom_rdata
);


    typedef enum logic { SINGLE_REQ, CACHE_LINE_REQ } req_t;
   
    enum logic [2:0] { Idle, Read, Write, WaitRead, WaitWrite } state_d, state_q;

    logic [63:0]      address;
    logic             req;
    logic             gnt;
    logic             we;
    logic [7:0]       be;

    assign sbbusy_o = (state_q != Idle) ? 1'b1 : 1'b0;

    AXI_BUS #(
        .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH   ),
        .AXI_DATA_WIDTH ( AXI_DATA_WIDTH      ),
        .AXI_ID_WIDTH   ( AXI_ID_WIDTH        ),
        .AXI_USER_WIDTH ( AXI_USER_WIDTH      )
    ) axi_master();
  
    always_comb begin
        req     = 1'b0;
        address = sbaddress_i;
        we      = 1'b0;
        be      = '0;

        sberror_o       = '0;
        sberror_valid_o = 1'b0;
        sbaddress_o     = sbaddress_i;

        state_d = state_q;

        case (state_q)
            Idle: begin

                if (sbaddress_write_valid_i && sbreadonaddr_i)  state_d = Read;

                if (sbdata_write_valid_i) state_d = Write;

                if (sbdata_read_valid_i && sbreadondata_i) state_d = Read;
            end

            Read: begin
                req = 1'b1;
                if (gnt) state_d = WaitRead;
            end

            Write: begin
                req = 1'b1;
                we  = 1'b1;

                case (sbaccess_i)
                    3'b000: be[ sbaddress_i[2:0]] = '1;
                    3'b001: be[{sbaddress_i[2:1], 1'b0} +: 2] = '1;
                    3'b010: be[{sbaddress_i[2:2], 2'b0} +: 4] = '1;
                    3'b011: be = '1;
                    default:;
                endcase
                if (gnt) state_d = WaitWrite;
            end

            WaitRead: begin
                if (sbdata_valid_o) begin
                    state_d = Idle;

                    if (sbautoincrement_i) sbaddress_o = sbaddress_i + (1 << sbaccess_i);
                end
            end

            WaitWrite: begin
                if (sbdata_valid_o) begin
                    state_d = Idle;

                    if (sbautoincrement_i) sbaddress_o = sbaddress_i + (1 << sbaccess_i);
                end
            end
        endcase

        if (sbaccess_i > 3 && state_q != Idle) begin
            req             = 1'b0;
            state_d         = Idle;
            sberror_valid_o = 1'b1;
            sberror_o       = 'd3;
        end

    end

    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (~rst_ni) begin
            state_q <= Idle;
        end else begin
            state_q <= state_d;
        end
    end


    axi_adapter #(
        .DATA_WIDTH            ( 128                       )
    ) i_axi_master (
        .clk_i                 ( clk_i                     ),
        .rst_ni                ( rst_ni                    ),
        .req_i                 ( req                       ),
        .type_i                ( SINGLE_REQ                ),
        .gnt_o                 ( gnt                       ),
        .gnt_id_o              (                           ),
        .addr_i                ( address                   ),
        .we_i                  ( we                        ),
        .wdata_i               ( sbdata_i                  ),
        .be_i                  ( be                        ),
        .size_i                ( sbaccess_i[1:0]           ),
        .id_i                  ( '0                        ),
        .valid_o               ( sbdata_valid_o            ),
        .rdata_o               ( sbdata_o                  ),
        .id_o                  (                           ),
        .critical_word_o       (                           ),
        .critical_word_valid_o (                           ),
        .axi                   ( axi_master                )
    );

    axi2mem #(
        .AXI_ID_WIDTH   ( AXI_ID_WIDTH        ),
        .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH   ),
        .AXI_DATA_WIDTH ( AXI_DATA_WIDTH      ),
        .AXI_USER_WIDTH ( AXI_USER_WIDTH      )
    ) i_axi2rom (
        .clk_i  ( clk_i      ),
        .rst_ni ( rst_ni     ),
        .slave  ( axi_master ),
        .req_o  ( rom_req    ),
        .we_o   ( rom_we     ),
        .addr_o ( rom_addr   ),
        .be_o   ( rom_be     ),
        .data_o ( rom_wdata  ),
        .data_i ( rom_rdata  )
    );

endmodule