data/full_repos/permissive/13201424/vlog/eth_mcb_if.v
data/verilator_xmls/e0767f0a-88c5-4322-8bee-27f3e921d6e3.xml
module eth_mcb_if (
	input clk,
	input rst,
	
	output reg rd_en_out,
	input [35:0] rd_d_in,
	input rd_empty_in,
	
	output reg mcb_cmd_en_out,
	output [2:0] mcb_cmd_instr_out,
	output [5:0] mcb_cmd_bl_out,
	output reg [29:0] mcb_cmd_byte_addr_out,
	input mcb_cmd_empty_in,
	input mcb_cmd_full_in,
	
	output reg mcb_wr_en_out,
	output [7:0] mcb_wr_mask_out,
	output reg [63:0] mcb_wr_data_out,
	input mcb_wr_full_in,
	input mcb_wr_empty_in,
	input mcb_wr_error_in,
	input mcb_wr_underrun_in,
	input [6:0] mcb_wr_count_in,
	
	output mcb_rd_en_out,
	input [63:0] mcb_rd_data_in,
	input mcb_rd_full_in,
	input mcb_rd_empty_in,
	input mcb_rd_error_in,
	input mcb_rd_overflow_in,
	input [6:0] mcb_rd_count_in
);

	assign mcb_wr_mask_out = 8'h0;
	assign mcb_rd_en_out = 1'b0;
	assign mcb_cmd_instr_out = 3'b000;
	assign mcb_cmd_bl_out = 6'h0;
	
	reg rd_rdy;

	reg toggle;

	always @ (posedge clk) begin
		if (rst) begin
			mcb_cmd_byte_addr_out <= 0;
			mcb_wr_en_out <= 0;
			mcb_wr_data_out <= 0;
			
			rd_en_out <= 0;
			rd_rdy <= 0;

			toggle <= 0;
			
		end else begin
		
			rd_rdy <= rd_en_out;

		
			if (!mcb_wr_full_in && !mcb_cmd_full_in) begin
				rd_en_out <= !rd_empty_in;
				if (rd_rdy && rd_en_out) begin
					if (rd_d_in[33]) begin



						mcb_wr_en_out <= 0;
						toggle <= 0;
						
					end else begin




						if (!toggle) begin
							mcb_wr_data_out[63:32] <= rd_d_in[31:0];
							mcb_wr_data_out[31:0] <= 0;
							mcb_wr_en_out <= 0;
						end else begin
							mcb_wr_data_out[31:0] <= rd_d_in[31:0];
							mcb_wr_en_out <= 1;
						end
						toggle <= !toggle;
					end
					
				end else begin


					mcb_wr_en_out <= 0;
				end
				
			end else begin

				rd_en_out <= 0;
				mcb_wr_en_out <= 0;
			end
			
			if (rd_d_in[33])
				mcb_cmd_byte_addr_out <= rd_d_in[29:0];
			else if (mcb_cmd_en_out)
				mcb_cmd_byte_addr_out <= mcb_cmd_byte_addr_out + 29'd8;
			
			mcb_cmd_en_out <= mcb_wr_en_out;
		end
	end
endmodule
module eth_mcb_if (
	input clk,
	input rst,
	
	output reg rd_en_out,
	input [35:0] rd_d_in,
	input rd_empty_in,
	
	output reg mcb_cmd_en_out,
	output [2:0] mcb_cmd_instr_out,
	output [5:0] mcb_cmd_bl_out,
	output reg [29:0] mcb_cmd_byte_addr_out,
	input mcb_cmd_empty_in,
	input mcb_cmd_full_in,
	
	output reg mcb_wr_en_out,
	output [7:0] mcb_wr_mask_out,
	output reg [63:0] mcb_wr_data_out,
	input mcb_wr_full_in,
	input mcb_wr_empty_in,
	input mcb_wr_error_in,
	input mcb_wr_underrun_in,
	input [6:0] mcb_wr_count_in,
	
	output mcb_rd_en_out,
	input [63:0] mcb_rd_data_in,
	input mcb_rd_full_in,
	input mcb_rd_empty_in,
	input mcb_rd_error_in,
	input mcb_rd_overflow_in,
	input [6:0] mcb_rd_count_in
);


	assign mcb_wr_mask_out = 8'h0;
	assign mcb_rd_en_out = 1'b0;
	assign mcb_cmd_instr_out = 3'b000;
	assign mcb_cmd_bl_out = 6'h0;
	
	reg rd_rdy;

	reg toggle;

	always @ (posedge clk) begin
		if (rst) begin
			mcb_cmd_byte_addr_out <= 0;
			mcb_wr_en_out <= 0;
			mcb_wr_data_out <= 0;
			
			rd_en_out <= 0;
			rd_rdy <= 0;

			toggle <= 0;
			
		end else begin
		
			rd_rdy <= rd_en_out;

		
			if (!mcb_wr_full_in && !mcb_cmd_full_in) begin
				rd_en_out <= !rd_empty_in;
				if (rd_rdy && rd_en_out) begin
					if (rd_d_in[33]) begin



						mcb_wr_en_out <= 0;
						toggle <= 0;
						
					end else begin




						if (!toggle) begin
							mcb_wr_data_out[63:32] <= rd_d_in[31:0];
							mcb_wr_data_out[31:0] <= 0;
							mcb_wr_en_out <= 0;
						end else begin
							mcb_wr_data_out[31:0] <= rd_d_in[31:0];
							mcb_wr_en_out <= 1;
						end
						toggle <= !toggle;
					end
					
				end else begin


					mcb_wr_en_out <= 0;
				end
				
			end else begin

				rd_en_out <= 0;
				mcb_wr_en_out <= 0;
			end
			
			if (rd_d_in[33])
				mcb_cmd_byte_addr_out <= rd_d_in[29:0];
			else if (mcb_cmd_en_out)
				mcb_cmd_byte_addr_out <= mcb_cmd_byte_addr_out + 29'd8;
			
			mcb_cmd_en_out <= mcb_wr_en_out;
		end
	end
endmodule