data/full_repos/permissive/170013753/src/rom.v
data/verilator_xmls/d1ef5670-ebae-4f72-8075-2074fcc66493.xml
module rom(
  input  [15:0] addr,
  output reg [15:0] o
);

reg [15:0] memory [65535:0];




always @(addr) begin
  case(addr)

    16'd00:  o <= 16'b0000_0000_0000_0000;
    16'd02:  o <= 16'b1000_0001_0000_0010;
    16'd04:  o <= 16'b1000_0010_0000_0001;
    16'd06:  o <= 16'b0000_0011_0010_0001;
    16'd08:  o <= 16'b0001_0011_0011_0000;
    16'd10:  o <= 16'b0010_0010_0010_0011;
    16'd12:  o <= 16'b0011_0010_0011_0010;
    16'd14:  o <= 16'b0100_0100_0100_0000;
    16'd16:  o <= 16'b0101_0100_0100_0100;
    16'd18:  o <= 16'b0110_0010_0010_0000;
    16'd20:  o <= 16'b0111_0010_0010_0000;

    16'd22:  o <= 16'b0101_0001_0001_0001;
    16'd24:  o <= 16'b0101_0010_0010_0010;
    16'd26:  o <= 16'b0101_0011_0011_0011;
    16'd28:  o <= 16'b0101_0100_0100_0100;

    16'd30:  o <= 16'b1000_0001_1100_1100;
    16'd32:  o <= 16'b1000_0010_1010_1010;
    16'd34:  o <= 16'b1001_0011_0001_0010;

    16'd36:  o <= 16'b0101_0001_0001_0001;
    16'd38:  o <= 16'b0101_0010_0010_0010;
    16'd40:  o <= 16'b0101_0011_0011_0011;

    16'd42:  o <= 16'b1000_0001_0000_0010;
    16'd44:  o <= 16'b1000_0010_0000_1000;
    16'd46:  o <= 16'b1011_0000_0010_0001;
    16'd48:  o <= 16'b0101_0001_0001_0001;
    16'd50:  o <= 16'b1010_0001_0010_0000;
    16'd52:  o <= 16'b0000_0000_0001_0000;

    16'd54:  o <= 16'b0101_0001_0001_0001;
    16'd56:  o <= 16'b0101_0010_0010_0010;

    16'd58:  o <= 16'b1000_0001_0000_0011;
    16'd60:  o <= 16'b1100_0000_0000_0001;
    16'd62:  o <= 16'b0000_0000_0000_0000;
    16'd64:  o <= 16'b0000_0000_0000_0000;
    16'd66:  o <= 16'b0000_0000_0000_0000;
    16'd68:  o <= 16'b1000_0001_0000_0111;
    16'd70:  o <= 16'b0101_0001_0001_0001;

    16'd72:  o <= 16'b1000_0010_0101_0010;
    16'd74:  o <= 16'b1101_0001_0010_0000;
    16'd76:  o <= 16'b0000_0000_0000_0000;
    16'd78:  o <= 16'b0000_0000_0000_0000;
    16'd80:  o <= 16'b0000_0000_0000_0000;
    16'd82:  o <= 16'b0000_0001_0001_0000;
    16'd84:  o <= 16'b0101_0001_0001_0001;
    16'd86:  o <= 16'b0101_0010_0010_0010;

    default: o <= 16'b0000_0000_0000_0000;
  endcase
end

endmodule
module rom(
  input  [15:0] addr,
  output reg [15:0] o
);


reg [15:0] memory [65535:0];




always @(addr) begin
  case(addr)

    16'd00:  o <= 16'b0000_0000_0000_0000;
    16'd02:  o <= 16'b1000_0001_0000_0010;
    16'd04:  o <= 16'b1000_0010_0000_0001;
    16'd06:  o <= 16'b0000_0011_0010_0001;
    16'd08:  o <= 16'b0001_0011_0011_0000;
    16'd10:  o <= 16'b0010_0010_0010_0011;
    16'd12:  o <= 16'b0011_0010_0011_0010;
    16'd14:  o <= 16'b0100_0100_0100_0000;
    16'd16:  o <= 16'b0101_0100_0100_0100;
    16'd18:  o <= 16'b0110_0010_0010_0000;
    16'd20:  o <= 16'b0111_0010_0010_0000;

    16'd22:  o <= 16'b0101_0001_0001_0001;
    16'd24:  o <= 16'b0101_0010_0010_0010;
    16'd26:  o <= 16'b0101_0011_0011_0011;
    16'd28:  o <= 16'b0101_0100_0100_0100;

    16'd30:  o <= 16'b1000_0001_1100_1100;
    16'd32:  o <= 16'b1000_0010_1010_1010;
    16'd34:  o <= 16'b1001_0011_0001_0010;

    16'd36:  o <= 16'b0101_0001_0001_0001;
    16'd38:  o <= 16'b0101_0010_0010_0010;
    16'd40:  o <= 16'b0101_0011_0011_0011;

    16'd42:  o <= 16'b1000_0001_0000_0010;
    16'd44:  o <= 16'b1000_0010_0000_1000;
    16'd46:  o <= 16'b1011_0000_0010_0001;
    16'd48:  o <= 16'b0101_0001_0001_0001;
    16'd50:  o <= 16'b1010_0001_0010_0000;
    16'd52:  o <= 16'b0000_0000_0001_0000;

    16'd54:  o <= 16'b0101_0001_0001_0001;
    16'd56:  o <= 16'b0101_0010_0010_0010;

    16'd58:  o <= 16'b1000_0001_0000_0011;
    16'd60:  o <= 16'b1100_0000_0000_0001;
    16'd62:  o <= 16'b0000_0000_0000_0000;
    16'd64:  o <= 16'b0000_0000_0000_0000;
    16'd66:  o <= 16'b0000_0000_0000_0000;
    16'd68:  o <= 16'b1000_0001_0000_0111;
    16'd70:  o <= 16'b0101_0001_0001_0001;

    16'd72:  o <= 16'b1000_0010_0101_0010;
    16'd74:  o <= 16'b1101_0001_0010_0000;
    16'd76:  o <= 16'b0000_0000_0000_0000;
    16'd78:  o <= 16'b0000_0000_0000_0000;
    16'd80:  o <= 16'b0000_0000_0000_0000;
    16'd82:  o <= 16'b0000_0001_0001_0000;
    16'd84:  o <= 16'b0101_0001_0001_0001;
    16'd86:  o <= 16'b0101_0010_0010_0010;

    default: o <= 16'b0000_0000_0000_0000;
  endcase
end

endmodule