data/full_repos/permissive/167962127/wave_mux_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167962127/wave_mux_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167962127/wave_mux_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167962127/wave_mux_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167962127/wave_mux_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/167962127/wave_mux_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/167962127/wave_mux_tb.v:15: Cannot find file containing module: \'wave_mux\'\n  wave_mux UUT(\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/wave_mux\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/wave_mux.v\n             data/full_repos/permissive/167962127,data/full_repos/permissive/167962127/wave_mux.sv\n             wave_mux\n             wave_mux.v\n             wave_mux.sv\n             obj_dir/wave_mux\n             obj_dir/wave_mux.v\n             obj_dir/wave_mux.sv\n%Warning-WIDTH: data/full_repos/permissive/167962127/wave_mux_tb.v:29: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                     : ... In instance wave_mux_tb\n    r_sel <= 3\'b001;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/167962127/wave_mux_tb.v:31: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                     : ... In instance wave_mux_tb\n    r_sel <= 3\'b010;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/167962127/wave_mux_tb.v:33: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                     : ... In instance wave_mux_tb\n    r_sel <= 3\'b011;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/167962127/wave_mux_tb.v:35: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                     : ... In instance wave_mux_tb\n    r_sel <= 3\'b100;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/167962127/wave_mux_tb.v:37: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                     : ... In instance wave_mux_tb\n    r_sel <= 3\'b000;\n          ^~\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module wave_mux_tb();
  
  reg [1:0] r_sel = 2'b00;
  reg [15:0] r_sine = 16'hef;
  reg [15:0] r_noise = 16'hde;
  reg [15:0] r_saw = 16'hff;
  reg [15:0] r_tri = 16'had;
  reg [15:0] r_square = 16'hbe;

  wire [15:0] w_data;

  wave_mux UUT(
    .i_sel(r_sel),
    .i_sine(r_sine),
    .i_saw(r_saw),
    .i_square(r_square),
    .i_tri(r_tri),
    .i_noise(r_noise),
    .o_data(w_data)
  );


  always
  begin
    #100;
    r_sel <= 3'b001;
    #100;
    r_sel <= 3'b010;
    #100;
    r_sel <= 3'b011;
    #100;
    r_sel <= 3'b100;
    #100;
    r_sel <= 3'b000;
  end
endmodule
module wave_mux_tb();

  
  reg [1:0] r_sel = 2'b00;
  reg [15:0] r_sine = 16'hef;
  reg [15:0] r_noise = 16'hde;
  reg [15:0] r_saw = 16'hff;
  reg [15:0] r_tri = 16'had;
  reg [15:0] r_square = 16'hbe;

  wire [15:0] w_data;

  wave_mux UUT(
    .i_sel(r_sel),
    .i_sine(r_sine),
    .i_saw(r_saw),
    .i_square(r_square),
    .i_tri(r_tri),
    .i_noise(r_noise),
    .o_data(w_data)
  );


  always
  begin
    #100;
    r_sel <= 3'b001;
    #100;
    r_sel <= 3'b010;
    #100;
    r_sel <= 3'b011;
    #100;
    r_sel <= 3'b100;
    #100;
    r_sel <= 3'b000;
  end
endmodule