data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v
1: b'%Error: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:1: Cannot find include file: m.v\n`include "m.v" \n         ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1,data/full_repos/permissive/161314640/m.v\n             data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1,data/full_repos/permissive/161314640/m.v.v\n             data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1,data/full_repos/permissive/161314640/m.v.sv\n             m.v\n             m.v.v\n             m.v.sv\n             obj_dir/m.v\n             obj_dir/m.v.v\n             obj_dir/m.v.sv\n%Error: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:10: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("m.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:11: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, testbench);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:13: Unsupported or unknown PLI call: $monitor\n        $monitor("%b%b%b%b = %b %b %b %b %b",a,b,c,d,m1,m2,m3,m4,m5);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #1; reset =0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #1;ready=0; a=0; b=0; c=0; d=1; ready=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #1;ready=0; a=0; b=0; c=1; d=0; ready=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #1;ready=0; a=0; b=0; c=1; d=1; ready=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #1;ready=0; a=0; b=1; c=0; d=0; ready=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #1;ready=0; a=0; b=1; c=0; d=1; ready=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #1;ready=0; a=0; b=1; c=1; d=0; ready=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #1;ready=0; a=0; b=1; c=1; d=1; ready=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #1;ready=0; a=1; b=0; c=0; d=0; ready=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #1;ready=0; a=1; b=0; c=0; d=1; ready=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161314640/TP1-Codigo-Morse-CCF251/TP1-Codigo-Morse-Parte-1/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #1;ready=0; a=0; b=0; c=0; d=0; ready=1;\n        ^\n%Error: Exiting due to 4 error(s), 11 warning(s)\n'
module testbench ();
    reg a,b,c,d,reset,ready;
    wire m1,m2,m3,m4,m5;

    m instancial (.a(a), .b(b), .c(c), .d(d), .m1(m1),.m2(m2),.m3(m3),.m4(m4),.m5(m5),.reset(reset),.ready(ready));

    initial begin
        $dumpfile("m.vcd");
        $dumpvars(0, testbench);
        $display("a b c d = m1 m2 m3 m4 m5");
        $monitor("%b%b%b%b = %b %b %b %b %b",a,b,c,d,m1,m2,m3,m4,m5);
    end





    initial begin



            reset =1;
        #1; reset =0;
        #1;ready=0; a=0; b=0; c=0; d=1; ready=1;
        #1;ready=0; a=0; b=0; c=1; d=0; ready=1;
        #1;ready=0; a=0; b=0; c=1; d=1; ready=1;
        #1;ready=0; a=0; b=1; c=0; d=0; ready=1;
        #1;ready=0; a=0; b=1; c=0; d=1; ready=1;
        #1;ready=0; a=0; b=1; c=1; d=0; ready=1;
        #1;ready=0; a=0; b=1; c=1; d=1; ready=1;
        #1;ready=0; a=1; b=0; c=0; d=0; ready=1;
        #1;ready=0; a=1; b=0; c=0; d=1; ready=1;
        #1;ready=0; a=0; b=0; c=0; d=0; ready=1;

        $finish;
    end



endmodule
module testbench ();

    reg a,b,c,d,reset,ready;
    wire m1,m2,m3,m4,m5;

    m instancial (.a(a), .b(b), .c(c), .d(d), .m1(m1),.m2(m2),.m3(m3),.m4(m4),.m5(m5),.reset(reset),.ready(ready));

    initial begin
        $dumpfile("m.vcd");
        $dumpvars(0, testbench);
        $display("a b c d = m1 m2 m3 m4 m5");
        $monitor("%b%b%b%b = %b %b %b %b %b",a,b,c,d,m1,m2,m3,m4,m5);
    end





    initial begin



            reset =1;
        #1; reset =0;
        #1;ready=0; a=0; b=0; c=0; d=1; ready=1;
        #1;ready=0; a=0; b=0; c=1; d=0; ready=1;
        #1;ready=0; a=0; b=0; c=1; d=1; ready=1;
        #1;ready=0; a=0; b=1; c=0; d=0; ready=1;
        #1;ready=0; a=0; b=1; c=0; d=1; ready=1;
        #1;ready=0; a=0; b=1; c=1; d=0; ready=1;
        #1;ready=0; a=0; b=1; c=1; d=1; ready=1;
        #1;ready=0; a=1; b=0; c=0; d=0; ready=1;
        #1;ready=0; a=1; b=0; c=0; d=1; ready=1;
        #1;ready=0; a=0; b=0; c=0; d=0; ready=1;

        $finish;
    end



endmodule