data/full_repos/permissive/16552133/src/verilog/program_memory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/16552133/src/verilog/program_memory.v:40: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 1 bits.\n                                                                                   : ... In instance program_memory\n    data_out = pdra[address];\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/16552133/src/verilog/program_memory.v:46: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'bzzzzzzzzzzzzzzzz\' generates 16 bits.\n                                                                                   : ... In instance program_memory\n   data_out = 16\'hZZ;\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module program_memory #(parameter s_addr=1, parameter s_word=1)(clk,address,data_out,enable);
	parameter s_rom = (2**s_addr);
	parameter tclk = (5*2*20);
	integer i;
	input clk, enable;
	input [s_addr-1:0]address;
	output reg [s_rom-1:0]data_out;
	reg ready;
	reg [s_word-1:0]pdra [s_rom-1:0];
	
	initial begin

		$readmemb("program.mem",pdra);


	end
	
	always @(posedge clk)
	begin
		if (enable == 1) begin

				data_out = pdra[address];
			ready = 1;
				
		end
		else begin
			ready = 0;
			data_out = 16'hZZ;
		end
	end
	

endmodule
module program_memory #(parameter s_addr=1, parameter s_word=1)(clk,address,data_out,enable);

	parameter s_rom = (2**s_addr);
	parameter tclk = (5*2*20);
	integer i;
	input clk, enable;
	input [s_addr-1:0]address;
	output reg [s_rom-1:0]data_out;
	reg ready;
	reg [s_word-1:0]pdra [s_rom-1:0];
	
	initial begin

		$readmemb("program.mem",pdra);


	end
	
	always @(posedge clk)
	begin
		if (enable == 1) begin

				data_out = pdra[address];
			ready = 1;
				
		end
		else begin
			ready = 0;
			data_out = 16'hZZ;
		end
	end
	

endmodule