data/full_repos/permissive/167962127/amp.v
1: b'%Warning-WIDTH: data/full_repos/permissive/167962127/amp.v:14: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                             : ... In instance amp\n    o_data <= r_temp >> 16;\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module amp(
  input i_clk,
  input [15:0] i_wave,
  input [15:0] i_amp,
  output reg [15:0] o_data
);


  reg [31:0] r_temp;

  always @ (posedge i_clk)
  begin
    r_temp <= i_wave * i_amp;
    o_data <= r_temp >> 16;
  end

endmodule
module amp(
  input i_clk,
  input [15:0] i_wave,
  input [15:0] i_amp,
  output reg [15:0] o_data
);



  reg [31:0] r_temp;

  always @ (posedge i_clk)
  begin
    r_temp <= i_wave * i_amp;
    o_data <= r_temp >> 16;
  end

endmodule