data/full_repos/permissive/136422019/src/Clock.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/136422019/src/Clock.v:8: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/Clock.v:10: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Clock(
	output reg clk
);

always begin
	clk = 1;
	#50;
	clk = 0;
	#50;
end

endmodule
module Clock(
	output reg clk
);


always begin
	clk = 1;
	#50;
	clk = 0;
	#50;
end

endmodule