data/full_repos/permissive/175132042/rtl/picorv32/scripts/smtbmc/opcode.v
 line:1: before: "function"
1: b'%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/picorv32/scripts/smtbmc/opcode.v:82: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n  if (opcode[31:20] == 12\'hC00 && opcode[19:12] == 3\'b010 && opcode[6:0] == 7\'b1110011) opcode_sys = 1;  \n                                                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/picorv32/scripts/smtbmc/opcode.v:83: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n  if (opcode[31:20] == 12\'hC01 && opcode[19:12] == 3\'b010 && opcode[6:0] == 7\'b1110011) opcode_sys = 1;  \n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/picorv32/scripts/smtbmc/opcode.v:84: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n  if (opcode[31:20] == 12\'hC02 && opcode[19:12] == 3\'b010 && opcode[6:0] == 7\'b1110011) opcode_sys = 1;  \n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/picorv32/scripts/smtbmc/opcode.v:85: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n  if (opcode[31:20] == 12\'hC80 && opcode[19:12] == 3\'b010 && opcode[6:0] == 7\'b1110011) opcode_sys = 1;  \n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/picorv32/scripts/smtbmc/opcode.v:86: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n  if (opcode[31:20] == 12\'hC81 && opcode[19:12] == 3\'b010 && opcode[6:0] == 7\'b1110011) opcode_sys = 1;  \n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/picorv32/scripts/smtbmc/opcode.v:87: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n  if (opcode[31:20] == 12\'hC82 && opcode[19:12] == 3\'b010 && opcode[6:0] == 7\'b1110011) opcode_sys = 1;  \n                                                ^~\n%Error: Exiting due to 6 warning(s)\n'
function opcode_valid;
	input [31:0] opcode;
	begin
		opcode_valid = 0;
		if (opcode_jump  (opcode)) opcode_valid = 1;
		if (opcode_branch(opcode)) opcode_valid = 1;
		if (opcode_load  (opcode)) opcode_valid = 1;
		if (opcode_store (opcode)) opcode_valid = 1;
		if (opcode_alui  (opcode)) opcode_valid = 1;
		if (opcode_alu   (opcode)) opcode_valid = 1;
		if (opcode_sys   (opcode)) opcode_valid = 1;
	end
endfunction
function opcode_valid;

	input [31:0] opcode;
	begin
		opcode_valid = 0;
		if (opcode_jump  (opcode)) opcode_valid = 1;
		if (opcode_branch(opcode)) opcode_valid = 1;
		if (opcode_load  (opcode)) opcode_valid = 1;
		if (opcode_store (opcode)) opcode_valid = 1;
		if (opcode_alui  (opcode)) opcode_valid = 1;
		if (opcode_alu   (opcode)) opcode_valid = 1;
		if (opcode_sys   (opcode)) opcode_valid = 1;
	end
endfunction