data/full_repos/permissive/170402453/SMPS_ZVS/SMPS_ZVS_Controller.v
 line:55: before: "."
1: b'%Error: data/full_repos/permissive/170402453/SMPS_ZVS/SMPS_ZVS_Controller.v:56: Cannot find file containing module: \'SubClock\'\n SubClock sc1(clk, PWMCLK);\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170402453/SMPS_ZVS,data/full_repos/permissive/170402453/SubClock\n             data/full_repos/permissive/170402453/SMPS_ZVS,data/full_repos/permissive/170402453/SubClock.v\n             data/full_repos/permissive/170402453/SMPS_ZVS,data/full_repos/permissive/170402453/SubClock.sv\n             SubClock\n             SubClock.v\n             SubClock.sv\n             obj_dir/SubClock\n             obj_dir/SubClock.v\n             obj_dir/SubClock.sv\n%Error: data/full_repos/permissive/170402453/SMPS_ZVS/SMPS_ZVS_Controller.v:58: Cannot find file containing module: \'PWMR\'\n PWMR p1(CLK1, 0, DutyCycle, SMPS_Driver1);  \n ^~~~\n%Error: data/full_repos/permissive/170402453/SMPS_ZVS/SMPS_ZVS_Controller.v:59: Cannot find file containing module: \'PWMR\'\n PWMR p2(CLK2, 0, DutyCycle, SMPS_Driver2);  \n ^~~~\n%Error: data/full_repos/permissive/170402453/SMPS_ZVS/SMPS_ZVS_Controller.v:60: Cannot find file containing module: \'PWMR\'\n PWMR p3(CLK3, rst3, DutyCycle, SMPS_Driver3);  \n ^~~~\n%Error: data/full_repos/permissive/170402453/SMPS_ZVS/SMPS_ZVS_Controller.v:61: Cannot find file containing module: \'PWMR\'\n PWMR p4(CLK4, rst4, DutyCycle, SMPS_Driver4);  \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170402453/SMPS_ZVS/SMPS_ZVS_Controller.v:95: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 24 bits.\n                                                                                      : ... In instance SMPS_ZVS_Controller\n     phase = ((SMPS_50V_VSense>SMPS_50V_CSense) ?  \n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module SMPS_ZVS_Controller(
    input clk,
    input [23:0] SMPS_50V_VSense,
    input [23:0] SMPS_50V_CSense,
    output SMPS_Driver1,
    output SMPS_Driver2,
    output SMPS_Driver3,
    output SMPS_Driver4
    );
	 


	reg [7:0] DutyCycle;
	reg CLK1,CLK2,CLK3,CLK4;
	reg [7:0] phase;
	reg [8:0] mainPhase1;
	wire PWMCLK;
	reg [7:0] phase2,phase4;
	reg rst3, rst4;
	
	initial begin
		DutyCycle=102;
		CLK1=0;
		CLK2=0;
		CLK3=0;
		CLK4=0;
		phase=0;
		phase2=255;
		phase4=255;
		rst3=0;
		rst4=0;
		mainPhase1=0;
	end
	
	defparam sc1.Divider=4;
	SubClock sc1(clk, PWMCLK);
	
	PWMR p1(CLK1, 0, DutyCycle, SMPS_Driver1);
	PWMR p2(CLK2, 0, DutyCycle, SMPS_Driver2);
	PWMR p3(CLK3, rst3, DutyCycle, SMPS_Driver3);
	PWMR p4(CLK4, rst4, DutyCycle, SMPS_Driver4);
	
	always @(posedge PWMCLK) begin

		rst3=0;
		rst4=0;
		
		CLK1=~CLK1;
		mainPhase1 = mainPhase1+1;
		

		if(phase2==0) begin
			CLK2=~CLK2;
		end
		phase2 = (phase2>0) ? phase2-1 : 0;
		

		if(phase==0) begin
			CLK3=~CLK3;
			if(phase4==0) begin
				CLK4=~CLK4;
			end else phase4 = (phase4==0) ? 255 : phase4;
			phase4 = (phase4>0) ? phase4-1 : 0;
			


			if(mainPhase1 == 0) begin

				rst3=1;
				rst4=1;
				phase4=255;


				if(SMPS_50V_VSense < 12007693) begin
					phase = ((SMPS_50V_VSense>SMPS_50V_CSense) ?
								(SMPS_50V_VSense-SMPS_50V_CSense) :
								(SMPS_50V_CSense-SMPS_50V_VSense)
							  )>>17;
				end else phase=0;
			end
		end else phase = (phase==0) ? 255 : phase;
		phase = (phase>0) ? phase-1 : 0;
	end
endmodule
module SMPS_ZVS_Controller(
    input clk,
    input [23:0] SMPS_50V_VSense,
    input [23:0] SMPS_50V_CSense,
    output SMPS_Driver1,
    output SMPS_Driver2,
    output SMPS_Driver3,
    output SMPS_Driver4
    );

	 


	reg [7:0] DutyCycle;
	reg CLK1,CLK2,CLK3,CLK4;
	reg [7:0] phase;
	reg [8:0] mainPhase1;
	wire PWMCLK;
	reg [7:0] phase2,phase4;
	reg rst3, rst4;
	
	initial begin
		DutyCycle=102;
		CLK1=0;
		CLK2=0;
		CLK3=0;
		CLK4=0;
		phase=0;
		phase2=255;
		phase4=255;
		rst3=0;
		rst4=0;
		mainPhase1=0;
	end
	
	defparam sc1.Divider=4;
	SubClock sc1(clk, PWMCLK);
	
	PWMR p1(CLK1, 0, DutyCycle, SMPS_Driver1);
	PWMR p2(CLK2, 0, DutyCycle, SMPS_Driver2);
	PWMR p3(CLK3, rst3, DutyCycle, SMPS_Driver3);
	PWMR p4(CLK4, rst4, DutyCycle, SMPS_Driver4);
	
	always @(posedge PWMCLK) begin

		rst3=0;
		rst4=0;
		
		CLK1=~CLK1;
		mainPhase1 = mainPhase1+1;
		

		if(phase2==0) begin
			CLK2=~CLK2;
		end
		phase2 = (phase2>0) ? phase2-1 : 0;
		

		if(phase==0) begin
			CLK3=~CLK3;
			if(phase4==0) begin
				CLK4=~CLK4;
			end else phase4 = (phase4==0) ? 255 : phase4;
			phase4 = (phase4>0) ? phase4-1 : 0;
			


			if(mainPhase1 == 0) begin

				rst3=1;
				rst4=1;
				phase4=255;


				if(SMPS_50V_VSense < 12007693) begin
					phase = ((SMPS_50V_VSense>SMPS_50V_CSense) ?
								(SMPS_50V_VSense-SMPS_50V_CSense) :
								(SMPS_50V_CSense-SMPS_50V_VSense)
							  )>>17;
				end else phase=0;
			end
		end else phase = (phase==0) ? 255 : phase;
		phase = (phase>0) ? phase-1 : 0;
	end
endmodule