data/full_repos/permissive/175132042/simulation/uart_interrupt.v
None: at end of input
1: b'%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:11: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175132042/simulation,data/full_repos/permissive/175132042/timescale.v\n             data/full_repos/permissive/175132042/simulation,data/full_repos/permissive/175132042/timescale.v.v\n             data/full_repos/permissive/175132042/simulation,data/full_repos/permissive/175132042/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:12: Cannot find include file: simulation_includes.vh\n`include "simulation_includes.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:21: Cannot find include file: setup.v\n`include "setup.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:29: syntax error, unexpected \'@\'\n      @(posedge `WB_RST);\n      ^\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:29: Define or directive not defined: \'`WB_RST\'\n      @(posedge `WB_RST);\n                ^~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:30: Define or directive not defined: \'`WB_RST\'\n      @(negedge `WB_RST);\n                ^~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:31: Define or directive not defined: \'`WB_CLK\'\n      @(posedge `WB_CLK);\n                ^~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:32: Define or directive not defined: \'`UART_CONFIG\'\n      `UART_CONFIG;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:37: Define or directive not defined: \'`TRIGGER\'\n      @(posedge `TRIGGER[0]);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:38: Define or directive not defined: \'`TEST_COMPARE\'\n      `TEST_COMPARE("TRIGGER HIGH", 1, `TRIGGER[0]);\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:38: syntax error, unexpected \',\'\n      `TEST_COMPARE("TRIGGER HIGH", 1, `TRIGGER[0]);\n                                  ^\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:38: Define or directive not defined: \'`TRIGGER\'\n      `TEST_COMPARE("TRIGGER HIGH", 1, `TRIGGER[0]);\n                                       ^~~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:40: Define or directive not defined: \'`UART_WRITE_CHAR\'\n      `UART_WRITE_CHAR("A");\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:40: syntax error, unexpected \';\'\n      `UART_WRITE_CHAR("A");\n                           ^\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:41: Define or directive not defined: \'`UART_READ_CHAR\'\n      `UART_READ_CHAR("A");\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:41: syntax error, unexpected \';\'\n      `UART_READ_CHAR("A");\n                          ^\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:43: Define or directive not defined: \'`UART_WRITE_CHAR\'\n      `UART_WRITE_CHAR("B");\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:43: syntax error, unexpected \';\'\n      `UART_WRITE_CHAR("B");\n                           ^\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:44: Define or directive not defined: \'`UART_READ_CHAR\'\n      `UART_READ_CHAR("B");\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:44: syntax error, unexpected \';\'\n      `UART_READ_CHAR("B");\n                          ^\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:46: Define or directive not defined: \'`UART_WRITE_CHAR\'\n      `UART_WRITE_CHAR("C");\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:46: syntax error, unexpected \';\'\n      `UART_WRITE_CHAR("C");\n                           ^\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:47: Define or directive not defined: \'`UART_READ_CHAR\'\n      `UART_READ_CHAR("C");\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:47: syntax error, unexpected \';\'\n      `UART_READ_CHAR("C");\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #10000;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/175132042/simulation/uart_interrupt.v:51: Define or directive not defined: \'`TEST_COMPLETE\'\n      `TEST_COMPLETE;      \n      ^~~~~~~~~~~~~~\n%Error: Exiting due to 25 error(s), 1 warning(s)\n'
module test_case ();





   parameter simulation_name = "uart_interrupt";    
   parameter number_of_tests = 5;
`include "setup.v"

   reg  err;
   reg [31:0] data_out;
   integer    i;
   
   initial begin
      $display("Boot Case");
      @(posedge `WB_RST);
      @(negedge `WB_RST);
      @(posedge `WB_CLK);
      `UART_CONFIG;




      @(posedge `TRIGGER[0]);
      `TEST_COMPARE("TRIGGER HIGH", 1, `TRIGGER[0]);
      
      `UART_WRITE_CHAR("A");
      `UART_READ_CHAR("A");

      `UART_WRITE_CHAR("B");
      `UART_READ_CHAR("B");

      `UART_WRITE_CHAR("C");
      `UART_READ_CHAR("C");

      
      #10000;
      `TEST_COMPLETE;      
   end

endmodule
module test_case ();






   parameter simulation_name = "uart_interrupt";    
   parameter number_of_tests = 5;
`include "setup.v"

   reg  err;
   reg [31:0] data_out;
   integer    i;
   
   initial begin
      $display("Boot Case");
      @(posedge `WB_RST);
      @(negedge `WB_RST);
      @(posedge `WB_CLK);
      `UART_CONFIG;




      @(posedge `TRIGGER[0]);
      `TEST_COMPARE("TRIGGER HIGH", 1, `TRIGGER[0]);
      
      `UART_WRITE_CHAR("A");
      `UART_READ_CHAR("A");

      `UART_WRITE_CHAR("B");
      `UART_READ_CHAR("B");

      `UART_WRITE_CHAR("C");
      `UART_READ_CHAR("C");

      
      #10000;
      `TEST_COMPLETE;      
   end

endmodule