data/full_repos/permissive/165846232/components/Debouncer/Debouncer.v
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data/verilator_xmls/5d86551d-f534-4c30-b9a4-dda3e350072e.xml
module Debouncer
#(
    parameter DEBOUNCER_COUNTER_WIDTH = 19
) (
    input Clk,
    input Input,
    output reg State = 0,
    output Output
);

    reg Sync0 = 0, Sync1 = 0;

    reg [DEBOUNCER_COUNTER_WIDTH-1:0] Counter;
    wire Idle = (State == Sync1);
    wire Max = &Counter;

    always @(posedge Clk)
    begin
        Sync0 <= Input;
        Sync1 <= Sync0;
        if(Idle)
            Counter <= 0;
        else
        begin
            Counter <= Counter + 1;
            if(Max)
                State <= ~State;
        end
    end

    assign Output = ~Idle & Max & ~State;
endmodule
module Debouncer
#(
    parameter DEBOUNCER_COUNTER_WIDTH = 19
) (
    input Clk,
    input Input,
    output reg State = 0,
    output Output
);


    reg Sync0 = 0, Sync1 = 0;

    reg [DEBOUNCER_COUNTER_WIDTH-1:0] Counter;
    wire Idle = (State == Sync1);
    wire Max = &Counter;

    always @(posedge Clk)
    begin
        Sync0 <= Input;
        Sync1 <= Sync0;
        if(Idle)
            Counter <= 0;
        else
        begin
            Counter <= Counter + 1;
            if(Max)
                State <= ~State;
        end
    end

    assign Output = ~Idle & Max & ~State;
endmodule