data/full_repos/permissive/159479522/tb_washing_machine.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/159479522/tb_washing_machine.v:44: Unsupported: Ignoring delay on this delayed statement.\n          #(5) start_pause <= 1;  \n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159479522/tb_washing_machine.v:47: Unsupported: Ignoring delay on this delayed statement.\n          #(5) clk <= ~clk;\n          ^\n%Error: data/full_repos/permissive/159479522/tb_washing_machine.v:33: Cannot find file containing module: \'Washing_machine\'\n     Washing_machine tb (clk,reset,start_pause,module_select,water_select,power_led,start_led,\n     ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159479522,data/full_repos/permissive/159479522/Washing_machine\n             data/full_repos/permissive/159479522,data/full_repos/permissive/159479522/Washing_machine.v\n             data/full_repos/permissive/159479522,data/full_repos/permissive/159479522/Washing_machine.sv\n             Washing_machine\n             Washing_machine.v\n             Washing_machine.sv\n             obj_dir/Washing_machine\n             obj_dir/Washing_machine.v\n             obj_dir/Washing_machine.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_washing_machine();
reg   clk,reset,start_pause,module_select,water_select;
    wire   in_led,out_led;
    wire  start_led,power_led,wash_led,rinse_led,dry_led;
    wire [3:0] water_level;
    wire [2:0] model_now;
    wire [5:0] time_now;   
    wire [5:0] time_all;      
    wire power_off;
    wire if_finish;  
     Washing_machine tb (clk,reset,start_pause,module_select,water_select,power_led,start_led,
    wash_led,rinse_led,dry_led,in_led,out_led,state,count,buzzer_led,
    water_level,model_now,time_now,time_all,power_off,if_finish);
   initial    begin
        clk <= 1;
             end   
       initial    begin
          reset <= 1;
          start_pause <= 0;
          water_select <= 0;
          module_select <= 0;        
          #(5) start_pause <= 1;  
          end    
          always  begin
          #(5) clk <= ~clk;
          end 
endmodule
module tb_washing_machine();

reg   clk,reset,start_pause,module_select,water_select;
    wire   in_led,out_led;
    wire  start_led,power_led,wash_led,rinse_led,dry_led;
    wire [3:0] water_level;
    wire [2:0] model_now;
    wire [5:0] time_now;   
    wire [5:0] time_all;      
    wire power_off;
    wire if_finish;  
     Washing_machine tb (clk,reset,start_pause,module_select,water_select,power_led,start_led,
    wash_led,rinse_led,dry_led,in_led,out_led,state,count,buzzer_led,
    water_level,model_now,time_now,time_all,power_off,if_finish);
   initial    begin
        clk <= 1;
             end   
       initial    begin
          reset <= 1;
          start_pause <= 0;
          water_select <= 0;
          module_select <= 0;        
          #(5) start_pause <= 1;  
          end    
          always  begin
          #(5) clk <= ~clk;
          end 
endmodule