data/full_repos/permissive/139213403/FPGA/uart_test.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/139213403/FPGA/uart_test.v:17: Cannot find file containing module: 'uart'\nuart uart_unit(clk, reset, btn_tick, btn_tick, rx, rec_data1, tx_full, rx_empty, rec_data, tx);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/uart\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/uart.v\n             data/full_repos/permissive/139213403/FPGA,data/full_repos/permissive/139213403/uart.sv\n             uart\n             uart.v\n             uart.sv\n             obj_dir/uart\n             obj_dir/uart.v\n             obj_dir/uart.sv\n%Error: data/full_repos/permissive/139213403/FPGA/uart_test.v:18: Cannot find file containing module: 'debounce'\ndebounce btn_db_unit(clk, reset, btn[0], btn_tick);\n^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module uart_test
(
	input wire clk, reset,
	input wire rx,
	input wire [2:0] btn,
	output wire tx,
	output wire [3:0] an,
	output wire [6:0] sseg, led
);


wire tx_full, rx_empty, btn_tick;
wire [7:0] rec_data, rec_data1;



uart uart_unit(clk, reset, btn_tick, btn_tick, rx, rec_data1, tx_full, rx_empty, rec_data, tx);
debounce btn_db_unit(clk, reset, btn[0], btn_tick);

assign rec_data1 = rec_data + 1'b1;

assign led = rec_data[6:0];
assign an = 4'b1110;
assign sseg = {1'b1, ~tx_full, 2'b11, ~rx_empty, 2'b11}; 

endmodule
module uart_test
(
	input wire clk, reset,
	input wire rx,
	input wire [2:0] btn,
	output wire tx,
	output wire [3:0] an,
	output wire [6:0] sseg, led
);



wire tx_full, rx_empty, btn_tick;
wire [7:0] rec_data, rec_data1;



uart uart_unit(clk, reset, btn_tick, btn_tick, rx, rec_data1, tx_full, rx_empty, rec_data, tx);
debounce btn_db_unit(clk, reset, btn[0], btn_tick);

assign rec_data1 = rec_data + 1'b1;

assign led = rec_data[6:0];
assign an = 4'b1110;
assign sseg = {1'b1, ~tx_full, 2'b11, ~rx_empty, 2'b11}; 

endmodule