data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/MP3_Controller.v
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/MP3_Controller.v\n%Error: Exiting due to 4 error(s)\n'
module MP3_Controller(
    input [5:0] Number_to_Play,
	 input clock,
	 input enable,
    output reg [18:1] trigger_out
	 
    );
	 
	 reg [18:1] trigger = 0;
always@(*)
begin

	trigger = 18'b111111111111111111;

	case(Number_to_Play)
	
	1	:	trigger[1] = 0;
	2	:	trigger[2] = 0;
	3	:	trigger[3] = 0;
	4	:	trigger[4] = 0;
	5	:	trigger[5] = 0;
	6	:	trigger[6] = 0;
	7	:	trigger[7] = 0;
	8	:	trigger[8] = 0;
	9	:	trigger[9] = 0;
	10	:	trigger[10] = 0;
	11	:	trigger[11] = 0;
	12	:	trigger[12] = 0;
	13	:	trigger[13] = 0;
	14	:	trigger[14] = 0;
	15	:	trigger[15] = 0;
	16	:	trigger[16] = 0;
	17	:	trigger[17] = 0;
	18	:	trigger[18] = 0;
	
	default : trigger = 18'b111111111111111111;
	

	endcase 

end

always@(posedge clock)
begin
	if(enable)
		trigger_out <= trigger;
end
endmodule
module MP3_Controller(
    input [5:0] Number_to_Play,
	 input clock,
	 input enable,
    output reg [18:1] trigger_out
	 
    );

	 
	 reg [18:1] trigger = 0;
always@(*)
begin

	trigger = 18'b111111111111111111;

	case(Number_to_Play)
	
	1	:	trigger[1] = 0;
	2	:	trigger[2] = 0;
	3	:	trigger[3] = 0;
	4	:	trigger[4] = 0;
	5	:	trigger[5] = 0;
	6	:	trigger[6] = 0;
	7	:	trigger[7] = 0;
	8	:	trigger[8] = 0;
	9	:	trigger[9] = 0;
	10	:	trigger[10] = 0;
	11	:	trigger[11] = 0;
	12	:	trigger[12] = 0;
	13	:	trigger[13] = 0;
	14	:	trigger[14] = 0;
	15	:	trigger[15] = 0;
	16	:	trigger[16] = 0;
	17	:	trigger[17] = 0;
	18	:	trigger[18] = 0;
	
	default : trigger = 18'b111111111111111111;
	

	endcase 

end

always@(posedge clock)
begin
	if(enable)
		trigger_out <= trigger;
end
endmodule