data/full_repos/permissive/104269513/mem_mod_master2_32bit - FinalFSM - final project_combined.v
 line:310: before: ")"
1: b'%Error: Invalid Option: -\n'
module mem_mod_mast
			#( 	parameter UDP_REG_SRC_WIDTH = 2,
				parameter MAX_DEPTH = 256,
				parameter ADDR_WIDTH = 8,
				parameter DATA_WIDTH = 64,
				parameter CTRL_WIDTH = DATA_WIDTH/8
			)
			(

				input 	[DATA_WIDTH-1:0]			in_data,
				input 	[CTRL_WIDTH-1:0]			in_ctrl,
				output 	[DATA_WIDTH-1:0]			out_data,
				output 	[CTRL_WIDTH-1:0]			out_ctrl,


				input 								out_rdy,
				input 								in_wr,
				output 								in_rdy,
				output 								out_wr,
				

				input                               reg_req_in,
				input                               reg_ack_in,
				input                               reg_rd_wr_L_in,
				input  [`UDP_REG_ADDR_WIDTH-1:0]    reg_addr_in,
				input  [`CPCI_NF2_DATA_WIDTH-1:0]   reg_data_in,
				input  [UDP_REG_SRC_WIDTH-1:0]     	reg_src_in,

				output                              reg_req_out,
				output                              reg_ack_out,
				output                              reg_rd_wr_L_out,
				output  [`UDP_REG_ADDR_WIDTH-1:0]   reg_addr_out,
				output  [`CPCI_NF2_DATA_WIDTH-1:0]  reg_data_out,
				output  [UDP_REG_SRC_WIDTH-1:0]    	reg_src_out,
					

				input clk,
				input rst				
				);
					
					

wire [31:0] cmd;










wire IorD;
wire [8:0] Addr_in;
wire [DATA_WIDTH-1:0] Data_In;
wire [DATA_WIDTH-1:0] Data_out_DM;
wire full,empty;
wire nearly_full,nearly_empty;

wire [7:0] FIFO_RD_addr;
wire [7:0] FIFO_WR_addr;
wire [1:0] fifo_state;
wire [8:0] DEPTH;
wire PL_EN, SW_CTRL;
wire [1:0] fifo_rd_en, fifo_wr_en;
wire [1:0] packet_count;
wire PL1_done;
wire [2:0] ip_fifo_sel;	



wire [DATA_WIDTH-1:0] in_data_MC, in_data_PLDCF;
wire [CTRL_WIDTH-1:0] in_ctrl_MC, in_ctrl_PLDCF;
wire in_rdy_MC, in_rdy_PLDCF;
wire in_wr_MC, in_wr_PLDCF;





























 generic_regs
   #( 
      .UDP_REG_SRC_WIDTH   (UDP_REG_SRC_WIDTH),
      .TAG                 (`MEM_BLOCK_ADDR),
      .REG_ADDR_WIDTH      (`MEM_REG_ADDR_WIDTH),
      .NUM_COUNTERS        (0),
      .NUM_SOFTWARE_REGS   (3),
      .NUM_HARDWARE_REGS   (4)
   ) module_regs (
      .reg_req_in       (reg_req_in),
      .reg_ack_in       (reg_ack_in),
      .reg_rd_wr_L_in   (reg_rd_wr_L_in),
      .reg_addr_in      (reg_addr_in),
      .reg_data_in      (reg_data_in),
      .reg_src_in       (reg_src_in),

      .reg_req_out      (reg_req_out),
      .reg_ack_out      (reg_ack_out),
      .reg_rd_wr_L_out  (reg_rd_wr_L_out),
      .reg_addr_out     (reg_addr_out),
      .reg_data_out     (reg_data_out),
      .reg_src_out      (reg_src_out),


      .counter_updates  (),
      .counter_decrement(),


      .software_regs    ({cmd,Data_In}),


      .hardware_regs    ({26'h0,packet_count,PL_EN,SW_CTRL,fifo_state,fifo_rd_en,fifo_wr_en,FIFO_WR_addr,FIFO_RD_addr, full, empty, out_rdy, DEPTH, Data_out_DM}),

      .clk              (clk),
      .reset            (rst)
    );







pipeline 	 	#(
				.ADDR_WIDTH(ADDR_WIDTH),
				.DATA_WIDTH(DATA_WIDTH),
				.CTRL_WIDTH(CTRL_WIDTH),
				.Number_of_FIFO(`Number_of_FIFO)
				)
				PL1
				(

				.in_data(in_data),
				.in_ctrl(in_ctrl),
				.out_data(in_data_MC),
				.out_ctrl(in_ctrl_MC),


				.out_rdy(in_rdy_MC),
				.in_wr(in_wr),
				.in_rdy(in_rdy),
				.out_wr(in_wr_MC),
				

				.IorD(),
				.Addr_in(),
				.Data_In(),
				

				.Addr_DM(),
				.Addr_IM(),		
				.Data_out_IM(),
				.Data_out_DM(),
				.full(),
				.empty(),			
				.fifo_busy(),			
				.packet_count(),			
				.FIFO_RD_addr(),
				.FIFO_WR_addr(),
				.fifo_state(),
				.DEPTH(),
				.PL_EN(),
				.SW_CTRL(),
				.fifo_rd_en(),
				.fifo_wr_en(),
				

				.op_fifo_sel(ip_fifo_sel),
				.PL_done(PL1_done),
				

				.clk(clk),
				.rst(rst)
				);
 			
master_ctrl	#(
				.ADDR_WIDTH(ADDR_WIDTH),
				.DATA_WIDTH(DATA_WIDTH),
				.CTRL_WIDTH(CTRL_WIDTH),
				.Number_of_FIFO(`Number_of_FIFO)
			)
			UUT
			(	

				.ip_fifo_sel(ip_fifo_sel),
				.ip_PL_done(PL1_done),
				

				

				.in_rdy(in_rdy_MC),
				.in_wr(in_wr_MC),
				.out_rdy(in_rdy_PLDCF),
				.out_wr(in_wr_PLDCF),
				

				.pckt_count(),
				.state(),
				.full(),
				.nearly_full(),
				.nearly_empty(),
				.empty(),
				.pckt_rd_wr(),
				

				.fifo_data_in(in_data_MC),
				.fifo_data_out(in_data_PLDCF),
				.fifo_ctrl_in(in_ctrl_MC),
				.fifo_ctrl_out(in_ctrl_PLDCF),
				

				.clk(clk),
				.rst(rst)

			);			
			

pipeline_dualCF #(
				.MAX_DEPTH(MAX_DEPTH),
				.ADDR_WIDTH(ADDR_WIDTH),
				.DATA_WIDTH(DATA_WIDTH),
				.CTRL_WIDTH(CTRL_WIDTH),
				.Number_of_FIFO()
				)
				PL2
				(

				.in_data(in_data_PLDCF),
				.in_ctrl(in_ctrl_PLDCF),
				.out_data(out_data),
				.out_ctrl(out_ctrl),


				.out_rdy(out_rdy),
				.in_wr(in_wr_PLDCF),
				.in_rdy(in_rdy_PLDCF),
				.out_wr(out_wr),
				

				.IorD(),
				.Addr_in(),
				.Data_In(),
				

				.Addr_DM(),
				.Addr_IM(),		
				.Data_out_IM(),
				.Data_out_DM(),
				.full(),
				.nearly_full(),
				.nearly_empty(),
				.empty(),			
				.fifo_busy(),			
				.packet_count(),			
				.FIFO_RD_addr(),
				.FIFO_WR_addr(),
				.fifo_state(),
				.DEPTH(),
				.PL_EN(),
				.SW_CTRL(),
				.fifo_rd_en(),
				.fifo_wr_en(),
				

				.Master_reg(),
				

				.clk(clk),
				.rst(rst)
				);
 
 
assign MOD = {cmd[31],cmd[27]};
assign IorD = cmd[29];
assign Addr_in = cmd[8:0];




endmodule
module mem_mod_mast
			#( 	parameter UDP_REG_SRC_WIDTH = 2,
				parameter MAX_DEPTH = 256,
				parameter ADDR_WIDTH = 8,
				parameter DATA_WIDTH = 64,
				parameter CTRL_WIDTH = DATA_WIDTH/8
			)
			(

				input 	[DATA_WIDTH-1:0]			in_data,
				input 	[CTRL_WIDTH-1:0]			in_ctrl,
				output 	[DATA_WIDTH-1:0]			out_data,
				output 	[CTRL_WIDTH-1:0]			out_ctrl,


				input 								out_rdy,
				input 								in_wr,
				output 								in_rdy,
				output 								out_wr,
				

				input                               reg_req_in,
				input                               reg_ack_in,
				input                               reg_rd_wr_L_in,
				input  [`UDP_REG_ADDR_WIDTH-1:0]    reg_addr_in,
				input  [`CPCI_NF2_DATA_WIDTH-1:0]   reg_data_in,
				input  [UDP_REG_SRC_WIDTH-1:0]     	reg_src_in,

				output                              reg_req_out,
				output                              reg_ack_out,
				output                              reg_rd_wr_L_out,
				output  [`UDP_REG_ADDR_WIDTH-1:0]   reg_addr_out,
				output  [`CPCI_NF2_DATA_WIDTH-1:0]  reg_data_out,
				output  [UDP_REG_SRC_WIDTH-1:0]    	reg_src_out,
					

				input clk,
				input rst				
				);

					
					

wire [31:0] cmd;










wire IorD;
wire [8:0] Addr_in;
wire [DATA_WIDTH-1:0] Data_In;
wire [DATA_WIDTH-1:0] Data_out_DM;
wire full,empty;
wire nearly_full,nearly_empty;

wire [7:0] FIFO_RD_addr;
wire [7:0] FIFO_WR_addr;
wire [1:0] fifo_state;
wire [8:0] DEPTH;
wire PL_EN, SW_CTRL;
wire [1:0] fifo_rd_en, fifo_wr_en;
wire [1:0] packet_count;
wire PL1_done;
wire [2:0] ip_fifo_sel;	



wire [DATA_WIDTH-1:0] in_data_MC, in_data_PLDCF;
wire [CTRL_WIDTH-1:0] in_ctrl_MC, in_ctrl_PLDCF;
wire in_rdy_MC, in_rdy_PLDCF;
wire in_wr_MC, in_wr_PLDCF;





























 generic_regs
   #( 
      .UDP_REG_SRC_WIDTH   (UDP_REG_SRC_WIDTH),
      .TAG                 (`MEM_BLOCK_ADDR),
      .REG_ADDR_WIDTH      (`MEM_REG_ADDR_WIDTH),
      .NUM_COUNTERS        (0),
      .NUM_SOFTWARE_REGS   (3),
      .NUM_HARDWARE_REGS   (4)
   ) module_regs (
      .reg_req_in       (reg_req_in),
      .reg_ack_in       (reg_ack_in),
      .reg_rd_wr_L_in   (reg_rd_wr_L_in),
      .reg_addr_in      (reg_addr_in),
      .reg_data_in      (reg_data_in),
      .reg_src_in       (reg_src_in),

      .reg_req_out      (reg_req_out),
      .reg_ack_out      (reg_ack_out),
      .reg_rd_wr_L_out  (reg_rd_wr_L_out),
      .reg_addr_out     (reg_addr_out),
      .reg_data_out     (reg_data_out),
      .reg_src_out      (reg_src_out),


      .counter_updates  (),
      .counter_decrement(),


      .software_regs    ({cmd,Data_In}),


      .hardware_regs    ({26'h0,packet_count,PL_EN,SW_CTRL,fifo_state,fifo_rd_en,fifo_wr_en,FIFO_WR_addr,FIFO_RD_addr, full, empty, out_rdy, DEPTH, Data_out_DM}),

      .clk              (clk),
      .reset            (rst)
    );







pipeline 	 	#(
				.ADDR_WIDTH(ADDR_WIDTH),
				.DATA_WIDTH(DATA_WIDTH),
				.CTRL_WIDTH(CTRL_WIDTH),
				.Number_of_FIFO(`Number_of_FIFO)
				)
				PL1
				(

				.in_data(in_data),
				.in_ctrl(in_ctrl),
				.out_data(in_data_MC),
				.out_ctrl(in_ctrl_MC),


				.out_rdy(in_rdy_MC),
				.in_wr(in_wr),
				.in_rdy(in_rdy),
				.out_wr(in_wr_MC),
				

				.IorD(),
				.Addr_in(),
				.Data_In(),
				

				.Addr_DM(),
				.Addr_IM(),		
				.Data_out_IM(),
				.Data_out_DM(),
				.full(),
				.empty(),			
				.fifo_busy(),			
				.packet_count(),			
				.FIFO_RD_addr(),
				.FIFO_WR_addr(),
				.fifo_state(),
				.DEPTH(),
				.PL_EN(),
				.SW_CTRL(),
				.fifo_rd_en(),
				.fifo_wr_en(),
				

				.op_fifo_sel(ip_fifo_sel),
				.PL_done(PL1_done),
				

				.clk(clk),
				.rst(rst)
				);
 			
master_ctrl	#(
				.ADDR_WIDTH(ADDR_WIDTH),
				.DATA_WIDTH(DATA_WIDTH),
				.CTRL_WIDTH(CTRL_WIDTH),
				.Number_of_FIFO(`Number_of_FIFO)
			)
			UUT
			(	

				.ip_fifo_sel(ip_fifo_sel),
				.ip_PL_done(PL1_done),
				

				

				.in_rdy(in_rdy_MC),
				.in_wr(in_wr_MC),
				.out_rdy(in_rdy_PLDCF),
				.out_wr(in_wr_PLDCF),
				

				.pckt_count(),
				.state(),
				.full(),
				.nearly_full(),
				.nearly_empty(),
				.empty(),
				.pckt_rd_wr(),
				

				.fifo_data_in(in_data_MC),
				.fifo_data_out(in_data_PLDCF),
				.fifo_ctrl_in(in_ctrl_MC),
				.fifo_ctrl_out(in_ctrl_PLDCF),
				

				.clk(clk),
				.rst(rst)

			);			
			

pipeline_dualCF #(
				.MAX_DEPTH(MAX_DEPTH),
				.ADDR_WIDTH(ADDR_WIDTH),
				.DATA_WIDTH(DATA_WIDTH),
				.CTRL_WIDTH(CTRL_WIDTH),
				.Number_of_FIFO()
				)
				PL2
				(

				.in_data(in_data_PLDCF),
				.in_ctrl(in_ctrl_PLDCF),
				.out_data(out_data),
				.out_ctrl(out_ctrl),


				.out_rdy(out_rdy),
				.in_wr(in_wr_PLDCF),
				.in_rdy(in_rdy_PLDCF),
				.out_wr(out_wr),
				

				.IorD(),
				.Addr_in(),
				.Data_In(),
				

				.Addr_DM(),
				.Addr_IM(),		
				.Data_out_IM(),
				.Data_out_DM(),
				.full(),
				.nearly_full(),
				.nearly_empty(),
				.empty(),			
				.fifo_busy(),			
				.packet_count(),			
				.FIFO_RD_addr(),
				.FIFO_WR_addr(),
				.fifo_state(),
				.DEPTH(),
				.PL_EN(),
				.SW_CTRL(),
				.fifo_rd_en(),
				.fifo_wr_en(),
				

				.Master_reg(),
				

				.clk(clk),
				.rst(rst)
				);
 
 
assign MOD = {cmd[31],cmd[27]};
assign IorD = cmd[29];
assign Addr_in = cmd[8:0];




endmodule