data/full_repos/permissive/193530477/source codes/CNT138T_tb.v
1: b'%Error: Cannot find file containing module: codes,data/full_repos/permissive/193530477\n        ... Looked in:\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.v\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.sv\n             codes,data/full_repos/permissive/193530477\n             codes,data/full_repos/permissive/193530477.v\n             codes,data/full_repos/permissive/193530477.sv\n             obj_dir/codes,data/full_repos/permissive/193530477\n             obj_dir/codes,data/full_repos/permissive/193530477.v\n             obj_dir/codes,data/full_repos/permissive/193530477.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/193530477/source\n%Error: Cannot find file containing module: codes/CNT138T_tb.v\n%Error: Exiting due to 3 error(s)\n'
module CNT138T_tb;

reg clk_4;
reg[3:0] state;
reg[9:0] end_addr;
reg[9:0] start_addr;

wire[9:0] rom_addr;

reg clk;


CNT138T CNT138T_inst (
	.CLK ( clk_4 ),
	.STATE( state ),
	.end_addr( end_addr ),
	.start_addr( start_addr ),
	.CNT8 ( rom_addr )
	);

	initial begin
		clk = 1'b0;
		clk_4 = 1'b0;
		state = 4'b0001;
		start_addr = 10'd0;
		end_addr = 10'd138;
	end
	
	always 
	#5 clk_4 = ~clk_4;
	
	always 
	#100 clk = ~clk;
	

	always @ (posedge clk) begin
		if (state >= 4'd2) begin 
			state <= 4'd1;
			start_addr <= 10'd0;
			end_addr <= 10'd138;
			end 
		else begin
			state <= state + 1'b1;
			start_addr <= 10'd139;
			end_addr <= 10'd335;
			end 
	end 
	
endmodule
module CNT138T_tb;


reg clk_4;
reg[3:0] state;
reg[9:0] end_addr;
reg[9:0] start_addr;

wire[9:0] rom_addr;

reg clk;


CNT138T CNT138T_inst (
	.CLK ( clk_4 ),
	.STATE( state ),
	.end_addr( end_addr ),
	.start_addr( start_addr ),
	.CNT8 ( rom_addr )
	);

	initial begin
		clk = 1'b0;
		clk_4 = 1'b0;
		state = 4'b0001;
		start_addr = 10'd0;
		end_addr = 10'd138;
	end
	
	always 
	#5 clk_4 = ~clk_4;
	
	always 
	#100 clk = ~clk;
	

	always @ (posedge clk) begin
		if (state >= 4'd2) begin 
			state <= 4'd1;
			start_addr <= 10'd0;
			end_addr <= 10'd138;
			end 
		else begin
			state <= state + 1'b1;
			start_addr <= 10'd139;
			end_addr <= 10'd335;
			end 
	end 
	
endmodule