data/full_repos/permissive/148200700/Quartus/ip/random_number_generator/ring_oscillator/ring_oscillator.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/148200700/Quartus/ip/random_number_generator/ring_oscillator/ring_oscillator.sv:25: Logical Operator GENIF expects 1 bit on the If, but If\'s AND generates 32 bits.\n                                                                                                                             : ... In instance ring_oscillator\nif(i & 1) begin\n^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/148200700/Quartus/ip/random_number_generator/ring_oscillator/ring_oscillator.sv:25: Expecting expression to be constant, but variable isn\'t const: \'i\'\n                                                                                                                     : ... In instance ring_oscillator\nif(i & 1) begin\n   ^\n%Error: data/full_repos/permissive/148200700/Quartus/ip/random_number_generator/ring_oscillator/ring_oscillator.sv:25: Generate If condition must evaluate to constant\n                                                                                                                     : ... In instance ring_oscillator\nif(i & 1) begin\n     ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module ring_oscillator
#(
	parameter BIT_WIDTH = 100
)(
	input  wire clk,
	input  wire reset,
	
	input  wire enable_osc,
	
	output reg  clk_out
);

reg enable;
(*keep*) reg [BIT_WIDTH-1 : 0] ring;

genvar i;
generate

for(i = 0; i < (BIT_WIDTH-1); i=i+1) begin : inverter_ring
	always @ * begin
		ring[i+1] = ~ring[i];
	end
end

if(i & 1) begin
	always @ * begin
		ring[0] = (enable) ? (ring[i]) : (1'b0);
	end
end else begin
	always @ * begin
		ring[0] = (enable) ? (~ring[i]) : (1'b0);
	end
end

always @ * begin
	clk_out = ring[i];
end

endgenerate

always @ (posedge clk or posedge reset) begin
	if(reset) begin
		enable <= 1'b0;
	end else begin
		enable <= enable_osc;
	end
end

endmodule
module ring_oscillator
#(
	parameter BIT_WIDTH = 100
)(
	input  wire clk,
	input  wire reset,
	
	input  wire enable_osc,
	
	output reg  clk_out
);


reg enable;
(*keep*) reg [BIT_WIDTH-1 : 0] ring;

genvar i;
generate

for(i = 0; i < (BIT_WIDTH-1); i=i+1) begin : inverter_ring
	always @ * begin
		ring[i+1] = ~ring[i];
	end
end

if(i & 1) begin
	always @ * begin
		ring[0] = (enable) ? (ring[i]) : (1'b0);
	end
end else begin
	always @ * begin
		ring[0] = (enable) ? (~ring[i]) : (1'b0);
	end
end

always @ * begin
	clk_out = ring[i];
end

endgenerate

always @ (posedge clk or posedge reset) begin
	if(reset) begin
		enable <= 1'b0;
	end else begin
		enable <= enable_osc;
	end
end

endmodule