data/full_repos/permissive/141582589/src/ethernet/1G/g_udp.v
'utf-8' codec can't decode byte 0xbd in position 402: invalid start byte
1: b"%Error: data/full_repos/permissive/141582589/src/ethernet/1G/g_udp.v:39: Cannot find file containing module: 'g_ipsend'\ng_ipsend g_ipsend_inst(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141582589/src/ethernet/1G,data/full_repos/permissive/141582589/g_ipsend\n             data/full_repos/permissive/141582589/src/ethernet/1G,data/full_repos/permissive/141582589/g_ipsend.v\n             data/full_repos/permissive/141582589/src/ethernet/1G,data/full_repos/permissive/141582589/g_ipsend.sv\n             g_ipsend\n             g_ipsend.v\n             g_ipsend.sv\n             obj_dir/g_ipsend\n             obj_dir/g_ipsend.v\n             obj_dir/g_ipsend.sv\n%Error: data/full_repos/permissive/141582589/src/ethernet/1G/g_udp.v:58: Cannot find file containing module: 'g_crc'\ng_crc g_crc_inst(\n^~~~~\n%Error: data/full_repos/permissive/141582589/src/ethernet/1G/g_udp.v:67: Cannot find file containing module: 'g_iprecieve'\ng_iprecieve g_iprecieve_inst(\n^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module g_udp(
			input wire           reset_n,
			
			input	 wire           e_rxc,
			input  wire	[7:0]	    e_rxd, 
			input	 wire           e_rxdv,	
			output wire 	       data_o_valid,
			output wire [31:0]    ram_wr_data,
			output wire [15:0]    rx_total_length,
			output wire [15:0]    mydata_num,
			output wire [3:0]     rx_state,
			output wire [15:0]    rx_data_length,
		   output wire [8:0]     ram_wr_addr,
		
			output wire	          e_txen,
			output wire	[7:0]     e_txd,                              
			output wire		       e_txer,
			input  wire [31:0]    ram_rd_data,
		   output      [3:0]     tx_state,
			output      [31:0]    datain_reg,
			input  wire [15:0]    tx_data_length,
			input  wire [15:0]    tx_total_length,
		   output wire [8:0]     ram_rd_addr,
			output wire           data_receive
);


wire	[31:0] crcnext;
wire	[31:0] crc32;
wire	crcreset;
wire	crcen;



g_ipsend g_ipsend_inst(
	.clk(e_rxc),
	.txen(e_txen),
	.txer(e_txer),
	.dataout(e_txd),	
	.reset_n(reset_n),
	.crc(crc32),
	.datain(ram_rd_data),
	.crcen(crcen),
	.crcre(crcreset),
	.crc_valid(crc_valid),
	.tx_state(tx_state),
	.datain_reg(datain_reg),
	.tx_data_length(tx_data_length),
	.tx_total_length(tx_total_length),
	.ram_rd_addr(ram_rd_addr)
	);
	

g_crc	g_crc_inst(
	.Clk(e_rxc),
	.Reset(crcreset),
	.Enable(crcen),
	.Data_in(e_txd),
	.Crc(crc32),
	.CrcNext(crcnext));


g_iprecieve g_iprecieve_inst(
	.clk(e_rxc),
	.datain(e_rxd),
	.e_rxdv(e_rxdv),	
	.clr(reset_n),
	.board_mac(),	
	.pc_mac(),
	.IP_Prtcl(),
	.IP_layer(),
	.pc_IP(),	
	.board_IP(),
	.UDP_layer(),
	.mydata_num(mydata_num),
	.data_o(ram_wr_data),	
	.valid_ip_P(),
	.rx_total_length(rx_total_length),
	.data_o_valid(data_o_valid),                                       
	.rx_state(rx_state),
	.rx_data_length(rx_data_length),
	.ram_wr_addr(ram_wr_addr),
	.data_receive(data_receive)	
	
	
	);
	
endmodule
module g_udp(
			input wire           reset_n,
			
			input	 wire           e_rxc,
			input  wire	[7:0]	    e_rxd, 
			input	 wire           e_rxdv,	
			output wire 	       data_o_valid,
			output wire [31:0]    ram_wr_data,
			output wire [15:0]    rx_total_length,
			output wire [15:0]    mydata_num,
			output wire [3:0]     rx_state,
			output wire [15:0]    rx_data_length,
		   output wire [8:0]     ram_wr_addr,
		
			output wire	          e_txen,
			output wire	[7:0]     e_txd,                              
			output wire		       e_txer,
			input  wire [31:0]    ram_rd_data,
		   output      [3:0]     tx_state,
			output      [31:0]    datain_reg,
			input  wire [15:0]    tx_data_length,
			input  wire [15:0]    tx_total_length,
		   output wire [8:0]     ram_rd_addr,
			output wire           data_receive
);



wire	[31:0] crcnext;
wire	[31:0] crc32;
wire	crcreset;
wire	crcen;



g_ipsend g_ipsend_inst(
	.clk(e_rxc),
	.txen(e_txen),
	.txer(e_txer),
	.dataout(e_txd),	
	.reset_n(reset_n),
	.crc(crc32),
	.datain(ram_rd_data),
	.crcen(crcen),
	.crcre(crcreset),
	.crc_valid(crc_valid),
	.tx_state(tx_state),
	.datain_reg(datain_reg),
	.tx_data_length(tx_data_length),
	.tx_total_length(tx_total_length),
	.ram_rd_addr(ram_rd_addr)
	);
	

g_crc	g_crc_inst(
	.Clk(e_rxc),
	.Reset(crcreset),
	.Enable(crcen),
	.Data_in(e_txd),
	.Crc(crc32),
	.CrcNext(crcnext));


g_iprecieve g_iprecieve_inst(
	.clk(e_rxc),
	.datain(e_rxd),
	.e_rxdv(e_rxdv),	
	.clr(reset_n),
	.board_mac(),	
	.pc_mac(),
	.IP_Prtcl(),
	.IP_layer(),
	.pc_IP(),	
	.board_IP(),
	.UDP_layer(),
	.mydata_num(mydata_num),
	.data_o(ram_wr_data),	
	.valid_ip_P(),
	.rx_total_length(rx_total_length),
	.data_o_valid(data_o_valid),                                       
	.rx_state(rx_state),
	.rx_data_length(rx_data_length),
	.ram_wr_addr(ram_wr_addr),
	.data_receive(data_receive)	
	
	
	);
	
endmodule