data/full_repos/permissive/211878730/atlys/practice/register4_async_reset_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/register4_async_reset_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/register4_async_reset_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/register4_async_reset_test.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/register4_async_reset_test.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/register4_async_reset_test.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/register4_async_reset_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/register4_async_reset_test.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/register4_async_reset_test.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/211878730/atlys/practice/register4_async_reset_test.v:14: Cannot find file containing module: \'register4_async_reset\'\n register4_async_reset uut (\n ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/register4_async_reset\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/register4_async_reset.v\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/register4_async_reset.sv\n             register4_async_reset\n             register4_async_reset.v\n             register4_async_reset.sv\n             obj_dir/register4_async_reset\n             obj_dir/register4_async_reset.v\n             obj_dir/register4_async_reset.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register4_async_reset_test;


	reg clk;
	reg reset;
	reg [3:0] data;


	wire [3:0] q;


	register4_async_reset uut (
		.clk(clk), 
		.reset(reset), 
		.data(data), 
		.q(q)
	);

	initial begin

		clk = 0;
		reset = 1;
		data = 0;


		#1;
        

		clk = 1;
		reset = 1;
		data = 4'b1010;
		#1;

		clk = 0;
		reset = 1;
		data = 4'b1010;
		#1;

		clk = 1;
		reset = 1;
		data = 4'b1010;
		#1;

		clk = 0;
		reset = 0;
		data = 4'b1010;
		#1;

		clk = 1;
		reset = 0;
		data = 4'b1010;
		#1;

		clk = 0;
		reset = 1;
		data = 4'b1010;
		#1;

		clk = 1;
		reset = 1;
		data = 4'b1010;
		#1;
	end
      
endmodule
module register4_async_reset_test;



	reg clk;
	reg reset;
	reg [3:0] data;


	wire [3:0] q;


	register4_async_reset uut (
		.clk(clk), 
		.reset(reset), 
		.data(data), 
		.q(q)
	);

	initial begin

		clk = 0;
		reset = 1;
		data = 0;


		#1;
        

		clk = 1;
		reset = 1;
		data = 4'b1010;
		#1;

		clk = 0;
		reset = 1;
		data = 4'b1010;
		#1;

		clk = 1;
		reset = 1;
		data = 4'b1010;
		#1;

		clk = 0;
		reset = 0;
		data = 4'b1010;
		#1;

		clk = 1;
		reset = 0;
		data = 4'b1010;
		#1;

		clk = 0;
		reset = 1;
		data = 4'b1010;
		#1;

		clk = 1;
		reset = 1;
		data = 4'b1010;
		#1;
	end
      
endmodule