data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/xor_gate.v
data/verilator_xmls/9c1b2035-0136-4655-a15a-bb078a3b2e2d.xml
module xor_gate(input wire x, input wire y, output wire z);




assign z = x ^ y;

endmodule
module xor_gate(input wire x, input wire y, output wire z);





assign z = x ^ y;

endmodule