data/full_repos/permissive/125927162/7SEG/7seg.v
data/verilator_xmls/0046561a-43d9-4a4b-83a7-b309f5ffd5c3.xml
module sseg (in, invert, out_q, oe);
   input [3:0] in;
   input       oe;
	input invert;
   output wire [6:0] out_q;
   reg [6:0] 	     out_d;
   









   always @ (in) begin
     case (in)
       0: out_d = 7'b0111111;
       1: out_d = 7'b0000110;
       2: out_d = 7'b1011011;
       3: out_d = 7'b1001111;
       4: out_d = 7'b1100110;
       5: out_d = 7'b1101101;
       6: out_d = 7'b1111101;
       7: out_d = 7'b0000111;
       8: out_d = 7'b1111111;
       9: out_d = 7'b1101111;
       10: out_d = 7'b1110111;
       11: out_d = 7'b1111100;
       12: out_d = 7'b0111001;
       13: out_d = 7'b1011110;
       14: out_d = 7'b1111011;
       15: out_d = 7'b1110001;
     endcase
   end

   assign out_q = oe? (invert? ~out_d : out_d) : 7'bZZZZZZZ;
endmodule
module sseg (in, invert, out_q, oe);

   input [3:0] in;
   input       oe;
	input invert;
   output wire [6:0] out_q;
   reg [6:0] 	     out_d;
   









   always @ (in) begin
     case (in)
       0: out_d = 7'b0111111;
       1: out_d = 7'b0000110;
       2: out_d = 7'b1011011;
       3: out_d = 7'b1001111;
       4: out_d = 7'b1100110;
       5: out_d = 7'b1101101;
       6: out_d = 7'b1111101;
       7: out_d = 7'b0000111;
       8: out_d = 7'b1111111;
       9: out_d = 7'b1101111;
       10: out_d = 7'b1110111;
       11: out_d = 7'b1111100;
       12: out_d = 7'b0111001;
       13: out_d = 7'b1011110;
       14: out_d = 7'b1111011;
       15: out_d = 7'b1110001;
     endcase
   end

   assign out_q = oe? (invert? ~out_d : out_d) : 7'bZZZZZZZ;
endmodule