data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/mux-4x1/mux-4x1-tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/mux-4x1/mux-4x1-tb.v:22: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("mux-4x1-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/mux-4x1/mux-4x1-tb.v:23: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, mux_4x1_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/multiplexers-and-demultiplexers/mux-4x1/mux-4x1-tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_4x1_tb;


reg     A, B, C, D;
reg     [1:0] SEL;
wire    Y;
integer i;


mux_4x1 uut(
    .a(A), .b(B), .c(C), .d(D),
    .sel(SEL),
    .y(Y)
);


initial begin
    $dumpfile("mux-4x1-tb.vcd");
    $dumpvars(0, mux_4x1_tb);
end


initial begin
    $display("test start");
    A = 0; B = 0; C = 0; D = 0;
    SEL = 2'b00;

    for (i = 0; i < 64; i = i + 1) begin
        {SEL, D, C, B, A} = i;
        #10;
    end
    
    $display("test complete");
    $finish;
end

endmodule
module mux_4x1_tb;



reg     A, B, C, D;
reg     [1:0] SEL;
wire    Y;
integer i;


mux_4x1 uut(
    .a(A), .b(B), .c(C), .d(D),
    .sel(SEL),
    .y(Y)
);


initial begin
    $dumpfile("mux-4x1-tb.vcd");
    $dumpvars(0, mux_4x1_tb);
end


initial begin
    $display("test start");
    A = 0; B = 0; C = 0; D = 0;
    SEL = 2'b00;

    for (i = 0; i < 64; i = i + 1) begin
        {SEL, D, C, B, A} = i;
        #10;
    end
    
    $display("test complete");
    $finish;
end

endmodule