data/full_repos/permissive/112219256/nextpc_gen.v
1: b"%Error: data/full_repos/permissive/112219256/nextpc_gen.v:63: Cannot find file containing module: 'MUX_4_32'\n    MUX_4_32 PCS_MUX(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.v\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.sv\n             MUX_4_32\n             MUX_4_32.v\n             MUX_4_32.sv\n             obj_dir/MUX_4_32\n             obj_dir/MUX_4_32.v\n             obj_dir/MUX_4_32.sv\n%Error: Exiting due to 1 error(s)\n"
module nextpc_gen(
    input              clk            ,
    input              rst            ,
    input              PCWrite        ,
    input              JSrc           ,
    input              eret           ,   
    input              ex_int_handle  ,            
    input       [ 1:0] PCSrc          ,    
    input       [31:0] JR_target      ,        
    input       [31:0] J_target       ,       
    input       [31:0] Br_addr        ,      
    input       [31:0] epc            , 

    output reg         PC_AdEL        ,  
    output reg  [31:0] PC             ,
    output reg  [31:0] PC_buffer      ,
    input              PC_refresh          

  );
    parameter reset_addr  = 32'hbfc00000;
    parameter except_addr = 32'hbfc00380;
    
    reg [31:0] PC_next;
        
    wire [31:0] Jump_addr, inst_addr, PC_mux;

    assign Jump_addr = JSrc ? JR_target : J_target;

    assign inst_addr = ex_int_handle  ? except_addr : 
                                eret  ? epc         : PC_mux;

    always @(posedge clk) begin
        if (rst) begin
            PC          <= reset_addr;
            PC_next     <= reset_addr + 32'd4;
            PC_buffer   <= 'd0;
            PC_AdEL     <= 'd0;
        end
        else if (PC_refresh) begin
            PC          <= inst_addr;
            PC_next     <= inst_addr + 32'd4;
            PC_buffer   <= PC;
            PC_AdEL     <= |PC[1:0] ? 1'b1 : 1'b0;
        end
        else begin
            PC_next     <= PC_next;
            PC          <= PC;
            PC_buffer   <= PC_buffer;
            PC_AdEL     <= PC_AdEL  ;
        end
    end
     
    MUX_4_32 PCS_MUX(
        .Src1   (    PC_next),
        .Src2   (  Jump_addr),
        .Src3   (    Br_addr),
        .Src4   (      32'd0),
        .op     (      PCSrc),
        .Result (     PC_mux)
    ); 

endmodule
module nextpc_gen(
    input              clk            ,
    input              rst            ,
    input              PCWrite        ,
    input              JSrc           ,
    input              eret           ,   
    input              ex_int_handle  ,            
    input       [ 1:0] PCSrc          ,    
    input       [31:0] JR_target      ,        
    input       [31:0] J_target       ,       
    input       [31:0] Br_addr        ,      
    input       [31:0] epc            , 

    output reg         PC_AdEL        ,  
    output reg  [31:0] PC             ,
    output reg  [31:0] PC_buffer      ,
    input              PC_refresh          

  );

    parameter reset_addr  = 32'hbfc00000;
    parameter except_addr = 32'hbfc00380;
    
    reg [31:0] PC_next;
        
    wire [31:0] Jump_addr, inst_addr, PC_mux;

    assign Jump_addr = JSrc ? JR_target : J_target;

    assign inst_addr = ex_int_handle  ? except_addr : 
                                eret  ? epc         : PC_mux;

    always @(posedge clk) begin
        if (rst) begin
            PC          <= reset_addr;
            PC_next     <= reset_addr + 32'd4;
            PC_buffer   <= 'd0;
            PC_AdEL     <= 'd0;
        end
        else if (PC_refresh) begin
            PC          <= inst_addr;
            PC_next     <= inst_addr + 32'd4;
            PC_buffer   <= PC;
            PC_AdEL     <= |PC[1:0] ? 1'b1 : 1'b0;
        end
        else begin
            PC_next     <= PC_next;
            PC          <= PC;
            PC_buffer   <= PC_buffer;
            PC_AdEL     <= PC_AdEL  ;
        end
    end
     
    MUX_4_32 PCS_MUX(
        .Src1   (    PC_next),
        .Src2   (  Jump_addr),
        .Src3   (    Br_addr),
        .Src4   (      32'd0),
        .op     (      PCSrc),
        .Result (     PC_mux)
    ); 

endmodule