data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_common_unpack_data.v
1: b"%Error: data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules/alt_vipvfr131_common_unpack_data.v:54: Cannot find file containing module: 'alt_vipvfr131_common_pulling_width_adapter'\nalt_vipvfr131_common_pulling_width_adapter\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_common_pulling_width_adapter\n             data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_common_pulling_width_adapter.v\n             data/full_repos/permissive/116866011/BSP/c5soc/hardware/de10_nano_sharedonly_hdmi/system/synthesis/submodules,data/full_repos/permissive/116866011/alt_vipvfr131_common_pulling_width_adapter.sv\n             alt_vipvfr131_common_pulling_width_adapter\n             alt_vipvfr131_common_pulling_width_adapter.v\n             alt_vipvfr131_common_pulling_width_adapter.sv\n             obj_dir/alt_vipvfr131_common_pulling_width_adapter\n             obj_dir/alt_vipvfr131_common_pulling_width_adapter.v\n             obj_dir/alt_vipvfr131_common_pulling_width_adapter.sv\n%Error: Exiting due to 1 error(s)\n"
module alt_vipvfr131_common_unpack_data

	(	clock,
		reset,
		

	  data_in,
	  read,
	  stall_in,
		

	  data_out,
	  write,
	  stall_out,
	  

	  clear);


parameter DATA_WIDTH_IN = 128;
parameter DATA_WIDTH_OUT = 24;

input		clock;
input		reset;
	  

input		[DATA_WIDTH_IN - 1 : 0] data_in;

output  read;
input		stall_in;
		

input		stall_out;
output	reg write;
output	[DATA_WIDTH_OUT - 1:0] data_out;

input		clear;

wire need_input;
wire ena;

assign ena = ~stall_in;


assign read = need_input;


alt_vipvfr131_common_pulling_width_adapter
	#(.IN_WIDTH (DATA_WIDTH_IN),
    .OUT_WIDTH (DATA_WIDTH_OUT)
	)
fu_inst
  ( .clock (clock),
    .reset (reset),
    .input_data (data_in),
    .need_input (need_input),
    .output_data (data_out),
    .pull (1'b1),
    .pull_en (~stall_out),
    .discard (1'b1),
    .discard_en (clear),
    .ena (ena)
  );

always @(posedge clock or posedge reset)
	if (reset) begin
		write <= 1'b0;
	end
	else if (~stall_out) begin
		write <= ena;
	end
		
endmodule
module alt_vipvfr131_common_unpack_data

	(	clock,
		reset,
		

	  data_in,
	  read,
	  stall_in,
		

	  data_out,
	  write,
	  stall_out,
	  

	  clear);



parameter DATA_WIDTH_IN = 128;
parameter DATA_WIDTH_OUT = 24;

input		clock;
input		reset;
	  

input		[DATA_WIDTH_IN - 1 : 0] data_in;

output  read;
input		stall_in;
		

input		stall_out;
output	reg write;
output	[DATA_WIDTH_OUT - 1:0] data_out;

input		clear;

wire need_input;
wire ena;

assign ena = ~stall_in;


assign read = need_input;


alt_vipvfr131_common_pulling_width_adapter
	#(.IN_WIDTH (DATA_WIDTH_IN),
    .OUT_WIDTH (DATA_WIDTH_OUT)
	)
fu_inst
  ( .clock (clock),
    .reset (reset),
    .input_data (data_in),
    .need_input (need_input),
    .output_data (data_out),
    .pull (1'b1),
    .pull_en (~stall_out),
    .discard (1'b1),
    .discard_en (clear),
    .ena (ena)
  );

always @(posedge clock or posedge reset)
	if (reset) begin
		write <= 1'b0;
	end
	else if (~stall_out) begin
		write <= ena;
	end
		
endmodule