data/full_repos/permissive/207610706/src/host_ctrl.v
 line:345: before: "("
1: b'%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:1: Cannot find include file: ./uart/uart_defines.v\n`include "./uart/uart_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207610706/src,data/full_repos/permissive/207610706/./uart/uart_defines.v\n             data/full_repos/permissive/207610706/src,data/full_repos/permissive/207610706/./uart/uart_defines.v.v\n             data/full_repos/permissive/207610706/src,data/full_repos/permissive/207610706/./uart/uart_defines.v.sv\n             ./uart/uart_defines.v\n             ./uart/uart_defines.v.v\n             ./uart/uart_defines.v.sv\n             obj_dir/./uart/uart_defines.v\n             obj_dir/./uart/uart_defines.v.v\n             obj_dir/./uart/uart_defines.v.sv\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:2: Cannot find include file: wrapper_defines.vh\n`include "wrapper_defines.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:3: Cannot find include file: aeses_defines.vh\n`include "aeses_defines.vh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:272: Define or directive not defined: \'`KEY_128\'\n  host_aes_key_mode_o             <= `KEY_128;\n                                     ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:272: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  host_aes_key_mode_o             <= `KEY_128;\n                                             ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:389: Define or directive not defined: \'`UART_REG_LC\'\n    set_uart_op(WRITE_OP,`UART_REG_LC,4\'b1,8\'b10000011);\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:402: Define or directive not defined: \'`UART_REG_DL1\'\n    set_uart_op(WRITE_OP,`UART_REG_DL1,4\'d1,`UART_CLK_DIV_DEF);      \n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:402: Define or directive not defined: \'`UART_CLK_DIV_DEF\'\n    set_uart_op(WRITE_OP,`UART_REG_DL1,4\'d1,`UART_CLK_DIV_DEF);      \n                                            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:415: Define or directive not defined: \'`UART_REG_LC\'\n    set_uart_op(WRITE_OP,`UART_REG_LC,4\'b1,8\'b00000011);\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:445: Define or directive not defined: \'`AESES_RESET_BIT\'\n                    if(data[`AESES_RESET_BIT] == 1\'b1)  \n                            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:445: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                    if(data[`AESES_RESET_BIT] == 1\'b1)  \n                                            ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:451: Define or directive not defined: \'`AESES_KEY_256_BIT\'\n                        if(data[`AESES_KEY_256_BIT] == 1\'b1)\n                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:451: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                        if(data[`AESES_KEY_256_BIT] == 1\'b1)\n                                                  ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:453: Define or directive not defined: \'`KEY_256\'\n                            host_aes_key_mode_next = `KEY_256;\n                                                     ^~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:455: Define or directive not defined: \'`AESES_KEY_FIELD\'\n                            host_aes_key_mode_next = data[`AESES_KEY_FIELD];\n                                                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:457: Define or directive not defined: \'`AESES_EN_BIT\'\n                    else if(data[`AESES_EN_BIT] == 1\'b1)\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:463: Define or directive not defined: \'`AESES_ENC_DEC\'\n                        host_aes_enc_decneg_next = data[`AESES_ENC_DEC];\n                                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:463: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                        host_aes_enc_decneg_next = data[`AESES_ENC_DEC];\n                                                                      ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:470: Define or directive not defined: \'`UART_REG_LS\'\n                set_uart_op(READ_OP,`UART_REG_LS,1,0);\n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:471: Define or directive not defined: \'`UART_LS_DR\'\n                if(wb_ack_uart_i && wb_dat_uart_i[`UART_LS_DR]==1)  \n                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:471: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                if(wb_ack_uart_i && wb_dat_uart_i[`UART_LS_DR]==1)  \n                                                             ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:478: Unsupported or unknown PLI call: $strobe\n                    $strobe("@%0t: Host0 - UART_FIFO_RX_BUF_HAS_BYTE",$time);\n                    ^~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:483: Define or directive not defined: \'`UART_REG_RB\'\n                set_uart_op(READ_OP,`UART_REG_RB,1,0);\n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:489: syntax error, unexpected \'=\', expecting IDENTIFIER\n                        ss_next = ss_after_read;\n                                ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:494: syntax error, unexpected \'=\', expecting IDENTIFIER\n                        ss_next = CHECK_UART_RXFIFO;\n                                ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:499: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    wb_cyc_uart_o_next    = 0;\n                                          ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:503: Unsupported or unknown PLI call: $strobe\n                    $strobe("@%0t: Host0 - END_READ_UART",$time);\n                    ^~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:507: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    ss_next = READ_BYTE_UART;\n                            ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:508: Unsupported or unknown PLI call: $strobe\n                    $strobe("@%0t: Host0 - TRY_READ_UART",$time);\n                    ^~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:515: Define or directive not defined: \'`UART_REG_LS\'\n    set_uart_op(READ_OP,`UART_REG_LS,1,0);\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:516: Define or directive not defined: \'`UART_LS_TE\'\n    if(wb_ack_uart_i && wb_dat_uart_i[`UART_LS_TE]==1)\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:516: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    if(wb_ack_uart_i && wb_dat_uart_i[`UART_LS_TE]==1)\n                                                 ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:524: Unsupported or unknown PLI call: $strobe\n     $strobe("@%0t: Host0 - UART_FIFO_TX_BUF_EMPTY",$time);\n     ^~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:529: Define or directive not defined: \'`UART_REG_TR\'\n    set_uart_op(WRITE_OP,`UART_REG_TR,1, enc_r[ (UART_DW * (15-cnt_recvbyte)) +: 8] );\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:534: syntax error, unexpected \'=\', expecting IDENTIFIER\n      ss_next = GET_AESES_CONTROL_BYTE;\n              ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:539: syntax error, unexpected \'=\', expecting IDENTIFIER\n      ss_next = CHECK_UART_TXFIFO;\n              ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:544: syntax error, unexpected \'=\', expecting IDENTIFIER\n     wb_cyc_uart_o_next = 0;\n                        ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:547: Unsupported or unknown PLI call: $strobe\n     $strobe("@%0t: Host0 - END_WRITE_UART",$time);\n     ^~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:551: syntax error, unexpected \'=\', expecting IDENTIFIER\n     ss_next = WRITE_BYTE_UART;\n             ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:552: Unsupported or unknown PLI call: $strobe\n     $strobe("@%0t: Host0 - TRY_WRITE_UART",$time);\n     ^~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:565: Unsupported or unknown PLI call: $strobe\n     $strobe("@%0t: Host0 - AES_CORE is ready",$time);\n     ^~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:573: Unsupported or unknown PLI call: $strobe\n     $strobe("@%0t: Host0 - key schedule STARTED",$time);\n     ^~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:581: Unsupported or unknown PLI call: $strobe\n     $strobe("@%0t: Host0 - key scheduled DONE, waiting for blocks to encrypt/decrypt",$time);\n     ^~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:591: syntax error, unexpected \'=\', expecting IDENTIFIER\n     ss_next = TRIGGER_DELAY_PRE_COMP;\n             ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:592: Unsupported or unknown PLI call: $strobe\n     $strobe("@%0t: Host0 - AES_CORE is ready",$time);\n     ^~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:617: syntax error, unexpected \'=\', expecting IDENTIFIER\n     ss_next = AES_WAIT_COMP_DONE;\n             ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:618: Unsupported or unknown PLI call: $strobe\n     $strobe("@%0t: Host0 - AES computation STARTED",$time);\n     ^~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:627: syntax error, unexpected \'=\', expecting IDENTIFIER\n     enc_r_next = aes_host_result_i;\n                ^\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:630: Unsupported or unknown PLI call: $strobe\n     $strobe("@%0t: Host0 - AES computation DONE with output: %h",$time,aes_host_result_i);\n     ^~~~~~~\n%Error: data/full_repos/permissive/207610706/src/host_ctrl.v:670: syntax error, unexpected \'=\', expecting IDENTIFIER\n    reuse_cnt_inc = 1\'b1;\n                  ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module host_ctrl(
					wb_clk,wb_rst,

					wb_adr_uart_o,
					wb_dat_uart_o,
					wb_cyc_uart_o,
					wb_stb_uart_o,
					wb_sel_uart_o,
					wb_we_uart_o,
					wb_dat_uart_i,
					wb_ack_uart_i,

					host_aes_key_o,
					host_aes_blk_o,
					host_aes_key_mode_o,
					host_aes_enable_key_schedule_o,
					host_aes_enable_op_o,
					host_aes_enc_decneg_o,
					aes_host_result_i,
					aes_host_result_valid_i,
					aes_host_ready_i,

					trigger_o,
					recv_byte_led_o
			);

parameter UART_AW	=	3;
parameter UART_DW	=	8;
parameter CNT_BIT	=	16;
parameter NUM_BYTE_BLK	=	16;
parameter NUM_BYTE_KEY  =   32;

parameter AES_KW = 256;
parameter AES_DW = 128;

parameter TRIGGER_BIT_W 		= 18;
parameter TRIGGER_MAX			= 100000;
parameter AES_PRE_POST_DELAY 	= 20;

parameter NUM_CNT_REUSE_TIMES 	= 0;
parameter NUM_CNT_REUSE_BIT 	= 16;




input wb_clk;
input wb_rst;




output	reg [UART_AW-1:0]	wb_adr_uart_o;
output	reg [UART_DW-1:0]	wb_dat_uart_o;
output 	reg					wb_cyc_uart_o;
output 	reg					wb_stb_uart_o;
output	reg [3:0]			wb_sel_uart_o;
output	reg 				wb_we_uart_o;

input	[UART_DW-1:0]	wb_dat_uart_i;
input 					wb_ack_uart_i;



output      [0:AES_KW-1]    host_aes_key_o;
output      [0:AES_DW-1]    host_aes_blk_o;
output  reg [1:0]           host_aes_key_mode_o;
output  reg                 host_aes_enc_decneg_o;
output  reg                 host_aes_enable_key_schedule_o;
output  reg                 host_aes_enable_op_o;

input		[0:AES_DW-1]	aes_host_result_i;
input	 					aes_host_result_valid_i;
input 						aes_host_ready_i;


output [7:0]	recv_byte_led_o;
output reg		trigger_o;


function integer clog2(input integer value);
begin
		if(value==0)
			clog2=0;
		else
		begin
			while(value>0)
			begin
				clog2=clog2+1;
				value=value>>1;
			end
		end
end
endfunction


localparam [4:0]	CONFIGURE					= 5'd0,
					WE_UART_DIV_REG				= 5'd1,
					SET_UART_DIV_REG			= 5'd2,
					END_CONFIGURE				= 5'd3,

					GET_AESES_CONTROL_BYTE		= 5'd4,
					PARSE_AESES_CONTROL_BYTE	= 5'd5,

					CHECK_UART_RXFIFO			= 5'd6,
					READ_BYTE_UART         		= 5'd7,
					
					CHECK_UART_TXFIFO			= 5'd8,
					WRITE_BYTE_UART    			= 5'd9,

					AES_WAIT_READY_INIT			= 5'd18,
					AES_INIT_KEY_1				= 5'd19,
					AES_INIT_KEY_2				= 5'd20,

					AES_WAIT_READY_COMP			= 5'd21,
					AES_START_COMPUTATION		= 5'd22,
					AES_WAIT_COMP_DONE			= 5'd23,

					TRIGGER_DELAY				= 5'd24,

					TRIGGER_DELAY_PRE_COMP		= 5'd25,
					TRIGGER_DELAY_POST_COMP		= 5'd26,

					PREPARE_REUSE_DATA			= 5'd27;



reg [4:0] ss, ss_next;
reg [4:0] ss_after_read, ss_after_read_next;

reg trigger_o_next;
reg [TRIGGER_BIT_W-1:0] trigger_cnt, trigger_cnt_next;

reg trigger_cnt_inc;
reg trigger_cnt_rst;
reg trigger_cnt_we;


reg [TRIGGER_BIT_W-1:0] cnt_aes_delay, cnt_aes_delay_next;

reg cnt_aes_delay_inc;
reg cnt_aes_delay_rst;
reg cnt_aes_delay_we;

reg [NUM_CNT_REUSE_BIT-1:0] reuse_cnt,	reuse_cnt_next;
reg reuse_cnt_we;
reg reuse_cnt_rst;
reg reuse_cnt_inc;





reg [UART_DW-1:0] key_r 	[0:NUM_BYTE_KEY-1];
reg key_r_we_next;
wire [0:255] key_wire;


reg [UART_DW-1:0] plain_r 	[0:NUM_BYTE_BLK-1];
reg plain_r_we_next;
reg plainFlush_r_we_next;
wire [0:127] plain_wire;

reg [0:127] enc_r, enc_r_next;

reg [UART_DW-1:0] 		data, data_next;

localparam CTR_WIDTH = $clog2(NUM_BYTE_KEY);

reg [CTR_WIDTH:0] cnt_recvbyte, cnt_recvbyte_next, cnt_recvbyte_rst_value;
reg	cnt_recvbyte_dec;
reg	cnt_recvbyte_rst;
reg	cnt_recvbyte_we;


reg [UART_AW-1:0]	wb_adr_uart_o_next;
reg [UART_DW-1:0]	wb_dat_uart_o_next;
reg					wb_cyc_uart_o_next;
reg					wb_stb_uart_o_next;
reg [3:0]			wb_sel_uart_o_next;
reg 				wb_we_uart_o_next;


reg [1:0]   host_aes_key_mode_next;
reg         host_aes_enc_decneg_next;
reg         host_aes_enable_key_schedule_next;
reg         host_aes_enable_op_next;







localparam 	READ_OP		= 1'b0;
localparam	WRITE_OP	= 1'b1;

task set_uart_op;
input rw;
input [UART_AW-1:0] addr;
input [3:0] sel;
input [UART_DW-1:0] wdata;
begin
	wb_cyc_uart_o_next	= 1;
	wb_stb_uart_o_next	= 1;
	wb_adr_uart_o_next	= addr;
	wb_sel_uart_o_next	= sel;
	wb_we_uart_o_next	= rw;
	wb_dat_uart_o_next	= wdata;
end
endtask



assign host_aes_blk_o 	= {
                        plain_r[15],	plain_r[14], 	plain_r[13], 	plain_r[12],
						plain_r[11],	plain_r[10],	plain_r[9],		plain_r[8],
						plain_r[7],		plain_r[6],		plain_r[5],		plain_r[4],
						plain_r[3],		plain_r[2],		plain_r[1], 	plain_r[0] };

assign host_aes_key_o 	= {
                        key_r[31],		key_r[30],		key_r[29],		key_r[28],
                        key_r[27],		key_r[26],		key_r[25],		key_r[24],
                        key_r[23],		key_r[22],		key_r[21],		key_r[20],
                        key_r[19],		key_r[18],		key_r[17],		key_r[16],
                        key_r[15],		key_r[14],		key_r[13],		key_r[12],
						key_r[11],		key_r[10],		key_r[9],		key_r[8],
						key_r[7],		key_r[6],		key_r[5],		key_r[4],
						key_r[3],		key_r[2],		key_r[1], 		key_r[0] };

assign recv_byte_led_o[4:0] = ss;
assign recv_byte_led_o[5] = host_aes_enc_decneg_o;
assign recv_byte_led_o[7:6] = host_aes_key_mode_o;





always@(posedge wb_clk, posedge wb_rst)
begin:seq_host
	integer i;
	if(wb_rst)
	begin
		ss 				<=	CONFIGURE;
		ss_after_read   <=  GET_AESES_CONTROL_BYTE;
		trigger_o 		<=	0;
		trigger_cnt		<=	0;
		cnt_aes_delay	<=	0;
		reuse_cnt		<=	0;

		wb_adr_uart_o	<=	{UART_AW{1'b0}};
		wb_cyc_uart_o	<=	0;
		wb_stb_uart_o	<=	0;
		wb_sel_uart_o	<=	0;
		wb_dat_uart_o	<=	0;
		wb_we_uart_o	<=	0;
		data			<=	0;

		for(i=0;i<NUM_BYTE_KEY;i=i+1)
			key_r[i]	<=	0;

		for(i=0;i<NUM_BYTE_BLK;i=i+1)
			plain_r[i]	<=	0;

		cnt_recvbyte	<=	0;
		enc_r			<=	0;


		host_aes_key_mode_o             <= `KEY_128;
        host_aes_enc_decneg_o           <= 1'b1;
        host_aes_enable_key_schedule_o  <= 1'b0;
        host_aes_enable_op_o            <= 1'b0;
	end
	else
	begin
		ss				<=	ss_next;
		trigger_o 		<=	trigger_o_next;

		if(trigger_cnt_we)
			trigger_cnt		<=	trigger_cnt_next;

		if(cnt_aes_delay_we)
			cnt_aes_delay	<=	cnt_aes_delay_next;
		if(reuse_cnt_we)
			reuse_cnt		<=	reuse_cnt_next;


		wb_adr_uart_o	<= wb_adr_uart_o_next;
		wb_cyc_uart_o	<= wb_cyc_uart_o_next;
		wb_stb_uart_o	<= wb_stb_uart_o_next;
		wb_sel_uart_o	<= wb_sel_uart_o_next;
		wb_dat_uart_o	<= wb_dat_uart_o_next;
		wb_we_uart_o	<= wb_we_uart_o_next;
		data			<= data_next;


		if(cnt_recvbyte_we)
			cnt_recvbyte		<=	cnt_recvbyte_next;

		if(key_r_we_next)
			key_r[cnt_recvbyte]	<=	data_next;

		if(plain_r_we_next)
		begin
			if(plainFlush_r_we_next)
			begin
				for(i=0; i<NUM_BYTE_BLK; i=i+1)
				begin
					plain_r[NUM_BYTE_BLK-1-i] <= enc_r[(UART_DW * (i))+:8];

				end
			end
			else
				plain_r[cnt_recvbyte]	<=	data_next;
		end
		enc_r		<= enc_r_next;


		host_aes_key_mode_o             <= host_aes_key_mode_next;
        host_aes_enc_decneg_o           <= host_aes_enc_decneg_next;
        host_aes_enable_key_schedule_o  <= host_aes_enable_key_schedule_next;
        host_aes_enable_op_o            <= host_aes_enable_op_next;
	

	    ss_after_read       <=  ss_after_read_next;
	end
end






always@(*)
begin

	ss_next 			= ss;
	trigger_o_next		= trigger_o;


	wb_adr_uart_o_next	= wb_adr_uart_o;
	wb_cyc_uart_o_next	= wb_cyc_uart_o;
	wb_stb_uart_o_next	= wb_stb_uart_o;
	wb_sel_uart_o_next	= wb_sel_uart_o;
	wb_we_uart_o_next	= wb_we_uart_o;
	wb_dat_uart_o_next	= wb_dat_uart_o;
	data_next			= data;


	plainFlush_r_we_next= 0;
	enc_r_next			= enc_r;


	host_aes_key_mode_next = host_aes_key_mode_o;
    host_aes_enc_decneg_next = host_aes_enc_decneg_o;
    host_aes_enable_key_schedule_next = 1'b0;
    host_aes_enable_op_next = 1'b0;

	trigger_cnt_inc = 0;
    trigger_cnt_rst = 0;

	cnt_recvbyte_dec = 0;
	cnt_recvbyte_rst = 0;

	reuse_cnt_inc = 0;
	reuse_cnt_rst = 0;

	cnt_aes_delay_inc=0;
	cnt_aes_delay_rst=0;
	

	ss_after_read_next = ss_after_read;
	cnt_recvbyte_rst_value = 0;

	case(ss)

		CONFIGURE:
			begin
			if(wb_rst==0)
				ss_next = WE_UART_DIV_REG;
			else
				ss_next = CONFIGURE;
			end
		WE_UART_DIV_REG:
			begin
				set_uart_op(WRITE_OP,`UART_REG_LC,4'b1,8'b10000011);
				if(wb_ack_uart_i)
				begin
					ss_next = SET_UART_DIV_REG;
					wb_cyc_uart_o_next	= 0;
					wb_stb_uart_o_next	= 0;
					wb_we_uart_o_next	= 0;
				end
				else
					ss_next = WE_UART_DIV_REG;
			end
		SET_UART_DIV_REG:
			begin
				set_uart_op(WRITE_OP,`UART_REG_DL1,4'd1,`UART_CLK_DIV_DEF);
				if(wb_ack_uart_i)
				begin
					ss_next = END_CONFIGURE;
					wb_cyc_uart_o_next	= 0;
					wb_stb_uart_o_next	= 0;
					wb_we_uart_o_next	= 0;
					end
				else
					ss_next = SET_UART_DIV_REG;
			end
		END_CONFIGURE:
			begin
				set_uart_op(WRITE_OP,`UART_REG_LC,4'b1,8'b00000011);
				if(wb_ack_uart_i)
				begin
					ss_next = GET_AESES_CONTROL_BYTE;

					wb_cyc_uart_o_next	= 0;
					wb_stb_uart_o_next	= 0;
					wb_we_uart_o_next	= 0;
					end
				else
					ss_next = END_CONFIGURE;
			end
			


        GET_AESES_CONTROL_BYTE:
            begin
                    ss_next = CHECK_UART_RXFIFO;
                    cnt_recvbyte_rst = 1'b1;
                    cnt_recvbyte_rst_value = 0;
                    ss_after_read_next = PARSE_AESES_CONTROL_BYTE;
            end
        PARSE_AESES_CONTROL_BYTE:
            begin


                    ss_next = CHECK_UART_RXFIFO;
                    

                    
                    if(data[`AESES_RESET_BIT] == 1'b1)
                    begin
                        cnt_recvbyte_rst = 1'b1;
                        cnt_recvbyte_rst_value = NUM_BYTE_KEY-1;
                        ss_after_read_next = AES_WAIT_READY_INIT;

                        if(data[`AESES_KEY_256_BIT] == 1'b1)

                            host_aes_key_mode_next = `KEY_256;
                        else
                            host_aes_key_mode_next = data[`AESES_KEY_FIELD];
                    end
                    else if(data[`AESES_EN_BIT] == 1'b1)
                    begin
                        cnt_recvbyte_rst = 1'b1;
                        cnt_recvbyte_rst_value = NUM_BYTE_BLK-1;
                        ss_after_read_next = AES_WAIT_READY_COMP;

                        host_aes_enc_decneg_next = data[`AESES_ENC_DEC];
                    end
                    else
                        ss_next = GET_AESES_CONTROL_BYTE;
            end
        CHECK_UART_RXFIFO:
            begin
                set_uart_op(READ_OP,`UART_REG_LS,1,0);
                if(wb_ack_uart_i && wb_dat_uart_i[`UART_LS_DR]==1)
                begin
                    ss_next = READ_BYTE_UART;

                    wb_cyc_uart_o_next    = 0;
                    wb_stb_uart_o_next    = 0;
                    wb_we_uart_o_next    = 0;
                    $strobe("@%0t: Host0 - UART_FIFO_RX_BUF_HAS_BYTE",$time);
                end
            end
        READ_BYTE_UART:
            begin
                set_uart_op(READ_OP,`UART_REG_RB,1,0);
                if(wb_ack_uart_i)
                begin
                    if(cnt_recvbyte==0)
                    begin

                        ss_next = ss_after_read;
                        cnt_recvbyte_rst = 1;
                    end
                    else
                    begin
                        ss_next = CHECK_UART_RXFIFO;
                        cnt_recvbyte_dec = 1;
                    end
    

                    wb_cyc_uart_o_next    = 0;
                    wb_stb_uart_o_next    = 0;
                    wb_we_uart_o_next    = 0;
                    data_next = wb_dat_uart_i;
                    $strobe("@%0t: Host0 - END_READ_UART",$time);
                end
                else
                begin
                    ss_next = READ_BYTE_UART;
                    $strobe("@%0t: Host0 - TRY_READ_UART",$time);
                end
            end


		CHECK_UART_TXFIFO:
			begin
				set_uart_op(READ_OP,`UART_REG_LS,1,0);
				if(wb_ack_uart_i && wb_dat_uart_i[`UART_LS_TE]==1)
				begin
					ss_next = WRITE_BYTE_UART;

					wb_cyc_uart_o_next	= 0;
					wb_stb_uart_o_next	= 0;
					wb_we_uart_o_next	= 0;
					
					$strobe("@%0t: Host0 - UART_FIFO_TX_BUF_EMPTY",$time);
				end
			end
		WRITE_BYTE_UART:
			begin
				set_uart_op(WRITE_OP,`UART_REG_TR,1, enc_r[ (UART_DW * (15-cnt_recvbyte)) +: 8] );
				if(wb_ack_uart_i)
				begin
					if(cnt_recvbyte==0)
					begin
						ss_next = GET_AESES_CONTROL_BYTE;

					end
					else
					begin
						ss_next = CHECK_UART_TXFIFO;
						cnt_recvbyte_dec = 1;
					end


					wb_cyc_uart_o_next	= 0;
					wb_stb_uart_o_next	= 0;
					wb_we_uart_o_next	= 0;
					$strobe("@%0t: Host0 - END_WRITE_UART",$time);
				end
				else
				begin
					ss_next = WRITE_BYTE_UART;
					$strobe("@%0t: Host0 - TRY_WRITE_UART",$time);
				end
			end


		AES_WAIT_READY_INIT:
			begin
				if(aes_host_ready_i)
				begin
					ss_next = AES_INIT_KEY_1;


					host_aes_enable_key_schedule_next = 1'b1;
					$strobe("@%0t: Host0 - AES_CORE is ready",$time);
				end
			end
		AES_INIT_KEY_1:
			begin
				if(~aes_host_ready_i)
				begin
					ss_next = AES_INIT_KEY_2;
					$strobe("@%0t: Host0 - key schedule STARTED",$time);
				end
			end
		AES_INIT_KEY_2:
			begin
				if(aes_host_ready_i)
				begin
					ss_next = GET_AESES_CONTROL_BYTE;
					$strobe("@%0t: Host0 - key scheduled DONE, waiting for blocks to encrypt/decrypt",$time);
				end
			end


		AES_WAIT_READY_COMP:
				begin
				trigger_o_next	=	1;
				if(aes_host_ready_i)
				begin
					ss_next = TRIGGER_DELAY_PRE_COMP;
					$strobe("@%0t: Host0 - AES_CORE is ready",$time);
				end
				end
		TRIGGER_DELAY_PRE_COMP:
			begin

				if(cnt_aes_delay == AES_PRE_POST_DELAY)
				begin
					cnt_aes_delay_rst = 1'b1;
					ss_next = AES_START_COMPUTATION;

					host_aes_enable_op_next = 1'b1;
				end
				else
				begin
					cnt_aes_delay_inc=1'b1;
				end

			end
		AES_START_COMPUTATION:
			begin

				ss_next = AES_START_COMPUTATION;
				if(~aes_host_ready_i)
				begin
					ss_next = AES_WAIT_COMP_DONE;
					$strobe("@%0t: Host0 - AES computation STARTED",$time);
				end
			end
		AES_WAIT_COMP_DONE:
			begin
				ss_next = AES_WAIT_COMP_DONE;

				if(aes_host_result_valid_i)
				begin
					enc_r_next = aes_host_result_i;
					ss_next = TRIGGER_DELAY_POST_COMP;

					$strobe("@%0t: Host0 - AES computation DONE with output: %h",$time,aes_host_result_i);
				end
			end
		TRIGGER_DELAY_POST_COMP:
			begin
				if(cnt_aes_delay == AES_PRE_POST_DELAY)
				begin
    				trigger_o_next	=	0;
					cnt_aes_delay_rst = 1'b1;
					ss_next = TRIGGER_DELAY;
				end
				else
				begin
					cnt_aes_delay_inc = 1'b1;
				end

			end


		TRIGGER_DELAY:
			begin
				if(trigger_cnt == TRIGGER_MAX)
				begin
					trigger_cnt_rst = 1'b1;
					ss_next = PREPARE_REUSE_DATA;
				end
				else
				begin
					trigger_cnt_inc=1'b1;
				end

			end


		PREPARE_REUSE_DATA:
		begin
			cnt_recvbyte_rst = 1;

			if(reuse_cnt != NUM_CNT_REUSE_TIMES )
			begin
				reuse_cnt_inc = 1'b1;

				plainFlush_r_we_next	= 1'b1;
				ss_next = AES_WAIT_READY_COMP;
			end
			else
			begin
				ss_next = CHECK_UART_TXFIFO;
				reuse_cnt_rst = 1'b1;
				cnt_recvbyte_rst = 1'b1;
                cnt_recvbyte_rst_value = NUM_BYTE_BLK-1;
			end
		end
	endcase
end



always@(*)
begin
		reuse_cnt_next	= 16'b0;
		reuse_cnt_we	= 1'b0;

		if(reuse_cnt_inc)
		begin
			reuse_cnt_next	= reuse_cnt + 1'b1;
			reuse_cnt_we 	=	1'b1;
		end
		else if(reuse_cnt_rst)
		begin
			reuse_cnt_next	= 16'b0;
			reuse_cnt_we 	= 1'b1;
		end
end



always@(*)
begin

		cnt_aes_delay_next	= 16'b0;
		cnt_aes_delay_we		= 1'b0;

		if(cnt_aes_delay_inc)
		begin
			cnt_aes_delay_next	=	cnt_aes_delay + 1'b1;
			cnt_aes_delay_we 	=	1'b1;
		end
		else if(cnt_aes_delay_rst)
		begin
			cnt_aes_delay_next	= 0;
			cnt_aes_delay_we 	= 1'b1;
		end
end



always@(*)
begin
		trigger_cnt_next	= 16'b0;
		trigger_cnt_we		= 1'b0;

		if(trigger_cnt_inc)
		begin
			trigger_cnt_next	=	trigger_cnt + 1'b1;
			trigger_cnt_we 		=	1'b1;
		end
		else if(trigger_cnt_rst)
		begin
			trigger_cnt_next	= 0;
			trigger_cnt_we 		= 1'b1;
		end
end



always@(*)
begin
		cnt_recvbyte_next	= 'b0;
		cnt_recvbyte_we		= 1'b0;

		if(cnt_recvbyte_dec)
		begin
			cnt_recvbyte_next	=	cnt_recvbyte - 1'b1;
			cnt_recvbyte_we 	=	1'b1;
		end
		else if(cnt_recvbyte_rst)
		begin




			cnt_recvbyte_next	= cnt_recvbyte_rst_value;
			cnt_recvbyte_we 	= 1'b1;
		end
end



always@(*)
begin
    key_r_we_next = wb_ack_uart_i && ss_after_read == AES_WAIT_READY_INIT;
    plain_r_we_next = plainFlush_r_we_next || (wb_ack_uart_i && ss_after_read == AES_WAIT_READY_COMP);
end

endmodule
module host_ctrl(
					wb_clk,wb_rst,

					wb_adr_uart_o,
					wb_dat_uart_o,
					wb_cyc_uart_o,
					wb_stb_uart_o,
					wb_sel_uart_o,
					wb_we_uart_o,
					wb_dat_uart_i,
					wb_ack_uart_i,

					host_aes_key_o,
					host_aes_blk_o,
					host_aes_key_mode_o,
					host_aes_enable_key_schedule_o,
					host_aes_enable_op_o,
					host_aes_enc_decneg_o,
					aes_host_result_i,
					aes_host_result_valid_i,
					aes_host_ready_i,

					trigger_o,
					recv_byte_led_o
			);


parameter UART_AW	=	3;
parameter UART_DW	=	8;
parameter CNT_BIT	=	16;
parameter NUM_BYTE_BLK	=	16;
parameter NUM_BYTE_KEY  =   32;

parameter AES_KW = 256;
parameter AES_DW = 128;

parameter TRIGGER_BIT_W 		= 18;
parameter TRIGGER_MAX			= 100000;
parameter AES_PRE_POST_DELAY 	= 20;

parameter NUM_CNT_REUSE_TIMES 	= 0;
parameter NUM_CNT_REUSE_BIT 	= 16;




input wb_clk;
input wb_rst;




output	reg [UART_AW-1:0]	wb_adr_uart_o;
output	reg [UART_DW-1:0]	wb_dat_uart_o;
output 	reg					wb_cyc_uart_o;
output 	reg					wb_stb_uart_o;
output	reg [3:0]			wb_sel_uart_o;
output	reg 				wb_we_uart_o;

input	[UART_DW-1:0]	wb_dat_uart_i;
input 					wb_ack_uart_i;



output      [0:AES_KW-1]    host_aes_key_o;
output      [0:AES_DW-1]    host_aes_blk_o;
output  reg [1:0]           host_aes_key_mode_o;
output  reg                 host_aes_enc_decneg_o;
output  reg                 host_aes_enable_key_schedule_o;
output  reg                 host_aes_enable_op_o;

input		[0:AES_DW-1]	aes_host_result_i;
input	 					aes_host_result_valid_i;
input 						aes_host_ready_i;


output [7:0]	recv_byte_led_o;
output reg		trigger_o;


function integer clog2(input integer value);
begin
		if(value==0)
			clog2=0;
		else
		begin
			while(value>0)
			begin
				clog2=clog2+1;
				value=value>>1;
			end
		end
end
endfunction


localparam [4:0]	CONFIGURE					= 5'd0,
					WE_UART_DIV_REG				= 5'd1,
					SET_UART_DIV_REG			= 5'd2,
					END_CONFIGURE				= 5'd3,

					GET_AESES_CONTROL_BYTE		= 5'd4,
					PARSE_AESES_CONTROL_BYTE	= 5'd5,

					CHECK_UART_RXFIFO			= 5'd6,
					READ_BYTE_UART         		= 5'd7,
					
					CHECK_UART_TXFIFO			= 5'd8,
					WRITE_BYTE_UART    			= 5'd9,

					AES_WAIT_READY_INIT			= 5'd18,
					AES_INIT_KEY_1				= 5'd19,
					AES_INIT_KEY_2				= 5'd20,

					AES_WAIT_READY_COMP			= 5'd21,
					AES_START_COMPUTATION		= 5'd22,
					AES_WAIT_COMP_DONE			= 5'd23,

					TRIGGER_DELAY				= 5'd24,

					TRIGGER_DELAY_PRE_COMP		= 5'd25,
					TRIGGER_DELAY_POST_COMP		= 5'd26,

					PREPARE_REUSE_DATA			= 5'd27;



reg [4:0] ss, ss_next;
reg [4:0] ss_after_read, ss_after_read_next;

reg trigger_o_next;
reg [TRIGGER_BIT_W-1:0] trigger_cnt, trigger_cnt_next;

reg trigger_cnt_inc;
reg trigger_cnt_rst;
reg trigger_cnt_we;


reg [TRIGGER_BIT_W-1:0] cnt_aes_delay, cnt_aes_delay_next;

reg cnt_aes_delay_inc;
reg cnt_aes_delay_rst;
reg cnt_aes_delay_we;

reg [NUM_CNT_REUSE_BIT-1:0] reuse_cnt,	reuse_cnt_next;
reg reuse_cnt_we;
reg reuse_cnt_rst;
reg reuse_cnt_inc;





reg [UART_DW-1:0] key_r 	[0:NUM_BYTE_KEY-1];
reg key_r_we_next;
wire [0:255] key_wire;


reg [UART_DW-1:0] plain_r 	[0:NUM_BYTE_BLK-1];
reg plain_r_we_next;
reg plainFlush_r_we_next;
wire [0:127] plain_wire;

reg [0:127] enc_r, enc_r_next;

reg [UART_DW-1:0] 		data, data_next;

localparam CTR_WIDTH = $clog2(NUM_BYTE_KEY);

reg [CTR_WIDTH:0] cnt_recvbyte, cnt_recvbyte_next, cnt_recvbyte_rst_value;
reg	cnt_recvbyte_dec;
reg	cnt_recvbyte_rst;
reg	cnt_recvbyte_we;


reg [UART_AW-1:0]	wb_adr_uart_o_next;
reg [UART_DW-1:0]	wb_dat_uart_o_next;
reg					wb_cyc_uart_o_next;
reg					wb_stb_uart_o_next;
reg [3:0]			wb_sel_uart_o_next;
reg 				wb_we_uart_o_next;


reg [1:0]   host_aes_key_mode_next;
reg         host_aes_enc_decneg_next;
reg         host_aes_enable_key_schedule_next;
reg         host_aes_enable_op_next;







localparam 	READ_OP		= 1'b0;
localparam	WRITE_OP	= 1'b1;

task set_uart_op;
input rw;
input [UART_AW-1:0] addr;
input [3:0] sel;
input [UART_DW-1:0] wdata;
begin
	wb_cyc_uart_o_next	= 1;
	wb_stb_uart_o_next	= 1;
	wb_adr_uart_o_next	= addr;
	wb_sel_uart_o_next	= sel;
	wb_we_uart_o_next	= rw;
	wb_dat_uart_o_next	= wdata;
end
endtask



assign host_aes_blk_o 	= {
                        plain_r[15],	plain_r[14], 	plain_r[13], 	plain_r[12],
						plain_r[11],	plain_r[10],	plain_r[9],		plain_r[8],
						plain_r[7],		plain_r[6],		plain_r[5],		plain_r[4],
						plain_r[3],		plain_r[2],		plain_r[1], 	plain_r[0] };

assign host_aes_key_o 	= {
                        key_r[31],		key_r[30],		key_r[29],		key_r[28],
                        key_r[27],		key_r[26],		key_r[25],		key_r[24],
                        key_r[23],		key_r[22],		key_r[21],		key_r[20],
                        key_r[19],		key_r[18],		key_r[17],		key_r[16],
                        key_r[15],		key_r[14],		key_r[13],		key_r[12],
						key_r[11],		key_r[10],		key_r[9],		key_r[8],
						key_r[7],		key_r[6],		key_r[5],		key_r[4],
						key_r[3],		key_r[2],		key_r[1], 		key_r[0] };

assign recv_byte_led_o[4:0] = ss;
assign recv_byte_led_o[5] = host_aes_enc_decneg_o;
assign recv_byte_led_o[7:6] = host_aes_key_mode_o;





always@(posedge wb_clk, posedge wb_rst)
begin:seq_host
	integer i;
	if(wb_rst)
	begin
		ss 				<=	CONFIGURE;
		ss_after_read   <=  GET_AESES_CONTROL_BYTE;
		trigger_o 		<=	0;
		trigger_cnt		<=	0;
		cnt_aes_delay	<=	0;
		reuse_cnt		<=	0;

		wb_adr_uart_o	<=	{UART_AW{1'b0}};
		wb_cyc_uart_o	<=	0;
		wb_stb_uart_o	<=	0;
		wb_sel_uart_o	<=	0;
		wb_dat_uart_o	<=	0;
		wb_we_uart_o	<=	0;
		data			<=	0;

		for(i=0;i<NUM_BYTE_KEY;i=i+1)
			key_r[i]	<=	0;

		for(i=0;i<NUM_BYTE_BLK;i=i+1)
			plain_r[i]	<=	0;

		cnt_recvbyte	<=	0;
		enc_r			<=	0;


		host_aes_key_mode_o             <= `KEY_128;
        host_aes_enc_decneg_o           <= 1'b1;
        host_aes_enable_key_schedule_o  <= 1'b0;
        host_aes_enable_op_o            <= 1'b0;
	end
	else
	begin
		ss				<=	ss_next;
		trigger_o 		<=	trigger_o_next;

		if(trigger_cnt_we)
			trigger_cnt		<=	trigger_cnt_next;

		if(cnt_aes_delay_we)
			cnt_aes_delay	<=	cnt_aes_delay_next;
		if(reuse_cnt_we)
			reuse_cnt		<=	reuse_cnt_next;


		wb_adr_uart_o	<= wb_adr_uart_o_next;
		wb_cyc_uart_o	<= wb_cyc_uart_o_next;
		wb_stb_uart_o	<= wb_stb_uart_o_next;
		wb_sel_uart_o	<= wb_sel_uart_o_next;
		wb_dat_uart_o	<= wb_dat_uart_o_next;
		wb_we_uart_o	<= wb_we_uart_o_next;
		data			<= data_next;


		if(cnt_recvbyte_we)
			cnt_recvbyte		<=	cnt_recvbyte_next;

		if(key_r_we_next)
			key_r[cnt_recvbyte]	<=	data_next;

		if(plain_r_we_next)
		begin
			if(plainFlush_r_we_next)
			begin
				for(i=0; i<NUM_BYTE_BLK; i=i+1)
				begin
					plain_r[NUM_BYTE_BLK-1-i] <= enc_r[(UART_DW * (i))+:8];

				end
			end
			else
				plain_r[cnt_recvbyte]	<=	data_next;
		end
		enc_r		<= enc_r_next;


		host_aes_key_mode_o             <= host_aes_key_mode_next;
        host_aes_enc_decneg_o           <= host_aes_enc_decneg_next;
        host_aes_enable_key_schedule_o  <= host_aes_enable_key_schedule_next;
        host_aes_enable_op_o            <= host_aes_enable_op_next;
	

	    ss_after_read       <=  ss_after_read_next;
	end
end






always@(*)
begin

	ss_next 			= ss;
	trigger_o_next		= trigger_o;


	wb_adr_uart_o_next	= wb_adr_uart_o;
	wb_cyc_uart_o_next	= wb_cyc_uart_o;
	wb_stb_uart_o_next	= wb_stb_uart_o;
	wb_sel_uart_o_next	= wb_sel_uart_o;
	wb_we_uart_o_next	= wb_we_uart_o;
	wb_dat_uart_o_next	= wb_dat_uart_o;
	data_next			= data;


	plainFlush_r_we_next= 0;
	enc_r_next			= enc_r;


	host_aes_key_mode_next = host_aes_key_mode_o;
    host_aes_enc_decneg_next = host_aes_enc_decneg_o;
    host_aes_enable_key_schedule_next = 1'b0;
    host_aes_enable_op_next = 1'b0;

	trigger_cnt_inc = 0;
    trigger_cnt_rst = 0;

	cnt_recvbyte_dec = 0;
	cnt_recvbyte_rst = 0;

	reuse_cnt_inc = 0;
	reuse_cnt_rst = 0;

	cnt_aes_delay_inc=0;
	cnt_aes_delay_rst=0;
	

	ss_after_read_next = ss_after_read;
	cnt_recvbyte_rst_value = 0;

	case(ss)

		CONFIGURE:
			begin
			if(wb_rst==0)
				ss_next = WE_UART_DIV_REG;
			else
				ss_next = CONFIGURE;
			end
		WE_UART_DIV_REG:
			begin
				set_uart_op(WRITE_OP,`UART_REG_LC,4'b1,8'b10000011);
				if(wb_ack_uart_i)
				begin
					ss_next = SET_UART_DIV_REG;
					wb_cyc_uart_o_next	= 0;
					wb_stb_uart_o_next	= 0;
					wb_we_uart_o_next	= 0;
				end
				else
					ss_next = WE_UART_DIV_REG;
			end
		SET_UART_DIV_REG:
			begin
				set_uart_op(WRITE_OP,`UART_REG_DL1,4'd1,`UART_CLK_DIV_DEF);
				if(wb_ack_uart_i)
				begin
					ss_next = END_CONFIGURE;
					wb_cyc_uart_o_next	= 0;
					wb_stb_uart_o_next	= 0;
					wb_we_uart_o_next	= 0;
					end
				else
					ss_next = SET_UART_DIV_REG;
			end
		END_CONFIGURE:
			begin
				set_uart_op(WRITE_OP,`UART_REG_LC,4'b1,8'b00000011);
				if(wb_ack_uart_i)
				begin
					ss_next = GET_AESES_CONTROL_BYTE;

					wb_cyc_uart_o_next	= 0;
					wb_stb_uart_o_next	= 0;
					wb_we_uart_o_next	= 0;
					end
				else
					ss_next = END_CONFIGURE;
			end
			


        GET_AESES_CONTROL_BYTE:
            begin
                    ss_next = CHECK_UART_RXFIFO;
                    cnt_recvbyte_rst = 1'b1;
                    cnt_recvbyte_rst_value = 0;
                    ss_after_read_next = PARSE_AESES_CONTROL_BYTE;
            end
        PARSE_AESES_CONTROL_BYTE:
            begin


                    ss_next = CHECK_UART_RXFIFO;
                    

                    
                    if(data[`AESES_RESET_BIT] == 1'b1)
                    begin
                        cnt_recvbyte_rst = 1'b1;
                        cnt_recvbyte_rst_value = NUM_BYTE_KEY-1;
                        ss_after_read_next = AES_WAIT_READY_INIT;

                        if(data[`AESES_KEY_256_BIT] == 1'b1)

                            host_aes_key_mode_next = `KEY_256;
                        else
                            host_aes_key_mode_next = data[`AESES_KEY_FIELD];
                    end
                    else if(data[`AESES_EN_BIT] == 1'b1)
                    begin
                        cnt_recvbyte_rst = 1'b1;
                        cnt_recvbyte_rst_value = NUM_BYTE_BLK-1;
                        ss_after_read_next = AES_WAIT_READY_COMP;

                        host_aes_enc_decneg_next = data[`AESES_ENC_DEC];
                    end
                    else
                        ss_next = GET_AESES_CONTROL_BYTE;
            end
        CHECK_UART_RXFIFO:
            begin
                set_uart_op(READ_OP,`UART_REG_LS,1,0);
                if(wb_ack_uart_i && wb_dat_uart_i[`UART_LS_DR]==1)
                begin
                    ss_next = READ_BYTE_UART;

                    wb_cyc_uart_o_next    = 0;
                    wb_stb_uart_o_next    = 0;
                    wb_we_uart_o_next    = 0;
                    $strobe("@%0t: Host0 - UART_FIFO_RX_BUF_HAS_BYTE",$time);
                end
            end
        READ_BYTE_UART:
            begin
                set_uart_op(READ_OP,`UART_REG_RB,1,0);
                if(wb_ack_uart_i)
                begin
                    if(cnt_recvbyte==0)
                    begin

                        ss_next = ss_after_read;
                        cnt_recvbyte_rst = 1;
                    end
                    else
                    begin
                        ss_next = CHECK_UART_RXFIFO;
                        cnt_recvbyte_dec = 1;
                    end
    

                    wb_cyc_uart_o_next    = 0;
                    wb_stb_uart_o_next    = 0;
                    wb_we_uart_o_next    = 0;
                    data_next = wb_dat_uart_i;
                    $strobe("@%0t: Host0 - END_READ_UART",$time);
                end
                else
                begin
                    ss_next = READ_BYTE_UART;
                    $strobe("@%0t: Host0 - TRY_READ_UART",$time);
                end
            end


		CHECK_UART_TXFIFO:
			begin
				set_uart_op(READ_OP,`UART_REG_LS,1,0);
				if(wb_ack_uart_i && wb_dat_uart_i[`UART_LS_TE]==1)
				begin
					ss_next = WRITE_BYTE_UART;

					wb_cyc_uart_o_next	= 0;
					wb_stb_uart_o_next	= 0;
					wb_we_uart_o_next	= 0;
					
					$strobe("@%0t: Host0 - UART_FIFO_TX_BUF_EMPTY",$time);
				end
			end
		WRITE_BYTE_UART:
			begin
				set_uart_op(WRITE_OP,`UART_REG_TR,1, enc_r[ (UART_DW * (15-cnt_recvbyte)) +: 8] );
				if(wb_ack_uart_i)
				begin
					if(cnt_recvbyte==0)
					begin
						ss_next = GET_AESES_CONTROL_BYTE;

					end
					else
					begin
						ss_next = CHECK_UART_TXFIFO;
						cnt_recvbyte_dec = 1;
					end


					wb_cyc_uart_o_next	= 0;
					wb_stb_uart_o_next	= 0;
					wb_we_uart_o_next	= 0;
					$strobe("@%0t: Host0 - END_WRITE_UART",$time);
				end
				else
				begin
					ss_next = WRITE_BYTE_UART;
					$strobe("@%0t: Host0 - TRY_WRITE_UART",$time);
				end
			end


		AES_WAIT_READY_INIT:
			begin
				if(aes_host_ready_i)
				begin
					ss_next = AES_INIT_KEY_1;


					host_aes_enable_key_schedule_next = 1'b1;
					$strobe("@%0t: Host0 - AES_CORE is ready",$time);
				end
			end
		AES_INIT_KEY_1:
			begin
				if(~aes_host_ready_i)
				begin
					ss_next = AES_INIT_KEY_2;
					$strobe("@%0t: Host0 - key schedule STARTED",$time);
				end
			end
		AES_INIT_KEY_2:
			begin
				if(aes_host_ready_i)
				begin
					ss_next = GET_AESES_CONTROL_BYTE;
					$strobe("@%0t: Host0 - key scheduled DONE, waiting for blocks to encrypt/decrypt",$time);
				end
			end


		AES_WAIT_READY_COMP:
				begin
				trigger_o_next	=	1;
				if(aes_host_ready_i)
				begin
					ss_next = TRIGGER_DELAY_PRE_COMP;
					$strobe("@%0t: Host0 - AES_CORE is ready",$time);
				end
				end
		TRIGGER_DELAY_PRE_COMP:
			begin

				if(cnt_aes_delay == AES_PRE_POST_DELAY)
				begin
					cnt_aes_delay_rst = 1'b1;
					ss_next = AES_START_COMPUTATION;

					host_aes_enable_op_next = 1'b1;
				end
				else
				begin
					cnt_aes_delay_inc=1'b1;
				end

			end
		AES_START_COMPUTATION:
			begin

				ss_next = AES_START_COMPUTATION;
				if(~aes_host_ready_i)
				begin
					ss_next = AES_WAIT_COMP_DONE;
					$strobe("@%0t: Host0 - AES computation STARTED",$time);
				end
			end
		AES_WAIT_COMP_DONE:
			begin
				ss_next = AES_WAIT_COMP_DONE;

				if(aes_host_result_valid_i)
				begin
					enc_r_next = aes_host_result_i;
					ss_next = TRIGGER_DELAY_POST_COMP;

					$strobe("@%0t: Host0 - AES computation DONE with output: %h",$time,aes_host_result_i);
				end
			end
		TRIGGER_DELAY_POST_COMP:
			begin
				if(cnt_aes_delay == AES_PRE_POST_DELAY)
				begin
    				trigger_o_next	=	0;
					cnt_aes_delay_rst = 1'b1;
					ss_next = TRIGGER_DELAY;
				end
				else
				begin
					cnt_aes_delay_inc = 1'b1;
				end

			end


		TRIGGER_DELAY:
			begin
				if(trigger_cnt == TRIGGER_MAX)
				begin
					trigger_cnt_rst = 1'b1;
					ss_next = PREPARE_REUSE_DATA;
				end
				else
				begin
					trigger_cnt_inc=1'b1;
				end

			end


		PREPARE_REUSE_DATA:
		begin
			cnt_recvbyte_rst = 1;

			if(reuse_cnt != NUM_CNT_REUSE_TIMES )
			begin
				reuse_cnt_inc = 1'b1;

				plainFlush_r_we_next	= 1'b1;
				ss_next = AES_WAIT_READY_COMP;
			end
			else
			begin
				ss_next = CHECK_UART_TXFIFO;
				reuse_cnt_rst = 1'b1;
				cnt_recvbyte_rst = 1'b1;
                cnt_recvbyte_rst_value = NUM_BYTE_BLK-1;
			end
		end
	endcase
end



always@(*)
begin
		reuse_cnt_next	= 16'b0;
		reuse_cnt_we	= 1'b0;

		if(reuse_cnt_inc)
		begin
			reuse_cnt_next	= reuse_cnt + 1'b1;
			reuse_cnt_we 	=	1'b1;
		end
		else if(reuse_cnt_rst)
		begin
			reuse_cnt_next	= 16'b0;
			reuse_cnt_we 	= 1'b1;
		end
end



always@(*)
begin

		cnt_aes_delay_next	= 16'b0;
		cnt_aes_delay_we		= 1'b0;

		if(cnt_aes_delay_inc)
		begin
			cnt_aes_delay_next	=	cnt_aes_delay + 1'b1;
			cnt_aes_delay_we 	=	1'b1;
		end
		else if(cnt_aes_delay_rst)
		begin
			cnt_aes_delay_next	= 0;
			cnt_aes_delay_we 	= 1'b1;
		end
end



always@(*)
begin
		trigger_cnt_next	= 16'b0;
		trigger_cnt_we		= 1'b0;

		if(trigger_cnt_inc)
		begin
			trigger_cnt_next	=	trigger_cnt + 1'b1;
			trigger_cnt_we 		=	1'b1;
		end
		else if(trigger_cnt_rst)
		begin
			trigger_cnt_next	= 0;
			trigger_cnt_we 		= 1'b1;
		end
end



always@(*)
begin
		cnt_recvbyte_next	= 'b0;
		cnt_recvbyte_we		= 1'b0;

		if(cnt_recvbyte_dec)
		begin
			cnt_recvbyte_next	=	cnt_recvbyte - 1'b1;
			cnt_recvbyte_we 	=	1'b1;
		end
		else if(cnt_recvbyte_rst)
		begin




			cnt_recvbyte_next	= cnt_recvbyte_rst_value;
			cnt_recvbyte_we 	= 1'b1;
		end
end



always@(*)
begin
    key_r_we_next = wb_ack_uart_i && ss_after_read == AES_WAIT_READY_INIT;
    plain_r_we_next = plainFlush_r_we_next || (wb_ack_uart_i && ss_after_read == AES_WAIT_READY_COMP);
end

endmodule