data/full_repos/permissive/169258653/pipeline-with-cache/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/hazard.v
data/verilator_xmls/71be7d76-63be-4920-81aa-f840eb97431a.xml
module hazard(
    input [4:0] rsD,rtD,rsE,rtE,
    input [4:0] writeregE,writeregM,writeregW,
    input regwriteE,regwriteM,regwriteW,
    input memtoregE,memtoregM,branchD,
    output forwardaD,forwardbD,
    output reg [1:0] forwardaE,forwardbE,
    output stallF,stallD,flushE,
    input [1:0] jumpD,
    output [15:0] led,
    input beep
    );
    
    wire lwstallD,branchstallD;
    wire jalrstallD;
    
    wire [15:0] BEEP;
    

    assign forwardaD=(rsD!=0 & rsD==writeregM & regwriteM);
    assign forwardbD=(rtD!=0 & rtD==writeregM & regwriteM);
    

    always@(*)
    begin
        forwardaE=2'b00;
        if(rsE!=0)
        begin
            if(rsE==writeregM & regwriteM)
                forwardaE=2'b10;
            else
                if(rsE==writeregW & regwriteW)
                    forwardaE=2'b01;
        end
        
        forwardbE=2'b00;
        if(rtE!=0)
        begin 
            if(rtE==writeregM & regwriteM)
                forwardbE=2'b10;
            else
                if(rtE==writeregW & regwriteW)
                    forwardbE=2'b01;
        end
    end
    

    assign lwstallD=memtoregE & (rtE==rsD | rtE==rtD);
    assign branchstallD=branchD & 
                           (regwriteE & (writeregE==rsD | writeregE==rtD) | 
                            memtoregM & (writeregM==rsD | writeregM==rtD));
    assign jalrstallD=(jumpD==2'b10) & 
                         (regwriteE & writeregE==rsD |
                          memtoregM & writeregM==rsD);
    
    assign stallD=lwstallD | branchstallD | jalrstallD;
    assign stallF=stallD;
    assign flushE=stallD;
    

    assign BEEP={beep,beep,beep,beep,
                 beep,beep,beep,beep,
                 beep,beep,beep,beep,
                 beep,beep,beep,beep};  

    assign led={stallF,stallD,flushE,
                lwstallD,branchstallD,jalrstallD,
                forwardaD,forwardbD,
                forwardaE,forwardbE,
                BEEP[3:0]};
    
endmodule
module hazard(
    input [4:0] rsD,rtD,rsE,rtE,
    input [4:0] writeregE,writeregM,writeregW,
    input regwriteE,regwriteM,regwriteW,
    input memtoregE,memtoregM,branchD,
    output forwardaD,forwardbD,
    output reg [1:0] forwardaE,forwardbE,
    output stallF,stallD,flushE,
    input [1:0] jumpD,
    output [15:0] led,
    input beep
    );

    
    wire lwstallD,branchstallD;
    wire jalrstallD;
    
    wire [15:0] BEEP;
    

    assign forwardaD=(rsD!=0 & rsD==writeregM & regwriteM);
    assign forwardbD=(rtD!=0 & rtD==writeregM & regwriteM);
    

    always@(*)
    begin
        forwardaE=2'b00;
        if(rsE!=0)
        begin
            if(rsE==writeregM & regwriteM)
                forwardaE=2'b10;
            else
                if(rsE==writeregW & regwriteW)
                    forwardaE=2'b01;
        end
        
        forwardbE=2'b00;
        if(rtE!=0)
        begin 
            if(rtE==writeregM & regwriteM)
                forwardbE=2'b10;
            else
                if(rtE==writeregW & regwriteW)
                    forwardbE=2'b01;
        end
    end
    

    assign lwstallD=memtoregE & (rtE==rsD | rtE==rtD);
    assign branchstallD=branchD & 
                           (regwriteE & (writeregE==rsD | writeregE==rtD) | 
                            memtoregM & (writeregM==rsD | writeregM==rtD));
    assign jalrstallD=(jumpD==2'b10) & 
                         (regwriteE & writeregE==rsD |
                          memtoregM & writeregM==rsD);
    
    assign stallD=lwstallD | branchstallD | jalrstallD;
    assign stallF=stallD;
    assign flushE=stallD;
    

    assign BEEP={beep,beep,beep,beep,
                 beep,beep,beep,beep,
                 beep,beep,beep,beep,
                 beep,beep,beep,beep};  

    assign led={stallF,stallD,flushE,
                lwstallD,branchstallD,jalrstallD,
                forwardaD,forwardbD,
                forwardaE,forwardbE,
                BEEP[3:0]};
    
endmodule