data/full_repos/permissive/154371523/Code/rtl/xregf.v
1: b'%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:2: Cannot find include file: xdefs.vh\n`include "xdefs.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh.v\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/xdefs.vh.sv\n             xdefs.vh\n             xdefs.vh.v\n             xdefs.vh.sv\n             obj_dir/xdefs.vh\n             obj_dir/xdefs.vh.v\n             obj_dir/xdefs.vh.sv\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:3: Cannot find include file: xregfdefs.vh\n`include "xregfdefs.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:10: Define or directive not defined: \'`REGF_ADDR_W\'\n       input [`REGF_ADDR_W-1:0] ext_addr,\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:11: Define or directive not defined: \'`DATA_W\'\n       input [`DATA_W-1:0]      ext_data_in,\n              ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:12: Define or directive not defined: \'`DATA_W\'\n       output [`DATA_W-1:0]     ext_data_out,\n               ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:17: Define or directive not defined: \'`REGF_ADDR_W\'\n       input [`REGF_ADDR_W-1:0] int_addr,\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:18: Define or directive not defined: \'`DATA_W\'\n       input [`DATA_W-1:0]      int_data_in,\n              ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:19: Define or directive not defined: \'`DATA_W\'\n       output [`DATA_W-1:0]     int_data_out\n               ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:24: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W-1:0]     reg_1 [2**`REGF_ADDR_W-1:0];\n        ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:24: Define or directive not defined: \'`REGF_ADDR_W\'\n   reg [`DATA_W-1:0]     reg_1 [2**`REGF_ADDR_W-1:0];\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:25: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W-1:0]     reg_2 [2**`REGF_ADDR_W-1:0];\n        ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:25: Define or directive not defined: \'`REGF_ADDR_W\'\n   reg [`DATA_W-1:0]     reg_2 [2**`REGF_ADDR_W-1:0];\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:28: Define or directive not defined: \'`DATA_W\'\n   wire [`DATA_W-1:0]     data_in;\n         ^~~~~~~\n%Error: data/full_repos/permissive/154371523/Code/rtl/xregf.v:29: Define or directive not defined: \'`REGF_ADDR_W\'\n   wire [`REGF_ADDR_W-1:0]    addr;\n         ^~~~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module xregf (
	      input 		       clk,


	      input 		       ext_we,
	      input [`REGF_ADDR_W-1:0] ext_addr,
	      input [`DATA_W-1:0]      ext_data_in,
	      output [`DATA_W-1:0]     ext_data_out,


	      input 		       int_sel,
	      input 		       int_we,
	      input [`REGF_ADDR_W-1:0] int_addr,
	      input [`DATA_W-1:0]      int_data_in,
	      output [`DATA_W-1:0]     int_data_out
	      );



   reg [`DATA_W-1:0] 				reg_1 [2**`REGF_ADDR_W-1:0];
   reg [`DATA_W-1:0] 				reg_2 [2**`REGF_ADDR_W-1:0];

   wire 					int_we_int;
   wire [`DATA_W-1:0] 				data_in;
   wire [`REGF_ADDR_W-1:0] 			addr;
   wire 					we;

   assign int_we_int = int_sel & int_we;
   assign we = ext_we | int_we_int;
   assign addr = (ext_we == 1'b1) ? ext_addr : int_addr;
   assign data_in = (ext_we == 1'b1) ? ext_data_in : int_data_in;

   assign ext_data_out = reg_1[ext_addr];
   assign int_data_out = reg_2[int_addr];

   always @ (posedge clk) begin
      if (we) begin
	 reg_1[addr] <= data_in;
	 reg_2[addr] <= data_in;
      end
   end

endmodule
module xregf (
	      input 		       clk,


	      input 		       ext_we,
	      input [`REGF_ADDR_W-1:0] ext_addr,
	      input [`DATA_W-1:0]      ext_data_in,
	      output [`DATA_W-1:0]     ext_data_out,


	      input 		       int_sel,
	      input 		       int_we,
	      input [`REGF_ADDR_W-1:0] int_addr,
	      input [`DATA_W-1:0]      int_data_in,
	      output [`DATA_W-1:0]     int_data_out
	      );




   reg [`DATA_W-1:0] 				reg_1 [2**`REGF_ADDR_W-1:0];
   reg [`DATA_W-1:0] 				reg_2 [2**`REGF_ADDR_W-1:0];

   wire 					int_we_int;
   wire [`DATA_W-1:0] 				data_in;
   wire [`REGF_ADDR_W-1:0] 			addr;
   wire 					we;

   assign int_we_int = int_sel & int_we;
   assign we = ext_we | int_we_int;
   assign addr = (ext_we == 1'b1) ? ext_addr : int_addr;
   assign data_in = (ext_we == 1'b1) ? ext_data_in : int_data_in;

   assign ext_data_out = reg_1[ext_addr];
   assign int_data_out = reg_2[int_addr];

   always @ (posedge clk) begin
      if (we) begin
	 reg_1[addr] <= data_in;
	 reg_2[addr] <= data_in;
      end
   end

endmodule