data/full_repos/permissive/168395472/problems/11_uart_mmio/alu.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/168395472/problems/11_uart_mmio/alu.v:18: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                                   : ... In instance alu\n        3\'b010: res = sign_a < sign_b;   \n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/168395472/problems/11_uart_mmio/alu.v:19: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                                   : ... In instance alu\n        3\'b011: res = src_a < src_b;     \n                    ^\n%Error: Exiting due to 2 warning(s)\n'
module alu(
    input [31:0]src_a,
    input [31:0]src_b,
    input [2:0]op,
    input alt,

    output reg [31:0]res
);

wire signed [31:0]sign_a = src_a;
wire signed [31:0]sign_b = src_b;
wire [4:0]shamt = src_b[4:0];

always @(*) begin
    case (op)
        3'b000: res = src_a + (alt ? (~src_b + 32'b1) : src_b);
        3'b001: res = src_a << shamt;
        3'b010: res = sign_a < sign_b;
        3'b011: res = src_a < src_b;
        3'b100: res = src_a ^ src_b;
        3'b101: res = alt ? (sign_a >>> shamt) : (src_a >> shamt);
        3'b110: res = src_a | src_b;
        3'b111: res = src_a & src_b;
    endcase
end

endmodule
module alu(
    input [31:0]src_a,
    input [31:0]src_b,
    input [2:0]op,
    input alt,

    output reg [31:0]res
);


wire signed [31:0]sign_a = src_a;
wire signed [31:0]sign_b = src_b;
wire [4:0]shamt = src_b[4:0];

always @(*) begin
    case (op)
        3'b000: res = src_a + (alt ? (~src_b + 32'b1) : src_b);
        3'b001: res = src_a << shamt;
        3'b010: res = sign_a < sign_b;
        3'b011: res = src_a < src_b;
        3'b100: res = src_a ^ src_b;
        3'b101: res = alt ? (sign_a >>> shamt) : (src_a >> shamt);
        3'b110: res = src_a | src_b;
        3'b111: res = src_a & src_b;
    endcase
end

endmodule