data/full_repos/permissive/121864597/Main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/121864597/Main.v:36: Unsupported: Ignoring delay on this delayed statement.\n#45 reset = 0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/121864597/Main.v:44: Unsupported: Ignoring delay on this delayed statement.\n#5 clk = !clk ;\n^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module D2(d,clk,q);
input d;
input clk;
output q;
reg q;
initial
q = 1'b0;
always @(posedge clk)
q <= d;
endmodule
module D2(d,clk,q);

input d;
input clk;
output q;
reg q;
initial
q = 1'b0;
always @(posedge clk)
q <= d;
endmodule