data/full_repos/permissive/217060808/bsg_cache/bsg_cache_sbuf/bsg_cache_sbuf_ways_p_2_addr_width_p_28_data_width_p_32/top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_sbuf/bsg_cache_sbuf_ways_p_2_addr_width_p_28_data_width_p_32/top.v:122: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                               : ... In instance top.wrapper.mux_segmented_merge1\n                       (N4)? data0_i[7:0] : 1\'b0;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_sbuf/bsg_cache_sbuf_ways_p_2_addr_width_p_28_data_width_p_32/top.v:125: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                               : ... In instance top.wrapper.mux_segmented_merge1\n                        (N5)? data0_i[15:8] : 1\'b0;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_sbuf/bsg_cache_sbuf_ways_p_2_addr_width_p_28_data_width_p_32/top.v:128: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                               : ... In instance top.wrapper.mux_segmented_merge1\n                         (N6)? data0_i[23:16] : 1\'b0;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_sbuf/bsg_cache_sbuf_ways_p_2_addr_width_p_28_data_width_p_32/top.v:131: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                               : ... In instance top.wrapper.mux_segmented_merge1\n                         (N7)? data0_i[31:24] : 1\'b0;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_sbuf/bsg_cache_sbuf_ways_p_2_addr_width_p_28_data_width_p_32/top.v:83: Operator COND expects 65 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                              : ... In instance top.wrapper.sbq\n                                                                                                                                                                                                                                                                                                                                              (N1)? data_i : 1\'b0;\n                                                                                                                                                                                                                                                                                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_sbuf/bsg_cache_sbuf_ways_p_2_addr_width_p_28_data_width_p_32/top.v:87: Operator COND expects 65 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                              : ... In instance top.wrapper.sbq\n                  (N3)? data_i : 1\'b0;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_sbuf/bsg_cache_sbuf_ways_p_2_addr_width_p_28_data_width_p_32/top.v:265: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                               : ... In instance top.wrapper\n                        (N5)? { N23, N22 } : 1\'b0;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_sbuf/bsg_cache_sbuf_ways_p_2_addr_width_p_28_data_width_p_32/top.v:272: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                               : ... In instance top.wrapper\n                                  (N66)? bypass_mask_n : 1\'b0;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_cache/bsg_cache_sbuf/bsg_cache_sbuf_ways_p_2_addr_width_p_28_data_width_p_32/top.v:274: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                               : ... In instance top.wrapper\n                                                                                                                                                                              (N66)? bypass_data_n : 1\'b0;\n                                                                                                                                                                                   ^\n%Error: Exiting due to 9 warning(s)\n'
module bsg_mux_segmented_segments_p4_segment_width_p8
(
  data0_i,
  data1_i,
  sel_i,
  data_o
);

  input [31:0] data0_i;
  input [31:0] data1_i;
  input [3:0] sel_i;
  output [31:0] data_o;
  wire [31:0] data_o;
  wire N0,N1,N2,N3,N4,N5,N6,N7;
  assign data_o[7:0] = (N0)? data1_i[7:0] : 
                       (N4)? data0_i[7:0] : 1'b0;
  assign N0 = sel_i[0];
  assign data_o[15:8] = (N1)? data1_i[15:8] : 
                        (N5)? data0_i[15:8] : 1'b0;
  assign N1 = sel_i[1];
  assign data_o[23:16] = (N2)? data1_i[23:16] : 
                         (N6)? data0_i[23:16] : 1'b0;
  assign N2 = sel_i[2];
  assign data_o[31:24] = (N3)? data1_i[31:24] : 
                         (N7)? data0_i[31:24] : 1'b0;
  assign N3 = sel_i[3];
  assign N4 = ~sel_i[0];
  assign N5 = ~sel_i[1];
  assign N6 = ~sel_i[2];
  assign N7 = ~sel_i[3];

endmodule
module bsg_mux_segmented_segments_p4_segment_width_p8
(
  data0_i,
  data1_i,
  sel_i,
  data_o
);


  input [31:0] data0_i;
  input [31:0] data1_i;
  input [3:0] sel_i;
  output [31:0] data_o;
  wire [31:0] data_o;
  wire N0,N1,N2,N3,N4,N5,N6,N7;
  assign data_o[7:0] = (N0)? data1_i[7:0] : 
                       (N4)? data0_i[7:0] : 1'b0;
  assign N0 = sel_i[0];
  assign data_o[15:8] = (N1)? data1_i[15:8] : 
                        (N5)? data0_i[15:8] : 1'b0;
  assign N1 = sel_i[1];
  assign data_o[23:16] = (N2)? data1_i[23:16] : 
                         (N6)? data0_i[23:16] : 1'b0;
  assign N2 = sel_i[2];
  assign data_o[31:24] = (N3)? data1_i[31:24] : 
                         (N7)? data0_i[31:24] : 1'b0;
  assign N3 = sel_i[3];
  assign N4 = ~sel_i[0];
  assign N5 = ~sel_i[1];
  assign N6 = ~sel_i[2];
  assign N7 = ~sel_i[3];

endmodule