data/full_repos/permissive/190595283/Modulos/ControleALU.v
data/verilator_xmls/82a1655f-2667-41b3-b616-e7bbb0ac9bbe.xml
module ControleALU (OpCode_ALU,Func_Code,Controle_ALU);
  input [1:0] OpCode_ALU;
  input [5:0]Func_Code;
  output reg [3:0]Controle_ALU;

  always @ ( OpCode_ALU or Func_Code ) begin
    case(OpCode_ALU)
       0: begin
          Controle_ALU = `ALU_ADD;
          end
       1: begin
         Controle_ALU = `ALU_SUB;
          end
       2: begin
            case (Func_Code)
            32:begin
                 Controle_ALU = `ALU_ADD;
               end
            34:begin
                 Controle_ALU = `ALU_SUB;
               end
            36:begin
                 Controle_ALU = `ALU_AND;
               end
            38:begin
                 Controle_ALU = `ALU_XOR;
              end
            37:begin
                 Controle_ALU = `ALU_OR;
               end
            39:begin
                Controle_ALU = `ALU_NOR;
               end
            42:begin
                 Controle_ALU = `ALU_SLT;
               end
          endcase
          end
  endcase
  end
endmodule
module ControleALU (OpCode_ALU,Func_Code,Controle_ALU);

  input [1:0] OpCode_ALU;
  input [5:0]Func_Code;
  output reg [3:0]Controle_ALU;

  always @ ( OpCode_ALU or Func_Code ) begin
    case(OpCode_ALU)
       0: begin
          Controle_ALU = `ALU_ADD;
          end
       1: begin
         Controle_ALU = `ALU_SUB;
          end
       2: begin
            case (Func_Code)
            32:begin
                 Controle_ALU = `ALU_ADD;
               end
            34:begin
                 Controle_ALU = `ALU_SUB;
               end
            36:begin
                 Controle_ALU = `ALU_AND;
               end
            38:begin
                 Controle_ALU = `ALU_XOR;
              end
            37:begin
                 Controle_ALU = `ALU_OR;
               end
            39:begin
                Controle_ALU = `ALU_NOR;
               end
            42:begin
                 Controle_ALU = `ALU_SLT;
               end
          endcase
          end
  endcase
  end
endmodule