data/full_repos/permissive/18477150/testsuite/verilator_sim/gearbox/gb_66_40/sonic_gb_66_40_testbench.sv
1: b"%Error: data/full_repos/permissive/18477150/testsuite/verilator_sim/gearbox/gb_66_40/sonic_gb_66_40_testbench.sv:29: Cannot find file containing module: 'sonic_gearbox_66_40'\n   sonic_gearbox_66_40 gearbox (.data_in(data_in_delayed),\n   ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18477150/testsuite/verilator_sim/gearbox/gb_66_40,data/full_repos/permissive/18477150/sonic_gearbox_66_40\n             data/full_repos/permissive/18477150/testsuite/verilator_sim/gearbox/gb_66_40,data/full_repos/permissive/18477150/sonic_gearbox_66_40.v\n             data/full_repos/permissive/18477150/testsuite/verilator_sim/gearbox/gb_66_40,data/full_repos/permissive/18477150/sonic_gearbox_66_40.sv\n             sonic_gearbox_66_40\n             sonic_gearbox_66_40.v\n             sonic_gearbox_66_40.sv\n             obj_dir/sonic_gearbox_66_40\n             obj_dir/sonic_gearbox_66_40.v\n             obj_dir/sonic_gearbox_66_40.sv\n%Error: Exiting due to 1 error(s)\n"
module sonic_gb_66_40_testbench (

   data_out, rd_req_out,

   data_in, clk_in, reset, ena
   ) ;
   input [65:0] data_in;
   input 	clk_in;
   input 	reset;
   input 	ena;
   
   output [39:0] data_out;
   output 	 rd_req_out;

   logic [65:0]	 data_in_delayed;


   always @ (posedge clk_in) begin
      data_in_delayed <= data_in;
   end
      
   sonic_gearbox_66_40 gearbox (.data_in(data_in_delayed),
				.clk_in(clk_in),
				.reset(reset),
				.ena(ena),
				.data_out(data_out),
				.rd_req_out(rd_req_out)
				);
      
endmodule
module sonic_gb_66_40_testbench (

   data_out, rd_req_out,

   data_in, clk_in, reset, ena
   ) ;

   input [65:0] data_in;
   input 	clk_in;
   input 	reset;
   input 	ena;
   
   output [39:0] data_out;
   output 	 rd_req_out;

   logic [65:0]	 data_in_delayed;


   always @ (posedge clk_in) begin
      data_in_delayed <= data_in;
   end
      
   sonic_gearbox_66_40 gearbox (.data_in(data_in_delayed),
				.clk_in(clk_in),
				.reset(reset),
				.ena(ena),
				.data_out(data_out),
				.rd_req_out(rd_req_out)
				);
      
endmodule