data/full_repos/permissive/194847941/demo/12_game/sources/rtl/mcu/bus.v
1: b'%Warning-WIDTH: data/full_repos/permissive/194847941/demo/12_game/sources/rtl/mcu/bus.v:56: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'bus_wdata\' generates 8 bits.\n                                                                                          : ... In instance bus\n         0: led <= bus_wdata;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/194847941/demo/12_game/sources/rtl/mcu/bus.v:58: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'bus_wdata\' generates 8 bits.\n                                                                                          : ... In instance bus\n   2: vram_wdata <= bus_wdata;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/194847941/demo/12_game/sources/rtl/mcu/bus.v:70: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'led\' generates 1 bits.\n                                                                                          : ... In instance bus\n         0: bus_rdata <= led;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/194847941/demo/12_game/sources/rtl/mcu/bus.v:71: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'key\' generates 6 bits.\n                                                                                          : ... In instance bus\n   1: bus_rdata <= key;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/194847941/demo/12_game/sources/rtl/mcu/bus.v:72: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'vram_rdata\' generates 1 bits.\n                                                                                          : ... In instance bus\n   2: bus_rdata <= vram_rdata;\n                ^~\n%Error: Exiting due to 5 warning(s)\n'
module bus
(
    input   wire		clk,
    

	input	wire		bus_wen,
	input	wire [7:0]	bus_waddr,
	input	wire [7:0]	bus_wdata,
	

	input	wire		bus_ren,
	input	wire [7:0]	bus_raddr,
	output	reg  [7:0]	bus_rdata,
    


	output	reg			vram_wen,
	output	reg			vram_wdata,
	output	reg			vram_ren,
	input	wire		vram_rdata,
	output	reg [7:0]	vram_addr,
	

	input	wire [5:0]	key,
	output	reg			clear,
    output  reg			led
);


always@(posedge clk)
begin
    if(bus_wen)
    begin
        case(bus_waddr)
         0: led <= bus_wdata;
		 1: vram_addr <= bus_wdata;
		 2: vram_wdata <= bus_wdata;
		
        endcase
    end
end


always@(posedge clk)
begin
    if(bus_ren)
    begin
        case(bus_raddr)
         0: bus_rdata <= led;
		 1: bus_rdata <= key;
		 2: bus_rdata <= vram_rdata;
		 
		 
         default: bus_rdata <= 0;
        endcase
    end
end


always@(posedge clk)
begin
	clear <= bus_ren && (bus_raddr == 1);
	vram_ren <= bus_wen && (bus_waddr == 1);
	vram_wen <= bus_wen && (bus_waddr == 2);
end

endmodule
module bus
(
    input   wire		clk,
    

	input	wire		bus_wen,
	input	wire [7:0]	bus_waddr,
	input	wire [7:0]	bus_wdata,
	

	input	wire		bus_ren,
	input	wire [7:0]	bus_raddr,
	output	reg  [7:0]	bus_rdata,
    


	output	reg			vram_wen,
	output	reg			vram_wdata,
	output	reg			vram_ren,
	input	wire		vram_rdata,
	output	reg [7:0]	vram_addr,
	

	input	wire [5:0]	key,
	output	reg			clear,
    output  reg			led
);



always@(posedge clk)
begin
    if(bus_wen)
    begin
        case(bus_waddr)
         0: led <= bus_wdata;
		 1: vram_addr <= bus_wdata;
		 2: vram_wdata <= bus_wdata;
		
        endcase
    end
end


always@(posedge clk)
begin
    if(bus_ren)
    begin
        case(bus_raddr)
         0: bus_rdata <= led;
		 1: bus_rdata <= key;
		 2: bus_rdata <= vram_rdata;
		 
		 
         default: bus_rdata <= 0;
        endcase
    end
end


always@(posedge clk)
begin
	clear <= bus_ren && (bus_raddr == 1);
	vram_ren <= bus_wen && (bus_waddr == 1);
	vram_wen <= bus_wen && (bus_waddr == 2);
end

endmodule