data/full_repos/permissive/101171422/sim/trainsim.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #5 rst = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #1 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/trainsim.v:169: Unsupported: Ignoring delay on this delayed statement.\n initial forever #0.5 clk = !clk;\n                 ^\n%Warning-INFINITELOOP: data/full_repos/permissive/101171422/sim/trainsim.v:169: Infinite loop (condition always true)\n                                                                              : ... In instance trainsim_test\n initial forever #0.5 clk = !clk;\n         ^~~~~~~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module LFSR8_11D
(
	input wire       clk,
	output reg [7:0] LFSR = 255
);


	wire feedback = LFSR[7] ^ (LFSR[6:0] == 7'b0000000);

	always @(posedge clk) begin
		LFSR[0] <= feedback;
		LFSR[1] <= LFSR[0];
		LFSR[2] <= LFSR[1] ^ feedback;
		LFSR[3] <= LFSR[2] ^ feedback;
		LFSR[4] <= LFSR[3] ^ feedback;
		LFSR[5] <= LFSR[4];
		LFSR[6] <= LFSR[5];
		LFSR[7] <= LFSR[6];
	end
endmodule
module LFSR8_11D
(
	input wire       clk,
	output reg [7:0] LFSR = 255
);



	wire feedback = LFSR[7] ^ (LFSR[6:0] == 7'b0000000);

	always @(posedge clk) begin
		LFSR[0] <= feedback;
		LFSR[1] <= LFSR[0];
		LFSR[2] <= LFSR[1] ^ feedback;
		LFSR[3] <= LFSR[2] ^ feedback;
		LFSR[4] <= LFSR[3] ^ feedback;
		LFSR[5] <= LFSR[4];
		LFSR[6] <= LFSR[5];
		LFSR[7] <= LFSR[6];
	end
endmodule