data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v
 line:72: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:67: syntax error, unexpected \'@\'\n        @ (negedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:70: Unsupported: Ignoring delay on this delayed statement.\n        reset = 1; #(20); reset = 0;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #(7*20);  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:83: Unsupported: Ignoring delay on this delayed statement.\n            #(20);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:85: Unsupported: Ignoring delay on this delayed statement.\n        f_ack = 1; #(20); f_ack = 0;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:88: Unsupported: Ignoring delay on this delayed statement.\n            #(20);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:93: Unsupported: Ignoring delay on this delayed statement.\n        reset = 1; #(20); reset = 0;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #(4*20);  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:101: Unsupported: Ignoring delay on this delayed statement.\n            #(20);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:110: Unsupported: Ignoring delay on this delayed statement.\n        reset = 1; #(20); reset = 0;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:118: Unsupported: Ignoring delay on this delayed statement.\n            #(20);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:128: Unsupported: Ignoring delay on this delayed statement.\n        reset = 1; #(20); reset = 0;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:135: Unsupported: Ignoring delay on this delayed statement.\n            #(20);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:145: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:146: Unsupported: Ignoring delay on this delayed statement.\n        f_ack = 1; #(20); f_ack = 0;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:151: Unsupported: Ignoring delay on this delayed statement.\n            in = 64\'h1234567890ABCDEF; #(20);\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:155: Unsupported: Ignoring delay on this delayed statement.\n        in = 64\'h1234567890ABCDEF; #(20);\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:160: Unsupported: Ignoring delay on this delayed statement.\n        f_ack = 1; #(20); f_ack = 0;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:167: Unsupported: Ignoring delay on this delayed statement.\n            #(20);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/21918028/high_throughput_core/testbench/test_padder.v:175: Unsupported: Ignoring delay on this delayed statement.\n    always #(20/2) clk = ~ clk;\n           ^\n%Error: Exiting due to 1 error(s), 27 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_padder;


    reg clk;
    reg reset;
    reg [63:0] in;
    reg in_ready;
    reg is_last;
    reg [2:0] byte_num;
    reg f_ack;


    wire buffer_full;
    wire [575:0] out;
    wire out_ready;


    integer i;


    padder uut (
        .clk(clk),
        .reset(reset),
        .in(in),
        .in_ready(in_ready),
        .is_last(is_last),
        .byte_num(byte_num),
        .buffer_full(buffer_full),
        .out(out),
        .out_ready(out_ready),
        .f_ack(f_ack)
    );

    initial begin

        clk = 0;
        reset = 1;
        in = 0;
        in_ready = 0;
        is_last = 0;
        byte_num = 0;
        f_ack = 0;


        #100;


        @ (negedge clk);


        reset = 1; #(`P); reset = 0;
        #(7*`P);
        if (buffer_full !== 0) error;
        in_ready = 1;
        is_last = 1;
        #(`P);
        in_ready = 1;
        is_last = 1;
        #(`P);
        in_ready = 0;
        is_last = 0;

        while (out_ready !== 1)
            #(`P);
        check({8'h1, 560'h0, 8'h80});
        f_ack = 1; #(`P); f_ack = 0;
        for(i=0; i<5; i=i+1)
          begin
            #(`P);
            if (buffer_full !== 0) error;
          end


        reset = 1; #(`P); reset = 0;
        #(4*`P);
        in_ready = 1;
        byte_num = 7;
        is_last = 0;
        for (i=0; i<8; i=i+1)
          begin
            in = 64'h1234567890ABCDEF;
            #(`P);
          end
        is_last = 1;
        #(`P);
        in_ready = 0;
        is_last = 0;
        check({ {8{64'h1234567890ABCDEF}}, 64'h1234567890ABCD81 });


        reset = 1; #(`P); reset = 0;

        in_ready = 1;
        byte_num = 7;
        is_last = 0;
        for (i=0; i<8; i=i+1)
          begin
            in = 64'h1234567890ABCDEF;
            #(`P);
          end
        is_last = 1;
        byte_num = 0;
        #(`P);
        in_ready = 0;
        is_last = 0;
        check({ {8{64'h1234567890ABCDEF}}, 64'h0100000000000080 });


        reset = 1; #(`P); reset = 0;
        in_ready = 1;
        byte_num = 7;
        is_last = 0;
        for (i=0; i<9; i=i+1)
          begin
            in = 64'h1234567890ABCDEF;
            #(`P);
          end
        if (out_ready !== 1) error;
        check({9{64'h1234567890ABCDEF}});
        #(`P/2);
        if (buffer_full !== 1) error;
        #(`P/2);
        in = 64'h999;
        #(`P/2);
        if (buffer_full !== 1) error;
        #(`P/2);
        f_ack = 1; #(`P); f_ack = 0;
        if (out_ready !== 0) error;

        for (i=0; i<8; i=i+1)
          begin
            in = 64'h1234567890ABCDEF; #(`P);
          end
        byte_num = 6;
        is_last = 1;
        in = 64'h1234567890ABCDEF; #(`P);
        if (out_ready !== 1) error;
        check({ {8{64'h1234567890ABCDEF}}, 64'h1234567890AB0180 });
        is_last = 0;

        f_ack = 1; #(`P); f_ack = 0;

        in_ready = 0;
        is_last = 0;
        for (i=0; i<10; i=i+1)
          begin
            if (out_ready === 1) error;
            #(`P);
          end
        in_ready = 0;

        $display("Good!");
        $finish;
    end

    always #(`P/2) clk = ~ clk;

    task error;
        begin
              $display("E");
              $finish;
        end
    endtask

    task check;
        input [575:0] wish;
        begin
          if (out !== wish)
            begin
              $display("out:%h wish:%h", out, wish);
              error;
            end
        end
    endtask
endmodule
module test_padder;



    reg clk;
    reg reset;
    reg [63:0] in;
    reg in_ready;
    reg is_last;
    reg [2:0] byte_num;
    reg f_ack;


    wire buffer_full;
    wire [575:0] out;
    wire out_ready;


    integer i;


    padder uut (
        .clk(clk),
        .reset(reset),
        .in(in),
        .in_ready(in_ready),
        .is_last(is_last),
        .byte_num(byte_num),
        .buffer_full(buffer_full),
        .out(out),
        .out_ready(out_ready),
        .f_ack(f_ack)
    );

    initial begin

        clk = 0;
        reset = 1;
        in = 0;
        in_ready = 0;
        is_last = 0;
        byte_num = 0;
        f_ack = 0;


        #100;


        @ (negedge clk);


        reset = 1; #(`P); reset = 0;
        #(7*`P);
        if (buffer_full !== 0) error;
        in_ready = 1;
        is_last = 1;
        #(`P);
        in_ready = 1;
        is_last = 1;
        #(`P);
        in_ready = 0;
        is_last = 0;

        while (out_ready !== 1)
            #(`P);
        check({8'h1, 560'h0, 8'h80});
        f_ack = 1; #(`P); f_ack = 0;
        for(i=0; i<5; i=i+1)
          begin
            #(`P);
            if (buffer_full !== 0) error;
          end


        reset = 1; #(`P); reset = 0;
        #(4*`P);
        in_ready = 1;
        byte_num = 7;
        is_last = 0;
        for (i=0; i<8; i=i+1)
          begin
            in = 64'h1234567890ABCDEF;
            #(`P);
          end
        is_last = 1;
        #(`P);
        in_ready = 0;
        is_last = 0;
        check({ {8{64'h1234567890ABCDEF}}, 64'h1234567890ABCD81 });


        reset = 1; #(`P); reset = 0;

        in_ready = 1;
        byte_num = 7;
        is_last = 0;
        for (i=0; i<8; i=i+1)
          begin
            in = 64'h1234567890ABCDEF;
            #(`P);
          end
        is_last = 1;
        byte_num = 0;
        #(`P);
        in_ready = 0;
        is_last = 0;
        check({ {8{64'h1234567890ABCDEF}}, 64'h0100000000000080 });


        reset = 1; #(`P); reset = 0;
        in_ready = 1;
        byte_num = 7;
        is_last = 0;
        for (i=0; i<9; i=i+1)
          begin
            in = 64'h1234567890ABCDEF;
            #(`P);
          end
        if (out_ready !== 1) error;
        check({9{64'h1234567890ABCDEF}});
        #(`P/2);
        if (buffer_full !== 1) error;
        #(`P/2);
        in = 64'h999;
        #(`P/2);
        if (buffer_full !== 1) error;
        #(`P/2);
        f_ack = 1; #(`P); f_ack = 0;
        if (out_ready !== 0) error;

        for (i=0; i<8; i=i+1)
          begin
            in = 64'h1234567890ABCDEF; #(`P);
          end
        byte_num = 6;
        is_last = 1;
        in = 64'h1234567890ABCDEF; #(`P);
        if (out_ready !== 1) error;
        check({ {8{64'h1234567890ABCDEF}}, 64'h1234567890AB0180 });
        is_last = 0;

        f_ack = 1; #(`P); f_ack = 0;

        in_ready = 0;
        is_last = 0;
        for (i=0; i<10; i=i+1)
          begin
            if (out_ready === 1) error;
            #(`P);
          end
        in_ready = 0;

        $display("Good!");
        $finish;
    end

    always #(`P/2) clk = ~ clk;

    task error;
        begin
              $display("E");
              $finish;
        end
    endtask

    task check;
        input [575:0] wish;
        begin
          if (out !== wish)
            begin
              $display("out:%h wish:%h", out, wish);
              error;
            end
        end
    endtask
endmodule