data/full_repos/permissive/143278/ivltests/pr1570635b.v
data/verilator_xmls/e94cddf0-6323-4267-b3f3-abafc23a1edc.xml
module test;








reg [15:0] a, b, answer;

initial
  begin
    a = 16'h8000;
    b = 16'h8000;
    answer = (a + b + 0) >> 1;
    if ( answer != 16'h8000 )
      begin
          $display("FAILED -- expected 16'h8000  received 16'h%h", answer);
          $finish;
      end
    $display("PASSED");
  end

endmodule
module test;









reg [15:0] a, b, answer;

initial
  begin
    a = 16'h8000;
    b = 16'h8000;
    answer = (a + b + 0) >> 1;
    if ( answer != 16'h8000 )
      begin
          $display("FAILED -- expected 16'h8000  received 16'h%h", answer);
          $finish;
      end
    $display("PASSED");
  end

endmodule