data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/simplez_tb.v
 line:49: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/simplez_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/simplez_tb.v:44: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("simplez_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/simplez_tb.v:45: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, simplez_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/simplez_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #2 rstn <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/simplez_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  # 160 $display("FIN de la simulacion");\n  ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simplez_tb();


parameter ROMFILE = "prog.list";


parameter WAIT_DELAY = 20;


reg clk = 0;


wire [7:0] leds;
wire stop;
reg rstn = 0;
wire tx;


simplez #(.ROMFILE(ROMFILE), .WAIT_DELAY(WAIT_DELAY))
  dut(
    .clk(clk),
    .rstn_ini(rstn),
    .leds(leds),
    .stop(stop),
    .tx(tx)
  );


always #1 clk = ~clk;



initial begin


  $dumpfile("simplez_tb.vcd");
  $dumpvars(0, simplez_tb);

  #2 rstn <= 1;

  # 160 $display("FIN de la simulacion");
  $finish;
end

endmodule
module simplez_tb();



parameter ROMFILE = "prog.list";


parameter WAIT_DELAY = 20;


reg clk = 0;


wire [7:0] leds;
wire stop;
reg rstn = 0;
wire tx;


simplez #(.ROMFILE(ROMFILE), .WAIT_DELAY(WAIT_DELAY))
  dut(
    .clk(clk),
    .rstn_ini(rstn),
    .leds(leds),
    .stop(stop),
    .tx(tx)
  );


always #1 clk = ~clk;



initial begin


  $dumpfile("simplez_tb.vcd");
  $dumpvars(0, simplez_tb);

  #2 rstn <= 1;

  # 160 $display("FIN de la simulacion");
  $finish;
end

endmodule