data/full_repos/permissive/174783592/WallacePL/Wallace8BitPLTB.v
 line:40: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/174783592/WallacePL/Wallace8BitPLTB.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #75 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174783592/WallacePL/Wallace8BitPLTB.v:43: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk <= ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174783592/WallacePL/Wallace8BitPLTB.v:44: Unsupported: Ignoring delay on this delayed statement.\n always #5 a <= a + 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174783592/WallacePL/Wallace8BitPLTB.v:45: Unsupported: Ignoring delay on this delayed statement.\n always #5 b <= b + 1;\n        ^\n%Error: data/full_repos/permissive/174783592/WallacePL/Wallace8BitPLTB.v:47: Unsupported or unknown PLI call: $monitor\ninitial $monitor($time,"clk=%d a =%d  b=%d\\n u=%b,v=%b sumwire=%b lp=%b   p=%d ",clk,a,b,w.pl4u6,w.pl4v6,w.s1.sumwire,w.lp,p);\n        ^~~~~~~~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Wallace8BitPLTB();

	reg [7:0] a;
	reg [7:0] b;
	reg clk;
	wire[16:0] p;



	Wallace8BitPL w(a,b,p,clk);
	initial begin

		a <= {2{4'b1111}};
		b <= {2{4'b1111}};
		clk <= 0;
		#75 $finish;
	end

	always #5 clk <= ~clk;
	always #5 a <= a + 1;
	always #5 b <= b + 1;

initial	$monitor($time,"clk=%d a =%d  b=%d\n u=%b,v=%b sumwire=%b lp=%b   p=%d ",clk,a,b,w.pl4u6,w.pl4v6,w.s1.sumwire,w.lp,p);



	endmodule
module Wallace8BitPLTB();


	reg [7:0] a;
	reg [7:0] b;
	reg clk;
	wire[16:0] p;



	Wallace8BitPL w(a,b,p,clk);
	initial begin

		a <= {2{4'b1111}};
		b <= {2{4'b1111}};
		clk <= 0;
		#75 $finish;
	end

	always #5 clk <= ~clk;
	always #5 a <= a + 1;
	always #5 b <= b + 1;

initial	$monitor($time,"clk=%d a =%d  b=%d\n u=%b,v=%b sumwire=%b lp=%b   p=%d ",clk,a,b,w.pl4u6,w.pl4v6,w.s1.sumwire,w.lp,p);



	endmodule