data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v
 line:20: before: "i"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:7: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:26: Unsupported: Ignoring delay on this delayed statement.\n       #1 A = $random % MAX;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #1 A = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #1 A = 23\'h7fffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #1 B = 23\'h7fffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #1 B = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:37: Unsupported: Ignoring delay on this delayed statement.\n       #1 A = $random % MAX;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #1 A = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:43: Unsupported: Ignoring delay on this delayed statement.\n       #1 B = $random % MAX;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:49: Unsupported: Ignoring delay on this delayed statement.\n       #1 A = $random % MAX;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #40000;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:26: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                    : ... In instance test.stim\n       #1 A = $random % MAX;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:27: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                    : ... In instance test.stim\n          B = $random % MAX;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:37: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                    : ... In instance test.stim\n       #1 A = $random % MAX;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:43: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                    : ... In instance test.stim\n       #1 B = $random % MAX;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:49: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                    : ... In instance test.stim\n       #1 A = $random % MAX;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:50: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                    : ... In instance test.stim\n          B = $random % MAX;\n            ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_sdiv23_stdlogic.v:86: Cannot find file containing module: \'sdiv23\'\n  sdiv23       duv            (.a_i(a), .b_i(b), .c_o(r) );\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/sdiv23\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/sdiv23.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/sdiv23.sv\n             sdiv23\n             sdiv23.v\n             sdiv23.sv\n             obj_dir/sdiv23\n             obj_dir/sdiv23.v\n             obj_dir/sdiv23.sv\n%Error: Exiting due to 1 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  wire signed [22:0] a, b;
  wire signed [22:0] r;

  stimulus     stim           (.A(a), .B(b));
  sdiv23       duv            (.a_i(a), .b_i(b), .c_o(r) );
  check        check          (.a(a), .b(b), .c(r) );

  initial begin
    #40000;
    $display("PASSED");
    $finish;
  end

endmodule
module test;

  wire signed [22:0] a, b;
  wire signed [22:0] r;

  stimulus     stim           (.A(a), .B(b));
  sdiv23       duv            (.a_i(a), .b_i(b), .c_o(r) );
  check        check          (.a(a), .b(b), .c(r) );

  initial begin
    #40000;
    $display("PASSED");
    $finish;
  end

endmodule