data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v
None: at end of input
1: b'%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:2: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch,data/full_repos/permissive/180413071/constants.vh\n             data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch,data/full_repos/permissive/180413071/constants.vh.v\n             data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch,data/full_repos/permissive/180413071/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:3: Cannot find include file: files.vh\n`include "files.vh" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:6: Define or directive not defined: \'`INSTRUCTION_FILE\'\nmodule Fetch #(parameter PATH=`INSTRUCTION_FILE) (\n                              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:6: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule Fetch #(parameter PATH=`INSTRUCTION_FILE) (\n                                               ^\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:11: Define or directive not defined: \'`WORD\'\n    input  [`WORD-1:0]      branch_target,\n            ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:12: Define or directive not defined: \'`WORD\'\n    input  [`WORD-1:0]      alu_result,\n            ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:13: Define or directive not defined: \'`WORD\'\n    output [`WORD-1:0]      pc,\n            ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:14: Define or directive not defined: \'`WORD\'\n    output [`WORD-1:0]      incremented_pc,\n            ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:15: Define or directive not defined: \'`INSTR_LEN\'\n    output [`INSTR_LEN-1:0] instruction\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:18: Define or directive not defined: \'`WORD\'\n    wire [`WORD-1:0] new_pc;\n          ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:19: syntax error, unexpected assign\n    assign incremented_pc = reset ? 0 : (pc + `WORD\'d4);\n    ^~~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:19: Define or directive not defined: \'`WORD\'\n    assign incremented_pc = reset ? 0 : (pc + `WORD\'d4);\n                                              ^~~~~\n%Error: data/full_repos/permissive/180413071/nonpipelined/sources/hardware/fetch/Fetch.v:28: Define or directive not defined: \'`WORD\'\n    mux4 #(.SIZE(`WORD)) mux4_pc_source(\n                 ^~~~~\n%Error: Exiting due to 13 error(s)\n'
module Fetch #(parameter PATH=`INSTRUCTION_FILE) (
    input                   clk,
    input                   read_clk,
    input                   reset,
    input  [1:0]            pc_src,
    input  [`WORD-1:0]      branch_target,
    input  [`WORD-1:0]      alu_result,
    output [`WORD-1:0]      pc,
    output [`WORD-1:0]      incremented_pc,
    output [`INSTR_LEN-1:0] instruction
);

    wire [`WORD-1:0] new_pc;
    assign incremented_pc = reset ? 0 : (pc + `WORD'd4);
    
    register register_pc(
        .clk(clk),
        .reset(reset),
        .D(new_pc),
        .Q(pc)
    );
    
    mux4 #(.SIZE(`WORD)) mux4_pc_source(
        .a(incremented_pc),
        .b(branch_target),
        .c(alu_result),
        .d(pc),
        .control(pc_src),
        .out(new_pc)
    );
    
    instruction_mem #(.PATH(PATH)) instruction_mem(
        .clk(read_clk),
        .reset(reset),
        .address(pc),
        .instruction(instruction)
    );

endmodule
module Fetch #(parameter PATH=`INSTRUCTION_FILE) (
    input                   clk,
    input                   read_clk,
    input                   reset,
    input  [1:0]            pc_src,
    input  [`WORD-1:0]      branch_target,
    input  [`WORD-1:0]      alu_result,
    output [`WORD-1:0]      pc,
    output [`WORD-1:0]      incremented_pc,
    output [`INSTR_LEN-1:0] instruction
);


    wire [`WORD-1:0] new_pc;
    assign incremented_pc = reset ? 0 : (pc + `WORD'd4);
    
    register register_pc(
        .clk(clk),
        .reset(reset),
        .D(new_pc),
        .Q(pc)
    );
    
    mux4 #(.SIZE(`WORD)) mux4_pc_source(
        .a(incremented_pc),
        .b(branch_target),
        .c(alu_result),
        .d(pc),
        .control(pc_src),
        .out(new_pc)
    );
    
    instruction_mem #(.PATH(PATH)) instruction_mem(
        .clk(read_clk),
        .reset(reset),
        .address(pc),
        .instruction(instruction)
    );

endmodule