data/full_repos/permissive/117026779/src/Memory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/117026779/src/Memory.v:180: Multiple top level modules\n                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                        : ... Top module \'RAM\'\nmodule RAM #(\n       ^~~\n                                                                        : ... Top module \'ROM\'\nmodule ROM #(\n       ^~~\n                                                                        : ... Top module \'FIFO\'\nmodule FIFO #(\n       ^~~~\n                                                                        : ... Top module \'STACK\'\nmodule STACK #(\n       ^~~~~\n                                                                        : ... Top module \'SHIFTREGISTER\'\nmodule SHIFTREGISTER #(parameter WIDTH = 8)(\n       ^~~~~~~~~~~~~\n                                                                        : ... Top module \'REGISTER\'\nmodule REGISTER #(parameter WIDTH = 8)(\n       ^~~~~~~~\n                                                                        : ... Top module \'SHIFTLOADREG\'\nmodule SHIFTLOADREG #(parameter WIDTH = 8)(\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:366: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                     : ... In instance STACK\n        mem[write_position] = 0;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:384: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                     : ... In instance STACK\n            mem[write_position] = in;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:385: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'write_position\' generates 4 bits.\n                                                                     : ... In instance STACK\n            if(write_position == LENGTH-1)\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:399: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                     : ... In instance STACK\n            out = mem[read_position];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:400: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'read_position\' generates 4 bits.\n                                                                     : ... In instance STACK\n            if(read_position == LENGTH-1)\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:266: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                     : ... In instance FIFO\n        mem[write_position] = 0;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:285: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                     : ... In instance FIFO\n            mem[write_position] = in;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:286: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'write_position\' generates 4 bits.\n                                                                     : ... In instance FIFO\n            if(write_position == LENGTH-1)\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:300: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                     : ... In instance FIFO\n            out = mem[read_position];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:301: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'read_position\' generates 4 bits.\n                                                                     : ... In instance FIFO\n            if(read_position == LENGTH-1)\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:199: Bit extraction of array[4096:0] requires 13 bit index, not 12 bits.\n                                                                     : ... In instance ROM\nassign out = rom[a];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:199: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 33 bits.\n                                                                     : ... In instance ROM\nassign out = rom[a];\n           ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:121: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'we\' generates 4 bits.\n                                                                     : ... In instance RAM\nassign data = (cs && oe && !we) ? data_out : {(WIDTH){1\'bz}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:160: Bit extraction of array[4096:0] requires 13 bit index, not 12 bits.\n                                                                     : ... In instance RAM\n                memory_in[(MINIMUM_SECTIONAL_WIDTH*(c+1))-1 : MINIMUM_SECTIONAL_WIDTH*c] = ram[address][(MINIMUM_SECTIONAL_WIDTH*(c+1))-1 : MINIMUM_SECTIONAL_WIDTH*c];\n                                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:170: Bit extraction of array[4096:0] requires 13 bit index, not 12 bits.\n                                                                     : ... In instance RAM\n       ram[address] = memory_in;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/117026779/src/Memory.v:174: Bit extraction of array[4096:0] requires 13 bit index, not 12 bits.\n                                                                     : ... In instance RAM\n        data_out = ram[address];\n                      ^\n%Error: Exiting due to 17 warning(s)\n'
module SHIFTLOADREG #(parameter WIDTH = 8)(
	input wire rst,
	input wire clk,
    input wire load,
	input wire en,
	input wire in,
    input wire [WIDTH-1:0] D,
	output reg [WIDTH-1:0] Q
);

always @(posedge clk or posedge rst)
begin
    if (rst)
    begin
    	Q <= 0;
    end
    else if(load)
    begin
        Q <= D;
    end
    else if(en)
    begin
        Q <= { Q[WIDTH-2:0], in };
    end
end

endmodule
module SHIFTLOADREG #(parameter WIDTH = 8)(
	input wire rst,
	input wire clk,
    input wire load,
	input wire en,
	input wire in,
    input wire [WIDTH-1:0] D,
	output reg [WIDTH-1:0] Q
);


always @(posedge clk or posedge rst)
begin
    if (rst)
    begin
    	Q <= 0;
    end
    else if(load)
    begin
        Q <= D;
    end
    else if(en)
    begin
        Q <= { Q[WIDTH-2:0], in };
    end
end

endmodule