data/full_repos/permissive/143278/ivltests/sf1289.v
[Errno 2] No such file or directory: 'preprocess.output'
139: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sf1289.v:30: Unsupported: Ignoring delay on this delayed statement.\n   initial #100 $display("PASSED");\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/143278/ivltests/sf1289.v:9: Multiple top level modules\n                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                        : ... Top module \'test1\'\nmodule test1();   \n       ^~~~~\n                                                                        : ... Top module \'test2\'\nmodule test2();   \n       ^~~~~\n                                                                        : ... Top module \'test3\'\nmodule test3();   \n       ^~~~~\n                                                                        : ... Top module \'test4\'\nmodule test4();   \n       ^~~~~\n                                                                        : ... Top module \'stub\'\nSegmentation fault\n%Error: Command Failed /usr/bin/verilator_bin --xml-output data/verilator_xmls/428a94c3-e93c-41b1-a459-99444a8de736.xml --y data/full_repos/permissive/143278/ivltests\\,data/full_repos/permissive/143278 data/full_repos/permissive/143278/ivltests/sf1289.v\n'
module stub;
   initial #100 $display("PASSED");
endmodule
module stub;

   initial #100 $display("PASSED");
endmodule