data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:181: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:183: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:185: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:187: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:189: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:191: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:193: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:195: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:198: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:200: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:202: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:204: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:206: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:208: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:210: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:212: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:215: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:217: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:219: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:221: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:223: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:225: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:227: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:229: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:232: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:234: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:236: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:238: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:240: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:242: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:244: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:246: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:249: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:251: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:253: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:255: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:257: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:259: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:261: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:263: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:267: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:269: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:271: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:273: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:275: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:277: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:279: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:281: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:284: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:286: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:288: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:290: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:292: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:294: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:296: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:298: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:302: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:304: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:306: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:308: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:310: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:312: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:314: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:316: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:321: Unsupported: Ignoring delay on this delayed statement.\n always #500 clk = ~clk;    \n        ^\n%Error: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/mul_test.v:99: Cannot find file containing module: \'DiscreteCosineTransform\'\n DiscreteCosineTransform uut (\n ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/DiscreteCosineTransform\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/DiscreteCosineTransform.v\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/DiscreteCosineTransform.sv\n             DiscreteCosineTransform\n             DiscreteCosineTransform.v\n             DiscreteCosineTransform.sv\n             obj_dir/DiscreteCosineTransform\n             obj_dir/DiscreteCosineTransform.v\n             obj_dir/DiscreteCosineTransform.sv\n%Error: Exiting due to 1 error(s), 66 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mul_test;


	reg [15:0] datain;
	reg clk;
	reg reset;


	wire [31:0] D11_final;
	wire [31:0] D12_final;
	wire [31:0] D13_final;
	wire [31:0] D14_final;
	wire [31:0] D15_final;
	wire [31:0] D16_final;
	wire [31:0] D17_final;
	wire [31:0] D18_final;
	wire [31:0] D21_final;
	wire [31:0] D22_final;
	wire [31:0] D23_final;
	wire [31:0] D24_final;
	wire [31:0] D25_final;
	wire [31:0] D26_final;
	wire [31:0] D27_final;
	wire [31:0] D28_final;
	wire [31:0] D31_final;
	wire [31:0] D32_final;
	wire [31:0] D33_final;
	wire [31:0] D34_final;
	wire [31:0] D35_final;
	wire [31:0] D36_final;
	wire [31:0] D37_final;
	wire [31:0] D38_final;
	wire [31:0] D41_final;
	wire [31:0] D42_final;
	wire [31:0] D43_final;
	wire [31:0] D44_final;
	wire [31:0] D45_final;
	wire [31:0] D46_final;
	wire [31:0] D47_final;
	wire [31:0] D48_final;
	wire [31:0] D51_final;
	wire [31:0] D52_final;
	wire [31:0] D53_final;
	wire [31:0] D54_final;
	wire [31:0] D55_final;
	wire [31:0] D56_final;
	wire [31:0] D57_final;
	wire [31:0] D58_final;
	wire [31:0] D61_final;
	wire [31:0] D62_final;
	wire [31:0] D63_final;
	wire [31:0] D64_final;
	wire [31:0] D65_final;
	wire [31:0] D66_final;
	wire [31:0] D67_final;
	wire [31:0] D68_final;
	wire [31:0] D71_final;
	wire [31:0] D72_final;
	wire [31:0] D73_final;
	wire [31:0] D74_final;
	wire [31:0] D75_final;
	wire [31:0] D76_final;
	wire [31:0] D77_final;
	wire [31:0] D78_final;
	wire [31:0] D81_final;
	wire [31:0] D82_final;
	wire [31:0] D83_final;
	wire [31:0] D84_final;
	wire [31:0] D85_final;
	wire [31:0] D86_final;
	wire [31:0] D87_final;
	wire [31:0] D88_final;


	DiscreteCosineTransform uut (
		.D11_final(D11_final), 
		.D12_final(D12_final), 
		.D13_final(D13_final), 
		.D14_final(D14_final), 
		.D15_final(D15_final), 
		.D16_final(D16_final), 
		.D17_final(D17_final), 
		.D18_final(D18_final), 
		.D21_final(D21_final), 
		.D22_final(D22_final), 
		.D23_final(D23_final), 
		.D24_final(D24_final), 
		.D25_final(D25_final), 
		.D26_final(D26_final), 
		.D27_final(D27_final), 
		.D28_final(D28_final), 
		.D31_final(D31_final), 
		.D32_final(D32_final), 
		.D33_final(D33_final), 
		.D34_final(D34_final), 
		.D35_final(D35_final), 
		.D36_final(D36_final), 
		.D37_final(D37_final), 
		.D38_final(D38_final), 
		.D41_final(D41_final), 
		.D42_final(D42_final), 
		.D43_final(D43_final), 
		.D44_final(D44_final), 
		.D45_final(D45_final), 
		.D46_final(D46_final), 
		.D47_final(D47_final), 
		.D48_final(D48_final), 
		.D51_final(D51_final), 
		.D52_final(D52_final), 
		.D53_final(D53_final), 
		.D54_final(D54_final), 
		.D55_final(D55_final), 
		.D56_final(D56_final), 
		.D57_final(D57_final), 
		.D58_final(D58_final), 
		.D61_final(D61_final), 
		.D62_final(D62_final), 
		.D63_final(D63_final), 
		.D64_final(D64_final), 
		.D65_final(D65_final), 
		.D66_final(D66_final), 
		.D67_final(D67_final), 
		.D68_final(D68_final), 
		.D71_final(D71_final), 
		.D72_final(D72_final), 
		.D73_final(D73_final), 
		.D74_final(D74_final), 
		.D75_final(D75_final), 
		.D76_final(D76_final), 
		.D77_final(D77_final), 
		.D78_final(D78_final), 
		.D81_final(D81_final), 
		.D82_final(D82_final), 
		.D83_final(D83_final), 
		.D84_final(D84_final), 
		.D85_final(D85_final), 
		.D86_final(D86_final), 
		.D87_final(D87_final), 
		.D88_final(D88_final), 
		.datain(datain), 
		.clk(clk), 
		.reset(reset)
	);

	initial begin

		datain = 0;
		clk = 0;
		reset = 0;
		
		


		#100;
		
datain=16'b0001110000000000;
#1000;
datain=16'b0010000000000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0010000000000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0001111100000000;
#1000;

datain=16'b0001111100000000;
#1000;
datain=16'b0001101000000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001101000000000;
#1000;
datain=16'b0001100100000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001100100000000;
#1000;
datain=16'b0001111100000000;
#1000;

datain=16'b0001111000000000;
#1000;
datain=16'b0001110100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001110100000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001110100000000;
#1000;
datain=16'b0001110000000000;
#1000;

datain=16'b0001101100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001110100000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0001111000000000;
#1000;

datain=16'b0001111000000000;
#1000;
datain=16'b0001110100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001110100000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0001100100000000;
#1000;
datain=16'b0001110000000000;
#1000;


datain=16'b0001110000000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001111100000000;
#1000;

datain=16'b0001111100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0001100000000000;
#1000;
datain=16'b0001101000000000;
#1000;
datain=16'b0001110100000000;
#1000;


datain=16'b0001111000000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0010000100000000;
#1000;
        


	end
	always #500 clk = ~clk;    
      
endmodule
module mul_test;



	reg [15:0] datain;
	reg clk;
	reg reset;


	wire [31:0] D11_final;
	wire [31:0] D12_final;
	wire [31:0] D13_final;
	wire [31:0] D14_final;
	wire [31:0] D15_final;
	wire [31:0] D16_final;
	wire [31:0] D17_final;
	wire [31:0] D18_final;
	wire [31:0] D21_final;
	wire [31:0] D22_final;
	wire [31:0] D23_final;
	wire [31:0] D24_final;
	wire [31:0] D25_final;
	wire [31:0] D26_final;
	wire [31:0] D27_final;
	wire [31:0] D28_final;
	wire [31:0] D31_final;
	wire [31:0] D32_final;
	wire [31:0] D33_final;
	wire [31:0] D34_final;
	wire [31:0] D35_final;
	wire [31:0] D36_final;
	wire [31:0] D37_final;
	wire [31:0] D38_final;
	wire [31:0] D41_final;
	wire [31:0] D42_final;
	wire [31:0] D43_final;
	wire [31:0] D44_final;
	wire [31:0] D45_final;
	wire [31:0] D46_final;
	wire [31:0] D47_final;
	wire [31:0] D48_final;
	wire [31:0] D51_final;
	wire [31:0] D52_final;
	wire [31:0] D53_final;
	wire [31:0] D54_final;
	wire [31:0] D55_final;
	wire [31:0] D56_final;
	wire [31:0] D57_final;
	wire [31:0] D58_final;
	wire [31:0] D61_final;
	wire [31:0] D62_final;
	wire [31:0] D63_final;
	wire [31:0] D64_final;
	wire [31:0] D65_final;
	wire [31:0] D66_final;
	wire [31:0] D67_final;
	wire [31:0] D68_final;
	wire [31:0] D71_final;
	wire [31:0] D72_final;
	wire [31:0] D73_final;
	wire [31:0] D74_final;
	wire [31:0] D75_final;
	wire [31:0] D76_final;
	wire [31:0] D77_final;
	wire [31:0] D78_final;
	wire [31:0] D81_final;
	wire [31:0] D82_final;
	wire [31:0] D83_final;
	wire [31:0] D84_final;
	wire [31:0] D85_final;
	wire [31:0] D86_final;
	wire [31:0] D87_final;
	wire [31:0] D88_final;


	DiscreteCosineTransform uut (
		.D11_final(D11_final), 
		.D12_final(D12_final), 
		.D13_final(D13_final), 
		.D14_final(D14_final), 
		.D15_final(D15_final), 
		.D16_final(D16_final), 
		.D17_final(D17_final), 
		.D18_final(D18_final), 
		.D21_final(D21_final), 
		.D22_final(D22_final), 
		.D23_final(D23_final), 
		.D24_final(D24_final), 
		.D25_final(D25_final), 
		.D26_final(D26_final), 
		.D27_final(D27_final), 
		.D28_final(D28_final), 
		.D31_final(D31_final), 
		.D32_final(D32_final), 
		.D33_final(D33_final), 
		.D34_final(D34_final), 
		.D35_final(D35_final), 
		.D36_final(D36_final), 
		.D37_final(D37_final), 
		.D38_final(D38_final), 
		.D41_final(D41_final), 
		.D42_final(D42_final), 
		.D43_final(D43_final), 
		.D44_final(D44_final), 
		.D45_final(D45_final), 
		.D46_final(D46_final), 
		.D47_final(D47_final), 
		.D48_final(D48_final), 
		.D51_final(D51_final), 
		.D52_final(D52_final), 
		.D53_final(D53_final), 
		.D54_final(D54_final), 
		.D55_final(D55_final), 
		.D56_final(D56_final), 
		.D57_final(D57_final), 
		.D58_final(D58_final), 
		.D61_final(D61_final), 
		.D62_final(D62_final), 
		.D63_final(D63_final), 
		.D64_final(D64_final), 
		.D65_final(D65_final), 
		.D66_final(D66_final), 
		.D67_final(D67_final), 
		.D68_final(D68_final), 
		.D71_final(D71_final), 
		.D72_final(D72_final), 
		.D73_final(D73_final), 
		.D74_final(D74_final), 
		.D75_final(D75_final), 
		.D76_final(D76_final), 
		.D77_final(D77_final), 
		.D78_final(D78_final), 
		.D81_final(D81_final), 
		.D82_final(D82_final), 
		.D83_final(D83_final), 
		.D84_final(D84_final), 
		.D85_final(D85_final), 
		.D86_final(D86_final), 
		.D87_final(D87_final), 
		.D88_final(D88_final), 
		.datain(datain), 
		.clk(clk), 
		.reset(reset)
	);

	initial begin

		datain = 0;
		clk = 0;
		reset = 0;
		
		


		#100;
		
datain=16'b0001110000000000;
#1000;
datain=16'b0010000000000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0010000000000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0001111100000000;
#1000;

datain=16'b0001111100000000;
#1000;
datain=16'b0001101000000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001101000000000;
#1000;
datain=16'b0001100100000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001100100000000;
#1000;
datain=16'b0001111100000000;
#1000;

datain=16'b0001111000000000;
#1000;
datain=16'b0001110100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001110100000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001110100000000;
#1000;
datain=16'b0001110000000000;
#1000;

datain=16'b0001101100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001110100000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0001111000000000;
#1000;

datain=16'b0001111000000000;
#1000;
datain=16'b0001110100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001110100000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0001100100000000;
#1000;
datain=16'b0001110000000000;
#1000;


datain=16'b0001110000000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001111100000000;
#1000;

datain=16'b0001111100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001111100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001110000000000;
#1000;
datain=16'b0001100000000000;
#1000;
datain=16'b0001101000000000;
#1000;
datain=16'b0001110100000000;
#1000;


datain=16'b0001111000000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0001111000000000;
#1000;
datain=16'b0001101100000000;
#1000;
datain=16'b0010000100000000;
#1000;
        


	end
	always #500 clk = ~clk;    
      
endmodule