data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v
1: b'%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:51: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v.v\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:53: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:83: Define or directive not defined: \'`OR1200_MULTICYCLE_WIDTH\'\ninput [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:84: Define or directive not defined: \'`OR1200_WAIT_ON_WIDTH\'\n                                                                            : ... Suggested alternative: \'`OR1200_WAIT_IC\'\ninput   [`OR1200_WAIT_ON_WIDTH-1:0]  wait_on;   \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:109: Define or directive not defined: \'`OR1200_MULTICYCLE_WIDTH\'\nreg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt;\n     ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:111: Define or directive not defined: \'`OR1200_WAIT_ON_WIDTH\'\n                                                                             : ... Suggested alternative: \'`OR1200_WAIT_IC\'\nreg [`OR1200_WAIT_ON_WIDTH-1:0] waiting_on;\n     ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:142: Define or directive not defined: \'`OR1200_RST_EVENT\'\nalways @(posedge clk or `OR1200_RST_EVENT rst)\n                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:143: Define or directive not defined: \'`OR1200_RST_VALUE\'\n if (rst == `OR1200_RST_VALUE)\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:143: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `OR1200_RST_VALUE)\n                             ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:159: Define or directive not defined: \'`OR1200_RST_EVENT\'\nalways @(posedge clk or `OR1200_RST_EVENT rst)\n                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:160: Define or directive not defined: \'`OR1200_RST_VALUE\'\n if (rst == `OR1200_RST_VALUE)\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:160: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `OR1200_RST_VALUE)\n                             ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:161: Define or directive not defined: \'`OR1200_MULTICYCLE_WIDTH\'\n  multicycle_cnt <=  `OR1200_MULTICYCLE_WIDTH\'d0;\n                     ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:163: Define or directive not defined: \'`OR1200_MULTICYCLE_WIDTH\'\n  multicycle_cnt <=  multicycle_cnt - `OR1200_MULTICYCLE_WIDTH\'d1;\n                                      ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:171: Define or directive not defined: \'`OR1200_RST_EVENT\'\nalways @(posedge clk or `OR1200_RST_EVENT rst)\n                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:172: Define or directive not defined: \'`OR1200_RST_VALUE\'\n  if (rst == `OR1200_RST_VALUE)\n             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:172: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if (rst == `OR1200_RST_VALUE)\n                              ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:174: Define or directive not defined: \'`OR1200_WAIT_ON_MULTMAC\'\n  else if ((waiting_on == `OR1200_WAIT_ON_MULTMAC) & !mac_stall)\n                          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:176: Define or directive not defined: \'`OR1200_WAIT_ON_FPU\'\n                                                                             : ... Suggested alternative: \'`OR1200_WAIT_IC\'\n  else if ((waiting_on == `OR1200_WAIT_ON_FPU) & fpu_done)\n                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_freeze.v:178: Define or directive not defined: \'`OR1200_WAIT_ON_MTSPR\'\n  else if ((waiting_on == `OR1200_WAIT_ON_MTSPR) & mtspr_done)\n                          ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 20 error(s)\n'
module or1200_freeze
  (

   clk, rst,
   

   multicycle, wait_on, flushpipe, extend_flush, lsu_stall, if_stall,
   lsu_unstall, du_stall, mac_stall, 
   force_dslot_fetch, abort_ex,
   genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze, saving_if_insn,
   fpu_done, mtspr_done,
   icpu_ack_i, icpu_err_i
   );




input				clk;
input				rst;
input	[`OR1200_MULTICYCLE_WIDTH-1:0]	multicycle;
input   [`OR1200_WAIT_ON_WIDTH-1:0] 	wait_on;   
input				flushpipe;
input				extend_flush;
input				lsu_stall;
input				if_stall;
input				lsu_unstall;
input				force_dslot_fetch;
input				abort_ex;
input				du_stall;
input				mac_stall;
output				genpc_freeze;
output				if_freeze;
output				id_freeze;
output				ex_freeze;
output				wb_freeze;
input                           saving_if_insn;
input   			fpu_done;
input   			mtspr_done;   
input				icpu_ack_i;
input				icpu_err_i;




wire				multicycle_freeze;
reg	[`OR1200_MULTICYCLE_WIDTH-1:0]	multicycle_cnt;
reg				flushpipe_r;
reg [`OR1200_WAIT_ON_WIDTH-1:0]	waiting_on;
   
















assign genpc_freeze = (du_stall & !saving_if_insn) | flushpipe_r;
assign if_freeze = id_freeze | extend_flush;

assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze 
		    | (|waiting_on) | force_dslot_fetch) | du_stall;
assign ex_freeze = wb_freeze;

assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze 
		    | (|waiting_on)) | du_stall | abort_ex;




always @(posedge clk or `OR1200_RST_EVENT rst)
	if (rst == `OR1200_RST_VALUE)
		flushpipe_r <=  1'b0;
	else if (icpu_ack_i | icpu_err_i)

		flushpipe_r <=  flushpipe;
	else if (!flushpipe)
		flushpipe_r <=  1'b0;
		



assign multicycle_freeze = |multicycle_cnt;




always @(posedge clk or `OR1200_RST_EVENT rst)
	if (rst == `OR1200_RST_VALUE)
		multicycle_cnt <=  `OR1200_MULTICYCLE_WIDTH'd0;
	else if (|multicycle_cnt)
		multicycle_cnt <=  multicycle_cnt - `OR1200_MULTICYCLE_WIDTH'd1;
	else if (|multicycle & !ex_freeze)
		multicycle_cnt <=  multicycle;





always @(posedge clk or `OR1200_RST_EVENT rst)
  if (rst == `OR1200_RST_VALUE)
    waiting_on <= 0;
  else if ((waiting_on == `OR1200_WAIT_ON_MULTMAC) & !mac_stall)
    waiting_on <= 0;   
  else if ((waiting_on == `OR1200_WAIT_ON_FPU) & fpu_done)
    waiting_on <= 0;
  else if ((waiting_on == `OR1200_WAIT_ON_MTSPR) & mtspr_done)
    waiting_on <= 0;
  else if (!ex_freeze)
    waiting_on <= wait_on;
   
	   
endmodule
module or1200_freeze
  (

   clk, rst,
   

   multicycle, wait_on, flushpipe, extend_flush, lsu_stall, if_stall,
   lsu_unstall, du_stall, mac_stall, 
   force_dslot_fetch, abort_ex,
   genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze, saving_if_insn,
   fpu_done, mtspr_done,
   icpu_ack_i, icpu_err_i
   );





input				clk;
input				rst;
input	[`OR1200_MULTICYCLE_WIDTH-1:0]	multicycle;
input   [`OR1200_WAIT_ON_WIDTH-1:0] 	wait_on;   
input				flushpipe;
input				extend_flush;
input				lsu_stall;
input				if_stall;
input				lsu_unstall;
input				force_dslot_fetch;
input				abort_ex;
input				du_stall;
input				mac_stall;
output				genpc_freeze;
output				if_freeze;
output				id_freeze;
output				ex_freeze;
output				wb_freeze;
input                           saving_if_insn;
input   			fpu_done;
input   			mtspr_done;   
input				icpu_ack_i;
input				icpu_err_i;




wire				multicycle_freeze;
reg	[`OR1200_MULTICYCLE_WIDTH-1:0]	multicycle_cnt;
reg				flushpipe_r;
reg [`OR1200_WAIT_ON_WIDTH-1:0]	waiting_on;
   
















assign genpc_freeze = (du_stall & !saving_if_insn) | flushpipe_r;
assign if_freeze = id_freeze | extend_flush;

assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze 
		    | (|waiting_on) | force_dslot_fetch) | du_stall;
assign ex_freeze = wb_freeze;

assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze 
		    | (|waiting_on)) | du_stall | abort_ex;




always @(posedge clk or `OR1200_RST_EVENT rst)
	if (rst == `OR1200_RST_VALUE)
		flushpipe_r <=  1'b0;
	else if (icpu_ack_i | icpu_err_i)

		flushpipe_r <=  flushpipe;
	else if (!flushpipe)
		flushpipe_r <=  1'b0;
		



assign multicycle_freeze = |multicycle_cnt;




always @(posedge clk or `OR1200_RST_EVENT rst)
	if (rst == `OR1200_RST_VALUE)
		multicycle_cnt <=  `OR1200_MULTICYCLE_WIDTH'd0;
	else if (|multicycle_cnt)
		multicycle_cnt <=  multicycle_cnt - `OR1200_MULTICYCLE_WIDTH'd1;
	else if (|multicycle & !ex_freeze)
		multicycle_cnt <=  multicycle;





always @(posedge clk or `OR1200_RST_EVENT rst)
  if (rst == `OR1200_RST_VALUE)
    waiting_on <= 0;
  else if ((waiting_on == `OR1200_WAIT_ON_MULTMAC) & !mac_stall)
    waiting_on <= 0;   
  else if ((waiting_on == `OR1200_WAIT_ON_FPU) & fpu_done)
    waiting_on <= 0;
  else if ((waiting_on == `OR1200_WAIT_ON_MTSPR) & mtspr_done)
    waiting_on <= 0;
  else if (!ex_freeze)
    waiting_on <= wait_on;
   
	   
endmodule