data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog/seg_instruction_fetch.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog/seg_instruction_fetch.v:94: Cannot find file containing module: 'mem_instruction'\n    mem_instruction #(\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog,data/full_repos/permissive/206437232/mem_instruction\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog,data/full_repos/permissive/206437232/mem_instruction.v\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Verilog,data/full_repos/permissive/206437232/mem_instruction.sv\n             mem_instruction\n             mem_instruction.v\n             mem_instruction.sv\n             obj_dir/mem_instruction\n             obj_dir/mem_instruction.v\n             obj_dir/mem_instruction.sv\n%Error: Exiting due to 1 error(s)\n"
module seg_instruction_fetch
    #( parameter
        LEN                     = 32,

        RAM_WIDTH_PROGRAM       = 32,
        RAM_DEPTH_PROGRAM       = 2048,
        RAM_PERFORMANCE_PROGRAM = "LOW_LATENCY",
        INIT_FILE_PROGRAM       = ""
    )
    (

        input wire                          i_clk,
        input wire                          i_rst,
        input wire  [LEN - 1 : 0]           i_PC_branch,
        input wire  [LEN - 1 : 0]           i_PC_dir_jump,
        input wire                          i_PCSrc,
        input wire                          i_jump,
        input wire                          i_stall_flag,
        input wire                          i_preload_flag,
        input wire  [LEN - 1 : 0]           i_preload_address,
        input wire  [LEN - 1 : 0]           i_preload_instruction,
        input wire                          i_enable_pipeline,

        output wire [LEN - 1 : 0]           o_instruction,
        output wire [LEN - 1 : 0]           o_PC
    );
    

    wire [LEN - 1 : 0]  mem_address;
    wire                ena;
    wire                rsta;
    wire                regcea;
    wire                halt_flag;


    reg [LEN - 1 : 0]   reg_PC = {LEN{1'b0}};
    reg [LEN - 1 : 0]   reg_PC_aumentado;
    

    assign ena      = 1;
    assign rsta     = 0;
    assign regcea   = 1;
    





























    always @(posedge i_clk) begin
        if (!i_rst) begin
            reg_PC <= {LEN{1'b0}};
        end else if (i_enable_pipeline && !halt_flag) begin
            reg_PC <= mem_address + 1;
        end else begin
            reg_PC <= mem_address;
        end
    end

    assign mem_address = (i_preload_flag) ? i_preload_address :
                         (i_PCSrc) ? i_PC_branch :
                         (i_jump) ? i_PC_dir_jump :
                         (i_stall_flag) ? reg_PC - 1 :
                         reg_PC;

    assign o_PC = reg_PC;


    mem_instruction #(
        .RAM_WIDTH          (RAM_WIDTH_PROGRAM),
        .RAM_DEPTH          (RAM_DEPTH_PROGRAM),
        .RAM_PERFORMANCE    (RAM_PERFORMANCE_PROGRAM),
        .INIT_FILE          (INIT_FILE_PROGRAM)
    )
    u_mem_instruction
    (
        .i_addr     (mem_address),
        .i_dina     (i_preload_instruction),
        .i_clk      (i_clk),
        .i_wea      (i_preload_flag),
        .i_ena      (ena),
        .i_rsta     (rsta),
        .i_regcea   (regcea),
        .o_data     (o_instruction),
        .o_halt     (halt_flag)
    );

endmodule
module seg_instruction_fetch
    #( parameter
        LEN                     = 32,

        RAM_WIDTH_PROGRAM       = 32,
        RAM_DEPTH_PROGRAM       = 2048,
        RAM_PERFORMANCE_PROGRAM = "LOW_LATENCY",
        INIT_FILE_PROGRAM       = ""
    )
    (

        input wire                          i_clk,
        input wire                          i_rst,
        input wire  [LEN - 1 : 0]           i_PC_branch,
        input wire  [LEN - 1 : 0]           i_PC_dir_jump,
        input wire                          i_PCSrc,
        input wire                          i_jump,
        input wire                          i_stall_flag,
        input wire                          i_preload_flag,
        input wire  [LEN - 1 : 0]           i_preload_address,
        input wire  [LEN - 1 : 0]           i_preload_instruction,
        input wire                          i_enable_pipeline,

        output wire [LEN - 1 : 0]           o_instruction,
        output wire [LEN - 1 : 0]           o_PC
    );

    

    wire [LEN - 1 : 0]  mem_address;
    wire                ena;
    wire                rsta;
    wire                regcea;
    wire                halt_flag;


    reg [LEN - 1 : 0]   reg_PC = {LEN{1'b0}};
    reg [LEN - 1 : 0]   reg_PC_aumentado;
    

    assign ena      = 1;
    assign rsta     = 0;
    assign regcea   = 1;
    





























    always @(posedge i_clk) begin
        if (!i_rst) begin
            reg_PC <= {LEN{1'b0}};
        end else if (i_enable_pipeline && !halt_flag) begin
            reg_PC <= mem_address + 1;
        end else begin
            reg_PC <= mem_address;
        end
    end

    assign mem_address = (i_preload_flag) ? i_preload_address :
                         (i_PCSrc) ? i_PC_branch :
                         (i_jump) ? i_PC_dir_jump :
                         (i_stall_flag) ? reg_PC - 1 :
                         reg_PC;

    assign o_PC = reg_PC;


    mem_instruction #(
        .RAM_WIDTH          (RAM_WIDTH_PROGRAM),
        .RAM_DEPTH          (RAM_DEPTH_PROGRAM),
        .RAM_PERFORMANCE    (RAM_PERFORMANCE_PROGRAM),
        .INIT_FILE          (INIT_FILE_PROGRAM)
    )
    u_mem_instruction
    (
        .i_addr     (mem_address),
        .i_dina     (i_preload_instruction),
        .i_clk      (i_clk),
        .i_wea      (i_preload_flag),
        .i_ena      (ena),
        .i_rsta     (rsta),
        .i_regcea   (regcea),
        .o_data     (o_instruction),
        .o_halt     (halt_flag)
    );

endmodule