data/full_repos/permissive/179947554/simplecpu.v
 line:177: before: "$"
1: b'%Error: data/full_repos/permissive/179947554/simplecpu.v:174: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/179947554/simplecpu.v:175: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, icarus_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/179947554/simplecpu.v:177: Unsupported: Ignoring delay on this delayed statement.\n    #60 $finish;       \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/179947554/simplecpu.v:182: Unsupported: Ignoring delay on this delayed statement.\n    #1 i_clk = ~i_clk;   \n    ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simplecpu (i_clk);
  input i_clk;

  wire [7:0] databus;
  wire [7:0] addressbus;
  wire [7:0] Memvalue;
  wire [7:0] Xvalue;
  wire [7:0] ARvalue;
  wire [7:0] IRvalue;
  wire [7:0] PCvalue;
  wire [7:0] uSeqvalue;
  wire [7:0] Decodevalue;


  wire	     PCload;
  wire	     Xload;
  wire	     IRload;
  wire	     ARload;
  wire	     ARena;
  wire	     Xena;
  wire	     uSreset;
  wire	     PCincr;


  assign addressbus= ARena ? ARvalue : PCvalue;
  assign databus=    Xena  ? Xvalue  : Memvalue;


  register  Xreg(i_clk, Xload,  databus, Xvalue);
  register IRreg(i_clk, IRload, databus, IRvalue);
  register ARreg(i_clk, ARload, databus, ARvalue);



  counter uSeq(i_clk, uSreset, 1'b1,   8'h00,   uSeqvalue);
  counter   PC(i_clk, PCload,  PCincr, ARvalue, PCvalue);

  memory #(.filename("rom.hex"))
	 ROM(i_clk, Xena, addressbus, databus, Memvalue);
  memory #(.filename("decode.hex"))
	 Decode(i_clk, 1'b0, {IRvalue[3:0],uSeqvalue[3:0]}, 8'h00, Decodevalue);



  assign PCincr=  Decodevalue[7];
  assign uSreset= Decodevalue[6];
  assign Xena=    Decodevalue[5];
  assign ARena=   Decodevalue[4];
  assign ARload=  Decodevalue[3];
  assign IRload=  Decodevalue[2];
  assign Xload=   Decodevalue[1];
  assign PCload=  Decodevalue[0];

endmodule
module simplecpu (i_clk);

  input i_clk;

  wire [7:0] databus;
  wire [7:0] addressbus;
  wire [7:0] Memvalue;
  wire [7:0] Xvalue;
  wire [7:0] ARvalue;
  wire [7:0] IRvalue;
  wire [7:0] PCvalue;
  wire [7:0] uSeqvalue;
  wire [7:0] Decodevalue;


  wire	     PCload;
  wire	     Xload;
  wire	     IRload;
  wire	     ARload;
  wire	     ARena;
  wire	     Xena;
  wire	     uSreset;
  wire	     PCincr;


  assign addressbus= ARena ? ARvalue : PCvalue;
  assign databus=    Xena  ? Xvalue  : Memvalue;


  register  Xreg(i_clk, Xload,  databus, Xvalue);
  register IRreg(i_clk, IRload, databus, IRvalue);
  register ARreg(i_clk, ARload, databus, ARvalue);



  counter uSeq(i_clk, uSreset, 1'b1,   8'h00,   uSeqvalue);
  counter   PC(i_clk, PCload,  PCincr, ARvalue, PCvalue);

  memory #(.filename("rom.hex"))
	 ROM(i_clk, Xena, addressbus, databus, Memvalue);
  memory #(.filename("decode.hex"))
	 Decode(i_clk, 1'b0, {IRvalue[3:0],uSeqvalue[3:0]}, 8'h00, Decodevalue);



  assign PCincr=  Decodevalue[7];
  assign uSreset= Decodevalue[6];
  assign Xena=    Decodevalue[5];
  assign ARena=   Decodevalue[4];
  assign ARload=  Decodevalue[3];
  assign IRload=  Decodevalue[2];
  assign Xload=   Decodevalue[1];
  assign PCload=  Decodevalue[0];

endmodule