data/full_repos/permissive/165160692/04.FPGA/5932_00_153_194/hdl/5932_74HC194.v
None: at end of input
1: b'%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_00_153_194/hdl/5932_74HC194.v:4: Little bit endian vector: MSB < LSB of bit range: 0:3\ninput[1:0]S;input[0:3]D;\n                 ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_00_153_194/hdl/5932_74HC194.v:5: Little bit endian vector: MSB < LSB of bit range: 0:3\noutput [0:3]Q;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_00_153_194/hdl/5932_74HC194.v:6: Little bit endian vector: MSB < LSB of bit range: 0:3\nreg [0:3]QAUX;\n    ^\n%Error: Exiting due to 3 warning(s)\n'
module HC194(MR,S,CP,DSR,DSL,D,Q);
input MR,CP,DSR,DSL;
input[1:0]S;input[0:3]D;
output [0:3]Q;
reg [0:3]QAUX;

always@(negedge MR or posedge CP)
 begin
  if(!MR)QAUX=0;
  else if(S==2'b00)QAUX<=QAUX;
  else if(S==2'b01)QAUX={DSR,QAUX[1:3]};
  else if(S==2'b10)QAUX={QAUX[0:2],DSL};
  else if(S==2'b11)QAUX=D;
 end
assign Q=QAUX;
endmodule
module HC194(MR,S,CP,DSR,DSL,D,Q);

input MR,CP,DSR,DSL;
input[1:0]S;input[0:3]D;
output [0:3]Q;
reg [0:3]QAUX;

always@(negedge MR or posedge CP)
 begin
  if(!MR)QAUX=0;
  else if(S==2'b00)QAUX<=QAUX;
  else if(S==2'b01)QAUX={DSR,QAUX[1:3]};
  else if(S==2'b10)QAUX={QAUX[0:2],DSL};
  else if(S==2'b11)QAUX=D;
 end
assign Q=QAUX;
endmodule