data/full_repos/permissive/172602559/FPGA_Lab_2-Arithmetic_Circuit/lab2.v
 line:1: before: "~"
1: b"%Error: data/full_repos/permissive/172602559/FPGA_Lab_2-Arithmetic_Circuit/lab2.v:1: syntax error, unexpected '~', expecting '['\nmodule mux2_M0(W0,~A,S1);\n                  ^\n%Error: data/full_repos/permissive/172602559/FPGA_Lab_2-Arithmetic_Circuit/lab2.v:17: syntax error, unexpected '~', expecting '['\nmodule mux4(W1,A,~A,O,S0,S1);\n                 ^\n%Error: data/full_repos/permissive/172602559/FPGA_Lab_2-Arithmetic_Circuit/lab2.v:26: syntax error, unexpected '~', expecting '['\nmodule mux2_M2(W2, B, ~B, S0);\n                      ^\n%Error: data/full_repos/permissive/172602559/FPGA_Lab_2-Arithmetic_Circuit/lab2.v:50: syntax error, unexpected input, expecting ';'\ninput [3:0] W1, W2, CIN;\n^~~~~\n%Error: data/full_repos/permissive/172602559/FPGA_Lab_2-Arithmetic_Circuit/lab2.v:54: syntax error, unexpected IDENTIFIER\nAdd_half1(W3, W4, W1, W2);\n^~~~~~~~~\n%Error: data/full_repos/permissive/172602559/FPGA_Lab_2-Arithmetic_Circuit/lab2.v:70: syntax error, unexpected '(', expecting IDENTIFIER\nfull_add(F, CO, W1, W2, CIN);\n         ^\n%Error: Exiting due to 6 error(s)\n"
module mux2_M0(W0,~A,S1);
input S1;
input[3:0] ~A;
output[3:0] W0;
assign W0 = S1 ? ~A:0;

endmodule
module mux2_M0(W0,~A,S1);

input S1;
input[3:0] ~A;
output[3:0] W0;
assign W0 = S1 ? ~A:0;

endmodule