data/full_repos/permissive/106408053/verilog/clockman.v
1: b"%Error: data/full_repos/permissive/106408053/verilog/clockman.v:35: Cannot find file containing module: 'DCM_SP'\nDCM_SP #(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/DCM_SP\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/DCM_SP.v\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/DCM_SP.sv\n             DCM_SP\n             DCM_SP.v\n             DCM_SP.sv\n             obj_dir/DCM_SP\n             obj_dir/DCM_SP.v\n             obj_dir/DCM_SP.sv\n%Error: data/full_repos/permissive/106408053/verilog/clockman.v:60: Cannot find file containing module: 'BUFG'\n  BUFG BUFG_clkfb(.I(clkfb), .O(clkfbbuf));\n  ^~~~\n%Error: Exiting due to 2 error(s)\n"
module pll_wrapper (clkin, clk0);
input clkin;
output clk0;

parameter TRUE = 1'b1;
parameter FALSE = 1'b0;

wire clkin;
wire clk0;

wire clkfb; 
wire clkfbbuf; 

DCM_SP #(
  .CLKDV_DIVIDE(2.0),
  .CLKFX_DIVIDE(8),
  .CLKFX_MULTIPLY(25),
  .CLKIN_DIVIDE_BY_2("FALSE"),
  .CLKIN_PERIOD(31.250),
  .CLKOUT_PHASE_SHIFT("NONE"),
  .CLK_FEEDBACK("1X"),
  .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
  .DLL_FREQUENCY_MODE("LOW"),
  .DFS_FREQUENCY_MODE("LOW"),
  .DUTY_CYCLE_CORRECTION("TRUE"),
  .PHASE_SHIFT(0),
  .STARTUP_WAIT("FALSE")
  ) DCM_baseClock (
  .CLK0(clkfb),
  .CLKFX(clk0),
  .CLKFB(clkfbbuf),
  .CLKIN(clkin),
  .PSCLK(1'b0),
  .PSEN(1'b0),
  .PSINCDEC(1'b0),
  .RST(1'b0)
);

  BUFG BUFG_clkfb(.I(clkfb), .O(clkfbbuf));
  
endmodule
module pll_wrapper (clkin, clk0);

input clkin;
output clk0;

parameter TRUE = 1'b1;
parameter FALSE = 1'b0;

wire clkin;
wire clk0;

wire clkfb; 
wire clkfbbuf; 

DCM_SP #(
  .CLKDV_DIVIDE(2.0),
  .CLKFX_DIVIDE(8),
  .CLKFX_MULTIPLY(25),
  .CLKIN_DIVIDE_BY_2("FALSE"),
  .CLKIN_PERIOD(31.250),
  .CLKOUT_PHASE_SHIFT("NONE"),
  .CLK_FEEDBACK("1X"),
  .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
  .DLL_FREQUENCY_MODE("LOW"),
  .DFS_FREQUENCY_MODE("LOW"),
  .DUTY_CYCLE_CORRECTION("TRUE"),
  .PHASE_SHIFT(0),
  .STARTUP_WAIT("FALSE")
  ) DCM_baseClock (
  .CLK0(clkfb),
  .CLKFX(clk0),
  .CLKFB(clkfbbuf),
  .CLKIN(clkin),
  .PSCLK(1'b0),
  .PSEN(1'b0),
  .PSINCDEC(1'b0),
  .RST(1'b0)
);

  BUFG BUFG_clkfb(.I(clkfb), .O(clkfbbuf));
  
endmodule