data/full_repos/permissive/201488448/1_verilog/06_xnor.v
data/verilator_xmls/42ad0ca9-bbbb-45a9-b675-4d3ce0dfa500.xml
module top_module( 
    input a, 
    input b, 
    output out );

    assign	out = ~(a^b);
    
endmodule
module top_module( 
    input a, 
    input b, 
    output out );


    assign	out = ~(a^b);
    
endmodule