data/full_repos/permissive/128659832/verilog/PC_tb.v
 line:38: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always #4 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/128659832/verilog/PC_tb.v:33: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("PC_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/128659832/verilog/PC_tb.v:34: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, PC_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #1  rst = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #2 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #2  rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #6  wPC = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #2  wPC = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #4  branch=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #2  wPC = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #2  wPC = 0;            \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #4  branch=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #2  wPC = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #2  wPC = 0;            \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #4  branch=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #2  wPC = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #2  wPC = 0;            \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #4  branch=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #2  wPC = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #2  wPC = 0;            \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #4  branch=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #2  wPC = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #2  wPC = 0;            \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/PC_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 22 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PC_tb;

    reg clk  = 0;
    reg rst = 0;
    reg branch = 0;
    reg ijump = 0;
    reg aluFlag = 0;
    reg wPC = 0;

    reg  [7:0] jmpAddr = 8'b00;
    wire [7:0] PC;


    PC PC0 (
        .clk(clk),
        .rst(rst),
        .jmpAddr(jmpAddr),
        .branch(branch),
        .ijump(ijump),
        .aluFlag(aluFlag),
        .wPC(wPC),
        .PC(PC)
    );


    always #4 clk = ~clk;


    initial begin

        $dumpfile("PC_tb.vcd");
        $dumpvars(0, PC_tb);

        #2 

        #1  rst = 1;
        #2  rst = 0;
        
        #6  wPC = 1;
        #2  wPC = 0;


        #4  branch=1;
            ijump=1;
            aluFlag = 0;
            jmpAddr = 8'hB2;

        #2  wPC = 1;
        #2  wPC = 0;            



        #4  branch=0;
            ijump=0;
            aluFlag = 0;
            jmpAddr = 8'h00;

        #2  wPC = 1;
        #2  wPC = 0;            


        #4  branch=0;
            ijump=0;
            aluFlag = 0;
            jmpAddr = 8'h00;

        #2  wPC = 1;
        #2  wPC = 0;            


        #4  branch=1;
            ijump=0;
            aluFlag = 1;
            jmpAddr = 8'hA0;

        #2  wPC = 1;
        #2  wPC = 0;            


        #4  branch=1;
            ijump=0;
            aluFlag = 0;
            jmpAddr = 8'hA0;

        #2  wPC = 1;
        #2  wPC = 0;            

        #10 $finish;
    end


endmodule
module PC_tb;


    reg clk  = 0;
    reg rst = 0;
    reg branch = 0;
    reg ijump = 0;
    reg aluFlag = 0;
    reg wPC = 0;

    reg  [7:0] jmpAddr = 8'b00;
    wire [7:0] PC;


    PC PC0 (
        .clk(clk),
        .rst(rst),
        .jmpAddr(jmpAddr),
        .branch(branch),
        .ijump(ijump),
        .aluFlag(aluFlag),
        .wPC(wPC),
        .PC(PC)
    );


    always #4 clk = ~clk;


    initial begin

        $dumpfile("PC_tb.vcd");
        $dumpvars(0, PC_tb);

        #2 

        #1  rst = 1;
        #2  rst = 0;
        
        #6  wPC = 1;
        #2  wPC = 0;


        #4  branch=1;
            ijump=1;
            aluFlag = 0;
            jmpAddr = 8'hB2;

        #2  wPC = 1;
        #2  wPC = 0;            



        #4  branch=0;
            ijump=0;
            aluFlag = 0;
            jmpAddr = 8'h00;

        #2  wPC = 1;
        #2  wPC = 0;            


        #4  branch=0;
            ijump=0;
            aluFlag = 0;
            jmpAddr = 8'h00;

        #2  wPC = 1;
        #2  wPC = 0;            


        #4  branch=1;
            ijump=0;
            aluFlag = 1;
            jmpAddr = 8'hA0;

        #2  wPC = 1;
        #2  wPC = 0;            


        #4  branch=1;
            ijump=0;
            aluFlag = 0;
            jmpAddr = 8'hA0;

        #2  wPC = 1;
        #2  wPC = 0;            

        #10 $finish;
    end


endmodule