data/full_repos/permissive/135820056/rtl/miracle.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/135820056/rtl/miracle.sv:117: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                       : ... In instance miraclepiano\n   strobe_count <= 8\'h00;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/135820056/rtl/miracle.sv:157: Cannot find file containing module: \'dpram\'\ndpram #(9) inbuffer\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/135820056/rtl,data/full_repos/permissive/135820056/dpram\n             data/full_repos/permissive/135820056/rtl,data/full_repos/permissive/135820056/dpram.v\n             data/full_repos/permissive/135820056/rtl,data/full_repos/permissive/135820056/dpram.sv\n             dpram\n             dpram.v\n             dpram.sv\n             obj_dir/dpram\n             obj_dir/dpram.v\n             obj_dir/dpram.sv\n%Error: data/full_repos/permissive/135820056/rtl/miracle.sv:170: Cannot find file containing module: \'dpram\'\ndpram #(9) outbuffer\n^~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module midi_uart (
  input  wire           clk,

  input  wire           reset,
  input  wire           tdata_i,
  input  wire [ 16-1:0] data_i,
  output wire [ 16-1:0] data_o,
  input  wire           uartbrk,
  input  wire           rbfmirror,
  output wire           txint,
  output wire           rxint,
  output wire           txd,
  input  wire           rxd
);


wire clk_en = 1;


localparam LONG_BIT  = 15;
localparam OVRUN_BIT = 15-11;
localparam RBF_BIT   = 14-11;
localparam TBE_BIT   = 13-11;
localparam TSRE_BIT  = 12-11;
localparam RXD_BIT   = 11-11;



reg  [  2-1:0] rxd_sync = 2'b11;
wire           rxds;
always @ (posedge clk) begin
  if (clk_en) begin
    rxd_sync <= #1 {rxd_sync[0],rxd};
  end
end
assign rxds = rxd_sync[1];




localparam [16-1:0] HALF_PERIOD=16'd859;

reg  [ 16-1:0] serper = HALF_PERIOD;


reg  [ 16-1:0] serdat = 16'h0000;
always @ (posedge clk) begin
  if (clk_en) begin
    if (tdata_i)
      serdat <= #1 data_i;
  end
end



localparam [  2-1:0] TX_IDLE=2'd0, TX_SHIFT=2'd2;
reg  [  2-1:0] tx_state;
reg  [ 16-1:0] tx_cnt;
reg  [ 16-1:0] tx_shift;
reg            tx_txd;
reg            tx_irq;
reg            tx_tbe;
reg            tx_tsre;

always @ (posedge clk) begin
  if (clk_en) begin
    if (reset) begin
      tx_state  <= #1 TX_IDLE;
      tx_txd    <= #1 1'b1;
		tx_irq    <= #1 1'b0;
      tx_tbe    <= #1 1'b1;
      tx_tsre   <= #1 1'b1;
    end else begin
      case (tx_state)
        TX_IDLE : begin

          tx_txd <= #1 1'b1;

          if (!tx_tbe) begin

            tx_irq <= #1 1'b1;



            tx_txd <= #1 1'b0;

            tx_tsre <= #1 1'b0;
            tx_shift <= #1 serdat;

            tx_cnt <= #1 {serper[14:0], 1'b1};

            tx_state <= #1 TX_SHIFT;
          end
        end
        TX_SHIFT: begin

          tx_irq <= #1 1'b0;

          if (tx_cnt == 16'd0) begin

            if (tx_shift == 16'd0) begin

              if (tx_tbe) tx_tsre <= #1 1'b1;

              tx_state <= #1 TX_IDLE;
            end else begin

              tx_cnt <= #1 {serper[14:0], 1'b1};

              tx_shift <= #1 {1'b0, tx_shift[15:1]};
              tx_txd <= #1 tx_shift[0];
            end
          end else begin

            tx_cnt <= #1 tx_cnt - 16'd1;
          end
        end
        default: begin

          tx_state <= #1 TX_IDLE;
        end
      endcase

      if (uartbrk) tx_txd <= #1 1'b0;

      tx_tbe <= #1 (tdata_i) ? 1'b0 : ((tx_state == TX_IDLE) ? 1'b1 : tx_tbe);
    end
  end
end



localparam [  2-1:0] RX_IDLE=2'd0, RX_START=2'd1, RX_SHIFT=2'd2;
reg  [  2-1:0] rx_state;
reg  [ 16-1:0] rx_cnt;
reg  [ 10-1:0] rx_shift;
reg  [ 10-1:0] rx_data;
reg            rx_rbf;
reg            rx_rxd;
reg            rx_irq;
reg            rx_ovrun;

always @ (posedge clk) begin
  if (clk_en) begin
    if (reset) begin
      rx_state <= #1 RX_IDLE;
      rx_rbf   <= #1 1'b0;
      rx_rxd   <= #1 1'b1;
		rx_irq   <= #1 1'b0;
      rx_ovrun <= #1 1'b0;
    end else begin
      case (rx_state)
        RX_IDLE : begin

          rx_irq <= #1 1'b0;

          if (rx_rxd && !rxds) begin

            rx_shift <= #1 {serper[LONG_BIT], {9{1'b1}}};
            rx_cnt <= #1 {1'b0, serper[14:0]};

            rx_state <= #1 RX_START;
          end
        end
        RX_START : begin

          if (rx_cnt == 16'h0) begin

            if (!rxds) begin

              rx_shift <= #1 {rxds, rx_shift[9:1]};

              rx_cnt <= #1 {serper[14:0], 1'b1};

              rx_state <= #1 RX_SHIFT;
            end else begin

              rx_state <= #1 RX_IDLE;
            end
          end else begin
            rx_cnt <= #1 rx_cnt - 16'd1;
          end

          if (!rx_rxd && rxds) begin
            rx_state <= #1 RX_IDLE;
          end
        end
        RX_SHIFT : begin

          if (rx_cnt == 16'h0) begin

            rx_shift <= #1 {rxds, rx_shift[9:1]};

            rx_cnt <= #1 {serper[14:0], 1'b1};

            if (rx_shift[0] == 1'b0) begin

              rx_irq <= #1 1'b1;



              rx_data[9] <= #1 rxds;
              if (serper[LONG_BIT]) begin
                rx_data[8:0] <= #1 rx_shift[9:1];
              end else begin
                rx_data[8:0] <= #1 {rxds, rx_shift[9:2]};
              end

              rx_state <= #1 RX_IDLE;
            end
          end else begin
            rx_cnt <= #1 rx_cnt - 16'd1;
          end
        end
        default : begin

          rx_state <= #1 RX_IDLE;
        end
      endcase

      rx_rxd <= #1 rxds;

      rx_rbf <= #1 rbfmirror;

      rx_ovrun <= #1 (!rbfmirror &&  rx_rbf) ? 1'b0 : (((rx_state == RX_SHIFT) && ~|rx_cnt && !rx_shift[0]) ? rbfmirror : rx_ovrun);
    end
  end
end





wire [  5-1:0] serdatr;
assign serdatr  = {rx_ovrun, rx_rbf, tx_tbe, tx_tsre, rx_rxd};


assign txint = tx_irq;
assign rxint = rx_irq;


assign txd   = tx_txd;


assign data_o = {serdatr, 1'b0, rx_data};


endmodule
module midi_uart (
  input  wire           clk,

  input  wire           reset,
  input  wire           tdata_i,
  input  wire [ 16-1:0] data_i,
  output wire [ 16-1:0] data_o,
  input  wire           uartbrk,
  input  wire           rbfmirror,
  output wire           txint,
  output wire           rxint,
  output wire           txd,
  input  wire           rxd
);



wire clk_en = 1;


localparam LONG_BIT  = 15;
localparam OVRUN_BIT = 15-11;
localparam RBF_BIT   = 14-11;
localparam TBE_BIT   = 13-11;
localparam TSRE_BIT  = 12-11;
localparam RXD_BIT   = 11-11;



reg  [  2-1:0] rxd_sync = 2'b11;
wire           rxds;
always @ (posedge clk) begin
  if (clk_en) begin
    rxd_sync <= #1 {rxd_sync[0],rxd};
  end
end
assign rxds = rxd_sync[1];




localparam [16-1:0] HALF_PERIOD=16'd859;

reg  [ 16-1:0] serper = HALF_PERIOD;


reg  [ 16-1:0] serdat = 16'h0000;
always @ (posedge clk) begin
  if (clk_en) begin
    if (tdata_i)
      serdat <= #1 data_i;
  end
end



localparam [  2-1:0] TX_IDLE=2'd0, TX_SHIFT=2'd2;
reg  [  2-1:0] tx_state;
reg  [ 16-1:0] tx_cnt;
reg  [ 16-1:0] tx_shift;
reg            tx_txd;
reg            tx_irq;
reg            tx_tbe;
reg            tx_tsre;

always @ (posedge clk) begin
  if (clk_en) begin
    if (reset) begin
      tx_state  <= #1 TX_IDLE;
      tx_txd    <= #1 1'b1;
		tx_irq    <= #1 1'b0;
      tx_tbe    <= #1 1'b1;
      tx_tsre   <= #1 1'b1;
    end else begin
      case (tx_state)
        TX_IDLE : begin

          tx_txd <= #1 1'b1;

          if (!tx_tbe) begin

            tx_irq <= #1 1'b1;



            tx_txd <= #1 1'b0;

            tx_tsre <= #1 1'b0;
            tx_shift <= #1 serdat;

            tx_cnt <= #1 {serper[14:0], 1'b1};

            tx_state <= #1 TX_SHIFT;
          end
        end
        TX_SHIFT: begin

          tx_irq <= #1 1'b0;

          if (tx_cnt == 16'd0) begin

            if (tx_shift == 16'd0) begin

              if (tx_tbe) tx_tsre <= #1 1'b1;

              tx_state <= #1 TX_IDLE;
            end else begin

              tx_cnt <= #1 {serper[14:0], 1'b1};

              tx_shift <= #1 {1'b0, tx_shift[15:1]};
              tx_txd <= #1 tx_shift[0];
            end
          end else begin

            tx_cnt <= #1 tx_cnt - 16'd1;
          end
        end
        default: begin

          tx_state <= #1 TX_IDLE;
        end
      endcase

      if (uartbrk) tx_txd <= #1 1'b0;

      tx_tbe <= #1 (tdata_i) ? 1'b0 : ((tx_state == TX_IDLE) ? 1'b1 : tx_tbe);
    end
  end
end



localparam [  2-1:0] RX_IDLE=2'd0, RX_START=2'd1, RX_SHIFT=2'd2;
reg  [  2-1:0] rx_state;
reg  [ 16-1:0] rx_cnt;
reg  [ 10-1:0] rx_shift;
reg  [ 10-1:0] rx_data;
reg            rx_rbf;
reg            rx_rxd;
reg            rx_irq;
reg            rx_ovrun;

always @ (posedge clk) begin
  if (clk_en) begin
    if (reset) begin
      rx_state <= #1 RX_IDLE;
      rx_rbf   <= #1 1'b0;
      rx_rxd   <= #1 1'b1;
		rx_irq   <= #1 1'b0;
      rx_ovrun <= #1 1'b0;
    end else begin
      case (rx_state)
        RX_IDLE : begin

          rx_irq <= #1 1'b0;

          if (rx_rxd && !rxds) begin

            rx_shift <= #1 {serper[LONG_BIT], {9{1'b1}}};
            rx_cnt <= #1 {1'b0, serper[14:0]};

            rx_state <= #1 RX_START;
          end
        end
        RX_START : begin

          if (rx_cnt == 16'h0) begin

            if (!rxds) begin

              rx_shift <= #1 {rxds, rx_shift[9:1]};

              rx_cnt <= #1 {serper[14:0], 1'b1};

              rx_state <= #1 RX_SHIFT;
            end else begin

              rx_state <= #1 RX_IDLE;
            end
          end else begin
            rx_cnt <= #1 rx_cnt - 16'd1;
          end

          if (!rx_rxd && rxds) begin
            rx_state <= #1 RX_IDLE;
          end
        end
        RX_SHIFT : begin

          if (rx_cnt == 16'h0) begin

            rx_shift <= #1 {rxds, rx_shift[9:1]};

            rx_cnt <= #1 {serper[14:0], 1'b1};

            if (rx_shift[0] == 1'b0) begin

              rx_irq <= #1 1'b1;



              rx_data[9] <= #1 rxds;
              if (serper[LONG_BIT]) begin
                rx_data[8:0] <= #1 rx_shift[9:1];
              end else begin
                rx_data[8:0] <= #1 {rxds, rx_shift[9:2]};
              end

              rx_state <= #1 RX_IDLE;
            end
          end else begin
            rx_cnt <= #1 rx_cnt - 16'd1;
          end
        end
        default : begin

          rx_state <= #1 RX_IDLE;
        end
      endcase

      rx_rxd <= #1 rxds;

      rx_rbf <= #1 rbfmirror;

      rx_ovrun <= #1 (!rbfmirror &&  rx_rbf) ? 1'b0 : (((rx_state == RX_SHIFT) && ~|rx_cnt && !rx_shift[0]) ? rbfmirror : rx_ovrun);
    end
  end
end





wire [  5-1:0] serdatr;
assign serdatr  = {rx_ovrun, rx_rbf, tx_tbe, tx_tsre, rx_rxd};


assign txint = tx_irq;
assign rxint = rx_irq;


assign txd   = tx_txd;


assign data_o = {serdatr, 1'b0, rx_data};


endmodule