data/full_repos/permissive/167856740/cpu/mux2.v
data/verilator_xmls/260abd81-a205-44c1-89b9-b8884d27ee23.xml
module mux2(
		input wire I_sel,
		input wire [31:0] I_data1,
		input wire [31:0] I_data2,
		output wire [31:0] O_data
	  );

    assign O_data = (I_sel == 1'b0) ? I_data1 :  I_data2;

endmodule
module mux2(
		input wire I_sel,
		input wire [31:0] I_data1,
		input wire [31:0] I_data2,
		output wire [31:0] O_data
	  );


    assign O_data = (I_sel == 1'b0) ? I_data1 :  I_data2;

endmodule