data/full_repos/permissive/195227969/work/code/sb_sim_rtl/SB_DFF.v
data/verilator_xmls/ce67036b-31bd-4b05-8b6a-795380526877.xml
module SB_DFF
  ( input C,D,
    output reg Q
    );
   initial
     Q = 1'b0;   
   always @(posedge C)
       Q <= D;
endmodule
module SB_DFF
  ( input C,D,
    output reg Q
    );

   initial
     Q = 1'b0;   
   always @(posedge C)
       Q <= D;
endmodule