data/full_repos/permissive/19572582/Lab2/lab2_part7.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:60: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] SSD;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:21: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] HEX1, HEX0;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:31: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0] - 60;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:34: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0] - 50;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:37: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0] - 40;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:40: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0] - 30;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:43: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0] - 20;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:46: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0] - 10;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part7.v:49: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 6 bits.\n                                                                        : ... In instance lab2_part7\n      ONES = SW[5:0];\n           ^\n%Error: Exiting due to 9 warning(s)\n'
module lab2_part7 (SW, LEDR, HEX1, HEX0);
  input [5:0] SW;
  output [0:6] HEX1, HEX0;
  output [5:0] LEDR;

  reg [3:0] TENS, ONES;

  assign LEDR = SW;

  always begin
    if (SW[5:0] > 59) begin
      TENS = 6;
      ONES = SW[5:0] - 60;
    end else if (SW[5:0] > 49) begin
      TENS = 5;
      ONES = SW[5:0] - 50;
    end else if (SW[5:0] > 39) begin
      TENS = 4;
      ONES = SW[5:0] - 40;
    end else if (SW[5:0] > 29) begin
      TENS = 3;
      ONES = SW[5:0] - 30;
    end else if (SW[5:0] > 19) begin
      TENS = 2;
      ONES = SW[5:0] - 20;
    end else if (SW[5:0] > 9) begin
      TENS = 1;
      ONES = SW[5:0] - 10;
    end else begin
      TENS = 0;
      ONES = SW[5:0];
    end
  end

  b2d_7seg H1 (TENS, HEX1);
  b2d_7seg H0 (ONES, HEX0);

endmodule
module lab2_part7 (SW, LEDR, HEX1, HEX0);

  input [5:0] SW;
  output [0:6] HEX1, HEX0;
  output [5:0] LEDR;

  reg [3:0] TENS, ONES;

  assign LEDR = SW;

  always begin
    if (SW[5:0] > 59) begin
      TENS = 6;
      ONES = SW[5:0] - 60;
    end else if (SW[5:0] > 49) begin
      TENS = 5;
      ONES = SW[5:0] - 50;
    end else if (SW[5:0] > 39) begin
      TENS = 4;
      ONES = SW[5:0] - 40;
    end else if (SW[5:0] > 29) begin
      TENS = 3;
      ONES = SW[5:0] - 30;
    end else if (SW[5:0] > 19) begin
      TENS = 2;
      ONES = SW[5:0] - 20;
    end else if (SW[5:0] > 9) begin
      TENS = 1;
      ONES = SW[5:0] - 10;
    end else begin
      TENS = 0;
      ONES = SW[5:0];
    end
  end

  b2d_7seg H1 (TENS, HEX1);
  b2d_7seg H0 (ONES, HEX0);

endmodule