data/full_repos/permissive/14349674/animation/svAnimation.sv
 line:211: before: "."
1: b'%Warning-WIDTH: data/full_repos/permissive/14349674/animation/svAnimation.sv:378: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'Q_y\' generates 7 bits.\n                                                                                : ... In instance animation.FSM\n       if(Q_y == (SIZEOF_Y - 1))\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/14349674/animation/svAnimation.sv:374: Operator LT expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'Q_x\' generates 8 bits.\n                                                                                : ... In instance animation.FSM\n       if(Q_x < (SIZEOF_X-1))\n              ^\n%Warning-WIDTH: data/full_repos/permissive/14349674/animation/svAnimation.sv:439: Operator ADD expects 32 or 15 bits on the RHS, but RHS\'s VARREF \'Q_x\' generates 8 bits.\n                                                                                : ... In instance animation.FSM\n  address = ((SIZEOF_X*Q_y) + Q_x) + 1;  \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/14349674/animation/svAnimation.sv:279: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                : ... In instance animation.colorMux\n output reg [2:0] drawColor = 1\'b0;\n                              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/14349674/animation/svAnimation.sv:106: Input port connection \'SIZEOF_X\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'sizeX\' generates 8 bits.\n                                                                                : ... In instance animation\n   .SIZEOF_X(sizeX),\n    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/14349674/animation/svAnimation.sv:107: Input port connection \'SIZEOF_Y\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'sizeY\' generates 7 bits.\n                                                                                : ... In instance animation\n   .SIZEOF_Y(sizeY),\n    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/14349674/animation/svAnimation.sv:113: Output port connection \'Q_y\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'Q_Y\' generates 8 bits.\n                                                                                : ... In instance animation\n   .Q_y(Q_Y),\n    ^~~\n%Error: data/full_repos/permissive/14349674/animation/svAnimation.sv:117: Cannot find file containing module: \'gameLogic\'\n gameLogic dxBall\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/14349674/animation,data/full_repos/permissive/14349674/gameLogic\n             data/full_repos/permissive/14349674/animation,data/full_repos/permissive/14349674/gameLogic.v\n             data/full_repos/permissive/14349674/animation,data/full_repos/permissive/14349674/gameLogic.sv\n             gameLogic\n             gameLogic.v\n             gameLogic.sv\n             obj_dir/gameLogic\n             obj_dir/gameLogic.v\n             obj_dir/gameLogic.sv\n%Error: data/full_repos/permissive/14349674/animation/svAnimation.sv:149: Cannot find file containing module: \'newRom\'\n newRom myRom(\n ^~~~~~\n%Error: data/full_repos/permissive/14349674/animation/svAnimation.sv:155: Cannot find file containing module: \'newRom2\'\n newRom2 blankRom(\n ^~~~~~~\n%Error: data/full_repos/permissive/14349674/animation/svAnimation.sv:160: Cannot find file containing module: \'newRom3\'\n newRom3 paddleRom(\n ^~~~~~~\n%Error: data/full_repos/permissive/14349674/animation/svAnimation.sv:165: Cannot find file containing module: \'newRom4\'\n newRom4 blockRom(\n ^~~~~~~\n%Error: data/full_repos/permissive/14349674/animation/svAnimation.sv:170: Cannot find file containing module: \'newRom5\'\n newRom5 gameStartRom(\n ^~~~~~~\n%Error: data/full_repos/permissive/14349674/animation/svAnimation.sv:175: Cannot find file containing module: \'newRom6\'\n newRom6 gameResetRom(\n ^~~~~~~\n%Error: data/full_repos/permissive/14349674/animation/svAnimation.sv:181: Cannot find file containing module: \'hex_7seg\'\n hex_7seg score1(\n ^~~~~~~~\n%Error: data/full_repos/permissive/14349674/animation/svAnimation.sv:185: Cannot find file containing module: \'hex_7seg\'\n hex_7seg score2(\n ^~~~~~~~\n%Error: data/full_repos/permissive/14349674/animation/svAnimation.sv:195: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n%Error: Exiting due to 10 error(s), 7 warning(s)\n'
module fsm_draw_logic 
	(
		clk,
		reset,
		go,
		eraseColor,
		drawColor,
		old_posX,
		old_posY,
		new_posX,
		new_posY,
		SIZEOF_X,
		SIZEOF_Y,

		writeEn,
		address,
		color,
		Q_x,
		Q_y,
		pos_x,
		pos_y
	);

	input clk, reset, go;
	input [2:0] eraseColor, drawColor;
	input [7:0] new_posX;
	input [6:0] new_posY;
	input [7:0] old_posX;
	input [6:0] old_posY;
	input [8:0] SIZEOF_X;
	input [7:0] SIZEOF_Y;

	output reg writeEn;
	output reg [14:0] address;
	output reg [7:0] Q_x = 8'b0;
	output reg [6:0] Q_y = 7'b0;
	output reg [2:0] color;
	output reg [7:0] pos_x;
	output reg [6:0] pos_y;

	parameter IDLE = 3'b000,
				 DRAW = 3'b001,
				 ERASE = 3'b010,
				 HSYNC = 3'b011,
				 VSYNC = 3'b100;

	reg [2:0] state = IDLE, next_state = IDLE;
	reg blankEn = 1'b0;


	always@(posedge clk or negedge reset)
	begin
		if (!reset) 
		  state <= IDLE;
		else
		  state <= next_state;
	end

	always@(state, go, Q_x, Q_y, SIZEOF_X, SIZEOF_Y, blankEn)
	begin
		case(state)
			IDLE: begin




							if(go == 1'b1)
								next_state = ERASE;
							else
								next_state = IDLE;

					end
			DRAW: begin
						next_state = HSYNC;
					end
			ERASE: begin
						next_state = HSYNC;
					 end
			HSYNC: begin
						 if(Q_x < (SIZEOF_X-1))
							next_state = HSYNC;
						 else
						 begin
							if(Q_y == (SIZEOF_Y - 1))
							begin
								if(blankEn == 1'b1)
									next_state = DRAW;
								else
									next_state = IDLE;
							 end
							 else
								next_state = VSYNC;
						 end
					 end
			VSYNC: begin
						next_state = HSYNC;
					 end
		endcase
	end

	always@(posedge clk or negedge reset)
	begin
		if (!reset) 
		begin
			Q_x <= 8'b0;
			Q_y <= 7'b0;
		end
		else 
		begin
			case(next_state)
				IDLE: begin
							writeEn <= 1'b0;
							blankEn <= 1'b0;
							Q_x <= 8'b0;
							Q_y <= 7'b0;
						end
				DRAW: begin
							blankEn <= 1'b0;
							Q_x <= 8'b0;
							Q_y <= 7'b0;
							pos_x <= new_posX;
							pos_y <= new_posY;
						end
				ERASE: begin
							 writeEn <= 1'b1;
							 blankEn <= 1'b1;
							 Q_x <= 8'b0;
							 Q_y <= 7'b0;
							 pos_x <= old_posX;
							 pos_y <= old_posY;
						 end
				HSYNC: begin
							Q_x <= Q_x + 1;
						 end
				VSYNC: begin
							 Q_x <= 8'b0;
							 Q_y <= Q_y + 1;
						 end
			endcase
		end
	end
	
	always@(*)
	begin
		address = ((SIZEOF_X*Q_y) + Q_x) + 1;
		if(blankEn == 1'b1)
				color = eraseColor;
			else
				color = drawColor;
	end

endmodule
module fsm_draw_logic 
	(
		clk,
		reset,
		go,
		eraseColor,
		drawColor,
		old_posX,
		old_posY,
		new_posX,
		new_posY,
		SIZEOF_X,
		SIZEOF_Y,

		writeEn,
		address,
		color,
		Q_x,
		Q_y,
		pos_x,
		pos_y
	);


	input clk, reset, go;
	input [2:0] eraseColor, drawColor;
	input [7:0] new_posX;
	input [6:0] new_posY;
	input [7:0] old_posX;
	input [6:0] old_posY;
	input [8:0] SIZEOF_X;
	input [7:0] SIZEOF_Y;

	output reg writeEn;
	output reg [14:0] address;
	output reg [7:0] Q_x = 8'b0;
	output reg [6:0] Q_y = 7'b0;
	output reg [2:0] color;
	output reg [7:0] pos_x;
	output reg [6:0] pos_y;

	parameter IDLE = 3'b000,
				 DRAW = 3'b001,
				 ERASE = 3'b010,
				 HSYNC = 3'b011,
				 VSYNC = 3'b100;

	reg [2:0] state = IDLE, next_state = IDLE;
	reg blankEn = 1'b0;


	always@(posedge clk or negedge reset)
	begin
		if (!reset) 
		  state <= IDLE;
		else
		  state <= next_state;
	end

	always@(state, go, Q_x, Q_y, SIZEOF_X, SIZEOF_Y, blankEn)
	begin
		case(state)
			IDLE: begin




							if(go == 1'b1)
								next_state = ERASE;
							else
								next_state = IDLE;

					end
			DRAW: begin
						next_state = HSYNC;
					end
			ERASE: begin
						next_state = HSYNC;
					 end
			HSYNC: begin
						 if(Q_x < (SIZEOF_X-1))
							next_state = HSYNC;
						 else
						 begin
							if(Q_y == (SIZEOF_Y - 1))
							begin
								if(blankEn == 1'b1)
									next_state = DRAW;
								else
									next_state = IDLE;
							 end
							 else
								next_state = VSYNC;
						 end
					 end
			VSYNC: begin
						next_state = HSYNC;
					 end
		endcase
	end

	always@(posedge clk or negedge reset)
	begin
		if (!reset) 
		begin
			Q_x <= 8'b0;
			Q_y <= 7'b0;
		end
		else 
		begin
			case(next_state)
				IDLE: begin
							writeEn <= 1'b0;
							blankEn <= 1'b0;
							Q_x <= 8'b0;
							Q_y <= 7'b0;
						end
				DRAW: begin
							blankEn <= 1'b0;
							Q_x <= 8'b0;
							Q_y <= 7'b0;
							pos_x <= new_posX;
							pos_y <= new_posY;
						end
				ERASE: begin
							 writeEn <= 1'b1;
							 blankEn <= 1'b1;
							 Q_x <= 8'b0;
							 Q_y <= 7'b0;
							 pos_x <= old_posX;
							 pos_y <= old_posY;
						 end
				HSYNC: begin
							Q_x <= Q_x + 1;
						 end
				VSYNC: begin
							 Q_x <= 8'b0;
							 Q_y <= Q_y + 1;
						 end
			endcase
		end
	end
	
	always@(*)
	begin
		address = ((SIZEOF_X*Q_y) + Q_x) + 1;
		if(blankEn == 1'b1)
				color = eraseColor;
			else
				color = drawColor;
	end

endmodule