data/full_repos/permissive/143278/ivltests/pr2201909.v
 line:3: before: "["
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2201909.v:6: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg passed = 1'b1;
  real rvar [1:0];

  initial begin
    #1;
    rvar[0] = -1.0;
    if (rvar[0] != -1.0) begin
      $display("Failed: real array[0], expected -1.0, got %g", rvar[0]);
      passed = 1'b0;
    end

    rvar[1] = 2.0;
    if (rvar[1] != 2.0) begin
      $display("Failed: real array[1], expected 2.0, got %g", rvar[1]);
      passed = 1'b0;
    end

    if (passed) $display("PASSED");
  end
endmodule
module top;

  reg passed = 1'b1;
  real rvar [1:0];

  initial begin
    #1;
    rvar[0] = -1.0;
    if (rvar[0] != -1.0) begin
      $display("Failed: real array[0], expected -1.0, got %g", rvar[0]);
      passed = 1'b0;
    end

    rvar[1] = 2.0;
    if (rvar[1] != 2.0) begin
      $display("Failed: real array[1], expected 2.0, got %g", rvar[1]);
      passed = 1'b0;
    end

    if (passed) $display("PASSED");
  end
endmodule