data/full_repos/permissive/160024456/day02/checker_test.v
 line:3: before: "["
1: b'%Error: data/full_repos/permissive/160024456/day02/checker_test.v:7: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  checker dut (.data(data), .pair(pair), .triplet(triplet));\n  ^~~~~~~\n%Error: data/full_repos/permissive/160024456/day02/checker_test.v:7: syntax error, unexpected \'(\', expecting IDENTIFIER\n  checker dut (.data(data), .pair(pair), .triplet(triplet));\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/160024456/day02/checker_test.v:12: Unsupported: Ignoring delay on this delayed statement.\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160024456/day02/checker_test.v:16: Unsupported: Ignoring delay on this delayed statement.\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module checker_test;

  reg [25:0][7:0] data;
  wire pair;
  wire triplet;

  checker dut (.data(data), .pair(pair), .triplet(triplet));

  initial begin
    $display("start");

    data[0] = 119; data[1] = 108; data[2] = 112; data[3] = 105; data[4] = 111; data[5] = 103; data[6] = 115; data[7] = 118; data[8] = 100; data[9] = 102; data[10] = 101; data[11] = 99; data[12] = 106; data[13] = 100; data[14] = 113; data[15] = 109; data[16] = 110; data[17] = 120; data[18] = 97; data[19] = 107; data[20] = 117; data[21] = 100; data[22] = 114; data[23] = 104; data[24] = 98; data[25] = 122; #10
    if ((pair != 0) || (triplet != 1))
      $display("failed data=%b", data, ", pair=", pair, ", triplet=", triplet);

    data[0] = 119; data[1] = 98; data[2] = 112; data[3] = 105; data[4] = 111; data[5] = 103; data[6] = 115; data[7] = 118; data[8] = 100; data[9] = 102; data[10] = 101; data[11] = 99; data[12] = 106; data[13] = 100; data[14] = 113; data[15] = 109; data[16] = 110; data[17] = 120; data[18] = 97; data[19] = 107; data[20] = 117; data[21] = 100; data[22] = 114; data[23] = 104; data[24] = 98; data[25] = 122; #10
    if ((pair != 1) || (triplet != 1))
      $display("failed data=%b", data, ", pair=", pair, ", triplet=", triplet);

    $display("done");
  end

endmodule
module checker_test;


  reg [25:0][7:0] data;
  wire pair;
  wire triplet;

  checker dut (.data(data), .pair(pair), .triplet(triplet));

  initial begin
    $display("start");

    data[0] = 119; data[1] = 108; data[2] = 112; data[3] = 105; data[4] = 111; data[5] = 103; data[6] = 115; data[7] = 118; data[8] = 100; data[9] = 102; data[10] = 101; data[11] = 99; data[12] = 106; data[13] = 100; data[14] = 113; data[15] = 109; data[16] = 110; data[17] = 120; data[18] = 97; data[19] = 107; data[20] = 117; data[21] = 100; data[22] = 114; data[23] = 104; data[24] = 98; data[25] = 122; #10
    if ((pair != 0) || (triplet != 1))
      $display("failed data=%b", data, ", pair=", pair, ", triplet=", triplet);

    data[0] = 119; data[1] = 98; data[2] = 112; data[3] = 105; data[4] = 111; data[5] = 103; data[6] = 115; data[7] = 118; data[8] = 100; data[9] = 102; data[10] = 101; data[11] = 99; data[12] = 106; data[13] = 100; data[14] = 113; data[15] = 109; data[16] = 110; data[17] = 120; data[18] = 97; data[19] = 107; data[20] = 117; data[21] = 100; data[22] = 114; data[23] = 104; data[24] = 98; data[25] = 122; #10
    if ((pair != 1) || (triplet != 1))
      $display("failed data=%b", data, ", pair=", pair, ", triplet=", triplet);

    $display("done");
  end

endmodule