data/full_repos/permissive/147974511/src/ShiftRows.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/147974511/src/ShiftRows.v:13: Little bit endian vector: MSB < LSB of bit range: 0:127\n  input  wire  [0:127] Data,\n               ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/147974511/src/ShiftRows.v:14: Little bit endian vector: MSB < LSB of bit range: 0:127\n output reg  [0:127] Shifted_Data,\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/147974511/src/ShiftRows.v:20: Little bit endian vector: MSB < LSB of bit range: 0:127\n wire  [0:127] Shifted_Data_comb;\n       ^\n%Error: Exiting due to 3 warning(s)\n'
module shiftRows (
  input enable,clk,reset,
  input  wire  [0:127] Data,
	output reg  [0:127] Shifted_Data,
	output reg done );
	



	wire  [0:127] Shifted_Data_comb;
    


    assign Shifted_Data_comb[0+:8] = Data[0+:8];
    assign Shifted_Data_comb[32+:8] = Data[32+:8];
    assign Shifted_Data_comb[64+:8] = Data[64+:8];
    assign Shifted_Data_comb[96+:8] = Data[96+:8];


    assign Shifted_Data_comb [8+:8] = Data[40+:8];
    assign Shifted_Data_comb [40+:8] = Data[72+:8];
    assign Shifted_Data_comb [72+:8] = Data[104+:8];
    assign Shifted_Data_comb [104+:8] = Data[8+:8];


    assign Shifted_Data_comb [16+:8] = Data[80+:8];
    assign Shifted_Data_comb [48+:8] = Data[112+:8];
    assign Shifted_Data_comb [80+:8] = Data[16+:8];
    assign Shifted_Data_comb [112+:8] = Data[48+:8];



    assign Shifted_Data_comb [24+:8] = Data[120+:8];
    assign Shifted_Data_comb [56+:8] = Data[24+:8];
    assign Shifted_Data_comb [88+:8] = Data[56+:8];
    assign Shifted_Data_comb [120+:8] = Data[88+:8];



initial done <= 0;
initial Shifted_Data <= 128'b0;
always @(posedge clk)
  begin
    if (reset)
		begin
	       Shifted_Data <= 128'b0;
		    done <= 0;
		end
  else if (enable) begin

	    Shifted_Data <= Shifted_Data_comb;
		done <= 1;
	end		
	else done <= 0;
end




`ifdef FORMAL

    reg f_past_valid;
    initial f_past_valid = 0;

    initial assume(reset);


    always @(posedge clk)
        f_past_valid = 1;




    always @(posedge clk)
        if(!f_past_valid || $past(reset))
        begin
            assert(Shifted_Data == 128'd0);
            assert(done == 1'b0);
        end






    always @(posedge clk)
        if(enable || $past(enable))
            assume($stable(Data));



    function [127:0] shiftRows(input [127:0] Datai);
        reg [7:0] data [0:3] [0:3];
        reg [7:0] shifted_data[0:3] [0:3];
        reg [127:0] shift_fn_out;
        integer i,j,ij;
        

        for ( i=0; i<=3; i=i+1)
            for ( j=0; j<=3; j=j+1)
            begin 
                ij =15-((4*i)+j);
                data[j][i]=Datai[ij*8  +:  8];
            end	
                

        for ( j=0; j<=3; j=j+1)
            shifted_data[0][j] = data[0][j];
        

        shifted_data[1][0] = data[1][1];
        shifted_data[1][1] = data[1][2];
        shifted_data[1][2] = data[1][3];
        shifted_data[1][3] = data[1][0];
        

        shifted_data[2][0] = data[2][2];
        shifted_data[2][1] = data[2][3];
        shifted_data[2][2] = data[2][0];
        shifted_data[2][3] = data[2][1];
        

        shifted_data[3][0] = data[3][3];
        shifted_data[3][1] = data[3][0];
        shifted_data[3][2] = data[3][1];
        shifted_data[3][3] = data[3][2];
     

        for ( i=0; i<=3; i=i+1)
            for ( j=0; j<=3; j=j+1)
            begin 
                ij =15-((4*i)+j);
                shift_fn_out[ij*8  +:  8]=shifted_data[j][i];
            end


            shiftRows = shift_fn_out;
    endfunction

    reg [127:0] f_shifted_Data;

    always @(*)
        f_shifted_Data = shiftRows(Data);

    always @(posedge clk)
        if(done)
            assert(Shifted_Data == f_shifted_Data);

`endif

endmodule
module shiftRows (
  input enable,clk,reset,
  input  wire  [0:127] Data,
	output reg  [0:127] Shifted_Data,
	output reg done );

	



	wire  [0:127] Shifted_Data_comb;
    


    assign Shifted_Data_comb[0+:8] = Data[0+:8];
    assign Shifted_Data_comb[32+:8] = Data[32+:8];
    assign Shifted_Data_comb[64+:8] = Data[64+:8];
    assign Shifted_Data_comb[96+:8] = Data[96+:8];


    assign Shifted_Data_comb [8+:8] = Data[40+:8];
    assign Shifted_Data_comb [40+:8] = Data[72+:8];
    assign Shifted_Data_comb [72+:8] = Data[104+:8];
    assign Shifted_Data_comb [104+:8] = Data[8+:8];


    assign Shifted_Data_comb [16+:8] = Data[80+:8];
    assign Shifted_Data_comb [48+:8] = Data[112+:8];
    assign Shifted_Data_comb [80+:8] = Data[16+:8];
    assign Shifted_Data_comb [112+:8] = Data[48+:8];



    assign Shifted_Data_comb [24+:8] = Data[120+:8];
    assign Shifted_Data_comb [56+:8] = Data[24+:8];
    assign Shifted_Data_comb [88+:8] = Data[56+:8];
    assign Shifted_Data_comb [120+:8] = Data[88+:8];



initial done <= 0;
initial Shifted_Data <= 128'b0;
always @(posedge clk)
  begin
    if (reset)
		begin
	       Shifted_Data <= 128'b0;
		    done <= 0;
		end
  else if (enable) begin

	    Shifted_Data <= Shifted_Data_comb;
		done <= 1;
	end		
	else done <= 0;
end




`ifdef FORMAL

    reg f_past_valid;
    initial f_past_valid = 0;

    initial assume(reset);


    always @(posedge clk)
        f_past_valid = 1;




    always @(posedge clk)
        if(!f_past_valid || $past(reset))
        begin
            assert(Shifted_Data == 128'd0);
            assert(done == 1'b0);
        end






    always @(posedge clk)
        if(enable || $past(enable))
            assume($stable(Data));



    function [127:0] shiftRows(input [127:0] Datai);
        reg [7:0] data [0:3] [0:3];
        reg [7:0] shifted_data[0:3] [0:3];
        reg [127:0] shift_fn_out;
        integer i,j,ij;
        

        for ( i=0; i<=3; i=i+1)
            for ( j=0; j<=3; j=j+1)
            begin 
                ij =15-((4*i)+j);
                data[j][i]=Datai[ij*8  +:  8];
            end	
                

        for ( j=0; j<=3; j=j+1)
            shifted_data[0][j] = data[0][j];
        

        shifted_data[1][0] = data[1][1];
        shifted_data[1][1] = data[1][2];
        shifted_data[1][2] = data[1][3];
        shifted_data[1][3] = data[1][0];
        

        shifted_data[2][0] = data[2][2];
        shifted_data[2][1] = data[2][3];
        shifted_data[2][2] = data[2][0];
        shifted_data[2][3] = data[2][1];
        

        shifted_data[3][0] = data[3][3];
        shifted_data[3][1] = data[3][0];
        shifted_data[3][2] = data[3][1];
        shifted_data[3][3] = data[3][2];
     

        for ( i=0; i<=3; i=i+1)
            for ( j=0; j<=3; j=j+1)
            begin 
                ij =15-((4*i)+j);
                shift_fn_out[ij*8  +:  8]=shifted_data[j][i];
            end


            shiftRows = shift_fn_out;
    endfunction

    reg [127:0] f_shifted_Data;

    always @(*)
        f_shifted_Data = shiftRows(Data);

    always @(posedge clk)
        if(done)
            assert(Shifted_Data == f_shifted_Data);

`endif

endmodule