data/full_repos/permissive/202237519/verilog/digitalsystem5/line_decoder_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem5/line_decoder_tb.v:1: Cannot find include file: line_decoder.v\n`include "line_decoder.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem5,data/full_repos/permissive/202237519/line_decoder.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem5,data/full_repos/permissive/202237519/line_decoder.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem5,data/full_repos/permissive/202237519/line_decoder.v.sv\n             line_decoder.v\n             line_decoder.v.v\n             line_decoder.v.sv\n             obj_dir/line_decoder.v\n             obj_dir/line_decoder.v.v\n             obj_dir/line_decoder.v.sv\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem5/line_decoder_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("line_decoder_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem5/line_decoder_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,line_decoder_tb);  \n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem5/line_decoder_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module line_decoder_tb;

reg [3:0]A;
wire [3:0]B;
integer i;

line_decoder ld(A,B);
initial begin
    $dumpfile("line_decoder_tb.vcd");
    $dumpvars(0,line_decoder_tb);
    for (i = 4'b0000; i <= 4'b1111; i = i+1)
    begin
        A <= i;
        #10;
    end
    $finish;
end

endmodule
module line_decoder_tb;


reg [3:0]A;
wire [3:0]B;
integer i;

line_decoder ld(A,B);
initial begin
    $dumpfile("line_decoder_tb.vcd");
    $dumpvars(0,line_decoder_tb);
    for (i = 4'b0000; i <= 4'b1111; i = i+1)
    begin
        A <= i;
        #10;
    end
    $finish;
end

endmodule