data/full_repos/permissive/165663914/firmware/ASMI_interface.v
1: b'%Warning-WIDTH: data/full_repos/permissive/165663914/firmware/ASMI_interface.v:84: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                 : ... In instance ASMI_interface\n    state <= 1\'d1;\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/165663914/firmware/ASMI_interface.v:189: Cannot find file containing module: \'ASMI\'\nASMI  ASMI_inst(.reset(1\'b0), .addr(address),.sector_erase(sector_erase), .busy(busy), .clkin(clock),\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/165663914/firmware,data/full_repos/permissive/165663914/ASMI\n             data/full_repos/permissive/165663914/firmware,data/full_repos/permissive/165663914/ASMI.v\n             data/full_repos/permissive/165663914/firmware,data/full_repos/permissive/165663914/ASMI.sv\n             ASMI\n             ASMI.v\n             ASMI.sv\n             obj_dir/ASMI\n             obj_dir/ASMI.v\n             obj_dir/ASMI.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module ASMI_interface (clock, busy, erase, erase_ACK, IF_Rx_used, rdreq, IF_PHY_data,
					   erase_done, erase_done_ACK, send_more, send_more_ACK, num_blocks, NCONFIG); 

input 	wire 	clock;
input 	wire 	erase;
input 	wire 	[9:0]IF_Rx_used;
input  	wire  	erase_done_ACK;
input  	wire	send_more_ACK;
input   wire	[7:0]IF_PHY_data;
input   wire    [13:0]num_blocks;

output 	wire	busy;
output 	reg 	rdreq;
output 	reg 	erase_done;
output  reg		send_more;
output  reg		erase_ACK;
output  reg     NCONFIG;


reg		sector_erase;
reg 	[23:0]address;
reg 	write_enable; 
reg 	write;
reg     shift_bytes; 
reg 	[3:0]state;
reg 	[13:0]page;
reg 	[8:0]byte_count;
reg     [24:0]reset_delay;



wire [7:0]datain;
assign datain = {IF_PHY_data[0],IF_PHY_data[1],IF_PHY_data[2],IF_PHY_data[3],IF_PHY_data[4],IF_PHY_data[5],IF_PHY_data[6],IF_PHY_data[7]};



always @ (negedge clock) 
begin 
case (state)

0:	begin 
		sector_erase <= 0;
		write_enable <= 0;
		write <= 0;
		erase_ACK <= 0;
		erase_done <= 0;
		address <= 24'h000000;
		byte_count <= 0;
		page <= 0;
		send_more <= 0;
		NCONFIG <= 0;
		if (erase) 
			 state <= 1'd1;
		else if(IF_Rx_used > 254)
			state <= 5;		 
	end


1:	begin
		erase_ACK <= 1'b1;
		write_enable <= 1'b1;
		sector_erase <= 1'b1;
		state <= 2;
	end 

2:	begin
		write_enable <= 0;
		sector_erase <= 0;
		if (busy) state <= 2;
		else if (address != 24'h1F0000) begin 
				address <= address + 24'h010000;
				state <= 1;
		end 
		else state <= 3;
	end

3:	begin
		erase_done <= 1'b1;
		state <= 4;
	end 

4:	begin
		if (erase_done_ACK) state <= 0;
	end
	

5: 	begin 
	rdreq <= 1'b1;					
	byte_count <= 0;
	state <= state + 1'b1;
	end 

6:	begin
		if (byte_count == 9'd256) begin
			byte_count <= 0;
			shift_bytes <= 0;
			rdreq <= 0;
			page <= page + 1'b1;
			state <= state + 1'b1;
		end 
		else begin
			write_enable <= 1'b1;
			shift_bytes <= 1'b1;
			byte_count <= byte_count + 1'b1;
		end
	end 

7:	begin
	write <= 1;
	state <= state + 1'b1;
	send_more <= 1'b1;		
	end 


8:	begin 
	write <= 0;
	write_enable <= 0;
		if (send_more_ACK) send_more <= 0;
		if (page == num_blocks) begin
			 send_more <= 1'b1;
			 state <= state + 1'b1;
		end 
		else if (!busy && IF_Rx_used > 254  && send_more == 0) begin
			address <= address + 24'd256;
			state <= 5;
		end
	end 


9: 	begin
		if (send_more_ACK) begin 
			send_more <= 0;		
			state <= state + 1'b1;
		end 
	end 
	

10:	begin
		if (reset_delay == 25000000) begin		
			if (!busy)
				NCONFIG <= 1'b1;
		end 																
		else reset_delay <= reset_delay + 1'b1;
	end 
	
default: state <= 0;
		
endcase
end 








ASMI  ASMI_inst(.reset(1'b0), .addr(address),.sector_erase(sector_erase), .busy(busy), .clkin(clock),
    						   .wren(write_enable), .sector_protect(0),
							   .datain(datain), .write(write), .shift_bytes(shift_bytes)); 


endmodule
module ASMI_interface (clock, busy, erase, erase_ACK, IF_Rx_used, rdreq, IF_PHY_data,
					   erase_done, erase_done_ACK, send_more, send_more_ACK, num_blocks, NCONFIG);
 

input 	wire 	clock;
input 	wire 	erase;
input 	wire 	[9:0]IF_Rx_used;
input  	wire  	erase_done_ACK;
input  	wire	send_more_ACK;
input   wire	[7:0]IF_PHY_data;
input   wire    [13:0]num_blocks;

output 	wire	busy;
output 	reg 	rdreq;
output 	reg 	erase_done;
output  reg		send_more;
output  reg		erase_ACK;
output  reg     NCONFIG;


reg		sector_erase;
reg 	[23:0]address;
reg 	write_enable; 
reg 	write;
reg     shift_bytes; 
reg 	[3:0]state;
reg 	[13:0]page;
reg 	[8:0]byte_count;
reg     [24:0]reset_delay;



wire [7:0]datain;
assign datain = {IF_PHY_data[0],IF_PHY_data[1],IF_PHY_data[2],IF_PHY_data[3],IF_PHY_data[4],IF_PHY_data[5],IF_PHY_data[6],IF_PHY_data[7]};



always @ (negedge clock) 
begin 
case (state)

0:	begin 
		sector_erase <= 0;
		write_enable <= 0;
		write <= 0;
		erase_ACK <= 0;
		erase_done <= 0;
		address <= 24'h000000;
		byte_count <= 0;
		page <= 0;
		send_more <= 0;
		NCONFIG <= 0;
		if (erase) 
			 state <= 1'd1;
		else if(IF_Rx_used > 254)
			state <= 5;		 
	end


1:	begin
		erase_ACK <= 1'b1;
		write_enable <= 1'b1;
		sector_erase <= 1'b1;
		state <= 2;
	end 

2:	begin
		write_enable <= 0;
		sector_erase <= 0;
		if (busy) state <= 2;
		else if (address != 24'h1F0000) begin 
				address <= address + 24'h010000;
				state <= 1;
		end 
		else state <= 3;
	end

3:	begin
		erase_done <= 1'b1;
		state <= 4;
	end 

4:	begin
		if (erase_done_ACK) state <= 0;
	end
	

5: 	begin 
	rdreq <= 1'b1;					
	byte_count <= 0;
	state <= state + 1'b1;
	end 

6:	begin
		if (byte_count == 9'd256) begin
			byte_count <= 0;
			shift_bytes <= 0;
			rdreq <= 0;
			page <= page + 1'b1;
			state <= state + 1'b1;
		end 
		else begin
			write_enable <= 1'b1;
			shift_bytes <= 1'b1;
			byte_count <= byte_count + 1'b1;
		end
	end 

7:	begin
	write <= 1;
	state <= state + 1'b1;
	send_more <= 1'b1;		
	end 


8:	begin 
	write <= 0;
	write_enable <= 0;
		if (send_more_ACK) send_more <= 0;
		if (page == num_blocks) begin
			 send_more <= 1'b1;
			 state <= state + 1'b1;
		end 
		else if (!busy && IF_Rx_used > 254  && send_more == 0) begin
			address <= address + 24'd256;
			state <= 5;
		end
	end 


9: 	begin
		if (send_more_ACK) begin 
			send_more <= 0;		
			state <= state + 1'b1;
		end 
	end 
	

10:	begin
		if (reset_delay == 25000000) begin		
			if (!busy)
				NCONFIG <= 1'b1;
		end 																
		else reset_delay <= reset_delay + 1'b1;
	end 
	
default: state <= 0;
		
endcase
end 








ASMI  ASMI_inst(.reset(1'b0), .addr(address),.sector_erase(sector_erase), .busy(busy), .clkin(clock),
    						   .wren(write_enable), .sector_protect(0),
							   .datain(datain), .write(write), .shift_bytes(shift_bytes)); 


endmodule