data/full_repos/permissive/130390123/proc.v
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1: b'%Warning-IMPLICIT: data/full_repos/permissive/130390123/proc.v:21: Signal definition not found, creating implicitly: \'I\'\n                                                                 : ... Suggested alternative: \'IR\'\n assign I = IR[8:6];\n        ^\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/130390123/proc.v:19: Cannot find file containing module: \'regn\'\n regn regI (DIN, IRin, Clock, IR);\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/130390123,data/full_repos/permissive/130390123/regn\n             data/full_repos/permissive/130390123,data/full_repos/permissive/130390123/regn.v\n             data/full_repos/permissive/130390123,data/full_repos/permissive/130390123/regn.sv\n             regn\n             regn.v\n             regn.sv\n             obj_dir/regn\n             obj_dir/regn.v\n             obj_dir/regn.sv\n%Warning-WIDTH: data/full_repos/permissive/130390123/proc.v:21: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                              : ... In instance proc\n assign I = IR[8:6];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/130390123/proc.v:22: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                              : ... In instance proc\n assign RX = IR[5:3];\n           ^\n%Warning-WIDTH: data/full_repos/permissive/130390123/proc.v:23: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                              : ... In instance proc\n assign RY = IR[2:0];\n           ^\n%Error: data/full_repos/permissive/130390123/proc.v:36: Cannot find file containing module: \'upcount\'\n upcount Tstep (1\'b0, Clock, Tstep_Q);\n ^~~~~~~\n%Error: data/full_repos/permissive/130390123/proc.v:37: Cannot find file containing module: \'dec3to8\'\n dec3to8 decX (RX, 1\'b1, Xreg);\n ^~~~~~~\n%Error: data/full_repos/permissive/130390123/proc.v:38: Cannot find file containing module: \'dec3to8\'\n dec3to8 decY (RY, 1\'b1, Yreg);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/130390123/proc.v:93: Bit extraction of array[7:0] requires 3 bit index, not 1 bits.\n                                                              : ... In instance proc\n      Rout[RY] = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/130390123/proc.v:94: Bit extraction of array[7:0] requires 3 bit index, not 1 bits.\n                                                              : ... In instance proc\n      Rin[RX] = 1;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/130390123/proc.v:100: Bit extraction of array[7:0] requires 3 bit index, not 1 bits.\n                                                               : ... In instance proc\n      Rin[RX] = 1;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/130390123/proc.v:105: Bit extraction of array[7:0] requires 3 bit index, not 1 bits.\n                                                               : ... In instance proc\n      Rout[RX] = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/130390123/proc.v:112: Bit extraction of array[7:0] requires 3 bit index, not 1 bits.\n                                                               : ... In instance proc\n      Rout[RX] = 1;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/130390123/proc.v:90: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'I\' generates 1 bits.\n                                                              : ... In instance proc\n    case(I)\n    ^~~~\n%Error: data/full_repos/permissive/130390123/proc.v:169: Cannot find file containing module: \'regn\'\n regn reg0 (BusWires, Rin[0], Clock, R[0]);\n ^~~~\n%Error: data/full_repos/permissive/130390123/proc.v:170: Cannot find file containing module: \'regn\'\n regn reg1 (BusWires, Rin[1], Clock, R[1]);\n ^~~~\n%Error: data/full_repos/permissive/130390123/proc.v:171: Cannot find file containing module: \'regn\'\n regn reg2 (BusWires, Rin[2], Clock, R[2]);\n ^~~~\n%Error: data/full_repos/permissive/130390123/proc.v:172: Cannot find file containing module: \'regn\'\n regn reg3 (BusWires, Rin[3], Clock, R[3]);\n ^~~~\n%Error: data/full_repos/permissive/130390123/proc.v:173: Cannot find file containing module: \'regn\'\n regn reg4 (BusWires, Rin[4], Clock, R[4]);\n ^~~~\n%Error: data/full_repos/permissive/130390123/proc.v:174: Cannot find file containing module: \'regn\'\n regn reg5 (BusWires, Rin[5], Clock, R[5]);\n ^~~~\n%Error: data/full_repos/permissive/130390123/proc.v:175: Cannot find file containing module: \'regn\'\n regn reg6 (BusWires, Rin[6], Clock, R[6]);\n ^~~~\n%Error: data/full_repos/permissive/130390123/proc.v:176: Cannot find file containing module: \'regn\'\n regn reg7 (BusWires, Rin[7], Clock, R[7]); \n ^~~~\n%Error: data/full_repos/permissive/130390123/proc.v:177: Cannot find file containing module: \'regn\'\n regn regA (BusWires, Ain, Clock, A);\n ^~~~\n%Error: data/full_repos/permissive/130390123/proc.v:178: Cannot find file containing module: \'regn\'\n regn regG (GinData, Gin, Clock, G);\n ^~~~\n%Error: Exiting due to 14 error(s), 10 warning(s)\n'
module proc (DIN, Resetn, Clock, Run, Done, BusWires, State);
	input [15:0] DIN;
	input Resetn, Clock, Run;
	output reg Done = 0;
	output [15:0] BusWires;
	output [1:0] State;
	
	wire [15:0] IR;
	wire [15:0] R [0:7];
	wire RX, RY;
	wire Xreg, Yreg;
	wire [1:0] Tstep_Q;
	

	wire [15:0] G;
	wire [15:0] A;
	wire [15:0] GinData;
	
	regn regI (DIN, IRin, Clock, IR);
	
	assign I = IR[8:6];
	assign RX = IR[5:3];
	assign RY = IR[2:0];
	
	reg IRin = 0;	
	reg Rin[0:7];
	reg Rout[0:7];
	reg Ain;
	reg Gin;
	reg Aout;
	reg Gout;
	reg DINout;
	reg sub = 0;
	
	wire Clear = Resetn;
	upcount Tstep (1'b0, Clock, Tstep_Q);
	dec3to8 decX (RX, 1'b1, Xreg);
	dec3to8 decY (RY, 1'b1, Yreg);
	
	always @(Tstep_Q or I or Xreg or Yreg)
	begin
		case(Tstep_Q)
			2'b00:
			begin
				IRin = 1'b1;
				Done = 0;
				Rin[0] = 0;
				Rin[1] = 0;
				Rin[2] = 0;
				Rin[3] = 0;
				Rin[4] = 0;
				Rin[5] = 0;
				Rin[6] = 0;
				Rin[7] = 0;
				Ain = 0;
				Gin = 0;
				Rout[0] = 0;
				Rout[1] = 0;
				Rout[2] = 0;
				Rout[3] = 0;
				Rout[4] = 0;
				Rout[5] = 0;
				Rout[6] = 0;
				Rout[7] = 0;
				DINout = 0;
			end		
			2'b01:
			begin
				IRin = 0;
				Done = 0;
				Rin[0] = 0;
				Rin[1] = 0;
				Rin[2] = 0;
				Rin[3] = 0;
				Rin[4] = 0;
				Rin[5] = 0;
				Rin[6] = 0;
				Rin[7] = 0;
				Ain = 0;
				Gin = 0;
				Rout[0] = 0;
				Rout[1] = 0;
				Rout[2] = 0;
				Rout[3] = 0;
				Rout[4] = 0;
				Rout[5] = 0;
				Rout[6] = 0;
				Rout[7] = 0;
				DINout = 0;
				case(I)
					3'b000:
					begin
						Rout[RY] = 1;
						Rin[RX] = 1;
						Done = 1;
					end
					3'b001:
					begin
						DINout = 1;
						Rin[RX] = 1;
						Done = 1;
					end
					3'b010:
					begin
						Rout[RX] = 1;
						Ain = 1;
						Done = 0;
						sub = 0;
					end
					3'b011:
					begin
						Rout[RX] = 1;
						Ain = 1;
						Done = 0;
						sub = 1;
					end
				endcase
			end		
			2'b10:
			begin				
				Done = 0;
				Rin[0] = 0;
				Rin[1] = 0;
				Rin[2] = 0;
				Rin[3] = 0;
				Rin[4] = 0;
				Rin[5] = 0;
				Rin[6] = 0;
				Rin[7] = 0;
				Ain = 0;
				Gin = 0;
				Rout[0] = 0;
				Rout[1] = 0;
				Rout[2] = 0;
				Rout[3] = 0;
				Rout[4] = 0;
				Rout[5] = 0;
				Rout[6] = 0;
				Rout[7] = 0;
				DINout = 0;
			end		
			2'b11:
			begin				
				Done = 0;
				Rin[0] = 0;
				Rin[1] = 0;
				Rin[2] = 0;
				Rin[3] = 0;
				Rin[4] = 0;
				Rin[5] = 0;
				Rin[6] = 0;
				Rin[7] = 0;
				Ain = 0;
				Gin = 0;
				Rout[0] = 0;
				Rout[1] = 0;
				Rout[2] = 0;
				Rout[3] = 0;
				Rout[4] = 0;
				Rout[5] = 0;
				Rout[6] = 0;
				Rout[7] = 0;
				DINout = 0;
			end
		endcase
	end
	

	regn reg0 (BusWires, Rin[0], Clock, R[0]);
	regn reg1 (BusWires, Rin[1], Clock, R[1]);
	regn reg2 (BusWires, Rin[2], Clock, R[2]);
	regn reg3 (BusWires, Rin[3], Clock, R[3]);
	regn reg4 (BusWires, Rin[4], Clock, R[4]);
	regn reg5 (BusWires, Rin[5], Clock, R[5]);
	regn reg6 (BusWires, Rin[6], Clock, R[6]);
	regn reg7 (BusWires, Rin[7], Clock, R[7]);	
	regn regA (BusWires, Ain, Clock, A);
	regn regG (GinData, Gin, Clock, G);
	

	assign GinData = ({16{~sub}} & (A[15:0] + BusWires));
	
	assign BusWires = ({16{Rout[0]}} & R[0]) | ({16{Rout[1]}} & R[1]) | ({16{Rout[2]}} & R[2]) | ({16{Rout[3]}} & R[3])
	 | ({16{Rout[4]}} & R[4]) | ({16{Rout[5]}} & R[5]) | ({16{Rout[6]}} & R[6]) | ({16{Rout[7]}} & R[7]) | ({16{DINout}} & DIN) 
	 | ({16{Gout}} & G) | ({16{Aout}} & A);
	assign State = Tstep_Q;
endmodule
module proc (DIN, Resetn, Clock, Run, Done, BusWires, State);

	input [15:0] DIN;
	input Resetn, Clock, Run;
	output reg Done = 0;
	output [15:0] BusWires;
	output [1:0] State;
	
	wire [15:0] IR;
	wire [15:0] R [0:7];
	wire RX, RY;
	wire Xreg, Yreg;
	wire [1:0] Tstep_Q;
	

	wire [15:0] G;
	wire [15:0] A;
	wire [15:0] GinData;
	
	regn regI (DIN, IRin, Clock, IR);
	
	assign I = IR[8:6];
	assign RX = IR[5:3];
	assign RY = IR[2:0];
	
	reg IRin = 0;	
	reg Rin[0:7];
	reg Rout[0:7];
	reg Ain;
	reg Gin;
	reg Aout;
	reg Gout;
	reg DINout;
	reg sub = 0;
	
	wire Clear = Resetn;
	upcount Tstep (1'b0, Clock, Tstep_Q);
	dec3to8 decX (RX, 1'b1, Xreg);
	dec3to8 decY (RY, 1'b1, Yreg);
	
	always @(Tstep_Q or I or Xreg or Yreg)
	begin
		case(Tstep_Q)
			2'b00:
			begin
				IRin = 1'b1;
				Done = 0;
				Rin[0] = 0;
				Rin[1] = 0;
				Rin[2] = 0;
				Rin[3] = 0;
				Rin[4] = 0;
				Rin[5] = 0;
				Rin[6] = 0;
				Rin[7] = 0;
				Ain = 0;
				Gin = 0;
				Rout[0] = 0;
				Rout[1] = 0;
				Rout[2] = 0;
				Rout[3] = 0;
				Rout[4] = 0;
				Rout[5] = 0;
				Rout[6] = 0;
				Rout[7] = 0;
				DINout = 0;
			end		
			2'b01:
			begin
				IRin = 0;
				Done = 0;
				Rin[0] = 0;
				Rin[1] = 0;
				Rin[2] = 0;
				Rin[3] = 0;
				Rin[4] = 0;
				Rin[5] = 0;
				Rin[6] = 0;
				Rin[7] = 0;
				Ain = 0;
				Gin = 0;
				Rout[0] = 0;
				Rout[1] = 0;
				Rout[2] = 0;
				Rout[3] = 0;
				Rout[4] = 0;
				Rout[5] = 0;
				Rout[6] = 0;
				Rout[7] = 0;
				DINout = 0;
				case(I)
					3'b000:
					begin
						Rout[RY] = 1;
						Rin[RX] = 1;
						Done = 1;
					end
					3'b001:
					begin
						DINout = 1;
						Rin[RX] = 1;
						Done = 1;
					end
					3'b010:
					begin
						Rout[RX] = 1;
						Ain = 1;
						Done = 0;
						sub = 0;
					end
					3'b011:
					begin
						Rout[RX] = 1;
						Ain = 1;
						Done = 0;
						sub = 1;
					end
				endcase
			end		
			2'b10:
			begin				
				Done = 0;
				Rin[0] = 0;
				Rin[1] = 0;
				Rin[2] = 0;
				Rin[3] = 0;
				Rin[4] = 0;
				Rin[5] = 0;
				Rin[6] = 0;
				Rin[7] = 0;
				Ain = 0;
				Gin = 0;
				Rout[0] = 0;
				Rout[1] = 0;
				Rout[2] = 0;
				Rout[3] = 0;
				Rout[4] = 0;
				Rout[5] = 0;
				Rout[6] = 0;
				Rout[7] = 0;
				DINout = 0;
			end		
			2'b11:
			begin				
				Done = 0;
				Rin[0] = 0;
				Rin[1] = 0;
				Rin[2] = 0;
				Rin[3] = 0;
				Rin[4] = 0;
				Rin[5] = 0;
				Rin[6] = 0;
				Rin[7] = 0;
				Ain = 0;
				Gin = 0;
				Rout[0] = 0;
				Rout[1] = 0;
				Rout[2] = 0;
				Rout[3] = 0;
				Rout[4] = 0;
				Rout[5] = 0;
				Rout[6] = 0;
				Rout[7] = 0;
				DINout = 0;
			end
		endcase
	end
	

	regn reg0 (BusWires, Rin[0], Clock, R[0]);
	regn reg1 (BusWires, Rin[1], Clock, R[1]);
	regn reg2 (BusWires, Rin[2], Clock, R[2]);
	regn reg3 (BusWires, Rin[3], Clock, R[3]);
	regn reg4 (BusWires, Rin[4], Clock, R[4]);
	regn reg5 (BusWires, Rin[5], Clock, R[5]);
	regn reg6 (BusWires, Rin[6], Clock, R[6]);
	regn reg7 (BusWires, Rin[7], Clock, R[7]);	
	regn regA (BusWires, Ain, Clock, A);
	regn regG (GinData, Gin, Clock, G);
	

	assign GinData = ({16{~sub}} & (A[15:0] + BusWires));
	
	assign BusWires = ({16{Rout[0]}} & R[0]) | ({16{Rout[1]}} & R[1]) | ({16{Rout[2]}} & R[2]) | ({16{Rout[3]}} & R[3])
	 | ({16{Rout[4]}} & R[4]) | ({16{Rout[5]}} & R[5]) | ({16{Rout[6]}} & R[6]) | ({16{Rout[7]}} & R[7]) | ({16{DINout}} & DIN) 
	 | ({16{Gout}} & G) | ({16{Aout}} & A);
	assign State = Tstep_Q;
endmodule