data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0502/lab5.srcs/sources_1/new/time_divider.v
data/verilator_xmls/578fab4c-8763-4448-b209-14432646d20e.xml
module time_divider(
    input clock_in,
    output reg clock_out
    );
	 reg [20:0] buffer;
	 initial begin 
	 buffer=0; 
	 end

	 always@(posedge clock_in)
	 begin
		buffer<=buffer+1;
		clock_out<=buffer[1];
	 end
endmodule
module time_divider(
    input clock_in,
    output reg clock_out
    );

	 reg [20:0] buffer;
	 initial begin 
	 buffer=0; 
	 end

	 always@(posedge clock_in)
	 begin
		buffer<=buffer+1;
		clock_out<=buffer[1];
	 end
endmodule