data/full_repos/permissive/143278/ivltests/real_force_rel.v
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1: b'%Error: data/full_repos/permissive/143278/ivltests/real_force_rel.v:6: Unsupported: Verilog 1995 force\n  always @(d) force f = z;\n              ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_force_rel.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_force_rel.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1 d = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_force_rel.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1 f = 1.0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_force_rel.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1 assign f = y;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_force_rel.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/real_force_rel.v:41: Unsupported: Verilog 1995 release\n    #1 release f;\n       ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_force_rel.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #1 release f;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_force_rel.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #1 z = 0.0;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/real_force_rel.v:55: Unsupported: Verilog 1995 deassign\n    #1 deassign f;\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_force_rel.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #1 deassign f;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_force_rel.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #1 y = 0.0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_force_rel.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #1 f = 2.0;\n    ^\n%Error: Exiting due to 3 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ();
  reg pass = 1'b1;
  reg d;
  real f = 0.0, z = 0.0, y = 1.0;

  always @(d) force f = z;

  initial begin

    #1;
    if (f != 0.0) begin
      $display("Failed initial value, expected 0.0, got %f", f);
      pass = 1'b0;
    end



    #1 d = 0;
    #1 f = 1.0;
    if (f != 0.0) begin
      $display("Failed force holding (normal), expected 0.0, got %f", f);
      pass = 1'b0;
    end


    #1 assign f = y;
    if (f != 0.0) begin
      $display("Failed force holding (assign), expected 0.0, got %f", f);
      pass = 1'b0;
    end


    z = 1.0;
    #1;
    if (f != 1.0) begin
      $display("Failed force propagation, expected 1.0, got %f", f);
      pass = 1'b0;
    end


    #1 release f;
    if (f != 1.0) begin
      $display("Failed release holding, expected 1.0, got %f", f);
      pass = 1'b0;
    end


    #1 z = 0.0;
    if (f != 1.0) begin
      $display("Failed variable unlinking (force), expected 1.0, got %f", f);
      pass = 1'b0;
    end


    #1 deassign f;
    if (f != 1.0) begin
      $display("Failed deassign holding, expected 1.0, got %f", f);
      pass = 1'b0;
    end


    #1 y = 0.0;
    if (f != 1.0) begin
      $display("Failed variable unlinking (deassign), expected 1.0, got %f", f);
      pass = 1'b0;
    end


    #1 f = 2.0;
    if (f != 2.0) begin
      $display("Failed release, expected 2.0, got %f", f);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module test ();

  reg pass = 1'b1;
  reg d;
  real f = 0.0, z = 0.0, y = 1.0;

  always @(d) force f = z;

  initial begin

    #1;
    if (f != 0.0) begin
      $display("Failed initial value, expected 0.0, got %f", f);
      pass = 1'b0;
    end



    #1 d = 0;
    #1 f = 1.0;
    if (f != 0.0) begin
      $display("Failed force holding (normal), expected 0.0, got %f", f);
      pass = 1'b0;
    end


    #1 assign f = y;
    if (f != 0.0) begin
      $display("Failed force holding (assign), expected 0.0, got %f", f);
      pass = 1'b0;
    end


    z = 1.0;
    #1;
    if (f != 1.0) begin
      $display("Failed force propagation, expected 1.0, got %f", f);
      pass = 1'b0;
    end


    #1 release f;
    if (f != 1.0) begin
      $display("Failed release holding, expected 1.0, got %f", f);
      pass = 1'b0;
    end


    #1 z = 0.0;
    if (f != 1.0) begin
      $display("Failed variable unlinking (force), expected 1.0, got %f", f);
      pass = 1'b0;
    end


    #1 deassign f;
    if (f != 1.0) begin
      $display("Failed deassign holding, expected 1.0, got %f", f);
      pass = 1'b0;
    end


    #1 y = 0.0;
    if (f != 1.0) begin
      $display("Failed variable unlinking (deassign), expected 1.0, got %f", f);
      pass = 1'b0;
    end


    #1 f = 2.0;
    if (f != 2.0) begin
      $display("Failed release, expected 2.0, got %f", f);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule