data/full_repos/permissive/217697217/problems/01_sign_ext/testbench.v
 line:42: before: "$"
1: b'%Error: data/full_repos/permissive/217697217/problems/01_sign_ext/testbench.v:35: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;       \n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/217697217/problems/01_sign_ext/testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #2 imm = 5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/217697217/problems/01_sign_ext/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #2 imm = 12;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/217697217/problems/01_sign_ext/testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #2 imm = -5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/217697217/problems/01_sign_ext/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #2 imm = -12;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/217697217/problems/01_sign_ext/testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #2 imm = 1337;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/217697217/problems/01_sign_ext/testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #2 imm = -2019;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/217697217/problems/01_sign_ext/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #2 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

reg [11:0]imm = 0;

wire [31:0]ext_imm;
sign_ext se(.imm(imm), .ext_imm(ext_imm));


wire [31:0]ext_imm2;
sign_ext2 se2(.imm(imm), .ext_imm(ext_imm2));

wire [31:0]minus_ext_imm;
neg neg(.x(ext_imm), .minus_x(minus_ext_imm));

wire [31:0]zero;

assign zero = ext_imm + minus_ext_imm;
initial begin
    $dumpvars;
    #2 imm = 5;
    #2 imm = 12;
    #2 imm = -5;
    #2 imm = -12;
    #2 imm = 1337;
    #2 imm = -2019;
    #2 $finish;
end

endmodule
module testbench();


reg [11:0]imm = 0;

wire [31:0]ext_imm;
sign_ext se(.imm(imm), .ext_imm(ext_imm));


wire [31:0]ext_imm2;
sign_ext2 se2(.imm(imm), .ext_imm(ext_imm2));

wire [31:0]minus_ext_imm;
neg neg(.x(ext_imm), .minus_x(minus_ext_imm));

wire [31:0]zero;

assign zero = ext_imm + minus_ext_imm;
initial begin
    $dumpvars;
    #2 imm = 5;
    #2 imm = 12;
    #2 imm = -5;
    #2 imm = -12;
    #2 imm = 1337;
    #2 imm = -2019;
    #2 $finish;
end

endmodule