data/full_repos/permissive/131249673/MIPS_L_PipeLine/work/Reg_EX_MEM.v
1: b'%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/work/Reg_EX_MEM.v:1: Cannot find include file: flopr.v\n`include "flopr.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine/work,data/full_repos/permissive/131249673/flopr.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine/work,data/full_repos/permissive/131249673/flopr.v.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine/work,data/full_repos/permissive/131249673/flopr.v.sv\n             flopr.v\n             flopr.v.v\n             flopr.v.sv\n             obj_dir/flopr.v\n             obj_dir/flopr.v.v\n             obj_dir/flopr.v.sv\n%Error: Exiting due to 1 error(s)\n'
module Reg_EX_MEM( clk, rst,
	EX_instr, EX_MEM_instr,
	ALUOut, ALUSource_B, WriteDst, 
	ALUOut_EX_MEM_r, ALUSource_B_EX_MEM_r, WriteDst_EX_MEM_r,
	B_Reg, B_Reg_r);

	
	input clk, rst;

	input	[31:0]	EX_instr;
	input	[31:0]	ALUOut;
	input	[31:0]	ALUSource_B;
	input	[4:0]	WriteDst;
	input	[31:0]	B_Reg;
	

	output	[31:0]	EX_MEM_instr;
	output	[31:0]	ALUOut_EX_MEM_r;
	output	[31:0]	ALUSource_B_EX_MEM_r;
	output	[4:0]	WriteDst_EX_MEM_r;
	output	[31:0]	B_Reg_r;


   
	flopr #(.WIDTH(32))	EX_MEM_instr_r (
		.clk(clk), .rst(rst), .d(EX_instr), .q(EX_MEM_instr)
	);

	flopr #(.WIDTH(32))	ALUOut_r(
		.clk(clk), .rst(rst), .d(ALUOut), .q(ALUOut_EX_MEM_r)
	);

	flopr #(.WIDTH(32))	ALUSource_B_r(
		.clk(clk), .rst(rst), .d(ALUSource_B), .q(ALUSource_B_EX_MEM_r)
	);

	flopr #(.WIDTH(5))	WriteDst_r(
		.clk(clk), .rst(rst), .d(WriteDst), .q(WriteDst_EX_MEM_r)
	);

	flopr #(.WIDTH(32)) B_r (
		.clk(clk), .rst(rst), .d(B_Reg), .q(B_Reg_r)
	);

endmodule
module Reg_EX_MEM( clk, rst,
	EX_instr, EX_MEM_instr,
	ALUOut, ALUSource_B, WriteDst, 
	ALUOut_EX_MEM_r, ALUSource_B_EX_MEM_r, WriteDst_EX_MEM_r,
	B_Reg, B_Reg_r);


	
	input clk, rst;

	input	[31:0]	EX_instr;
	input	[31:0]	ALUOut;
	input	[31:0]	ALUSource_B;
	input	[4:0]	WriteDst;
	input	[31:0]	B_Reg;
	

	output	[31:0]	EX_MEM_instr;
	output	[31:0]	ALUOut_EX_MEM_r;
	output	[31:0]	ALUSource_B_EX_MEM_r;
	output	[4:0]	WriteDst_EX_MEM_r;
	output	[31:0]	B_Reg_r;


   
	flopr #(.WIDTH(32))	EX_MEM_instr_r (
		.clk(clk), .rst(rst), .d(EX_instr), .q(EX_MEM_instr)
	);

	flopr #(.WIDTH(32))	ALUOut_r(
		.clk(clk), .rst(rst), .d(ALUOut), .q(ALUOut_EX_MEM_r)
	);

	flopr #(.WIDTH(32))	ALUSource_B_r(
		.clk(clk), .rst(rst), .d(ALUSource_B), .q(ALUSource_B_EX_MEM_r)
	);

	flopr #(.WIDTH(5))	WriteDst_r(
		.clk(clk), .rst(rst), .d(WriteDst), .q(WriteDst_EX_MEM_r)
	);

	flopr #(.WIDTH(32)) B_r (
		.clk(clk), .rst(rst), .d(B_Reg), .q(B_Reg_r)
	);

endmodule