data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v
 line:65: before: ":"
1: b'%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:108: Cannot find include file: clogb2.vh\n`include "clogb2.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197252258/src/cr_engine/cwnd,data/full_repos/permissive/197252258/clogb2.vh\n             data/full_repos/permissive/197252258/src/cr_engine/cwnd,data/full_repos/permissive/197252258/clogb2.vh.v\n             data/full_repos/permissive/197252258/src/cr_engine/cwnd,data/full_repos/permissive/197252258/clogb2.vh.sv\n             clogb2.vh\n             clogb2.vh.v\n             clogb2.vh.sv\n             obj_dir/clogb2.vh\n             obj_dir/clogb2.vh.v\n             obj_dir/clogb2.vh.sv\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:7: Define or directive not defined: \'`FLOW_ID_W\'\n    input   [`FLOW_ID_W-1:0]            enq_fid_in,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:8: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]       enq_seq_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:9: Define or directive not defined: \'`TX_CNT_W\'\n    input   [`TX_CNT_W-1:0]             enq_seq_tx_id_in,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:11: Define or directive not defined: \'`DD_CONTEXT_W\'\n    input   [`DD_CONTEXT_W-1:0]         dd_cntxt_in,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:13: Define or directive not defined: \'`FLOW_ID_W\'\n    input   [`FLOW_ID_W-1:0]            incoming_fid_in,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:14: Define or directive not defined: \'`PKT_TYPE_W\'\n    input   [`PKT_TYPE_W-1:0]           pkt_type_in,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:15: Define or directive not defined: \'`PKT_DATA_W\'\n    input   [`PKT_DATA_W-1:0]           pkt_data_in,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:17: Define or directive not defined: \'`FLOW_ID_W\'\n    input   [`FLOW_ID_W-1:0]            timeout_fid_in,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:22: Define or directive not defined: \'`FLOW_ID_W\'\n    output  [`FLOW_ID_W-1:0]            dp_fid_out,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:24: Define or directive not defined: \'`FLOW_ID_W\'\n    output  [`FLOW_ID_W-1:0]            next_seq_fid_out,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:25: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    output  [`FLOW_SEQ_NUM_W-1:0]       next_seq_out,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:26: Define or directive not defined: \'`TX_CNT_W\'\n    output  [`TX_CNT_W-1:0]             next_seq_tx_id_out,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:28: Define or directive not defined: \'`CR_CONTEXT_W\'\n    output  [`CR_CONTEXT_W-1:0]         cr_cntxt_out\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:31: Define or directive not defined: \'`FLOW_ID_W\'\nwire    [`FLOW_ID_W-1:0]        tx_fid_in;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:36: Define or directive not defined: \'`FLOW_ID_W\'\nwire    [`FLOW_ID_W-1:0]            tx_enq_fid1;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:37: Define or directive not defined: \'`FLOW_ID_W\'\nwire    [`FLOW_ID_W-1:0]            tx_enq_fid2;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:39: Define or directive not defined: \'`CR_CONTEXT_W\'\nassign  cr_cntxt_out  = {`CR_CONTEXT_W{1\'b0}};\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:62: Define or directive not defined: \'`FLOW_ID_W\'\nreg     [`FLOW_ID_W - 1:0]      queue_w_data_0;    \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:63: Define or directive not defined: \'`FLOW_ID_W\'\nreg     [`FLOW_ID_W - 1:0]      queue_w_data_1;    \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:65: Define or directive not defined: \'`FLOW_ID_W\'\nwire    [`FLOW_ID_W:0]          ni_fifo_size;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:65: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire    [`FLOW_ID_W:0]          ni_fifo_size;\n                   ^\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:69: Define or directive not defined: \'`FLOW_ID_W\'\nwire    [`FLOW_ID_W - 1:0]      tx_fid_tmp;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:72: Define or directive not defined: \'`FLOW_ID_NONE\'\nassign tx_fifo_w_val_0 = queue_w_data_0 != `FLOW_ID_NONE;\n                                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:72: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign tx_fifo_w_val_0 = queue_w_data_0 != `FLOW_ID_NONE;\n                                                        ^\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:73: Define or directive not defined: \'`FLOW_ID_NONE\'\nassign tx_fifo_w_val_1 = queue_w_data_1 != `FLOW_ID_NONE;\n                                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:73: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign tx_fifo_w_val_1 = queue_w_data_1 != `FLOW_ID_NONE;\n                                                        ^\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:77: Define or directive not defined: \'`FLOW_ID_NONE\'\n        queue_w_data_0 <= `FLOW_ID_NONE;\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:77: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        queue_w_data_0 <= `FLOW_ID_NONE;\n                                       ^\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:78: Define or directive not defined: \'`FLOW_ID_NONE\'\n        queue_w_data_1 <= `FLOW_ID_NONE;\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:78: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        queue_w_data_1 <= `FLOW_ID_NONE;\n                                       ^\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:86: Define or directive not defined: \'`FLOW_ID_NONE\'\nassign tx_fid_in = tx_val ? tx_fid_tmp : `FLOW_ID_NONE;\n                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign tx_fid_in = tx_val ? tx_fid_tmp : `FLOW_ID_NONE;\n                                                      ^\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:88: Define or directive not defined: \'`FLOW_ID_W\'\nfifo_2w #(.FIFO_WIDTH  (`FLOW_ID_W     ),\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/cr_engine/cwnd/cr_engine.v:89: Define or directive not defined: \'`MAX_FLOW_CNT\'\n          .FIFO_DEPTH  (`MAX_FLOW_CNT  ))\n                        ^~~~~~~~~~~~~\n%Error: Exiting due to 35 error(s)\n'
module cr_engine (
    input                               clk,
    input                               rst_n,    

    input   [`FLOW_ID_W-1:0]            enq_fid_in,
    input   [`FLOW_SEQ_NUM_W-1:0]       enq_seq_in,
    input   [`TX_CNT_W-1:0]             enq_seq_tx_id_in,

    input   [`DD_CONTEXT_W-1:0]         dd_cntxt_in,

    input   [`FLOW_ID_W-1:0]            incoming_fid_in,
    input   [`PKT_TYPE_W-1:0]           pkt_type_in,
    input   [`PKT_DATA_W-1:0]           pkt_data_in,

    input   [`FLOW_ID_W-1:0]            timeout_fid_in,

    input                               tx_val,

    
    output  [`FLOW_ID_W-1:0]            dp_fid_out,
    
    output  [`FLOW_ID_W-1:0]            next_seq_fid_out,
    output  [`FLOW_SEQ_NUM_W-1:0]       next_seq_out,
    output  [`TX_CNT_W-1:0]             next_seq_tx_id_out,

    output  [`CR_CONTEXT_W-1:0]         cr_cntxt_out
);

wire    [`FLOW_ID_W-1:0]        tx_fid_in;




wire    [`FLOW_ID_W-1:0]            tx_enq_fid1;
wire    [`FLOW_ID_W-1:0]            tx_enq_fid2;

assign  cr_cntxt_out  = {`CR_CONTEXT_W{1'b0}};

cr_core  core   (.clk                       (clk                    ),
                 .rst_n                     (rst_n                  ),
                 .enq_fid_in                (enq_fid_in             ),
                 .enq_seq_in                (enq_seq_in             ),
                 .enq_seq_tx_id_in          (enq_seq_tx_id_in       ),
                 .tx_fid_in                 (tx_fid_in              ),

                 .tx_enq_fid1               (tx_enq_fid1            ),
                 .tx_enq_fid2               (tx_enq_fid2            ),
                 .next_seq                  (next_seq_out           ),
                 .next_seq_tx_id            (next_seq_tx_id_out     ),
                 .next_seq_fid              (next_seq_fid_out       ),
                 .dp_fid                    (dp_fid_out             ));
                 




wire    tx_fifo_w_val_0;
wire    tx_fifo_w_val_1;

reg     [`FLOW_ID_W - 1:0]      queue_w_data_0;    
reg     [`FLOW_ID_W - 1:0]      queue_w_data_1;    

wire    [`FLOW_ID_W:0]          ni_fifo_size;
wire                            ni_fifo_full;
wire                            ni_fifo_data_avail;

wire    [`FLOW_ID_W - 1:0]      tx_fid_tmp;


assign tx_fifo_w_val_0 = queue_w_data_0 != `FLOW_ID_NONE;
assign tx_fifo_w_val_1 = queue_w_data_1 != `FLOW_ID_NONE;

always @(posedge clk) begin
    if (~rst_n) begin
        queue_w_data_0 <= `FLOW_ID_NONE;
        queue_w_data_1 <= `FLOW_ID_NONE;
    end
    else begin
        queue_w_data_0 <= tx_enq_fid1;
        queue_w_data_1 <= tx_enq_fid2;
    end 
end

assign tx_fid_in = tx_val ? tx_fid_tmp : `FLOW_ID_NONE;

fifo_2w #(.FIFO_WIDTH  (`FLOW_ID_W     ),
          .FIFO_DEPTH  (`MAX_FLOW_CNT  ))
                 tx_fifo(.clk           (clk                ),
                         .rst_n         (rst_n              ),
                         
                         .w_val_0       (tx_fifo_w_val_0    ),
                         .w_data_0      (queue_w_data_0     ),
                         
                         .w_val_1       (tx_fifo_w_val_1    ),
                         .w_data_1      (queue_w_data_1     ),

                         .r_val         (tx_val             ),
                         .r_data        (tx_fid_tmp         ),

                         .size          (ni_fifo_size       ),
                         .full          (ni_fifo_full       ),
                         .data_avail    (ni_fifo_data_avail ));



`include "clogb2.vh"
endmodule
module cr_engine (
    input                               clk,
    input                               rst_n,    

    input   [`FLOW_ID_W-1:0]            enq_fid_in,
    input   [`FLOW_SEQ_NUM_W-1:0]       enq_seq_in,
    input   [`TX_CNT_W-1:0]             enq_seq_tx_id_in,

    input   [`DD_CONTEXT_W-1:0]         dd_cntxt_in,

    input   [`FLOW_ID_W-1:0]            incoming_fid_in,
    input   [`PKT_TYPE_W-1:0]           pkt_type_in,
    input   [`PKT_DATA_W-1:0]           pkt_data_in,

    input   [`FLOW_ID_W-1:0]            timeout_fid_in,

    input                               tx_val,

    
    output  [`FLOW_ID_W-1:0]            dp_fid_out,
    
    output  [`FLOW_ID_W-1:0]            next_seq_fid_out,
    output  [`FLOW_SEQ_NUM_W-1:0]       next_seq_out,
    output  [`TX_CNT_W-1:0]             next_seq_tx_id_out,

    output  [`CR_CONTEXT_W-1:0]         cr_cntxt_out
);


wire    [`FLOW_ID_W-1:0]        tx_fid_in;




wire    [`FLOW_ID_W-1:0]            tx_enq_fid1;
wire    [`FLOW_ID_W-1:0]            tx_enq_fid2;

assign  cr_cntxt_out  = {`CR_CONTEXT_W{1'b0}};

cr_core  core   (.clk                       (clk                    ),
                 .rst_n                     (rst_n                  ),
                 .enq_fid_in                (enq_fid_in             ),
                 .enq_seq_in                (enq_seq_in             ),
                 .enq_seq_tx_id_in          (enq_seq_tx_id_in       ),
                 .tx_fid_in                 (tx_fid_in              ),

                 .tx_enq_fid1               (tx_enq_fid1            ),
                 .tx_enq_fid2               (tx_enq_fid2            ),
                 .next_seq                  (next_seq_out           ),
                 .next_seq_tx_id            (next_seq_tx_id_out     ),
                 .next_seq_fid              (next_seq_fid_out       ),
                 .dp_fid                    (dp_fid_out             ));
                 




wire    tx_fifo_w_val_0;
wire    tx_fifo_w_val_1;

reg     [`FLOW_ID_W - 1:0]      queue_w_data_0;    
reg     [`FLOW_ID_W - 1:0]      queue_w_data_1;    

wire    [`FLOW_ID_W:0]          ni_fifo_size;
wire                            ni_fifo_full;
wire                            ni_fifo_data_avail;

wire    [`FLOW_ID_W - 1:0]      tx_fid_tmp;


assign tx_fifo_w_val_0 = queue_w_data_0 != `FLOW_ID_NONE;
assign tx_fifo_w_val_1 = queue_w_data_1 != `FLOW_ID_NONE;

always @(posedge clk) begin
    if (~rst_n) begin
        queue_w_data_0 <= `FLOW_ID_NONE;
        queue_w_data_1 <= `FLOW_ID_NONE;
    end
    else begin
        queue_w_data_0 <= tx_enq_fid1;
        queue_w_data_1 <= tx_enq_fid2;
    end 
end

assign tx_fid_in = tx_val ? tx_fid_tmp : `FLOW_ID_NONE;

fifo_2w #(.FIFO_WIDTH  (`FLOW_ID_W     ),
          .FIFO_DEPTH  (`MAX_FLOW_CNT  ))
                 tx_fifo(.clk           (clk                ),
                         .rst_n         (rst_n              ),
                         
                         .w_val_0       (tx_fifo_w_val_0    ),
                         .w_data_0      (queue_w_data_0     ),
                         
                         .w_val_1       (tx_fifo_w_val_1    ),
                         .w_data_1      (queue_w_data_1     ),

                         .r_val         (tx_val             ),
                         .r_data        (tx_fid_tmp         ),

                         .size          (ni_fifo_size       ),
                         .full          (ni_fifo_full       ),
                         .data_avail    (ni_fifo_data_avail ));



`include "clogb2.vh"
endmodule