data/full_repos/permissive/189193559/01/Blinky.v
data/verilator_xmls/0ed6990e-aeca-480c-89aa-9958f9998739.xml
module Blinky(
    RST, CLK, LED
    );


    input RST, CLK;
    output LED;


    reg [31:0] cnt_led;
    reg led_buf;


    assign LED = led_buf;

    initial begin
        cnt_led <= 32'd0;
        led_buf <= 0;
    end

    always @(posedge CLK) begin

        if(RST == 1) begin
            cnt_led <= 32'd0;
            led_buf <= 0;
        end
        else begin
            if(cnt_led >= 32'd62500000) begin
                cnt_led <= 32'd0;
                led_buf <= ~led_buf;
            end
            else begin
                cnt_led <= cnt_led + 32'd1;
            end
        end
    end

endmodule
module Blinky(
    RST, CLK, LED
    );



    input RST, CLK;
    output LED;


    reg [31:0] cnt_led;
    reg led_buf;


    assign LED = led_buf;

    initial begin
        cnt_led <= 32'd0;
        led_buf <= 0;
    end

    always @(posedge CLK) begin

        if(RST == 1) begin
            cnt_led <= 32'd0;
            led_buf <= 0;
        end
        else begin
            if(cnt_led >= 32'd62500000) begin
                cnt_led <= 32'd0;
                led_buf <= ~led_buf;
            end
            else begin
                cnt_led <= cnt_led + 32'd1;
            end
        end
    end

endmodule