data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v
1: b'%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:18: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_1, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:19: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_1, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:20: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_1, coutb, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:21: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(gnd, net_11, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:22: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, coutb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:23: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, net_23, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:24: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_23, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:25: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_7(gnd, net_23, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:26: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_8(net_23, sb, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:27: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_9(gnd, net_33, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:28: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_10(net_33, net_32, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:29: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_11(net_32, sb, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:30: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_12(gnd, cout, coutb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:31: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_13(gnd, s, sb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:32: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(sb, net_92, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:33: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(net_92, net_90, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:34: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_90, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:35: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(sb, net_94, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:36: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(net_94, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:37: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_6(net_94, vdd, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:38: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_7(net_94, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:39: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_8(cout, vdd, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:40: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_9(net_95, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:41: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_10(coutb, net_95, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:42: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_11(net_111, vdd, a);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:43: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_12(net_111, vdd, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:44: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_13(coutb, net_111, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:45: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_14(s, vdd, sb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:54: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, y, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:55: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:67: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_5, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:68: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_5, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:69: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:70: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:82: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_0, net_1, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:83: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_0, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:84: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, Y, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:85: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(net_11, Y, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:86: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_11, net_1);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:87: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_1, vdd, A);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:88: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_1, vdd, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:89: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(Y, vdd, net_1);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:90: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_28, vdd, B);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/PPR.v:91: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(Y, net_28, A);\n          ^~~~~~\n%Error: Exiting due to 44 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PPR(PP0, PP1, PP2, PP3, Sign0, Sign1, Sign2, C0, C1, C10, C11, C12, C2, 
      C3, C4, C5, C6, C7, C8, C9, S0, S1, S10, S11, S12, S2, S3, S4, S5, S6, 
      S7, S8, S9);
  input [8:0] PP0;
  input [8:0] PP1;
  input [8:0] PP2;
  input [8:0] PP3;
  input Sign0;
  input Sign1;
  input Sign2;
  output C0;
  output C1;
  output C10;
  output C11;
  output C12;
  output C2;
  output C3;
  output C4;
  output C5;
  output C6;
  output C7;
  output C8;
  output C9;
  output S0;
  output S1;
  output S10;
  output S11;
  output S12;
  output S2;
  output S3;
  output S4;
  output S5;
  output S6;
  output S7;
  output S8;
  output S9;

  supply1 vdd;
  supply0 gnd;
  wire FTC_19_Cout, net_202, net_214, net_221, net_226, net_239, net_244;
  wire net_253, net_262, net_271, net_284, net_364, net_366;

  wordlib8__FTC FTC_3(.Cin(gnd), .I1(PP0[2]), .I2(PP1[0]), .I3(gnd), .I4(gnd), 
      .C(C0), .Cout(net_364), .S(S0));
  wordlib8__FTC FTC_6(.Cin(net_364), .I1(PP0[3]), .I2(PP1[1]), .I3(gnd), 
      .I4(gnd), .C(C1), .Cout(net_366), .S(S1));
  wordlib8__FTC FTC_8(.Cin(net_366), .I1(PP0[4]), .I2(PP1[2]), .I3(PP2[0]), 
      .I4(gnd), .C(C2), .Cout(net_202), .S(S2));
  wordlib8__FTC FTC_9(.Cin(net_202), .I1(PP0[5]), .I2(PP1[3]), .I3(PP2[1]), 
      .I4(gnd), .C(C3), .Cout(net_214), .S(S3));
  wordlib8__FTC FTC_10(.Cin(net_214), .I1(PP0[6]), .I2(PP1[4]), .I3(PP2[2]), 
      .I4(PP3[0]), .C(C4), .Cout(net_221), .S(S4));
  wordlib8__FTC FTC_11(.Cin(net_221), .I1(PP0[7]), .I2(PP1[5]), .I3(PP2[3]), 
      .I4(PP3[1]), .C(C5), .Cout(net_226), .S(S5));
  wordlib8__FTC FTC_12(.Cin(net_226), .I1(PP0[8]), .I2(PP1[6]), .I3(PP2[4]), 
      .I4(PP3[2]), .C(C6), .Cout(net_239), .S(S6));
  wordlib8__FTC FTC_13(.Cin(net_239), .I1(Sign0), .I2(PP1[7]), .I3(PP2[5]), 
      .I4(PP3[3]), .C(C7), .Cout(net_244), .S(S7));
  wordlib8__FTC FTC_14(.Cin(net_244), .I1(Sign0), .I2(PP1[8]), .I3(PP2[6]), 
      .I4(PP3[4]), .C(C8), .Cout(net_253), .S(S8));
  wordlib8__FTC FTC_15(.Cin(net_253), .I1(Sign0), .I2(Sign1), .I3(PP2[7]), 
      .I4(PP3[5]), .C(C9), .Cout(net_262), .S(S9));
  wordlib8__FTC FTC_17(.Cin(net_262), .I1(Sign0), .I2(Sign1), .I3(PP2[8]), 
      .I4(PP3[6]), .C(C10), .Cout(net_271), .S(S10));
  wordlib8__FTC FTC_18(.Cin(net_271), .I1(Sign0), .I2(Sign1), .I3(Sign2), 
      .I4(PP3[7]), .C(C11), .Cout(net_284), .S(S11));
  wordlib8__FTC FTC_19(.Cin(net_284), .I1(Sign0), .I2(Sign1), .I3(Sign2), 
      .I4(PP3[8]), .C(C12), .Cout(FTC_19_Cout), .S(S12));
endmodule
module PPR(PP0, PP1, PP2, PP3, Sign0, Sign1, Sign2, C0, C1, C10, C11, C12, C2, 
      C3, C4, C5, C6, C7, C8, C9, S0, S1, S10, S11, S12, S2, S3, S4, S5, S6, 
      S7, S8, S9);

  input [8:0] PP0;
  input [8:0] PP1;
  input [8:0] PP2;
  input [8:0] PP3;
  input Sign0;
  input Sign1;
  input Sign2;
  output C0;
  output C1;
  output C10;
  output C11;
  output C12;
  output C2;
  output C3;
  output C4;
  output C5;
  output C6;
  output C7;
  output C8;
  output C9;
  output S0;
  output S1;
  output S10;
  output S11;
  output S12;
  output S2;
  output S3;
  output S4;
  output S5;
  output S6;
  output S7;
  output S8;
  output S9;

  supply1 vdd;
  supply0 gnd;
  wire FTC_19_Cout, net_202, net_214, net_221, net_226, net_239, net_244;
  wire net_253, net_262, net_271, net_284, net_364, net_366;

  wordlib8__FTC FTC_3(.Cin(gnd), .I1(PP0[2]), .I2(PP1[0]), .I3(gnd), .I4(gnd), 
      .C(C0), .Cout(net_364), .S(S0));
  wordlib8__FTC FTC_6(.Cin(net_364), .I1(PP0[3]), .I2(PP1[1]), .I3(gnd), 
      .I4(gnd), .C(C1), .Cout(net_366), .S(S1));
  wordlib8__FTC FTC_8(.Cin(net_366), .I1(PP0[4]), .I2(PP1[2]), .I3(PP2[0]), 
      .I4(gnd), .C(C2), .Cout(net_202), .S(S2));
  wordlib8__FTC FTC_9(.Cin(net_202), .I1(PP0[5]), .I2(PP1[3]), .I3(PP2[1]), 
      .I4(gnd), .C(C3), .Cout(net_214), .S(S3));
  wordlib8__FTC FTC_10(.Cin(net_214), .I1(PP0[6]), .I2(PP1[4]), .I3(PP2[2]), 
      .I4(PP3[0]), .C(C4), .Cout(net_221), .S(S4));
  wordlib8__FTC FTC_11(.Cin(net_221), .I1(PP0[7]), .I2(PP1[5]), .I3(PP2[3]), 
      .I4(PP3[1]), .C(C5), .Cout(net_226), .S(S5));
  wordlib8__FTC FTC_12(.Cin(net_226), .I1(PP0[8]), .I2(PP1[6]), .I3(PP2[4]), 
      .I4(PP3[2]), .C(C6), .Cout(net_239), .S(S6));
  wordlib8__FTC FTC_13(.Cin(net_239), .I1(Sign0), .I2(PP1[7]), .I3(PP2[5]), 
      .I4(PP3[3]), .C(C7), .Cout(net_244), .S(S7));
  wordlib8__FTC FTC_14(.Cin(net_244), .I1(Sign0), .I2(PP1[8]), .I3(PP2[6]), 
      .I4(PP3[4]), .C(C8), .Cout(net_253), .S(S8));
  wordlib8__FTC FTC_15(.Cin(net_253), .I1(Sign0), .I2(Sign1), .I3(PP2[7]), 
      .I4(PP3[5]), .C(C9), .Cout(net_262), .S(S9));
  wordlib8__FTC FTC_17(.Cin(net_262), .I1(Sign0), .I2(Sign1), .I3(PP2[8]), 
      .I4(PP3[6]), .C(C10), .Cout(net_271), .S(S10));
  wordlib8__FTC FTC_18(.Cin(net_271), .I1(Sign0), .I2(Sign1), .I3(Sign2), 
      .I4(PP3[7]), .C(C11), .Cout(net_284), .S(S11));
  wordlib8__FTC FTC_19(.Cin(net_284), .I1(Sign0), .I2(Sign1), .I3(Sign2), 
      .I4(PP3[8]), .C(C12), .Cout(FTC_19_Cout), .S(S12));
endmodule