data/full_repos/permissive/106966316/memoriaintrucciones_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Error: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:30: Cannot find file containing module: \'memoriaintrucciones\'\nmemoriaintrucciones uut(\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoriaintrucciones\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoriaintrucciones.v\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/memoriaintrucciones.sv\n             memoriaintrucciones\n             memoriaintrucciones.v\n             memoriaintrucciones.sv\n             obj_dir/memoriaintrucciones\n             obj_dir/memoriaintrucciones.v\n             obj_dir/memoriaintrucciones.sv\n%Warning-WIDTH: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:50: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                : ... In instance memoriaintrucciones_tb\ndireinstru = 5\'b00000;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:52: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h1\' generates 5 bits.\n                                                                                : ... In instance memoriaintrucciones_tb\ndireinstru = 5\'b00001;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:54: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h2\' generates 5 bits.\n                                                                                : ... In instance memoriaintrucciones_tb\ndireinstru = 5\'b00010;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/106966316/memoriaintrucciones_tb.v:56: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h3\' generates 5 bits.\n                                                                                : ... In instance memoriaintrucciones_tb\ndireinstru = 5\'b00011;\n           ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memoriaintrucciones_tb;

   reg [5:0] direinstru;
   wire [31:0] instru;
   reg clk;
	reg reset;
    
memoriaintrucciones uut(
    .direinstru(direinstru),
    .instru(instru),
    .clk(clk)
 );

always begin 

clk = 1'b1;
#50;
clk = 1'b0;
#50;

end
    
initial begin
reset = 1'b1;
#100
reset = 1'b0;
#100
direinstru = 5'b00000;
#100;
direinstru = 5'b00001;
#100;
direinstru = 5'b00010;
#100;
direinstru = 5'b00011;


end

endmodule
module memoriaintrucciones_tb;


   reg [5:0] direinstru;
   wire [31:0] instru;
   reg clk;
	reg reset;
    
memoriaintrucciones uut(
    .direinstru(direinstru),
    .instru(instru),
    .clk(clk)
 );

always begin 

clk = 1'b1;
#50;
clk = 1'b0;
#50;

end
    
initial begin
reset = 1'b1;
#100
reset = 1'b0;
#100
direinstru = 5'b00000;
#100;
direinstru = 5'b00001;
#100;
direinstru = 5'b00010;
#100;
direinstru = 5'b00011;


end

endmodule