data/full_repos/permissive/114811571/test/samples/generated/generated.v
data/verilator_xmls/34188a8e-aa1f-4e49-9bb2-e954645c3c67.xml
module generated #(
                   parameter DataWidth = 16
) (input [DataWidth - 1 : 0] loadVal,
   output [DataWidth - 1 : 0] resVal,
   input                      clk);

   reg [DataWidth - 1 : 0]    tmp;

   always @(posedge clk) begin
      tmp <= loadVal;
   end

   assign resVal = tmp + 1;

endmodule
module generated #(
                   parameter DataWidth = 16
) (input [DataWidth - 1 : 0] loadVal,
   output [DataWidth - 1 : 0] resVal,
   input                      clk);


   reg [DataWidth - 1 : 0]    tmp;

   always @(posedge clk) begin
      tmp <= loadVal;
   end

   assign resVal = tmp + 1;

endmodule