data/full_repos/permissive/115035459/verilog/src/lib/easypll.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/easypll.v:66: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                    : ... Top module \'easypll\'\nmodule easypll #(\n       ^~~~~~~\n                                                                                    : ... Top module \'pll_pad\'\nmodule pll_pad #(\n       ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/easypll.v:76: Cannot find file containing module: \'SB_PLL40_PAD\'\n SB_PLL40_PAD #(\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/SB_PLL40_PAD\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/SB_PLL40_PAD.v\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/SB_PLL40_PAD.sv\n             SB_PLL40_PAD\n             SB_PLL40_PAD.v\n             SB_PLL40_PAD.sv\n             obj_dir/SB_PLL40_PAD\n             obj_dir/SB_PLL40_PAD.v\n             obj_dir/SB_PLL40_PAD.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/easypll.v:23: Cannot find file containing module: \'SB_PLL40_CORE\'\n SB_PLL40_CORE #(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module easypll #(
	parameter DIVR=0,
	parameter DIVF=63,
	parameter DIVQ=3,
	parameter FILTER_RANGE=1
) (
	input clock_input,
	input reset_active_low,

	output global_clock_output,
	output pll_is_locked
);

	SB_PLL40_CORE #(

		.FEEDBACK_PATH("SIMPLE"),













		.DIVR(DIVR),
		.DIVF(DIVF),
		.DIVQ(DIVQ),
		.FILTER_RANGE(FILTER_RANGE)



	) my_pll_instance (

		.REFERENCECLK(clock_input),
		.PLLOUTGLOBAL(global_clock_output),






		.RESETB(reset_active_low),




		.LOCK(pll_is_locked)
	);
endmodule
module easypll #(
	parameter DIVR=0,
	parameter DIVF=63,
	parameter DIVQ=3,
	parameter FILTER_RANGE=1
) (
	input clock_input,
	input reset_active_low,

	output global_clock_output,
	output pll_is_locked
);


	SB_PLL40_CORE #(

		.FEEDBACK_PATH("SIMPLE"),













		.DIVR(DIVR),
		.DIVF(DIVF),
		.DIVQ(DIVQ),
		.FILTER_RANGE(FILTER_RANGE)



	) my_pll_instance (

		.REFERENCECLK(clock_input),
		.PLLOUTGLOBAL(global_clock_output),






		.RESETB(reset_active_low),




		.LOCK(pll_is_locked)
	);
endmodule