data/full_repos/permissive/201488448/1_verilog/16_repeat.v
data/verilator_xmls/234d058f-06fd-44f1-8e26-96c8466df7a5.xml
module top_module (
	input [7:0] in,
	output [31:0] out
);




	assign out = { {24{in[7]}}, in };
	
endmodule
module top_module (
	input [7:0] in,
	output [31:0] out
);





	assign out = { {24{in[7]}}, in };
	
endmodule