data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim_main.sv
 line:14: before: "*"
1: b"%Error: data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top/tb_sim_main.sv:11: Cannot find file containing module: 'ultra96v2_rtos'\n    ultra96v2_rtos\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top,data/full_repos/permissive/2084115/ultra96v2_rtos\n             data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top,data/full_repos/permissive/2084115/ultra96v2_rtos.v\n             data/full_repos/permissive/2084115/projects/ultra96v2_rtos/sim/tb_top,data/full_repos/permissive/2084115/ultra96v2_rtos.sv\n             ultra96v2_rtos\n             ultra96v2_rtos.v\n             ultra96v2_rtos.sv\n             obj_dir/ultra96v2_rtos\n             obj_dir/ultra96v2_rtos.v\n             obj_dir/ultra96v2_rtos.sv\n%Error: Exiting due to 1 error(s)\n"
module tb_sim_main();

    logic   [1:0]   led;
    
    ultra96v2_rtos
        i_top
            (
                .*
            );
    
endmodule
module tb_sim_main();


    logic   [1:0]   led;
    
    ultra96v2_rtos
        i_top
            (
                .*
            );
    
endmodule