data/full_repos/permissive/133819542/src/ctrl.v
1: b'%Error: data/full_repos/permissive/133819542/src/ctrl.v:12: Cannot find include file: const.v\n`include "const.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v.v\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v.sv\n             const.v\n             const.v.v\n             const.v.sv\n             obj_dir/const.v\n             obj_dir/const.v.v\n             obj_dir/const.v.sv\n%Error: data/full_repos/permissive/133819542/src/ctrl.v:18: Define or directive not defined: \'`StallBus\'\n    output  reg [`StallBus]   stall                \n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ctrl.v:18: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    output  reg [`StallBus]   stall                \n                          ^\n%Error: data/full_repos/permissive/133819542/src/ctrl.v:22: Define or directive not defined: \'`RESET_ENABLE\'\n        if(rst == `RESET_ENABLE) begin\n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/ctrl.v:24: Define or directive not defined: \'`STOP\'\n        end else if (stallreq_from_ex == `STOP) begin \n                                         ^~~~~\n%Error: data/full_repos/permissive/133819542/src/ctrl.v:26: Define or directive not defined: \'`STOP\'\n        end else if (stallreq_from_id == `STOP) begin\n                                         ^~~~~\n%Error: Exiting due to 6 error(s)\n'
module ctrl (
    input  wire               rst              ,
    input  wire               stallreq_from_id ,
    input  wire               stallreq_from_ex ,
    output  reg [`StallBus]   stall
);
    
    always @(*) begin
        if(rst == `RESET_ENABLE) begin
            stall <= 6'b000000;
        end else if (stallreq_from_ex == `STOP) begin 
            stall <= 6'b001111;
        end else if (stallreq_from_id == `STOP) begin
            stall <= 6'b000111;
        end else begin 
            stall <= 6'b000000;
        end
    end
endmodule
module ctrl (
    input  wire               rst              ,
    input  wire               stallreq_from_id ,
    input  wire               stallreq_from_ex ,
    output  reg [`StallBus]   stall
);

    
    always @(*) begin
        if(rst == `RESET_ENABLE) begin
            stall <= 6'b000000;
        end else if (stallreq_from_ex == `STOP) begin 
            stall <= 6'b001111;
        end else if (stallreq_from_id == `STOP) begin
            stall <= 6'b000111;
        end else begin 
            stall <= 6'b000000;
        end
    end
endmodule