data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/mac/mac_9/mac_9.v
data/verilator_xmls/1be6fbb3-5a00-446b-b210-e32632f8671c.xml
module mac_9(a, b, c, out);
parameter DATA_WIDTH = 9;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out = a * b + c;

endmodule
module mac_9(a, b, c, out);

parameter DATA_WIDTH = 9;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out = a * b + c;

endmodule