data/full_repos/permissive/129797190/rtl/cpu/branch.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/129797190/rtl/cpu/branch.v:28: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'branch_pc_mux\'\nmodule branch_pc_mux (\n       ^~~~~~~~~~~~~\n                                                                           : ... Top module \'branch_unit\'\nmodule branch_unit (\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/branch.v:39: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'op_in\' generates 3 bits.\n                                                                        : ... In instance branch_unit\n        case (op_in)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/129797190/rtl/cpu/branch.v:25: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 65 bits.\n                                                                        : ... In instance branch_pc_mux\n    assign pc_out = {pc[63:1], 2\'b00};\n                  ^\n%Error: Exiting due to 3 warning(s)\n'
module branch_pc_mux (

    input pc_src_in,

    input [63:0] pc_in,
    input [63:0] rs1_value_in,
    input [63:0] imm_value_in,

    output wire [63:0] pc_out 
);
    wire [63:0] pc;

    assign pc = (pc_src_in ? rs1_value_in : pc_in) + imm_value_in;
    assign pc_out = {pc[63:1], 2'b00};
endmodule
module branch_pc_mux (

    input pc_src_in,

    input [63:0] pc_in,
    input [63:0] rs1_value_in,
    input [63:0] imm_value_in,

    output wire [63:0] pc_out 
);

    wire [63:0] pc;

    assign pc = (pc_src_in ? rs1_value_in : pc_in) + imm_value_in;
    assign pc_out = {pc[63:1], 2'b00};
endmodule