data/full_repos/permissive/150133337/fpga/hardware/testbench/common/clk_rst_driver.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/150133337/fpga/hardware/testbench/common/clk_rst_driver.v:7: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = !clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/150133337/fpga/hardware/testbench/common/clk_rst_driver.v:13: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clk_rst_driver (
    output reg      clk,
    output reg      reset_n,
    output wire     reset
);

always #1 clk = !clk;
assign reset = !reset_n;

initial begin
    clk = 0;
    reset_n = 0;
    @(negedge clk);
    @(negedge clk);
    reset_n = 1;
end

endmodule
module clk_rst_driver (
    output reg      clk,
    output reg      reset_n,
    output wire     reset
);


always #1 clk = !clk;
assign reset = !reset_n;

initial begin
    clk = 0;
    reset_n = 0;
    @(negedge clk);
    @(negedge clk);
    reset_n = 1;
end

endmodule