data/full_repos/permissive/188068190/ridecore-src-buggy/prioenc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/188068190/ridecore-src-buggy/prioenc.v:39: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'mask\' generates 2 bits.\n                                                                                    : ... In instance allocateunit.msku\n  out[i] = (mask < i) ? 1\'b0 : 1\'b1;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/188068190/ridecore-src-buggy/prioenc.v:18: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                    : ... In instance allocateunit.p2\n     out = i;\n         ^\n%Error: Exiting due to 2 warning(s)\n'
module maskunit  #(
		   parameter REQ_LEN = 4,
		   parameter GRANT_LEN = 2
		   )
   (
    input wire [GRANT_LEN-1:0] mask,
    input wire [REQ_LEN-1:0]   in,
    output reg [REQ_LEN-1:0]   out
   );
   
   integer 		      i;
   always @ (*) begin
      out = 0;
      for (i = 0 ; i < REQ_LEN ; i = i+1) begin
	 out[i] = (mask < i) ? 1'b0 : 1'b1;
      end
   end
endmodule
module maskunit  #(
		   parameter REQ_LEN = 4,
		   parameter GRANT_LEN = 2
		   )
   (
    input wire [GRANT_LEN-1:0] mask,
    input wire [REQ_LEN-1:0]   in,
    output reg [REQ_LEN-1:0]   out
   );

   
   integer 		      i;
   always @ (*) begin
      out = 0;
      for (i = 0 ; i < REQ_LEN ; i = i+1) begin
	 out[i] = (mask < i) ? 1'b0 : 1'b1;
      end
   end
endmodule