data/full_repos/permissive/143278/ivltests/not_a_latch2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:61: Unsupported: Ignoring delay on this delayed statement.\n      #1 ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:67: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:68: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg clk, load, drain, data;
   wire foo, bar;

   test dut (.clk(clk), .load(load), .drain(drain), .data(data),
	     .foo_nxt(foo), .bar_nxt(bar));

   (* ivl_synthesis_off *)
   initial begin
      clk = 0;
      load = 1;
      drain = 0;
      data = 1;
      #1 clk = 1;
      #1 clk = 0;
      $display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b",
	       $time, load, drain, data, foo, bar);
      if (foo !== 1 || bar !== 1) begin
	 $display("FAILED -- foo=%b, bar=%b (1)", foo, bar);
	 $finish;
      end
      data = 0;
      #1 clk = 1;
      #1 clk = 0;
      $display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b",
	       $time, load, drain, data, foo, bar);
      if (foo !== 0 || bar !== 1) begin
	 $display("FAILED -- foo=%b, bar=%b (2)", foo, bar);
	 $finish;
      end
      load = 0;
      drain = 1;
      #1 ;
      if (foo !== 0 || bar !== 0) begin
	 $display("FAILED -- foo=%b, bar=%b (3)", foo, bar);
	 $finish;
      end

      #1 clk = 1;
      #1 clk = 0;
      $display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b",
	       $time, load, drain, data, foo, bar);

      $display("PASSED");
   end

endmodule
module main;


   reg clk, load, drain, data;
   wire foo, bar;

   test dut (.clk(clk), .load(load), .drain(drain), .data(data),
	     .foo_nxt(foo), .bar_nxt(bar));

   (* ivl_synthesis_off *)
   initial begin
      clk = 0;
      load = 1;
      drain = 0;
      data = 1;
      #1 clk = 1;
      #1 clk = 0;
      $display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b",
	       $time, load, drain, data, foo, bar);
      if (foo !== 1 || bar !== 1) begin
	 $display("FAILED -- foo=%b, bar=%b (1)", foo, bar);
	 $finish;
      end
      data = 0;
      #1 clk = 1;
      #1 clk = 0;
      $display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b",
	       $time, load, drain, data, foo, bar);
      if (foo !== 0 || bar !== 1) begin
	 $display("FAILED -- foo=%b, bar=%b (2)", foo, bar);
	 $finish;
      end
      load = 0;
      drain = 1;
      #1 ;
      if (foo !== 0 || bar !== 0) begin
	 $display("FAILED -- foo=%b, bar=%b (3)", foo, bar);
	 $finish;
      end

      #1 clk = 1;
      #1 clk = 0;
      $display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b",
	       $time, load, drain, data, foo, bar);

      $display("PASSED");
   end

endmodule