data/full_repos/permissive/220281533/inst_parser.v
1: b'%Warning-WIDTH: data/full_repos/permissive/220281533/inst_parser.v:45: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s SEL generates 27 bits.\n                                                                     : ... In instance inst_parser\n   address = instruction[26:0];\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module inst_parser(
	output wire [5:0] opcode,
	output reg [4:0] rs, rt, rd, shamt, 
	output reg [5:0] funct,
	output reg[15:0] immediate,
	output reg [25:0] address,
	input [31:0] instruction, p_count
);

	assign opcode = instruction[31:26];
	
	always @(instruction) begin

		if(opcode == 6'h0) begin
			shamt = instruction[10:6];
			rd = instruction[15:11];
			rt = instruction[20:16];
			rs = instruction[25:21];
			funct = instruction[5:0];
		end

		else if(opcode == 6'h2 | opcode == 6'h3) begin
			address = instruction[26:0];
		end

		else begin
			rt = instruction[20:16];
			rs = instruction[25:21];
			immediate = instruction[15:0];
		end
	end
	
endmodule
module inst_parser(
	output wire [5:0] opcode,
	output reg [4:0] rs, rt, rd, shamt, 
	output reg [5:0] funct,
	output reg[15:0] immediate,
	output reg [25:0] address,
	input [31:0] instruction, p_count
);


	assign opcode = instruction[31:26];
	
	always @(instruction) begin

		if(opcode == 6'h0) begin
			shamt = instruction[10:6];
			rd = instruction[15:11];
			rt = instruction[20:16];
			rs = instruction[25:21];
			funct = instruction[5:0];
		end

		else if(opcode == 6'h2 | opcode == 6'h3) begin
			address = instruction[26:0];
		end

		else begin
			rt = instruction[20:16];
			rs = instruction[25:21];
			immediate = instruction[15:0];
		end
	end
	
endmodule