data/full_repos/permissive/206994752/shuffler.v
 line:22 column:33: Illegal character "'"
1: b"%Error: data/full_repos/permissive/206994752/shuffler.v:160: syntax error, unexpected '=', expecting ',' or '}'\n                        var_control = 1;\n                                    ^\n%Error: data/full_repos/permissive/206994752/shuffler.v:182: syntax error, unexpected endcase\n    endcase\n    ^~~~~~~\n%Error: Cannot continue\n"
module shuffler
(
    input start,
    input [3:0] memData,
    input clock,

    output reg [5:0] nextA,
    output reg [3:0] newData,
    output reg wren,
    output reg memClock, 
    output reg finish

);

reg var_control;
reg [3:0] memF;
reg [3:0] memS;
reg [5:0] addrsF;
reg [5:0] addrsS;
reg [3:0] stateA, stateF;

parameter   Begin           = 4'b 0000,
            Read_Ram_F      = 4'b 0001,
            Save_Ram_F      = 4'b 0010,
            Next_Addrs      = 4'b 0011,
            Read_Ram_S      = 4'b 0100,
            Save_Ram_S      = 4'b 0101,
            Write_S         = 4'b 0110,
            Return_Addrs    = 4'b 0111,
            Write_F         = 4'b 1000,
            Controler       = 4'b 1001,
            Incrementa_F    = 4'b 1010,
            Incrementa_S    = 4'b 1011,
            Decrementa_S    = 4'b 1100,
            Change_Addrs    = 4'b 1101,
            Shuffled        = 4'b 1111;


always @(posedge clock)
begin
    if (start)
        begin
            stateA <= stateF;

            case(stateF)
                Read_Ram_F:
                    memF <= memData;
                
                Read_Ram_S:
                    memS <= memData;
                
                Incrementa_F:
                    addrsF <= addrsF + 1;

                Decrementa_S:
                    addrsS <= addrsS - 2;
                
                Incrementa_S:
                    addrsS <= addrsS + 4;
            endcase
        end
    else
        begin
            stateA <= Begin;
            addrsF <= 0;
            addrsS <= 36;
            var_control <= 0;
        end
end


always @(*)
begin

    wren = 0;
    memClock = 0;
    finish = 0;
    
    case(stateA)
        Begin:
            begin
                stateF = Read_Ram_F;
                nextA = addrsF;
            end

        Read_Ram_F:
            begin
                stateF = Save_Ram_F;
                nextA = addrsF;
                memClock = 1;
            end
        
        Save_Ram_F:
            begin
                stateF = Next_Addrs;
                nextA = addrsF;
                wren = 1;
                memF = memData;
            end

        Next_Addrs:
            begin
                stateF = Read_Ram_S;
                nextA = addrsS;
            end

        Read_Ram_S:
            begin
                stateF = Save_Ram_S;
                nextA = addrsS;
                memClock = 1;
            end

        Save_Ram_S:
            begin
                stateF = Write_S;
                nextA = addrsS;
                wren = 1;
                memS = memData;
            end

        Write_S:
            begin
                stateF = Return_Addrs;
                memClock = 1;
                wren = 1;
                newData = memF;
            end

        Return_Addrs:
            begin
                stateF = Write_F;
                nextA = addrsF;
            end

        Write_F:
            begin
                stateF = Controler;
                memClock = 1;
                wren = 1;
                newData = memS;
            end

        Controler:
            begin
                if(addrsF<51)
                stateF = Incrementa_F;
                else 
                stateF = Shuffled;
            end

        Incrementa_F:
            begin
                if(var_control && addrsS<51)
                stateF = Incrementa_S;
                else if (addrsS>1)
                    begin
                    stateF = Decrementa_S;
                    if(addrsS==2){
                        var_control = 1;
                    }
                    end
            end

        Incrementa_S:
            stateF = Change_Addrs;

        Decrementa_S:
            stateF = Change_Addrs;

        Change_Addrs:
            begin
                stateF = Read_Ram_F;
                nextA = addrsF;
            end

        Shuffled:
            begin
                finish = 1;
                stateF = Shuffled;
            end
    endcase
end

endmodule
module shuffler
(
    input start,
    input [3:0] memData,
    input clock,

    output reg [5:0] nextA,
    output reg [3:0] newData,
    output reg wren,
    output reg memClock, 
    output reg finish

);


reg var_control;
reg [3:0] memF;
reg [3:0] memS;
reg [5:0] addrsF;
reg [5:0] addrsS;
reg [3:0] stateA, stateF;

parameter   Begin           = 4'b 0000,
            Read_Ram_F      = 4'b 0001,
            Save_Ram_F      = 4'b 0010,
            Next_Addrs      = 4'b 0011,
            Read_Ram_S      = 4'b 0100,
            Save_Ram_S      = 4'b 0101,
            Write_S         = 4'b 0110,
            Return_Addrs    = 4'b 0111,
            Write_F         = 4'b 1000,
            Controler       = 4'b 1001,
            Incrementa_F    = 4'b 1010,
            Incrementa_S    = 4'b 1011,
            Decrementa_S    = 4'b 1100,
            Change_Addrs    = 4'b 1101,
            Shuffled        = 4'b 1111;


always @(posedge clock)
begin
    if (start)
        begin
            stateA <= stateF;

            case(stateF)
                Read_Ram_F:
                    memF <= memData;
                
                Read_Ram_S:
                    memS <= memData;
                
                Incrementa_F:
                    addrsF <= addrsF + 1;

                Decrementa_S:
                    addrsS <= addrsS - 2;
                
                Incrementa_S:
                    addrsS <= addrsS + 4;
            endcase
        end
    else
        begin
            stateA <= Begin;
            addrsF <= 0;
            addrsS <= 36;
            var_control <= 0;
        end
end


always @(*)
begin

    wren = 0;
    memClock = 0;
    finish = 0;
    
    case(stateA)
        Begin:
            begin
                stateF = Read_Ram_F;
                nextA = addrsF;
            end

        Read_Ram_F:
            begin
                stateF = Save_Ram_F;
                nextA = addrsF;
                memClock = 1;
            end
        
        Save_Ram_F:
            begin
                stateF = Next_Addrs;
                nextA = addrsF;
                wren = 1;
                memF = memData;
            end

        Next_Addrs:
            begin
                stateF = Read_Ram_S;
                nextA = addrsS;
            end

        Read_Ram_S:
            begin
                stateF = Save_Ram_S;
                nextA = addrsS;
                memClock = 1;
            end

        Save_Ram_S:
            begin
                stateF = Write_S;
                nextA = addrsS;
                wren = 1;
                memS = memData;
            end

        Write_S:
            begin
                stateF = Return_Addrs;
                memClock = 1;
                wren = 1;
                newData = memF;
            end

        Return_Addrs:
            begin
                stateF = Write_F;
                nextA = addrsF;
            end

        Write_F:
            begin
                stateF = Controler;
                memClock = 1;
                wren = 1;
                newData = memS;
            end

        Controler:
            begin
                if(addrsF<51)
                stateF = Incrementa_F;
                else 
                stateF = Shuffled;
            end

        Incrementa_F:
            begin
                if(var_control && addrsS<51)
                stateF = Incrementa_S;
                else if (addrsS>1)
                    begin
                    stateF = Decrementa_S;
                    if(addrsS==2){
                        var_control = 1;
                    }
                    end
            end

        Incrementa_S:
            stateF = Change_Addrs;

        Decrementa_S:
            stateF = Change_Addrs;

        Change_Addrs:
            begin
                stateF = Read_Ram_F;
                nextA = addrsF;
            end

        Shuffled:
            begin
                finish = 1;
                stateF = Shuffled;
            end
    endcase
end

endmodule