data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/tart_dsp.v
None: at end of input
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/tart_dsp.v:96: Cannot find include file: tartcfg.v\n`include "tartcfg.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/tartcfg.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/tartcfg.v.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/tartcfg.v.sv\n             tartcfg.v\n             tartcfg.v.v\n             tartcfg.v.sv\n             obj_dir/tartcfg.v\n             obj_dir/tartcfg.v.v\n             obj_dir/tartcfg.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/tart_dsp.v:798: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("%12t: WB stuck.", $time);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/tart_dsp.v:799: Unsupported: Ignoring delay on this delayed statement.\n        #80 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module tart_dsp
  #(
    parameter AXNUM = 24,
    parameter NSB   = AXNUM-1,


    parameter ACCUM = 24,
    parameter BLOCK = ACCUM,
    parameter MSB   = BLOCK-1,
    parameter TRATE = 12,
    parameter TBITS = 4,


    parameter NREAD = 576,
    parameter RBITS = 10,
    parameter RSB   = RBITS-1,


    parameter XBITS = 4,
    parameter XSB   = XBITS-1,


    parameter CBITS = XBITS+RBITS,
    parameter CSB   = CBITS-1,


    parameter BBITS = 8,
    parameter BSB   = BBITS-1,
    parameter WSB   = BBITS-2,
    parameter ABITS = 12,
    parameter ASB   = ABITS-1,


    parameter PIPED = 1,
    parameter CHECK = 1,
    parameter ASYNC = 1,
    parameter RESET = 1,
    parameter VIZWR = 0,


    parameter NOISY = 0,
    parameter DELAY = 3)
   (
    input          clk_x,
    input          clk_i,
    input          rst_i,


    input          vld_i,
    input          new_i,
    input [NSB:0]  sig_i,


    input          cyc_i,
    input          stb_i,
    input          we_i,
    output         ack_o,
    output         wat_o,
    output         rty_o,
    output         err_o,
    input [1:0]    adr_i,
    input [7:0]    dat_i,
    output [7:0]   dat_o,


    input          sce_i,


    output         enabled_o,
    output         pending_o,
    output         switched_o,
    output         newblock_o,
    output         streamed_o,
    output [31:0]  checksum_o,


    output         overflow_o,
    output [XSB:0] bank_o,
    output         stuck_o,
    output         limp_o
    );





   reg             ack = 1'b0, viz = 1'b0;
   reg [BSB:0]     dat;
   wire            cyc_w, stb_w, ack_w, fetch, store;






   wire [MSB:0]    v_drx, v_dtx;
   wire [RSB:0]    v_adr;
   wire [CSB:0]    c_adr;
   wire            v_cyc, v_stb, v_we;
   wire            v_ack, v_wat, v_rty, v_err;



   wire            sram_a_ce, sram_a_we;
   wire [RSB:0]    sram_a_ad;
   wire [3:0]      sram_a_be;
   wire [31:0]     sram_a_di, sram_a_do;

   wire            sram_b_ce, sram_b_we;
   wire [ASB:0]    sram_b_ad;
   wire            sram_b_be;
   wire [7:0]      sram_b_di, sram_b_do;





   reg [4:0]       log_block = 5'h0;
   reg             enabled = 1'b0, accessed = 1'b0, available = 1'b0;
   reg             overwrite = 1'b0, overflow = 1'b0;
   wire            switched, newblock, wrapped;
   wire [31:0]     checksum;
   reg [MSB:0]     blocksize = {ACCUM{1'b0}};


   reg [XSB:0]     bank = 4'h0;
   wire [XBITS:0]  next;


   wire [BSB:0]    dsp_stream, dsp_status, dsp_debug, dsp_system;
   reg             dsp_set = 1'b0, dsp_clr = 1'b0;
   reg             new_bnk = 1'b0, upd_bnk = 1'b0, bs_upd = 1'b0;
   wire            bs_new_w;


   wire            swp_x;





   assign enabled_o  = enabled;
   assign pending_o  = available;
   assign newblock_o = newblock;
   assign streamed_o = wrapped;
   assign switched_o = switched;
   assign checksum_o = checksum;


   assign overflow_o = overflow;
   assign bank_o     = bank;
   assign stuck_o    = stuck;
   assign limp_o     = limp;


   assign next       = bank + 1;





   assign ack_o      = ack;
   assign wat_o      = 1'b0;
   assign rty_o      = 1'b0;
   assign err_o      = 1'b0;
   assign dat_o      = dat;


   assign cyc_w      = CHECK ? cyc_i : 1'b1;
   assign stb_w      = cyc_w && stb_i;
   assign ack_w      = stb_w && adr_i != `DSP_STREAM || viz;
   assign fetch      = stb_w && !we_i;
   assign store      = stb_w &&  we_i;






   assign dsp_stream = sram_b_do;
   assign dsp_status = {available,  accessed, overflow, 1'b0, bank};
   assign dsp_debug  = {    stuck,      limp,                 6'h0};
   assign dsp_system = {  enabled, overwrite,     1'b0,  log_block};









   always @(posedge clk_i)
     if (rst_i && RESET)
       ack <= #DELAY 1'b0;
     else
       ack <= #DELAY ack_w;




   always @(posedge clk_i)
     if (stb_w)
       case (adr_i)
         `DSP_STREAM: dat <= #DELAY dsp_stream;
         `DSP_STATUS: dat <= #DELAY dsp_status;
         `DSP_DEBUG:  dat <= #DELAY dsp_debug;
         `DSP_SYSTEM: dat <= #DELAY dsp_system;
         default:     dat <= #DELAY 8'bx;
       endcase







   always @(posedge clk_i)
     if (rst_i && RESET)
       viz <= #DELAY 1'b0;
     else
       viz <= #DELAY stb_w && adr_i == `DSP_STREAM;


   






   always @(posedge clk_i)
     if (rst_i) begin
        if (RESET) begin
           dsp_set   <= #DELAY 1'b0;
           dsp_clr   <= #DELAY 1'b1;
           upd_bnk   <= #DELAY 1'b0;
        end
        overwrite <= #DELAY 1'b0;
     end
     else if (store)
       case (adr_i)


         `DSP_STATUS: begin
            new_bnk <= #DELAY dat_i[XSB:0];
            upd_bnk <= #DELAY 1'b1;
         end

         `DSP_SYSTEM: begin
            dsp_set   <= #DELAY dat_i[BSB];
            dsp_clr   <= #DELAY ~dat_i[BSB];
            overwrite <= #DELAY dat_i[BSB-1];
            log_block <= #DELAY dat_i[4:0];
         end
       endcase
     else begin
        upd_bnk <= #DELAY 1'b0;
        dsp_set <= #DELAY dsp_set ? !enabled : 1'b0;
        dsp_clr <= #DELAY 1'b0;
     end








   always @(posedge clk_i)
     if (rst_i || overflow && !overwrite || dsp_clr)
       enabled <= #DELAY 1'b0;
     else if (dsp_set && vld_i && new_i)
       enabled <= #DELAY 1'b1;
     else
       enabled <= #DELAY enabled;



   assign bs_new_w = store && adr_i == `DSP_SYSTEM;

   always @(posedge clk_i) begin
      bs_upd <= #DELAY bs_new_w && !bs_upd;
      if (bs_upd)
`ifdef  __LOOKUP_BLOCKSIZE
        case (log_block)
          0:  blocksize <= #DELAY        0;
          1:  blocksize <= #DELAY        1;
          2:  blocksize <= #DELAY        3;
          3:  blocksize <= #DELAY        7;
          4:  blocksize <= #DELAY       15;
          5:  blocksize <= #DELAY       31;
          6:  blocksize <= #DELAY       63;
          7:  blocksize <= #DELAY      127;
          8:  blocksize <= #DELAY      255;
          9:  blocksize <= #DELAY      511;
          10: blocksize <= #DELAY     1023;
          11: blocksize <= #DELAY     2047;
          12: blocksize <= #DELAY     4095;
          13: blocksize <= #DELAY     8191;
          14: blocksize <= #DELAY    16383;
          15: blocksize <= #DELAY    32767;
          16: blocksize <= #DELAY    65535;
          17: blocksize <= #DELAY   131071;
          18: blocksize <= #DELAY   262143;
          19: blocksize <= #DELAY   524287;
          20: blocksize <= #DELAY  1048575;
          21: blocksize <= #DELAY  2097151;
          22: blocksize <= #DELAY  4194303;
          23: blocksize <= #DELAY  8388607;
          default:
            blocksize   <= #DELAY 16777215;
        endcase
`else

      blocksize <= #DELAY (1 << dat_i[4:0]) - 1;
`endif
   end






   always @(posedge clk_i)
     if (rst_i)
       bank <= #DELAY {XBITS{1'b0}};
`ifdef __USE_SETTABLE_BLOCK_COUNTER
     else if (upd_bnk)
       bank <= #DELAY new_bnk;
`endif
     else
       bank <= #DELAY wrapped ? next[XSB:0] : bank;





   always @(posedge clk_i)
     if (rst_i && RESET || newblock)
       accessed <= #DELAY 1'b0;
     else
       accessed <= #DELAY accessed || viz;



   always @(posedge clk_i)
     if (rst_i && RESET)
       available <= #DELAY 1'b0;
     else if (newblock)
       available <= #DELAY 1'b1;
     else if (viz)
       available <= #DELAY 1'b0;









   (* NOMERGE = "TRUE" *)
   reg [MSB:0]  block_x = {ACCUM{1'b0}}, block_s = {ACCUM{1'b0}};

   always @(posedge clk_x) begin
      block_s  <= #DELAY blocksize;
      block_x  <= #DELAY block_s;
   end








`ifdef  __USE_OVERFLOW_DETECTION

   (* NOMERGE = "TRUE" *)
   wire               overflow_x;

   (* NOMERGE = "TRUE" *)
   reg                overflow_s;



   always @(posedge clk_i) begin
      overflow_s <= #DELAY overflow_x;
      overflow   <= #DELAY overflow_s;
   end
`endif












`ifdef __USE_ASYNC_FETCH
   wire               stream_reset = ~sce_i;
`else   
   reg                stream_reset = 1'b1;

   always @(posedge clk_i)
     stream_reset <= #DELAY ~sce_i;
`endif












   wire               s_stb;
   wire               s_ack, s_wat, s_rty, s_err;
   wire [BSB:0]       s_dat;

   assign s_stb = CHECK ? stb_w && adr_i == `DSP_STREAM : stb_w;

   wb_sram_stream
     #(  .WIDTH(BBITS),
         .WORDS(NREAD << 2),
         .WBITS(ABITS),
         .RESET(1),
         .START(0),
         .TICKS(1),
         .READ (1),
         .WRITE(VIZWR),
         .USEBE(0),
         .PIPED(PIPED),
         .ASYNC(1),
         .CHECK(CHECK),
         .DELAY(DELAY)
         ) STREAM
       ( .clk_i(clk_i),
         .rst_i(stream_reset),


         .cyc_i(cyc_w),
         .stb_i(s_stb),
         .we_i (we_i),
         .ack_o(s_ack),
         .wat_o(s_wat),
         .rty_o(s_rty),
         .err_o(s_err),
         .sel_i(1'b0),
         .dat_i(dat_i),
         .dat_o(s_dat),


         .sram_ce_o(sram_b_ce),
         .sram_we_o(sram_b_we),
         .sram_be_o(sram_b_be),
         .sram_ad_o(sram_b_ad),
         .sram_do_i(sram_b_do),
         .sram_di_o(sram_b_di),
 
         .wrapped_o(wrapped)
         );








   (* NOMERGE *) reg rst_viz = 1'b1;

   always @(posedge clk_i)
     rst_viz <= #DELAY rst_i;


   parameter BSIZE = TRATE*2;
   parameter DBITS = TBITS+1;
   parameter COUNT = 24;
   parameter NBITS = 5;

   wire [31:0] v_dat;

   assign v_dtx    = v_dat[MSB:0];

   tart_visibilities
     #(  .WIDTH(32),
         .XBITS(XBITS),
         .COUNT(COUNT),
         .CBITS(NBITS),
         .BSIZE(BSIZE),
         .BBITS(DBITS),
         .CHECK(CHECK),
         .DELAY(DELAY)
         ) VIZ
       ( .clk_i(clk_i),
         .rst_i(rst_viz),


         .cyc_o(v_cyc),
         .stb_o(v_stb),
         .we_o (v_we), 
         .ack_i(v_ack),
         .wat_i(v_wat),
         .rty_i(v_rty),
         .err_i(v_err),
         .adr_o(v_adr),
         .dat_i({{32-ACCUM{1'b0}}, v_drx}),
         .dat_o(v_dat),


         .sram_ce_o(sram_a_ce),
         .sram_we_o(sram_a_we),
         .sram_be_o(sram_a_be),
         .sram_ad_o(sram_a_ad),
         .sram_do_i(sram_a_do),
         .sram_di_o(sram_a_di),


         .streamed_i(wrapped),
         .newblock_o(newblock),
         .checksum_o(checksum),


         .clk_x     (clk_x),
         .switch_x  (swp_x),
         .overflow_x(overflow_x)
         );









   (* NOMERGE *) reg rst_cor = 1'b1;

   always @(posedge clk_i)
     rst_cor <= #DELAY rst_i;



   assign c_adr = {bank, v_adr};

   tart_correlator
     #(  .ACCUM(BLOCK),
         .IBITS(AXNUM),
         .ABITS(CBITS),
         .TRATE(TRATE),
         .TBITS(TBITS),
         .XBITS(XBITS),
         .SEQRD(1),
         .DSLOW(0),
         .SSLOW(0),
         .DDUPS(0),
         .SDUPS(1),
         .PIPED(PIPED),
         .CHECK(CHECK),
         .DELAY(DELAY)
         ) COR
       ( .clk_x(clk_x),
         .clk_i(clk_i),
         .rst_i(rst_cor),

         .cyc_i(v_cyc),
         .stb_i(v_stb),
         .we_i (v_we ),
         .ack_o(v_ack),
         .wat_o(v_wat),
         .rty_o(v_rty),
         .err_o(v_err),
         .adr_i(c_adr),
         .dat_i(v_dtx),
         .dat_o(v_drx),

         .vld_i(enabled),
         .new_i(new_i),
         .sig_i(sig_i),

         .switching_o(switched),

         .sums_x_i(block_x),
         .swap_x_o(swp_x),
         .bank_x_o()
         );










   wire [15:0] sram_a_hi, sram_a_lo;


   assign sram_a_hi = {sram_a_di[31:28], sram_a_di[23:20],
                       sram_a_di[15:12], sram_a_di[7:4]};
   assign sram_a_lo = {sram_a_di[27:24], sram_a_di[19:16],
                       sram_a_di[11:8] , sram_a_di[3:0]};


   RAMB16X16X4_TDP
     #( .DELAY(DELAY)
        ) SRAM0
       (.CLKA (clk_i),
        .ENA  (sram_a_ce),
        .WEA  (sram_a_be[1:0]),
        .ADDRA(sram_a_ad),
        .DIA  (sram_a_lo),
        .DOA  (sram_a_do[15:0]),

        .CLKB (clk_i),
        .ENB  (sram_b_ce),
        .WEB  (sram_b_we),
        .ADDRB(sram_b_ad),
        .DIB  (sram_b_di[3:0]),
        .DOB  (sram_b_do[3:0])
        );


   RAMB16X16X4_TDP
     #( .DELAY(DELAY)
        ) SRAM1
       (.CLKA (clk_i),
        .ENA  (sram_a_ce),
        .WEA  (sram_a_be[3:2]),
        .ADDRA(sram_a_ad),
        .DIA  (sram_a_hi),
        .DOA  (sram_a_do[31:16]),

        .CLKB (clk_i),
        .ENB  (sram_b_ce),
        .WEB  (sram_b_we),
        .ADDRB(sram_b_ad),
        .DIB  (sram_b_di[7:4]),
        .DOB  (sram_b_do[7:4])
        );








`ifdef __RELEASE_BUILD
   wire               stuck = 1'b0;
   wire               limp  = 1'b0;

`else
   reg                stuck = 1'b0;
   reg                limp  = 1'b1;
   reg [5:0]          count = 6'h0;
   wire [5:0]         cnext = count[4:0] + 1'b1;


   always @(posedge clk_i)
     if (rst_i)
       {count, stuck} <= #DELAY 7'b0;
     else if (v_cyc && v_ack) begin
        if (!count[5])
          {count, stuck} <= #DELAY {cnext, stuck};
        else
          {count, stuck} <= #DELAY {count, 1'b1};
     end
     else if (!v_cyc)
       {count, stuck} <= #DELAY {6'h0, stuck};


   always @(posedge clk_i)
     if (rst_i)
       limp <= #DELAY 1'b1;
     else if (v_cyc && v_ack && enabled)
       limp <= #DELAY 1'b0;

   always @(posedge clk_i)
     if (stuck) begin
        #10 $display("%12t: WB stuck.", $time);
        #80 $finish;
     end
`endif


endmodule
module tart_dsp
  #(
    parameter AXNUM = 24,
    parameter NSB   = AXNUM-1,


    parameter ACCUM = 24,
    parameter BLOCK = ACCUM,
    parameter MSB   = BLOCK-1,
    parameter TRATE = 12,
    parameter TBITS = 4,


    parameter NREAD = 576,
    parameter RBITS = 10,
    parameter RSB   = RBITS-1,


    parameter XBITS = 4,
    parameter XSB   = XBITS-1,


    parameter CBITS = XBITS+RBITS,
    parameter CSB   = CBITS-1,


    parameter BBITS = 8,
    parameter BSB   = BBITS-1,
    parameter WSB   = BBITS-2,
    parameter ABITS = 12,
    parameter ASB   = ABITS-1,


    parameter PIPED = 1,
    parameter CHECK = 1,
    parameter ASYNC = 1,
    parameter RESET = 1,
    parameter VIZWR = 0,


    parameter NOISY = 0,
    parameter DELAY = 3)
   (
    input          clk_x,
    input          clk_i,
    input          rst_i,


    input          vld_i,
    input          new_i,
    input [NSB:0]  sig_i,


    input          cyc_i,
    input          stb_i,
    input          we_i,
    output         ack_o,
    output         wat_o,
    output         rty_o,
    output         err_o,
    input [1:0]    adr_i,
    input [7:0]    dat_i,
    output [7:0]   dat_o,


    input          sce_i,


    output         enabled_o,
    output         pending_o,
    output         switched_o,
    output         newblock_o,
    output         streamed_o,
    output [31:0]  checksum_o,


    output         overflow_o,
    output [XSB:0] bank_o,
    output         stuck_o,
    output         limp_o
    );






   reg             ack = 1'b0, viz = 1'b0;
   reg [BSB:0]     dat;
   wire            cyc_w, stb_w, ack_w, fetch, store;






   wire [MSB:0]    v_drx, v_dtx;
   wire [RSB:0]    v_adr;
   wire [CSB:0]    c_adr;
   wire            v_cyc, v_stb, v_we;
   wire            v_ack, v_wat, v_rty, v_err;



   wire            sram_a_ce, sram_a_we;
   wire [RSB:0]    sram_a_ad;
   wire [3:0]      sram_a_be;
   wire [31:0]     sram_a_di, sram_a_do;

   wire            sram_b_ce, sram_b_we;
   wire [ASB:0]    sram_b_ad;
   wire            sram_b_be;
   wire [7:0]      sram_b_di, sram_b_do;





   reg [4:0]       log_block = 5'h0;
   reg             enabled = 1'b0, accessed = 1'b0, available = 1'b0;
   reg             overwrite = 1'b0, overflow = 1'b0;
   wire            switched, newblock, wrapped;
   wire [31:0]     checksum;
   reg [MSB:0]     blocksize = {ACCUM{1'b0}};


   reg [XSB:0]     bank = 4'h0;
   wire [XBITS:0]  next;


   wire [BSB:0]    dsp_stream, dsp_status, dsp_debug, dsp_system;
   reg             dsp_set = 1'b0, dsp_clr = 1'b0;
   reg             new_bnk = 1'b0, upd_bnk = 1'b0, bs_upd = 1'b0;
   wire            bs_new_w;


   wire            swp_x;





   assign enabled_o  = enabled;
   assign pending_o  = available;
   assign newblock_o = newblock;
   assign streamed_o = wrapped;
   assign switched_o = switched;
   assign checksum_o = checksum;


   assign overflow_o = overflow;
   assign bank_o     = bank;
   assign stuck_o    = stuck;
   assign limp_o     = limp;


   assign next       = bank + 1;





   assign ack_o      = ack;
   assign wat_o      = 1'b0;
   assign rty_o      = 1'b0;
   assign err_o      = 1'b0;
   assign dat_o      = dat;


   assign cyc_w      = CHECK ? cyc_i : 1'b1;
   assign stb_w      = cyc_w && stb_i;
   assign ack_w      = stb_w && adr_i != `DSP_STREAM || viz;
   assign fetch      = stb_w && !we_i;
   assign store      = stb_w &&  we_i;






   assign dsp_stream = sram_b_do;
   assign dsp_status = {available,  accessed, overflow, 1'b0, bank};
   assign dsp_debug  = {    stuck,      limp,                 6'h0};
   assign dsp_system = {  enabled, overwrite,     1'b0,  log_block};









   always @(posedge clk_i)
     if (rst_i && RESET)
       ack <= #DELAY 1'b0;
     else
       ack <= #DELAY ack_w;




   always @(posedge clk_i)
     if (stb_w)
       case (adr_i)
         `DSP_STREAM: dat <= #DELAY dsp_stream;
         `DSP_STATUS: dat <= #DELAY dsp_status;
         `DSP_DEBUG:  dat <= #DELAY dsp_debug;
         `DSP_SYSTEM: dat <= #DELAY dsp_system;
         default:     dat <= #DELAY 8'bx;
       endcase







   always @(posedge clk_i)
     if (rst_i && RESET)
       viz <= #DELAY 1'b0;
     else
       viz <= #DELAY stb_w && adr_i == `DSP_STREAM;


   






   always @(posedge clk_i)
     if (rst_i) begin
        if (RESET) begin
           dsp_set   <= #DELAY 1'b0;
           dsp_clr   <= #DELAY 1'b1;
           upd_bnk   <= #DELAY 1'b0;
        end
        overwrite <= #DELAY 1'b0;
     end
     else if (store)
       case (adr_i)


         `DSP_STATUS: begin
            new_bnk <= #DELAY dat_i[XSB:0];
            upd_bnk <= #DELAY 1'b1;
         end

         `DSP_SYSTEM: begin
            dsp_set   <= #DELAY dat_i[BSB];
            dsp_clr   <= #DELAY ~dat_i[BSB];
            overwrite <= #DELAY dat_i[BSB-1];
            log_block <= #DELAY dat_i[4:0];
         end
       endcase
     else begin
        upd_bnk <= #DELAY 1'b0;
        dsp_set <= #DELAY dsp_set ? !enabled : 1'b0;
        dsp_clr <= #DELAY 1'b0;
     end








   always @(posedge clk_i)
     if (rst_i || overflow && !overwrite || dsp_clr)
       enabled <= #DELAY 1'b0;
     else if (dsp_set && vld_i && new_i)
       enabled <= #DELAY 1'b1;
     else
       enabled <= #DELAY enabled;



   assign bs_new_w = store && adr_i == `DSP_SYSTEM;

   always @(posedge clk_i) begin
      bs_upd <= #DELAY bs_new_w && !bs_upd;
      if (bs_upd)
`ifdef  __LOOKUP_BLOCKSIZE
        case (log_block)
          0:  blocksize <= #DELAY        0;
          1:  blocksize <= #DELAY        1;
          2:  blocksize <= #DELAY        3;
          3:  blocksize <= #DELAY        7;
          4:  blocksize <= #DELAY       15;
          5:  blocksize <= #DELAY       31;
          6:  blocksize <= #DELAY       63;
          7:  blocksize <= #DELAY      127;
          8:  blocksize <= #DELAY      255;
          9:  blocksize <= #DELAY      511;
          10: blocksize <= #DELAY     1023;
          11: blocksize <= #DELAY     2047;
          12: blocksize <= #DELAY     4095;
          13: blocksize <= #DELAY     8191;
          14: blocksize <= #DELAY    16383;
          15: blocksize <= #DELAY    32767;
          16: blocksize <= #DELAY    65535;
          17: blocksize <= #DELAY   131071;
          18: blocksize <= #DELAY   262143;
          19: blocksize <= #DELAY   524287;
          20: blocksize <= #DELAY  1048575;
          21: blocksize <= #DELAY  2097151;
          22: blocksize <= #DELAY  4194303;
          23: blocksize <= #DELAY  8388607;
          default:
            blocksize   <= #DELAY 16777215;
        endcase
`else

      blocksize <= #DELAY (1 << dat_i[4:0]) - 1;
`endif
   end






   always @(posedge clk_i)
     if (rst_i)
       bank <= #DELAY {XBITS{1'b0}};
`ifdef __USE_SETTABLE_BLOCK_COUNTER
     else if (upd_bnk)
       bank <= #DELAY new_bnk;
`endif
     else
       bank <= #DELAY wrapped ? next[XSB:0] : bank;





   always @(posedge clk_i)
     if (rst_i && RESET || newblock)
       accessed <= #DELAY 1'b0;
     else
       accessed <= #DELAY accessed || viz;



   always @(posedge clk_i)
     if (rst_i && RESET)
       available <= #DELAY 1'b0;
     else if (newblock)
       available <= #DELAY 1'b1;
     else if (viz)
       available <= #DELAY 1'b0;









   (* NOMERGE = "TRUE" *)
   reg [MSB:0]  block_x = {ACCUM{1'b0}}, block_s = {ACCUM{1'b0}};

   always @(posedge clk_x) begin
      block_s  <= #DELAY blocksize;
      block_x  <= #DELAY block_s;
   end








`ifdef  __USE_OVERFLOW_DETECTION

   (* NOMERGE = "TRUE" *)
   wire               overflow_x;

   (* NOMERGE = "TRUE" *)
   reg                overflow_s;



   always @(posedge clk_i) begin
      overflow_s <= #DELAY overflow_x;
      overflow   <= #DELAY overflow_s;
   end
`endif












`ifdef __USE_ASYNC_FETCH
   wire               stream_reset = ~sce_i;
`else   
   reg                stream_reset = 1'b1;

   always @(posedge clk_i)
     stream_reset <= #DELAY ~sce_i;
`endif












   wire               s_stb;
   wire               s_ack, s_wat, s_rty, s_err;
   wire [BSB:0]       s_dat;

   assign s_stb = CHECK ? stb_w && adr_i == `DSP_STREAM : stb_w;

   wb_sram_stream
     #(  .WIDTH(BBITS),
         .WORDS(NREAD << 2),
         .WBITS(ABITS),
         .RESET(1),
         .START(0),
         .TICKS(1),
         .READ (1),
         .WRITE(VIZWR),
         .USEBE(0),
         .PIPED(PIPED),
         .ASYNC(1),
         .CHECK(CHECK),
         .DELAY(DELAY)
         ) STREAM
       ( .clk_i(clk_i),
         .rst_i(stream_reset),


         .cyc_i(cyc_w),
         .stb_i(s_stb),
         .we_i (we_i),
         .ack_o(s_ack),
         .wat_o(s_wat),
         .rty_o(s_rty),
         .err_o(s_err),
         .sel_i(1'b0),
         .dat_i(dat_i),
         .dat_o(s_dat),


         .sram_ce_o(sram_b_ce),
         .sram_we_o(sram_b_we),
         .sram_be_o(sram_b_be),
         .sram_ad_o(sram_b_ad),
         .sram_do_i(sram_b_do),
         .sram_di_o(sram_b_di),
 
         .wrapped_o(wrapped)
         );








   (* NOMERGE *) reg rst_viz = 1'b1;

   always @(posedge clk_i)
     rst_viz <= #DELAY rst_i;


   parameter BSIZE = TRATE*2;
   parameter DBITS = TBITS+1;
   parameter COUNT = 24;
   parameter NBITS = 5;

   wire [31:0] v_dat;

   assign v_dtx    = v_dat[MSB:0];

   tart_visibilities
     #(  .WIDTH(32),
         .XBITS(XBITS),
         .COUNT(COUNT),
         .CBITS(NBITS),
         .BSIZE(BSIZE),
         .BBITS(DBITS),
         .CHECK(CHECK),
         .DELAY(DELAY)
         ) VIZ
       ( .clk_i(clk_i),
         .rst_i(rst_viz),


         .cyc_o(v_cyc),
         .stb_o(v_stb),
         .we_o (v_we), 
         .ack_i(v_ack),
         .wat_i(v_wat),
         .rty_i(v_rty),
         .err_i(v_err),
         .adr_o(v_adr),
         .dat_i({{32-ACCUM{1'b0}}, v_drx}),
         .dat_o(v_dat),


         .sram_ce_o(sram_a_ce),
         .sram_we_o(sram_a_we),
         .sram_be_o(sram_a_be),
         .sram_ad_o(sram_a_ad),
         .sram_do_i(sram_a_do),
         .sram_di_o(sram_a_di),


         .streamed_i(wrapped),
         .newblock_o(newblock),
         .checksum_o(checksum),


         .clk_x     (clk_x),
         .switch_x  (swp_x),
         .overflow_x(overflow_x)
         );









   (* NOMERGE *) reg rst_cor = 1'b1;

   always @(posedge clk_i)
     rst_cor <= #DELAY rst_i;



   assign c_adr = {bank, v_adr};

   tart_correlator
     #(  .ACCUM(BLOCK),
         .IBITS(AXNUM),
         .ABITS(CBITS),
         .TRATE(TRATE),
         .TBITS(TBITS),
         .XBITS(XBITS),
         .SEQRD(1),
         .DSLOW(0),
         .SSLOW(0),
         .DDUPS(0),
         .SDUPS(1),
         .PIPED(PIPED),
         .CHECK(CHECK),
         .DELAY(DELAY)
         ) COR
       ( .clk_x(clk_x),
         .clk_i(clk_i),
         .rst_i(rst_cor),

         .cyc_i(v_cyc),
         .stb_i(v_stb),
         .we_i (v_we ),
         .ack_o(v_ack),
         .wat_o(v_wat),
         .rty_o(v_rty),
         .err_o(v_err),
         .adr_i(c_adr),
         .dat_i(v_dtx),
         .dat_o(v_drx),

         .vld_i(enabled),
         .new_i(new_i),
         .sig_i(sig_i),

         .switching_o(switched),

         .sums_x_i(block_x),
         .swap_x_o(swp_x),
         .bank_x_o()
         );










   wire [15:0] sram_a_hi, sram_a_lo;


   assign sram_a_hi = {sram_a_di[31:28], sram_a_di[23:20],
                       sram_a_di[15:12], sram_a_di[7:4]};
   assign sram_a_lo = {sram_a_di[27:24], sram_a_di[19:16],
                       sram_a_di[11:8] , sram_a_di[3:0]};


   RAMB16X16X4_TDP
     #( .DELAY(DELAY)
        ) SRAM0
       (.CLKA (clk_i),
        .ENA  (sram_a_ce),
        .WEA  (sram_a_be[1:0]),
        .ADDRA(sram_a_ad),
        .DIA  (sram_a_lo),
        .DOA  (sram_a_do[15:0]),

        .CLKB (clk_i),
        .ENB  (sram_b_ce),
        .WEB  (sram_b_we),
        .ADDRB(sram_b_ad),
        .DIB  (sram_b_di[3:0]),
        .DOB  (sram_b_do[3:0])
        );


   RAMB16X16X4_TDP
     #( .DELAY(DELAY)
        ) SRAM1
       (.CLKA (clk_i),
        .ENA  (sram_a_ce),
        .WEA  (sram_a_be[3:2]),
        .ADDRA(sram_a_ad),
        .DIA  (sram_a_hi),
        .DOA  (sram_a_do[31:16]),

        .CLKB (clk_i),
        .ENB  (sram_b_ce),
        .WEB  (sram_b_we),
        .ADDRB(sram_b_ad),
        .DIB  (sram_b_di[7:4]),
        .DOB  (sram_b_do[7:4])
        );








`ifdef __RELEASE_BUILD
   wire               stuck = 1'b0;
   wire               limp  = 1'b0;

`else
   reg                stuck = 1'b0;
   reg                limp  = 1'b1;
   reg [5:0]          count = 6'h0;
   wire [5:0]         cnext = count[4:0] + 1'b1;


   always @(posedge clk_i)
     if (rst_i)
       {count, stuck} <= #DELAY 7'b0;
     else if (v_cyc && v_ack) begin
        if (!count[5])
          {count, stuck} <= #DELAY {cnext, stuck};
        else
          {count, stuck} <= #DELAY {count, 1'b1};
     end
     else if (!v_cyc)
       {count, stuck} <= #DELAY {6'h0, stuck};


   always @(posedge clk_i)
     if (rst_i)
       limp <= #DELAY 1'b1;
     else if (v_cyc && v_ack && enabled)
       limp <= #DELAY 1'b0;

   always @(posedge clk_i)
     if (stuck) begin
        #10 $display("%12t: WB stuck.", $time);
        #80 $finish;
     end
`endif


endmodule