data/full_repos/permissive/114459345/srcCache/ex_mem.v
1: b'%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:2: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n             data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:13: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] ex_aluop,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:13: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`AluOpBus] ex_aluop,\n                     ^\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:14: Define or directive not defined: \'`AluFunct3Bus\'\n input wire[`AluFunct3Bus] ex_alufunct3,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`MemAddrBus] ex_maddr,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:16: Define or directive not defined: \'`MemAddrBus\'\n input wire[`MemAddrBus] ex_maddr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] ex_wd,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:18: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] ex_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:19: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] ex_wdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:22: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus] mem_aluop,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:23: Define or directive not defined: \'`AluFunct3Bus\'\n output reg[`AluFunct3Bus] mem_alufunct3,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`MemAddrBus] mem_maddr,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:25: Define or directive not defined: \'`MemAddrBus\'\n output reg[`MemAddrBus] mem_maddr,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:27: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] mem_wd,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:27: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] mem_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:28: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] mem_wdata\n            ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:33: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:34: Define or directive not defined: \'`ChipDisable\'\n   ce <= `ChipDisable;    \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:37: Define or directive not defined: \'`ChipEnable\'\n   ce <= `ChipEnable;    \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:42: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:43: Define or directive not defined: \'`NOP\'\n   mem_aluop <= `NOP;\n                ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:44: Define or directive not defined: \'`NOP_FUNCT3\'\n   mem_alufunct3 <= `NOP_FUNCT3;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:45: Define or directive not defined: \'`MemDisable\'\n   mem_me <= `MemDisable;\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:46: Define or directive not defined: \'`NopMem\'\n   mem_maddr <= `NopMem;\n                ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:47: Define or directive not defined: \'`WriteDisable\'\n   mem_wreg <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:48: Define or directive not defined: \'`NopRegAddr\'\n   mem_wd <= `NopRegAddr;\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:49: Define or directive not defined: \'`ZeroWord\'\n   mem_wdata <= `ZeroWord;\n                ^~~~~~~~~\n%Error: Exiting due to 27 error(s)\n'
module ex_mem(

	input wire clk,
	input wire rst,
	

	output reg ce,
	

	input wire[`AluOpBus] ex_aluop,
	input wire[`AluFunct3Bus] ex_alufunct3,
	input wire ex_me,
	input wire[`MemAddrBus] ex_maddr,
	input wire ex_wreg,
	input wire[`RegAddrBus] ex_wd,
	input wire[`RegBus] ex_wdata,
	

	output reg[`AluOpBus] mem_aluop,
	output reg[`AluFunct3Bus] mem_alufunct3,
	output reg mem_me,
	output reg[`MemAddrBus] mem_maddr,
	output reg mem_wreg,
	output reg[`RegAddrBus] mem_wd,
	output reg[`RegBus] mem_wdata

);
	
	always @ (posedge clk) begin
		if(rst == `RstEnable) begin
			ce <= `ChipDisable;
		end
		else begin
			ce <= `ChipEnable;
		end
	end
	
	always @ (posedge clk) begin
		if(rst == `RstEnable) begin
			mem_aluop <= `NOP;
			mem_alufunct3 <= `NOP_FUNCT3;
			mem_me <= `MemDisable;
			mem_maddr <= `NopMem;
			mem_wreg <= `WriteDisable;
			mem_wd <= `NopRegAddr;
			mem_wdata <= `ZeroWord;
		end
		else begin
			mem_aluop <= ex_aluop;
			mem_alufunct3 <= ex_alufunct3;
			mem_me <= ex_me;
			mem_maddr <= ex_maddr;
			mem_wreg <= ex_wreg;
			mem_wd <= ex_wd;
			mem_wdata <= ex_wdata;
		end
	end

endmodule
module ex_mem(

	input wire clk,
	input wire rst,
	

	output reg ce,
	

	input wire[`AluOpBus] ex_aluop,
	input wire[`AluFunct3Bus] ex_alufunct3,
	input wire ex_me,
	input wire[`MemAddrBus] ex_maddr,
	input wire ex_wreg,
	input wire[`RegAddrBus] ex_wd,
	input wire[`RegBus] ex_wdata,
	

	output reg[`AluOpBus] mem_aluop,
	output reg[`AluFunct3Bus] mem_alufunct3,
	output reg mem_me,
	output reg[`MemAddrBus] mem_maddr,
	output reg mem_wreg,
	output reg[`RegAddrBus] mem_wd,
	output reg[`RegBus] mem_wdata

);

	
	always @ (posedge clk) begin
		if(rst == `RstEnable) begin
			ce <= `ChipDisable;
		end
		else begin
			ce <= `ChipEnable;
		end
	end
	
	always @ (posedge clk) begin
		if(rst == `RstEnable) begin
			mem_aluop <= `NOP;
			mem_alufunct3 <= `NOP_FUNCT3;
			mem_me <= `MemDisable;
			mem_maddr <= `NopMem;
			mem_wreg <= `WriteDisable;
			mem_wd <= `NopRegAddr;
			mem_wdata <= `ZeroWord;
		end
		else begin
			mem_aluop <= ex_aluop;
			mem_alufunct3 <= ex_alufunct3;
			mem_me <= ex_me;
			mem_maddr <= ex_maddr;
			mem_wreg <= ex_wreg;
			mem_wd <= ex_wd;
			mem_wdata <= ex_wdata;
		end
	end

endmodule