data/full_repos/permissive/122693972/hdlsrc/testbench.v
 line:19: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/122693972/hdlsrc/testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n# TIME_RUN  $stop();\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/122693972/hdlsrc/testbench.v:66: Unsupported: Ignoring delay on this delayed statement.\n  # 100 O_RST   = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122693972/hdlsrc/testbench.v:67: Unsupported: Ignoring delay on this delayed statement.\n  # 200 O_RST   = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/122693972/hdlsrc/testbench.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #CLK_PERIOD_HALF O_CLK = ~O_CLK;\n  ^\n%Error: data/full_repos/permissive/122693972/hdlsrc/testbench.v:32: Cannot find file containing module: \'u_add_1\'\nu_add_1 U_add(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122693972/hdlsrc,data/full_repos/permissive/122693972/u_add_1\n             data/full_repos/permissive/122693972/hdlsrc,data/full_repos/permissive/122693972/u_add_1.v\n             data/full_repos/permissive/122693972/hdlsrc,data/full_repos/permissive/122693972/u_add_1.sv\n             u_add_1\n             u_add_1.v\n             u_add_1.sv\n             obj_dir/u_add_1\n             obj_dir/u_add_1.v\n             obj_dir/u_add_1.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();


parameter CLK_PERIOD      = 10            ;
parameter CLK_PERIOD_2    = CLK_PERIOD*2  ;
parameter CLK_PERIOD_HALF = (CLK_PERIOD/2);


parameter TIME_RUN        = CLK_PERIOD* 1024 * 30;

wire  W_clk, W_rst;



initial begin
# TIME_RUN  $stop();
end


gen_clk_rst U_gen_clk_rst(
  .O_CLK(W_clk),
  .O_RST(W_rst));
defparam U_gen_clk_rst.CLK_PERIOD_HALF = CLK_PERIOD_HALF;

reg  signed [8-1:0]   R_U_add_IN ;
wire signed [8-1:0]   W_U_add_OUT;


u_add_1 U_add(
  .IN  (R_U_add_IN ),
  .OUT (W_U_add_OUT));
defparam U_add.WL  = 8;



always @ (posedge W_clk or posedge W_rst) begin
  if(W_rst) begin
    R_U_add_IN  <= #1 0;
  end 
  else begin
    R_U_add_IN  <= #1 R_U_add_IN  + 1;
  end
end

endmodule
module testbench();



parameter CLK_PERIOD      = 10            ;
parameter CLK_PERIOD_2    = CLK_PERIOD*2  ;
parameter CLK_PERIOD_HALF = (CLK_PERIOD/2);


parameter TIME_RUN        = CLK_PERIOD* 1024 * 30;

wire  W_clk, W_rst;



initial begin
# TIME_RUN  $stop();
end


gen_clk_rst U_gen_clk_rst(
  .O_CLK(W_clk),
  .O_RST(W_rst));
defparam U_gen_clk_rst.CLK_PERIOD_HALF = CLK_PERIOD_HALF;

reg  signed [8-1:0]   R_U_add_IN ;
wire signed [8-1:0]   W_U_add_OUT;


u_add_1 U_add(
  .IN  (R_U_add_IN ),
  .OUT (W_U_add_OUT));
defparam U_add.WL  = 8;



always @ (posedge W_clk or posedge W_rst) begin
  if(W_rst) begin
    R_U_add_IN  <= #1 0;
  end 
  else begin
    R_U_add_IN  <= #1 R_U_add_IN  + 1;
  end
end

endmodule