data/full_repos/permissive/143278/ivltests/pr1609611.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/143278/ivltests/pr1609611.v:7: Little bit endian vector: MSB < LSB of bit range: 0:5\n   wire [0:5]      hit_bar;\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1609611.v:10: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                         : ... In instance x\n   wire [31:0]      e = ad_in_d[31:bar0_low];\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1609611.v:11: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'base_address0\' generates 16 bits.\n                                                                         : ... In instance x\n   wire       b = (base_address0==e);\n                                ^~\n%Error: Exiting due to 3 warning(s)\n'
module x;

   parameter bar0_low = 5'd16;
   reg [31:bar0_low] base_address0;

   reg [31:0]	     ad_in_d;
   wire [0:5]	     hit_bar;

   wire		     a = |bar0_low;
   wire [31:0]	     e = ad_in_d[31:bar0_low];
   wire		     b = (base_address0==e);
   wire		     d = b;

   assign	     hit_bar[0] = a ? d : 0;

   initial begin
      if ($bits(base_address0) != 16) begin
	 $display("FAILED -- $bits(base_address0) = %0d", $bits(base_address0));
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module x;


   parameter bar0_low = 5'd16;
   reg [31:bar0_low] base_address0;

   reg [31:0]	     ad_in_d;
   wire [0:5]	     hit_bar;

   wire		     a = |bar0_low;
   wire [31:0]	     e = ad_in_d[31:bar0_low];
   wire		     b = (base_address0==e);
   wire		     d = b;

   assign	     hit_bar[0] = a ? d : 0;

   initial begin
      if ($bits(base_address0) != 16) begin
	 $display("FAILED -- $bits(base_address0) = %0d", $bits(base_address0));
	 $finish;
      end

      $display("PASSED");
   end

endmodule