data/full_repos/permissive/117851934/ddr_layout_V5/ip/ad9245/hdl/ad9245.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/25dde139-5156-43ae-948c-ef6ddef22424.xml
module ad9245					
(

	input  wire [13:0] ad_data,
	

	input  wire clk,
	input  wire reset_n,
	input  wire chipselect,
	input  wire read,
	output reg [31:0] readdata
);

	always @(posedge clk or negedge reset_n)
	begin
		if (!reset_n)
		begin

		end
		else
		begin
			if(chipselect && read)
			begin
				readdata <= {18'h0,ad_data};
			end
		end
	end

endmodule
module ad9245					
(

	input  wire [13:0] ad_data,
	

	input  wire clk,
	input  wire reset_n,
	input  wire chipselect,
	input  wire read,
	output reg [31:0] readdata
);


	always @(posedge clk or negedge reset_n)
	begin
		if (!reset_n)
		begin

		end
		else
		begin
			if(chipselect && read)
			begin
				readdata <= {18'h0,ad_data};
			end
		end
	end

endmodule