data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_サンプル回路/FPGA-CPU/FPGA_counter/ctrg_rmv.v
1: b'%Warning-WIDTH: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter/ctrg_rmv.v:27: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                             : ... In instance ctrg_rmv\n      PSW_1D <= 1\'b000;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter/ctrg_rmv.v:34: Cannot find file containing module: \'key_module\'\n key_module key_module1(  \n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter,data/full_repos/permissive/183580645/key_module\n             data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter,data/full_repos/permissive/183580645/key_module.v\n             data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter,data/full_repos/permissive/183580645/key_module.sv\n             key_module\n             key_module.v\n             key_module.sv\n             obj_dir/key_module\n             obj_dir/key_module.v\n             obj_dir/key_module.sv\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter/ctrg_rmv.v:41: Cannot find file containing module: \'key_module\'\n key_module key_module2(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/183580645/docs/MU500-manual/MU500-RXSET01/2_\xe3\x82\xb5\xe3\x83\xb3\xe3\x83\x97\xe3\x83\xab\xe5\x9b\x9e\xe8\xb7\xaf/FPGA-CPU/FPGA_counter/ctrg_rmv.v:48: Cannot find file containing module: \'key_module\'\n key_module key_module3(\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module ctrg_rmv( 

	  CLK, RSTN,
	  PSW,

	  PSW_SIG
	);


	input  CLK,RSTN;
	input  [2:0] PSW;

	output [2:0] PSW_SIG;

	reg    [2:0] PSW_1D;


	always@( posedge CLK or negedge RSTN ) begin
		if( RSTN == 1'b0 )begin
	    	PSW_1D <= 1'b000;
		end
	  	else begin
	    	PSW_1D <= PSW;
		end
	end

	key_module key_module1( 	
								.CLK(CLK),
								.RSTN(RSTN),
								.PSW_1D(PSW_1D[0]),
								.PSW_SIG(PSW_SIG[0])
							);

	key_module key_module2(
								.CLK(CLK),
								.RSTN(RSTN),
								.PSW_1D(PSW_1D[1]),
								.PSW_SIG(PSW_SIG[1])
							);

	key_module key_module3(
								.CLK(CLK),
								.RSTN(RSTN),
								.PSW_1D(PSW_1D[2]),
								.PSW_SIG(PSW_SIG[2])
							);


	endmodule
module ctrg_rmv( 

	  CLK, RSTN,
	  PSW,

	  PSW_SIG
	);



	input  CLK,RSTN;
	input  [2:0] PSW;

	output [2:0] PSW_SIG;

	reg    [2:0] PSW_1D;


	always@( posedge CLK or negedge RSTN ) begin
		if( RSTN == 1'b0 )begin
	    	PSW_1D <= 1'b000;
		end
	  	else begin
	    	PSW_1D <= PSW;
		end
	end

	key_module key_module1( 	
								.CLK(CLK),
								.RSTN(RSTN),
								.PSW_1D(PSW_1D[0]),
								.PSW_SIG(PSW_SIG[0])
							);

	key_module key_module2(
								.CLK(CLK),
								.RSTN(RSTN),
								.PSW_1D(PSW_1D[1]),
								.PSW_SIG(PSW_SIG[1])
							);

	key_module key_module3(
								.CLK(CLK),
								.RSTN(RSTN),
								.PSW_1D(PSW_1D[2]),
								.PSW_SIG(PSW_SIG[2])
							);


	endmodule