data/full_repos/permissive/143278/ivltests/pr544.v
 line:4: before: "("
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr544.v:4: syntax error, unexpected (-for-strength, expecting \'(\'\n    bufif1  (pull0,   pull1  ) ( y, p01, p01g );\n             ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr544.v:8: Unsupported or unknown PLI call: $monitor\n        $monitor( "%T Pu:%b/%b St:%b/%b Y:%b,%v",\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'b0x00;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'b000x;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'b1x00;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'b001x;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'b0100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'b0001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'b1100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'b0011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'bx100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'b00x1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'b010x;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'bx10x;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'b111x;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #100 { p01, p01g, s01, s01g } = 4\'bx11x;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr544.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #100 ;\n        ^\n%Error: Exiting due to 2 error(s), 15 warning(s)\n'
module example;
    wire    y;
    reg     p01, p01g, s01, s01g;
    bufif1  (pull0,   pull1  ) ( y, p01, p01g );
    bufif1  (strong0, strong1) ( y, s01, s01g );

    initial begin
        $monitor( "%T Pu:%b/%b St:%b/%b Y:%b,%v",
                  $time, p01, p01g, s01, s01g, y, y );
             { p01, p01g, s01, s01g } = 4'b0000;
        #100 { p01, p01g, s01, s01g } = 4'b0x00;
        #100 { p01, p01g, s01, s01g } = 4'b000x;
        #100 { p01, p01g, s01, s01g } = 4'b1x00;
        #100 { p01, p01g, s01, s01g } = 4'b001x;
        #100 { p01, p01g, s01, s01g } = 4'b0100;
        #100 { p01, p01g, s01, s01g } = 4'b0001;
        #100 { p01, p01g, s01, s01g } = 4'b1100;
        #100 { p01, p01g, s01, s01g } = 4'b0011;
        #100 { p01, p01g, s01, s01g } = 4'bx100;
        #100 { p01, p01g, s01, s01g } = 4'b00x1;
        #100 { p01, p01g, s01, s01g } = 4'b010x;
        #100 { p01, p01g, s01, s01g } = 4'bx10x;
        #100 { p01, p01g, s01, s01g } = 4'b111x;
        #100 { p01, p01g, s01, s01g } = 4'bx11x;
        #100 ;
    end
endmodule
module example;

    wire    y;
    reg     p01, p01g, s01, s01g;
    bufif1  (pull0,   pull1  ) ( y, p01, p01g );
    bufif1  (strong0, strong1) ( y, s01, s01g );

    initial begin
        $monitor( "%T Pu:%b/%b St:%b/%b Y:%b,%v",
                  $time, p01, p01g, s01, s01g, y, y );
             { p01, p01g, s01, s01g } = 4'b0000;
        #100 { p01, p01g, s01, s01g } = 4'b0x00;
        #100 { p01, p01g, s01, s01g } = 4'b000x;
        #100 { p01, p01g, s01, s01g } = 4'b1x00;
        #100 { p01, p01g, s01, s01g } = 4'b001x;
        #100 { p01, p01g, s01, s01g } = 4'b0100;
        #100 { p01, p01g, s01, s01g } = 4'b0001;
        #100 { p01, p01g, s01, s01g } = 4'b1100;
        #100 { p01, p01g, s01, s01g } = 4'b0011;
        #100 { p01, p01g, s01, s01g } = 4'bx100;
        #100 { p01, p01g, s01, s01g } = 4'b00x1;
        #100 { p01, p01g, s01, s01g } = 4'b010x;
        #100 { p01, p01g, s01, s01g } = 4'bx10x;
        #100 { p01, p01g, s01, s01g } = 4'b111x;
        #100 { p01, p01g, s01, s01g } = 4'bx11x;
        #100 ;
    end
endmodule