data/full_repos/permissive/167856740/cpu/load_generator.v
None: at end of input
1: b'%Error: data/full_repos/permissive/167856740/cpu/load_generator.v:4: Cannot find include file: load_generator.vh\n`include "load_generator.vh" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167856740/cpu,data/full_repos/permissive/167856740/load_generator.vh\n             data/full_repos/permissive/167856740/cpu,data/full_repos/permissive/167856740/load_generator.vh.v\n             data/full_repos/permissive/167856740/cpu,data/full_repos/permissive/167856740/load_generator.vh.sv\n             load_generator.vh\n             load_generator.vh.v\n             load_generator.vh.sv\n             obj_dir/load_generator.vh\n             obj_dir/load_generator.vh.v\n             obj_dir/load_generator.vh.sv\n%Error: data/full_repos/permissive/167856740/cpu/load_generator.v:14: Define or directive not defined: \'`LOAD_LB\'\n            `LOAD_LB: O_data = {{24{I_data[7]}},I_data[7:0]};\n            ^~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/load_generator.v:14: syntax error, unexpected \':\', expecting endcase\n            `LOAD_LB: O_data = {{24{I_data[7]}},I_data[7:0]};\n                    ^\n%Error: data/full_repos/permissive/167856740/cpu/load_generator.v:15: Define or directive not defined: \'`LOAD_LH\'\n            `LOAD_LH: O_data = {{16{I_data[15]}},I_data[15:0]};\n            ^~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/load_generator.v:16: Define or directive not defined: \'`LOAD_LW\'\n            `LOAD_LW: O_data = I_data;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/load_generator.v:17: Define or directive not defined: \'`LOAD_LBU\'\n            `LOAD_LBU: O_data = {24\'h000000,I_data[7:0]};\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/load_generator.v:18: Define or directive not defined: \'`LOAD_LHU\'\n            `LOAD_LHU: O_data = {16\'h0000,I_data[15:0]};\n            ^~~~~~~~~\n%Error: Cannot continue\n'
module load_generator(
    input wire [2:0] I_loadsel,
    input wire [31:0] I_data,
    output reg [31:0] O_data
    );
    
    always @(*) begin
        case(I_loadsel)
            `LOAD_LB: O_data = {{24{I_data[7]}},I_data[7:0]};
            `LOAD_LH: O_data = {{16{I_data[15]}},I_data[15:0]};
            `LOAD_LW: O_data = I_data;
            `LOAD_LBU: O_data = {24'h000000,I_data[7:0]};
            `LOAD_LHU: O_data = {16'h0000,I_data[15:0]};
            default: O_data = I_data;
        endcase
    end
    
endmodule
module load_generator(
    input wire [2:0] I_loadsel,
    input wire [31:0] I_data,
    output reg [31:0] O_data
    );

    
    always @(*) begin
        case(I_loadsel)
            `LOAD_LB: O_data = {{24{I_data[7]}},I_data[7:0]};
            `LOAD_LH: O_data = {{16{I_data[15]}},I_data[15:0]};
            `LOAD_LW: O_data = I_data;
            `LOAD_LBU: O_data = {24'h000000,I_data[7:0]};
            `LOAD_LHU: O_data = {16'h0000,I_data[15:0]};
            default: O_data = I_data;
        endcase
    end
    
endmodule