data/full_repos/permissive/117880471/HW3/u_fa_ha_multiplier_4bit.v
 line:12: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/u_fa_ha_multiplier_4bit.v:9: Unsupported: Ignoring delay on this delayed statement.\n #00 a = 4\'b0011; b = 4\'b0101;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/u_fa_ha_multiplier_4bit.v:10: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 4\'b0101; b = 4\'b1010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/u_fa_ha_multiplier_4bit.v:11: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 4\'b1111; b = 4\'b1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/u_fa_ha_multiplier_4bit.v:12: Unsupported: Ignoring delay on this delayed statement.\n #20 $stop;\n ^\n%Error: data/full_repos/permissive/117880471/HW3/u_fa_ha_multiplier_4bit.v:17: Unsupported or unknown PLI call: $monitor\n $monitor("$time=%3d, prod=%8b, a=%4b, b=%4b", $time, prod, a, b);\n ^~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/u_fa_ha_multiplier_4bit.v:22: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("u_fa_ha_multiplier_4bit.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/u_fa_ha_multiplier_4bit.v:23: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module u_fa_ha_multiplier_4bit(prod, a, b);

output wire [7:0] prod;
input wire [3:0] a, b;

wire w_cout_1_0;
wire w_cout_2_0, w_cout_2_1;
wire w_cout_3_0, w_cout_3_1, w_cout_3_2;
wire w_cout_4_0, w_cout_4_1;
wire w_cout_5_0;

wire w_and_1_0, w_and_1_1;
wire w_and_2_0, w_and_2_1, w_and_2_2;
wire w_and_3_0, w_and_3_1, w_and_3_2, w_and_3_3;
wire w_and_4_0, w_and_4_1, w_and_4_2;
wire w_and_5_0, w_and_5_1;
wire w_and_6_0;

wire interm_2_0, interm_3_0, interm_3_1, interm_4_0;


half_adder ha_sum_and_0_0(.cout(prod[0]), .a(a[0]), .b(b[0]) );
half_adder ha_and_1_0(.cout(w_and_1_0), .a(a[1]), .b(b[0]));
half_adder ha_and_1_1(.cout(w_and_1_1), .a(a[0]), .b(b[1]));
half_adder ha_and_2_0(.cout(w_and_2_0), .a(a[2]), .b(b[0]));
half_adder ha_and_2_1(.cout(w_and_2_1), .a(a[1]), .b(b[1]));
half_adder ha_and_2_2(.cout(w_and_2_2), .a(a[0]), .b(b[2]));
half_adder ha_and_3_0(.cout(w_and_3_0), .a(a[3]), .b(b[0]));
half_adder ha_and_3_1(.cout(w_and_3_1), .a(a[2]), .b(b[1]));
half_adder ha_and_3_2(.cout(w_and_3_2), .a(a[1]), .b(b[2]));
half_adder ha_and_3_3(.cout(w_and_3_3), .a(a[0]), .b(b[3]));
half_adder ha_and_4_0(.cout(w_and_4_0), .a(a[3]), .b(b[1]));
half_adder ha_and_4_1(.cout(w_and_4_1), .a(a[2]), .b(b[2]));
half_adder ha_and_4_2(.cout(w_and_4_2), .a(a[1]), .b(b[3]));
half_adder ha_and_5_0(.cout(w_and_5_0), .a(a[3]), .b(b[2]));
half_adder ha_and_5_1(.cout(w_and_5_1), .a(a[2]), .b(b[3]));
half_adder ha_and_6_0(.cout(w_and_6_0), .a(a[3]), .b(b[3]));


half_adder ha_sum_1_0(.sum(prod[1]), .cout(w_cout_1_0), .a(w_and_1_0), .b(w_and_1_1) );

full_adder fa_interm_sum_2_0(.sum(interm_2_0), .cout(w_cout_2_0), .a(w_and_2_0), .b(w_and_2_1), .cin(w_cout_1_0));
full_adder fa_sum_2_0(.sum(prod[2]), .cout(w_cout_2_1), .a(w_and_2_2), b(interm_2_0), .cin(w_cout_2_0));

full_adder fa_interm_sum_3_0(.sum(interm_3_0),.cout(w_cout_3_0),.a(w_and_3_0), b(w_and_3_1), .cin(w_cout_2_1));
full_adder fa_interm_sum_3_1(.sum(interm_3_1),.cout(w_cout_3_1),.a(w_cout_3_0), .b(interm_3_0), .cin(w_and_3_2));
full_adder fa_sum_3_0(.sum(prod[3]), .cout(w_cout_3_2), .a(w_and_3_3), .b(interm_3_1), .cin(w_cout_3_1)); 

full_adder fa_interm_sum_4_0(.sum(interm_4_0), .cout(w_cout_4_0), .a(w_and_4_0), .b(w_and_4_1), .cin(w_cout_3_2));
full_adder fa_sum_4_0(.sum(prod[4]), .cout(w_cout_4_1), .a(w_and_4_2), b(interm_4_0), .cin(w_cout_4_0));

full_adder fa_sum_5_0(.sum(prod[5]), .cout(w_cout_5_0), .a(w_and_5_0), .b(w_and_5_1), .cin(w_cout_4_0));

half_adder ha_sum_6_0_7_0(.sum(prod[6]), .cout(prod[7]), .a(w_and_6_0), .b(w_cout_5_0));


endmodule
module u_fa_ha_multiplier_4bit(prod, a, b);


output wire [7:0] prod;
input wire [3:0] a, b;

wire w_cout_1_0;
wire w_cout_2_0, w_cout_2_1;
wire w_cout_3_0, w_cout_3_1, w_cout_3_2;
wire w_cout_4_0, w_cout_4_1;
wire w_cout_5_0;

wire w_and_1_0, w_and_1_1;
wire w_and_2_0, w_and_2_1, w_and_2_2;
wire w_and_3_0, w_and_3_1, w_and_3_2, w_and_3_3;
wire w_and_4_0, w_and_4_1, w_and_4_2;
wire w_and_5_0, w_and_5_1;
wire w_and_6_0;

wire interm_2_0, interm_3_0, interm_3_1, interm_4_0;


half_adder ha_sum_and_0_0(.cout(prod[0]), .a(a[0]), .b(b[0]) );
half_adder ha_and_1_0(.cout(w_and_1_0), .a(a[1]), .b(b[0]));
half_adder ha_and_1_1(.cout(w_and_1_1), .a(a[0]), .b(b[1]));
half_adder ha_and_2_0(.cout(w_and_2_0), .a(a[2]), .b(b[0]));
half_adder ha_and_2_1(.cout(w_and_2_1), .a(a[1]), .b(b[1]));
half_adder ha_and_2_2(.cout(w_and_2_2), .a(a[0]), .b(b[2]));
half_adder ha_and_3_0(.cout(w_and_3_0), .a(a[3]), .b(b[0]));
half_adder ha_and_3_1(.cout(w_and_3_1), .a(a[2]), .b(b[1]));
half_adder ha_and_3_2(.cout(w_and_3_2), .a(a[1]), .b(b[2]));
half_adder ha_and_3_3(.cout(w_and_3_3), .a(a[0]), .b(b[3]));
half_adder ha_and_4_0(.cout(w_and_4_0), .a(a[3]), .b(b[1]));
half_adder ha_and_4_1(.cout(w_and_4_1), .a(a[2]), .b(b[2]));
half_adder ha_and_4_2(.cout(w_and_4_2), .a(a[1]), .b(b[3]));
half_adder ha_and_5_0(.cout(w_and_5_0), .a(a[3]), .b(b[2]));
half_adder ha_and_5_1(.cout(w_and_5_1), .a(a[2]), .b(b[3]));
half_adder ha_and_6_0(.cout(w_and_6_0), .a(a[3]), .b(b[3]));


half_adder ha_sum_1_0(.sum(prod[1]), .cout(w_cout_1_0), .a(w_and_1_0), .b(w_and_1_1) );

full_adder fa_interm_sum_2_0(.sum(interm_2_0), .cout(w_cout_2_0), .a(w_and_2_0), .b(w_and_2_1), .cin(w_cout_1_0));
full_adder fa_sum_2_0(.sum(prod[2]), .cout(w_cout_2_1), .a(w_and_2_2), b(interm_2_0), .cin(w_cout_2_0));

full_adder fa_interm_sum_3_0(.sum(interm_3_0),.cout(w_cout_3_0),.a(w_and_3_0), b(w_and_3_1), .cin(w_cout_2_1));
full_adder fa_interm_sum_3_1(.sum(interm_3_1),.cout(w_cout_3_1),.a(w_cout_3_0), .b(interm_3_0), .cin(w_and_3_2));
full_adder fa_sum_3_0(.sum(prod[3]), .cout(w_cout_3_2), .a(w_and_3_3), .b(interm_3_1), .cin(w_cout_3_1)); 

full_adder fa_interm_sum_4_0(.sum(interm_4_0), .cout(w_cout_4_0), .a(w_and_4_0), .b(w_and_4_1), .cin(w_cout_3_2));
full_adder fa_sum_4_0(.sum(prod[4]), .cout(w_cout_4_1), .a(w_and_4_2), b(interm_4_0), .cin(w_cout_4_0));

full_adder fa_sum_5_0(.sum(prod[5]), .cout(w_cout_5_0), .a(w_and_5_0), .b(w_and_5_1), .cin(w_cout_4_0));

half_adder ha_sum_6_0_7_0(.sum(prod[6]), .cout(prod[7]), .a(w_and_6_0), .b(w_cout_5_0));


endmodule