data/full_repos/permissive/130536678/Single-Cycle/ARM_CPU.v
 line:98: before: "INSTRUCTION"
1: b"%Error: data/full_repos/permissive/130536678/Single-Cycle/ARM_CPU.v:506: syntax error, unexpected $end, expecting ';'\n    Data[31] = 64   h00000000;\n                 ^\n%Error: Cannot continue\n"
module Data_Memory
(
  input [63:0] inputAddress,
  input [63:0] inputData,
  input CONTROL_MemRead,
  input CONTROL_MemWrite,
  output reg [63:0] outputData
);

  reg [63:0] Data[31:0];

  integer initCount;

  initial begin
    for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
      Data[initCount] = initCount * 100;
    end

   Data[10] = 1540;
   Data[11] = 2117;
  end

    always @(inputAddress, inputData, CONTROL_MemRead, CONTROL_MemWrite) begin
      if (CONTROL_MemWrite == 1) begin
        Data[inputAddress] = inputData;
      end

      if (CONTROL_MemRead == 1) begin
        outputData = Data[inputAddress];
      end
    end
endmodule
module Data_Memory
(
  input [63:0] inputAddress,
  input [63:0] inputData,
  input CONTROL_MemRead,
  input CONTROL_MemWrite,
  output reg [63:0] outputData
);


  reg [63:0] Data[31:0];

  integer initCount;

  initial begin
    for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
      Data[initCount] = initCount * 100;
    end

   Data[10] = 1540;
   Data[11] = 2117;
  end

    always @(inputAddress, inputData, CONTROL_MemRead, CONTROL_MemWrite) begin
      if (CONTROL_MemWrite == 1) begin
        Data[inputAddress] = inputData;
      end

      if (CONTROL_MemRead == 1) begin
        outputData = Data[inputAddress];
      end
    end
endmodule