data/full_repos/permissive/171756809/binary_debias.v
data/verilator_xmls/64328ddf-f360-458a-a961-9f174d6569bf.xml
module binary_debias(input wire clk, input wire metastable, output reg bit_ready, output reg random);

	reg last_random;

	always @ (posedge clk) begin
		bit_ready <= bit_ready+1;
		if(bit_ready) begin
			random <= !metastable ^ last_random;
		end else begin
			last_random <= metastable;
		end
	end

endmodule
module binary_debias(input wire clk, input wire metastable, output reg bit_ready, output reg random);


	reg last_random;

	always @ (posedge clk) begin
		bit_ready <= bit_ready+1;
		if(bit_ready) begin
			random <= !metastable ^ last_random;
		end else begin
			last_random <= metastable;
		end
	end

endmodule