data/full_repos/permissive/125379288/pbs_fsm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:26: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_VICTORY\' generates 4 bits.\n                                                                 : ... In instance control\n          next_state = S_VICTORY;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:28: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOSS\' generates 4 bits.\n                                                                 : ... In instance control\n        next_state = S_LOSS;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:31: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_UPDATE_AI_HP\' generates 4 bits.\n                                                                 : ... In instance control\n       S_LOAD_PM: next_state = S_UPDATE_AI_HP;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:32: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_UPDATE_P_HP\' generates 4 bits.\n                                                                 : ... In instance control\n       S_UPDATE_AI_HP: next_state = S_UPDATE_P_HP; \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:33: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_PM\' generates 4 bits.\n                                                                 : ... In instance control\n         S_UPDATE_P_HP: next_state = S_LOAD_PM;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:34: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_VICTORY\' generates 4 bits.\n                                                                 : ... In instance control\n       S_VICTORY: next_state = S_VICTORY;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:35: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOSS\' generates 4 bits.\n                                                                 : ... In instance control\n       S_LOSS: next_state = S_LOSS;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:36: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_PM\' generates 4 bits.\n                                                                 : ... In instance control\n       default:   next_state = S_LOAD_PM;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:30: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_PM\' generates 4 bits.\n                                                                 : ... In instance control\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:30: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_UPDATE_AI_HP\' generates 4 bits.\n                                                                 : ... In instance control\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:30: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_UPDATE_P_HP\' generates 4 bits.\n                                                                 : ... In instance control\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:30: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_VICTORY\' generates 4 bits.\n                                                                 : ... In instance control\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:30: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOSS\' generates 4 bits.\n                                                                 : ... In instance control\n     case (current_state)\n     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:57: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_PM\' generates 4 bits.\n                                                                 : ... In instance control\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:57: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_UPDATE_AI_HP\' generates 4 bits.\n                                                                 : ... In instance control\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:57: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_UPDATE_P_HP\' generates 4 bits.\n                                                                 : ... In instance control\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:57: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_VICTORY\' generates 4 bits.\n                                                                 : ... In instance control\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:57: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOSS\' generates 4 bits.\n                                                                 : ... In instance control\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/125379288/pbs_fsm.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_PM\' generates 4 bits.\n                                                                 : ... In instance control\n            current_state <= S_LOAD_PM;\n                          ^~\n%Error: Exiting due to 19 warning(s)\n'
module control(
    input clk,
    input reset_n,
    input go,
    input p_hp,
	 input ai_dead,
	 input p_dead,
	 output reg victory,
	 output reg loss,
    output reg active_trainer, load_ai_hp, apply_p_damage, apply_ai_damage, target,
	 output reg state1, state2, state3
    );

    reg [5:0] current_state, next_state; 
    
    localparam  S_LOAD_PM         = 4'd0,
                S_UPDATE_AI_HP    = 4'd1,
                S_UPDATE_P_HP     = 4'd2,
                S_VICTORY         = 4'd3,
                S_LOSS            = 4'd4;
    

    always@(*)
    begin: state_table 
	         if (ai_dead)
			       next_state = S_VICTORY;
			   else if (p_dead)
				    next_state = S_LOSS;
			   else begin
					case (current_state)
						 S_LOAD_PM: next_state = S_UPDATE_AI_HP;
						 S_UPDATE_AI_HP: next_state = S_UPDATE_P_HP; 
					    S_UPDATE_P_HP: next_state = S_LOAD_PM;
						 S_VICTORY: next_state = S_VICTORY;
						 S_LOSS: next_state = S_LOSS;
						 default:   next_state = S_LOAD_PM;
				  endcase
		      end
    end
   


    always @(*)
    begin: enable_signals

        active_trainer = 1'b0;
        target = 1'b0;
		  load_ai_hp = 1'b0;
		  apply_p_damage = 1'b0;
        apply_ai_damage = 1'b0;
		  victory = 1'b0;
		  loss = 1'b0;
		  state1 = 1'b0;
		  state2 = 1'b0;
		  state3 = 1'b0;

        case (current_state)
		      S_LOAD_PM: begin
				    state1 = 1'b1;
					 end
            S_UPDATE_AI_HP: begin
				    active_trainer = 1'b0;
                target = 1'b1;
                apply_ai_damage = 1'b1;
					 state2 = 1'b1;
                end
            S_UPDATE_P_HP: begin
				    active_trainer = 1'b1;
                target = 1'b0;
                apply_p_damage = 1'b1;
					 state3 = 1'b1;
                end
            S_VICTORY: begin
                victory = 1'b1;
                end
            S_LOSS: begin
                loss = 1'b1;
                end
            

        endcase
    end
   

    always@(posedge clk)
    begin: state_FFs
        if(!reset_n)
            current_state <= S_LOAD_PM;
        else
            current_state <= next_state;
    end
endmodule
module control(
    input clk,
    input reset_n,
    input go,
    input p_hp,
	 input ai_dead,
	 input p_dead,
	 output reg victory,
	 output reg loss,
    output reg active_trainer, load_ai_hp, apply_p_damage, apply_ai_damage, target,
	 output reg state1, state2, state3
    );


    reg [5:0] current_state, next_state; 
    
    localparam  S_LOAD_PM         = 4'd0,
                S_UPDATE_AI_HP    = 4'd1,
                S_UPDATE_P_HP     = 4'd2,
                S_VICTORY         = 4'd3,
                S_LOSS            = 4'd4;
    

    always@(*)
    begin: state_table 
	         if (ai_dead)
			       next_state = S_VICTORY;
			   else if (p_dead)
				    next_state = S_LOSS;
			   else begin
					case (current_state)
						 S_LOAD_PM: next_state = S_UPDATE_AI_HP;
						 S_UPDATE_AI_HP: next_state = S_UPDATE_P_HP; 
					    S_UPDATE_P_HP: next_state = S_LOAD_PM;
						 S_VICTORY: next_state = S_VICTORY;
						 S_LOSS: next_state = S_LOSS;
						 default:   next_state = S_LOAD_PM;
				  endcase
		      end
    end
   


    always @(*)
    begin: enable_signals

        active_trainer = 1'b0;
        target = 1'b0;
		  load_ai_hp = 1'b0;
		  apply_p_damage = 1'b0;
        apply_ai_damage = 1'b0;
		  victory = 1'b0;
		  loss = 1'b0;
		  state1 = 1'b0;
		  state2 = 1'b0;
		  state3 = 1'b0;

        case (current_state)
		      S_LOAD_PM: begin
				    state1 = 1'b1;
					 end
            S_UPDATE_AI_HP: begin
				    active_trainer = 1'b0;
                target = 1'b1;
                apply_ai_damage = 1'b1;
					 state2 = 1'b1;
                end
            S_UPDATE_P_HP: begin
				    active_trainer = 1'b1;
                target = 1'b0;
                apply_p_damage = 1'b1;
					 state3 = 1'b1;
                end
            S_VICTORY: begin
                victory = 1'b1;
                end
            S_LOSS: begin
                loss = 1'b1;
                end
            

        endcase
    end
   

    always@(posedge clk)
    begin: state_FFs
        if(!reset_n)
            current_state <= S_LOAD_PM;
        else
            current_state <= next_state;
    end
endmodule