data/full_repos/permissive/143278/ivltests/repeat2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/repeat2.v:33: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n                                                                       : ... In instance main\n      test = {{0{1\'b1}}, 1\'b0};\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/repeat2.v:39: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n                                                                       : ... In instance main\n      test = {1{1\'b1}};\n           ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/repeat2.v:45: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                       : ... In instance main\n      test = {2{1\'b1}};\n           ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/repeat2.v:51: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                       : ... In instance main\n      test = {3{1\'b1}};\n           ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/repeat2.v:63: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                       : ... In instance main\n      test = {5{1\'b1}};\n           ^\n%Error: Exiting due to 5 warning(s)\n'
module main;

   reg [3:0] test;

   initial begin

      test = {{0{1'b1}}, 1'b0};
      if (test !== 4'b0000) begin
	 $display("FAILED -- {0{1'b1} == %b", test);
	 $finish;
      end

      test = {1{1'b1}};
      if (test !== 4'b0001) begin
	 $display("FAILED -- {1{1'b1} == %b", test);
	 $finish;
      end

      test = {2{1'b1}};
      if (test !== 4'b0011) begin
	 $display("FAILED -- {2{1'b1} == %b", test);
	 $finish;
      end

      test = {3{1'b1}};
      if (test !== 4'b0111) begin
	 $display("FAILED -- {3{1'b1} == %b", test);
	 $finish;
      end

      test = {4{1'b1}};
      if (test !== 4'b1111) begin
	 $display("FAILED -- {4{1'b1} == %b", test);
	 $finish;
      end

      test = {5{1'b1}};
      if (test !== 4'b1111) begin
	 $display("FAILED -- {5{1'b1} == %b", test);
	 $finish;
      end

      $display("PASSED");

   end

endmodule
module main;


   reg [3:0] test;

   initial begin

      test = {{0{1'b1}}, 1'b0};
      if (test !== 4'b0000) begin
	 $display("FAILED -- {0{1'b1} == %b", test);
	 $finish;
      end

      test = {1{1'b1}};
      if (test !== 4'b0001) begin
	 $display("FAILED -- {1{1'b1} == %b", test);
	 $finish;
      end

      test = {2{1'b1}};
      if (test !== 4'b0011) begin
	 $display("FAILED -- {2{1'b1} == %b", test);
	 $finish;
      end

      test = {3{1'b1}};
      if (test !== 4'b0111) begin
	 $display("FAILED -- {3{1'b1} == %b", test);
	 $finish;
      end

      test = {4{1'b1}};
      if (test !== 4'b1111) begin
	 $display("FAILED -- {4{1'b1} == %b", test);
	 $finish;
      end

      test = {5{1'b1}};
      if (test !== 4'b1111) begin
	 $display("FAILED -- {5{1'b1} == %b", test);
	 $finish;
      end

      $display("PASSED");

   end

endmodule