data/full_repos/permissive/184108896/testbench/fw_dd.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:43: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:48: Unsupported: Ignoring delay on this delayed statement.\n #25 in_valid = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:55: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0055_001a_0006_0052;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:56: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0006_0025_0000_001c;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:57: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h003a_000e_001e_002f;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:58: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0053_0000_0060_0019;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:59: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0023_0044_000f_002e;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:60: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0000_0033_002c_0041;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:61: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h004f_004d_0009_0058;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:62: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0034_0004_0055_0059;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:63: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0021_0064_0037_0000;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:64: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0028_0045_004d_003d;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:65: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0057_001b_0000_000d;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:66: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0047_0060_0028_005f;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:67: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0044_0000_004f_0023;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:68: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0012_0003_0062_0002;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:69: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0000_0039_0035_005d;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:71: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0036_0052_0014_0000;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:72: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0059_0013_0045_001d;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:73: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0057_004c_0000_0002;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:74: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0041_002e_0009_0048;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:75: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0042_0000_0029_0051;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:76: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h001d_002f_0010_0021;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:77: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0000_000a_001e_0057;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:78: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h002a_0034_0029_001e;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:79: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0007_001c_0020_002a;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:80: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0033_0016_0032_0000;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:81: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0054_0044_0012_0042;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:82: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h005e_0038_0000_0004;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:83: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0014_0039_0062_005a;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:84: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0001_0000_0061_0014;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:85: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0019_0062_0048_002d;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:86: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0000_0050_0018_0047;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:88: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h004e_0057_0054_0000;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:89: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0057_0024_005e_0010;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:90: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0016_0032_0000_005d;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:91: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h003c_005b_001c_003f;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:92: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0029_0000_001b_0040;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:93: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h000c_0025_0049_001b;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:94: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0000_001e_0044_0045;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:95: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0018_003f_001f_0053;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:96: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0003_001e_0024_0044;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:97: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0046_003b_0017_0000;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:98: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h000c_0039_005e_0044;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:99: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h004a_001e_0000_002b;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:100: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0026_0055_0014_0016;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:101: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0010_0000_0019_0063;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:102: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h005c_001b_000e_0047;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:103: Unsupported: Ignoring delay on this delayed statement.\n   #10 fw_in = 64\'h0000_004a_0039_0051;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184108896/testbench/fw_dd.v:106: Unsupported: Ignoring delay on this delayed statement.\n   #10 in_valid = 0;\n   ^\n%Error: data/full_repos/permissive/184108896/testbench/fw_dd.v:23: Cannot find file containing module: \'clock\'\nclock   clock(.reset(reset), .clk(clk));\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/184108896/testbench,data/full_repos/permissive/184108896/clock\n             data/full_repos/permissive/184108896/testbench,data/full_repos/permissive/184108896/clock.v\n             data/full_repos/permissive/184108896/testbench,data/full_repos/permissive/184108896/clock.sv\n             clock\n             clock.v\n             clock.sv\n             obj_dir/clock\n             obj_dir/clock.v\n             obj_dir/clock.sv\n%Error: data/full_repos/permissive/184108896/testbench/fw_dd.v:25: Cannot find file containing module: \'fw\'\nfw  fw_inst(\n^~\n%Error: Exiting due to 2 error(s), 50 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fw_dd;

reg reset;
wire clk;

reg [63:0] fw_in;
reg in_valid;
reg [1:0] phase;

clock   clock(.reset(reset), .clk(clk));

fw		fw_inst(
	.reset(reset),
	.clk(clk),
	.phase(phase),
	.inhibit(),

	.inD(fw_in),
	.in_valid(in_valid),

	.outD(),
	.out_valid()
);

initial
begin
	reset = 1;
	in_valid = 0;
	phase = 2'b11;
	#10 reset = 0;
end

initial
begin: fw_input
	#25 in_valid = 1;





   fw_in = 64'h0061_0047_003f_0000;
   #10 fw_in = 64'h0055_001a_0006_0052;
   #10 fw_in = 64'h0006_0025_0000_001c;
   #10 fw_in = 64'h003a_000e_001e_002f;
   #10 fw_in = 64'h0053_0000_0060_0019;
   #10 fw_in = 64'h0023_0044_000f_002e;
   #10 fw_in = 64'h0000_0033_002c_0041;
   #10 fw_in = 64'h004f_004d_0009_0058;
   #10 fw_in = 64'h0034_0004_0055_0059;
   #10 fw_in = 64'h0021_0064_0037_0000;
   #10 fw_in = 64'h0028_0045_004d_003d;
   #10 fw_in = 64'h0057_001b_0000_000d;
   #10 fw_in = 64'h0047_0060_0028_005f;
   #10 fw_in = 64'h0044_0000_004f_0023;
   #10 fw_in = 64'h0012_0003_0062_0002;
   #10 fw_in = 64'h0000_0039_0035_005d;

   #10 fw_in = 64'h0036_0052_0014_0000;
   #10 fw_in = 64'h0059_0013_0045_001d;
   #10 fw_in = 64'h0057_004c_0000_0002;
   #10 fw_in = 64'h0041_002e_0009_0048;
   #10 fw_in = 64'h0042_0000_0029_0051;
   #10 fw_in = 64'h001d_002f_0010_0021;
   #10 fw_in = 64'h0000_000a_001e_0057;
   #10 fw_in = 64'h002a_0034_0029_001e;
   #10 fw_in = 64'h0007_001c_0020_002a;
   #10 fw_in = 64'h0033_0016_0032_0000;
   #10 fw_in = 64'h0054_0044_0012_0042;
   #10 fw_in = 64'h005e_0038_0000_0004;
   #10 fw_in = 64'h0014_0039_0062_005a;
   #10 fw_in = 64'h0001_0000_0061_0014;
   #10 fw_in = 64'h0019_0062_0048_002d;
   #10 fw_in = 64'h0000_0050_0018_0047;

   #10 fw_in = 64'h004e_0057_0054_0000;
   #10 fw_in = 64'h0057_0024_005e_0010;
   #10 fw_in = 64'h0016_0032_0000_005d;
   #10 fw_in = 64'h003c_005b_001c_003f;
   #10 fw_in = 64'h0029_0000_001b_0040;
   #10 fw_in = 64'h000c_0025_0049_001b;
   #10 fw_in = 64'h0000_001e_0044_0045;
   #10 fw_in = 64'h0018_003f_001f_0053;
   #10 fw_in = 64'h0003_001e_0024_0044;
   #10 fw_in = 64'h0046_003b_0017_0000;
   #10 fw_in = 64'h000c_0039_005e_0044;
   #10 fw_in = 64'h004a_001e_0000_002b;
   #10 fw_in = 64'h0026_0055_0014_0016;
   #10 fw_in = 64'h0010_0000_0019_0063;
   #10 fw_in = 64'h005c_001b_000e_0047;
   #10 fw_in = 64'h0000_004a_0039_0051;


   #10 in_valid = 0;
end 
endmodule
module fw_dd;


reg reset;
wire clk;

reg [63:0] fw_in;
reg in_valid;
reg [1:0] phase;

clock   clock(.reset(reset), .clk(clk));

fw		fw_inst(
	.reset(reset),
	.clk(clk),
	.phase(phase),
	.inhibit(),

	.inD(fw_in),
	.in_valid(in_valid),

	.outD(),
	.out_valid()
);

initial
begin
	reset = 1;
	in_valid = 0;
	phase = 2'b11;
	#10 reset = 0;
end

initial
begin: fw_input
	#25 in_valid = 1;





   fw_in = 64'h0061_0047_003f_0000;
   #10 fw_in = 64'h0055_001a_0006_0052;
   #10 fw_in = 64'h0006_0025_0000_001c;
   #10 fw_in = 64'h003a_000e_001e_002f;
   #10 fw_in = 64'h0053_0000_0060_0019;
   #10 fw_in = 64'h0023_0044_000f_002e;
   #10 fw_in = 64'h0000_0033_002c_0041;
   #10 fw_in = 64'h004f_004d_0009_0058;
   #10 fw_in = 64'h0034_0004_0055_0059;
   #10 fw_in = 64'h0021_0064_0037_0000;
   #10 fw_in = 64'h0028_0045_004d_003d;
   #10 fw_in = 64'h0057_001b_0000_000d;
   #10 fw_in = 64'h0047_0060_0028_005f;
   #10 fw_in = 64'h0044_0000_004f_0023;
   #10 fw_in = 64'h0012_0003_0062_0002;
   #10 fw_in = 64'h0000_0039_0035_005d;

   #10 fw_in = 64'h0036_0052_0014_0000;
   #10 fw_in = 64'h0059_0013_0045_001d;
   #10 fw_in = 64'h0057_004c_0000_0002;
   #10 fw_in = 64'h0041_002e_0009_0048;
   #10 fw_in = 64'h0042_0000_0029_0051;
   #10 fw_in = 64'h001d_002f_0010_0021;
   #10 fw_in = 64'h0000_000a_001e_0057;
   #10 fw_in = 64'h002a_0034_0029_001e;
   #10 fw_in = 64'h0007_001c_0020_002a;
   #10 fw_in = 64'h0033_0016_0032_0000;
   #10 fw_in = 64'h0054_0044_0012_0042;
   #10 fw_in = 64'h005e_0038_0000_0004;
   #10 fw_in = 64'h0014_0039_0062_005a;
   #10 fw_in = 64'h0001_0000_0061_0014;
   #10 fw_in = 64'h0019_0062_0048_002d;
   #10 fw_in = 64'h0000_0050_0018_0047;

   #10 fw_in = 64'h004e_0057_0054_0000;
   #10 fw_in = 64'h0057_0024_005e_0010;
   #10 fw_in = 64'h0016_0032_0000_005d;
   #10 fw_in = 64'h003c_005b_001c_003f;
   #10 fw_in = 64'h0029_0000_001b_0040;
   #10 fw_in = 64'h000c_0025_0049_001b;
   #10 fw_in = 64'h0000_001e_0044_0045;
   #10 fw_in = 64'h0018_003f_001f_0053;
   #10 fw_in = 64'h0003_001e_0024_0044;
   #10 fw_in = 64'h0046_003b_0017_0000;
   #10 fw_in = 64'h000c_0039_005e_0044;
   #10 fw_in = 64'h004a_001e_0000_002b;
   #10 fw_in = 64'h0026_0055_0014_0016;
   #10 fw_in = 64'h0010_0000_0019_0063;
   #10 fw_in = 64'h005c_001b_000e_0047;
   #10 fw_in = 64'h0000_004a_0039_0051;


   #10 in_valid = 0;
end 
endmodule