data/full_repos/permissive/211316121/lab8_2_nexys4/Display.v
data/verilator_xmls/6768e043-c1d4-4bd6-ae9b-77158dc57bba.xml
module clkdiv(
    input clk,
    output clk1_4hz
);
reg [24:0] q;
always@(posedge clk)
    q<=q+1;
assign clk1_4hz=q[24];
endmodule
module clkdiv(
    input clk,
    output clk1_4hz
);

reg [24:0] q;
always@(posedge clk)
    q<=q+1;
assign clk1_4hz=q[24];
endmodule