data/full_repos/permissive/167489907/Control Unit/CPU_tb.v
1: b'%Error: Cannot find file containing module: Unit,data/full_repos/permissive/167489907\n        ... Looked in:\n             data/full_repos/permissive/167489907/Control/Unit,data/full_repos/permissive/167489907\n             data/full_repos/permissive/167489907/Control/Unit,data/full_repos/permissive/167489907.v\n             data/full_repos/permissive/167489907/Control/Unit,data/full_repos/permissive/167489907.sv\n             Unit,data/full_repos/permissive/167489907\n             Unit,data/full_repos/permissive/167489907.v\n             Unit,data/full_repos/permissive/167489907.sv\n             obj_dir/Unit,data/full_repos/permissive/167489907\n             obj_dir/Unit,data/full_repos/permissive/167489907.v\n             obj_dir/Unit,data/full_repos/permissive/167489907.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/167489907/Control\n%Error: Cannot find file containing module: Unit/CPU_tb.v\n%Error: Exiting due to 3 error(s)\n'
module CPU_tb;

reg clk, rst;
wire [3:0] status;
wire [2:0] constant_sel;
wire [63:0] D, reg_out, r1, r2, r3, r4, r5, r6, r7;
wire [33:0] control_word;
wire [31:0] IR_Out;
wire [1:0] EX0_sel;
wire AS, PC_Sel, K_Sel, IL, SL, C0, MW, RW, ram_select, rom_select;
wire [1:0] NS, DS, PS;
wire [4:0] FS, DA, SA, SB;
wire [63:0] ALU_out, K;
wire [1:0] state;
wire [31:0] PC_out, rom_out;

CPU dut(clk, rst, reg_out, status);

assign r1 = dut.core.r1;
assign r2 = dut.core.r2;
assign r3 = dut.core.r3;
assign r4 = dut.core.r4;
assign r5 = dut.core.r5;
assign r6 = dut.core.r6;
assign r7 = dut.core.r7;
assign D = dut.core.D;
assign ALU_out = dut.core.regfile_alu_ram.F;


assign ram_select = dut.core.regfile_alu_ram.ram_select;
assign rom_select = dut.core.regfile_alu_ram.rom_select;
assign rom_out = dut.core.regfile_alu_ram.rom_out;
assign PC_out = dut.core.PC_out;
assign K = dut.K;
assign control_word = dut.control_word;
assign state = dut.CU.state;
assign IR_Out = dut.core.IR_Out;
assign EX0_sel = dut.CU.EX0_sel;
assign AS = dut.AS;
assign PC_Sel = dut.PC_Sel;
assign K_Sel = dut.K_Sel;
assign constant_sel = dut.CU.constant_sel;
assign IL = dut.IL;
assign SL = dut.SL;
assign C0 = dut.C0;
assign MW = dut.MW;
assign RW = dut.RW;
assign NS = dut.NS;
assign DS = dut.DS;
assign PS = dut.PS;
assign FS = dut.FS;
assign DA = dut.DA;
assign SA = dut.SA;
assign SB = dut.SB;






























always begin
	#10 clk = ~clk;
end
	
initial begin
	clk <= 1'b0;
	rst <= 1'b1;
	#15;
	rst <= 1'b0;
	
	#50000;
	$stop;
end
endmodule
module CPU_tb;


reg clk, rst;
wire [3:0] status;
wire [2:0] constant_sel;
wire [63:0] D, reg_out, r1, r2, r3, r4, r5, r6, r7;
wire [33:0] control_word;
wire [31:0] IR_Out;
wire [1:0] EX0_sel;
wire AS, PC_Sel, K_Sel, IL, SL, C0, MW, RW, ram_select, rom_select;
wire [1:0] NS, DS, PS;
wire [4:0] FS, DA, SA, SB;
wire [63:0] ALU_out, K;
wire [1:0] state;
wire [31:0] PC_out, rom_out;

CPU dut(clk, rst, reg_out, status);

assign r1 = dut.core.r1;
assign r2 = dut.core.r2;
assign r3 = dut.core.r3;
assign r4 = dut.core.r4;
assign r5 = dut.core.r5;
assign r6 = dut.core.r6;
assign r7 = dut.core.r7;
assign D = dut.core.D;
assign ALU_out = dut.core.regfile_alu_ram.F;


assign ram_select = dut.core.regfile_alu_ram.ram_select;
assign rom_select = dut.core.regfile_alu_ram.rom_select;
assign rom_out = dut.core.regfile_alu_ram.rom_out;
assign PC_out = dut.core.PC_out;
assign K = dut.K;
assign control_word = dut.control_word;
assign state = dut.CU.state;
assign IR_Out = dut.core.IR_Out;
assign EX0_sel = dut.CU.EX0_sel;
assign AS = dut.AS;
assign PC_Sel = dut.PC_Sel;
assign K_Sel = dut.K_Sel;
assign constant_sel = dut.CU.constant_sel;
assign IL = dut.IL;
assign SL = dut.SL;
assign C0 = dut.C0;
assign MW = dut.MW;
assign RW = dut.RW;
assign NS = dut.NS;
assign DS = dut.DS;
assign PS = dut.PS;
assign FS = dut.FS;
assign DA = dut.DA;
assign SA = dut.SA;
assign SB = dut.SB;






























always begin
	#10 clk = ~clk;
end
	
initial begin
	clk <= 1'b0;
	rst <= 1'b1;
	#15;
	rst <= 1'b0;
	
	#50000;
	$stop;
end
endmodule