data/full_repos/permissive/15946916/Project3/DataMemory.v
data/verilator_xmls/08b93cae-837e-40d5-9a06-6fd50e352fca.xml
module DataMem (ReadD, Addr, WriteD, MemR, MemW, CLK, Reset_l);
	input [31:0] Addr, WriteD;
	input MemR, MemW, CLK, Reset_l;
	output [31:0] ReadD;
	reg [31:0] ReadD;
	reg [31:0] Data[4095:0];
	integer i;
	

		
	initial	begin
	   Data[0] = 4;
	   Data[1] = 3;
	   Data[2] = 50;
	   Data[3] = 40;
	   Data[4] = 30;
	   Data[5] = 0;
	   Data[6] = 0;
	   Data[7] = 0;
	   Data[8] = 0;
	end

	always @ (posedge CLK)
	begin
	if (MemR==1)
			ReadD = Data[Addr>>2];
	end
	
	always @ (negedge CLK)
	begin
		if (MemW==1)
		begin
			Data[Addr>>2] <= WriteD;
			$display("\nSTORE WORD  old MEM[%d]= %d new data= %d\n",Addr>>2 ,Data[Addr>>2], WriteD);
		end
	end
	
	
endmodule
module DataMem (ReadD, Addr, WriteD, MemR, MemW, CLK, Reset_l);

	input [31:0] Addr, WriteD;
	input MemR, MemW, CLK, Reset_l;
	output [31:0] ReadD;
	reg [31:0] ReadD;
	reg [31:0] Data[4095:0];
	integer i;
	

		
	initial	begin
	   Data[0] = 4;
	   Data[1] = 3;
	   Data[2] = 50;
	   Data[3] = 40;
	   Data[4] = 30;
	   Data[5] = 0;
	   Data[6] = 0;
	   Data[7] = 0;
	   Data[8] = 0;
	end

	always @ (posedge CLK)
	begin
	if (MemR==1)
			ReadD = Data[Addr>>2];
	end
	
	always @ (negedge CLK)
	begin
		if (MemW==1)
		begin
			Data[Addr>>2] <= WriteD;
			$display("\nSTORE WORD  old MEM[%d]= %d new data= %d\n",Addr>>2 ,Data[Addr>>2], WriteD);
		end
	end
	
	
endmodule