data/full_repos/permissive/18770871/reg_load_LHB_LLB.v
1: b'%Warning-WIDTH: data/full_repos/permissive/18770871/reg_load_LHB_LLB.v:13: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SIGNED generates 8 bits.\n                                                                         : ... In instance reg_load_LHB_LLB\n    assign Out = (opcode==4\'b1010)? {imm_val[7:0], In[7:0]} : ($signed(imm_val[7:0]));    \n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module reg_load_LHB_LLB(opcode, In, imm_val, Out);
    parameter DSIZE = 16;
    input [3:0] opcode;


    input [DSIZE-1:0] In;
    input [15:0] imm_val;
    
    output [DSIZE-1:0] Out;
    assign Out = (opcode==`LHB)? {imm_val[7:0], In[7:0]} : ($signed(imm_val[7:0]));    
endmodule
module reg_load_LHB_LLB(opcode, In, imm_val, Out);

    parameter DSIZE = 16;
    input [3:0] opcode;


    input [DSIZE-1:0] In;
    input [15:0] imm_val;
    
    output [DSIZE-1:0] Out;
    assign Out = (opcode==`LHB)? {imm_val[7:0], In[7:0]} : ($signed(imm_val[7:0]));    
endmodule