data/full_repos/permissive/160024456/lib/plain_counter_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160024456/lib/plain_counter_test.v:12: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = !clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160024456/lib/plain_counter_test.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #10 en = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160024456/lib/plain_counter_test.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160024456/lib/plain_counter_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #30\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160024456/lib/plain_counter_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160024456/lib/plain_counter_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #40\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160024456/lib/plain_counter_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/160024456/lib/plain_counter_test.v:8: Cannot find file containing module: \'plain_counter\'\n  plain_counter #(.WIDTH(4), .VAL(5)) dut1 (.clk(clk), .en(en), .inc(1\'b1), .v(v1), .r(r1));\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160024456/lib,data/full_repos/permissive/160024456/plain_counter\n             data/full_repos/permissive/160024456/lib,data/full_repos/permissive/160024456/plain_counter.v\n             data/full_repos/permissive/160024456/lib,data/full_repos/permissive/160024456/plain_counter.sv\n             plain_counter\n             plain_counter.v\n             plain_counter.sv\n             obj_dir/plain_counter\n             obj_dir/plain_counter.v\n             obj_dir/plain_counter.sv\n%Error: data/full_repos/permissive/160024456/lib/plain_counter_test.v:9: Cannot find file containing module: \'plain_counter\'\n  plain_counter #(.WIDTH(4), .VAL(2)) dut2 (.clk(clk), .en(en), .inc(r1), .v(v2), .r(r2));\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160024456/lib/plain_counter_test.v:10: Cannot find file containing module: \'plain_counter\'\n  plain_counter #(.WIDTH(4), .VAL(2)) dut3 (.clk(clk), .en(en), .inc(r2), .v(v3), .r(r3));\n  ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module plain_counter_test;

  reg clk = 0;
  reg en = 0;
  wire [3:0] v1, v2, v3;
  wire r1, r2, r3;

  plain_counter #(.WIDTH(4), .VAL(5)) dut1 (.clk(clk), .en(en), .inc(1'b1), .v(v1), .r(r1));
  plain_counter #(.WIDTH(4), .VAL(2)) dut2 (.clk(clk), .en(en), .inc(r1), .v(v2), .r(r2));
  plain_counter #(.WIDTH(4), .VAL(2)) dut3 (.clk(clk), .en(en), .inc(r2), .v(v3), .r(r3));

  always #5 clk = !clk;

  initial begin
    $display("start");

    #10 en = 1;
    if ((v1 !== 0) || (r1 !== 0) || (v2 !== 0) || (r2 !== 0) || (v3 !== 0) || (r3 !== 0))
      $display("failed time=", $time, ", v1=", v1, ", r1=", r1, ", v2=", v2, ", r2=", r2, ", v3=", v3, ", r3=", r3);

    #10
    if ((v1 !== 1) || (r1 !== 0) || (v2 !== 0) || (r2 !== 0) || (v3 !== 0) || (r3 !== 0))
      $display("failed time=", $time, ", v1=", v1, ", r1=", r1, ", v2=", v2, ", r2=", r2, ", v3=", v3, ", r3=", r3);

    #30
    if ((v1 !== 4) || (r1 !== 1) || (v2 !== 0) || (r2 !== 0) || (v3 !== 0) || (r3 !== 0))
      $display("failed time=", $time, ", v1=", v1, ", r1=", r1, ", v2=", v2, ", r2=", r2, ", v3=", v3, ", r3=", r3);

    #10
    if ((v1 !== 0) || (r1 !== 0) || (v2 !== 1) || (r2 !== 0) || (v3 !== 0) || (r3 !== 0))
      $display("failed time=", $time, ", v1=", v1, ", r1=", r1, ", v2=", v2, ", r2=", r2, ", v3=", v3, ", r3=", r3);

    #40
    if ((v1 !== 4) || (r1 !== 1) || (v2 !== 1) || (r2 !== 1) || (v3 !== 0) || (r3 !== 0))
      $display("failed time=", $time, ", v1=", v1, ", r1=", r1, ", v2=", v2, ", r2=", r2, ", v3=", v3, ", r3=", r3);

    #10
    if ((v1 !== 0) || (r1 !== 0) || (v2 !== 0) || (r2 !== 0) || (v3 !== 1) || (r3 !== 0))
      $display("failed time=", $time, ", v1=", v1, ", r1=", r1, ", v2=", v2, ", r2=", r2, ", v3=", v3, ", r3=", r3);

    $display("done");
    $finish;
  end

endmodule
module plain_counter_test;


  reg clk = 0;
  reg en = 0;
  wire [3:0] v1, v2, v3;
  wire r1, r2, r3;

  plain_counter #(.WIDTH(4), .VAL(5)) dut1 (.clk(clk), .en(en), .inc(1'b1), .v(v1), .r(r1));
  plain_counter #(.WIDTH(4), .VAL(2)) dut2 (.clk(clk), .en(en), .inc(r1), .v(v2), .r(r2));
  plain_counter #(.WIDTH(4), .VAL(2)) dut3 (.clk(clk), .en(en), .inc(r2), .v(v3), .r(r3));

  always #5 clk = !clk;

  initial begin
    $display("start");

    #10 en = 1;
    if ((v1 !== 0) || (r1 !== 0) || (v2 !== 0) || (r2 !== 0) || (v3 !== 0) || (r3 !== 0))
      $display("failed time=", $time, ", v1=", v1, ", r1=", r1, ", v2=", v2, ", r2=", r2, ", v3=", v3, ", r3=", r3);

    #10
    if ((v1 !== 1) || (r1 !== 0) || (v2 !== 0) || (r2 !== 0) || (v3 !== 0) || (r3 !== 0))
      $display("failed time=", $time, ", v1=", v1, ", r1=", r1, ", v2=", v2, ", r2=", r2, ", v3=", v3, ", r3=", r3);

    #30
    if ((v1 !== 4) || (r1 !== 1) || (v2 !== 0) || (r2 !== 0) || (v3 !== 0) || (r3 !== 0))
      $display("failed time=", $time, ", v1=", v1, ", r1=", r1, ", v2=", v2, ", r2=", r2, ", v3=", v3, ", r3=", r3);

    #10
    if ((v1 !== 0) || (r1 !== 0) || (v2 !== 1) || (r2 !== 0) || (v3 !== 0) || (r3 !== 0))
      $display("failed time=", $time, ", v1=", v1, ", r1=", r1, ", v2=", v2, ", r2=", r2, ", v3=", v3, ", r3=", r3);

    #40
    if ((v1 !== 4) || (r1 !== 1) || (v2 !== 1) || (r2 !== 1) || (v3 !== 0) || (r3 !== 0))
      $display("failed time=", $time, ", v1=", v1, ", r1=", r1, ", v2=", v2, ", r2=", r2, ", v3=", v3, ", r3=", r3);

    #10
    if ((v1 !== 0) || (r1 !== 0) || (v2 !== 0) || (r2 !== 0) || (v3 !== 1) || (r3 !== 0))
      $display("failed time=", $time, ", v1=", v1, ", r1=", r1, ", v2=", v2, ", r2=", r2, ", v3=", v3, ", r3=", r3);

    $display("done");
    $finish;
  end

endmodule