data/full_repos/permissive/136510272/projects/version.1.zx80/video.v
'utf-8' codec can't decode byte 0x82 in position 6: invalid start byte
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:28: Operator SUB expects 10 bits on the RHS, but RHS\'s CONST \'8\'h30\' generates 8 bits.\n                                                                                       : ... In instance video\nwire [9:0] rx = x - 8\'d48;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:29: Operator SUB expects 10 bits on the RHS, but RHS\'s CONST \'8\'h30\' generates 8 bits.\n                                                                                       : ... In instance video\nwire [9:0] ry = y - 8\'d48;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:38: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance video\n        x <= 1\'b0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:39: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance video\n        y <= (y == 10\'d525) ? 1\'b0 : (y + 1\'b1); \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:53: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance video\n            r <= bitset? 1\'b0 : 5\'h0F;  \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:54: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance video\n            g <= bitset? 1\'b0 : 6\'h1F;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:55: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance video\n            b <= bitset? 1\'b0 : 5\'h0F;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:60: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance video\n            r <= vga_border[0] ? 5\'h0F : 1\'b0; \n                               ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:61: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance video\n            g <= vga_border[1] ? 6\'h1F : 1\'b0;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:62: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance video\n            b <= vga_border[2] ? 5\'h0F : 1\'b0;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:67: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance video\n    end else begin r <= 1\'b0; g <= 1\'b0; b <= 1\'b0; end\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:67: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance video\n    end else begin r <= 1\'b0; g <= 1\'b0; b <= 1\'b0; end\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:67: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance video\n    end else begin r <= 1\'b0; g <= 1\'b0; b <= 1\'b0; end\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:73: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 15 bits.\n                                                                                       : ... In instance video\n        4\'h0: begin addr <= {2\'b10, ry[8:1], rx[8:4]}; end \n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/version.1.zx80/video.v:76: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 15 bits.\n                                                                                       : ... In instance video\n        4\'h1: begin addr <= {5\'b10110, ry[8:4], rx[8:4]}; bit8 <= d8_chr; end \n                         ^~\n%Error: Exiting due to 15 warning(s)\n'
module video(

    input wire        clock,        
    input wire [7:0]  d8_chr,
    input wire [2:0]  vga_border,
    output reg [13:0] addr,
    output reg [4:0]  r,
    output reg [5:0]  g,
    output reg [4:0]  b,
    output reg        hs,
    output reg        vs
);




reg  [9:0] x;
reg  [9:0] y;
reg  [7:0] attr;
reg  [7:0] bit8;
reg  [7:0] mask;


wire [9:0] rx = x - 8'd48;
wire [9:0] ry = y - 8'd48;
wire       bitset = mask[ 3'h7 ^ rx[3:1] ];


always @(posedge clock) begin


    if (x == 10'd800) begin
    
        x <= 1'b0;
        y <= (y == 10'd525) ? 1'b0 : (y + 1'b1); 
        
    end else x <= x + 1'b1;
    

    hs <= (x >= 10'd656 && x <= 10'd751);
    vs <= (y >= 10'd490 && y <= 10'd492);
    


    if (x < 10'd640 && y < 10'd480) begin
    
        if (x >= 64 && x < 576 && y >= 48 && y < 432) begin
        
            r <= bitset? 1'b0 : 5'h0F;
            g <= bitset? 1'b0 : 6'h1F;
            b <= bitset? 1'b0 : 5'h0F;
        

        end else begin 
        
            r <= vga_border[0] ? 5'h0F : 1'b0; 
            g <= vga_border[1] ? 6'h1F : 1'b0;
            b <= vga_border[2] ? 5'h0F : 1'b0;
            
        end


    end else begin r <= 1'b0; g <= 1'b0; b <= 1'b0; end

    
    case (rx[3:0])
    

        4'h0: begin addr <= {2'b10, ry[8:1], rx[8:4]}; end 
        

        4'h1: begin addr <= {5'b10110, ry[8:4], rx[8:4]}; bit8 <= d8_chr; end 
        

        4'hF: begin attr <= d8_chr; mask <= bit8; end 

    endcase

end

endmodule
module video(

    input wire        clock,        
    input wire [7:0]  d8_chr,
    input wire [2:0]  vga_border,
    output reg [13:0] addr,
    output reg [4:0]  r,
    output reg [5:0]  g,
    output reg [4:0]  b,
    output reg        hs,
    output reg        vs
);





reg  [9:0] x;
reg  [9:0] y;
reg  [7:0] attr;
reg  [7:0] bit8;
reg  [7:0] mask;


wire [9:0] rx = x - 8'd48;
wire [9:0] ry = y - 8'd48;
wire       bitset = mask[ 3'h7 ^ rx[3:1] ];


always @(posedge clock) begin


    if (x == 10'd800) begin
    
        x <= 1'b0;
        y <= (y == 10'd525) ? 1'b0 : (y + 1'b1); 
        
    end else x <= x + 1'b1;
    

    hs <= (x >= 10'd656 && x <= 10'd751);
    vs <= (y >= 10'd490 && y <= 10'd492);
    


    if (x < 10'd640 && y < 10'd480) begin
    
        if (x >= 64 && x < 576 && y >= 48 && y < 432) begin
        
            r <= bitset? 1'b0 : 5'h0F;
            g <= bitset? 1'b0 : 6'h1F;
            b <= bitset? 1'b0 : 5'h0F;
        

        end else begin 
        
            r <= vga_border[0] ? 5'h0F : 1'b0; 
            g <= vga_border[1] ? 6'h1F : 1'b0;
            b <= vga_border[2] ? 5'h0F : 1'b0;
            
        end


    end else begin r <= 1'b0; g <= 1'b0; b <= 1'b0; end

    
    case (rx[3:0])
    

        4'h0: begin addr <= {2'b10, ry[8:1], rx[8:4]}; end 
        

        4'h1: begin addr <= {5'b10110, ry[8:4], rx[8:4]}; bit8 <= d8_chr; end 
        

        4'hF: begin attr <= d8_chr; mask <= bit8; end 

    endcase

end

endmodule