data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = !clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #100; $stop;\n ^\n%Error: data/full_repos/permissive/167489907/Examples/4x16-Register-File/regfile4x16_tb.v:11: Cannot find file containing module: \'regfile4x16\'\nregfile4x16 uut (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167489907/Examples/4x16-Register-File,data/full_repos/permissive/167489907/regfile4x16\n             data/full_repos/permissive/167489907/Examples/4x16-Register-File,data/full_repos/permissive/167489907/regfile4x16.v\n             data/full_repos/permissive/167489907/Examples/4x16-Register-File,data/full_repos/permissive/167489907/regfile4x16.sv\n             regfile4x16\n             regfile4x16.v\n             regfile4x16.sv\n             obj_dir/regfile4x16\n             obj_dir/regfile4x16.v\n             obj_dir/regfile4x16.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module regfile4x16_tb;

reg clk;
reg write;
reg [2:0] wrAddr;
reg [15:0] wrData;
reg[2:0] rdAddrA, rdAddrB;

wire[15:0] rdDataA, rdDataB;

regfile4x16 uut (
	.write(write),
	.clk(clk),
	.wrAddr(wrAddr),
	.wrData(wrData),
	.rdAddrA(rdAddrA),
	.rdAddrB(rdAddrB),
	.rdDataA(rdDataA),
	.rdDataB(rdDataB));
	
initial clk = 0;
always #10 clk = !clk;
initial begin
	write = 1'b0;
	wrAddr = 3'b0;
	wrData = 16'b0;
	rdAddrA = 3'bx;
	rdAddrB = 3'bx;
	#100;
	
	wrAddr = 3'b000;
	#100;
	wrData = 16'hFFFF;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	wrAddr = 3'b001;
	#100;
	wrData = 16'hAAAA;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	wrAddr = 3'b010;
	#100;
	wrData = 16'hCCCC;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	wrAddr = 3'b011;
	#100;
	wrData = 16'hF0F0;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	rdAddrA = 3'b000;
	rdAddrB = 3'b001;
	#100;
	rdAddrA = 3'b010;
	rdAddrB = 3'b011;
	#100; $stop;
end
endmodule
module regfile4x16_tb;


reg clk;
reg write;
reg [2:0] wrAddr;
reg [15:0] wrData;
reg[2:0] rdAddrA, rdAddrB;

wire[15:0] rdDataA, rdDataB;

regfile4x16 uut (
	.write(write),
	.clk(clk),
	.wrAddr(wrAddr),
	.wrData(wrData),
	.rdAddrA(rdAddrA),
	.rdAddrB(rdAddrB),
	.rdDataA(rdDataA),
	.rdDataB(rdDataB));
	
initial clk = 0;
always #10 clk = !clk;
initial begin
	write = 1'b0;
	wrAddr = 3'b0;
	wrData = 16'b0;
	rdAddrA = 3'bx;
	rdAddrB = 3'bx;
	#100;
	
	wrAddr = 3'b000;
	#100;
	wrData = 16'hFFFF;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	wrAddr = 3'b001;
	#100;
	wrData = 16'hAAAA;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	wrAddr = 3'b010;
	#100;
	wrData = 16'hCCCC;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	wrAddr = 3'b011;
	#100;
	wrData = 16'hF0F0;
	#100;
	
	write = 1'b0;
	#100;
	write = 1'b1;
	#100;
	rdAddrA = 3'b000;
	rdAddrB = 3'b001;
	#100;
	rdAddrA = 3'b010;
	rdAddrB = 3'b011;
	#100; $stop;
end
endmodule