data/full_repos/permissive/143278/ivltests/pr1697732.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1697732.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #1 if (test_bit !== value[addr]) begin\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1697732.v:6: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                        : ... In instance main\n   wire       test_bit = value[addr] == 1;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1697732.v:14: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                         : ... In instance main\n       addr, value[addr], test_bit);\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1697732.v:12: Bit extraction of var[3:0] requires 2 bit index, not 3 bits.\n                                                                         : ... In instance main\n  #1 if (test_bit !== value[addr]) begin\n                           ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [3:0]  value;
   reg [2:0]  addr;

   wire       test_bit = value[addr] == 1;

   initial begin
      value = 'b0110;

      for (addr = 0 ;  addr < 4 ;  addr = addr+1) begin
	 #1 if (test_bit !== value[addr]) begin
	    $display("FAILED -- value[%d]=%b, test_bit=%b",
		     addr, value[addr], test_bit);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule
module main;


   reg [3:0]  value;
   reg [2:0]  addr;

   wire       test_bit = value[addr] == 1;

   initial begin
      value = 'b0110;

      for (addr = 0 ;  addr < 4 ;  addr = addr+1) begin
	 #1 if (test_bit !== value[addr]) begin
	    $display("FAILED -- value[%d]=%b, test_bit=%b",
		     addr, value[addr], test_bit);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule