data/full_repos/permissive/136510272/projects/vga640x480/videoadapter.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/vga640x480/videoadapter.v:39: Operator GT expects 11 bits on the RHS, but RHS\'s CONST \'10\'h2b0\' generates 10 bits.\n                                                                                          : ... In instance videoadapter\nassign  hs = x > 10\'d688 && x <= 10\'d784; \n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/vga640x480/videoadapter.v:39: Operator LTE expects 11 bits on the RHS, but RHS\'s CONST \'10\'h310\' generates 10 bits.\n                                                                                          : ... In instance videoadapter\nassign  hs = x > 10\'d688 && x <= 10\'d784; \n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/vga640x480/videoadapter.v:41: Operator LT expects 11 bits on the RHS, but RHS\'s CONST \'10\'h280\' generates 10 bits.\n                                                                                          : ... In instance videoadapter\nwire    display = x < 10\'d640 && y < 10\'d480;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/vga640x480/videoadapter.v:54: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                          : ... In instance videoadapter\n    x <= xend ?         1\'b0 : x + 1\'b1;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/vga640x480/videoadapter.v:55: Operator COND expects 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                          : ... In instance videoadapter\n    y <= xend ? (yend ? 1\'b0 : y + 1\'b1) : y;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/vga640x480/videoadapter.v:60: Operator ASSIGNDLY expects 22 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                                          : ... In instance videoadapter\n        addr <= {y[8:1], x[8:1]}; \n             ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/vga640x480/videoadapter.v:68: Operator ASSIGNDLY expects 22 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                                          : ... In instance videoadapter\n        addr <= {y[8:1], x[8:1]}; \n             ^~\n%Error: Exiting due to 7 warning(s)\n'
module videoadapter(

    input   wire            clock,
    output  wire            hs,
    output  wire            vs,
    output  wire    [4:0]   r,
    output  wire    [5:0]   g,
    output  wire    [4:0]   b,
    
    input   wire            busy,
    output  reg             rden,
    output  reg     [21:0]  addr,
    input   wire    [15:0]  dr,
    
    output  reg     [15:0]  dw,
    output  reg             wren
);

assign r = dp[15:11];
assign g = dp[10:5];
assign b = dp[4:0];

reg     [15:0]  dp;
reg     [2:0]   div25;
reg     [10:0]  x;
reg     [9:0]   y;

assign  hs = x > 10'd688 && x <= 10'd784; 
assign  vs = y > 10'd513 && y <= 10'd515; 
wire    display = x < 10'd640 && y < 10'd480;
wire    xend = x == 11'd800;
wire    yend = y == 10'd525;






always @(posedge clock) div25 <= div25 + 1'b1;
always @(posedge div25[1]) begin    


    x <= xend ?         1'b0 : x + 1'b1;
    y <= xend ? (yend ? 1'b0 : y + 1'b1) : y;
    
    if (display) begin

        dp   <= dr;
        addr <= {y[8:1], x[8:1]}; 
        rden <= 1'b1;  
        wren <= 1'b0;
    

    end else begin 
    
        rden <= 1'b0;         
        addr <= {y[8:1], x[8:1]}; 
        
        if (y > 40 && y < 80 && x < 790) begin dw <= {x[4:0],x[5:0],y[4:0]}; wren <= 1'b1; end else wren <= 1'b0;
        
    end

end

endmodule
module videoadapter(

    input   wire            clock,
    output  wire            hs,
    output  wire            vs,
    output  wire    [4:0]   r,
    output  wire    [5:0]   g,
    output  wire    [4:0]   b,
    
    input   wire            busy,
    output  reg             rden,
    output  reg     [21:0]  addr,
    input   wire    [15:0]  dr,
    
    output  reg     [15:0]  dw,
    output  reg             wren
);


assign r = dp[15:11];
assign g = dp[10:5];
assign b = dp[4:0];

reg     [15:0]  dp;
reg     [2:0]   div25;
reg     [10:0]  x;
reg     [9:0]   y;

assign  hs = x > 10'd688 && x <= 10'd784; 
assign  vs = y > 10'd513 && y <= 10'd515; 
wire    display = x < 10'd640 && y < 10'd480;
wire    xend = x == 11'd800;
wire    yend = y == 10'd525;






always @(posedge clock) div25 <= div25 + 1'b1;
always @(posedge div25[1]) begin    


    x <= xend ?         1'b0 : x + 1'b1;
    y <= xend ? (yend ? 1'b0 : y + 1'b1) : y;
    
    if (display) begin

        dp   <= dr;
        addr <= {y[8:1], x[8:1]}; 
        rden <= 1'b1;  
        wren <= 1'b0;
    

    end else begin 
    
        rden <= 1'b0;         
        addr <= {y[8:1], x[8:1]}; 
        
        if (y > 40 && y < 80 && x < 790) begin dw <= {x[4:0],x[5:0],y[4:0]}; wren <= 1'b1; end else wren <= 1'b0;
        
    end

end

endmodule