data/full_repos/permissive/176628218/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/176628218/test.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/176628218/test.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #100 one_brd =1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176628218/test.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #100 one_brd =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176628218/test.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #100 two_brd =1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176628218/test.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #100 two_brd =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176628218/test.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #100 five_brd =1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176628218/test.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #100 five_brd =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176628218/test.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #100 p1_brd = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176628218/test.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #100 p1_brd = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/176628218/test.v:97: Unsupported: Ignoring delay on this delayed statement.\n #5 clk_brd = ~clk_brd;\n ^\n%Error: data/full_repos/permissive/176628218/test.v:49: Cannot find file containing module: \'top_module\'\n top_module uut (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/176628218,data/full_repos/permissive/176628218/top_module\n             data/full_repos/permissive/176628218,data/full_repos/permissive/176628218/top_module.v\n             data/full_repos/permissive/176628218,data/full_repos/permissive/176628218/top_module.sv\n             top_module\n             top_module.v\n             top_module.sv\n             obj_dir/top_module\n             obj_dir/top_module.v\n             obj_dir/top_module.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;


	reg clk_brd;
	reg reset_brd;
	reg cancel_brd;
	reg ten_brd;
	reg one_brd;
	reg five_brd;
	reg two_brd;
	reg p0_brd;
	reg p1_brd;
	reg p2_brd;
	reg p3_brd;


	wire power_brd;
	wire used_brd;
	wire get_brd;
	wire back_brd;
	wire [7:0] seg_brd;
	wire [7:0] an;


	top_module uut (
		.clk_brd(clk_brd), 
		.reset_brd(reset_brd), 
		.cancel_brd(cancel_brd), 
		.ten_brd(ten_brd), 
		.one_brd(one_brd), 
		.five_brd(five_brd), 
		.two_brd(two_brd), 
		.p0_brd(p0_brd), 
		.p1_brd(p1_brd), 
		.p2_brd(p2_brd), 
		.p3_brd(p3_brd), 
		.power_brd(power_brd), 
		.used_brd(used_brd), 
		.get_brd(get_brd), 
		.back_brd(back_brd), 
		.seg_brd(seg_brd), 
		.an(an)
	);

	initial begin

		clk_brd = 0;
		reset_brd = 0;
		cancel_brd = 0;
		ten_brd = 0;
		one_brd = 0;
		five_brd = 0;
		two_brd = 0;
		p0_brd = 0;
		p1_brd = 0;
		p2_brd = 0;
		p3_brd = 0;


		#100;
        

		#100 one_brd =1;
		#100 one_brd =0;
		#100 two_brd =1;
		#100 two_brd =0;
		#100 five_brd =1;
		#100 five_brd =0;
		#100 p1_brd = 1;
		#100 p1_brd = 0;
	end
   always begin
	#5	clk_brd = ~clk_brd;
	end
	
endmodule
module test;



	reg clk_brd;
	reg reset_brd;
	reg cancel_brd;
	reg ten_brd;
	reg one_brd;
	reg five_brd;
	reg two_brd;
	reg p0_brd;
	reg p1_brd;
	reg p2_brd;
	reg p3_brd;


	wire power_brd;
	wire used_brd;
	wire get_brd;
	wire back_brd;
	wire [7:0] seg_brd;
	wire [7:0] an;


	top_module uut (
		.clk_brd(clk_brd), 
		.reset_brd(reset_brd), 
		.cancel_brd(cancel_brd), 
		.ten_brd(ten_brd), 
		.one_brd(one_brd), 
		.five_brd(five_brd), 
		.two_brd(two_brd), 
		.p0_brd(p0_brd), 
		.p1_brd(p1_brd), 
		.p2_brd(p2_brd), 
		.p3_brd(p3_brd), 
		.power_brd(power_brd), 
		.used_brd(used_brd), 
		.get_brd(get_brd), 
		.back_brd(back_brd), 
		.seg_brd(seg_brd), 
		.an(an)
	);

	initial begin

		clk_brd = 0;
		reset_brd = 0;
		cancel_brd = 0;
		ten_brd = 0;
		one_brd = 0;
		five_brd = 0;
		two_brd = 0;
		p0_brd = 0;
		p1_brd = 0;
		p2_brd = 0;
		p3_brd = 0;


		#100;
        

		#100 one_brd =1;
		#100 one_brd =0;
		#100 two_brd =1;
		#100 two_brd =0;
		#100 five_brd =1;
		#100 five_brd =0;
		#100 p1_brd = 1;
		#100 p1_brd = 0;
	end
   always begin
	#5	clk_brd = ~clk_brd;
	end
	
endmodule