data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:358: Cannot find file containing module: 'NOR3A'\n    NOR3A \\SM_8S_1_i_0_a3[3]  (.A(Disp_dat[2]), .B(Disp_dat[0]), .C(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis,data/full_repos/permissive/165160692/NOR3A\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis,data/full_repos/permissive/165160692/NOR3A.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis,data/full_repos/permissive/165160692/NOR3A.sv\n             NOR3A\n             NOR3A.v\n             NOR3A.sv\n             obj_dir/NOR3A\n             obj_dir/NOR3A.v\n             obj_dir/NOR3A.sv\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:360: Cannot find file containing module: 'NOR2A'\n    NOR2A \\SM_8S_1_i_0_1[3]  (.A(SM_8S_1_i_0_a3_0_0), .B(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:362: Cannot find file containing module: 'NOR2B'\n    NOR2B \\SM_8S_1_i_0_o2[1]  (.A(Disp_dat[3]), .B(Disp_dat[1]), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:364: Cannot find file containing module: 'NOR3B'\n    NOR3B \\SM_8S_1_i_i_a2[6]  (.A(Disp_dat[1]), .B(Disp_dat[2]), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:366: Cannot find file containing module: 'AX1C'\n    AX1C \\SM_8S_1_i_i_x2[6]  (.A(Disp_dat[1]), .B(Disp_dat[2]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:368: Cannot find file containing module: 'GND'\n    GND GND_i_0 (.Y(GND_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:369: Cannot find file containing module: 'NOR2'\n    NOR2 \\SM_8S_1_0_0_o2[5]  (.A(Disp_dat[1]), .B(Disp_dat[2]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:371: Cannot find file containing module: 'OR2B'\n    OR2B \\SM_8S_1_i_0_a3_0[1]  (.A(Disp_dat[2]), .B(Disp_dat[0]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:373: Cannot find file containing module: 'AO1C'\n    AO1C \\SM_8S_1_0_0[5]  (.A(N_17), .B(Disp_dat[0]), .C(N_15_i), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:375: Cannot find file containing module: 'VCC'\n    VCC VCC_i (.Y(VCC));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:376: Cannot find file containing module: 'OR3C'\n    OR3C \\SM_8S_1_0_i_a3_0[2]  (.A(Disp_dat[3]), .B(Disp_dat[0]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:378: Cannot find file containing module: 'AO1A'\n    AO1A \\SM_8S_1_i_i_a3[6]  (.A(Disp_dat[0]), .B(Disp_dat[2]), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:380: Cannot find file containing module: 'AOI1B'\n    AOI1B \\SM_8S_1_i_i_a3_0[4]  (.A(Disp_dat[2]), .B(Disp_dat[1]), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:382: Cannot find file containing module: 'GND'\n    GND GND_i (.Y(GND));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:383: Cannot find file containing module: 'XOR2'\n    XOR2 \\SM_8S_1_i_0_x2[0]  (.A(Disp_dat[2]), .B(Disp_dat[0]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:385: Cannot find file containing module: 'OA1B'\n    OA1B \\SM_8S_1_i_0[1]  (.A(N_19), .B(\\SM_8S_1_i_0_a3_0[1]_net_1 ), \n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:387: Cannot find file containing module: 'VCC'\n    VCC VCC_i_0 (.Y(VCC_0));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:388: Cannot find file containing module: 'OR2B'\n    OR2B \\SM_8S_1_i_i_1[6]  (.A(N_70), .B(N_15_i), .Y(Seg_c[6]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:389: Cannot find file containing module: 'OR2A'\n    OR2A \\SM_8S_1_i_0_a3_0[0]  (.A(N_19), .B(N_14_i_i), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:683: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_3[2]  (.A(Q_NS_e2_0_a2_1_0), .B(N_30), .Y(N_40));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:684: Cannot find file containing module: 'AOI1B'\n    AOI1B \\Q_NS_RNO_2[2]  (.A(Q_NS[2]), .B(Q_NSlde_i_o2tt_m1_0_a2), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:686: Cannot find file containing module: 'OR3C'\n    OR3C \\Q_NS_RNO[1]  (.A(N_34), .B(Q_NS_e1_0_0), .C(N_39_i), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:688: Cannot find file containing module: 'AOI1B'\n    AOI1B \\Q_NS_RNO_0[4]  (.A(Q_NS[4]), .B(Q_NSlde_i_o2tt_m1_0_a2), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:690: Cannot find file containing module: 'OR2B'\n    OR2B Q_NS_e1_0_a2_4 (.A(N_30), .B(one_seond_clk_0_Cout), .Y(N_62));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:691: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_1[7]  (.A(Q_NS[7]), .B(Q_NSlde_i_o2tt_m1_0_a2), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:693: Cannot find file containing module: 'OR3C'\n    OR3C \\Q_NS_RNO[7]  (.A(N_56), .B(N_58), .C(N_57), .Y(Q_NS_e7));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:694: Cannot find file containing module: 'OR3'\n    OR3 \\Q_NS_RNO_2[3]  (.A(N_19), .B(Q_NS[3]), .C(N_62), .Y(N_44));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:695: Cannot find file containing module: 'OA1'\n    OA1 \\Q_NS_RNO_2[6]  (.A(N_22), .B(Q_NS[5]), .C(Q_NS[6]), .Y(\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:697: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_0[3]  (.A(Q_NS_e3_0_a2_0), .B(N_30), .Y(N_43));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:698: Cannot find file containing module: 'NOR2B'\n    NOR2B \\Q_NS_RNO_3[3]  (.A(Q_NS[3]), .B(N_19), .Y(Q_NS_e3_0_a2_0));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:699: Cannot find file containing module: 'VCC'\n    VCC VCC_i (.Y(VCC));\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:700: Cannot find file containing module: 'NOR2B'\n    NOR2B \\Q_NS_RNO_3[5]  (.A(Q_NS[5]), .B(N_22), .Y(Q_NS_e5_0_a2_0_0));\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:701: Cannot find file containing module: 'OR3B'\n    OR3B \\Q_NS_RNO_0[7]  (.A(N_30), .B(Q_NS[7]), .C(N_26), .Y(N_56));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:702: Cannot find file containing module: 'NOR3'\n    NOR3 \\Q_NS_RNISBRL[6]  (.A(N_22), .B(Q_NS[5]), .C(Q_NS[6]), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:704: Cannot find file containing module: 'DFN1'\n    DFN1 \\Q_NS[0]  (.D(Q_NS_e0), .CLK(Clk_c), .Q(Q_NS[0]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:705: Cannot find file containing module: 'AO1C'\n    AO1C \\Q_NS_RNO[2]  (.A(N_19), .B(N_24), .C(Q_NS_e2_0_2), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:707: Cannot find file containing module: 'OR3B'\n    OR3B \\Q_NS_RNIF75S[7]  (.A(one_seond_clk_0_Cout), .B(N_26), .C(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:709: Cannot find file containing module: 'OR3B'\n    OR3B \\Q_NS_RNO_1[2]  (.A(Green2_c), .B(N_16), .C(N_30), .Y(N_41));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:710: Cannot find file containing module: 'DFN1'\n    DFN1 \\Q_NS[7]  (.D(Q_NS_e7), .CLK(Clk_c), .Q(Q_NS[7]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:711: Cannot find file containing module: 'NOR2A'\n    NOR2A Q_NS_e2_0_a2_4_1 (.A(current_state[0]), .B(Red1_c), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:713: Cannot find file containing module: 'DFN1'\n    DFN1 \\Q_NS[5]  (.D(Q_NS_e5), .CLK(Clk_c), .Q(Q_NS[5]));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:714: Cannot find file containing module: 'NOR3C'\n    NOR3C \\Q_NS_RNO_0[2]  (.A(N_41), .B(Q_NS_e2_0_0), .C(N_39_i), .Y(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:716: Cannot find file containing module: 'NOR2'\n    NOR2 un1_Reset_1_i_i_a2 (.A(Ld_i), .B(Reset_c), .Y(N_30));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:717: Cannot find file containing module: 'OR3C'\n    OR3C \\Q_NS_RNO[3]  (.A(N_43), .B(N_45), .C(N_44), .Y(Q_NS_e3));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:718: Cannot find file containing module: 'AOI1B'\n    AOI1B \\Q_NS_RNO_0[6]  (.A(Q_NS[6]), .B(Q_NSlde_i_o2tt_m1_0_a2), .C(\n    ^~~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:720: Cannot find file containing module: 'OR3A'\n    OR3A \\Q_NS_RNO_2[7]  (.A(N_26), .B(N_62), .C(Q_NS[7]), .Y(N_57));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:721: Cannot find file containing module: 'OA1'\n    OA1 \\Q_NS_RNO_4[2]  (.A(Q_NS[0]), .B(Q_NS[1]), .C(Q_NS[2]), .Y(\n    ^~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:723: Cannot find file containing module: 'OR3A'\n    OR3A \\Q_NS_RNO_1[5]  (.A(N_24), .B(N_22), .C(Q_NS[5]), .Y(N_51));\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:724: Cannot find file containing module: 'AO1C'\n    AO1C \\Q_NS_RNO[6]  (.A(N_62), .B(N_26), .C(Q_NS_e6_0_0), .Y(\n    ^~~~\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_traf_ctl/synthesis/XYF.v:726: Cannot find file containing module: 'OR2B'\n    OR2B \\Q_NS_RNO_1[6]  (.A(Q_NS_e6_0_a2_0), .B(N_30), .Y(N_54));\n    ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module XYF(
       Clk,
       Reset,
       Red1,
       Yellow1,
       Green1,
       Red2,
       Yellow2,
       Green2,
       Seg,
       Sl
    );
input  Clk;
input  Reset;
output Red1;
output Yellow1;
output Green1;
output Red2;
output Yellow2;
output Green2;
output [7:0] Seg;
output [3:0] Sl;

    wire \Q_NS_0[0] , \Q_NS_0[1] , \Q_NS_0[2] , \Q_NS_0[3] , 
        \Q_NS_0[4] , \Q_NS_0[5] , \Q_NS_0[6] , \Q_NS_0[7] , \Q_NS[0] , 
        \Q_NS[1] , \Q_NS[2] , \Q_NS[3] , \Q_NS[4] , \Q_NS[5] , 
        \Q_NS[6] , \Q_NS[7] , one_seond_clk_0_Cout, VCC, 
        \trattic_control_0.current_state[0] , \timer_EW.State_i_0[3] , 
        \dymamic_led_0.Disp_dat9 , \dymamic_led_0.Disp_dat6 , 
        \dymamic_led_0.Disp_dat7 , \dymamic_led_0.Disp_dat8 , 
        \SM_8S_1_i_0_a3_0[0] , \SM_8S_1_i_0[1] , 
        \dymamic_led_0.HC4511_0.N_6 , Clk_c, Reset_c, Red1_c, 
        Yellow1_c, Green1_c, Green2_c, \Seg_c[4] , \Seg_c[5] , 
        \Seg_c[6] , GND, timer_NS_0_Done_NS, timer_EW_Done_NS, 
        \timer_NS_0.Ld_i , \un1_BIN_to_BCD_1[1] , 
        \un1_BIN_to_BCD_1_1[0] , \un1_BIN_to_BCD_0_1[1] , 
        \un1_BIN_to_BCD_1_1[1] , \un1_BIN_to_BCD_0[1] , 
        \un1_BIN_to_BCD_0_1[0] , \un1_BIN_to_BCD_1[2] , 
        \un1_BIN_to_BCD_0_1[2] , \un1_BIN_to_BCD_1_1[2] , 
        \un1_BIN_to_BCD_0[2] , \un1_BIN_to_BCD_0[3] , 
        \un1_BIN_to_BCD_1_1[3] , \un1_BIN_to_BCD_1[3] , 
        \un1_BIN_to_BCD_0_1[3] , Q_NSlde_i_o2tt_m1_0_a2, 
        \dymamic_led_0.HC4511_0.N_21_i_0 , Red1_c_i, \timer_EW.Ld_i , 
        \timer_NS_0.N_16 , \timer_EW.N_60 , GND_0, VCC_0;
    
    BIN_to_BCD_BIN_to_BCD_0 BIN_to_BCD_0 (.un1_BIN_to_BCD_0({
        \un1_BIN_to_BCD_0[3] , \un1_BIN_to_BCD_0[2] , 
        \un1_BIN_to_BCD_0[1] }), .un1_BIN_to_BCD_0_1({
        \un1_BIN_to_BCD_0_1[3] , \un1_BIN_to_BCD_0_1[2] , 
        \un1_BIN_to_BCD_0_1[1] , \un1_BIN_to_BCD_0_1[0] }), .Q_NS_0({
        \Q_NS_0[7] , \Q_NS_0[6] , \Q_NS_0[5] , \Q_NS_0[4] , 
        \Q_NS_0[3] , \Q_NS_0[2] , \Q_NS_0[1] }));
    CLKBUF Clk_pad (.PAD(Clk), .Y(Clk_c));
    OUTBUF \Sl_pad[0]  (.D(\dymamic_led_0.Disp_dat6 ), .PAD(Sl[0]));
    OUTBUF \Seg_pad[5]  (.D(\Seg_c[5] ), .PAD(Seg[5]));
    OUTBUF Yellow2_pad (.D(\timer_EW.State_i_0[3] ), .PAD(Yellow2));
    GND GND_i_0 (.Y(GND_0));
    one_seond_clk one_seond_clk_0 (.Clk_c(Clk_c), 
        .one_seond_clk_0_Cout(one_seond_clk_0_Cout), .Reset_c(Reset_c));
    trattic_control trattic_control_0 (.State_i_0({
        \timer_EW.State_i_0[3] }), .current_state({
        \trattic_control_0.current_state[0] }), .Reset_c(Reset_c), 
        .Clk_c(Clk_c), .timer_EW_Done_NS(timer_EW_Done_NS), .Yellow1_c(
        Yellow1_c), .Red1_c_i(Red1_c_i), .Ld_i_0(\timer_NS_0.Ld_i ), 
        .Green1_c(Green1_c), .timer_NS_0_Done_NS(timer_NS_0_Done_NS), 
        .Ld_i(\timer_EW.Ld_i ), .Red1_c(Red1_c), .Green2_c(Green2_c));
    OUTBUF \Sl_pad[1]  (.D(\dymamic_led_0.Disp_dat7 ), .PAD(Sl[1]));
    OUTBUF \Seg_pad[2]  (.D(\dymamic_led_0.HC4511_0.N_6 ), .PAD(Seg[2])
        );
    VCC VCC_i (.Y(VCC));
    OUTBUF \Seg_pad[4]  (.D(\Seg_c[4] ), .PAD(Seg[4]));
    OUTBUF \Seg_pad[3]  (.D(\dymamic_led_0.HC4511_0.N_21_i_0 ), .PAD(
        Seg[3]));
    BIN_to_BCD_BIN_to_BCD_0_1 BIN_to_BCD_1 (.un1_BIN_to_BCD_1({
        \un1_BIN_to_BCD_1[3] , \un1_BIN_to_BCD_1[2] , 
        \un1_BIN_to_BCD_1[1] }), .un1_BIN_to_BCD_1_1({
        \un1_BIN_to_BCD_1_1[3] , \un1_BIN_to_BCD_1_1[2] , 
        \un1_BIN_to_BCD_1_1[1] , \un1_BIN_to_BCD_1_1[0] }), .Q_NS({
        \Q_NS[7] , \Q_NS[6] , \Q_NS[5] , \Q_NS[4] , \Q_NS[3] , 
        \Q_NS[2] , \Q_NS[1] }));
    OUTBUF \Seg_pad[6]  (.D(\Seg_c[6] ), .PAD(Seg[6]));
    OUTBUF Green2_pad (.D(Green2_c), .PAD(Green2));
    dymamic_led dymamic_led_0 (.SM_8S_1_i_0({\SM_8S_1_i_0[1] }), 
        .SM_8S_1_i_0_a3_0({\SM_8S_1_i_0_a3_0[0] }), .Seg_c({\Seg_c[6] , 
        \Seg_c[5] , \Seg_c[4] }), .Q_NS({\Q_NS[0] }), .Q_NS_0({
        \Q_NS_0[0] }), .un1_BIN_to_BCD_1_1({\un1_BIN_to_BCD_1_1[3] , 
        \un1_BIN_to_BCD_1_1[2] , \un1_BIN_to_BCD_1_1[1] , 
        \un1_BIN_to_BCD_1_1[0] }), .un1_BIN_to_BCD_0_1({
        \un1_BIN_to_BCD_0_1[3] , \un1_BIN_to_BCD_0_1[2] , 
        \un1_BIN_to_BCD_0_1[1] , \un1_BIN_to_BCD_0_1[0] }), 
        .un1_BIN_to_BCD_1({\un1_BIN_to_BCD_1[3] , 
        \un1_BIN_to_BCD_1[2] , \un1_BIN_to_BCD_1[1] }), 
        .un1_BIN_to_BCD_0({\un1_BIN_to_BCD_0[3] , 
        \un1_BIN_to_BCD_0[2] , \un1_BIN_to_BCD_0[1] }), .N_6(
        \dymamic_led_0.HC4511_0.N_6 ), .N_21_i_0(
        \dymamic_led_0.HC4511_0.N_21_i_0 ), .Reset_c(Reset_c), .Clk_c(
        Clk_c), .Disp_dat8(\dymamic_led_0.Disp_dat8 ), .Disp_dat7(
        \dymamic_led_0.Disp_dat7 ), .Disp_dat6(
        \dymamic_led_0.Disp_dat6 ), .Disp_dat9(
        \dymamic_led_0.Disp_dat9 ));
    GND GND_i (.Y(GND));
    OUTBUF Yellow1_pad (.D(Yellow1_c), .PAD(Yellow1));
    INBUF Reset_pad (.PAD(Reset), .Y(Reset_c));
    OUTBUF Red1_pad (.D(Red1_c), .PAD(Red1));
    VCC VCC_i_0 (.Y(VCC_0));
    timer_NS timer_NS_0 (.current_state({
        \trattic_control_0.current_state[0] }), .Q_NS_0({\Q_NS_0[7] , 
        \Q_NS_0[6] , \Q_NS_0[5] , \Q_NS_0[4] , \Q_NS_0[3] , 
        \Q_NS_0[2] , \Q_NS_0[1] , \Q_NS_0[0] }), .Clk_c(Clk_c), 
        .Red1_c(Red1_c), .Yellow1_c(Yellow1_c), 
        .Q_NSlde_i_o2tt_m1_0_a2(Q_NSlde_i_o2tt_m1_0_a2), .N_60_0(
        \timer_EW.N_60 ), .Ld_i(\timer_NS_0.Ld_i ), .Reset_c(Reset_c), 
        .timer_NS_0_Done_NS(timer_NS_0_Done_NS), .one_seond_clk_0_Cout(
        one_seond_clk_0_Cout), .N_16(\timer_NS_0.N_16 ));
    OUTBUF \Sl_pad[3]  (.D(\dymamic_led_0.Disp_dat9 ), .PAD(Sl[3]));
    OUTBUF \Sl_pad[2]  (.D(\dymamic_led_0.Disp_dat8 ), .PAD(Sl[2]));
    timer_EW timer_EW (.current_state({
        \trattic_control_0.current_state[0] }), .Q_NS({\Q_NS[7] , 
        \Q_NS[6] , \Q_NS[5] , \Q_NS[4] , \Q_NS[3] , \Q_NS[2] , 
        \Q_NS[1] , \Q_NS[0] }), .Clk_c(Clk_c), .timer_EW_Done_NS(
        timer_EW_Done_NS), .Red1_c(Red1_c), .Q_NSlde_i_o2tt_m1_0_a2(
        Q_NSlde_i_o2tt_m1_0_a2), .one_seond_clk_0_Cout(
        one_seond_clk_0_Cout), .Reset_c(Reset_c), .Ld_i(
        \timer_EW.Ld_i ), .Green2_c(Green2_c), .N_16(\timer_NS_0.N_16 )
        , .N_60(\timer_EW.N_60 ));
    OUTBUF \Seg_pad[1]  (.D(\SM_8S_1_i_0[1] ), .PAD(Seg[1]));
    OUTBUF Red2_pad (.D(Red1_c_i), .PAD(Red2));
    OUTBUF \Seg_pad[7]  (.D(GND), .PAD(Seg[7]));
    OUTBUF \Seg_pad[0]  (.D(\SM_8S_1_i_0_a3_0[0] ), .PAD(Seg[0]));
    OUTBUF Green1_pad (.D(Green1_c), .PAD(Green1));
    
endmodule
module XYF(
       Clk,
       Reset,
       Red1,
       Yellow1,
       Green1,
       Red2,
       Yellow2,
       Green2,
       Seg,
       Sl
    );

input  Clk;
input  Reset;
output Red1;
output Yellow1;
output Green1;
output Red2;
output Yellow2;
output Green2;
output [7:0] Seg;
output [3:0] Sl;

    wire \Q_NS_0[0] , \Q_NS_0[1] , \Q_NS_0[2] , \Q_NS_0[3] , 
        \Q_NS_0[4] , \Q_NS_0[5] , \Q_NS_0[6] , \Q_NS_0[7] , \Q_NS[0] , 
        \Q_NS[1] , \Q_NS[2] , \Q_NS[3] , \Q_NS[4] , \Q_NS[5] , 
        \Q_NS[6] , \Q_NS[7] , one_seond_clk_0_Cout, VCC, 
        \trattic_control_0.current_state[0] , \timer_EW.State_i_0[3] , 
        \dymamic_led_0.Disp_dat9 , \dymamic_led_0.Disp_dat6 , 
        \dymamic_led_0.Disp_dat7 , \dymamic_led_0.Disp_dat8 , 
        \SM_8S_1_i_0_a3_0[0] , \SM_8S_1_i_0[1] , 
        \dymamic_led_0.HC4511_0.N_6 , Clk_c, Reset_c, Red1_c, 
        Yellow1_c, Green1_c, Green2_c, \Seg_c[4] , \Seg_c[5] , 
        \Seg_c[6] , GND, timer_NS_0_Done_NS, timer_EW_Done_NS, 
        \timer_NS_0.Ld_i , \un1_BIN_to_BCD_1[1] , 
        \un1_BIN_to_BCD_1_1[0] , \un1_BIN_to_BCD_0_1[1] , 
        \un1_BIN_to_BCD_1_1[1] , \un1_BIN_to_BCD_0[1] , 
        \un1_BIN_to_BCD_0_1[0] , \un1_BIN_to_BCD_1[2] , 
        \un1_BIN_to_BCD_0_1[2] , \un1_BIN_to_BCD_1_1[2] , 
        \un1_BIN_to_BCD_0[2] , \un1_BIN_to_BCD_0[3] , 
        \un1_BIN_to_BCD_1_1[3] , \un1_BIN_to_BCD_1[3] , 
        \un1_BIN_to_BCD_0_1[3] , Q_NSlde_i_o2tt_m1_0_a2, 
        \dymamic_led_0.HC4511_0.N_21_i_0 , Red1_c_i, \timer_EW.Ld_i , 
        \timer_NS_0.N_16 , \timer_EW.N_60 , GND_0, VCC_0;
    
    BIN_to_BCD_BIN_to_BCD_0 BIN_to_BCD_0 (.un1_BIN_to_BCD_0({
        \un1_BIN_to_BCD_0[3] , \un1_BIN_to_BCD_0[2] , 
        \un1_BIN_to_BCD_0[1] }), .un1_BIN_to_BCD_0_1({
        \un1_BIN_to_BCD_0_1[3] , \un1_BIN_to_BCD_0_1[2] , 
        \un1_BIN_to_BCD_0_1[1] , \un1_BIN_to_BCD_0_1[0] }), .Q_NS_0({
        \Q_NS_0[7] , \Q_NS_0[6] , \Q_NS_0[5] , \Q_NS_0[4] , 
        \Q_NS_0[3] , \Q_NS_0[2] , \Q_NS_0[1] }));
    CLKBUF Clk_pad (.PAD(Clk), .Y(Clk_c));
    OUTBUF \Sl_pad[0]  (.D(\dymamic_led_0.Disp_dat6 ), .PAD(Sl[0]));
    OUTBUF \Seg_pad[5]  (.D(\Seg_c[5] ), .PAD(Seg[5]));
    OUTBUF Yellow2_pad (.D(\timer_EW.State_i_0[3] ), .PAD(Yellow2));
    GND GND_i_0 (.Y(GND_0));
    one_seond_clk one_seond_clk_0 (.Clk_c(Clk_c), 
        .one_seond_clk_0_Cout(one_seond_clk_0_Cout), .Reset_c(Reset_c));
    trattic_control trattic_control_0 (.State_i_0({
        \timer_EW.State_i_0[3] }), .current_state({
        \trattic_control_0.current_state[0] }), .Reset_c(Reset_c), 
        .Clk_c(Clk_c), .timer_EW_Done_NS(timer_EW_Done_NS), .Yellow1_c(
        Yellow1_c), .Red1_c_i(Red1_c_i), .Ld_i_0(\timer_NS_0.Ld_i ), 
        .Green1_c(Green1_c), .timer_NS_0_Done_NS(timer_NS_0_Done_NS), 
        .Ld_i(\timer_EW.Ld_i ), .Red1_c(Red1_c), .Green2_c(Green2_c));
    OUTBUF \Sl_pad[1]  (.D(\dymamic_led_0.Disp_dat7 ), .PAD(Sl[1]));
    OUTBUF \Seg_pad[2]  (.D(\dymamic_led_0.HC4511_0.N_6 ), .PAD(Seg[2])
        );
    VCC VCC_i (.Y(VCC));
    OUTBUF \Seg_pad[4]  (.D(\Seg_c[4] ), .PAD(Seg[4]));
    OUTBUF \Seg_pad[3]  (.D(\dymamic_led_0.HC4511_0.N_21_i_0 ), .PAD(
        Seg[3]));
    BIN_to_BCD_BIN_to_BCD_0_1 BIN_to_BCD_1 (.un1_BIN_to_BCD_1({
        \un1_BIN_to_BCD_1[3] , \un1_BIN_to_BCD_1[2] , 
        \un1_BIN_to_BCD_1[1] }), .un1_BIN_to_BCD_1_1({
        \un1_BIN_to_BCD_1_1[3] , \un1_BIN_to_BCD_1_1[2] , 
        \un1_BIN_to_BCD_1_1[1] , \un1_BIN_to_BCD_1_1[0] }), .Q_NS({
        \Q_NS[7] , \Q_NS[6] , \Q_NS[5] , \Q_NS[4] , \Q_NS[3] , 
        \Q_NS[2] , \Q_NS[1] }));
    OUTBUF \Seg_pad[6]  (.D(\Seg_c[6] ), .PAD(Seg[6]));
    OUTBUF Green2_pad (.D(Green2_c), .PAD(Green2));
    dymamic_led dymamic_led_0 (.SM_8S_1_i_0({\SM_8S_1_i_0[1] }), 
        .SM_8S_1_i_0_a3_0({\SM_8S_1_i_0_a3_0[0] }), .Seg_c({\Seg_c[6] , 
        \Seg_c[5] , \Seg_c[4] }), .Q_NS({\Q_NS[0] }), .Q_NS_0({
        \Q_NS_0[0] }), .un1_BIN_to_BCD_1_1({\un1_BIN_to_BCD_1_1[3] , 
        \un1_BIN_to_BCD_1_1[2] , \un1_BIN_to_BCD_1_1[1] , 
        \un1_BIN_to_BCD_1_1[0] }), .un1_BIN_to_BCD_0_1({
        \un1_BIN_to_BCD_0_1[3] , \un1_BIN_to_BCD_0_1[2] , 
        \un1_BIN_to_BCD_0_1[1] , \un1_BIN_to_BCD_0_1[0] }), 
        .un1_BIN_to_BCD_1({\un1_BIN_to_BCD_1[3] , 
        \un1_BIN_to_BCD_1[2] , \un1_BIN_to_BCD_1[1] }), 
        .un1_BIN_to_BCD_0({\un1_BIN_to_BCD_0[3] , 
        \un1_BIN_to_BCD_0[2] , \un1_BIN_to_BCD_0[1] }), .N_6(
        \dymamic_led_0.HC4511_0.N_6 ), .N_21_i_0(
        \dymamic_led_0.HC4511_0.N_21_i_0 ), .Reset_c(Reset_c), .Clk_c(
        Clk_c), .Disp_dat8(\dymamic_led_0.Disp_dat8 ), .Disp_dat7(
        \dymamic_led_0.Disp_dat7 ), .Disp_dat6(
        \dymamic_led_0.Disp_dat6 ), .Disp_dat9(
        \dymamic_led_0.Disp_dat9 ));
    GND GND_i (.Y(GND));
    OUTBUF Yellow1_pad (.D(Yellow1_c), .PAD(Yellow1));
    INBUF Reset_pad (.PAD(Reset), .Y(Reset_c));
    OUTBUF Red1_pad (.D(Red1_c), .PAD(Red1));
    VCC VCC_i_0 (.Y(VCC_0));
    timer_NS timer_NS_0 (.current_state({
        \trattic_control_0.current_state[0] }), .Q_NS_0({\Q_NS_0[7] , 
        \Q_NS_0[6] , \Q_NS_0[5] , \Q_NS_0[4] , \Q_NS_0[3] , 
        \Q_NS_0[2] , \Q_NS_0[1] , \Q_NS_0[0] }), .Clk_c(Clk_c), 
        .Red1_c(Red1_c), .Yellow1_c(Yellow1_c), 
        .Q_NSlde_i_o2tt_m1_0_a2(Q_NSlde_i_o2tt_m1_0_a2), .N_60_0(
        \timer_EW.N_60 ), .Ld_i(\timer_NS_0.Ld_i ), .Reset_c(Reset_c), 
        .timer_NS_0_Done_NS(timer_NS_0_Done_NS), .one_seond_clk_0_Cout(
        one_seond_clk_0_Cout), .N_16(\timer_NS_0.N_16 ));
    OUTBUF \Sl_pad[3]  (.D(\dymamic_led_0.Disp_dat9 ), .PAD(Sl[3]));
    OUTBUF \Sl_pad[2]  (.D(\dymamic_led_0.Disp_dat8 ), .PAD(Sl[2]));
    timer_EW timer_EW (.current_state({
        \trattic_control_0.current_state[0] }), .Q_NS({\Q_NS[7] , 
        \Q_NS[6] , \Q_NS[5] , \Q_NS[4] , \Q_NS[3] , \Q_NS[2] , 
        \Q_NS[1] , \Q_NS[0] }), .Clk_c(Clk_c), .timer_EW_Done_NS(
        timer_EW_Done_NS), .Red1_c(Red1_c), .Q_NSlde_i_o2tt_m1_0_a2(
        Q_NSlde_i_o2tt_m1_0_a2), .one_seond_clk_0_Cout(
        one_seond_clk_0_Cout), .Reset_c(Reset_c), .Ld_i(
        \timer_EW.Ld_i ), .Green2_c(Green2_c), .N_16(\timer_NS_0.N_16 )
        , .N_60(\timer_EW.N_60 ));
    OUTBUF \Seg_pad[1]  (.D(\SM_8S_1_i_0[1] ), .PAD(Seg[1]));
    OUTBUF Red2_pad (.D(Red1_c_i), .PAD(Red2));
    OUTBUF \Seg_pad[7]  (.D(GND), .PAD(Seg[7]));
    OUTBUF \Seg_pad[0]  (.D(\SM_8S_1_i_0_a3_0[0] ), .PAD(Seg[0]));
    OUTBUF Green1_pad (.D(Green1_c), .PAD(Green1));
    
endmodule