data/full_repos/permissive/143278/ivltests/pr1828642.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1828642.v:17: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                         : ... In instance generate_memory\n    Byte[0].Data[i] = i*16 + 1;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1828642.v:18: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                         : ... In instance generate_memory\n    Byte[1].Data[i] = i*16 + 2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1828642.v:19: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                         : ... In instance generate_memory\n    Byte[2].Data[i] = i*16 + 3;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1828642.v:20: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                         : ... In instance generate_memory\n    Byte[3].Data[i] = i*16 + 4;\n                    ^\n%Error: Exiting due to 4 warning(s)\n'
module generate_memory();

generate
  genvar	b;

  for (b = 0; b < 4; b = b + 1) begin: Byte
    reg [7:0] Data[0:3];
  end
endgenerate

integer		i;

initial begin
  for (i = 0; i < 4; i = i + 1) begin
    Byte[0].Data[i] = i*16 + 1;
    Byte[1].Data[i] = i*16 + 2;
    Byte[2].Data[i] = i*16 + 3;
    Byte[3].Data[i] = i*16 + 4;
  end
  for (i = 0; i < 4; i = i + 1) begin
    $display("%h", Byte[0].Data[i]);
    $display("%h", Byte[1].Data[i]);
    $display("%h", Byte[2].Data[i]);
    $display("%h", Byte[3].Data[i]);
  end
end

endmodule
module generate_memory();


generate
  genvar	b;

  for (b = 0; b < 4; b = b + 1) begin: Byte
    reg [7:0] Data[0:3];
  end
endgenerate

integer		i;

initial begin
  for (i = 0; i < 4; i = i + 1) begin
    Byte[0].Data[i] = i*16 + 1;
    Byte[1].Data[i] = i*16 + 2;
    Byte[2].Data[i] = i*16 + 3;
    Byte[3].Data[i] = i*16 + 4;
  end
  for (i = 0; i < 4; i = i + 1) begin
    $display("%h", Byte[0].Data[i]);
    $display("%h", Byte[1].Data[i]);
    $display("%h", Byte[2].Data[i]);
    $display("%h", Byte[3].Data[i]);
  end
end

endmodule