data/full_repos/permissive/135475029/lab_9/src/RegisterFile.v
1: b'%Error: data/full_repos/permissive/135475029/lab_9/src/RegisterFile.v:39: Cannot find file containing module: \'reg_half\'\n  reg_half i_portA  (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135475029/lab_9/src,data/full_repos/permissive/135475029/reg_half\n             data/full_repos/permissive/135475029/lab_9/src,data/full_repos/permissive/135475029/reg_half.v\n             data/full_repos/permissive/135475029/lab_9/src,data/full_repos/permissive/135475029/reg_half.sv\n             reg_half\n             reg_half.v\n             reg_half.sv\n             obj_dir/reg_half\n             obj_dir/reg_half.v\n             obj_dir/reg_half.sv\n%Error: data/full_repos/permissive/135475029/lab_9/src/RegisterFile.v:47: Cannot find file containing module: \'reg_half\'\n reg_half i_portB (\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/135475029/lab_9/src/RegisterFile.v:59: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                : ... In instance RegisterFile\n    assign RD1 = (A1 != 4\'b0000) ? Read1 : 0;  \n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/135475029/lab_9/src/RegisterFile.v:60: Operator NEQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                : ... In instance RegisterFile\n   assign RD2 = (A2 != 4\'b0000) ? Read2 : 0;  \n                    ^~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module RegisterFile(
       input   [4:0] A1,
			 output [31:0] RD1,
			 input   [4:0] A2,
			 output [31:0] RD2,
			 input   [4:0] A3,
			 input  [31:0] WD3,
			 input         WE3,
			 input         CLK
    );


   wire [31:0] Read1;
	 wire [31:0] Read2;




	 reg_half i_portA	 (
	   .a(A3),
	   .d(WD3),
	   .dpra(A1),
	   .clk(CLK),
	   .we(WE3),
	   .dpo(Read1));

	reg_half i_portB (
	   .a(A3),
	   .d(WD3),
	   .dpra(A2),
	   .clk(CLK),
	   .we(WE3),
	   .dpo(Read2));





    assign RD1 = (A1 != 4'b0000) ? Read1 : 0;
	  assign RD2 = (A2 != 4'b0000) ? Read2 : 0;

endmodule
module RegisterFile(
       input   [4:0] A1,
			 output [31:0] RD1,
			 input   [4:0] A2,
			 output [31:0] RD2,
			 input   [4:0] A3,
			 input  [31:0] WD3,
			 input         WE3,
			 input         CLK
    );



   wire [31:0] Read1;
	 wire [31:0] Read2;




	 reg_half i_portA	 (
	   .a(A3),
	   .d(WD3),
	   .dpra(A1),
	   .clk(CLK),
	   .we(WE3),
	   .dpo(Read1));

	reg_half i_portB (
	   .a(A3),
	   .d(WD3),
	   .dpra(A2),
	   .clk(CLK),
	   .we(WE3),
	   .dpo(Read2));





    assign RD1 = (A1 != 4'b0000) ? Read1 : 0;
	  assign RD2 = (A2 != 4'b0000) ? Read2 : 0;

endmodule