data/full_repos/permissive/137633637/jingzhe.srcs/sources_1/new/CounterModTen.v
data/verilator_xmls/f253c7dd-6716-4cfb-a50e-94433d361575.xml
module CounterModTen(clk,rst,start,q);

input clk;
input rst;
input start;
output reg [3:0] q;
always @(posedge clk or posedge rst)
begin
    if (rst)
        q <= 4'b0000;
    else if(start)
    begin
        if(q==4'b1001)
            q <=4'b0000;
        else
            q<=q+4'b0001;
    end
end
endmodule
module CounterModTen(clk,rst,start,q);


input clk;
input rst;
input start;
output reg [3:0] q;
always @(posedge clk or posedge rst)
begin
    if (rst)
        q <= 4'b0000;
    else if(start)
    begin
        if(q==4'b1001)
            q <=4'b0000;
        else
            q<=q+4'b0001;
    end
end
endmodule