data/full_repos/permissive/162646941/src/counter_ex2.v
data/verilator_xmls/5e7bee82-481d-4831-88c0-efd5d72a2576.xml
module counter_ex2(clk,clr,q);

	input clk,clr; 
	output reg [15:0] q = 16'h0000;

	always @ (posedge clk)
	begin
		if(clr)
			q <= 16'h0000;
		else begin
			q <= q + 1;
			if(q==999) begin
				q <= 16'h0000;

			end
		end
	end

endmodule
module counter_ex2(clk,clr,q);


	input clk,clr; 
	output reg [15:0] q = 16'h0000;

	always @ (posedge clk)
	begin
		if(clr)
			q <= 16'h0000;
		else begin
			q <= q + 1;
			if(q==999) begin
				q <= 16'h0000;

			end
		end
	end

endmodule