data/full_repos/permissive/123304708/src/datapath/alu.v
None: at end of input
1: b'%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:1: Cannot find include file: ././define/ctrl_def.v\n`include "././define/ctrl_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123304708/src/datapath,data/full_repos/permissive/123304708/././define/ctrl_def.v\n             data/full_repos/permissive/123304708/src/datapath,data/full_repos/permissive/123304708/././define/ctrl_def.v.v\n             data/full_repos/permissive/123304708/src/datapath,data/full_repos/permissive/123304708/././define/ctrl_def.v.sv\n             ././define/ctrl_def.v\n             ././define/ctrl_def.v.v\n             ././define/ctrl_def.v.sv\n             obj_dir/././define/ctrl_def.v\n             obj_dir/././define/ctrl_def.v.v\n             obj_dir/././define/ctrl_def.v.sv\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:16: Define or directive not defined: \'`ALUOP_ADD\'\n      `ALUOP_ADD:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:16: syntax error, unexpected \':\', expecting endcase\n      `ALUOP_ADD:\n                ^\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:18: Define or directive not defined: \'`ALUOP_SUB\'\n      `ALUOP_SUB:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:20: Define or directive not defined: \'`ALUOP_SLL\'\n      `ALUOP_SLL:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:22: Define or directive not defined: \'`ALUOP_SRL\'\n      `ALUOP_SRL:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:24: Define or directive not defined: \'`ALUOP_SRA\'\n      `ALUOP_SRA:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:26: Define or directive not defined: \'`ALUOP_AND\'\n      `ALUOP_AND:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:28: Define or directive not defined: \'`ALUOP_OR\'\n      `ALUOP_OR:\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:30: Define or directive not defined: \'`ALUOP_XOR\'\n      `ALUOP_XOR:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:32: Define or directive not defined: \'`ALUOP_NOR\'\n      `ALUOP_NOR:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:34: Define or directive not defined: \'`ALUOP_SLT\'\n      `ALUOP_SLT:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:36: Define or directive not defined: \'`ALUOP_SLTU\'\n      `ALUOP_SLTU:\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:38: Define or directive not defined: \'`ALUOP_LUI\'\n      `ALUOP_LUI:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:40: Define or directive not defined: \'`ALUOP_BNE\'\n      `ALUOP_BNE:\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:42: Define or directive not defined: \'`ALUOP_BLEZ\'\n      `ALUOP_BLEZ:\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:44: Define or directive not defined: \'`ALUOP_BGTZ\'\n      `ALUOP_BGTZ:\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:46: Define or directive not defined: \'`ALUOP_BLTZ\'\n      `ALUOP_BLTZ:\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/123304708/src/datapath/alu.v:48: Define or directive not defined: \'`ALUOP_BGEZ\'\n      `ALUOP_BGEZ:\n      ^~~~~~~~~~~\n%Error: Cannot continue\n'
module alu(
  input [31:0] A,
  input [31:0] B,
  input [4:0] ALUOp,
  output reg[31:0] result 
  );
  
  integer dif;
  initial  dif = A - B;
  
  always@(*)
  begin
    case(ALUOp)
      `ALUOP_ADD:
        result = A + B;
      `ALUOP_SUB:
        result = A - B;
      `ALUOP_SLL:
        result = B << A[4:0];
      `ALUOP_SRL:
        result = B >> A[4:0];
      `ALUOP_SRA:
        result = B >> A[4:0] | ( {32{B[31]}} << (6'b100000-{1'b0, A[4:0]}));
      `ALUOP_AND:
        result = A & B;
      `ALUOP_OR:
        result = A | B;
      `ALUOP_XOR:
        result = A ^ B;
      `ALUOP_NOR:
        result = ~ (A | B);
      `ALUOP_SLT:
        result = ((A[31] && !B[31]) || ((!(A[31] ^ B[31])) && dif[31]))? 32'h1 : 32'h0;
      `ALUOP_SLTU:
        result = (A < B)? 32'b1 : 32'b0;
      `ALUOP_LUI:
        result = {B[15:0],16'b0};
      `ALUOP_BNE:
        result = (A == B)? 32'b1 : 32'b0;
      `ALUOP_BLEZ:
        result = (!A[31] && A!=32'b0)? 32'b1: 32'b0;
      `ALUOP_BGTZ:
        result = (!A[31] && A!=32'b0)? 32'b0: 32'b1;
      `ALUOP_BLTZ:
        result = (A[31])? 32'b0 : 32'b1;
      `ALUOP_BGEZ:
        result = (!A[31])? 32'b0 : 32'b1;      
      default: result = 32'b0;
    endcase
  end
  
endmodule
module alu(
  input [31:0] A,
  input [31:0] B,
  input [4:0] ALUOp,
  output reg[31:0] result 
  );

  
  integer dif;
  initial  dif = A - B;
  
  always@(*)
  begin
    case(ALUOp)
      `ALUOP_ADD:
        result = A + B;
      `ALUOP_SUB:
        result = A - B;
      `ALUOP_SLL:
        result = B << A[4:0];
      `ALUOP_SRL:
        result = B >> A[4:0];
      `ALUOP_SRA:
        result = B >> A[4:0] | ( {32{B[31]}} << (6'b100000-{1'b0, A[4:0]}));
      `ALUOP_AND:
        result = A & B;
      `ALUOP_OR:
        result = A | B;
      `ALUOP_XOR:
        result = A ^ B;
      `ALUOP_NOR:
        result = ~ (A | B);
      `ALUOP_SLT:
        result = ((A[31] && !B[31]) || ((!(A[31] ^ B[31])) && dif[31]))? 32'h1 : 32'h0;
      `ALUOP_SLTU:
        result = (A < B)? 32'b1 : 32'b0;
      `ALUOP_LUI:
        result = {B[15:0],16'b0};
      `ALUOP_BNE:
        result = (A == B)? 32'b1 : 32'b0;
      `ALUOP_BLEZ:
        result = (!A[31] && A!=32'b0)? 32'b1: 32'b0;
      `ALUOP_BGTZ:
        result = (!A[31] && A!=32'b0)? 32'b0: 32'b1;
      `ALUOP_BLTZ:
        result = (A[31])? 32'b0 : 32'b1;
      `ALUOP_BGEZ:
        result = (!A[31])? 32'b0 : 32'b1;      
      default: result = 32'b0;
    endcase
  end
  
endmodule