data/full_repos/permissive/135077285/mux32Bits3.v
data/verilator_xmls/3fe5e922-3f03-4faf-9639-743834646e49.xml
module mux32Bits3 (
  input wire [31:0] entrada1,
  input wire [31:0] entrada2,
  input wire [31:0] entrada3,
  input wire [1:0] seletor,
  output reg [31:0] saida
);

  always @(*) begin
    case (seletor)
      2'b00 : saida <= entrada1;
      2'b01 : saida <= entrada2;
      2'b10 : saida <= entrada3;
    endcase
  end

endmodule
module mux32Bits3 (
  input wire [31:0] entrada1,
  input wire [31:0] entrada2,
  input wire [31:0] entrada3,
  input wire [1:0] seletor,
  output reg [31:0] saida
);


  always @(*) begin
    case (seletor)
      2'b00 : saida <= entrada1;
      2'b01 : saida <= entrada2;
      2'b10 : saida <= entrada3;
    endcase
  end

endmodule