data/full_repos/permissive/186491764/ALU.v
data/verilator_xmls/045ef446-b7ff-4805-bc7a-c88c5706a2c3.xml
module ALU( input  [7:0] a, 
 input  [7:0] b,  
 input  [1:0] select, 
 
 output reg [7:0] Operation,  
 output zero
    );
always @(*)
begin 
 case(select)
 2'b00: Operation = a + b; 
 2'b01: Operation = a - b; 
 2'b10: Operation = ~a;
 
 default:Operation = a + b;
 endcase
end
assign zero = (Operation==8'd0) ? 1'b1: 1'b0;

endmodule
module ALU( input  [7:0] a, 
 input  [7:0] b,  
 input  [1:0] select, 
 
 output reg [7:0] Operation,  
 output zero
    );

always @(*)
begin 
 case(select)
 2'b00: Operation = a + b; 
 2'b01: Operation = a - b; 
 2'b10: Operation = ~a;
 
 default:Operation = a + b;
 endcase
end
assign zero = (Operation==8'd0) ? 1'b1: 1'b0;

endmodule