data/full_repos/permissive/167274925/ALUControl.v
 line:73: before: "M_AXI_AWPROT"
1: b'%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case expression, but Case expression\'s VARREF \'Function\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h20\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h21\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h18\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h19\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h22\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h24\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h25\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h2a\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h27\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h26\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h4\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h11\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h13\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h10\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h12\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h6\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h3\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h7\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h0\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'h2\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'hb\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/167274925/ALUControl.v:33: Operator CASE expects 9 bits on the Case Item, but Case Item\'s CONST \'6\'ha\' generates 6 bits.\n                                                                    : ... In instance ALUControl\n    case(Function)\n    ^~~~\n%Error: Exiting due to 23 warning(s)\n'
module ALUControl(ALUop,R,RV,Function,ALUCtrl,SLLsrc);
input [3:0] ALUop;
input [5:0] Function;
input R,RV;
output reg [5:0]ALUCtrl;
output reg SLLsrc;
  always@*begin 
    SLLsrc<=0;
  if(ALUop==4'b0000)begin

    ALUCtrl<=6'b00010;
    end 
   else if (ALUop==4'b0001)begin
      ALUCtrl<=6'd6;
    end 
   else if(ALUop==4'b1010)begin
    ALUCtrl<=6'd33; 
   end 
   else if (ALUop==4'b1011)begin
    ALUCtrl<=6'd34; 
   end 
   else if ( ALUop==4'b1101)begin
    ALUCtrl<=6'd35; 
   end 
   else if ( ALUop==4'b1111)begin
      ALUCtrl<=6'd36; 
     end 
   else if (ALUop==4'b0010)begin
    case(Function)
     6'b100000:    ALUCtrl<=6'd2;
     6'b100001:    ALUCtrl<=6'd2;
     6'b011000:    ALUCtrl<=6'd4;
     6'b011001:    ALUCtrl<=6'd24;
     6'b100010:    ALUCtrl<=6'd6;
     6'b100100:    ALUCtrl<=6'd0;
     6'b100101:    ALUCtrl<=6'd1;
     6'b101010:    ALUCtrl<=6'd7;
     9'b101011:    ALUCtrl<=6'd19;
     6'b100111:    ALUCtrl<=6'd12;
     6'b100110:    ALUCtrl<=6'd3;
     6'b000100:    ALUCtrl<=6'd5;
     6'b010001:    ALUCtrl<=6'd30;
     6'b010011:    ALUCtrl<=6'd29;
     6'b010000:    ALUCtrl<=6'd31;
     6'b010010:    ALUCtrl<=6'd23;
     6'b000110:  begin 
      if(RV=='b0)begin 
       ALUCtrl<=6'd9;
        end 
      else if(RV=='b1)begin
       ALUCtrl<=6'd20;
      end 
       end 
     6'b000011:   begin 
         ALUCtrl<=6'd13;
         SLLsrc<=1;
      end 
     6'b000111: ALUCtrl<=6'd13;
     6'b000000: begin 
         ALUCtrl<=6'd10;
         SLLsrc<=1;
         end  
     6'b000010: begin 
         if(R==1'b0)begin
         ALUCtrl<=6'd11;
         end 
         else if(R==1'b1)begin
         ALUCtrl<=6'd21;
         end 
         SLLsrc<=1;
         end  
      6'b001011: ALUCtrl<=6'd14;
      6'b001010: ALUCtrl<=6'd15;
    endcase 
   end 
     else if(ALUop==4'b0011)begin
        ALUCtrl<=6'd27;
      end   
    else if(ALUop==4'b0100)begin
              ALUCtrl<=6'd22;
            end 
    else if(ALUop==4'b0101)begin
            ALUCtrl<=6'd28;
        end 
    else if(ALUop==4'b0110)begin
            ALUCtrl<=6'd7;
    end 
    else if(ALUop==4'b1110)begin
                ALUCtrl<=6'd19;
        end 
    else if(ALUop==4'b0111)begin
                ALUCtrl<=6'd18;
                SLLsrc<=1;
        end
     else if(ALUop==4'b1000)begin
     if(Function==6'b000010)begin
          ALUCtrl<=6'd8;
         end 
         else if(Function==6'b000000)begin
            ALUCtrl<=6'd16;
           end 
         else if(Function==6'b000100)begin
              ALUCtrl<=6'd17;
                end  
     end   
    if(ALUop==4'b1001)begin 
       ALUCtrl<=6'd32;
    end  
   end 
endmodule
module ALUControl(ALUop,R,RV,Function,ALUCtrl,SLLsrc);

input [3:0] ALUop;
input [5:0] Function;
input R,RV;
output reg [5:0]ALUCtrl;
output reg SLLsrc;
  always@*begin 
    SLLsrc<=0;
  if(ALUop==4'b0000)begin

    ALUCtrl<=6'b00010;
    end 
   else if (ALUop==4'b0001)begin
      ALUCtrl<=6'd6;
    end 
   else if(ALUop==4'b1010)begin
    ALUCtrl<=6'd33; 
   end 
   else if (ALUop==4'b1011)begin
    ALUCtrl<=6'd34; 
   end 
   else if ( ALUop==4'b1101)begin
    ALUCtrl<=6'd35; 
   end 
   else if ( ALUop==4'b1111)begin
      ALUCtrl<=6'd36; 
     end 
   else if (ALUop==4'b0010)begin
    case(Function)
     6'b100000:    ALUCtrl<=6'd2;
     6'b100001:    ALUCtrl<=6'd2;
     6'b011000:    ALUCtrl<=6'd4;
     6'b011001:    ALUCtrl<=6'd24;
     6'b100010:    ALUCtrl<=6'd6;
     6'b100100:    ALUCtrl<=6'd0;
     6'b100101:    ALUCtrl<=6'd1;
     6'b101010:    ALUCtrl<=6'd7;
     9'b101011:    ALUCtrl<=6'd19;
     6'b100111:    ALUCtrl<=6'd12;
     6'b100110:    ALUCtrl<=6'd3;
     6'b000100:    ALUCtrl<=6'd5;
     6'b010001:    ALUCtrl<=6'd30;
     6'b010011:    ALUCtrl<=6'd29;
     6'b010000:    ALUCtrl<=6'd31;
     6'b010010:    ALUCtrl<=6'd23;
     6'b000110:  begin 
      if(RV=='b0)begin 
       ALUCtrl<=6'd9;
        end 
      else if(RV=='b1)begin
       ALUCtrl<=6'd20;
      end 
       end 
     6'b000011:   begin 
         ALUCtrl<=6'd13;
         SLLsrc<=1;
      end 
     6'b000111: ALUCtrl<=6'd13;
     6'b000000: begin 
         ALUCtrl<=6'd10;
         SLLsrc<=1;
         end  
     6'b000010: begin 
         if(R==1'b0)begin
         ALUCtrl<=6'd11;
         end 
         else if(R==1'b1)begin
         ALUCtrl<=6'd21;
         end 
         SLLsrc<=1;
         end  
      6'b001011: ALUCtrl<=6'd14;
      6'b001010: ALUCtrl<=6'd15;
    endcase 
   end 
     else if(ALUop==4'b0011)begin
        ALUCtrl<=6'd27;
      end   
    else if(ALUop==4'b0100)begin
              ALUCtrl<=6'd22;
            end 
    else if(ALUop==4'b0101)begin
            ALUCtrl<=6'd28;
        end 
    else if(ALUop==4'b0110)begin
            ALUCtrl<=6'd7;
    end 
    else if(ALUop==4'b1110)begin
                ALUCtrl<=6'd19;
        end 
    else if(ALUop==4'b0111)begin
                ALUCtrl<=6'd18;
                SLLsrc<=1;
        end
     else if(ALUop==4'b1000)begin
     if(Function==6'b000010)begin
          ALUCtrl<=6'd8;
         end 
         else if(Function==6'b000000)begin
            ALUCtrl<=6'd16;
           end 
         else if(Function==6'b000100)begin
              ALUCtrl<=6'd17;
                end  
     end   
    if(ALUop==4'b1001)begin 
       ALUCtrl<=6'd32;
    end  
   end 
endmodule