data/full_repos/permissive/201488448/1_verilog/21_shift.v
1: b"%Error: data/full_repos/permissive/201488448/1_verilog/21_shift.v:11: Cannot find file containing module: 'my_dff'\n my_dff d1 ( clk, d, a );\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/my_dff\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/my_dff.v\n             data/full_repos/permissive/201488448/1_verilog,data/full_repos/permissive/201488448/my_dff.sv\n             my_dff\n             my_dff.v\n             my_dff.sv\n             obj_dir/my_dff\n             obj_dir/my_dff.v\n             obj_dir/my_dff.sv\n%Error: data/full_repos/permissive/201488448/1_verilog/21_shift.v:12: Cannot find file containing module: 'my_dff'\n my_dff d2 ( clk, a, b );\n ^~~~~~\n%Error: data/full_repos/permissive/201488448/1_verilog/21_shift.v:13: Cannot find file containing module: 'my_dff'\n my_dff d3 ( clk, b, q );\n ^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_module (
	input clk,
	input d,
	output q
);

	wire a, b;



	my_dff d1 ( clk, d, a );
	my_dff d2 ( clk, a, b );
	my_dff d3 ( clk, b, q );

endmodule
module top_module (
	input clk,
	input d,
	output q
);


	wire a, b;



	my_dff d1 ( clk, d, a );
	my_dff d2 ( clk, a, b );
	my_dff d3 ( clk, b, q );

endmodule