data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/testvga.sv
1: b"%Error: data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/testvga.sv:22: Cannot find file containing module: 'vga40x30x2'\nvga40x30x2 vga(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl,data/full_repos/permissive/169639758/vga40x30x2\n             data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl,data/full_repos/permissive/169639758/vga40x30x2.v\n             data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl,data/full_repos/permissive/169639758/vga40x30x2.sv\n             vga40x30x2\n             vga40x30x2.v\n             vga40x30x2.sv\n             obj_dir/vga40x30x2\n             obj_dir/vga40x30x2.v\n             obj_dir/vga40x30x2.sv\n%Error: Exiting due to 1 error(s)\n"
module testbench(
        input clk,
	output [3:0]vga_red,
	output [3:0]vga_grn,
	output [3:0]vga_blu,
	output vga_hsync,
	output vga_vsync,
	output vga_frame
        );

wire [1:0]red;
wire [1:0]grn;
wire [1:0]blu;

vga40x30x2 vga(
	.clk25m(clk),
	.red(red),
	.grn(grn),
	.blu(blu),
	.hs(vga_hsync),
	.vs(vga_vsync),
	.fr(vga_frame),
	.vram_waddr(11'b0),
	.vram_wdata(8'b0),
	.vram_we(1'b0),
	.vram_clk(clk)
	);

assign vga_red = { red, red[0], red[0] };
assign vga_grn = { grn, grn[0], grn[0] };
assign vga_blu = { blu, blu[0], blu[0] };

endmodule
module testbench(
        input clk,
	output [3:0]vga_red,
	output [3:0]vga_grn,
	output [3:0]vga_blu,
	output vga_hsync,
	output vga_vsync,
	output vga_frame
        );


wire [1:0]red;
wire [1:0]grn;
wire [1:0]blu;

vga40x30x2 vga(
	.clk25m(clk),
	.red(red),
	.grn(grn),
	.blu(blu),
	.hs(vga_hsync),
	.vs(vga_vsync),
	.fr(vga_frame),
	.vram_waddr(11'b0),
	.vram_wdata(8'b0),
	.vram_we(1'b0),
	.vram_clk(clk)
	);

assign vga_red = { red, red[0], red[0] };
assign vga_grn = { grn, grn[0], grn[0] };
assign vga_blu = { blu, blu[0], blu[0] };

endmodule