data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #500000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #500000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #500000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #500000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #500000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:115: Unsupported: Ignoring delay on this delayed statement.\n        #500000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #500000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:127: Unsupported: Ignoring delay on this delayed statement.\n        #500000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:137: Unsupported: Ignoring delay on this delayed statement.\n        #1 clock_Main_reg = ~clock_Main_reg;\n        ^\n%Error: data/full_repos/permissive/105948944/simulations/H_Bridge_v2_testBench.v:52: Cannot find file containing module: \'H_Bridge_v2\'\n    H_Bridge_v2 H1(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/H_Bridge_v2\n             data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/H_Bridge_v2.v\n             data/full_repos/permissive/105948944/simulations,data/full_repos/permissive/105948944/H_Bridge_v2.sv\n             H_Bridge_v2\n             H_Bridge_v2.v\n             H_Bridge_v2.sv\n             obj_dir/H_Bridge_v2\n             obj_dir/H_Bridge_v2.v\n             obj_dir/H_Bridge_v2.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module H_Bridge_testBench(
    );
    reg clock_Main_reg; 
    reg [3:0]movingDirection_reg;  
    reg [5:0]motorSpeed_reg, currentSensing_reg;        
    wire enA_wire, enB_wire, in1_wire, in2_wire, in3_wire, in4_wire;






    
    parameter INTERTIAL_STOP  =   4'b0000;
    parameter HARD_STOP    =      4'b1111;
    parameter FORWARD =           4'b0110;
    parameter REVERSE   =         4'b1001;
    parameter TURN_RIGHT  =       4'b0101;
    parameter TURN_LEFT    =      4'b1010;
        


    
    H_Bridge_v2 H1(
    .clock(clock_Main_reg),
    .movingDirection(movingDirection_reg),
    .motorSpeed(motorSpeed_reg),
    .currentSensing(currentSensing_reg),
    .enA(enA_wire), 
    .enB(enB_wire),
    .in1(in1_wire),
    .in2(in2_wire),
    .in3(in3_wire),
    .in4(in4_wire)




    );
    
    initial
    begin
        clock_Main_reg <= 0;


        movingDirection_reg <= INTERTIAL_STOP;
        motorSpeed_reg[2:0] <= 3'b000;
        motorSpeed_reg[5:3] <= 3'b000; 
        currentSensing_reg <= 0;

        #10
        
        movingDirection_reg <= FORWARD;
        motorSpeed_reg[2:0] <= 3'b111;
        motorSpeed_reg[5:3] <= 3'b111; 
        currentSensing_reg <= 0;
        #500000
        
        movingDirection_reg <= REVERSE;
        motorSpeed_reg[2:0] <= 3'b110;
        motorSpeed_reg[5:3] <= 3'b110; 
        currentSensing_reg <= 0;
        #500000
        
        movingDirection_reg <= TURN_RIGHT;
        motorSpeed_reg[2:0] <= 3'b101;
        motorSpeed_reg[5:3] <= 3'b101; 
        currentSensing_reg <= 0;
        #500000
        
        movingDirection_reg <= TURN_LEFT;
        motorSpeed_reg[2:0] <= 3'b100;
        motorSpeed_reg[5:3] <= 3'b100; 
        currentSensing_reg <= 0;  
        #500000
        
        movingDirection_reg <= TURN_LEFT;
        motorSpeed_reg[2:0] <= 3'b111;
        motorSpeed_reg[5:3] <= 3'b111; 
        currentSensing_reg <= 1;
        #500000
        
        movingDirection_reg <= FORWARD;
        motorSpeed_reg[2:0] <= 3'b011;
        motorSpeed_reg[5:3] <= 3'b011; 
        currentSensing_reg <= 0;
        #500000
        
        movingDirection_reg <= FORWARD;
        motorSpeed_reg[2:0] <= 3'b110;
        motorSpeed_reg[5:3] <= 3'b110; 
        currentSensing_reg <= 0;
        #500000
        
        movingDirection_reg <= FORWARD;
        motorSpeed_reg[2:0] <= 3'b111;
        motorSpeed_reg[5:3] <= 3'b111; 
        currentSensing_reg <= 0;
        #500000
        
        movingDirection_reg <= INTERTIAL_STOP;
        motorSpeed_reg[2:0] <= 3'b000;
        motorSpeed_reg[5:3] <= 3'b000; 
        currentSensing_reg <= 0;
    end

    
    always
        #1 clock_Main_reg = ~clock_Main_reg;
        
endmodule
module H_Bridge_testBench(
    );

    reg clock_Main_reg; 
    reg [3:0]movingDirection_reg;  
    reg [5:0]motorSpeed_reg, currentSensing_reg;        
    wire enA_wire, enB_wire, in1_wire, in2_wire, in3_wire, in4_wire;






    
    parameter INTERTIAL_STOP  =   4'b0000;
    parameter HARD_STOP    =      4'b1111;
    parameter FORWARD =           4'b0110;
    parameter REVERSE   =         4'b1001;
    parameter TURN_RIGHT  =       4'b0101;
    parameter TURN_LEFT    =      4'b1010;
        


    
    H_Bridge_v2 H1(
    .clock(clock_Main_reg),
    .movingDirection(movingDirection_reg),
    .motorSpeed(motorSpeed_reg),
    .currentSensing(currentSensing_reg),
    .enA(enA_wire), 
    .enB(enB_wire),
    .in1(in1_wire),
    .in2(in2_wire),
    .in3(in3_wire),
    .in4(in4_wire)




    );
    
    initial
    begin
        clock_Main_reg <= 0;


        movingDirection_reg <= INTERTIAL_STOP;
        motorSpeed_reg[2:0] <= 3'b000;
        motorSpeed_reg[5:3] <= 3'b000; 
        currentSensing_reg <= 0;

        #10
        
        movingDirection_reg <= FORWARD;
        motorSpeed_reg[2:0] <= 3'b111;
        motorSpeed_reg[5:3] <= 3'b111; 
        currentSensing_reg <= 0;
        #500000
        
        movingDirection_reg <= REVERSE;
        motorSpeed_reg[2:0] <= 3'b110;
        motorSpeed_reg[5:3] <= 3'b110; 
        currentSensing_reg <= 0;
        #500000
        
        movingDirection_reg <= TURN_RIGHT;
        motorSpeed_reg[2:0] <= 3'b101;
        motorSpeed_reg[5:3] <= 3'b101; 
        currentSensing_reg <= 0;
        #500000
        
        movingDirection_reg <= TURN_LEFT;
        motorSpeed_reg[2:0] <= 3'b100;
        motorSpeed_reg[5:3] <= 3'b100; 
        currentSensing_reg <= 0;  
        #500000
        
        movingDirection_reg <= TURN_LEFT;
        motorSpeed_reg[2:0] <= 3'b111;
        motorSpeed_reg[5:3] <= 3'b111; 
        currentSensing_reg <= 1;
        #500000
        
        movingDirection_reg <= FORWARD;
        motorSpeed_reg[2:0] <= 3'b011;
        motorSpeed_reg[5:3] <= 3'b011; 
        currentSensing_reg <= 0;
        #500000
        
        movingDirection_reg <= FORWARD;
        motorSpeed_reg[2:0] <= 3'b110;
        motorSpeed_reg[5:3] <= 3'b110; 
        currentSensing_reg <= 0;
        #500000
        
        movingDirection_reg <= FORWARD;
        motorSpeed_reg[2:0] <= 3'b111;
        motorSpeed_reg[5:3] <= 3'b111; 
        currentSensing_reg <= 0;
        #500000
        
        movingDirection_reg <= INTERTIAL_STOP;
        motorSpeed_reg[2:0] <= 3'b000;
        motorSpeed_reg[5:3] <= 3'b000; 
        currentSensing_reg <= 0;
    end

    
    always
        #1 clock_Main_reg = ~clock_Main_reg;
        
endmodule