data/full_repos/permissive/135852214/Verilog/tof.v
data/verilator_xmls/74d437f7-4ebe-4fb9-b819-875347390692.xml
module tof(
    input [2:0] in,
    output [2:0] out
    );
wire w;
assign w = in[0] & in[1];
assign out[0] = in[0];
assign out[1] = in[1];
assign out[2] = in[2] ^ w;


endmodule
module tof(
    input [2:0] in,
    output [2:0] out
    );

wire w;
assign w = in[0] & in[1];
assign out[0] = in[0];
assign out[1] = in[1];
assign out[2] = in[2] ^ w;


endmodule