data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/debouncer.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/debouncer.v:75: Multiple top level modules\n                                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                              : ... Top module \'key_debounce\'\nmodule key_debounce(  \n       ^~~~~~~~~~~~\n                                                                                                              : ... Top module \'switch_debounce\'\nmodule switch_debounce(     \n       ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/debouncer.v:155: Operator ASSIGNDLY expects 29 bits on the Assign RHS, but Assign RHS\'s CONST \'28\'h0\' generates 28 bits.\n                                                                                                            : ... In instance switch_debounce\n       count<=28\'d0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/debouncer.v:161: Operator ASSIGNDLY expects 29 bits on the Assign RHS, but Assign RHS\'s CONST \'28\'h0\' generates 28 bits.\n                                                                                                            : ... In instance switch_debounce\n        count<=28\'d0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/debouncer.v:158: Operator EQ expects 29 bits on the RHS, but RHS\'s CONST \'28\'h186a0\' generates 28 bits.\n                                                                                                            : ... In instance switch_debounce\n      if(count==28\'d100000)\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sources_1/new/debouncer.v:171: Operator ASSIGNDLY expects 29 bits on the Assign RHS, but Assign RHS\'s CONST \'28\'h0\' generates 28 bits.\n                                                                                                            : ... In instance switch_debounce\n       count<=28\'d0;\n            ^~\n%Error: Exiting due to 5 warning(s)\n'
module switch_debounce(     
    input CLK,
    input RSTn,
    input [15:0] sw_in,
    output reg [15:0] sw_out=0
    );
    reg [1:0]next_state;
    reg [15:0]sw_temp;
    reg time_20ms;
    reg is_count;
    reg [28:0] count;
    always @ ( posedge CLK or negedge RSTn )
	    if( !RSTn )
		    begin
			    sw_temp <= 16'b0000000000000000;
			    next_state <= 2'd0;
			    is_count     <= 1'b0;
			    sw_out <= 16'b0000000000000000;
		    end
	    else
		    begin
			    case(next_state) 
				    2'b00:
					    if(sw_in!=16'b0000000000000000)
						    begin
							    next_state<= 2'd1;
							    is_count<= 1'b1;
							    sw_temp<= sw_in;
						    end
						else
						    begin
							    next_state<= 2'd0;
							    sw_temp<= 16'b0000000000000000;
							    is_count<= 1'b0;
						    end
				    2'b01:
					    if(time_20ms==1'b1 )
					    	begin
							    is_count<= 1'b0;
							    next_state<= 2'd2;
					    	end
					    else
					    	begin
					    		sw_temp<= sw_in;
					    		if(sw_in!=sw_temp)
					    			begin
					    				is_count<=1'b0;
					    				next_state<= 2'd0;
					    			end
					    		else
								    begin
									    next_state<= 2'd1;
									    is_count<= 1'b1;
								    end
					    	end
				    2'b10:
					    if(sw_in!=sw_temp || sw_in==16'b0000000000000000)
						    begin
							    sw_out<= sw_temp;    
							    next_state<= 2'd3;
						    end
					    else
						    begin 
							    sw_out<= 16'b0000000000000000;
							    next_state<= 2'd2;
						    end
				    2'b11:
				    	begin
						    next_state<= 2'd0;
						    sw_out<= 16'b0000000000000000;
				    	end
				    default:
				    	next_state<= 2'd0;
			    endcase

			 end
	always @ ( posedge CLK or negedge RSTn )
		if(!RSTn)
		    begin
			    time_20ms<=1'b0;
			    count<=28'd0;
		    end
		else if(is_count==1'b1)
		    if(count==28'd100000)
			    begin
				    time_20ms<=1'b1;
				    count<=28'd0;
			    end
		    else
			    begin
				    time_20ms<=1'b0;
				    count<=count+1'd1;
			    end
		else
		    begin
			    time_20ms<=1'b0;
			    count<=28'd0;
	    	end
endmodule
module switch_debounce(     
    input CLK,
    input RSTn,
    input [15:0] sw_in,
    output reg [15:0] sw_out=0
    );

    reg [1:0]next_state;
    reg [15:0]sw_temp;
    reg time_20ms;
    reg is_count;
    reg [28:0] count;
    always @ ( posedge CLK or negedge RSTn )
	    if( !RSTn )
		    begin
			    sw_temp <= 16'b0000000000000000;
			    next_state <= 2'd0;
			    is_count     <= 1'b0;
			    sw_out <= 16'b0000000000000000;
		    end
	    else
		    begin
			    case(next_state) 
				    2'b00:
					    if(sw_in!=16'b0000000000000000)
						    begin
							    next_state<= 2'd1;
							    is_count<= 1'b1;
							    sw_temp<= sw_in;
						    end
						else
						    begin
							    next_state<= 2'd0;
							    sw_temp<= 16'b0000000000000000;
							    is_count<= 1'b0;
						    end
				    2'b01:
					    if(time_20ms==1'b1 )
					    	begin
							    is_count<= 1'b0;
							    next_state<= 2'd2;
					    	end
					    else
					    	begin
					    		sw_temp<= sw_in;
					    		if(sw_in!=sw_temp)
					    			begin
					    				is_count<=1'b0;
					    				next_state<= 2'd0;
					    			end
					    		else
								    begin
									    next_state<= 2'd1;
									    is_count<= 1'b1;
								    end
					    	end
				    2'b10:
					    if(sw_in!=sw_temp || sw_in==16'b0000000000000000)
						    begin
							    sw_out<= sw_temp;    
							    next_state<= 2'd3;
						    end
					    else
						    begin 
							    sw_out<= 16'b0000000000000000;
							    next_state<= 2'd2;
						    end
				    2'b11:
				    	begin
						    next_state<= 2'd0;
						    sw_out<= 16'b0000000000000000;
				    	end
				    default:
				    	next_state<= 2'd0;
			    endcase

			 end
	always @ ( posedge CLK or negedge RSTn )
		if(!RSTn)
		    begin
			    time_20ms<=1'b0;
			    count<=28'd0;
		    end
		else if(is_count==1'b1)
		    if(count==28'd100000)
			    begin
				    time_20ms<=1'b1;
				    count<=28'd0;
			    end
		    else
			    begin
				    time_20ms<=1'b0;
				    count<=count+1'd1;
			    end
		else
		    begin
			    time_20ms<=1'b0;
			    count<=28'd0;
	    	end
endmodule