data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v
 line:609: before: "dat_o"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:506: Signal definition not found, creating implicitly: \'param_scs\'\n                                                                                            : ... Suggested alternative: \'param_o\'\n   assign     param_scs       = param2[3];  \n              ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:612: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                         : ... In instance spi_flash_ctrl.simple_spi\n  assign rfre = wb_acc & (adr_i == 2\'b10) & ack_o & ~we_i;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:631: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                                         : ... In instance spi_flash_ctrl.simple_spi\n  wire wr_spsr = wb_wr & (adr_i == 2\'b01);\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:192: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s REPLICATE generates 32 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n   wire [63:0]      buf_addr_t = (buf_addr[31:20]==12\'h1fc)? \n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:192: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s REPLICATE generates 32 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n   wire [63:0]      buf_addr_t = (buf_addr[31:20]==12\'h1fc)? \n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:370: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'nxt_addr\' generates 24 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n                                                   nxt_addr - 24\'h1f    :\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:370: Operator SUB expects 64 bits on the RHS, but RHS\'s CONST \'24\'h1f\' generates 24 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n                                                   nxt_addr - 24\'h1f    :\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:371: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'nxt_addr\' generates 24 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n                                                   nxt_addr + 24\'b1) :\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:371: Operator ADD expects 64 bits on the RHS, but RHS\'s CONST \'24\'h1\' generates 24 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n                                                   nxt_addr + 24\'b1) :\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:369: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s VARREF \'nxt_addr\' generates 24 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n                     byte_ready & ~spi_pause? (buf_wrap&(&nxt_addr[4:0]) & ~(tot_bytes == 8\'b0)?\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/149848590/src/dev/spi/godson_sbridge_spi.v:368: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s COND generates 64 bits.\n                                                                                         : ... In instance spi_flash_ctrl\n         nxt_addr <= new_axireq & s_idle    ? buf_addr_t :\n                  ^~\n%Error: Exiting due to 11 warning(s)\n'
module spi_fifo4(clk, rst, clr,  din, we, dout, re, full, empty);

parameter dw = 8;

input           clk, rst;
input           clr;
input   [dw:1]  din;
input           we;
output  [dw:1]  dout;
input           re;
output          full, empty;

reg     [dw:1]  mem[0:3];
reg     [1:0]   wp;
reg     [1:0]   rp;
wire    [1:0]   wp_p1;
wire    [1:0]   wp_p2;
wire    [1:0]   rp_p1;
wire            full, empty;
reg             gb;

always @(posedge clk)
        if(!rst)        wp <=  2'h0;
        else
        if(clr)         wp <=  2'h0;
        else
        if(we)          wp <=  wp_p1;

assign wp_p1 = wp + 2'h1;
assign wp_p2 = wp + 2'h2;

always @(posedge clk)
        if(!rst)        rp <=  2'h0;
        else
        if(clr)         rp <=  2'h0;
        else
        if(re)          rp <=  rp_p1;

assign rp_p1 = rp + 2'h1;

assign  dout = mem[ rp ];

always @(posedge clk)
        if(we)  mem[ wp ] <=  din;

assign empty = (wp == rp) & !gb;
assign full  = (wp == rp) &  gb;

always @(posedge clk)
        if(!rst)                        gb <=  1'b0;
        else
        if(clr)                         gb <=  1'b0;
        else
        if((wp_p1 == rp) & we)          gb <=  1'b1;
        else
        if(re)                          gb <=  1'b0;

endmodule
module spi_fifo4(clk, rst, clr,  din, we, dout, re, full, empty);


parameter dw = 8;

input           clk, rst;
input           clr;
input   [dw:1]  din;
input           we;
output  [dw:1]  dout;
input           re;
output          full, empty;

reg     [dw:1]  mem[0:3];
reg     [1:0]   wp;
reg     [1:0]   rp;
wire    [1:0]   wp_p1;
wire    [1:0]   wp_p2;
wire    [1:0]   rp_p1;
wire            full, empty;
reg             gb;

always @(posedge clk)
        if(!rst)        wp <=  2'h0;
        else
        if(clr)         wp <=  2'h0;
        else
        if(we)          wp <=  wp_p1;

assign wp_p1 = wp + 2'h1;
assign wp_p2 = wp + 2'h2;

always @(posedge clk)
        if(!rst)        rp <=  2'h0;
        else
        if(clr)         rp <=  2'h0;
        else
        if(re)          rp <=  rp_p1;

assign rp_p1 = rp + 2'h1;

assign  dout = mem[ rp ];

always @(posedge clk)
        if(we)  mem[ wp ] <=  din;

assign empty = (wp == rp) & !gb;
assign full  = (wp == rp) &  gb;

always @(posedge clk)
        if(!rst)                        gb <=  1'b0;
        else
        if(clr)                         gb <=  1'b0;
        else
        if((wp_p1 == rp) & we)          gb <=  1'b1;
        else
        if(re)                          gb <=  1'b0;

endmodule