data/full_repos/permissive/104660645/sequence_detector/src/hdl/ss_mux.v
1: b"%Error: data/full_repos/permissive/104660645/sequence_detector/src/hdl/ss_mux.v:46: Cannot find file containing module: 'bcd_to_ss'\n bcd_to_ss to_ss (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104660645/sequence_detector/src/hdl,data/full_repos/permissive/104660645/bcd_to_ss\n             data/full_repos/permissive/104660645/sequence_detector/src/hdl,data/full_repos/permissive/104660645/bcd_to_ss.v\n             data/full_repos/permissive/104660645/sequence_detector/src/hdl,data/full_repos/permissive/104660645/bcd_to_ss.sv\n             bcd_to_ss\n             bcd_to_ss.v\n             bcd_to_ss.sv\n             obj_dir/bcd_to_ss\n             obj_dir/bcd_to_ss.v\n             obj_dir/bcd_to_ss.sv\n%Error: Exiting due to 1 error(s)\n"
module ss_mux
(
	input clk,
	input [31:0] bcd,
	input [7:0] dots,
	output [7:0] ss_value,
	output [7:0] ss_select
);

	localparam DIG_0 = 8'b00000001;
	localparam DIG_1 = 8'b00000010;
	localparam DIG_2 = 8'b00000100;
	localparam DIG_3 = 8'b00001000;
	localparam DIG_4 = 8'b00010000;
	localparam DIG_5 = 8'b00100000;
	localparam DIG_6 = 8'b01000000;
	localparam DIG_7 = 8'b10000000;

	reg [7:0] ss_select_q;
	reg [7:0] ss_select_d;


	wire dot_enable;
	assign dot_enable = |(ss_select_q & dots);


	reg [3:0] bcd_nibble;
	wire [6:0] ss_digits;

	bcd_to_ss to_ss (
		.bcd_in(bcd_nibble),
		.out(ss_digits)
	);


	assign ss_value = {~dot_enable, ss_digits};
	assign ss_select = ~ss_select_q;


	always @(*) begin
		case (ss_select_q)
		DIG_0: begin



			bcd_nibble = bcd[3:0];
			ss_select_d = DIG_1;
		end
		DIG_1: begin
			bcd_nibble = bcd[7:4];
			ss_select_d = DIG_2;
		end
		DIG_2: begin
			bcd_nibble = bcd[11:8];
			ss_select_d = DIG_3;
		end
		DIG_3: begin
			bcd_nibble = bcd[15:12];
			ss_select_d = DIG_4;
		end
		DIG_4: begin
			bcd_nibble = bcd[19:16];
			ss_select_d = DIG_5;
		end
		DIG_5: begin
			bcd_nibble = bcd[23:20];
			ss_select_d = DIG_6;
		end
		DIG_6: begin
			bcd_nibble = bcd[27:24];
			ss_select_d = DIG_7;
		end
		DIG_7: begin


			bcd_nibble = bcd[31:28];
			ss_select_d = DIG_0;
		end
		default: begin


			bcd_nibble = bcd[31:28];
			ss_select_d = DIG_0;
		end
		endcase
	end


	always @(posedge clk)
		ss_select_q <= ss_select_d;

endmodule
module ss_mux
(
	input clk,
	input [31:0] bcd,
	input [7:0] dots,
	output [7:0] ss_value,
	output [7:0] ss_select
);


	localparam DIG_0 = 8'b00000001;
	localparam DIG_1 = 8'b00000010;
	localparam DIG_2 = 8'b00000100;
	localparam DIG_3 = 8'b00001000;
	localparam DIG_4 = 8'b00010000;
	localparam DIG_5 = 8'b00100000;
	localparam DIG_6 = 8'b01000000;
	localparam DIG_7 = 8'b10000000;

	reg [7:0] ss_select_q;
	reg [7:0] ss_select_d;


	wire dot_enable;
	assign dot_enable = |(ss_select_q & dots);


	reg [3:0] bcd_nibble;
	wire [6:0] ss_digits;

	bcd_to_ss to_ss (
		.bcd_in(bcd_nibble),
		.out(ss_digits)
	);


	assign ss_value = {~dot_enable, ss_digits};
	assign ss_select = ~ss_select_q;


	always @(*) begin
		case (ss_select_q)
		DIG_0: begin



			bcd_nibble = bcd[3:0];
			ss_select_d = DIG_1;
		end
		DIG_1: begin
			bcd_nibble = bcd[7:4];
			ss_select_d = DIG_2;
		end
		DIG_2: begin
			bcd_nibble = bcd[11:8];
			ss_select_d = DIG_3;
		end
		DIG_3: begin
			bcd_nibble = bcd[15:12];
			ss_select_d = DIG_4;
		end
		DIG_4: begin
			bcd_nibble = bcd[19:16];
			ss_select_d = DIG_5;
		end
		DIG_5: begin
			bcd_nibble = bcd[23:20];
			ss_select_d = DIG_6;
		end
		DIG_6: begin
			bcd_nibble = bcd[27:24];
			ss_select_d = DIG_7;
		end
		DIG_7: begin


			bcd_nibble = bcd[31:28];
			ss_select_d = DIG_0;
		end
		default: begin


			bcd_nibble = bcd[31:28];
			ss_select_d = DIG_0;
		end
		endcase
	end


	always @(posedge clk)
		ss_select_q <= ss_select_d;

endmodule