data/full_repos/permissive/168228981/mux.v
data/verilator_xmls/9ec936e7-b876-4d1a-a3d2-27a3ea357d9e.xml
module mux(in1,in2,select,out);
input in1,in2,select;
output reg out;
always @(select or in1 or in2) begin
case (select)
1: out = in1;
0: out = in2;
endcase 
end

endmodule
module mux(in1,in2,select,out);

input in1,in2,select;
output reg out;
always @(select or in1 or in2) begin
case (select)
1: out = in1;
0: out = in2;
endcase 
end

endmodule