data/full_repos/permissive/128426084/src/sources_1/new/Controller_status_decode.v
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data/verilator_xmls/d5b4da7e-8367-42dc-aad4-14da409a8a3c.xml
module Controller_status_decode(

    input wire pclk,
    input wire [7:0] contByte,
    input wire Read,
    input wire clr,
    output reg ready = 0,
    output reg [3:0]address,
    output UP,
    output DOWN,
    output LEFT,
    output RIGHT,
    output [1:0] MODE,
    output START,
    output [7:0] L_JOY_Y,
    output [7:0] L_JOY_X,
    output [7:0] R_JOY_Y,
    output [7:0] R_JOY_X,
    output X,
    output O,
    output SQ,
    output CI,
    output SELECT,
    output L_JOY,
    output R_JOY

    );
    
    reg [7:0] Data [8:0];
    reg [3:0] i = 0;
    
    
        always @(posedge pclk)
            if(Read && (i<=8))    
                begin
                    address = i;
                end
            else if(i == 9)
                begin
                    ready = 1;
                end
            
            always @*
                if(clr && ready)
                    ready = 0;
         
         always @(negedge pclk)
            if(Read && (i<=8))
                begin
                    Data[i] = contByte;
                    i = i+1;
                end 
            
endmodule
module Controller_status_decode(

    input wire pclk,
    input wire [7:0] contByte,
    input wire Read,
    input wire clr,
    output reg ready = 0,
    output reg [3:0]address,
    output UP,
    output DOWN,
    output LEFT,
    output RIGHT,
    output [1:0] MODE,
    output START,
    output [7:0] L_JOY_Y,
    output [7:0] L_JOY_X,
    output [7:0] R_JOY_Y,
    output [7:0] R_JOY_X,
    output X,
    output O,
    output SQ,
    output CI,
    output SELECT,
    output L_JOY,
    output R_JOY

    );

    
    reg [7:0] Data [8:0];
    reg [3:0] i = 0;
    
    
        always @(posedge pclk)
            if(Read && (i<=8))    
                begin
                    address = i;
                end
            else if(i == 9)
                begin
                    ready = 1;
                end
            
            always @*
                if(clr && ready)
                    ready = 0;
         
         always @(negedge pclk)
            if(Read && (i<=8))
                begin
                    Data[i] = contByte;
                    i = i+1;
                end 
            
endmodule