data/full_repos/permissive/157424577/cache_decoder.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/157424577/cache_decoder.v:11: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'tag'\n                                                                           : ... In instance cache_decoder\n        tag <= address[31:12];\n        ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/157424577/cache_decoder.v:12: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'index'\n                                                                           : ... In instance cache_decoder\n        index <= address[11:4];\n        ^~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/157424577/cache_decoder.v:13: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'blk_offset'\n                                                                           : ... In instance cache_decoder\n        blk_offset <= address[3:0];\n        ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module cache_decoder(clk, address, tag, index, blk_offset);
    input clk;
    input [31:0] address;

    output [19:0] tag;
    output [7:0] index;
    output [3:0] blk_offset;

    always@(posedge clk)
    begin
        tag <= address[31:12];
        index <= address[11:4];
        blk_offset <= address[3:0];
    end
endmodule
module cache_decoder(clk, address, tag, index, blk_offset);

    input clk;
    input [31:0] address;

    output [19:0] tag;
    output [7:0] index;
    output [3:0] blk_offset;

    always@(posedge clk)
    begin
        tag <= address[31:12];
        index <= address[11:4];
        blk_offset <= address[3:0];
    end
endmodule