data/full_repos/permissive/205957121/mango1.v
 line:426 column:26: Illegal character "'"
1: b'%Error: data/full_repos/permissive/205957121/mango1.v:2: Cannot find include file: hvsync_generator.v\n`include "hvsync_generator.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205957121,data/full_repos/permissive/205957121/hvsync_generator.v\n             data/full_repos/permissive/205957121,data/full_repos/permissive/205957121/hvsync_generator.v.v\n             data/full_repos/permissive/205957121,data/full_repos/permissive/205957121/hvsync_generator.v.sv\n             hvsync_generator.v\n             hvsync_generator.v.v\n             hvsync_generator.v.sv\n             obj_dir/hvsync_generator.v\n             obj_dir/hvsync_generator.v.v\n             obj_dir/hvsync_generator.v.sv\n%Error: data/full_repos/permissive/205957121/mango1.v:3: Cannot find include file: cpu6502.v\n`include "cpu6502.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/205957121/mango1.v:4: Cannot find include file: font_cp437_8x8.v\n`include "font_cp437_8x8.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module signetics_term(clk, reset, hpos, vpos, tready, dot, te, ti);

  input clk,reset;
  input [8:0] hpos;
  input [8:0] vpos;
  input te;
  input [7:0] ti;
  output tready;
  output dot;
  
  reg [7:0] dshift[1024];
  reg [9:0] dofs;
  reg [9:0] scroll;
  reg [9:0] scnt;

  always @(posedge clk or posedge reset)
    if (reset) begin
      scnt <= 0;
      scroll <= 0;
      dofs <= 28*32;
      scroll <= 0;
    end else if (scnt > 0) begin
      dshift[scroll] <= 0;
      scroll <= scroll + 1;
      scnt <= scnt - 1;
    end else if (te) begin
      if (ti == 13) begin
        scnt <= 32;
        dofs <= ((dofs + 32) & ~31);
      end else if (ti >= 32) begin
        dshift[dofs] <= ti;
        if ((dofs & 31) == 31) scnt <= 32;
        dofs <= dofs + 1;
      end
    end


  font_cp437_8x8 tile_rom(
    .addr(char_addr),
    .data(char_data)
  );
  wire [9:0] nt_addr = {vpos[7:3], hpos[7:3]};
  wire [7:0] cur_char = dshift[nt_addr + scroll];
  wire [10:0] char_addr = {cur_char, vpos[2:0]};
  wire [7:0] char_data;
  wire dot = char_data[~hpos[2:0]];
  


  assign tready = !reset && !te && scnt == 0 && hpos == 256;
  
  initial begin
    integer i;
    for (i=0; i<1024; i=i+1) dshift[i] = 0;
  end
  
endmodule
module signetics_term(clk, reset, hpos, vpos, tready, dot, te, ti);


  input clk,reset;
  input [8:0] hpos;
  input [8:0] vpos;
  input te;
  input [7:0] ti;
  output tready;
  output dot;
  
  reg [7:0] dshift[1024];
  reg [9:0] dofs;
  reg [9:0] scroll;
  reg [9:0] scnt;

  always @(posedge clk or posedge reset)
    if (reset) begin
      scnt <= 0;
      scroll <= 0;
      dofs <= 28*32;
      scroll <= 0;
    end else if (scnt > 0) begin
      dshift[scroll] <= 0;
      scroll <= scroll + 1;
      scnt <= scnt - 1;
    end else if (te) begin
      if (ti == 13) begin
        scnt <= 32;
        dofs <= ((dofs + 32) & ~31);
      end else if (ti >= 32) begin
        dshift[dofs] <= ti;
        if ((dofs & 31) == 31) scnt <= 32;
        dofs <= dofs + 1;
      end
    end


  font_cp437_8x8 tile_rom(
    .addr(char_addr),
    .data(char_data)
  );
  wire [9:0] nt_addr = {vpos[7:3], hpos[7:3]};
  wire [7:0] cur_char = dshift[nt_addr + scroll];
  wire [10:0] char_addr = {cur_char, vpos[2:0]};
  wire [7:0] char_data;
  wire dot = char_data[~hpos[2:0]];
  


  assign tready = !reset && !te && scnt == 0 && hpos == 256;
  
  initial begin
    integer i;
    for (i=0; i<1024; i=i+1) dshift[i] = 0;
  end
  
endmodule