data/full_repos/permissive/132304455/src/alu1.v
data/verilator_xmls/08501cab-b376-455c-ab93-4e15e0decd47.xml
module alu1(out, carryout, A, B, carryin);
    output      out, carryout;
    input       A, B, carryin;

    full_adder fa1(out, carryout, A, B, carryin);

endmodule
module alu1(out, carryout, A, B, carryin);

    output      out, carryout;
    input       A, B, carryin;

    full_adder fa1(out, carryout, A, B, carryin);

endmodule