data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/output_m.v
data/verilator_xmls/236e08b1-38e0-48b9-8abc-ead5d3f37a2b.xml
module OutPort 
   #(
        parameter DATA_WIDTH = 37, 
        parameter POSITION = 4'b0101
   )
(
dataOutE, 
dataOutW,
dataOutS,
dataOutN,
dataOutL,
Outr_L,Outr_N,Outr_E,Outr_S,Outr_W,
Outw_L,Outw_N,Outw_E,Outw_S,Outw_W,
DataFiFo,
rdreq,
clk,
empty,
reset
);

output [DATA_WIDTH-1:0]  dataOutE, dataOutW, dataOutS, dataOutN, dataOutL;
input empty;
input reset;
input clk;
output Outr_L,Outr_N,Outr_E,Outr_S,Outr_W;
input Outw_L,Outw_N,Outw_E,Outw_S,Outw_W;
input [DATA_WIDTH-1:0] DataFiFo;
output rdreq;
reg rdreq;
reg [DATA_WIDTH-1:0]  dataOutE, dataOutW, dataOutS, dataOutN, dataOutL;
reg [1:0] step;

reg [4:0] Outr;
wire [4:0] Outw;

reg [2:0] routes[8:0][8:0];
initial
begin
  routes[0][0]=4;   routes[0][1]=0;   routes[0][2]=0;   routes[0][3]=0;   routes[0][4]=1;   routes[0][5]=1;   routes[0][6]=1;   routes[0][7]=1; 
  routes[1][0]=0;   routes[1][1]=4;   routes[1][2]=1;   routes[1][3]=2;   routes[1][4]=1;   routes[1][5]=2;   routes[1][6]=2;   routes[1][7]=0; 
  routes[2][0]=0;   routes[2][1]=0;   routes[2][2]=4;   routes[2][3]=1;   routes[2][4]=2;   routes[2][5]=1;   routes[2][6]=1;   routes[2][7]=2; 
  routes[3][0]=0;   routes[3][1]=0;   routes[3][2]=1;   routes[3][3]=4;   routes[3][4]=1;   routes[3][5]=2;   routes[3][6]=3;   routes[3][7]=2; 
  routes[4][0]=1;   routes[4][1]=0;   routes[4][2]=0;   routes[4][3]=0;   routes[4][4]=4;   routes[4][5]=1;   routes[4][6]=1;   routes[4][7]=1; 
  routes[5][0]=1;   routes[5][1]=0;   routes[5][2]=0;   routes[5][3]=0;   routes[5][4]=1;   routes[5][5]=4;   routes[5][6]=0;   routes[5][7]=1; 
  routes[6][0]=1;   routes[6][1]=0;   routes[6][2]=0;   routes[6][3]=0;   routes[6][4]=1;   routes[6][5]=0;   routes[6][6]=4;   routes[6][7]=1; 
  routes[7][0]=0;   routes[7][1]=0;   routes[7][2]=1;   routes[7][3]=3;   routes[7][4]=1;   routes[7][5]=2;   routes[7][6]=3;   routes[7][7]=4; 
end


assign Outw = {Outw_L,Outw_N,Outw_E,Outw_S,Outw_W};
assign {Outr_L,Outr_N,Outr_E,Outr_S,Outr_W} = Outr;

always @(posedge clk or posedge reset)

begin
	if (reset == 1'b1)
        begin
			step<=0;

			rdreq<=0;
			Outr<=0;
			
		end
    else
		begin

			case (step)
				2'b00:  if (!empty)
							begin
								rdreq<=1;
								step=2'b01;

							end

				2'b01: 	begin
						rdreq<=0;
						if (Outr == Outw)
							begin
								Outr<=0;
								step=2'b10;

							end

					end
				2'b10:  begin
				        case (routes[POSITION][DataFiFo[3:0]])
  				          0: begin Outr = 5'b00001; dataOutW=DataFiFo; end
				          1: begin Outr = 5'b00010; dataOutS=DataFiFo; end
				          2: begin Outr = 5'b00100; dataOutE=DataFiFo; end				  				        
				          3: begin Outr = 5'b01000; dataOutN=DataFiFo; end
				          4: begin Outr = 5'b10000; dataOutL=DataFiFo; end			
				        endcase	        				                








                $display("SW %d: Send flit at time: %t to %d", POSITION, $time, DataFiFo[3:0]);
								step=2'b11;
								end
				2'b11: if (Outr == Outw) begin Outr<=0; step=2'b00; end


			endcase
		end
end				
endmodule
module OutPort 
   #(
        parameter DATA_WIDTH = 37, 
        parameter POSITION = 4'b0101
   )
(
dataOutE, 
dataOutW,
dataOutS,
dataOutN,
dataOutL,
Outr_L,Outr_N,Outr_E,Outr_S,Outr_W,
Outw_L,Outw_N,Outw_E,Outw_S,Outw_W,
DataFiFo,
rdreq,
clk,
empty,
reset
);


output [DATA_WIDTH-1:0]  dataOutE, dataOutW, dataOutS, dataOutN, dataOutL;
input empty;
input reset;
input clk;
output Outr_L,Outr_N,Outr_E,Outr_S,Outr_W;
input Outw_L,Outw_N,Outw_E,Outw_S,Outw_W;
input [DATA_WIDTH-1:0] DataFiFo;
output rdreq;
reg rdreq;
reg [DATA_WIDTH-1:0]  dataOutE, dataOutW, dataOutS, dataOutN, dataOutL;
reg [1:0] step;

reg [4:0] Outr;
wire [4:0] Outw;

reg [2:0] routes[8:0][8:0];
initial
begin
  routes[0][0]=4;   routes[0][1]=0;   routes[0][2]=0;   routes[0][3]=0;   routes[0][4]=1;   routes[0][5]=1;   routes[0][6]=1;   routes[0][7]=1; 
  routes[1][0]=0;   routes[1][1]=4;   routes[1][2]=1;   routes[1][3]=2;   routes[1][4]=1;   routes[1][5]=2;   routes[1][6]=2;   routes[1][7]=0; 
  routes[2][0]=0;   routes[2][1]=0;   routes[2][2]=4;   routes[2][3]=1;   routes[2][4]=2;   routes[2][5]=1;   routes[2][6]=1;   routes[2][7]=2; 
  routes[3][0]=0;   routes[3][1]=0;   routes[3][2]=1;   routes[3][3]=4;   routes[3][4]=1;   routes[3][5]=2;   routes[3][6]=3;   routes[3][7]=2; 
  routes[4][0]=1;   routes[4][1]=0;   routes[4][2]=0;   routes[4][3]=0;   routes[4][4]=4;   routes[4][5]=1;   routes[4][6]=1;   routes[4][7]=1; 
  routes[5][0]=1;   routes[5][1]=0;   routes[5][2]=0;   routes[5][3]=0;   routes[5][4]=1;   routes[5][5]=4;   routes[5][6]=0;   routes[5][7]=1; 
  routes[6][0]=1;   routes[6][1]=0;   routes[6][2]=0;   routes[6][3]=0;   routes[6][4]=1;   routes[6][5]=0;   routes[6][6]=4;   routes[6][7]=1; 
  routes[7][0]=0;   routes[7][1]=0;   routes[7][2]=1;   routes[7][3]=3;   routes[7][4]=1;   routes[7][5]=2;   routes[7][6]=3;   routes[7][7]=4; 
end


assign Outw = {Outw_L,Outw_N,Outw_E,Outw_S,Outw_W};
assign {Outr_L,Outr_N,Outr_E,Outr_S,Outr_W} = Outr;

always @(posedge clk or posedge reset)

begin
	if (reset == 1'b1)
        begin
			step<=0;

			rdreq<=0;
			Outr<=0;
			
		end
    else
		begin

			case (step)
				2'b00:  if (!empty)
							begin
								rdreq<=1;
								step=2'b01;

							end

				2'b01: 	begin
						rdreq<=0;
						if (Outr == Outw)
							begin
								Outr<=0;
								step=2'b10;

							end

					end
				2'b10:  begin
				        case (routes[POSITION][DataFiFo[3:0]])
  				          0: begin Outr = 5'b00001; dataOutW=DataFiFo; end
				          1: begin Outr = 5'b00010; dataOutS=DataFiFo; end
				          2: begin Outr = 5'b00100; dataOutE=DataFiFo; end				  				        
				          3: begin Outr = 5'b01000; dataOutN=DataFiFo; end
				          4: begin Outr = 5'b10000; dataOutL=DataFiFo; end			
				        endcase	        				                








                $display("SW %d: Send flit at time: %t to %d", POSITION, $time, DataFiFo[3:0]);
								step=2'b11;
								end
				2'b11: if (Outr == Outw) begin Outr<=0; step=2'b00; end


			endcase
		end
end				
endmodule