data/full_repos/permissive/117439411/Pacman_ACL_v1/sel_data.v
data/verilator_xmls/929ddaaf-1088-4d04-b231-8702b912ec37.xml
module sel_Data(
		CLK,
		RST,
		xAxis,
		yAxis,
		x_DOUT,
		y_DOUT
);




   input        CLK;
   input        RST;
   input [9:0]  xAxis;
   input [9:0]  yAxis;
   output [9:0] x_DOUT;
   output [9:0] y_DOUT;



   reg [9:0]    x_DOUT;
   reg [9:0]    y_DOUT;   






		always @(posedge CLK or posedge RST)
			begin
				if (RST == 1'b1)
					begin
						x_DOUT <= 10'b0000000000;
						y_DOUT <= 10'b0000000000;
					end
				else 
					begin
						if (xAxis[9] == 1'b1)
							x_DOUT <= {xAxis[9], (9'b000000000 - xAxis[8:0])};
						else
							x_DOUT <= xAxis;
						if (yAxis[9] == 1'b1)
							y_DOUT <= {yAxis[9], (9'b000000000 - yAxis[8:0])};
						else
							y_DOUT <= yAxis;
					end
			end	
endmodule
module sel_Data(
		CLK,
		RST,
		xAxis,
		yAxis,
		x_DOUT,
		y_DOUT
);





   input        CLK;
   input        RST;
   input [9:0]  xAxis;
   input [9:0]  yAxis;
   output [9:0] x_DOUT;
   output [9:0] y_DOUT;



   reg [9:0]    x_DOUT;
   reg [9:0]    y_DOUT;   






		always @(posedge CLK or posedge RST)
			begin
				if (RST == 1'b1)
					begin
						x_DOUT <= 10'b0000000000;
						y_DOUT <= 10'b0000000000;
					end
				else 
					begin
						if (xAxis[9] == 1'b1)
							x_DOUT <= {xAxis[9], (9'b000000000 - xAxis[8:0])};
						else
							x_DOUT <= xAxis;
						if (yAxis[9] == 1'b1)
							y_DOUT <= {yAxis[9], (9'b000000000 - yAxis[8:0])};
						else
							y_DOUT <= yAxis;
					end
			end	
endmodule