data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:5: Cannot find include file: defines.sv\n`include "defines.sv" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench,data/full_repos/permissive/194652065/defines.sv\n             data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench,data/full_repos/permissive/194652065/defines.sv.v\n             data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench,data/full_repos/permissive/194652065/defines.sv.sv\n             defines.sv\n             defines.sv.v\n             defines.sv.sv\n             obj_dir/defines.sv\n             obj_dir/defines.sv.v\n             obj_dir/defines.sv.sv\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:13: Define or directive not defined: \'`P_INP_DATA_W\'\n  reg [`P_INP_DATA_W-1:0] i_data;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:15: Define or directive not defined: \'`P_OUP_DATA_W\'\n  wire signed [`P_OUP_DATA_W-1:0] oup_data;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:28: Define or directive not defined: \'`P_OUP_DATA_W\'\n  reg signed [`P_OUP_DATA_W-1:0]       o_data_mat;\n              ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:33: Unsupported: Ignoring delay on this delayed statement.\n      #170 i_rst_an = 1\'b0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:34: Unsupported: Ignoring delay on this delayed statement.\n      #205 i_rst_an = 1\'b1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:40: Unsupported: Ignoring delay on this delayed statement.\n      #410 i_ena = 1\'b1;\n      ^\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:49: Define or directive not defined: \'`TESTCASE\'\n      $display("### Testcase %d", `TESTCASE);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      $display("### Testcase %d", `TESTCASE);\n                                           ^\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:51: Define or directive not defined: \'`TESTCASE\'\n      $sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");\n                                                                                ^~~~~~~~~\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:51: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      $sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");\n                                                                                         ^\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:52: Define or directive not defined: \'`TESTCASE\'\n      $sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");\n                                                                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:52: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      $sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");\n                                                                                           ^\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:56: Define or directive not defined: \'`NULL\'\n      if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin\n                          ^~~~~\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:56: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin\n                               ^\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:56: Define or directive not defined: \'`NULL\'\n      if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin\n                                                  ^~~~~\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:61: syntax error, unexpected \'@\'\n      @(posedge data_ready) \n      ^\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:67: syntax error, unexpected $display\n            $display("### INFO: Testcase FAILED");\n            ^~~~~~~~\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:85: syntax error, unexpected \'=\', expecting IDENTIFIER\n        data_ready = 1\'b1;\n                   ^\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:105: Define or directive not defined: \'`P_INP_DATA_W\'\n    .gp_inp_width    (`P_INP_DATA_W),  \n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:106: Define or directive not defined: \'`P_COEFF_L\'\n    .gp_coeff_length (`P_COEFF_L),\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:107: Define or directive not defined: \'`P_COEFF_W\'\n    .gp_coeff_width  (`P_COEFF_W),\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:108: Define or directive not defined: \'`P_TF_DF\'\n    .gp_tf_df      (`P_TF_DF),\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/194652065/.drl_src_code/filt_fir/sim/testbench/filt_fir_tb.sv:109: Define or directive not defined: \'`P_SYMM\'\n    .gp_symm         (`P_SYMM),\n                      ^~~~~~~\n%Error: Exiting due to 21 error(s), 3 warning(s)\n'
module filt_fir_tb;
  time CLK_PERIOD = 50;
  
  reg       i_rst_an;
  reg       i_ena;
  reg       i_clk;
  reg [`P_INP_DATA_W-1:0] i_data;
  wire                 rdy;
  wire signed [`P_OUP_DATA_W-1:0] oup_data;
  reg                             data_ready;
  integer error_count=0;
  integer nr_of_samples=0;
  reg [8*64:1]                    filename_vcd;

  reg [8*64:1]                    filename_mat_inp;
  integer                         fid_mat_inp;
  integer                         status_mat_inp;  

  reg [8*64:1]                    filename_mat_oup;
  integer                         fid_mat_oup;
  integer                         status_mat_oup;
  reg signed [`P_OUP_DATA_W-1:0]       o_data_mat;

  initial
    begin
           i_rst_an = 1'b1;
      #170 i_rst_an = 1'b0;
      #205 i_rst_an = 1'b1;
    end
  
  initial
    begin
           i_ena = 1'b0;
      #410 i_ena = 1'b1;
    end
  
  initial i_clk = 1'b0;
  always i_clk = #(CLK_PERIOD) ~i_clk;
  
  initial
    begin: TEXTIO_READ_IN
      $display("### INFO: RTL Simulation of FIR Filter.");
      $display("### Testcase %d", `TESTCASE);

      $sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
      $sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
      $display("%s",filename_mat_inp);
      fid_mat_inp = $fopen(filename_mat_inp, "r");
      fid_mat_oup = $fopen(filename_mat_oup, "r");
      if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
        $display("data_file handle was NULL");
        $finish;
      end
      
      @(posedge data_ready) 
        begin 
	  $fclose(fid_mat_inp); 
	  $fclose(fid_mat_oup); 

	  if (error_count>0)
            $display("### INFO: Testcase FAILED");
          else
            $display("### INFO: Testcase PASSED with %d samples", nr_of_samples);
	    
  	  $finish; 
	end
    end
    
  always @(posedge i_clk)
    begin: MATLAB_STIMULI
      if (i_rst_an && i_ena) begin
        status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_data);
	nr_of_samples <= nr_of_samples + 1;
      end
      else
        i_data = 'd0;
	
      if ($feof(fid_mat_inp)) begin
        data_ready = 1'b1;
      end
    end
  
  always @(posedge i_clk)
    begin: MATLAB_RESPONSE
      if (i_rst_an && i_ena)
        status_mat_oup = $fscanf(fid_mat_oup,"%d\n", o_data_mat);
    end

  always @(negedge i_clk)
    begin
      if (i_rst_an && i_ena)
        if (oup_data != o_data_mat) 
	  begin 
	    $error("### RTL = %d, MAT = %d", oup_data, o_data_mat); error_count<= error_count + 1;
	  end
    end
      
  filt_fir #(
    .gp_inp_width    (`P_INP_DATA_W),  
    .gp_coeff_length (`P_COEFF_L),
    .gp_coeff_width  (`P_COEFF_W),
    .gp_tf_df	     (`P_TF_DF),
    .gp_symm         (`P_SYMM),
    .gp_oup_width    ()
  ) dut (
    .i_rst_an (i_rst_an),
    .i_ena    (i_ena),
    .i_clk    (i_clk),
    .i_data   (i_data),
    .o_data   (oup_data)
  );

`ifdef VCD
  initial
     begin
       $sformat(filename_vcd,"%s%0d%s","filt_fir_",`TESTCASE,".vcd");
       $dumpfile(filename_vcd);
       $dumpvars(0,filt_fir_tb);
     end
`endif
    
endmodule
module filt_fir_tb;

  time CLK_PERIOD = 50;
  
  reg       i_rst_an;
  reg       i_ena;
  reg       i_clk;
  reg [`P_INP_DATA_W-1:0] i_data;
  wire                 rdy;
  wire signed [`P_OUP_DATA_W-1:0] oup_data;
  reg                             data_ready;
  integer error_count=0;
  integer nr_of_samples=0;
  reg [8*64:1]                    filename_vcd;

  reg [8*64:1]                    filename_mat_inp;
  integer                         fid_mat_inp;
  integer                         status_mat_inp;  

  reg [8*64:1]                    filename_mat_oup;
  integer                         fid_mat_oup;
  integer                         status_mat_oup;
  reg signed [`P_OUP_DATA_W-1:0]       o_data_mat;

  initial
    begin
           i_rst_an = 1'b1;
      #170 i_rst_an = 1'b0;
      #205 i_rst_an = 1'b1;
    end
  
  initial
    begin
           i_ena = 1'b0;
      #410 i_ena = 1'b1;
    end
  
  initial i_clk = 1'b0;
  always i_clk = #(CLK_PERIOD) ~i_clk;
  
  initial
    begin: TEXTIO_READ_IN
      $display("### INFO: RTL Simulation of FIR Filter.");
      $display("### Testcase %d", `TESTCASE);

      $sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
      $sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
      $display("%s",filename_mat_inp);
      fid_mat_inp = $fopen(filename_mat_inp, "r");
      fid_mat_oup = $fopen(filename_mat_oup, "r");
      if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
        $display("data_file handle was NULL");
        $finish;
      end
      
      @(posedge data_ready) 
        begin 
	  $fclose(fid_mat_inp); 
	  $fclose(fid_mat_oup); 

	  if (error_count>0)
            $display("### INFO: Testcase FAILED");
          else
            $display("### INFO: Testcase PASSED with %d samples", nr_of_samples);
	    
  	  $finish; 
	end
    end
    
  always @(posedge i_clk)
    begin: MATLAB_STIMULI
      if (i_rst_an && i_ena) begin
        status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_data);
	nr_of_samples <= nr_of_samples + 1;
      end
      else
        i_data = 'd0;
	
      if ($feof(fid_mat_inp)) begin
        data_ready = 1'b1;
      end
    end
  
  always @(posedge i_clk)
    begin: MATLAB_RESPONSE
      if (i_rst_an && i_ena)
        status_mat_oup = $fscanf(fid_mat_oup,"%d\n", o_data_mat);
    end

  always @(negedge i_clk)
    begin
      if (i_rst_an && i_ena)
        if (oup_data != o_data_mat) 
	  begin 
	    $error("### RTL = %d, MAT = %d", oup_data, o_data_mat); error_count<= error_count + 1;
	  end
    end
      
  filt_fir #(
    .gp_inp_width    (`P_INP_DATA_W),  
    .gp_coeff_length (`P_COEFF_L),
    .gp_coeff_width  (`P_COEFF_W),
    .gp_tf_df	     (`P_TF_DF),
    .gp_symm         (`P_SYMM),
    .gp_oup_width    ()
  ) dut (
    .i_rst_an (i_rst_an),
    .i_ena    (i_ena),
    .i_clk    (i_clk),
    .i_data   (i_data),
    .o_data   (oup_data)
  );

`ifdef VCD
  initial
     begin
       $sformat(filename_vcd,"%s%0d%s","filt_fir_",`TESTCASE,".vcd");
       $dumpfile(filename_vcd);
       $dumpvars(0,filt_fir_tb);
     end
`endif
    
endmodule