data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/dmem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/dmem.v:33: Bit extraction of array[127:0] requires 7 bit index, not 30 bits.\n                                                                                                                                  : ... In instance dmem\n    assign rd=RAM[adr[31:2]];\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/dmem.v:37: Bit extraction of array[127:0] requires 7 bit index, not 30 bits.\n                                                                                                                                  : ... In instance dmem\n        RAM[adr[31:2]]<=wd;\n           ^\n%Error: Exiting due to 2 warning(s)\n'
module dmem(
    input clk,we,
    input [31:0] adr,wd,
    output [31:0] rd,
    input [6:0] SW,
    output reg [31:0] t
    );
    
    reg [31:0] RAM[127:0];
    
    assign rd=RAM[adr[31:2]];
    
    always@(posedge clk)
    if(we)
        RAM[adr[31:2]]<=wd;
        

    always@(*)
        t<=RAM[SW];
    
endmodule
module dmem(
    input clk,we,
    input [31:0] adr,wd,
    output [31:0] rd,
    input [6:0] SW,
    output reg [31:0] t
    );

    
    reg [31:0] RAM[127:0];
    
    assign rd=RAM[adr[31:2]];
    
    always@(posedge clk)
    if(we)
        RAM[adr[31:2]]<=wd;
        

    always@(*)
        t<=RAM[SW];
    
endmodule