data/full_repos/permissive/159029085/src/cpld_fifo.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/159029085/src/cpld_fifo.v:239: Signal definition not found, creating implicitly: \'slave_rd\'\n                                                                           : ... Suggested alternative: \'slave_rd_b\'\n                      .oeb(slave_rd),\n                           ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module cpld_fifo(
                 input [15:0] adr,
                 input	ioreq_b,
                 input	clk,
                 input	reset_b,
                 input	wr_b,
                 input	rd_b,
                 input	slave_rd_b,
                 input	slave_wr,
                 input  slave_unused,
                 
                 inout [7:0]	host_data,
                 inout [7:0]	slave_data,
                 output	slave_dor,
                 output	slave_dir
                 );


  wire host_slave_wclk, slave_host_oeb;
  
  glue glue_u(
            .adr(adr),
            .ioreq_b(ioreq_b),
            .clk(clk),
            .reset_b(reset_b),
            .wr_b(wr_b),
            .rd_b(rd_b),
            .slave_rd_b(slave_rd_b),
            .slave_wr(slave_wr),
            .host_slave_wclk(host_slave_wclk),
            .slave_host_oeb(slave_host_oeb),
            .slave_dor(slave_dor),
            .host_dor(host_data[1]),
            .slave_dir(slave_dir),
            .host_dir(host_data[0])
              
       );

  lvc374 slave_host_u(
                      .clk(slave_wr),
                      .oeb(slave_host_oeb),
                      .d(slave_data),
                      .q(host_data)
         );

  lvc374 host_slave_u(
                      .clk(host_slave_wclk),
                      .oeb(slave_rd),
                      .d(host_data),
                      .q(slave_data)                      
         );
    
  
endmodule
module cpld_fifo(
                 input [15:0] adr,
                 input	ioreq_b,
                 input	clk,
                 input	reset_b,
                 input	wr_b,
                 input	rd_b,
                 input	slave_rd_b,
                 input	slave_wr,
                 input  slave_unused,
                 
                 inout [7:0]	host_data,
                 inout [7:0]	slave_data,
                 output	slave_dor,
                 output	slave_dir
                 );



  wire host_slave_wclk, slave_host_oeb;
  
  glue glue_u(
            .adr(adr),
            .ioreq_b(ioreq_b),
            .clk(clk),
            .reset_b(reset_b),
            .wr_b(wr_b),
            .rd_b(rd_b),
            .slave_rd_b(slave_rd_b),
            .slave_wr(slave_wr),
            .host_slave_wclk(host_slave_wclk),
            .slave_host_oeb(slave_host_oeb),
            .slave_dor(slave_dor),
            .host_dor(host_data[1]),
            .slave_dir(slave_dir),
            .host_dir(host_data[0])
              
       );

  lvc374 slave_host_u(
                      .clk(slave_wr),
                      .oeb(slave_host_oeb),
                      .d(slave_data),
                      .q(host_data)
         );

  lvc374 host_slave_u(
                      .clk(host_slave_wclk),
                      .oeb(slave_rd),
                      .d(host_data),
                      .q(slave_data)                      
         );
    
  
endmodule