data/full_repos/permissive/139213403/FPGA/reset_controller_testbench.v
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/reset_controller_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/reset_controller_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/reset_controller_testbench.v:26: syntax error, unexpected \'@\'\n   @(negedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/reset_controller_testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n   #(T);\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/reset_controller_testbench.v:36: syntax error, unexpected \'@\'\n   @(negedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/reset_controller_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/reset_controller_testbench.v:46: syntax error, unexpected \'@\'\n   @(negedge reset);\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/reset_controller_testbench.v:52: syntax error, unexpected \'@\'\n     @(negedge clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/reset_controller_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n     #(T * (i + 2));\n     ^\n%Error: Exiting due to 4 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reset_controller_testbench;
	localparam T = 20;
	localparam M = 8;
	
	integer i;
	reg clk, reset;
	reg start;
	reg [M-1:0] m;
	wire en, ready;
	
	reset_controller #(.M_BITS(M)) uut(.clk(clk), .reset(reset), .start(start), .m(m), .en(en), .ready(ready));
	

	always
		begin
			clk = 1'b1;
			#(T / 2);
			clk = 1'b0;
			#(T / 2);
		end
		
	task do_reset;
		input reg [M-1:0] count;
		begin
			$display("do_reset: %d counts", count);
			@(negedge clk);
			m = count;
			start = 1;
			#(T);
			start = 0;
		end
	endtask
	
	initial
		begin
			@(negedge clk);
			reset = 1;
			m = 0;
			#(T / 2);
			reset = 0;
		end
		

	initial
		begin
			@(negedge reset);
			@(negedge clk);
			
			for (i = 0; i < 256; i = i + 1)
				begin
					do_reset(i);
					@(negedge clk);
					#(T * (i + 2));
				end
			
			$stop;
		end
	
endmodule
module reset_controller_testbench;

	localparam T = 20;
	localparam M = 8;
	
	integer i;
	reg clk, reset;
	reg start;
	reg [M-1:0] m;
	wire en, ready;
	
	reset_controller #(.M_BITS(M)) uut(.clk(clk), .reset(reset), .start(start), .m(m), .en(en), .ready(ready));
	

	always
		begin
			clk = 1'b1;
			#(T / 2);
			clk = 1'b0;
			#(T / 2);
		end
		
	task do_reset;
		input reg [M-1:0] count;
		begin
			$display("do_reset: %d counts", count);
			@(negedge clk);
			m = count;
			start = 1;
			#(T);
			start = 0;
		end
	endtask
	
	initial
		begin
			@(negedge clk);
			reset = 1;
			m = 0;
			#(T / 2);
			reset = 0;
		end
		

	initial
		begin
			@(negedge reset);
			@(negedge clk);
			
			for (i = 0; i < 256; i = i + 1)
				begin
					do_reset(i);
					@(negedge clk);
					#(T * (i + 2));
				end
			
			$stop;
		end
	
endmodule