data/full_repos/permissive/143278/ivltests/assign_op_type.v
 line:17: before: "+"
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/assign_op_type.v:17: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'a\' generates 4 bits.\n                                                                              : ... In instance test\n  b += a;\n    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/assign_op_type.v:18: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'a\' generates 4 bits.\n                                                                              : ... In instance test\n  c += a;\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/assign_op_type.v:19: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'a\' generates 4 bits.\n                                                                              : ... In instance test\n  {d} += a;\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/assign_op_type.v:20: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'a\' generates 4 bits.\n                                                                              : ... In instance test\n  e[7:0] += a;\n         ^~\n%Error: Exiting due to 4 warning(s)\n'
module test();

reg signed [3:0] a;
reg        [7:0] b;
reg signed [7:0] c;
reg signed [7:0] d;
reg signed [7:0] e;

reg failed = 0;

initial begin
  a = -1;
  b = 4;
  c = 4;
  d = 4;
  e = 4;
  b += a;
  c += a;
  {d} += a;
  e[7:0] += a;
  $display("%0d", b);
  if (b !== 19) failed = 1;
  $display("%0d", c);
  if (c !==  3) failed = 1;
  $display("%0d", d);
  if (d !== 19) failed = 1;
  $display("%0d", e);
  if (e !== 19) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module test();


reg signed [3:0] a;
reg        [7:0] b;
reg signed [7:0] c;
reg signed [7:0] d;
reg signed [7:0] e;

reg failed = 0;

initial begin
  a = -1;
  b = 4;
  c = 4;
  d = 4;
  e = 4;
  b += a;
  c += a;
  {d} += a;
  e[7:0] += a;
  $display("%0d", b);
  if (b !== 19) failed = 1;
  $display("%0d", c);
  if (c !==  3) failed = 1;
  $display("%0d", d);
  if (d !== 19) failed = 1;
  $display("%0d", e);
  if (e !== 19) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule