data/full_repos/permissive/201488448/1_verilog/02_wire4.v
data/verilator_xmls/17cd9cbc-0610-4a98-92b1-2dc4f6dca0d0.xml
module top_module (
	input a,
	input b,
	input c,
	output w,
	output x,
	output y,
	output z  );
	
	assign w = a;
	assign x = b;
	assign y = b;
	assign z = c;

endmodule
module top_module (
	input a,
	input b,
	input c,
	output w,
	output x,
	output y,
	output z  );

	
	assign w = a;
	assign x = b;
	assign y = b;
	assign z = c;

endmodule