data/full_repos/permissive/121410129/Step2/TB2_Gray.v
 line:32: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/121410129/Step2/TB2_Gray.v:31: Unsupported: Ignoring delay on this delayed statement.\n #20reset <= 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/121410129/Step2/TB2_Gray.v:32: Unsupported: Ignoring delay on this delayed statement.\n #300$finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/121410129/Step2/TB2_Gray.v:37: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Error: data/full_repos/permissive/121410129/Step2/TB2_Gray.v:21: Cannot find file containing module: \'gray_Nbits\'\ngray_Nbits DUT(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/121410129/Step2,data/full_repos/permissive/121410129/gray_Nbits\n             data/full_repos/permissive/121410129/Step2,data/full_repos/permissive/121410129/gray_Nbits.v\n             data/full_repos/permissive/121410129/Step2,data/full_repos/permissive/121410129/gray_Nbits.sv\n             gray_Nbits\n             gray_Nbits.v\n             gray_Nbits.sv\n             obj_dir/gray_Nbits\n             obj_dir/gray_Nbits.v\n             obj_dir/gray_Nbits.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB2();
reg clk, reset;
wire [3:0]leds;






gray_Nbits DUT(
	.clk		(clk),
	.reset		(reset),
	.gray_out	(leds)
);


initial begin
	clk <= 1;
	reset <= 1;
	#20reset <= 0;
	#300$finish;
end


always begin
	#5 clk <= ~clk;
end

  
endmodule
module TB2();

reg clk, reset;
wire [3:0]leds;






gray_Nbits DUT(
	.clk		(clk),
	.reset		(reset),
	.gray_out	(leds)
);


initial begin
	clk <= 1;
	reset <= 1;
	#20reset <= 0;
	#300$finish;
end


always begin
	#5 clk <= ~clk;
end

  
endmodule