data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:146: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:160: Unsupported: Ignoring delay on this delayed statement.\n   #8;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:162: Unsupported: Ignoring delay on this delayed statement.\n   #8;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:164: Unsupported: Ignoring delay on this delayed statement.\n   #8;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:183: Unsupported: Ignoring delay on this delayed statement.\n  #4;\n  ^\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'write_clock\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'read_clock\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'sync_read_address\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'channel\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'start_read_address\'\n ) fg (\n   ^~\n%Warning-PINMISSING: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:128: Cell has missing pin: \'end_read_address\'\n ) fg (\n   ^~\n%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:111: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                       : ... Top module \'sequencer_sync\'\nmodule sequencer_sync #(\n       ^~~~~~~~~~~~~~\n                                                                                       : ... Top module \'function_generator_tb\'\nmodule function_generator_tb;\n       ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/sequencer.v:129: Pin not found: \'clock\'\n  .clock(clock),\n   ^~~~~\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module function_generator_tb;
	parameter DATA_BUS_WIDTH = 8;
	parameter ADDRESS_BUS_DEPTH = 11;
	parameter NUMBER_OF_CHANNELS = 1;
	parameter ADDRESS_MAX = (2**ADDRESS_BUS_DEPTH)-1;
	reg clock = 0;
	reg reset = 1;


	reg [DATA_BUS_WIDTH-1:0] data_in = 0;
	reg [ADDRESS_BUS_DEPTH-1:0] write_address = 0;
	reg write_enable = 0;
	wire [DATA_BUS_WIDTH-1:0] data_out;
	function_generator #(
		.DATA_BUS_WIDTH(DATA_BUS_WIDTH),
		.ADDRESS_BUS_DEPTH(ADDRESS_BUS_DEPTH),
		.NUMBER_OF_CHANNELS(NUMBER_OF_CHANNELS)
	) fg (
		.clock(clock),
		.reset(reset),
		.write_address(write_address),
		.data_in(data_in),
		.write_enable(write_enable),
		.data_out(data_out)


	);
	reg [ADDRESS_BUS_DEPTH-1:0] ad;
	initial begin
		clock <= 0;
		reset <= 1;

		data_in <= 0;
		write_address <= 0;
		write_enable <= 0;
		#8;
		reset <= 0;
		#8;
		for (ad=0; ad<=ADDRESS_MAX; ad=ad+1) begin : ramp
			write_address <= ad;
			if (0) begin
				if (write_address==123) begin
					data_in <= 1;
				end else begin
					data_in <= 0;
				end
			end else begin
				data_in <= ad[7:0];
			end
			#8;
			write_enable <= 1;
			#8;
			write_enable <= 0;
			#8;
		end















	end
	always begin
		#4;
		clock = ~clock;
	end
endmodule
module function_generator_tb;

	parameter DATA_BUS_WIDTH = 8;
	parameter ADDRESS_BUS_DEPTH = 11;
	parameter NUMBER_OF_CHANNELS = 1;
	parameter ADDRESS_MAX = (2**ADDRESS_BUS_DEPTH)-1;
	reg clock = 0;
	reg reset = 1;


	reg [DATA_BUS_WIDTH-1:0] data_in = 0;
	reg [ADDRESS_BUS_DEPTH-1:0] write_address = 0;
	reg write_enable = 0;
	wire [DATA_BUS_WIDTH-1:0] data_out;
	function_generator #(
		.DATA_BUS_WIDTH(DATA_BUS_WIDTH),
		.ADDRESS_BUS_DEPTH(ADDRESS_BUS_DEPTH),
		.NUMBER_OF_CHANNELS(NUMBER_OF_CHANNELS)
	) fg (
		.clock(clock),
		.reset(reset),
		.write_address(write_address),
		.data_in(data_in),
		.write_enable(write_enable),
		.data_out(data_out)


	);
	reg [ADDRESS_BUS_DEPTH-1:0] ad;
	initial begin
		clock <= 0;
		reset <= 1;

		data_in <= 0;
		write_address <= 0;
		write_enable <= 0;
		#8;
		reset <= 0;
		#8;
		for (ad=0; ad<=ADDRESS_MAX; ad=ad+1) begin : ramp
			write_address <= ad;
			if (0) begin
				if (write_address==123) begin
					data_in <= 1;
				end else begin
					data_in <= 0;
				end
			end else begin
				data_in <= ad[7:0];
			end
			#8;
			write_enable <= 1;
			#8;
			write_enable <= 0;
			#8;
		end















	end
	always begin
		#4;
		clock = ~clock;
	end
endmodule