data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:310: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                    : ... Top module \'ARM_CPU\'\nmodule ARM_CPU\n       ^~~~~~~\n                                                                                    : ... Top module \'IC\'\nmodule IC\n       ^~\n                                                                                    : ... Top module \'Data_Memory\'\nmodule Data_Memory\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:563: Operator ASSIGN expects 38 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                                 : ... In instance ARM_CPU.unit4\n      outImmediate[63:26] = {64{outImmediate[25]}};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:566: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s SEL generates 19 bits.\n                                                                                 : ... In instance ARM_CPU.unit4\n      outImmediate[19:0] = inputInstruction[23:5];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:567: Operator ASSIGN expects 44 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                                 : ... In instance ARM_CPU.unit4\n      outImmediate[63:20] = {64{outImmediate[19]}};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:570: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 9 bits.\n                                                                                 : ... In instance ARM_CPU.unit4\n      outImmediate[9:0] = inputInstruction[20:12];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:571: Operator ASSIGN expects 54 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                                 : ... In instance ARM_CPU.unit4\n      outImmediate[63:10] = {64{outImmediate[9]}};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:515: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                 : ... In instance ARM_CPU.unit2\n            reg_out <= 1\'bx;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:287: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'initCount\' generates 32 bits.\n                                                                                 : ... In instance ARM_CPU.unit3\n      Data[initCount] = initCount;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:406: Bit extraction of array[31:0] requires 5 bit index, not 64 bits.\n                                                                                 : ... In instance Data_Memory\n        Data[inputAddress] = inputData;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:408: Bit extraction of array[31:0] requires 5 bit index, not 64 bits.\n                                                                                 : ... In instance Data_Memory\n        outputData = Data[inputAddress];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:336: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hf8\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[0] = 8\'hf8;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:337: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h40\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[1] = 8\'h40;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:338: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h11\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[2] = 8\'h11;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:339: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h22\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[3] = 8\'h22;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:342: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h8b\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[4] = 8\'h8b;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:343: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[5] = 8\'h05;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:344: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[6] = 8\'h01;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:345: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h43\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[7] = 8\'h43;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:348: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hcb\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[8] = 8\'hcb;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:349: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[9] = 8\'h05;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:350: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h1\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[10] = 8\'h01;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:351: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h44\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[11] = 8\'h44;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:354: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'haa\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[12] = 8\'haa;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:355: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'ha\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[13] = 8\'h0a;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:356: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[14] = 8\'h03;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:357: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hc5\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[15] = 8\'hc5;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:360: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h8a\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[16] = 8\'h8a;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:361: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'ha\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[17] = 8\'h0a;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:362: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[18] = 8\'h03;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:363: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hc6\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[19] = 8\'hc6;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:366: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hf8\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[20] = 8\'hf8;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:367: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[21] = 8\'h00;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:368: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h3\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[22] = 8\'h03;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:369: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'he2\' generates 8 bits.\n                                                                                 : ... In instance IC\n    Data[23] = 8\'he2;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:374: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                                 : ... In instance IC\n    instruction_out[8:0] = Data[PC_in + 3];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:375: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                                 : ... In instance IC\n    instruction_out[16:8] = Data[PC_in + 2];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:376: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                                 : ... In instance IC\n    instruction_out[24:16] = Data[PC_in + 1];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:377: Bit extraction of array[63:0] requires 6 bit index, not 64 bits.\n                                                                                 : ... In instance IC\n    instruction_out[31:24] = Data[PC_in];\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/130536678/Pipelined-Only/ARM_CPU.v:377: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                                 : ... In instance IC\n    instruction_out[31:24] = Data[PC_in];\n                           ^\n%Error: Exiting due to 39 warning(s)\n'
module ARM_CPU
(
  input RESET,
  input CLOCK,
  input [31:0] IC,
  input [63:0] mem_data_in,
  output reg [63:0] PC,
  output [63:0] mem_address_out,
  output [63:0] mem_data_out,
  output control_memwrite_out,
  output control_memread_out
);

  always @(posedge CLOCK) begin
    if (PC === 64'bx) begin
    	PC <= 0;
   	end else if (PCSrc_wire == 1'b1) begin
      PC <= jump_PC_wire;
    end else begin
      PC <= PC + 4;
  end


  end


  wire PCSrc_wire;
  wire [63:0] jump_PC_wire;
  wire [63:0] IFID_PC;
  wire [31:0] IFID_IC;
  IFID cache1 (CLOCK, PC, IC, IFID_PC, IFID_IC);



  wire [1:0] CONTROL_aluop;
  wire CONTROL_alusrc;
  wire CONTROL_isZeroBranch;
  wire CONTROL_isUnconBranch;
  wire CONTROL_memRead;
  wire CONTROL_memwrite;
  wire CONTROL_regwrite;
  wire CONTROL_mem2reg;
  ARM_Control unit1 (IFID_IC[31:21], CONTROL_aluop, CONTROL_alusrc, CONTROL_isZeroBranch, CONTROL_isUnconBranch, CONTROL_memRead, CONTROL_memwrite, CONTROL_regwrite, CONTROL_mem2reg);

  wire [4:0] reg2_wire;
  ID_Mux unit2(IFID_IC[20:16], IFID_IC[4:0], IFID_IC[28], reg2_wire);

  wire [63:0] reg1_data, reg2_data;
  wire MEMWB_regwrite;
  wire [4:0] MEMWB_write_reg;
  wire [63:0] write_reg_data;
  Registers unit3(CLOCK, IFID_IC[9:5], reg2_wire, MEMWB_write_reg, write_reg_data, MEMWB_regwrite, reg1_data, reg2_data);

  wire [63:0] sign_extend_wire;
  SignExtend unit4 (IFID_IC, sign_extend_wire);

  wire [1:0] IDEX_aluop;
  wire IDEX_alusrc;
  wire IDEX_isZeroBranch;
  wire IDEX_isUnconBranch;
  wire IDEX_memRead;
  wire IDEX_memwrite;
  wire IDEX_regwrite;
  wire IDEX_mem2reg;
  wire [63:0] IDEX_reg1_data;
  wire [63:0] IDEX_reg2_data;
  wire [63:0] IDEX_PC;
  wire [63:0] IDEX_sign_extend;
  wire [10:0] IDEX_alu_control;
  wire [4:0] IDEX_write_reg;
  IDEX cache2 (CLOCK, CONTROL_aluop, CONTROL_alusrc, CONTROL_isZeroBranch, CONTROL_isUnconBranch, CONTROL_memRead, CONTROL_memwrite, CONTROL_regwrite, CONTROL_mem2reg, IFID_PC, reg1_data, reg2_data, sign_extend_wire, IFID_IC[31:21], IFID_IC[4:0], IDEX_aluop, IDEX_alusrc, IDEX_isZeroBranch, IDEX_isUnconBranch, IDEX_memRead, IDEX_memwrite, IDEX_regwrite, IDEX_mem2reg, IDEX_PC, IDEX_reg1_data, IDEX_reg2_data, IDEX_sign_extend, IDEX_alu_control, IDEX_write_reg);



  wire [63:0] shift_left_wire;
  wire [63:0] PC_jump;
  wire jump_is_zero;
  Shift_Left unit5 (IDEX_sign_extend, shift_left_wire);
  ALU unit6 (IDEX_PC, shift_left_wire, 4'b0010, PC_jump, jump_is_zero);

  wire [3:0] alu_main_control_wire;
  wire [63:0] alu_data2_wire;
  wire alu_main_is_zero;
  wire [63:0] alu_main_result;
  ALU_Control unit7(IDEX_aluop, IDEX_alu_control, alu_main_control_wire);
  ALU_Mux mux3(IDEX_reg2_data, IDEX_sign_extend, IDEX_alusrc, alu_data2_wire);
  ALU main_alu(IDEX_reg1_data, alu_data2_wire, alu_main_control_wire, alu_main_result, alu_main_is_zero);

  wire EXMEM_isZeroBranch;
  wire EXMEM_isUnconBranch;
  wire EXMEM_regwrite;
  wire EXMEM_mem2reg;
  wire EXMEM_alu_zero;
  wire [4:0] EXMEM_write_reg;
  EXMEM cache3(CLOCK, IDEX_isZeroBranch, IDEX_isUnconBranch, IDEX_memRead, IDEX_memwrite, IDEX_regwrite, IDEX_mem2reg, PC_jump, alu_main_is_zero, alu_main_result, IDEX_reg2_data, IDEX_write_reg, EXMEM_isZeroBranch, EXMEM_isUnconBranch, control_memread_out, control_memwrite_out, EXMEM_regwrite, EXMEM_mem2reg, jump_PC_wire, EXMEM_alu_zero, mem_address_out, mem_data_out, EXMEM_write_reg);



  Branch unit8 (EXMEM_isUnconBranch, EXMEM_isZeroBranch, EXMEM_alu_zero, PCSrc_wire);

  wire MEMWB_mem2reg;
  wire [63:0] MEMWB_address;
  wire [63:0] MEMWB_read_data;
  MEMWB cache4(CLOCK, mem_address_out, mem_data_in, EXMEM_write_reg, EXMEM_regwrite, EXMEM_mem2reg, MEMWB_address, MEMWB_read_data, MEMWB_write_reg, MEMWB_regwrite, MEMWB_mem2reg);



  WB_Mux unit9 (MEMWB_address, MEMWB_read_data, MEMWB_mem2reg, write_reg_data);
endmodule
module ARM_CPU
(
  input RESET,
  input CLOCK,
  input [31:0] IC,
  input [63:0] mem_data_in,
  output reg [63:0] PC,
  output [63:0] mem_address_out,
  output [63:0] mem_data_out,
  output control_memwrite_out,
  output control_memread_out
);


  always @(posedge CLOCK) begin
    if (PC === 64'bx) begin
    	PC <= 0;
   	end else if (PCSrc_wire == 1'b1) begin
      PC <= jump_PC_wire;
    end else begin
      PC <= PC + 4;
  end


  end


  wire PCSrc_wire;
  wire [63:0] jump_PC_wire;
  wire [63:0] IFID_PC;
  wire [31:0] IFID_IC;
  IFID cache1 (CLOCK, PC, IC, IFID_PC, IFID_IC);



  wire [1:0] CONTROL_aluop;
  wire CONTROL_alusrc;
  wire CONTROL_isZeroBranch;
  wire CONTROL_isUnconBranch;
  wire CONTROL_memRead;
  wire CONTROL_memwrite;
  wire CONTROL_regwrite;
  wire CONTROL_mem2reg;
  ARM_Control unit1 (IFID_IC[31:21], CONTROL_aluop, CONTROL_alusrc, CONTROL_isZeroBranch, CONTROL_isUnconBranch, CONTROL_memRead, CONTROL_memwrite, CONTROL_regwrite, CONTROL_mem2reg);

  wire [4:0] reg2_wire;
  ID_Mux unit2(IFID_IC[20:16], IFID_IC[4:0], IFID_IC[28], reg2_wire);

  wire [63:0] reg1_data, reg2_data;
  wire MEMWB_regwrite;
  wire [4:0] MEMWB_write_reg;
  wire [63:0] write_reg_data;
  Registers unit3(CLOCK, IFID_IC[9:5], reg2_wire, MEMWB_write_reg, write_reg_data, MEMWB_regwrite, reg1_data, reg2_data);

  wire [63:0] sign_extend_wire;
  SignExtend unit4 (IFID_IC, sign_extend_wire);

  wire [1:0] IDEX_aluop;
  wire IDEX_alusrc;
  wire IDEX_isZeroBranch;
  wire IDEX_isUnconBranch;
  wire IDEX_memRead;
  wire IDEX_memwrite;
  wire IDEX_regwrite;
  wire IDEX_mem2reg;
  wire [63:0] IDEX_reg1_data;
  wire [63:0] IDEX_reg2_data;
  wire [63:0] IDEX_PC;
  wire [63:0] IDEX_sign_extend;
  wire [10:0] IDEX_alu_control;
  wire [4:0] IDEX_write_reg;
  IDEX cache2 (CLOCK, CONTROL_aluop, CONTROL_alusrc, CONTROL_isZeroBranch, CONTROL_isUnconBranch, CONTROL_memRead, CONTROL_memwrite, CONTROL_regwrite, CONTROL_mem2reg, IFID_PC, reg1_data, reg2_data, sign_extend_wire, IFID_IC[31:21], IFID_IC[4:0], IDEX_aluop, IDEX_alusrc, IDEX_isZeroBranch, IDEX_isUnconBranch, IDEX_memRead, IDEX_memwrite, IDEX_regwrite, IDEX_mem2reg, IDEX_PC, IDEX_reg1_data, IDEX_reg2_data, IDEX_sign_extend, IDEX_alu_control, IDEX_write_reg);



  wire [63:0] shift_left_wire;
  wire [63:0] PC_jump;
  wire jump_is_zero;
  Shift_Left unit5 (IDEX_sign_extend, shift_left_wire);
  ALU unit6 (IDEX_PC, shift_left_wire, 4'b0010, PC_jump, jump_is_zero);

  wire [3:0] alu_main_control_wire;
  wire [63:0] alu_data2_wire;
  wire alu_main_is_zero;
  wire [63:0] alu_main_result;
  ALU_Control unit7(IDEX_aluop, IDEX_alu_control, alu_main_control_wire);
  ALU_Mux mux3(IDEX_reg2_data, IDEX_sign_extend, IDEX_alusrc, alu_data2_wire);
  ALU main_alu(IDEX_reg1_data, alu_data2_wire, alu_main_control_wire, alu_main_result, alu_main_is_zero);

  wire EXMEM_isZeroBranch;
  wire EXMEM_isUnconBranch;
  wire EXMEM_regwrite;
  wire EXMEM_mem2reg;
  wire EXMEM_alu_zero;
  wire [4:0] EXMEM_write_reg;
  EXMEM cache3(CLOCK, IDEX_isZeroBranch, IDEX_isUnconBranch, IDEX_memRead, IDEX_memwrite, IDEX_regwrite, IDEX_mem2reg, PC_jump, alu_main_is_zero, alu_main_result, IDEX_reg2_data, IDEX_write_reg, EXMEM_isZeroBranch, EXMEM_isUnconBranch, control_memread_out, control_memwrite_out, EXMEM_regwrite, EXMEM_mem2reg, jump_PC_wire, EXMEM_alu_zero, mem_address_out, mem_data_out, EXMEM_write_reg);



  Branch unit8 (EXMEM_isUnconBranch, EXMEM_isZeroBranch, EXMEM_alu_zero, PCSrc_wire);

  wire MEMWB_mem2reg;
  wire [63:0] MEMWB_address;
  wire [63:0] MEMWB_read_data;
  MEMWB cache4(CLOCK, mem_address_out, mem_data_in, EXMEM_write_reg, EXMEM_regwrite, EXMEM_mem2reg, MEMWB_address, MEMWB_read_data, MEMWB_write_reg, MEMWB_regwrite, MEMWB_mem2reg);



  WB_Mux unit9 (MEMWB_address, MEMWB_read_data, MEMWB_mem2reg, write_reg_data);
endmodule