data/full_repos/permissive/201488448/2_circuits/2_sequential/25_countbcd.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/25_countbcd.v:42: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                                 : ... In instance top_module.c1000\n            q <= 4'd0;\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/25_countbcd.v:45: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                                 : ... In instance top_module.c1000\n                q <= 4'd0;\n                ^\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/2_sequential/25_countbcd.v:47: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                                 : ... In instance top_module.c1000\n                q <= q + 1'b1;\n                ^\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input reset,
    output [3:1] ena,
    output [15:0] q);

    bcd c1(
        .clk(clk),
        .reset(reset),
        .enable(1'b1),
        .q(q[3:0])
    );
    
    bcd c10(
        .clk(clk),
        .reset(reset),
        .enable(q[3:0]==9),
        .q(q[7:4])
    );
    
    bcd c100(
        .clk(clk),
        .reset(reset),
        .enable(q[3:0]==9 && q[7:4]==9),
        .q(q[11:8])
    );
    
    bcd c1000(
        .clk(clk),
        .reset(reset),
        .enable(q[11:8]==9 && q[3:0]==9 && q[7:4]==9),
        .q(q[15:12])
    );
    
    assign	ena = {q[11:8]==9 && q[3:0]==9 && q[7:4]==9, q[3:0]==9 && q[7:4]==9, q[3:0]==9};
    
endmodule
module top_module (
    input clk,
    input reset,
    output [3:1] ena,
    output [15:0] q);


    bcd c1(
        .clk(clk),
        .reset(reset),
        .enable(1'b1),
        .q(q[3:0])
    );
    
    bcd c10(
        .clk(clk),
        .reset(reset),
        .enable(q[3:0]==9),
        .q(q[7:4])
    );
    
    bcd c100(
        .clk(clk),
        .reset(reset),
        .enable(q[3:0]==9 && q[7:4]==9),
        .q(q[11:8])
    );
    
    bcd c1000(
        .clk(clk),
        .reset(reset),
        .enable(q[11:8]==9 && q[3:0]==9 && q[7:4]==9),
        .q(q[15:12])
    );
    
    assign	ena = {q[11:8]==9 && q[3:0]==9 && q[7:4]==9, q[3:0]==9 && q[7:4]==9, q[3:0]==9};
    
endmodule