data/full_repos/permissive/136510272/projects/07_reduced86/main.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/07_reduced86/main.v:14: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk       = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/07_reduced86/main.v:15: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk50       = ~clk50;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/07_reduced86/main.v:16: Unsupported: Ignoring delay on this delayed statement.\nalways #2 clk25       = ~clk25;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/07_reduced86/main.v:19: Unsupported: Ignoring delay on this delayed statement.\ninitial #2 ps2_data = 8\'h76;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/07_reduced86/main.v:20: Unsupported: Ignoring delay on this delayed statement.\ninitial #2 ps2_data_clk = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/07_reduced86/main.v:21: Unsupported: Ignoring delay on this delayed statement.\ninitial #4 ps2_data_clk = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/136510272/projects/07_reduced86/main.v:29: Unsupported: Ignoring delay on this delayed statement.\ninitial begin clk = 1; #2000 $finish; end\n                       ^\n%Error: data/full_repos/permissive/136510272/projects/07_reduced86/main.v:30: Unsupported or unknown PLI call: $dumpfile\ninitial begin $dumpfile("main.vcd"); $dumpvars(0, main); end\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/07_reduced86/main.v:30: Unsupported or unknown PLI call: $dumpvars\ninitial begin $dumpfile("main.vcd"); $dumpvars(0, main); end\n                                     ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;



reg clk = 1'b0;
reg clk25 = 1'b0;
reg clk50 = 1'b0;

reg [7:0] ps2_data = 8'h00;
reg       ps2_data_clk = 1'b0;

always #0.5 clk       = ~clk;
always #1 clk50       = ~clk50;
always #2 clk25       = ~clk25;


initial #2 ps2_data = 8'h76;
initial #2 ps2_data_clk = 1'b1;
initial #4 ps2_data_clk = 1'b0;



initial begin clk = 1; #2000 $finish; end
initial begin $dumpfile("main.vcd"); $dumpvars(0, main); end



reg  [7:0]  i;
wire [7:0]  o;
wire [15:0] a;
wire        w; 
reg  [1:0]  flw = 2'b00; 


reg [ 7:0] memory[65536];




initial begin $readmemh("init/ram.hex",  memory, 16'h0000); end
initial begin $readmemh("init/bios.hex", memory, 16'hC000); end 

always @(posedge clk) begin


    i <= memory[ a ];
    

    if (w) memory[ a ] <= o;
    
end

wire  [15:0] port_addr;
wire  [15:0] port_in;
wire  [15:0] port_out;
wire         port_bit;
wire         port_clk;
wire         port_read;
wire  [10:0] cursor;


port_controller PortCTRL(

    clk50,
    port_addr,
    port_in,
    port_out,
    port_bit,
    port_clk,
    port_read,
    

    ps2_data,
    ps2_data_clk,
    
    cursor
);


cpu CPU(1'b0, 
        clk, clk25, i, o, a, w, 
        port_addr, port_in, port_out, port_bit, port_clk, port_read);
    
endmodule
module main;




reg clk = 1'b0;
reg clk25 = 1'b0;
reg clk50 = 1'b0;

reg [7:0] ps2_data = 8'h00;
reg       ps2_data_clk = 1'b0;

always #0.5 clk       = ~clk;
always #1 clk50       = ~clk50;
always #2 clk25       = ~clk25;


initial #2 ps2_data = 8'h76;
initial #2 ps2_data_clk = 1'b1;
initial #4 ps2_data_clk = 1'b0;



initial begin clk = 1; #2000 $finish; end
initial begin $dumpfile("main.vcd"); $dumpvars(0, main); end



reg  [7:0]  i;
wire [7:0]  o;
wire [15:0] a;
wire        w; 
reg  [1:0]  flw = 2'b00; 


reg [ 7:0] memory[65536];




initial begin $readmemh("init/ram.hex",  memory, 16'h0000); end
initial begin $readmemh("init/bios.hex", memory, 16'hC000); end 

always @(posedge clk) begin


    i <= memory[ a ];
    

    if (w) memory[ a ] <= o;
    
end

wire  [15:0] port_addr;
wire  [15:0] port_in;
wire  [15:0] port_out;
wire         port_bit;
wire         port_clk;
wire         port_read;
wire  [10:0] cursor;


port_controller PortCTRL(

    clk50,
    port_addr,
    port_in,
    port_out,
    port_bit,
    port_clk,
    port_read,
    

    ps2_data,
    ps2_data_clk,
    
    cursor
);


cpu CPU(1'b0, 
        clk, clk25, i, o, a, w, 
        port_addr, port_in, port_out, port_bit, port_clk, port_read);
    
endmodule