data/full_repos/permissive/114421971/clb_n5ffmux/top.v
 line:53: before: "="
1: b"%Error: data/full_repos/permissive/114421971/clb_n5ffmux/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n                                      ^~\n%Error: data/full_repos/permissive/114421971/clb_n5ffmux/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n        ^~\n%Error: data/full_repos/permissive/114421971/clb_n5ffmux/top.v:53: syntax error, unexpected '=', expecting ',' or ';'\n    wire lutno5 [3:0] = {lutdo5, lutco5, lutbo5, lutao5};\n                      ^\n%Error: Exiting due to 3 error(s)\n"
module roi(input clk, input [255:0] din, output [255:0] dout);
    clb_N5FFMUX  # (.LOC("SLICE_X22Y100"), .N(0))
        clb_N5FFMUX_0 (.clk(clk), .din(din[  0 +: 8]), .dout(dout[0 +: 8]));
    clb_N5FFMUX  # (.LOC("SLICE_X22Y101"), .N(1))
        clb_N5FFMUX_1 (.clk(clk), .din(din[  8 +: 8]), .dout(dout[8 +: 8]));
    clb_N5FFMUX  # (.LOC("SLICE_X22Y102"), .N(2))
        clb_N5FFMUX_2 (.clk(clk), .din(din[  16 +: 8]), .dout(dout[16 +: 8]));
    clb_N5FFMUX  # (.LOC("SLICE_X22Y103"), .N(3))
        clb_N5FFMUX_3 (.clk(clk), .din(din[  24 +: 8]), .dout(dout[24 +: 8]));
endmodule
module roi(input clk, input [255:0] din, output [255:0] dout);

    clb_N5FFMUX  # (.LOC("SLICE_X22Y100"), .N(0))
        clb_N5FFMUX_0 (.clk(clk), .din(din[  0 +: 8]), .dout(dout[0 +: 8]));
    clb_N5FFMUX  # (.LOC("SLICE_X22Y101"), .N(1))
        clb_N5FFMUX_1 (.clk(clk), .din(din[  8 +: 8]), .dout(dout[8 +: 8]));
    clb_N5FFMUX  # (.LOC("SLICE_X22Y102"), .N(2))
        clb_N5FFMUX_2 (.clk(clk), .din(din[  16 +: 8]), .dout(dout[16 +: 8]));
    clb_N5FFMUX  # (.LOC("SLICE_X22Y103"), .N(3))
        clb_N5FFMUX_3 (.clk(clk), .din(din[  24 +: 8]), .dout(dout[24 +: 8]));
endmodule