data/full_repos/permissive/211866113/ASTRA_RAM_BIST_top_module.v
 line:210: before: "+"
1: b'%Error: data/full_repos/permissive/211866113/ASTRA_RAM_BIST_top_module.v:1: Cannot find include file: ASTRA_RAM_BIST_MAIN_module.v\n`include "ASTRA_RAM_BIST_MAIN_module.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/ASTRA_RAM_BIST_MAIN_module.v\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/ASTRA_RAM_BIST_MAIN_module.v.v\n             data/full_repos/permissive/211866113,data/full_repos/permissive/211866113/ASTRA_RAM_BIST_MAIN_module.v.sv\n             ASTRA_RAM_BIST_MAIN_module.v\n             ASTRA_RAM_BIST_MAIN_module.v.v\n             ASTRA_RAM_BIST_MAIN_module.v.sv\n             obj_dir/ASTRA_RAM_BIST_MAIN_module.v\n             obj_dir/ASTRA_RAM_BIST_MAIN_module.v.v\n             obj_dir/ASTRA_RAM_BIST_MAIN_module.v.sv\n%Error: data/full_repos/permissive/211866113/ASTRA_RAM_BIST_top_module.v:2: Cannot find include file: word_gen.v\n`include "word_gen.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/211866113/ASTRA_RAM_BIST_top_module.v:3: Cannot find include file: RAM.v\n`include "RAM.v" \n         ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ASTRA_RAM_BIST_top_module.v:59: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/211866113/ASTRA_RAM_BIST_top_module.v:63: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("ASTRA_RAM_BIST_test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/211866113/ASTRA_RAM_BIST_top_module.v:64: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0);  \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ASTRA_RAM_BIST_top_module.v:74: Unsupported: Ignoring delay on this delayed statement.\n            #3 gen_next = FALSE;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ASTRA_RAM_BIST_top_module.v:77: Unsupported: Ignoring delay on this delayed statement.\n            #1 WE = FALSE;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ASTRA_RAM_BIST_top_module.v:79: Unsupported: Ignoring delay on this delayed statement.\n            #1 ADDRESS++;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ASTRA_RAM_BIST_top_module.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #10  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/211866113/ASTRA_RAM_BIST_top_module.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #250 $display("Simulation STOP. :: time is %0t", $time);\n        ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n'
module ASTRA_RAM_BIST_tester ();
    parameter FALSE = 1'b0;
    parameter TRUE = 1'b1;

    integer i;

    reg     clk = 1'b0;


    reg        gen_next;
    wire [2:0] DATA_GEN;


    reg [1:0]  ADDRESS;
    wire [1:0] RAM_ADDRESS;
    wire [2:0] DATA;
    wire [2:0] OUT;


    reg        CS, WE, OE;
    wire       CS_RAM, WE_RAM, OE_RAM;
    wire [2:0] DATA_BIST;


    reg         start;
    wire        MARCHING;
    wire        SUCCESS;
    wire [1:0]  BIST_ADDRESS;
    wire        CS_BIST, WE_BIST, OE_BIST;

    word_gen my_gen(gen_next, DATA_GEN);
    ASTRA_RAM_BIST my_BIST(clk, start, MARCHING, SUCCESS, BIST_ADDRESS,
        DATA_BIST, OUT, CS_BIST, WE_BIST, OE_BIST);
    RAM_module my_RAM(RAM_ADDRESS, DATA, OUT, CS_RAM, WE_RAM, OE_RAM);


    assign RAM_ADDRESS = (MARCHING) ? BIST_ADDRESS : ADDRESS;

    assign CS_RAM = (MARCHING) ? CS_BIST : CS;
    assign WE_RAM = (MARCHING) ? WE_BIST : WE;
    assign OE_RAM = (MARCHING) ? OE_BIST : OE;

    assign DATA = (MARCHING) ? DATA_BIST : DATA_GEN;

    always begin
	clk <= ~clk;
	#5;
    end

    initial begin
        $dumpfile("ASTRA_RAM_BIST_test.vcd");
        $dumpvars(0);


        i=0;
        OE = FALSE;
        WE = FALSE;
        CS = FALSE;
        gen_next = FALSE;
        ADDRESS = 2'b00;
        for (i = 0; i< 4; i = i + 1) begin
            #3 gen_next = FALSE;
            WE = TRUE;
            CS = TRUE;
            #1 WE = FALSE;
            CS = FALSE;
            #1 ADDRESS++;
            gen_next = TRUE;
        end
        #10

        start = TRUE;
        start = FALSE;
        $display("BIST START INITIATED. :: time is %0t", $time);



        #250 $display("Simulation STOP. :: time is %0t", $time);
        $finish;
    end

endmodule
module ASTRA_RAM_BIST_tester ();

    parameter FALSE = 1'b0;
    parameter TRUE = 1'b1;

    integer i;

    reg     clk = 1'b0;


    reg        gen_next;
    wire [2:0] DATA_GEN;


    reg [1:0]  ADDRESS;
    wire [1:0] RAM_ADDRESS;
    wire [2:0] DATA;
    wire [2:0] OUT;


    reg        CS, WE, OE;
    wire       CS_RAM, WE_RAM, OE_RAM;
    wire [2:0] DATA_BIST;


    reg         start;
    wire        MARCHING;
    wire        SUCCESS;
    wire [1:0]  BIST_ADDRESS;
    wire        CS_BIST, WE_BIST, OE_BIST;

    word_gen my_gen(gen_next, DATA_GEN);
    ASTRA_RAM_BIST my_BIST(clk, start, MARCHING, SUCCESS, BIST_ADDRESS,
        DATA_BIST, OUT, CS_BIST, WE_BIST, OE_BIST);
    RAM_module my_RAM(RAM_ADDRESS, DATA, OUT, CS_RAM, WE_RAM, OE_RAM);


    assign RAM_ADDRESS = (MARCHING) ? BIST_ADDRESS : ADDRESS;

    assign CS_RAM = (MARCHING) ? CS_BIST : CS;
    assign WE_RAM = (MARCHING) ? WE_BIST : WE;
    assign OE_RAM = (MARCHING) ? OE_BIST : OE;

    assign DATA = (MARCHING) ? DATA_BIST : DATA_GEN;

    always begin
	clk <= ~clk;
	#5;
    end

    initial begin
        $dumpfile("ASTRA_RAM_BIST_test.vcd");
        $dumpvars(0);


        i=0;
        OE = FALSE;
        WE = FALSE;
        CS = FALSE;
        gen_next = FALSE;
        ADDRESS = 2'b00;
        for (i = 0; i< 4; i = i + 1) begin
            #3 gen_next = FALSE;
            WE = TRUE;
            CS = TRUE;
            #1 WE = FALSE;
            CS = FALSE;
            #1 ADDRESS++;
            gen_next = TRUE;
        end
        #10

        start = TRUE;
        start = FALSE;
        $display("BIST START INITIATED. :: time is %0t", $time);



        #250 $display("Simulation STOP. :: time is %0t", $time);
        $finish;
    end

endmodule