data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/multiplier.v
1: b'%Warning-WIDTH: data/full_repos/permissive/200650987/src/verilog/discarded/CPU/myCPU/multiplier.v:28: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                                    : ... In instance mul\n    assign result = C + S + cin;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module wallace_tree(
    input  wire [16:0] x,
    input  wire [14:0] ci,
    output wire [14:0] co,
    output wire        C,
    output wire        S
);
    wire [14:0] s;
    full_adder adder00(x [ 0], x [ 1], x [ 2], co[ 0], s[ 0]);
    full_adder adder01(x [ 3], x [ 4], x [ 5], co[ 1], s[ 1]);
    full_adder adder02(x [ 6], x [ 7], x [ 8], co[ 2], s[ 2]);
    full_adder adder03(x [ 9], x [10], x [11], co[ 3], s[ 3]);
    full_adder adder04(x [12], x [13], x [14], co[ 4], s[ 4]);
    full_adder adder05(x [15], x [16], 1'b0  , co[ 5], s[ 5]);
    full_adder adder06(s [ 0], s [ 1], s [ 2], co[ 6], s[ 6]);
    full_adder adder07(s [ 3], s [ 4], s [ 5], co[ 7], s[ 7]);
    full_adder adder08(ci[ 0], ci[ 1], ci[ 2], co[ 8], s[ 8]);
    full_adder adder09(ci[ 3], ci[ 4], ci[ 5], co[ 9], s[ 9]);
    full_adder adder10(s [ 6], s [ 7], s [ 8], co[10], s[10]);
    full_adder adder11(s [ 9], ci[ 6], ci[ 7], co[11], s[11]);
    full_adder adder12(s [10], s [11], ci[ 8], co[12], s[12]);
    full_adder adder13(ci[ 9], ci[10], ci[11], co[13], s[13]);
    full_adder adder14(s [12], s [13], ci[12], co[14], s[14]);
    full_adder adder15(s [14], ci[13], ci[14], C     , S    );
endmodule
module wallace_tree(
    input  wire [16:0] x,
    input  wire [14:0] ci,
    output wire [14:0] co,
    output wire        C,
    output wire        S
);

    wire [14:0] s;
    full_adder adder00(x [ 0], x [ 1], x [ 2], co[ 0], s[ 0]);
    full_adder adder01(x [ 3], x [ 4], x [ 5], co[ 1], s[ 1]);
    full_adder adder02(x [ 6], x [ 7], x [ 8], co[ 2], s[ 2]);
    full_adder adder03(x [ 9], x [10], x [11], co[ 3], s[ 3]);
    full_adder adder04(x [12], x [13], x [14], co[ 4], s[ 4]);
    full_adder adder05(x [15], x [16], 1'b0  , co[ 5], s[ 5]);
    full_adder adder06(s [ 0], s [ 1], s [ 2], co[ 6], s[ 6]);
    full_adder adder07(s [ 3], s [ 4], s [ 5], co[ 7], s[ 7]);
    full_adder adder08(ci[ 0], ci[ 1], ci[ 2], co[ 8], s[ 8]);
    full_adder adder09(ci[ 3], ci[ 4], ci[ 5], co[ 9], s[ 9]);
    full_adder adder10(s [ 6], s [ 7], s [ 8], co[10], s[10]);
    full_adder adder11(s [ 9], ci[ 6], ci[ 7], co[11], s[11]);
    full_adder adder12(s [10], s [11], ci[ 8], co[12], s[12]);
    full_adder adder13(ci[ 9], ci[10], ci[11], co[13], s[13]);
    full_adder adder14(s [12], s [13], ci[12], co[14], s[14]);
    full_adder adder15(s [14], ci[13], ci[14], C     , S    );
endmodule