data/full_repos/permissive/215901856/Testing/debouncer.v
data/verilator_xmls/11117c5c-36c0-41f5-bfe3-57d604564eaa.xml
module debouncer(clk, rst, in_n, out_c);
  input clk, rst, in_n;
  output out_c;

  reg [2:0] mid;

  always@(posedge clk or posedge rst)
    begin
      if(rst)
        begin
          mid <= 3'b0;
        end
      else
        begin
          mid <= {mid[1:0], in_n};
        end
    end

  assign out_c = (~mid[2]) & mid[1];

endmodule
module debouncer(clk, rst, in_n, out_c);

  input clk, rst, in_n;
  output out_c;

  reg [2:0] mid;

  always@(posedge clk or posedge rst)
    begin
      if(rst)
        begin
          mid <= 3'b0;
        end
      else
        begin
          mid <= {mid[1:0], in_n};
        end
    end

  assign out_c = (~mid[2]) & mid[1];

endmodule