data/full_repos/permissive/147265957/src/hellodisp.v
 line:29: before: "/"
data/verilator_xmls/05e5dd28-0157-4d43-b322-8814d5670fad.xml
module hellodisp(
    clk, sdpsel, sdpdisp
);
    input clk;
    output reg [7:0] sdpsel;
    output reg [7:0] sdpdisp;
    reg [2:0] curr_dig;
    initial curr_dig = 0;
    always @(posedge clk) begin

        curr_dig = curr_dig + 1;
        if(curr_dig > 4) begin
            curr_dig = 0;
        end
        sdpsel = 8'b11111111;
        sdpsel[curr_dig] = 0;

        case(curr_dig)
            0: sdpdisp = 8'b10100011;
            1: sdpdisp = 8'b11000111;
            2: sdpdisp = 8'b11000111;
            3: sdpdisp = 8'b10000110;
            4: sdpdisp = 8'b10001001;
        endcase
    end
endmodule
module hellodisp(
    clk, sdpsel, sdpdisp
);

    input clk;
    output reg [7:0] sdpsel;
    output reg [7:0] sdpdisp;
    reg [2:0] curr_dig;
    initial curr_dig = 0;
    always @(posedge clk) begin

        curr_dig = curr_dig + 1;
        if(curr_dig > 4) begin
            curr_dig = 0;
        end
        sdpsel = 8'b11111111;
        sdpsel[curr_dig] = 0;

        case(curr_dig)
            0: sdpdisp = 8'b10100011;
            1: sdpdisp = 8'b11000111;
            2: sdpdisp = 8'b11000111;
            3: sdpdisp = 8'b10000110;
            4: sdpdisp = 8'b10001001;
        endcase
    end
endmodule