data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v
None: at end of input
1: b'%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:1: Cannot find include file: cypress.v\n`include "cypress.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out,data/full_repos/permissive/193054270/cypress.v\n             data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out,data/full_repos/permissive/193054270/cypress.v.v\n             data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out,data/full_repos/permissive/193054270/cypress.v.sv\n             cypress.v\n             cypress.v.v\n             cypress.v.sv\n             obj_dir/cypress.v\n             obj_dir/cypress.v.v\n             obj_dir/cypress.v.sv\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:65: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:65: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                   ^\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:65: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:65: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:66: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:66: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:66: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:67: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:67: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:67: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:68: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:69: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:69: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:69: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:70: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:70: Define or directive not defined: \'`CS_A0_SRC___F0\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:70: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:71: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:71: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:71: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:72: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:73: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:73: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:73: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:74: Define or directive not defined: \'`CS_SHFT_OP___SL\'\n    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:74: Define or directive not defined: \'`CS_A0_SRC__ALU\'\n    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:74: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:75: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:75: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:75: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:76: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:77: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:77: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:77: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:78: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:78: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:78: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:79: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:79: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:79: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:80: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:81: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:81: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:81: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:82: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:82: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:82: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:83: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/dma_in/dma_in.cydsn/led_out/led_out.v:83: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module led_out (
	input   clock,
    input   sync,
	output  led_out,
    output  dma
);

localparam PG_IDLE  = 3'b000;
localparam PG_COPY  = 3'b001;
localparam PG_SHIFT = 3'b010;
localparam PG_WAIT  = 3'b011;

reg[2:0] pg_state;
reg[3:0] bit_count;

wire f0_not_full;
wire f0_is_empty;

reg sync_edge;
reg shift_out;
reg led_out_reg;

always @(posedge clock)
begin
    case(pg_state)
    PG_IDLE:
    begin
        if(~f0_is_empty)
            pg_state <= PG_COPY;
    end
    
    PG_COPY:
    begin
        bit_count <= 4'd0;
        pg_state <= PG_SHIFT;
        sync_edge <= sync;
    end
    
    PG_SHIFT:
    begin
        led_out_reg <= shift_out;
        bit_count <= bit_count + 4'd1;
        pg_state <= (bit_count[3]) ? PG_IDLE : PG_WAIT;
    end
    
    PG_WAIT:
    begin
        if(sync_edge != sync)
        begin
            sync_edge <= sync;
            pg_state <= PG_SHIFT;
        end
    end

    endcase
end

assign led_out = led_out_reg;
assign dma = f0_not_full;

cy_psoc3_dp8 #(.cy_dpconfig_a(
{
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    8'hFF, 8'h00,
    8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
    `SC_SI_A_DEFSI,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
    `SC_CMP0_NOCHN,
    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}
)) dp(
    .reset(1'b0),
    .clk(clock),
    .cs_addr(pg_state),
    .route_si(1'b0),
    .route_ci(1'b0),
    .f0_load(1'b0),
    .f1_load(1'b0),
    .d0_load(1'b0),
    .d1_load(1'b0),
    .so(shift_out),
    .f0_bus_stat(f0_not_full),
    .f0_blk_stat(f0_is_empty)
);

endmodule
module led_out (
	input   clock,
    input   sync,
	output  led_out,
    output  dma
);


localparam PG_IDLE  = 3'b000;
localparam PG_COPY  = 3'b001;
localparam PG_SHIFT = 3'b010;
localparam PG_WAIT  = 3'b011;

reg[2:0] pg_state;
reg[3:0] bit_count;

wire f0_not_full;
wire f0_is_empty;

reg sync_edge;
reg shift_out;
reg led_out_reg;

always @(posedge clock)
begin
    case(pg_state)
    PG_IDLE:
    begin
        if(~f0_is_empty)
            pg_state <= PG_COPY;
    end
    
    PG_COPY:
    begin
        bit_count <= 4'd0;
        pg_state <= PG_SHIFT;
        sync_edge <= sync;
    end
    
    PG_SHIFT:
    begin
        led_out_reg <= shift_out;
        bit_count <= bit_count + 4'd1;
        pg_state <= (bit_count[3]) ? PG_IDLE : PG_WAIT;
    end
    
    PG_WAIT:
    begin
        if(sync_edge != sync)
        begin
            sync_edge <= sync;
            pg_state <= PG_SHIFT;
        end
    end

    endcase
end

assign led_out = led_out_reg;
assign dma = f0_not_full;

cy_psoc3_dp8 #(.cy_dpconfig_a(
{
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    8'hFF, 8'h00,
    8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
    `SC_SI_A_DEFSI,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
    `SC_CMP0_NOCHN,
    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}
)) dp(
    .reset(1'b0),
    .clk(clock),
    .cs_addr(pg_state),
    .route_si(1'b0),
    .route_ci(1'b0),
    .f0_load(1'b0),
    .f1_load(1'b0),
    .d0_load(1'b0),
    .d1_load(1'b0),
    .so(shift_out),
    .f0_bus_stat(f0_not_full),
    .f0_blk_stat(f0_is_empty)
);

endmodule