data/full_repos/permissive/154590168/sim/tb/TB.v
 line:123: before: "begin"
1: b'%Error: data/full_repos/permissive/154590168/sim/tb/TB.v:183: Cannot find include file: stim.v\n`include "stim.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154590168/sim/tb,data/full_repos/permissive/154590168/stim.v\n             data/full_repos/permissive/154590168/sim/tb,data/full_repos/permissive/154590168/stim.v.v\n             data/full_repos/permissive/154590168/sim/tb,data/full_repos/permissive/154590168/stim.v.sv\n             stim.v\n             stim.v.v\n             stim.v.sv\n             obj_dir/stim.v\n             obj_dir/stim.v.v\n             obj_dir/stim.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/154590168/sim/tb/TB.v:96: Unsupported: Ignoring delay on this delayed statement.\n    clock = 0; #10;\n               ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/154590168/sim/tb/TB.v:97: Unsupported: Ignoring delay on this delayed statement.\n    clock = 1; #10;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/154590168/sim/tb/TB.v:101: Unsupported: Ignoring delay on this delayed statement.\n    reset = 0; #20;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/154590168/sim/tb/TB.v:102: Unsupported: Ignoring delay on this delayed statement.\n    reset = 1; #100;\n               ^\n%Error: data/full_repos/permissive/154590168/sim/tb/TB.v:123: syntax error, unexpected \'@\'\n    forever @(negedge clock) begin\n            ^\n%Error: data/full_repos/permissive/154590168/sim/tb/TB.v:133: syntax error, unexpected \';\', expecting IDENTIFIER\n    if (VERIFY) verify_data_memory;\n                                  ^\n%Error: data/full_repos/permissive/154590168/sim/tb/TB.v:141: syntax error, unexpected begin\nbegin\n^~~~~\n%Error: data/full_repos/permissive/154590168/sim/tb/TB.v:144: syntax error, unexpected $fwrite\n        if (i % 16 ==  0)   $fwrite(fp, "@%h", i);\n                            ^~~~~~~\n%Error: data/full_repos/permissive/154590168/sim/tb/TB.v:145: syntax error, unexpected $fwrite\n        if (i %  4 ==  0)   $fwrite(fp, " ");\n                            ^~~~~~~\n%Error: data/full_repos/permissive/154590168/sim/tb/TB.v:147: syntax error, unexpected $fwrite\n        if (i % 16 == 15)   $fwrite(fp, "\\n");\n                            ^~~~~~~\n%Error: data/full_repos/permissive/154590168/sim/tb/TB.v:157: syntax error, unexpected begin\nbegin\n^~~~~\n%Error: data/full_repos/permissive/154590168/sim/tb/TB.v:162: syntax error, unexpected \'=\', expecting IDENTIFIER\n            ng = 1;\n               ^\n%Error: data/full_repos/permissive/154590168/sim/tb/TB.v:166: syntax error, unexpected $display\n    if (ng) $display("[FAILED] RAM contents not matched.");\n            ^~~~~~~~\n%Error: Exiting due to 10 error(s), 4 warning(s)\n'
module TB;

`ifdef VERIFY
    localparam  VERIFY = 1;
`else
    localparam  VERIFY = 0;
`endif


reg         clock;
reg         reset;
wire[15:0]  pm_rdata;
wire[15:0]  pm_addr;
wire        pm_re;
wire        pm_we;
wire[15:0]  pm_wdata;
wire[7:0]   dm_rdata;
wire[15:0]  dm_addr;
wire        dm_re;
wire        dm_we;
wire[7:0]   dm_wdata;
wire[7:0]   io_rdata;
wire[7:0]   io_addr;
wire        io_re;
wire        io_we;
wire[7:0]   io_wdata;
reg         irq;
reg [15:0]  irq_addr;




CPU CPU (
    .clock      (clock      ),
    .reset      (reset      ),
    .pm_rdata   (pm_rdata   ),
    .pm_addr    (pm_addr    ),
    .pm_re      (pm_re      ),
    .pm_we      (pm_we      ),
    .pm_wdata   (pm_wdata   ),
    .dm_rdata   (dm_rdata   ),
    .dm_addr    (dm_addr    ),
    .dm_re      (dm_re      ),
    .dm_we      (dm_we      ),
    .dm_wdata   (dm_wdata   ),
    .io_rdata   (io_rdata   ),
    .io_addr    (io_addr    ),
    .io_re      (io_re      ),
    .io_we      (io_we      ),
    .io_wdata   (io_wdata   ),
    .irq        (irq        ),
    .irq_addr   (irq_addr   )
);


wire    i_pm_we = pm_we & (pm_addr[15:10] == 6'h00);

RAM #(.AW(10),.DW(16)) PM (
    .clock      (~clock     ),
    .addr       (pm_addr[9:0]),
    .we         (i_pm_we    ),
    .wdata      (pm_wdata   ),
    .rdata      (pm_rdata   )
);


wire    i_dm_we = dm_we & (dm_addr[15:10] == 6'h00);

RAM #(.AW(10),.DW(8)) DM (
    .clock      (~clock     ),
    .addr       (dm_addr[9:0]),
    .we         (i_dm_we    ),
    .wdata      (dm_wdata   ),
    .rdata      (dm_rdata   )
);


IoReg IOR (
    .clock      (clock      ),
    .reset      (reset      ),
    .addr       (io_addr    ),
    .we         (io_we      ),
    .wdata      (io_wdata   ),
    .rdata      (io_rdata   ),
    .ext_out    (           )
);




always begin
    clock = 0; #10;
    clock = 1; #10;
end

initial begin
    reset = 0; #20;
    reset = 1; #100;
    reset = 0;
end

initial begin
    irq = 0;
    irq_addr = 0;
end


initial begin
    $readmemh("PM.dat", PM.mem);
end





reg     sim_end;
initial begin
    sim_end = 0;
    forever @(negedge clock) begin
        if ((dm_addr == 16'hfeff) & dm_we & (dm_wdata == 8'hff)) begin
            sim_end = 1;
        end
    end
end
initial begin
    wait (sim_end);
    #100;
    save_data_memory;
    if (VERIFY) verify_data_memory;
    $finish;
end


task save_data_memory;
    integer     fp;
    reg [15:0]  i;
begin
    fp = $fopen("DM.dat", "w");
    for (i = 0; i < 2**10; i = i + 1) begin
        if (i % 16 ==  0)   $fwrite(fp, "@%h", i);
        if (i %  4 ==  0)   $fwrite(fp, " ");
                            $fwrite(fp, " %h", DM.mem[i]);
        if (i % 16 == 15)   $fwrite(fp, "\n");
    end
    $fclose(fp);
end
endtask


task verify_data_memory;
    reg [15:0]  i;
    reg         ng;
begin
    $readmemh("DM_exp.dat", DM_exp.mem);
    ng = 0;
    for (i = 0; i < 2**10; i = i + 1) begin
        if (DM.mem[i] !== DM_exp.mem[i]) begin
            ng = 1;
            $display("NG: @%h act=%h exp=%h", i, DM.mem[i], DM_exp.mem[i]);
        end
    end
    if (ng) $display("[FAILED] RAM contents not matched.");
    else    $display("[PASSED] All RAM contents matched.");
end
endtask


RAM #(.AW(10),.DW(8)) DM_exp (
    .clock  (1'b0   ),
    .addr   (10'h000),
    .we     (1'b0   ),
    .wdata  (8'h00  ),
    .rdata  (       )
);




`include "stim.v"

endmodule
module TB;


`ifdef VERIFY
    localparam  VERIFY = 1;
`else
    localparam  VERIFY = 0;
`endif


reg         clock;
reg         reset;
wire[15:0]  pm_rdata;
wire[15:0]  pm_addr;
wire        pm_re;
wire        pm_we;
wire[15:0]  pm_wdata;
wire[7:0]   dm_rdata;
wire[15:0]  dm_addr;
wire        dm_re;
wire        dm_we;
wire[7:0]   dm_wdata;
wire[7:0]   io_rdata;
wire[7:0]   io_addr;
wire        io_re;
wire        io_we;
wire[7:0]   io_wdata;
reg         irq;
reg [15:0]  irq_addr;




CPU CPU (
    .clock      (clock      ),
    .reset      (reset      ),
    .pm_rdata   (pm_rdata   ),
    .pm_addr    (pm_addr    ),
    .pm_re      (pm_re      ),
    .pm_we      (pm_we      ),
    .pm_wdata   (pm_wdata   ),
    .dm_rdata   (dm_rdata   ),
    .dm_addr    (dm_addr    ),
    .dm_re      (dm_re      ),
    .dm_we      (dm_we      ),
    .dm_wdata   (dm_wdata   ),
    .io_rdata   (io_rdata   ),
    .io_addr    (io_addr    ),
    .io_re      (io_re      ),
    .io_we      (io_we      ),
    .io_wdata   (io_wdata   ),
    .irq        (irq        ),
    .irq_addr   (irq_addr   )
);


wire    i_pm_we = pm_we & (pm_addr[15:10] == 6'h00);

RAM #(.AW(10),.DW(16)) PM (
    .clock      (~clock     ),
    .addr       (pm_addr[9:0]),
    .we         (i_pm_we    ),
    .wdata      (pm_wdata   ),
    .rdata      (pm_rdata   )
);


wire    i_dm_we = dm_we & (dm_addr[15:10] == 6'h00);

RAM #(.AW(10),.DW(8)) DM (
    .clock      (~clock     ),
    .addr       (dm_addr[9:0]),
    .we         (i_dm_we    ),
    .wdata      (dm_wdata   ),
    .rdata      (dm_rdata   )
);


IoReg IOR (
    .clock      (clock      ),
    .reset      (reset      ),
    .addr       (io_addr    ),
    .we         (io_we      ),
    .wdata      (io_wdata   ),
    .rdata      (io_rdata   ),
    .ext_out    (           )
);




always begin
    clock = 0; #10;
    clock = 1; #10;
end

initial begin
    reset = 0; #20;
    reset = 1; #100;
    reset = 0;
end

initial begin
    irq = 0;
    irq_addr = 0;
end


initial begin
    $readmemh("PM.dat", PM.mem);
end





reg     sim_end;
initial begin
    sim_end = 0;
    forever @(negedge clock) begin
        if ((dm_addr == 16'hfeff) & dm_we & (dm_wdata == 8'hff)) begin
            sim_end = 1;
        end
    end
end
initial begin
    wait (sim_end);
    #100;
    save_data_memory;
    if (VERIFY) verify_data_memory;
    $finish;
end


task save_data_memory;
    integer     fp;
    reg [15:0]  i;
begin
    fp = $fopen("DM.dat", "w");
    for (i = 0; i < 2**10; i = i + 1) begin
        if (i % 16 ==  0)   $fwrite(fp, "@%h", i);
        if (i %  4 ==  0)   $fwrite(fp, " ");
                            $fwrite(fp, " %h", DM.mem[i]);
        if (i % 16 == 15)   $fwrite(fp, "\n");
    end
    $fclose(fp);
end
endtask


task verify_data_memory;
    reg [15:0]  i;
    reg         ng;
begin
    $readmemh("DM_exp.dat", DM_exp.mem);
    ng = 0;
    for (i = 0; i < 2**10; i = i + 1) begin
        if (DM.mem[i] !== DM_exp.mem[i]) begin
            ng = 1;
            $display("NG: @%h act=%h exp=%h", i, DM.mem[i], DM_exp.mem[i]);
        end
    end
    if (ng) $display("[FAILED] RAM contents not matched.");
    else    $display("[PASSED] All RAM contents matched.");
end
endtask


RAM #(.AW(10),.DW(8)) DM_exp (
    .clock  (1'b0   ),
    .addr   (10'h000),
    .we     (1'b0   ),
    .wdata  (8'h00  ),
    .rdata  (       )
);




`include "stim.v"

endmodule