data/full_repos/permissive/211316121/lab3_1/sources_1/new/fullAdder.v
data/verilator_xmls/a60fd92d-d3e2-4e45-a4f3-762331341d87.xml
module fullAdder(
    input x,
    input y,
    input z,
    output s,
    output c
    );
    wire not_x,not_y,not_z;
    wire half_xy,not_half_xy;
    wire nand_h1,nand_h2,nand_f1,nand_f2;
    wire nand_c1,nand_c2;
    nand 
        NAH1(nand_h1,not_x,y),
        NAH2(nand_h2,x,not_y),
        NAH3(half_xy,nand_h1,nand_h2),
        NAF1(nand_f1,not_half_xy,z),
        NAF2(nand_f2,half_xy,not_z),
        NAF3(s,nand_f1,nand_f2),
        NAC1(nand_c1,half_xy,z),
        NAC2(nand_c2,x,y),
        NAC3(c,nand_c1,nand_c2);
    not
        NH1(not_x,x),
        NH2(not_y,y),
        NF1(not_half_xy,half_xy),
        NF2(not_z,z);
endmodule
module fullAdder(
    input x,
    input y,
    input z,
    output s,
    output c
    );

    wire not_x,not_y,not_z;
    wire half_xy,not_half_xy;
    wire nand_h1,nand_h2,nand_f1,nand_f2;
    wire nand_c1,nand_c2;
    nand 
        NAH1(nand_h1,not_x,y),
        NAH2(nand_h2,x,not_y),
        NAH3(half_xy,nand_h1,nand_h2),
        NAF1(nand_f1,not_half_xy,z),
        NAF2(nand_f2,half_xy,not_z),
        NAF3(s,nand_f1,nand_f2),
        NAC1(nand_c1,half_xy,z),
        NAC2(nand_c2,x,y),
        NAC3(c,nand_c1,nand_c2);
    not
        NH1(not_x,x),
        NH2(not_y,y),
        NF1(not_half_xy,half_xy),
        NF2(not_z,z);
endmodule