data/full_repos/permissive/216615048/src/simulation/ALU_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/ALU_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/ALU_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/ALU_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/ALU_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n#50\n^\n%Error: data/full_repos/permissive/216615048/src/simulation/ALU_tb.v:32: Cannot find file containing module: \'ALU32bit\'\nALU32bit alu(a,b,sel,r,z);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/ALU32bit\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/ALU32bit.v\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/ALU32bit.sv\n             ALU32bit\n             ALU32bit.v\n             ALU32bit.sv\n             obj_dir/ALU32bit\n             obj_dir/ALU32bit.v\n             obj_dir/ALU32bit.sv\n%Warning-WIDTH: data/full_repos/permissive/216615048/src/simulation/ALU_tb.v:40: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                               : ... In instance ALU_tb\na=4\'b1010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/216615048/src/simulation/ALU_tb.v:41: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                                               : ... In instance ALU_tb\nb=4\'b0101;\n ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_tb();


reg [31:0]a;
reg [31:0]b;
reg [3:0]sel;
wire [31:0]r;
wire z;
 
ALU32bit alu(a,b,sel,r,z);

initial begin
a=2;
b=2;
sel=4'b0010;
#50

a=4'b1010;
b=4'b0101;
sel=4'b0000;
#50

a=100;
b=55;
sel=4'b0110;
#50
a=100;
b=55;
sel=4'b0001;
#50
a=10;
b=5;
sel=4'b0001;





end
endmodule
module ALU_tb();



reg [31:0]a;
reg [31:0]b;
reg [3:0]sel;
wire [31:0]r;
wire z;
 
ALU32bit alu(a,b,sel,r,z);

initial begin
a=2;
b=2;
sel=4'b0010;
#50

a=4'b1010;
b=4'b0101;
sel=4'b0000;
#50

a=100;
b=55;
sel=4'b0110;
#50
a=100;
b=55;
sel=4'b0001;
#50
a=10;
b=5;
sel=4'b0001;





end
endmodule