data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v
1: b'%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:45: Cannot find include file: openMSP430_defines.v\n`include "openMSP430_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/152581089/Verilog/MSP430,data/full_repos/permissive/152581089/openMSP430_defines.v\n             data/full_repos/permissive/152581089/Verilog/MSP430,data/full_repos/permissive/152581089/openMSP430_defines.v.v\n             data/full_repos/permissive/152581089/Verilog/MSP430,data/full_repos/permissive/152581089/openMSP430_defines.v.sv\n             openMSP430_defines.v\n             openMSP430_defines.v.v\n             openMSP430_defines.v.sv\n             obj_dir/openMSP430_defines.v\n             obj_dir/openMSP430_defines.v.v\n             obj_dir/openMSP430_defines.v.sv\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:257: Cannot find include file: openMSP430_undefines.v\n`include "openMSP430_undefines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:151: Define or directive not defined: \'`ALU_SRC_INV\'\nwire        op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]);\n                                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:151: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire        op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]);\n                                                                ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:161: Define or directive not defined: \'`JL\'\nwire        jmp_not_taken  = (inst_jmp[`JL]  & ~(status[3]^status[2])) |\n                                       ^~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:161: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire        jmp_not_taken  = (inst_jmp[`JL]  & ~(status[3]^status[2])) |\n                                          ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:162: Define or directive not defined: \'`JGE\'\n                             (inst_jmp[`JGE] &  (status[3]^status[2])) |\n                                       ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:163: Define or directive not defined: \'`JN\'\n                             (inst_jmp[`JN]  &  ~status[2])            |\n                                       ^~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:164: Define or directive not defined: \'`JC\'\n                             (inst_jmp[`JC]  &  ~status[0])            |\n                                       ^~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:165: Define or directive not defined: \'`JNC\'\n                             (inst_jmp[`JNC] &   status[0])            |\n                                       ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:166: Define or directive not defined: \'`JEQ\'\n                             (inst_jmp[`JEQ] &  ~status[1])            |\n                                       ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:167: Define or directive not defined: \'`JNE\'\n                             (inst_jmp[`JNE] &   status[1]);\n                                       ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:178: Define or directive not defined: \'`ALU_INC_C\'\nwire        alu_inc         = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) |\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:178: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire        alu_inc         = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) |\n                                                                ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:179: Define or directive not defined: \'`ALU_INC\'\n                                             inst_alu[`ALU_INC]);\n                                                      ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:193: Define or directive not defined: \'`RRC\'\nwire        alu_shift_msb  = inst_so[`RRC] ? status[0]     :\n                                     ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:193: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire        alu_shift_msb  = inst_so[`RRC] ? status[0]     :\n                                         ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:205: Define or directive not defined: \'`ALU_AND\'\nwire        alu_short_thro = ~(inst_alu[`ALU_AND]   |\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:205: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire        alu_short_thro = ~(inst_alu[`ALU_AND]   |\n                                                ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:206: Define or directive not defined: \'`ALU_OR\'\n                               inst_alu[`ALU_OR]    |\n                                        ^~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:207: Define or directive not defined: \'`ALU_XOR\'\n                               inst_alu[`ALU_XOR]   |\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:208: Define or directive not defined: \'`ALU_SHIFT\'\n                               inst_alu[`ALU_SHIFT] |\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:209: Define or directive not defined: \'`SWPB\'\n                               inst_so[`SWPB]       |\n                                       ^~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:210: Define or directive not defined: \'`SXT\'\n                               inst_so[`SXT]);\n                                       ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:212: Define or directive not defined: \'`ALU_AND\'\nwire [16:0] alu_short      = ({17{inst_alu[`ALU_AND]}}   & alu_and)   |\n                                           ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:212: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [16:0] alu_short      = ({17{inst_alu[`ALU_AND]}}   & alu_and)   |\n                                                   ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:213: Define or directive not defined: \'`ALU_OR\'\n                             ({17{inst_alu[`ALU_OR]}}    & alu_or)    |\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:214: Define or directive not defined: \'`ALU_XOR\'\n                             ({17{inst_alu[`ALU_XOR]}}   & alu_xor)   |\n                                           ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:215: Define or directive not defined: \'`ALU_SHIFT\'\n                             ({17{inst_alu[`ALU_SHIFT]}} & alu_shift) |\n                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:216: Define or directive not defined: \'`SWPB\'\n                             ({17{inst_so[`SWPB]}}       & alu_swpb)  |\n                                          ^~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:217: Define or directive not defined: \'`SXT\'\n                             ({17{inst_so[`SXT]}}        & alu_sxt)   |\n                                          ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:222: Define or directive not defined: \'`IRQ\'\nwire [16:0] alu_out_nxt    = (inst_so[`IRQ] | dbg_halt_st |\n                                      ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:222: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [16:0] alu_out_nxt    = (inst_so[`IRQ] | dbg_halt_st |\n                                          ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:223: Define or directive not defined: \'`ALU_ADD\'\n                              inst_alu[`ALU_ADD]) ? alu_add_inc :\n                                       ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:224: Define or directive not defined: \'`ALU_DADD\'\n                              inst_alu[`ALU_DADD] ? alu_dadd    : alu_short;\n                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:246: Define or directive not defined: \'`ALU_SHIFT\'\nassign  alu_stat    = inst_alu[`ALU_SHIFT]  ? {1\'b0, N,Z,op_src_in[0]} :\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:246: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign  alu_stat    = inst_alu[`ALU_SHIFT]  ? {1\'b0, N,Z,op_src_in[0]} :\n                                         ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:247: Define or directive not defined: \'`ALU_STAT_7\'\n                      inst_alu[`ALU_STAT_7] ? {1\'b0, N,Z,~Z}           :\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:248: Define or directive not defined: \'`ALU_XOR\'\n                      inst_alu[`ALU_XOR]    ? {V_xor,N,Z,~Z}           : {V,N,Z,C};\n                               ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:250: Define or directive not defined: \'`ALU_STAT_F\'\nassign  alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4\'b1111 : 4\'b0000;\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:250: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign  alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4\'b1111 : 4\'b0000;\n                                           ^\n%Error: Exiting due to 41 error(s)\n'
function [4:0] bcd_add;

   input [3:0] X;
   input [3:0] Y;
   input       C_;

   reg   [4:0] Z_;
   begin
      Z_ = {1'b0,X}+{1'b0,Y}+{4'b0000,C_};
      if (Z_<5'd10) bcd_add = Z_;
      else          bcd_add = Z_+5'd6;
   end

endfunction
function [4:0] bcd_add;


   input [3:0] X;
   input [3:0] Y;
   input       C_;

   reg   [4:0] Z_;
   begin
      Z_ = {1'b0,X}+{1'b0,Y}+{4'b0000,C_};
      if (Z_<5'd10) bcd_add = Z_;
      else          bcd_add = Z_+5'd6;
   end

endfunction