data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_output_lvds.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_output_lvds.v:116: Cannot find file containing module: 'OSERDESE2'\n  OSERDESE2 #(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen,data/full_repos/permissive/214858095/OSERDESE2\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen,data/full_repos/permissive/214858095/OSERDESE2.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen,data/full_repos/permissive/214858095/OSERDESE2.sv\n             OSERDESE2\n             OSERDESE2.v\n             OSERDESE2.sv\n             obj_dir/OSERDESE2\n             obj_dir/OSERDESE2.v\n             obj_dir/OSERDESE2.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_output_lvds.v:165: Cannot find file containing module: 'ODELAYE2'\n      ODELAYE2 #(\n      ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_output_lvds.v:196: Cannot find file containing module: 'OBUFDS'\n  OBUFDS ddr_clk_obuf (\n  ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_output_lvds.v:209: Cannot find file containing module: 'OSERDESE2'\n  OSERDESE2 #(\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_output_lvds.v:261: Cannot find file containing module: 'ODELAYE2'\n      ODELAYE2 #(\n      ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_output_lvds.v:290: Cannot find file containing module: 'OBUFDS'\n  OBUFDS ddr_frame_obuf (\n  ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_output_lvds.v:311: Cannot find file containing module: 'OSERDESE2'\n      OSERDESE2 #(\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_output_lvds.v:359: Cannot find file containing module: 'ODELAYE2'\n        ODELAYE2 #(\n        ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/io_cap_gen/cat_output_lvds.v:387: Cannot find file containing module: 'OBUFDS'\n      OBUFDS ddr_data_obuf (\n      ^~~~~~\n%Error: Exiting due to 9 error(s)\n"
module cat_output_lvds #(
  parameter INVERT_FRAME_TX   = 0,
  parameter INVERT_DATA_TX    = 6'b00_0000,
  parameter USE_CLOCK_DELAY   = 1,
  parameter USE_DATA_DELAY    = 1,
  parameter CLOCK_DELAY_MODE = "VAR_LOAD",
  parameter DATA_DELAY_MODE  = "VAR_LOAD",
  parameter CLOCK_DELAY       = 0,
  parameter DATA_DELAY        = 0,
  parameter WIDTH             = 6,
  parameter GROUP             = "DEFAULT"
) (
  input clk200,
  input rst,


  input frame_sample,


  input ddr_clk,
  input sdr_clk,


  output ddr_clk_p,
  output ddr_clk_n,


  output [WIDTH-1:0] ddr_data_p,
  output [WIDTH-1:0] ddr_data_n,
  output             ddr_frame_p,
  output             ddr_frame_n,


  input       ctrl_clk,
  input [4:0] ctrl_data_delay,
  input [4:0] ctrl_clk_delay,
  input       ctrl_ld_data_delay,
  input       ctrl_ld_clk_delay,


  input radio_clk,


  input [(WIDTH*2)-1:0] i0,
  input [(WIDTH*2)-1:0] q0,
  input [(WIDTH*2)-1:0] i1,
  input [(WIDTH*2)-1:0] q1

);






  reg rst_sdr_sync;

  always @(posedge sdr_clk or posedge rst)
    if (rst)
      rst_sdr_sync <= 1'b1;
    else
      rst_sdr_sync <= 1'b0;




  reg [(WIDTH*2)-1:0] radio_data_i0, radio_data_q0;
  reg [(WIDTH*2)-1:0] radio_data_i1, radio_data_q1;
  reg [(WIDTH*2)-1:0] data_i0, data_q0, data_i1, data_q1;


  always @(posedge radio_clk)
  begin


    radio_data_i0 <= i0;
    radio_data_q0 <= q0;
    radio_data_i1 <= i1;
    radio_data_q1 <= q1;
  end







  always @(posedge sdr_clk)
  begin
    data_i0 <= radio_data_i0 ^ {INVERT_DATA_TX,INVERT_DATA_TX};
    data_q0 <= radio_data_q0 ^ {INVERT_DATA_TX,INVERT_DATA_TX};
    data_i1 <= radio_data_i1 ^ {INVERT_DATA_TX,INVERT_DATA_TX};
    data_q1 <= radio_data_q1 ^ {INVERT_DATA_TX,INVERT_DATA_TX};
  end




  wire ddr_clk_out, ddr_clk_dly;

  OSERDESE2 #(
    .DATA_RATE_OQ   ("DDR"),
    .DATA_RATE_TQ   ("DDR"),
    .DATA_WIDTH     (8),
    .INIT_OQ        (1'b0),
    .INIT_TQ        (1'b0),
    .SERDES_MODE    ("MASTER"),
    .SRVAL_OQ       (1'b0),
    .SRVAL_TQ       (1'b0),
    .TBYTE_CTL      ("FALSE"),
    .TBYTE_SRC      ("FALSE"),
    .TRISTATE_WIDTH (1)
  ) ddr_clk_oserdese2 (
    .OFB       (),
    .OQ        (ddr_clk_out),

    .SHIFTOUT1 (),
    .SHIFTOUT2 (),
    .TBYTEOUT  (),
    .TFB       (),
    .TQ        (),
    .CLK       (ddr_clk),
    .CLKDIV    (sdr_clk),

    .D1        (1'b1),
    .D2        (1'b0),
    .D3        (1'b1),
    .D4        (1'b0),
    .D5        (1'b1),
    .D6        (1'b0),
    .D7        (1'b1),
    .D8        (1'b0),
    .OCE       (1'b1),
    .RST       (rst_sdr_sync),

    .SHIFTIN1  (1'b0),
    .SHIFTIN2  (1'b0),

    .T1        (1'b0),
    .T2        (1'b0),
    .T3        (1'b0),
    .T4        (1'b0),
    .TBYTEIN   (1'b0),
    .TCE       (1'b0)
  );

  generate
    if (USE_CLOCK_DELAY) begin : gen_clock_odelay
      (* IODELAY_GROUP = GROUP *)
      ODELAYE2 #(
        .CINVCTRL_SEL          ("FALSE"),
        .DELAY_SRC             ("ODATAIN"),
        .HIGH_PERFORMANCE_MODE ("FALSE"),
        .ODELAY_TYPE           (CLOCK_DELAY_MODE),
        .ODELAY_VALUE          (CLOCK_DELAY),
        .PIPE_SEL              ("FALSE"),
        .REFCLK_FREQUENCY      (200.0),
        .SIGNAL_PATTERN        ("CLOCK")
      ) ddr_clk_odelaye2 (
        .CNTVALUEOUT (),
        .DATAOUT     (ddr_clk_dly),
        .C           (ctrl_clk),
        .CE          (1'b0),
        .CINVCTRL    (1'b0),
        .CLKIN       (1'b0),
        .CNTVALUEIN  (ctrl_clk_delay),
        .INC         (1'b0),
        .LD          (ctrl_ld_clk_delay),

        .LDPIPEEN    (1'b0),
        .ODATAIN     (ddr_clk_out),
        .REGRST      (1'b0)
      );
    end else begin
      assign ddr_clk_dly = ddr_clk_out;
    end
  endgenerate



  OBUFDS ddr_clk_obuf (
    .O  (ddr_clk_p),
    .OB (ddr_clk_n),
    .I  (ddr_clk_dly)
  );






  wire ddr_frame, ddr_frame_dly;

  OSERDESE2 #(
    .DATA_RATE_OQ   ("DDR"),
    .DATA_RATE_TQ   ("DDR"),
    .DATA_WIDTH     (8),
    .INIT_OQ        (1'b0),
    .INIT_TQ        (1'b0),
    .SERDES_MODE    ("MASTER"),
    .SRVAL_OQ       (1'b0),
    .SRVAL_TQ       (1'b0),
    .TBYTE_CTL      ("FALSE"),
    .TBYTE_SRC      ("FALSE"),
    .TRISTATE_WIDTH (1)
  ) ddr_frame_oserdese2 (
    .OFB       (),
    .OQ        (ddr_frame),

    .SHIFTOUT1 (),
    .SHIFTOUT2 (),
    .TBYTEOUT  (),
    .TFB       (),
    .TQ        (),
    .CLK       (ddr_clk),
    .CLKDIV    (sdr_clk),




    .D1        (~INVERT_FRAME_TX[0]),
    .D2        (~INVERT_FRAME_TX[0]),
    .D3        (INVERT_FRAME_TX[0] ~^ frame_sample),
    .D4        (INVERT_FRAME_TX[0] ~^ frame_sample),
    .D5        (INVERT_FRAME_TX[0]  ^ frame_sample),
    .D6        (INVERT_FRAME_TX[0]  ^ frame_sample),
    .D7        (INVERT_FRAME_TX[0]),
    .D8        (INVERT_FRAME_TX[0]),
    .OCE       (1'b1),
    .RST       (rst_sdr_sync),

    .SHIFTIN1  (1'b0),
    .SHIFTIN2  (1'b0),

    .T1        (1'b0),
    .T2        (1'b0),
    .T3        (1'b0),
    .T4        (1'b0),
    .TBYTEIN   (1'b0),
    .TCE       (1'b0)
  );

  generate
    if (USE_DATA_DELAY) begin : gen_frame_odelay
      (* IODELAY_GROUP = GROUP *)
      ODELAYE2 #(
        .CINVCTRL_SEL          ("FALSE"),
        .DELAY_SRC             ("ODATAIN"),
        .HIGH_PERFORMANCE_MODE ("FALSE"),
        .ODELAY_TYPE           (DATA_DELAY_MODE),
        .ODELAY_VALUE          (DATA_DELAY),
        .PIPE_SEL              ("FALSE"),
        .REFCLK_FREQUENCY      (200.0),
        .SIGNAL_PATTERN        ("DATA")
      ) ddr_frame_odelaye2 (
        .CNTVALUEOUT (),
        .DATAOUT     (ddr_frame_dly),
        .C           (ctrl_clk),
        .CE          (1'b0),
        .CINVCTRL    (1'b0),
        .CLKIN       (1'b0),
        .CNTVALUEIN  (ctrl_data_delay),
        .INC         (1'b0),
        .LD          (ctrl_ld_data_delay),

        .LDPIPEEN    (1'b0),
        .ODATAIN     (ddr_frame),
        .REGRST      (1'b0)
      );
    end else begin
      assign ddr_frame_dly = ddr_frame;
    end
  endgenerate

  OBUFDS ddr_frame_obuf (
    .O  (ddr_frame_p),
    .OB (ddr_frame_n),
    .I  (ddr_frame_dly)
  );





  wire [WIDTH-1:0] ddr_data;
  wire [WIDTH-1:0] ddr_data_dly ;





  genvar i;
  generate
    for (i=0 ; i<WIDTH ; i=i+1) begin : generate_data_bus

      OSERDESE2 #(
        .DATA_RATE_OQ   ("DDR"),
        .DATA_RATE_TQ   ("DDR"),
        .DATA_WIDTH     (8),
        .INIT_OQ        (1'b0),
        .INIT_TQ        (1'b0),
        .SERDES_MODE    ("MASTER"),
        .SRVAL_OQ       (1'b0),
        .SRVAL_TQ       (1'b0),
        .TBYTE_CTL      ("FALSE"),
        .TBYTE_SRC      ("FALSE"),
        .TRISTATE_WIDTH (1)
      ) ddr_data_oserdese2 (
        .OFB       (),
        .OQ        (ddr_data[i]),

        .SHIFTOUT1 (),
        .SHIFTOUT2 (),
        .TBYTEOUT  (),
        .TFB       (),
        .TQ        (),
        .CLK       (ddr_clk),
        .CLKDIV    (sdr_clk),

        .D1        (data_i0[WIDTH+i]),
        .D2        (data_q0[WIDTH+i]),
        .D3        (data_i0[i]),
        .D4        (data_q0[i]),
        .D5        (data_i1[WIDTH+i]),
        .D6        (data_q1[WIDTH+i]),
        .D7        (data_i1[i]),
        .D8        (data_q1[i]),
        .OCE       (1'b1),
        .RST       (rst_sdr_sync),

        .SHIFTIN1  (1'b0),
        .SHIFTIN2  (1'b0),

        .T1        (1'b0),
        .T2        (1'b0),
        .T3        (1'b0),
        .T4        (1'b0),
        .TBYTEIN   (1'b0),
        .TCE       (1'b0)
      );

      if (USE_DATA_DELAY) begin : gen_data_odelay
        (* IODELAY_GROUP = GROUP *)
        ODELAYE2 #(
          .CINVCTRL_SEL          ("FALSE"),
          .DELAY_SRC             ("ODATAIN"),
          .HIGH_PERFORMANCE_MODE ("FALSE"),
          .ODELAY_TYPE           (DATA_DELAY_MODE),
          .ODELAY_VALUE          (DATA_DELAY),
          .PIPE_SEL              ("FALSE"),
          .REFCLK_FREQUENCY      (200.0),
          .SIGNAL_PATTERN        ("DATA")
        ) ddr_data_odelaye2 (
          .CNTVALUEOUT (),
          .DATAOUT     (ddr_data_dly[i]),
          .C           (ctrl_clk),
          .CE          (1'b0),
          .CINVCTRL    (1'b0),
          .CLKIN       (1'b0),
          .CNTVALUEIN  (ctrl_data_delay),
          .INC         (1'b0),
          .LD          (ctrl_ld_data_delay),

          .LDPIPEEN    (1'b0),
          .ODATAIN     (ddr_data[i]),
          .REGRST      (1'b0)
        );
      end else begin
        assign ddr_data_dly[i] = ddr_data[i];
      end

      OBUFDS ddr_data_obuf (
        .O  (ddr_data_p[i]),
        .OB (ddr_data_n[i]),
        .I  (ddr_data_dly[i])
      );
    end

  endgenerate

endmodule
module cat_output_lvds #(
  parameter INVERT_FRAME_TX   = 0,
  parameter INVERT_DATA_TX    = 6'b00_0000,
  parameter USE_CLOCK_DELAY   = 1,
  parameter USE_DATA_DELAY    = 1,
  parameter CLOCK_DELAY_MODE = "VAR_LOAD",
  parameter DATA_DELAY_MODE  = "VAR_LOAD",
  parameter CLOCK_DELAY       = 0,
  parameter DATA_DELAY        = 0,
  parameter WIDTH             = 6,
  parameter GROUP             = "DEFAULT"
) (
  input clk200,
  input rst,


  input frame_sample,


  input ddr_clk,
  input sdr_clk,


  output ddr_clk_p,
  output ddr_clk_n,


  output [WIDTH-1:0] ddr_data_p,
  output [WIDTH-1:0] ddr_data_n,
  output             ddr_frame_p,
  output             ddr_frame_n,


  input       ctrl_clk,
  input [4:0] ctrl_data_delay,
  input [4:0] ctrl_clk_delay,
  input       ctrl_ld_data_delay,
  input       ctrl_ld_clk_delay,


  input radio_clk,


  input [(WIDTH*2)-1:0] i0,
  input [(WIDTH*2)-1:0] q0,
  input [(WIDTH*2)-1:0] i1,
  input [(WIDTH*2)-1:0] q1

);







  reg rst_sdr_sync;

  always @(posedge sdr_clk or posedge rst)
    if (rst)
      rst_sdr_sync <= 1'b1;
    else
      rst_sdr_sync <= 1'b0;




  reg [(WIDTH*2)-1:0] radio_data_i0, radio_data_q0;
  reg [(WIDTH*2)-1:0] radio_data_i1, radio_data_q1;
  reg [(WIDTH*2)-1:0] data_i0, data_q0, data_i1, data_q1;


  always @(posedge radio_clk)
  begin


    radio_data_i0 <= i0;
    radio_data_q0 <= q0;
    radio_data_i1 <= i1;
    radio_data_q1 <= q1;
  end







  always @(posedge sdr_clk)
  begin
    data_i0 <= radio_data_i0 ^ {INVERT_DATA_TX,INVERT_DATA_TX};
    data_q0 <= radio_data_q0 ^ {INVERT_DATA_TX,INVERT_DATA_TX};
    data_i1 <= radio_data_i1 ^ {INVERT_DATA_TX,INVERT_DATA_TX};
    data_q1 <= radio_data_q1 ^ {INVERT_DATA_TX,INVERT_DATA_TX};
  end




  wire ddr_clk_out, ddr_clk_dly;

  OSERDESE2 #(
    .DATA_RATE_OQ   ("DDR"),
    .DATA_RATE_TQ   ("DDR"),
    .DATA_WIDTH     (8),
    .INIT_OQ        (1'b0),
    .INIT_TQ        (1'b0),
    .SERDES_MODE    ("MASTER"),
    .SRVAL_OQ       (1'b0),
    .SRVAL_TQ       (1'b0),
    .TBYTE_CTL      ("FALSE"),
    .TBYTE_SRC      ("FALSE"),
    .TRISTATE_WIDTH (1)
  ) ddr_clk_oserdese2 (
    .OFB       (),
    .OQ        (ddr_clk_out),

    .SHIFTOUT1 (),
    .SHIFTOUT2 (),
    .TBYTEOUT  (),
    .TFB       (),
    .TQ        (),
    .CLK       (ddr_clk),
    .CLKDIV    (sdr_clk),

    .D1        (1'b1),
    .D2        (1'b0),
    .D3        (1'b1),
    .D4        (1'b0),
    .D5        (1'b1),
    .D6        (1'b0),
    .D7        (1'b1),
    .D8        (1'b0),
    .OCE       (1'b1),
    .RST       (rst_sdr_sync),

    .SHIFTIN1  (1'b0),
    .SHIFTIN2  (1'b0),

    .T1        (1'b0),
    .T2        (1'b0),
    .T3        (1'b0),
    .T4        (1'b0),
    .TBYTEIN   (1'b0),
    .TCE       (1'b0)
  );

  generate
    if (USE_CLOCK_DELAY) begin : gen_clock_odelay
      (* IODELAY_GROUP = GROUP *)
      ODELAYE2 #(
        .CINVCTRL_SEL          ("FALSE"),
        .DELAY_SRC             ("ODATAIN"),
        .HIGH_PERFORMANCE_MODE ("FALSE"),
        .ODELAY_TYPE           (CLOCK_DELAY_MODE),
        .ODELAY_VALUE          (CLOCK_DELAY),
        .PIPE_SEL              ("FALSE"),
        .REFCLK_FREQUENCY      (200.0),
        .SIGNAL_PATTERN        ("CLOCK")
      ) ddr_clk_odelaye2 (
        .CNTVALUEOUT (),
        .DATAOUT     (ddr_clk_dly),
        .C           (ctrl_clk),
        .CE          (1'b0),
        .CINVCTRL    (1'b0),
        .CLKIN       (1'b0),
        .CNTVALUEIN  (ctrl_clk_delay),
        .INC         (1'b0),
        .LD          (ctrl_ld_clk_delay),

        .LDPIPEEN    (1'b0),
        .ODATAIN     (ddr_clk_out),
        .REGRST      (1'b0)
      );
    end else begin
      assign ddr_clk_dly = ddr_clk_out;
    end
  endgenerate



  OBUFDS ddr_clk_obuf (
    .O  (ddr_clk_p),
    .OB (ddr_clk_n),
    .I  (ddr_clk_dly)
  );






  wire ddr_frame, ddr_frame_dly;

  OSERDESE2 #(
    .DATA_RATE_OQ   ("DDR"),
    .DATA_RATE_TQ   ("DDR"),
    .DATA_WIDTH     (8),
    .INIT_OQ        (1'b0),
    .INIT_TQ        (1'b0),
    .SERDES_MODE    ("MASTER"),
    .SRVAL_OQ       (1'b0),
    .SRVAL_TQ       (1'b0),
    .TBYTE_CTL      ("FALSE"),
    .TBYTE_SRC      ("FALSE"),
    .TRISTATE_WIDTH (1)
  ) ddr_frame_oserdese2 (
    .OFB       (),
    .OQ        (ddr_frame),

    .SHIFTOUT1 (),
    .SHIFTOUT2 (),
    .TBYTEOUT  (),
    .TFB       (),
    .TQ        (),
    .CLK       (ddr_clk),
    .CLKDIV    (sdr_clk),




    .D1        (~INVERT_FRAME_TX[0]),
    .D2        (~INVERT_FRAME_TX[0]),
    .D3        (INVERT_FRAME_TX[0] ~^ frame_sample),
    .D4        (INVERT_FRAME_TX[0] ~^ frame_sample),
    .D5        (INVERT_FRAME_TX[0]  ^ frame_sample),
    .D6        (INVERT_FRAME_TX[0]  ^ frame_sample),
    .D7        (INVERT_FRAME_TX[0]),
    .D8        (INVERT_FRAME_TX[0]),
    .OCE       (1'b1),
    .RST       (rst_sdr_sync),

    .SHIFTIN1  (1'b0),
    .SHIFTIN2  (1'b0),

    .T1        (1'b0),
    .T2        (1'b0),
    .T3        (1'b0),
    .T4        (1'b0),
    .TBYTEIN   (1'b0),
    .TCE       (1'b0)
  );

  generate
    if (USE_DATA_DELAY) begin : gen_frame_odelay
      (* IODELAY_GROUP = GROUP *)
      ODELAYE2 #(
        .CINVCTRL_SEL          ("FALSE"),
        .DELAY_SRC             ("ODATAIN"),
        .HIGH_PERFORMANCE_MODE ("FALSE"),
        .ODELAY_TYPE           (DATA_DELAY_MODE),
        .ODELAY_VALUE          (DATA_DELAY),
        .PIPE_SEL              ("FALSE"),
        .REFCLK_FREQUENCY      (200.0),
        .SIGNAL_PATTERN        ("DATA")
      ) ddr_frame_odelaye2 (
        .CNTVALUEOUT (),
        .DATAOUT     (ddr_frame_dly),
        .C           (ctrl_clk),
        .CE          (1'b0),
        .CINVCTRL    (1'b0),
        .CLKIN       (1'b0),
        .CNTVALUEIN  (ctrl_data_delay),
        .INC         (1'b0),
        .LD          (ctrl_ld_data_delay),

        .LDPIPEEN    (1'b0),
        .ODATAIN     (ddr_frame),
        .REGRST      (1'b0)
      );
    end else begin
      assign ddr_frame_dly = ddr_frame;
    end
  endgenerate

  OBUFDS ddr_frame_obuf (
    .O  (ddr_frame_p),
    .OB (ddr_frame_n),
    .I  (ddr_frame_dly)
  );





  wire [WIDTH-1:0] ddr_data;
  wire [WIDTH-1:0] ddr_data_dly ;





  genvar i;
  generate
    for (i=0 ; i<WIDTH ; i=i+1) begin : generate_data_bus

      OSERDESE2 #(
        .DATA_RATE_OQ   ("DDR"),
        .DATA_RATE_TQ   ("DDR"),
        .DATA_WIDTH     (8),
        .INIT_OQ        (1'b0),
        .INIT_TQ        (1'b0),
        .SERDES_MODE    ("MASTER"),
        .SRVAL_OQ       (1'b0),
        .SRVAL_TQ       (1'b0),
        .TBYTE_CTL      ("FALSE"),
        .TBYTE_SRC      ("FALSE"),
        .TRISTATE_WIDTH (1)
      ) ddr_data_oserdese2 (
        .OFB       (),
        .OQ        (ddr_data[i]),

        .SHIFTOUT1 (),
        .SHIFTOUT2 (),
        .TBYTEOUT  (),
        .TFB       (),
        .TQ        (),
        .CLK       (ddr_clk),
        .CLKDIV    (sdr_clk),

        .D1        (data_i0[WIDTH+i]),
        .D2        (data_q0[WIDTH+i]),
        .D3        (data_i0[i]),
        .D4        (data_q0[i]),
        .D5        (data_i1[WIDTH+i]),
        .D6        (data_q1[WIDTH+i]),
        .D7        (data_i1[i]),
        .D8        (data_q1[i]),
        .OCE       (1'b1),
        .RST       (rst_sdr_sync),

        .SHIFTIN1  (1'b0),
        .SHIFTIN2  (1'b0),

        .T1        (1'b0),
        .T2        (1'b0),
        .T3        (1'b0),
        .T4        (1'b0),
        .TBYTEIN   (1'b0),
        .TCE       (1'b0)
      );

      if (USE_DATA_DELAY) begin : gen_data_odelay
        (* IODELAY_GROUP = GROUP *)
        ODELAYE2 #(
          .CINVCTRL_SEL          ("FALSE"),
          .DELAY_SRC             ("ODATAIN"),
          .HIGH_PERFORMANCE_MODE ("FALSE"),
          .ODELAY_TYPE           (DATA_DELAY_MODE),
          .ODELAY_VALUE          (DATA_DELAY),
          .PIPE_SEL              ("FALSE"),
          .REFCLK_FREQUENCY      (200.0),
          .SIGNAL_PATTERN        ("DATA")
        ) ddr_data_odelaye2 (
          .CNTVALUEOUT (),
          .DATAOUT     (ddr_data_dly[i]),
          .C           (ctrl_clk),
          .CE          (1'b0),
          .CINVCTRL    (1'b0),
          .CLKIN       (1'b0),
          .CNTVALUEIN  (ctrl_data_delay),
          .INC         (1'b0),
          .LD          (ctrl_ld_data_delay),

          .LDPIPEEN    (1'b0),
          .ODATAIN     (ddr_data[i]),
          .REGRST      (1'b0)
        );
      end else begin
        assign ddr_data_dly[i] = ddr_data[i];
      end

      OBUFDS ddr_data_obuf (
        .O  (ddr_data_p[i]),
        .OB (ddr_data_n[i]),
        .I  (ddr_data_dly[i])
      );
    end

  endgenerate

endmodule