data/full_repos/permissive/109846502/maintb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/maintb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  forever #1 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/maintb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #20 rst = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/109846502/maintb.v:39: Cannot find file containing module: \'main\'\n main #(.div(2)) uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main.v\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module maintb;


	reg rst;
	reg clk;
	reg en;


	wire rw_out;
	wire rs_out;
	wire e_out;
	wire [7:0] db_out;


	main #(.div(2)) uut (
		.rst(rst), 
		.clk(clk), 
		.rw_out(rw_out), 
		.rs_out(rs_out), 
		.e_out(e_out), 
		.db_out(db_out)
	);

	initial begin
		en = 1'b1;
		clk = 1'b1;
		forever #1 clk = ~clk;
	end
	
	initial begin
		rst = 1'b1;
		#20 rst = 1'b0;
	end
	
      
endmodule
module maintb;



	reg rst;
	reg clk;
	reg en;


	wire rw_out;
	wire rs_out;
	wire e_out;
	wire [7:0] db_out;


	main #(.div(2)) uut (
		.rst(rst), 
		.clk(clk), 
		.rw_out(rw_out), 
		.rs_out(rs_out), 
		.e_out(e_out), 
		.db_out(db_out)
	);

	initial begin
		en = 1'b1;
		clk = 1'b1;
		forever #1 clk = ~clk;
	end
	
	initial begin
		rst = 1'b1;
		#20 rst = 1'b0;
	end
	
      
endmodule