data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/sim/axi_slave_sim.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/sim/axi_slave_sim.v:81: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/sim,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/sim,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/sim,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/sim/axi_slave_sim.v:93: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n      rnd = $unsigned($random(seed_i)) % 100;\n                      ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/axi/sim/axi_slave_sim.v:93: ../V3Ast.cpp:358: Null item passed to setOp1p\n      rnd = $unsigned($random(seed_i)) % 100;\n            ^~~~~~~~~\n'
module axi_slave_sim #(
  parameter DataBits        = 64,
  parameter AxiAddrBits     = 32,
  parameter MemAddrBits     = 12,
  parameter NumPendingReads = 4,
  parameter WrThroughput    = 63,
  parameter RdThroughput    = 57,
  parameter Seed            = 3,
  parameter MemInitFile     = "undefined",
  parameter MemDumpFile     = "memdump.dat")
(
  input                   clk,
  input                   rst,

  input                   dump_memory,

  input                   slv_awvalid,
  output                  slv_awready,
  input [3:0]             slv_awid,
  input [AxiAddrBits-1:0] slv_awaddr,
  input [3:0]             slv_awlen,
  input [2:0]             slv_awsize,
  input [1:0]             slv_awlock,
  input [1:0]             slv_awburst,

  input                   slv_wvalid,
  output                  slv_wready,
  input [3:0]             slv_wid,
  input [DataBits/8-1:0]  slv_wstrb,
  input                   slv_wlast,
  input [DataBits-1:0]    slv_wdata,

  output reg              slv_bvalid,
  input                   slv_bready,
  output [3:0]            slv_bid,
  output [1:0]            slv_bresp,

  input                   slv_arvalid,
  output                  slv_arready,
  input [3:0]             slv_arid,
  input [AxiAddrBits-1:0] slv_araddr,
  input [3:0]             slv_arlen,
  input [2:0]             slv_arsize,
  input [1:0]             slv_arlock,
  input [1:0]             slv_arburst,

  output                  slv_rvalid,
  input                   slv_rready,
  output [3:0]            slv_rid,
  output [DataBits-1:0]   slv_rdata,
  output [1:0]            slv_rresp,
  output                  slv_rlast);

`include "util.vh"

  localparam ByteAddrBits = clog2(DataBits/8);


  integer seed_i;
  initial seed_i = Seed;


  function weighted_rand(input integer probability_of_one);
    integer rnd;
    begin
      rnd = $unsigned($random(seed_i)) % 100;
      weighted_rand = (rnd < probability_of_one) ? 1 : 0;
    end
  endfunction

  reg [DataBits-1:0]    memory[2**MemAddrBits-1:0];
  initial begin
    if (MemInitFile != "undefined")
      $readmemh(MemInitFile, memory);
  end

  always @(posedge dump_memory) begin
    $writememh(MemDumpFile, memory);
  end




  localparam WrIdle = 0,
             WrBurst = 1;

  reg [1:0]             wr_state;
  reg [MemAddrBits-1:0] wr_addr;
  reg [4:0]             wr_burst, wr_count;
  reg                   wr_stalling;
  wire                  rsp_ready;

  begin:wr_process
    reg burst_done_i;
    always @(posedge clk) begin
      burst_done_i = 0;

      case (wr_state)

        WrIdle:
          if (slv_awvalid & slv_awready) begin
            wr_addr     <= slv_awaddr >> ByteAddrBits;
            wr_burst    <= slv_awlen + 1;
            wr_count    <= 0;
            wr_stalling <= weighted_rand(100 - WrThroughput);
            wr_state    <= WrBurst;
          end

        WrBurst:
          begin
            if (slv_wvalid & slv_wready) begin
              memory[wr_addr + wr_count] <= slv_wdata;
              wr_count                   <= wr_count + 1;
              if (wr_count == wr_burst-1) begin
                wr_state    <= WrIdle;
                burst_done_i = 1;

              end
            end


            if (wr_stalling || slv_wvalid) begin
              wr_stalling <= weighted_rand(100 - WrThroughput);
            end
          end

      endcase


      slv_bvalid <= ~rsp_ready | burst_done_i;

      if (rst) begin
        wr_state   <= WrIdle;
        slv_bvalid <= 0;
      end
    end
  end


  assign rsp_ready   = ~slv_bvalid | slv_bready;


  assign slv_awready = (wr_state == WrIdle) && (rsp_ready);


  assign slv_wready  = (wr_state == WrBurst) && (!wr_stalling);





  wire                   fifo_arvalid, fifo_arready;
  wire [MemAddrBits-1:0] fifo_araddr;
  wire [3:0]             fifo_arlen;


  wire [MemAddrBits-1:0] slv_araddr_word = slv_araddr >> ByteAddrBits;

  stream_fifo_1clk_regs #(
    .Width    (4 + MemAddrBits),
    .Depth    (NumPendingReads))
  fifo(
    .rst       (rst),
    .clk       (clk),

    .din_valid (slv_arvalid),
    .din_ready (slv_arready),
    .din_data  ({slv_arlen, slv_araddr_word}),

    .dout_valid(fifo_arvalid),
    .dout_ready(fifo_arready),
    .dout_data ({fifo_arlen, fifo_araddr}),
    .used      ());




  wire                rd_valid, rd_ready, stall_valid, stall_ready, rd_last;
  wire [DataBits-1:0] rd_data;
  reg  [3:0]          rd_count;
  reg                 rd_stalling;
  always @(posedge clk) begin

    if (rd_valid & rd_ready) begin
      if (rd_count == fifo_arlen) begin
        rd_count <= 0;
      end else begin
        rd_count <= rd_count + 1;
      end
    end
    if (rst) begin
      rd_count <= 0;
    end
  end

  assign rd_valid     = fifo_arvalid;
  assign rd_data      = memory[fifo_araddr + rd_count];
  assign rd_last      = rd_count == fifo_arlen;

  assign fifo_arready = (rd_last) ? rd_ready : 0;




  always @(posedge clk) begin
    rd_stalling <= weighted_rand(100 - RdThroughput);
  end
  assign stall_valid   = (rd_stalling) ? 0 : rd_valid;
  assign rd_ready      = (rd_stalling) ? 0 : stall_ready;




  stream_buf_v #(
    .DataBits (DataBits+1))
  rd_buf(
    .clk       (clk),
    .rst       (rst),
    .in_valid  (stall_valid),
    .in_ready  (stall_ready),
    .in_data   ({rd_last, rd_data}),
    .out_valid (slv_rvalid),
    .out_ready (slv_rready),
    .out_data  ({slv_rlast, slv_rdata}));


  assign slv_bid    = 0;
  assign slv_bresp  = 0;
  assign slv_rid    = 0;
  assign slv_rresp  = 0;

endmodule
module axi_slave_sim #(
  parameter DataBits        = 64,
  parameter AxiAddrBits     = 32,
  parameter MemAddrBits     = 12,
  parameter NumPendingReads = 4,
  parameter WrThroughput    = 63,
  parameter RdThroughput    = 57,
  parameter Seed            = 3,
  parameter MemInitFile     = "undefined",
  parameter MemDumpFile     = "memdump.dat")
(
  input                   clk,
  input                   rst,

  input                   dump_memory,

  input                   slv_awvalid,
  output                  slv_awready,
  input [3:0]             slv_awid,
  input [AxiAddrBits-1:0] slv_awaddr,
  input [3:0]             slv_awlen,
  input [2:0]             slv_awsize,
  input [1:0]             slv_awlock,
  input [1:0]             slv_awburst,

  input                   slv_wvalid,
  output                  slv_wready,
  input [3:0]             slv_wid,
  input [DataBits/8-1:0]  slv_wstrb,
  input                   slv_wlast,
  input [DataBits-1:0]    slv_wdata,

  output reg              slv_bvalid,
  input                   slv_bready,
  output [3:0]            slv_bid,
  output [1:0]            slv_bresp,

  input                   slv_arvalid,
  output                  slv_arready,
  input [3:0]             slv_arid,
  input [AxiAddrBits-1:0] slv_araddr,
  input [3:0]             slv_arlen,
  input [2:0]             slv_arsize,
  input [1:0]             slv_arlock,
  input [1:0]             slv_arburst,

  output                  slv_rvalid,
  input                   slv_rready,
  output [3:0]            slv_rid,
  output [DataBits-1:0]   slv_rdata,
  output [1:0]            slv_rresp,
  output                  slv_rlast);


`include "util.vh"

  localparam ByteAddrBits = clog2(DataBits/8);


  integer seed_i;
  initial seed_i = Seed;


  function weighted_rand(input integer probability_of_one);
    integer rnd;
    begin
      rnd = $unsigned($random(seed_i)) % 100;
      weighted_rand = (rnd < probability_of_one) ? 1 : 0;
    end
  endfunction

  reg [DataBits-1:0]    memory[2**MemAddrBits-1:0];
  initial begin
    if (MemInitFile != "undefined")
      $readmemh(MemInitFile, memory);
  end

  always @(posedge dump_memory) begin
    $writememh(MemDumpFile, memory);
  end




  localparam WrIdle = 0,
             WrBurst = 1;

  reg [1:0]             wr_state;
  reg [MemAddrBits-1:0] wr_addr;
  reg [4:0]             wr_burst, wr_count;
  reg                   wr_stalling;
  wire                  rsp_ready;

  begin:wr_process
    reg burst_done_i;
    always @(posedge clk) begin
      burst_done_i = 0;

      case (wr_state)

        WrIdle:
          if (slv_awvalid & slv_awready) begin
            wr_addr     <= slv_awaddr >> ByteAddrBits;
            wr_burst    <= slv_awlen + 1;
            wr_count    <= 0;
            wr_stalling <= weighted_rand(100 - WrThroughput);
            wr_state    <= WrBurst;
          end

        WrBurst:
          begin
            if (slv_wvalid & slv_wready) begin
              memory[wr_addr + wr_count] <= slv_wdata;
              wr_count                   <= wr_count + 1;
              if (wr_count == wr_burst-1) begin
                wr_state    <= WrIdle;
                burst_done_i = 1;

              end
            end


            if (wr_stalling || slv_wvalid) begin
              wr_stalling <= weighted_rand(100 - WrThroughput);
            end
          end

      endcase


      slv_bvalid <= ~rsp_ready | burst_done_i;

      if (rst) begin
        wr_state   <= WrIdle;
        slv_bvalid <= 0;
      end
    end
  end


  assign rsp_ready   = ~slv_bvalid | slv_bready;


  assign slv_awready = (wr_state == WrIdle) && (rsp_ready);


  assign slv_wready  = (wr_state == WrBurst) && (!wr_stalling);





  wire                   fifo_arvalid, fifo_arready;
  wire [MemAddrBits-1:0] fifo_araddr;
  wire [3:0]             fifo_arlen;


  wire [MemAddrBits-1:0] slv_araddr_word = slv_araddr >> ByteAddrBits;

  stream_fifo_1clk_regs #(
    .Width    (4 + MemAddrBits),
    .Depth    (NumPendingReads))
  fifo(
    .rst       (rst),
    .clk       (clk),

    .din_valid (slv_arvalid),
    .din_ready (slv_arready),
    .din_data  ({slv_arlen, slv_araddr_word}),

    .dout_valid(fifo_arvalid),
    .dout_ready(fifo_arready),
    .dout_data ({fifo_arlen, fifo_araddr}),
    .used      ());




  wire                rd_valid, rd_ready, stall_valid, stall_ready, rd_last;
  wire [DataBits-1:0] rd_data;
  reg  [3:0]          rd_count;
  reg                 rd_stalling;
  always @(posedge clk) begin

    if (rd_valid & rd_ready) begin
      if (rd_count == fifo_arlen) begin
        rd_count <= 0;
      end else begin
        rd_count <= rd_count + 1;
      end
    end
    if (rst) begin
      rd_count <= 0;
    end
  end

  assign rd_valid     = fifo_arvalid;
  assign rd_data      = memory[fifo_araddr + rd_count];
  assign rd_last      = rd_count == fifo_arlen;

  assign fifo_arready = (rd_last) ? rd_ready : 0;




  always @(posedge clk) begin
    rd_stalling <= weighted_rand(100 - RdThroughput);
  end
  assign stall_valid   = (rd_stalling) ? 0 : rd_valid;
  assign rd_ready      = (rd_stalling) ? 0 : stall_ready;




  stream_buf_v #(
    .DataBits (DataBits+1))
  rd_buf(
    .clk       (clk),
    .rst       (rst),
    .in_valid  (stall_valid),
    .in_ready  (stall_ready),
    .in_data   ({rd_last, rd_data}),
    .out_valid (slv_rvalid),
    .out_ready (slv_rready),
    .out_data  ({slv_rlast, slv_rdata}));


  assign slv_bid    = 0;
  assign slv_bresp  = 0;
  assign slv_rid    = 0;
  assign slv_rresp  = 0;

endmodule