data/full_repos/permissive/143278/ivltests/implicit-port7.v
 line:13: before: "*"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/implicit-port7.v:23: Unsupported: Ignoring delay on this delayed statement.\n   #1 if (b !== x || d !== ~x) begin\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/implicit-port7.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #1 a = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/implicit-port7.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #1 if (b !== x || d !== ~x) begin\n   ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
reg a;
reg x;
wire b, d;
m foo(.a(x), .e(), .*, .c(d), .d());
m foo2(.a(x), .d(), .*, .c(), .e());
m foo3(.a(x), .*, .d(), .c(), .e());
m foo4(.*, .a(x), .d(), .c(), .e());
m foo5(.a(x), .d(), .c(), .*, .e());
m foo6(.a(x), .d(), .c(), .e(), .*);

initial begin
   a = 0;
   x = 1;
   #1 if (b !== x || d !== ~x) begin
      $display("FAILED -- a=%b, x=%b, b=%b, d=%b", a, x, b, d);
   end
   #1 a = 1;
   #1 if (b !== x || d !== ~x) begin
      $display("FAILED -- a=%b, x=%b, b=%b, d=%b", a, x, b, d);
   end
   $display("PASSED");
end
endmodule
module top;

reg a;
reg x;
wire b, d;
m foo(.a(x), .e(), .*, .c(d), .d());
m foo2(.a(x), .d(), .*, .c(), .e());
m foo3(.a(x), .*, .d(), .c(), .e());
m foo4(.*, .a(x), .d(), .c(), .e());
m foo5(.a(x), .d(), .c(), .*, .e());
m foo6(.a(x), .d(), .c(), .e(), .*);

initial begin
   a = 0;
   x = 1;
   #1 if (b !== x || d !== ~x) begin
      $display("FAILED -- a=%b, x=%b, b=%b, d=%b", a, x, b, d);
   end
   #1 a = 1;
   #1 if (b !== x || d !== ~x) begin
      $display("FAILED -- a=%b, x=%b, b=%b, d=%b", a, x, b, d);
   end
   $display("PASSED");
end
endmodule