data/full_repos/permissive/110151336/lab_02/src/00_sr_latch_theory/sr_latch.v
data/verilator_xmls/2f21a069-d277-4886-9894-85b854751c76.xml
module sr_latch
(
    input   s,
    input   r,
    output  q,
    output  q_n
);
    assign q   = ~ ( r | q_n );
    assign q_n = ~ ( s | q   );

endmodule
module sr_latch
(
    input   s,
    input   r,
    output  q,
    output  q_n
);

    assign q   = ~ ( r | q_n );
    assign q_n = ~ ( s | q   );

endmodule