data/full_repos/permissive/147073815/syncbram_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/147073815/syncbram_fifo.v:51: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                       : ... In instance syncbram_fifo\n         wr_ptr <= 3\'d0;                           \n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/147073815/syncbram_fifo.v:52: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                       : ... In instance syncbram_fifo\n         rd_ptr <= 3\'d0;                           \n                ^~\n%Error: Exiting due to 2 warning(s)\n'
module syncbram_fifo ( clk, rst, buf_in, buf_out, wr_en, rd_en, buf_empty, buf_full );


input                     clk;
input                     rst;

input                     wr_en;
input                     rd_en;

input           [ 7 : 0 ] buf_in;

output          [ 7 : 0 ] buf_out;

output                    buf_empty;
output                    buf_full;

reg             [ 7 : 0 ] buf_out;

reg    [ `BUF_WIDTH : 0 ] rd_ptr;
reg    [ `BUF_WIDTH : 0 ] wr_ptr;
reg             [ 7 : 0 ] buf_mem[ `BUF_SIZE - 1 : 0 ];


assign buf_full = (( rd_ptr[`BUF_WIDTH] != wr_ptr[`BUF_WIDTH]) && ( rd_ptr[`BUF_WIDTH-1 : 0] == wr_ptr[`BUF_WIDTH-1 : 0] ));
assign buf_empty = ( rd_ptr == wr_ptr );

always @( posedge clk )
begin
   if ( rst )
      buf_out <= 8'b0;
   else if ( rd_en && !buf_empty )
      buf_out <= buf_mem[rd_ptr[`BUF_WIDTH-1 : 0]];
end

always@( posedge clk )
begin
   if ( wr_en && !buf_full )
      buf_mem[wr_ptr[`BUF_WIDTH-1 : 0]] <= buf_in;
end

always@( posedge clk )
begin
   if ( rst )
      begin
         wr_ptr <= `BUF_WIDTH'd0;
         rd_ptr <= `BUF_WIDTH'd0;
      end
   else
   begin
      if ( !buf_full && wr_en )
         wr_ptr <= wr_ptr + `BUF_WIDTH'd1;

      if ( !buf_empty && rd_en )
         rd_ptr <= rd_ptr + `BUF_WIDTH'd1;
   end
end
endmodule
module syncbram_fifo ( clk, rst, buf_in, buf_out, wr_en, rd_en, buf_empty, buf_full );



input                     clk;
input                     rst;

input                     wr_en;
input                     rd_en;

input           [ 7 : 0 ] buf_in;

output          [ 7 : 0 ] buf_out;

output                    buf_empty;
output                    buf_full;

reg             [ 7 : 0 ] buf_out;

reg    [ `BUF_WIDTH : 0 ] rd_ptr;
reg    [ `BUF_WIDTH : 0 ] wr_ptr;
reg             [ 7 : 0 ] buf_mem[ `BUF_SIZE - 1 : 0 ];


assign buf_full = (( rd_ptr[`BUF_WIDTH] != wr_ptr[`BUF_WIDTH]) && ( rd_ptr[`BUF_WIDTH-1 : 0] == wr_ptr[`BUF_WIDTH-1 : 0] ));
assign buf_empty = ( rd_ptr == wr_ptr );

always @( posedge clk )
begin
   if ( rst )
      buf_out <= 8'b0;
   else if ( rd_en && !buf_empty )
      buf_out <= buf_mem[rd_ptr[`BUF_WIDTH-1 : 0]];
end

always@( posedge clk )
begin
   if ( wr_en && !buf_full )
      buf_mem[wr_ptr[`BUF_WIDTH-1 : 0]] <= buf_in;
end

always@( posedge clk )
begin
   if ( rst )
      begin
         wr_ptr <= `BUF_WIDTH'd0;
         rd_ptr <= `BUF_WIDTH'd0;
      end
   else
   begin
      if ( !buf_full && wr_en )
         wr_ptr <= wr_ptr + `BUF_WIDTH'd1;

      if ( !buf_empty && rd_en )
         rd_ptr <= rd_ptr + `BUF_WIDTH'd1;
   end
end
endmodule