data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v
 line:135: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst= 1\'b1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #160 cpu_rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #160 cpu_rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #160 cpu_rx = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #160 cpu_rx = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #160 cpu_rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #160 cpu_rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #160 cpu_rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #160 cpu_rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #160 cpu_rx = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #160 cpu_rx = 1\'b1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #160 cpu_rx = 1\'b0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:73: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b1;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:74: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b0;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:75: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b0;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:76: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b0;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:77: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:78: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:79: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:80: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:82: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b1;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:84: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b0;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:86: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b1;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:87: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b1;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:88: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b1;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:89: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b0;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:90: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:91: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:92: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:93: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:95: Unsupported: Ignoring delay on this delayed statement.\n     #160 cpu_rx = 1\'b1;  \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:97: Unsupported: Ignoring delay on this delayed statement.\n      #160 cpu_rx = 1\'b0;  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #160 cpu_rx = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #160 cpu_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #160 cpu_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #160 cpu_rx = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #160 cpu_rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #160 cpu_rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #160 cpu_rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #160 cpu_rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #160 cpu_rx = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #160 cpu_rx = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:112: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b1;  \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:113: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;  \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:114: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b1;  \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:115: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;  \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:116: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:117: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:118: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:119: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:121: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b1;  \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:123: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;  \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:125: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;  \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:126: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;  \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:127: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;  \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:128: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;  \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:129: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:130: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b1;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:131: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:132: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b0;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:134: Unsupported: Ignoring delay on this delayed statement.\n         #160 cpu_rx = 1\'b1;  \n         ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #500000000 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:137: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 clk=~clk;   \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:138: Unsupported: Ignoring delay on this delayed statement.\nalways #5 rate=~rate;        \n       ^\n%Error: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:140: Cannot find file containing module: \'tx\'\ntx #(.NB_DATA(NB_DATA), .SB_TICK(SB_TICK))\n^~\n        ... Looked in:\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/tx\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/tx.v\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/tx.sv\n             tx\n             tx.v\n             tx.sv\n             obj_dir/tx\n             obj_dir/tx.v\n             obj_dir/tx.sv\n%Error: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:152: Cannot find file containing module: \'rx\'\nrx #(.NB_DATA(NB_DATA), .SB_TICK(SB_TICK))\n^~\n%Error: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:163: Cannot find file containing module: \'interfaz_tx\'\n    interfaz_tx #(.NB_DATA(NB_DATA))\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:176: Cannot find file containing module: \'interfaz_rx\'\n    interfaz_rx #(.NB_DATA(NB_DATA), .NB_OPERADOR(NB_OPERADOR))\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/205673649/UART/Simulacion/tb_top_gral.v:189: Cannot find file containing module: \'ALU\'\n    ALU #(.NB_DATA(NB_DATA), .NB_OPERADOR(NB_OPERADOR))\n    ^~~\n%Error: Exiting due to 5 error(s), 64 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top_gral();

localparam  NB_DATA    =  8;
localparam SB_TICK = 16;
localparam  NB_OPERADOR    =  6;

reg clk;
reg rst;
reg rate;


wire tx_interfaz_done_data;
wire [NB_DATA-1:0] interfaz_tx_data;
wire int_tx;  

wire rx_interfaz_done_data;
wire [NB_DATA-1:0] rx_interfaz_data;

wire [NB_DATA-1 : 0] dato_a;
wire [NB_DATA-1 : 0] dato_b;
wire [NB_OPERADOR-1 : 0] operador;
wire rx_alu_done;
wire done_alu_tx;
wire [NB_DATA-1 : 0] resultado;


wire tx_cpu;
reg cpu_rx;

initial	
begin
    clk = 1'b0;
    rate = 1'b0;
    rst = 1'b0;
    cpu_rx= 1'b1;
    
    #10 rst= 1'b1;
    #160 cpu_rx = 1'b0;
            
    #160 cpu_rx = 1'b0;
    #160 cpu_rx = 1'b1;
    #160 cpu_rx = 1'b1;
    #160 cpu_rx = 1'b0;
    #160 cpu_rx = 1'b0;
    #160 cpu_rx = 1'b0;
    #160 cpu_rx = 1'b0;
    #160 cpu_rx = 1'b0;
    
    #160 cpu_rx = 1'b1;
    
    #160 cpu_rx = 1'b0;
             
     #160 cpu_rx = 1'b1;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b1;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b0;
     
     #160 cpu_rx = 1'b1;
     
     #160 cpu_rx = 1'b0;
             
     #160 cpu_rx = 1'b1;
     #160 cpu_rx = 1'b1;
     #160 cpu_rx = 1'b1;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b1;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b0;
     
     #160 cpu_rx = 1'b1;
    
      #160 cpu_rx = 1'b0;
                
        #160 cpu_rx = 1'b0;
        #160 cpu_rx = 1'b1;
        #160 cpu_rx = 1'b1;
        #160 cpu_rx = 1'b0;
        #160 cpu_rx = 1'b0;
        #160 cpu_rx = 1'b0;
        #160 cpu_rx = 1'b0;
        #160 cpu_rx = 1'b0;
        
        #160 cpu_rx = 1'b1;
        
        #160 cpu_rx = 1'b0;
                 
         #160 cpu_rx = 1'b1;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b1;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         
         #160 cpu_rx = 1'b1;
         
         #160 cpu_rx = 1'b0;
                 
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b1;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         
         #160 cpu_rx = 1'b1;
    #500000000 $finish;
end
always #2.5 clk=~clk;
always #5 rate=~rate;

tx #(.NB_DATA(NB_DATA), .SB_TICK(SB_TICK))
u_tx
(
    .i_clk(clk),
    .i_rst(rst),
    .i_tx_start(int_tx),
    .i_tick(rate),
    .i_data(interfaz_tx_data),       
    .o_done_tx(tx_interfaz_done_data),       
    .o_tx(tx_cpu) 
);

rx #(.NB_DATA(NB_DATA), .SB_TICK(SB_TICK))
u_rx
(
    .i_clk(clk),
    .i_rst(rst),
    .i_bit(cpu_rx),                  
    .i_tick(rate),
    .o_done_data(rx_interfaz_done_data),  
    .o_data(rx_interfaz_data)      
);

    interfaz_tx #(.NB_DATA(NB_DATA))
    u_interfaztx
(
    .i_clk(clk),
    .i_rst(rst),
    .i_resultado(resultado),
    .i_done_alu(done_alu_tx),
    .i_done_tx(tx_interfaz_done_data),
    .o_data(interfaz_tx_data),
    .o_int_tx(int_tx)
);


    interfaz_rx #(.NB_DATA(NB_DATA), .NB_OPERADOR(NB_OPERADOR))
    u_interfazrx
(
    .i_clk(clk),
    .i_rst(rst),
    .i_data(rx_interfaz_data),
    .i_done_data(rx_interfaz_done_data),
    .o_a(dato_a), 
    .o_b(dato_b), 
    .o_op(operador), 
    .o_rx_alu_done(rx_alu_done)
);

    ALU #(.NB_DATA(NB_DATA), .NB_OPERADOR(NB_OPERADOR))
    u_alu
(
     .i_dato_a(dato_a),
     .i_dato_b(dato_b),
     .i_operador(operador),
     .i_alu_valid(rx_alu_done),
     .o_done_alu_tx(done_alu_tx),
     .o_resultado(resultado) 
);

endmodule
module tb_top_gral();


localparam  NB_DATA    =  8;
localparam SB_TICK = 16;
localparam  NB_OPERADOR    =  6;

reg clk;
reg rst;
reg rate;


wire tx_interfaz_done_data;
wire [NB_DATA-1:0] interfaz_tx_data;
wire int_tx;  

wire rx_interfaz_done_data;
wire [NB_DATA-1:0] rx_interfaz_data;

wire [NB_DATA-1 : 0] dato_a;
wire [NB_DATA-1 : 0] dato_b;
wire [NB_OPERADOR-1 : 0] operador;
wire rx_alu_done;
wire done_alu_tx;
wire [NB_DATA-1 : 0] resultado;


wire tx_cpu;
reg cpu_rx;

initial	
begin
    clk = 1'b0;
    rate = 1'b0;
    rst = 1'b0;
    cpu_rx= 1'b1;
    
    #10 rst= 1'b1;
    #160 cpu_rx = 1'b0;
            
    #160 cpu_rx = 1'b0;
    #160 cpu_rx = 1'b1;
    #160 cpu_rx = 1'b1;
    #160 cpu_rx = 1'b0;
    #160 cpu_rx = 1'b0;
    #160 cpu_rx = 1'b0;
    #160 cpu_rx = 1'b0;
    #160 cpu_rx = 1'b0;
    
    #160 cpu_rx = 1'b1;
    
    #160 cpu_rx = 1'b0;
             
     #160 cpu_rx = 1'b1;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b1;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b0;
     
     #160 cpu_rx = 1'b1;
     
     #160 cpu_rx = 1'b0;
             
     #160 cpu_rx = 1'b1;
     #160 cpu_rx = 1'b1;
     #160 cpu_rx = 1'b1;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b1;
     #160 cpu_rx = 1'b0;
     #160 cpu_rx = 1'b0;
     
     #160 cpu_rx = 1'b1;
    
      #160 cpu_rx = 1'b0;
                
        #160 cpu_rx = 1'b0;
        #160 cpu_rx = 1'b1;
        #160 cpu_rx = 1'b1;
        #160 cpu_rx = 1'b0;
        #160 cpu_rx = 1'b0;
        #160 cpu_rx = 1'b0;
        #160 cpu_rx = 1'b0;
        #160 cpu_rx = 1'b0;
        
        #160 cpu_rx = 1'b1;
        
        #160 cpu_rx = 1'b0;
                 
         #160 cpu_rx = 1'b1;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b1;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         
         #160 cpu_rx = 1'b1;
         
         #160 cpu_rx = 1'b0;
                 
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b1;
         #160 cpu_rx = 1'b0;
         #160 cpu_rx = 1'b0;
         
         #160 cpu_rx = 1'b1;
    #500000000 $finish;
end
always #2.5 clk=~clk;
always #5 rate=~rate;

tx #(.NB_DATA(NB_DATA), .SB_TICK(SB_TICK))
u_tx
(
    .i_clk(clk),
    .i_rst(rst),
    .i_tx_start(int_tx),
    .i_tick(rate),
    .i_data(interfaz_tx_data),       
    .o_done_tx(tx_interfaz_done_data),       
    .o_tx(tx_cpu) 
);

rx #(.NB_DATA(NB_DATA), .SB_TICK(SB_TICK))
u_rx
(
    .i_clk(clk),
    .i_rst(rst),
    .i_bit(cpu_rx),                  
    .i_tick(rate),
    .o_done_data(rx_interfaz_done_data),  
    .o_data(rx_interfaz_data)      
);

    interfaz_tx #(.NB_DATA(NB_DATA))
    u_interfaztx
(
    .i_clk(clk),
    .i_rst(rst),
    .i_resultado(resultado),
    .i_done_alu(done_alu_tx),
    .i_done_tx(tx_interfaz_done_data),
    .o_data(interfaz_tx_data),
    .o_int_tx(int_tx)
);


    interfaz_rx #(.NB_DATA(NB_DATA), .NB_OPERADOR(NB_OPERADOR))
    u_interfazrx
(
    .i_clk(clk),
    .i_rst(rst),
    .i_data(rx_interfaz_data),
    .i_done_data(rx_interfaz_done_data),
    .o_a(dato_a), 
    .o_b(dato_b), 
    .o_op(operador), 
    .o_rx_alu_done(rx_alu_done)
);

    ALU #(.NB_DATA(NB_DATA), .NB_OPERADOR(NB_OPERADOR))
    u_alu
(
     .i_dato_a(dato_a),
     .i_dato_b(dato_b),
     .i_operador(operador),
     .i_alu_valid(rx_alu_done),
     .o_done_alu_tx(done_alu_tx),
     .o_resultado(resultado) 
);

endmodule