data/full_repos/permissive/146618947/clase3_onoffswitch/flop.v
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data/verilator_xmls/6bd0c813-f334-4055-bbc9-b6abbb7cf0d4.xml
module flop (
             output reg Q,
             input      D,
             input      sClk
             );

   always @ (posedge sClk)
     begin
        Q <= D;
     end

endmodule
module flop (
             output reg Q,
             input      D,
             input      sClk
             );


   always @ (posedge sClk)
     begin
        Q <= D;
     end

endmodule