data/full_repos/permissive/117436613/mmix/regfile.sv
 line:45: before: "parameter"
1: b'%Error: data/full_repos/permissive/117436613/mmix/regfile.sv:23: Cannot find include file: mmix_defs.sv\n`include "mmix_defs.sv" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117436613/mmix,data/full_repos/permissive/117436613/mmix_defs.sv\n             data/full_repos/permissive/117436613/mmix,data/full_repos/permissive/117436613/mmix_defs.sv.v\n             data/full_repos/permissive/117436613/mmix,data/full_repos/permissive/117436613/mmix_defs.sv.sv\n             mmix_defs.sv\n             mmix_defs.sv.v\n             mmix_defs.sv.sv\n             obj_dir/mmix_defs.sv\n             obj_dir/mmix_defs.sv.v\n             obj_dir/mmix_defs.sv.sv\n%Error: Exiting due to 1 error(s)\n'
module regs(
	input logic clk,
	input	logic	reset_n,
	input logic	ra1_req,
	input logic	ra2_req,
	input logic	ra3_req,
	input logic	ra4_req,
	input logic[7:0] ra1,
	input logic[7:0] ra2,
	input logic[7:0] ra3,
	input logic[7:0] ra4,
	input logic we,
	input logic [7:0] wa,
	input logic[63:0] wd,
	output logic rd1_valid,
	output logic rd2_valid,
	output logic rd3_valid,
	output logic rd4_valid,
	output logic[63:0] rd1,
	output logic[63:0] rd2,
	output logic[63:0] rd3,
	output logic[63:0] rd4
	);
	

	reg[7:0]	prev_ra1, prev_ra2, prev_ra3, prev_ra4;
	
	logic	rd1_invalid, rd2_invalid, rd3_invalid, rd4_invalid;
	reg[7:0]	ra;
	wire[63:0] rd;
	reg[2:0] state;
	logic	rd1_dirty, rd2_dirty, rd3_dirty, rd4_dirty;
	
	sram rf(
		.clk,
		.reset_n,
		.ra,
		.we,
		.wa,
		.wd,
		.rd
	);
	
	assign rd1_valid = ~rd1_invalid;
	assign rd2_valid = ~rd2_invalid;
	assign rd3_valid = ~rd3_invalid;
	assign rd4_valid = ~rd4_invalid;
	
	assign rd1_invalid = ((prev_ra1 != ra1) & ra1_req) | rd1_dirty;
	assign rd2_invalid = ((prev_ra2 != ra2) & ra2_req) | rd2_dirty;
	assign rd3_invalid = ((prev_ra3 != ra3) & ra3_req) | rd3_dirty;
	assign rd4_invalid = ((prev_ra4 != ra4) & ra4_req) | rd4_dirty;
	
	always_latch begin
		if (reset_n == 0) begin
			prev_ra1 <= 0;
			prev_ra2 <= 0;
			prev_ra3 <= 0;
			prev_ra4 <= 0;




		end else begin
			if (state == 1) begin
				prev_ra1 <= ra1;
				rd1 <= rd;

			end
			if (state == 2) begin
				prev_ra2 <= ra2;
				rd2 <= rd;

			end
			if (state == 3) begin
				prev_ra3 <= ra3;
				rd3 <= rd;

			end
			if (state == 4) begin
				prev_ra4 <= ra4;
				rd4 <= rd;

			end
		










		end
	end
	
	always_ff @(posedge clk, negedge reset_n)
		if (reset_n == 0) begin
			ra <= 0;
			state <= 0;
			rd1_dirty <= 0;
			rd2_dirty <= 0;
			rd3_dirty <= 0;
			rd4_dirty <= 0;
		end else begin
			if (we) begin
				if ((wa == prev_ra1) | (wa == ra1))
					rd1_dirty <= 1;
				if ((wa == prev_ra2) | (wa == ra2))
					rd2_dirty <= 1;
				if ((wa == prev_ra3) | (wa == ra3))
					rd3_dirty <= 1;
				if ((wa == prev_ra4) | (wa == ra4))
					rd4_dirty <= 1;
			end else
				casex ({ rd1_invalid, rd2_invalid, rd3_invalid, rd4_invalid })
				4'b1xxx: begin
						ra <= ra1;
						state <= 1;
						rd1_dirty <= 0;
					end
				4'b01xx: begin
						ra <= ra2;
						state <= 2;
						rd2_dirty <= 0;
					end
				4'b001x: begin
						ra <= ra3;
						state <= 3;
						rd3_dirty <= 0;
					end
				4'b0001: begin
						ra <= ra4;
						state <= 4;
						rd4_dirty <= 0;
					end
				default: begin
						state <= 0;
					end
				endcase
		end
	
endmodule
module regs(
	input logic clk,
	input	logic	reset_n,
	input logic	ra1_req,
	input logic	ra2_req,
	input logic	ra3_req,
	input logic	ra4_req,
	input logic[7:0] ra1,
	input logic[7:0] ra2,
	input logic[7:0] ra3,
	input logic[7:0] ra4,
	input logic we,
	input logic [7:0] wa,
	input logic[63:0] wd,
	output logic rd1_valid,
	output logic rd2_valid,
	output logic rd3_valid,
	output logic rd4_valid,
	output logic[63:0] rd1,
	output logic[63:0] rd2,
	output logic[63:0] rd3,
	output logic[63:0] rd4
	);

	

	reg[7:0]	prev_ra1, prev_ra2, prev_ra3, prev_ra4;
	
	logic	rd1_invalid, rd2_invalid, rd3_invalid, rd4_invalid;
	reg[7:0]	ra;
	wire[63:0] rd;
	reg[2:0] state;
	logic	rd1_dirty, rd2_dirty, rd3_dirty, rd4_dirty;
	
	sram rf(
		.clk,
		.reset_n,
		.ra,
		.we,
		.wa,
		.wd,
		.rd
	);
	
	assign rd1_valid = ~rd1_invalid;
	assign rd2_valid = ~rd2_invalid;
	assign rd3_valid = ~rd3_invalid;
	assign rd4_valid = ~rd4_invalid;
	
	assign rd1_invalid = ((prev_ra1 != ra1) & ra1_req) | rd1_dirty;
	assign rd2_invalid = ((prev_ra2 != ra2) & ra2_req) | rd2_dirty;
	assign rd3_invalid = ((prev_ra3 != ra3) & ra3_req) | rd3_dirty;
	assign rd4_invalid = ((prev_ra4 != ra4) & ra4_req) | rd4_dirty;
	
	always_latch begin
		if (reset_n == 0) begin
			prev_ra1 <= 0;
			prev_ra2 <= 0;
			prev_ra3 <= 0;
			prev_ra4 <= 0;




		end else begin
			if (state == 1) begin
				prev_ra1 <= ra1;
				rd1 <= rd;

			end
			if (state == 2) begin
				prev_ra2 <= ra2;
				rd2 <= rd;

			end
			if (state == 3) begin
				prev_ra3 <= ra3;
				rd3 <= rd;

			end
			if (state == 4) begin
				prev_ra4 <= ra4;
				rd4 <= rd;

			end
		










		end
	end
	
	always_ff @(posedge clk, negedge reset_n)
		if (reset_n == 0) begin
			ra <= 0;
			state <= 0;
			rd1_dirty <= 0;
			rd2_dirty <= 0;
			rd3_dirty <= 0;
			rd4_dirty <= 0;
		end else begin
			if (we) begin
				if ((wa == prev_ra1) | (wa == ra1))
					rd1_dirty <= 1;
				if ((wa == prev_ra2) | (wa == ra2))
					rd2_dirty <= 1;
				if ((wa == prev_ra3) | (wa == ra3))
					rd3_dirty <= 1;
				if ((wa == prev_ra4) | (wa == ra4))
					rd4_dirty <= 1;
			end else
				casex ({ rd1_invalid, rd2_invalid, rd3_invalid, rd4_invalid })
				4'b1xxx: begin
						ra <= ra1;
						state <= 1;
						rd1_dirty <= 0;
					end
				4'b01xx: begin
						ra <= ra2;
						state <= 2;
						rd2_dirty <= 0;
					end
				4'b001x: begin
						ra <= ra3;
						state <= 3;
						rd3_dirty <= 0;
					end
				4'b0001: begin
						ra <= ra4;
						state <= 4;
						rd4_dirty <= 0;
					end
				default: begin
						state <= 0;
					end
				endcase
		end
	
endmodule