data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #4;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #4;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #2\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #4;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #4;\n    ^\n%Error: data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new/sim_xgmii_align.v:91: Cannot find file containing module: \'xgmii_rx_align\'\nxgmii_rx_align xgmii_rx_align_0(.CLK(clk), .RESET(reset), .XGMII_RXC(rxc), .XGMII_RXD(rxd), .ALGN_RXLEN(algn_rxlen), .ALGN_RXD(algn_rxd));\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new,data/full_repos/permissive/156650005/xgmii_rx_align\n             data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new,data/full_repos/permissive/156650005/xgmii_rx_align.v\n             data/full_repos/permissive/156650005/eth10g_capture.srcs/sim_1/new,data/full_repos/permissive/156650005/xgmii_rx_align.sv\n             xgmii_rx_align\n             xgmii_rx_align.v\n             xgmii_rx_align.sv\n             obj_dir/xgmii_rx_align\n             obj_dir/xgmii_rx_align.v\n             obj_dir/xgmii_rx_align.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_xgmii_align();

reg clk;
reg reset;
reg [63:0] rxd;
reg [7:0] rxc;

wire [63:0] algn_rxd;
wire [3:0] algn_rxlen;

initial begin
    clk = 0;
    forever clk = #1 !clk;
end

initial begin
    reset = 1;
    #10 reset = 0;
end

initial begin
    rxc = 8'b11111111;
    rxd = 64'h0707070707070707;
    #20;

    rxc = 8'b00000001;
    rxd = 64'hd5555555555555fb;
    #2;
    rxc = 8'b00000000;
    rxd = 64'hffffffffffffffff;
    #4;
    rxc = 8'b11111111;
    rxd = 64'h07070707070707fd;
    #2;

    rxc = 8'b00011111;
    rxd = 64'h555555fb07070707;
    #2;
    rxc = 8'b00000000;
    rxd = 64'hffffffffd5555555;
    #2;
    rxc = 8'b00000000;
    rxd = 64'hffffffffffffffff;
    #4;

    rxc = 8'b00011111;
    rxd = 64'h555555fb070707fd;
    #2
    rxc = 8'b00000000;
    rxd = 64'hffffffffd5555555;
    #2;
    rxc = 8'b00000000;
    rxd = 64'hffffffffffffffff;
    #4;
    rxc = 8'b11110000;
    rxd = 64'h070707fdffffffff;
    #2;

    rxc = 8'b00000001;
    rxd = 64'hd5555555555555fb;
    #2;
    rxc = 8'b00000000;
    rxd = 64'hffffffffffffffff;
    #4;
    rxc = 8'b11111111;
    rxd = 64'h07070707070707fd;
end

xgmii_rx_align xgmii_rx_align_0(.CLK(clk), .RESET(reset), .XGMII_RXC(rxc), .XGMII_RXD(rxd), .ALGN_RXLEN(algn_rxlen), .ALGN_RXD(algn_rxd));

endmodule
module sim_xgmii_align();


reg clk;
reg reset;
reg [63:0] rxd;
reg [7:0] rxc;

wire [63:0] algn_rxd;
wire [3:0] algn_rxlen;

initial begin
    clk = 0;
    forever clk = #1 !clk;
end

initial begin
    reset = 1;
    #10 reset = 0;
end

initial begin
    rxc = 8'b11111111;
    rxd = 64'h0707070707070707;
    #20;

    rxc = 8'b00000001;
    rxd = 64'hd5555555555555fb;
    #2;
    rxc = 8'b00000000;
    rxd = 64'hffffffffffffffff;
    #4;
    rxc = 8'b11111111;
    rxd = 64'h07070707070707fd;
    #2;

    rxc = 8'b00011111;
    rxd = 64'h555555fb07070707;
    #2;
    rxc = 8'b00000000;
    rxd = 64'hffffffffd5555555;
    #2;
    rxc = 8'b00000000;
    rxd = 64'hffffffffffffffff;
    #4;

    rxc = 8'b00011111;
    rxd = 64'h555555fb070707fd;
    #2
    rxc = 8'b00000000;
    rxd = 64'hffffffffd5555555;
    #2;
    rxc = 8'b00000000;
    rxd = 64'hffffffffffffffff;
    #4;
    rxc = 8'b11110000;
    rxd = 64'h070707fdffffffff;
    #2;

    rxc = 8'b00000001;
    rxd = 64'hd5555555555555fb;
    #2;
    rxc = 8'b00000000;
    rxd = 64'hffffffffffffffff;
    #4;
    rxc = 8'b11111111;
    rxd = 64'h07070707070707fd;
end

xgmii_rx_align xgmii_rx_align_0(.CLK(clk), .RESET(reset), .XGMII_RXC(rxc), .XGMII_RXD(rxd), .ALGN_RXLEN(algn_rxlen), .ALGN_RXD(algn_rxd));

endmodule