data/full_repos/permissive/113890540/icestorm version/j1.v
 line:106: before: "."
1: b'%Error: Cannot find file containing module: version,data/full_repos/permissive/113890540\n        ... Looked in:\n             data/full_repos/permissive/113890540/icestorm/version,data/full_repos/permissive/113890540\n             data/full_repos/permissive/113890540/icestorm/version,data/full_repos/permissive/113890540.v\n             data/full_repos/permissive/113890540/icestorm/version,data/full_repos/permissive/113890540.sv\n             version,data/full_repos/permissive/113890540\n             version,data/full_repos/permissive/113890540.v\n             version,data/full_repos/permissive/113890540.sv\n             obj_dir/version,data/full_repos/permissive/113890540\n             obj_dir/version,data/full_repos/permissive/113890540.v\n             obj_dir/version,data/full_repos/permissive/113890540.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113890540/icestorm\n%Error: Cannot find file containing module: version/j1.v\n%Error: Exiting due to 3 error(s)\n'
module j1(
  input wire clk,
  input wire resetq,

  output wire io_rd,
  output wire io_wr,
  
  output wire [15:0] mem_addr,
  output wire mem_wr,
  
  output wire [15:0] dout,
  input  wire [15:0] io_din,

  output wire [12:0] code_addr,
  input  wire [15:0] insn_from_memory,
  
  input  wire [7:0] int_rqst
);  

  reg [4:0] rsp, rspN;
  reg [4:0] dsp, dspN;
  reg [15:0] st0, st0N;
  reg dstkW;
  reg rstkW;
  wire [15:0] rstkD;
  reg [15:0] insn;
  reg [13:0] pc, pcN;
  
  reg interrupt_enable = 0;  
  wire interrupt_request = |( int_rqst );
  wire interrupt = interrupt_request & interrupt_enable;
  
  always @* begin
    casex (int_rqst)
      8'b1xxxxxxx : insn = interrupt ? 16'h5DFF : insn_from_memory;
      8'b01xxxxxx : insn = interrupt ? 16'h5DFE : insn_from_memory;
      8'b001xxxxx : insn = interrupt ? 16'h5DFD : insn_from_memory;
      8'b0001xxxx : insn = interrupt ? 16'h5DFC : insn_from_memory;
      8'b00001xxx : insn = interrupt ? 16'h5DFB : insn_from_memory;
      8'b000001xx : insn = interrupt ? 16'h5DFA : insn_from_memory;
      8'b0000001x : insn = interrupt ? 16'h5DF9 : insn_from_memory;
      8'b00000001 : insn = interrupt ? 16'h5DF8 : insn_from_memory;
      default     : insn = insn_from_memory; 
    endcase
  end

  wire [13:0] pc_plus_1 = pc + {13'b0, ~interrupt};
  wire fetch = pc[13] & ~interrupt;

  reg notreboot = 0;

  assign mem_addr = st0[15:0];
  assign code_addr = pcN;


  wire [15:0] st1, rst0;
  reg [1:0] dspI, rspI;

  stack2 #(.DEPTH(32)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
  stack2 #(.DEPTH(32)) dstack(.clk(clk), .rd(st1),  .we(dstkW), .wd(st0),   .delta(dspI));

  wire [16:0] minus = {1'b1, ~st0} + st1 + 1;
  
  wire signedless = st0[15] ^ st1[15] ? st1[15] : minus[16];
  wire unsignedless = minus[16];
  wire zeroflag = minus[15:0] == 0;



SB_MAC16 i_sbmac16 (
    .A(st0),
    .B(st1),
    .C(16'h0000),
    .D(16'h0000),
    .O(umstar),
    .CLK(0),
    .CE(1),
    .IRSTTOP(0),
    .IRSTBOT(0),
    .ORSTTOP(0),
    .ORSTBOT(0),
    .AHOLD(1),
    .BHOLD(1),
    .CHOLD(0),
    .DHOLD(0),
    .OHOLDTOP(0),
    .OHOLDBOT(0),
    .OLOADTOP(0),
    .OLOADBOT(0),
    .ADDSUBTOP(0),
    .ADDSUBBOT(0),
    .CO(),
    .CI(0),

    .ACCUMCI(),
    .ACCUMCO(),
    .SIGNEXTIN(0),
    .SIGNEXTOUT()     );

defparam i_sbmac16.B_SIGNED                            = 1'b0 ;
defparam i_sbmac16.A_SIGNED                            = 1'b0 ;
defparam i_sbmac16.BOTOUTPUT_SELECT                    = 2'b11 ;
defparam i_sbmac16.TOPOUTPUT_SELECT                    = 2'b11 ;


  wire [31:0] umstar;


  always @*
  begin

    casez ({fetch, insn[15:8]})


      9'b0_011_00001: st0N = st1;
      9'b0_011_00010: st0N = st0 + st1;
      9'b0_011_00011: st0N = st0 & st1;

      9'b0_011_00100: st0N = st0 | st1;
      9'b0_011_00101: st0N = st0 ^ st1;
      9'b0_011_00110: st0N = ~st0;
      9'b0_011_00111: st0N = {16{zeroflag}};

      9'b0_011_01000: st0N = {16{signedless}};
      9'b0_011_01001: st0N = {st0[15], st0[15:1]};
      9'b0_011_01010: st0N = {st0[14:0], 1'b0};
      9'b0_011_01011: st0N = rst0;

      9'b0_011_01100: st0N = minus[15:0];
      9'b0_011_01101: st0N = io_din;
      9'b0_011_01110: st0N = {11'b0, dsp};
      9'b0_011_01111: st0N = {16{unsignedless}};


      9'b1_???_?????: st0N = insn;

      9'b0_1??_?????: st0N = { 1'b0, insn[14:0] };


      9'b0_001_?????: st0N = st1;




      9'b0_011_10000: st0N = st1 << st0;
      9'b0_011_10001: st0N = st1 >> st0;
      9'b0_011_10010: st0N = $signed(st1) >>> st0;
      9'b0_011_10011: st0N = {11'b0, rsp};

      9'b0_011_10100: st0N = umstar[15:0];
      9'b0_011_10101: st0N = umstar[31:16];
      9'b0_011_10110: st0N = st0 + 1;
      9'b0_011_10111: st0N = st0 - 1;

      default: st0N = st0;
    endcase
  end

  wire func_T_N =   (insn[6:4] == 1);
  wire func_T_R =   (insn[6:4] == 2);
  wire func_write = (insn[6:4] == 3);
  wire func_iow =   (insn[6:4] == 4);
  wire func_ior =   (insn[6:4] == 5);
  wire func_dint =  (insn[6:4] == 6);
  wire func_eint =  (insn[6:4] == 7);

  wire is_alu = notreboot & !fetch & (insn[15:13] == 3'b011);

  assign mem_wr = is_alu & func_write;
  assign io_wr  = is_alu & func_iow;
  assign io_rd  = is_alu & func_ior;
  assign dout   = st1;

  wire eint = is_alu & func_eint;
  wire dint = is_alu & func_dint;

  wire interrupt_enableN = (interrupt_enable | eint) & ~(interrupt | dint);


  assign rstkD = (insn[13] == 1'b0) ? {1'b0, pc_plus_1, interrupt_enable} : st0;

  always @*
  begin
    casez ({fetch, insn[15:13]})
    4'b1_???,
    4'b0_1??:   {dstkW, dspI} = {1'b1,      2'b01};
    4'b0_001:   {dstkW, dspI} = {1'b0,      2'b11};
    4'b0_011:   {dstkW, dspI} = {func_T_N,  {insn[1:0]}};
    default:    {dstkW, dspI} = {1'b0,      2'b00};
    endcase
    dspN = dsp + {dspI[1], dspI[1], dspI[1], dspI};

    casez ({fetch, insn[15:13]})
    4'b1_???:   {rstkW, rspI} = {1'b0,      2'b11};
    4'b0_010:   {rstkW, rspI} = {1'b1,      2'b01};
    4'b0_011:   {rstkW, rspI} = {func_T_R,  insn[3:2]};
    default:    {rstkW, rspI} = {1'b0,      2'b00};
    endcase
    rspN = rsp + {rspI[1], rspI[1], rspI[1], rspI};

    casez ({notreboot, fetch, insn[15:13], insn[7], |st0})
    7'b0_0_???_?_?:   pcN = 0;
    7'b1_0_000_?_?,
    7'b1_0_010_?_?,
    7'b1_0_001_?_0:   pcN = {1'b0, insn[12:0]};
    7'b1_1_???_?_?,
    7'b1_0_011_1_?:   pcN = rst0[14:1];
    default:          pcN = pc_plus_1;
    endcase
  end

  always @(negedge resetq or posedge clk)
  begin
    if (!resetq) begin
      notreboot <= 0;
      { pc, dsp, rsp, st0, interrupt_enable} <= 0;
    end else begin
      notreboot <= 1;
      { pc, dsp, rsp, st0, interrupt_enable} <= { pcN, dspN, rspN, st0N, interrupt_enableN };
    end
  end

endmodule
module j1(
  input wire clk,
  input wire resetq,

  output wire io_rd,
  output wire io_wr,
  
  output wire [15:0] mem_addr,
  output wire mem_wr,
  
  output wire [15:0] dout,
  input  wire [15:0] io_din,

  output wire [12:0] code_addr,
  input  wire [15:0] insn_from_memory,
  
  input  wire [7:0] int_rqst
);
  

  reg [4:0] rsp, rspN;
  reg [4:0] dsp, dspN;
  reg [15:0] st0, st0N;
  reg dstkW;
  reg rstkW;
  wire [15:0] rstkD;
  reg [15:0] insn;
  reg [13:0] pc, pcN;
  
  reg interrupt_enable = 0;  
  wire interrupt_request = |( int_rqst );
  wire interrupt = interrupt_request & interrupt_enable;
  
  always @* begin
    casex (int_rqst)
      8'b1xxxxxxx : insn = interrupt ? 16'h5DFF : insn_from_memory;
      8'b01xxxxxx : insn = interrupt ? 16'h5DFE : insn_from_memory;
      8'b001xxxxx : insn = interrupt ? 16'h5DFD : insn_from_memory;
      8'b0001xxxx : insn = interrupt ? 16'h5DFC : insn_from_memory;
      8'b00001xxx : insn = interrupt ? 16'h5DFB : insn_from_memory;
      8'b000001xx : insn = interrupt ? 16'h5DFA : insn_from_memory;
      8'b0000001x : insn = interrupt ? 16'h5DF9 : insn_from_memory;
      8'b00000001 : insn = interrupt ? 16'h5DF8 : insn_from_memory;
      default     : insn = insn_from_memory; 
    endcase
  end

  wire [13:0] pc_plus_1 = pc + {13'b0, ~interrupt};
  wire fetch = pc[13] & ~interrupt;

  reg notreboot = 0;

  assign mem_addr = st0[15:0];
  assign code_addr = pcN;


  wire [15:0] st1, rst0;
  reg [1:0] dspI, rspI;

  stack2 #(.DEPTH(32)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
  stack2 #(.DEPTH(32)) dstack(.clk(clk), .rd(st1),  .we(dstkW), .wd(st0),   .delta(dspI));

  wire [16:0] minus = {1'b1, ~st0} + st1 + 1;
  
  wire signedless = st0[15] ^ st1[15] ? st1[15] : minus[16];
  wire unsignedless = minus[16];
  wire zeroflag = minus[15:0] == 0;



SB_MAC16 i_sbmac16 (
    .A(st0),
    .B(st1),
    .C(16'h0000),
    .D(16'h0000),
    .O(umstar),
    .CLK(0),
    .CE(1),
    .IRSTTOP(0),
    .IRSTBOT(0),
    .ORSTTOP(0),
    .ORSTBOT(0),
    .AHOLD(1),
    .BHOLD(1),
    .CHOLD(0),
    .DHOLD(0),
    .OHOLDTOP(0),
    .OHOLDBOT(0),
    .OLOADTOP(0),
    .OLOADBOT(0),
    .ADDSUBTOP(0),
    .ADDSUBBOT(0),
    .CO(),
    .CI(0),

    .ACCUMCI(),
    .ACCUMCO(),
    .SIGNEXTIN(0),
    .SIGNEXTOUT()     );

defparam i_sbmac16.B_SIGNED                            = 1'b0 ;
defparam i_sbmac16.A_SIGNED                            = 1'b0 ;
defparam i_sbmac16.BOTOUTPUT_SELECT                    = 2'b11 ;
defparam i_sbmac16.TOPOUTPUT_SELECT                    = 2'b11 ;


  wire [31:0] umstar;


  always @*
  begin

    casez ({fetch, insn[15:8]})


      9'b0_011_00001: st0N = st1;
      9'b0_011_00010: st0N = st0 + st1;
      9'b0_011_00011: st0N = st0 & st1;

      9'b0_011_00100: st0N = st0 | st1;
      9'b0_011_00101: st0N = st0 ^ st1;
      9'b0_011_00110: st0N = ~st0;
      9'b0_011_00111: st0N = {16{zeroflag}};

      9'b0_011_01000: st0N = {16{signedless}};
      9'b0_011_01001: st0N = {st0[15], st0[15:1]};
      9'b0_011_01010: st0N = {st0[14:0], 1'b0};
      9'b0_011_01011: st0N = rst0;

      9'b0_011_01100: st0N = minus[15:0];
      9'b0_011_01101: st0N = io_din;
      9'b0_011_01110: st0N = {11'b0, dsp};
      9'b0_011_01111: st0N = {16{unsignedless}};


      9'b1_???_?????: st0N = insn;

      9'b0_1??_?????: st0N = { 1'b0, insn[14:0] };


      9'b0_001_?????: st0N = st1;




      9'b0_011_10000: st0N = st1 << st0;
      9'b0_011_10001: st0N = st1 >> st0;
      9'b0_011_10010: st0N = $signed(st1) >>> st0;
      9'b0_011_10011: st0N = {11'b0, rsp};

      9'b0_011_10100: st0N = umstar[15:0];
      9'b0_011_10101: st0N = umstar[31:16];
      9'b0_011_10110: st0N = st0 + 1;
      9'b0_011_10111: st0N = st0 - 1;

      default: st0N = st0;
    endcase
  end

  wire func_T_N =   (insn[6:4] == 1);
  wire func_T_R =   (insn[6:4] == 2);
  wire func_write = (insn[6:4] == 3);
  wire func_iow =   (insn[6:4] == 4);
  wire func_ior =   (insn[6:4] == 5);
  wire func_dint =  (insn[6:4] == 6);
  wire func_eint =  (insn[6:4] == 7);

  wire is_alu = notreboot & !fetch & (insn[15:13] == 3'b011);

  assign mem_wr = is_alu & func_write;
  assign io_wr  = is_alu & func_iow;
  assign io_rd  = is_alu & func_ior;
  assign dout   = st1;

  wire eint = is_alu & func_eint;
  wire dint = is_alu & func_dint;

  wire interrupt_enableN = (interrupt_enable | eint) & ~(interrupt | dint);


  assign rstkD = (insn[13] == 1'b0) ? {1'b0, pc_plus_1, interrupt_enable} : st0;

  always @*
  begin
    casez ({fetch, insn[15:13]})
    4'b1_???,
    4'b0_1??:   {dstkW, dspI} = {1'b1,      2'b01};
    4'b0_001:   {dstkW, dspI} = {1'b0,      2'b11};
    4'b0_011:   {dstkW, dspI} = {func_T_N,  {insn[1:0]}};
    default:    {dstkW, dspI} = {1'b0,      2'b00};
    endcase
    dspN = dsp + {dspI[1], dspI[1], dspI[1], dspI};

    casez ({fetch, insn[15:13]})
    4'b1_???:   {rstkW, rspI} = {1'b0,      2'b11};
    4'b0_010:   {rstkW, rspI} = {1'b1,      2'b01};
    4'b0_011:   {rstkW, rspI} = {func_T_R,  insn[3:2]};
    default:    {rstkW, rspI} = {1'b0,      2'b00};
    endcase
    rspN = rsp + {rspI[1], rspI[1], rspI[1], rspI};

    casez ({notreboot, fetch, insn[15:13], insn[7], |st0})
    7'b0_0_???_?_?:   pcN = 0;
    7'b1_0_000_?_?,
    7'b1_0_010_?_?,
    7'b1_0_001_?_0:   pcN = {1'b0, insn[12:0]};
    7'b1_1_???_?_?,
    7'b1_0_011_1_?:   pcN = rst0[14:1];
    default:          pcN = pc_plus_1;
    endcase
  end

  always @(negedge resetq or posedge clk)
  begin
    if (!resetq) begin
      notreboot <= 0;
      { pc, dsp, rsp, st0, interrupt_enable} <= 0;
    end else begin
      notreboot <= 1;
      { pc, dsp, rsp, st0, interrupt_enable} <= { pcN, dspN, rspN, st0N, interrupt_enableN };
    end
  end

endmodule