data/full_repos/permissive/135852214/Verilog/dec_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dec_test.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/dec_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n   #10 in = i;\n   ^\n%Error: data/full_repos/permissive/135852214/Verilog/dec_test.v:34: Cannot find file containing module: \'decoder\'\n decoder uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/decoder\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/decoder.v\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/decoder.sv\n             decoder\n             decoder.v\n             decoder.sv\n             obj_dir/decoder\n             obj_dir/decoder.v\n             obj_dir/decoder.sv\n%Warning-WIDTH: data/full_repos/permissive/135852214/Verilog/dec_test.v:46: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                          : ... In instance dec_test\n   #10 in = i;\n          ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dec_test;


	reg [3:0] in;


	wire [6:0] out;
	integer i;

	decoder uut (
		.in(in), 
		.out(out)
	);

	initial begin

		in = 0;


		#100;
      for (i = 0; i < 16; i = i+1)
			#10 in = i;


	end
      
endmodule
module dec_test;



	reg [3:0] in;


	wire [6:0] out;
	integer i;

	decoder uut (
		.in(in), 
		.out(out)
	);

	initial begin

		in = 0;


		#100;
      for (i = 0; i < 16; i = i+1)
			#10 in = i;


	end
      
endmodule