data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v
 line:82: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:15: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("new_rx_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:16: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,new_rx_tb);\n           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #1000 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #30000;\n ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:54: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:58: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:62: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:64: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:72: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:76: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:80: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/vita_200/new_rx_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #8000;\n ^\n%Error: Exiting due to 9 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module new_rx_tb();

   reg clk    = 0;
   reg reset  = 1;
   
   always #10 clk = ~clk;
   
   initial $dumpfile("new_rx_tb.vcd");
   initial $dumpvars(0,new_rx_tb);

   initial
     begin
	#1000 reset = 0;
	#30000;
	$finish;
     end
   
   reg [7:0]   set_addr;
   reg [31:0]  set_data;
   reg 	       set_stb = 1'b0;
   
   reg [63:0]  vita_time;
   reg [31:0]  sample;
   reg 	       strobe;
   
   wire        run, full;

   wire [63:0] err_tdata;
   wire        err_tlast, err_tvalid, err_tready;

   wire [63:0] o_tdata;
   wire        o_tlast, o_tvalid;
   reg 	       o_tready;
   
   task send_command;
      input [63:0] send_time;
      input 	   send_at;
      input 	   chain;
      input 	   reload;
      input 	   stop;
      input [31:0] len;

      begin
	 set_stb <= 1;
	 set_addr <= 0;
	 set_data <= { send_at, chain, reload, stop, len };
	 @(posedge clk);
	 set_stb <= 1;
	 set_addr <= 1;
	 set_data <= send_time[63:32];
	 @(posedge clk);
	 set_stb <= 1;
	 set_addr <= 2;
	 set_data <= send_time[31:0];
	 @(posedge clk);
	 set_stb <= 0;
	 @(posedge clk);
      end
   endtask
   
   initial
     begin
	o_tready <= 0;
	while(reset)
	  @(posedge clk);
	set_stb <= 1;
	set_addr <= 8; 
	set_data <= 18;
	@(posedge clk);
	set_stb <= 1;
	set_addr <= 9; 
	set_data <= 32'hF00D_1234;
	@(posedge clk);
	
	send_command(64'h100, 1, 0, 0,0,150);
	send_command(64'h200, 1, 0, 0,0,4);


	#8000;
	o_tready <= 1;
     end
   
   always @(posedge clk)
     if(reset)
       vita_time <= 0;
     else
       vita_time <= vita_time + 1;

   new_rx_control #(.BASE(0)) rx_control
     (.clk(clk), .reset(reset), .clear(1'b0),
      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
      .vita_time(vita_time),
      .run(run), .eob(eob), .strobe(strobe), .full(full),
      .err_tdata(err_tdata), .err_tlast(err_tlast), .err_tvalid(err_tvalid), .err_tready(err_tready),
      .debug());

   new_rx_framer #(.BASE(8)) rx_framer
     (.clk(clk), .reset(reset), .clear(1'b0),
      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
      .vita_time(vita_time),
      .strobe(strobe), .sample(sample), .run(run), .eob(eob), .full(full),
      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
      );
   
   always @*
     strobe <= run;


   always @* sample <= vita_time[31:0];
   
   always @(posedge clk)
     if(o_tvalid & o_tready)
       if(o_tlast)
	 $display("%x\tLAST\n",o_tdata);
       else
	 $display("%x",o_tdata);

   assign err_tready = 1;
   
   always @(posedge clk)
     if(err_tvalid & err_tready)
       if(err_tlast)
	 $display("\t\t\t\tERR LAST \t%x",err_tdata);
       else
	 $display("\t\t\t\tERR\t\t%x",err_tdata);
   
endmodule
module new_rx_tb();


   reg clk    = 0;
   reg reset  = 1;
   
   always #10 clk = ~clk;
   
   initial $dumpfile("new_rx_tb.vcd");
   initial $dumpvars(0,new_rx_tb);

   initial
     begin
	#1000 reset = 0;
	#30000;
	$finish;
     end
   
   reg [7:0]   set_addr;
   reg [31:0]  set_data;
   reg 	       set_stb = 1'b0;
   
   reg [63:0]  vita_time;
   reg [31:0]  sample;
   reg 	       strobe;
   
   wire        run, full;

   wire [63:0] err_tdata;
   wire        err_tlast, err_tvalid, err_tready;

   wire [63:0] o_tdata;
   wire        o_tlast, o_tvalid;
   reg 	       o_tready;
   
   task send_command;
      input [63:0] send_time;
      input 	   send_at;
      input 	   chain;
      input 	   reload;
      input 	   stop;
      input [31:0] len;

      begin
	 set_stb <= 1;
	 set_addr <= 0;
	 set_data <= { send_at, chain, reload, stop, len };
	 @(posedge clk);
	 set_stb <= 1;
	 set_addr <= 1;
	 set_data <= send_time[63:32];
	 @(posedge clk);
	 set_stb <= 1;
	 set_addr <= 2;
	 set_data <= send_time[31:0];
	 @(posedge clk);
	 set_stb <= 0;
	 @(posedge clk);
      end
   endtask
   
   initial
     begin
	o_tready <= 0;
	while(reset)
	  @(posedge clk);
	set_stb <= 1;
	set_addr <= 8; 
	set_data <= 18;
	@(posedge clk);
	set_stb <= 1;
	set_addr <= 9; 
	set_data <= 32'hF00D_1234;
	@(posedge clk);
	
	send_command(64'h100, 1, 0, 0,0,150);
	send_command(64'h200, 1, 0, 0,0,4);


	#8000;
	o_tready <= 1;
     end
   
   always @(posedge clk)
     if(reset)
       vita_time <= 0;
     else
       vita_time <= vita_time + 1;

   new_rx_control #(.BASE(0)) rx_control
     (.clk(clk), .reset(reset), .clear(1'b0),
      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
      .vita_time(vita_time),
      .run(run), .eob(eob), .strobe(strobe), .full(full),
      .err_tdata(err_tdata), .err_tlast(err_tlast), .err_tvalid(err_tvalid), .err_tready(err_tready),
      .debug());

   new_rx_framer #(.BASE(8)) rx_framer
     (.clk(clk), .reset(reset), .clear(1'b0),
      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
      .vita_time(vita_time),
      .strobe(strobe), .sample(sample), .run(run), .eob(eob), .full(full),
      .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
      );
   
   always @*
     strobe <= run;


   always @* sample <= vita_time[31:0];
   
   always @(posedge clk)
     if(o_tvalid & o_tready)
       if(o_tlast)
	 $display("%x\tLAST\n",o_tdata);
       else
	 $display("%x",o_tdata);

   assign err_tready = 1;
   
   always @(posedge clk)
     if(err_tvalid & err_tready)
       if(err_tlast)
	 $display("\t\t\t\tERR LAST \t%x",err_tdata);
       else
	 $display("\t\t\t\tERR\t\t%x",err_tdata);
   
endmodule