data/full_repos/permissive/143278/ivltests/land5.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/land5.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (flag !== 0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/land5.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (flag !== 1) begin\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/land5.v:8: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'a\' generates 2 bits.\n                                                                    : ... In instance main\n     flag = a && b;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/land5.v:8: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'b\' generates 2 bits.\n                                                                    : ... In instance main\n     flag = a && b;\n              ^~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [1:0] a, b;
   reg	     flag;

   (* ivl_combinational *)
   always @(a, b)
     flag = a && b;

   (* ivl_synthesis_off *)
   initial begin
      a = 1;
      b = 0;
      #1 if (flag !== 0) begin
	 $display("FAILED -- a=%b, b=%b, flag=%b", a, b, flag);
	 $finish;
      end

      b = 2;
      #1 if (flag !== 1) begin
	 $display("FAILED -- a=%b, b=%b, flag=%b", a, b, flag);
	 $finish;
      end

      $display("PASSED");

   end

endmodule
module main;


   reg [1:0] a, b;
   reg	     flag;

   (* ivl_combinational *)
   always @(a, b)
     flag = a && b;

   (* ivl_synthesis_off *)
   initial begin
      a = 1;
      b = 0;
      #1 if (flag !== 0) begin
	 $display("FAILED -- a=%b, b=%b, flag=%b", a, b, flag);
	 $finish;
      end

      b = 2;
      #1 if (flag !== 1) begin
	 $display("FAILED -- a=%b, b=%b, flag=%b", a, b, flag);
	 $finish;
      end

      $display("PASSED");

   end

endmodule