data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Top.v
1: b'%Error: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Top.v:70: Cannot find file containing module: \'InstMemory\'\n    InstMemory u2(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new,data/full_repos/permissive/194376374/InstMemory\n             data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new,data/full_repos/permissive/194376374/InstMemory.v\n             data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new,data/full_repos/permissive/194376374/InstMemory.sv\n             InstMemory\n             InstMemory.v\n             InstMemory.sv\n             obj_dir/InstMemory\n             obj_dir/InstMemory.v\n             obj_dir/InstMemory.sv\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Top.v:77: Cannot find file containing module: \'Ctr\'\n    Ctr mainCtr(\n    ^~~\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Top.v:93: Cannot find file containing module: \'signext\'\n    signext u1(\n    ^~~~~~~\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Top.v:99: Cannot find file containing module: \'registers\'\n    registers u0(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Top.v:114: Cannot find file containing module: \'ALUctr\'\n    ALUctr u3(\n    ^~~~~~\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Top.v:121: Cannot find file containing module: \'ALU\'\n    ALU u4(\n    ^~~\n%Error: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Top.v:130: Cannot find file containing module: \'dataMemory\'\n    dataMemory u5(\n    ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Top.v:144: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                                                                     : ... In instance Top\n  else if (Zero && BRANCH) PC<=PC+4+(INST[15:0]<<2);\n                                               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/new/Top.v:145: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s SEL generates 26 bits.\n                                                                                                                     : ... In instance Top\n  else if (JUMP) PC<=(INST[25:0]<<2);\n                                ^~\n%Error: Exiting due to 7 error(s), 2 warning(s)\n'
module Top(
    input Clk,
    input reset
);
    
    reg [31:0] PC;
    wire [31:0] INST;
    

    wire [25:21] readReg1;
    wire [20:16] readReg2;
    wire [4:0] writeReg;
    wire [31:0] writeData;
    wire [31:0] readData1;
    wire [31:0] readData2;     

    

    wire [15:0] inst;
    wire [31:0] data;
    

    wire [3:0] ALUCtrOut;
    wire [31:0] aluRes;
    wire Zero;
    wire [31:0] input2;
    

    wire REG_DST;
    wire JUMP;
    wire BRANCH;
    wire MEM_READ;
    wire MEM_TO_REG;
    wire MEM_WRITE;
    wire [1:0] ALU_OP;
    wire ALU_SRC;
    wire REG_WRITE;
      

    wire [31:0] readData;
    

    initial begin
    PC=0;
    end    
    

    InstMemory u2(
        .INST(INST),
        .PC(PC),
        .reset(reset)
    );
        

    Ctr mainCtr(
        .OpCode(INST[31:26]),
        .RegDst(REG_DST),
        .Jump(JUMP),
        .Branch(BRANCH),
        .MemRead(MEM_READ),
        .MemToReg(MEM_TO_REG),
        .ALUOp(ALU_OP),
        .MemWrite(MEM_WRITE),
        .ALUSrc(ALU_SRC),
        .RegWrite(REG_WRITE)
    );
    
    assign writeReg = REG_DST ? INST[15:11] : INST[20:16];
                  

    signext u1(
        .inst(INST[15:0]),
        .data(data)
    );    
    

    registers u0(
        .readReg1(INST[25:21]),
        .readReg2(INST[20:16]),
        .writeReg(writeReg),
        .writeData(writeData),
        .regWrite(REG_WRITE),
        .Clk(Clk),
        
        .readData1(readData1),
        .readData2(readData2)
    );
    
    assign input2=ALU_SRC ? data:readData2;        
    

    ALUctr u3(
        .Funct(INST[5:0]),
        .ALUOp(ALU_OP),
        .ALUCtrOut(ALUCtrOut)   
    );
        

    ALU u4(
        .input1(readData1),
        .input2(input2),
        .aluCtr(ALUCtrOut),
        .aluRes(aluRes),
        .zero(Zero)
    );   
        

    dataMemory u5(
        .Clk(Clk),
        .address(aluRes),
        .writeData(readData2),
        .memWrite(MEM_WRITE),
        .memRead(MEM_READ),
        .readData(readData)
    );
    assign writeData= MEM_TO_REG ? readData : aluRes;   
                    

     always @ (posedge Clk)
        begin
		if (reset) PC<=0;
		else if (Zero && BRANCH) PC<=PC+4+(INST[15:0]<<2);
		else if (JUMP) PC<=(INST[25:0]<<2);
		else PC<=PC+4;
        PC=PC%32;
        end


endmodule
module Top(
    input Clk,
    input reset
);

    
    reg [31:0] PC;
    wire [31:0] INST;
    

    wire [25:21] readReg1;
    wire [20:16] readReg2;
    wire [4:0] writeReg;
    wire [31:0] writeData;
    wire [31:0] readData1;
    wire [31:0] readData2;     

    

    wire [15:0] inst;
    wire [31:0] data;
    

    wire [3:0] ALUCtrOut;
    wire [31:0] aluRes;
    wire Zero;
    wire [31:0] input2;
    

    wire REG_DST;
    wire JUMP;
    wire BRANCH;
    wire MEM_READ;
    wire MEM_TO_REG;
    wire MEM_WRITE;
    wire [1:0] ALU_OP;
    wire ALU_SRC;
    wire REG_WRITE;
      

    wire [31:0] readData;
    

    initial begin
    PC=0;
    end    
    

    InstMemory u2(
        .INST(INST),
        .PC(PC),
        .reset(reset)
    );
        

    Ctr mainCtr(
        .OpCode(INST[31:26]),
        .RegDst(REG_DST),
        .Jump(JUMP),
        .Branch(BRANCH),
        .MemRead(MEM_READ),
        .MemToReg(MEM_TO_REG),
        .ALUOp(ALU_OP),
        .MemWrite(MEM_WRITE),
        .ALUSrc(ALU_SRC),
        .RegWrite(REG_WRITE)
    );
    
    assign writeReg = REG_DST ? INST[15:11] : INST[20:16];
                  

    signext u1(
        .inst(INST[15:0]),
        .data(data)
    );    
    

    registers u0(
        .readReg1(INST[25:21]),
        .readReg2(INST[20:16]),
        .writeReg(writeReg),
        .writeData(writeData),
        .regWrite(REG_WRITE),
        .Clk(Clk),
        
        .readData1(readData1),
        .readData2(readData2)
    );
    
    assign input2=ALU_SRC ? data:readData2;        
    

    ALUctr u3(
        .Funct(INST[5:0]),
        .ALUOp(ALU_OP),
        .ALUCtrOut(ALUCtrOut)   
    );
        

    ALU u4(
        .input1(readData1),
        .input2(input2),
        .aluCtr(ALUCtrOut),
        .aluRes(aluRes),
        .zero(Zero)
    );   
        

    dataMemory u5(
        .Clk(Clk),
        .address(aluRes),
        .writeData(readData2),
        .memWrite(MEM_WRITE),
        .memRead(MEM_READ),
        .readData(readData)
    );
    assign writeData= MEM_TO_REG ? readData : aluRes;   
                    

     always @ (posedge Clk)
        begin
		if (reset) PC<=0;
		else if (Zero && BRANCH) PC<=PC+4+(INST[15:0]<<2);
		else if (JUMP) PC<=(INST[25:0]<<2);
		else PC<=PC+4;
        PC=PC%32;
        end


endmodule