data/full_repos/permissive/114553631/test/test_cpu.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/114553631/test/test_cpu.v:6: Cannot find include file: ../src/cpu.v\n`include "../src/cpu.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/cpu.v\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/cpu.v.v\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/cpu.v.sv\n             ../src/cpu.v\n             ../src/cpu.v.v\n             ../src/cpu.v.sv\n             obj_dir/../src/cpu.v\n             obj_dir/../src/cpu.v.v\n             obj_dir/../src/cpu.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_cpu.v:13: Unsupported: Ignoring delay on this delayed statement.\n    initial #stop_time $finish;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_cpu.v:20: Unsupported: Ignoring delay on this delayed statement.\n            #100 clk = ~clk;\n            ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module test_cpu;
    reg clk;
    
    parameter stop_time = 5000;
   
    initial #stop_time $finish;
        
    cpu CPU(clk);
    
    initial begin
        clk = 0;
        repeat(50)
            #100 clk = ~clk;
    end

endmodule
module test_cpu;

    reg clk;
    
    parameter stop_time = 5000;
   
    initial #stop_time $finish;
        
    cpu CPU(clk);
    
    initial begin
        clk = 0;
        repeat(50)
            #100 clk = ~clk;
    end

endmodule