data/full_repos/permissive/174323821/hdl/sdram/jtframe_shadow.v
1: b'%Warning-WIDTH: data/full_repos/permissive/174323821/hdl/sdram/jtframe_shadow.v:39: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s SUB generates 22 bits.\n                                                                                  : ... In instance jtframe_shadow\nwire [LW-1:0] wr_addr   = ba0_addr-START[AW-1:0];\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/174323821/hdl/sdram/jtframe_shadow.v:44: Cannot find file containing module: \'jtframe_dual_ram16\'\njtframe_dual_ram16 #(.aw(LW)) u_ram(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174323821/hdl/sdram,data/full_repos/permissive/174323821/jtframe_dual_ram16\n             data/full_repos/permissive/174323821/hdl/sdram,data/full_repos/permissive/174323821/jtframe_dual_ram16.v\n             data/full_repos/permissive/174323821/hdl/sdram,data/full_repos/permissive/174323821/jtframe_dual_ram16.sv\n             jtframe_dual_ram16\n             jtframe_dual_ram16.v\n             jtframe_dual_ram16.sv\n             obj_dir/jtframe_dual_ram16\n             obj_dir/jtframe_dual_ram16.v\n             obj_dir/jtframe_dual_ram16.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module jtframe_shadow #( parameter
    AW    = 22,
    START = 22'h10_0000,
    LW    = 15
) (
    input   clk_rom,


    input      [AW-1:0] ba0_addr,
    input               wr0,
    input        [15:0] din,
    input        [ 1:0] din_m,


    input      [AW-1:0] ioctl_addr,
    output       [ 7:0] ioctl_din
);

wire [15:0]   dout;
wire [LW-1:0] rd_addr   = ioctl_addr[LW:1];
wire [LW-1:0] wr_addr   = ba0_addr-START[AW-1:0];
wire [1:0]    wr_m      = (ba0_addr >= START && ba0_addr<( START + (1<<LW) )) ? ~din_m : 2'd0;

assign ioctl_din = ioctl_addr[0] ? dout[15:8] : dout[7:0];

jtframe_dual_ram16 #(.aw(LW)) u_ram(
    .clk0       ( clk_rom   ),
    .clk1       ( clk_rom   ),

    .data0      ( din       ),
    .addr0      ( wr_addr   ),
    .we0        ( wr_m      ),
    .q0         (           ),

    .data1      (           ),
    .addr1      ( rd_addr   ),
    .we1        ( 2'b0      ),
    .q1         ( dout      )
);

endmodule
module jtframe_shadow #( parameter
    AW    = 22,
    START = 22'h10_0000,
    LW    = 15
) (
    input   clk_rom,


    input      [AW-1:0] ba0_addr,
    input               wr0,
    input        [15:0] din,
    input        [ 1:0] din_m,


    input      [AW-1:0] ioctl_addr,
    output       [ 7:0] ioctl_din
);


wire [15:0]   dout;
wire [LW-1:0] rd_addr   = ioctl_addr[LW:1];
wire [LW-1:0] wr_addr   = ba0_addr-START[AW-1:0];
wire [1:0]    wr_m      = (ba0_addr >= START && ba0_addr<( START + (1<<LW) )) ? ~din_m : 2'd0;

assign ioctl_din = ioctl_addr[0] ? dout[15:8] : dout[7:0];

jtframe_dual_ram16 #(.aw(LW)) u_ram(
    .clk0       ( clk_rom   ),
    .clk1       ( clk_rom   ),

    .data0      ( din       ),
    .addr0      ( wr_addr   ),
    .we0        ( wr_m      ),
    .q0         (           ),

    .data1      (           ),
    .addr1      ( rd_addr   ),
    .we1        ( 2'b0      ),
    .q1         ( dout      )
);

endmodule