data/full_repos/permissive/127284763/clk_div.v
data/verilator_xmls/cae710e7-53fd-49ac-948d-23c1d5ca89a4.xml
module clk_div( input clk, 
				input rst, 
				output clk_en);

	reg [24:0] clk_count;

	always @ (posedge clk)

		begin
			if (rst)
				clk_count <= 0;
			else
				clk_count <= clk_count + 1;
		end
	assign clk_en = &clk_count;
endmodule
module clk_div( input clk, 
				input rst, 
				output clk_en);


	reg [24:0] clk_count;

	always @ (posedge clk)

		begin
			if (rst)
				clk_count <= 0;
			else
				clk_count <= clk_count + 1;
		end
	assign clk_en = &clk_count;
endmodule