data/full_repos/permissive/173150157/rtl/test/display_clocks_tb.v
 line:108: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/display_clocks_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/display_clocks_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #10000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173150157/rtl/test/display_clocks_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n       #5 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/173150157/rtl/test/display_clocks_tb.v:18: Cannot find file containing module: \'display_clocks\'\n    display_clocks #(\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/173150157/rtl/test,data/full_repos/permissive/173150157/display_clocks\n             data/full_repos/permissive/173150157/rtl/test,data/full_repos/permissive/173150157/display_clocks.v\n             data/full_repos/permissive/173150157/rtl/test,data/full_repos/permissive/173150157/display_clocks.sv\n             display_clocks\n             display_clocks.v\n             display_clocks.sv\n             obj_dir/display_clocks\n             obj_dir/display_clocks.v\n             obj_dir/display_clocks.sv\n%Error: data/full_repos/permissive/173150157/rtl/test/display_clocks_tb.v:40: Cannot find file containing module: \'display_clocks\'\n    display_clocks #(\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173150157/rtl/test/display_clocks_tb.v:62: Cannot find file containing module: \'display_clocks\'\n    display_clocks #(\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173150157/rtl/test/display_clocks_tb.v:84: Cannot find file containing module: \'display_clocks\'\n    display_clocks #(\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module display_clocks_tb();

    reg rst;
    reg clk;


    wire pix_clk_480p;
    wire pix_clk_5x_480p;
    wire clk_lock_480p;

    display_clocks #(
        .MULT_MASTER(31.5),
        .DIV_MASTER(5),
        .DIV_5X(5.0),
        .DIV_1X(25),
        .IN_PERIOD(10.0)
    )
    display_clocks_480p
    (
       .i_clk(clk),
       .i_rst(rst),
       .o_clk_1x(pix_clk_480p),
       .o_clk_5x(pix_clk_5x_480p),
       .o_locked(clk_lock_480p)
    );



    wire pix_clk_600p;
    wire pix_clk_5x_600p;
    wire clk_lock_600p;

    display_clocks #(
        .MULT_MASTER(10.0),
        .DIV_MASTER(1),
        .DIV_5X(5.0),
        .DIV_1X(25),
        .IN_PERIOD(10.0)
    )
    display_clocks_600p
    (
       .i_clk(clk),
       .i_rst(rst),
       .o_clk_1x(pix_clk_600p),
       .o_clk_5x(pix_clk_5x_600p),
       .o_locked(clk_lock_600p)
    );



    wire pix_clk_720p;
    wire pix_clk_5x_720p;
    wire clk_lock_720p;

    display_clocks #(
        .MULT_MASTER(37.125),
        .DIV_MASTER(5),
        .DIV_5X(2.0),
        .DIV_1X(10),
        .IN_PERIOD(10.0)
    )
    display_clocks_720p
    (
       .i_clk(clk),
       .i_rst(rst),
       .o_clk_1x(pix_clk_720p),
       .o_clk_5x(pix_clk_5x_720p),
       .o_locked(clk_lock_720p)
    );



    wire pix_clk_1080p;
    wire pix_clk_5x_1080p;
    wire clk_lock_1080p;

    display_clocks #(
        .MULT_MASTER(37.125),
        .DIV_MASTER(5),
        .DIV_5X(1.0),
        .DIV_1X(5),
        .IN_PERIOD(10.0)
    )
    display_clocks_1080p
    (
       .i_clk(clk),
       .i_rst(rst),
       .o_clk_1x(pix_clk_1080p),
       .o_clk_5x(pix_clk_5x_1080p),
       .o_locked(clk_lock_1080p)
    );


    initial begin
        $display($time, " << Starting Simulation >>");
        clk = 1;
        rst = 1;
        #10
        rst = 0;
        #10000
        $display($time, " << Simulation Complete >>");
    end

    always
       #5 clk = ~clk;

endmodule
module display_clocks_tb();


    reg rst;
    reg clk;


    wire pix_clk_480p;
    wire pix_clk_5x_480p;
    wire clk_lock_480p;

    display_clocks #(
        .MULT_MASTER(31.5),
        .DIV_MASTER(5),
        .DIV_5X(5.0),
        .DIV_1X(25),
        .IN_PERIOD(10.0)
    )
    display_clocks_480p
    (
       .i_clk(clk),
       .i_rst(rst),
       .o_clk_1x(pix_clk_480p),
       .o_clk_5x(pix_clk_5x_480p),
       .o_locked(clk_lock_480p)
    );



    wire pix_clk_600p;
    wire pix_clk_5x_600p;
    wire clk_lock_600p;

    display_clocks #(
        .MULT_MASTER(10.0),
        .DIV_MASTER(1),
        .DIV_5X(5.0),
        .DIV_1X(25),
        .IN_PERIOD(10.0)
    )
    display_clocks_600p
    (
       .i_clk(clk),
       .i_rst(rst),
       .o_clk_1x(pix_clk_600p),
       .o_clk_5x(pix_clk_5x_600p),
       .o_locked(clk_lock_600p)
    );



    wire pix_clk_720p;
    wire pix_clk_5x_720p;
    wire clk_lock_720p;

    display_clocks #(
        .MULT_MASTER(37.125),
        .DIV_MASTER(5),
        .DIV_5X(2.0),
        .DIV_1X(10),
        .IN_PERIOD(10.0)
    )
    display_clocks_720p
    (
       .i_clk(clk),
       .i_rst(rst),
       .o_clk_1x(pix_clk_720p),
       .o_clk_5x(pix_clk_5x_720p),
       .o_locked(clk_lock_720p)
    );



    wire pix_clk_1080p;
    wire pix_clk_5x_1080p;
    wire clk_lock_1080p;

    display_clocks #(
        .MULT_MASTER(37.125),
        .DIV_MASTER(5),
        .DIV_5X(1.0),
        .DIV_1X(5),
        .IN_PERIOD(10.0)
    )
    display_clocks_1080p
    (
       .i_clk(clk),
       .i_rst(rst),
       .o_clk_1x(pix_clk_1080p),
       .o_clk_5x(pix_clk_5x_1080p),
       .o_locked(clk_lock_1080p)
    );


    initial begin
        $display($time, " << Starting Simulation >>");
        clk = 1;
        rst = 1;
        #10
        rst = 0;
        #10000
        $display($time, " << Simulation Complete >>");
    end

    always
       #5 clk = ~clk;

endmodule