data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl/nt_recv_capture_mem_write.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl/nt_recv_capture_mem_write.v:129: Operator SHIFTL expects 33 bits on the LHS, but LHS\'s VARREF \'mem_addr_hi_i\' generates 32 bits.\n                                                                                                                    : ... In instance nt_recv_capture_mem_write\n  assign mem_addr = (mem_addr_hi_i << 32) | mem_addr_lo_i;\n                                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl/nt_recv_capture_mem_write.v:129: Operator OR expects 33 bits on the RHS, but RHS\'s VARREF \'mem_addr_lo_i\' generates 32 bits.\n                                                                                                                    : ... In instance nt_recv_capture_mem_write\n  assign mem_addr = (mem_addr_hi_i << 32) | mem_addr_lo_i;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl/nt_recv_capture_mem_write.v:274: Operator COND expects 32 or 11 bits on the Conditional True, but Conditional True\'s CONST \'8\'hff\' generates 8 bits.\n                                                                                                                    : ... In instance nt_recv_capture_mem_write\n          ~fifo_prog_empty_i ? 8\'hFF : (fifo_rd_data_count_i - 1);\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl/nt_recv_capture_mem_write.v:273: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 11 bits.\n                                                                                                                    : ... In instance nt_recv_capture_mem_write\n        nxt_m_axi_awlen =\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl/nt_recv_capture_mem_write.v:358: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'m_axi_awlen\' generates 8 bits.\n                                                                                                                    : ... In instance nt_recv_capture_mem_write\n            nxt_addr_wr = addr_wr_o + ((m_axi_awlen + 1) << 6);\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/136197078/hardware/ip/nt_recv_capture/hdl/nt_recv_capture_mem_write.v:355: Operator ADD expects 33 bits on the LHS, but LHS\'s VARREF \'m_axi_awlen\' generates 8 bits.\n                                                                                                                    : ... In instance nt_recv_capture_mem_write\n          if ((addr_wr_o + ((m_axi_awlen + 1) << 6)) == mem_size) begin\n                                         ^\n%Error: Exiting due to 6 warning(s)\n'
module nt_recv_capture_mem_write (

  input wire           clk,
  input wire           rstn,
  input wire           rst_sw,


  output reg [32:0]   m_axi_awaddr,
  output reg [7:0]    m_axi_awlen,
  output reg [2:0]    m_axi_awsize,
  output reg [1:0]    m_axi_awburst,
  output reg          m_axi_awlock,
  output reg [3:0]    m_axi_awcache,
  output reg [2:0]    m_axi_awprot,
  output reg [3:0]    m_axi_awqos,
  output reg          m_axi_awvalid,
  input wire          m_axi_awready,
  output reg [511:0]  m_axi_wdata,
  output reg [63:0]   m_axi_wstrb,
  output reg          m_axi_wlast,
  output reg          m_axi_wvalid,
  input wire          m_axi_wready,
  output reg          m_axi_bready,
  input wire [1:0]    m_axi_bresp,
  input wire          m_axi_bvalid,
  output reg [32:0]   m_axi_araddr,
  output reg [7:0]    m_axi_arlen,
  output reg [2:0]    m_axi_arsize,
  output reg [1:0]    m_axi_arburst,
  output reg          m_axi_arlock,
  output reg [3:0]    m_axi_arcache,
  output reg [2:0]    m_axi_arprot,
  output reg [3:0]    m_axi_arqos,
  output reg          m_axi_arvalid,
  input wire          m_axi_arready,
  output reg          m_axi_rready,
  input wire [511:0]  m_axi_rdata,
  input wire [1:0]    m_axi_rresp,
  input wire          m_axi_rlast,
  input wire          m_axi_rvalid,


  input wire [511:0]  fifo_dout_i,
  input wire          fifo_empty_i,
  input wire          fifo_prog_empty_i,
  input wire [10:0]   fifo_rd_data_count_i,
  output reg          fifo_rd_en_o,


  input wire [31:0]   mem_addr_hi_i,
  input wire [31:0]   mem_addr_lo_i,
  input wire [31:0]   mem_range_i,


  output reg [31:0]   addr_wr_o,
  input wire  [31:0]  addr_rd_i,


  input wire          active_i,
  input wire          flush_i,


  output reg          active_o
);


  wire [32:0] mem_addr;
  assign mem_addr = (mem_addr_hi_i << 32) | mem_addr_lo_i;


  wire [32:0] mem_size;
  assign mem_size = mem_range_i + 1'b1;


  parameter   RST             = 3'b000,
              INACTIVE        = 3'b001,
              START           = 3'b010,
              WAIT_RING_BUFF  = 3'b011,
              WAIT_FIFO       = 3'b100,
              WRITE_REQ       = 3'b101,
              WRITE           = 3'b110,
              WAIT_WRITE_RESP = 3'b111;

  reg [2:0]   state, nxt_state;
  reg [32:0]  nxt_m_axi_awaddr;
  reg         nxt_m_axi_awvalid;
  reg [7:0]   nxt_m_axi_awlen;
  reg         nxt_m_axi_wvalid;
  reg [7:0]   beats_cntr, nxt_beats_cntr;
  reg [31:0]  nxt_addr_wr;
  reg         flush, nxt_flush;


  always @(posedge clk) begin
    if (~rstn | rst_sw) begin
      state <= RST;
    end else begin
      state <= nxt_state;
    end

    m_axi_awaddr <= nxt_m_axi_awaddr;
    m_axi_awlen <= nxt_m_axi_awlen;
    m_axi_awvalid <= nxt_m_axi_awvalid;
    m_axi_wvalid <= nxt_m_axi_wvalid;
    m_axi_wstrb <= 64'hFFFFFFFFFFFFFFFF;
    m_axi_awsize <= 3'h6;
    m_axi_awburst <= 2'b01;
    m_axi_bready <= 1'b1;
    m_axi_awlock <= 1'b0;
    m_axi_awcache <= 4'b0011;
    m_axi_awprot <= 3'b0;
    m_axi_awqos <= 4'b0;
    m_axi_araddr <= 33'b0;
    m_axi_arlen <= 8'b0;
    m_axi_arsize <= 3'b0;
    m_axi_arburst <= 2'b0;
    m_axi_arlock <= 1'b0;
    m_axi_arcache <= 4'b0;
    m_axi_arprot <= 3'b0;
    m_axi_arqos <= 4'b0;
    m_axi_arvalid <= 1'b0;
    m_axi_rready <= 1'b0;

    beats_cntr <= nxt_beats_cntr;
    addr_wr_o <= nxt_addr_wr;
    flush <= nxt_flush;
  end


  always @(*) begin
    nxt_state = state;
    nxt_m_axi_awaddr = m_axi_awaddr;
    nxt_m_axi_awlen = m_axi_awlen;
    nxt_m_axi_awvalid = 1'b0;
    nxt_m_axi_wvalid = 1'b0;
    nxt_beats_cntr = beats_cntr;
    nxt_addr_wr = addr_wr_o;
    nxt_flush = 1'b0;

    case (state)

      RST: begin

        nxt_addr_wr = 32'b0;


        nxt_state = INACTIVE;
      end

      INACTIVE: begin
        if (flush_i) begin

          nxt_flush = 1'b1;
          nxt_state = WAIT_RING_BUFF;
        end else if (active_i) begin

          nxt_state = START;
        end
      end

      START: begin

        nxt_m_axi_awaddr = mem_addr;


        nxt_addr_wr = 32'b0;



        nxt_state = WAIT_RING_BUFF;
      end

      WAIT_RING_BUFF: begin



        if (~active_i & ~flush) begin

          nxt_state = INACTIVE;
        end else begin
          if (addr_rd_i == addr_wr_o) begin

            nxt_state = WAIT_FIFO;
          end else if (addr_rd_i < addr_wr_o) begin
            if (addr_rd_i != 0) begin

              nxt_state = WAIT_FIFO;
            end else if ((addr_wr_o + 'h4000) != mem_size) begin

              nxt_state = WAIT_FIFO;
            end
          end else if (addr_rd_i > addr_wr_o) begin
            if ((addr_rd_i - addr_wr_o) > 'h4000) begin

              nxt_state = WAIT_FIFO;
            end
          end
        end


        nxt_flush = flush;
      end

      WAIT_FIFO: begin







        nxt_m_axi_awlen =
          ~fifo_prog_empty_i ? 8'hFF : (fifo_rd_data_count_i - 1);

        if (~active_i & ~flush) begin

          nxt_state = INACTIVE;
        end else if (active_i) begin





          if (~fifo_prog_empty_i) begin

            nxt_state = WRITE_REQ;
          end
        end else if (flush) begin
          if (fifo_prog_empty_i & ~fifo_empty_i) begin


            nxt_state = WRITE_REQ;
          end else begin

            nxt_state = INACTIVE;
          end
        end
      end

      WRITE_REQ: begin



        if (m_axi_awvalid & m_axi_awready) begin

          nxt_state = WRITE;


          nxt_beats_cntr = 8'b0;
        end else begin

          nxt_m_axi_awvalid = 1'b1;
        end
      end

      WRITE: begin



        if (m_axi_wvalid & m_axi_wready) begin



          nxt_beats_cntr = beats_cntr + 1;


          if (m_axi_awaddr == (mem_addr + mem_size - 'h40)) begin

            nxt_m_axi_awaddr = mem_addr;
          end else begin
            nxt_m_axi_awaddr = m_axi_awaddr + 'h40;
          end

          if (beats_cntr == m_axi_awlen) begin

            nxt_state = WAIT_WRITE_RESP;
          end else begin

            nxt_m_axi_wvalid = 1'b1;
          end
        end else begin

          nxt_m_axi_wvalid = 1'b1;
        end
      end

      WAIT_WRITE_RESP: begin


        if (m_axi_bvalid) begin
          nxt_state = WAIT_RING_BUFF;


          if ((addr_wr_o + ((m_axi_awlen + 1) << 6)) == mem_size) begin
            nxt_addr_wr = 0;
          end else begin
            nxt_addr_wr = addr_wr_o + ((m_axi_awlen + 1) << 6);
          end
        end
      end

    endcase
  end


  always @(*) begin
    fifo_rd_en_o = m_axi_wvalid & m_axi_wready;


    m_axi_wdata = { fifo_dout_i[0+:64], fifo_dout_i[64+:64],
                    fifo_dout_i[128+:64], fifo_dout_i[192+:64],
                    fifo_dout_i[256+:64], fifo_dout_i[320+:64],
                    fifo_dout_i[384+:64], fifo_dout_i[448+:64]};


    m_axi_wlast = (beats_cntr == m_axi_awlen);
  end


  always @(posedge clk) begin
    if (~rstn | rst_sw) begin
      active_o <= 1'b0;
    end else begin
      active_o <= (state != RST) & (state != INACTIVE);
    end
  end

endmodule
module nt_recv_capture_mem_write (

  input wire           clk,
  input wire           rstn,
  input wire           rst_sw,


  output reg [32:0]   m_axi_awaddr,
  output reg [7:0]    m_axi_awlen,
  output reg [2:0]    m_axi_awsize,
  output reg [1:0]    m_axi_awburst,
  output reg          m_axi_awlock,
  output reg [3:0]    m_axi_awcache,
  output reg [2:0]    m_axi_awprot,
  output reg [3:0]    m_axi_awqos,
  output reg          m_axi_awvalid,
  input wire          m_axi_awready,
  output reg [511:0]  m_axi_wdata,
  output reg [63:0]   m_axi_wstrb,
  output reg          m_axi_wlast,
  output reg          m_axi_wvalid,
  input wire          m_axi_wready,
  output reg          m_axi_bready,
  input wire [1:0]    m_axi_bresp,
  input wire          m_axi_bvalid,
  output reg [32:0]   m_axi_araddr,
  output reg [7:0]    m_axi_arlen,
  output reg [2:0]    m_axi_arsize,
  output reg [1:0]    m_axi_arburst,
  output reg          m_axi_arlock,
  output reg [3:0]    m_axi_arcache,
  output reg [2:0]    m_axi_arprot,
  output reg [3:0]    m_axi_arqos,
  output reg          m_axi_arvalid,
  input wire          m_axi_arready,
  output reg          m_axi_rready,
  input wire [511:0]  m_axi_rdata,
  input wire [1:0]    m_axi_rresp,
  input wire          m_axi_rlast,
  input wire          m_axi_rvalid,


  input wire [511:0]  fifo_dout_i,
  input wire          fifo_empty_i,
  input wire          fifo_prog_empty_i,
  input wire [10:0]   fifo_rd_data_count_i,
  output reg          fifo_rd_en_o,


  input wire [31:0]   mem_addr_hi_i,
  input wire [31:0]   mem_addr_lo_i,
  input wire [31:0]   mem_range_i,


  output reg [31:0]   addr_wr_o,
  input wire  [31:0]  addr_rd_i,


  input wire          active_i,
  input wire          flush_i,


  output reg          active_o
);



  wire [32:0] mem_addr;
  assign mem_addr = (mem_addr_hi_i << 32) | mem_addr_lo_i;


  wire [32:0] mem_size;
  assign mem_size = mem_range_i + 1'b1;


  parameter   RST             = 3'b000,
              INACTIVE        = 3'b001,
              START           = 3'b010,
              WAIT_RING_BUFF  = 3'b011,
              WAIT_FIFO       = 3'b100,
              WRITE_REQ       = 3'b101,
              WRITE           = 3'b110,
              WAIT_WRITE_RESP = 3'b111;

  reg [2:0]   state, nxt_state;
  reg [32:0]  nxt_m_axi_awaddr;
  reg         nxt_m_axi_awvalid;
  reg [7:0]   nxt_m_axi_awlen;
  reg         nxt_m_axi_wvalid;
  reg [7:0]   beats_cntr, nxt_beats_cntr;
  reg [31:0]  nxt_addr_wr;
  reg         flush, nxt_flush;


  always @(posedge clk) begin
    if (~rstn | rst_sw) begin
      state <= RST;
    end else begin
      state <= nxt_state;
    end

    m_axi_awaddr <= nxt_m_axi_awaddr;
    m_axi_awlen <= nxt_m_axi_awlen;
    m_axi_awvalid <= nxt_m_axi_awvalid;
    m_axi_wvalid <= nxt_m_axi_wvalid;
    m_axi_wstrb <= 64'hFFFFFFFFFFFFFFFF;
    m_axi_awsize <= 3'h6;
    m_axi_awburst <= 2'b01;
    m_axi_bready <= 1'b1;
    m_axi_awlock <= 1'b0;
    m_axi_awcache <= 4'b0011;
    m_axi_awprot <= 3'b0;
    m_axi_awqos <= 4'b0;
    m_axi_araddr <= 33'b0;
    m_axi_arlen <= 8'b0;
    m_axi_arsize <= 3'b0;
    m_axi_arburst <= 2'b0;
    m_axi_arlock <= 1'b0;
    m_axi_arcache <= 4'b0;
    m_axi_arprot <= 3'b0;
    m_axi_arqos <= 4'b0;
    m_axi_arvalid <= 1'b0;
    m_axi_rready <= 1'b0;

    beats_cntr <= nxt_beats_cntr;
    addr_wr_o <= nxt_addr_wr;
    flush <= nxt_flush;
  end


  always @(*) begin
    nxt_state = state;
    nxt_m_axi_awaddr = m_axi_awaddr;
    nxt_m_axi_awlen = m_axi_awlen;
    nxt_m_axi_awvalid = 1'b0;
    nxt_m_axi_wvalid = 1'b0;
    nxt_beats_cntr = beats_cntr;
    nxt_addr_wr = addr_wr_o;
    nxt_flush = 1'b0;

    case (state)

      RST: begin

        nxt_addr_wr = 32'b0;


        nxt_state = INACTIVE;
      end

      INACTIVE: begin
        if (flush_i) begin

          nxt_flush = 1'b1;
          nxt_state = WAIT_RING_BUFF;
        end else if (active_i) begin

          nxt_state = START;
        end
      end

      START: begin

        nxt_m_axi_awaddr = mem_addr;


        nxt_addr_wr = 32'b0;



        nxt_state = WAIT_RING_BUFF;
      end

      WAIT_RING_BUFF: begin



        if (~active_i & ~flush) begin

          nxt_state = INACTIVE;
        end else begin
          if (addr_rd_i == addr_wr_o) begin

            nxt_state = WAIT_FIFO;
          end else if (addr_rd_i < addr_wr_o) begin
            if (addr_rd_i != 0) begin

              nxt_state = WAIT_FIFO;
            end else if ((addr_wr_o + 'h4000) != mem_size) begin

              nxt_state = WAIT_FIFO;
            end
          end else if (addr_rd_i > addr_wr_o) begin
            if ((addr_rd_i - addr_wr_o) > 'h4000) begin

              nxt_state = WAIT_FIFO;
            end
          end
        end


        nxt_flush = flush;
      end

      WAIT_FIFO: begin







        nxt_m_axi_awlen =
          ~fifo_prog_empty_i ? 8'hFF : (fifo_rd_data_count_i - 1);

        if (~active_i & ~flush) begin

          nxt_state = INACTIVE;
        end else if (active_i) begin





          if (~fifo_prog_empty_i) begin

            nxt_state = WRITE_REQ;
          end
        end else if (flush) begin
          if (fifo_prog_empty_i & ~fifo_empty_i) begin


            nxt_state = WRITE_REQ;
          end else begin

            nxt_state = INACTIVE;
          end
        end
      end

      WRITE_REQ: begin



        if (m_axi_awvalid & m_axi_awready) begin

          nxt_state = WRITE;


          nxt_beats_cntr = 8'b0;
        end else begin

          nxt_m_axi_awvalid = 1'b1;
        end
      end

      WRITE: begin



        if (m_axi_wvalid & m_axi_wready) begin



          nxt_beats_cntr = beats_cntr + 1;


          if (m_axi_awaddr == (mem_addr + mem_size - 'h40)) begin

            nxt_m_axi_awaddr = mem_addr;
          end else begin
            nxt_m_axi_awaddr = m_axi_awaddr + 'h40;
          end

          if (beats_cntr == m_axi_awlen) begin

            nxt_state = WAIT_WRITE_RESP;
          end else begin

            nxt_m_axi_wvalid = 1'b1;
          end
        end else begin

          nxt_m_axi_wvalid = 1'b1;
        end
      end

      WAIT_WRITE_RESP: begin


        if (m_axi_bvalid) begin
          nxt_state = WAIT_RING_BUFF;


          if ((addr_wr_o + ((m_axi_awlen + 1) << 6)) == mem_size) begin
            nxt_addr_wr = 0;
          end else begin
            nxt_addr_wr = addr_wr_o + ((m_axi_awlen + 1) << 6);
          end
        end
      end

    endcase
  end


  always @(*) begin
    fifo_rd_en_o = m_axi_wvalid & m_axi_wready;


    m_axi_wdata = { fifo_dout_i[0+:64], fifo_dout_i[64+:64],
                    fifo_dout_i[128+:64], fifo_dout_i[192+:64],
                    fifo_dout_i[256+:64], fifo_dout_i[320+:64],
                    fifo_dout_i[384+:64], fifo_dout_i[448+:64]};


    m_axi_wlast = (beats_cntr == m_axi_awlen);
  end


  always @(posedge clk) begin
    if (~rstn | rst_sw) begin
      active_o <= 1'b0;
    end else begin
      active_o <= (state != RST) & (state != INACTIVE);
    end
  end

endmodule