data/full_repos/permissive/131358616/design/uart/uart_tx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:26: Operator VAR \'IDLE_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h0\' generates 3 bits.\n                                                                             : ... In instance uart_tx\n    IDLE_st          = 3\'d0,\n    ^~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:27: Operator VAR \'INIT_SEND_START_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h1\' generates 3 bits.\n                                                                             : ... In instance uart_tx\n INIT_SEND_START_st  = 3\'d1,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:28: Operator VAR \'WAIT_SEND_START_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h2\' generates 3 bits.\n                                                                             : ... In instance uart_tx\n WAIT_SEND_START_st  = 3\'d2,\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:29: Operator VAR \'INIT_SEND_BIT_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h3\' generates 3 bits.\n                                                                             : ... In instance uart_tx\n INIT_SEND_BIT_st  = 3\'d3,\n ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:30: Operator VAR \'WAIT_SEND_BIT_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h4\' generates 3 bits.\n                                                                             : ... In instance uart_tx\n WAIT_SEND_BIT_st  = 3\'d4,\n ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:31: Operator VAR \'NEXT_BIT_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h5\' generates 3 bits.\n                                                                             : ... In instance uart_tx\n NEXT_BIT_st   = 3\'d5,\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:32: Operator VAR \'INIT_SEND_STOP_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h6\' generates 3 bits.\n                                                                             : ... In instance uart_tx\n INIT_SEND_STOP_st = 3\'d6,\n ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:33: Operator VAR \'WAIT_SEND_STOP_st\' expects 32 bits on the Initial value, but Initial value\'s CONST \'3\'h7\' generates 3 bits.\n                                                                             : ... In instance uart_tx\n WAIT_SEND_STOP_st = 3\'d7;\n ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:50: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE_st\' generates 32 bits.\n                                                                             : ... In instance uart_tx\n        state <= IDLE_st;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:84: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'clock_cycles_per_pulse\' generates 32 or 24 bits.\n                                                                             : ... In instance uart_tx\n        sync_cnt <= clock_cycles_per_pulse;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:97: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'INIT_SEND_START_st\' generates 32 bits.\n                                                                             : ... In instance uart_tx\n    next_state = INIT_SEND_START_st;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:100: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'WAIT_SEND_START_st\' generates 32 bits.\n                                                                              : ... In instance uart_tx\n   next_state = WAIT_SEND_START_st;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:103: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'INIT_SEND_BIT_st\' generates 32 bits.\n                                                                              : ... In instance uart_tx\n    next_state = INIT_SEND_BIT_st;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:106: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'WAIT_SEND_BIT_st\' generates 32 bits.\n                                                                              : ... In instance uart_tx\n   next_state = WAIT_SEND_BIT_st;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:110: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'NEXT_BIT_st\' generates 32 bits.\n                                                                              : ... In instance uart_tx\n     next_state = NEXT_BIT_st;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:112: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'INIT_SEND_STOP_st\' generates 32 bits.\n                                                                              : ... In instance uart_tx\n     next_state = INIT_SEND_STOP_st;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:116: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'INIT_SEND_BIT_st\' generates 32 bits.\n                                                                              : ... In instance uart_tx\n   next_state = INIT_SEND_BIT_st;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:118: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'WAIT_SEND_STOP_st\' generates 32 bits.\n                                                                              : ... In instance uart_tx\n   next_state = WAIT_SEND_STOP_st;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:121: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE_st\' generates 32 bits.\n                                                                              : ... In instance uart_tx\n    next_state = IDLE_st;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:94: Operator CASE expects 32 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 3 bits.\n                                                                             : ... In instance uart_tx\n    case (state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/131358616/design/uart/uart_tx.v:139: Operator CASE expects 32 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 3 bits.\n                                                                              : ... In instance uart_tx\n    case (state)\n    ^~~~\n%Error: Exiting due to 21 warning(s)\n'
module uart_tx (
    input wire rst_n,
    input wire clk,
    input wire start,
    input wire [7:0] data,   
    output reg tx,
    output reg busy
);

parameter  clock_frequency        = 12000000;
parameter  baud_rate              = 9600;

localparam clock_cycles_per_pulse = clock_frequency / baud_rate;

localparam integer 
    IDLE_st         	= 3'd0,
	INIT_SEND_START_st 	= 3'd1,
	WAIT_SEND_START_st 	= 3'd2,
	INIT_SEND_BIT_st 	= 3'd3,
	WAIT_SEND_BIT_st 	= 3'd4,
	NEXT_BIT_st			= 3'd5,
	INIT_SEND_STOP_st	= 3'd6,
	WAIT_SEND_STOP_st	= 3'd7;

reg [2:0] state, next_state;

reg [15:0] sync_cnt;
reg sync_cnt_ld, sync_cnt_en;

reg [2:0] bit_cnt;
reg bit_cnt_ld, bit_cnt_en;

reg [7:0] input_data;
reg input_data_ld;



always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        state <= IDLE_st;
    end else begin
        state <= next_state;
    end
end



always @(posedge clk, negedge rst_n) begin
	if (!rst_n) begin
		input_data <= 0;
	end else if (input_data_ld) begin
		input_data <= data;
	end
end



always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        bit_cnt <= 0;
    end else if (bit_cnt_ld) begin
        bit_cnt <= 0;
    end else if (bit_cnt_en) begin
        bit_cnt <= bit_cnt + 1;
    end
end



always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        sync_cnt <= 0;
    end else if (sync_cnt_ld) begin
        sync_cnt <= clock_cycles_per_pulse;
    end else if (sync_cnt_en) begin
        sync_cnt <= sync_cnt - 1;
    end
end



always @(*) begin
    next_state = state;
    case (state)
	 	IDLE_st:
			if (start) begin
				next_state = INIT_SEND_START_st;
			end
		INIT_SEND_START_st:
			next_state = WAIT_SEND_START_st;
		WAIT_SEND_START_st:
			if (sync_cnt == 0) begin
				next_state = INIT_SEND_BIT_st;
			end
		INIT_SEND_BIT_st:
			next_state = WAIT_SEND_BIT_st;
		WAIT_SEND_BIT_st:
			if (sync_cnt == 0) begin
				if (bit_cnt < 7) begin
					next_state = NEXT_BIT_st;
				end else if (bit_cnt == 7) begin
					next_state = INIT_SEND_STOP_st;
				end
			end
		NEXT_BIT_st:
			next_state = INIT_SEND_BIT_st;
		INIT_SEND_STOP_st:
			next_state = WAIT_SEND_STOP_st;
		WAIT_SEND_STOP_st:
			if (sync_cnt == 0) begin
				next_state = IDLE_st;
			end
    endcase 
end



always @(*) begin
	tx = 1;
	busy = 1;
	sync_cnt_ld = 0;
	sync_cnt_en = 0;

	bit_cnt_ld = 0; 
	bit_cnt_en = 0;

	input_data_ld = 0;

    case (state)
	 	IDLE_st: begin
			busy = 0;
		end
		INIT_SEND_START_st: begin
			tx = 0;
			input_data_ld = 1;
			bit_cnt_ld = 1;
			sync_cnt_ld = 1;
		end
		WAIT_SEND_START_st: begin
			tx = 0;
			sync_cnt_en = 1;
		end
		INIT_SEND_BIT_st: begin
			tx = input_data[bit_cnt];
			sync_cnt_ld = 1;
		end
		WAIT_SEND_BIT_st: begin
			tx = input_data[bit_cnt];
			sync_cnt_en = 1;
		end
		INIT_SEND_STOP_st: begin
			tx = 1;
			sync_cnt_ld = 1;
		end
		WAIT_SEND_STOP_st: begin
			tx = 1;
			sync_cnt_en = 1;
		end
		NEXT_BIT_st: begin
			bit_cnt_en = 1;
		end
    endcase 
end

endmodule
module uart_tx (
    input wire rst_n,
    input wire clk,
    input wire start,
    input wire [7:0] data,   
    output reg tx,
    output reg busy
);


parameter  clock_frequency        = 12000000;
parameter  baud_rate              = 9600;

localparam clock_cycles_per_pulse = clock_frequency / baud_rate;

localparam integer 
    IDLE_st         	= 3'd0,
	INIT_SEND_START_st 	= 3'd1,
	WAIT_SEND_START_st 	= 3'd2,
	INIT_SEND_BIT_st 	= 3'd3,
	WAIT_SEND_BIT_st 	= 3'd4,
	NEXT_BIT_st			= 3'd5,
	INIT_SEND_STOP_st	= 3'd6,
	WAIT_SEND_STOP_st	= 3'd7;

reg [2:0] state, next_state;

reg [15:0] sync_cnt;
reg sync_cnt_ld, sync_cnt_en;

reg [2:0] bit_cnt;
reg bit_cnt_ld, bit_cnt_en;

reg [7:0] input_data;
reg input_data_ld;



always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        state <= IDLE_st;
    end else begin
        state <= next_state;
    end
end



always @(posedge clk, negedge rst_n) begin
	if (!rst_n) begin
		input_data <= 0;
	end else if (input_data_ld) begin
		input_data <= data;
	end
end



always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        bit_cnt <= 0;
    end else if (bit_cnt_ld) begin
        bit_cnt <= 0;
    end else if (bit_cnt_en) begin
        bit_cnt <= bit_cnt + 1;
    end
end



always @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
        sync_cnt <= 0;
    end else if (sync_cnt_ld) begin
        sync_cnt <= clock_cycles_per_pulse;
    end else if (sync_cnt_en) begin
        sync_cnt <= sync_cnt - 1;
    end
end



always @(*) begin
    next_state = state;
    case (state)
	 	IDLE_st:
			if (start) begin
				next_state = INIT_SEND_START_st;
			end
		INIT_SEND_START_st:
			next_state = WAIT_SEND_START_st;
		WAIT_SEND_START_st:
			if (sync_cnt == 0) begin
				next_state = INIT_SEND_BIT_st;
			end
		INIT_SEND_BIT_st:
			next_state = WAIT_SEND_BIT_st;
		WAIT_SEND_BIT_st:
			if (sync_cnt == 0) begin
				if (bit_cnt < 7) begin
					next_state = NEXT_BIT_st;
				end else if (bit_cnt == 7) begin
					next_state = INIT_SEND_STOP_st;
				end
			end
		NEXT_BIT_st:
			next_state = INIT_SEND_BIT_st;
		INIT_SEND_STOP_st:
			next_state = WAIT_SEND_STOP_st;
		WAIT_SEND_STOP_st:
			if (sync_cnt == 0) begin
				next_state = IDLE_st;
			end
    endcase 
end



always @(*) begin
	tx = 1;
	busy = 1;
	sync_cnt_ld = 0;
	sync_cnt_en = 0;

	bit_cnt_ld = 0; 
	bit_cnt_en = 0;

	input_data_ld = 0;

    case (state)
	 	IDLE_st: begin
			busy = 0;
		end
		INIT_SEND_START_st: begin
			tx = 0;
			input_data_ld = 1;
			bit_cnt_ld = 1;
			sync_cnt_ld = 1;
		end
		WAIT_SEND_START_st: begin
			tx = 0;
			sync_cnt_en = 1;
		end
		INIT_SEND_BIT_st: begin
			tx = input_data[bit_cnt];
			sync_cnt_ld = 1;
		end
		WAIT_SEND_BIT_st: begin
			tx = input_data[bit_cnt];
			sync_cnt_en = 1;
		end
		INIT_SEND_STOP_st: begin
			tx = 1;
			sync_cnt_ld = 1;
		end
		WAIT_SEND_STOP_st: begin
			tx = 1;
			sync_cnt_en = 1;
		end
		NEXT_BIT_st: begin
			bit_cnt_en = 1;
		end
    endcase 
end

endmodule