data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/signext_16_32.v
data/verilator_xmls/ad7b7b9e-4ff2-47c2-aff8-0475ccbca824.xml
module signext_16_32(I, O);

    input [15:0] I;
    output reg [31:0] O;
    
    always @(I) 
    begin
        O <={{16{I[15]}}, I[15:0]};
    end
   
endmodule
module signext_16_32(I, O);


    input [15:0] I;
    output reg [31:0] O;
    
    always @(I) 
    begin
        O <={{16{I[15]}}, I[15:0]};
    end
   
endmodule