data/full_repos/permissive/123786074/processor_top/bode_rate_generator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/123786074/processor_top/bode_rate_generator.v:21: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'r_reg\' generates 2 bits.\n                                                                                           : ... In instance bode_rate_generator\n assign r_next = (r_reg==(M-1)) ? 1\'b0 :r_reg +1\'b1; \n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/123786074/processor_top/bode_rate_generator.v:21: Operator COND expects 2 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance bode_rate_generator\n assign r_next = (r_reg==(M-1)) ? 1\'b0 :r_reg +1\'b1; \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/123786074/processor_top/bode_rate_generator.v:23: Operator EQ expects 32 or 3 bits on the LHS, but LHS\'s VARREF \'r_reg\' generates 2 bits.\n                                                                                           : ... In instance bode_rate_generator\n assign max_tick = (r_reg==(M-1)) ? 1\'b1 : 1\'b0; \n                         ^~\n%Error: Exiting due to 3 warning(s)\n'
module bode_rate_generator
 #( parameter  N =2, M =4 ) 
 ( 
  input wire 					clk, reset, 
  output wire 					max_tick, 
  output wire 		[N-1:0] 	q 
  ); 
   
 reg 	[N-1:0] r_reg; 
 wire [N-1:0] r_next; 
  
 always@(posedge clk, posedge reset) 
  if(reset) 
   r_reg<=0; 
  else 
   r_reg<= r_next; 
    
 assign r_next = (r_reg==(M-1)) ? 1'b0 :r_reg +1'b1; 
 assign q = r_reg; 
 assign max_tick = (r_reg==(M-1)) ? 1'b1 : 1'b0; 
  
endmodule
module bode_rate_generator
 #( parameter  N =2, M =4 ) 
 ( 
  input wire 					clk, reset, 
  output wire 					max_tick, 
  output wire 		[N-1:0] 	q 
  );
 
   
 reg 	[N-1:0] r_reg; 
 wire [N-1:0] r_next; 
  
 always@(posedge clk, posedge reset) 
  if(reset) 
   r_reg<=0; 
  else 
   r_reg<= r_next; 
    
 assign r_next = (r_reg==(M-1)) ? 1'b0 :r_reg +1'b1; 
 assign q = r_reg; 
 assign max_tick = (r_reg==(M-1)) ? 1'b1 : 1'b0; 
  
endmodule