data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_ported/ovl_always_on_edge_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_ported/ovl_always_on_edge_tb.v:5: Cannot find include file: ovl_always_on_edge.v\n`include "ovl_always_on_edge.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_ported,data/full_repos/permissive/17099167/ovl_always_on_edge.v\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_ported,data/full_repos/permissive/17099167/ovl_always_on_edge.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric/ovl_ported,data/full_repos/permissive/17099167/ovl_always_on_edge.v.sv\n             ovl_always_on_edge.v\n             ovl_always_on_edge.v.v\n             ovl_always_on_edge.v.sv\n             obj_dir/ovl_always_on_edge.v\n             obj_dir/ovl_always_on_edge.v.v\n             obj_dir/ovl_always_on_edge.v.sv\n%Error: Exiting due to 1 error(s)\n'
module main();


   reg clk;
   reg reset;
   reg enable;
   reg sampling_event;
   reg test_expr;



   wire [2:0] fire;

   ovl_always_on_edge ovl_aoe_t(.clock(clk),
                                .reset(reset),
                                .enable(enable),
                                .sampling_event(sampling_event),
                                .test_expr(test_expr),
                                .fire(fire),
                                .edge_type(1),
                                .property_type(3),
                                .clock_edge(1),
                                .reset_polarity(0),
                                .gating_type(0),
                                .severity_level(3));

   initial begin
      clk = 0;
      reset = 1;
      enable = 0;
      sampling_event = 0;
      test_expr = 0;
      
   end
   always begin
      clk = #5 !clk;
   end
   
endmodule
module main();



   reg clk;
   reg reset;
   reg enable;
   reg sampling_event;
   reg test_expr;



   wire [2:0] fire;

   ovl_always_on_edge ovl_aoe_t(.clock(clk),
                                .reset(reset),
                                .enable(enable),
                                .sampling_event(sampling_event),
                                .test_expr(test_expr),
                                .fire(fire),
                                .edge_type(1),
                                .property_type(3),
                                .clock_edge(1),
                                .reset_polarity(0),
                                .gating_type(0),
                                .severity_level(3));

   initial begin
      clk = 0;
      reset = 1;
      enable = 0;
      sampling_event = 0;
      test_expr = 0;
      
   end
   always begin
      clk = #5 !clk;
   end
   
endmodule