data/full_repos/permissive/136422019/src/computer_tb.v
 line:44: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:181: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:187: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:199: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:202: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:205: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:215: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:218: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:230: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:246: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:249: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:252: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:255: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:261: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:264: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:267: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:273: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:277: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:280: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:283: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:286: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:289: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:292: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:295: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:298: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:304: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:308: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:311: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:314: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:317: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:320: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:323: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:326: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:329: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:335: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:339: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:342: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:345: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:348: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:351: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:354: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:357: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:360: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:366: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:370: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:373: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:376: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:379: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:382: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:385: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:388: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:391: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:397: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:401: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:404: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:407: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:410: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:413: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:416: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:422: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:426: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:429: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:432: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:435: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:438: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/136422019/src/computer_tb.v:441: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/136422019/src/computer_tb.v:27: Cannot find file containing module: \'computer\'\ncomputer cp(clkOut,\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/computer\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/computer.v\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/computer.sv\n             computer\n             computer.v\n             computer.sv\n             obj_dir/computer\n             obj_dir/computer.v\n             obj_dir/computer.sv\n%Error: Exiting due to 1 error(s), 108 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module computer_tb;


reg [31:0] cycle;
reg [31:0] test;

wire clkOut;
wire [31:0] busDataOut;

wire [31:0] r0_test, r1_test, r2_test, r3_test, r4_test, r5_test, r6_test, r7_test, r8_test, r9_test, 
	r10_test, r11_test, r12_test, r13_test, r14_test, r15_test, HI_test, LO_test, PC_test, Zhigh_test, 
	Zlow_test, Y_test, IR_test;

reg clr, PCinc_en, MDRread;

reg r0In, r1In, r2In, r3In, r4In, r5In, r6In, r7In, r8In, r9In, r10In, r11In,
	r12In, r13In, r14In, r15In, HIIn, LOIn, PCIn, IRIn, MARIn, MDRIn, Y_en, Z_en;

reg r0Out, r1Out, r2Out, r3Out, r4Out, r5Out, r6Out, r7Out, r8Out, r9Out, r10Out, r11Out,
	r12Out, r13Out, r14Out, r15Out, HIOut, LOOut, PCOut, IROut, MAROut, MDROut, InPortOut,
	Zlow_en, Zhigh_en;
reg [4:0] opcode;
reg [31:0] busDataIn;


computer cp(clkOut,

	r0_test, r1_test, r2_test, r3_test, r4_test, r5_test, r6_test, r7_test, r8_test, 
		r9_test, r10_test, r11_test, r12_test, r13_test, r14_test, r15_test, HI_test, 
		LO_test, PC_test, Zhigh_test, Zlow_test, Y_test, IR_test, busDataOut, 
	clr, PCinc_en, MDRread, Y_en, Z_en, Zlow_en, Zhigh_en,
	r0In, r1In, r2In, r3In, r4In, r5In, r6In, r7In, r8In, r9In, r10In, r11In,
		r12In, r13In, r14In, r15In, HIIn, LOIn, PCIn, IRIn, MARIn, MDRIn,
	r0Out, r1Out, r2Out, r3Out, r4Out, r5Out, r6Out, r7Out, r8Out, r9Out, r10Out, r11Out,
		r12Out, r13Out, r14Out, r15Out, HIOut, LOOut, PCOut, IROut, MAROut, MDROut, InPortOut,
	opcode,
	busDataIn
);

initial begin
	clr <= 1;
	#100
	setControlLow;
	#100
	adderTest;
	subTest;
	multTest;
	divTest;
	andTest;
	orTest;
	shrTest;
	shlTest;
	rorTest;
	rolTest;
	negTest;
	notTest;
end
	

task setControlLow; begin

	r0In <= 0; r1In <= 0; r2In <= 0; r3In <= 0; r4In <= 0; r5In <= 0; r6In <= 0; 
		r7In <= 0; r8In <= 0; r9In <= 0; r10In <= 0; r11In <= 0; r12In <= 0; r13In <= 0; 
		r14In <= 0; r15In <= 0; HIIn <= 0; LOIn <= 0; PCIn <= 0; IRIn <= 0; MARIn <= 0; 
		MDRIn <= 0; Z_en <= 0; Y_en <= 0;

	r0Out <= 0; r1Out <= 0; r2Out <= 0; r3Out <= 0; r4Out <= 0; r5Out <= 0; r6Out <= 0; 
		r7Out <= 0; r8Out <= 0; r9Out <= 0; r10Out <= 0; r11Out <= 0; r12Out <= 0; 
		r13Out <= 0; r14Out <= 0; r15Out <= 0; HIOut <= 0; LOOut <= 0; PCOut <= 0; 
		IROut <= 0; MAROut <= 0; MDROut <= 0; InPortOut <= 0; Zlow_en <= 0; Zhigh_en <= 0;

	clr <= 0; PCinc_en <= 0; MDRread <= 0;
	opcode <= 5'b00000;
	busDataIn <= 32'bzzzzzzzz_zzzzzzzz_zzzzzzzz_zzzzzzzz;
end
endtask

task adderTest; begin

	#100
	test <= 1;

	cycle <= -2; setControlLow; busDataIn <= 25; InPortOut <= 1; r2In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 10; InPortOut <= 1; r3In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r2Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r3Out <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r1In <= 1;
	#100;
end
endtask

task subTest; begin

	#100
	test <= 2;

	cycle <= -2; setControlLow; busDataIn <= 25; InPortOut <= 1; r4In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 10; InPortOut <= 1; r5In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r4Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r5Out <= 1; opcode <= 5'b00110; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r0In <= 1;
	#100;
end
endtask

task multTest; begin

	#100
	test <= 3;

	cycle <= -2; setControlLow; busDataIn <= 5; InPortOut <= 1; r5In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 10; InPortOut <= 1; r7In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r5Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r7Out <= 1; opcode <= 5'b10001; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; LOIn <= 1;
	#100

	cycle <= 6; setControlLow; Zhigh_en <= 1; HIIn <= 1;
	#100;
end
endtask

task divTest; begin

	#100
	test <= 4;

	cycle <= -2; setControlLow; busDataIn <= 32; InPortOut <= 1; r3In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 5; InPortOut <= 1; r1In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r3Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r1Out <= 1; opcode <= 5'b10010; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; LOIn <= 1;
	#100

	cycle <= 6; setControlLow; Zhigh_en <= 1; HIIn <= 1;
	#100;
end
endtask

task andTest; begin

	#100
	test <= 5;

	cycle <= -2; setControlLow; busDataIn <= 25; InPortOut <= 1; r3In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 10; InPortOut <= 1; r6In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r3Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r6Out <= 1; opcode <= 5'b00111; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r2In <= 1;
	#100;
end
endtask

task orTest; begin

	#100
	test <= 6;

	cycle <= -2; setControlLow; busDataIn <= 25; InPortOut <= 1; r1In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 10; InPortOut <= 1; r7In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r1Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r7Out <= 1; opcode <= 5'b01000; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r0In <= 1;
	#100;
end
endtask

task shrTest; begin

	#100
	test <= 7;

	cycle <= -2; setControlLow; busDataIn <= 32; InPortOut <= 1; r1In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 2; InPortOut <= 1; r3In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r1Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r3Out <= 1; opcode <= 5'b01001; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r2In <= 1;
	#100;
end
endtask

task shlTest; begin

	#100
	test <= 8;

	cycle <= -2; setControlLow; busDataIn <= -32; InPortOut <= 1; r0In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 2; InPortOut <= 1; r5In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r0Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r5Out <= 1; opcode <= 5'b01011; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r3In <= 1;
	#100;
end
endtask

task rorTest; begin

	#100
	test <= 9;

	cycle <= -2; setControlLow; busDataIn <= 'hD; InPortOut <= 1; r1In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 4; InPortOut <= 1; r2In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r1Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r2Out <= 1; opcode <= 5'b01100; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r1In <= 1;
	#100;
end
endtask

task rolTest; begin

	#100
	test <= 10;

	cycle <= -2; setControlLow; busDataIn <= 'hD000_0000; InPortOut <= 1; r0In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 4; InPortOut <= 1; r4In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r0Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r4Out <= 1; opcode <= 5'b01101; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r0In <= 1;
	#100;
end
endtask

task negTest; begin

	#100
	test <= 11;

	cycle <= -1; setControlLow; busDataIn <= 5; InPortOut <= 1; r2In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r2Out <= 1; opcode <= 5'b10011; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r1In <= 1;
	#100;
end
endtask

task notTest; begin

	#100
	test <= 12;

	cycle <= -1; setControlLow; busDataIn <= 5; InPortOut <= 1; r2In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r2Out <= 1; opcode <= 5'b10100; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r1In <= 1;
	#100;
end
endtask

endmodule
module computer_tb;



reg [31:0] cycle;
reg [31:0] test;

wire clkOut;
wire [31:0] busDataOut;

wire [31:0] r0_test, r1_test, r2_test, r3_test, r4_test, r5_test, r6_test, r7_test, r8_test, r9_test, 
	r10_test, r11_test, r12_test, r13_test, r14_test, r15_test, HI_test, LO_test, PC_test, Zhigh_test, 
	Zlow_test, Y_test, IR_test;

reg clr, PCinc_en, MDRread;

reg r0In, r1In, r2In, r3In, r4In, r5In, r6In, r7In, r8In, r9In, r10In, r11In,
	r12In, r13In, r14In, r15In, HIIn, LOIn, PCIn, IRIn, MARIn, MDRIn, Y_en, Z_en;

reg r0Out, r1Out, r2Out, r3Out, r4Out, r5Out, r6Out, r7Out, r8Out, r9Out, r10Out, r11Out,
	r12Out, r13Out, r14Out, r15Out, HIOut, LOOut, PCOut, IROut, MAROut, MDROut, InPortOut,
	Zlow_en, Zhigh_en;
reg [4:0] opcode;
reg [31:0] busDataIn;


computer cp(clkOut,

	r0_test, r1_test, r2_test, r3_test, r4_test, r5_test, r6_test, r7_test, r8_test, 
		r9_test, r10_test, r11_test, r12_test, r13_test, r14_test, r15_test, HI_test, 
		LO_test, PC_test, Zhigh_test, Zlow_test, Y_test, IR_test, busDataOut, 
	clr, PCinc_en, MDRread, Y_en, Z_en, Zlow_en, Zhigh_en,
	r0In, r1In, r2In, r3In, r4In, r5In, r6In, r7In, r8In, r9In, r10In, r11In,
		r12In, r13In, r14In, r15In, HIIn, LOIn, PCIn, IRIn, MARIn, MDRIn,
	r0Out, r1Out, r2Out, r3Out, r4Out, r5Out, r6Out, r7Out, r8Out, r9Out, r10Out, r11Out,
		r12Out, r13Out, r14Out, r15Out, HIOut, LOOut, PCOut, IROut, MAROut, MDROut, InPortOut,
	opcode,
	busDataIn
);

initial begin
	clr <= 1;
	#100
	setControlLow;
	#100
	adderTest;
	subTest;
	multTest;
	divTest;
	andTest;
	orTest;
	shrTest;
	shlTest;
	rorTest;
	rolTest;
	negTest;
	notTest;
end
	

task setControlLow; begin

	r0In <= 0; r1In <= 0; r2In <= 0; r3In <= 0; r4In <= 0; r5In <= 0; r6In <= 0; 
		r7In <= 0; r8In <= 0; r9In <= 0; r10In <= 0; r11In <= 0; r12In <= 0; r13In <= 0; 
		r14In <= 0; r15In <= 0; HIIn <= 0; LOIn <= 0; PCIn <= 0; IRIn <= 0; MARIn <= 0; 
		MDRIn <= 0; Z_en <= 0; Y_en <= 0;

	r0Out <= 0; r1Out <= 0; r2Out <= 0; r3Out <= 0; r4Out <= 0; r5Out <= 0; r6Out <= 0; 
		r7Out <= 0; r8Out <= 0; r9Out <= 0; r10Out <= 0; r11Out <= 0; r12Out <= 0; 
		r13Out <= 0; r14Out <= 0; r15Out <= 0; HIOut <= 0; LOOut <= 0; PCOut <= 0; 
		IROut <= 0; MAROut <= 0; MDROut <= 0; InPortOut <= 0; Zlow_en <= 0; Zhigh_en <= 0;

	clr <= 0; PCinc_en <= 0; MDRread <= 0;
	opcode <= 5'b00000;
	busDataIn <= 32'bzzzzzzzz_zzzzzzzz_zzzzzzzz_zzzzzzzz;
end
endtask

task adderTest; begin

	#100
	test <= 1;

	cycle <= -2; setControlLow; busDataIn <= 25; InPortOut <= 1; r2In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 10; InPortOut <= 1; r3In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r2Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r3Out <= 1; opcode <= 5'b001001; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r1In <= 1;
	#100;
end
endtask

task subTest; begin

	#100
	test <= 2;

	cycle <= -2; setControlLow; busDataIn <= 25; InPortOut <= 1; r4In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 10; InPortOut <= 1; r5In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r4Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r5Out <= 1; opcode <= 5'b00110; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r0In <= 1;
	#100;
end
endtask

task multTest; begin

	#100
	test <= 3;

	cycle <= -2; setControlLow; busDataIn <= 5; InPortOut <= 1; r5In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 10; InPortOut <= 1; r7In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r5Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r7Out <= 1; opcode <= 5'b10001; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; LOIn <= 1;
	#100

	cycle <= 6; setControlLow; Zhigh_en <= 1; HIIn <= 1;
	#100;
end
endtask

task divTest; begin

	#100
	test <= 4;

	cycle <= -2; setControlLow; busDataIn <= 32; InPortOut <= 1; r3In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 5; InPortOut <= 1; r1In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r3Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r1Out <= 1; opcode <= 5'b10010; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; LOIn <= 1;
	#100

	cycle <= 6; setControlLow; Zhigh_en <= 1; HIIn <= 1;
	#100;
end
endtask

task andTest; begin

	#100
	test <= 5;

	cycle <= -2; setControlLow; busDataIn <= 25; InPortOut <= 1; r3In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 10; InPortOut <= 1; r6In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r3Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r6Out <= 1; opcode <= 5'b00111; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r2In <= 1;
	#100;
end
endtask

task orTest; begin

	#100
	test <= 6;

	cycle <= -2; setControlLow; busDataIn <= 25; InPortOut <= 1; r1In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 10; InPortOut <= 1; r7In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r1Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r7Out <= 1; opcode <= 5'b01000; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r0In <= 1;
	#100;
end
endtask

task shrTest; begin

	#100
	test <= 7;

	cycle <= -2; setControlLow; busDataIn <= 32; InPortOut <= 1; r1In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 2; InPortOut <= 1; r3In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r1Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r3Out <= 1; opcode <= 5'b01001; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r2In <= 1;
	#100;
end
endtask

task shlTest; begin

	#100
	test <= 8;

	cycle <= -2; setControlLow; busDataIn <= -32; InPortOut <= 1; r0In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 2; InPortOut <= 1; r5In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r0Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r5Out <= 1; opcode <= 5'b01011; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r3In <= 1;
	#100;
end
endtask

task rorTest; begin

	#100
	test <= 9;

	cycle <= -2; setControlLow; busDataIn <= 'hD; InPortOut <= 1; r1In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 4; InPortOut <= 1; r2In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r1Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r2Out <= 1; opcode <= 5'b01100; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r1In <= 1;
	#100;
end
endtask

task rolTest; begin

	#100
	test <= 10;

	cycle <= -2; setControlLow; busDataIn <= 'hD000_0000; InPortOut <= 1; r0In <= 1;
	#100

	cycle <= -1; setControlLow; busDataIn <= 4; InPortOut <= 1; r4In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r0Out <= 1; Y_en <= 1;
	#100

	cycle <= 4; setControlLow; r4Out <= 1; opcode <= 5'b01101; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r0In <= 1;
	#100;
end
endtask

task negTest; begin

	#100
	test <= 11;

	cycle <= -1; setControlLow; busDataIn <= 5; InPortOut <= 1; r2In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r2Out <= 1; opcode <= 5'b10011; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r1In <= 1;
	#100;
end
endtask

task notTest; begin

	#100
	test <= 12;

	cycle <= -1; setControlLow; busDataIn <= 5; InPortOut <= 1; r2In <= 1;
	#100

	cycle <= 0; setControlLow; PCOut <= 1; MARIn <= 1; PCinc_en <= 1; Z_en <= 1;
	#100

	cycle <= 1; setControlLow; Zlow_en <= 1; PCIn <= 1; MDRread <= 1; MDRIn <= 1;
	#100

	cycle <= 2; setControlLow; MDROut <= 1; IRIn <= 1;
	#100

	cycle <= 3; setControlLow; r2Out <= 1; opcode <= 5'b10100; Z_en <= 1;
	#100

	cycle <= 5; setControlLow; Zlow_en <= 1; r1In <= 1;
	#100;
end
endtask

endmodule