data/full_repos/permissive/210844779/lab2/2.8.2/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.8.2/tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.8.2/tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.8.2/tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/210844779/lab2/2.8.2/tb.v:6: Cannot find file containing module: \'dff\'\n dff u0(.d(d),.clk(clk),.rst(rst),.q(q)); \n ^~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab2/2.8.2,data/full_repos/permissive/210844779/dff\n             data/full_repos/permissive/210844779/lab2/2.8.2,data/full_repos/permissive/210844779/dff.v\n             data/full_repos/permissive/210844779/lab2/2.8.2,data/full_repos/permissive/210844779/dff.sv\n             dff\n             dff.v\n             dff.sv\n             obj_dir/dff\n             obj_dir/dff.v\n             obj_dir/dff.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab2/2.8.2/tb.v:18: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                       : ... In instance tb\n d= $random;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab2/2.8.2/tb.v:19: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                       : ... In instance tb\n rst= $random;\n    ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  
  reg d,clk,rst;
  wire q;
  
 dff u0(.d(d),.clk(clk),.rst(rst),.q(q)); 
 always
begin
  clk=1'b0; 
  #5
  clk=1'b1; 
  #5;
end

always
begin
  
 d= $random;
 rst= $random;
 #10;
 
end

endmodule
module tb();

  
  reg d,clk,rst;
  wire q;
  
 dff u0(.d(d),.clk(clk),.rst(rst),.q(q)); 
 always
begin
  clk=1'b0; 
  #5
  clk=1'b1; 
  #5;
end

always
begin
  
 d= $random;
 rst= $random;
 #10;
 
end

endmodule