data/full_repos/permissive/140493787/src/hdl/vga_counter.v
 line:8: before: "TERMINAL_COUNT"
1: b'%Warning-STMTDLY: data/full_repos/permissive/140493787/src/hdl/vga_counter.v:52: Unsupported: Ignoring delay on this delayed statement.\n      forever #(CLK_PER / 2) clk <= ~clk;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/140493787/src/hdl/vga_counter.v:56: syntax error, unexpected \'@\'\n      reset <= 0; @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/140493787/src/hdl/vga_counter.v:57: syntax error, unexpected \'@\'\n      reset <= 1; @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/140493787/src/hdl/vga_counter.v:58: syntax error, unexpected \'@\'\n      reset <= 0; @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/140493787/src/hdl/vga_counter.v:59: syntax error, unexpected \'@\'\n      repeat (420100) @(posedge clk);\n                      ^\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vga_counter_testbench ();
   wire [9:0] q_h, q_v;
   wire       tc_h, tc_v;
   reg        clk, reset;

   wire reset_h, reset_v;

   assign reset_h = reset | tc_h;
   assign reset_v = reset | (tc_h & tc_v);

   vga_counter #(.TERMINAL_COUNT(799)) count_h (
      .q(q_h), 
      .tc(tc_h),
      .en(clk), 
      .clk(clk),
      .reset(reset_h)
   );
   vga_counter #(.TERMINAL_COUNT(524)) count_v (
      .q(q_v),
      .tc(tc_v),
      .en(tc_h),
      .clk(clk),
      .reset(reset_v)
   );

   parameter CLK_PER = 10;
   initial begin
      clk <= 1;
      forever #(CLK_PER / 2) clk <= ~clk;
   end

   initial begin
      reset <= 0; @(posedge clk);
      reset <= 1; @(posedge clk);
      reset <= 0; @(posedge clk);
      repeat (420100) @(posedge clk);
      $stop;
   end
endmodule
module vga_counter_testbench ();

   wire [9:0] q_h, q_v;
   wire       tc_h, tc_v;
   reg        clk, reset;

   wire reset_h, reset_v;

   assign reset_h = reset | tc_h;
   assign reset_v = reset | (tc_h & tc_v);

   vga_counter #(.TERMINAL_COUNT(799)) count_h (
      .q(q_h), 
      .tc(tc_h),
      .en(clk), 
      .clk(clk),
      .reset(reset_h)
   );
   vga_counter #(.TERMINAL_COUNT(524)) count_v (
      .q(q_v),
      .tc(tc_v),
      .en(tc_h),
      .clk(clk),
      .reset(reset_v)
   );

   parameter CLK_PER = 10;
   initial begin
      clk <= 1;
      forever #(CLK_PER / 2) clk <= ~clk;
   end

   initial begin
      reset <= 0; @(posedge clk);
      reset <= 1; @(posedge clk);
      reset <= 0; @(posedge clk);
      repeat (420100) @(posedge clk);
      $stop;
   end
endmodule