data/full_repos/permissive/174263347/jamma/hdl/interface.v
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-MULTITOP: data/full_repos/permissive/174263347/jamma/hdl/interface.v:19: Multiple top level modules\n                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                : ... Top module \'myLCEL\'\nmodule myLCEL (in, out);\n       ^~~~~~\n                                                                                : ... Top module \'myMUX_16_6\'\nmodule myMUX_16_6 ( select, in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, out );\n       ^~~~~~~~~~\n                                                                                : ... Top module \'myMUX_16_1\'\nmodule myMUX_16_1(select, in, out);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'myREVCOUNTER\'\nmodule myREVCOUNTER( clk, clrn, ena, plus, q );\n       ^~~~~~~~~~~~\n                                                                                : ... Top module \'myFRONTEXTRACTOR\'\nmodule myFRONTEXTRACTOR (clk, clrn, ena, in, out);\n       ^~~~~~~~~~~~~~~~\n                                                                                : ... Top module \'myDFFE2\'\nmodule myDFFE2 (clk, reset, enaA, dataA, enaB, dataB, q);\n       ^~~~~~~\n                                                                                : ... Top module \'myDFFE\'\nmodule myDFFE (clk, reset, enaA, dataA, q);\n       ^~~~~~\n                                                                                : ... Top module \'myDFF\'\nmodule myDFF (clk, reset, dataA, q);\n       ^~~~~\n                                                                                : ... Top module \'my4BREG\'\nmodule my4BREG (clk, reset, enaA, dataA, q);\n       ^~~~~~~\n                                                                                : ... Top module \'myNOISE\'\nmodule myNOISE (clk, reset, enaA, q);\n       ^~~~~~~\n                                                                                : ... Top module \'my4COUNTER\'\nmodule my4COUNTER (clk, reset, ena, set, data, q);\n       ^~~~~~~~~~\n                                                                                : ... Top module \'my16COUNTER\'\nmodule my16COUNTER (clk, reset, ena, set, data, q);\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/174263347/jamma/hdl/interface.v:50: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                             : ... In instance myMUX_16_6\n default:  rout <=  1\'bX;\n                ^~\n%Error: Exiting due to 2 warning(s)\n'
module my4BREG (clk, reset, enaA, dataA, q);

	parameter WIDTH=4;

	input	clk;
	input	reset;
	input	enaA;
	input	[WIDTH-1:0] dataA;
	output	[WIDTH-1:0] q;

	reg		[WIDTH-1:0] mt;

always @ (posedge clk or posedge reset) 
begin
	if (reset)
		mt <= 0;
	else if(enaA)
		mt <= dataA;
end
assign	q = mt;

endmodule
module my4BREG (clk, reset, enaA, dataA, q);


	parameter WIDTH=4;

	input	clk;
	input	reset;
	input	enaA;
	input	[WIDTH-1:0] dataA;
	output	[WIDTH-1:0] q;

	reg		[WIDTH-1:0] mt;

always @ (posedge clk or posedge reset) 
begin
	if (reset)
		mt <= 0;
	else if(enaA)
		mt <= dataA;
end
assign	q = mt;

endmodule