data/full_repos/permissive/178052224/Tarea3y4/modules/demux_tester_1-bit.v
 line:12: before: "("
1: b'%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/demux_tester_1-bit.v:6: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("demux_1bit.vcd");                \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/demux_tester_1-bit.v:7: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;                                 \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/demux_tester_1-bit.v:9: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/demux_tester_1-bit.v:13: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/demux_tester_1-bit.v:18: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/178052224/Tarea3y4/modules/demux_tester_1-bit.v:23: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea3y4/modules/demux_tester_1-bit.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always  #2 clk  <= ~clk;                     \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 6 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador_demux_1_bit( 
    input data_out0, data_out1,
    output reg clk, reset_L,  data_in);
    
    initial begin
    $dumpfile("demux_1bit.vcd");
    $dumpvars;
    reset_L <= 'b0;
    @(posedge clk);
        reset_L <= 1;
        
        repeat(12)begin
            @(posedge clk);
            data_in <= $random % 2;
        end

        repeat(3)begin
            @(posedge clk);
            reset_L <= 0;
            data_in <= $random % 2;
        end
        
    @(posedge clk);
        reset_L <='b0;
        $finish;

    end 
    always  #2 clk  <= ~clk;
    initial clk <= 0;
    initial data_in <= 'b0;

endmodule
module probador_demux_1_bit( 
    input data_out0, data_out1,
    output reg clk, reset_L,  data_in);

    
    initial begin
    $dumpfile("demux_1bit.vcd");
    $dumpvars;
    reset_L <= 'b0;
    @(posedge clk);
        reset_L <= 1;
        
        repeat(12)begin
            @(posedge clk);
            data_in <= $random % 2;
        end

        repeat(3)begin
            @(posedge clk);
            reset_L <= 0;
            data_in <= $random % 2;
        end
        
    @(posedge clk);
        reset_L <='b0;
        $finish;

    end 
    always  #2 clk  <= ~clk;
    initial clk <= 0;
    initial data_in <= 'b0;

endmodule