data/full_repos/permissive/165110048/assets/VGAdemo/Seg7Device.v
1: b"%Error: data/full_repos/permissive/165110048/assets/VGAdemo/Seg7Device.v:29: Cannot find file containing module: 'Seg7Decode'\n Seg7Decode U0(.hex(data), .point(point),\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165110048/assets/VGAdemo,data/full_repos/permissive/165110048/Seg7Decode\n             data/full_repos/permissive/165110048/assets/VGAdemo,data/full_repos/permissive/165110048/Seg7Decode.v\n             data/full_repos/permissive/165110048/assets/VGAdemo,data/full_repos/permissive/165110048/Seg7Decode.sv\n             Seg7Decode\n             Seg7Decode.v\n             Seg7Decode.sv\n             obj_dir/Seg7Decode\n             obj_dir/Seg7Decode.v\n             obj_dir/Seg7Decode.sv\n%Error: data/full_repos/permissive/165110048/assets/VGAdemo/Seg7Device.v:31: Cannot find file containing module: 'Seg7Remap'\n Seg7Remap U1(.I(data), .O(dispPattern));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/165110048/assets/VGAdemo/Seg7Device.v:33: Cannot find file containing module: 'ShiftReg'\n ShiftReg #(.WIDTH(64)) U2(.clk(clkIO), .pdata(dispData), .sout(sout));\n ^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module Seg7Device(
	input clkIO, input [1:0] clkScan, input clkBlink,
	input [31:0] data, input [7:0] point, input [7:0] LES,
	output [3:0] sout, output reg [7:0] segment, output reg [3:0] anode
);
	wire [63:0] dispData;
	wire [31:0] dispPattern;
	
	Seg7Decode U0(.hex(data), .point(point),
		.LE(LES & {8{clkBlink}}), .pattern(dispData));
	Seg7Remap U1(.I(data), .O(dispPattern));

	ShiftReg #(.WIDTH(64)) U2(.clk(clkIO), .pdata(dispData), .sout(sout));

	always @*
		case(clkScan)
		2'b00: begin segment <= ~dispPattern[ 7: 0]; anode <= 4'b1110; end
		2'b01: begin segment <= ~dispPattern[15: 8]; anode <= 4'b1101; end
		2'b10: begin segment <= ~dispPattern[23:16]; anode <= 4'b1011; end
		2'b11: begin segment <= ~dispPattern[31:24]; anode <= 4'b0111; end
		endcase
	
	
endmodule
module Seg7Device(
	input clkIO, input [1:0] clkScan, input clkBlink,
	input [31:0] data, input [7:0] point, input [7:0] LES,
	output [3:0] sout, output reg [7:0] segment, output reg [3:0] anode
);

	wire [63:0] dispData;
	wire [31:0] dispPattern;
	
	Seg7Decode U0(.hex(data), .point(point),
		.LE(LES & {8{clkBlink}}), .pattern(dispData));
	Seg7Remap U1(.I(data), .O(dispPattern));

	ShiftReg #(.WIDTH(64)) U2(.clk(clkIO), .pdata(dispData), .sout(sout));

	always @*
		case(clkScan)
		2'b00: begin segment <= ~dispPattern[ 7: 0]; anode <= 4'b1110; end
		2'b01: begin segment <= ~dispPattern[15: 8]; anode <= 4'b1101; end
		2'b10: begin segment <= ~dispPattern[23:16]; anode <= 4'b1011; end
		2'b11: begin segment <= ~dispPattern[31:24]; anode <= 4'b0111; end
		endcase
	
	
endmodule