data/full_repos/permissive/107007139/Project/pulse_detector.v
data/verilator_xmls/94c249d4-3c7e-4fcc-8901-784daab4a32a.xml
module pulse_detector(
    input  wire clk_4,
    input  wire btn_signal,
    output wire out
    );
    
    reg Q1, Q2;
    
    initial begin
        Q1 = 1'b0;
        Q2 = 1'b0;
    end
    
    always @(posedge clk_4) begin
        Q1 <= btn_signal;
        Q2 <= Q1;
    end
    
    assign out = Q1 & ~Q2;
endmodule
module pulse_detector(
    input  wire clk_4,
    input  wire btn_signal,
    output wire out
    );

    
    reg Q1, Q2;
    
    initial begin
        Q1 = 1'b0;
        Q2 = 1'b0;
    end
    
    always @(posedge clk_4) begin
        Q1 <= btn_signal;
        Q2 <= Q1;
    end
    
    assign out = Q1 & ~Q2;
endmodule