data/full_repos/permissive/216615048/src/ALU.v
 line:128: before: "("
1: b'%Error: data/full_repos/permissive/216615048/src/ALU.v:19: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216615048/src,data/full_repos/permissive/216615048/defines.v\n             data/full_repos/permissive/216615048/src,data/full_repos/permissive/216615048/defines.v.v\n             data/full_repos/permissive/216615048/src,data/full_repos/permissive/216615048/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/216615048/src/ALU.v:50: Define or directive not defined: \'`ALU_ADD\'\n            `ALU_ADD: r = add;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:50: syntax error, unexpected \':\', expecting endcase\n            `ALU_ADD: r = add;\n                    ^\n%Error: data/full_repos/permissive/216615048/src/ALU.v:51: Define or directive not defined: \'`ALU_SUB\'\n            `ALU_SUB : r = add;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:52: Define or directive not defined: \'`ALU_SUB\'\n            `ALU_SUB : r = add;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:53: Define or directive not defined: \'`ALU_PASS\'\n            `ALU_PASS : r = b;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:55: Define or directive not defined: \'`ALU_OR\'\n            `ALU_OR:  r = a | b;\n            ^~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:56: Define or directive not defined: \'`ALU_AND\'\n            `ALU_AND:  r = a & b;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:57: Define or directive not defined: \'`ALU_XOR\'\n            `ALU_XOR:  r = a ^ b;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:59: Define or directive not defined: \'`ALU_SRL\'\n            `ALU_SRL:  r=sh;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:60: Define or directive not defined: \'`ALU_SLL\'\n            `ALU_SLL:  r=sh;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:61: Define or directive not defined: \'`ALU_SRA\'\n            `ALU_SRA:  r=sh;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:63: Define or directive not defined: \'`ALU_SLT\'\n            `ALU_SLT:  r = {31\'b0,(sf != vf)}; \n            ^~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:64: Define or directive not defined: \'`ALU_SLTU\'\n            `ALU_SLTU:  r = {31\'b0,(~cf)};  \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:67: Define or directive not defined: \'`ALU_MUL\'\n            `ALU_MUL :  \n            ^~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:72: Define or directive not defined: \'`ALU_MULHU\'\n            `ALU_MULHU:\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:73: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n             begin\n             ^~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:77: Define or directive not defined: \'`ALU_MULH\'\n            `ALU_MULH:  \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:78: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            begin\n            ^~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:82: Define or directive not defined: \'`ALU_MULHSU\'\n            `ALU_MULHSU: \n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:83: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            begin\n            ^~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:88: Define or directive not defined: \'`ALU_DIV\'\n            `ALU_DIV:\n            ^~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:89: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            begin \n            ^~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:93: Define or directive not defined: \'`ALU_DIVU\'\n            `ALU_DIVU:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:94: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n             begin \n             ^~~~~\n%Error: data/full_repos/permissive/216615048/src/ALU.v:99: Define or directive not defined: \'`ALU_REM\'\n            `ALU_REM: r= $signed(a)%$signed(b); \n            ^~~~~~~~\n%Warning-ENDLABEL: data/full_repos/permissive/216615048/src/ALU.v:99: End label \'r\' does not match begin label \'\'\n            `ALU_REM: r= $signed(a)%$signed(b); \n                      ^\n                   ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/216615048/src/ALU.v:99: syntax error, unexpected \'=\'\n            `ALU_REM: r= $signed(a)%$signed(b); \n                       ^\n%Error: data/full_repos/permissive/216615048/src/ALU.v:100: Define or directive not defined: \'`ALU_REMU\'\n            `ALU_REMU:r= a%b; \n            ^~~~~~~~~\n%Error: Cannot continue\n'
module prv32_ALU(
	input   wire [31:0] a, b,
	input   wire [4:0]  shamt,
	output  reg  [31:0] r,
	output  wire        cf, zf, vf, sf,
	input   wire [4:0]  alufn
);

    wire [31:0] add, sub, op_b;
    wire cfa, cfs;
    
    assign op_b = (~b);
    
    assign {cf, add} = alufn[0] ? (a + op_b + 1'b1) : (a + b);
    
    assign zf = (add == 0);
    assign sf = add[31];
    assign vf = (a[31] ^ (op_b[31]) ^ add[31] ^ cf);
    
    wire[31:0] sh;
    shifter shifter0(a, shamt, alufn[1:0], sh);
    reg[63:0]m,ms,msu;



    always @ * begin
        r = 0;
        (* parallel_case *)
        case (alufn)

            `ALU_ADD: r = add;
            `ALU_SUB : r = add;
            `ALU_SUB : r = add;
            `ALU_PASS : r = b;

            `ALU_OR:  r = a | b;
            `ALU_AND:  r = a & b;
            `ALU_XOR:  r = a ^ b;

            `ALU_SRL:  r=sh;
            `ALU_SLL:  r=sh;
            `ALU_SRA:  r=sh;

            `ALU_SLT:  r = {31'b0,(sf != vf)}; 
            `ALU_SLTU:  r = {31'b0,(~cf)};  
            
            
            `ALU_MUL :  
            begin
                 ms=$signed(a) *$signed(b);
                r=ms[31:0];
             end
            `ALU_MULHU:
             begin
                 m = a*b;
                 r=m[63:32];
              end
            `ALU_MULH:  
            begin
                 ms=$signed(a) *$signed(b);
                r=ms[63:32];
             end
            `ALU_MULHSU: 
            begin
                msu= $signed(a)* b; 
                r=msu[63:32];
            end
            
            `ALU_DIV:
            begin 
            if(b!=0)
            r= $signed(a)/$signed(b);
            end
            `ALU_DIVU:
             begin 
               if(b!=0)
                r= a/b;
               end
           
            `ALU_REM: r= $signed(a)%$signed(b);
            `ALU_REMU:r= a%b;
            default: r = 32'b0;
        endcase
    end
endmodule
module prv32_ALU(
	input   wire [31:0] a, b,
	input   wire [4:0]  shamt,
	output  reg  [31:0] r,
	output  wire        cf, zf, vf, sf,
	input   wire [4:0]  alufn
);


    wire [31:0] add, sub, op_b;
    wire cfa, cfs;
    
    assign op_b = (~b);
    
    assign {cf, add} = alufn[0] ? (a + op_b + 1'b1) : (a + b);
    
    assign zf = (add == 0);
    assign sf = add[31];
    assign vf = (a[31] ^ (op_b[31]) ^ add[31] ^ cf);
    
    wire[31:0] sh;
    shifter shifter0(a, shamt, alufn[1:0], sh);
    reg[63:0]m,ms,msu;



    always @ * begin
        r = 0;
        (* parallel_case *)
        case (alufn)

            `ALU_ADD: r = add;
            `ALU_SUB : r = add;
            `ALU_SUB : r = add;
            `ALU_PASS : r = b;

            `ALU_OR:  r = a | b;
            `ALU_AND:  r = a & b;
            `ALU_XOR:  r = a ^ b;

            `ALU_SRL:  r=sh;
            `ALU_SLL:  r=sh;
            `ALU_SRA:  r=sh;

            `ALU_SLT:  r = {31'b0,(sf != vf)}; 
            `ALU_SLTU:  r = {31'b0,(~cf)};  
            
            
            `ALU_MUL :  
            begin
                 ms=$signed(a) *$signed(b);
                r=ms[31:0];
             end
            `ALU_MULHU:
             begin
                 m = a*b;
                 r=m[63:32];
              end
            `ALU_MULH:  
            begin
                 ms=$signed(a) *$signed(b);
                r=ms[63:32];
             end
            `ALU_MULHSU: 
            begin
                msu= $signed(a)* b; 
                r=msu[63:32];
            end
            
            `ALU_DIV:
            begin 
            if(b!=0)
            r= $signed(a)/$signed(b);
            end
            `ALU_DIVU:
             begin 
               if(b!=0)
                r= a/b;
               end
           
            `ALU_REM: r= $signed(a)%$signed(b);
            `ALU_REMU:r= a%b;
            default: r = 32'b0;
        endcase
    end
endmodule