data/full_repos/permissive/175070965/lib/arith/div.v
None: at end of input
1: b'%Error: data/full_repos/permissive/175070965/lib/arith/div.v:25: Cannot find include file: timescale.inc\n`include "timescale.inc" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175070965/lib/arith,data/full_repos/permissive/175070965/timescale.inc\n             data/full_repos/permissive/175070965/lib/arith,data/full_repos/permissive/175070965/timescale.inc.v\n             data/full_repos/permissive/175070965/lib/arith,data/full_repos/permissive/175070965/timescale.inc.sv\n             timescale.inc\n             timescale.inc.v\n             timescale.inc.sv\n             obj_dir/timescale.inc\n             obj_dir/timescale.inc.v\n             obj_dir/timescale.inc.sv\n%Error: Exiting due to 1 error(s)\n'
module div(clk, rstn, start, dividend, divisor, quotient, remainder, finish, addA, addB, addC, addRes);





parameter [31:0] WIDTH      = 32'd32;
parameter [31:0] RSHARE     = 32'd0;
parameter [31:0] INIT_SHIFT = 32'd0;





input wire                          clk;
input wire                          rstn;
input wire                          start;
input wire      [WIDTH-1:0]         dividend;
input wire      [WIDTH-1:0]         divisor;
output reg      [WIDTH-1:0]         quotient;
output reg      [WIDTH-1:0]         remainder;
output reg                          finish;

output wire     [WIDTH:0]           addA;
output wire     [WIDTH:0]           addB;
output wire                         addC;
input wire      [WIDTH:0]           addRes;





reg     [WIDTH-1:0]      result;
reg     [WIDTH-1:0]      denom;
reg     [6:0]            cycle;
reg                      neg_quotient;
reg                      neg_remainder;
reg                      active;
reg                      divzero;

wire    [WIDTH:0]        sub;

wire    [WIDTH-1:0]      nosign_dividend;
wire    [2*WIDTH-1:0]    remainder_result;





assign    nosign_dividend    = (dividend[WIDTH-1] == 1'b0) ? dividend : $unsigned(-dividend);
assign    remainder_result   = nosign_dividend << INIT_SHIFT;

generate





    if (RSHARE == 0) begin
        assign    sub     = {1'b0,remainder[WIDTH-2:0],result[WIDTH-1]} - {1'b0,denom};
        assign    addA    = {WIDTH+1{1'b0}};
        assign    addB    = {WIDTH+1{1'b0}};
        assign    addC    = 1'b0;
    end





    else begin
        assign    sub     = addRes;
        assign    addA    = {1'b0,remainder[WIDTH-2:0],result[WIDTH-1]};
        assign    addB    = {1'b1,~denom};
        assign    addC    = 1'b1;
    end
endgenerate





always @(posedge clk or negedge rstn) begin
    if (!rstn) begin
        finish <= 1'b1;
        active <= 1'b0;
        divzero <= 1'b0;
        neg_quotient <= 1'b0;
        neg_remainder <= 1'b0;
        cycle <= 7'd0;
        result <= {WIDTH{1'b0}};
        quotient <= {WIDTH{1'b0}};
        denom <= {WIDTH{1'b0}};
        remainder <= {WIDTH{1'b0}};
    end
    else begin
        if (finish == 1'b1) begin
            if (start == 1'b1) begin
                cycle <= WIDTH[6:0];
                {remainder,result} <= remainder_result;
                denom <= (divisor[WIDTH-1] == 1'b0) ? divisor : $unsigned(-divisor);
                neg_quotient <= dividend[WIDTH-1] ^ divisor[WIDTH-1];
                neg_remainder <= dividend[WIDTH-1];
                finish <= 1'b0;
                if (divisor == {WIDTH{1'b0}}) begin
                    divzero <= 1'b1;
                    remainder <= dividend;
                end else begin
                    active <= 1'b1;
                end
            end
        end
        else if (divzero) begin
            divzero <= 1'b0;
            quotient <= {WIDTH{1'b1}};

            finish <= 1'b1;
        end
        else if (active) begin
            if (sub[WIDTH] == 1'b0) begin
                remainder <= sub[WIDTH-1:0];
                result <= {result[WIDTH-2:0],1'b1};
            end
            else begin
                remainder <= {remainder[WIDTH-2:0],result[WIDTH-1]};
                result <= {result[WIDTH-2:0],1'b0};
            end
            if (cycle == 7'd1) begin
                active <= 1'b0;
            end
            cycle <= cycle - 7'd1;
        end
        else if (finish == 1'b0) begin
            finish <= 1'b1;
            quotient <= !neg_quotient ? result : $unsigned(-result);
            remainder <= !neg_remainder ? remainder : $unsigned(-remainder);
        end
    end
end





`ifndef GATE
initial begin
    if (WIDTH > 127) begin
        $display("CONFIG_ERROR: Increase cycle variable width!\n");
        $finish;
    end
end
`endif

endmodule
module div(clk, rstn, start, dividend, divisor, quotient, remainder, finish, addA, addB, addC, addRes);






parameter [31:0] WIDTH      = 32'd32;
parameter [31:0] RSHARE     = 32'd0;
parameter [31:0] INIT_SHIFT = 32'd0;





input wire                          clk;
input wire                          rstn;
input wire                          start;
input wire      [WIDTH-1:0]         dividend;
input wire      [WIDTH-1:0]         divisor;
output reg      [WIDTH-1:0]         quotient;
output reg      [WIDTH-1:0]         remainder;
output reg                          finish;

output wire     [WIDTH:0]           addA;
output wire     [WIDTH:0]           addB;
output wire                         addC;
input wire      [WIDTH:0]           addRes;





reg     [WIDTH-1:0]      result;
reg     [WIDTH-1:0]      denom;
reg     [6:0]            cycle;
reg                      neg_quotient;
reg                      neg_remainder;
reg                      active;
reg                      divzero;

wire    [WIDTH:0]        sub;

wire    [WIDTH-1:0]      nosign_dividend;
wire    [2*WIDTH-1:0]    remainder_result;





assign    nosign_dividend    = (dividend[WIDTH-1] == 1'b0) ? dividend : $unsigned(-dividend);
assign    remainder_result   = nosign_dividend << INIT_SHIFT;

generate





    if (RSHARE == 0) begin
        assign    sub     = {1'b0,remainder[WIDTH-2:0],result[WIDTH-1]} - {1'b0,denom};
        assign    addA    = {WIDTH+1{1'b0}};
        assign    addB    = {WIDTH+1{1'b0}};
        assign    addC    = 1'b0;
    end





    else begin
        assign    sub     = addRes;
        assign    addA    = {1'b0,remainder[WIDTH-2:0],result[WIDTH-1]};
        assign    addB    = {1'b1,~denom};
        assign    addC    = 1'b1;
    end
endgenerate





always @(posedge clk or negedge rstn) begin
    if (!rstn) begin
        finish <= 1'b1;
        active <= 1'b0;
        divzero <= 1'b0;
        neg_quotient <= 1'b0;
        neg_remainder <= 1'b0;
        cycle <= 7'd0;
        result <= {WIDTH{1'b0}};
        quotient <= {WIDTH{1'b0}};
        denom <= {WIDTH{1'b0}};
        remainder <= {WIDTH{1'b0}};
    end
    else begin
        if (finish == 1'b1) begin
            if (start == 1'b1) begin
                cycle <= WIDTH[6:0];
                {remainder,result} <= remainder_result;
                denom <= (divisor[WIDTH-1] == 1'b0) ? divisor : $unsigned(-divisor);
                neg_quotient <= dividend[WIDTH-1] ^ divisor[WIDTH-1];
                neg_remainder <= dividend[WIDTH-1];
                finish <= 1'b0;
                if (divisor == {WIDTH{1'b0}}) begin
                    divzero <= 1'b1;
                    remainder <= dividend;
                end else begin
                    active <= 1'b1;
                end
            end
        end
        else if (divzero) begin
            divzero <= 1'b0;
            quotient <= {WIDTH{1'b1}};

            finish <= 1'b1;
        end
        else if (active) begin
            if (sub[WIDTH] == 1'b0) begin
                remainder <= sub[WIDTH-1:0];
                result <= {result[WIDTH-2:0],1'b1};
            end
            else begin
                remainder <= {remainder[WIDTH-2:0],result[WIDTH-1]};
                result <= {result[WIDTH-2:0],1'b0};
            end
            if (cycle == 7'd1) begin
                active <= 1'b0;
            end
            cycle <= cycle - 7'd1;
        end
        else if (finish == 1'b0) begin
            finish <= 1'b1;
            quotient <= !neg_quotient ? result : $unsigned(-result);
            remainder <= !neg_remainder ? remainder : $unsigned(-remainder);
        end
    end
end





`ifndef GATE
initial begin
    if (WIDTH > 127) begin
        $display("CONFIG_ERROR: Increase cycle variable width!\n");
        $finish;
    end
end
`endif

endmodule