data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/sig_ctl_testbench.v
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1: b'%Error: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/sig_ctl_testbench.v:36: Unsupported or unknown PLI call: $monitor\n    $monitor($time," Main Sig = %b, Country Sig = %b, Car_on_cntry = %b", MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/sig_ctl_testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n    forever #5 CLOCK = ~CLOCK;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/sig_ctl_testbench.v:49: syntax error, unexpected \'@\'\n    repeat(5) @(negedge CLOCK);\n              ^\n%Error: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/sig_ctl_testbench.v:58: syntax error, unexpected \'@\'\n    repeat(20) @(negedge CLOCK);    CAR_ON_CNTRY_RD = 1\'b1;\n               ^\n%Error: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/sig_ctl_testbench.v:59: syntax error, unexpected \'@\'\n    repeat(10) @(negedge CLOCK);    CAR_ON_CNTRY_RD = 1\'b0;\n               ^\n%Error: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/sig_ctl_testbench.v:61: syntax error, unexpected \'@\'\n    repeat(20) @(negedge CLOCK);    CAR_ON_CNTRY_RD = 1\'b1;\n               ^\n%Error: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/sig_ctl_testbench.v:62: syntax error, unexpected \'@\'\n    repeat(10) @(negedge CLOCK);    CAR_ON_CNTRY_RD = 1\'b0;\n               ^\n%Error: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/sig_ctl_testbench.v:64: syntax error, unexpected \'@\'\n    repeat(20) @(negedge CLOCK);    CAR_ON_CNTRY_RD = 1\'b1;\n               ^\n%Error: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/sig_ctl_testbench.v:65: syntax error, unexpected \'@\'\n    repeat(10) @(negedge CLOCK);    CAR_ON_CNTRY_RD = 1\'b0;\n               ^\n%Error: data/full_repos/permissive/169574047/generate/generate.srcs/sim_1/new/sig_ctl_testbench.v:67: syntax error, unexpected \'@\'\n    repeat(10) @(negedge CLOCK);    $stop;\n               ^\n%Error: Exiting due to 9 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sig_ctl_testbench;

wire [1:0] MAIN_SIG,CNTRY_SIG;
reg CAR_ON_CNTRY_RD;
reg CLOCK,CLEAR;


sig_ctl SC(MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD, CLOCK, CLEAR);


initial
    $monitor($time," Main Sig = %b, Country Sig = %b, Car_on_cntry = %b", MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD);


initial
begin
    CLOCK = `FALSE;
    forever #5 CLOCK = ~CLOCK;
end


initial
begin
    CLEAR = `TRUE;
    repeat(5) @(negedge CLOCK);
    CLEAR = `FALSE;
end


initial
begin
    CAR_ON_CNTRY_RD = `FALSE;
    
    repeat(20) @(negedge CLOCK);    CAR_ON_CNTRY_RD = `TRUE;
    repeat(10) @(negedge CLOCK);    CAR_ON_CNTRY_RD = `FALSE;
    
    repeat(20) @(negedge CLOCK);    CAR_ON_CNTRY_RD = `TRUE;
    repeat(10) @(negedge CLOCK);    CAR_ON_CNTRY_RD = `FALSE;
    
    repeat(20) @(negedge CLOCK);    CAR_ON_CNTRY_RD = `TRUE;
    repeat(10) @(negedge CLOCK);    CAR_ON_CNTRY_RD = `FALSE;
    
    repeat(10) @(negedge CLOCK);    $stop;
end

endmodule
module sig_ctl_testbench;


wire [1:0] MAIN_SIG,CNTRY_SIG;
reg CAR_ON_CNTRY_RD;
reg CLOCK,CLEAR;


sig_ctl SC(MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD, CLOCK, CLEAR);


initial
    $monitor($time," Main Sig = %b, Country Sig = %b, Car_on_cntry = %b", MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD);


initial
begin
    CLOCK = `FALSE;
    forever #5 CLOCK = ~CLOCK;
end


initial
begin
    CLEAR = `TRUE;
    repeat(5) @(negedge CLOCK);
    CLEAR = `FALSE;
end


initial
begin
    CAR_ON_CNTRY_RD = `FALSE;
    
    repeat(20) @(negedge CLOCK);    CAR_ON_CNTRY_RD = `TRUE;
    repeat(10) @(negedge CLOCK);    CAR_ON_CNTRY_RD = `FALSE;
    
    repeat(20) @(negedge CLOCK);    CAR_ON_CNTRY_RD = `TRUE;
    repeat(10) @(negedge CLOCK);    CAR_ON_CNTRY_RD = `FALSE;
    
    repeat(20) @(negedge CLOCK);    CAR_ON_CNTRY_RD = `TRUE;
    repeat(10) @(negedge CLOCK);    CAR_ON_CNTRY_RD = `FALSE;
    
    repeat(10) @(negedge CLOCK);    $stop;
end

endmodule