data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_fetch_monociclo.v
 line:47: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_fetch_monociclo.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst= 1\'b1;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_fetch_monociclo.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #500 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_fetch_monociclo.v:51: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_fetch_monociclo.v:55: Cannot find file containing module: \'tl_instruction_fetch\'\ntl_instruction_fetch\n^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_instruction_fetch\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_instruction_fetch.v\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_instruction_fetch.sv\n             tl_instruction_fetch\n             tl_instruction_fetch.v\n             tl_instruction_fetch.sv\n             obj_dir/tl_instruction_fetch\n             obj_dir/tl_instruction_fetch.v\n             obj_dir/tl_instruction_fetch.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_instruction_fetch_monociclo();

localparam len=32;

reg clk;
reg rst;
reg [len-1:0] branch_dir;
reg PCSrc;
wire [len-1:0] instruccion;
wire [len-1:0] adder;


initial
begin
    clk = 1'b0;
    rst = 1'b0;
    branch_dir =0;
    PCSrc =0;
    #10 rst= 1'b1;


        

    
    #500 $finish;
end


always #2.5 clk=~clk;



tl_instruction_fetch
#(
    .len(len),
    .INIT_FILE_IM("/home/anij/facu/Arquitectura_de_Computadoras/agus-arqui/Arqui/MIPS/Source/instruction_memory.txt")


)
    u_tl_instruction_fetch
(
    .i_clk(clk),
    .i_rst(rst),
    .i_branch_dir(branch_dir),
    .i_PCSrc(PCSrc),
    .o_instruccion(instruccion),
    .o_adder(adder)
);

endmodule
module tb_instruction_fetch_monociclo();


localparam len=32;

reg clk;
reg rst;
reg [len-1:0] branch_dir;
reg PCSrc;
wire [len-1:0] instruccion;
wire [len-1:0] adder;


initial
begin
    clk = 1'b0;
    rst = 1'b0;
    branch_dir =0;
    PCSrc =0;
    #10 rst= 1'b1;


        

    
    #500 $finish;
end


always #2.5 clk=~clk;



tl_instruction_fetch
#(
    .len(len),
    .INIT_FILE_IM("/home/anij/facu/Arquitectura_de_Computadoras/agus-arqui/Arqui/MIPS/Source/instruction_memory.txt")


)
    u_tl_instruction_fetch
(
    .i_clk(clk),
    .i_rst(rst),
    .i_branch_dir(branch_dir),
    .i_PCSrc(PCSrc),
    .o_instruccion(instruccion),
    .o_adder(adder)
);

endmodule