data/full_repos/permissive/175808891/verilog/rv32cpu.v
1: b"%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:234: syntax error, unexpected type\n    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));\n                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:285: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\nmodule shifter(input[31:0] a, input [4:0] shamt, input[1:0] type,  output [31:0] r);\n                                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:288: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:343: syntax error, unexpected ',', expecting IDENTIFIER or do or final\n input   wire            int,\n                            ^\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:345: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input   wire            nmi\n ^~~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:369: syntax error, unexpected always\nalways @(posedge clk or posedge rst)\n^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module shifter(input[31:0] a, input [4:0] shamt, input[1:0] type,  output [31:0] r);
    wire [31 : 0] ma, my, y, x, sy;
    
    mirror m1(.in(a), .out(ma));
    mirror m2(.in(y), .out(my));
    
    assign x = type[0] ? ma : a;
    shr sh0(.a(x), .r(y), .shamt(shamt), .ar(type[1]));
    
    assign r = type[0] ? my : y;
    
endmodule
module shifter(input[31:0] a, input [4:0] shamt, input[1:0] type,  output [31:0] r);

    wire [31 : 0] ma, my, y, x, sy;
    
    mirror m1(.in(a), .out(ma));
    mirror m2(.in(y), .out(my));
    
    assign x = type[0] ? ma : a;
    shr sh0(.a(x), .r(y), .shamt(shamt), .ar(type[1]));
    
    assign r = type[0] ? my : y;
    
endmodule