data/full_repos/permissive/13136965/alu.v
1: b"%Error: data/full_repos/permissive/13136965/alu.v:2: Duplicate declaration of signal: 'zero'\n                                                   : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg zero;\n    ^~~~\n        data/full_repos/permissive/13136965/alu.v:1: ... Location of original declaration\nmodule alunit(output [31:0] sum,input [31:0] a,input [31:0] b,input cin,output zero);\n                                                                               ^~~~\n%Error: Exiting due to 1 error(s)\n"
module alunit(output [31:0] sum,input [31:0] a,input [31:0] b,input cin,output zero);
reg zero;
assign sum[31:0] = a + b + cin;
always @ ( sum )
begin
	if(sum[31:0] == 0)
		zero = 1'b1;
	else
		zero = 1'b0;
end
endmodule
module alunit(output [31:0] sum,input [31:0] a,input [31:0] b,input cin,output zero);

reg zero;
assign sum[31:0] = a + b + cin;
always @ ( sum )
begin
	if(sum[31:0] == 0)
		zero = 1'b1;
	else
		zero = 1'b0;
end
endmodule