data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/main_decoder.v
data/verilator_xmls/41a6ea67-9fc2-42d4-a3d4-842d02722909.xml
module main_decoder(
    input [5:0] op,
    output mem2reg, memwrite,
    output branch, 
    output [1:0] alusrca,
    output [1:0] alusrcb,
    output [1:0] regdst, 
    output regwrite,
    output jump,
    output [2:0] aluop,
    output extend,
    input [5:0] funct
    );
    
    reg [14:0] controls;
    
    assign {regwrite, regdst, alusrca,alusrcb, branch, memwrite, mem2reg, jump,aluop,extend}=controls;
    
    always@(*)
    case(op)
    6'b000000:
        case(funct)

        6'b000000:controls<=15'b101100000001111;
        6'b000011:controls<=15'b101100000001111;
        6'b000010:controls<=15'b101100000001111;

        default:controls<=15'b101010000001111;  
        endcase
    6'b100011:controls<=15'b100010100100001;
    6'b101011:controls<=15'b000010101000001;
    6'b001000:controls<=15'b100010100000001;

    

    6'b001100:controls<=15'b100010100000100;

    6'b001101:controls<=15'b100010100000110;

    6'b001110:controls<=15'b100010100001010;

    6'b001010:controls<=15'b100010100001001;

    
    6'b000100:controls<=15'b000010010000011;


    6'b000101:controls<=15'b000010010000011;
    
    6'b000010:controls<=15'b000010000010001;

    6'b000011:controls<=15'b110001100010001;

    
    6'b001111:controls<=15'b100010100001100;
    
    default:controls<=15'bxxxxxxxxxxxxxxx;
    endcase
    
endmodule
module main_decoder(
    input [5:0] op,
    output mem2reg, memwrite,
    output branch, 
    output [1:0] alusrca,
    output [1:0] alusrcb,
    output [1:0] regdst, 
    output regwrite,
    output jump,
    output [2:0] aluop,
    output extend,
    input [5:0] funct
    );

    
    reg [14:0] controls;
    
    assign {regwrite, regdst, alusrca,alusrcb, branch, memwrite, mem2reg, jump,aluop,extend}=controls;
    
    always@(*)
    case(op)
    6'b000000:
        case(funct)

        6'b000000:controls<=15'b101100000001111;
        6'b000011:controls<=15'b101100000001111;
        6'b000010:controls<=15'b101100000001111;

        default:controls<=15'b101010000001111;  
        endcase
    6'b100011:controls<=15'b100010100100001;
    6'b101011:controls<=15'b000010101000001;
    6'b001000:controls<=15'b100010100000001;

    

    6'b001100:controls<=15'b100010100000100;

    6'b001101:controls<=15'b100010100000110;

    6'b001110:controls<=15'b100010100001010;

    6'b001010:controls<=15'b100010100001001;

    
    6'b000100:controls<=15'b000010010000011;


    6'b000101:controls<=15'b000010010000011;
    
    6'b000010:controls<=15'b000010000010001;

    6'b000011:controls<=15'b110001100010001;

    
    6'b001111:controls<=15'b100010100001100;
    
    default:controls<=15'bxxxxxxxxxxxxxxx;
    endcase
    
endmodule