data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv_tb.v
 line:31: before: "+"
1: b'%Error: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv_tb.v:19: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("dotmatrix_wave.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv_tb.v:20: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, testbench);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #500;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #500;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #500;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/179227721/kimchi2018badge/matrixdrv_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
   reg clk;
   reg rst;
   wire [1:0] mat_r;
   wire [1:0] mat_g;
   wire [1:0] mat_b;
   wire [3:0] mat_row;
   wire mat_clk;
   wire mat_lat;
   wire mat_oe;

   integer i;

   matrixdrv drvblk (clk, rst, mat_r, mat_g, mat_b, mat_row, mat_clk, mat_lat, mat_oe);

   initial begin
      $dumpfile("dotmatrix_wave.vcd");
      $dumpvars(0, testbench);


      clk <= 0;
      rst <= 0;
      #500;
      clk <= 1;
      #500;
      clk <= 0;
      rst <= 1;
      #500;
      for (i = 0; i < 3000; i++)
        begin
           clk <= 1;
           #500;
           clk <= 0;
           #500;
        end
   end
endmodule
module testbench;

   reg clk;
   reg rst;
   wire [1:0] mat_r;
   wire [1:0] mat_g;
   wire [1:0] mat_b;
   wire [3:0] mat_row;
   wire mat_clk;
   wire mat_lat;
   wire mat_oe;

   integer i;

   matrixdrv drvblk (clk, rst, mat_r, mat_g, mat_b, mat_row, mat_clk, mat_lat, mat_oe);

   initial begin
      $dumpfile("dotmatrix_wave.vcd");
      $dumpvars(0, testbench);


      clk <= 0;
      rst <= 0;
      #500;
      clk <= 1;
      #500;
      clk <= 0;
      rst <= 1;
      #500;
      for (i = 0; i < 3000; i++)
        begin
           clk <= 1;
           #500;
           clk <= 0;
           #500;
        end
   end
endmodule