data/full_repos/permissive/170402453/RISC/TinyCPU_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/TinyCPU_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/TinyCPU_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/TinyCPU_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #20;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/TinyCPU_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/TinyCPU_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/TinyCPU_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #20;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/TinyCPU_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/TinyCPU_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC/TinyCPU_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk=~clk;\n        ^\n%Error: data/full_repos/permissive/170402453/RISC/TinyCPU_tb.v:49: Cannot find file containing module: \'TinyCPU\'\n TinyCPU uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170402453/RISC,data/full_repos/permissive/170402453/TinyCPU\n             data/full_repos/permissive/170402453/RISC,data/full_repos/permissive/170402453/TinyCPU.v\n             data/full_repos/permissive/170402453/RISC,data/full_repos/permissive/170402453/TinyCPU.sv\n             TinyCPU\n             TinyCPU.v\n             TinyCPU.sv\n             obj_dir/TinyCPU\n             obj_dir/TinyCPU.v\n             obj_dir/TinyCPU.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TinyCPU_tb;


	reg clk;
	reg LoadEnable;
	reg [1:0] ASelect;
	reg [1:0] BSelect;
	reg [1:0] DestinationSelect;
	reg [15:0] ConstantIn;
	reg MBSelect;
	reg MDSelect;
	reg [3:0] GSelect;
	reg [1:0] HSelect;
	reg MFSelect;
	reg [15:0] DataIn;


	wire [15:0] DataOut, AddressOut;
	wire statC;
	wire statV;
	wire statN;
	wire statZ;


	TinyCPU uut (
		.clk(clk), 
		.LoadEnable(LoadEnable), 
		.ASelect(ASelect), 
		.BSelect(BSelect), 
		.DestinationSelect(DestinationSelect), 
		.ConstantIn(ConstantIn), 
		.MBSelect(MBSelect), 
		.MDSelect(MDSelect), 
		.GSelect(GSelect), 
		.HSelect(HSelect), 
		.MFSelect(MFSelect), 
		.AddressOut(AddressOut), 
		.DataOut(DataOut), 
		.DataIn(DataIn), 
		.statC(statC), 
		.statV(statV), 
		.statN(statN), 
		.statZ(statZ)
	);

	initial begin

		clk = 0;
		LoadEnable = 0;
		ASelect = 0;
		BSelect = 0;
		DestinationSelect = 0;
		ConstantIn = 0;
		MBSelect = 0;
		MDSelect = 0;
		GSelect = 0;
		HSelect = 0;
		MFSelect = 0;

		DataIn = 0;


		#100;
        

		LoadEnable=1;
		DestinationSelect=0;
		DataIn=12345;
		MDSelect=1;
		#20;
		DestinationSelect=1;
		#20;
		DataIn=22222;
		#20;
		LoadEnable=0;
		

		ASelect = 0;
		BSelect = 1;
		
		GSelect = 4'b0010;
		#20;
		

		DestinationSelect=3;
		#20;
		
		MDSelect=0;
		LoadEnable=1;
		#40;
		LoadEnable=0;
		
		#20;
		

		BSelect = 3;
	end
	
	always #10 clk=~clk;
      
endmodule
module TinyCPU_tb;



	reg clk;
	reg LoadEnable;
	reg [1:0] ASelect;
	reg [1:0] BSelect;
	reg [1:0] DestinationSelect;
	reg [15:0] ConstantIn;
	reg MBSelect;
	reg MDSelect;
	reg [3:0] GSelect;
	reg [1:0] HSelect;
	reg MFSelect;
	reg [15:0] DataIn;


	wire [15:0] DataOut, AddressOut;
	wire statC;
	wire statV;
	wire statN;
	wire statZ;


	TinyCPU uut (
		.clk(clk), 
		.LoadEnable(LoadEnable), 
		.ASelect(ASelect), 
		.BSelect(BSelect), 
		.DestinationSelect(DestinationSelect), 
		.ConstantIn(ConstantIn), 
		.MBSelect(MBSelect), 
		.MDSelect(MDSelect), 
		.GSelect(GSelect), 
		.HSelect(HSelect), 
		.MFSelect(MFSelect), 
		.AddressOut(AddressOut), 
		.DataOut(DataOut), 
		.DataIn(DataIn), 
		.statC(statC), 
		.statV(statV), 
		.statN(statN), 
		.statZ(statZ)
	);

	initial begin

		clk = 0;
		LoadEnable = 0;
		ASelect = 0;
		BSelect = 0;
		DestinationSelect = 0;
		ConstantIn = 0;
		MBSelect = 0;
		MDSelect = 0;
		GSelect = 0;
		HSelect = 0;
		MFSelect = 0;

		DataIn = 0;


		#100;
        

		LoadEnable=1;
		DestinationSelect=0;
		DataIn=12345;
		MDSelect=1;
		#20;
		DestinationSelect=1;
		#20;
		DataIn=22222;
		#20;
		LoadEnable=0;
		

		ASelect = 0;
		BSelect = 1;
		
		GSelect = 4'b0010;
		#20;
		

		DestinationSelect=3;
		#20;
		
		MDSelect=0;
		LoadEnable=1;
		#40;
		LoadEnable=0;
		
		#20;
		

		BSelect = 3;
	end
	
	always #10 clk=~clk;
      
endmodule