data/full_repos/permissive/161526648/MEM_WB.v
data/verilator_xmls/37f84275-322a-4c44-b121-3555d7679a8e.xml
module MEM_WB (clock,reset,MemtoReg_mem,RegWrite_mem,ALUresult_mem,ReadData,WriteReg_mem,MemtoReg_wb,RegWrite_wb,ALUresult_wb,WriteReg_wb,ReadData_wb);
	input clock,reset,MemtoReg_mem,RegWrite_mem;
	input[31:0] ALUresult_mem,ReadData;
	input[4:0] WriteReg_mem;
	output reg MemtoReg_wb,RegWrite_wb;
	output reg[31:0] ALUresult_wb;
	output reg[4:0] WriteReg_wb;
	output reg[31:0] ReadData_wb;
	
	always @(posedge clock or posedge reset) begin
		if (reset)
			begin
				MemtoReg_wb = 0;
				RegWrite_wb = 0;
				ALUresult_wb = 32'b0;
				WriteReg_wb = 5'b0;
				ReadData_wb = 32'b0;
			end
		else
			begin
				MemtoReg_wb = MemtoReg_mem;
				RegWrite_wb = RegWrite_mem;
				ALUresult_wb = ALUresult_mem;
				WriteReg_wb = WriteReg_mem;
				ReadData_wb = ReadData;
			end
	end
endmodule
module MEM_WB (clock,reset,MemtoReg_mem,RegWrite_mem,ALUresult_mem,ReadData,WriteReg_mem,MemtoReg_wb,RegWrite_wb,ALUresult_wb,WriteReg_wb,ReadData_wb);

	input clock,reset,MemtoReg_mem,RegWrite_mem;
	input[31:0] ALUresult_mem,ReadData;
	input[4:0] WriteReg_mem;
	output reg MemtoReg_wb,RegWrite_wb;
	output reg[31:0] ALUresult_wb;
	output reg[4:0] WriteReg_wb;
	output reg[31:0] ReadData_wb;
	
	always @(posedge clock or posedge reset) begin
		if (reset)
			begin
				MemtoReg_wb = 0;
				RegWrite_wb = 0;
				ALUresult_wb = 32'b0;
				WriteReg_wb = 5'b0;
				ReadData_wb = 32'b0;
			end
		else
			begin
				MemtoReg_wb = MemtoReg_mem;
				RegWrite_wb = RegWrite_mem;
				ALUresult_wb = ALUresult_mem;
				WriteReg_wb = WriteReg_mem;
				ReadData_wb = ReadData;
			end
	end
endmodule