data/full_repos/permissive/125531440/core/src/main/verilog/loopback/ff.v
data/verilator_xmls/b70c2b97-9ac5-485e-a66d-3f2777a57c1b.xml
module ff
    (
     input      CLK,
     input      D,
     output reg Q
     );
    always @ (posedge CLK) begin 
	    Q <= #1 D; 
    end
endmodule
module ff
    (
     input      CLK,
     input      D,
     output reg Q
     );

    always @ (posedge CLK) begin 
	    Q <= #1 D; 
    end
endmodule