data/full_repos/permissive/200478172/source/L_Trans.v
data/verilator_xmls/3f009e24-5878-4418-9a2e-32592af0c9dd.xml
module L_Trans(
    input [31:0] a,
    input [2:0]ctr,
    
    output [31:0] z
    );
    reg [31:0] temp;
    always@(*)begin
        case(ctr)

            3'b001:temp<={{24{a[7]}},a[7:0]};

            3'b010:temp<={{24{1'b0}},a[7:0]};

            3'b011:temp<={{16{a[15]}},a[15:0]};

            3'b100:temp<={{16{1'b0}},a[15:0]};
            default:temp<=a;
        endcase
    end
    assign z=temp;
endmodule
module L_Trans(
    input [31:0] a,
    input [2:0]ctr,
    
    output [31:0] z
    );

    reg [31:0] temp;
    always@(*)begin
        case(ctr)

            3'b001:temp<={{24{a[7]}},a[7:0]};

            3'b010:temp<={{24{1'b0}},a[7:0]};

            3'b011:temp<={{16{a[15]}},a[15:0]};

            3'b100:temp<={{16{1'b0}},a[15:0]};
            default:temp<=a;
        endcase
    end
    assign z=temp;
endmodule