data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/clock_div.v
data/verilator_xmls/d5407bf6-6554-4da4-b24d-6a387efe1d12.xml
module clock_div #(
    parameter N = 2,
    parameter WIDTH = 8
)(  
    input clk,
    input rst_n,
    output reg clk_out
    );

    reg [WIDTH-1 : 0] cnt;
    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
            cnt <= 0;
        else
        begin
            if (cnt == N - 1)
            begin
                cnt <= 0;
            end
            else
            begin
                cnt <= cnt + 1;
            end
        end
    end
    
    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
            clk_out <= 0;
        else
            if (cnt == N - 1) begin
                clk_out <= !clk_out;
            end
    end
  
endmodule
module clock_div #(
    parameter N = 2,
    parameter WIDTH = 8
)(  
    input clk,
    input rst_n,
    output reg clk_out
    );


    reg [WIDTH-1 : 0] cnt;
    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
            cnt <= 0;
        else
        begin
            if (cnt == N - 1)
            begin
                cnt <= 0;
            end
            else
            begin
                cnt <= cnt + 1;
            end
        end
    end
    
    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
            clk_out <= 0;
        else
            if (cnt == N - 1) begin
                clk_out <= !clk_out;
            end
    end
  
endmodule