data/full_repos/permissive/110151336/lab_08/src/lab8.v
1: b'%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:231: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                          : ... In instance lab8\n    assign hex0 = moore_fsm_out ? 8\'b10100011 : 8\'b11111111;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_08/src/lab8.v:232: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                          : ... In instance lab8\n    assign hex1 = mealy_fsm_out ? 8\'b10011100 : 8\'b11111111;\n                ^\n%Error: Exiting due to 2 warning(s)\n'
module shift
# ( parameter width = 10 )
(
    input                     clock,
    input                     reset_n,
    input                     shift_enable,
    input                     button,
    output reg [width - 1:0]  shift_reg,
    output                    out
);

    always @ (posedge clock or negedge reset_n)
    begin
        if (! reset_n)
            shift_reg <= { width { 1'b0 } };
        else if (shift_enable)
            shift_reg <= { button, shift_reg [width - 1:1] };
    end

    assign out = shift_reg [0];

endmodule
module shift
# ( parameter width = 10 )
(
    input                     clock,
    input                     reset_n,
    input                     shift_enable,
    input                     button,
    output reg [width - 1:0]  shift_reg,
    output                    out
);


    always @ (posedge clock or negedge reset_n)
    begin
        if (! reset_n)
            shift_reg <= { width { 1'b0 } };
        else if (shift_enable)
            shift_reg <= { button, shift_reg [width - 1:1] };
    end

    assign out = shift_reg [0];

endmodule