data/full_repos/permissive/106492436/test_1.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/106492436/test_1.sv:31: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106492436/test_1.sv:34: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106492436/test_1.sv:36: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106492436/test_1.sv:43: Unsupported: Ignoring delay on this delayed statement.\n initial forever #10 clk = ~clk;\n                 ^\n%Error: data/full_repos/permissive/106492436/test_1.sv:15: Cannot find file containing module: \'MIPS\'\n MIPS uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/106492436,data/full_repos/permissive/106492436/MIPS\n             data/full_repos/permissive/106492436,data/full_repos/permissive/106492436/MIPS.v\n             data/full_repos/permissive/106492436,data/full_repos/permissive/106492436/MIPS.sv\n             MIPS\n             MIPS.v\n             MIPS.sv\n             obj_dir/MIPS\n             obj_dir/MIPS.v\n             obj_dir/MIPS.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_1;


	logic clk;
	logic rst;


	 logic [7:0] DATA;
	 logic RW;
	 logic EN;
	 logic RS;
	 logic ON;


	MIPS uut (
		.clk(clk),
		.rst(rst),
		.DATA(DATA),
		.RW(RW),
		.EN(EN),
		.RS(RS),
		.ON(ON)
	);

	initial begin

		clk = 0;
		rst = 1;


		#100;
		
		rst= 1;
		#200;
		rst= 0;
		#200;
		rst = 1;
        


	end
	
	initial forever #10 clk = ~clk;
      
endmodule
module test_1;



	logic clk;
	logic rst;


	 logic [7:0] DATA;
	 logic RW;
	 logic EN;
	 logic RS;
	 logic ON;


	MIPS uut (
		.clk(clk),
		.rst(rst),
		.DATA(DATA),
		.RW(RW),
		.EN(EN),
		.RS(RS),
		.ON(ON)
	);

	initial begin

		clk = 0;
		rst = 1;


		#100;
		
		rst= 1;
		#200;
		rst= 0;
		#200;
		rst = 1;
        


	end
	
	initial forever #10 clk = ~clk;
      
endmodule