data/full_repos/permissive/105152503/core/uart.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/393817ef-996b-4d80-bbeb-9620fec192de.xml
module uart(
	input  wire        clk            ,
	input  wire        rst            ,
	input  wire [ 7:0] tx_data        ,
	input  wire        tx_en          ,
	output reg         tx_ready       ,
	output reg         tx             ,
	output reg  [ 4:0] stage          ,
	output reg  [10:0] ctr             
	);

	parameter          BAUD_THRESHOLD= 10;
	reg         [ 7:0] tx_buffer         ;


	task reset; 
		begin
			tx       <= 1;
			tx_ready <= 1;
			ctr      <= 0;
			stage    <= 0;
			tx_buffer<= 0;
		end
	endtask


	always @ (posedge tx_en) begin
		tx_ready<= 0;
		tx_buffer<= tx_data;
	end


	always @ (posedge clk) begin

		if(rst) begin
			reset;
		end else if(~tx_ready) begin

			ctr<= ctr+ 1'b1;


			case(stage)
				5'h0     : tx<= 0;
				5'h1     : tx<= tx_buffer[0];
				5'h2     : tx<= tx_buffer[1];
				5'h3     : tx<= tx_buffer[2];
				5'h4     : tx<= tx_buffer[3];
				5'h5     : tx<= tx_buffer[4];
				5'h6     : tx<= tx_buffer[5];
				5'h7     : tx<= tx_buffer[6];
				5'h8     : tx<= tx_buffer[7];
				5'h9     : tx<= 0;
				5'ha     : tx<= 0;
				5'hb     : reset;
				default  : tx<= 1;
			endcase
		end else begin
			tx<= 1;
		end


		if(ctr== BAUD_THRESHOLD) begin
			stage<= stage+1'b1;
			ctr<= 0;
		end
	end

endmodule
module uart(
	input  wire        clk            ,
	input  wire        rst            ,
	input  wire [ 7:0] tx_data        ,
	input  wire        tx_en          ,
	output reg         tx_ready       ,
	output reg         tx             ,
	output reg  [ 4:0] stage          ,
	output reg  [10:0] ctr             
	);


	parameter          BAUD_THRESHOLD= 10;
	reg         [ 7:0] tx_buffer         ;


	task reset; 
		begin
			tx       <= 1;
			tx_ready <= 1;
			ctr      <= 0;
			stage    <= 0;
			tx_buffer<= 0;
		end
	endtask


	always @ (posedge tx_en) begin
		tx_ready<= 0;
		tx_buffer<= tx_data;
	end


	always @ (posedge clk) begin

		if(rst) begin
			reset;
		end else if(~tx_ready) begin

			ctr<= ctr+ 1'b1;


			case(stage)
				5'h0     : tx<= 0;
				5'h1     : tx<= tx_buffer[0];
				5'h2     : tx<= tx_buffer[1];
				5'h3     : tx<= tx_buffer[2];
				5'h4     : tx<= tx_buffer[3];
				5'h5     : tx<= tx_buffer[4];
				5'h6     : tx<= tx_buffer[5];
				5'h7     : tx<= tx_buffer[6];
				5'h8     : tx<= tx_buffer[7];
				5'h9     : tx<= 0;
				5'ha     : tx<= 0;
				5'hb     : reset;
				default  : tx<= 1;
			endcase
		end else begin
			tx<= 1;
		end


		if(ctr== BAUD_THRESHOLD) begin
			stage<= stage+1'b1;
			ctr<= 0;
		end
	end

endmodule