data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/clock.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/clock.v:8: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/clock.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock(output reg clk);


    always begin
        clk=0;
        #10;
        clk=1;
        #10;
    end

endmodule
module clock(output reg clk);



    always begin
        clk=0;
        #10;
        clk=1;
        #10;
    end

endmodule