data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v
 line:122: before: "$"
1: b'%Error: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:2: Cannot find include file: 32mpy.v\n`include "32mpy.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/198139336/2019_DD_LAB10/example,data/full_repos/permissive/198139336/32mpy.v\n             data/full_repos/permissive/198139336/2019_DD_LAB10/example,data/full_repos/permissive/198139336/32mpy.v.v\n             data/full_repos/permissive/198139336/2019_DD_LAB10/example,data/full_repos/permissive/198139336/32mpy.v.sv\n             32mpy.v\n             32mpy.v.v\n             32mpy.v.sv\n             obj_dir/32mpy.v\n             obj_dir/32mpy.v.v\n             obj_dir/32mpy.v.sv\n%Error: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:21: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("lab10.vcd");   \n ^~~~~~~~~\n%Error: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:22: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 1; \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:28: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:30: Unsupported: Ignoring delay on this delayed statement.\n #680 reset = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:33: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:35: Unsupported: Ignoring delay on this delayed statement.\n #680 reset = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:38: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:40: Unsupported: Ignoring delay on this delayed statement.\n #680 reset = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:43: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:45: Unsupported: Ignoring delay on this delayed statement.\n #680 reset = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:48: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:50: Unsupported: Ignoring delay on this delayed statement.\n #680 reset = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:53: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:55: Unsupported: Ignoring delay on this delayed statement.\n #680 reset = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:58: Unsupported: Ignoring delay on this delayed statement.\n #20 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:60: Unsupported: Ignoring delay on this delayed statement.\n #680 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/2019_DD_LAB10/example/tb32mpy.v:63: Unsupported: Ignoring delay on this delayed statement.\nalways #10 CLK = ~CLK;\n       ^\n%Error: Exiting due to 3 error(s), 16 warning(s)\n'
module tb_lab();
reg [31:0] in_a;
reg [31:0] in_b;
reg CLK;
reg reset;
wire [63:0] out;
wire out_valid;

reg [5:0]	count;
reg signed [64:0]	correct_ans;
reg error;
reg signed [63:0]	 temp_a;
reg signed [63:0]	temp_b;

lab m1(CLK, reset, in_a, in_b, out, out_valid);

initial begin
	$dumpfile("lab10.vcd");
	$dumpvars;
	CLK = 1'b0;
	
	#10 reset = 1;
	temp_a = 32'd30;
	temp_b = 32'd90;
	#20 reset = 0;
	
	#680 reset = 1;
	temp_a = 32'd30;
	temp_b = -32'd90;
	#20 reset = 0;
	
	#680 reset = 1;
	temp_a = -32'd30;
	temp_b = 32'd90;
	#20 reset = 0;
	
	#680 reset = 1;
	temp_a = -32'd30;
	temp_b = -32'd90;
	#20 reset = 0;

	#680 reset = 1;
	temp_a = 64'd4294967295;
	temp_b = 64'd4294967295;
	#20 reset = 0;
	
	#680 reset = 1;
	temp_a = 64'd4294967296;
	temp_b = 64'd1;
	#20 reset = 0;
	
	#680 reset = 1;
	temp_a = 64'd4294967297;
	temp_b = 64'd1;
	#20 reset = 0;

	#680 $finish;
end

always #10 CLK = ~CLK;

always @(posedge CLK or posedge reset)
begin
	if(reset)
	begin
		count <= 0;
		in_a <= temp_a;
		in_b <= temp_b;
		correct_ans <= 0;
		error <= 0;
	end

	else
	begin
		correct_ans <= temp_a *temp_b;
		count <= count +1;

		if(out_valid==1)
			if(out != correct_ans)
			begin
				error <=1;
				$display ();
				$display ("// Fail //");
				$display ("//%d * %d = ?",temp_a, temp_b);
				$display ("//your answer is %d, but correct answer is %d\n",
				out, correct_ans);
			end
			
			else
			begin
				error <= 0;
				$display ();
				$display ("// Successful //");
				$display ("//%d * %d = ?",temp_a, temp_b);
				$display ("//your answer is %d,  correct answer is %d\n",
				out, correct_ans);
			end
	end
end

endmodule
module tb_lab();

reg [31:0] in_a;
reg [31:0] in_b;
reg CLK;
reg reset;
wire [63:0] out;
wire out_valid;

reg [5:0]	count;
reg signed [64:0]	correct_ans;
reg error;
reg signed [63:0]	 temp_a;
reg signed [63:0]	temp_b;

lab m1(CLK, reset, in_a, in_b, out, out_valid);

initial begin
	$dumpfile("lab10.vcd");
	$dumpvars;
	CLK = 1'b0;
	
	#10 reset = 1;
	temp_a = 32'd30;
	temp_b = 32'd90;
	#20 reset = 0;
	
	#680 reset = 1;
	temp_a = 32'd30;
	temp_b = -32'd90;
	#20 reset = 0;
	
	#680 reset = 1;
	temp_a = -32'd30;
	temp_b = 32'd90;
	#20 reset = 0;
	
	#680 reset = 1;
	temp_a = -32'd30;
	temp_b = -32'd90;
	#20 reset = 0;

	#680 reset = 1;
	temp_a = 64'd4294967295;
	temp_b = 64'd4294967295;
	#20 reset = 0;
	
	#680 reset = 1;
	temp_a = 64'd4294967296;
	temp_b = 64'd1;
	#20 reset = 0;
	
	#680 reset = 1;
	temp_a = 64'd4294967297;
	temp_b = 64'd1;
	#20 reset = 0;

	#680 $finish;
end

always #10 CLK = ~CLK;

always @(posedge CLK or posedge reset)
begin
	if(reset)
	begin
		count <= 0;
		in_a <= temp_a;
		in_b <= temp_b;
		correct_ans <= 0;
		error <= 0;
	end

	else
	begin
		correct_ans <= temp_a *temp_b;
		count <= count +1;

		if(out_valid==1)
			if(out != correct_ans)
			begin
				error <=1;
				$display ();
				$display ("// Fail //");
				$display ("//%d * %d = ?",temp_a, temp_b);
				$display ("//your answer is %d, but correct answer is %d\n",
				out, correct_ans);
			end
			
			else
			begin
				error <= 0;
				$display ();
				$display ("// Successful //");
				$display ("//%d * %d = ?",temp_a, temp_b);
				$display ("//your answer is %d,  correct answer is %d\n",
				out, correct_ans);
			end
	end
end

endmodule