data/full_repos/permissive/143278/ivltests/lh_varindx.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/lh_varindx.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #1 ;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/lh_varindx.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #1 ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/lh_varindx.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #1 ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/lh_varindx.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #1 ;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/lh_varindx.v:28: Bit extraction of var[3:0] requires 2 bit index, not 4 bits.\n                                                                          : ... In instance main\n   a[b] = c;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/lh_varindx.v:35: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                          : ... In instance main\n    b = 1\'b0;\n      ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ;

reg [3:0] a,b;
reg c;
reg error;

always @(c or b)
   a[b] = c;

initial
  begin
    #1 ;
    a = 4'b1111;
    error = 0;
    b = 1'b0;
    c = 1'b0;
    #1 ;
    if(a != 4'b1110)
      begin
        $display("FAILED - var index -  a = %b, [b] = %d, c=%b",a,b,c);
        error = 1;
      end
    #1 ;
    b = 1;
    #1 ;
    if(a != 4'b1100)
      begin
        $display("FAILED - var index -  a = %b, [b] = %d, c=%b",a,b,c);
        error = 1;
      end

    if(error == 0)
       $display("PASSED");
  end

endmodule
module main ;


reg [3:0] a,b;
reg c;
reg error;

always @(c or b)
   a[b] = c;

initial
  begin
    #1 ;
    a = 4'b1111;
    error = 0;
    b = 1'b0;
    c = 1'b0;
    #1 ;
    if(a != 4'b1110)
      begin
        $display("FAILED - var index -  a = %b, [b] = %d, c=%b",a,b,c);
        error = 1;
      end
    #1 ;
    b = 1;
    #1 ;
    if(a != 4'b1100)
      begin
        $display("FAILED - var index -  a = %b, [b] = %d, c=%b",a,b,c);
        error = 1;
      end

    if(error == 0)
       $display("PASSED");
  end

endmodule