data/full_repos/permissive/166661632/p7/p7/Dmcut.v
1: b'%Error: data/full_repos/permissive/166661632/p7/p7/Dmcut.v:2: Cannot find include file: head.v\n`include"head.v" \n        ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166661632/p7/p7,data/full_repos/permissive/166661632/head.v\n             data/full_repos/permissive/166661632/p7/p7,data/full_repos/permissive/166661632/head.v.v\n             data/full_repos/permissive/166661632/p7/p7,data/full_repos/permissive/166661632/head.v.sv\n             head.v\n             head.v.v\n             head.v.sv\n             obj_dir/head.v\n             obj_dir/head.v.v\n             obj_dir/head.v.sv\n%Error: data/full_repos/permissive/166661632/p7/p7/Dmcut.v:20: Define or directive not defined: \'`wm_wd\'\n  if(wordmode==`wm_wd)\n               ^~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Dmcut.v:20: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if(wordmode==`wm_wd)\n                     ^\n%Error: data/full_repos/permissive/166661632/p7/p7/Dmcut.v:22: Define or directive not defined: \'`wm_hs\'\n  else if(wordmode==`wm_hs)\n                    ^~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Dmcut.v:24: Define or directive not defined: \'`wm_hu\'\n  else if(wordmode==`wm_hu)\n                    ^~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Dmcut.v:26: Define or directive not defined: \'`wm_bs\'\n  else if(wordmode==`wm_bs)\n                    ^~~~~~\n%Error: data/full_repos/permissive/166661632/p7/p7/Dmcut.v:28: Define or directive not defined: \'`wm_bu\'\n  else if(wordmode==`wm_bu)\n                    ^~~~~~\n%Error: Exiting due to 7 error(s)\n'
module Dmcut(dmout,ao_w,dr_w,wordmode);
input [31:0] dmout,ao_w;
input [2:0] wordmode;
output reg [31:0] dr_w;

initial begin
	dr_w=0;
end
wire [31:0] word[1:0];
assign word[0]=(ao_w[1]==1)?{16'b0,dmout[31:16]}:{16'b0,dmout[15:0]};
assign word[1]=(ao_w[1:0]==0)?{24'b0,dmout[7:0]}:
               (ao_w[1:0]==1)?{24'b0,dmout[15:8]}:
					(ao_w[1:0]==2)?{24'b0,dmout[23:16]}:
					{24'b0,dmout[31:24]};

always@(*)
	begin
		if(wordmode==`wm_wd)
			dr_w<=dmout;
		else if(wordmode==`wm_hs)
			dr_w<={{16{word[0][15]}},word[0][15:0]};
		else if(wordmode==`wm_hu)
			dr_w<={16'b0,word[0][15:0]};
		else if(wordmode==`wm_bs)
			dr_w<={{24{word[1][7]}},word[1][7:0]};
		else if(wordmode==`wm_bu)
			dr_w<={24'b0,word[1][7:0]};
		else dr_w<=32'h17231181;
	end


endmodule
module Dmcut(dmout,ao_w,dr_w,wordmode);

input [31:0] dmout,ao_w;
input [2:0] wordmode;
output reg [31:0] dr_w;

initial begin
	dr_w=0;
end
wire [31:0] word[1:0];
assign word[0]=(ao_w[1]==1)?{16'b0,dmout[31:16]}:{16'b0,dmout[15:0]};
assign word[1]=(ao_w[1:0]==0)?{24'b0,dmout[7:0]}:
               (ao_w[1:0]==1)?{24'b0,dmout[15:8]}:
					(ao_w[1:0]==2)?{24'b0,dmout[23:16]}:
					{24'b0,dmout[31:24]};

always@(*)
	begin
		if(wordmode==`wm_wd)
			dr_w<=dmout;
		else if(wordmode==`wm_hs)
			dr_w<={{16{word[0][15]}},word[0][15:0]};
		else if(wordmode==`wm_hu)
			dr_w<={16'b0,word[0][15:0]};
		else if(wordmode==`wm_bs)
			dr_w<={{24{word[1][7]}},word[1][7:0]};
		else if(wordmode==`wm_bu)
			dr_w<={24'b0,word[1][7:0]};
		else dr_w<=32'h17231181;
	end


endmodule