data/full_repos/permissive/123796236/add32.v
data/verilator_xmls/9a36744a-3f1a-4dab-a364-c948ae53de84.xml
module add32(result, a, b);
input [31:0] a, b;
output [31:0] result;
assign result = a + b;
endmodule
module add32(result, a, b);

input [31:0] a, b;
output [31:0] result;
assign result = a + b;
endmodule