data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:10: Cannot find include file: sim_exec_report.vh\n`include "sim_exec_report.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo,data/full_repos/permissive/214858095/sim_exec_report.vh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo,data/full_repos/permissive/214858095/sim_exec_report.vh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo,data/full_repos/permissive/214858095/sim_exec_report.vh.sv\n             sim_exec_report.vh\n             sim_exec_report.vh.v\n             sim_exec_report.vh.sv\n             obj_dir/sim_exec_report.vh\n             obj_dir/sim_exec_report.vh.v\n             obj_dir/sim_exec_report.vh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:11: Cannot find include file: sim_clks_rsts.vh\n`include "sim_clks_rsts.vh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:12: Cannot find include file: sim_cvita_lib.svh\n`include "sim_cvita_lib.svh" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:13: Cannot find include file: sim_axis_lib.svh\n`include "sim_axis_lib.svh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:14: Cannot find include file: sim_set_rb_lib.svh\n`include "sim_set_rb_lib.svh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:20: Define or directive not defined: \'`TEST_BENCH_INIT\'\n  `TEST_BENCH_INIT("axi_fifo_tb",4,1);\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:20: syntax error, unexpected \'(\'\n  `TEST_BENCH_INIT("axi_fifo_tb",4,1);\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:22: Define or directive not defined: \'`DEFINE_CLK\'\n  `DEFINE_CLK(clk, CLK_PERIOD, 50);\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:22: syntax error, unexpected \'(\'\n  `DEFINE_CLK(clk, CLK_PERIOD, 50);\n              ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:23: Define or directive not defined: \'`DEFINE_RESET\'\n  `DEFINE_RESET(reset, 0, 100);\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:66: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                   : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Wait for Reset");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:66: syntax error, unexpected \';\'\n    `TEST_CASE_START("Wait for Reset");\n                                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:69: syntax error, unexpected \'@\'\n    while (reset) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:70: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(~reset);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:70: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(~reset);\n                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:75: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                   : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Check filling FIFOs");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:75: syntax error, unexpected \';\'\n    `TEST_CASE_START("Check filling FIFOs");\n                                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:80: Define or directive not defined: \'`ASSERT_FATAL\'\n        `ASSERT_FATAL(m_axis.axis.tready[i],s);\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:80: syntax error, unexpected \',\'\n        `ASSERT_FATAL(m_axis.axis.tready[i],s);\n                                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:84: Define or directive not defined: \'`ASSERT_WARN\'\n      `ASSERT_WARN(~m_axis.axis.tready[i],s);\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:84: syntax error, unexpected \',\'\n      `ASSERT_WARN(~m_axis.axis.tready[i],s);\n                                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:86: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:86: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:91: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                   : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Check emptying FIFOs");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:91: syntax error, unexpected \';\'\n    `TEST_CASE_START("Check emptying FIFOs");\n                                            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:96: Define or directive not defined: \'`ASSERT_FATAL\'\n        `ASSERT_FATAL(s_axis.axis.tvalid[i],s);\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:96: syntax error, unexpected \',\'\n        `ASSERT_FATAL(s_axis.axis.tvalid[i],s);\n                                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:99: Define or directive not defined: \'`ASSERT_FATAL\'\n        `ASSERT_FATAL(read_word == k,s);\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:99: syntax error, unexpected \',\'\n        `ASSERT_FATAL(read_word == k,s);\n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:101: Define or directive not defined: \'`ASSERT_FATAL\'\n      `ASSERT_FATAL(~s_axis.axis.tvalid[i],"FIFO not empty after reading all entries!");\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:101: syntax error, unexpected \',\'\n      `ASSERT_FATAL(~s_axis.axis.tvalid[i],"FIFO not empty after reading all entries!");\n                                          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:103: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:103: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:108: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                                    : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Randomized Write / Read");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:108: syntax error, unexpected \';\'\n    `TEST_CASE_START("Randomized Write / Read");\n                                               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:111: Unsupported: fork statements\n      fork\n      ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:115: syntax error, unexpected \'@\'\n          while ($signed($random()) > 0) @(posedge clk);\n                                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:122: syntax error, unexpected \'@\'\n          while ($signed($random()) > 0) @(posedge clk);\n                                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:125: Define or directive not defined: \'`ASSERT_FATAL\'\n          `ASSERT_FATAL(read_word == k,s);\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:125: syntax error, unexpected \',\'\n          `ASSERT_FATAL(read_word == k,s);\n                                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:130: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:130: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/sim/fifo/axi_fifo/axi_fifo_tb.sv:131: Define or directive not defined: \'`TEST_BENCH_DONE\'\n    `TEST_BENCH_DONE;\n    ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 43 error(s)\n'
module axi_fifo_tb();

  `TEST_BENCH_INIT("axi_fifo_tb",`NUM_TEST_CASES,`NS_PER_TICK);
  localparam CLK_PERIOD = $ceil(1e9/166.67e6);
  `DEFINE_CLK(clk, CLK_PERIOD, 50);
  `DEFINE_RESET(reset, 0, 100);


  localparam NUM_FIFOS = 4;
  localparam integer FIFO_SIZES[NUM_FIFOS-1:0] = '{0,1,5,8};
  localparam NUM_ITERATIONS = 10000;


  reg  [NUM_FIFOS-1:0] clear;
  axis_master #(.DWIDTH(32), .NUM_STREAMS(NUM_FIFOS)) m_axis(.clk(clk));
  axis_slave #(.DWIDTH(32), .NUM_STREAMS(NUM_FIFOS)) s_axis(.clk(clk));

  genvar n;
  generate
    for (n = 0; n < NUM_FIFOS; n = n + 1) begin
      axi_fifo #(
        .SIZE(FIFO_SIZES[n]),
        .WIDTH(32))
      axi_fifo (
        .clk(clk), .reset(reset), .clear(clear[n]),
        .i_tdata(m_axis.axis.tdata[32*n +: 32]), .i_tvalid(m_axis.axis.tvalid[n]), .i_tready(m_axis.axis.tready[n]),
        .o_tdata(s_axis.axis.tdata[32*n +: 32]), .o_tvalid(s_axis.axis.tvalid[n]), .o_tready(s_axis.axis.tready[n]),
        .space(), .occupied());
    end
  endgenerate


  int write_word = 0;
  int read_word = 0;
  logic last;
  string s;

  initial begin
    clear = 'd0;


    `TEST_CASE_START("Wait for Reset");
    m_axis.reset();
    s_axis.reset();
    while (reset) @(posedge clk);
    `TEST_CASE_DONE(~reset);


    `TEST_CASE_START("Check filling FIFOs");
    for (int i = 0; i < NUM_FIFOS; i++) begin
      $display("Testing FIFO %0d, SIZE %0d",i,2**FIFO_SIZES[i]);
      for (int k = 0; k < 2**FIFO_SIZES[i]; k++) begin
        $sformat(s,"FIFO size should be %0d entries, but detected %0d!",2**FIFO_SIZES[i],k);
        `ASSERT_FATAL(m_axis.axis.tready[i],s);
        m_axis.push_word(k,0,i);
      end
      $sformat(s,"FIFO depth appears to be greater than %0d entries! Might be due to output registering.",2**FIFO_SIZES[i]);
      `ASSERT_WARN(~m_axis.axis.tready[i],s);
    end
    `TEST_CASE_DONE(1);


    `TEST_CASE_START("Check emptying FIFOs");
    for (int i = 0; i < NUM_FIFOS; i++) begin
      $display("Testing FIFO %0d, SIZE %0d",i,2**FIFO_SIZES[i]);
      for (int k = 0; k < 2**FIFO_SIZES[i]; k = k + 1) begin
        $sformat(s,"FIFO prematurely empty! Occured after %0d reads!",k);
        `ASSERT_FATAL(s_axis.axis.tvalid[i],s);
        s_axis.pull_word(read_word,last,i);
        $sformat(s,"Read invalid FIFO word! Expected: %0d, Actual: %0d",k,read_word);
        `ASSERT_FATAL(read_word == k,s);
      end
      `ASSERT_FATAL(~s_axis.axis.tvalid[i],"FIFO not empty after reading all entries!");
    end
    `TEST_CASE_DONE(1);


    `TEST_CASE_START("Randomized Write / Read");
    for (int i = 0; i < NUM_FIFOS; i++) begin
      $display("Testing FIFO %0d, SIZE %0d",i,2**FIFO_SIZES[i]);
      fork
      begin
        write_word = 0;
        for (int k = 0; k < NUM_ITERATIONS; k++) begin
          while ($signed($random()) > 0) @(posedge clk);
          m_axis.push_word(write_word,0,i);
          write_word++;
        end
      end
      begin
        for (int k = 0; k < NUM_ITERATIONS; k++) begin
          while ($signed($random()) > 0) @(posedge clk);
          s_axis.pull_word(read_word,last,i);
          $sformat(s,"Read invalid FIFO word! Expected: %0d, Actual: %0d",read_word,k);
          `ASSERT_FATAL(read_word == k,s);
        end
      end
      join
    end
    `TEST_CASE_DONE(1);
    `TEST_BENCH_DONE;
  end

endmodule
module axi_fifo_tb();


  `TEST_BENCH_INIT("axi_fifo_tb",`NUM_TEST_CASES,`NS_PER_TICK);
  localparam CLK_PERIOD = $ceil(1e9/166.67e6);
  `DEFINE_CLK(clk, CLK_PERIOD, 50);
  `DEFINE_RESET(reset, 0, 100);


  localparam NUM_FIFOS = 4;
  localparam integer FIFO_SIZES[NUM_FIFOS-1:0] = '{0,1,5,8};
  localparam NUM_ITERATIONS = 10000;


  reg  [NUM_FIFOS-1:0] clear;
  axis_master #(.DWIDTH(32), .NUM_STREAMS(NUM_FIFOS)) m_axis(.clk(clk));
  axis_slave #(.DWIDTH(32), .NUM_STREAMS(NUM_FIFOS)) s_axis(.clk(clk));

  genvar n;
  generate
    for (n = 0; n < NUM_FIFOS; n = n + 1) begin
      axi_fifo #(
        .SIZE(FIFO_SIZES[n]),
        .WIDTH(32))
      axi_fifo (
        .clk(clk), .reset(reset), .clear(clear[n]),
        .i_tdata(m_axis.axis.tdata[32*n +: 32]), .i_tvalid(m_axis.axis.tvalid[n]), .i_tready(m_axis.axis.tready[n]),
        .o_tdata(s_axis.axis.tdata[32*n +: 32]), .o_tvalid(s_axis.axis.tvalid[n]), .o_tready(s_axis.axis.tready[n]),
        .space(), .occupied());
    end
  endgenerate


  int write_word = 0;
  int read_word = 0;
  logic last;
  string s;

  initial begin
    clear = 'd0;


    `TEST_CASE_START("Wait for Reset");
    m_axis.reset();
    s_axis.reset();
    while (reset) @(posedge clk);
    `TEST_CASE_DONE(~reset);


    `TEST_CASE_START("Check filling FIFOs");
    for (int i = 0; i < NUM_FIFOS; i++) begin
      $display("Testing FIFO %0d, SIZE %0d",i,2**FIFO_SIZES[i]);
      for (int k = 0; k < 2**FIFO_SIZES[i]; k++) begin
        $sformat(s,"FIFO size should be %0d entries, but detected %0d!",2**FIFO_SIZES[i],k);
        `ASSERT_FATAL(m_axis.axis.tready[i],s);
        m_axis.push_word(k,0,i);
      end
      $sformat(s,"FIFO depth appears to be greater than %0d entries! Might be due to output registering.",2**FIFO_SIZES[i]);
      `ASSERT_WARN(~m_axis.axis.tready[i],s);
    end
    `TEST_CASE_DONE(1);


    `TEST_CASE_START("Check emptying FIFOs");
    for (int i = 0; i < NUM_FIFOS; i++) begin
      $display("Testing FIFO %0d, SIZE %0d",i,2**FIFO_SIZES[i]);
      for (int k = 0; k < 2**FIFO_SIZES[i]; k = k + 1) begin
        $sformat(s,"FIFO prematurely empty! Occured after %0d reads!",k);
        `ASSERT_FATAL(s_axis.axis.tvalid[i],s);
        s_axis.pull_word(read_word,last,i);
        $sformat(s,"Read invalid FIFO word! Expected: %0d, Actual: %0d",k,read_word);
        `ASSERT_FATAL(read_word == k,s);
      end
      `ASSERT_FATAL(~s_axis.axis.tvalid[i],"FIFO not empty after reading all entries!");
    end
    `TEST_CASE_DONE(1);


    `TEST_CASE_START("Randomized Write / Read");
    for (int i = 0; i < NUM_FIFOS; i++) begin
      $display("Testing FIFO %0d, SIZE %0d",i,2**FIFO_SIZES[i]);
      fork
      begin
        write_word = 0;
        for (int k = 0; k < NUM_ITERATIONS; k++) begin
          while ($signed($random()) > 0) @(posedge clk);
          m_axis.push_word(write_word,0,i);
          write_word++;
        end
      end
      begin
        for (int k = 0; k < NUM_ITERATIONS; k++) begin
          while ($signed($random()) > 0) @(posedge clk);
          s_axis.pull_word(read_word,last,i);
          $sformat(s,"Read invalid FIFO word! Expected: %0d, Actual: %0d",read_word,k);
          `ASSERT_FATAL(read_word == k,s);
        end
      end
      join
    end
    `TEST_CASE_DONE(1);
    `TEST_BENCH_DONE;
  end

endmodule