data/full_repos/permissive/205682213/src_v/audio_dac.v
1: b"%Error: data/full_repos/permissive/205682213/src_v/audio_dac.v:92: Cannot find file containing module: 'sigma_dac'\nsigma_dac\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205682213/src_v,data/full_repos/permissive/205682213/sigma_dac\n             data/full_repos/permissive/205682213/src_v,data/full_repos/permissive/205682213/sigma_dac.v\n             data/full_repos/permissive/205682213/src_v,data/full_repos/permissive/205682213/sigma_dac.sv\n             sigma_dac\n             sigma_dac.v\n             sigma_dac.sv\n             obj_dir/sigma_dac\n             obj_dir/sigma_dac.v\n             obj_dir/sigma_dac.sv\n%Error: data/full_repos/permissive/205682213/src_v/audio_dac.v:103: Cannot find file containing module: 'sigma_dac'\nsigma_dac\n^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module audio_dac
(

     input           clk_i
    ,input           rst_i
    ,input           audio_clk_i
    ,input           inport_tvalid_i
    ,input  [ 31:0]  inport_tdata_i
    ,input  [  3:0]  inport_tstrb_i
    ,input  [  3:0]  inport_tdest_i
    ,input           inport_tlast_i


    ,output          inport_tready_o
    ,output          audio_l_o
    ,output          audio_r_o
);







wire    bit_clock_w;

assign bit_clock_w = audio_clk_i;




reg [15:0] left_q;
reg [15:0] right_q;
reg        pop_q;

always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i)
   begin
        right_q <= 16'b0;
        left_q  <= 16'b0;
        pop_q   <= 1'b0;
   end
   else if (bit_clock_w && inport_tvalid_i)
   begin
        {right_q, left_q} <= inport_tdata_i;
        pop_q   <= 1'b1;
   end
   else
        pop_q   <= 1'b0;
end

assign inport_tready_o = pop_q;




sigma_dac
#( .NBITS(16) )
u_dac_l
(
    .clk_i(clk_i),
    .rst_i(rst_i),

    .din_i(left_q),
    .dout_o(audio_l_o)
);

sigma_dac
#( .NBITS(16) )
u_dac_r
(
    .clk_i(clk_i),
    .rst_i(rst_i),

    .din_i(right_q),
    .dout_o(audio_r_o)
);


endmodule
module audio_dac
(

     input           clk_i
    ,input           rst_i
    ,input           audio_clk_i
    ,input           inport_tvalid_i
    ,input  [ 31:0]  inport_tdata_i
    ,input  [  3:0]  inport_tstrb_i
    ,input  [  3:0]  inport_tdest_i
    ,input           inport_tlast_i


    ,output          inport_tready_o
    ,output          audio_l_o
    ,output          audio_r_o
);








wire    bit_clock_w;

assign bit_clock_w = audio_clk_i;




reg [15:0] left_q;
reg [15:0] right_q;
reg        pop_q;

always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i)
   begin
        right_q <= 16'b0;
        left_q  <= 16'b0;
        pop_q   <= 1'b0;
   end
   else if (bit_clock_w && inport_tvalid_i)
   begin
        {right_q, left_q} <= inport_tdata_i;
        pop_q   <= 1'b1;
   end
   else
        pop_q   <= 1'b0;
end

assign inport_tready_o = pop_q;




sigma_dac
#( .NBITS(16) )
u_dac_l
(
    .clk_i(clk_i),
    .rst_i(rst_i),

    .din_i(left_q),
    .dout_o(audio_l_o)
);

sigma_dac
#( .NBITS(16) )
u_dac_r
(
    .clk_i(clk_i),
    .rst_i(rst_i),

    .din_i(right_q),
    .dout_o(audio_r_o)
);


endmodule