data/full_repos/permissive/101171422/sim/counter.v
 line:25: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/counter.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #5 reset = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/counter.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #1000 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101171422/sim/counter.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #5 clock = ~clock;\n  ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_counter();
	reg        clock, reset;
	wire [3:0] count;

	initial begin
		clock = 1;
		reset = 1;
		#5 reset = 0;
		#1000 $finish;
	end
	
	always begin
		#5 clock = ~clock;
	end
	
	counter cnt(
		clock, 
		reset, 
		count
	);
endmodule
module test_counter();

	reg        clock, reset;
	wire [3:0] count;

	initial begin
		clock = 1;
		reset = 1;
		#5 reset = 0;
		#1000 $finish;
	end
	
	always begin
		#5 clock = ~clock;
	end
	
	counter cnt(
		clock, 
		reset, 
		count
	);
endmodule