data/full_repos/permissive/156417892/hdl/InstructionDecode/RegFile/RegFile_test.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionDecode/RegFile/RegFile_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionDecode/RegFile/RegFile_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionDecode/RegFile/RegFile_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionDecode/RegFile/RegFile_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionDecode/RegFile/RegFile_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #25 clk = ~clk;\n      ^\n%Error: data/full_repos/permissive/156417892/hdl/InstructionDecode/RegFile/RegFile_test.v:58: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("./RegFile.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/156417892/hdl/InstructionDecode/RegFile/RegFile_test.v:59: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_test;


   reg [4:0] rs, rt, rd;
   reg [31:0] writedata;
   reg regwrite;
   reg clk;
   

   wire [31:0] A, B;
   
   integer  i;

   RegFile uut(rs,
               rt,
               rd,
               writedata,
               A,
               B,
               regwrite,
               clk);
   initial begin

      #50;
      rs = 0;
      rt = 1;
      rd = 4;
      writedata = 5;
      regwrite = 0;
      
      #50;
      rs = 0;
      rt = 1;
      rd = 4;
      regwrite = 1;
      writedata = 5;
      
      #50;
      rs = 4;
      rt = 1;
      rd = 4;
      regwrite = 0;
      writedata = 5;
      
      #50;
      regwrite = 0;
   end
   
initial begin
   clk = 0; 
	for (i = 0; i < 200; i = i + 1)
      #25 clk = ~clk;
end

   initial begin
      $dumpfile("./RegFile.vcd");
      $dumpvars;
   end

endmodule
module main_test;



   reg [4:0] rs, rt, rd;
   reg [31:0] writedata;
   reg regwrite;
   reg clk;
   

   wire [31:0] A, B;
   
   integer  i;

   RegFile uut(rs,
               rt,
               rd,
               writedata,
               A,
               B,
               regwrite,
               clk);
   initial begin

      #50;
      rs = 0;
      rt = 1;
      rd = 4;
      writedata = 5;
      regwrite = 0;
      
      #50;
      rs = 0;
      rt = 1;
      rd = 4;
      regwrite = 1;
      writedata = 5;
      
      #50;
      rs = 4;
      rt = 1;
      rd = 4;
      regwrite = 0;
      writedata = 5;
      
      #50;
      regwrite = 0;
   end
   
initial begin
   clk = 0; 
	for (i = 0; i < 200; i = i + 1)
      #25 clk = ~clk;
end

   initial begin
      $dumpfile("./RegFile.vcd");
      $dumpvars;
   end

endmodule