data/full_repos/permissive/214823094/lab_7/project_1/project_1.srcs/sources_1/new/bus.v
data/verilator_xmls/7f7dd0f0-285f-46b7-bf12-d5571dcce98b.xml
module MUX_4_1(
    input [1:0] s,
    input [3:0] i0,
    input [3:0] i1,
    input [3:0] i2,
    input [3:0] i3,
    output reg [3:0] y
    );
    
    always@(*)
    begin 
        case(s)
        2'b00:y<=i0;
        2'b01:y<=i1;
        2'b10:y<=i2;
        2'b11:y<=i3;
        endcase
    end

endmodule
module MUX_4_1(
    input [1:0] s,
    input [3:0] i0,
    input [3:0] i1,
    input [3:0] i2,
    input [3:0] i3,
    output reg [3:0] y
    );

    
    always@(*)
    begin 
        case(s)
        2'b00:y<=i0;
        2'b01:y<=i1;
        2'b10:y<=i2;
        2'b11:y<=i3;
        endcase
    end

endmodule