data/full_repos/permissive/169380436/testbench.v
 line:34: before: "for"
1: b'%Error: data/full_repos/permissive/169380436/testbench.v:2: Cannot find include file: ./mem.v\n`include "./mem.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169380436,data/full_repos/permissive/169380436/./mem.v\n             data/full_repos/permissive/169380436,data/full_repos/permissive/169380436/./mem.v.v\n             data/full_repos/permissive/169380436,data/full_repos/permissive/169380436/./mem.v.sv\n             ./mem.v\n             ./mem.v.v\n             ./mem.v.sv\n             obj_dir/./mem.v\n             obj_dir/./mem.v.v\n             obj_dir/./mem.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/169380436/testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169380436/testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10        \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/169380436/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/169380436/testbench.v:39: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./tmp/testbench.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/169380436/testbench.v:40: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, testbench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/169380436/testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #2520\n    ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module testbench;

reg [32:0] memory [251:0];

reg [32:0] mem;
reg clk;
wire [32:0] out; 

mem mem_tb(
	.clk(clk),
	.mem(mem),
	.wave(out)
);

initial begin
	clk = 1;
	forever #1 clk = ~clk;
end

integer i;
initial begin
	mem = {33{1'b0}};
	#10
	for(i=0; i<251; i=i+1) begin
		#10
		mem = memory[i]; 
	end

end

initial begin
	$readmemb("memb.txt", memory);
end

initial begin
	$dumpfile("./tmp/testbench.vcd");
    $dumpvars(0, testbench);
    #2520
    $finish;
end

endmodule
module testbench;


reg [32:0] memory [251:0];

reg [32:0] mem;
reg clk;
wire [32:0] out; 

mem mem_tb(
	.clk(clk),
	.mem(mem),
	.wave(out)
);

initial begin
	clk = 1;
	forever #1 clk = ~clk;
end

integer i;
initial begin
	mem = {33{1'b0}};
	#10
	for(i=0; i<251; i=i+1) begin
		#10
		mem = memory[i]; 
	end

end

initial begin
	$readmemb("memb.txt", memory);
end

initial begin
	$dumpfile("./tmp/testbench.vcd");
    $dumpvars(0, testbench);
    #2520
    $finish;
end

endmodule