data/full_repos/permissive/179980995/Lab1/FA_4b_Structural/FA_4b_Structural.v
data/verilator_xmls/ea349f38-7cd9-49af-88ac-e2d7b8bbb93c.xml
module fa(a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
wire c1, c2, s1;
ha u1(a, b, s1, c1);
ha u2(s1, cin, sum, c2);
or (cout, c1, c2);
endmodule
module fa(a, b, cin, sum, cout);

input a, b, cin;
output sum, cout;
wire c1, c2, s1;
ha u1(a, b, s1, c1);
ha u2(s1, cin, sum, c2);
or (cout, c1, c2);
endmodule