data/full_repos/permissive/129527056/model/commando/sim/pcb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/129527056/model/commando/sim/pcb.v:23: Cannot find include file: pcb_model.v\n`include "pcb_model.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129527056/model/commando/sim,data/full_repos/permissive/129527056/pcb_model.v\n             data/full_repos/permissive/129527056/model/commando/sim,data/full_repos/permissive/129527056/pcb_model.v.v\n             data/full_repos/permissive/129527056/model/commando/sim,data/full_repos/permissive/129527056/pcb_model.v.sv\n             pcb_model.v\n             pcb_model.v.v\n             pcb_model.v.sv\n             obj_dir/pcb_model.v\n             obj_dir/pcb_model.v.v\n             obj_dir/pcb_model.v.sv\n%Error: Exiting due to 1 error(s)\n'
module pcb(
    input         CLK12,
    output        phiB,
    output  [8:0] H,
    output  [8:0] V,
    output        HINIT,
    output        LHBL,
    output        LVBL,

    input         FLIP,
    inout   [3:0] AB,
    inout   [7:0] DB,
    output        SCREN,
    output        LSCREN,
    output        phiSC,
    output        phiMAIN,
    input         D8CS,
    input         C8CS
);

`include "pcb_model.v"

endmodule
module pcb(
    input         CLK12,
    output        phiB,
    output  [8:0] H,
    output  [8:0] V,
    output        HINIT,
    output        LHBL,
    output        LVBL,

    input         FLIP,
    inout   [3:0] AB,
    inout   [7:0] DB,
    output        SCREN,
    output        LSCREN,
    output        phiSC,
    output        phiMAIN,
    input         D8CS,
    input         C8CS
);


`include "pcb_model.v"

endmodule