data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v
1: b'%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:90: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance seq_detect\n   num_high=1\'d0;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:91: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                       : ... In instance seq_detect\n   num_bits=1\'d0;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:145: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n       num_bits=1\'d0;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:146: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n       num_high=1\'d0;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:200: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n num_bits=1\'d1;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:201: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n num_high=1\'d1;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:255: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n num_bits=1\'d1;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:256: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n num_high=1\'d0;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:273: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n num_bits=1\'d1;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:274: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n num_high=1\'d1;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:301: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n     num_high=1\'d0;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:302: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n     num_bits=1\'d0;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:315: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n      num_high=1\'d1;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:316: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\nnum_bits=1\'d1;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:336: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n     num_bits=1\'d0;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:337: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n     num_high=1\'d0;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:346: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\nnum_bits=1\'d1;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:354: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\nnum_bits=1\'d1;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:356: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n      num_high=1\'d1;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:377: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n     num_high=1\'d0;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:378: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n     num_bits=1\'d0;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:387: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\nnum_bits=1\'d1;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:395: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\nnum_bits=1\'d1;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/21051978/processor/syn/src/seq_detector.v:397: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                        : ... In instance seq_detect\n      num_high=1\'d1;\n              ^\n%Error: Exiting due to 24 warning(s)\n'
module seq_detect (in,clk,rst,match,err);
	


	output match;

	output err;
	
	
	
	


	input in;

	input clk;

	input rst;
	
	
	
	





	

	reg match;
	reg err;

	reg [1:0] state, nextstate;

	reg [3:0] num_bits;

	reg [2:0] num_high;

	reg prev_find;
	
	
	
	


	parameter Szero = 2'b00;

	parameter Sone = 2'b01;

	parameter Sfound = 2'b10;

	parameter Serr = 2'b11;

	parameter total_bits = 4'd8;

	parameter total_high = 3'd5;
	
	
	
	
	
	

	always @(posedge clk)
	begin

		if (rst)
		begin
			num_high=1'd0;
			num_bits=1'd0;
			

			state <= Serr;
		end
		else
		begin

			state <= nextstate;
			num_bits=num_bits+1'd1;
			
			
			if (in==1'b1)
			begin
				num_high=num_high+1;
			end
		end
	end
	
	
	
	
	

	always @(in or state or nextstate)
	begin
		case (state)
			Sone:
				begin
					if((num_bits==4'd2)||(num_bits==4'd3)||(num_bits==4'd6))
					begin
$display($time, ">>>>>>>>>>state",state,"num_bits",num_bits);


					end
				
					if((in == 1'bz) || (in == 1'bx))
					begin

						$display($time, " << Err@1 >>");
						nextstate <= Serr;
					end
					else
					begin
						

						if ((in==1'd1) & (total_bits==num_bits)
							& (total_high==num_high))
						begin
							num_bits=1'd0;
							num_high=1'd0;
$display($time, "NUM_BITS and NUM_HIGH are RESET");

			
							$display($time, " << Go to State Sfound >>");
							nextstate <= Sfound;
						end
						else if(in == 1'b0)
						begin




if(num_bits==4'd0)
begin
	$display($time, "##############state",state,"num_bits",num_bits);
	num_bits=4'd2;
	num_high=3'd1;
end

							$display($time, " <<pre Szero >>");
							$display(num_high,"=!=",num_bits);
							


							$display($time, " << Szero >>");
							$display(num_high,"=!=",num_bits);

							nextstate <= Szero;
						end
						else
						begin
if(~((num_bits==4'd5) || (num_bits==4'd7) || (num_bits==4'd8)))
begin
	$display($time, "1----<<<state",state,"num_bits",num_bits);
	num_bits=1'd1;
	num_high=1'd1;
end
							$display($time, " << pre Sone>>");
							$display(num_high,"=!=",num_bits);
							





							$display($time, " << Sone>>");
							$display(num_high,"=!=",num_bits);

							nextstate <= Sone;
						end
					end
				end
				
				
				
				
				
			Szero:
				begin
					if((num_bits==4'd1)||(num_bits==4'd4)||(num_bits==4'd5)
						&(num_bits==4'd7)||(num_bits==4'd8))
					begin
$display($time, "<<<<<<<<<<state",state,"num_bits",num_bits);


					end
				
$display($time, " from state1::",state,"num_bits",num_bits,"in",in);				
					
					if((in == 1'bz) || (in == 1'bx))
					begin

						$display($time, " << Err@0 >>");
						nextstate <= Serr;
					end
					else
					begin

						if(in == 1'd0)
						begin
if((num_bits!=4'd2)&&(num_bits!=4'd3))
begin
	$display($time, "0---->>>state",state,"num_bits",num_bits);
	num_bits=1'd1;
	num_high=1'd0;
end
							$display($time, " << pre Szero >>");
							$display(num_high,"=!=",num_bits);
							


							$display($time, " << Szero >>");
							$display(num_high,"=!=",num_bits);
							nextstate <= Szero;
						end
						else
						begin
/



							$display($time, " << Sone>>");
							$display(num_high,"=!=",num_bits);
							nextstate <= Sone;
						end
					end
				end
				
				
				
				
				
			Sfound:
				begin
$display($time, "NUM_BITS==0 and NUM_HIGH==0");

					num_high=1'd0;
					num_bits=1'd0;
					prev_find=1'd1;
					
					$display($time, " << Reached State Sfound >>", num_bits);

					if(in == 1'd0)
					begin
						$display($time, " << Go to State Szero >>",num_bits);
						nextstate <= Szero;
					end
					else if(in == 1'd1)
					begin

						num_high=1'd1;
num_bits=1'd1;
					
						$display($time, "!!!!!!!!!!!!!!!!SGo to State Sone>>",num_bits);
						nextstate <= Sone;
					end
					else
					begin

						$display($time, " << Go to State Serr>>",num_bits);
						nextstate <= Serr;
					end
				end
				
				
				
				
			Serr:
				begin
$display($time, "NUM_BITS==NUM_HIGH==0");

					num_bits=1'd0;
					num_high=1'd0;
					
					
					$display($time, " << Reached State Serr >>", num_bits);

					if((in == 1'd0) & (rst==1'd0))
					begin


num_bits=1'd1;
						$display($time, " << Go to State Szero >>",num_bits);
						nextstate <= Szero;
					end
				   else if((in == 1'd1) & (rst==1'd0))
					begin


num_bits=1'd1;

						num_high=1'd1;
					
						$display($time, " << Go to State Sone>>",num_bits);
						nextstate <= Sone;
					end
					else
					begin

						$display($time, " << Go to State Sone>>",num_bits);
						nextstate <= Serr;
					end
				end
				
				
			
			

			default:
				begin
$display($time, "NUM_BITS  &&&  NUM_HIGH R RESET");

					num_high=1'd0;
					num_bits=1'd0;
					
					
					$display($time, " << Reached State Serr >>", num_bits);

					if((in == 1'd0) & (rst==1'd0))
					begin


num_bits=1'd1;
						$display($time, " << Go to State Szero >>",num_bits);
						nextstate <= Szero;
					end
					else if((in == 1'd1) & (rst==1'd0))
					begin


num_bits=1'd1;

						num_high=1'd1;
					
						$display($time, " << Go to State Sone>>",num_bits);
						nextstate <= Sone;
					end
					else
					begin

						$display($time, " << Go to State Sone>>",num_bits);
						nextstate <= Serr;
					end
				end
		endcase
	end
	
	

	always @(state)
	begin
		case(state)
			Sone:
				begin
					match=1'd0;
					err=1'd0;
				end
			Szero:
				begin
					match=1'd0;
					err=1'd0;
				end
			Sfound:
				begin
					match=1'd1;
					err=1'd0;
				end
			Serr:
				begin
					match=1'd0;
					err=1'd1;
				end
			
			

			default:
				begin
					match=1'd0;
					err=1'd1;
				end
		endcase
	end
	
endmodule
module seq_detect (in,clk,rst,match,err);

	


	output match;

	output err;
	
	
	
	


	input in;

	input clk;

	input rst;
	
	
	
	





	

	reg match;
	reg err;

	reg [1:0] state, nextstate;

	reg [3:0] num_bits;

	reg [2:0] num_high;

	reg prev_find;
	
	
	
	


	parameter Szero = 2'b00;

	parameter Sone = 2'b01;

	parameter Sfound = 2'b10;

	parameter Serr = 2'b11;

	parameter total_bits = 4'd8;

	parameter total_high = 3'd5;
	
	
	
	
	
	

	always @(posedge clk)
	begin

		if (rst)
		begin
			num_high=1'd0;
			num_bits=1'd0;
			

			state <= Serr;
		end
		else
		begin

			state <= nextstate;
			num_bits=num_bits+1'd1;
			
			
			if (in==1'b1)
			begin
				num_high=num_high+1;
			end
		end
	end
	
	
	
	
	

	always @(in or state or nextstate)
	begin
		case (state)
			Sone:
				begin
					if((num_bits==4'd2)||(num_bits==4'd3)||(num_bits==4'd6))
					begin
$display($time, ">>>>>>>>>>state",state,"num_bits",num_bits);


					end
				
					if((in == 1'bz) || (in == 1'bx))
					begin

						$display($time, " << Err@1 >>");
						nextstate <= Serr;
					end
					else
					begin
						

						if ((in==1'd1) & (total_bits==num_bits)
							& (total_high==num_high))
						begin
							num_bits=1'd0;
							num_high=1'd0;
$display($time, "NUM_BITS and NUM_HIGH are RESET");

			
							$display($time, " << Go to State Sfound >>");
							nextstate <= Sfound;
						end
						else if(in == 1'b0)
						begin




if(num_bits==4'd0)
begin
	$display($time, "##############state",state,"num_bits",num_bits);
	num_bits=4'd2;
	num_high=3'd1;
end

							$display($time, " <<pre Szero >>");
							$display(num_high,"=!=",num_bits);
							


							$display($time, " << Szero >>");
							$display(num_high,"=!=",num_bits);

							nextstate <= Szero;
						end
						else
						begin
if(~((num_bits==4'd5) || (num_bits==4'd7) || (num_bits==4'd8)))
begin
	$display($time, "1----<<<state",state,"num_bits",num_bits);
	num_bits=1'd1;
	num_high=1'd1;
end
							$display($time, " << pre Sone>>");
							$display(num_high,"=!=",num_bits);
							





							$display($time, " << Sone>>");
							$display(num_high,"=!=",num_bits);

							nextstate <= Sone;
						end
					end
				end
				
				
				
				
				
			Szero:
				begin
					if((num_bits==4'd1)||(num_bits==4'd4)||(num_bits==4'd5)
						&(num_bits==4'd7)||(num_bits==4'd8))
					begin
$display($time, "<<<<<<<<<<state",state,"num_bits",num_bits);


					end
				
$display($time, " from state1::",state,"num_bits",num_bits,"in",in);				
					
					if((in == 1'bz) || (in == 1'bx))
					begin

						$display($time, " << Err@0 >>");
						nextstate <= Serr;
					end
					else
					begin

						if(in == 1'd0)
						begin
if((num_bits!=4'd2)&&(num_bits!=4'd3))
begin
	$display($time, "0---->>>state",state,"num_bits",num_bits);
	num_bits=1'd1;
	num_high=1'd0;
end
							$display($time, " << pre Szero >>");
							$display(num_high,"=!=",num_bits);
							


							$display($time, " << Szero >>");
							$display(num_high,"=!=",num_bits);
							nextstate <= Szero;
						end
						else
						begin
/



							$display($time, " << Sone>>");
							$display(num_high,"=!=",num_bits);
							nextstate <= Sone;
						end
					end
				end
				
				
				
				
				
			Sfound:
				begin
$display($time, "NUM_BITS==0 and NUM_HIGH==0");

					num_high=1'd0;
					num_bits=1'd0;
					prev_find=1'd1;
					
					$display($time, " << Reached State Sfound >>", num_bits);

					if(in == 1'd0)
					begin
						$display($time, " << Go to State Szero >>",num_bits);
						nextstate <= Szero;
					end
					else if(in == 1'd1)
					begin

						num_high=1'd1;
num_bits=1'd1;
					
						$display($time, "!!!!!!!!!!!!!!!!SGo to State Sone>>",num_bits);
						nextstate <= Sone;
					end
					else
					begin

						$display($time, " << Go to State Serr>>",num_bits);
						nextstate <= Serr;
					end
				end
				
				
				
				
			Serr:
				begin
$display($time, "NUM_BITS==NUM_HIGH==0");

					num_bits=1'd0;
					num_high=1'd0;
					
					
					$display($time, " << Reached State Serr >>", num_bits);

					if((in == 1'd0) & (rst==1'd0))
					begin


num_bits=1'd1;
						$display($time, " << Go to State Szero >>",num_bits);
						nextstate <= Szero;
					end
				   else if((in == 1'd1) & (rst==1'd0))
					begin


num_bits=1'd1;

						num_high=1'd1;
					
						$display($time, " << Go to State Sone>>",num_bits);
						nextstate <= Sone;
					end
					else
					begin

						$display($time, " << Go to State Sone>>",num_bits);
						nextstate <= Serr;
					end
				end
				
				
			
			

			default:
				begin
$display($time, "NUM_BITS  &&&  NUM_HIGH R RESET");

					num_high=1'd0;
					num_bits=1'd0;
					
					
					$display($time, " << Reached State Serr >>", num_bits);

					if((in == 1'd0) & (rst==1'd0))
					begin


num_bits=1'd1;
						$display($time, " << Go to State Szero >>",num_bits);
						nextstate <= Szero;
					end
					else if((in == 1'd1) & (rst==1'd0))
					begin


num_bits=1'd1;

						num_high=1'd1;
					
						$display($time, " << Go to State Sone>>",num_bits);
						nextstate <= Sone;
					end
					else
					begin

						$display($time, " << Go to State Sone>>",num_bits);
						nextstate <= Serr;
					end
				end
		endcase
	end
	
	

	always @(state)
	begin
		case(state)
			Sone:
				begin
					match=1'd0;
					err=1'd0;
				end
			Szero:
				begin
					match=1'd0;
					err=1'd0;
				end
			Sfound:
				begin
					match=1'd1;
					err=1'd0;
				end
			Serr:
				begin
					match=1'd0;
					err=1'd1;
				end
			
			

			default:
				begin
					match=1'd0;
					err=1'd1;
				end
		endcase
	end
	
endmodule