data/full_repos/permissive/114652687/dut1/counter.v
 line:21: before: "or"
data/verilator_xmls/78751ed0-16cf-4bb4-bec4-fb3b39a04e74.xml
module counter #(parameter Size = 32) (
  input                   clock,
  input                   reset,
  output reg [Size-1 : 0] count
);
  always @(posedge clock or posedge reset) begin
    if (reset)
      count <= 0;
    else
      count <= count + 1;
  end
endmodule
module counter #(parameter Size = 32) (
  input                   clock,
  input                   reset,
  output reg [Size-1 : 0] count
);

  always @(posedge clock or posedge reset) begin
    if (reset)
      count <= 0;
    else
      count <= count + 1;
  end
endmodule