data/full_repos/permissive/14593708/tests/data-path-testbench.v
 line:24: before: "assign"
1: b'%Error: data/full_repos/permissive/14593708/tests/data-path-testbench.v:19: Unsupported or unknown PLI call: $monitor\n        $monitor("%d,\\t%d,\\t%d,\\t%b,\\t\\t%b\\t%d\\t%d",\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n     #0 assign output_enable = 1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n     #0 assign output_source_selector = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n     #0 assign immediate_1 = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n     #0 assign output_register_selector = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n     #0 assign immediate_1 = 21;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n     #1 assign output_register_selector = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n     #1 assign immediate_1 = 42;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n     #2 assign output_register_selector = 2;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n     #2 assign immediate_1 = 84;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n     #3 assign output_register_selector = 3;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n     #3 assign immediate_1 = 168;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n     #4 assign output_enable = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n     #4 assign input_register_selector_1 = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n     #4 assign input_register_selector_2 = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n     #5 assign input_register_selector_1 = 2;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n     #5 assign input_register_selector_2 = 3;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n     #6 assign input_register_selector_1 = 2;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n     #6 assign input_register_selector_2 = 3;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n     #6 assign output_register_selector = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n     #6 assign output_source_selector = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n     #6 assign output_enable = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\n     #6 assign alu_opcode = \'b10;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n     #7 assign output_enable = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:55: Unsupported: Ignoring delay on this delayed statement.\n     #7 assign input_register_selector_1 = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/14593708/tests/data-path-testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n     #7 assign input_register_selector_2 = 0;\n     ^\n%Error: Exiting due to 1 error(s), 25 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module data_path_testbench;

    reg[1:0]  input_register_selector_1;
    reg[1:0]  input_register_selector_2;
    reg[1:0]  output_register_selector;
    reg[1:0]  output_source_selector;
    reg       output_enable;
    reg[1:0]  alu_opcode;
    reg[31:0] immediate_1;
    reg[31:0] immediate_2;

    data_path data_path_0(input_register_selector_1, input_register_selector_2,
                          output_register_selector, output_source_selector,
                          output_enable, alu_opcode, immediate_1, immediate_2);

    initial
    begin
        $display("a\tb\tout\tout enabled\talu_opcode\tout data 1\tout data 2");
        $monitor("%d,\t%d,\t%d,\t%b,\t\t%b\t%d\t%d",
                 input_register_selector_1, input_register_selector_2,
                 output_register_selector, output_enable, alu_opcode,
                 data_path_0.input_data_1, data_path_0.input_data_2);

     #0 assign output_enable = 1;
     #0 assign output_source_selector = 1;
     #0 assign immediate_1 = 0;

     #0 assign output_register_selector = 0;
     #0 assign immediate_1 = 21;

     #1 assign output_register_selector = 1;
     #1 assign immediate_1 = 42;

     #2 assign output_register_selector = 2;
     #2 assign immediate_1 = 84;

     #3 assign output_register_selector = 3;
     #3 assign immediate_1 = 168;

     #4 assign output_enable = 0;
     #4 assign input_register_selector_1 = 0;
     #4 assign input_register_selector_2 = 1;

     #5 assign input_register_selector_1 = 2;
     #5 assign input_register_selector_2 = 3;

     #6 assign input_register_selector_1 = 2;
     #6 assign input_register_selector_2 = 3;
     #6 assign output_register_selector = 0;
     #6 assign output_source_selector = 0;
     #6 assign output_enable = 1;
     #6 assign alu_opcode = 'b10;

     #7 assign output_enable = 0;
     #7 assign input_register_selector_1 = 0;
     #7 assign input_register_selector_2 = 0;
    end

endmodule
module data_path_testbench;


    reg[1:0]  input_register_selector_1;
    reg[1:0]  input_register_selector_2;
    reg[1:0]  output_register_selector;
    reg[1:0]  output_source_selector;
    reg       output_enable;
    reg[1:0]  alu_opcode;
    reg[31:0] immediate_1;
    reg[31:0] immediate_2;

    data_path data_path_0(input_register_selector_1, input_register_selector_2,
                          output_register_selector, output_source_selector,
                          output_enable, alu_opcode, immediate_1, immediate_2);

    initial
    begin
        $display("a\tb\tout\tout enabled\talu_opcode\tout data 1\tout data 2");
        $monitor("%d,\t%d,\t%d,\t%b,\t\t%b\t%d\t%d",
                 input_register_selector_1, input_register_selector_2,
                 output_register_selector, output_enable, alu_opcode,
                 data_path_0.input_data_1, data_path_0.input_data_2);

     #0 assign output_enable = 1;
     #0 assign output_source_selector = 1;
     #0 assign immediate_1 = 0;

     #0 assign output_register_selector = 0;
     #0 assign immediate_1 = 21;

     #1 assign output_register_selector = 1;
     #1 assign immediate_1 = 42;

     #2 assign output_register_selector = 2;
     #2 assign immediate_1 = 84;

     #3 assign output_register_selector = 3;
     #3 assign immediate_1 = 168;

     #4 assign output_enable = 0;
     #4 assign input_register_selector_1 = 0;
     #4 assign input_register_selector_2 = 1;

     #5 assign input_register_selector_1 = 2;
     #5 assign input_register_selector_2 = 3;

     #6 assign input_register_selector_1 = 2;
     #6 assign input_register_selector_2 = 3;
     #6 assign output_register_selector = 0;
     #6 assign output_source_selector = 0;
     #6 assign output_enable = 1;
     #6 assign alu_opcode = 'b10;

     #7 assign output_enable = 0;
     #7 assign input_register_selector_1 = 0;
     #7 assign input_register_selector_2 = 0;
    end

endmodule