data/full_repos/permissive/21702465/source/Osc_Ring.v
 line:27: before: ","
1: b"%Error: data/full_repos/permissive/21702465/source/Osc_Ring.v:33: Cannot find file containing module: 'LUT1'\n LUT1 #(\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/21702465/source,data/full_repos/permissive/21702465/LUT1\n             data/full_repos/permissive/21702465/source,data/full_repos/permissive/21702465/LUT1.v\n             data/full_repos/permissive/21702465/source,data/full_repos/permissive/21702465/LUT1.sv\n             LUT1\n             LUT1.v\n             LUT1.sv\n             obj_dir/LUT1\n             obj_dir/LUT1.v\n             obj_dir/LUT1.sv\n%Error: data/full_repos/permissive/21702465/source/Osc_Ring.v:44: Cannot find file containing module: 'FD'\nFD Sample (\n^~\n%Error: Exiting due to 2 error(s)\n"
module Osc_Ring #(parameter n = 3)(
    input wire clk,
	 input wire rst,
    output wire out
    );

(*S = "YES", KEEP = "TRUE"*)wire [n:0] c;

genvar k;
generate
for (k = n-1; k >= 0; k = k - 1)
begin: inverter
	LUT1 #(
	.INIT(2'b01) 
	) inverter (
	.O(c[k]), 
	.I0(c[k+1]) 
	);
end
endgenerate

assign c[n] = rst? 1'b1 : c[0];

FD Sample (
	.Q (out),
	.C (clk),
	.D (c[0]));


endmodule
module Osc_Ring #(parameter n = 3)(
    input wire clk,
	 input wire rst,
    output wire out
    );


(*S = "YES", KEEP = "TRUE"*)wire [n:0] c;

genvar k;
generate
for (k = n-1; k >= 0; k = k - 1)
begin: inverter
	LUT1 #(
	.INIT(2'b01) 
	) inverter (
	.O(c[k]), 
	.I0(c[k+1]) 
	);
end
endgenerate

assign c[n] = rst? 1'b1 : c[0];

FD Sample (
	.Q (out),
	.C (clk),
	.D (c[0]));


endmodule