data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v
 line:70: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10 rst = 1\'b1;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #160 data_in = 8\'b10010110;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #160 tx_st = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #100 tx_st = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #1160 data_in = 8\'b10000110;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #160 tx_st = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #100 tx_st = 1\'b0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #1000 tx_st = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #100 tx_st = 1\'b0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #10000 rst = 1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #10000 rst = 1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #500000 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:73: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 clock=~clock;   \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:74: Unsupported: Ignoring delay on this delayed statement.\nalways #5 stick=~stick;   \n       ^\n%Error: data/full_repos/permissive/206437232/TP2-UART-2019/Test/tb_tx.v:78: Cannot find file containing module: \'uart_tx\'\nuart_tx\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP2-UART-2019/Test,data/full_repos/permissive/206437232/uart_tx\n             data/full_repos/permissive/206437232/TP2-UART-2019/Test,data/full_repos/permissive/206437232/uart_tx.v\n             data/full_repos/permissive/206437232/TP2-UART-2019/Test,data/full_repos/permissive/206437232/uart_tx.sv\n             uart_tx\n             uart_tx.v\n             uart_tx.sv\n             obj_dir/uart_tx\n             obj_dir/uart_tx.v\n             obj_dir/uart_tx.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_tx();


    parameter DBIT_TEST     = 8;
    parameter SB_TICK_TEST  = 16;
    


    

    reg                 clock;
    reg                 stick;
    reg                 rst;
    reg                 tx_st;
    reg [DBIT_TEST-1:0] data_in;
    wire                bit_tx;
    wire                tx_done;



    initial	begin
        stick = 1'b0;
        clock = 1'b0;
        rst = 1'b0;
        data_in = 8'b00000000;
        tx_st = 1'b0;
        #10 rst = 1'b1;
        

        #160 data_in = 8'b10010110;
        
        #160 tx_st = 1'b1;
        #100 tx_st = 1'b0;
    

        #1160 data_in = 8'b10000110;
        #160 tx_st = 1'b1;
        #100 tx_st = 1'b0; 
        

        #1000 tx_st = 1'b1;
        #100 tx_st = 1'b0; 
                

        #10000 rst = 1'b0;
        #10000 rst = 1'b1;
        
        
        #500000 $finish;
    end

always #2.5 clock=~clock;
always #5 stick=~stick;



uart_tx
#(
     .WIDTH_WORD_TX (DBIT_TEST),
     .CANT_BIT_STOP (SB_TICK_TEST)
 ) 
u_tx_1    
(
  .i_clk (clock),
  .s_tick (stick),
  .din (data_in),
  .reset (rst),
  .tx_start (tx_st),
  .tx (bit_tx),
  .tx_done_tick (tx_done)
);

endmodule
module tb_tx();



    parameter DBIT_TEST     = 8;
    parameter SB_TICK_TEST  = 16;
    


    

    reg                 clock;
    reg                 stick;
    reg                 rst;
    reg                 tx_st;
    reg [DBIT_TEST-1:0] data_in;
    wire                bit_tx;
    wire                tx_done;



    initial	begin
        stick = 1'b0;
        clock = 1'b0;
        rst = 1'b0;
        data_in = 8'b00000000;
        tx_st = 1'b0;
        #10 rst = 1'b1;
        

        #160 data_in = 8'b10010110;
        
        #160 tx_st = 1'b1;
        #100 tx_st = 1'b0;
    

        #1160 data_in = 8'b10000110;
        #160 tx_st = 1'b1;
        #100 tx_st = 1'b0; 
        

        #1000 tx_st = 1'b1;
        #100 tx_st = 1'b0; 
                

        #10000 rst = 1'b0;
        #10000 rst = 1'b1;
        
        
        #500000 $finish;
    end

always #2.5 clock=~clock;
always #5 stick=~stick;



uart_tx
#(
     .WIDTH_WORD_TX (DBIT_TEST),
     .CANT_BIT_STOP (SB_TICK_TEST)
 ) 
u_tx_1    
(
  .i_clk (clock),
  .s_tick (stick),
  .din (data_in),
  .reset (rst),
  .tx_start (tx_st),
  .tx (bit_tx),
  .tx_done_tick (tx_done)
);

endmodule