data/full_repos/permissive/143278/ivltests/signed12.v
 line:9: before: "$"
1: b'%Error: data/full_repos/permissive/143278/ivltests/signed12.v:9: Unsupported: Use $display with %b format instead: $displayb\n  initial #1 $displayb(out);\n             ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/signed12.v:9: Unsupported: Ignoring delay on this delayed statement.\n  initial #1 $displayb(out);\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

  wire signed [7:0] out;



  assign out = 5'sh1f;

  initial #1 $displayb(out);
endmodule
module top;


  wire signed [7:0] out;



  assign out = 5'sh1f;

  initial #1 $displayb(out);
endmodule