data/full_repos/permissive/121410129/Step4/TB4_Gray.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/121410129/Step4/TB4_Gray.v:25: Unsupported: Ignoring delay on this delayed statement.\n #50 reset <= 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/121410129/Step4/TB4_Gray.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Error: data/full_repos/permissive/121410129/Step4/TB4_Gray.v:36: Cannot find file containing module: \'GrayCounter_System\'\nGrayCounter_System #(N, distance) GrayCounter_System(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/121410129/Step4,data/full_repos/permissive/121410129/GrayCounter_System\n             data/full_repos/permissive/121410129/Step4,data/full_repos/permissive/121410129/GrayCounter_System.v\n             data/full_repos/permissive/121410129/Step4,data/full_repos/permissive/121410129/GrayCounter_System.sv\n             GrayCounter_System\n             GrayCounter_System.v\n             GrayCounter_System.sv\n             obj_dir/GrayCounter_System\n             obj_dir/GrayCounter_System.v\n             obj_dir/GrayCounter_System.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB4();
parameter N = 8;
parameter distance = 1000;
reg clk, reset;
wire [N-1:0] leds;


initial begin

	clk <= 1'b1;
	reset <= 1'b1;
	#50 reset <= 1'b0;
end


always begin
	#5 clk <= ~clk;
end




GrayCounter_System #(N, distance) GrayCounter_System(
	.clk	(clk),
	.reset	(reset),
	.leds	(leds)
);

endmodule
module TB4();

parameter N = 8;
parameter distance = 1000;
reg clk, reset;
wire [N-1:0] leds;


initial begin

	clk <= 1'b1;
	reset <= 1'b1;
	#50 reset <= 1'b0;
end


always begin
	#5 clk <= ~clk;
end




GrayCounter_System #(N, distance) GrayCounter_System(
	.clk	(clk),
	.reset	(reset),
	.leds	(leds)
);

endmodule