data/full_repos/permissive/21203606/ex2/ext2_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/21203606/ex2/ext2_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #250\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21203606/ex2/ext2_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #250\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21203606/ex2/ext2_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #250\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21203606/ex2/ext2_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #1000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21203606/ex2/ext2_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #50 tb_clk <= ~tb_clk;\n  ^\n%Error: data/full_repos/permissive/21203606/ex2/ext2_tb.v:13: Cannot find file containing module: \'foo_counter\'\nfoo_counter counterfoo(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21203606/ex2,data/full_repos/permissive/21203606/foo_counter\n             data/full_repos/permissive/21203606/ex2,data/full_repos/permissive/21203606/foo_counter.v\n             data/full_repos/permissive/21203606/ex2,data/full_repos/permissive/21203606/foo_counter.sv\n             foo_counter\n             foo_counter.v\n             foo_counter.sv\n             obj_dir/foo_counter\n             obj_dir/foo_counter.v\n             obj_dir/foo_counter.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ext2_tb ();
  


reg tb_clk;
reg tb_rst;
reg tb_en;
wire [7:0] tb_cnt;


foo_counter counterfoo(
  .clk(tb_clk),
  .rst(tb_rst),
  .en(tb_en),
  .cnt(tb_cnt));
  

initial
begin
  tb_clk <= 0;
  tb_rst <= 0;
  tb_en <= 0;
  
  #250
  tb_rst <= 1'b1;
  #250
  tb_rst <= 1'b0;
  
  #250
  tb_en <= 1'b1;
  #1000
  tb_en <= 0'b0;
  
end


always
begin
  #50 tb_clk <= ~tb_clk;
end

endmodule
module ext2_tb ();

  


reg tb_clk;
reg tb_rst;
reg tb_en;
wire [7:0] tb_cnt;


foo_counter counterfoo(
  .clk(tb_clk),
  .rst(tb_rst),
  .en(tb_en),
  .cnt(tb_cnt));
  

initial
begin
  tb_clk <= 0;
  tb_rst <= 0;
  tb_en <= 0;
  
  #250
  tb_rst <= 1'b1;
  #250
  tb_rst <= 1'b0;
  
  #250
  tb_en <= 1'b1;
  #1000
  tb_en <= 0'b0;
  
end


always
begin
  #50 tb_clk <= ~tb_clk;
end

endmodule