data/full_repos/permissive/118895561/Project 2/alu.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/118895561\n        ... Looked in:\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561.v\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561.sv\n             2,data/full_repos/permissive/118895561\n             2,data/full_repos/permissive/118895561.v\n             2,data/full_repos/permissive/118895561.sv\n             obj_dir/2,data/full_repos/permissive/118895561\n             obj_dir/2,data/full_repos/permissive/118895561.v\n             obj_dir/2,data/full_repos/permissive/118895561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/118895561/Project\n%Error: Cannot find file containing module: 2/alu.v\n%Error: Exiting due to 3 error(s)\n'
module alu(
	input			[31:0] A,
	input 		[31:0] B,
	input 		[3:0]  Op,
	output reg  [31:0] C,
	output reg			 Overflow
    );
	reg C_Top;
	reg [31:0] C_Temp;
	integer i;
	always @* begin
		case(Op)
			4'b0000:	C = A + B;
			4'b0001: C = A & B;
			4'b0010: C = A ^ B;
			4'b0011: C = B << A[4:0];
			4'b0100: 
				begin
					{C_Top, C} = {A[31], A} - {B[31], B};
					Overflow = (C_Top != C[31]);
				end
			4'b0101: C = A | B;
			4'b0110: C = {B[15:0], 16'b0};
			4'b0111: C = B >> A[4:0];
			4'b1000: C = A - B;
			4'b1001:
				begin
					{C_Top, C} = {A[31], A} + {B[31], B};
					Overflow = (C_Top != C[31]);
				end
			4'b1010: C = B << A[4:0];
			4'b1011: C = B;
			4'b1100: ;
			4'b1101: C = $signed(B) <<< A[4:0];
			4'b1110: C = ~( A | B );
			4'b1111: C = $signed(B) >>> A[4:0];
			default:	C = 32'bx;
		endcase
		if(Op != 4'b0100 && Op != 4'b1001)
			Overflow = 0;
			
	end

endmodule
module alu(
	input			[31:0] A,
	input 		[31:0] B,
	input 		[3:0]  Op,
	output reg  [31:0] C,
	output reg			 Overflow
    );

	reg C_Top;
	reg [31:0] C_Temp;
	integer i;
	always @* begin
		case(Op)
			4'b0000:	C = A + B;
			4'b0001: C = A & B;
			4'b0010: C = A ^ B;
			4'b0011: C = B << A[4:0];
			4'b0100: 
				begin
					{C_Top, C} = {A[31], A} - {B[31], B};
					Overflow = (C_Top != C[31]);
				end
			4'b0101: C = A | B;
			4'b0110: C = {B[15:0], 16'b0};
			4'b0111: C = B >> A[4:0];
			4'b1000: C = A - B;
			4'b1001:
				begin
					{C_Top, C} = {A[31], A} + {B[31], B};
					Overflow = (C_Top != C[31]);
				end
			4'b1010: C = B << A[4:0];
			4'b1011: C = B;
			4'b1100: ;
			4'b1101: C = $signed(B) <<< A[4:0];
			4'b1110: C = ~( A | B );
			4'b1111: C = $signed(B) >>> A[4:0];
			default:	C = 32'bx;
		endcase
		if(Op != 4'b0100 && Op != 4'b1001)
			Overflow = 0;
			
	end

endmodule