data/full_repos/permissive/167161024/spi_send_only.v
data/verilator_xmls/23d33bb2-21c0-4341-8672-841ca7a68ac4.xml
module spi_send_only(
					 input 			  clock,
					 input 			  reset_n,
					 input 			  trigger,
					 output reg 	  busy,
					 input [4:0] 	  packs_to_send,

					 input [63:0] 	  data_input,

					 output reg 	  cs,
					 output reg 	  sclk,
					 output reg [3:0] sdio
);

   parameter
	 STATE_IDLE = 0,
	 STATE_SEND = 1;

   reg 								  state;
   reg [4:0] 						  packs_cntr;


   reg [63:0] 						  data_send;
   
   




   
   always @(posedge clock) begin
	  if(~reset_n) begin
		 cs <= 0;
		 state <= STATE_IDLE;
		 busy <= 1;
		 sclk <= 1'b1;
		 sdio <= 4'b0;
		 packs_cntr <= 5'b0;
	  end else begin
		 case(state)
		   STATE_IDLE : begin
			  if(trigger & ~busy) begin
				 state <= STATE_SEND;
				 busy <= 1;
				 packs_cntr <= packs_to_send;
				 data_send <= data_input;				 
			  end else begin
				 busy <= 0;
				 sclk <= 1'b1;
				 sdio <= 4'b0;
				 packs_cntr <= 5'b0;
			  end
		   end
		   
		   STATE_SEND : begin
			  sclk <= 1'b0;
		   end
		   
		   default : begin
		   end
		 endcase
	  end
   end

   always @(negedge clock)begin
	  if(~reset_n) begin
	  end else begin
		 case(state)
		   STATE_IDLE : begin
		   end

		   STATE_SEND : begin
			  sclk <= 1'b1;
		   end

		   default :begin
		   end

		 endcase
	  end
   end


   always @(negedge sclk) begin
	  if(~reset_n) begin
		 sdio <= 4'b0;
	  end else begin
		 case (state)
		   STATE_IDLE : begin
		   end

		   STATE_SEND : begin

			  sdio[0] <= data_send[0];
			  sdio[1] <= data_send[1];
			  sdio[2] <= data_send[2];
			  sdio[3] <= data_send[3];

			  packs_cntr <= packs_cntr - 1;
		   end

		   default : begin
		   end
		 endcase
	  end
   end

   always @(posedge sclk) begin
	  case (state)
		STATE_IDLE :begin
		end

		STATE_SEND : begin
		   if(packs_cntr == 0) begin
			  data_send <= 64'h0;
			  state <= STATE_IDLE;
		   end else begin


			  data_send <= (data_send >> 4);
		   end
		end
	  endcase
   end
endmodule
module spi_send_only(
					 input 			  clock,
					 input 			  reset_n,
					 input 			  trigger,
					 output reg 	  busy,
					 input [4:0] 	  packs_to_send,

					 input [63:0] 	  data_input,

					 output reg 	  cs,
					 output reg 	  sclk,
					 output reg [3:0] sdio
);


   parameter
	 STATE_IDLE = 0,
	 STATE_SEND = 1;

   reg 								  state;
   reg [4:0] 						  packs_cntr;


   reg [63:0] 						  data_send;
   
   




   
   always @(posedge clock) begin
	  if(~reset_n) begin
		 cs <= 0;
		 state <= STATE_IDLE;
		 busy <= 1;
		 sclk <= 1'b1;
		 sdio <= 4'b0;
		 packs_cntr <= 5'b0;
	  end else begin
		 case(state)
		   STATE_IDLE : begin
			  if(trigger & ~busy) begin
				 state <= STATE_SEND;
				 busy <= 1;
				 packs_cntr <= packs_to_send;
				 data_send <= data_input;				 
			  end else begin
				 busy <= 0;
				 sclk <= 1'b1;
				 sdio <= 4'b0;
				 packs_cntr <= 5'b0;
			  end
		   end
		   
		   STATE_SEND : begin
			  sclk <= 1'b0;
		   end
		   
		   default : begin
		   end
		 endcase
	  end
   end

   always @(negedge clock)begin
	  if(~reset_n) begin
	  end else begin
		 case(state)
		   STATE_IDLE : begin
		   end

		   STATE_SEND : begin
			  sclk <= 1'b1;
		   end

		   default :begin
		   end

		 endcase
	  end
   end


   always @(negedge sclk) begin
	  if(~reset_n) begin
		 sdio <= 4'b0;
	  end else begin
		 case (state)
		   STATE_IDLE : begin
		   end

		   STATE_SEND : begin

			  sdio[0] <= data_send[0];
			  sdio[1] <= data_send[1];
			  sdio[2] <= data_send[2];
			  sdio[3] <= data_send[3];

			  packs_cntr <= packs_cntr - 1;
		   end

		   default : begin
		   end
		 endcase
	  end
   end

   always @(posedge sclk) begin
	  case (state)
		STATE_IDLE :begin
		end

		STATE_SEND : begin
		   if(packs_cntr == 0) begin
			  data_send <= 64'h0;
			  state <= STATE_IDLE;
		   end else begin


			  data_send <= (data_send >> 4);
		   end
		end
	  endcase
   end
endmodule