data/full_repos/permissive/126160535/verilog/code/synt/cam_config/OV7670_config_rom.v
data/verilator_xmls/2aba50ba-5c2c-40c7-afaa-dd15c8f9d68c.xml
module OV7670_config_rom(
    input wire clk,
    input wire [7:0] addr,
    output reg [15:0] dout
    );


     always @(posedge clk) begin
    case(addr)

	 0:  dout <= 16'h12_80;
    1:  dout <= 16'hFF_F0;
    2:  dout <= 16'h12_14;
    3:  dout <= 16'h11_80;
    4:  dout <= 16'h0C_00;
    5:  dout <= 16'h3E_00;
    6:  dout <= 16'h04_00;
    7:  dout <= 16'h40_d0;
    8:  dout <= 16'h3a_04;
    9:  dout <= 16'h14_18;
    10: dout <= 16'h4F_B3;
    11: dout <= 16'h50_B3;
    12: dout <= 16'h51_00;
    13: dout <= 16'h52_3d;
    14: dout <= 16'h53_A7;
    15: dout <= 16'h54_E4;
    16: dout <= 16'h58_9E;
    17: dout <= 16'h3D_C0;
    18: dout <= 16'h17_14;
    19: dout <= 16'h18_02;
    20: dout <= 16'h32_80;
    21: dout <= 16'h19_03;
    22: dout <= 16'h1A_7B;
    23: dout <= 16'h03_0A;
    24: dout <= 16'h0F_41;
    25: dout <= 16'h1E_30;
    26: dout <= 16'h33_0B;
    27: dout <= 16'h3C_78;
    28: dout <= 16'h69_00;
    29: dout <= 16'h74_00;
    30: dout <= 16'hB0_84;
    31: dout <= 16'hB1_0c;
    32: dout <= 16'hB2_0e;
    33: dout <= 16'hB3_80;

    34: dout <= 16'h70_3a;
    35: dout <= 16'h71_35;
    36: dout <= 16'h72_11;
    37: dout <= 16'h73_f0;
    38: dout <= 16'ha2_02;

    39: dout <= 16'h7a_20;
    40: dout <= 16'h7b_10;
    41: dout <= 16'h7c_1e;
    42: dout <= 16'h7d_35;
    43: dout <= 16'h7e_5a;
    44: dout <= 16'h7f_69;
    45: dout <= 16'h80_76;
    46: dout <= 16'h81_80;
    47: dout <= 16'h82_88;
    48: dout <= 16'h83_8f;
    49: dout <= 16'h84_96;
    50: dout <= 16'h85_a3;
    51: dout <= 16'h86_af;
    52: dout <= 16'h87_c4;
    53: dout <= 16'h88_d7;
    54: dout <= 16'h89_e8;

    55: dout <= 16'h13_e0;
    56: dout <= 16'h00_00;
    57: dout <= 16'h10_00;
    58: dout <= 16'h0d_40;
    59: dout <= 16'h14_18;
    60: dout <= 16'ha5_05;
    61: dout <= 16'hab_07;
    62: dout <= 16'h24_95;
    63: dout <= 16'h25_33;
    64: dout <= 16'h26_e3;
    65: dout <= 16'h9f_78;
    66: dout <= 16'ha0_68;
    67: dout <= 16'ha1_03;
    68: dout <= 16'ha6_d8;
    69: dout <= 16'ha7_d8;
    70: dout <= 16'ha8_f0;
    71: dout <= 16'ha9_90;
    72: dout <= 16'haa_94;

    73: dout <= 16'h13_e7;




    default: dout <= 16'hFF_FF;
    endcase 
    end
endmodule
module OV7670_config_rom(
    input wire clk,
    input wire [7:0] addr,
    output reg [15:0] dout
    );



     always @(posedge clk) begin
    case(addr)

	 0:  dout <= 16'h12_80;
    1:  dout <= 16'hFF_F0;
    2:  dout <= 16'h12_14;
    3:  dout <= 16'h11_80;
    4:  dout <= 16'h0C_00;
    5:  dout <= 16'h3E_00;
    6:  dout <= 16'h04_00;
    7:  dout <= 16'h40_d0;
    8:  dout <= 16'h3a_04;
    9:  dout <= 16'h14_18;
    10: dout <= 16'h4F_B3;
    11: dout <= 16'h50_B3;
    12: dout <= 16'h51_00;
    13: dout <= 16'h52_3d;
    14: dout <= 16'h53_A7;
    15: dout <= 16'h54_E4;
    16: dout <= 16'h58_9E;
    17: dout <= 16'h3D_C0;
    18: dout <= 16'h17_14;
    19: dout <= 16'h18_02;
    20: dout <= 16'h32_80;
    21: dout <= 16'h19_03;
    22: dout <= 16'h1A_7B;
    23: dout <= 16'h03_0A;
    24: dout <= 16'h0F_41;
    25: dout <= 16'h1E_30;
    26: dout <= 16'h33_0B;
    27: dout <= 16'h3C_78;
    28: dout <= 16'h69_00;
    29: dout <= 16'h74_00;
    30: dout <= 16'hB0_84;
    31: dout <= 16'hB1_0c;
    32: dout <= 16'hB2_0e;
    33: dout <= 16'hB3_80;

    34: dout <= 16'h70_3a;
    35: dout <= 16'h71_35;
    36: dout <= 16'h72_11;
    37: dout <= 16'h73_f0;
    38: dout <= 16'ha2_02;

    39: dout <= 16'h7a_20;
    40: dout <= 16'h7b_10;
    41: dout <= 16'h7c_1e;
    42: dout <= 16'h7d_35;
    43: dout <= 16'h7e_5a;
    44: dout <= 16'h7f_69;
    45: dout <= 16'h80_76;
    46: dout <= 16'h81_80;
    47: dout <= 16'h82_88;
    48: dout <= 16'h83_8f;
    49: dout <= 16'h84_96;
    50: dout <= 16'h85_a3;
    51: dout <= 16'h86_af;
    52: dout <= 16'h87_c4;
    53: dout <= 16'h88_d7;
    54: dout <= 16'h89_e8;

    55: dout <= 16'h13_e0;
    56: dout <= 16'h00_00;
    57: dout <= 16'h10_00;
    58: dout <= 16'h0d_40;
    59: dout <= 16'h14_18;
    60: dout <= 16'ha5_05;
    61: dout <= 16'hab_07;
    62: dout <= 16'h24_95;
    63: dout <= 16'h25_33;
    64: dout <= 16'h26_e3;
    65: dout <= 16'h9f_78;
    66: dout <= 16'ha0_68;
    67: dout <= 16'ha1_03;
    68: dout <= 16'ha6_d8;
    69: dout <= 16'ha7_d8;
    70: dout <= 16'ha8_f0;
    71: dout <= 16'ha9_90;
    72: dout <= 16'haa_94;

    73: dout <= 16'h13_e7;




    default: dout <= 16'hFF_FF;
    endcase 
    end
endmodule