data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v
 line:35: before: "$"
1: b'%Error: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("flipFlopNbit.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, s);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:16: Unsupported or unknown PLI call: $monitor\n $monitor("D is %b, clk is %b, reset_n is %b, D is %b.", D, clk, reset_n, Q);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n   # 20 reset_n = 1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n   # 50 D = 8\'d1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n   # 50 D = 8\'d2;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n   # 50 D = 8\'d3;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n   # 50 D = 8\'d4;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n   # 50 D = 8\'d5;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n   # 50 D = 8\'d6;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n   # 50 D = 8\'d7;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n   # 50 D = 8\'d10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n   # 50 D = 8\'d20;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n   # 50 D = 8\'d200;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n   # 50 reset_n = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n   # 200 $finish;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/127217549/rtl/flipFlopNbit_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = !clk;\n        ^\n%Error: Exiting due to 3 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module flipFlopNbit_tb;


   reg [7:0] D = 7'd0;
   reg 	     clk = 1'b0;
   reg 	     reset_n = 1'b0;
   wire [7:0] Q;

   initial
     begin

	$dumpfile("flipFlopNbit.vcd");

	$dumpvars(0, s);

	$monitor("D is %b, clk is %b, reset_n is %b, D is %b.", D, clk, reset_n, Q);





   # 20 reset_n = 1;

   # 50 D = 8'd1;
   # 50 D = 8'd2;
   # 50 D = 8'd3;
   # 50 D = 8'd4;
   # 50 D = 8'd5;
   # 50 D = 8'd6;
   # 50 D = 8'd7;
   # 50 D = 8'd10;
   # 50 D = 8'd20;
   # 50 D = 8'd200;
   # 50 reset_n = 0;
   # 200 $finish;
	
 	end


	always #5 clk = !clk;

   	flipFlopNbit s (D, clk, reset_n, Q);

endmodule
module flipFlopNbit_tb;



   reg [7:0] D = 7'd0;
   reg 	     clk = 1'b0;
   reg 	     reset_n = 1'b0;
   wire [7:0] Q;

   initial
     begin

	$dumpfile("flipFlopNbit.vcd");

	$dumpvars(0, s);

	$monitor("D is %b, clk is %b, reset_n is %b, D is %b.", D, clk, reset_n, Q);





   # 20 reset_n = 1;

   # 50 D = 8'd1;
   # 50 D = 8'd2;
   # 50 D = 8'd3;
   # 50 D = 8'd4;
   # 50 D = 8'd5;
   # 50 D = 8'd6;
   # 50 D = 8'd7;
   # 50 D = 8'd10;
   # 50 D = 8'd20;
   # 50 D = 8'd200;
   # 50 reset_n = 0;
   # 200 $finish;
	
 	end


	always #5 clk = !clk;

   	flipFlopNbit s (D, clk, reset_n, Q);

endmodule