data/full_repos/permissive/119387855/mips_alu.v
 line:52: before: "'H2"
1: b'%Error: data/full_repos/permissive/119387855/mips_alu.v:50: Unsupported or unknown PLI call: $monitor\n  $monitor("first_data: %b alu_op: %b second_data: %b = result: %b",first_data, alu_op, second_data, result);  \n  ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_alu(zero, result, alu_op, first_data, second_data, shamt);

	output reg zero;
	output reg [31:0] result;

	input [31:0] first_data;
	input [31:0] second_data;
	input [3:0] alu_op;
	input [4:0] shamt;

	always @* begin
		if(alu_op == 4'b1110) begin
			result = ($signed(first_data) < $signed(second_data)) ? 1 : 0 ;
		end else if(alu_op == 4'b1111) begin
			result = (first_data < second_data) ? 1 : 0 ;
		end else begin
			case(alu_op)
				4'b0000 :
					result = first_data & second_data;
				4'b0001 :
					result = first_data | second_data;
				4'b0010 :
					result = !(first_data | second_data);
				4'b0100 :
					result = $signed(first_data) + $signed(second_data);
				4'b0101 :
					result = first_data + second_data;
				4'b0110 :
					result = $signed(first_data) - $signed(second_data);
				4'b0111 :
					result = first_data - second_data;			
				4'b1000 :
					result = first_data <<< shamt;
				4'b1001 :
					result = first_data << shamt;
				4'b1010 :
					result = first_data >>> shamt;
				4'b1011 :
					result = first_data >> shamt;					
				4'b1100 :
					result = {first_data[15:0],{16'b0}};
				4'b0011 :
					result = first_data;
			endcase
		end
		zero = (first_data == second_data) ? 0 : 1 ;
	end
	
	initial begin
		$monitor("first_data: %b alu_op: %b second_data: %b = result: %b",first_data, alu_op, second_data, result);		
	end
endmodule
module mips_alu(zero, result, alu_op, first_data, second_data, shamt);


	output reg zero;
	output reg [31:0] result;

	input [31:0] first_data;
	input [31:0] second_data;
	input [3:0] alu_op;
	input [4:0] shamt;

	always @* begin
		if(alu_op == 4'b1110) begin
			result = ($signed(first_data) < $signed(second_data)) ? 1 : 0 ;
		end else if(alu_op == 4'b1111) begin
			result = (first_data < second_data) ? 1 : 0 ;
		end else begin
			case(alu_op)
				4'b0000 :
					result = first_data & second_data;
				4'b0001 :
					result = first_data | second_data;
				4'b0010 :
					result = !(first_data | second_data);
				4'b0100 :
					result = $signed(first_data) + $signed(second_data);
				4'b0101 :
					result = first_data + second_data;
				4'b0110 :
					result = $signed(first_data) - $signed(second_data);
				4'b0111 :
					result = first_data - second_data;			
				4'b1000 :
					result = first_data <<< shamt;
				4'b1001 :
					result = first_data << shamt;
				4'b1010 :
					result = first_data >>> shamt;
				4'b1011 :
					result = first_data >> shamt;					
				4'b1100 :
					result = {first_data[15:0],{16'b0}};
				4'b0011 :
					result = first_data;
			endcase
		end
		zero = (first_data == second_data) ? 0 : 1 ;
	end
	
	initial begin
		$monitor("first_data: %b alu_op: %b second_data: %b = result: %b",first_data, alu_op, second_data, result);		
	end
endmodule