data/full_repos/permissive/146246005/JK Flip Flop/TB_JKFF.v
 line:45: before: "$"
1: b'%Error: Cannot find file containing module: Flip\n        ... Looked in:\n             data/full_repos/permissive/146246005/JK/Flip\n             data/full_repos/permissive/146246005/JK/Flip.v\n             data/full_repos/permissive/146246005/JK/Flip.sv\n             Flip\n             Flip.v\n             Flip.sv\n             obj_dir/Flip\n             obj_dir/Flip.v\n             obj_dir/Flip.sv\n%Error: Cannot find file containing module: Flop,data/full_repos/permissive/146246005\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/JK\n%Error: Cannot find file containing module: Flop/TB_JKFF.v\n%Error: Exiting due to 4 error(s)\n'
module TB_JKFF();
    reg SD_N, CP, J, K_N, RD_N;
    wire Q, Q_N;

    JKFF UUT(Q, Q_N, SD_N, CP, J, K_N, RD_N);

    always #(`period*0.5) CP=~CP;



    initial begin
      $write ("This shows the given inputs");
      $display (" that will be a part of all tests in this lab.");
      $monitor ("%d ns  J = %b, K_N= %b, SD_N = %b, CP = %b, RD_N = %b   Q = %b  Q_N = %b",$time,J,K_N,SD_N,CP,RD_N,Q,Q_N);
    end

    initial begin

      $dumpfile("dump.vcd");
      $dumpvars;

     $display("Async Set Test");
     J=1 ; K_N=1 ; SD_N=0 ; CP=1 ; RD_N=1;
     #28 $display("Q = %b  Q_N = %b", Q, Q_N);

     #(`period/2) $display("Async Reset Test");
     J=1 ; K_N=1 ; SD_N=1 ; RD_N=0;
     #28 $display("Q = %b  Q_N = %b", Q, Q_N);


     #`period $display("Indeterminate Test");
     J=1 ; K_N=1 ; SD_N=0 ; RD_N=0;
	 #28 $display("Q = %b  Q_N = %b", Q, Q_N);


     #`period $display("Load 0 Test");
     J=0 ; K_N=0 ; SD_N=1 ; RD_N=1;
     #28 $display("Q = %b  Q_N = %b", Q, Q_N);

     #`period $display("Load 1 Test");
     J=1 ; K_N=1 ; SD_N=1  ; RD_N=1;
      $strobe("q = %b  q_n = %b", Q, Q_N);
     #29 $display("Q = %b  Q_N = %b", Q, Q_N);

     #`period $display("Hold");
     J=0; K_N=1; SD_N=1; RD_N=1;
     #28 $display("Q = %b  Q_N = %b", Q, Q_N);

     #`period $display("Toggle");
     J=1; K_N=0; SD_N=1; RD_N=1;
 	 #28 $display("Q = %b  Q_N = %b", Q, Q_N);

     #`period $display("Hold");
     J=1; K_N=1; SD_N=1; RD_N=1;
     #28 $display("Q = %b  Q_N = %b", Q, Q_N);

     #100 $finish;

    end
endmodule
module TB_JKFF();

    reg SD_N, CP, J, K_N, RD_N;
    wire Q, Q_N;

    JKFF UUT(Q, Q_N, SD_N, CP, J, K_N, RD_N);

    always #(`period*0.5) CP=~CP;



    initial begin
      $write ("This shows the given inputs");
      $display (" that will be a part of all tests in this lab.");
      $monitor ("%d ns  J = %b, K_N= %b, SD_N = %b, CP = %b, RD_N = %b   Q = %b  Q_N = %b",$time,J,K_N,SD_N,CP,RD_N,Q,Q_N);
    end

    initial begin

      $dumpfile("dump.vcd");
      $dumpvars;

     $display("Async Set Test");
     J=1 ; K_N=1 ; SD_N=0 ; CP=1 ; RD_N=1;
     #28 $display("Q = %b  Q_N = %b", Q, Q_N);

     #(`period/2) $display("Async Reset Test");
     J=1 ; K_N=1 ; SD_N=1 ; RD_N=0;
     #28 $display("Q = %b  Q_N = %b", Q, Q_N);


     #`period $display("Indeterminate Test");
     J=1 ; K_N=1 ; SD_N=0 ; RD_N=0;
	 #28 $display("Q = %b  Q_N = %b", Q, Q_N);


     #`period $display("Load 0 Test");
     J=0 ; K_N=0 ; SD_N=1 ; RD_N=1;
     #28 $display("Q = %b  Q_N = %b", Q, Q_N);

     #`period $display("Load 1 Test");
     J=1 ; K_N=1 ; SD_N=1  ; RD_N=1;
      $strobe("q = %b  q_n = %b", Q, Q_N);
     #29 $display("Q = %b  Q_N = %b", Q, Q_N);

     #`period $display("Hold");
     J=0; K_N=1; SD_N=1; RD_N=1;
     #28 $display("Q = %b  Q_N = %b", Q, Q_N);

     #`period $display("Toggle");
     J=1; K_N=0; SD_N=1; RD_N=1;
 	 #28 $display("Q = %b  Q_N = %b", Q, Q_N);

     #`period $display("Hold");
     J=1; K_N=1; SD_N=1; RD_N=1;
     #28 $display("Q = %b  Q_N = %b", Q, Q_N);

     #100 $finish;

    end
endmodule