data/full_repos/permissive/114421971/bram_rom/top.v
1: b"%Error: data/full_repos/permissive/114421971/bram_rom/top.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n                                      ^~\n%Error: data/full_repos/permissive/114421971/bram_rom/top.v:27: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n        ^~\n%Error: Exiting due to 2 error(s)\n"
module roi(input clk, input [255:0] din, output [255:0] dout);
    ram_RAMB18E1 #(.LOC("XXX"))
            ram_RAMB18E1(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
endmodule
module roi(input clk, input [255:0] din, output [255:0] dout);

    ram_RAMB18E1 #(.LOC("XXX"))
            ram_RAMB18E1(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
endmodule