data/full_repos/permissive/183843067/passwd.v
1: b'%Warning-WIDTH: data/full_repos/permissive/183843067/passwd.v:195: Input port connection \'K\' expects 10 bits on the pin connection, but pin connection\'s VARREF \'SYS_K\' generates 1 bits.\n                                                                 : ... In instance Top\nPasswd PASS(.CLK(SYS_CLK),.del(SYS_DEL),.K(SYS_K),.lock(SYS_LOCK),.Data(USER_DATA));\n                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Passwd(
        input CLK,
        input del,
        input [9:0] K,
        output reg lock,
        output reg [15:0] Data
);
integer count=0;
reg [15:0] passwd=16'b1001_1001_0111_0000;
reg [15:0] root=16'b0000_0001_0010_0011;
initial
    begin
      Data<=0;
      lock<=1;
    end
always @ (posedge CLK)
    begin
      if (count==4)
        begin
          if (Data==passwd)
            begin
                lock<=0;
            end
          else
            if (Data==root)
                begin
                  lock<=0;
                end
            else
                begin
                  lock<=1;
                  Data<=0;
                end
        count<=0;
        Data<=0;
        end
    else
        begin
            if (del==1)
                begin
                  Data<=Data>>4;
                  count=count-1;
                end
          if (K!=0)
            begin
              case (K)
                10'b100_000_000_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=0;
                      count<=count+1;
                    end
                10'b010_000_000_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=1;
                      count=count+1;
                    end
                10'b001_000_000_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=2;
                      count=count+1;
                    end
                10'b000_100_000_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=3;
                      count=count+1;
                    end
                10'b000_010_000_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=4;
                      count=count+1;
                    end
                10'b000_001_000_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=5;
                      count=count+1;
                    end
                10'b000_000_100_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=6;
                      count=count+1;
                    end
                10'b000_000_010_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=7;
                      count=count+1;
                    end
                10'b000_000_001_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=8;
                      count=count+1;
                    end
                10'b000_000_000_1:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=9;
                      count=count+1;
                    end
              endcase
            end
        end
    end
endmodule
module Passwd(
        input CLK,
        input del,
        input [9:0] K,
        output reg lock,
        output reg [15:0] Data
);

integer count=0;
reg [15:0] passwd=16'b1001_1001_0111_0000;
reg [15:0] root=16'b0000_0001_0010_0011;
initial
    begin
      Data<=0;
      lock<=1;
    end
always @ (posedge CLK)
    begin
      if (count==4)
        begin
          if (Data==passwd)
            begin
                lock<=0;
            end
          else
            if (Data==root)
                begin
                  lock<=0;
                end
            else
                begin
                  lock<=1;
                  Data<=0;
                end
        count<=0;
        Data<=0;
        end
    else
        begin
            if (del==1)
                begin
                  Data<=Data>>4;
                  count=count-1;
                end
          if (K!=0)
            begin
              case (K)
                10'b100_000_000_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=0;
                      count<=count+1;
                    end
                10'b010_000_000_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=1;
                      count=count+1;
                    end
                10'b001_000_000_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=2;
                      count=count+1;
                    end
                10'b000_100_000_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=3;
                      count=count+1;
                    end
                10'b000_010_000_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=4;
                      count=count+1;
                    end
                10'b000_001_000_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=5;
                      count=count+1;
                    end
                10'b000_000_100_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=6;
                      count=count+1;
                    end
                10'b000_000_010_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=7;
                      count=count+1;
                    end
                10'b000_000_001_0:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=8;
                      count=count+1;
                    end
                10'b000_000_000_1:
                    begin
                      Data<=Data<<4;
                      Data[3:0]<=9;
                      count=count+1;
                    end
              endcase
            end
        end
    end
endmodule