data/full_repos/permissive/194781874/sine_wave.v
1: b'%Warning-WIDTH: data/full_repos/permissive/194781874/sine_wave.v:18: Operator SUB expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'PHASE\' generates 12 bits.\n                                                                   : ... In instance sine_wave\n    assign ANGLE = (PHASE <= 1024) ? PHASE * 4 * 333 / 106 : (PHASE <= 2048) ? (2048 - PHASE) * 4 * 333 / 106 : (PHASE <= 3072) ? (PHASE - 2048) * 4 * 333 / 106 : (4096 - PHASE) * 4 * 333 / 106;\n                                                                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/194781874/sine_wave.v:18: Operator SUB expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'PHASE\' generates 12 bits.\n                                                                   : ... In instance sine_wave\n    assign ANGLE = (PHASE <= 1024) ? PHASE * 4 * 333 / 106 : (PHASE <= 2048) ? (2048 - PHASE) * 4 * 333 / 106 : (PHASE <= 3072) ? (PHASE - 2048) * 4 * 333 / 106 : (4096 - PHASE) * 4 * 333 / 106;\n                                                                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/194781874/sine_wave.v:18: Operator SUB expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'PHASE\' generates 12 bits.\n                                                                   : ... In instance sine_wave\n    assign ANGLE = (PHASE <= 1024) ? PHASE * 4 * 333 / 106 : (PHASE <= 2048) ? (2048 - PHASE) * 4 * 333 / 106 : (PHASE <= 3072) ? (PHASE - 2048) * 4 * 333 / 106 : (4096 - PHASE) * 4 * 333 / 106;\n                                                                                                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/194781874/sine_wave.v:19: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 16 bits.\n                                                                   : ... In instance sine_wave\n    assign DATA = (FORM == 2\'b00) ? ((PHASE_REG < 1024) ? 2046 + SIN * 2 : (PHASE_REG < 2048) ? 2049 - SIN * 2 : (PHASE_REG < 3072) ? 2049 - SIN * 2 : 2046 + SIN * 2) :\n                ^\n%Error: data/full_repos/permissive/194781874/sine_wave.v:29: Cannot find file containing module: \'cordic_core\'\n    cordic_core cordic_ip_core(.aclk(CORDIC_CLK), .s_axis_phase_tvalid(IN_VALID), .s_axis_phase_tdata(ANGLE), .m_axis_dout_tdata(OUT));\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194781874,data/full_repos/permissive/194781874/cordic_core\n             data/full_repos/permissive/194781874,data/full_repos/permissive/194781874/cordic_core.v\n             data/full_repos/permissive/194781874,data/full_repos/permissive/194781874/cordic_core.sv\n             cordic_core\n             cordic_core.v\n             cordic_core.sv\n             obj_dir/cordic_core\n             obj_dir/cordic_core.v\n             obj_dir/cordic_core.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module sine_wave(
    input CORDIC_CLK,
    input [11:0] PHASE,
    input [1:0] FORM,
    output [11:0] DATA
    );
    
    reg [3:0] COUNT = 0;
    reg [11:0] PHASE_REG;
    reg IN_VALID = 1;
    wire [31:0] OUT;
    wire [15:0] ANGLE;
    wire [15:0] SIN;
    
    assign SIN = OUT[15:0];
    assign ANGLE = (PHASE <= 1024) ? PHASE * 4 * 333 / 106 : (PHASE <= 2048) ? (2048 - PHASE) * 4 * 333 / 106 : (PHASE <= 3072) ? (PHASE - 2048) * 4 * 333 / 106 : (4096 - PHASE) * 4 * 333 / 106;
    assign DATA = (FORM == 2'b00) ? ((PHASE_REG < 1024) ? 2046 + SIN * 2 : (PHASE_REG < 2048) ? 2049 - SIN * 2 : (PHASE_REG < 3072) ? 2049 - SIN * 2 : 2046 + SIN * 2) :
                  (FORM == 2'b01) ? ((PHASE_REG < 1024) ? 2046 + SIN * 2 : (PHASE_REG < 2048) ? 2048 : (PHASE_REG < 3072) ? 2048 : 2046 + SIN * 2) :
                  (FORM == 2'b10) ? ((PHASE_REG < 1024) ? 2049 - SIN * 2 : (PHASE_REG < 2048) ? 2046 + SIN * 2 : (PHASE_REG < 3072) ? 2046 + SIN * 2 : 2049 - SIN * 2) : 
                  ((PHASE_REG < 1024) ? 2046 + SIN * 2 : (PHASE_REG < 2048) ? 2046 + SIN * 2 : (PHASE_REG < 3072) ? 2046 + SIN * 2 : 2046 + SIN * 2);
    
    always @ (posedge CORDIC_CLK) begin
        COUNT = COUNT + 1;
        PHASE_REG = (COUNT == 4'b0000) ? PHASE : PHASE_REG;
    end
        
    cordic_core cordic_ip_core(.aclk(CORDIC_CLK), .s_axis_phase_tvalid(IN_VALID), .s_axis_phase_tdata(ANGLE), .m_axis_dout_tdata(OUT));
endmodule
module sine_wave(
    input CORDIC_CLK,
    input [11:0] PHASE,
    input [1:0] FORM,
    output [11:0] DATA
    );

    
    reg [3:0] COUNT = 0;
    reg [11:0] PHASE_REG;
    reg IN_VALID = 1;
    wire [31:0] OUT;
    wire [15:0] ANGLE;
    wire [15:0] SIN;
    
    assign SIN = OUT[15:0];
    assign ANGLE = (PHASE <= 1024) ? PHASE * 4 * 333 / 106 : (PHASE <= 2048) ? (2048 - PHASE) * 4 * 333 / 106 : (PHASE <= 3072) ? (PHASE - 2048) * 4 * 333 / 106 : (4096 - PHASE) * 4 * 333 / 106;
    assign DATA = (FORM == 2'b00) ? ((PHASE_REG < 1024) ? 2046 + SIN * 2 : (PHASE_REG < 2048) ? 2049 - SIN * 2 : (PHASE_REG < 3072) ? 2049 - SIN * 2 : 2046 + SIN * 2) :
                  (FORM == 2'b01) ? ((PHASE_REG < 1024) ? 2046 + SIN * 2 : (PHASE_REG < 2048) ? 2048 : (PHASE_REG < 3072) ? 2048 : 2046 + SIN * 2) :
                  (FORM == 2'b10) ? ((PHASE_REG < 1024) ? 2049 - SIN * 2 : (PHASE_REG < 2048) ? 2046 + SIN * 2 : (PHASE_REG < 3072) ? 2046 + SIN * 2 : 2049 - SIN * 2) : 
                  ((PHASE_REG < 1024) ? 2046 + SIN * 2 : (PHASE_REG < 2048) ? 2046 + SIN * 2 : (PHASE_REG < 3072) ? 2046 + SIN * 2 : 2046 + SIN * 2);
    
    always @ (posedge CORDIC_CLK) begin
        COUNT = COUNT + 1;
        PHASE_REG = (COUNT == 4'b0000) ? PHASE : PHASE_REG;
    end
        
    cordic_core cordic_ip_core(.aclk(CORDIC_CLK), .s_axis_phase_tvalid(IN_VALID), .s_axis_phase_tdata(ANGLE), .m_axis_dout_tdata(OUT));
endmodule