data/full_repos/permissive/143278/ivltests/vhdl_wait.v
1: b"%Error: data/full_repos/permissive/143278/ivltests/vhdl_wait.v:24: Cannot find file containing module: 'vhdl_wait'\nvhdl_wait dut(a, b);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_wait\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_wait.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_wait.sv\n             vhdl_wait\n             vhdl_wait.v\n             vhdl_wait.sv\n             obj_dir/vhdl_wait\n             obj_dir/vhdl_wait.v\n             obj_dir/vhdl_wait.sv\n%Error: Exiting due to 1 error(s)\n"
module vhdl_wait_test;
logic [1:0] a, b;
vhdl_wait dut(a, b);

always @(posedge b[0]) begin
    $display("wait 1 acknowledged");

    a[1] = 1'b0;
end

always @(posedge b[1]) begin
    $display("wait 2 acknowledged");
end

initial begin

    a = 2'b00;
end

endmodule
module vhdl_wait_test;

logic [1:0] a, b;
vhdl_wait dut(a, b);

always @(posedge b[0]) begin
    $display("wait 1 acknowledged");

    a[1] = 1'b0;
end

always @(posedge b[1]) begin
    $display("wait 2 acknowledged");
end

initial begin

    a = 2'b00;
end

endmodule