data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_top.sv
1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_top.sv:15: Cannot find file containing module: 'ffd'\nffd #(16) speed_fd(CLK, RESET, WE & (A == 3'd4), WD[15:0], bit_time);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/ffd\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/ffd.v\n             data/full_repos/permissive/10379745/hw_de0/hard/uart,data/full_repos/permissive/10379745/ffd.sv\n             ffd\n             ffd.v\n             ffd.sv\n             obj_dir/ffd\n             obj_dir/ffd.v\n             obj_dir/ffd.sv\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_top.sv:16: Cannot find file containing module: 'ffd'\nffd  #(2)   par_fd(CLK, RESET, WE & (A == 3'd6),  WD[1:0], {par_odd, par_en});   \n^~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_top.sv:18: Cannot find file containing module: 'buffered_rx'\nbuffered_rx #(5, 434) buffered_rx ( .CLK        ( CLK        ),\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_top.sv:30: Cannot find file containing module: 'buffered_tx'\nbuffered_tx #(5, 434) buffered_tx ( .CLK        ( CLK        ),\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/uart/uart_top.sv:41: Cannot find file containing module: 'mux4'\nmux4 #(32) omux( A[2:1],\n^~~~\n%Error: Exiting due to 5 error(s)\n"
module uart_top ( input         CLK,
                  input         RESET,
                  input         WE,
                  input         RE,
                  input   [2:0] A,
                  input  [31:0] WD,
                  output [31:0] RD,
                  output        UART_TX,
                  input         UART_RX  );

logic [31:0] rx_rd, tx_rd;
logic [15:0] bit_time;
logic        par_en, par_odd;

ffd #(16) speed_fd(CLK, RESET, WE & (A == 3'd4), WD[15:0], bit_time);
ffd  #(2)   par_fd(CLK, RESET, WE & (A == 3'd6),  WD[1:0], {par_odd, par_en});   

buffered_rx #(5, 434) buffered_rx ( .CLK        ( CLK        ),
                                    .RESET      ( RESET      ),
                                    .BIT_TIME   ( bit_time   ),
                                    .PARITY_EN  ( par_en     ),
                                    .PARITY_ODD ( par_odd    ),
                                    .RE         ( RE & ~A[2] & A[1]  ),
                                    .WE         ( WE & ~A[2] & A[1]  ),
                                    .A          ( A[0]       ),
                                    .RD         ( rx_rd      ),
                                    .UART_RX    ( UART_RX    ) );


buffered_tx #(5, 434) buffered_tx ( .CLK        ( CLK        ),
                                    .RESET      ( RESET      ),
                                    .BIT_TIME   ( bit_time   ),
                                    .PARITY_EN  ( par_en     ),
                                    .PARITY_ODD ( par_odd    ),
                                    .WE         ( WE & ~A[2] & ~A[1] ),
                                    .A          ( A[0]       ),
                                    .WD         ( WD         ),
                                    .RD         ( tx_rd      ),
                                    .UART_TX    ( UART_TX    ) );

mux4 #(32) omux( A[2:1],
                 tx_rd,
                 rx_rd,
                 {16'd0, bit_time},
                 {30'd0, par_odd, par_en},
                 RD );

endmodule
module uart_top ( input         CLK,
                  input         RESET,
                  input         WE,
                  input         RE,
                  input   [2:0] A,
                  input  [31:0] WD,
                  output [31:0] RD,
                  output        UART_TX,
                  input         UART_RX  );


logic [31:0] rx_rd, tx_rd;
logic [15:0] bit_time;
logic        par_en, par_odd;

ffd #(16) speed_fd(CLK, RESET, WE & (A == 3'd4), WD[15:0], bit_time);
ffd  #(2)   par_fd(CLK, RESET, WE & (A == 3'd6),  WD[1:0], {par_odd, par_en});   

buffered_rx #(5, 434) buffered_rx ( .CLK        ( CLK        ),
                                    .RESET      ( RESET      ),
                                    .BIT_TIME   ( bit_time   ),
                                    .PARITY_EN  ( par_en     ),
                                    .PARITY_ODD ( par_odd    ),
                                    .RE         ( RE & ~A[2] & A[1]  ),
                                    .WE         ( WE & ~A[2] & A[1]  ),
                                    .A          ( A[0]       ),
                                    .RD         ( rx_rd      ),
                                    .UART_RX    ( UART_RX    ) );


buffered_tx #(5, 434) buffered_tx ( .CLK        ( CLK        ),
                                    .RESET      ( RESET      ),
                                    .BIT_TIME   ( bit_time   ),
                                    .PARITY_EN  ( par_en     ),
                                    .PARITY_ODD ( par_odd    ),
                                    .WE         ( WE & ~A[2] & ~A[1] ),
                                    .A          ( A[0]       ),
                                    .WD         ( WD         ),
                                    .RD         ( tx_rd      ),
                                    .UART_TX    ( UART_TX    ) );

mux4 #(32) omux( A[2:1],
                 tx_rd,
                 rx_rd,
                 {16'd0, bit_time},
                 {30'd0, par_odd, par_en},
                 RD );

endmodule