data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v
1: b"%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:170: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n  output [DATA_WIDTH_R-1:0] do,\n                            ^~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:206: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  output [DATA_WIDTH_R-1:0] do,\n                            ^~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:225: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  output [3:0]do\n              ^~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:759: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  input [3:0] do,\n              ^~\n%Error: data/full_repos/permissive/200142067/bin/synth/yosys-abc/share/yosys/anlogic/eagle_bb.v:893: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  output [7:0] do,\n               ^~\n%Error: Exiting due to 5 error(s)\n"
module EG_LOGIC_FIFO(
  input rst,
  input [DATA_WIDTH_W-1:0] di,
  output [DATA_WIDTH_R-1:0] do,
  input clkw,
  input we,
  input clkr,
  input re,
  input ore,
  input [2:0] csw,
  input [2:0] csr,
  output empty_flag,
  output aempty_flag,
  output full_flag,
  output afull_flag
);
  parameter DATA_WIDTH_W = 9;
  parameter DATA_WIDTH_R = DATA_WIDTH_W;
  parameter DATA_DEPTH_W = 1024;
  parameter DATA_DEPTH_R = DATA_WIDTH_W * DATA_DEPTH_W / DATA_WIDTH_R;
  parameter MODE = "FIFO8K";
  parameter REGMODE_W = "NOREG";
  parameter REGMODE_R = "NOREG";
  parameter E = 0;
  parameter AE = 6;
  parameter AF = DATA_DEPTH_W - 6;
  parameter F = DATA_DEPTH_W;
  parameter GSR = "DISABLE";
  parameter RESETMODE = "ASYNC";
  parameter ASYNC_RESET_RELEASE = "SYNC";
  parameter ENDIAN = "LITTLE";
endmodule
module EG_LOGIC_FIFO(
  input rst,
  input [DATA_WIDTH_W-1:0] di,
  output [DATA_WIDTH_R-1:0] do,
  input clkw,
  input we,
  input clkr,
  input re,
  input ore,
  input [2:0] csw,
  input [2:0] csr,
  output empty_flag,
  output aempty_flag,
  output full_flag,
  output afull_flag
);

  parameter DATA_WIDTH_W = 9;
  parameter DATA_WIDTH_R = DATA_WIDTH_W;
  parameter DATA_DEPTH_W = 1024;
  parameter DATA_DEPTH_R = DATA_WIDTH_W * DATA_DEPTH_W / DATA_WIDTH_R;
  parameter MODE = "FIFO8K";
  parameter REGMODE_W = "NOREG";
  parameter REGMODE_R = "NOREG";
  parameter E = 0;
  parameter AE = 6;
  parameter AF = DATA_DEPTH_W - 6;
  parameter F = DATA_DEPTH_W;
  parameter GSR = "DISABLE";
  parameter RESETMODE = "ASYNC";
  parameter ASYNC_RESET_RELEASE = "SYNC";
  parameter ENDIAN = "LITTLE";
endmodule