data/full_repos/permissive/172908596/Data Memory/dm.v
1: b'%Error: Cannot find file containing module: Memory,data/full_repos/permissive/172908596\n        ... Looked in:\n             data/full_repos/permissive/172908596/Data/Memory,data/full_repos/permissive/172908596\n             data/full_repos/permissive/172908596/Data/Memory,data/full_repos/permissive/172908596.v\n             data/full_repos/permissive/172908596/Data/Memory,data/full_repos/permissive/172908596.sv\n             Memory,data/full_repos/permissive/172908596\n             Memory,data/full_repos/permissive/172908596.v\n             Memory,data/full_repos/permissive/172908596.sv\n             obj_dir/Memory,data/full_repos/permissive/172908596\n             obj_dir/Memory,data/full_repos/permissive/172908596.v\n             obj_dir/Memory,data/full_repos/permissive/172908596.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/172908596/Data\n%Error: Cannot find file containing module: Memory/dm.v\n%Error: Exiting due to 3 error(s)\n'
module DM#(parameter addr_width = 3,data_width = 64)
(
    input wire clk,
    input wire w,
    input wire [addr_width-1:0] addr,
    input wire [data_width-1:0] din,
    output reg [data_width-1:0] dout
);

reg [data_width-1:0] data_memory[2**addr_width-1:0];

always @(posedge clk)
begin
    if (w == 1) 
	begin
        data_memory[addr] = din;
	end
dout = data_memory[addr];

end

endmodule
module DM#(parameter addr_width = 3,data_width = 64)
(
    input wire clk,
    input wire w,
    input wire [addr_width-1:0] addr,
    input wire [data_width-1:0] din,
    output reg [data_width-1:0] dout
);


reg [data_width-1:0] data_memory[2**addr_width-1:0];

always @(posedge clk)
begin
    if (w == 1) 
	begin
        data_memory[addr] = din;
	end
dout = data_memory[addr];

end

endmodule