data/full_repos/permissive/187199324/stannel/RamDumper.v
1: b'%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:4: Define or directive not defined: \'`ADDRESS_BITS\'\n  parameter addrBits = `ADDRESS_BITS,\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:4: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  parameter addrBits = `ADDRESS_BITS,\n                                    ^\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:5: Define or directive not defined: \'`DATA_BITS\'\n  parameter dataBits = `DATA_BITS,\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:5: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  parameter dataBits = `DATA_BITS,\n                                 ^\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:6: Define or directive not defined: \'`ICE_STICK_CLOCK_RATE\'\n  parameter clockRate = `ICE_STICK_CLOCK_RATE\n                        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:7: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n) (\n^\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n  input  wire                reset,\n  ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n  input  wire                enabled,\n  ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n  input  wire [dataBits-1:0] dataOut,\n  ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:12: syntax error, unexpected output, expecting IDENTIFIER or do or final\n  output wire [dataBits-1:0] dataIn,\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n  output wire [addrBits-1:0] address,\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n  output wire                readWriteMode,\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n  input  wire                txReady,\n  ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n  output wire                txSignalStart,\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:17: syntax error, unexpected output, expecting IDENTIFIER or do or final\n  output wire [7:0]          txData,\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:18: syntax error, unexpected output, expecting IDENTIFIER or do or final\n  output wire                finished\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:33: syntax error, unexpected assign\n  assign address = rAddress;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:37: syntax error, unexpected assign\n  assign txSignalStart = wTxSignalStart;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:44: syntax error, unexpected assign\n  assign finished = wFinished;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:47: syntax error, unexpected assign\n  assign readWriteMode = wReadWriteMode;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:70: Define or directive not defined: \'`RAM_READ\'\n    wReadWriteMode = `RAM_READ;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:90: Define or directive not defined: \'`RAM_WRITE\'\n        wReadWriteMode = `RAM_WRITE;\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/RamDumper.v:95: Define or directive not defined: \'`RAM_WRITE\'\n        wReadWriteMode = `RAM_WRITE;\n                         ^~~~~~~~~~\n%Error: Exiting due to 24 error(s)\n'
module RamDumper #(
  parameter addrBits = `ADDRESS_BITS,
  parameter dataBits = `DATA_BITS,
  parameter clockRate = `ICE_STICK_CLOCK_RATE
) (
  input  wire                clk,
  input  wire                reset,
  input  wire                enabled,
  input  wire [dataBits-1:0] dataOut,
  output wire [dataBits-1:0] dataIn,
  output wire [addrBits-1:0] address,
  output wire                readWriteMode,
  input  wire                txReady,
  output wire                txSignalStart,
  output wire [7:0]          txData,
  output wire                finished
);

  localparam PREPARE_WRITE_HIGH = 3'd0;
  localparam WRITE_HIGH         = 3'd1;
  localparam PREPARE_WRITE_LOW  = 3'd2;
  localparam WRITE_LOW          = 3'd3;
  localparam ZERO_PREP          = 3'd4;
  localparam ZERO1              = 3'd5;
  localparam ZERO2              = 3'd6;

  reg [2:0] rState;
  reg [2:0] wNextState;

  reg [addrBits-1:0] rAddress;
  assign address = rAddress;
  wire wIsLastAddress = &rAddress;

  reg wTxSignalStart;
  assign txSignalStart = wTxSignalStart;

  assign txData = rState == WRITE_HIGH ? dataOut[15:8] : dataOut[7:0];

  reg wAddressCounterEnabled;

  reg wFinished;
  assign finished = wFinished;

  reg wReadWriteMode;
  assign readWriteMode = wReadWriteMode;
  assign dataIn = 0;

  always @(posedge clk)
  begin
    if (!reset || !enabled)
    begin
      rAddress <= 0;
      rState   <= PREPARE_WRITE_HIGH;
    end
    else
    begin
      rState <= wNextState;
      if (wAddressCounterEnabled)
        rAddress <= rAddress + 1;
    end
  end

  always @(*)
  begin
    wAddressCounterEnabled = 0;
    wTxSignalStart = 0;
    wFinished = 0;
    wReadWriteMode = `RAM_READ;
    case (rState)
      PREPARE_WRITE_HIGH:
        wNextState = txReady && enabled ? WRITE_HIGH : PREPARE_WRITE_HIGH;
      WRITE_HIGH:
      begin
        wTxSignalStart = 1;
        wNextState = PREPARE_WRITE_LOW;
      end
      PREPARE_WRITE_LOW:
        wNextState = txReady ? WRITE_LOW : PREPARE_WRITE_LOW;
      WRITE_LOW:
      begin
        wTxSignalStart = 1;
        wNextState = ZERO1;
      end
      ZERO_PREP:
        wNextState = txReady ? ZERO1 : ZERO_PREP;
      ZERO1:
      begin
        wReadWriteMode = `RAM_WRITE;
        wNextState = ZERO2;
      end
      ZERO2:
      begin
        wReadWriteMode = `RAM_WRITE;
        wNextState = PREPARE_WRITE_HIGH;
        wAddressCounterEnabled = 1;
        wFinished = wIsLastAddress;
      end
      default:
        wNextState = PREPARE_WRITE_HIGH;
    endcase
  end

endmodule
module RamDumper #(
  parameter addrBits = `ADDRESS_BITS,
  parameter dataBits = `DATA_BITS,
  parameter clockRate = `ICE_STICK_CLOCK_RATE
) (
  input  wire                clk,
  input  wire                reset,
  input  wire                enabled,
  input  wire [dataBits-1:0] dataOut,
  output wire [dataBits-1:0] dataIn,
  output wire [addrBits-1:0] address,
  output wire                readWriteMode,
  input  wire                txReady,
  output wire                txSignalStart,
  output wire [7:0]          txData,
  output wire                finished
);


  localparam PREPARE_WRITE_HIGH = 3'd0;
  localparam WRITE_HIGH         = 3'd1;
  localparam PREPARE_WRITE_LOW  = 3'd2;
  localparam WRITE_LOW          = 3'd3;
  localparam ZERO_PREP          = 3'd4;
  localparam ZERO1              = 3'd5;
  localparam ZERO2              = 3'd6;

  reg [2:0] rState;
  reg [2:0] wNextState;

  reg [addrBits-1:0] rAddress;
  assign address = rAddress;
  wire wIsLastAddress = &rAddress;

  reg wTxSignalStart;
  assign txSignalStart = wTxSignalStart;

  assign txData = rState == WRITE_HIGH ? dataOut[15:8] : dataOut[7:0];

  reg wAddressCounterEnabled;

  reg wFinished;
  assign finished = wFinished;

  reg wReadWriteMode;
  assign readWriteMode = wReadWriteMode;
  assign dataIn = 0;

  always @(posedge clk)
  begin
    if (!reset || !enabled)
    begin
      rAddress <= 0;
      rState   <= PREPARE_WRITE_HIGH;
    end
    else
    begin
      rState <= wNextState;
      if (wAddressCounterEnabled)
        rAddress <= rAddress + 1;
    end
  end

  always @(*)
  begin
    wAddressCounterEnabled = 0;
    wTxSignalStart = 0;
    wFinished = 0;
    wReadWriteMode = `RAM_READ;
    case (rState)
      PREPARE_WRITE_HIGH:
        wNextState = txReady && enabled ? WRITE_HIGH : PREPARE_WRITE_HIGH;
      WRITE_HIGH:
      begin
        wTxSignalStart = 1;
        wNextState = PREPARE_WRITE_LOW;
      end
      PREPARE_WRITE_LOW:
        wNextState = txReady ? WRITE_LOW : PREPARE_WRITE_LOW;
      WRITE_LOW:
      begin
        wTxSignalStart = 1;
        wNextState = ZERO1;
      end
      ZERO_PREP:
        wNextState = txReady ? ZERO1 : ZERO_PREP;
      ZERO1:
      begin
        wReadWriteMode = `RAM_WRITE;
        wNextState = ZERO2;
      end
      ZERO2:
      begin
        wReadWriteMode = `RAM_WRITE;
        wNextState = PREPARE_WRITE_HIGH;
        wAddressCounterEnabled = 1;
        wFinished = wIsLastAddress;
      end
      default:
        wNextState = PREPARE_WRITE_HIGH;
    endcase
  end

endmodule