data/full_repos/permissive/143278/ivltests/pr812.v
 line:47: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr812.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("tp = %f, tp2 = %f", tp, tp2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top();
	parameter tp = 'd1;

	reg a;
	wire b;

	bot b1(b, a);

	initial begin
		a = 0;
		$display("tp = %d in top", tp);
	end
endmodule
module top();

	parameter tp = 'd1;

	reg a;
	wire b;

	bot b1(b, a);

	initial begin
		a = 0;
		$display("tp = %d in top", tp);
	end
endmodule