data/full_repos/permissive/135077285/mux32Bits2.v
data/verilator_xmls/f94b07ad-e354-4b91-b191-1460df1bbcb1.xml
module mux32Bits2 (
  input wire [31:0] entrada1,
  input wire [31:0] entrada2,
  input wire seletor,
  output reg [31:0] saida
);

  always @(*) saida <= (seletor) ? entrada1 : entrada2;
endmodule
module mux32Bits2 (
  input wire [31:0] entrada1,
  input wire [31:0] entrada2,
  input wire seletor,
  output reg [31:0] saida
);


  always @(*) saida <= (seletor) ? entrada1 : entrada2;
endmodule