data/full_repos/permissive/109846502/clockDivider.v
Syntax Error
1: b'%Warning-IMPLICIT: data/full_repos/permissive/109846502/clockDivider.v:32: Signal definition not found, creating implicitly: \'comp\'\nassign comp = (cnt == (div - 1));\n       ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
function integer clog2b;
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
	val = val >> 1;
end
endfunction
function integer clog2b;

input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
	val = val >> 1;
end
endfunction