data/full_repos/permissive/115035459/verilog/src/mza-test009.multi-segment-driver.v
 line:31: before: "="
1: b'%Error: data/full_repos/permissive/115035459/verilog/src/mza-test009.multi-segment-driver.v:7: Cannot find include file: lib/hex2bcd.v\n`include "lib/hex2bcd.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.v\n             data/full_repos/permissive/115035459/verilog/src,data/full_repos/permissive/115035459/lib/hex2bcd.v.sv\n             lib/hex2bcd.v\n             lib/hex2bcd.v.v\n             lib/hex2bcd.v.sv\n             obj_dir/lib/hex2bcd.v\n             obj_dir/lib/hex2bcd.v.v\n             obj_dir/lib/hex2bcd.v.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/mza-test009.multi-segment-driver.v:8: Cannot find include file: lib/segmented_display_driver.v\n`include "lib/segmented_display_driver.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module mytop (
	input clock,
	output [5:1] LED,
	inout [7:0] J1,
	inout [7:0] J2,
	inout [7:0] J3
);
	wire reset = 0;
	wire [35:0] bcd;
	wire [23:0] data = 24'd00112233;
	if (1) begin



		wire [7:0] segment;
		assign { J3[3], J1[2], J2[0], J3[0], J3[2], J3[5], J1[1], J1[7] } = segment;
		assign J3[1] = 1;
		wire [3:0] anode;
		assign J3[4] = anode[0];
		assign J1[4] = anode[1];
		assign J1[3] = anode[2];
		assign J1[0] = anode[3];

		segmented_display_driver #(.NUMBER_OF_SEGMENTS(8), .NUMBER_OF_NYBBLES(4)) my_instance_name (.clock(clock), .data(bcd[15:0]), .dp(4'h0), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode());
		hex2bcd #(.INPUT_SIZE_IN_NYBBLES(4)) h2binst ( .clock(clock), .reset(reset), .hex_in(data[15:0]), .bcd_out(bcd[23:0]), .sync() );
		assign J3[7] = 0;
		assign J3[6] = 0;
		assign J2[7] = 0;
		assign J2[6] = 0;
		assign J2[5] = 0;
		assign J2[4] = 0;
		assign J2[3] = 0;
		assign J2[2] = 0;
		assign J2[1] = 0;
		assign J1[6] = 0;
		assign J1[5] = 0;
	end else if (0) begin

		wire [15:0] segment;
		assign { J1[3], J1[4], J1[4], J3[3], J1[0], J1[1], J2[7], J2[0], J3[0], J3[1], J3[2], J3[2], J3[4], J3[5], J1[2], J2[3], J2[1], J2[4] } = segment;
		assign J1[5]  = 1;
		assign J2[6]  = anode[0];
		assign J1[6]  = anode[0];
		wire [1:0] anode;
		segmented_display_driver #(.number_of_segments(16), .number_of_nybbles(2)) my_instance_name (.clock(clock), .data(bcd[7:0]), .dp(2'h0), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode());
		hex2bcd #(.input_size_in_nybbles(4)) h2binst ( .clock(clock), .reset(reset), .hex_in(data), .bcd_out(bcd), .sync() );
	end else begin




		wire [7:0] segment;
		assign { J1[4], J1[1], J3[4], J3[5], J1[2], J1[5], J1[3], J3[2] } = segment;
		wire [7:0] anode;
		assign { J2[7], J2[4], J2[5], J2[6], J3[6], J3[7], J3[3], J3[1] } = anode;

		segmented_display_driver #(.number_of_segments(8), .number_of_nybbles(8)) my_segmented_display_driver (.clock(clock), .data(bcd[31:0]), .dp(8'b00010000), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode(signal_output));


		assign J2[2] = 0;
		assign J2[1] = 0;

		assign J1[7] = 0;
		assign J1[6] = 0;
		hex2bcd #(.input_size_in_nybbles(6)) h2binst ( .clock(clock), .reset(reset), .hex_in(data), .bcd_out(bcd), .sync() );
		wire signal_output;
		assign J1[0] = signal_output;
	end
	assign LED = 0;
	reg [40:0] raw_counter = 0;
	reg [40:0] alternate_counter = 0;

	wire [15:0] counter_1000Hz = alternate_counter[26:12];

	wire [15:0] counter_10Hz = alternate_counter[34:19];
	wire [15:0] counter_1Hz = alternate_counter[37:22];
	reg [2:0] clock_token = 0;
	always @(posedge clock) begin
		if (raw_counter[40:10]==0) begin
			clock_token <= 3'b001;
		end else begin
			clock_token <= { clock_token[1:0], clock_token[2] };
		end
		if (clock_token == 3'b001) begin
			alternate_counter++;
		end
		raw_counter++;
	end










endmodule
module mytop (
	input clock,
	output [5:1] LED,
	inout [7:0] J1,
	inout [7:0] J2,
	inout [7:0] J3
);

	wire reset = 0;
	wire [35:0] bcd;
	wire [23:0] data = 24'd00112233;
	if (1) begin



		wire [7:0] segment;
		assign { J3[3], J1[2], J2[0], J3[0], J3[2], J3[5], J1[1], J1[7] } = segment;
		assign J3[1] = 1;
		wire [3:0] anode;
		assign J3[4] = anode[0];
		assign J1[4] = anode[1];
		assign J1[3] = anode[2];
		assign J1[0] = anode[3];

		segmented_display_driver #(.NUMBER_OF_SEGMENTS(8), .NUMBER_OF_NYBBLES(4)) my_instance_name (.clock(clock), .data(bcd[15:0]), .dp(4'h0), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode());
		hex2bcd #(.INPUT_SIZE_IN_NYBBLES(4)) h2binst ( .clock(clock), .reset(reset), .hex_in(data[15:0]), .bcd_out(bcd[23:0]), .sync() );
		assign J3[7] = 0;
		assign J3[6] = 0;
		assign J2[7] = 0;
		assign J2[6] = 0;
		assign J2[5] = 0;
		assign J2[4] = 0;
		assign J2[3] = 0;
		assign J2[2] = 0;
		assign J2[1] = 0;
		assign J1[6] = 0;
		assign J1[5] = 0;
	end else if (0) begin

		wire [15:0] segment;
		assign { J1[3], J1[4], J1[4], J3[3], J1[0], J1[1], J2[7], J2[0], J3[0], J3[1], J3[2], J3[2], J3[4], J3[5], J1[2], J2[3], J2[1], J2[4] } = segment;
		assign J1[5]  = 1;
		assign J2[6]  = anode[0];
		assign J1[6]  = anode[0];
		wire [1:0] anode;
		segmented_display_driver #(.number_of_segments(16), .number_of_nybbles(2)) my_instance_name (.clock(clock), .data(bcd[7:0]), .dp(2'h0), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode());
		hex2bcd #(.input_size_in_nybbles(4)) h2binst ( .clock(clock), .reset(reset), .hex_in(data), .bcd_out(bcd), .sync() );
	end else begin




		wire [7:0] segment;
		assign { J1[4], J1[1], J3[4], J3[5], J1[2], J1[5], J1[3], J3[2] } = segment;
		wire [7:0] anode;
		assign { J2[7], J2[4], J2[5], J2[6], J3[6], J3[7], J3[3], J3[1] } = anode;

		segmented_display_driver #(.number_of_segments(8), .number_of_nybbles(8)) my_segmented_display_driver (.clock(clock), .data(bcd[31:0]), .dp(8'b00010000), .cathode(segment), .anode(anode), .sync_anode(), .sync_cathode(signal_output));


		assign J2[2] = 0;
		assign J2[1] = 0;

		assign J1[7] = 0;
		assign J1[6] = 0;
		hex2bcd #(.input_size_in_nybbles(6)) h2binst ( .clock(clock), .reset(reset), .hex_in(data), .bcd_out(bcd), .sync() );
		wire signal_output;
		assign J1[0] = signal_output;
	end
	assign LED = 0;
	reg [40:0] raw_counter = 0;
	reg [40:0] alternate_counter = 0;

	wire [15:0] counter_1000Hz = alternate_counter[26:12];

	wire [15:0] counter_10Hz = alternate_counter[34:19];
	wire [15:0] counter_1Hz = alternate_counter[37:22];
	reg [2:0] clock_token = 0;
	always @(posedge clock) begin
		if (raw_counter[40:10]==0) begin
			clock_token <= 3'b001;
		end else begin
			clock_token <= { clock_token[1:0], clock_token[2] };
		end
		if (clock_token == 3'b001) begin
			alternate_counter++;
		end
		raw_counter++;
	end










endmodule