data/full_repos/permissive/200104480/Processor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:440: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'singleBit\' generates 1 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.A.ze\n assign dataOut = 32\'b0 + singleBit;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:361: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'dataIn\' generates 16 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.ZE\n assign dataOut = 32\'b0 + dataIn;\n                        ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder4(input [3:0] A,
			input [3:0] B,
			input carryIn,
			output reg [3:0] sum,
			output reg carryOut);	
			
	reg [3:0] C;
	always @(*)
	begin
	C[0]=carryIn;
	C[1]=A[0] & B[0] | (A[0] | B[0]) & C[0];
	C[2]=A[1] & B[1] | (A[1] | B[1]) & C[1];
	C[3]=A[2] & B[2] | (A[2] | B[2]) & C[2];
	carryOut=A[3] & B[3] | (A[3] | B[3]) & C[3];
	sum = A ^ B ^ C;
	end
endmodule
module adder4(input [3:0] A,
			input [3:0] B,
			input carryIn,
			output reg [3:0] sum,
			output reg carryOut);
	
			
	reg [3:0] C;
	always @(*)
	begin
	C[0]=carryIn;
	C[1]=A[0] & B[0] | (A[0] | B[0]) & C[0];
	C[2]=A[1] & B[1] | (A[1] | B[1]) & C[1];
	C[3]=A[2] & B[2] | (A[2] | B[2]) & C[2];
	carryOut=A[3] & B[3] | (A[3] | B[3]) & C[3];
	sum = A ^ B ^ C;
	end
endmodule