data/full_repos/permissive/152666281/VGA.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152666281/VGA.v:34: Operator EQ expects 12 bits on the RHS, but RHS\'s VARREF \'hpixel_end\' generates 11 bits.\n                                                             : ... In instance VGA\nwire hcount_ov = (hcount == hpixel_end);\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/152666281/VGA.v:35: Operator EQ expects 12 bits on the RHS, but RHS\'s VARREF \'vline_end\' generates 11 bits.\n                                                             : ... In instance VGA\nwire vcount_ov = (vcount == vline_end);\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/152666281/VGA.v:36: Operator GTE expects 12 bits on the RHS, but RHS\'s VARREF \'hdat_begin\' generates 11 bits.\n                                                             : ... In instance VGA\nwire dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end)) && ((vcount >= vdat_begin) && (vcount < vdat_end));\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/152666281/VGA.v:36: Operator LT expects 12 bits on the RHS, but RHS\'s VARREF \'hdat_end\' generates 11 bits.\n                                                             : ... In instance VGA\nwire dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end)) && ((vcount >= vdat_begin) && (vcount < vdat_end));\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/152666281/VGA.v:36: Operator GTE expects 12 bits on the RHS, but RHS\'s VARREF \'vdat_begin\' generates 11 bits.\n                                                             : ... In instance VGA\nwire dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end)) && ((vcount >= vdat_begin) && (vcount < vdat_end));\n                                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/152666281/VGA.v:36: Operator LT expects 12 bits on the RHS, but RHS\'s VARREF \'vdat_end\' generates 11 bits.\n                                                             : ... In instance VGA\nwire dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end)) && ((vcount >= vdat_begin) && (vcount < vdat_end));\n                                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/152666281/VGA.v:38: Operator GT expects 12 bits on the RHS, but RHS\'s VARREF \'hsync_end\' generates 11 bits.\n                                                             : ... In instance VGA\nassign VGA_hsync = (hcount > hsync_end);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/152666281/VGA.v:39: Operator GT expects 12 bits on the RHS, but RHS\'s VARREF \'vsync_end\' generates 11 bits.\n                                                             : ... In instance VGA\nassign VGA_vsync = (vcount > vsync_end);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/152666281/VGA.v:50: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                             : ... In instance VGA\n  if(hcount_ov && vcount_ov) vcount <= 11\'b0;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/152666281/VGA.v:52: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                             : ... In instance VGA\n  if (hcount_ov) hcount <= 11\'d0;\n                        ^~\n%Error: Exiting due to 10 warning(s)\n'
module VGA(
   input  wire       clk,
   input wire [2:0]  rgb_data,
   output wire       graphics_trigger,
   output wire [11:0] graphics_coords_x,
   output wire [11:0] graphics_coords_y,
   output wire [2:0] VGA_rgb,
   output wire       VGA_hsync,
   output wire       VGA_vsync
);

parameter








  hsync_end  = 11'd190,
  hdat_begin = 11'd286,
  hdat_end   = 11'd1566,
  hpixel_end = 11'd1598,
  vsync_end  = 11'd1,
  vdat_begin = 11'd68,
  vdat_end   = 11'd1028,
  vline_end  = 11'd1048;

reg [11:0] hcount;
reg [11:0] vcount;
wire graphics_clk = clk;

wire hcount_ov = (hcount == hpixel_end);
wire vcount_ov = (vcount == vline_end);
wire dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end)) && ((vcount >= vdat_begin) && (vcount < vdat_end));

assign VGA_hsync = (hcount > hsync_end);
assign VGA_vsync = (vcount > vsync_end);
assign VGA_rgb = (dat_act) ?  rgb_data : 3'b0;
assign graphics_coords_x = hcount - hdat_begin;
assign graphics_coords_y = vcount - vdat_begin;
assign graphics_trigger = dat_act & graphics_clk;





always @(posedge graphics_clk) begin
  if(hcount_ov && vcount_ov) vcount <= 11'b0;
  else if(hcount_ov) vcount <= vcount + 11'b1;
  if (hcount_ov) hcount <= 11'd0;
  else hcount <= hcount + 11'd1;
end
endmodule
module VGA(
   input  wire       clk,
   input wire [2:0]  rgb_data,
   output wire       graphics_trigger,
   output wire [11:0] graphics_coords_x,
   output wire [11:0] graphics_coords_y,
   output wire [2:0] VGA_rgb,
   output wire       VGA_hsync,
   output wire       VGA_vsync
);


parameter








  hsync_end  = 11'd190,
  hdat_begin = 11'd286,
  hdat_end   = 11'd1566,
  hpixel_end = 11'd1598,
  vsync_end  = 11'd1,
  vdat_begin = 11'd68,
  vdat_end   = 11'd1028,
  vline_end  = 11'd1048;

reg [11:0] hcount;
reg [11:0] vcount;
wire graphics_clk = clk;

wire hcount_ov = (hcount == hpixel_end);
wire vcount_ov = (vcount == vline_end);
wire dat_act = ((hcount >= hdat_begin) && (hcount < hdat_end)) && ((vcount >= vdat_begin) && (vcount < vdat_end));

assign VGA_hsync = (hcount > hsync_end);
assign VGA_vsync = (vcount > vsync_end);
assign VGA_rgb = (dat_act) ?  rgb_data : 3'b0;
assign graphics_coords_x = hcount - hdat_begin;
assign graphics_coords_y = vcount - vdat_begin;
assign graphics_trigger = dat_act & graphics_clk;





always @(posedge graphics_clk) begin
  if(hcount_ov && vcount_ov) vcount <= 11'b0;
  else if(hcount_ov) vcount <= vcount + 11'b1;
  if (hcount_ov) hcount <= 11'd0;
  else hcount <= hcount + 11'd1;
end
endmodule