data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/XEM6310-Verilog/First.v
1: b"%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/XEM6310-Verilog/First.v:45: Cannot find file containing module: 'okHost'\nokHost okHI(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/XEM6310-Verilog,data/full_repos/permissive/120539939/okHost\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/XEM6310-Verilog,data/full_repos/permissive/120539939/okHost.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/XEM6310-Verilog,data/full_repos/permissive/120539939/okHost.sv\n             okHost\n             okHost.v\n             okHost.sv\n             obj_dir/okHost\n             obj_dir/okHost.v\n             obj_dir/okHost.sv\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/XEM6310-Verilog/First.v:55: Cannot find file containing module: 'okWireOR'\nokWireOR # (.N(2)) wireOR (okEH, okEHx);\n^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/XEM6310-Verilog/First.v:57: Cannot find file containing module: 'okWireIn'\nokWireIn     ep00 (.okHE(okHE),                             .ep_addr(8'h00), .ep_dataout(ep00wire));\n^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/XEM6310-Verilog/First.v:58: Cannot find file containing module: 'okWireIn'\nokWireIn     ep01 (.okHE(okHE),                             .ep_addr(8'h01), .ep_dataout(ep01wire));\n^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/XEM6310-Verilog/First.v:59: Cannot find file containing module: 'okWireIn'\nokWireIn     ep02 (.okHE(okHE),                             .ep_addr(8'h02), .ep_dataout(ep02wire));\n^~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/XEM6310-Verilog/First.v:60: Cannot find file containing module: 'okWireOut'\nokWireOut    ep20 (.okHE(okHE), .okEH(okEHx[ 0*65 +: 65 ]), .ep_addr(8'h20), .ep_datain(ep20wire));\n^~~~~~~~~\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/First/XEM6310-Verilog/First.v:61: Cannot find file containing module: 'okWireOut'\nokWireOut    ep21 (.okHE(okHE), .okEH(okEHx[ 1*65 +: 65 ]), .ep_addr(8'h21), .ep_datain(ep21wire));\n^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module First(
	input  wire [4:0]   okUH,
	output wire [2:0]   okHU,
	inout  wire [31:0]  okUHU,
	inout  wire         okAA,

	output wire [7:0]   led
	);


wire         okClk;
wire [112:0] okHE;
wire [64:0]  okEH;


wire [31:0]  ep00wire;
wire [31:0]  ep01wire;
wire [31:0]  ep02wire;
wire [31:0]  ep20wire;
reg  [31:0]  ep21wire;

assign led      = ~ep00wire[7:0];
assign ep20wire = {32'h0000};
always @(posedge okClk)  ep21wire <= ep01wire + ep02wire;


wire [65*2-1:0]  okEHx;
okHost okHI(
	.okUH(okUH),
	.okHU(okHU),
	.okUHU(okUHU),
	.okAA(okAA),
	.okClk(okClk),
	.okHE(okHE), 
	.okEH(okEH)
);

okWireOR # (.N(2)) wireOR (okEH, okEHx);

okWireIn     ep00 (.okHE(okHE),                             .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireIn     ep01 (.okHE(okHE),                             .ep_addr(8'h01), .ep_dataout(ep01wire));
okWireIn     ep02 (.okHE(okHE),                             .ep_addr(8'h02), .ep_dataout(ep02wire));
okWireOut    ep20 (.okHE(okHE), .okEH(okEHx[ 0*65 +: 65 ]), .ep_addr(8'h20), .ep_datain(ep20wire));
okWireOut    ep21 (.okHE(okHE), .okEH(okEHx[ 1*65 +: 65 ]), .ep_addr(8'h21), .ep_datain(ep21wire));

endmodule
module First(
	input  wire [4:0]   okUH,
	output wire [2:0]   okHU,
	inout  wire [31:0]  okUHU,
	inout  wire         okAA,

	output wire [7:0]   led
	);



wire         okClk;
wire [112:0] okHE;
wire [64:0]  okEH;


wire [31:0]  ep00wire;
wire [31:0]  ep01wire;
wire [31:0]  ep02wire;
wire [31:0]  ep20wire;
reg  [31:0]  ep21wire;

assign led      = ~ep00wire[7:0];
assign ep20wire = {32'h0000};
always @(posedge okClk)  ep21wire <= ep01wire + ep02wire;


wire [65*2-1:0]  okEHx;
okHost okHI(
	.okUH(okUH),
	.okHU(okHU),
	.okUHU(okUHU),
	.okAA(okAA),
	.okClk(okClk),
	.okHE(okHE), 
	.okEH(okEH)
);

okWireOR # (.N(2)) wireOR (okEH, okEHx);

okWireIn     ep00 (.okHE(okHE),                             .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireIn     ep01 (.okHE(okHE),                             .ep_addr(8'h01), .ep_dataout(ep01wire));
okWireIn     ep02 (.okHE(okHE),                             .ep_addr(8'h02), .ep_dataout(ep02wire));
okWireOut    ep20 (.okHE(okHE), .okEH(okEHx[ 0*65 +: 65 ]), .ep_addr(8'h20), .ep_datain(ep20wire));
okWireOut    ep21 (.okHE(okHE), .okEH(okEHx[ 1*65 +: 65 ]), .ep_addr(8'h21), .ep_datain(ep21wire));

endmodule