data/full_repos/permissive/192010622/src/rgb.v
 line:45: before: "."
1: b'%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/rgb.v:50: Signal definition not found, creating implicitly: \'clk\'\n   always @(posedge clk)\n                    ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/192010622/src/rgb.v:39: Cannot find file containing module: \'SB_HFOSC\'\n  SB_HFOSC OSC_i (                   \n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/192010622/src,data/full_repos/permissive/192010622/SB_HFOSC\n             data/full_repos/permissive/192010622/src,data/full_repos/permissive/192010622/SB_HFOSC.v\n             data/full_repos/permissive/192010622/src,data/full_repos/permissive/192010622/SB_HFOSC.sv\n             SB_HFOSC\n             SB_HFOSC.v\n             SB_HFOSC.sv\n             obj_dir/SB_HFOSC\n             obj_dir/SB_HFOSC.v\n             obj_dir/SB_HFOSC.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module fpga_top (
    output reg  WF_NEO
);

 








   reg  [23:0] pixel0;

   reg  [4:0]  pixel_bit_cnt;
   reg  [1:0]  pixel_cnt;
   reg  [23:0] shift_pixels;

   wire        phase;
   reg         phase_d;
   reg         phase_tmp;

   reg         np_eof;
   wire        np_sof;

   reg [2:0] reset_cnt;
   reg [3:0] np_clk_cnt;
   reg       pixel_bit_end;
   reg       tog_bit0;
   reg       tog_bit1;




  wire clk_en;
  assign clk_en = 1'b1;

  SB_HFOSC OSC_i (
        .CLKHFEN(clk_en),
        .CLKHFPU(clk_en),
        .CLKHF(clk));


   defparam OSC_i.CLKHF_DIV = "0b10";




   always @(posedge clk)





         begin 
           if (phase==0)
             begin
            if (np_sof)
           begin
                   WF_NEO      <= 1'b1;
              end
               else
                 begin
                   WF_NEO         <= 1'b0;
                   shift_pixels <= pixel0;
                   pixel_bit_cnt<= 5'b0;
                   np_eof       <= 1'b0;
                 end
             end
           else
             begin
               if (( shift_pixels[0] && tog_bit1) ||
                   (~shift_pixels[0] && tog_bit0) )
                  WF_NEO <= 1'b0;


               if (pixel_bit_end)
                 if (pixel_bit_cnt != 23)
                   begin
                     WF_NEO          <= 1'b1;
                     shift_pixels  <= {1'b0,shift_pixels[23:1]};
                     pixel_bit_cnt <= pixel_bit_cnt + 1'b1;
                   end
           else
             begin
                     np_eof <= 1'b1;
                     WF_NEO   <= 1'b0; 
             end
             end
         end


































parameter [3:0] BIT1_HI = 10;
parameter [3:0] BIT1_LO =  5;
parameter [3:0] BIT0_HI =  5;
parameter [3:0] BIT0_LO = 10;

parameter [3:0] NEO_PERIOD = 15;



   always @(posedge clk)
     begin
       if (np_sof)
         begin
           np_clk_cnt <= 4'b1;

         end
       else if (phase == 1'b1)
         begin
           if (np_clk_cnt == NEO_PERIOD- 4'h1)
             begin
               np_clk_cnt     <= 4'b0;
               pixel_bit_end  <= 1'b1;
             end
           else
             np_clk_cnt <= np_clk_cnt + 4'b1;

           if (np_clk_cnt == BIT0_HI -4'h1)
             tog_bit0 <= 1'b1;
           else
             tog_bit0 <= 1'b0;

           if (np_clk_cnt == BIT1_HI -4'h1)
             tog_bit1 <= 1'b1;
           else
             tog_bit1 <= 1'b0;

           if (pixel_bit_end) pixel_bit_end <= 1'b0;
         end
     end




     wire ten_us;
     wire two_ms;


     ten_usec  ten_usec ( 
           .clk(clk),
           .ten_us(ten_us));


     two_msec two_msec( 
           .clk(clk),
           .ten_us(ten_us),
           .two_ms(two_ms));




   always @(posedge clk)
     begin
       if (phase_tmp == 0)
      begin
           if (ten_us)
             begin
               if (reset_cnt == 'h6)
                 begin
                   phase_tmp <= 1'b1;
                   reset_cnt <= 'd0;
                 end
               else
                 reset_cnt <= reset_cnt + 3'd1;
             end  
         end

       if (np_eof)
         phase_tmp <= 1'b0;


       phase_d <= phase_tmp;

     end

    assign np_sof =  ~phase_d && phase_tmp; 
    assign phase = phase_d;







  reg [1:0] cnt;
  reg [6:0] cnt2;
  reg       updn;
  reg [2:0] ph;

  wire [6:0]  cnt2_G;
  wire [6:0]  cnt2_R;
  wire [6:0]  cnt2_B;


  wire [6:0] cnt2_w={cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};

  assign cnt2_G = cnt2_w;
  assign cnt2_R = cnt2_w;
  assign cnt2_B = cnt2_w;



   always @(posedge clk)
     begin
       if (two_ms)
      begin
           cnt <= cnt + 2'h01;
           if (cnt == 0)
             begin
               if (cnt2 ==  127)
              begin
                   cnt2 <= 126;
                   updn = ~updn;
                ph <= ph + 3'b1;
              end
            else if (cnt2 == 1 && updn ==1)
                begin
                     cnt2 <= 1;
                     updn = ~updn;
                  ph <= ph + 3'b1;
                end
            else if (updn==0)
                     cnt2 <= cnt2 + 7'b1;
            else
                     cnt2 <= cnt2 - 7'b1;
        end
     end
    end
        


   always @(*)
    case (ph)
      3'h0: pixel0[23:0] <= {8'h00,8'hfe,8'h00};
      3'h1: pixel0[23:0] <= {8'h00,8'h00,8'hfe};
      3'h2: pixel0[23:0] <= {8'hfe,8'h00,8'h00};
      3'h3: pixel0[23:0] <= {8'h00,{cnt2_R,1'b0},8'h00};
      3'h4: pixel0[23:0] <= {8'h00,8'h00,{cnt2_G,1'b0}};
      3'h5: pixel0[23:0] <= {{cnt2_B,1'b0},8'h00,8'h00};
      3'h6: pixel0[23:0] <= {8'h00,{cnt2_R,1'b0},{~cnt2_G,1'b0}};
      3'h7: pixel0[23:0] <= {{cnt2_B,1'b0},8'h00,{~cnt2_G,1'b0}};
    endcase


endmodule
module fpga_top (
    output reg  WF_NEO
);


 








   reg  [23:0] pixel0;

   reg  [4:0]  pixel_bit_cnt;
   reg  [1:0]  pixel_cnt;
   reg  [23:0] shift_pixels;

   wire        phase;
   reg         phase_d;
   reg         phase_tmp;

   reg         np_eof;
   wire        np_sof;

   reg [2:0] reset_cnt;
   reg [3:0] np_clk_cnt;
   reg       pixel_bit_end;
   reg       tog_bit0;
   reg       tog_bit1;




  wire clk_en;
  assign clk_en = 1'b1;

  SB_HFOSC OSC_i (
        .CLKHFEN(clk_en),
        .CLKHFPU(clk_en),
        .CLKHF(clk));


   defparam OSC_i.CLKHF_DIV = "0b10";




   always @(posedge clk)





         begin 
           if (phase==0)
             begin
            if (np_sof)
           begin
                   WF_NEO      <= 1'b1;
              end
               else
                 begin
                   WF_NEO         <= 1'b0;
                   shift_pixels <= pixel0;
                   pixel_bit_cnt<= 5'b0;
                   np_eof       <= 1'b0;
                 end
             end
           else
             begin
               if (( shift_pixels[0] && tog_bit1) ||
                   (~shift_pixels[0] && tog_bit0) )
                  WF_NEO <= 1'b0;


               if (pixel_bit_end)
                 if (pixel_bit_cnt != 23)
                   begin
                     WF_NEO          <= 1'b1;
                     shift_pixels  <= {1'b0,shift_pixels[23:1]};
                     pixel_bit_cnt <= pixel_bit_cnt + 1'b1;
                   end
           else
             begin
                     np_eof <= 1'b1;
                     WF_NEO   <= 1'b0; 
             end
             end
         end


































parameter [3:0] BIT1_HI = 10;
parameter [3:0] BIT1_LO =  5;
parameter [3:0] BIT0_HI =  5;
parameter [3:0] BIT0_LO = 10;

parameter [3:0] NEO_PERIOD = 15;



   always @(posedge clk)
     begin
       if (np_sof)
         begin
           np_clk_cnt <= 4'b1;

         end
       else if (phase == 1'b1)
         begin
           if (np_clk_cnt == NEO_PERIOD- 4'h1)
             begin
               np_clk_cnt     <= 4'b0;
               pixel_bit_end  <= 1'b1;
             end
           else
             np_clk_cnt <= np_clk_cnt + 4'b1;

           if (np_clk_cnt == BIT0_HI -4'h1)
             tog_bit0 <= 1'b1;
           else
             tog_bit0 <= 1'b0;

           if (np_clk_cnt == BIT1_HI -4'h1)
             tog_bit1 <= 1'b1;
           else
             tog_bit1 <= 1'b0;

           if (pixel_bit_end) pixel_bit_end <= 1'b0;
         end
     end




     wire ten_us;
     wire two_ms;


     ten_usec  ten_usec ( 
           .clk(clk),
           .ten_us(ten_us));


     two_msec two_msec( 
           .clk(clk),
           .ten_us(ten_us),
           .two_ms(two_ms));




   always @(posedge clk)
     begin
       if (phase_tmp == 0)
      begin
           if (ten_us)
             begin
               if (reset_cnt == 'h6)
                 begin
                   phase_tmp <= 1'b1;
                   reset_cnt <= 'd0;
                 end
               else
                 reset_cnt <= reset_cnt + 3'd1;
             end  
         end

       if (np_eof)
         phase_tmp <= 1'b0;


       phase_d <= phase_tmp;

     end

    assign np_sof =  ~phase_d && phase_tmp; 
    assign phase = phase_d;







  reg [1:0] cnt;
  reg [6:0] cnt2;
  reg       updn;
  reg [2:0] ph;

  wire [6:0]  cnt2_G;
  wire [6:0]  cnt2_R;
  wire [6:0]  cnt2_B;


  wire [6:0] cnt2_w={cnt2[0],cnt2[1],cnt2[2],cnt2[3],cnt2[4],cnt2[5],cnt2[6]};

  assign cnt2_G = cnt2_w;
  assign cnt2_R = cnt2_w;
  assign cnt2_B = cnt2_w;



   always @(posedge clk)
     begin
       if (two_ms)
      begin
           cnt <= cnt + 2'h01;
           if (cnt == 0)
             begin
               if (cnt2 ==  127)
              begin
                   cnt2 <= 126;
                   updn = ~updn;
                ph <= ph + 3'b1;
              end
            else if (cnt2 == 1 && updn ==1)
                begin
                     cnt2 <= 1;
                     updn = ~updn;
                  ph <= ph + 3'b1;
                end
            else if (updn==0)
                     cnt2 <= cnt2 + 7'b1;
            else
                     cnt2 <= cnt2 - 7'b1;
        end
     end
    end
        


   always @(*)
    case (ph)
      3'h0: pixel0[23:0] <= {8'h00,8'hfe,8'h00};
      3'h1: pixel0[23:0] <= {8'h00,8'h00,8'hfe};
      3'h2: pixel0[23:0] <= {8'hfe,8'h00,8'h00};
      3'h3: pixel0[23:0] <= {8'h00,{cnt2_R,1'b0},8'h00};
      3'h4: pixel0[23:0] <= {8'h00,8'h00,{cnt2_G,1'b0}};
      3'h5: pixel0[23:0] <= {{cnt2_B,1'b0},8'h00,8'h00};
      3'h6: pixel0[23:0] <= {8'h00,{cnt2_R,1'b0},{~cnt2_G,1'b0}};
      3'h7: pixel0[23:0] <= {{cnt2_B,1'b0},8'h00,{~cnt2_G,1'b0}};
    endcase


endmodule