data/full_repos/permissive/112861503/test/lamp_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/112861503/test/lamp_tb.v:2: Cannot find include file: lamp.v\n`include "lamp.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/112861503/test,data/full_repos/permissive/112861503/lamp.v\n             data/full_repos/permissive/112861503/test,data/full_repos/permissive/112861503/lamp.v.v\n             data/full_repos/permissive/112861503/test,data/full_repos/permissive/112861503/lamp.v.sv\n             lamp.v\n             lamp.v.v\n             lamp.v.sv\n             obj_dir/lamp.v\n             obj_dir/lamp.v.v\n             obj_dir/lamp.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #0.025 r_clk = !r_clk;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #100000 $display($time, " 100 ms have passed");\n    ^\n%Error: data/full_repos/permissive/112861503/test/lamp_tb.v:53: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("lamp.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/112861503/test/lamp_tb.v:54: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, lamp_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #100000 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n      #5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/112861503/test/lamp_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n%Error: Exiting due to 3 error(s), 8 warning(s)\n'
module lamp_tb();

  reg r_clk;

  reg r_dck;
  reg r_cs;
  reg r_mosi;

  wire w_clk;
  wire w_dai;
  wire w_lat;
    
  integer i;

  lamp #(
    .c_freq (20000000)
  ) lamp (
    .i_clk (r_clk),
    .i_dck (r_dck),
    .i_cs (r_cs),
    .i_mosi (r_mosi),
    .o_clk (w_clk),
    .o_dai (w_dai),
    .o_lat (w_lat)
  );

  initial begin
    r_clk = 0;
    r_dck = 0;
    r_cs = 1;
    r_mosi = 0;
  end 
 
  always begin
    #0.025 r_clk = !r_clk;
  end

  always begin
    #100000 $display($time, " 100 ms have passed");
  end

  initial begin

    r_cs = 0;
    sendData(128'h000e0078001001001001800800800800);
    r_cs = 1;
  end

  initial begin
    $dumpfile("lamp.vcd");
    $dumpvars(0, lamp_tb);
    #100000 $finish;
  end

  task sendData;
    input [127:0] i_data;
    begin
      r_cs = 0;
      #10;
      for(i=0; i<128; i=i+1) begin
        #5;
        r_dck = 0;
        r_mosi = i_data[127 - i];
        #5;
        r_dck = 1;
      end
      #5;
      r_dck = 0;
      r_mosi = 0;
      #10;
      r_cs = 1;
    end
  endtask
   
endmodule
module lamp_tb();


  reg r_clk;

  reg r_dck;
  reg r_cs;
  reg r_mosi;

  wire w_clk;
  wire w_dai;
  wire w_lat;
    
  integer i;

  lamp #(
    .c_freq (20000000)
  ) lamp (
    .i_clk (r_clk),
    .i_dck (r_dck),
    .i_cs (r_cs),
    .i_mosi (r_mosi),
    .o_clk (w_clk),
    .o_dai (w_dai),
    .o_lat (w_lat)
  );

  initial begin
    r_clk = 0;
    r_dck = 0;
    r_cs = 1;
    r_mosi = 0;
  end 
 
  always begin
    #0.025 r_clk = !r_clk;
  end

  always begin
    #100000 $display($time, " 100 ms have passed");
  end

  initial begin

    r_cs = 0;
    sendData(128'h000e0078001001001001800800800800);
    r_cs = 1;
  end

  initial begin
    $dumpfile("lamp.vcd");
    $dumpvars(0, lamp_tb);
    #100000 $finish;
  end

  task sendData;
    input [127:0] i_data;
    begin
      r_cs = 0;
      #10;
      for(i=0; i<128; i=i+1) begin
        #5;
        r_dck = 0;
        r_mosi = i_data[127 - i];
        #5;
        r_dck = 1;
      end
      #5;
      r_dck = 0;
      r_mosi = 0;
      #10;
      r_cs = 1;
    end
  endtask
   
endmodule