data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag/jtag_if.v
1: b"%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag/jtag_if.v:29: Cannot find file containing module: 'jtag_dmi_if'\njtag_dmi_if#(  \n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag,data/full_repos/permissive/125344718/jtag_dmi_if\n             data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag,data/full_repos/permissive/125344718/jtag_dmi_if.v\n             data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag,data/full_repos/permissive/125344718/jtag_dmi_if.sv\n             jtag_dmi_if\n             jtag_dmi_if.v\n             jtag_dmi_if.sv\n             obj_dir/jtag_dmi_if\n             obj_dir/jtag_dmi_if.v\n             obj_dir/jtag_dmi_if.sv\n%Error: data/full_repos/permissive/125344718/rv32i_arty_bram/src/rtl/jtag/jtag_if.v:47: Cannot find file containing module: 'jtag_info_if'\njtag_info_if#(\n^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module jtag_if#(
    parameter DMI_ADDR_WIDTH = 7,
    parameter DMI_DATA_WIDTH = 32,
    parameter DMI_OP_WIDTH = 2,
    parameter TX_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH),
    parameter RX_WIDTH = (DMI_DATA_WIDTH+DMI_OP_WIDTH),
    parameter INFO_DATA_WIDTH = 32
)(


    output creq_vld,
    output [TX_WIDTH-1:0] creq_data,
    input creq_rdy,
    input cresp_vld,
    input [RX_WIDTH-1:0] cresp_data,
    output cresp_rdy,
    input reset,
    input clock,



    output jsys_reset,

    input init_ddr3_done
);

jtag_dmi_if#(
    .JTAG_CHAIN(4),
    .DMI_ADDR_WIDTH(DMI_ADDR_WIDTH),
    .DMI_DATA_WIDTH(DMI_DATA_WIDTH),
    .DMI_OP_WIDTH(DMI_OP_WIDTH)
) jtag_dmi_dev (

    .creq_vld(creq_vld),
    .creq_data(creq_data),
    .creq_rdy(creq_rdy),
    .cresp_vld(cresp_vld),
    .cresp_data(cresp_data),
    .cresp_rdy(cresp_rdy),

    .reset(reset),
    .clock(clock)
);

jtag_info_if#(
    .JTAG_CHAIN(3),
    .JTAG_DATA_WIDTH(32)
) jtag_info_dev (

    .jsys_reset(jsys_reset),

    .init_ddr3_done(init_ddr3_done)
);

endmodule
module jtag_if#(
    parameter DMI_ADDR_WIDTH = 7,
    parameter DMI_DATA_WIDTH = 32,
    parameter DMI_OP_WIDTH = 2,
    parameter TX_WIDTH = (DMI_ADDR_WIDTH+DMI_DATA_WIDTH+DMI_OP_WIDTH),
    parameter RX_WIDTH = (DMI_DATA_WIDTH+DMI_OP_WIDTH),
    parameter INFO_DATA_WIDTH = 32
)(


    output creq_vld,
    output [TX_WIDTH-1:0] creq_data,
    input creq_rdy,
    input cresp_vld,
    input [RX_WIDTH-1:0] cresp_data,
    output cresp_rdy,
    input reset,
    input clock,



    output jsys_reset,

    input init_ddr3_done
);


jtag_dmi_if#(
    .JTAG_CHAIN(4),
    .DMI_ADDR_WIDTH(DMI_ADDR_WIDTH),
    .DMI_DATA_WIDTH(DMI_DATA_WIDTH),
    .DMI_OP_WIDTH(DMI_OP_WIDTH)
) jtag_dmi_dev (

    .creq_vld(creq_vld),
    .creq_data(creq_data),
    .creq_rdy(creq_rdy),
    .cresp_vld(cresp_vld),
    .cresp_data(cresp_data),
    .cresp_rdy(cresp_rdy),

    .reset(reset),
    .clock(clock)
);

jtag_info_if#(
    .JTAG_CHAIN(3),
    .JTAG_DATA_WIDTH(32)
) jtag_info_dev (

    .jsys_reset(jsys_reset),

    .init_ddr3_done(init_ddr3_done)
);

endmodule