data/full_repos/permissive/18770871/adder.v
data/verilator_xmls/9cf3bed3-9455-4ad4-a178-b8f050e9f673.xml
module adder( pc_add, imm, shiftout);
  input [15:0] pc_add;
  input [15:0] imm;
  output [15:0] shiftout;
  assign shiftout = pc_add + imm;
endmodule
module adder( pc_add, imm, shiftout);

  input [15:0] pc_add;
  input [15:0] imm;
  output [15:0] shiftout;
  assign shiftout = pc_add + imm;
endmodule