data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Bitextern.v
data/verilator_xmls/364874f5-1b80-43fe-8459-c5456ace0b41.xml
module Bitextern(
input extern_way,
input [15:0]data_in,
output reg [31:0]data_out
    );
    initial
    begin
        data_out = 32'h00000;
    end    
    always@(data_in or extern_way)
    begin
        if(!extern_way || !data_in[15])
        begin
            data_out[31:16] <= 16'h0000;
        end
        else begin
            data_out[31:16] <= 16'hffff;
        end
        data_out[15:0] <= data_in;
    end
endmodule
module Bitextern(
input extern_way,
input [15:0]data_in,
output reg [31:0]data_out
    );

    initial
    begin
        data_out = 32'h00000;
    end    
    always@(data_in or extern_way)
    begin
        if(!extern_way || !data_in[15])
        begin
            data_out[31:16] <= 16'h0000;
        end
        else begin
            data_out[31:16] <= 16'hffff;
        end
        data_out[15:0] <= data_in;
    end
endmodule