data/full_repos/permissive/139213403/FPGA/blinker_counter_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/blinker_counter_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/blinker_counter_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/blinker_counter_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/blinker_counter_testbench.v:31: syntax error, unexpected \'@\'\n   @(negedge reset);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/blinker_counter_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #(200);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/blinker_counter_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n   #(200);  \n   ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module blinker_counter_testbench;
	
	localparam T=20;
	
	reg clk, reset;
	reg blink;
	wire b_en;
	
	blinker_counter #(.C_ON(3), .C_OFF(2), .C_BITS(2)) uut(clk, reset, blink, b_en);

	always
		begin
			clk = 1'b1;
			#(T / 2);
			clk = 1'b0;
			#(T / 2);
		end
		

	initial
		begin
			reset = 1'b1;
			#(T / 2);
			reset = 1'b0;
		end
	
	initial
		begin
			@(negedge reset);
			blink = 1'b1;
			#(200);
			blink = 1'b0;
			#(200);		
			$stop;
		end
	
endmodule
module blinker_counter_testbench;

	
	localparam T=20;
	
	reg clk, reset;
	reg blink;
	wire b_en;
	
	blinker_counter #(.C_ON(3), .C_OFF(2), .C_BITS(2)) uut(clk, reset, blink, b_en);

	always
		begin
			clk = 1'b1;
			#(T / 2);
			clk = 1'b0;
			#(T / 2);
		end
		

	initial
		begin
			reset = 1'b1;
			#(T / 2);
			reset = 1'b0;
		end
	
	initial
		begin
			@(negedge reset);
			blink = 1'b1;
			#(200);
			blink = 1'b0;
			#(200);		
			$stop;
		end
	
endmodule