data/full_repos/permissive/109936328/tb/tb_instruction_memory.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:1: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/opcodes.vh\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/opcodes.vh.v\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/opcodes.vh.sv\n             opcodes.vh\n             opcodes.vh.v\n             opcodes.vh.sv\n             obj_dir/opcodes.vh\n             obj_dir/opcodes.vh.v\n             obj_dir/opcodes.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:13: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] req_addr;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:15: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] res_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:19: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_instruction_memory.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:20: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_instruction_memory.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_HPERIOD);\n    ^\n%Error: Exiting due to 5 error(s), 3 warning(s)\n'
module tb_instruction_memory;

  localparam CLK_HPERIOD = 5;
  localparam CLK_PERIOD = 2 * CLK_HPERIOD;

  localparam INSTR_MAX = 5;
  localparam INSTR_FILE = "instr.txt";

  reg clk = 0;

  reg [`ADDR_W - 1:0] req_addr;

  wire [`WORD_W - 1:0] res_data;

  integer i;
  initial begin
    $dumpfile("tb_instruction_memory.vcd");
    $dumpvars;

    $display("Printing instructions.");
    for(i = 0; i < INSTR_MAX; i = i + 1) begin
      req_addr = {i, 2'b00};
      #(CLK_PERIOD);
      $display("%8h", res_data);
    end

    $display("Out of bounds test.");
    req_addr = {INSTR_MAX, 2'b00};
    #(CLK_PERIOD);
    $display("%8h", res_data);

    $finish;
  end

  always begin
    #(CLK_HPERIOD);
    clk = ~clk;
  end

  instruction_memory#(
    .INSTR_MAX(INSTR_MAX),
    .INSTR_FILE(INSTR_FILE)
  ) dut(
    .clk(clk),

    .i_req_addr(req_addr),

    .o_res_data(res_data)
  );

endmodule
module tb_instruction_memory;


  localparam CLK_HPERIOD = 5;
  localparam CLK_PERIOD = 2 * CLK_HPERIOD;

  localparam INSTR_MAX = 5;
  localparam INSTR_FILE = "instr.txt";

  reg clk = 0;

  reg [`ADDR_W - 1:0] req_addr;

  wire [`WORD_W - 1:0] res_data;

  integer i;
  initial begin
    $dumpfile("tb_instruction_memory.vcd");
    $dumpvars;

    $display("Printing instructions.");
    for(i = 0; i < INSTR_MAX; i = i + 1) begin
      req_addr = {i, 2'b00};
      #(CLK_PERIOD);
      $display("%8h", res_data);
    end

    $display("Out of bounds test.");
    req_addr = {INSTR_MAX, 2'b00};
    #(CLK_PERIOD);
    $display("%8h", res_data);

    $finish;
  end

  always begin
    #(CLK_HPERIOD);
    clk = ~clk;
  end

  instruction_memory#(
    .INSTR_MAX(INSTR_MAX),
    .INSTR_FILE(INSTR_FILE)
  ) dut(
    .clk(clk),

    .i_req_addr(req_addr),

    .o_res_data(res_data)
  );

endmodule