data/full_repos/permissive/167489907/ALU/ALU_LEGv8.v
None: at end of input
1: b"%Error: data/full_repos/permissive/167489907/ALU/ALU_LEGv8.v:39: Cannot find file containing module: 'CLA_adder64bit'\n CLA_adder64bit adder_inst (C0, A_Signal, B_Signal, add_output, C);\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167489907/ALU,data/full_repos/permissive/167489907/CLA_adder64bit\n             data/full_repos/permissive/167489907/ALU,data/full_repos/permissive/167489907/CLA_adder64bit.v\n             data/full_repos/permissive/167489907/ALU,data/full_repos/permissive/167489907/CLA_adder64bit.sv\n             CLA_adder64bit\n             CLA_adder64bit.v\n             CLA_adder64bit.sv\n             obj_dir/CLA_adder64bit\n             obj_dir/CLA_adder64bit.v\n             obj_dir/CLA_adder64bit.sv\n%Error: data/full_repos/permissive/167489907/ALU/ALU_LEGv8.v:42: Cannot find file containing module: 'Mux8to1Nbit'\n Mux8to1Nbit #(64) main_mux (F, FS[4:2], 64'b0, 64'b0, shift_right, shift_left, xor_output, add_output, or_output, and_output);\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Shifter(left, right, A, shift_amount);
	input [63:0] A;
	input [5:0] shift_amount;
	output reg [63:0] left, right;
	always @* begin
		left = A << shift_amount;
		right = A >> shift_amount;
	end
endmodule
module Shifter(left, right, A, shift_amount);

	input [63:0] A;
	input [5:0] shift_amount;
	output reg [63:0] left, right;
	always @* begin
		left = A << shift_amount;
		right = A >> shift_amount;
	end
endmodule