data/full_repos/permissive/135077285/main.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/135077285/main.v:465: Multiple top level modules\n                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                  : ... Top module \'main\'\nmodule main (clock, instr, reset);\n       ^~~~\n                                                                  : ... Top module \'setSeg\'\nmodule setSeg(in, out);\n       ^~~~~~\n%Error: data/full_repos/permissive/135077285/main.v:127: Input/output/inout does not appear in port list: \'regWriteMemWb\'\n  input wire regWriteMemWb;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135077285/main.v:128: Input/output/inout does not appear in port list: \'memToRegMemWb\'\n  input wire memToRegMemWb;\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135077285/main.v:130: Input/output/inout does not appear in port list: \'readDataMemoryMemWb\'\n  input wire [31:0] readDataMemoryMemWb;\n                    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135077285/main.v:131: Input/output/inout does not appear in port list: \'aluResultMemWb\'\n  input wire [31:0] aluResultMemWb;\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/135077285/main.v:132: Input/output/inout does not appear in port list: \'writeRegisterMemWb\'\n  input wire [4:0] writeRegisterMemWb;\n                   ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module main (clock, instr, reset);



  input wire clock;
  output wire reset;
  output reg [31:0] instr;

  reg [31:0] FOUR = 4;
  reg [3:0] ADD_CODE = 4'b0000;


  wire [31:0] readAddress;


  wire [31:0] instruction;
  wire [31:0] outInstruction;


  wire [31:0] readData1;
  wire [31:0] readData2;


  wire [31:0] signExtendWire;


  wire [3:0] aluControlWire;


  wire [31:0] readDataMemory;


  wire [4:0] mux1;
  wire [31:0] mux2;
  wire [31:0] mux3;
  wire [31:0] mux4;
  wire [31:0] muxA;


  wire pcSrc;


  wire [31:0] alu1;
  wire alu1Zero;
  wire [31:0] alu2;
  wire [31:0] alu3;
  wire [31:0] outPc;


  wire [31:0] alu3Input;
  wire [31:0] muxUla;


  wire helper;


  wire [3:0] exControl;
  wire [2:0] memControl;
  wire [1:0] wbControl;


  wire regDest, hzdRegDest;
  wire [1:0] aluOp;
  wire [1:0] hzdAluOp;
  wire aluSrc, hzdAluSrc;
  wire branch;
  wire memRead;
  wire memWrite;
  wire memToReg;
  wire regWrite;
  wire [31:0] readDataIdEx1;
  wire [31:0] readDataIdEx2;
  wire [31:0] signExtendIdEx;
  wire [4:0] rd;
  wire [4:0] rt;
  wire [4:0] rs;
  wire [31:0] ifId;

  wire [2:0] memControlIdEx;
  wire [2:0] hzdMemControlIdEx;
  wire [1:0] wbControlIdEx;
  wire [1:0] hzdWbControlIdEx;



  wire [1:0] wbControlExMem;
  wire branchExMem;
  wire memReadExMem;
  wire memWriteExMem;

  wire [31:0] aluResult;
  wire [31:0] aluZero;
  wire [31:0] addResult;
  wire [31:0] registerData;
  wire [4:0] writeRegister;


  wire hzdMuxControl, hzdPCWrite, hzdIFIDWrite;


  input wire regWriteMemWb;
  input wire memToRegMemWb;

  input wire [31:0] readDataMemoryMemWb;
  input wire [31:0] aluResultMemWb;
  input wire [4:0] writeRegisterMemWb;


  wire [1:0] fowardA;
  wire [1:0] fowardB;



   pc PC (
    .nextAddress(mux4),
    .clock(clock),
    .readAddress(readAddress),
    .hzdWrite(hzdPcWrite)
   );









  instructionMemory IM(
    .reset(reset),
    .readAddress(readAddress),
    .instruction(instruction)
  );


  ifId IFID(

    .clock(clock),
    .hzdWrite(hzdIfIdWrite),
    .pc(alu3),
    .instruction(instruction),


    .outPc(outPc),
    .outInstruction(outInstruction)
  );


  muxHazard MuxHazard (


    .control(hzdMuxControl),
    .regDest(exControl[3]),
    .aluOp(exControl[2:1]),
    .aluSrc(exControl[0]),

    .memControlIdEx(memControlIdEx),

    .wbControlIdEx(wbControlIdEx),



    .hzdRegDest(hzdRegDest),
    .hzdAluOp(hzdAluOp),
    .hzdAluSrc(hzdAluSrc),


    .hzdMemControlIdEx(hzdMemControlIdEx),

    .hzdWbControlIdEx(hzdWbControlIdEx)
  );


  hazardUnit HazardUnit(
    .reset(reset),
    .rt(rt),
    .memRead(memControlIdEx[1]),
    .instruction(outInstruction),
    .controller(hzdMuxControl),
    .hzdPcWrite(hzdPcWrite),
    .hzdIfIdWrite(hzdIfIdWrite)
  );


  instructionControl IC(
    .opCode(outInstruction[31:26]),
    .exControl(exControl),
    .memControl(memControl),
    .wbControl(wbControl)
  );


  registers REGS(
    .regWrite(regWrite),
    .register1(outInstruction[25:21]),
    .register2(outInstruction[20:16]),
    .writeRegister(mux1),
    .writeData(mux2),
    .readData1(readData1),
    .readData2(readData2)
  );


  signExtend SIGNEXTEND(
    .entrada(outInstruction[15:0]),
    .saida(signExtendWire)
  );


  idEx ID_EX(
    .clock(clock),



    .regDestInput(hzdRegDest),
    .aluOpInput(hzdAluOp),
    .aluSrcInput(hzdAluSrc),


    .memControlInput(hzdMemControlIdEx),


    .wbControlInput(hzdWbControlIdEx),


    .readData1Input(readData1),
    .readData2Input(readData2),
    .signExtendWireInput(signExtendWire),
    .rdInput(outInstruction[15:11]),
    .rtInput(outInstruction[20:16]),
    .rsInput(outInstruction[25:21]),
    .ifIdInput(outPc),



    .regDest(regDest),
    .aluOp(aluOp),
    .aluSrc(aluSrc),


    .memControlIdEx(memControlIdEx),


    .wbControlIdEx(wbControlIdEx),


    .readData1(readDataIdEx1),
    .readData2(readDataIdEx2),
    .signExtendWire(signExtendIdEx),
    .rd(rd),
    .rt(rt),
    .rs(rs),
    .ifId(ifId)
  );


  mux5Bits2 MUX1(
    .entrada1(rd),
    .entrada2(rt),
    .seletor(regDest),
    .saida(mux1)
  );


  mux32Bits3 MUX3(
    .entrada1(readData2),
    .entrada2(alu1),
    .entrada3(mux2),
    .seletor(fowardB),
    .saida(mux3)
  );


  aluControl ALUCONT(
    .aluOp(aluOp),
    .funct(outInstruction[5:0]),
    .saida(aluControlWire)
  );


  mux32Bits3 MUXULA(
    .entrada1(readData1),
    .entrada2(alu1),
    .entrada3(mux2),
    .seletor(fowardA),
    .saida(muxUla)
  );



  alu ALU1(
    .entrada1(muxUla),
    .entrada2(muxA),
    .unidadeControle(aluControlWire),
    .saida(alu1),
    .zero(alu1Zero)
  );


  fowarding FOWARDING(
    .clock(clock),


    .rs(rs),
    .rt(rt),


    .writeRegister(writeRegister),
    .regWrite(wbControlExMem[1]),


    .writeRegisterMemWb(writeRegisterMemWb),
    .regWriteMemWb(regWriteMemWb),



    .fowardA(fowardA),
    .fowardB(fowardB)
  );


  exMem EX_MEM(
    .clock(clock),



    .memControlInput(memControlIdEx),


    .wbControlInput(wbControlIdEx),


    .aluResultInput(alu1),
    .aluZeroInput(alu1Zero),
    .pcInput(alu3),
    .registerDataInput(readDataIdEx2),
    .writeRegisterInput(mux1),



    .wbControlExMem(wbControlExMem),
    .branch(branchExMem),
    .memRead(memReadExMem),
    .memWrite(memWriteExMem),

    .aluResult(aluResult),
    .aluZero(aluZero),
    .pc(addResult),
    .registerData(registerData),
    .writeRegister(writeRegister)
  );


  dataMemory DM(
    .address(aluResult),
    .writeData(registerData),
    .memRead(memReadExMem),
    .memWrite(memWriteExMem),
    .readData(readDataMemory)
  );


  memWb MEMWB(
    .clock(clock),


    .readDataMemoryInput(readDataMemory),
    .aluResultInput(aluResult),
    .writeRegisterInput(writeRegister),


    .regWrite(regWriteMemWb),
    .memToReg(memToRegMemWb),
    .readDataMemory(readDataMemoryMemWb),
    .aluResult(aluResultMemWb),
    .writeRegister(writeRegisterMemWb)
  );


  mux32Bits2 MUX2(
    .entrada1(readDataMemory),
    .entrada2(alu1),
    .seletor(memToReg),
    .saida(mux2)
  );


  assign pcSrc = (aluZero && branchExMem);

  shiftLeft Shift(
    .shift_input(signExtendIdEx),
    .shift_output(alu3Input)
  );


  alu ALU2(
    .entrada1(readAddress),
    .entrada2(FOUR),
    .unidadeControle(ADD_CODE),
    .saida(alu2),
    .zero(helper)
  );


  alu ALU3(
    .entrada1(alu2),
    .entrada2(alu3Input),
    .unidadeControle(ADD_CODE),
    .saida(alu3),
    .zero(helper)
  );


  mux32Bits2 MUX4(
    .entrada1(addResult),
    .entrada2(alu2),
    .seletor(pcSrc),
    .saida(mux4)
  );


  mux32Bits2 MUXA(
    .entrada1(alu3Input),
    .entrada2(mux3),
    .seletor(aluSrc),
    .saida(muxA)
  );

  always @(posedge clock) begin
    instr <= outInstruction;
  end
endmodule
module main (clock, instr, reset);




  input wire clock;
  output wire reset;
  output reg [31:0] instr;

  reg [31:0] FOUR = 4;
  reg [3:0] ADD_CODE = 4'b0000;


  wire [31:0] readAddress;


  wire [31:0] instruction;
  wire [31:0] outInstruction;


  wire [31:0] readData1;
  wire [31:0] readData2;


  wire [31:0] signExtendWire;


  wire [3:0] aluControlWire;


  wire [31:0] readDataMemory;


  wire [4:0] mux1;
  wire [31:0] mux2;
  wire [31:0] mux3;
  wire [31:0] mux4;
  wire [31:0] muxA;


  wire pcSrc;


  wire [31:0] alu1;
  wire alu1Zero;
  wire [31:0] alu2;
  wire [31:0] alu3;
  wire [31:0] outPc;


  wire [31:0] alu3Input;
  wire [31:0] muxUla;


  wire helper;


  wire [3:0] exControl;
  wire [2:0] memControl;
  wire [1:0] wbControl;


  wire regDest, hzdRegDest;
  wire [1:0] aluOp;
  wire [1:0] hzdAluOp;
  wire aluSrc, hzdAluSrc;
  wire branch;
  wire memRead;
  wire memWrite;
  wire memToReg;
  wire regWrite;
  wire [31:0] readDataIdEx1;
  wire [31:0] readDataIdEx2;
  wire [31:0] signExtendIdEx;
  wire [4:0] rd;
  wire [4:0] rt;
  wire [4:0] rs;
  wire [31:0] ifId;

  wire [2:0] memControlIdEx;
  wire [2:0] hzdMemControlIdEx;
  wire [1:0] wbControlIdEx;
  wire [1:0] hzdWbControlIdEx;



  wire [1:0] wbControlExMem;
  wire branchExMem;
  wire memReadExMem;
  wire memWriteExMem;

  wire [31:0] aluResult;
  wire [31:0] aluZero;
  wire [31:0] addResult;
  wire [31:0] registerData;
  wire [4:0] writeRegister;


  wire hzdMuxControl, hzdPCWrite, hzdIFIDWrite;


  input wire regWriteMemWb;
  input wire memToRegMemWb;

  input wire [31:0] readDataMemoryMemWb;
  input wire [31:0] aluResultMemWb;
  input wire [4:0] writeRegisterMemWb;


  wire [1:0] fowardA;
  wire [1:0] fowardB;



   pc PC (
    .nextAddress(mux4),
    .clock(clock),
    .readAddress(readAddress),
    .hzdWrite(hzdPcWrite)
   );









  instructionMemory IM(
    .reset(reset),
    .readAddress(readAddress),
    .instruction(instruction)
  );


  ifId IFID(

    .clock(clock),
    .hzdWrite(hzdIfIdWrite),
    .pc(alu3),
    .instruction(instruction),


    .outPc(outPc),
    .outInstruction(outInstruction)
  );


  muxHazard MuxHazard (


    .control(hzdMuxControl),
    .regDest(exControl[3]),
    .aluOp(exControl[2:1]),
    .aluSrc(exControl[0]),

    .memControlIdEx(memControlIdEx),

    .wbControlIdEx(wbControlIdEx),



    .hzdRegDest(hzdRegDest),
    .hzdAluOp(hzdAluOp),
    .hzdAluSrc(hzdAluSrc),


    .hzdMemControlIdEx(hzdMemControlIdEx),

    .hzdWbControlIdEx(hzdWbControlIdEx)
  );


  hazardUnit HazardUnit(
    .reset(reset),
    .rt(rt),
    .memRead(memControlIdEx[1]),
    .instruction(outInstruction),
    .controller(hzdMuxControl),
    .hzdPcWrite(hzdPcWrite),
    .hzdIfIdWrite(hzdIfIdWrite)
  );


  instructionControl IC(
    .opCode(outInstruction[31:26]),
    .exControl(exControl),
    .memControl(memControl),
    .wbControl(wbControl)
  );


  registers REGS(
    .regWrite(regWrite),
    .register1(outInstruction[25:21]),
    .register2(outInstruction[20:16]),
    .writeRegister(mux1),
    .writeData(mux2),
    .readData1(readData1),
    .readData2(readData2)
  );


  signExtend SIGNEXTEND(
    .entrada(outInstruction[15:0]),
    .saida(signExtendWire)
  );


  idEx ID_EX(
    .clock(clock),



    .regDestInput(hzdRegDest),
    .aluOpInput(hzdAluOp),
    .aluSrcInput(hzdAluSrc),


    .memControlInput(hzdMemControlIdEx),


    .wbControlInput(hzdWbControlIdEx),


    .readData1Input(readData1),
    .readData2Input(readData2),
    .signExtendWireInput(signExtendWire),
    .rdInput(outInstruction[15:11]),
    .rtInput(outInstruction[20:16]),
    .rsInput(outInstruction[25:21]),
    .ifIdInput(outPc),



    .regDest(regDest),
    .aluOp(aluOp),
    .aluSrc(aluSrc),


    .memControlIdEx(memControlIdEx),


    .wbControlIdEx(wbControlIdEx),


    .readData1(readDataIdEx1),
    .readData2(readDataIdEx2),
    .signExtendWire(signExtendIdEx),
    .rd(rd),
    .rt(rt),
    .rs(rs),
    .ifId(ifId)
  );


  mux5Bits2 MUX1(
    .entrada1(rd),
    .entrada2(rt),
    .seletor(regDest),
    .saida(mux1)
  );


  mux32Bits3 MUX3(
    .entrada1(readData2),
    .entrada2(alu1),
    .entrada3(mux2),
    .seletor(fowardB),
    .saida(mux3)
  );


  aluControl ALUCONT(
    .aluOp(aluOp),
    .funct(outInstruction[5:0]),
    .saida(aluControlWire)
  );


  mux32Bits3 MUXULA(
    .entrada1(readData1),
    .entrada2(alu1),
    .entrada3(mux2),
    .seletor(fowardA),
    .saida(muxUla)
  );



  alu ALU1(
    .entrada1(muxUla),
    .entrada2(muxA),
    .unidadeControle(aluControlWire),
    .saida(alu1),
    .zero(alu1Zero)
  );


  fowarding FOWARDING(
    .clock(clock),


    .rs(rs),
    .rt(rt),


    .writeRegister(writeRegister),
    .regWrite(wbControlExMem[1]),


    .writeRegisterMemWb(writeRegisterMemWb),
    .regWriteMemWb(regWriteMemWb),



    .fowardA(fowardA),
    .fowardB(fowardB)
  );


  exMem EX_MEM(
    .clock(clock),



    .memControlInput(memControlIdEx),


    .wbControlInput(wbControlIdEx),


    .aluResultInput(alu1),
    .aluZeroInput(alu1Zero),
    .pcInput(alu3),
    .registerDataInput(readDataIdEx2),
    .writeRegisterInput(mux1),



    .wbControlExMem(wbControlExMem),
    .branch(branchExMem),
    .memRead(memReadExMem),
    .memWrite(memWriteExMem),

    .aluResult(aluResult),
    .aluZero(aluZero),
    .pc(addResult),
    .registerData(registerData),
    .writeRegister(writeRegister)
  );


  dataMemory DM(
    .address(aluResult),
    .writeData(registerData),
    .memRead(memReadExMem),
    .memWrite(memWriteExMem),
    .readData(readDataMemory)
  );


  memWb MEMWB(
    .clock(clock),


    .readDataMemoryInput(readDataMemory),
    .aluResultInput(aluResult),
    .writeRegisterInput(writeRegister),


    .regWrite(regWriteMemWb),
    .memToReg(memToRegMemWb),
    .readDataMemory(readDataMemoryMemWb),
    .aluResult(aluResultMemWb),
    .writeRegister(writeRegisterMemWb)
  );


  mux32Bits2 MUX2(
    .entrada1(readDataMemory),
    .entrada2(alu1),
    .seletor(memToReg),
    .saida(mux2)
  );


  assign pcSrc = (aluZero && branchExMem);

  shiftLeft Shift(
    .shift_input(signExtendIdEx),
    .shift_output(alu3Input)
  );


  alu ALU2(
    .entrada1(readAddress),
    .entrada2(FOUR),
    .unidadeControle(ADD_CODE),
    .saida(alu2),
    .zero(helper)
  );


  alu ALU3(
    .entrada1(alu2),
    .entrada2(alu3Input),
    .unidadeControle(ADD_CODE),
    .saida(alu3),
    .zero(helper)
  );


  mux32Bits2 MUX4(
    .entrada1(addResult),
    .entrada2(alu2),
    .seletor(pcSrc),
    .saida(mux4)
  );


  mux32Bits2 MUXA(
    .entrada1(alu3Input),
    .entrada2(mux3),
    .seletor(aluSrc),
    .saida(muxA)
  );

  always @(posedge clock) begin
    instr <= outInstruction;
  end
endmodule