data/full_repos/permissive/143278/ivltests/br987.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br987.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br987.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/br987.v:22: Cannot find file containing module: \'bug5\'\nbug5 dut(clk, trig, data_o);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/bug5\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/bug5.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/bug5.sv\n             bug5\n             bug5.v\n             bug5.sv\n             obj_dir/bug5\n             obj_dir/bug5.v\n             obj_dir/bug5.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module br987_test;
logic clk, trig, data_o;
bug5 dut(clk, trig, data_o);

initial begin
    trig = 1;
    clk = 0;
    #1 clk = ~clk;
    #1 clk = ~clk;
    $display("PASSED");
end

endmodule
module br987_test;

logic clk, trig, data_o;
bug5 dut(clk, trig, data_o);

initial begin
    trig = 1;
    clk = 0;
    #1 clk = ~clk;
    #1 clk = ~clk;
    $display("PASSED");
end

endmodule