data/full_repos/permissive/129155059/03-library/modulos_estructural.v
 line:7: before: ":"
1: b'%Warning-STMTDLY: data/full_repos/permissive/129155059/03-library/modulos_estructural.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #14;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/129155059/03-library/modulos_estructural.v:33: Multiple top level modules\n                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                           : ... Top module \'NOR\'\nmodule NOR (\n       ^~~\n                                                                                           : ... Top module \'NOT\'\nmodule NOT (\n       ^~~\n                                                                                           : ... Top module \'mux2a1\'\nmodule mux2a1(\n       ^~~~~~\n                                                                                           : ... Top module \'FLOP_D\'\nmodule FLOP_D (\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/129155059/03-library/modulos_estructural.v:52: Signal definition not found, creating implicitly: \'x\'\n NAND   nand1(Sel,1\'b1,x);\n                       ^\n%Warning-IMPLICIT: data/full_repos/permissive/129155059/03-library/modulos_estructural.v:53: Signal definition not found, creating implicitly: \'z\'\n NAND   nand2(In2,Sel,z);\n                      ^\n%Warning-IMPLICIT: data/full_repos/permissive/129155059/03-library/modulos_estructural.v:54: Signal definition not found, creating implicitly: \'y\'\n NAND   nand3(x,In1,y);\n                    ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FLOP_D (
	input D,
	input Clk,
	output reg Q);

	real time_a;
	real time_b;
	real delta_ab;
	integer exep = 0;

	always @ ( posedge D or negedge D ) begin
		time_a = $realtime;
		$display("flanco: %d",time_b);
		$display("cambio: %d",time_a);
		$display("delta: %d",time_b-time_a);
		if (time_a != 0 && time_b != 0 ) begin
			if ((0 <= (time_b-time_a))&&((time_b-time_a) < 20)&&(exep == 0)) begin
				$display("Delta %d, Se ha violado el tiempo de septup del flip-flop en el tiempo %d, con el flanco %d se va a proceder en forma de exepcion",delta_ab,time_a,time_b);
				exep <= 1;
			end else if ((-15.0 < (time_b-time_a))&& ((time_b-time_a) < 0) && (exep == 0)) begin
				$display("Delta %d, Se ha violado el tiempo de hold del flip-flop %d, con el flanco %d, se va proceder en forma de exepcion", delta_ab,time_a,time_b);
				exep <= 1;
			end
		end
	end



	always @ (posedge Clk) begin
		time_b = $realtime;
		$display("flanco: %d",time_b);
		$display("cambio: %d",time_a);
		$display("delta: %d",time_b-time_a);
		if (time_a != 0 && time_b !=0 ) begin
			if ((0 <= (time_b-time_a))&&((time_b-time_a) < 20)&&(exep == 0)) begin
				$display("Delta %d, Se ha violado el tiempo de septup del flip-flop en el tiempo %d, con el flanco %d se va a proceder en forma de exepcion",delta_ab,time_a,time_b);
				exep <= 1;
			end else if ((-15.0 < (time_b-time_a))&& ((time_b-time_a) < 0) && (exep == 0)) begin
				$display("Delta %d, Se ha violado el tiempo de hold del flip-flop %d, con el flanco %d, se va proceder en forma de exepcion", delta_ab,time_a,time_b);
				exep <= 1;
			end
		end

		#14;
		Q <= D;



	end





endmodule
module FLOP_D (
	input D,
	input Clk,
	output reg Q);


	real time_a;
	real time_b;
	real delta_ab;
	integer exep = 0;

	always @ ( posedge D or negedge D ) begin
		time_a = $realtime;
		$display("flanco: %d",time_b);
		$display("cambio: %d",time_a);
		$display("delta: %d",time_b-time_a);
		if (time_a != 0 && time_b != 0 ) begin
			if ((0 <= (time_b-time_a))&&((time_b-time_a) < 20)&&(exep == 0)) begin
				$display("Delta %d, Se ha violado el tiempo de septup del flip-flop en el tiempo %d, con el flanco %d se va a proceder en forma de exepcion",delta_ab,time_a,time_b);
				exep <= 1;
			end else if ((-15.0 < (time_b-time_a))&& ((time_b-time_a) < 0) && (exep == 0)) begin
				$display("Delta %d, Se ha violado el tiempo de hold del flip-flop %d, con el flanco %d, se va proceder en forma de exepcion", delta_ab,time_a,time_b);
				exep <= 1;
			end
		end
	end



	always @ (posedge Clk) begin
		time_b = $realtime;
		$display("flanco: %d",time_b);
		$display("cambio: %d",time_a);
		$display("delta: %d",time_b-time_a);
		if (time_a != 0 && time_b !=0 ) begin
			if ((0 <= (time_b-time_a))&&((time_b-time_a) < 20)&&(exep == 0)) begin
				$display("Delta %d, Se ha violado el tiempo de septup del flip-flop en el tiempo %d, con el flanco %d se va a proceder en forma de exepcion",delta_ab,time_a,time_b);
				exep <= 1;
			end else if ((-15.0 < (time_b-time_a))&& ((time_b-time_a) < 0) && (exep == 0)) begin
				$display("Delta %d, Se ha violado el tiempo de hold del flip-flop %d, con el flanco %d, se va proceder en forma de exepcion", delta_ab,time_a,time_b);
				exep <= 1;
			end
		end

		#14;
		Q <= D;



	end





endmodule