data/full_repos/permissive/143278/ivltests/tern4.v
data/verilator_xmls/14e2750b-1979-48af-9754-b7bc33ff0caf.xml
module main;

   reg out, c, a, b;

   initial begin
      c = 0;
      a = 0;
      b = 1;
      out = c ? (a & b) : b;

      $display("%b = %b ? (%b & %b) : %b;", out, c, a, b, b);
      if (out !== 1) begin
	 $display("FAILED -- out=%b result is incorrect!", out);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   reg out, c, a, b;

   initial begin
      c = 0;
      a = 0;
      b = 1;
      out = c ? (a & b) : b;

      $display("%b = %b ? (%b & %b) : %b;", out, c, a, b, b);
      if (out !== 1) begin
	 $display("FAILED -- out=%b result is incorrect!", out);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule