data/full_repos/permissive/201488448/3_verification/2_tb/4_tb2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/201488448/3_verification/2_tb/4_tb2.v:6: Unsupported: Ignoring delay on this delayed statement.\n        #0 clk=0;in=0;s=3\'d2;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/201488448/3_verification/2_tb/4_tb2.v:7: Unsupported: Ignoring delay on this delayed statement.\n        #10 s=3\'d6;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201488448/3_verification/2_tb/4_tb2.v:8: Unsupported: Ignoring delay on this delayed statement.\n        #10 s=3\'d2;in=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201488448/3_verification/2_tb/4_tb2.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #10 s=3\'d7;in=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201488448/3_verification/2_tb/4_tb2.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #10 s=3\'d0;in=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201488448/3_verification/2_tb/4_tb2.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #30 in=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/201488448/3_verification/2_tb/4_tb2.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk=~clk; \n        ^\n%Error: data/full_repos/permissive/201488448/3_verification/2_tb/4_tb2.v:18: Cannot find file containing module: \'q7\'\n    q7 q(clk,in,s,out);\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/201488448/3_verification/2_tb,data/full_repos/permissive/201488448/q7\n             data/full_repos/permissive/201488448/3_verification/2_tb,data/full_repos/permissive/201488448/q7.v\n             data/full_repos/permissive/201488448/3_verification/2_tb,data/full_repos/permissive/201488448/q7.sv\n             q7\n             q7.v\n             q7.sv\n             obj_dir/q7\n             obj_dir/q7.v\n             obj_dir/q7.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_module();
	reg clk,in,out;
    reg	[2:0]	s;
    
    initial begin
       	#0	clk=0;in=0;s=3'd2;
        #10	s=3'd6;
        #10	s=3'd2;in=1;
        #10	s=3'd7;in=0;
        #10	s=3'd0;in=1;
        #30	in=0;
    end
    
    always begin
       	#5	clk=~clk; 
    end
    
    q7 q(clk,in,s,out);
    
endmodule
module top_module();

	reg clk,in,out;
    reg	[2:0]	s;
    
    initial begin
       	#0	clk=0;in=0;s=3'd2;
        #10	s=3'd6;
        #10	s=3'd2;in=1;
        #10	s=3'd7;in=0;
        #10	s=3'd0;in=1;
        #30	in=0;
    end
    
    always begin
       	#5	clk=~clk; 
    end
    
    q7 q(clk,in,s,out);
    
endmodule