data/full_repos/permissive/197042892/hardware/17.srcs/DAC_spi_master.v
1: b'%Warning-WIDTH: data/full_repos/permissive/197042892/hardware/17.srcs/DAC_spi_master.v:133: Operator AND expects 24 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                          : ... In instance spi_controller\n   din = (full_command_one_period >> shift_counter_helper) & 1\'b1;\n                                                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/197042892/hardware/17.srcs/DAC_spi_master.v:133: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 24 bits.\n                                                                                          : ... In instance spi_controller\n   din = (full_command_one_period >> shift_counter_helper) & 1\'b1;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/197042892/hardware/17.srcs/DAC_spi_master.v:140: Operator AND expects 24 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                          : ... In instance spi_controller\n  din = (full_command_one_period >> shift_counter_helper) & 1\'b1;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/197042892/hardware/17.srcs/DAC_spi_master.v:140: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 24 bits.\n                                                                                          : ... In instance spi_controller\n  din = (full_command_one_period >> shift_counter_helper) & 1\'b1;\n      ^\n%Error: Exiting due to 4 warning(s)\n'
module spi_controller(
	input  wire			clk,
	input  wire			rst,
	input  wire [2:0]	mode_pc,
	input  wire 		clear_request,
	input  wire			pipe,
	input  wire [15:0]	data_from_memory,
	input  wire [15:0]	data_from_user,
	input  wire 		sdo_bit,
	input  wire [1:0]	counter2spi,
	input  wire 		no_trig,
	input  wire 		channel_disable,
	input  wire 		channel_enable,

	output wire			clear,
	output reg			latch,
	output wire			sclk,
	output reg			din,
	output wire			spi_pipe_clk,
	output wire [4:0] 	alarm_out,
	output reg			config_counter,
	output wire			channel_is_disable
    );

wire [7:0] 	address_byte;
wire [23:0] full_command;
reg	 [23:0] full_command_one_period;
reg  [23:0] full_command_one_period_prev;
reg  [4:0] 	counter;
wire [4:0]	shift_counter_helper;
wire [2:0] 	mode;
reg			output_en;
reg			output_en_proposed;
wire		next_output_en;
wire		next_output_en_proposed;
reg	 [23:0] alarm;

assign shift_counter_helper = ~counter + 5'd24;
assign next_output_en = output_en;
assign next_output_en_proposed = output_en_proposed;
assign channel_is_disable = ~output_en;
assign alarm_out = alarm[4:0];
assign clear = clear_request;
assign sclk = ((counter >= 5'd24) | (full_command_one_period == full_command_one_period_prev) )? 0 :clk;

assign mode = ((output_en != output_en_proposed) && (output_en_proposed == 1'b0)) ? 3'b110
			: ((output_en != output_en_proposed) && (output_en_proposed == 1'b1)) ? 3'b011
			: (counter2spi == 2) ? 3'b111
			: (counter2spi == 3) ? 3'b000
			: mode_pc;

assign address_byte = (mode == 3'b001) ? 8'b00000001

					: (mode == 3'b011) ? 8'b01010101
					: (mode == 3'b110) ? 8'b01010101
					: (mode == 3'b100) ? 8'b01010110
					: (mode == 3'b101) ? 8'b01010111

					: (mode == 3'b010) ? 8'b01011001
					: (mode == 3'b111) ? 8'b00000010
					: 8'b0;			
															
assign full_command =
					  (mode == 3'b010) ?  {address_byte, 16'b1111111111111111}
					: (mode == 3'b100) ?  {address_byte, 16'b0000000000000001}
					: (mode == 3'b011) ?  {address_byte, 16'b0001000000000110}
					: (mode == 3'b110) ?  {address_byte, 16'b0000000000000110}
					: (mode == 3'b101) ?  {address_byte, 16'b0000000000000000}
					: (mode == 3'b000) ?  {address_byte, 16'b0000000000000000}
					: (mode == 3'b111) ?  {address_byte, 16'b0000000000000000}
					:  pipe ? {address_byte, data_from_memory} 
					: {address_byte, data_from_user};

assign spi_pipe_clk = (counter == 5'd29);

always @ (posedge clk) begin
	if (full_command_one_period_prev == 24'h020000) begin
		if (counter < 5'd24) begin
			alarm[5'd23-counter] = sdo_bit;
		end
	end
end

always @ (negedge clk) begin
	if (rst) begin
		output_en_proposed <= 1'b0;
	end else if (channel_disable) begin
		output_en_proposed <= 1'b0;
	end else if (channel_enable) begin
		output_en_proposed <= 1'b1;
	end else if (output_en && no_trig) begin
		output_en_proposed <= 1'b0;
	end else begin
		output_en_proposed <= next_output_en_proposed;
	end
end

always @ (negedge clk) begin
	if(rst | channel_disable) begin
		counter <= 0;
	end else begin
		counter <= counter + 1;
	end
end

always @ (negedge clk) begin
	if (full_command_one_period == full_command_one_period_prev) begin
		latch <= 1'b0;
	end else begin 
		if(counter >= 5'd23) begin
			if(counter < 5'd29) begin
				latch <= 1'b1;
			end else begin
				latch <= 1'b0;
			end
		end else begin
			latch <= 1'b0;
		end
	end
end

always @ (*) begin
	if(counter >= 5'd23) begin
		if(counter < 5'd24) begin
			din = (full_command_one_period >> shift_counter_helper) & 1'b1;
		end else if(counter < 5'd29) begin
			din = 1'b0;
		end else begin
			din = 1'b0;
		end
	end else begin
		din = (full_command_one_period >> shift_counter_helper) & 1'b1;
	end
end

always @ (negedge clk) begin
	if (counter == 5'd31) begin
		full_command_one_period <= full_command;
		full_command_one_period_prev <= full_command_one_period;
	end

	if (rst) begin
		output_en <= 1'b0;
	end else if (full_command_one_period == 24'h551006) begin
		output_en <= 1'b1;
	end else if (full_command_one_period == 24'h550006) begin
		output_en <= 1'b0;
	end else begin
		output_en <= next_output_en;
	end
	
	if (counter == 5'd31 && full_command_one_period == 24'h551006) begin
		config_counter <= 1'b1;
	end else begin
		config_counter <= 1'b0;
	end
end
		
endmodule
module spi_controller(
	input  wire			clk,
	input  wire			rst,
	input  wire [2:0]	mode_pc,
	input  wire 		clear_request,
	input  wire			pipe,
	input  wire [15:0]	data_from_memory,
	input  wire [15:0]	data_from_user,
	input  wire 		sdo_bit,
	input  wire [1:0]	counter2spi,
	input  wire 		no_trig,
	input  wire 		channel_disable,
	input  wire 		channel_enable,

	output wire			clear,
	output reg			latch,
	output wire			sclk,
	output reg			din,
	output wire			spi_pipe_clk,
	output wire [4:0] 	alarm_out,
	output reg			config_counter,
	output wire			channel_is_disable
    );


wire [7:0] 	address_byte;
wire [23:0] full_command;
reg	 [23:0] full_command_one_period;
reg  [23:0] full_command_one_period_prev;
reg  [4:0] 	counter;
wire [4:0]	shift_counter_helper;
wire [2:0] 	mode;
reg			output_en;
reg			output_en_proposed;
wire		next_output_en;
wire		next_output_en_proposed;
reg	 [23:0] alarm;

assign shift_counter_helper = ~counter + 5'd24;
assign next_output_en = output_en;
assign next_output_en_proposed = output_en_proposed;
assign channel_is_disable = ~output_en;
assign alarm_out = alarm[4:0];
assign clear = clear_request;
assign sclk = ((counter >= 5'd24) | (full_command_one_period == full_command_one_period_prev) )? 0 :clk;

assign mode = ((output_en != output_en_proposed) && (output_en_proposed == 1'b0)) ? 3'b110
			: ((output_en != output_en_proposed) && (output_en_proposed == 1'b1)) ? 3'b011
			: (counter2spi == 2) ? 3'b111
			: (counter2spi == 3) ? 3'b000
			: mode_pc;

assign address_byte = (mode == 3'b001) ? 8'b00000001

					: (mode == 3'b011) ? 8'b01010101
					: (mode == 3'b110) ? 8'b01010101
					: (mode == 3'b100) ? 8'b01010110
					: (mode == 3'b101) ? 8'b01010111

					: (mode == 3'b010) ? 8'b01011001
					: (mode == 3'b111) ? 8'b00000010
					: 8'b0;			
															
assign full_command =
					  (mode == 3'b010) ?  {address_byte, 16'b1111111111111111}
					: (mode == 3'b100) ?  {address_byte, 16'b0000000000000001}
					: (mode == 3'b011) ?  {address_byte, 16'b0001000000000110}
					: (mode == 3'b110) ?  {address_byte, 16'b0000000000000110}
					: (mode == 3'b101) ?  {address_byte, 16'b0000000000000000}
					: (mode == 3'b000) ?  {address_byte, 16'b0000000000000000}
					: (mode == 3'b111) ?  {address_byte, 16'b0000000000000000}
					:  pipe ? {address_byte, data_from_memory} 
					: {address_byte, data_from_user};

assign spi_pipe_clk = (counter == 5'd29);

always @ (posedge clk) begin
	if (full_command_one_period_prev == 24'h020000) begin
		if (counter < 5'd24) begin
			alarm[5'd23-counter] = sdo_bit;
		end
	end
end

always @ (negedge clk) begin
	if (rst) begin
		output_en_proposed <= 1'b0;
	end else if (channel_disable) begin
		output_en_proposed <= 1'b0;
	end else if (channel_enable) begin
		output_en_proposed <= 1'b1;
	end else if (output_en && no_trig) begin
		output_en_proposed <= 1'b0;
	end else begin
		output_en_proposed <= next_output_en_proposed;
	end
end

always @ (negedge clk) begin
	if(rst | channel_disable) begin
		counter <= 0;
	end else begin
		counter <= counter + 1;
	end
end

always @ (negedge clk) begin
	if (full_command_one_period == full_command_one_period_prev) begin
		latch <= 1'b0;
	end else begin 
		if(counter >= 5'd23) begin
			if(counter < 5'd29) begin
				latch <= 1'b1;
			end else begin
				latch <= 1'b0;
			end
		end else begin
			latch <= 1'b0;
		end
	end
end

always @ (*) begin
	if(counter >= 5'd23) begin
		if(counter < 5'd24) begin
			din = (full_command_one_period >> shift_counter_helper) & 1'b1;
		end else if(counter < 5'd29) begin
			din = 1'b0;
		end else begin
			din = 1'b0;
		end
	end else begin
		din = (full_command_one_period >> shift_counter_helper) & 1'b1;
	end
end

always @ (negedge clk) begin
	if (counter == 5'd31) begin
		full_command_one_period <= full_command;
		full_command_one_period_prev <= full_command_one_period;
	end

	if (rst) begin
		output_en <= 1'b0;
	end else if (full_command_one_period == 24'h551006) begin
		output_en <= 1'b1;
	end else if (full_command_one_period == 24'h550006) begin
		output_en <= 1'b0;
	end else begin
		output_en <= next_output_en;
	end
	
	if (counter == 5'd31 && full_command_one_period == 24'h551006) begin
		config_counter <= 1'b1;
	end else begin
		config_counter <= 1'b0;
	end
end
		
endmodule