data/full_repos/permissive/143278/ivltests/pr2233192.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2233192.v:19: Unsupported: Ignoring delay on this delayed statement.\n #1 if (remainder !== 32\'hffffffff) begin\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2233192.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 if (rrem !== 32\'hffffffff) begin\n ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bug05_integerRem;

reg passed;

reg signed[31:0] reg0;
reg signed[31:0] reg1;
reg signed[31:0] rrem;
wire signed[31:0] dividend=reg0;
wire signed[31:0] divisor=reg1;
wire signed[31:0] remainder;

assign remainder= dividend%divisor;

initial begin
	passed = 1'b1;
	reg0=32'hffffffff;
	reg1=32'h0d1f0796;

	#1 if (remainder !== 32'hffffffff) begin
		$display("Failed: CA remainder, expected 32'hffffffff, got %h",
		         remainder);
		passed = 1'b0;
	end

        rrem = reg0 % reg1;
	#1 if (rrem !== 32'hffffffff) begin
		$display("Failed: remainder, expected 32'hffffffff, got %h",
		         rrem);
		passed = 1'b0;
	end

	if (passed) $display("PASSED");
end

endmodule
module bug05_integerRem;


reg passed;

reg signed[31:0] reg0;
reg signed[31:0] reg1;
reg signed[31:0] rrem;
wire signed[31:0] dividend=reg0;
wire signed[31:0] divisor=reg1;
wire signed[31:0] remainder;

assign remainder= dividend%divisor;

initial begin
	passed = 1'b1;
	reg0=32'hffffffff;
	reg1=32'h0d1f0796;

	#1 if (remainder !== 32'hffffffff) begin
		$display("Failed: CA remainder, expected 32'hffffffff, got %h",
		         remainder);
		passed = 1'b0;
	end

        rrem = reg0 % reg1;
	#1 if (rrem !== 32'hffffffff) begin
		$display("Failed: remainder, expected 32'hffffffff, got %h",
		         rrem);
		passed = 1'b0;
	end

	if (passed) $display("PASSED");
end

endmodule