data/full_repos/permissive/193419875/src/ProgramCounter.v
data/verilator_xmls/81265b0e-8bfe-43a5-81cf-8cfd56d5b9a6.xml
module ProgramCounter
(
	input CLOCK,
	input RESET,
	input PCWire,
	input [63:0] programCounter_in,
	output reg [63:0] programCounter_out
);

	always @(posedge CLOCK) begin
		if(PCWire) begin
			if (programCounter_in === 64'bx) begin
				programCounter_out  <= 0;
			end	else begin
				programCounter_out <= programCounter_in;
			end
		end
	end

	always @(RESET) begin
		programCounter_out = 0;
	end
endmodule
module ProgramCounter
(
	input CLOCK,
	input RESET,
	input PCWire,
	input [63:0] programCounter_in,
	output reg [63:0] programCounter_out
);


	always @(posedge CLOCK) begin
		if(PCWire) begin
			if (programCounter_in === 64'bx) begin
				programCounter_out  <= 0;
			end	else begin
				programCounter_out <= programCounter_in;
			end
		end
	end

	always @(RESET) begin
		programCounter_out = 0;
	end
endmodule