data/full_repos/permissive/164484080/rtl/rom.v
1: b'%Error: data/full_repos/permissive/164484080/rtl/rom.v:22: Cannot find include file: config.v\n`include "config.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164484080/rtl,data/full_repos/permissive/164484080/config.v\n             data/full_repos/permissive/164484080/rtl,data/full_repos/permissive/164484080/config.v.v\n             data/full_repos/permissive/164484080/rtl,data/full_repos/permissive/164484080/config.v.sv\n             config.v\n             config.v.v\n             config.v.sv\n             obj_dir/config.v\n             obj_dir/config.v.v\n             obj_dir/config.v.sv\n%Error: data/full_repos/permissive/164484080/rtl/rom.v:23: Cannot find include file: wishbone.v\n`include "wishbone.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/rom.v:24: Cannot find include file: utils.v\n`include "utils.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/rom.v:33: Define or directive not defined: \'`WB_SLAVE_PORT_SIGNALS\'\n    `WB_SLAVE_PORT_SIGNALS(rom_)\n    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/rom.v:33: syntax error, unexpected \'(\', expecting \'[\'\n    `WB_SLAVE_PORT_SIGNALS(rom_)\n                           ^~~~\n%Error: data/full_repos/permissive/164484080/rtl/rom.v:42: Define or directive not defined: \'`DAT_WIDTH\'\n    reg [`DAT_WIDTH-1:0] r_dat_o;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/rom.v:46: syntax error, unexpected assign\n    assign rom_ack_o = rom_stb_i ? r_ack : 1\'b0;\n    ^~~~~~\n%Error: Exiting due to 7 error(s)\n'
module rom (
    input rst_i,
    input clk_i,

    `WB_SLAVE_PORT_SIGNALS(rom_)
);



    parameter INSTRUCTIONS = 128;
    parameter GRANULE = 8;

    reg state = `STATE_IDLE;
    reg [`DAT_WIDTH-1:0] r_dat_o;
    reg r_ack = 1'h0;
    reg r_err = 1'h0;

    assign rom_ack_o = rom_stb_i ? r_ack : 1'b0;
    assign rom_err_o = rom_stb_i ? r_err : 1'b0;
    assign rom_dat_o = r_dat_o;

    always @(*) begin
        casex (rom_adr_i)
16'h0000: r_dat_o = 64'h0287800010001018;
16'h0008: r_dat_o = 64'h1687800000008000;
16'h0010: r_dat_o = 64'h0286c01002000010;
16'h0018: r_dat_o = 64'h02804000000002a0;
16'h0020: r_dat_o = 64'h1a07c00000000020;
16'h0028: r_dat_o = 64'h028680000004e200;
16'h0030: r_dat_o = 64'h0c86800000000020;
16'h0038: r_dat_o = 64'h084fc1fffffffff0;
16'h0040: r_dat_o = 64'hff00000000000000;
16'h0048: r_dat_o = 64'h0407360000000000;
16'h0050: r_dat_o = 64'h0a87000000000000;
16'h0058: r_dat_o = 64'h084fc1ffffffffe8;
16'h0060: r_dat_o = 64'h0606c20000000010;
16'h0068: r_dat_o = 64'h1d00000000000000;
            default:  r_dat_o = 64'hfe00000000000000;
        endcase
    end

    always @(posedge clk_i) begin
        if (rst_i) begin
            state <= `STATE_IDLE;
            r_ack <= 1'h0;
            r_err <= 1'h0;
        end else begin
            case (state)
                `STATE_IDLE: begin
                    if (rom_stb_i) begin
                        state <= `STATE_WAIT_FOR_PHASE_END;

                        if (rom_we_i) begin


                            r_ack <= 1'h0;
                            r_err <= 1'h1;
                        end else begin
                            r_ack <= 1'h1;
                            r_err <= 1'h0;
                        end
                    end
                end
                `STATE_WAIT_FOR_PHASE_END: begin
                    if (~rom_stb_i) begin
                        state <= `STATE_IDLE;
                        r_ack <= 1'h0;
                        r_err <= 1'h0;
                    end
                end
            endcase
        end
    end

endmodule
module rom (
    input rst_i,
    input clk_i,

    `WB_SLAVE_PORT_SIGNALS(rom_)
);




    parameter INSTRUCTIONS = 128;
    parameter GRANULE = 8;

    reg state = `STATE_IDLE;
    reg [`DAT_WIDTH-1:0] r_dat_o;
    reg r_ack = 1'h0;
    reg r_err = 1'h0;

    assign rom_ack_o = rom_stb_i ? r_ack : 1'b0;
    assign rom_err_o = rom_stb_i ? r_err : 1'b0;
    assign rom_dat_o = r_dat_o;

    always @(*) begin
        casex (rom_adr_i)
16'h0000: r_dat_o = 64'h0287800010001018;
16'h0008: r_dat_o = 64'h1687800000008000;
16'h0010: r_dat_o = 64'h0286c01002000010;
16'h0018: r_dat_o = 64'h02804000000002a0;
16'h0020: r_dat_o = 64'h1a07c00000000020;
16'h0028: r_dat_o = 64'h028680000004e200;
16'h0030: r_dat_o = 64'h0c86800000000020;
16'h0038: r_dat_o = 64'h084fc1fffffffff0;
16'h0040: r_dat_o = 64'hff00000000000000;
16'h0048: r_dat_o = 64'h0407360000000000;
16'h0050: r_dat_o = 64'h0a87000000000000;
16'h0058: r_dat_o = 64'h084fc1ffffffffe8;
16'h0060: r_dat_o = 64'h0606c20000000010;
16'h0068: r_dat_o = 64'h1d00000000000000;
            default:  r_dat_o = 64'hfe00000000000000;
        endcase
    end

    always @(posedge clk_i) begin
        if (rst_i) begin
            state <= `STATE_IDLE;
            r_ack <= 1'h0;
            r_err <= 1'h0;
        end else begin
            case (state)
                `STATE_IDLE: begin
                    if (rom_stb_i) begin
                        state <= `STATE_WAIT_FOR_PHASE_END;

                        if (rom_we_i) begin


                            r_ack <= 1'h0;
                            r_err <= 1'h1;
                        end else begin
                            r_ack <= 1'h1;
                            r_err <= 1'h0;
                        end
                    end
                end
                `STATE_WAIT_FOR_PHASE_END: begin
                    if (~rom_stb_i) begin
                        state <= `STATE_IDLE;
                        r_ack <= 1'h0;
                        r_err <= 1'h0;
                    end
                end
            endcase
        end
    end

endmodule