data/full_repos/permissive/161568282/UM/UM_v1/hold1clk.v
data/verilator_xmls/88c220d4-34a2-471a-a87c-a3df22a307b0.xml
module hold1clk(
clk,
reset,
stage_enable_in,
stage_enable_out
);


input clk;
input reset;
input stage_enable_in;
output  stage_enable_out;

reg stage_enable_out;


always @ (posedge clk or negedge reset)
begin
    if(!reset)
      begin
			    stage_enable_out <= 1'b0;
      end
    else
      begin
          if(stage_enable_in == 1'b1)
            begin
               stage_enable_out <= 1'b1;
            end
          else stage_enable_out <= 1'b0;
      end
end

























endmodule
module hold1clk(
clk,
reset,
stage_enable_in,
stage_enable_out
);



input clk;
input reset;
input stage_enable_in;
output  stage_enable_out;

reg stage_enable_out;


always @ (posedge clk or negedge reset)
begin
    if(!reset)
      begin
			    stage_enable_out <= 1'b0;
      end
    else
      begin
          if(stage_enable_in == 1'b1)
            begin
               stage_enable_out <= 1'b1;
            end
          else stage_enable_out <= 1'b0;
      end
end

























endmodule