data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_table_lookup.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_table_lookup.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_table_lookup.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_table_lookup.v:55: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_table_lookup.v:32: Cannot find file containing module: \'table_lookup\'\n table_lookup uut (\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150152921/apps/aes/step1/testbench,data/full_repos/permissive/150152921/table_lookup\n             data/full_repos/permissive/150152921/apps/aes/step1/testbench,data/full_repos/permissive/150152921/table_lookup.v\n             data/full_repos/permissive/150152921/apps/aes/step1/testbench,data/full_repos/permissive/150152921/table_lookup.sv\n             table_lookup\n             table_lookup.v\n             table_lookup.sv\n             obj_dir/table_lookup\n             obj_dir/table_lookup.v\n             obj_dir/table_lookup.sv\n%Warning-WIDTH: data/full_repos/permissive/150152921/apps/aes/step1/testbench/test_table_lookup.v:45: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h193de3be\' generates 31 bits.\n                                                                                                    : ... In instance test_table_lookup\n        state = 31\'h193de3be;\n              ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_table_lookup;


	reg clk;
	reg [31:0] state;


	wire [31:0] p0;
	wire [31:0] p1;
	wire [31:0] p2;
	wire [31:0] p3;


	table_lookup uut (
		.clk(clk), 
		.state(state), 
		.p0(p0), 
		.p1(p1), 
		.p2(p2), 
		.p3(p3)
	);

	initial begin
		clk = 0;
		state = 0;
		#100;
        state = 31'h193de3be;
        #20;
        if (p0 !== 32'hb3_d4_d4_67) begin $display("E"); $finish; end
        if (p1 !== 32'h69_4e_27_27) begin $display("E"); $finish; end
        if (p2 !== 32'h11_33_22_11) begin $display("E"); $finish; end
        if (p3 !== 32'hae_ae_e9_47) begin $display("E"); $finish; end
        $display("Good.");
        $finish;
	end
    
    always #5 clk = ~clk;
endmodule
module test_table_lookup;



	reg clk;
	reg [31:0] state;


	wire [31:0] p0;
	wire [31:0] p1;
	wire [31:0] p2;
	wire [31:0] p3;


	table_lookup uut (
		.clk(clk), 
		.state(state), 
		.p0(p0), 
		.p1(p1), 
		.p2(p2), 
		.p3(p3)
	);

	initial begin
		clk = 0;
		state = 0;
		#100;
        state = 31'h193de3be;
        #20;
        if (p0 !== 32'hb3_d4_d4_67) begin $display("E"); $finish; end
        if (p1 !== 32'h69_4e_27_27) begin $display("E"); $finish; end
        if (p2 !== 32'h11_33_22_11) begin $display("E"); $finish; end
        if (p3 !== 32'hae_ae_e9_47) begin $display("E"); $finish; end
        $display("Good.");
        $finish;
	end
    
    always #5 clk = ~clk;
endmodule