data/full_repos/permissive/197614074/Relu.v
data/verilator_xmls/6c0a8419-6e70-4b91-a104-e0f75bfa91a6.xml
module Relu(
		input 					signed 	[7:0] data,
		input										clk,
		output 	 	reg		signed 	[7:0] result
    );
		initial begin result = 0 ;end
		parameter THRESSHOLD = 0;
		always @ (posedge clk)begin
			result = (data > THRESSHOLD)? (data) : (8'b00000000);
		end
endmodule
module Relu(
		input 					signed 	[7:0] data,
		input										clk,
		output 	 	reg		signed 	[7:0] result
    );

		initial begin result = 0 ;end
		parameter THRESSHOLD = 0;
		always @ (posedge clk)begin
			result = (data > THRESSHOLD)? (data) : (8'b00000000);
		end
endmodule