data/full_repos/permissive/165901145/seq_detector.srcs/sources_1/new/detect_count.v
1: b"%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sources_1/new/detect_count.v:30: Unsupported: SystemVerilog 2009 reserved word not implemented: 'let'\n    wire let;\n         ^~~\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sources_1/new/detect_count.v:30: syntax error, unexpected ';', expecting IDENTIFIER or do or final\n    wire let;\n            ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sources_1/new/detect_count.v:32: Unsupported: SystemVerilog 2009 reserved word not implemented: 'let'\n    detector detect(w,clk,let,stage_no);\n                          ^~~\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sources_1/new/detect_count.v:33: Unsupported: SystemVerilog 2009 reserved word not implemented: 'let'\n    Tcounter #(5) counter(let,rest_n,clk,count);\n                          ^~~\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sources_1/new/detect_count.v:49: Unsupported: SystemVerilog 2009 reserved word not implemented: 'let'\n      if (let == 0) begin\n          ^~~\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sources_1/new/detect_count.v:49: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\n      if (let == 0) begin\n              ^~\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sources_1/new/detect_count.v:51: Unsupported: SystemVerilog 2009 reserved word not implemented: 'let'\n          z<=let;\n             ^~~\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sources_1/new/detect_count.v:54: syntax error, unexpected '=', expecting IDENTIFIER\n        if(when == 0) when =1;\n                           ^\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sources_1/new/detect_count.v:56: Unsupported: SystemVerilog 2009 reserved word not implemented: 'let'\n      else if (let == 1) begin\n               ^~~\n%Error: data/full_repos/permissive/165901145/seq_detector.srcs/sources_1/new/detect_count.v:57: Unsupported: SystemVerilog 2009 reserved word not implemented: 'let'\n        z <= let;\n             ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n"
module detect_count(
    input w,
    input rest_n,
    input clk,
    output reg z,
    output [3:0] count
    );
    wire let;
    wire [2:0] stage_no;
    detector detect(w,clk,let,stage_no);
    Tcounter #(5) counter(let,rest_n,clk,count);
    integer when = 1;












    always @(posedge clk)
    begin
      if (let == 0) begin
        if(when == 1) begin
          z<=let;
          when = 0;
        end
        if(when == 0) when =1;
      end
      else if (let == 1) begin
        z <= let;
      end
    end
endmodule
module detect_count(
    input w,
    input rest_n,
    input clk,
    output reg z,
    output [3:0] count
    );

    wire let;
    wire [2:0] stage_no;
    detector detect(w,clk,let,stage_no);
    Tcounter #(5) counter(let,rest_n,clk,count);
    integer when = 1;












    always @(posedge clk)
    begin
      if (let == 0) begin
        if(when == 1) begin
          z<=let;
          when = 0;
        end
        if(when == 0) when =1;
      end
      else if (let == 1) begin
        z <= let;
      end
    end
endmodule