data/full_repos/permissive/118895561/Project 2/comms.v
1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/118895561\n        ... Looked in:\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561.v\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561.sv\n             2,data/full_repos/permissive/118895561\n             2,data/full_repos/permissive/118895561.v\n             2,data/full_repos/permissive/118895561.sv\n             obj_dir/2,data/full_repos/permissive/118895561\n             obj_dir/2,data/full_repos/permissive/118895561.v\n             obj_dir/2,data/full_repos/permissive/118895561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/118895561/Project\n%Error: Cannot find file containing module: 2/comms.v\n%Error: Exiting due to 3 error(s)\n'
module comms(
    input [31:0] Instr_E, 
    input [31:0] A, B, ALU_Out, HI, LO,
    output reg [31:0] ALU_Out_E
    );
	 
	 wire [5:0]  Op, Func;
	 wire [31:0] Sub;
	 wire C_Signed, C_Unsigned;
	 wire sltu, slt, mfhi, mflo; 
	 wire [3:0] ctrl;
	 
	 assign Op 	 = Instr_E[31:26];
	 assign Func = Instr_E[5:0];
	 
	 assign ctrl = {sltu, slt, mfhi, mflo};
	 assign slt  = (Op == 6'b001010) | (Op == 6'b000000 & Func == 6'b101010);
	 assign sltu = (Op == 6'b001011) | (Op == 6'b000000 & Func == 6'b101011);
	 assign mfhi = (Op == 6'b000000 & Func == 6'b010000);
	 assign mflo = (Op == 6'b000000 & Func == 6'b010010);
	 
	 
	 assign {C_Signed, Sub}   = {A[31], A} - {B[31], B};
	 assign {C_Unsigned, Sub} = {1'b0, A} - {1'b0, B};
	 
	 
	 
	always @(*) begin
			case(ctrl)
			 4'b1000 : ALU_Out_E = {31'b0,C_Unsigned};
			 4'b0100 : ALU_Out_E = {31'b0,C_Signed};
			 4'b0010 : ALU_Out_E = HI;
			 4'b0001 : ALU_Out_E = LO;
			 default : ALU_Out_E = ALU_Out;
			endcase
	end
endmodule
module comms(
    input [31:0] Instr_E, 
    input [31:0] A, B, ALU_Out, HI, LO,
    output reg [31:0] ALU_Out_E
    );

	 
	 wire [5:0]  Op, Func;
	 wire [31:0] Sub;
	 wire C_Signed, C_Unsigned;
	 wire sltu, slt, mfhi, mflo; 
	 wire [3:0] ctrl;
	 
	 assign Op 	 = Instr_E[31:26];
	 assign Func = Instr_E[5:0];
	 
	 assign ctrl = {sltu, slt, mfhi, mflo};
	 assign slt  = (Op == 6'b001010) | (Op == 6'b000000 & Func == 6'b101010);
	 assign sltu = (Op == 6'b001011) | (Op == 6'b000000 & Func == 6'b101011);
	 assign mfhi = (Op == 6'b000000 & Func == 6'b010000);
	 assign mflo = (Op == 6'b000000 & Func == 6'b010010);
	 
	 
	 assign {C_Signed, Sub}   = {A[31], A} - {B[31], B};
	 assign {C_Unsigned, Sub} = {1'b0, A} - {1'b0, B};
	 
	 
	 
	always @(*) begin
			case(ctrl)
			 4'b1000 : ALU_Out_E = {31'b0,C_Unsigned};
			 4'b0100 : ALU_Out_E = {31'b0,C_Signed};
			 4'b0010 : ALU_Out_E = HI;
			 4'b0001 : ALU_Out_E = LO;
			 default : ALU_Out_E = ALU_Out;
			endcase
	end
endmodule