data/full_repos/permissive/174323821/hdl/clocking/jtframe_freqinfo.v
data/verilator_xmls/2c42156c-1aae-4068-9b82-2f02f2270071.xml
module jtframe_freqinfo #(parameter
    KHZ   = 1,
    MFREQ = 48_000
)(
    input             rst,
    input             clk,
    input             pulse,
    output reg [15:0] fave,
    output reg [15:0] fworst
);

wire cnt_event;
wire cen;

generate
    if( KHZ==1 )
        assign cen = 1;
    else begin


        reg [9:0] div;
        assign cen = div==999;
        always @(posedge clk, posedge rst) begin
            if( rst ) begin
                div <= 0;
            end else begin
                div <= cen ? 10'd0 : div+10'd1;
            end
        end
    end
endgenerate


reg [15:0] freq_cnt, fout_cnt;
reg        pulse_l;

assign cnt_event = pulse & ~pulse_l;

always @(posedge clk, posedge rst) begin
    if( rst ) begin
        freq_cnt <= 0;
        fworst   <= 16'hffff;
        fave     <= 0;
    end else begin
        pulse_l <= pulse;
        if( cen ) freq_cnt <= freq_cnt + 1'd1;
        if( cnt_event ) fout_cnt<=fout_cnt+1'd1;
        if( freq_cnt == MFREQ-1 ) begin
            freq_cnt <= 0;
            fout_cnt <= 0;
            fave <= fout_cnt;
            if( fworst > fout_cnt ) fworst <= fout_cnt;
        end
    end
end

endmodule
module jtframe_freqinfo #(parameter
    KHZ   = 1,
    MFREQ = 48_000
)(
    input             rst,
    input             clk,
    input             pulse,
    output reg [15:0] fave,
    output reg [15:0] fworst
);


wire cnt_event;
wire cen;

generate
    if( KHZ==1 )
        assign cen = 1;
    else begin


        reg [9:0] div;
        assign cen = div==999;
        always @(posedge clk, posedge rst) begin
            if( rst ) begin
                div <= 0;
            end else begin
                div <= cen ? 10'd0 : div+10'd1;
            end
        end
    end
endgenerate


reg [15:0] freq_cnt, fout_cnt;
reg        pulse_l;

assign cnt_event = pulse & ~pulse_l;

always @(posedge clk, posedge rst) begin
    if( rst ) begin
        freq_cnt <= 0;
        fworst   <= 16'hffff;
        fave     <= 0;
    end else begin
        pulse_l <= pulse;
        if( cen ) freq_cnt <= freq_cnt + 1'd1;
        if( cnt_event ) fout_cnt<=fout_cnt+1'd1;
        if( freq_cnt == MFREQ-1 ) begin
            freq_cnt <= 0;
            fout_cnt <= 0;
            fave <= fout_cnt;
            if( fworst > fout_cnt ) fworst <= fout_cnt;
        end
    end
end

endmodule