data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v
1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:7: Define or directive not defined: \'`ADDR_BUS\'\n    input wire [`ADDR_BUS] f_predPC_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`ADDR_BUS] f_predPC_i,\n                         ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:8: Define or directive not defined: \'`ADDR_BUS\'\n    output reg [`ADDR_BUS] F_predPC_o\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:13: Define or directive not defined: \'`ADDR_ZERO\'\n        F_predPC_o <= `ADDR_ZERO;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:18: Define or directive not defined: \'`RST_EN\'\n            if(rst == `RST_EN)\n                      ^~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:20: Define or directive not defined: \'`ADDR_ZERO\'\n                F_predPC_o <= `ADDR_ZERO;\n                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/fetch_reg.v:22: Define or directive not defined: \'`FALSE\'\n            else if(F_stall_i == `FALSE)\n                                 ^~~~~~\n%Error: Exiting due to 8 error(s)\n'
module fetch_reg(
    input wire clk,
    input wire rst,
    input wire F_stall_i,
    input wire [`ADDR_BUS] f_predPC_i,
    output reg [`ADDR_BUS] F_predPC_o
    );
    
    initial
    begin
        F_predPC_o <= `ADDR_ZERO;
    end
    
    always @(posedge clk)
        begin
            if(rst == `RST_EN)
            begin
                F_predPC_o <= `ADDR_ZERO;
            end
            else if(F_stall_i == `FALSE)
            begin
                F_predPC_o <= f_predPC_i;
            end
            else
            begin
                F_predPC_o <= F_predPC_o;
            end
        end
endmodule
module fetch_reg(
    input wire clk,
    input wire rst,
    input wire F_stall_i,
    input wire [`ADDR_BUS] f_predPC_i,
    output reg [`ADDR_BUS] F_predPC_o
    );

    
    initial
    begin
        F_predPC_o <= `ADDR_ZERO;
    end
    
    always @(posedge clk)
        begin
            if(rst == `RST_EN)
            begin
                F_predPC_o <= `ADDR_ZERO;
            end
            else if(F_stall_i == `FALSE)
            begin
                F_predPC_o <= f_predPC_i;
            end
            else
            begin
                F_predPC_o <= F_predPC_o;
            end
        end
endmodule