data/full_repos/permissive/169574047/gates/gates.srcs/sim_1/new/testbench.v
 line:36: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/169574047/gates/gates.srcs/sim_1/new/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #5 in1=0;in2=1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169574047/gates/gates.srcs/sim_1/new/testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #5 in1=1;in2=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/gates/gates.srcs/sim_1/new/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #5 in1=1;in2=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/gates/gates.srcs/sim_1/new/testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/169574047/gates/gates.srcs/sim_1/new/testbench.v:25: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire [0:15] out;\n     ^\n%Error: data/full_repos/permissive/169574047/gates/gates.srcs/sim_1/new/testbench.v:28: Cannot find file containing module: \'gates\'\ngates g1(out,in1,in2);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/169574047/gates/gates.srcs/sim_1/new,data/full_repos/permissive/169574047/gates\n             data/full_repos/permissive/169574047/gates/gates.srcs/sim_1/new,data/full_repos/permissive/169574047/gates.v\n             data/full_repos/permissive/169574047/gates/gates.srcs/sim_1/new,data/full_repos/permissive/169574047/gates.sv\n             gates\n             gates.v\n             gates.sv\n             obj_dir/gates\n             obj_dir/gates.v\n             obj_dir/gates.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

wire [0:15] out;
reg in1,in2;

gates g1(out,in1,in2);

initial
begin
    in1=0;in2=0;
    #5 in1=0;in2=1;
    #5 in1=1;in2=0;
    #5 in1=1;in2=1;
    #5 $finish;
end

endmodule
module testbench;


wire [0:15] out;
reg in1,in2;

gates g1(out,in1,in2);

initial
begin
    in1=0;in2=0;
    #5 in1=0;in2=1;
    #5 in1=1;in2=0;
    #5 in1=1;in2=1;
    #5 $finish;
end

endmodule