data/full_repos/permissive/121770408/Master.v
 line:17: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/121770408/Master.v:13: Unsupported: Ignoring delay on this delayed statement.\n#10 ss1 = 0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/121770408/Master.v:24: Unsupported: Ignoring delay on this delayed statement.\n#2 scl = !scl;\n^\n%Error: data/full_repos/permissive/121770408/Master.v:28: syntax error, unexpected IDENTIFIER\nVerilog Code for Slave \n^~~~~~~\n%Error: data/full_repos/permissive/121770408/Master.v:65: Too many digits for 1 bit number: 1\'bx1\nmiso<=1\'bx1;\n      ^~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Master(scl,mosi,miso,ss1,ss2,ss3,ss4);
output reg scl;
input [0:0]miso;
output reg [0:0]mosi;
output reg ss1;
output reg ss2;
output reg ss3;
output reg ss4;
reg [16:0]xx;
initial begin
scl = 0;
ss1 = 1;
#10 ss1 = 0;
xx = 17'b010101011_00011001;
end
always @(negedge ss1)
slock ;
always @(posedge scl)begin
mosi = xx[16];
xx = xx<<1;
end
task slock;
repeat (38)
#2 scl = !scl;
endtask: slock;
Slave1 slv1(scl,miso,mosi,ss1);
endmodule
module Master(scl,mosi,miso,ss1,ss2,ss3,ss4);

output reg scl;
input [0:0]miso;
output reg [0:0]mosi;
output reg ss1;
output reg ss2;
output reg ss3;
output reg ss4;
reg [16:0]xx;
initial begin
scl = 0;
ss1 = 1;
#10 ss1 = 0;
xx = 17'b010101011_00011001;
end
always @(negedge ss1)
slock ;
always @(posedge scl)begin
mosi = xx[16];
xx = xx<<1;
end
task slock;
repeat (38)
#2 scl = !scl;
endtask: slock;
Slave1 slv1(scl,miso,mosi,ss1);
endmodule