data/full_repos/permissive/180217218/fpga/src/top.v
None: at end of input
1: b'%Error: data/full_repos/permissive/180217218/fpga/src/top.v:48: Cannot find file containing module: \'Uart\'\n Uart u0 (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/180217218/fpga/src,data/full_repos/permissive/180217218/Uart\n             data/full_repos/permissive/180217218/fpga/src,data/full_repos/permissive/180217218/Uart.v\n             data/full_repos/permissive/180217218/fpga/src,data/full_repos/permissive/180217218/Uart.sv\n             Uart\n             Uart.v\n             Uart.sv\n             obj_dir/Uart\n             obj_dir/Uart.v\n             obj_dir/Uart.sv\n%Warning-WIDTH: data/full_repos/permissive/180217218/fpga/src/top.v:136: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                       : ... In instance Top\n    if((nextDat[bitcnt] && (symcnt == 10)) ||\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/180217218/fpga/src/top.v:137: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                       : ... In instance Top\n     (!nextDat[bitcnt] && (symcnt == 5)))\n              ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module Top
(
	input clk,

	output uart_tx,
	input uart_rx,
	input uart_rts,
	output uart_cts,
	
	output ndat,


	output [4:0] led,
	output reg debug
);



	reg [7:0] dataSend = 8'h00;
	reg dataSendCmd = 0;
	reg dataSendValid = 0;
	wire dataSendValid_b;
	wire dataSendAck;
	wire [7:0] dataRecv;
	wire dataRecvCmd;
	wire dataRecvValid;
	reg dataRecvAck = 0;
	reg dataRecvThrottle = 0;

	Uart u0 (
		.clk(clk),
		.rx(uart_rx),
		.cts(uart_cts),
		.tx(uart_tx),
		.rts(uart_rts),
		.dataSend(dataSend),
		.dataSendCmd(dataSendCmd),
		.dataSendValid(dataSendValid_b),
		.dataSendAck(dataSendAck),
		.dataRecv(dataRecv),
		.dataRecvCmd(dataRecvCmd),
		.dataRecvValid(dataRecvValid),
		.dataRecvAck(dataRecvAck),
		.dataRecvThrottle(dataRecvThrottle)
	);
	

	reg [7:0] mem [31:0];
	reg [4:0] memW = 0;
	reg [4:0] memR = 0;
	reg [4:0] memBufLen = 0;
	reg next = 1;
	reg nextBak = 0;
	reg [7:0] nextDat = 0;
	reg nextDatValid = 0;
	

	always @(posedge clk)
	begin
		debug <= 0;
		dataRecvAck <= 1;
		if(dataRecvValid) begin
			if(next) begin
				nextBak <= 1;
			end
			mem[memW] = dataRecv;
			memW <= memW + 1;
			memBufLen <= memBufLen + 1;
			dataRecvAck <= 1;
		end else if((next || nextBak) && (memBufLen > 0)) begin
			nextDat <= mem[memR];
			nextDatValid <= 1;
			memR <= memR + 1;
			memBufLen <= memBufLen - 1;
			nextBak <= 0;
		end else if(next || nextBak) begin
			nextDatValid <= 0;
			nextBak <= 1;
		end
		
		if(memBufLen > 20) begin
			dataRecvThrottle <= 1;
		end else if (memBufLen < 10) begin
			dataRecvThrottle <= 0;
		end

	end


	reg [23:0] testdat = 24'hFF22FD;
	reg [9:0] rstcnt = 0;
	reg [3:0] symcnt = 0;
	reg [4:0] bitcnt = 0;
	reg [1:0] state = 0;
	
	reg dat = 0;
	
	always @(posedge clk)
	begin
		next <= 0;
		
		case(state)
			0: begin
				if (rstcnt == 10'b1111111111) begin
					if(nextDatValid) begin
						rstcnt <= 0;
						bitcnt <= 7;
						state <= 1;
						dat <= 1;
					end
				end else begin
					rstcnt <= rstcnt + 1;
					dat <= 0;
				end
			end
			
			1: begin
				if((nextDat[bitcnt] && (symcnt == 10)) ||
					(!nextDat[bitcnt] && (symcnt == 5)))
				begin
					dat <= 0;
				end
			
				if (symcnt == 15) begin
					symcnt <= 0;
					if (bitcnt == 0) begin
						if(!nextDatValid) begin
							state <= 0;
						end else begin
							bitcnt <= 7;
							dat <= 1;
						end
					end else begin
						bitcnt <= bitcnt - 1;
						dat <= 1;
					end
				end else begin
					if((bitcnt == 0) && (symcnt == 12)) begin
						next <= 1;
					end
					symcnt <= symcnt + 1;
				end
			end
		endcase
	end
	
	assign ndat = dat;


	reg [24:0] cnt = 0;

	always @(posedge clk)
	begin
		cnt <= cnt + 1;
	end

	assign led = cnt[24:20];

endmodule
module Top
(
	input clk,

	output uart_tx,
	input uart_rx,
	input uart_rts,
	output uart_cts,
	
	output ndat,


	output [4:0] led,
	output reg debug
);




	reg [7:0] dataSend = 8'h00;
	reg dataSendCmd = 0;
	reg dataSendValid = 0;
	wire dataSendValid_b;
	wire dataSendAck;
	wire [7:0] dataRecv;
	wire dataRecvCmd;
	wire dataRecvValid;
	reg dataRecvAck = 0;
	reg dataRecvThrottle = 0;

	Uart u0 (
		.clk(clk),
		.rx(uart_rx),
		.cts(uart_cts),
		.tx(uart_tx),
		.rts(uart_rts),
		.dataSend(dataSend),
		.dataSendCmd(dataSendCmd),
		.dataSendValid(dataSendValid_b),
		.dataSendAck(dataSendAck),
		.dataRecv(dataRecv),
		.dataRecvCmd(dataRecvCmd),
		.dataRecvValid(dataRecvValid),
		.dataRecvAck(dataRecvAck),
		.dataRecvThrottle(dataRecvThrottle)
	);
	

	reg [7:0] mem [31:0];
	reg [4:0] memW = 0;
	reg [4:0] memR = 0;
	reg [4:0] memBufLen = 0;
	reg next = 1;
	reg nextBak = 0;
	reg [7:0] nextDat = 0;
	reg nextDatValid = 0;
	

	always @(posedge clk)
	begin
		debug <= 0;
		dataRecvAck <= 1;
		if(dataRecvValid) begin
			if(next) begin
				nextBak <= 1;
			end
			mem[memW] = dataRecv;
			memW <= memW + 1;
			memBufLen <= memBufLen + 1;
			dataRecvAck <= 1;
		end else if((next || nextBak) && (memBufLen > 0)) begin
			nextDat <= mem[memR];
			nextDatValid <= 1;
			memR <= memR + 1;
			memBufLen <= memBufLen - 1;
			nextBak <= 0;
		end else if(next || nextBak) begin
			nextDatValid <= 0;
			nextBak <= 1;
		end
		
		if(memBufLen > 20) begin
			dataRecvThrottle <= 1;
		end else if (memBufLen < 10) begin
			dataRecvThrottle <= 0;
		end

	end


	reg [23:0] testdat = 24'hFF22FD;
	reg [9:0] rstcnt = 0;
	reg [3:0] symcnt = 0;
	reg [4:0] bitcnt = 0;
	reg [1:0] state = 0;
	
	reg dat = 0;
	
	always @(posedge clk)
	begin
		next <= 0;
		
		case(state)
			0: begin
				if (rstcnt == 10'b1111111111) begin
					if(nextDatValid) begin
						rstcnt <= 0;
						bitcnt <= 7;
						state <= 1;
						dat <= 1;
					end
				end else begin
					rstcnt <= rstcnt + 1;
					dat <= 0;
				end
			end
			
			1: begin
				if((nextDat[bitcnt] && (symcnt == 10)) ||
					(!nextDat[bitcnt] && (symcnt == 5)))
				begin
					dat <= 0;
				end
			
				if (symcnt == 15) begin
					symcnt <= 0;
					if (bitcnt == 0) begin
						if(!nextDatValid) begin
							state <= 0;
						end else begin
							bitcnt <= 7;
							dat <= 1;
						end
					end else begin
						bitcnt <= bitcnt - 1;
						dat <= 1;
					end
				end else begin
					if((bitcnt == 0) && (symcnt == 12)) begin
						next <= 1;
					end
					symcnt <= symcnt + 1;
				end
			end
		endcase
	end
	
	assign ndat = dat;


	reg [24:0] cnt = 0;

	always @(posedge clk)
	begin
		cnt <= cnt + 1;
	end

	assign led = cnt[24:20];

endmodule