data/full_repos/permissive/137045072/pipeline_mem2wb.v
1: b'%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:22: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:36: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] reg_write_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input      [`DATA_BUS] reg_write_in,\n                         ^\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:37: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] reg_write_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:38: Define or directive not defined: \'`VREG_BUS\'\n    input      [`VREG_BUS] virtual_write_addr_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:39: Define or directive not defined: \'`VREG_BUS\'\n    output reg [`VREG_BUS] virtual_write_addr_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:40: Define or directive not defined: \'`PREG_BUS\'\n    input      [`PREG_BUS] physical_write_addr_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:41: Define or directive not defined: \'`PREG_BUS\'\n    output reg [`PREG_BUS] physical_write_addr_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:44: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input                  wb_cp0_in,\n    ^~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:46: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input      [`CP0_REG_BUS] cp0_write_addr_in,\n    ^~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:46: Define or directive not defined: \'`CP0_REG_BUS\'\n    input      [`CP0_REG_BUS] cp0_write_addr_in,\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:47: Define or directive not defined: \'`CP0_REG_BUS\'\n    output reg [`CP0_REG_BUS] cp0_write_addr_out,\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:48: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] cp0_write_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/pipeline_mem2wb.v:49: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] cp0_write_out\n                ^~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module pipeline_mem2wb #(
    parameter DATA_WIDTH = 32,
    parameter FREE_LIST_WIDTH = 3
)(
    input      clk,
    input      rst_n,
    input      flush,
    input      global_flush,
    input      stall,

    input      wb_reg_in,
    output reg wb_reg_out,
    input      [`DATA_BUS] reg_write_in,
    output reg [`DATA_BUS] reg_write_out,
    input      [`VREG_BUS] virtual_write_addr_in,
    output reg [`VREG_BUS] virtual_write_addr_out,
    input      [`PREG_BUS] physical_write_addr_in,
    output reg [`PREG_BUS] physical_write_addr_out,
    input      [FREE_LIST_WIDTH-1:0] active_list_index_in,
    output reg [FREE_LIST_WIDTH-1:0] active_list_index_out,
    input                  wb_cp0_in,
    output reg             wb_cp0_out,
    input      [`CP0_REG_BUS] cp0_write_addr_in,
    output reg [`CP0_REG_BUS] cp0_write_addr_out,
    input      [`DATA_BUS] cp0_write_in,
    output reg [`DATA_BUS] cp0_write_out

    );

    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            wb_reg_out <= 0;
            reg_write_out <= 0;
            virtual_write_addr_out <= 0;
            physical_write_addr_out <= 0;
            active_list_index_out <= 0;
            wb_cp0_out <= 0;
            cp0_write_addr_out <= 0;
            cp0_write_out <= 0;
        end
        else
        begin
            if (!stall)
            begin
                if (flush || global_flush)
                begin
                    wb_reg_out <= 0;
                    reg_write_out <= 0;
                    virtual_write_addr_out <= 0;
                    physical_write_addr_out <= 0;
                    active_list_index_out <= 0;
                    wb_cp0_out <= 0;
                    cp0_write_addr_out <= 0;
                    cp0_write_out <= 0;
                end
                else
                begin
                    wb_reg_out <= wb_reg_in;
                    reg_write_out <= reg_write_in;
                    virtual_write_addr_out <= virtual_write_addr_in;
                    physical_write_addr_out <= physical_write_addr_in;
                    active_list_index_out <= active_list_index_in;
                    wb_cp0_out <= wb_cp0_in;
                    cp0_write_addr_out <= cp0_write_addr_in;
                    cp0_write_out <= cp0_write_in;
                end
            end
        end
    end
endmodule
module pipeline_mem2wb #(
    parameter DATA_WIDTH = 32,
    parameter FREE_LIST_WIDTH = 3
)(
    input      clk,
    input      rst_n,
    input      flush,
    input      global_flush,
    input      stall,

    input      wb_reg_in,
    output reg wb_reg_out,
    input      [`DATA_BUS] reg_write_in,
    output reg [`DATA_BUS] reg_write_out,
    input      [`VREG_BUS] virtual_write_addr_in,
    output reg [`VREG_BUS] virtual_write_addr_out,
    input      [`PREG_BUS] physical_write_addr_in,
    output reg [`PREG_BUS] physical_write_addr_out,
    input      [FREE_LIST_WIDTH-1:0] active_list_index_in,
    output reg [FREE_LIST_WIDTH-1:0] active_list_index_out,
    input                  wb_cp0_in,
    output reg             wb_cp0_out,
    input      [`CP0_REG_BUS] cp0_write_addr_in,
    output reg [`CP0_REG_BUS] cp0_write_addr_out,
    input      [`DATA_BUS] cp0_write_in,
    output reg [`DATA_BUS] cp0_write_out

    );


    always @(posedge clk, negedge rst_n)
    begin
        if (!rst_n)
        begin
            wb_reg_out <= 0;
            reg_write_out <= 0;
            virtual_write_addr_out <= 0;
            physical_write_addr_out <= 0;
            active_list_index_out <= 0;
            wb_cp0_out <= 0;
            cp0_write_addr_out <= 0;
            cp0_write_out <= 0;
        end
        else
        begin
            if (!stall)
            begin
                if (flush || global_flush)
                begin
                    wb_reg_out <= 0;
                    reg_write_out <= 0;
                    virtual_write_addr_out <= 0;
                    physical_write_addr_out <= 0;
                    active_list_index_out <= 0;
                    wb_cp0_out <= 0;
                    cp0_write_addr_out <= 0;
                    cp0_write_out <= 0;
                end
                else
                begin
                    wb_reg_out <= wb_reg_in;
                    reg_write_out <= reg_write_in;
                    virtual_write_addr_out <= virtual_write_addr_in;
                    physical_write_addr_out <= physical_write_addr_in;
                    active_list_index_out <= active_list_index_in;
                    wb_cp0_out <= wb_cp0_in;
                    cp0_write_addr_out <= cp0_write_addr_in;
                    cp0_write_out <= cp0_write_in;
                end
            end
        end
    end
endmodule