data/full_repos/permissive/197356760/GCD/Register.v
data/verilator_xmls/0fd1a000-8626-4c30-8ae5-ba3bbc94d76d.xml
module reg_module #(parameter width = 8)
				  (input clk, en,
				   input [width-1:0] in,
				   output reg [width-1:0] out);
				
	always @(posedge clk) begin
		if (en) begin
			out <= in;
		end	
	end
endmodule
module reg_module #(parameter width = 8)
				  (input clk, en,
				   input [width-1:0] in,
				   output reg [width-1:0] out);

				
	always @(posedge clk) begin
		if (en) begin
			out <= in;
		end	
	end
endmodule