data/full_repos/permissive/214620165/rtl/core/riscv_irq_sync.sv
 line:114 column:23: Illegal character "'"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/214620165/rtl/core/riscv_irq_sync.sv:62: Signal definition not found, creating implicitly: \'irq_debug\'\n                                                                                     : ... Suggested alternative: \'irq_debug_i\'\n .q    (irq_debug)\n        ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sync_pose 
#(
	parameter int width = 1
)
(
	input                 clk,
	input                 rst_n,
	input  [width-1 : 0]  d,
	output [width-1 : 0]  q
);

	logic  [width-1 : 0] q_0;
	logic  [width-1 : 0] q_1;
	logic  [width-1 : 0] q_2;


	always_ff @(posedge clk or negedge rst_n) begin 
		if(~rst_n) begin
			q_0 <= '0;
			q_1 <= '0;
			q_2 <= '0;
		end else begin
			q_0 <= d;
			q_1 <= q_0;
			q_2 <= q_1;
		end
	end

	assign q = ~q_2&q_1;


endmodule
module sync_pose 
#(
	parameter int width = 1
)
(
	input                 clk,
	input                 rst_n,
	input  [width-1 : 0]  d,
	output [width-1 : 0]  q
);


	logic  [width-1 : 0] q_0;
	logic  [width-1 : 0] q_1;
	logic  [width-1 : 0] q_2;


	always_ff @(posedge clk or negedge rst_n) begin 
		if(~rst_n) begin
			q_0 <= '0;
			q_1 <= '0;
			q_2 <= '0;
		end else begin
			q_0 <= d;
			q_1 <= q_0;
			q_2 <= q_1;
		end
	end

	assign q = ~q_2&q_1;


endmodule