data/full_repos/permissive/143278/ivltests/pr2109179.v
 line:28: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2109179.v:14: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2109179.v:28: Unsupported: Ignoring delay on this delayed statement.\n   #2 $display("PASSED");\n   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2109179.v:15: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s CONST \'?32?h2\' generates 32 or 2 bits.\n                                                                         : ... In instance t\n   if(!i && vosz1 !== 0) begin\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2109179.v:15: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s CONST \'?32?h3\' generates 32 or 2 bits.\n                                                                         : ... In instance t\n   if(!i && vosz1 !== 0) begin\n      ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t();

reg [1:0] f;
reg [1:0] oszok;
wire [2:0] vosz1;

genvar i;

generate
	for(i = 0; i < 4; i = i + 1) begin : reg_tomb_gen
		wire [2:0] vosz1;
		assign vosz1 = i - f + oszok + 1;
		initial begin
			#1;
			if(!i && vosz1 !== 0) begin
			   $display("FAIL -- i=%b, f=%b, oszok=%b, vosz1=%b",
				    i, f, oszok, vosz1);
			   $finish;
			end
		end
	end
endgenerate

initial
begin
   f = 3;
   oszok = 2;
   #2 $display("PASSED");
end
endmodule
module t();


reg [1:0] f;
reg [1:0] oszok;
wire [2:0] vosz1;

genvar i;

generate
	for(i = 0; i < 4; i = i + 1) begin : reg_tomb_gen
		wire [2:0] vosz1;
		assign vosz1 = i - f + oszok + 1;
		initial begin
			#1;
			if(!i && vosz1 !== 0) begin
			   $display("FAIL -- i=%b, f=%b, oszok=%b, vosz1=%b",
				    i, f, oszok, vosz1);
			   $finish;
			end
		end
	end
endgenerate

initial
begin
   f = 3;
   oszok = 2;
   #2 $display("PASSED");
end
endmodule