data/full_repos/permissive/109506234/test.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109506234/test.v:2: Cannot find include file: VerilogBM_120-120.v\n`include "VerilogBM_120-120.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109506234,data/full_repos/permissive/109506234/VerilogBM_120-120.v\n             data/full_repos/permissive/109506234,data/full_repos/permissive/109506234/VerilogBM_120-120.v.v\n             data/full_repos/permissive/109506234,data/full_repos/permissive/109506234/VerilogBM_120-120.v.sv\n             VerilogBM_120-120.v\n             VerilogBM_120-120.v.v\n             VerilogBM_120-120.v.sv\n             obj_dir/VerilogBM_120-120.v\n             obj_dir/VerilogBM_120-120.v.v\n             obj_dir/VerilogBM_120-120.v.sv\n%Error: data/full_repos/permissive/109506234/test.v:9: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120_add.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:10: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:16: Unsupported: Ignoring delay on this delayed statement.\n#1 C=1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:17: Unsupported: Ignoring delay on this delayed statement.\n#1 C=0;\n^\n%Error: data/full_repos/permissive/109506234/test.v:24: Too many digits for 32 bit number: 01000001110010000000000000000000\n        ... As that number was unsized (\'d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)\n        ... Suggest adding a size to it.\n#1 input_a=01000001110010000000000000000000; \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:24: Unsupported: Ignoring delay on this delayed statement.\n#1 input_a=01000001110010000000000000000000; \n^\n%Error: data/full_repos/permissive/109506234/test.v:25: Too many digits for 32 bit number: 01000001001000000000000000000000\ninput_b=01000001001000000000000000000000;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:33: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120_div.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:34: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:40: Unsupported: Ignoring delay on this delayed statement.\n#1 C=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:41: Unsupported: Ignoring delay on this delayed statement.\n#1 C=0;\n^\n%Error: data/full_repos/permissive/109506234/test.v:48: Too many digits for 32 bit number: 01000001110010000000000000000000\n#1 input_a=01000001110010000000000000000000; \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:48: Unsupported: Ignoring delay on this delayed statement.\n#1 input_a=01000001110010000000000000000000; \n^\n%Error: data/full_repos/permissive/109506234/test.v:49: Too many digits for 32 bit number: 01000001001000000000000000000000\ninput_b=01000001001000000000000000000000;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:53: Unsupported or unknown PLI call: $monitor\n$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk); \n^~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:61: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:62: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:67: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("VerilogBM_120_120_mult.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:68: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,Verilog_120_120);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:73: Unsupported: Ignoring delay on this delayed statement.\n#1 C=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:74: Unsupported: Ignoring delay on this delayed statement.\n#1 C=0;\n^\n%Error: data/full_repos/permissive/109506234/test.v:81: Too many digits for 32 bit number: 01000001110010000000000000000000\n#1 input_a=01000001110010000000000000000000; \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109506234/test.v:81: Unsupported: Ignoring delay on this delayed statement.\n#1 input_a=01000001110010000000000000000000; \n^\n%Error: data/full_repos/permissive/109506234/test.v:82: Too many digits for 32 bit number: 01000001001000000000000000000000\ninput_b=01000001001000000000000000000000;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109506234/test.v:86: Unsupported or unknown PLI call: $monitor\n$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk); \n^~~~~~~~\n%Error: Exiting due to 17 error(s), 9 warning(s)\n'
module Verilog_120_120120();
reg input_a,input_b,clk,rst;
wire output_z; 
initial
begin
$dumpfile("VerilogBM_120_120_div.vcd");
$dumpvars(0,Verilog_120_120);
end
divider divider_Verilog_120_120(input_a,input_b,clk,rst,output_z);
initial begin
forever begin
C=0;
#1 C=1;
#1 C=0;
end
end
initial
begin
input_a=00000000000000000000000000000000; 
input_b=00000000000000000000000000000000; 
#1 input_a=01000001110010000000000000000000; 
input_b=01000001001000000000000000000000;
end
initial
begin
$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk); 
end
endmodule
module Verilog_120_120120();

reg input_a,input_b,clk,rst;
wire output_z; 
initial
begin
$dumpfile("VerilogBM_120_120_div.vcd");
$dumpvars(0,Verilog_120_120);
end
divider divider_Verilog_120_120(input_a,input_b,clk,rst,output_z);
initial begin
forever begin
C=0;
#1 C=1;
#1 C=0;
end
end
initial
begin
input_a=00000000000000000000000000000000; 
input_b=00000000000000000000000000000000; 
#1 input_a=01000001110010000000000000000000; 
input_b=01000001001000000000000000000000;
end
initial
begin
$monitor("input_a=%32b input_b=%32b output_z=%32b clk=%1b",input_a,input_b,output_z,clk); 
end
endmodule