data/full_repos/permissive/20688874/coding_theory/encoder_pl.v
data/verilator_xmls/00d5ee5d-0508-437b-baac-6d49a2fb1b30.xml
module encoder (b,c);
	output [0:0] c;

	input [0:0] b;

	reg [0:0] c;

	always @(b)
	begin
	end
endmodule
module encoder (b,c);

	output [0:0] c;

	input [0:0] b;

	reg [0:0] c;

	always @(b)
	begin
	end
endmodule