data/full_repos/permissive/161275071/sys/hdmi_config.sv
 line:38: before: "reg"
1: b"%Error: data/full_repos/permissive/161275071/sys/hdmi_config.sv:67: syntax error, unexpected '=', expecting ',' or ';'\nwire [15:0] init_data[58] = \n                          ^\n%Error: Exiting due to 1 error(s)\n"
module hdmi_config
(

	input			iCLK,
	input			iRST_N,
	
	input       dvi_mode,
	input       audio_96k,


	output		I2C_SCL,
	inout 		I2C_SDA
);


reg        mI2C_GO = 0;
wire       mI2C_END;
wire       mI2C_ACK;
reg [15:0] LUT_DATA;
reg  [7:0] LUT_INDEX = 0;

i2c #(50_000_000, 20_000) i2c_av
(
	.CLK(iCLK),

	.I2C_SCL(I2C_SCL),
	.I2C_SDA(I2C_SDA),

	.I2C_DATA({8'h72,init_data[LUT_INDEX]}),
	.START(mI2C_GO),
	.END(mI2C_END),
	.ACK(mI2C_ACK)
);


always@(posedge iCLK or negedge iRST_N) begin
	reg  [1:0] mSetup_ST = 0;

	if(!iRST_N) begin
		LUT_INDEX	<=	0;
		mSetup_ST	<=	0;
		mI2C_GO		<=	0;
	end else begin
		if(init_data[LUT_INDEX] != 16'hFFFF) begin
			case(mSetup_ST)
			0:	begin
					mI2C_GO		<=	1;
					mSetup_ST	<=	1;
				end
			1: if(~mI2C_END) mSetup_ST	<=	2;
			2:	begin
					mI2C_GO <= 0;
					if(mI2C_END) begin
						mSetup_ST <= 0;
						if(!mI2C_ACK) LUT_INDEX <= LUT_INDEX + 8'd1;
					end
				end
			endcase
		end
	end
end




wire [15:0] init_data[58] = 
'{
	16'h9803,

	{8'hD6, 8'b1100_0000},





	16'h4110,
	16'h9A70,
	16'h9C30,
	{8'h9D, 8'b0110_0001},


	16'hA2A4,
	16'hA3A4,
	16'hE0D0,


	16'h35_40,
	16'h36_D9,
	16'h37_0A,
	16'h38_00,
	16'h39_2D,
	16'h3A_00,

	{8'h16, 8'b0011_1000},






	{8'h17, 8'b01100010},

	{8'h18, 8'b0100_0110},




	{8'h3B, 8'b0000_0000},

	16'h4000,

	{8'h48, 8'b0000_1000},



	16'h49A8,
	16'h4C00,

	{8'h55, 8'b0001_0000},




	16'h7301,

	{8'h94, 8'b1000_0000},

	16'h9902,
	16'h9B18,

	16'h9F00,

	{8'hA1, 8'b0000_0000},
	
	16'hA408,
	16'hA504,
	16'hA600,
	16'hA700,
	16'hA800,
	16'hA900,
	16'hAA00,
	16'hAB40,
	
	{8'hAF, 6'b0001_01,~dvi_mode,1'b0},






	16'hB900,

	{8'hBA, 8'b0110_0000},








					
	16'hBB00,
	
	16'hDE9C,
	16'hE460,
	16'hFA7D,

	

	
	{8'h0A, 8'b0000_0000},


	{8'h0B, 8'b0000_1110},
									
	{8'h0C, 8'b0000_0100},



									
	{8'h0D, 8'b0001_0000},
	{8'h14, 8'b0000_0010},
	{8'h15, audio_96k, 7'b010_0000},



	16'h0100,
	audio_96k ? 16'h0230 : 16'h0218,
	16'h0300,

	16'h0701,
	16'h0822,
	16'h090A,

	16'hFFFF
};



endmodule
module hdmi_config
(

	input			iCLK,
	input			iRST_N,
	
	input       dvi_mode,
	input       audio_96k,


	output		I2C_SCL,
	inout 		I2C_SDA
);



reg        mI2C_GO = 0;
wire       mI2C_END;
wire       mI2C_ACK;
reg [15:0] LUT_DATA;
reg  [7:0] LUT_INDEX = 0;

i2c #(50_000_000, 20_000) i2c_av
(
	.CLK(iCLK),

	.I2C_SCL(I2C_SCL),
	.I2C_SDA(I2C_SDA),

	.I2C_DATA({8'h72,init_data[LUT_INDEX]}),
	.START(mI2C_GO),
	.END(mI2C_END),
	.ACK(mI2C_ACK)
);


always@(posedge iCLK or negedge iRST_N) begin
	reg  [1:0] mSetup_ST = 0;

	if(!iRST_N) begin
		LUT_INDEX	<=	0;
		mSetup_ST	<=	0;
		mI2C_GO		<=	0;
	end else begin
		if(init_data[LUT_INDEX] != 16'hFFFF) begin
			case(mSetup_ST)
			0:	begin
					mI2C_GO		<=	1;
					mSetup_ST	<=	1;
				end
			1: if(~mI2C_END) mSetup_ST	<=	2;
			2:	begin
					mI2C_GO <= 0;
					if(mI2C_END) begin
						mSetup_ST <= 0;
						if(!mI2C_ACK) LUT_INDEX <= LUT_INDEX + 8'd1;
					end
				end
			endcase
		end
	end
end




wire [15:0] init_data[58] = 
'{
	16'h9803,

	{8'hD6, 8'b1100_0000},





	16'h4110,
	16'h9A70,
	16'h9C30,
	{8'h9D, 8'b0110_0001},


	16'hA2A4,
	16'hA3A4,
	16'hE0D0,


	16'h35_40,
	16'h36_D9,
	16'h37_0A,
	16'h38_00,
	16'h39_2D,
	16'h3A_00,

	{8'h16, 8'b0011_1000},






	{8'h17, 8'b01100010},

	{8'h18, 8'b0100_0110},




	{8'h3B, 8'b0000_0000},

	16'h4000,

	{8'h48, 8'b0000_1000},



	16'h49A8,
	16'h4C00,

	{8'h55, 8'b0001_0000},




	16'h7301,

	{8'h94, 8'b1000_0000},

	16'h9902,
	16'h9B18,

	16'h9F00,

	{8'hA1, 8'b0000_0000},
	
	16'hA408,
	16'hA504,
	16'hA600,
	16'hA700,
	16'hA800,
	16'hA900,
	16'hAA00,
	16'hAB40,
	
	{8'hAF, 6'b0001_01,~dvi_mode,1'b0},






	16'hB900,

	{8'hBA, 8'b0110_0000},








					
	16'hBB00,
	
	16'hDE9C,
	16'hE460,
	16'hFA7D,

	

	
	{8'h0A, 8'b0000_0000},


	{8'h0B, 8'b0000_1110},
									
	{8'h0C, 8'b0000_0100},



									
	{8'h0D, 8'b0001_0000},
	{8'h14, 8'b0000_0010},
	{8'h15, audio_96k, 7'b010_0000},



	16'h0100,
	audio_96k ? 16'h0230 : 16'h0218,
	16'h0300,

	16'h0701,
	16'h0822,
	16'h090A,

	16'hFFFF
};



endmodule