data/full_repos/permissive/181738725/wavetrace/verilog/lib/ram/ram_1c_1r_1w.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/ram/ram_1c_1r_1w.sv:32: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/ram,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/ram,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/ram,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module ram_1c_1r_1w (clk, wr_en, wr_addr, wr_data, rd_addr, rd_data);
`include "util.vh"

  parameter  Width = 18;
  parameter  Depth = 64;
  parameter  ReportCollision = 1;

  localparam AddrBits = clog2(Depth);

  input                  clk;

  input                  wr_en;
  input [AddrBits-1:0]   wr_addr;
  input [Width-1:0]      wr_data;

  input [AddrBits-1:0]   rd_addr;
  output reg [Width-1:0] rd_data;





  reg [Width-1:0] mem[0:Depth-1];
  reg [Width-1:0] rd_data_i;

  always_ff @(posedge clk) begin
    if (wr_en)
      mem[wr_addr] <= wr_data;
    rd_data_i <= mem[rd_addr];
  end





  reg  collision;
  always_ff @(posedge clk) begin
    collision <= wr_en && wr_addr == rd_addr;
    if (ReportCollision) begin
      assert (!wr_en || (wr_addr != rd_addr)) else
        $error("Read and write to same address: read data indeterminate");
    end
  end


  always_comb begin
    rd_data = rd_data_i;

    if (collision)
      rd_data = {{Width}{1'bx}};

  end


endmodule
module ram_1c_1r_1w (clk, wr_en, wr_addr, wr_data, rd_addr, rd_data);

`include "util.vh"

  parameter  Width = 18;
  parameter  Depth = 64;
  parameter  ReportCollision = 1;

  localparam AddrBits = clog2(Depth);

  input                  clk;

  input                  wr_en;
  input [AddrBits-1:0]   wr_addr;
  input [Width-1:0]      wr_data;

  input [AddrBits-1:0]   rd_addr;
  output reg [Width-1:0] rd_data;





  reg [Width-1:0] mem[0:Depth-1];
  reg [Width-1:0] rd_data_i;

  always_ff @(posedge clk) begin
    if (wr_en)
      mem[wr_addr] <= wr_data;
    rd_data_i <= mem[rd_addr];
  end





  reg  collision;
  always_ff @(posedge clk) begin
    collision <= wr_en && wr_addr == rd_addr;
    if (ReportCollision) begin
      assert (!wr_en || (wr_addr != rd_addr)) else
        $error("Read and write to same address: read data indeterminate");
    end
  end


  always_comb begin
    rd_data = rd_data_i;

    if (collision)
      rd_data = {{Width}{1'bx}};

  end


endmodule