data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/mux3.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/mux3.v:35: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                                                  : ... In instance mux3\n    default:y<=32\'bx;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mux3 #(parameter WIDTH=8)
    (
    input [WIDTH-1:0] d00,d01,d10,
    input [1:0] s,
    output reg [WIDTH-1:0] y
    );
    
    always@(*)
    case(s)
    2'b00:y<=d00;
    2'b01:y<=d01;
    2'b10:y<=d10;
    default:y<=32'bx;
    endcase
    
endmodule
module mux3 #(parameter WIDTH=8)
    (
    input [WIDTH-1:0] d00,d01,d10,
    input [1:0] s,
    output reg [WIDTH-1:0] y
    );

    
    always@(*)
    case(s)
    2'b00:y<=d00;
    2'b01:y<=d01;
    2'b10:y<=d10;
    default:y<=32'bx;
    endcase
    
endmodule