data/full_repos/permissive/170365068/Single verilog file/mipsFull.v
1: b'%Error: Cannot find file containing module: verilog\n        ... Looked in:\n             data/full_repos/permissive/170365068/Single/verilog\n             data/full_repos/permissive/170365068/Single/verilog.v\n             data/full_repos/permissive/170365068/Single/verilog.sv\n             verilog\n             verilog.v\n             verilog.sv\n             obj_dir/verilog\n             obj_dir/verilog.v\n             obj_dir/verilog.sv\n%Error: Cannot find file containing module: file,data/full_repos/permissive/170365068\n%Error: Cannot find file containing module: data/full_repos/permissive/170365068/Single\n%Error: Cannot find file containing module: file/mipsFull.v\n%Error: Exiting due to 4 error(s)\n'
module mux32(D0,D1,select,Out);
	
	input [31:0]D0,D1;
	input select;
	
	output reg [31:0] Out;
	
	always@(*)
		if(select)
			Out<=D1;
		else 
			Out<=D0;
endmodule
module mux32(D0,D1,select,Out);

	
	input [31:0]D0,D1;
	input select;
	
	output reg [31:0] Out;
	
	always@(*)
		if(select)
			Out<=D1;
		else 
			Out<=D0;
endmodule