data/full_repos/permissive/129155059/proyecto-02/wrr/testbench_synth.v
 line:23: before: "("
1: b'%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/testbench_synth.v:1: Cannot find include file: tester.v\n`include "tester.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-02/wrr,data/full_repos/permissive/129155059/tester.v\n             data/full_repos/permissive/129155059/proyecto-02/wrr,data/full_repos/permissive/129155059/tester.v.v\n             data/full_repos/permissive/129155059/proyecto-02/wrr,data/full_repos/permissive/129155059/tester.v.sv\n             tester.v\n             tester.v.v\n             tester.v.sv\n             obj_dir/tester.v\n             obj_dir/tester.v.v\n             obj_dir/tester.v.sv\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/testbench_synth.v:2: Cannot find include file: mux4_1_synth.v\n`include "mux4_1_synth.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/testbench_synth.v:3: Cannot find include file: wrr_synth.v\n`include "wrr_synth.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/wrr/testbench_synth.v:4: Cannot find include file: vc_table_synth.v\n`include "vc_table_synth.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module testbench_synth;

  wire [1:0] VC_id_tb, request_id_tb, vc_assign_tb;
  wire [2:0] weight_tb, weight_assign_tb;
  wire [3:0] Data_Word_tb;
  wire       clk_tb, reset_tb, data_out_tb, edit_weight_tb;


  mux4_1_cond mux_synth( .VC_id      (VC_id_tb),
                        .Data_Word  (Data_Word_tb),
                        .reset      (reset_tb),
                        .data_out   (data_out_tb)
  );

  wrr_cond wrr_mod_synth(.reset      (reset_tb),
                        .clk        (clk_tb),
                        .weight     (weight_tb),
                        .request_id (request_id_tb),
                        .grant_id   (VC_id_tb)
  );

  vc_table_cond table_synth( .clk          (clk_tb),
                            .reset        (reset_tb),
                            .edit_weight  (edit_weight_tb),
                            .weight_assign(weight_assign_tb),
                            .weight       (weight_tb),
                            .vc           (request_id_tb)
  );

  tester  letest_synth(  .weight_assign  (weight_assign_tb),
                        .vc_assign      (vc_assign_tb),
                        .CLK_2MHz       (clk_tb),
                        .reset          (reset_tb),
                        .edit_weight    (edit_weight_tb),
                        .Data_Word      (Data_Word_tb)
  );

endmodule
module testbench_synth;


  wire [1:0] VC_id_tb, request_id_tb, vc_assign_tb;
  wire [2:0] weight_tb, weight_assign_tb;
  wire [3:0] Data_Word_tb;
  wire       clk_tb, reset_tb, data_out_tb, edit_weight_tb;


  mux4_1_cond mux_synth( .VC_id      (VC_id_tb),
                        .Data_Word  (Data_Word_tb),
                        .reset      (reset_tb),
                        .data_out   (data_out_tb)
  );

  wrr_cond wrr_mod_synth(.reset      (reset_tb),
                        .clk        (clk_tb),
                        .weight     (weight_tb),
                        .request_id (request_id_tb),
                        .grant_id   (VC_id_tb)
  );

  vc_table_cond table_synth( .clk          (clk_tb),
                            .reset        (reset_tb),
                            .edit_weight  (edit_weight_tb),
                            .weight_assign(weight_assign_tb),
                            .weight       (weight_tb),
                            .vc           (request_id_tb)
  );

  tester  letest_synth(  .weight_assign  (weight_assign_tb),
                        .vc_assign      (vc_assign_tb),
                        .CLK_2MHz       (clk_tb),
                        .reset          (reset_tb),
                        .edit_weight    (edit_weight_tb),
                        .Data_Word      (Data_Word_tb)
  );

endmodule