data/full_repos/permissive/168395472/labs/02_dff/dff.v
data/verilator_xmls/16b2a26a-4604-4eac-b916-e1a87f680ae9.xml
module dff(
    input clk,
    input d,

    output reg q
);

always @(posedge clk) begin
    q <= d;
end

endmodule
module dff(
    input clk,
    input d,

    output reg q
);


always @(posedge clk) begin
    q <= d;
end

endmodule