data/full_repos/permissive/21051978/processor/pisotb.v
 line:127: before: "~"
1: b'%Error: data/full_repos/permissive/21051978/processor/pisotb.v:26: Cannot find include file: piso.v\n`include "piso.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/piso.v\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/piso.v.v\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/piso.v.sv\n             piso.v\n             piso.v.v\n             piso.v.sv\n             obj_dir/piso.v\n             obj_dir/piso.v.v\n             obj_dir/piso.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:94: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:95: Unsupported: Ignoring delay on this delayed statement.\n     #5 clock = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #90\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #90\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:162: Unsupported: Ignoring delay on this delayed statement.\n  #90\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:168: Unsupported: Ignoring delay on this delayed statement.\n  #90\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #40      \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:180: Unsupported: Ignoring delay on this delayed statement.\n  #30      \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #90\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:198: Unsupported: Ignoring delay on this delayed statement.\n  #70      \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:205: Unsupported: Ignoring delay on this delayed statement.\n  #90\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:211: Unsupported: Ignoring delay on this delayed statement.\n  #90\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:217: Unsupported: Ignoring delay on this delayed statement.\n  #90\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:223: Unsupported: Ignoring delay on this delayed statement.\n  #90\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:229: Unsupported: Ignoring delay on this delayed statement.\n  #90\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:239: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/pisotb.v:234: Unsupported: Ignoring delay on this delayed statement.\n  #120\n  ^\n%Error: Exiting due to 1 error(s), 18 warning(s)\n'
module tb_piso();

	


	wire s_out,valid_op;
	
	
	
	
	
	
	

	


	reg load_en,clock,reset_low;
	reg [7:0] data_input;
	
	
	
	
	
	
	
	
	



	
	
	
	
	
	
	
	
	
	
	
	

	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;
    end	
	
	
	
	
	
	
	
	
	

	

	PISO pisoc (


		s_out,valid_op,data_input,load_en,reset_low,clock);
	
	
	
	
	
	

	

	initial
	begin

		$display($time, " << Starting the simulation >>");

		reset_low=1'd0;
		load_en=1'd1;
		data_input=8'd10;
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd13;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd6;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd5;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd7;
		
		
		#40
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd3;
		
		
		#30
		reset_low=1'd0;
		load_en=1'd1;
		data_input=8'd2;
		
		
		#20
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd15;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd9;
		
		
		#70
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd14;
		
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd12;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd10;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd0;
		data_input=8'd236;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd174;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd214;
		
		#120
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_piso();


	


	wire s_out,valid_op;
	
	
	
	
	
	
	

	


	reg load_en,clock,reset_low;
	reg [7:0] data_input;
	
	
	
	
	
	
	
	
	



	
	
	
	
	
	
	
	
	
	
	
	

	

	always begin

    	#5 clock = 0;
    	#5 clock = 1;
    end	
	
	
	
	
	
	
	
	
	

	

	PISO pisoc (


		s_out,valid_op,data_input,load_en,reset_low,clock);
	
	
	
	
	
	

	

	initial
	begin

		$display($time, " << Starting the simulation >>");

		reset_low=1'd0;
		load_en=1'd1;
		data_input=8'd10;
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd13;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd6;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd5;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd7;
		
		
		#40
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd3;
		
		
		#30
		reset_low=1'd0;
		load_en=1'd1;
		data_input=8'd2;
		
		
		#20
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd15;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd9;
		
		
		#70
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd14;
		
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd12;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd10;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd0;
		data_input=8'd236;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd174;
		
		
		#90
		reset_low=1'd1;
		load_en=1'd1;
		data_input=8'd214;
		
		#120
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule