data/full_repos/permissive/14432793/rfid-verilog/tag/controller.v
 line:253: before: "begin"
data/verilator_xmls/fd1239ca-74ae-4335-9286-b09b12c34045.xml
module controller (reset, clk, rx_overflow, rx_cmd, currentrn, currenthandle,
                   packet_complete, txsetupdone, tx_done, 
                   rx_en, tx_en, docrc, handlematch,
                   bitsrcselect, readfrommsp, readwriteptr, rx_q, rx_updn,
                   use_uid, use_q, comm_enable);
  
  parameter QUERYREP   = 9'b000000001;
  parameter ACK        = 9'b000000010;
  parameter QUERY      = 9'b000000100;
  parameter QUERYADJ   = 9'b000001000;
  parameter SELECT     = 9'b000010000;
  parameter NACK       = 9'b000100000;
  parameter REQRN      = 9'b001000000;
  parameter READ       = 9'b010000000;
  parameter WRITE      = 9'b100000000;

  parameter bitsrcselect_RNG = 2'd0;
  parameter bitsrcselect_EPC = 2'd1;
  parameter bitsrcselect_ADC = 2'd2;
  parameter bitsrcselect_UID = 2'd3;
   
  input reset, clk, rx_overflow, packet_complete, txsetupdone, tx_done;
  input [8:0] rx_cmd;
  input [15:0]  currentrn;
  output [15:0] currenthandle;
  output rx_en, tx_en, docrc;
  output [1:0] bitsrcselect;
  input [7:0] readwriteptr;
  output readfrommsp;
  input use_uid, use_q;
  input [3:0] rx_q;
  input [2:0] rx_updn;
  input handlematch, comm_enable;

  reg [3:0] rx_q_reg;
  reg readfrommsp;
  reg [15:0] storedhandle;
  reg [1:0] bitsrcselect;
  reg docrc;
  reg rx_en, tx_en;

  reg commstate;
  parameter STATE_RX      = 1'b0;
  parameter STATE_TX      = 1'b1;





  reg tagisopen;
  assign currenthandle = tagisopen ? storedhandle : currentrn;









  reg [14:0] slotcounter;
  

  wire [3:0] q_adj, q_up, q_dn;
  assign q_up  = (rx_q_reg < 4'd15 && rx_updn[2] && rx_updn[1]) ? rx_q_reg + 4'd1 : rx_q_reg;
  assign q_dn  = (rx_q_reg > 4'd0  && rx_updn[0] && rx_updn[1]) ? rx_q_reg - 4'd1 : rx_q_reg;
  assign q_adj = rx_updn[0] ? q_dn : q_up;
  




  wire [14:0] newslotcounter;
  wire [3:0] q_ctl;
  assign q_ctl = (rx_cmd == QUERY) ? rx_q : q_adj;

  reg [14:0] slotcountermask;

  always @ (q_ctl) begin
  case(q_ctl)
    0:  slotcountermask = 15'b000000000000000;
    1:  slotcountermask = 15'b000000000000001;
    2:  slotcountermask = 15'b000000000000011;
    3:  slotcountermask = 15'b000000000000111;
    4:  slotcountermask = 15'b000000000001111;
    5:  slotcountermask = 15'b000000000011111;
    6:  slotcountermask = 15'b000000000111111;
    7:  slotcountermask = 15'b000000001111111;
    8:  slotcountermask = 15'b000000011111111;
    9:  slotcountermask = 15'b000000111111111;
    10: slotcountermask = 15'b000001111111111;
    11: slotcountermask = 15'b000011111111111;
    12: slotcountermask = 15'b000111111111111;
    13: slotcountermask = 15'b001111111111111;
    14: slotcountermask = 15'b011111111111111;
    15: slotcountermask = 15'b111111111111111;
    default: slotcountermask = 15'b000000000000000;
  endcase
  end
  assign newslotcounter = currentrn[14:0] & slotcountermask;
  
  always @ (posedge clk or posedge reset) begin
    if (reset) begin
      commstate <= STATE_RX;
      bitsrcselect    <= 2'd0;
      docrc     <= 0;
      tx_en     <= 0;
      rx_en     <= 0;
      tagisopen <= 0;
      rx_q_reg  <= 0;
      slotcounter  <= 0;
      storedhandle <= 0;
      readfrommsp  <= 0;
    end else if (commstate == STATE_TX) begin
      if(txsetupdone) begin
        rx_en <= 0;
      end
      if(tx_done) begin
        tx_en     <= 0;
        commstate <= STATE_RX;
      end else begin
        tx_en <= 1;
      end
      end else if (commstate == STATE_RX) begin
        if(packet_complete) begin
          case (rx_cmd)
           QUERYREP: begin
             tagisopen   <= 0;
             slotcounter <= slotcounter - 15'd1;
             if (comm_enable & ((slotcounter-15'd1)==0 | ~use_q)) begin
               commstate     <= STATE_TX;
               bitsrcselect        <= bitsrcselect_RNG;
               docrc         <= 0;
             end else begin
               rx_en <= 0;
             end
           end
           ACK: begin
             tagisopen <= 0;
             if (comm_enable && handlematch) begin
               commstate <= STATE_TX;
               bitsrcselect    <= use_uid ? bitsrcselect_UID : bitsrcselect_EPC;
               docrc     <= 1;
             end else begin
             rx_en <= 0;
             end
           end
           QUERY: begin
             tagisopen <= 0;
             rx_q_reg  <= rx_q;

             slotcounter <= newslotcounter;
             
             if (comm_enable & (newslotcounter==0 | ~use_q)) begin
               commstate     <= STATE_TX;
               bitsrcselect        <= bitsrcselect_RNG;
               docrc         <= 0;
             end else begin
               rx_en <= 0;
             end
           end
           QUERYADJ: begin
             tagisopen <= 0;
             rx_q_reg  <= q_adj;

             slotcounter <= newslotcounter;
             
             if (comm_enable & (newslotcounter==0 | ~use_q)) begin
               commstate     <= STATE_TX;
               bitsrcselect        <= bitsrcselect_RNG;
               docrc         <= 0;
             end else begin
               rx_en <= 0;
             end
           end
           SELECT: begin
             tagisopen <= 0;
             rx_en <= 0;
           end
           NACK: begin
             tagisopen <= 0;
             rx_en     <= 0;
           end
           REQRN: begin
             if (comm_enable && handlematch) begin


               if (!tagisopen) begin
                 storedhandle <= currentrn;
                 tagisopen    <= 1;
               end

               commstate <= STATE_TX;
               bitsrcselect    <= bitsrcselect_RNG;
               docrc     <= 1;
             end else begin
               rx_en <= 0;
             end
           end
           READ: begin
             if (comm_enable && handlematch) begin
               if (readwriteptr == 0) readfrommsp <= 0;
               else                   readfrommsp <= 1;
               commstate  <= STATE_TX;
               bitsrcselect     <= bitsrcselect_ADC;
               docrc      <= 1;
             end else begin
               rx_en <= 0;
             end
           end
           WRITE: begin
             rx_en <= 0;
           end
          default begin
             rx_en <= 0;
          end
          endcase
        end else if(rx_overflow) begin
          rx_en <= 0;
        end else begin
          rx_en <= 1;
          tx_en <= 0;
        end
      end
    end
endmodule
module controller (reset, clk, rx_overflow, rx_cmd, currentrn, currenthandle,
                   packet_complete, txsetupdone, tx_done, 
                   rx_en, tx_en, docrc, handlematch,
                   bitsrcselect, readfrommsp, readwriteptr, rx_q, rx_updn,
                   use_uid, use_q, comm_enable);

  
  parameter QUERYREP   = 9'b000000001;
  parameter ACK        = 9'b000000010;
  parameter QUERY      = 9'b000000100;
  parameter QUERYADJ   = 9'b000001000;
  parameter SELECT     = 9'b000010000;
  parameter NACK       = 9'b000100000;
  parameter REQRN      = 9'b001000000;
  parameter READ       = 9'b010000000;
  parameter WRITE      = 9'b100000000;

  parameter bitsrcselect_RNG = 2'd0;
  parameter bitsrcselect_EPC = 2'd1;
  parameter bitsrcselect_ADC = 2'd2;
  parameter bitsrcselect_UID = 2'd3;
   
  input reset, clk, rx_overflow, packet_complete, txsetupdone, tx_done;
  input [8:0] rx_cmd;
  input [15:0]  currentrn;
  output [15:0] currenthandle;
  output rx_en, tx_en, docrc;
  output [1:0] bitsrcselect;
  input [7:0] readwriteptr;
  output readfrommsp;
  input use_uid, use_q;
  input [3:0] rx_q;
  input [2:0] rx_updn;
  input handlematch, comm_enable;

  reg [3:0] rx_q_reg;
  reg readfrommsp;
  reg [15:0] storedhandle;
  reg [1:0] bitsrcselect;
  reg docrc;
  reg rx_en, tx_en;

  reg commstate;
  parameter STATE_RX      = 1'b0;
  parameter STATE_TX      = 1'b1;





  reg tagisopen;
  assign currenthandle = tagisopen ? storedhandle : currentrn;









  reg [14:0] slotcounter;
  

  wire [3:0] q_adj, q_up, q_dn;
  assign q_up  = (rx_q_reg < 4'd15 && rx_updn[2] && rx_updn[1]) ? rx_q_reg + 4'd1 : rx_q_reg;
  assign q_dn  = (rx_q_reg > 4'd0  && rx_updn[0] && rx_updn[1]) ? rx_q_reg - 4'd1 : rx_q_reg;
  assign q_adj = rx_updn[0] ? q_dn : q_up;
  




  wire [14:0] newslotcounter;
  wire [3:0] q_ctl;
  assign q_ctl = (rx_cmd == QUERY) ? rx_q : q_adj;

  reg [14:0] slotcountermask;

  always @ (q_ctl) begin
  case(q_ctl)
    0:  slotcountermask = 15'b000000000000000;
    1:  slotcountermask = 15'b000000000000001;
    2:  slotcountermask = 15'b000000000000011;
    3:  slotcountermask = 15'b000000000000111;
    4:  slotcountermask = 15'b000000000001111;
    5:  slotcountermask = 15'b000000000011111;
    6:  slotcountermask = 15'b000000000111111;
    7:  slotcountermask = 15'b000000001111111;
    8:  slotcountermask = 15'b000000011111111;
    9:  slotcountermask = 15'b000000111111111;
    10: slotcountermask = 15'b000001111111111;
    11: slotcountermask = 15'b000011111111111;
    12: slotcountermask = 15'b000111111111111;
    13: slotcountermask = 15'b001111111111111;
    14: slotcountermask = 15'b011111111111111;
    15: slotcountermask = 15'b111111111111111;
    default: slotcountermask = 15'b000000000000000;
  endcase
  end
  assign newslotcounter = currentrn[14:0] & slotcountermask;
  
  always @ (posedge clk or posedge reset) begin
    if (reset) begin
      commstate <= STATE_RX;
      bitsrcselect    <= 2'd0;
      docrc     <= 0;
      tx_en     <= 0;
      rx_en     <= 0;
      tagisopen <= 0;
      rx_q_reg  <= 0;
      slotcounter  <= 0;
      storedhandle <= 0;
      readfrommsp  <= 0;
    end else if (commstate == STATE_TX) begin
      if(txsetupdone) begin
        rx_en <= 0;
      end
      if(tx_done) begin
        tx_en     <= 0;
        commstate <= STATE_RX;
      end else begin
        tx_en <= 1;
      end
      end else if (commstate == STATE_RX) begin
        if(packet_complete) begin
          case (rx_cmd)
           QUERYREP: begin
             tagisopen   <= 0;
             slotcounter <= slotcounter - 15'd1;
             if (comm_enable & ((slotcounter-15'd1)==0 | ~use_q)) begin
               commstate     <= STATE_TX;
               bitsrcselect        <= bitsrcselect_RNG;
               docrc         <= 0;
             end else begin
               rx_en <= 0;
             end
           end
           ACK: begin
             tagisopen <= 0;
             if (comm_enable && handlematch) begin
               commstate <= STATE_TX;
               bitsrcselect    <= use_uid ? bitsrcselect_UID : bitsrcselect_EPC;
               docrc     <= 1;
             end else begin
             rx_en <= 0;
             end
           end
           QUERY: begin
             tagisopen <= 0;
             rx_q_reg  <= rx_q;

             slotcounter <= newslotcounter;
             
             if (comm_enable & (newslotcounter==0 | ~use_q)) begin
               commstate     <= STATE_TX;
               bitsrcselect        <= bitsrcselect_RNG;
               docrc         <= 0;
             end else begin
               rx_en <= 0;
             end
           end
           QUERYADJ: begin
             tagisopen <= 0;
             rx_q_reg  <= q_adj;

             slotcounter <= newslotcounter;
             
             if (comm_enable & (newslotcounter==0 | ~use_q)) begin
               commstate     <= STATE_TX;
               bitsrcselect        <= bitsrcselect_RNG;
               docrc         <= 0;
             end else begin
               rx_en <= 0;
             end
           end
           SELECT: begin
             tagisopen <= 0;
             rx_en <= 0;
           end
           NACK: begin
             tagisopen <= 0;
             rx_en     <= 0;
           end
           REQRN: begin
             if (comm_enable && handlematch) begin


               if (!tagisopen) begin
                 storedhandle <= currentrn;
                 tagisopen    <= 1;
               end

               commstate <= STATE_TX;
               bitsrcselect    <= bitsrcselect_RNG;
               docrc     <= 1;
             end else begin
               rx_en <= 0;
             end
           end
           READ: begin
             if (comm_enable && handlematch) begin
               if (readwriteptr == 0) readfrommsp <= 0;
               else                   readfrommsp <= 1;
               commstate  <= STATE_TX;
               bitsrcselect     <= bitsrcselect_ADC;
               docrc      <= 1;
             end else begin
               rx_en <= 0;
             end
           end
           WRITE: begin
             rx_en <= 0;
           end
          default begin
             rx_en <= 0;
          end
          endcase
        end else if(rx_overflow) begin
          rx_en <= 0;
        end else begin
          rx_en <= 1;
          tx_en <= 0;
        end
      end
    end
endmodule