data/full_repos/permissive/209997170/Sound/sound_ref/source/triangle.v
1: b'%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/sound_ref/source/triangle.v:12: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'out_q\' generates 1 bits.\n                                                                                         : ... In instance triangle\nassign out = out_q;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/sound_ref/source/triangle.v:21: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'out_q\' generates 1 bits.\n                                                                                         : ... In instance triangle\n        out_d = out_q + dir_q;   \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/sound_ref/source/triangle.v:21: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s ADD generates 8 bits.\n                                                                                         : ... In instance triangle\n        out_d = out_q + dir_q;   \n              ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/sound_ref/source/triangle.v:22: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance triangle\n        ctr_q = 1\'b0;            \n              ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/sound_ref/source/triangle.v:25: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'out_d\' generates 1 bits.\n                                                                                         : ... In instance triangle\n    if (out_d == {CTR_SIZE{1\'b1}} || out_d == {CTR_SIZE{1\'b0}}) begin\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/sound_ref/source/triangle.v:25: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'out_d\' generates 1 bits.\n                                                                                         : ... In instance triangle\n    if (out_d == {CTR_SIZE{1\'b1}} || out_d == {CTR_SIZE{1\'b0}}) begin\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/sound_ref/source/triangle.v:32: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance triangle\n        ctr_q <= 1\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/sound_ref/source/triangle.v:33: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                         : ... In instance triangle\n        dir_q <= 1\'b1;\n              ^~\n%Error: Exiting due to 8 warning(s)\n'
module triangle #(parameter CTR_SIZE = 8) (
    input  clk,
    input  rst,
    input  [CTR_SIZE-1:0] invslope,
    output [CTR_SIZE-1:0] out
    );

reg out_d, out_q;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [CTR_SIZE-1:0] dir_d, dir_q;

assign out = out_q;

always@(ctr_q) begin
    ctr_d = ctr_q + 1'b1;
end

always@(*) begin

    if (ctr_q > invslope) begin
        out_d = out_q + dir_q;
        ctr_q = 1'b0;
    end

    if (out_d == {CTR_SIZE{1'b1}} || out_d == {CTR_SIZE{1'b0}}) begin
        dir_d = ~dir_d;
    end
end

always@(posedge clk) begin
    if (rst) begin
        ctr_q <= 1'b0;
        dir_q <= 1'b1;
    end else begin
        ctr_q <= ctr_d;
        dir_q <= dir_d;
    end
    out_q <= out_d;
end

endmodule
module triangle #(parameter CTR_SIZE = 8) (
    input  clk,
    input  rst,
    input  [CTR_SIZE-1:0] invslope,
    output [CTR_SIZE-1:0] out
    );


reg out_d, out_q;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [CTR_SIZE-1:0] dir_d, dir_q;

assign out = out_q;

always@(ctr_q) begin
    ctr_d = ctr_q + 1'b1;
end

always@(*) begin

    if (ctr_q > invslope) begin
        out_d = out_q + dir_q;
        ctr_q = 1'b0;
    end

    if (out_d == {CTR_SIZE{1'b1}} || out_d == {CTR_SIZE{1'b0}}) begin
        dir_d = ~dir_d;
    end
end

always@(posedge clk) begin
    if (rst) begin
        ctr_q <= 1'b0;
        dir_q <= 1'b1;
    end else begin
        ctr_q <= ctr_d;
        dir_q <= dir_d;
    end
    out_q <= out_d;
end

endmodule