data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v
1: b'%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:73: Operator DIV expects 32 bits on the RHS, but RHS\'s VARREF \'LOOP\' generates 7 bits.\n                                                                                          : ... In instance sha256_transform\n  for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:133: Cannot find file containing module: \'e0\'\n e0 e0_blk (rx_state[(((0)+1)*(32)-1):((0)*(32))], e0_w);\n ^~\n        ... Looked in:\n             data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/e0\n             data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/e0.v\n             data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/e0.sv\n             e0\n             e0.v\n             e0.sv\n             obj_dir/e0\n             obj_dir/e0.v\n             obj_dir/e0.sv\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:134: Cannot find file containing module: \'e1\'\n e1 e1_blk (rx_state[(((4)+1)*(32)-1):((4)*(32))], e1_w);\n ^~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:135: Cannot find file containing module: \'ch\'\n ch ch_blk (rx_state[(((4)+1)*(32)-1):((4)*(32))], rx_state[(((5)+1)*(32)-1):((5)*(32))], rx_state[(((6)+1)*(32)-1):((6)*(32))], ch_w);\n ^~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:136: Cannot find file containing module: \'maj\'\n maj maj_blk (rx_state[(((0)+1)*(32)-1):((0)*(32))], rx_state[(((1)+1)*(32)-1):((1)*(32))], rx_state[(((2)+1)*(32)-1):((2)*(32))], maj_w);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:137: Cannot find file containing module: \'s0\'\n s0 s0_blk (rx_w[63:32], s0_w);\n ^~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/sha256_transform.v:138: Cannot find file containing module: \'s1\'\n s1 s1_blk (rx_w[479:448], s1_w);\n ^~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);

	input clk;
	input [31:0] k;
	input [511:0] rx_w;
	input [255:0] rx_state;

	output reg [511:0] tx_w;
	output reg [255:0] tx_state;


	wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;


	e0	e0_blk	(rx_state[`IDX(0)], e0_w);
	e1	e1_blk	(rx_state[`IDX(4)], e1_w);
	ch	ch_blk	(rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
	maj	maj_blk	(rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
	s0	s0_blk	(rx_w[63:32], s0_w);
	s1	s1_blk	(rx_w[479:448], s1_w);

	wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
	wire [31:0] t2 = e0_w + maj_w;
	wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
	

	always @ (posedge clk)
	begin
		tx_w[511:480] <= new_w;
		tx_w[479:0] <= rx_w[511:32];

		tx_state[`IDX(7)] <= rx_state[`IDX(6)];
		tx_state[`IDX(6)] <= rx_state[`IDX(5)];
		tx_state[`IDX(5)] <= rx_state[`IDX(4)];
		tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
		tx_state[`IDX(3)] <= rx_state[`IDX(2)];
		tx_state[`IDX(2)] <= rx_state[`IDX(1)];
		tx_state[`IDX(1)] <= rx_state[`IDX(0)];
		tx_state[`IDX(0)] <= t1 + t2;
	end

endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);


	input clk;
	input [31:0] k;
	input [511:0] rx_w;
	input [255:0] rx_state;

	output reg [511:0] tx_w;
	output reg [255:0] tx_state;


	wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;


	e0	e0_blk	(rx_state[`IDX(0)], e0_w);
	e1	e1_blk	(rx_state[`IDX(4)], e1_w);
	ch	ch_blk	(rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
	maj	maj_blk	(rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
	s0	s0_blk	(rx_w[63:32], s0_w);
	s1	s1_blk	(rx_w[479:448], s1_w);

	wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
	wire [31:0] t2 = e0_w + maj_w;
	wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
	

	always @ (posedge clk)
	begin
		tx_w[511:480] <= new_w;
		tx_w[479:0] <= rx_w[511:32];

		tx_state[`IDX(7)] <= rx_state[`IDX(6)];
		tx_state[`IDX(6)] <= rx_state[`IDX(5)];
		tx_state[`IDX(5)] <= rx_state[`IDX(4)];
		tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
		tx_state[`IDX(3)] <= rx_state[`IDX(2)];
		tx_state[`IDX(2)] <= rx_state[`IDX(1)];
		tx_state[`IDX(1)] <= rx_state[`IDX(0)];
		tx_state[`IDX(0)] <= t1 + t2;
	end

endmodule