data/full_repos/permissive/208113388/afu/afp/afp3_eng_fsm_main.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/208113388/afu/afp/afp3_eng_fsm_main.v:309: Cannot find file containing module: 'mcp3_ohc05'\n  mcp3_ohc05  main_seq_err (\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208113388/afu/afp,data/full_repos/permissive/208113388/mcp3_ohc05\n             data/full_repos/permissive/208113388/afu/afp,data/full_repos/permissive/208113388/mcp3_ohc05.v\n             data/full_repos/permissive/208113388/afu/afp,data/full_repos/permissive/208113388/mcp3_ohc05.sv\n             mcp3_ohc05\n             mcp3_ohc05.v\n             mcp3_ohc05.sv\n             obj_dir/mcp3_ohc05\n             obj_dir/mcp3_ohc05.v\n             obj_dir/mcp3_ohc05.sv\n%Error: Exiting due to 1 error(s)\n"
module afp3_eng_fsm_main
  (

    input                 clock                                           
  , input                 reset


  , input                 mmio_eng_use_pasid_for_actag
  , input                 mmio_eng_enable
  , input                 mmio_eng_type_ld
  , input                 mmio_eng_type_st
  , input         [63:12] mmio_eng_base_addr
  , input         [31:12] mmio_eng_offset_mask
  , input           [1:0] mmio_eng_ld_size
  , input           [1:0] mmio_eng_st_size
  , input           [9:0] mmio_eng_pasid
  , input                 mmio_eng_send_interrupt
  , input                 mmio_eng_send_wkhstthrd
  , input                 mmio_eng_error_intrpt_enable
  , input                 mmio_eng_wkhstthrd_intrpt_enable
  , input                 mmio_eng_extra_write_mode
  , input                 mmio_eng_mmio_lat_mode
  , input                 mmio_eng_mmio_lat_mode_sz_512_st
  , input                 mmio_eng_mmio_lat_mode_sz_512_ld
  , input                 mmio_eng_mmio_lat_extra_read
  , input          [63:7] mmio_eng_mmio_lat_ld_ea
  , input                 mmio_eng_xtouch_enable
  , input           [1:0] mmio_eng_xtouch_pg_n
  , input           [5:0] mmio_eng_xtouch_pg_size



  , input                 actag_seq_done
  , input                 arb_eng_tags_idle
  , input                 arb_eng_ld_gnt
  , input                 arb_eng_st_gnt

  , input                 xtouch_error_q
  , input                 cpy_ld_error_q
  , input                 cpy_st_error_q
  , input                 wkhstthrd_error_q
  , input                 atomic_error_q


  , input                 intrpt_idle_st
  , input                 intrpt_rtry_idle_st
  , input                 wkhstthrd_idle_st
  , input                 wkhstthrd_rtry_idle_st
  , input                 atomic_idle_st
  , input                 atomic_rtry_idle_st


  , output                main_seq_error

  , output          [4:0] main_state
  , output                main_idle_st
  , output                main_actag_st
  , output                main_send_st
  , output                main_err_intrpt_st
  , output                main_stop_st

  , output                start_actag_seq

  , output                start_xtouch_seq
  , output                start_cpy_ld_seq
  , output                start_cpy_st_seq
  , output                start_wkhstthrd_seq

  , output                start_atomic_seq
  , output                start_intrpt_seq


  , output                main_seq_done

  , output         [63:6] cpy_ld_ea_q
  , output         [63:6] cpy_st_ea_q
  , output         [63:0] xtouch_ea_q
  , output                cpy_ld_idle_st
  , output                cpy_st_idle_st
  , output                cpy_ld_wt4rsp_st
  , output                cpy_st_wt4rsp_st
  , output                cpy_ld_type_sel
  , output                cpy_st_type_sel

  , output                we_cmd_is_intrpt_q
  , output                we_cmd_is_wkhstthrd_q

  , output          [9:0] cmd_pasid_q
  , output                eng_arb_init
  , output                eng_arb_ld_enable
  , output                eng_arb_st_enable

  );





  wire            skip_assign_actag;
  wire            misc_idle;
  wire      [1:0] intrpt_cmd;

  wire            any_major_error;
  wire            stop_for_wkhstthrd_error;
  wire            all_tags_idle;
  wire            main_seq_err_int;
  wire            main_idle_st_int;
  wire     [12:0] main_seq_sel;
  reg       [6:0] main_seq;

  wire            start_capture;

  wire            ld_enable;
  wire            st_enable;
  wire            send_error_intrpt;
  wire            start_intrpt;
  wire            start_wkhstthrd;
  wire            xtouch_enable;


  wire            inc_addr;
  wire     [31:7] offset_addr_plus1;
  wire     [31:7] offset_addr_plus2;
  wire     [31:7] offset_addr_plus1or2;
  wire     [31:7] next_addr;
  wire            toggle_addr_for_mmio_lat;
  wire     [31:7] toggle_addr;
  wire     [63:6] curr_addr;

  wire            extra_read_mode;
  wire            toggle_ld_addr_for_extra_read;
  wire            extra_read_ea_bit8;


  wire            xtouch_pg_size_4k;
  wire            xtouch_pg_size_64k;
  wire            xtouch_pg_size_2m;
  wire            xtouch_pg_size_16m;
  wire            xtouch_pg_size_1g;

  reg      [63:0] xtouch_addr_mask;
  wire            crossed_page;
  wire      [7:0] xtouch_adder_sel;
  reg     [31:12] xtouch_addr_adder;
  wire    [31:12] xtouch_plus_n;





  wire             use_pasid_for_actag_d;
  reg              use_pasid_for_actag_q;


  reg              mmio_eng_enable_q;


  reg              mmio_eng_mmio_lat_mode_q;


  reg              mmio_eng_mmio_lat_mode_sz_512_st_q;


  reg              mmio_eng_mmio_lat_mode_sz_512_ld_q;


  reg              mmio_eng_mmio_lat_extra_read_q;


  reg              mmio_eng_type_ld_q;


  reg              mmio_eng_type_st_q;

  reg      [63:12] base_addr_q;

  reg      [31:12] offset_mask_q;

  reg        [9:0] mmio_eng_pasid_q;

  wire       [4:0] main_seq_d;
 `ifdef MARK_DEBUG_ACTIVE (* mark_debug = "TRUE" *) `endif
  reg        [4:0] main_seq_q;

  wire             step_size_256_d;
  reg              step_size_256_q;

  wire      [31:7] offset_addr_d;
  reg       [31:7] offset_addr_q;

  wire             toggle_ld_addr_bit8_d;
  reg              toggle_ld_addr_bit8_q;

  wire      [63:7] cpy_ld_ea_int_d;
  reg       [63:7] cpy_ld_ea_int_q;

  wire       [5:0] xtouch_pg_size_d;
  reg        [5:0] xtouch_pg_size_q;

  wire             inc_addr_d;
  reg              inc_addr_q;

  wire             xtouch_addr_en;
  wire     [31:12] xtouch_addr_d;
  reg      [31:12] xtouch_addr_q;

  wire             send_interrupt_d;
  reg              send_interrupt_q;

  wire             send_wkhstthrd_d;
  reg              send_wkhstthrd_q;

  wire             send_wkhstthrd_intrpt_d;
  reg              send_wkhstthrd_intrpt_q;

  wire             cmd_is_intrpt_d;
  reg              cmd_is_intrpt_q;

  wire             cmd_is_wkhstthrd_d;
  reg              cmd_is_wkhstthrd_q;


  reg              mmio_eng_error_intrpt_enable_q;


  reg              mmio_eng_wkhstthrd_intrpt_enable_q;


  reg              mmio_eng_extra_write_mode_q;


  reg              mmio_eng_xtouch_enable_q;


  reg        [1:0] mmio_eng_xtouch_pg_n_q;











  assign  use_pasid_for_actag_d   =   mmio_eng_use_pasid_for_actag;


  assign  skip_assign_actag       =  ( use_pasid_for_actag_q );

  assign  cmd_pasid_q[9:0]  =  mmio_eng_pasid_q[9:0];





  assign  send_interrupt_d  =  mmio_eng_send_interrupt | (send_interrupt_q & ~start_intrpt);

  assign  send_wkhstthrd_d  =  mmio_eng_send_wkhstthrd | (send_wkhstthrd_q & ~start_wkhstthrd);


  assign  misc_idle  =  intrpt_idle_st    & intrpt_rtry_idle_st &
                        wkhstthrd_idle_st & wkhstthrd_rtry_idle_st &
                        atomic_idle_st    & atomic_rtry_idle_st;

  assign  send_wkhstthrd_intrpt_d  =  ( wkhstthrd_error_q | send_wkhstthrd_intrpt_q) & ~start_intrpt & mmio_eng_wkhstthrd_intrpt_enable_q;


  assign  intrpt_cmd[1:0]    =  (start_intrpt & send_error_intrpt)       ?  2'b00 :
                                (start_intrpt & send_wkhstthrd_intrpt_q) ?  2'b01 :
                                (start_intrpt & send_interrupt_q)        ?  2'b10 :
                                (start_wkhstthrd)                        ?  2'b01 :
                                                                         { cmd_is_intrpt_q, cmd_is_wkhstthrd_q };

  assign  cmd_is_intrpt_d    = intrpt_cmd[1];
  assign  cmd_is_wkhstthrd_d = intrpt_cmd[0];

  assign  we_cmd_is_intrpt_q    =  cmd_is_intrpt_q;
  assign  we_cmd_is_wkhstthrd_q =  cmd_is_wkhstthrd_q;






  mcp3_ohc05  main_seq_err (
    .one_hot_vector   ( main_seq_q[4:0] ),
    .one_hot_error    ( main_seq_err_int )
  );

  assign  any_major_error  =  xtouch_error_q | cpy_ld_error_q | cpy_st_error_q | atomic_error_q ;

  assign  stop_for_wkhstthrd_error =  wkhstthrd_error_q & ~mmio_eng_wkhstthrd_intrpt_enable_q;

  assign  all_tags_idle  =  arb_eng_tags_idle & misc_idle;


  assign  main_idle_st      =  main_seq_q[0];
  assign  main_actag_st     =  main_seq_q[1];
  assign  main_send_st      =  main_seq_q[2];
  assign  main_err_intrpt_st=  main_seq_q[3];
  assign  main_stop_st      =  main_seq_q[4];

  assign  main_idle_st_int  =  main_seq_q[0];
              

  assign  main_seq_sel[12:0] = { mmio_eng_enable_q, skip_assign_actag, actag_seq_done, any_major_error, mmio_eng_error_intrpt_enable_q, stop_for_wkhstthrd_error, start_intrpt, all_tags_idle, main_seq_q[4:0] };

  always @*
    begin
      casez ( main_seq_sel[12:0] )


















            13'b00?_?????_00001 :  main_seq[6:0] =  7'b00_00001 ;
            13'b10?_0????_00001 :  main_seq[6:0] =  7'b11_00010 ;
            13'b11?_0????_00001 :  main_seq[6:0] =  7'b01_00100 ;

            13'b??0_?????_00010 :  main_seq[6:0] =  7'b00_00010 ;
            13'b1?1_?????_00010 :  main_seq[6:0] =  7'b00_00100 ;
            13'b0?1_?????_00010 :  main_seq[6:0] =  7'b00_00001 ;

            13'b1??_0?0??_00100 :  main_seq[6:0] =  7'b00_00100 ;
            13'b0??_?????_00100 :  main_seq[6:0] =  7'b00_10000 ;
            13'b1??_??1??_00100 :  main_seq[6:0] =  7'b00_10000 ;
            13'b1??_100??_00100 :  main_seq[6:0] =  7'b00_10000 ;
            13'b1??_110??_00100 :  main_seq[6:0] =  7'b00_01000 ;

            13'b1??_???0?_01000 :  main_seq[6:0] =  7'b00_01000 ;
            13'b1??_???1?_01000 :  main_seq[6:0] =  7'b00_10000 ;
            13'b0??_?????_01000 :  main_seq[6:0] =  7'b00_10000 ;

            13'b???_????0_10000 :  main_seq[6:0] =  7'b00_10000 ;
            13'b???_????1_10000 :  main_seq[6:0] =  7'b00_00001 ;

            default             :  main_seq[6:0] =  7'b00_00001 ;

      endcase
    end


  assign  start_actag_seq      =  main_seq[6];
  assign  start_capture        =  main_seq[5];


  assign  main_seq_d[4:0]      = ( reset || main_seq_err_int ) ? 5'b1 : main_seq[4:0];


  assign  main_state[4:0]      =  main_seq_q[4:0];

  assign  eng_arb_init         =  start_capture;
  assign  ld_enable            =  main_seq_q[2] & ~mmio_eng_extra_write_mode_q;
  assign  st_enable            =  main_seq_q[2] & ~mmio_eng_extra_write_mode_q;

  assign  send_error_intrpt    =  main_seq_q[3];

  assign  start_intrpt         =  ( (main_seq_q[2] & send_interrupt_q) |
                                    (main_seq_q[2] & send_wkhstthrd_intrpt_q) |
                                    (send_error_intrpt) )  &
                                  misc_idle &
                                  ~send_wkhstthrd_q;

  assign  start_wkhstthrd      =  main_seq_q[2] & send_wkhstthrd_q & misc_idle;

  assign  xtouch_enable        =  main_seq_q[2] & mmio_eng_xtouch_enable_q;

  assign  cpy_ld_idle_st       =  main_seq_q[0];
  assign  cpy_st_idle_st       =  main_seq_q[0];

  assign  cpy_ld_wt4rsp_st     =  main_seq_q[2] | main_seq_q[3] | main_seq_q[4];
  assign  cpy_st_wt4rsp_st     =  main_seq_q[2] | main_seq_q[3] | main_seq_q[4];

  assign  eng_arb_ld_enable    =  ld_enable;
  assign  eng_arb_st_enable    =  st_enable;

  assign  cpy_ld_type_sel      =  mmio_eng_type_ld_q;
  assign  cpy_st_type_sel      =  mmio_eng_type_st_q;

  assign  start_xtouch_seq     =  xtouch_enable & crossed_page;
  assign  start_cpy_ld_seq     =  ld_enable;
  assign  start_cpy_st_seq     =  st_enable;
  assign  start_wkhstthrd_seq  =  start_wkhstthrd;

  assign  start_atomic_seq     =  1'b0;
  assign  start_intrpt_seq     =  start_intrpt;



  assign  main_seq_done        =  main_idle_st_int;


  assign  main_seq_error  =  main_seq_err_int;






  assign  step_size_256_d  =  (mmio_eng_ld_size[1:0] == 2'b11) || (mmio_eng_st_size[1:0] == 2'b11);

  assign  inc_addr  =  (arb_eng_ld_gnt | arb_eng_st_gnt) &
                        ~mmio_eng_mmio_lat_mode_q & ~mmio_eng_extra_write_mode_q;

  assign  offset_addr_plus1[31:7]  =  offset_addr_q[31:7] + 25'b1;
  assign  offset_addr_plus2[31:7]  =  {(offset_addr_q[31:8] + 24'b1), 1'b0};

  assign  offset_addr_plus1or2[31:7]  = step_size_256_q ?  offset_addr_plus2[31:7]  :
                                                           offset_addr_plus1[31:7];

  assign  next_addr[31:12]  =  (base_addr_q[31:12]          & ~offset_mask_q[31:12]) |
	                       (offset_addr_plus1or2[31:12] &  offset_mask_q[31:12]);

  assign  next_addr[11:7]   =  offset_addr_plus1or2[11:7];  


  assign  toggle_addr_for_mmio_lat  = mmio_eng_mmio_lat_mode_q & mmio_eng_mmio_lat_mode_sz_512_st_q & arb_eng_st_gnt;
  assign  toggle_addr[31:7] =  { offset_addr_q[31:9], (~offset_addr_q[8]), offset_addr_q[7] };

  assign  offset_addr_d[31:7]  =  start_capture ? { base_addr_q[31:12] , 5'b0 } :
                                  inc_addr      ?   next_addr[31:7] :
                       toggle_addr_for_mmio_lat ?   toggle_addr[31:7] :
                                                    offset_addr_q[31:7];

  assign  curr_addr[63:32]   =  base_addr_q[63:32];
  assign  curr_addr[31:7]    =  offset_addr_q[31:7];
  assign  curr_addr[6]       =  1'b0;

  assign  cpy_st_ea_q[63:6]  =  curr_addr[63:6];




  assign  extra_read_mode = mmio_eng_mmio_lat_mode_q & mmio_eng_mmio_lat_extra_read_q;
  assign  toggle_ld_addr_for_extra_read  = mmio_eng_mmio_lat_mode_q & mmio_eng_mmio_lat_mode_sz_512_ld_q & mmio_eng_mmio_lat_extra_read_q & arb_eng_ld_gnt;

  assign  toggle_ld_addr_bit8_d  =  reset | (~extra_read_mode) ? 1'b0 :
                                    toggle_ld_addr_for_extra_read ? (~toggle_ld_addr_bit8_q) :
                                                                      toggle_ld_addr_bit8_q;

  assign  extra_read_ea_bit8  =  mmio_eng_mmio_lat_ld_ea[8] | toggle_ld_addr_bit8_d;

  assign  cpy_ld_ea_int_d[63:7]  = extra_read_mode ? { mmio_eng_mmio_lat_ld_ea[63:9], extra_read_ea_bit8, mmio_eng_mmio_lat_ld_ea[7]} :
                                                     { base_addr_q[63:32], offset_addr_d[31:7] };

  assign  cpy_ld_ea_q[63:6]  =  { cpy_ld_ea_int_q[63:7] , 1'b0 };
















  assign  xtouch_pg_size_d[5:0]  = mmio_eng_xtouch_pg_size[5:0];

  assign  xtouch_pg_size_4k   =  ( xtouch_pg_size_q[5:0] == 6'b00_1100 );
  assign  xtouch_pg_size_64k  =  ( xtouch_pg_size_q[5:0] == 6'b01_0000 );
  assign  xtouch_pg_size_2m   =  ( xtouch_pg_size_q[5:0] == 6'b01_0101 );
  assign  xtouch_pg_size_16m  =  ( xtouch_pg_size_q[5:0] == 6'b01_1000 );
  assign  xtouch_pg_size_1g   =  ( xtouch_pg_size_q[5:0] == 6'b01_1110 );


  always @*
    begin
    casez ( xtouch_pg_size_q[5:0] )








            6'b01_1110 :  xtouch_addr_mask[63:0] = 64'h0000_0000_3FFF_FFFF ;
            6'b01_1000 :  xtouch_addr_mask[63:0] = 64'h0000_0000_00FF_FFFF ;
            6'b01_0101 :  xtouch_addr_mask[63:0] = 64'h0000_0000_001F_FFFF ;
            6'b01_0000 :  xtouch_addr_mask[63:0] = 64'h0000_0000_0000_FFFF ;
            6'b00_1100 :  xtouch_addr_mask[63:0] = 64'h0000_0000_0000_0FFF ;

            default    :  xtouch_addr_mask[63:0] = 64'h0000_0000_0000_0FFF ;

      endcase
    end



  assign  inc_addr_d  = inc_addr;

  assign  crossed_page  =  inc_addr_q  &  ~(| (curr_addr[63:6] & xtouch_addr_mask[63:6]) );




  assign  xtouch_adder_sel[7:0]  =  { mmio_eng_xtouch_pg_n_q[1:0], xtouch_pg_size_q[5:0] };

  always @*
    begin
    casez ( xtouch_adder_sel[7:0] )








            8'b00_00_1100 :  xtouch_addr_adder[31:12] = 20'h00001 ;
            8'b01_00_1100 :  xtouch_addr_adder[31:12] = 20'h00002 ;
            8'b10_00_1100 :  xtouch_addr_adder[31:12] = 20'h00003 ;
            8'b11_00_1100 :  xtouch_addr_adder[31:12] = 20'h00004 ;

            8'b00_01_0000 :  xtouch_addr_adder[31:12] = 20'h00010 ;
            8'b01_01_0000 :  xtouch_addr_adder[31:12] = 20'h00020 ;
            8'b10_01_0000 :  xtouch_addr_adder[31:12] = 20'h00030 ;
            8'b11_01_0000 :  xtouch_addr_adder[31:12] = 20'h00040 ;

            8'b00_01_0101 :  xtouch_addr_adder[31:12] = 20'h00200 ;
            8'b01_01_0101 :  xtouch_addr_adder[31:12] = 20'h00400 ;
            8'b10_01_0101 :  xtouch_addr_adder[31:12] = 20'h00600 ;
            8'b11_01_0101 :  xtouch_addr_adder[31:12] = 20'h00800 ;

            8'b00_01_1000 :  xtouch_addr_adder[31:12] = 20'h01000 ;
            8'b01_01_1000 :  xtouch_addr_adder[31:12] = 20'h01000 ;
            8'b10_01_1000 :  xtouch_addr_adder[31:12] = 20'h01000 ;
            8'b11_01_1000 :  xtouch_addr_adder[31:12] = 20'h01000 ;

            8'b00_01_1110 :  xtouch_addr_adder[31:12] = 20'h40000 ;
            8'b01_01_1110 :  xtouch_addr_adder[31:12] = 20'h80000 ;
            8'b10_01_1110 :  xtouch_addr_adder[31:12] = 20'hC0000 ;







            default       :  xtouch_addr_adder[31:12] = 20'h00001 ;

      endcase
    end

  assign  xtouch_plus_n[31:12]  =  curr_addr[31:12] + xtouch_addr_adder[31:12];

  assign  xtouch_addr_en  =  crossed_page & xtouch_enable;
  assign  xtouch_addr_d[31:12]  =  (base_addr_q[31:12]   & ~offset_mask_q[31:12]) |
	                         (xtouch_plus_n[31:12]   &  offset_mask_q[31:12]);

  assign  xtouch_ea_q[63:0]  =  { base_addr_q[63:32], xtouch_addr_q[31:12], 12'b0 };





  always @ ( posedge clock )
    begin

      if (reset)
        begin
            mmio_eng_enable_q                    <=  1'b0;
            mmio_eng_mmio_lat_mode_q             <=  1'b0;
            mmio_eng_mmio_lat_mode_sz_512_st_q   <=  1'b0;
            mmio_eng_mmio_lat_mode_sz_512_ld_q   <=  1'b0;
            mmio_eng_mmio_lat_extra_read_q       <=  1'b0;
	    send_interrupt_q                     <=  1'b0;
	    send_wkhstthrd_q                     <=  1'b0;
	    send_wkhstthrd_intrpt_q              <=  1'b0;
        end
      else
        begin
            mmio_eng_enable_q                    <=  mmio_eng_enable;
            mmio_eng_mmio_lat_mode_q             <=  mmio_eng_mmio_lat_mode;
            mmio_eng_mmio_lat_mode_sz_512_st_q   <=  mmio_eng_mmio_lat_mode_sz_512_st;
            mmio_eng_mmio_lat_mode_sz_512_ld_q   <=  mmio_eng_mmio_lat_mode_sz_512_ld;
            mmio_eng_mmio_lat_extra_read_q       <=  mmio_eng_mmio_lat_extra_read;
	    send_interrupt_q                     <= send_interrupt_d;
	    send_wkhstthrd_q                     <= send_wkhstthrd_d;
	    send_wkhstthrd_intrpt_q              <= send_wkhstthrd_intrpt_d;
        end


      if (main_idle_st_int)
        begin
          mmio_eng_type_ld_q                 <= mmio_eng_type_ld;
          mmio_eng_type_st_q                 <= mmio_eng_type_st;
	  base_addr_q[63:12]                 <= mmio_eng_base_addr[63:12];
	  offset_mask_q[31:12]               <= mmio_eng_offset_mask[31:12];
	  mmio_eng_pasid_q[9:0]              <= mmio_eng_pasid[9:0];
          step_size_256_q                    <= step_size_256_d;
        end

      use_pasid_for_actag_q                  <= use_pasid_for_actag_d;

      cmd_is_intrpt_q                        <= cmd_is_intrpt_d;
      cmd_is_wkhstthrd_q                     <= cmd_is_wkhstthrd_d;

      mmio_eng_error_intrpt_enable_q         <= mmio_eng_error_intrpt_enable;
      mmio_eng_wkhstthrd_intrpt_enable_q     <= mmio_eng_wkhstthrd_intrpt_enable;
      mmio_eng_extra_write_mode_q            <= mmio_eng_extra_write_mode;

      main_seq_q[4:0]                        <= main_seq_d[4:0];        

      offset_addr_q[31:7]                    <= offset_addr_d[31:7];

      toggle_ld_addr_bit8_q                  <= toggle_ld_addr_bit8_d;
      cpy_ld_ea_int_q[63:7]                  <= cpy_ld_ea_int_d[63:7];

      xtouch_pg_size_q[5:0]                  <= xtouch_pg_size_d[5:0];
      inc_addr_q                             <= inc_addr_d;

      if (xtouch_addr_en)
       begin
         xtouch_addr_q[31:12]                <= xtouch_addr_d[31:12];
       end

      mmio_eng_xtouch_enable_q               <= mmio_eng_xtouch_enable;
      mmio_eng_xtouch_pg_n_q[1:0]            <= mmio_eng_xtouch_pg_n[1:0];

    end

endmodule
module afp3_eng_fsm_main
  (

    input                 clock                                           
  , input                 reset


  , input                 mmio_eng_use_pasid_for_actag
  , input                 mmio_eng_enable
  , input                 mmio_eng_type_ld
  , input                 mmio_eng_type_st
  , input         [63:12] mmio_eng_base_addr
  , input         [31:12] mmio_eng_offset_mask
  , input           [1:0] mmio_eng_ld_size
  , input           [1:0] mmio_eng_st_size
  , input           [9:0] mmio_eng_pasid
  , input                 mmio_eng_send_interrupt
  , input                 mmio_eng_send_wkhstthrd
  , input                 mmio_eng_error_intrpt_enable
  , input                 mmio_eng_wkhstthrd_intrpt_enable
  , input                 mmio_eng_extra_write_mode
  , input                 mmio_eng_mmio_lat_mode
  , input                 mmio_eng_mmio_lat_mode_sz_512_st
  , input                 mmio_eng_mmio_lat_mode_sz_512_ld
  , input                 mmio_eng_mmio_lat_extra_read
  , input          [63:7] mmio_eng_mmio_lat_ld_ea
  , input                 mmio_eng_xtouch_enable
  , input           [1:0] mmio_eng_xtouch_pg_n
  , input           [5:0] mmio_eng_xtouch_pg_size



  , input                 actag_seq_done
  , input                 arb_eng_tags_idle
  , input                 arb_eng_ld_gnt
  , input                 arb_eng_st_gnt

  , input                 xtouch_error_q
  , input                 cpy_ld_error_q
  , input                 cpy_st_error_q
  , input                 wkhstthrd_error_q
  , input                 atomic_error_q


  , input                 intrpt_idle_st
  , input                 intrpt_rtry_idle_st
  , input                 wkhstthrd_idle_st
  , input                 wkhstthrd_rtry_idle_st
  , input                 atomic_idle_st
  , input                 atomic_rtry_idle_st


  , output                main_seq_error

  , output          [4:0] main_state
  , output                main_idle_st
  , output                main_actag_st
  , output                main_send_st
  , output                main_err_intrpt_st
  , output                main_stop_st

  , output                start_actag_seq

  , output                start_xtouch_seq
  , output                start_cpy_ld_seq
  , output                start_cpy_st_seq
  , output                start_wkhstthrd_seq

  , output                start_atomic_seq
  , output                start_intrpt_seq


  , output                main_seq_done

  , output         [63:6] cpy_ld_ea_q
  , output         [63:6] cpy_st_ea_q
  , output         [63:0] xtouch_ea_q
  , output                cpy_ld_idle_st
  , output                cpy_st_idle_st
  , output                cpy_ld_wt4rsp_st
  , output                cpy_st_wt4rsp_st
  , output                cpy_ld_type_sel
  , output                cpy_st_type_sel

  , output                we_cmd_is_intrpt_q
  , output                we_cmd_is_wkhstthrd_q

  , output          [9:0] cmd_pasid_q
  , output                eng_arb_init
  , output                eng_arb_ld_enable
  , output                eng_arb_st_enable

  );






  wire            skip_assign_actag;
  wire            misc_idle;
  wire      [1:0] intrpt_cmd;

  wire            any_major_error;
  wire            stop_for_wkhstthrd_error;
  wire            all_tags_idle;
  wire            main_seq_err_int;
  wire            main_idle_st_int;
  wire     [12:0] main_seq_sel;
  reg       [6:0] main_seq;

  wire            start_capture;

  wire            ld_enable;
  wire            st_enable;
  wire            send_error_intrpt;
  wire            start_intrpt;
  wire            start_wkhstthrd;
  wire            xtouch_enable;


  wire            inc_addr;
  wire     [31:7] offset_addr_plus1;
  wire     [31:7] offset_addr_plus2;
  wire     [31:7] offset_addr_plus1or2;
  wire     [31:7] next_addr;
  wire            toggle_addr_for_mmio_lat;
  wire     [31:7] toggle_addr;
  wire     [63:6] curr_addr;

  wire            extra_read_mode;
  wire            toggle_ld_addr_for_extra_read;
  wire            extra_read_ea_bit8;


  wire            xtouch_pg_size_4k;
  wire            xtouch_pg_size_64k;
  wire            xtouch_pg_size_2m;
  wire            xtouch_pg_size_16m;
  wire            xtouch_pg_size_1g;

  reg      [63:0] xtouch_addr_mask;
  wire            crossed_page;
  wire      [7:0] xtouch_adder_sel;
  reg     [31:12] xtouch_addr_adder;
  wire    [31:12] xtouch_plus_n;





  wire             use_pasid_for_actag_d;
  reg              use_pasid_for_actag_q;


  reg              mmio_eng_enable_q;


  reg              mmio_eng_mmio_lat_mode_q;


  reg              mmio_eng_mmio_lat_mode_sz_512_st_q;


  reg              mmio_eng_mmio_lat_mode_sz_512_ld_q;


  reg              mmio_eng_mmio_lat_extra_read_q;


  reg              mmio_eng_type_ld_q;


  reg              mmio_eng_type_st_q;

  reg      [63:12] base_addr_q;

  reg      [31:12] offset_mask_q;

  reg        [9:0] mmio_eng_pasid_q;

  wire       [4:0] main_seq_d;
 `ifdef MARK_DEBUG_ACTIVE (* mark_debug = "TRUE" *) `endif
  reg        [4:0] main_seq_q;

  wire             step_size_256_d;
  reg              step_size_256_q;

  wire      [31:7] offset_addr_d;
  reg       [31:7] offset_addr_q;

  wire             toggle_ld_addr_bit8_d;
  reg              toggle_ld_addr_bit8_q;

  wire      [63:7] cpy_ld_ea_int_d;
  reg       [63:7] cpy_ld_ea_int_q;

  wire       [5:0] xtouch_pg_size_d;
  reg        [5:0] xtouch_pg_size_q;

  wire             inc_addr_d;
  reg              inc_addr_q;

  wire             xtouch_addr_en;
  wire     [31:12] xtouch_addr_d;
  reg      [31:12] xtouch_addr_q;

  wire             send_interrupt_d;
  reg              send_interrupt_q;

  wire             send_wkhstthrd_d;
  reg              send_wkhstthrd_q;

  wire             send_wkhstthrd_intrpt_d;
  reg              send_wkhstthrd_intrpt_q;

  wire             cmd_is_intrpt_d;
  reg              cmd_is_intrpt_q;

  wire             cmd_is_wkhstthrd_d;
  reg              cmd_is_wkhstthrd_q;


  reg              mmio_eng_error_intrpt_enable_q;


  reg              mmio_eng_wkhstthrd_intrpt_enable_q;


  reg              mmio_eng_extra_write_mode_q;


  reg              mmio_eng_xtouch_enable_q;


  reg        [1:0] mmio_eng_xtouch_pg_n_q;











  assign  use_pasid_for_actag_d   =   mmio_eng_use_pasid_for_actag;


  assign  skip_assign_actag       =  ( use_pasid_for_actag_q );

  assign  cmd_pasid_q[9:0]  =  mmio_eng_pasid_q[9:0];





  assign  send_interrupt_d  =  mmio_eng_send_interrupt | (send_interrupt_q & ~start_intrpt);

  assign  send_wkhstthrd_d  =  mmio_eng_send_wkhstthrd | (send_wkhstthrd_q & ~start_wkhstthrd);


  assign  misc_idle  =  intrpt_idle_st    & intrpt_rtry_idle_st &
                        wkhstthrd_idle_st & wkhstthrd_rtry_idle_st &
                        atomic_idle_st    & atomic_rtry_idle_st;

  assign  send_wkhstthrd_intrpt_d  =  ( wkhstthrd_error_q | send_wkhstthrd_intrpt_q) & ~start_intrpt & mmio_eng_wkhstthrd_intrpt_enable_q;


  assign  intrpt_cmd[1:0]    =  (start_intrpt & send_error_intrpt)       ?  2'b00 :
                                (start_intrpt & send_wkhstthrd_intrpt_q) ?  2'b01 :
                                (start_intrpt & send_interrupt_q)        ?  2'b10 :
                                (start_wkhstthrd)                        ?  2'b01 :
                                                                         { cmd_is_intrpt_q, cmd_is_wkhstthrd_q };

  assign  cmd_is_intrpt_d    = intrpt_cmd[1];
  assign  cmd_is_wkhstthrd_d = intrpt_cmd[0];

  assign  we_cmd_is_intrpt_q    =  cmd_is_intrpt_q;
  assign  we_cmd_is_wkhstthrd_q =  cmd_is_wkhstthrd_q;






  mcp3_ohc05  main_seq_err (
    .one_hot_vector   ( main_seq_q[4:0] ),
    .one_hot_error    ( main_seq_err_int )
  );

  assign  any_major_error  =  xtouch_error_q | cpy_ld_error_q | cpy_st_error_q | atomic_error_q ;

  assign  stop_for_wkhstthrd_error =  wkhstthrd_error_q & ~mmio_eng_wkhstthrd_intrpt_enable_q;

  assign  all_tags_idle  =  arb_eng_tags_idle & misc_idle;


  assign  main_idle_st      =  main_seq_q[0];
  assign  main_actag_st     =  main_seq_q[1];
  assign  main_send_st      =  main_seq_q[2];
  assign  main_err_intrpt_st=  main_seq_q[3];
  assign  main_stop_st      =  main_seq_q[4];

  assign  main_idle_st_int  =  main_seq_q[0];
              

  assign  main_seq_sel[12:0] = { mmio_eng_enable_q, skip_assign_actag, actag_seq_done, any_major_error, mmio_eng_error_intrpt_enable_q, stop_for_wkhstthrd_error, start_intrpt, all_tags_idle, main_seq_q[4:0] };

  always @*
    begin
      casez ( main_seq_sel[12:0] )


















            13'b00?_?????_00001 :  main_seq[6:0] =  7'b00_00001 ;
            13'b10?_0????_00001 :  main_seq[6:0] =  7'b11_00010 ;
            13'b11?_0????_00001 :  main_seq[6:0] =  7'b01_00100 ;

            13'b??0_?????_00010 :  main_seq[6:0] =  7'b00_00010 ;
            13'b1?1_?????_00010 :  main_seq[6:0] =  7'b00_00100 ;
            13'b0?1_?????_00010 :  main_seq[6:0] =  7'b00_00001 ;

            13'b1??_0?0??_00100 :  main_seq[6:0] =  7'b00_00100 ;
            13'b0??_?????_00100 :  main_seq[6:0] =  7'b00_10000 ;
            13'b1??_??1??_00100 :  main_seq[6:0] =  7'b00_10000 ;
            13'b1??_100??_00100 :  main_seq[6:0] =  7'b00_10000 ;
            13'b1??_110??_00100 :  main_seq[6:0] =  7'b00_01000 ;

            13'b1??_???0?_01000 :  main_seq[6:0] =  7'b00_01000 ;
            13'b1??_???1?_01000 :  main_seq[6:0] =  7'b00_10000 ;
            13'b0??_?????_01000 :  main_seq[6:0] =  7'b00_10000 ;

            13'b???_????0_10000 :  main_seq[6:0] =  7'b00_10000 ;
            13'b???_????1_10000 :  main_seq[6:0] =  7'b00_00001 ;

            default             :  main_seq[6:0] =  7'b00_00001 ;

      endcase
    end


  assign  start_actag_seq      =  main_seq[6];
  assign  start_capture        =  main_seq[5];


  assign  main_seq_d[4:0]      = ( reset || main_seq_err_int ) ? 5'b1 : main_seq[4:0];


  assign  main_state[4:0]      =  main_seq_q[4:0];

  assign  eng_arb_init         =  start_capture;
  assign  ld_enable            =  main_seq_q[2] & ~mmio_eng_extra_write_mode_q;
  assign  st_enable            =  main_seq_q[2] & ~mmio_eng_extra_write_mode_q;

  assign  send_error_intrpt    =  main_seq_q[3];

  assign  start_intrpt         =  ( (main_seq_q[2] & send_interrupt_q) |
                                    (main_seq_q[2] & send_wkhstthrd_intrpt_q) |
                                    (send_error_intrpt) )  &
                                  misc_idle &
                                  ~send_wkhstthrd_q;

  assign  start_wkhstthrd      =  main_seq_q[2] & send_wkhstthrd_q & misc_idle;

  assign  xtouch_enable        =  main_seq_q[2] & mmio_eng_xtouch_enable_q;

  assign  cpy_ld_idle_st       =  main_seq_q[0];
  assign  cpy_st_idle_st       =  main_seq_q[0];

  assign  cpy_ld_wt4rsp_st     =  main_seq_q[2] | main_seq_q[3] | main_seq_q[4];
  assign  cpy_st_wt4rsp_st     =  main_seq_q[2] | main_seq_q[3] | main_seq_q[4];

  assign  eng_arb_ld_enable    =  ld_enable;
  assign  eng_arb_st_enable    =  st_enable;

  assign  cpy_ld_type_sel      =  mmio_eng_type_ld_q;
  assign  cpy_st_type_sel      =  mmio_eng_type_st_q;

  assign  start_xtouch_seq     =  xtouch_enable & crossed_page;
  assign  start_cpy_ld_seq     =  ld_enable;
  assign  start_cpy_st_seq     =  st_enable;
  assign  start_wkhstthrd_seq  =  start_wkhstthrd;

  assign  start_atomic_seq     =  1'b0;
  assign  start_intrpt_seq     =  start_intrpt;



  assign  main_seq_done        =  main_idle_st_int;


  assign  main_seq_error  =  main_seq_err_int;






  assign  step_size_256_d  =  (mmio_eng_ld_size[1:0] == 2'b11) || (mmio_eng_st_size[1:0] == 2'b11);

  assign  inc_addr  =  (arb_eng_ld_gnt | arb_eng_st_gnt) &
                        ~mmio_eng_mmio_lat_mode_q & ~mmio_eng_extra_write_mode_q;

  assign  offset_addr_plus1[31:7]  =  offset_addr_q[31:7] + 25'b1;
  assign  offset_addr_plus2[31:7]  =  {(offset_addr_q[31:8] + 24'b1), 1'b0};

  assign  offset_addr_plus1or2[31:7]  = step_size_256_q ?  offset_addr_plus2[31:7]  :
                                                           offset_addr_plus1[31:7];

  assign  next_addr[31:12]  =  (base_addr_q[31:12]          & ~offset_mask_q[31:12]) |
	                       (offset_addr_plus1or2[31:12] &  offset_mask_q[31:12]);

  assign  next_addr[11:7]   =  offset_addr_plus1or2[11:7];  


  assign  toggle_addr_for_mmio_lat  = mmio_eng_mmio_lat_mode_q & mmio_eng_mmio_lat_mode_sz_512_st_q & arb_eng_st_gnt;
  assign  toggle_addr[31:7] =  { offset_addr_q[31:9], (~offset_addr_q[8]), offset_addr_q[7] };

  assign  offset_addr_d[31:7]  =  start_capture ? { base_addr_q[31:12] , 5'b0 } :
                                  inc_addr      ?   next_addr[31:7] :
                       toggle_addr_for_mmio_lat ?   toggle_addr[31:7] :
                                                    offset_addr_q[31:7];

  assign  curr_addr[63:32]   =  base_addr_q[63:32];
  assign  curr_addr[31:7]    =  offset_addr_q[31:7];
  assign  curr_addr[6]       =  1'b0;

  assign  cpy_st_ea_q[63:6]  =  curr_addr[63:6];




  assign  extra_read_mode = mmio_eng_mmio_lat_mode_q & mmio_eng_mmio_lat_extra_read_q;
  assign  toggle_ld_addr_for_extra_read  = mmio_eng_mmio_lat_mode_q & mmio_eng_mmio_lat_mode_sz_512_ld_q & mmio_eng_mmio_lat_extra_read_q & arb_eng_ld_gnt;

  assign  toggle_ld_addr_bit8_d  =  reset | (~extra_read_mode) ? 1'b0 :
                                    toggle_ld_addr_for_extra_read ? (~toggle_ld_addr_bit8_q) :
                                                                      toggle_ld_addr_bit8_q;

  assign  extra_read_ea_bit8  =  mmio_eng_mmio_lat_ld_ea[8] | toggle_ld_addr_bit8_d;

  assign  cpy_ld_ea_int_d[63:7]  = extra_read_mode ? { mmio_eng_mmio_lat_ld_ea[63:9], extra_read_ea_bit8, mmio_eng_mmio_lat_ld_ea[7]} :
                                                     { base_addr_q[63:32], offset_addr_d[31:7] };

  assign  cpy_ld_ea_q[63:6]  =  { cpy_ld_ea_int_q[63:7] , 1'b0 };
















  assign  xtouch_pg_size_d[5:0]  = mmio_eng_xtouch_pg_size[5:0];

  assign  xtouch_pg_size_4k   =  ( xtouch_pg_size_q[5:0] == 6'b00_1100 );
  assign  xtouch_pg_size_64k  =  ( xtouch_pg_size_q[5:0] == 6'b01_0000 );
  assign  xtouch_pg_size_2m   =  ( xtouch_pg_size_q[5:0] == 6'b01_0101 );
  assign  xtouch_pg_size_16m  =  ( xtouch_pg_size_q[5:0] == 6'b01_1000 );
  assign  xtouch_pg_size_1g   =  ( xtouch_pg_size_q[5:0] == 6'b01_1110 );


  always @*
    begin
    casez ( xtouch_pg_size_q[5:0] )








            6'b01_1110 :  xtouch_addr_mask[63:0] = 64'h0000_0000_3FFF_FFFF ;
            6'b01_1000 :  xtouch_addr_mask[63:0] = 64'h0000_0000_00FF_FFFF ;
            6'b01_0101 :  xtouch_addr_mask[63:0] = 64'h0000_0000_001F_FFFF ;
            6'b01_0000 :  xtouch_addr_mask[63:0] = 64'h0000_0000_0000_FFFF ;
            6'b00_1100 :  xtouch_addr_mask[63:0] = 64'h0000_0000_0000_0FFF ;

            default    :  xtouch_addr_mask[63:0] = 64'h0000_0000_0000_0FFF ;

      endcase
    end



  assign  inc_addr_d  = inc_addr;

  assign  crossed_page  =  inc_addr_q  &  ~(| (curr_addr[63:6] & xtouch_addr_mask[63:6]) );




  assign  xtouch_adder_sel[7:0]  =  { mmio_eng_xtouch_pg_n_q[1:0], xtouch_pg_size_q[5:0] };

  always @*
    begin
    casez ( xtouch_adder_sel[7:0] )








            8'b00_00_1100 :  xtouch_addr_adder[31:12] = 20'h00001 ;
            8'b01_00_1100 :  xtouch_addr_adder[31:12] = 20'h00002 ;
            8'b10_00_1100 :  xtouch_addr_adder[31:12] = 20'h00003 ;
            8'b11_00_1100 :  xtouch_addr_adder[31:12] = 20'h00004 ;

            8'b00_01_0000 :  xtouch_addr_adder[31:12] = 20'h00010 ;
            8'b01_01_0000 :  xtouch_addr_adder[31:12] = 20'h00020 ;
            8'b10_01_0000 :  xtouch_addr_adder[31:12] = 20'h00030 ;
            8'b11_01_0000 :  xtouch_addr_adder[31:12] = 20'h00040 ;

            8'b00_01_0101 :  xtouch_addr_adder[31:12] = 20'h00200 ;
            8'b01_01_0101 :  xtouch_addr_adder[31:12] = 20'h00400 ;
            8'b10_01_0101 :  xtouch_addr_adder[31:12] = 20'h00600 ;
            8'b11_01_0101 :  xtouch_addr_adder[31:12] = 20'h00800 ;

            8'b00_01_1000 :  xtouch_addr_adder[31:12] = 20'h01000 ;
            8'b01_01_1000 :  xtouch_addr_adder[31:12] = 20'h01000 ;
            8'b10_01_1000 :  xtouch_addr_adder[31:12] = 20'h01000 ;
            8'b11_01_1000 :  xtouch_addr_adder[31:12] = 20'h01000 ;

            8'b00_01_1110 :  xtouch_addr_adder[31:12] = 20'h40000 ;
            8'b01_01_1110 :  xtouch_addr_adder[31:12] = 20'h80000 ;
            8'b10_01_1110 :  xtouch_addr_adder[31:12] = 20'hC0000 ;







            default       :  xtouch_addr_adder[31:12] = 20'h00001 ;

      endcase
    end

  assign  xtouch_plus_n[31:12]  =  curr_addr[31:12] + xtouch_addr_adder[31:12];

  assign  xtouch_addr_en  =  crossed_page & xtouch_enable;
  assign  xtouch_addr_d[31:12]  =  (base_addr_q[31:12]   & ~offset_mask_q[31:12]) |
	                         (xtouch_plus_n[31:12]   &  offset_mask_q[31:12]);

  assign  xtouch_ea_q[63:0]  =  { base_addr_q[63:32], xtouch_addr_q[31:12], 12'b0 };





  always @ ( posedge clock )
    begin

      if (reset)
        begin
            mmio_eng_enable_q                    <=  1'b0;
            mmio_eng_mmio_lat_mode_q             <=  1'b0;
            mmio_eng_mmio_lat_mode_sz_512_st_q   <=  1'b0;
            mmio_eng_mmio_lat_mode_sz_512_ld_q   <=  1'b0;
            mmio_eng_mmio_lat_extra_read_q       <=  1'b0;
	    send_interrupt_q                     <=  1'b0;
	    send_wkhstthrd_q                     <=  1'b0;
	    send_wkhstthrd_intrpt_q              <=  1'b0;
        end
      else
        begin
            mmio_eng_enable_q                    <=  mmio_eng_enable;
            mmio_eng_mmio_lat_mode_q             <=  mmio_eng_mmio_lat_mode;
            mmio_eng_mmio_lat_mode_sz_512_st_q   <=  mmio_eng_mmio_lat_mode_sz_512_st;
            mmio_eng_mmio_lat_mode_sz_512_ld_q   <=  mmio_eng_mmio_lat_mode_sz_512_ld;
            mmio_eng_mmio_lat_extra_read_q       <=  mmio_eng_mmio_lat_extra_read;
	    send_interrupt_q                     <= send_interrupt_d;
	    send_wkhstthrd_q                     <= send_wkhstthrd_d;
	    send_wkhstthrd_intrpt_q              <= send_wkhstthrd_intrpt_d;
        end


      if (main_idle_st_int)
        begin
          mmio_eng_type_ld_q                 <= mmio_eng_type_ld;
          mmio_eng_type_st_q                 <= mmio_eng_type_st;
	  base_addr_q[63:12]                 <= mmio_eng_base_addr[63:12];
	  offset_mask_q[31:12]               <= mmio_eng_offset_mask[31:12];
	  mmio_eng_pasid_q[9:0]              <= mmio_eng_pasid[9:0];
          step_size_256_q                    <= step_size_256_d;
        end

      use_pasid_for_actag_q                  <= use_pasid_for_actag_d;

      cmd_is_intrpt_q                        <= cmd_is_intrpt_d;
      cmd_is_wkhstthrd_q                     <= cmd_is_wkhstthrd_d;

      mmio_eng_error_intrpt_enable_q         <= mmio_eng_error_intrpt_enable;
      mmio_eng_wkhstthrd_intrpt_enable_q     <= mmio_eng_wkhstthrd_intrpt_enable;
      mmio_eng_extra_write_mode_q            <= mmio_eng_extra_write_mode;

      main_seq_q[4:0]                        <= main_seq_d[4:0];        

      offset_addr_q[31:7]                    <= offset_addr_d[31:7];

      toggle_ld_addr_bit8_q                  <= toggle_ld_addr_bit8_d;
      cpy_ld_ea_int_q[63:7]                  <= cpy_ld_ea_int_d[63:7];

      xtouch_pg_size_q[5:0]                  <= xtouch_pg_size_d[5:0];
      inc_addr_q                             <= inc_addr_d;

      if (xtouch_addr_en)
       begin
         xtouch_addr_q[31:12]                <= xtouch_addr_d[31:12];
       end

      mmio_eng_xtouch_enable_q               <= mmio_eng_xtouch_enable;
      mmio_eng_xtouch_pg_n_q[1:0]            <= mmio_eng_xtouch_pg_n[1:0];

    end

endmodule