data/full_repos/permissive/146324357/resampler.v
 line:11: before: "real"
1: b'%Warning-WIDTH: data/full_repos/permissive/146324357/resampler.v:59: Operator ITORD expects 32 bits on the LHS, but LHS\'s VARREF \'wr_ptr\' generates 4 bits.\n                                                                   : ... In instance resampler\n  rd_ptr = wr_ptr - interp_grp_delay/input_period;\n           ^~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-REALCVT: data/full_repos/permissive/146324357/resampler.v:59: Implicit conversion of real to integer\n  rd_ptr = wr_ptr - interp_grp_delay/input_period;\n                  ^\n%Error: Exiting due to 2 warning(s)\n'
module resampler(
  input real vin,
  input clk,
  output real vout
);


real ts_fifo[16];
real vs_fifo[16];

real input_period = 0.0;
real ts_prev = 0.0;
real ts_sample = 0.0;

real interp_grp_delay = 50000;

reg [3:0] wr_ptr = 0;
reg [3:0] rd_ptr = 0;
reg [3:0] rd_ptr_t0 = 0;
reg [3:0] rd_ptr_t1 = 0;
reg [3:0] rd_ptr_t2 = 0;
reg [3:0] rd_ptr_t3 = 0;

real t0,t1,t2,t3;
real y0,y1,y2,y3;
real L0,L1,L2,L3;
real t,y;



integer ii;

always @(vin)
begin
  input_period = $realtime - ts_prev;  
  ts_fifo[wr_ptr] = $realtime;
  vs_fifo[wr_ptr] = vin;

  wr_ptr = wr_ptr + 1;
  rd_ptr = wr_ptr - interp_grp_delay/input_period;
  ts_prev = $realtime;
end


always @(posedge clk)
begin
  ts_sample = $realtime;

  rd_ptr_t0 = rd_ptr-2;
  rd_ptr_t1 = rd_ptr-1;
  rd_ptr_t2 = rd_ptr;
  rd_ptr_t3 = rd_ptr+1;
  

  
t=ts_sample-interp_grp_delay;
t0=ts_fifo[rd_ptr_t0];
t1=ts_fifo[rd_ptr_t1];
t2=ts_fifo[rd_ptr_t2];
t3=ts_fifo[rd_ptr_t3];
y0=vs_fifo[rd_ptr_t0];
y1=vs_fifo[rd_ptr_t1];
y2=vs_fifo[rd_ptr_t2];
y3=vs_fifo[rd_ptr_t3];
L0=((t-t1)/(t0-t1))*((t-t2)/(t0-t2))*((t-t3)/(t0-t3));
L1=((t-t0)/(t1-t0))*((t-t2)/(t1-t2))*((t-t3)/(t1-t3));
L2=((t-t0)/(t2-t0))*((t-t1)/(t2-t1))*((t-t3)/(t2-t3));
L3=((t-t0)/(t3-t0))*((t-t1)/(t3-t1))*((t-t2)/(t3-t2));
y=L0*y0+L1*y1+L2*y2+L3*y3;

  
end

assign vout = y;

endmodule
module resampler(
  input real vin,
  input clk,
  output real vout
);



real ts_fifo[16];
real vs_fifo[16];

real input_period = 0.0;
real ts_prev = 0.0;
real ts_sample = 0.0;

real interp_grp_delay = 50000;

reg [3:0] wr_ptr = 0;
reg [3:0] rd_ptr = 0;
reg [3:0] rd_ptr_t0 = 0;
reg [3:0] rd_ptr_t1 = 0;
reg [3:0] rd_ptr_t2 = 0;
reg [3:0] rd_ptr_t3 = 0;

real t0,t1,t2,t3;
real y0,y1,y2,y3;
real L0,L1,L2,L3;
real t,y;



integer ii;

always @(vin)
begin
  input_period = $realtime - ts_prev;  
  ts_fifo[wr_ptr] = $realtime;
  vs_fifo[wr_ptr] = vin;

  wr_ptr = wr_ptr + 1;
  rd_ptr = wr_ptr - interp_grp_delay/input_period;
  ts_prev = $realtime;
end


always @(posedge clk)
begin
  ts_sample = $realtime;

  rd_ptr_t0 = rd_ptr-2;
  rd_ptr_t1 = rd_ptr-1;
  rd_ptr_t2 = rd_ptr;
  rd_ptr_t3 = rd_ptr+1;
  

  
t=ts_sample-interp_grp_delay;
t0=ts_fifo[rd_ptr_t0];
t1=ts_fifo[rd_ptr_t1];
t2=ts_fifo[rd_ptr_t2];
t3=ts_fifo[rd_ptr_t3];
y0=vs_fifo[rd_ptr_t0];
y1=vs_fifo[rd_ptr_t1];
y2=vs_fifo[rd_ptr_t2];
y3=vs_fifo[rd_ptr_t3];
L0=((t-t1)/(t0-t1))*((t-t2)/(t0-t2))*((t-t3)/(t0-t3));
L1=((t-t0)/(t1-t0))*((t-t2)/(t1-t2))*((t-t3)/(t1-t3));
L2=((t-t0)/(t2-t0))*((t-t1)/(t2-t1))*((t-t3)/(t2-t3));
L3=((t-t0)/(t3-t0))*((t-t1)/(t3-t1))*((t-t2)/(t3-t2));
y=L0*y0+L1*y1+L2*y2+L3*y3;

  
end

assign vout = y;

endmodule