data/full_repos/permissive/200314387/verilog/74670/test.v
 line:50: before: ">"
1: b'%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:6: Cannot find include file: hct74670.v\n`include "hct74670.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/74670,data/full_repos/permissive/200314387/hct74670.v\n             data/full_repos/permissive/200314387/verilog/74670,data/full_repos/permissive/200314387/hct74670.v.v\n             data/full_repos/permissive/200314387/verilog/74670,data/full_repos/permissive/200314387/hct74670.v.sv\n             hct74670.v\n             hct74670.v.v\n             hct74670.v.sv\n             obj_dir/hct74670.v\n             obj_dir/hct74670.v.v\n             obj_dir/hct74670.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:7: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:26: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:27: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, regfile);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:56: Define or directive not defined: \'`equals\'\n        `equals(rd_data , undefined_data, "nothing written so all data should be x");\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:56: syntax error, unexpected \',\'\n        `equals(rd_data , undefined_data, "nothing written so all data should be x");\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74670/test.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:61: Define or directive not defined: \'`equals\'\n        `equals(rd_data , undefined_data, "nothing written yet due to PD so all data should be x");\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:61: syntax error, unexpected \',\'\n        `equals(rd_data , undefined_data, "nothing written yet due to PD so all data should be x");\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74670/test.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:63: Define or directive not defined: \'`equals\'\n        `equals(rd_data , 10, "write propagated");\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:63: syntax error, unexpected \',\'\n        `equals(rd_data , 10, "write propagated");\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74670/test.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #25\n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:68: Define or directive not defined: \'`equals\'\n        `equals(rd_data , 10, "write enabled - data changed - output not propagated yet");\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:68: syntax error, unexpected \',\'\n        `equals(rd_data , 10, "write enabled - data changed - output not propagated yet");\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74670/test.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:70: Define or directive not defined: \'`equals\'\n        `equals(rd_data , 1, "write enabled and write data changed - should have propagated to read");\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:70: syntax error, unexpected \',\'\n        `equals(rd_data , 1, "write enabled and write data changed - should have propagated to read");\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74670/test.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #24\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74670/test.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:78: Define or directive not defined: \'`equals\'\n        `equals(rd_data , 1, "write disabled - retains value");\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:78: syntax error, unexpected \',\'\n        `equals(rd_data , 1, "write disabled - retains value");\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74670/test.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:83: Define or directive not defined: \'`equals\'\n        `equals(rd_data , 15, "write enabled location 2");\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:83: syntax error, unexpected \',\'\n        `equals(rd_data , 15, "write enabled location 2");\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74670/test.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #29\n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:88: Define or directive not defined: \'`equals\'\n        `equals(rd_data , zed_data, "read disabled");\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74670/test.v:88: syntax error, unexpected \',\'\n        `equals(rd_data , zed_data, "read disabled");\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74670/test.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #29\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74670/test.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #29\n        ^\n%Error: Exiting due to 20 error(s), 10 warning(s)\n'
module icarus_tb();
    
    logic _wr_en;
    logic _rd_en;
    logic [1:0] wr_addr, rd_addr;
    logic [3:0] wr_data, rd_data;
    
    hct74670 regfile(
    _wr_en, wr_addr,  wr_data,
    _rd_en, rd_addr,  rd_data
    );
    
    
    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0, regfile);
        
        $display ("");
        $display ($time,"   %s   %s | %s <= %s  | %s => %s", "_wr_en", "_rd_en",   "wr_addr", "wr_data", "rd_addr", "rd_data");
`ifndef verilator        
        $monitor ($time,"   %5b   %5b | %7b <= %7b  | %7b => %7b", _wr_en, _rd_en,   wr_addr, wr_data, rd_addr, rd_data);
`endif
    end
    
    



    
    initial begin
        parameter low      = 1'b0;
        parameter high     = 1'b1;
        parameter enabled  = low;
        parameter disabled = high;
        
        parameter undefined_data = 4'bx;
        parameter zed_data       = 4'bz;
        
        $display("%9t ", $time, " init");
        _rd_en   = enabled;
        wr_addr = 0;
        wr_data = 10;
        rd_addr = 0;
        #10
        `equals(rd_data , undefined_data, "nothing written so all data should be x");
        
        _wr_en = enabled;
        $display("%9t ", $time, " _wr_en=0");
        #5
        `equals(rd_data , undefined_data, "nothing written yet due to PD so all data should be x");
        #25
        `equals(rd_data , 10, "write propagated");
        
        wr_data = 1;
        $display("%9t ", $time, " wr_data=1");
        #5
        `equals(rd_data , 10, "write enabled - data changed - output not propagated yet");
        #24
        `equals(rd_data , 1, "write enabled and write data changed - should have propagated to read");
        
        #5
        
        wr_data = 15;
        $display("%9t ", $time, " wr_data=15 _wr_en=1");
        _wr_en   = disabled;
        #1
        `equals(rd_data , 1, "write disabled - retains value");
        
        _wr_en = enabled;
        $display("%9t ", $time, " _wr_en=0");
        #29
        `equals(rd_data , 15, "write enabled location 2");
        
        _rd_en = disabled;
        $display("%9t ", $time, " _rd_en=1");
        #29
        `equals(rd_data , zed_data, "read disabled");
        
        #29
        $finish;
    end
    
    
endmodule
module icarus_tb();

    
    logic _wr_en;
    logic _rd_en;
    logic [1:0] wr_addr, rd_addr;
    logic [3:0] wr_data, rd_data;
    
    hct74670 regfile(
    _wr_en, wr_addr,  wr_data,
    _rd_en, rd_addr,  rd_data
    );
    
    
    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0, regfile);
        
        $display ("");
        $display ($time,"   %s   %s | %s <= %s  | %s => %s", "_wr_en", "_rd_en",   "wr_addr", "wr_data", "rd_addr", "rd_data");
`ifndef verilator        
        $monitor ($time,"   %5b   %5b | %7b <= %7b  | %7b => %7b", _wr_en, _rd_en,   wr_addr, wr_data, rd_addr, rd_data);
`endif
    end
    
    



    
    initial begin
        parameter low      = 1'b0;
        parameter high     = 1'b1;
        parameter enabled  = low;
        parameter disabled = high;
        
        parameter undefined_data = 4'bx;
        parameter zed_data       = 4'bz;
        
        $display("%9t ", $time, " init");
        _rd_en   = enabled;
        wr_addr = 0;
        wr_data = 10;
        rd_addr = 0;
        #10
        `equals(rd_data , undefined_data, "nothing written so all data should be x");
        
        _wr_en = enabled;
        $display("%9t ", $time, " _wr_en=0");
        #5
        `equals(rd_data , undefined_data, "nothing written yet due to PD so all data should be x");
        #25
        `equals(rd_data , 10, "write propagated");
        
        wr_data = 1;
        $display("%9t ", $time, " wr_data=1");
        #5
        `equals(rd_data , 10, "write enabled - data changed - output not propagated yet");
        #24
        `equals(rd_data , 1, "write enabled and write data changed - should have propagated to read");
        
        #5
        
        wr_data = 15;
        $display("%9t ", $time, " wr_data=15 _wr_en=1");
        _wr_en   = disabled;
        #1
        `equals(rd_data , 1, "write disabled - retains value");
        
        _wr_en = enabled;
        $display("%9t ", $time, " _wr_en=0");
        #29
        `equals(rd_data , 15, "write enabled location 2");
        
        _rd_en = disabled;
        $display("%9t ", $time, " _rd_en=1");
        #29
        `equals(rd_data , zed_data, "read disabled");
        
        #29
        $finish;
    end
    
    
endmodule