data/full_repos/permissive/107499099/mips_de2-115/MIPS/ram8x2048_sim.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/MIPS/ram8x2048_sim.v:43: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 11 bits.\n                                                                                         : ... In instance ram8x2048_sim\n  assign word_addr = ram_addr[12:2];\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/MIPS/ram8x2048_sim.v:48: Bit extraction of array[2048:0] requires 12 bit index, not 6 bits.\n                                                                                         : ... In instance ram8x2048_sim\n      mem[word_addr] <= ram_write_data;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/MIPS/ram8x2048_sim.v:55: Bit extraction of array[2048:0] requires 12 bit index, not 6 bits.\n                                                                                         : ... In instance ram8x2048_sim\n      read_data = mem[word_addr];\n                     ^\n%Error: Exiting due to 3 warning(s)\n'
module ram8x2048_sim (clk, ram_addr, ram_write_enable,
		      ram_write_data, ram_read_data, key_ram_addr, key_ram_wdata , key_ram_wen);


  input                       clk;
  input  [12:0]          ram_addr;
  input          ram_write_enable;
  input  [31:0]    ram_write_data;
  input  [12:0]     key_ram_addr;
  input  [31:0]    key_ram_wdata;
  input              key_ram_wen;
   

  output [31:0]     ram_read_data;

  reg    [31:0]         mem[0:2048];
  reg    [31:0]	        read_data;


  wire    [5:0]         word_addr;

  assign word_addr = ram_addr[12:2];


  always @(posedge clk) begin
    if (ram_write_enable == 1'b1) begin
      mem[word_addr] <= ram_write_data;
    end
  end


  always @(word_addr or ram_write_enable or ram_write_data) begin
    if (ram_write_enable == 1'b0) begin
      read_data = mem[word_addr];
    end else begin
      read_data = ram_write_data;
    end
  end

  assign ram_read_data = ((key_ram_addr == `SCAN_ASCII_ADDR)
                            && (key_ram_wen == `SCAN_ASCII_WEN)
                            && (ram_addr == `SCAN_ASCII_ADDR)
                            && (ram_write_enable == 1'b0)) ? key_ram_wdata : read_data;

endmodule
module ram8x2048_sim (clk, ram_addr, ram_write_enable,
		      ram_write_data, ram_read_data, key_ram_addr, key_ram_wdata , key_ram_wen);



  input                       clk;
  input  [12:0]          ram_addr;
  input          ram_write_enable;
  input  [31:0]    ram_write_data;
  input  [12:0]     key_ram_addr;
  input  [31:0]    key_ram_wdata;
  input              key_ram_wen;
   

  output [31:0]     ram_read_data;

  reg    [31:0]         mem[0:2048];
  reg    [31:0]	        read_data;


  wire    [5:0]         word_addr;

  assign word_addr = ram_addr[12:2];


  always @(posedge clk) begin
    if (ram_write_enable == 1'b1) begin
      mem[word_addr] <= ram_write_data;
    end
  end


  always @(word_addr or ram_write_enable or ram_write_data) begin
    if (ram_write_enable == 1'b0) begin
      read_data = mem[word_addr];
    end else begin
      read_data = ram_write_data;
    end
  end

  assign ram_read_data = ((key_ram_addr == `SCAN_ASCII_ADDR)
                            && (key_ram_wen == `SCAN_ASCII_WEN)
                            && (ram_addr == `SCAN_ASCII_ADDR)
                            && (ram_write_enable == 1'b0)) ? key_ram_wdata : read_data;

endmodule