data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v
'utf-8' codec can't decode byte 0xb5 in position 533: invalid start byte
1: b'%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = ~CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #25 D = ~D;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #150 RESET=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #50 RESET=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #200 $finish;\n    ^\n%Error: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:50: Unsupported: Verilog 1995 force\n    #50 force assign_deassign.q = 1\'b1;\n        ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #50 force assign_deassign.q = 1\'b1;\n    ^\n%Error: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:51: Unsupported: Verilog 1995 release\n    #100 release assign_deassign.q;\n         ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #100 release assign_deassign.q;\n    ^\n%Error: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:61: Unsupported: Verilog 1995 force\n    #50 force out = a | b & c;\n        ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #50 force out = a | b & c;\n    ^\n%Error: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:62: Unsupported: Verilog 1995 release\n    #50 release out;\n        ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/169574047/practical_modeling/practical_modeling.srcs/sources_1/new/force_release.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #50 release out;\n    ^\n%Error: Exiting due to 4 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module force_release;

reg D,CLK,RESET;
wire Q,QBar;


assign_deassign d1(Q,QBar,D,CLK,RESET);

always
    #10 CLK = ~CLK;

always
    #25 D = ~D;
        
initial
begin
    D=1; CLK=0; RESET=0;
    #150 RESET=1;
    #50 RESET=0;
    #200 $finish;
end


initial
begin


    #50 force assign_deassign.q = 1'b1;
    #100 release assign_deassign.q;
end


reg a=1, b=0, c=1;
wire out;
assign out = a & b & c;

initial
begin
    #50 force out = a | b & c;
    #50 release out;
end

endmodule
module force_release;


reg D,CLK,RESET;
wire Q,QBar;


assign_deassign d1(Q,QBar,D,CLK,RESET);

always
    #10 CLK = ~CLK;

always
    #25 D = ~D;
        
initial
begin
    D=1; CLK=0; RESET=0;
    #150 RESET=1;
    #50 RESET=0;
    #200 $finish;
end


initial
begin


    #50 force assign_deassign.q = 1'b1;
    #100 release assign_deassign.q;
end


reg a=1, b=0, c=1;
wire out;
assign out = a & b & c;

initial
begin
    #50 force out = a | b & c;
    #50 release out;
end

endmodule