data/full_repos/permissive/122184933/FPGA/fifo.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/122184933/FPGA/fifo.v:52: Signal definition not found, creating implicitly: \'wr_en\'\n if (wr_en) mem[wr_addr[ADDR_BITS-1:0]] <= wr_data;\n     ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/122184933/FPGA/fifo.v:73: Signal definition not found, creating implicitly: \'rd_en\'\n assign rd_en = (ALLOW_UNDERFLOW) ? rd_oe : rd_oe & ~rd_empty;\n        ^~~~~\n%Error: data/full_repos/permissive/122184933/FPGA/fifo.v:39: Cannot find file containing module: \'gray\'\ngray #(.WIDTH(ADDR_BITS + 1)) rd_gray(.clk(rd_clk), .rst(rd_rst), \n^~~~\n        ... Looked in:\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/gray\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/gray.v\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/gray.sv\n             gray\n             gray.v\n             gray.sv\n             obj_dir/gray\n             obj_dir/gray.v\n             obj_dir/gray.sv\n%Error: data/full_repos/permissive/122184933/FPGA/fifo.v:41: Cannot find file containing module: \'gray\'\ngray #(.WIDTH(ADDR_BITS + 1)) wr_gray(.clk(wr_clk), .rst(wr_rst), \n^~~~\n%Error: data/full_repos/permissive/122184933/FPGA/fifo.v:45: Cannot find file containing module: \'sync\'\nsync #(.WIDTH(ADDR_BITS + 1)) rd_sync(.clk(rd_clk), .rst(rd_rst), \n^~~~\n%Error: data/full_repos/permissive/122184933/FPGA/fifo.v:47: Cannot find file containing module: \'sync\'\nsync #(.WIDTH(ADDR_BITS + 1)) wr_sync(.clk(wr_clk), .rst(wr_rst), \n^~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module fifo # (

	parameter DATA_BITS = 8,

	parameter ADDR_BITS = 4,

	parameter ALLOW_OVERFLOW = 0,

	parameter ALLOW_UNDERFLOW = 0
)	
(

	input wire wr_clk, wr_rst, wr_we,

	input wire [DATA_BITS-1:0] wr_data,

	output wire wr_full,
	

	input wire rd_clk, rd_rst, rd_oe,

	output wire [DATA_BITS-1:0] rd_data,

	output wire rd_empty
);


wire [ADDR_BITS : 0] rd_addr, wr_addr;

wire [ADDR_BITS : 0] rd_addr_wr_domain, wr_addr_rd_domain;


reg [DATA_BITS-1:0] mem [0:(1 << ADDR_BITS) - 1];


gray #(.WIDTH(ADDR_BITS + 1)) rd_gray(.clk(rd_clk), .rst(rd_rst), 
	.enable(rd_en), .out(rd_addr));
gray #(.WIDTH(ADDR_BITS + 1)) wr_gray(.clk(wr_clk), .rst(wr_rst), 
	.enable(wr_en), .out(wr_addr));


sync #(.WIDTH(ADDR_BITS + 1)) rd_sync(.clk(rd_clk), .rst(rd_rst), 
	.in(rd_addr), .out(rd_addr_wr_domain));
sync #(.WIDTH(ADDR_BITS + 1)) wr_sync(.clk(wr_clk), .rst(wr_rst), 
	.in(wr_addr), .out(wr_addr_rd_domain));


always @ (posedge wr_clk)
	if (wr_en) mem[wr_addr[ADDR_BITS-1:0]] <= wr_data;
		

assign rd_data = mem[rd_addr[ADDR_BITS-1:0]];


assign rd_empty = rd_addr == wr_addr_rd_domain;

generate

	if (ADDR_BITS > 1) begin
		assign wr_full = wr_addr == {~rd_addr_wr_domain[ADDR_BITS:ADDR_BITS-1], 
			rd_addr_wr_domain[ADDR_BITS-2:0]};

	end else begin
		assign wr_full = wr_addr == ~rd_addr_wr_domain[ADDR_BITS:ADDR_BITS-1];
	end
endgenerate


generate
	assign rd_en = (ALLOW_UNDERFLOW) ? rd_oe : rd_oe & ~rd_empty;
	assign wr_en = (ALLOW_OVERFLOW) ? wr_we : wr_we & ~wr_full;
endgenerate 

endmodule
module fifo # (

	parameter DATA_BITS = 8,

	parameter ADDR_BITS = 4,

	parameter ALLOW_OVERFLOW = 0,

	parameter ALLOW_UNDERFLOW = 0
)	
(

	input wire wr_clk, wr_rst, wr_we,

	input wire [DATA_BITS-1:0] wr_data,

	output wire wr_full,
	

	input wire rd_clk, rd_rst, rd_oe,

	output wire [DATA_BITS-1:0] rd_data,

	output wire rd_empty
);



wire [ADDR_BITS : 0] rd_addr, wr_addr;

wire [ADDR_BITS : 0] rd_addr_wr_domain, wr_addr_rd_domain;


reg [DATA_BITS-1:0] mem [0:(1 << ADDR_BITS) - 1];


gray #(.WIDTH(ADDR_BITS + 1)) rd_gray(.clk(rd_clk), .rst(rd_rst), 
	.enable(rd_en), .out(rd_addr));
gray #(.WIDTH(ADDR_BITS + 1)) wr_gray(.clk(wr_clk), .rst(wr_rst), 
	.enable(wr_en), .out(wr_addr));


sync #(.WIDTH(ADDR_BITS + 1)) rd_sync(.clk(rd_clk), .rst(rd_rst), 
	.in(rd_addr), .out(rd_addr_wr_domain));
sync #(.WIDTH(ADDR_BITS + 1)) wr_sync(.clk(wr_clk), .rst(wr_rst), 
	.in(wr_addr), .out(wr_addr_rd_domain));


always @ (posedge wr_clk)
	if (wr_en) mem[wr_addr[ADDR_BITS-1:0]] <= wr_data;
		

assign rd_data = mem[rd_addr[ADDR_BITS-1:0]];


assign rd_empty = rd_addr == wr_addr_rd_domain;

generate

	if (ADDR_BITS > 1) begin
		assign wr_full = wr_addr == {~rd_addr_wr_domain[ADDR_BITS:ADDR_BITS-1], 
			rd_addr_wr_domain[ADDR_BITS-2:0]};

	end else begin
		assign wr_full = wr_addr == ~rd_addr_wr_domain[ADDR_BITS:ADDR_BITS-1];
	end
endgenerate


generate
	assign rd_en = (ALLOW_UNDERFLOW) ? rd_oe : rd_oe & ~rd_empty;
	assign wr_en = (ALLOW_OVERFLOW) ? wr_we : wr_we & ~wr_full;
endgenerate 

endmodule