data/full_repos/permissive/214620165/rtl/core/instr_axi.sv
 line:16: before: "import"
1: b'%Error: data/full_repos/permissive/214620165/rtl/core/instr_axi.sv:16: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport riscv_package::*;\n       ^~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n'
module instr_axi #(
    parameter int unsigned FETCH_ADDR_WIDTH = 34,
    parameter int unsigned FETCH_DATA_WIDTH = 32,
    parameter int unsigned ID_WIDTH         = 4,

    parameter int unsigned AXI_ADDR_WIDTH   = FETCH_ADDR_WIDTH,


    parameter int unsigned AXI_ID_WIDTH     = ID_WIDTH


)(
   input  logic                         clk_i,
   input  logic                         rst_ni,



   input  logic                         refill_req_i,
   input  logic                         refill_type_i,
   output logic                         refill_gnt_o,
   input  logic [FETCH_ADDR_WIDTH-1:0]  refill_addr_i,
   input  logic [ID_WIDTH-1:0]          refill_ID_i,

   output logic                         refill_r_valid_o,
   output logic [FETCH_DATA_WIDTH-1:0]  refill_r_data_o,
   output logic                         refill_r_last_o,

   output logic [ID_WIDTH-1:0]          refill_r_ID_o,

   AXI_BUS.Master                       axi
);

    assign axi.aw_valid  = '0;
    assign axi.aw_addr   = '0;
    assign axi.aw_prot   = '0;

    assign axi.aw_len    = '0;
    assign axi.aw_size   = 3'b000;
    assign axi.aw_burst  = 2'b00;
    assign axi.aw_lock   = '0;
    assign axi.aw_cache  = '0;
    assign axi.aw_qos    = '0;
    assign axi.aw_id     = '0;


    assign axi.w_valid   = '0;
    assign axi.w_data    = '0;
    assign axi.w_strb    = '0;

    assign axi.w_last    = 1'b0;
    assign axi.b_ready   = 1'b0;

always_ff @(posedge clk_i or negedge rst_ni) begin 
    if(~rst_ni) begin
        axi.ar_valid  <='0;
        axi.ar_addr   <='0;      
    end else begin
        axi.ar_valid  <= refill_req_i;
        axi.ar_addr   <= {{(AXI_ADDR_WIDTH-FETCH_ADDR_WIDTH){1'b0}},refill_addr_i};
    end
end


    assign axi.ar_prot   = '0;

    assign axi.ar_len    = (refill_type_i) ? 8'h01 : 8'h00;
    assign axi.ar_size   = 3'b010;
    assign axi.ar_burst  = 2'b01;
    assign axi.ar_lock   = '0;
    assign axi.ar_cache  = '0;
    assign axi.ar_qos    = '0;
    assign axi.ar_id     = refill_ID_i;


    assign axi.r_ready   = 1'b1;
	






	
    assign refill_gnt_o     = axi.ar_ready & axi.ar_valid;
    assign refill_r_valid_o = axi.r_valid;
    assign refill_r_ID_o    = axi.r_id;
    assign refill_r_data_o  = axi.r_data;
    assign refill_r_last_o  = axi.r_last;

endmodule
module instr_axi #(
    parameter int unsigned FETCH_ADDR_WIDTH = 34,
    parameter int unsigned FETCH_DATA_WIDTH = 32,
    parameter int unsigned ID_WIDTH         = 4,

    parameter int unsigned AXI_ADDR_WIDTH   = FETCH_ADDR_WIDTH,


    parameter int unsigned AXI_ID_WIDTH     = ID_WIDTH


)(
   input  logic                         clk_i,
   input  logic                         rst_ni,



   input  logic                         refill_req_i,
   input  logic                         refill_type_i,
   output logic                         refill_gnt_o,
   input  logic [FETCH_ADDR_WIDTH-1:0]  refill_addr_i,
   input  logic [ID_WIDTH-1:0]          refill_ID_i,

   output logic                         refill_r_valid_o,
   output logic [FETCH_DATA_WIDTH-1:0]  refill_r_data_o,
   output logic                         refill_r_last_o,

   output logic [ID_WIDTH-1:0]          refill_r_ID_o,

   AXI_BUS.Master                       axi
);


    assign axi.aw_valid  = '0;
    assign axi.aw_addr   = '0;
    assign axi.aw_prot   = '0;

    assign axi.aw_len    = '0;
    assign axi.aw_size   = 3'b000;
    assign axi.aw_burst  = 2'b00;
    assign axi.aw_lock   = '0;
    assign axi.aw_cache  = '0;
    assign axi.aw_qos    = '0;
    assign axi.aw_id     = '0;


    assign axi.w_valid   = '0;
    assign axi.w_data    = '0;
    assign axi.w_strb    = '0;

    assign axi.w_last    = 1'b0;
    assign axi.b_ready   = 1'b0;

always_ff @(posedge clk_i or negedge rst_ni) begin 
    if(~rst_ni) begin
        axi.ar_valid  <='0;
        axi.ar_addr   <='0;      
    end else begin
        axi.ar_valid  <= refill_req_i;
        axi.ar_addr   <= {{(AXI_ADDR_WIDTH-FETCH_ADDR_WIDTH){1'b0}},refill_addr_i};
    end
end


    assign axi.ar_prot   = '0;

    assign axi.ar_len    = (refill_type_i) ? 8'h01 : 8'h00;
    assign axi.ar_size   = 3'b010;
    assign axi.ar_burst  = 2'b01;
    assign axi.ar_lock   = '0;
    assign axi.ar_cache  = '0;
    assign axi.ar_qos    = '0;
    assign axi.ar_id     = refill_ID_i;


    assign axi.r_ready   = 1'b1;
	






	
    assign refill_gnt_o     = axi.ar_ready & axi.ar_valid;
    assign refill_r_valid_o = axi.r_valid;
    assign refill_r_ID_o    = axi.r_id;
    assign refill_r_data_o  = axi.r_data;
    assign refill_r_last_o  = axi.r_last;

endmodule