data/full_repos/permissive/211316121/lab7_2/TrafficFarm.v
data/verilator_xmls/25bc4578-aa7e-43e4-a633-38d4d2910e9c.xml
module clkdiv(
    input clk,
    input clr,
    output clk3
    );
    reg [24:0] q;
    
    always@(posedge clk)
        if(clr) q<=0;
        else q<=q+1;
    
    assign clk3=q[24];    
endmodule
module clkdiv(
    input clk,
    input clr,
    output clk3
    );

    reg [24:0] q;
    
    always@(posedge clk)
        if(clr) q<=0;
        else q<=q+1;
    
    assign clk3=q[24];    
endmodule