data/full_repos/permissive/185301529/regfile.sv
 line:11: before: "]"
1: b'%Warning-WIDTH: data/full_repos/permissive/185301529/regfile.sv:26: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'dest\' generates 5 bits.\n                                                                  : ... In instance regfile\n    if (load && dest)\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/185301529/regfile.sv:34: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'src_a\' generates 5 bits.\n                                                                  : ... In instance regfile\n    reg_a = src_a ? data[src_a] : 0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/185301529/regfile.sv:35: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'src_b\' generates 5 bits.\n                                                                  : ... In instance regfile\n    reg_b = src_b ? data[src_b] : 0;\n                  ^\n%Error: Exiting due to 3 warning(s)\n'
module regfile
(
    input clk,
    input load,
    input [31:0] in,
    input [4:0] src_a, src_b, dest,
    output logic [31:0] reg_a, reg_b
);

logic [31:0] data [32];


initial
begin
    for (int i = 0; i < $size(data); i++)
    begin
        data[i] = 32'b0;
    end
end

always_ff @(posedge clk)
begin
    if (load && dest)
    begin
        data[dest] = in;
    end
end

always_comb
begin
    reg_a = src_a ? data[src_a] : 0;
    reg_b = src_b ? data[src_b] : 0;
end

endmodule
module regfile
(
    input clk,
    input load,
    input [31:0] in,
    input [4:0] src_a, src_b, dest,
    output logic [31:0] reg_a, reg_b
);


logic [31:0] data [32];


initial
begin
    for (int i = 0; i < $size(data); i++)
    begin
        data[i] = 32'b0;
    end
end

always_ff @(posedge clk)
begin
    if (load && dest)
    begin
        data[dest] = in;
    end
end

always_comb
begin
    reg_a = src_a ? data[src_a] : 0;
    reg_b = src_b ? data[src_b] : 0;
end

endmodule