data/full_repos/permissive/10379745/hard/exceptions.sv
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1: b'%Warning-MULTITOP: data/full_repos/permissive/10379745/hard/exceptions.sv:3: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'exceptions\'\nmodule exceptions (  input          CLK,\n       ^~~~~~~~~~\n                                                                           : ... Top module \'if_except\'\n                     if_except.excp EXC,      \n                     ^~~~~~~~~\n                                                                           : ... Top module \'if_debug\'\n                     if_debug.excp  DEBUG );  \n                     ^~~~~~~~\n%Error: data/full_repos/permissive/10379745/hard/exceptions.sv:3: Unsupported: Interfaced port on top level module\n                     if_except.excp EXC,      \n                                    ^~~\n%Error: data/full_repos/permissive/10379745/hard/exceptions.sv:4: Unsupported: Interfaced port on top level module\n                     if_debug.excp  DEBUG );  \n                                    ^~~~~\n%Error: data/full_repos/permissive/10379745/hard/exceptions.sv:3: Cannot find file containing interface: \'if_except\'\n                     if_except.excp EXC,      \n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hard/exceptions.sv:4: Cannot find file containing interface: \'if_debug\'\n                     if_debug.excp  DEBUG );  \n                     ^~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/10379745/hard/exceptions.sv:3: ../V3LinkDot.cpp:2055: Unlinked interface\n                     if_except.excp EXC,      \n                     ^~~~~~~~~\n'
module exceptions (  input          CLK,
                     input          RESET,
                     if_except.excp EXC,
                     if_debug.excp  DEBUG );


logic  [31:0] epc, ejump_vector;
logic   [7:0] e_vec;
logic   [4:0] cause;
logic         e_enter;

assign e_enter = RESET         | 
                 EXC.SYSCALL   |
                 EXC.BREAK     |
                 EXC.RI        |     
                 EXC.CpU       |
                 EXC.OV        |   
                 EXC.IBE       |
                 EXC.DBE       |
                 EXC.INTERRUPT ;    



assign e_vec = {EXC.IBE, EXC.RI, EXC.CpU, EXC.BREAK, EXC.SYSCALL, 
                EXC.OV, EXC.DBE, EXC.INTERRUPT};

always_comb
  casex(e_vec)
  8'b1XXXXXXX: cause = 5'd06;
  8'b01XXXXXX: cause = 5'd10;
  8'b001XXXXX: cause = 5'd11;
  8'b0001XXXX: cause = 5'd09;
  8'b00001XXX: cause = 5'd08;
  8'b000001XX: cause = 5'd12;
  8'b0000001X: cause = 5'd07;
  8'b00000001: cause = 5'd00;
  default:     cause = 5'd31;
  endcase


mux2 #(32) epc_sel( EXC.DELAY_SLOT,  EXC.PC_WB, (EXC.PC_WB - 3'd4), epc );


mux2 #(32) vec_sel( RESET | DEBUG.INST_SUBST, 32'h00000100, 32'h00000000, ejump_vector);

assign EXC.RESET     = e_enter | EXC.ERET;
assign EXC.E_ENTER   = e_enter;
assign EXC.E_USE_VEC = e_enter | EXC.ERET | DEBUG.INST_SUBST;

assign EXC.VECTOR    = EXC.ERET ? EXC.EPC_Q : ejump_vector;

assign EXC.CAUSE   = cause;
assign EXC.EPC     = epc;

endmodule
module exceptions (  input          CLK,
                     input          RESET,
                     if_except.excp EXC,
                     if_debug.excp  DEBUG );



logic  [31:0] epc, ejump_vector;
logic   [7:0] e_vec;
logic   [4:0] cause;
logic         e_enter;

assign e_enter = RESET         | 
                 EXC.SYSCALL   |
                 EXC.BREAK     |
                 EXC.RI        |     
                 EXC.CpU       |
                 EXC.OV        |   
                 EXC.IBE       |
                 EXC.DBE       |
                 EXC.INTERRUPT ;    



assign e_vec = {EXC.IBE, EXC.RI, EXC.CpU, EXC.BREAK, EXC.SYSCALL, 
                EXC.OV, EXC.DBE, EXC.INTERRUPT};

always_comb
  casex(e_vec)
  8'b1XXXXXXX: cause = 5'd06;
  8'b01XXXXXX: cause = 5'd10;
  8'b001XXXXX: cause = 5'd11;
  8'b0001XXXX: cause = 5'd09;
  8'b00001XXX: cause = 5'd08;
  8'b000001XX: cause = 5'd12;
  8'b0000001X: cause = 5'd07;
  8'b00000001: cause = 5'd00;
  default:     cause = 5'd31;
  endcase


mux2 #(32) epc_sel( EXC.DELAY_SLOT,  EXC.PC_WB, (EXC.PC_WB - 3'd4), epc );


mux2 #(32) vec_sel( RESET | DEBUG.INST_SUBST, 32'h00000100, 32'h00000000, ejump_vector);

assign EXC.RESET     = e_enter | EXC.ERET;
assign EXC.E_ENTER   = e_enter;
assign EXC.E_USE_VEC = e_enter | EXC.ERET | DEBUG.INST_SUBST;

assign EXC.VECTOR    = EXC.ERET ? EXC.EPC_Q : ejump_vector;

assign EXC.CAUSE   = cause;
assign EXC.EPC     = epc;

endmodule