data/full_repos/permissive/157101210/regfile.t.v
1: b'%Error: data/full_repos/permissive/157101210/regfile.t.v:6: Cannot find include file: regfile.v\n`include "regfile.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/regfile.v\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/regfile.v.v\n             data/full_repos/permissive/157101210,data/full_repos/permissive/157101210/regfile.v.sv\n             regfile.v\n             regfile.v.v\n             regfile.v.sv\n             obj_dir/regfile.v\n             obj_dir/regfile.v.v\n             obj_dir/regfile.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:113: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:153: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:153: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:177: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:177: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:208: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:208: Unsupported: Ignoring delay on this delayed statement.\n  #5 Clk=0; #5 Clk=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:217: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/157101210/regfile.t.v:224: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Error: Exiting due to 1 error(s), 21 warning(s)\n'
module hw4testbenchharness();

  wire[31:0]	ReadData1;
  wire[31:0]	ReadData2;
  wire[31:0]	WriteData;
  wire[4:0]	ReadRegister1;
  wire[4:0]	ReadRegister2;
  wire[4:0]	WriteRegister;
  wire		RegWrite;
  wire		Clk;

  reg		begintest;
  wire  	endtest;
  wire		dutpassed;


  regfile DUT
  (
    .ReadData1(ReadData1),
    .ReadData2(ReadData2),
    .WriteData(WriteData),
    .ReadRegister1(ReadRegister1),
    .ReadRegister2(ReadRegister2),
    .WriteRegister(WriteRegister),
    .wEnable(RegWrite),
    .Clk(Clk)
  );


  hw4testbench tester
  (
    .begintest(begintest),
    .endtest(endtest), 
    .dutpassed(dutpassed),
    .ReadData1(ReadData1),
    .ReadData2(ReadData2),
    .WriteData(WriteData), 
    .ReadRegister1(ReadRegister1), 
    .ReadRegister2(ReadRegister2),
    .WriteRegister(WriteRegister),
    .RegWrite(RegWrite), 
    .Clk(Clk)
  );


  initial begin
    $display("Starting Regfile Tests.");
    begintest=0;
    #10;
    begintest=1;
    #1000;
  end


  always @(negedge endtest) begin
    $display("Regfile tests passed?: %b", dutpassed);
    $display();
  end

endmodule
module hw4testbenchharness();


  wire[31:0]	ReadData1;
  wire[31:0]	ReadData2;
  wire[31:0]	WriteData;
  wire[4:0]	ReadRegister1;
  wire[4:0]	ReadRegister2;
  wire[4:0]	WriteRegister;
  wire		RegWrite;
  wire		Clk;

  reg		begintest;
  wire  	endtest;
  wire		dutpassed;


  regfile DUT
  (
    .ReadData1(ReadData1),
    .ReadData2(ReadData2),
    .WriteData(WriteData),
    .ReadRegister1(ReadRegister1),
    .ReadRegister2(ReadRegister2),
    .WriteRegister(WriteRegister),
    .wEnable(RegWrite),
    .Clk(Clk)
  );


  hw4testbench tester
  (
    .begintest(begintest),
    .endtest(endtest), 
    .dutpassed(dutpassed),
    .ReadData1(ReadData1),
    .ReadData2(ReadData2),
    .WriteData(WriteData), 
    .ReadRegister1(ReadRegister1), 
    .ReadRegister2(ReadRegister2),
    .WriteRegister(WriteRegister),
    .RegWrite(RegWrite), 
    .Clk(Clk)
  );


  initial begin
    $display("Starting Regfile Tests.");
    begintest=0;
    #10;
    begintest=1;
    #1000;
  end


  always @(negedge endtest) begin
    $display("Regfile tests passed?: %b", dutpassed);
    $display();
  end

endmodule