data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:2: Cannot find include file: xcfi_macros.sv\n`include "xcfi_macros.sv" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201267735/verif/rvfi/models,data/full_repos/permissive/201267735/xcfi_macros.sv\n             data/full_repos/permissive/201267735/verif/rvfi/models,data/full_repos/permissive/201267735/xcfi_macros.sv.v\n             data/full_repos/permissive/201267735/verif/rvfi/models,data/full_repos/permissive/201267735/xcfi_macros.sv.sv\n             xcfi_macros.sv\n             xcfi_macros.sv.v\n             xcfi_macros.sv.sv\n             obj_dir/xcfi_macros.sv\n             obj_dir/xcfi_macros.sv.v\n             obj_dir/xcfi_macros.sv.sv\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:6: Define or directive not defined: \'`XCFI_TRACE_INPUTS\'\n    `XCFI_TRACE_INPUTS,\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:6: syntax error, unexpected \',\', expecting \'[\'\n    `XCFI_TRACE_INPUTS,\n                      ^\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:8: Define or directive not defined: \'`XCFI_SPEC_OUTPUTS\'\n    `XCFI_SPEC_OUTPUTS\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:12: Define or directive not defined: \'`XCFI_INSN_CHECK_COMMON\'\n`XCFI_INSN_CHECK_COMMON\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:17: Define or directive not defined: \'`RS1\'\nwire [31:0] insn_result = (((`RS1 >> 7) | (`RS1 << 32-7))) ^\n                             ^~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:17: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nwire [31:0] insn_result = (((`RS1 >> 7) | (`RS1 << 32-7))) ^\n                                  ^~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:17: Define or directive not defined: \'`RS1\'\nwire [31:0] insn_result = (((`RS1 >> 7) | (`RS1 << 32-7))) ^\n                                           ^~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:18: Define or directive not defined: \'`RS1\'\n                          (((`RS1 >> 18) | (`RS1 << 32-18))) ^\n                             ^~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:18: Define or directive not defined: \'`RS1\'\n                          (((`RS1 >> 18) | (`RS1 << 32-18))) ^\n                                            ^~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:19: Define or directive not defined: \'`RS1\'\n                          (((`RS1 >> 3)              )) ;\n                             ^~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:23: Define or directive not defined: \'`FIELD_RS1_ADDR\'\nassign spec_rs1_addr    = `FIELD_RS1_ADDR;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_sha256_s0.v:26: Define or directive not defined: \'`FIELD_RD_ADDR\'\nassign spec_rd_addr     = `FIELD_RD_ADDR;\n                          ^~~~~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module xcfi_insn_spec (

    `XCFI_TRACE_INPUTS,

    `XCFI_SPEC_OUTPUTS

);

`XCFI_INSN_CHECK_COMMON

`define ROR32(a,b) ((a >> b) | (a << 32-b))
`define SRL32(a,b) ((a >> b)              )

wire [31:0] insn_result = (`ROR32(`RS1, 7)) ^
                          (`ROR32(`RS1,18)) ^
                          (`SRL32(`RS1, 3)) ;

assign spec_valid       = rvfi_valid && dec_xc_sha256_s0;
assign spec_trap        = 1'b0;
assign spec_rs1_addr    = `FIELD_RS1_ADDR;
assign spec_rs2_addr    = 0;
assign spec_rs3_addr    = 0;
assign spec_rd_addr     = `FIELD_RD_ADDR;
assign spec_rd_wdata    = |spec_rd_addr ? insn_result : 0;
assign spec_rd_wide     = 1'b0;
assign spec_rd_wdatahi  = 32'b0;
assign spec_pc_wdata    = rvfi_pc_rdata + 4;
assign spec_mem_addr    = 0;
assign spec_mem_rmask   = 0;

assign spec_mem_wmask   = 0;
assign spec_mem_wdata   = 0;

endmodule
module xcfi_insn_spec (

    `XCFI_TRACE_INPUTS,

    `XCFI_SPEC_OUTPUTS

);


`XCFI_INSN_CHECK_COMMON

`define ROR32(a,b) ((a >> b) | (a << 32-b))
`define SRL32(a,b) ((a >> b)              )

wire [31:0] insn_result = (`ROR32(`RS1, 7)) ^
                          (`ROR32(`RS1,18)) ^
                          (`SRL32(`RS1, 3)) ;

assign spec_valid       = rvfi_valid && dec_xc_sha256_s0;
assign spec_trap        = 1'b0;
assign spec_rs1_addr    = `FIELD_RS1_ADDR;
assign spec_rs2_addr    = 0;
assign spec_rs3_addr    = 0;
assign spec_rd_addr     = `FIELD_RD_ADDR;
assign spec_rd_wdata    = |spec_rd_addr ? insn_result : 0;
assign spec_rd_wide     = 1'b0;
assign spec_rd_wdatahi  = 32'b0;
assign spec_pc_wdata    = rvfi_pc_rdata + 4;
assign spec_mem_addr    = 0;
assign spec_mem_rmask   = 0;

assign spec_mem_wmask   = 0;
assign spec_mem_wdata   = 0;

endmodule