data/full_repos/permissive/123786074/registers.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/123786074/registers.v:20: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                      : ... Top module \'regn\'\nmodule regn(Clock, load, D_in, D_out);\n       ^~~~\n                                                                      : ... Top module \'regn_incr\'\nmodule regn_incr(Clock, load, incr, D_in, D_out);\n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module regn_incr(Clock, load, incr, D_in, D_out);
  parameter n = 16;
  input 			[n-1:0] 		D_in;
  input 							load;
  input 							Clock;
  input 							incr;
  output reg 	[n-1:0] 		D_out;

  always @(posedge Clock)
	begin
    if (load)
      D_out <= D_in;
	 if (incr)
		D_out <= D_out + 16'd1 ; 
	end
endmodule
module regn_incr(Clock, load, incr, D_in, D_out);

  parameter n = 16;
  input 			[n-1:0] 		D_in;
  input 							load;
  input 							Clock;
  input 							incr;
  output reg 	[n-1:0] 		D_out;

  always @(posedge Clock)
	begin
    if (load)
      D_out <= D_in;
	 if (incr)
		D_out <= D_out + 16'd1 ; 
	end
endmodule