data/full_repos/permissive/110381502/src/mojo_top.v
1: b'%Error: data/full_repos/permissive/110381502/src/mojo_top.v:31: Cannot find file containing module: \'vga_clock\'\nvga_clock vga_clock(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110381502/src,data/full_repos/permissive/110381502/vga_clock\n             data/full_repos/permissive/110381502/src,data/full_repos/permissive/110381502/vga_clock.v\n             data/full_repos/permissive/110381502/src,data/full_repos/permissive/110381502/vga_clock.sv\n             vga_clock\n             vga_clock.v\n             vga_clock.sv\n             obj_dir/vga_clock\n             obj_dir/vga_clock.v\n             obj_dir/vga_clock.sv\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/mojo_top.v:81: Operator AND expects 10 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                      : ... In instance mojo_top\n  red_out <= (vsync_count >> 2) & 4\'hF;\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/mojo_top.v:81: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s AND generates 10 bits.\n                                                                      : ... In instance mojo_top\n  red_out <= (vsync_count >> 2) & 4\'hF;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/mojo_top.v:82: Operator AND expects 11 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                      : ... In instance mojo_top\n  green_out <= (hsync_count >> 2) & 4\'hF;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/mojo_top.v:82: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s AND generates 11 bits.\n                                                                      : ... In instance mojo_top\n  green_out <= (hsync_count >> 2) & 4\'hF;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/mojo_top.v:83: Operator AND expects 11 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                      : ... In instance mojo_top\n  blue_out <= (hsync_count >> 4) & 4\'hF;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/110381502/src/mojo_top.v:83: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s AND generates 11 bits.\n                                                                      : ... In instance mojo_top\n  blue_out <= (hsync_count >> 4) & 4\'hF;\n           ^~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module mojo_top(

    input clk,

    input rst_n,

    input cclk,

    output[7:0]led,

    output spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,

    output [3:0] spi_channel,

    input avr_tx,
    output avr_rx,
    input avr_rx_busy,

    output reg hsync,
	 output reg vsync,
	 output reg[3:0] red_out,
	 output reg[3:0] green_out,
	 output reg[3:0] blue_out
	 );

wire vgaclk;

vga_clock vga_clock(
      .CLK_IN1(clk),
      .CLK_VGA(vgaclk)
);

wire rst = ~rst_n;


assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;

assign led[6:0] = 7'b0;
assign led[7] = rst;



reg[10:0] hsync_count;
reg[9:0] vsync_count;




parameter VGA_HORIZ_RES = 800;
parameter VGA_VERT_RES = 600;
parameter VGA_HORIZ_FRONT_PORCH_END = 840;
parameter VGA_HORIZ_SYNC_END = 968;
parameter VGA_HORIZ_BACK_PORCH_END = 1055;
parameter VGA_VERT_FRONT_PORCH_END = 601;
parameter VGA_VERT_SYNC_END = 606;
parameter VGA_VERT_BACK_PORCH_END = 627;


always @(posedge vgaclk) begin

  if (hsync_count < VGA_HORIZ_RES) begin

	 hsync <= 1'b1;
	 hsync_count <= hsync_count + 1;
	 
	 if (vsync_count < VGA_VERT_RES) begin


		red_out <= (vsync_count >> 2) & 4'hF;
		green_out <= (hsync_count >> 2) & 4'hF;
		blue_out <= (hsync_count >> 4) & 4'hF;
	 end else begin

		red_out <= 4'b0;
		green_out <= 4'b0;
		blue_out <= 4'b0;
	 end
  end else if (hsync_count >= VGA_HORIZ_RES && hsync_count < VGA_HORIZ_FRONT_PORCH_END) begin

	 hsync <= 1'b1;
	 hsync_count <= hsync_count + 1;

	 red_out <= 4'b0;
	 green_out <= 4'b0;
	 blue_out <= 4'b0;
  end else if (hsync_count >= VGA_HORIZ_FRONT_PORCH_END && hsync_count < VGA_HORIZ_SYNC_END) begin

	 hsync <= 1'b0;
	 hsync_count <= hsync_count + 1;

	 red_out <= 4'b0;
	 green_out <= 4'b0;
	 blue_out <= 4'b0;
  end else if (hsync_count >= VGA_HORIZ_SYNC_END && hsync_count < VGA_HORIZ_BACK_PORCH_END) begin

	 hsync <= 1'b1;
	 hsync_count <= hsync_count + 1;

	 red_out <= 4'b0;
	 green_out <= 4'b0;
	 blue_out <= 4'b0;
  end else if (vsync_count < VGA_VERT_BACK_PORCH_END) begin


	 hsync <= 1'b1;
	 hsync_count <= 11'b0;
	 vsync_count <= vsync_count + 1;

	 red_out <= 4'b0;
	 green_out <= 4'b0;
	 blue_out <= 4'b0;
  end else begin


	 hsync <= 1'b1;
	 hsync_count <= 11'b0;
	 vsync_count <= 10'b0;

	 red_out <= 4'b0;
	 green_out <= 4'b0;
	 blue_out <= 4'b0;
  end
  

  if (vsync_count > VGA_VERT_FRONT_PORCH_END && vsync_count < VGA_VERT_SYNC_END) begin

    vsync <= 1'b0;
  end else begin

    vsync <= 1'b1;
  end
end

endmodule
module mojo_top(

    input clk,

    input rst_n,

    input cclk,

    output[7:0]led,

    output spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,

    output [3:0] spi_channel,

    input avr_tx,
    output avr_rx,
    input avr_rx_busy,

    output reg hsync,
	 output reg vsync,
	 output reg[3:0] red_out,
	 output reg[3:0] green_out,
	 output reg[3:0] blue_out
	 );


wire vgaclk;

vga_clock vga_clock(
      .CLK_IN1(clk),
      .CLK_VGA(vgaclk)
);

wire rst = ~rst_n;


assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;

assign led[6:0] = 7'b0;
assign led[7] = rst;



reg[10:0] hsync_count;
reg[9:0] vsync_count;




parameter VGA_HORIZ_RES = 800;
parameter VGA_VERT_RES = 600;
parameter VGA_HORIZ_FRONT_PORCH_END = 840;
parameter VGA_HORIZ_SYNC_END = 968;
parameter VGA_HORIZ_BACK_PORCH_END = 1055;
parameter VGA_VERT_FRONT_PORCH_END = 601;
parameter VGA_VERT_SYNC_END = 606;
parameter VGA_VERT_BACK_PORCH_END = 627;


always @(posedge vgaclk) begin

  if (hsync_count < VGA_HORIZ_RES) begin

	 hsync <= 1'b1;
	 hsync_count <= hsync_count + 1;
	 
	 if (vsync_count < VGA_VERT_RES) begin


		red_out <= (vsync_count >> 2) & 4'hF;
		green_out <= (hsync_count >> 2) & 4'hF;
		blue_out <= (hsync_count >> 4) & 4'hF;
	 end else begin

		red_out <= 4'b0;
		green_out <= 4'b0;
		blue_out <= 4'b0;
	 end
  end else if (hsync_count >= VGA_HORIZ_RES && hsync_count < VGA_HORIZ_FRONT_PORCH_END) begin

	 hsync <= 1'b1;
	 hsync_count <= hsync_count + 1;

	 red_out <= 4'b0;
	 green_out <= 4'b0;
	 blue_out <= 4'b0;
  end else if (hsync_count >= VGA_HORIZ_FRONT_PORCH_END && hsync_count < VGA_HORIZ_SYNC_END) begin

	 hsync <= 1'b0;
	 hsync_count <= hsync_count + 1;

	 red_out <= 4'b0;
	 green_out <= 4'b0;
	 blue_out <= 4'b0;
  end else if (hsync_count >= VGA_HORIZ_SYNC_END && hsync_count < VGA_HORIZ_BACK_PORCH_END) begin

	 hsync <= 1'b1;
	 hsync_count <= hsync_count + 1;

	 red_out <= 4'b0;
	 green_out <= 4'b0;
	 blue_out <= 4'b0;
  end else if (vsync_count < VGA_VERT_BACK_PORCH_END) begin


	 hsync <= 1'b1;
	 hsync_count <= 11'b0;
	 vsync_count <= vsync_count + 1;

	 red_out <= 4'b0;
	 green_out <= 4'b0;
	 blue_out <= 4'b0;
  end else begin


	 hsync <= 1'b1;
	 hsync_count <= 11'b0;
	 vsync_count <= 10'b0;

	 red_out <= 4'b0;
	 green_out <= 4'b0;
	 blue_out <= 4'b0;
  end
  

  if (vsync_count > VGA_VERT_FRONT_PORCH_END && vsync_count < VGA_VERT_SYNC_END) begin

    vsync <= 1'b0;
  end else begin

    vsync <= 1'b1;
  end
end

endmodule