data/full_repos/permissive/107007139/Lab 4/lab_test_full_file.v
1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/107007139\n        ... Looked in:\n             data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139\n             data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.v\n             data/full_repos/permissive/107007139/Lab/4,data/full_repos/permissive/107007139.sv\n             4,data/full_repos/permissive/107007139\n             4,data/full_repos/permissive/107007139.v\n             4,data/full_repos/permissive/107007139.sv\n             obj_dir/4,data/full_repos/permissive/107007139\n             obj_dir/4,data/full_repos/permissive/107007139.v\n             obj_dir/4,data/full_repos/permissive/107007139.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/107007139/Lab\n%Error: Cannot find file containing module: 4/lab_test_full_file.v\n%Error: Exiting due to 3 error(s)\n'
module lab_test_module(input clk, input [2:0] examiner_value, input session_pb,
                       output [3:0] link_with_box_output_1, output [7:0] link_with_box_output_2,
                       output reg [5:0] my_register_one);


    wire [2:0] link_to_box_input_7;
    assign link_to_box_input_7 = (session_pb == 1) ? 7 : examiner_value;


    

    reg [13:0] my_register_two;
    

    wire out1;
    wire out2;
    wire out3;
    my_clock1 clock1(clk, out1);
    my_clock2 clock2(clk, out2);
    my_clock3 clock3(clk, out3);
    

    wire pulse;
    my_single_pulse single_pulse(out2, session_pb, pulse);
    

    initial begin
        my_register_one = 6'b100111;
        my_register_two = 400;
    end
    

    always @(posedge pulse) begin
        my_register_one <= my_register_one + 1;
    end
    

    always @(posedge out1) begin
        my_register_two <= my_register_two + 1;
    end
    







    session_black_box black_box(clk, out3, my_register_two, link_with_box_output_1, link_with_box_output_2, out1, out2, out3, link_to_box_input_7);
    
endmodule
module lab_test_module(input clk, input [2:0] examiner_value, input session_pb,
                       output [3:0] link_with_box_output_1, output [7:0] link_with_box_output_2,
                       output reg [5:0] my_register_one);



    wire [2:0] link_to_box_input_7;
    assign link_to_box_input_7 = (session_pb == 1) ? 7 : examiner_value;


    

    reg [13:0] my_register_two;
    

    wire out1;
    wire out2;
    wire out3;
    my_clock1 clock1(clk, out1);
    my_clock2 clock2(clk, out2);
    my_clock3 clock3(clk, out3);
    

    wire pulse;
    my_single_pulse single_pulse(out2, session_pb, pulse);
    

    initial begin
        my_register_one = 6'b100111;
        my_register_two = 400;
    end
    

    always @(posedge pulse) begin
        my_register_one <= my_register_one + 1;
    end
    

    always @(posedge out1) begin
        my_register_two <= my_register_two + 1;
    end
    







    session_black_box black_box(clk, out3, my_register_two, link_with_box_output_1, link_with_box_output_2, out1, out2, out3, link_to_box_input_7);
    
endmodule