data/full_repos/permissive/130171615/regfile.v
data/verilator_xmls/a89ed750-291b-4d75-bd81-ac09c98b7785.xml
module regfile(clk, reset, wr, rD, D, rA, A, rB, B);
    parameter       N=4;
    parameter       S=32;

    input           clk;
    input           reset;
    input           wr;

    input   [N-1:0] rD;
    input   [N-1:0] rA;
    input   [N-1:0] rB;

    input   [S-1:0] D;
    output  [S-1:0] A;
    output  [S-1:0] B;


    
    integer 	    i;
    reg     [S-1:0] rf [0:1<<N-1];


    assign A = rf[rA];
    assign B = rf[rB];

    always @(posedge clk) begin
        if (reset) begin

	        for (i = 0; i < 1<<N-1; i = i + 1) begin
	            rf[i] <= 0;
	        end
        end else begin
	        if (wr) rf[rD] <= D;
        end
    end
endmodule
module regfile(clk, reset, wr, rD, D, rA, A, rB, B);

    parameter       N=4;
    parameter       S=32;

    input           clk;
    input           reset;
    input           wr;

    input   [N-1:0] rD;
    input   [N-1:0] rA;
    input   [N-1:0] rB;

    input   [S-1:0] D;
    output  [S-1:0] A;
    output  [S-1:0] B;


    
    integer 	    i;
    reg     [S-1:0] rf [0:1<<N-1];


    assign A = rf[rA];
    assign B = rf[rB];

    always @(posedge clk) begin
        if (reset) begin

	        for (i = 0; i < 1<<N-1; i = i + 1) begin
	            rf[i] <= 0;
	        end
        end else begin
	        if (wr) rf[rD] <= D;
        end
    end
endmodule