data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv
 line:19: before: "class"
1: b"%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:19: Unsupported: classes\nclass tl_tx_trans extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:19: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass tl_tx_trans extends uvm_sequence_item;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:45: syntax error, unexpected rand\n    rand bit               config_type;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:46: syntax error, unexpected rand\n    rand bit [2:0]         plength;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:47: syntax error, unexpected rand\n    rand bit [1:0]         dlength;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:48: syntax error, unexpected rand\n    rand bit [1:0]         dpart;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:49: syntax error, unexpected rand\n    rand bit [15:0]        capp_tag;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:50: syntax error, unexpected rand\n    rand bit [15:0]        afu_tag;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:51: syntax error, unexpected rand\n    rand bit [63:0]        byte_enable;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:52: syntax error, unexpected rand\n    rand bit [63:0]        physical_addr;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:53: syntax error, unexpected rand\n    rand bit [3:0]         cmd_flag;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:54: syntax error, unexpected rand\n    rand bit [63:0]        object_handle;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:55: syntax error, unexpected rand\n    rand bit [7:0]         mad;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:56: syntax error, unexpected rand\n    rand bit [3:0]         resp_code;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:57: syntax error, unexpected rand\n    rand bit [5:0]         tlx_dcp_3;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:58: syntax error, unexpected rand\n    rand bit [5:0]         tlx_dcp_0;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:59: syntax error, unexpected rand\n    rand bit [3:0]         tlx_vc_3;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:60: syntax error, unexpected rand\n    rand bit [3:0]         tlx_vc_0;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:62: syntax error, unexpected rand\n    rand bit [63:0]        data_carrier[32];\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:63: syntax error, unexpected rand\n    rand bit [2:0]         data_error[32];            \n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:64: syntax error, unexpected rand\n    rand bit [71:0]        xmeta[32];                 \n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:65: syntax error, unexpected rand\n    rand bit [6:0]         meta[32];                  \n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:69: syntax error, unexpected rand\n    rand int               data_carrier_type;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:70: syntax error, unexpected rand\n    rand bit [5:0]         data_template;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:78: syntax error, unexpected rand\n    rand packet_type_enum  packet_type;\n    ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:80: Define or directive not defined: '`uvm_object_utils_begin'\n    `uvm_object_utils_begin(tl_tx_trans)\n    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:80: syntax error, unexpected '('\n    `uvm_object_utils_begin(tl_tx_trans)\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:81: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (is_cmd,                        UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:82: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (config_type,                   UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:83: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (plength,                       UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:84: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (dlength,                       UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:85: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (dpart,                         UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:86: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (capp_tag,                      UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:87: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (afu_tag,                       UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:88: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (byte_enable,                   UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:89: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (physical_addr,                 UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:90: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (cmd_flag,                      UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:91: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (object_handle,                 UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:92: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (mad,                           UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:93: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (resp_code,                     UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:94: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (tlx_dcp_3,                     UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:95: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (tlx_dcp_0,                     UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:96: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (tlx_vc_3,                      UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:97: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (tlx_vc_0,                      UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:98: Define or directive not defined: '`uvm_field_sarray_int'\n        `uvm_field_sarray_int   (data_carrier,                  UVM_ALL_ON)\n        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:99: Define or directive not defined: '`uvm_field_sarray_int'\n        `uvm_field_sarray_int   (data_error,                    UVM_ALL_ON)\n        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:100: Define or directive not defined: '`uvm_field_sarray_int'\n        `uvm_field_sarray_int   (xmeta,                         UVM_ALL_ON)\n        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:101: Define or directive not defined: '`uvm_field_sarray_int'\n        `uvm_field_sarray_int   (meta,                          UVM_ALL_ON)\n        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:102: Define or directive not defined: '`uvm_field_enum'\n        `uvm_field_enum         (packet_type_enum, packet_type, UVM_ALL_ON)\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/tl_bfm/util/tl_tx_trans.sv:103: Define or directive not defined: '`uvm_field_int'\n        `uvm_field_int          (data_carrier_type,             UVM_ALL_ON)\n        ^~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n"
function new(string name="tl_tx_trans");
        super.new(name);
        is_cmd = 1;
        config_type = 0;
        intrp_handler_begin = 0;
        intrp_handler_end = 0;
    endfunction
function new(string name="tl_tx_trans");

        super.new(name);
        is_cmd = 1;
        config_type = 0;
        intrp_handler_begin = 0;
        intrp_handler_end = 0;
    endfunction