data/full_repos/permissive/179980995/Lab1/FA_4b_Behavioral/FA_4b_Behavioral.v
1: b'%Warning-WIDTH: data/full_repos/permissive/179980995/Lab1/FA_4b_Behavioral/FA_4b_Behavioral.v:15: Operator ADD expects 5 bits on the RHS, but RHS\'s REPLICATE generates 2 bits.\n                                                                                                : ... In instance full_adder_4b\ntemp = {1\'b0,a} + {1\'b0,b} + {1\'b0,cin};\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module full_adder_4b(a, b, cin, sum, cout);


input [3:0] a, b;
input cin;


output [3:0] sum;
output cout;


reg [4:0] temp;
always @(*)
begin
temp = {1'b0,a} + {1'b0,b} + {1'b0,cin};
end
assign sum = temp[3:0];
assign cout = temp[4];
endmodule
module full_adder_4b(a, b, cin, sum, cout);



input [3:0] a, b;
input cin;


output [3:0] sum;
output cout;


reg [4:0] temp;
always @(*)
begin
temp = {1'b0,a} + {1'b0,b} + {1'b0,cin};
end
assign sum = temp[3:0];
assign cout = temp[4];
endmodule