data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/shift_left_2_testbench.v
 line:19: before: "$"
1: b'%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/shift_left_2_testbench.v:11: Unsupported or unknown PLI call: $monitor\n    $monitor(in, shift);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/shift_left_2_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/shift_left_2_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module shift_left_2_testbench;

reg [31:0] in;
wire [31:0] shift;

shift_left_2 uut(.in(in), .shift(shift));

initial begin
    $monitor(in, shift);
    

    in=32'b1111;
    #5
    in=32'b0011;
    #5

    $finish;
end
endmodule
module shift_left_2_testbench;


reg [31:0] in;
wire [31:0] shift;

shift_left_2 uut(.in(in), .shift(shift));

initial begin
    $monitor(in, shift);
    

    in=32'b1111;
    #5
    in=32'b0011;
    #5

    $finish;
end
endmodule