data/full_repos/permissive/109936328/tb/tb_pipeline.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:3: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:4: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:5: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:16: Define or directive not defined: \'`ADDR_W\'\n  wire [`ADDR_W - 1:0] instr_req_addr;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:18: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] instr_res_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:20: Define or directive not defined: \'`ADDR_W\'\n  wire [`ADDR_W - 1:0] mem_req_addr;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:21: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] mem_req_wr_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:23: Define or directive not defined: \'`MEM_COUNT_W\'\n  wire [`MEM_COUNT_W - 1:0] mem_req_count;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:25: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] mem_res_rd_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:26: Define or directive not defined: \'`MEM_CODE_W\'\n  wire [`MEM_CODE_W - 1:0] mem_res_code;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:29: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_pipeline.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:30: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars();\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #CLK_PERIOD;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:37: Define or directive not defined: \'`ADDR_W\'\n    wait (instr_req_addr[`ADDR_W - 1:2] == \'h100);\n                         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_pipeline.v:37: Unsupported: wait statements\n    wait (instr_req_addr[`ADDR_W - 1:2] == \'h100);\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_pipeline.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #CLK_HPERIOD;\n    ^\n%Error: Exiting due to 14 error(s), 2 warning(s)\n'
module tb_pipeline;
  localparam CLK_HPERIOD = 5;
  localparam CLK_PERIOD = 2 * CLK_HPERIOD;
  localparam SIM_DURATION = 30;

  reg clk = 0;
  reg resetn = 0;
  reg rf_aresetn = 0;

  wire [`ADDR_W - 1:0] instr_req_addr;
  wire instr_req_en;
  wire [`WORD_W - 1:0] instr_res_data;

  wire [`ADDR_W - 1:0] mem_req_addr;
  wire [`WORD_W - 1:0] mem_req_wr_data;
  wire mem_req_wr_en;
  wire [`MEM_COUNT_W - 1:0] mem_req_count;

  wire [`WORD_W - 1:0] mem_res_rd_data;
  wire [`MEM_CODE_W - 1:0] mem_res_code;

  initial begin
    $dumpfile("tb_pipeline.vcd");
    $dumpvars();

    #CLK_PERIOD;
    resetn = 1;
    rf_aresetn = 1;


    wait (instr_req_addr[`ADDR_W - 1:2] == 'h100);

    $finish();
  end

  always begin: clk_gen
    #CLK_HPERIOD;
    clk = ~clk;
  end

  pipeline#(
    .DUMP_VARS(1),
    .DUMP_FILE("tb_pipeline.vcd")
  ) dut(
    .clk(clk),
    .resetn(resetn),
    .aresetn(rf_aresetn),

    .o_instr_req_addr(instr_req_addr),
    .o_instr_req_en(instr_req_en),
    .i_instr_res_data(instr_res_data),

    .o_mem_req_addr(mem_req_addr),
    .o_mem_req_wr_data(mem_req_wr_data),
    .o_mem_req_wr_en(mem_req_wr_en),
    .o_mem_req_count(mem_req_count),

    .i_mem_res_rd_data(mem_res_rd_data),
    .i_mem_res_code(mem_res_code)
  );

  instruction_memory#(
    .INSTR_MAX(256),
    .INSTR_FILE("program.dat"),
    .DUMP_INSTR(0),
    .DUMP_FILE("tb_pipeline.vcd")
  ) imem(
    .clk(clk),
    .i_req_addr(instr_req_addr),
    .o_res_data(instr_res_data)
  );

  memory_interface#(
    .WORD_COUNT(3),
    .DUMP_VARS(1),
    .DUMP_FILE("tb_pipeline.vcd")
  ) dmem(
    .clk(clk),
    .aresetn(rf_aresetn),

    .i_req_addr(mem_req_addr),
    .i_req_wr_data(mem_req_wr_data),
    .i_req_wr_en(mem_req_wr_en),
    .i_req_count(mem_req_count),

    .o_res_rd_data(mem_res_rd_data),
    .o_res_code(mem_res_code)
  );

endmodule
module tb_pipeline;

  localparam CLK_HPERIOD = 5;
  localparam CLK_PERIOD = 2 * CLK_HPERIOD;
  localparam SIM_DURATION = 30;

  reg clk = 0;
  reg resetn = 0;
  reg rf_aresetn = 0;

  wire [`ADDR_W - 1:0] instr_req_addr;
  wire instr_req_en;
  wire [`WORD_W - 1:0] instr_res_data;

  wire [`ADDR_W - 1:0] mem_req_addr;
  wire [`WORD_W - 1:0] mem_req_wr_data;
  wire mem_req_wr_en;
  wire [`MEM_COUNT_W - 1:0] mem_req_count;

  wire [`WORD_W - 1:0] mem_res_rd_data;
  wire [`MEM_CODE_W - 1:0] mem_res_code;

  initial begin
    $dumpfile("tb_pipeline.vcd");
    $dumpvars();

    #CLK_PERIOD;
    resetn = 1;
    rf_aresetn = 1;


    wait (instr_req_addr[`ADDR_W - 1:2] == 'h100);

    $finish();
  end

  always begin: clk_gen
    #CLK_HPERIOD;
    clk = ~clk;
  end

  pipeline#(
    .DUMP_VARS(1),
    .DUMP_FILE("tb_pipeline.vcd")
  ) dut(
    .clk(clk),
    .resetn(resetn),
    .aresetn(rf_aresetn),

    .o_instr_req_addr(instr_req_addr),
    .o_instr_req_en(instr_req_en),
    .i_instr_res_data(instr_res_data),

    .o_mem_req_addr(mem_req_addr),
    .o_mem_req_wr_data(mem_req_wr_data),
    .o_mem_req_wr_en(mem_req_wr_en),
    .o_mem_req_count(mem_req_count),

    .i_mem_res_rd_data(mem_res_rd_data),
    .i_mem_res_code(mem_res_code)
  );

  instruction_memory#(
    .INSTR_MAX(256),
    .INSTR_FILE("program.dat"),
    .DUMP_INSTR(0),
    .DUMP_FILE("tb_pipeline.vcd")
  ) imem(
    .clk(clk),
    .i_req_addr(instr_req_addr),
    .o_res_data(instr_res_data)
  );

  memory_interface#(
    .WORD_COUNT(3),
    .DUMP_VARS(1),
    .DUMP_FILE("tb_pipeline.vcd")
  ) dmem(
    .clk(clk),
    .aresetn(rf_aresetn),

    .i_req_addr(mem_req_addr),
    .i_req_wr_data(mem_req_wr_data),
    .i_req_wr_en(mem_req_wr_en),
    .i_req_count(mem_req_count),

    .o_res_rd_data(mem_res_rd_data),
    .o_res_code(mem_res_code)
  );

endmodule