data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1/ccc1.v
1: b"%Error: data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1/ccc1.v:57: Cannot find file containing module: 'ccc1_ccc1_0_FCCC'\nccc1_ccc1_0_FCCC ccc1_0(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1,data/full_repos/permissive/153287529/ccc1_ccc1_0_FCCC\n             data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1,data/full_repos/permissive/153287529/ccc1_ccc1_0_FCCC.v\n             data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1,data/full_repos/permissive/153287529/ccc1_ccc1_0_FCCC.sv\n             ccc1_ccc1_0_FCCC\n             ccc1_ccc1_0_FCCC.v\n             ccc1_ccc1_0_FCCC.sv\n             obj_dir/ccc1_ccc1_0_FCCC\n             obj_dir/ccc1_ccc1_0_FCCC.v\n             obj_dir/ccc1_ccc1_0_FCCC.sv\n%Error: Exiting due to 1 error(s)\n"
module ccc1(

    RCOSC_25_50MHZ,

    GL0,
    LOCK
);




input  RCOSC_25_50MHZ;



output GL0;
output LOCK;



wire   GL0_net_0;
wire   LOCK_net_0;
wire   RCOSC_25_50MHZ;
wire   GL0_net_1;
wire   LOCK_net_1;



wire   GND_net;
wire   [7:2]PADDR_const_net_0;
wire   [7:0]PWDATA_const_net_0;



assign GND_net            = 1'b0;
assign PADDR_const_net_0  = 6'h00;
assign PWDATA_const_net_0 = 8'h00;



assign GL0_net_1  = GL0_net_0;
assign GL0        = GL0_net_1;
assign LOCK_net_1 = LOCK_net_0;
assign LOCK       = LOCK_net_1;




ccc1_ccc1_0_FCCC ccc1_0(

        .RCOSC_25_50MHZ ( RCOSC_25_50MHZ ),

        .GL0            ( GL0_net_0 ),
        .LOCK           ( LOCK_net_0 ) 
        );


endmodule
module ccc1(

    RCOSC_25_50MHZ,

    GL0,
    LOCK
);





input  RCOSC_25_50MHZ;



output GL0;
output LOCK;



wire   GL0_net_0;
wire   LOCK_net_0;
wire   RCOSC_25_50MHZ;
wire   GL0_net_1;
wire   LOCK_net_1;



wire   GND_net;
wire   [7:2]PADDR_const_net_0;
wire   [7:0]PWDATA_const_net_0;



assign GND_net            = 1'b0;
assign PADDR_const_net_0  = 6'h00;
assign PWDATA_const_net_0 = 8'h00;



assign GL0_net_1  = GL0_net_0;
assign GL0        = GL0_net_1;
assign LOCK_net_1 = LOCK_net_0;
assign LOCK       = LOCK_net_1;




ccc1_ccc1_0_FCCC ccc1_0(

        .RCOSC_25_50MHZ ( RCOSC_25_50MHZ ),

        .GL0            ( GL0_net_0 ),
        .LOCK           ( LOCK_net_0 ) 
        );


endmodule