data/full_repos/permissive/143278/ivltests/br_gh6.v
 line:14: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh6.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("a = %b y = %b", a, y);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh6.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("a = %b y = %b", a, y);\n  ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bug();

reg  a;
wire y;

assign y = |(-a);

reg failed = 0;

initial begin
  a = 0;
  #1 $display("a = %b y = %b", a, y);
  if (y !== 0) failed = 1;
  a = 1;
  #1 $display("a = %b y = %b", a, y);
  if (y !== 1) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module bug();


reg  a;
wire y;

assign y = |(-a);

reg failed = 0;

initial begin
  a = 0;
  #1 $display("a = %b y = %b", a, y);
  if (y !== 0) failed = 1;
  a = 1;
  #1 $display("a = %b y = %b", a, y);
  if (y !== 1) failed = 1;

  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule