data/full_repos/permissive/100331186/tarea2/release/modulos/registro.v
1: b"%Error: data/full_repos/permissive/100331186/tarea2/release/modulos/registro.v:48: Duplicate declaration of signal: 's_out'\n                                                                                 : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  reg s_out;\n      ^~~~~\n        data/full_repos/permissive/100331186/tarea2/release/modulos/registro.v:43: ... Location of original declaration\n  output s_out         \n         ^~~~~\n%Error: data/full_repos/permissive/100331186/tarea2/release/modulos/registro.v:49: Duplicate declaration of signal: 'q'\n  reg [3:0] q;\n            ^\n        data/full_repos/permissive/100331186/tarea2/release/modulos/registro.v:42: ... Location of original declaration\n  output [3:0] q,      \n               ^\n%Error: Exiting due to 2 error(s)\n"
module registro (
  input        clk,
  input        enb,


  input        dir,


  input        s_in,
  input  [1:0] modo,



  input  [3:0] d,
  output [3:0] q,
  output s_out
);



  reg s_out;
  reg [3:0] q;


  always @(posedge clk) begin






    if (modo == 2'b00) s_out <= dir ? q[0] : q[3];
    else s_out <= 0;


    if (enb) begin


      if (modo == 2'b00)      q <= dir ? {s_in, q[3:1]} : {q[2:0], s_in};


      else if (modo == 2'b01) q <= dir ? {q[0], q[3:1]} : {q[2:0], q[3]};


      else if (modo == 2'b10) q <= d;
    end
  end
endmodule
module registro (
  input        clk,
  input        enb,


  input        dir,


  input        s_in,
  input  [1:0] modo,



  input  [3:0] d,
  output [3:0] q,
  output s_out
);




  reg s_out;
  reg [3:0] q;


  always @(posedge clk) begin






    if (modo == 2'b00) s_out <= dir ? q[0] : q[3];
    else s_out <= 0;


    if (enb) begin


      if (modo == 2'b00)      q <= dir ? {s_in, q[3:1]} : {q[2:0], s_in};


      else if (modo == 2'b01) q <= dir ? {q[0], q[3:1]} : {q[2:0], q[3]};


      else if (modo == 2'b10) q <= d;
    end
  end
endmodule