data/full_repos/permissive/211878730/atlys/practice/rs232c_tx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/211878730/atlys/practice/rs232c_tx.v:26: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 24 bits.\n                                                                                  : ... In instance rs232c_tx\n assign tx_div = ((sys_clk / rate) - 1);\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/211878730/atlys/practice/rs232c_tx.v:27: Cannot find file containing module: \'clk_div\'\n clk_div div(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/clk_div\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/clk_div.v\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/clk_div.sv\n             clk_div\n             clk_div.v\n             clk_div.sv\n             obj_dir/clk_div\n             obj_dir/clk_div.v\n             obj_dir/clk_div.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module rs232c_tx(clk, rst, wr, din, dout, ready);
    parameter sys_clk = 14000000;
	parameter rate = 9600;
	input  wire clk;
	input  wire rst;
	input  wire wr;
	input  wire [7:0] din;
	output reg dout;
	output wire ready;
	 
	reg [7:0] in_din;
	reg load;
	reg [2:0] cbit;
	reg run;
	 
	wire tx_en;
	wire [15:0] tx_div;
	 
	reg [3:0] status;
	 
	assign ready = (run == 0 && load == 0) ? 1'b1 : 1'b0;
	 
	assign tx_div = ((sys_clk / rate) - 1);
	clk_div div(
	    .clk(clk),
		.rst(rst),
		.div(tx_div),
		.clk_out(tx_en)
	);
	 
	always @(posedge clk or posedge rst) begin
	    if (rst == 1) begin
		    load <= 0;
		end else begin
		    if (wr == 1 && run == 0) begin
				load <= 1;
				in_din <= din;
			end
			if (load == 1 && run == 1) begin
				load <= 0;
			end
		end
	end
	 
	always @(posedge tx_en or posedge rst) begin
	    if (rst == 1) begin
		    dout <= 1;
			cbit <= 0;
			run <= 0;
			status <= 0;
		end else begin
			if (status == 0) begin
				if (load == 1) begin
					dout <= 0;
					cbit <= 0;
					run <= 1;
					status <= 1;
				end else begin
					dout <= 1;
					run <= 0;
				end
			end else if (status == 1) begin
				if (cbit == 7) begin
					status <= 2;
				end
				cbit <= cbit + 1'b1;
				dout <= in_din[cbit];
			end else if (status == 2) begin
				status <= 0;
				dout <= 1;
			end else begin
				dout <= 1;
				status <= 0;
			end
		end
	end
endmodule
module rs232c_tx(clk, rst, wr, din, dout, ready);

    parameter sys_clk = 14000000;
	parameter rate = 9600;
	input  wire clk;
	input  wire rst;
	input  wire wr;
	input  wire [7:0] din;
	output reg dout;
	output wire ready;
	 
	reg [7:0] in_din;
	reg load;
	reg [2:0] cbit;
	reg run;
	 
	wire tx_en;
	wire [15:0] tx_div;
	 
	reg [3:0] status;
	 
	assign ready = (run == 0 && load == 0) ? 1'b1 : 1'b0;
	 
	assign tx_div = ((sys_clk / rate) - 1);
	clk_div div(
	    .clk(clk),
		.rst(rst),
		.div(tx_div),
		.clk_out(tx_en)
	);
	 
	always @(posedge clk or posedge rst) begin
	    if (rst == 1) begin
		    load <= 0;
		end else begin
		    if (wr == 1 && run == 0) begin
				load <= 1;
				in_din <= din;
			end
			if (load == 1 && run == 1) begin
				load <= 0;
			end
		end
	end
	 
	always @(posedge tx_en or posedge rst) begin
	    if (rst == 1) begin
		    dout <= 1;
			cbit <= 0;
			run <= 0;
			status <= 0;
		end else begin
			if (status == 0) begin
				if (load == 1) begin
					dout <= 0;
					cbit <= 0;
					run <= 1;
					status <= 1;
				end else begin
					dout <= 1;
					run <= 0;
				end
			end else if (status == 1) begin
				if (cbit == 7) begin
					status <= 2;
				end
				cbit <= cbit + 1'b1;
				dout <= in_din[cbit];
			end else if (status == 2) begin
				status <= 0;
				dout <= 1;
			end else begin
				dout <= 1;
				status <= 0;
			end
		end
	end
endmodule