data/full_repos/permissive/13136965/dmemory.v
1: b"%Error: data/full_repos/permissive/13136965/dmemory.v:2: Duplicate declaration of signal: 'data'\n                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg [31:0] data;\n           ^~~~\n        data/full_repos/permissive/13136965/dmemory.v:1: ... Location of original declaration\nmodule datamemory(output [31:0] data,input [15:0] addr,input [31:0] inputd,input write,input read,input clk);\n                                ^~~~\n%Error: Exiting due to 1 error(s)\n"
module datamemory(output [31:0] data,input [15:0] addr,input [31:0] inputd,input write,input read,input clk);
reg [31:0] data;
reg [31:0] memdata [255:0];

always @(negedge clk)
	begin
		if(write == 1'b1)
			memdata[addr[7:0]]=inputd[31:0];
		if(read == 1'b1)
			data[31:0]=memdata[addr[7:0]];
	end
	
initial
	begin
		memdata[0]=32'b00000000000000000000000000000111;
		memdata[1]=32'b00000000000000000000000000001011;
		memdata[2]=32'b00000000000000000000000000000001;
		memdata[3]=32'b00000000000000000000000000001000;
		memdata[4]=32'b00000000000000000000000000000111;
	end
	
endmodule
module datamemory(output [31:0] data,input [15:0] addr,input [31:0] inputd,input write,input read,input clk);

reg [31:0] data;
reg [31:0] memdata [255:0];

always @(negedge clk)
	begin
		if(write == 1'b1)
			memdata[addr[7:0]]=inputd[31:0];
		if(read == 1'b1)
			data[31:0]=memdata[addr[7:0]];
	end
	
initial
	begin
		memdata[0]=32'b00000000000000000000000000000111;
		memdata[1]=32'b00000000000000000000000000001011;
		memdata[2]=32'b00000000000000000000000000000001;
		memdata[3]=32'b00000000000000000000000000001000;
		memdata[4]=32'b00000000000000000000000000000111;
	end
	
endmodule