data/full_repos/permissive/172538466/hw/src/ram.v
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1: b'%Error: data/full_repos/permissive/172538466/hw/src/ram.v:1: Cannot find include file: defs.vh\n`include "defs.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh.v\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh.sv\n             defs.vh\n             defs.vh.v\n             defs.vh.sv\n             obj_dir/defs.vh\n             obj_dir/defs.vh.v\n             obj_dir/defs.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module ram #(parameter AWIDTH = 8)
   (
    input              HCLK_I,
    input              HRESET_N_I,

    input              HREADY_I,
    input              HSEL_I,
    input [2:0]        HSIZE_I,
    input              HWRITE_I,
    input [AWIDTH-1:0] HADDR_I,
    input [31:0]       HRDATA_I,
    output [31:0]      HWDATA_O,
    output             HRESP_O,
    output             HREADY_O
    );


   localparam COUNT = 2 ** (AWIDTH-2);
   reg [7:0]           mem0[0:COUNT-1];
   reg [7:0]           mem1[0:COUNT-1];
   reg [7:0]           mem2[0:COUNT-1];
   reg [7:0]           mem3[0:COUNT-1];


   reg [AWIDTH-1:0]    adr_d;
   reg [1:0]           size_d;
   reg                 write_d;
   reg                 enable_d;

   always @(posedge HCLK_I) begin
     adr_d <= HADDR_I;
     size_d <= HSIZE_I[1:0];
   end

   always @(posedge HCLK_I) begin
     if(!HRESET_N_I) begin
       write_d <= 0;
       enable_d <= 0;
     end else begin
       write_d <= HWRITE_I;
       enable_d <= HREADY_I & HSEL_I;
     end
   end



   wire [1:0]          adr_low_d = adr_d[1:0];
   wire [AWIDTH-3:0]   adr_hi_d = adr_d[AWIDTH-1:2];

   always @(posedge HCLK_I) begin
     if(write_d & enable_d) begin
       case({size_d, adr_low_d})

         4'b00_00: mem0[adr_hi_d] <= HRDATA_I[7:0];
         4'b00_01: mem1[adr_hi_d] <= HRDATA_I[15:8];
         4'b00_10: mem2[adr_hi_d] <= HRDATA_I[23:16];
         4'b00_11: mem3[adr_hi_d] <= HRDATA_I[31:24];

         4'b01_00: begin
           mem0[adr_hi_d] <= HRDATA_I[7:0];
           mem1[adr_hi_d] <= HRDATA_I[15:8];
         end

         4'b01_10: begin
           mem2[adr_hi_d] <= HRDATA_I[23:16];
           mem3[adr_hi_d] <= HRDATA_I[31:24];
         end

         4'b10_00: begin
           mem0[adr_hi_d] <= HRDATA_I[7:0];
           mem1[adr_hi_d] <= HRDATA_I[15:8];
           mem2[adr_hi_d] <= HRDATA_I[23:16];
           mem3[adr_hi_d] <= HRDATA_I[31:24];
         end
       endcase
     end
   end


   assign HWDATA_O = { mem3[adr_hi_d], mem2[adr_hi_d], mem1[adr_hi_d], mem0[adr_hi_d] };
   assign HREADY_O = enable_d;
   assign HRESP_O = 0;
endmodule
module ram #(parameter AWIDTH = 8)
   (
    input              HCLK_I,
    input              HRESET_N_I,

    input              HREADY_I,
    input              HSEL_I,
    input [2:0]        HSIZE_I,
    input              HWRITE_I,
    input [AWIDTH-1:0] HADDR_I,
    input [31:0]       HRDATA_I,
    output [31:0]      HWDATA_O,
    output             HRESP_O,
    output             HREADY_O
    );



   localparam COUNT = 2 ** (AWIDTH-2);
   reg [7:0]           mem0[0:COUNT-1];
   reg [7:0]           mem1[0:COUNT-1];
   reg [7:0]           mem2[0:COUNT-1];
   reg [7:0]           mem3[0:COUNT-1];


   reg [AWIDTH-1:0]    adr_d;
   reg [1:0]           size_d;
   reg                 write_d;
   reg                 enable_d;

   always @(posedge HCLK_I) begin
     adr_d <= HADDR_I;
     size_d <= HSIZE_I[1:0];
   end

   always @(posedge HCLK_I) begin
     if(!HRESET_N_I) begin
       write_d <= 0;
       enable_d <= 0;
     end else begin
       write_d <= HWRITE_I;
       enable_d <= HREADY_I & HSEL_I;
     end
   end



   wire [1:0]          adr_low_d = adr_d[1:0];
   wire [AWIDTH-3:0]   adr_hi_d = adr_d[AWIDTH-1:2];

   always @(posedge HCLK_I) begin
     if(write_d & enable_d) begin
       case({size_d, adr_low_d})

         4'b00_00: mem0[adr_hi_d] <= HRDATA_I[7:0];
         4'b00_01: mem1[adr_hi_d] <= HRDATA_I[15:8];
         4'b00_10: mem2[adr_hi_d] <= HRDATA_I[23:16];
         4'b00_11: mem3[adr_hi_d] <= HRDATA_I[31:24];

         4'b01_00: begin
           mem0[adr_hi_d] <= HRDATA_I[7:0];
           mem1[adr_hi_d] <= HRDATA_I[15:8];
         end

         4'b01_10: begin
           mem2[adr_hi_d] <= HRDATA_I[23:16];
           mem3[adr_hi_d] <= HRDATA_I[31:24];
         end

         4'b10_00: begin
           mem0[adr_hi_d] <= HRDATA_I[7:0];
           mem1[adr_hi_d] <= HRDATA_I[15:8];
           mem2[adr_hi_d] <= HRDATA_I[23:16];
           mem3[adr_hi_d] <= HRDATA_I[31:24];
         end
       endcase
     end
   end


   assign HWDATA_O = { mem3[adr_hi_d], mem2[adr_hi_d], mem1[adr_hi_d], mem0[adr_hi_d] };
   assign HREADY_O = enable_d;
   assign HRESP_O = 0;
endmodule