data/full_repos/permissive/175063152/ip/trng_1.0/src/rtl/avalanche_entropy.v
1: b"%Error: data/full_repos/permissive/175063152/ip/trng_1.0/src/rtl/avalanche_entropy.v:124: Cannot find file containing module: 'avalanche_entropy_core'\n  avalanche_entropy_core core(\n  ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175063152/ip/trng_1.0/src/rtl,data/full_repos/permissive/175063152/avalanche_entropy_core\n             data/full_repos/permissive/175063152/ip/trng_1.0/src/rtl,data/full_repos/permissive/175063152/avalanche_entropy_core.v\n             data/full_repos/permissive/175063152/ip/trng_1.0/src/rtl,data/full_repos/permissive/175063152/avalanche_entropy_core.sv\n             avalanche_entropy_core\n             avalanche_entropy_core.v\n             avalanche_entropy_core.sv\n             obj_dir/avalanche_entropy_core\n             obj_dir/avalanche_entropy_core.v\n             obj_dir/avalanche_entropy_core.sv\n%Error: Exiting due to 1 error(s)\n"
module avalanche_entropy(
                         input wire           clk,
                         input wire           reset_n,

                         input wire           noise,

                         input wire           cs,
                         input wire           we,
                         input wire  [7 : 0]  address,
                         input wire  [31 : 0] write_data,
                         output wire [31 : 0] read_data,
                         output wire          error,

                         input wire           discard,
                         input wire           test_mode,
                         output wire          security_error,

                         output wire          entropy_enabled,
                         output wire [31 : 0] entropy_data,
                         output wire          entropy_valid,
                         input wire           entropy_ack,

                         output wire [7 : 0]  debug,
                         input wire           debug_update
                        );





  parameter ADDR_NAME0              = 8'h00;
  parameter ADDR_NAME1              = 8'h01;
  parameter ADDR_VERSION            = 8'h02;

  parameter ADDR_CTRL               = 8'h10;
  parameter CTRL_ENABLE_BIT         = 0;

  parameter ADDR_STATUS             = 8'h11;
  parameter STATUS_ENABLE_VALID_BIT = 0;

  parameter ADDR_ENTROPY            = 8'h20;
  parameter ADDR_DELTA              = 8'h30;


  parameter CORE_NAME0              = 32'h6578746e;
  parameter CORE_NAME1              = 32'h6f697365;
  parameter CORE_VERSION            = 32'h302e3130;





  reg          enable_reg;
  reg          enable_new;
  reg          enable_we;





  wire [31 : 0]  delta;

  reg [31 : 0]   tmp_read_data;
  reg            tmp_error;





  assign read_data       = tmp_read_data;
  assign error           = tmp_error;
  assign security_error  = 0;

  assign entropy_enabled = enable_reg;





  avalanche_entropy_core core(
                              .clk(clk),
                              .reset_n(reset_n),

                              .noise(noise),

                              .enable(enable_reg),

                              .entropy_data(entropy_data),
                              .entropy_valid(entropy_valid),
                              .entropy_ack(entropy_ack),

                              .delta(delta),

                              .debug(debug),
                              .debug_update(debug_update)
                             );





  always @ (posedge clk or negedge reset_n)
    begin
      if (!reset_n)
        begin
          enable_reg <= 1;
        end
      else
        begin
          if (enable_we)
            begin
              enable_reg <= enable_new;
            end
        end
    end





  always @*
    begin : api_logic
      tmp_read_data = 32'h00000000;
      tmp_error     = 1'b0;
      enable_new    = 0;
      enable_we     = 0;

      if (cs)
        begin
          if (we)
            begin
              case (address)

                ADDR_CTRL:
                  begin
                    enable_new = write_data[CTRL_ENABLE_BIT];
                    enable_we  = 1;
                  end

                default:
                  begin
                    tmp_error = 1;
                  end
              endcase
            end

          else
            begin
              case (address)
                ADDR_NAME0:
                  begin
                    tmp_read_data = CORE_NAME0;
                  end

                ADDR_NAME1:
                  begin
                    tmp_read_data = CORE_NAME1;
                  end

                ADDR_VERSION:
                  begin
                    tmp_read_data = CORE_VERSION;
                  end

                ADDR_CTRL:
                  begin
                    tmp_read_data = {31'h00000000, enable_reg};
                  end

                ADDR_STATUS:
                  begin
                    tmp_read_data = {31'h00000000, entropy_valid};
                   end

                ADDR_ENTROPY:
                  begin
                    tmp_read_data = entropy_data;
                  end

                ADDR_DELTA:
                  begin
                    tmp_read_data = delta;
                  end

                default:
                  begin
                    tmp_error = 1;
                  end
              endcase
            end
        end
    end

endmodule
module avalanche_entropy(
                         input wire           clk,
                         input wire           reset_n,

                         input wire           noise,

                         input wire           cs,
                         input wire           we,
                         input wire  [7 : 0]  address,
                         input wire  [31 : 0] write_data,
                         output wire [31 : 0] read_data,
                         output wire          error,

                         input wire           discard,
                         input wire           test_mode,
                         output wire          security_error,

                         output wire          entropy_enabled,
                         output wire [31 : 0] entropy_data,
                         output wire          entropy_valid,
                         input wire           entropy_ack,

                         output wire [7 : 0]  debug,
                         input wire           debug_update
                        );






  parameter ADDR_NAME0              = 8'h00;
  parameter ADDR_NAME1              = 8'h01;
  parameter ADDR_VERSION            = 8'h02;

  parameter ADDR_CTRL               = 8'h10;
  parameter CTRL_ENABLE_BIT         = 0;

  parameter ADDR_STATUS             = 8'h11;
  parameter STATUS_ENABLE_VALID_BIT = 0;

  parameter ADDR_ENTROPY            = 8'h20;
  parameter ADDR_DELTA              = 8'h30;


  parameter CORE_NAME0              = 32'h6578746e;
  parameter CORE_NAME1              = 32'h6f697365;
  parameter CORE_VERSION            = 32'h302e3130;





  reg          enable_reg;
  reg          enable_new;
  reg          enable_we;





  wire [31 : 0]  delta;

  reg [31 : 0]   tmp_read_data;
  reg            tmp_error;





  assign read_data       = tmp_read_data;
  assign error           = tmp_error;
  assign security_error  = 0;

  assign entropy_enabled = enable_reg;





  avalanche_entropy_core core(
                              .clk(clk),
                              .reset_n(reset_n),

                              .noise(noise),

                              .enable(enable_reg),

                              .entropy_data(entropy_data),
                              .entropy_valid(entropy_valid),
                              .entropy_ack(entropy_ack),

                              .delta(delta),

                              .debug(debug),
                              .debug_update(debug_update)
                             );





  always @ (posedge clk or negedge reset_n)
    begin
      if (!reset_n)
        begin
          enable_reg <= 1;
        end
      else
        begin
          if (enable_we)
            begin
              enable_reg <= enable_new;
            end
        end
    end





  always @*
    begin : api_logic
      tmp_read_data = 32'h00000000;
      tmp_error     = 1'b0;
      enable_new    = 0;
      enable_we     = 0;

      if (cs)
        begin
          if (we)
            begin
              case (address)

                ADDR_CTRL:
                  begin
                    enable_new = write_data[CTRL_ENABLE_BIT];
                    enable_we  = 1;
                  end

                default:
                  begin
                    tmp_error = 1;
                  end
              endcase
            end

          else
            begin
              case (address)
                ADDR_NAME0:
                  begin
                    tmp_read_data = CORE_NAME0;
                  end

                ADDR_NAME1:
                  begin
                    tmp_read_data = CORE_NAME1;
                  end

                ADDR_VERSION:
                  begin
                    tmp_read_data = CORE_VERSION;
                  end

                ADDR_CTRL:
                  begin
                    tmp_read_data = {31'h00000000, enable_reg};
                  end

                ADDR_STATUS:
                  begin
                    tmp_read_data = {31'h00000000, entropy_valid};
                   end

                ADDR_ENTROPY:
                  begin
                    tmp_read_data = entropy_data;
                  end

                ADDR_DELTA:
                  begin
                    tmp_read_data = delta;
                  end

                default:
                  begin
                    tmp_error = 1;
                  end
              endcase
            end
        end
    end

endmodule