data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi/axi_embed_tlast_tkeep.v
 line:1 column:1: Illegal character '\x00'
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi/axi_embed_tlast_tkeep.v:77: syntax error, unexpected '(', expecting IDENTIFIER\n    DATA_W_is_not_large_enough_to_store_escape_code_TKEEP_and_TLAST();\n                                                                    ^\n%Error: Exiting due to 1 error(s)\n"
module axi_embed_tlast_tkeep #(
  parameter DATA_W = 64,
  parameter KEEP_W = DATA_W/8
) (
  input clk,
  input rst,


  input  [DATA_W-1:0] i_tdata,
  input  [KEEP_W-1:0] i_tkeep,
  input               i_tlast,
  input               i_tvalid,
  output              i_tready,


  output reg [DATA_W-1:0] o_tdata,
  output                  o_tvalid,
  input                   o_tready
);

  localparam                  ESC_WORD_W = 32;
  localparam [ESC_WORD_W-1:0] ESC_WORD   = 'hDEADBEEF;






  if (DATA_W < ESC_WORD_W+KEEP_W+1) begin : gen_assertion

    DATA_W_is_not_large_enough_to_store_escape_code_TKEEP_and_TLAST();
  end






  localparam PASS   = 0;
  localparam ESCAPE = 1;

  localparam ST_IDLE = 0;
  localparam ST_DATA = 1;

  reg [0:0] state = ST_IDLE;
  reg [0:0] next_state;

  reg [0:0] select;

  always @(posedge clk) begin
    if (rst) begin
      state <= ST_IDLE;
    end else begin if (o_tready)
      state <= next_state;
    end
  end

  always @(*) begin
    case(state)
      ST_IDLE: begin
        if (i_tlast && i_tvalid) begin
          next_state = ST_DATA;
          select     = ESCAPE;
        end else if ((i_tdata[DATA_W-1 -: ESC_WORD_W] == ESC_WORD) && i_tvalid) begin
          next_state = ST_DATA;
          select     = ESCAPE;
        end else begin
          next_state = ST_IDLE;
          select     = PASS;
        end
      end

      ST_DATA: begin
        select = PASS;
        if (i_tvalid) begin
          next_state = ST_IDLE;
        end else begin
          next_state = ST_DATA;
        end
      end
    endcase
  end






  always @(*) begin
    case(select)
      PASS   : begin
        o_tdata = i_tdata;
      end
      ESCAPE : begin
        o_tdata                         = {DATA_W{1'b0}};
        o_tdata[DATA_W-1 -: ESC_WORD_W] = ESC_WORD;
        o_tdata[       1 +:     KEEP_W] = i_tkeep;
        o_tdata[       0 +:          1] = i_tlast;
      end
    endcase
  end

  assign o_tvalid = (select == PASS) ? i_tvalid : 1'b1;
  assign i_tready = (select == PASS) ? o_tready : 1'b0;

endmodule
module axi_embed_tlast_tkeep #(
  parameter DATA_W = 64,
  parameter KEEP_W = DATA_W/8
) (
  input clk,
  input rst,


  input  [DATA_W-1:0] i_tdata,
  input  [KEEP_W-1:0] i_tkeep,
  input               i_tlast,
  input               i_tvalid,
  output              i_tready,


  output reg [DATA_W-1:0] o_tdata,
  output                  o_tvalid,
  input                   o_tready
);


  localparam                  ESC_WORD_W = 32;
  localparam [ESC_WORD_W-1:0] ESC_WORD   = 'hDEADBEEF;






  if (DATA_W < ESC_WORD_W+KEEP_W+1) begin : gen_assertion

    DATA_W_is_not_large_enough_to_store_escape_code_TKEEP_and_TLAST();
  end






  localparam PASS   = 0;
  localparam ESCAPE = 1;

  localparam ST_IDLE = 0;
  localparam ST_DATA = 1;

  reg [0:0] state = ST_IDLE;
  reg [0:0] next_state;

  reg [0:0] select;

  always @(posedge clk) begin
    if (rst) begin
      state <= ST_IDLE;
    end else begin if (o_tready)
      state <= next_state;
    end
  end

  always @(*) begin
    case(state)
      ST_IDLE: begin
        if (i_tlast && i_tvalid) begin
          next_state = ST_DATA;
          select     = ESCAPE;
        end else if ((i_tdata[DATA_W-1 -: ESC_WORD_W] == ESC_WORD) && i_tvalid) begin
          next_state = ST_DATA;
          select     = ESCAPE;
        end else begin
          next_state = ST_IDLE;
          select     = PASS;
        end
      end

      ST_DATA: begin
        select = PASS;
        if (i_tvalid) begin
          next_state = ST_IDLE;
        end else begin
          next_state = ST_DATA;
        end
      end
    endcase
  end






  always @(*) begin
    case(select)
      PASS   : begin
        o_tdata = i_tdata;
      end
      ESCAPE : begin
        o_tdata                         = {DATA_W{1'b0}};
        o_tdata[DATA_W-1 -: ESC_WORD_W] = ESC_WORD;
        o_tdata[       1 +:     KEEP_W] = i_tkeep;
        o_tdata[       0 +:          1] = i_tlast;
      end
    endcase
  end

  assign o_tvalid = (select == PASS) ? i_tvalid : 1'b1;
  assign i_tready = (select == PASS) ? o_tready : 1'b0;

endmodule