data/full_repos/permissive/119557600/Divider_tb.v
 line:42: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/119557600/Divider_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #55 reset   <= 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/119557600/Divider_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10 mode     <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119557600/Divider_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #100mode     <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/119557600/Divider_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/119557600/Divider_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #5clk <= ~clk;\n    ^\n%Error: data/full_repos/permissive/119557600/Divider_tb.v:9: Cannot find file containing module: \'Divider_Modulo\'\nDivider_Modulo Divider_Modulo(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119557600,data/full_repos/permissive/119557600/Divider_Modulo\n             data/full_repos/permissive/119557600,data/full_repos/permissive/119557600/Divider_Modulo.v\n             data/full_repos/permissive/119557600,data/full_repos/permissive/119557600/Divider_Modulo.sv\n             Divider_Modulo\n             Divider_Modulo.v\n             Divider_Modulo.sv\n             obj_dir/Divider_Modulo\n             obj_dir/Divider_Modulo.v\n             obj_dir/Divider_Modulo.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Divider_tb ();

reg clk, reset, valid_in, mode;
reg [15:0]divisor;
reg [31:0]dividend;
wire valid_out;
wire [31:0]result;

Divider_Modulo Divider_Modulo(
    .clk        (clk),
    .reset      (reset),
	.mode       (mode),
    .valid_in   (valid_in),
    .divisor    (divisor),
    .dividend   (dividend),
	.result     (result),
	.valid_out  (valid_out)
);



initial begin
    clk         <= 1'b1;
    reset       <= 1'b1;
    valid_in    <= 1'b0;
    #55 reset   <= 1'b0;


    mode        <= 1'b0;
	valid_in	<= 1'b1;
    divisor     <= 16'b0110_0011_0000_0011;
    dividend    <= 32'b0010_0000_0000_0100_0000_0000_1100_0000;



	#10 mode     <= 1'b1;
	valid_in	<= 1'b1;
    divisor     <= 16'b0110_0011_0110_0011;
    dividend    <= 32'b0010_1001_0010_0100_1100_0100_1100_0011;



	#100mode     <= 1'b1;
	valid_in	<= 1'b1;
    divisor     <= 16'd5;
    dividend    <= 32'd21;



    #100 $finish;
end

always begin
    #5clk <= ~clk;
end

endmodule
module Divider_tb ();


reg clk, reset, valid_in, mode;
reg [15:0]divisor;
reg [31:0]dividend;
wire valid_out;
wire [31:0]result;

Divider_Modulo Divider_Modulo(
    .clk        (clk),
    .reset      (reset),
	.mode       (mode),
    .valid_in   (valid_in),
    .divisor    (divisor),
    .dividend   (dividend),
	.result     (result),
	.valid_out  (valid_out)
);



initial begin
    clk         <= 1'b1;
    reset       <= 1'b1;
    valid_in    <= 1'b0;
    #55 reset   <= 1'b0;


    mode        <= 1'b0;
	valid_in	<= 1'b1;
    divisor     <= 16'b0110_0011_0000_0011;
    dividend    <= 32'b0010_0000_0000_0100_0000_0000_1100_0000;



	#10 mode     <= 1'b1;
	valid_in	<= 1'b1;
    divisor     <= 16'b0110_0011_0110_0011;
    dividend    <= 32'b0010_1001_0010_0100_1100_0100_1100_0011;



	#100mode     <= 1'b1;
	valid_in	<= 1'b1;
    divisor     <= 16'd5;
    dividend    <= 32'd21;



    #100 $finish;
end

always begin
    #5clk <= ~clk;
end

endmodule