data/full_repos/permissive/101548714/RS_FlipFlop.v
data/verilator_xmls/2eaff417-5a28-480f-b379-dda537bb12b8.xml
module RSFF(RS,clk,q,qbar);
  input [1:0] RS;
  output q,qbar;
  input clk;
  reg q,qbar;
  
  always @(posedge clk) begin
    case (RS)
      2'd0: q = q;
      2'd1: q = 0;
      2'd2: q = 1;
      2'd3: q = 1'bx;
    endcase
    qbar = ~q;
  end
endmodule
module RSFF(RS,clk,q,qbar);

  input [1:0] RS;
  output q,qbar;
  input clk;
  reg q,qbar;
  
  always @(posedge clk) begin
    case (RS)
      2'd0: q = q;
      2'd1: q = 0;
      2'd2: q = 1;
      2'd3: q = 1'bx;
    endcase
    qbar = ~q;
  end
endmodule