data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips_tb.v
1: b'%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips_tb.v:12: Unsupported or unknown PLI call: $monitor\n   $monitor("PC = 0x%8X, IF_instr = 0x%8X, ID_instr = 0x%8X, EX_instr = 0x%8X, MEM_instr = 0x%8X, WB_instr = 0x%8X", \n   ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #5 ;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #20 ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/131249673/MIPS_L_PipeLine/mips_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #(50) clk = ~clk;\n    ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_tb();
    
   reg clk, rst;
    
   mips U_MIPS(
      .clk(clk), .rst(rst)
   );
    
   initial begin
      $readmemh( "code.txt" , U_MIPS.U_IM.imem ) ;

	  $monitor("PC = 0x%8X, IF_instr = 0x%8X, ID_instr = 0x%8X, EX_instr = 0x%8X, MEM_instr = 0x%8X, WB_instr = 0x%8X", 
		  U_MIPS.U_PC.PC, U_MIPS.im_dout, U_MIPS.ID_instr, U_MIPS.EX_instr, U_MIPS.MEM_instr, U_MIPS.WB_instr );
      clk = 1 ;
      rst = 0 ;
      #5 ;
      rst = 1 ;
      #20 ;
      rst = 0 ;
   end
   
   always
	   #(50) clk = ~clk;
   
endmodule
module mips_tb();

    
   reg clk, rst;
    
   mips U_MIPS(
      .clk(clk), .rst(rst)
   );
    
   initial begin
      $readmemh( "code.txt" , U_MIPS.U_IM.imem ) ;

	  $monitor("PC = 0x%8X, IF_instr = 0x%8X, ID_instr = 0x%8X, EX_instr = 0x%8X, MEM_instr = 0x%8X, WB_instr = 0x%8X", 
		  U_MIPS.U_PC.PC, U_MIPS.im_dout, U_MIPS.ID_instr, U_MIPS.EX_instr, U_MIPS.MEM_instr, U_MIPS.WB_instr );
      clk = 1 ;
      rst = 0 ;
      #5 ;
      rst = 1 ;
      #20 ;
      rst = 0 ;
   end
   
   always
	   #(50) clk = ~clk;
   
endmodule