data/full_repos/permissive/209534045/src/wsg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/209534045/src/wsg.v:197: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'waveout\' generates 8 bits.\n                                                                  : ... In instance WSG_3CH.core\n            sndmix  <= sndmix + waveout;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/209534045/src/wsg.v:204: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'waveout\' generates 8 bits.\n                                                                  : ... In instance WSG_3CH.core\n            sndmix  <= sndmix + waveout;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/209534045/src/wsg.v:212: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'waveout\' generates 8 bits.\n                                                                  : ... In instance WSG_3CH.core\n            sndmix  <= sndmix + waveout;\n                              ^\n%Error: Exiting due to 3 warning(s)\n'
module WSGREGS
(
	input			RESET,
	input			CPUCLK,
	input [4:0]	ADRS,
	input			WR,
	input [3:0]	DATA,
	
	output reg  [2:0] W0,
	output reg  [2:0] W1,
	output reg  [2:0] W2,

	output reg  [3:0] V0,
	output reg  [3:0] V1,
	output reg  [3:0] V2,
 
	output reg [19:0] F0,
	output reg [15:0] F1,
	output reg [15:0] F2
);

always @ ( posedge CPUCLK or posedge RESET ) begin

   if ( RESET ) begin

      W0 <= 0;
      W1 <= 0;
      W2 <= 0;

      F0 <= 0;
      F1 <= 0;
      F2 <= 0;

      V0 <= 0;
      V1 <= 0;
      V2 <= 0;

   end
   else begin

      if ( WR ) case ( ADRS )

      5'h05: W0 <= DATA[2:0];
      5'h0A: W1 <= DATA[2:0];
      5'h0F: W2 <= DATA[2:0];

      5'h15: V0 <= DATA;
      5'h1A: V1 <= DATA;
      5'h1F: V2 <= DATA;

      5'h10: F0[3:0]   <= DATA;
      5'h11: F0[7:4]   <= DATA;
      5'h12: F0[11:8]  <= DATA;
      5'h13: F0[15:12] <= DATA;
      5'h14: F0[19:16] <= DATA;

      5'h16: F1[3:0]   <= DATA;
      5'h17: F1[7:4]   <= DATA;
      5'h18: F1[11:8]  <= DATA;
      5'h19: F1[15:12] <= DATA;

      5'h1B: F2[3:0]   <= DATA;
      5'h1C: F2[7:4]   <= DATA;
      5'h1D: F2[11:8]  <= DATA;
      5'h1E: F2[15:12] <= DATA;

      default:;

      endcase

   end

end

endmodule
module WSGREGS
(
	input			RESET,
	input			CPUCLK,
	input [4:0]	ADRS,
	input			WR,
	input [3:0]	DATA,
	
	output reg  [2:0] W0,
	output reg  [2:0] W1,
	output reg  [2:0] W2,

	output reg  [3:0] V0,
	output reg  [3:0] V1,
	output reg  [3:0] V2,
 
	output reg [19:0] F0,
	output reg [15:0] F1,
	output reg [15:0] F2
);


always @ ( posedge CPUCLK or posedge RESET ) begin

   if ( RESET ) begin

      W0 <= 0;
      W1 <= 0;
      W2 <= 0;

      F0 <= 0;
      F1 <= 0;
      F2 <= 0;

      V0 <= 0;
      V1 <= 0;
      V2 <= 0;

   end
   else begin

      if ( WR ) case ( ADRS )

      5'h05: W0 <= DATA[2:0];
      5'h0A: W1 <= DATA[2:0];
      5'h0F: W2 <= DATA[2:0];

      5'h15: V0 <= DATA;
      5'h1A: V1 <= DATA;
      5'h1F: V2 <= DATA;

      5'h10: F0[3:0]   <= DATA;
      5'h11: F0[7:4]   <= DATA;
      5'h12: F0[11:8]  <= DATA;
      5'h13: F0[15:12] <= DATA;
      5'h14: F0[19:16] <= DATA;

      5'h16: F1[3:0]   <= DATA;
      5'h17: F1[7:4]   <= DATA;
      5'h18: F1[11:8]  <= DATA;
      5'h19: F1[15:12] <= DATA;

      5'h1B: F2[3:0]   <= DATA;
      5'h1C: F2[7:4]   <= DATA;
      5'h1D: F2[11:8]  <= DATA;
      5'h1E: F2[15:12] <= DATA;

      default:;

      endcase

   end

end

endmodule