data/full_repos/permissive/175808891/verilog/ff_addmul.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/175808891/verilog/ff_addmul.v:30: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'fixed_adder\'\nmodule fixed_adder(num1, num2, result, overflow);\n       ^~~~~~~~~~~\n                                                                              : ... Top module \'fixed_multi\'\nmodule fixed_multi(num1, num2, result, overflow);\n       ^~~~~~~~~~~\n                                                                              : ... Top module \'float_multi\'\nmodule float_multi(num1, num2, result, overflow);\n       ^~~~~~~~~~~\n                                                                              : ... Top module \'float_adder\'\nmodule float_adder(num1, num2, result, overflow);\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:142: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 5 bits.\n                                                                            : ... In instance float_adder\n  assign ex_diff = big_ex - small_ex;  \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:145: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'big_ex\' generates 5 bits.\n                                                                            : ... In instance float_adder\n  assign exCheck = (sum[11]) ? (big_ex + 5\'b1) : big_ex;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:167: Operator NEQ expects 5 bits on the LHS, but LHS\'s VARREF \'big_sig\' generates 1 bits.\n                                                                            : ... In instance float_adder\n      if(big_sig != small_ex)\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:96: Operator SHIFTR expects 16 bits on the LHS, but LHS\'s VARREF \'float1\' generates 11 bits.\n                                                                           : ... In instance float_multi\n      mid[0] = (float1 >> 10) & {16{fra2[0]}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:96: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s AND generates 16 bits.\n                                                                           : ... In instance float_multi\n      mid[0] = (float1 >> 10) & {16{fra2[0]}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:97: Operator SHIFTR expects 16 bits on the LHS, but LHS\'s VARREF \'float1\' generates 11 bits.\n                                                                           : ... In instance float_multi\n      mid[1] = (float1 >> 9) & {16{fra2[1]}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:97: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s AND generates 16 bits.\n                                                                           : ... In instance float_multi\n      mid[1] = (float1 >> 9) & {16{fra2[1]}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:98: Operator SHIFTR expects 16 bits on the LHS, but LHS\'s VARREF \'float1\' generates 11 bits.\n                                                                           : ... In instance float_multi\n      mid[2] = (float1 >> 8) & {16{fra2[2]}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:98: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s AND generates 16 bits.\n                                                                           : ... In instance float_multi\n      mid[2] = (float1 >> 8) & {16{fra2[2]}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:99: Operator SHIFTR expects 16 bits on the LHS, but LHS\'s VARREF \'float1\' generates 11 bits.\n                                                                           : ... In instance float_multi\n      mid[3] = (float1 >> 7) & {16{fra2[3]}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:99: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s AND generates 16 bits.\n                                                                           : ... In instance float_multi\n      mid[3] = (float1 >> 7) & {16{fra2[3]}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:100: Operator SHIFTR expects 16 bits on the LHS, but LHS\'s VARREF \'float1\' generates 11 bits.\n                                                                            : ... In instance float_multi\n      mid[4] = (float1 >> 6) & {16{fra2[4]}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:100: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s AND generates 16 bits.\n                                                                            : ... In instance float_multi\n      mid[4] = (float1 >> 6) & {16{fra2[4]}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:101: Operator SHIFTR expects 16 bits on the LHS, but LHS\'s VARREF \'float1\' generates 11 bits.\n                                                                            : ... In instance float_multi\n      mid[5] = (float1 >> 5) & {16{fra2[5]}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:101: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s AND generates 16 bits.\n                                                                            : ... In instance float_multi\n      mid[5] = (float1 >> 5) & {16{fra2[5]}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:102: Operator SHIFTR expects 16 bits on the LHS, but LHS\'s VARREF \'float1\' generates 11 bits.\n                                                                            : ... In instance float_multi\n      mid[6] = (float1 >> 4) & {16{fra2[6]}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:102: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s AND generates 16 bits.\n                                                                            : ... In instance float_multi\n      mid[6] = (float1 >> 4) & {16{fra2[6]}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:103: Operator SHIFTR expects 16 bits on the LHS, but LHS\'s VARREF \'float1\' generates 11 bits.\n                                                                            : ... In instance float_multi\n      mid[7] = (float1 >> 3) & {16{fra2[7]}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:103: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s AND generates 16 bits.\n                                                                            : ... In instance float_multi\n      mid[7] = (float1 >> 3) & {16{fra2[7]}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:104: Operator SHIFTR expects 16 bits on the LHS, but LHS\'s VARREF \'float1\' generates 11 bits.\n                                                                            : ... In instance float_multi\n      mid[8] = (float1 >> 2) & {16{fra2[8]}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:104: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s AND generates 16 bits.\n                                                                            : ... In instance float_multi\n      mid[8] = (float1 >> 2) & {16{fra2[8]}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:105: Operator SHIFTR expects 16 bits on the LHS, but LHS\'s VARREF \'float1\' generates 11 bits.\n                                                                            : ... In instance float_multi\n      mid[9] = (float1 >> 1) & {16{fra2[9]}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:105: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s AND generates 16 bits.\n                                                                            : ... In instance float_multi\n      mid[9] = (float1 >> 1) & {16{fra2[9]}};\n             ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:50: Operator SHIFTR expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[0] = (num1 >> 8) & {16{num2[0]}};\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:50: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[0] = (num1 >> 8) & {16{num2[0]}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:51: Operator SHIFTR expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[1] = (num1 >> 7) & {16{num2[1]}};\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:51: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[1] = (num1 >> 7) & {16{num2[1]}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:52: Operator SHIFTR expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[2] = (num1 >> 6) & {16{num2[2]}};\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:52: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[2] = (num1 >> 6) & {16{num2[2]}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:53: Operator SHIFTR expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[3] = (num1 >> 5) & {16{num2[3]}};\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:53: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[3] = (num1 >> 5) & {16{num2[3]}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:54: Operator SHIFTR expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[4] = (num1 >> 4) & {16{num2[4]}};\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:54: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[4] = (num1 >> 4) & {16{num2[4]}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:55: Operator SHIFTR expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[5] = (num1 >> 3) & {16{num2[5]}};\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:55: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[5] = (num1 >> 3) & {16{num2[5]}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:56: Operator SHIFTR expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[6] = (num1 >> 2) & {16{num2[6]}};\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:56: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[6] = (num1 >> 2) & {16{num2[6]}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:57: Operator SHIFTR expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[7] = (num1 >> 1) & {16{num2[7]}};\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:57: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[7] = (num1 >> 1) & {16{num2[7]}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:58: Operator AND expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[8] =  num1 & {16{num2[8]}};\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:58: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[8] =  num1 & {16{num2[8]}};\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:59: Operator SHIFTL expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[9] = (num1 << 1) & {16{num2[9]}};\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:59: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[9] = (num1 << 1) & {16{num2[9]}};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:60: Operator SHIFTL expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[10] = (num1 << 2) & {16{num2[10]}};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:60: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[10] = (num1 << 2) & {16{num2[10]}};\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:61: Operator SHIFTL expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[11] = (num1 << 3) & {16{num2[11]}};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:61: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[11] = (num1 << 3) & {16{num2[11]}};\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:62: Operator SHIFTL expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[12] = (num1 << 4) & {16{num2[12]}};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:62: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[12] = (num1 << 4) & {16{num2[12]}};\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:63: Operator SHIFTL expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[13] = (num1 << 5) & {16{num2[13]}};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:63: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[13] = (num1 << 5) & {16{num2[13]}};\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:64: Operator SHIFTL expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[14] = (num1 << 6) & {16{num2[14]}};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:64: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[14] = (num1 << 6) & {16{num2[14]}};\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:65: Operator SHIFTL expects 23 bits on the LHS, but LHS\'s VARREF \'num1\' generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[15] = (num1 << 7) & {16{num2[15]}};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/175808891/verilog/ff_addmul.v:65: Operator AND expects 23 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                           : ... In instance fixed_multi\n      mid[15] = (num1 << 7) & {16{num2[15]}};\n                            ^\n%Error: Exiting due to 56 warning(s)\n'
module float_adder(num1, num2, result, overflow);
  input [15:0] num1, num2;
  output [15:0] result;
  output overflow;
  reg [15:0] bigNum, smallNum;
  wire [9:0] big_fra, small_fra;
  wire [4:0] big_ex, small_ex;
  wire [5:0] exCheck;
  wire big_sig, small_sig;
  wire [10:0] big_float, small_float;
  reg [10:0] sign_small_float, shifted_small_float;
  wire [3:0] ex_diff;
  wire [11:0] sum;
  
  assign overflow = (big_sig & small_sig) & ((&big_ex) & (&small_ex)) & sum[11];
  assign result[15] = big_sig;
  assign result[14:10] = exCheck[4:0];
  assign result[9:0] = (sum[11]) ? sum[10:1] : sum[9:0];


  assign {big_sig, big_ex, big_fra} = bigNum;
  assign {small_sig, small_ex, small_fra} = smallNum;

  assign big_float = {1'b1, big_fra};
  assign small_float = {1'b1, small_fra};
  assign ex_diff = big_ex - small_ex;
  assign sum = sign_small_float + big_float;

  assign exCheck = (sum[11]) ? (big_ex + 5'b1) : big_ex;

  always@*
    begin
      case (ex_diff)
        0: shifted_small_float = small_float;
        1: shifted_small_float = (small_float >> 1);
        2: shifted_small_float = (small_float >> 2);
        3: shifted_small_float = (small_float >> 3);
        4: shifted_small_float = (small_float >> 4);
        5: shifted_small_float = (small_float >> 5);
        6: shifted_small_float = (small_float >> 6);
        7: shifted_small_float = (small_float >> 7);
        8: shifted_small_float = (small_float >> 8);
        9: shifted_small_float = (small_float >> 9);
        10: shifted_small_float = (small_float >> 10);
        default: shifted_small_float = 11'b0;
      endcase
    end

  always@*
    begin
      if(big_sig != small_ex)
        begin
          sign_small_float = ~shifted_small_float + 11'b1;
        end
      else
        begin
          sign_small_float = shifted_small_float;
        end
    end

  always@*
    begin
      if(num2[14:10] > num1[14:10])
        begin
          bigNum = num2;
          smallNum = num1;
        end
      else if(num2[14:10] == num1[14:10])
        begin
          if(num2[9:0] > num1[9:0])
            begin
              bigNum = num2;
              smallNum = num1;
            end
          else
            begin
              bigNum = num1;
              smallNum = num2;
            end
        end
      else
        begin
          bigNum = num1;
          smallNum = num2;
        end
    end

endmodule
module float_adder(num1, num2, result, overflow);

  input [15:0] num1, num2;
  output [15:0] result;
  output overflow;
  reg [15:0] bigNum, smallNum;
  wire [9:0] big_fra, small_fra;
  wire [4:0] big_ex, small_ex;
  wire [5:0] exCheck;
  wire big_sig, small_sig;
  wire [10:0] big_float, small_float;
  reg [10:0] sign_small_float, shifted_small_float;
  wire [3:0] ex_diff;
  wire [11:0] sum;
  
  assign overflow = (big_sig & small_sig) & ((&big_ex) & (&small_ex)) & sum[11];
  assign result[15] = big_sig;
  assign result[14:10] = exCheck[4:0];
  assign result[9:0] = (sum[11]) ? sum[10:1] : sum[9:0];


  assign {big_sig, big_ex, big_fra} = bigNum;
  assign {small_sig, small_ex, small_fra} = smallNum;

  assign big_float = {1'b1, big_fra};
  assign small_float = {1'b1, small_fra};
  assign ex_diff = big_ex - small_ex;
  assign sum = sign_small_float + big_float;

  assign exCheck = (sum[11]) ? (big_ex + 5'b1) : big_ex;

  always@*
    begin
      case (ex_diff)
        0: shifted_small_float = small_float;
        1: shifted_small_float = (small_float >> 1);
        2: shifted_small_float = (small_float >> 2);
        3: shifted_small_float = (small_float >> 3);
        4: shifted_small_float = (small_float >> 4);
        5: shifted_small_float = (small_float >> 5);
        6: shifted_small_float = (small_float >> 6);
        7: shifted_small_float = (small_float >> 7);
        8: shifted_small_float = (small_float >> 8);
        9: shifted_small_float = (small_float >> 9);
        10: shifted_small_float = (small_float >> 10);
        default: shifted_small_float = 11'b0;
      endcase
    end

  always@*
    begin
      if(big_sig != small_ex)
        begin
          sign_small_float = ~shifted_small_float + 11'b1;
        end
      else
        begin
          sign_small_float = shifted_small_float;
        end
    end

  always@*
    begin
      if(num2[14:10] > num1[14:10])
        begin
          bigNum = num2;
          smallNum = num1;
        end
      else if(num2[14:10] == num1[14:10])
        begin
          if(num2[9:0] > num1[9:0])
            begin
              bigNum = num2;
              smallNum = num1;
            end
          else
            begin
              bigNum = num1;
              smallNum = num2;
            end
        end
      else
        begin
          bigNum = num1;
          smallNum = num2;
        end
    end

endmodule