data/full_repos/permissive/125520060/problem-1004-mux2_4/top.v
data/verilator_xmls/4edaccde-86b6-4310-a902-0969dff6bfb4.xml
module mux2_4(
    a
   ,b
   ,sel
   ,q
);

input   [3:0]   a, b;
input           sel;
output  [3:0]   q;

assign q = sel ? a : b;

endmodule
module mux2_4(
    a
   ,b
   ,sel
   ,q
);


input   [3:0]   a, b;
input           sel;
output  [3:0]   q;

assign q = sel ? a : b;

endmodule