data/full_repos/permissive/175808891/verilog/dct.v
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1: b'%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:103: Cell has missing pin: \'en\'\nbutterfly b1(x01,x71,x[0],x[7]);\n          ^~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:104: Cell has missing pin: \'en\'\nbutterfly b2(x11,x61,x[1],x[6]);\n          ^~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:105: Cell has missing pin: \'en\'\nbutterfly b3(x21,x51,x[2],x[5]);\n          ^~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:106: Cell has missing pin: \'en\'\nbutterfly b4(x31,x41,x[3],x[4]);\n          ^~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:109: Cell has missing pin: \'en\'\nbutterfly b5(x02,x32,x01,x31);\n          ^~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:110: Cell has missing pin: \'en\'\nbutterfly b6(x12,x22,x11,x21);\n          ^~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:128: Cell has missing pin: \'en\'\nbutterfly b9(x03,x13,x02,x12);\n          ^~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:137: Cell has missing pin: \'en\'\nbutterfly b11(x43,x53,x42,x52);\n          ^~~\n%Warning-PINMISSING: data/full_repos/permissive/175808891/verilog/dct.v:138: Cell has missing pin: \'en\'\nbutterfly b12(x63,x73,x62,x72);\n          ^~~\n%Error: data/full_repos/permissive/175808891/verilog/dct.v:140: Can\'t find definition of variable: \'sqrt8\'\n                                                              : ... Suggested alternative: \'sqrt2\'\nassign x1=(x03*sqrt8);\n               ^~~~~\n%Error: Exiting due to 1 error(s), 9 warning(s)\n'
module butterfly(
    output reg [31:0] sum,diff,
    input [31:0] x,y,
    input en
    );

always @(en or x or y)
begin
  sum=x+y;
  diff=x-y;
end
endmodule
module butterfly(
    output reg [31:0] sum,diff,
    input [31:0] x,y,
    input en
    );


always @(en or x or y)
begin
  sum=x+y;
  diff=x-y;
end
endmodule