data/full_repos/permissive/163728837/src/mmap_leds.v
1: b'%Error: data/full_repos/permissive/163728837/src/mmap_leds.v:102: Cannot find file containing module: \'angle_rom\'\nangle_rom angle_rom (\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/163728837/src,data/full_repos/permissive/163728837/angle_rom\n             data/full_repos/permissive/163728837/src,data/full_repos/permissive/163728837/angle_rom.v\n             data/full_repos/permissive/163728837/src,data/full_repos/permissive/163728837/angle_rom.sv\n             angle_rom\n             angle_rom.v\n             angle_rom.sv\n             obj_dir/angle_rom\n             obj_dir/angle_rom.v\n             obj_dir/angle_rom.sv\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/mmap_leds.v:191: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n                                                                        : ... In instance mmap_interface\n        tram_waddr = 13\'d0;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/mmap_leds.v:192: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance mmap_interface\n        tram_write_data = 8\'d0;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/mmap_leds.v:194: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n                                                                        : ... In instance mmap_interface\n        tpram_waddr = 13\'d0;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/mmap_leds.v:195: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance mmap_interface\n        tpram_write_data = 8\'d0;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/mmap_leds.v:199: Operator ASSIGN expects 40 bits on the Assign RHS, but Assign RHS\'s CONST \'39\'h0\' generates 39 bits.\n                                                                        : ... In instance mmap_interface\n        smeta_write_data = 39\'d0;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/mmap_leds.v:208: Operator NEQ expects 9 bits on the RHS, but RHS\'s CONST \'8\'hf0\' generates 8 bits.\n                                                                        : ... In instance mmap_interface\n            if (lw_raddr_q != 8\'d240) begin\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/mmap_leds.v:261: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'led_q\' generates 3 bits.\n                                                                        : ... In instance mmap_interface\n                            data_d[7:0] = led_q;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/mmap_leds.v:334: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                        : ... In instance mmap_interface\n                                pipe_done_d = 10\'d0;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/mmap_leds.v:318: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'31\'h0\' generates 31 bits.\n                                                                        : ... In instance mmap_interface\n                            case (m_address)\n                            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/mmap_leds.v:318: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'31\'h1\' generates 31 bits.\n                                                                        : ... In instance mmap_interface\n                            case (m_address)\n                            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/mmap_leds.v:382: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                        : ... In instance mmap_interface\n                lw_raddr_d = 8\'d0;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/163728837/src/mmap_leds.v:408: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                        : ... In instance mmap_interface\n                pipe_done_d = 10\'d0;\n                            ^\n%Error: Exiting due to 1 error(s), 12 warning(s)\n'
module mmap_interface (
    input clk,
    input rst,

    output [2:0] leds,
    output flush_busy,


    input m_new_cmd,
    input m_write,
    input [5:0] m_cmd,
    input [31:0] m_address,
    input [31:0] m_data,


    output [31:0] s_data,
    output s_drdy,


    output [79:0] angle,


    output reg [8:0] cast_x,
    output [15:0] map_pos_x,
    output [15:0] map_pos_y,
    output reg cast_start,
    input cast_busy,
    input cast_done,


    input [39:0] line_height,
    input line_write_ready,
    input line_write_done,
    output reg line_write_start,
    output [8:0] line_ram_raddr,
    input [15:0] line_ram_read_data,

    output reg [13:0] tram_waddr,
    output reg [3:0] tram_write_data,
    output reg tram_write_en,
    output reg [7:0] tpram_waddr,
    output reg [15:0] tpram_write_data,
    output reg tpram_write_en,


    output reg [6:0] smeta_waddr,
    output reg [39:0] smeta_write_data,
    output reg smeta_write_en,
    output reg sprite_start,
    input sprite_done,


    output reg [7:0] lcd_data_in,
    output reg lcd_data_dcx,
    output reg lcd_start,
    output lcd_rst,
    input lcd_done
);


localparam CMD_LEDS = 0,
    CMD_TEXP_LOAD = 1,
    CMD_TEX_LOAD = 3,
    CMD_CAST_FB = 4,
    CMD_LCD = 5,
    CMD_SPRITE_META = 6;

reg [2:0] led_d, led_q;
reg [31:0] data_d, data_q;
reg drdy_d, drdy_q;

assign leds = led_q;
assign s_data = data_q;
assign s_drdy = drdy_q;
assign lcd_rst = lcd_rst_q;
assign flush_busy = lcdstate_q != LCDIDLE;


localparam IDLE = 0,
    WAIT_DUMP = 4,
    WAIT_LCD = 5,
    WAIT_FOR_CAST = 6,
    WAIT_FOR_LINE = 7,
    CAST_FB = 8,
    CAST_FB_START = 9;

localparam LCDIDLE= 0,
    LCD_FB_DUMP = 2,
    LCD_FB_READRAM_RES = 3,
    LCD_FB_SPLIT = 4,
    LCD_FB_SPLIT_WAIT = 5,
    LCD_FB_DUMP_START = 6;

reg [4:0] state_d, state_q;
reg [4:0] lcdstate_d, lcdstate_q;


reg [6:0] angle_addr;
angle_rom angle_rom (
    .clk(clk),
    .addr(angle_addr),
    .angle(angle)
);


reg [15:0] map_pos_x_d, map_pos_x_q;
reg [15:0] map_pos_y_d, map_pos_y_q;
reg [6:0] turn_addr_d, turn_addr_q;


assign map_pos_x = map_pos_x_q;
assign map_pos_y = map_pos_y_q;
reg [8:0] lw_raddr_d, lw_raddr_q;
reg [8:0] lw_base_raddr_d, lw_base_raddr_q;
assign line_ram_raddr = lw_raddr_q + lw_base_raddr_q;


localparam WIDTH = 320,
    HEIGHT = 240;
reg [8:0] camera_x_d, camera_x_q;
reg dump_ready_d, dump_ready_q;
reg line_go_d, line_go_q;
reg lcd_go_d, lcd_go_q;
reg lcd_ready_d, lcd_ready_q;
reg lcd_done_d, lcd_done_q;



reg [8:0] pipe_done_d, pipe_done_q; 


reg lcd_rst_d, lcd_rst_q;
reg lcd_bcnt_d, lcd_bcnt_q;


reg [31:0] frame_cycle_d, frame_cycle_q;
reg [31:0] lframe_cycle_d, lframe_cycle_q;

initial begin
    lcd_rst_q = 1'b0;
    camera_x_q = 9'd0;
    turn_addr_q = 7'd0;
    lframe_cycle_q = 0;
end










always @(*) begin
        state_d = state_q;
        lcdstate_d = lcdstate_q;
        led_d = led_q;
        data_d = data_q;
        drdy_d = 0;
        line_write_start = 1'b0;
        lw_raddr_d = lw_raddr_q;
        lw_base_raddr_d = lw_base_raddr_q;
        dump_ready_d = dump_ready_q;
        line_go_d = line_go_q;
        lcd_go_d = lcd_go_q;
        lcd_ready_d = lcd_ready_q;
        lcd_done_d = lcd_done_q;
        pipe_done_d = pipe_done_q;
        frame_cycle_d = frame_cycle_q + 1'b1;
        lframe_cycle_d = lframe_cycle_q;

        camera_x_d = camera_x_q;
        map_pos_x_d = map_pos_x_q;
        map_pos_y_d = map_pos_y_q;
        turn_addr_d = turn_addr_q;
        cast_x = camera_x_q;

        angle_addr = turn_addr_q;
        cast_start = 1'b0;

        lcd_data_in = 8'd0;
        lcd_data_dcx = 1'b0;
        lcd_start = 1'b0;
        lcd_rst_d = lcd_rst_q;
        lcd_bcnt_d = lcd_bcnt_q;

        tram_waddr = 13'd0;
        tram_write_data = 8'd0;
        tram_write_en = 1'b0;
        tpram_waddr = 13'd0;
        tpram_write_data = 8'd0;
        tpram_write_en = 1'b0;

        smeta_waddr = 7'd0;
        smeta_write_data = 39'd0;
        smeta_write_en = 1'b0;
        sprite_start = 1'b0;

        case (lcdstate_q)
          LCDIDLE: begin

          end
          LCD_FB_DUMP: begin
            if (lw_raddr_q != 8'd240) begin
                lcdstate_d = LCD_FB_READRAM_RES;
            end else begin
                lcd_done_d = 1'b1;
                lcdstate_d = LCDIDLE;

                if (lw_base_raddr_q == 9'd0) begin
                    lw_base_raddr_d = 9'd240;
                end else begin
                    lw_base_raddr_d = 9'd0;
                end
            end
          end
          LCD_FB_READRAM_RES: begin
            data_d[15:0] = line_ram_read_data;
            lcd_bcnt_d = 1'b0;
            lcdstate_d = LCD_FB_SPLIT;
          end
          LCD_FB_SPLIT: begin

            lcd_bcnt_d = ~lcd_bcnt_q;
            if (!lcd_bcnt_q) begin
                lcd_data_in = data_q[15:8];
            end else begin
                lcd_data_in = data_q[7:0];
            end

            lcd_data_dcx = 1'b1;
            lcd_start = 1'b1;
            lcdstate_d = LCD_FB_SPLIT_WAIT;
          end
          LCD_FB_SPLIT_WAIT: begin
            if (lcd_done) begin
                if (!lcd_bcnt_q) begin
                    lw_raddr_d = lw_raddr_q + 1'b1;
                    lcdstate_d = LCD_FB_DUMP;
                end else begin
                    lcdstate_d = LCD_FB_SPLIT;
                end
            end
          end
          default: lcdstate_d = LCDIDLE;
        endcase

        case (state_q)
          IDLE: begin
            if (m_new_cmd) begin
                led_d[0] = 1'b0;
                case (m_cmd)
                    CMD_LEDS: begin
                        if (m_write) begin
                            led_d[2:0] = m_data[2:0];
                        end else begin
                            data_d[7:0] = led_q;
                            drdy_d = 1'b1;
                        end
                    end
                    CMD_LCD: begin


                        if (m_write) begin
                            state_d = WAIT_LCD;
                            lcd_data_in = m_data[7:0];
                            lcd_data_dcx = m_data[8];
                            lcd_start = 1'b1;
                        end else begin

                            lcd_rst_d = m_address[0];
                            drdy_d = 1'b1;
                        end
                    end
                    CMD_TEX_LOAD: begin
                        if (m_write) begin
                            tram_waddr = m_address[13:0];
                            tram_write_data = m_data[3:0];
                            tram_write_en = 1'b1;
                        end else begin

                            data_d = 32'd0;
                            drdy_d = 1'b1;
                        end
                    end
                    CMD_TEXP_LOAD: begin
                        if (m_write) begin
                            tpram_waddr = m_address[7:0];
                            tpram_write_data = m_data[15:0];
                            tpram_write_en = 1'b1;
                        end else begin

                            data_d = 32'd0;
                            drdy_d = 1'b1;
                        end
                    end
                    CMD_SPRITE_META: begin
                        if (m_write) begin
                            smeta_waddr = m_address[6:0];

                            smeta_write_data[39:32] = m_address[15:8];

                            smeta_write_data[31:0] = m_data;
                            smeta_write_en = 1'b1;
                            led_d[1] = 1'b1;
                        end else begin

                            data_d = 32'd0;
                            drdy_d = 1'b1;
                        end
                    end
                    CMD_CAST_FB: begin
                        if (m_write) begin
                            case (m_address)
                            31'd0: begin
                                map_pos_x_d = m_data[31:16];
                                map_pos_y_d = m_data[15:0];
                                camera_x_d = 9'd0;
                            end
                            31'd1: begin
                                turn_addr_d = m_data[6:0];
                                state_d = CAST_FB_START;
                                lcd_data_dcx = 1'b0;
                                lcd_data_in = 8'h2C;
                                lcd_start = 1'b1;

                                dump_ready_d = 1'b1;
                                lcd_ready_d = 1'b1;
                                line_go_d = 1'b0;
                                pipe_done_d = 10'd0;

                                sprite_start = 1'b1;
                                frame_cycle_d = 32'd0;
                            end
                            endcase
                        end else begin

                            data_d = lframe_cycle_q;
                            drdy_d = 1'b1;
                        end
                    end
                endcase
            end else begin
                led_d[0] = 1'b1;
            end
          end
          CAST_FB_START: begin

              if (sprite_done) begin
                cast_start = 1'b1;
                state_d = CAST_FB;
              end
          end
          CAST_FB: begin
              if (cast_done) begin
                line_go_d = 1'b1;
                camera_x_d = camera_x_q + 1'b1;
              end

              if (line_go_q && dump_ready_q) begin
                line_write_start = 1'b1;
                line_go_d = 1'b0;
                dump_ready_d = 1'b0;

                if (camera_x_q != WIDTH) begin
                    cast_start = 1'b1;
                end
              end

              if (line_write_done) begin
                lcd_go_d = 1'b1;
              end

              if (lcd_go_q && lcd_ready_q) begin
                dump_ready_d = 1'b1;
                lcd_go_d = 1'b0;
                lcd_ready_d = 1'b0;
                lw_raddr_d = 8'd0;
                lcdstate_d = LCD_FB_DUMP;
              end

              if (lcd_done_q) begin
                lcd_ready_d = 1'b1;
                lcd_done_d = 1'b0;
              end







              if (camera_x_q == WIDTH && !cast_busy && dump_ready_q && lcd_ready_q) begin
                pipe_done_d = pipe_done_q + 1'b1;
                if (&pipe_done_q) begin
                  lcd_data_dcx = 1'b0;
                  lcd_data_in = 8'h00;
                  lcd_start = 1'b1;
                  state_d = WAIT_LCD;

                  lframe_cycle_d = frame_cycle_q;
                end
              end else begin
                pipe_done_d = 10'd0;
              end
          end
          WAIT_LCD: begin
            if (lcd_done) begin
                state_d = IDLE;
            end
          end
          default: state_d = IDLE;
        endcase
end

always @(posedge clk) begin
    if (rst) begin
        led_q <= 0;
        data_q <= 0;
        drdy_q <= 0;
    	state_q = 0;
        lcdstate_q = 0;
        map_pos_x_q <= 0;
        map_pos_y_q <= 0;
        lw_raddr_q <= 0;
        lw_base_raddr_q <= 0;
        camera_x_q <= 0;
        turn_addr_q <= 0;
        lcd_bcnt_q <= 0;
      end else begin
        state_q = state_d;
        lcdstate_q = lcdstate_d;
        data_q <= data_d;
        drdy_q <= drdy_d;
        led_q <= led_d;
        map_pos_x_q <= map_pos_x_d;
        map_pos_y_q <= map_pos_y_d;
        lw_raddr_q <= lw_raddr_d;
        lw_base_raddr_q <= lw_base_raddr_d;
        camera_x_q <= camera_x_d;
        turn_addr_q <= turn_addr_d;
        lcd_bcnt_q <= lcd_bcnt_d;
      end

      lcd_rst_q <= lcd_rst_d;
      dump_ready_q <= dump_ready_d;
      line_go_q <= line_go_d;
      lcd_done_q <= lcd_done_d;
      lcd_go_q <= lcd_go_d;
      lcd_ready_q <= lcd_ready_d;
      pipe_done_q <= pipe_done_d;
      frame_cycle_q <= frame_cycle_d;
      lframe_cycle_q <= lframe_cycle_d;
end

endmodule
module mmap_interface (
    input clk,
    input rst,

    output [2:0] leds,
    output flush_busy,


    input m_new_cmd,
    input m_write,
    input [5:0] m_cmd,
    input [31:0] m_address,
    input [31:0] m_data,


    output [31:0] s_data,
    output s_drdy,


    output [79:0] angle,


    output reg [8:0] cast_x,
    output [15:0] map_pos_x,
    output [15:0] map_pos_y,
    output reg cast_start,
    input cast_busy,
    input cast_done,


    input [39:0] line_height,
    input line_write_ready,
    input line_write_done,
    output reg line_write_start,
    output [8:0] line_ram_raddr,
    input [15:0] line_ram_read_data,

    output reg [13:0] tram_waddr,
    output reg [3:0] tram_write_data,
    output reg tram_write_en,
    output reg [7:0] tpram_waddr,
    output reg [15:0] tpram_write_data,
    output reg tpram_write_en,


    output reg [6:0] smeta_waddr,
    output reg [39:0] smeta_write_data,
    output reg smeta_write_en,
    output reg sprite_start,
    input sprite_done,


    output reg [7:0] lcd_data_in,
    output reg lcd_data_dcx,
    output reg lcd_start,
    output lcd_rst,
    input lcd_done
);



localparam CMD_LEDS = 0,
    CMD_TEXP_LOAD = 1,
    CMD_TEX_LOAD = 3,
    CMD_CAST_FB = 4,
    CMD_LCD = 5,
    CMD_SPRITE_META = 6;

reg [2:0] led_d, led_q;
reg [31:0] data_d, data_q;
reg drdy_d, drdy_q;

assign leds = led_q;
assign s_data = data_q;
assign s_drdy = drdy_q;
assign lcd_rst = lcd_rst_q;
assign flush_busy = lcdstate_q != LCDIDLE;


localparam IDLE = 0,
    WAIT_DUMP = 4,
    WAIT_LCD = 5,
    WAIT_FOR_CAST = 6,
    WAIT_FOR_LINE = 7,
    CAST_FB = 8,
    CAST_FB_START = 9;

localparam LCDIDLE= 0,
    LCD_FB_DUMP = 2,
    LCD_FB_READRAM_RES = 3,
    LCD_FB_SPLIT = 4,
    LCD_FB_SPLIT_WAIT = 5,
    LCD_FB_DUMP_START = 6;

reg [4:0] state_d, state_q;
reg [4:0] lcdstate_d, lcdstate_q;


reg [6:0] angle_addr;
angle_rom angle_rom (
    .clk(clk),
    .addr(angle_addr),
    .angle(angle)
);


reg [15:0] map_pos_x_d, map_pos_x_q;
reg [15:0] map_pos_y_d, map_pos_y_q;
reg [6:0] turn_addr_d, turn_addr_q;


assign map_pos_x = map_pos_x_q;
assign map_pos_y = map_pos_y_q;
reg [8:0] lw_raddr_d, lw_raddr_q;
reg [8:0] lw_base_raddr_d, lw_base_raddr_q;
assign line_ram_raddr = lw_raddr_q + lw_base_raddr_q;


localparam WIDTH = 320,
    HEIGHT = 240;
reg [8:0] camera_x_d, camera_x_q;
reg dump_ready_d, dump_ready_q;
reg line_go_d, line_go_q;
reg lcd_go_d, lcd_go_q;
reg lcd_ready_d, lcd_ready_q;
reg lcd_done_d, lcd_done_q;



reg [8:0] pipe_done_d, pipe_done_q; 


reg lcd_rst_d, lcd_rst_q;
reg lcd_bcnt_d, lcd_bcnt_q;


reg [31:0] frame_cycle_d, frame_cycle_q;
reg [31:0] lframe_cycle_d, lframe_cycle_q;

initial begin
    lcd_rst_q = 1'b0;
    camera_x_q = 9'd0;
    turn_addr_q = 7'd0;
    lframe_cycle_q = 0;
end










always @(*) begin
        state_d = state_q;
        lcdstate_d = lcdstate_q;
        led_d = led_q;
        data_d = data_q;
        drdy_d = 0;
        line_write_start = 1'b0;
        lw_raddr_d = lw_raddr_q;
        lw_base_raddr_d = lw_base_raddr_q;
        dump_ready_d = dump_ready_q;
        line_go_d = line_go_q;
        lcd_go_d = lcd_go_q;
        lcd_ready_d = lcd_ready_q;
        lcd_done_d = lcd_done_q;
        pipe_done_d = pipe_done_q;
        frame_cycle_d = frame_cycle_q + 1'b1;
        lframe_cycle_d = lframe_cycle_q;

        camera_x_d = camera_x_q;
        map_pos_x_d = map_pos_x_q;
        map_pos_y_d = map_pos_y_q;
        turn_addr_d = turn_addr_q;
        cast_x = camera_x_q;

        angle_addr = turn_addr_q;
        cast_start = 1'b0;

        lcd_data_in = 8'd0;
        lcd_data_dcx = 1'b0;
        lcd_start = 1'b0;
        lcd_rst_d = lcd_rst_q;
        lcd_bcnt_d = lcd_bcnt_q;

        tram_waddr = 13'd0;
        tram_write_data = 8'd0;
        tram_write_en = 1'b0;
        tpram_waddr = 13'd0;
        tpram_write_data = 8'd0;
        tpram_write_en = 1'b0;

        smeta_waddr = 7'd0;
        smeta_write_data = 39'd0;
        smeta_write_en = 1'b0;
        sprite_start = 1'b0;

        case (lcdstate_q)
          LCDIDLE: begin

          end
          LCD_FB_DUMP: begin
            if (lw_raddr_q != 8'd240) begin
                lcdstate_d = LCD_FB_READRAM_RES;
            end else begin
                lcd_done_d = 1'b1;
                lcdstate_d = LCDIDLE;

                if (lw_base_raddr_q == 9'd0) begin
                    lw_base_raddr_d = 9'd240;
                end else begin
                    lw_base_raddr_d = 9'd0;
                end
            end
          end
          LCD_FB_READRAM_RES: begin
            data_d[15:0] = line_ram_read_data;
            lcd_bcnt_d = 1'b0;
            lcdstate_d = LCD_FB_SPLIT;
          end
          LCD_FB_SPLIT: begin

            lcd_bcnt_d = ~lcd_bcnt_q;
            if (!lcd_bcnt_q) begin
                lcd_data_in = data_q[15:8];
            end else begin
                lcd_data_in = data_q[7:0];
            end

            lcd_data_dcx = 1'b1;
            lcd_start = 1'b1;
            lcdstate_d = LCD_FB_SPLIT_WAIT;
          end
          LCD_FB_SPLIT_WAIT: begin
            if (lcd_done) begin
                if (!lcd_bcnt_q) begin
                    lw_raddr_d = lw_raddr_q + 1'b1;
                    lcdstate_d = LCD_FB_DUMP;
                end else begin
                    lcdstate_d = LCD_FB_SPLIT;
                end
            end
          end
          default: lcdstate_d = LCDIDLE;
        endcase

        case (state_q)
          IDLE: begin
            if (m_new_cmd) begin
                led_d[0] = 1'b0;
                case (m_cmd)
                    CMD_LEDS: begin
                        if (m_write) begin
                            led_d[2:0] = m_data[2:0];
                        end else begin
                            data_d[7:0] = led_q;
                            drdy_d = 1'b1;
                        end
                    end
                    CMD_LCD: begin


                        if (m_write) begin
                            state_d = WAIT_LCD;
                            lcd_data_in = m_data[7:0];
                            lcd_data_dcx = m_data[8];
                            lcd_start = 1'b1;
                        end else begin

                            lcd_rst_d = m_address[0];
                            drdy_d = 1'b1;
                        end
                    end
                    CMD_TEX_LOAD: begin
                        if (m_write) begin
                            tram_waddr = m_address[13:0];
                            tram_write_data = m_data[3:0];
                            tram_write_en = 1'b1;
                        end else begin

                            data_d = 32'd0;
                            drdy_d = 1'b1;
                        end
                    end
                    CMD_TEXP_LOAD: begin
                        if (m_write) begin
                            tpram_waddr = m_address[7:0];
                            tpram_write_data = m_data[15:0];
                            tpram_write_en = 1'b1;
                        end else begin

                            data_d = 32'd0;
                            drdy_d = 1'b1;
                        end
                    end
                    CMD_SPRITE_META: begin
                        if (m_write) begin
                            smeta_waddr = m_address[6:0];

                            smeta_write_data[39:32] = m_address[15:8];

                            smeta_write_data[31:0] = m_data;
                            smeta_write_en = 1'b1;
                            led_d[1] = 1'b1;
                        end else begin

                            data_d = 32'd0;
                            drdy_d = 1'b1;
                        end
                    end
                    CMD_CAST_FB: begin
                        if (m_write) begin
                            case (m_address)
                            31'd0: begin
                                map_pos_x_d = m_data[31:16];
                                map_pos_y_d = m_data[15:0];
                                camera_x_d = 9'd0;
                            end
                            31'd1: begin
                                turn_addr_d = m_data[6:0];
                                state_d = CAST_FB_START;
                                lcd_data_dcx = 1'b0;
                                lcd_data_in = 8'h2C;
                                lcd_start = 1'b1;

                                dump_ready_d = 1'b1;
                                lcd_ready_d = 1'b1;
                                line_go_d = 1'b0;
                                pipe_done_d = 10'd0;

                                sprite_start = 1'b1;
                                frame_cycle_d = 32'd0;
                            end
                            endcase
                        end else begin

                            data_d = lframe_cycle_q;
                            drdy_d = 1'b1;
                        end
                    end
                endcase
            end else begin
                led_d[0] = 1'b1;
            end
          end
          CAST_FB_START: begin

              if (sprite_done) begin
                cast_start = 1'b1;
                state_d = CAST_FB;
              end
          end
          CAST_FB: begin
              if (cast_done) begin
                line_go_d = 1'b1;
                camera_x_d = camera_x_q + 1'b1;
              end

              if (line_go_q && dump_ready_q) begin
                line_write_start = 1'b1;
                line_go_d = 1'b0;
                dump_ready_d = 1'b0;

                if (camera_x_q != WIDTH) begin
                    cast_start = 1'b1;
                end
              end

              if (line_write_done) begin
                lcd_go_d = 1'b1;
              end

              if (lcd_go_q && lcd_ready_q) begin
                dump_ready_d = 1'b1;
                lcd_go_d = 1'b0;
                lcd_ready_d = 1'b0;
                lw_raddr_d = 8'd0;
                lcdstate_d = LCD_FB_DUMP;
              end

              if (lcd_done_q) begin
                lcd_ready_d = 1'b1;
                lcd_done_d = 1'b0;
              end







              if (camera_x_q == WIDTH && !cast_busy && dump_ready_q && lcd_ready_q) begin
                pipe_done_d = pipe_done_q + 1'b1;
                if (&pipe_done_q) begin
                  lcd_data_dcx = 1'b0;
                  lcd_data_in = 8'h00;
                  lcd_start = 1'b1;
                  state_d = WAIT_LCD;

                  lframe_cycle_d = frame_cycle_q;
                end
              end else begin
                pipe_done_d = 10'd0;
              end
          end
          WAIT_LCD: begin
            if (lcd_done) begin
                state_d = IDLE;
            end
          end
          default: state_d = IDLE;
        endcase
end

always @(posedge clk) begin
    if (rst) begin
        led_q <= 0;
        data_q <= 0;
        drdy_q <= 0;
    	state_q = 0;
        lcdstate_q = 0;
        map_pos_x_q <= 0;
        map_pos_y_q <= 0;
        lw_raddr_q <= 0;
        lw_base_raddr_q <= 0;
        camera_x_q <= 0;
        turn_addr_q <= 0;
        lcd_bcnt_q <= 0;
      end else begin
        state_q = state_d;
        lcdstate_q = lcdstate_d;
        data_q <= data_d;
        drdy_q <= drdy_d;
        led_q <= led_d;
        map_pos_x_q <= map_pos_x_d;
        map_pos_y_q <= map_pos_y_d;
        lw_raddr_q <= lw_raddr_d;
        lw_base_raddr_q <= lw_base_raddr_d;
        camera_x_q <= camera_x_d;
        turn_addr_q <= turn_addr_d;
        lcd_bcnt_q <= lcd_bcnt_d;
      end

      lcd_rst_q <= lcd_rst_d;
      dump_ready_q <= dump_ready_d;
      line_go_q <= line_go_d;
      lcd_done_q <= lcd_done_d;
      lcd_go_q <= lcd_go_d;
      lcd_ready_q <= lcd_ready_d;
      pipe_done_q <= pipe_done_d;
      frame_cycle_q <= frame_cycle_d;
      lframe_cycle_q <= lframe_cycle_d;
end

endmodule