data/full_repos/permissive/116266634/mips_testbench.v
 line:13: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/116266634/mips_testbench.v:10: Unsupported: Ignoring delay on this delayed statement.\n #50 clock=~clock;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116266634/mips_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n #3200 $finish;\n ^\n%Error: data/full_repos/permissive/116266634/mips_testbench.v:19: Unsupported or unknown PLI call: $writememb\n $writememb("res_registers.mem", test.registers.registers);\n ^~~~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_testbench ();
reg clock;
wire result;

mips_core test(clock);

initial clock = 0;

always
	#50 clock=~clock;

initial begin
	#3200 $finish;

end


always @ (*) begin
	$writememb("res_registers.mem", test.registers.registers);
end

endmodule
module mips_testbench ();

reg clock;
wire result;

mips_core test(clock);

initial clock = 0;

always
	#50 clock=~clock;

initial begin
	#3200 $finish;

end


always @ (*) begin
	$writememb("res_registers.mem", test.registers.registers);
end

endmodule