data/full_repos/permissive/172538466/hw/src/ahb_gpio.v
None: at end of input
1: b'%Error: data/full_repos/permissive/172538466/hw/src/ahb_gpio.v:1: Cannot find include file: defs.vh\n`include "defs.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh.v\n             data/full_repos/permissive/172538466/hw/src,data/full_repos/permissive/172538466/defs.vh.sv\n             defs.vh\n             defs.vh.v\n             defs.vh.sv\n             obj_dir/defs.vh\n             obj_dir/defs.vh.v\n             obj_dir/defs.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module ahb_gpio
(
 input             HCLK_I,
 input             HRESET_N_I,

 input [7:0]       PORT_I,
 output [7:0]      PORT_O,
 output [7:0]      DIR_O,

 input             HREADY_I,
 input             HSEL_I,
 input [2:0]       HSIZE_I,
 input             HWRITE_I,
 input [11:0]      HADDR_I,
 input [31:0]      HRDATA_I,
 output reg [31:0] HWDATA_O,
 output            HRESP_O,
 output            HREADY_O
 );

   localparam REG_DATA = 1'b0;
   localparam REG_DIR =  1'b1;

   assign PORT_O = data;
   assign DIR_O = dir;



   assign HRESP_O = 0;
   assign HREADY_O = enable_d;
   wire        enable = HSEL_I;



   wire [0:0]  adr = HADDR_I[2:2];
   reg [0:0]   adr_d;
   reg         enable_d;
   reg         write_d;

   always @(posedge HCLK_I) begin
     adr_d <= adr;
     write_d <= HWRITE_I;
   end

   always @(posedge HCLK_I)
     if(!HRESET_N_I)
       enable_d <= 0;
     else
       enable_d <= enable;


   reg [7:0]       dir;
   reg [7:0]       data;
   always @(posedge HCLK_I) begin
     if(!HRESET_N_I) begin
       dir <= 8'd0;
     end else begin


       if (enable_d & write_d) begin
         case(adr_d)
           REG_DATA: data <= HRDATA_I[7:0];
           REG_DIR: dir <= HRDATA_I[7:0];
         endcase
       end
     end
   end


   always @(posedge HCLK_I)
     if(enable & !HWRITE_I) begin
       case(adr)
         REG_DATA: HWDATA_O <= { 24'd0,  (PORT_I & ~dir) | (data & dir)};
         REG_DIR: HWDATA_O <= { 24'd0, dir };
         default: HWDATA_O <= 32'dx;
       endcase
     end
endmodule
module ahb_gpio
(
 input             HCLK_I,
 input             HRESET_N_I,

 input [7:0]       PORT_I,
 output [7:0]      PORT_O,
 output [7:0]      DIR_O,

 input             HREADY_I,
 input             HSEL_I,
 input [2:0]       HSIZE_I,
 input             HWRITE_I,
 input [11:0]      HADDR_I,
 input [31:0]      HRDATA_I,
 output reg [31:0] HWDATA_O,
 output            HRESP_O,
 output            HREADY_O
 );


   localparam REG_DATA = 1'b0;
   localparam REG_DIR =  1'b1;

   assign PORT_O = data;
   assign DIR_O = dir;



   assign HRESP_O = 0;
   assign HREADY_O = enable_d;
   wire        enable = HSEL_I;



   wire [0:0]  adr = HADDR_I[2:2];
   reg [0:0]   adr_d;
   reg         enable_d;
   reg         write_d;

   always @(posedge HCLK_I) begin
     adr_d <= adr;
     write_d <= HWRITE_I;
   end

   always @(posedge HCLK_I)
     if(!HRESET_N_I)
       enable_d <= 0;
     else
       enable_d <= enable;


   reg [7:0]       dir;
   reg [7:0]       data;
   always @(posedge HCLK_I) begin
     if(!HRESET_N_I) begin
       dir <= 8'd0;
     end else begin


       if (enable_d & write_d) begin
         case(adr_d)
           REG_DATA: data <= HRDATA_I[7:0];
           REG_DIR: dir <= HRDATA_I[7:0];
         endcase
       end
     end
   end


   always @(posedge HCLK_I)
     if(enable & !HWRITE_I) begin
       case(adr)
         REG_DATA: HWDATA_O <= { 24'd0,  (PORT_I & ~dir) | (data & dir)};
         REG_DIR: HWDATA_O <= { 24'd0, dir };
         default: HWDATA_O <= 32'dx;
       endcase
     end
endmodule