data/full_repos/permissive/19435930/toplevel_test.v
 line:123: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #3000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #1852;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #1852;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #1852;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:88: Unsupported: Ignoring delay on this delayed statement.\n   #37.04;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:91: Unsupported: Ignoring delay on this delayed statement.\n   #37.04;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:95: Unsupported: Ignoring delay on this delayed statement.\n   #37.04;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:98: Unsupported: Ignoring delay on this delayed statement.\n   #37.04;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:100: Unsupported: Ignoring delay on this delayed statement.\n   #37.04;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:104: Unsupported: Ignoring delay on this delayed statement.\n   #37.04;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:107: Unsupported: Ignoring delay on this delayed statement.\n   #37.04;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:109: Unsupported: Ignoring delay on this delayed statement.\n   #37.04;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:113: Unsupported: Ignoring delay on this delayed statement.\n   #37.04;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:116: Unsupported: Ignoring delay on this delayed statement.\n   #37.04;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:120: Unsupported: Ignoring delay on this delayed statement.\nalways #18.52 CLK <= ~CLK;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:121: Unsupported: Ignoring delay on this delayed statement.\nalways #18.52 PIXCLK <= ~PIXCLK;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/toplevel_test.v:123: Unsupported: Ignoring delay on this delayed statement.\ninitial #100000 $finish;      \n        ^\n%Error: data/full_repos/permissive/19435930/toplevel_test.v:21: Cannot find file containing module: \'topmodule\'\n topmodule #(2,3) uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19435930,data/full_repos/permissive/19435930/topmodule\n             data/full_repos/permissive/19435930,data/full_repos/permissive/19435930/topmodule.v\n             data/full_repos/permissive/19435930,data/full_repos/permissive/19435930/topmodule.sv\n             topmodule\n             topmodule.v\n             topmodule.sv\n             obj_dir/topmodule\n             obj_dir/topmodule.v\n             obj_dir/topmodule.sv\n%Error: data/full_repos/permissive/19435930/toplevel_test.v:35: Cannot find file containing module: \'uart_receive\'\n uart_receive uut1 (\n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 28 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module toplevel_test;



	reg RST = 1;
	reg CLK = 0;
	reg RXD = 1;

	reg PIXCLK = 1;
	reg FRAME_VALID = 0;
	reg LINE_VALID = 0;
	reg [9:0] DATA_IN = 0;


	wire TXD;
	wire CAM_SYSCLK = CLK;


	topmodule #(2,3) uut (
		.RST(RST), 
		.CLK(CLK), 
		.UART_RXD(RXD), 
		.UART_TXD(TXD),
		.CAM_PIXCLK(PIXCLK),
		.CAM_FRAME_VALID(FRAME_VALID),
		.CAM_LINE_VALID(LINE_VALID),
		.CAM_DATA(DATA_IN)
	);

	wire [7:0] DECODED;
	wire DECODED_READY;

	uart_receive uut1 (
		.RST(RST),
		.CLK(CLK),
		.RXD(TXD),
		.DATA(DECODED),
		.RXD_READY(DECODED_READY)
	);


	initial begin
	

		#1000;
		RST = 0;
		#3000;
		

		RXD = 0;
		#1000;
		RXD = 0;
		#1000;
		RXD = 1;
		#1000;
		RXD = 0;
		#1000;
		RXD = 1;
		#1000;
		RXD = 0;
		#1000;
		RXD = 1;
		#1000;
		RXD = 0;
		#1000;
		RXD = 1;
		#1000;
		RXD = 1;
		#1000;
		
	end
	
	initial begin

		LINE_VALID = 1;
		FRAME_VALID = 1;
		DATA_IN = 0;

		#1852;
		#1852;
		#1852;
		forever
		begin
			LINE_VALID = 0;
			FRAME_VALID = 0;
			#37.04;
			
			FRAME_VALID = 1;
			#37.04;
			
			LINE_VALID = 1;
			DATA_IN = 11<<2;
			#37.04;
			LINE_VALID = 1;
			DATA_IN = 12<<2;
			#37.04;
			LINE_VALID = 0;
			#37.04;
			
			LINE_VALID = 1;
			DATA_IN = 21<<2;
			#37.04;
			LINE_VALID = 1;
			DATA_IN = 22<<2;
			#37.04;
			LINE_VALID = 0;
			#37.04;
			
			LINE_VALID = 1;
			DATA_IN = 31<<2;
			#37.04;
			LINE_VALID = 1;
			DATA_IN = 32<<2;
			#37.04;
		end
	end
	
always #18.52 CLK <= ~CLK;
always #18.52 PIXCLK <= ~PIXCLK;
	
initial #100000 $finish;      
	
endmodule
module toplevel_test;




	reg RST = 1;
	reg CLK = 0;
	reg RXD = 1;

	reg PIXCLK = 1;
	reg FRAME_VALID = 0;
	reg LINE_VALID = 0;
	reg [9:0] DATA_IN = 0;


	wire TXD;
	wire CAM_SYSCLK = CLK;


	topmodule #(2,3) uut (
		.RST(RST), 
		.CLK(CLK), 
		.UART_RXD(RXD), 
		.UART_TXD(TXD),
		.CAM_PIXCLK(PIXCLK),
		.CAM_FRAME_VALID(FRAME_VALID),
		.CAM_LINE_VALID(LINE_VALID),
		.CAM_DATA(DATA_IN)
	);

	wire [7:0] DECODED;
	wire DECODED_READY;

	uart_receive uut1 (
		.RST(RST),
		.CLK(CLK),
		.RXD(TXD),
		.DATA(DECODED),
		.RXD_READY(DECODED_READY)
	);


	initial begin
	

		#1000;
		RST = 0;
		#3000;
		

		RXD = 0;
		#1000;
		RXD = 0;
		#1000;
		RXD = 1;
		#1000;
		RXD = 0;
		#1000;
		RXD = 1;
		#1000;
		RXD = 0;
		#1000;
		RXD = 1;
		#1000;
		RXD = 0;
		#1000;
		RXD = 1;
		#1000;
		RXD = 1;
		#1000;
		
	end
	
	initial begin

		LINE_VALID = 1;
		FRAME_VALID = 1;
		DATA_IN = 0;

		#1852;
		#1852;
		#1852;
		forever
		begin
			LINE_VALID = 0;
			FRAME_VALID = 0;
			#37.04;
			
			FRAME_VALID = 1;
			#37.04;
			
			LINE_VALID = 1;
			DATA_IN = 11<<2;
			#37.04;
			LINE_VALID = 1;
			DATA_IN = 12<<2;
			#37.04;
			LINE_VALID = 0;
			#37.04;
			
			LINE_VALID = 1;
			DATA_IN = 21<<2;
			#37.04;
			LINE_VALID = 1;
			DATA_IN = 22<<2;
			#37.04;
			LINE_VALID = 0;
			#37.04;
			
			LINE_VALID = 1;
			DATA_IN = 31<<2;
			#37.04;
			LINE_VALID = 1;
			DATA_IN = 32<<2;
			#37.04;
		end
	end
	
always #18.52 CLK <= ~CLK;
always #18.52 PIXCLK <= ~PIXCLK;
	
initial #100000 $finish;      
	
endmodule