data/full_repos/permissive/198139336/DDLab5_forStudent/testbench_cont_8bit_adder.v
 line:29: before: "begin"
1: b'%Error: data/full_repos/permissive/198139336/DDLab5_forStudent/testbench_cont_8bit_adder.v:14: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("cont_8bit_adder.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/198139336/DDLab5_forStudent/testbench_cont_8bit_adder.v:15: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/198139336/DDLab5_forStudent/testbench_cont_8bit_adder.v:32: Unsupported or unknown PLI call: $monitor\n    $monitor("%4dns monitor: a=%d b=%d cin=%d sum=%d cout=%d", $stime, a, b, cin, sum, cout);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab5_forStudent/testbench_cont_8bit_adder.v:28: Unsupported: Ignoring delay on this delayed statement.\nalways #1\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab5_forStudent/testbench_cont_8bit_adder.v:35: Unsupported: Ignoring delay on this delayed statement.\nalways #2 b = b >>2; \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab5_forStudent/testbench_cont_8bit_adder.v:36: Unsupported: Ignoring delay on this delayed statement.\nalways #3 cin = ~cin; \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/DDLab5_forStudent/testbench_cont_8bit_adder.v:37: Unsupported: Ignoring delay on this delayed statement.\ninitial #15 $finish; \n        ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench_cont_8bit_adder;

reg [7:0] a, b;
reg cin;
wire [7:0] sum;
wire cout;

cont_8bit_adder DUT(sum, cout, a, b, cin);


initial begin
    $dumpfile("cont_8bit_adder.vcd");
    $dumpvars;
end

initial
begin
    a = 8'b11110000;
    b = 8'b11111111;
    cin = 1'b1;



end

always #1
begin
    a = ( a<<1 | cin );

    $monitor("%4dns monitor: a=%d b=%d cin=%d sum=%d cout=%d", $stime, a, b, cin, sum, cout);
end

always #2 b = b >>2;
always #3 cin = ~cin;
initial #15 $finish;
endmodule
module testbench_cont_8bit_adder;


reg [7:0] a, b;
reg cin;
wire [7:0] sum;
wire cout;

cont_8bit_adder DUT(sum, cout, a, b, cin);


initial begin
    $dumpfile("cont_8bit_adder.vcd");
    $dumpvars;
end

initial
begin
    a = 8'b11110000;
    b = 8'b11111111;
    cin = 1'b1;



end

always #1
begin
    a = ( a<<1 | cin );

    $monitor("%4dns monitor: a=%d b=%d cin=%d sum=%d cout=%d", $stime, a, b, cin, sum, cout);
end

always #2 b = b >>2;
always #3 cin = ~cin;
initial #15 $finish;
endmodule