data/full_repos/permissive/211235278/09. Simple DMA CPU/DMA.v
1: b'%Error: Cannot find file containing module: Simple\n        ... Looked in:\n             data/full_repos/permissive/211235278/09./Simple\n             data/full_repos/permissive/211235278/09./Simple.v\n             data/full_repos/permissive/211235278/09./Simple.sv\n             Simple\n             Simple.v\n             Simple.sv\n             obj_dir/Simple\n             obj_dir/Simple.v\n             obj_dir/Simple.sv\n%Error: Cannot find file containing module: DMA\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/211235278\n%Error: Cannot find file containing module: data/full_repos/permissive/211235278/09.\n%Error: Cannot find file containing module: CPU/DMA.v\n%Error: Exiting due to 5 error(s)\n'
module DMA (
    input CLK, BG,
    input [4 * `WORD_SIZE - 1 : 0] edata,
    input cmd,
    output reg BR, WR,
    output reg [`WORD_SIZE - 3 : 0] addr,
    output reg [4 * `WORD_SIZE - 1 : 0] data,
    output [1:0] offset,
    output reg interrupt);

    reg [1:0] block;
    reg [2:0] counter;
    
    assign offset = BG ? block : 2'bz;
    
    always @(posedge CLK) begin

        if (cmd && !interrupt) BR <= 1;
        else BR <= 0;
        

        if (BG && !interrupt) begin
            addr <= 14'h7d + block;
            data <= edata;
            if (counter == 0) begin
                counter <= `LATENCY;
                WR <= 1;
            end else begin
                counter <= counter - 1;
            end
        end else begin
            addr <= 14'bz;
            data <= 64'bz;
            WR <= 1'bz;
            interrupt <= 0;
            block <= 0;
            counter <= 0;
        end
    end
    

    always @(negedge CLK) begin
        if (BG && !interrupt && counter==1) begin
            counter <= 0;
            if (block == 2) begin
                block <= 0;
                interrupt <= 1;
                BR <= 0;
                WR <= 0;
            end else begin
                block <= block + 1;
            end
        end
    end

endmodule
module DMA (
    input CLK, BG,
    input [4 * `WORD_SIZE - 1 : 0] edata,
    input cmd,
    output reg BR, WR,
    output reg [`WORD_SIZE - 3 : 0] addr,
    output reg [4 * `WORD_SIZE - 1 : 0] data,
    output [1:0] offset,
    output reg interrupt);


    reg [1:0] block;
    reg [2:0] counter;
    
    assign offset = BG ? block : 2'bz;
    
    always @(posedge CLK) begin

        if (cmd && !interrupt) BR <= 1;
        else BR <= 0;
        

        if (BG && !interrupt) begin
            addr <= 14'h7d + block;
            data <= edata;
            if (counter == 0) begin
                counter <= `LATENCY;
                WR <= 1;
            end else begin
                counter <= counter - 1;
            end
        end else begin
            addr <= 14'bz;
            data <= 64'bz;
            WR <= 1'bz;
            interrupt <= 0;
            block <= 0;
            counter <= 0;
        end
    end
    

    always @(negedge CLK) begin
        if (BG && !interrupt && counter==1) begin
            counter <= 0;
            if (block == 2) begin
                block <= 0;
                interrupt <= 1;
                BR <= 0;
                WR <= 0;
            end else begin
                block <= block + 1;
            end
        end
    end

endmodule