data/full_repos/permissive/131249673/MIPS_L_PipeLine/Brancher.v
1: b'%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Brancher.v:1: Cannot find include file: ctrl_encode_def.v\n`include "ctrl_encode_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/ctrl_encode_def.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/ctrl_encode_def.v.v\n             data/full_repos/permissive/131249673/MIPS_L_PipeLine,data/full_repos/permissive/131249673/ctrl_encode_def.v.sv\n             ctrl_encode_def.v\n             ctrl_encode_def.v.v\n             ctrl_encode_def.v.sv\n             obj_dir/ctrl_encode_def.v\n             obj_dir/ctrl_encode_def.v.v\n             obj_dir/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Brancher.v:2: Cannot find include file: instruction_def.v\n`include "instruction_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Brancher.v:57: Define or directive not defined: \'`INSTR_BEQ_OP\'\n if ( Op == `INSTR_BEQ_OP && Zero)\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Brancher.v:57: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if ( Op == `INSTR_BEQ_OP && Zero)\n                          ^~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Brancher.v:59: Define or directive not defined: \'`INSTR_BNE_OP\'\n if ( Op == `INSTR_BNE_OP && !Zero)\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_PipeLine/Brancher.v:59: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if ( Op == `INSTR_BNE_OP && !Zero)\n                          ^~\n%Error: Exiting due to 6 error(s)\n'
module brancher(Op, rs, rt, Imm,
	brSignal,
	WriteDst_EX, WriteDst_MEM,
	RD1, RD2, ALUOut_C, dm_dout,
	EX_ctrl_RegWr, MEM_ctrl_RegWr
	);

	input	[15:0]	Imm;
	input	[4:0]	rs;
	input	[4:0]	rt;
	input	[5:0]	Op;

	input	[4:0]	WriteDst_EX;
	input	[4:0]	WriteDst_MEM;
	
	input			EX_ctrl_RegWr;
	input			MEM_ctrl_RegWr;

	input	[31:0]	RD1;
	input	[31:0]	RD2;
	input	[31:0]	ALUOut_C;
	input	[31:0]	dm_dout;
	
	output	brSignal;
	
	reg		brSignal;
	reg		Zero;
	reg  [31:0]  R1;
	reg  [31:0]  R2;
	
	wire		[31:0]	RD1;
	wire		[31:0]	RD2;

	initial
	begin
	end

	always @(*) begin	  
	Zero = 0;
	brSignal = 0;

	  R1 = RD1;
	  R2 = RD2;
	if (EX_ctrl_RegWr && (rs == WriteDst_EX))
		R1 = ALUOut_C;
	if (EX_ctrl_RegWr && (rt == WriteDst_EX))
		R2 = ALUOut_C;
	if (MEM_ctrl_RegWr && (rs == WriteDst_MEM))
		R1 = dm_dout;
	if (MEM_ctrl_RegWr && (rt == WriteDst_MEM))
		R2 = dm_dout;

	if (R1 == R2)
		Zero = 1;
	if ( Op == `INSTR_BEQ_OP && Zero)
		brSignal = 1;
	if ( Op == `INSTR_BNE_OP && !Zero)
		brSignal = 1;

	end
endmodule
module brancher(Op, rs, rt, Imm,
	brSignal,
	WriteDst_EX, WriteDst_MEM,
	RD1, RD2, ALUOut_C, dm_dout,
	EX_ctrl_RegWr, MEM_ctrl_RegWr
	);


	input	[15:0]	Imm;
	input	[4:0]	rs;
	input	[4:0]	rt;
	input	[5:0]	Op;

	input	[4:0]	WriteDst_EX;
	input	[4:0]	WriteDst_MEM;
	
	input			EX_ctrl_RegWr;
	input			MEM_ctrl_RegWr;

	input	[31:0]	RD1;
	input	[31:0]	RD2;
	input	[31:0]	ALUOut_C;
	input	[31:0]	dm_dout;
	
	output	brSignal;
	
	reg		brSignal;
	reg		Zero;
	reg  [31:0]  R1;
	reg  [31:0]  R2;
	
	wire		[31:0]	RD1;
	wire		[31:0]	RD2;

	initial
	begin
	end

	always @(*) begin	  
	Zero = 0;
	brSignal = 0;

	  R1 = RD1;
	  R2 = RD2;
	if (EX_ctrl_RegWr && (rs == WriteDst_EX))
		R1 = ALUOut_C;
	if (EX_ctrl_RegWr && (rt == WriteDst_EX))
		R2 = ALUOut_C;
	if (MEM_ctrl_RegWr && (rs == WriteDst_MEM))
		R1 = dm_dout;
	if (MEM_ctrl_RegWr && (rt == WriteDst_MEM))
		R2 = dm_dout;

	if (R1 == R2)
		Zero = 1;
	if ( Op == `INSTR_BEQ_OP && Zero)
		brSignal = 1;
	if ( Op == `INSTR_BNE_OP && !Zero)
		brSignal = 1;

	end
endmodule