data/full_repos/permissive/143278/ivltests/signed2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/signed2.v:32: Operator NEGATE expects 32 bits on the LHS, but LHS\'s CONST \'4\'hc\' generates 4 bits.\n                                                                       : ... In instance test\n    I0 = -4\'d12;\n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module test;

integer I0,I1;
reg [15:0] R0,R1;
reg [3:0] error;

initial
  begin
    error = 0;
    I0 = -4'd12;
    I1 = -32'd12;
    if(I0 !== 32'hfffffff4)
      begin
        $display("FAILED - negative decimal assignment failed. I0 s/b fffffff4, is %h",
                I0);
        error =1;
      end
    if(I1 !== 32'hfffffff4)
      begin
         $display("FAILED - negative decimal assignment failed. I1 s/b fffffff4, is %h",
                I1);
        error = 1;
      end
    if(error === 0)
      $display("PASSED");
  end

endmodule
module test;


integer I0,I1;
reg [15:0] R0,R1;
reg [3:0] error;

initial
  begin
    error = 0;
    I0 = -4'd12;
    I1 = -32'd12;
    if(I0 !== 32'hfffffff4)
      begin
        $display("FAILED - negative decimal assignment failed. I0 s/b fffffff4, is %h",
                I0);
        error =1;
      end
    if(I1 !== 32'hfffffff4)
      begin
         $display("FAILED - negative decimal assignment failed. I1 s/b fffffff4, is %h",
                I1);
        error = 1;
      end
    if(error === 0)
      $display("PASSED");
  end

endmodule