data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v
 line:80: before: "("
1: b'%Warning-MULTITOP: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v:73: Multiple top level modules\n                                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                   : ... Top module \'dsp_t1_20x18x64_cfg_ports\'\nmodule dsp_t1_20x18x64_cfg_ports (\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                   : ... Top module \'dsp_t1_10x9x32_cfg_ports\'\nmodule dsp_t1_10x9x32_cfg_ports (\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                   : ... Top module \'dsp_t1_20x18x64_cfg_params\'\nmodule dsp_t1_20x18x64_cfg_params (\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                   : ... Top module \'dsp_t1_10x9x32_cfg_params\'\nmodule dsp_t1_10x9x32_cfg_params (\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v:231: Cannot find file containing module: \'QL_DSP3\'\n    QL_DSP3 # (\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f,data/full_repos/permissive/220229160/QL_DSP3\n             data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f,data/full_repos/permissive/220229160/QL_DSP3.v\n             data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f,data/full_repos/permissive/220229160/QL_DSP3.sv\n             QL_DSP3\n             QL_DSP3.v\n             QL_DSP3.sv\n             obj_dir/QL_DSP3\n             obj_dir/QL_DSP3.v\n             obj_dir/QL_DSP3.sv\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v:167: Cannot find file containing module: \'QL_DSP3\'\n    QL_DSP3 # (\n    ^~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v:105: Cannot find file containing module: \'QL_DSP2\'\n    QL_DSP2 # (\n    ^~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v:45: Cannot find file containing module: \'QL_DSP2\'\n    QL_DSP2 # (\n    ^~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module dsp_t1_10x9x32_cfg_params (
    input  [ 9:0] a_i,
    input  [ 8:0] b_i,
    input  [ 5:0] acc_fir_i,
    output [18:0] z_o,
    output [ 8:0] dly_b_o,

    (* clkbuf_sink *)
    input         clock_i,
    input         reset_i,

    input  [2:0]  feedback_i,
    input         load_acc_i,
    input         unsigned_a_i,
    input         unsigned_b_i,
    input         subtract_i
);

    parameter [9:0] COEFF_0 = 10'd0;
    parameter [9:0] COEFF_1 = 10'd0;
    parameter [9:0] COEFF_2 = 10'd0;
    parameter [9:0] COEFF_3 = 10'd0;

    parameter [2:0] OUTPUT_SELECT   = 3'd0;
    parameter [0:0] SATURATE_ENABLE = 1'd0;
    parameter [5:0] SHIFT_RIGHT     = 6'd0;
    parameter [0:0] ROUND           = 1'd0;
    parameter [0:0] REGISTER_INPUTS = 1'd0;

    wire [37:0] z;
    wire [17:0] dly_b;

    QL_DSP3 # (
        .MODE_BITS  ({
            REGISTER_INPUTS,
            ROUND,
            SHIFT_RIGHT,
            SATURATE_ENABLE,
            OUTPUT_SELECT,
            1'b1,
            10'd0, COEFF_3,
            10'd0, COEFF_2,
            10'd0, COEFF_1,
            10'd0, COEFF_0
        })
    ) _TECHMAP_REPLACE_ (
        .a                  ({10'd0, a_i}),
        .b                  ({ 9'd0, b_i}),
        .acc_fir            (acc_fir_i),
        .z                  (z),
        .dly_b              (dly_b),

        .clk                (clock_i),
        .reset              (reset_i),

        .feedback           (feedback_i),
        .load_acc           (load_acc_i),
        .unsigned_a         (unsigned_a_i),
        .unsigned_b         (unsigned_b_i),
        .subtract           (subtract_i)
    );

    assign z_o = z[18:0];
    assign dly_b_o = dly_b_o[8:0];

endmodule
module dsp_t1_10x9x32_cfg_params (
    input  [ 9:0] a_i,
    input  [ 8:0] b_i,
    input  [ 5:0] acc_fir_i,
    output [18:0] z_o,
    output [ 8:0] dly_b_o,

    (* clkbuf_sink *)
    input         clock_i,
    input         reset_i,

    input  [2:0]  feedback_i,
    input         load_acc_i,
    input         unsigned_a_i,
    input         unsigned_b_i,
    input         subtract_i
);


    parameter [9:0] COEFF_0 = 10'd0;
    parameter [9:0] COEFF_1 = 10'd0;
    parameter [9:0] COEFF_2 = 10'd0;
    parameter [9:0] COEFF_3 = 10'd0;

    parameter [2:0] OUTPUT_SELECT   = 3'd0;
    parameter [0:0] SATURATE_ENABLE = 1'd0;
    parameter [5:0] SHIFT_RIGHT     = 6'd0;
    parameter [0:0] ROUND           = 1'd0;
    parameter [0:0] REGISTER_INPUTS = 1'd0;

    wire [37:0] z;
    wire [17:0] dly_b;

    QL_DSP3 # (
        .MODE_BITS  ({
            REGISTER_INPUTS,
            ROUND,
            SHIFT_RIGHT,
            SATURATE_ENABLE,
            OUTPUT_SELECT,
            1'b1,
            10'd0, COEFF_3,
            10'd0, COEFF_2,
            10'd0, COEFF_1,
            10'd0, COEFF_0
        })
    ) _TECHMAP_REPLACE_ (
        .a                  ({10'd0, a_i}),
        .b                  ({ 9'd0, b_i}),
        .acc_fir            (acc_fir_i),
        .z                  (z),
        .dly_b              (dly_b),

        .clk                (clock_i),
        .reset              (reset_i),

        .feedback           (feedback_i),
        .load_acc           (load_acc_i),
        .unsigned_a         (unsigned_a_i),
        .unsigned_b         (unsigned_b_i),
        .subtract           (subtract_i)
    );

    assign z_o = z[18:0];
    assign dly_b_o = dly_b_o[8:0];

endmodule