data/full_repos/permissive/196851857/datapath/alu.v
None: at end of input
1: b'%Error: data/full_repos/permissive/196851857/datapath/alu.v:1: Cannot find include file: ..\\\\control\\\\ctrl_signals_def.v\n`include "..\\\\control\\\\ctrl_signals_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/196851857/datapath,data/full_repos/permissive/196851857/..\\\\control\\\\ctrl_signals_def.v\n             data/full_repos/permissive/196851857/datapath,data/full_repos/permissive/196851857/..\\\\control\\\\ctrl_signals_def.v.v\n             data/full_repos/permissive/196851857/datapath,data/full_repos/permissive/196851857/..\\\\control\\\\ctrl_signals_def.v.sv\n             ..\\\\control\\\\ctrl_signals_def.v\n             ..\\\\control\\\\ctrl_signals_def.v.v\n             ..\\\\control\\\\ctrl_signals_def.v.sv\n             obj_dir/..\\\\control\\\\ctrl_signals_def.v\n             obj_dir/..\\\\control\\\\ctrl_signals_def.v.v\n             obj_dir/..\\\\control\\\\ctrl_signals_def.v.sv\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:18: Define or directive not defined: \'`alu_addu\'\n      `alu_addu: result <= A + B;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:18: syntax error, unexpected \':\', expecting endcase\n      `alu_addu: result <= A + B;\n               ^\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:19: Define or directive not defined: \'`alu_subu\'\n      `alu_subu: result <= (A - B);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:20: Define or directive not defined: \'`alu_slt\'\n      `alu_slt:  result <= ($signed(A) < $signed(B));\n      ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:21: Define or directive not defined: \'`alu_and\'\n      `alu_and:  result <= (A & B);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:22: Define or directive not defined: \'`alu_nor\'\n      `alu_nor:  result <= (~(A | B));\n      ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:23: Define or directive not defined: \'`alu_or\'\n      `alu_or:   result <= (A | B);\n      ^~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:24: Define or directive not defined: \'`alu_xor\'\n      `alu_xor:  result <= (A ^ B);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:25: Define or directive not defined: \'`alu_sltu\'\n      `alu_sltu: result <=  (A < B);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:26: Define or directive not defined: \'`alu_sllv\'\n      `alu_sllv: result <= (B << A);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:27: Define or directive not defined: \'`alu_srav\'\n      `alu_srav: result <= (($signed(B)) >>> A);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:28: Define or directive not defined: \'`alu_srlv\'\n      `alu_srlv: result <= (B >> A);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:29: Define or directive not defined: \'`alu_sll\'\n      `alu_sll:  result <= (B << shamt);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:30: Define or directive not defined: \'`alu_srl\'\n      `alu_srl:  result <= (B >> shamt);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:31: Define or directive not defined: \'`alu_sra\'\n      `alu_sra:  result <= (($signed(B)) >>> shamt);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:32: Define or directive not defined: \'`alu_lui\'\n      `alu_lui:  result <= B;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:33: Define or directive not defined: \'`alu_nop\'\n      `alu_nop:  result <= 32\'h0000_0000;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/alu.v:40: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module alu (
  A, B, ALUctr, result,
  zero, pos, neg,
  shamt
);
  parameter WIDTH = 32;
  
  input [4:0] ALUctr;
  input [WIDTH-1:0] A, B;
  input [4:0] shamt;
  output reg [WIDTH-1:0] result;
  output zero, pos, neg;
  
  always@(A or B or ALUctr or shamt)
  begin
    case(ALUctr)
      `alu_addu: result <= A + B;
      `alu_subu: result <= (A - B);
      `alu_slt:  result <= ($signed(A) < $signed(B));
      `alu_and:  result <= (A & B);
      `alu_nor:  result <= (~(A | B));
      `alu_or:   result <= (A | B);
      `alu_xor:  result <= (A ^ B);
      `alu_sltu: result <=  (A < B);
      `alu_sllv: result <= (B << A);
      `alu_srav: result <= (($signed(B)) >>> A);
      `alu_srlv: result <= (B >> A);
      `alu_sll:  result <= (B << shamt);
      `alu_srl:  result <= (B >> shamt);
      `alu_sra:  result <= (($signed(B)) >>> shamt);
      `alu_lui:  result <= B;
      `alu_nop:  result <= 32'h0000_0000;
      default:   result <= 32'h0000_0000;
    endcase
  end
  assign zero = (result == 0);
  assign pos = ($signed(result) > 0);
  assign neg = ($signed(result) < 0);
endmodule
module alu (
  A, B, ALUctr, result,
  zero, pos, neg,
  shamt
);

  parameter WIDTH = 32;
  
  input [4:0] ALUctr;
  input [WIDTH-1:0] A, B;
  input [4:0] shamt;
  output reg [WIDTH-1:0] result;
  output zero, pos, neg;
  
  always@(A or B or ALUctr or shamt)
  begin
    case(ALUctr)
      `alu_addu: result <= A + B;
      `alu_subu: result <= (A - B);
      `alu_slt:  result <= ($signed(A) < $signed(B));
      `alu_and:  result <= (A & B);
      `alu_nor:  result <= (~(A | B));
      `alu_or:   result <= (A | B);
      `alu_xor:  result <= (A ^ B);
      `alu_sltu: result <=  (A < B);
      `alu_sllv: result <= (B << A);
      `alu_srav: result <= (($signed(B)) >>> A);
      `alu_srlv: result <= (B >> A);
      `alu_sll:  result <= (B << shamt);
      `alu_srl:  result <= (B >> shamt);
      `alu_sra:  result <= (($signed(B)) >>> shamt);
      `alu_lui:  result <= B;
      `alu_nop:  result <= 32'h0000_0000;
      default:   result <= 32'h0000_0000;
    endcase
  end
  assign zero = (result == 0);
  assign pos = ($signed(result) > 0);
  assign neg = ($signed(result) < 0);
endmodule