data/full_repos/permissive/160024456/day03/part2.v
1: b'%Error: data/full_repos/permissive/160024456/day03/part2.v:25: Cannot find file containing module: \'plain_counter\'\nplain_counter #(.WIDTH(11), .VAL(1237)) plain_counter1 (.clk(clk), .en(ready), .inc(1\'b1), .v(counter1), .r(counter1_overflow));\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160024456/day03,data/full_repos/permissive/160024456/plain_counter\n             data/full_repos/permissive/160024456/day03,data/full_repos/permissive/160024456/plain_counter.v\n             data/full_repos/permissive/160024456/day03,data/full_repos/permissive/160024456/plain_counter.sv\n             plain_counter\n             plain_counter.v\n             plain_counter.sv\n             obj_dir/plain_counter\n             obj_dir/plain_counter.v\n             obj_dir/plain_counter.sv\n%Error: data/full_repos/permissive/160024456/day03/part2.v:26: Cannot find file containing module: \'plain_counter\'\nplain_counter #(.WIDTH(11), .VAL(1237)) plain_counter2 (.clk(clk), .en(ready), .inc(counter1_overflow), .v(counter2), .r(counter2_overflow));\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160024456/day03/part2.v:28: Cannot find file containing module: \'rom\'\nrom rom1 (.clk(clk), .addr(counter1), .left(left1), .top(top1), .w(w1), .h(h1));\n^~~\n%Error: data/full_repos/permissive/160024456/day03/part2.v:29: Cannot find file containing module: \'rom\'\nrom rom2 (.clk(clk), .addr(counter2), .left(left2), .top(top2), .w(w2), .h(h2));\n^~~\n%Error: data/full_repos/permissive/160024456/day03/part2.v:32: Cannot find file containing module: \'data_exporter\'\ndata_exporter data_exporter1 (.clk(clk), .en(ready), .data({17\'b0, solution}), .leds(leds));\n^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/160024456/day03/part2.v:35: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'w1\' generates 5 bits.\n                                                                     : ... In instance part2\nassign right1 = left1 + w1;\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/160024456/day03/part2.v:36: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'h1\' generates 5 bits.\n                                                                     : ... In instance part2\nassign bottom1 = top1 + h1;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/160024456/day03/part2.v:37: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'w2\' generates 5 bits.\n                                                                     : ... In instance part2\nassign right2 = left2 + w2;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/160024456/day03/part2.v:38: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'h2\' generates 5 bits.\n                                                                     : ... In instance part2\nassign bottom2 = top2 + h2;\n                      ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module part2 (
  input wire clk,
  output reg LED1,
  output reg LED5,
  output wire PMOD1,
  output wire PMOD2,
  output wire PMOD3,
  output wire PMOD4,
  output wire PMOD7,
  output wire PMOD8,
  output wire PMOD9,
  output wire PMOD10
);

reg ready = 0;
reg [10:0] solution;

wire [10:0] counter1, counter2;
wire [9:0] left1, left2, top1, top2, right1, right2, bottom1, bottom2;
wire [4:0] w1, w2, h1, h2;
wire counter1_overflow, counter2_overflow;
reg overlap1;
reg done;

plain_counter #(.WIDTH(11), .VAL(1237)) plain_counter1 (.clk(clk), .en(ready), .inc(1'b1), .v(counter1), .r(counter1_overflow));
plain_counter #(.WIDTH(11), .VAL(1237)) plain_counter2 (.clk(clk), .en(ready), .inc(counter1_overflow), .v(counter2), .r(counter2_overflow));

rom rom1 (.clk(clk), .addr(counter1), .left(left1), .top(top1), .w(w1), .h(h1));
rom rom2 (.clk(clk), .addr(counter2), .left(left2), .top(top2), .w(w2), .h(h2));

wire [7:0] leds;
data_exporter data_exporter1 (.clk(clk), .en(ready), .data({17'b0, solution}), .leds(leds));
assign leds = {PMOD1, PMOD2, PMOD3, PMOD4, PMOD7, PMOD8, PMOD9, PMOD10};

assign right1 = left1 + w1;
assign bottom1 = top1 + h1;
assign right2 = left2 + w2;
assign bottom2 = top2 + h2;

always @(posedge clk) begin
  if (ready == 1) begin
    LED1 <= 1;
    if (done == 1) begin
      LED5 <= 1;
    end
    else begin
      if (!((left1 >= right2) | (right1 <= left2) | (top1 >= bottom2) | (bottom1 <= top2))) begin
        if (counter1 != counter2) begin
          overlap1 = 1;
        end
      end

      if (counter1_overflow) begin
        if (overlap1 == 0) begin
          solution <= counter2;
        end
        overlap1 = 0;
      end

      if (counter2_overflow == 1) begin
        done <= 1;
      end
    end
  end
  else begin
    done <= 0;
    solution <= 0;
    overlap1 <= 0;
    ready <= 1;
    LED1 <= 0;
    LED5 <= 0;
  end
end

endmodule
module part2 (
  input wire clk,
  output reg LED1,
  output reg LED5,
  output wire PMOD1,
  output wire PMOD2,
  output wire PMOD3,
  output wire PMOD4,
  output wire PMOD7,
  output wire PMOD8,
  output wire PMOD9,
  output wire PMOD10
);


reg ready = 0;
reg [10:0] solution;

wire [10:0] counter1, counter2;
wire [9:0] left1, left2, top1, top2, right1, right2, bottom1, bottom2;
wire [4:0] w1, w2, h1, h2;
wire counter1_overflow, counter2_overflow;
reg overlap1;
reg done;

plain_counter #(.WIDTH(11), .VAL(1237)) plain_counter1 (.clk(clk), .en(ready), .inc(1'b1), .v(counter1), .r(counter1_overflow));
plain_counter #(.WIDTH(11), .VAL(1237)) plain_counter2 (.clk(clk), .en(ready), .inc(counter1_overflow), .v(counter2), .r(counter2_overflow));

rom rom1 (.clk(clk), .addr(counter1), .left(left1), .top(top1), .w(w1), .h(h1));
rom rom2 (.clk(clk), .addr(counter2), .left(left2), .top(top2), .w(w2), .h(h2));

wire [7:0] leds;
data_exporter data_exporter1 (.clk(clk), .en(ready), .data({17'b0, solution}), .leds(leds));
assign leds = {PMOD1, PMOD2, PMOD3, PMOD4, PMOD7, PMOD8, PMOD9, PMOD10};

assign right1 = left1 + w1;
assign bottom1 = top1 + h1;
assign right2 = left2 + w2;
assign bottom2 = top2 + h2;

always @(posedge clk) begin
  if (ready == 1) begin
    LED1 <= 1;
    if (done == 1) begin
      LED5 <= 1;
    end
    else begin
      if (!((left1 >= right2) | (right1 <= left2) | (top1 >= bottom2) | (bottom1 <= top2))) begin
        if (counter1 != counter2) begin
          overlap1 = 1;
        end
      end

      if (counter1_overflow) begin
        if (overlap1 == 0) begin
          solution <= counter2;
        end
        overlap1 = 0;
      end

      if (counter2_overflow == 1) begin
        done <= 1;
      end
    end
  end
  else begin
    done <= 0;
    solution <= 0;
    overlap1 <= 0;
    ready <= 1;
    LED1 <= 0;
    LED5 <= 0;
  end
end

endmodule