data/full_repos/permissive/189714993/Stoper.srcs/sources_1/new/Stoper/ms_clock_switched.v
data/verilator_xmls/281217e0-6913-4143-ad09-2e5107d1ece3.xml
module ms_clock_switched(ms_clock, control, ms_clock_switched);

	input ms_clock, control;
	output ms_clock_switched;
	reg ms_clock_switched;
	reg state;
	

	always @ (negedge control)
		state <= ~state;
	
	always @ (ms_clock)
		begin
		    if (state === 1'bx) state = 1'b0;
			if (state == 0)
				ms_clock_switched <= 0;
			else
				ms_clock_switched <= ms_clock;
		end
endmodule
module ms_clock_switched(ms_clock, control, ms_clock_switched);


	input ms_clock, control;
	output ms_clock_switched;
	reg ms_clock_switched;
	reg state;
	

	always @ (negedge control)
		state <= ~state;
	
	always @ (ms_clock)
		begin
		    if (state === 1'bx) state = 1'b0;
			if (state == 0)
				ms_clock_switched <= 0;
			else
				ms_clock_switched <= ms_clock;
		end
endmodule