data/full_repos/permissive/194106100/DE0/DE0_top.v
 line:99: before: ")"
1: b"%Error: data/full_repos/permissive/194106100/DE0/DE0_top.v:83: Cannot find file containing module: 'sys_reset'\n sys_reset RSTU (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194106100/DE0,data/full_repos/permissive/194106100/sys_reset\n             data/full_repos/permissive/194106100/DE0,data/full_repos/permissive/194106100/sys_reset.v\n             data/full_repos/permissive/194106100/DE0,data/full_repos/permissive/194106100/sys_reset.sv\n             sys_reset\n             sys_reset.v\n             sys_reset.sv\n             obj_dir/sys_reset\n             obj_dir/sys_reset.v\n             obj_dir/sys_reset.sv\n%Error: data/full_repos/permissive/194106100/DE0/DE0_top.v:87: Cannot find file containing module: 'GLOBAL'\n GLOBAL rst_GU (\n ^~~~~~\n%Error: data/full_repos/permissive/194106100/DE0/DE0_top.v:91: Cannot find file containing module: 'vjtag_test'\n vjtag_test VU (\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module DE0_top
(

	input wire CLOCK_50,
	input wire CLOCK_50_2,

	input wire [2:0] BUTTON,

	input wire [9:0] SW,

	output wire [6:0] HEX0_D,
	output wire HEX0_DP,
	output wire [6:0] HEX1_D,
	output wire HEX1_DP,
	output wire [6:0] HEX2_D,
	output wire HEX2_DP,
	output wire [6:0] HEX3_D,
	output wire HEX3_DP,

	output wire [9:0] LEDG,

	output wire UART_TXD,
	input wire UART_RXD,
	output wire UART_CTS,
	input wire UART_RTS,

	inout wire [15:0] DRAM_DQ,
	output wire [12:0] DRAM_ADDR,
	output wire DRAM_LDQM,
	output wire DRAM_UDQM,
	output wire DRAM_WE_N,
	output wire DRAM_CAS_N,
	output wire DRAM_RAS_N,
	output wire DRAM_CS_N,
	output wire DRAM_BA_0,
	output wire DRAM_BA_1,
	output wire DRAM_CLK,
	output wire DRAM_CKE,

	inout wire [15:0] FL_DQ,
	output wire [21:0] FL_ADDR,
	output wire FL_WE_N,
	output wire FL_RST_N,
	output wire FL_OE_N,
	output wire FL_CE_N,
	output wire FL_WP_N,
	output wire FL_BYTE_N,
	input wire FL_RY,

	output wire LCD_BLON,
	output wire LCD_RW,
	output wire LCD_EN,
	output wire LCD_RS,
	inout wire [7:0] LCD_DATA,

	input wire [3:0] SD_DAT,
	inout wire SD_CMD,
	output wire SD_CLK,
	input wire SD_WP_N,

	input wire PS2_KBCLK,
	input wire PS2_KBDAT,
	inout wire PS2_MSCLK,
	inout wire PS2_MSDAT,

	output wire VGA_HS,
	output wire VGA_VS,
	output wire [3:0] VGA_R,
	output wire [3:0] VGA_G,
	output wire [3:0] VGA_B,

	input wire [1:0] GPIO0_CLKIN,
	output wire [1:0] GPIO0_CLKOUT,
	inout wire [31:0] GPIO0_D,
	input wire [1:0] GPIO1_CLKIN,
	output wire [1:0] GPIO1_CLKOUT,
	inout wire [31:0] GPIO1_D
);

wire reset, g_reset;

	sys_reset RSTU (
		.RSTn(BUTTON[0]), .CLK(CLOCK_50), .DOUT(reset)
	);

	GLOBAL rst_GU (
		.IN(reset), .OUT(g_reset)
	);

	vjtag_test VU (
		.p_reset(g_reset),
		.m_clock(CLOCK_50),
		.HEX0(HEX0_D),
		.HEX1(HEX1_D),
		.HEX2(HEX2_D),
		.HEX3(HEX3_D),
		.LEDG(LEDG),
	);

	assign HEX0_DP = 1'b1;
	assign HEX1_DP = 1'b1;
	assign HEX2_DP = 1'b1;
	assign HEX3_DP = 1'b1;

	assign GPIO0_D = 32'bz;
	assign GPIO1_D = 32'bz;

endmodule
module DE0_top
(

	input wire CLOCK_50,
	input wire CLOCK_50_2,

	input wire [2:0] BUTTON,

	input wire [9:0] SW,

	output wire [6:0] HEX0_D,
	output wire HEX0_DP,
	output wire [6:0] HEX1_D,
	output wire HEX1_DP,
	output wire [6:0] HEX2_D,
	output wire HEX2_DP,
	output wire [6:0] HEX3_D,
	output wire HEX3_DP,

	output wire [9:0] LEDG,

	output wire UART_TXD,
	input wire UART_RXD,
	output wire UART_CTS,
	input wire UART_RTS,

	inout wire [15:0] DRAM_DQ,
	output wire [12:0] DRAM_ADDR,
	output wire DRAM_LDQM,
	output wire DRAM_UDQM,
	output wire DRAM_WE_N,
	output wire DRAM_CAS_N,
	output wire DRAM_RAS_N,
	output wire DRAM_CS_N,
	output wire DRAM_BA_0,
	output wire DRAM_BA_1,
	output wire DRAM_CLK,
	output wire DRAM_CKE,

	inout wire [15:0] FL_DQ,
	output wire [21:0] FL_ADDR,
	output wire FL_WE_N,
	output wire FL_RST_N,
	output wire FL_OE_N,
	output wire FL_CE_N,
	output wire FL_WP_N,
	output wire FL_BYTE_N,
	input wire FL_RY,

	output wire LCD_BLON,
	output wire LCD_RW,
	output wire LCD_EN,
	output wire LCD_RS,
	inout wire [7:0] LCD_DATA,

	input wire [3:0] SD_DAT,
	inout wire SD_CMD,
	output wire SD_CLK,
	input wire SD_WP_N,

	input wire PS2_KBCLK,
	input wire PS2_KBDAT,
	inout wire PS2_MSCLK,
	inout wire PS2_MSDAT,

	output wire VGA_HS,
	output wire VGA_VS,
	output wire [3:0] VGA_R,
	output wire [3:0] VGA_G,
	output wire [3:0] VGA_B,

	input wire [1:0] GPIO0_CLKIN,
	output wire [1:0] GPIO0_CLKOUT,
	inout wire [31:0] GPIO0_D,
	input wire [1:0] GPIO1_CLKIN,
	output wire [1:0] GPIO1_CLKOUT,
	inout wire [31:0] GPIO1_D
);


wire reset, g_reset;

	sys_reset RSTU (
		.RSTn(BUTTON[0]), .CLK(CLOCK_50), .DOUT(reset)
	);

	GLOBAL rst_GU (
		.IN(reset), .OUT(g_reset)
	);

	vjtag_test VU (
		.p_reset(g_reset),
		.m_clock(CLOCK_50),
		.HEX0(HEX0_D),
		.HEX1(HEX1_D),
		.HEX2(HEX2_D),
		.HEX3(HEX3_D),
		.LEDG(LEDG),
	);

	assign HEX0_DP = 1'b1;
	assign HEX1_DP = 1'b1;
	assign HEX2_DP = 1'b1;
	assign HEX3_DP = 1'b1;

	assign GPIO0_D = 32'bz;
	assign GPIO1_D = 32'bz;

endmodule