data/full_repos/permissive/135852214/Verilog/dff.v
data/verilator_xmls/3a6785ac-2254-40b4-8303-9bbe7e8ff3c4.xml
module dff(
    input data_in,
    output reg data_out,
    input wr_e,
    input clr,
    input clk
    );

always @(posedge clk, posedge clr)
begin
	if(clr)
		data_out <= 1'b0;
	else if(wr_e)
		data_out <= data_in;
end

endmodule
module dff(
    input data_in,
    output reg data_out,
    input wr_e,
    input clr,
    input clk
    );


always @(posedge clk, posedge clr)
begin
	if(clr)
		data_out <= 1'b0;
	else if(wr_e)
		data_out <= data_in;
end

endmodule