data/full_repos/permissive/161526648/pc.v
data/verilator_xmls/7aaffbfd-7c40-4191-9491-2871e101be9f.xml
module pc(in,reset,clock,out);
	input [31:0] in;
	input	clock,reset;
	output reg[31:0] out;
	
	initial begin
		out = 32'b0;
	end
	
	always @(posedge clock or posedge reset) begin
	if (reset==1'b1)
		out <= 32'b0;
	else out <= in;
	end
endmodule
module pc(in,reset,clock,out);

	input [31:0] in;
	input	clock,reset;
	output reg[31:0] out;
	
	initial begin
		out = 32'b0;
	end
	
	always @(posedge clock or posedge reset) begin
	if (reset==1'b1)
		out <= 32'b0;
	else out <= in;
	end
endmodule