data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/inv.v
 line:10: before: "a_bus_r2c"
data/verilator_xmls/d66098a1-3b16-4e6f-84f7-cff47f293141.xml
module INVTX1(in, out);
  input [0:0] in;
  output [0:0] out;

  assign out = ~in;

endmodule
module INVTX1(in, out);

  input [0:0] in;
  output [0:0] out;

  assign out = ~in;

endmodule