data/full_repos/permissive/15244593/src/hw/fpga/source/enet_if/v7_enet_top.v
1: b"%Error: data/full_repos/permissive/15244593/src/hw/fpga/source/enet_if/v7_enet_top.v:74: Cannot find file containing module: 'v7_ethernet_top'\nv7_ethernet_top v7_et\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/15244593/src/hw/fpga/source/enet_if,data/full_repos/permissive/15244593/v7_ethernet_top\n             data/full_repos/permissive/15244593/src/hw/fpga/source/enet_if,data/full_repos/permissive/15244593/v7_ethernet_top.v\n             data/full_repos/permissive/15244593/src/hw/fpga/source/enet_if,data/full_repos/permissive/15244593/v7_ethernet_top.sv\n             v7_ethernet_top\n             v7_ethernet_top.v\n             v7_ethernet_top.sv\n             obj_dir/v7_ethernet_top\n             obj_dir/v7_ethernet_top.v\n             obj_dir/v7_ethernet_top.sv\n%Error: Exiting due to 1 error(s)\n"
module ethernet_top(
  input                i_rst,
  input                i_clk_125,
  input                i_clk_200,
  output               phy_resetn,

  output [7:0]         gmii_txd,
  output               gmii_tx_en,
  output               gmii_tx_er,
  output               gmii_tx_clk,
  input  [7:0]         gmii_rxd,
  input                gmii_rx_dv,
  input                gmii_rx_er,
  input                gmii_rx_clk,
  input                gmii_col,
  input                gmii_crs,
  input                mii_tx_clk,

  input                gtrefclk_p,
  input                gtrefclk_n,
  output               txp,
  output               txn,
  input                rxp,
  input                rxn,
   
  output        synchronization_done,
  output        linkup,


  output        mdio_out,
  input         mdio_in,
  output        mdc_out,
  output        mdio_t,


  input                i_enet_enable,
  input                i_enet_loopback,
  input   [31:0]       i_enet_ddr_source_addr,
  input   [31:0]       i_enet_ddr_dest_addr,
  input   [31:0]       i_enet_rcv_data_size,
  input   [31:0]       i_enet_snd_data_size,
  output  [31:0]       o_enet_rx_cnt,
  output  [31:0]       o_enet_tx_cnt,
  output               o_enet_rx_done,
  output               o_enet_tx_done,
  

  output               o_ddr_wr_req,
  output               o_ddr_rd_req,
  output   [255:0]     o_ddr_wr_data,
  output      [31:0]   o_ddr_wr_be,
  output      [31:0]   o_ddr_wr_addr,
  output      [31:0]   o_ddr_rd_addr,
  input       [255:0]  i_ddr_rd_data,
  input                i_ddr_wr_ack,
  input                i_ddr_rd_ack,
  input                i_ddr_rd_data_valid
);



v7_ethernet_top v7_et
(
.glbl_rst(i_rst),
.i_clk_200(i_clk_200),
.phy_resetn(phy_resetn),
.gtrefclk_p(gtrefclk_p),
.gtrefclk_n(gtrefclk_n),
.txp(txp),
.txn(txn),
.rxp(rxp),
.rxn(rxn),
.synchronization_done(synchronization_done),
.linkup(linkup),
.mdio_i(mdio_in),
.mdio_o(mdio_out),
.mdio_t(mdio_t),
.mdc(mdc_out),
.i_enet_enable(i_enet_enable),
.i_enet_loopback(i_enet_loopback),
.i_enet_ddr_source_addr(i_enet_ddr_source_addr),
.i_enet_ddr_dest_addr(i_enet_ddr_dest_addr),
.i_enet_rcv_data_size(i_enet_rcv_data_size),
.i_enet_snd_data_size(i_enet_snd_data_size),
.o_enet_rx_cnt(o_enet_rx_cnt),
.o_enet_tx_cnt(o_enet_tx_cnt),
.o_enet_rx_done(o_enet_rx_done),
.o_enet_tx_done(o_enet_tx_done),
.o_ddr_wr_req(o_ddr_wr_req),
.o_ddr_rd_req(o_ddr_rd_req),
.o_ddr_wr_data(o_ddr_wr_data),
.o_ddr_wr_be(o_ddr_wr_be),
.o_ddr_wr_addr(o_ddr_wr_addr),
.o_ddr_rd_addr(o_ddr_rd_addr),
.i_ddr_rd_data(i_ddr_rd_data),
.i_ddr_wr_ack(i_ddr_wr_ack),
.i_ddr_rd_ack(i_ddr_rd_ack),
.i_ddr_rd_data_valid(i_ddr_rd_data_valid)
);

endmodule
module ethernet_top(
  input                i_rst,
  input                i_clk_125,
  input                i_clk_200,
  output               phy_resetn,

  output [7:0]         gmii_txd,
  output               gmii_tx_en,
  output               gmii_tx_er,
  output               gmii_tx_clk,
  input  [7:0]         gmii_rxd,
  input                gmii_rx_dv,
  input                gmii_rx_er,
  input                gmii_rx_clk,
  input                gmii_col,
  input                gmii_crs,
  input                mii_tx_clk,

  input                gtrefclk_p,
  input                gtrefclk_n,
  output               txp,
  output               txn,
  input                rxp,
  input                rxn,
   
  output        synchronization_done,
  output        linkup,


  output        mdio_out,
  input         mdio_in,
  output        mdc_out,
  output        mdio_t,


  input                i_enet_enable,
  input                i_enet_loopback,
  input   [31:0]       i_enet_ddr_source_addr,
  input   [31:0]       i_enet_ddr_dest_addr,
  input   [31:0]       i_enet_rcv_data_size,
  input   [31:0]       i_enet_snd_data_size,
  output  [31:0]       o_enet_rx_cnt,
  output  [31:0]       o_enet_tx_cnt,
  output               o_enet_rx_done,
  output               o_enet_tx_done,
  

  output               o_ddr_wr_req,
  output               o_ddr_rd_req,
  output   [255:0]     o_ddr_wr_data,
  output      [31:0]   o_ddr_wr_be,
  output      [31:0]   o_ddr_wr_addr,
  output      [31:0]   o_ddr_rd_addr,
  input       [255:0]  i_ddr_rd_data,
  input                i_ddr_wr_ack,
  input                i_ddr_rd_ack,
  input                i_ddr_rd_data_valid
);




v7_ethernet_top v7_et
(
.glbl_rst(i_rst),
.i_clk_200(i_clk_200),
.phy_resetn(phy_resetn),
.gtrefclk_p(gtrefclk_p),
.gtrefclk_n(gtrefclk_n),
.txp(txp),
.txn(txn),
.rxp(rxp),
.rxn(rxn),
.synchronization_done(synchronization_done),
.linkup(linkup),
.mdio_i(mdio_in),
.mdio_o(mdio_out),
.mdio_t(mdio_t),
.mdc(mdc_out),
.i_enet_enable(i_enet_enable),
.i_enet_loopback(i_enet_loopback),
.i_enet_ddr_source_addr(i_enet_ddr_source_addr),
.i_enet_ddr_dest_addr(i_enet_ddr_dest_addr),
.i_enet_rcv_data_size(i_enet_rcv_data_size),
.i_enet_snd_data_size(i_enet_snd_data_size),
.o_enet_rx_cnt(o_enet_rx_cnt),
.o_enet_tx_cnt(o_enet_tx_cnt),
.o_enet_rx_done(o_enet_rx_done),
.o_enet_tx_done(o_enet_tx_done),
.o_ddr_wr_req(o_ddr_wr_req),
.o_ddr_rd_req(o_ddr_rd_req),
.o_ddr_wr_data(o_ddr_wr_data),
.o_ddr_wr_be(o_ddr_wr_be),
.o_ddr_wr_addr(o_ddr_wr_addr),
.o_ddr_rd_addr(o_ddr_rd_addr),
.i_ddr_rd_data(i_ddr_rd_data),
.i_ddr_wr_ack(i_ddr_wr_ack),
.i_ddr_rd_ack(i_ddr_rd_ack),
.i_ddr_rd_data_valid(i_ddr_rd_data_valid)
);

endmodule