data/full_repos/permissive/109936328/pipeline/ex.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/pipeline/ex.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:2: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:3: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:4: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:50: Define or directive not defined: \'`ADDR_W\'\n  input [`ADDR_W - 1:0] i_pc;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:51: Define or directive not defined: \'`INSTR_W\'\n  input [`INSTR_W - 1:0] i_instr;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:53: Define or directive not defined: \'`ALU_OP_W\'\n  input [`ALU_OP_W - 1:0] i_alu_op;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:55: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_alu_data_a;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:56: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_alu_data_b;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:57: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_imm;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:59: Define or directive not defined: \'`MEM_OP_W\'\n  input [`MEM_OP_W - 1:0] i_mem_op;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:61: Define or directive not defined: \'`DEST_SRC_W\'\n  input [`DEST_SRC_W - 1:0] i_dest_src;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:62: Define or directive not defined: \'`REG_IDX_W\'\n  input [`REG_IDX_W - 1:0] i_dest_reg;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:66: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] r_pc;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:67: Define or directive not defined: \'`INSTR_W\'\n  reg [`INSTR_W - 1:0] r_instr;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:69: Define or directive not defined: \'`ALU_OP_W\'\n  reg [`ALU_OP_W - 1:0] r_alu_op;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:71: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] r_alu_data_a;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:72: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] r_alu_data_b;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:73: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] r_imm;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:75: Define or directive not defined: \'`MEM_OP_W\'\n  reg [`MEM_OP_W - 1:0] r_mem_op;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:77: Define or directive not defined: \'`DEST_SRC_W\'\n  reg [`DEST_SRC_W - 1:0] r_dest_src;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:78: Define or directive not defined: \'`REG_IDX_W\'\n  reg [`REG_IDX_W - 1:0] r_dest_reg;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:82: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] s_alu_eval;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:85: Define or directive not defined: \'`ADDR_W\'\n  output [`ADDR_W - 1:0] o_pc;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:86: Define or directive not defined: \'`INSTR_W\'\n  output [`INSTR_W - 1:0] o_instr;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:88: Define or directive not defined: \'`DEST_SRC_W\'\n  output [`DEST_SRC_W - 1:0] o_dest_src;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:89: Define or directive not defined: \'`REG_IDX_W\'\n  output [`REG_IDX_W - 1:0] o_dest_reg;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:91: Define or directive not defined: \'`WORD_W\'\n  output [`WORD_W - 1:0] o_alu_eval;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:93: Define or directive not defined: \'`MEM_OP_W\'\n  output [`MEM_OP_W - 1:0] o_mem_op;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:95: Define or directive not defined: \'`ADDR_W\'\n  output [`ADDR_W - 1:0] o_mem_req_addr;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:96: Define or directive not defined: \'`WORD_W\'\n  output [`WORD_W - 1:0] o_mem_req_wr_data;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:98: Define or directive not defined: \'`MEM_COUNT_W\'\n  output reg [`MEM_COUNT_W - 1:0] o_mem_req_count;\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:101: Define or directive not defined: \'`ADDR_W\'\n  output [`ADDR_W - 1:0] o_branch_addr;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:122: Define or directive not defined: \'`ALU_ADD\'\n      r_alu_op <= `ALU_ADD;\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:122: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      r_alu_op <= `ALU_ADD;\n                          ^\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:128: Define or directive not defined: \'`MEM_OP_NOP\'\n      r_mem_op <= `MEM_OP_NOP;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:128: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      r_mem_op <= `MEM_OP_NOP;\n                             ^\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:130: Define or directive not defined: \'`DEST_SRC_NONE\'\n      r_dest_src <= `DEST_SRC_NONE;\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:130: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      r_dest_src <= `DEST_SRC_NONE;\n                                  ^\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:169: Define or directive not defined: \'`MEM_OP_WR_WORD\'\n      `MEM_OP_WR_WORD: begin\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:169: syntax error, unexpected \':\', expecting endcase\n      `MEM_OP_WR_WORD: begin\n                     ^\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:170: Define or directive not defined: \'`MEM_COUNT_WORD\'\n        o_mem_req_count = `MEM_COUNT_WORD;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:174: Define or directive not defined: \'`MEM_OP_WR_HALF\'\n      `MEM_OP_WR_HALF: begin\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:174: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      `MEM_OP_WR_HALF: begin\n                       ^~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:175: Define or directive not defined: \'`MEM_COUNT_HALF\'\n        o_mem_req_count = `MEM_COUNT_HALF;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:179: Define or directive not defined: \'`MEM_OP_WR_BYTE\'\n      `MEM_OP_WR_BYTE: begin\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:179: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      `MEM_OP_WR_BYTE: begin\n                       ^~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:180: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n        o_mem_req_count = `MEM_COUNT_BYTE;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:184: Define or directive not defined: \'`MEM_OP_RD_WORD\'\n      `MEM_OP_RD_WORD: begin\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/ex.v:184: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n      `MEM_OP_RD_WORD: begin\n                       ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ex(
  clk,
  clr,
  stall,

  i_pc,
  i_instr,

  i_alu_op,

  i_alu_data_a,
  i_alu_data_b,
  i_imm,

  i_mem_op,

  i_dest_src,
  i_dest_reg,

  i_branch_op,

  o_pc,
  o_instr,

  o_dest_src,
  o_dest_reg,

  o_alu_eval,

  o_mem_op,

  o_mem_req_addr,
  o_mem_req_wr_data,
  o_mem_req_wr_en,
  o_mem_req_count,

  o_branch,
  o_branch_addr
);

  input clk;
  input clr;
  input stall;

  input [`ADDR_W - 1:0] i_pc;
  input [`INSTR_W - 1:0] i_instr;

  input [`ALU_OP_W - 1:0] i_alu_op;

  input [`WORD_W - 1:0] i_alu_data_a;
  input [`WORD_W - 1:0] i_alu_data_b;
  input [`WORD_W - 1:0] i_imm;

  input [`MEM_OP_W - 1:0] i_mem_op;

  input [`DEST_SRC_W - 1:0] i_dest_src;
  input [`REG_IDX_W - 1:0] i_dest_reg;

  input i_branch_op;

  reg [`ADDR_W - 1:0] r_pc;
  reg [`INSTR_W - 1:0] r_instr;

  reg [`ALU_OP_W - 1:0] r_alu_op;

  reg [`WORD_W - 1:0] r_alu_data_a;
  reg [`WORD_W - 1:0] r_alu_data_b;
  reg [`WORD_W - 1:0] r_imm;

  reg [`MEM_OP_W - 1:0] r_mem_op;

  reg [`DEST_SRC_W - 1:0] r_dest_src;
  reg [`REG_IDX_W - 1:0] r_dest_reg;

  reg r_branch_op;

  wire [`WORD_W - 1:0] s_alu_eval;
  wire s_alu_zero;

  output [`ADDR_W - 1:0] o_pc;
  output [`INSTR_W - 1:0] o_instr;

  output [`DEST_SRC_W - 1:0] o_dest_src;
  output [`REG_IDX_W - 1:0] o_dest_reg;

  output [`WORD_W - 1:0] o_alu_eval;

  output [`MEM_OP_W - 1:0] o_mem_op;

  output [`ADDR_W - 1:0] o_mem_req_addr;
  output [`WORD_W - 1:0] o_mem_req_wr_data;
  output reg o_mem_req_wr_en;
  output reg [`MEM_COUNT_W - 1:0] o_mem_req_count;

  output o_branch;
  output [`ADDR_W - 1:0] o_branch_addr;


  assign o_pc = r_pc;
  assign o_instr = r_instr;

  assign o_dest_src = r_dest_src;
  assign o_dest_reg = r_dest_reg;

  assign o_alu_eval = s_alu_eval;

  assign o_mem_op = r_mem_op;

  assign o_branch = s_alu_zero & r_branch_op;
  assign o_branch_addr = r_pc + r_imm;

  always@(posedge clk) begin
    if(clr == 1) begin
      r_pc <= 0;
      r_instr <= 0;

      r_alu_op <= `ALU_ADD;

      r_alu_data_a <= 0;
      r_alu_data_b <= 0;
      r_imm <= 0;
      
      r_mem_op <= `MEM_OP_NOP;

      r_dest_src <= `DEST_SRC_NONE;
      r_dest_reg <= 0;

      r_branch_op <= 0;
    end else if(stall == 0) begin
      r_pc <= i_pc;
      r_instr <= i_instr;

      r_alu_op <= i_alu_op;

      r_mem_op <= i_mem_op;

      r_alu_data_a <= i_alu_data_a;
      r_alu_data_b <= i_alu_data_b;
      r_imm <= i_imm;

      r_dest_src <= i_dest_src;
      r_dest_reg <= i_dest_reg;

      r_branch_op <= i_branch_op;
    end
  end

  alu comp(
    .opp_a(r_alu_data_a),
    .opp_b(r_alu_data_b),

    .op(r_alu_op),

    .eval(s_alu_eval),
    .zero(s_alu_zero)
  );

  assign o_mem_req_addr = r_imm + r_alu_data_a;
  assign o_mem_req_wr_data = r_alu_data_b;
  

  always@(*) begin
    case(r_mem_op)
      `MEM_OP_WR_WORD: begin
        o_mem_req_count = `MEM_COUNT_WORD;
        o_mem_req_wr_en = 1;
      end

      `MEM_OP_WR_HALF: begin
        o_mem_req_count = `MEM_COUNT_HALF;
        o_mem_req_wr_en = 1;
      end

      `MEM_OP_WR_BYTE: begin
        o_mem_req_count = `MEM_COUNT_BYTE;
        o_mem_req_wr_en = 1;
      end

      `MEM_OP_RD_WORD: begin
        o_mem_req_count = `MEM_COUNT_WORD;
        o_mem_req_wr_en = 0;
      end

      `MEM_OP_RD_HALF: begin
        o_mem_req_count = `MEM_COUNT_HALF;
        o_mem_req_wr_en = 0;
      end

      `MEM_OP_RD_BYTE: begin
        o_mem_req_count = `MEM_COUNT_BYTE;
        o_mem_req_wr_en = 0;
      end

      `MEM_OP_RD_UHALF: begin
        o_mem_req_count = `MEM_COUNT_HALF;
        o_mem_req_wr_en = 0;
      end

      `MEM_OP_RD_UBYTE: begin
        o_mem_req_count = `MEM_COUNT_BYTE;
        o_mem_req_wr_en = 0;
      end

      default: begin
        o_mem_req_count = `MEM_COUNT_NONE;
        o_mem_req_wr_en = 0;
      end
    endcase
  end

endmodule
module ex(
  clk,
  clr,
  stall,

  i_pc,
  i_instr,

  i_alu_op,

  i_alu_data_a,
  i_alu_data_b,
  i_imm,

  i_mem_op,

  i_dest_src,
  i_dest_reg,

  i_branch_op,

  o_pc,
  o_instr,

  o_dest_src,
  o_dest_reg,

  o_alu_eval,

  o_mem_op,

  o_mem_req_addr,
  o_mem_req_wr_data,
  o_mem_req_wr_en,
  o_mem_req_count,

  o_branch,
  o_branch_addr
);


  input clk;
  input clr;
  input stall;

  input [`ADDR_W - 1:0] i_pc;
  input [`INSTR_W - 1:0] i_instr;

  input [`ALU_OP_W - 1:0] i_alu_op;

  input [`WORD_W - 1:0] i_alu_data_a;
  input [`WORD_W - 1:0] i_alu_data_b;
  input [`WORD_W - 1:0] i_imm;

  input [`MEM_OP_W - 1:0] i_mem_op;

  input [`DEST_SRC_W - 1:0] i_dest_src;
  input [`REG_IDX_W - 1:0] i_dest_reg;

  input i_branch_op;

  reg [`ADDR_W - 1:0] r_pc;
  reg [`INSTR_W - 1:0] r_instr;

  reg [`ALU_OP_W - 1:0] r_alu_op;

  reg [`WORD_W - 1:0] r_alu_data_a;
  reg [`WORD_W - 1:0] r_alu_data_b;
  reg [`WORD_W - 1:0] r_imm;

  reg [`MEM_OP_W - 1:0] r_mem_op;

  reg [`DEST_SRC_W - 1:0] r_dest_src;
  reg [`REG_IDX_W - 1:0] r_dest_reg;

  reg r_branch_op;

  wire [`WORD_W - 1:0] s_alu_eval;
  wire s_alu_zero;

  output [`ADDR_W - 1:0] o_pc;
  output [`INSTR_W - 1:0] o_instr;

  output [`DEST_SRC_W - 1:0] o_dest_src;
  output [`REG_IDX_W - 1:0] o_dest_reg;

  output [`WORD_W - 1:0] o_alu_eval;

  output [`MEM_OP_W - 1:0] o_mem_op;

  output [`ADDR_W - 1:0] o_mem_req_addr;
  output [`WORD_W - 1:0] o_mem_req_wr_data;
  output reg o_mem_req_wr_en;
  output reg [`MEM_COUNT_W - 1:0] o_mem_req_count;

  output o_branch;
  output [`ADDR_W - 1:0] o_branch_addr;


  assign o_pc = r_pc;
  assign o_instr = r_instr;

  assign o_dest_src = r_dest_src;
  assign o_dest_reg = r_dest_reg;

  assign o_alu_eval = s_alu_eval;

  assign o_mem_op = r_mem_op;

  assign o_branch = s_alu_zero & r_branch_op;
  assign o_branch_addr = r_pc + r_imm;

  always@(posedge clk) begin
    if(clr == 1) begin
      r_pc <= 0;
      r_instr <= 0;

      r_alu_op <= `ALU_ADD;

      r_alu_data_a <= 0;
      r_alu_data_b <= 0;
      r_imm <= 0;
      
      r_mem_op <= `MEM_OP_NOP;

      r_dest_src <= `DEST_SRC_NONE;
      r_dest_reg <= 0;

      r_branch_op <= 0;
    end else if(stall == 0) begin
      r_pc <= i_pc;
      r_instr <= i_instr;

      r_alu_op <= i_alu_op;

      r_mem_op <= i_mem_op;

      r_alu_data_a <= i_alu_data_a;
      r_alu_data_b <= i_alu_data_b;
      r_imm <= i_imm;

      r_dest_src <= i_dest_src;
      r_dest_reg <= i_dest_reg;

      r_branch_op <= i_branch_op;
    end
  end

  alu comp(
    .opp_a(r_alu_data_a),
    .opp_b(r_alu_data_b),

    .op(r_alu_op),

    .eval(s_alu_eval),
    .zero(s_alu_zero)
  );

  assign o_mem_req_addr = r_imm + r_alu_data_a;
  assign o_mem_req_wr_data = r_alu_data_b;
  

  always@(*) begin
    case(r_mem_op)
      `MEM_OP_WR_WORD: begin
        o_mem_req_count = `MEM_COUNT_WORD;
        o_mem_req_wr_en = 1;
      end

      `MEM_OP_WR_HALF: begin
        o_mem_req_count = `MEM_COUNT_HALF;
        o_mem_req_wr_en = 1;
      end

      `MEM_OP_WR_BYTE: begin
        o_mem_req_count = `MEM_COUNT_BYTE;
        o_mem_req_wr_en = 1;
      end

      `MEM_OP_RD_WORD: begin
        o_mem_req_count = `MEM_COUNT_WORD;
        o_mem_req_wr_en = 0;
      end

      `MEM_OP_RD_HALF: begin
        o_mem_req_count = `MEM_COUNT_HALF;
        o_mem_req_wr_en = 0;
      end

      `MEM_OP_RD_BYTE: begin
        o_mem_req_count = `MEM_COUNT_BYTE;
        o_mem_req_wr_en = 0;
      end

      `MEM_OP_RD_UHALF: begin
        o_mem_req_count = `MEM_COUNT_HALF;
        o_mem_req_wr_en = 0;
      end

      `MEM_OP_RD_UBYTE: begin
        o_mem_req_count = `MEM_COUNT_BYTE;
        o_mem_req_wr_en = 0;
      end

      default: begin
        o_mem_req_count = `MEM_COUNT_NONE;
        o_mem_req_wr_en = 0;
      end
    endcase
  end

endmodule