data/full_repos/permissive/214278225/1_7SegmentDisplay/BuildingBlocks/SevenSegOneDig/SevenSegOneDig.v
data/verilator_xmls/a0dd015b-b9f0-43ad-9d58-e19623ae2518.xml
module SevenSegOneDig(in, sevenSeg,anode);

input [3:0] in;
output reg [7:0] sevenSeg;
output reg [3:0] anode;



always @(*) begin
	sevenSeg = 8'b00000010;
	anode = 4'b1110;
	case(in)
		0: sevenSeg = 8'b00000010;
		1: sevenSeg = 8'b10011110;
		2: sevenSeg = 8'b00100100;
		3: sevenSeg = 8'b00001100;
		4: sevenSeg = 8'b10011000;
		5: sevenSeg = 8'b01001000;
		6: sevenSeg = 8'b01000000;
		7: sevenSeg = 8'b00011110;
		8: sevenSeg = 8'b00000000;
		9: sevenSeg = 8'b00001000;
		10: sevenSeg = 8'b00010000;
		11: sevenSeg = 8'b11000000;
		12: sevenSeg = 8'b01100010;
		13: sevenSeg = 8'b10000100;
		14: sevenSeg = 8'b01100000;
		15: sevenSeg = 8'b01110000;
	endcase
end

endmodule
module SevenSegOneDig(in, sevenSeg,anode);


input [3:0] in;
output reg [7:0] sevenSeg;
output reg [3:0] anode;



always @(*) begin
	sevenSeg = 8'b00000010;
	anode = 4'b1110;
	case(in)
		0: sevenSeg = 8'b00000010;
		1: sevenSeg = 8'b10011110;
		2: sevenSeg = 8'b00100100;
		3: sevenSeg = 8'b00001100;
		4: sevenSeg = 8'b10011000;
		5: sevenSeg = 8'b01001000;
		6: sevenSeg = 8'b01000000;
		7: sevenSeg = 8'b00011110;
		8: sevenSeg = 8'b00000000;
		9: sevenSeg = 8'b00001000;
		10: sevenSeg = 8'b00010000;
		11: sevenSeg = 8'b11000000;
		12: sevenSeg = 8'b01100010;
		13: sevenSeg = 8'b10000100;
		14: sevenSeg = 8'b01100000;
		15: sevenSeg = 8'b01110000;
	endcase
end

endmodule