data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v
1: b'%Error: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:35: syntax error, unexpected \')\', expecting "\'{"\n    crt_sys ob_crt_sys( clk, _reset, db, ds, as, _wr, ma, md,  _mcs, _mrd, _mwr, med_res, pixel, sync, a, b, hsync, vsync, extsyncon, int);\n                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #200 mdi = 8\'b0000_0001;     \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #400 mdi = 8\'b0000_0010;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #400 mdi = 8\'b1000_0100;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #400 mdi = 8\'b0000_1000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #400 mdi = 8\'bzzzz_zzzz;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #400 mdi = 8\'b0000_1000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #400 mdi = 8\'b0000_1000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #400 mdi = 8\'b0000_1000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #400 mdi = 8\'b0000_1000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #400 mdi = 8\'b0000_1000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #200 mdi = 8\'b0000_0001;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #400 mdi = 8\'b0000_0010;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #400 mdi = 8\'b1000_0100;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #400 mdi = 8\'b0000_1000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #20 _reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #200 dbi = 8\'b0000_0001;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #400 dbi = 8\'b0000_0010;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #400 dbi = 8\'b1000_0100;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #400 dbi = 8\'b0000_1000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #400 dbi = 8\'b0000_1000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #400 dbi = 8\'bzzzz_zzzz;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #400 dbi = 8\'bzzzz_zzzz;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #400 dbi = 8\'bzzzz_zzzz;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #400 dbi = 8\'bzzzz_zzzz;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #400 dbi = 8\'bzzzz_zzzz;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #200 dbi = 8\'b0000_0001;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #400 dbi = 8\'b0000_0010;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #400 dbi = 8\'b1000_0100;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #400 dbi = 8\'b0000_1000;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:96: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:111: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:112: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #200  as = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:118: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 0;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 0;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 0;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:123: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 0;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:125: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:126: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 0;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:127: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:128: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:130: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:131: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:132: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:133: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:134: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:135: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:136: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:137: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:138: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 0;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 0;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:142: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 0;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 0;       \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:145: Unsupported: Ignoring delay on this delayed statement.\n        #200  _wr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:150: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:151: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:152: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:153: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:154: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:155: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:156: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:157: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:158: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:159: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:160: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 1;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:161: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:162: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:163: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:164: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:165: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:166: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:167: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:168: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:169: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:170: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:171: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:172: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:173: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:174: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:175: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:176: Unsupported: Ignoring delay on this delayed statement.\n        #200  ds = 0;        \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:183: Unsupported: Ignoring delay on this delayed statement.\n        #10000 a = 4\'b1111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:184: Unsupported: Ignoring delay on this delayed statement.\n        #10000 a = 4\'b0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:185: Unsupported: Ignoring delay on this delayed statement.\n        #10000 a = 4\'b1111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:186: Unsupported: Ignoring delay on this delayed statement.\n        #10000 a = 4\'b0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:187: Unsupported: Ignoring delay on this delayed statement.\n        #10000 a = 4\'b1111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:188: Unsupported: Ignoring delay on this delayed statement.\n        #10000 a = 4\'b0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:189: Unsupported: Ignoring delay on this delayed statement.\n        #10000 a = 4\'b1111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:190: Unsupported: Ignoring delay on this delayed statement.\n        #10000 a = 4\'b0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:195: Unsupported: Ignoring delay on this delayed statement.\n        #15000 b = 4\'b1111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:196: Unsupported: Ignoring delay on this delayed statement.\n        #10000 b = 4\'b0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:197: Unsupported: Ignoring delay on this delayed statement.\n        #10000 b = 4\'b1111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:198: Unsupported: Ignoring delay on this delayed statement.\n        #10000 b = 4\'b0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:199: Unsupported: Ignoring delay on this delayed statement.\n        #10000 b = 4\'b1111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:200: Unsupported: Ignoring delay on this delayed statement.\n        #10000 b = 4\'b0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:201: Unsupported: Ignoring delay on this delayed statement.\n        #10000 b = 4\'b1111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/174263347/crtv10/hdl/crt_top.v:202: Unsupported: Ignoring delay on this delayed statement.\n        #10000 b = 4\'b0000;\n        ^\n%Error: Exiting due to 1 error(s), 128 warning(s)\n'
module crt_top;

    reg             clk, _reset;
    wire            med_res;
    reg     [7:0]   dbi, mdi;
    reg             ds, as, _wr;
    wire    [3:0]   pixel;
	wire  	[7:0]	md;
	wire	[19:0]  ma;
	wire    [7:0]	db;
    reg     [3:0]   a, b;
    reg             hsync, vsync;
    wire            extsyncon;
    
    assign extsyncon = 1;
    assign med_res 	 = 1;  
	assign db = dbi;
    assign md = mdi;

    crt_sys ob_crt_sys( clk, _reset, db, ds, as, _wr, ma, md,  _mcs, _mrd, _mwr, med_res, pixel, sync, a, b, hsync, vsync, extsyncon, int);

    initial begin
        mdi <= 8'bzzzz_zzzz;
        #200 mdi = 8'b0000_0001;
        #400 mdi = 8'b0000_0010;
        #400 mdi = 8'b1000_0100;
        #400 mdi = 8'b0000_1000;
        #400 mdi = 8'bzzzz_zzzz;
        #400 mdi = 8'b0000_1000;
        #400 mdi = 8'b0000_1000;
        #400 mdi = 8'b0000_1000;
        #400 mdi = 8'b0000_1000;
        #400 mdi = 8'b0000_1000;
        #200 mdi = 8'b0000_0001;
        #400 mdi = 8'b0000_0010;
        #400 mdi = 8'b1000_0100;
        #400 mdi = 8'b0000_1000;
    end

    initial begin
        clk = 1'b0;
        forever clk = #33.9 ~clk;
    end

    initial begin
        _reset = 0;
        #20 _reset = 1;
    end


    initial begin
        dbi = 8'bzzzz_zzzz;
        #200 dbi = 8'b0000_0001;
        #400 dbi = 8'b0000_0010;
        #400 dbi = 8'b1000_0100;
        #400 dbi = 8'b0000_1000;
        #400 dbi = 8'b0000_1000;
        #400 dbi = 8'bzzzz_zzzz;
        #400 dbi = 8'bzzzz_zzzz;
        #400 dbi = 8'bzzzz_zzzz;
        #400 dbi = 8'bzzzz_zzzz;
        #400 dbi = 8'bzzzz_zzzz;
        #200 dbi = 8'b0000_0001;
        #400 dbi = 8'b0000_0010;
        #400 dbi = 8'b1000_0100;
        #400 dbi = 8'b0000_1000;
    end

    initial begin
        as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 0;
        #200  as = 0;
        #200  as = 0;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
    end

    initial begin
        _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
    end

    initial begin
        ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 1;
        #200  ds = 0;
        #200  ds = 1;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
    end



    initial begin
        a = 4'b0000;
        #10000 a = 4'b1111;
        #10000 a = 4'b0000;
        #10000 a = 4'b1111;
        #10000 a = 4'b0000;
        #10000 a = 4'b1111;
        #10000 a = 4'b0000;
        #10000 a = 4'b1111;
        #10000 a = 4'b0000;
    end

    initial begin
        b = 4'b0000;
        #15000 b = 4'b1111;
        #10000 b = 4'b0000;
        #10000 b = 4'b1111;
        #10000 b = 4'b0000;
        #10000 b = 4'b1111;
        #10000 b = 4'b0000;
        #10000 b = 4'b1111;
        #10000 b = 4'b0000;
    end

endmodule
module crt_top;


    reg             clk, _reset;
    wire            med_res;
    reg     [7:0]   dbi, mdi;
    reg             ds, as, _wr;
    wire    [3:0]   pixel;
	wire  	[7:0]	md;
	wire	[19:0]  ma;
	wire    [7:0]	db;
    reg     [3:0]   a, b;
    reg             hsync, vsync;
    wire            extsyncon;
    
    assign extsyncon = 1;
    assign med_res 	 = 1;  
	assign db = dbi;
    assign md = mdi;

    crt_sys ob_crt_sys( clk, _reset, db, ds, as, _wr, ma, md,  _mcs, _mrd, _mwr, med_res, pixel, sync, a, b, hsync, vsync, extsyncon, int);

    initial begin
        mdi <= 8'bzzzz_zzzz;
        #200 mdi = 8'b0000_0001;
        #400 mdi = 8'b0000_0010;
        #400 mdi = 8'b1000_0100;
        #400 mdi = 8'b0000_1000;
        #400 mdi = 8'bzzzz_zzzz;
        #400 mdi = 8'b0000_1000;
        #400 mdi = 8'b0000_1000;
        #400 mdi = 8'b0000_1000;
        #400 mdi = 8'b0000_1000;
        #400 mdi = 8'b0000_1000;
        #200 mdi = 8'b0000_0001;
        #400 mdi = 8'b0000_0010;
        #400 mdi = 8'b1000_0100;
        #400 mdi = 8'b0000_1000;
    end

    initial begin
        clk = 1'b0;
        forever clk = #33.9 ~clk;
    end

    initial begin
        _reset = 0;
        #20 _reset = 1;
    end


    initial begin
        dbi = 8'bzzzz_zzzz;
        #200 dbi = 8'b0000_0001;
        #400 dbi = 8'b0000_0010;
        #400 dbi = 8'b1000_0100;
        #400 dbi = 8'b0000_1000;
        #400 dbi = 8'b0000_1000;
        #400 dbi = 8'bzzzz_zzzz;
        #400 dbi = 8'bzzzz_zzzz;
        #400 dbi = 8'bzzzz_zzzz;
        #400 dbi = 8'bzzzz_zzzz;
        #400 dbi = 8'bzzzz_zzzz;
        #200 dbi = 8'b0000_0001;
        #400 dbi = 8'b0000_0010;
        #400 dbi = 8'b1000_0100;
        #400 dbi = 8'b0000_1000;
    end

    initial begin
        as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 0;
        #200  as = 0;
        #200  as = 0;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
        #200  as = 1;
        #200  as = 0;
    end

    initial begin
        _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
        #200  _wr = 0;
        #200  _wr = 1;
    end

    initial begin
        ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 1;
        #200  ds = 0;
        #200  ds = 1;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
        #200  ds = 0;
    end



    initial begin
        a = 4'b0000;
        #10000 a = 4'b1111;
        #10000 a = 4'b0000;
        #10000 a = 4'b1111;
        #10000 a = 4'b0000;
        #10000 a = 4'b1111;
        #10000 a = 4'b0000;
        #10000 a = 4'b1111;
        #10000 a = 4'b0000;
    end

    initial begin
        b = 4'b0000;
        #15000 b = 4'b1111;
        #10000 b = 4'b0000;
        #10000 b = 4'b1111;
        #10000 b = 4'b0000;
        #10000 b = 4'b1111;
        #10000 b = 4'b0000;
        #10000 b = 4'b1111;
        #10000 b = 4'b0000;
    end

endmodule