data/full_repos/permissive/137454634/count.v
None: at end of input
1: b'%Warning-MULTITOP: data/full_repos/permissive/137454634/count.v:40: Multiple top level modules\n                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                  : ... Top module \'counter_run\'\nmodule counter_run(endRun,CP,CP_H,StRun);\n       ^~~~~~~~~~~\n                                                                  : ... Top module \'counter_open\'\nmodule counter_open(endOpen,dispStage,CP,StOpen,pause,close);\n       ^~~~~~~~~~~~\n                                                                  : ... Top module \'delaybutton\'\nmodule delaybutton(pause,CP,delay);\n       ^~~~~~~~~~~\n                                                                  : ... Top module \'divideclk\'\nmodule divideclk(clk4hz,clk32hz,StRun,StOpen);\n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module counter_run(endRun,CP,CP_H,StRun);

	input CP,CP_H,StRun;	
	output reg endRun;
	reg [2:0] count;
	
	always @ (posedge CP)
		if(!StRun) begin count <= 3'b000; end
		else
			begin
			if(count==3'd5)
				begin count<=3'd0; end
			else
				begin count<=count+1'd1; end
			end
	always @ (CP_H)
		if(!StRun) begin endRun<=0; end
		else
			begin
			if(count==3'd5)
				begin endRun<=1; end
			else
				begin endRun<=0; end
			end
			
endmodule
module counter_run(endRun,CP,CP_H,StRun);


	input CP,CP_H,StRun;	
	output reg endRun;
	reg [2:0] count;
	
	always @ (posedge CP)
		if(!StRun) begin count <= 3'b000; end
		else
			begin
			if(count==3'd5)
				begin count<=3'd0; end
			else
				begin count<=count+1'd1; end
			end
	always @ (CP_H)
		if(!StRun) begin endRun<=0; end
		else
			begin
			if(count==3'd5)
				begin endRun<=1; end
			else
				begin endRun<=0; end
			end
			
endmodule