data/full_repos/permissive/143278/ivltests/sv_package4.v
 line:5: before: "package"
data/verilator_xmls/f8f08c4b-6bbd-46a0-92ac-ef94029ab6f4.xml
module main;

   import p1::word;

   initial begin
      if ($bits(word) != 16) begin
	 $display("FAILED -- $bits(p1::word) == %0d", $bits(p1::word));
	 $finish;
      end

      word = 'haa55;

      if (word != 'haa55) begin
	 $display("FAILED -- p1::word = %h", word);
	 $finish;
      end

      word.low = 'h66;
      word.high = 'hbb;
      if (word != 'hbb66 || word.low != 8'h66) begin
	 $display("FAILED -- p1::word = %h", word);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end
endmodule
module main;


   import p1::word;

   initial begin
      if ($bits(word) != 16) begin
	 $display("FAILED -- $bits(p1::word) == %0d", $bits(p1::word));
	 $finish;
      end

      word = 'haa55;

      if (word != 'haa55) begin
	 $display("FAILED -- p1::word = %h", word);
	 $finish;
      end

      word.low = 'h66;
      word.high = 'hbb;
      if (word != 'hbb66 || word.low != 8'h66) begin
	 $display("FAILED -- p1::word = %h", word);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end
endmodule