data/full_repos/permissive/218126213/top_tb.v
1: b'%Error: data/full_repos/permissive/218126213/top_tb.v:1: Cannot find include file: global_memory_parameters.v\n`include "global_memory_parameters.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/218126213,data/full_repos/permissive/218126213/global_memory_parameters.v\n             data/full_repos/permissive/218126213,data/full_repos/permissive/218126213/global_memory_parameters.v.v\n             data/full_repos/permissive/218126213,data/full_repos/permissive/218126213/global_memory_parameters.v.sv\n             global_memory_parameters.v\n             global_memory_parameters.v.v\n             global_memory_parameters.v.sv\n             obj_dir/global_memory_parameters.v\n             obj_dir/global_memory_parameters.v.v\n             obj_dir/global_memory_parameters.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10 clk=!clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #65104 SCK=!SCK;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #2604160 S<=1\'b0; #130208\n ^\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #2604160 S<=1\'b0; #130208\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n D<=1\'b1;#130208\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n D<=1\'b0;#130208\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n D<=1\'b0;#130208\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n D<=1\'b1;#130208\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n D<=1\'b1;#130208\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n D<=1\'b1;#130208\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n D<=1\'b1;#130208\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n D<=1\'b1;#130208\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/218126213/top_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n D<=1\'b0;S<=1\'b0;#130208\n                 ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n'
module top_tb();

wire Q;
reg D;
reg SCK;
reg S;
reg RESET;
reg W_ENABLE;
reg clk;

spi_flash_memory uut
(	
	.clk(clk),
	.Q(Q),
	.D(D),
	.SCK(SCK),
	.S(S),
	.RESET(RESET),
	.W_ENABLE(W_ENABLE)
);

initial
begin
	RESET=1'b1;
	W_ENABLE=1'b1;
	SCK=1'b0;
	S=1'b1;
	D=1'b0;
	clk=1'b0;
end

always
begin
	#10 clk=!clk;
end

always
begin
	#65104 SCK=!SCK;
end	
	
always @ (negedge SCK)
begin
	#2604160 S<=1'b0; #130208
	D<=1'b1;#130208
	D<=1'b0;#130208
	D<=1'b0;#130208
	D<=1'b1;#130208
	D<=1'b1;#130208
	D<=1'b1;#130208
	D<=1'b1;#130208
	D<=1'b1;#130208
	D<=1'b0;S<=1'b0;#130208
	S<=1'b0;
end

endmodule
module top_tb();


wire Q;
reg D;
reg SCK;
reg S;
reg RESET;
reg W_ENABLE;
reg clk;

spi_flash_memory uut
(	
	.clk(clk),
	.Q(Q),
	.D(D),
	.SCK(SCK),
	.S(S),
	.RESET(RESET),
	.W_ENABLE(W_ENABLE)
);

initial
begin
	RESET=1'b1;
	W_ENABLE=1'b1;
	SCK=1'b0;
	S=1'b1;
	D=1'b0;
	clk=1'b0;
end

always
begin
	#10 clk=!clk;
end

always
begin
	#65104 SCK=!SCK;
end	
	
always @ (negedge SCK)
begin
	#2604160 S<=1'b0; #130208
	D<=1'b1;#130208
	D<=1'b0;#130208
	D<=1'b0;#130208
	D<=1'b1;#130208
	D<=1'b1;#130208
	D<=1'b1;#130208
	D<=1'b1;#130208
	D<=1'b1;#130208
	D<=1'b0;S<=1'b0;#130208
	S<=1'b0;
end

endmodule