data/full_repos/permissive/165490876/src/synth/ControlInterface.v
1: b'%Warning-WIDTH: data/full_repos/permissive/165490876/src/synth/ControlInterface.v:37: Operator OR expects 12 bits on the RHS, but RHS\'s VARREF \'MOSI\' generates 1 bits.\n                                                                                    : ... In instance ControlInterface\n   shiftRegister <= (shiftRegister << 1 | MOSI);\n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ControlInterface  #(parameter ADDR_BITS = 4, parameter DATA_BITS = 8)(
  output [DATA_BITS-1 : 0] controlWord,
  output [ADDR_BITS-1 : 0] controlAddress,
  output wire controlReady,
  input wire SCLK,
  input wire MOSI,
  input wire SS   
);
	parameter REGISTER_SIZE = ADDR_BITS + DATA_BITS;
	
	reg [REGISTER_SIZE-1 : 0] shiftRegister;
	reg [REGISTER_SIZE-1 : 0] outputRegister;
	

	always @(posedge SCLK) begin
		if (SS == 1) begin			
			shiftRegister <= (shiftRegister << 1 | MOSI);
		end
	end


	always @(negedge SS) begin
	  outputRegister <= shiftRegister;	  
	end

	assign controlReady = SS;
	assign controlAddress = outputRegister[REGISTER_SIZE-1 -: ADDR_BITS];
	assign controlWord  = outputRegister[DATA_BITS-1 : 0];
	
endmodule
module ControlInterface  #(parameter ADDR_BITS = 4, parameter DATA_BITS = 8)(
  output [DATA_BITS-1 : 0] controlWord,
  output [ADDR_BITS-1 : 0] controlAddress,
  output wire controlReady,
  input wire SCLK,
  input wire MOSI,
  input wire SS   
);

	parameter REGISTER_SIZE = ADDR_BITS + DATA_BITS;
	
	reg [REGISTER_SIZE-1 : 0] shiftRegister;
	reg [REGISTER_SIZE-1 : 0] outputRegister;
	

	always @(posedge SCLK) begin
		if (SS == 1) begin			
			shiftRegister <= (shiftRegister << 1 | MOSI);
		end
	end


	always @(negedge SS) begin
	  outputRegister <= shiftRegister;	  
	end

	assign controlReady = SS;
	assign controlAddress = outputRegister[REGISTER_SIZE-1 -: ADDR_BITS];
	assign controlWord  = outputRegister[DATA_BITS-1 : 0];
	
endmodule