data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog/wb_ram_xilinx_bank.v
1: b'%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog/wb_ram_xilinx_bank.v:31: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s COND generates 16 bits.\n                                                                                                   : ... In instance wb_ram_xilinx_bank\n   wire [14:0]       address = (|we & bank_select) ? waddr : raddr;\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog/wb_ram_xilinx_bank.v:43: Cannot find file containing module: \'RAMB16_S9\'\n   RAMB16_S9 ram0(\n   ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog,data/full_repos/permissive/175132042/RAMB16_S9\n             data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog,data/full_repos/permissive/175132042/RAMB16_S9.v\n             data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog,data/full_repos/permissive/175132042/RAMB16_S9.sv\n             RAMB16_S9\n             RAMB16_S9.v\n             RAMB16_S9.sv\n             obj_dir/RAMB16_S9\n             obj_dir/RAMB16_S9.v\n             obj_dir/RAMB16_S9.sv\n%Error: data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog/wb_ram_xilinx_bank.v:55: Cannot find file containing module: \'RAMB16_S9\'\n   RAMB16_S9 ram1(\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog/wb_ram_xilinx_bank.v:67: Cannot find file containing module: \'RAMB16_S9\'\n   RAMB16_S9 ram2(\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/175132042/rtl/wb_ram/rtl/verilog/wb_ram_xilinx_bank.v:79: Cannot find file containing module: \'RAMB16_S9\'\n   RAMB16_S9 ram3(\n   ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module wb_ram_xilinx_bank (

   dout,

   clk, rst, we, din, waddr, raddr, bank_select
   ) ;

   input clk;
   input rst;   
   input [3:0] we;
   input [31:0] din;
   input [15:0] waddr;
   input [15:0] raddr;
   input wire   bank_select;
   
   output wire [31:0] dout;




   wire [14:0]       address = (|we & bank_select) ? waddr : raddr;
   



   wire [3:0]        enable = {4{bank_select}};


`ifndef XILINX_RAMB16_S9



   RAMB16_S9 ram0(
		          .DO(dout[7:0]), 
		          .DOP(), 
		          .ADDR(address[10:0]), 
		          .CLK(clk),
		          .DI(din[7:0]), 
		          .DIP(1'b0), 
		          .EN(enable[0]), 
		          .SSR(rst), 
		          .WE(we[0])
		          );

   RAMB16_S9 ram1(
		          .DO(dout[15:8]), 
		          .DOP(), 
		          .ADDR(address[10:0]), 
		          .CLK(clk),
		          .DI(din[15:8]), 
		          .DIP(1'b0), 
		          .EN(enable[1]), 
		          .SSR(rst), 
		          .WE(we[1])
		          );
   
   RAMB16_S9 ram2(
		          .DO(dout[23:16]), 
		          .DOP(), 
		          .ADDR(address[10:0]), 
		          .CLK(clk),
		          .DI(din[23:16]), 
		          .DIP(1'b0), 
		          .EN(enable[2]), 
		          .SSR(rst), 
		          .WE(we[2])
		          );
   
   RAMB16_S9 ram3(
		          .DO(dout[31:24]), 
		          .DOP(), 
		          .ADDR(address[10:0]), 
		          .CLK(clk),
		          .DI(din[31:24]), 
		          .DIP(1'b0), 
		          .EN(enable[3]), 
		          .SSR(rst), 
		          .WE(we[3])
		          );
`else
   wire              VSS = 1'b0;
   wire              VDD = 1'b1;
   
   RAMB36E1 #(.READ_WIDTH_A(36), .RAM_MODE(SDP))
   ram0(
        .CASCADEOUTA(), 
        .CASCADEOUTB(), 
        .DBITERR(VSS), 
        .DOADO(dout), 
        .DOBDO(), 
        .DOPADOP(), 
        .DOPBDOP(), 
        .ECCPARITY(), 
        .RDADDRECC(), 
        .SBITERR(), 
		.ADDRARDADDR(), 
        .ADDRBWRADDR(), 
        .CASCADEINA(), 
        .CASCADEINB(), 
        .CLKARDCLK(clk), 
        .CLKBWRCLK(clk), 
        .DIADI(din), 
        .DIBDI(), 
        .DIPADIP(), 
        .DIPBDIP(), 
        .ENARDEN(VDD), 
        .ENBWREN(VSS), 
        .INJECTDBITERR(VSS), 
        .INJECTSBITERR(VSS), 
        .REGCEAREGCE(VSS), 
        .REGCEB(VSS), 
        .RSTRAMARSTRAM(rst), 
        .RSTRAMB(rst), 
        .RSTREGARSTREG(rst), 
        .RSTREGB(rst), 
        .WEA(we), 
        .WEBWE({8{VSS}})
        
        );   
`endif
   
   
endmodule
module wb_ram_xilinx_bank (

   dout,

   clk, rst, we, din, waddr, raddr, bank_select
   ) ;


   input clk;
   input rst;   
   input [3:0] we;
   input [31:0] din;
   input [15:0] waddr;
   input [15:0] raddr;
   input wire   bank_select;
   
   output wire [31:0] dout;




   wire [14:0]       address = (|we & bank_select) ? waddr : raddr;
   



   wire [3:0]        enable = {4{bank_select}};


`ifndef XILINX_RAMB16_S9



   RAMB16_S9 ram0(
		          .DO(dout[7:0]), 
		          .DOP(), 
		          .ADDR(address[10:0]), 
		          .CLK(clk),
		          .DI(din[7:0]), 
		          .DIP(1'b0), 
		          .EN(enable[0]), 
		          .SSR(rst), 
		          .WE(we[0])
		          );

   RAMB16_S9 ram1(
		          .DO(dout[15:8]), 
		          .DOP(), 
		          .ADDR(address[10:0]), 
		          .CLK(clk),
		          .DI(din[15:8]), 
		          .DIP(1'b0), 
		          .EN(enable[1]), 
		          .SSR(rst), 
		          .WE(we[1])
		          );
   
   RAMB16_S9 ram2(
		          .DO(dout[23:16]), 
		          .DOP(), 
		          .ADDR(address[10:0]), 
		          .CLK(clk),
		          .DI(din[23:16]), 
		          .DIP(1'b0), 
		          .EN(enable[2]), 
		          .SSR(rst), 
		          .WE(we[2])
		          );
   
   RAMB16_S9 ram3(
		          .DO(dout[31:24]), 
		          .DOP(), 
		          .ADDR(address[10:0]), 
		          .CLK(clk),
		          .DI(din[31:24]), 
		          .DIP(1'b0), 
		          .EN(enable[3]), 
		          .SSR(rst), 
		          .WE(we[3])
		          );
`else
   wire              VSS = 1'b0;
   wire              VDD = 1'b1;
   
   RAMB36E1 #(.READ_WIDTH_A(36), .RAM_MODE(SDP))
   ram0(
        .CASCADEOUTA(), 
        .CASCADEOUTB(), 
        .DBITERR(VSS), 
        .DOADO(dout), 
        .DOBDO(), 
        .DOPADOP(), 
        .DOPBDOP(), 
        .ECCPARITY(), 
        .RDADDRECC(), 
        .SBITERR(), 
		.ADDRARDADDR(), 
        .ADDRBWRADDR(), 
        .CASCADEINA(), 
        .CASCADEINB(), 
        .CLKARDCLK(clk), 
        .CLKBWRCLK(clk), 
        .DIADI(din), 
        .DIBDI(), 
        .DIPADIP(), 
        .DIPBDIP(), 
        .ENARDEN(VDD), 
        .ENBWREN(VSS), 
        .INJECTDBITERR(VSS), 
        .INJECTSBITERR(VSS), 
        .REGCEAREGCE(VSS), 
        .REGCEB(VSS), 
        .RSTRAMARSTRAM(rst), 
        .RSTRAMB(rst), 
        .RSTREGARSTREG(rst), 
        .RSTREGB(rst), 
        .WEA(we), 
        .WEBWE({8{VSS}})
        
        );   
`endif
   
   
endmodule