data/full_repos/permissive/133819542/src/pc_reg.v
1: b'%Error: data/full_repos/permissive/133819542/src/pc_reg.v:9: Cannot find include file: const.v\n`include "const.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v.v\n             data/full_repos/permissive/133819542/src,data/full_repos/permissive/133819542/const.v.sv\n             const.v\n             const.v.v\n             const.v.sv\n             obj_dir/const.v\n             obj_dir/const.v.v\n             obj_dir/const.v.sv\n%Error: data/full_repos/permissive/133819542/src/pc_reg.v:14: Define or directive not defined: \'`StallBus\'\n    input wire  [`StallBus   ]    stall          ,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/pc_reg.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire  [`StallBus   ]    stall          ,\n                             ^\n%Error: data/full_repos/permissive/133819542/src/pc_reg.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire  [`RegBus     ]    branch_addr_i  ,\n    ^~~~~\n%Error: data/full_repos/permissive/133819542/src/pc_reg.v:16: Define or directive not defined: \'`RegBus\'\n    input wire  [`RegBus     ]    branch_addr_i  ,\n                 ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/pc_reg.v:17: Define or directive not defined: \'`InstAddrBus\'\n    output reg  [`InstAddrBus]    pc             ,\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/pc_reg.v:22: Define or directive not defined: \'`RESET_ENABLE\'\n        if(rst == `RESET_ENABLE) begin \n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/pc_reg.v:23: Define or directive not defined: \'`CHIP_DISABLE\'\n            ce <= `CHIP_DISABLE;\n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/pc_reg.v:25: Define or directive not defined: \'`CHIP_ENABLE\'\n            ce <= `CHIP_ENABLE;\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/pc_reg.v:30: Define or directive not defined: \'`CHIP_DISABLE\'\n        if(ce == `CHIP_DISABLE) begin\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133819542/src/pc_reg.v:32: Define or directive not defined: \'`NOSTOP\'\n        end else if (stall[0] == `NOSTOP) begin            \n                                 ^~~~~~~\n%Error: data/full_repos/permissive/133819542/src/pc_reg.v:33: Define or directive not defined: \'`BRANCH\'\n                if(branch_flag_i == `BRANCH)               \n                                    ^~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module pc_reg (
    input wire                    clk            ,
    input wire                    rst            ,
    input wire  [`StallBus   ]    stall          ,
    input wire                    branch_flag_i  ,
    input wire  [`RegBus     ]    branch_addr_i  ,
    output reg  [`InstAddrBus]    pc             ,
    output reg                    ce
);

    always @(posedge clk) begin
        if(rst == `RESET_ENABLE) begin 
            ce <= `CHIP_DISABLE;
        end else begin 
            ce <= `CHIP_ENABLE;
        end
    end

    always @(posedge clk) begin
        if(ce == `CHIP_DISABLE) begin
            pc <= 0;
        end else if (stall[0] == `NOSTOP) begin
                if(branch_flag_i == `BRANCH)
                    pc <= branch_addr_i;
                else pc <= pc + 4;
        end
    end
endmodule
module pc_reg (
    input wire                    clk            ,
    input wire                    rst            ,
    input wire  [`StallBus   ]    stall          ,
    input wire                    branch_flag_i  ,
    input wire  [`RegBus     ]    branch_addr_i  ,
    output reg  [`InstAddrBus]    pc             ,
    output reg                    ce
);


    always @(posedge clk) begin
        if(rst == `RESET_ENABLE) begin 
            ce <= `CHIP_DISABLE;
        end else begin 
            ce <= `CHIP_ENABLE;
        end
    end

    always @(posedge clk) begin
        if(ce == `CHIP_DISABLE) begin
            pc <= 0;
        end else if (stall[0] == `NOSTOP) begin
                if(branch_flag_i == `BRANCH)
                    pc <= branch_addr_i;
                else pc <= pc + 4;
        end
    end
endmodule