data/full_repos/permissive/2084115/projects/zybo_vga/rtl/zybo_sw.v
data/verilator_xmls/8760c458-20a2-4d5c-8f7d-832bf574f4d5.xml
module zybo_sw
        (
            input   wire            in_clk125,
            
            output  wire            vga_hsync,
            output  wire            vga_vsync,
            output  wire    [4:0]   vga_r,
            output  wire    [5:0]   vga_g,
            output  wire    [4:0]   vga_b,
            
            input   wire    [3:0]   push_sw,
            input   wire    [3:0]   dip_sw,
            output  wire    [3:0]   led
        );
    
    
    assign led = dip_sw ^ push_sw;
    
    
endmodule
module zybo_sw
        (
            input   wire            in_clk125,
            
            output  wire            vga_hsync,
            output  wire            vga_vsync,
            output  wire    [4:0]   vga_r,
            output  wire    [5:0]   vga_g,
            output  wire    [4:0]   vga_b,
            
            input   wire    [3:0]   push_sw,
            input   wire    [3:0]   dip_sw,
            output  wire    [3:0]   led
        );

    
    
    assign led = dip_sw ^ push_sw;
    
    
endmodule