data/full_repos/permissive/136660017/tut-01-modules.v
1: b'%Error: data/full_repos/permissive/136660017/tut-01-modules.v:17: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,bench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/136660017/tut-01-modules.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136660017/tut-01-modules.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/136660017/tut-01-modules.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bench;
  reg in;
  wire out1,out2;

  inv1 x1(out1,in);
  inv2 x2(out2,in);

  initial begin
    $dumpvars(0,bench);
    #5;
    in=0;
    #5;
    in=1;
    #5;
    $finish;
  end
endmodule
module bench;

  reg in;
  wire out1,out2;

  inv1 x1(out1,in);
  inv2 x2(out2,in);

  initial begin
    $dumpvars(0,bench);
    #5;
    in=0;
    #5;
    in=1;
    #5;
    $finish;
  end
endmodule