data/full_repos/permissive/159823067/omercevik_hw2_32bitalu_verilog_files/mux2to1.v
data/verilator_xmls/cc62618d-07b7-418c-b76a-bef6d2afd63d.xml
module mux2to1(out,i1,i0,s);
    output out;
    input i1,i0,s;
	 wire u,m,n;
    not (u,s);
    and (m,s,i1);
    and (n,u,i0);
    or (out,m,n);
endmodule
module mux2to1(out,i1,i0,s);

    output out;
    input i1,i0,s;
	 wire u,m,n;
    not (u,s);
    and (m,s,i1);
    and (n,u,i0);
    or (out,m,n);
endmodule