data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/mux2.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/mux2.v:65: Multiple top level modules\n                                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                             : ... Top module \'MUX2\'\nmodule MUX2(\n       ^~~~\n                                                                                                             : ... Top module \'CARRY_MUX2\'\nmodule CARRY_MUX2(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module CARRY_MUX2(
	input [0:0] A0,
	input [0:0] A1,
	input [0:0] S,
	output [0:0] Y
	);
  
	assign Y = S ? A1 : A0;





endmodule
module CARRY_MUX2(
	input [0:0] A0,
	input [0:0] A1,
	input [0:0] S,
	output [0:0] Y
	);

  
	assign Y = S ? A1 : A0;





endmodule