data/full_repos/permissive/216210370/soc/rtc.v
1: b"%Error: data/full_repos/permissive/216210370/soc/rtc.v:892: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.v\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:510: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:469: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:409: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:197: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module rtc_clr_sync(
  pclk,
  pdu_aou_wen_clr_sync,
  presetn,
  rtc_clk,
  test_mode,
  wen_clr
);
input        pclk;                
input        presetn;             
input        rtc_clk;             
input        test_mode;           
input        wen_clr;             
output       pdu_aou_wen_clr_sync; 
reg          pclk_load_sync1;     
reg          pclk_load_sync2;     
reg          rtc_load_sync1;      
reg          rtc_load_sync2;      
reg          wen_clr_hold;        
wire         gate_en;             
wire         load_done;           
wire         pclk;                
wire         pclk_sync;           
wire         pdu_aou_wen_clr_sync; 
wire         presetn;             
wire         rtc_clk;             
wire         test_mode;           
wire         wen_clr;             
assign gate_en = wen_clr | wen_clr_hold | pclk_load_sync2;
gated_clk_cell  gatecell (
  .clk_in               (pclk                ),
  .clk_out              (pclk_sync           ),
  .external_en          (gate_en             ),
  .global_en            (1'b0                ),
  .local_en             (1'b0                ),
  .module_en            (1'b0                ),
  .pad_yy_gate_clk_en_b (1'b0                ),
  .pad_yy_test_mode     (test_mode           )
);
 always @(posedge pclk_sync or negedge presetn)
 begin
   if(~presetn)
     begin
       wen_clr_hold <= 1'b0;
     end
   else if(load_done)
     begin
       wen_clr_hold <= 1'b0;
     end
   else if(wen_clr)
     begin
       wen_clr_hold <= 1'b1;
     end
 end
 always @(posedge rtc_clk or negedge presetn)
 begin
   if(~presetn)
     begin
       rtc_load_sync1 <= 1'b0;
       rtc_load_sync2 <= 1'b0;
     end
   else
     begin
       rtc_load_sync1 <= wen_clr_hold;
       rtc_load_sync2 <= rtc_load_sync1;
     end
 end
 always @(posedge pclk_sync or negedge presetn)
 begin
   if(~presetn)
     begin
       pclk_load_sync1 <= 1'b0;
       pclk_load_sync2 <= 1'b0;
     end
   else
     begin
       pclk_load_sync1 <= rtc_load_sync2;
       pclk_load_sync2 <= pclk_load_sync1;
     end
 end
assign load_done = pclk_load_sync2;
assign pdu_aou_wen_clr_sync = rtc_load_sync2;
endmodule
module rtc_clr_sync(
  pclk,
  pdu_aou_wen_clr_sync,
  presetn,
  rtc_clk,
  test_mode,
  wen_clr
);

input        pclk;                
input        presetn;             
input        rtc_clk;             
input        test_mode;           
input        wen_clr;             
output       pdu_aou_wen_clr_sync; 
reg          pclk_load_sync1;     
reg          pclk_load_sync2;     
reg          rtc_load_sync1;      
reg          rtc_load_sync2;      
reg          wen_clr_hold;        
wire         gate_en;             
wire         load_done;           
wire         pclk;                
wire         pclk_sync;           
wire         pdu_aou_wen_clr_sync; 
wire         presetn;             
wire         rtc_clk;             
wire         test_mode;           
wire         wen_clr;             
assign gate_en = wen_clr | wen_clr_hold | pclk_load_sync2;
gated_clk_cell  gatecell (
  .clk_in               (pclk                ),
  .clk_out              (pclk_sync           ),
  .external_en          (gate_en             ),
  .global_en            (1'b0                ),
  .local_en             (1'b0                ),
  .module_en            (1'b0                ),
  .pad_yy_gate_clk_en_b (1'b0                ),
  .pad_yy_test_mode     (test_mode           )
);
 always @(posedge pclk_sync or negedge presetn)
 begin
   if(~presetn)
     begin
       wen_clr_hold <= 1'b0;
     end
   else if(load_done)
     begin
       wen_clr_hold <= 1'b0;
     end
   else if(wen_clr)
     begin
       wen_clr_hold <= 1'b1;
     end
 end
 always @(posedge rtc_clk or negedge presetn)
 begin
   if(~presetn)
     begin
       rtc_load_sync1 <= 1'b0;
       rtc_load_sync2 <= 1'b0;
     end
   else
     begin
       rtc_load_sync1 <= wen_clr_hold;
       rtc_load_sync2 <= rtc_load_sync1;
     end
 end
 always @(posedge pclk_sync or negedge presetn)
 begin
   if(~presetn)
     begin
       pclk_load_sync1 <= 1'b0;
       pclk_load_sync2 <= 1'b0;
     end
   else
     begin
       pclk_load_sync1 <= rtc_load_sync2;
       pclk_load_sync2 <= pclk_load_sync1;
     end
 end
assign load_done = pclk_load_sync2;
assign pdu_aou_wen_clr_sync = rtc_load_sync2;
endmodule