data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v:1: Cannot find include file: jk.v\n`include "jk.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/jk.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/jk.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/jk.v.sv\n             jk.v\n             jk.v.v\n             jk.v.sv\n             obj_dir/jk.v\n             obj_dir/jk.v.v\n             obj_dir/jk.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v:14: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("jk_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v:15: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,jk_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    j<= 0; k<= 0; #10;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    j<= 0; k<= 1; #10;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    j<= 1; k<= 0; #10;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    j<= 1; k<= 1; #10;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    j<= 0; k<= 0; #10;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    j<= 0; k<= 1; #10;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    j<= 1; k<= 0; #10;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/202237519/verilog/digitalsystem6/jk_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    j<= 1; k<= 1; #10;\n                  ^\n%Error: Exiting due to 3 error(s), 9 warning(s)\n'
module jk_tb;

reg clk, set, j, k;
wire Q, nQ;


always #2.5 clk <= ~clk;

 JK_FF jk_ff(clk,set,j,k,Q,nQ);

initial begin
    $dumpfile("jk_tb.vcd");
    $dumpvars(0,jk_tb);
    clk <= 1; set <= 0;
    j<= 0; k<= 0; #10;
    j<= 0; k<= 1; #10;
    j<= 1; k<= 0; #10;
    j<= 1; k<= 1; #10;
    j<= 0; k<= 0; #10;
    j<= 0; k<= 1; #10;
    j<= 1; k<= 0; #10;
    j<= 1; k<= 1; #10;
    $finish;
    end


endmodule
module jk_tb;


reg clk, set, j, k;
wire Q, nQ;


always #2.5 clk <= ~clk;

 JK_FF jk_ff(clk,set,j,k,Q,nQ);

initial begin
    $dumpfile("jk_tb.vcd");
    $dumpvars(0,jk_tb);
    clk <= 1; set <= 0;
    j<= 0; k<= 0; #10;
    j<= 0; k<= 1; #10;
    j<= 1; k<= 0; #10;
    j<= 1; k<= 1; #10;
    j<= 0; k<= 0; #10;
    j<= 0; k<= 1; #10;
    j<= 1; k<= 0; #10;
    j<= 1; k<= 1; #10;
    $finish;
    end


endmodule