data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v
 line:116: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#10 rst = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n#10 rst = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #10 cs = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #20 address = address + 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #10 cs = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #20 address = address +1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #10 cs = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n           #20 address = address + 1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n           #10 address = address + 1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #10 address = address + 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n     #50;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n    #10 cs = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n           #20 address = address + 1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n#100 $finish;\n^\n%Error: data/full_repos/permissive/18770871/memory/phase2_unified/memory_tb.v:17: Cannot find file containing module: \'memory\'\nmemory m0 (\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18770871/memory/phase2_unified,data/full_repos/permissive/18770871/memory\n             data/full_repos/permissive/18770871/memory/phase2_unified,data/full_repos/permissive/18770871/memory.v\n             data/full_repos/permissive/18770871/memory/phase2_unified,data/full_repos/permissive/18770871/memory.sv\n             memory\n             memory.v\n             memory.sv\n             obj_dir/memory\n             obj_dir/memory.v\n             obj_dir/memory.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_tb;
parameter ASIZE=16;
parameter DSIZE=16;
reg clk;
reg rst;
reg cs;
reg wen;
reg [ASIZE-1:0] address;
reg [DSIZE-1:0] data_in;
reg [3:0] fileid;
wire [DSIZE-1:0] data_out;

`define TEST_LIMIT 20

memory m0 (
  .clk(clk),
  .rst(rst),
  .cs(cs),
  .wen(wen),
  .addr(address),
  .data_in(data_in),
  .fileid(fileid),
  .data_out(data_out)
);

integer i;


always #5 clk = ~clk;

initial
  begin
    clk = 0; rst = 0; fileid = 0;
    wen = 1;
    cs = 0;
    data_in=16'hFFFF;
    address = 0;
#10 rst = 1;
#10 rst = 0;




    for (i = 0; i < 20; i = i + 1)
        begin
	   cs = 1;
	   $write("%0dns: Data[%h] = ",$time,address);
	   #10 cs = 0;
	   #20 address = address + 1;
           $write("%h\n", data_out);
        end
    address = 0;
    wen = 0;
    #50;


    for(i=0; i < `TEST_LIMIT; i = i + 1)
	begin
		cs = 1;
		$write("%0dns: Write Data %h to Address %h\n",$time, data_in, address);
		#10 cs = 0;
		#20 address = address +1;
		data_in = data_in -1;
	end

    address = 0;
    wen =1 ;
    #50;
    for (i = 0; i < `TEST_LIMIT; i = i + 1)
        begin
	   cs = 1;
           $write("%0dns: Data[%h] = ",$time,address);
	   #10 cs = 0;
           #20 address = address + 1;
           $write("%h\n", data_out);
        end
    address = 0;
    #50;

        for (i = 0; i < `TEST_LIMIT; i = i + 1)
        begin
	   cs = 1;
           $write("%0dns: Data[%h] = ",$time,address);
           #10 address = address + 1;
           $write("%h\n", data_out);
        end
    address = 0;
    data_in = 16'h00FF;
    cs = 0;

    #50;
    wen = 0; 
    for (i = 0; i < `TEST_LIMIT; i = i + 1)
        begin
	   cs = 1;
           $write("%0dns: Write Data %h to Address %h\n",$time, data_in, address);
	   #10 address = address + 1;
               data_in = data_in - 1;
        end
     cs = 0;
     #50;
     address = 0;
     wen = 1;

    for (i = 0; i < `TEST_LIMIT; i = i + 1)
        begin
	   cs = 1;
           $write("%0dns: Data[%h] = ",$time,address);
	   #10 cs = 0;
           #20 address = address + 1;
           $write("%h\n", data_out);
        end

#100 $finish;
  end

endmodule
module memory_tb;

parameter ASIZE=16;
parameter DSIZE=16;
reg clk;
reg rst;
reg cs;
reg wen;
reg [ASIZE-1:0] address;
reg [DSIZE-1:0] data_in;
reg [3:0] fileid;
wire [DSIZE-1:0] data_out;

`define TEST_LIMIT 20

memory m0 (
  .clk(clk),
  .rst(rst),
  .cs(cs),
  .wen(wen),
  .addr(address),
  .data_in(data_in),
  .fileid(fileid),
  .data_out(data_out)
);

integer i;


always #5 clk = ~clk;

initial
  begin
    clk = 0; rst = 0; fileid = 0;
    wen = 1;
    cs = 0;
    data_in=16'hFFFF;
    address = 0;
#10 rst = 1;
#10 rst = 0;




    for (i = 0; i < 20; i = i + 1)
        begin
	   cs = 1;
	   $write("%0dns: Data[%h] = ",$time,address);
	   #10 cs = 0;
	   #20 address = address + 1;
           $write("%h\n", data_out);
        end
    address = 0;
    wen = 0;
    #50;


    for(i=0; i < `TEST_LIMIT; i = i + 1)
	begin
		cs = 1;
		$write("%0dns: Write Data %h to Address %h\n",$time, data_in, address);
		#10 cs = 0;
		#20 address = address +1;
		data_in = data_in -1;
	end

    address = 0;
    wen =1 ;
    #50;
    for (i = 0; i < `TEST_LIMIT; i = i + 1)
        begin
	   cs = 1;
           $write("%0dns: Data[%h] = ",$time,address);
	   #10 cs = 0;
           #20 address = address + 1;
           $write("%h\n", data_out);
        end
    address = 0;
    #50;

        for (i = 0; i < `TEST_LIMIT; i = i + 1)
        begin
	   cs = 1;
           $write("%0dns: Data[%h] = ",$time,address);
           #10 address = address + 1;
           $write("%h\n", data_out);
        end
    address = 0;
    data_in = 16'h00FF;
    cs = 0;

    #50;
    wen = 0; 
    for (i = 0; i < `TEST_LIMIT; i = i + 1)
        begin
	   cs = 1;
           $write("%0dns: Write Data %h to Address %h\n",$time, data_in, address);
	   #10 address = address + 1;
               data_in = data_in - 1;
        end
     cs = 0;
     #50;
     address = 0;
     wen = 1;

    for (i = 0; i < `TEST_LIMIT; i = i + 1)
        begin
	   cs = 1;
           $write("%0dns: Data[%h] = ",$time,address);
	   #10 cs = 0;
           #20 address = address + 1;
           $write("%h\n", data_out);
        end

#100 $finish;
  end

endmodule