data/full_repos/permissive/143278/vhdl_tests/pr2281519.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/vhdl_tests/pr2281519.v:6: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 10 bits.\n                                                                          : ... In instance test\n     lowp2_out <= ( {lowp2_tmp[8], lowp2_tmp} ) >> 1;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module test();
   wire clk;
   reg  [8:0]	lowp2_tmp;
   reg  [8:0]	lowp2_out;
  always @(posedge clk) begin
     lowp2_out <= ( {lowp2_tmp[8], lowp2_tmp} ) >> 1;
  end
endmodule
module test();

   wire clk;
   reg  [8:0]	lowp2_tmp;
   reg  [8:0]	lowp2_out;
  always @(posedge clk) begin
     lowp2_out <= ( {lowp2_tmp[8], lowp2_tmp} ) >> 1;
  end
endmodule