data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/loopback/loopback.v
None: at end of input
1: b'%Error: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/loopback/loopback.v:1: Cannot find include file: common.vh\n`include "common.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/loopback,data/full_repos/permissive/150133337/common.vh\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/loopback,data/full_repos/permissive/150133337/common.vh.v\n             data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/loopback,data/full_repos/permissive/150133337/common.vh.sv\n             common.vh\n             common.vh.v\n             common.vh.sv\n             obj_dir/common.vh\n             obj_dir/common.vh.v\n             obj_dir/common.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module loopback #(



  parameter integer AXI_DATA_W       = 64
) (



  input  wire                                         clk,
  input  wire                                         reset,

  input  wire                                         stream_read_ready,
  output wire                                         stream_read_req,
  input  wire  [ AXI_DATA_W           -1 : 0 ]        stream_read_data,

  input  wire                                         buffer_read_ready,
  output wire                                         buffer_read_req,
  input  wire  [ AXI_DATA_W           -1 : 0 ]        buffer_read_data,

  input  wire                                         stream_write_ready,
  output wire                                         stream_write_req,
  output wire  [ AXI_DATA_W           -1 : 0 ]        stream_write_data
);



  reg stream_read_req_d;
  reg stream_read_req_dd;
  reg [AXI_DATA_W-1:0] stream_read_data_d;



  always @(posedge clk)
  begin
    if (reset) begin
      stream_read_req_d <= 1'b0;
      stream_read_data_d <= 'b0;
    end else begin
      stream_read_req_d <= stream_read_req;
      stream_read_data_d <= stream_read_data;
    end
  end


  assign stream_read_req = stream_read_ready && stream_write_ready;
  assign stream_write_req = stream_read_req_d;
  assign stream_write_data = stream_read_data;


  assign buffer_read_req = buffer_read_ready;


endmodule
module loopback #(



  parameter integer AXI_DATA_W       = 64
) (



  input  wire                                         clk,
  input  wire                                         reset,

  input  wire                                         stream_read_ready,
  output wire                                         stream_read_req,
  input  wire  [ AXI_DATA_W           -1 : 0 ]        stream_read_data,

  input  wire                                         buffer_read_ready,
  output wire                                         buffer_read_req,
  input  wire  [ AXI_DATA_W           -1 : 0 ]        buffer_read_data,

  input  wire                                         stream_write_ready,
  output wire                                         stream_write_req,
  output wire  [ AXI_DATA_W           -1 : 0 ]        stream_write_data
);




  reg stream_read_req_d;
  reg stream_read_req_dd;
  reg [AXI_DATA_W-1:0] stream_read_data_d;



  always @(posedge clk)
  begin
    if (reset) begin
      stream_read_req_d <= 1'b0;
      stream_read_data_d <= 'b0;
    end else begin
      stream_read_req_d <= stream_read_req;
      stream_read_data_d <= stream_read_data;
    end
  end


  assign stream_read_req = stream_read_ready && stream_write_ready;
  assign stream_write_req = stream_read_req_d;
  assign stream_write_data = stream_read_data;


  assign buffer_read_req = buffer_read_ready;


endmodule