data/full_repos/permissive/143278/ivltests/modparam.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:131: Unsupported: Ignoring delay on this delayed statement.\n    #3;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:138: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:141: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/modparam.v:158: Unsupported: Ignoring delay on this delayed statement.\nalways #(5) clk = ~clk;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/modparam.v:134: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                         : ... In instance top\n    din = 32\'b0_00;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/modparam.v:137: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                         : ... In instance top\n    din = 32\'h1;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/modparam.v:140: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h2\' generates 32 bits.\n                                                                         : ... In instance top\n    din = 32\'h2;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/modparam.v:143: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3\' generates 32 bits.\n                                                                         : ... In instance top\n    din = 32\'h3;\n        ^\n%Error: Exiting due to 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory(clk, we, addr, din,  dout);

parameter WIDTH=8;

input			clk;
input			we;
input [1:0]		addr;
input [WIDTH-1:0]	din;

output [WIDTH-1:0]	dout;
reg    [WIDTH-1:0]	dout;

wire    [WIDTH-1:0]	dout0,dout1,dout2,dout3;
reg			we0,we1,we2,we3;

reg32 #(WIDTH) reg0 (.clk(clk),.we(we0),.din(din[WIDTH-1:0]),
                     .dout(dout0[WIDTH-1:0]));
reg32 #(WIDTH) reg1 (.clk(clk),.we(we1),.din(din[WIDTH-1:0]),
                     .dout(dout1[WIDTH-1:0]));
reg32 #(WIDTH) reg2 (.clk(clk),.we(we2),.din(din[WIDTH-1:0]),
                     .dout(dout2[WIDTH-1:0]));
reg32 #(WIDTH) reg3 (.clk(clk),.we(we3),.din(din[WIDTH-1:0]),
                     .dout(dout3[WIDTH-1:0]));




always @(addr or we)
   case (addr)
      2'b00: begin
               we0 = we;
               we1 = 0;
               we2 = 0;
               we3 = 0;
             end
      2'b01: begin
               we0 = 0;
               we1 = we;
               we2 = 0;
               we3 = 0;
             end
      2'b10: begin
               we0 = 0;
               we1 = 0;
               we2 = we;
               we3 = 0;
             end
      2'b11: begin
               we0 = 0;
               we1 = 0;
               we2 = 0;
               we3 = we;
             end
   endcase




always @(addr or dout0 or dout1 or dout2 or dout3)
   case (addr)
      2'b00: dout = dout0;
      2'b01: dout = dout1;
      2'b10: dout = dout2;
      2'b11: dout = dout3;
   endcase

endmodule
module memory(clk, we, addr, din,  dout);


parameter WIDTH=8;

input			clk;
input			we;
input [1:0]		addr;
input [WIDTH-1:0]	din;

output [WIDTH-1:0]	dout;
reg    [WIDTH-1:0]	dout;

wire    [WIDTH-1:0]	dout0,dout1,dout2,dout3;
reg			we0,we1,we2,we3;

reg32 #(WIDTH) reg0 (.clk(clk),.we(we0),.din(din[WIDTH-1:0]),
                     .dout(dout0[WIDTH-1:0]));
reg32 #(WIDTH) reg1 (.clk(clk),.we(we1),.din(din[WIDTH-1:0]),
                     .dout(dout1[WIDTH-1:0]));
reg32 #(WIDTH) reg2 (.clk(clk),.we(we2),.din(din[WIDTH-1:0]),
                     .dout(dout2[WIDTH-1:0]));
reg32 #(WIDTH) reg3 (.clk(clk),.we(we3),.din(din[WIDTH-1:0]),
                     .dout(dout3[WIDTH-1:0]));




always @(addr or we)
   case (addr)
      2'b00: begin
               we0 = we;
               we1 = 0;
               we2 = 0;
               we3 = 0;
             end
      2'b01: begin
               we0 = 0;
               we1 = we;
               we2 = 0;
               we3 = 0;
             end
      2'b10: begin
               we0 = 0;
               we1 = 0;
               we2 = we;
               we3 = 0;
             end
      2'b11: begin
               we0 = 0;
               we1 = 0;
               we2 = 0;
               we3 = we;
             end
   endcase




always @(addr or dout0 or dout1 or dout2 or dout3)
   case (addr)
      2'b00: dout = dout0;
      2'b01: dout = dout1;
      2'b10: dout = dout2;
      2'b11: dout = dout3;
   endcase

endmodule