data/full_repos/permissive/143278/ivltests/pr2350934b.v
 line:8: before: "case"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2350934b.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a.dummy !== 1) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr2350934b.v:5: Can\'t find definition of \'block\' in dotted task/function: \'block.f\'\n                                                                 : ... In instance top.a\n    initial dummy = block.f(0);\n                          ^\n        ... Known scopes under \'f\': <no cells found>\n        ... Known scopes under \'f\': <no cells found>\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top ();
   test #(1) a();
   test #(2) b();
   test #(4) c();

   initial begin
      #1 if (a.dummy !== 1) begin
	 $display("FAILED -- a.dummy = %d", a.dummy);
	 $finish;
      end
      if (b.dummy !== 2) begin
	 $display("FAILED -- b.dummy = %d", b.dummy);
	 $finish;
      end
      if (c.dummy !== 4) begin
	 $display("FAILED -- c.dummy = %d", c.dummy);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module top ();

   test #(1) a();
   test #(2) b();
   test #(4) c();

   initial begin
      #1 if (a.dummy !== 1) begin
	 $display("FAILED -- a.dummy = %d", a.dummy);
	 $finish;
      end
      if (b.dummy !== 2) begin
	 $display("FAILED -- b.dummy = %d", b.dummy);
	 $finish;
      end
      if (c.dummy !== 4) begin
	 $display("FAILED -- c.dummy = %d", c.dummy);
	 $finish;
      end

      $display("PASSED");
   end

endmodule