data/full_repos/permissive/123218339/memory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/123218339/memory.v:46: Bit extraction of array[1023:0] requires 10 bit index, not 16 bits.\n                                                                : ... In instance mem\n  data_out_buf <= {memory[address], memory[address+1]};\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/123218339/memory.v:53: Bit extraction of array[1023:0] requires 10 bit index, not 16 bits.\n                                                                : ... In instance mem\n   memory[address] <= data_in[15:8];\n         ^\n%Error: Exiting due to 2 warning(s)\n'
module mem(clock, address, wr_en, data_in, data_out);
	input clock, wr_en;
	input [`WORD_WIDTH-1:0] address, data_in;
	output [`WORD_WIDTH-1:0] data_out;


	reg [`MEM_WIDTH-1:0] memory [0:`MEM_DEPTH-1];



	initial begin
		$readmemh("./mem.txt", memory);
	end



	reg [`WORD_WIDTH-1:0] data_out_buf;

	always@(*)
		data_out_buf <= {memory[address], memory[address+1]};

	assign data_out = data_out_buf;


	always@(posedge clock) begin
		if (wr_en) begin
			memory[address] <= data_in[15:8];
			memory[address+1] <= data_in[7:0];
		end
	end
endmodule
module mem(clock, address, wr_en, data_in, data_out);

	input clock, wr_en;
	input [`WORD_WIDTH-1:0] address, data_in;
	output [`WORD_WIDTH-1:0] data_out;


	reg [`MEM_WIDTH-1:0] memory [0:`MEM_DEPTH-1];



	initial begin
		$readmemh("./mem.txt", memory);
	end



	reg [`WORD_WIDTH-1:0] data_out_buf;

	always@(*)
		data_out_buf <= {memory[address], memory[address+1]};

	assign data_out = data_out_buf;


	always@(posedge clock) begin
		if (wr_en) begin
			memory[address] <= data_in[15:8];
			memory[address+1] <= data_in[7:0];
		end
	end
endmodule