data/full_repos/permissive/19572582/Lab2/lab2_part2.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part2.v:115: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] SSD;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part2.v:86: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] SSD;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part2.v:22: Little bit endian vector: MSB < LSB of bit range: 0:6\noutput [0:6] HEX0, HEX1, HEX2, HEX3;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/19572582/Lab2/lab2_part2.v:78: Input port connection \'V\' expects 3 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                                        : ... In instance lab2_part3\n  circuitA A0 (SW[3:0], A[2:0]);\n                 ^\n%Error: Exiting due to 4 warning(s)\n'
module mux_4bit_2to1 (s, U, V, M);

  input s;
  input [3:0] U, V;
  output [3:0] M;

  assign M = ({4{~s}} & U) | ({4{s}} & V);
endmodule
module mux_4bit_2to1 (s, U, V, M);


  input s;
  input [3:0] U, V;
  output [3:0] M;

  assign M = ({4{~s}} & U) | ({4{s}} & V);
endmodule