data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v
 line:62: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0000000000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0000100000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0001000000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0001100000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0010000000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0010100000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0011000000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0011100000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0000000000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0000100000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0001000000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0001100000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0010000000000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0010100000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0011000000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0011100000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_instruc = 16\'b0000000000011101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #2 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:65: Unsupported: Ignoring delay on this delayed statement.\n    always #1 i_clk = ~i_clk;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:42: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                   : ... In instance tb_CPU\n        data_memory_out = $random%2048;\n                        ^\n%Error: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_CPU.v:67: Cannot find file containing module: \'CPU\'\n    CPU #(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/CPU\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/CPU.v\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Exiting due to 1 error(s), 21 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_CPU();
    parameter NB_INSTRUC      = 16;
    parameter NB_OPCODE       = 5;
    parameter NB_OPERAND      = 11;
    parameter NB_ADDR         = 11;
    parameter NB_DATA         = 16;


    reg                          i_clk;
    reg                          i_rst;
    reg [NB_INSTRUC - 1 : 0]     i_instruc;
    reg [NB_DATA - 1 : 0]        i_data_memory;

    wire [NB_ADDR -1 : 0]        o_addr_program_mem;
    wire [NB_ADDR - 1 : 0]       o_addr_data_mem;
    wire [NB_DATA - 1 : 0]       o_data_memory;
    wire                         o_WrRam;
    wire                         o_RdRam;

    reg [NB_DATA - 1 : 0] data_memory_out;
    reg [NB_DATA - 1 : 0] data_memory_in;

    always @(*) begin
        if (o_RdRam) begin
            i_data_memory = data_memory_out;
        end
        if (o_WrRam) begin
            data_memory_in = o_data_memory;
        end
    end

    initial begin
        i_clk = 1'b0;
        i_rst = 1'b0;
        i_instruc = {NB_INSTRUC{1'b0}};
        data_memory_out = {NB_DATA{1'b0}};

        #2
        i_rst = 1'b1;
        data_memory_out = $random%2048;

        #2 i_instruc = 16'b0000000000011101;
        #2 i_instruc = 16'b0000100000011101;
        #2 i_instruc = 16'b0001000000011101;
        #2 i_instruc = 16'b0001100000011101;
        #2 i_instruc = 16'b0010000000000000;
        #2 i_instruc = 16'b0010100000000000;
        #2 i_instruc = 16'b0011000000000000;
        #2 i_instruc = 16'b0011100000000000;
        #2 i_instruc = 16'b0000000000000000;
        #2 i_instruc = 16'b0000100000000000;
        #2 i_instruc = 16'b0001000000000000;
        #2 i_instruc = 16'b0001100000000000;
        #2 i_instruc = 16'b0010000000000000;
        #2 i_instruc = 16'b0010100000011101;
        #2 i_instruc = 16'b0011000000011101;
        #2 i_instruc = 16'b0011100000011101;
        #2 i_instruc = 16'b0000000000011101;
        
        #2 $finish;
    end

    always #1 i_clk = ~i_clk;

    CPU #(
        .NB_INSTRUC (NB_INSTRUC),
        .NB_OPCODE  (NB_OPCODE),
        .NB_OPERAND (NB_OPERAND),
        .NB_ADDR    (NB_ADDR),
        .NB_DATA    (NB_DATA)
    )
    tb_CPU (

        .i_clk          (i_clk),
        .i_rst          (i_rst),
        .i_instruc      (i_instruc),
        .i_data_memory  (i_data_memory),

        .o_addr_program_mem (o_addr_program_mem),
        .o_addr_data_mem    (o_addr_data_mem),
        .o_data_memory      (o_data_memory),
        .o_WrRam            (o_WrRam),
        .o_RdRam            (o_RdRam)
    );

endmodule
module tb_CPU();

    parameter NB_INSTRUC      = 16;
    parameter NB_OPCODE       = 5;
    parameter NB_OPERAND      = 11;
    parameter NB_ADDR         = 11;
    parameter NB_DATA         = 16;


    reg                          i_clk;
    reg                          i_rst;
    reg [NB_INSTRUC - 1 : 0]     i_instruc;
    reg [NB_DATA - 1 : 0]        i_data_memory;

    wire [NB_ADDR -1 : 0]        o_addr_program_mem;
    wire [NB_ADDR - 1 : 0]       o_addr_data_mem;
    wire [NB_DATA - 1 : 0]       o_data_memory;
    wire                         o_WrRam;
    wire                         o_RdRam;

    reg [NB_DATA - 1 : 0] data_memory_out;
    reg [NB_DATA - 1 : 0] data_memory_in;

    always @(*) begin
        if (o_RdRam) begin
            i_data_memory = data_memory_out;
        end
        if (o_WrRam) begin
            data_memory_in = o_data_memory;
        end
    end

    initial begin
        i_clk = 1'b0;
        i_rst = 1'b0;
        i_instruc = {NB_INSTRUC{1'b0}};
        data_memory_out = {NB_DATA{1'b0}};

        #2
        i_rst = 1'b1;
        data_memory_out = $random%2048;

        #2 i_instruc = 16'b0000000000011101;
        #2 i_instruc = 16'b0000100000011101;
        #2 i_instruc = 16'b0001000000011101;
        #2 i_instruc = 16'b0001100000011101;
        #2 i_instruc = 16'b0010000000000000;
        #2 i_instruc = 16'b0010100000000000;
        #2 i_instruc = 16'b0011000000000000;
        #2 i_instruc = 16'b0011100000000000;
        #2 i_instruc = 16'b0000000000000000;
        #2 i_instruc = 16'b0000100000000000;
        #2 i_instruc = 16'b0001000000000000;
        #2 i_instruc = 16'b0001100000000000;
        #2 i_instruc = 16'b0010000000000000;
        #2 i_instruc = 16'b0010100000011101;
        #2 i_instruc = 16'b0011000000011101;
        #2 i_instruc = 16'b0011100000011101;
        #2 i_instruc = 16'b0000000000011101;
        
        #2 $finish;
    end

    always #1 i_clk = ~i_clk;

    CPU #(
        .NB_INSTRUC (NB_INSTRUC),
        .NB_OPCODE  (NB_OPCODE),
        .NB_OPERAND (NB_OPERAND),
        .NB_ADDR    (NB_ADDR),
        .NB_DATA    (NB_DATA)
    )
    tb_CPU (

        .i_clk          (i_clk),
        .i_rst          (i_rst),
        .i_instruc      (i_instruc),
        .i_data_memory  (i_data_memory),

        .o_addr_program_mem (o_addr_program_mem),
        .o_addr_data_mem    (o_addr_data_mem),
        .o_data_memory      (o_data_memory),
        .o_WrRam            (o_WrRam),
        .o_RdRam            (o_RdRam)
    );

endmodule