data/full_repos/permissive/128659832/verilog/ufifo_tb.v
 line:87: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:55: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile(  "ufifo_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:56: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, ufifo_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_data = i;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_wr = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_wr = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_rd = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_rd = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_data = i;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_wr = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n            #2  INBOX_i_wr = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #2  INBOX_i_rd = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #2  INBOX_i_rd = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n                #2 ;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/ufifo_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #1000 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ufifo_tb;

    reg        clk     = 0;
    reg        i_rst   = 0;


    always #1 clk = ~clk;





    reg               INBOX_i_wr = 0;
    reg  signed [7:0] INBOX_i_data = 0;
    reg               INBOX_i_rd = 0;
    reg               INBOX_i_rst = 0;
    wire signed [7:0] INBOX_o_data;
    wire              INBOX_empty_n;
    wire              INBOX_full;

    wire        [4:0] INBOX_i_dmp_pos;
    wire        [7:0] INBOX_o_dmp_data; 
    wire              INBOX_o_dmp_valid; 

    ufifo #(.LGFLEN(4'd5), .RXFIFO(1)) INBOX (

        .i_wr(INBOX_i_wr),
        .i_data(INBOX_i_data),

        .i_rd(INBOX_i_rd),
        .o_data(INBOX_o_data),

        .o_empty_n( INBOX_empty_n ),
        .o_err( INBOX_full ),


        .i_dmp_pos(INBOX_i_dmp_pos),
        .o_dmp_data(INBOX_o_dmp_data),
        .o_dmp_valid(INBOX_o_dmp_valid),

        .i_rst(INBOX_i_rst),
        .i_clk(clk)
    );    


    integer i;

    integer x,y;


    initial begin

        $dumpfile(  "ufifo_tb.vcd");
        $dumpvars(0, ufifo_tb);


        for (i = 0; i<8; i=i+1) begin
            #2  INBOX_i_data = i;
            #2  INBOX_i_wr = 1;
            #2  INBOX_i_wr = 0;
        end


        for (i = 0; i<4; i=i+1) begin
            #2  INBOX_i_rd = 1;
            #2  INBOX_i_rd = 0;
        end


        for (i = 0; i<20; i=i+1) begin
            #2  INBOX_i_data = i;
            #2  INBOX_i_wr = 1;
            #2  INBOX_i_wr = 0;
        end

        #2  INBOX_i_rd = 1;
        #2  INBOX_i_rd = 0;

        for (y = 0; y<480; y=y+1) begin
            for (x = 0; x<640; x=x+1) begin
                #2 ;
            end
        end

        #1000 $finish;
    end

    reg         show_digit_i2;
    reg [9:0]   px_x0, px_y0;
    reg [9:0]   px_x1, px_y1;
    reg [9:0]   px_x2, px_y2;
    reg [1:0]   digit_sel_i2;

    always @( posedge clk) begin
        px_y0 <= y;
        px_x0 <= x;
        { px_x1, px_y1 } <= { px_x0, px_y0 };
        { px_x2, px_y2 } <= { px_x2, px_y2 };
        show_digit_i2 <= show_digit_i1;
    end


    wire [10:0] rom_addr;
    wire        font_bit2;
    font font0 (
        .i_clk(clk),
        .i_addr(rom_addr),
        .i_bit(~bit_addr),
        .o_data(font_bit2)
    );
    assign rom_addr = {char_addr, row_addr};




    wire        inbox_on1;
    wire [7:0]  char_addr_i;
    wire [2:0]  row_addr_i;
    wire [2:0]  bit_addr_i;

    assign inbox_on1 = ( px_y1[9:3] == 1 ) || ( px_y1[9:3] == 2 ) ;
    assign row_addr_i = px_y1[2:0];
    assign bit_addr_i = px_x1[2:0];

    wire [1:0]  digit_sel_i;
    assign digit_sel_i = px_x1[4:3];



    assign INBOX_i_dmp_pos=px_x0[9:5] - 5'd 2 + ( ( px_y0[9:3] == 2 ) ? 5'd 16 : 5'd 0 ) ;

    wire show_digit_i1 = inbox_on1 &&
        ( digit_sel_i == 2'd1 || digit_sel_i == 2'd2 ) &&
        INBOX_o_dmp_valid &&
        ( px_x1[9:3] >= 8 ) ;

    hex_to_ascii_digit hex_to_ascii_inbox(
        .data( INBOX_o_dmp_data ),
        .sel( digit_sel_i ),
        .o_ascii_code( char_addr_i )
    );






    reg [7:0] char_addr;
    reg [2:0] row_addr;
    reg [2:0] bit_addr;

    always @*
    begin
        if (inbox_on1)
            begin
                char_addr = char_addr_i;
                row_addr = row_addr_i;
                bit_addr = bit_addr_i;
            end
        else
            begin
                char_addr = 0;
                row_addr = 0;
                bit_addr = 0;
            end
    end




    reg [2:0] text_rgb;
    always @*
    begin
        text_rgb = 3'b110;
        if (show_digit_i2)
            begin
                if (font_bit2)
                    text_rgb = 3'b001;
            end





    end      

endmodule
module ufifo_tb;


    reg        clk     = 0;
    reg        i_rst   = 0;


    always #1 clk = ~clk;





    reg               INBOX_i_wr = 0;
    reg  signed [7:0] INBOX_i_data = 0;
    reg               INBOX_i_rd = 0;
    reg               INBOX_i_rst = 0;
    wire signed [7:0] INBOX_o_data;
    wire              INBOX_empty_n;
    wire              INBOX_full;

    wire        [4:0] INBOX_i_dmp_pos;
    wire        [7:0] INBOX_o_dmp_data; 
    wire              INBOX_o_dmp_valid; 

    ufifo #(.LGFLEN(4'd5), .RXFIFO(1)) INBOX (

        .i_wr(INBOX_i_wr),
        .i_data(INBOX_i_data),

        .i_rd(INBOX_i_rd),
        .o_data(INBOX_o_data),

        .o_empty_n( INBOX_empty_n ),
        .o_err( INBOX_full ),


        .i_dmp_pos(INBOX_i_dmp_pos),
        .o_dmp_data(INBOX_o_dmp_data),
        .o_dmp_valid(INBOX_o_dmp_valid),

        .i_rst(INBOX_i_rst),
        .i_clk(clk)
    );    


    integer i;

    integer x,y;


    initial begin

        $dumpfile(  "ufifo_tb.vcd");
        $dumpvars(0, ufifo_tb);


        for (i = 0; i<8; i=i+1) begin
            #2  INBOX_i_data = i;
            #2  INBOX_i_wr = 1;
            #2  INBOX_i_wr = 0;
        end


        for (i = 0; i<4; i=i+1) begin
            #2  INBOX_i_rd = 1;
            #2  INBOX_i_rd = 0;
        end


        for (i = 0; i<20; i=i+1) begin
            #2  INBOX_i_data = i;
            #2  INBOX_i_wr = 1;
            #2  INBOX_i_wr = 0;
        end

        #2  INBOX_i_rd = 1;
        #2  INBOX_i_rd = 0;

        for (y = 0; y<480; y=y+1) begin
            for (x = 0; x<640; x=x+1) begin
                #2 ;
            end
        end

        #1000 $finish;
    end

    reg         show_digit_i2;
    reg [9:0]   px_x0, px_y0;
    reg [9:0]   px_x1, px_y1;
    reg [9:0]   px_x2, px_y2;
    reg [1:0]   digit_sel_i2;

    always @( posedge clk) begin
        px_y0 <= y;
        px_x0 <= x;
        { px_x1, px_y1 } <= { px_x0, px_y0 };
        { px_x2, px_y2 } <= { px_x2, px_y2 };
        show_digit_i2 <= show_digit_i1;
    end


    wire [10:0] rom_addr;
    wire        font_bit2;
    font font0 (
        .i_clk(clk),
        .i_addr(rom_addr),
        .i_bit(~bit_addr),
        .o_data(font_bit2)
    );
    assign rom_addr = {char_addr, row_addr};




    wire        inbox_on1;
    wire [7:0]  char_addr_i;
    wire [2:0]  row_addr_i;
    wire [2:0]  bit_addr_i;

    assign inbox_on1 = ( px_y1[9:3] == 1 ) || ( px_y1[9:3] == 2 ) ;
    assign row_addr_i = px_y1[2:0];
    assign bit_addr_i = px_x1[2:0];

    wire [1:0]  digit_sel_i;
    assign digit_sel_i = px_x1[4:3];



    assign INBOX_i_dmp_pos=px_x0[9:5] - 5'd 2 + ( ( px_y0[9:3] == 2 ) ? 5'd 16 : 5'd 0 ) ;

    wire show_digit_i1 = inbox_on1 &&
        ( digit_sel_i == 2'd1 || digit_sel_i == 2'd2 ) &&
        INBOX_o_dmp_valid &&
        ( px_x1[9:3] >= 8 ) ;

    hex_to_ascii_digit hex_to_ascii_inbox(
        .data( INBOX_o_dmp_data ),
        .sel( digit_sel_i ),
        .o_ascii_code( char_addr_i )
    );






    reg [7:0] char_addr;
    reg [2:0] row_addr;
    reg [2:0] bit_addr;

    always @*
    begin
        if (inbox_on1)
            begin
                char_addr = char_addr_i;
                row_addr = row_addr_i;
                bit_addr = bit_addr_i;
            end
        else
            begin
                char_addr = 0;
                row_addr = 0;
                bit_addr = 0;
            end
    end




    reg [2:0] text_rgb;
    always @*
    begin
        text_rgb = 3'b110;
        if (show_digit_i2)
            begin
                if (font_bit2)
                    text_rgb = 3'b001;
            end





    end      

endmodule