data/full_repos/permissive/159555381/adder.v
 line:22: before: ","
1: b'%Error: data/full_repos/permissive/159555381/adder.v:22: Unsupported or unknown PLI call: $monitor\n   $monitor( $time,,, "X1: %d,    X2: %d   Cy: %b    out: %d", X1, X2, Cy, out);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/159555381/adder.v:22: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   $monitor( $time,,, "X1: %d,    X2: %d   Cy: %b    out: %d", X1, X2, Cy, out);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/adder.v:23: Unsupported: Ignoring delay on this delayed statement.\n   #5 X1= 10; X2=5;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159555381/adder.v:24: Unsupported: Ignoring delay on this delayed statement.\n                 #5 X1 = 5; X2 = 6;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/adder.v:25: Unsupported: Ignoring delay on this delayed statement.\n                 #5 X1 = 20; X2 = 15;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/adder.v:26: Unsupported: Ignoring delay on this delayed statement.\n                 #5 X1 = 8; X2 = 7;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/adder.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #5 X1 = 255; X2 = 128;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/adder.v:29: Unsupported: Ignoring delay on this delayed statement.\n                 #5 $finish;\n                 ^\n%Error: data/full_repos/permissive/159555381/adder.v:46: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("Fulladder.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/159555381/adder.v:47: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,TB);\n  ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB;
	wire [7:0] X1,X2;

	wire [7:0] out;
	wire Cy;

	adder MyFulladder(X1,X2,out,Cy);
	test tes(X1, X2, out, Cy);

	initial
	begin
		$dumpfile("Fulladder.vcd");
		$dumpvars(0,TB);
	end

endmodule
module TB;

	wire [7:0] X1,X2;

	wire [7:0] out;
	wire Cy;

	adder MyFulladder(X1,X2,out,Cy);
	test tes(X1, X2, out, Cy);

	initial
	begin
		$dumpfile("Fulladder.vcd");
		$dumpvars(0,TB);
	end

endmodule