data/full_repos/permissive/172912857/project_bcd_7dig/bcd_7dig.v
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data/verilator_xmls/2c5f037e-d35a-4abe-b4b8-0ad997fa253c.xml
module bcdto7segmentclocked(
    input [3:0] A, B, C, D,
    input reset,
    input clk,
    output [3:0] anode,
    output [6:0] seg 
    );

wire [3:0] x;
wire [3:0] an;
wire [1:0] sel;
wire clk_div;
bcdto7segment_dataflow bcdto7segment(.x(x), .an(an), .anode(anode), .seg(seg));
mux16to4 mux16to4(.A(A),.B(B),.C(C), .D(D), .sel(sel), .S(x));
demux4to1 demux4to1(.sel(sel), .A(an[0]), .B(an[1]), .C(an[2]), .D(an[3]));
counter counter(.reset(reset), .clk(clk_div), .out(sel));
ClkDivider ClkDivider(.clk(clk),.rst(reset),.clk_div(clk_div));

endmodule
module bcdto7segmentclocked(
    input [3:0] A, B, C, D,
    input reset,
    input clk,
    output [3:0] anode,
    output [6:0] seg 
    );


wire [3:0] x;
wire [3:0] an;
wire [1:0] sel;
wire clk_div;
bcdto7segment_dataflow bcdto7segment(.x(x), .an(an), .anode(anode), .seg(seg));
mux16to4 mux16to4(.A(A),.B(B),.C(C), .D(D), .sel(sel), .S(x));
demux4to1 demux4to1(.sel(sel), .A(an[0]), .B(an[1]), .C(an[2]), .D(an[3]));
counter counter(.reset(reset), .clk(clk_div), .out(sel));
ClkDivider ClkDivider(.clk(clk),.rst(reset),.clk_div(clk_div));

endmodule