data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v:27: Cannot find file containing module: \'pc_vga_font_rom\'\npc_vga_font_rom char_rom(pixel_clk, ram_contents[7:0], pixel_row[3:0], pixel_en);\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/118895292/peripheral/vga,data/full_repos/permissive/118895292/pc_vga_font_rom\n             data/full_repos/permissive/118895292/peripheral/vga,data/full_repos/permissive/118895292/pc_vga_font_rom.v\n             data/full_repos/permissive/118895292/peripheral/vga,data/full_repos/permissive/118895292/pc_vga_font_rom.sv\n             pc_vga_font_rom\n             pc_vga_font_rom.v\n             pc_vga_font_rom.sv\n             obj_dir/pc_vga_font_rom\n             obj_dir/pc_vga_font_rom.v\n             obj_dir/pc_vga_font_rom.sv\n%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v:58: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                                      : ... In instance vga_pixel_gen\n  ram_addr <= (next_col / 16\'d8) + ((next_row / 16\'d16) * 16\'d80);\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v:59: Operator AND expects 32 or 16 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                      : ... In instance vga_pixel_gen\n  if ((next_col / 8) & 1\'b1)\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v:59: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 32 or 16 bits.\n                                                                                      : ... In instance vga_pixel_gen\n  if ((next_col / 8) & 1\'b1)\n  ^~\n%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v:73: Bit extraction of var[15:0] requires 4 bit index, not 3 bits.\n                                                                                      : ... In instance vga_pixel_gen\n  vga_r <= {4{data_reset || ram_addr_past_80x25 ? 1\'b0 : (!rom_output_even[pixel_col[2:0]] ? rom_output_even[14] : rom_output_even[10])}};\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v:74: Bit extraction of var[15:0] requires 4 bit index, not 3 bits.\n                                                                                      : ... In instance vga_pixel_gen\n  vga_g <= {4{data_reset || ram_addr_past_80x25 ? 1\'b0 : (!rom_output_even[pixel_col[2:0]] ? rom_output_even[13] : rom_output_even[9])}};\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v:75: Bit extraction of var[15:0] requires 4 bit index, not 3 bits.\n                                                                                      : ... In instance vga_pixel_gen\n  vga_b <= {4{data_reset || ram_addr_past_80x25 ? 1\'b0 : (!rom_output_even[pixel_col[2:0]] ? rom_output_even[12] : rom_output_even[8])}};\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v:79: Bit extraction of var[15:0] requires 4 bit index, not 3 bits.\n                                                                                      : ... In instance vga_pixel_gen\n  vga_r <= {4{data_reset || ram_addr_past_80x25 ? 1\'b0 : (!rom_output_odd[pixel_col[2:0]] ? rom_output_odd[14] : rom_output_odd[10])}};\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v:80: Bit extraction of var[15:0] requires 4 bit index, not 3 bits.\n                                                                                      : ... In instance vga_pixel_gen\n  vga_g <= {4{data_reset || ram_addr_past_80x25 ? 1\'b0 : (!rom_output_odd[pixel_col[2:0]] ? rom_output_odd[13] : rom_output_odd[9])}};\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v:81: Bit extraction of var[15:0] requires 4 bit index, not 3 bits.\n                                                                                      : ... In instance vga_pixel_gen\n  vga_b <= {4{data_reset || ram_addr_past_80x25 ? 1\'b0 : (!rom_output_odd[pixel_col[2:0]] ? rom_output_odd[12] : rom_output_odd[8])}};\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v:71: Operator AND expects 32 or 16 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                      : ... In instance vga_pixel_gen\n if ((pixel_col / 8) & 1\'b1)\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/118895292/peripheral/vga/vga_pixel_gen.v:71: Logical Operator IF expects 1 bit on the If, but If\'s AND generates 32 or 16 bits.\n                                                                                      : ... In instance vga_pixel_gen\n if ((pixel_col / 8) & 1\'b1)\n ^~\n%Error: Exiting due to 1 error(s), 11 warning(s)\n'
module vga_pixel_gen (
	pixel_clk,
	data_reset,
	ram_addr,
	ram_contents,
	pixel_col,
	pixel_row,
	vga_r,
	vga_g,
	vga_b
);

input wire pixel_clk;
input data_reset;
output reg [11:0] ram_addr;
input [15:0] ram_contents;
input [15:0] pixel_col;
input [15:0] pixel_row;
output reg [3:0] vga_r;
output reg [3:0] vga_g;
output reg [3:0] vga_b;

wire [7:0] pixel_en;
wire ram_addr_past_80x25;
reg data_reset_sync;

pc_vga_font_rom char_rom(pixel_clk, ram_contents[7:0], pixel_row[3:0], pixel_en);
assign ram_addr_past_80x25 = pixel_row >= (25*16);

reg [15:0] rom_output_odd;
reg [15:0] rom_output_even;

reg [15:0] next_col;
reg [15:0] next_row;

always @(posedge pixel_clk)
begin




	if (!data_reset)
	begin
		if ((pixel_col + 8) >= 640)
		begin
			next_col <= 0;
			if ((pixel_row + 1) >= 480)
				next_row <= 0;
			else
				next_row <= pixel_row + 1;
		end
		else
		begin
			next_row <= pixel_row;
			next_col <= pixel_col + 8;
		end
		
		ram_addr <= (next_col / 16'd8) + ((next_row / 16'd16) * 16'd80);
		if ((next_col / 8) & 1'b1)
		begin
			rom_output_even[15:8] <= ram_contents[15:8];
			rom_output_even[7:0] <= pixel_en;
		end
		else
		begin
			rom_output_odd[15:8] <= ram_contents[15:8];
			rom_output_odd[7:0] <= pixel_en;
		end
	end
	
	if ((pixel_col / 8) & 1'b1)
	begin
		vga_r <= {4{data_reset || ram_addr_past_80x25 ? 1'b0 : (!rom_output_even[pixel_col[2:0]] ? rom_output_even[14] : rom_output_even[10])}};
		vga_g <= {4{data_reset || ram_addr_past_80x25 ? 1'b0 : (!rom_output_even[pixel_col[2:0]] ? rom_output_even[13] : rom_output_even[9])}};
		vga_b <= {4{data_reset || ram_addr_past_80x25 ? 1'b0 : (!rom_output_even[pixel_col[2:0]] ? rom_output_even[12] : rom_output_even[8])}};
	end
	else
		begin
		vga_r <= {4{data_reset || ram_addr_past_80x25 ? 1'b0 : (!rom_output_odd[pixel_col[2:0]] ? rom_output_odd[14] : rom_output_odd[10])}};
		vga_g <= {4{data_reset || ram_addr_past_80x25 ? 1'b0 : (!rom_output_odd[pixel_col[2:0]] ? rom_output_odd[13] : rom_output_odd[9])}};
		vga_b <= {4{data_reset || ram_addr_past_80x25 ? 1'b0 : (!rom_output_odd[pixel_col[2:0]] ? rom_output_odd[12] : rom_output_odd[8])}};
	end
end

endmodule
module vga_pixel_gen (
	pixel_clk,
	data_reset,
	ram_addr,
	ram_contents,
	pixel_col,
	pixel_row,
	vga_r,
	vga_g,
	vga_b
);


input wire pixel_clk;
input data_reset;
output reg [11:0] ram_addr;
input [15:0] ram_contents;
input [15:0] pixel_col;
input [15:0] pixel_row;
output reg [3:0] vga_r;
output reg [3:0] vga_g;
output reg [3:0] vga_b;

wire [7:0] pixel_en;
wire ram_addr_past_80x25;
reg data_reset_sync;

pc_vga_font_rom char_rom(pixel_clk, ram_contents[7:0], pixel_row[3:0], pixel_en);
assign ram_addr_past_80x25 = pixel_row >= (25*16);

reg [15:0] rom_output_odd;
reg [15:0] rom_output_even;

reg [15:0] next_col;
reg [15:0] next_row;

always @(posedge pixel_clk)
begin




	if (!data_reset)
	begin
		if ((pixel_col + 8) >= 640)
		begin
			next_col <= 0;
			if ((pixel_row + 1) >= 480)
				next_row <= 0;
			else
				next_row <= pixel_row + 1;
		end
		else
		begin
			next_row <= pixel_row;
			next_col <= pixel_col + 8;
		end
		
		ram_addr <= (next_col / 16'd8) + ((next_row / 16'd16) * 16'd80);
		if ((next_col / 8) & 1'b1)
		begin
			rom_output_even[15:8] <= ram_contents[15:8];
			rom_output_even[7:0] <= pixel_en;
		end
		else
		begin
			rom_output_odd[15:8] <= ram_contents[15:8];
			rom_output_odd[7:0] <= pixel_en;
		end
	end
	
	if ((pixel_col / 8) & 1'b1)
	begin
		vga_r <= {4{data_reset || ram_addr_past_80x25 ? 1'b0 : (!rom_output_even[pixel_col[2:0]] ? rom_output_even[14] : rom_output_even[10])}};
		vga_g <= {4{data_reset || ram_addr_past_80x25 ? 1'b0 : (!rom_output_even[pixel_col[2:0]] ? rom_output_even[13] : rom_output_even[9])}};
		vga_b <= {4{data_reset || ram_addr_past_80x25 ? 1'b0 : (!rom_output_even[pixel_col[2:0]] ? rom_output_even[12] : rom_output_even[8])}};
	end
	else
		begin
		vga_r <= {4{data_reset || ram_addr_past_80x25 ? 1'b0 : (!rom_output_odd[pixel_col[2:0]] ? rom_output_odd[14] : rom_output_odd[10])}};
		vga_g <= {4{data_reset || ram_addr_past_80x25 ? 1'b0 : (!rom_output_odd[pixel_col[2:0]] ? rom_output_odd[13] : rom_output_odd[9])}};
		vga_b <= {4{data_reset || ram_addr_past_80x25 ? 1'b0 : (!rom_output_odd[pixel_col[2:0]] ? rom_output_odd[12] : rom_output_odd[8])}};
	end
end

endmodule