data/full_repos/permissive/11584509/experimental/CM1/flasher.v
data/verilator_xmls/2d09b61c-5058-49f7-af41-65cfb8339615.xml
module flasher(
		clk,
		flash
	);



	

	parameter BITS = 24;
								


	input clk;
	output flash;



	reg [BITS-1:0] counter;
	


	assign flash = counter[BITS-1];
	


	always @(posedge clk)
		counter <= counter + 1;

endmodule
module flasher(
		clk,
		flash
	);




	

	parameter BITS = 24;
								


	input clk;
	output flash;



	reg [BITS-1:0] counter;
	


	assign flash = counter[BITS-1];
	


	always @(posedge clk)
		counter <= counter + 1;

endmodule