data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/ethernet_tx.v
1: b"%Error: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/ethernet_tx.v:23: Cannot find file containing module: 'add_crc32'\nadd_crc32 i_add_crc32(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files,data/full_repos/permissive/219917900/add_crc32\n             data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files,data/full_repos/permissive/219917900/add_crc32.v\n             data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files,data/full_repos/permissive/219917900/add_crc32.sv\n             add_crc32\n             add_crc32.v\n             add_crc32.sv\n             obj_dir/add_crc32\n             obj_dir/add_crc32.v\n             obj_dir/add_crc32.sv\n%Error: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/ethernet_tx.v:37: Cannot find file containing module: 'add_preamble'\nadd_preamble i_add_preamble(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/219917900/txrx_rtl_files/tx_rtl_files/ethernet_tx.v:46: Cannot find file containing module: 'rgmii_tx'\nrgmii_tx i_rgmii_tx(\n^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module ethernet_tx (
	input wire clk125MHz,
	input wire clk125MHz90,
	input wire [7:0] raw_data,
	input wire raw_data_valid,
	input wire raw_data_enable,
	input wire phy_ready,
	

	output wire [3:0] eth_txd,
	output wire eth_txck,
	output wire eth_txctl
);


wire [7:0] with_crc;
wire with_crc_valid;
wire with_crc_enable;


add_crc32 i_add_crc32(
	.clk(clk125MHz),
	.data_in(raw_data),
	.data_valid_in(raw_data_valid),
	.data_enable_in(raw_data_enable),
	.data_out(with_crc),
	.data_valid_out(with_crc_valid),
	.data_enable_out(with_crc_enable)
	);

wire [7:0] fully_framed;
wire fully_framed_valid;
wire fully_framed_enable;
wire fully_framed_err;
add_preamble i_add_preamble(
	.clk(clk125MHz),
	.data_in(with_crc),
	.data_valid_in(with_crc_valid),
	.data_enable_in(with_crc_enable),
	.data_out(fully_framed),
	.data_valid_out(fully_framed_valid),
	.data_enable_out(fully_framed_enable)
	);
rgmii_tx i_rgmii_tx(
	.clk(clk125MHz),
	.clk90(clk125MHz90),
	.phy_ready(1'b1),

	.data(fully_framed),
	.data_valid(fully_framed_valid),
	.data_enable(fully_framed_enable),
	.data_error(1'b0),
	.eth_txck(eth_txck),
	.eth_txctl(eth_txctl),
	.eth_txd(eth_txd)
	);



endmodule
module ethernet_tx (
	input wire clk125MHz,
	input wire clk125MHz90,
	input wire [7:0] raw_data,
	input wire raw_data_valid,
	input wire raw_data_enable,
	input wire phy_ready,
	

	output wire [3:0] eth_txd,
	output wire eth_txck,
	output wire eth_txctl
);



wire [7:0] with_crc;
wire with_crc_valid;
wire with_crc_enable;


add_crc32 i_add_crc32(
	.clk(clk125MHz),
	.data_in(raw_data),
	.data_valid_in(raw_data_valid),
	.data_enable_in(raw_data_enable),
	.data_out(with_crc),
	.data_valid_out(with_crc_valid),
	.data_enable_out(with_crc_enable)
	);

wire [7:0] fully_framed;
wire fully_framed_valid;
wire fully_framed_enable;
wire fully_framed_err;
add_preamble i_add_preamble(
	.clk(clk125MHz),
	.data_in(with_crc),
	.data_valid_in(with_crc_valid),
	.data_enable_in(with_crc_enable),
	.data_out(fully_framed),
	.data_valid_out(fully_framed_valid),
	.data_enable_out(fully_framed_enable)
	);
rgmii_tx i_rgmii_tx(
	.clk(clk125MHz),
	.clk90(clk125MHz90),
	.phy_ready(1'b1),

	.data(fully_framed),
	.data_valid(fully_framed_valid),
	.data_enable(fully_framed_enable),
	.data_error(1'b0),
	.eth_txck(eth_txck),
	.eth_txctl(eth_txctl),
	.eth_txd(eth_txd)
	);



endmodule