data/full_repos/permissive/178052224/Tarea6/demux_valid/src/yosys+demux_valid.v
1: b'%Error: data/full_repos/permissive/178052224/Tarea6/demux_valid/src/yosys+demux_valid.v:153: Can\'t resolve module reference: \'$_DLATCH_P_\'\n  \\$_DLATCH_P_  _37_ (\n                ^~~~\n%Warning-MULTITOP: data/full_repos/permissive/178052224/Tarea6/demux_valid/src/yosys+demux_valid.v:153: Multiple top level modules\n                                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                      : ... Top module \'demux_valid\'\nmodule demux_valid(clk, reset_L, valid_in, data_tran, data_out0, data_out1, data_in, valid_out0, valid_out1);\n       ^~~~~~~~~~~\n                                                                                                      : ... Top module \'$_DLATCH_P_\'\n  \\$_DLATCH_P_  _37_ (\n                ^~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module demux_valid(clk, reset_L, valid_in, data_tran, data_out0, data_out1, data_in, valid_out0, valid_out1);
  (* src = "src/demux_valid.v:12" *)
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  (* src = "src/demux_valid.v:3" *)
  input clk;
  (* src = "src/demux_valid.v:5" *)
  input [3:0] data_in;
  (* src = "src/demux_valid.v:4" *)
  output [3:0] data_out0;
  (* src = "src/demux_valid.v:4" *)
  output [3:0] data_out1;
  (* src = "src/demux_valid.v:4" *)
  output [3:0] data_tran;
  (* src = "src/demux_valid.v:3" *)
  input reset_L;
  (* src = "src/demux_valid.v:9" *)
  wire s;
  (* src = "src/demux_valid.v:3" *)
  input valid_in;
  (* src = "src/demux_valid.v:6" *)
  output valid_out0;
  (* src = "src/demux_valid.v:6" *)
  output valid_out1;
  NOT _13_ (
    .A(valid_in),
    .Y(_01_)
  );
  NAND _14_ (
    .A(reset_L),
    .B(s),
    .Y(_02_)
  );
  NOR _15_ (
    .A(_02_),
    .B(_01_),
    .Y(valid_out1)
  );
  NAND _16_ (
    .A(reset_L),
    .B(valid_in),
    .Y(_03_)
  );
  NOR _17_ (
    .A(_03_),
    .B(s),
    .Y(valid_out0)
  );
  NOT _18_ (
    .A(data_in[0]),
    .Y(_04_)
  );
  NOR _19_ (
    .A(_02_),
    .B(_04_),
    .Y(data_out1[0])
  );
  NOT _20_ (
    .A(data_in[1]),
    .Y(_05_)
  );
  NOR _21_ (
    .A(_02_),
    .B(_05_),
    .Y(data_out1[1])
  );
  NOT _22_ (
    .A(data_in[2]),
    .Y(_07_)
  );
  NOR _23_ (
    .A(_02_),
    .B(_07_),
    .Y(data_out1[2])
  );
  NOT _24_ (
    .A(data_in[3]),
    .Y(_08_)
  );
  NOR _25_ (
    .A(_02_),
    .B(_08_),
    .Y(data_out1[3])
  );
  NAND _26_ (
    .A(reset_L),
    .B(data_in[0]),
    .Y(_09_)
  );
  NOR _27_ (
    .A(_09_),
    .B(s),
    .Y(data_out0[0])
  );
  NAND _28_ (
    .A(reset_L),
    .B(data_in[1]),
    .Y(_10_)
  );
  NOR _29_ (
    .A(_10_),
    .B(s),
    .Y(data_out0[1])
  );
  NAND _30_ (
    .A(reset_L),
    .B(data_in[2]),
    .Y(_11_)
  );
  NOR _31_ (
    .A(_11_),
    .B(s),
    .Y(data_out0[2])
  );
  NAND _32_ (
    .A(reset_L),
    .B(data_in[3]),
    .Y(_12_)
  );
  NOR _33_ (
    .A(_12_),
    .B(s),
    .Y(data_out0[3])
  );
  NOT _34_ (
    .A(s),
    .Y(_00_)
  );
  NOT _35_ (
    .A(reset_L),
    .Y(_06_)
  );
  DFF _36_ (
    .C(clk),
    .D(_00_),
    .Q(s)
  );
  \$_DLATCH_P_  _37_ (
    .D(1'b0),
    .E(_06_),
    .Q(s)
  );
  assign data_tran = data_in;
endmodule
module demux_valid(clk, reset_L, valid_in, data_tran, data_out0, data_out1, data_in, valid_out0, valid_out1);

  (* src = "src/demux_valid.v:12" *)
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  (* src = "src/demux_valid.v:3" *)
  input clk;
  (* src = "src/demux_valid.v:5" *)
  input [3:0] data_in;
  (* src = "src/demux_valid.v:4" *)
  output [3:0] data_out0;
  (* src = "src/demux_valid.v:4" *)
  output [3:0] data_out1;
  (* src = "src/demux_valid.v:4" *)
  output [3:0] data_tran;
  (* src = "src/demux_valid.v:3" *)
  input reset_L;
  (* src = "src/demux_valid.v:9" *)
  wire s;
  (* src = "src/demux_valid.v:3" *)
  input valid_in;
  (* src = "src/demux_valid.v:6" *)
  output valid_out0;
  (* src = "src/demux_valid.v:6" *)
  output valid_out1;
  NOT _13_ (
    .A(valid_in),
    .Y(_01_)
  );
  NAND _14_ (
    .A(reset_L),
    .B(s),
    .Y(_02_)
  );
  NOR _15_ (
    .A(_02_),
    .B(_01_),
    .Y(valid_out1)
  );
  NAND _16_ (
    .A(reset_L),
    .B(valid_in),
    .Y(_03_)
  );
  NOR _17_ (
    .A(_03_),
    .B(s),
    .Y(valid_out0)
  );
  NOT _18_ (
    .A(data_in[0]),
    .Y(_04_)
  );
  NOR _19_ (
    .A(_02_),
    .B(_04_),
    .Y(data_out1[0])
  );
  NOT _20_ (
    .A(data_in[1]),
    .Y(_05_)
  );
  NOR _21_ (
    .A(_02_),
    .B(_05_),
    .Y(data_out1[1])
  );
  NOT _22_ (
    .A(data_in[2]),
    .Y(_07_)
  );
  NOR _23_ (
    .A(_02_),
    .B(_07_),
    .Y(data_out1[2])
  );
  NOT _24_ (
    .A(data_in[3]),
    .Y(_08_)
  );
  NOR _25_ (
    .A(_02_),
    .B(_08_),
    .Y(data_out1[3])
  );
  NAND _26_ (
    .A(reset_L),
    .B(data_in[0]),
    .Y(_09_)
  );
  NOR _27_ (
    .A(_09_),
    .B(s),
    .Y(data_out0[0])
  );
  NAND _28_ (
    .A(reset_L),
    .B(data_in[1]),
    .Y(_10_)
  );
  NOR _29_ (
    .A(_10_),
    .B(s),
    .Y(data_out0[1])
  );
  NAND _30_ (
    .A(reset_L),
    .B(data_in[2]),
    .Y(_11_)
  );
  NOR _31_ (
    .A(_11_),
    .B(s),
    .Y(data_out0[2])
  );
  NAND _32_ (
    .A(reset_L),
    .B(data_in[3]),
    .Y(_12_)
  );
  NOR _33_ (
    .A(_12_),
    .B(s),
    .Y(data_out0[3])
  );
  NOT _34_ (
    .A(s),
    .Y(_00_)
  );
  NOT _35_ (
    .A(reset_L),
    .Y(_06_)
  );
  DFF _36_ (
    .C(clk),
    .D(_00_),
    .Q(s)
  );
  \$_DLATCH_P_  _37_ (
    .D(1'b0),
    .E(_06_),
    .Q(s)
  );
  assign data_tran = data_in;
endmodule