data/full_repos/permissive/198830281/clkDivider.v
1: b'%Error: data/full_repos/permissive/198830281/clkDivider.v:14: Unsupported: `default_nettype of other than none or wire: `default_nettype None\n`default_nettype None\n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clkDivider #(parameter integer factor = 100) (output clkOut, input clkIn);

    reg[31:0] counter;


    initial begin
        counter = 32'd0;
    end


    always @ (posedge clkIn) begin
        counter <= counter + 1;

        if(counter == factor)
            counter <= 0;
    end


    assign clkOut = (counter < factor/2) ? 1'b0 : 1'b1;
endmodule
module clkDivider #(parameter integer factor = 100) (output clkOut, input clkIn);


    reg[31:0] counter;


    initial begin
        counter = 32'd0;
    end


    always @ (posedge clkIn) begin
        counter <= counter + 1;

        if(counter == factor)
            counter <= 0;
    end


    assign clkOut = (counter < factor/2) ? 1'b0 : 1'b1;
endmodule