data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/baudgen_tx.v
1: b'%Error: data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/baudgen_tx.v:12: Cannot find include file: baudgen.vh\n`include "baudgen.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez,data/full_repos/permissive/132480659/baudgen.vh\n             data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez,data/full_repos/permissive/132480659/baudgen.vh.v\n             data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez,data/full_repos/permissive/132480659/baudgen.vh.sv\n             baudgen.vh\n             baudgen.vh.v\n             baudgen.vh.sv\n             obj_dir/baudgen.vh\n             obj_dir/baudgen.vh.v\n             obj_dir/baudgen.vh.sv\n%Error: data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/baudgen_tx.v:31: Define or directive not defined: \'`B115200\'\n          parameter BAUDRATE = `B115200   \n                               ^~~~~~~~\n%Error: data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/baudgen_tx.v:32: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n)(\n^\n%Error: data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/baudgen_tx.v:34: syntax error, unexpected input, expecting IDENTIFIER or do or final\n          input wire clk,                \n          ^~~~~\n%Error: data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/baudgen_tx.v:35: syntax error, unexpected input, expecting IDENTIFIER or do or final\n          input wire clk_ena,            \n          ^~~~~\n%Error: data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/baudgen_tx.v:36: syntax error, unexpected output, expecting IDENTIFIER or do or final\n          output wire clk_out            \n          ^~~~~~\n%Error: data/full_repos/permissive/132480659/Colecciones/CTIF-MadridCap-6/examples/06-Simplez/baudgen_tx.v:46: syntax error, unexpected always\nalways @(posedge clk)\n^~~~~~\n%Error: Exiting due to 7 error(s)\n'
module baudgen_tx #(
          parameter BAUDRATE = `B115200
)(
          input wire rstn,
          input wire clk,
          input wire clk_ena,
          output wire clk_out
);


localparam N = $clog2(BAUDRATE);



reg [N-1:0] divcounter = 0;

always @(posedge clk)

  if (!rstn)
    divcounter <= 0;

  else if (clk_ena)

    divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
  else


    divcounter <= BAUDRATE - 1;



assign clk_out = (divcounter == 0) ? clk_ena : 0;


endmodule
module baudgen_tx #(
          parameter BAUDRATE = `B115200
)(
          input wire rstn,
          input wire clk,
          input wire clk_ena,
          output wire clk_out
);



localparam N = $clog2(BAUDRATE);



reg [N-1:0] divcounter = 0;

always @(posedge clk)

  if (!rstn)
    divcounter <= 0;

  else if (clk_ena)

    divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
  else


    divcounter <= BAUDRATE - 1;



assign clk_out = (divcounter == 0) ? clk_ena : 0;


endmodule