data/full_repos/permissive/114642806/dev/milestone1/counter.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/114642806/dev/milestone1/counter.v:59: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'counter\'\nmodule counter(CLOCK_50, enable);\n       ^~~~~~~\n                                                                                   : ... Top module \'backup_counter\'\nmodule backup_counter(CLOCK_50, enable_next);\n       ^~~~~~~~~~~~~~\n                                                                                   : ... Top module \'selector\'\nmodule selector(select, clock, enable, count1);\n       ^~~~~~~~\n                                                                                   : ... Top module \'displayHEX\'\nmodule displayHEX (s,h);\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/114642806/dev/milestone1/counter.v:100: Operator GTE expects 28 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                 : ... In instance selector\n   2\'b00: out = (count1 >= 1\'b1)? 1\'b1 : 1\'b0;\n                        ^~\n%Error: Exiting due to 2 warning(s)\n'
module backup_counter(CLOCK_50, enable_next);

input CLOCK_50;
output enable_next;

reg [28:0] count = 29'b0;
assign enable_next = (count == 29'b11101110011010110010100000000) ? 1'b1 : 1'b0;






always @(posedge CLOCK_50)
	begin
	if (enable_next == 1'b1)
		begin
			count <= 0;
		end
	else
		begin
			count <= count + 1'b1;
		end
	end
endmodule
module backup_counter(CLOCK_50, enable_next);


input CLOCK_50;
output enable_next;

reg [28:0] count = 29'b0;
assign enable_next = (count == 29'b11101110011010110010100000000) ? 1'b1 : 1'b0;






always @(posedge CLOCK_50)
	begin
	if (enable_next == 1'b1)
		begin
			count <= 0;
		end
	else
		begin
			count <= count + 1'b1;
		end
	end
endmodule