data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v
 line:150: before: "reg"
1: b"%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:338: Cannot find file containing module: 'IC82x6'\nIC82x6 #(.INVERTED_OUTPUT(0)) \n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board,data/full_repos/permissive/160858992/IC82x6\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board,data/full_repos/permissive/160858992/IC82x6.v\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board,data/full_repos/permissive/160858992/IC82x6.sv\n             IC82x6\n             IC82x6.v\n             IC82x6.sv\n             obj_dir/IC82x6\n             obj_dir/IC82x6.v\n             obj_dir/IC82x6.sv\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:348: Cannot find file containing module: 'IC82x6'\nIC82x6 #(.INVERTED_OUTPUT(0)) \n^~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:355: Cannot find file containing module: 'SN74LS298'\nSN74LS298 d3(.ws(m_w), .clk(n_c1), .reset(global_reset), .s1(d3_s1), .s2(d3_s2), .q(d3_q));\n^~~~~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:361: Cannot find file containing module: 'SN74LS298'\nSN74LS298 d4(.ws(m_w), .clk(n_c1), .reset(global_reset), .s1(d4_s1), .s2(d4_s2), .q(d4_q));\n^~~~~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:366: Cannot find file containing module: 'SN74LS257'\nSN74LS257 #(.INVERTED_OUTPUT(0)) \n^~~~~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:372: Cannot find file containing module: 'SN74LS257'\nSN74LS257 #(.INVERTED_OUTPUT(0)) \n^~~~~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:379: Cannot find file containing module: 'SN74LS374'\nSN74LS374 d8(.clk(z_c2), .reset(global_reset), .out_control(gnd), .data(d8_data), .out(d8_out));\n^~~~~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:386: Cannot find file containing module: 'IC82x6'\nIC82x6 #(.INVERTED_OUTPUT(1)) \n^~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:394: Cannot find file containing module: 'IC82x6'\nIC82x6 #(.INVERTED_OUTPUT(1)) \n^~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:398: Cannot find file containing module: 'SN74LS365'\nSN74LS365 #(.INVERTED_OUTPUT(0))\n^~~~~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:402: Cannot find file containing module: 'SN74LS365'\nSN74LS365 #(.INVERTED_OUTPUT(0))\n^~~~~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:406: Cannot find file containing module: 'SN74LS365'\nSN74LS365 #(.INVERTED_OUTPUT(1))\n^~~~~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:410: Cannot find file containing module: 'SN74LS07'\nSN74LS07 d18(.a6(d17_out[5]), .y6(f_tim),\n^~~~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:415: Cannot find file containing module: 'rw_trigger'\nrw_trigger rw_trig(.reset(global_reset), .clk(isa_clk), .ior(isa_ior), .iow(isa_iow), .r(q_r), .w(m_w));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:418: Cannot find file containing module: 'address_request_decoder'\naddress_request_decoder addr_decoder(.address(isa_addr), .ale(isa_ale), .aen(isa_aen), .ior(g_rd), .iow(p_wr), \n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/sm2201_interface_board.v:422: Cannot find file containing module: 'micro_program_automate'\nmicro_program_automate automate (.reset(global_reset), .clk(isa_clk), \n^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 16 error(s)\n"
module sm2201_interface_board(

    inout wire [7:0] isa_data,
    input wire isa_ale,
    input wire isa_aen,
    input wire isa_clk,
    output wire isa_chrdy,
    input wire isa_reset,
    input wire isa_ior,
    input wire isa_iow,
    input wire [9:0] isa_addr,
    output wire [7:0] isa_irq,

    inout wire [15:0] cb_data,
    input wire cb_prr,
    output wire cb_cx1,
    input wire cb_zk4,
    output wire [11:0] cb_addr,
    output wire cb_prepare_bus,
    output wire cb_b_b1,
    output wire cb_pc4,
    output wire cb_cx3,
    output wire q_r_debug
);

wire m_w;
wire n_c1;
wire k_sel2;
wire q_r;
wire d_sel;
wire z_c2;
wire x0;
wire x1;
wire rdy;


wire b_cxi;
wire b_cxi_pulled;
wire g_rd;
wire p_wr;
wire l_sel1;
wire v_rp;

wire [3:0] d1_di;
wire [3:0] d1_db;

wire [3:0] d2_di;
wire [3:0] d2_db;

wire [3:0] d3_s1;
wire [3:0] d3_s2;
wire [3:0] d3_q;

wire [3:0] d4_s1;
wire [3:0] d4_s2;
wire [3:0] d4_q;

wire [3:0] d6_a;
wire [3:0] d6_b;
wire [3:0] d6_y;

wire [3:0] d7_a;
wire [3:0] d7_b;
wire [3:0] d7_y;

wire [7:0] d8_data;
wire [7:0] d8_out;

wire [3:0] d11_di;
wire [3:0] d11_db;
wire [3:0] d11_do;

wire [3:0] d12_di;
wire [3:0] d12_db;
wire [3:0] d12_do;

wire [5:0] d13_data;
wire [5:0] d13_out;

wire [5:0] d14_data;
wire [5:0] d14_out;

wire [5:0] d17_data;
wire [5:0] d17_out;

wire [1:0] micro_program_automate_addr;
wire interrupt_en;

supply0 gnd;
supply1 vcc;

reg global_reset;
reg [7:0] counter;
reg [1:0] state;

localparam reg[7:0] RESET_COUNTER = 10;
localparam reg[1:0] INITIAL_STATE = 0;
localparam reg[1:0] BEGIN_INIT_STATE = 1;
localparam reg[1:0] INITED_STATE = 2;





assign d1_di[0] = d4_q[0];
assign d1_di[1] = d4_q[2];
assign d1_di[2] = d4_q[3];
assign d1_di[3] = d4_q[1];


assign d4_s1[0] = cb_data[4];
assign d4_s1[1] = cb_data[7];
assign d4_s1[2] = cb_data[6];
assign d4_s1[3] = cb_data[5];

assign d4_s2[0] = cb_data[12];
assign d4_s2[1] = cb_data[15];
assign d4_s2[2] = cb_data[14];
assign d4_s2[3] = cb_data[13];



assign d2_di[0] = d3_q[0];
assign d2_di[1] = d3_q[2];
assign d2_di[2] = d3_q[3];
assign d2_di[3] = d3_q[1];


assign d3_s1[0] = cb_data[1];
assign d3_s1[1] = cb_data[3];
assign d3_s1[2] = cb_data[2];
assign d3_s1[3] = cb_data[0];

assign d3_s2[0] = cb_data[9];
assign d3_s2[1] = cb_data[11];
assign d3_s2[2] = cb_data[10];
assign d3_s2[3] = cb_data[8];


assign d6_a[0] = d4_q[0];
assign d6_a[1] = d4_q[3];
assign d6_a[2] = d4_q[1];
assign d6_a[3] = d4_q[2];

assign d6_b[0] = cb_data[4];
assign d6_b[1] = cb_data[5];
assign d6_b[2] = cb_data[7];
assign d6_b[3] = cb_data[6];


assign d7_a[0] = d3_q[0];
assign d7_a[1] = d3_q[3];
assign d7_a[2] = d3_q[1];
assign d7_a[3] = d3_q[2];

assign d7_b[0] = cb_data[1];
assign d7_b[1] = cb_data[0];
assign d7_b[2] = cb_data[3];
assign d7_b[3] = cb_data[2];


assign d11_di[0] = d6_y[0];
assign d11_di[1] = d6_y[1];
assign d11_di[2] = d6_y[3];
assign d11_di[3] = d6_y[2];


assign d12_di[0] = d7_y[0];
assign d12_di[1] = d7_y[1];
assign d12_di[2] = d7_y[3];
assign d12_di[3] = d7_y[2];


assign d8_data[0] = cb_data[5];
assign d8_data[1] = cb_data[0];
assign d8_data[2] = cb_data[6];
assign d8_data[3] = cb_data[1];
assign d8_data[4] = cb_data[3];
assign d8_data[5] = cb_data[7];
assign d8_data[6] = cb_data[2];
assign d8_data[7] = cb_data[4];


assign d13_data[0] = vcc;
assign d13_data[1] = d8_out[0];
assign d13_data[2] = d8_out[2];
assign d13_data[3] = x0;
assign d13_data[4] = x1;
assign d13_data[5] = m_w;


assign d14_data[0] = d8_out[6];
assign d14_data[1] = d8_out[3];
assign d14_data[2] = d8_out[4];
assign d14_data[3] = d8_out[1];
assign d14_data[4] = d8_out[7];
assign d14_data[5] = vcc;


assign d17_data[0] = isa_addr[4];
assign d17_data[1] = isa_addr[3];
assign d17_data[2] = isa_addr[2];
assign d17_data[3] = isa_addr[1];
assign d17_data[4] = isa_reset;
assign d17_data[5] = rdy;



assign v_rp = d8_out[5];
assign g_rd = isa_ior;
assign p_wr = isa_iow;
assign b_cxi_pulled = b_cxi == 1'b0 ? b_cxi : 1'b1;




assign cb_addr[0] = gnd;
assign cb_addr[1] = d17_out[3];
assign cb_addr[2] = d17_out[2];
assign cb_addr[3] = d17_out[1];
assign cb_addr[4] = d17_out[0];
assign cb_addr[5] = d14_out[3];
assign cb_addr[6] = d14_out[1];
assign cb_addr[7] = d14_out[0];
assign cb_addr[8] = d14_out[2];
assign cb_addr[9] = d14_out[4];
assign cb_addr[10] = d13_out[1];
assign cb_addr[11] = d13_out[2];
assign cb_pc4 = d13_out[3];
assign cb_cx3 = d13_out[4];
assign cb_b_b1 = d13_out[5];
assign cb_prepare_bus = d17_out[4];
assign cb_cx1 = b_cxi_pulled;
assign isa_irq[7] = b_cxi_pulled == 1'b0 ? 1'b0: 1'b1;
assign isa_irq[0] = vcc;
assign isa_irq[1] = vcc;
assign isa_irq[2] = vcc;
assign isa_irq[3] = vcc;
assign isa_irq[4] = vcc;
assign isa_irq[5] = vcc;
assign isa_irq[6] = vcc;

assign cb_data[4] = d11_do[0];
assign cb_data[5] = d11_do[1];
assign cb_data[6] = d11_do[2];
assign cb_data[7] = d11_do[3];

assign cb_data[0] = d12_do[0];
assign cb_data[1] = d12_do[1];
assign cb_data[2] = d12_do[2];
assign cb_data[3] = d12_do[3];

assign cb_data[12] = d1_db[0];
assign cb_data[14] = d1_db[1];
assign cb_data[13] = d1_db[2];
assign cb_data[15] = d1_db[3];

assign cb_data[9] = d2_db[0];
assign cb_data[10] = d2_db[1];
assign cb_data[8] = d2_db[2];
assign cb_data[11] = d2_db[3];

assign isa_data[0] = d12_db[1];
assign isa_data[1] = d12_db[0];
assign isa_data[2] = d12_db[2];
assign isa_data[3] = d12_db[3];
assign isa_data[4] = d11_db[0];
assign isa_data[5] = d11_db[1];
assign isa_data[6] = d11_db[2];
assign isa_data[7] = d11_db[3];


assign q_r_debug = q_r;




IC82x6 #(.INVERTED_OUTPUT(0)) 
   d1 (.dce(gnd), .cs_n(m_w), .d_in(d1_di), .d_bus(d1_db));


IC82x6 #(.INVERTED_OUTPUT(0)) 
    d2 (.dce(gnd), .cs_n(m_w), .d_in(d2_di), .d_bus(d2_db));


SN74LS298 d3(.ws(m_w), .clk(n_c1), .reset(global_reset), .s1(d3_s1), .s2(d3_s2), .q(d3_q));


SN74LS298 d4(.ws(m_w), .clk(n_c1), .reset(global_reset), .s1(d4_s1), .s2(d4_s2), .q(d4_q));


SN74LS257 #(.INVERTED_OUTPUT(0)) 
    d6(.select(k_sel2), .out_control(gnd), .a(d6_a), .b(d6_b), .y(d6_y));


SN74LS257 #(.INVERTED_OUTPUT(0)) 
    d7(.select(k_sel2), .out_control(gnd), .a(d7_a), .b(d7_b), .y(d7_y));


SN74LS374 d8(.clk(z_c2), .reset(global_reset), .out_control(gnd), .data(d8_data), .out(d8_out));


IC82x6 #(.INVERTED_OUTPUT(1)) 
    d11 (.dce(q_r), .cs_n(d_sel), .d_in(d11_di), .d_bus(d11_db), .d_out(d11_do));
 

IC82x6 #(.INVERTED_OUTPUT(1)) 
    d12 (.dce(q_r), .cs_n(d_sel), .d_in(d12_di), .d_bus(d12_db), .d_out(d12_do));


SN74LS365 #(.INVERTED_OUTPUT(0))
    d13(.e1(gnd), .e2(gnd), .data(d13_data), .out(d13_out));


SN74LS365 #(.INVERTED_OUTPUT(0))
    d14(.e1(l_sel1), .e2(l_sel1), .data(d14_data), .out(d14_out));


SN74LS365 #(.INVERTED_OUTPUT(1))
    d17(.e1(gnd), .e2(gnd), .data(d17_data), .out(d17_out));


SN74LS07 d18(.a6(d17_out[5]), .y6(f_tim),
             .a3(cb_prr), .y3(b_cxi),
             .a1(rdy), .y1(isa_chrdy)
             );

rw_trigger rw_trig(.reset(global_reset), .clk(isa_clk), .ior(isa_ior), .iow(isa_iow), .r(q_r), .w(m_w));


address_request_decoder addr_decoder(.address(isa_addr), .ale(isa_ale), .aen(isa_aen), .ior(g_rd), .iow(p_wr), 
                                     .interrupt_req(v_rp), .zk4(cb_zk4), .sel(d_sel), .sel1(l_sel1), 
                                     .internal_address(micro_program_automate_addr), .interrupt_en(interrupt_en));

micro_program_automate automate (.reset(global_reset), .clk(isa_clk), 
                                 .a(micro_program_automate_addr), .w(m_w), .sel(d_sel), .tim(f_tim),
                                 .ie(interrupt_en), .cx1(b_cxi_pulled),
                                 .rdy(rdy), .c1(n_c1), .c2(z_c2), .sel2(k_sel2), .x0(x0), .x1(x1));

always @(posedge isa_clk)
begin
    case (state)
        INITIAL_STATE:
        begin
            if (counter == 1)
            begin
                state <= BEGIN_INIT_STATE;
            end
        end
        BEGIN_INIT_STATE:
        begin
            if (counter == RESET_COUNTER)
                state <= INITED_STATE;
        end
        INITED_STATE:
        begin
            state <= INITED_STATE;
        end
        default:
        begin
             state <= INITIAL_STATE;
        end
    endcase
end

always @(posedge isa_clk)
begin
    if(state == INITIAL_STATE)
    begin
        counter <= 1;
    end
    else if (state == BEGIN_INIT_STATE)
    begin
        counter <= counter + 1;
        global_reset <= 1;
    end
    else
    begin
        global_reset <= 0;
    end
end

endmodule
module sm2201_interface_board(

    inout wire [7:0] isa_data,
    input wire isa_ale,
    input wire isa_aen,
    input wire isa_clk,
    output wire isa_chrdy,
    input wire isa_reset,
    input wire isa_ior,
    input wire isa_iow,
    input wire [9:0] isa_addr,
    output wire [7:0] isa_irq,

    inout wire [15:0] cb_data,
    input wire cb_prr,
    output wire cb_cx1,
    input wire cb_zk4,
    output wire [11:0] cb_addr,
    output wire cb_prepare_bus,
    output wire cb_b_b1,
    output wire cb_pc4,
    output wire cb_cx3,
    output wire q_r_debug
);


wire m_w;
wire n_c1;
wire k_sel2;
wire q_r;
wire d_sel;
wire z_c2;
wire x0;
wire x1;
wire rdy;


wire b_cxi;
wire b_cxi_pulled;
wire g_rd;
wire p_wr;
wire l_sel1;
wire v_rp;

wire [3:0] d1_di;
wire [3:0] d1_db;

wire [3:0] d2_di;
wire [3:0] d2_db;

wire [3:0] d3_s1;
wire [3:0] d3_s2;
wire [3:0] d3_q;

wire [3:0] d4_s1;
wire [3:0] d4_s2;
wire [3:0] d4_q;

wire [3:0] d6_a;
wire [3:0] d6_b;
wire [3:0] d6_y;

wire [3:0] d7_a;
wire [3:0] d7_b;
wire [3:0] d7_y;

wire [7:0] d8_data;
wire [7:0] d8_out;

wire [3:0] d11_di;
wire [3:0] d11_db;
wire [3:0] d11_do;

wire [3:0] d12_di;
wire [3:0] d12_db;
wire [3:0] d12_do;

wire [5:0] d13_data;
wire [5:0] d13_out;

wire [5:0] d14_data;
wire [5:0] d14_out;

wire [5:0] d17_data;
wire [5:0] d17_out;

wire [1:0] micro_program_automate_addr;
wire interrupt_en;

supply0 gnd;
supply1 vcc;

reg global_reset;
reg [7:0] counter;
reg [1:0] state;

localparam reg[7:0] RESET_COUNTER = 10;
localparam reg[1:0] INITIAL_STATE = 0;
localparam reg[1:0] BEGIN_INIT_STATE = 1;
localparam reg[1:0] INITED_STATE = 2;





assign d1_di[0] = d4_q[0];
assign d1_di[1] = d4_q[2];
assign d1_di[2] = d4_q[3];
assign d1_di[3] = d4_q[1];


assign d4_s1[0] = cb_data[4];
assign d4_s1[1] = cb_data[7];
assign d4_s1[2] = cb_data[6];
assign d4_s1[3] = cb_data[5];

assign d4_s2[0] = cb_data[12];
assign d4_s2[1] = cb_data[15];
assign d4_s2[2] = cb_data[14];
assign d4_s2[3] = cb_data[13];



assign d2_di[0] = d3_q[0];
assign d2_di[1] = d3_q[2];
assign d2_di[2] = d3_q[3];
assign d2_di[3] = d3_q[1];


assign d3_s1[0] = cb_data[1];
assign d3_s1[1] = cb_data[3];
assign d3_s1[2] = cb_data[2];
assign d3_s1[3] = cb_data[0];

assign d3_s2[0] = cb_data[9];
assign d3_s2[1] = cb_data[11];
assign d3_s2[2] = cb_data[10];
assign d3_s2[3] = cb_data[8];


assign d6_a[0] = d4_q[0];
assign d6_a[1] = d4_q[3];
assign d6_a[2] = d4_q[1];
assign d6_a[3] = d4_q[2];

assign d6_b[0] = cb_data[4];
assign d6_b[1] = cb_data[5];
assign d6_b[2] = cb_data[7];
assign d6_b[3] = cb_data[6];


assign d7_a[0] = d3_q[0];
assign d7_a[1] = d3_q[3];
assign d7_a[2] = d3_q[1];
assign d7_a[3] = d3_q[2];

assign d7_b[0] = cb_data[1];
assign d7_b[1] = cb_data[0];
assign d7_b[2] = cb_data[3];
assign d7_b[3] = cb_data[2];


assign d11_di[0] = d6_y[0];
assign d11_di[1] = d6_y[1];
assign d11_di[2] = d6_y[3];
assign d11_di[3] = d6_y[2];


assign d12_di[0] = d7_y[0];
assign d12_di[1] = d7_y[1];
assign d12_di[2] = d7_y[3];
assign d12_di[3] = d7_y[2];


assign d8_data[0] = cb_data[5];
assign d8_data[1] = cb_data[0];
assign d8_data[2] = cb_data[6];
assign d8_data[3] = cb_data[1];
assign d8_data[4] = cb_data[3];
assign d8_data[5] = cb_data[7];
assign d8_data[6] = cb_data[2];
assign d8_data[7] = cb_data[4];


assign d13_data[0] = vcc;
assign d13_data[1] = d8_out[0];
assign d13_data[2] = d8_out[2];
assign d13_data[3] = x0;
assign d13_data[4] = x1;
assign d13_data[5] = m_w;


assign d14_data[0] = d8_out[6];
assign d14_data[1] = d8_out[3];
assign d14_data[2] = d8_out[4];
assign d14_data[3] = d8_out[1];
assign d14_data[4] = d8_out[7];
assign d14_data[5] = vcc;


assign d17_data[0] = isa_addr[4];
assign d17_data[1] = isa_addr[3];
assign d17_data[2] = isa_addr[2];
assign d17_data[3] = isa_addr[1];
assign d17_data[4] = isa_reset;
assign d17_data[5] = rdy;



assign v_rp = d8_out[5];
assign g_rd = isa_ior;
assign p_wr = isa_iow;
assign b_cxi_pulled = b_cxi == 1'b0 ? b_cxi : 1'b1;




assign cb_addr[0] = gnd;
assign cb_addr[1] = d17_out[3];
assign cb_addr[2] = d17_out[2];
assign cb_addr[3] = d17_out[1];
assign cb_addr[4] = d17_out[0];
assign cb_addr[5] = d14_out[3];
assign cb_addr[6] = d14_out[1];
assign cb_addr[7] = d14_out[0];
assign cb_addr[8] = d14_out[2];
assign cb_addr[9] = d14_out[4];
assign cb_addr[10] = d13_out[1];
assign cb_addr[11] = d13_out[2];
assign cb_pc4 = d13_out[3];
assign cb_cx3 = d13_out[4];
assign cb_b_b1 = d13_out[5];
assign cb_prepare_bus = d17_out[4];
assign cb_cx1 = b_cxi_pulled;
assign isa_irq[7] = b_cxi_pulled == 1'b0 ? 1'b0: 1'b1;
assign isa_irq[0] = vcc;
assign isa_irq[1] = vcc;
assign isa_irq[2] = vcc;
assign isa_irq[3] = vcc;
assign isa_irq[4] = vcc;
assign isa_irq[5] = vcc;
assign isa_irq[6] = vcc;

assign cb_data[4] = d11_do[0];
assign cb_data[5] = d11_do[1];
assign cb_data[6] = d11_do[2];
assign cb_data[7] = d11_do[3];

assign cb_data[0] = d12_do[0];
assign cb_data[1] = d12_do[1];
assign cb_data[2] = d12_do[2];
assign cb_data[3] = d12_do[3];

assign cb_data[12] = d1_db[0];
assign cb_data[14] = d1_db[1];
assign cb_data[13] = d1_db[2];
assign cb_data[15] = d1_db[3];

assign cb_data[9] = d2_db[0];
assign cb_data[10] = d2_db[1];
assign cb_data[8] = d2_db[2];
assign cb_data[11] = d2_db[3];

assign isa_data[0] = d12_db[1];
assign isa_data[1] = d12_db[0];
assign isa_data[2] = d12_db[2];
assign isa_data[3] = d12_db[3];
assign isa_data[4] = d11_db[0];
assign isa_data[5] = d11_db[1];
assign isa_data[6] = d11_db[2];
assign isa_data[7] = d11_db[3];


assign q_r_debug = q_r;




IC82x6 #(.INVERTED_OUTPUT(0)) 
   d1 (.dce(gnd), .cs_n(m_w), .d_in(d1_di), .d_bus(d1_db));


IC82x6 #(.INVERTED_OUTPUT(0)) 
    d2 (.dce(gnd), .cs_n(m_w), .d_in(d2_di), .d_bus(d2_db));


SN74LS298 d3(.ws(m_w), .clk(n_c1), .reset(global_reset), .s1(d3_s1), .s2(d3_s2), .q(d3_q));


SN74LS298 d4(.ws(m_w), .clk(n_c1), .reset(global_reset), .s1(d4_s1), .s2(d4_s2), .q(d4_q));


SN74LS257 #(.INVERTED_OUTPUT(0)) 
    d6(.select(k_sel2), .out_control(gnd), .a(d6_a), .b(d6_b), .y(d6_y));


SN74LS257 #(.INVERTED_OUTPUT(0)) 
    d7(.select(k_sel2), .out_control(gnd), .a(d7_a), .b(d7_b), .y(d7_y));


SN74LS374 d8(.clk(z_c2), .reset(global_reset), .out_control(gnd), .data(d8_data), .out(d8_out));


IC82x6 #(.INVERTED_OUTPUT(1)) 
    d11 (.dce(q_r), .cs_n(d_sel), .d_in(d11_di), .d_bus(d11_db), .d_out(d11_do));
 

IC82x6 #(.INVERTED_OUTPUT(1)) 
    d12 (.dce(q_r), .cs_n(d_sel), .d_in(d12_di), .d_bus(d12_db), .d_out(d12_do));


SN74LS365 #(.INVERTED_OUTPUT(0))
    d13(.e1(gnd), .e2(gnd), .data(d13_data), .out(d13_out));


SN74LS365 #(.INVERTED_OUTPUT(0))
    d14(.e1(l_sel1), .e2(l_sel1), .data(d14_data), .out(d14_out));


SN74LS365 #(.INVERTED_OUTPUT(1))
    d17(.e1(gnd), .e2(gnd), .data(d17_data), .out(d17_out));


SN74LS07 d18(.a6(d17_out[5]), .y6(f_tim),
             .a3(cb_prr), .y3(b_cxi),
             .a1(rdy), .y1(isa_chrdy)
             );

rw_trigger rw_trig(.reset(global_reset), .clk(isa_clk), .ior(isa_ior), .iow(isa_iow), .r(q_r), .w(m_w));


address_request_decoder addr_decoder(.address(isa_addr), .ale(isa_ale), .aen(isa_aen), .ior(g_rd), .iow(p_wr), 
                                     .interrupt_req(v_rp), .zk4(cb_zk4), .sel(d_sel), .sel1(l_sel1), 
                                     .internal_address(micro_program_automate_addr), .interrupt_en(interrupt_en));

micro_program_automate automate (.reset(global_reset), .clk(isa_clk), 
                                 .a(micro_program_automate_addr), .w(m_w), .sel(d_sel), .tim(f_tim),
                                 .ie(interrupt_en), .cx1(b_cxi_pulled),
                                 .rdy(rdy), .c1(n_c1), .c2(z_c2), .sel2(k_sel2), .x0(x0), .x1(x1));

always @(posedge isa_clk)
begin
    case (state)
        INITIAL_STATE:
        begin
            if (counter == 1)
            begin
                state <= BEGIN_INIT_STATE;
            end
        end
        BEGIN_INIT_STATE:
        begin
            if (counter == RESET_COUNTER)
                state <= INITED_STATE;
        end
        INITED_STATE:
        begin
            state <= INITED_STATE;
        end
        default:
        begin
             state <= INITIAL_STATE;
        end
    endcase
end

always @(posedge isa_clk)
begin
    if(state == INITIAL_STATE)
    begin
        counter <= 1;
    end
    else if (state == BEGIN_INIT_STATE)
    begin
        counter <= counter + 1;
        global_reset <= 1;
    end
    else
    begin
        global_reset <= 0;
    end
end

endmodule