data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/cavlc_len_gen.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/cavlc_len_gen.v:40: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl,data/full_repos/permissive/137416811/defines.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl,data/full_repos/permissive/137416811/defines.v.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl,data/full_repos/permissive/137416811/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/cavlc_len_gen.v:72: Define or directive not defined: \'`cavlc_read_total_coeffs_bit\'\n    cavlc_state[`cavlc_read_total_coeffs_bit]  : len_comb <= len_read_total_coeffs_comb;\n                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/cavlc_len_gen.v:72: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    cavlc_state[`cavlc_read_total_coeffs_bit]  : len_comb <= len_read_total_coeffs_comb;\n                                            ^\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/cavlc_len_gen.v:73: Define or directive not defined: \'`cavlc_read_t1s_flags_bit\'\n    cavlc_state[`cavlc_read_t1s_flags_bit],  \n                ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/cavlc_len_gen.v:74: Define or directive not defined: \'`cavlc_read_level_prefix_bit\'\n    cavlc_state[`cavlc_read_level_prefix_bit],\n                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/cavlc_len_gen.v:75: Define or directive not defined: \'`cavlc_read_level_suffix_bit\'\n    cavlc_state[`cavlc_read_level_suffix_bit]  : len_comb <= len_read_levels_comb;       \n                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/cavlc_len_gen.v:76: Define or directive not defined: \'`cavlc_read_total_zeros_bit\'\n    cavlc_state[`cavlc_read_total_zeros_bit]   : len_comb <= len_read_total_zeros_comb;\n                ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/cavlc_len_gen.v:77: Define or directive not defined: \'`cavlc_read_run_befores_bit\'\n    cavlc_state[`cavlc_read_run_befores_bit]   : len_comb <= len_read_run_befores_comb;\n                ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/cavlc_len_gen.v:78: Define or directive not defined: \'`cavlc_calc_level_bit\'\n    cavlc_state[`cavlc_calc_level_bit],\n                ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/cavlc_len_gen.v:79: Define or directive not defined: \'`cavlc_idle_bit\'\n    cavlc_state[`cavlc_idle_bit]               : len_comb <= 0;\n                ^~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module cavlc_len_gen
(
    cavlc_state,
    len_read_total_coeffs_comb,
    len_read_levels_comb,
    len_read_total_zeros_comb,
    len_read_run_befores_comb,
    len_comb
);



input  [7:0] cavlc_state;
input  [4:0] len_read_total_coeffs_comb;
input  [4:0] len_read_levels_comb;
input  [3:0] len_read_total_zeros_comb;
input  [3:0] len_read_run_befores_comb;

output [4:0] len_comb;




reg [4:0] len_comb;




always @ (*)
case (1'b1)
    cavlc_state[`cavlc_read_total_coeffs_bit]  : len_comb <= len_read_total_coeffs_comb;
    cavlc_state[`cavlc_read_t1s_flags_bit],  
    cavlc_state[`cavlc_read_level_prefix_bit],
    cavlc_state[`cavlc_read_level_suffix_bit]  : len_comb <= len_read_levels_comb;       
    cavlc_state[`cavlc_read_total_zeros_bit]   : len_comb <= len_read_total_zeros_comb;
    cavlc_state[`cavlc_read_run_befores_bit]   : len_comb <= len_read_run_befores_comb;
    cavlc_state[`cavlc_calc_level_bit],
    cavlc_state[`cavlc_idle_bit]               : len_comb <= 0;
    default                                    : len_comb <= 'bx;
endcase

endmodule
module cavlc_len_gen
(
    cavlc_state,
    len_read_total_coeffs_comb,
    len_read_levels_comb,
    len_read_total_zeros_comb,
    len_read_run_befores_comb,
    len_comb
);




input  [7:0] cavlc_state;
input  [4:0] len_read_total_coeffs_comb;
input  [4:0] len_read_levels_comb;
input  [3:0] len_read_total_zeros_comb;
input  [3:0] len_read_run_befores_comb;

output [4:0] len_comb;




reg [4:0] len_comb;




always @ (*)
case (1'b1)
    cavlc_state[`cavlc_read_total_coeffs_bit]  : len_comb <= len_read_total_coeffs_comb;
    cavlc_state[`cavlc_read_t1s_flags_bit],  
    cavlc_state[`cavlc_read_level_prefix_bit],
    cavlc_state[`cavlc_read_level_suffix_bit]  : len_comb <= len_read_levels_comb;       
    cavlc_state[`cavlc_read_total_zeros_bit]   : len_comb <= len_read_total_zeros_comb;
    cavlc_state[`cavlc_read_run_befores_bit]   : len_comb <= len_read_run_befores_comb;
    cavlc_state[`cavlc_calc_level_bit],
    cavlc_state[`cavlc_idle_bit]               : len_comb <= 0;
    default                                    : len_comb <= 'bx;
endcase

endmodule