data/full_repos/permissive/201488448/3_verification/2_tb/1_clk.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/201488448/3_verification/2_tb/1_clk.v:6: Unsupported: Ignoring delay on this delayed statement.\n       #0 clk = 0; \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/201488448/3_verification/2_tb/1_clk.v:10: Unsupported: Ignoring delay on this delayed statement.\n       #5 clk = ~clk; \n       ^\n%Error: data/full_repos/permissive/201488448/3_verification/2_tb/1_clk.v:13: Cannot find file containing module: \'dut\'\n    dut dut1(clk);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/201488448/3_verification/2_tb,data/full_repos/permissive/201488448/dut\n             data/full_repos/permissive/201488448/3_verification/2_tb,data/full_repos/permissive/201488448/dut.v\n             data/full_repos/permissive/201488448/3_verification/2_tb,data/full_repos/permissive/201488448/dut.sv\n             dut\n             dut.v\n             dut.sv\n             obj_dir/dut\n             obj_dir/dut.v\n             obj_dir/dut.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_module ( );

    reg clk;
    initial begin
       #0 clk = 0; 
    end
    
    always begin
       #5 clk = ~clk; 
    end
    
    dut dut1(clk);
    
endmodule
module top_module ( );


    reg clk;
    initial begin
       #0 clk = 0; 
    end
    
    always begin
       #5 clk = ~clk; 
    end
    
    dut dut1(clk);
    
endmodule