data/full_repos/permissive/129127690/mem_1M.v
1: b"%Error: data/full_repos/permissive/129127690/mem_1M.v:15: Cannot find file containing module: 'demux_3_8'\n demux_3_8 #(2) demux(dira[17:15],mem_action_val,mem_action[0],mem_action[1],mem_action[2],mem_action[3],mem_action[4],\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/demux_3_8\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/demux_3_8.v\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/demux_3_8.sv\n             demux_3_8\n             demux_3_8.v\n             demux_3_8.sv\n             obj_dir/demux_3_8\n             obj_dir/demux_3_8.v\n             obj_dir/demux_3_8.sv\n%Error: data/full_repos/permissive/129127690/mem_1M.v:17: Cannot find file containing module: 'mux_8_3'\n mux_8_3 #(32) mux(mem_blk[0],mem_blk[1],mem_blk[2],mem_blk[3],mem_blk[4],mem_blk[5],mem_blk[6],mem_blk[7],dira[17:15],out); \n ^~~~~~~\n%Error: data/full_repos/permissive/129127690/mem_1M.v:23: Cannot find file containing module: 'mem_128k'\n   mem_128k mem_piece(dira[14:0],write_data,clk,mem_action[i][0],mem_action[i][1], mem_blk[i]);\n   ^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module mem_1M
	(input[17:0] dira,
	input[31:0] write_data,
	input clk, memwrite, memread,
	output[31:0] out);
	
	
	wire [1:0] mem_action [0:7];
	wire [31:0] mem_blk [0:7];
	wire [1:0] mem_action_val;
	assign mem_action_val[0] = memwrite;
	assign mem_action_val[1] = memread;
	
	demux_3_8 #(2) demux(dira[17:15],mem_action_val,mem_action[0],mem_action[1],mem_action[2],mem_action[3],mem_action[4],
		mem_action[5],mem_action[6],mem_action[7]); 
	mux_8_3 #(32) mux(mem_blk[0],mem_blk[1],mem_blk[2],mem_blk[3],mem_blk[4],mem_blk[5],mem_blk[6],mem_blk[7],dira[17:15],out); 
	
	
	genvar i;
	generate 
		for (i = 0; i < 8; i = i+1) begin:forloop
			mem_128k mem_piece(dira[14:0],write_data,clk,mem_action[i][0],mem_action[i][1], mem_blk[i]);
		end
	
	endgenerate
	
	
endmodule
module mem_1M
	(input[17:0] dira,
	input[31:0] write_data,
	input clk, memwrite, memread,
	output[31:0] out);

	
	
	wire [1:0] mem_action [0:7];
	wire [31:0] mem_blk [0:7];
	wire [1:0] mem_action_val;
	assign mem_action_val[0] = memwrite;
	assign mem_action_val[1] = memread;
	
	demux_3_8 #(2) demux(dira[17:15],mem_action_val,mem_action[0],mem_action[1],mem_action[2],mem_action[3],mem_action[4],
		mem_action[5],mem_action[6],mem_action[7]); 
	mux_8_3 #(32) mux(mem_blk[0],mem_blk[1],mem_blk[2],mem_blk[3],mem_blk[4],mem_blk[5],mem_blk[6],mem_blk[7],dira[17:15],out); 
	
	
	genvar i;
	generate 
		for (i = 0; i < 8; i = i+1) begin:forloop
			mem_128k mem_piece(dira[14:0],write_data,clk,mem_action[i][0],mem_action[i][1], mem_blk[i]);
		end
	
	endgenerate
	
	
endmodule