data/full_repos/permissive/143278/ivltests/br978.v
 line:9: before: "$"
1: b'%Error: data/full_repos/permissive/143278/ivltests/br978.v:6: Unsupported or unknown PLI call: $ivlh_to_unsigned\nassign result = data + $ivlh_to_unsigned(8, 16);\n                       ^~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br978.v:9: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("result = %0d", result);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

wire [15:0] data = 8;
wire [15:0] result;

assign result = data + $ivlh_to_unsigned(8, 16);

initial begin
  #1 $display("result = %0d", result);
  if (result === 16)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module test();


wire [15:0] data = 8;
wire [15:0] result;

assign result = data + $ivlh_to_unsigned(8, 16);

initial begin
  #1 $display("result = %0d", result);
  if (result === 16)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule