data/full_repos/permissive/212763527/school_project/16_Mealy/sources/main.v
1: b"%Error: data/full_repos/permissive/212763527/school_project/16_Mealy/sources/main.v:19: Cannot find file containing module: 'debkey'\n    debkey #(T50MS) udeb(clk, btnclk, btnclk_d);\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/school_project/16_Mealy/sources,data/full_repos/permissive/212763527/debkey\n             data/full_repos/permissive/212763527/school_project/16_Mealy/sources,data/full_repos/permissive/212763527/debkey.v\n             data/full_repos/permissive/212763527/school_project/16_Mealy/sources,data/full_repos/permissive/212763527/debkey.sv\n             debkey\n             debkey.v\n             debkey.sv\n             obj_dir/debkey\n             obj_dir/debkey.v\n             obj_dir/debkey.sv\n%Error: data/full_repos/permissive/212763527/school_project/16_Mealy/sources/main.v:28: Cannot find file containing module: 'par2ser'\npar2ser up2s (din, read, rst, btnclk_d, X);\n^~~~~~~\n%Error: data/full_repos/permissive/212763527/school_project/16_Mealy/sources/main.v:33: Cannot find file containing module: 'mealy'\nmealy umly (btnclk_d, rst, X, Y);\n^~~~~\n%Error: Exiting due to 3 error(s)\n"
module main #(parameter T50MS = 50*10**5)
             (input [7:0] din,
              input read,
              input rst,
              input clk,
              input btnclk,
              output ldrst,
              output ldclk,
              output ldres);


wire btnclk_d;
if (T50MS == 0)

    assign btnclk_d = btnclk;
else

    debkey #(T50MS) udeb(clk, btnclk, btnclk_d);


assign ldclk = btnclk_d;

assign ldrst = rst;


wire X;
par2ser up2s (din, read, rst, btnclk_d, X);


wire Y;
assign ldres = Y;
mealy umly (btnclk_d, rst, X, Y);

endmodule
module main #(parameter T50MS = 50*10**5)
             (input [7:0] din,
              input read,
              input rst,
              input clk,
              input btnclk,
              output ldrst,
              output ldclk,
              output ldres);



wire btnclk_d;
if (T50MS == 0)

    assign btnclk_d = btnclk;
else

    debkey #(T50MS) udeb(clk, btnclk, btnclk_d);


assign ldclk = btnclk_d;

assign ldrst = rst;


wire X;
par2ser up2s (din, read, rst, btnclk_d, X);


wire Y;
assign ldres = Y;
mealy umly (btnclk_d, rst, X, Y);

endmodule