data/full_repos/permissive/20688874/viterbi/viterbidec.v
1: b'%Error: data/full_repos/permissive/20688874/viterbi/viterbidec.v:25: Cannot find include file: acs.v\n`include "acs.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/acs.v\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/acs.v.v\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/acs.v.sv\n             acs.v\n             acs.v.v\n             acs.v.sv\n             obj_dir/acs.v\n             obj_dir/acs.v.v\n             obj_dir/acs.v.sv\n%Error: data/full_repos/permissive/20688874/viterbi/viterbidec.v:26: Cannot find include file: bmu.v\n`include "bmu.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/20688874/viterbi/viterbidec.v:27: Cannot find include file: pmsm.v\n`include "pmsm.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/20688874/viterbi/viterbidec.v:28: Cannot find include file: spd.v\n`include "spd.v" \n         ^~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module viterbi_decoder (d, cx, clk, reset);


	output d;
	
	
	
	
	


	input [1:0] cx;

	input clk;

	input reset;
	
	
	
	
	





	





	


	
	
	


	wire d;
	

	wire [1:0] brch_met0,brch_met1,brch_met2,brch_met3;
	wire [1:0] brch_met4,brch_met5,brch_met6,brch_met7;
	


	wire d0,d1,d2,d3;

	wire [3:0] n_pm0,n_pm1,n_pm2,n_pm3;
	

	wire [3:0] p_m0, p_m1, p_m2, p_m3;
	
	
	

	
	
	

	

	

	bmu brch_met (cx[0], cx[1],
		brch_met0,brch_met1,brch_met2,brch_met3,
		brch_met4,brch_met5,brch_met6,brch_met7);
	

	

	 

	add_compare_select acs0 (n_pm0, d0,
		p_m0, brch_met0, p_m1, brch_met2);

	add_compare_select acs1 (n_pm1, d1,
		p_m2, brch_met4, p_m3, brch_met6);

	add_compare_select acs2 (n_pm2, d2,
		p_m0, brch_met1, p_m1, brch_met3);

	add_compare_select acs3 (n_pm3, d3,
		p_m2, brch_met5, p_m3, brch_met7);
		

	

	pmsm path_metric_sm (n_pm0, n_pm1, n_pm2, n_pm3,
		p_m0, p_m1, p_m2, p_m3, clk, reset);
	

	

	spd survivor_path_dec (d0, d1, d2, d3, p_m0, p_m1, p_m2, p_m3,
		d, clk, reset);
	
endmodule
module viterbi_decoder (d, cx, clk, reset);



	output d;
	
	
	
	
	


	input [1:0] cx;

	input clk;

	input reset;
	
	
	
	
	





	





	


	
	
	


	wire d;
	

	wire [1:0] brch_met0,brch_met1,brch_met2,brch_met3;
	wire [1:0] brch_met4,brch_met5,brch_met6,brch_met7;
	


	wire d0,d1,d2,d3;

	wire [3:0] n_pm0,n_pm1,n_pm2,n_pm3;
	

	wire [3:0] p_m0, p_m1, p_m2, p_m3;
	
	
	

	
	
	

	

	

	bmu brch_met (cx[0], cx[1],
		brch_met0,brch_met1,brch_met2,brch_met3,
		brch_met4,brch_met5,brch_met6,brch_met7);
	

	

	 

	add_compare_select acs0 (n_pm0, d0,
		p_m0, brch_met0, p_m1, brch_met2);

	add_compare_select acs1 (n_pm1, d1,
		p_m2, brch_met4, p_m3, brch_met6);

	add_compare_select acs2 (n_pm2, d2,
		p_m0, brch_met1, p_m1, brch_met3);

	add_compare_select acs3 (n_pm3, d3,
		p_m2, brch_met5, p_m3, brch_met7);
		

	

	pmsm path_metric_sm (n_pm0, n_pm1, n_pm2, n_pm3,
		p_m0, p_m1, p_m2, p_m3, clk, reset);
	

	

	spd survivor_path_dec (d0, d1, d2, d3, p_m0, p_m1, p_m2, p_m3,
		d, clk, reset);
	
endmodule