data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v
 line:44: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:29: Unsupported: Ignoring delay on this delayed statement.\n always #(period/2) clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:36: Unsupported or unknown PLI call: $fsdbDumpfile\n   $fsdbDumpfile("fifo.fsdb");\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:38: Unsupported or unknown PLI call: $fsdbDumpvars\n  $fsdbDumpvars;\n  ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #(period);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #(delay)  rst_n = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #(period*4) rst_n = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #(period*2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d1);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d3);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d4);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d5);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #(period) invalid;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #(period) invalid;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #(period) invalid;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d6);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d7);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d8);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d9);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d11);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d12);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d13);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #(period) invalid;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d14);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d15);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d16);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d17);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d18);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d19);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d20);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d21);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d22);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d23);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d24);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d25);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d26);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d27);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d28);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d29);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d30);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d31);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d32);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d33);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d34);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d35);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d36);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d37);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d38);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d39);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d40);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d41);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d42);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d43);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d44);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #(period) pushing(8\'d45);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:138: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:140: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:141: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:142: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:143: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #(period) popping;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:146: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #(period) idle;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/101062124_hw4/fifo_t.v:149: Unsupported: Ignoring delay on this delayed statement.\n  #(period*4);\n  ^\n%Error: Exiting due to 2 error(s), 101 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stimulus;
	parameter period = 20;
	parameter delay = 2;



	reg clk, rst_n, push, pop;
	reg [7:0] datain;
	wire empty, almost_empty, full, almost_full, error;
	wire [7:0] dataout;

	fifo fifo1 (
					clk,
					rst_n,
					push,
					pop,
					datain,
					empty,
					almost_empty,
					full,
					almost_full,
					error,
					dataout
			   );

	always #(period/2) clk = ~clk;

	initial begin
		`ifdef NETLIST
			$sdf_annotate("fifo_syn.sdf", fifo1);
			$fsdbDumpfile("fifo_syn.fsdb");
		`else
			$fsdbDumpfile("fifo.fsdb");
		`endif
		$fsdbDumpvars;
	end

	initial begin
		clk = 1;
		rst_n = 1;
		idle;
		#(period);
		#(delay)  rst_n = 0;
		#(period*4) rst_n = 1;


		#(period*2);

		#(period) popping;
		#(period) idle;
		#(period) pushing(8'd1);
		#(period) idle;
		#(period) pushing(8'd2);
		#(period) pushing(8'd3);
		#(period) pushing(8'd4);
		#(period) popping;
		#(period) pushing(8'd5);
		#(period) popping;
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) idle;
		#(period) invalid;
		#(period) invalid;
		#(period) idle;
		#(period) idle;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) invalid;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) pushing(8'd6);
		#(period) pushing(8'd7);
		#(period) pushing(8'd8);
		#(period) pushing(8'd9);
		#(period) pushing(8'd11);
		#(period) pushing(8'd12);
		#(period) pushing(8'd13);
		#(period) idle;
		#(period) invalid;
		#(period) idle;
		#(period) pushing(8'd14);
		#(period) pushing(8'd15);
		#(period) pushing(8'd16);
		#(period) pushing(8'd17);
		#(period) pushing(8'd18);
		#(period) pushing(8'd19);
		#(period) pushing(8'd20);
		#(period) pushing(8'd21);
		#(period) pushing(8'd22);
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) pushing(8'd23);
		#(period) pushing(8'd24);
		#(period) pushing(8'd25);
		#(period) pushing(8'd26);
		#(period) pushing(8'd27);
		#(period) pushing(8'd28);
		#(period) pushing(8'd29);
		#(period) pushing(8'd30);
		#(period) idle;
		#(period) pushing(8'd31);
		#(period) pushing(8'd32);
		#(period) pushing(8'd33);
		#(period) pushing(8'd34);
		#(period) pushing(8'd35);
		#(period) pushing(8'd36);
		#(period) pushing(8'd37);
		#(period) pushing(8'd38);
		#(period) pushing(8'd39);
		#(period) pushing(8'd40);
		#(period) pushing(8'd41);
		#(period) pushing(8'd42);
		#(period) pushing(8'd43);
		#(period) pushing(8'd44);
		#(period) pushing(8'd45);
		#(period) idle;
		#(period) idle;
		#(period) idle;
		#(period) idle;
		#(period) idle;

		#(period) popping;
		#(period) idle;
		#(period) idle;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;

		#(period) idle;
		#(period*4);
		$finish;
	end


	task idle;
		begin
			push = 0;
			pop = 0;
			datain = 8'b0;
		end
	endtask
	task pushing;
		input [7:0] data;
		begin
			push = 1;
			pop = 0;
			datain = data;
		end
	endtask
	task popping;
		begin
			push = 0;
			pop = 1;
		end
	endtask
	task invalid;
		begin
			push = 1;
			pop = 1;
		end
	endtask
endmodule
module stimulus;

	parameter period = 20;
	parameter delay = 2;



	reg clk, rst_n, push, pop;
	reg [7:0] datain;
	wire empty, almost_empty, full, almost_full, error;
	wire [7:0] dataout;

	fifo fifo1 (
					clk,
					rst_n,
					push,
					pop,
					datain,
					empty,
					almost_empty,
					full,
					almost_full,
					error,
					dataout
			   );

	always #(period/2) clk = ~clk;

	initial begin
		`ifdef NETLIST
			$sdf_annotate("fifo_syn.sdf", fifo1);
			$fsdbDumpfile("fifo_syn.fsdb");
		`else
			$fsdbDumpfile("fifo.fsdb");
		`endif
		$fsdbDumpvars;
	end

	initial begin
		clk = 1;
		rst_n = 1;
		idle;
		#(period);
		#(delay)  rst_n = 0;
		#(period*4) rst_n = 1;


		#(period*2);

		#(period) popping;
		#(period) idle;
		#(period) pushing(8'd1);
		#(period) idle;
		#(period) pushing(8'd2);
		#(period) pushing(8'd3);
		#(period) pushing(8'd4);
		#(period) popping;
		#(period) pushing(8'd5);
		#(period) popping;
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) idle;
		#(period) invalid;
		#(period) invalid;
		#(period) idle;
		#(period) idle;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) invalid;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) pushing(8'd6);
		#(period) pushing(8'd7);
		#(period) pushing(8'd8);
		#(period) pushing(8'd9);
		#(period) pushing(8'd11);
		#(period) pushing(8'd12);
		#(period) pushing(8'd13);
		#(period) idle;
		#(period) invalid;
		#(period) idle;
		#(period) pushing(8'd14);
		#(period) pushing(8'd15);
		#(period) pushing(8'd16);
		#(period) pushing(8'd17);
		#(period) pushing(8'd18);
		#(period) pushing(8'd19);
		#(period) pushing(8'd20);
		#(period) pushing(8'd21);
		#(period) pushing(8'd22);
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) pushing(8'd23);
		#(period) pushing(8'd24);
		#(period) pushing(8'd25);
		#(period) pushing(8'd26);
		#(period) pushing(8'd27);
		#(period) pushing(8'd28);
		#(period) pushing(8'd29);
		#(period) pushing(8'd30);
		#(period) idle;
		#(period) pushing(8'd31);
		#(period) pushing(8'd32);
		#(period) pushing(8'd33);
		#(period) pushing(8'd34);
		#(period) pushing(8'd35);
		#(period) pushing(8'd36);
		#(period) pushing(8'd37);
		#(period) pushing(8'd38);
		#(period) pushing(8'd39);
		#(period) pushing(8'd40);
		#(period) pushing(8'd41);
		#(period) pushing(8'd42);
		#(period) pushing(8'd43);
		#(period) pushing(8'd44);
		#(period) pushing(8'd45);
		#(period) idle;
		#(period) idle;
		#(period) idle;
		#(period) idle;
		#(period) idle;

		#(period) popping;
		#(period) idle;
		#(period) idle;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;
		#(period) popping;
		#(period) idle;

		#(period) idle;
		#(period*4);
		$finish;
	end


	task idle;
		begin
			push = 0;
			pop = 0;
			datain = 8'b0;
		end
	endtask
	task pushing;
		input [7:0] data;
		begin
			push = 1;
			pop = 0;
			datain = data;
		end
	endtask
	task popping;
		begin
			push = 0;
			pop = 1;
		end
	endtask
	task invalid;
		begin
			push = 1;
			pop = 1;
		end
	endtask
endmodule