data/full_repos/permissive/159001439/src/real_clock.v
 line:13: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/159001439/src/real_clock.v:30: Operator ADD expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'sub_cnt\' generates 7 bits.\n                                                                        : ... In instance real_clock\nassign us_tick = (sub_cnt+1==US_CYCLES);\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/real_clock.v:33: Operator ASSIGNW expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'us_cnt\' generates 20 bits.\n                                                                        : ... In instance real_clock\nassign sub_us = us_cnt;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/real_clock.v:50: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'set_us\' generates 24 bits.\n                                                                        : ... In instance real_clock\n        us_cnt <= set_us;\n               ^~\n%Error: Exiting due to 3 warning(s)\n'
function integer clogb2 (input integer size);
begin
	size = size - 1;
	for (clogb2=1; size>1; clogb2=clogb2+1)
		size = size >> 1;
end
endfunction
function integer clogb2 (input integer size);

begin
	size = size - 1;
	for (clogb2=1; size>1; clogb2=clogb2+1)
		size = size >> 1;
end
endfunction