data/full_repos/permissive/115351337/uart/reciever_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/115351337/uart/reciever_tb.v:42: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("reciever_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/115351337/uart/reciever_tb.v:43: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,reciever_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #100 clear = 1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #1248 clear = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #100  clear = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #100  rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #1248 rx = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #2496 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/115351337/uart/reciever_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #6 clk = ~clk;\n        ^\n%Error: Exiting due to 2 error(s), 26 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reciever_tb;
    reg clk;
    wire [7:0] data;
    reg  [7:0] stored_data;
    wire flag;
    reg clear;
    reg rx;

    uart_rx reciever(clk, rx, clear, data, flag);

    initial begin
        $dumpfile("reciever_tb.vcd");
        $dumpvars(0,reciever_tb);
        rx = 1'b1;
        clk = 1'b0;
        clear = 1'b1;
        #100 clear = 1'b0;
        rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b1;
        #1248 clear = 1'b1;
        #100  clear = 1'b0;
        #100  rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b1;
        #2496 $finish;
    end

    always begin
        #6 clk = ~clk;
        stored_data <= data;
    end
endmodule
module reciever_tb;

    reg clk;
    wire [7:0] data;
    reg  [7:0] stored_data;
    wire flag;
    reg clear;
    reg rx;

    uart_rx reciever(clk, rx, clear, data, flag);

    initial begin
        $dumpfile("reciever_tb.vcd");
        $dumpvars(0,reciever_tb);
        rx = 1'b1;
        clk = 1'b0;
        clear = 1'b1;
        #100 clear = 1'b0;
        rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b1;
        #1248 clear = 1'b1;
        #100  clear = 1'b0;
        #100  rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b0;
        #1248 rx = 1'b1;
        #1248 rx = 1'b1;
        #2496 $finish;
    end

    always begin
        #6 clk = ~clk;
        stored_data <= data;
    end
endmodule