data/full_repos/permissive/127044786/blocks/Display/iPxs/Overlay/DynNumber.v
data/verilator_xmls/92b3657c-79c2-4150-9bfb-a0ef966e75d8.xml
module DynNumber (
        input wire         clk,
		input wire         reset,
		input wire         inc,
		input wire         dec,
        output wire  [3:0] number,
		output wire        carry_out
        );

assign number = counter;
assign carry_out = carry;

reg [3:0] counter = 0;
reg stop_inc = 1'b0;
reg stop_dec = 1'b0;
reg carry = 1'b0;

always @(posedge clk)
begin
    if (~inc) stop_inc <= 1'b0;
    if (~dec) stop_dec <= 1'b0;
    if (reset)
        counter <= 0;
    else if (inc && ~stop_inc)
        begin
        stop_inc <= 1'b1;
        if (counter == 9)
			begin
	   		counter <= 0;
			carry <= 1'b1;
			end
        else
            begin
       		counter <= counter+1;
       		carry <= 1'b0;
			end
        end
    else if (dec && ~stop_dec)
        begin
        stop_dec <= 1'b1;
        if (counter == 0)
			begin
	   		counter <= 9;
			carry <= 1'b1;
			end
        else
            begin
       		counter <= counter-1;
       		carry <= 1'b0;
			end
        end
end

endmodule
module DynNumber (
        input wire         clk,
		input wire         reset,
		input wire         inc,
		input wire         dec,
        output wire  [3:0] number,
		output wire        carry_out
        );


assign number = counter;
assign carry_out = carry;

reg [3:0] counter = 0;
reg stop_inc = 1'b0;
reg stop_dec = 1'b0;
reg carry = 1'b0;

always @(posedge clk)
begin
    if (~inc) stop_inc <= 1'b0;
    if (~dec) stop_dec <= 1'b0;
    if (reset)
        counter <= 0;
    else if (inc && ~stop_inc)
        begin
        stop_inc <= 1'b1;
        if (counter == 9)
			begin
	   		counter <= 0;
			carry <= 1'b1;
			end
        else
            begin
       		counter <= counter+1;
       		carry <= 1'b0;
			end
        end
    else if (dec && ~stop_dec)
        begin
        stop_dec <= 1'b1;
        if (counter == 0)
			begin
	   		counter <= 9;
			carry <= 1'b1;
			end
        else
            begin
       		counter <= counter-1;
       		carry <= 1'b0;
			end
        end
end

endmodule