data/full_repos/permissive/143278/ivltests/pr2166188.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2166188.v:25: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2166188.v:23: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh7b\' generates 32 or 7 bits.\n                                                                         : ... In instance t\n fls = 123;\n     ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t();

parameter eh = 11;
parameter mh = 52;

parameter ih2 = 6;
parameter fh = 7;

localparam ih = 1 << ih2;

reg [ih - 1:0] i_abs;

reg at;
reg [ih2 - 1:0] fls;

wire [ih - 1:0] i_norm;

assign i_norm = i_abs << (at ? ih - mh - 1 : fls);

initial
begin
	at = 1;
	fls = 123;
	i_abs = 'h123;
	#1;
	if(i_norm !== ('h123 << 11))
		$display("FAILED");
	else
		$display("PASSED");
end

endmodule
module t();


parameter eh = 11;
parameter mh = 52;

parameter ih2 = 6;
parameter fh = 7;

localparam ih = 1 << ih2;

reg [ih - 1:0] i_abs;

reg at;
reg [ih2 - 1:0] fls;

wire [ih - 1:0] i_norm;

assign i_norm = i_abs << (at ? ih - mh - 1 : fls);

initial
begin
	at = 1;
	fls = 123;
	i_abs = 'h123;
	#1;
	if(i_norm !== ('h123 << 11))
		$display("FAILED");
	else
		$display("PASSED");
end

endmodule