data/full_repos/permissive/181665138/verilog/capitolo_iii/D_flip_flop.v
1: b'%Error: data/full_repos/permissive/181665138/verilog/capitolo_iii/D_flip_flop.v:17: Cannot find include file: Clock.v\n`include "Clock.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181665138/verilog/capitolo_iii,data/full_repos/permissive/181665138/Clock.v\n             data/full_repos/permissive/181665138/verilog/capitolo_iii,data/full_repos/permissive/181665138/Clock.v.v\n             data/full_repos/permissive/181665138/verilog/capitolo_iii,data/full_repos/permissive/181665138/Clock.v.sv\n             Clock.v\n             Clock.v.v\n             Clock.v.sv\n             obj_dir/Clock.v\n             obj_dir/Clock.v.v\n             obj_dir/Clock.v.sv\n%Error: Exiting due to 1 error(s)\n'
module D_flip_flop(q, preset_, preclear_, d);
    input preset_, preclear_;
    input d;
    output q;
    
    wire qN;


    wire c;
    Clock clock(c);


    assign #3 q = ~((preset_ & (~d & c)) | qN | ~preclear_);
    assign #3 qN = ~(~preset_ | ((d & c) & preclear_) | q);
endmodule
module D_flip_flop(q, preset_, preclear_, d);

    input preset_, preclear_;
    input d;
    output q;
    
    wire qN;


    wire c;
    Clock clock(c);


    assign #3 q = ~((preset_ & (~d & c)) | qN | ~preclear_);
    assign #3 qN = ~(~preset_ | ((d & c) & preclear_) | q);
endmodule