data/full_repos/permissive/117736309/clk_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/117736309/clk_test.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #(PERIOD / 2) clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/117736309/clk_test.v:19: Cannot find file containing module: \'clk_pixel\'\n    clk_pixel uut (\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117736309,data/full_repos/permissive/117736309/clk_pixel\n             data/full_repos/permissive/117736309,data/full_repos/permissive/117736309/clk_pixel.v\n             data/full_repos/permissive/117736309,data/full_repos/permissive/117736309/clk_pixel.sv\n             clk_pixel\n             clk_pixel.v\n             clk_pixel.sv\n             obj_dir/clk_pixel\n             obj_dir/clk_pixel.v\n             obj_dir/clk_pixel.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clk_test;

    reg clk;
    parameter PERIOD = 10;

    initial
        clk = 0;

    always
        #(PERIOD / 2) clk = ~clk;


    wire clk_pixel;


    clk_pixel uut (
        .clk(clk),
        .clk_pixel(clk_pixel)
    );

endmodule
module clk_test;


    reg clk;
    parameter PERIOD = 10;

    initial
        clk = 0;

    always
        #(PERIOD / 2) clk = ~clk;


    wire clk_pixel;


    clk_pixel uut (
        .clk(clk),
        .clk_pixel(clk_pixel)
    );

endmodule