data/full_repos/permissive/131249673/MIPS_L_MultiCycle/MemExtender.v
1: b'%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/MemExtender.v:1: Cannot find include file: ctrl_encode_def.v\n`include "ctrl_encode_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131249673/MIPS_L_MultiCycle,data/full_repos/permissive/131249673/ctrl_encode_def.v\n             data/full_repos/permissive/131249673/MIPS_L_MultiCycle,data/full_repos/permissive/131249673/ctrl_encode_def.v.v\n             data/full_repos/permissive/131249673/MIPS_L_MultiCycle,data/full_repos/permissive/131249673/ctrl_encode_def.v.sv\n             ctrl_encode_def.v\n             ctrl_encode_def.v.v\n             ctrl_encode_def.v.sv\n             obj_dir/ctrl_encode_def.v\n             obj_dir/ctrl_encode_def.v.v\n             obj_dir/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/MemExtender.v:13: Define or directive not defined: \'`ME_LW\'\n      `ME_LW : dout = din;\n      ^~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/MemExtender.v:13: syntax error, unexpected \':\', expecting endcase\n      `ME_LW : dout = din;\n             ^\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/MemExtender.v:14: Define or directive not defined: \'`ME_LH\'\n     `ME_LH : if(ALUOut[1] == 1\'b1)\n     ^~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/MemExtender.v:19: Define or directive not defined: \'`ME_LHU\'\n     `ME_LHU: if(ALUOut[1] == 1\'b1)\n     ^~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/MemExtender.v:24: Define or directive not defined: \'`ME_LB\'\n     `ME_LB : if(ALUOut == 2\'b00)\n     ^~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/MemExtender.v:33: Define or directive not defined: \'`ME_LBU\'\n     `ME_LBU: if(ALUOut == 2\'b00)\n     ^~~~~~~\n%Error: Cannot continue\n'
module MemExtender(ALUOut, op, din, dout);
    
	input  [1:0] ALUOut;
	input  [2:0] op;
	input  [31:0] din;
	output [31:0] dout;
	
	reg [31:0] dout;
	
	always @(*) begin
	    case (op)
		    `ME_LW : dout = din;
			  `ME_LH : if(ALUOut[1] == 1'b1)
						dout = { { 16{ din[31] } } , din[31:16] };
					 else 
					    dout = { { 16{ din[15] } } , din[15:0] };
						
			  `ME_LHU: if(ALUOut[1] == 1'b1)
						dout = {16'b0, din[31:16]};
					 else 
						dout = {16'b0, din[15:0]};
						
			  `ME_LB : if(ALUOut == 2'b00)
						dout = { {24{din[7]} } , din[7:0]};
					 else if(ALUOut == 2'b01)
					    dout = { {24{din[15]} }, din[15:8]};
					 else if(ALUOut == 2'b10)
					    dout = { {24{din[23]} }, din[23:16]};
					 else if(ALUOut == 2'b11)
					    dout = { {24{din[31]} }, din[31:24]};
						
			  `ME_LBU: if(ALUOut == 2'b00)
						dout = { 24'b0, din[7:0]};
					 else if(ALUOut == 2'b01)
					    dout = { 24'b0, din[15:8]};
					 else if(ALUOut == 2'b10)
					    dout = { 24'b0, din[23:16]};
					 else if(ALUOut == 2'b11)
					    dout = { 24'b0, din[31:24]};
		endcase
	end
endmodule
module MemExtender(ALUOut, op, din, dout);

    
	input  [1:0] ALUOut;
	input  [2:0] op;
	input  [31:0] din;
	output [31:0] dout;
	
	reg [31:0] dout;
	
	always @(*) begin
	    case (op)
		    `ME_LW : dout = din;
			  `ME_LH : if(ALUOut[1] == 1'b1)
						dout = { { 16{ din[31] } } , din[31:16] };
					 else 
					    dout = { { 16{ din[15] } } , din[15:0] };
						
			  `ME_LHU: if(ALUOut[1] == 1'b1)
						dout = {16'b0, din[31:16]};
					 else 
						dout = {16'b0, din[15:0]};
						
			  `ME_LB : if(ALUOut == 2'b00)
						dout = { {24{din[7]} } , din[7:0]};
					 else if(ALUOut == 2'b01)
					    dout = { {24{din[15]} }, din[15:8]};
					 else if(ALUOut == 2'b10)
					    dout = { {24{din[23]} }, din[23:16]};
					 else if(ALUOut == 2'b11)
					    dout = { {24{din[31]} }, din[31:24]};
						
			  `ME_LBU: if(ALUOut == 2'b00)
						dout = { 24'b0, din[7:0]};
					 else if(ALUOut == 2'b01)
					    dout = { 24'b0, din[15:8]};
					 else if(ALUOut == 2'b10)
					    dout = { 24'b0, din[23:16]};
					 else if(ALUOut == 2'b11)
					    dout = { 24'b0, din[31:24]};
		endcase
	end
endmodule