data/full_repos/permissive/160024456/day01/part2_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160024456/day01/part2_test.v:9: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = !clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/160024456/day01/part2_test.v:13: Unsupported or unknown PLI call: $monitor\n    $monitor("time=%d, clk=%b, en=%b, done=%b, result=%d, sum=%d, dut.real_counter1=%d, dut.real_counter2=%d", $time, clk, dut.en, dut.done,\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/160024456/day01/part2_test.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10 en = 1;\n    ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module part2_test;

  reg clk = 0;
  reg en = 0;
  wire signed [63:0] result;

  part2 dut (.clk(clk), .en(en), .result(result));

  always #5 clk = !clk;

  initial begin
    $display("start");
    $monitor("time=%d, clk=%b, en=%b, done=%b, result=%d, sum=%d, dut.real_counter1=%d, dut.real_counter2=%d", $time, clk, dut.en, dut.done,
      result, dut.sum1, dut.real_counter1, dut.real_counter2);

    #10 en = 1;
  end

endmodule
module part2_test;


  reg clk = 0;
  reg en = 0;
  wire signed [63:0] result;

  part2 dut (.clk(clk), .en(en), .result(result));

  always #5 clk = !clk;

  initial begin
    $display("start");
    $monitor("time=%d, clk=%b, en=%b, done=%b, result=%d, sum=%d, dut.real_counter1=%d, dut.real_counter2=%d", $time, clk, dut.en, dut.done,
      result, dut.sum1, dut.real_counter1, dut.real_counter2);

    #10 en = 1;
  end

endmodule