data/full_repos/permissive/143278/ivltests/casesynth4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/casesynth4.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a!==0 || b!==1) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/casesynth4.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a!==1 || b!==0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/casesynth4.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a!==0 || b!==0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/casesynth4.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a!==1 || b!==1) begin\n      ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test
  (output reg       a,
   output reg	    b,
   input wire [1:0] sel,
   input wire	    d
);

   always @* begin
      b = d;
      case (sel)
	0:
	  begin
	     a = 0;
	     b = 1;
	  end
	1:
	  begin
	     a = 1;
	     b = 0;
	  end
	default:
	  begin
	     a = d;
	  end
      endcase
   end

endmodule
module test
  (output reg       a,
   output reg	    b,
   input wire [1:0] sel,
   input wire	    d
);


   always @* begin
      b = d;
      case (sel)
	0:
	  begin
	     a = 0;
	     b = 1;
	  end
	1:
	  begin
	     a = 1;
	     b = 0;
	  end
	default:
	  begin
	     a = d;
	  end
      endcase
   end

endmodule