data/full_repos/permissive/169225814/modules/crypto_lib/rtl/random_num_gen.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/169225814/modules/crypto_lib/rtl/random_num_gen.v:147: Signal definition not found, creating implicitly: \'en_trig\'\n assign en_trig = (cnt < 3\'b011) ? 1\'b1 : 1\'b0; \n        ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/rtl/random_num_gen.v:46: Cannot find file containing module: \'trng_wrap\'\ntrng_wrap trng_wrap_inst0 (\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169225814/modules/crypto_lib/rtl,data/full_repos/permissive/169225814/trng_wrap\n             data/full_repos/permissive/169225814/modules/crypto_lib/rtl,data/full_repos/permissive/169225814/trng_wrap.v\n             data/full_repos/permissive/169225814/modules/crypto_lib/rtl,data/full_repos/permissive/169225814/trng_wrap.sv\n             trng_wrap\n             trng_wrap.v\n             trng_wrap.sv\n             obj_dir/trng_wrap\n             obj_dir/trng_wrap.v\n             obj_dir/trng_wrap.sv\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/rtl/random_num_gen.v:53: Cannot find file containing module: \'trng_wrap\'\ntrng_wrap trng_wrap_inst1 (\n^~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/rtl/random_num_gen.v:60: Cannot find file containing module: \'trng_wrap\'\ntrng_wrap trng_wrap_inst2 (\n^~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/rtl/random_num_gen.v:67: Cannot find file containing module: \'trng_wrap\'\ntrng_wrap trng_wrap_inst3 (\n^~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/rtl/random_num_gen.v:74: Cannot find file containing module: \'trng_wrap\'\ntrng_wrap trng_wrap_inst4 (\n^~~~~~~~~\n%Error: data/full_repos/permissive/169225814/modules/crypto_lib/rtl/random_num_gen.v:83: Cannot find file containing module: \'vn_corrector\'\nvn_corrector #(\n^~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module random_num_gen #(
  parameter  NBITS = 2048 )(
  input  wire               clk,
  input  wire               rst_n,
  input  wire               enable_p,
  input  wire               bypass,
  input  wire [11:0]        maxbits,
  output wire               done_p,
  output wire [NBITS-1 :0]  y
);

wire [4:0]  y_loc;

reg        vn_din;
reg        wait4_done;
reg [2:0]  cnt;
reg [4:0]  en_loc;


trng_wrap trng_wrap_inst0 (
  .clk      (clk),
  .rst_n    (rst_n),
  .en       (en_loc[0]),
  .y        (y_loc[0])
);

trng_wrap trng_wrap_inst1 (
  .clk      (clk),
  .rst_n    (rst_n),
  .en       (en_loc[1]),
  .y        (y_loc[1])
);

trng_wrap trng_wrap_inst2 (
  .clk      (clk),
  .rst_n    (rst_n),
  .en       (en_loc[2]),
  .y        (y_loc[2])
);

trng_wrap trng_wrap_inst3 (
  .clk      (clk),
  .rst_n    (rst_n),
  .en       (en_loc[3]),
  .y        (y_loc[3])
);

trng_wrap trng_wrap_inst4 (
  .clk      (clk),
  .rst_n    (rst_n),
  .en       (en_loc[4]),
  .y        (y_loc[4])
);



vn_corrector #(
  .NBITS (NBITS))
  vn_corrector_inst (
  .clk      (clk),
  .rst_n    (rst_n),
  .bypass   (bypass),
  .enable_p (en_trig),
  .din      (vn_din),
  .maxbits  (maxbits),
  .done_p   (done_p),
  .y        (y)
);


 always @* begin
   if (cnt == 3'b011) begin
     vn_din = y_loc[0];
   end
   else if (cnt == 3'b100) begin
     vn_din = y_loc[1];
   end
   else if (cnt == 3'b000) begin
     vn_din = y_loc[2];
   end
   else if (cnt == 3'b001) begin
     vn_din = y_loc[3];
   end
   else if (cnt == 3'b010) begin
     vn_din = y_loc[4];
   end
   else begin
     vn_din = 1'b0;
   end
 end
      
 always @ (posedge clk or negedge rst_n) begin
   if (rst_n == 1'b0) begin
     cnt        <= 3'b111;
     wait4_done <= 1'b0;
   end
   else begin
     if (enable_p == 1'b1) begin
       cnt        <= 3'b0;
       wait4_done <= 1'b1;
     end
     else if (done_p == 1'b1) begin
       cnt        <= 3'b111;
       wait4_done <= 1'b0;
     end
     else if (wait4_done == 1'b1) begin
       if (cnt[2] == 1'b1) begin
         cnt <= 3'b0;
       end
       else begin
         cnt <= cnt + 1'b1;
       end
     end
     else begin
       cnt        <= 3'b111;
       wait4_done <= 1'b0;
     end
   end
 end

 assign en_trig = (cnt < 3'b011) ? 1'b1 : 1'b0; 

 always @ (posedge clk or negedge rst_n) begin
   if (rst_n == 1'b0) begin
     en_loc <= 5'b0;
   end
   else if (done_p == 1'b1) begin
     en_loc <= 5'b0;
   end
   else begin
     en_loc[0] <= en_trig;
     en_loc[1] <= en_loc[0];
     en_loc[2] <= en_loc[1];
     en_loc[3] <= en_loc[2];
     en_loc[4] <= en_loc[3];
   end
 end


endmodule
module random_num_gen #(
  parameter  NBITS = 2048 )(
  input  wire               clk,
  input  wire               rst_n,
  input  wire               enable_p,
  input  wire               bypass,
  input  wire [11:0]        maxbits,
  output wire               done_p,
  output wire [NBITS-1 :0]  y
);


wire [4:0]  y_loc;

reg        vn_din;
reg        wait4_done;
reg [2:0]  cnt;
reg [4:0]  en_loc;


trng_wrap trng_wrap_inst0 (
  .clk      (clk),
  .rst_n    (rst_n),
  .en       (en_loc[0]),
  .y        (y_loc[0])
);

trng_wrap trng_wrap_inst1 (
  .clk      (clk),
  .rst_n    (rst_n),
  .en       (en_loc[1]),
  .y        (y_loc[1])
);

trng_wrap trng_wrap_inst2 (
  .clk      (clk),
  .rst_n    (rst_n),
  .en       (en_loc[2]),
  .y        (y_loc[2])
);

trng_wrap trng_wrap_inst3 (
  .clk      (clk),
  .rst_n    (rst_n),
  .en       (en_loc[3]),
  .y        (y_loc[3])
);

trng_wrap trng_wrap_inst4 (
  .clk      (clk),
  .rst_n    (rst_n),
  .en       (en_loc[4]),
  .y        (y_loc[4])
);



vn_corrector #(
  .NBITS (NBITS))
  vn_corrector_inst (
  .clk      (clk),
  .rst_n    (rst_n),
  .bypass   (bypass),
  .enable_p (en_trig),
  .din      (vn_din),
  .maxbits  (maxbits),
  .done_p   (done_p),
  .y        (y)
);


 always @* begin
   if (cnt == 3'b011) begin
     vn_din = y_loc[0];
   end
   else if (cnt == 3'b100) begin
     vn_din = y_loc[1];
   end
   else if (cnt == 3'b000) begin
     vn_din = y_loc[2];
   end
   else if (cnt == 3'b001) begin
     vn_din = y_loc[3];
   end
   else if (cnt == 3'b010) begin
     vn_din = y_loc[4];
   end
   else begin
     vn_din = 1'b0;
   end
 end
      
 always @ (posedge clk or negedge rst_n) begin
   if (rst_n == 1'b0) begin
     cnt        <= 3'b111;
     wait4_done <= 1'b0;
   end
   else begin
     if (enable_p == 1'b1) begin
       cnt        <= 3'b0;
       wait4_done <= 1'b1;
     end
     else if (done_p == 1'b1) begin
       cnt        <= 3'b111;
       wait4_done <= 1'b0;
     end
     else if (wait4_done == 1'b1) begin
       if (cnt[2] == 1'b1) begin
         cnt <= 3'b0;
       end
       else begin
         cnt <= cnt + 1'b1;
       end
     end
     else begin
       cnt        <= 3'b111;
       wait4_done <= 1'b0;
     end
   end
 end

 assign en_trig = (cnt < 3'b011) ? 1'b1 : 1'b0; 

 always @ (posedge clk or negedge rst_n) begin
   if (rst_n == 1'b0) begin
     en_loc <= 5'b0;
   end
   else if (done_p == 1'b1) begin
     en_loc <= 5'b0;
   end
   else begin
     en_loc[0] <= en_trig;
     en_loc[1] <= en_loc[0];
     en_loc[2] <= en_loc[1];
     en_loc[3] <= en_loc[2];
     en_loc[4] <= en_loc[3];
   end
 end


endmodule