data/full_repos/permissive/194680577/ips_spi.v
1: b"%Error: data/full_repos/permissive/194680577/ips_spi.v:104: syntax error, unexpected '(', expecting IDENTIFIER\n HexSegDeg(sw[3:0], hled0);\n           ^~\n%Error: Exiting due to 1 error(s)\n"
module SerialTx(clk, btn, sw, led, hled0, hled1, hled2, hled3, Txd, Rxd);
	input clk;
	input [2:0] btn;
	input [9:0] sw;
	input [9:0] led;
	input [7:0] hled0;
	input [7:0] hled1;
	input [7:0] hled2;
	input [7:0] hled3;
	output Txd;
	output Rxd;
	wire [7:0] bdat;
	wire reset, sclk;
	
	unchatter uc(btn[2], clk, reset);
	BaundrateGen bg(clk, sw[9:8], sclk);
	SerialOut so(sclk, reset, sw[7:0], Txd);
	
	assign bdat=(sw[9:8]==2'd0)? 8'h38:
		(sw[9:8]==2'd1)? 8'h19:
		(sw[9:8]==2'd2)? 8'h96: 8'h48;
	
	assign led=10'h0;
	HexSegDeg(sw[3:0], hled0);
	HexSegDeg(sw[7:4], hled1);
	HexSegDeg(bdat[3:0], hled2);
	HexSegDeg(bdat[7:4], hled3);
	
endmodule
module SerialTx(clk, btn, sw, led, hled0, hled1, hled2, hled3, Txd, Rxd);

	input clk;
	input [2:0] btn;
	input [9:0] sw;
	input [9:0] led;
	input [7:0] hled0;
	input [7:0] hled1;
	input [7:0] hled2;
	input [7:0] hled3;
	output Txd;
	output Rxd;
	wire [7:0] bdat;
	wire reset, sclk;
	
	unchatter uc(btn[2], clk, reset);
	BaundrateGen bg(clk, sw[9:8], sclk);
	SerialOut so(sclk, reset, sw[7:0], Txd);
	
	assign bdat=(sw[9:8]==2'd0)? 8'h38:
		(sw[9:8]==2'd1)? 8'h19:
		(sw[9:8]==2'd2)? 8'h96: 8'h48;
	
	assign led=10'h0;
	HexSegDeg(sw[3:0], hled0);
	HexSegDeg(sw[7:4], hled1);
	HexSegDeg(bdat[3:0], hled2);
	HexSegDeg(bdat[7:4], hled3);
	
endmodule