data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial.v
1: b'%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial.v:18: Operator SUB expects 33 bits on the LHS, but LHS\'s VARREF \'a_r\' generates 16 bits.\n                                                                                                    : ... In instance complexmulttrial\nassign temp_r = ((a_r - b_r)*(w_r) - (a_i - b_i)*(w_i));\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial.v:18: Operator SUB expects 33 bits on the RHS, but RHS\'s VARREF \'b_r\' generates 16 bits.\n                                                                                                    : ... In instance complexmulttrial\nassign temp_r = ((a_r - b_r)*(w_r) - (a_i - b_i)*(w_i));\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial.v:18: Operator SUB expects 33 bits on the LHS, but LHS\'s VARREF \'a_i\' generates 16 bits.\n                                                                                                    : ... In instance complexmulttrial\nassign temp_r = ((a_r - b_r)*(w_r) - (a_i - b_i)*(w_i));\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial.v:18: Operator SUB expects 33 bits on the RHS, but RHS\'s VARREF \'b_i\' generates 16 bits.\n                                                                                                    : ... In instance complexmulttrial\nassign temp_r = ((a_r - b_r)*(w_r) - (a_i - b_i)*(w_i));\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial.v:19: Operator SUB expects 33 bits on the LHS, but LHS\'s VARREF \'a_i\' generates 16 bits.\n                                                                                                    : ... In instance complexmulttrial\nassign temp_i = ((a_i - b_i)*(w_r) + (a_r - b_r)*(w_i));\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial.v:19: Operator SUB expects 33 bits on the RHS, but RHS\'s VARREF \'b_i\' generates 16 bits.\n                                                                                                    : ... In instance complexmulttrial\nassign temp_i = ((a_i - b_i)*(w_r) + (a_r - b_r)*(w_i));\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial.v:19: Operator SUB expects 33 bits on the LHS, but LHS\'s VARREF \'a_r\' generates 16 bits.\n                                                                                                    : ... In instance complexmulttrial\nassign temp_i = ((a_i - b_i)*(w_r) + (a_r - b_r)*(w_i));\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial.v:19: Operator SUB expects 33 bits on the RHS, but RHS\'s VARREF \'b_r\' generates 16 bits.\n                                                                                                    : ... In instance complexmulttrial\nassign temp_i = ((a_i - b_i)*(w_r) + (a_r - b_r)*(w_i));\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial.v:20: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 15 bits.\n                                                                                                    : ... In instance complexmulttrial\nassign y_r[15:0] = temp_r[32:18];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/158984095/Homework4/Question2_FFT/complex_mult_trial.v:21: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 15 bits.\n                                                                                                    : ... In instance complexmulttrial\nassign y_i[15:0] = temp_i[32:18];\n                 ^\n%Error: Exiting due to 10 warning(s)\n'
module complexmulttrial(
input [15:0] a_r,
input [15:0] a_i,
input [15:0] b_r,
input [15:0] b_i,
input [15:0] w_r,
input [15:0] w_i,
output [15:0] x_r,
output [15:0] x_i,
output [15:0] y_r,
output [15:0] y_i);

wire [32:0] temp_r;
wire [32:0] temp_i;

assign x_r = a_r + b_r;
assign x_i = a_i + b_i;
assign temp_r = ((a_r - b_r)*(w_r) - (a_i - b_i)*(w_i));
assign temp_i = ((a_i - b_i)*(w_r) + (a_r - b_r)*(w_i));
assign y_r[15:0] = temp_r[32:18];
assign y_i[15:0] = temp_i[32:18];



endmodule
module complexmulttrial(
input [15:0] a_r,
input [15:0] a_i,
input [15:0] b_r,
input [15:0] b_i,
input [15:0] w_r,
input [15:0] w_i,
output [15:0] x_r,
output [15:0] x_i,
output [15:0] y_r,
output [15:0] y_i);


wire [32:0] temp_r;
wire [32:0] temp_i;

assign x_r = a_r + b_r;
assign x_i = a_i + b_i;
assign temp_r = ((a_r - b_r)*(w_r) - (a_i - b_i)*(w_i));
assign temp_i = ((a_i - b_i)*(w_r) + (a_r - b_r)*(w_i));
assign y_r[15:0] = temp_r[32:18];
assign y_i[15:0] = temp_i[32:18];



endmodule