data/full_repos/permissive/208741034/mux/rtl/mux.v
data/verilator_xmls/ee884cb9-72f5-4bbf-9d4c-a7c57a84c311.xml
module mux(

input   in1,
input   in2,

input   sel,
output  reg out

);


always @(*)begin















   out = sel ? in2 : in1;
end
endmodule
module mux(

input   in1,
input   in2,

input   sel,
output  reg out

);



always @(*)begin















   out = sel ? in2 : in1;
end
endmodule