data/full_repos/permissive/150329835/src/Comparison.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/150329835/src/Comparison.v:16: Cannot find file containing module: 'MULTIPLEXER'\n MULTIPLEXER M2(OP,W[39:30],W[29:20],W[19:10],W[9:0],F);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150329835/src,data/full_repos/permissive/150329835/MULTIPLEXER\n             data/full_repos/permissive/150329835/src,data/full_repos/permissive/150329835/MULTIPLEXER.v\n             data/full_repos/permissive/150329835/src,data/full_repos/permissive/150329835/MULTIPLEXER.sv\n             MULTIPLEXER\n             MULTIPLEXER.v\n             MULTIPLEXER.sv\n             obj_dir/MULTIPLEXER\n             obj_dir/MULTIPLEXER.v\n             obj_dir/MULTIPLEXER.sv\n%Error: Exiting due to 1 error(s)\n"
module MAX(A,B,F);
	input [3:0] A,B;
	wire [6:0] i;
	output [9:0] F;


	assign i[0] = A[3] & ~B[3];

	assign i[1] = ~(A[3]^B[3]);

	assign i[2] = (i[1]&A[2]& ~B[2])|i[0];

	assign i[3] = i[1] & ~(A[2]^B[2]);

	assign i[4] = (i[3]&A[1]& ~B[1])|i[2];

	assign i[5] = i[3] & ~(A[1]^B[1]);

	assign i[6] = (i[5]&A[0]& ~B[0])|i[4];
	
	assign F[0] = (i[6]&A[0])|(~i[6]&B[0]);
	assign F[1] = (i[6]&A[1])|(~i[6]&B[1]);
	assign F[2] = (i[6]&A[2])|(~i[6]&B[2]);
	assign F[3] = A[3]|B[3];
	assign F[9:4] = 6'b000000;
endmodule
module MAX(A,B,F);

	input [3:0] A,B;
	wire [6:0] i;
	output [9:0] F;


	assign i[0] = A[3] & ~B[3];

	assign i[1] = ~(A[3]^B[3]);

	assign i[2] = (i[1]&A[2]& ~B[2])|i[0];

	assign i[3] = i[1] & ~(A[2]^B[2]);

	assign i[4] = (i[3]&A[1]& ~B[1])|i[2];

	assign i[5] = i[3] & ~(A[1]^B[1]);

	assign i[6] = (i[5]&A[0]& ~B[0])|i[4];
	
	assign F[0] = (i[6]&A[0])|(~i[6]&B[0]);
	assign F[1] = (i[6]&A[1])|(~i[6]&B[1]);
	assign F[2] = (i[6]&A[2])|(~i[6]&B[2]);
	assign F[3] = A[3]|B[3];
	assign F[9:4] = 6'b000000;
endmodule