data/full_repos/permissive/174369527/mul_pipelined/mul_tb.v
 line:1: before: "timescale"
1: b'%Error: data/full_repos/permissive/174369527/mul_pipelined/mul_tb.v:1: syntax error, unexpected IDENTIFIER\ntimescale 1ns/1ps\n^~~~~~~~~\n%Error: Exiting due to 1 error(s)\n'
module mult_piped_8x8_2sC_tb;

  reg clock, reset;
  reg [7:0] a_in, b_in;
  wire [15:0] y_out;






  mult_piped_8x8_2sC DUT (a_in, b_in, clock, reset, y_out);

endmodule
module mult_piped_8x8_2sC_tb;


  reg clock, reset;
  reg [7:0] a_in, b_in;
  wire [15:0] y_out;






  mult_piped_8x8_2sC DUT (a_in, b_in, clock, reset, y_out);

endmodule