data/full_repos/permissive/143278/ivltests/sdw_stmt002.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/143278/ivltests/sdw_stmt002.v:23: Little bit endian vector: MSB < LSB of bit range: 0:7\nreg [0:7] var1, var2;  \n    ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/143278/ivltests/sdw_stmt002.v:26: Little bit endian vector: MSB < LSB of bit range: 2:9\nreg [2:9] var5;   \n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/sdw_stmt002.v:123: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                            : ... In instance main\n     var1[0:3] = var3[3:2];  \n               ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/sdw_stmt002.v:136: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'var5\' generates 8 bits.\n                                                                            : ... In instance main\n     var3 = var5;   \n          ^\n%Error: Exiting due to 4 warning(s)\n'
module main;

reg [0:7] var1, var2;
reg [3:0] var3;
reg var4;
reg [2:9] var5;
reg error;

initial
  begin

     error = 0;
     if(var1 !== 8'hxx)
       begin
         $display("FAILED - sdw_stmt002 - var1 not 8'hxx");
          error = 1;
       end
     if(var2 !== 8'hxx)
       begin
         $display("FAILED -  sdw_stmt002 -var2 not 8'hxx");
          error = 1;
       end
     if(var3 !== 4'bx_xxx)
       begin
         $display("FAILED -  sdw_stmt002 -var3 not 4'hx");
          error = 1;
       end
     if(var4 !== 1'bx)
       begin
         $display("FAILED -  sdw_stmt002 -var4 not 1'bx");
          error = 1;
       end
     if(var5 !== 8'hxx)
       begin
         $display("FAILED -  sdw_stmt002 -var5 not 8'hxx");
          error = 1;
       end

     var1 = 8'b1001_0010;
     var2 = 255;
     var3 = 4'hf;
     var4 = 0;
     var5 = 8'h99;

     if(var1 != 8'h92)
       begin
         $display("FAILED - sdw_stmt002 - var1 not 8'h96");
          error = 1;
       end
     if(var2 != 8'hff)
       begin
         $display("FAILED -  sdw_stmt002 -var2 not 8'hff");
          error = 1;
       end
     if(var3 != 4'b1111)
       begin
         $display("FAILED -  sdw_stmt002 -var3 not 4'hf");
          error = 1;
       end
     if(var4 != 1'b0)
       begin
         $display("FAILED -  sdw_stmt002 -var4 not 1'b0");
          error = 1;
       end
     if(var5 != 8'h99)
       begin
         $display("FAILED -  sdw_stmt002 -var5 not 8'h99");
          error = 1;
       end


     var1 [3:6] = var3;

     if(var1 != 8'h9e)
       begin
         $display("FAILED -  sdw_stmt002 - subfield assign failed");
          error = 1;
       end

     var3 = 4'o11;
     var4 = 1'b1;
     var5 = 8'h66;

     if(var3 != 4'b1001)
       begin
         $display("FAILED -  sdw_stmt002 -var3 octal assign");
          error = 1;
       end
     if(var4 != 1'b1)
       begin
         $display("FAILED -  sdw_stmt002 -var4 not 1'b1");
          error = 1;
       end
     if(var5 != 8'h66)
       begin
         $display("FAILED -  sdw_stmt002 -var5 not 8'h66");
          error = 1;
       end



     var3  = var1[4:7];
     var1[0:3] = var3[3:2];

     if(var1 != 8'h3e)
       begin
         $display("FAILED - sdw_stmt002 - subfield assign(1) w/ 0 extension");
          error = 1;
       end
     if(var3 != 4'b1110)
       begin
         $display("FAILED -  sdw_stmt002 -subfield assign(2)");
          error = 1;
       end

     var3 = var5;
     var5[5] = var4;

     if(var3 != 4'h6)
       begin
         $display("FAILED -  sdw_stmt002 - 4bit from 8 bit assign");
          error = 1;
       end
     if(var5 != 8'h76)
       begin
         $display("FAILED -  sdw_stmt002 - single sub-bit assign ");
          error = 1;
       end

     if(error == 0)
       $display("PASSED");
  end

endmodule
module main;


reg [0:7] var1, var2;
reg [3:0] var3;
reg var4;
reg [2:9] var5;
reg error;

initial
  begin

     error = 0;
     if(var1 !== 8'hxx)
       begin
         $display("FAILED - sdw_stmt002 - var1 not 8'hxx");
          error = 1;
       end
     if(var2 !== 8'hxx)
       begin
         $display("FAILED -  sdw_stmt002 -var2 not 8'hxx");
          error = 1;
       end
     if(var3 !== 4'bx_xxx)
       begin
         $display("FAILED -  sdw_stmt002 -var3 not 4'hx");
          error = 1;
       end
     if(var4 !== 1'bx)
       begin
         $display("FAILED -  sdw_stmt002 -var4 not 1'bx");
          error = 1;
       end
     if(var5 !== 8'hxx)
       begin
         $display("FAILED -  sdw_stmt002 -var5 not 8'hxx");
          error = 1;
       end

     var1 = 8'b1001_0010;
     var2 = 255;
     var3 = 4'hf;
     var4 = 0;
     var5 = 8'h99;

     if(var1 != 8'h92)
       begin
         $display("FAILED - sdw_stmt002 - var1 not 8'h96");
          error = 1;
       end
     if(var2 != 8'hff)
       begin
         $display("FAILED -  sdw_stmt002 -var2 not 8'hff");
          error = 1;
       end
     if(var3 != 4'b1111)
       begin
         $display("FAILED -  sdw_stmt002 -var3 not 4'hf");
          error = 1;
       end
     if(var4 != 1'b0)
       begin
         $display("FAILED -  sdw_stmt002 -var4 not 1'b0");
          error = 1;
       end
     if(var5 != 8'h99)
       begin
         $display("FAILED -  sdw_stmt002 -var5 not 8'h99");
          error = 1;
       end


     var1 [3:6] = var3;

     if(var1 != 8'h9e)
       begin
         $display("FAILED -  sdw_stmt002 - subfield assign failed");
          error = 1;
       end

     var3 = 4'o11;
     var4 = 1'b1;
     var5 = 8'h66;

     if(var3 != 4'b1001)
       begin
         $display("FAILED -  sdw_stmt002 -var3 octal assign");
          error = 1;
       end
     if(var4 != 1'b1)
       begin
         $display("FAILED -  sdw_stmt002 -var4 not 1'b1");
          error = 1;
       end
     if(var5 != 8'h66)
       begin
         $display("FAILED -  sdw_stmt002 -var5 not 8'h66");
          error = 1;
       end



     var3  = var1[4:7];
     var1[0:3] = var3[3:2];

     if(var1 != 8'h3e)
       begin
         $display("FAILED - sdw_stmt002 - subfield assign(1) w/ 0 extension");
          error = 1;
       end
     if(var3 != 4'b1110)
       begin
         $display("FAILED -  sdw_stmt002 -subfield assign(2)");
          error = 1;
       end

     var3 = var5;
     var5[5] = var4;

     if(var3 != 4'h6)
       begin
         $display("FAILED -  sdw_stmt002 - 4bit from 8 bit assign");
          error = 1;
       end
     if(var5 != 8'h76)
       begin
         $display("FAILED -  sdw_stmt002 - single sub-bit assign ");
          error = 1;
       end

     if(error == 0)
       $display("PASSED");
  end

endmodule