data/full_repos/permissive/13111265/verilog/src/receivers/test/ClkRecoverSetCounter_tb.v
 line:44: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/13111265/verilog/src/receivers/test/ClkRecoverSetCounter_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/13111265/verilog/src/receivers/test/ClkRecoverSetCounter_tb.v:43: syntax error, unexpected \'@\'\n    @(posedge clk) \n    ^\n%Error: data/full_repos/permissive/13111265/verilog/src/receivers/test/ClkRecoverSetCounter_tb.v:47: Unsupported: wait statements\n        wait(~full);\n        ^~~~\n%Error: data/full_repos/permissive/13111265/verilog/src/receivers/test/ClkRecoverSetCounter_tb.v:48: syntax error, unexpected \'@\'\n        @(posedge clk) dataIn <= $random(); writeStrobe = 1\'b1;\n        ^\n%Error: data/full_repos/permissive/13111265/verilog/src/receivers/test/ClkRecoverSetCounter_tb.v:49: syntax error, unexpected \'@\'\n        @(posedge clk) writeStrobe = 1\'b0;\n        ^\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ClkRecoverSetCounter_tb ();

parameter TARGET_PERIOD = 10;

reg clk;
reg rst;
reg en;
reg [7:0] dataIn;
reg writeStrobe;

wire dataPresent;
wire halfFull;
wire full;
wire tx;
wire clkStrobe;
wire rxClocked;

integer i;

integer enCounter;

always #1 clk = ~clk;

always @(posedge clk) begin
    if (enCounter == TARGET_PERIOD-1) begin
        enCounter <= 'd0;
        en <= 1'b1;
    end
    else begin
        enCounter <= enCounter + 1;
        en <= 1'b0;
    end
end


initial begin
    clk = 1'b0;
    rst = 1'b1;
    en = 1'b0;
    enCounter = 'd0;
    dataIn = 'd0;
    writeStrobe = 1'b0;
    @(posedge clk) 
    @(posedge clk) 
    rst = 1'b0;
    for (i=0; i<50000; i=i+1) begin
        wait(~full);
        @(posedge clk) dataIn <= $random(); writeStrobe = 1'b1;
        @(posedge clk) writeStrobe = 1'b0;
        @(posedge clk);
    end
    $stop(2);
end

Tx8b10b #(
    .FILL_WORD_RD0(10'b0011111010),
    .FILL_WORD_RD1(10'b1100000101),
    .FILL_WORD_FLIP(1'b1),
    .LOG2_DEPTH(4)
)
txTest (
    .clk(clk),
    .rst(rst),
    .en(en),
    .dataIn(dataIn),
    .writeStrobe(writeStrobe),
    .dataPresent(dataPresent),
    .halfFull(halfFull),
    .full(full),
    .tx(tx)
);

ClkRecoverSetCounter #(
    .TARGET_PERIOD(TARGET_PERIOD)
)
uut (

    .clk(clk),
    .rst(rst),
    .rx(tx),

    .clkStrobe(clkStrobe),
    .rxClocked(rxClocked)
);

endmodule
module ClkRecoverSetCounter_tb ();


parameter TARGET_PERIOD = 10;

reg clk;
reg rst;
reg en;
reg [7:0] dataIn;
reg writeStrobe;

wire dataPresent;
wire halfFull;
wire full;
wire tx;
wire clkStrobe;
wire rxClocked;

integer i;

integer enCounter;

always #1 clk = ~clk;

always @(posedge clk) begin
    if (enCounter == TARGET_PERIOD-1) begin
        enCounter <= 'd0;
        en <= 1'b1;
    end
    else begin
        enCounter <= enCounter + 1;
        en <= 1'b0;
    end
end


initial begin
    clk = 1'b0;
    rst = 1'b1;
    en = 1'b0;
    enCounter = 'd0;
    dataIn = 'd0;
    writeStrobe = 1'b0;
    @(posedge clk) 
    @(posedge clk) 
    rst = 1'b0;
    for (i=0; i<50000; i=i+1) begin
        wait(~full);
        @(posedge clk) dataIn <= $random(); writeStrobe = 1'b1;
        @(posedge clk) writeStrobe = 1'b0;
        @(posedge clk);
    end
    $stop(2);
end

Tx8b10b #(
    .FILL_WORD_RD0(10'b0011111010),
    .FILL_WORD_RD1(10'b1100000101),
    .FILL_WORD_FLIP(1'b1),
    .LOG2_DEPTH(4)
)
txTest (
    .clk(clk),
    .rst(rst),
    .en(en),
    .dataIn(dataIn),
    .writeStrobe(writeStrobe),
    .dataPresent(dataPresent),
    .halfFull(halfFull),
    .full(full),
    .tx(tx)
);

ClkRecoverSetCounter #(
    .TARGET_PERIOD(TARGET_PERIOD)
)
uut (

    .clk(clk),
    .rst(rst),
    .rx(tx),

    .clkStrobe(clkStrobe),
    .rxClocked(rxClocked)
);

endmodule