data/full_repos/permissive/154352170/PC.v
data/verilator_xmls/c6cdb05c-4508-4c7a-95f9-6227ee8d10d8.xml
module PC(
    input clk,
    input reset,
	 input PC_En,
	 input [31:0] PC_Next,
    output reg [31:0] PC_Out
    );

    initial begin
	    PC_Out <= 32'h00003000;
    end
	 
	 always @ (posedge clk) begin
	 
	    if(reset == 1)
		    PC_Out <= 32'h00003000;
		 
		 else if(PC_En == 1)
		    PC_Out <= PC_Next;
    
	 end			 
		    
endmodule
module PC(
    input clk,
    input reset,
	 input PC_En,
	 input [31:0] PC_Next,
    output reg [31:0] PC_Out
    );


    initial begin
	    PC_Out <= 32'h00003000;
    end
	 
	 always @ (posedge clk) begin
	 
	    if(reset == 1)
		    PC_Out <= 32'h00003000;
		 
		 else if(PC_En == 1)
		    PC_Out <= PC_Next;
    
	 end			 
		    
endmodule