data/full_repos/permissive/121864698/Latch.v
data/verilator_xmls/1607a528-83a4-477a-9ce8-54abb318cc83.xml
module lat(in,out,clk);
input [7:0] in;
input clk;
output reg[7:0] out;
reg [7:0]memdataout;
always @ (posedge clk)
out=in;
endmodule
module lat(in,out,clk);

input [7:0] in;
input clk;
output reg[7:0] out;
reg [7:0]memdataout;
always @ (posedge clk)
out=in;
endmodule