data/full_repos/permissive/174323821/hdl/clocking/jtframe_cendiv.v
data/verilator_xmls/a9d32710-336b-4326-a6ce-f717c32a9a59.xml
module jtframe_cendiv(
    input      clk,
    input      cen_in,
    output reg cen_div,
    output     cen_da
);

reg d = 0;

assign cen_da = cen_in & d;

always @(posedge clk) begin
    if( cen_in ) d<=~d;
    cen_div <= cen_da;
end


endmodule
module jtframe_cendiv(
    input      clk,
    input      cen_in,
    output reg cen_div,
    output     cen_da
);


reg d = 0;

assign cen_da = cen_in & d;

always @(posedge clk) begin
    if( cen_in ) d<=~d;
    cen_div <= cen_da;
end


endmodule