data/full_repos/permissive/125927162/MUX/MUX.v
data/verilator_xmls/636ea93d-3e5b-4274-bf75-373c9df3da19.xml
module mux (a, b, q, switch);
   parameter BUS_WIDTH = 4;
   input [BUS_WIDTH - 1:0] a;
   input [BUS_WIDTH - 1:0] b;
   output [BUS_WIDTH - 1:0] q;
   input 		   switch;

   assign q = switch ? a : b;
   
endmodule
module mux (a, b, q, switch);

   parameter BUS_WIDTH = 4;
   input [BUS_WIDTH - 1:0] a;
   input [BUS_WIDTH - 1:0] b;
   output [BUS_WIDTH - 1:0] q;
   input 		   switch;

   assign q = switch ? a : b;
   
endmodule