data/full_repos/permissive/115487336/mycode/Whac-A-Mole/state.v
data/verilator_xmls/e1766e4d-4ea6-4b3c-b3c4-008801510262.xml
module state(
	input clk,
	input rst_n,
	input buttonpress,
	input delayover,
	input timeover,
	input scorezero,
	output [4:0] state
);

reg [4:0] curr_state;
reg [4:0] next_state;







assign state = curr_state;

always@(posedge clk or posedge rst_n)
begin
	if(rst_n)
		curr_state <= 5'b0;
	else
		curr_state <= next_state;
end



always@(*)
begin
	if(curr_state == 5'd0)
		next_state = 5'd1;
	else if(curr_state == 5'd1)
	begin
		if(buttonpress)
			next_state=5'd2;
		else
			next_state=5'd1;
	end
	else if(curr_state == 5'd2)
	begin
		if(delayover)
			next_state=5'd3;
		else
			next_state=5'd2;
	end
	else if(curr_state == 5'd3)
	begin
		if(timeover||scorezero)
			next_state=5'd4;
		else
			next_state=5'd3;
	end
	else
		next_state=5'd4;
end
endmodule
module state(
	input clk,
	input rst_n,
	input buttonpress,
	input delayover,
	input timeover,
	input scorezero,
	output [4:0] state
);


reg [4:0] curr_state;
reg [4:0] next_state;







assign state = curr_state;

always@(posedge clk or posedge rst_n)
begin
	if(rst_n)
		curr_state <= 5'b0;
	else
		curr_state <= next_state;
end



always@(*)
begin
	if(curr_state == 5'd0)
		next_state = 5'd1;
	else if(curr_state == 5'd1)
	begin
		if(buttonpress)
			next_state=5'd2;
		else
			next_state=5'd1;
	end
	else if(curr_state == 5'd2)
	begin
		if(delayover)
			next_state=5'd3;
		else
			next_state=5'd2;
	end
	else if(curr_state == 5'd3)
	begin
		if(timeover||scorezero)
			next_state=5'd4;
		else
			next_state=5'd3;
	end
	else
		next_state=5'd4;
end
endmodule