data/full_repos/permissive/133161058/cla.rca/hdl/adder.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:57: Define or directive not defined: '`REG_SIZE'\n        output [`REG_SIZE:0] S;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:57: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n        output [`REG_SIZE:0] S;\n                         ^\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:59: Define or directive not defined: '`REG_SIZE'\n        input [`REG_SIZE:0] A,B;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:59: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n        input [`REG_SIZE:0] A,B;\n                        ^\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:62: Define or directive not defined: '`REG_SIZE'\n        wire [`REG_SIZE:0] Atemp,Btemp,Btemp1,Stemp;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:62: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n        wire [`REG_SIZE:0] Atemp,Btemp,Btemp1,Stemp;\n                       ^\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:63: Define or directive not defined: '`REG_SIZE'\n        reg [`REG_SIZE:0] CIN;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:63: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n        reg [`REG_SIZE:0] CIN;\n                      ^\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:76: Define or directive not defined: '`REG_SIZE'\n                for(i=0;i<`REG_SIZE+1;i=i+1)\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:81: Define or directive not defined: '`CLA_SIZE'\n        CLA Add1 (Stemp[`CLA_SIZE:0],W_1,Atemp[`CLA_SIZE:0],Btemp1[`CLA_SIZE:0],Y_2);\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:81: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n        CLA Add1 (Stemp[`CLA_SIZE:0],W_1,Atemp[`CLA_SIZE:0],Btemp1[`CLA_SIZE:0],Y_2);\n                                 ^\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:81: Define or directive not defined: '`CLA_SIZE'\n        CLA Add1 (Stemp[`CLA_SIZE:0],W_1,Atemp[`CLA_SIZE:0],Btemp1[`CLA_SIZE:0],Y_2);\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:81: Define or directive not defined: '`CLA_SIZE'\n        CLA Add1 (Stemp[`CLA_SIZE:0],W_1,Atemp[`CLA_SIZE:0],Btemp1[`CLA_SIZE:0],Y_2);\n                                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:83: Define or directive not defined: '`CLA_SIZE'\n        CLA Add2 (Stemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_2,Atemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],Btemp1[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_1);\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:83: Define or directive not defined: '`CLA_SIZE'\n        CLA Add2 (Stemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_2,Atemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],Btemp1[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_1);\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:83: Define or directive not defined: '`CLA_SIZE'\n        CLA Add2 (Stemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_2,Atemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],Btemp1[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_1);\n                                                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:83: Define or directive not defined: '`CLA_SIZE'\n        CLA Add2 (Stemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_2,Atemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],Btemp1[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_1);\n                                                                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:83: Define or directive not defined: '`CLA_SIZE'\n        CLA Add2 (Stemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_2,Atemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],Btemp1[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_1);\n                                                                                                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:83: Define or directive not defined: '`CLA_SIZE'\n        CLA Add2 (Stemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_2,Atemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],Btemp1[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_1);\n                                                                                                                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:85: Define or directive not defined: '`CLA_SIZE'\n        CLA Add3 (Stemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_3,Atemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],Btemp1[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_2);\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:85: Define or directive not defined: '`CLA_SIZE'\n        CLA Add3 (Stemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_3,Atemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],Btemp1[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_2);\n                                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:85: Define or directive not defined: '`CLA_SIZE'\n        CLA Add3 (Stemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_3,Atemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],Btemp1[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_2);\n                                                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:85: Define or directive not defined: '`CLA_SIZE'\n        CLA Add3 (Stemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_3,Atemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],Btemp1[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_2);\n                                                                                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:85: Define or directive not defined: '`CLA_SIZE'\n        CLA Add3 (Stemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_3,Atemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],Btemp1[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_2);\n                                                                                                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:85: Define or directive not defined: '`CLA_SIZE'\n        CLA Add3 (Stemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_3,Atemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],Btemp1[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_2);\n                                                                                                                                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:87: Define or directive not defined: '`REG_SIZE'\n        CLA Add4 (Stemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Y_3,Atemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Btemp1[`REG_SIZE:(`CLA_SIZE + 1)*3],W_3);\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:87: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n        CLA Add4 (Stemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Y_3,Atemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Btemp1[`REG_SIZE:(`CLA_SIZE + 1)*3],W_3);\n                                 ^\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:87: Define or directive not defined: '`CLA_SIZE'\n        CLA Add4 (Stemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Y_3,Atemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Btemp1[`REG_SIZE:(`CLA_SIZE + 1)*3],W_3);\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:87: Define or directive not defined: '`REG_SIZE'\n        CLA Add4 (Stemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Y_3,Atemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Btemp1[`REG_SIZE:(`CLA_SIZE + 1)*3],W_3);\n                                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:87: Define or directive not defined: '`CLA_SIZE'\n        CLA Add4 (Stemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Y_3,Atemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Btemp1[`REG_SIZE:(`CLA_SIZE + 1)*3],W_3);\n                                                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:87: Define or directive not defined: '`REG_SIZE'\n        CLA Add4 (Stemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Y_3,Atemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Btemp1[`REG_SIZE:(`CLA_SIZE + 1)*3],W_3);\n                                                                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/cla.rca/hdl/adder.v:87: Define or directive not defined: '`CLA_SIZE'\n        CLA Add4 (Stemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Y_3,Atemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Btemp1[`REG_SIZE:(`CLA_SIZE + 1)*3],W_3);\n                                                                                                              ^~~~~~~~~\n%Error: Exiting due to 32 error(s)\n"
module Adder (S, sign, Asign, A, B, AS);
        output [`REG_SIZE:0] S;
        output sign;
        input [`REG_SIZE:0] A,B;
        input Asign,AS;

        wire [`REG_SIZE:0] Atemp,Btemp,Btemp1,Stemp;
        reg [`REG_SIZE:0] CIN;
        wire Y_1,Y_2,Y_3,Y_4;

        assign Y_1 = (~AS) & Asign;

        BusMux2_1 MUX_0 (Atemp,A,B,Y_1);
        BusMux2_1 MUX_1 (Btemp,B,A,Y_1);

        assign Y_2 = Asign ^ AS;

        integer i;
always @ (Y_2)
        begin
                for(i=0;i<`REG_SIZE+1;i=i+1)
                CIN[i] <= Y_2;
        end
        assign Btemp1 = Btemp ^ CIN;

        CLA Add1 (Stemp[`CLA_SIZE:0],W_1,Atemp[`CLA_SIZE:0],Btemp1[`CLA_SIZE:0],Y_2);

        CLA Add2 (Stemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_2,Atemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],Btemp1[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_1);

        CLA Add3 (Stemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_3,Atemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],Btemp1[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_2);

        CLA Add4 (Stemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Y_3,Atemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Btemp1[`REG_SIZE:(`CLA_SIZE + 1)*3],W_3);

        assign Y_4 = (~Y_3) & (Asign ^ AS);

        complement Compl (S,Stemp,Y_4);
        assign sign = (~Y_3 & AS) | (~Y_3 & Asign) | (AS & Asign);

endmodule
module Adder (S, sign, Asign, A, B, AS);

        output [`REG_SIZE:0] S;
        output sign;
        input [`REG_SIZE:0] A,B;
        input Asign,AS;

        wire [`REG_SIZE:0] Atemp,Btemp,Btemp1,Stemp;
        reg [`REG_SIZE:0] CIN;
        wire Y_1,Y_2,Y_3,Y_4;

        assign Y_1 = (~AS) & Asign;

        BusMux2_1 MUX_0 (Atemp,A,B,Y_1);
        BusMux2_1 MUX_1 (Btemp,B,A,Y_1);

        assign Y_2 = Asign ^ AS;

        integer i;
always @ (Y_2)
        begin
                for(i=0;i<`REG_SIZE+1;i=i+1)
                CIN[i] <= Y_2;
        end
        assign Btemp1 = Btemp ^ CIN;

        CLA Add1 (Stemp[`CLA_SIZE:0],W_1,Atemp[`CLA_SIZE:0],Btemp1[`CLA_SIZE:0],Y_2);

        CLA Add2 (Stemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_2,Atemp[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],Btemp1[((`CLA_SIZE + 1)*2 - 1):(`CLA_SIZE + 1)],W_1);

        CLA Add3 (Stemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_3,Atemp[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],Btemp1[((`CLA_SIZE + 1)*3 - 1):((`CLA_SIZE + 1)*2)],W_2);

        CLA Add4 (Stemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Y_3,Atemp[`REG_SIZE:(`CLA_SIZE + 1)*3],Btemp1[`REG_SIZE:(`CLA_SIZE + 1)*3],W_3);

        assign Y_4 = (~Y_3) & (Asign ^ AS);

        complement Compl (S,Stemp,Y_4);
        assign sign = (~Y_3 & AS) | (~Y_3 & Asign) | (AS & Asign);

endmodule