data/full_repos/permissive/135852214/Verilog/mux12bit.v
data/verilator_xmls/fdf49101-5a7c-444b-a897-6b398a0481ee.xml
module mux12bit(
    input [11:0] a,
    input [11:0] b,
    input sel,
    output reg [11:0] x
    );

always @*
if (~sel)
	x <= a;
else
	x <= b;
endmodule
module mux12bit(
    input [11:0] a,
    input [11:0] b,
    input sel,
    output reg [11:0] x
    );


always @*
if (~sel)
	x <= a;
else
	x <= b;
endmodule