data/full_repos/permissive/143278/ivltests/escape4b.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/escape4b.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/escape4b.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

   reg [1:0] \bot.m [1:0];

   bot bot();

   initial begin
      #1;
      \bot.m [0] = 2'b11;
      #1;
      $display("\\bot.m [0] == %b", \bot.m [0]);
      $display("bot.m[0] == %b", bot.m[0] );

      if (\bot.m [0] !== 2'b11) begin
	 $display("FAILED -- \\bot.m [0] !== 2'b11");
	 $finish;
      end

      if (bot.m[0] !== 2'b00) begin
	 $display("FAILED -- bot.m[0] !== 2'b00");
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module top;


   reg [1:0] \bot.m [1:0];

   bot bot();

   initial begin
      #1;
      \bot.m [0] = 2'b11;
      #1;
      $display("\\bot.m [0] == %b", \bot.m [0]);
      $display("bot.m[0] == %b", bot.m[0] );

      if (\bot.m [0] !== 2'b11) begin
	 $display("FAILED -- \\bot.m [0] !== 2'b11");
	 $finish;
      end

      if (bot.m[0] !== 2'b00) begin
	 $display("FAILED -- bot.m[0] !== 2'b00");
	 $finish;
      end

      $display("PASSED");
   end
endmodule