data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:1: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Mips/Type/Word.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Mips/Type/Word.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Register,data/full_repos/permissive/131921633/Mips/Type/Word.v.sv\n             Mips/Type/Word.v\n             Mips/Type/Word.v.v\n             Mips/Type/Word.v.sv\n             obj_dir/Mips/Type/Word.v\n             obj_dir/Mips/Type/Word.v.v\n             obj_dir/Mips/Type/Word.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:2: Cannot find include file: Mips/Type/RegAddr.v\n`include "Mips/Type/RegAddr.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:3: Cannot find include file: Mips/Instruction/Format/RFormat.v\n`include "Mips/Instruction/Format/RFormat.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:5: Cannot find include file: Mips/Control/Signal/Register/Signal/WriteDataSource.v\n`include "Mips/Control/Signal/Register/Signal/WriteDataSource.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:8: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteDataSource_T\'\n ( `Mips_Control_Signal_Register_Signal_WriteDataSource_T(input) source\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:8: syntax error, unexpected \'(\', expecting \'[\'\n ( `Mips_Control_Signal_Register_Signal_WriteDataSource_T(input) source\n                                                          ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:9: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T(input) memOut\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:10: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T(input) pcAddr\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:11: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T(input) aluResult\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:12: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T(output) wrData\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:15: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (reg) wrData$;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:18: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteDataSource_Memory\'\n  `Mips_Control_Signal_Register_Signal_WriteDataSource_Memory : wrData$ = memOut;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:19: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteDataSource_Pc\'\n  `Mips_Control_Signal_Register_Signal_WriteDataSource_Pc     : wrData$ = pcAddr + 4;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Register/wrData.v:20: Define or directive not defined: \'`Mips_Control_Signal_Register_Signal_WriteDataSource_Alu\'\n  `Mips_Control_Signal_Register_Signal_WriteDataSource_Alu    : wrData$ = aluResult;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module Mips_Datapath_Register_wrData
	( `Mips_Control_Signal_Register_Signal_WriteDataSource_T(input) source
	, `Mips_Type_Word_T(input) memOut
	, `Mips_Type_Word_T(input) pcAddr
	, `Mips_Type_Word_T(input) aluResult
	, `Mips_Type_Word_T(output) wrData
	);

`Mips_Type_Word_T (reg) wrData$;
always @(*)
	case(source)
		`Mips_Control_Signal_Register_Signal_WriteDataSource_Memory : wrData$ = memOut;
		`Mips_Control_Signal_Register_Signal_WriteDataSource_Pc     : wrData$ = pcAddr + 4;
		`Mips_Control_Signal_Register_Signal_WriteDataSource_Alu    : wrData$ = aluResult;
		default                                                     : wrData$ = aluResult;
	endcase
assign wrData = wrData$;

endmodule
module Mips_Datapath_Register_wrData
	( `Mips_Control_Signal_Register_Signal_WriteDataSource_T(input) source
	, `Mips_Type_Word_T(input) memOut
	, `Mips_Type_Word_T(input) pcAddr
	, `Mips_Type_Word_T(input) aluResult
	, `Mips_Type_Word_T(output) wrData
	);


`Mips_Type_Word_T (reg) wrData$;
always @(*)
	case(source)
		`Mips_Control_Signal_Register_Signal_WriteDataSource_Memory : wrData$ = memOut;
		`Mips_Control_Signal_Register_Signal_WriteDataSource_Pc     : wrData$ = pcAddr + 4;
		`Mips_Control_Signal_Register_Signal_WriteDataSource_Alu    : wrData$ = aluResult;
		default                                                     : wrData$ = aluResult;
	endcase
assign wrData = wrData$;

endmodule