data/full_repos/permissive/143278/ivltests/pr1960633.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1960633.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #1 ;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [7:0] foo;

`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
   wire [3:0] below = foo[2:-1];
   wire [3:0] above = foo[8:5];
   wire [9:0] span = foo[8:-1];
`else
   wire [3:0] below = {foo[2:0], 1'bx};
   wire [3:0] above = {1'bx, foo[7:5]};
   wire [9:0] span = {1'bx, foo[7:0], 1'bx};
`endif

   initial begin
      foo = 'h55;
      #1 ;
      if (below !== 4'b101_x) begin
	 $display("FAILED");
	 $finish;
      end
      if (above !== 4'bx_010) begin
	 $display("FAILED");
	 $finish;
      end
      if (span !== 10'bx_01010101_x) begin
	 $display("FAILED");
	 $finish;
      end
      $display("PASSED");
   end

endmodule
module main;


   reg [7:0] foo;

`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
   wire [3:0] below = foo[2:-1];
   wire [3:0] above = foo[8:5];
   wire [9:0] span = foo[8:-1];
`else
   wire [3:0] below = {foo[2:0], 1'bx};
   wire [3:0] above = {1'bx, foo[7:5]};
   wire [9:0] span = {1'bx, foo[7:0], 1'bx};
`endif

   initial begin
      foo = 'h55;
      #1 ;
      if (below !== 4'b101_x) begin
	 $display("FAILED");
	 $finish;
      end
      if (above !== 4'bx_010) begin
	 $display("FAILED");
	 $finish;
      end
      if (span !== 10'bx_01010101_x) begin
	 $display("FAILED");
	 $finish;
      end
      $display("PASSED");
   end

endmodule