data/full_repos/permissive/137633637/jingzhe.srcs/sources_1/new/main.v
1: b"%Error: data/full_repos/permissive/137633637/jingzhe.srcs/sources_1/new/main.v:58: Cannot find file containing module: 'CounterModTen'\nCounterModTen u0(clk0,input_rst,input_start,q0);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137633637/jingzhe.srcs/sources_1/new,data/full_repos/permissive/137633637/CounterModTen\n             data/full_repos/permissive/137633637/jingzhe.srcs/sources_1/new,data/full_repos/permissive/137633637/CounterModTen.v\n             data/full_repos/permissive/137633637/jingzhe.srcs/sources_1/new,data/full_repos/permissive/137633637/CounterModTen.sv\n             CounterModTen\n             CounterModTen.v\n             CounterModTen.sv\n             obj_dir/CounterModTen\n             obj_dir/CounterModTen.v\n             obj_dir/CounterModTen.sv\n%Error: data/full_repos/permissive/137633637/jingzhe.srcs/sources_1/new/main.v:59: Cannot find file containing module: 'CounterModTen'\nCounterModTen u1(clk1,input_rst,input_start,q1);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137633637/jingzhe.srcs/sources_1/new/main.v:60: Cannot find file containing module: 'CounterModTen'\nCounterModTen u2(clk2,input_rst,input_start,q2);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137633637/jingzhe.srcs/sources_1/new/main.v:61: Cannot find file containing module: 'CounterModTen'\nCounterModTen u3(clk3,input_rst,input_start,q3);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137633637/jingzhe.srcs/sources_1/new/main.v:64: Cannot find file containing module: 'screen'\nscreen s0(clk,num,input_rst,led);\n^~~~~~\n%Error: data/full_repos/permissive/137633637/jingzhe.srcs/sources_1/new/main.v:65: Cannot find file containing module: 'screen'\nscreen s1(clk,countdown,0,led_countdown);\n^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module main(clk,clk0,clk1,clk2,clk3,rst,setpw,judge,pos,led,pos_countdown,led_countdown,staus);

input clk;
input clk0,clk1,clk2,clk3;
input rst;
input setpw;
input judge;

output reg [3:0] pos;
output [6:0] led;
output [6:0] led_countdown;
output reg pos_countdown;
output reg staus;

integer clock_led,clock_countdown;
wire [3:0] q0,q1,q2,q3;
reg [3:0] pw0,pw1,pw2,pw3;
reg [3:0] num;
reg timeout;
reg [3:0] countdown;
reg input_start,input_rst;

initial
begin

    countdown=4'b0101;
    pos=4'b0001;
    timeout=0;
    clock_led=0;
    clock_countdown=0;
    pos_countdown=1;
    staus=1;
end


CounterModTen u0(clk0,input_rst,input_start,q0);
CounterModTen u1(clk1,input_rst,input_start,q1);
CounterModTen u2(clk2,input_rst,input_start,q2);
CounterModTen u3(clk3,input_rst,input_start,q3);


screen s0(clk,num,input_rst,led);
screen s1(clk,countdown,0,led_countdown);

always @(posedge clk)
begin

    if(countdown==4'b0000)
    begin
    input_start<=0;
    input_rst<=1;
    end
    else
    begin
    	input_start<=setpw|judge;
    	input_rst<=rst|((~judge)&(~setpw));
    end


    if(clock_led==200000)
    begin
        timeout<=1;
        clock_led<=0;
    end
    else
    begin
        timeout<=0;
        clock_led<=clock_led+1;
    end


    if(judge&&countdown!=4'b0000&&~staus)
    begin
        if(clock_countdown!=1250000000)
        begin
            clock_countdown<=clock_countdown+1;
        end
        case(clock_countdown)
            1250000000:
                countdown<=4'b0000;
            1000000000:
                countdown<=4'b0001;
            750000000:
                countdown<=4'b0010;
            500000000:
                countdown<=4'b0011;
            250000000:
                countdown<=4'b0100;
            0:
                countdown<=4'b0101;
        endcase
    end
    else if(~judge)
    begin
        countdown<=4'b0101;
        clock_countdown<=0;
    end


    if(setpw && staus)
    begin
        pw0<=q0;
        pw1<=q1;
        pw2<=q2;
        pw3<=q3;
    end

end


always @(posedge timeout)
begin
    if (pos==4'b0001)
    begin
        pos<=4'b0010;
        num<=q1;
    end
    else if(pos==4'b0010)
    begin
        pos<=4'b0100;
        num<=q2;
    end
    else if(pos==4'b0100)
    begin
        pos<=4'b1000;
        num<=q3;
    end
    else if(pos==4'b1000)
    begin
        pos<=4'b0001;
        num<=q0;
    end
end


always @(*)
begin
    if(judge)
    begin
        if(pw0==q0&&pw1==q1&&pw2==q2&&pw3==q3&&countdown!=4'b0000)
            staus<=1;
        else
            staus<=0;
    end
end

endmodule
module main(clk,clk0,clk1,clk2,clk3,rst,setpw,judge,pos,led,pos_countdown,led_countdown,staus);


input clk;
input clk0,clk1,clk2,clk3;
input rst;
input setpw;
input judge;

output reg [3:0] pos;
output [6:0] led;
output [6:0] led_countdown;
output reg pos_countdown;
output reg staus;

integer clock_led,clock_countdown;
wire [3:0] q0,q1,q2,q3;
reg [3:0] pw0,pw1,pw2,pw3;
reg [3:0] num;
reg timeout;
reg [3:0] countdown;
reg input_start,input_rst;

initial
begin

    countdown=4'b0101;
    pos=4'b0001;
    timeout=0;
    clock_led=0;
    clock_countdown=0;
    pos_countdown=1;
    staus=1;
end


CounterModTen u0(clk0,input_rst,input_start,q0);
CounterModTen u1(clk1,input_rst,input_start,q1);
CounterModTen u2(clk2,input_rst,input_start,q2);
CounterModTen u3(clk3,input_rst,input_start,q3);


screen s0(clk,num,input_rst,led);
screen s1(clk,countdown,0,led_countdown);

always @(posedge clk)
begin

    if(countdown==4'b0000)
    begin
    input_start<=0;
    input_rst<=1;
    end
    else
    begin
    	input_start<=setpw|judge;
    	input_rst<=rst|((~judge)&(~setpw));
    end


    if(clock_led==200000)
    begin
        timeout<=1;
        clock_led<=0;
    end
    else
    begin
        timeout<=0;
        clock_led<=clock_led+1;
    end


    if(judge&&countdown!=4'b0000&&~staus)
    begin
        if(clock_countdown!=1250000000)
        begin
            clock_countdown<=clock_countdown+1;
        end
        case(clock_countdown)
            1250000000:
                countdown<=4'b0000;
            1000000000:
                countdown<=4'b0001;
            750000000:
                countdown<=4'b0010;
            500000000:
                countdown<=4'b0011;
            250000000:
                countdown<=4'b0100;
            0:
                countdown<=4'b0101;
        endcase
    end
    else if(~judge)
    begin
        countdown<=4'b0101;
        clock_countdown<=0;
    end


    if(setpw && staus)
    begin
        pw0<=q0;
        pw1<=q1;
        pw2<=q2;
        pw3<=q3;
    end

end


always @(posedge timeout)
begin
    if (pos==4'b0001)
    begin
        pos<=4'b0010;
        num<=q1;
    end
    else if(pos==4'b0010)
    begin
        pos<=4'b0100;
        num<=q2;
    end
    else if(pos==4'b0100)
    begin
        pos<=4'b1000;
        num<=q3;
    end
    else if(pos==4'b1000)
    begin
        pos<=4'b0001;
        num<=q0;
    end
end


always @(*)
begin
    if(judge)
    begin
        if(pw0==q0&&pw1==q1&&pw2==q2&&pw3==q3&&countdown!=4'b0000)
            staus<=1;
        else
            staus<=0;
    end
end

endmodule