data/full_repos/permissive/13953309/NW_fifo.v
 line:103: before: "typedef"
1: b"%Error: data/full_repos/permissive/13953309/NW_fifo.v:110: syntax error, unexpected IDENTIFIER, expecting '.' or ';'\ntypedef flit_t fifo_elements_t;\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:134: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:135: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t data_out, second_data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:275: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:276: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t data_out, second_data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:513: syntax error, unexpected IDENTIFIER, expecting ';'\n   input     fifo_elements_t data_in;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:514: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t data_out;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/13953309/NW_fifo.v:515: syntax error, unexpected IDENTIFIER, expecting ';'\n   output    fifo_elements_t second_data_out;\n                             ^~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module fifo_r (push, pop, data_in, data_out, second_data_out, clk, rst_n);


   parameter init_fifo_contents = 0;



   parameter size = 8;

   parameter output_reg = 1;

   parameter low_power = 0;




   parameter always_write = 1'b0;


   
   input     push, pop;
   input     fifo_elements_t data_in;
   output    fifo_elements_t data_out, second_data_out;
   input     clk, rst_n;

   fifov_flags_t local_flags;

   fifo_elements_t fifo_data_out, second_data;
   fifo_elements_t fifo_out_reg;

   fifo_elements_t to_reg;
   
   logic bypass, fifo_push, fifo_pop;

   generate
   if (!output_reg) begin

      fifo_buffer #(.init_fifo_contents(init_fifo_contents), 

		    .size(always_write+size), .output_reg(0), 
		    .low_power(low_power), .always_write(always_write))
         fifo_buf (push, pop, data_in, data_out, second_data, clk, rst_n);

      assign second_data_out = second_data;
      
   end else begin



      fifo_buffer #(.init_fifo_contents(init_fifo_contents),

		    .size(always_write+size), .output_reg(0), .low_power(low_power),
		    .always_write(always_write))
         fifo_buf (push, pop, data_in, fifo_data_out, second_data, clk, rst_n);






      fifo_flags #(.size(always_write+size), 
		   .init_fifo_contents(init_fifo_contents)) gen_localflags
	(push, pop, local_flags, clk, rst_n);   

      always@(posedge clk) begin
	 if (!rst_n) begin

            if (init_fifo_contents!=0) begin
               fifo_out_reg<=1;
            end
	 end else begin
	    fifo_out_reg<=to_reg;


	    
	 end
      end


      always_comb
	begin
           if (local_flags.empty || (local_flags.nearly_empty && pop)) begin
              if (push) begin
		 to_reg = data_in;
              end else begin


		 to_reg = '0;
              end
           end else if (pop) begin
	      to_reg = second_data;
           end else begin
              to_reg = fifo_data_out;
           end
	end
      
      assign data_out = fifo_out_reg;
      assign second_data_out = second_data;

   end
   endgenerate
   
endmodule
module fifo_r (push, pop, data_in, data_out, second_data_out, clk, rst_n);



   parameter init_fifo_contents = 0;



   parameter size = 8;

   parameter output_reg = 1;

   parameter low_power = 0;




   parameter always_write = 1'b0;


   
   input     push, pop;
   input     fifo_elements_t data_in;
   output    fifo_elements_t data_out, second_data_out;
   input     clk, rst_n;

   fifov_flags_t local_flags;

   fifo_elements_t fifo_data_out, second_data;
   fifo_elements_t fifo_out_reg;

   fifo_elements_t to_reg;
   
   logic bypass, fifo_push, fifo_pop;

   generate
   if (!output_reg) begin

      fifo_buffer #(.init_fifo_contents(init_fifo_contents), 

		    .size(always_write+size), .output_reg(0), 
		    .low_power(low_power), .always_write(always_write))
         fifo_buf (push, pop, data_in, data_out, second_data, clk, rst_n);

      assign second_data_out = second_data;
      
   end else begin



      fifo_buffer #(.init_fifo_contents(init_fifo_contents),

		    .size(always_write+size), .output_reg(0), .low_power(low_power),
		    .always_write(always_write))
         fifo_buf (push, pop, data_in, fifo_data_out, second_data, clk, rst_n);






      fifo_flags #(.size(always_write+size), 
		   .init_fifo_contents(init_fifo_contents)) gen_localflags
	(push, pop, local_flags, clk, rst_n);   

      always@(posedge clk) begin
	 if (!rst_n) begin

            if (init_fifo_contents!=0) begin
               fifo_out_reg<=1;
            end
	 end else begin
	    fifo_out_reg<=to_reg;


	    
	 end
      end


      always_comb
	begin
           if (local_flags.empty || (local_flags.nearly_empty && pop)) begin
              if (push) begin
		 to_reg = data_in;
              end else begin


		 to_reg = '0;
              end
           end else if (pop) begin
	      to_reg = second_data;
           end else begin
              to_reg = fifo_data_out;
           end
	end
      
      assign data_out = fifo_out_reg;
      assign second_data_out = second_data;

   end
   endgenerate
   
endmodule