data/full_repos/permissive/135822174/api/static/F721000/109_1/1/lab11.v
 line:238: before: "begin"
1: b'%Warning-WIDTH: data/full_repos/permissive/135822174/api/static/F721000/109_1/1/lab11.v:289: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h0\' generates 31 bits.\n                                                                                           : ... In instance lab11.keypad_detect\n   keypadDelay <= 31\'d0;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/135822174/api/static/F721000/109_1/1/lab11.v:295: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h0\' generates 31 bits.\n                                                                                           : ... In instance lab11.keypad_detect\n    keypadDelay <= 31\'d0;\n                ^~\n%Error: Exiting due to 2 warning(s)\n'
module clk_divi (clk,rst,counter,div_clk);
	input clk,rst;
	input [31:0]counter;
	output div_clk;
	reg div_clk;
	reg [31:0]count;
	always @ (posedge clk)
	begin 
		if (!rst)
		begin 
		count <= 32'd0;
		div_clk <=1'b0;
		end
		else
		begin 
			if (count == counter)
			begin 
			count<=32'd0;
			div_clk <=~div_clk;
			end
			else
			begin 
				count <= count + 32'd1;
			end
		end
   end
endmodule
module clk_divi (clk,rst,counter,div_clk);

	input clk,rst;
	input [31:0]counter;
	output div_clk;
	reg div_clk;
	reg [31:0]count;
	always @ (posedge clk)
	begin 
		if (!rst)
		begin 
		count <= 32'd0;
		div_clk <=1'b0;
		end
		else
		begin 
			if (count == counter)
			begin 
			count<=32'd0;
			div_clk <=~div_clk;
			end
			else
			begin 
				count <= count + 32'd1;
			end
		end
   end
endmodule