data/full_repos/permissive/207610706/src/key_schedule_storage/circular_lifo.sv
 line:30: before: "+"
1: b'%Warning-LITENDIAN: data/full_repos/permissive/207610706/src/key_schedule_storage/circular_lifo.sv:10: Little bit endian vector: MSB < LSB of bit range: 0:31\ninput [0:WIDTH-1] din;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/207610706/src/key_schedule_storage/circular_lifo.sv:13: Little bit endian vector: MSB < LSB of bit range: 0:31\noutput [0:WIDTH-1] dout;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/207610706/src/key_schedule_storage/circular_lifo.sv:15: Little bit endian vector: MSB < LSB of bit range: 0:31\nreg [0:WIDTH-1] internal_regs[0:DEPTH-1];\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/207610706/src/key_schedule_storage/circular_lifo.sv:16: Little bit endian vector: MSB < LSB of bit range: 0:31\nreg [0:WIDTH-1] next_internal_regs[0:DEPTH-1];\n    ^\n%Error: Exiting due to 4 warning(s)\n'
module circular_lifo
#(parameter WIDTH=32, parameter DEPTH=8)
    (
        clk, rst,
        din, dout,
        en, r_wneg
    );

input clk, rst;
input [0:WIDTH-1] din;
input en, r_wneg;

output [0:WIDTH-1] dout;

reg [0:WIDTH-1] internal_regs[0:DEPTH-1];
reg [0:WIDTH-1] next_internal_regs[0:DEPTH-1];



integer j;
always@(posedge clk)
begin
    for(j=0; j < DEPTH; j++)
    begin
        if(rst)
            internal_regs[j] <= {WIDTH{1'b0}};
        else if(en)
            internal_regs[j] <= next_internal_regs[j];
    end
end

integer i;
always@(*)
begin
    next_internal_regs[0] = r_wneg ? din : internal_regs[1];
    next_internal_regs[DEPTH-1] = r_wneg ? internal_regs[DEPTH-2] : internal_regs[0];
    
    for(i=1; i < DEPTH-1; i++)
        next_internal_regs[i] = r_wneg ? internal_regs[i-1] : internal_regs[i+1];
end

assign dout = internal_regs[0];

endmodule
module circular_lifo
#(parameter WIDTH=32, parameter DEPTH=8)
    (
        clk, rst,
        din, dout,
        en, r_wneg
    );


input clk, rst;
input [0:WIDTH-1] din;
input en, r_wneg;

output [0:WIDTH-1] dout;

reg [0:WIDTH-1] internal_regs[0:DEPTH-1];
reg [0:WIDTH-1] next_internal_regs[0:DEPTH-1];



integer j;
always@(posedge clk)
begin
    for(j=0; j < DEPTH; j++)
    begin
        if(rst)
            internal_regs[j] <= {WIDTH{1'b0}};
        else if(en)
            internal_regs[j] <= next_internal_regs[j];
    end
end

integer i;
always@(*)
begin
    next_internal_regs[0] = r_wneg ? din : internal_regs[1];
    next_internal_regs[DEPTH-1] = r_wneg ? internal_regs[DEPTH-2] : internal_regs[0];
    
    for(i=1; i < DEPTH-1; i++)
        next_internal_regs[i] = r_wneg ? internal_regs[i-1] : internal_regs[i+1];
end

assign dout = internal_regs[0];

endmodule