data/full_repos/permissive/143278/ivltests/br_gh283c.v
data/verilator_xmls/f490d685-6b87-4ddc-9625-076eb3c87bd2.xml
module bug();

reg        d;
reg [31:0] x;
reg [31:0] y;
reg [31:0] z;

initial begin
  d = 1;
  x = 32'hffffffff << {d, 64'd0};
  y = 32'hffffffff >> {d, 64'd0};
  z = 32'hffffffff >>> {d, 64'd0};
  $display("%h", x);
  $display("%h", y);
  $display("%h", z);
  if (x === 32'd0 && y === 32'd0 && z === 32'd0)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module bug();


reg        d;
reg [31:0] x;
reg [31:0] y;
reg [31:0] z;

initial begin
  d = 1;
  x = 32'hffffffff << {d, 64'd0};
  y = 32'hffffffff >> {d, 64'd0};
  z = 32'hffffffff >>> {d, 64'd0};
  $display("%h", x);
  $display("%h", y);
  $display("%h", z);
  if (x === 32'd0 && y === 32'd0 && z === 32'd0)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule