data/full_repos/permissive/104269513/control_logic.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/control_logic.v:238: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/104269513/control_logic.v:229: Cell has missing pin: \'PL_done\'\ncontrol control(.instruction(instruction), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .Jump(Jump), .ble(ble), .imme(imme), .ALUop(ALUop), .Master_reg(Master_reg), .mem_sel(mem_sel));\n        ^~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/104269513/control_logic.v:229: Cell has missing pin: \'FW_ld\'\ncontrol control(.instruction(instruction), .RegWrite(RegWrite), .ALUSrc(ALUSrc), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .Jump(Jump), .ble(ble), .imme(imme), .ALUop(ALUop), .Master_reg(Master_reg), .mem_sel(mem_sel));\n        ^~~~~~~\n%Warning-INFINITELOOP: data/full_repos/permissive/104269513/control_logic.v:238: Infinite loop (condition always true)\n                                                                               : ... In instance control_tb\nforever #10 clk = ~clk;\n^~~~~~~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control (
				input [31:0] instruction,
				output reg RegWrite,
				output reg ALUSrc,
				output reg MemWrite,
				output reg MemtoReg,	
				output reg Jump,	
				output reg ble,	
				output reg imme, 
				output reg PL_done,
				output reg FW_ld,
				output reg [3:0] ALUop,
				output reg [2:0] Master_reg,
				output reg mem_sel);

wire [6:0]opcode;
wire [2:0]func3;
wire [6:0]func7;


assign opcode = instruction[6:0];
assign func3 = instruction[14:12];
assign func7 = instruction[31:25];


always @(*)
begin
RegWrite = 0;
ALUSrc = 0;
MemWrite = 0;
MemtoReg = 0;
Jump = 0;
ble = 0;
imme = 0;
ALUop = 'd0;
FW_ld = 0;
PL_done = 0;
Master_reg = 'd0;
mem_sel = 'b0;
	case (opcode)	
		
			`ADDIW: 
					begin										
					RegWrite = 'b1;
					ALUSrc = 'b1;
					MemtoReg = 'b1;
					imme = 'b1;
					PL_done = 0;
					end	
					
			`IMMEDIATE:
					begin
					RegWrite = 'b1;
					ALUSrc = 'b1;
					MemtoReg = 'b1;
					imme = 'b1;
					PL_done = 0;
					if (func3 == 'b000)
						ALUop = 'd0;
					
					else if(func3 == 'b001)
						ALUop='d6;
					
					else if(func3 == 'b100)
						ALUop='d4;
						
					else if(func3 == 'b101) 
						if ((func7 == 'b0000000) || (func7 == 'b0000001))
							ALUop = 'd7;
						
						else if((func7 == 'b0100000) || (func7 == 'b0100001))
							ALUop = 'd8;
						
					else
						ALUop='d0;
					end
					
			`ADD_SUB_AND_OR:
					begin
					RegWrite = 'b1;
					MemtoReg = 'b1;
					PL_done = 0;
					if (func7 == 'b0000000)
						if(func3 == 'b000) 
							ALUop = 'd0;
						else if(func3 == 'b110) 
							ALUop = 'd3;
						else if(func3 == 'b111) 
							ALUop = 'd2;
						
					else if(func7 == 'b0100000)
						ALUop = 'd1;
						
					else
						ALUop = 'd0;
					end
			
			`SD:
					begin
					if(func3 == 'b111) 
						mem_sel = 'b1;
					else
						mem_sel = 'b0;
					ALUSrc = 'b1;
					MemWrite = 'b1;
					PL_done = 0;
					end
			
			`BLE:	begin
					 ble = 'b1;
					 PL_done = 0;
					end
				
			`LD:
					begin
					if(func3 == 'b111) 
						mem_sel = 'b1;
					else
						mem_sel = 'b0;					
					RegWrite = 'b1;
					ALUSrc = 'b1;
					imme = 'b1;
					PL_done = 0;
					end
					
			`J:
					begin 
					RegWrite = 'b1;
					Jump = 'b1;
					PL_done = 0;
					end
					
			`FIFO:
					begin
					FW_ld = 0;
					PL_done = 0;
					if (func3 == 'b000)
						begin
						FW_ld = 1;
						RegWrite = 'b1;
						end
					else if(func3 == 'b001)
						PL_done = 1;	
					else
					begin
						FW_ld = 0;
						PL_done = 0;
					end
					end
					
			`Master_Control:
					begin
					if (func3 == 'b000)
						Master_reg = 'b000;
					if (func3 == 'b001)
						Master_reg = 'b001;
					if (func3 == 'b010)
						Master_reg = 'b010;
					if (func3 == 'b011)
						Master_reg = 'b011;
					if (func3 == 'b100)
						Master_reg = 'b100;
					if (func3 == 'b101)
						Master_reg = 'b101;
					if (func3 == 'b110)
						Master_reg = 'b110;
					end
					
			default:
					begin
						RegWrite = 0;
						ALUSrc = 0;
						MemWrite = 0;
						MemtoReg = 0;
						Jump = 0;
						ble = 0;
						imme = 0;
						ALUop = 'd0;
						FW_ld = 0;
						PL_done = 0;
						Master_reg = 'd0;
						mem_sel = 'b0;
					end
	endcase
	
end
endmodule
module control (
				input [31:0] instruction,
				output reg RegWrite,
				output reg ALUSrc,
				output reg MemWrite,
				output reg MemtoReg,	
				output reg Jump,	
				output reg ble,	
				output reg imme, 
				output reg PL_done,
				output reg FW_ld,
				output reg [3:0] ALUop,
				output reg [2:0] Master_reg,
				output reg mem_sel);


wire [6:0]opcode;
wire [2:0]func3;
wire [6:0]func7;


assign opcode = instruction[6:0];
assign func3 = instruction[14:12];
assign func7 = instruction[31:25];


always @(*)
begin
RegWrite = 0;
ALUSrc = 0;
MemWrite = 0;
MemtoReg = 0;
Jump = 0;
ble = 0;
imme = 0;
ALUop = 'd0;
FW_ld = 0;
PL_done = 0;
Master_reg = 'd0;
mem_sel = 'b0;
	case (opcode)	
		
			`ADDIW: 
					begin										
					RegWrite = 'b1;
					ALUSrc = 'b1;
					MemtoReg = 'b1;
					imme = 'b1;
					PL_done = 0;
					end	
					
			`IMMEDIATE:
					begin
					RegWrite = 'b1;
					ALUSrc = 'b1;
					MemtoReg = 'b1;
					imme = 'b1;
					PL_done = 0;
					if (func3 == 'b000)
						ALUop = 'd0;
					
					else if(func3 == 'b001)
						ALUop='d6;
					
					else if(func3 == 'b100)
						ALUop='d4;
						
					else if(func3 == 'b101) 
						if ((func7 == 'b0000000) || (func7 == 'b0000001))
							ALUop = 'd7;
						
						else if((func7 == 'b0100000) || (func7 == 'b0100001))
							ALUop = 'd8;
						
					else
						ALUop='d0;
					end
					
			`ADD_SUB_AND_OR:
					begin
					RegWrite = 'b1;
					MemtoReg = 'b1;
					PL_done = 0;
					if (func7 == 'b0000000)
						if(func3 == 'b000) 
							ALUop = 'd0;
						else if(func3 == 'b110) 
							ALUop = 'd3;
						else if(func3 == 'b111) 
							ALUop = 'd2;
						
					else if(func7 == 'b0100000)
						ALUop = 'd1;
						
					else
						ALUop = 'd0;
					end
			
			`SD:
					begin
					if(func3 == 'b111) 
						mem_sel = 'b1;
					else
						mem_sel = 'b0;
					ALUSrc = 'b1;
					MemWrite = 'b1;
					PL_done = 0;
					end
			
			`BLE:	begin
					 ble = 'b1;
					 PL_done = 0;
					end
				
			`LD:
					begin
					if(func3 == 'b111) 
						mem_sel = 'b1;
					else
						mem_sel = 'b0;					
					RegWrite = 'b1;
					ALUSrc = 'b1;
					imme = 'b1;
					PL_done = 0;
					end
					
			`J:
					begin 
					RegWrite = 'b1;
					Jump = 'b1;
					PL_done = 0;
					end
					
			`FIFO:
					begin
					FW_ld = 0;
					PL_done = 0;
					if (func3 == 'b000)
						begin
						FW_ld = 1;
						RegWrite = 'b1;
						end
					else if(func3 == 'b001)
						PL_done = 1;	
					else
					begin
						FW_ld = 0;
						PL_done = 0;
					end
					end
					
			`Master_Control:
					begin
					if (func3 == 'b000)
						Master_reg = 'b000;
					if (func3 == 'b001)
						Master_reg = 'b001;
					if (func3 == 'b010)
						Master_reg = 'b010;
					if (func3 == 'b011)
						Master_reg = 'b011;
					if (func3 == 'b100)
						Master_reg = 'b100;
					if (func3 == 'b101)
						Master_reg = 'b101;
					if (func3 == 'b110)
						Master_reg = 'b110;
					end
					
			default:
					begin
						RegWrite = 0;
						ALUSrc = 0;
						MemWrite = 0;
						MemtoReg = 0;
						Jump = 0;
						ble = 0;
						imme = 0;
						ALUop = 'd0;
						FW_ld = 0;
						PL_done = 0;
						Master_reg = 'd0;
						mem_sel = 'b0;
					end
	endcase
	
end
endmodule