data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog/uart.v
1: b"%Error: data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog/uart.v:59: Cannot find file containing module: 'baud_rate_gen'\n    baud_rate_gen #(\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog,data/full_repos/permissive/206437232/baud_rate_gen\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog,data/full_repos/permissive/206437232/baud_rate_gen.v\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog,data/full_repos/permissive/206437232/baud_rate_gen.sv\n             baud_rate_gen\n             baud_rate_gen.v\n             baud_rate_gen.sv\n             obj_dir/baud_rate_gen\n             obj_dir/baud_rate_gen.v\n             obj_dir/baud_rate_gen.sv\n%Error: data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog/uart.v:71: Cannot find file containing module: 'rx'\n    rx #(\n    ^~\n%Error: data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog/uart.v:85: Cannot find file containing module: 'tx'\n    tx  #(\n    ^~\n%Error: data/full_repos/permissive/206437232/TP3-BIP1-2019/Verilog/uart.v:100: Cannot find file containing module: 'interface_circuit'\n    interface_circuit #(\n    ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module uart   #(


      parameter DBIT = 8,
                SB_TICK = 16,

                BAUDRATE_DIVISOR = 651,
                BAUDRATE_DIVISOR_BITS = 10,
                NB_OP = 6
   )
   (

    input wire              i_clk, 
    input wire              i_reset,
    input wire              RsRx,

    output wire             RsTx
   );
    


    wire             tick;
    wire             rx_done_tick;
    wire             tx_done_tick;
    wire             tx_empty;
    wire             tx_start;
    wire [DBIT-1:0]  tx_data_out; 
    wire [DBIT-1:0]  rx_data_out;
    wire [DBIT-1:0]  data_a;
    wire [DBIT-1:0]  data_b;   
    wire [DBIT-1:0]  o_alu;
    wire [NB_OP-1:0] operation;
    wire o_tx;
   
    assign RsTx = o_tx;
   

    baud_rate_gen #(
        .BAUDRATE_DIVISOR       (BAUDRATE_DIVISOR),
        .BAUDRATE_DIVISOR_BITS  (BAUDRATE_DIVISOR_BITS)
    )
    u_baud_rate (
        .i_clk          (i_clk),
        .i_reset        (i_reset),
        .o_tick         (tick)      
    );



    rx #(
        .DBIT(DBIT),
        .SB_TICK(SB_TICK)
    ) 
    u_rx
      ( .i_clk          (i_clk),
        .i_reset        (i_reset),
        .rx             (RsRx), 
        .s_tick         (tick),
        .rx_done_tick   (rx_done_tick),
        .o_data_out     (rx_data_out)
      );
    

    tx  #(
        .DBIT(DBIT),
        .SB_TICK(SB_TICK)
    ) 
    u_tx
      ( .i_clk          (i_clk), 
        .i_reset        (i_reset), 
        .tx_start       (tx_start),
        .s_tick         (tick), 
        .din            (tx_data_out),
        .tx_done_tick   (tx_done_tick), 
        .tx             (o_tx)
      );
      

    interface_circuit #(
        .DBIT(DBIT),
        .NB_OP(NB_OP)
    )
    u_interface_circuit
    (
        .i_clk            (i_clk),
        .i_reset          (i_reset),
        .i_rx_done_tick   (rx_done_tick),
        .i_rx_data_in     (rx_data_out),
        .i_alu_data_in    (o_alu),

        .o_data_a         (data_a),
        .o_data_b         (data_b),
        .o_operation      (operation),  
        .o_tx_start       (tx_start), 
        .o_data_out       (tx_data_out)
    );

endmodule
module uart   #(


      parameter DBIT = 8,
                SB_TICK = 16,

                BAUDRATE_DIVISOR = 651,
                BAUDRATE_DIVISOR_BITS = 10,
                NB_OP = 6
   )
   (

    input wire              i_clk, 
    input wire              i_reset,
    input wire              RsRx,

    output wire             RsTx
   );

    


    wire             tick;
    wire             rx_done_tick;
    wire             tx_done_tick;
    wire             tx_empty;
    wire             tx_start;
    wire [DBIT-1:0]  tx_data_out; 
    wire [DBIT-1:0]  rx_data_out;
    wire [DBIT-1:0]  data_a;
    wire [DBIT-1:0]  data_b;   
    wire [DBIT-1:0]  o_alu;
    wire [NB_OP-1:0] operation;
    wire o_tx;
   
    assign RsTx = o_tx;
   

    baud_rate_gen #(
        .BAUDRATE_DIVISOR       (BAUDRATE_DIVISOR),
        .BAUDRATE_DIVISOR_BITS  (BAUDRATE_DIVISOR_BITS)
    )
    u_baud_rate (
        .i_clk          (i_clk),
        .i_reset        (i_reset),
        .o_tick         (tick)      
    );



    rx #(
        .DBIT(DBIT),
        .SB_TICK(SB_TICK)
    ) 
    u_rx
      ( .i_clk          (i_clk),
        .i_reset        (i_reset),
        .rx             (RsRx), 
        .s_tick         (tick),
        .rx_done_tick   (rx_done_tick),
        .o_data_out     (rx_data_out)
      );
    

    tx  #(
        .DBIT(DBIT),
        .SB_TICK(SB_TICK)
    ) 
    u_tx
      ( .i_clk          (i_clk), 
        .i_reset        (i_reset), 
        .tx_start       (tx_start),
        .s_tick         (tick), 
        .din            (tx_data_out),
        .tx_done_tick   (tx_done_tick), 
        .tx             (o_tx)
      );
      

    interface_circuit #(
        .DBIT(DBIT),
        .NB_OP(NB_OP)
    )
    u_interface_circuit
    (
        .i_clk            (i_clk),
        .i_reset          (i_reset),
        .i_rx_done_tick   (rx_done_tick),
        .i_rx_data_in     (rx_data_out),
        .i_alu_data_in    (o_alu),

        .o_data_a         (data_a),
        .o_data_b         (data_b),
        .o_operation      (operation),  
        .o_tx_start       (tx_start), 
        .o_data_out       (tx_data_out)
    );

endmodule