data/full_repos/permissive/154590168/rtl_cpu/ALU.v
1: b'%Error: data/full_repos/permissive/154590168/rtl_cpu/ALU.v:27: Cannot find include file: OpNumber.v\n`include "OpNumber.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v.v\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/OpNumber.v.sv\n             OpNumber.v\n             OpNumber.v.v\n             OpNumber.v.sv\n             obj_dir/OpNumber.v\n             obj_dir/OpNumber.v.v\n             obj_dir/OpNumber.v.sv\n%Error: Exiting due to 1 error(s)\n'
module  ALU (
    input   [15:0]  ai,
    input   [15:0]  bi,
    input           ci,
    input           sel_adc_b,
    input           sel_sbc_b,
    input           sel_adc_w,
    input           sel_sbc_w,
    input           sel_and,
    input           sel_or,
    input           sel_eor,
    input           sr_zf,
    input   [0:82]  op_decode,
    output  [15:0]  ro,
    output          cf,
    output          zf,
    output          nf,
    output          vf,
    output          sf,
    output          hf
);


`include "OpNumber.v"
wire    op_sbc    = op_decode[B_SBC   ];
wire    op_sbci   = op_decode[B_SBCI  ];
wire    op_cpc    = op_decode[B_CPC   ];
wire    op_asr    = op_decode[B_ASR   ];
wire    op_lsr    = op_decode[B_LSR   ];
wire    op_ror    = op_decode[B_ROR   ];
wire    op_swap   = op_decode[B_SWAP  ];


wire[15:0]  sw_bi;
wire        sw_ci;
wire[15:0]  so;
wire        co;
wire        adc_b_hf;
wire        adc_b_cf;
wire        adc_b_vf;
wire        adc_w_vf;
wire[7:0]   ai_l;
wire[7:0]   bi_l;
wire[7:0]   and_ro;
wire[7:0]   or_ro;
wire[7:0]   eor_ro;
wire[7:0]   asr_ro;
wire[7:0]   lsr_ro;
wire[7:0]   ror_ro;
wire        asr_cf;
wire        lsr_cf;
wire        ror_cf;
wire        asr_vf;
wire        lsr_vf;
wire        ror_vf;
wire[7:0]   swap_ro;
wire        sel_adc_sbc;
wire        byte_op;
wire        word_op;
wire        zf_and_op;


assign  sw_bi = (sel_sbc_b | sel_sbc_w) ? ~bi : bi;
assign  sw_ci = (sel_sbc_b | sel_sbc_w) ? ~ci : ci;


assign  {co, so} = ai + sw_bi + sw_ci;

assign  adc_b_hf = (ai[3] & sw_bi[3]) | (ai[3] & ~so[3]) | (sw_bi[3] & ~so[3]);
assign  adc_b_cf = (ai[7] & sw_bi[7]) | (ai[7] & ~so[7]) | (sw_bi[7] & ~so[7]);
assign  adc_b_vf = (~ai[ 7] & ~sw_bi[ 7] & so[ 7]) | (ai[ 7] & sw_bi[ 7] & ~so[ 7]);
assign  adc_w_vf = (~ai[15] & ~sw_bi[15] & so[15]) | (ai[15] & sw_bi[15] & ~so[15]);


assign  ai_l = ai[7:0];
assign  bi_l = bi[7:0];

assign  and_ro = ai_l & bi_l;
assign  or_ro  = ai_l | bi_l;
assign  eor_ro = ai_l ^ bi_l;


assign  {asr_ro, asr_cf} = {ai_l[7], ai_l};
assign  {lsr_ro, lsr_cf} = {1'b0, ai_l};
assign  {ror_ro, ror_cf} = {ci, ai_l};

assign  asr_vf = asr_ro[7] ^ asr_cf;
assign  lsr_vf = lsr_ro[7] ^ lsr_cf;
assign  ror_vf = ror_ro[7] ^ ror_cf;


assign  swap_ro = {ai_l[3:0], ai_l[7:4]};


assign  sel_adc_sbc = sel_adc_b | sel_sbc_b
                    | sel_adc_w | sel_sbc_w;

assign  ro = (sel_adc_sbc ? so : 16'h0000)
           | (sel_and ? {8'h00, and_ro } : 16'h0000)
           | (sel_or  ? {8'h00, or_ro  } : 16'h0000)
           | (sel_eor ? {8'h00, eor_ro } : 16'h0000)
           | (op_asr  ? {8'h00, asr_ro } : 16'h0000)
           | (op_lsr  ? {8'h00, lsr_ro } : 16'h0000)
           | (op_ror  ? {8'h00, ror_ro } : 16'h0000)
           | (op_swap ? {8'h00, swap_ro} : 16'h0000);


assign  byte_op = sel_adc_b
                | sel_sbc_b
                | sel_and
                | sel_or
                | sel_eor
                | op_asr
                | op_lsr
                | op_ror
                | op_swap;

assign  word_op = sel_adc_w
                | sel_sbc_w;

assign  zf_and_op = op_sbc
                  | op_sbci
                  | op_cpc;

assign  cf = (sel_adc_b & adc_b_cf)
           | (sel_sbc_b & ~adc_b_cf)
           | (sel_adc_w & co)
           | (sel_sbc_w & ~co)
           | (op_asr & asr_cf)
           | (op_lsr & lsr_cf)
           | (op_ror & ror_cf);

assign  zf = ((byte_op &  zf_and_op) & (sr_zf & (ro[7:0] == 8'h00)))
           | ((byte_op & ~zf_and_op) & (ro[7:0] == 8'h00))
           | (word_op & (ro == 16'h0000));

assign  nf = (byte_op & ro[7])
           | (word_op & ro[15]);

assign  vf = ((sel_adc_b | sel_sbc_b) & adc_b_vf)
           | ((sel_adc_w | sel_sbc_w) & adc_w_vf)
           | (op_asr & asr_vf)
           | (op_lsr & lsr_vf)
           | (op_ror & ror_vf);

assign  sf = nf ^ vf;

assign  hf = (sel_adc_b & adc_b_hf)
           | (sel_sbc_b & ~adc_b_hf);

endmodule
module  ALU (
    input   [15:0]  ai,
    input   [15:0]  bi,
    input           ci,
    input           sel_adc_b,
    input           sel_sbc_b,
    input           sel_adc_w,
    input           sel_sbc_w,
    input           sel_and,
    input           sel_or,
    input           sel_eor,
    input           sr_zf,
    input   [0:82]  op_decode,
    output  [15:0]  ro,
    output          cf,
    output          zf,
    output          nf,
    output          vf,
    output          sf,
    output          hf
);



`include "OpNumber.v"
wire    op_sbc    = op_decode[B_SBC   ];
wire    op_sbci   = op_decode[B_SBCI  ];
wire    op_cpc    = op_decode[B_CPC   ];
wire    op_asr    = op_decode[B_ASR   ];
wire    op_lsr    = op_decode[B_LSR   ];
wire    op_ror    = op_decode[B_ROR   ];
wire    op_swap   = op_decode[B_SWAP  ];


wire[15:0]  sw_bi;
wire        sw_ci;
wire[15:0]  so;
wire        co;
wire        adc_b_hf;
wire        adc_b_cf;
wire        adc_b_vf;
wire        adc_w_vf;
wire[7:0]   ai_l;
wire[7:0]   bi_l;
wire[7:0]   and_ro;
wire[7:0]   or_ro;
wire[7:0]   eor_ro;
wire[7:0]   asr_ro;
wire[7:0]   lsr_ro;
wire[7:0]   ror_ro;
wire        asr_cf;
wire        lsr_cf;
wire        ror_cf;
wire        asr_vf;
wire        lsr_vf;
wire        ror_vf;
wire[7:0]   swap_ro;
wire        sel_adc_sbc;
wire        byte_op;
wire        word_op;
wire        zf_and_op;


assign  sw_bi = (sel_sbc_b | sel_sbc_w) ? ~bi : bi;
assign  sw_ci = (sel_sbc_b | sel_sbc_w) ? ~ci : ci;


assign  {co, so} = ai + sw_bi + sw_ci;

assign  adc_b_hf = (ai[3] & sw_bi[3]) | (ai[3] & ~so[3]) | (sw_bi[3] & ~so[3]);
assign  adc_b_cf = (ai[7] & sw_bi[7]) | (ai[7] & ~so[7]) | (sw_bi[7] & ~so[7]);
assign  adc_b_vf = (~ai[ 7] & ~sw_bi[ 7] & so[ 7]) | (ai[ 7] & sw_bi[ 7] & ~so[ 7]);
assign  adc_w_vf = (~ai[15] & ~sw_bi[15] & so[15]) | (ai[15] & sw_bi[15] & ~so[15]);


assign  ai_l = ai[7:0];
assign  bi_l = bi[7:0];

assign  and_ro = ai_l & bi_l;
assign  or_ro  = ai_l | bi_l;
assign  eor_ro = ai_l ^ bi_l;


assign  {asr_ro, asr_cf} = {ai_l[7], ai_l};
assign  {lsr_ro, lsr_cf} = {1'b0, ai_l};
assign  {ror_ro, ror_cf} = {ci, ai_l};

assign  asr_vf = asr_ro[7] ^ asr_cf;
assign  lsr_vf = lsr_ro[7] ^ lsr_cf;
assign  ror_vf = ror_ro[7] ^ ror_cf;


assign  swap_ro = {ai_l[3:0], ai_l[7:4]};


assign  sel_adc_sbc = sel_adc_b | sel_sbc_b
                    | sel_adc_w | sel_sbc_w;

assign  ro = (sel_adc_sbc ? so : 16'h0000)
           | (sel_and ? {8'h00, and_ro } : 16'h0000)
           | (sel_or  ? {8'h00, or_ro  } : 16'h0000)
           | (sel_eor ? {8'h00, eor_ro } : 16'h0000)
           | (op_asr  ? {8'h00, asr_ro } : 16'h0000)
           | (op_lsr  ? {8'h00, lsr_ro } : 16'h0000)
           | (op_ror  ? {8'h00, ror_ro } : 16'h0000)
           | (op_swap ? {8'h00, swap_ro} : 16'h0000);


assign  byte_op = sel_adc_b
                | sel_sbc_b
                | sel_and
                | sel_or
                | sel_eor
                | op_asr
                | op_lsr
                | op_ror
                | op_swap;

assign  word_op = sel_adc_w
                | sel_sbc_w;

assign  zf_and_op = op_sbc
                  | op_sbci
                  | op_cpc;

assign  cf = (sel_adc_b & adc_b_cf)
           | (sel_sbc_b & ~adc_b_cf)
           | (sel_adc_w & co)
           | (sel_sbc_w & ~co)
           | (op_asr & asr_cf)
           | (op_lsr & lsr_cf)
           | (op_ror & ror_cf);

assign  zf = ((byte_op &  zf_and_op) & (sr_zf & (ro[7:0] == 8'h00)))
           | ((byte_op & ~zf_and_op) & (ro[7:0] == 8'h00))
           | (word_op & (ro == 16'h0000));

assign  nf = (byte_op & ro[7])
           | (word_op & ro[15]);

assign  vf = ((sel_adc_b | sel_sbc_b) & adc_b_vf)
           | ((sel_adc_w | sel_sbc_w) & adc_w_vf)
           | (op_asr & asr_vf)
           | (op_lsr & lsr_vf)
           | (op_ror & ror_vf);

assign  sf = nf ^ vf;

assign  hf = (sel_adc_b & adc_b_hf)
           | (sel_sbc_b & ~adc_b_hf);

endmodule