data/full_repos/permissive/109608368/memory/Enable_control.v
data/verilator_xmls/ddec4607-72f3-4e03-8c64-8cadd3d3a7db.xml
module Enable_control(current_state, out);
    input [1:0] current_state;
    output reg out;
    
    always@(*)
    begin

        if(current_state[1:0] != 2'b00) out <= 0;
        else out <= 1;
    end
endmodule
module Enable_control(current_state, out);

    input [1:0] current_state;
    output reg out;
    
    always@(*)
    begin

        if(current_state[1:0] != 2'b00) out <= 0;
        else out <= 1;
    end
endmodule