data/full_repos/permissive/100822769/data_memory.v
data/verilator_xmls/c3206005-371a-4f21-a401-2f96d45c9e32.xml
module data_memory(


	clk,
	addr,
	rdata,
	wdata,
	wren
);


    
	input clk;
    input [31:0] addr;
	input [31:0] wdata;
	input [3:0] wren;
	

   
    output [31:0] rdata;


 
    reg	[7:0] memory_lane0	[65535:0];
    reg	[7:0] memory_lane1	[65535:0];
    reg	[7:0] memory_lane2	[65535:0];
    reg	[7:0] memory_lane3	[65535:0];
    


   
	assign rdata = {
						memory_lane3[addr[17:2]],
						memory_lane2[addr[17:2]],
						memory_lane1[addr[17:2]],
						memory_lane0[addr[17:2]]
					};


    						
	
    always @(posedge clk)
	begin
		if (wren[0])
			memory_lane0[addr[17:2]] <= wdata[7:0];
			
		if (wren[1])
			memory_lane1[addr[17:2]] <= wdata[15:8];
			
		if (wren[2])
			memory_lane2[addr[17:2]] <= wdata[23:16];
			
		if (wren[3])
			memory_lane3[addr[17:2]] <= wdata[31:24];
	end
	
 endmodule
module data_memory(


	clk,
	addr,
	rdata,
	wdata,
	wren
);



    
	input clk;
    input [31:0] addr;
	input [31:0] wdata;
	input [3:0] wren;
	

   
    output [31:0] rdata;


 
    reg	[7:0] memory_lane0	[65535:0];
    reg	[7:0] memory_lane1	[65535:0];
    reg	[7:0] memory_lane2	[65535:0];
    reg	[7:0] memory_lane3	[65535:0];
    


   
	assign rdata = {
						memory_lane3[addr[17:2]],
						memory_lane2[addr[17:2]],
						memory_lane1[addr[17:2]],
						memory_lane0[addr[17:2]]
					};


    						
	
    always @(posedge clk)
	begin
		if (wren[0])
			memory_lane0[addr[17:2]] <= wdata[7:0];
			
		if (wren[1])
			memory_lane1[addr[17:2]] <= wdata[15:8];
			
		if (wren[2])
			memory_lane2[addr[17:2]] <= wdata[23:16];
			
		if (wren[3])
			memory_lane3[addr[17:2]] <= wdata[31:24];
	end
	
 endmodule