data/full_repos/permissive/109936328/tb/tb_memory_interface.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/tb,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:2: Cannot find include file: mem_codes.vh\n`include "mem_codes.vh" \n         ^~~~~~~~~~~~~~\n%Warning-BSSPACE: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:4: Backslash followed by whitespace, perhaps the whitespace is accidental?\n`define ASSERT(cond)\\  \n                    ^\n                  ... Use "/* verilator lint_off BSSPACE */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:5: syntax error, unexpected if\n  if(!(cond)) begin \\\n  ^~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:24: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] req_addr;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:26: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] req_wr_data;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:28: Define or directive not defined: \'`MEM_COUNT_W\'\n  reg [`MEM_COUNT_W - 1:0] req_count;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:33: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] rd_data;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:36: Define or directive not defined: \'`MEM_CODE_W\'\n  wire [`MEM_CODE_W - 1:0] res_code;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:39: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] test_addr [0:TEST_DATA_SIZE - 1];\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:41: Define or directive not defined: \'`MEM_COUNT_W\'\n  reg [`MEM_COUNT_W - 1:0] test_count [0:TEST_DATA_SIZE - 1];\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:43: Define or directive not defined: \'`WORD_W\'\n  reg [`WORD_W - 1:0] test_data [0:TEST_DATA_SIZE - 1];\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:69: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_memory_interface.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:70: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:78: Define or directive not defined: \'`MEM_COUNT_NONE\'\n    req_count = `MEM_COUNT_NONE;\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:78: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    req_count = `MEM_COUNT_NONE;\n                               ^\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:84: Unsupported or unknown PLI call: $urandom\n      test_count[i] = $urandom % 3 + 1;\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:87: Unsupported or unknown PLI call: $urandom\n      test_data[i] = $urandom;\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:91: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n        `MEM_COUNT_BYTE: begin\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:91: syntax error, unexpected \':\', expecting endcase\n        `MEM_COUNT_BYTE: begin\n                       ^\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:93: Unsupported or unknown PLI call: $urandom\n          test_addr[i][1:0] = $urandom % 4;\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:97: Define or directive not defined: \'`MEM_COUNT_HALF\'\n        `MEM_COUNT_HALF: begin\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:97: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n        `MEM_COUNT_HALF: begin\n                         ^~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:100: Unsupported or unknown PLI call: $urandom\n          test_addr[i][1] = $urandom % 2;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:103: syntax error, unexpected endcase\n      endcase\n      ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:112: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD);\n    ^\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:122: Define or directive not defined: \'`MEM_COUNT_WORD\'\n    req_count = `MEM_COUNT_WORD;\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:122: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    req_count = `MEM_COUNT_WORD;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:126: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:143: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:152: Define or directive not defined: \'`MEM_COUNT_BYTE\'\n        `MEM_COUNT_BYTE: begin\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:152: syntax error, unexpected \':\', expecting endcase\n        `MEM_COUNT_BYTE: begin\n                       ^\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:163: Define or directive not defined: \'`MEM_COUNT_HALF\'\n        `MEM_COUNT_HALF: begin\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:173: Define or directive not defined: \'`MEM_COUNT_WORD\'\n        `MEM_COUNT_WORD: \n        ^~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:190: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Error: data/full_repos/permissive/109936328/tb/tb_memory_interface.v:203: syntax error, unexpected always\n  always begin\n  ^~~~~~\n%Error: Exiting due to 31 error(s), 5 warning(s)\n'
module tb_memory_interface;

  localparam CLK_PERIOD = 2;
  localparam RESET_DURATION = 5;

  localparam WORD_COUNT = 128;
  localparam TEST_DATA_SIZE = 64;
  

  reg clk;
  reg aresetn;



  reg [`ADDR_W - 1:0] req_addr;

  reg [`WORD_W - 1:0] req_wr_data;

  reg [`MEM_COUNT_W - 1:0] req_count;

  reg req_wr_en;


  wire [`WORD_W - 1:0] rd_data;

  wire [`MEM_CODE_W - 1:0] res_code;


  reg [`ADDR_W - 1:0] test_addr [0:TEST_DATA_SIZE - 1];

  reg [`MEM_COUNT_W - 1:0] test_count [0:TEST_DATA_SIZE - 1];

  reg [`WORD_W - 1:0] test_data [0:TEST_DATA_SIZE - 1];


  integer test_num;

  integer i;
  

  memory_interface#(
    .WORD_COUNT(WORD_COUNT)
  ) dut(
    .clk(clk),
    .aresetn(aresetn),

    .i_req_addr(req_addr),
    .i_req_wr_data(req_wr_data),
    .i_req_count(req_count),
    .i_req_wr_en(req_wr_en),

    .o_res_rd_data(rd_data),
    .o_res_code(res_code)
  );

  initial begin

    $dumpfile("tb_memory_interface.vcd");
    $dumpvars;


    clk = 0;
    aresetn = 0;

    req_addr = 0;
    req_wr_data = 0;
    req_count = `MEM_COUNT_NONE;
    req_wr_en = 0;


    for(i = 0; i < TEST_DATA_SIZE; i = i + 1) begin

      test_count[i] = $urandom % 3 + 1;

      test_addr[i] = i << 2;
      test_data[i] = $urandom;
      

      case(test_count[i])
        `MEM_COUNT_BYTE: begin

          test_addr[i][1:0] = $urandom % 4;
          test_data[i][31:8] = 0;
        end

        `MEM_COUNT_HALF: begin

          test_addr[i][0] = 0;
          test_addr[i][1] = $urandom % 2;
          test_data[i][31:16] = 0;
        end
      endcase
    end


    #(RESET_DURATION * CLK_PERIOD);


    aresetn = 1;

    #(CLK_PERIOD);




    test_num = 1;
    $display("[%0d] Testing misalignment!", test_num);

    req_wr_en = 1;
    req_wr_data = 32'hdeadbeef;
    req_count = `MEM_COUNT_WORD;

    req_addr = 32'h1;

    #(CLK_PERIOD);

    `ASSERT(res_code == `MEM_CODE_MISALIGNED)




    test_num = test_num + 1;
    $display("[%0d] Testing write!", test_num);

    req_wr_en = 1;
    for(i = 0; i < TEST_DATA_SIZE; i = i + 1) begin

      req_addr = test_addr[i];
      req_count = test_count[i];
      req_wr_data = test_data[i];

      #(CLK_PERIOD);


      `ASSERT(rd_data == 0)

      `ASSERT(res_code == `MEM_CODE_WRITE)


      case(req_count)
        `MEM_COUNT_BYTE: begin
        
          case(req_addr[1:0])
            0: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][7:0] == req_wr_data[7:0])
            1: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][15:8] == req_wr_data[7:0])
            2: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][23:16] == req_wr_data[7:0])
            3: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][31:24] == req_wr_data[7:0])
          endcase
        
        end

        `MEM_COUNT_HALF: begin

          case(req_addr[1])
            0: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][15:0] == req_wr_data[15:0])
            1: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][31:16] == req_wr_data[15:0])
          endcase
        
        end
        
          
        `MEM_COUNT_WORD: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]] == req_wr_data)
      endcase
    end

    req_wr_en = 0;
    



    test_num = test_num + 1;
    $display("[%0d] Testing read!", test_num);

    for(i = 0; i < TEST_DATA_SIZE; i = i + 1) begin

      req_addr = test_addr[i];
      req_count = test_count[i];

      #(CLK_PERIOD);
      

      `ASSERT(rd_data == test_data[i])

      `ASSERT(res_code == `MEM_CODE_READ)
    end

    $display("All assertions passed!");
    $finish;
  end


  always begin
    #(CLK_PERIOD / 2);
    clk = ~clk;
  end


endmodule
module tb_memory_interface;


  localparam CLK_PERIOD = 2;
  localparam RESET_DURATION = 5;

  localparam WORD_COUNT = 128;
  localparam TEST_DATA_SIZE = 64;
  

  reg clk;
  reg aresetn;



  reg [`ADDR_W - 1:0] req_addr;

  reg [`WORD_W - 1:0] req_wr_data;

  reg [`MEM_COUNT_W - 1:0] req_count;

  reg req_wr_en;


  wire [`WORD_W - 1:0] rd_data;

  wire [`MEM_CODE_W - 1:0] res_code;


  reg [`ADDR_W - 1:0] test_addr [0:TEST_DATA_SIZE - 1];

  reg [`MEM_COUNT_W - 1:0] test_count [0:TEST_DATA_SIZE - 1];

  reg [`WORD_W - 1:0] test_data [0:TEST_DATA_SIZE - 1];


  integer test_num;

  integer i;
  

  memory_interface#(
    .WORD_COUNT(WORD_COUNT)
  ) dut(
    .clk(clk),
    .aresetn(aresetn),

    .i_req_addr(req_addr),
    .i_req_wr_data(req_wr_data),
    .i_req_count(req_count),
    .i_req_wr_en(req_wr_en),

    .o_res_rd_data(rd_data),
    .o_res_code(res_code)
  );

  initial begin

    $dumpfile("tb_memory_interface.vcd");
    $dumpvars;


    clk = 0;
    aresetn = 0;

    req_addr = 0;
    req_wr_data = 0;
    req_count = `MEM_COUNT_NONE;
    req_wr_en = 0;


    for(i = 0; i < TEST_DATA_SIZE; i = i + 1) begin

      test_count[i] = $urandom % 3 + 1;

      test_addr[i] = i << 2;
      test_data[i] = $urandom;
      

      case(test_count[i])
        `MEM_COUNT_BYTE: begin

          test_addr[i][1:0] = $urandom % 4;
          test_data[i][31:8] = 0;
        end

        `MEM_COUNT_HALF: begin

          test_addr[i][0] = 0;
          test_addr[i][1] = $urandom % 2;
          test_data[i][31:16] = 0;
        end
      endcase
    end


    #(RESET_DURATION * CLK_PERIOD);


    aresetn = 1;

    #(CLK_PERIOD);




    test_num = 1;
    $display("[%0d] Testing misalignment!", test_num);

    req_wr_en = 1;
    req_wr_data = 32'hdeadbeef;
    req_count = `MEM_COUNT_WORD;

    req_addr = 32'h1;

    #(CLK_PERIOD);

    `ASSERT(res_code == `MEM_CODE_MISALIGNED)




    test_num = test_num + 1;
    $display("[%0d] Testing write!", test_num);

    req_wr_en = 1;
    for(i = 0; i < TEST_DATA_SIZE; i = i + 1) begin

      req_addr = test_addr[i];
      req_count = test_count[i];
      req_wr_data = test_data[i];

      #(CLK_PERIOD);


      `ASSERT(rd_data == 0)

      `ASSERT(res_code == `MEM_CODE_WRITE)


      case(req_count)
        `MEM_COUNT_BYTE: begin
        
          case(req_addr[1:0])
            0: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][7:0] == req_wr_data[7:0])
            1: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][15:8] == req_wr_data[7:0])
            2: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][23:16] == req_wr_data[7:0])
            3: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][31:24] == req_wr_data[7:0])
          endcase
        
        end

        `MEM_COUNT_HALF: begin

          case(req_addr[1])
            0: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][15:0] == req_wr_data[15:0])
            1: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]][31:16] == req_wr_data[15:0])
          endcase
        
        end
        
          
        `MEM_COUNT_WORD: `ASSERT(dut.r_mem[req_addr[`ADDR_W - 1:2]] == req_wr_data)
      endcase
    end

    req_wr_en = 0;
    



    test_num = test_num + 1;
    $display("[%0d] Testing read!", test_num);

    for(i = 0; i < TEST_DATA_SIZE; i = i + 1) begin

      req_addr = test_addr[i];
      req_count = test_count[i];

      #(CLK_PERIOD);
      

      `ASSERT(rd_data == test_data[i])

      `ASSERT(res_code == `MEM_CODE_READ)
    end

    $display("All assertions passed!");
    $finish;
  end


  always begin
    #(CLK_PERIOD / 2);
    clk = ~clk;
  end


endmodule