data/full_repos/permissive/143278/ivltests/pr3571573.v
 line:8: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3571573.v:8: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b", top_io);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module data_test(inout [6:1] io);

wire [4:1] io1;
wire       io2;
wire       io3;

assign io = {io3, io2, io1};

assign io1[3:2] = 2'b01;

endmodule
module data_test(inout [6:1] io);


wire [4:1] io1;
wire       io2;
wire       io3;

assign io = {io3, io2, io1};

assign io1[3:2] = 2'b01;

endmodule