data/full_repos/permissive/167263918/pll/top.v
 line:53: before: ")"
1: b"%Error: data/full_repos/permissive/167263918/pll/top.v:17: Cannot find file containing module: 'SB_HFOSC'\n   SB_HFOSC SB_HFOSC_inst(\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167263918/pll,data/full_repos/permissive/167263918/SB_HFOSC\n             data/full_repos/permissive/167263918/pll,data/full_repos/permissive/167263918/SB_HFOSC.v\n             data/full_repos/permissive/167263918/pll,data/full_repos/permissive/167263918/SB_HFOSC.sv\n             SB_HFOSC\n             SB_HFOSC.v\n             SB_HFOSC.sv\n             obj_dir/SB_HFOSC\n             obj_dir/SB_HFOSC.v\n             obj_dir/SB_HFOSC.sv\n%Error: data/full_repos/permissive/167263918/pll/top.v:24: Cannot find file containing module: 'SB_LFOSC'\n   SB_LFOSC SB_LFOSC_inst(\n   ^~~~~~~~\n%Error: data/full_repos/permissive/167263918/pll/top.v:46: Cannot find file containing module: 'SB_PLL40_CORE'\n   SB_PLL40_CORE #(\n   ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top(input [3:0] SW,output LED_R, output LED_G, output LED_B);
   wire clk_48mhz;
   wire clk_10khz;
   wire clk_24mhz;

   reg [2:0] led;
   reg [24:0] counter_slow;
   reg [24:0] counter_fast;


   assign LED_R = ~led[0];
   assign LED_G = ~led[1];
   assign LED_B = ~led[2];


   SB_HFOSC SB_HFOSC_inst(
      .CLKHFEN(1),
      .CLKHFPU(1),
      .CLKHF(clk_48mhz)
   );


   SB_LFOSC SB_LFOSC_inst(
      .CLKLFEN(1),
      .CLKLFPU(1),
      .CLKLF(clk_10khz)
   );

















   SB_PLL40_CORE #(
      .FEEDBACK_PATH("SIMPLE"),
      .PLLOUT_SELECT("GENCLK"),
      .DIVR(4'b0000),
      .DIVF(7'b0001111),
      .DIVQ(3'b101),
      .FILTER_RANGE(3'b100),
    ) SB_PLL40_CORE_inst (
      .RESETB(1'b1),
      .BYPASS(1'b0),
      .PLLOUTCORE(clk_24mhz),
      .REFERENCECLK(clk_48mhz)
   );

   initial begin
      led = 0;
      counter_slow = 0;
      counter_fast = 0;
   end

   always @(posedge clk_24mhz)
   begin
      counter_slow <= counter_slow + 1;
      if (counter_slow == 24*1024*1024) begin
         led[0] <= ~led[0];
         counter_slow <= 0;
      end
   end

   always @(posedge clk_48mhz)
   begin
      counter_fast <= counter_fast + 1;
      if (counter_fast == 24*1024*1024) begin
         led[1] <= ~led[1];
         counter_fast <= 0;
      end
   end

endmodule
module top(input [3:0] SW,output LED_R, output LED_G, output LED_B);

   wire clk_48mhz;
   wire clk_10khz;
   wire clk_24mhz;

   reg [2:0] led;
   reg [24:0] counter_slow;
   reg [24:0] counter_fast;


   assign LED_R = ~led[0];
   assign LED_G = ~led[1];
   assign LED_B = ~led[2];


   SB_HFOSC SB_HFOSC_inst(
      .CLKHFEN(1),
      .CLKHFPU(1),
      .CLKHF(clk_48mhz)
   );


   SB_LFOSC SB_LFOSC_inst(
      .CLKLFEN(1),
      .CLKLFPU(1),
      .CLKLF(clk_10khz)
   );

















   SB_PLL40_CORE #(
      .FEEDBACK_PATH("SIMPLE"),
      .PLLOUT_SELECT("GENCLK"),
      .DIVR(4'b0000),
      .DIVF(7'b0001111),
      .DIVQ(3'b101),
      .FILTER_RANGE(3'b100),
    ) SB_PLL40_CORE_inst (
      .RESETB(1'b1),
      .BYPASS(1'b0),
      .PLLOUTCORE(clk_24mhz),
      .REFERENCECLK(clk_48mhz)
   );

   initial begin
      led = 0;
      counter_slow = 0;
      counter_fast = 0;
   end

   always @(posedge clk_24mhz)
   begin
      counter_slow <= counter_slow + 1;
      if (counter_slow == 24*1024*1024) begin
         led[0] <= ~led[0];
         counter_slow <= 0;
      end
   end

   always @(posedge clk_48mhz)
   begin
      counter_fast <= counter_fast + 1;
      if (counter_fast == 24*1024*1024) begin
         led[1] <= ~led[1];
         counter_fast <= 0;
      end
   end

endmodule