data/full_repos/permissive/184916587/Test_CPU.v
 line:17: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_CPU.v:13: Unsupported: Ignoring delay on this delayed statement.\n   #0 Reset=1;PCWre=0;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_CPU.v:14: Unsupported: Ignoring delay on this delayed statement.\n   #5 Reset=0;PCWre=1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_CPU.v:15: Unsupported: Ignoring delay on this delayed statement.\n   #0 Reset=0;PCWre=0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_CPU.v:16: Unsupported: Ignoring delay on this delayed statement.\n   #5 Reset=0;PCWre=1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/184916587/Test_CPU.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #5 $finish;\n   ^\n%Error: data/full_repos/permissive/184916587/Test_CPU.v:22: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("CPU.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/184916587/Test_CPU.v:23: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0,Test_CPU);\n   ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_CPU;
	reg PCWre;
	reg Reset;

	CPU test_cpu(
		.PCWre(PCWre),
		.Reset(Reset)
	);

	initial
		begin
			#0 Reset=1;PCWre=0;
			#5 Reset=0;PCWre=1;
			#0 Reset=0;PCWre=0;
			#5 Reset=0;PCWre=1;
			#5 $finish;
		end

	initial
		begin
			$dumpfile("CPU.vcd");
			$dumpvars(0,Test_CPU);
		end
endmodule
module Test_CPU;

	reg PCWre;
	reg Reset;

	CPU test_cpu(
		.PCWre(PCWre),
		.Reset(Reset)
	);

	initial
		begin
			#0 Reset=1;PCWre=0;
			#5 Reset=0;PCWre=1;
			#0 Reset=0;PCWre=0;
			#5 Reset=0;PCWre=1;
			#5 $finish;
		end

	initial
		begin
			$dumpfile("CPU.vcd");
			$dumpvars(0,Test_CPU);
		end
endmodule