data/full_repos/permissive/135008983/code/bcd7seg.v
data/verilator_xmls/98c8f61e-8139-417b-967f-3d768d8c48fa.xml
module bcd7seg (oSEG, LatchBCD); 
output reg [6:0]        oSEG;
input      [3:0]    LatchBCD;
always @ (LatchBCD) 
begin
	case (LatchBCD)
		4'h0: oSEG = 7'b1000000;
		4'h1: oSEG = 7'b1111001;
		4'h2: oSEG = 7'b0100100;
		4'h3: oSEG = 7'b0110000;
		4'h4: oSEG = 7'b0011001;
		4'h5: oSEG = 7'b0010010;
		4'h6: oSEG = 7'b0000010;
		4'h7: oSEG = 7'b1111000;
		4'h8: oSEG = 7'b0000000;
		4'h9: oSEG = 7'b0010000;
		4'hf: oSEG = 7'b0001110;
		default: oSEG = 7'b1111111;
	endcase 
end

endmodule
module bcd7seg (oSEG, LatchBCD);
 
output reg [6:0]        oSEG;
input      [3:0]    LatchBCD;
always @ (LatchBCD) 
begin
	case (LatchBCD)
		4'h0: oSEG = 7'b1000000;
		4'h1: oSEG = 7'b1111001;
		4'h2: oSEG = 7'b0100100;
		4'h3: oSEG = 7'b0110000;
		4'h4: oSEG = 7'b0011001;
		4'h5: oSEG = 7'b0010010;
		4'h6: oSEG = 7'b0000010;
		4'h7: oSEG = 7'b1111000;
		4'h8: oSEG = 7'b0000000;
		4'h9: oSEG = 7'b0010000;
		4'hf: oSEG = 7'b0001110;
		default: oSEG = 7'b1111111;
	endcase 
end

endmodule