data/full_repos/permissive/163025478/cpu.v
 line:47: before: "."
1: b'%Warning-WIDTH: data/full_repos/permissive/163025478/cpu.v:59: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s REDOR generates 1 bits.\n                                                             : ... In instance cpu\n                  (addr_w == TST) ? |data  : \n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module cpu(clk, reset, port);
  parameter WIDTH = 8;
  parameter RAM_SIZE = 8;
  parameter ROM_SIZE = 8;

  parameter PC  = 0;
  parameter CG  = 1;
  parameter TST = 2;
  parameter ADD = 3;
  parameter SUB = 4;
  parameter PORT = 5;
  
  input clk, reset;
  output [WIDTH-1 : 0] port;

  wire [WIDTH-1 : 0] addr_r, addr_w, data_r, data_w, data;
  
  reg [WIDTH-1 : 0] reg_pc;
  reg [WIDTH-1 : 0] reg_reg;
  reg [WIDTH-1 : 0] reg_port;
  assign port = reg_port;

  rom1r rom(reg_pc, {addr_w, addr_r});
  defparam rom.ADDR_WIDTH = ROM_SIZE;
  defparam rom.DATA_WIDTH = RAM_SIZE * 2;

  ram1r1w ram (clk, addr_w, data_w, addr_r, data_r);
  defparam ram.ADDR_WIDTH = RAM_SIZE;
  defparam ram.DATA_WIDTH = WIDTH;

  assign data   = (addr_r == PC)   ? reg_pc + 1 : 
                  (addr_r == PORT) ? reg_port : 
                   data_r;

  assign data_w = (addr_w == CG)  ? addr_r : 
                  (addr_w == TST) ? |data  : 
                  (addr_w == ADD) ? data + reg_reg : 
                  (addr_w == SUB) ? data - reg_reg : 
                   data;

  always @ (posedge clk) begin
    if (reset) begin
      reg_pc <= 0;
    end else begin
      reg_reg <= data_w;
      if (addr_w == PC) begin
        reg_pc <= data_w; 
      end else begin
        reg_pc <= reg_pc  + (((addr_w == TST) & data_w[0]) ? 2 : 1);
        case (addr_w)
          PORT: reg_port <= data_w;
        endcase
      end
    end
  end
endmodule
module cpu(clk, reset, port);

  parameter WIDTH = 8;
  parameter RAM_SIZE = 8;
  parameter ROM_SIZE = 8;

  parameter PC  = 0;
  parameter CG  = 1;
  parameter TST = 2;
  parameter ADD = 3;
  parameter SUB = 4;
  parameter PORT = 5;
  
  input clk, reset;
  output [WIDTH-1 : 0] port;

  wire [WIDTH-1 : 0] addr_r, addr_w, data_r, data_w, data;
  
  reg [WIDTH-1 : 0] reg_pc;
  reg [WIDTH-1 : 0] reg_reg;
  reg [WIDTH-1 : 0] reg_port;
  assign port = reg_port;

  rom1r rom(reg_pc, {addr_w, addr_r});
  defparam rom.ADDR_WIDTH = ROM_SIZE;
  defparam rom.DATA_WIDTH = RAM_SIZE * 2;

  ram1r1w ram (clk, addr_w, data_w, addr_r, data_r);
  defparam ram.ADDR_WIDTH = RAM_SIZE;
  defparam ram.DATA_WIDTH = WIDTH;

  assign data   = (addr_r == PC)   ? reg_pc + 1 : 
                  (addr_r == PORT) ? reg_port : 
                   data_r;

  assign data_w = (addr_w == CG)  ? addr_r : 
                  (addr_w == TST) ? |data  : 
                  (addr_w == ADD) ? data + reg_reg : 
                  (addr_w == SUB) ? data - reg_reg : 
                   data;

  always @ (posedge clk) begin
    if (reset) begin
      reg_pc <= 0;
    end else begin
      reg_reg <= data_w;
      if (addr_w == PC) begin
        reg_pc <= data_w; 
      end else begin
        reg_pc <= reg_pc  + (((addr_w == TST) & data_w[0]) ? 2 : 1);
        case (addr_w)
          PORT: reg_port <= data_w;
        endcase
      end
    end
  end
endmodule