data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k_tb.v
 line:46: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clock <= ~clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k_tb.v:21: Unsupported or unknown PLI call: $dumpfile\n $dumpfile ("tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k_tb.v:22: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #10 write = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #220\n ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/fifo/sync/sfifo2k_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sfifo2k_tb;

reg	clock	= 1;
reg	reset_n	= 1;
reg	read	= 0;
reg	write	= 0;

reg	[17:0]	wr_data	= 0;
wire	[17:0]	rd_data;

wire	full;
wire	empty;

always	#5 clock	<= ~clock;


integer	ii;
initial begin : Sim
	$write ("%% ");
	$dumpfile ("tb.vcd");
	$dumpvars;
	
	
	#2
	reset_n	= 0;
	
	#10
	reset_n	= 1;
	
	for (ii=0; ii<20; ii=ii+1) begin
		#10 write	= 1;
		wr_data		= ii;
	end
	
	#10
	read	= 1;
	write	= 0;
	wr_data	= ii;
	
	#220
	read	= 0;
	write	= 0;
	
	#30
	$finish;
end



sfifo2k #(
	.WIDTH	(18),
	.SIZE	(16),
	.PWIDTH	(4)
) FIFO0 (
	.clock_i	(clock),
	.reset_ni	(reset_n),
	.read_i		(read),
	.write_i	(write),
	.data_i		(wr_data),
	.data_o		(rd_data),
	
	.empty_o	(empty),
	.full_o		(full)
);


endmodule
module sfifo2k_tb;


reg	clock	= 1;
reg	reset_n	= 1;
reg	read	= 0;
reg	write	= 0;

reg	[17:0]	wr_data	= 0;
wire	[17:0]	rd_data;

wire	full;
wire	empty;

always	#5 clock	<= ~clock;


integer	ii;
initial begin : Sim
	$write ("%% ");
	$dumpfile ("tb.vcd");
	$dumpvars;
	
	
	#2
	reset_n	= 0;
	
	#10
	reset_n	= 1;
	
	for (ii=0; ii<20; ii=ii+1) begin
		#10 write	= 1;
		wr_data		= ii;
	end
	
	#10
	read	= 1;
	write	= 0;
	wr_data	= ii;
	
	#220
	read	= 0;
	write	= 0;
	
	#30
	$finish;
end



sfifo2k #(
	.WIDTH	(18),
	.SIZE	(16),
	.PWIDTH	(4)
) FIFO0 (
	.clock_i	(clock),
	.reset_ni	(reset_n),
	.read_i		(read),
	.write_i	(write),
	.data_i		(wr_data),
	.data_o		(rd_data),
	
	.empty_o	(empty),
	.full_o		(full)
);


endmodule