data/full_repos/permissive/143278/ivltests/pr2038048.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2038048.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #2 Index = i;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2038048.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #2 if (pass) $display("PASSED");\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2038048.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1 if (Value !== Index % 8) begin\n  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2038048.v:20: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                         : ... In instance array_word_part_select\n    Data[i] = i;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2038048.v:23: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                         : ... In instance array_word_part_select\n    #2 Index = i;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2038048.v:30: Operator NEQCASE expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'Value\' generates 3 bits.\n                                                                         : ... In instance array_word_part_select\n  #1 if (Value !== Index % 8) begin\n               ^~~\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module array_word_part_select();
reg pass = 1'b1;

reg  [3:0]	Data[15:0];

reg  [3:0]	Index;

wire [2:0]	Value;


assign Value = Data[Index][2:0];

integer		i;

initial begin
  for (i = 0; i < 16; i = i + 1) begin
    Data[i] = i;
  end
  for (i = 0; i < 16; i = i + 1) begin
    #2 Index = i;
  end
  #2 if (pass) $display("PASSED");
end

always @(Index) begin

  #1 if (Value !== Index % 8) begin
    $display("Failed: testing index %d, expected %d, got %d", Index,
             Index % 8, Value);
    pass = 1'b0;
  end
end

endmodule
module array_word_part_select();

reg pass = 1'b1;

reg  [3:0]	Data[15:0];

reg  [3:0]	Index;

wire [2:0]	Value;


assign Value = Data[Index][2:0];

integer		i;

initial begin
  for (i = 0; i < 16; i = i + 1) begin
    Data[i] = i;
  end
  for (i = 0; i < 16; i = i + 1) begin
    #2 Index = i;
  end
  #2 if (pass) $display("PASSED");
end

always @(Index) begin

  #1 if (Value !== Index % 8) begin
    $display("Failed: testing index %d, expected %d, got %d", Index,
             Index % 8, Value);
    pass = 1'b0;
  end
end

endmodule