data/full_repos/permissive/143278/blif/blif01f.v
data/verilator_xmls/1171aa98-81e1-4982-985f-b847fc978a2d.xml
module muxN
  #(parameter WID = 4, parameter SWID = 2)
   (input wire [WID-1:0]  D,
    input wire [SWID-1:0] S,
    output wire		  Q
);

   assign Q = D[S];

endmodule
module muxN
  #(parameter WID = 4, parameter SWID = 2)
   (input wire [WID-1:0]  D,
    input wire [SWID-1:0] S,
    output wire		  Q
);


   assign Q = D[S];

endmodule