data/full_repos/permissive/160895047/Memory_Test.v
 line:47: before: "$"
1: b'%Error: data/full_repos/permissive/160895047/Memory_Test.v:1: Cannot find include file: Memory.v\n`include "Memory.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160895047,data/full_repos/permissive/160895047/Memory.v\n             data/full_repos/permissive/160895047,data/full_repos/permissive/160895047/Memory.v.v\n             data/full_repos/permissive/160895047,data/full_repos/permissive/160895047/Memory.v.sv\n             Memory.v\n             Memory.v.v\n             Memory.v.sv\n             obj_dir/Memory.v\n             obj_dir/Memory.v.v\n             obj_dir/Memory.v.sv\n%Error: data/full_repos/permissive/160895047/Memory_Test.v:13: Unsupported or unknown PLI call: $monitor\n $monitor("%g\\t%g\\t%g\\t%g\\t%g", $time, A, D, WE, WD);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/160895047/Memory_Test.v:19: Unsupported: Ignoring delay on this delayed statement.\n #256 WE = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160895047/Memory_Test.v:20: Unsupported: Ignoring delay on this delayed statement.\n #256 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/160895047/Memory_Test.v:25: Unsupported: Ignoring delay on this delayed statement.\n #1 clock <= ~clock;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module Memory_Test();
reg [31:0] A;
reg [7:0] TA;
wire [31:0] D;
reg [31:0] WD;
reg WE;

reg clock;
initial 
begin
	$display("time\tA\tD\tWE\tWD");
	$monitor("%g\t%g\t%g\t%g\t%g", $time, A, D, WE, WD);

	clock = 0;
	TA = 0;
	WD = 0;
	WE = 1;
	#256 WE = 0;
	#256 $finish;
end

always
begin
	#1 clock <= ~clock;
	TA = TA + 1;
	A = TA;
	WD = WD + 5;
end

Memory U0 (
	clock,
	A,
	D,
	WE,
	WD
);
endmodule
module Memory_Test();

reg [31:0] A;
reg [7:0] TA;
wire [31:0] D;
reg [31:0] WD;
reg WE;

reg clock;
initial 
begin
	$display("time\tA\tD\tWE\tWD");
	$monitor("%g\t%g\t%g\t%g\t%g", $time, A, D, WE, WD);

	clock = 0;
	TA = 0;
	WD = 0;
	WE = 1;
	#256 WE = 0;
	#256 $finish;
end

always
begin
	#1 clock <= ~clock;
	TA = TA + 1;
	A = TA;
	WD = WD + 5;
end

Memory U0 (
	clock,
	A,
	D,
	WE,
	WD
);
endmodule