data/full_repos/permissive/193753641/full_adder.v
data/verilator_xmls/88ffeb3b-ba39-4a62-94c7-ba0c9a6131d2.xml
module full_adder(a,b,cin,s,cout);

input a,b,cin;
output s,cout;
wire z1,z2,z3;
xor(z1,a,b);
xor(s,z1,cin);
and(z2,z1,cin);
and(z3,a,b);
or(cout,z2,z3);

endmodule
module full_adder(a,b,cin,s,cout);


input a,b,cin;
output s,cout;
wire z1,z2,z3;
xor(z1,a,b);
xor(s,z1,cin);
and(z2,z1,cin);
and(z3,a,b);
or(cout,z2,z3);

endmodule