data/full_repos/permissive/209534045/src/wsg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/209534045/src/wsg.v:197: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'waveout\' generates 8 bits.\n                                                                  : ... In instance WSG_3CH.core\n            sndmix  <= sndmix + waveout;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/209534045/src/wsg.v:204: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'waveout\' generates 8 bits.\n                                                                  : ... In instance WSG_3CH.core\n            sndmix  <= sndmix + waveout;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/209534045/src/wsg.v:212: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'waveout\' generates 8 bits.\n                                                                  : ... In instance WSG_3CH.core\n            sndmix  <= sndmix + waveout;\n                              ^\n%Error: Exiting due to 3 warning(s)\n'
module WSGCLKGEN( input in, output reg out );
reg [7:0] count;
always @( posedge in ) begin
	if (count > 8'd249) begin
		count <= count - 8'd249;
      out <= ~out;
	end
   else count <= count + 8'd1;
end
endmodule
module WSGCLKGEN( input in, output reg out );

reg [7:0] count;
always @( posedge in ) begin
	if (count > 8'd249) begin
		count <= count - 8'd249;
      out <= ~out;
	end
   else count <= count + 8'd1;
end
endmodule