data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/dac_gen_TF.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/dac_gen_TF.v:46: Unsupported: Ignoring delay on this delayed statement.\nalways #2 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/dac_gen_TF.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/dac_gen_TF.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/dac_gen_TF.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/dac_gen_TF.v:38: Cannot find file containing module: \'DAC_TEST\'\n DAC_TEST uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/DAC_TEST\n             data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/DAC_TEST.v\n             data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller,data/full_repos/permissive/116048589/DAC_TEST.sv\n             DAC_TEST\n             DAC_TEST.v\n             DAC_TEST.sv\n             obj_dir/DAC_TEST\n             obj_dir/DAC_TEST.v\n             obj_dir/DAC_TEST.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dac_gen_TF;


	reg clk;
	reg count_test;
	reg reset;


	wire [31:0] toSPI;
	wire toEnable;
	wire toReset;


	DAC_TEST uut (
		.clk(clk), 

		.reset(reset), 
		.toSPI(toSPI), 
		.toEnable(toEnable), 
		.toReset(toReset)
	);
always #2 clk = ~clk;
	initial begin

		clk = 0;
		count_test = 0;
		reset = 0;
		#10;
		reset = 1;
		#10;
		reset = 0;

		#100;
        


	end
      
endmodule
module dac_gen_TF;



	reg clk;
	reg count_test;
	reg reset;


	wire [31:0] toSPI;
	wire toEnable;
	wire toReset;


	DAC_TEST uut (
		.clk(clk), 

		.reset(reset), 
		.toSPI(toSPI), 
		.toEnable(toEnable), 
		.toReset(toReset)
	);
always #2 clk = ~clk;
	initial begin

		clk = 0;
		count_test = 0;
		reset = 0;
		#10;
		reset = 1;
		#10;
		reset = 0;

		#100;
        


	end
      
endmodule