data/full_repos/permissive/167856740/cpu/tb/control_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:1: Cannot find include file: control_defintions.vh\n`include "control_defintions.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/control_defintions.vh\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/control_defintions.vh.v\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/control_defintions.vh.sv\n             control_defintions.vh\n             control_defintions.vh.v\n             control_defintions.vh.sv\n             obj_dir/control_defintions.vh\n             obj_dir/control_defintions.vh.v\n             obj_dir/control_defintions.vh.sv\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:47: Define or directive not defined: \'`CONTROL_IN_LUI\'\n        {control,breq,brlt} = `CONTROL_IN_LUI;\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:47: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        {control,breq,brlt} = `CONTROL_IN_LUI;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("LUI:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:49: Define or directive not defined: \'`CONTROL_IN_AUIPC\'\n        #10 {control,breq,brlt} = `CONTROL_IN_AUIPC;\n                                  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:49: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_AUIPC;\n                                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_AUIPC;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("AUIPC:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:55: Define or directive not defined: \'`CONTROL_IN_JAL\'\n        #10 {control,breq,brlt} = `CONTROL_IN_JAL;\n                                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:55: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_JAL;\n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_JAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("JAL:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:57: Define or directive not defined: \'`CONTROL_IN_JALR\'\n        #10 {control,breq,brlt} = `CONTROL_IN_JALR; \n                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:57: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_JALR; \n                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_JALR; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("JALR:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:62: Define or directive not defined: \'`CONTROL_IN_BEQ_TRUE\'\n        #10 {control,breq,brlt} = `CONTROL_IN_BEQ_TRUE;  \n                                  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_BEQ_TRUE;  \n                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_BEQ_TRUE;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("BEQ:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:64: Define or directive not defined: \'`CONTROL_IN_BNE_TRUE\'\n        #10 {control,breq,brlt} = `CONTROL_IN_BNE_TRUE; \n                                  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:64: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_BNE_TRUE; \n                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_BNE_TRUE; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("BNE:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:66: Define or directive not defined: \'`CONTROL_IN_BLT_TRUE\'\n        #10 {control,breq,brlt} = `CONTROL_IN_BLT_TRUE;  \n                                  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_BLT_TRUE;  \n                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_BLT_TRUE;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("BLT:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:68: Define or directive not defined: \'`CONTROL_IN_BGE_TRUE\'\n        #10 {control,breq,brlt} = `CONTROL_IN_BGE_TRUE;  \n                                  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:68: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_BGE_TRUE;  \n                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_BGE_TRUE;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("BGE:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:70: Define or directive not defined: \'`CONTROL_IN_BLTU_TRUE\'\n        #10 {control,breq,brlt} = `CONTROL_IN_BLTU_TRUE; \n                                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:70: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_BLTU_TRUE; \n                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_BLTU_TRUE; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("BLTU:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:72: Define or directive not defined: \'`CONTROL_IN_BGEU_TRUE\'\n        #10 {control,breq,brlt} = `CONTROL_IN_BGEU_TRUE; \n                                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:72: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_BGEU_TRUE; \n                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_BGEU_TRUE; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("BGEU:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:77: Define or directive not defined: \'`CONTROL_IN_BEQ_FALSE\'\n        #10 {control,breq,brlt} = `CONTROL_IN_BEQ_FALSE;  \n                                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:77: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_BEQ_FALSE;  \n                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_BEQ_FALSE;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("BEQ:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:79: Define or directive not defined: \'`CONTROL_IN_BNE_FALSE\'\n        #10 {control,breq,brlt} = `CONTROL_IN_BNE_FALSE; \n                                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_BNE_FALSE; \n                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_BNE_FALSE; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("BNE:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:81: Define or directive not defined: \'`CONTROL_IN_BLT_FALSE\'\n        #10 {control,breq,brlt} = `CONTROL_IN_BLT_FALSE;  \n                                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_BLT_FALSE;  \n                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_BLT_FALSE;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("BLT:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:83: Define or directive not defined: \'`CONTROL_IN_BGE_FALSE\'\n        #10 {control,breq,brlt} = `CONTROL_IN_BGE_FALSE;  \n                                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_BGE_FALSE;  \n                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_BGE_FALSE;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("BGE:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:85: Define or directive not defined: \'`CONTROL_IN_BLTU_FALSE\'\n        #10 {control,breq,brlt} = `CONTROL_IN_BLTU_FALSE; \n                                  ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:85: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_BLTU_FALSE; \n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_BLTU_FALSE; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("BLTU:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:87: Define or directive not defined: \'`CONTROL_IN_BGEU_FALSE\'\n        #10 {control,breq,brlt} = `CONTROL_IN_BGEU_FALSE; \n                                  ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:87: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_BGEU_FALSE; \n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_BGEU_FALSE; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("BGEU:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:92: Define or directive not defined: \'`CONTROL_IN_LB\'\n        #10 {control,breq,brlt} = `CONTROL_IN_LB; \n                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:92: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_LB; \n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_LB; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("LB:\\t\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:94: Define or directive not defined: \'`CONTROL_IN_LH\'\n        #10 {control,breq,brlt} = `CONTROL_IN_LH; \n                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:94: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_LH; \n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_LH; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("LH:\\t\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:96: Define or directive not defined: \'`CONTROL_IN_LW\'\n        #10 {control,breq,brlt} = `CONTROL_IN_LW; \n                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_LW; \n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_LW; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("LW:\\t\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:98: Define or directive not defined: \'`CONTROL_IN_LBU\'\n        #10 {control,breq,brlt} = `CONTROL_IN_LBU; \n                                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:98: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_LBU; \n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_LBU; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("LBU:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:100: Define or directive not defined: \'`CONTROL_IN_LHU\'\n        #10 {control,breq,brlt} = `CONTROL_IN_LHU;\n                                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_LHU;\n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_LHU;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("LHU:\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:105: Define or directive not defined: \'`CONTROL_IN_SB\'\n        #10 {control,breq,brlt} = `CONTROL_IN_SB; \n                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_SB; \n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_SB; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("SB:\\t\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:107: Define or directive not defined: \'`CONTROL_IN_SH\'\n        #10 {control,breq,brlt} = `CONTROL_IN_SH;   \n                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:107: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_SH;   \n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_SH;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("SH:\\t\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:109: Define or directive not defined: \'`CONTROL_IN_SW\'\n        #10 {control,breq,brlt} = `CONTROL_IN_SW;  \n                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:109: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #10 {control,breq,brlt} = `CONTROL_IN_SW;  \n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #10 {control,breq,brlt} = `CONTROL_IN_SW;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #10 $display("SW:\\t\\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});\n        ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/control_tb.v:114: Define or directive not defined: \'`CONTROL_IN_ADDI\'\n        #10 {control,breq,brlt} = `CONTROL_IN_ADDI;\n                                  ^~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module control_tb;
	

    reg [9:0] control;
    reg breq;
    reg brlt;
    
    wire pcsel;
    wire [2:0] immsel;
    wire regwen;
    wire brun;
    wire asel;
    wire bsel;
    wire [3:0] alusel;
    wire memrw;
    wire [2:0] loadsel;
    wire [1:0] storesel;
    wire [1:0] wbsel;

    

    control ctrl(
        .I_control(control),
        .I_breq(breq),
        .I_brlt(brlt),
        
        .O_pcsel(pcsel),
        .O_immsel(immsel),
        .O_regwen(regwen),
        .O_brun(brun),
        .O_asel(asel),
        .O_bsel(bsel),
        .O_alusel(alusel),
        .O_memrw(memrw),
         .O_loadsel(loadsel),
        .O_storesel(storesel),
        .O_wbsel(wbsel)
    );

	initial begin



        $display("Control Codes for Upper Immediates");
        {control,breq,brlt} = `CONTROL_IN_LUI;
        #10 $display("LUI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_AUIPC;
        #10 $display("AUIPC:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});

        

        $display("\nControl Codes for Jumps");
        #10 {control,breq,brlt} = `CONTROL_IN_JAL;
        #10 $display("JAL:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_JALR; 
        #10 $display("JALR:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        

        $display("\nControl Codes for Branches - True");
        #10 {control,breq,brlt} = `CONTROL_IN_BEQ_TRUE;  
        #10 $display("BEQ:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BNE_TRUE; 
        #10 $display("BNE:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BLT_TRUE;  
        #10 $display("BLT:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BGE_TRUE;  
        #10 $display("BGE:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BLTU_TRUE; 
        #10 $display("BLTU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BGEU_TRUE; 
        #10 $display("BGEU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});


        $display("\nControl Codes for Branches - False");
        #10 {control,breq,brlt} = `CONTROL_IN_BEQ_FALSE;  
        #10 $display("BEQ:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BNE_FALSE; 
        #10 $display("BNE:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BLT_FALSE;  
        #10 $display("BLT:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BGE_FALSE;  
        #10 $display("BGE:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BLTU_FALSE; 
        #10 $display("BLTU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BGEU_FALSE; 
        #10 $display("BGEU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        

        $display("\nControl Codes for Loads");
        #10 {control,breq,brlt} = `CONTROL_IN_LB; 
        #10 $display("LB:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_LH; 
        #10 $display("LH:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_LW; 
        #10 $display("LW:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_LBU; 
        #10 $display("LBU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_LHU;
        #10 $display("LHU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        

        $display("\nControl Codes for Stores");
        #10 {control,breq,brlt} = `CONTROL_IN_SB; 
        #10 $display("SB:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SH;   
        #10 $display("SH:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SW;  
        #10 $display("SW:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        

        $display("\nControl Codes for Register <-> Immediate Operations");
        #10 {control,breq,brlt} = `CONTROL_IN_ADDI;
        #10 $display("ADDI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SLTI; 
        #10 $display("SLTI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SLTIU;
        #10 $display("SLTIU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_XORI; 
        #10 $display("XORI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_ORI; 
        #10 $display("ORI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_ANDI; 
        #10 $display("ANDI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SLLI; 
        #10 $display("SLLI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SRLI; 
        #10 $display("SRLI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SRAI; 
        #10 $display("SRAI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        

        $display("\nControl Codes for Register <-> Register Operations");
        #10 {control,breq,brlt} = `CONTROL_IN_ADD; 
        #10 $display("ADD:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SUB;
        #10 $display("SUB:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel}); 
        #10 {control,breq,brlt} = `CONTROL_IN_SLL;  
        #10 $display("SLL:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SLT; 
        #10 $display("SLT:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SLTU; 
        #10 $display("SLTU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_XOR; 
        #10 $display("XOR:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SRL;  
        #10 $display("SRL:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SRA; 
        #10 $display("SRA:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_OR;  
        #10 $display("OR:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_AND;  
        #10 $display("AND:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        

        $display("\nTesting Default Case");
        #10 {control,breq,brlt} = 11'b11111111111;  
        #10 $display("DEFAULT:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        


		#10 $finish;
	end
	
endmodule
module control_tb;

	

    reg [9:0] control;
    reg breq;
    reg brlt;
    
    wire pcsel;
    wire [2:0] immsel;
    wire regwen;
    wire brun;
    wire asel;
    wire bsel;
    wire [3:0] alusel;
    wire memrw;
    wire [2:0] loadsel;
    wire [1:0] storesel;
    wire [1:0] wbsel;

    

    control ctrl(
        .I_control(control),
        .I_breq(breq),
        .I_brlt(brlt),
        
        .O_pcsel(pcsel),
        .O_immsel(immsel),
        .O_regwen(regwen),
        .O_brun(brun),
        .O_asel(asel),
        .O_bsel(bsel),
        .O_alusel(alusel),
        .O_memrw(memrw),
         .O_loadsel(loadsel),
        .O_storesel(storesel),
        .O_wbsel(wbsel)
    );

	initial begin



        $display("Control Codes for Upper Immediates");
        {control,breq,brlt} = `CONTROL_IN_LUI;
        #10 $display("LUI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_AUIPC;
        #10 $display("AUIPC:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});

        

        $display("\nControl Codes for Jumps");
        #10 {control,breq,brlt} = `CONTROL_IN_JAL;
        #10 $display("JAL:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_JALR; 
        #10 $display("JALR:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        

        $display("\nControl Codes for Branches - True");
        #10 {control,breq,brlt} = `CONTROL_IN_BEQ_TRUE;  
        #10 $display("BEQ:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BNE_TRUE; 
        #10 $display("BNE:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BLT_TRUE;  
        #10 $display("BLT:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BGE_TRUE;  
        #10 $display("BGE:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BLTU_TRUE; 
        #10 $display("BLTU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BGEU_TRUE; 
        #10 $display("BGEU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});


        $display("\nControl Codes for Branches - False");
        #10 {control,breq,brlt} = `CONTROL_IN_BEQ_FALSE;  
        #10 $display("BEQ:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BNE_FALSE; 
        #10 $display("BNE:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BLT_FALSE;  
        #10 $display("BLT:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BGE_FALSE;  
        #10 $display("BGE:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BLTU_FALSE; 
        #10 $display("BLTU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_BGEU_FALSE; 
        #10 $display("BGEU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        

        $display("\nControl Codes for Loads");
        #10 {control,breq,brlt} = `CONTROL_IN_LB; 
        #10 $display("LB:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_LH; 
        #10 $display("LH:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_LW; 
        #10 $display("LW:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_LBU; 
        #10 $display("LBU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_LHU;
        #10 $display("LHU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        

        $display("\nControl Codes for Stores");
        #10 {control,breq,brlt} = `CONTROL_IN_SB; 
        #10 $display("SB:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SH;   
        #10 $display("SH:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SW;  
        #10 $display("SW:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        

        $display("\nControl Codes for Register <-> Immediate Operations");
        #10 {control,breq,brlt} = `CONTROL_IN_ADDI;
        #10 $display("ADDI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SLTI; 
        #10 $display("SLTI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SLTIU;
        #10 $display("SLTIU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_XORI; 
        #10 $display("XORI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_ORI; 
        #10 $display("ORI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_ANDI; 
        #10 $display("ANDI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SLLI; 
        #10 $display("SLLI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SRLI; 
        #10 $display("SRLI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SRAI; 
        #10 $display("SRAI:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        

        $display("\nControl Codes for Register <-> Register Operations");
        #10 {control,breq,brlt} = `CONTROL_IN_ADD; 
        #10 $display("ADD:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SUB;
        #10 $display("SUB:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel}); 
        #10 {control,breq,brlt} = `CONTROL_IN_SLL;  
        #10 $display("SLL:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SLT; 
        #10 $display("SLT:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SLTU; 
        #10 $display("SLTU:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_XOR; 
        #10 $display("XOR:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SRL;  
        #10 $display("SRL:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_SRA; 
        #10 $display("SRA:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_OR;  
        #10 $display("OR:\t\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        #10 {control,breq,brlt} = `CONTROL_IN_AND;  
        #10 $display("AND:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        

        $display("\nTesting Default Case");
        #10 {control,breq,brlt} = 11'b11111111111;  
        #10 $display("DEFAULT:\tIn=%b, Out=%b", {control,breq,brlt}, {pcsel, immsel, regwen, brun, asel, bsel, alusel, memrw, loadsel, storesel, wbsel});
        


		#10 $finish;
	end
	
endmodule