data/full_repos/permissive/175063152/ip/gcm_aes_1.0/src/rtl/aes_rcon.v
data/verilator_xmls/ed4fd1ff-bb23-44fd-ba7f-0228a5421b31.xml
module aes_rcon(clk, kld, out);
input		clk;
input		kld;
output	[7:0]	out;
reg	[7:0]	out;
reg	[3:0]	rcnt;
wire	[3:0]	rcnt_next;

always @(posedge clk)
begin
	if(kld)	out <=  8'h01;
	else		out <=  frcon(rcnt_next);

end	

assign rcnt_next = rcnt + 4'h1;

always @(posedge clk)
begin
	if(kld)	rcnt <=  4'h0;
	else		rcnt <=  rcnt_next;

end

function [7:0]	frcon;
input	[3:0]	i;
case(i)
   4'h0: frcon=8'h01;
   4'h1: frcon=8'h02;
   4'h2: frcon=8'h04;
   4'h3: frcon=8'h08;
   4'h4: frcon=8'h10;
   4'h5: frcon=8'h20;
   4'h6: frcon=8'h40;
   4'h7: frcon=8'h80;
   4'h8: frcon=8'h1b;
   4'h9: frcon=8'h36;
   default: frcon=8'h00;
endcase
endfunction

endmodule
module aes_rcon(clk, kld, out);

input		clk;
input		kld;
output	[7:0]	out;
reg	[7:0]	out;
reg	[3:0]	rcnt;
wire	[3:0]	rcnt_next;

always @(posedge clk)
begin
	if(kld)	out <=  8'h01;
	else		out <=  frcon(rcnt_next);

end	

assign rcnt_next = rcnt + 4'h1;

always @(posedge clk)
begin
	if(kld)	rcnt <=  4'h0;
	else		rcnt <=  rcnt_next;

end

function [7:0]	frcon;
input	[3:0]	i;
case(i)
   4'h0: frcon=8'h01;
   4'h1: frcon=8'h02;
   4'h2: frcon=8'h04;
   4'h3: frcon=8'h08;
   4'h4: frcon=8'h10;
   4'h5: frcon=8'h20;
   4'h6: frcon=8'h40;
   4'h7: frcon=8'h80;
   4'h8: frcon=8'h1b;
   4'h9: frcon=8'h36;
   default: frcon=8'h00;
endcase
endfunction

endmodule