data/full_repos/permissive/20759093/CPU_TOP.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/20759093/CPU_TOP.v:241: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'Single_Cycle_CPU\'\nmodule Single_Cycle_CPU(\n       ^~~~~~~~~~~~~~~~\n                                                                    : ... Top module \'mux_2_to_1_5\'\nmodule mux_2_to_1_5(\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/20759093/CPU_TOP.v:496: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                 : ... In instance Single_Cycle_CPU.M4\n            4\'b1001 : result <= (A < B);\n                             ^~\n%Error: data/full_repos/permissive/20759093/CPU_TOP.v:104: Cannot find file containing module: \'RAM_A\'\n    RAM_A M8(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A.v\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A.sv\n             RAM_A\n             RAM_A.v\n             RAM_A.sv\n             obj_dir/RAM_A\n             obj_dir/RAM_A.v\n             obj_dir/RAM_A.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module mux_4_to_1_32(
    input [31:0] A,B,C,D,
    input [1:0] enable,
    output reg[31:0] O
);

    always @* begin
        case (enable) 
            2'b00 : begin
                O <= A;
            end
            2'b01 : begin
                O <= B;
            end
            2'b10 : begin
                O <= C;
            end
            2'b11 : begin
                O <= D;
            end
        endcase
    end

endmodule
module mux_4_to_1_32(
    input [31:0] A,B,C,D,
    input [1:0] enable,
    output reg[31:0] O
);


    always @* begin
        case (enable) 
            2'b00 : begin
                O <= A;
            end
            2'b01 : begin
                O <= B;
            end
            2'b10 : begin
                O <= C;
            end
            2'b11 : begin
                O <= D;
            end
        endcase
    end

endmodule