data/full_repos/permissive/129527056/cores/1943/ver/timing/test.v
 line:38: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/129527056/cores/1943/ver/timing/test.v:10: Unsupported: Ignoring delay on this delayed statement.\n    forever #41.66 clk=~clk;     \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129527056/cores/1943/ver/timing/test.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #50 rst=0;\n    ^\n%Error: data/full_repos/permissive/129527056/cores/1943/ver/timing/test.v:32: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test.lxt");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129527056/cores/1943/ver/timing/test.v:33: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,test);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/129527056/cores/1943/ver/timing/test.v:34: Unsupported or unknown PLI call: $dumpon\n    $dumpon;\n    ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/129527056/cores/1943/ver/timing/test.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #60_000_000 $finish;\n    ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

reg clk, rst, cen6;

initial begin
    clk=0;
    cen6=0;
    forever #41.66 clk=~clk;
end

always @(posedge clk) cen6<=~cen6 & ~rst;

initial begin
    rst = 1;
    #50 rst=0;
end

wire LHBL, LVBL, intrq, hsync, vsync, sync;

parameter LAYOUT=0;

jtgng_timer #(
    .LAYOUT ( LAYOUT    )
) u_timer(
    .clk        ( clk   ),
    .cen6       ( cen6  )
);

initial begin
    $dumpfile("test.lxt");
    $dumpvars(0,test);
    $dumpon;
end

initial begin
    #60_000_000 $finish;
end

endmodule
module test;


reg clk, rst, cen6;

initial begin
    clk=0;
    cen6=0;
    forever #41.66 clk=~clk;
end

always @(posedge clk) cen6<=~cen6 & ~rst;

initial begin
    rst = 1;
    #50 rst=0;
end

wire LHBL, LVBL, intrq, hsync, vsync, sync;

parameter LAYOUT=0;

jtgng_timer #(
    .LAYOUT ( LAYOUT    )
) u_timer(
    .clk        ( clk   ),
    .cen6       ( cen6  )
);

initial begin
    $dumpfile("test.lxt");
    $dumpvars(0,test);
    $dumpon;
end

initial begin
    #60_000_000 $finish;
end

endmodule