data/full_repos/permissive/139476920/rtl/ramcpld.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/139476920/rtl/ramcpld.v:126: Signal definition not found, creating implicitly: \'RAM_ACCESS\'\n                                                                         : ... Suggested alternative: \'GAYLE_ACCESS\'\nwire fastcycle_int =   (RAM_ACCESS | RAM_WAIT) & GAYLE_D2 & Z2_ACCESS & GAYLE_ACCESS & GAYLE_IDE;\n                        ^~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/139476920/rtl/ramcpld.v:126: Signal definition not found, creating implicitly: \'RAM_WAIT\'\n                                                                         : ... Suggested alternative: \'RAM_A\'\nwire fastcycle_int =   (RAM_ACCESS | RAM_WAIT) & GAYLE_D2 & Z2_ACCESS & GAYLE_ACCESS & GAYLE_IDE;\n                                     ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/139476920/rtl/ramcpld.v:126: Signal definition not found, creating implicitly: \'Z2_ACCESS\'\n                                                                         : ... Suggested alternative: \'RAM_ACCESS\'\nwire fastcycle_int =   (RAM_ACCESS | RAM_WAIT) & GAYLE_D2 & Z2_ACCESS & GAYLE_ACCESS & GAYLE_IDE;\n                                                            ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/139476920/rtl/ramcpld.v:213: Signal definition not found, creating implicitly: \'FASTCYCLE1\'\nassign DSACK[1] = FASTCYCLE1 ? 1\'bz : 1\'b0;\n                  ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/139476920/rtl/ramcpld.v:214: Signal definition not found, creating implicitly: \'FASTCYCLE0\'\n                                                                         : ... Suggested alternative: \'FASTCYCLE1\'\nassign DSACK[0] = FASTCYCLE0 ? 1\'bz : 1\'b0;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/139476920/rtl/ramcpld.v:74: Cannot find file containing module: \'gayle\'\ngayle GAYLE(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/139476920/rtl,data/full_repos/permissive/139476920/gayle\n             data/full_repos/permissive/139476920/rtl,data/full_repos/permissive/139476920/gayle.v\n             data/full_repos/permissive/139476920/rtl,data/full_repos/permissive/139476920/gayle.sv\n             gayle\n             gayle.v\n             gayle.sv\n             obj_dir/gayle\n             obj_dir/gayle.v\n             obj_dir/gayle.sv\n%Error: data/full_repos/permissive/139476920/rtl/ramcpld.v:92: Cannot find file containing module: \'fastmem\'\nfastmem FASTRAM( \n^~~~~~~\n%Error: data/full_repos/permissive/139476920/rtl/ramcpld.v:128: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Error: data/full_repos/permissive/139476920/rtl/ramcpld.v:137: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Warning-WIDTH: data/full_repos/permissive/139476920/rtl/ramcpld.v:150: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?hf\' generates 32 or 4 bits.\n                                                                      : ... In instance ramcpld\n      POR <= \'hF;\n          ^~\n%Error: data/full_repos/permissive/139476920/rtl/ramcpld.v:187: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Error: data/full_repos/permissive/139476920/rtl/ramcpld.v:196: Cannot find file containing module: \'FDCP\'\nFDCP #(.INIT(1\'b1)) \n^~~~\n%Error: Exiting due to 6 error(s), 6 warning(s)\n'
module ramcpld(

		input	CLKCPU,
		input	RESET,

		input	[23:0] A,
		
		inout	[7:0] D,
		input [1:0] SIZ,
		
		input   IDEINT,
		output  INT2,
        
		input 	AS20,
		input		RW20,
		input 	DS20,
		

		output 		 RAM_MUX,		
		output 		 RAMOE,
		output [3:0] CAS,
		output [1:0] RAS,
		output [1:0] RAM_A,

		output [1:0] DSACK,
		output		 PUNT,
		
		output		 IOR,
		output		 IOW,
		
		output [1:0] IDECS

       );


wire GAYLE_INT2;


wire GAYLE_IDE = ({A[23:15]} != {8'hDA,1'b0}) | AS20;


wire GAYLE_REGS = (A[23:15] != {8'hDA, 1'b1});

wire GAYLE_ID= (A[23:15] != {8'hDE, 1'b0});
wire GAYLE_ACCESS = (GAYLE_ID & GAYLE_REGS) | AS20;

reg [2:0] POR = 3'b111;

wire gayle_dout;
   
gayle GAYLE(

    .CLKCPU ( CLKCPU        ),
    .RESET  ( RESET         ),
    .CS     ( GAYLE_ACCESS  ),
    .DS     ( DS20  | GAYLE_ACCESS       ),
    .RW     ( RW20          ),
    .A18    ( A[18]         ),
    .A      ( {A[13:12]}	),
    .IDE_INT( IDEINT        ),
    .INT2   ( GAYLE_INT2    ),
    .D7	    ( D[7]	        ),
	.DOUT7	( gayle_dout  	 )

);
reg AS20_D = 1'b1;
reg AS20_D2 = 1'b1;

fastmem FASTRAM( 
					
					.CLKCPU		( CLKCPU	),
					.RESET		( RESET & ~POR[2]	),
					.AS20		( AS20     ),
					.DS20		( DS20		),
					.RW20		( RW20		),
        
					.A			( A			), 
					.D			( D			),
					.SIZ		( SIZ		),
			
					.CAS		( CAS		),
					.RAS		( RAS		),
					
					.RAM_MUX 	( RAM_MUX	),
					.RAMOE 		( RAMOE		),
					.RAM_A 		( RAM_A		),
					.RAM_ACCESS ( RAM_ACCESS),
					
					.Z2_ACCESS 	( Z2_ACCESS	),
					.WAIT		( RAM_WAIT )
					
               );

reg intcycle_dout = 1'b0;

reg GAYLE_D  = 1'b1;
reg GAYLE_D2 = 1'b1;

wire DSHOLD2 = {AS20_D,AS20, RW20} == {1'b1,1'b0,1'b0};
wire IOR_INT = ~RW20 | GAYLE_IDE | DSHOLD2;
wire IOW_INT = RW20 | GAYLE_IDE | DSHOLD2; 

wire fastcycle_int =   (RAM_ACCESS | RAM_WAIT) & GAYLE_D2 & Z2_ACCESS & GAYLE_ACCESS & GAYLE_IDE;
	
FDCP #(.INIT(1'b1)) 
	FASTCYCLE1_FF (
		.Q(FASTCYCLE1),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(fastcycle_int),
		.PRE(AS20)
);

FDCP #(.INIT(1'b1)) 
	FASTCYCLE0_FF (
		.Q(FASTCYCLE0),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(fastcycle_int | RAM_ACCESS),
		.PRE(AS20)
);

always @(posedge CLKCPU or negedge RESET) begin	

   if (RESET == 1'b0) begin

      POR <= 'hF;

   end else begin



      POR[2:0] <= {POR[1:0], 1'b0};
      
   end

end
 
always @(posedge CLKCPU or posedge AS20) begin	
	
	 if (AS20 == 1'b1) begin 

		AS20_D <= 1'b1;
		AS20_D2 <= 1'b1;
		GAYLE_D <= 1'b1;
		GAYLE_D2 <= 1'b1;
		
	end else begin 

		intcycle_dout <= (~GAYLE_ACCESS) & RW20;
		AS20_D <= AS20;
		AS20_D2 <= AS20_D;
		GAYLE_D2 <= GAYLE_D;
		
		if (GAYLE_IDE == 1'b0) begin 
			
			GAYLE_D <= 1'b0;
		
		end
	end
	 
end

FDCP #(.INIT(1'b1)) 
	IOR_FF (
		.Q(IOR),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(IOR_INT),
		.PRE(AS20)
);

FDCP #(.INIT(1'b1)) 
	IOW_FF (
		.Q(IOW),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(IOW_INT),
		.PRE(AS20)
);

assign PUNT = POR[2] | GAYLE_ACCESS & GAYLE_IDE & RAM_ACCESS & Z2_ACCESS  ? 1'bz : 1'b0;
assign IDECS = A[12] ? {GAYLE_IDE, 1'b1} : {1'b1, GAYLE_IDE}; 

assign INT2 = GAYLE_INT2 ? 1'b0 : 1'bz;
wire [7:4] data_out = GAYLE_ACCESS ? 4'b1111 : {gayle_dout,3'b000};

assign D[7:0] = (intcycle_dout) ? {data_out[7:4], 4'h0} : 8'bzzzzzzzz;   

assign DSACK[1] = FASTCYCLE1 ? 1'bz : 1'b0;
assign DSACK[0] = FASTCYCLE0 ? 1'bz : 1'b0;

endmodule
module ramcpld(

		input	CLKCPU,
		input	RESET,

		input	[23:0] A,
		
		inout	[7:0] D,
		input [1:0] SIZ,
		
		input   IDEINT,
		output  INT2,
        
		input 	AS20,
		input		RW20,
		input 	DS20,
		

		output 		 RAM_MUX,		
		output 		 RAMOE,
		output [3:0] CAS,
		output [1:0] RAS,
		output [1:0] RAM_A,

		output [1:0] DSACK,
		output		 PUNT,
		
		output		 IOR,
		output		 IOW,
		
		output [1:0] IDECS

       );



wire GAYLE_INT2;


wire GAYLE_IDE = ({A[23:15]} != {8'hDA,1'b0}) | AS20;


wire GAYLE_REGS = (A[23:15] != {8'hDA, 1'b1});

wire GAYLE_ID= (A[23:15] != {8'hDE, 1'b0});
wire GAYLE_ACCESS = (GAYLE_ID & GAYLE_REGS) | AS20;

reg [2:0] POR = 3'b111;

wire gayle_dout;
   
gayle GAYLE(

    .CLKCPU ( CLKCPU        ),
    .RESET  ( RESET         ),
    .CS     ( GAYLE_ACCESS  ),
    .DS     ( DS20  | GAYLE_ACCESS       ),
    .RW     ( RW20          ),
    .A18    ( A[18]         ),
    .A      ( {A[13:12]}	),
    .IDE_INT( IDEINT        ),
    .INT2   ( GAYLE_INT2    ),
    .D7	    ( D[7]	        ),
	.DOUT7	( gayle_dout  	 )

);
reg AS20_D = 1'b1;
reg AS20_D2 = 1'b1;

fastmem FASTRAM( 
					
					.CLKCPU		( CLKCPU	),
					.RESET		( RESET & ~POR[2]	),
					.AS20		( AS20     ),
					.DS20		( DS20		),
					.RW20		( RW20		),
        
					.A			( A			), 
					.D			( D			),
					.SIZ		( SIZ		),
			
					.CAS		( CAS		),
					.RAS		( RAS		),
					
					.RAM_MUX 	( RAM_MUX	),
					.RAMOE 		( RAMOE		),
					.RAM_A 		( RAM_A		),
					.RAM_ACCESS ( RAM_ACCESS),
					
					.Z2_ACCESS 	( Z2_ACCESS	),
					.WAIT		( RAM_WAIT )
					
               );

reg intcycle_dout = 1'b0;

reg GAYLE_D  = 1'b1;
reg GAYLE_D2 = 1'b1;

wire DSHOLD2 = {AS20_D,AS20, RW20} == {1'b1,1'b0,1'b0};
wire IOR_INT = ~RW20 | GAYLE_IDE | DSHOLD2;
wire IOW_INT = RW20 | GAYLE_IDE | DSHOLD2; 

wire fastcycle_int =   (RAM_ACCESS | RAM_WAIT) & GAYLE_D2 & Z2_ACCESS & GAYLE_ACCESS & GAYLE_IDE;
	
FDCP #(.INIT(1'b1)) 
	FASTCYCLE1_FF (
		.Q(FASTCYCLE1),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(fastcycle_int),
		.PRE(AS20)
);

FDCP #(.INIT(1'b1)) 
	FASTCYCLE0_FF (
		.Q(FASTCYCLE0),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(fastcycle_int | RAM_ACCESS),
		.PRE(AS20)
);

always @(posedge CLKCPU or negedge RESET) begin	

   if (RESET == 1'b0) begin

      POR <= 'hF;

   end else begin



      POR[2:0] <= {POR[1:0], 1'b0};
      
   end

end
 
always @(posedge CLKCPU or posedge AS20) begin	
	
	 if (AS20 == 1'b1) begin 

		AS20_D <= 1'b1;
		AS20_D2 <= 1'b1;
		GAYLE_D <= 1'b1;
		GAYLE_D2 <= 1'b1;
		
	end else begin 

		intcycle_dout <= (~GAYLE_ACCESS) & RW20;
		AS20_D <= AS20;
		AS20_D2 <= AS20_D;
		GAYLE_D2 <= GAYLE_D;
		
		if (GAYLE_IDE == 1'b0) begin 
			
			GAYLE_D <= 1'b0;
		
		end
	end
	 
end

FDCP #(.INIT(1'b1)) 
	IOR_FF (
		.Q(IOR),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(IOR_INT),
		.PRE(AS20)
);

FDCP #(.INIT(1'b1)) 
	IOW_FF (
		.Q(IOW),
		.C(CLKCPU),
		.CLR(1'b0),
		.D(IOW_INT),
		.PRE(AS20)
);

assign PUNT = POR[2] | GAYLE_ACCESS & GAYLE_IDE & RAM_ACCESS & Z2_ACCESS  ? 1'bz : 1'b0;
assign IDECS = A[12] ? {GAYLE_IDE, 1'b1} : {1'b1, GAYLE_IDE}; 

assign INT2 = GAYLE_INT2 ? 1'b0 : 1'bz;
wire [7:4] data_out = GAYLE_ACCESS ? 4'b1111 : {gayle_dout,3'b000};

assign D[7:0] = (intcycle_dout) ? {data_out[7:4], 4'h0} : 8'bzzzzzzzz;   

assign DSACK[1] = FASTCYCLE1 ? 1'bz : 1'b0;
assign DSACK[0] = FASTCYCLE0 ? 1'bz : 1'b0;

endmodule