data/full_repos/permissive/113582216/Homework/timer.v
data/verilator_xmls/542711e8-5b05-4250-a1f2-50b51d6944e8.xml
module timer(
    input clk,
    input reset,
    output [3:0] bcdout
    );
    reg [25:0] count;
    reg [3:0] out;

    initial
    begin
        count = 26'b0;
        out = 4'd9;
    end

    always @ (negedge clk)
    begin
        if (reset)
        begin
            count <= 26'b0;
        end
        else
        begin
            count <= count + 1;
        end
    end

    always @ (negedge clk)
    begin
        if (reset)
            out <= 4'd9;
        else
        begin
            if(count==(~26'b0))
            begin
                if (out==4'd0)
                    out <= 4'd9;
                else
                    out <= out - 1;
            end
        end
    end

    assign bcdout = out;

endmodule
module timer(
    input clk,
    input reset,
    output [3:0] bcdout
    );

    reg [25:0] count;
    reg [3:0] out;

    initial
    begin
        count = 26'b0;
        out = 4'd9;
    end

    always @ (negedge clk)
    begin
        if (reset)
        begin
            count <= 26'b0;
        end
        else
        begin
            count <= count + 1;
        end
    end

    always @ (negedge clk)
    begin
        if (reset)
            out <= 4'd9;
        else
        begin
            if(count==(~26'b0))
            begin
                if (out==4'd0)
                    out <= 4'd9;
                else
                    out <= out - 1;
            end
        end
    end

    assign bcdout = out;

endmodule