data/full_repos/permissive/146399661/src/vedic/vedic8_t.v
 line:32: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/146399661/src/vedic/vedic8_t.v:31: Unsupported: Ignoring delay on this delayed statement.\n#10 a=8\'b11111111;b=8\'b11111111;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/vedic/vedic8_t.v:32: Unsupported: Ignoring delay on this delayed statement.\n#10$stop;\n^\n%Error: data/full_repos/permissive/146399661/src/vedic/vedic8_t.v:29: Cannot find file containing module: \'vedic8\'\nvedic8 uut(.a(a),.b(b),.c(c));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146399661/src/vedic,data/full_repos/permissive/146399661/vedic8\n             data/full_repos/permissive/146399661/src/vedic,data/full_repos/permissive/146399661/vedic8.v\n             data/full_repos/permissive/146399661/src/vedic,data/full_repos/permissive/146399661/vedic8.sv\n             vedic8\n             vedic8.v\n             vedic8.sv\n             obj_dir/vedic8\n             obj_dir/vedic8.v\n             obj_dir/vedic8.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vedic8_t;
wire d;
wire e;
wire f;
reg [7:0]a;
reg [7:0]b;
wire [15:0]q0;	
wire [15:0]q1;	
wire [15:0]q2;
wire [15:0]q3;	
wire [15:0]c;
wire [7:0]temp1;
wire [11:0]temp2;
wire [11:0]temp3;
wire [11:0]temp4;
wire [7:0]q4;
wire [11:0]q5;
wire [11:0]q6;
vedic8 uut(.a(a),.b(b),.c(c));
initial begin
#10 a=8'b11111111;b=8'b11111111;
#10$stop;
end
endmodule
module vedic8_t;

wire d;
wire e;
wire f;
reg [7:0]a;
reg [7:0]b;
wire [15:0]q0;	
wire [15:0]q1;	
wire [15:0]q2;
wire [15:0]q3;	
wire [15:0]c;
wire [7:0]temp1;
wire [11:0]temp2;
wire [11:0]temp3;
wire [11:0]temp4;
wire [7:0]q4;
wire [11:0]q5;
wire [11:0]q6;
vedic8 uut(.a(a),.b(b),.c(c));
initial begin
#10 a=8'b11111111;b=8'b11111111;
#10$stop;
end
endmodule