data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sim_1/new/test.v
1: b'%Warning-WIDTH: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sim_1/new/test.v:29: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'ha\' generates 8 bits.\n                                                                                                  : ... In instance test\n    wire [8:0] count = 8\'h0A;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sim_1/new/test.v:40: Cannot find file containing module: \'seg7decimal\'\n    seg7decimal show (count[8:0], clk, SEG[6:0], AN[1:0], DP);\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sim_1/new,data/full_repos/permissive/204410271/seg7decimal\n             data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sim_1/new,data/full_repos/permissive/204410271/seg7decimal.v\n             data/full_repos/permissive/204410271/FPGA_Metro_Ticketing.srcs/sim_1/new,data/full_repos/permissive/204410271/seg7decimal.sv\n             seg7decimal\n             seg7decimal.v\n             seg7decimal.sv\n             obj_dir/seg7decimal\n             obj_dir/seg7decimal.v\n             obj_dir/seg7decimal.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module test(

    );
    wire [6:0] SEG;
    wire [7:0] AN;
    wire DP;
    wire [8:0] count = 8'h0A;
    wire [15:0] SW;
    reg clk = 1;
    always @(*)
        clk = ~clk;






    seg7decimal show (count[8:0], clk, SEG[6:0], AN[1:0], DP);
endmodule
module test(

    );

    wire [6:0] SEG;
    wire [7:0] AN;
    wire DP;
    wire [8:0] count = 8'h0A;
    wire [15:0] SW;
    reg clk = 1;
    always @(*)
        clk = ~clk;






    seg7decimal show (count[8:0], clk, SEG[6:0], AN[1:0], DP);
endmodule