data/full_repos/permissive/157979234/Semester III/Digital Design and Computer Organization/Session 07/mproc.v
1: b'%Error: Cannot find file containing module: III/Digital\n        ... Looked in:\n             data/full_repos/permissive/157979234/Semester/III/Digital\n             data/full_repos/permissive/157979234/Semester/III/Digital.v\n             data/full_repos/permissive/157979234/Semester/III/Digital.sv\n             III/Digital\n             III/Digital.v\n             III/Digital.sv\n             obj_dir/III/Digital\n             obj_dir/III/Digital.v\n             obj_dir/III/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Organization/Session\n%Error: Cannot find file containing module: 07,data/full_repos/permissive/157979234\n%Error: Cannot find file containing module: data/full_repos/permissive/157979234/Semester\n%Error: Cannot find file containing module: 07/mproc.v\n%Error: Exiting due to 8 error(s)\n'
module mproc (input wire clk, reset, input wire [15:0] ins, output wire [15:0] addr);
  wire pc_inc, cout; wire [2:0] rd_addr_a, rd_addr_b, wr_addr; wire [1:0] op; wire [15:0] cur_ins, d_out_a, d_out_b;

  pc pc_0 (clk, reset, pc_inc, 1'b0, 1'b0, 16'b0, addr);
  ir ir_0 (clk, reset, load_ir, ins, cur_ins);
  control_logic control_logic_0 (clk, reset, cur_ins, rd_addr_a, rd_addr_b, wr_addr, op, pc_inc, load_ir, wr_reg);
  reg_alu reg_alu_0 (clk, reset, 1'b1, wr_reg, op, rd_addr_a, rd_addr_b, wr_addr, 16'b0, d_out_a, d_out_b, cout);
endmodule
module mproc (input wire clk, reset, input wire [15:0] ins, output wire [15:0] addr);

  wire pc_inc, cout; wire [2:0] rd_addr_a, rd_addr_b, wr_addr; wire [1:0] op; wire [15:0] cur_ins, d_out_a, d_out_b;

  pc pc_0 (clk, reset, pc_inc, 1'b0, 1'b0, 16'b0, addr);
  ir ir_0 (clk, reset, load_ir, ins, cur_ins);
  control_logic control_logic_0 (clk, reset, cur_ins, rd_addr_a, rd_addr_b, wr_addr, op, pc_inc, load_ir, wr_reg);
  reg_alu reg_alu_0 (clk, reset, 1'b1, wr_reg, op, rd_addr_a, rd_addr_b, wr_addr, 16'b0, d_out_a, d_out_b, cout);
endmodule