data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:64: Unsupported: Ignoring delay on this delayed statement.\n# 100\n^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:67: Unsupported: Ignoring delay on this delayed statement.\n# 100 \n^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:74: Unsupported: Ignoring delay on this delayed statement.\n# 20 \n^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:81: Unsupported: Ignoring delay on this delayed statement.\n# 20 \n^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:88: Unsupported: Ignoring delay on this delayed statement.\n# 20 \n^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:96: Unsupported: Ignoring delay on this delayed statement.\n# 20 \n^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:102: Unsupported: Ignoring delay on this delayed statement.\n# 20 \n^\n%Warning-STMTDLY: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:108: Unsupported: Ignoring delay on this delayed statement.\n# 20 \n^\n%Error: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:23: Cannot find file containing module: \'icb_interface\'\nicb_interface sim_icb_interface (\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm,data/full_repos/permissive/160924877/icb_interface\n             data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm,data/full_repos/permissive/160924877/icb_interface.v\n             data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm,data/full_repos/permissive/160924877/icb_interface.sv\n             icb_interface\n             icb_interface.v\n             icb_interface.sv\n             obj_dir/icb_interface\n             obj_dir/icb_interface.v\n             obj_dir/icb_interface.sv\n%Warning-WIDTH: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:70: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h8\' generates 5 bits.\n                                                                                              : ... In instance sim_icb\n i_icb_cmd_addr = 5\'d8; \n                ^\n%Warning-WIDTH: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:77: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h9\' generates 5 bits.\n                                                                                              : ... In instance sim_icb\n i_icb_cmd_addr = 5\'d9; \n                ^\n%Warning-WIDTH: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:84: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'ha\' generates 5 bits.\n                                                                                              : ... In instance sim_icb\n i_icb_cmd_addr = 5\'d10; \n                ^\n%Warning-WIDTH: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:91: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'hb\' generates 5 bits.\n                                                                                              : ... In instance sim_icb\n i_icb_cmd_addr = 5\'d11; \n                ^\n%Warning-WIDTH: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:99: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h8\' generates 5 bits.\n                                                                                              : ... In instance sim_icb\n i_icb_cmd_addr = 5\'d8; \n                ^\n%Warning-WIDTH: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:105: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h9\' generates 5 bits.\n                                                                                               : ... In instance sim_icb\n i_icb_cmd_addr = 5\'d9; \n                ^\n%Warning-WIDTH: data/full_repos/permissive/160924877/RISCV_RA_PL/e203/Robotic_Arm/sim_icb.v:111: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h2\' generates 5 bits.\n                                                                                               : ... In instance sim_icb\n i_icb_cmd_addr = 5\'d2; \n                ^\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_icb (

	
);


reg	i_icb_cmd_valid;
wire i_icb_cmd_ready;
reg [31:0] i_icb_cmd_addr; 
reg i_icb_cmd_read; 
reg [31:0] i_icb_cmd_wdata;
	
wire i_icb_rsp_valid;
wire i_icb_rsp_ready;
wire [31:0]	i_icb_rsp_rdata;

reg	clk;
reg	rst_n;



icb_interface sim_icb_interface (

	.i_icb_cmd_valid(i_icb_cmd_valid),
	.i_icb_cmd_ready(i_icb_cmd_ready),
	.i_icb_cmd_addr(i_icb_cmd_addr),
	.i_icb_cmd_read(i_icb_cmd_read),
	.i_icb_cmd_wdata(i_icb_cmd_wdata),

	.i_icb_rsp_valid(i_icb_rsp_valid),
	.i_icb_rsp_ready(i_icb_rsp_ready),
	.i_icb_rsp_rdata(i_icb_rsp_rdata),

	.clk(clk),
	.rst_n(rst_n)

);


assign i_icb_rsp_ready = i_icb_rsp_valid;



always begin
	#10
	clk = ~clk;

end


initial begin
	clk = 1'b0;



	rst_n = 1'b0;

	i_icb_cmd_valid = 'd0;
	i_icb_cmd_addr = 'd0; 
	i_icb_cmd_read = 'd0; 
	i_icb_cmd_wdata = 'd0;

# 100
	rst_n = 1'b1;

# 100	

	i_icb_cmd_valid = 1'b1;
	i_icb_cmd_addr = 5'd8; 
	i_icb_cmd_read = 'd0; 
	i_icb_cmd_wdata = 32'd10;

# 20 

	i_icb_cmd_valid = 1'b1;
	i_icb_cmd_addr = 5'd9; 
	i_icb_cmd_read = 'd0; 
	i_icb_cmd_wdata = 32'd12;

# 20 

	i_icb_cmd_valid = 1'b1;
	i_icb_cmd_addr = 5'd10; 
	i_icb_cmd_read = 'd0; 
	i_icb_cmd_wdata = 32'd14;

# 20 

	i_icb_cmd_valid = 1'b0;
	i_icb_cmd_addr = 5'd11; 
	i_icb_cmd_read = 'd0; 
	i_icb_cmd_wdata = 32'd14;


# 20 

	i_icb_cmd_valid = 1'b1;
	i_icb_cmd_addr = 5'd8; 
	i_icb_cmd_read = 'd1; 

# 20 

	i_icb_cmd_valid = 1'b1;
	i_icb_cmd_addr = 5'd9; 
	i_icb_cmd_read = 'd1; 

# 20 

	i_icb_cmd_valid = 1'b1;
	i_icb_cmd_addr = 5'd2; 
	i_icb_cmd_read = 'd1; 

end


endmodule
module sim_icb (

	
);



reg	i_icb_cmd_valid;
wire i_icb_cmd_ready;
reg [31:0] i_icb_cmd_addr; 
reg i_icb_cmd_read; 
reg [31:0] i_icb_cmd_wdata;
	
wire i_icb_rsp_valid;
wire i_icb_rsp_ready;
wire [31:0]	i_icb_rsp_rdata;

reg	clk;
reg	rst_n;



icb_interface sim_icb_interface (

	.i_icb_cmd_valid(i_icb_cmd_valid),
	.i_icb_cmd_ready(i_icb_cmd_ready),
	.i_icb_cmd_addr(i_icb_cmd_addr),
	.i_icb_cmd_read(i_icb_cmd_read),
	.i_icb_cmd_wdata(i_icb_cmd_wdata),

	.i_icb_rsp_valid(i_icb_rsp_valid),
	.i_icb_rsp_ready(i_icb_rsp_ready),
	.i_icb_rsp_rdata(i_icb_rsp_rdata),

	.clk(clk),
	.rst_n(rst_n)

);


assign i_icb_rsp_ready = i_icb_rsp_valid;



always begin
	#10
	clk = ~clk;

end


initial begin
	clk = 1'b0;



	rst_n = 1'b0;

	i_icb_cmd_valid = 'd0;
	i_icb_cmd_addr = 'd0; 
	i_icb_cmd_read = 'd0; 
	i_icb_cmd_wdata = 'd0;

# 100
	rst_n = 1'b1;

# 100	

	i_icb_cmd_valid = 1'b1;
	i_icb_cmd_addr = 5'd8; 
	i_icb_cmd_read = 'd0; 
	i_icb_cmd_wdata = 32'd10;

# 20 

	i_icb_cmd_valid = 1'b1;
	i_icb_cmd_addr = 5'd9; 
	i_icb_cmd_read = 'd0; 
	i_icb_cmd_wdata = 32'd12;

# 20 

	i_icb_cmd_valid = 1'b1;
	i_icb_cmd_addr = 5'd10; 
	i_icb_cmd_read = 'd0; 
	i_icb_cmd_wdata = 32'd14;

# 20 

	i_icb_cmd_valid = 1'b0;
	i_icb_cmd_addr = 5'd11; 
	i_icb_cmd_read = 'd0; 
	i_icb_cmd_wdata = 32'd14;


# 20 

	i_icb_cmd_valid = 1'b1;
	i_icb_cmd_addr = 5'd8; 
	i_icb_cmd_read = 'd1; 

# 20 

	i_icb_cmd_valid = 1'b1;
	i_icb_cmd_addr = 5'd9; 
	i_icb_cmd_read = 'd1; 

# 20 

	i_icb_cmd_valid = 1'b1;
	i_icb_cmd_addr = 5'd2; 
	i_icb_cmd_read = 'd1; 

end


endmodule