data/full_repos/permissive/176628218/clk_divider.v
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data/verilator_xmls/dbcdef1b-f313-45d7-bbc0-a2d9284ddd7e.xml
module clk_divider(
    input clk,
    output reg clk_divd

    );
    
    reg [31:0]count;

    parameter delay = 100_000;
    initial begin
        count = 0;
        clk_divd = 0;

    end
    
    always@ (posedge clk) begin
        if (count >= delay / 2) begin
            count = 0;
            clk_divd = ~clk_divd;
        end
        count = count + 1;
    end
	 







    
endmodule
module clk_divider(
    input clk,
    output reg clk_divd

    );

    
    reg [31:0]count;

    parameter delay = 100_000;
    initial begin
        count = 0;
        clk_divd = 0;

    end
    
    always@ (posedge clk) begin
        if (count >= delay / 2) begin
            count = 0;
            clk_divd = ~clk_divd;
        end
        count = count + 1;
    end
	 







    
endmodule