data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sources_1/new/RF.v
data/verilator_xmls/e088e1e4-7ccf-4956-8de0-3c83984771a0.xml
module RF(
input clk, rea, reb, we,
input [1:0] raa, rab, wa,
input [2:0] din,
output reg [2:0] douta, doutb
);

reg [2:0] RegFile [3:0];

always @ (rea, reb, raa, rab)
begin
        if (rea)
            douta = RegFile[raa];
        else douta = 3'b000;
        if (reb)
            doutb = RegFile[rab];
        else doutb = 3'b000;
end

always @ (posedge clk)
begin
        if(we)
            RegFile[wa] <= din;
        else
            RegFile[wa] <= RegFile[wa];
end
endmodule
module RF(
input clk, rea, reb, we,
input [1:0] raa, rab, wa,
input [2:0] din,
output reg [2:0] douta, doutb
);


reg [2:0] RegFile [3:0];

always @ (rea, reb, raa, rab)
begin
        if (rea)
            douta = RegFile[raa];
        else douta = 3'b000;
        if (reb)
            doutb = RegFile[rab];
        else doutb = 3'b000;
end

always @ (posedge clk)
begin
        if(we)
            RegFile[wa] <= din;
        else
            RegFile[wa] <= RegFile[wa];
end
endmodule