data/full_repos/permissive/126160535/verilog/top/cam_proj_top.v
1: b"%Error: data/full_repos/permissive/126160535/verilog/top/cam_proj_top.v:90: Cannot find file containing module: 'pll'\npll pll_for_sdram_0\n^~~\n        ... Looked in:\n             data/full_repos/permissive/126160535/verilog/top,data/full_repos/permissive/126160535/pll\n             data/full_repos/permissive/126160535/verilog/top,data/full_repos/permissive/126160535/pll.v\n             data/full_repos/permissive/126160535/verilog/top,data/full_repos/permissive/126160535/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Error: data/full_repos/permissive/126160535/verilog/top/cam_proj_top.v:100: Cannot find file containing module: 'pll_for_disp'\npll_for_disp pll2\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/126160535/verilog/top/cam_proj_top.v:110: Cannot find file containing module: 'cam_wrp'\ncam_wrp cam_wrp_0\n^~~~~~~\n%Error: data/full_repos/permissive/126160535/verilog/top/cam_proj_top.v:126: Cannot find file containing module: 'hellosoc_top'\nhellosoc_top TFT(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/126160535/verilog/top/cam_proj_top.v:175: Cannot find file containing module: 'sdram_controller'\nsdram_controller SDRAM(\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/126160535/verilog/top/cam_proj_top.v:207: Cannot find file containing module: 'pre_v2'\npre_v2 grayscale(\n^~~~~~\n%Error: data/full_repos/permissive/126160535/verilog/top/cam_proj_top.v:222: Cannot find file containing module: 'TOP'\nTOP neiroset (\n^~~\n%Error: data/full_repos/permissive/126160535/verilog/top/cam_proj_top.v:297: Cannot find file containing module: 'camera_configure'\ncamera_configure \n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module cam_proj_top
(

	input wire clk50,             
	input wire rst,
	input wire start_gray_kn,

	input wire [7:0] data_cam,
	input wire VSYNC_cam,
	input wire HREF_cam,
	input wire PCLK_cam,
	output wire XCLK_cam,
	output reg res_cam,
	output reg on_off_cam,
	output wire sioc,
	output wire siod,

	output wire [4:0] r,  
	output wire [5:0] g,
	output wire [4:0] b, 	

	output wire cs_n,
	output wire ras_n,
	output wire cas_n,
	output wire we_n,
	output wire [1:0] dqm,
	output wire [11:0] sd_addr,
	output wire [1:0] ba,
	output wire Cke,
	inout wire [15:0] sd_data, 
	output wire sdram_clk, 

	input tft_sdo,
	output wire tft_sck, 
	output wire tft_sdi, 
	output wire tft_dc, 
	output wire tft_reset, 
	output wire tft_cs,

	output [7:0] LED
);

wire fbClk;
wire rst_n;
wire clk25;
wire clk100;
wire clk24;
wire clk143; 
wire [15:0] input_fifo_to_sdram;

assign rst_n = rst;
assign sdram_clk = clk143;

wire locked;
wire [11:0] output_rdusedw_TFT;
wire start_image;
wire [3:0] RESULT;
reg GO_NEIROSET;
wire end_neiroset;
reg [3:0] RESULT_2;

wire ctrl_busy;
wire [23:0] wr_addr;
wire wr_enable;
wire [15:0] rd_data;
reg [23:0] rd_addr;
wire rd_ready;
reg ready;



assign LED[0] = wr_enable;
assign LED[1] = !wr_enable;
assign LED[2] = 1'b0;
assign LED[3] = 1'b0;
assign LED[4] = 1'b0;
assign LED[5] = 1'b0;
assign LED[6] = 1'b0;
assign LED[7] = 1'b0;




pll pll_for_sdram_0
(
	.areset   ( !rst_n ),
	.inclk0   ( clk50 ),
	.c0       ( clk100 ),
	.c2       ( clk25 ),
	.c3       ( clk24 ),
	.locked   ( locked )
);

pll_for_disp pll2
(
	.areset   ( !rst_n ),
	.inclk0   ( clk50 ),
	.c0       ( clk143 )

);



cam_wrp cam_wrp_0
(
	.rst_n                ( rst_n ),
	.data_cam             ( data_cam ),
	.HREF_cam             ( HREF_cam ),
	.PCLK_cam             ( PCLK_cam ),
	.ctrl_busy            ( ctrl_busy ),
	.input_fifo_to_sdram  ( input_fifo_to_sdram ),
	.addr_sdram           ( wr_addr ),
	.wr_enable            ( wr_enable )
);

assign XCLK_cam = clk24;



hellosoc_top TFT(
	.tft_sdo            ( tft_sdo ), 
	.tft_sck            ( tft_sck ), 
	.tft_sdi            ( tft_sdi ), 
	.tft_dc             ( tft_dc ), 
	.tft_reset          ( tft_reset ), 
	.tft_cs             ( tft_cs ),
	.rst_n              ( rst_n ),
	.clk_sdram          ( !rd_ready ),
	.wr_fifo            ( (!wr_enable) && ready ),
	.sdram_data         ( rd_data ),
	.tft_clk            ( clk100 ),
	.output_rdusedw     ( output_rdusedw_TFT ),
	.fbClk              ( fbClk ),
	.r                  ( r ),
	.g                  ( g ),
	.b                  ( b ),
	.start_28           ( start_image ),
	.RESULT             ( RESULT_2 )
);

reg [9:0] x_sdram;

always @(posedge rd_ready or negedge rst_n)
begin
	if (!rst_n)
	begin
		rd_addr = 320*201+3;
		ready=1'b1;
		x_sdram=0;
	end
	else
	begin
		if ((!wr_enable)&&(ready))
				begin
					if (rd_addr < 24'd76799) rd_addr = rd_addr + 1'b1;
					else rd_addr=24'd0;
					if (x_sdram<320) x_sdram=x_sdram+1'b1;
					else x_sdram=1;
				end
		if (x_sdram==320)
			begin
				if ((!wr_enable)&&(output_rdusedw_TFT<=3000)) begin ready=1'b1;  end
				else begin  ready=1'b0;  end
			end
	end
end

	
sdram_controller SDRAM(
	.wr_addr       (wr_addr),
	.wr_data       (input_fifo_to_sdram),
	.wr_enable     (wr_enable),
	.rd_addr       (rd_addr),
	.rd_data       (rd_data),
	.rd_ready      (rd_ready),
	.rd_enable     (!wr_enable),
	.busy          (ctrl_busy), 
	.rst_n         (rst_n), 
	.clk           (clk143),

	.addr          (sd_addr), 
	.bank_addr     (ba), 
	.data          (sd_data), 
	.clock_enable  (Cke),	 
	.cs_n          (cs_n), 
	.ras_n         (ras_n), 
	.cas_n         (cas_n), 
	.we_n          (we_n),	
	.data_mask_low (dqm[0]), 
	.data_mask_high(dqm[1]) 
);


reg start_gray;
wire end_gray;
reg [9:0] x_gray, y_gray;
wire [4:0] i_gray, j_gray;
wire [12:0] out_data_gray;
wire wrreq_gray;

pre_v2 grayscale(
	.clk           (fbClk), 
	.rst_n         (rst_n),
	.start         (start_gray), 
	.data          ({r,g,b}), 
	.end_pre       (end_gray), 
	.output_data   (out_data_gray), 
	.x             (x_gray), 
	.y             (y_gray), 
	.i             (i_gray), 
	.j             (j_gray) ,
	.data_req      (wrreq_gray)
);


TOP neiroset (
	.clk                (clk50),
	.GO                 (GO_NEIROSET),
	.RESULT             (RESULT),
	.we_database        (wrreq_gray),
	.dp_database        (out_data_gray),
	.address_p_database (j_gray*28+i_gray),
	.STOP               (end_neiroset)
);


always @(posedge fbClk or negedge rst_n) 
begin
	if ( !rst_n )
	begin
		x_gray = 10'd0;
		y_gray = 10'd0;
		start_gray = 1'b0;
	end
	else
	begin
		if (start_image)
			begin
				if (x_gray == 10'd319) 
				begin
					x_gray <= 10'd0;
					if (y_gray == 10'd239) 
					begin
						y_gray <= 10'd0;
					end
					else y_gray <= y_gray+1'b1;
				end
				else x_gray <= x_gray+1'b1;
			end
			
		if ((GO_NEIROSET == 1'b1) && (x_gray == 10'd47) && (y_gray == 10'd239)) start_gray = 1'b1;
		if (end_gray) start_gray = 1'b0;
	end
end	


always @(posedge clk50 or negedge rst_n) 
begin
	if ( !rst_n )
	begin
		RESULT_2 = 4'b1111;
		GO_NEIROSET = 1'b1;
	end
	else
	begin
		if (end_gray) begin GO_NEIROSET = 1'b0; end
		if (end_neiroset) begin GO_NEIROSET = 1'b1; RESULT_2 = RESULT; end
	end
end




reg [2:0] strt;

always @(posedge clk25 or negedge rst_n)
	if (!rst_n)
		strt <= 3'h0;
	else
	begin
		if (locked)
			begin
				if ( &strt )
					strt	<= strt;
				else
					strt	<= strt + 1'h1;
			end
	end


camera_configure 
#(	
	.CLK_FREQ 	( 25000000 )
)
camera_configure_0
(
	.clk   ( clk25            ),	
	.start ( ( strt == 3'h6 ) ),
	.sioc  ( sioc             ),
	.siod  ( siod             ),
	.done  ( 			        )
);


assign res_cam    = rst_n;
assign on_off_cam = !rst_n;

endmodule
module cam_proj_top
(

	input wire clk50,             
	input wire rst,
	input wire start_gray_kn,

	input wire [7:0] data_cam,
	input wire VSYNC_cam,
	input wire HREF_cam,
	input wire PCLK_cam,
	output wire XCLK_cam,
	output reg res_cam,
	output reg on_off_cam,
	output wire sioc,
	output wire siod,

	output wire [4:0] r,  
	output wire [5:0] g,
	output wire [4:0] b, 	

	output wire cs_n,
	output wire ras_n,
	output wire cas_n,
	output wire we_n,
	output wire [1:0] dqm,
	output wire [11:0] sd_addr,
	output wire [1:0] ba,
	output wire Cke,
	inout wire [15:0] sd_data, 
	output wire sdram_clk, 

	input tft_sdo,
	output wire tft_sck, 
	output wire tft_sdi, 
	output wire tft_dc, 
	output wire tft_reset, 
	output wire tft_cs,

	output [7:0] LED
);


wire fbClk;
wire rst_n;
wire clk25;
wire clk100;
wire clk24;
wire clk143; 
wire [15:0] input_fifo_to_sdram;

assign rst_n = rst;
assign sdram_clk = clk143;

wire locked;
wire [11:0] output_rdusedw_TFT;
wire start_image;
wire [3:0] RESULT;
reg GO_NEIROSET;
wire end_neiroset;
reg [3:0] RESULT_2;

wire ctrl_busy;
wire [23:0] wr_addr;
wire wr_enable;
wire [15:0] rd_data;
reg [23:0] rd_addr;
wire rd_ready;
reg ready;



assign LED[0] = wr_enable;
assign LED[1] = !wr_enable;
assign LED[2] = 1'b0;
assign LED[3] = 1'b0;
assign LED[4] = 1'b0;
assign LED[5] = 1'b0;
assign LED[6] = 1'b0;
assign LED[7] = 1'b0;




pll pll_for_sdram_0
(
	.areset   ( !rst_n ),
	.inclk0   ( clk50 ),
	.c0       ( clk100 ),
	.c2       ( clk25 ),
	.c3       ( clk24 ),
	.locked   ( locked )
);

pll_for_disp pll2
(
	.areset   ( !rst_n ),
	.inclk0   ( clk50 ),
	.c0       ( clk143 )

);



cam_wrp cam_wrp_0
(
	.rst_n                ( rst_n ),
	.data_cam             ( data_cam ),
	.HREF_cam             ( HREF_cam ),
	.PCLK_cam             ( PCLK_cam ),
	.ctrl_busy            ( ctrl_busy ),
	.input_fifo_to_sdram  ( input_fifo_to_sdram ),
	.addr_sdram           ( wr_addr ),
	.wr_enable            ( wr_enable )
);

assign XCLK_cam = clk24;



hellosoc_top TFT(
	.tft_sdo            ( tft_sdo ), 
	.tft_sck            ( tft_sck ), 
	.tft_sdi            ( tft_sdi ), 
	.tft_dc             ( tft_dc ), 
	.tft_reset          ( tft_reset ), 
	.tft_cs             ( tft_cs ),
	.rst_n              ( rst_n ),
	.clk_sdram          ( !rd_ready ),
	.wr_fifo            ( (!wr_enable) && ready ),
	.sdram_data         ( rd_data ),
	.tft_clk            ( clk100 ),
	.output_rdusedw     ( output_rdusedw_TFT ),
	.fbClk              ( fbClk ),
	.r                  ( r ),
	.g                  ( g ),
	.b                  ( b ),
	.start_28           ( start_image ),
	.RESULT             ( RESULT_2 )
);

reg [9:0] x_sdram;

always @(posedge rd_ready or negedge rst_n)
begin
	if (!rst_n)
	begin
		rd_addr = 320*201+3;
		ready=1'b1;
		x_sdram=0;
	end
	else
	begin
		if ((!wr_enable)&&(ready))
				begin
					if (rd_addr < 24'd76799) rd_addr = rd_addr + 1'b1;
					else rd_addr=24'd0;
					if (x_sdram<320) x_sdram=x_sdram+1'b1;
					else x_sdram=1;
				end
		if (x_sdram==320)
			begin
				if ((!wr_enable)&&(output_rdusedw_TFT<=3000)) begin ready=1'b1;  end
				else begin  ready=1'b0;  end
			end
	end
end

	
sdram_controller SDRAM(
	.wr_addr       (wr_addr),
	.wr_data       (input_fifo_to_sdram),
	.wr_enable     (wr_enable),
	.rd_addr       (rd_addr),
	.rd_data       (rd_data),
	.rd_ready      (rd_ready),
	.rd_enable     (!wr_enable),
	.busy          (ctrl_busy), 
	.rst_n         (rst_n), 
	.clk           (clk143),

	.addr          (sd_addr), 
	.bank_addr     (ba), 
	.data          (sd_data), 
	.clock_enable  (Cke),	 
	.cs_n          (cs_n), 
	.ras_n         (ras_n), 
	.cas_n         (cas_n), 
	.we_n          (we_n),	
	.data_mask_low (dqm[0]), 
	.data_mask_high(dqm[1]) 
);


reg start_gray;
wire end_gray;
reg [9:0] x_gray, y_gray;
wire [4:0] i_gray, j_gray;
wire [12:0] out_data_gray;
wire wrreq_gray;

pre_v2 grayscale(
	.clk           (fbClk), 
	.rst_n         (rst_n),
	.start         (start_gray), 
	.data          ({r,g,b}), 
	.end_pre       (end_gray), 
	.output_data   (out_data_gray), 
	.x             (x_gray), 
	.y             (y_gray), 
	.i             (i_gray), 
	.j             (j_gray) ,
	.data_req      (wrreq_gray)
);


TOP neiroset (
	.clk                (clk50),
	.GO                 (GO_NEIROSET),
	.RESULT             (RESULT),
	.we_database        (wrreq_gray),
	.dp_database        (out_data_gray),
	.address_p_database (j_gray*28+i_gray),
	.STOP               (end_neiroset)
);


always @(posedge fbClk or negedge rst_n) 
begin
	if ( !rst_n )
	begin
		x_gray = 10'd0;
		y_gray = 10'd0;
		start_gray = 1'b0;
	end
	else
	begin
		if (start_image)
			begin
				if (x_gray == 10'd319) 
				begin
					x_gray <= 10'd0;
					if (y_gray == 10'd239) 
					begin
						y_gray <= 10'd0;
					end
					else y_gray <= y_gray+1'b1;
				end
				else x_gray <= x_gray+1'b1;
			end
			
		if ((GO_NEIROSET == 1'b1) && (x_gray == 10'd47) && (y_gray == 10'd239)) start_gray = 1'b1;
		if (end_gray) start_gray = 1'b0;
	end
end	


always @(posedge clk50 or negedge rst_n) 
begin
	if ( !rst_n )
	begin
		RESULT_2 = 4'b1111;
		GO_NEIROSET = 1'b1;
	end
	else
	begin
		if (end_gray) begin GO_NEIROSET = 1'b0; end
		if (end_neiroset) begin GO_NEIROSET = 1'b1; RESULT_2 = RESULT; end
	end
end




reg [2:0] strt;

always @(posedge clk25 or negedge rst_n)
	if (!rst_n)
		strt <= 3'h0;
	else
	begin
		if (locked)
			begin
				if ( &strt )
					strt	<= strt;
				else
					strt	<= strt + 1'h1;
			end
	end


camera_configure 
#(	
	.CLK_FREQ 	( 25000000 )
)
camera_configure_0
(
	.clk   ( clk25            ),	
	.start ( ( strt == 3'h6 ) ),
	.sioc  ( sioc             ),
	.siod  ( siod             ),
	.done  ( 			        )
);


assign res_cam    = rst_n;
assign on_off_cam = !rst_n;

endmodule