data/full_repos/permissive/169639758/ice40/regressions/issue0148/hdl/cpu/regfile.v
data/verilator_xmls/3b607852-d82c-482c-9e56-2496e3c72f3b.xml
module regfile #(
	parameter AWIDTH = 4,
	parameter DWIDTH = 16
	)(
	input clk,
	input [AWIDTH-1:0]asel,
	input [AWIDTH-1:0]bsel,
	input [AWIDTH-1:0]wsel,
	input wreg,
	output [DWIDTH-1:0]adata,
	output [DWIDTH-1:0]bdata,
	input [DWIDTH-1:0]wdata
	);

reg [DWIDTH-1:0] R[0:((1<<AWIDTH)-1)];

always @(posedge clk) begin
	if (wreg)
		R[wsel] <= wdata;
end
assign adata = R[asel];
assign bdata = R[bsel];

endmodule
module regfile #(
	parameter AWIDTH = 4,
	parameter DWIDTH = 16
	)(
	input clk,
	input [AWIDTH-1:0]asel,
	input [AWIDTH-1:0]bsel,
	input [AWIDTH-1:0]wsel,
	input wreg,
	output [DWIDTH-1:0]adata,
	output [DWIDTH-1:0]bdata,
	input [DWIDTH-1:0]wdata
	);


reg [DWIDTH-1:0] R[0:((1<<AWIDTH)-1)];

always @(posedge clk) begin
	if (wreg)
		R[wsel] <= wdata;
end
assign adata = R[asel];
assign bdata = R[bsel];

endmodule