data/full_repos/permissive/135852214/Verilog/CUsim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/CUsim.v:59: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk <= ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/CUsim.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/135852214/Verilog/CUsim.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #20 INSTR = i;\n        ^\n%Error: data/full_repos/permissive/135852214/Verilog/CUsim.v:45: Cannot find file containing module: \'CU\'\n CU uut (\n ^~\n        ... Looked in:\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/CU\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/CU.v\n             data/full_repos/permissive/135852214/Verilog,data/full_repos/permissive/135852214/CU.sv\n             CU\n             CU.v\n             CU.sv\n             obj_dir/CU\n             obj_dir/CU.v\n             obj_dir/CU.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CUsim;


	reg [3:0] INSTR;
	reg OVF;
	reg clk;
	reg reset;
	reg [3:0] i;


	wire WEa;
	wire WEb;
	wire WEpc;
	wire CTRLa;
	wire CTRLpc;
	wire CTRLaddr;
	wire RW;
	wire CIN;


	CU uut (
		.INSTR(INSTR), 
		.OVF(OVF), 
		.clk(clk), 
		.reset(reset), 
		.WEa(WEa), 
		.WEb(WEb), 
		.WEpc(WEpc), 
		.CTRLa(CTRLa), 
		.CTRLpc(CTRLpc), 
		.CTRLaddr(CTRLaddr), 
		.RW(RW), 
		.CIN(CIN)
	);
	always #10 clk <= ~clk;
	initial begin

		INSTR = 0;
		OVF = 0;
		clk = 0;
		reset = 1;


		#100;
		reset = 0;
		for(i = 4'd0; i < 4'd11; i = i+1)
        #20 INSTR = i;


	end
      
endmodule
module CUsim;



	reg [3:0] INSTR;
	reg OVF;
	reg clk;
	reg reset;
	reg [3:0] i;


	wire WEa;
	wire WEb;
	wire WEpc;
	wire CTRLa;
	wire CTRLpc;
	wire CTRLaddr;
	wire RW;
	wire CIN;


	CU uut (
		.INSTR(INSTR), 
		.OVF(OVF), 
		.clk(clk), 
		.reset(reset), 
		.WEa(WEa), 
		.WEb(WEb), 
		.WEpc(WEpc), 
		.CTRLa(CTRLa), 
		.CTRLpc(CTRLpc), 
		.CTRLaddr(CTRLaddr), 
		.RW(RW), 
		.CIN(CIN)
	);
	always #10 clk <= ~clk;
	initial begin

		INSTR = 0;
		OVF = 0;
		clk = 0;
		reset = 1;


		#100;
		reset = 0;
		for(i = 4'd0; i < 4'd11; i = i+1)
        #20 INSTR = i;


	end
      
endmodule