data/full_repos/permissive/125592111/verilog/Multiplexers.v
None: at end of input
1: b'%Warning-MULTITOP: data/full_repos/permissive/125592111/verilog/Multiplexers.v:32: Multiple top level modules\n                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                 : ... Top module \'first_alu_mux_3_to_1\'\nmodule first_alu_mux_3_to_1(In1_RegRs, In2_fwdEx, In3_fwdMem, Ctrl_FwdA, out);\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'second_alu_mux_3_to_1\'\nmodule second_alu_mux_3_to_1(In1_RegRt, In2_fwdEx, In3_fwdMem, Ctrl_FwdB, out);\n       ^~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'third_alu_mux_2_to_1\'\nmodule third_alu_mux_2_to_1(In1_second_alu_mux, In2_immediate, Ctrl_ALUSrc, out);\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'idEx_to_exMem_mux_2_to_1\'\nmodule idEx_to_exMem_mux_2_to_1(In1_rd, In2_rt, Ctrl_RegDst, out);\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'writeback_source_mux_3_to_1\'\nmodule writeback_source_mux_3_to_1(In1_ALU_Result, In2_Mem_output, In3_PC_plus_4, Ctrl_MemToReg, out);\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'regDst_mux_2_to_1\'\nmodule regDst_mux_2_to_1(In2_rType_rd, In3_jal_ra, Ctrl_RegDst, out);\n       ^~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'first_PC4_or_branch_mux_2_to_1\'\nmodule first_PC4_or_branch_mux_2_to_1(In1_PC_plus_4, In2_BTA, Ctrl_Branch_Gate, out);\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'second_jump_or_first_mux_2_to_1\'\nmodule second_jump_or_first_mux_2_to_1(In1_first_mux, In2_jump_addr_calc, Ctrl_Jump, out);\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'third_jr_or_second_mux_2_to_1\'\nmodule third_jr_or_second_mux_2_to_1(In1_second_mux, In2_reg_value_ra, JRCtrl, out);\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'hazard_stall_mux_2_to_1\'\nmodule hazard_stall_mux_2_to_1(h_RegWrite, h_MemWrite, Ctrl_Mux_Select_Stall, h_RegWrite_out, h_MemWrite_out);\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'PC_input_mux_2_to_1\'\nmodule PC_input_mux_2_to_1(pc_plus_4, branch_or_jump_in, Ctrl_branch_or_jump_taken, out);\n       ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module idEx_to_exMem_mux_2_to_1(In1_rd, In2_rt, Ctrl_RegDst, out);
	input [4:0] In1_rd, In2_rt;
	input [1:0] Ctrl_RegDst;
	output reg [4:0] out;
	always @(In1_rd, In2_rt, Ctrl_RegDst) begin
		case (Ctrl_RegDst) 
			0: out <= In2_rt;
			1: out <= In1_rd;
		endcase
	end
endmodule
module idEx_to_exMem_mux_2_to_1(In1_rd, In2_rt, Ctrl_RegDst, out);

	input [4:0] In1_rd, In2_rt;
	input [1:0] Ctrl_RegDst;
	output reg [4:0] out;
	always @(In1_rd, In2_rt, Ctrl_RegDst) begin
		case (Ctrl_RegDst) 
			0: out <= In2_rt;
			1: out <= In1_rd;
		endcase
	end
endmodule