data/full_repos/permissive/129155059/proyecto-01/includes/mux_ctr_cond.v
None: at end of input
data/verilator_xmls/96b25ff2-9d5b-4155-bdde-d0bf1b265cf0.xml
module mux_ctr_cond(  input             valid_count,
                      input             CLK,
                      input             reset,
                      output reg [2:0]  CTR
                      );





always @ (posedge CLK) begin
  if (reset) begin
    if (valid_count) begin
      CTR <= CTR + 1;
    end else begin
      CTR <= CTR;
    end
  end else begin
    CTR <= 3'b111;
  end
end

endmodule
module mux_ctr_cond(  input             valid_count,
                      input             CLK,
                      input             reset,
                      output reg [2:0]  CTR
                      );






always @ (posedge CLK) begin
  if (reset) begin
    if (valid_count) begin
      CTR <= CTR + 1;
    end else begin
      CTR <= CTR;
    end
  end else begin
    CTR <= 3'b111;
  end
end

endmodule