data/full_repos/permissive/114943225/trigger.v
 line:37: before: ")"
1: b"%Error: data/full_repos/permissive/114943225/trigger.v:15: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\n input[2:0] type,\n            ^~~~\n%Error: data/full_repos/permissive/114943225/trigger.v:28: syntax error, unexpected IDENTIFIER\n comparator triggerComp (\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module edge_Trig(

	input clkIn,
	input[13:0] trigLvl,
	input[13:0] adc_data,
	input[13:0] trigHyst,
	input[2:0]	type,
	input			enable,
	output reg q

);


	wire compEvent;
	wire qStore;
	reg  qStorePos;
	reg  qStoreNeg;
	wire deadZone;

	comparator triggerComp (
	
		.clkIn(clkIn),
		.threshold(trigLvl),
		.hysteresis(trigHyst),
		.adc_data(adc_data),
		.q(compEvent),
		.z(deadZone),
	
	);
	
	initial begin
		qStorePos <= 0;
		qStoreNeg <= 0;
	end
	
	assign qStore = qStorePos | qStoreNeg;
	
	always @(posedge compEvent) begin	
		
		if ((type == 3'd1 || type == 3'd3)) begin
			
			qStorePos <= 1 & enable;
			
		end
		
	end
	
	
	always @(negedge compEvent) begin
	
		if ((type == 3'd2 || type == 3'd3)) begin
		
			qStoreNeg <= 1 & enable;
		
		end

	end
	

	
	
	always @(posedge clkIn) begin
	
		if (type == 3'd0) begin
		
			q = 0;
		
		end
		
		else if (type == 3'd4) begin
		
			q = 1;
		
		end
		
		else begin
			

			if (deadZone == 0) begin
				q = qStore;
			end
		
		end
	
	end
	
endmodule
module edge_Trig(

	input clkIn,
	input[13:0] trigLvl,
	input[13:0] adc_data,
	input[13:0] trigHyst,
	input[2:0]	type,
	input			enable,
	output reg q

);



	wire compEvent;
	wire qStore;
	reg  qStorePos;
	reg  qStoreNeg;
	wire deadZone;

	comparator triggerComp (
	
		.clkIn(clkIn),
		.threshold(trigLvl),
		.hysteresis(trigHyst),
		.adc_data(adc_data),
		.q(compEvent),
		.z(deadZone),
	
	);
	
	initial begin
		qStorePos <= 0;
		qStoreNeg <= 0;
	end
	
	assign qStore = qStorePos | qStoreNeg;
	
	always @(posedge compEvent) begin	
		
		if ((type == 3'd1 || type == 3'd3)) begin
			
			qStorePos <= 1 & enable;
			
		end
		
	end
	
	
	always @(negedge compEvent) begin
	
		if ((type == 3'd2 || type == 3'd3)) begin
		
			qStoreNeg <= 1 & enable;
		
		end

	end
	

	
	
	always @(posedge clkIn) begin
	
		if (type == 3'd0) begin
		
			q = 0;
		
		end
		
		else if (type == 3'd4) begin
		
			q = 1;
		
		end
		
		else begin
			

			if (deadZone == 0) begin
				q = qStore;
			end
		
		end
	
	end
	
endmodule