data/full_repos/permissive/130234582/demo_002/test_top.v
 line:21: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/130234582/demo_002/test_top.v:21: Unsupported: Ignoring delay on this delayed statement.\n     #5ns;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/130234582/demo_002/test_top.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #17ns\n    ^\n%Error: data/full_repos/permissive/130234582/demo_002/test_top.v:43: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/130234582/demo_002/test_top.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10000ns\n    ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_top;


reg clk;
reg rst_n;


initial begin

    clk = 0;

    forever begin

	    #5ns;

        clk = ~clk;
	end
end


initial begin

    rst_n = 0;




    #17ns

    rst_n = 1;
end


initial begin

    $dumpvars(0);
    #10000ns
    $finish;
end


wire clk_o;





CLK_DIV_2 DUT
(



    .clk    (clk),
    .rst_n  (rst_n),
    .clk_o  (clk_o)
);
endmodule
module test_top;



reg clk;
reg rst_n;


initial begin

    clk = 0;

    forever begin

	    #5ns;

        clk = ~clk;
	end
end


initial begin

    rst_n = 0;




    #17ns

    rst_n = 1;
end


initial begin

    $dumpvars(0);
    #10000ns
    $finish;
end


wire clk_o;





CLK_DIV_2 DUT
(



    .clk    (clk),
    .rst_n  (rst_n),
    .clk_o  (clk_o)
);
endmodule