data/full_repos/permissive/150152921/apps/aes/baseline/rtl/aes_256.v
 line:49: before: ","
1: b"%Error: data/full_repos/permissive/150152921/apps/aes/baseline/rtl/aes_256.v:135: Cannot find file containing module: 'S4'\n    S4\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/150152921/apps/aes/baseline/rtl,data/full_repos/permissive/150152921/S4\n             data/full_repos/permissive/150152921/apps/aes/baseline/rtl,data/full_repos/permissive/150152921/S4.v\n             data/full_repos/permissive/150152921/apps/aes/baseline/rtl,data/full_repos/permissive/150152921/S4.sv\n             S4\n             S4.v\n             S4.sv\n             obj_dir/S4\n             obj_dir/S4.v\n             obj_dir/S4.sv\n%Error: data/full_repos/permissive/150152921/apps/aes/baseline/rtl/aes_256.v:100: Cannot find file containing module: 'S4'\n    S4\n    ^~\n%Error: data/full_repos/permissive/150152921/apps/aes/baseline/rtl/aes_256.v:59: Cannot find file containing module: 'one_round'\n    one_round\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/aes/baseline/rtl/aes_256.v:74: Cannot find file containing module: 'final_round'\n    final_round\n    ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module expand_key_type_A_256 (clk, in, rcon, out_1, out_2);
    input              clk;
    input      [255:0] in;
    input      [7:0]   rcon;
    output reg [255:0] out_1;
    output     [127:0] out_2;
    wire       [31:0]  k0, k1, k2, k3, k4, k5, k6, k7,
                       v0, v1, v2, v3;
    reg        [31:0]  k0a, k1a, k2a, k3a, k4a, k5a, k6a, k7a;
    wire       [31:0]  k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8a;

    assign {k0, k1, k2, k3, k4, k5, k6, k7} = in;
    
    assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
    assign v1 = v0 ^ k1;
    assign v2 = v1 ^ k2;
    assign v3 = v2 ^ k3;

    always @ (posedge clk)
        {k0a, k1a, k2a, k3a, k4a, k5a, k6a, k7a} <= {v0, v1, v2, v3, k4, k5, k6, k7};

    S4
        S4_0 (clk, {k7[23:0], k7[31:24]}, k8a);

    assign k0b = k0a ^ k8a;
    assign k1b = k1a ^ k8a;
    assign k2b = k2a ^ k8a;
    assign k3b = k3a ^ k8a;
    assign {k4b, k5b, k6b, k7b} = {k4a, k5a, k6a, k7a};

    always @ (posedge clk)
        out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b};

    assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
module expand_key_type_A_256 (clk, in, rcon, out_1, out_2);

    input              clk;
    input      [255:0] in;
    input      [7:0]   rcon;
    output reg [255:0] out_1;
    output     [127:0] out_2;
    wire       [31:0]  k0, k1, k2, k3, k4, k5, k6, k7,
                       v0, v1, v2, v3;
    reg        [31:0]  k0a, k1a, k2a, k3a, k4a, k5a, k6a, k7a;
    wire       [31:0]  k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8a;

    assign {k0, k1, k2, k3, k4, k5, k6, k7} = in;
    
    assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
    assign v1 = v0 ^ k1;
    assign v2 = v1 ^ k2;
    assign v3 = v2 ^ k3;

    always @ (posedge clk)
        {k0a, k1a, k2a, k3a, k4a, k5a, k6a, k7a} <= {v0, v1, v2, v3, k4, k5, k6, k7};

    S4
        S4_0 (clk, {k7[23:0], k7[31:24]}, k8a);

    assign k0b = k0a ^ k8a;
    assign k1b = k1a ^ k8a;
    assign k2b = k2a ^ k8a;
    assign k3b = k3a ^ k8a;
    assign {k4b, k5b, k6b, k7b} = {k4a, k5a, k6a, k7a};

    always @ (posedge clk)
        out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b};

    assign out_2 = {k0b, k1b, k2b, k3b};
endmodule