data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_RAM_dual.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_RAM_dual.v:49: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD/2) \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_RAM_dual.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*3);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_RAM_dual.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*3);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_RAM_dual.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*3);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_RAM_dual.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_RAM_dual.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #(CLK_PERIOD*3);\n        ^\n%Error: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_RAM_dual.v:25: Cannot find file containing module: \'RAM_dual\'\n    RAM_dual #(8, 0) utt_s(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212763527/school_project/14_memory/testbenches,data/full_repos/permissive/212763527/RAM_dual\n             data/full_repos/permissive/212763527/school_project/14_memory/testbenches,data/full_repos/permissive/212763527/RAM_dual.v\n             data/full_repos/permissive/212763527/school_project/14_memory/testbenches,data/full_repos/permissive/212763527/RAM_dual.sv\n             RAM_dual\n             RAM_dual.v\n             RAM_dual.sv\n             obj_dir/RAM_dual\n             obj_dir/RAM_dual.v\n             obj_dir/RAM_dual.sv\n%Error: data/full_repos/permissive/212763527/school_project/14_memory/testbenches/tb_RAM_dual.v:37: Cannot find file containing module: \'RAM_dual\'\n    RAM_dual #(8, 1) utt_a(\n    ^~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_RAM_dual;

    reg clk;


    reg [7:0] din_a;
    reg [7:0] din_b;
    reg [2:0] addr_a;
    reg [2:0] addr_b;
    reg we;


    wire [7:0] dout_a_s;
    wire [7:0] dout_b_s;
    wire [7:0] dout_a_t;
    wire [7:0] dout_b_t;

    initial begin
        clk = 0;
    end
    

    RAM_dual #(8, 0) utt_s(
        din_a,
        din_b,
        addr_a,
        addr_b,
        clk,
        we,
        dout_a_s,
        dout_b_s
    );
    

    RAM_dual #(8, 1) utt_a(
        din_a,
        din_b,
        addr_a,
        addr_b,
        clk,
        we,
        dout_a_t,
        dout_b_t
    );

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;

    initial begin
        we = 1'b1;

        din_a = 8'h0_0;
        din_b = 8'h1_0;
        addr_a = 0;
        addr_b = 0;
        
        #(CLK_PERIOD*3);

        din_a = 8'h0_1;
        din_b = 8'h1_1;
        addr_a = 1;
        addr_b = 1;

        #(CLK_PERIOD*3);

        we = 1'b0;
        addr_a = 0;
        addr_b = 0;

        #(CLK_PERIOD*3);

        #3;

        addr_a = 1;
        addr_b = 1;

        #(CLK_PERIOD*3);

        $finish;
    end

endmodule
module tb_RAM_dual;


    reg clk;


    reg [7:0] din_a;
    reg [7:0] din_b;
    reg [2:0] addr_a;
    reg [2:0] addr_b;
    reg we;


    wire [7:0] dout_a_s;
    wire [7:0] dout_b_s;
    wire [7:0] dout_a_t;
    wire [7:0] dout_b_t;

    initial begin
        clk = 0;
    end
    

    RAM_dual #(8, 0) utt_s(
        din_a,
        din_b,
        addr_a,
        addr_b,
        clk,
        we,
        dout_a_s,
        dout_b_s
    );
    

    RAM_dual #(8, 1) utt_a(
        din_a,
        din_b,
        addr_a,
        addr_b,
        clk,
        we,
        dout_a_t,
        dout_b_t
    );

    localparam CLK_PERIOD = 10;
    always #(CLK_PERIOD/2) 
        clk=~clk;

    initial begin
        we = 1'b1;

        din_a = 8'h0_0;
        din_b = 8'h1_0;
        addr_a = 0;
        addr_b = 0;
        
        #(CLK_PERIOD*3);

        din_a = 8'h0_1;
        din_b = 8'h1_1;
        addr_a = 1;
        addr_b = 1;

        #(CLK_PERIOD*3);

        we = 1'b0;
        addr_a = 0;
        addr_b = 0;

        #(CLK_PERIOD*3);

        #3;

        addr_a = 1;
        addr_b = 1;

        #(CLK_PERIOD*3);

        $finish;
    end

endmodule