data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:10: Cannot find include file: sm_cpu.vh\n `include "sm_cpu.vh" \n          ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq,data/full_repos/permissive/102870077/sm_cpu.vh\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq,data/full_repos/permissive/102870077/sm_cpu.vh.v\n             data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq,data/full_repos/permissive/102870077/sm_cpu.vh.sv\n             sm_cpu.vh\n             sm_cpu.vh.v\n             sm_cpu.vh.sv\n             obj_dir/sm_cpu.vh\n             obj_dir/sm_cpu.vh.v\n             obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:11: Cannot find include file: sm_pcpu.vh\n `include "sm_pcpu.vh" \n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:52: Define or directive not defined: \'`HZ_FW_EF\'\n    wire [31:0] EPC_F     = ( hz_forwardEPC_F == `HZ_FW_EF ) ? writeData_E :\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire [31:0] EPC_F     = ( hz_forwardEPC_F == `HZ_FW_EF ) ? writeData_E :\n                                                           ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:53: Define or directive not defined: \'`HZ_FW_MF\'\n                            ( hz_forwardEPC_F == `HZ_FW_MF ) ? writeData_M :\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:56: Define or directive not defined: \'`PC_EXC\'\n    wire [31:0] pcNew_F   = cw_pcExc_D == `PC_EXC  ?  cp0_ExcHandler_M :\n                                          ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:56: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n    wire [31:0] pcNew_F   = cw_pcExc_D == `PC_EXC  ?  cp0_ExcHandler_M :\n                                                   ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:57: Define or directive not defined: \'`PC_ERET\'\n                            cw_pcExc_D == `PC_ERET ?  EPC_F            :\n                                          ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:235: Define or directive not defined: \'`HZ_FW_WE\'\n    wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:235: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (\n                                                         ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:236: Define or directive not defined: \'`HZ_FW_ME\'\n                            ( hz_forwardA_E == `HZ_FW_ME ) ? aluResult_M : regData1_E );\n                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:239: Define or directive not defined: \'`HZ_FW_WE\'\n    assign      writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:239: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign      writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (\n                                                           ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:240: Define or directive not defined: \'`HZ_FW_ME\'\n                              ( hz_forwardB_E == `HZ_FW_ME ) ? aluResult_M : regData2_E );\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:463: Define or directive not defined: \'`HZ_FW_NONE\'\n    assign hz_forwardA_E =  ( instrRs_E == 5\'b0                        ) ? `HZ_FW_NONE : (\n                                                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:463: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign hz_forwardA_E =  ( instrRs_E == 5\'b0                        ) ? `HZ_FW_NONE : (\n                                                                                       ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:464: Define or directive not defined: \'`HZ_FW_ME\'\n                            ( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME   : (\n                                                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:465: Define or directive not defined: \'`HZ_FW_WE\'\n                            ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));\n                                                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:465: Define or directive not defined: \'`HZ_FW_NONE\'\n                            ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));\n                                                                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:467: Define or directive not defined: \'`HZ_FW_NONE\'\n    assign hz_forwardB_E =  ( instrRt_E == 5\'b0                        ) ? `HZ_FW_NONE : (\n                                                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:467: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign hz_forwardB_E =  ( instrRt_E == 5\'b0                        ) ? `HZ_FW_NONE : (\n                                                                                       ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:468: Define or directive not defined: \'`HZ_FW_ME\'\n                            ( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME   : (\n                                                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:469: Define or directive not defined: \'`HZ_FW_WE\'\n                            ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));\n                                                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:469: Define or directive not defined: \'`HZ_FW_NONE\'\n                            ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));\n                                                                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:501: Define or directive not defined: \'`CP0_REG_NUM_EPC\'\n                               instrRd_E  == `CP0_REG_NUM_EPC && \n                                             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:501: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n                               instrRd_E  == `CP0_REG_NUM_EPC && \n                                                              ^~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:502: Define or directive not defined: \'`CP0_REG_SEL_EPC\'\n                               instrSel_E == `CP0_REG_SEL_EPC ) ? `HZ_FW_EF :\n                                             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:502: Define or directive not defined: \'`HZ_FW_EF\'\n                               instrSel_E == `CP0_REG_SEL_EPC ) ? `HZ_FW_EF :\n                                                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:504: Define or directive not defined: \'`CP0_REG_NUM_EPC\'\n                               instrRd_M  == `CP0_REG_NUM_EPC && \n                                             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:505: Define or directive not defined: \'`CP0_REG_SEL_EPC\'\n                               instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;\n                                             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:505: Define or directive not defined: \'`HZ_FW_MF\'\n                               instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;\n                                                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:505: Define or directive not defined: \'`HZ_FW_NONE\'\n                               instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;\n                                                                              ^~~~~~~~~~~\n%Error: Exiting due to 32 error(s)\n'
module sm_hazard_unit
(
    input   [ 4:0]  instrRs_E,
    input   [ 4:0]  instrRt_E,
    input   [ 4:0]  writeReg_M,
    input   [ 4:0]  writeReg_W,
    input           cw_regWrite_M,
    input           cw_regWrite_W,
    output  [ 1:0]  hz_forwardA_E,
    output  [ 1:0]  hz_forwardB_E,

    input   [ 4:0]  instrRs_D,
    input   [ 4:0]  instrRt_D,
    input   [ 4:0]  writeReg_E,
    input           cw_memToReg_E,
    output          hz_stall_n_F,
    output          hz_stall_n_D,
    output          hz_flush_n_E,

    input           cw_branch_D,
    input           cw_regWrite_E,
    input           cw_memToReg_M,
    output          hz_forwardA_D,
    output          hz_forwardB_D,

    input           cw_cpzToReg_E,
    input           cw_pcSrc_D,
    input           irqRequest_E,
    input           irqRequest_M,
    output          hz_flush_n_D,
    input           cw_cpzExcEret_D,
    input           excSync_D,
    output          hz_cancel_branch_F,
    output          hz_forwardEPC_E,
    output          hz_irq_disable_D,
    output   [ 1:0] hz_forwardEPC_F,
    input           cw_cpzRegWrite_E,
    input           cw_cpzRegWrite_M,
    input   [ 4:0]  instrRd_E,
    input   [ 4:0]  instrRd_M,
    input   [ 2:0]  instrSel_E,
    input   [ 2:0]  instrSel_M
);

    assign hz_forwardA_E =  ( instrRs_E == 5'b0                        ) ? `HZ_FW_NONE : (
                            ( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME   : (
                            ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));

    assign hz_forwardB_E =  ( instrRt_E == 5'b0                        ) ? `HZ_FW_NONE : (
                            ( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME   : (
                            ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));


    wire hz_mem_stall = ( cw_cpzToReg_E || cw_memToReg_E ) && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E );


    assign hz_forwardA_D = ( instrRs_D != 5'b0 && instrRs_D == writeReg_M && cw_regWrite_M );
    assign hz_forwardB_D = ( instrRt_D != 5'b0 && instrRt_D == writeReg_M && cw_regWrite_M );

    wire hz_branch_stall =  cw_branch_D && (
                             ( cw_regWrite_E && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E ))
                          || ( cw_memToReg_M && ( instrRs_D == writeReg_M || instrRt_D == writeReg_M ))
                            );

    wire hz_stall = hz_mem_stall || hz_branch_stall;


    wire   hz_branch_after_irq = cw_pcSrc_D & irqRequest_E;
    assign hz_cancel_branch_F  = hz_branch_after_irq;
    assign hz_forwardEPC_E     = hz_branch_after_irq;


    assign hz_irq_disable_D = irqRequest_E | irqRequest_M;


    assign hz_flush_n_D = ~((cw_pcSrc_D & ~irqRequest_E)
                           | cw_cpzExcEret_D
                           | excSync_D );



    assign hz_forwardEPC_F = ( cw_cpzExcEret_D && cw_cpzRegWrite_E && 
                               instrRd_E  == `CP0_REG_NUM_EPC && 
                               instrSel_E == `CP0_REG_SEL_EPC ) ? `HZ_FW_EF :
                             ( cw_cpzExcEret_D && cw_cpzRegWrite_M && 
                               instrRd_M  == `CP0_REG_NUM_EPC && 
                               instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;


    assign hz_stall_n_F = ~hz_stall;
    assign hz_stall_n_D = ~hz_stall;
    assign hz_flush_n_E = ~hz_stall;

endmodule
module sm_hazard_unit
(
    input   [ 4:0]  instrRs_E,
    input   [ 4:0]  instrRt_E,
    input   [ 4:0]  writeReg_M,
    input   [ 4:0]  writeReg_W,
    input           cw_regWrite_M,
    input           cw_regWrite_W,
    output  [ 1:0]  hz_forwardA_E,
    output  [ 1:0]  hz_forwardB_E,

    input   [ 4:0]  instrRs_D,
    input   [ 4:0]  instrRt_D,
    input   [ 4:0]  writeReg_E,
    input           cw_memToReg_E,
    output          hz_stall_n_F,
    output          hz_stall_n_D,
    output          hz_flush_n_E,

    input           cw_branch_D,
    input           cw_regWrite_E,
    input           cw_memToReg_M,
    output          hz_forwardA_D,
    output          hz_forwardB_D,

    input           cw_cpzToReg_E,
    input           cw_pcSrc_D,
    input           irqRequest_E,
    input           irqRequest_M,
    output          hz_flush_n_D,
    input           cw_cpzExcEret_D,
    input           excSync_D,
    output          hz_cancel_branch_F,
    output          hz_forwardEPC_E,
    output          hz_irq_disable_D,
    output   [ 1:0] hz_forwardEPC_F,
    input           cw_cpzRegWrite_E,
    input           cw_cpzRegWrite_M,
    input   [ 4:0]  instrRd_E,
    input   [ 4:0]  instrRd_M,
    input   [ 2:0]  instrSel_E,
    input   [ 2:0]  instrSel_M
);


    assign hz_forwardA_E =  ( instrRs_E == 5'b0                        ) ? `HZ_FW_NONE : (
                            ( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME   : (
                            ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));

    assign hz_forwardB_E =  ( instrRt_E == 5'b0                        ) ? `HZ_FW_NONE : (
                            ( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME   : (
                            ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE   : `HZ_FW_NONE ));


    wire hz_mem_stall = ( cw_cpzToReg_E || cw_memToReg_E ) && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E );


    assign hz_forwardA_D = ( instrRs_D != 5'b0 && instrRs_D == writeReg_M && cw_regWrite_M );
    assign hz_forwardB_D = ( instrRt_D != 5'b0 && instrRt_D == writeReg_M && cw_regWrite_M );

    wire hz_branch_stall =  cw_branch_D && (
                             ( cw_regWrite_E && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E ))
                          || ( cw_memToReg_M && ( instrRs_D == writeReg_M || instrRt_D == writeReg_M ))
                            );

    wire hz_stall = hz_mem_stall || hz_branch_stall;


    wire   hz_branch_after_irq = cw_pcSrc_D & irqRequest_E;
    assign hz_cancel_branch_F  = hz_branch_after_irq;
    assign hz_forwardEPC_E     = hz_branch_after_irq;


    assign hz_irq_disable_D = irqRequest_E | irqRequest_M;


    assign hz_flush_n_D = ~((cw_pcSrc_D & ~irqRequest_E)
                           | cw_cpzExcEret_D
                           | excSync_D );



    assign hz_forwardEPC_F = ( cw_cpzExcEret_D && cw_cpzRegWrite_E && 
                               instrRd_E  == `CP0_REG_NUM_EPC && 
                               instrSel_E == `CP0_REG_SEL_EPC ) ? `HZ_FW_EF :
                             ( cw_cpzExcEret_D && cw_cpzRegWrite_M && 
                               instrRd_M  == `CP0_REG_NUM_EPC && 
                               instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;


    assign hz_stall_n_F = ~hz_stall;
    assign hz_stall_n_D = ~hz_stall;
    assign hz_flush_n_E = ~hz_stall;

endmodule