data/full_repos/permissive/136510272/projects/version.1.zx80/marsohod2.v
 line:189: before: ")"
1: b"%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/marsohod2.v:78: Cannot find file containing module: 'pll'\npll PLL(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/projects/version.1.zx80,data/full_repos/permissive/136510272/pll\n             data/full_repos/permissive/136510272/projects/version.1.zx80,data/full_repos/permissive/136510272/pll.v\n             data/full_repos/permissive/136510272/projects/version.1.zx80,data/full_repos/permissive/136510272/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/marsohod2.v:134: Cannot find file containing module: 'rom'\nrom  ROM(\n^~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/marsohod2.v:144: Cannot find file containing module: 'ram'\nram  RAM(\n^~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/marsohod2.v:176: Cannot find file containing module: 'processor'\nprocessor CPU(\n^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/marsohod2.v:194: Cannot find file containing module: 'port'\nport PORT(\n^~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/marsohod2.v:206: Cannot find file containing module: 'video'\nvideo VID(\n^~~~~\n%Error: Exiting due to 6 error(s)\n"
module marsohod2(


    input   wire        clk,


    output  wire [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,






    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse   
);


wire        locked;
wire        m_ready = 1'b1;
wire [15:0] o_addr;
wire [7:0]  o_data;
wire        o_wr;





wire [3:0]  cpu_led;
wire [15:0] address;
wire        clock_25;
wire        clock_12;
wire        clock_6;
wire        clock_cpu = clock_25;


reg  wren_100mhz = 1'b0;




pll PLL(
    .inclk0(clk), 
    .c0(clock_25), 
    .c1(clock_12), 
    .c2(clock_6), 
    .locked(locked)
);






wire [13:0] address_vm;


wire [7:0] data8_rom;
wire [7:0] data8_ram;
wire [7:0] data8_vid;
wire [7:0] data8_w;
reg  [7:0] data8;


reg  wren_ram;
reg  wren_distr;
wire wren;


wire        port_clock;
wire [15:0] port_addr;
wire [7:0]  port_data;
wire [7:0]  port_in;
wire [2:0]  vga_border;


always @(posedge clk) begin


    if (clock_cpu) begin    

        wren_100mhz <= 1'b0;
        wren_distr  <= 1'b0;
        
    end

    else if (!clock_cpu && !wren_100mhz) begin

        wren_100mhz <= 1'b1;
        wren_distr  <= wren;

    end

end



rom  ROM(
    
    .clock   (clk),
    .addr_rd (address[13:0]),
    .q       (data8_rom)

);



ram  RAM(

    .clock   (clk),


    .addr_rw (address[13:0]),
    .data    (data8_w),
    .wren    (wren_ram & wren_distr),
    .q_rw    (data8_ram),
    

    .addr_rd (address_vm[13:0]),
    .q       (data8_vid)
);





always @* begin


    if (address < 16'h4000)       begin data8[7:0] = data8_rom[7:0]; wren_ram = 1'b0; end   
                   

    else if (address < 16'h8000)  begin data8[7:0] = data8_ram[7:0]; wren_ram = 1'b1; end

end




processor CPU(

    .clock   (clock_cpu & locked),
    .i_data  (data8),        
    .o_data  (data8_w),
    .o_addr  (address),
    .o_wr    (wren),  
    

    .port_clock (port_clock),
    .port_addr  (port_addr),
    .port_in    (port_in),
    .port_data  (port_data),
);




port PORT(

    .clock      (port_clock),
    .addr       (port_addr),        
    .data_in    (port_data),
    .data_out   (port_in),
    .vga_border (vga_border),
);




video VID(

    .clock      (clock_25),


    .d8_chr     (data8_vid),
    .addr       (address_vm),
    .vga_border (vga_border),        


    .r(vga_red),
    .g(vga_green),
    .b(vga_blue),
    .hs(vga_hs),
    .vs(vga_vs)
);

endmodule
module marsohod2(


    input   wire        clk,


    output  wire [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,






    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse   
);



wire        locked;
wire        m_ready = 1'b1;
wire [15:0] o_addr;
wire [7:0]  o_data;
wire        o_wr;





wire [3:0]  cpu_led;
wire [15:0] address;
wire        clock_25;
wire        clock_12;
wire        clock_6;
wire        clock_cpu = clock_25;


reg  wren_100mhz = 1'b0;




pll PLL(
    .inclk0(clk), 
    .c0(clock_25), 
    .c1(clock_12), 
    .c2(clock_6), 
    .locked(locked)
);






wire [13:0] address_vm;


wire [7:0] data8_rom;
wire [7:0] data8_ram;
wire [7:0] data8_vid;
wire [7:0] data8_w;
reg  [7:0] data8;


reg  wren_ram;
reg  wren_distr;
wire wren;


wire        port_clock;
wire [15:0] port_addr;
wire [7:0]  port_data;
wire [7:0]  port_in;
wire [2:0]  vga_border;


always @(posedge clk) begin


    if (clock_cpu) begin    

        wren_100mhz <= 1'b0;
        wren_distr  <= 1'b0;
        
    end

    else if (!clock_cpu && !wren_100mhz) begin

        wren_100mhz <= 1'b1;
        wren_distr  <= wren;

    end

end



rom  ROM(
    
    .clock   (clk),
    .addr_rd (address[13:0]),
    .q       (data8_rom)

);



ram  RAM(

    .clock   (clk),


    .addr_rw (address[13:0]),
    .data    (data8_w),
    .wren    (wren_ram & wren_distr),
    .q_rw    (data8_ram),
    

    .addr_rd (address_vm[13:0]),
    .q       (data8_vid)
);





always @* begin


    if (address < 16'h4000)       begin data8[7:0] = data8_rom[7:0]; wren_ram = 1'b0; end   
                   

    else if (address < 16'h8000)  begin data8[7:0] = data8_ram[7:0]; wren_ram = 1'b1; end

end




processor CPU(

    .clock   (clock_cpu & locked),
    .i_data  (data8),        
    .o_data  (data8_w),
    .o_addr  (address),
    .o_wr    (wren),  
    

    .port_clock (port_clock),
    .port_addr  (port_addr),
    .port_in    (port_in),
    .port_data  (port_data),
);




port PORT(

    .clock      (port_clock),
    .addr       (port_addr),        
    .data_in    (port_data),
    .data_out   (port_in),
    .vga_border (vga_border),
);




video VID(

    .clock      (clock_25),


    .d8_chr     (data8_vid),
    .addr       (address_vm),
    .vga_border (vga_border),        


    .r(vga_red),
    .g(vga_green),
    .b(vga_blue),
    .hs(vga_hs),
    .vs(vga_vs)
);

endmodule