data/full_repos/permissive/203063855/tb/instrmem_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/203063855/tb/instrmem_tb.v:9: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/203063855/tb/instrmem_tb.v:10: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0,test);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/203063855/tb/instrmem_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n      # 1 addr = 7\'b0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/203063855/tb/instrmem_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n      # 100 addr = 7\'b0000000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/203063855/tb/instrmem_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n      # 100 addr = 7\'b0000001;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/203063855/tb/instrmem_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n      # 100 addr = 7\'b0000010;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/203063855/tb/instrmem_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n      # 100 addr = 7\'b0000011;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/203063855/tb/instrmem_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n      # 100 $finish;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/203063855/tb/instrmem_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = !clk;\n         ^\n%Error: data/full_repos/permissive/203063855/tb/instrmem_tb.v:27: Unsupported or unknown PLI call: $monitor\n    $monitor("At time %t, intr addr = %h, inst = %h", $time, addr, instr);\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  

  reg[6:0] addr;
  reg clk = 0;

  initial
    begin
      $dumpfile("test.vcd");
      $dumpvars(0,test);

      # 1 addr = 7'b0;
      # 100 addr = 7'b0000000;
      # 100 addr = 7'b0000001;
      # 100 addr = 7'b0000010;
      # 100 addr = 7'b0000011;
      # 100 $finish;
  end


  always #1 clk = !clk;

  wire[31:0] instr;
  InstrMem im1 (clk, addr, instr);

  initial
    $monitor("At time %t, intr addr = %h, inst = %h", $time, addr, instr);

endmodule
module test;

  

  reg[6:0] addr;
  reg clk = 0;

  initial
    begin
      $dumpfile("test.vcd");
      $dumpvars(0,test);

      # 1 addr = 7'b0;
      # 100 addr = 7'b0000000;
      # 100 addr = 7'b0000001;
      # 100 addr = 7'b0000010;
      # 100 addr = 7'b0000011;
      # 100 $finish;
  end


  always #1 clk = !clk;

  wire[31:0] instr;
  InstrMem im1 (clk, addr, instr);

  initial
    $monitor("At time %t, intr addr = %h, inst = %h", $time, addr, instr);

endmodule