data/full_repos/permissive/174155074/combinational-logic/data-operators/full-adder/full-adder-tb.v
1: b'%Error: data/full_repos/permissive/174155074/combinational-logic/data-operators/full-adder/full-adder-tb.v:20: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("full-adder-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/combinational-logic/data-operators/full-adder/full-adder-tb.v:21: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, full_adder_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/combinational-logic/data-operators/full-adder/full-adder-tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module full_adder_tb;


reg     A, B, CIN;
wire    SUM, COUT;
integer i;


full_adder uut(
    .a(A), .b(B), .cin(CIN),
    .sum(SUM), .cout(COUT)
);


initial begin
    $dumpfile("full-adder-tb.vcd");
    $dumpvars(0, full_adder_tb);
end


initial begin
    $display("test start");
    A = 0;
    B = 0;
    CIN = 0;

    for (i = 0; i < 8; i = i + 1) begin
        {A, B, CIN} = i;
        #10;
    end
    
    $display("test complete");
    $finish;
end

endmodule
module full_adder_tb;



reg     A, B, CIN;
wire    SUM, COUT;
integer i;


full_adder uut(
    .a(A), .b(B), .cin(CIN),
    .sum(SUM), .cout(COUT)
);


initial begin
    $dumpfile("full-adder-tb.vcd");
    $dumpvars(0, full_adder_tb);
end


initial begin
    $display("test start");
    A = 0;
    B = 0;
    CIN = 0;

    for (i = 0; i < 8; i = i + 1) begin
        {A, B, CIN} = i;
        #10;
    end
    
    $display("test complete");
    $finish;
end

endmodule