data/full_repos/permissive/119209630/src/mojo_top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/119209630/src/mojo_top.v:40: Cannot find file containing module: 'cpu_example'\n cpu_example cpu (\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/119209630/src,data/full_repos/permissive/119209630/cpu_example\n             data/full_repos/permissive/119209630/src,data/full_repos/permissive/119209630/cpu_example.v\n             data/full_repos/permissive/119209630/src,data/full_repos/permissive/119209630/cpu_example.sv\n             cpu_example\n             cpu_example.v\n             cpu_example.sv\n             obj_dir/cpu_example\n             obj_dir/cpu_example.v\n             obj_dir/cpu_example.sv\n%Error: Exiting due to 1 error(s)\n"
module mojo_top(

		input clk,

		input rst_n,

		input cclk,

		output[7:0]led,

		output spi_miso,
		input spi_ss,
		input spi_mosi,
		input spi_sck,

		output [3:0] spi_channel,

		input avr_tx,
		output avr_rx,
		input avr_rx_busy
	);

	wire rst = ~rst_n;


	assign spi_miso = 1'bz;
	assign avr_rx = 1'bz;
	assign spi_channel = 4'bzzzz;


	wire [7:0] address;
	reg [7:0] din;
	wire [7:0] dout;
	wire write;
	wire read;

	reg [7:0] led_d, led_q;
	assign led = led_q;

	cpu_example cpu (
		.clk(clk),
		.rst(rst),
		.dout(dout),
		.din(din),
		.write(write),
		.read(read),
		.addr(address)
	);

	always @(*) begin
		led_d = led_q;
		din = 8'hxx;

		if (address == 8'd128) begin
			if (write)
				led_d = dout;
			if (read)
				din = led_q;
		end
	end

	always @(posedge clk) begin
		led_q <= led_d;
	end

endmodule
module mojo_top(

		input clk,

		input rst_n,

		input cclk,

		output[7:0]led,

		output spi_miso,
		input spi_ss,
		input spi_mosi,
		input spi_sck,

		output [3:0] spi_channel,

		input avr_tx,
		output avr_rx,
		input avr_rx_busy
	);


	wire rst = ~rst_n;


	assign spi_miso = 1'bz;
	assign avr_rx = 1'bz;
	assign spi_channel = 4'bzzzz;


	wire [7:0] address;
	reg [7:0] din;
	wire [7:0] dout;
	wire write;
	wire read;

	reg [7:0] led_d, led_q;
	assign led = led_q;

	cpu_example cpu (
		.clk(clk),
		.rst(rst),
		.dout(dout),
		.din(din),
		.write(write),
		.read(read),
		.addr(address)
	);

	always @(*) begin
		led_d = led_q;
		din = 8'hxx;

		if (address == 8'd128) begin
			if (write)
				led_d = dout;
			if (read)
				din = led_q;
		end
	end

	always @(posedge clk) begin
		led_q <= led_d;
	end

endmodule