data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv
 line:38: before: "["
1: b'%Error: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:69: Cannot find file containing module: \'acl_iface_address_to_bankaddress\'\n    acl_iface_address_to_bankaddress #(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter,data/full_repos/permissive/205229557/acl_iface_address_to_bankaddress\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter,data/full_repos/permissive/205229557/acl_iface_address_to_bankaddress.v\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter,data/full_repos/permissive/205229557/acl_iface_address_to_bankaddress.sv\n             acl_iface_address_to_bankaddress\n             acl_iface_address_to_bankaddress.v\n             acl_iface_address_to_bankaddress.sv\n             obj_dir/acl_iface_address_to_bankaddress\n             obj_dir/acl_iface_address_to_bankaddress.v\n             obj_dir/acl_iface_address_to_bankaddress.sv\n%Error: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:120: Cannot find file containing module: \'acl_iface_ll_fifo\'\n        acl_iface_ll_fifo #(\n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:152: Cannot find file containing module: \'scfifo\'\n            scfifo #(\n            ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:196: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                                                                                          : ... In instance mem_router_reorder\n                    df_free <= READ_DATA_FIFO_DEPTH - 1;\n                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:198: Operator ADD expects 3 bits on the RHS, but RHS\'s VARREF \'incr_df_free\' generates 1 bits.\n                                                                                                                                                          : ... In instance mem_router_reorder\n                    df_free <= df_free + incr_df_free - ((decr_df_free) ? m_arb_burstcount : 1\'b0);\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:198: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s VARREF \'m_arb_burstcount\' generates 1 bits.\n                                                                                                                                                          : ... In instance mem_router_reorder\n                    df_free <= df_free + incr_df_free - ((decr_df_free) ? m_arb_burstcount : 1\'b0);\n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:198: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                          : ... In instance mem_router_reorder\n                    df_free <= df_free + incr_df_free - ((decr_df_free) ? m_arb_burstcount : 1\'b0);\n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:275: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'ack_counter_incr\' generates 4 bits.\n                                                                                                                                                          : ... In instance mem_router_reorder\n                ack_counter <= ack_counter + ack_counter_incr - decr_ack_counter;\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:275: Operator SUB expects 15 bits on the RHS, but RHS\'s VARREF \'decr_ack_counter\' generates 1 bits.\n                                                                                                                                                          : ... In instance mem_router_reorder\n                ack_counter <= ack_counter + ack_counter_incr - decr_ack_counter;\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:287: Operator ADD expects 4 bits on the RHS, but RHS\'s ARRAYSEL generates 1 bits.\n                                                                                                                                                          : ... In instance mem_router_reorder\n                ack_counter_incr += b_wrp_ack[wrp_b];\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:293: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                                                                                          : ... In instance mem_router_reorder\n                ack_free <= WRITE_ACK_FIFO_DEPTH - 1;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:295: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'incr_ack_free\' generates 1 bits.\n                                                                                                                                                          : ... In instance mem_router_reorder\n                ack_free <= ack_free + incr_ack_free - decr_ack_free;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/iface/ip/mem_splitter/mem_router_reorder.sv:295: Operator SUB expects 15 bits on the RHS, but RHS\'s VARREF \'decr_ack_free\' generates 1 bits.\n                                                                                                                                                          : ... In instance mem_router_reorder\n                ack_free <= ack_free + incr_ack_free - decr_ack_free;\n                                                     ^\n%Error: Exiting due to 3 error(s), 10 warning(s)\n'
module mem_router_reorder #(    
    parameter integer DATA_W = 256,
    parameter integer BURSTCOUNT_W = 1,
    parameter integer ADDRESS_W = 32,
    parameter integer BYTEENA_W = DATA_W / 8,

    parameter integer NUM_BANKS = 8,
    parameter integer BANK_SEL_BIT = ADDRESS_W-$clog2(NUM_BANKS),

    parameter integer BANK_MAX_PENDING_READS = 2*2**BURSTCOUNT_W-4,
    parameter integer BANK_MAX_PENDING_WRITES = 2047
)
(
    input logic clock,
    input logic resetn,


    input logic [NUM_BANKS-1:0] bank_select,


    input logic m_arb_request,
    input logic m_arb_read,
    input logic m_arb_write,
    input logic [DATA_W-1:0] m_arb_writedata,
    input logic [BURSTCOUNT_W-1:0] m_arb_burstcount,
    input logic [ADDRESS_W-1:0] m_arb_address,
    input logic [BYTEENA_W-1:0] m_arb_byteenable,

    output logic m_arb_stall,

    output logic m_wrp_ack,

    output logic m_rrp_datavalid,
    output logic [DATA_W-1:0] m_rrp_data,


    output logic b_arb_request [NUM_BANKS],
    output logic b_arb_read [NUM_BANKS],
    output logic b_arb_write [NUM_BANKS],
    output logic [DATA_W-1:0] b_arb_writedata [NUM_BANKS],
    output logic [BURSTCOUNT_W-1:0] b_arb_burstcount [NUM_BANKS],
    output logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] b_arb_address [NUM_BANKS],
    output logic [BYTEENA_W-1:0] b_arb_byteenable [NUM_BANKS],

    input logic b_arb_stall [NUM_BANKS],

    input logic b_wrp_ack [NUM_BANKS],

    input logic b_rrp_datavalid [NUM_BANKS],
    input logic [DATA_W-1:0] b_rrp_data [NUM_BANKS]
);


    localparam READ_DATA_FIFO_DEPTH = BANK_MAX_PENDING_READS + 3 + 1;


    localparam READ_BANK_SELECT_FIFO_DEPTH = NUM_BANKS > READ_DATA_FIFO_DEPTH ? NUM_BANKS : READ_DATA_FIFO_DEPTH;


    localparam WRITE_ACK_FIFO_DEPTH = BANK_MAX_PENDING_WRITES * NUM_BANKS + 1;

    genvar i;

    logic [NUM_BANKS-1:0] m_arb_bank_sel;
    logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] m_arb_bank_address;


    acl_iface_address_to_bankaddress #(
      .ADDRESS_W( ADDRESS_W ),
      .NUM_BANKS( NUM_BANKS ),
      .BANK_SEL_BIT( BANK_SEL_BIT))
      a2b (
        .address(m_arb_address),
        .bank_sel_1hot(m_arb_bank_sel),
        .bank_address(m_arb_bank_address));


    generate
    begin:req
        integer req_b;
        logic stall;

        always_comb
        begin
            stall = 1'b0;

            for( req_b = 0; req_b < NUM_BANKS; req_b = req_b + 1 )
            begin:bank
                b_arb_request[req_b] = m_arb_request & m_arb_bank_sel[req_b] & ~(rrp.stall | wrp.stall);
                b_arb_read[req_b] = m_arb_read & m_arb_bank_sel[req_b] & ~(rrp.stall | wrp.stall);
                b_arb_write[req_b] = m_arb_write & m_arb_bank_sel[req_b] & ~(rrp.stall | wrp.stall);
                b_arb_writedata[req_b] = m_arb_writedata;
                b_arb_burstcount[req_b] = m_arb_burstcount;
                b_arb_address[req_b] = m_arb_bank_address;
                b_arb_byteenable[req_b] = m_arb_byteenable;

                stall |= b_arb_stall[req_b] & m_arb_bank_sel[req_b];
            end
        end
    end
    endgenerate





    generate
    begin:rrp
        integer rrp_b;
        logic stall;

        logic [NUM_BANKS-1:0] bs_in, bs_out, bank_df_valid, bank_df_no_free;
        logic [BURSTCOUNT_W-1:0] bs_burstcount, bs_burstcounter;
        logic bs_read, bs_write, bs_full, bs_empty, bs_valid, bs_doneburst;
        logic [DATA_W-1:0] bank_df_out [NUM_BANKS];



        acl_iface_ll_fifo #(
            .DEPTH(READ_BANK_SELECT_FIFO_DEPTH),
            .WIDTH(BURSTCOUNT_W+NUM_BANKS)
        )
        bs_fifo (
            .clk( clock ),
            .reset( ~resetn ),
            .data_in( {m_arb_burstcount,bs_in} ),
            .write( bs_write ),
            .data_out( {bs_burstcount,bs_out} ),
            .read( bs_doneburst && bs_read ),
            .empty( bs_empty ),
            .full( bs_full )
        );

        assign bs_doneburst = (bs_burstcounter == bs_burstcount);
        always @( posedge clock or negedge resetn )
          if (!resetn)
            bs_burstcounter <= 'b01;
          else if (bs_doneburst && bs_read)
            bs_burstcounter <= 'b01;
          else if (bs_read)
            bs_burstcounter <= bs_burstcounter + 'b01;



        for( i = 0; i < NUM_BANKS; i = i + 1 )
        begin:bank

            logic [DATA_W-1:0] df_in, df_out;
            logic df_read, df_write, df_full, df_empty;

            scfifo #(
                .lpm_width( DATA_W ),
                .lpm_widthu( $clog2(READ_DATA_FIFO_DEPTH) ),
                .lpm_numwords( READ_DATA_FIFO_DEPTH ),
                .add_ram_output_register( "ON" ),
                .lpm_showahead( "ON" ),
                .intended_device_family( "stratixiv" )
            )
            data_fifo (
                .aclr( ~resetn ),
                .clock( clock ),
                .empty( df_empty ),
                .full( df_full ),
                .data( df_in ),
                .q( df_out ),
                .wrreq( df_write ),
                .rdreq( df_read ),
                .sclr(),
                .usedw(),
                .almost_full(),
                .almost_empty()
            );








            logic [$clog2(READ_DATA_FIFO_DEPTH):0] df_free;
            logic incr_df_free, decr_df_free;


            assign df_in = b_rrp_data[i];
            assign df_write = b_rrp_datavalid[i];
            assign df_read = bs_valid & bs_out[i] & bank_df_valid[i];

            assign bank_df_valid[i] = ~df_empty;
            assign bank_df_out[i] = df_out;


            always @( posedge clock or negedge resetn )
                if( !resetn )
                    df_free <= READ_DATA_FIFO_DEPTH - 1;
                else
                    df_free <= df_free + incr_df_free - ((decr_df_free) ? m_arb_burstcount : 1'b0);

            assign incr_df_free = df_read;
            assign decr_df_free = m_arb_read & bs_in[i] & ~(req.stall | bs_full | bank_df_no_free[i]);



            assign bank_df_no_free[i] = df_free < (2**(BURSTCOUNT_W-1));

        end


        assign bs_in = m_arb_bank_sel;
        assign bs_write = m_arb_read & ~(req.stall | stall);
        assign bs_read = bs_valid & |(bs_out & bank_df_valid);
        assign bs_valid = ~bs_empty;



        assign stall = m_arb_read & (bs_full | |(bs_in & bank_df_no_free));


        logic [DATA_W-1:0] rrp_data;
        always_comb
        begin
            rrp_data = '0;

            for( rrp_b = 0; rrp_b < NUM_BANKS; rrp_b = rrp_b + 1 )
                rrp_data |= bs_out[rrp_b] ? bank_df_out[rrp_b] : '0;
        end

        always @( posedge clock or negedge resetn )
            if( !resetn )
                m_rrp_datavalid <= 1'b0;
            else
                m_rrp_datavalid <= bs_read;

        always @( posedge clock )
            m_rrp_data <= rrp_data;
    end
    endgenerate



    generate
    begin:wrp
        integer wrp_b;
        logic stall;








        logic [$clog2(WRITE_ACK_FIFO_DEPTH):0] ack_counter;
        logic decr_ack_counter;
        logic [$clog2(NUM_BANKS + 1)-1:0] ack_counter_incr;
        logic has_acks;








        logic [$clog2(WRITE_ACK_FIFO_DEPTH):0] ack_free;
        logic incr_ack_free, decr_ack_free;
        logic ack_no_free;


        always @( posedge clock or negedge resetn )
            if( !resetn )
                ack_counter <= {$bits(ack_counter){1'b1}};
            else
                ack_counter <= ack_counter + ack_counter_incr - decr_ack_counter;

        assign decr_ack_counter = has_acks;
        assign has_acks = ~ack_counter[$bits(ack_counter) - 1];

        always_comb
        begin


            ack_counter_incr = '0;

            for( wrp_b = 0; wrp_b < NUM_BANKS; wrp_b = wrp_b + 1 )
                ack_counter_incr += b_wrp_ack[wrp_b];
        end


        always @( posedge clock or negedge resetn )
            if( !resetn )
                ack_free <= WRITE_ACK_FIFO_DEPTH - 1;
            else
                ack_free <= ack_free + incr_ack_free - decr_ack_free;

        assign incr_ack_free = decr_ack_counter;
        assign decr_ack_free = m_arb_write & ~(req.stall | ack_no_free);
        assign ack_no_free = ack_free[$bits(ack_free) - 1];



        assign stall = m_arb_write & ack_no_free;


        assign m_wrp_ack = has_acks;
    end
    endgenerate


    assign m_arb_stall = req.stall | rrp.stall | wrp.stall;

endmodule
module mem_router_reorder #(    
    parameter integer DATA_W = 256,
    parameter integer BURSTCOUNT_W = 1,
    parameter integer ADDRESS_W = 32,
    parameter integer BYTEENA_W = DATA_W / 8,

    parameter integer NUM_BANKS = 8,
    parameter integer BANK_SEL_BIT = ADDRESS_W-$clog2(NUM_BANKS),

    parameter integer BANK_MAX_PENDING_READS = 2*2**BURSTCOUNT_W-4,
    parameter integer BANK_MAX_PENDING_WRITES = 2047
)
(
    input logic clock,
    input logic resetn,


    input logic [NUM_BANKS-1:0] bank_select,


    input logic m_arb_request,
    input logic m_arb_read,
    input logic m_arb_write,
    input logic [DATA_W-1:0] m_arb_writedata,
    input logic [BURSTCOUNT_W-1:0] m_arb_burstcount,
    input logic [ADDRESS_W-1:0] m_arb_address,
    input logic [BYTEENA_W-1:0] m_arb_byteenable,

    output logic m_arb_stall,

    output logic m_wrp_ack,

    output logic m_rrp_datavalid,
    output logic [DATA_W-1:0] m_rrp_data,


    output logic b_arb_request [NUM_BANKS],
    output logic b_arb_read [NUM_BANKS],
    output logic b_arb_write [NUM_BANKS],
    output logic [DATA_W-1:0] b_arb_writedata [NUM_BANKS],
    output logic [BURSTCOUNT_W-1:0] b_arb_burstcount [NUM_BANKS],
    output logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] b_arb_address [NUM_BANKS],
    output logic [BYTEENA_W-1:0] b_arb_byteenable [NUM_BANKS],

    input logic b_arb_stall [NUM_BANKS],

    input logic b_wrp_ack [NUM_BANKS],

    input logic b_rrp_datavalid [NUM_BANKS],
    input logic [DATA_W-1:0] b_rrp_data [NUM_BANKS]
);



    localparam READ_DATA_FIFO_DEPTH = BANK_MAX_PENDING_READS + 3 + 1;


    localparam READ_BANK_SELECT_FIFO_DEPTH = NUM_BANKS > READ_DATA_FIFO_DEPTH ? NUM_BANKS : READ_DATA_FIFO_DEPTH;


    localparam WRITE_ACK_FIFO_DEPTH = BANK_MAX_PENDING_WRITES * NUM_BANKS + 1;

    genvar i;

    logic [NUM_BANKS-1:0] m_arb_bank_sel;
    logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] m_arb_bank_address;


    acl_iface_address_to_bankaddress #(
      .ADDRESS_W( ADDRESS_W ),
      .NUM_BANKS( NUM_BANKS ),
      .BANK_SEL_BIT( BANK_SEL_BIT))
      a2b (
        .address(m_arb_address),
        .bank_sel_1hot(m_arb_bank_sel),
        .bank_address(m_arb_bank_address));


    generate
    begin:req
        integer req_b;
        logic stall;

        always_comb
        begin
            stall = 1'b0;

            for( req_b = 0; req_b < NUM_BANKS; req_b = req_b + 1 )
            begin:bank
                b_arb_request[req_b] = m_arb_request & m_arb_bank_sel[req_b] & ~(rrp.stall | wrp.stall);
                b_arb_read[req_b] = m_arb_read & m_arb_bank_sel[req_b] & ~(rrp.stall | wrp.stall);
                b_arb_write[req_b] = m_arb_write & m_arb_bank_sel[req_b] & ~(rrp.stall | wrp.stall);
                b_arb_writedata[req_b] = m_arb_writedata;
                b_arb_burstcount[req_b] = m_arb_burstcount;
                b_arb_address[req_b] = m_arb_bank_address;
                b_arb_byteenable[req_b] = m_arb_byteenable;

                stall |= b_arb_stall[req_b] & m_arb_bank_sel[req_b];
            end
        end
    end
    endgenerate





    generate
    begin:rrp
        integer rrp_b;
        logic stall;

        logic [NUM_BANKS-1:0] bs_in, bs_out, bank_df_valid, bank_df_no_free;
        logic [BURSTCOUNT_W-1:0] bs_burstcount, bs_burstcounter;
        logic bs_read, bs_write, bs_full, bs_empty, bs_valid, bs_doneburst;
        logic [DATA_W-1:0] bank_df_out [NUM_BANKS];



        acl_iface_ll_fifo #(
            .DEPTH(READ_BANK_SELECT_FIFO_DEPTH),
            .WIDTH(BURSTCOUNT_W+NUM_BANKS)
        )
        bs_fifo (
            .clk( clock ),
            .reset( ~resetn ),
            .data_in( {m_arb_burstcount,bs_in} ),
            .write( bs_write ),
            .data_out( {bs_burstcount,bs_out} ),
            .read( bs_doneburst && bs_read ),
            .empty( bs_empty ),
            .full( bs_full )
        );

        assign bs_doneburst = (bs_burstcounter == bs_burstcount);
        always @( posedge clock or negedge resetn )
          if (!resetn)
            bs_burstcounter <= 'b01;
          else if (bs_doneburst && bs_read)
            bs_burstcounter <= 'b01;
          else if (bs_read)
            bs_burstcounter <= bs_burstcounter + 'b01;



        for( i = 0; i < NUM_BANKS; i = i + 1 )
        begin:bank

            logic [DATA_W-1:0] df_in, df_out;
            logic df_read, df_write, df_full, df_empty;

            scfifo #(
                .lpm_width( DATA_W ),
                .lpm_widthu( $clog2(READ_DATA_FIFO_DEPTH) ),
                .lpm_numwords( READ_DATA_FIFO_DEPTH ),
                .add_ram_output_register( "ON" ),
                .lpm_showahead( "ON" ),
                .intended_device_family( "stratixiv" )
            )
            data_fifo (
                .aclr( ~resetn ),
                .clock( clock ),
                .empty( df_empty ),
                .full( df_full ),
                .data( df_in ),
                .q( df_out ),
                .wrreq( df_write ),
                .rdreq( df_read ),
                .sclr(),
                .usedw(),
                .almost_full(),
                .almost_empty()
            );








            logic [$clog2(READ_DATA_FIFO_DEPTH):0] df_free;
            logic incr_df_free, decr_df_free;


            assign df_in = b_rrp_data[i];
            assign df_write = b_rrp_datavalid[i];
            assign df_read = bs_valid & bs_out[i] & bank_df_valid[i];

            assign bank_df_valid[i] = ~df_empty;
            assign bank_df_out[i] = df_out;


            always @( posedge clock or negedge resetn )
                if( !resetn )
                    df_free <= READ_DATA_FIFO_DEPTH - 1;
                else
                    df_free <= df_free + incr_df_free - ((decr_df_free) ? m_arb_burstcount : 1'b0);

            assign incr_df_free = df_read;
            assign decr_df_free = m_arb_read & bs_in[i] & ~(req.stall | bs_full | bank_df_no_free[i]);



            assign bank_df_no_free[i] = df_free < (2**(BURSTCOUNT_W-1));

        end


        assign bs_in = m_arb_bank_sel;
        assign bs_write = m_arb_read & ~(req.stall | stall);
        assign bs_read = bs_valid & |(bs_out & bank_df_valid);
        assign bs_valid = ~bs_empty;



        assign stall = m_arb_read & (bs_full | |(bs_in & bank_df_no_free));


        logic [DATA_W-1:0] rrp_data;
        always_comb
        begin
            rrp_data = '0;

            for( rrp_b = 0; rrp_b < NUM_BANKS; rrp_b = rrp_b + 1 )
                rrp_data |= bs_out[rrp_b] ? bank_df_out[rrp_b] : '0;
        end

        always @( posedge clock or negedge resetn )
            if( !resetn )
                m_rrp_datavalid <= 1'b0;
            else
                m_rrp_datavalid <= bs_read;

        always @( posedge clock )
            m_rrp_data <= rrp_data;
    end
    endgenerate



    generate
    begin:wrp
        integer wrp_b;
        logic stall;








        logic [$clog2(WRITE_ACK_FIFO_DEPTH):0] ack_counter;
        logic decr_ack_counter;
        logic [$clog2(NUM_BANKS + 1)-1:0] ack_counter_incr;
        logic has_acks;








        logic [$clog2(WRITE_ACK_FIFO_DEPTH):0] ack_free;
        logic incr_ack_free, decr_ack_free;
        logic ack_no_free;


        always @( posedge clock or negedge resetn )
            if( !resetn )
                ack_counter <= {$bits(ack_counter){1'b1}};
            else
                ack_counter <= ack_counter + ack_counter_incr - decr_ack_counter;

        assign decr_ack_counter = has_acks;
        assign has_acks = ~ack_counter[$bits(ack_counter) - 1];

        always_comb
        begin


            ack_counter_incr = '0;

            for( wrp_b = 0; wrp_b < NUM_BANKS; wrp_b = wrp_b + 1 )
                ack_counter_incr += b_wrp_ack[wrp_b];
        end


        always @( posedge clock or negedge resetn )
            if( !resetn )
                ack_free <= WRITE_ACK_FIFO_DEPTH - 1;
            else
                ack_free <= ack_free + incr_ack_free - decr_ack_free;

        assign incr_ack_free = decr_ack_counter;
        assign decr_ack_free = m_arb_write & ~(req.stall | ack_no_free);
        assign ack_no_free = ack_free[$bits(ack_free) - 1];



        assign stall = m_arb_write & ack_no_free;


        assign m_wrp_ack = has_acks;
    end
    endgenerate


    assign m_arb_stall = req.stall | rrp.stall | wrp.stall;

endmodule