data/full_repos/permissive/124803629/src/Pipeline_CPU/UART.v
1: b'%Warning-WIDTH: data/full_repos/permissive/124803629/src/Pipeline_CPU/UART.v:55: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                                               : ... In instance UART.UART_Receiver_1\n      rx_data[cnt_catch]<=uart_rx;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module UART(reset, sysclk, clk, rd, wr, addr, wdata, rdata, UART_RX, UART_TX, RX_IRQ, TX_IRQ);
input sysclk, reset, clk, rd, wr, UART_RX;
input [31:0] addr, wdata;
output UART_TX, RX_IRQ, TX_IRQ;
output reg [31:0] rdata;
wire rx_status, tx_status, tx_over;
wire[7:0] rx_data;
reg[7:0] UART_RXD, UART_TXD;
reg[4:0] UART_CON;
reg tx_en; 


always @(*) begin
	if(rd) begin
		case(addr)
			32'h4000_0018: rdata = {24'd0, UART_TXD};
			32'h4000_001c: rdata = {24'd0, UART_RXD};
			32'h4000_0020: rdata = {27'd0, UART_CON};
			default: rdata = 32'd0;
		endcase
	end
	else
		rdata = 32'd0;
end

always @(posedge clk or negedge reset) begin
	if(~reset) begin
		UART_RXD <= 8'd0;
		UART_TXD <= 8'd0;
		UART_CON <= 5'd0;
		tx_en <= 0;
	end
	else begin
		

		if(rx_status) begin
			UART_RXD <= rx_data;
			UART_CON[3] <= 1'b1;
		end
		

		if(UART_CON[4] && tx_status) begin
			UART_CON[2] <= 1'b1;
		end
		UART_CON[4] <= ~tx_status;
		

		if(rd && (addr == 32'h4000_0020)) begin
			UART_CON[2] <= 1'b0;
			UART_CON[3] <= 1'b0;
		end
		

		if(wr) begin
			case(addr)
				32'h4000_0018: begin
					UART_TXD <= wdata[7:0];
					tx_en <= 1;
				end
				32'h4000_0020: UART_CON[1:0] <= wdata[1:0];
				default: ;
			endcase
		end
		if(tx_en)
			tx_en <= 0;
	end
end


assign RX_IRQ = UART_CON[1] && UART_CON[3];
assign TX_IRQ = UART_CON[0] && UART_CON[2];

UART_Receiver UART_Receiver_1(.uart_rx(UART_RX), .sysclk(sysclk), .rx_data(rx_data), .rx_status(rx_status), .rx_LoadFinish(UART_CON[3]), .reset(reset));

UART_Sender UART_Sender_1(.tx_data(UART_TXD), .tx_en(tx_en), .sysclk(sysclk), .tx_status(tx_status), .uart_tx(UART_TX), .reset(reset));

endmodule
module UART(reset, sysclk, clk, rd, wr, addr, wdata, rdata, UART_RX, UART_TX, RX_IRQ, TX_IRQ);

input sysclk, reset, clk, rd, wr, UART_RX;
input [31:0] addr, wdata;
output UART_TX, RX_IRQ, TX_IRQ;
output reg [31:0] rdata;
wire rx_status, tx_status, tx_over;
wire[7:0] rx_data;
reg[7:0] UART_RXD, UART_TXD;
reg[4:0] UART_CON;
reg tx_en; 


always @(*) begin
	if(rd) begin
		case(addr)
			32'h4000_0018: rdata = {24'd0, UART_TXD};
			32'h4000_001c: rdata = {24'd0, UART_RXD};
			32'h4000_0020: rdata = {27'd0, UART_CON};
			default: rdata = 32'd0;
		endcase
	end
	else
		rdata = 32'd0;
end

always @(posedge clk or negedge reset) begin
	if(~reset) begin
		UART_RXD <= 8'd0;
		UART_TXD <= 8'd0;
		UART_CON <= 5'd0;
		tx_en <= 0;
	end
	else begin
		

		if(rx_status) begin
			UART_RXD <= rx_data;
			UART_CON[3] <= 1'b1;
		end
		

		if(UART_CON[4] && tx_status) begin
			UART_CON[2] <= 1'b1;
		end
		UART_CON[4] <= ~tx_status;
		

		if(rd && (addr == 32'h4000_0020)) begin
			UART_CON[2] <= 1'b0;
			UART_CON[3] <= 1'b0;
		end
		

		if(wr) begin
			case(addr)
				32'h4000_0018: begin
					UART_TXD <= wdata[7:0];
					tx_en <= 1;
				end
				32'h4000_0020: UART_CON[1:0] <= wdata[1:0];
				default: ;
			endcase
		end
		if(tx_en)
			tx_en <= 0;
	end
end


assign RX_IRQ = UART_CON[1] && UART_CON[3];
assign TX_IRQ = UART_CON[0] && UART_CON[2];

UART_Receiver UART_Receiver_1(.uart_rx(UART_RX), .sysclk(sysclk), .rx_data(rx_data), .rx_status(rx_status), .rx_LoadFinish(UART_CON[3]), .reset(reset));

UART_Sender UART_Sender_1(.tx_data(UART_TXD), .tx_en(tx_en), .sysclk(sysclk), .tx_status(tx_status), .uart_tx(UART_TX), .reset(reset));

endmodule