data/full_repos/permissive/200478172/source/II.v
1: b'%Warning-WIDTH: data/full_repos/permissive/200478172/source/II.v:32: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 30 bits.\n                                                                   : ... In instance II\n        temp<={a,b<<2};\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module II(
    input [3:0] a,
    input [25:0] b,
    input ctr,
    output [31:0] r
    );
    reg [31:0] temp;
    always@(*)begin
        if(ctr==1)begin
        temp<={a,b<<2};
        end
    end
    assign r = temp;
endmodule
module II(
    input [3:0] a,
    input [25:0] b,
    input ctr,
    output [31:0] r
    );

    reg [31:0] temp;
    always@(*)begin
        if(ctr==1)begin
        temp<={a,b<<2};
        end
    end
    assign r = temp;
endmodule