data/full_repos/permissive/201196900/Tutorial/04_mux4x1.v
data/verilator_xmls/63f8d4c0-e28b-44d1-aca5-8576c91e1f96.xml
module mux4x1(input clk, input [7:0]a, input [7:0]b, input [7:0]c, input [7:0]d, input [1:0]select, output reg [7:0]q);

reg [7:0] q_next;

always @(posedge clk)begin
    q<=q_next;
end

always @(*)begin
    q_next=q;
    case(select)
        2'b00:q_next=a;
        2'b01:q_next=b;
        2'b10:q_next=c;
        2'b11:q_next=d;   
    endcase
end

endmodule
module mux4x1(input clk, input [7:0]a, input [7:0]b, input [7:0]c, input [7:0]d, input [1:0]select, output reg [7:0]q);


reg [7:0] q_next;

always @(posedge clk)begin
    q<=q_next;
end

always @(*)begin
    q_next=q;
    case(select)
        2'b00:q_next=a;
        2'b01:q_next=b;
        2'b10:q_next=c;
        2'b11:q_next=d;   
    endcase
end

endmodule