data/full_repos/permissive/141038711/hdl/apb_edgeirq.v
data/verilator_xmls/1858800b-e280-4bcf-bd69-e28ee6ce6895.xml
module apb_edgeirq (

   input             reset_n,
   input             enable,


   input             pclk,            
   input      [ 2:0] paddr,
   input             pwrite,
   input             psel,
   input             penable,
   input      [31:0] pwdata,
   output reg [31:0] prdata,
   output            pready,
   output            pslverr,
   output            irq,


   input      [ 3:0] irq_posedge
);

reg  [3:0] edge_detect;
reg  [3:0] irq_control;
reg  [3:0] irq_edgeseen;
wire [3:0] irq_pending;

wire apb_write = psel & penable & pwrite;
wire apb_read  = psel & ~pwrite;

   assign pready  = 1'b1;
   assign pslverr = 1'b0;
   
   assign irq_pending = irq_edgeseen & irq_control;
   assign irq = |irq_pending;
   
   always @(posedge pclk or negedge reset_n)
   begin : rr
      integer b;
      if (!reset_n)
      begin
         edge_detect  <= 4'h0;
         irq_edgeseen <= 4'h0;
         irq_control  <= 4'h0;
         prdata    <= 32'h0;
      end
      else if (enable)
      begin
         
         edge_detect <= irq_posedge;
         
         for (b=0; b<4; b=b+1)
         begin

            if (~edge_detect[b] & irq_posedge[b])
               irq_edgeseen[b] <= 1'b1;
            else
            begin

               if (apb_write && (paddr==3'h4) && pwdata[b])
                  irq_edgeseen[b] <= 1'b0;
            end
         end
         
         if (apb_write)
         begin
            case (paddr)
            3'h0  : irq_control <= pwdata[3:0];

           endcase
         end
         


         if (apb_read)
         begin
            case (paddr)
            3'h0 : prdata <= {28'h0,irq_control};
            3'h4 : prdata <= {24'h0,irq_pending,irq_edgeseen};
            endcase
         end
         else
            prdata <= 32'h0;
      end
   end
   
endmodule
module apb_edgeirq (

   input             reset_n,
   input             enable,


   input             pclk,            
   input      [ 2:0] paddr,
   input             pwrite,
   input             psel,
   input             penable,
   input      [31:0] pwdata,
   output reg [31:0] prdata,
   output            pready,
   output            pslverr,
   output            irq,


   input      [ 3:0] irq_posedge
);


reg  [3:0] edge_detect;
reg  [3:0] irq_control;
reg  [3:0] irq_edgeseen;
wire [3:0] irq_pending;

wire apb_write = psel & penable & pwrite;
wire apb_read  = psel & ~pwrite;

   assign pready  = 1'b1;
   assign pslverr = 1'b0;
   
   assign irq_pending = irq_edgeseen & irq_control;
   assign irq = |irq_pending;
   
   always @(posedge pclk or negedge reset_n)
   begin : rr
      integer b;
      if (!reset_n)
      begin
         edge_detect  <= 4'h0;
         irq_edgeseen <= 4'h0;
         irq_control  <= 4'h0;
         prdata    <= 32'h0;
      end
      else if (enable)
      begin
         
         edge_detect <= irq_posedge;
         
         for (b=0; b<4; b=b+1)
         begin

            if (~edge_detect[b] & irq_posedge[b])
               irq_edgeseen[b] <= 1'b1;
            else
            begin

               if (apb_write && (paddr==3'h4) && pwdata[b])
                  irq_edgeseen[b] <= 1'b0;
            end
         end
         
         if (apb_write)
         begin
            case (paddr)
            3'h0  : irq_control <= pwdata[3:0];

           endcase
         end
         


         if (apb_read)
         begin
            case (paddr)
            3'h0 : prdata <= {28'h0,irq_control};
            3'h4 : prdata <= {24'h0,irq_pending,irq_edgeseen};
            endcase
         end
         else
            prdata <= 32'h0;
      end
   end
   
endmodule