data/full_repos/permissive/167856740/cpu/tb/mux2_tb.v
 line:29: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/mux2_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/mux2_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #10 sel = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167856740/cpu/tb/mux2_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: data/full_repos/permissive/167856740/cpu/tb/mux2_tb.v:14: Cannot find file containing module: \'mux2\'\n mux2 mux2(.I_sel(sel), .I_data1(source_1), .I_data2(source_2), .O_data(destination));\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/mux2\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/mux2.v\n             data/full_repos/permissive/167856740/cpu/tb,data/full_repos/permissive/167856740/mux2.sv\n             mux2\n             mux2.v\n             mux2.sv\n             obj_dir/mux2\n             obj_dir/mux2.v\n             obj_dir/mux2.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux2_tb;
	

	reg clk;
	reg sel;	
	reg [31:0] source_1;
	reg [31:0] source_2;
	wire [31:0] destination;


	mux2 mux2(.I_sel(sel), .I_data1(source_1), .I_data2(source_2), .O_data(destination));


	always begin
		#5 clk = ~clk;
	end

	initial begin

		clk = 1; sel = 0; source_1 = 32'h00000001; source_2 = 32'h00000002;
	

		#10 sel = 1;
		

		#10 $finish;
	end
	
endmodule
module mux2_tb;

	

	reg clk;
	reg sel;	
	reg [31:0] source_1;
	reg [31:0] source_2;
	wire [31:0] destination;


	mux2 mux2(.I_sel(sel), .I_data1(source_1), .I_data2(source_2), .O_data(destination));


	always begin
		#5 clk = ~clk;
	end

	initial begin

		clk = 1; sel = 0; source_1 = 32'h00000001; source_2 = 32'h00000002;
	

		#10 sel = 1;
		

		#10 $finish;
	end
	
endmodule