data/full_repos/permissive/11525292/fpga/test/dsha_finisher.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/11525292/fpga/test/dsha_finisher.v:48: Unsupported: Ignoring delay on this delayed statement.\n always #(P/2) clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11525292/fpga/test/dsha_finisher.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #(135*P);\n  ^\n%Error: data/full_repos/permissive/11525292/fpga/test/dsha_finisher.v:57: Can\'t find definition of \'chunk1\' in dotted scope/variable: \'uut.chunk1\'\n  uut.chunk1.roundnum = 6\'h3e;\n      ^~~~~~\n        ... Known scopes under \'uut\': <no cells found>\n%Error: data/full_repos/permissive/11525292/fpga/test/dsha_finisher.v:58: Can\'t find definition of \'chunk2\' in dotted scope/variable: \'uut.chunk2\'\n  uut.chunk2.roundnum = 6\'h3e;\n      ^~~~~~\n        ... Known scopes under \'uut\': <no cells found>\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dsha_finisher_test;


	reg clk;
	reg [255:0] X;
	reg [95:0] Y;
	reg [31:0] in_nonce;


	wire [255:0] hash;
	wire [31:0] out_nonce;


	dsha_finisher uut (
		.clk(clk), 
		.X(X), 
		.Y(Y), 
		.in_nonce(in_nonce), 
		.hash(hash), 
		.out_nonce(out_nonce)
	);
	
	parameter P=10;
	always #(P/2) clk = ~clk;


	initial begin

		clk = 0;
		X = 256'h356d66244c73b9f1e1a328b2c6615412a965a72218c5c19eb5c5d4073db86a04;
		Y = 96'h1c2ac4af504e86edec9d69b1;
		in_nonce = 32'hb2957c02;
		uut.chunk1.roundnum = 6'h3e;
		uut.chunk2.roundnum = 6'h3e;

		#(135*P);
		$finish();
	end
      
endmodule
module dsha_finisher_test;



	reg clk;
	reg [255:0] X;
	reg [95:0] Y;
	reg [31:0] in_nonce;


	wire [255:0] hash;
	wire [31:0] out_nonce;


	dsha_finisher uut (
		.clk(clk), 
		.X(X), 
		.Y(Y), 
		.in_nonce(in_nonce), 
		.hash(hash), 
		.out_nonce(out_nonce)
	);
	
	parameter P=10;
	always #(P/2) clk = ~clk;


	initial begin

		clk = 0;
		X = 256'h356d66244c73b9f1e1a328b2c6615412a965a72218c5c19eb5c5d4073db86a04;
		Y = 96'h1c2ac4af504e86edec9d69b1;
		in_nonce = 32'hb2957c02;
		uut.chunk1.roundnum = 6'h3e;
		uut.chunk2.roundnum = 6'h3e;

		#(135*P);
		$finish();
	end
      
endmodule