data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Square_root/Square_Root_ReciprocalorNo_multicycle.v
1: b'%Error: Cannot find file containing module: Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Square_root,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Square_root/Square_Root_ReciprocalorNo_multicycle.v\n%Error: Exiting due to 3 error(s)\n'
module Square_Root_Reciprocal_GS_multicycle

		#(parameter WL = 24,




						LUT_bits = 15,
						LUT_addWidth = 12,
						dWL = 26,
						ITERATION = 0,
						m = LUT_addWidth + 1
						
		 ) 		

		(
			input CLK,
			input nRST,
			input CE,
			     
			input [WL-1:0] din,

			output reg [WL-1:0] dout
		);	

			reg   [LUT_bits-1:0] LUT [2**LUT_addWidth-1:0];
			wire  [dWL-1:0] d1_net, r2_net;
			reg	  [dWL-1:0] p2;
			wire  [dWL-1:0] d2;
			reg   [dWL-1:0] d2_s;
			reg   [dWL-1:0] onep5FP =  0;
			wire  [dWL-1:0] r2;
			wire  [WL-1 :0] tmp_result_1;
			reg   [WL-1 :0] tmp_result_2;
			reg   [LUT_bits-1 : 0]	  ini;
			reg   [WL-1		  : 0]    ini2;
			reg   [LUT_addWidth-1:0] reg_cmp;
			wire  [WL-1:0] iniValue;
			reg   Sel;





integer pointer;

		always @ (posedge CLK) begin
			if(~nRST) begin
					Sel <= 1'b0;
					pointer <= 0;
			end
			else begin
				if (CE) begin
					tmp_result_2 <= tmp_result_1;
					if (pointer == ITERATION) begin
						dout <= tmp_result_1;
						pointer <= 0;
						Sel <= 1'b0;
					end else begin
						pointer <= pointer + 1;
						Sel <= 1'b1;
					end
				end
			end
		end		

	always @ * begin
			if(~nRST) begin
					reg_cmp <= 0;
					p2 <= 0;
					ini <= 0;
					ini2 <= 0;
					p2 <= 0;
					d2_s <= 0;
					onep5FP[dWL-1:dWL-2] <= 2'b11;
			end else begin
				if (CE) begin
					reg_cmp  <= din[WL-2 : WL-1-LUT_addWidth];  
					ini <= LUT[reg_cmp];
					ini2[WL-1:WL-LUT_bits] <= ini;
					d2_s <= d2 >> 1;
					p2 <= onep5FP - d2_s;
				end
			end
	end	

	multiplexer #(.N(WL)) Sel_input_mux (.a(ini2),.b(tmp_result_2),.Sel(Sel),.out(iniValue));	
	
    mult_unsigned #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(WL-1), .WIO(1), .WFO(dWL-1)) multiplier_1 
				   (.CLK(CLK), .RST(nRST), .in1(iniValue), .in2(din), .out(d1_net));

    mult_unsigned #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(dWL-1), .WIO(1), .WFO(dWL-1)) multiplier_2 
				   (.CLK(CLK), .RST(nRST), .in1(iniValue), .in2(d1_net), .out(d2));
	
    mult_unsigned #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(dWL-1), .WIO(1), .WFO(dWL-1)) multiplier_4 
				   (.CLK(CLK), .RST(nRST), .in1(iniValue), .in2(p2), .out(r2));	


	ux_round2nearest
		#(
			.WordLength(dWL),
			.RoundLength(dWL-WL)
		 )
	round_0 
		(
			.CLK(CLK),
			.RESET(RST),
			.CE(CE),
			.x(r2),
			.y(tmp_result_1)
		 );	
			   
endmodule
module Square_Root_Reciprocal_GS_multicycle

		#(parameter WL = 24,




						LUT_bits = 15,
						LUT_addWidth = 12,
						dWL = 26,
						ITERATION = 0,
						m = LUT_addWidth + 1
						
		 ) 		

		(
			input CLK,
			input nRST,
			input CE,
			     
			input [WL-1:0] din,

			output reg [WL-1:0] dout
		);
	

			reg   [LUT_bits-1:0] LUT [2**LUT_addWidth-1:0];
			wire  [dWL-1:0] d1_net, r2_net;
			reg	  [dWL-1:0] p2;
			wire  [dWL-1:0] d2;
			reg   [dWL-1:0] d2_s;
			reg   [dWL-1:0] onep5FP =  0;
			wire  [dWL-1:0] r2;
			wire  [WL-1 :0] tmp_result_1;
			reg   [WL-1 :0] tmp_result_2;
			reg   [LUT_bits-1 : 0]	  ini;
			reg   [WL-1		  : 0]    ini2;
			reg   [LUT_addWidth-1:0] reg_cmp;
			wire  [WL-1:0] iniValue;
			reg   Sel;





integer pointer;

		always @ (posedge CLK) begin
			if(~nRST) begin
					Sel <= 1'b0;
					pointer <= 0;
			end
			else begin
				if (CE) begin
					tmp_result_2 <= tmp_result_1;
					if (pointer == ITERATION) begin
						dout <= tmp_result_1;
						pointer <= 0;
						Sel <= 1'b0;
					end else begin
						pointer <= pointer + 1;
						Sel <= 1'b1;
					end
				end
			end
		end		

	always @ * begin
			if(~nRST) begin
					reg_cmp <= 0;
					p2 <= 0;
					ini <= 0;
					ini2 <= 0;
					p2 <= 0;
					d2_s <= 0;
					onep5FP[dWL-1:dWL-2] <= 2'b11;
			end else begin
				if (CE) begin
					reg_cmp  <= din[WL-2 : WL-1-LUT_addWidth];  
					ini <= LUT[reg_cmp];
					ini2[WL-1:WL-LUT_bits] <= ini;
					d2_s <= d2 >> 1;
					p2 <= onep5FP - d2_s;
				end
			end
	end	

	multiplexer #(.N(WL)) Sel_input_mux (.a(ini2),.b(tmp_result_2),.Sel(Sel),.out(iniValue));	
	
    mult_unsigned #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(WL-1), .WIO(1), .WFO(dWL-1)) multiplier_1 
				   (.CLK(CLK), .RST(nRST), .in1(iniValue), .in2(din), .out(d1_net));

    mult_unsigned #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(dWL-1), .WIO(1), .WFO(dWL-1)) multiplier_2 
				   (.CLK(CLK), .RST(nRST), .in1(iniValue), .in2(d1_net), .out(d2));
	
    mult_unsigned #(.WI1(1), .WF1(WL-1), .WI2(1), .WF2(dWL-1), .WIO(1), .WFO(dWL-1)) multiplier_4 
				   (.CLK(CLK), .RST(nRST), .in1(iniValue), .in2(p2), .out(r2));	


	ux_round2nearest
		#(
			.WordLength(dWL),
			.RoundLength(dWL-WL)
		 )
	round_0 
		(
			.CLK(CLK),
			.RESET(RST),
			.CE(CE),
			.x(r2),
			.y(tmp_result_1)
		 );	
			   
endmodule