data/full_repos/permissive/151820635/processor.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-PINMISSING: data/full_repos/permissive/151820635/processor.v:176: Cell has missing pin: \'op\'\nALU a(read_data1,read_data2,Rd,result,op);\n    ^\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/151820635/processor.v:18: Bit extraction of array[7:0] requires 3 bit index, not 8 bits.\n                                                                   : ... In instance processor.c.i.m\nassign inst_code = {Mem[PC]};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/151820635/processor.v:151: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'Rd\' generates 3 bits.\n                                                                    : ... In instance processor.p2\nid_exwb_reg1[0] = Rd;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/151820635/processor.v:152: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'result\' generates 8 bits.\n                                                                    : ... In instance processor.p2\nid_exwb_reg2[0] = result;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/151820635/processor.v:154: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 1 bits.\n                                                                    : ... In instance processor.p2\nassign write_reg = id_exwb_reg1[0];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/151820635/processor.v:155: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 1 bits.\n                                                                    : ... In instance processor.p2\nassign write_reg = id_exwb_reg2[0];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/151820635/processor.v:58: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                   : ... In instance processor.p1\nif_id_reg[0] = inst_code[2:0];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/151820635/processor.v:59: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                   : ... In instance processor.p1\nif_id_reg[1] = inst_code[5:3];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/151820635/processor.v:61: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 2 bits.\n                                                                   : ... In instance processor.p1\nassign Rs = if_id_reg[0];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/151820635/processor.v:62: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 2 bits.\n                                                                   : ... In instance processor.p1\nassign Rd = if_id_reg[1];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/151820635/processor.v:176: Output port connection \'write_reg\' expects 3 bits on the pin connection, but pin connection\'s VARREF \'op\' generates 2 bits.\n                                                                    : ... In instance processor\nALU a(read_data1,read_data2,Rd,result,op);\n                                      ^~\n%Error: Exiting due to 11 warning(s)\n'
module in_fetch(input clk,
input rst,
output [7:0] inst_code
);
reg [7:0] PC;
i_mem m(PC,inst_code, rst);
always @ (posedge clk, negedge rst)
begin

if (rst==0)
PC<=0;

else 
PC<=PC +1;
end


endmodule
module in_fetch(input clk,
input rst,
output [7:0] inst_code
);

reg [7:0] PC;
i_mem m(PC,inst_code, rst);
always @ (posedge clk, negedge rst)
begin

if (rst==0)
PC<=0;

else 
PC<=PC +1;
end


endmodule