data/full_repos/permissive/135077285/aluControl.v
data/verilator_xmls/3aadc5fd-4bcd-4564-92b5-832217540188.xml
module aluControl (
  input wire [1:0] aluOp,
  input wire [5:0] funct,
  output reg [3:0] saida
);

  always @(*) begin
    case(aluOp)
      0: saida <= 0;
      1: saida <= 1;
      2: begin
        case(funct)
          6'b10_0000: saida <= 0;
          6'b10_0010: saida <= 1;
          6'b10_0100: saida <= 2;
          6'b10_0101: saida <= 3;
          6'b00_0000: saida <= 4;
          6'b00_0010: saida <= 5;
          6'b10_1010: saida <= 6;
        endcase
      end
    endcase
  end



















endmodule
module aluControl (
  input wire [1:0] aluOp,
  input wire [5:0] funct,
  output reg [3:0] saida
);


  always @(*) begin
    case(aluOp)
      0: saida <= 0;
      1: saida <= 1;
      2: begin
        case(funct)
          6'b10_0000: saida <= 0;
          6'b10_0010: saida <= 1;
          6'b10_0100: saida <= 2;
          6'b10_0101: saida <= 3;
          6'b00_0000: saida <= 4;
          6'b00_0010: saida <= 5;
          6'b10_1010: saida <= 6;
        endcase
      end
    endcase
  end



















endmodule