data/full_repos/permissive/191467986/rtl/Clock.v
1: b"%Error: data/full_repos/permissive/191467986/rtl/Clock.v:22: Cannot find file containing module: 'Divider'\n    Divider #(DIVISOR) clock_divider\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191467986/rtl,data/full_repos/permissive/191467986/Divider\n             data/full_repos/permissive/191467986/rtl,data/full_repos/permissive/191467986/Divider.v\n             data/full_repos/permissive/191467986/rtl,data/full_repos/permissive/191467986/Divider.sv\n             Divider\n             Divider.v\n             Divider.sv\n             obj_dir/Divider\n             obj_dir/Divider.v\n             obj_dir/Divider.sv\n%Error: Exiting due to 1 error(s)\n"
module Clock
(
    input       i_SYS_CLOCK,
    input       i_HALT,
    input       i_STEP_TOGGLE,
    input       i_STEP_CLOCK,

    output      o_CLOCK,
    output      o_CLOCK_n
);  

    wire        w_CLOCK;

    reg         r_CLOCK_SIGNAL	= 0;
    reg         r_MANUAL_STEP	= 0;

    parameter   DIVISOR         = 32'hFFFFFF;
    
    reg         HALTED          = 0;

    Divider #(DIVISOR) clock_divider
    (
        i_SYS_CLOCK,
        w_CLOCK
    );


    always @(posedge i_STEP_TOGGLE)
    begin
        r_MANUAL_STEP <= !r_MANUAL_STEP;
    end


    always @(posedge i_SYS_CLOCK)
    begin

        if (i_HALT)
            HALTED <= 1;
        else begin

            if (r_MANUAL_STEP)
                r_CLOCK_SIGNAL <= i_STEP_CLOCK;

            else
                r_CLOCK_SIGNAL <= w_CLOCK;
        end
    end

    assign o_CLOCK      = r_CLOCK_SIGNAL & !HALTED;
    assign o_CLOCK_n    = !o_CLOCK;
endmodule
module Clock
(
    input       i_SYS_CLOCK,
    input       i_HALT,
    input       i_STEP_TOGGLE,
    input       i_STEP_CLOCK,

    output      o_CLOCK,
    output      o_CLOCK_n
);
  

    wire        w_CLOCK;

    reg         r_CLOCK_SIGNAL	= 0;
    reg         r_MANUAL_STEP	= 0;

    parameter   DIVISOR         = 32'hFFFFFF;
    
    reg         HALTED          = 0;

    Divider #(DIVISOR) clock_divider
    (
        i_SYS_CLOCK,
        w_CLOCK
    );


    always @(posedge i_STEP_TOGGLE)
    begin
        r_MANUAL_STEP <= !r_MANUAL_STEP;
    end


    always @(posedge i_SYS_CLOCK)
    begin

        if (i_HALT)
            HALTED <= 1;
        else begin

            if (r_MANUAL_STEP)
                r_CLOCK_SIGNAL <= i_STEP_CLOCK;

            else
                r_CLOCK_SIGNAL <= w_CLOCK;
        end
    end

    assign o_CLOCK      = r_CLOCK_SIGNAL & !HALTED;
    assign o_CLOCK_n    = !o_CLOCK;
endmodule