data/full_repos/permissive/108382235/SingleCycleTest.v
 line:48: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/108382235/SingleCycleTest.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #0 SwitchClk_10=1; reset=1;Time=-1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/108382235/SingleCycleTest.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset=0;\n  ^\n%Error: data/full_repos/permissive/108382235/SingleCycleTest.v:43: Unsupported or unknown PLI call: $monitor\n  $monitor(" Time: %d, CLK = %d, PC = %h \\n [$s0] = %h, [$s1] = %h, [$s2] = %h \\n [$s3] = %h, [$s4] = %h, [$s5] = %h \\n [$s6] = %h, [$s7] = %h, [$t0] = %h \\n [$t1] = %h, [$t2] = %h, [$t3] = %h \\n [$t4] = %h, [$t5] = %h, [$t6] = %h \\n [$t7] = %h, [$t8] = %h, [$t9] = %h \\n ", Time, SwitchClk_10, CurrentPC, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/108382235/SingleCycleTest.v:46: Unsupported: Ignoring delay on this delayed statement.\n always #50 SwitchClk_10=~SwitchClk_10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/108382235/SingleCycleTest.v:48: Unsupported: Ignoring delay on this delayed statement.\n initial #3000 $stop;\n         ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SingleCycleTest;
	wire [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC;

	reg SwitchClk_10, reset;

	reg [9:0] Time;
	
	SingleCycle UUT(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,CurrentPC, SwitchClk_10, reset);
	
	always @(posedge SwitchClk_10) begin
		Time=Time+1;
	end
	
	initial begin 
		#0 SwitchClk_10=1; reset=1;Time=-1;
		#10 reset=0;
	end
	
	initial begin
		$display("**********************************************");
		$display("The textual simulation results:");
		$display("**********************************************");
		$monitor(" Time: %d, CLK = %d, PC	= %h \n [$s0] = %h, [$s1] = %h, [$s2] = %h \n [$s3] = %h, [$s4] = %h, [$s5] = %h \n [$s6] = %h, [$s7] = %h, [$t0] = %h \n [$t1] = %h, [$t2] = %h, [$t3] = %h \n [$t4] = %h, [$t5] = %h, [$t6] = %h \n [$t7] = %h, [$t8] = %h, [$t9] = %h \n ", Time, SwitchClk_10, CurrentPC, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9);
	end
	
	always #50 SwitchClk_10=~SwitchClk_10;
	
	initial #3000 $stop;

endmodule
module SingleCycleTest;

	wire [31:0] s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC;

	reg SwitchClk_10, reset;

	reg [9:0] Time;
	
	SingleCycle UUT(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9,CurrentPC, SwitchClk_10, reset);
	
	always @(posedge SwitchClk_10) begin
		Time=Time+1;
	end
	
	initial begin 
		#0 SwitchClk_10=1; reset=1;Time=-1;
		#10 reset=0;
	end
	
	initial begin
		$display("**********************************************");
		$display("The textual simulation results:");
		$display("**********************************************");
		$monitor(" Time: %d, CLK = %d, PC	= %h \n [$s0] = %h, [$s1] = %h, [$s2] = %h \n [$s3] = %h, [$s4] = %h, [$s5] = %h \n [$s6] = %h, [$s7] = %h, [$t0] = %h \n [$t1] = %h, [$t2] = %h, [$t3] = %h \n [$t4] = %h, [$t5] = %h, [$t6] = %h \n [$t7] = %h, [$t8] = %h, [$t9] = %h \n ", Time, SwitchClk_10, CurrentPC, s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9);
	end
	
	always #50 SwitchClk_10=~SwitchClk_10;
	
	initial #3000 $stop;

endmodule