data/full_repos/permissive/18770871/memory/phase1_separate/memory_tb.v
 line:63: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase1_separate/memory_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n#10 rst = 1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase1_separate/memory_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n#10 rst = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase1_separate/memory_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10 address = address + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase1_separate/memory_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n#10 rst = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase1_separate/memory_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n#10 rst = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase1_separate/memory_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10 address = address + 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase1_separate/memory_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n           #10 address = address + 1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase1_separate/memory_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n#100 $finish;\n^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/memory/phase1_separate/memory_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/18770871/memory/phase1_separate/memory_tb.v:16: Cannot find file containing module: \'memory\'\nmemory d0 (\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18770871/memory/phase1_separate,data/full_repos/permissive/18770871/memory\n             data/full_repos/permissive/18770871/memory/phase1_separate,data/full_repos/permissive/18770871/memory.v\n             data/full_repos/permissive/18770871/memory/phase1_separate,data/full_repos/permissive/18770871/memory.sv\n             memory\n             memory.v\n             memory.sv\n             obj_dir/memory\n             obj_dir/memory.v\n             obj_dir/memory.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_tb;
parameter ASIZE=16;
parameter DSIZE=16;
reg clk;
reg rst;
reg wen;
reg [ASIZE-1:0] address;
reg [DSIZE-1:0] data_in;
wire [DSIZE-1:0] data_out;
reg [3:0] fileid;

`define TEST_LIMIT 100

memory d0 (
  .clk(clk),
  .rst(rst),
  .wen(wen),
  .addr(address),
  .data_in(data_in),
  .data_out(data_out),
  .fileid(fileid)
);

integer i;

initial begin
   fileid = 0; clk = 0;   rst = 0; wen = 1; data_in=16'hFFFF; address = 0;
#10 rst = 1;
#10 rst = 0;
   for(i = 0; i< 2 ** ASIZE; i=i+1) begin
	$write("%0dns: Data[%h] = ",$time,address);
	#10 address = address + 1;
	$write("%h\n", data_out);
	if(data_out == 0) begin
		i=2**ASIZE;
	end
    end
   fileid = 8; address = 0;
#10 rst = 1;
#10 rst = 0;
   for(i = 0; i< 2 ** ASIZE; i=i+1) begin
        $write("%0dns: Data[%h] = ",$time,address);
        #10 address = address + 1;
        $write("%h\n", data_out);
        if(data_out == 0) begin
                i=2**ASIZE;
        end
    end
    address = 0;
    wen = 0; 
    for (i = 0; i < 2 ** ASIZE; i = i + 1)
        begin
           $write("%0dns: Data[%h] = ",$time,address);
           #10 address = address + 1;
               data_in = data_in - 1;
           $write("%h\n", data_out);
           if(address == `TEST_LIMIT) begin
                i=2**ASIZE;
           end 
        end
#100 $finish;
end


always #5 clk = ~clk;

endmodule
module memory_tb;

parameter ASIZE=16;
parameter DSIZE=16;
reg clk;
reg rst;
reg wen;
reg [ASIZE-1:0] address;
reg [DSIZE-1:0] data_in;
wire [DSIZE-1:0] data_out;
reg [3:0] fileid;

`define TEST_LIMIT 100

memory d0 (
  .clk(clk),
  .rst(rst),
  .wen(wen),
  .addr(address),
  .data_in(data_in),
  .data_out(data_out),
  .fileid(fileid)
);

integer i;

initial begin
   fileid = 0; clk = 0;   rst = 0; wen = 1; data_in=16'hFFFF; address = 0;
#10 rst = 1;
#10 rst = 0;
   for(i = 0; i< 2 ** ASIZE; i=i+1) begin
	$write("%0dns: Data[%h] = ",$time,address);
	#10 address = address + 1;
	$write("%h\n", data_out);
	if(data_out == 0) begin
		i=2**ASIZE;
	end
    end
   fileid = 8; address = 0;
#10 rst = 1;
#10 rst = 0;
   for(i = 0; i< 2 ** ASIZE; i=i+1) begin
        $write("%0dns: Data[%h] = ",$time,address);
        #10 address = address + 1;
        $write("%h\n", data_out);
        if(data_out == 0) begin
                i=2**ASIZE;
        end
    end
    address = 0;
    wen = 0; 
    for (i = 0; i < 2 ** ASIZE; i = i + 1)
        begin
           $write("%0dns: Data[%h] = ",$time,address);
           #10 address = address + 1;
               data_in = data_in - 1;
           $write("%h\n", data_out);
           if(address == `TEST_LIMIT) begin
                i=2**ASIZE;
           end 
        end
#100 $finish;
end


always #5 clk = ~clk;

endmodule