data/full_repos/permissive/143278/ivltests/sv_uwire3.v
 line:5: before: "typedef"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sv_uwire3.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #1  ;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
   sample_t dst;
   logic [1:0] src_a, src_b;

   DUT dut(.out(dst), .x(src_a), .y(src_b));

   initial begin
      src_a = 1;
      src_b = 2;

      #1;
      if (dst.a !== 1) begin
	 $display("FAILED -- dst.a=%b (dst=%b)", dst.a, dst);
	 $finish;
      end

      if (dst.b !== 2) begin
	 $display("FAILED -- dst.b=%b (dst=%b)", dst.b, dst);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;

   sample_t dst;
   logic [1:0] src_a, src_b;

   DUT dut(.out(dst), .x(src_a), .y(src_b));

   initial begin
      src_a = 1;
      src_b = 2;

      #1;
      if (dst.a !== 1) begin
	 $display("FAILED -- dst.a=%b (dst=%b)", dst.a, dst);
	 $finish;
      end

      if (dst.b !== 2) begin
	 $display("FAILED -- dst.b=%b (dst=%b)", dst.b, dst);
	 $finish;
      end

      $display("PASSED");
   end
endmodule