data/full_repos/permissive/188434311/verilog/register_slice/synchronizer/sync_reg_p.v
1: b"%Error: data/full_repos/permissive/188434311/verilog/register_slice/synchronizer/sync_reg_p.v:19: Can't find definition of variable: 'async_data_i'\n                                                                                                : ... Suggested alternative: 'aync_data_i'\nassign indata = { data_d[ STAGE - 2 : 0 ] , async_data_i } ;\n                                            ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module sync_reg_p #(
  parameter STAGE = 2
)
(
  input   wire  clki,
  input   wire  rstn,
  input   wire  aync_data_i,
  output  wire  sync_data_o
);

reg  [ STAGE - 1 : 0 ]  data_d;
wire [ STAGE - 1 : 0 ]  indata;

assign indata = { data_d[ STAGE - 2 : 0 ] , async_data_i } ;
assign sync_data_o =   data_d[ STAGE - 1 ]                ; 

genvar i;
generate
  for( i = 0 ; i < STAGE ; i = i + 1 ) begin:stage
    synchronizer_p sync_d1_p_inst(
      .clki(clki),
      .rstn(rstn),
      .data_i(indata[i]),
      .data_o(data_d[i])
    );
  end
endgenerate

endmodule
module sync_reg_p #(
  parameter STAGE = 2
)
(
  input   wire  clki,
  input   wire  rstn,
  input   wire  aync_data_i,
  output  wire  sync_data_o
);


reg  [ STAGE - 1 : 0 ]  data_d;
wire [ STAGE - 1 : 0 ]  indata;

assign indata = { data_d[ STAGE - 2 : 0 ] , async_data_i } ;
assign sync_data_o =   data_d[ STAGE - 1 ]                ; 

genvar i;
generate
  for( i = 0 ; i < STAGE ; i = i + 1 ) begin:stage
    synchronizer_p sync_d1_p_inst(
      .clki(clki),
      .rstn(rstn),
      .data_i(indata[i]),
      .data_o(data_d[i])
    );
  end
endgenerate

endmodule