data/full_repos/permissive/116048589/Xilinx_Project/SPI_Master_Controller/DAC_TEST.v
data/verilator_xmls/694d7ee2-0596-4597-8317-78b838865e18.xml
module DAC_TEST(
    input clk,
	 input count_test,
	 input reset,
    output [31:0] toSPI,
	 output reg toEnable,
	 output toReset
	 
    );

reg [1:0] PS, NS;
parameter idle = 0;
parameter sendEnable = 1;
parameter doNothing = 2;
reg [11:0] DAC_Count = 0;

always@(posedge clk)
begin
	if(reset)
		PS <= idle;
	else
		PS <= NS;

end

always@(*)
begin
	NS <= idle;
	case(PS)
		idle				:	NS <= sendEnable;
		sendEnable		:	NS <= doNothing;
		doNothing		: 	NS	<= (count_test) ? idle : doNothing;
		default			:	NS <=	idle;
	endcase 
end


always@(*)
begin
	toEnable <= 0;
	case(PS)
		sendEnable	:	toEnable <= 1;
		default		:	toEnable <= 0;

	endcase
end




always@(posedge clk)
	if(count_test)
	begin
		DAC_Count <= DAC_Count + 1;
	end	





assign toSPI = {8'b11111111, 4'b0011,4'b0000,DAC_Count,4'b1111};

assign toReset = ~reset;
endmodule
module DAC_TEST(
    input clk,
	 input count_test,
	 input reset,
    output [31:0] toSPI,
	 output reg toEnable,
	 output toReset
	 
    );


reg [1:0] PS, NS;
parameter idle = 0;
parameter sendEnable = 1;
parameter doNothing = 2;
reg [11:0] DAC_Count = 0;

always@(posedge clk)
begin
	if(reset)
		PS <= idle;
	else
		PS <= NS;

end

always@(*)
begin
	NS <= idle;
	case(PS)
		idle				:	NS <= sendEnable;
		sendEnable		:	NS <= doNothing;
		doNothing		: 	NS	<= (count_test) ? idle : doNothing;
		default			:	NS <=	idle;
	endcase 
end


always@(*)
begin
	toEnable <= 0;
	case(PS)
		sendEnable	:	toEnable <= 1;
		default		:	toEnable <= 0;

	endcase
end




always@(posedge clk)
	if(count_test)
	begin
		DAC_Count <= DAC_Count + 1;
	end	





assign toSPI = {8'b11111111, 4'b0011,4'b0000,DAC_Count,4'b1111};

assign toReset = ~reset;
endmodule