data/full_repos/permissive/136009613/decoderTB.v
1: b'%Error: data/full_repos/permissive/136009613/decoderTB.v:3: syntax error, unexpected \'=\', expecting IDENTIFIER\n parameter byte = 8;\n                ^\n%Error: data/full_repos/permissive/136009613/decoderTB.v:4: syntax error, unexpected \';\', expecting "\'{"\n parameter width_in = 4 * byte;\n                              ^\n%Error: data/full_repos/permissive/136009613/decoderTB.v:5: syntax error, unexpected \';\', expecting "\'{"\n parameter width_out = 4 * byte;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/decoderTB.v:29: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = !clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136009613/decoderTB.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #15 reset = 1; start = 1; instruction_in = 32\'h03000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/decoderTB.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #50 start = 0; instruction_in = 32\'h04000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/decoderTB.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #5 start = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/decoderTB.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #20 reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/decoderTB.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #15 reset = 1; instruction_in = 32\'h6f000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/decoderTB.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #15 instruction_in = 32\'h91000000;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/decoderTB.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #15 instruction_in = 32\'h50000000;  \n  ^\n%Error: Exiting due to 3 error(s), 8 warning(s)\n'
module decoderTB;

	parameter byte = 8;
	parameter width_in = 4 * byte;
	parameter width_out = 4 * byte;
	parameter address_size = 16;
	
	reg clk;
	reg reset;
	reg start;
	wire ready;
	reg [width_in - 1:0] instruction_in;
	wire [width_out - 1:0] instruction_out;
	wire start_for_memory;
	wire [address_size - 1:0] address_for_memory;
	
	decoder TB(
		.clk(clk),
		.reset(reset),
		.start(start),
		.ready(ready),
		.instruction_in(instruction_in),
		.instruction_out(instruction_out),
		.start_for_memory(start_for_memory),
		.address_for_memory(address_for_memory)
	);
	
	initial clk = 0;
	always #5 clk = !clk;
	
	initial reset = 0;
	
	initial
	begin
	
		#15 reset = 1; start = 1; instruction_in = 32'h03000000;
		
		#50 start = 0; instruction_in = 32'h04000000;
		
		#5 start = 1;
		
		#20 reset = 0;
		
		#15 reset = 1; instruction_in = 32'h6f000000;
		
		#15 instruction_in = 32'h91000000;
		
		#15 instruction_in = 32'h50000000;

	end

endmodule
module decoderTB;


	parameter byte = 8;
	parameter width_in = 4 * byte;
	parameter width_out = 4 * byte;
	parameter address_size = 16;
	
	reg clk;
	reg reset;
	reg start;
	wire ready;
	reg [width_in - 1:0] instruction_in;
	wire [width_out - 1:0] instruction_out;
	wire start_for_memory;
	wire [address_size - 1:0] address_for_memory;
	
	decoder TB(
		.clk(clk),
		.reset(reset),
		.start(start),
		.ready(ready),
		.instruction_in(instruction_in),
		.instruction_out(instruction_out),
		.start_for_memory(start_for_memory),
		.address_for_memory(address_for_memory)
	);
	
	initial clk = 0;
	always #5 clk = !clk;
	
	initial reset = 0;
	
	initial
	begin
	
		#15 reset = 1; start = 1; instruction_in = 32'h03000000;
		
		#50 start = 0; instruction_in = 32'h04000000;
		
		#5 start = 1;
		
		#20 reset = 0;
		
		#15 reset = 1; instruction_in = 32'h6f000000;
		
		#15 instruction_in = 32'h91000000;
		
		#15 instruction_in = 32'h50000000;

	end

endmodule