data/full_repos/permissive/199399537/greybox_tmp/greybox_tmp/mgvbv.v
 line:58: before: "."
1: b"%Error: data/full_repos/permissive/199399537/greybox_tmp/greybox_tmp/mgvbv.v:48: Cannot find file containing module: 'dcfifo'\n dcfifo   mgl_prim1\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/199399537/greybox_tmp/greybox_tmp,data/full_repos/permissive/199399537/dcfifo\n             data/full_repos/permissive/199399537/greybox_tmp/greybox_tmp,data/full_repos/permissive/199399537/dcfifo.v\n             data/full_repos/permissive/199399537/greybox_tmp/greybox_tmp,data/full_repos/permissive/199399537/dcfifo.sv\n             dcfifo\n             dcfifo.v\n             dcfifo.sv\n             obj_dir/dcfifo\n             obj_dir/dcfifo.v\n             obj_dir/dcfifo.sv\n%Error: Exiting due to 1 error(s)\n"
module  mgvbv
	( 
	data,
	q,
	rdclk,
	rdreq,
	wrclk,
	wrreq,
	wrusedw);
	input   [15:0]  data;
	output   [15:0]  q;
	input   rdclk;
	input   rdreq;
	input   wrclk;
	input   wrreq;
	output   [8:0]  wrusedw;

	wire  [15:0]   wire_mgl_prim1_q;
	wire  [8:0]   wire_mgl_prim1_wrusedw;

	dcfifo   mgl_prim1
	( 
	.data(data),
	.q(wire_mgl_prim1_q),
	.rdclk(rdclk),
	.rdreq(rdreq),
	.wrclk(wrclk),
	.wrreq(wrreq),
	.wrusedw(wire_mgl_prim1_wrusedw));
	defparam
		mgl_prim1.add_ram_output_register = "ON",
		mgl_prim1.clocks_are_synchronized = "FALSE",
		mgl_prim1.intended_device_family = "Cyclone",
		mgl_prim1.lpm_numwords = 512,
		mgl_prim1.lpm_showahead = "OFF",
		mgl_prim1.lpm_type = "dcfifo",
		mgl_prim1.lpm_width = 16,
		mgl_prim1.lpm_widthu = 9,
		mgl_prim1.overflow_checking = "ON",
		mgl_prim1.underflow_checking = "ON",
		mgl_prim1.use_eab = "ON",
		mgl_prim1.lpm_hint = "RAM_BLOCK_TYPE=M4K";
	assign
		q = wire_mgl_prim1_q,
		wrusedw = wire_mgl_prim1_wrusedw;
endmodule
module  mgvbv
	( 
	data,
	q,
	rdclk,
	rdreq,
	wrclk,
	wrreq,
	wrusedw);

	input   [15:0]  data;
	output   [15:0]  q;
	input   rdclk;
	input   rdreq;
	input   wrclk;
	input   wrreq;
	output   [8:0]  wrusedw;

	wire  [15:0]   wire_mgl_prim1_q;
	wire  [8:0]   wire_mgl_prim1_wrusedw;

	dcfifo   mgl_prim1
	( 
	.data(data),
	.q(wire_mgl_prim1_q),
	.rdclk(rdclk),
	.rdreq(rdreq),
	.wrclk(wrclk),
	.wrreq(wrreq),
	.wrusedw(wire_mgl_prim1_wrusedw));
	defparam
		mgl_prim1.add_ram_output_register = "ON",
		mgl_prim1.clocks_are_synchronized = "FALSE",
		mgl_prim1.intended_device_family = "Cyclone",
		mgl_prim1.lpm_numwords = 512,
		mgl_prim1.lpm_showahead = "OFF",
		mgl_prim1.lpm_type = "dcfifo",
		mgl_prim1.lpm_width = 16,
		mgl_prim1.lpm_widthu = 9,
		mgl_prim1.overflow_checking = "ON",
		mgl_prim1.underflow_checking = "ON",
		mgl_prim1.use_eab = "ON",
		mgl_prim1.lpm_hint = "RAM_BLOCK_TYPE=M4K";
	assign
		q = wire_mgl_prim1_q,
		wrusedw = wire_mgl_prim1_wrusedw;
endmodule