data/full_repos/permissive/196412397/clock_divider_param.v
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1: b'%Warning-UNSIGNED: data/full_repos/permissive/196412397/clock_divider_param.v:22: Comparison is constant due to unsigned arithmetic\n                                                                                : ... In instance clock_divider\n    else if (counter >= 0 )\n                     ^~\n                   ... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module clock_divider #(
    parameter DIVIDER =2,
    parameter WIDTH =2
) (
    input clk,
    output clk_out);

reg state=1'b0, next_state=1'b1;
reg [WIDTH-1:0] counter = DIVIDER-1 ; 

always@(posedge clk)begin
    state <= next_state;
    if ( counter == 0) begin
        next_state <= ~next_state;
        counter <= DIVIDER-1;
    end
    else if (counter >= 0 )
        counter <= counter - 1;
end

assign clk_out = state;

endmodule
module clock_divider #(
    parameter DIVIDER =2,
    parameter WIDTH =2
) (
    input clk,
    output clk_out);


reg state=1'b0, next_state=1'b1;
reg [WIDTH-1:0] counter = DIVIDER-1 ; 

always@(posedge clk)begin
    state <= next_state;
    if ( counter == 0) begin
        next_state <= ~next_state;
        counter <= DIVIDER-1;
    end
    else if (counter >= 0 )
        counter <= counter - 1;
end

assign clk_out = state;

endmodule