data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl/clk_gen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl/clk_gen.v:37: Bit extraction of array[3:0] requires 2 bit index, not 5 bits.\n                                                                                              : ... In instance clk_gen\n    if(address<clk_num) clk_pre[address]<=writedata;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/117851934/ddr_layout_V5/ip/clk_gen/hdl/clk_gen.v:41: Bit extraction of array[3:0] requires 2 bit index, not 5 bits.\n                                                                                              : ... In instance clk_gen\n    if(address<clk_num) readdata<=clk_pre[address];\n                                         ^\n%Error: Exiting due to 2 warning(s)\n'
module clk_gen					
(clk_source,clk_out,clk,reset_n,chipselect,address,read,write,readdata,writedata);
	parameter clk_num=4;

	input  wire clk_source;
	output wire [clk_num-1:0] clk_out;
	

	input  wire clk;
	input  wire reset_n;
	input  wire chipselect;
	input  wire [4:0] address;
	input  wire read;
	input  wire write;
	output reg  [31:0] readdata;
	input  wire [31:0] writedata;

	
	reg	[31:0] clk_pre[0:clk_num-1];
	reg [31:0] clk_count[0:clk_num-1];
	reg [clk_num-1:0] clk_out2;
	integer i;

	always @(posedge clk or negedge reset_n)
	begin
		if (!reset_n)
		begin
			for(i=0;i<clk_num;i=i+1) clk_pre[i]<=2+i;
		end
		else
		begin
			if(chipselect && write)
			begin
				if(address<clk_num) clk_pre[address]<=writedata;
			end
			else if(chipselect && read)
			begin
				if(address<clk_num) readdata<=clk_pre[address];
			end
		end
	end
	
	always @(posedge clk_source or negedge reset_n)
	begin
		if (!reset_n)
		begin
			for(i=0;i<clk_num;i=i+1) begin 
				clk_count[i]<= 0;
				clk_out2[i] <= 0;
			end
		end
		else
		begin
			for(i=0;i<clk_num;i=i+1) begin
				if(clk_count[i]>=clk_pre[i]-1) begin
					clk_count[i]<= 0;
					clk_out2[i] <= ~clk_out2[i];
				end else if(clk_count[i]==(clk_pre[i]>>1)-1) begin
					clk_count[i]<=clk_count[i]+1;
					clk_out2[i] <= ~clk_out2[i];
				end else begin
					clk_count[i]<=clk_count[i]+1;
					clk_out2[i] <= clk_out2[i];
				end
			end
		end
	end
	
	generate
  genvar j;
    for(j=0;j<clk_num;j=j+1) 
    begin:mux_clk
      assign clk_out[j] = (clk_pre[j]==1)? clk_source : clk_out2[j];
    end
  endgenerate
endmodule
module clk_gen					
(clk_source,clk_out,clk,reset_n,chipselect,address,read,write,readdata,writedata);

	parameter clk_num=4;

	input  wire clk_source;
	output wire [clk_num-1:0] clk_out;
	

	input  wire clk;
	input  wire reset_n;
	input  wire chipselect;
	input  wire [4:0] address;
	input  wire read;
	input  wire write;
	output reg  [31:0] readdata;
	input  wire [31:0] writedata;

	
	reg	[31:0] clk_pre[0:clk_num-1];
	reg [31:0] clk_count[0:clk_num-1];
	reg [clk_num-1:0] clk_out2;
	integer i;

	always @(posedge clk or negedge reset_n)
	begin
		if (!reset_n)
		begin
			for(i=0;i<clk_num;i=i+1) clk_pre[i]<=2+i;
		end
		else
		begin
			if(chipselect && write)
			begin
				if(address<clk_num) clk_pre[address]<=writedata;
			end
			else if(chipselect && read)
			begin
				if(address<clk_num) readdata<=clk_pre[address];
			end
		end
	end
	
	always @(posedge clk_source or negedge reset_n)
	begin
		if (!reset_n)
		begin
			for(i=0;i<clk_num;i=i+1) begin 
				clk_count[i]<= 0;
				clk_out2[i] <= 0;
			end
		end
		else
		begin
			for(i=0;i<clk_num;i=i+1) begin
				if(clk_count[i]>=clk_pre[i]-1) begin
					clk_count[i]<= 0;
					clk_out2[i] <= ~clk_out2[i];
				end else if(clk_count[i]==(clk_pre[i]>>1)-1) begin
					clk_count[i]<=clk_count[i]+1;
					clk_out2[i] <= ~clk_out2[i];
				end else begin
					clk_count[i]<=clk_count[i]+1;
					clk_out2[i] <= clk_out2[i];
				end
			end
		end
	end
	
	generate
  genvar j;
    for(j=0;j<clk_num;j=j+1) 
    begin:mux_clk
      assign clk_out[j] = (clk_pre[j]==1)? clk_source : clk_out2[j];
    end
  endgenerate
endmodule