data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v
 line:40: before: "."
1: b'%Warning-MULTITOP: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:464: Multiple top level modules\n                                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                 : ... Top module \'fpga_top\'\nmodule fpga_top(\n       ^~~~~~~~\n                                                                                                 : ... Top module \'WF_neo_fading_rom\'\nmodule WF_neo_fading_rom ( rd_data, rd_addr,clk);\n       ^~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:44: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:46: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:52: Signal definition not found, creating implicitly: \'five_ms\'\n           .timer_pulse(five_ms));\n                        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:60: Signal definition not found, creating implicitly: \'switch_pushed\'\n      .switch_pushed(switch_pushed),     \n                     ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:349: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                              : ... In instance fpga_top.neopixel_inst\n                   pixel_bit_cnt <= 1\'b0;\n                                 ^~\n%Error: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:478: Cannot find file containing module: \'SB_RAM256x16\'\n                 SB_RAM256x16  ram ( .WDATA(16\'b0),\n                 ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_RAM256x16\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_RAM256x16.v\n             data/full_repos/permissive/179884651/examples,data/full_repos/permissive/179884651/SB_RAM256x16.sv\n             SB_RAM256x16\n             SB_RAM256x16.v\n             SB_RAM256x16.sv\n             obj_dir/SB_RAM256x16\n             obj_dir/SB_RAM256x16.v\n             obj_dir/SB_RAM256x16.sv\n%Error: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:34: Cannot find file containing module: \'SB_HFOSC\'\n  SB_HFOSC OSC_i (\n  ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h1\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h2\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h3\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/179884651/examples/WF_neopixelx8_fading_demo2.v:166: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                              : ... In instance fpga_top\n      case (ram_rd_addr)\n      ^~~~\n%Error: Exiting due to 2 error(s), 14 warning(s)\n'
module WF_switch_debounce (
     input  wire clk,
     input  wire sample_en,
     input  wire switch_in,
     output reg  switch_out,
     output wire switch_pushed,
     output wire switch_released);

     reg  [2:0] switch;
     reg        switch_out_d;

     always @ (posedge clk)
       begin
         if ( sample_en)
           switch <= { switch[1:0],switch_in };

         if (switch == 3'b000)
           switch_out <= 1'b1;
         else if (switch == 3'b111)
           switch_out <= 1'b0;

         switch_out_d <= switch_out;
       end

     assign switch_pushed   = ~switch_out &&  switch_out_d;
     assign switch_released =  switch_out && ~switch_out_d;

   endmodule
module WF_switch_debounce (
     input  wire clk,
     input  wire sample_en,
     input  wire switch_in,
     output reg  switch_out,
     output wire switch_pushed,
     output wire switch_released);


     reg  [2:0] switch;
     reg        switch_out_d;

     always @ (posedge clk)
       begin
         if ( sample_en)
           switch <= { switch[1:0],switch_in };

         if (switch == 3'b000)
           switch_out <= 1'b1;
         else if (switch == 3'b111)
           switch_out <= 1'b0;

         switch_out_d <= switch_out;
       end

     assign switch_pushed   = ~switch_out &&  switch_out_d;
     assign switch_released =  switch_out && ~switch_out_d;

   endmodule