data/full_repos/permissive/161517951/divisao2.v
data/verilator_xmls/5da81de7-31a4-4a28-8089-70c92f862d42.xml
module divisao2 (A, S);

input  [3:0]A;
output [3:0]S;
 
assign S[0] = A[1];
assign S[1] = A[2];
assign S[2] = A[3];
assign S[3] = 0;
 
endmodule
module divisao2 (A, S);


input  [3:0]A;
output [3:0]S;
 
assign S[0] = A[1];
assign S[1] = A[2];
assign S[2] = A[3];
assign S[3] = 0;
 
endmodule