data/full_repos/permissive/113756623/Max7219Counter/work/verilog/base_ctr_11.v
 line:22: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/base_ctr_11.v:22: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance base_ctr_11\n  reg [4:0] M_val_d, M_val_q = 1\'h0;\n                               ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/base_ctr_11.v:28: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'M_val_q\' generates 5 bits.\n                                                                                                 : ... In instance base_ctr_11\n    ovf = M_val_q == 6\'h0f && inc;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/base_ctr_11.v:31: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance base_ctr_11\n        M_val_d = 1\'h0;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/base_ctr_11.v:30: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'M_val_q\' generates 5 bits.\n                                                                                                 : ... In instance base_ctr_11\n      if (M_val_q == 6\'h0f) begin\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/base_ctr_11.v:40: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                 : ... In instance base_ctr_11\n      M_val_q <= 1\'h0;\n              ^~\n%Error: Exiting due to 5 warning(s)\n'
module base_ctr_11 (
    input clk,
    input rst,
    input inc,
    output reg ovf,
    output reg [4:0] value
  );
  
  localparam BASE = 5'h10;
  
  
  reg [4:0] M_val_d, M_val_q = 1'h0;
  
  always @* begin
    M_val_d = M_val_q;
    
    value = M_val_q;
    ovf = M_val_q == 6'h0f && inc;
    if (inc) begin
      if (M_val_q == 6'h0f) begin
        M_val_d = 1'h0;
      end else begin
        M_val_d = M_val_q + 1'h1;
      end
    end
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_val_q <= 1'h0;
    end else begin
      M_val_q <= M_val_d;
    end
  end
  
endmodule
module base_ctr_11 (
    input clk,
    input rst,
    input inc,
    output reg ovf,
    output reg [4:0] value
  );

  
  localparam BASE = 5'h10;
  
  
  reg [4:0] M_val_d, M_val_q = 1'h0;
  
  always @* begin
    M_val_d = M_val_q;
    
    value = M_val_q;
    ovf = M_val_q == 6'h0f && inc;
    if (inc) begin
      if (M_val_q == 6'h0f) begin
        M_val_d = 1'h0;
      end else begin
        M_val_d = M_val_q + 1'h1;
      end
    end
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_val_q <= 1'h0;
    end else begin
      M_val_q <= M_val_d;
    end
  end
  
endmodule