data/full_repos/permissive/153690221/Source/VinithaCode/InstructionCache.v
 line:20: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/153690221/Source/VinithaCode/InstructionCache.v:294: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 3 bits.\n                                                                                              : ... In instance INSTRUCTION_CACHE\n     InstructionLine[IC_TagBits+IC_LRUBits-1:IC_TagBits] = 4-1;\n                                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/153690221/Source/VinithaCode/InstructionCache.v:164: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'UpdateInstruction_LRU\' generates 1 bits.\n                                                                                              : ... In instance INSTRUCTION_CACHE\n   temp = UpdateInstruction_LRU(IC_LRU, Index);  \n        ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/Source/VinithaCode/InstructionCache.v:187: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'UpdateInstruction_LRU\' generates 1 bits.\n                                                                                              : ... In instance INSTRUCTION_CACHE\n   temp = UpdateInstruction_LRU(IC_LRU, Index);  \n        ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/Source/VinithaCode/InstructionCache.v:201: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'w\' generates 32 bits.\n                                                                                              : ... In instance INSTRUCTION_CACHE\n     InstructionLine[IC_TagBits + IC_LRUBits-1 : IC_TagBits] = w;\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/Source/VinithaCode/InstructionCache.v:232: Operator NEQ expects 12 bits on the RHS, but RHS\'s CONST \'8\'h78\' generates 8 bits.\n                                                                                              : ... In instance INSTRUCTION_CACHE\n     if(print == TRUE || MESI_Bits != Invalid || IC_Tag != "x")\n                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/153690221/Source/VinithaCode/InstructionCache.v:313: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h49\' generates 8 bits.\n                                                                                              : ... In instance INSTRUCTION_CACHE\n   2\'b00: Get_MESI_ID = "I";\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/Source/VinithaCode/InstructionCache.v:314: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h45\' generates 8 bits.\n                                                                                              : ... In instance INSTRUCTION_CACHE\n   2\'b01: Get_MESI_ID = "E";\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/Source/VinithaCode/InstructionCache.v:315: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h53\' generates 8 bits.\n                                                                                              : ... In instance INSTRUCTION_CACHE\n   2\'b10: Get_MESI_ID = "S";\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/153690221/Source/VinithaCode/InstructionCache.v:316: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h4d\' generates 8 bits.\n                                                                                              : ... In instance INSTRUCTION_CACHE\n   2\'b11: Get_MESI_ID = "M";\n                      ^\n%Error: Exiting due to 9 warning(s)\n'
function [8:0] Get_MESI_ID;
		input [1:0] MESI;
		
		begin
			case(MESI)
			2'b00: Get_MESI_ID = "I";
			2'b01: Get_MESI_ID = "E";
			2'b10: Get_MESI_ID = "S";
			2'b11: Get_MESI_ID = "M";
			endcase
		end
	endfunction
function [8:0] Get_MESI_ID;

		input [1:0] MESI;
		
		begin
			case(MESI)
			2'b00: Get_MESI_ID = "I";
			2'b01: Get_MESI_ID = "E";
			2'b10: Get_MESI_ID = "S";
			2'b11: Get_MESI_ID = "M";
			endcase
		end
	endfunction