data/full_repos/permissive/160156794/binary_clock_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160156794/binary_clock_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/160156794/binary_clock_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/160156794/binary_clock_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, BCLOCK);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/160156794/binary_clock_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #2 reset <= 1\'b0;\n    ^\n%Error: data/full_repos/permissive/160156794/binary_clock_tb.v:28: Unsupported: wait statements\n    wait(BCLOCK.d3 == 2 & BCLOCK.d2 == 3);\n    ^~~~\n%Error: data/full_repos/permissive/160156794/binary_clock_tb.v:29: Unsupported: wait statements\n    wait(BCLOCK.d3 == 0 & BCLOCK.d2 == 0);\n    ^~~~\n%Error: data/full_repos/permissive/160156794/binary_clock_tb.v:30: Unsupported: wait statements\n    wait(BCLOCK.d3 == 2 & BCLOCK.d2 == 3);\n    ^~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  reg  clk;
  reg  reset;
  reg  ce;
  wire  [13:0] count;
  binary_clock BCLOCK(clk, reset, ce, count);

  always
    #1 clk = ~clk;

  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, BCLOCK);


    clk = 1'b0;
    ce = 1'b1;
    reset = 1'b1;

    #2 reset <= 1'b0;
  end

  initial begin
    wait(BCLOCK.d3 == 2 & BCLOCK.d2 == 3);
    wait(BCLOCK.d3 == 0 & BCLOCK.d2 == 0);
    wait(BCLOCK.d3 == 2 & BCLOCK.d2 == 3);
    $finish;
  end





endmodule
module test;

  reg  clk;
  reg  reset;
  reg  ce;
  wire  [13:0] count;
  binary_clock BCLOCK(clk, reset, ce, count);

  always
    #1 clk = ~clk;

  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, BCLOCK);


    clk = 1'b0;
    ce = 1'b1;
    reset = 1'b1;

    #2 reset <= 1'b0;
  end

  initial begin
    wait(BCLOCK.d3 == 2 & BCLOCK.d2 == 3);
    wait(BCLOCK.d3 == 0 & BCLOCK.d2 == 0);
    wait(BCLOCK.d3 == 2 & BCLOCK.d2 == 3);
    $finish;
  end





endmodule