data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf/apufClassic.v
1: b"%Error: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf/apufClassic.v:43: Cannot find file containing module: 'switchChain'\n  switchChain  #(.nStage(nStage) ) SWITCH_CHAIN( \n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf,data/full_repos/permissive/128781882/switchChain\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf,data/full_repos/permissive/128781882/switchChain.v\n             data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf,data/full_repos/permissive/128781882/switchChain.sv\n             switchChain\n             switchChain.v\n             switchChain.sv\n             obj_dir/switchChain\n             obj_dir/switchChain.v\n             obj_dir/switchChain.sv\n%Error: data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf/apufClassic.v:61: Cannot find file containing module: 'nandLatch'\n nandLatch ARBITER(\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module apufClassic #(parameter nStage = 64)(
	clk, 
	tigSignal, 
	vcc,
	c,
	respReady, 
	respBit
	);
	
	input clk;
	input tigSignal;
	input vcc;
	input [nStage-1:0] c;
	output respReady;            
	output respBit;
	
	wire pathT;
	wire pathB;
	reg tigReg;

	

	assign respReady = (pathT & pathB);
	

	always@(posedge clk) begin 
	 if(tigSignal)
		 tigReg <= vcc; 
	 else 
		 tigReg <= 1'b0; 
	end 


	 (*KEEP_HIERARCHY = "TRUE"*)
	 switchChain  #(.nStage(nStage) ) SWITCH_CHAIN( 
		 .inT(tigReg), 
		 .inB(tigReg), 
		 .c(c),
		 .outT(pathT),
		 .outB(pathB)
	 );




	
   (*KEEP_HIERARCHY = "TRUE"*)
	nandLatch ARBITER(
		.s(pathT),
		.r(pathB),
		.q(respBit),
		.qbar()
	 );
	 
	
endmodule
module apufClassic #(parameter nStage = 64)(
	clk, 
	tigSignal, 
	vcc,
	c,
	respReady, 
	respBit
	);

	
	input clk;
	input tigSignal;
	input vcc;
	input [nStage-1:0] c;
	output respReady;            
	output respBit;
	
	wire pathT;
	wire pathB;
	reg tigReg;

	

	assign respReady = (pathT & pathB);
	

	always@(posedge clk) begin 
	 if(tigSignal)
		 tigReg <= vcc; 
	 else 
		 tigReg <= 1'b0; 
	end 


	 (*KEEP_HIERARCHY = "TRUE"*)
	 switchChain  #(.nStage(nStage) ) SWITCH_CHAIN( 
		 .inT(tigReg), 
		 .inB(tigReg), 
		 .c(c),
		 .outT(pathT),
		 .outB(pathB)
	 );




	
   (*KEEP_HIERARCHY = "TRUE"*)
	nandLatch ARBITER(
		.s(pathT),
		.r(pathB),
		.q(respBit),
		.qbar()
	 );
	 
	
endmodule