data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v
 line:21: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  repeat(4) #10 clk=~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 clk=~clk;\n          ^\n%Error: data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v:34: syntax error, unexpected \'@\'\n  @(negedge reset);\n  ^\n%Error: data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v:38: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n   #1 $display("out=%h, out_exp=%h, fr_active=%h, fr_active_exp=%h, fr_valid=%h, fr_valid_exp=%h",\n   ^\n%Error: data/full_repos/permissive/116308238/unit_tests/pckthandler_fsm_tb.v:42: syntax error, unexpected \'@\'\n  repeat(20) @(posedge clk);\n             ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pckthandler_fsm_tb;
	reg clk, reset;
	reg [15:0] data_stream;
	reg [23:0] ph_stream;
	reg ph_select, valid_stream, ecc_error;

	wire [15:0] out_stream;
	wire frame_active, frame_valid;

	integer fd, status;

	reg [15:0] out_exp;
	reg fr_active_exp, fr_valid_exp;

	pckthandler_fsm DUT(clk, reset, data_stream, ph_stream, ph_select, valid_stream,
		ecc_error, out_stream, frame_active, frame_valid);


	initial begin
		clk = 0; reset =1;
		repeat(4) #10 clk=~clk;
		reset = 0;
		forever #10 clk=~clk;
	end


	initial begin
		fd = $fopen("pckthandler_fsm_testvec.txt", "r");
	end


	initial begin
		data_stream = 0; ph_stream= 0; ph_select = 0; valid_stream=0; ecc_error=0;
		@(negedge reset);
		while(!$feof(fd)) begin
			status = $fscanf(fd, "%h, %h, %h, %h, %h, %h, %h\n", data_stream, ph_stream, valid_stream, ph_select,
				out_exp, fr_active_exp, fr_valid_exp);
			@(posedge clk);
			#1 $display("out=%h, out_exp=%h, fr_active=%h, fr_active_exp=%h, fr_valid=%h, fr_valid_exp=%h",
				out_stream, out_exp, frame_active, fr_active_exp, frame_valid, fr_valid_exp);
		end
		repeat(20) @(posedge clk);
		$fclose(fd);
		$finish;
	end
endmodule
module pckthandler_fsm_tb;

	reg clk, reset;
	reg [15:0] data_stream;
	reg [23:0] ph_stream;
	reg ph_select, valid_stream, ecc_error;

	wire [15:0] out_stream;
	wire frame_active, frame_valid;

	integer fd, status;

	reg [15:0] out_exp;
	reg fr_active_exp, fr_valid_exp;

	pckthandler_fsm DUT(clk, reset, data_stream, ph_stream, ph_select, valid_stream,
		ecc_error, out_stream, frame_active, frame_valid);


	initial begin
		clk = 0; reset =1;
		repeat(4) #10 clk=~clk;
		reset = 0;
		forever #10 clk=~clk;
	end


	initial begin
		fd = $fopen("pckthandler_fsm_testvec.txt", "r");
	end


	initial begin
		data_stream = 0; ph_stream= 0; ph_select = 0; valid_stream=0; ecc_error=0;
		@(negedge reset);
		while(!$feof(fd)) begin
			status = $fscanf(fd, "%h, %h, %h, %h, %h, %h, %h\n", data_stream, ph_stream, valid_stream, ph_select,
				out_exp, fr_active_exp, fr_valid_exp);
			@(posedge clk);
			#1 $display("out=%h, out_exp=%h, fr_active=%h, fr_active_exp=%h, fr_valid=%h, fr_valid_exp=%h",
				out_stream, out_exp, frame_active, fr_active_exp, frame_valid, fr_valid_exp);
		end
		repeat(20) @(posedge clk);
		$fclose(fd);
		$finish;
	end
endmodule