data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitCount.v
1: b"%Error: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitCount.v:6: Cannot find file containing module: 'jkFlipFlop'\n  jkFlipFlop flop1(~reset, K, CLK, Q[0]);\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop,data/full_repos/permissive/172602559/jkFlipFlop\n             data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop,data/full_repos/permissive/172602559/jkFlipFlop.v\n             data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop,data/full_repos/permissive/172602559/jkFlipFlop.sv\n             jkFlipFlop\n             jkFlipFlop.v\n             jkFlipFlop.sv\n             obj_dir/jkFlipFlop\n             obj_dir/jkFlipFlop.v\n             obj_dir/jkFlipFlop.sv\n%Error: data/full_repos/permissive/172602559/FPGA_Lab_3-Latches_Flip-flops_and_Sequential_Circuits/Flipflop/bitCount.v:7: Cannot find file containing module: 'jkFlipFlop'\n  jkFlipFlop flop2(~reset & Q[0] , reset | Q[0], CLK, Q[1]);\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module bitCount(K, CLK, reset, Q);
  input K;
  input CLK, reset;
  output [1:0] Q;

  jkFlipFlop flop1(~reset, K, CLK, Q[0]);
  jkFlipFlop flop2(~reset & Q[0] , reset | Q[0], CLK, Q[1]);
endmodule
module bitCount(K, CLK, reset, Q);

  input K;
  input CLK, reset;
  output [1:0] Q;

  jkFlipFlop flop1(~reset, K, CLK, Q[0]);
  jkFlipFlop flop2(~reset & Q[0] , reset | Q[0], CLK, Q[1]);
endmodule