data/full_repos/permissive/107434030/src/freq_est_testbench.v
 line:61: before: "/"
1: b'%Warning-STMTDLY: data/full_repos/permissive/107434030/src/freq_est_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #(clk_period_half);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107434030/src/freq_est_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #(clk_period);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/107434030/src/freq_est_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #(clk_period*7);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/107434030/src/freq_est_testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #(clk_period);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/107434030/src/freq_est_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n   #(clk_period);\n   ^\n%Error: data/full_repos/permissive/107434030/src/freq_est_testbench.v:23: Cannot find file containing module: \'freq_est\'\n freq_est DUT(\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/107434030/src,data/full_repos/permissive/107434030/freq_est\n             data/full_repos/permissive/107434030/src,data/full_repos/permissive/107434030/freq_est.v\n             data/full_repos/permissive/107434030/src,data/full_repos/permissive/107434030/freq_est.sv\n             freq_est\n             freq_est.v\n             freq_est.sv\n             obj_dir/freq_est\n             obj_dir/freq_est.v\n             obj_dir/freq_est.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module freq_est_testbench();

	localparam clk_period = 0.0625;
	localparam clk_period_half = 0.03125;

	integer sample_count;

	reg clk_16MHz, RESETn;
	reg stop;

	reg signed [3:0] signal;
	wire valid;
	wire [9:0] counter_result;

	reg [3:0] signal_thread [0:9999];

	always begin : clock_toggle_16MHz
		#(clk_period_half);
		clk_16MHz = ~clk_16MHz;
	end

	freq_est DUT(
		.clk           (clk_16MHz),
		.RESETn        (RESETn),
		.stop          (stop),
		.signal        (signal),
		.valid         (valid),
		.counter_result(counter_result)
	);


	initial begin : run_sim

		$readmemh("signal.dat", signal_thread);

		signal = signal_thread[0] - 4'd8;

		sample_count = 0;
		clk_16MHz = 1;
		RESETn = 0;
		stop = 0;
		#(clk_period);

		#(clk_period*7);
		RESETn = 1;
		#(clk_period);
		while (sample_count < 10000) begin
			signal = signal_thread[sample_count] - 4'd8;
			sample_count = sample_count + 1;
			#(clk_period);
			if(sample_count == 5000)
				stop = 1;
			if(sample_count == 5100)
				stop = 0;
		end
		stop = 1;

	end

endmodule
module freq_est_testbench();


	localparam clk_period = 0.0625;
	localparam clk_period_half = 0.03125;

	integer sample_count;

	reg clk_16MHz, RESETn;
	reg stop;

	reg signed [3:0] signal;
	wire valid;
	wire [9:0] counter_result;

	reg [3:0] signal_thread [0:9999];

	always begin : clock_toggle_16MHz
		#(clk_period_half);
		clk_16MHz = ~clk_16MHz;
	end

	freq_est DUT(
		.clk           (clk_16MHz),
		.RESETn        (RESETn),
		.stop          (stop),
		.signal        (signal),
		.valid         (valid),
		.counter_result(counter_result)
	);


	initial begin : run_sim

		$readmemh("signal.dat", signal_thread);

		signal = signal_thread[0] - 4'd8;

		sample_count = 0;
		clk_16MHz = 1;
		RESETn = 0;
		stop = 0;
		#(clk_period);

		#(clk_period*7);
		RESETn = 1;
		#(clk_period);
		while (sample_count < 10000) begin
			signal = signal_thread[sample_count] - 4'd8;
			sample_count = sample_count + 1;
			#(clk_period);
			if(sample_count == 5000)
				stop = 1;
			if(sample_count == 5100)
				stop = 0;
		end
		stop = 1;

	end

endmodule