data/full_repos/permissive/143278/ivltests/memsynth7.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memsynth7.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memsynth7.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memsynth7.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memsynth7.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memsynth7.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memsynth7.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memsynth7.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memsynth7.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memsynth7.v:58: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memsynth7.v:59: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memsynth7.v:66: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memsynth7.v:67: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Error: Exiting due to 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [7:0] a;
   reg [2:0] adr, w_adr;
   reg	     rst, clk, ae, wr;

   (* ivl_synthesis_on *)
   always @(posedge clk)
     if (rst) begin
	a   <= 8'b00000000;
	adr <= 3'b000;
     end else if (ae) begin
	adr <= w_adr;
     end else if (wr) begin
	adr <= adr + 1;
	a[adr] <= 1;
     end

   (* ivl_synthesis_off *)
   initial begin

      clk = 0;
      wr = 0;
      ae = 0;
      rst = 1;
      #1 clk = 1;
      #1 clk = 0;
      if (a !== 8'b0000_0000 || adr !== 3'b000) begin
	 $display("FAILED - reset - a=%b, adr=%b", a, adr);
	 $finish;
      end

      rst = 0;
      #1 clk = 1;
      #1 clk = 0;
      if (a !== 8'b0000_0000 || adr !== 3'b000) begin
	 $display("FAILED - pause - a=%b, adr=%b", a, adr);
	 $finish;
      end

      wr = 1;
      #1 clk = 1;
      #1 clk = 0;
      if (a !== 8'b0000_0001 || adr !== 3'b001) begin
	 $display("FAILED - wr 1 - a=%b, adr=%b", a, adr);
	 $finish;
      end

      #1 clk = 1;
      #1 clk = 0;
      if (a !== 8'b0000_0011 || adr !== 3'b010) begin
	 $display("FAILED - wr 2 - a=%b, adr=%b", a, adr);
	 $finish;
      end

      ae = 1;
      w_adr = 4;
      #1 clk = 1;
      #1 clk = 0;
      if (a !== 8'b0000_0011 || adr !== 3'b100) begin
	 $display("FAILED - ae - a=%b, adr=%b", a, adr);
	 $finish;
      end

      ae = 0;
      #1 clk = 1;
      #1 clk = 0;
      if (a !== 8'b0001_0011 || adr !== 3'b101) begin
	 $display("FAILED - ae - a=%b, adr=%b", a, adr);
	 $finish;
      end

      $display("PASSED");

   end

endmodule
module main;


   reg [7:0] a;
   reg [2:0] adr, w_adr;
   reg	     rst, clk, ae, wr;

   (* ivl_synthesis_on *)
   always @(posedge clk)
     if (rst) begin
	a   <= 8'b00000000;
	adr <= 3'b000;
     end else if (ae) begin
	adr <= w_adr;
     end else if (wr) begin
	adr <= adr + 1;
	a[adr] <= 1;
     end

   (* ivl_synthesis_off *)
   initial begin

      clk = 0;
      wr = 0;
      ae = 0;
      rst = 1;
      #1 clk = 1;
      #1 clk = 0;
      if (a !== 8'b0000_0000 || adr !== 3'b000) begin
	 $display("FAILED - reset - a=%b, adr=%b", a, adr);
	 $finish;
      end

      rst = 0;
      #1 clk = 1;
      #1 clk = 0;
      if (a !== 8'b0000_0000 || adr !== 3'b000) begin
	 $display("FAILED - pause - a=%b, adr=%b", a, adr);
	 $finish;
      end

      wr = 1;
      #1 clk = 1;
      #1 clk = 0;
      if (a !== 8'b0000_0001 || adr !== 3'b001) begin
	 $display("FAILED - wr 1 - a=%b, adr=%b", a, adr);
	 $finish;
      end

      #1 clk = 1;
      #1 clk = 0;
      if (a !== 8'b0000_0011 || adr !== 3'b010) begin
	 $display("FAILED - wr 2 - a=%b, adr=%b", a, adr);
	 $finish;
      end

      ae = 1;
      w_adr = 4;
      #1 clk = 1;
      #1 clk = 0;
      if (a !== 8'b0000_0011 || adr !== 3'b100) begin
	 $display("FAILED - ae - a=%b, adr=%b", a, adr);
	 $finish;
      end

      ae = 0;
      #1 clk = 1;
      #1 clk = 0;
      if (a !== 8'b0001_0011 || adr !== 3'b101) begin
	 $display("FAILED - ae - a=%b, adr=%b", a, adr);
	 $finish;
      end

      $display("PASSED");

   end

endmodule