data/full_repos/permissive/148324174/HDLBits/Circuits/Multiplexers.v
1: b'%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/Multiplexers.v:7: Duplicate declaration of module: \'top_module\'\nmodule top_module( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/Multiplexers.v:1: ... Location of original declaration\nmodule top_module( \n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/Multiplexers.v:28: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/Multiplexers.v:1: ... Location of original declaration\nmodule top_module( \n       ^~~~~~~~~~\n%Warning-MODDUP: data/full_repos/permissive/148324174/HDLBits/Circuits/Multiplexers.v:37: Duplicate declaration of module: \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                 data/full_repos/permissive/148324174/HDLBits/Circuits/Multiplexers.v:1: ... Location of original declaration\nmodule top_module( \n       ^~~~~~~~~~\n%Error: Exiting due to 3 warning(s)\n'
module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    always @(*)begin
        case(sel)
            0: out = a;
            1: out = b;
            2: out = c;
            3: out = d;
            4: out = e;
            5: out = f;
            6: out = g;
            7: out = h;
            8: out = i;
            default: out = 16'hffff;
        endcase
    end
endmodule
module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );

    always @(*)begin
        case(sel)
            0: out = a;
            1: out = b;
            2: out = c;
            3: out = d;
            4: out = e;
            5: out = f;
            6: out = g;
            7: out = h;
            8: out = i;
            default: out = 16'hffff;
        endcase
    end
endmodule