data/full_repos/permissive/146399661/src/rng/test.v
None: at end of input
1: b'%Error: data/full_repos/permissive/146399661/src/rng/test.v:2: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/146399661/src/rng,data/full_repos/permissive/146399661/constants.vh\n             data/full_repos/permissive/146399661/src/rng,data/full_repos/permissive/146399661/constants.vh.v\n             data/full_repos/permissive/146399661/src/rng,data/full_repos/permissive/146399661/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rng/test.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rng/test.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rng/test.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rng/test.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rng/test.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/146399661/src/rng/test.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module main;
`include "constants.vh"

reg clk,en,reset;
wire [WORDSIZE-1:0] dataout;

rng rng(clk,en,reset,dataout,ready);

initial begin
    $display("test >> Resetting the RNG chip");
    en = 0;
    reset = 1;
    #10;
    reset= 0;

    en = 1;
    $display("test >> RNG counter is %d", dataout);
    #10;
    $display("test >> RNG counter is %d", dataout);
    #10;
    $display("test >> RNG counter is %d", dataout);
    #10;
end

always begin
    clk = 0;
    #5;
    clk = 1;
    #5;
end
endmodule
module main;

`include "constants.vh"

reg clk,en,reset;
wire [WORDSIZE-1:0] dataout;

rng rng(clk,en,reset,dataout,ready);

initial begin
    $display("test >> Resetting the RNG chip");
    en = 0;
    reset = 1;
    #10;
    reset= 0;

    en = 1;
    $display("test >> RNG counter is %d", dataout);
    #10;
    $display("test >> RNG counter is %d", dataout);
    #10;
    $display("test >> RNG counter is %d", dataout);
    #10;
end

always begin
    clk = 0;
    #5;
    clk = 1;
    #5;
end
endmodule