data/full_repos/permissive/158922207/Verilog Design/modules/ControlRegisters.v
1: b'%Error: Cannot find file containing module: Design/modules,data/full_repos/permissive/158922207\n        ... Looked in:\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.v\n             data/full_repos/permissive/158922207/Verilog/Design/modules,data/full_repos/permissive/158922207.sv\n             Design/modules,data/full_repos/permissive/158922207\n             Design/modules,data/full_repos/permissive/158922207.v\n             Design/modules,data/full_repos/permissive/158922207.sv\n             obj_dir/Design/modules,data/full_repos/permissive/158922207\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.v\n             obj_dir/Design/modules,data/full_repos/permissive/158922207.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/158922207/Verilog\n%Error: Cannot find file containing module: Design/modules/ControlRegisters.v\n%Error: Exiting due to 3 error(s)\n'
module EXControlReg(EX_ALUSrc, EX_RegDest, EX_ALUOp,ALUSrc, RegDest, ALUOp, W_en, reset, clock);
input W_en, reset, clock,ALUSrc;
input [1:0] ALUOp,RegDest;
output EX_ALUSrc;
output [1:0] EX_ALUOp,EX_RegDest;
reg [4:0] mem;

assign EX_ALUSrc = mem[4];
assign EX_RegDest = {mem[3],mem[2]};
assign EX_ALUOp = {mem[1], mem[0]};

always @(posedge clock or posedge reset) begin
if (reset)
    mem <= 5'd0;
else begin
    if(W_en)
       mem <= {ALUSrc, RegDest[1:0], ALUOp[1:0]};
end
end
endmodule
module EXControlReg(EX_ALUSrc, EX_RegDest, EX_ALUOp,ALUSrc, RegDest, ALUOp, W_en, reset, clock);

input W_en, reset, clock,ALUSrc;
input [1:0] ALUOp,RegDest;
output EX_ALUSrc;
output [1:0] EX_ALUOp,EX_RegDest;
reg [4:0] mem;

assign EX_ALUSrc = mem[4];
assign EX_RegDest = {mem[3],mem[2]};
assign EX_ALUOp = {mem[1], mem[0]};

always @(posedge clock or posedge reset) begin
if (reset)
    mem <= 5'd0;
else begin
    if(W_en)
       mem <= {ALUSrc, RegDest[1:0], ALUOp[1:0]};
end
end
endmodule