data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v
 line:71: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #0\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #2  rst = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10  done_data =1\'b1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #2 done_data =1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10  done_data =1\'b1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #1 done_data =1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #10  done_data =1\'b1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #1 done_data =1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:61: Unsupported: Ignoring delay on this delayed statement.\n   #10  done_data =1\'b1; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:63: Unsupported: Ignoring delay on this delayed statement.\n   #2 done_data =1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:64: Unsupported: Ignoring delay on this delayed statement.\n   #10  done_data =1\'b1; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:66: Unsupported: Ignoring delay on this delayed statement.\n   #1 done_data =1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:67: Unsupported: Ignoring delay on this delayed statement.\n   #10  done_data =1\'b1; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:69: Unsupported: Ignoring delay on this delayed statement.\n   #1 done_data =1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #200 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:74: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:76: Cannot find file containing module: \'interfaz_rx\'\n    interfaz_rx \n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/interfaz_rx\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/interfaz_rx.v\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/interfaz_rx.sv\n             interfaz_rx\n             interfaz_rx.v\n             interfaz_rx.sv\n             obj_dir/interfaz_rx\n             obj_dir/interfaz_rx.v\n             obj_dir/interfaz_rx.sv\n%Error: data/full_repos/permissive/205673649/UART/Simulacion/tb_intRx_alu.v:90: Cannot find file containing module: \'ALU\'\n    ALU\n    ^~~\n%Error: Exiting due to 2 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_intRx_alu();


localparam  NB_DBIT_01    =  8;
localparam NB_OPER_01 = 6;


reg  clk;
reg  rst;
reg [NB_DBIT_01-1:0] data;
reg done_data;


wire  signed       [NB_DBIT_01-1:0]        o_data_bus_a;
wire  signed       [NB_DBIT_01-1:0]        o_data_bus_b;
wire  [NB_OPER_01-1:0]    o_data_operador;
wire rx_alu_done;
wire [NB_DBIT_01-1:0] alu_resultado;
wire tx_done_alu;

initial begin
  #0
  rst = 1'b0;
  clk = 1'b0;
  done_data = 1'b0;
  data = 8'b0;
   
  #2  rst = 1'b1;
  #10  done_data =1'b1; 
  data= 8'b00000100;
  #2 done_data =1'b0;
  #10  done_data =1'b1; 
  data= 8'b00000010;
  #1 done_data =1'b0;
  #10  done_data =1'b1; 
  data= 8'b00100000;
  #1 done_data =1'b0;
  
   #10  done_data =1'b1; 
   data= 8'b00000110;
   #2 done_data =1'b0;
   #10  done_data =1'b1; 
   data= 8'b00000011;
   #1 done_data =1'b0;
   #10  done_data =1'b1; 
   data= 8'b00100010;
   #1 done_data =1'b0;
  
  #200 $finish;
end

always #1 clk = ~clk;

    interfaz_rx 
    #(.NB_DATA           (NB_DBIT_01), .NB_OPERADOR(NB_OPER_01))
    u_interfaz_01
    (
      .i_clk (clk),
      .i_rst (rst),
      .i_data (data),
      .i_done_data (done_data),
      .o_rx_alu_done(rx_alu_done),
      .o_a (o_data_bus_a),
      .o_b (o_data_bus_b),
      .o_op (o_data_operador)
    );
    
    ALU
    #(.NB_DATA           (NB_DBIT_01), .NB_OPERADOR(NB_OPER_01))
    u_alu1
    (
     .i_dato_a(o_data_bus_a),
     .i_dato_b(o_data_bus_b),
     .i_operador(o_data_operador),
     .i_alu_valid(rx_alu_done),
     .o_done_alu_tx(tx_done_alu),
     .o_resultado(alu_resultado)  
    );

endmodule
module tb_intRx_alu();



localparam  NB_DBIT_01    =  8;
localparam NB_OPER_01 = 6;


reg  clk;
reg  rst;
reg [NB_DBIT_01-1:0] data;
reg done_data;


wire  signed       [NB_DBIT_01-1:0]        o_data_bus_a;
wire  signed       [NB_DBIT_01-1:0]        o_data_bus_b;
wire  [NB_OPER_01-1:0]    o_data_operador;
wire rx_alu_done;
wire [NB_DBIT_01-1:0] alu_resultado;
wire tx_done_alu;

initial begin
  #0
  rst = 1'b0;
  clk = 1'b0;
  done_data = 1'b0;
  data = 8'b0;
   
  #2  rst = 1'b1;
  #10  done_data =1'b1; 
  data= 8'b00000100;
  #2 done_data =1'b0;
  #10  done_data =1'b1; 
  data= 8'b00000010;
  #1 done_data =1'b0;
  #10  done_data =1'b1; 
  data= 8'b00100000;
  #1 done_data =1'b0;
  
   #10  done_data =1'b1; 
   data= 8'b00000110;
   #2 done_data =1'b0;
   #10  done_data =1'b1; 
   data= 8'b00000011;
   #1 done_data =1'b0;
   #10  done_data =1'b1; 
   data= 8'b00100010;
   #1 done_data =1'b0;
  
  #200 $finish;
end

always #1 clk = ~clk;

    interfaz_rx 
    #(.NB_DATA           (NB_DBIT_01), .NB_OPERADOR(NB_OPER_01))
    u_interfaz_01
    (
      .i_clk (clk),
      .i_rst (rst),
      .i_data (data),
      .i_done_data (done_data),
      .o_rx_alu_done(rx_alu_done),
      .o_a (o_data_bus_a),
      .o_b (o_data_bus_b),
      .o_op (o_data_operador)
    );
    
    ALU
    #(.NB_DATA           (NB_DBIT_01), .NB_OPERADOR(NB_OPER_01))
    u_alu1
    (
     .i_dato_a(o_data_bus_a),
     .i_dato_b(o_data_bus_b),
     .i_operador(o_data_operador),
     .i_alu_valid(rx_alu_done),
     .o_done_alu_tx(tx_done_alu),
     .o_resultado(alu_resultado)  
    );

endmodule