data/full_repos/permissive/150331006/src/Clock_divider.v
data/verilator_xmls/406ea119-b62b-4329-b264-f2a9dc8ba057.xml
module Clock_divider(IN,OUT);
	input IN;
	output reg OUT;
	integer count;
	parameter A = 50000;
	
	initial
		OUT <= 0;
	
	always @(posedge IN)
	begin
		count <= count + 1;
		if (count == A)
		begin
			OUT <= 1;
			count <= 0;
		end
		else
			OUT <= 0;
	end
endmodule
module Clock_divider(IN,OUT);

	input IN;
	output reg OUT;
	integer count;
	parameter A = 50000;
	
	initial
		OUT <= 0;
	
	always @(posedge IN)
	begin
		count <= count + 1;
		if (count == A)
		begin
			OUT <= 1;
			count <= 0;
		end
		else
			OUT <= 0;
	end
endmodule