data/full_repos/permissive/105269489/src/verilog/Test benches/tb_Fsmv.v
'utf-8' codec can't decode byte 0xed in position 215: invalid continuation byte
1: b'%Error: Cannot find file containing module: benches,data/full_repos/permissive/105269489\n        ... Looked in:\n             data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489\n             data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489.v\n             data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489.sv\n             benches,data/full_repos/permissive/105269489\n             benches,data/full_repos/permissive/105269489.v\n             benches,data/full_repos/permissive/105269489.sv\n             obj_dir/benches,data/full_repos/permissive/105269489\n             obj_dir/benches,data/full_repos/permissive/105269489.v\n             obj_dir/benches,data/full_repos/permissive/105269489.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/verilog/Test\n%Error: Cannot find file containing module: benches/tb_Fsmv.v\n%Error: Exiting due to 3 error(s)\n'
module tb_FSM();	

	parameter NB_ADDRESS= 10;

    parameter NB_IMAGE  = 10;



    reg                    	CLK;
    reg                    	reset;
    reg                    	SOP;
    reg [NB_IMAGE-1:0]     	imgLength;
    reg                    	valid;
    reg 					load; 
    wire [NB_ADDRESS-1:0]  	writeAddress;
    wire [NB_ADDRESS-1:0]  	readAddress;
    wire                   	EOP;
    wire                   	chblock;
    wire 					vld;
    integer i;
	initial	begin
		CLK       = 1'b0;
		SOP       = 1'b0;	
		imgLength = 10'hf;
		valid     = 1'b0;
		load 	  = 1'b0;
		reset     = 1'b1;		
		#10 reset = 1'b0;

		#5 load = 1'b1; 
		
		for(i=0; i<= imgLength; i=i+1)begin
			#5 valid = 1'b1;
			#5 valid = 1'b0;
		end
		load = 1'b0;	



		
		#30 SOP = 1'b1;
		#20 SOP = 1'b0;

		#200 $finish;
	end
	always #2.5 CLK=~CLK;

	Fsmv#(  
		.NB_ADDRESS(NB_ADDRESS),
		.NB_IMAGE (NB_IMAGE),
		.N_CONV (4))
		u_Fsmv(
			.o_readAdd(readAddress),
			.o_writeAdd(writeAddress),
			.o_EoP(EOP),
			.o_changeBlock(chblock),
			.o_fms2conVld(vld),
			.i_CLK(CLK),
			.i_reset(reset),
			.i_SoP(SOP),
			.i_imgLength(imgLength),
			.i_valid(valid),
			.i_load(load));


endmodule
module tb_FSM();
	

	parameter NB_ADDRESS= 10;

    parameter NB_IMAGE  = 10;



    reg                    	CLK;
    reg                    	reset;
    reg                    	SOP;
    reg [NB_IMAGE-1:0]     	imgLength;
    reg                    	valid;
    reg 					load; 
    wire [NB_ADDRESS-1:0]  	writeAddress;
    wire [NB_ADDRESS-1:0]  	readAddress;
    wire                   	EOP;
    wire                   	chblock;
    wire 					vld;
    integer i;
	initial	begin
		CLK       = 1'b0;
		SOP       = 1'b0;	
		imgLength = 10'hf;
		valid     = 1'b0;
		load 	  = 1'b0;
		reset     = 1'b1;		
		#10 reset = 1'b0;

		#5 load = 1'b1; 
		
		for(i=0; i<= imgLength; i=i+1)begin
			#5 valid = 1'b1;
			#5 valid = 1'b0;
		end
		load = 1'b0;	



		
		#30 SOP = 1'b1;
		#20 SOP = 1'b0;

		#200 $finish;
	end
	always #2.5 CLK=~CLK;

	Fsmv#(  
		.NB_ADDRESS(NB_ADDRESS),
		.NB_IMAGE (NB_IMAGE),
		.N_CONV (4))
		u_Fsmv(
			.o_readAdd(readAddress),
			.o_writeAdd(writeAddress),
			.o_EoP(EOP),
			.o_changeBlock(chblock),
			.o_fms2conVld(vld),
			.i_CLK(CLK),
			.i_reset(reset),
			.i_SoP(SOP),
			.i_imgLength(imgLength),
			.i_valid(valid),
			.i_load(load));


endmodule