data/full_repos/permissive/114553631/test/test_F_reg.v
 line:42: before: "$"
1: b'%Error: data/full_repos/permissive/114553631/test/test_F_reg.v:6: Cannot find include file: ../src/F_reg.v\n`include "../src/F_reg.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/F_reg.v\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/F_reg.v.v\n             data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/F_reg.v.sv\n             ../src/F_reg.v\n             ../src/F_reg.v.v\n             ../src/F_reg.v.sv\n             obj_dir/../src/F_reg.v\n             obj_dir/../src/F_reg.v.v\n             obj_dir/../src/F_reg.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:18: Unsupported: Ignoring delay on this delayed statement.\n    initial #stop_time $finish;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:42: Unsupported: Ignoring delay on this delayed statement.\n            #10 clk = ~clk;\n            ^\n%Error: data/full_repos/permissive/114553631/test/test_F_reg.v:46: Unsupported or unknown PLI call: $monitor\n        $monitor("time = ", $time, "F_ValP=%d, F_stall=%d, f_valP=%d", F_valP, F_stall, f_valP);\n        ^~~~~~~~\n%Error: Exiting due to 2 error(s), 10 warning(s)\n'
module test_F_reg;
    reg [31:0] f_valP = 0;
    reg clk = 0;
    reg F_stall = 0;
    wire [31:0] F_valP;

    parameter stop_time = 80;

    F_reg FREG(F_valP, f_valP, clk, F_stall);

    initial #stop_time $finish;
    
    initial begin
        #10;
        f_valP = 4;
        #10;
        f_valP = 8;
        #10;
        F_stall = 1;
        f_valP = 12;
        #10;
        f_valP = 16;
        #10;
        f_valP = 20;
        #10;
        F_stall = 0;
        f_valP = 24;
        #10;
        f_valP = 28;
        #10;
    end

    initial begin
        repeat(8)
            #10 clk = ~clk;
    end

    initial begin
        $monitor("time = ", $time, "F_ValP=%d, F_stall=%d, f_valP=%d", F_valP, F_stall, f_valP);
    end

endmodule
module test_F_reg;

    reg [31:0] f_valP = 0;
    reg clk = 0;
    reg F_stall = 0;
    wire [31:0] F_valP;

    parameter stop_time = 80;

    F_reg FREG(F_valP, f_valP, clk, F_stall);

    initial #stop_time $finish;
    
    initial begin
        #10;
        f_valP = 4;
        #10;
        f_valP = 8;
        #10;
        F_stall = 1;
        f_valP = 12;
        #10;
        f_valP = 16;
        #10;
        f_valP = 20;
        #10;
        F_stall = 0;
        f_valP = 24;
        #10;
        f_valP = 28;
        #10;
    end

    initial begin
        repeat(8)
            #10 clk = ~clk;
    end

    initial begin
        $monitor("time = ", $time, "F_ValP=%d, F_stall=%d, f_valP=%d", F_valP, F_stall, f_valP);
    end

endmodule