data/full_repos/permissive/152581089/Verilog/MSP430/io_cell.v
data/verilator_xmls/6dce0a2e-9bd7-45b8-a00a-dd2dea337bee.xml
module  io_cell (


    pad,
		 

    data_in,


    data_out_en,
    data_out
);



inout          pad;



output         data_in;



input          data_out_en;
input          data_out;






assign  data_in  =  pad;
assign  pad      =  data_out_en ? data_out : 1'bz;


endmodule
module  io_cell (


    pad,
		 

    data_in,


    data_out_en,
    data_out
);




inout          pad;



output         data_in;



input          data_out_en;
input          data_out;






assign  data_in  =  pad;
assign  pad      =  data_out_en ? data_out : 1'bz;


endmodule