data/full_repos/permissive/142844950/rtl/b_lut/b_lut_ftb.v
 line:24: before: "("
1: b'%Error: data/full_repos/permissive/142844950/rtl/b_lut/b_lut_ftb.v:14: Unsupported or unknown PLI call: $anyseq\nreg  [31:0]  crs1    = $anyseq;\n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/b_lut/b_lut_ftb.v:15: Unsupported or unknown PLI call: $anyseq\nreg  [31:0]  crs2    = $anyseq;\n                       ^~~~~~~\n%Error: data/full_repos/permissive/142844950/rtl/b_lut/b_lut_ftb.v:16: Unsupported or unknown PLI call: $anyseq\nreg  [31:0]  crs3    = $anyseq;\n                       ^~~~~~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module b_lut_ftb(

input clock,
input reset

);

reg  [31:0]  crs1    = $anyseq;
reg  [31:0]  crs2    = $anyseq;
reg  [31:0]  crs3    = $anyseq;

wire [31:0]  result     ;
wire [31:0]  expectation;


always @(posedge clock) begin

    assert(result == expectation);

    if(crs1 == 32'h01234567 &&
       crs2 == 32'h76543210 &&
       crs2 == 32'hfedcba98 ) begin
        assert(result == 32'h76543210);
    end
    
    if(crs1 == 32'h012345a7 &&
       crs2 == 32'h76543210 &&
       crs2 == 32'hfedcb198 ) begin
        assert(result == 32'h76543210);
    end

end


b_lut_checker i_b_lut_checker(
.crs1  (crs1  ),
.crs2  (crs2  ),
.crs3  (crs3  ),
.result(expectation)
);


b_lut i_b_lut(
.crs1  (crs1  ),
.crs2  (crs2  ),
.crs3  (crs3  ),
.result(result)
);


endmodule
module b_lut_ftb(

input clock,
input reset

);


reg  [31:0]  crs1    = $anyseq;
reg  [31:0]  crs2    = $anyseq;
reg  [31:0]  crs3    = $anyseq;

wire [31:0]  result     ;
wire [31:0]  expectation;


always @(posedge clock) begin

    assert(result == expectation);

    if(crs1 == 32'h01234567 &&
       crs2 == 32'h76543210 &&
       crs2 == 32'hfedcba98 ) begin
        assert(result == 32'h76543210);
    end
    
    if(crs1 == 32'h012345a7 &&
       crs2 == 32'h76543210 &&
       crs2 == 32'hfedcb198 ) begin
        assert(result == 32'h76543210);
    end

end


b_lut_checker i_b_lut_checker(
.crs1  (crs1  ),
.crs2  (crs2  ),
.crs3  (crs3  ),
.result(expectation)
);


b_lut i_b_lut(
.crs1  (crs1  ),
.crs2  (crs2  ),
.crs3  (crs3  ),
.result(result)
);


endmodule