data/full_repos/permissive/171279647/hdl/basic/bitonic_node.v
1: b"%Error: data/full_repos/permissive/171279647/hdl/basic/bitonic_node.v:66: Cannot find file containing module: 'bitonic_comp'\n bitonic_comp #(\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/171279647/hdl/basic,data/full_repos/permissive/171279647/bitonic_comp\n             data/full_repos/permissive/171279647/hdl/basic,data/full_repos/permissive/171279647/bitonic_comp.v\n             data/full_repos/permissive/171279647/hdl/basic,data/full_repos/permissive/171279647/bitonic_comp.sv\n             bitonic_comp\n             bitonic_comp.v\n             bitonic_comp.sv\n             obj_dir/bitonic_comp\n             obj_dir/bitonic_comp.v\n             obj_dir/bitonic_comp.sv\n%Error: Exiting due to 1 error(s)\n"
module bitonic_node #(
	parameter DATA_WIDTH = 16,
	parameter ORDER = 0,
	parameter POLARITY = 0,
	parameter SIGNED = 0
)
(
	input wire clk,
	input wire [DATA_WIDTH*2**(ORDER+1)-1:0]data_in,
	output wire [DATA_WIDTH*2**(ORDER+1)-1:0]data_out
);

localparam COMP_NUM = 2**ORDER;

genvar i;

generate for (i = 0; i < COMP_NUM; i = i + 1) begin: COMP
	wire [DATA_WIDTH-1:0]A;
	wire [DATA_WIDTH-1:0]B;
	wire [DATA_WIDTH-1:0]H;
	wire [DATA_WIDTH-1:0]L;
	
	assign A = data_in[DATA_WIDTH*(i + 1 + COMP_NUM * 0)-1-:DATA_WIDTH];
	assign B = data_in[DATA_WIDTH*(i + 1 + COMP_NUM * 1)-1-:DATA_WIDTH];
	assign data_out[DATA_WIDTH*(i + 1 + COMP_NUM * 0)-1-:DATA_WIDTH] = H;
	assign data_out[DATA_WIDTH*(i + 1 + COMP_NUM * 1)-1-:DATA_WIDTH] = L;

	bitonic_comp #(
		.DATA_WIDTH(DATA_WIDTH),
		.POLARITY(POLARITY),
		.SIGNED(SIGNED)
	) comp_inst (
		.CLK(clk),
		.A(A),
		.B(B),
		.H(H),
		.L(L)
	);
end endgenerate

endmodule
module bitonic_node #(
	parameter DATA_WIDTH = 16,
	parameter ORDER = 0,
	parameter POLARITY = 0,
	parameter SIGNED = 0
)
(
	input wire clk,
	input wire [DATA_WIDTH*2**(ORDER+1)-1:0]data_in,
	output wire [DATA_WIDTH*2**(ORDER+1)-1:0]data_out
);


localparam COMP_NUM = 2**ORDER;

genvar i;

generate for (i = 0; i < COMP_NUM; i = i + 1) begin: COMP
	wire [DATA_WIDTH-1:0]A;
	wire [DATA_WIDTH-1:0]B;
	wire [DATA_WIDTH-1:0]H;
	wire [DATA_WIDTH-1:0]L;
	
	assign A = data_in[DATA_WIDTH*(i + 1 + COMP_NUM * 0)-1-:DATA_WIDTH];
	assign B = data_in[DATA_WIDTH*(i + 1 + COMP_NUM * 1)-1-:DATA_WIDTH];
	assign data_out[DATA_WIDTH*(i + 1 + COMP_NUM * 0)-1-:DATA_WIDTH] = H;
	assign data_out[DATA_WIDTH*(i + 1 + COMP_NUM * 1)-1-:DATA_WIDTH] = L;

	bitonic_comp #(
		.DATA_WIDTH(DATA_WIDTH),
		.POLARITY(POLARITY),
		.SIGNED(SIGNED)
	) comp_inst (
		.CLK(clk),
		.A(A),
		.B(B),
		.H(H),
		.L(L)
	);
end endgenerate

endmodule