data/full_repos/permissive/175808891/verilog/rv32cpu.v
1: b"%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:234: syntax error, unexpected type\n    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));\n                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:285: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\nmodule shifter(input[31:0] a, input [4:0] shamt, input[1:0] type,  output [31:0] r);\n                                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:288: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:343: syntax error, unexpected ',', expecting IDENTIFIER or do or final\n input   wire            int,\n                            ^\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:345: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input   wire            nmi\n ^~~~~\n%Error: data/full_repos/permissive/175808891/verilog/rv32cpu.v:369: syntax error, unexpected always\nalways @(posedge clk or posedge rst)\n^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module ALU(
	input   wire [31:0] a, b,
	input   wire [4:0]  shamt,
	output  reg  [31:0] r,
	output  wire        cf, zf, vf, sf,
	input   wire [3:0]  alufn
);

    wire [31:0] add, sub, op_b;
    wire cfa, cfs;
    
    assign op_b = (~b);
    
    assign {cf, add} = alufn[0] ? (a + op_b + 1'b1) : (a + b);
    
    assign zf = (add == 0);
    assign sf = add[31];
    assign vf = (a[31] ^ (op_b[31]) ^ add[31] ^ cf);
    
    wire[31:0] sh;
    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));
    
    always @ * begin
        r = 0;
        
        case (alufn)	

            4'b00_00 : r = add;
            4'b00_01 : r = add;
            4'b00_11 : r = b;

            4'b01_00:  r = a | b;
            4'b01_01:  r = a & b;
            4'b01_11:  r = a ^ b;

            4'b10_00:  r=sh;
            4'b10_01:  r=sh;
            4'b10_10:  r=sh;

            4'b11_01:  r = {31'b0,(sf != vf)}; 
            4'b11_11:  r = {31'b0,(~cf)};            	
        endcase
    end
endmodule
module ALU(
	input   wire [31:0] a, b,
	input   wire [4:0]  shamt,
	output  reg  [31:0] r,
	output  wire        cf, zf, vf, sf,
	input   wire [3:0]  alufn
);


    wire [31:0] add, sub, op_b;
    wire cfa, cfs;
    
    assign op_b = (~b);
    
    assign {cf, add} = alufn[0] ? (a + op_b + 1'b1) : (a + b);
    
    assign zf = (add == 0);
    assign sf = add[31];
    assign vf = (a[31] ^ (op_b[31]) ^ add[31] ^ cf);
    
    wire[31:0] sh;
    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));
    
    always @ * begin
        r = 0;
        
        case (alufn)	

            4'b00_00 : r = add;
            4'b00_01 : r = add;
            4'b00_11 : r = b;

            4'b01_00:  r = a | b;
            4'b01_01:  r = a & b;
            4'b01_11:  r = a ^ b;

            4'b10_00:  r=sh;
            4'b10_01:  r=sh;
            4'b10_10:  r=sh;

            4'b11_01:  r = {31'b0,(sf != vf)}; 
            4'b11_11:  r = {31'b0,(~cf)};            	
        endcase
    end
endmodule