data/full_repos/permissive/169294490/FPGA/src/VGA/vga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169294490/FPGA/src/VGA/vga.v:41: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                          : ... In instance vga_controller.hs\n reg [10:0] count = 10\'b0000000000;\n                    ^~~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169294490/FPGA/src/VGA/vga.v:6: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                         : ... In instance vga_controller.vs\n reg [10:0] count = 10\'b0000000000;\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169294490/FPGA/src/VGA/vga.v:102: Cannot find file containing module: \'framebuffer\'\n framebuffer   fb(clk50, rst, blank, red_out, green_out, blue_out, line_clk, vblank, fb_data, fb_addr, fb_we, framebuffer_addr_rd, framebuffer_data_rd, framebuffer_rd_en);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169294490/FPGA/src/VGA,data/full_repos/permissive/169294490/framebuffer\n             data/full_repos/permissive/169294490/FPGA/src/VGA,data/full_repos/permissive/169294490/framebuffer.v\n             data/full_repos/permissive/169294490/FPGA/src/VGA,data/full_repos/permissive/169294490/framebuffer.sv\n             framebuffer\n             framebuffer.v\n             framebuffer.sv\n             obj_dir/framebuffer\n             obj_dir/framebuffer.v\n             obj_dir/framebuffer.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module hsync(clk50, hsync_out, blank_out, newline_out);
	input clk50;
	output hsync_out, blank_out, newline_out;

	reg [10:0] count = 10'b0000000000;
	reg hsync 	= 0;
	reg blank 	= 0;
	reg newline 	= 0;

	always @(posedge clk50)
	begin
		if (count < 1040)
			count  <= count + 11'h1;
		else
			count  <= 0;
	end

	always @(posedge clk50)
	begin
		if (count == 0)
			newline <= 1;
		else
			newline <= 0;
	end

	always @(posedge clk50)
	begin
		if (count >= 800)
			blank  <= 1;
		else
			blank  <= 0;
	end

	always @(posedge clk50)
	begin
		if (count < 856)
			hsync <= 1;
		else if (count >= 856 && count < 976)
			hsync <= 0;
		else if (count >= 976)
			hsync <= 1;
	end
				 
   assign hsync_out    = hsync;
	assign blank_out    = blank;
	assign newline_out  = newline;

endmodule
module hsync(clk50, hsync_out, blank_out, newline_out);

	input clk50;
	output hsync_out, blank_out, newline_out;

	reg [10:0] count = 10'b0000000000;
	reg hsync 	= 0;
	reg blank 	= 0;
	reg newline 	= 0;

	always @(posedge clk50)
	begin
		if (count < 1040)
			count  <= count + 11'h1;
		else
			count  <= 0;
	end

	always @(posedge clk50)
	begin
		if (count == 0)
			newline <= 1;
		else
			newline <= 0;
	end

	always @(posedge clk50)
	begin
		if (count >= 800)
			blank  <= 1;
		else
			blank  <= 0;
	end

	always @(posedge clk50)
	begin
		if (count < 856)
			hsync <= 1;
		else if (count >= 856 && count < 976)
			hsync <= 0;
		else if (count >= 976)
			hsync <= 1;
	end
				 
   assign hsync_out    = hsync;
	assign blank_out    = blank;
	assign newline_out  = newline;

endmodule