data/full_repos/permissive/191827066/nica/verilog/ddr_address_mapping.v
1: b'%Warning-WIDTH: data/full_repos/permissive/191827066/nica/verilog/ddr_address_mapping.v:262: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s SEL generates 10 bits.\n                                                                                           : ... In instance ddr_address_mapping\n  assign map_wraddr = ddr_adrs_map_ctrl[0] ? map_wraddr_test_mode : ik2map_addr[40:31];\n                                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/191827066/nica/verilog/ddr_address_mapping.v:263: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s SEL generates 10 bits.\n                                                                                           : ... In instance ddr_address_mapping\n  assign map_rdaddr = ddr_adrs_map_ctrl[16] ? map_rdaddr_test_mode : ik2map_addr[40:31];\n                                            ^\n%Error: data/full_repos/permissive/191827066/nica/verilog/ddr_address_mapping.v:457: Cannot find file containing module: \'ddr_adrs_mapping\'\nddr_adrs_mapping ddr_addr_table (\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191827066/nica/verilog,data/full_repos/permissive/191827066/ddr_adrs_mapping\n             data/full_repos/permissive/191827066/nica/verilog,data/full_repos/permissive/191827066/ddr_adrs_mapping.v\n             data/full_repos/permissive/191827066/nica/verilog,data/full_repos/permissive/191827066/ddr_adrs_mapping.sv\n             ddr_adrs_mapping\n             ddr_adrs_mapping.v\n             ddr_adrs_mapping.sv\n             obj_dir/ddr_adrs_mapping\n             obj_dir/ddr_adrs_mapping.v\n             obj_dir/ddr_adrs_mapping.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module ddr_address_mapping #(
parameter
    AXILITE_ADDR_WIDTH = 13,
    AXILITE_DATA_WIDTH = 32
)(
    input wire 				  clk,
    input wire 				  reset,




    input wire 				  rdwr_mode,


    input wire [AXILITE_ADDR_WIDTH-1:0]   axi_AWADDR,
    input wire 				  axi_AWVALID,
    output wire 			  axi_AWREADY,
    input wire [AXILITE_DATA_WIDTH-1:0]   axi_WDATA,
    input wire 				  axi_WVALID,
    output wire 			  axi_WREADY,
    input wire [AXILITE_DATA_WIDTH/8-1:0] axi_WSTRB,
    output wire 			  axi_BVALID,
    input wire 				  axi_BREADY,
    output wire [1:0] 			  axi_BRESP,


    output 				  ik2map_rdy,
    input 				  ik2map_vld,
    input [63:0] 			  ik2map_addr,
    input [1:0] 			  ik2map_burst,
    input [3:0] 			  ik2map_cache,
    input [2:0] 			  ik2map_id,
    input [7:0] 			  ik2map_len,
    input [1:0] 			  ik2map_lock,
    input [2:0] 			  ik2map_prot,
    input [3:0] 			  ik2map_qos,
    input [3:0] 			  ik2map_region,
    input [2:0] 			  ik2map_size,


    input 				  map2ddr_rdy,
    output 				  map2ddr_vld,



    output [31:0] 			  map2ddr_addr,
    output [1:0] 			  map2ddr_burst,
    output [3:0] 			  map2ddr_cache,
    output [2:0] 			  map2ddr_id,
    output [7:0] 			  map2ddr_len,
    output [1:0] 			  map2ddr_lock,
    output [2:0] 			  map2ddr_prot,
    output [3:0] 			  map2ddr_qos,
    output [3:0] 			  map2ddr_region,
    output [2:0] 			  map2ddr_size
  
  );

  
localparam
    WRIDLE                     = 2'd0,
    WRDATA                     = 2'd1,
    WRRESP                     = 2'd2,
    RDIDLE                     = 2'd0,
    RDDATA                     = 2'd1;

localparam
  DDR_ADDR_MAP_START      = 13'h1000,
  DDR_ADDR_MAP_END        = 13'h1400,
  DDR_ADDR_MAP_CTRL       = 13'h1800,
  DDR_ADDR_MAP_WRBASE0    = 13'h1810,
  DDR_ADDR_MAP_WRBASE1    = 13'h1814,
  DDR_ADDR_MAP_RDBASE0    = 13'h1818,
  DDR_ADDR_MAP_RDBASE1    = 13'h181c;

  wire 	      axi_aw_hs;
  wire 	      axi_w_hs;
  reg [1:0]   axi_wstate;
  reg [1:0]   axi_wnext;
  reg 	      ddr_adrs_table_wr;
  reg [AXILITE_ADDR_WIDTH-1 : 0] axi_waddr;
  reg [31:0] 			 ddr_adrs_table_datain;

  wire [9:0] map_addr;
  wire [31:0] map_out;
  reg [31:0]  stage3_map;
  wire 	      stage1_enable;
  reg 	      stage1_vld;
  wire 	      stage1_rdy;
  wire	      stage2_enable;
  reg 	      stage2_vld;
  wire 	      stage2_rdy;
  wire	      stage3_enable;
  reg 	      stage3_vld;
  wire 	      stage3_rdy;
  wire	      stage4_enable;
  reg 	      stage4_vld;
  wire 	      stage4_rdy;

  reg [31:0]  stage1_addr;
  reg [1:0]   stage1_burst;
  reg [3:0]   stage1_cache;
  reg [2:0]   stage1_id;
  reg [7:0]   stage1_len;
  reg [1:0]   stage1_lock;
  reg [2:0]   stage1_prot;
  reg [3:0]   stage1_qos;
  reg [3:0]   stage1_region;
  reg [2:0]   stage1_size;

  reg [31:0]  stage2_addr;
  reg [1:0]   stage2_burst;
  reg [3:0]   stage2_cache;
  reg [2:0]   stage2_id;
  reg [7:0]   stage2_len;
  reg [1:0]   stage2_lock;
  reg [2:0]   stage2_prot;
  reg [3:0]   stage2_qos;
  reg [3:0]   stage2_region;
  reg [2:0]   stage2_size;

  reg [31:0]  stage3_addr;
  reg [1:0]   stage3_burst;
  reg [3:0]   stage3_cache;
  reg [2:0]   stage3_id;
  reg [7:0]   stage3_len;
  reg [1:0]   stage3_lock;
  reg [2:0]   stage3_prot;
  reg [3:0]   stage3_qos;
  reg [3:0]   stage3_region;
  reg [2:0]   stage3_size;

  reg [31:0]  stage4_addr;
  reg [1:0]   stage4_burst;
  reg [3:0]   stage4_cache;
  reg [2:0]   stage4_id;
  reg [7:0]   stage4_len;
  reg [1:0]   stage4_lock;
  reg [2:0]   stage4_prot;
  reg [3:0]   stage4_qos;
  reg [3:0]   stage4_region;
  reg [2:0]   stage4_size;
  






















  reg [31:0] 			 ddr_adrs_map_ctrl;
  reg [31:0] 			 ddr_adrs_map_wrbase0;
  reg [31:0] 			 ddr_adrs_map_wrbase1;
  reg [31:0] 			 ddr_adrs_map_rdbase0;
  reg [31:0] 			 ddr_adrs_map_rdbase1;
  reg 				 ddr_adrs_map_wr_toggle;
  reg 				 ddr_adrs_map_rd_toggle;
  wire [31:0] 			 map_wraddr_test_mode;
  wire [31:0] 			 map_wraddr;
  wire [31:0] 			 map_rdaddr_test_mode;
  wire [31:0] 			 map_rdaddr;
  
  always @(posedge clk) begin
    if (reset) begin
      ddr_adrs_map_wr_toggle <= 1'b0;
      ddr_adrs_map_rd_toggle <= 1'b0;
    end
    else begin
      if (ik2map_rdy & ik2map_vld) begin
	ddr_adrs_map_rd_toggle <= rdwr_mode ? ddr_adrs_map_rd_toggle + 1 : ddr_adrs_map_rd_toggle;
	ddr_adrs_map_wr_toggle <= rdwr_mode ? ddr_adrs_map_wr_toggle : ddr_adrs_map_wr_toggle + 1;
      end
    end
  end
  


  assign map_wraddr_test_mode = ddr_adrs_map_wr_toggle ? ddr_adrs_map_wrbase1 : ddr_adrs_map_wrbase0;
  assign map_rdaddr_test_mode = ddr_adrs_map_rd_toggle ? ddr_adrs_map_rdbase1 : ddr_adrs_map_rdbase0;




  


  assign map_wraddr = ddr_adrs_map_ctrl[0] ? map_wraddr_test_mode : ik2map_addr[40:31];
  assign map_rdaddr = ddr_adrs_map_ctrl[16] ? map_rdaddr_test_mode : ik2map_addr[40:31];
  assign map_addr = ~rdwr_mode ? map_wraddr[9:0] : map_rdaddr[9:0];



  assign axi_AWREADY = (axi_wstate == WRIDLE);
  assign axi_WREADY  = (axi_wstate == WRDATA);
  assign axi_BRESP   = 2'b00;
  assign axi_BVALID  = (axi_wstate == WRRESP);
  assign axi_aw_hs   = axi_AWVALID & axi_AWREADY;
  assign axi_w_hs    = axi_WVALID & axi_WREADY;
  

  always @(posedge clk) begin
    if (reset)
      axi_wstate <= WRIDLE;
    else
      axi_wstate <= axi_wnext;
  end
  

  always @(*) begin
    case (axi_wstate)
      WRIDLE:
        if (axi_AWVALID)
          axi_wnext = WRDATA;
        else
          axi_wnext = WRIDLE;
      WRDATA:
        if (axi_WVALID)
          axi_wnext = WRRESP;
        else
          axi_wnext = WRDATA;
      WRRESP:
        if (axi_BREADY)
          axi_wnext = WRIDLE;
        else
          axi_wnext = WRRESP;
      default:
        axi_wnext = WRIDLE;
    endcase
  end
  

  always @(posedge clk) begin
    if (axi_aw_hs)
      axi_waddr <= axi_AWADDR[AXILITE_ADDR_WIDTH-1 : 0];
  end
  

  always @(posedge clk) begin
    if (reset) begin
      ddr_adrs_table_wr <= 1'b0;
      ddr_adrs_map_ctrl <= 32'h00000000;
      ddr_adrs_map_wrbase0 <= 32'h00000000;
      ddr_adrs_map_wrbase1 <= 32'h00000000;
      ddr_adrs_map_rdbase0 <= 32'h00000000;
      ddr_adrs_map_rdbase1 <= 32'h00000000;
    end
    else
      begin
	if (axi_w_hs && axi_waddr >= DDR_ADDR_MAP_START && axi_waddr < DDR_ADDR_MAP_END) begin
	  ddr_adrs_table_wr <= 1'b1;
	  ddr_adrs_table_datain <= axi_WDATA;
	end
	else
	  ddr_adrs_table_wr <= 1'b0;
	
	if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_CTRL)
	  ddr_adrs_map_ctrl <= axi_WDATA;
	if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_WRBASE0)
	  ddr_adrs_map_wrbase0 <= axi_WDATA;
	if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_WRBASE1)
	  ddr_adrs_map_wrbase1 <= axi_WDATA;
	if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_RDBASE0)
	  ddr_adrs_map_rdbase0 <= axi_WDATA;
	if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_RDBASE1)
	  ddr_adrs_map_rdbase1 <= axi_WDATA;
      end
  end
  


  assign ik2map_rdy = stage1_rdy;
  
  assign stage1_enable = ik2map_vld & ik2map_rdy;
  assign stage1_rdy = ~stage1_vld | stage2_rdy;

  assign stage2_enable = stage1_vld & stage2_rdy;
  assign stage2_rdy = ~stage2_vld | stage3_rdy;

  assign stage3_enable = stage2_vld & stage3_rdy;
  assign stage3_rdy = ~stage3_vld | stage4_rdy;

  assign stage4_enable = stage3_vld & stage4_rdy;
  assign stage4_rdy = ~stage4_vld | map2ddr_rdy;

  assign map2ddr_vld = stage4_vld;
  assign map2ddr_addr = stage4_addr;
  assign map2ddr_burst = stage4_burst;
  assign map2ddr_cache = stage4_cache;
  assign map2ddr_id = stage4_id;
  assign map2ddr_len = stage4_len;
  assign map2ddr_lock = stage4_lock;
  assign map2ddr_prot = stage4_prot;
  assign map2ddr_qos = stage4_qos;
  assign map2ddr_region = stage4_region;
  assign map2ddr_size = stage4_size;
  
  
always @(posedge clk) begin
  if (reset) begin
    stage1_vld <= 1'b0;
    stage2_vld <= 1'b0;
    stage3_vld <= 1'b0;
    stage4_vld <= 1'b0;
  end
  else begin
    if (stage1_enable) begin
      stage1_addr <= {1'b0, ik2map_addr[30:0]};
      stage1_burst <= ik2map_burst;
      stage1_cache <= ik2map_cache;
      stage1_id <= ik2map_id;
      stage1_len <= ik2map_len;
      stage1_lock <= ik2map_lock;
      stage1_prot <= ik2map_prot;
      stage1_qos <= ik2map_qos;
      stage1_region <= ik2map_region;
      stage1_size <= ik2map_size;
      stage1_vld <= 1'b1;
    end
    else if (stage1_vld & stage2_rdy) begin
      stage1_vld <= 1'b0;
    end

    if (stage2_enable) begin
      stage2_addr <= {1'b0, stage1_addr[30:0]};
      stage2_burst <= stage1_burst;
      stage2_cache <= stage1_cache;
      stage2_id <= stage1_id;
      stage2_len <= stage1_len;
      stage2_lock <= stage1_lock;
      stage2_prot <= stage1_prot;
      stage2_qos <= stage1_qos;
      stage2_region <= stage1_region;
      stage2_size <= stage1_size;
      stage2_vld <= 1'b1;
    end
    else if (stage2_vld & stage3_rdy) begin
      stage2_vld <= 1'b0;
    end

    if (stage3_enable) begin
      stage3_map <= map_out;
      stage3_addr <= {1'b0, stage2_addr[30:0]};
      stage3_burst <= stage2_burst;
      stage3_cache <= stage2_cache;
      stage3_id <= stage2_id;
      stage3_len <= stage2_len;
      stage3_lock <= stage2_lock;
      stage3_prot <= stage2_prot;
      stage3_qos <= stage2_qos;
      stage3_region <= stage2_region;
      stage3_size <= stage2_size;
      stage3_vld <= 1'b1;
    end
    else if (stage3_vld & stage4_rdy) begin
      stage3_vld <= 1'b0;
    end

    if (stage4_enable) begin

      stage4_addr <= {1'b0, stage3_addr[30:12] + stage3_map[18:0] , stage3_addr[11:0]};

      stage4_burst <= stage3_burst;
      stage4_cache <= stage3_cache;
      stage4_id <= stage3_id;
      stage4_len <= stage3_len;
      stage4_lock <= stage3_lock;
      stage4_prot <= stage3_prot;
      stage4_qos <= stage3_qos;
      stage4_region <= stage3_region;
      stage4_size <= stage3_size;
      stage4_vld <= 1'b1;
    end

    else if (stage4_vld & map2ddr_rdy) begin
      stage4_vld <= 1'b0;
    end

  end
end

  
ddr_adrs_mapping ddr_addr_table (
  .clka(clk),


  .addra({2'b0, axi_waddr[9:2]}),
  .wea(ddr_adrs_table_wr),
  .dina(ddr_adrs_table_datain),



  .clkb(clk),
  .addrb(map_addr),



  .doutb(map_out)
);
  
endmodule
module ddr_address_mapping #(
parameter
    AXILITE_ADDR_WIDTH = 13,
    AXILITE_DATA_WIDTH = 32
)(
    input wire 				  clk,
    input wire 				  reset,




    input wire 				  rdwr_mode,


    input wire [AXILITE_ADDR_WIDTH-1:0]   axi_AWADDR,
    input wire 				  axi_AWVALID,
    output wire 			  axi_AWREADY,
    input wire [AXILITE_DATA_WIDTH-1:0]   axi_WDATA,
    input wire 				  axi_WVALID,
    output wire 			  axi_WREADY,
    input wire [AXILITE_DATA_WIDTH/8-1:0] axi_WSTRB,
    output wire 			  axi_BVALID,
    input wire 				  axi_BREADY,
    output wire [1:0] 			  axi_BRESP,


    output 				  ik2map_rdy,
    input 				  ik2map_vld,
    input [63:0] 			  ik2map_addr,
    input [1:0] 			  ik2map_burst,
    input [3:0] 			  ik2map_cache,
    input [2:0] 			  ik2map_id,
    input [7:0] 			  ik2map_len,
    input [1:0] 			  ik2map_lock,
    input [2:0] 			  ik2map_prot,
    input [3:0] 			  ik2map_qos,
    input [3:0] 			  ik2map_region,
    input [2:0] 			  ik2map_size,


    input 				  map2ddr_rdy,
    output 				  map2ddr_vld,



    output [31:0] 			  map2ddr_addr,
    output [1:0] 			  map2ddr_burst,
    output [3:0] 			  map2ddr_cache,
    output [2:0] 			  map2ddr_id,
    output [7:0] 			  map2ddr_len,
    output [1:0] 			  map2ddr_lock,
    output [2:0] 			  map2ddr_prot,
    output [3:0] 			  map2ddr_qos,
    output [3:0] 			  map2ddr_region,
    output [2:0] 			  map2ddr_size
  
  );


  
localparam
    WRIDLE                     = 2'd0,
    WRDATA                     = 2'd1,
    WRRESP                     = 2'd2,
    RDIDLE                     = 2'd0,
    RDDATA                     = 2'd1;

localparam
  DDR_ADDR_MAP_START      = 13'h1000,
  DDR_ADDR_MAP_END        = 13'h1400,
  DDR_ADDR_MAP_CTRL       = 13'h1800,
  DDR_ADDR_MAP_WRBASE0    = 13'h1810,
  DDR_ADDR_MAP_WRBASE1    = 13'h1814,
  DDR_ADDR_MAP_RDBASE0    = 13'h1818,
  DDR_ADDR_MAP_RDBASE1    = 13'h181c;

  wire 	      axi_aw_hs;
  wire 	      axi_w_hs;
  reg [1:0]   axi_wstate;
  reg [1:0]   axi_wnext;
  reg 	      ddr_adrs_table_wr;
  reg [AXILITE_ADDR_WIDTH-1 : 0] axi_waddr;
  reg [31:0] 			 ddr_adrs_table_datain;

  wire [9:0] map_addr;
  wire [31:0] map_out;
  reg [31:0]  stage3_map;
  wire 	      stage1_enable;
  reg 	      stage1_vld;
  wire 	      stage1_rdy;
  wire	      stage2_enable;
  reg 	      stage2_vld;
  wire 	      stage2_rdy;
  wire	      stage3_enable;
  reg 	      stage3_vld;
  wire 	      stage3_rdy;
  wire	      stage4_enable;
  reg 	      stage4_vld;
  wire 	      stage4_rdy;

  reg [31:0]  stage1_addr;
  reg [1:0]   stage1_burst;
  reg [3:0]   stage1_cache;
  reg [2:0]   stage1_id;
  reg [7:0]   stage1_len;
  reg [1:0]   stage1_lock;
  reg [2:0]   stage1_prot;
  reg [3:0]   stage1_qos;
  reg [3:0]   stage1_region;
  reg [2:0]   stage1_size;

  reg [31:0]  stage2_addr;
  reg [1:0]   stage2_burst;
  reg [3:0]   stage2_cache;
  reg [2:0]   stage2_id;
  reg [7:0]   stage2_len;
  reg [1:0]   stage2_lock;
  reg [2:0]   stage2_prot;
  reg [3:0]   stage2_qos;
  reg [3:0]   stage2_region;
  reg [2:0]   stage2_size;

  reg [31:0]  stage3_addr;
  reg [1:0]   stage3_burst;
  reg [3:0]   stage3_cache;
  reg [2:0]   stage3_id;
  reg [7:0]   stage3_len;
  reg [1:0]   stage3_lock;
  reg [2:0]   stage3_prot;
  reg [3:0]   stage3_qos;
  reg [3:0]   stage3_region;
  reg [2:0]   stage3_size;

  reg [31:0]  stage4_addr;
  reg [1:0]   stage4_burst;
  reg [3:0]   stage4_cache;
  reg [2:0]   stage4_id;
  reg [7:0]   stage4_len;
  reg [1:0]   stage4_lock;
  reg [2:0]   stage4_prot;
  reg [3:0]   stage4_qos;
  reg [3:0]   stage4_region;
  reg [2:0]   stage4_size;
  






















  reg [31:0] 			 ddr_adrs_map_ctrl;
  reg [31:0] 			 ddr_adrs_map_wrbase0;
  reg [31:0] 			 ddr_adrs_map_wrbase1;
  reg [31:0] 			 ddr_adrs_map_rdbase0;
  reg [31:0] 			 ddr_adrs_map_rdbase1;
  reg 				 ddr_adrs_map_wr_toggle;
  reg 				 ddr_adrs_map_rd_toggle;
  wire [31:0] 			 map_wraddr_test_mode;
  wire [31:0] 			 map_wraddr;
  wire [31:0] 			 map_rdaddr_test_mode;
  wire [31:0] 			 map_rdaddr;
  
  always @(posedge clk) begin
    if (reset) begin
      ddr_adrs_map_wr_toggle <= 1'b0;
      ddr_adrs_map_rd_toggle <= 1'b0;
    end
    else begin
      if (ik2map_rdy & ik2map_vld) begin
	ddr_adrs_map_rd_toggle <= rdwr_mode ? ddr_adrs_map_rd_toggle + 1 : ddr_adrs_map_rd_toggle;
	ddr_adrs_map_wr_toggle <= rdwr_mode ? ddr_adrs_map_wr_toggle : ddr_adrs_map_wr_toggle + 1;
      end
    end
  end
  


  assign map_wraddr_test_mode = ddr_adrs_map_wr_toggle ? ddr_adrs_map_wrbase1 : ddr_adrs_map_wrbase0;
  assign map_rdaddr_test_mode = ddr_adrs_map_rd_toggle ? ddr_adrs_map_rdbase1 : ddr_adrs_map_rdbase0;




  


  assign map_wraddr = ddr_adrs_map_ctrl[0] ? map_wraddr_test_mode : ik2map_addr[40:31];
  assign map_rdaddr = ddr_adrs_map_ctrl[16] ? map_rdaddr_test_mode : ik2map_addr[40:31];
  assign map_addr = ~rdwr_mode ? map_wraddr[9:0] : map_rdaddr[9:0];



  assign axi_AWREADY = (axi_wstate == WRIDLE);
  assign axi_WREADY  = (axi_wstate == WRDATA);
  assign axi_BRESP   = 2'b00;
  assign axi_BVALID  = (axi_wstate == WRRESP);
  assign axi_aw_hs   = axi_AWVALID & axi_AWREADY;
  assign axi_w_hs    = axi_WVALID & axi_WREADY;
  

  always @(posedge clk) begin
    if (reset)
      axi_wstate <= WRIDLE;
    else
      axi_wstate <= axi_wnext;
  end
  

  always @(*) begin
    case (axi_wstate)
      WRIDLE:
        if (axi_AWVALID)
          axi_wnext = WRDATA;
        else
          axi_wnext = WRIDLE;
      WRDATA:
        if (axi_WVALID)
          axi_wnext = WRRESP;
        else
          axi_wnext = WRDATA;
      WRRESP:
        if (axi_BREADY)
          axi_wnext = WRIDLE;
        else
          axi_wnext = WRRESP;
      default:
        axi_wnext = WRIDLE;
    endcase
  end
  

  always @(posedge clk) begin
    if (axi_aw_hs)
      axi_waddr <= axi_AWADDR[AXILITE_ADDR_WIDTH-1 : 0];
  end
  

  always @(posedge clk) begin
    if (reset) begin
      ddr_adrs_table_wr <= 1'b0;
      ddr_adrs_map_ctrl <= 32'h00000000;
      ddr_adrs_map_wrbase0 <= 32'h00000000;
      ddr_adrs_map_wrbase1 <= 32'h00000000;
      ddr_adrs_map_rdbase0 <= 32'h00000000;
      ddr_adrs_map_rdbase1 <= 32'h00000000;
    end
    else
      begin
	if (axi_w_hs && axi_waddr >= DDR_ADDR_MAP_START && axi_waddr < DDR_ADDR_MAP_END) begin
	  ddr_adrs_table_wr <= 1'b1;
	  ddr_adrs_table_datain <= axi_WDATA;
	end
	else
	  ddr_adrs_table_wr <= 1'b0;
	
	if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_CTRL)
	  ddr_adrs_map_ctrl <= axi_WDATA;
	if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_WRBASE0)
	  ddr_adrs_map_wrbase0 <= axi_WDATA;
	if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_WRBASE1)
	  ddr_adrs_map_wrbase1 <= axi_WDATA;
	if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_RDBASE0)
	  ddr_adrs_map_rdbase0 <= axi_WDATA;
	if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_RDBASE1)
	  ddr_adrs_map_rdbase1 <= axi_WDATA;
      end
  end
  


  assign ik2map_rdy = stage1_rdy;
  
  assign stage1_enable = ik2map_vld & ik2map_rdy;
  assign stage1_rdy = ~stage1_vld | stage2_rdy;

  assign stage2_enable = stage1_vld & stage2_rdy;
  assign stage2_rdy = ~stage2_vld | stage3_rdy;

  assign stage3_enable = stage2_vld & stage3_rdy;
  assign stage3_rdy = ~stage3_vld | stage4_rdy;

  assign stage4_enable = stage3_vld & stage4_rdy;
  assign stage4_rdy = ~stage4_vld | map2ddr_rdy;

  assign map2ddr_vld = stage4_vld;
  assign map2ddr_addr = stage4_addr;
  assign map2ddr_burst = stage4_burst;
  assign map2ddr_cache = stage4_cache;
  assign map2ddr_id = stage4_id;
  assign map2ddr_len = stage4_len;
  assign map2ddr_lock = stage4_lock;
  assign map2ddr_prot = stage4_prot;
  assign map2ddr_qos = stage4_qos;
  assign map2ddr_region = stage4_region;
  assign map2ddr_size = stage4_size;
  
  
always @(posedge clk) begin
  if (reset) begin
    stage1_vld <= 1'b0;
    stage2_vld <= 1'b0;
    stage3_vld <= 1'b0;
    stage4_vld <= 1'b0;
  end
  else begin
    if (stage1_enable) begin
      stage1_addr <= {1'b0, ik2map_addr[30:0]};
      stage1_burst <= ik2map_burst;
      stage1_cache <= ik2map_cache;
      stage1_id <= ik2map_id;
      stage1_len <= ik2map_len;
      stage1_lock <= ik2map_lock;
      stage1_prot <= ik2map_prot;
      stage1_qos <= ik2map_qos;
      stage1_region <= ik2map_region;
      stage1_size <= ik2map_size;
      stage1_vld <= 1'b1;
    end
    else if (stage1_vld & stage2_rdy) begin
      stage1_vld <= 1'b0;
    end

    if (stage2_enable) begin
      stage2_addr <= {1'b0, stage1_addr[30:0]};
      stage2_burst <= stage1_burst;
      stage2_cache <= stage1_cache;
      stage2_id <= stage1_id;
      stage2_len <= stage1_len;
      stage2_lock <= stage1_lock;
      stage2_prot <= stage1_prot;
      stage2_qos <= stage1_qos;
      stage2_region <= stage1_region;
      stage2_size <= stage1_size;
      stage2_vld <= 1'b1;
    end
    else if (stage2_vld & stage3_rdy) begin
      stage2_vld <= 1'b0;
    end

    if (stage3_enable) begin
      stage3_map <= map_out;
      stage3_addr <= {1'b0, stage2_addr[30:0]};
      stage3_burst <= stage2_burst;
      stage3_cache <= stage2_cache;
      stage3_id <= stage2_id;
      stage3_len <= stage2_len;
      stage3_lock <= stage2_lock;
      stage3_prot <= stage2_prot;
      stage3_qos <= stage2_qos;
      stage3_region <= stage2_region;
      stage3_size <= stage2_size;
      stage3_vld <= 1'b1;
    end
    else if (stage3_vld & stage4_rdy) begin
      stage3_vld <= 1'b0;
    end

    if (stage4_enable) begin

      stage4_addr <= {1'b0, stage3_addr[30:12] + stage3_map[18:0] , stage3_addr[11:0]};

      stage4_burst <= stage3_burst;
      stage4_cache <= stage3_cache;
      stage4_id <= stage3_id;
      stage4_len <= stage3_len;
      stage4_lock <= stage3_lock;
      stage4_prot <= stage3_prot;
      stage4_qos <= stage3_qos;
      stage4_region <= stage3_region;
      stage4_size <= stage3_size;
      stage4_vld <= 1'b1;
    end

    else if (stage4_vld & map2ddr_rdy) begin
      stage4_vld <= 1'b0;
    end

  end
end

  
ddr_adrs_mapping ddr_addr_table (
  .clka(clk),


  .addra({2'b0, axi_waddr[9:2]}),
  .wea(ddr_adrs_table_wr),
  .dina(ddr_adrs_table_datain),



  .clkb(clk),
  .addrb(map_addr),



  .doutb(map_out)
);
  
endmodule