data/full_repos/permissive/178052224/Tarea6/demux_valid/src/demux_valid.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/178052224/Tarea6/demux_valid/src/demux_valid.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #5 s <= ~s; \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module demux_valid(
                    input clk, reset_L, valid_in,
                    output reg [3:0] data_tran, data_out0, data_out1,
                    input [3:0] data_in,
                    output reg valid_out0, valid_out1                   );


    reg s;


    always@(posedge clk)
    begin
    #5 s <= ~s; 
        case (valid_in)
            0: begin
                data_tran <= data_tran;
            end

            1: begin
                data_tran <= data_in;
            end
        endcase
    end
   

    always@(*)
    begin
        data_out0 = 0;
        data_out1 = 0;
        data_tran = data_in;
        valid_out0 = 'b0;
        valid_out1 = 'b0;
        

        if (reset_L == 0) begin
            data_out0 = 0;
            data_out1 = 0;
            valid_out0 = 'b0;
            valid_out1 = 'b0;
            s = 0;
        end


        else begin
            if (s==0) begin
                data_out0 = data_tran;

                valid_out0 = valid_in;

                
            end     
            
            else begin

                data_out1 = data_tran;

                valid_out1 = valid_in;
            end
        end 
    end
    
endmodule
module demux_valid(
                    input clk, reset_L, valid_in,
                    output reg [3:0] data_tran, data_out0, data_out1,
                    input [3:0] data_in,
                    output reg valid_out0, valid_out1                   );



    reg s;


    always@(posedge clk)
    begin
    #5 s <= ~s; 
        case (valid_in)
            0: begin
                data_tran <= data_tran;
            end

            1: begin
                data_tran <= data_in;
            end
        endcase
    end
   

    always@(*)
    begin
        data_out0 = 0;
        data_out1 = 0;
        data_tran = data_in;
        valid_out0 = 'b0;
        valid_out1 = 'b0;
        

        if (reset_L == 0) begin
            data_out0 = 0;
            data_out1 = 0;
            valid_out0 = 'b0;
            valid_out1 = 'b0;
            s = 0;
        end


        else begin
            if (s==0) begin
                data_out0 = data_tran;

                valid_out0 = valid_in;

                
            end     
            
            else begin

                data_out1 = data_tran;

                valid_out1 = valid_in;
            end
        end 
    end
    
endmodule