data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/iic_master2.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/iic_master2.v:296: Signal definition not found, creating implicitly: \'clk_div\'\n                                                                                                                      : ... Suggested alternative: \'clk_i\'\n   temp_div[0] <= clk_div;\n                  ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/iic_master2.v:148: Cannot find file containing module: \'IIC_driver_ASM2\'\n IIC_driver_ASM2 IIC_BUS(.rst_i   (rst_i),      \n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog,data/full_repos/permissive/156971787/IIC_driver_ASM2\n             data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog,data/full_repos/permissive/156971787/IIC_driver_ASM2.v\n             data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog,data/full_repos/permissive/156971787/IIC_driver_ASM2.sv\n             IIC_driver_ASM2\n             IIC_driver_ASM2.v\n             IIC_driver_ASM2.sv\n             obj_dir/IIC_driver_ASM2\n             obj_dir/IIC_driver_ASM2.v\n             obj_dir/IIC_driver_ASM2.sv\n%Error: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/iic_master2.v:164: Cannot find file containing module: \'clk_div_IIC\'\n clk_div_IIC  CLK_DIV (.clk_i (clk_i),         \n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/iic_master2.v:169: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'vid_ACK_o\' generates 1 bits.\n                                                                                                                   : ... In instance iic_master2\n assign TEST1=vid_ACK_o;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/iic_master2.v:170: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'RegAdress\' generates 8 bits.\n                                                                                                                   : ... In instance iic_master2\n assign TEST3=RegAdress;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/iic_master2.v:253: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                                                                   : ... In instance iic_master2\n   index    <= 6\'h00;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/iic_master2.v:263: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'num_op\' generates 7 bits.\n                                                                                                                   : ... In instance iic_master2\n   for(i=0;i<(num_op+1);i=i+1) \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/iic_master2.v:276: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'num_op\' generates 7 bits.\n                                                                                                                   : ... In instance iic_master2\n    for(i=0;i<(num_op+1);i=i+1) \n                     ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n'
module iic_master2
	(
			input rst_i,
			input clk_i,

			input  SDA_io_I,
			output SDA_io_O,
			output SDA_io_T,
			output SCL_o,

			input CSR_DONE,
			input [18:0] i2c_reg0, 
			input [18:0] i2c_reg1,
			input [18:0] i2c_reg2,
			input [18:0] i2c_reg3, 
			input [18:0] i2c_reg4,
			input [18:0] i2c_reg5,
			input [18:0] i2c_reg6, 
			input [18:0] i2c_reg7,
			input [18:0] i2c_reg8,
			input [18:0] i2c_reg9, 
			input [18:0] i2c_reg10,
			input [18:0] i2c_reg11,
			input [18:0] i2c_reg12,
			input [18:0] i2c_reg13, 
			input [18:0] i2c_reg14,
			input [18:0] i2c_reg15,
			input [18:0] i2c_reg16, 
			input [18:0] i2c_reg17,
			input [18:0] i2c_reg18,
			input [18:0] i2c_reg19, 
			input [18:0] i2c_reg20,
			input [18:0] i2c_reg21,
			input [18:0] i2c_reg22, 
			input [18:0] i2c_reg23,
			input [18:0] i2c_reg24,
			input [18:0] i2c_reg25,
			input [18:0] i2c_reg26, 
			input [18:0] i2c_reg27,
			input [18:0] i2c_reg28,
			input [18:0] i2c_reg29, 
			input [18:0] i2c_reg30,
			input [18:0] i2c_reg31,
			input [18:0] i2c_reg32, 
			input [18:0] i2c_reg33,
			input [18:0] i2c_reg34,
			input [18:0] i2c_reg35, 
			input [18:0] i2c_reg36,
			input [18:0] i2c_reg37,
			input [18:0] i2c_reg38,
			input [18:0] i2c_reg39,
			input [18:0] i2c_reg40,
			input [18:0] i2c_reg41, 
			input [18:0] i2c_reg42,
			input [18:0] i2c_reg43,
			input [18:0] i2c_reg44, 
			input [18:0] i2c_reg45,
			input [18:0] i2c_reg46,
			input [18:0] i2c_reg47,
			input [18:0] i2c_reg48,
			input [18:0] i2c_reg49,
			input [18:0] i2c_reg50, 
			input [18:0] i2c_reg51,
			input [18:0] i2c_reg52,
			input [18:0] i2c_reg53,
			input [18:0] i2c_reg54, 
			input [18:0] i2c_reg55,
			input [18:0] i2c_reg56,
			input [18:0] i2c_reg57,
			input [18:0] i2c_reg58,
			input [18:0] i2c_reg59,

			output reg vid_ACK_o,
			output wire [31:0] data_o,
			output wire [31:0] ACK_o,
			output wire [31:0] TEST1,TEST2,TEST3
			);
			

	localparam
					DAB_DVI = 7'b1110110 ,
					DAB_VGA = 7'b1001100 ,

					Valid = 1'b1,
					NotValid = 1'b0,

					R = 1'b1,
					W = 1'b0,	
					CH = 1'b1,
					AD = 1'b0,
					USE = 1'b1;

	reg vld_o;
	reg Enable_I2C;
	reg [1:0] temp_rdy;
	reg [1:0] temp_div;
	reg [1:0] temp_csrdone;
	reg [6:0] index;
	reg [9:0] counter;
	reg [7:0] DeviceAdress;
	reg [7:0] RegAdress;
	reg [7:0] DataOUT;
	reg [31:0] i;
	

	localparam num_op=7'd119;
	reg [18:0] d_rw_reg_data [num_op:0];
	reg [18:0] temp [num_op-60:0];
	

	wire rdy_i;
	

	IIC_driver_ASM2 IIC_BUS(.rst_i   (rst_i),
									.clk_i   (clk_div),
									.DA_i    (DeviceAdress),
									.RA_i    (RegAdress),
									.data_i  (DataOUT),
									.data_o  (data_o),
									.SDA_io_I(SDA_io_I),
									.SDA_io_O(SDA_io_O),
									.SDA_io_T(SDA_io_T),
									.SCL_o 	(SCL_o),
									.vld_i 	(vld_o),
									.rdy_o 	(rdy_i),
									.ACK_o	(ACK_o),
									.TEST2	(TEST2)
									); 	 
									
	clk_div_IIC 	CLK_DIV (.clk_i (clk_i),
								   .rst_i (rst_i),
								   .clk_o (clk_div));
	

	assign TEST1=vid_ACK_o;
	assign TEST3=RegAdress;
	

	

	always @(i2c_reg0 or i2c_reg1 or i2c_reg2 or i2c_reg3 or i2c_reg4 or 
				i2c_reg5 or i2c_reg6 or i2c_reg7 or i2c_reg8 or i2c_reg9 or i2c_reg10 or i2c_reg11 or
				i2c_reg12 or i2c_reg13 or i2c_reg14 or i2c_reg15 or i2c_reg16 or i2c_reg17 or i2c_reg18 or i2c_reg19 or
				i2c_reg20 or i2c_reg21 or i2c_reg22 or i2c_reg23 or i2c_reg24 or i2c_reg25 or i2c_reg26 or i2c_reg27 or
				i2c_reg28 or i2c_reg29 or i2c_reg30 or i2c_reg31 or i2c_reg32 or i2c_reg33 or i2c_reg34 or i2c_reg35 or
				i2c_reg36 or i2c_reg37 or i2c_reg38 or i2c_reg39 or i2c_reg40 or i2c_reg41 or i2c_reg42 or i2c_reg43 or
				i2c_reg44 or i2c_reg45 or i2c_reg46 or i2c_reg47 or i2c_reg48 or i2c_reg49 or i2c_reg50 or i2c_reg51 or
				i2c_reg52 or i2c_reg53 or i2c_reg54 or i2c_reg55 or i2c_reg56 or i2c_reg57 or i2c_reg58 or i2c_reg59)
	begin
		temp[0]=i2c_reg0; 
		temp[1]=i2c_reg1;
		temp[2]=i2c_reg2;
		temp[3]=i2c_reg3;
		temp[4]=i2c_reg4;
		temp[5]=i2c_reg5;
		temp[6]=i2c_reg6;
		temp[7]=i2c_reg7;
		temp[8]=i2c_reg8;
		temp[9]=i2c_reg9;
		temp[10]=i2c_reg10;
		temp[11]=i2c_reg11;
		temp[12]=i2c_reg12;
		temp[13]=i2c_reg13;
		temp[14]=i2c_reg14;
		temp[15]=i2c_reg15;
		temp[16]=i2c_reg16;
		temp[17]=i2c_reg17;
		temp[18]=i2c_reg18;
		temp[19]=i2c_reg19;
		temp[20]=i2c_reg20;
		temp[21]=i2c_reg21;
		temp[22]=i2c_reg22;
		temp[23]=i2c_reg23;
		temp[24]=i2c_reg24;
		temp[25]=i2c_reg25;
		temp[26]=i2c_reg26;
		temp[27]=i2c_reg27;
		temp[28]=i2c_reg28;
		temp[29]=i2c_reg29;
		temp[30]=i2c_reg30;
		temp[31]=i2c_reg31;
		temp[32]=i2c_reg32;
		temp[33]=i2c_reg33;
		temp[34]=i2c_reg34;
		temp[35]=i2c_reg35;
		temp[36]=i2c_reg36;
		temp[37]=i2c_reg37;
		temp[38]=i2c_reg38;
		temp[39]=i2c_reg39;
		temp[40]=i2c_reg40;
		temp[41]=i2c_reg41;
		temp[42]=i2c_reg42;
		temp[43]=i2c_reg43;
		temp[44]=i2c_reg44;
		temp[45]=i2c_reg45;
		temp[46]=i2c_reg46;
		temp[47]=i2c_reg47;
		temp[48]=i2c_reg48;
		temp[49]=i2c_reg49;
		temp[50]=i2c_reg50;
		temp[51]=i2c_reg51;
		temp[52]=i2c_reg52;
		temp[53]=i2c_reg53;
		temp[54]=i2c_reg54;
		temp[55]=i2c_reg55;
		temp[56]=i2c_reg56;
		temp[57]=i2c_reg57;
		temp[58]=i2c_reg58;
		temp[59]=i2c_reg59;
	end	


	always @(posedge clk_i or posedge rst_i)
	begin
		if(rst_i)
		begin
			Enable_I2C	 <= 1'b0;
			vid_ACK_o	 <= 1'b0;
			index			 <= 6'h00;
			counter		 <= 10'h000;
			vld_o			 <= Valid;
			temp_rdy		 <= 2'b11;
			temp_div		 <= 2'b00;
			temp_csrdone <= 2'b00;
			DeviceAdress <= 8'h00;
			RegAdress	 <= 8'h00;
			DataOUT		 <= 8'h00;

			for(i=0;i<(num_op+1);i=i+1) 
			begin
				d_rw_reg_data[i]<=0;
			end
		end	
		else
		begin

			temp_csrdone[0]<=CSR_DONE;
			temp_csrdone[1]<=temp_csrdone[0];
			
			if(temp_csrdone==2'b01 && Enable_I2C==1'b0)
			begin
				for(i=0;i<(num_op+1);i=i+1) 
				begin
					if(i<=59)
						d_rw_reg_data[i]<=temp[i];

					else
					begin
						d_rw_reg_data[i]<={temp[i-60][18:17],1'b1,temp[i-60][15:0]}; 

					end
				end

				index<=0;
				Enable_I2C<=1'b1;
			end

			temp_rdy[0] <= rdy_i;
			temp_rdy[1] <= temp_rdy[0];
			

			temp_div[0] <= clk_div;
			temp_div[1] <= temp_div[0];
			

			if(Enable_I2C)
			begin
				if(temp_div==2'b01)
				begin
					if(counter>10'd4)
					begin
						if( temp_rdy == 2'b11 && vld_o==Valid && index <(num_op+1) && temp_div==2'b01 ) 
						begin
							if(d_rw_reg_data[index][18]==USE)
							begin
								vld_o <= NotValid;
								index <= index + 1'b1;
								RegAdress<= d_rw_reg_data[index][15:8];
								
								if(d_rw_reg_data[index][17]==CH) DeviceAdress[7:1]<=DAB_DVI;
								else DeviceAdress[7:1]<=DAB_VGA;
								
								if( d_rw_reg_data[index][16]==R)
								begin
									DeviceAdress[0]<=R;
									DataOUT <= 8'h00;
								end				
								else
								begin	
									DeviceAdress[0] <= W;
									DataOUT <= d_rw_reg_data[index][7:0];
								end
							end
							else
							begin
								index <= index + 1'b1;
							end
						end
						else
						begin
							if( temp_rdy == 2'b01 )
							begin
								vld_o <= Valid;
								DeviceAdress <= 8'h00;
								RegAdress <= 8'h00;
								DataOUT <= 8'h00;	
								counter<=10'h000;
							end
							if(index==(num_op+1))
							begin
								if(counter>10'd100 ) vid_ACK_o<=1'b1;
								else counter<=counter+1'b1;
							end
						end
					end
					else counter<=counter+1'b1;
				end
			end		
		end
	end
endmodule
module iic_master2
	(
			input rst_i,
			input clk_i,

			input  SDA_io_I,
			output SDA_io_O,
			output SDA_io_T,
			output SCL_o,

			input CSR_DONE,
			input [18:0] i2c_reg0, 
			input [18:0] i2c_reg1,
			input [18:0] i2c_reg2,
			input [18:0] i2c_reg3, 
			input [18:0] i2c_reg4,
			input [18:0] i2c_reg5,
			input [18:0] i2c_reg6, 
			input [18:0] i2c_reg7,
			input [18:0] i2c_reg8,
			input [18:0] i2c_reg9, 
			input [18:0] i2c_reg10,
			input [18:0] i2c_reg11,
			input [18:0] i2c_reg12,
			input [18:0] i2c_reg13, 
			input [18:0] i2c_reg14,
			input [18:0] i2c_reg15,
			input [18:0] i2c_reg16, 
			input [18:0] i2c_reg17,
			input [18:0] i2c_reg18,
			input [18:0] i2c_reg19, 
			input [18:0] i2c_reg20,
			input [18:0] i2c_reg21,
			input [18:0] i2c_reg22, 
			input [18:0] i2c_reg23,
			input [18:0] i2c_reg24,
			input [18:0] i2c_reg25,
			input [18:0] i2c_reg26, 
			input [18:0] i2c_reg27,
			input [18:0] i2c_reg28,
			input [18:0] i2c_reg29, 
			input [18:0] i2c_reg30,
			input [18:0] i2c_reg31,
			input [18:0] i2c_reg32, 
			input [18:0] i2c_reg33,
			input [18:0] i2c_reg34,
			input [18:0] i2c_reg35, 
			input [18:0] i2c_reg36,
			input [18:0] i2c_reg37,
			input [18:0] i2c_reg38,
			input [18:0] i2c_reg39,
			input [18:0] i2c_reg40,
			input [18:0] i2c_reg41, 
			input [18:0] i2c_reg42,
			input [18:0] i2c_reg43,
			input [18:0] i2c_reg44, 
			input [18:0] i2c_reg45,
			input [18:0] i2c_reg46,
			input [18:0] i2c_reg47,
			input [18:0] i2c_reg48,
			input [18:0] i2c_reg49,
			input [18:0] i2c_reg50, 
			input [18:0] i2c_reg51,
			input [18:0] i2c_reg52,
			input [18:0] i2c_reg53,
			input [18:0] i2c_reg54, 
			input [18:0] i2c_reg55,
			input [18:0] i2c_reg56,
			input [18:0] i2c_reg57,
			input [18:0] i2c_reg58,
			input [18:0] i2c_reg59,

			output reg vid_ACK_o,
			output wire [31:0] data_o,
			output wire [31:0] ACK_o,
			output wire [31:0] TEST1,TEST2,TEST3
			);

			

	localparam
					DAB_DVI = 7'b1110110 ,
					DAB_VGA = 7'b1001100 ,

					Valid = 1'b1,
					NotValid = 1'b0,

					R = 1'b1,
					W = 1'b0,	
					CH = 1'b1,
					AD = 1'b0,
					USE = 1'b1;

	reg vld_o;
	reg Enable_I2C;
	reg [1:0] temp_rdy;
	reg [1:0] temp_div;
	reg [1:0] temp_csrdone;
	reg [6:0] index;
	reg [9:0] counter;
	reg [7:0] DeviceAdress;
	reg [7:0] RegAdress;
	reg [7:0] DataOUT;
	reg [31:0] i;
	

	localparam num_op=7'd119;
	reg [18:0] d_rw_reg_data [num_op:0];
	reg [18:0] temp [num_op-60:0];
	

	wire rdy_i;
	

	IIC_driver_ASM2 IIC_BUS(.rst_i   (rst_i),
									.clk_i   (clk_div),
									.DA_i    (DeviceAdress),
									.RA_i    (RegAdress),
									.data_i  (DataOUT),
									.data_o  (data_o),
									.SDA_io_I(SDA_io_I),
									.SDA_io_O(SDA_io_O),
									.SDA_io_T(SDA_io_T),
									.SCL_o 	(SCL_o),
									.vld_i 	(vld_o),
									.rdy_o 	(rdy_i),
									.ACK_o	(ACK_o),
									.TEST2	(TEST2)
									); 	 
									
	clk_div_IIC 	CLK_DIV (.clk_i (clk_i),
								   .rst_i (rst_i),
								   .clk_o (clk_div));
	

	assign TEST1=vid_ACK_o;
	assign TEST3=RegAdress;
	

	

	always @(i2c_reg0 or i2c_reg1 or i2c_reg2 or i2c_reg3 or i2c_reg4 or 
				i2c_reg5 or i2c_reg6 or i2c_reg7 or i2c_reg8 or i2c_reg9 or i2c_reg10 or i2c_reg11 or
				i2c_reg12 or i2c_reg13 or i2c_reg14 or i2c_reg15 or i2c_reg16 or i2c_reg17 or i2c_reg18 or i2c_reg19 or
				i2c_reg20 or i2c_reg21 or i2c_reg22 or i2c_reg23 or i2c_reg24 or i2c_reg25 or i2c_reg26 or i2c_reg27 or
				i2c_reg28 or i2c_reg29 or i2c_reg30 or i2c_reg31 or i2c_reg32 or i2c_reg33 or i2c_reg34 or i2c_reg35 or
				i2c_reg36 or i2c_reg37 or i2c_reg38 or i2c_reg39 or i2c_reg40 or i2c_reg41 or i2c_reg42 or i2c_reg43 or
				i2c_reg44 or i2c_reg45 or i2c_reg46 or i2c_reg47 or i2c_reg48 or i2c_reg49 or i2c_reg50 or i2c_reg51 or
				i2c_reg52 or i2c_reg53 or i2c_reg54 or i2c_reg55 or i2c_reg56 or i2c_reg57 or i2c_reg58 or i2c_reg59)
	begin
		temp[0]=i2c_reg0; 
		temp[1]=i2c_reg1;
		temp[2]=i2c_reg2;
		temp[3]=i2c_reg3;
		temp[4]=i2c_reg4;
		temp[5]=i2c_reg5;
		temp[6]=i2c_reg6;
		temp[7]=i2c_reg7;
		temp[8]=i2c_reg8;
		temp[9]=i2c_reg9;
		temp[10]=i2c_reg10;
		temp[11]=i2c_reg11;
		temp[12]=i2c_reg12;
		temp[13]=i2c_reg13;
		temp[14]=i2c_reg14;
		temp[15]=i2c_reg15;
		temp[16]=i2c_reg16;
		temp[17]=i2c_reg17;
		temp[18]=i2c_reg18;
		temp[19]=i2c_reg19;
		temp[20]=i2c_reg20;
		temp[21]=i2c_reg21;
		temp[22]=i2c_reg22;
		temp[23]=i2c_reg23;
		temp[24]=i2c_reg24;
		temp[25]=i2c_reg25;
		temp[26]=i2c_reg26;
		temp[27]=i2c_reg27;
		temp[28]=i2c_reg28;
		temp[29]=i2c_reg29;
		temp[30]=i2c_reg30;
		temp[31]=i2c_reg31;
		temp[32]=i2c_reg32;
		temp[33]=i2c_reg33;
		temp[34]=i2c_reg34;
		temp[35]=i2c_reg35;
		temp[36]=i2c_reg36;
		temp[37]=i2c_reg37;
		temp[38]=i2c_reg38;
		temp[39]=i2c_reg39;
		temp[40]=i2c_reg40;
		temp[41]=i2c_reg41;
		temp[42]=i2c_reg42;
		temp[43]=i2c_reg43;
		temp[44]=i2c_reg44;
		temp[45]=i2c_reg45;
		temp[46]=i2c_reg46;
		temp[47]=i2c_reg47;
		temp[48]=i2c_reg48;
		temp[49]=i2c_reg49;
		temp[50]=i2c_reg50;
		temp[51]=i2c_reg51;
		temp[52]=i2c_reg52;
		temp[53]=i2c_reg53;
		temp[54]=i2c_reg54;
		temp[55]=i2c_reg55;
		temp[56]=i2c_reg56;
		temp[57]=i2c_reg57;
		temp[58]=i2c_reg58;
		temp[59]=i2c_reg59;
	end	


	always @(posedge clk_i or posedge rst_i)
	begin
		if(rst_i)
		begin
			Enable_I2C	 <= 1'b0;
			vid_ACK_o	 <= 1'b0;
			index			 <= 6'h00;
			counter		 <= 10'h000;
			vld_o			 <= Valid;
			temp_rdy		 <= 2'b11;
			temp_div		 <= 2'b00;
			temp_csrdone <= 2'b00;
			DeviceAdress <= 8'h00;
			RegAdress	 <= 8'h00;
			DataOUT		 <= 8'h00;

			for(i=0;i<(num_op+1);i=i+1) 
			begin
				d_rw_reg_data[i]<=0;
			end
		end	
		else
		begin

			temp_csrdone[0]<=CSR_DONE;
			temp_csrdone[1]<=temp_csrdone[0];
			
			if(temp_csrdone==2'b01 && Enable_I2C==1'b0)
			begin
				for(i=0;i<(num_op+1);i=i+1) 
				begin
					if(i<=59)
						d_rw_reg_data[i]<=temp[i];

					else
					begin
						d_rw_reg_data[i]<={temp[i-60][18:17],1'b1,temp[i-60][15:0]}; 

					end
				end

				index<=0;
				Enable_I2C<=1'b1;
			end

			temp_rdy[0] <= rdy_i;
			temp_rdy[1] <= temp_rdy[0];
			

			temp_div[0] <= clk_div;
			temp_div[1] <= temp_div[0];
			

			if(Enable_I2C)
			begin
				if(temp_div==2'b01)
				begin
					if(counter>10'd4)
					begin
						if( temp_rdy == 2'b11 && vld_o==Valid && index <(num_op+1) && temp_div==2'b01 ) 
						begin
							if(d_rw_reg_data[index][18]==USE)
							begin
								vld_o <= NotValid;
								index <= index + 1'b1;
								RegAdress<= d_rw_reg_data[index][15:8];
								
								if(d_rw_reg_data[index][17]==CH) DeviceAdress[7:1]<=DAB_DVI;
								else DeviceAdress[7:1]<=DAB_VGA;
								
								if( d_rw_reg_data[index][16]==R)
								begin
									DeviceAdress[0]<=R;
									DataOUT <= 8'h00;
								end				
								else
								begin	
									DeviceAdress[0] <= W;
									DataOUT <= d_rw_reg_data[index][7:0];
								end
							end
							else
							begin
								index <= index + 1'b1;
							end
						end
						else
						begin
							if( temp_rdy == 2'b01 )
							begin
								vld_o <= Valid;
								DeviceAdress <= 8'h00;
								RegAdress <= 8'h00;
								DataOUT <= 8'h00;	
								counter<=10'h000;
							end
							if(index==(num_op+1))
							begin
								if(counter>10'd100 ) vid_ACK_o<=1'b1;
								else counter<=counter+1'b1;
							end
						end
					end
					else counter<=counter+1'b1;
				end
			end		
		end
	end
endmodule