data/full_repos/permissive/139299103/MultiCycleCPU.srcs/sources_1/new/ALU.v
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data/verilator_xmls/6846b20b-dea6-4568-8112-c2eeae63d055.xml
module ALU(
  DataA, DataB,  ALUOp,  ALUResult, zero,  sign
);
      input wire [31:0] DataA; 
      input wire [31:0] DataB; 
      input  [2:0] ALUOp; 
      output reg [31:0] ALUResult; 
      output  zero; 
      output  sign;
      
      initial begin
         ALUResult = 0;
      end
      assign sign = ( ALUResult[31] == 0)?0:1;
      assign zero = ( ALUResult == 0 )?1:0;
      
      always @( ALUOp or DataA or DataB ) begin
          case (ALUOp)
              3'b000 : ALUResult = DataA + DataB;  
              3'b001 : ALUResult = DataA - DataB; 
              3'b010 : ALUResult = (DataA < DataB) ? 1 : 0;
              3'b011 : ALUResult = (((DataA<DataB) && (DataA[31] == DataB[31] )) ||( ( DataA[31] ==1 && DataB[31] == 0))) ? 1:0;
              3'b100 : ALUResult = DataB << DataA;
              3'b101 : ALUResult = DataA | DataB;  
              3'b110 : ALUResult = DataA & DataB;
              3'b111: if(DataA[31] == DataB[31]) ALUResult = 0;
                      else ALUResult = 1;
              default : begin
                  ALUResult = 0;
              end
          endcase
      end
endmodule
module ALU(
  DataA, DataB,  ALUOp,  ALUResult, zero,  sign
);

      input wire [31:0] DataA; 
      input wire [31:0] DataB; 
      input  [2:0] ALUOp; 
      output reg [31:0] ALUResult; 
      output  zero; 
      output  sign;
      
      initial begin
         ALUResult = 0;
      end
      assign sign = ( ALUResult[31] == 0)?0:1;
      assign zero = ( ALUResult == 0 )?1:0;
      
      always @( ALUOp or DataA or DataB ) begin
          case (ALUOp)
              3'b000 : ALUResult = DataA + DataB;  
              3'b001 : ALUResult = DataA - DataB; 
              3'b010 : ALUResult = (DataA < DataB) ? 1 : 0;
              3'b011 : ALUResult = (((DataA<DataB) && (DataA[31] == DataB[31] )) ||( ( DataA[31] ==1 && DataB[31] == 0))) ? 1:0;
              3'b100 : ALUResult = DataB << DataA;
              3'b101 : ALUResult = DataA | DataB;  
              3'b110 : ALUResult = DataA & DataB;
              3'b111: if(DataA[31] == DataB[31]) ALUResult = 0;
                      else ALUResult = 1;
              default : begin
                  ALUResult = 0;
              end
          endcase
      end
endmodule