data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v
1: b'%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:127: Selection index out of range: 4:4 outside 3:1\n                                                                                  : ... In instance vga_fifo\n        5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);\n                                 ^\n                   ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:128: Selection index out of range: 5:5 outside 3:1\n                                                                                  : ... In instance vga_fifo\n        6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);\n                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:128: Selection index out of range: 4:4 outside 3:1\n                                                                                  : ... In instance vga_fifo\n        6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);\n                                        ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:129: Selection index out of range: 6:6 outside 3:1\n                                                                                  : ... In instance vga_fifo\n        7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);\n                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:129: Selection index out of range: 5:5 outside 3:1\n                                                                                  : ... In instance vga_fifo\n        7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);\n                                        ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:130: Selection index out of range: 7:7 outside 3:1\n                                                                                  : ... In instance vga_fifo\n        8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);\n                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:130: Selection index out of range: 5:5 outside 3:1\n                                                                                  : ... In instance vga_fifo\n        8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);\n                                        ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:130: Selection index out of range: 4:4 outside 3:1\n                                                                                  : ... In instance vga_fifo\n        8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);\n                                               ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:131: Selection index out of range: 8:8 outside 3:1\n                                                                                  : ... In instance vga_fifo\n        9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);\n                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:131: Selection index out of range: 4:4 outside 3:1\n                                                                                  : ... In instance vga_fifo\n        9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);\n                                        ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:132: Selection index out of range: 9:9 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);\n                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:132: Selection index out of range: 6:6 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:133: Selection index out of range: 10:10 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);\n                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:133: Selection index out of range: 8:8 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:134: Selection index out of range: 11:11 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);\n                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:134: Selection index out of range: 5:5 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:135: Selection index out of range: 12:12 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);\n                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:136: Selection index out of range: 13:13 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);\n                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:136: Selection index out of range: 4:4 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:137: Selection index out of range: 14:14 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);\n                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:137: Selection index out of range: 13:13 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:138: Selection index out of range: 15:15 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);\n                                 ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:138: Selection index out of range: 14:14 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);\n                                         ^\n%Warning-SELRANGE: data/full_repos/permissive/131712122/rtl/verilog/vga_fifo.v:138: Selection index out of range: 12:12 outside 3:1\n                                                                                  : ... In instance vga_fifo\n       16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);\n                                                 ^\n%Error: Exiting due to 24 warning(s)\n'
module vga_fifo (
	clk,
	aclr,
	sclr,
	wreq,
	rreq,
	d,
	q,
	nword,
	empty,
	full,
	aempty,
	afull
	);




	parameter aw =  3;
	parameter dw =  8;




	input             clk;
	input             aclr;
	input             sclr;

	input             wreq;
	input             rreq;
	input  [dw:1]     d;
	output [dw:1]     q;

	output [aw:0]     nword;

	output            empty;
	output            full;

	output            aempty;
	output            afull;

	reg [aw:0] nword;
	reg        empty, full;




	reg  [aw:1] rp, wp;
	wire [dw:1] ramq;
	wire fwreq, frreq;

`ifdef VGA_FIFO_ALL_ENTRIES
	function lsb;
	   input [aw:1] q;
	   case (aw)
	       2: lsb = ~q[2];
	       3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]);
	       4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]);
	       5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);
	       6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);
	       7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);
	       8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
	       9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);
	      10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);
	      11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);
	      12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
	      13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
	      14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
	      15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);
	      16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
	   endcase
	endfunction
`else
	function lsb;
	   input [aw:1] q;
	   case (aw)
	       2: lsb = ~q[2];
	       3: lsb = ~(q[3] ^ q[2]);
	       4: lsb = ~(q[4] ^ q[3]);
	       5: lsb = ~(q[5] ^ q[3]);
	       6: lsb = ~(q[6] ^ q[5]);
	       7: lsb = ~(q[7] ^ q[6]);
	       8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
	       9: lsb = ~(q[9] ^ q[5]);
	      10: lsb = ~(q[10] ^ q[7]);
	      11: lsb = ~(q[11] ^ q[9]);
	      12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
	      13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
	      14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
	      15: lsb = ~(q[15] ^ q[14]);
	      16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
	   endcase
	endfunction
`endif

`ifdef RW_CHECK
  assign fwreq = wreq & ~full;
  assign frreq = rreq & ~empty;
`else
  assign fwreq = wreq;
  assign frreq = rreq;
`endif




	always @(posedge clk or negedge aclr)
	  if (~aclr)      rp <= #1 0;
	  else if (sclr)  rp <= #1 0;
	  else if (frreq) rp <= #1 {rp[aw-1:1], lsb(rp)};




	always @(posedge clk or negedge aclr)
	  if (~aclr)      wp <= #1 0;
	  else if (sclr)  wp <= #1 0;
	  else if (fwreq) wp <= #1 {wp[aw-1:1], lsb(wp)};





	reg [dw:1] mem [(1<<aw) -1:0];


	always @(posedge clk)
	  if (fwreq)
	    mem[wp] <= #1 d;

	assign q = mem[rp];



	assign aempty = (rp[aw-1:1] == wp[aw:2]) & (lsb(rp) == wp[1]) & frreq & ~fwreq;
	always @(posedge clk or negedge aclr)
	  if (~aclr)
	    empty <= #1 1'b1;
	  else if (sclr)
	    empty <= #1 1'b1;
	  else
	    empty <= #1 aempty | (empty & (~fwreq + frreq));

	assign afull = (wp[aw-1:1] == rp[aw:2]) & (lsb(wp) == rp[1]) & fwreq & ~frreq;
	always @(posedge clk or negedge aclr)
	  if (~aclr)
	    full <= #1 1'b0;
	  else if (sclr)
	    full <= #1 1'b0;
	  else
	    full <= #1 afull | ( full & (~frreq + fwreq) );


	always @(posedge clk or negedge aclr)
	  if (~aclr)
	    nword <= #1 0;
	  else if (sclr)
	    nword <= #1 0;
	  else
	    begin
	        if (wreq & !rreq)
	          nword <= #1 nword +1;
	        else if (rreq & !wreq)
	          nword <= #1 nword -1;
	    end





	always @(posedge clk)
	  if (full & fwreq)
	    $display("Writing while FIFO full (%m)\n");

	always @(posedge clk)
	  if (empty & frreq)
	    $display("Reading while FIFO empty (%m)\n");

endmodule
module vga_fifo (
	clk,
	aclr,
	sclr,
	wreq,
	rreq,
	d,
	q,
	nword,
	empty,
	full,
	aempty,
	afull
	);





	parameter aw =  3;
	parameter dw =  8;




	input             clk;
	input             aclr;
	input             sclr;

	input             wreq;
	input             rreq;
	input  [dw:1]     d;
	output [dw:1]     q;

	output [aw:0]     nword;

	output            empty;
	output            full;

	output            aempty;
	output            afull;

	reg [aw:0] nword;
	reg        empty, full;




	reg  [aw:1] rp, wp;
	wire [dw:1] ramq;
	wire fwreq, frreq;

`ifdef VGA_FIFO_ALL_ENTRIES
	function lsb;
	   input [aw:1] q;
	   case (aw)
	       2: lsb = ~q[2];
	       3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]);
	       4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]);
	       5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);
	       6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);
	       7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);
	       8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
	       9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);
	      10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);
	      11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);
	      12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
	      13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
	      14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
	      15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);
	      16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
	   endcase
	endfunction
`else
	function lsb;
	   input [aw:1] q;
	   case (aw)
	       2: lsb = ~q[2];
	       3: lsb = ~(q[3] ^ q[2]);
	       4: lsb = ~(q[4] ^ q[3]);
	       5: lsb = ~(q[5] ^ q[3]);
	       6: lsb = ~(q[6] ^ q[5]);
	       7: lsb = ~(q[7] ^ q[6]);
	       8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
	       9: lsb = ~(q[9] ^ q[5]);
	      10: lsb = ~(q[10] ^ q[7]);
	      11: lsb = ~(q[11] ^ q[9]);
	      12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
	      13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
	      14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
	      15: lsb = ~(q[15] ^ q[14]);
	      16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
	   endcase
	endfunction
`endif

`ifdef RW_CHECK
  assign fwreq = wreq & ~full;
  assign frreq = rreq & ~empty;
`else
  assign fwreq = wreq;
  assign frreq = rreq;
`endif




	always @(posedge clk or negedge aclr)
	  if (~aclr)      rp <= #1 0;
	  else if (sclr)  rp <= #1 0;
	  else if (frreq) rp <= #1 {rp[aw-1:1], lsb(rp)};




	always @(posedge clk or negedge aclr)
	  if (~aclr)      wp <= #1 0;
	  else if (sclr)  wp <= #1 0;
	  else if (fwreq) wp <= #1 {wp[aw-1:1], lsb(wp)};





	reg [dw:1] mem [(1<<aw) -1:0];


	always @(posedge clk)
	  if (fwreq)
	    mem[wp] <= #1 d;

	assign q = mem[rp];



	assign aempty = (rp[aw-1:1] == wp[aw:2]) & (lsb(rp) == wp[1]) & frreq & ~fwreq;
	always @(posedge clk or negedge aclr)
	  if (~aclr)
	    empty <= #1 1'b1;
	  else if (sclr)
	    empty <= #1 1'b1;
	  else
	    empty <= #1 aempty | (empty & (~fwreq + frreq));

	assign afull = (wp[aw-1:1] == rp[aw:2]) & (lsb(wp) == rp[1]) & fwreq & ~frreq;
	always @(posedge clk or negedge aclr)
	  if (~aclr)
	    full <= #1 1'b0;
	  else if (sclr)
	    full <= #1 1'b0;
	  else
	    full <= #1 afull | ( full & (~frreq + fwreq) );


	always @(posedge clk or negedge aclr)
	  if (~aclr)
	    nword <= #1 0;
	  else if (sclr)
	    nword <= #1 0;
	  else
	    begin
	        if (wreq & !rreq)
	          nword <= #1 nword +1;
	        else if (rreq & !wreq)
	          nword <= #1 nword -1;
	    end





	always @(posedge clk)
	  if (full & fwreq)
	    $display("Writing while FIFO full (%m)\n");

	always @(posedge clk)
	  if (empty & frreq)
	    $display("Reading while FIFO empty (%m)\n");

endmodule