data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_top_bip1.v
 line:51: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_top_bip1.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #2 i_rst = 1\'b1;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_top_bip1.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #40 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_top_bip1.v:54: Unsupported: Ignoring delay on this delayed statement.\n    always #1 i_clk = ~i_clk;\n           ^\n%Error: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_top_bip1.v:57: Cannot find file containing module: \'top_bip1\'\n    top_bip1 #(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/top_bip1\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/top_bip1.v\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/top_bip1.sv\n             top_bip1\n             top_bip1.v\n             top_bip1.sv\n             obj_dir/top_bip1\n             obj_dir/top_bip1.v\n             obj_dir/top_bip1.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top_bip1();

    parameter NB_INSTRUC      = 16;
    parameter NB_OPCODE       = 5;
    parameter NB_OPERAND      = 11;
    parameter NB_ADDR         = 11;
    parameter NB_DATA         = 16;

    parameter RAM_WIDTH_PROGRAM       = 16;
    parameter RAM_DEPTH_PROGRAM       = 2048;
    parameter RAM_PERFORMANCE_PROGRAM = "LOW_LATENCY";
    parameter INIT_FILE_PROGRAM       = "/home/martin/git/Arquitectura_de_Computadoras_2019/TP3-BIP1-2019/Test/init_ram_program.mem";

    parameter RAM_WIDTH_DATA          = 16;
    parameter RAM_DEPTH_DATA          = 1024; 
    parameter RAM_PERFORMANCE_DATA    = "LOW_LATENCY";
    parameter INIT_FILE_DATA          = "/home/martin/git/Arquitectura_de_Computadoras_2019/TP3-BIP1-2019/Test/init_ram_data.mem";


    reg i_clk;
    reg i_rst;

    initial begin
        i_clk = 1'b0;
        i_rst = 1'b0;

        #2 i_rst = 1'b1;
        
        #40 $finish;
    end

    always #1 i_clk = ~i_clk;


    top_bip1 #(

        .NB_INSTRUC (NB_INSTRUC),
        .NB_OPCODE  (NB_OPCODE),
        .NB_OPERAND (NB_OPERAND),
        .NB_ADDR    (NB_ADDR),
        .NB_DATA    (NB_DATA),

        .RAM_WIDTH_PROGRAM          (RAM_WIDTH_PROGRAM),
        .RAM_DEPTH_PROGRAM          (RAM_DEPTH_PROGRAM),
        .RAM_PERFORMANCE_PROGRAM    (RAM_PERFORMANCE_PROGRAM),
        .INIT_FILE_PROGRAM          (INIT_FILE_PROGRAM),

        .RAM_WIDTH_DATA             (RAM_WIDTH_DATA),
        .RAM_DEPTH_DATA             (RAM_DEPTH_DATA),
        .RAM_PERFORMANCE_DATA       (RAM_PERFORMANCE_DATA),
        .INIT_FILE_DATA             (INIT_FILE_DATA)
    )
    tb_top_bip1
    (
        .i_clk     (i_clk),
        .i_rst     (i_rst)
    );

endmodule
module tb_top_bip1();


    parameter NB_INSTRUC      = 16;
    parameter NB_OPCODE       = 5;
    parameter NB_OPERAND      = 11;
    parameter NB_ADDR         = 11;
    parameter NB_DATA         = 16;

    parameter RAM_WIDTH_PROGRAM       = 16;
    parameter RAM_DEPTH_PROGRAM       = 2048;
    parameter RAM_PERFORMANCE_PROGRAM = "LOW_LATENCY";
    parameter INIT_FILE_PROGRAM       = "/home/martin/git/Arquitectura_de_Computadoras_2019/TP3-BIP1-2019/Test/init_ram_program.mem";

    parameter RAM_WIDTH_DATA          = 16;
    parameter RAM_DEPTH_DATA          = 1024; 
    parameter RAM_PERFORMANCE_DATA    = "LOW_LATENCY";
    parameter INIT_FILE_DATA          = "/home/martin/git/Arquitectura_de_Computadoras_2019/TP3-BIP1-2019/Test/init_ram_data.mem";


    reg i_clk;
    reg i_rst;

    initial begin
        i_clk = 1'b0;
        i_rst = 1'b0;

        #2 i_rst = 1'b1;
        
        #40 $finish;
    end

    always #1 i_clk = ~i_clk;


    top_bip1 #(

        .NB_INSTRUC (NB_INSTRUC),
        .NB_OPCODE  (NB_OPCODE),
        .NB_OPERAND (NB_OPERAND),
        .NB_ADDR    (NB_ADDR),
        .NB_DATA    (NB_DATA),

        .RAM_WIDTH_PROGRAM          (RAM_WIDTH_PROGRAM),
        .RAM_DEPTH_PROGRAM          (RAM_DEPTH_PROGRAM),
        .RAM_PERFORMANCE_PROGRAM    (RAM_PERFORMANCE_PROGRAM),
        .INIT_FILE_PROGRAM          (INIT_FILE_PROGRAM),

        .RAM_WIDTH_DATA             (RAM_WIDTH_DATA),
        .RAM_DEPTH_DATA             (RAM_DEPTH_DATA),
        .RAM_PERFORMANCE_DATA       (RAM_PERFORMANCE_DATA),
        .INIT_FILE_DATA             (INIT_FILE_DATA)
    )
    tb_top_bip1
    (
        .i_clk     (i_clk),
        .i_rst     (i_rst)
    );

endmodule