data/full_repos/permissive/194847941/demo/12_game/sources/rtl/mcu/debug.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/78846c21-ee5e-48f1-9433-b127e6306bde.xml
module debug
(
    input   wire		clk,
    

    output  reg			rom_wen,
    output  reg [23:0]	rom_waddr,
    output  reg [7:0]	rom_wdata,
    

    output  reg			rom_ren,
    output  reg  [23:0]	rom_raddr,
    input   wire [7:0]	rom_rdata,
    

    output  reg			dbg_en,
    output  reg			dbg_inst_en,
    output  reg  [7:0]	dbg_inst,
    

    output  reg  [3:0]	read_abcd,
    input   wire		dbg_info_en,
    input   wire [15:0]	dbg_info,
    

	input	wire		recv_en,
	input	wire [7:0]	recv_cmd,
	input	wire [7:0]	recv_data,
    output  reg			send_en,
    output  reg  [7:0]	send_cmd,
    output  reg  [7:0]	send_data,
    input   wire		send_ready
);

reg free_run_cmd;
reg debug_cmd;
reg clear_rom_addr_cmd;
reg clear_rom_data_cmd;
reg read_rom_cmd;
reg write_rom_cmd;
reg read_a_cmd;
reg read_b_cmd;
reg read_c_cmd;
reg read_d_cmd;
reg rom_ren_d0;
reg rom_ren_d1;
reg rom_bk_en;


always@(*)
begin
    free_run_cmd        = (recv_cmd == 0);
    debug_cmd           = (recv_cmd == 1);
    clear_rom_addr_cmd  = (recv_cmd == 2);
    clear_rom_data_cmd  = (recv_cmd == 3);
    read_rom_cmd        = (recv_cmd == 4);
    write_rom_cmd       = (recv_cmd == 5);
    read_a_cmd          = (recv_cmd == 6);
    read_b_cmd          = (recv_cmd == 7);
    read_c_cmd          = (recv_cmd == 8);
    read_d_cmd          = (recv_cmd == 9);
end


always@(posedge clk)
begin
    if(free_run_cmd)
        dbg_en <= 0;
    else if(debug_cmd)
        dbg_en <= 1;
end


always@(posedge clk)
begin
    dbg_inst_en <= recv_en && debug_cmd;
    if(debug_cmd)
        dbg_inst <= recv_data;
end


always@(posedge clk)
begin
    read_abcd[0] <= recv_en && read_a_cmd;
    read_abcd[1] <= recv_en && read_b_cmd;
    read_abcd[2] <= recv_en && read_c_cmd;
    read_abcd[3] <= recv_en && read_d_cmd;
end


always@(posedge clk)
begin
    if(clear_rom_data_cmd)
        rom_wen <= 1;
    else
        rom_wen <= recv_en && write_rom_cmd;
end


always@(posedge clk)
begin
    if(clear_rom_addr_cmd)
        rom_waddr <= 0;
    else if(rom_wen)
        rom_waddr <= rom_waddr + 1;
end


always@(posedge clk)
begin
    if(clear_rom_data_cmd)
        rom_wdata <= 0;
    else if(recv_en && write_rom_cmd)
        rom_wdata <= recv_data;
end


always@(posedge clk)
begin
    rom_ren <= recv_en && read_rom_cmd;
end


always@(posedge clk)
begin
    if(clear_rom_addr_cmd)
        rom_raddr <= 0;
    else if(rom_ren)
        rom_raddr <= rom_raddr + 1;
end


always@(posedge clk)
begin
    rom_ren_d0 <= rom_ren;
    rom_ren_d1 <= rom_ren_d0;
    rom_bk_en <= rom_ren_d1;
end


always@(posedge clk)
begin
    send_en <= send_ready && (dbg_info_en || rom_bk_en);
end


always@(posedge clk)
begin
    if(dbg_info_en)
    begin
        send_cmd <= dbg_info[15:8];
        send_data <= dbg_info[7:0];
    end
    else if(rom_bk_en)
    begin
        send_cmd <= 0;
        send_data <= rom_rdata;
    end
end

endmodule
module debug
(
    input   wire		clk,
    

    output  reg			rom_wen,
    output  reg [23:0]	rom_waddr,
    output  reg [7:0]	rom_wdata,
    

    output  reg			rom_ren,
    output  reg  [23:0]	rom_raddr,
    input   wire [7:0]	rom_rdata,
    

    output  reg			dbg_en,
    output  reg			dbg_inst_en,
    output  reg  [7:0]	dbg_inst,
    

    output  reg  [3:0]	read_abcd,
    input   wire		dbg_info_en,
    input   wire [15:0]	dbg_info,
    

	input	wire		recv_en,
	input	wire [7:0]	recv_cmd,
	input	wire [7:0]	recv_data,
    output  reg			send_en,
    output  reg  [7:0]	send_cmd,
    output  reg  [7:0]	send_data,
    input   wire		send_ready
);


reg free_run_cmd;
reg debug_cmd;
reg clear_rom_addr_cmd;
reg clear_rom_data_cmd;
reg read_rom_cmd;
reg write_rom_cmd;
reg read_a_cmd;
reg read_b_cmd;
reg read_c_cmd;
reg read_d_cmd;
reg rom_ren_d0;
reg rom_ren_d1;
reg rom_bk_en;


always@(*)
begin
    free_run_cmd        = (recv_cmd == 0);
    debug_cmd           = (recv_cmd == 1);
    clear_rom_addr_cmd  = (recv_cmd == 2);
    clear_rom_data_cmd  = (recv_cmd == 3);
    read_rom_cmd        = (recv_cmd == 4);
    write_rom_cmd       = (recv_cmd == 5);
    read_a_cmd          = (recv_cmd == 6);
    read_b_cmd          = (recv_cmd == 7);
    read_c_cmd          = (recv_cmd == 8);
    read_d_cmd          = (recv_cmd == 9);
end


always@(posedge clk)
begin
    if(free_run_cmd)
        dbg_en <= 0;
    else if(debug_cmd)
        dbg_en <= 1;
end


always@(posedge clk)
begin
    dbg_inst_en <= recv_en && debug_cmd;
    if(debug_cmd)
        dbg_inst <= recv_data;
end


always@(posedge clk)
begin
    read_abcd[0] <= recv_en && read_a_cmd;
    read_abcd[1] <= recv_en && read_b_cmd;
    read_abcd[2] <= recv_en && read_c_cmd;
    read_abcd[3] <= recv_en && read_d_cmd;
end


always@(posedge clk)
begin
    if(clear_rom_data_cmd)
        rom_wen <= 1;
    else
        rom_wen <= recv_en && write_rom_cmd;
end


always@(posedge clk)
begin
    if(clear_rom_addr_cmd)
        rom_waddr <= 0;
    else if(rom_wen)
        rom_waddr <= rom_waddr + 1;
end


always@(posedge clk)
begin
    if(clear_rom_data_cmd)
        rom_wdata <= 0;
    else if(recv_en && write_rom_cmd)
        rom_wdata <= recv_data;
end


always@(posedge clk)
begin
    rom_ren <= recv_en && read_rom_cmd;
end


always@(posedge clk)
begin
    if(clear_rom_addr_cmd)
        rom_raddr <= 0;
    else if(rom_ren)
        rom_raddr <= rom_raddr + 1;
end


always@(posedge clk)
begin
    rom_ren_d0 <= rom_ren;
    rom_ren_d1 <= rom_ren_d0;
    rom_bk_en <= rom_ren_d1;
end


always@(posedge clk)
begin
    send_en <= send_ready && (dbg_info_en || rom_bk_en);
end


always@(posedge clk)
begin
    if(dbg_info_en)
    begin
        send_cmd <= dbg_info[15:8];
        send_data <= dbg_info[7:0];
    end
    else if(rom_bk_en)
    begin
        send_cmd <= 0;
        send_data <= rom_rdata;
    end
end

endmodule