data/full_repos/permissive/124999927/tb/tb_fifo_sync.v
1: b'%Error: data/full_repos/permissive/124999927/tb/tb_fifo_sync.v:34: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_fifo_sync.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/124999927/tb/tb_fifo_sync.v:35: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/124999927/tb/tb_fifo_sync.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #(RESET_DURATION * CLK_PERIOD);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/124999927/tb/tb_fifo_sync.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/124999927/tb/tb_fifo_sync.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/124999927/tb/tb_fifo_sync.v:84: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/124999927/tb/tb_fifo_sync.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/124999927/tb/tb_fifo_sync.v:109: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/124999927/tb/tb_fifo_sync.v:124: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/124999927/tb/tb_fifo_sync.v:139: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/124999927/tb/tb_fifo_sync.v:151: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/124999927/tb/tb_fifo_sync.v:167: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD / 2);\n    ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_fifo_sync;

  localparam CLK_PERIOD = 2;
  localparam RESET_DURATION = 5;

  localparam DATA_W = 10;
  localparam SIZE = 16;

  reg clk;
  reg aresetn;

  wire [DATA_W - 1:0] data_rd;
  reg rd_en;

  reg [DATA_W - 1:0] data_wr;
  reg wr_en;

  wire [$clog2(SIZE):0] data_count;
  wire full;
  wire overflow;
  wire empty;
  wire underflow;

  reg [DATA_W - 1:0] test_data [0:SIZE];

  integer i;
  initial begin
    $dumpfile("tb_fifo_sync.vcd");
    $dumpvars;

    clk = 0;
    aresetn = 0;

    rd_en = 0;
    data_wr = 0;
    wr_en = 0;


    for(i = 0; i < SIZE + 1; i = i + 1) begin
      test_data[i] = $random % (1 << DATA_W);
    end

    #(RESET_DURATION * CLK_PERIOD);

    aresetn = 1;

    #(CLK_PERIOD);

    $display("Reset test!");

    `ASSERT(data_count == 0)
    `ASSERT(full == 0)
    `ASSERT(overflow == 0)
    `ASSERT(empty == 1)
    `ASSERT(underflow == 0)

    rd_en = 1;

    #(CLK_PERIOD);

    $display("Testing underflow condition!");

    `ASSERT(data_count == 0)
    `ASSERT(full == 0)
    `ASSERT(overflow == 0)
    `ASSERT(empty == 1)
    `ASSERT(underflow == 1)

    rd_en = 0;

    $display("Testing data write!");
    wr_en = 1;
    for(i = 0; i < SIZE; i = i + 1) begin
      $display("[%d] writing %d", i, test_data[i]);

      data_wr = test_data[i];

      #(CLK_PERIOD);

      `ASSERT(data_count == i + 1)
      `ASSERT(full == (i == SIZE - 1))
      `ASSERT(overflow == 0)
      `ASSERT(empty == 0)
      `ASSERT(underflow == 0)
    end

    data_wr = test_data[SIZE];

    #(CLK_PERIOD);

    $display("Testing overflow condition!");

    `ASSERT(data_count == SIZE)
    `ASSERT(full == 1)
    `ASSERT(overflow == 1)
    `ASSERT(empty == 0)
    `ASSERT(underflow == 0)

    $display("Testing data read!");
    wr_en = 0;
    rd_en = 1;
    for(i = 1; i <= SIZE; i = i + 1) begin
      #(CLK_PERIOD);

      `ASSERT(data_rd == test_data[i])
      `ASSERT(data_count == SIZE - i)
      `ASSERT(full == 0)
      `ASSERT(overflow == 0)
      `ASSERT(empty == (i == SIZE))
      `ASSERT(underflow == 0)

    end

    wr_en = 1;
    rd_en = 0;
    for(i = 0; i < SIZE / 2; i = i + 1) begin
      data_wr = test_data[i];
      #(CLK_PERIOD);

      `ASSERT(data_count == i + 1)
      `ASSERT(full == 0)
      `ASSERT(overflow == 0)
      `ASSERT(empty == 0)
      `ASSERT(underflow == 0)
    end

    $display("Testing read and write at the same time!");
    wr_en = 1;
    rd_en = 1;
    for(i = 0; i < SIZE / 2; i = i + 1) begin
      data_wr = test_data[i + SIZE / 2];

      #(CLK_PERIOD);

      `ASSERT(data_rd == test_data[i])
      `ASSERT(data_count == SIZE / 2)
      `ASSERT(full == 0)
      `ASSERT(overflow == 0)
      `ASSERT(empty == 0)
      `ASSERT(underflow == 0)
    end

    wr_en = 0;
    for(i = SIZE / 2; i < SIZE; i = i + 1) begin
      #(CLK_PERIOD);

      `ASSERT(data_rd == test_data[i])
      `ASSERT(data_count == SIZE - i - 1)
      `ASSERT(full == 0)
      `ASSERT(overflow == 0)
      `ASSERT(empty == (i == SIZE - 1))
      `ASSERT(underflow == 0)
    end

    $display("All assertions passed!");
    $finish;
  end


  always begin
    #(CLK_PERIOD / 2);
    clk = ~clk;
  end


  fifo_sync#(
    .DATA_W(DATA_W),
    .SIZE(SIZE)
  ) dut(
    .clk(clk),
    .aresetn(aresetn),


    .data_wr(data_wr),

    .wr_en(wr_en),


    .data_rd(data_rd),

    .rd_en(rd_en),


    .data_count(data_count),

    .full(full),

    .overflow(overflow),

    .empty(empty),

    .underflow(underflow)
  );

endmodule
module tb_fifo_sync;


  localparam CLK_PERIOD = 2;
  localparam RESET_DURATION = 5;

  localparam DATA_W = 10;
  localparam SIZE = 16;

  reg clk;
  reg aresetn;

  wire [DATA_W - 1:0] data_rd;
  reg rd_en;

  reg [DATA_W - 1:0] data_wr;
  reg wr_en;

  wire [$clog2(SIZE):0] data_count;
  wire full;
  wire overflow;
  wire empty;
  wire underflow;

  reg [DATA_W - 1:0] test_data [0:SIZE];

  integer i;
  initial begin
    $dumpfile("tb_fifo_sync.vcd");
    $dumpvars;

    clk = 0;
    aresetn = 0;

    rd_en = 0;
    data_wr = 0;
    wr_en = 0;


    for(i = 0; i < SIZE + 1; i = i + 1) begin
      test_data[i] = $random % (1 << DATA_W);
    end

    #(RESET_DURATION * CLK_PERIOD);

    aresetn = 1;

    #(CLK_PERIOD);

    $display("Reset test!");

    `ASSERT(data_count == 0)
    `ASSERT(full == 0)
    `ASSERT(overflow == 0)
    `ASSERT(empty == 1)
    `ASSERT(underflow == 0)

    rd_en = 1;

    #(CLK_PERIOD);

    $display("Testing underflow condition!");

    `ASSERT(data_count == 0)
    `ASSERT(full == 0)
    `ASSERT(overflow == 0)
    `ASSERT(empty == 1)
    `ASSERT(underflow == 1)

    rd_en = 0;

    $display("Testing data write!");
    wr_en = 1;
    for(i = 0; i < SIZE; i = i + 1) begin
      $display("[%d] writing %d", i, test_data[i]);

      data_wr = test_data[i];

      #(CLK_PERIOD);

      `ASSERT(data_count == i + 1)
      `ASSERT(full == (i == SIZE - 1))
      `ASSERT(overflow == 0)
      `ASSERT(empty == 0)
      `ASSERT(underflow == 0)
    end

    data_wr = test_data[SIZE];

    #(CLK_PERIOD);

    $display("Testing overflow condition!");

    `ASSERT(data_count == SIZE)
    `ASSERT(full == 1)
    `ASSERT(overflow == 1)
    `ASSERT(empty == 0)
    `ASSERT(underflow == 0)

    $display("Testing data read!");
    wr_en = 0;
    rd_en = 1;
    for(i = 1; i <= SIZE; i = i + 1) begin
      #(CLK_PERIOD);

      `ASSERT(data_rd == test_data[i])
      `ASSERT(data_count == SIZE - i)
      `ASSERT(full == 0)
      `ASSERT(overflow == 0)
      `ASSERT(empty == (i == SIZE))
      `ASSERT(underflow == 0)

    end

    wr_en = 1;
    rd_en = 0;
    for(i = 0; i < SIZE / 2; i = i + 1) begin
      data_wr = test_data[i];
      #(CLK_PERIOD);

      `ASSERT(data_count == i + 1)
      `ASSERT(full == 0)
      `ASSERT(overflow == 0)
      `ASSERT(empty == 0)
      `ASSERT(underflow == 0)
    end

    $display("Testing read and write at the same time!");
    wr_en = 1;
    rd_en = 1;
    for(i = 0; i < SIZE / 2; i = i + 1) begin
      data_wr = test_data[i + SIZE / 2];

      #(CLK_PERIOD);

      `ASSERT(data_rd == test_data[i])
      `ASSERT(data_count == SIZE / 2)
      `ASSERT(full == 0)
      `ASSERT(overflow == 0)
      `ASSERT(empty == 0)
      `ASSERT(underflow == 0)
    end

    wr_en = 0;
    for(i = SIZE / 2; i < SIZE; i = i + 1) begin
      #(CLK_PERIOD);

      `ASSERT(data_rd == test_data[i])
      `ASSERT(data_count == SIZE - i - 1)
      `ASSERT(full == 0)
      `ASSERT(overflow == 0)
      `ASSERT(empty == (i == SIZE - 1))
      `ASSERT(underflow == 0)
    end

    $display("All assertions passed!");
    $finish;
  end


  always begin
    #(CLK_PERIOD / 2);
    clk = ~clk;
  end


  fifo_sync#(
    .DATA_W(DATA_W),
    .SIZE(SIZE)
  ) dut(
    .clk(clk),
    .aresetn(aresetn),


    .data_wr(data_wr),

    .wr_en(wr_en),


    .data_rd(data_rd),

    .rd_en(rd_en),


    .data_count(data_count),

    .full(full),

    .overflow(overflow),

    .empty(empty),

    .underflow(underflow)
  );

endmodule