data/full_repos/permissive/166661632/p6/p6-HAC VERSION/IFU.v
1: b'%Error: Cannot find file containing module: VERSION,data/full_repos/permissive/166661632\n        ... Looked in:\n             data/full_repos/permissive/166661632/p6/p6-HAC/VERSION,data/full_repos/permissive/166661632\n             data/full_repos/permissive/166661632/p6/p6-HAC/VERSION,data/full_repos/permissive/166661632.v\n             data/full_repos/permissive/166661632/p6/p6-HAC/VERSION,data/full_repos/permissive/166661632.sv\n             VERSION,data/full_repos/permissive/166661632\n             VERSION,data/full_repos/permissive/166661632.v\n             VERSION,data/full_repos/permissive/166661632.sv\n             obj_dir/VERSION,data/full_repos/permissive/166661632\n             obj_dir/VERSION,data/full_repos/permissive/166661632.v\n             obj_dir/VERSION,data/full_repos/permissive/166661632.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/166661632/p6/p6-HAC\n%Error: Cannot find file containing module: VERSION/IFU.v\n%Error: Exiting due to 3 error(s)\n'
module IFU (clk,clr,stall,branch,intreq,npcout,instr,pc8);
input clk,clr,stall,branch,intreq;
input [31:0] npcout;
output [31:0] instr,pc8;

reg [31:0] inmem[4095:0];
reg [31:0]pc;

integer i;
initial begin


	pc=32'h00003000;
	$readmemh("code.txt",inmem);
	$readmemh("code_handler.txt",inmem,1120,2047);
end

always @(posedge clk)
begin
	if (clr)
		pc<=32'h00003000;
	else if (intreq)
		pc<=npcout;
	else if(stall)
		pc<=pc;
	else if(branch)
		pc<=npcout;
	else
		pc<=pc+4;
end
wire [31:0] add=pc-32'h00003000;
assign instr=inmem[add[31:2]];
assign pc8=pc+8;
endmodule
module IFU (clk,clr,stall,branch,intreq,npcout,instr,pc8);

input clk,clr,stall,branch,intreq;
input [31:0] npcout;
output [31:0] instr,pc8;

reg [31:0] inmem[4095:0];
reg [31:0]pc;

integer i;
initial begin


	pc=32'h00003000;
	$readmemh("code.txt",inmem);
	$readmemh("code_handler.txt",inmem,1120,2047);
end

always @(posedge clk)
begin
	if (clr)
		pc<=32'h00003000;
	else if (intreq)
		pc<=npcout;
	else if(stall)
		pc<=pc;
	else if(branch)
		pc<=npcout;
	else
		pc<=pc+4;
end
wire [31:0] add=pc-32'h00003000;
assign instr=inmem[add[31:2]];
assign pc8=pc+8;
endmodule