data/full_repos/permissive/193759799/src/ALUControl.v
data/verilator_xmls/41c6d68b-f699-4231-bfc9-9871e26ceec7.xml
module ALUControl (
  input       [1:0] ALUOp,
  input       [5:0] OpCode,
  input       [5:0] Funct,
  output reg  [3:0] ALUControlOut
  );

  always @(*)
  begin
    case (ALUOp)
      2'b00: ALUControlOut <= 4'b0001;
      2'b01: ALUControlOut <= 4'b0010;
      2'b10:
        begin
          case (Funct)
            6'b100000: ALUControlOut <= 4'b0000;
            6'b100001: ALUControlOut <= 4'b0001;
            6'b100010: ALUControlOut <= 4'b0010;
            6'b100011: ALUControlOut <= 4'b0011;
            6'b100101: ALUControlOut <= 4'b0101;
            6'b100110: ALUControlOut <= 4'b0110;
            6'b101000: ALUControlOut <= 4'b1000;
            6'b101001: ALUControlOut <= 4'b1001;
          endcase
        end
      2'b11:
        begin
          case (OpCode)
            6'b110000: ALUControlOut <= 4'b0000;
            6'b110001: ALUControlOut <= 4'b0001;
          endcase
        end
    endcase
  end

endmodule
module ALUControl (
  input       [1:0] ALUOp,
  input       [5:0] OpCode,
  input       [5:0] Funct,
  output reg  [3:0] ALUControlOut
  );


  always @(*)
  begin
    case (ALUOp)
      2'b00: ALUControlOut <= 4'b0001;
      2'b01: ALUControlOut <= 4'b0010;
      2'b10:
        begin
          case (Funct)
            6'b100000: ALUControlOut <= 4'b0000;
            6'b100001: ALUControlOut <= 4'b0001;
            6'b100010: ALUControlOut <= 4'b0010;
            6'b100011: ALUControlOut <= 4'b0011;
            6'b100101: ALUControlOut <= 4'b0101;
            6'b100110: ALUControlOut <= 4'b0110;
            6'b101000: ALUControlOut <= 4'b1000;
            6'b101001: ALUControlOut <= 4'b1001;
          endcase
        end
      2'b11:
        begin
          case (OpCode)
            6'b110000: ALUControlOut <= 4'b0000;
            6'b110001: ALUControlOut <= 4'b0001;
          endcase
        end
    endcase
  end

endmodule