data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v
 line:23: before: ")"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_rst  = 1\'b1;               \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b000000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_funct     = 6\'b000010;     \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_funct     = 6\'b000011;     \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_funct     = 6\'b001000;     \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_funct     = 6\'b001001;     \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_funct     = 6\'b100000;     \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b100000;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b100001;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b100011;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b100111;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b100100;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b100101;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b101000;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b101001;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b101011;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b001000;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b001100;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b001101;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b001110;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b001111;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b001010;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b000100;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b000101;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b000010;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #10 i_opcode    = 6\'b000011;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Error: data/full_repos/permissive/206437232/TP4-MIPS-2019/Test/tb_control.v:93: Cannot find file containing module: \'control\'\n    control\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/control\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/control.v\n             data/full_repos/permissive/206437232/TP4-MIPS-2019/Test,data/full_repos/permissive/206437232/control.sv\n             control\n             control.v\n             control.sv\n             obj_dir/control\n             obj_dir/control.v\n             obj_dir/control.sv\n%Error: Exiting due to 1 error(s), 28 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_control#();
 	


    parameter NB_OPCODE     = 6;
    parameter NB_CTRL_EX    = 10;
    parameter NB_CTRL_M     = 9;
    parameter NB_CTRL_WB    = 2;
    

    reg                         i_rst;
    reg [NB_OPCODE-1:0]         i_opcode;
    reg [NB_OPCODE-1:0]         i_funct;
    

    wire  [NB_CTRL_WB-1:0]      o_ctrl_wb_bus;
    wire  [NB_CTRL_M-1:0]       o_ctrl_mem_bus;
    wire  [NB_CTRL_EX-1:0]      o_ctrl_exc_bus;

    
    initial    
    begin
    #1
    i_opcode = 0;
    i_funct  = 0;

    i_rst  = 1'b0;
    #10 i_rst  = 1'b1;
    

    #10 i_opcode    = 6'b000000;
        i_funct     = 6'b000000;
        
    #10 i_funct     = 6'b000010;
    #10 i_funct     = 6'b000011;
    #10 i_funct     = 6'b001000;
    #10 i_funct     = 6'b001001;
    #10 i_funct     = 6'b100000;
    

    #10 i_opcode    = 6'b100000;
    #10 i_opcode    = 6'b100001;
    #10 i_opcode    = 6'b100011;
    #10 i_opcode    = 6'b100111;
    #10 i_opcode    = 6'b100100;
    #10 i_opcode    = 6'b100101;
    

    #10 i_opcode    = 6'b101000;
    #10 i_opcode    = 6'b101001;
    #10 i_opcode    = 6'b101011;
    

    #10 i_opcode    = 6'b001000;
    #10 i_opcode    = 6'b001100;
    #10 i_opcode    = 6'b001101;
    #10 i_opcode    = 6'b001110;
    #10 i_opcode    = 6'b001111;
    #10 i_opcode    = 6'b001010;
    

    #10 i_opcode    = 6'b000100;
    #10 i_opcode    = 6'b000101;
    #10 i_opcode    = 6'b000010;
    #10 i_opcode    = 6'b000011;
    
    #10 $finish;
    end
    

    control
    #(
    .NB_OPCODE          (NB_OPCODE      ),
    .NB_CTRL_EX         (NB_CTRL_EX     ),
    .NB_CTRL_M          (NB_CTRL_M      ),
    .NB_CTRL_WB         (NB_CTRL_WB     )
    )
    u_control
    (
    .i_rst              (i_rst          ),
    .i_opcode           (i_opcode       ),
    .i_funct            (i_funct        ),
    .o_ctrl_wb_bus      (o_ctrl_wb_bus  ),
    .o_ctrl_mem_bus     (o_ctrl_mem_bus ),
    .o_ctrl_exc_bus     (o_ctrl_exc_bus )
    );

endmodule
module tb_control#();

 	


    parameter NB_OPCODE     = 6;
    parameter NB_CTRL_EX    = 10;
    parameter NB_CTRL_M     = 9;
    parameter NB_CTRL_WB    = 2;
    

    reg                         i_rst;
    reg [NB_OPCODE-1:0]         i_opcode;
    reg [NB_OPCODE-1:0]         i_funct;
    

    wire  [NB_CTRL_WB-1:0]      o_ctrl_wb_bus;
    wire  [NB_CTRL_M-1:0]       o_ctrl_mem_bus;
    wire  [NB_CTRL_EX-1:0]      o_ctrl_exc_bus;

    
    initial    
    begin
    #1
    i_opcode = 0;
    i_funct  = 0;

    i_rst  = 1'b0;
    #10 i_rst  = 1'b1;
    

    #10 i_opcode    = 6'b000000;
        i_funct     = 6'b000000;
        
    #10 i_funct     = 6'b000010;
    #10 i_funct     = 6'b000011;
    #10 i_funct     = 6'b001000;
    #10 i_funct     = 6'b001001;
    #10 i_funct     = 6'b100000;
    

    #10 i_opcode    = 6'b100000;
    #10 i_opcode    = 6'b100001;
    #10 i_opcode    = 6'b100011;
    #10 i_opcode    = 6'b100111;
    #10 i_opcode    = 6'b100100;
    #10 i_opcode    = 6'b100101;
    

    #10 i_opcode    = 6'b101000;
    #10 i_opcode    = 6'b101001;
    #10 i_opcode    = 6'b101011;
    

    #10 i_opcode    = 6'b001000;
    #10 i_opcode    = 6'b001100;
    #10 i_opcode    = 6'b001101;
    #10 i_opcode    = 6'b001110;
    #10 i_opcode    = 6'b001111;
    #10 i_opcode    = 6'b001010;
    

    #10 i_opcode    = 6'b000100;
    #10 i_opcode    = 6'b000101;
    #10 i_opcode    = 6'b000010;
    #10 i_opcode    = 6'b000011;
    
    #10 $finish;
    end
    

    control
    #(
    .NB_OPCODE          (NB_OPCODE      ),
    .NB_CTRL_EX         (NB_CTRL_EX     ),
    .NB_CTRL_M          (NB_CTRL_M      ),
    .NB_CTRL_WB         (NB_CTRL_WB     )
    )
    u_control
    (
    .i_rst              (i_rst          ),
    .i_opcode           (i_opcode       ),
    .i_funct            (i_funct        ),
    .o_ctrl_wb_bus      (o_ctrl_wb_bus  ),
    .o_ctrl_mem_bus     (o_ctrl_mem_bus ),
    .o_ctrl_exc_bus     (o_ctrl_exc_bus )
    );

endmodule