data/full_repos/permissive/181665138/references/verilog/RL-20190214.v
 line:34: before: "=="
1: b"%Error: data/full_repos/permissive/181665138/references/verilog/RL-20190214.v:34: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(reset_ == 0) #1 begin\n                    ^~\n%Error: data/full_repos/permissive/181665138/references/verilog/RL-20190214.v:75: syntax error, unexpected '=', expecting IDENTIFIER\n        mia_funzione = ((abs_di_intero(A1) - abs_di_intero(A2)) < 0) ? A2:A1;\n                     ^\n%Error: data/full_repos/permissive/181665138/references/verilog/RL-20190214.v:80: syntax error, unexpected '=', expecting IDENTIFIER\n        abs_di_intero = (A[7] == 0)? A:(~A + 1);\n                      ^\n%Error: Cannot continue\n"
function [7:0] abs_di_intero;
        input   [7:0]   A;
        abs_di_intero = (A[7] == 0)? A:(~A + 1);
    endfunction
function [7:0] abs_di_intero;

        input   [7:0]   A;
        abs_di_intero = (A[7] == 0)? A:(~A + 1);
    endfunction