data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v
 line:846: before: ")"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:581: Signal definition not found, creating implicitly: \'OTG_FSPEED\'\nassign OTG_FSPEED = 1\'bz;\n       ^~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:582: Signal definition not found, creating implicitly: \'OTG_LSPEED\'\n                                                                                          : ... Suggested alternative: \'OTG_FSPEED\'\nassign OTG_LSPEED = 1\'bz;\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:601: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 36 bits.\n                                                                                       : ... In instance DE2_115_Default\nassign mSEG7_DIG = { key_ascii_D[7:4], key_ascii_D[3:0],\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:607: Operator ADD expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'PUT_ROW\' generates 5 bits.\n                                                                                       : ... In instance DE2_115_Default\nassign ROW_Cursor = (PUT_ROW+1)*16+1;\n                            ^\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:611: Cannot find file containing module: \'Reset_Delay\'\nReset_Delay   r0 ( .iCLK(CLOCK_50),.oRESET(DLY_RST) );\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/107499099/mips_de2-115,data/full_repos/permissive/107499099/Reset_Delay\n             data/full_repos/permissive/107499099/mips_de2-115,data/full_repos/permissive/107499099/Reset_Delay.v\n             data/full_repos/permissive/107499099/mips_de2-115,data/full_repos/permissive/107499099/Reset_Delay.sv\n             Reset_Delay\n             Reset_Delay.v\n             Reset_Delay.sv\n             obj_dir/Reset_Delay\n             obj_dir/Reset_Delay.v\n             obj_dir/Reset_Delay.sv\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:613: Cannot find file containing module: \'VGA_Audio_PLL\'\nVGA_Audio_PLL   p1 ( .areset(~DLY_RST),.inclk0(CLOCK2_50),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(mVGA_CLK) );\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:616: Cannot find file containing module: \'SEG7_LUT_8\'\nSEG7_LUT_8    u0 ( .oSEG0(HEX0),\n^~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:631: Cannot find file containing module: \'VGA_Controller\'\nVGA_Controller  u1 (  \n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:658: Cannot find file containing module: \'VGA_OSD_RAM\'\nVGA_OSD_RAM   u2 (  \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:680: Cannot find file containing module: \'I2C_AV_Config\'\nI2C_AV_Config   u3 (  \n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:687: Cannot find file containing module: \'AUDIO_DAC\'\nAUDIO_DAC    u4 (  \n^~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:697: Cannot find file containing module: \'LCD_TEST\'\nLCD_TEST    u5 (  \n^~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:711: Cannot find file containing module: \'KEYBOARD_DEC\'\nKEYBOARD_DEC u6 (  \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:725: Cannot find file containing module: \'VGA_CHAR_RAM\'\nVGA_CHAR_RAM u7 (  \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:745: Cannot find file containing module: \'update_monitor_rom\'\nupdate_monitor_rom  update_rom(.addr(romMonitorAddr), .data(romMonitorRdat));\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:747: Cannot find file containing module: \'VGA_CHAR_Ctrl\'\nVGA_CHAR_Ctrl u8 (  \n^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:789: Operator ASSIGNDLY expects 36 bits on the Assign RHS, but Assign RHS\'s VARREF \'RAM_WDATA\' generates 32 bits.\n                                                                                       : ... In instance DE2_115_Default\n   gpio_reg <= RAM_WDATA;\n            ^~\n%Error: data/full_repos/permissive/107499099/mips_de2-115/DE2_115_Default.v:819: Cannot find file containing module: \'cpu\'\ncpu u9(  \n^~~\n%Error: Exiting due to 13 error(s), 5 warning(s)\n'
module DE2_115_Default(


	CLOCK_50,
   CLOCK2_50,
   CLOCK3_50,
	ENETCLK_25,


	SMA_CLKIN,
	SMA_CLKOUT,


	LEDG,
	LEDR,


	KEY,


	SW,


	HEX0,
	HEX1,
	HEX2,
	HEX3,
	HEX4,
	HEX5,
	HEX6,
	HEX7,


	LCD_BLON,
	LCD_DATA,
	LCD_EN,
	LCD_ON,
	LCD_RS,
	LCD_RW,


	UART_CTS,
	UART_RTS,
	UART_RXD,
	UART_TXD,


	PS2_CLK,
	PS2_DAT,
	PS2_CLK2,
	PS2_DAT2,


	SD_CLK,
	SD_CMD,
	SD_DAT,
	SD_WP_N,


	VGA_B,
	VGA_BLANK_N,
	VGA_CLK,
	VGA_G,
	VGA_HS,
	VGA_R,
	VGA_SYNC_N,
	VGA_VS,


	AUD_ADCDAT,
	AUD_ADCLRCK,
	AUD_BCLK,
	AUD_DACDAT,
	AUD_DACLRCK,
	AUD_XCK,


	EEP_I2C_SCLK,
	EEP_I2C_SDAT,


	I2C_SCLK,
	I2C_SDAT,


	ENET0_GTX_CLK,
	ENET0_INT_N,
	ENET0_MDC,
	ENET0_MDIO,
	ENET0_RST_N,
	ENET0_RX_CLK,
	ENET0_RX_COL,
	ENET0_RX_CRS,
	ENET0_RX_DATA,
	ENET0_RX_DV,
	ENET0_RX_ER,
	ENET0_TX_CLK,
	ENET0_TX_DATA,
	ENET0_TX_EN,
	ENET0_TX_ER,
	ENET0_LINK100,


	ENET1_GTX_CLK,
	ENET1_INT_N,
	ENET1_MDC,
	ENET1_MDIO,
	ENET1_RST_N,
	ENET1_RX_CLK,
	ENET1_RX_COL,
	ENET1_RX_CRS,
	ENET1_RX_DATA,
	ENET1_RX_DV,
	ENET1_RX_ER,
	ENET1_TX_CLK,
	ENET1_TX_DATA,
	ENET1_TX_EN,
	ENET1_TX_ER,
	ENET1_LINK100,


	TD_CLK27,
	TD_DATA,
	TD_HS,
	TD_RESET_N,
	TD_VS,


   OTG_DATA,
   OTG_ADDR,
   OTG_CS_N,
   OTG_WR_N,
   OTG_RD_N,
   OTG_INT,
   OTG_RST_N,

	IRDA_RXD,


	DRAM_ADDR,
	DRAM_BA,
	DRAM_CAS_N,
	DRAM_CKE,
	DRAM_CLK,
	DRAM_CS_N,
	DRAM_DQ,
	DRAM_DQM,
	DRAM_RAS_N,
	DRAM_WE_N,


	SRAM_ADDR,
	SRAM_CE_N,
	SRAM_DQ,
	SRAM_LB_N,
	SRAM_OE_N,
	SRAM_UB_N,
	SRAM_WE_N,


	FL_ADDR,
	FL_CE_N,
	FL_DQ,
	FL_OE_N,
	FL_RST_N,
	FL_RY,
	FL_WE_N,
	FL_WP_N,


	GPIO,




	HSMC_CLKIN_P1,
	HSMC_CLKIN_P2,
	HSMC_CLKIN0,


	HSMC_CLKOUT_P1,
	HSMC_CLKOUT_P2,
	HSMC_CLKOUT0,
	HSMC_D,

	HSMC_RX_D_P,

	HSMC_TX_D_P,

   EX_IO	
);










input		          		CLOCK_50;
input		          		CLOCK2_50;
input		          		CLOCK3_50;
input		          		ENETCLK_25;


input		          		SMA_CLKIN;
output		          	SMA_CLKOUT;


output		   [8:0]		LEDG;
output	      [17:0]	LEDR;


input		      [3:0]		KEY;


input		      [17:0]	SW;


output		   [6:0]		HEX0;
output		   [6:0]		HEX1;
output		   [6:0]		HEX2;
output		   [6:0]		HEX3;
output		   [6:0]		HEX4;
output		   [6:0]		HEX5;
output		   [6:0]		HEX6;
output		   [6:0]		HEX7;


output		        		LCD_BLON;
inout		      [7:0]		LCD_DATA;
output		          	LCD_EN;
output		          	LCD_ON;
output		          	LCD_RS;
output		        		LCD_RW;


output		        		UART_CTS;
input		          		UART_RTS;
input		          		UART_RXD;
output		          	UART_TXD;


inout		          		PS2_CLK;
inout		          		PS2_DAT;
inout		          		PS2_CLK2;
inout		          		PS2_DAT2;


output		        		SD_CLK;
inout		          		SD_CMD;
inout		      [3:0]		SD_DAT;
input		          		SD_WP_N;


output		   [7:0]		VGA_B;
output		        		VGA_BLANK_N;
output		        		VGA_CLK;
output		   [7:0]		VGA_G;
output	          		VGA_HS;
output	      [7:0]		VGA_R;
output	         		VGA_SYNC_N;
output	          		VGA_VS;


input		          		AUD_ADCDAT;
inout		          		AUD_ADCLRCK;
inout		          		AUD_BCLK;
output		        		AUD_DACDAT;
inout		          		AUD_DACLRCK;
output		        		AUD_XCK;


output		        		EEP_I2C_SCLK;
inout		          		EEP_I2C_SDAT;


output		        		I2C_SCLK;
inout		          		I2C_SDAT;


output		        		ENET0_GTX_CLK;
input		          		ENET0_INT_N;
output		        		ENET0_MDC;
input		          		ENET0_MDIO;
output		        		ENET0_RST_N;
input		          		ENET0_RX_CLK;
input		          		ENET0_RX_COL;
input		          		ENET0_RX_CRS;
input		      [3:0]		ENET0_RX_DATA;
input		          		ENET0_RX_DV;
input		          		ENET0_RX_ER;
input		          		ENET0_TX_CLK;
output		   [3:0]		ENET0_TX_DATA;
output		        		ENET0_TX_EN;
output		        		ENET0_TX_ER;
input		          		ENET0_LINK100;


output		        		ENET1_GTX_CLK;
input		          		ENET1_INT_N;
output		        		ENET1_MDC;
input		          		ENET1_MDIO;
output		        		ENET1_RST_N;
input		          		ENET1_RX_CLK;
input		          		ENET1_RX_COL;
input		          		ENET1_RX_CRS;
input		      [3:0]		ENET1_RX_DATA;
input		          		ENET1_RX_DV;
input		          		ENET1_RX_ER;
input		          		ENET1_TX_CLK;
output		   [3:0]		ENET1_TX_DATA;
output		        		ENET1_TX_EN;
output		        		ENET1_TX_ER;
input		          		ENET1_LINK100;


input		          		TD_CLK27;
input		      [7:0]		TD_DATA;
input		          		TD_HS;
output		        		TD_RESET_N;
input		          		TD_VS;



inout           [15:0]  OTG_DATA;
output          [1:0]   OTG_ADDR;
output                  OTG_CS_N;
output                  OTG_WR_N;
output                  OTG_RD_N;
input                   OTG_INT;
output                  OTG_RST_N;


input		          		IRDA_RXD;


output		  [12:0]		DRAM_ADDR;
output	      [1:0]		DRAM_BA;
output		        		DRAM_CAS_N;
output		        		DRAM_CKE;
output		        		DRAM_CLK;
output		        		DRAM_CS_N;
inout		     [31:0]		DRAM_DQ;
output		   [3:0]		DRAM_DQM;
output		        		DRAM_RAS_N;
output		        		DRAM_WE_N;


output		  [19:0]		SRAM_ADDR;
output		        		SRAM_CE_N;
inout		     [15:0]		SRAM_DQ;
output		        		SRAM_LB_N;
output		        		SRAM_OE_N;
output		        		SRAM_UB_N;
output		        		SRAM_WE_N;


output	     [22:0]		FL_ADDR;
output		        		FL_CE_N;
inout		      [7:0]		FL_DQ;
output		        		FL_OE_N;
output		        		FL_RST_N;
input		          		FL_RY;
output		        		FL_WE_N;
output		        		FL_WP_N;


inout		     [35:0]		GPIO;





input		          		HSMC_CLKIN_P1;
input		          		HSMC_CLKIN_P2;
input		          		HSMC_CLKIN0;


output		          	HSMC_CLKOUT_P1;
output		          	HSMC_CLKOUT_P2;
output		          	HSMC_CLKOUT0;
inout		      [3:0]		HSMC_D;

input		      [16:0]	HSMC_RX_D_P;

output	      [16:0]	HSMC_TX_D_P;


inout		      [6:0]		EX_IO;








wire		   AUD_CTRL_CLK;

wire [31:0]	mSEG7_DIG;
wire		   VGA_CTRL_CLK;
wire  [9:0]	mVGA_R;
wire  [9:0]	mVGA_G;
wire  [9:0]	mVGA_B;
wire [19:0]	mVGA_ADDR;
wire 		mVGA_WEN;
wire	[9:0]	mVGA_CoordX;
wire	[9:0]	mVGA_CoordY;
wire		   DLY_RST;



wire			mVGA_CLK;
wire	[9:0]	mRed;
wire	[9:0]	mGreen;
wire	[9:0]	mBlue;
wire			VGA_Read;

wire  [9:0] recon_VGA_R;
wire  [9:0] recon_VGA_G;
wire  [9:0] recon_VGA_B;


wire	[3:0]	Remain;
wire	[9:0]	Quotient;

wire			mDVAL;






wire [7:0]  LCD_D_1;
wire        LCD_RW_1;
wire        LCD_EN_1;
wire        LCD_RS_1;




wire	[7:0]	key_data_D;
wire		key_parity_D;
wire		key_stopbit_D;
wire	[7:0]	key_ascii_D;
wire		key_stroke;


wire		pixel_val;


wire	[4:0]	PUT_ROW;
wire	[5:0]	PUT_COL;
wire		PUT_EN;
wire	[7:0]	PUT_DATA;

wire	[8:0]	ROW_Cursor;
wire	[9:0]	COL_Cursor;

wire	        CLOCK_CPU;
wire	[11:0]  PC;
wire	[31:0]	ALU_Y;
wire	[31:0]	ALU_A;
wire	[31:0]	ALU_B;
wire	[3:0]	ALU_CTRL;
wire	[1:0]	ALU_COMP;
wire	[31:0]	REG_DATA1;
wire	[4:0]	REG_IDX1;
wire	[31:0]	REG_DATA2;
wire	[4:0]	REG_IDX2;
wire	[31:0]	REG_WDATA;
wire	[4:0]	REG_WIDX;
wire		REG_WEN;
wire	[12:0]	RAM_ADDR;
wire	[31:0]	RAM_RDATA;
wire	[31:0]	RAM_WDATA;
wire		RAM_WEN;
wire	[12:0]	toRAM_ADDR;
wire	[31:0]	toRAM_WDATA;
wire		toRAM_WEN;

wire		cpu_clk;

reg cpu_clk_reg;
reg key1_reg;
reg sw0_reg;
reg sw1_reg;

reg  [31:0]	Cont;
reg [35:0] gpio_reg;








assign LCD_DATA = LCD_D_1;
assign LCD_RW   = LCD_RW_1;
assign LCD_EN   = LCD_EN_1;
assign LCD_RS   = LCD_RS_1; 
assign LCD_ON   = 1'b1;
assign LCD_BLON = 1'b0;

assign DRAM_DQ 			= 32'hzzzzzzzz;
 
assign AUD_ADCLRCK    	= 1'bz;     					
assign AUD_DACLRCK 		= 1'bz;     					
assign AUD_DACDAT 		= 1'bz;     					
assign AUD_BCLK 		   = 1'bz;     						
assign AUD_XCK 		   = 1'bz;     						
   						
assign I2C_SDAT 		   = 1'bz;     						
assign I2C_SCLK		   = 1'bz;
assign EEP_I2C_SDAT 		= 1'bz;     						
assign EEP_I2C_SCLK		= 1'bz;      						
assign SD_DAT 				= 4'bz;     							    						
assign SD_CMD 				= 1'bz;     						
assign SD_CLK 				= 1'bz;     						
assign OTG_DATA   		= 16'hzzzz;	

assign FL_DQ        		= 8'hzz;				


assign	SD_DAT		=	4'bz;
assign	GPIO   		=	36'hzzzzzzzz;


assign	OTG_FSPEED	=	1'bz;
assign	OTG_LSPEED	=	1'bz;


assign	DRAM_DQ		=	32'hzzzzzzzz;
assign	SRAM_DQ		=	16'hzzzz;
assign	SD_DAT		=	4'bz;


always@(posedge CLOCK_50 or negedge KEY[2])
    begin
        if(!KEY[2])
			 Cont	<=	0;
        else
			 Cont	<=	Cont+1;
    end

assign	TD_RESET_N	=	1'b1;
assign	AUD_ADCLRCK	=	AUD_DACLRCK;
assign	AUD_XCK	    =	AUD_CTRL_CLK;
assign	mSEG7_DIG	=	{	key_ascii_D[7:4], key_ascii_D[3:0],
					key_data_D[7:4], key_data_D[3:0], 8'b0000, PC};
assign	LEDR			=	{	Cont[26:24],Cont[26:24],Cont[26:24],
							Cont[26:24],Cont[26:24],Cont[26:24]	};
assign	LEDG			=	{	Cont[26:24],Cont[26:24],Cont[26:24]	};

assign	ROW_Cursor	=	(PUT_ROW+1)*16+1;
assign	COL_Cursor	=	PUT_COL*16;


Reset_Delay			r0	(	.iCLK(CLOCK_50),.oRESET(DLY_RST)	);

VGA_Audio_PLL 		p1	(	.areset(~DLY_RST),.inclk0(CLOCK2_50),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(mVGA_CLK)	);


SEG7_LUT_8 			u0	(	.oSEG0(HEX0),
							.oSEG1(HEX1),
							.oSEG2(HEX2),
							.oSEG3(HEX3),
							.oSEG4(HEX4),
							.oSEG5(HEX5),
							.oSEG6(HEX6),
							.oSEG7(HEX7),
							.iDIG(mSEG7_DIG) );




assign VGA_CLK = VGA_CTRL_CLK;

VGA_Controller		u1	(

							.iCursor_RGB_EN(4'hf),
							.iCursor_X(COL_Cursor),
							.iCursor_Y(ROW_Cursor),
							.iCursor_R(512),
							.iCursor_G(0),
							.iCursor_B(0),
							.oAddress(mVGA_ADDR),
							.oCoord_X(mVGA_CoordX),
							.oCoord_Y(mVGA_CoordY),
							.oWen(mVGA_WEN),
							.iRed(mVGA_R),
							.iGreen(mVGA_G),
							.iBlue(mVGA_B),

							.oVGA_R(VGA_R),
							.oVGA_G(VGA_G),
							.oVGA_B(VGA_B),
							.oVGA_H_SYNC(VGA_HS),
							.oVGA_V_SYNC(VGA_VS),
							.oVGA_SYNC(VGA_SYNC_N),
							.oVGA_BLANK(VGA_BLANK_N),

							.iCLK(VGA_CTRL_CLK),
							.iRST_N(DLY_RST)	);							 
							 
VGA_OSD_RAM			u2	(
							.oRed(mVGA_R),
							.oGreen(mVGA_G),
							.oBlue(mVGA_B),
							.iVGA_ADDR(mVGA_ADDR),
							.iVGA_CLK(VGA_CLK),

							.iWR_DATA(pixel_val),
							.iWR_ADDR(mVGA_ADDR),
							.iWR_EN(mVGA_WEN),
							.iWR_CLK(VGA_CLK),

							.iON_R(1023),
							.iON_G(1023),
							.iON_B(1023),
							.iOFF_R(0),
							.iOFF_G(0),
							.iOFF_B(512),

							.iRST_N(DLY_RST)	);
							

I2C_AV_Config 		u3	(
							.iCLK(CLOCK_50),
							.iRST_N(KEY[2]),

							.I2C_SCLK(I2C_SCLK),
							.I2C_SDAT(I2C_SDAT)	);

AUDIO_DAC 			u4	(
							.oAUD_BCK(AUD_BCLK),
							.oAUD_DATA(AUD_DACDAT),
							.oAUD_LRCK(AUD_DACLRCK),

							.iSrc_Select(SW[17]),
				         .iCLK_18_4(AUD_CTRL_CLK),
							.iRST_N(DLY_RST)	);


LCD_TEST 			u5	(
							.iCLK(CLOCK_50),
							.iRST_N(DLY_RST),

							.LCD_DATA(LCD_D_1),
							.LCD_RW(LCD_RW_1),
							.LCD_EN(LCD_EN_1),
							.LCD_RS(LCD_RS_1)	);




KEYBOARD_DEC u6 (
	.iClock          (CLOCK_50),
	.iReset_N        (KEY[2]),

	.iKeyboard_DATA  (PS2_DAT),
	.iKeyboard_CLOCK (PS2_CLK),

	.oKey_data_D     (key_data_D),
	.oKey_parity_D   (key_parity_D),
	.oKey_stopbit_D  (key_stopbit_D),
	.oKey_ascii_D    (key_ascii_D),
	.oKey_stroke     (key_stroke)
);

VGA_CHAR_RAM u7 (
	.oPIXEL_VAL  (pixel_val),
	.iVGA_ADDR   (mVGA_ADDR),
	.iVGA_CoordX (mVGA_CoordX),
	.iVGA_CoordY (mVGA_CoordY),
	.iVGA_CLK    (VGA_CLK),

	.iWR_DATA(PUT_DATA),

	.iWR_PUT_ROW (PUT_ROW),
	.iWR_PUT_COL (PUT_COL),
	.iWR_EN      (PUT_EN),
	.iWR_CLK     (VGA_CTRL_CLK),

	.iRST_N      (DLY_RST)
);


wire[9:0] romMonitorAddr;
wire[31:0] romMonitorRdat;
update_monitor_rom  update_rom(.addr(romMonitorAddr), .data(romMonitorRdat));

VGA_CHAR_Ctrl u8 (
	.ikey_ascii_D    (key_ascii_D),
	.ikey_stroke     (key_stroke),
	.imVGA_WEN       (mVGA_WEN),
	.iVGA_CLK        (VGA_CLK),
	.iCLOCK          (CLOCK_50),
	.iPC             (PC),
	.iALU_Y          (ALU_Y),
	.iALU_A          (ALU_A),
	.iALU_B          (ALU_B),
	.iALU_CTRL       (ALU_CTRL),
	.iALU_COMP       (ALU_COMP),
	.iREG_DATA1      (REG_DATA1),
	.iREG_IDX1       (REG_IDX1),
	.iREG_DATA2      (REG_DATA2),
	.iREG_IDX2       (REG_IDX2),
	.iREG_WDATA      (REG_WDATA),
	.iREG_WIDX       (REG_WIDX),
	.iREG_WEN        (REG_WEN),
	.iRAM_ADDR       (RAM_ADDR),
	.iRAM_RDATA      (RAM_RDATA),
	.iRAM_WDATA      (RAM_WDATA),
	.iRAM_WEN        (RAM_WEN),
	.oCurrentPosRow  (PUT_ROW),
	.oCurrentPosCol  (PUT_COL),
	.oPUT_EN         (PUT_EN),
	.oPUT_DATA       (PUT_DATA),
	.oRAM_ADDR       (toRAM_ADDR),
	.oRAM_WDATA      (toRAM_WDATA),
	.oRAM_WEN        (toRAM_WEN),
	.oROMmonitorADDR (romMonitorAddr),
	.iROMmonitorRDAT (romMonitorRdat),

	.iRST_N          (KEY[2])
);


always @(posedge CLOCK_50 or negedge KEY[2]) begin
	if (KEY[2] == 1'b0) begin
		gpio_reg <= 0;
	end else begin
		if ((RAM_ADDR == `GPIO0_ADDR) && (RAM_WEN == 1'b1)) begin
			gpio_reg <= RAM_WDATA;
		end
	end
end
                                                                                
assign GPIO = gpio_reg;

always @(posedge CLOCK_50 or negedge KEY[2]) begin
	if (KEY[2] == 1'b0) begin
		cpu_clk_reg <= 1'b0;
		key1_reg    <= 1'b0;
		sw0_reg     <= 1'b0;
		sw1_reg     <= 1'b0;
	end else begin
		if (key1_reg != KEY[3]) begin
			key1_reg <= KEY[3];
		end

		if (sw0_reg != SW[0]) begin
			sw0_reg <= SW[0];
		end

		if (sw1_reg != SW[1]) begin
			sw1_reg <= SW[1];
		end
	end
end

assign cpu_clk = CLOCK_50;

cpu u9(
	.clk          (cpu_clk),
	.reset        (KEY[2]),
	.clk_ctrl0    (sw0_reg),
	.clk_ctrl1    (sw1_reg),
	.clk_ctrl_clk (key1_reg),
	.o_clock      (CLOCK_CPU),
	.o_pc         (PC),
	.o_alu_y      (ALU_Y),
	.o_alu_a      (ALU_A),
	.o_alu_b      (ALU_B),
	.o_alu_ctrl   (ALU_CTRL),
	.o_alu_comp   (ALU_COMP),
	.o_reg_data1  (REG_DATA1),
	.o_reg_idx1   (REG_IDX1),
	.o_reg_data2  (REG_DATA2),
	.o_reg_idx2   (REG_IDX2),
	.o_reg_wdata  (REG_WDATA),
	.o_reg_widx   (REG_WIDX),
	.o_reg_wen    (REG_WEN),
	.o_ram_addr   (RAM_ADDR),
	.o_ram_rdata  (RAM_RDATA),
	.o_ram_wdata  (RAM_WDATA),
	.o_ram_wen    (RAM_WEN),
	.i_ram_addr   (toRAM_ADDR),
	.i_ram_wdata  (toRAM_WDATA),
	.i_ram_wen    (toRAM_WEN),
);

endmodule
module DE2_115_Default(


	CLOCK_50,
   CLOCK2_50,
   CLOCK3_50,
	ENETCLK_25,


	SMA_CLKIN,
	SMA_CLKOUT,


	LEDG,
	LEDR,


	KEY,


	SW,


	HEX0,
	HEX1,
	HEX2,
	HEX3,
	HEX4,
	HEX5,
	HEX6,
	HEX7,


	LCD_BLON,
	LCD_DATA,
	LCD_EN,
	LCD_ON,
	LCD_RS,
	LCD_RW,


	UART_CTS,
	UART_RTS,
	UART_RXD,
	UART_TXD,


	PS2_CLK,
	PS2_DAT,
	PS2_CLK2,
	PS2_DAT2,


	SD_CLK,
	SD_CMD,
	SD_DAT,
	SD_WP_N,


	VGA_B,
	VGA_BLANK_N,
	VGA_CLK,
	VGA_G,
	VGA_HS,
	VGA_R,
	VGA_SYNC_N,
	VGA_VS,


	AUD_ADCDAT,
	AUD_ADCLRCK,
	AUD_BCLK,
	AUD_DACDAT,
	AUD_DACLRCK,
	AUD_XCK,


	EEP_I2C_SCLK,
	EEP_I2C_SDAT,


	I2C_SCLK,
	I2C_SDAT,


	ENET0_GTX_CLK,
	ENET0_INT_N,
	ENET0_MDC,
	ENET0_MDIO,
	ENET0_RST_N,
	ENET0_RX_CLK,
	ENET0_RX_COL,
	ENET0_RX_CRS,
	ENET0_RX_DATA,
	ENET0_RX_DV,
	ENET0_RX_ER,
	ENET0_TX_CLK,
	ENET0_TX_DATA,
	ENET0_TX_EN,
	ENET0_TX_ER,
	ENET0_LINK100,


	ENET1_GTX_CLK,
	ENET1_INT_N,
	ENET1_MDC,
	ENET1_MDIO,
	ENET1_RST_N,
	ENET1_RX_CLK,
	ENET1_RX_COL,
	ENET1_RX_CRS,
	ENET1_RX_DATA,
	ENET1_RX_DV,
	ENET1_RX_ER,
	ENET1_TX_CLK,
	ENET1_TX_DATA,
	ENET1_TX_EN,
	ENET1_TX_ER,
	ENET1_LINK100,


	TD_CLK27,
	TD_DATA,
	TD_HS,
	TD_RESET_N,
	TD_VS,


   OTG_DATA,
   OTG_ADDR,
   OTG_CS_N,
   OTG_WR_N,
   OTG_RD_N,
   OTG_INT,
   OTG_RST_N,

	IRDA_RXD,


	DRAM_ADDR,
	DRAM_BA,
	DRAM_CAS_N,
	DRAM_CKE,
	DRAM_CLK,
	DRAM_CS_N,
	DRAM_DQ,
	DRAM_DQM,
	DRAM_RAS_N,
	DRAM_WE_N,


	SRAM_ADDR,
	SRAM_CE_N,
	SRAM_DQ,
	SRAM_LB_N,
	SRAM_OE_N,
	SRAM_UB_N,
	SRAM_WE_N,


	FL_ADDR,
	FL_CE_N,
	FL_DQ,
	FL_OE_N,
	FL_RST_N,
	FL_RY,
	FL_WE_N,
	FL_WP_N,


	GPIO,




	HSMC_CLKIN_P1,
	HSMC_CLKIN_P2,
	HSMC_CLKIN0,


	HSMC_CLKOUT_P1,
	HSMC_CLKOUT_P2,
	HSMC_CLKOUT0,
	HSMC_D,

	HSMC_RX_D_P,

	HSMC_TX_D_P,

   EX_IO	
);











input		          		CLOCK_50;
input		          		CLOCK2_50;
input		          		CLOCK3_50;
input		          		ENETCLK_25;


input		          		SMA_CLKIN;
output		          	SMA_CLKOUT;


output		   [8:0]		LEDG;
output	      [17:0]	LEDR;


input		      [3:0]		KEY;


input		      [17:0]	SW;


output		   [6:0]		HEX0;
output		   [6:0]		HEX1;
output		   [6:0]		HEX2;
output		   [6:0]		HEX3;
output		   [6:0]		HEX4;
output		   [6:0]		HEX5;
output		   [6:0]		HEX6;
output		   [6:0]		HEX7;


output		        		LCD_BLON;
inout		      [7:0]		LCD_DATA;
output		          	LCD_EN;
output		          	LCD_ON;
output		          	LCD_RS;
output		        		LCD_RW;


output		        		UART_CTS;
input		          		UART_RTS;
input		          		UART_RXD;
output		          	UART_TXD;


inout		          		PS2_CLK;
inout		          		PS2_DAT;
inout		          		PS2_CLK2;
inout		          		PS2_DAT2;


output		        		SD_CLK;
inout		          		SD_CMD;
inout		      [3:0]		SD_DAT;
input		          		SD_WP_N;


output		   [7:0]		VGA_B;
output		        		VGA_BLANK_N;
output		        		VGA_CLK;
output		   [7:0]		VGA_G;
output	          		VGA_HS;
output	      [7:0]		VGA_R;
output	         		VGA_SYNC_N;
output	          		VGA_VS;


input		          		AUD_ADCDAT;
inout		          		AUD_ADCLRCK;
inout		          		AUD_BCLK;
output		        		AUD_DACDAT;
inout		          		AUD_DACLRCK;
output		        		AUD_XCK;


output		        		EEP_I2C_SCLK;
inout		          		EEP_I2C_SDAT;


output		        		I2C_SCLK;
inout		          		I2C_SDAT;


output		        		ENET0_GTX_CLK;
input		          		ENET0_INT_N;
output		        		ENET0_MDC;
input		          		ENET0_MDIO;
output		        		ENET0_RST_N;
input		          		ENET0_RX_CLK;
input		          		ENET0_RX_COL;
input		          		ENET0_RX_CRS;
input		      [3:0]		ENET0_RX_DATA;
input		          		ENET0_RX_DV;
input		          		ENET0_RX_ER;
input		          		ENET0_TX_CLK;
output		   [3:0]		ENET0_TX_DATA;
output		        		ENET0_TX_EN;
output		        		ENET0_TX_ER;
input		          		ENET0_LINK100;


output		        		ENET1_GTX_CLK;
input		          		ENET1_INT_N;
output		        		ENET1_MDC;
input		          		ENET1_MDIO;
output		        		ENET1_RST_N;
input		          		ENET1_RX_CLK;
input		          		ENET1_RX_COL;
input		          		ENET1_RX_CRS;
input		      [3:0]		ENET1_RX_DATA;
input		          		ENET1_RX_DV;
input		          		ENET1_RX_ER;
input		          		ENET1_TX_CLK;
output		   [3:0]		ENET1_TX_DATA;
output		        		ENET1_TX_EN;
output		        		ENET1_TX_ER;
input		          		ENET1_LINK100;


input		          		TD_CLK27;
input		      [7:0]		TD_DATA;
input		          		TD_HS;
output		        		TD_RESET_N;
input		          		TD_VS;



inout           [15:0]  OTG_DATA;
output          [1:0]   OTG_ADDR;
output                  OTG_CS_N;
output                  OTG_WR_N;
output                  OTG_RD_N;
input                   OTG_INT;
output                  OTG_RST_N;


input		          		IRDA_RXD;


output		  [12:0]		DRAM_ADDR;
output	      [1:0]		DRAM_BA;
output		        		DRAM_CAS_N;
output		        		DRAM_CKE;
output		        		DRAM_CLK;
output		        		DRAM_CS_N;
inout		     [31:0]		DRAM_DQ;
output		   [3:0]		DRAM_DQM;
output		        		DRAM_RAS_N;
output		        		DRAM_WE_N;


output		  [19:0]		SRAM_ADDR;
output		        		SRAM_CE_N;
inout		     [15:0]		SRAM_DQ;
output		        		SRAM_LB_N;
output		        		SRAM_OE_N;
output		        		SRAM_UB_N;
output		        		SRAM_WE_N;


output	     [22:0]		FL_ADDR;
output		        		FL_CE_N;
inout		      [7:0]		FL_DQ;
output		        		FL_OE_N;
output		        		FL_RST_N;
input		          		FL_RY;
output		        		FL_WE_N;
output		        		FL_WP_N;


inout		     [35:0]		GPIO;





input		          		HSMC_CLKIN_P1;
input		          		HSMC_CLKIN_P2;
input		          		HSMC_CLKIN0;


output		          	HSMC_CLKOUT_P1;
output		          	HSMC_CLKOUT_P2;
output		          	HSMC_CLKOUT0;
inout		      [3:0]		HSMC_D;

input		      [16:0]	HSMC_RX_D_P;

output	      [16:0]	HSMC_TX_D_P;


inout		      [6:0]		EX_IO;








wire		   AUD_CTRL_CLK;

wire [31:0]	mSEG7_DIG;
wire		   VGA_CTRL_CLK;
wire  [9:0]	mVGA_R;
wire  [9:0]	mVGA_G;
wire  [9:0]	mVGA_B;
wire [19:0]	mVGA_ADDR;
wire 		mVGA_WEN;
wire	[9:0]	mVGA_CoordX;
wire	[9:0]	mVGA_CoordY;
wire		   DLY_RST;



wire			mVGA_CLK;
wire	[9:0]	mRed;
wire	[9:0]	mGreen;
wire	[9:0]	mBlue;
wire			VGA_Read;

wire  [9:0] recon_VGA_R;
wire  [9:0] recon_VGA_G;
wire  [9:0] recon_VGA_B;


wire	[3:0]	Remain;
wire	[9:0]	Quotient;

wire			mDVAL;






wire [7:0]  LCD_D_1;
wire        LCD_RW_1;
wire        LCD_EN_1;
wire        LCD_RS_1;




wire	[7:0]	key_data_D;
wire		key_parity_D;
wire		key_stopbit_D;
wire	[7:0]	key_ascii_D;
wire		key_stroke;


wire		pixel_val;


wire	[4:0]	PUT_ROW;
wire	[5:0]	PUT_COL;
wire		PUT_EN;
wire	[7:0]	PUT_DATA;

wire	[8:0]	ROW_Cursor;
wire	[9:0]	COL_Cursor;

wire	        CLOCK_CPU;
wire	[11:0]  PC;
wire	[31:0]	ALU_Y;
wire	[31:0]	ALU_A;
wire	[31:0]	ALU_B;
wire	[3:0]	ALU_CTRL;
wire	[1:0]	ALU_COMP;
wire	[31:0]	REG_DATA1;
wire	[4:0]	REG_IDX1;
wire	[31:0]	REG_DATA2;
wire	[4:0]	REG_IDX2;
wire	[31:0]	REG_WDATA;
wire	[4:0]	REG_WIDX;
wire		REG_WEN;
wire	[12:0]	RAM_ADDR;
wire	[31:0]	RAM_RDATA;
wire	[31:0]	RAM_WDATA;
wire		RAM_WEN;
wire	[12:0]	toRAM_ADDR;
wire	[31:0]	toRAM_WDATA;
wire		toRAM_WEN;

wire		cpu_clk;

reg cpu_clk_reg;
reg key1_reg;
reg sw0_reg;
reg sw1_reg;

reg  [31:0]	Cont;
reg [35:0] gpio_reg;








assign LCD_DATA = LCD_D_1;
assign LCD_RW   = LCD_RW_1;
assign LCD_EN   = LCD_EN_1;
assign LCD_RS   = LCD_RS_1; 
assign LCD_ON   = 1'b1;
assign LCD_BLON = 1'b0;

assign DRAM_DQ 			= 32'hzzzzzzzz;
 
assign AUD_ADCLRCK    	= 1'bz;     					
assign AUD_DACLRCK 		= 1'bz;     					
assign AUD_DACDAT 		= 1'bz;     					
assign AUD_BCLK 		   = 1'bz;     						
assign AUD_XCK 		   = 1'bz;     						
   						
assign I2C_SDAT 		   = 1'bz;     						
assign I2C_SCLK		   = 1'bz;
assign EEP_I2C_SDAT 		= 1'bz;     						
assign EEP_I2C_SCLK		= 1'bz;      						
assign SD_DAT 				= 4'bz;     							    						
assign SD_CMD 				= 1'bz;     						
assign SD_CLK 				= 1'bz;     						
assign OTG_DATA   		= 16'hzzzz;	

assign FL_DQ        		= 8'hzz;				


assign	SD_DAT		=	4'bz;
assign	GPIO   		=	36'hzzzzzzzz;


assign	OTG_FSPEED	=	1'bz;
assign	OTG_LSPEED	=	1'bz;


assign	DRAM_DQ		=	32'hzzzzzzzz;
assign	SRAM_DQ		=	16'hzzzz;
assign	SD_DAT		=	4'bz;


always@(posedge CLOCK_50 or negedge KEY[2])
    begin
        if(!KEY[2])
			 Cont	<=	0;
        else
			 Cont	<=	Cont+1;
    end

assign	TD_RESET_N	=	1'b1;
assign	AUD_ADCLRCK	=	AUD_DACLRCK;
assign	AUD_XCK	    =	AUD_CTRL_CLK;
assign	mSEG7_DIG	=	{	key_ascii_D[7:4], key_ascii_D[3:0],
					key_data_D[7:4], key_data_D[3:0], 8'b0000, PC};
assign	LEDR			=	{	Cont[26:24],Cont[26:24],Cont[26:24],
							Cont[26:24],Cont[26:24],Cont[26:24]	};
assign	LEDG			=	{	Cont[26:24],Cont[26:24],Cont[26:24]	};

assign	ROW_Cursor	=	(PUT_ROW+1)*16+1;
assign	COL_Cursor	=	PUT_COL*16;


Reset_Delay			r0	(	.iCLK(CLOCK_50),.oRESET(DLY_RST)	);

VGA_Audio_PLL 		p1	(	.areset(~DLY_RST),.inclk0(CLOCK2_50),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(mVGA_CLK)	);


SEG7_LUT_8 			u0	(	.oSEG0(HEX0),
							.oSEG1(HEX1),
							.oSEG2(HEX2),
							.oSEG3(HEX3),
							.oSEG4(HEX4),
							.oSEG5(HEX5),
							.oSEG6(HEX6),
							.oSEG7(HEX7),
							.iDIG(mSEG7_DIG) );




assign VGA_CLK = VGA_CTRL_CLK;

VGA_Controller		u1	(

							.iCursor_RGB_EN(4'hf),
							.iCursor_X(COL_Cursor),
							.iCursor_Y(ROW_Cursor),
							.iCursor_R(512),
							.iCursor_G(0),
							.iCursor_B(0),
							.oAddress(mVGA_ADDR),
							.oCoord_X(mVGA_CoordX),
							.oCoord_Y(mVGA_CoordY),
							.oWen(mVGA_WEN),
							.iRed(mVGA_R),
							.iGreen(mVGA_G),
							.iBlue(mVGA_B),

							.oVGA_R(VGA_R),
							.oVGA_G(VGA_G),
							.oVGA_B(VGA_B),
							.oVGA_H_SYNC(VGA_HS),
							.oVGA_V_SYNC(VGA_VS),
							.oVGA_SYNC(VGA_SYNC_N),
							.oVGA_BLANK(VGA_BLANK_N),

							.iCLK(VGA_CTRL_CLK),
							.iRST_N(DLY_RST)	);							 
							 
VGA_OSD_RAM			u2	(
							.oRed(mVGA_R),
							.oGreen(mVGA_G),
							.oBlue(mVGA_B),
							.iVGA_ADDR(mVGA_ADDR),
							.iVGA_CLK(VGA_CLK),

							.iWR_DATA(pixel_val),
							.iWR_ADDR(mVGA_ADDR),
							.iWR_EN(mVGA_WEN),
							.iWR_CLK(VGA_CLK),

							.iON_R(1023),
							.iON_G(1023),
							.iON_B(1023),
							.iOFF_R(0),
							.iOFF_G(0),
							.iOFF_B(512),

							.iRST_N(DLY_RST)	);
							

I2C_AV_Config 		u3	(
							.iCLK(CLOCK_50),
							.iRST_N(KEY[2]),

							.I2C_SCLK(I2C_SCLK),
							.I2C_SDAT(I2C_SDAT)	);

AUDIO_DAC 			u4	(
							.oAUD_BCK(AUD_BCLK),
							.oAUD_DATA(AUD_DACDAT),
							.oAUD_LRCK(AUD_DACLRCK),

							.iSrc_Select(SW[17]),
				         .iCLK_18_4(AUD_CTRL_CLK),
							.iRST_N(DLY_RST)	);


LCD_TEST 			u5	(
							.iCLK(CLOCK_50),
							.iRST_N(DLY_RST),

							.LCD_DATA(LCD_D_1),
							.LCD_RW(LCD_RW_1),
							.LCD_EN(LCD_EN_1),
							.LCD_RS(LCD_RS_1)	);




KEYBOARD_DEC u6 (
	.iClock          (CLOCK_50),
	.iReset_N        (KEY[2]),

	.iKeyboard_DATA  (PS2_DAT),
	.iKeyboard_CLOCK (PS2_CLK),

	.oKey_data_D     (key_data_D),
	.oKey_parity_D   (key_parity_D),
	.oKey_stopbit_D  (key_stopbit_D),
	.oKey_ascii_D    (key_ascii_D),
	.oKey_stroke     (key_stroke)
);

VGA_CHAR_RAM u7 (
	.oPIXEL_VAL  (pixel_val),
	.iVGA_ADDR   (mVGA_ADDR),
	.iVGA_CoordX (mVGA_CoordX),
	.iVGA_CoordY (mVGA_CoordY),
	.iVGA_CLK    (VGA_CLK),

	.iWR_DATA(PUT_DATA),

	.iWR_PUT_ROW (PUT_ROW),
	.iWR_PUT_COL (PUT_COL),
	.iWR_EN      (PUT_EN),
	.iWR_CLK     (VGA_CTRL_CLK),

	.iRST_N      (DLY_RST)
);


wire[9:0] romMonitorAddr;
wire[31:0] romMonitorRdat;
update_monitor_rom  update_rom(.addr(romMonitorAddr), .data(romMonitorRdat));

VGA_CHAR_Ctrl u8 (
	.ikey_ascii_D    (key_ascii_D),
	.ikey_stroke     (key_stroke),
	.imVGA_WEN       (mVGA_WEN),
	.iVGA_CLK        (VGA_CLK),
	.iCLOCK          (CLOCK_50),
	.iPC             (PC),
	.iALU_Y          (ALU_Y),
	.iALU_A          (ALU_A),
	.iALU_B          (ALU_B),
	.iALU_CTRL       (ALU_CTRL),
	.iALU_COMP       (ALU_COMP),
	.iREG_DATA1      (REG_DATA1),
	.iREG_IDX1       (REG_IDX1),
	.iREG_DATA2      (REG_DATA2),
	.iREG_IDX2       (REG_IDX2),
	.iREG_WDATA      (REG_WDATA),
	.iREG_WIDX       (REG_WIDX),
	.iREG_WEN        (REG_WEN),
	.iRAM_ADDR       (RAM_ADDR),
	.iRAM_RDATA      (RAM_RDATA),
	.iRAM_WDATA      (RAM_WDATA),
	.iRAM_WEN        (RAM_WEN),
	.oCurrentPosRow  (PUT_ROW),
	.oCurrentPosCol  (PUT_COL),
	.oPUT_EN         (PUT_EN),
	.oPUT_DATA       (PUT_DATA),
	.oRAM_ADDR       (toRAM_ADDR),
	.oRAM_WDATA      (toRAM_WDATA),
	.oRAM_WEN        (toRAM_WEN),
	.oROMmonitorADDR (romMonitorAddr),
	.iROMmonitorRDAT (romMonitorRdat),

	.iRST_N          (KEY[2])
);


always @(posedge CLOCK_50 or negedge KEY[2]) begin
	if (KEY[2] == 1'b0) begin
		gpio_reg <= 0;
	end else begin
		if ((RAM_ADDR == `GPIO0_ADDR) && (RAM_WEN == 1'b1)) begin
			gpio_reg <= RAM_WDATA;
		end
	end
end
                                                                                
assign GPIO = gpio_reg;

always @(posedge CLOCK_50 or negedge KEY[2]) begin
	if (KEY[2] == 1'b0) begin
		cpu_clk_reg <= 1'b0;
		key1_reg    <= 1'b0;
		sw0_reg     <= 1'b0;
		sw1_reg     <= 1'b0;
	end else begin
		if (key1_reg != KEY[3]) begin
			key1_reg <= KEY[3];
		end

		if (sw0_reg != SW[0]) begin
			sw0_reg <= SW[0];
		end

		if (sw1_reg != SW[1]) begin
			sw1_reg <= SW[1];
		end
	end
end

assign cpu_clk = CLOCK_50;

cpu u9(
	.clk          (cpu_clk),
	.reset        (KEY[2]),
	.clk_ctrl0    (sw0_reg),
	.clk_ctrl1    (sw1_reg),
	.clk_ctrl_clk (key1_reg),
	.o_clock      (CLOCK_CPU),
	.o_pc         (PC),
	.o_alu_y      (ALU_Y),
	.o_alu_a      (ALU_A),
	.o_alu_b      (ALU_B),
	.o_alu_ctrl   (ALU_CTRL),
	.o_alu_comp   (ALU_COMP),
	.o_reg_data1  (REG_DATA1),
	.o_reg_idx1   (REG_IDX1),
	.o_reg_data2  (REG_DATA2),
	.o_reg_idx2   (REG_IDX2),
	.o_reg_wdata  (REG_WDATA),
	.o_reg_widx   (REG_WIDX),
	.o_reg_wen    (REG_WEN),
	.o_ram_addr   (RAM_ADDR),
	.o_ram_rdata  (RAM_RDATA),
	.o_ram_wdata  (RAM_WDATA),
	.o_ram_wen    (RAM_WEN),
	.i_ram_addr   (toRAM_ADDR),
	.i_ram_wdata  (toRAM_WDATA),
	.i_ram_wen    (toRAM_WEN),
);

endmodule