data/full_repos/permissive/143278/ivltests/pr1628288.v
 line:18: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1628288.v:9: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk = ~clk;   \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr1628288.v:16: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1628288.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #0 read_bad(data);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1628288.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #20;   \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1628288.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #1 $finish(0);\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1628288.v:36: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1628288.v:55: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg clk;
  reg dout;
  reg [7:0] data;
  integer lp;

  always #10 clk = ~clk;

  always @(negedge clk) dout = ~dout;

  initial begin
    clk = 0;
    dout = 0;
    @(negedge clk);
    for (lp=0; lp<4; lp=lp+1) begin
      #0 read_bad(data);
      $display("Read(%0d) %b from the bit stream.", lp, data);
      #20;
    end

    #1 $finish(0);
  end


  task read_bad;
    output [7:0] edata;

    integer i;

    reg [7:0] rddata;

    begin
      for(i=7; i>=0; i=i-1) begin
        @(posedge clk);
        $display("  Reading bit %0d", i);
        rddata[i] = dout;
      end

      assign edata = rddata;
    end
  endtask


  task read_good;
    output [7:0] edata;

   integer i;

    reg [7:0] edata;

    begin
      for(i=7; i>=0; i=i-1) begin
        @(posedge clk);
        $display("  Reading bit %0d", i);
        edata[i] = dout;
      end
    end
  endtask
endmodule
module top;

  reg clk;
  reg dout;
  reg [7:0] data;
  integer lp;

  always #10 clk = ~clk;

  always @(negedge clk) dout = ~dout;

  initial begin
    clk = 0;
    dout = 0;
    @(negedge clk);
    for (lp=0; lp<4; lp=lp+1) begin
      #0 read_bad(data);
      $display("Read(%0d) %b from the bit stream.", lp, data);
      #20;
    end

    #1 $finish(0);
  end


  task read_bad;
    output [7:0] edata;

    integer i;

    reg [7:0] rddata;

    begin
      for(i=7; i>=0; i=i-1) begin
        @(posedge clk);
        $display("  Reading bit %0d", i);
        rddata[i] = dout;
      end

      assign edata = rddata;
    end
  endtask


  task read_good;
    output [7:0] edata;

   integer i;

    reg [7:0] edata;

    begin
      for(i=7; i>=0; i=i-1) begin
        @(posedge clk);
        $display("  Reading bit %0d", i);
        edata[i] = dout;
      end
    end
  endtask
endmodule