data/full_repos/permissive/161048197/project_1.srcs/sim_1/imports/new/test.v
 line:43: before: "]"
1: b'%Error: data/full_repos/permissive/161048197/project_1.srcs/sim_1/imports/new/test.v:43: Define or directive not defined: \'`ALU_OP_BUS\'\n    wire [`ALU_OP_BUS]  alu_op;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sim_1/imports/new/test.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`ALU_OP_BUS]  alu_op;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/161048197/project_1.srcs/sim_1/imports/new/test.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/161048197/project_1.srcs/sim_1/imports/new/test.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #25\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/161048197/project_1.srcs/sim_1/imports/new/test.v:85: Unsupported: Ignoring delay on this delayed statement.\n        forever #50 \n                ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module test;
    

    reg clk;
    reg rst_n;
    

    wire [31:0] inst;
    wire [31:0] pc;
    wire [31:0] next_pc;
    wire [31:0] alu_res;
    wire [31:0] write_data;
    wire [4:0] write_addr;
    wire write_en;
    wire [4:0] rs_addr;
    wire [31:0] rs_data;
    wire [4:0] rt_addr;
    wire [31:0] rt_data;
    wire [31:0] imm;
    wire [31:0] br_tgt;
    wire [31:0] mem_read;
    wire [`ALU_OP_BUS]  alu_op;
    wire zero;
    wire b_ctrl, jump, branch;
    wire take_branch;
    wire [1:0] fetch_rw;
    wire halt;
    
    main main(
        .clk(clk),
        .rst_n(rst_n),
        .inst(inst),
        .pc(pc),
        .next_pc(next_pc),
        .alu_res(alu_res),
        .reg_write_data(write_data),
        .reg_write_addr(write_addr),
        .reg_write_en(write_en),
        .rs_addr(rs_addr),
        .rs_data(rs_data),
        .rt_addr(rt_addr),
        .rt_data(rt_data),
        .imm(imm),
        .branch_target(br_tgt),
        .mem_read(mem_read),
        .alu_op(alu_op),
        .zero(zero),
        .b_ctrl(b_ctrl),
        .jump(jump),
        .branch(branch),
        .take_branch(take_branch),
        .pc_src(fetch_rw),
        .halt(halt));
        
    initial 
    begin

        clk = 0;
        rst_n = 0;
        #25;
            rst_n = 1;
        #25
        clk = !clk;
        forever #50 
        begin
            clk = !clk;
        end
    end
        
endmodule
module test;

    

    reg clk;
    reg rst_n;
    

    wire [31:0] inst;
    wire [31:0] pc;
    wire [31:0] next_pc;
    wire [31:0] alu_res;
    wire [31:0] write_data;
    wire [4:0] write_addr;
    wire write_en;
    wire [4:0] rs_addr;
    wire [31:0] rs_data;
    wire [4:0] rt_addr;
    wire [31:0] rt_data;
    wire [31:0] imm;
    wire [31:0] br_tgt;
    wire [31:0] mem_read;
    wire [`ALU_OP_BUS]  alu_op;
    wire zero;
    wire b_ctrl, jump, branch;
    wire take_branch;
    wire [1:0] fetch_rw;
    wire halt;
    
    main main(
        .clk(clk),
        .rst_n(rst_n),
        .inst(inst),
        .pc(pc),
        .next_pc(next_pc),
        .alu_res(alu_res),
        .reg_write_data(write_data),
        .reg_write_addr(write_addr),
        .reg_write_en(write_en),
        .rs_addr(rs_addr),
        .rs_data(rs_data),
        .rt_addr(rt_addr),
        .rt_data(rt_data),
        .imm(imm),
        .branch_target(br_tgt),
        .mem_read(mem_read),
        .alu_op(alu_op),
        .zero(zero),
        .b_ctrl(b_ctrl),
        .jump(jump),
        .branch(branch),
        .take_branch(take_branch),
        .pc_src(fetch_rw),
        .halt(halt));
        
    initial 
    begin

        clk = 0;
        rst_n = 0;
        #25;
            rst_n = 1;
        #25
        clk = !clk;
        forever #50 
        begin
            clk = !clk;
        end
    end
        
endmodule