data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v
 line:1: before: "["
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:7: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:25: Unsupported: Ignoring delay on this delayed statement.\n       #1 A[103:8] = {$random, $random, $random};\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:32: Unsupported: Ignoring delay on this delayed statement.\n       #1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #120000;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:26: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                     : ... In instance test.stim\n          A[7:0] = $random % 256;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:28: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                     : ... In instance test.stim\n          B[7:0] = $random % 256;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:34: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                     : ... In instance test.stim\n       A[7:0] = $random % 256;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:36: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                     : ... In instance test.stim\n       B[7:0] = $random % 256;\n              ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_xnor104_stdlogic.v:73: Cannot find file containing module: \'xnor104\'\n  xnor104      duv            (.a_i(a), .b_i(b), .c_o(r) );\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/xnor104\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/xnor104.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/xnor104.sv\n             xnor104\n             xnor104.v\n             xnor104.sv\n             obj_dir/xnor104\n             obj_dir/xnor104.v\n             obj_dir/xnor104.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  wire unsigned [103:0] a, b;
  wire unsigned [103:0] r;

  stimulus     stim           (.A(a), .B(b));
  xnor104      duv            (.a_i(a), .b_i(b), .c_o(r) );
  check        check          (.a(a), .b(b), .c(r) );

  initial begin
    #120000;
    $display("PASSED");
    $finish;
  end

endmodule
module test;

  wire unsigned [103:0] a, b;
  wire unsigned [103:0] r;

  stimulus     stim           (.A(a), .B(b));
  xnor104      duv            (.a_i(a), .b_i(b), .c_o(r) );
  check        check          (.a(a), .b(b), .c(r) );

  initial begin
    #120000;
    $display("PASSED");
    $finish;
  end

endmodule