data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v
 line:69: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #5                                                          \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #5                                                          \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #1 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:72: Unsupported: Ignoring delay on this delayed statement.\n    always #2.5 i_clk = ~i_clk;      \n           ^\n%Error: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_program_mem.v:74: Cannot find file containing module: \'program_mem\'\n    program_mem #(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/program_mem\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/program_mem.v\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/program_mem.sv\n             program_mem\n             program_mem.v\n             program_mem.sv\n             obj_dir/program_mem\n             obj_dir/program_mem.v\n             obj_dir/program_mem.sv\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_program_mem();
    parameter   RAM_WIDTH = 16;
    parameter   RAM_DEPTH = 2048;
    parameter   RAM_PERFORMANCE = "LOW_LATENCY";
    parameter   INIT_FILE = "/home/martin/git/Arquitectura_de_Computadoras_2019/TP3-BIP1-2019/Test/init_ram_program.mem";
    


    

    reg [16-1:0]            i_addr;
    reg                     i_clk;

    wire [RAM_WIDTH-1:0]    o_data;
    
    initial begin
        i_clk   = 1'b0;
                                     
        i_addr  = 16'h0000;
        #5
        i_addr  = 16'h0001;
        #5                                                          
        i_addr  = 16'h0002;
        #5                                                          
        i_addr  = 16'h0003;
        #5
        i_addr  = 16'h0004;
        #5
        i_addr  = 16'h0005;
        #5
        i_addr  = 16'h0006;
        #5
        i_addr  = 16'h0007;
        #5
        i_addr  = 16'h0008;
        #5
        i_addr  = 16'h0009;
        #5
        i_addr  = 16'h000A;
        #5
        i_addr  = 16'h000B;
        #5
        i_addr  = 16'h000C;
        #5
        i_addr  = 16'h000D;
        
        #1 $finish;
    end
    
    always #2.5 i_clk = ~i_clk;
    
    program_mem #(
        .RAM_WIDTH          (RAM_WIDTH),
        .RAM_DEPTH          (RAM_DEPTH),
        .RAM_PERFORMANCE    (RAM_PERFORMANCE),
        .INIT_FILE          (INIT_FILE)
    )
    u_program_mem
    (
        .i_addr     (i_addr),
        .i_clk      (i_clk),
        .o_data     (o_data)
    );
    
endmodule
module tb_program_mem();

    parameter   RAM_WIDTH = 16;
    parameter   RAM_DEPTH = 2048;
    parameter   RAM_PERFORMANCE = "LOW_LATENCY";
    parameter   INIT_FILE = "/home/martin/git/Arquitectura_de_Computadoras_2019/TP3-BIP1-2019/Test/init_ram_program.mem";
    


    

    reg [16-1:0]            i_addr;
    reg                     i_clk;

    wire [RAM_WIDTH-1:0]    o_data;
    
    initial begin
        i_clk   = 1'b0;
                                     
        i_addr  = 16'h0000;
        #5
        i_addr  = 16'h0001;
        #5                                                          
        i_addr  = 16'h0002;
        #5                                                          
        i_addr  = 16'h0003;
        #5
        i_addr  = 16'h0004;
        #5
        i_addr  = 16'h0005;
        #5
        i_addr  = 16'h0006;
        #5
        i_addr  = 16'h0007;
        #5
        i_addr  = 16'h0008;
        #5
        i_addr  = 16'h0009;
        #5
        i_addr  = 16'h000A;
        #5
        i_addr  = 16'h000B;
        #5
        i_addr  = 16'h000C;
        #5
        i_addr  = 16'h000D;
        
        #1 $finish;
    end
    
    always #2.5 i_clk = ~i_clk;
    
    program_mem #(
        .RAM_WIDTH          (RAM_WIDTH),
        .RAM_DEPTH          (RAM_DEPTH),
        .RAM_PERFORMANCE    (RAM_PERFORMANCE),
        .INIT_FILE          (INIT_FILE)
    )
    u_program_mem
    (
        .i_addr     (i_addr),
        .i_clk      (i_clk),
        .o_data     (o_data)
    );
    
endmodule