data/full_repos/permissive/143278/ivltests/sv_unit1b.v
 line:15: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/sv_unit1b.v:15: Unsupported: Ignoring delay on this delayed statement.\ninitial #2 begin\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/sv_unit1b.v:13: Can\'t find definition of variable: \'b\'\nbuf(a,b);\n      ^\n%Warning-IMPLICIT: data/full_repos/permissive/143278/ivltests/sv_unit1b.v:13: Signal definition not found, creating implicitly: \'a\'\nbuf(a,b);\n    ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test2(input w);

buf(a,b);

initial #2 begin
  $display("test2 macro1 = %0d", `MACRO1 );
  $display("test2 macro2 = %0d", `MACRO2 );
  $display("test2 macro3 = %0d", `MACRO3 );
  $display("test2 wire = %b", a);
end

endmodule
module test2(input w);


buf(a,b);

initial #2 begin
  $display("test2 macro1 = %0d", `MACRO1 );
  $display("test2 macro2 = %0d", `MACRO2 );
  $display("test2 macro3 = %0d", `MACRO3 );
  $display("test2 wire = %b", a);
end

endmodule