data/full_repos/permissive/160156109/mips-work/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160156109/mips-work/alu.v:16: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 48 bits.\n                                                                       : ... In instance alu\n        4\'b1010 : dout = {busB, 16\'h0};\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module alu(ALUctr, busA, busB, zero, dout);
  input [3:0] ALUctr;
  input [31:0] busA, busB;
  output zero;
  output reg [31:0] dout;

  assign zero = dout == 0 ? 1 : 0;

  always @(ALUctr, busA, busB)
  begin
    case(ALUctr)
        4'b0010 : dout = busA + busB;
        4'b0110 : dout = busA - busB;
        4'b0001 : dout = busA | busB;
        4'b0111 : dout = busA & busB;
        4'b1010 : dout = {busB, 16'h0};
    endcase
  end
endmodule
module alu(ALUctr, busA, busB, zero, dout);

  input [3:0] ALUctr;
  input [31:0] busA, busB;
  output zero;
  output reg [31:0] dout;

  assign zero = dout == 0 ? 1 : 0;

  always @(ALUctr, busA, busB)
  begin
    case(ALUctr)
        4'b0010 : dout = busA + busB;
        4'b0110 : dout = busA - busB;
        4'b0001 : dout = busA | busB;
        4'b0111 : dout = busA & busB;
        4'b1010 : dout = {busB, 16'h0};
    endcase
  end
endmodule