data/full_repos/permissive/139881681/mixer/synthesis/submodules/status_hex.v
data/verilator_xmls/642593b9-f3ca-4516-8eb4-2f7cc51e5a52.xml
module status_hex(output reg[6:0] hex, input lsource_ready, input rsource_ready, input lsink_valid, input rsink_valid);
	always @*
	begin
		hex = {1'b1, lsink_valid, lsource_ready, 1'b1, rsource_ready, rsink_valid, 1'b1};
	end
endmodule
module status_hex(output reg[6:0] hex, input lsource_ready, input rsource_ready, input lsink_valid, input rsink_valid);

	always @*
	begin
		hex = {1'b1, lsink_valid, lsource_ready, 1'b1, rsource_ready, rsink_valid, 1'b1};
	end
endmodule