data/full_repos/permissive/129155059/proyecto-01/byte_striping/bytejoining_cond.v
data/verilator_xmls/bd7bd336-09ed-4847-a750-66eb28024def.xml
module mux4a1 (
  input [7:0] In0, In1, In2, In3,
  input [1:0] Sel,
  output reg [7:0] outmux
  );
  always @ ( Sel ) begin
    case (Sel)
      2'b00: outmux = In0;
      2'b01: outmux = In1;
      2'b10: outmux = In2;
      2'b11: outmux = In3;
    endcase
  end

endmodule
module mux4a1 (
  input [7:0] In0, In1, In2, In3,
  input [1:0] Sel,
  output reg [7:0] outmux
  );

  always @ ( Sel ) begin
    case (Sel)
      2'b00: outmux = In0;
      2'b01: outmux = In1;
      2'b10: outmux = In2;
      2'b11: outmux = In3;
    endcase
  end

endmodule