data/full_repos/permissive/135475029/lab_9/src/MIPS_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/135475029/lab_9/src/MIPS_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n     clk=1; #50;       \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135475029/lab_9/src/MIPS_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n    clk=0; #50;       \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/135475029/lab_9/src/MIPS_test.v:53: Unsupported: Ignoring delay on this delayed statement.\n     #60;          \n     ^\n%Warning-STMTDLY: data/full_repos/permissive/135475029/lab_9/src/MIPS_test.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #1100;        \n    ^\n%Error: data/full_repos/permissive/135475029/lab_9/src/MIPS_test.v:60: Cannot find file containing module: \'MIPS\'\n MIPS uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/135475029/lab_9/src,data/full_repos/permissive/135475029/MIPS\n             data/full_repos/permissive/135475029/lab_9/src,data/full_repos/permissive/135475029/MIPS.v\n             data/full_repos/permissive/135475029/lab_9/src,data/full_repos/permissive/135475029/MIPS.sv\n             MIPS\n             MIPS.v\n             MIPS.sv\n             obj_dir/MIPS\n             obj_dir/MIPS.v\n             obj_dir/MIPS.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MIPS_test;










	wire [31:0] result;
	wire [31:0] PC;

	reg         clk   ;
	reg         reset ;



	always
	  begin
	    clk=1; #50;
		  clk=0; #50;
	  end


	initial
	  begin
     reset = 1;
     #60;
     reset= 0;
	   #1100;
	   $stop;
	  end


 MIPS uut (
    .CLK(clk),
    .RESET(reset),
    .DATA(result),
    .ADDRESS(PC)
    );

endmodule
module MIPS_test;











	wire [31:0] result;
	wire [31:0] PC;

	reg         clk   ;
	reg         reset ;



	always
	  begin
	    clk=1; #50;
		  clk=0; #50;
	  end


	initial
	  begin
     reset = 1;
     #60;
     reset= 0;
	   #1100;
	   $stop;
	  end


 MIPS uut (
    .CLK(clk),
    .RESET(reset),
    .DATA(result),
    .ADDRESS(PC)
    );

endmodule