data/full_repos/permissive/174323821/hdl/sdram/jtframe_sdram_bank_core.v
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-WIDTH: data/full_repos/permissive/174323821/hdl/sdram/jtframe_sdram_bank_core.v:173: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                            : ... In instance jtframe_sdram_bank_core\n    activate = ( (!all_st[READ_ST] && rd ) || (!all_st[STW-2:(HF?2:1)] && wr)) && !rfshing;\n                                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/174323821/hdl/sdram/jtframe_sdram_bank_core.v:187: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 6 bits.\n                                                                                            : ... In instance jtframe_sdram_bank_core\n    refresh  = !all_st[STW-1:1] && rfsh_en && !rd && !wr && !rfshing;\n               ^\n%Error: Exiting due to 2 warning(s)\n'
function [STW-1:0] next;
    input [STW-1:0] cur;
    input [1:0] ba;



    next =    ((activate && ba_rq==ba)
           || (read && ba_fifo[HF?0:1]==ba)
           || (!cur[0] && !cur[READ_ST]) )
           || rfshing ?
                        { cur[STW-2:0], cur[STW-1] } :
                        cur;
endfunction
function [STW-1:0] next;

    input [STW-1:0] cur;
    input [1:0] ba;



    next =    ((activate && ba_rq==ba)
           || (read && ba_fifo[HF?0:1]==ba)
           || (!cur[0] && !cur[READ_ST]) )
           || rfshing ?
                        { cur[STW-2:0], cur[STW-1] } :
                        cur;
endfunction