data/full_repos/permissive/114380772/Snake/Apple_generate_module.v
1: b'%Warning-CMPCONST: data/full_repos/permissive/114380772/Snake/Apple_generate_module.v:40: Comparison is constant due to limited range\n                                                                                        : ... In instance Apple_generate_module\n      Apple_1[7:4] <= (Random_num_1[7:4] > 4\'d15)?(Random_num_1[7:4] - 4\'d15):((Random_num_1[7:4] == 4\'d0)?4\'d1:Random_num_1[7:4]);\n                                         ^\n                   ... Use "/* verilator lint_off CMPCONST */" and lint_on around source to disable this message.\n%Warning-CMPCONST: data/full_repos/permissive/114380772/Snake/Apple_generate_module.v:41: Comparison is constant due to limited range\n                                                                                        : ... In instance Apple_generate_module\n      Apple_1[3:0] <= (Random_num_1[3:0] > 4\'d15)?(Random_num_1[3:0] - 4\'d15):((Random_num_1[3:0] == 4\'d0)?4\'d1:Random_num_1[3:0]);\n                                         ^\n%Warning-CMPCONST: data/full_repos/permissive/114380772/Snake/Apple_generate_module.v:42: Comparison is constant due to limited range\n                                                                                        : ... In instance Apple_generate_module\n      Apple_2[7:4] <= (Random_num_2[7:4] > 4\'d15)?(Random_num_2[7:4] - 4\'d15):((Random_num_2[7:4] == 4\'d0)?4\'d1:Random_num_2[7:4]);\n                                         ^\n%Warning-CMPCONST: data/full_repos/permissive/114380772/Snake/Apple_generate_module.v:43: Comparison is constant due to limited range\n                                                                                        : ... In instance Apple_generate_module\n      Apple_2[3:0] <= (Random_num_2[3:0] > 4\'d15)?(Random_num_2[3:0] - 4\'d15):((Random_num_2[3:0] == 4\'d0)?4\'d1:Random_num_2[3:0]);\n                                         ^\n%Warning-CMPCONST: data/full_repos/permissive/114380772/Snake/Apple_generate_module.v:44: Comparison is constant due to limited range\n                                                                                        : ... In instance Apple_generate_module\n      Apple_3[7:4] <= (Random_num_3[7:4] > 4\'d15)?(Random_num_3[7:4] - 4\'d15):((Random_num_3[7:4] == 4\'d0)?4\'d1:Random_num_3[7:4]);\n                                         ^\n%Warning-CMPCONST: data/full_repos/permissive/114380772/Snake/Apple_generate_module.v:45: Comparison is constant due to limited range\n                                                                                        : ... In instance Apple_generate_module\n      Apple_3[3:0] <= (Random_num_3[3:0] > 4\'d15)?(Random_num_3[3:0] - 4\'d15):((Random_num_3[3:0] == 4\'d0)?4\'d1:Random_num_3[3:0]);\n                                         ^\n%Error: Exiting due to 6 warning(s)\n'
module Apple_generate_module
(
	input Clk_24mhz,
	input Rst_n,
	input [7:0] Head,
	output reg [7:0] Apple_1,
	output reg [7:0] Apple_2,
	output reg [7:0] Apple_3,
	output reg Body_add_sig
);

	reg [31:0] Count1;
	reg [7:0] Random_num_1;
	reg [7:0] Random_num_2;
	reg [7:0] Random_num_3;
	
	always@(posedge Clk_24mhz)
	begin	
		Random_num_1 <= Random_num_1 + 8'd126;
		Random_num_2 <= Random_num_2 + 8'd65;
		Random_num_3 <= Random_num_3 + 8'd89;
	end
	
	always@(posedge Clk_24mhz or negedge Rst_n)
	begin
		if(!Rst_n)
		begin
			Count1 <= 32'd0;
			Apple_1 <= {4'd5,4'd8};
			Apple_2 <= {4'd6,4'd10};
			Apple_3 <= {4'd10,4'd8};
			Body_add_sig <= 1'd0;
		end
		else
				begin
					Count1 <= 32'd0;
					if(Apple_1 == Head | Apple_2 == Head | Apple_3 == Head)
					begin
						Body_add_sig <= 1'd1;
						Apple_1[7:4] <= (Random_num_1[7:4] > 4'd15)?(Random_num_1[7:4] - 4'd15):((Random_num_1[7:4] == 4'd0)?4'd1:Random_num_1[7:4]);
						Apple_1[3:0] <= (Random_num_1[3:0] > 4'd15)?(Random_num_1[3:0] - 4'd15):((Random_num_1[3:0] == 4'd0)?4'd1:Random_num_1[3:0]);
						Apple_2[7:4] <= (Random_num_2[7:4] > 4'd15)?(Random_num_2[7:4] - 4'd15):((Random_num_2[7:4] == 4'd0)?4'd1:Random_num_2[7:4]);
						Apple_2[3:0] <= (Random_num_2[3:0] > 4'd15)?(Random_num_2[3:0] - 4'd15):((Random_num_2[3:0] == 4'd0)?4'd1:Random_num_2[3:0]);
						Apple_3[7:4] <= (Random_num_3[7:4] > 4'd15)?(Random_num_3[7:4] - 4'd15):((Random_num_3[7:4] == 4'd0)?4'd1:Random_num_3[7:4]);
						Apple_3[3:0] <= (Random_num_3[3:0] > 4'd15)?(Random_num_3[3:0] - 4'd15):((Random_num_3[3:0] == 4'd0)?4'd1:Random_num_3[3:0]);
					end   
					else
						Body_add_sig <= 1'd0;
				end


	end
endmodule
module Apple_generate_module
(
	input Clk_24mhz,
	input Rst_n,
	input [7:0] Head,
	output reg [7:0] Apple_1,
	output reg [7:0] Apple_2,
	output reg [7:0] Apple_3,
	output reg Body_add_sig
);


	reg [31:0] Count1;
	reg [7:0] Random_num_1;
	reg [7:0] Random_num_2;
	reg [7:0] Random_num_3;
	
	always@(posedge Clk_24mhz)
	begin	
		Random_num_1 <= Random_num_1 + 8'd126;
		Random_num_2 <= Random_num_2 + 8'd65;
		Random_num_3 <= Random_num_3 + 8'd89;
	end
	
	always@(posedge Clk_24mhz or negedge Rst_n)
	begin
		if(!Rst_n)
		begin
			Count1 <= 32'd0;
			Apple_1 <= {4'd5,4'd8};
			Apple_2 <= {4'd6,4'd10};
			Apple_3 <= {4'd10,4'd8};
			Body_add_sig <= 1'd0;
		end
		else
				begin
					Count1 <= 32'd0;
					if(Apple_1 == Head | Apple_2 == Head | Apple_3 == Head)
					begin
						Body_add_sig <= 1'd1;
						Apple_1[7:4] <= (Random_num_1[7:4] > 4'd15)?(Random_num_1[7:4] - 4'd15):((Random_num_1[7:4] == 4'd0)?4'd1:Random_num_1[7:4]);
						Apple_1[3:0] <= (Random_num_1[3:0] > 4'd15)?(Random_num_1[3:0] - 4'd15):((Random_num_1[3:0] == 4'd0)?4'd1:Random_num_1[3:0]);
						Apple_2[7:4] <= (Random_num_2[7:4] > 4'd15)?(Random_num_2[7:4] - 4'd15):((Random_num_2[7:4] == 4'd0)?4'd1:Random_num_2[7:4]);
						Apple_2[3:0] <= (Random_num_2[3:0] > 4'd15)?(Random_num_2[3:0] - 4'd15):((Random_num_2[3:0] == 4'd0)?4'd1:Random_num_2[3:0]);
						Apple_3[7:4] <= (Random_num_3[7:4] > 4'd15)?(Random_num_3[7:4] - 4'd15):((Random_num_3[7:4] == 4'd0)?4'd1:Random_num_3[7:4]);
						Apple_3[3:0] <= (Random_num_3[3:0] > 4'd15)?(Random_num_3[3:0] - 4'd15):((Random_num_3[3:0] == 4'd0)?4'd1:Random_num_3[3:0]);
					end   
					else
						Body_add_sig <= 1'd0;
				end


	end
endmodule