data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/mult_32x32.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/mult_32x32.v:12: Little bit endian vector: MSB < LSB of bit range: 0:31\n input [0:31] a,\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/mult_32x32.v:13: Little bit endian vector: MSB < LSB of bit range: 0:31\n input [0:31] b,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/mult_32x32.v:14: Little bit endian vector: MSB < LSB of bit range: 0:63\n output [0:63] out,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/mult_32x32.v:15: Little bit endian vector: MSB < LSB of bit range: 0:1\n    input [0:1] mode);\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/mult_32x32.v:17: Little bit endian vector: MSB < LSB of bit range: 0:63\n    reg [0:63] out_reg;\n        ^\n%Error: Exiting due to 5 warning(s)\n'
module mult_32x32 (
	input [0:31] a,
	input [0:31] b,
	output [0:63] out,
    input [0:1] mode);

    reg [0:63] out_reg;

    always @(mode, a, b) begin 
       if (2'b01 == mode) begin
         out_reg[0:15] <= a[0:7] * b[0:7];
         out_reg[16:31] <= a[8:15] * b[8:15];
         out_reg[32:47] <= a[16:23] * b[16:23];
         out_reg[48:63] <= a[24:31] * b[24:31];
       end else if (2'b10 == mode) begin
         out_reg[0:31] <= a[0:15] * b[0:15];
         out_reg[32:63] <= a[16:31] * b[16:31];
       end else begin
         out_reg <= a * b;
       end
    end

    assign out = out_reg;

endmodule
module mult_32x32 (
	input [0:31] a,
	input [0:31] b,
	output [0:63] out,
    input [0:1] mode);


    reg [0:63] out_reg;

    always @(mode, a, b) begin 
       if (2'b01 == mode) begin
         out_reg[0:15] <= a[0:7] * b[0:7];
         out_reg[16:31] <= a[8:15] * b[8:15];
         out_reg[32:47] <= a[16:23] * b[16:23];
         out_reg[48:63] <= a[24:31] * b[24:31];
       end else if (2'b10 == mode) begin
         out_reg[0:31] <= a[0:15] * b[0:15];
         out_reg[32:63] <= a[16:31] * b[16:31];
       end else begin
         out_reg <= a * b;
       end
    end

    assign out = out_reg;

endmodule