data/full_repos/permissive/146246005/Sequence Controller/SeqConTL.sv
 line:18: before: "package"
1: b'%Error: Cannot find file containing module: Controller,data/full_repos/permissive/146246005\n        ... Looked in:\n             data/full_repos/permissive/146246005/Sequence/Controller,data/full_repos/permissive/146246005\n             data/full_repos/permissive/146246005/Sequence/Controller,data/full_repos/permissive/146246005.v\n             data/full_repos/permissive/146246005/Sequence/Controller,data/full_repos/permissive/146246005.sv\n             Controller,data/full_repos/permissive/146246005\n             Controller,data/full_repos/permissive/146246005.v\n             Controller,data/full_repos/permissive/146246005.sv\n             obj_dir/Controller,data/full_repos/permissive/146246005\n             obj_dir/Controller,data/full_repos/permissive/146246005.v\n             obj_dir/Controller,data/full_repos/permissive/146246005.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/Sequence\n%Error: Cannot find file containing module: Controller/SeqConTL.sv\n%Error: Exiting due to 3 error(s)\n'
module sequence_controller(ADDR,OPCODE,PHASE,I_FLAG,ZF,NF,OF,CF,IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS);
    import cycle_package::*;
	input [6:0] ADDR;
	input [3:0] OPCODE;
	input CYCLE PHASE;
	input I_FLAG,ZF,NF,OF,CF;
	output reg IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS;
	reg branches;

  localparam	LOAD = 0,
		  		STORE = 1,
		  		ADD = 2,
		  		SUB = 3,
		  		AND = 4,
		  		OR = 5,
		  		XOR = 6,
		  		NOT = 7,
		  		B = 8,	
		  		BZ = 9,	
		  		BN = 10,	
		  		BV = 11,	
		  		BC = 12;	

always @(PHASE,I_FLAG,ZF,NF,OF,CF,ADDR,OPCODE)
	case (PHASE)

	FETCH:
	begin
	IR_EN=1'b1; 
	PC_EN=1'b0;
	end

	DECODE:
	begin
		case (OPCODE)
		LOAD:
		begin
		RAM_OE <= 1'b1;
		RAM_CS <= 1'b1;
		RDR_EN <= 1'b1;
		end

		STORE:
		begin
		if(ADDR==67) PORT_RD <= 1'b1;
		else ALU_OE <= 1'b1;
		end

		ADD:
		begin
		A_EN = 1'b1;
		B_EN = 1'b1;
		end

		SUB:
		begin
		A_EN = 1'b1;
		B_EN = 1'b1;
		end

		AND:
		begin
		A_EN = 1'b1;
		B_EN = 1'b1;
		end

		OR:
		begin
		A_EN = 1'b1;
		B_EN = 1'b1;
		end

		XOR:
		begin
		A_EN = 1'b1;
		B_EN = 1'b1;
		end

		NOT:
		begin
		A_EN = 1'b1;
		B_EN = 1'b1;
		end


		endcase
	end 

	EXECUTE:
	begin 
		case (OPCODE) 
		LOAD:
		begin
			case (ADDR)
			64: A_EN = 1'b1;    
			65: B_EN =1'b1;     
			66: PDR_EN <=1'b1;   
			67: PORT_EN <=1'b1;  
			endcase
		end
		
		STORE:
		begin
		RAM_CS <= 1'b0;
		end
		
		ADD:
		begin
		ALU_EN <=1'b1; 
		end

		SUB:
		begin
		ALU_EN <=1'b1;
		end

		AND:
		begin
		ALU_EN <=1'b1;
		end

		OR:
		begin
		ALU_EN <=1'b1;
		end

		XOR:
		begin
		ALU_EN <=1'b1;
		end

		NOT:
		begin
		ALU_EN <=1'b1;
		end

	endcase
    end



	UPDATE: begin
	case(OPCODE)
		B: PC_LOAD=1'b1;
		BZ: PC_LOAD=ZF;
		BN: PC_LOAD=NF;
		BV: PC_LOAD=OF;
		BC: PC_LOAD=CF;
		default: PC_LOAD=1'b0;
	endcase
	IR_EN <= 1'b0;
	A_EN = 1'b0;
	B_EN = 1'b0;
	PDR_EN <= 1'b0;
	PORT_EN <= 1'b0;
	PORT_RD <= 1'b0;
	ALU_EN <= 1'b0;
	ALU_OE <= 1'b0;
	RAM_OE <= 1'b0;
	RDR_EN <= 1'b0;
	PC_EN=1'b1; 
	PC_LOAD=1'b0; 
	RAM_CS <= 1'b1; 
	end

    default: begin
      	IR_EN <= 1'b0;
		A_EN = 1'b0;
		B_EN = 1'b0;
		PDR_EN <= 1'b0;
		PORT_EN <= 1'b0;
		PORT_RD <= 1'b0;
		ALU_EN <= 1'b0;
		ALU_OE <= 1'b0;
		RAM_OE <= 1'b0;
		RDR_EN <= 1'b0;
		PC_EN=1'b0; 
		PC_LOAD=1'b0; 
		RAM_CS <= 1'b1;
    end
	endcase
endmodule
module sequence_controller(ADDR,OPCODE,PHASE,I_FLAG,ZF,NF,OF,CF,IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS);

    import cycle_package::*;
	input [6:0] ADDR;
	input [3:0] OPCODE;
	input CYCLE PHASE;
	input I_FLAG,ZF,NF,OF,CF;
	output reg IR_EN,A_EN,B_EN,PDR_EN,PORT_EN,PORT_RD,PC_EN,PC_LOAD,ALU_EN,ALU_OE,RAM_OE,RDR_EN,RAM_CS;
	reg branches;

  localparam	LOAD = 0,
		  		STORE = 1,
		  		ADD = 2,
		  		SUB = 3,
		  		AND = 4,
		  		OR = 5,
		  		XOR = 6,
		  		NOT = 7,
		  		B = 8,	
		  		BZ = 9,	
		  		BN = 10,	
		  		BV = 11,	
		  		BC = 12;	

always @(PHASE,I_FLAG,ZF,NF,OF,CF,ADDR,OPCODE)
	case (PHASE)

	FETCH:
	begin
	IR_EN=1'b1; 
	PC_EN=1'b0;
	end

	DECODE:
	begin
		case (OPCODE)
		LOAD:
		begin
		RAM_OE <= 1'b1;
		RAM_CS <= 1'b1;
		RDR_EN <= 1'b1;
		end

		STORE:
		begin
		if(ADDR==67) PORT_RD <= 1'b1;
		else ALU_OE <= 1'b1;
		end

		ADD:
		begin
		A_EN = 1'b1;
		B_EN = 1'b1;
		end

		SUB:
		begin
		A_EN = 1'b1;
		B_EN = 1'b1;
		end

		AND:
		begin
		A_EN = 1'b1;
		B_EN = 1'b1;
		end

		OR:
		begin
		A_EN = 1'b1;
		B_EN = 1'b1;
		end

		XOR:
		begin
		A_EN = 1'b1;
		B_EN = 1'b1;
		end

		NOT:
		begin
		A_EN = 1'b1;
		B_EN = 1'b1;
		end


		endcase
	end 

	EXECUTE:
	begin 
		case (OPCODE) 
		LOAD:
		begin
			case (ADDR)
			64: A_EN = 1'b1;    
			65: B_EN =1'b1;     
			66: PDR_EN <=1'b1;   
			67: PORT_EN <=1'b1;  
			endcase
		end
		
		STORE:
		begin
		RAM_CS <= 1'b0;
		end
		
		ADD:
		begin
		ALU_EN <=1'b1; 
		end

		SUB:
		begin
		ALU_EN <=1'b1;
		end

		AND:
		begin
		ALU_EN <=1'b1;
		end

		OR:
		begin
		ALU_EN <=1'b1;
		end

		XOR:
		begin
		ALU_EN <=1'b1;
		end

		NOT:
		begin
		ALU_EN <=1'b1;
		end

	endcase
    end



	UPDATE: begin
	case(OPCODE)
		B: PC_LOAD=1'b1;
		BZ: PC_LOAD=ZF;
		BN: PC_LOAD=NF;
		BV: PC_LOAD=OF;
		BC: PC_LOAD=CF;
		default: PC_LOAD=1'b0;
	endcase
	IR_EN <= 1'b0;
	A_EN = 1'b0;
	B_EN = 1'b0;
	PDR_EN <= 1'b0;
	PORT_EN <= 1'b0;
	PORT_RD <= 1'b0;
	ALU_EN <= 1'b0;
	ALU_OE <= 1'b0;
	RAM_OE <= 1'b0;
	RDR_EN <= 1'b0;
	PC_EN=1'b1; 
	PC_LOAD=1'b0; 
	RAM_CS <= 1'b1; 
	end

    default: begin
      	IR_EN <= 1'b0;
		A_EN = 1'b0;
		B_EN = 1'b0;
		PDR_EN <= 1'b0;
		PORT_EN <= 1'b0;
		PORT_RD <= 1'b0;
		ALU_EN <= 1'b0;
		ALU_OE <= 1'b0;
		RAM_OE <= 1'b0;
		RDR_EN <= 1'b0;
		PC_EN=1'b0; 
		PC_LOAD=1'b0; 
		RAM_CS <= 1'b1;
    end
	endcase
endmodule