data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/txd.v
None: at end of input
1: b'%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/txd.v:14: Cannot find include file: .\\\\src\\\\head_uart.v\n`include    ".\\\\src\\\\head_uart.v" \n            ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src,data/full_repos/permissive/166661632/.\\\\src\\\\head_uart.v\n             data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src,data/full_repos/permissive/166661632/.\\\\src\\\\head_uart.v.v\n             data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src,data/full_repos/permissive/166661632/.\\\\src\\\\head_uart.v.sv\n             .\\\\src\\\\head_uart.v\n             .\\\\src\\\\head_uart.v.v\n             .\\\\src\\\\head_uart.v.sv\n             obj_dir/.\\\\src\\\\head_uart.v\n             obj_dir/.\\\\src\\\\head_uart.v.v\n             obj_dir/.\\\\src\\\\head_uart.v.sv\n%Error: Exiting due to 1 error(s)\n'
module  tx_unit( d_in, load, en_tx, txd, ts, clk, rst ) ;
    input   [7:0]                   d_in ;
    input                           load ;
    input                           en_tx ;
    output                          txd ;
    output                          ts ;
    input                           clk ;
    input                           rst ;
    

    ctrl_shift  U_CTRL_SHFT( en_tx, load, shift, ts, clk, rst ) ;


    trans_reg   U_TRANS_REG( d_in, load, shift, txd, clk, rst ) ;
    
endmodule
module  tx_unit( d_in, load, en_tx, txd, ts, clk, rst ) ;

    input   [7:0]                   d_in ;
    input                           load ;
    input                           en_tx ;
    output                          txd ;
    output                          ts ;
    input                           clk ;
    input                           rst ;
    

    ctrl_shift  U_CTRL_SHFT( en_tx, load, shift, ts, clk, rst ) ;


    trans_reg   U_TRANS_REG( d_in, load, shift, txd, clk, rst ) ;
    
endmodule