data/full_repos/permissive/20803096/rslatch_tb.v
 line:4: before: "("
1: b'%Error: data/full_repos/permissive/20803096/rslatch_tb.v:1: Cannot find include file: simulargs_incl.v\n`include "simulargs_incl.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20803096,data/full_repos/permissive/20803096/simulargs_incl.v\n             data/full_repos/permissive/20803096,data/full_repos/permissive/20803096/simulargs_incl.v.v\n             data/full_repos/permissive/20803096,data/full_repos/permissive/20803096/simulargs_incl.v.sv\n             simulargs_incl.v\n             simulargs_incl.v.v\n             simulargs_incl.v.sv\n             obj_dir/simulargs_incl.v\n             obj_dir/simulargs_incl.v.v\n             obj_dir/simulargs_incl.v.sv\n%Error: data/full_repos/permissive/20803096/rslatch_tb.v:4: Cannot find include file: simulutil_incl.v\n`include "simulutil_incl.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/20803096/rslatch_tb.v:15: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("rslatch_wave.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/20803096/rslatch_tb.v:16: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, testbench);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20803096/rslatch_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #250;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20803096/rslatch_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n   #250;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/20803096/rslatch_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n   #250;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/20803096/rslatch_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n   #250;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/20803096/rslatch_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n   #250;\n   ^\n%Error: Exiting due to 4 error(s), 5 warning(s)\n'
module testbench;
`include "simulutil_incl.v"
	reg r;
	reg s;
	wire q;
	wire nq;
	
	integer i;

	rslatch rsl1 (r, s, 1, q, nq);

	initial begin
		$dumpfile("rslatch_wave.vcd");
		$dumpvars(0, testbench);

		r <= 1;
		s <= 0;

		#250;

		for(i = 0; i < 5; i = i + 1)
		begin
			s <= 0;
			r <= 0;

			#250;
			$display("r = %b, s = %b, q = %b, nq = %b", r, s, q, nq);
			assert (q == 0 && nq != 0);
	
			s <= 1;
			r <= 0;

			#250;
			$display("r = %b, s = %b, q = %b, nq = %b", r, s, q, nq);
			assert (q == 1 && nq != 1);

			s <= 0;
			r <= 0;
	
			#250;
			$display("r = %b, s = %b, q = %b, nq = %b", r, s, q, nq);
			assert (q == 1 && nq != 1);
	
			s <= 0;
			r <= 1;
	
			#250;
			$display("r = %b, s = %b, q = %b, nq = %b", r, s, q, nq);
			assert (q == 0 && nq != 0);
		end
	end
endmodule
module testbench;

`include "simulutil_incl.v"
	reg r;
	reg s;
	wire q;
	wire nq;
	
	integer i;

	rslatch rsl1 (r, s, 1, q, nq);

	initial begin
		$dumpfile("rslatch_wave.vcd");
		$dumpvars(0, testbench);

		r <= 1;
		s <= 0;

		#250;

		for(i = 0; i < 5; i = i + 1)
		begin
			s <= 0;
			r <= 0;

			#250;
			$display("r = %b, s = %b, q = %b, nq = %b", r, s, q, nq);
			assert (q == 0 && nq != 0);
	
			s <= 1;
			r <= 0;

			#250;
			$display("r = %b, s = %b, q = %b, nq = %b", r, s, q, nq);
			assert (q == 1 && nq != 1);

			s <= 0;
			r <= 0;
	
			#250;
			$display("r = %b, s = %b, q = %b, nq = %b", r, s, q, nq);
			assert (q == 1 && nq != 1);
	
			s <= 0;
			r <= 1;
	
			#250;
			$display("r = %b, s = %b, q = %b, nq = %b", r, s, q, nq);
			assert (q == 0 && nq != 0);
		end
	end
endmodule