data/full_repos/permissive/209997170/LEDTrial1/work/planAhead/LEDTrial1/LEDTrial1.srcs/sources_1/imports/verilog/mojo_top_0.v
1: b"%Error: data/full_repos/permissive/209997170/LEDTrial1/work/planAhead/LEDTrial1/LEDTrial1.srcs/sources_1/imports/verilog/mojo_top_0.v:29: Cannot find file containing module: 'reset_conditioner_1'\n  reset_conditioner_1 reset_cond (\n  ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/209997170/LEDTrial1/work/planAhead/LEDTrial1/LEDTrial1.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170/reset_conditioner_1\n             data/full_repos/permissive/209997170/LEDTrial1/work/planAhead/LEDTrial1/LEDTrial1.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170/reset_conditioner_1.v\n             data/full_repos/permissive/209997170/LEDTrial1/work/planAhead/LEDTrial1/LEDTrial1.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170/reset_conditioner_1.sv\n             reset_conditioner_1\n             reset_conditioner_1.v\n             reset_conditioner_1.sv\n             obj_dir/reset_conditioner_1\n             obj_dir/reset_conditioner_1.v\n             obj_dir/reset_conditioner_1.sv\n%Error: data/full_repos/permissive/209997170/LEDTrial1/work/planAhead/LEDTrial1/LEDTrial1.srcs/sources_1/imports/verilog/mojo_top_0.v:40: Cannot find file containing module: 'ledprocess_2'\n  ledprocess_2 led2 (\n  ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mojo_top_0 (
    input clk,
    input rst_n,
    output reg [7:0] led,
    input cclk,
    output reg spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,
    output reg [3:0] spi_channel,
    input avr_tx,
    output reg avr_rx,
    input avr_rx_busy,
    output reg outled
  );
  
  
  
  reg rst;
  
  wire [1-1:0] M_reset_cond_out;
  reg [1-1:0] M_reset_cond_in;
  reset_conditioner_1 reset_cond (
    .clk(clk),
    .in(M_reset_cond_in),
    .out(M_reset_cond_out)
  );
  wire [8-1:0] M_led2_pixel;
  wire [1-1:0] M_led2_led;
  reg [256-1:0] M_led2_map;
  reg [8-1:0] M_led2_win_pos;
  reg [16-1:0] M_led2_player_pos;
  reg [1-1:0] M_led2_update;
  ledprocess_2 led2 (
    .clk(clk),
    .rst(rst),
    .map(M_led2_map),
    .win_pos(M_led2_win_pos),
    .player_pos(M_led2_player_pos),
    .update(M_led2_update),
    .pixel(M_led2_pixel),
    .led(M_led2_led)
  );
  
  always @* begin
    M_reset_cond_in = ~rst_n;
    rst = M_reset_cond_out;
    led = 8'h11;
    spi_miso = 1'bz;
    spi_channel = 4'bzzzz;
    avr_rx = 1'bz;
    M_led2_update = 1'h1;
    M_led2_win_pos = 8'h75;
    M_led2_player_pos = 16'h8889;
    M_led2_map = 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff;
    outled = M_led2_led;
  end
endmodule
module mojo_top_0 (
    input clk,
    input rst_n,
    output reg [7:0] led,
    input cclk,
    output reg spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,
    output reg [3:0] spi_channel,
    input avr_tx,
    output reg avr_rx,
    input avr_rx_busy,
    output reg outled
  );

  
  
  
  reg rst;
  
  wire [1-1:0] M_reset_cond_out;
  reg [1-1:0] M_reset_cond_in;
  reset_conditioner_1 reset_cond (
    .clk(clk),
    .in(M_reset_cond_in),
    .out(M_reset_cond_out)
  );
  wire [8-1:0] M_led2_pixel;
  wire [1-1:0] M_led2_led;
  reg [256-1:0] M_led2_map;
  reg [8-1:0] M_led2_win_pos;
  reg [16-1:0] M_led2_player_pos;
  reg [1-1:0] M_led2_update;
  ledprocess_2 led2 (
    .clk(clk),
    .rst(rst),
    .map(M_led2_map),
    .win_pos(M_led2_win_pos),
    .player_pos(M_led2_player_pos),
    .update(M_led2_update),
    .pixel(M_led2_pixel),
    .led(M_led2_led)
  );
  
  always @* begin
    M_reset_cond_in = ~rst_n;
    rst = M_reset_cond_out;
    led = 8'h11;
    spi_miso = 1'bz;
    spi_channel = 4'bzzzz;
    avr_rx = 1'bz;
    M_led2_update = 1'h1;
    M_led2_win_pos = 8'h75;
    M_led2_player_pos = 16'h8889;
    M_led2_map = 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff;
    outled = M_led2_led;
  end
endmodule