data/full_repos/permissive/143278/ivltests/br_gh127e.v
 line:30: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh127e.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #1 $display("%b : %b %b : %b %b : %b %b", r[1:0], i1, o1, i2, o2, i3, o3);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br_gh127e.v:17: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 3 bits.\n                                                                         : ... In instance top\nassign i1 = r;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br_gh127e.v:18: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 3 bits.\n                                                                         : ... In instance top\nassign i2 = r;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br_gh127e.v:19: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 3 bits.\n                                                                         : ... In instance top\nassign i3 = r;\n          ^\n%Error: data/full_repos/permissive/143278/ivltests/br_gh127e.v:21: Unsupported: Inout port connection \'out\' to inout signal requires 2 bits, but connection\'s VARREF \'o1\' generates 1 bits.\n                                                                 : ... In instance top\ncopy copy1(o1, i1);\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br_gh127e.v:21: Inout port connection \'out\' expects 2 bits on the pin connection, but pin connection\'s VARREF \'o1\' generates 1 bits.\n                                                                         : ... In instance top\ncopy copy1(o1, i1);\n           ^~\n%Error: data/full_repos/permissive/143278/ivltests/br_gh127e.v:23: Unsupported: Inout port connection \'out\' to inout signal requires 2 bits, but connection\'s VARREF \'o3\' generates 3 bits.\n                                                                 : ... In instance top\ncopy copy3(o3, i3);\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br_gh127e.v:23: Inout port connection \'out\' expects 2 bits on the pin connection, but pin connection\'s VARREF \'o3\' generates 3 bits.\n                                                                         : ... In instance top\ncopy copy3(o3, i3);\n           ^~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top();

reg  [2:0] r;
wire [1:0] i1;
wire [1:0] i2;
wire [1:0] i3;
wire [0:0] o1;
wire [1:0] o2;
wire [2:0] o3;

assign i1 = r;
assign i2 = r;
assign i3 = r;

copy copy1(o1, i1);
copy copy2(o2, i2);
copy copy3(o3, i3);

reg failed;

initial begin
  failed = 0;
  for (r = 0; r < 4; r = r + 1) begin
    #1 $display("%b : %b %b : %b %b : %b %b", r[1:0], i1, o1, i2, o2, i3, o3);
    if (o1 !== r[0])           failed = 1;
    if (o2 !== r[1:0])         failed = 1;
    if (o3 !== {1'bz, r[1:0]}) failed = 1;
  end
  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule
module top();


reg  [2:0] r;
wire [1:0] i1;
wire [1:0] i2;
wire [1:0] i3;
wire [0:0] o1;
wire [1:0] o2;
wire [2:0] o3;

assign i1 = r;
assign i2 = r;
assign i3 = r;

copy copy1(o1, i1);
copy copy2(o2, i2);
copy copy3(o3, i3);

reg failed;

initial begin
  failed = 0;
  for (r = 0; r < 4; r = r + 1) begin
    #1 $display("%b : %b %b : %b %b : %b %b", r[1:0], i1, o1, i2, o2, i3, o3);
    if (o1 !== r[0])           failed = 1;
    if (o2 !== r[1:0])         failed = 1;
    if (o3 !== {1'bz, r[1:0]}) failed = 1;
  end
  if (failed)
    $display("FAILED");
  else
    $display("PASSED");
end

endmodule