data/full_repos/permissive/205055389/test/verga/spec5.v
 line:20: before: "."
1: b'%Error: data/full_repos/permissive/205055389/test/verga/spec5.v:7: Unsupported or unknown PLI call: $monitor\n    $monitor("%4d: a=%d b=%d - x=%d y=%d",$time,a,b,x,y);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/spec5.v:13: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/205055389/test/verga/spec5.v:20: syntax error, unexpected \'.\', expecting \'[\'\nmodule foo #(.p1(10), .p2(21)) (a,b,x,y);\n             ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module foo #(.p1(10), .p2(21)) (a,b,x,y);
input a,b;
output x,y;

  specify
    if (a) (a *> x) = p1;
    if (!a) (a *> x) = p2;
    (b *> x) = 12;
    (a, b *> y) = 17;
  endspecify

  assign {x,y} = a + b;

endmodule
module foo #(.p1(10), .p2(21)) (a,b,x,y);

input a,b;
output x,y;

  specify
    if (a) (a *> x) = p1;
    if (!a) (a *> x) = p2;
    (b *> x) = 12;
    (a, b *> y) = 17;
  endspecify

  assign {x,y} = a + b;

endmodule