data/full_repos/permissive/101427841/test_v/micro_test1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #90;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #160; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #120;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:143: Unsupported: Ignoring delay on this delayed statement.\n  #120;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:151: Unsupported: Ignoring delay on this delayed statement.\n  #120;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:154: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:160: Unsupported: Ignoring delay on this delayed statement.\n  #150;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #120;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:168: Unsupported: Ignoring delay on this delayed statement.\n  #120;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/101427841/test_v/micro_test1.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: data/full_repos/permissive/101427841/test_v/micro_test1.v:46: Cannot find file containing module: \'MCPU_v1\'\n MCPU_v1 uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/101427841/test_v,data/full_repos/permissive/101427841/MCPU_v1\n             data/full_repos/permissive/101427841/test_v,data/full_repos/permissive/101427841/MCPU_v1.v\n             data/full_repos/permissive/101427841/test_v,data/full_repos/permissive/101427841/MCPU_v1.sv\n             MCPU_v1\n             MCPU_v1.v\n             MCPU_v1.sv\n             obj_dir/MCPU_v1\n             obj_dir/MCPU_v1.v\n             obj_dir/MCPU_v1.sv\n%Error: Exiting due to 1 error(s), 25 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module micro_test1;


	reg clk;
	reg reset;
	reg [31:0] Data_in;
	reg [4:0] test_reg_index;
	reg INT;
	reg MIO_ready;


	wire mem_w;
	wire [31:0] Addr_out;
	wire [31:0] Data_out;
	wire [4:0] state;
	wire [31:0] PC_out;
	wire [31:0] inst_out;
	wire [31:0] test_reg_result;
	wire CPU_MIO;


	MCPU_v1 uut (
		.clk(clk), 
		.reset(reset), 
		.mem_w(mem_w), 
		.Addr_out(Addr_out), 
		.Data_out(Data_out), 
		.Data_in(Data_in), 
		.state(state), 
		.PC_out(PC_out), 
		.inst_out(inst_out), 
		.test_reg_index(test_reg_index), 
		.test_reg_result(test_reg_result), 
		.INT(INT), 
		.MIO_ready(MIO_ready), 
		.CPU_MIO(CPU_MIO)
	);

		initial begin

		clk = 0;
		reset = 0;
		Data_in = 0;
		test_reg_index = 0;
		INT = 0;
		MIO_ready = 0;


		#10;
		reset = 1;
		#90;
		reset = 0;
		
		Data_in = 32'h20210001;
		test_reg_index = 1;
		#160;
		
		Data_in = 32'h00211020;
		test_reg_index = 2;
		#160;
		
		Data_in = 32'h34630003;
		test_reg_index = 3;
		#160;
		
		Data_in = 32'h00622022;
		test_reg_index = 4;
		#160;
		
		Data_in = 32'h00432827;
		test_reg_index = 5;
		#160;
		
		Data_in = 32'h00433026;
		test_reg_index = 6;
		#160;
		
		Data_in = 32'h0043382A;
		test_reg_index = 7;
		#160;
		
		Data_in = 32'h28E8FFFF;
		test_reg_index = 8;
		#160;
		
		Data_in = 32'h00014FC0;
		test_reg_index = 9;
		#160;
		
		Data_in = 32'h000957C2;
		test_reg_index = 10;
		#160;
		
		Data_in = 32'h01405825;
		test_reg_index = 11;
		#160;
		
		Data_in = 32'h316CFFFF;
		test_reg_index = 12;
		#160;
		
		Data_in = 32'h3C0DFFFF;
		test_reg_index = 13;
		#160;
		
		Data_in = 32'h39AE0000;
		test_reg_index = 14;
		#160; 

		Data_in = 32'h11C0FFF1;
		#120;
		

		
		Data_in = 32'h1400FFF0;
		#120;
		


		Data_in = 32'h08000011;
		#120;
		
		Data_in = 32'hAC0E0008;
		#160;
		
		Data_in = 32'h8C0F0008;
		test_reg_index = 15;
		#50;
		Data_in = 32'h12345678;
		#150;
		
		Data_in = 32'h0C000016;
		test_reg_index = 31;
		#120;
		
		Data_in = 32'h01E08009;
		test_reg_index = 16;
		#120;
		
        
	end
	
	always @ * begin
		#20;
		clk <= ~clk;
	end
      
endmodule
module micro_test1;



	reg clk;
	reg reset;
	reg [31:0] Data_in;
	reg [4:0] test_reg_index;
	reg INT;
	reg MIO_ready;


	wire mem_w;
	wire [31:0] Addr_out;
	wire [31:0] Data_out;
	wire [4:0] state;
	wire [31:0] PC_out;
	wire [31:0] inst_out;
	wire [31:0] test_reg_result;
	wire CPU_MIO;


	MCPU_v1 uut (
		.clk(clk), 
		.reset(reset), 
		.mem_w(mem_w), 
		.Addr_out(Addr_out), 
		.Data_out(Data_out), 
		.Data_in(Data_in), 
		.state(state), 
		.PC_out(PC_out), 
		.inst_out(inst_out), 
		.test_reg_index(test_reg_index), 
		.test_reg_result(test_reg_result), 
		.INT(INT), 
		.MIO_ready(MIO_ready), 
		.CPU_MIO(CPU_MIO)
	);

		initial begin

		clk = 0;
		reset = 0;
		Data_in = 0;
		test_reg_index = 0;
		INT = 0;
		MIO_ready = 0;


		#10;
		reset = 1;
		#90;
		reset = 0;
		
		Data_in = 32'h20210001;
		test_reg_index = 1;
		#160;
		
		Data_in = 32'h00211020;
		test_reg_index = 2;
		#160;
		
		Data_in = 32'h34630003;
		test_reg_index = 3;
		#160;
		
		Data_in = 32'h00622022;
		test_reg_index = 4;
		#160;
		
		Data_in = 32'h00432827;
		test_reg_index = 5;
		#160;
		
		Data_in = 32'h00433026;
		test_reg_index = 6;
		#160;
		
		Data_in = 32'h0043382A;
		test_reg_index = 7;
		#160;
		
		Data_in = 32'h28E8FFFF;
		test_reg_index = 8;
		#160;
		
		Data_in = 32'h00014FC0;
		test_reg_index = 9;
		#160;
		
		Data_in = 32'h000957C2;
		test_reg_index = 10;
		#160;
		
		Data_in = 32'h01405825;
		test_reg_index = 11;
		#160;
		
		Data_in = 32'h316CFFFF;
		test_reg_index = 12;
		#160;
		
		Data_in = 32'h3C0DFFFF;
		test_reg_index = 13;
		#160;
		
		Data_in = 32'h39AE0000;
		test_reg_index = 14;
		#160; 

		Data_in = 32'h11C0FFF1;
		#120;
		

		
		Data_in = 32'h1400FFF0;
		#120;
		


		Data_in = 32'h08000011;
		#120;
		
		Data_in = 32'hAC0E0008;
		#160;
		
		Data_in = 32'h8C0F0008;
		test_reg_index = 15;
		#50;
		Data_in = 32'h12345678;
		#150;
		
		Data_in = 32'h0C000016;
		test_reg_index = 31;
		#120;
		
		Data_in = 32'h01E08009;
		test_reg_index = 16;
		#120;
		
        
	end
	
	always @ * begin
		#20;
		clk <= ~clk;
	end
      
endmodule