data/full_repos/permissive/143278/ivltests/real_mod_in_ca.v
 line:6: before: "="
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_mod_in_ca.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #0.9;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_mod_in_ca.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #0.1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_mod_in_ca.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_mod_in_ca.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1 ra = 2.0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_mod_in_ca.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_mod_in_ca.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #1 rb = 4.0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/real_mod_in_ca.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/real_mod_in_ca.v:10: Expected integral (non-real) input to MODDIV\n                                                                      : ... In instance top\n  assign #1 rmod = ra % rb;\n                   ^~\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/real_mod_in_ca.v:10: Implicit conversion of real to integer\n  assign #1 rmod = ra % rb;\n                   ^~\n%Error: data/full_repos/permissive/143278/ivltests/real_mod_in_ca.v:10: Expected integral (non-real) input to MODDIV\n                                                                      : ... In instance top\n  assign #1 rmod = ra % rb;\n                        ^~\n%Warning-REALCVT: data/full_repos/permissive/143278/ivltests/real_mod_in_ca.v:10: Implicit conversion of real to integer\n  assign #1 rmod = ra % rb;\n                        ^~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass = 1'b1;

  real ra = 1.0, rb = 2.0;
  wire real rmod;


  assign #1 rmod = ra % rb;

  initial begin
    #0.9;
    if (rmod == 1.0) begin
      pass = 1'b0;
      $display("Real: modulus value not delayed.");
    end

    #0.1;
    #0;
    if (rmod != 1.0) begin
      pass = 1'b0;
      $display("Real: modulus value not correct, expected 1.0 got %g.", rmod);
    end

    #1 ra = 2.0;
    #2;
    if (rmod != 0.0) begin
      pass = 1'b0;
      $display("Real: modulus value not correct, expected 0.0 got %g.", rmod);
    end

    #1 rb = 4.0;
    #2;
    if (rmod != 2.0) begin
      pass = 1'b0;
      $display("Real: modulus value not correct, expected 2.0 got %g.", rmod);
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass = 1'b1;

  real ra = 1.0, rb = 2.0;
  wire real rmod;


  assign #1 rmod = ra % rb;

  initial begin
    #0.9;
    if (rmod == 1.0) begin
      pass = 1'b0;
      $display("Real: modulus value not delayed.");
    end

    #0.1;
    #0;
    if (rmod != 1.0) begin
      pass = 1'b0;
      $display("Real: modulus value not correct, expected 1.0 got %g.", rmod);
    end

    #1 ra = 2.0;
    #2;
    if (rmod != 0.0) begin
      pass = 1'b0;
      $display("Real: modulus value not correct, expected 0.0 got %g.", rmod);
    end

    #1 rb = 4.0;
    #2;
    if (rmod != 2.0) begin
      pass = 1'b0;
      $display("Real: modulus value not correct, expected 2.0 got %g.", rmod);
    end

    if (pass) $display("PASSED");
  end
endmodule