data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v
1: b'%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:1: Cannot find include file: constants.vh\n`include "constants.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/constants.vh.sv\n             constants.vh\n             constants.vh.v\n             constants.vh.sv\n             obj_dir/constants.vh\n             obj_dir/constants.vh.v\n             obj_dir/constants.vh.sv\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:4: Define or directive not defined: \'`ADDR_LEN\'\n         parameter BRAM_ADDR_WIDTH = `ADDR_LEN,\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:4: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n         parameter BRAM_ADDR_WIDTH = `ADDR_LEN,\n                                              ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:5: Define or directive not defined: \'`DATA_LEN\'\n         parameter BRAM_DATA_WIDTH = `DATA_LEN,\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:5: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n         parameter BRAM_DATA_WIDTH = `DATA_LEN,\n                                              ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:7: syntax error, unexpected \')\', expecting \';\'\n         ) \n         ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0] raddr1,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:11: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [BRAM_DATA_WIDTH-1:0] rdata1,\n    ^~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:12: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0] waddr,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_DATA_WIDTH-1:0] wdata,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire         we\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:19: syntax error, unexpected always\n   always @ (posedge clk) begin\n   ^~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:27: Define or directive not defined: \'`ADDR_LEN\'\n         parameter BRAM_ADDR_WIDTH = `ADDR_LEN,\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:27: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n         parameter BRAM_ADDR_WIDTH = `ADDR_LEN,\n                                              ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:28: Define or directive not defined: \'`DATA_LEN\'\n         parameter BRAM_DATA_WIDTH = `DATA_LEN,\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:28: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n         parameter BRAM_DATA_WIDTH = `DATA_LEN,\n                                              ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:30: syntax error, unexpected \')\', expecting \';\'\n         ) \n         ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0] raddr1,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:34: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0] raddr2,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:35: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [BRAM_DATA_WIDTH-1:0] rdata1,\n    ^~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:36: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [BRAM_DATA_WIDTH-1:0] rdata2,\n    ^~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:37: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0] waddr,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:38: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_DATA_WIDTH-1:0] wdata,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:39: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire         we\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:44: syntax error, unexpected always\n   always @ (posedge clk) begin\n   ^~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:53: Define or directive not defined: \'`ADDR_LEN\'\n         parameter BRAM_ADDR_WIDTH = `ADDR_LEN,\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:53: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n         parameter BRAM_ADDR_WIDTH = `ADDR_LEN,\n                                              ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:54: Define or directive not defined: \'`DATA_LEN\'\n         parameter BRAM_DATA_WIDTH = `DATA_LEN,\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:54: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n         parameter BRAM_DATA_WIDTH = `DATA_LEN,\n                                              ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:56: syntax error, unexpected \')\', expecting \';\'\n         ) \n         ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:59: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0] raddr1,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:60: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0] raddr2,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:61: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [BRAM_DATA_WIDTH-1:0] rdata1,\n    ^~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:62: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [BRAM_DATA_WIDTH-1:0] rdata2,\n    ^~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:63: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0] waddr1,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:64: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0] waddr2,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:65: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_DATA_WIDTH-1:0] wdata1,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:66: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_DATA_WIDTH-1:0] wdata2,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:67: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire         we1,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:68: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire         we2\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:73: syntax error, unexpected always\n   always @ (posedge clk) begin\n   ^~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:84: Define or directive not defined: \'`ADDR_LEN\'\n         parameter BRAM_ADDR_WIDTH = `ADDR_LEN,\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:84: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n         parameter BRAM_ADDR_WIDTH = `ADDR_LEN,\n                                              ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:85: Define or directive not defined: \'`DATA_LEN\'\n         parameter BRAM_DATA_WIDTH = `DATA_LEN,\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:85: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n         parameter BRAM_DATA_WIDTH = `DATA_LEN,\n                                              ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:87: syntax error, unexpected \')\', expecting \';\'\n         ) \n         ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:90: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0]  raddr1,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:91: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0]  raddr2,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:92: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0]  raddr3,\n    ^~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/ram_sync.v:93: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [BRAM_ADDR_WIDTH-1:0]  raddr4,\n    ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ram_sync_6r2w #(
		       parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
		       parameter BRAM_DATA_WIDTH = `DATA_LEN,
		       parameter DATA_DEPTH      = 32
		       ) 
   (
    input wire 			      clk,
    input wire [BRAM_ADDR_WIDTH-1:0]  raddr1,
    input wire [BRAM_ADDR_WIDTH-1:0]  raddr2,
    input wire [BRAM_ADDR_WIDTH-1:0]  raddr3,
    input wire [BRAM_ADDR_WIDTH-1:0]  raddr4,
    input wire [BRAM_ADDR_WIDTH-1:0]  raddr5,
    input wire [BRAM_ADDR_WIDTH-1:0]  raddr6,
    output wire [BRAM_DATA_WIDTH-1:0] rdata1,
    output wire [BRAM_DATA_WIDTH-1:0] rdata2,
    output wire [BRAM_DATA_WIDTH-1:0] rdata3,
    output wire [BRAM_DATA_WIDTH-1:0] rdata4,
    output wire [BRAM_DATA_WIDTH-1:0] rdata5,
    output wire [BRAM_DATA_WIDTH-1:0] rdata6,
    input wire [BRAM_ADDR_WIDTH-1:0]  waddr1,
    input wire [BRAM_ADDR_WIDTH-1:0]  waddr2,
    input wire [BRAM_DATA_WIDTH-1:0]  wdata1,
    input wire [BRAM_DATA_WIDTH-1:0]  wdata2,
    input wire 			      we1,
    input wire 			      we2
    );

   ram_sync_2r2w 
     #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 
   mem0(
	.clk(clk),
	.raddr1(raddr1),
	.raddr2(raddr2),
	.rdata1(rdata1),
	.rdata2(rdata2),
	.waddr1(waddr1),
	.waddr2(waddr2),
	.wdata1(wdata1),
	.wdata2(wdata2),
	.we1(we1),
	.we2(we2)
	);

   ram_sync_2r2w 
     #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 
   mem1(
	.clk(clk),
	.raddr1(raddr3),
	.raddr2(raddr4),
	.rdata1(rdata3),
	.rdata2(rdata4),
	.waddr1(waddr1),
	.waddr2(waddr2),
	.wdata1(wdata1),
	.wdata2(wdata2),
	.we1(we1),
	.we2(we2)
	);

   ram_sync_2r2w 
     #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 
   mem2(
	.clk(clk),
	.raddr1(raddr5),
	.raddr2(raddr6),
	.rdata1(rdata5),
	.rdata2(rdata6),
	.waddr1(waddr1),
	.waddr2(waddr2),
	.wdata1(wdata1),
	.wdata2(wdata2),
	.we1(we1),
	.we2(we2)
	);
   
endmodule
module ram_sync_6r2w #(
		       parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
		       parameter BRAM_DATA_WIDTH = `DATA_LEN,
		       parameter DATA_DEPTH      = 32
		       ) 
   (
    input wire 			      clk,
    input wire [BRAM_ADDR_WIDTH-1:0]  raddr1,
    input wire [BRAM_ADDR_WIDTH-1:0]  raddr2,
    input wire [BRAM_ADDR_WIDTH-1:0]  raddr3,
    input wire [BRAM_ADDR_WIDTH-1:0]  raddr4,
    input wire [BRAM_ADDR_WIDTH-1:0]  raddr5,
    input wire [BRAM_ADDR_WIDTH-1:0]  raddr6,
    output wire [BRAM_DATA_WIDTH-1:0] rdata1,
    output wire [BRAM_DATA_WIDTH-1:0] rdata2,
    output wire [BRAM_DATA_WIDTH-1:0] rdata3,
    output wire [BRAM_DATA_WIDTH-1:0] rdata4,
    output wire [BRAM_DATA_WIDTH-1:0] rdata5,
    output wire [BRAM_DATA_WIDTH-1:0] rdata6,
    input wire [BRAM_ADDR_WIDTH-1:0]  waddr1,
    input wire [BRAM_ADDR_WIDTH-1:0]  waddr2,
    input wire [BRAM_DATA_WIDTH-1:0]  wdata1,
    input wire [BRAM_DATA_WIDTH-1:0]  wdata2,
    input wire 			      we1,
    input wire 			      we2
    );


   ram_sync_2r2w 
     #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 
   mem0(
	.clk(clk),
	.raddr1(raddr1),
	.raddr2(raddr2),
	.rdata1(rdata1),
	.rdata2(rdata2),
	.waddr1(waddr1),
	.waddr2(waddr2),
	.wdata1(wdata1),
	.wdata2(wdata2),
	.we1(we1),
	.we2(we2)
	);

   ram_sync_2r2w 
     #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 
   mem1(
	.clk(clk),
	.raddr1(raddr3),
	.raddr2(raddr4),
	.rdata1(rdata3),
	.rdata2(rdata4),
	.waddr1(waddr1),
	.waddr2(waddr2),
	.wdata1(wdata1),
	.wdata2(wdata2),
	.we1(we1),
	.we2(we2)
	);

   ram_sync_2r2w 
     #(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH) 
   mem2(
	.clk(clk),
	.raddr1(raddr5),
	.raddr2(raddr6),
	.rdata1(rdata5),
	.rdata2(rdata6),
	.waddr1(waddr1),
	.waddr2(waddr2),
	.wdata1(wdata1),
	.wdata2(wdata2),
	.we1(we1),
	.we2(we2)
	);
   
endmodule