data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/ALU_TF.v
 line:60: before: ")"
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/ALU_TF.v\n%Error: Exiting due to 4 error(s)\n'
module ALU_TF;


	reg [15:0] aInput;
	reg [15:0] bInput;


	reg [2:0] ALUop;
	reg [3:0] OPCodeExtention;



	wire [15:0] aluResult;
	wire C;
	wire L;
	wire F;
	wire Z;
	wire N;
	


	ALU uut (
		.aInput(aInput), 
		.bInput(bInput), 	
		.aluResult(aluResult), 
		.C(C), 
		.L(L), 
		.F(F), 
		.Z(Z), 
		.N(N)
	);
	
		ALUctrl uut (
		.ALUop(ALUop), 
		.OPCodeExtention(OPCodeExtention), 
	);
	
	integer i;
	integer errorCount, k;

	initial begin

		aInput = 0;
		bInput = 0;
		ALUop  = 0;
		OPCodeExtention = 0;
		errorCount = 0;
		

		
		
		#100
      $display("testing add"); 
		
		ALUOp = 0;
		for(i = 0; i < 512; i = i + 1)
		begin
			#10;	
			aInput = i;
			for(k = 0; k < 512; k = k + 1) 
			begin
				#10
				bInput = k;
				#10;
				if( (aInput + bInput) != aluResult)
				begin
					#10;
					$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", aInput, bInput, aluResult, aInput + bInput);
					errorCount = errorCount + 1;
				end
			end
		end
		
		
		
		
		
		#10;
		ALUOp = 4;
		#10
		$display("testing subtract");
		for(i = 0; i < 512; i = i + 1)
		begin
			#10
			{aInput, bInput} = i;
			#10
				if( (aInput - bInput) != aluResult)
				begin
					#10;
					$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", aInput, bInput, aluResult, aInput - bInput);
					errorCount = errorCount + 1;
				end
			
			#10;
		end
		$display("testing carry");
		for(i = 0; i < 512; i = i + 1)
		begin
			#10
			{aInput, bInput} = i;
			#10
				if( (aInput+ bInput) && CLFZN[4])
				begin
					#10;
					$display("A is %d. B is %d, F is %d.", aInput, bInput, aluResult);
				end
	
		end
		
		$display("Testing finished.  Error count is %d.", errorCount);	
		
	end
      
endmodule
module ALU_TF;



	reg [15:0] aInput;
	reg [15:0] bInput;


	reg [2:0] ALUop;
	reg [3:0] OPCodeExtention;



	wire [15:0] aluResult;
	wire C;
	wire L;
	wire F;
	wire Z;
	wire N;
	


	ALU uut (
		.aInput(aInput), 
		.bInput(bInput), 	
		.aluResult(aluResult), 
		.C(C), 
		.L(L), 
		.F(F), 
		.Z(Z), 
		.N(N)
	);
	
		ALUctrl uut (
		.ALUop(ALUop), 
		.OPCodeExtention(OPCodeExtention), 
	);
	
	integer i;
	integer errorCount, k;

	initial begin

		aInput = 0;
		bInput = 0;
		ALUop  = 0;
		OPCodeExtention = 0;
		errorCount = 0;
		

		
		
		#100
      $display("testing add"); 
		
		ALUOp = 0;
		for(i = 0; i < 512; i = i + 1)
		begin
			#10;	
			aInput = i;
			for(k = 0; k < 512; k = k + 1) 
			begin
				#10
				bInput = k;
				#10;
				if( (aInput + bInput) != aluResult)
				begin
					#10;
					$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", aInput, bInput, aluResult, aInput + bInput);
					errorCount = errorCount + 1;
				end
			end
		end
		
		
		
		
		
		#10;
		ALUOp = 4;
		#10
		$display("testing subtract");
		for(i = 0; i < 512; i = i + 1)
		begin
			#10
			{aInput, bInput} = i;
			#10
				if( (aInput - bInput) != aluResult)
				begin
					#10;
					$display("There was an error. A is %d. B is %d, F is %d. F should be %d.", aInput, bInput, aluResult, aInput - bInput);
					errorCount = errorCount + 1;
				end
			
			#10;
		end
		$display("testing carry");
		for(i = 0; i < 512; i = i + 1)
		begin
			#10
			{aInput, bInput} = i;
			#10
				if( (aInput+ bInput) && CLFZN[4])
				begin
					#10;
					$display("A is %d. B is %d, F is %d.", aInput, bInput, aluResult);
				end
	
		end
		
		$display("Testing finished.  Error count is %d.", errorCount);	
		
	end
      
endmodule