data/full_repos/permissive/113780415/src/top_test.v
 line:1736: before: "&&"
1: b"%Error: data/full_repos/permissive/113780415/src/top_test.v:869: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(posedge clk && enable == 1'b1)\n                                   ^~\n%Error: Cannot continue\n"
module winner_indicator(player, computer, winner, enable);




	input [1:0] player;

	input [1:0] computer;

	input enable;

	output reg [1:0] winner;

	




	always @(*)

	begin

	   if (enable == 1'b1)



			if (player == 2'b00 && computer == 2'b00)

				winner <= 2'b11;



			else if (player == 2'b00 && computer == 2'b01)

				winner <= 2'b01;



			else if (player == 2'b00 && computer == 2'b10)

				winner <= 2'b00;



			else if (player == 2'b01 && computer == 2'b01)

				winner <= 2'b11;



			else if (player == 2'b01 && computer == 2'b10)

				winner <= 2'b01;



			else if (player == 2'b01 && computer == 2'b00)

				winner <= 2'b00;



			else if (player == 2'b10 && computer == 2'b10)

				winner <= 2'b11;



			else if (player == 2'b10 && computer == 2'b00)

				winner <= 2'b01;



			else

				winner <= 2'b00;

		else

		    winner <= 2'b11;

		

	end

endmodule
module winner_indicator(player, computer, winner, enable);





	input [1:0] player;

	input [1:0] computer;

	input enable;

	output reg [1:0] winner;

	




	always @(*)

	begin

	   if (enable == 1'b1)



			if (player == 2'b00 && computer == 2'b00)

				winner <= 2'b11;



			else if (player == 2'b00 && computer == 2'b01)

				winner <= 2'b01;



			else if (player == 2'b00 && computer == 2'b10)

				winner <= 2'b00;



			else if (player == 2'b01 && computer == 2'b01)

				winner <= 2'b11;



			else if (player == 2'b01 && computer == 2'b10)

				winner <= 2'b01;



			else if (player == 2'b01 && computer == 2'b00)

				winner <= 2'b00;



			else if (player == 2'b10 && computer == 2'b10)

				winner <= 2'b11;



			else if (player == 2'b10 && computer == 2'b00)

				winner <= 2'b01;



			else

				winner <= 2'b00;

		else

		    winner <= 2'b11;

		

	end

endmodule