data/full_repos/permissive/160024456/lib/half_adder_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160024456/lib/half_adder_test.v:13: Unsupported: Ignoring delay on this delayed statement.\n    a = 0; b = 0; #10\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160024456/lib/half_adder_test.v:17: Unsupported: Ignoring delay on this delayed statement.\n    a = 1; b = 0; #10\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160024456/lib/half_adder_test.v:21: Unsupported: Ignoring delay on this delayed statement.\n    a = 0; b = 1; #10\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160024456/lib/half_adder_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n    a = 1; b = 1; #10\n                  ^\n%Error: data/full_repos/permissive/160024456/lib/half_adder_test.v:8: Cannot find file containing module: \'half_adder\'\n  half_adder dut (.a(a), .b(b), .r(r), .c(c));\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160024456/lib,data/full_repos/permissive/160024456/half_adder\n             data/full_repos/permissive/160024456/lib,data/full_repos/permissive/160024456/half_adder.v\n             data/full_repos/permissive/160024456/lib,data/full_repos/permissive/160024456/half_adder.sv\n             half_adder\n             half_adder.v\n             half_adder.sv\n             obj_dir/half_adder\n             obj_dir/half_adder.v\n             obj_dir/half_adder.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module half_adder_test;

  reg a = 0;
  reg b = 0;
  wire r;
  wire c;

  half_adder dut (.a(a), .b(b), .r(r), .c(c));

  initial begin
    $display("start");

    a = 0; b = 0; #10
    if ((r !== 0) || (c !== 0))
      $display("failed a=", a, ", b=", b, ", r=", r, ", c=", c);

    a = 1; b = 0; #10
    if ((r !== 1) || (c !== 0))
      $display("failed a=", a, ", b=", b, ", r=", r, ", c=", c);

    a = 0; b = 1; #10
    if ((r !== 1) || (c !== 0))
      $display("failed a=", a, ", b=", b, ", r=", r, ", c=", c);

    a = 1; b = 1; #10
    if ((r !== 0) || (c !== 1))
      $display("failed a=", a, ", b=", b, ", r=", r, ", c=", c);

    $display("done");
  end

endmodule
module half_adder_test;


  reg a = 0;
  reg b = 0;
  wire r;
  wire c;

  half_adder dut (.a(a), .b(b), .r(r), .c(c));

  initial begin
    $display("start");

    a = 0; b = 0; #10
    if ((r !== 0) || (c !== 0))
      $display("failed a=", a, ", b=", b, ", r=", r, ", c=", c);

    a = 1; b = 0; #10
    if ((r !== 1) || (c !== 0))
      $display("failed a=", a, ", b=", b, ", r=", r, ", c=", c);

    a = 0; b = 1; #10
    if ((r !== 1) || (c !== 0))
      $display("failed a=", a, ", b=", b, ", r=", r, ", c=", c);

    a = 1; b = 1; #10
    if ((r !== 0) || (c !== 1))
      $display("failed a=", a, ", b=", b, ", r=", r, ", c=", c);

    $display("done");
  end

endmodule