data/full_repos/permissive/148200700/Quartus/designFilesPro/FifoKBandIN/FifoKBandIN_bb.v
data/verilator_xmls/0e59c36f-e5d8-44e5-a362-201aa867d443.xml
module FifoKBandIN (
		input  wire [2:0] data,
		input  wire       wrreq,
		input  wire       rdreq,
		input  wire       wrclk,
		input  wire       rdclk,
		input  wire       aclr,
		output wire [2:0] q,
		output wire       rdempty,
		output wire       wrfull
	);
endmodule
module FifoKBandIN (
		input  wire [2:0] data,
		input  wire       wrreq,
		input  wire       rdreq,
		input  wire       wrclk,
		input  wire       rdclk,
		input  wire       aclr,
		output wire [2:0] q,
		output wire       rdempty,
		output wire       wrfull
	);

endmodule