data/full_repos/permissive/118027048/tests/VarintParser_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/118027048/tests/VarintParser_sim.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/118027048/tests/VarintParser_sim.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/118027048/tests/VarintParser_sim.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Error: data/full_repos/permissive/118027048/tests/VarintParser_sim.v:70: Cannot find file containing module: \'VarintParser\'\n VarintParser dut(\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/118027048/tests,data/full_repos/permissive/118027048/VarintParser\n             data/full_repos/permissive/118027048/tests,data/full_repos/permissive/118027048/VarintParser.v\n             data/full_repos/permissive/118027048/tests,data/full_repos/permissive/118027048/VarintParser.sv\n             VarintParser\n             VarintParser.v\n             VarintParser.sv\n             obj_dir/VarintParser\n             obj_dir/VarintParser.v\n             obj_dir/VarintParser.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module VarintParser_sim();




	reg		ready	= 0;

	reg		clk		= 0;

	initial begin
		#100;
		ready = 1;
	end

	always begin
		#5;
		clk = 0;
		#5;
		clk = ready;
	end




	reg			start	= 0;
	reg			valid	= 0;
	reg[7:0]	din 	= 0;
	reg			dsign	= 0;

	wire[63:0]	dout;
	wire		done;
	wire		error;

	VarintParser dut(
		.clk(clk),

		.start(start),
		.valid(valid),
		.din(din),
		.dsign(dsign),

		.dout(dout),
		.done(done),
		.error(error)
	);




	reg[7:0] state	= 0;

	always @(posedge clk) begin

		start	<= 0;
		valid	<= 0;
		dsign	<= 0;

		case(state)


			0: begin
				start		<= 1;
				valid		<= 1;
				din			<= 8'h8;

				state		<= 1;
			end


			1: begin

				if(!done || error || (dout != 8) ) begin
					$display("FAIL: unsigned test case 1 failed");
					$finish;
				end

				start		<= 1;
				valid		<= 1;
				din			<= 8'hac;

				state		<= 2;
			end
			2: begin
				valid		<= 1;
				din			<= 8'h02;
				state		<= 3;
			end


			3: begin

				if(!done || error || (dout != 300) ) begin
					$display("FAIL: unsigned test case 2 failed");
					$finish;
				end

				start		<= 1;
				valid		<= 1;
				dsign		<= 1;
				din			<= 8'h3;

				state		<= 4;

			end


			4: begin

				if(!done || error || ($signed(dout) != -2) ) begin
					$display("FAIL: signed test case 1 failed");
					$finish;
				end

				start		<= 1;
				valid		<= 1;
				dsign		<= 1;
				din			<= 8'h2;

				state		<= 5;

			end


			5: begin

				if(!done || error || ($signed(dout) != 1) ) begin
					$display("FAIL: signed test case 2 failed");
					$finish;
				end

				$display("PASS");
				$finish;
			end

		endcase

	end


endmodule
module VarintParser_sim();





	reg		ready	= 0;

	reg		clk		= 0;

	initial begin
		#100;
		ready = 1;
	end

	always begin
		#5;
		clk = 0;
		#5;
		clk = ready;
	end




	reg			start	= 0;
	reg			valid	= 0;
	reg[7:0]	din 	= 0;
	reg			dsign	= 0;

	wire[63:0]	dout;
	wire		done;
	wire		error;

	VarintParser dut(
		.clk(clk),

		.start(start),
		.valid(valid),
		.din(din),
		.dsign(dsign),

		.dout(dout),
		.done(done),
		.error(error)
	);




	reg[7:0] state	= 0;

	always @(posedge clk) begin

		start	<= 0;
		valid	<= 0;
		dsign	<= 0;

		case(state)


			0: begin
				start		<= 1;
				valid		<= 1;
				din			<= 8'h8;

				state		<= 1;
			end


			1: begin

				if(!done || error || (dout != 8) ) begin
					$display("FAIL: unsigned test case 1 failed");
					$finish;
				end

				start		<= 1;
				valid		<= 1;
				din			<= 8'hac;

				state		<= 2;
			end
			2: begin
				valid		<= 1;
				din			<= 8'h02;
				state		<= 3;
			end


			3: begin

				if(!done || error || (dout != 300) ) begin
					$display("FAIL: unsigned test case 2 failed");
					$finish;
				end

				start		<= 1;
				valid		<= 1;
				dsign		<= 1;
				din			<= 8'h3;

				state		<= 4;

			end


			4: begin

				if(!done || error || ($signed(dout) != -2) ) begin
					$display("FAIL: signed test case 1 failed");
					$finish;
				end

				start		<= 1;
				valid		<= 1;
				dsign		<= 1;
				din			<= 8'h2;

				state		<= 5;

			end


			5: begin

				if(!done || error || ($signed(dout) != 1) ) begin
					$display("FAIL: signed test case 2 failed");
					$finish;
				end

				$display("PASS");
				$finish;
			end

		endcase

	end


endmodule