data/full_repos/permissive/167274925/clkDiv.v
data/verilator_xmls/f5f3ab93-5d8f-4fbc-8e33-53de5d4a82c6.xml
module clkDiv(rst,clk,clkout);


parameter Div1=100000000;

input clk,rst;
output reg clkout;
reg [26:0] counter;
reg clkint;
always@(posedge clk) begin 
if(rst==1) begin
counter<=0;
clkint<=0;
clkout<=0;
end
else begin

    if( counter== Div1-1) begin
            clkout <= ~clkint;
            clkint <= ~clkint;
            counter <= 0;
         end
         else begin
            clkout <= clkint;
            clkint <= clkint;
            counter <= counter + 1;
         end
    end
 
end  
endmodule
module clkDiv(rst,clk,clkout);



parameter Div1=100000000;

input clk,rst;
output reg clkout;
reg [26:0] counter;
reg clkint;
always@(posedge clk) begin 
if(rst==1) begin
counter<=0;
clkint<=0;
clkout<=0;
end
else begin

    if( counter== Div1-1) begin
            clkout <= ~clkint;
            clkint <= ~clkint;
            counter <= 0;
         end
         else begin
            clkout <= clkint;
            clkint <= clkint;
            counter <= counter + 1;
         end
    end
 
end  
endmodule