data/full_repos/permissive/138713719/hdl/data_bus_test.v
data/verilator_xmls/de014328-31e8-49bc-83c1-8ea43ed3d973.xml
module data_bus_test
    (
    input wire clk,
    input wire rst,
    
    input wire en,
    
    output reg mem,
    output reg rw,
    input wire ready,
    
    output wire [19:0] addr,
    output reg [7:0] data2ram,
    input wire [7:0] data2fpga,
    
    output wire done,
    output wire result
    );
    
    

   

    localparam S_IDLE    = 3'd0,
               S_WRITE   = 3'd1,
               S_READ    = 3'd2,
               S_COMPARE = 3'd3,
               S_DONE    = 3'd4;
    
    localparam TEST_ADDR = 20'h0_0000;
    localparam INIT_DATA = 8'b0000_0001;
    
    localparam FAIL    = 1'b0,
               SUCCESS = 1'b1;
    
    

    

    reg [2:0] state_ff, state_ns;
    

    reg [7:0] data_ff, data_ns;
    reg result_ff, result_ns;
    
    

    
    always @(posedge clk, posedge rst)
        if(rst)
            begin
                state_ff <= S_IDLE;
                data_ff <= INIT_DATA;
                result_ff <= FAIL;
            end
        else
            begin
                state_ff <= state_ns;
                data_ff <= data_ns;
                result_ff <= result_ns;
            end
    
    

    
    always @*
        begin
            state_ns = state_ff;
            
            mem = 1'b0;
            rw = 1'b1;
            data2ram = 8'd0;
            
            data_ns = data_ff;
            result_ns = result_ff;
            
            case(state_ff)

                S_IDLE:                   
                    if(en)
                        begin
                            data_ns = INIT_DATA;
                            result_ns = FAIL;
                            
                            state_ns = S_WRITE;
                        end
                

                S_WRITE:
                    if(ready)
                        begin
                            mem = 1'b1;
                            rw = 1'b0;
                            data2ram = data_ff;
                            
                            state_ns = S_READ;
                        end
                

                S_READ:
                    if(ready)
                        begin                            
                            mem = 1'b1;
                            rw = 1'b1;
                            
                            state_ns = S_COMPARE;
                        end
                

                S_COMPARE:
                    if(ready)

                        if(data2fpga != data_ff)
                            state_ns = S_DONE;
                        else
                            if(data_ff[7])
                                begin

                                    result_ns = SUCCESS;
                                    state_ns = S_DONE;
                                end
                            else
                                begin

                                    data_ns = data_ff << 8'd1;
                                    state_ns = S_WRITE;
                                end
                
                S_DONE:
                    state_ns = S_DONE;
                
                default:
                    state_ns = S_DONE;
            
            endcase
        end
    
    



    assign addr = TEST_ADDR;
    

    assign done = (state_ff == S_DONE);
    assign result = result_ff;
    
endmodule
module data_bus_test
    (
    input wire clk,
    input wire rst,
    
    input wire en,
    
    output reg mem,
    output reg rw,
    input wire ready,
    
    output wire [19:0] addr,
    output reg [7:0] data2ram,
    input wire [7:0] data2fpga,
    
    output wire done,
    output wire result
    );

    
    

   

    localparam S_IDLE    = 3'd0,
               S_WRITE   = 3'd1,
               S_READ    = 3'd2,
               S_COMPARE = 3'd3,
               S_DONE    = 3'd4;
    
    localparam TEST_ADDR = 20'h0_0000;
    localparam INIT_DATA = 8'b0000_0001;
    
    localparam FAIL    = 1'b0,
               SUCCESS = 1'b1;
    
    

    

    reg [2:0] state_ff, state_ns;
    

    reg [7:0] data_ff, data_ns;
    reg result_ff, result_ns;
    
    

    
    always @(posedge clk, posedge rst)
        if(rst)
            begin
                state_ff <= S_IDLE;
                data_ff <= INIT_DATA;
                result_ff <= FAIL;
            end
        else
            begin
                state_ff <= state_ns;
                data_ff <= data_ns;
                result_ff <= result_ns;
            end
    
    

    
    always @*
        begin
            state_ns = state_ff;
            
            mem = 1'b0;
            rw = 1'b1;
            data2ram = 8'd0;
            
            data_ns = data_ff;
            result_ns = result_ff;
            
            case(state_ff)

                S_IDLE:                   
                    if(en)
                        begin
                            data_ns = INIT_DATA;
                            result_ns = FAIL;
                            
                            state_ns = S_WRITE;
                        end
                

                S_WRITE:
                    if(ready)
                        begin
                            mem = 1'b1;
                            rw = 1'b0;
                            data2ram = data_ff;
                            
                            state_ns = S_READ;
                        end
                

                S_READ:
                    if(ready)
                        begin                            
                            mem = 1'b1;
                            rw = 1'b1;
                            
                            state_ns = S_COMPARE;
                        end
                

                S_COMPARE:
                    if(ready)

                        if(data2fpga != data_ff)
                            state_ns = S_DONE;
                        else
                            if(data_ff[7])
                                begin

                                    result_ns = SUCCESS;
                                    state_ns = S_DONE;
                                end
                            else
                                begin

                                    data_ns = data_ff << 8'd1;
                                    state_ns = S_WRITE;
                                end
                
                S_DONE:
                    state_ns = S_DONE;
                
                default:
                    state_ns = S_DONE;
            
            endcase
        end
    
    



    assign addr = TEST_ADDR;
    

    assign done = (state_ff == S_DONE);
    assign result = result_ff;
    
endmodule