data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #500;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #104;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #104;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #104;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #104;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #104;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #104;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #104;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #104;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #104;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\nalways #20 ext_clk_25m <= ~ext_clk_25m;\n       ^\n%Error: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:17: Cannot find file containing module: \'glbl\'\nglbl glbl();\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation,data/full_repos/permissive/194847941/glbl\n             data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation,data/full_repos/permissive/194847941/glbl.v\n             data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation,data/full_repos/permissive/194847941/glbl.sv\n             glbl\n             glbl.v\n             glbl.sv\n             obj_dir/glbl\n             obj_dir/glbl.v\n             obj_dir/glbl.sv\n%Error: data/full_repos/permissive/194847941/demo/7_uart_rd_ram/simulation/uart_top_tb.v:20: Cannot find file containing module: \'uart_top\'\nuart_top uut(\n^~~~~~~~\n%Error: Exiting due to 2 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_top_tb();

reg ext_clk_25m;
reg ext_rst_n;
reg uart_rx;
wire uart_tx;


parameter PERIOD = 10;


glbl glbl();


uart_top uut(
	.ext_clk_25m(ext_clk_25m),
	.ext_rst_n(ext_rst_n),
	.uart_rx(uart_rx),
	.uart_tx(uart_tx));


initial begin

	ext_clk_25m = 0;
	ext_rst_n = 1;
	
	#500;
	uart_rx = 1;
	#104;
	
	uart_rx = 0;
	#104;
	uart_rx = 0;
	#104;
	uart_rx = 0;
	#104;
	uart_rx = 0;
	#104;
	uart_rx = 0;
	#104;
	uart_rx = 1;
	#104;
	uart_rx = 0;
	#104;
	uart_rx = 1;
	#104;
	
	uart_rx = 0;
	
		
		
	
end

always #20 ext_clk_25m <= ~ext_clk_25m;

endmodule
module uart_top_tb();


reg ext_clk_25m;
reg ext_rst_n;
reg uart_rx;
wire uart_tx;


parameter PERIOD = 10;


glbl glbl();


uart_top uut(
	.ext_clk_25m(ext_clk_25m),
	.ext_rst_n(ext_rst_n),
	.uart_rx(uart_rx),
	.uart_tx(uart_tx));


initial begin

	ext_clk_25m = 0;
	ext_rst_n = 1;
	
	#500;
	uart_rx = 1;
	#104;
	
	uart_rx = 0;
	#104;
	uart_rx = 0;
	#104;
	uart_rx = 0;
	#104;
	uart_rx = 0;
	#104;
	uart_rx = 0;
	#104;
	uart_rx = 1;
	#104;
	uart_rx = 0;
	#104;
	uart_rx = 1;
	#104;
	
	uart_rx = 0;
	
		
		
	
end

always #20 ext_clk_25m <= ~ext_clk_25m;

endmodule