data/full_repos/permissive/143278/ivltests/pr1603918.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #1 a = 1\'b1;             \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (q !== 1\'bx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1 a = 1\'b0;             \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (q !== 1\'b1) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #1 a = 1\'b1;             \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (q !== 1\'bx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1 a = 1\'bx;             \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (q !== 1\'bx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1 a = 1\'b1;             \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (q !== 1\'bx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1 a = 1\'bx; b = 1\'b1;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (q !== 1\'bx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #1 b = 1\'b0;             \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (q !== 1\'b1) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #1 b = 1\'b1;             \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1603918.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (q !== 1\'bx) begin\n    ^\n%Error: Exiting due to 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  wire q;
  reg a, b;

  initial begin



    #1 a = 1'b1;
    #1 if (q !== 1'bx) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 a = 1'b0;
    #1 if (q !== 1'b1) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 a = 1'b1;
    #1 if (q !== 1'bx) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 a = 1'bx;
    #1 if (q !== 1'bx) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 a = 1'b1;
    #1 if (q !== 1'bx) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 a = 1'bx; b = 1'b1;
    #1 if (q !== 1'bx) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 b = 1'b0;
    #1 if (q !== 1'b1) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 b = 1'b1;
    #1 if (q !== 1'bx) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    $display("PASSED");
    $finish;
  end

  nand dut (q, a, b);

endmodule
module top;

  wire q;
  reg a, b;

  initial begin



    #1 a = 1'b1;
    #1 if (q !== 1'bx) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 a = 1'b0;
    #1 if (q !== 1'b1) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 a = 1'b1;
    #1 if (q !== 1'bx) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 a = 1'bx;
    #1 if (q !== 1'bx) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 a = 1'b1;
    #1 if (q !== 1'bx) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 a = 1'bx; b = 1'b1;
    #1 if (q !== 1'bx) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 b = 1'b0;
    #1 if (q !== 1'b1) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    #1 b = 1'b1;
    #1 if (q !== 1'bx) begin
       $display("FAILED -- %b nand %b --> %b", a, b, q);
       $finish;
    end
    $display("PASSED");
    $finish;
  end

  nand dut (q, a, b);

endmodule