data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v
 line:104: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n            #(T_clk / 2);\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n            #(T_clk / 2);\n            ^\n%Error: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:110: syntax error, unexpected \'@\'\n            @(posedge oe_n);\n            ^\n%Error: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:121: syntax error, unexpected \'@\'\n            @(negedge we_n);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n            #(T_wp) sram = dq;\n            ^\n%Error: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:129: syntax error, unexpected \'@\'\n            @(negedge oe_n);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n            #(T_oe) dq_in = sram;\n            ^\n%Error: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:133: syntax error, unexpected \'@\'\n            @(posedge oe_n);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n            #(T_ohz) dq_in = 8\'bzzzz_zzzz;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n            #(T_clk / 2) rst = 0;\n            ^\n%Error: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:167: syntax error, unexpected \'@\'\n            @(posedge clk) wait(ready);\n            ^\n%Error: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:173: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:184: syntax error, unexpected \'@\'\n            @(posedge clk) wait(ready);\n            ^\n%Error: data/full_repos/permissive/138713719/sim/sram_ctrl_tb.v:190: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: Exiting due to 8 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sram_ctrl_tb;
    
    

    
    reg clk;
    reg rst;
    reg mem;
    reg rw;
    reg [19:0] addr;
    reg [7:0] data2ram;
    
    

    
    wire ready;
    wire [7:0] data2fpga;
    wire [7:0] data2fpga_unreg;
    wire we_n;
    wire oe_n;
    wire [19:0] a;
    wire [7:0] dq;
    
    

    

    localparam T_clk = 20;
    

    localparam T_wp  = 8,
               T_oe  = 4.5,
               T_ohz = 4;
    
    



    reg [7:0] dq_in;
    

    reg [7:0] sram;
    
    

    

    assign dq = dq_in;
    
    

	
    sram_ctrl uut
        (
        .clk(clk),
        .rst(rst),
        .mem(mem),
        .rw(rw),
        .ready(ready),
        .addr(addr),
        .data2ram(data2ram),
        .data2fpga(data2fpga),
        .data2fpga_unreg(data2fpga_unreg),
        .we_n(we_n),
        .oe_n(oe_n),
        .a(a),
        .dq(dq)
        );
    
    

    

    always
        begin
            clk = 1'b1;
            #(T_clk / 2);
            
            clk = 1'b0;
            #(T_clk / 2);
        end
    
    

	
    initial
        begin
            initialize();
        
            write_sram(20'h0_0000, "A");
            read_sram(20'h0_0000);
            

            @(posedge oe_n);
            @(posedge clk) $stop;
        end
    
    



    always
        begin

            @(negedge we_n);
            #(T_wp) sram = dq;
        end 
    

    always
        begin

            @(negedge oe_n);
            #(T_oe) dq_in = sram;
            

            @(posedge oe_n);
            #(T_ohz) dq_in = 8'bzzzz_zzzz;
        end
    
    

    

    task initialize;
        begin

            mem = 0;
            rw = 1;
            addr = 0;
            data2ram = 0;
            

            dq_in = 8'bzzzz_zzzz;
	        
            reset_async();
        end
    endtask
	

    task reset_async;
        begin
            rst = 1;
            #(T_clk / 2) rst = 0;
        end
    endtask
	

    task write_sram(input [19:0] address, input [7:0] data);
        begin
            @(posedge clk) wait(ready);
            mem = 1;
            rw = 0;
            addr = address;
            data2ram = data;
    
            @(posedge clk);
            mem = 0;
            rw = 1;
            addr = 0;
            data2ram = 0;
        end
    endtask
    

    task read_sram(input [19:0] address);
        begin
            @(posedge clk) wait(ready);
            mem = 1;
            rw = 1;
            addr = address;
            data2ram = 0;
            
            @(posedge clk);
            mem = 0;
            rw = 1;
            addr = 0;
            data2ram = 0;
        end
    endtask
	
endmodule
module sram_ctrl_tb;

    
    

    
    reg clk;
    reg rst;
    reg mem;
    reg rw;
    reg [19:0] addr;
    reg [7:0] data2ram;
    
    

    
    wire ready;
    wire [7:0] data2fpga;
    wire [7:0] data2fpga_unreg;
    wire we_n;
    wire oe_n;
    wire [19:0] a;
    wire [7:0] dq;
    
    

    

    localparam T_clk = 20;
    

    localparam T_wp  = 8,
               T_oe  = 4.5,
               T_ohz = 4;
    
    



    reg [7:0] dq_in;
    

    reg [7:0] sram;
    
    

    

    assign dq = dq_in;
    
    

	
    sram_ctrl uut
        (
        .clk(clk),
        .rst(rst),
        .mem(mem),
        .rw(rw),
        .ready(ready),
        .addr(addr),
        .data2ram(data2ram),
        .data2fpga(data2fpga),
        .data2fpga_unreg(data2fpga_unreg),
        .we_n(we_n),
        .oe_n(oe_n),
        .a(a),
        .dq(dq)
        );
    
    

    

    always
        begin
            clk = 1'b1;
            #(T_clk / 2);
            
            clk = 1'b0;
            #(T_clk / 2);
        end
    
    

	
    initial
        begin
            initialize();
        
            write_sram(20'h0_0000, "A");
            read_sram(20'h0_0000);
            

            @(posedge oe_n);
            @(posedge clk) $stop;
        end
    
    



    always
        begin

            @(negedge we_n);
            #(T_wp) sram = dq;
        end 
    

    always
        begin

            @(negedge oe_n);
            #(T_oe) dq_in = sram;
            

            @(posedge oe_n);
            #(T_ohz) dq_in = 8'bzzzz_zzzz;
        end
    
    

    

    task initialize;
        begin

            mem = 0;
            rw = 1;
            addr = 0;
            data2ram = 0;
            

            dq_in = 8'bzzzz_zzzz;
	        
            reset_async();
        end
    endtask
	

    task reset_async;
        begin
            rst = 1;
            #(T_clk / 2) rst = 0;
        end
    endtask
	

    task write_sram(input [19:0] address, input [7:0] data);
        begin
            @(posedge clk) wait(ready);
            mem = 1;
            rw = 0;
            addr = address;
            data2ram = data;
    
            @(posedge clk);
            mem = 0;
            rw = 1;
            addr = 0;
            data2ram = 0;
        end
    endtask
    

    task read_sram(input [19:0] address);
        begin
            @(posedge clk) wait(ready);
            mem = 1;
            rw = 1;
            addr = address;
            data2ram = 0;
            
            @(posedge clk);
            mem = 0;
            rw = 1;
            addr = 0;
            data2ram = 0;
        end
    endtask
	
endmodule