data/full_repos/permissive/101862289/btn1_pergesmentesito.v
data/verilator_xmls/f8908a4d-039a-430e-a0cb-5b1b0f795f00.xml
module btn1_pergesmentesito(
    input btn,
	 input clk,
	 input en,
    output btn1_en
    );

	 wire rst = ~btn;
	 wire carry;
	 wire engedelyezes;
	 reg[15:0] Q;


	 assign carry=(Q==4);
	 assign engedelyezes=((btn^carry)&en);


	 always@(posedge clk)
	 begin
		if(rst) Q<=16'b0;
		else if(engedelyezes) Q<=Q+1;
	 end

	 reg dff;


	 always@(posedge clk)
	 begin
		if(en)	dff<=carry;
	 end

	 assign btn1_en=(dff&~carry);



endmodule
module btn1_pergesmentesito(
    input btn,
	 input clk,
	 input en,
    output btn1_en
    );


	 wire rst = ~btn;
	 wire carry;
	 wire engedelyezes;
	 reg[15:0] Q;


	 assign carry=(Q==4);
	 assign engedelyezes=((btn^carry)&en);


	 always@(posedge clk)
	 begin
		if(rst) Q<=16'b0;
		else if(engedelyezes) Q<=Q+1;
	 end

	 reg dff;


	 always@(posedge clk)
	 begin
		if(en)	dff<=carry;
	 end

	 assign btn1_en=(dff&~carry);



endmodule