data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v
 line:23: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #52080 RX = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Error: data/full_repos/permissive/113268705/FPGA_UART/tb_UART.v:16: Cannot find file containing module: \'UART\'\n UART uart(.CLK(clk),.TX(TX),.RX(RX));\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/113268705/FPGA_UART,data/full_repos/permissive/113268705/UART\n             data/full_repos/permissive/113268705/FPGA_UART,data/full_repos/permissive/113268705/UART.v\n             data/full_repos/permissive/113268705/FPGA_UART,data/full_repos/permissive/113268705/UART.sv\n             UART\n             UART.v\n             UART.sv\n             obj_dir/UART\n             obj_dir/UART.v\n             obj_dir/UART.sv\n%Error: Exiting due to 1 error(s), 22 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_UART;

	reg clk;
	reg RX;
	wire TX;
	

	
	UART uart(.CLK(clk),.TX(TX),.RX(RX));

	
	initial begin
		clk = 0;
		RX = 1;
		#100
		#52080 RX = 0;
		
		#52080 RX = 1;
		#52080 RX = 0;
		#52080 RX = 0;
		#52080 RX = 1;
		
		#52080 RX = 0;
		#52080 RX = 1;
		#52080 RX = 1;
		#52080 RX = 0;
		
		#52080 RX = 1;
		
		#52080 RX = 0;
		
		#52080 RX = 0;
		#52080 RX = 1;
		#52080 RX = 1;
		#52080 RX = 0;
		
		#52080 RX = 1;
		#52080 RX = 0;
		#52080 RX = 0;
		#52080 RX = 1;
		
		#52080 RX = 1;
	end
	
	always
		#10 clk = ~clk;
endmodule
module tb_UART;


	reg clk;
	reg RX;
	wire TX;
	

	
	UART uart(.CLK(clk),.TX(TX),.RX(RX));

	
	initial begin
		clk = 0;
		RX = 1;
		#100
		#52080 RX = 0;
		
		#52080 RX = 1;
		#52080 RX = 0;
		#52080 RX = 0;
		#52080 RX = 1;
		
		#52080 RX = 0;
		#52080 RX = 1;
		#52080 RX = 1;
		#52080 RX = 0;
		
		#52080 RX = 1;
		
		#52080 RX = 0;
		
		#52080 RX = 0;
		#52080 RX = 1;
		#52080 RX = 1;
		#52080 RX = 0;
		
		#52080 RX = 1;
		#52080 RX = 0;
		#52080 RX = 0;
		#52080 RX = 1;
		
		#52080 RX = 1;
	end
	
	always
		#10 clk = ~clk;
endmodule