data/full_repos/permissive/129155059/05-yosys_register/registro_cond.v
1: b'%Error: data/full_repos/permissive/129155059/05-yosys_register/registro_cond.v:1: Cannot find include file: definitions.v\n`include "definitions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/05-yosys_register,data/full_repos/permissive/129155059/definitions.v\n             data/full_repos/permissive/129155059/05-yosys_register,data/full_repos/permissive/129155059/definitions.v.v\n             data/full_repos/permissive/129155059/05-yosys_register,data/full_repos/permissive/129155059/definitions.v.sv\n             definitions.v\n             definitions.v.v\n             definitions.v.sv\n             obj_dir/definitions.v\n             obj_dir/definitions.v.v\n             obj_dir/definitions.v.sv\n%Error: data/full_repos/permissive/129155059/05-yosys_register/registro_cond.v:19: Define or directive not defined: \'`PUSH\'\n      `PUSH:\n      ^~~~~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/registro_cond.v:19: syntax error, unexpected \':\', expecting endcase\n      `PUSH:\n           ^\n%Error: data/full_repos/permissive/129155059/05-yosys_register/registro_cond.v:24: syntax error, unexpected else\n        end else begin\n            ^~~~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/registro_cond.v:28: syntax error, unexpected end\n      end\n      ^~~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/registro_cond.v:30: Define or directive not defined: \'`CYCLE\'\n      `CYCLE:\n      ^~~~~~\n%Error: data/full_repos/permissive/129155059/05-yosys_register/registro_cond.v:41: Define or directive not defined: \'`LOAD\'\n      `LOAD:\n      ^~~~~\n%Error: Cannot continue\n'
module registro_cond #(parameter WIDTH = 4, parameter PwrC = 0)
(
output  reg   [WIDTH-1 : 0] Q,
output  reg                 S_OUT,

input   wire  [WIDTH-1 : 0] D,
input   wire  [1 : 0]       MODO,
input   wire                CLK, ENB, DIR, S_IN
);

always @ (posedge CLK) begin
  if (~ENB) begin
    Q <= Q;
  end else begin

    case (MODO)
      `PUSH:
      begin
        if (DIR == 0) begin
          S_OUT <= Q[WIDTH - 1];
          Q <= {Q[WIDTH - 2 : 0], S_IN};
        end else begin
          S_OUT <= Q[0];
          Q <= {S_IN, Q[WIDTH - 1 : 1]};
        end
      end

      `CYCLE:
      begin
        if (DIR == 0) begin
            Q[WIDTH - 1 : 0] <= {Q[WIDTH - 2 : 0], Q[WIDTH - 1]};
            S_OUT <= 0;
        end else begin
            Q[WIDTH - 1 : 0] <= {Q[0], Q[WIDTH - 1 : 1]};
            S_OUT <= 0;
        end
      end

      `LOAD:
      begin
        Q[WIDTH - 1 : 0] <= D[WIDTH - 1 : 0];
        S_OUT <= 0;
      end

      default:
      begin
        Q[WIDTH - 1 : 0] <= D[WIDTH - 1 : 0];
        S_OUT <= 0;
      end

    endcase

  end


end







endmodule
module registro_cond #(parameter WIDTH = 4, parameter PwrC = 0)
(
output  reg   [WIDTH-1 : 0] Q,
output  reg                 S_OUT,

input   wire  [WIDTH-1 : 0] D,
input   wire  [1 : 0]       MODO,
input   wire                CLK, ENB, DIR, S_IN
);


always @ (posedge CLK) begin
  if (~ENB) begin
    Q <= Q;
  end else begin

    case (MODO)
      `PUSH:
      begin
        if (DIR == 0) begin
          S_OUT <= Q[WIDTH - 1];
          Q <= {Q[WIDTH - 2 : 0], S_IN};
        end else begin
          S_OUT <= Q[0];
          Q <= {S_IN, Q[WIDTH - 1 : 1]};
        end
      end

      `CYCLE:
      begin
        if (DIR == 0) begin
            Q[WIDTH - 1 : 0] <= {Q[WIDTH - 2 : 0], Q[WIDTH - 1]};
            S_OUT <= 0;
        end else begin
            Q[WIDTH - 1 : 0] <= {Q[0], Q[WIDTH - 1 : 1]};
            S_OUT <= 0;
        end
      end

      `LOAD:
      begin
        Q[WIDTH - 1 : 0] <= D[WIDTH - 1 : 0];
        S_OUT <= 0;
      end

      default:
      begin
        Q[WIDTH - 1 : 0] <= D[WIDTH - 1 : 0];
        S_OUT <= 0;
      end

    endcase

  end


end







endmodule