data/full_repos/permissive/148200700/Quartus/designFiles/KBandIPsubPro/KBandIPsubPro_bb.v
data/verilator_xmls/6ac98242-7a9b-422e-92ef-2515fb5f87db.xml
module KBandIPsubPro (
		input  wire         m0_waitrequest,
		input  wire [127:0] m0_readdata,
		input  wire         m0_readdatavalid,
		output wire [4:0]   m0_burstcount,
		output wire [127:0] m0_writedata,
		output wire [29:0]  m0_address,
		output wire         m0_write,
		output wire         m0_read,
		output wire [15:0]  m0_byteenable,
		output wire         m0_debugaccess,
		output wire         kbandinput_1_csr_irq_irq,
		output wire         kbandinput_2_csr_irq_irq,
		output wire         kbandoutput_csr_irq_irq,
		input  wire         clk_clk,
		input  wire         reset_reset_n,
		input  wire         clk_int_clk,
		output wire         sfpga_waitrequest,
		output wire [63:0]  sfpga_readdata,
		output wire         sfpga_readdatavalid,
		input  wire [0:0]   sfpga_burstcount,
		input  wire [63:0]  sfpga_writedata,
		input  wire [17:0]  sfpga_address,
		input  wire         sfpga_write,
		input  wire         sfpga_read,
		input  wire [7:0]   sfpga_byteenable,
		input  wire         sfpga_debugaccess,
		output wire         slw_waitrequest,
		output wire [31:0]  slw_readdata,
		output wire         slw_readdatavalid,
		input  wire [0:0]   slw_burstcount,
		input  wire [31:0]  slw_writedata,
		input  wire [16:0]  slw_address,
		input  wire         slw_write,
		input  wire         slw_read,
		input  wire [3:0]   slw_byteenable,
		input  wire         slw_debugaccess
	);
endmodule
module KBandIPsubPro (
		input  wire         m0_waitrequest,
		input  wire [127:0] m0_readdata,
		input  wire         m0_readdatavalid,
		output wire [4:0]   m0_burstcount,
		output wire [127:0] m0_writedata,
		output wire [29:0]  m0_address,
		output wire         m0_write,
		output wire         m0_read,
		output wire [15:0]  m0_byteenable,
		output wire         m0_debugaccess,
		output wire         kbandinput_1_csr_irq_irq,
		output wire         kbandinput_2_csr_irq_irq,
		output wire         kbandoutput_csr_irq_irq,
		input  wire         clk_clk,
		input  wire         reset_reset_n,
		input  wire         clk_int_clk,
		output wire         sfpga_waitrequest,
		output wire [63:0]  sfpga_readdata,
		output wire         sfpga_readdatavalid,
		input  wire [0:0]   sfpga_burstcount,
		input  wire [63:0]  sfpga_writedata,
		input  wire [17:0]  sfpga_address,
		input  wire         sfpga_write,
		input  wire         sfpga_read,
		input  wire [7:0]   sfpga_byteenable,
		input  wire         sfpga_debugaccess,
		output wire         slw_waitrequest,
		output wire [31:0]  slw_readdata,
		output wire         slw_readdatavalid,
		input  wire [0:0]   slw_burstcount,
		input  wire [31:0]  slw_writedata,
		input  wire [16:0]  slw_address,
		input  wire         slw_write,
		input  wire         slw_read,
		input  wire [3:0]   slw_byteenable,
		input  wire         slw_debugaccess
	);

endmodule