data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_CORE_y.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_CORE_y.v:58: Little bit endian vector: MSB < LSB of bit range: -1:0\ninput [16*0 -1:0] ew_alu_in_data;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_CORE_y.v:61: Little bit endian vector: MSB < LSB of bit range: -1:0\ninput [32*0 -1:0] ew_data_in_pd;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_CORE_y.v:64: Little bit endian vector: MSB < LSB of bit range: -1:0\ninput [16*0 -1:0] ew_mul_in_data;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_CORE_y.v:67: Little bit endian vector: MSB < LSB of bit range: -1:0\noutput [32*0 -1:0] ew_data_out_pd;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_CORE_y.v:114: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [32*0 -1:0] alu_cvt_out_pd;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_CORE_y.v:117: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [32*0 -1:0] mul_cvt_out_pd;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_CORE_y.v:120: Little bit endian vector: MSB < LSB of bit range: -1:0\nwire [32*0 -1:0] core_out_pd;\n     ^\n%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_CORE_y.v:174: Cannot find file containing module: \'NV_NVDLA_SDP_HLS_Y_cvt_top\'\nNV_NVDLA_SDP_HLS_Y_cvt_top u_alu_cvt (\n^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/NV_NVDLA_SDP_HLS_Y_cvt_top\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/NV_NVDLA_SDP_HLS_Y_cvt_top.v\n             data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src,data/full_repos/permissive/157769001/NV_NVDLA_SDP_HLS_Y_cvt_top.sv\n             NV_NVDLA_SDP_HLS_Y_cvt_top\n             NV_NVDLA_SDP_HLS_Y_cvt_top.v\n             NV_NVDLA_SDP_HLS_Y_cvt_top.sv\n             obj_dir/NV_NVDLA_SDP_HLS_Y_cvt_top\n             obj_dir/NV_NVDLA_SDP_HLS_Y_cvt_top.v\n             obj_dir/NV_NVDLA_SDP_HLS_Y_cvt_top.sv\n%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_CORE_y.v:188: Cannot find file containing module: \'NV_NVDLA_SDP_HLS_Y_cvt_top\'\nNV_NVDLA_SDP_HLS_Y_cvt_top u_mul_cvt (\n^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157769001/ip_repo/nvdla_1.0/src/NV_NVDLA_SDP_CORE_y.v:202: Cannot find file containing module: \'NV_NVDLA_SDP_HLS_Y_int_core\'\nNV_NVDLA_SDP_HLS_Y_int_core u_core (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 7 warning(s)\n'
module NV_NVDLA_SDP_CORE_y (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,op_en_load
  ,pwrbus_ram_pd
  ,ew_alu_in_rdy
  ,ew_alu_in_data
  ,ew_alu_in_vld
  ,ew_mul_in_data
  ,ew_mul_in_vld
  ,ew_mul_in_rdy
  ,ew_data_in_pd
  ,ew_data_in_pvld
  ,ew_data_in_prdy
  ,reg2dp_nan_to_zero
  ,reg2dp_perf_lut_en
  ,reg2dp_proc_precision
  ,reg2dp_ew_alu_algo
  ,reg2dp_ew_alu_bypass
  ,reg2dp_ew_alu_cvt_bypass
  ,reg2dp_ew_alu_cvt_offset
  ,reg2dp_ew_alu_cvt_scale
  ,reg2dp_ew_alu_cvt_truncate
  ,reg2dp_ew_alu_operand
  ,reg2dp_ew_alu_src
  ,reg2dp_ew_lut_bypass
  ,reg2dp_ew_mul_bypass
  ,reg2dp_ew_mul_cvt_bypass
  ,reg2dp_ew_mul_cvt_offset
  ,reg2dp_ew_mul_cvt_scale
  ,reg2dp_ew_mul_cvt_truncate
  ,reg2dp_ew_mul_operand
  ,reg2dp_ew_mul_prelu
  ,reg2dp_ew_mul_src
  ,reg2dp_ew_truncate
  ,ew_data_out_pd
  ,ew_data_out_pvld
  ,ew_data_out_prdy
  );
input nvdla_core_clk;
input nvdla_core_rstn;
input [16*0 -1:0] ew_alu_in_data;
input ew_alu_in_vld;
output ew_alu_in_rdy;
input [32*0 -1:0] ew_data_in_pd;
input ew_data_in_pvld;
output ew_data_in_prdy;
input [16*0 -1:0] ew_mul_in_data;
input ew_mul_in_vld;
output ew_mul_in_rdy;
output [32*0 -1:0] ew_data_out_pd;
output ew_data_out_pvld;
input ew_data_out_prdy;
input [1:0] reg2dp_ew_alu_algo;
input reg2dp_ew_alu_bypass;
input reg2dp_ew_alu_cvt_bypass;
input [31:0] reg2dp_ew_alu_cvt_offset;
input [15:0] reg2dp_ew_alu_cvt_scale;
input [5:0] reg2dp_ew_alu_cvt_truncate;
input [31:0] reg2dp_ew_alu_operand;
input reg2dp_ew_alu_src;
input reg2dp_ew_lut_bypass;
input reg2dp_ew_mul_bypass;
input reg2dp_ew_mul_cvt_bypass;
input [31:0] reg2dp_ew_mul_cvt_offset;
input [15:0] reg2dp_ew_mul_cvt_scale;
input [5:0] reg2dp_ew_mul_cvt_truncate;
input [31:0] reg2dp_ew_mul_operand;
input reg2dp_ew_mul_prelu;
input reg2dp_ew_mul_src;
input [9:0] reg2dp_ew_truncate;
input reg2dp_nan_to_zero;
input reg2dp_perf_lut_en;
input [1:0] reg2dp_proc_precision;

input [31:0] pwrbus_ram_pd;
input op_en_load;
reg [1:0] cfg_ew_alu_algo;
reg cfg_ew_alu_bypass;
reg cfg_ew_alu_cvt_bypass;
reg [31:0] cfg_ew_alu_cvt_offset;
reg [15:0] cfg_ew_alu_cvt_scale;
reg [5:0] cfg_ew_alu_cvt_truncate;
reg [31:0] cfg_ew_alu_operand;
reg cfg_ew_alu_src;
reg cfg_ew_lut_bypass;
reg cfg_ew_mul_bypass;
reg cfg_ew_mul_cvt_bypass;
reg [31:0] cfg_ew_mul_cvt_offset;
reg [15:0] cfg_ew_mul_cvt_scale;
reg [5:0] cfg_ew_mul_cvt_truncate;
reg [31:0] cfg_ew_mul_operand;
reg cfg_ew_mul_prelu;
reg cfg_ew_mul_src;
reg [9:0] cfg_ew_truncate;
reg cfg_nan_to_zero;
reg [1:0] cfg_proc_precision;
wire [32*0 -1:0] alu_cvt_out_pd;
wire alu_cvt_out_prdy;
wire alu_cvt_out_pvld;
wire [32*0 -1:0] mul_cvt_out_pd;
wire mul_cvt_out_prdy;
wire mul_cvt_out_pvld;
wire [32*0 -1:0] core_out_pd;
wire core_out_prdy;
wire core_out_pvld;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    cfg_proc_precision <= {2{1'b0}};
    cfg_nan_to_zero <= 1'b0;
    cfg_ew_alu_operand <= {32{1'b0}};
    cfg_ew_alu_bypass <= 1'b0;
    cfg_ew_alu_algo <= {2{1'b0}};
    cfg_ew_alu_src <= 1'b0;
    cfg_ew_alu_cvt_bypass <= 1'b0;
    cfg_ew_alu_cvt_offset <= {32{1'b0}};
    cfg_ew_alu_cvt_scale <= {16{1'b0}};
    cfg_ew_alu_cvt_truncate <= {6{1'b0}};
    cfg_ew_mul_operand <= {32{1'b0}};
    cfg_ew_mul_bypass <= 1'b0;
    cfg_ew_mul_src <= 1'b0;
    cfg_ew_mul_cvt_bypass <= 1'b0;
    cfg_ew_mul_cvt_offset <= {32{1'b0}};
    cfg_ew_mul_cvt_scale <= {16{1'b0}};
    cfg_ew_mul_cvt_truncate <= {6{1'b0}};
    cfg_ew_truncate <= {10{1'b0}};
    cfg_ew_mul_prelu <= 1'b0;
    cfg_ew_lut_bypass <= 1'b1;
  end else begin
    if (op_en_load) begin
        cfg_proc_precision <= reg2dp_proc_precision ;
        cfg_nan_to_zero <= reg2dp_nan_to_zero ;
        cfg_ew_alu_operand <= reg2dp_ew_alu_operand ;
        cfg_ew_alu_bypass <= reg2dp_ew_alu_bypass ;
        cfg_ew_alu_algo <= reg2dp_ew_alu_algo ;
        cfg_ew_alu_src <= reg2dp_ew_alu_src ;
        cfg_ew_alu_cvt_bypass <= reg2dp_ew_alu_cvt_bypass ;
        cfg_ew_alu_cvt_offset <= reg2dp_ew_alu_cvt_offset ;
        cfg_ew_alu_cvt_scale <= reg2dp_ew_alu_cvt_scale ;
        cfg_ew_alu_cvt_truncate <= reg2dp_ew_alu_cvt_truncate;
        cfg_ew_mul_operand <= reg2dp_ew_mul_operand ;
        cfg_ew_mul_bypass <= reg2dp_ew_mul_bypass ;
        cfg_ew_mul_src <= reg2dp_ew_mul_src ;
        cfg_ew_mul_cvt_bypass <= reg2dp_ew_mul_cvt_bypass ;
        cfg_ew_mul_cvt_offset <= reg2dp_ew_mul_cvt_offset ;
        cfg_ew_mul_cvt_scale <= reg2dp_ew_mul_cvt_scale ;
        cfg_ew_mul_cvt_truncate <= reg2dp_ew_mul_cvt_truncate;
        cfg_ew_truncate <= reg2dp_ew_truncate ;
        cfg_ew_mul_prelu <= reg2dp_ew_mul_prelu ;
        cfg_ew_lut_bypass <= 1'b1;
    end
  end
end




NV_NVDLA_SDP_HLS_Y_cvt_top u_alu_cvt (
   .cfg_cvt_bypass (cfg_ew_alu_cvt_bypass)
  ,.cfg_cvt_offset (cfg_ew_alu_cvt_offset[31:0])
  ,.cfg_cvt_scale (cfg_ew_alu_cvt_scale[15:0])
  ,.cfg_cvt_truncate (cfg_ew_alu_cvt_truncate[5:0])
  ,.cvt_data_in (ew_alu_in_data[16*0 -1:0])
  ,.cvt_in_pvld (ew_alu_in_vld)
  ,.cvt_in_prdy (ew_alu_in_rdy)
  ,.cvt_out_prdy (alu_cvt_out_prdy)
  ,.cvt_data_out (alu_cvt_out_pd[32*0 -1:0])
  ,.cvt_out_pvld (alu_cvt_out_pvld)
  ,.nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  );
NV_NVDLA_SDP_HLS_Y_cvt_top u_mul_cvt (
   .cfg_cvt_bypass (cfg_ew_mul_cvt_bypass)
  ,.cfg_cvt_offset (cfg_ew_mul_cvt_offset[31:0])
  ,.cfg_cvt_scale (cfg_ew_mul_cvt_scale[15:0])
  ,.cfg_cvt_truncate (cfg_ew_mul_cvt_truncate[5:0])
  ,.cvt_data_in (ew_mul_in_data[16*0 -1:0])
  ,.cvt_in_pvld (ew_mul_in_vld)
  ,.cvt_in_prdy (ew_mul_in_rdy)
  ,.cvt_out_prdy (mul_cvt_out_prdy)
  ,.cvt_data_out (mul_cvt_out_pd[32*0 -1:0])
  ,.cvt_out_pvld (mul_cvt_out_pvld)
  ,.nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  );
NV_NVDLA_SDP_HLS_Y_int_core u_core (
   .cfg_alu_algo (cfg_ew_alu_algo[1:0])
  ,.cfg_alu_bypass (cfg_ew_alu_bypass)
  ,.cfg_alu_op (cfg_ew_alu_operand[31:0])
  ,.cfg_alu_src (cfg_ew_alu_src)
  ,.cfg_mul_bypass (cfg_ew_mul_bypass)
  ,.cfg_mul_op (cfg_ew_mul_operand[31:0])
  ,.cfg_mul_prelu (cfg_ew_mul_prelu)
  ,.cfg_mul_src (cfg_ew_mul_src)
  ,.cfg_mul_truncate (cfg_ew_truncate[9:0])
  ,.chn_alu_op (alu_cvt_out_pd[32*0 -1:0])
  ,.chn_alu_op_pvld (alu_cvt_out_pvld)
  ,.chn_data_in (ew_data_in_pd[32*0 -1:0])
  ,.chn_in_pvld (ew_data_in_pvld)
  ,.chn_in_prdy (ew_data_in_prdy)
  ,.chn_mul_op (mul_cvt_out_pd[32*0 -1:0])
  ,.chn_mul_op_pvld (mul_cvt_out_pvld)
  ,.chn_alu_op_prdy (alu_cvt_out_prdy)
  ,.chn_mul_op_prdy (mul_cvt_out_prdy)
  ,.chn_data_out (core_out_pd[32*0 -1:0])
  ,.chn_out_pvld (core_out_pvld)
  ,.chn_out_prdy (core_out_prdy)
  ,.nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  );
assign core_out_prdy = ew_data_out_prdy;
assign ew_data_out_pvld = core_out_pvld;
assign ew_data_out_pd = core_out_pd;
endmodule
module NV_NVDLA_SDP_CORE_y (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,op_en_load
  ,pwrbus_ram_pd
  ,ew_alu_in_rdy
  ,ew_alu_in_data
  ,ew_alu_in_vld
  ,ew_mul_in_data
  ,ew_mul_in_vld
  ,ew_mul_in_rdy
  ,ew_data_in_pd
  ,ew_data_in_pvld
  ,ew_data_in_prdy
  ,reg2dp_nan_to_zero
  ,reg2dp_perf_lut_en
  ,reg2dp_proc_precision
  ,reg2dp_ew_alu_algo
  ,reg2dp_ew_alu_bypass
  ,reg2dp_ew_alu_cvt_bypass
  ,reg2dp_ew_alu_cvt_offset
  ,reg2dp_ew_alu_cvt_scale
  ,reg2dp_ew_alu_cvt_truncate
  ,reg2dp_ew_alu_operand
  ,reg2dp_ew_alu_src
  ,reg2dp_ew_lut_bypass
  ,reg2dp_ew_mul_bypass
  ,reg2dp_ew_mul_cvt_bypass
  ,reg2dp_ew_mul_cvt_offset
  ,reg2dp_ew_mul_cvt_scale
  ,reg2dp_ew_mul_cvt_truncate
  ,reg2dp_ew_mul_operand
  ,reg2dp_ew_mul_prelu
  ,reg2dp_ew_mul_src
  ,reg2dp_ew_truncate
  ,ew_data_out_pd
  ,ew_data_out_pvld
  ,ew_data_out_prdy
  );

input nvdla_core_clk;
input nvdla_core_rstn;
input [16*0 -1:0] ew_alu_in_data;
input ew_alu_in_vld;
output ew_alu_in_rdy;
input [32*0 -1:0] ew_data_in_pd;
input ew_data_in_pvld;
output ew_data_in_prdy;
input [16*0 -1:0] ew_mul_in_data;
input ew_mul_in_vld;
output ew_mul_in_rdy;
output [32*0 -1:0] ew_data_out_pd;
output ew_data_out_pvld;
input ew_data_out_prdy;
input [1:0] reg2dp_ew_alu_algo;
input reg2dp_ew_alu_bypass;
input reg2dp_ew_alu_cvt_bypass;
input [31:0] reg2dp_ew_alu_cvt_offset;
input [15:0] reg2dp_ew_alu_cvt_scale;
input [5:0] reg2dp_ew_alu_cvt_truncate;
input [31:0] reg2dp_ew_alu_operand;
input reg2dp_ew_alu_src;
input reg2dp_ew_lut_bypass;
input reg2dp_ew_mul_bypass;
input reg2dp_ew_mul_cvt_bypass;
input [31:0] reg2dp_ew_mul_cvt_offset;
input [15:0] reg2dp_ew_mul_cvt_scale;
input [5:0] reg2dp_ew_mul_cvt_truncate;
input [31:0] reg2dp_ew_mul_operand;
input reg2dp_ew_mul_prelu;
input reg2dp_ew_mul_src;
input [9:0] reg2dp_ew_truncate;
input reg2dp_nan_to_zero;
input reg2dp_perf_lut_en;
input [1:0] reg2dp_proc_precision;

input [31:0] pwrbus_ram_pd;
input op_en_load;
reg [1:0] cfg_ew_alu_algo;
reg cfg_ew_alu_bypass;
reg cfg_ew_alu_cvt_bypass;
reg [31:0] cfg_ew_alu_cvt_offset;
reg [15:0] cfg_ew_alu_cvt_scale;
reg [5:0] cfg_ew_alu_cvt_truncate;
reg [31:0] cfg_ew_alu_operand;
reg cfg_ew_alu_src;
reg cfg_ew_lut_bypass;
reg cfg_ew_mul_bypass;
reg cfg_ew_mul_cvt_bypass;
reg [31:0] cfg_ew_mul_cvt_offset;
reg [15:0] cfg_ew_mul_cvt_scale;
reg [5:0] cfg_ew_mul_cvt_truncate;
reg [31:0] cfg_ew_mul_operand;
reg cfg_ew_mul_prelu;
reg cfg_ew_mul_src;
reg [9:0] cfg_ew_truncate;
reg cfg_nan_to_zero;
reg [1:0] cfg_proc_precision;
wire [32*0 -1:0] alu_cvt_out_pd;
wire alu_cvt_out_prdy;
wire alu_cvt_out_pvld;
wire [32*0 -1:0] mul_cvt_out_pd;
wire mul_cvt_out_prdy;
wire mul_cvt_out_pvld;
wire [32*0 -1:0] core_out_pd;
wire core_out_prdy;
wire core_out_pvld;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    cfg_proc_precision <= {2{1'b0}};
    cfg_nan_to_zero <= 1'b0;
    cfg_ew_alu_operand <= {32{1'b0}};
    cfg_ew_alu_bypass <= 1'b0;
    cfg_ew_alu_algo <= {2{1'b0}};
    cfg_ew_alu_src <= 1'b0;
    cfg_ew_alu_cvt_bypass <= 1'b0;
    cfg_ew_alu_cvt_offset <= {32{1'b0}};
    cfg_ew_alu_cvt_scale <= {16{1'b0}};
    cfg_ew_alu_cvt_truncate <= {6{1'b0}};
    cfg_ew_mul_operand <= {32{1'b0}};
    cfg_ew_mul_bypass <= 1'b0;
    cfg_ew_mul_src <= 1'b0;
    cfg_ew_mul_cvt_bypass <= 1'b0;
    cfg_ew_mul_cvt_offset <= {32{1'b0}};
    cfg_ew_mul_cvt_scale <= {16{1'b0}};
    cfg_ew_mul_cvt_truncate <= {6{1'b0}};
    cfg_ew_truncate <= {10{1'b0}};
    cfg_ew_mul_prelu <= 1'b0;
    cfg_ew_lut_bypass <= 1'b1;
  end else begin
    if (op_en_load) begin
        cfg_proc_precision <= reg2dp_proc_precision ;
        cfg_nan_to_zero <= reg2dp_nan_to_zero ;
        cfg_ew_alu_operand <= reg2dp_ew_alu_operand ;
        cfg_ew_alu_bypass <= reg2dp_ew_alu_bypass ;
        cfg_ew_alu_algo <= reg2dp_ew_alu_algo ;
        cfg_ew_alu_src <= reg2dp_ew_alu_src ;
        cfg_ew_alu_cvt_bypass <= reg2dp_ew_alu_cvt_bypass ;
        cfg_ew_alu_cvt_offset <= reg2dp_ew_alu_cvt_offset ;
        cfg_ew_alu_cvt_scale <= reg2dp_ew_alu_cvt_scale ;
        cfg_ew_alu_cvt_truncate <= reg2dp_ew_alu_cvt_truncate;
        cfg_ew_mul_operand <= reg2dp_ew_mul_operand ;
        cfg_ew_mul_bypass <= reg2dp_ew_mul_bypass ;
        cfg_ew_mul_src <= reg2dp_ew_mul_src ;
        cfg_ew_mul_cvt_bypass <= reg2dp_ew_mul_cvt_bypass ;
        cfg_ew_mul_cvt_offset <= reg2dp_ew_mul_cvt_offset ;
        cfg_ew_mul_cvt_scale <= reg2dp_ew_mul_cvt_scale ;
        cfg_ew_mul_cvt_truncate <= reg2dp_ew_mul_cvt_truncate;
        cfg_ew_truncate <= reg2dp_ew_truncate ;
        cfg_ew_mul_prelu <= reg2dp_ew_mul_prelu ;
        cfg_ew_lut_bypass <= 1'b1;
    end
  end
end




NV_NVDLA_SDP_HLS_Y_cvt_top u_alu_cvt (
   .cfg_cvt_bypass (cfg_ew_alu_cvt_bypass)
  ,.cfg_cvt_offset (cfg_ew_alu_cvt_offset[31:0])
  ,.cfg_cvt_scale (cfg_ew_alu_cvt_scale[15:0])
  ,.cfg_cvt_truncate (cfg_ew_alu_cvt_truncate[5:0])
  ,.cvt_data_in (ew_alu_in_data[16*0 -1:0])
  ,.cvt_in_pvld (ew_alu_in_vld)
  ,.cvt_in_prdy (ew_alu_in_rdy)
  ,.cvt_out_prdy (alu_cvt_out_prdy)
  ,.cvt_data_out (alu_cvt_out_pd[32*0 -1:0])
  ,.cvt_out_pvld (alu_cvt_out_pvld)
  ,.nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  );
NV_NVDLA_SDP_HLS_Y_cvt_top u_mul_cvt (
   .cfg_cvt_bypass (cfg_ew_mul_cvt_bypass)
  ,.cfg_cvt_offset (cfg_ew_mul_cvt_offset[31:0])
  ,.cfg_cvt_scale (cfg_ew_mul_cvt_scale[15:0])
  ,.cfg_cvt_truncate (cfg_ew_mul_cvt_truncate[5:0])
  ,.cvt_data_in (ew_mul_in_data[16*0 -1:0])
  ,.cvt_in_pvld (ew_mul_in_vld)
  ,.cvt_in_prdy (ew_mul_in_rdy)
  ,.cvt_out_prdy (mul_cvt_out_prdy)
  ,.cvt_data_out (mul_cvt_out_pd[32*0 -1:0])
  ,.cvt_out_pvld (mul_cvt_out_pvld)
  ,.nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  );
NV_NVDLA_SDP_HLS_Y_int_core u_core (
   .cfg_alu_algo (cfg_ew_alu_algo[1:0])
  ,.cfg_alu_bypass (cfg_ew_alu_bypass)
  ,.cfg_alu_op (cfg_ew_alu_operand[31:0])
  ,.cfg_alu_src (cfg_ew_alu_src)
  ,.cfg_mul_bypass (cfg_ew_mul_bypass)
  ,.cfg_mul_op (cfg_ew_mul_operand[31:0])
  ,.cfg_mul_prelu (cfg_ew_mul_prelu)
  ,.cfg_mul_src (cfg_ew_mul_src)
  ,.cfg_mul_truncate (cfg_ew_truncate[9:0])
  ,.chn_alu_op (alu_cvt_out_pd[32*0 -1:0])
  ,.chn_alu_op_pvld (alu_cvt_out_pvld)
  ,.chn_data_in (ew_data_in_pd[32*0 -1:0])
  ,.chn_in_pvld (ew_data_in_pvld)
  ,.chn_in_prdy (ew_data_in_prdy)
  ,.chn_mul_op (mul_cvt_out_pd[32*0 -1:0])
  ,.chn_mul_op_pvld (mul_cvt_out_pvld)
  ,.chn_alu_op_prdy (alu_cvt_out_prdy)
  ,.chn_mul_op_prdy (mul_cvt_out_prdy)
  ,.chn_data_out (core_out_pd[32*0 -1:0])
  ,.chn_out_pvld (core_out_pvld)
  ,.chn_out_prdy (core_out_prdy)
  ,.nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  );
assign core_out_prdy = ew_data_out_prdy;
assign ew_data_out_pvld = core_out_pvld;
assign ew_data_out_pd = core_out_pd;
endmodule