data/full_repos/permissive/146246005/Register- D Flip-Flop- SR Latch/dff.v
1: b'%Error: Cannot find file containing module: D\n        ... Looked in:\n             data/full_repos/permissive/146246005/Register-/D\n             data/full_repos/permissive/146246005/Register-/D.v\n             data/full_repos/permissive/146246005/Register-/D.sv\n             D\n             D.v\n             D.sv\n             obj_dir/D\n             obj_dir/D.v\n             obj_dir/D.sv\n%Error: Cannot find file containing module: Flip-Flop-\n%Error: Cannot find file containing module: SR\n%Error: Cannot find file containing module: Latch,data/full_repos/permissive/146246005\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/Register-\n%Error: Cannot find file containing module: Latch/dff.v\n%Error: Exiting due to 6 error(s)\n'
module dff(q, qbar, clock, data, clear);	

	output q, qbar;
	input clock, data, clear;

	not #(`InverterIN+ `InverterOUT) CLR1(cbar,clear);
	not #(`InverterIN+ `InverterOUT) CLR2(clr,cbar);
	not #(`InverterIN+ `InverterOUT) CLK1(clkbar,clock);
	not #(`InverterIN+ `InverterOUT) CLK2(clk,clkbar);
	not #(`InverterIN+ `InverterOUT) D1(dbar,data);
	not #(`InverterIN+ `InverterOUT) D2(d,dbar);
	
	SR_Latch2 #(2, 0.5, 3, 1.0) SR1(sbar,s,rbar,1'b1,clr,clk);
	SR_Latch2 #(3, 0.8, 3, 0.8) SR2(r,rbar,s,clk,clr,d);
	SR_Latch2 #(2, 4.5, 3, 4.5) SR3(q,qbar,s,1'b1,clr,r);

endmodule
module dff(q, qbar, clock, data, clear);
	

	output q, qbar;
	input clock, data, clear;

	not #(`InverterIN+ `InverterOUT) CLR1(cbar,clear);
	not #(`InverterIN+ `InverterOUT) CLR2(clr,cbar);
	not #(`InverterIN+ `InverterOUT) CLK1(clkbar,clock);
	not #(`InverterIN+ `InverterOUT) CLK2(clk,clkbar);
	not #(`InverterIN+ `InverterOUT) D1(dbar,data);
	not #(`InverterIN+ `InverterOUT) D2(d,dbar);
	
	SR_Latch2 #(2, 0.5, 3, 1.0) SR1(sbar,s,rbar,1'b1,clr,clk);
	SR_Latch2 #(3, 0.8, 3, 0.8) SR2(r,rbar,s,clk,clr,d);
	SR_Latch2 #(2, 4.5, 3, 4.5) SR3(q,qbar,s,1'b1,clr,r);

endmodule