data/full_repos/permissive/216344104/pid.v
1: b'%Warning-WIDTH: data/full_repos/permissive/216344104/pid.v:88: Operator ASSIGNDLY expects 40 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                             : ... In instance pid\n      drive          <= 32\'d0; \n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/216344104/pid.v:92: Operator ADD expects 40 bits on the LHS, but LHS\'s VARREF \'process\' generates 32 bits.\n                                                             : ... In instance pid\n         drive <= process + ((Kp*error)>> 3) + ((Ki*int_error_new)>> 3);\n                          ^\n%Error: Exiting due to 2 warning(s)\n'
module pid(
	input	clk,
	input	nRst,
	input    wire  signed   [31:0]   target,
    input    wire  signed   [31:0]   process,
    input    wire  signed   [31:0]   Kp,
    input    wire  signed   [31:0]   Ki,
    input    wire  signed   [31:0]   Kd,
	output   reg   signed   [39:0]   drive
);

   wire  signed   [31:0]   error;
   wire  signed   [31:0]   int_error_new;
   reg   signed   [31:0]   int_error_old;

   assign error = target - process;
   assign int_error_new = error + int_error_old;

	always@(posedge clk or negedge nRst) begin
		if(!nRst) begin
	     drive          <= 32'd0;	
         int_error_old  <= 32'd0;
		end 
		else begin 
         drive <= process + ((Kp*error)>> 3) + ((Ki*int_error_new)>> 3);
         int_error_old <= int_error_new;
		end
	end
endmodule
module pid(
	input	clk,
	input	nRst,
	input    wire  signed   [31:0]   target,
    input    wire  signed   [31:0]   process,
    input    wire  signed   [31:0]   Kp,
    input    wire  signed   [31:0]   Ki,
    input    wire  signed   [31:0]   Kd,
	output   reg   signed   [39:0]   drive
);


   wire  signed   [31:0]   error;
   wire  signed   [31:0]   int_error_new;
   reg   signed   [31:0]   int_error_old;

   assign error = target - process;
   assign int_error_new = error + int_error_old;

	always@(posedge clk or negedge nRst) begin
		if(!nRst) begin
	     drive          <= 32'd0;	
         int_error_old  <= 32'd0;
		end 
		else begin 
         drive <= process + ((Kp*error)>> 3) + ((Ki*int_error_new)>> 3);
         int_error_old <= int_error_new;
		end
	end
endmodule