data/full_repos/permissive/209997170/5. io_seg test/work/planAhead/io_seg test/io_seg test.srcs/sources_1/imports/verilog/mojo_top_0.v
1: b'%Error: Cannot find file containing module: io_seg\n        ... Looked in:\n             data/full_repos/permissive/209997170/5./io_seg\n             data/full_repos/permissive/209997170/5./io_seg.v\n             data/full_repos/permissive/209997170/5./io_seg.sv\n             io_seg\n             io_seg.v\n             io_seg.sv\n             obj_dir/io_seg\n             obj_dir/io_seg.v\n             obj_dir/io_seg.sv\n%Error: Cannot find file containing module: test/work/planAhead/io_seg\n%Error: Cannot find file containing module: test/io_seg\n%Error: Cannot find file containing module: test.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170\n%Error: Cannot find file containing module: data/full_repos/permissive/209997170/5.\n%Error: Cannot find file containing module: test.srcs/sources_1/imports/verilog/mojo_top_0.v\n%Error: Exiting due to 6 error(s)\n'
module mojo_top_0 (
    input clk,
    input rst_n,
    output reg [7:0] led,
    input cclk,
    output reg spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,
    output reg [3:0] spi_channel,
    input avr_tx,
    output reg avr_rx,
    input avr_rx_busy,
    output reg [23:0] io_led,
    output reg [7:0] io_seg,
    output reg [3:0] io_sel,
    input [4:0] io_button,
    input [23:0] io_dip
  );
  
  
  
  reg rst;
  
  wire [1-1:0] M_reset_cond_out;
  reg [1-1:0] M_reset_cond_in;
  reset_conditioner_1 reset_cond (
    .clk(clk),
    .in(M_reset_cond_in),
    .out(M_reset_cond_out)
  );
  
  always @* begin
    M_reset_cond_in = ~rst_n;
    rst = M_reset_cond_out;
    led = 8'h00;
    spi_miso = 1'bz;
    spi_channel = 4'bzzzz;
    avr_rx = 1'bz;
    io_led = 24'h000000;
    io_seg = 8'h00;
    io_sel = 4'h0;
  end
endmodule
module mojo_top_0 (
    input clk,
    input rst_n,
    output reg [7:0] led,
    input cclk,
    output reg spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,
    output reg [3:0] spi_channel,
    input avr_tx,
    output reg avr_rx,
    input avr_rx_busy,
    output reg [23:0] io_led,
    output reg [7:0] io_seg,
    output reg [3:0] io_sel,
    input [4:0] io_button,
    input [23:0] io_dip
  );

  
  
  
  reg rst;
  
  wire [1-1:0] M_reset_cond_out;
  reg [1-1:0] M_reset_cond_in;
  reset_conditioner_1 reset_cond (
    .clk(clk),
    .in(M_reset_cond_in),
    .out(M_reset_cond_out)
  );
  
  always @* begin
    M_reset_cond_in = ~rst_n;
    rst = M_reset_cond_out;
    led = 8'h00;
    spi_miso = 1'bz;
    spi_channel = 4'bzzzz;
    avr_rx = 1'bz;
    io_led = 24'h000000;
    io_seg = 8'h00;
    io_sel = 4'h0;
  end
endmodule