data/full_repos/permissive/130390123/regn.v
data/verilator_xmls/51ceeb2b-793c-4179-b246-f946b958031b.xml
module regn(
	R, 
	Rin, 
	Clock, 
	Q
	);
	parameter n = 16;
	input [n-1:0] R;
	input Rin, Clock;
	output [n-1:0] Q;
	reg [n-1:0] Q;
	always @(posedge Clock)
		if (Rin)
			Q <= R;
endmodule
module regn(
	R, 
	Rin, 
	Clock, 
	Q
	);

	parameter n = 16;
	input [n-1:0] R;
	input Rin, Clock;
	output [n-1:0] Q;
	reg [n-1:0] Q;
	always @(posedge Clock)
		if (Rin)
			Q <= R;
endmodule