data/full_repos/permissive/133161058/rca/hdl/adder.v
 line:31: before: ":"
1: b"%Error: data/full_repos/permissive/133161058/rca/hdl/adder.v:31: Define or directive not defined: '`REG_SIZE'\n        output [`REG_SIZE:0] S;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/rca/hdl/adder.v:31: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n        output [`REG_SIZE:0] S;\n                         ^\n%Error: data/full_repos/permissive/133161058/rca/hdl/adder.v:33: Define or directive not defined: '`REG_SIZE'\n        input [`REG_SIZE:0] A,B;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/rca/hdl/adder.v:33: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n        input [`REG_SIZE:0] A,B;\n                        ^\n%Error: data/full_repos/permissive/133161058/rca/hdl/adder.v:36: Define or directive not defined: '`REG_SIZE'\n        wire [`REG_SIZE:0] Atemp,Btemp,Btemp1,Stemp;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/rca/hdl/adder.v:36: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n        wire [`REG_SIZE:0] Atemp,Btemp,Btemp1,Stemp;\n                       ^\n%Error: data/full_repos/permissive/133161058/rca/hdl/adder.v:37: Define or directive not defined: '`REG_SIZE'\n        reg [`REG_SIZE:0] CIN;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/133161058/rca/hdl/adder.v:37: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\n        reg [`REG_SIZE:0] CIN;\n                      ^\n%Error: data/full_repos/permissive/133161058/rca/hdl/adder.v:50: Define or directive not defined: '`REG_SIZE'\n                for(i=0;i<`REG_SIZE+1;i=i+1)\n                          ^~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module Adder (S, sign, Asign, A, B, AS);
        output [`REG_SIZE:0] S;
        output sign;
        input [`REG_SIZE:0] A,B;
        input Asign,AS;

        wire [`REG_SIZE:0] Atemp,Btemp,Btemp1,Stemp;
        reg [`REG_SIZE:0] CIN;
        wire Y_1,Y_2,Y_3,Y_4;

        assign Y_1 = (~AS) & Asign;

        BusMux2_1 MUX_0 (Atemp,A,B,Y_1);
        BusMux2_1 MUX_1 (Btemp,B,A,Y_1);

        assign Y_2 = Asign ^ AS;

        integer i;
always @ (Y_2)
        begin
                for(i=0;i<`REG_SIZE+1;i=i+1)
                CIN[i] <= Y_2;
        end
        assign Btemp1 = Btemp ^ CIN;

        RCA Add (Stemp,Y_3,Atemp,Btemp1,Y_2);

        assign Y_4 = (~Y_3) & (Asign ^ AS);

        complement Compl (S,Stemp,Y_4);
        assign sign = (~Y_3 & AS) | (~Y_3 & Asign) | (AS & Asign);

endmodule
module Adder (S, sign, Asign, A, B, AS);

        output [`REG_SIZE:0] S;
        output sign;
        input [`REG_SIZE:0] A,B;
        input Asign,AS;

        wire [`REG_SIZE:0] Atemp,Btemp,Btemp1,Stemp;
        reg [`REG_SIZE:0] CIN;
        wire Y_1,Y_2,Y_3,Y_4;

        assign Y_1 = (~AS) & Asign;

        BusMux2_1 MUX_0 (Atemp,A,B,Y_1);
        BusMux2_1 MUX_1 (Btemp,B,A,Y_1);

        assign Y_2 = Asign ^ AS;

        integer i;
always @ (Y_2)
        begin
                for(i=0;i<`REG_SIZE+1;i=i+1)
                CIN[i] <= Y_2;
        end
        assign Btemp1 = Btemp ^ CIN;

        RCA Add (Stemp,Y_3,Atemp,Btemp1,Y_2);

        assign Y_4 = (~Y_3) & (Asign ^ AS);

        complement Compl (S,Stemp,Y_4);
        assign sign = (~Y_3 & AS) | (~Y_3 & Asign) | (AS & Asign);

endmodule