data/full_repos/permissive/19478345/multistage_interconnect_network/multistage_interconnect_network_synthesis.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/19478345/multistage_interconnect_network/multistage_interconnect_network_synthesis.v:4: Little bit endian vector: MSB < LSB of bit range: 0:7\n    wire [0:7] push;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/19478345/multistage_interconnect_network/multistage_interconnect_network_synthesis.v:6: Little bit endian vector: MSB < LSB of bit range: 0:7\n    wire [0:7] valid; \n         ^\n%Error: data/full_repos/permissive/19478345/multistage_interconnect_network/multistage_interconnect_network_synthesis.v:10: Cannot find file containing module: \'multistage_interconnect_network\'\n    multistage_interconnect_network dut(clk, push, d_in, valid, d_out, control);\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19478345/multistage_interconnect_network,data/full_repos/permissive/19478345/multistage_interconnect_network\n             data/full_repos/permissive/19478345/multistage_interconnect_network,data/full_repos/permissive/19478345/multistage_interconnect_network.v\n             data/full_repos/permissive/19478345/multistage_interconnect_network,data/full_repos/permissive/19478345/multistage_interconnect_network.sv\n             multistage_interconnect_network\n             multistage_interconnect_network.v\n             multistage_interconnect_network.sv\n             obj_dir/multistage_interconnect_network\n             obj_dir/multistage_interconnect_network.v\n             obj_dir/multistage_interconnect_network.sv\n%Warning-LITENDIAN: data/full_repos/permissive/19478345/multistage_interconnect_network/multistage_interconnect_network_synthesis.v:12: Little bit endian vector: MSB < LSB of bit range: 0:1035\n    reg [0:8+16*64+4-1] input_reg;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/19478345/multistage_interconnect_network/multistage_interconnect_network_synthesis.v:13: Little bit endian vector: MSB < LSB of bit range: 0:1031\n    reg [0:8+16*64-1] output_reg;\n        ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module multistage_interconnect_network_synthesis(clk, in, out, sel);
    input clk, in, sel;
    output reg out;
    wire [0:7] push;
    wire [16*64-1:0] d_in;
    wire [0:7] valid; 
    wire [64*16-1:0] d_out;
    wire [3:0] control;

    multistage_interconnect_network dut(clk, push, d_in, valid, d_out, control);

    reg [0:8+16*64+4-1] input_reg;
    reg [0:8+16*64-1] output_reg;
    assign push = input_reg[0:7];
    assign d_in = input_reg[8:8+16*64-1];
    assign control = input_reg[8+16*64:16*64+8+4-1];
    always @(posedge clk) begin
        input_reg[0] <= in;
        input_reg[1:8+16*64+4-1] <= input_reg[0:8+16*64+4-2];
        if(sel) begin
            out <= output_reg[8+16*64-1];
            output_reg[1:8+16*64-1] <= output_reg[0:8+16*64-2];
        end else begin
            output_reg[0:7] <= valid;
            output_reg[8:8+16*64-1] <= d_out;
        end
        
    end


endmodule
module multistage_interconnect_network_synthesis(clk, in, out, sel);

    input clk, in, sel;
    output reg out;
    wire [0:7] push;
    wire [16*64-1:0] d_in;
    wire [0:7] valid; 
    wire [64*16-1:0] d_out;
    wire [3:0] control;

    multistage_interconnect_network dut(clk, push, d_in, valid, d_out, control);

    reg [0:8+16*64+4-1] input_reg;
    reg [0:8+16*64-1] output_reg;
    assign push = input_reg[0:7];
    assign d_in = input_reg[8:8+16*64-1];
    assign control = input_reg[8+16*64:16*64+8+4-1];
    always @(posedge clk) begin
        input_reg[0] <= in;
        input_reg[1:8+16*64+4-1] <= input_reg[0:8+16*64+4-2];
        if(sel) begin
            out <= output_reg[8+16*64-1];
            output_reg[1:8+16*64-1] <= output_reg[0:8+16*64-2];
        end else begin
            output_reg[0:7] <= valid;
            output_reg[8:8+16*64-1] <= d_out;
        end
        
    end


endmodule