data/full_repos/permissive/208358418/iverilog_tutorial/code_samples/simple_tb.v
 line:18: before: "$"
1: b'%Error: data/full_repos/permissive/208358418/iverilog_tutorial/code_samples/simple_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("simple.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/208358418/iverilog_tutorial/code_samples/simple_tb.v:12: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, s);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/208358418/iverilog_tutorial/code_samples/simple_tb.v:13: Unsupported or unknown PLI call: $monitor\n        $monitor("A is %b, B is %b.", A, B);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/208358418/iverilog_tutorial/code_samples/simple_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #50 A = 4\'b1100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/208358418/iverilog_tutorial/code_samples/simple_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #100 A = 4\'b0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/208358418/iverilog_tutorial/code_samples/simple_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish;\n        ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simple_tb;


   reg [3:0] A = 4'b1010;
   wire [3:0] B;

   initial
     begin

        $dumpfile("simple.vcd");

        $dumpvars(0, s);
        $monitor("A is %b, B is %b.", A, B);


        #50 A = 4'b1100;
        #100 A = 4'b0000;
        #100 $finish;
     end


   simple s(A, B);
endmodule
module simple_tb;



   reg [3:0] A = 4'b1010;
   wire [3:0] B;

   initial
     begin

        $dumpfile("simple.vcd");

        $dumpvars(0, s);
        $monitor("A is %b, B is %b.", A, B);


        #50 A = 4'b1100;
        #100 A = 4'b0000;
        #100 $finish;
     end


   simple s(A, B);
endmodule