data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder_1/rtl/rs_decoder_1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder_1/rtl/rs_decoder_1.v:551: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 4 bits.\n                                                                                                                                  : ... In instance rs_decoder_1.x1\n   if ((phase0 & delta) && (count != -1)) L <= count - L + 1;\n                                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder_1/rtl/rs_decoder_1.v:148: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s OR generates 5 bits.\n                                                                                                                                  : ... In instance rs_decoder_1\n assign temp = syn_shift && (s0 | s1 | s2 | s3 | s4 | s5 | s6 | s7 | s8 | s9 | s10 | s11);\n                         ^~\n%Error: Exiting due to 2 warning(s)\n'
module rsdec_syn_m1 (y, x);
	input [4:0] x;
	output [4:0] y;
	reg [4:0] y;
	always @ (x)
	begin
		y[0] = x[3];
		y[1] = x[4];
		y[2] = x[0] ^ x[3];
		y[3] = x[1] ^ x[4];
		y[4] = x[2];
	end
endmodule
module rsdec_syn_m1 (y, x);

	input [4:0] x;
	output [4:0] y;
	reg [4:0] y;
	always @ (x)
	begin
		y[0] = x[3];
		y[1] = x[4];
		y[2] = x[0] ^ x[3];
		y[3] = x[1] ^ x[4];
		y[4] = x[2];
	end
endmodule