data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #5 C = !C;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #30 D = !D;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #2 CLR = CLEAR_VAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #2 CLR = ~CLEAR_VAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #40 CLR = CLEAR_VAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #2  CLR = ~CLEAR_VAL;\n        ^\n%Error: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/d_trig_testbench.v:23: Cannot find file containing module: \'d_trig\'\n    d_trig #(\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation,data/full_repos/permissive/110143902/d_trig\n             data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation,data/full_repos/permissive/110143902/d_trig.v\n             data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation,data/full_repos/permissive/110143902/d_trig.sv\n             d_trig\n             d_trig.v\n             d_trig.sv\n             obj_dir/d_trig\n             obj_dir/d_trig.v\n             obj_dir/d_trig.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module d_trig_testbench ( );

    parameter reg CLEAR_DATA  = 0;
    parameter     CLEAR_VAL   = 1;

    reg D, DCLR, C, CLR;
    wire Q, notQ;

    d_trig #(
        .CLEAR_VAL(CLEAR_VAL)
    )
    d_trig_i (
        .D(D),
        .DCLR(CLEAR_DATA),
        .C(C),
        .CLR(CLR),
        .Q(Q),
        .notQ(notQ)
    );


    always
        #5 C = !C;


    always
        #30 D = !D;


    initial begin
        D = 0;
        C = 0;
        CLR = ~CLEAR_VAL;


        #2 CLR = CLEAR_VAL;
        #2 CLR = ~CLEAR_VAL;

        #40 CLR = CLEAR_VAL;
        #2  CLR = ~CLEAR_VAL;
    end

endmodule
module d_trig_testbench ( );


    parameter reg CLEAR_DATA  = 0;
    parameter     CLEAR_VAL   = 1;

    reg D, DCLR, C, CLR;
    wire Q, notQ;

    d_trig #(
        .CLEAR_VAL(CLEAR_VAL)
    )
    d_trig_i (
        .D(D),
        .DCLR(CLEAR_DATA),
        .C(C),
        .CLR(CLR),
        .Q(Q),
        .notQ(notQ)
    );


    always
        #5 C = !C;


    always
        #30 D = !D;


    initial begin
        D = 0;
        C = 0;
        CLR = ~CLEAR_VAL;


        #2 CLR = CLEAR_VAL;
        #2 CLR = ~CLEAR_VAL;

        #40 CLR = CLEAR_VAL;
        #2  CLR = ~CLEAR_VAL;
    end

endmodule