data/full_repos/permissive/160437780/Source/freqControl.v
 line:8: before: "="
1: b'%Error: data/full_repos/permissive/160437780/Source/freqControl.v:19: Cannot find file containing module: \'getFreq\'\ngetFreq getFq(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160437780/Source,data/full_repos/permissive/160437780/getFreq\n             data/full_repos/permissive/160437780/Source,data/full_repos/permissive/160437780/getFreq.v\n             data/full_repos/permissive/160437780/Source,data/full_repos/permissive/160437780/getFreq.sv\n             getFreq\n             getFreq.v\n             getFreq.sv\n             obj_dir/getFreq\n             obj_dir/getFreq.v\n             obj_dir/getFreq.sv\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/freqControl.v:32: Operator ASSIGNDLY expects 27 bits on the Assign RHS, but Assign RHS\'s VARREF \'frequency\' generates 20 bits.\n                                                                            : ... In instance freqControl\n        result <= frequency;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module freqControl(
input CLK100MHZ,                                        
input signal,                                         
output reg [5:0] counter = 0,                                 
output reg [15:0] freq = 0

    );
    wire [19:0] frequency;
    reg [19:0] pastFrequency = 0;
    reg [5:0] c_counter = 0;
    reg [5:0] fAVG_counter = 0;
    reg beginCalc = 0;
    reg [26:0] result = 0;
    wire [19:0] frequencyAVG; 
getFreq getFq(
.CLK100MHZ(CLK100MHZ),
.signal(signal),
.frequency(frequency)
);




always @ (posedge CLK100MHZ) begin
    
    if (pastFrequency != frequency) begin

        result <= frequency;
        pastFrequency <= frequency;
        beginCalc <= 1;
    end else begin
            c_counter <= c_counter;
            pastFrequency <= frequency;
            beginCalc <= beginCalc;
        end
    
    if(beginCalc) begin
    
    end    

    case(1)
        1: begin counter <= c_counter[5:0]; freq <= frequency[19:4]; end
    endcase

end


endmodule
module freqControl(
input CLK100MHZ,                                        
input signal,                                         
output reg [5:0] counter = 0,                                 
output reg [15:0] freq = 0

    );

    wire [19:0] frequency;
    reg [19:0] pastFrequency = 0;
    reg [5:0] c_counter = 0;
    reg [5:0] fAVG_counter = 0;
    reg beginCalc = 0;
    reg [26:0] result = 0;
    wire [19:0] frequencyAVG; 
getFreq getFq(
.CLK100MHZ(CLK100MHZ),
.signal(signal),
.frequency(frequency)
);




always @ (posedge CLK100MHZ) begin
    
    if (pastFrequency != frequency) begin

        result <= frequency;
        pastFrequency <= frequency;
        beginCalc <= 1;
    end else begin
            c_counter <= c_counter;
            pastFrequency <= frequency;
            beginCalc <= beginCalc;
        end
    
    if(beginCalc) begin
    
    end    

    case(1)
        1: begin counter <= c_counter[5:0]; freq <= frequency[19:4]; end
    endcase

end


endmodule