data/full_repos/permissive/202237519/verilog/digitalsystem6/reg.v
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem6/reg.v:1: Cannot find include file: d_ff.v\n`include "d_ff.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/d_ff.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/d_ff.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem6,data/full_repos/permissive/202237519/d_ff.v.sv\n             d_ff.v\n             d_ff.v.v\n             d_ff.v.sv\n             obj_dir/d_ff.v\n             obj_dir/d_ff.v.v\n             obj_dir/d_ff.v.sv\n%Error: Exiting due to 1 error(s)\n'
module register(CLK, SI, SO);
   input SI, CLK;
   output [3:0] SO;
   wire[3:0] SO;
   D_FF F1(.CLK(CLK), .D(SI), .set(1'b0),.Q(SO[0]), .nQ());
   D_FF F2(.CLK(CLK), .D(SO[0]),.set(1'b0), .Q(SO[1]), .nQ());
   D_FF F3(.CLK(CLK), .D(SO[1]),.set(1'b0), .Q(SO[2]), .nQ());
   D_FF F4(.CLK(CLK), .D(SO[2]),.set(1'b0), .Q(SO[3]), .nQ());
endmodule
module register(CLK, SI, SO);

   input SI, CLK;
   output [3:0] SO;
   wire[3:0] SO;
   D_FF F1(.CLK(CLK), .D(SI), .set(1'b0),.Q(SO[0]), .nQ());
   D_FF F2(.CLK(CLK), .D(SO[0]),.set(1'b0), .Q(SO[1]), .nQ());
   D_FF F3(.CLK(CLK), .D(SO[1]),.set(1'b0), .Q(SO[2]), .nQ());
   D_FF F4(.CLK(CLK), .D(SO[2]),.set(1'b0), .Q(SO[3]), .nQ());
endmodule