data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15m.v
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15m.v:112: Cannot find file containing module: 'mfsr4'\n mfsr4 MFSR0 (\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo,data/full_repos/permissive/20430511/mfsr4\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo,data/full_repos/permissive/20430511/mfsr4.v\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo,data/full_repos/permissive/20430511/mfsr4.sv\n             mfsr4\n             mfsr4.v\n             mfsr4.sv\n             obj_dir/mfsr4\n             obj_dir/mfsr4.v\n             obj_dir/mfsr4.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo15m.v:118: Cannot find file containing module: 'mfsr4'\n mfsr4 MFSR1 (\n ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module fifo15m (
		read_clock_i,
		write_clock_i,
		reset_i,
		read_i,
		write_i,
		data_i,
		data_o,
		almost_full_o,
		almost_empty_o,
		not_empty_o
	);
	

	parameter	FIFO_WIDTH	= 8'd16;
	
	input	read_clock_i;
	input	write_clock_i;
	input	reset_i;
	input	read_i;
	input	write_i;
	input	[FIFO_WIDTH - 1:0]	data_i;
	output	[FIFO_WIDTH - 1:0]	data_o;
	output	almost_full_o;
	output	almost_empty_o;
	output	not_empty_o;
	
	

	reg	[3:0]	f_start	= 4'h1;
	reg	[3:0]	f_end	= 4'h1;
	wire	[3:0]	f_start_w, f_end_w;
	
	

	assign	almost_full_o	= (f_start == f_end_w);
	assign	almost_empty_o	= (f_start_w == f_end);
	assign	not_empty_o		= (f_start != f_end);
	
	

	always @(posedge read_clock_i)
	begin
		if (reset_i)
			f_start	<= 4'b1;
		else
		begin
			if (read_i)
				f_start	<= f_start_w;
			else
				f_start	<= f_start;
		end
	end
	
	

	always @(posedge write_clock_i)
	begin
		if (reset_i)
			f_end	<= 4'b1;
		else
		begin
			if (write_i)
				f_end	<= f_end_w;
			else
				f_end	<= f_end;
		end
	end
	

	reg    [FIFO_WIDTH - 1:0]  mem[0:15];
	
	always @ (posedge write_clock_i)
	begin
		if (write_i)
		begin
			mem[f_end]  <= data_i;  
		end
	end
	
	assign data_o = mem[f_start];
	
	
	

	mfsr4 MFSR0 (
		.count_i (f_start),
		.count_o (f_start_w)
	);
	

	mfsr4 MFSR1 (
		.count_i (f_end),
		.count_o (f_end_w)
	);
	
	



`ifdef __icarus
	initial begin : Init
		init_mem (0);
	end
	
	
	task init_mem;
		input	val;
		integer	val, n;
	begin : Init_Mem
		for (n = 0; n < 16; n = n + 1)
			mem[n]	= val;
	end
	endtask
`endif
	
	
endmodule
module fifo15m (
		read_clock_i,
		write_clock_i,
		reset_i,
		read_i,
		write_i,
		data_i,
		data_o,
		almost_full_o,
		almost_empty_o,
		not_empty_o
	);

	

	parameter	FIFO_WIDTH	= 8'd16;
	
	input	read_clock_i;
	input	write_clock_i;
	input	reset_i;
	input	read_i;
	input	write_i;
	input	[FIFO_WIDTH - 1:0]	data_i;
	output	[FIFO_WIDTH - 1:0]	data_o;
	output	almost_full_o;
	output	almost_empty_o;
	output	not_empty_o;
	
	

	reg	[3:0]	f_start	= 4'h1;
	reg	[3:0]	f_end	= 4'h1;
	wire	[3:0]	f_start_w, f_end_w;
	
	

	assign	almost_full_o	= (f_start == f_end_w);
	assign	almost_empty_o	= (f_start_w == f_end);
	assign	not_empty_o		= (f_start != f_end);
	
	

	always @(posedge read_clock_i)
	begin
		if (reset_i)
			f_start	<= 4'b1;
		else
		begin
			if (read_i)
				f_start	<= f_start_w;
			else
				f_start	<= f_start;
		end
	end
	
	

	always @(posedge write_clock_i)
	begin
		if (reset_i)
			f_end	<= 4'b1;
		else
		begin
			if (write_i)
				f_end	<= f_end_w;
			else
				f_end	<= f_end;
		end
	end
	

	reg    [FIFO_WIDTH - 1:0]  mem[0:15];
	
	always @ (posedge write_clock_i)
	begin
		if (write_i)
		begin
			mem[f_end]  <= data_i;  
		end
	end
	
	assign data_o = mem[f_start];
	
	
	

	mfsr4 MFSR0 (
		.count_i (f_start),
		.count_o (f_start_w)
	);
	

	mfsr4 MFSR1 (
		.count_i (f_end),
		.count_o (f_end_w)
	);
	
	



`ifdef __icarus
	initial begin : Init
		init_mem (0);
	end
	
	
	task init_mem;
		input	val;
		integer	val, n;
	begin : Init_Mem
		for (n = 0; n < 16; n = n + 1)
			mem[n]	= val;
	end
	endtask
`endif
	
	
endmodule