data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/data1.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/data1.v:1: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu,data/full_repos/permissive/131921633/Mips/Type/Word.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu,data/full_repos/permissive/131921633/Mips/Type/Word.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu,data/full_repos/permissive/131921633/Mips/Type/Word.v.sv\n             Mips/Type/Word.v\n             Mips/Type/Word.v.v\n             Mips/Type/Word.v.sv\n             obj_dir/Mips/Type/Word.v\n             obj_dir/Mips/Type/Word.v.v\n             obj_dir/Mips/Type/Word.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/data1.v:3: Cannot find include file: Mips/Control/Signal/Alu/Signal/Data1Source.v\n`include "Mips/Control/Signal/Alu/Signal/Data1Source.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/data1.v:6: Define or directive not defined: \'`Mips_Control_Signal_Alu_Signal_Data1Source_T\'\n ( `Mips_Control_Signal_Alu_Signal_Data1Source_T (input) control\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/data1.v:6: syntax error, unexpected \'(\', expecting \'[\'\n ( `Mips_Control_Signal_Alu_Signal_Data1Source_T (input) control\n                                                  ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/data1.v:7: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (input) shamt\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/data1.v:8: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (input) regPort1\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/data1.v:9: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T (output) data1\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/data1.v:12: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (reg) data1$ ;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/data1.v:15: Define or directive not defined: \'`Mips_Control_Signal_Alu_Signal_Data1Source_Shamt\'\n  `Mips_Control_Signal_Alu_Signal_Data1Source_Shamt     : data1$ = shamt;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Alu/data1.v:16: Define or directive not defined: \'`Mips_Control_Signal_Alu_Signal_Data1Source_Register\'\n  `Mips_Control_Signal_Alu_Signal_Data1Source_Register  : data1$ = regPort1;\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n'
module Mips_Datapath_Alu_data1
	( `Mips_Control_Signal_Alu_Signal_Data1Source_T (input) control
	, `Mips_Type_Word_T (input) shamt
	, `Mips_Type_Word_T (input) regPort1
	, `Mips_Type_Word_T (output) data1
	);

`Mips_Type_Word_T (reg) data1$ ;
always @(*)
	case(control)
		`Mips_Control_Signal_Alu_Signal_Data1Source_Shamt     : data1$ = shamt;
		`Mips_Control_Signal_Alu_Signal_Data1Source_Register  : data1$ = regPort1;
		default                                               : data1$ = regPort1;
	endcase
assign data1 = data1$;

endmodule
module Mips_Datapath_Alu_data1
	( `Mips_Control_Signal_Alu_Signal_Data1Source_T (input) control
	, `Mips_Type_Word_T (input) shamt
	, `Mips_Type_Word_T (input) regPort1
	, `Mips_Type_Word_T (output) data1
	);


`Mips_Type_Word_T (reg) data1$ ;
always @(*)
	case(control)
		`Mips_Control_Signal_Alu_Signal_Data1Source_Shamt     : data1$ = shamt;
		`Mips_Control_Signal_Alu_Signal_Data1Source_Register  : data1$ = regPort1;
		default                                               : data1$ = regPort1;
	endcase
assign data1 = data1$;

endmodule