data/full_repos/permissive/126791278/MemoryDataRegister.v
data/verilator_xmls/1d768b93-c2ac-4275-981c-c92a45de8fce.xml
module memoryDataRegister(MDR_OUT, MDR_IN, clk);
	
	output reg [15:0] MDR_OUT;
	
	input wire [15:0] MDR_IN;
	input wire clk;
	
	always@(posedge clk)
	begin
		MDR_OUT <= MDR_IN;
	end
endmodule
module memoryDataRegister(MDR_OUT, MDR_IN, clk);

	
	output reg [15:0] MDR_OUT;
	
	input wire [15:0] MDR_IN;
	input wire clk;
	
	always@(posedge clk)
	begin
		MDR_OUT <= MDR_IN;
	end
endmodule