data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl/dual_dma_v1_0_M_AXIS.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-SELRANGE: data/full_repos/permissive/135295301/common/ip/dual_dma_1.0/hdl/dual_dma_v1_0_M_AXIS.v:182: Selection index out of range: 63:32 outside 31:0\n                                                                                                             : ... In instance dual_dma_v1_0_M_AXIS\n        write_counter <= cmd_write_str_m_axis_tdata[63:32];\n                                                   ^\n                   ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module dual_dma_v1_0_M_AXIS #
	(


		parameter integer C_M_AXI_CMD_STR_WIDTH	= 32,
		parameter integer C_M_AXI_STS_STR_WIDTH	= 32,
		parameter integer C_M_AXIS_BURST_LEN	= 16,





		parameter integer C_M_AXIS_TDATA_WIDTH	= 32,

		parameter integer C_M_START_COUNT	= 32
	)
	(



		input wire cmd_write_str_m_axis_tvalid,
		output reg cmd_write_str_m_axis_tready,
		input wire [C_M_AXI_CMD_STR_WIDTH - 1 : 0] cmd_write_str_m_axis_tdata,



		output reg sts_write_str_s_axis_tvalid,
		input wire sts_write_str_s_axis_tready,
		output reg [C_M_AXI_STS_STR_WIDTH - 1 : 0] sts_write_str_s_axis_tdata,


		output reg ul_axi_wready,
		input wire ul_axi_wvalid,
		input wire ul_axi_wlast,





		input wire  M_AXIS_ACLK,

		input wire  M_AXIS_ARESETN,

		output reg  M_AXIS_TVALID,





		output reg  M_AXIS_TLAST,

		input wire  M_AXIS_TREADY
	);                                              
	                                                                                     


	function integer clogb2 (input integer bit_depth);                                   
	  begin                                                                              
	    for(clogb2=0; bit_depth>0; clogb2=clogb2+1)                                      
	      bit_depth = bit_depth >> 1;                                                    
	  end                                                                                
	endfunction                                              



	localparam integer BYTES_PER_BEAT = C_M_AXIS_TDATA_WIDTH/8;
	localparam integer BYTES_PER_BURST = C_M_AXIS_BURST_LEN*BYTES_PER_BEAT;


	localparam integer STATE_BIT_WIDTH 		= 4;
	localparam [STATE_BIT_WIDTH - 1 : 0] IDLE 	= 4'b0001;
	localparam [STATE_BIT_WIDTH - 1 : 0] BURST 	= 4'b0010;
	localparam [STATE_BIT_WIDTH - 1 : 0] WAIT 	= 4'b0100;
	localparam [STATE_BIT_WIDTH - 1 : 0] DONE 	= 4'b1000;

	reg  [STATE_BIT_WIDTH - 1 : 0] 		state_write;
	reg  [STATE_BIT_WIDTH - 1 : 0] 		next_state_write;

	reg load_write_registers;
	reg [31 : 0] write_counter;



	always @( posedge M_AXIS_ACLK )
	begin
	  if ( M_AXIS_ARESETN == 1'b0 )
		begin
		    state_write <= IDLE;
		end
	  else
		begin
		    state_write <= next_state_write;
		end
	end



	always @( * )
	begin
	    load_write_registers = 1'b0;
	    cmd_write_str_m_axis_tready = 1'b0;
	    sts_write_str_s_axis_tvalid = 1'b0;
	    ul_axi_wready = 1'b0;
	    M_AXIS_TVALID = 1'b0;

	    case(state_write)
		IDLE:
		    begin
			if(cmd_write_str_m_axis_tvalid == 1'b1)
			    begin				
	    			cmd_write_str_m_axis_tready = 1'b1;			
	    			load_write_registers = 1'b1;
				next_state_write = WAIT;
			    end
			else
			    begin
		    		next_state_write = IDLE;
			    end
		    end
		WAIT:
		    begin
			if(write_counter == 0)
			    begin
				next_state_write = DONE;
			    end
			else
			    begin
		    		ul_axi_wready = M_AXIS_TREADY;
		    		M_AXIS_TVALID = ul_axi_wvalid;
		    		next_state_write = WAIT;
			    end
		    end
		DONE:
		    begin
			if(sts_write_str_s_axis_tready == 1'b1)
			    begin				
	    			sts_write_str_s_axis_tvalid = 1'b1;
				next_state_write = IDLE;
			    end
			else
			    begin
		    		next_state_write = WAIT;
			    end
		    end
		default:
		    next_state_write = IDLE;
	    endcase
	end


	  always @(posedge M_AXIS_ACLK)
	  begin
	    if (M_AXIS_ARESETN == 0)
	      begin
	        write_counter <= 0;
	      end
	    else
		if(load_write_registers == 1'b1)
		   begin
		      sts_write_str_s_axis_tdata <= cmd_write_str_m_axis_tdata[31:0];
		      write_counter <= cmd_write_str_m_axis_tdata[63:32];
		   end
		else if(M_AXIS_TVALID && M_AXIS_TREADY && write_counter >= BYTES_PER_BEAT)
		   begin
		      write_counter <= write_counter - BYTES_PER_BEAT;
		   end
		else if(M_AXIS_TVALID && M_AXIS_TREADY && write_counter < BYTES_PER_BEAT)
		   begin
		      write_counter <= 0;
		   end
	  end


	  always @(*)
	  begin
	    if(write_counter > 0 && write_counter <= BYTES_PER_BEAT)
		M_AXIS_TLAST = 1'b1;
	    else
		M_AXIS_TLAST = 1'b0;
	  end



	endmodule
module dual_dma_v1_0_M_AXIS #
	(


		parameter integer C_M_AXI_CMD_STR_WIDTH	= 32,
		parameter integer C_M_AXI_STS_STR_WIDTH	= 32,
		parameter integer C_M_AXIS_BURST_LEN	= 16,





		parameter integer C_M_AXIS_TDATA_WIDTH	= 32,

		parameter integer C_M_START_COUNT	= 32
	)
	(



		input wire cmd_write_str_m_axis_tvalid,
		output reg cmd_write_str_m_axis_tready,
		input wire [C_M_AXI_CMD_STR_WIDTH - 1 : 0] cmd_write_str_m_axis_tdata,



		output reg sts_write_str_s_axis_tvalid,
		input wire sts_write_str_s_axis_tready,
		output reg [C_M_AXI_STS_STR_WIDTH - 1 : 0] sts_write_str_s_axis_tdata,


		output reg ul_axi_wready,
		input wire ul_axi_wvalid,
		input wire ul_axi_wlast,





		input wire  M_AXIS_ACLK,

		input wire  M_AXIS_ARESETN,

		output reg  M_AXIS_TVALID,





		output reg  M_AXIS_TLAST,

		input wire  M_AXIS_TREADY
	);
                                              
	                                                                                     


	function integer clogb2 (input integer bit_depth);                                   
	  begin                                                                              
	    for(clogb2=0; bit_depth>0; clogb2=clogb2+1)                                      
	      bit_depth = bit_depth >> 1;                                                    
	  end                                                                                
	endfunction                                              



	localparam integer BYTES_PER_BEAT = C_M_AXIS_TDATA_WIDTH/8;
	localparam integer BYTES_PER_BURST = C_M_AXIS_BURST_LEN*BYTES_PER_BEAT;


	localparam integer STATE_BIT_WIDTH 		= 4;
	localparam [STATE_BIT_WIDTH - 1 : 0] IDLE 	= 4'b0001;
	localparam [STATE_BIT_WIDTH - 1 : 0] BURST 	= 4'b0010;
	localparam [STATE_BIT_WIDTH - 1 : 0] WAIT 	= 4'b0100;
	localparam [STATE_BIT_WIDTH - 1 : 0] DONE 	= 4'b1000;

	reg  [STATE_BIT_WIDTH - 1 : 0] 		state_write;
	reg  [STATE_BIT_WIDTH - 1 : 0] 		next_state_write;

	reg load_write_registers;
	reg [31 : 0] write_counter;



	always @( posedge M_AXIS_ACLK )
	begin
	  if ( M_AXIS_ARESETN == 1'b0 )
		begin
		    state_write <= IDLE;
		end
	  else
		begin
		    state_write <= next_state_write;
		end
	end



	always @( * )
	begin
	    load_write_registers = 1'b0;
	    cmd_write_str_m_axis_tready = 1'b0;
	    sts_write_str_s_axis_tvalid = 1'b0;
	    ul_axi_wready = 1'b0;
	    M_AXIS_TVALID = 1'b0;

	    case(state_write)
		IDLE:
		    begin
			if(cmd_write_str_m_axis_tvalid == 1'b1)
			    begin				
	    			cmd_write_str_m_axis_tready = 1'b1;			
	    			load_write_registers = 1'b1;
				next_state_write = WAIT;
			    end
			else
			    begin
		    		next_state_write = IDLE;
			    end
		    end
		WAIT:
		    begin
			if(write_counter == 0)
			    begin
				next_state_write = DONE;
			    end
			else
			    begin
		    		ul_axi_wready = M_AXIS_TREADY;
		    		M_AXIS_TVALID = ul_axi_wvalid;
		    		next_state_write = WAIT;
			    end
		    end
		DONE:
		    begin
			if(sts_write_str_s_axis_tready == 1'b1)
			    begin				
	    			sts_write_str_s_axis_tvalid = 1'b1;
				next_state_write = IDLE;
			    end
			else
			    begin
		    		next_state_write = WAIT;
			    end
		    end
		default:
		    next_state_write = IDLE;
	    endcase
	end


	  always @(posedge M_AXIS_ACLK)
	  begin
	    if (M_AXIS_ARESETN == 0)
	      begin
	        write_counter <= 0;
	      end
	    else
		if(load_write_registers == 1'b1)
		   begin
		      sts_write_str_s_axis_tdata <= cmd_write_str_m_axis_tdata[31:0];
		      write_counter <= cmd_write_str_m_axis_tdata[63:32];
		   end
		else if(M_AXIS_TVALID && M_AXIS_TREADY && write_counter >= BYTES_PER_BEAT)
		   begin
		      write_counter <= write_counter - BYTES_PER_BEAT;
		   end
		else if(M_AXIS_TVALID && M_AXIS_TREADY && write_counter < BYTES_PER_BEAT)
		   begin
		      write_counter <= 0;
		   end
	  end


	  always @(*)
	  begin
	    if(write_counter > 0 && write_counter <= BYTES_PER_BEAT)
		M_AXIS_TLAST = 1'b1;
	    else
		M_AXIS_TLAST = 1'b0;
	  end



	endmodule