data/full_repos/permissive/197806087/vga/vgaimproved/timer.v
1: b"%Error: data/full_repos/permissive/197806087/vga/vgaimproved/timer.v:24: Cannot find file containing module: 'frame_buffer'\n    frame_buffer #(.H_WIDTH(H_WIDTH), .V_WIDTH(V_WIDTH), .R_DEPTH(R_DEPTH),\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197806087/vga/vgaimproved,data/full_repos/permissive/197806087/frame_buffer\n             data/full_repos/permissive/197806087/vga/vgaimproved,data/full_repos/permissive/197806087/frame_buffer.v\n             data/full_repos/permissive/197806087/vga/vgaimproved,data/full_repos/permissive/197806087/frame_buffer.sv\n             frame_buffer\n             frame_buffer.v\n             frame_buffer.sv\n             obj_dir/frame_buffer\n             obj_dir/frame_buffer.v\n             obj_dir/frame_buffer.sv\n%Error: Exiting due to 1 error(s)\n"
module counter #(parameter H_WIDTH = 200, V_WIDTH = 600, HF_PORCH = 10, 
                 H_PULSE = 32, HB_PORCH = 22, VF_PORCH = 1, V_PULSE = 4, 
                 VB_PORCH = 23, R_DEPTH = 2, G_DEPTH = 2, B_DEPTH = 2) (
        input wire clk,

        output wire h_sync_pulse,
        output wire v_sync_pulse,
        output reg [R_DEPTH - 1:0] R,
        output reg [G_DEPTH - 1:0] G,
        output reg [B_DEPTH - 1:0] B
        );
    localparam H_BITS = $clog2(H_WIDTH + HF_PORCH + H_PULSE + HB_PORCH),
            V_BITS = $clog2(V_WIDTH + VF_PORCH + V_PULSE + VB_PORCH);
    reg h_porch = 0;
    reg pre_h_porch = 0;
    reg h_sync = 1;
    assign h_sync_pulse = ~h_sync;
    reg v_porch = 0;
    reg v_sync = 1;
    assign v_sync_pulse = ~v_sync;
    reg [H_BITS - 1:0] h_count = 0;
    reg [V_BITS - 1:0] v_count = 0;
    wire [R_DEPTH + G_DEPTH + B_DEPTH - 1:0] color_out;
    frame_buffer #(.H_WIDTH(H_WIDTH), .V_WIDTH(V_WIDTH), .R_DEPTH(R_DEPTH),
                   .G_DEPTH(G_DEPTH), .B_DEPTH(B_DEPTH))
            f1(.clk(clk), .pre_h_porch(pre_h_porch), .h_porch(h_porch), .h_index(h_count), 
            .v_index(v_count), .color_out(color_out));



    always @(posedge clk) begin
        R <= color_out[5:4];
        G <= color_out[3:2];
        B <= color_out[1:0];
        h_count <= h_count + 1'b1;
        if (h_count >= H_WIDTH - 2) begin
            pre_h_porch <= 1;
        end
        if (h_count >= H_WIDTH - 1) begin
            h_porch <= 1;
            if (h_count >= H_WIDTH + HF_PORCH - 1 && h_count < H_WIDTH + HF_PORCH + H_PULSE - 1) begin
                h_sync <= 0;
            end
            if (h_count >= H_WIDTH + HF_PORCH + H_PULSE - 1) begin
                h_sync <= 1;
            end
            if (h_count == H_WIDTH + HF_PORCH + H_PULSE + HB_PORCH - 2) begin
                pre_h_porch <= 0;
            end
            if (h_count == H_WIDTH + HF_PORCH + H_PULSE + HB_PORCH - 1) begin
                h_count <= 0;
                h_porch <= 0;
                h_sync <= 1;
                pre_h_porch <= 0;
            end
        end
        else begin
            h_sync <= 1;
        end
    end

    always @(negedge h_porch) begin
        v_count <= v_count + 1'b1;
        if (v_count >= V_WIDTH - 1) begin
            v_porch <= 1;
            if (v_count >= V_WIDTH + VF_PORCH - 1 && v_count < V_WIDTH + VF_PORCH + V_PULSE - 1) begin
                v_sync <= 0;
            end
            if (v_count >= V_WIDTH + VF_PORCH + V_PULSE - 1) begin
                v_sync <= 1;
            end
            if (v_count == V_WIDTH + VF_PORCH + V_PULSE + VB_PORCH - 1) begin
                v_count <= 0;
                v_porch <= 0;
                v_sync <= 1;
            end
        end
        else begin
            v_sync <= 1;
        end
    end
endmodule
module counter #(parameter H_WIDTH = 200, V_WIDTH = 600, HF_PORCH = 10, 
                 H_PULSE = 32, HB_PORCH = 22, VF_PORCH = 1, V_PULSE = 4, 
                 VB_PORCH = 23, R_DEPTH = 2, G_DEPTH = 2, B_DEPTH = 2) (
        input wire clk,

        output wire h_sync_pulse,
        output wire v_sync_pulse,
        output reg [R_DEPTH - 1:0] R,
        output reg [G_DEPTH - 1:0] G,
        output reg [B_DEPTH - 1:0] B
        );

    localparam H_BITS = $clog2(H_WIDTH + HF_PORCH + H_PULSE + HB_PORCH),
            V_BITS = $clog2(V_WIDTH + VF_PORCH + V_PULSE + VB_PORCH);
    reg h_porch = 0;
    reg pre_h_porch = 0;
    reg h_sync = 1;
    assign h_sync_pulse = ~h_sync;
    reg v_porch = 0;
    reg v_sync = 1;
    assign v_sync_pulse = ~v_sync;
    reg [H_BITS - 1:0] h_count = 0;
    reg [V_BITS - 1:0] v_count = 0;
    wire [R_DEPTH + G_DEPTH + B_DEPTH - 1:0] color_out;
    frame_buffer #(.H_WIDTH(H_WIDTH), .V_WIDTH(V_WIDTH), .R_DEPTH(R_DEPTH),
                   .G_DEPTH(G_DEPTH), .B_DEPTH(B_DEPTH))
            f1(.clk(clk), .pre_h_porch(pre_h_porch), .h_porch(h_porch), .h_index(h_count), 
            .v_index(v_count), .color_out(color_out));



    always @(posedge clk) begin
        R <= color_out[5:4];
        G <= color_out[3:2];
        B <= color_out[1:0];
        h_count <= h_count + 1'b1;
        if (h_count >= H_WIDTH - 2) begin
            pre_h_porch <= 1;
        end
        if (h_count >= H_WIDTH - 1) begin
            h_porch <= 1;
            if (h_count >= H_WIDTH + HF_PORCH - 1 && h_count < H_WIDTH + HF_PORCH + H_PULSE - 1) begin
                h_sync <= 0;
            end
            if (h_count >= H_WIDTH + HF_PORCH + H_PULSE - 1) begin
                h_sync <= 1;
            end
            if (h_count == H_WIDTH + HF_PORCH + H_PULSE + HB_PORCH - 2) begin
                pre_h_porch <= 0;
            end
            if (h_count == H_WIDTH + HF_PORCH + H_PULSE + HB_PORCH - 1) begin
                h_count <= 0;
                h_porch <= 0;
                h_sync <= 1;
                pre_h_porch <= 0;
            end
        end
        else begin
            h_sync <= 1;
        end
    end

    always @(negedge h_porch) begin
        v_count <= v_count + 1'b1;
        if (v_count >= V_WIDTH - 1) begin
            v_porch <= 1;
            if (v_count >= V_WIDTH + VF_PORCH - 1 && v_count < V_WIDTH + VF_PORCH + V_PULSE - 1) begin
                v_sync <= 0;
            end
            if (v_count >= V_WIDTH + VF_PORCH + V_PULSE - 1) begin
                v_sync <= 1;
            end
            if (v_count == V_WIDTH + VF_PORCH + V_PULSE + VB_PORCH - 1) begin
                v_count <= 0;
                v_porch <= 0;
                v_sync <= 1;
            end
        end
        else begin
            v_sync <= 1;
        end
    end
endmodule