data/full_repos/permissive/121203026/virtex6/bf16x16/matlab/verilog_files/DesignAGU.v
data/verilator_xmls/33560f5c-6f80-4b39-8b68-ff8b44d3b4e8.xml
module AGU( input rst_global, clk, write_enable_cu, read_enable_cu, rollover_phase_counter,pre_rollover_phase_counter,
				output iteration_done,
				output reg [9:0] read_address, write_address );


parameter number_of_columns = 768;

wire read_enable  = read_enable_cu  | pre_rollover_phase_counter;
wire write_enable = write_enable_cu | rollover_phase_counter;

wire   read_end 		 = (read_address == number_of_columns - 1);
wire  write_end 		 = (write_address == number_of_columns - 1);

wire rst_read         = rst_global | read_end   & read_enable;
wire rst_write        = rst_global | write_end  ;



assign iteration_done = write_end ;


always@(posedge clk)
	if(rst_read)
		read_address  <= 0 ;
	else
		if(read_enable)
			read_address  <= read_address + 1 ;
		else
			read_address  <= read_address;
		
		
always@(posedge clk)
	if(rst_write)
		write_address <= 0 ;
	else
		if(write_enable)
			write_address  <= write_address + 1 ;
		else
			write_address  <= write_address;
		
		
		
endmodule
module AGU( input rst_global, clk, write_enable_cu, read_enable_cu, rollover_phase_counter,pre_rollover_phase_counter,
				output iteration_done,
				output reg [9:0] read_address, write_address );



parameter number_of_columns = 768;

wire read_enable  = read_enable_cu  | pre_rollover_phase_counter;
wire write_enable = write_enable_cu | rollover_phase_counter;

wire   read_end 		 = (read_address == number_of_columns - 1);
wire  write_end 		 = (write_address == number_of_columns - 1);

wire rst_read         = rst_global | read_end   & read_enable;
wire rst_write        = rst_global | write_end  ;



assign iteration_done = write_end ;


always@(posedge clk)
	if(rst_read)
		read_address  <= 0 ;
	else
		if(read_enable)
			read_address  <= read_address + 1 ;
		else
			read_address  <= read_address;
		
		
always@(posedge clk)
	if(rst_write)
		write_address <= 0 ;
	else
		if(write_enable)
			write_address  <= write_address + 1 ;
		else
			write_address  <= write_address;
		
		
		
endmodule