data/full_repos/permissive/161033574/rawlcd_tb.v
1: b'%Error: data/full_repos/permissive/161033574/rawlcd_tb.v:7: Cannot find include file: lcd_params.vh\n`include "lcd_params.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161033574,data/full_repos/permissive/161033574/lcd_params.vh\n             data/full_repos/permissive/161033574,data/full_repos/permissive/161033574/lcd_params.vh.v\n             data/full_repos/permissive/161033574,data/full_repos/permissive/161033574/lcd_params.vh.sv\n             lcd_params.vh\n             lcd_params.vh.v\n             lcd_params.vh.sv\n             obj_dir/lcd_params.vh\n             obj_dir/lcd_params.vh.v\n             obj_dir/lcd_params.vh.sv\n%Error: data/full_repos/permissive/161033574/rawlcd_tb.v:48: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("rawlcd_wave.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/161033574/rawlcd_tb.v:49: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, lcd1);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/161033574/rawlcd_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/161033574/rawlcd_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/161033574/rawlcd_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/161033574/rawlcd_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n      #10000000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/161033574/rawlcd_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk <= ~clk;\n          ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module rawlcd_tb;
   reg clk;
   reg rst_n;
   wire [3:0] data;
   wire flm;
   wire lp;
   wire dclk;
   wire m;
   wire fb_clk;
   wire [31:0] fb_addr;
   wire [7:0]  fb_data;

   testram tram1(.clk(fb_clk),
                 .addr(fb_addr),
                 .data(fb_data));

   lcd lcd1(.clk(clk),
            .rst_n(rst_n),
            .fb_clk(fb_clk),
            .fb_data(fb_data),
            .fb_addr(fb_addr),
            .data(data),
            .flm(flm),
            .lp(lp),
            .dclk(dclk),
            .m(m));

   initial begin
      $dumpfile("rawlcd_wave.vcd");
      $dumpvars(0, lcd1);

      clk <= 0;
      rst_n <= 1;
      #1;
      rst_n <= 0;
      #1;
      rst_n <= 1;
      #1;
      #10000000;
      $finish;
   end

   always #10 clk <= ~clk;
endmodule
module rawlcd_tb;

   reg clk;
   reg rst_n;
   wire [3:0] data;
   wire flm;
   wire lp;
   wire dclk;
   wire m;
   wire fb_clk;
   wire [31:0] fb_addr;
   wire [7:0]  fb_data;

   testram tram1(.clk(fb_clk),
                 .addr(fb_addr),
                 .data(fb_data));

   lcd lcd1(.clk(clk),
            .rst_n(rst_n),
            .fb_clk(fb_clk),
            .fb_data(fb_data),
            .fb_addr(fb_addr),
            .data(data),
            .flm(flm),
            .lp(lp),
            .dclk(dclk),
            .m(m));

   initial begin
      $dumpfile("rawlcd_wave.vcd");
      $dumpvars(0, lcd1);

      clk <= 0;
      rst_n <= 1;
      #1;
      rst_n <= 0;
      #1;
      rst_n <= 1;
      #1;
      #10000000;
      $finish;
   end

   always #10 clk <= ~clk;
endmodule