data/full_repos/permissive/101548714/T_Flip_Flop.v
data/verilator_xmls/f0376c94-d048-442b-88d8-33a1ec2e6e53.xml
module TFF(T,rst,clk,q);
  input T,rst,clk;
  output q;
  reg q;
  
  always @(posedge clk) begin
    if(rst==1) begin
      q<=0;
    end
    else begin
      q<=~T;
    end
  end
endmodule
module TFF(T,rst,clk,q);

  input T,rst,clk;
  output q;
  reg q;
  
  always @(posedge clk) begin
    if(rst==1) begin
      q<=0;
    end
    else begin
      q<=~T;
    end
  end
endmodule