data/full_repos/permissive/204486675/hdl/adc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/204486675/hdl/adc.v:53: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                 : ... In instance adc\n  data_o <= 16\'h00;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/204486675/hdl/adc.v:69: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                 : ... In instance adc\n     data_o <= 16\'h00;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/204486675/hdl/adc.v:72: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 6 bits.\n                                                                 : ... In instance adc\n      bitcount <= 32-1;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/204486675/hdl/adc.v:100: Bit extraction of var[13:0] requires 4 bit index, not 5 bits.\n                                                                  : ... In instance adc\n        data_o[bitcount] <= miso;\n              ^\n%Error: Exiting due to 4 warning(s)\n'
module adc (

	rst,
	clkin,

	go,
	state,
	calibrate,

	data_o,

	sclk,
	miso,
	cs
	);


input rst;
input clkin;

input go;
output reg state;
input calibrate;

output reg [`ADC_BITS-1:0] data_o;
reg [4:0] bitcount;

reg [2:0] delay;

input miso;
output reg sclk;
output reg cs;


reg clockphase;

always @ (posedge clkin or posedge rst)

if(rst)
	begin
		data_o <= 16'h00;

		sclk <= 1'b0;
		state <= 1'b0;
		cs <= 1'b1;

	end
else
	begin
		if(state === 1'b0)
			begin
			if(go === 1'b1)
				begin
					state <= 1'b1;

					cs <= 1'b0;
					data_o <= 16'h00;
					delay<=3'b111;
					if(calibrate===1'b1)
						bitcount <= `ADC_CALIBRATION_BITS-1;
					else
						bitcount <= `ADC_BITS-1;
				end
			else
				begin

					cs <= 1'b1;
				end
			end

		else
		begin
			if(sclk === 1'b0)
				begin
					delay<=delay-1;
					if(delay===3'b000)
						begin
							sclk <= 1'b1;
							delay<=3'b111;
						end
				end
		  else
				begin
					delay<=delay-1;
					if(delay===3'b000)
						begin
							if(calibrate===1'b0)
								data_o[bitcount] <= miso;
							sclk <= 1'b0;
							bitcount <= bitcount - 1;
							delay<=3'b111;
							if(bitcount===0)
								begin
									state<=1'b0;
								end
							end
				end
		end
	end

endmodule
module adc (

	rst,
	clkin,

	go,
	state,
	calibrate,

	data_o,

	sclk,
	miso,
	cs
	);



input rst;
input clkin;

input go;
output reg state;
input calibrate;

output reg [`ADC_BITS-1:0] data_o;
reg [4:0] bitcount;

reg [2:0] delay;

input miso;
output reg sclk;
output reg cs;


reg clockphase;

always @ (posedge clkin or posedge rst)

if(rst)
	begin
		data_o <= 16'h00;

		sclk <= 1'b0;
		state <= 1'b0;
		cs <= 1'b1;

	end
else
	begin
		if(state === 1'b0)
			begin
			if(go === 1'b1)
				begin
					state <= 1'b1;

					cs <= 1'b0;
					data_o <= 16'h00;
					delay<=3'b111;
					if(calibrate===1'b1)
						bitcount <= `ADC_CALIBRATION_BITS-1;
					else
						bitcount <= `ADC_BITS-1;
				end
			else
				begin

					cs <= 1'b1;
				end
			end

		else
		begin
			if(sclk === 1'b0)
				begin
					delay<=delay-1;
					if(delay===3'b000)
						begin
							sclk <= 1'b1;
							delay<=3'b111;
						end
				end
		  else
				begin
					delay<=delay-1;
					if(delay===3'b000)
						begin
							if(calibrate===1'b0)
								data_o[bitcount] <= miso;
							sclk <= 1'b0;
							bitcount <= bitcount - 1;
							delay<=3'b111;
							if(bitcount===0)
								begin
									state<=1'b0;
								end
							end
				end
		end
	end

endmodule