data/full_repos/permissive/18433224/test.v
data/verilator_xmls/e3bee1b4-bd53-4575-be60-99311fb12735.xml
module test(
    input a,b,
    output c);
    
    assign c=a+b;
    
endmodule
module test(
    input a,b,
    output c);

    
    assign c=a+b;
    
endmodule