data/full_repos/permissive/191638444/project_hxf5071_pbc5080.srcs/sources_1/imports/new/control_unit.v
data/verilator_xmls/a7ebd402-a2b7-4dfa-820e-3bf5fcddcfbf.xml
module control_unit(op, func, wreg, m2reg, wmem, aluc, aluimm, regrt);

    input [5:0] op;
    input [5:0] func;
    
    output reg [0:0] m2reg; 
    output reg [0:0] aluimm;
    output reg [0:0] regrt;
    
    output reg [0:0] wreg;
    output reg [0:0] wmem;
    
    output reg [3:0] aluc;
    
    always @ (op, func)
    begin
        case(op)
        6'b000000:
        begin
            m2reg <= 'b0;
            aluimm <= 'b0;
            regrt <= 'b0;
            wreg <= 'b1;
            wmem <= 'b0;
            case(func)
            6'b100000:
            begin
                aluc <=4'b0010;
            end
            6'b100010:
            begin
                aluc <=4'b0110;
            end
            6'b100100:
            begin
                aluc <=4'b0000;
            end
            6'b100101:
            begin
                aluc <=4'b0001;
            end
            6'b100110:
            begin
                aluc <=4'b0011;
            end
            6'b101010:
            begin
                aluc <=4'b0111;
            end
            
            6'b000000:
            begin
                aluc <=4'b0010;
            end
            
            6'b000010:
            begin
                aluc <=4'd0010;
            end
            6'b000011:
            begin
                aluc <=4'd0010;
            end
            
            6'b001000:
            begin
                aluc <=4'd0010;
            end
            
            
            endcase
            
        end
        6'b001000:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        6'b001100:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        6'b001101:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        6'b001110:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        6'b100011:
        begin
            m2reg <= 'b1;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0010;
        end
        6'b101011:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b0;
            wmem <= 'b1;
            aluc <= 'b0010;
        end
        6'b000100:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b0;
            wmem <= 'b0;
            aluc <= 'd1;
        end
        6'b000101:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b0;
            wmem <= 'b0;
            aluc <= 'd1;
        end
        6'b001111:
        begin
            m2reg <= 'b1;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        6'b000010:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b0;
            wreg <= 'b0;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        6'b000011:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b0;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        default:
        begin
            m2reg <= 'b0;
            aluimm <= 'b0;
            regrt <= 'b0;
            wreg <= 'b0;
            wmem <= 'b0;
            aluc <= 'd15;
        end
        endcase
    end
endmodule
module control_unit(op, func, wreg, m2reg, wmem, aluc, aluimm, regrt);


    input [5:0] op;
    input [5:0] func;
    
    output reg [0:0] m2reg; 
    output reg [0:0] aluimm;
    output reg [0:0] regrt;
    
    output reg [0:0] wreg;
    output reg [0:0] wmem;
    
    output reg [3:0] aluc;
    
    always @ (op, func)
    begin
        case(op)
        6'b000000:
        begin
            m2reg <= 'b0;
            aluimm <= 'b0;
            regrt <= 'b0;
            wreg <= 'b1;
            wmem <= 'b0;
            case(func)
            6'b100000:
            begin
                aluc <=4'b0010;
            end
            6'b100010:
            begin
                aluc <=4'b0110;
            end
            6'b100100:
            begin
                aluc <=4'b0000;
            end
            6'b100101:
            begin
                aluc <=4'b0001;
            end
            6'b100110:
            begin
                aluc <=4'b0011;
            end
            6'b101010:
            begin
                aluc <=4'b0111;
            end
            
            6'b000000:
            begin
                aluc <=4'b0010;
            end
            
            6'b000010:
            begin
                aluc <=4'd0010;
            end
            6'b000011:
            begin
                aluc <=4'd0010;
            end
            
            6'b001000:
            begin
                aluc <=4'd0010;
            end
            
            
            endcase
            
        end
        6'b001000:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        6'b001100:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        6'b001101:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        6'b001110:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        6'b100011:
        begin
            m2reg <= 'b1;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0010;
        end
        6'b101011:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b0;
            wmem <= 'b1;
            aluc <= 'b0010;
        end
        6'b000100:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b0;
            wmem <= 'b0;
            aluc <= 'd1;
        end
        6'b000101:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b0;
            wmem <= 'b0;
            aluc <= 'd1;
        end
        6'b001111:
        begin
            m2reg <= 'b1;
            aluimm <= 'b1;
            regrt <= 'b1;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        6'b000010:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b0;
            wreg <= 'b0;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        6'b000011:
        begin
            m2reg <= 'b0;
            aluimm <= 'b1;
            regrt <= 'b0;
            wreg <= 'b1;
            wmem <= 'b0;
            aluc <= 'b0;
        end
        default:
        begin
            m2reg <= 'b0;
            aluimm <= 'b0;
            regrt <= 'b0;
            wreg <= 'b0;
            wmem <= 'b0;
            aluc <= 'd15;
        end
        endcase
    end
endmodule