data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_deserializer_eof.v
1: b"%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_deserializer_eof.v:46: Cannot find file containing module: 'stream_deserializer'\n  stream_deserializer #(\n  ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream,data/full_repos/permissive/181738725/stream_deserializer\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream,data/full_repos/permissive/181738725/stream_deserializer.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream,data/full_repos/permissive/181738725/stream_deserializer.sv\n             stream_deserializer\n             stream_deserializer.v\n             stream_deserializer.sv\n             obj_dir/stream_deserializer\n             obj_dir/stream_deserializer.v\n             obj_dir/stream_deserializer.sv\n%Error: Exiting due to 1 error(s)\n"
module stream_deserializer_eof #(
  parameter DataBits = 8,
  parameter Ratio    = 2)
(
  input                           clk,
  input                           rst,

  input                           in_valid,
  output                          in_ready,
  input [DataBits-1:0]            in_data,
  input                           in_eof,

  output                          out_valid,
  input                           out_ready,
  output reg [Ratio*DataBits-1:0] out_data,
  output                          out_eof
);

  wire [Ratio*(DataBits+1)-1:0] out_data_i;
  stream_deserializer #(
    .DataBits (DataBits+1),
    .Ratio    (Ratio))
  ser (
    .rst       (rst),
    .clk       (clk),
    .in_valid  (in_valid),
    .in_ready  (in_ready),
    .in_data   ({in_eof, in_data}),
    .out_valid (out_valid),
    .out_ready (out_ready),
    .out_data  (out_data_i));

  integer i;
  always @(*) begin
    for (i=0; i < Ratio; i=i+1) begin
      out_data[i*DataBits +: DataBits] = out_data_i[i*(DataBits+1) +: DataBits];
    end
  end

  assign out_eof = out_data_i[Ratio*(DataBits+1)-1];

endmodule
module stream_deserializer_eof #(
  parameter DataBits = 8,
  parameter Ratio    = 2)
(
  input                           clk,
  input                           rst,

  input                           in_valid,
  output                          in_ready,
  input [DataBits-1:0]            in_data,
  input                           in_eof,

  output                          out_valid,
  input                           out_ready,
  output reg [Ratio*DataBits-1:0] out_data,
  output                          out_eof
);


  wire [Ratio*(DataBits+1)-1:0] out_data_i;
  stream_deserializer #(
    .DataBits (DataBits+1),
    .Ratio    (Ratio))
  ser (
    .rst       (rst),
    .clk       (clk),
    .in_valid  (in_valid),
    .in_ready  (in_ready),
    .in_data   ({in_eof, in_data}),
    .out_valid (out_valid),
    .out_ready (out_ready),
    .out_data  (out_data_i));

  integer i;
  always @(*) begin
    for (i=0; i < Ratio; i=i+1) begin
      out_data[i*DataBits +: DataBits] = out_data_i[i*(DataBits+1) +: DataBits];
    end
  end

  assign out_eof = out_data_i[Ratio*(DataBits+1)-1];

endmodule