data/full_repos/permissive/143278/ivltests/pr1494799.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1494799.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1  ;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr1494799.v:31: Unsupported or unknown PLI call: $is_signed\n $display("%b %b %b %b", $is_signed(a),\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1494799.v:32: Unsupported or unknown PLI call: $is_signed\n $is_signed(b), $is_signed(c), $is_signed(c >>> 1));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1494799.v:32: Unsupported or unknown PLI call: $is_signed\n $is_signed(b), $is_signed(c), $is_signed(c >>> 1));\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr1494799.v:32: Unsupported or unknown PLI call: $is_signed\n $is_signed(b), $is_signed(c), $is_signed(c >>> 1));\n                               ^~~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();
 reg signed [19:0] a, b;
 reg signed [24:0] z, c;

 wire signed [24:0] y;

 wire signed [24:0] w = a + b + c - (c >>> 1);

 math m(a,b,c,y);

 initial begin
 a = -5;
 $display("a = %x %d", a, a);
 b = 0;
 $display("b = %x %d", b, b);
 c = 8;
 $display("c = %x %d", c, c);
 z = a + b + c - (c >>> 1);
    #1;
 $display("z = %x, %d, %b", z, z, z);
 $display("y = %x, %d, %b", y, y, y);
 $display("w = %x, %d, %b", w, w, w);
 $display("%b %b %b %b", $is_signed(a),
 $is_signed(b), $is_signed(c), $is_signed(c >>> 1));
 end
 endmodule
module test();

 reg signed [19:0] a, b;
 reg signed [24:0] z, c;

 wire signed [24:0] y;

 wire signed [24:0] w = a + b + c - (c >>> 1);

 math m(a,b,c,y);

 initial begin
 a = -5;
 $display("a = %x %d", a, a);
 b = 0;
 $display("b = %x %d", b, b);
 c = 8;
 $display("c = %x %d", c, c);
 z = a + b + c - (c >>> 1);
    #1;
 $display("z = %x, %d, %b", z, z, z);
 $display("y = %x, %d, %b", y, y, y);
 $display("w = %x, %d, %b", w, w, w);
 $display("%b %b %b %b", $is_signed(a),
 $is_signed(b), $is_signed(c), $is_signed(c >>> 1));
 end
 endmodule