data/full_repos/permissive/20430511/hardware/FPGA/fifo/fifo16s.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/bcabec27-0ffc-40a3-ba76-4ee65ffb493b.xml
module fifo16s (
	clock_i,
	reset_ni,
	
	read_i,
	write_i,
	data_i,
	data_o,
	
	empty_no,
	full_o
);


parameter	WIDTH	= 16;
parameter	MSB	= WIDTH - 1;

input		clock_i;
input		reset_ni;

input		read_i;
input		write_i;
input	[MSB:0]	data_i;
output	[MSB:0]	data_o;

output	empty_no;
output	full_o;






reg	[4:0]	f_start	= 5'h0;
reg	[4:0]	f_end	= 5'h0;

wire	ptrs_equal;


reg	[MSB:0]	mem [0:15];





assign	ptrs_equal	= (f_start [3:0] == f_end [3:0]);
assign	empty_no	= !((f_start [4] == f_end [4]) && ptrs_equal);
assign	full_o		= ((f_start [4] != f_end [4]) && ptrs_equal);

assign data_o		= mem [f_start [3:0]];



always @(posedge clock_i)
	if (!reset_ni)
		f_start	<= 0;
	else begin
		if (read_i && empty_no)
			f_start	<= f_start + 1;
		else
			f_start	<= f_start;
	end



always @(posedge clock_i)
	if (!reset_ni)
		f_end	<= 0;
	else begin
		if (write_i && !full_o)
			f_end	<= f_end + 1;
		else
			f_end	<= f_end;
	end


always @ (posedge clock_i)
	if (write_i && !full_o)
		mem [f_end [3:0]]  <= data_i;


`ifdef __icarus




	initial begin : Init
		init_mem (0);
	end
	
	
	task init_mem;
		input	val;
		integer	val, n;
	begin : Init_Mem
		for (n = 0; n < 16; n = n + 1)
			mem[n]	= val;
	end
	endtask
`endif
	
	
endmodule
module fifo16s (
	clock_i,
	reset_ni,
	
	read_i,
	write_i,
	data_i,
	data_o,
	
	empty_no,
	full_o
);



parameter	WIDTH	= 16;
parameter	MSB	= WIDTH - 1;

input		clock_i;
input		reset_ni;

input		read_i;
input		write_i;
input	[MSB:0]	data_i;
output	[MSB:0]	data_o;

output	empty_no;
output	full_o;






reg	[4:0]	f_start	= 5'h0;
reg	[4:0]	f_end	= 5'h0;

wire	ptrs_equal;


reg	[MSB:0]	mem [0:15];





assign	ptrs_equal	= (f_start [3:0] == f_end [3:0]);
assign	empty_no	= !((f_start [4] == f_end [4]) && ptrs_equal);
assign	full_o		= ((f_start [4] != f_end [4]) && ptrs_equal);

assign data_o		= mem [f_start [3:0]];



always @(posedge clock_i)
	if (!reset_ni)
		f_start	<= 0;
	else begin
		if (read_i && empty_no)
			f_start	<= f_start + 1;
		else
			f_start	<= f_start;
	end



always @(posedge clock_i)
	if (!reset_ni)
		f_end	<= 0;
	else begin
		if (write_i && !full_o)
			f_end	<= f_end + 1;
		else
			f_end	<= f_end;
	end


always @ (posedge clock_i)
	if (write_i && !full_o)
		mem [f_end [3:0]]  <= data_i;


`ifdef __icarus




	initial begin : Init
		init_mem (0);
	end
	
	
	task init_mem;
		input	val;
		integer	val, n;
	begin : Init_Mem
		for (n = 0; n < 16; n = n + 1)
			mem[n]	= val;
	end
	endtask
`endif
	
	
endmodule