data/full_repos/permissive/128566293/TBench/verilog/tc_heartbeat.v
None: at end of input
1: b'%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_heartbeat.v:21: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128566293/TBench/verilog,data/full_repos/permissive/128566293/timescale.v\n             data/full_repos/permissive/128566293/TBench/verilog,data/full_repos/permissive/128566293/timescale.v.v\n             data/full_repos/permissive/128566293/TBench/verilog,data/full_repos/permissive/128566293/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_heartbeat.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_heartbeat.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_heartbeat.v:82: syntax error, unexpected \'@\'\n    @ (negedge rst_tb);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_heartbeat.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #((0.8 * 10));\n    ^\n%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_heartbeat.v:92: syntax error, unexpected \'@\'\n        @ (posedge clk_tb);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_heartbeat.v:103: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_heartbeat.v:115: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile(`DUMPFILE);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_heartbeat.v:115: Define or directive not defined: \'`DUMPFILE\'\n    $dumpfile(`DUMPFILE);\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_heartbeat.v:116: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_heartbeat.v:118: Unsupported: Ignoring delay on this delayed statement.\n    #(800_000);\n    ^\n%Error: Exiting due to 6 error(s), 5 warning(s)\n'
module tc_heartbeat (

);



    reg                 clk_tb = ~0;

always @ (clk_tb)
begin
    clk_tb <= #(`CLK_PERIOD/2) ~clk_tb;
end

    reg                 rst_tb = 0;

initial
begin
    #1;

    rst_tb <= ~0;
    rst_tb <= #(`RST_PERIOD) 0;
end



    localparam          f_clkin = 12_000;

    wire                w_ledout;



    defparam dut.f_clkin = f_clkin;

VfD_heartbeat dut (
    .o_led              (w_ledout),

    .clk                (clk_tb),
    .rst                (rst_tb)
);



    integer             failed = 0;

task t_initialize;
begin
    #1;
    @ (negedge rst_tb);
    @ (posedge clk_tb);
    #(`STROBE);
end
endtask

task t_run;
    input integer reps;
begin
    repeat(reps) begin
        @ (posedge clk_tb);
    end
end
endtask

initial
begin
    t_initialize;

    t_run(25_000);

    #1;
    if (failed)
        $display("\t%m: *failed* %0d times", failed);
    else
        $display("\t%m: *well done*");
    $finish;
end



initial
begin
    $dumpfile(`DUMPFILE);
    $dumpvars;

    #(`TIMELIMIT);
    $display("\t%m: *time limit (%t) reached*", $time);
    $finish;
end

endmodule
module tc_heartbeat (

);




    reg                 clk_tb = ~0;

always @ (clk_tb)
begin
    clk_tb <= #(`CLK_PERIOD/2) ~clk_tb;
end

    reg                 rst_tb = 0;

initial
begin
    #1;

    rst_tb <= ~0;
    rst_tb <= #(`RST_PERIOD) 0;
end



    localparam          f_clkin = 12_000;

    wire                w_ledout;



    defparam dut.f_clkin = f_clkin;

VfD_heartbeat dut (
    .o_led              (w_ledout),

    .clk                (clk_tb),
    .rst                (rst_tb)
);



    integer             failed = 0;

task t_initialize;
begin
    #1;
    @ (negedge rst_tb);
    @ (posedge clk_tb);
    #(`STROBE);
end
endtask

task t_run;
    input integer reps;
begin
    repeat(reps) begin
        @ (posedge clk_tb);
    end
end
endtask

initial
begin
    t_initialize;

    t_run(25_000);

    #1;
    if (failed)
        $display("\t%m: *failed* %0d times", failed);
    else
        $display("\t%m: *well done*");
    $finish;
end



initial
begin
    $dumpfile(`DUMPFILE);
    $dumpvars;

    #(`TIMELIMIT);
    $display("\t%m: *time limit (%t) reached*", $time);
    $finish;
end

endmodule