data/full_repos/permissive/123690745/MEMWB.v
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data/verilator_xmls/39c8b3d4-67fd-4e02-8852-9275eb0f2f35.xml
module MEMWB(
	 input InterruptRequest,
	 input clk, input reset,
    input [31:0] ReadDataM,
	 output reg [31:0] ReadDataW = 0,
    input [31:0] ReadDataCM,
	 output reg [31:0] ReadDataCW = 0,
	 input [15:0] ReadDataHM,
	 output reg [15:0] ReadDataHW = 0,
	 input [7:0] ReadDataBM,
	 output reg [7:0] ReadDataBW = 0,
    input [31:0] ALUOutM,
    output reg [31:0] ALUOutW = 0,
    input [4:0] WriteRegM,
    output reg [4:0] WriteRegW = 0,
	 input [31:0] InstrM,
	 output reg [31:0] InstrW = 0,
	 input [31:0] CPURD,
	 output reg [31:0] CPURDW = 0,
	 input [31:0] CP0DataOutM,
	 output reg [31:0] CP0DataOutW = 0,
	 input [31:0] PCM,
	 output reg [31:0] PCW = 0
    );
	always @(posedge clk) begin
		if (reset || InterruptRequest) begin
			ReadDataW <= 0;
			ReadDataCW <= 0;
			ReadDataHW <= 0;
			ReadDataBW <= 0;
			ALUOutW <= 0;
			WriteRegW <= 0;
			InstrW <= 0;
			CPURDW <= 0;
			CP0DataOutW <= 0;
			PCW <= 0;
		end
		else begin
			ReadDataW <= ReadDataM;
			ReadDataCW <= ReadDataCM;
			ReadDataHW <= ReadDataHM;
			ReadDataBW <= ReadDataBM;
			ALUOutW <= ALUOutM;
			WriteRegW <= WriteRegM;
			InstrW <= InstrM;
			CPURDW <= CPURD;
			CP0DataOutW <= CP0DataOutM;
			PCW <= PCM;

		end
	end

endmodule
module MEMWB(
	 input InterruptRequest,
	 input clk, input reset,
    input [31:0] ReadDataM,
	 output reg [31:0] ReadDataW = 0,
    input [31:0] ReadDataCM,
	 output reg [31:0] ReadDataCW = 0,
	 input [15:0] ReadDataHM,
	 output reg [15:0] ReadDataHW = 0,
	 input [7:0] ReadDataBM,
	 output reg [7:0] ReadDataBW = 0,
    input [31:0] ALUOutM,
    output reg [31:0] ALUOutW = 0,
    input [4:0] WriteRegM,
    output reg [4:0] WriteRegW = 0,
	 input [31:0] InstrM,
	 output reg [31:0] InstrW = 0,
	 input [31:0] CPURD,
	 output reg [31:0] CPURDW = 0,
	 input [31:0] CP0DataOutM,
	 output reg [31:0] CP0DataOutW = 0,
	 input [31:0] PCM,
	 output reg [31:0] PCW = 0
    );

	always @(posedge clk) begin
		if (reset || InterruptRequest) begin
			ReadDataW <= 0;
			ReadDataCW <= 0;
			ReadDataHW <= 0;
			ReadDataBW <= 0;
			ALUOutW <= 0;
			WriteRegW <= 0;
			InstrW <= 0;
			CPURDW <= 0;
			CP0DataOutW <= 0;
			PCW <= 0;
		end
		else begin
			ReadDataW <= ReadDataM;
			ReadDataCW <= ReadDataCM;
			ReadDataHW <= ReadDataHM;
			ReadDataBW <= ReadDataBM;
			ALUOutW <= ALUOutM;
			WriteRegW <= WriteRegM;
			InstrW <= InstrM;
			CPURDW <= CPURD;
			CP0DataOutW <= CP0DataOutM;
			PCW <= PCM;

		end
	end

endmodule