data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:65: Cannot find include file: adbg_defines.v\n`include "adbg_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog,data/full_repos/permissive/17099167/adbg_defines.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog,data/full_repos/permissive/17099167/adbg_defines.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog,data/full_repos/permissive/17099167/adbg_defines.v.sv\n             adbg_defines.v\n             adbg_defines.v.v\n             adbg_defines.v.sv\n             obj_dir/adbg_defines.v\n             obj_dir/adbg_defines.v.v\n             obj_dir/adbg_defines.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:66: Cannot find include file: adbg_or1k_defines.v\n`include "adbg_or1k_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:136: Define or directive not defined: \'`DBG_OR1K_REGSELECT_SIZE\'\n   reg [`DBG_OR1K_REGSELECT_SIZE-1:0] internal_register_select;   \n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:188: Define or directive not defined: \'`DBG_OR1K_REGSELECT_SIZE\'\n   wire [`DBG_OR1K_REGSELECT_SIZE-1:0] reg_select_data;  \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:206: Define or directive not defined: \'`DBG_OR1K_REGSELECT_SIZE\'\n   assign     reg_select_data = data_register_i[47:(47-(`DBG_OR1K_REGSELECT_SIZE-1))];\n                                                        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:212: Define or directive not defined: \'`DBG_OR1K_CMD_BWRITE32\'\n   assign     burst_instruction = (operation_in == `DBG_OR1K_CMD_BWRITE32) | (operation_in == `DBG_OR1K_CMD_BREAD32);\n                                                   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:212: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign     burst_instruction = (operation_in == `DBG_OR1K_CMD_BWRITE32) | (operation_in == `DBG_OR1K_CMD_BREAD32);\n                                                                         ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:212: Define or directive not defined: \'`DBG_OR1K_CMD_BREAD32\'\n   assign     burst_instruction = (operation_in == `DBG_OR1K_CMD_BWRITE32) | (operation_in == `DBG_OR1K_CMD_BREAD32);\n                                                                                              ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:213: Define or directive not defined: \'`DBG_OR1K_CMD_IREG_WR\'\n   assign     intreg_instruction = ((operation_in == `DBG_OR1K_CMD_IREG_WR) | (operation_in == `DBG_OR1K_CMD_IREG_SEL));\n                                                     ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:213: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign     intreg_instruction = ((operation_in == `DBG_OR1K_CMD_IREG_WR) | (operation_in == `DBG_OR1K_CMD_IREG_SEL));\n                                                                          ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:213: Define or directive not defined: \'`DBG_OR1K_CMD_IREG_SEL\'\n   assign     intreg_instruction = ((operation_in == `DBG_OR1K_CMD_IREG_WR) | (operation_in == `DBG_OR1K_CMD_IREG_SEL));\n                                                                                               ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:214: Define or directive not defined: \'`DBG_OR1K_CMD_IREG_WR\'\n   assign     intreg_write = (operation_in == `DBG_OR1K_CMD_IREG_WR);\n                                              ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:214: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign     intreg_write = (operation_in == `DBG_OR1K_CMD_IREG_WR);\n                                                                   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:240: Define or directive not defined: \'`DBG_OR1K_INTREG_STATUS\'\n          `DBG_OR1K_INTREG_STATUS: data_from_internal_reg = {30\'h0, internal_reg_status};\n          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:240: syntax error, unexpected \':\', expecting endcase\n          `DBG_OR1K_INTREG_STATUS: data_from_internal_reg = {30\'h0, internal_reg_status};\n                                 ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:254: Define or directive not defined: \'`DBG_OR1K_INTREG_STATUS\'\n   assign status_reg_wr = (intreg_ld_en & (reg_select_data == `DBG_OR1K_INTREG_STATUS));\n                                                              ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:257: Define or directive not defined: \'`DBG_OR1K_REGSELECT_SIZE\'\n         .data_i(data_register_i[(47-`DBG_OR1K_REGSELECT_SIZE):(47-(`DBG_OR1K_REGSELECT_SIZE+1))]), \n                                     ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:257: Define or directive not defined: \'`DBG_OR1K_REGSELECT_SIZE\'\n         .data_i(data_register_i[(47-`DBG_OR1K_REGSELECT_SIZE):(47-(`DBG_OR1K_REGSELECT_SIZE+1))]), \n                                                                    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v:277: syntax error, unexpected always\n   always @ (posedge tck_i or posedge rst_i)   \n   ^~~~~~\n%Error: Exiting due to 19 error(s)\n'
module adbg_or1k_module (

			 tck_i,
			 module_tdo_o,
			 tdi_i,


			 capture_dr_i,
			 shift_dr_i,
			 update_dr_i,

			 data_register_i,
			 module_select_i,
			 top_inhibit_o,
			 rst_i,


			 cpu_clk_i, 
			 cpu_addr_o, 
			 cpu_data_i, 
			 cpu_data_o,
			 cpu_bp_i,
			 cpu_stall_o,
			 cpu_stb_o,
			 cpu_we_o,
			 cpu_ack_i,
			 cpu_rst_o
			 );


   input         tck_i;
   output        module_tdo_o;
   input         tdi_i;


   input         capture_dr_i;
   input         shift_dr_i;
   input         update_dr_i;

   input [52:0]  data_register_i;
   input         module_select_i;
   output        top_inhibit_o;
   input         rst_i;


   input 	 cpu_clk_i;
   output [31:0] cpu_addr_o;
   input [31:0]  cpu_data_i;
   output [31:0] cpu_data_o;
   output 	 cpu_stb_o;
   output 	 cpu_we_o;
   input 	 cpu_ack_i;
   output 	 cpu_rst_o;
   input 	 cpu_bp_i;
   output 	 cpu_stall_o;


   reg 		 module_tdo_o;
   reg 		 top_inhibit_o;



   reg [31:0] 	 address_counter;
   reg [5:0] 	 bit_count;
   reg [15:0] 	 word_count;
   reg [3:0] 	 operation;
   reg [31:0] 	 data_out_shift_reg;
   reg [`DBG_OR1K_REGSELECT_SIZE-1:0] internal_register_select;
   wire [1:0] 			      internal_reg_status;



   reg 				      addr_sel;
   reg 				      addr_ct_en;
   reg 				      op_reg_en;
   reg 				      bit_ct_en;
   reg 				      bit_ct_rst;
   reg 				      word_ct_sel;
   reg 				      word_ct_en;
   reg 				      out_reg_ld_en;
   reg 				      out_reg_shift_en;
   reg 				      out_reg_data_sel;
   reg [1:0] 			      tdo_output_sel;
   reg 				      biu_strobe;
   reg 				      crc_clr;
   reg 				      crc_en;
   reg 				      crc_in_sel;
   reg 				      crc_shift_en;
   reg 				      regsel_ld_en;
   reg 				      intreg_ld_en;



   wire 			      word_count_zero;
   wire 			      bit_count_max;
   wire 			      module_cmd;
   wire 			      biu_ready;
   wire 			      burst_instruction;
   wire 			      intreg_instruction;
   wire 			      intreg_write;
   wire 			      rd_op;
   wire 			      crc_match;
   wire 			      bit_count_32;


   wire [5:0] 			      word_size_bits;
   wire [2:0] 			      address_increment;
   wire [32:0] 			      incremented_address;
   wire [31:0] 			      data_to_addr_counter;
   wire [15:0] 			      data_to_word_counter;
   wire [15:0] 			      decremented_word_count;
   wire [31:0] 			      address_data_in;
   wire [15:0] 			      count_data_in;
   wire [3:0] 			      operation_in;
   wire [31:0] 			      data_to_biu;
   wire [31:0] 			      data_from_biu;
   wire [31:0] 			      crc_data_out;
   wire 			      crc_data_in;
   wire 			      crc_serial_out;
   wire [`DBG_OR1K_REGSELECT_SIZE-1:0] reg_select_data;
   wire [31:0] 			       out_reg_data;
   reg [31:0] 			       data_from_internal_reg;
   wire 			       status_reg_wr;





       assign module_cmd = ~(data_register_i[52]);
   assign     operation_in = data_register_i[51:48];
   assign     address_data_in = data_register_i[47:16];
   assign     count_data_in = data_register_i[15:0];
`ifdef ADBG_USE_HISPEED
   assign     data_to_biu = {tdi_i,data_register_i[52:22]};
`else   
   assign     data_to_biu = data_register_i[52:21];
`endif   
   assign     reg_select_data = data_register_i[47:(47-(`DBG_OR1K_REGSELECT_SIZE-1))];





   assign     burst_instruction = (operation_in == `DBG_OR1K_CMD_BWRITE32) | (operation_in == `DBG_OR1K_CMD_BREAD32);
   assign     intreg_instruction = ((operation_in == `DBG_OR1K_CMD_IREG_WR) | (operation_in == `DBG_OR1K_CMD_IREG_SEL));
   assign     intreg_write = (operation_in == `DBG_OR1K_CMD_IREG_WR);


   assign     word_size_bits = 5'd31;
   assign     address_increment = 3'd1;



   assign     rd_op = operation[2];






   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i) internal_register_select = 1'h0;
	else if(regsel_ld_en) internal_register_select = reg_select_data;
     end



   always @ (internal_register_select or internal_reg_status)
     begin
	case(internal_register_select) 
          `DBG_OR1K_INTREG_STATUS: data_from_internal_reg = {30'h0, internal_reg_status};
          default: data_from_internal_reg = {30'h0, internal_reg_status};
	endcase
     end
   









   assign status_reg_wr = (intreg_ld_en & (reg_select_data == `DBG_OR1K_INTREG_STATUS));

   adbg_or1k_status_reg or1k_statusreg_i (
				     .data_i(data_register_i[(47-`DBG_OR1K_REGSELECT_SIZE):(47-(`DBG_OR1K_REGSELECT_SIZE+1))]), 
				     .we_i(status_reg_wr),
				     .tck_i(tck_i),
				     .bp_i(cpu_bp_i),
				     .rst_i(rst_i),
				     .cpu_clk_i(cpu_clk_i),
				     .ctrl_reg_o(internal_reg_status),
				     .cpu_stall_o(cpu_stall_o),
				     .cpu_rst_o(cpu_rst_o)
				     );





     assign data_to_addr_counter = (addr_sel) ? incremented_address[31:0] : address_data_in;
   assign   incremented_address = address_counter + address_increment;



   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  address_counter <= 32'h0;
	else if(addr_ct_en)
	  address_counter <= data_to_addr_counter;
     end




   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  operation <= 4'h0;
	else if(op_reg_en)
	  operation <= operation_in;
     end




   always @ (posedge tck_i or posedge rst_i)
     begin

	if(rst_i)             bit_count <= 6'h0;
	else if(bit_ct_rst)  bit_count <= 6'h0;
	else if(bit_ct_en)    bit_count <= bit_count + 6'h1;

     end

   assign bit_count_max = (bit_count == word_size_bits) ? 1'b1 : 1'b0 ;
   assign bit_count_32 = (bit_count == 6'h20) ? 1'b1 : 1'b0;




   assign data_to_word_counter = (word_ct_sel) ?  decremented_word_count : count_data_in;
   assign decremented_word_count = word_count - 16'h1;



   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  word_count <= 16'h0;
	else if(word_ct_en)
	  word_count <= data_to_word_counter;
     end

   assign word_count_zero = (word_count == 16'h0);




			    assign out_reg_data = (out_reg_data_sel) ? data_from_internal_reg : data_from_biu;

   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i) data_out_shift_reg <= 32'h0;
	else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data;
	else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[31:1]};
     end


   always @ (tdo_output_sel or data_out_shift_reg[0] or biu_ready or crc_match or crc_serial_out)
     begin
	if(tdo_output_sel == 2'h0) module_tdo_o <= biu_ready;
	else if(tdo_output_sel == 2'h1) module_tdo_o <= data_out_shift_reg[0];
	else if(tdo_output_sel == 2'h2) module_tdo_o <= crc_match;
	else module_tdo_o <= crc_serial_out;
     end







   adbg_or1k_biu or1k_biu_i (

			     .tck_i           (tck_i),
			     .rst_i           (rst_i),
			     .data_i          (data_to_biu),
			     .data_o          (data_from_biu),
			     .addr_i          (address_counter),
			     .strobe_i        (biu_strobe),
			     .rd_wrn_i        (rd_op),
			     .rdy_o           (biu_ready),

			     

			     .cpu_clk_i(cpu_clk_i),
			     .cpu_addr_o(cpu_addr_o),
			     .cpu_data_i(cpu_data_i),
			     .cpu_data_o(cpu_data_o),
			     .cpu_stb_o(cpu_stb_o),
			     .cpu_we_o(cpu_we_o),
			     .cpu_ack_i(cpu_ack_i)
			     );






     assign crc_data_in = (crc_in_sel) ? tdi_i : data_out_shift_reg[0];

   adbg_crc32 or1k_crc_i
     (
      .clk(tck_i), 
      .data(crc_data_in),
      .enable(crc_en),
      .shift(crc_shift_en),
      .clr(crc_clr),
      .rst(rst_i),
      .crc_out(crc_data_out),
      .serial_out(crc_serial_out)
      );

   assign   crc_match = (data_register_i[52:21] == crc_data_out) ? 1'b1 : 1'b0;








`define STATE_idle     4'h0
`define STATE_Rbegin   4'h1
`define STATE_Rready   4'h2
`define STATE_Rstatus  4'h3
`define STATE_Rburst   4'h4
`define STATE_Wready   4'h5
`define STATE_Wwait    4'h6
`define STATE_Wburst   4'h7
`define STATE_Wstatus  4'h8
`define STATE_Rcrc     4'h9
`define STATE_Wcrc     4'ha
`define STATE_Wmatch   4'hb

   reg [3:0] module_state;
   reg [3:0] module_next_state;




   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  module_state <= `STATE_idle;
	else
	  module_state <= module_next_state;
     end



   always @ (module_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or operation_in[2]
	     or word_count_zero or bit_count_max or data_register_i[52] or bit_count_32 or biu_ready
	     or module_cmd or intreg_write or decremented_word_count or burst_instruction)
     begin
	case(module_state)
	  `STATE_idle:
	    begin
	       if(module_cmd && module_select_i && update_dr_i && burst_instruction && operation_in[2]) module_next_state <= `STATE_Rbegin;
	       else if(module_cmd && module_select_i && update_dr_i && burst_instruction) module_next_state <= `STATE_Wready;
	       else module_next_state <= `STATE_idle;
	    end

	  `STATE_Rbegin:
	    begin
	       if(word_count_zero) module_next_state <= `STATE_idle;
	       else module_next_state <= `STATE_Rready;
	    end
	  `STATE_Rready:
	    begin
	       if(module_select_i && capture_dr_i) module_next_state <= `STATE_Rstatus;
	       else module_next_state <= `STATE_Rready;
	    end
	  `STATE_Rstatus:
	    begin
	       if(update_dr_i) module_next_state <= `STATE_idle; 
	       else if (biu_ready) module_next_state <= `STATE_Rburst;
	       else module_next_state <= `STATE_Rstatus;
	    end
	  `STATE_Rburst:
	    begin
	       if(update_dr_i) module_next_state <= `STATE_idle; 
	       else if(bit_count_max && word_count_zero) module_next_state <= `STATE_Rcrc;
`ifndef ADBG_USE_HISPEED         
	       else if(bit_count_max) module_next_state <= `STATE_Rstatus;
`endif	         
	       else module_next_state <= `STATE_Rburst;
	    end
	  `STATE_Rcrc:
	    begin
	       if(update_dr_i) module_next_state <= `STATE_idle;

	       else module_next_state <= `STATE_Rcrc;    
	    end

	  `STATE_Wready:
	    begin
	       if(word_count_zero) module_next_state <= `STATE_idle;
	       else if(module_select_i && capture_dr_i) module_next_state <= `STATE_Wwait;
	       else module_next_state <= `STATE_Wready;
	    end
	  `STATE_Wwait:
	    begin
	       if(update_dr_i)  module_next_state <= `STATE_idle;
	       else if(module_select_i && data_register_i[52]) module_next_state <= `STATE_Wburst;
	       else module_next_state <= `STATE_Wwait;
	    end
	  `STATE_Wburst:
	    begin
	       if(update_dr_i)  module_next_state <= `STATE_idle;
	       else if(bit_count_max) 
	         begin
`ifdef ADBG_USE_HISPEED
		        if(word_count_zero) module_next_state <= `STATE_Wcrc;
		        else module_next_state <= `STATE_Wburst;
`else	           
	         module_next_state <= `STATE_Wstatus;
`endif	           
	         end
	       else module_next_state <= `STATE_Wburst;
	    end
	  `STATE_Wstatus:
	    begin
	       if(update_dr_i)  module_next_state <= `STATE_idle;
	       else if(word_count_zero) module_next_state <= `STATE_Wcrc;



	       else module_next_state <= `STATE_Wburst;
	    end
	  
	  `STATE_Wcrc:
	    begin
	       if(update_dr_i)  module_next_state <= `STATE_idle;
	       else if(bit_count_32) module_next_state <= `STATE_Wmatch;
	       else module_next_state <= `STATE_Wcrc;    
	    end
	  
	  `STATE_Wmatch:
	    begin
	       if(update_dr_i)  module_next_state <= `STATE_idle;

	       else module_next_state <= `STATE_Wmatch;    
	    end

	  default: module_next_state <= `STATE_idle;
	endcase
     end



   always @ (module_state or module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or operation_in[2]
	     or word_count_zero or bit_count_max or data_register_i[52] or biu_ready or intreg_instruction
	     or module_cmd or intreg_write or decremented_word_count)
     begin

	addr_sel <= 1'b1;
	addr_ct_en <= 1'b0;
	op_reg_en <= 1'b0;
	bit_ct_en <= 1'b0;
	bit_ct_rst <= 1'b0;
	word_ct_sel <= 1'b1;
	word_ct_en <= 1'b0;
	out_reg_ld_en <= 1'b0;
	out_reg_shift_en <= 1'b0;
	tdo_output_sel <= 2'b1;
	biu_strobe <= 1'b0;
	crc_clr <= 1'b0;
	crc_en <= 1'b0;
	crc_in_sel <= 1'b0;
	crc_shift_en <= 1'b0;
	out_reg_data_sel <= 1'b1;
	regsel_ld_en <= 1'b0;
	intreg_ld_en <= 1'b0;
	top_inhibit_o <= 1'b0;

	case(module_state)
	  `STATE_idle:
	    begin
	       addr_sel <= 1'b0;
	       word_ct_sel <= 1'b0;
	       

	       if(module_select_i & shift_dr_i) out_reg_shift_en <= 1'b1;
	       if(module_select_i & capture_dr_i) 
		 begin
		    out_reg_data_sel <= 1'b1;
		    out_reg_ld_en <= 1'b1;
		 end
	       if(module_select_i & module_cmd & update_dr_i) begin
		  if(intreg_instruction) regsel_ld_en <= 1'b1;
		  if(intreg_write)       intreg_ld_en <= 1'b1;
	       end
	       

	       if(module_next_state != `STATE_idle) begin
		  addr_ct_en <= 1'b1;
		  op_reg_en <= 1'b1;
		  bit_ct_rst <= 1'b1;
		  word_ct_en <= 1'b1;
		  crc_clr <= 1'b1;
	       end
	    end

	  `STATE_Rbegin:
	    begin
	       if(!word_count_zero) begin
		  biu_strobe <= 1'b1;
		  addr_sel <= 1'b1;
		  addr_ct_en <= 1'b1;
	       end
	    end

	  `STATE_Rready:
	    ;
	  
	  `STATE_Rstatus:
	    begin
	       tdo_output_sel <= 2'h0;
	       top_inhibit_o <= 1'b1;
	       
	       if (module_next_state == `STATE_Rburst) 
	       begin
	         out_reg_data_sel <= 1'b0;
	         out_reg_ld_en <= 1'b1;
	         bit_ct_rst <= 1'b1;
	         word_ct_sel <= 1'b1;
	         word_ct_en <= 1'b1;
	         if(!(decremented_word_count == 0) && !word_count_zero)
	         begin
	           biu_strobe <= 1'b1;
	           addr_sel <= 1'b1;
	           addr_ct_en <= 1'b1;
	         end
	       end
	    end

	  `STATE_Rburst:
	    begin
	       tdo_output_sel <= 2'h1;
	       out_reg_shift_en <= 1'b1;
	       bit_ct_en <= 1'b1;
	       crc_en <= 1'b1;
	       crc_in_sel <= 1'b0;
	       top_inhibit_o <= 1'b1;
	       
`ifdef ADBG_USE_HISPEED
	       if(bit_count_max)
	       begin
	         out_reg_data_sel <= 1'b0;
	         out_reg_ld_en <= 1'b1;
	         bit_ct_rst <= 1'b1;
	         word_ct_sel <= 1'b1;
	         word_ct_en <= 1'b1;
	         if(!(decremented_word_count == 0) && !word_count_zero)
	         begin
	           biu_strobe <= 1'b1;
	           addr_sel <= 1'b1;
	           addr_ct_en <= 1'b1;
	         end
	       end
`endif	       
	    end

	  `STATE_Rcrc:
	    begin

	       tdo_output_sel <= 2'h3;
	       crc_shift_en <= 1'b1;
	       top_inhibit_o <= 1'b1;
	    end

	  `STATE_Wready:
	    ;

	  `STATE_Wwait:
	    begin
	       tdo_output_sel <= 2'h1;
	       top_inhibit_o <= 1'b1;
	       if(module_next_state == `STATE_Wburst) begin
		  bit_ct_en <= 1'b1;
		  word_ct_sel <= 1'b1;
		  word_ct_en <= 1'b1;
		  crc_en <= 1'b1;
		  crc_in_sel <= 1'b1;
	       end
	    end

	  `STATE_Wburst:
	    begin
	       bit_ct_en <= 1'b1;
	       tdo_output_sel <= 2'h1;
	       crc_en <= 1'b1;
	       crc_in_sel <= 1'b1;
	       top_inhibit_o <= 1'b1;
	       
`ifdef ADBG_USE_HISPEED


	       if(bit_count_max)
		      begin
		      bit_ct_rst <= 1'b1;


		      biu_strobe <= 1'b1;
		      addr_ct_en <= 1'b1;


		      word_ct_sel <= 1'b1;
		      word_ct_en <= 1'b1;
		      end
`endif		       
	    end

	  `STATE_Wstatus:
	    begin
	       tdo_output_sel <= 2'h0;

	       biu_strobe <= 1'b1;
	       word_ct_sel <= 1'b1;
	       word_ct_en <= 1'b1;
	       bit_ct_rst <= 1'b1;
	       addr_ct_en <= 1'b1;
	       top_inhibit_o <= 1'b1;
	    end
	  
	  `STATE_Wcrc:
	    begin
               bit_ct_en <= 1'b1;
               top_inhibit_o <= 1'b1;
               if(module_next_state == `STATE_Wmatch) tdo_output_sel <= 2'h2;
	    end
	  
	  `STATE_Wmatch:
	    begin
               tdo_output_sel <= 2'h2;
               top_inhibit_o <= 1'b1;
	    end

	  default: ;
	endcase
     end


endmodule
module adbg_or1k_module (

			 tck_i,
			 module_tdo_o,
			 tdi_i,


			 capture_dr_i,
			 shift_dr_i,
			 update_dr_i,

			 data_register_i,
			 module_select_i,
			 top_inhibit_o,
			 rst_i,


			 cpu_clk_i, 
			 cpu_addr_o, 
			 cpu_data_i, 
			 cpu_data_o,
			 cpu_bp_i,
			 cpu_stall_o,
			 cpu_stb_o,
			 cpu_we_o,
			 cpu_ack_i,
			 cpu_rst_o
			 );



   input         tck_i;
   output        module_tdo_o;
   input         tdi_i;


   input         capture_dr_i;
   input         shift_dr_i;
   input         update_dr_i;

   input [52:0]  data_register_i;
   input         module_select_i;
   output        top_inhibit_o;
   input         rst_i;


   input 	 cpu_clk_i;
   output [31:0] cpu_addr_o;
   input [31:0]  cpu_data_i;
   output [31:0] cpu_data_o;
   output 	 cpu_stb_o;
   output 	 cpu_we_o;
   input 	 cpu_ack_i;
   output 	 cpu_rst_o;
   input 	 cpu_bp_i;
   output 	 cpu_stall_o;


   reg 		 module_tdo_o;
   reg 		 top_inhibit_o;



   reg [31:0] 	 address_counter;
   reg [5:0] 	 bit_count;
   reg [15:0] 	 word_count;
   reg [3:0] 	 operation;
   reg [31:0] 	 data_out_shift_reg;
   reg [`DBG_OR1K_REGSELECT_SIZE-1:0] internal_register_select;
   wire [1:0] 			      internal_reg_status;



   reg 				      addr_sel;
   reg 				      addr_ct_en;
   reg 				      op_reg_en;
   reg 				      bit_ct_en;
   reg 				      bit_ct_rst;
   reg 				      word_ct_sel;
   reg 				      word_ct_en;
   reg 				      out_reg_ld_en;
   reg 				      out_reg_shift_en;
   reg 				      out_reg_data_sel;
   reg [1:0] 			      tdo_output_sel;
   reg 				      biu_strobe;
   reg 				      crc_clr;
   reg 				      crc_en;
   reg 				      crc_in_sel;
   reg 				      crc_shift_en;
   reg 				      regsel_ld_en;
   reg 				      intreg_ld_en;



   wire 			      word_count_zero;
   wire 			      bit_count_max;
   wire 			      module_cmd;
   wire 			      biu_ready;
   wire 			      burst_instruction;
   wire 			      intreg_instruction;
   wire 			      intreg_write;
   wire 			      rd_op;
   wire 			      crc_match;
   wire 			      bit_count_32;


   wire [5:0] 			      word_size_bits;
   wire [2:0] 			      address_increment;
   wire [32:0] 			      incremented_address;
   wire [31:0] 			      data_to_addr_counter;
   wire [15:0] 			      data_to_word_counter;
   wire [15:0] 			      decremented_word_count;
   wire [31:0] 			      address_data_in;
   wire [15:0] 			      count_data_in;
   wire [3:0] 			      operation_in;
   wire [31:0] 			      data_to_biu;
   wire [31:0] 			      data_from_biu;
   wire [31:0] 			      crc_data_out;
   wire 			      crc_data_in;
   wire 			      crc_serial_out;
   wire [`DBG_OR1K_REGSELECT_SIZE-1:0] reg_select_data;
   wire [31:0] 			       out_reg_data;
   reg [31:0] 			       data_from_internal_reg;
   wire 			       status_reg_wr;





       assign module_cmd = ~(data_register_i[52]);
   assign     operation_in = data_register_i[51:48];
   assign     address_data_in = data_register_i[47:16];
   assign     count_data_in = data_register_i[15:0];
`ifdef ADBG_USE_HISPEED
   assign     data_to_biu = {tdi_i,data_register_i[52:22]};
`else   
   assign     data_to_biu = data_register_i[52:21];
`endif   
   assign     reg_select_data = data_register_i[47:(47-(`DBG_OR1K_REGSELECT_SIZE-1))];





   assign     burst_instruction = (operation_in == `DBG_OR1K_CMD_BWRITE32) | (operation_in == `DBG_OR1K_CMD_BREAD32);
   assign     intreg_instruction = ((operation_in == `DBG_OR1K_CMD_IREG_WR) | (operation_in == `DBG_OR1K_CMD_IREG_SEL));
   assign     intreg_write = (operation_in == `DBG_OR1K_CMD_IREG_WR);


   assign     word_size_bits = 5'd31;
   assign     address_increment = 3'd1;



   assign     rd_op = operation[2];






   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i) internal_register_select = 1'h0;
	else if(regsel_ld_en) internal_register_select = reg_select_data;
     end



   always @ (internal_register_select or internal_reg_status)
     begin
	case(internal_register_select) 
          `DBG_OR1K_INTREG_STATUS: data_from_internal_reg = {30'h0, internal_reg_status};
          default: data_from_internal_reg = {30'h0, internal_reg_status};
	endcase
     end
   









   assign status_reg_wr = (intreg_ld_en & (reg_select_data == `DBG_OR1K_INTREG_STATUS));

   adbg_or1k_status_reg or1k_statusreg_i (
				     .data_i(data_register_i[(47-`DBG_OR1K_REGSELECT_SIZE):(47-(`DBG_OR1K_REGSELECT_SIZE+1))]), 
				     .we_i(status_reg_wr),
				     .tck_i(tck_i),
				     .bp_i(cpu_bp_i),
				     .rst_i(rst_i),
				     .cpu_clk_i(cpu_clk_i),
				     .ctrl_reg_o(internal_reg_status),
				     .cpu_stall_o(cpu_stall_o),
				     .cpu_rst_o(cpu_rst_o)
				     );





     assign data_to_addr_counter = (addr_sel) ? incremented_address[31:0] : address_data_in;
   assign   incremented_address = address_counter + address_increment;



   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  address_counter <= 32'h0;
	else if(addr_ct_en)
	  address_counter <= data_to_addr_counter;
     end




   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  operation <= 4'h0;
	else if(op_reg_en)
	  operation <= operation_in;
     end




   always @ (posedge tck_i or posedge rst_i)
     begin

	if(rst_i)             bit_count <= 6'h0;
	else if(bit_ct_rst)  bit_count <= 6'h0;
	else if(bit_ct_en)    bit_count <= bit_count + 6'h1;

     end

   assign bit_count_max = (bit_count == word_size_bits) ? 1'b1 : 1'b0 ;
   assign bit_count_32 = (bit_count == 6'h20) ? 1'b1 : 1'b0;




   assign data_to_word_counter = (word_ct_sel) ?  decremented_word_count : count_data_in;
   assign decremented_word_count = word_count - 16'h1;



   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  word_count <= 16'h0;
	else if(word_ct_en)
	  word_count <= data_to_word_counter;
     end

   assign word_count_zero = (word_count == 16'h0);




			    assign out_reg_data = (out_reg_data_sel) ? data_from_internal_reg : data_from_biu;

   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i) data_out_shift_reg <= 32'h0;
	else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data;
	else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[31:1]};
     end


   always @ (tdo_output_sel or data_out_shift_reg[0] or biu_ready or crc_match or crc_serial_out)
     begin
	if(tdo_output_sel == 2'h0) module_tdo_o <= biu_ready;
	else if(tdo_output_sel == 2'h1) module_tdo_o <= data_out_shift_reg[0];
	else if(tdo_output_sel == 2'h2) module_tdo_o <= crc_match;
	else module_tdo_o <= crc_serial_out;
     end







   adbg_or1k_biu or1k_biu_i (

			     .tck_i           (tck_i),
			     .rst_i           (rst_i),
			     .data_i          (data_to_biu),
			     .data_o          (data_from_biu),
			     .addr_i          (address_counter),
			     .strobe_i        (biu_strobe),
			     .rd_wrn_i        (rd_op),
			     .rdy_o           (biu_ready),

			     

			     .cpu_clk_i(cpu_clk_i),
			     .cpu_addr_o(cpu_addr_o),
			     .cpu_data_i(cpu_data_i),
			     .cpu_data_o(cpu_data_o),
			     .cpu_stb_o(cpu_stb_o),
			     .cpu_we_o(cpu_we_o),
			     .cpu_ack_i(cpu_ack_i)
			     );






     assign crc_data_in = (crc_in_sel) ? tdi_i : data_out_shift_reg[0];

   adbg_crc32 or1k_crc_i
     (
      .clk(tck_i), 
      .data(crc_data_in),
      .enable(crc_en),
      .shift(crc_shift_en),
      .clr(crc_clr),
      .rst(rst_i),
      .crc_out(crc_data_out),
      .serial_out(crc_serial_out)
      );

   assign   crc_match = (data_register_i[52:21] == crc_data_out) ? 1'b1 : 1'b0;








`define STATE_idle     4'h0
`define STATE_Rbegin   4'h1
`define STATE_Rready   4'h2
`define STATE_Rstatus  4'h3
`define STATE_Rburst   4'h4
`define STATE_Wready   4'h5
`define STATE_Wwait    4'h6
`define STATE_Wburst   4'h7
`define STATE_Wstatus  4'h8
`define STATE_Rcrc     4'h9
`define STATE_Wcrc     4'ha
`define STATE_Wmatch   4'hb

   reg [3:0] module_state;
   reg [3:0] module_next_state;




   always @ (posedge tck_i or posedge rst_i)
     begin
	if(rst_i)
	  module_state <= `STATE_idle;
	else
	  module_state <= module_next_state;
     end



   always @ (module_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or operation_in[2]
	     or word_count_zero or bit_count_max or data_register_i[52] or bit_count_32 or biu_ready
	     or module_cmd or intreg_write or decremented_word_count or burst_instruction)
     begin
	case(module_state)
	  `STATE_idle:
	    begin
	       if(module_cmd && module_select_i && update_dr_i && burst_instruction && operation_in[2]) module_next_state <= `STATE_Rbegin;
	       else if(module_cmd && module_select_i && update_dr_i && burst_instruction) module_next_state <= `STATE_Wready;
	       else module_next_state <= `STATE_idle;
	    end

	  `STATE_Rbegin:
	    begin
	       if(word_count_zero) module_next_state <= `STATE_idle;
	       else module_next_state <= `STATE_Rready;
	    end
	  `STATE_Rready:
	    begin
	       if(module_select_i && capture_dr_i) module_next_state <= `STATE_Rstatus;
	       else module_next_state <= `STATE_Rready;
	    end
	  `STATE_Rstatus:
	    begin
	       if(update_dr_i) module_next_state <= `STATE_idle; 
	       else if (biu_ready) module_next_state <= `STATE_Rburst;
	       else module_next_state <= `STATE_Rstatus;
	    end
	  `STATE_Rburst:
	    begin
	       if(update_dr_i) module_next_state <= `STATE_idle; 
	       else if(bit_count_max && word_count_zero) module_next_state <= `STATE_Rcrc;
`ifndef ADBG_USE_HISPEED         
	       else if(bit_count_max) module_next_state <= `STATE_Rstatus;
`endif	         
	       else module_next_state <= `STATE_Rburst;
	    end
	  `STATE_Rcrc:
	    begin
	       if(update_dr_i) module_next_state <= `STATE_idle;

	       else module_next_state <= `STATE_Rcrc;    
	    end

	  `STATE_Wready:
	    begin
	       if(word_count_zero) module_next_state <= `STATE_idle;
	       else if(module_select_i && capture_dr_i) module_next_state <= `STATE_Wwait;
	       else module_next_state <= `STATE_Wready;
	    end
	  `STATE_Wwait:
	    begin
	       if(update_dr_i)  module_next_state <= `STATE_idle;
	       else if(module_select_i && data_register_i[52]) module_next_state <= `STATE_Wburst;
	       else module_next_state <= `STATE_Wwait;
	    end
	  `STATE_Wburst:
	    begin
	       if(update_dr_i)  module_next_state <= `STATE_idle;
	       else if(bit_count_max) 
	         begin
`ifdef ADBG_USE_HISPEED
		        if(word_count_zero) module_next_state <= `STATE_Wcrc;
		        else module_next_state <= `STATE_Wburst;
`else	           
	         module_next_state <= `STATE_Wstatus;
`endif	           
	         end
	       else module_next_state <= `STATE_Wburst;
	    end
	  `STATE_Wstatus:
	    begin
	       if(update_dr_i)  module_next_state <= `STATE_idle;
	       else if(word_count_zero) module_next_state <= `STATE_Wcrc;



	       else module_next_state <= `STATE_Wburst;
	    end
	  
	  `STATE_Wcrc:
	    begin
	       if(update_dr_i)  module_next_state <= `STATE_idle;
	       else if(bit_count_32) module_next_state <= `STATE_Wmatch;
	       else module_next_state <= `STATE_Wcrc;    
	    end
	  
	  `STATE_Wmatch:
	    begin
	       if(update_dr_i)  module_next_state <= `STATE_idle;

	       else module_next_state <= `STATE_Wmatch;    
	    end

	  default: module_next_state <= `STATE_idle;
	endcase
     end



   always @ (module_state or module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or operation_in[2]
	     or word_count_zero or bit_count_max or data_register_i[52] or biu_ready or intreg_instruction
	     or module_cmd or intreg_write or decremented_word_count)
     begin

	addr_sel <= 1'b1;
	addr_ct_en <= 1'b0;
	op_reg_en <= 1'b0;
	bit_ct_en <= 1'b0;
	bit_ct_rst <= 1'b0;
	word_ct_sel <= 1'b1;
	word_ct_en <= 1'b0;
	out_reg_ld_en <= 1'b0;
	out_reg_shift_en <= 1'b0;
	tdo_output_sel <= 2'b1;
	biu_strobe <= 1'b0;
	crc_clr <= 1'b0;
	crc_en <= 1'b0;
	crc_in_sel <= 1'b0;
	crc_shift_en <= 1'b0;
	out_reg_data_sel <= 1'b1;
	regsel_ld_en <= 1'b0;
	intreg_ld_en <= 1'b0;
	top_inhibit_o <= 1'b0;

	case(module_state)
	  `STATE_idle:
	    begin
	       addr_sel <= 1'b0;
	       word_ct_sel <= 1'b0;
	       

	       if(module_select_i & shift_dr_i) out_reg_shift_en <= 1'b1;
	       if(module_select_i & capture_dr_i) 
		 begin
		    out_reg_data_sel <= 1'b1;
		    out_reg_ld_en <= 1'b1;
		 end
	       if(module_select_i & module_cmd & update_dr_i) begin
		  if(intreg_instruction) regsel_ld_en <= 1'b1;
		  if(intreg_write)       intreg_ld_en <= 1'b1;
	       end
	       

	       if(module_next_state != `STATE_idle) begin
		  addr_ct_en <= 1'b1;
		  op_reg_en <= 1'b1;
		  bit_ct_rst <= 1'b1;
		  word_ct_en <= 1'b1;
		  crc_clr <= 1'b1;
	       end
	    end

	  `STATE_Rbegin:
	    begin
	       if(!word_count_zero) begin
		  biu_strobe <= 1'b1;
		  addr_sel <= 1'b1;
		  addr_ct_en <= 1'b1;
	       end
	    end

	  `STATE_Rready:
	    ;
	  
	  `STATE_Rstatus:
	    begin
	       tdo_output_sel <= 2'h0;
	       top_inhibit_o <= 1'b1;
	       
	       if (module_next_state == `STATE_Rburst) 
	       begin
	         out_reg_data_sel <= 1'b0;
	         out_reg_ld_en <= 1'b1;
	         bit_ct_rst <= 1'b1;
	         word_ct_sel <= 1'b1;
	         word_ct_en <= 1'b1;
	         if(!(decremented_word_count == 0) && !word_count_zero)
	         begin
	           biu_strobe <= 1'b1;
	           addr_sel <= 1'b1;
	           addr_ct_en <= 1'b1;
	         end
	       end
	    end

	  `STATE_Rburst:
	    begin
	       tdo_output_sel <= 2'h1;
	       out_reg_shift_en <= 1'b1;
	       bit_ct_en <= 1'b1;
	       crc_en <= 1'b1;
	       crc_in_sel <= 1'b0;
	       top_inhibit_o <= 1'b1;
	       
`ifdef ADBG_USE_HISPEED
	       if(bit_count_max)
	       begin
	         out_reg_data_sel <= 1'b0;
	         out_reg_ld_en <= 1'b1;
	         bit_ct_rst <= 1'b1;
	         word_ct_sel <= 1'b1;
	         word_ct_en <= 1'b1;
	         if(!(decremented_word_count == 0) && !word_count_zero)
	         begin
	           biu_strobe <= 1'b1;
	           addr_sel <= 1'b1;
	           addr_ct_en <= 1'b1;
	         end
	       end
`endif	       
	    end

	  `STATE_Rcrc:
	    begin

	       tdo_output_sel <= 2'h3;
	       crc_shift_en <= 1'b1;
	       top_inhibit_o <= 1'b1;
	    end

	  `STATE_Wready:
	    ;

	  `STATE_Wwait:
	    begin
	       tdo_output_sel <= 2'h1;
	       top_inhibit_o <= 1'b1;
	       if(module_next_state == `STATE_Wburst) begin
		  bit_ct_en <= 1'b1;
		  word_ct_sel <= 1'b1;
		  word_ct_en <= 1'b1;
		  crc_en <= 1'b1;
		  crc_in_sel <= 1'b1;
	       end
	    end

	  `STATE_Wburst:
	    begin
	       bit_ct_en <= 1'b1;
	       tdo_output_sel <= 2'h1;
	       crc_en <= 1'b1;
	       crc_in_sel <= 1'b1;
	       top_inhibit_o <= 1'b1;
	       
`ifdef ADBG_USE_HISPEED


	       if(bit_count_max)
		      begin
		      bit_ct_rst <= 1'b1;


		      biu_strobe <= 1'b1;
		      addr_ct_en <= 1'b1;


		      word_ct_sel <= 1'b1;
		      word_ct_en <= 1'b1;
		      end
`endif		       
	    end

	  `STATE_Wstatus:
	    begin
	       tdo_output_sel <= 2'h0;

	       biu_strobe <= 1'b1;
	       word_ct_sel <= 1'b1;
	       word_ct_en <= 1'b1;
	       bit_ct_rst <= 1'b1;
	       addr_ct_en <= 1'b1;
	       top_inhibit_o <= 1'b1;
	    end
	  
	  `STATE_Wcrc:
	    begin
               bit_ct_en <= 1'b1;
               top_inhibit_o <= 1'b1;
               if(module_next_state == `STATE_Wmatch) tdo_output_sel <= 2'h2;
	    end
	  
	  `STATE_Wmatch:
	    begin
               tdo_output_sel <= 2'h2;
               top_inhibit_o <= 1'b1;
	    end

	  default: ;
	endcase
     end


endmodule