data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:68: Operator EQ expects 2 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                               : ... In instance jelly_cpu_alu\n    assign adder_in_carry = (op_adder_func == 1\'b1) ? 1\'b1 : 1\'b0;\n                                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:70: Cannot find file containing module: \'jelly_cpu_adder\'\n    jelly_cpu_adder\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/mipsi,data/full_repos/permissive/2084115/jelly_cpu_adder\n             data/full_repos/permissive/2084115/rtl/mipsi,data/full_repos/permissive/2084115/jelly_cpu_adder.v\n             data/full_repos/permissive/2084115/rtl/mipsi,data/full_repos/permissive/2084115/jelly_cpu_adder.sv\n             jelly_cpu_adder\n             jelly_cpu_adder.v\n             jelly_cpu_adder.sv\n             obj_dir/jelly_cpu_adder\n             obj_dir/jelly_cpu_adder.v\n             obj_dir/jelly_cpu_adder.sv\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:89: Operator OR expects 32 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                               : ... In instance jelly_cpu_alu\n                            | (op_logic_func == 2\'b01)  ?  (in_data0 | in_data1) : {DATA_WIDTH{1\'b0}}\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:89: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 32 bits.\n                                                                               : ... In instance jelly_cpu_alu\n                            | (op_logic_func == 2\'b01)  ?  (in_data0 | in_data1) : {DATA_WIDTH{1\'b0}}\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:90: Operator OR expects 32 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                               : ... In instance jelly_cpu_alu\n                            | (op_logic_func == 2\'b10) ?  (in_data0 ^ in_data1) : {DATA_WIDTH{1\'b0}}\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:90: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 32 bits.\n                                                                               : ... In instance jelly_cpu_alu\n                            | (op_logic_func == 2\'b10) ?  (in_data0 ^ in_data1) : {DATA_WIDTH{1\'b0}}\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:91: Operator OR expects 32 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                               : ... In instance jelly_cpu_alu\n                            | (op_logic_func == 2\'b11) ? ~(in_data0 | in_data1) : {DATA_WIDTH{1\'b0}};\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:91: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 32 bits.\n                                                                               : ... In instance jelly_cpu_alu\n                            | (op_logic_func == 2\'b11) ? ~(in_data0 | in_data1) : {DATA_WIDTH{1\'b0}};\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:95: Operator EQ expects 2 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                               : ... In instance jelly_cpu_alu\n    assign comp_out_data[0] = (op_comp_func == 1\'b1) ? (out_negative != out_overflow) : ~out_carry;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:100: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'op_logic_en\' generates 1 bits.\n                                                                                : ... In instance jelly_cpu_alu\n                    | op_logic_en ? logic_out_data : {DATA_WIDTH{1\'b0}}\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:100: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 32 bits.\n                                                                                : ... In instance jelly_cpu_alu\n                    | op_logic_en ? logic_out_data : {DATA_WIDTH{1\'b0}}\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:101: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'op_comp_en\' generates 1 bits.\n                                                                                : ... In instance jelly_cpu_alu\n                    | op_comp_en  ? comp_out_data  : {DATA_WIDTH{1\'b0}};\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/mipsi/jelly_cpu_alu.v:101: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 32 bits.\n                                                                                : ... In instance jelly_cpu_alu\n                    | op_comp_en  ? comp_out_data  : {DATA_WIDTH{1\'b0}};\n                                  ^\n%Error: Exiting due to 1 error(s), 12 warning(s)\n'
module jelly_cpu_alu
        #(
            parameter                           DATA_SIZE  = 5,
            parameter                           DATA_WIDTH = (1 << DATA_SIZE)
        )
        (
            input   wire                        op_adder_en,
            input   wire    [1:0]               op_adder_func,

            input   wire                        op_logic_en,
            input   wire    [1:0]               op_logic_func,
            
            input   wire                        op_comp_en,
            input   wire    [1:0]               op_comp_func,
            
            input   wire    [DATA_WIDTH-1:0]    in_data0,
            input   wire    [DATA_WIDTH-1:0]    in_data1,
            
            output  wire    [DATA_WIDTH-1:0]    out_data,
            output  wire                        out_carry,
            output  wire                        out_overflow,
            output  wire                        out_negative,
            output  wire                        out_zero
        );
    

    wire    [DATA_WIDTH-1:0]    adder_in_data0;
    wire    [DATA_WIDTH-1:0]    adder_in_data1;
    wire                        adder_in_carry;
    wire    [DATA_WIDTH-1:0]    adder_out_data;
    
    assign adder_in_data0 = in_data0;
    assign adder_in_data1 = (op_adder_func[0] ? ~in_data1 : in_data1) &
                            (op_adder_func[1] ? {DATA_WIDTH{1'b0}} : {DATA_WIDTH{1'b1}});
    
    assign adder_in_carry = (op_adder_func == `ALU_ADDER_FUNC_SUB) ? 1'b1 : 1'b0;
    
    jelly_cpu_adder
        i_cpu_adder
            (
                .in_data0       (adder_in_data0),
                .in_data1       (adder_in_data1),
                .in_carry       (adder_in_carry),
            
                .out_data       (adder_out_data),
            
                .out_carry      (out_carry),
                .out_overflow   (out_overflow),
                .out_negative   (out_negative),
                .out_zero       (out_zero)
            );
    
    

    wire    [DATA_WIDTH-1:0]    logic_out_data;
    assign logic_out_data = (op_logic_func == `ALU_LOGIC_FUNC_AND) ?  (in_data0 & in_data1) : {DATA_WIDTH{1'b0}}
                            | (op_logic_func == `ALU_LOGIC_FUNC_OR)  ?  (in_data0 | in_data1) : {DATA_WIDTH{1'b0}}
                            | (op_logic_func == `ALU_LOGIC_FUNC_XOR) ?  (in_data0 ^ in_data1) : {DATA_WIDTH{1'b0}}
                            | (op_logic_func == `ALU_LOGIC_FUNC_NOR) ? ~(in_data0 | in_data1) : {DATA_WIDTH{1'b0}};
    

    wire    [DATA_WIDTH-1:0]    comp_out_data;
    assign comp_out_data[0] = (op_comp_func == `ALU_COMP_FUNC_SLT) ? (out_negative != out_overflow) : ~out_carry;
    assign comp_out_data[DATA_WIDTH-1:1] = 0;
    

    assign out_data = op_adder_en ? adder_out_data : {DATA_WIDTH{1'b0}}
                    | op_logic_en ? logic_out_data : {DATA_WIDTH{1'b0}}
                    | op_comp_en  ? comp_out_data  : {DATA_WIDTH{1'b0}};
    
    
endmodule
module jelly_cpu_alu
        #(
            parameter                           DATA_SIZE  = 5,
            parameter                           DATA_WIDTH = (1 << DATA_SIZE)
        )
        (
            input   wire                        op_adder_en,
            input   wire    [1:0]               op_adder_func,

            input   wire                        op_logic_en,
            input   wire    [1:0]               op_logic_func,
            
            input   wire                        op_comp_en,
            input   wire    [1:0]               op_comp_func,
            
            input   wire    [DATA_WIDTH-1:0]    in_data0,
            input   wire    [DATA_WIDTH-1:0]    in_data1,
            
            output  wire    [DATA_WIDTH-1:0]    out_data,
            output  wire                        out_carry,
            output  wire                        out_overflow,
            output  wire                        out_negative,
            output  wire                        out_zero
        );

    

    wire    [DATA_WIDTH-1:0]    adder_in_data0;
    wire    [DATA_WIDTH-1:0]    adder_in_data1;
    wire                        adder_in_carry;
    wire    [DATA_WIDTH-1:0]    adder_out_data;
    
    assign adder_in_data0 = in_data0;
    assign adder_in_data1 = (op_adder_func[0] ? ~in_data1 : in_data1) &
                            (op_adder_func[1] ? {DATA_WIDTH{1'b0}} : {DATA_WIDTH{1'b1}});
    
    assign adder_in_carry = (op_adder_func == `ALU_ADDER_FUNC_SUB) ? 1'b1 : 1'b0;
    
    jelly_cpu_adder
        i_cpu_adder
            (
                .in_data0       (adder_in_data0),
                .in_data1       (adder_in_data1),
                .in_carry       (adder_in_carry),
            
                .out_data       (adder_out_data),
            
                .out_carry      (out_carry),
                .out_overflow   (out_overflow),
                .out_negative   (out_negative),
                .out_zero       (out_zero)
            );
    
    

    wire    [DATA_WIDTH-1:0]    logic_out_data;
    assign logic_out_data = (op_logic_func == `ALU_LOGIC_FUNC_AND) ?  (in_data0 & in_data1) : {DATA_WIDTH{1'b0}}
                            | (op_logic_func == `ALU_LOGIC_FUNC_OR)  ?  (in_data0 | in_data1) : {DATA_WIDTH{1'b0}}
                            | (op_logic_func == `ALU_LOGIC_FUNC_XOR) ?  (in_data0 ^ in_data1) : {DATA_WIDTH{1'b0}}
                            | (op_logic_func == `ALU_LOGIC_FUNC_NOR) ? ~(in_data0 | in_data1) : {DATA_WIDTH{1'b0}};
    

    wire    [DATA_WIDTH-1:0]    comp_out_data;
    assign comp_out_data[0] = (op_comp_func == `ALU_COMP_FUNC_SLT) ? (out_negative != out_overflow) : ~out_carry;
    assign comp_out_data[DATA_WIDTH-1:1] = 0;
    

    assign out_data = op_adder_en ? adder_out_data : {DATA_WIDTH{1'b0}}
                    | op_logic_en ? logic_out_data : {DATA_WIDTH{1'b0}}
                    | op_comp_en  ? comp_out_data  : {DATA_WIDTH{1'b0}};
    
    
endmodule