data/full_repos/permissive/167489907/Data Path/Datapath Core/datapath_core.v
 line:51: before: "."
1: b'%Error: Cannot find file containing module: Path/Datapath\n        ... Looked in:\n             data/full_repos/permissive/167489907/Data/Path/Datapath\n             data/full_repos/permissive/167489907/Data/Path/Datapath.v\n             data/full_repos/permissive/167489907/Data/Path/Datapath.sv\n             Path/Datapath\n             Path/Datapath.v\n             Path/Datapath.sv\n             obj_dir/Path/Datapath\n             obj_dir/Path/Datapath.v\n             obj_dir/Path/Datapath.sv\n%Error: Cannot find file containing module: Core,data/full_repos/permissive/167489907\n%Error: Cannot find file containing module: data/full_repos/permissive/167489907/Data\n%Error: Cannot find file containing module: Core/datapath_core.v\n%Error: Exiting due to 4 error(s)\n'
module datapath_core(
	input clk,
	input rst,
	input AS,
	input [1:0] DS,
	input [1:0] PS,
	input PC_Sel,
	input K_Sel,
	input IL,
	input SL,
	input [4:0] FS,
	input C0,
	input MW,
	input RW,
	input [4:0] DA,
	input [4:0] SA, SB,
	input [63:0] K,
	output [15:0] r0, r1, r2, r3, r4, r5, r6, r7,
	output reg [3:0] SF,
	output [31:0] IR_Out);

wire EN_ADDR_ALU, EN_ADDR_PC, EN_DATA_ALU, EN_DATA_B, EN_DATA_PC, MR;
wire [3:0]Status;
wire [63:0] D;
wire [31:0] ADDR, PC_in, PC_out;



assign {EN_ADDR_PC, EN_ADDR_ALU} = AS == 1'b0 ? 2'b01 : 2'b10;


assign {MR, EN_DATA_PC, EN_DATA_B, EN_DATA_ALU} = DS == 2'b00 ? 4'b0001 :
																  DS == 2'b01 ? 4'b0010 :
																  DS == 2'b10 ? 4'b0100 :
																  DS == 2'b11 ? 4'b1000 : 4'b0001;



parameter STATUS_DEFAULT = 4'b0000;
always @(posedge clk or posedge rst)
	begin
		if (rst) SF <= STATUS_DEFAULT;
		else if (SL) SF <= Status;
		else SF <= SF;
	end


ram_datapath regfile_alu_ram(.W(RW), .clk(clk), .rst(rst), .EN_ALU(EN_DATA_ALU), .EN_B(EN_DATA_B), .EN_ADDR(EN_ADDR_ALU), 
.K_SEL(K_Sel), .PC_SEL(PC_Sel), .C0(C0), .WE(MW), .OE(MR), .SA(SA), .SB(SB), .DA(DA), .FS(FS), .K(K),
.Status(Status), .r0(r0), .r1(r1), .r2(r2), .r3(r3), .r4(r4), .r5(r5), .r6(r6), .r7(r7), .D(D), .ADDR(ADDR), .PC_in(PC_in));
defparam regfile_alu_ram.ram0.DATA_WIDTH = 64;
defparam regfile_alu_ram.ram0.ADDR_WIDTH = 12;





program_counter PC(.clk(clk), .rst(rst), .in(PC_in), .PS(PS), .out(PC_out));
defparam PC.PC_RESET_VALUE = 12'h800;


RegisterNbit IR(.Q(IR_Out), .D(D[31:0]), .L(IL), .R(rst), .clock(clk));
defparam IR.N = 32;


tribuf32 addr_pc(.in(PC_out), .control(EN_ADDR_PC), .out(ADDR));
tribuf64 data_pc(.in({32'b0, PC_out}), .control(EN_DATA_PC), .out(D));

	
endmodule
module datapath_core(
	input clk,
	input rst,
	input AS,
	input [1:0] DS,
	input [1:0] PS,
	input PC_Sel,
	input K_Sel,
	input IL,
	input SL,
	input [4:0] FS,
	input C0,
	input MW,
	input RW,
	input [4:0] DA,
	input [4:0] SA, SB,
	input [63:0] K,
	output [15:0] r0, r1, r2, r3, r4, r5, r6, r7,
	output reg [3:0] SF,
	output [31:0] IR_Out);


wire EN_ADDR_ALU, EN_ADDR_PC, EN_DATA_ALU, EN_DATA_B, EN_DATA_PC, MR;
wire [3:0]Status;
wire [63:0] D;
wire [31:0] ADDR, PC_in, PC_out;



assign {EN_ADDR_PC, EN_ADDR_ALU} = AS == 1'b0 ? 2'b01 : 2'b10;


assign {MR, EN_DATA_PC, EN_DATA_B, EN_DATA_ALU} = DS == 2'b00 ? 4'b0001 :
																  DS == 2'b01 ? 4'b0010 :
																  DS == 2'b10 ? 4'b0100 :
																  DS == 2'b11 ? 4'b1000 : 4'b0001;



parameter STATUS_DEFAULT = 4'b0000;
always @(posedge clk or posedge rst)
	begin
		if (rst) SF <= STATUS_DEFAULT;
		else if (SL) SF <= Status;
		else SF <= SF;
	end


ram_datapath regfile_alu_ram(.W(RW), .clk(clk), .rst(rst), .EN_ALU(EN_DATA_ALU), .EN_B(EN_DATA_B), .EN_ADDR(EN_ADDR_ALU), 
.K_SEL(K_Sel), .PC_SEL(PC_Sel), .C0(C0), .WE(MW), .OE(MR), .SA(SA), .SB(SB), .DA(DA), .FS(FS), .K(K),
.Status(Status), .r0(r0), .r1(r1), .r2(r2), .r3(r3), .r4(r4), .r5(r5), .r6(r6), .r7(r7), .D(D), .ADDR(ADDR), .PC_in(PC_in));
defparam regfile_alu_ram.ram0.DATA_WIDTH = 64;
defparam regfile_alu_ram.ram0.ADDR_WIDTH = 12;





program_counter PC(.clk(clk), .rst(rst), .in(PC_in), .PS(PS), .out(PC_out));
defparam PC.PC_RESET_VALUE = 12'h800;


RegisterNbit IR(.Q(IR_Out), .D(D[31:0]), .L(IL), .R(rst), .clock(clk));
defparam IR.N = 32;


tribuf32 addr_pc(.in(PC_out), .control(EN_ADDR_PC), .out(ADDR));
tribuf64 data_pc(.in({32'b0, PC_out}), .control(EN_DATA_PC), .out(D));

	
endmodule