data/full_repos/permissive/20270692/labs/lab7/mux21.v
data/verilator_xmls/09dea372-3ef6-4990-8550-b55bfce0b99a.xml
module mux21 (a, b, select, y);

  input a, b, select;
  wire a, b, select;

  output y;
  wire y;

  wire w1, w2;

  assign w1=a&(~select);
  assign w2=b&(select);

  assign y=w1|w2;

endmodule
module mux21 (a, b, select, y);


  input a, b, select;
  wire a, b, select;

  output y;
  wire y;

  wire w1, w2;

  assign w1=a&(~select);
  assign w2=b&(select);

  assign y=w1|w2;

endmodule