data/full_repos/permissive/174323821/hdl/cpu/j68/j68_dpram_2048x20.v
data/verilator_xmls/49853926-e656-47dc-bf12-059f0e2a7402.xml
module j68_dpram_2048x20
(

    input         clock,
    input         clocken,

    input         rden_a,
    input  [10:0] address_a,
    output reg [19:0] q_a,

    input   [1:0] wren_b,
    input  [10:0] address_b,
    input  [15:0] data_b,
    output reg [15:0] q_b
);
    parameter RAM_INIT_FILE = "j68_ram.mem";


    reg  [19:0] r_mem_blk [0:2047];

    initial begin
        $readmemb(RAM_INIT_FILE, r_mem_blk);
    end


    always@(posedge clock) begin : PORT_A
        if (rden_a & clocken) begin
            q_a <= r_mem_blk[address_a];
        end
    end


    always@(posedge clock) begin : PORT_B

        if (clocken) begin
            q_b <= r_mem_blk[address_b][15:0];
            if (wren_b[0]) begin
                r_mem_blk[address_b][7:0]  <= data_b[7:0];
            end
            if (wren_b[1]) begin
                r_mem_blk[address_b][15:8] <= data_b[15:8];
            end
        end
    end

endmodule
module j68_dpram_2048x20
(

    input         clock,
    input         clocken,

    input         rden_a,
    input  [10:0] address_a,
    output reg [19:0] q_a,

    input   [1:0] wren_b,
    input  [10:0] address_b,
    input  [15:0] data_b,
    output reg [15:0] q_b
);

    parameter RAM_INIT_FILE = "j68_ram.mem";


    reg  [19:0] r_mem_blk [0:2047];

    initial begin
        $readmemb(RAM_INIT_FILE, r_mem_blk);
    end


    always@(posedge clock) begin : PORT_A
        if (rden_a & clocken) begin
            q_a <= r_mem_blk[address_a];
        end
    end


    always@(posedge clock) begin : PORT_B

        if (clocken) begin
            q_b <= r_mem_blk[address_b][15:0];
            if (wren_b[0]) begin
                r_mem_blk[address_b][7:0]  <= data_b[7:0];
            end
            if (wren_b[1]) begin
                r_mem_blk[address_b][15:8] <= data_b[15:8];
            end
        end
    end

endmodule