data/full_repos/permissive/197356760/GCD/Datapath.v
1: b"%Error: data/full_repos/permissive/197356760/GCD/Datapath.v:20: Cannot find file containing module: 'mux3to1'\n mux3to1 #(width) mux_A (a, sub_out, reg_b_out, sel_a, a_mux_out);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197356760/GCD,data/full_repos/permissive/197356760/mux3to1\n             data/full_repos/permissive/197356760/GCD,data/full_repos/permissive/197356760/mux3to1.v\n             data/full_repos/permissive/197356760/GCD,data/full_repos/permissive/197356760/mux3to1.sv\n             mux3to1\n             mux3to1.v\n             mux3to1.sv\n             obj_dir/mux3to1\n             obj_dir/mux3to1.v\n             obj_dir/mux3to1.sv\n%Error: data/full_repos/permissive/197356760/GCD/Datapath.v:21: Cannot find file containing module: 'reg_module'\n reg_module #(width) reg_a (clk, en_a, a_mux_out, reg_a_out);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/197356760/GCD/Datapath.v:22: Cannot find file containing module: 'reg_module'\n reg_module #(width) reg_b (clk, en_b, b_mux_out, reg_b_out);\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module datapath #(parameter width = 8) 
				(input clk, rst, en_a, en_b,
				 input [width-1:0] a, b,
				 input [1:0] sel_a,
				 input sel_b,
				 output b_zero, a_lt_b,
				 output [width-1:0] result);
				 
	wire [width-1:0] reg_a_out, reg_b_out, a_mux_out, b_mux_out, sub_out;
	
	mux3to1 #(width) mux_A (a, sub_out, reg_b_out, sel_a, a_mux_out);
	reg_module #(width) reg_a (clk, en_a, a_mux_out, reg_a_out);
	reg_module #(width) reg_b (clk, en_b, b_mux_out, reg_b_out);
	
	assign b_zero = (reg_b_out == 0);
	assign a_lt_b = (reg_a_out < reg_b_out);
	assign b_mux_out = sel_b ? reg_a_out : b;
	assign sub_out = (reg_a_out - reg_b_out);
	assign result = reg_a_out;
	
endmodule
module datapath #(parameter width = 8) 
				(input clk, rst, en_a, en_b,
				 input [width-1:0] a, b,
				 input [1:0] sel_a,
				 input sel_b,
				 output b_zero, a_lt_b,
				 output [width-1:0] result);

				 
	wire [width-1:0] reg_a_out, reg_b_out, a_mux_out, b_mux_out, sub_out;
	
	mux3to1 #(width) mux_A (a, sub_out, reg_b_out, sel_a, a_mux_out);
	reg_module #(width) reg_a (clk, en_a, a_mux_out, reg_a_out);
	reg_module #(width) reg_b (clk, en_b, b_mux_out, reg_b_out);
	
	assign b_zero = (reg_b_out == 0);
	assign a_lt_b = (reg_a_out < reg_b_out);
	assign b_mux_out = sel_b ? reg_a_out : b;
	assign sub_out = (reg_a_out - reg_b_out);
	assign result = reg_a_out;
	
endmodule