data/full_repos/permissive/195227969/work/cold_store/oldram.v
1: b"%Error: data/full_repos/permissive/195227969/work/cold_store/oldram.v:125: Cannot find file containing module: 'SB_SPRAM256KA'\n               SB_SPRAM256KA sram\n               ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/195227969/work/cold_store,data/full_repos/permissive/195227969/SB_SPRAM256KA\n             data/full_repos/permissive/195227969/work/cold_store,data/full_repos/permissive/195227969/SB_SPRAM256KA.v\n             data/full_repos/permissive/195227969/work/cold_store,data/full_repos/permissive/195227969/SB_SPRAM256KA.sv\n             SB_SPRAM256KA\n             SB_SPRAM256KA.v\n             SB_SPRAM256KA.sv\n             obj_dir/SB_SPRAM256KA\n             obj_dir/SB_SPRAM256KA.v\n             obj_dir/SB_SPRAM256KA.sv\n%Error: Exiting due to 1 error(s)\n"
module m_ram
  # ( parameter HIGHLEVEL = 1,
      SRAMADRWIDTH = 16
      )
   (
    input         CLK_I,
    input [31:0]  DAT_I,
    input [31:0]  ADR_I,
    input         STB_I,
    input         WE_I,
    input [3:0]   SEL_I,
    output [31:0] DAT_O,
    output        ACK_O,
    output        m_ram_killwarnings
    );

   
   localparam SRAM_READLATENCY =  1;
   localparam SRAM_WRITELATENCY = 0;

   generate




      if ( SRAMADRWIDTH == 0 ) begin

         assign DAT_O = 32'h0;
         assign ACK_O = 1'b0;
         assign m_ram_killwarnings = CLK_I & STB_I & WE_I & &ADR_I & &DAT_I & &SEL_I;
      end else begin
         



         wire [(SRAMADRWIDTH-15)*32-1:0] o;
`ifdef verilator
         wire [(SRAMADRWIDTH-15)*32-1:0] zo;
`endif
         wire [SRAMADRWIDTH-16:0]        we;
         wire [7:0]                      srammask;
         wire                            readack;
         wire [31:0]                     preDAT_O;
         genvar                          j,k;
         
         assign srammask = {{2{SEL_I[3]}},{2{SEL_I[2]}},{2{SEL_I[1]}},{2{SEL_I[0]}}};
         
         for ( j = 0; j < SRAMADRWIDTH-15; j = j + 1 ) begin : blk0
            for ( k = 0; k < 2; k = k + 1 ) begin : blk1
               SB_SPRAM256KA sram
                      (
                       .DATAIN     ( DAT_I[k*16+15 : k*16]       ),
                       .ADDRESS    ( ADR_I[15 : 2]               ),
                       .MASKWREN   ( srammask[k*4+3 : k*4]       ),
                       .WREN       ( we[j]                       ),
                       .CLOCK      ( CLK_I                       ),
                       .CHIPSELECT ( 1'b1                        ),
                       .POWEROFF   ( 1'b1 ),
                       .STANDBY    ( 1'b0                        ),
                       .SLEEP      ( 1'b0                        ),
`ifdef verilator                       
                       .preDATAOUT ( zo[j*32+k*16+15 : j*32+k*16]),
`endif
                       .DATAOUT    ( o[j*32+k*16+15 : j*32+k*16] )
                       );
            end
         end
         
         if ( HIGHLEVEL != 0 ) begin



            wire                            writestrobe;
            wire                            writeack;
            wire                            readstrobe;
            
            assign writestrobe = STB_I & WE_I;
            if ( SRAM_WRITELATENCY == 0 ) begin
               assign writeack = writestrobe;
            end else begin

               reg [SRAM_WRITELATENCY:0] writeackdly;

               always @(posedge CLK_I) begin
                  if ( writeackdly == 0 )
                    writeackdly[SRAM_WRITELATENCY:0] <= {writestrobe,writeackdly[SRAM_WRITELATENCY:1]};
                  else
                    writeackdly[SRAM_WRITELATENCY:0] <= {1'b0,writeackdly[SRAM_WRITELATENCY:1]};
               end
               assign writeack = writeackdly[1];
            end
            
            assign readstrobe = STB_I & ~WE_I;
            if ( SRAM_READLATENCY == 0) begin
               assign readack = readstrobe;
            end else begin

               reg [SRAM_READLATENCY:0] readackdly;

               always @(posedge CLK_I) begin
                  if ( readackdly == 0 ) 
                    readackdly[SRAM_READLATENCY:0] <= {readstrobe,readackdly[SRAM_READLATENCY:1]};
                  else
                    readackdly[SRAM_READLATENCY:0] <= {1'b0,readackdly[SRAM_READLATENCY:1]};
               end
               assign readack = readackdly[1];
            end
            assign ACK_O = readack | writeack;
                        
            if ( SRAMADRWIDTH == 16 ) begin
               assign we[0] = writestrobe;
`ifdef verilator
               if ( SRAM_READLATENCY == 0 ) begin
                  assign preDAT_O = zo[31:0];
               end else begin
                  assign preDAT_O = o[31:0];
               end
`else
               assign preDAT_O = o[31:0];
`endif
            end else begin
               assign we[0] = writestrobe & ~ADR_I[16];
               assign we[1] = writestrobe &  ADR_I[16];

`ifdef verilator
               if ( SRAM_READLATENCY == 0 ) begin
                  assign preDAT_O = ADR_I[16] ? zo[63:32] : zo[31:0];
               end else begin
                  assign preDAT_O = ADR_I[16] ? o[63:32] : o[31:0];
               end
`else
               assign preDAT_O = ADR_I[16] ? o[63:32] : o[31:0];
`endif
            end
            
`ifdef verilator
            assign DAT_O = ACK_O ? preDAT_O : 32'habbababa;
`else
            assign DAT_O = preDAT_O;
`endif

         end else begin
            




            if ( SRAMADRWIDTH == 16 ) begin
               SB_LUT4 #(.LUT_INIT(16'h8888)) we_l(.O(we[0]), .I3(1'b0), .I2(1'b0), .I1(STB_I), .I0(WE_I)); 
               assign preDAT_O = o[31:0];
            end else begin
               SB_LUT4 #(.LUT_INIT(16'h0808)) we0_l(.O(we[0]), .I3(1'b0), .I2(ADR_I[16]), .I1(STB_I), .I0(WE_I));
               SB_LUT4 #(.LUT_INIT(16'h8080)) we1_l(.O(we[1]), .I3(1'b0), .I2(ADR_I[16]), .I1(STB_I), .I0(WE_I));

               assign preDAT_O = ADR_I[16] ? o[63:32] : o[31:0];
            end

            wire cmb_readack;
            SB_LUT4 #(.LUT_INIT(16'h0404)) readack_l(.O(cmb_readack), .I3(1'b0), .I2(readack), .I1(STB_I), .I0(WE_I)); 
            SB_DFF readack_r(.Q(readack), .C(CLK_I), .D(cmb_readack));





            

            SB_LUT4 #(.LUT_INIT(16'hf8f8)) ACK_O_l(.O(ACK_O), .I3(1'b0), .I2(readack), .I1(STB_I), .I0(WE_I)); 




`ifdef verilator
            assign DAT_O = ACK_O ? preDAT_O : 32'habbababa;
`else
            assign DAT_O = preDAT_O;
`endif
         end
         
         assign m_ram_killwarnings = &ADR_I |
`ifdef verilator                                     
                                     &zo |
`endif
                                     &o;            
         

      end
   endgenerate
   
endmodule
module m_ram
  # ( parameter HIGHLEVEL = 1,
      SRAMADRWIDTH = 16
      )
   (
    input         CLK_I,
    input [31:0]  DAT_I,
    input [31:0]  ADR_I,
    input         STB_I,
    input         WE_I,
    input [3:0]   SEL_I,
    output [31:0] DAT_O,
    output        ACK_O,
    output        m_ram_killwarnings
    );


   
   localparam SRAM_READLATENCY =  1;
   localparam SRAM_WRITELATENCY = 0;

   generate




      if ( SRAMADRWIDTH == 0 ) begin

         assign DAT_O = 32'h0;
         assign ACK_O = 1'b0;
         assign m_ram_killwarnings = CLK_I & STB_I & WE_I & &ADR_I & &DAT_I & &SEL_I;
      end else begin
         



         wire [(SRAMADRWIDTH-15)*32-1:0] o;
`ifdef verilator
         wire [(SRAMADRWIDTH-15)*32-1:0] zo;
`endif
         wire [SRAMADRWIDTH-16:0]        we;
         wire [7:0]                      srammask;
         wire                            readack;
         wire [31:0]                     preDAT_O;
         genvar                          j,k;
         
         assign srammask = {{2{SEL_I[3]}},{2{SEL_I[2]}},{2{SEL_I[1]}},{2{SEL_I[0]}}};
         
         for ( j = 0; j < SRAMADRWIDTH-15; j = j + 1 ) begin : blk0
            for ( k = 0; k < 2; k = k + 1 ) begin : blk1
               SB_SPRAM256KA sram
                      (
                       .DATAIN     ( DAT_I[k*16+15 : k*16]       ),
                       .ADDRESS    ( ADR_I[15 : 2]               ),
                       .MASKWREN   ( srammask[k*4+3 : k*4]       ),
                       .WREN       ( we[j]                       ),
                       .CLOCK      ( CLK_I                       ),
                       .CHIPSELECT ( 1'b1                        ),
                       .POWEROFF   ( 1'b1 ),
                       .STANDBY    ( 1'b0                        ),
                       .SLEEP      ( 1'b0                        ),
`ifdef verilator                       
                       .preDATAOUT ( zo[j*32+k*16+15 : j*32+k*16]),
`endif
                       .DATAOUT    ( o[j*32+k*16+15 : j*32+k*16] )
                       );
            end
         end
         
         if ( HIGHLEVEL != 0 ) begin



            wire                            writestrobe;
            wire                            writeack;
            wire                            readstrobe;
            
            assign writestrobe = STB_I & WE_I;
            if ( SRAM_WRITELATENCY == 0 ) begin
               assign writeack = writestrobe;
            end else begin

               reg [SRAM_WRITELATENCY:0] writeackdly;

               always @(posedge CLK_I) begin
                  if ( writeackdly == 0 )
                    writeackdly[SRAM_WRITELATENCY:0] <= {writestrobe,writeackdly[SRAM_WRITELATENCY:1]};
                  else
                    writeackdly[SRAM_WRITELATENCY:0] <= {1'b0,writeackdly[SRAM_WRITELATENCY:1]};
               end
               assign writeack = writeackdly[1];
            end
            
            assign readstrobe = STB_I & ~WE_I;
            if ( SRAM_READLATENCY == 0) begin
               assign readack = readstrobe;
            end else begin

               reg [SRAM_READLATENCY:0] readackdly;

               always @(posedge CLK_I) begin
                  if ( readackdly == 0 ) 
                    readackdly[SRAM_READLATENCY:0] <= {readstrobe,readackdly[SRAM_READLATENCY:1]};
                  else
                    readackdly[SRAM_READLATENCY:0] <= {1'b0,readackdly[SRAM_READLATENCY:1]};
               end
               assign readack = readackdly[1];
            end
            assign ACK_O = readack | writeack;
                        
            if ( SRAMADRWIDTH == 16 ) begin
               assign we[0] = writestrobe;
`ifdef verilator
               if ( SRAM_READLATENCY == 0 ) begin
                  assign preDAT_O = zo[31:0];
               end else begin
                  assign preDAT_O = o[31:0];
               end
`else
               assign preDAT_O = o[31:0];
`endif
            end else begin
               assign we[0] = writestrobe & ~ADR_I[16];
               assign we[1] = writestrobe &  ADR_I[16];

`ifdef verilator
               if ( SRAM_READLATENCY == 0 ) begin
                  assign preDAT_O = ADR_I[16] ? zo[63:32] : zo[31:0];
               end else begin
                  assign preDAT_O = ADR_I[16] ? o[63:32] : o[31:0];
               end
`else
               assign preDAT_O = ADR_I[16] ? o[63:32] : o[31:0];
`endif
            end
            
`ifdef verilator
            assign DAT_O = ACK_O ? preDAT_O : 32'habbababa;
`else
            assign DAT_O = preDAT_O;
`endif

         end else begin
            




            if ( SRAMADRWIDTH == 16 ) begin
               SB_LUT4 #(.LUT_INIT(16'h8888)) we_l(.O(we[0]), .I3(1'b0), .I2(1'b0), .I1(STB_I), .I0(WE_I)); 
               assign preDAT_O = o[31:0];
            end else begin
               SB_LUT4 #(.LUT_INIT(16'h0808)) we0_l(.O(we[0]), .I3(1'b0), .I2(ADR_I[16]), .I1(STB_I), .I0(WE_I));
               SB_LUT4 #(.LUT_INIT(16'h8080)) we1_l(.O(we[1]), .I3(1'b0), .I2(ADR_I[16]), .I1(STB_I), .I0(WE_I));

               assign preDAT_O = ADR_I[16] ? o[63:32] : o[31:0];
            end

            wire cmb_readack;
            SB_LUT4 #(.LUT_INIT(16'h0404)) readack_l(.O(cmb_readack), .I3(1'b0), .I2(readack), .I1(STB_I), .I0(WE_I)); 
            SB_DFF readack_r(.Q(readack), .C(CLK_I), .D(cmb_readack));





            

            SB_LUT4 #(.LUT_INIT(16'hf8f8)) ACK_O_l(.O(ACK_O), .I3(1'b0), .I2(readack), .I1(STB_I), .I0(WE_I)); 




`ifdef verilator
            assign DAT_O = ACK_O ? preDAT_O : 32'habbababa;
`else
            assign DAT_O = preDAT_O;
`endif
         end
         
         assign m_ram_killwarnings = &ADR_I |
`ifdef verilator                                     
                                     &zo |
`endif
                                     &o;            
         

      end
   endgenerate
   
endmodule