data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v
 line:307: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:170: Operator NEQ expects 32 bits on the RHS, but RHS\'s SEL generates 22 bits.\n                                                                                        : ... In instance ahb_master\nwire b1k_spec      = (haddr[0] + (1 << i_size)) >> 10 != haddr[0][31:10];\n                                                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:328: Operator NEQ expects 32 bits on the RHS, but RHS\'s SEL generates 22 bits.\n                                                                                        : ... In instance ahb_master\n        if ( addr + (val << (1 << sz )) >> 10 != addr[31:10] )\n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:254: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n                                                                                        : ... In instance ahb_master\n                                haddr[0]  <= !i_cont ? i_addr : haddr[0] + (rd_wr << i_size);\n                                                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:256: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n                                                                                        : ... In instance ahb_master\n                                                               !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size);\n                                                                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:259: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n                                                                                        : ... In instance ahb_master\n                                burst_ctr <= compute_burst_ctr(!i_cont ? i_min_len : beat_ctr - rd_wr, \n                                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:260: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'rd_wr\' generates 1 bits.\n                                                                                        : ... In instance ahb_master\n                                                               !i_cont ? i_addr : haddr[0] + (rd_wr << i_size) , i_size); \n                                                                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:262: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n                                                                                        : ... In instance ahb_master\n                                beat_ctr  <= !i_cont ? i_min_len : ((hburst == INCR) ? beat_ctr : beat_ctr - rd_wr); \n                                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:268: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s NEQ generates 1 bits.\n                                                                                        : ... In instance ahb_master\n                                haddr[0]  <= haddr[0] + ((htrans[0] != BUSY) << i_size);\n                                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:270: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n                                                                                        : ... In instance ahb_master\n                                burst_ctr <= o_hburst == INCR ? burst_ctr : (burst_ctr - rd_wr);\n                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/100152754/ahb_master/sources/ahb_master.v:271: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rd_wr\' generates 1 bits.\n                                                                                        : ... In instance ahb_master\n                                beat_ctr  <= o_hburst == INCR ? beat_ctr  : (beat_ctr  - rd_wr);\n                                                                                       ^\n%Error: Exiting due to 10 warning(s)\n'
function [2:0] compute_hburst (input [B:0] val, input [31:0] addr, input [2:0] sz);
begin
        compute_hburst =        (val >= 16 && no_cross(addr, 15, sz)) ? INCR16 :
                                (val >= 8  && no_cross(addr, 7, sz))  ? INCR8 :
                                (val >= 4  && no_cross(addr, 3, sz))  ? INCR4 : INCR;

        $display($time, "val = %d, addr = %d, sz = %d, compute_hburst = %d", val, addr, sz, compute_hburst);
end
endfunction
function [2:0] compute_hburst (input [B:0] val, input [31:0] addr, input [2:0] sz);

begin
        compute_hburst =        (val >= 16 && no_cross(addr, 15, sz)) ? INCR16 :
                                (val >= 8  && no_cross(addr, 7, sz))  ? INCR8 :
                                (val >= 4  && no_cross(addr, 3, sz))  ? INCR4 : INCR;

        $display($time, "val = %d, addr = %d, sz = %d, compute_hburst = %d", val, addr, sz, compute_hburst);
end
endfunction