data/full_repos/permissive/206783267/UART/DUT/uart_rx.v
 line:17: before: "["
1: b'%Warning-WIDTH: data/full_repos/permissive/206783267/UART/DUT/uart_rx.v:213: Logical Operator WHILE expects 1 bit on the For Test Condition, but For Test Condition\'s SHIFTR generates 32 bits.\n                                                                           : ... In instance uart_rx\n  while(v>>log2) \n  ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/206783267/UART/DUT/uart_rx.v:62: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'clk_count\' generates 10 bits.\n                                                                          : ... In instance uart_rx\n   if(clk_count == FREQ_COUNT)\n                ^~\n%Error: Exiting due to 2 warning(s)\n'
function integer log2(input integer v);
	begin
		log2=0;
		while(v>>log2) 
			log2=log2+1;
	end
endfunction
function integer log2(input integer v);

	begin
		log2=0;
		while(v>>log2) 
			log2=log2+1;
	end
endfunction