data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:1: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Data/Control/Control.v\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Data/Control/Control.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Data/Control/Control.v.sv\n             Data/Control/Control.v\n             Data/Control/Control.v.v\n             Data/Control/Control.v.sv\n             obj_dir/Data/Control/Control.v\n             obj_dir/Data/Control/Control.v.v\n             obj_dir/Data/Control/Control.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:2: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:3: Cannot find include file: Mips/Type/Bool.v\n`include "Mips/Type/Bool.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:5: Cannot find include file: Mips/Pipeline/Haz/Reg.v\n`include "Mips/Pipeline/Haz/Reg.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:6: Cannot find include file: Mips/Pipeline/Mem/Reg.v\n`include "Mips/Pipeline/Mem/Reg.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:7: Cannot find include file: Mips/Pipeline/Pc/Reg.v\n`include "Mips/Pipeline/Pc/Reg.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:8: Cannot find include file: Mips/Pipeline/Reg/Ex.v\n`include "Mips/Pipeline/Reg/Ex.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:9: Cannot find include file: Mips/Pipeline/Reg/Pc.v\n`include "Mips/Pipeline/Reg/Pc.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:10: Cannot find include file: Mips/Pipeline/Reg/Fwd.v\n`include "Mips/Pipeline/Reg/Fwd.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:11: Cannot find include file: Mips/Pipeline/Reg/Haz.v\n`include "Mips/Pipeline/Reg/Haz.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:13: Cannot find include file: Mips/Datapath/Register/datapath.v\n`include "Mips/Datapath/Register/datapath.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:14: Cannot find include file: Mips/Datapath/Register/stall.v\n`include "Mips/Datapath/Register/stall.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:15: Cannot find include file: Mips/Control/Control.v\n`include "Mips/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:16: Cannot find include file: Mips/Control/generate.v\n`include "Mips/Control/generate.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:22: Define or directive not defined: \'`Data_Control_Control_T\'\n ( `Data_Control_Control_T (input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:22: syntax error, unexpected \'(\', expecting \'[\'\n ( `Data_Control_Control_T (input) ctrl\n                            ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:23: Define or directive not defined: \'`Mips_Pipeline_HazReg_T\'\n , `Mips_Pipeline_HazReg_T (input) pipeHazReg\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:24: Define or directive not defined: \'`Mips_Pipeline_MemReg_T\'\n , `Mips_Pipeline_MemReg_T (input) pipeMemReg\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:25: Define or directive not defined: \'`Mips_Pipeline_PcReg_T\'\n , `Mips_Pipeline_PcReg_T  (input) pipePcReg\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:26: Define or directive not defined: \'`Mips_Pipeline_RegHaz_T\'\n , `Mips_Pipeline_RegHaz_T (output) pipeRegHaz\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:27: Define or directive not defined: \'`Mips_Pipeline_RegEx_T\'\n , `Mips_Pipeline_RegEx_T  (output) pipeRegEx\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:28: Define or directive not defined: \'`Mips_Pipeline_RegPc_T\'\n , `Mips_Pipeline_RegPc_T  (output) pipeRegPc\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:29: Define or directive not defined: \'`Mips_Pipeline_RegFwd_T\'\n , `Mips_Pipeline_RegFwd_T (output) pipeRegFwd\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:32: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pipePcReg_instruction ;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:33: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pipePcReg_pcAddr ;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:40: Define or directive not defined: \'`Mips_Type_Bool_T\'\n`Mips_Type_Bool_T (wire) pipeHazReg_stall;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:46: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pipeMemReg_instruction;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:47: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pipeMemReg_pcAddr;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:48: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pipeMemReg_memOut;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:49: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) pipeMemReg_aluResult;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:50: Define or directive not defined: \'`Mips_Type_RegPorts_T\'\n`Mips_Type_RegPorts_T (wire) pipeMemReg_regPorts;\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:60: Define or directive not defined: \'`Mips_Control_Control_T\'\n`Mips_Control_Control_T (wire) control;\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:66: Define or directive not defined: \'`Mips_Control_Control_T\'\n`Mips_Control_Control_T (wire) stall_control;\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:67: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) stall_instruction;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:76: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) regPort1 ;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:77: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) regPort2 ;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:78: Define or directive not defined: \'`Mips_Type_RegPorts_T\'\n`Mips_Type_RegPorts_T (wire) regPorts ;\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:80: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) regWriteData ;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/reg.v:80: syntax error, unexpected \'(\'\n`Mips_Type_Word_T (wire) regWriteData ;\n                   ^~~~\n%Error: Exiting due to 39 error(s)\n'
module Mips_Stage_reg #
	( parameter DELAYED = 1
	, parameter PASSTHROUGH = DELAYED
	)
	( `Data_Control_Control_T (input) ctrl
	, `Mips_Pipeline_HazReg_T (input) pipeHazReg
	, `Mips_Pipeline_MemReg_T (input) pipeMemReg
	, `Mips_Pipeline_PcReg_T  (input) pipePcReg
	, `Mips_Pipeline_RegHaz_T (output) pipeRegHaz
	, `Mips_Pipeline_RegEx_T  (output) pipeRegEx
	, `Mips_Pipeline_RegPc_T  (output) pipeRegPc
	, `Mips_Pipeline_RegFwd_T (output) pipeRegFwd
	);

`Mips_Type_Word_T (wire) pipePcReg_instruction ;
`Mips_Type_Word_T (wire) pipePcReg_pcAddr ;
Mips_Pipeline_PcReg_unpack PCREG
	( .in (pipePcReg)
	, .instruction (pipePcReg_instruction)
	, .pcAddr      (pipePcReg_pcAddr)
	);

`Mips_Type_Bool_T (wire) pipeHazReg_stall;
Mips_Pipeline_HazReg_unpack HAZREG
	( .in (pipeHazReg)
	, .stall (pipeHazReg_stall)
	);

`Mips_Type_Word_T (wire) pipeMemReg_instruction;
`Mips_Type_Word_T (wire) pipeMemReg_pcAddr;
`Mips_Type_Word_T (wire) pipeMemReg_memOut;
`Mips_Type_Word_T (wire) pipeMemReg_aluResult;
`Mips_Type_RegPorts_T (wire) pipeMemReg_regPorts;
Mips_Pipeline_MemReg_unpack MEMREG
	( .in (pipeMemReg)
	, .instruction (pipeMemReg_instruction)
	, .pcAddr      (pipeMemReg_pcAddr)
	, .memOut      (pipeMemReg_memOut)
	, .aluResult   (pipeMemReg_aluResult)
	, .regPorts    (pipeMemReg_regPorts)
	);

`Mips_Control_Control_T (wire) control;
Mips_Control_generate CTRL
	( .instruction (pipePcReg_instruction)
	, .control     (control)
	);

`Mips_Control_Control_T (wire) stall_control;
`Mips_Type_Word_T (wire) stall_instruction;
Mips_Datapath_Register_stall STALL
	( .stall (pipeHazReg_stall)
	, .inControl (control)
	, .outControl (stall_control)
	, .inInstruction (pipePcReg_instruction)
	, .outInstruction (stall_instruction)
	);

`Mips_Type_Word_T (wire) regPort1 ;
`Mips_Type_Word_T (wire) regPort2 ;
`Mips_Type_RegPorts_T (wire) regPorts ;
wire regPortEq ;
`Mips_Type_Word_T (wire) regWriteData ;
Mips_Datapath_Register_datapath #
	( .PASSTHROUGH (PASSTHROUGH)
	) REG
	( .ctrl (ctrl)
	, .control     (stall_control)
	, .instruction (stall_instruction)
	, .pcAddr      (pipeMemReg_pcAddr)
	, .memOut      (pipeMemReg_memOut)
	, .aluResult   (pipeMemReg_aluResult)
	, .portsIn     (pipeMemReg_regPorts)
	, .port1       (regPort1)
	, .port2       (regPort2)
	, .portEq      (regPortEq)
	, .portsOut    (regPorts)
	, .writeData   (regWriteData)
	);

Mips_Pipeline_RegEx_generate #
	( .DELAYED (DELAYED)
	) REGEX
	( .ctrl (ctrl)
	, .instruction (stall_instruction)
	, .pcAddr      (pipePcReg_pcAddr)
	, .regPort1    (regPort1)
	, .regPort2    (regPort2)
	, .regPorts    (regPorts)
	, .control     (stall_control)
	, .out         (pipeRegEx)
	);

Mips_Pipeline_RegPc_generate #
	( .DELAYED (DELAYED)
	) REGPC
	( .ctrl (ctrl)
	, .regPort1  (regPort1)
	, .regPortEq (regPortEq)
	, .control   (stall_control)
	, .out       (pipeRegPc)
	);

Mips_Pipeline_RegFwd_pack REGFWD
	( .out (pipeRegFwd)
	, .writeData (regWriteData)
	, .regPorts  (pipeMemReg_regPorts)
	);

Mips_Pipeline_RegHaz_pack REGHAZ
	( .out (pipeRegHaz)
	, .control (control)
	, .instruction (pipePcReg_instruction)
	);

endmodule
module Mips_Stage_reg #
	( parameter DELAYED = 1
	, parameter PASSTHROUGH = DELAYED
	)
	( `Data_Control_Control_T (input) ctrl
	, `Mips_Pipeline_HazReg_T (input) pipeHazReg
	, `Mips_Pipeline_MemReg_T (input) pipeMemReg
	, `Mips_Pipeline_PcReg_T  (input) pipePcReg
	, `Mips_Pipeline_RegHaz_T (output) pipeRegHaz
	, `Mips_Pipeline_RegEx_T  (output) pipeRegEx
	, `Mips_Pipeline_RegPc_T  (output) pipeRegPc
	, `Mips_Pipeline_RegFwd_T (output) pipeRegFwd
	);


`Mips_Type_Word_T (wire) pipePcReg_instruction ;
`Mips_Type_Word_T (wire) pipePcReg_pcAddr ;
Mips_Pipeline_PcReg_unpack PCREG
	( .in (pipePcReg)
	, .instruction (pipePcReg_instruction)
	, .pcAddr      (pipePcReg_pcAddr)
	);

`Mips_Type_Bool_T (wire) pipeHazReg_stall;
Mips_Pipeline_HazReg_unpack HAZREG
	( .in (pipeHazReg)
	, .stall (pipeHazReg_stall)
	);

`Mips_Type_Word_T (wire) pipeMemReg_instruction;
`Mips_Type_Word_T (wire) pipeMemReg_pcAddr;
`Mips_Type_Word_T (wire) pipeMemReg_memOut;
`Mips_Type_Word_T (wire) pipeMemReg_aluResult;
`Mips_Type_RegPorts_T (wire) pipeMemReg_regPorts;
Mips_Pipeline_MemReg_unpack MEMREG
	( .in (pipeMemReg)
	, .instruction (pipeMemReg_instruction)
	, .pcAddr      (pipeMemReg_pcAddr)
	, .memOut      (pipeMemReg_memOut)
	, .aluResult   (pipeMemReg_aluResult)
	, .regPorts    (pipeMemReg_regPorts)
	);

`Mips_Control_Control_T (wire) control;
Mips_Control_generate CTRL
	( .instruction (pipePcReg_instruction)
	, .control     (control)
	);

`Mips_Control_Control_T (wire) stall_control;
`Mips_Type_Word_T (wire) stall_instruction;
Mips_Datapath_Register_stall STALL
	( .stall (pipeHazReg_stall)
	, .inControl (control)
	, .outControl (stall_control)
	, .inInstruction (pipePcReg_instruction)
	, .outInstruction (stall_instruction)
	);

`Mips_Type_Word_T (wire) regPort1 ;
`Mips_Type_Word_T (wire) regPort2 ;
`Mips_Type_RegPorts_T (wire) regPorts ;
wire regPortEq ;
`Mips_Type_Word_T (wire) regWriteData ;
Mips_Datapath_Register_datapath #
	( .PASSTHROUGH (PASSTHROUGH)
	) REG
	( .ctrl (ctrl)
	, .control     (stall_control)
	, .instruction (stall_instruction)
	, .pcAddr      (pipeMemReg_pcAddr)
	, .memOut      (pipeMemReg_memOut)
	, .aluResult   (pipeMemReg_aluResult)
	, .portsIn     (pipeMemReg_regPorts)
	, .port1       (regPort1)
	, .port2       (regPort2)
	, .portEq      (regPortEq)
	, .portsOut    (regPorts)
	, .writeData   (regWriteData)
	);

Mips_Pipeline_RegEx_generate #
	( .DELAYED (DELAYED)
	) REGEX
	( .ctrl (ctrl)
	, .instruction (stall_instruction)
	, .pcAddr      (pipePcReg_pcAddr)
	, .regPort1    (regPort1)
	, .regPort2    (regPort2)
	, .regPorts    (regPorts)
	, .control     (stall_control)
	, .out         (pipeRegEx)
	);

Mips_Pipeline_RegPc_generate #
	( .DELAYED (DELAYED)
	) REGPC
	( .ctrl (ctrl)
	, .regPort1  (regPort1)
	, .regPortEq (regPortEq)
	, .control   (stall_control)
	, .out       (pipeRegPc)
	);

Mips_Pipeline_RegFwd_pack REGFWD
	( .out (pipeRegFwd)
	, .writeData (regWriteData)
	, .regPorts  (pipeMemReg_regPorts)
	);

Mips_Pipeline_RegHaz_pack REGHAZ
	( .out (pipeRegHaz)
	, .control (control)
	, .instruction (pipePcReg_instruction)
	);

endmodule