data/full_repos/permissive/165846232/components/AdjClockDivider/AdjClockDivider.v
data/verilator_xmls/daa654dc-9ef0-4541-a1e6-6e7e603d6854.xml
module AdjClockDivider
#(
	parameter INPUT_BIT_WIDTH = 8
)
(
    input Clk,
    input ClkEnable,
    input [(INPUT_BIT_WIDTH-1):0] FrequencyDividerFactor,
    output reg ClkOutput,
	output reg ClkEnableOutput
);

    reg [(INPUT_BIT_WIDTH-1):0] InternalCounter;

    initial InternalCounter = 0;

    always @(posedge Clk)
    begin
	    ClkEnableOutput <= 0;
	    if(ClkEnable)
			 begin
				 InternalCounter <= InternalCounter + 1;
				 if(InternalCounter >= FrequencyDividerFactor - 1)
				 begin
					 InternalCounter <= 0;
					 ClkOutput <= !ClkOutput;
					 ClkEnableOutput <= 1;
				 end
			 end
    end
    
endmodule
module AdjClockDivider
#(
	parameter INPUT_BIT_WIDTH = 8
)
(
    input Clk,
    input ClkEnable,
    input [(INPUT_BIT_WIDTH-1):0] FrequencyDividerFactor,
    output reg ClkOutput,
	output reg ClkEnableOutput
);


    reg [(INPUT_BIT_WIDTH-1):0] InternalCounter;

    initial InternalCounter = 0;

    always @(posedge Clk)
    begin
	    ClkEnableOutput <= 0;
	    if(ClkEnable)
			 begin
				 InternalCounter <= InternalCounter + 1;
				 if(InternalCounter >= FrequencyDividerFactor - 1)
				 begin
					 InternalCounter <= 0;
					 ClkOutput <= !ClkOutput;
					 ClkEnableOutput <= 1;
				 end
			 end
    end
    
endmodule