data/full_repos/permissive/14193640/fpga/led_controller_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/led_controller_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/led_controller_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/led_controller_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/led_controller_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #200;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/led_controller_testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #40;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/14193640/fpga/led_controller_testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #660;\n      ^\n%Error: data/full_repos/permissive/14193640/fpga/led_controller_testbench.v:19: Cannot find file containing module: \'led_controller\'\n   led_controller uut\n   ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/14193640/fpga,data/full_repos/permissive/14193640/led_controller\n             data/full_repos/permissive/14193640/fpga,data/full_repos/permissive/14193640/led_controller.v\n             data/full_repos/permissive/14193640/fpga,data/full_repos/permissive/14193640/led_controller.sv\n             led_controller\n             led_controller.v\n             led_controller.sv\n             obj_dir/led_controller\n             obj_dir/led_controller.v\n             obj_dir/led_controller.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module led_controller_testbench;

   reg         clk;
   reg         reset_n;
   reg         test_panel_select_n;
   reg [31:0]  chunk_data;
   reg [3:0]   chunk_addr;
   reg         chunk_write_enable;
   reg [3:0]   row_addr;
   reg [1:0]   panel_addr;
   wire        serial_clk;
   wire        latch_enable;
   wire        output_enable_n;
   wire [11:0] serial_data_out;
   wire [15:0] row_select_n;

   led_controller uut
     (.clk(clk), .reset_n(reset_n), .test_panel_select_n(test_panel_select_n),
      .chunk_data(chunk_data), .chunk_addr(chunk_addr),
      .chunk_write_enable(chunk_write_enable), .row_addr(row_addr),
      .panel_addr(panel_addr), .serial_clk(serial_clk), 
      .latch_enable(latch_enable), .output_enable_n(output_enable_n),
      .serial_data_out(serial_data_out), .row_select_n(row_select_n)
      );

   always begin
      clk = 1'b1;
      #10;
      clk = 1'b0;
      #10;
   end

   initial begin
      reset_n = 1'b0;
      test_panel_select_n = 1'b0;
      chunk_data = 32'hffffffff;
      chunk_addr = 4'h0;
      chunk_write_enable = 1'b0;
      row_addr = 4'h0;
      panel_addr = 2'h3;
      #100;
      
      reset_n = 1'b1;
      #200;

      chunk_write_enable = 1'b1;
      #40;

      chunk_write_enable = 1'b0;
      #660;
      
      $stop;
   end

endmodule
module led_controller_testbench;


   reg         clk;
   reg         reset_n;
   reg         test_panel_select_n;
   reg [31:0]  chunk_data;
   reg [3:0]   chunk_addr;
   reg         chunk_write_enable;
   reg [3:0]   row_addr;
   reg [1:0]   panel_addr;
   wire        serial_clk;
   wire        latch_enable;
   wire        output_enable_n;
   wire [11:0] serial_data_out;
   wire [15:0] row_select_n;

   led_controller uut
     (.clk(clk), .reset_n(reset_n), .test_panel_select_n(test_panel_select_n),
      .chunk_data(chunk_data), .chunk_addr(chunk_addr),
      .chunk_write_enable(chunk_write_enable), .row_addr(row_addr),
      .panel_addr(panel_addr), .serial_clk(serial_clk), 
      .latch_enable(latch_enable), .output_enable_n(output_enable_n),
      .serial_data_out(serial_data_out), .row_select_n(row_select_n)
      );

   always begin
      clk = 1'b1;
      #10;
      clk = 1'b0;
      #10;
   end

   initial begin
      reset_n = 1'b0;
      test_panel_select_n = 1'b0;
      chunk_data = 32'hffffffff;
      chunk_addr = 4'h0;
      chunk_write_enable = 1'b0;
      row_addr = 4'h0;
      panel_addr = 2'h3;
      #100;
      
      reset_n = 1'b1;
      #200;

      chunk_write_enable = 1'b1;
      #40;

      chunk_write_enable = 1'b0;
      #660;
      
      $stop;
   end

endmodule