data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/lfsr/lfsr.v
1: b'%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/lfsr/lfsr.v:16: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'INIT_DATA\' generates 32 bits.\n                                                                                                                    : ... In instance lfsr\n            lfsr_data_out <= INIT_DATA;\n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module lfsr
#(
    parameter integer DATA_WIDTH = 4,
    parameter integer INIT_DATA  = 0,
    parameter         POLYNOMIAL = 4'h9
)(
    input  wire                 clk,
    input  wire                 reset,
    output reg [DATA_WIDTH-1:0] lfsr_data_out
);

    wire feedback = ^(lfsr_data_out & POLYNOMIAL);

    always @(posedge clk)
        if (reset)
            lfsr_data_out <= INIT_DATA;
        else
            lfsr_data_out <= {lfsr_data_out[DATA_WIDTH-2:0], feedback};
endmodule
module lfsr
#(
    parameter integer DATA_WIDTH = 4,
    parameter integer INIT_DATA  = 0,
    parameter         POLYNOMIAL = 4'h9
)(
    input  wire                 clk,
    input  wire                 reset,
    output reg [DATA_WIDTH-1:0] lfsr_data_out
);


    wire feedback = ^(lfsr_data_out & POLYNOMIAL);

    always @(posedge clk)
        if (reset)
            lfsr_data_out <= INIT_DATA;
        else
            lfsr_data_out <= {lfsr_data_out[DATA_WIDTH-2:0], feedback};
endmodule