data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v
None: at end of input
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:10: Define or directive not defined: \'`AluOpWidth\'\n  input wire[`AluOpWidth-1:0]  id_aluop,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:11: Define or directive not defined: \'`AluSelWidth\'\n  input wire[`AluSelWidth-1:0] id_alusel,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:12: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] id_reg1,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:13: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] id_reg2,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:14: Define or directive not defined: \'`RegAddrWidth\'\n  input wire[`RegAddrWidth-1:0] id_wd,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:16: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] id_addr_base,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:17: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] id_addr_off,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:21: Define or directive not defined: \'`AluOpWidth\'\n  output reg[`AluOpWidth-1:0]  ex_aluop,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:22: Define or directive not defined: \'`AluSelWidth\'\n  output reg[`AluSelWidth-1:0] ex_alusel,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:23: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] ex_reg1,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:24: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] ex_reg2,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:25: Define or directive not defined: \'`RegAddrWidth\'\n  output reg[`RegAddrWidth-1:0] ex_wd,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:27: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] ex_addr_base,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:28: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] ex_addr_off,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:36: Define or directive not defined: \'`RstEnable\'\n  if(rst == `RstEnable) begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:36: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if(rst == `RstEnable) begin\n                      ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:37: Define or directive not defined: \'`EXE_NOP_OP\'\n   ex_aluop <= `EXE_NOP_OP;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:38: Define or directive not defined: \'`EXE_NOP_RES\'\n   ex_alusel <= `EXE_NOP_RES;\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:38: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_alusel <= `EXE_NOP_RES;\n                            ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:39: Define or directive not defined: \'`ZeroWord\'\n   ex_reg1  <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:39: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_reg1  <= `ZeroWord;\n                        ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:40: Define or directive not defined: \'`ZeroWord\'\n   ex_reg2  <= `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_reg2  <= `ZeroWord;\n                        ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:41: Define or directive not defined: \'`ZeroRegAddr\'\n   ex_wd  <= `ZeroRegAddr;\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:41: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_wd  <= `ZeroRegAddr;\n                         ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:42: Define or directive not defined: \'`WriteDisable\'\n   ex_wreg  <= `WriteDisable;\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_wreg  <= `WriteDisable;\n                            ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:43: Define or directive not defined: \'`ZeroWord\'\n   ex_addr_base <= `ZeroWord;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_addr_base <= `ZeroWord;\n                            ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:44: Define or directive not defined: \'`ZeroWord\'\n   ex_addr_off <= `ZeroWord;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:44: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   ex_addr_off <= `ZeroWord;\n                           ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:45: Define or directive not defined: \'`NoJump\'\n   jump_type_o <= `NoJump;\n                  ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   jump_type_o <= `NoJump;\n                         ^\n%Error: Cannot continue\n'
module id_ex(
		input wire clk,
		input wire rst,
		input wire[5:0] stall,
		

		input wire[`AluOpWidth-1:0]		id_aluop,
		input wire[`AluSelWidth-1:0]	id_alusel,
		input wire[`RegDataWidth-1:0]	id_reg1,
		input wire[`RegDataWidth-1:0]	id_reg2,
		input wire[`RegAddrWidth-1:0]	id_wd,
		input wire id_wreg,
		input wire[`RegDataWidth-1:0]	id_addr_base,
		input wire[`RegDataWidth-1:0]	id_addr_off,
		input wire[1:0] id_jump_type,
		

		output reg[`AluOpWidth-1:0]		ex_aluop,
		output reg[`AluSelWidth-1:0]	ex_alusel,
		output reg[`RegDataWidth-1:0]	ex_reg1,
		output reg[`RegDataWidth-1:0]	ex_reg2,
		output reg[`RegAddrWidth-1:0]	ex_wd,
		output reg ex_wreg,
		output reg[`RegDataWidth-1:0]	ex_addr_base,
		output reg[`RegDataWidth-1:0]	ex_addr_off,


		output reg[1:0] jump_type_o
		
	);
	always @ (posedge clk)
	begin
		if(rst == `RstEnable) begin
			ex_aluop	<=	`EXE_NOP_OP;
			ex_alusel	<=	`EXE_NOP_RES;
			ex_reg1		<=	`ZeroWord;
			ex_reg2		<=	`ZeroWord;
			ex_wd		<=	`ZeroRegAddr;
			ex_wreg		<=	`WriteDisable;
			ex_addr_base <= `ZeroWord;
			ex_addr_off	<=	`ZeroWord;
			jump_type_o	<=	`NoJump;
		end else if(!stall[2]) begin
			ex_aluop	<=	id_aluop;
			ex_alusel	<=	id_alusel;
			ex_reg1		<=	id_reg1;
			ex_reg2		<=	id_reg2;
			ex_wd		<=	id_wd;
			ex_wreg		<=	id_wreg;
			ex_addr_base <= id_addr_base;
			ex_addr_off	<=	id_addr_off;
			jump_type_o	<=	id_jump_type;
		end 
	end
	
endmodule
module id_ex(
		input wire clk,
		input wire rst,
		input wire[5:0] stall,
		

		input wire[`AluOpWidth-1:0]		id_aluop,
		input wire[`AluSelWidth-1:0]	id_alusel,
		input wire[`RegDataWidth-1:0]	id_reg1,
		input wire[`RegDataWidth-1:0]	id_reg2,
		input wire[`RegAddrWidth-1:0]	id_wd,
		input wire id_wreg,
		input wire[`RegDataWidth-1:0]	id_addr_base,
		input wire[`RegDataWidth-1:0]	id_addr_off,
		input wire[1:0] id_jump_type,
		

		output reg[`AluOpWidth-1:0]		ex_aluop,
		output reg[`AluSelWidth-1:0]	ex_alusel,
		output reg[`RegDataWidth-1:0]	ex_reg1,
		output reg[`RegDataWidth-1:0]	ex_reg2,
		output reg[`RegAddrWidth-1:0]	ex_wd,
		output reg ex_wreg,
		output reg[`RegDataWidth-1:0]	ex_addr_base,
		output reg[`RegDataWidth-1:0]	ex_addr_off,


		output reg[1:0] jump_type_o
		
	);

	always @ (posedge clk)
	begin
		if(rst == `RstEnable) begin
			ex_aluop	<=	`EXE_NOP_OP;
			ex_alusel	<=	`EXE_NOP_RES;
			ex_reg1		<=	`ZeroWord;
			ex_reg2		<=	`ZeroWord;
			ex_wd		<=	`ZeroRegAddr;
			ex_wreg		<=	`WriteDisable;
			ex_addr_base <= `ZeroWord;
			ex_addr_off	<=	`ZeroWord;
			jump_type_o	<=	`NoJump;
		end else if(!stall[2]) begin
			ex_aluop	<=	id_aluop;
			ex_alusel	<=	id_alusel;
			ex_reg1		<=	id_reg1;
			ex_reg2		<=	id_reg2;
			ex_wd		<=	id_wd;
			ex_wreg		<=	id_wreg;
			ex_addr_base <= id_addr_base;
			ex_addr_off	<=	id_addr_off;
			jump_type_o	<=	id_jump_type;
		end 
	end
	
endmodule