data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v
 line:55: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_rst = 1\'b1;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_opcode = 5\'b00000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_opcode = 5\'b00001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_opcode = 5\'b00010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_opcode = 5\'b00011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_opcode = 5\'b00100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_opcode = 5\'b00101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_opcode = 5\'b00110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_opcode = 5\'b00111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #10 i_opcode = 5\'b00000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Error: data/full_repos/permissive/206437232/TP3-BIP1-2019/Test/tb_instruction_decoder.v:58: Cannot find file containing module: \'instruction_decoder\'\n    instruction_decoder #(\n    ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/instruction_decoder\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/instruction_decoder.v\n             data/full_repos/permissive/206437232/TP3-BIP1-2019/Test,data/full_repos/permissive/206437232/instruction_decoder.sv\n             instruction_decoder\n             instruction_decoder.v\n             instruction_decoder.sv\n             obj_dir/instruction_decoder\n             obj_dir/instruction_decoder.v\n             obj_dir/instruction_decoder.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_instruction_decoder();

    parameter NB_OPCODE = 5;


    reg                     i_rst;
    reg [NB_OPCODE - 1 : 0] i_opcode;

    wire         o_WrPC;
    wire [1 : 0] o_SelA;
    wire         o_SelB;
    wire         o_WrAcc;
    wire         o_op;
    wire         o_WrRam;
    wire         o_RdRam;

    initial begin
        i_rst = 1'b0;
        i_opcode = {NB_OPCODE{1'b0}};

        #10 i_rst = 1'b1;

        #10 i_opcode = 5'b00000;
        #10 i_opcode = 5'b00001;
        #10 i_opcode = 5'b00010;
        #10 i_opcode = 5'b00011;
        #10 i_opcode = 5'b00100;
        #10 i_opcode = 5'b00101;
        #10 i_opcode = 5'b00110;
        #10 i_opcode = 5'b00111;
        #10 i_opcode = 5'b00000;
        
        #10 $finish;
    end

    instruction_decoder #(
        .NB_OPCODE  (NB_OPCODE)
    )
    tb_instruction_decoder (

        .i_rst      (i_rst),
        .i_opcode   (i_opcode),

        .o_WrPC     (o_WrPC),
        .o_SelA     (o_SelA),
        .o_SelB     (o_SelB),
        .o_WrAcc    (o_WrAcc),
        .o_op       (o_op),
        .o_WrRam    (o_WrRam),
        .o_RdRam    (o_RdRam)
    );

endmodule
module tb_instruction_decoder();


    parameter NB_OPCODE = 5;


    reg                     i_rst;
    reg [NB_OPCODE - 1 : 0] i_opcode;

    wire         o_WrPC;
    wire [1 : 0] o_SelA;
    wire         o_SelB;
    wire         o_WrAcc;
    wire         o_op;
    wire         o_WrRam;
    wire         o_RdRam;

    initial begin
        i_rst = 1'b0;
        i_opcode = {NB_OPCODE{1'b0}};

        #10 i_rst = 1'b1;

        #10 i_opcode = 5'b00000;
        #10 i_opcode = 5'b00001;
        #10 i_opcode = 5'b00010;
        #10 i_opcode = 5'b00011;
        #10 i_opcode = 5'b00100;
        #10 i_opcode = 5'b00101;
        #10 i_opcode = 5'b00110;
        #10 i_opcode = 5'b00111;
        #10 i_opcode = 5'b00000;
        
        #10 $finish;
    end

    instruction_decoder #(
        .NB_OPCODE  (NB_OPCODE)
    )
    tb_instruction_decoder (

        .i_rst      (i_rst),
        .i_opcode   (i_opcode),

        .o_WrPC     (o_WrPC),
        .o_SelA     (o_SelA),
        .o_SelB     (o_SelB),
        .o_WrAcc    (o_WrAcc),
        .o_op       (o_op),
        .o_WrRam    (o_WrRam),
        .o_RdRam    (o_RdRam)
    );

endmodule