data/full_repos/permissive/150152921/apps/aes/step3/rtl/aes_256_wrapper.v
1: b"%Error: data/full_repos/permissive/150152921/apps/aes/step3/rtl/aes_256_wrapper.v:34: Cannot find file containing module: 'regchain'\n regchain #(0, 128) state_hp(CLK, STATE, state);\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150152921/apps/aes/step3/rtl,data/full_repos/permissive/150152921/regchain\n             data/full_repos/permissive/150152921/apps/aes/step3/rtl,data/full_repos/permissive/150152921/regchain.v\n             data/full_repos/permissive/150152921/apps/aes/step3/rtl,data/full_repos/permissive/150152921/regchain.sv\n             regchain\n             regchain.v\n             regchain.sv\n             obj_dir/regchain\n             obj_dir/regchain.v\n             obj_dir/regchain.sv\n%Error: data/full_repos/permissive/150152921/apps/aes/step3/rtl/aes_256_wrapper.v:36: Cannot find file containing module: 'regchain'\n regchain #(0, 256) key_hp(CLK, KEY, key);\n ^~~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/aes/step3/rtl/aes_256_wrapper.v:39: Cannot find file containing module: 'aes_256'\n aes_256 core\n ^~~~~~~\n%Error: data/full_repos/permissive/150152921/apps/aes/step3/rtl/aes_256_wrapper.v:50: Cannot find file containing module: 'regchain'\n regchain #(2, 128) out_hp(CLK, out, OUT);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module top
(
	input		CLK,
	input	[127:0]	STATE,
	input	[255:0]	KEY,
	output	[127:0]	OUT
);

	wire	[127:0]	state;
	wire	[255:0]	key;
	wire	[127:0]	out;

`ifdef TTDSE
	regchain #(`NUM_FRONT, 128) state_hp(CLK, STATE, state);
	regchain #(`NUM_FRONT, 256) key_hp(CLK, KEY, key);
`else
	regchain #(0, 128) state_hp(CLK, STATE, state);

	regchain #(0, 256) key_hp(CLK, KEY, key);
`endif

	aes_256 core
	(
		.clk(CLK),
		.state(state),
		.key(key),
		.out(out)
	);

`ifdef TTDSE
	regchain #(`NUM_BACK, 128) out_hp(CLK, out, OUT);
`else
	regchain #(2, 128) out_hp(CLK, out, OUT);
`endif

endmodule
module top
(
	input		CLK,
	input	[127:0]	STATE,
	input	[255:0]	KEY,
	output	[127:0]	OUT
);


	wire	[127:0]	state;
	wire	[255:0]	key;
	wire	[127:0]	out;

`ifdef TTDSE
	regchain #(`NUM_FRONT, 128) state_hp(CLK, STATE, state);
	regchain #(`NUM_FRONT, 256) key_hp(CLK, KEY, key);
`else
	regchain #(0, 128) state_hp(CLK, STATE, state);

	regchain #(0, 256) key_hp(CLK, KEY, key);
`endif

	aes_256 core
	(
		.clk(CLK),
		.state(state),
		.key(key),
		.out(out)
	);

`ifdef TTDSE
	regchain #(`NUM_BACK, 128) out_hp(CLK, out, OUT);
`else
	regchain #(2, 128) out_hp(CLK, out, OUT);
`endif

endmodule