data/full_repos/permissive/148324174/CombLogic/fdiv_tb.v
 line:21: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/fdiv_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #20 rst = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/fdiv_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #500 $finish; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/148324174/CombLogic/fdiv_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\nalways #5 fin = ~fin;\n       ^\n%Error: data/full_repos/permissive/148324174/CombLogic/fdiv_tb.v:8: Cannot find file containing module: \'fdiv\'\nfdiv #(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/148324174/CombLogic,data/full_repos/permissive/148324174/fdiv\n             data/full_repos/permissive/148324174/CombLogic,data/full_repos/permissive/148324174/fdiv.v\n             data/full_repos/permissive/148324174/CombLogic,data/full_repos/permissive/148324174/fdiv.sv\n             fdiv\n             fdiv.v\n             fdiv.sv\n             obj_dir/fdiv\n             obj_dir/fdiv.v\n             obj_dir/fdiv.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fdiv_tb;

reg fin, rst;
wire fout;

fdiv #(
	.Ndiv(4)
	)
U1 (
	.fin(fin),
	.rst(rst),
	.fout(fout)
	);

initial begin
	rst = 1'b1;
	fin = 1'b0;
	#20 rst = 1'b0;
	#500 $finish; 
end

always #5 fin = ~fin;

endmodule
module fdiv_tb;


reg fin, rst;
wire fout;

fdiv #(
	.Ndiv(4)
	)
U1 (
	.fin(fin),
	.rst(rst),
	.fout(fout)
	);

initial begin
	rst = 1'b1;
	fin = 1'b0;
	#20 rst = 1'b0;
	#500 $finish; 
end

always #5 fin = ~fin;

endmodule