data/full_repos/permissive/162928820/clockdiv.v
data/verilator_xmls/3c18c276-eb8f-4b6c-b21e-eef1e518b599.xml
module clockdiv(
	input wire clk,
	output wire segclk,
	output wire sltclk
	);

	reg [23:0] q = 0;


	always @(posedge clk) begin
		q <= q + 1;
	end


	assign segclk = q[14];
	

	assign sltclk = q[23];

endmodule
module clockdiv(
	input wire clk,
	output wire segclk,
	output wire sltclk
	);


	reg [23:0] q = 0;


	always @(posedge clk) begin
		q <= q + 1;
	end


	assign segclk = q[14];
	

	assign sltclk = q[23];

endmodule