data/full_repos/permissive/154590168/rtl_cpu/CPU.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:38: Little bit endian vector: MSB < LSB of bit range: 0:82\nwire[0:82]  op_decode;\n    ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:102: Cannot find file containing module: \'PcAndIr\'\nPcAndIr PAI (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/PcAndIr\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/PcAndIr.v\n             data/full_repos/permissive/154590168/rtl_cpu,data/full_repos/permissive/154590168/PcAndIr.sv\n             PcAndIr\n             PcAndIr.v\n             PcAndIr.sv\n             obj_dir/PcAndIr\n             obj_dir/PcAndIr.v\n             obj_dir/PcAndIr.sv\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:129: Cannot find file containing module: \'OpDecode\'\nOpDecode DEC (\n^~~~~~~~\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:134: Cannot find file containing module: \'TimDecode\'\nTimDecode TIM (\n^~~~~~~~~\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:151: Cannot find file containing module: \'AluInput\'\nAluInput AIN (\n^~~~~~~~\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:170: Cannot find file containing module: \'ALU\'\nALU ALU (\n^~~\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:192: Cannot find file containing module: \'Multiply\'\nMultiply MUL (\n^~~~~~~~\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:202: Cannot find file containing module: \'PtrCalc\'\nPtrCalc PTR (\n^~~~~~~\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:211: Cannot find file containing module: \'BitSetClr\'\nBitSetClr BSC (\n^~~~~~~~~\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:224: Cannot find file containing module: \'PmCont\'\nPmCont PMC (\n^~~~~~\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:245: Cannot find file containing module: \'DmCont\'\nDmCont DMC (\n^~~~~~\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:282: Cannot find file containing module: \'RfRead\'\nRfRead RFR (\n^~~~~~\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:290: Cannot find file containing module: \'RfWrite\'\nRfWrite RFW (\n^~~~~~~\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:308: Cannot find file containing module: \'RegFile\'\nRegFile RF (\n^~~~~~~\n%Error: data/full_repos/permissive/154590168/rtl_cpu/CPU.v:321: Cannot find file containing module: \'SregAndSp\'\nSregAndSp SAS (\n^~~~~~~~~\n%Error: Exiting due to 14 error(s), 1 warning(s)\n'
module  CPU (
    input           clock,
    input           reset,
    input   [15:0]  pm_rdata,
    output  [15:0]  pm_addr,
    output          pm_re,
    output          pm_we,
    output  [15:0]  pm_wdata,
    input   [7:0]   dm_rdata,
    output  [15:0]  dm_addr,
    output          dm_re,
    output          dm_we,
    output  [7:0]   dm_wdata,
    input   [7:0]   io_rdata,
    output  [7:0]   io_addr,
    output          io_re,
    output          io_we,
    output  [7:0]   io_wdata,
    input           irq,
    input   [15:0]  irq_addr
);




wire[15:0]  pc;
wire[15:0]  pc_new;
wire        pc_new_en;
wire[15:0]  ir;
wire[15:0]  ir_2nd;
wire[1:0]   cycle;
wire        skip_en;
wire        irq_det;
wire        irq_ret;
wire[0:82]  op_decode;
wire        tim_cyc_end;
wire        tim_pc_en;
wire        tim_pm_re;
wire        tim_dm_re;
wire        tim_dm_we;
wire        tim_rf_we;
wire        tim_sr_en;
wire        tim_sp_en;
wire[15:0]  alu_ai;
wire[15:0]  alu_bi;
wire        alu_ci;
wire        sel_adc_b;
wire        sel_sbc_b;
wire        sel_adc_w;
wire        sel_sbc_w;
wire        sel_and;
wire        sel_or;
wire        sel_eor;
wire[15:0]  alu_ro;
wire        alu_cf;
wire        alu_zf;
wire        alu_nf;
wire        alu_vf;
wire        alu_sf;
wire        alu_hf;
wire[15:0]  mul_ro;
wire        mul_cf;
wire        mul_zf;
wire[15:0]  ptr_ai;
wire[15:0]  ptr_ro;
wire[7:0]   bsc_ro;
wire        bst_tf;
wire        mm_sp_l_we;
wire        mm_sp_h_we;
wire        mm_sreg_we;
wire[7:0]   mm_io_wdata;
wire[7:0]   mm_io_rdata;
wire[7:0]   mm_rdata;
wire        mm_rdata_en;
wire[7:0]   lpm_data;
wire        lpm_data_en;
wire[4:0]   rf_waddr;
wire[15:0]  rf_wdata;
wire        rf_we_byte;
wire        rf_we_word;
wire        rf_re_word;
wire[4:0]   rf_raddr_a;
wire[4:0]   rf_raddr_b;
wire[15:0]  rf_rdata_a;
wire[7:0]   rf_rdata_b;
wire[15:0]  sp;
wire[7:0]   sreg;
wire        sr_cf;
wire        sr_zf;
wire        sr_tf;
wire        sr_if;





wire        cpse_zf = (rf_rdata_a[7:0] == rf_rdata_b);

PcAndIr PAI (
    .clock      (clock      ),
    .reset      (reset      ),
    .pm_rdata   (pm_rdata   ),
    .dm_rdata   (dm_rdata   ),
    .io_rdata   (mm_io_rdata),
    .rf_rdata   (rf_rdata_b ),
    .sreg       (sreg       ),
    .alu_ro     (alu_ro     ),
    .alu_zf     (cpse_zf    ),
    .irq        (irq        ),
    .irq_addr   (irq_addr   ),
    .sr_if      (sr_if      ),
    .op_decode  (op_decode  ),
    .tim_cyc_end(tim_cyc_end),
    .tim_pc_en  (tim_pc_en  ),
    .pc         (pc         ),
    .pc_new     (pc_new     ),
    .pc_new_en  (pc_new_en  ),
    .ir         (ir         ),
    .ir_2nd     (ir_2nd     ),
    .cycle      (cycle      ),
    .skip_en    (skip_en    ),
    .irq_det    (irq_det    ),
    .irq_ret    (irq_ret    )
);

OpDecode DEC (
    .ir         (ir         ),
    .op_decode  (op_decode  )
);

TimDecode TIM (
    .ir         (ir         ),
    .cycle      (cycle      ),
    .skip_en    (skip_en    ),
    .tim_cyc_end(tim_cyc_end),
    .tim_pc_en  (tim_pc_en  ),
    .tim_pm_re  (tim_pm_re  ),
    .tim_dm_re  (tim_dm_re  ),
    .tim_dm_we  (tim_dm_we  ),
    .tim_rf_we  (tim_rf_we  ),
    .tim_sr_en  (tim_sr_en  ),
    .tim_sp_en  (tim_sp_en  )
);




AluInput AIN (
    .ir         (ir         ),
    .rf_rdata_a (rf_rdata_a ),
    .rf_rdata_b (rf_rdata_b ),
    .sr_cf      (sr_cf      ),
    .pc         (pc         ),
    .ir_2nd     (ir_2nd     ),
    .alu_ai     (alu_ai     ),
    .alu_bi     (alu_bi     ),
    .alu_ci     (alu_ci     ),
    .sel_adc_b  (sel_adc_b  ),
    .sel_sbc_b  (sel_sbc_b  ),
    .sel_adc_w  (sel_adc_w  ),
    .sel_sbc_w  (sel_sbc_w  ),
    .sel_and    (sel_and    ),
    .sel_or     (sel_or     ),
    .sel_eor    (sel_eor    )
);

ALU ALU (
    .ai         (alu_ai     ),
    .bi         (alu_bi     ),
    .ci         (alu_ci     ),
    .sel_adc_b  (sel_adc_b  ),
    .sel_sbc_b  (sel_sbc_b  ),
    .sel_adc_w  (sel_adc_w  ),
    .sel_sbc_w  (sel_sbc_w  ),
    .sel_and    (sel_and    ),
    .sel_or     (sel_or     ),
    .sel_eor    (sel_eor    ),
    .sr_zf      (sr_zf      ),
    .op_decode  (op_decode  ),
    .ro         (alu_ro     ),
    .cf         (alu_cf     ),
    .zf         (alu_zf     ),
    .nf         (alu_nf     ),
    .vf         (alu_vf     ),
    .sf         (alu_sf     ),
    .hf         (alu_hf     )
);

Multiply MUL (
    .clock      (clock      ),
    .ai         (alu_ai[7:0]),
    .bi         (alu_bi[7:0]),
    .op_decode  (op_decode  ),
    .ro         (mul_ro     ),
    .cf         (mul_cf     ),
    .zf         (mul_zf     )
);

PtrCalc PTR (
    .ir         (ir         ),
    .ir_2nd     (ir_2nd     ),
    .sp         (sp         ),
    .rf_rdata_a (rf_rdata_a ),
    .ptr_ai     (ptr_ai     ),
    .ptr_ro     (ptr_ro     )
);

BitSetClr BSC (
    .ir         (ir         ),
    .io_rdata   (mm_io_rdata),
    .rf_rdata   (rf_rdata_b ),
    .sreg       (sreg       ),
    .sr_tf      (sr_tf      ),
    .bsc_ro     (bsc_ro     ),
    .bst_tf     (bst_tf     )
);




PmCont PMC (
    .clock      (clock      ),
    .reset      (reset      ),
    .pm_rdata   (pm_rdata   ),
    .pc         (pc         ),
    .pc_new     (pc_new     ),
    .pc_new_en  (pc_new_en  ),
    .cycle      (cycle      ),
    .skip_en    (skip_en    ),
    .irq_det    (irq_det    ),
    .rf_rdata   (rf_rdata_a ),
    .op_decode  (op_decode  ),
    .tim_pm_re  (tim_pm_re  ),
    .pm_addr    (pm_addr    ),
    .pm_re      (pm_re      ),
    .pm_we      (pm_we      ),
    .pm_wdata   (pm_wdata   ),
    .lpm_data   (lpm_data   ),
    .lpm_data_en(lpm_data_en)
);

DmCont DMC (
    .clock      (clock      ),
    .reset      (reset      ),
    .dm_rdata   (dm_rdata   ),
    .io_rdata   (io_rdata   ),
    .rf_rdata   (rf_rdata_b ),
    .sreg       (sreg       ),
    .sp         (sp         ),
    .pc         (pc         ),
    .ir         (ir         ),
    .cycle      (cycle      ),
    .ptr_ai     (ptr_ai     ),
    .ptr_ro     (ptr_ro     ),
    .bsc_ro     (bsc_ro     ),
    .op_decode  (op_decode  ),
    .tim_dm_re  (tim_dm_re  ),
    .tim_dm_we  (tim_dm_we  ),
    .dm_addr    (dm_addr    ),
    .dm_re      (dm_re      ),
    .dm_we      (dm_we      ),
    .dm_wdata   (dm_wdata   ),
    .io_addr    (io_addr    ),
    .io_re      (io_re      ),
    .io_we      (io_we      ),
    .io_wdata   (io_wdata   ),
    .mm_sp_l_we (mm_sp_l_we ),
    .mm_sp_h_we (mm_sp_h_we ),
    .mm_sreg_we (mm_sreg_we ),
    .mm_io_wdata(mm_io_wdata),
    .mm_io_rdata(mm_io_rdata),
    .mm_rdata   (mm_rdata   ),
    .mm_rdata_en(mm_rdata_en)
);




RfRead RFR (
    .ir         (ir         ),
    .cycle      (cycle      ),
    .re_word    (rf_re_word ),
    .raddr_a    (rf_raddr_a ),
    .raddr_b    (rf_raddr_b )
);

RfWrite RFW (
    .ir         (ir         ),
    .cycle      (cycle      ),
    .alu_ro     (alu_ro     ),
    .mul_ro     (mul_ro     ),
    .ptr_ro     (ptr_ro     ),
    .bsc_ro     (bsc_ro     ),
    .mm_rdata   (mm_rdata   ),
    .mm_rdata_en(mm_rdata_en),
    .lpm_data   (lpm_data   ),
    .lpm_data_en(lpm_data_en),
    .tim_rf_we  (tim_rf_we  ),
    .waddr      (rf_waddr   ),
    .wdata      (rf_wdata   ),
    .we_byte    (rf_we_byte ),
    .we_word    (rf_we_word )
);

RegFile RF (
    .clock      (clock      ),
    .waddr      (rf_waddr   ),
    .wdata      (rf_wdata   ),
    .we_byte    (rf_we_byte ),
    .we_word    (rf_we_word ),
    .re_word    (rf_re_word ),
    .raddr_a    (rf_raddr_a ),
    .raddr_b    (rf_raddr_b ),
    .rdata_a    (rf_rdata_a ),
    .rdata_b    (rf_rdata_b )
);

SregAndSp SAS (
    .clock      (clock      ),
    .reset      (reset      ),
    .ir         (ir         ),
    .alu_cf     (alu_cf     ),
    .alu_zf     (alu_zf     ),
    .alu_nf     (alu_nf     ),
    .alu_vf     (alu_vf     ),
    .alu_sf     (alu_sf     ),
    .alu_hf     (alu_hf     ),
    .mul_cf     (mul_cf     ),
    .mul_zf     (mul_zf     ),
    .ptr_ro     (ptr_ro     ),
    .bsc_ro     (bsc_ro     ),
    .bst_tf     (bst_tf     ),
    .mm_sp_l_we (mm_sp_l_we ),
    .mm_sp_h_we (mm_sp_h_we ),
    .mm_sreg_we (mm_sreg_we ),
    .mm_io_wdata(mm_io_wdata),
    .irq_det    (irq_det    ),
    .irq_ret    (irq_ret    ),
    .tim_sr_en  (tim_sr_en  ),
    .tim_sp_en  (tim_sp_en  ),
    .sp         (sp         ),
    .sreg       (sreg       ),
    .sr_cf      (sr_cf      ),
    .sr_zf      (sr_zf      ),
    .sr_tf      (sr_tf      ),
    .sr_if      (sr_if      )
);

endmodule
module  CPU (
    input           clock,
    input           reset,
    input   [15:0]  pm_rdata,
    output  [15:0]  pm_addr,
    output          pm_re,
    output          pm_we,
    output  [15:0]  pm_wdata,
    input   [7:0]   dm_rdata,
    output  [15:0]  dm_addr,
    output          dm_re,
    output          dm_we,
    output  [7:0]   dm_wdata,
    input   [7:0]   io_rdata,
    output  [7:0]   io_addr,
    output          io_re,
    output          io_we,
    output  [7:0]   io_wdata,
    input           irq,
    input   [15:0]  irq_addr
);





wire[15:0]  pc;
wire[15:0]  pc_new;
wire        pc_new_en;
wire[15:0]  ir;
wire[15:0]  ir_2nd;
wire[1:0]   cycle;
wire        skip_en;
wire        irq_det;
wire        irq_ret;
wire[0:82]  op_decode;
wire        tim_cyc_end;
wire        tim_pc_en;
wire        tim_pm_re;
wire        tim_dm_re;
wire        tim_dm_we;
wire        tim_rf_we;
wire        tim_sr_en;
wire        tim_sp_en;
wire[15:0]  alu_ai;
wire[15:0]  alu_bi;
wire        alu_ci;
wire        sel_adc_b;
wire        sel_sbc_b;
wire        sel_adc_w;
wire        sel_sbc_w;
wire        sel_and;
wire        sel_or;
wire        sel_eor;
wire[15:0]  alu_ro;
wire        alu_cf;
wire        alu_zf;
wire        alu_nf;
wire        alu_vf;
wire        alu_sf;
wire        alu_hf;
wire[15:0]  mul_ro;
wire        mul_cf;
wire        mul_zf;
wire[15:0]  ptr_ai;
wire[15:0]  ptr_ro;
wire[7:0]   bsc_ro;
wire        bst_tf;
wire        mm_sp_l_we;
wire        mm_sp_h_we;
wire        mm_sreg_we;
wire[7:0]   mm_io_wdata;
wire[7:0]   mm_io_rdata;
wire[7:0]   mm_rdata;
wire        mm_rdata_en;
wire[7:0]   lpm_data;
wire        lpm_data_en;
wire[4:0]   rf_waddr;
wire[15:0]  rf_wdata;
wire        rf_we_byte;
wire        rf_we_word;
wire        rf_re_word;
wire[4:0]   rf_raddr_a;
wire[4:0]   rf_raddr_b;
wire[15:0]  rf_rdata_a;
wire[7:0]   rf_rdata_b;
wire[15:0]  sp;
wire[7:0]   sreg;
wire        sr_cf;
wire        sr_zf;
wire        sr_tf;
wire        sr_if;





wire        cpse_zf = (rf_rdata_a[7:0] == rf_rdata_b);

PcAndIr PAI (
    .clock      (clock      ),
    .reset      (reset      ),
    .pm_rdata   (pm_rdata   ),
    .dm_rdata   (dm_rdata   ),
    .io_rdata   (mm_io_rdata),
    .rf_rdata   (rf_rdata_b ),
    .sreg       (sreg       ),
    .alu_ro     (alu_ro     ),
    .alu_zf     (cpse_zf    ),
    .irq        (irq        ),
    .irq_addr   (irq_addr   ),
    .sr_if      (sr_if      ),
    .op_decode  (op_decode  ),
    .tim_cyc_end(tim_cyc_end),
    .tim_pc_en  (tim_pc_en  ),
    .pc         (pc         ),
    .pc_new     (pc_new     ),
    .pc_new_en  (pc_new_en  ),
    .ir         (ir         ),
    .ir_2nd     (ir_2nd     ),
    .cycle      (cycle      ),
    .skip_en    (skip_en    ),
    .irq_det    (irq_det    ),
    .irq_ret    (irq_ret    )
);

OpDecode DEC (
    .ir         (ir         ),
    .op_decode  (op_decode  )
);

TimDecode TIM (
    .ir         (ir         ),
    .cycle      (cycle      ),
    .skip_en    (skip_en    ),
    .tim_cyc_end(tim_cyc_end),
    .tim_pc_en  (tim_pc_en  ),
    .tim_pm_re  (tim_pm_re  ),
    .tim_dm_re  (tim_dm_re  ),
    .tim_dm_we  (tim_dm_we  ),
    .tim_rf_we  (tim_rf_we  ),
    .tim_sr_en  (tim_sr_en  ),
    .tim_sp_en  (tim_sp_en  )
);




AluInput AIN (
    .ir         (ir         ),
    .rf_rdata_a (rf_rdata_a ),
    .rf_rdata_b (rf_rdata_b ),
    .sr_cf      (sr_cf      ),
    .pc         (pc         ),
    .ir_2nd     (ir_2nd     ),
    .alu_ai     (alu_ai     ),
    .alu_bi     (alu_bi     ),
    .alu_ci     (alu_ci     ),
    .sel_adc_b  (sel_adc_b  ),
    .sel_sbc_b  (sel_sbc_b  ),
    .sel_adc_w  (sel_adc_w  ),
    .sel_sbc_w  (sel_sbc_w  ),
    .sel_and    (sel_and    ),
    .sel_or     (sel_or     ),
    .sel_eor    (sel_eor    )
);

ALU ALU (
    .ai         (alu_ai     ),
    .bi         (alu_bi     ),
    .ci         (alu_ci     ),
    .sel_adc_b  (sel_adc_b  ),
    .sel_sbc_b  (sel_sbc_b  ),
    .sel_adc_w  (sel_adc_w  ),
    .sel_sbc_w  (sel_sbc_w  ),
    .sel_and    (sel_and    ),
    .sel_or     (sel_or     ),
    .sel_eor    (sel_eor    ),
    .sr_zf      (sr_zf      ),
    .op_decode  (op_decode  ),
    .ro         (alu_ro     ),
    .cf         (alu_cf     ),
    .zf         (alu_zf     ),
    .nf         (alu_nf     ),
    .vf         (alu_vf     ),
    .sf         (alu_sf     ),
    .hf         (alu_hf     )
);

Multiply MUL (
    .clock      (clock      ),
    .ai         (alu_ai[7:0]),
    .bi         (alu_bi[7:0]),
    .op_decode  (op_decode  ),
    .ro         (mul_ro     ),
    .cf         (mul_cf     ),
    .zf         (mul_zf     )
);

PtrCalc PTR (
    .ir         (ir         ),
    .ir_2nd     (ir_2nd     ),
    .sp         (sp         ),
    .rf_rdata_a (rf_rdata_a ),
    .ptr_ai     (ptr_ai     ),
    .ptr_ro     (ptr_ro     )
);

BitSetClr BSC (
    .ir         (ir         ),
    .io_rdata   (mm_io_rdata),
    .rf_rdata   (rf_rdata_b ),
    .sreg       (sreg       ),
    .sr_tf      (sr_tf      ),
    .bsc_ro     (bsc_ro     ),
    .bst_tf     (bst_tf     )
);




PmCont PMC (
    .clock      (clock      ),
    .reset      (reset      ),
    .pm_rdata   (pm_rdata   ),
    .pc         (pc         ),
    .pc_new     (pc_new     ),
    .pc_new_en  (pc_new_en  ),
    .cycle      (cycle      ),
    .skip_en    (skip_en    ),
    .irq_det    (irq_det    ),
    .rf_rdata   (rf_rdata_a ),
    .op_decode  (op_decode  ),
    .tim_pm_re  (tim_pm_re  ),
    .pm_addr    (pm_addr    ),
    .pm_re      (pm_re      ),
    .pm_we      (pm_we      ),
    .pm_wdata   (pm_wdata   ),
    .lpm_data   (lpm_data   ),
    .lpm_data_en(lpm_data_en)
);

DmCont DMC (
    .clock      (clock      ),
    .reset      (reset      ),
    .dm_rdata   (dm_rdata   ),
    .io_rdata   (io_rdata   ),
    .rf_rdata   (rf_rdata_b ),
    .sreg       (sreg       ),
    .sp         (sp         ),
    .pc         (pc         ),
    .ir         (ir         ),
    .cycle      (cycle      ),
    .ptr_ai     (ptr_ai     ),
    .ptr_ro     (ptr_ro     ),
    .bsc_ro     (bsc_ro     ),
    .op_decode  (op_decode  ),
    .tim_dm_re  (tim_dm_re  ),
    .tim_dm_we  (tim_dm_we  ),
    .dm_addr    (dm_addr    ),
    .dm_re      (dm_re      ),
    .dm_we      (dm_we      ),
    .dm_wdata   (dm_wdata   ),
    .io_addr    (io_addr    ),
    .io_re      (io_re      ),
    .io_we      (io_we      ),
    .io_wdata   (io_wdata   ),
    .mm_sp_l_we (mm_sp_l_we ),
    .mm_sp_h_we (mm_sp_h_we ),
    .mm_sreg_we (mm_sreg_we ),
    .mm_io_wdata(mm_io_wdata),
    .mm_io_rdata(mm_io_rdata),
    .mm_rdata   (mm_rdata   ),
    .mm_rdata_en(mm_rdata_en)
);




RfRead RFR (
    .ir         (ir         ),
    .cycle      (cycle      ),
    .re_word    (rf_re_word ),
    .raddr_a    (rf_raddr_a ),
    .raddr_b    (rf_raddr_b )
);

RfWrite RFW (
    .ir         (ir         ),
    .cycle      (cycle      ),
    .alu_ro     (alu_ro     ),
    .mul_ro     (mul_ro     ),
    .ptr_ro     (ptr_ro     ),
    .bsc_ro     (bsc_ro     ),
    .mm_rdata   (mm_rdata   ),
    .mm_rdata_en(mm_rdata_en),
    .lpm_data   (lpm_data   ),
    .lpm_data_en(lpm_data_en),
    .tim_rf_we  (tim_rf_we  ),
    .waddr      (rf_waddr   ),
    .wdata      (rf_wdata   ),
    .we_byte    (rf_we_byte ),
    .we_word    (rf_we_word )
);

RegFile RF (
    .clock      (clock      ),
    .waddr      (rf_waddr   ),
    .wdata      (rf_wdata   ),
    .we_byte    (rf_we_byte ),
    .we_word    (rf_we_word ),
    .re_word    (rf_re_word ),
    .raddr_a    (rf_raddr_a ),
    .raddr_b    (rf_raddr_b ),
    .rdata_a    (rf_rdata_a ),
    .rdata_b    (rf_rdata_b )
);

SregAndSp SAS (
    .clock      (clock      ),
    .reset      (reset      ),
    .ir         (ir         ),
    .alu_cf     (alu_cf     ),
    .alu_zf     (alu_zf     ),
    .alu_nf     (alu_nf     ),
    .alu_vf     (alu_vf     ),
    .alu_sf     (alu_sf     ),
    .alu_hf     (alu_hf     ),
    .mul_cf     (mul_cf     ),
    .mul_zf     (mul_zf     ),
    .ptr_ro     (ptr_ro     ),
    .bsc_ro     (bsc_ro     ),
    .bst_tf     (bst_tf     ),
    .mm_sp_l_we (mm_sp_l_we ),
    .mm_sp_h_we (mm_sp_h_we ),
    .mm_sreg_we (mm_sreg_we ),
    .mm_io_wdata(mm_io_wdata),
    .irq_det    (irq_det    ),
    .irq_ret    (irq_ret    ),
    .tim_sr_en  (tim_sr_en  ),
    .tim_sp_en  (tim_sp_en  ),
    .sp         (sp         ),
    .sreg       (sreg       ),
    .sr_cf      (sr_cf      ),
    .sr_zf      (sr_zf      ),
    .sr_tf      (sr_tf      ),
    .sr_if      (sr_if      )
);

endmodule