data/full_repos/permissive/13136965/programcounter.v
 line:4: before: "reset"
1: b'%Warning-STMTDLY: data/full_repos/permissive/13136965/programcounter.v:6: Unsupported: Ignoring delay on this delayed statement.\n #6\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/13136965/programcounter.v:2: Duplicate declaration of signal: \'cnt\'\n                                                              : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg [31:0] cnt;\n           ^~~\n        data/full_repos/permissive/13136965/programcounter.v:1: ... Location of original declaration\nmodule programcounter(input [31:0] in,input clk,output [31:0] cnt,input reset);\n                                                              ^~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module programcounter(input [31:0] in,input clk,output [31:0] cnt,input reset);
reg [31:0] cnt;

always @(negedge clk,reset)
begin
	#6
	cnt[31:0] = in[31:0];
	if(reset==1'b1)
		cnt[31:0] = 32'b00000000000000000000000000000000;	
end

initial
	begin
		cnt[31:0] = 32'b00000000000000000000000000000000;
	end

endmodule
module programcounter(input [31:0] in,input clk,output [31:0] cnt,input reset);

reg [31:0] cnt;

always @(negedge clk,reset)
begin
	#6
	cnt[31:0] = in[31:0];
	if(reset==1'b1)
		cnt[31:0] = 32'b00000000000000000000000000000000;	
end

initial
	begin
		cnt[31:0] = 32'b00000000000000000000000000000000;
	end

endmodule