data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/w_init_controller.v
None: at end of input
1: b'%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/w_init_controller.v:22: Cannot find include file: common.h\n`include "common.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h.v\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h.sv\n             common.h\n             common.h.v\n             common.h.sv\n             obj_dir/common.h\n             obj_dir/common.h.v\n             obj_dir/common.h.sv\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/w_init_controller.v:46: Define or directive not defined: \'`BW_DATA_IN\'\nparameter BW_DATA_IN = `BW_DATA_IN;\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/w_init_controller.v:46: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DATA_IN = `BW_DATA_IN;\n                                  ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/w_init_controller.v:47: Define or directive not defined: \'`BW_DATA\'\nparameter BW_DATA = `BW_DATA;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/w_init_controller.v:47: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DATA = `BW_DATA;\n                            ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/w_init_controller.v:48: Define or directive not defined: \'`NUM_W_MODULE\'\nparameter NUM_W_MODULE = `NUM_W_MODULE;\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/w_init_controller.v:48: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter NUM_W_MODULE = `NUM_W_MODULE;\n                                      ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/w_init_controller.v:49: Define or directive not defined: \'`BW_DIM_EMB\'\nparameter BW_DIM_EMB = `BW_DIM_EMB;\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/w_init_controller.v:49: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter BW_DIM_EMB = `BW_DIM_EMB;\n                                  ^\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/w_init_controller.v:50: Define or directive not defined: \'`DIM_EMB\'\nparameter DIM_EMB = `DIM_EMB;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/w_init_controller.v:50: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter DIM_EMB = `DIM_EMB;\n                            ^\n%Error: Exiting due to 11 error(s)\n'
module w_init_controller
(

    clk,

    rst_n,

    en_w_load_to_fpga,
    valid_fifo_in,
    data_fifo_in,


    we,
    data_out,
    addr_out


);




parameter BW_DATA_IN = `BW_DATA_IN;
parameter BW_DATA = `BW_DATA;
parameter NUM_W_MODULE = `NUM_W_MODULE;
parameter BW_DIM_EMB = `BW_DIM_EMB;
parameter DIM_EMB = `DIM_EMB;





input wire clk;

input wire rst_n;

input wire en_w_load_to_fpga;
input wire valid_fifo_in;
input wire [BW_DATA_IN-1:0] data_fifo_in;


output reg we;
output wire [BW_DATA*DIM_EMB-1:0] data_out;
output reg [BW_DATA_IN-1:0] addr_out;




genvar i;

reg [BW_DATA-1:0] _data_out [0:DIM_EMB-1];

reg en_w_load_to_fpga_sync;

wire rst_n_count_buf_32;
wire en_count_buf_32;
wire count_count_buf_32;
wire done_count_buf_32;

wire rst_n_count_emb_vec;
wire en_count_emb_vec;
wire [BW_DIM_EMB-1:0] count_count_emb_vec;
wire done_count_emb_vec;

wire [BW_DIM_EMB-1:0] addr_emb_vec;

wire we_addr_out;
reg done_addr_out;

wire done;

wire [BW_DATA-1:0] _data_out_16_to_32;
wire [BW_DATA_IN-1:0] _ext_low_bit;

reg [BW_DATA-1:0] data_buf_32;
wire addr_data_buf_32;

wire we_data_out_buf_32;
reg we_data_out;




assign we_addr_out = en_w_load_to_fpga_sync&&valid_fifo_in&&(!done_addr_out);
assign we_data_out_buf_32 = en_w_load_to_fpga_sync&&valid_fifo_in&&(done_addr_out);


assign rst_n_count_buf_32 = rst_n&&en_w_load_to_fpga_sync;
assign en_count_buf_32 = en_w_load_to_fpga_sync&&done_addr_out&&valid_fifo_in;

assign rst_n_count_emb_vec = rst_n&&en_w_load_to_fpga_sync;

assign en_count_emb_vec = we_data_out;

assign addr_data_buf_32 = count_count_buf_32;
assign addr_emb_vec = count_count_emb_vec;

assign done = en_w_load_to_fpga_sync&&done_count_emb_vec;










always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_w_load_to_fpga_sync <= 1'b0;
    else
        if(done==1'b1)
            en_w_load_to_fpga_sync <= 1'b0;
        else
            if(en_w_load_to_fpga_sync==1'b0)
                en_w_load_to_fpga_sync <= en_w_load_to_fpga;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        we <= 1'b0;
    else
        if(we==1'b0)
            we <= done;
        else
            we <= 1'b0;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        we_data_out <= 1'b0;
    else
        if(done_count_buf_32==1'b1)
            we_data_out <= en_count_buf_32;
        else
            we_data_out <= 1'b0;

end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        data_buf_32 <= {32{1'b0}};
    else
        if(we_data_out_buf_32==1'b1)
            if(addr_data_buf_32==1'b0)
                data_buf_32[31:16] <= data_fifo_in;
            else
                data_buf_32[15:0] <= data_fifo_in;
end

generate
    for(i=0;i<DIM_EMB;i=i+1)
    begin
        assign data_out[(i+1)*BW_DATA-1-:BW_DATA] = _data_out[i];
    end
endgenerate

generate
    for(i=0;i<DIM_EMB;i=i+1)
    begin
        always@(posedge clk or negedge rst_n)
        begin
            if(rst_n==1'b0)
                _data_out[i] <= {BW_DATA{1'b0}};
            else
                if((we_data_out==1'b1)&&(i==addr_emb_vec))

                    _data_out[i] <= data_buf_32;
        end
    end
endgenerate

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        done_addr_out <= 1'b0;
    else
        if(done==1'b1)
            done_addr_out <= 1'b0;
        else
            if(we_addr_out==1'b1)
                done_addr_out <=1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        addr_out <= {BW_DATA_IN{1'b0}};
    else
        if(we_addr_out==1'b1)
            addr_out <= data_fifo_in;
end





counter
#(
    .BW(1),
    .COUNT_VALUE(1)
)
count_buf_32
(

    .clk(clk),

    .rst_n(rst_n_count_buf_32),

    .en(en_count_buf_32),
    .en_hold_max(1'b0),

    .count(count_count_buf_32),
    .done(done_count_buf_32)
);

counter
#(
    .BW(BW_DIM_EMB+1),
    .COUNT_VALUE(DIM_EMB)
)
count_emb_vec
(

    .clk(clk),

    .rst_n(rst_n_count_emb_vec),

    .en(en_count_emb_vec),
    .en_hold_max(1'b0),

    .count(count_count_emb_vec),
    .done(done_count_emb_vec)
);




`ifdef DEBUG
`ifdef DEBUG_ILA

ila
w_init_controller
(
    .clk(clk),


    .probe0(en_w_load_to_fpga),
    .probe1(valid_fifo_in),
    .probe2(we),
    .probe3(en_w_load_to_fpga_sync),
    .probe4(rst_n_count_emb_vec),
    .probe5(en_count_emb_vec),
    .probe6(done_count_emb_vec),
    .probe7(we_addr_out),


    .probe8(done_addr_out),
    .probe9(done),
    .probe10(),
    .probe11(),
    .probe12(),
    .probe13(),
    .probe14(),
    .probe15(),


    .probe16(data_fifo_in),
    .probe17(addr_out),
    .probe18(),
    .probe19(),
    .probe20(),
    .probe21(),
    .probe22(),
    .probe23(),


    .probe24(count_count_emb_vec),
    .probe25(addr_emb_vec),
    .probe26(_data_out[0]),
    .probe27(_data_out[1]),
    .probe28(_data_out[31]),
    .probe29(data_out[(0+1)*BW_DATA-1-:BW_DATA]),
    .probe30(data_out[(1+1)*BW_DATA-1-:BW_DATA]),
    .probe31(data_out[(31+1)*BW_DATA-1-:BW_DATA]),


    .probe32(),
    .probe33(),
    .probe34(),
    .probe35(),
    .probe36(),
    .probe37(),
    .probe38(),
    .probe39(),


    .probe40(),
    .probe41(),
    .probe42(),
    .probe43(),
    .probe44(),
    .probe45(),
    .probe46(),
    .probe47(),


    .probe48(),
    .probe49(),
    .probe50(),
    .probe51(),
    .probe52(),
    .probe53(),
    .probe54(),
    .probe55(),


    .probe56(),
    .probe57(),
    .probe58(),
    .probe59(),
    .probe60(),
    .probe61(),
    .probe62(),
    .probe63()
);
`endif
`endif


endmodule
module w_init_controller
(

    clk,

    rst_n,

    en_w_load_to_fpga,
    valid_fifo_in,
    data_fifo_in,


    we,
    data_out,
    addr_out


);





parameter BW_DATA_IN = `BW_DATA_IN;
parameter BW_DATA = `BW_DATA;
parameter NUM_W_MODULE = `NUM_W_MODULE;
parameter BW_DIM_EMB = `BW_DIM_EMB;
parameter DIM_EMB = `DIM_EMB;





input wire clk;

input wire rst_n;

input wire en_w_load_to_fpga;
input wire valid_fifo_in;
input wire [BW_DATA_IN-1:0] data_fifo_in;


output reg we;
output wire [BW_DATA*DIM_EMB-1:0] data_out;
output reg [BW_DATA_IN-1:0] addr_out;




genvar i;

reg [BW_DATA-1:0] _data_out [0:DIM_EMB-1];

reg en_w_load_to_fpga_sync;

wire rst_n_count_buf_32;
wire en_count_buf_32;
wire count_count_buf_32;
wire done_count_buf_32;

wire rst_n_count_emb_vec;
wire en_count_emb_vec;
wire [BW_DIM_EMB-1:0] count_count_emb_vec;
wire done_count_emb_vec;

wire [BW_DIM_EMB-1:0] addr_emb_vec;

wire we_addr_out;
reg done_addr_out;

wire done;

wire [BW_DATA-1:0] _data_out_16_to_32;
wire [BW_DATA_IN-1:0] _ext_low_bit;

reg [BW_DATA-1:0] data_buf_32;
wire addr_data_buf_32;

wire we_data_out_buf_32;
reg we_data_out;




assign we_addr_out = en_w_load_to_fpga_sync&&valid_fifo_in&&(!done_addr_out);
assign we_data_out_buf_32 = en_w_load_to_fpga_sync&&valid_fifo_in&&(done_addr_out);


assign rst_n_count_buf_32 = rst_n&&en_w_load_to_fpga_sync;
assign en_count_buf_32 = en_w_load_to_fpga_sync&&done_addr_out&&valid_fifo_in;

assign rst_n_count_emb_vec = rst_n&&en_w_load_to_fpga_sync;

assign en_count_emb_vec = we_data_out;

assign addr_data_buf_32 = count_count_buf_32;
assign addr_emb_vec = count_count_emb_vec;

assign done = en_w_load_to_fpga_sync&&done_count_emb_vec;










always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        en_w_load_to_fpga_sync <= 1'b0;
    else
        if(done==1'b1)
            en_w_load_to_fpga_sync <= 1'b0;
        else
            if(en_w_load_to_fpga_sync==1'b0)
                en_w_load_to_fpga_sync <= en_w_load_to_fpga;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        we <= 1'b0;
    else
        if(we==1'b0)
            we <= done;
        else
            we <= 1'b0;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        we_data_out <= 1'b0;
    else
        if(done_count_buf_32==1'b1)
            we_data_out <= en_count_buf_32;
        else
            we_data_out <= 1'b0;

end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        data_buf_32 <= {32{1'b0}};
    else
        if(we_data_out_buf_32==1'b1)
            if(addr_data_buf_32==1'b0)
                data_buf_32[31:16] <= data_fifo_in;
            else
                data_buf_32[15:0] <= data_fifo_in;
end

generate
    for(i=0;i<DIM_EMB;i=i+1)
    begin
        assign data_out[(i+1)*BW_DATA-1-:BW_DATA] = _data_out[i];
    end
endgenerate

generate
    for(i=0;i<DIM_EMB;i=i+1)
    begin
        always@(posedge clk or negedge rst_n)
        begin
            if(rst_n==1'b0)
                _data_out[i] <= {BW_DATA{1'b0}};
            else
                if((we_data_out==1'b1)&&(i==addr_emb_vec))

                    _data_out[i] <= data_buf_32;
        end
    end
endgenerate

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        done_addr_out <= 1'b0;
    else
        if(done==1'b1)
            done_addr_out <= 1'b0;
        else
            if(we_addr_out==1'b1)
                done_addr_out <=1'b1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        addr_out <= {BW_DATA_IN{1'b0}};
    else
        if(we_addr_out==1'b1)
            addr_out <= data_fifo_in;
end





counter
#(
    .BW(1),
    .COUNT_VALUE(1)
)
count_buf_32
(

    .clk(clk),

    .rst_n(rst_n_count_buf_32),

    .en(en_count_buf_32),
    .en_hold_max(1'b0),

    .count(count_count_buf_32),
    .done(done_count_buf_32)
);

counter
#(
    .BW(BW_DIM_EMB+1),
    .COUNT_VALUE(DIM_EMB)
)
count_emb_vec
(

    .clk(clk),

    .rst_n(rst_n_count_emb_vec),

    .en(en_count_emb_vec),
    .en_hold_max(1'b0),

    .count(count_count_emb_vec),
    .done(done_count_emb_vec)
);




`ifdef DEBUG
`ifdef DEBUG_ILA

ila
w_init_controller
(
    .clk(clk),


    .probe0(en_w_load_to_fpga),
    .probe1(valid_fifo_in),
    .probe2(we),
    .probe3(en_w_load_to_fpga_sync),
    .probe4(rst_n_count_emb_vec),
    .probe5(en_count_emb_vec),
    .probe6(done_count_emb_vec),
    .probe7(we_addr_out),


    .probe8(done_addr_out),
    .probe9(done),
    .probe10(),
    .probe11(),
    .probe12(),
    .probe13(),
    .probe14(),
    .probe15(),


    .probe16(data_fifo_in),
    .probe17(addr_out),
    .probe18(),
    .probe19(),
    .probe20(),
    .probe21(),
    .probe22(),
    .probe23(),


    .probe24(count_count_emb_vec),
    .probe25(addr_emb_vec),
    .probe26(_data_out[0]),
    .probe27(_data_out[1]),
    .probe28(_data_out[31]),
    .probe29(data_out[(0+1)*BW_DATA-1-:BW_DATA]),
    .probe30(data_out[(1+1)*BW_DATA-1-:BW_DATA]),
    .probe31(data_out[(31+1)*BW_DATA-1-:BW_DATA]),


    .probe32(),
    .probe33(),
    .probe34(),
    .probe35(),
    .probe36(),
    .probe37(),
    .probe38(),
    .probe39(),


    .probe40(),
    .probe41(),
    .probe42(),
    .probe43(),
    .probe44(),
    .probe45(),
    .probe46(),
    .probe47(),


    .probe48(),
    .probe49(),
    .probe50(),
    .probe51(),
    .probe52(),
    .probe53(),
    .probe54(),
    .probe55(),


    .probe56(),
    .probe57(),
    .probe58(),
    .probe59(),
    .probe60(),
    .probe61(),
    .probe62(),
    .probe63()
);
`endif
`endif


endmodule