data/full_repos/permissive/154804262/testBench/UartTx_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/UartTx_tb.v:7: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/UartTx_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #50 reset = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/UartTx_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #34567 reset = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/UartTx_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #20 reset = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/UartTx_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #300000 reset = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/UartTx_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #2000 reset = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/154804262/testBench/UartTx_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #300000 txEnable = ~txEnable;\n  ^\n%Error: data/full_repos/permissive/154804262/testBench/UartTx_tb.v:32: Cannot find file containing module: \'UartTx\'\n UartTx UartTxIns(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154804262/testBench,data/full_repos/permissive/154804262/UartTx\n             data/full_repos/permissive/154804262/testBench,data/full_repos/permissive/154804262/UartTx.v\n             data/full_repos/permissive/154804262/testBench,data/full_repos/permissive/154804262/UartTx.sv\n             UartTx\n             UartTx.v\n             UartTx.sv\n             obj_dir/UartTx\n             obj_dir/UartTx.v\n             obj_dir/UartTx.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UartTx_tb;

	reg clk;
	initial
		clk = 1'b0;
	always
		#5 clk = ~clk;

	reg reset;
	initial
	begin
		reset = 1'b0;
		#50 reset = 1'b1;
		#34567 reset = 1'b0;
		#20 reset = 1'b1;
		#300000 reset = 1'b0;
		#2000 reset = 1'b1;
	end
	
	reg txEnable;
	initial
		txEnable = 1'b0;
	always
		#300000 txEnable = ~txEnable;
	
	reg[7:0] uartInByte;
	initial
		uartInByte = 8'h72;

	wire uartTxBit;
	wire uartTxDone;
	UartTx UartTxIns(
		.clk(clk),
		.reset(reset),
		.txEnable(txEnable),
		.uartInByte(uartInByte),
		.uartTxBit(uartTxBit),
		.uartTxDone(uartTxDone)
		);

endmodule
module UartTx_tb;


	reg clk;
	initial
		clk = 1'b0;
	always
		#5 clk = ~clk;

	reg reset;
	initial
	begin
		reset = 1'b0;
		#50 reset = 1'b1;
		#34567 reset = 1'b0;
		#20 reset = 1'b1;
		#300000 reset = 1'b0;
		#2000 reset = 1'b1;
	end
	
	reg txEnable;
	initial
		txEnable = 1'b0;
	always
		#300000 txEnable = ~txEnable;
	
	reg[7:0] uartInByte;
	initial
		uartInByte = 8'h72;

	wire uartTxBit;
	wire uartTxDone;
	UartTx UartTxIns(
		.clk(clk),
		.reset(reset),
		.txEnable(txEnable),
		.uartInByte(uartInByte),
		.uartTxBit(uartTxBit),
		.uartTxDone(uartTxDone)
		);

endmodule