data/full_repos/permissive/186491764/Instruction_Memory.v
data/verilator_xmls/9d003f9c-3358-4412-b621-8fb7a792d6ec.xml
module Instruction_Memory(
 input[15:0] pc,
 output[15:0] instruction
    );
	 
reg [15:0] memory [9:0];
 wire [3 : 0] location = pc[4 : 1];
 
 initial
 begin

 memory [0] = 16'b0100010001000010;
 memory [1] = 16'b0100010011000001;
 memory [2] = 16'b0100010100000011;
 memory [3] = 16'b0100010101000100;
 memory [4] = 16'b0000000000000000;
 memory [5] = 16'b1000001011001000;
 memory [6] = 16'b1010001011011000;
 memory [7] = 16'b1010000100000000;
 memory [8] = 16'b1110000101111100;
 memory [9] = 16'b0010001000000000;
 end
 assign instruction =  memory[location]; 

endmodule
module Instruction_Memory(
 input[15:0] pc,
 output[15:0] instruction
    );

	 
reg [15:0] memory [9:0];
 wire [3 : 0] location = pc[4 : 1];
 
 initial
 begin

 memory [0] = 16'b0100010001000010;
 memory [1] = 16'b0100010011000001;
 memory [2] = 16'b0100010100000011;
 memory [3] = 16'b0100010101000100;
 memory [4] = 16'b0000000000000000;
 memory [5] = 16'b1000001011001000;
 memory [6] = 16'b1010001011011000;
 memory [7] = 16'b1010000100000000;
 memory [8] = 16'b1110000101111100;
 memory [9] = 16'b0010001000000000;
 end
 assign instruction =  memory[location]; 

endmodule