data/full_repos/permissive/20101677/vgamem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/20101677/vgamem.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 12 bits.\n                                                               : ... In instance vgamem\nassign line   = ypos / 16;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20101677/vgamem.v:67: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 12 bits.\n                                                               : ... In instance vgamem\nassign column = xpos / 8;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/20101677/vgamem.v:70: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                               : ... In instance vgamem\nassign char = doutb[15:8];\n            ^\n%Error: data/full_repos/permissive/20101677/vgamem.v:81: Cannot find file containing module: \'memchar\'\nmemchar charmem (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20101677,data/full_repos/permissive/20101677/memchar\n             data/full_repos/permissive/20101677,data/full_repos/permissive/20101677/memchar.v\n             data/full_repos/permissive/20101677,data/full_repos/permissive/20101677/memchar.sv\n             memchar\n             memchar.v\n             memchar.sv\n             obj_dir/memchar\n             obj_dir/memchar.v\n             obj_dir/memchar.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module vgamem(

	input wire clr,


    input wire clka,
	input wire ena,
	input wire wea,
	input wire [12:0] addra,
	input wire [15:0] dina,
	output wire [15:0] douta,



    input wire clkb,
	output wire [6:0] char,
	output wire [7:0] fontcolor,
	output wire [7:0] backcolor,
	output wire Blink,



	input wire xsync,
	input wire ysync,
	input wire [11:0] xpos,
	input wire [11:0] ypos,
	input wire valid,

	output reg hsync,
	output reg vsync,
	output reg [11:0] hc,
	output reg [11:0] vc,
	output reg vidon
    );

wire [12:0] addrb;
wire [15:0] dinb;
wire [15:0] doutb;

wire Increase;
wire [2:0] backRGB;
wire [2:0] fontRGB;


wire [6:0] column;
wire [5:0] line;

assign line   = ypos / 16;
assign column = xpos / 8;

assign addrb = {line, column};
assign char = doutb[15:8];
assign {Blink, backRGB, Increase, fontRGB} = doutb[7:0];

assign fontcolor = {Increase, fontRGB[2], 1'b0,
                    Increase, fontRGB[1], 1'b0,
					Increase, fontRGB[0]};

assign backcolor = {1'b0, backRGB[2], 1'b0,
                    1'b0, backRGB[1], 1'b0,
					1'b0, backRGB[0]};

memchar charmem (

  .clka(clka),
  .ena(ena),
  .wea(wea),
  .addra(addra),
  .dina(dina),
  .douta(douta),

  .clkb(clkb),
  .enb(valid),
  .web(1'b0),
  .addrb(addrb),
  .dinb(dinb),
  .doutb(doutb)
);

always @(posedge clkb) begin
    hsync <= xsync;
	vsync <= ysync;
	hc <= xpos;
	vc <= ypos;
	vidon <= valid;
end

endmodule
module vgamem(

	input wire clr,


    input wire clka,
	input wire ena,
	input wire wea,
	input wire [12:0] addra,
	input wire [15:0] dina,
	output wire [15:0] douta,



    input wire clkb,
	output wire [6:0] char,
	output wire [7:0] fontcolor,
	output wire [7:0] backcolor,
	output wire Blink,



	input wire xsync,
	input wire ysync,
	input wire [11:0] xpos,
	input wire [11:0] ypos,
	input wire valid,

	output reg hsync,
	output reg vsync,
	output reg [11:0] hc,
	output reg [11:0] vc,
	output reg vidon
    );


wire [12:0] addrb;
wire [15:0] dinb;
wire [15:0] doutb;

wire Increase;
wire [2:0] backRGB;
wire [2:0] fontRGB;


wire [6:0] column;
wire [5:0] line;

assign line   = ypos / 16;
assign column = xpos / 8;

assign addrb = {line, column};
assign char = doutb[15:8];
assign {Blink, backRGB, Increase, fontRGB} = doutb[7:0];

assign fontcolor = {Increase, fontRGB[2], 1'b0,
                    Increase, fontRGB[1], 1'b0,
					Increase, fontRGB[0]};

assign backcolor = {1'b0, backRGB[2], 1'b0,
                    1'b0, backRGB[1], 1'b0,
					1'b0, backRGB[0]};

memchar charmem (

  .clka(clka),
  .ena(ena),
  .wea(wea),
  .addra(addra),
  .dina(dina),
  .douta(douta),

  .clkb(clkb),
  .enb(valid),
  .web(1'b0),
  .addrb(addrb),
  .dinb(dinb),
  .doutb(doutb)
);

always @(posedge clkb) begin
    hsync <= xsync;
	vsync <= ysync;
	hc <= xpos;
	vc <= ypos;
	vidon <= valid;
end

endmodule