data/full_repos/permissive/126791278/testbenches/tb_programCounter.v
 line:23: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_programCounter.v:12: Unsupported: Ignoring delay on this delayed statement.\n #000 clk = 1\'b1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_programCounter.v:13: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk <= ~clk;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_programCounter.v:18: Unsupported: Ignoring delay on this delayed statement.\n #00 C_PCWrite=1\'b1; PC_IN <= 16\'d15;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_programCounter.v:19: Unsupported: Ignoring delay on this delayed statement.\n #50 PC_IN <= 16\'d20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_programCounter.v:20: Unsupported: Ignoring delay on this delayed statement.\n #50 PC_IN <= 16\'d01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_programCounter.v:21: Unsupported: Ignoring delay on this delayed statement.\n #50 C_PCWrite <= 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_programCounter.v:22: Unsupported: Ignoring delay on this delayed statement.\n #50 PC_IN <= 16\'d0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/126791278/testbenches/tb_programCounter.v:23: Unsupported: Ignoring delay on this delayed statement.\n #50 $stop;\n ^\n%Error: data/full_repos/permissive/126791278/testbenches/tb_programCounter.v:28: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("programCounter.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/126791278/testbenches/tb_programCounter.v:29: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/126791278/testbenches/tb_programCounter.v:32: Unsupported or unknown PLI call: $monitor\ninitial $monitor("time=%3d, PC_OUT=%16h, PC_IN=%16h, C_PCWrite=%b", $time, PC_OUT, PC_IN, C_PCWrite);\n        ^~~~~~~~\n%Error: Exiting due to 3 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_dataMemory();

reg [15:0]PC_IN;
reg  clk, C_PCWrite;
wire [15:0] PC_OUT;

programCounter uut(PC_OUT, PC_IN, C_PCWrite, clk);

initial
begin
	#000 clk = 1'b1;
	forever #10 clk <= ~clk;
end

initial
begin	
	#00 C_PCWrite=1'b1;	PC_IN <= 16'd15;
	#50 PC_IN <= 16'd20;
	#50 PC_IN <= 16'd01;
	#50 C_PCWrite <= 1'b0;
	#50 PC_IN <= 16'd0;
	#50 $stop;
end

initial
begin
	$dumpfile("programCounter.vcd");
	$dumpvars;
end

initial $monitor("time=%3d, PC_OUT=%16h, PC_IN=%16h, C_PCWrite=%b", $time, PC_OUT, PC_IN, C_PCWrite);

endmodule
module tb_dataMemory();


reg [15:0]PC_IN;
reg  clk, C_PCWrite;
wire [15:0] PC_OUT;

programCounter uut(PC_OUT, PC_IN, C_PCWrite, clk);

initial
begin
	#000 clk = 1'b1;
	forever #10 clk <= ~clk;
end

initial
begin	
	#00 C_PCWrite=1'b1;	PC_IN <= 16'd15;
	#50 PC_IN <= 16'd20;
	#50 PC_IN <= 16'd01;
	#50 C_PCWrite <= 1'b0;
	#50 PC_IN <= 16'd0;
	#50 $stop;
end

initial
begin
	$dumpfile("programCounter.vcd");
	$dumpvars;
end

initial $monitor("time=%3d, PC_OUT=%16h, PC_IN=%16h, C_PCWrite=%b", $time, PC_OUT, PC_IN, C_PCWrite);

endmodule