data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v
'utf-8' codec can't decode byte 0xbe in position 6: invalid start byte
1: b'%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v\n             data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.v\n             data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new,data/full_repos/permissive/115162999/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:9: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus]   addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus]   addr,\n                        ^\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:10: Define or directive not defined: \'`InstBus\'\n output reg[`InstBus]     inst\n            ^~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:14: Define or directive not defined: \'`InstMemNum\'\n reg[7:0]  inst_mem[0:`InstMemNum-1];\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:16: syntax error, unexpected initial\n initial $readmemh ( "ori.mem", inst_mem );\n ^~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:19: Define or directive not defined: \'`ChipDisable\'\n  if (ce == `ChipDisable) begin\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/115162999/src/CPU.srcs/sim_1/new/inst_rom.v:20: Define or directive not defined: \'`ZeroWord\'\n   inst <= `ZeroWord;\n           ^~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module inst_rom(


	input wire                    ce,
	input wire[`InstAddrBus]			addr,
	output reg[`InstBus]					inst
	
);

	reg[7:0]  inst_mem[0:`InstMemNum-1];

	initial $readmemh ( "ori.mem", inst_mem );

	always @ (*) begin
		if (ce == `ChipDisable) begin
			inst <= `ZeroWord;
	  end else begin
		  inst <= {inst_mem[addr[31:0]+3], inst_mem[addr[31:0]+2], inst_mem[addr[31:0]+1], inst_mem[addr[31:0]]};
		end
	end

endmodule
module inst_rom(


	input wire                    ce,
	input wire[`InstAddrBus]			addr,
	output reg[`InstBus]					inst
	
);


	reg[7:0]  inst_mem[0:`InstMemNum-1];

	initial $readmemh ( "ori.mem", inst_mem );

	always @ (*) begin
		if (ce == `ChipDisable) begin
			inst <= `ZeroWord;
	  end else begin
		  inst <= {inst_mem[addr[31:0]+3], inst_mem[addr[31:0]+2], inst_mem[addr[31:0]+1], inst_mem[addr[31:0]]};
		end
	end

endmodule