data/full_repos/permissive/112626266/PIPELINE.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/112626266/PIPELINE.v:23: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'IFID\'\nmodule IFID(clock,Inst,IFIDWrite ,PcPlusFour,InstReg,PcPlusFourReg);\n       ^~~~\n                                                                     : ... Top module \'IDEX\'\nmodule IDEX(clock,WB,M,EX,DataA,DataB,imm_value,RegRs,RegRt,RegRd,WBreg,Mreg,EXreg,DataAreg,\n       ^~~~\n                                                                     : ... Top module \'EXMEM\'\nmodule EXMEM(clock,WB,M,ALUOut,RegRD,WriteDataIn,Mreg,WBreg,ALUreg,RegRDreg,WriteDataOut);\n       ^~~~~\n                                                                     : ... Top module \'MEMWB\'\nmodule MEMWB(clock,WB,Memout,ALUOut,RegRD,WBreg,Memreg,ALUreg,RegRDreg);\n       ^~~~~\n%Error: Exiting due to 1 warning(s)\n'
module MEMWB(clock,WB,Memout,ALUOut,RegRD,WBreg,Memreg,ALUreg,RegRDreg);
input                   clock;
input           [1:0]   WB;
input           [4:0]   RegRD;
input           [31:0]  Memout,ALUOut;
output  reg     [1:0]   WBreg;
output  reg     [31:0]  Memreg,ALUreg;
output  reg     [4:0]   RegRDreg;
initial 
begin
WBreg = 0;
Memreg = 0;
ALUreg = 0;
RegRDreg = 0;
end
always@(posedge clock)
begin
WBreg <= WB;
Memreg <= Memout;
ALUreg <= ALUOut;
RegRDreg <= RegRD;
end
endmodule
module MEMWB(clock,WB,Memout,ALUOut,RegRD,WBreg,Memreg,ALUreg,RegRDreg);

input                   clock;
input           [1:0]   WB;
input           [4:0]   RegRD;
input           [31:0]  Memout,ALUOut;
output  reg     [1:0]   WBreg;
output  reg     [31:0]  Memreg,ALUreg;
output  reg     [4:0]   RegRDreg;
initial 
begin
WBreg = 0;
Memreg = 0;
ALUreg = 0;
RegRDreg = 0;
end
always@(posedge clock)
begin
WBreg <= WB;
Memreg <= Memout;
ALUreg <= ALUOut;
RegRDreg <= RegRD;
end
endmodule