data/full_repos/permissive/189570969/1180300220-崔涵/1180300220-崔涵-完整工程/project_1.srcs/sources_1/new/compare.v
1: b"%Error: data/full_repos/permissive/189570969/1180300220-\xe5\xb4\x94\xe6\xb6\xb5/1180300220-\xe5\xb4\x94\xe6\xb6\xb5-\xe5\xae\x8c\xe6\x95\xb4\xe5\xb7\xa5\xe7\xa8\x8b/project_1.srcs/sources_1/new/compare.v:45: Duplicate declaration of signal: 'answer'\n    reg answer;\n        ^~~~~~\n        data/full_repos/permissive/189570969/1180300220-\xe5\xb4\x94\xe6\xb6\xb5/1180300220-\xe5\xb4\x94\xe6\xb6\xb5-\xe5\xae\x8c\xe6\x95\xb4\xe5\xb7\xa5\xe7\xa8\x8b/project_1.srcs/sources_1/new/compare.v:42: ... Location of original declaration\n    output reg answer\n               ^~~~~~\n%Error: Exiting due to 1 error(s)\n"
module compar(
    input d11,
    input d12,
    input d13,
    input d14,
    input d21,
    input d22,
    input d23,
    input d24,
    input d31,
    input d32,
    input d33,
    input d34,
    input d41,
    input d42,
    input d43,
    input d44,
    input  change,
    input  enter,
    output reg answer
    );
    reg [15:0] code = 16'b0001000100010001;
    reg answer;
    always@(*)
    
    begin
    if(enter == 1)
      answer = ({d11,d12,d13,d14,d21,d22,d23,d24,d31,d32,d33,d34,d41,d42,d43,d44} == code)? 1'b1:1'b0;
      if(answer && change == 1)
        code = {d11,d12,d13,d14,d21,d22,d23,d24,d31,d32,d33,d34,d41,d42,d43,d44};
    end
endmodule
module compar(
    input d11,
    input d12,
    input d13,
    input d14,
    input d21,
    input d22,
    input d23,
    input d24,
    input d31,
    input d32,
    input d33,
    input d34,
    input d41,
    input d42,
    input d43,
    input d44,
    input  change,
    input  enter,
    output reg answer
    );

    reg [15:0] code = 16'b0001000100010001;
    reg answer;
    always@(*)
    
    begin
    if(enter == 1)
      answer = ({d11,d12,d13,d14,d21,d22,d23,d24,d31,d32,d33,d34,d41,d42,d43,d44} == code)? 1'b1:1'b0;
      if(answer && change == 1)
        code = {d11,d12,d13,d14,d21,d22,d23,d24,d31,d32,d33,d34,d41,d42,d43,d44};
    end
endmodule