data/full_repos/permissive/143278/ivltests/attrib01_module.v
None: at end of input
data/verilator_xmls/1d3203c7-09e8-4063-98c5-fa4e09f6ae83.xml
module bar(clk, rst, inp, out);
  input  wire clk;
  input  wire rst;
  input  wire inp;
  output reg  out;

  always @(posedge clk)
    if (rst) out <= 1'd0;
    else     out <= ~inp;

endmodule
module bar(clk, rst, inp, out);

  input  wire clk;
  input  wire rst;
  input  wire inp;
  output reg  out;

  always @(posedge clk)
    if (rst) out <= 1'd0;
    else     out <= ~inp;

endmodule