data/full_repos/permissive/137045072/forwarding_unit.v
1: b'%Error: data/full_repos/permissive/137045072/forwarding_unit.v:25: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:30: Define or directive not defined: \'`PREG_BUS\'\n    input [`PREG_BUS] dec_prs_addr,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`PREG_BUS] dec_prs_addr,\n                    ^\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:31: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] dec_rs_data,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:33: Define or directive not defined: \'`PREG_BUS\'\n    input [`PREG_BUS] dec_prt_addr,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:34: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] dec_rt_data,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:39: Define or directive not defined: \'`PREG_BUS\'\n    input [`PREG_BUS] exec_write_addr,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:40: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] exec_write,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:44: Define or directive not defined: \'`PREG_BUS\'\n    input [`PREG_BUS] mem_write_addr,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:45: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] mem_write,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:49: Define or directive not defined: \'`PREG_BUS\'\n    input [`PREG_BUS] wb_write_addr,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:50: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] wb_write,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:52: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] dec_rs_override,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:53: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] dec_rt_override\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:63: Define or directive not defined: \'`EX_ALU\'\n            if (exec_wb_reg && exec_exec_src == `EX_ALU && dec_prs_addr == exec_write_addr)\n                                                ^~~~~~~\n%Error: data/full_repos/permissive/137045072/forwarding_unit.v:73: Define or directive not defined: \'`EX_ALU\'\n            if (exec_wb_reg && exec_exec_src == `EX_ALU && dec_prt_addr == exec_write_addr)\n                                                ^~~~~~~\n%Error: Exiting due to 16 error(s)\n'
module forwarding_unit#(parameter DATA_WIDTH = 32)(

    input dec_rs_enable,
    input [`PREG_BUS] dec_prs_addr,
    input [`DATA_BUS] dec_rs_data,
    input dec_rt_enable,
    input [`PREG_BUS] dec_prt_addr,
    input [`DATA_BUS] dec_rt_data,


    input exec_wb_reg,
    input [1:0] exec_exec_src,
    input [`PREG_BUS] exec_write_addr,
    input [`DATA_BUS] exec_write,


    input mem_wb_reg,
    input [`PREG_BUS] mem_write_addr,
    input [`DATA_BUS] mem_write,


    input wb_wb_reg,
    input [`PREG_BUS] wb_write_addr,
    input [`DATA_BUS] wb_write,

    output reg [`DATA_BUS] dec_rs_override,
    output reg [`DATA_BUS] dec_rt_override
    );

    always @*
    begin
        dec_rs_override <= dec_rs_data;
        dec_rt_override <= dec_rt_data;

        if (dec_rs_enable)
        begin
            if (exec_wb_reg && exec_exec_src == `EX_ALU && dec_prs_addr == exec_write_addr)
                dec_rs_override <= exec_write;
            else if (mem_wb_reg && dec_prs_addr == mem_write_addr)
                dec_rs_override <= mem_write;
            else if (wb_wb_reg && dec_prs_addr == wb_write_addr)
                dec_rs_override <= wb_write;
        end

        if (dec_rt_enable)
        begin
            if (exec_wb_reg && exec_exec_src == `EX_ALU && dec_prt_addr == exec_write_addr)
                dec_rt_override <= exec_write;
            else if (mem_wb_reg && dec_prt_addr == mem_write_addr)
                dec_rt_override <= mem_write;
            else if (wb_wb_reg && dec_prt_addr == wb_write_addr)
                dec_rt_override <= wb_write;
        end


    end

endmodule
module forwarding_unit#(parameter DATA_WIDTH = 32)(

    input dec_rs_enable,
    input [`PREG_BUS] dec_prs_addr,
    input [`DATA_BUS] dec_rs_data,
    input dec_rt_enable,
    input [`PREG_BUS] dec_prt_addr,
    input [`DATA_BUS] dec_rt_data,


    input exec_wb_reg,
    input [1:0] exec_exec_src,
    input [`PREG_BUS] exec_write_addr,
    input [`DATA_BUS] exec_write,


    input mem_wb_reg,
    input [`PREG_BUS] mem_write_addr,
    input [`DATA_BUS] mem_write,


    input wb_wb_reg,
    input [`PREG_BUS] wb_write_addr,
    input [`DATA_BUS] wb_write,

    output reg [`DATA_BUS] dec_rs_override,
    output reg [`DATA_BUS] dec_rt_override
    );


    always @*
    begin
        dec_rs_override <= dec_rs_data;
        dec_rt_override <= dec_rt_data;

        if (dec_rs_enable)
        begin
            if (exec_wb_reg && exec_exec_src == `EX_ALU && dec_prs_addr == exec_write_addr)
                dec_rs_override <= exec_write;
            else if (mem_wb_reg && dec_prs_addr == mem_write_addr)
                dec_rs_override <= mem_write;
            else if (wb_wb_reg && dec_prs_addr == wb_write_addr)
                dec_rs_override <= wb_write;
        end

        if (dec_rt_enable)
        begin
            if (exec_wb_reg && exec_exec_src == `EX_ALU && dec_prt_addr == exec_write_addr)
                dec_rt_override <= exec_write;
            else if (mem_wb_reg && dec_prt_addr == mem_write_addr)
                dec_rt_override <= mem_write;
            else if (wb_wb_reg && dec_prt_addr == wb_write_addr)
                dec_rt_override <= wb_write;
        end


    end

endmodule