data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/rtl/b2_demux_1_4_univ.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/rtl/b2_demux_1_4_univ.v:17: Cannot find file containing module: 'bN_demux_1_4_case'\n            bN_demux_1_4_case #(2) dmux\n            ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/rtl,data/full_repos/permissive/147690299/bN_demux_1_4_case\n             data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/rtl,data/full_repos/permissive/147690299/bN_demux_1_4_case.v\n             data/full_repos/permissive/147690299/lab/16_comb_demux_Nbit/rtl,data/full_repos/permissive/147690299/bN_demux_1_4_case.sv\n             bN_demux_1_4_case\n             bN_demux_1_4_case.v\n             bN_demux_1_4_case.sv\n             obj_dir/bN_demux_1_4_case\n             obj_dir/bN_demux_1_4_case.v\n             obj_dir/bN_demux_1_4_case.sv\n%Error: Exiting due to 1 error(s)\n"
module b2_demux_1_4_univ
#(
    parameter MODE = "CASE"
)(
    input  [1:0] din,
    input  [1:0] sel,
    output [1:0] dout0,
    output [1:0] dout1,
    output [1:0] dout2,
    output [1:0] dout3
);

    generate

        if(MODE == "CASE") begin : demux_case
            bN_demux_1_4_case #(2) dmux
            (
                .din    ( din   ),
                .sel    ( sel   ),
                .dout0  ( dout0 ),
                .dout1  ( dout1 ),
                .dout2  ( dout2 ),
                .dout3  ( dout3 ) 
            );
        end


        else if(MODE == "SV") begin : demux_sv
            wire [7:0] dout;
            assign { dout3, dout2, dout1, dout0 } = dout;

            bN_demux_1_N
            #(
                .DATA_WIDTH (2),
                .ADDR_WIDTH (2)
            )
            dmux
            (
                .din  ( din  ),
                .sel  ( sel  ),
                .dout ( dout ) 
            );
        end


        else begin : nothing
            assign dout0 = 2'b0;
            assign dout1 = 2'b0;
            assign dout2 = 2'b0;
            assign dout3 = 2'b0;
        end

    endgenerate
endmodule
module b2_demux_1_4_univ
#(
    parameter MODE = "CASE"
)(
    input  [1:0] din,
    input  [1:0] sel,
    output [1:0] dout0,
    output [1:0] dout1,
    output [1:0] dout2,
    output [1:0] dout3
);


    generate

        if(MODE == "CASE") begin : demux_case
            bN_demux_1_4_case #(2) dmux
            (
                .din    ( din   ),
                .sel    ( sel   ),
                .dout0  ( dout0 ),
                .dout1  ( dout1 ),
                .dout2  ( dout2 ),
                .dout3  ( dout3 ) 
            );
        end


        else if(MODE == "SV") begin : demux_sv
            wire [7:0] dout;
            assign { dout3, dout2, dout1, dout0 } = dout;

            bN_demux_1_N
            #(
                .DATA_WIDTH (2),
                .ADDR_WIDTH (2)
            )
            dmux
            (
                .din  ( din  ),
                .sel  ( sel  ),
                .dout ( dout ) 
            );
        end


        else begin : nothing
            assign dout0 = 2'b0;
            assign dout1 = 2'b0;
            assign dout2 = 2'b0;
            assign dout3 = 2'b0;
        end

    endgenerate
endmodule