data/full_repos/permissive/116468596/count8.v
1: b"%Error: data/full_repos/permissive/116468596/count8.v:37: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD0), .Q(outQ[0]));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.v\n             data/full_repos/permissive/116468596,data/full_repos/permissive/116468596/FDRE.sv\n             FDRE\n             FDRE.v\n             FDRE.sv\n             obj_dir/FDRE\n             obj_dir/FDRE.v\n             obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/116468596/count8.v:38: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD1), .Q(outQ[1]));\n    ^~~~\n%Error: data/full_repos/permissive/116468596/count8.v:39: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD2), .Q(outQ[2]));\n    ^~~~\n%Error: data/full_repos/permissive/116468596/count8.v:40: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD3), .Q(outQ[3]));\n    ^~~~\n%Error: data/full_repos/permissive/116468596/count8.v:41: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) bit5 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD4), .Q(outQ[4]));\n    ^~~~\n%Error: data/full_repos/permissive/116468596/count8.v:42: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) bit6 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD5), .Q(outQ[5]));\n    ^~~~\n%Error: data/full_repos/permissive/116468596/count8.v:43: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) bit7 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD6), .Q(outQ[6]));\n    ^~~~\n%Error: data/full_repos/permissive/116468596/count8.v:44: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) bit8 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD7), .Q(outQ[7]));\n    ^~~~\n%Error: Exiting due to 8 error(s)\n"
module count8(
    input clk, enable, reset,
    output twoSec
    );
    wire [7:0] outQ;
    wire inD0 = enable ^ outQ[0];
    wire inD1 = (enable & outQ[0]) ^ outQ[1];
    wire inD2 = (enable & outQ[0] & outQ[1]) ^ outQ[2];
    wire inD3 = (enable & outQ[0] & outQ[1] & outQ[2]) ^ outQ[3];
    wire inD4 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3]) ^ outQ[4];
    wire inD5 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4]) ^ outQ[5];
    wire inD6 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5]) ^ outQ[6];
    wire inD7 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5] & outQ[6]) ^ outQ[7];

    FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD0), .Q(outQ[0]));
    FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD1), .Q(outQ[1]));
    FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD2), .Q(outQ[2]));
    FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD3), .Q(outQ[3]));
    FDRE #(.INIT(1'b0) ) bit5 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD4), .Q(outQ[4]));
    FDRE #(.INIT(1'b0) ) bit6 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD5), .Q(outQ[5]));
    FDRE #(.INIT(1'b0) ) bit7 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD6), .Q(outQ[6]));
    FDRE #(.INIT(1'b0) ) bit8 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD7), .Q(outQ[7]));

    assign twoSec = ( ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & outQ[7] );   
    
endmodule
module count8(
    input clk, enable, reset,
    output twoSec
    );

    wire [7:0] outQ;
    wire inD0 = enable ^ outQ[0];
    wire inD1 = (enable & outQ[0]) ^ outQ[1];
    wire inD2 = (enable & outQ[0] & outQ[1]) ^ outQ[2];
    wire inD3 = (enable & outQ[0] & outQ[1] & outQ[2]) ^ outQ[3];
    wire inD4 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3]) ^ outQ[4];
    wire inD5 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4]) ^ outQ[5];
    wire inD6 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5]) ^ outQ[6];
    wire inD7 = (enable & outQ[0] & outQ[1] & outQ[2] & outQ[3] & outQ[4] & outQ[5] & outQ[6]) ^ outQ[7];

    FDRE #(.INIT(1'b0) ) bit1 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD0), .Q(outQ[0]));
    FDRE #(.INIT(1'b0) ) bit2 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD1), .Q(outQ[1]));
    FDRE #(.INIT(1'b0) ) bit3 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD2), .Q(outQ[2]));
    FDRE #(.INIT(1'b0) ) bit4 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD3), .Q(outQ[3]));
    FDRE #(.INIT(1'b0) ) bit5 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD4), .Q(outQ[4]));
    FDRE #(.INIT(1'b0) ) bit6 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD5), .Q(outQ[5]));
    FDRE #(.INIT(1'b0) ) bit7 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD6), .Q(outQ[6]));
    FDRE #(.INIT(1'b0) ) bit8 (.C(clk), .R(reset), .CE(enable & ~TC), .D(inD7), .Q(outQ[7]));

    assign twoSec = ( ~outQ[0] & ~outQ[1] & ~outQ[2] & ~outQ[3] & ~outQ[4] & ~outQ[5] & ~outQ[6] & outQ[7] );   
    
endmodule