data/full_repos/permissive/209997170/2. blinker/work/planAhead/blinker/blinker.srcs/sources_1/imports/verilog/blinker_2.v
 line:15: before: "="
1: b'%Error: Cannot find file containing module: blinker/work/planAhead/blinker/blinker.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170\n        ... Looked in:\n             data/full_repos/permissive/209997170/2./blinker/work/planAhead/blinker/blinker.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170\n             data/full_repos/permissive/209997170/2./blinker/work/planAhead/blinker/blinker.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170.v\n             data/full_repos/permissive/209997170/2./blinker/work/planAhead/blinker/blinker.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170.sv\n             blinker/work/planAhead/blinker/blinker.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170\n             blinker/work/planAhead/blinker/blinker.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170.v\n             blinker/work/planAhead/blinker/blinker.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170.sv\n             obj_dir/blinker/work/planAhead/blinker/blinker.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170\n             obj_dir/blinker/work/planAhead/blinker/blinker.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170.v\n             obj_dir/blinker/work/planAhead/blinker/blinker.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/209997170/2.\n%Error: Cannot find file containing module: blinker/work/planAhead/blinker/blinker.srcs/sources_1/imports/verilog/blinker_2.v\n%Error: Exiting due to 3 error(s)\n'
module blinker_2 (
    input clk,
    input rst,
    output reg blink
  );
  
  
  
  reg [26:0] M_counter_d, M_counter_q = 1'h0;
  
  always @* begin
    M_counter_d = M_counter_q;
    
    blink = M_counter_q[25+0-:1];
    M_counter_d = M_counter_q + 1'h1;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_counter_q <= 1'h0;
    end else begin
      M_counter_q <= M_counter_d;
    end
  end
  
endmodule
module blinker_2 (
    input clk,
    input rst,
    output reg blink
  );

  
  
  
  reg [26:0] M_counter_d, M_counter_q = 1'h0;
  
  always @* begin
    M_counter_d = M_counter_q;
    
    blink = M_counter_q[25+0-:1];
    M_counter_d = M_counter_q + 1'h1;
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_counter_q <= 1'h0;
    end else begin
      M_counter_q <= M_counter_d;
    end
  end
  
endmodule