data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v
1: b'%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:52: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:60: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n output [`E203_ITAG_WIDTH-1:0] dis_ptr,\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:61: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n output [`E203_ITAG_WIDTH-1:0] ret_ptr,\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:63: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n output [`E203_RFIDX_WIDTH-1:0] ret_rdidx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:66: Define or directive not defined: \'`E203_PC_SIZE\'\n output [`E203_PC_SIZE-1:0] ret_pc,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:76: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n input  [`E203_RFIDX_WIDTH-1:0] disp_i_rs1idx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:77: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n input  [`E203_RFIDX_WIDTH-1:0] disp_i_rs2idx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:78: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n input  [`E203_RFIDX_WIDTH-1:0] disp_i_rs3idx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:79: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n input  [`E203_RFIDX_WIDTH-1:0] disp_i_rdidx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:80: Define or directive not defined: \'`E203_PC_SIZE\'\n input  [`E203_PC_SIZE    -1:0] disp_i_pc,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:92: Define or directive not defined: \'`E203_OITF_DEPTH\'\n wire [`E203_OITF_DEPTH-1:0] vld_set;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:93: Define or directive not defined: \'`E203_OITF_DEPTH\'\n wire [`E203_OITF_DEPTH-1:0] vld_clr;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:94: Define or directive not defined: \'`E203_OITF_DEPTH\'\n wire [`E203_OITF_DEPTH-1:0] vld_ena;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:95: Define or directive not defined: \'`E203_OITF_DEPTH\'\n wire [`E203_OITF_DEPTH-1:0] vld_nxt;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:96: Define or directive not defined: \'`E203_OITF_DEPTH\'\n wire [`E203_OITF_DEPTH-1:0] vld_r;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:97: Define or directive not defined: \'`E203_OITF_DEPTH\'\n wire [`E203_OITF_DEPTH-1:0] rdwen_r;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:99: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n wire [`E203_RFIDX_WIDTH-1:0] rdidx_r[`E203_OITF_DEPTH-1:0];\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:99: Define or directive not defined: \'`E203_OITF_DEPTH\'\n wire [`E203_RFIDX_WIDTH-1:0] rdidx_r[`E203_OITF_DEPTH-1:0];\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:102: Define or directive not defined: \'`E203_PC_SIZE\'\n wire [`E203_PC_SIZE-1:0] pc_r[`E203_OITF_DEPTH-1:0];\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:102: Define or directive not defined: \'`E203_OITF_DEPTH\'\n wire [`E203_PC_SIZE-1:0] pc_r[`E203_OITF_DEPTH-1:0];\n                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:109: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n wire [`E203_ITAG_WIDTH-1:0] alc_ptr_r;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:110: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n wire [`E203_ITAG_WIDTH-1:0] ret_ptr_r;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:113: Define or directive not defined: \'`E203_OITF_DEPTH\'\n if(`E203_OITF_DEPTH > 1) begin: depth_gt1 \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:113: syntax error, unexpected \'>\', expecting TYPE-IDENTIFIER\n if(`E203_OITF_DEPTH > 1) begin: depth_gt1 \n                     ^\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:116: Define or directive not defined: \'`E203_OITF_DEPTH\'\n   wire alc_ptr_flg_ena = (alc_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & alc_ptr_ena;\n                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:120: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n   wire [`E203_ITAG_WIDTH-1:0] alc_ptr_nxt; \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:122: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n   assign alc_ptr_nxt = alc_ptr_flg_ena ? `E203_ITAG_WIDTH\'b0 : (alc_ptr_r + 1\'b1);\n                                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:124: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n   sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) alc_ptr_dfflrs(alc_ptr_ena, alc_ptr_nxt, alc_ptr_r, clk, rst_n);\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:129: Define or directive not defined: \'`E203_OITF_DEPTH\'\n   wire ret_ptr_flg_ena = (ret_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & ret_ptr_ena;\n                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:133: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n   wire [`E203_ITAG_WIDTH-1:0] ret_ptr_nxt; \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:135: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n   assign ret_ptr_nxt = ret_ptr_flg_ena ? `E203_ITAG_WIDTH\'b0 : (ret_ptr_r + 1\'b1);\n                                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:137: Define or directive not defined: \'`E203_ITAG_WIDTH\'\n   sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) ret_ptr_dfflrs(ret_ptr_ena, ret_ptr_nxt, ret_ptr_r, clk, rst_n);\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:141: syntax error, unexpected end\n end \n ^~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:147: syntax error, unexpected end\n end \n ^~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:160: Define or directive not defined: \'`E203_OITF_DEPTH\'\n wire [`E203_OITF_DEPTH-1:0] rd_match_rs1idx;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:161: Define or directive not defined: \'`E203_OITF_DEPTH\'\n wire [`E203_OITF_DEPTH-1:0] rd_match_rs2idx;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:162: Define or directive not defined: \'`E203_OITF_DEPTH\'\n wire [`E203_OITF_DEPTH-1:0] rd_match_rs3idx;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:163: Define or directive not defined: \'`E203_OITF_DEPTH\'\n wire [`E203_OITF_DEPTH-1:0] rd_match_rdidx;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:166: syntax error, unexpected generate\n generate  \n ^~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:167: Define or directive not defined: \'`E203_OITF_DEPTH\'\n   for (i=0; i<`E203_OITF_DEPTH; i=i+1) begin:oitf_entries \n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:176: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n    sirv_gnrl_dffl #(`E203_RFIDX_WIDTH) rdidx_dfflrs(vld_set[i], disp_i_rdidx, rdidx_r[i], clk);\n                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:177: Define or directive not defined: \'`E203_PC_SIZE\'\n    sirv_gnrl_dffl #(`E203_PC_SIZE    ) pc_dfflrs   (vld_set[i], disp_i_pc   , pc_r[i]   , clk);\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:186: syntax error, unexpected end\n   end \n   ^~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_exu_oitf.v:199: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module e203_exu_oitf (
	output dis_ready,

	input  dis_ena,
	input  ret_ena,

	output [`E203_ITAG_WIDTH-1:0] dis_ptr,
	output [`E203_ITAG_WIDTH-1:0] ret_ptr,

	output [`E203_RFIDX_WIDTH-1:0] ret_rdidx,
	output ret_rdwen,

	output [`E203_PC_SIZE-1:0] ret_pc,

	input  disp_i_rs1en,
	input  disp_i_rs2en,
	input  disp_i_rs3en,
	input  disp_i_rdwen,




	input  [`E203_RFIDX_WIDTH-1:0] disp_i_rs1idx,
	input  [`E203_RFIDX_WIDTH-1:0] disp_i_rs2idx,
	input  [`E203_RFIDX_WIDTH-1:0] disp_i_rs3idx,
	input  [`E203_RFIDX_WIDTH-1:0] disp_i_rdidx,
	input  [`E203_PC_SIZE    -1:0] disp_i_pc,

	output oitfrd_match_disprs1,
	output oitfrd_match_disprs2,
	output oitfrd_match_disprs3,
	output oitfrd_match_disprd,

	output oitf_empty,
	input  clk,
	input  rst_n
);

	wire [`E203_OITF_DEPTH-1:0] vld_set;
	wire [`E203_OITF_DEPTH-1:0] vld_clr;
	wire [`E203_OITF_DEPTH-1:0] vld_ena;
	wire [`E203_OITF_DEPTH-1:0] vld_nxt;
	wire [`E203_OITF_DEPTH-1:0] vld_r;
	wire [`E203_OITF_DEPTH-1:0] rdwen_r;

	wire [`E203_RFIDX_WIDTH-1:0] rdidx_r[`E203_OITF_DEPTH-1:0];


	wire [`E203_PC_SIZE-1:0] pc_r[`E203_OITF_DEPTH-1:0];

	wire alc_ptr_ena = dis_ena;
	wire ret_ptr_ena = ret_ena;

	wire oitf_full ;
	
	wire [`E203_ITAG_WIDTH-1:0] alc_ptr_r;
	wire [`E203_ITAG_WIDTH-1:0] ret_ptr_r;

	generate
	if(`E203_OITF_DEPTH > 1) begin: depth_gt1
			wire alc_ptr_flg_r;
			wire alc_ptr_flg_nxt = ~alc_ptr_flg_r;
			wire alc_ptr_flg_ena = (alc_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & alc_ptr_ena;
			
			sirv_gnrl_dfflr #(1) alc_ptr_flg_dfflrs(alc_ptr_flg_ena, alc_ptr_flg_nxt, alc_ptr_flg_r, clk, rst_n);
			
			wire [`E203_ITAG_WIDTH-1:0] alc_ptr_nxt; 
			
			assign alc_ptr_nxt = alc_ptr_flg_ena ? `E203_ITAG_WIDTH'b0 : (alc_ptr_r + 1'b1);
			
			sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) alc_ptr_dfflrs(alc_ptr_ena, alc_ptr_nxt, alc_ptr_r, clk, rst_n);
			
			
			wire ret_ptr_flg_r;
			wire ret_ptr_flg_nxt = ~ret_ptr_flg_r;
			wire ret_ptr_flg_ena = (ret_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & ret_ptr_ena;
			
			sirv_gnrl_dfflr #(1) ret_ptr_flg_dfflrs(ret_ptr_flg_ena, ret_ptr_flg_nxt, ret_ptr_flg_r, clk, rst_n);
			
			wire [`E203_ITAG_WIDTH-1:0] ret_ptr_nxt; 
			
			assign ret_ptr_nxt = ret_ptr_flg_ena ? `E203_ITAG_WIDTH'b0 : (ret_ptr_r + 1'b1);

			sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) ret_ptr_dfflrs(ret_ptr_ena, ret_ptr_nxt, ret_ptr_r, clk, rst_n);

			assign oitf_empty = (ret_ptr_r == alc_ptr_r) &   (ret_ptr_flg_r == alc_ptr_flg_r);
			assign oitf_full  = (ret_ptr_r == alc_ptr_r) & (~(ret_ptr_flg_r == alc_ptr_flg_r));
	end
	else begin: depth_eq1
			assign alc_ptr_r =1'b0;
			assign ret_ptr_r =1'b0;
			assign oitf_empty = ~vld_r[0];
			assign oitf_full  = vld_r[0];
	end
	endgenerate

	assign ret_ptr = ret_ptr_r;
	assign dis_ptr = alc_ptr_r;






	assign dis_ready = (~oitf_full);
	
	wire [`E203_OITF_DEPTH-1:0] rd_match_rs1idx;
	wire [`E203_OITF_DEPTH-1:0] rd_match_rs2idx;
	wire [`E203_OITF_DEPTH-1:0] rd_match_rs3idx;
	wire [`E203_OITF_DEPTH-1:0] rd_match_rdidx;

	genvar i;
	generate
			for (i=0; i<`E203_OITF_DEPTH; i=i+1) begin:oitf_entries
	
				assign vld_set[i] = alc_ptr_ena & (alc_ptr_r == i);
				assign vld_clr[i] = ret_ptr_ena & (ret_ptr_r == i);
				assign vld_ena[i] = vld_set[i] |   vld_clr[i];
				assign vld_nxt[i] = vld_set[i] | (~vld_clr[i]);
	
				sirv_gnrl_dfflr #(1) vld_dfflrs(vld_ena[i], vld_nxt[i], vld_r[i], clk, rst_n);

				sirv_gnrl_dffl #(`E203_RFIDX_WIDTH) rdidx_dfflrs(vld_set[i], disp_i_rdidx, rdidx_r[i], clk);
				sirv_gnrl_dffl #(`E203_PC_SIZE    ) pc_dfflrs   (vld_set[i], disp_i_pc   , pc_r[i]   , clk);
				sirv_gnrl_dffl #(1)                 rdwen_dfflrs(vld_set[i], disp_i_rdwen, rdwen_r[i], clk);


				assign rd_match_rs1idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs1en & (rdidx_r[i] == disp_i_rs1idx);
				assign rd_match_rs2idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs2en & (rdidx_r[i] == disp_i_rs2idx);
				assign rd_match_rs3idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs3en & (rdidx_r[i] == disp_i_rs3idx);
				assign rd_match_rdidx [i] = vld_r[i] & rdwen_r[i] & disp_i_rdwen & (rdidx_r[i] == disp_i_rdidx );
	
			end
	endgenerate

	assign oitfrd_match_disprs1 = |rd_match_rs1idx;
	assign oitfrd_match_disprs2 = |rd_match_rs2idx;
	assign oitfrd_match_disprs3 = |rd_match_rs3idx;
	assign oitfrd_match_disprd  = |rd_match_rdidx ;

	assign ret_rdidx = rdidx_r[ret_ptr];
	assign ret_pc    = pc_r [ret_ptr];
	assign ret_rdwen = rdwen_r[ret_ptr];


endmodule
module e203_exu_oitf (
	output dis_ready,

	input  dis_ena,
	input  ret_ena,

	output [`E203_ITAG_WIDTH-1:0] dis_ptr,
	output [`E203_ITAG_WIDTH-1:0] ret_ptr,

	output [`E203_RFIDX_WIDTH-1:0] ret_rdidx,
	output ret_rdwen,

	output [`E203_PC_SIZE-1:0] ret_pc,

	input  disp_i_rs1en,
	input  disp_i_rs2en,
	input  disp_i_rs3en,
	input  disp_i_rdwen,




	input  [`E203_RFIDX_WIDTH-1:0] disp_i_rs1idx,
	input  [`E203_RFIDX_WIDTH-1:0] disp_i_rs2idx,
	input  [`E203_RFIDX_WIDTH-1:0] disp_i_rs3idx,
	input  [`E203_RFIDX_WIDTH-1:0] disp_i_rdidx,
	input  [`E203_PC_SIZE    -1:0] disp_i_pc,

	output oitfrd_match_disprs1,
	output oitfrd_match_disprs2,
	output oitfrd_match_disprs3,
	output oitfrd_match_disprd,

	output oitf_empty,
	input  clk,
	input  rst_n
);


	wire [`E203_OITF_DEPTH-1:0] vld_set;
	wire [`E203_OITF_DEPTH-1:0] vld_clr;
	wire [`E203_OITF_DEPTH-1:0] vld_ena;
	wire [`E203_OITF_DEPTH-1:0] vld_nxt;
	wire [`E203_OITF_DEPTH-1:0] vld_r;
	wire [`E203_OITF_DEPTH-1:0] rdwen_r;

	wire [`E203_RFIDX_WIDTH-1:0] rdidx_r[`E203_OITF_DEPTH-1:0];


	wire [`E203_PC_SIZE-1:0] pc_r[`E203_OITF_DEPTH-1:0];

	wire alc_ptr_ena = dis_ena;
	wire ret_ptr_ena = ret_ena;

	wire oitf_full ;
	
	wire [`E203_ITAG_WIDTH-1:0] alc_ptr_r;
	wire [`E203_ITAG_WIDTH-1:0] ret_ptr_r;

	generate
	if(`E203_OITF_DEPTH > 1) begin: depth_gt1
			wire alc_ptr_flg_r;
			wire alc_ptr_flg_nxt = ~alc_ptr_flg_r;
			wire alc_ptr_flg_ena = (alc_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & alc_ptr_ena;
			
			sirv_gnrl_dfflr #(1) alc_ptr_flg_dfflrs(alc_ptr_flg_ena, alc_ptr_flg_nxt, alc_ptr_flg_r, clk, rst_n);
			
			wire [`E203_ITAG_WIDTH-1:0] alc_ptr_nxt; 
			
			assign alc_ptr_nxt = alc_ptr_flg_ena ? `E203_ITAG_WIDTH'b0 : (alc_ptr_r + 1'b1);
			
			sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) alc_ptr_dfflrs(alc_ptr_ena, alc_ptr_nxt, alc_ptr_r, clk, rst_n);
			
			
			wire ret_ptr_flg_r;
			wire ret_ptr_flg_nxt = ~ret_ptr_flg_r;
			wire ret_ptr_flg_ena = (ret_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & ret_ptr_ena;
			
			sirv_gnrl_dfflr #(1) ret_ptr_flg_dfflrs(ret_ptr_flg_ena, ret_ptr_flg_nxt, ret_ptr_flg_r, clk, rst_n);
			
			wire [`E203_ITAG_WIDTH-1:0] ret_ptr_nxt; 
			
			assign ret_ptr_nxt = ret_ptr_flg_ena ? `E203_ITAG_WIDTH'b0 : (ret_ptr_r + 1'b1);

			sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) ret_ptr_dfflrs(ret_ptr_ena, ret_ptr_nxt, ret_ptr_r, clk, rst_n);

			assign oitf_empty = (ret_ptr_r == alc_ptr_r) &   (ret_ptr_flg_r == alc_ptr_flg_r);
			assign oitf_full  = (ret_ptr_r == alc_ptr_r) & (~(ret_ptr_flg_r == alc_ptr_flg_r));
	end
	else begin: depth_eq1
			assign alc_ptr_r =1'b0;
			assign ret_ptr_r =1'b0;
			assign oitf_empty = ~vld_r[0];
			assign oitf_full  = vld_r[0];
	end
	endgenerate

	assign ret_ptr = ret_ptr_r;
	assign dis_ptr = alc_ptr_r;






	assign dis_ready = (~oitf_full);
	
	wire [`E203_OITF_DEPTH-1:0] rd_match_rs1idx;
	wire [`E203_OITF_DEPTH-1:0] rd_match_rs2idx;
	wire [`E203_OITF_DEPTH-1:0] rd_match_rs3idx;
	wire [`E203_OITF_DEPTH-1:0] rd_match_rdidx;

	genvar i;
	generate
			for (i=0; i<`E203_OITF_DEPTH; i=i+1) begin:oitf_entries
	
				assign vld_set[i] = alc_ptr_ena & (alc_ptr_r == i);
				assign vld_clr[i] = ret_ptr_ena & (ret_ptr_r == i);
				assign vld_ena[i] = vld_set[i] |   vld_clr[i];
				assign vld_nxt[i] = vld_set[i] | (~vld_clr[i]);
	
				sirv_gnrl_dfflr #(1) vld_dfflrs(vld_ena[i], vld_nxt[i], vld_r[i], clk, rst_n);

				sirv_gnrl_dffl #(`E203_RFIDX_WIDTH) rdidx_dfflrs(vld_set[i], disp_i_rdidx, rdidx_r[i], clk);
				sirv_gnrl_dffl #(`E203_PC_SIZE    ) pc_dfflrs   (vld_set[i], disp_i_pc   , pc_r[i]   , clk);
				sirv_gnrl_dffl #(1)                 rdwen_dfflrs(vld_set[i], disp_i_rdwen, rdwen_r[i], clk);


				assign rd_match_rs1idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs1en & (rdidx_r[i] == disp_i_rs1idx);
				assign rd_match_rs2idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs2en & (rdidx_r[i] == disp_i_rs2idx);
				assign rd_match_rs3idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs3en & (rdidx_r[i] == disp_i_rs3idx);
				assign rd_match_rdidx [i] = vld_r[i] & rdwen_r[i] & disp_i_rdwen & (rdidx_r[i] == disp_i_rdidx );
	
			end
	endgenerate

	assign oitfrd_match_disprs1 = |rd_match_rs1idx;
	assign oitfrd_match_disprs2 = |rd_match_rs2idx;
	assign oitfrd_match_disprs3 = |rd_match_rs3idx;
	assign oitfrd_match_disprd  = |rd_match_rdidx ;

	assign ret_rdidx = rdidx_r[ret_ptr];
	assign ret_pc    = pc_r [ret_ptr];
	assign ret_rdwen = rdwen_r[ret_ptr];


endmodule