data/full_repos/permissive/150266237/parte2.v
1: b'%Error: data/full_repos/permissive/150266237/parte2.v:119: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile ("out.vcd"); \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/150266237/parte2.v:120: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars; \n     ^~~~~~~~~\n%Error: data/full_repos/permissive/150266237/parte2.v:125: Unsupported or unknown PLI call: $monitor\n     $monitor($time," c %b res %b a %b s %d smem %d sporta %d",c,res,a,saida,saida1,saida2);\n     ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:126: Unsupported: Ignoring delay on this delayed statement.\n      #1 res=0; a=0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:127: Unsupported: Ignoring delay on this delayed statement.\n      #1 res=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:128: Unsupported: Ignoring delay on this delayed statement.\n      #8 a=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:129: Unsupported: Ignoring delay on this delayed statement.\n      #16 a=0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:130: Unsupported: Ignoring delay on this delayed statement.\n      #12 a=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/150266237/parte2.v:131: Unsupported: Ignoring delay on this delayed statement.\n      #4;\n      ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stateCase(clk, reset, a, saida);
input clk,reset,a;
    output [2:0] saida;
    reg [2:0] estado;

    parameter zero = 3'b010, dois = 3'b110, tres = 3'b100, quatro = 3'b000, cinco = 3'b001;

    assign saida =  (estado == zero) ? 3'd0 :
                    (estado == dois) ? 3'd2 :
                    (estado == tres) ? 3'd3 :
                    (estado == quatro) ? 3'd4 : 3'd5;

    always @(posedge clk or  negedge reset) 
    begin
        if(reset == 0) estado = zero;
        else 
            case (estado)
                zero : estado = tres;
                dois : estado = quatro;
                tres : estado = (a == 1) ? cinco : dois;
                quatro : estado = (a == 1) ? tres : zero;
                cinco : estado = dois;
            endcase
    end
endmodule
module stateCase(clk, reset, a, saida);

input clk,reset,a;
    output [2:0] saida;
    reg [2:0] estado;

    parameter zero = 3'b010, dois = 3'b110, tres = 3'b100, quatro = 3'b000, cinco = 3'b001;

    assign saida =  (estado == zero) ? 3'd0 :
                    (estado == dois) ? 3'd2 :
                    (estado == tres) ? 3'd3 :
                    (estado == quatro) ? 3'd4 : 3'd5;

    always @(posedge clk or  negedge reset) 
    begin
        if(reset == 0) estado = zero;
        else 
            case (estado)
                zero : estado = tres;
                dois : estado = quatro;
                tres : estado = (a == 1) ? cinco : dois;
                quatro : estado = (a == 1) ? tres : zero;
                cinco : estado = dois;
            endcase
    end
endmodule