data/full_repos/permissive/123364505/risc32_core.v
None: at end of input
1: b'%Error: data/full_repos/permissive/123364505/risc32_core.v:44: Cannot find include file: d:\\xilinx\\designs\\risc32\\opcodes.vh\n `include "d:\\xilinx\\designs\\risc32\\opcodes.vh" \n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123364505,data/full_repos/permissive/123364505/d:\\xilinx\\designs\\risc32\\opcodes.vh\n             data/full_repos/permissive/123364505,data/full_repos/permissive/123364505/d:\\xilinx\\designs\\risc32\\opcodes.vh.v\n             data/full_repos/permissive/123364505,data/full_repos/permissive/123364505/d:\\xilinx\\designs\\risc32\\opcodes.vh.sv\n             d:\\xilinx\\designs\\risc32\\opcodes.vh\n             d:\\xilinx\\designs\\risc32\\opcodes.vh.v\n             d:\\xilinx\\designs\\risc32\\opcodes.vh.sv\n             obj_dir/d:\\xilinx\\designs\\risc32\\opcodes.vh\n             obj_dir/d:\\xilinx\\designs\\risc32\\opcodes.vh.v\n             obj_dir/d:\\xilinx\\designs\\risc32\\opcodes.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module risc32_core(
		input wire clk, reset,
		input wire interrupt,
		output wire interrupt_ack,
		output wire [ 31 : 0 ] address,
		input wire [ 31 : 0 ] instruction,
		input wire [ 7 : 0 ] inport,
		output wire [ 31 : 0 ] outport,
		output reg halt
    );

	`include "d:\xilinx\designs\risc32\opcodes.vh"


	localparam WORD_SIZE		= 32;
	localparam GPR_COUNT 	= 32;
	localparam RAM_SIZE		= 10;
	localparam FLASH_SIZE	= 10;

	localparam TRUE			= 1'b1;
	localparam FALSE			= 1'b0;
	

	localparam state_fetch 		= 3'b000;
	localparam state_decode 	= 3'b001;
	localparam state_execute	= 3'b010;
	localparam state_mem			= 3'b011;
	localparam state_store 		= 3'b100;
	localparam state_wait		= 3'b101;
	localparam state_unused1 	= 3'b110;
	localparam state_unused2	= 3'b111;
	

	localparam MSR_INIT = 0;
	localparam RESET_VECTOR = 0;
	







	reg [ 2:0 ] current_state;
	reg [ 2:0 ] next_state;
	

	localparam C 	= 0;
	localparam DC 	= 1;
	localparam Z 	= 2;
	localparam PD	= 3;
	localparam TO	= 4;
	localparam RP0	= 5;
	localparam RP1	= 6;
	localparam IRP	= 7;
	





	reg [ WORD_SIZE - 1 : 0 ] MSR;
	

	reg [ WORD_SIZE - 1 : 0 ] IR;


	reg [ 5 : 0 ] OPCODE;
	

	reg [ 4 : 0 ] Rs, Rt, Rd;


	reg [ WORD_SIZE - 1 : 0 ] A;
	reg [ WORD_SIZE - 1 : 0 ] B;


	reg [ WORD_SIZE - 1 : 0 ] ALUOutput;
	

	reg [ 25 : 0 ] Addr;
	

	reg [ WORD_SIZE - 1 : 0 ] IMM;




	reg [ WORD_SIZE - 1 : 0 ] NPC;
	reg [ WORD_SIZE - 1 : 0 ] LMD;
	
	



	

	reg [ WORD_SIZE - 1 : 0 ] FLASH[ 2 ** FLASH_SIZE - 1 : 0 ];
	

	reg [ WORD_SIZE - 1 : 0 ] GPR[ GPR_COUNT - 1 : 0 ];
	

	reg [ WORD_SIZE - 1 : 0 ] SRAM [ 2 ** RAM_SIZE - 1 : 0 ];
	




	always @ (posedge clk, posedge reset)
	begin
		if (reset)
			begin

				current_state <= state_fetch;


				GPR[PC] 	= RESET_VECTOR;
				GPR[SP] 	= 0;
				GPR[LR]	= 0;
				GPR[0]	= 0;
				MSR 		<= MSR_INIT;

				halt 		<= FALSE;
			end
		else
			begin	
				



				case( current_state )
					



					state_fetch: 
					begin

						IR = instruction;

						

						NPC = GPR [ PC ] + 4;
						
						next_state = state_decode;
					end




					state_decode:
					begin








						OPCODE 	<= IR[ 31 : 26 ];
						Rs			<= IR[ 25 : 21 ];
						Rt			<= IR[ 20: 16 ];
						Rd	 		<= IR[ 15 : 11 ];
						A			<= GPR[ IR[ 25 : 21 ] ];
						B			<= GPR[ IR[ 20: 16 ] ];
						Addr		<= IR[ 25 : 0 ];
	

						IMM 		<= { {16{IR[15]}}, IR[ 15 : 0 ] };
						
						next_state = state_execute;
					end
					



					state_execute:
					begin
						case(OPCODE)
							OP_NOP:
							begin

							end
							
							OP_ADD:
							begin
								{MSR[C], ALUOutput} = A + B;
								MSR[Z] = ALUOutput == 0 ? TRUE : FALSE;
							end
							
							OP_SUB:
							begin
								{MSR[C], ALUOutput} = A - B;
								MSR[Z] = ALUOutput == 0 ? TRUE : FALSE;
							end

							OP_LD:
							begin

								ALUOutput = A + IMM;
							end
							
							OP_LDI:
							begin
								ALUOutput = IMM;
							end
							
							OP_ST:
							begin
								ALUOutput = Rd;
							end
							
							OP_GOTO:
							begin
								ALUOutput = NPC + (IMM << 2);
							end
							
							OP_CALL:
							begin
							end
							
							OP_RET:
							begin
							end
							
							default:
							begin
								halt <= TRUE;
							end
							
						endcase
						
						next_state = state_mem;
					end
					



					state_mem:
					begin

						GPR[PC] = NPC;

						case(OPCODE)
							OP_LD:
							begin
								LMD = SRAM[ALUOutput];
							end
							
							OP_ST:
							begin
								SRAM[ALUOutput] = B;
							end
							
							OP_GOTO:
							begin
								GPR[PC] = ALUOutput;
							end
							
						endcase

						next_state = state_store;
					end
					



					state_store:
					begin
						case(OPCODE)
							
							OP_MTSR:
							begin
								MSR = B;
							end
							
							OP_MFSR:
							begin
								GPR[Rt] = MSR;
							end
							
							OP_ADD,
							OP_SUB:
							begin
								GPR[Rd] = ALUOutput;
							end
							
							OP_LD:
							begin
								GPR[Rt] = LMD;
							end

							OP_LDI:
							begin
								GPR[Rt] = ALUOutput;
							end
							
						endcase
							
						next_state = state_fetch;
					end
					



					state_wait:
					begin
						next_state = state_fetch;
					end
					



					default: 
					begin 
						halt <= TRUE;
					end
				endcase


			current_state <= next_state;
			end
	end
	

	assign address = GPR[PC];
	assign outport = GPR[3];
	assign interrupt_ack = FALSE;
	
endmodule
module risc32_core(
		input wire clk, reset,
		input wire interrupt,
		output wire interrupt_ack,
		output wire [ 31 : 0 ] address,
		input wire [ 31 : 0 ] instruction,
		input wire [ 7 : 0 ] inport,
		output wire [ 31 : 0 ] outport,
		output reg halt
    );


	`include "d:\xilinx\designs\risc32\opcodes.vh"


	localparam WORD_SIZE		= 32;
	localparam GPR_COUNT 	= 32;
	localparam RAM_SIZE		= 10;
	localparam FLASH_SIZE	= 10;

	localparam TRUE			= 1'b1;
	localparam FALSE			= 1'b0;
	

	localparam state_fetch 		= 3'b000;
	localparam state_decode 	= 3'b001;
	localparam state_execute	= 3'b010;
	localparam state_mem			= 3'b011;
	localparam state_store 		= 3'b100;
	localparam state_wait		= 3'b101;
	localparam state_unused1 	= 3'b110;
	localparam state_unused2	= 3'b111;
	

	localparam MSR_INIT = 0;
	localparam RESET_VECTOR = 0;
	







	reg [ 2:0 ] current_state;
	reg [ 2:0 ] next_state;
	

	localparam C 	= 0;
	localparam DC 	= 1;
	localparam Z 	= 2;
	localparam PD	= 3;
	localparam TO	= 4;
	localparam RP0	= 5;
	localparam RP1	= 6;
	localparam IRP	= 7;
	





	reg [ WORD_SIZE - 1 : 0 ] MSR;
	

	reg [ WORD_SIZE - 1 : 0 ] IR;


	reg [ 5 : 0 ] OPCODE;
	

	reg [ 4 : 0 ] Rs, Rt, Rd;


	reg [ WORD_SIZE - 1 : 0 ] A;
	reg [ WORD_SIZE - 1 : 0 ] B;


	reg [ WORD_SIZE - 1 : 0 ] ALUOutput;
	

	reg [ 25 : 0 ] Addr;
	

	reg [ WORD_SIZE - 1 : 0 ] IMM;




	reg [ WORD_SIZE - 1 : 0 ] NPC;
	reg [ WORD_SIZE - 1 : 0 ] LMD;
	
	



	

	reg [ WORD_SIZE - 1 : 0 ] FLASH[ 2 ** FLASH_SIZE - 1 : 0 ];
	

	reg [ WORD_SIZE - 1 : 0 ] GPR[ GPR_COUNT - 1 : 0 ];
	

	reg [ WORD_SIZE - 1 : 0 ] SRAM [ 2 ** RAM_SIZE - 1 : 0 ];
	




	always @ (posedge clk, posedge reset)
	begin
		if (reset)
			begin

				current_state <= state_fetch;


				GPR[PC] 	= RESET_VECTOR;
				GPR[SP] 	= 0;
				GPR[LR]	= 0;
				GPR[0]	= 0;
				MSR 		<= MSR_INIT;

				halt 		<= FALSE;
			end
		else
			begin	
				



				case( current_state )
					



					state_fetch: 
					begin

						IR = instruction;

						

						NPC = GPR [ PC ] + 4;
						
						next_state = state_decode;
					end




					state_decode:
					begin








						OPCODE 	<= IR[ 31 : 26 ];
						Rs			<= IR[ 25 : 21 ];
						Rt			<= IR[ 20: 16 ];
						Rd	 		<= IR[ 15 : 11 ];
						A			<= GPR[ IR[ 25 : 21 ] ];
						B			<= GPR[ IR[ 20: 16 ] ];
						Addr		<= IR[ 25 : 0 ];
	

						IMM 		<= { {16{IR[15]}}, IR[ 15 : 0 ] };
						
						next_state = state_execute;
					end
					



					state_execute:
					begin
						case(OPCODE)
							OP_NOP:
							begin

							end
							
							OP_ADD:
							begin
								{MSR[C], ALUOutput} = A + B;
								MSR[Z] = ALUOutput == 0 ? TRUE : FALSE;
							end
							
							OP_SUB:
							begin
								{MSR[C], ALUOutput} = A - B;
								MSR[Z] = ALUOutput == 0 ? TRUE : FALSE;
							end

							OP_LD:
							begin

								ALUOutput = A + IMM;
							end
							
							OP_LDI:
							begin
								ALUOutput = IMM;
							end
							
							OP_ST:
							begin
								ALUOutput = Rd;
							end
							
							OP_GOTO:
							begin
								ALUOutput = NPC + (IMM << 2);
							end
							
							OP_CALL:
							begin
							end
							
							OP_RET:
							begin
							end
							
							default:
							begin
								halt <= TRUE;
							end
							
						endcase
						
						next_state = state_mem;
					end
					



					state_mem:
					begin

						GPR[PC] = NPC;

						case(OPCODE)
							OP_LD:
							begin
								LMD = SRAM[ALUOutput];
							end
							
							OP_ST:
							begin
								SRAM[ALUOutput] = B;
							end
							
							OP_GOTO:
							begin
								GPR[PC] = ALUOutput;
							end
							
						endcase

						next_state = state_store;
					end
					



					state_store:
					begin
						case(OPCODE)
							
							OP_MTSR:
							begin
								MSR = B;
							end
							
							OP_MFSR:
							begin
								GPR[Rt] = MSR;
							end
							
							OP_ADD,
							OP_SUB:
							begin
								GPR[Rd] = ALUOutput;
							end
							
							OP_LD:
							begin
								GPR[Rt] = LMD;
							end

							OP_LDI:
							begin
								GPR[Rt] = ALUOutput;
							end
							
						endcase
							
						next_state = state_fetch;
					end
					



					state_wait:
					begin
						next_state = state_fetch;
					end
					



					default: 
					begin 
						halt <= TRUE;
					end
				endcase


			current_state <= next_state;
			end
	end
	

	assign address = GPR[PC];
	assign outport = GPR[3];
	assign interrupt_ack = FALSE;
	
endmodule