data/full_repos/permissive/208113388/board_support_packages/ad9h7/verilog/cfg_reg_to_axi4lite.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/ad8f85cb-b6b9-40d9-8b1a-632c4e3f4eb9.xml
module cfg_reg_to_axi4lite (


    input          s_axi_aclk
  , input          s_axi_aresetn


  , input   [13:0] cfg_axi_addr
  , input          cfg_axi_wren
  , input   [31:0] cfg_axi_wdata
  , input          cfg_axi_rden
  , output  [31:0] axi_cfg_rdata
  , output         axi_cfg_done
  , output   [1:0] axi_cfg_bresp
  , output   [1:0] axi_cfg_rresp

  , input          data_expand_enable
  , input          data_expand_dir


  , output  [13:0] s_axi_awaddr  
  , output         s_axi_awvalid 
  , input          s_axi_awready  
  , output  [31:0] s_axi_wdata 
  , output   [3:0] s_axi_wstrb  
  , output         s_axi_wvalid  
  , input          s_axi_wready 
  , input    [1:0] s_axi_bresp 
  , input          s_axi_bvalid  
  , output         s_axi_bready  
  , output  [13:0] s_axi_araddr  
  , output         s_axi_arvalid  
  , input          s_axi_arready 
  , input   [31:0] s_axi_rdata  
  , input    [1:0] s_axi_rresp  
  , input          s_axi_rvalid 
  , output         s_axi_rready
);







wire rising_wren;
wire rising_rden;
reg  delay_wren_q;
reg  delay_rden_q;
always @(posedge(s_axi_aclk))
  begin
    delay_wren_q <= cfg_axi_wren;
    delay_rden_q <= cfg_axi_rden;
  end
assign rising_wren = cfg_axi_wren & ~delay_wren_q;
assign rising_rden = cfg_axi_rden & ~delay_rden_q;





reg  [7:0] expander_wdata;
reg  [1:0] expander_state_q;
reg        expander_wren_q;
reg        expander_rden_q;
wire       exp_done_wr;
wire       exp_done_rd;
reg        set_done_wr;
reg        set_done_rd;




always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0 || data_expand_enable == 1'b0)
    begin                                  
      expander_state_q <= 2'b00;                          
      expander_wren_q  <= 1'b0;
      expander_rden_q  <= 1'b0;
    end
  else if (rising_wren == 1'b1 || rising_rden == 1'b1)
    begin                                  
      expander_state_q <= 2'b00;
      expander_wren_q  <= 1'b0;
      expander_rden_q  <= 1'b0;
    end
  else if (set_done_wr == 1'b1 || set_done_rd == 1'b1)
    begin
      if (expander_state_q == 2'b11)
        begin
          expander_state_q <= 2'b00;
          expander_wren_q  <= 1'b0;
          expander_rden_q  <= 1'b0;
        end
      else
        begin
          expander_state_q <= expander_state_q + 2'b01;
          expander_wren_q  <= set_done_wr;
          expander_rden_q  <= set_done_rd;
        end
    end
  else
    begin
      expander_state_q <= expander_state_q;
      expander_wren_q  <= 1'b0;
      expander_rden_q  <= 1'b0;
    end



assign exp_done_wr = (expander_state_q == 2'b11 && set_done_wr == 1'b1) ? 1'b1 : 1'b0;
assign exp_done_rd = (expander_state_q == 2'b11 && set_done_rd == 1'b1) ? 1'b1 : 1'b0;


always @(*)
  if (data_expand_enable == 1'b1 && data_expand_dir == 1'b0)
    case (expander_state_q)
      2'b00: expander_wdata = cfg_axi_wdata[ 7: 0];
      2'b01: expander_wdata = cfg_axi_wdata[15: 8];
      2'b10: expander_wdata = cfg_axi_wdata[23:16];
      2'b11: expander_wdata = cfg_axi_wdata[31:24];
    endcase
  else if (data_expand_enable == 1'b1 && data_expand_dir == 1'b1)
    case (expander_state_q)
      2'b00: expander_wdata = cfg_axi_wdata[31:24];
      2'b01: expander_wdata = cfg_axi_wdata[23:16];
      2'b10: expander_wdata = cfg_axi_wdata[15: 8];
      2'b11: expander_wdata = cfg_axi_wdata[ 7: 0];
    endcase
  else
    expander_wdata = 8'h00;











assign s_axi_awaddr = cfg_axi_addr;
assign s_axi_araddr = cfg_axi_addr;
assign s_axi_wdata  = (data_expand_enable == 1'b0) ? cfg_axi_wdata : {24'b0, expander_wdata};
assign s_axi_wstrb  = (data_expand_enable == 1'b0) ? 4'b1111 : 4'b0001;






















reg  done_q;
always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0)
    done_q <= 1'b0;
  else if (rising_wren == 1'b1 || rising_rden == 1'b1)
    done_q <= 1'b0;
  else if ( (data_expand_enable == 1'b0
             && (set_done_wr == 1'b1 || set_done_rd == 1'b1) )
         || (data_expand_enable == 1'b1
             && (exp_done_wr == 1'b1 || exp_done_rd == 1'b1) )
          )
    done_q <= 1'b1;
  else if (done_q == 1'b1)
    done_q <= 1'b0;
  else
    done_q <= done_q;
assign axi_cfg_done = done_q;






reg  awvalid_q;
always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0)
    awvalid_q <= 1'b0;
  else if (rising_wren == 1'b1 || expander_wren_q == 1'b1)
    awvalid_q <= 1'b1;
  else if (awvalid_q == 1'b1 && s_axi_awready == 1'b1)
    awvalid_q <= 1'b0;
  else
    awvalid_q <= awvalid_q;
assign s_axi_awvalid = awvalid_q;



reg  wvalid_q;
always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0)
    wvalid_q <= 1'b0;
  else if (rising_wren == 1'b1 || expander_wren_q == 1'b1)
    wvalid_q <= 1'b1;
  else if (wvalid_q == 1'b1 && s_axi_wready == 1'b1)
    wvalid_q <= 1'b0;
  else
    wvalid_q <= wvalid_q;           
assign s_axi_wvalid = wvalid_q;



assign s_axi_bready = (s_axi_aresetn == 1'b0) ? 1'b0 : 1'b1;




reg  [1:0] bresp_q;
always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0)
    begin
      bresp_q     <= 2'b00;
      set_done_wr <= 1'b0;
    end
  else if (rising_wren == 1'b1)
    begin
      bresp_q     <= 2'b00; 
      set_done_wr <= 1'b0;                               
    end
  else if (s_axi_bvalid == 1'b1)
    begin
      bresp_q     <= bresp_q | s_axi_bresp;
      set_done_wr <= 1'b1;
    end
  else
    begin
      bresp_q     <= bresp_q;
      set_done_wr <= 1'b0;
    end
assign axi_cfg_bresp = bresp_q;






reg  arvalid_q;
always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0)
    arvalid_q <= 1'b0;
  else if (rising_rden == 1'b1 || expander_rden_q == 1'b1)
    arvalid_q <= 1'b1;
  else if (arvalid_q == 1'b1 && s_axi_arready == 1'b1)
    arvalid_q <= 1'b0;
  else
    arvalid_q <= arvalid_q;
assign s_axi_arvalid = arvalid_q;



assign s_axi_rready = (s_axi_aresetn == 1'b0) ? 1'b0 : 1'b1;



reg   [1:0] rresp_q;
reg  [31:0] rdata_q;
always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0)
    begin
      rresp_q     <= 2'b00;
      rdata_q     <= 32'h0000_0000;
      set_done_rd <= 1'b0;
    end
  else if (rising_rden == 1'b1)
    begin
      rresp_q     <= 2'b00; 
      rdata_q     <= 32'h0000_0000;
      set_done_rd <= 1'b0;                               
    end
  else if (s_axi_rvalid == 1'b1)
    begin
      rresp_q     <= rresp_q | s_axi_rresp;

      if (data_expand_enable == 1'b1 && data_expand_dir == 1'b0)
        case (expander_state_q)
          2'b00: rdata_q <= {rdata_q[31: 8], s_axi_rdata[7:0]                };     
          2'b01: rdata_q <= {rdata_q[31:16], s_axi_rdata[7:0], rdata_q[ 7:0] };
          2'b10: rdata_q <= {rdata_q[31:24], s_axi_rdata[7:0], rdata_q[15:0] };
          2'b11: rdata_q <= {                s_axi_rdata[7:0], rdata_q[23:0] };
        endcase
      else if (data_expand_enable == 1'b1 && data_expand_dir == 1'b1)
        case (expander_state_q)
          2'b00: rdata_q <= {                s_axi_rdata[7:0], rdata_q[23:0] };
          2'b01: rdata_q <= {rdata_q[31:24], s_axi_rdata[7:0], rdata_q[15:0] };
          2'b10: rdata_q <= {rdata_q[31:16], s_axi_rdata[7:0], rdata_q[ 7:0] };
          2'b11: rdata_q <= {rdata_q[31: 8], s_axi_rdata[7:0]                };     
        endcase
      else
        rdata_q <= s_axi_rdata;

      set_done_rd <= 1'b1;
    end
  else                                                   
    begin
      rresp_q     <= rresp_q;
      rdata_q     <= rdata_q;
      set_done_rd <= 1'b0;
    end
assign axi_cfg_rresp = rresp_q;
assign axi_cfg_rdata = rdata_q;


endmodule
module cfg_reg_to_axi4lite (


    input          s_axi_aclk
  , input          s_axi_aresetn


  , input   [13:0] cfg_axi_addr
  , input          cfg_axi_wren
  , input   [31:0] cfg_axi_wdata
  , input          cfg_axi_rden
  , output  [31:0] axi_cfg_rdata
  , output         axi_cfg_done
  , output   [1:0] axi_cfg_bresp
  , output   [1:0] axi_cfg_rresp

  , input          data_expand_enable
  , input          data_expand_dir


  , output  [13:0] s_axi_awaddr  
  , output         s_axi_awvalid 
  , input          s_axi_awready  
  , output  [31:0] s_axi_wdata 
  , output   [3:0] s_axi_wstrb  
  , output         s_axi_wvalid  
  , input          s_axi_wready 
  , input    [1:0] s_axi_bresp 
  , input          s_axi_bvalid  
  , output         s_axi_bready  
  , output  [13:0] s_axi_araddr  
  , output         s_axi_arvalid  
  , input          s_axi_arready 
  , input   [31:0] s_axi_rdata  
  , input    [1:0] s_axi_rresp  
  , input          s_axi_rvalid 
  , output         s_axi_rready
);








wire rising_wren;
wire rising_rden;
reg  delay_wren_q;
reg  delay_rden_q;
always @(posedge(s_axi_aclk))
  begin
    delay_wren_q <= cfg_axi_wren;
    delay_rden_q <= cfg_axi_rden;
  end
assign rising_wren = cfg_axi_wren & ~delay_wren_q;
assign rising_rden = cfg_axi_rden & ~delay_rden_q;





reg  [7:0] expander_wdata;
reg  [1:0] expander_state_q;
reg        expander_wren_q;
reg        expander_rden_q;
wire       exp_done_wr;
wire       exp_done_rd;
reg        set_done_wr;
reg        set_done_rd;




always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0 || data_expand_enable == 1'b0)
    begin                                  
      expander_state_q <= 2'b00;                          
      expander_wren_q  <= 1'b0;
      expander_rden_q  <= 1'b0;
    end
  else if (rising_wren == 1'b1 || rising_rden == 1'b1)
    begin                                  
      expander_state_q <= 2'b00;
      expander_wren_q  <= 1'b0;
      expander_rden_q  <= 1'b0;
    end
  else if (set_done_wr == 1'b1 || set_done_rd == 1'b1)
    begin
      if (expander_state_q == 2'b11)
        begin
          expander_state_q <= 2'b00;
          expander_wren_q  <= 1'b0;
          expander_rden_q  <= 1'b0;
        end
      else
        begin
          expander_state_q <= expander_state_q + 2'b01;
          expander_wren_q  <= set_done_wr;
          expander_rden_q  <= set_done_rd;
        end
    end
  else
    begin
      expander_state_q <= expander_state_q;
      expander_wren_q  <= 1'b0;
      expander_rden_q  <= 1'b0;
    end



assign exp_done_wr = (expander_state_q == 2'b11 && set_done_wr == 1'b1) ? 1'b1 : 1'b0;
assign exp_done_rd = (expander_state_q == 2'b11 && set_done_rd == 1'b1) ? 1'b1 : 1'b0;


always @(*)
  if (data_expand_enable == 1'b1 && data_expand_dir == 1'b0)
    case (expander_state_q)
      2'b00: expander_wdata = cfg_axi_wdata[ 7: 0];
      2'b01: expander_wdata = cfg_axi_wdata[15: 8];
      2'b10: expander_wdata = cfg_axi_wdata[23:16];
      2'b11: expander_wdata = cfg_axi_wdata[31:24];
    endcase
  else if (data_expand_enable == 1'b1 && data_expand_dir == 1'b1)
    case (expander_state_q)
      2'b00: expander_wdata = cfg_axi_wdata[31:24];
      2'b01: expander_wdata = cfg_axi_wdata[23:16];
      2'b10: expander_wdata = cfg_axi_wdata[15: 8];
      2'b11: expander_wdata = cfg_axi_wdata[ 7: 0];
    endcase
  else
    expander_wdata = 8'h00;











assign s_axi_awaddr = cfg_axi_addr;
assign s_axi_araddr = cfg_axi_addr;
assign s_axi_wdata  = (data_expand_enable == 1'b0) ? cfg_axi_wdata : {24'b0, expander_wdata};
assign s_axi_wstrb  = (data_expand_enable == 1'b0) ? 4'b1111 : 4'b0001;






















reg  done_q;
always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0)
    done_q <= 1'b0;
  else if (rising_wren == 1'b1 || rising_rden == 1'b1)
    done_q <= 1'b0;
  else if ( (data_expand_enable == 1'b0
             && (set_done_wr == 1'b1 || set_done_rd == 1'b1) )
         || (data_expand_enable == 1'b1
             && (exp_done_wr == 1'b1 || exp_done_rd == 1'b1) )
          )
    done_q <= 1'b1;
  else if (done_q == 1'b1)
    done_q <= 1'b0;
  else
    done_q <= done_q;
assign axi_cfg_done = done_q;






reg  awvalid_q;
always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0)
    awvalid_q <= 1'b0;
  else if (rising_wren == 1'b1 || expander_wren_q == 1'b1)
    awvalid_q <= 1'b1;
  else if (awvalid_q == 1'b1 && s_axi_awready == 1'b1)
    awvalid_q <= 1'b0;
  else
    awvalid_q <= awvalid_q;
assign s_axi_awvalid = awvalid_q;



reg  wvalid_q;
always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0)
    wvalid_q <= 1'b0;
  else if (rising_wren == 1'b1 || expander_wren_q == 1'b1)
    wvalid_q <= 1'b1;
  else if (wvalid_q == 1'b1 && s_axi_wready == 1'b1)
    wvalid_q <= 1'b0;
  else
    wvalid_q <= wvalid_q;           
assign s_axi_wvalid = wvalid_q;



assign s_axi_bready = (s_axi_aresetn == 1'b0) ? 1'b0 : 1'b1;




reg  [1:0] bresp_q;
always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0)
    begin
      bresp_q     <= 2'b00;
      set_done_wr <= 1'b0;
    end
  else if (rising_wren == 1'b1)
    begin
      bresp_q     <= 2'b00; 
      set_done_wr <= 1'b0;                               
    end
  else if (s_axi_bvalid == 1'b1)
    begin
      bresp_q     <= bresp_q | s_axi_bresp;
      set_done_wr <= 1'b1;
    end
  else
    begin
      bresp_q     <= bresp_q;
      set_done_wr <= 1'b0;
    end
assign axi_cfg_bresp = bresp_q;






reg  arvalid_q;
always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0)
    arvalid_q <= 1'b0;
  else if (rising_rden == 1'b1 || expander_rden_q == 1'b1)
    arvalid_q <= 1'b1;
  else if (arvalid_q == 1'b1 && s_axi_arready == 1'b1)
    arvalid_q <= 1'b0;
  else
    arvalid_q <= arvalid_q;
assign s_axi_arvalid = arvalid_q;



assign s_axi_rready = (s_axi_aresetn == 1'b0) ? 1'b0 : 1'b1;



reg   [1:0] rresp_q;
reg  [31:0] rdata_q;
always @(posedge(s_axi_aclk))
  if (s_axi_aresetn == 1'b0)
    begin
      rresp_q     <= 2'b00;
      rdata_q     <= 32'h0000_0000;
      set_done_rd <= 1'b0;
    end
  else if (rising_rden == 1'b1)
    begin
      rresp_q     <= 2'b00; 
      rdata_q     <= 32'h0000_0000;
      set_done_rd <= 1'b0;                               
    end
  else if (s_axi_rvalid == 1'b1)
    begin
      rresp_q     <= rresp_q | s_axi_rresp;

      if (data_expand_enable == 1'b1 && data_expand_dir == 1'b0)
        case (expander_state_q)
          2'b00: rdata_q <= {rdata_q[31: 8], s_axi_rdata[7:0]                };     
          2'b01: rdata_q <= {rdata_q[31:16], s_axi_rdata[7:0], rdata_q[ 7:0] };
          2'b10: rdata_q <= {rdata_q[31:24], s_axi_rdata[7:0], rdata_q[15:0] };
          2'b11: rdata_q <= {                s_axi_rdata[7:0], rdata_q[23:0] };
        endcase
      else if (data_expand_enable == 1'b1 && data_expand_dir == 1'b1)
        case (expander_state_q)
          2'b00: rdata_q <= {                s_axi_rdata[7:0], rdata_q[23:0] };
          2'b01: rdata_q <= {rdata_q[31:24], s_axi_rdata[7:0], rdata_q[15:0] };
          2'b10: rdata_q <= {rdata_q[31:16], s_axi_rdata[7:0], rdata_q[ 7:0] };
          2'b11: rdata_q <= {rdata_q[31: 8], s_axi_rdata[7:0]                };     
        endcase
      else
        rdata_q <= s_axi_rdata;

      set_done_rd <= 1'b1;
    end
  else                                                   
    begin
      rresp_q     <= rresp_q;
      rdata_q     <= rdata_q;
      set_done_rd <= 1'b0;
    end
assign axi_cfg_rresp = rresp_q;
assign axi_cfg_rdata = rdata_q;


endmodule