data/full_repos/permissive/106966316/sram.v
data/verilator_xmls/27e4b1b1-9159-4dfd-8f55-4110b3e95358.xml
module sram(clk,CSram,Direc,Datain,LeerMem,Dataout,EscrMem);
    input clk;
    input CSram;
    input [7:0] Direc;
    input [31:0] Datain;
    input LeerMem;
    output wire [31:0] Dataout;
    input EscrMem;
    
reg [31:0] RAM [0:255];

assign Dataout = LeerMem ? RAM[Direc]:32'b0;

always @ (posedge clk) 
begin

if(CSram==1'b1)
begin
    if (EscrMem==1'b1)
        begin
            RAM[Direc] = Datain;
        end  

end
end
endmodule
module sram(clk,CSram,Direc,Datain,LeerMem,Dataout,EscrMem);

    input clk;
    input CSram;
    input [7:0] Direc;
    input [31:0] Datain;
    input LeerMem;
    output wire [31:0] Dataout;
    input EscrMem;
    
reg [31:0] RAM [0:255];

assign Dataout = LeerMem ? RAM[Direc]:32'b0;

always @ (posedge clk) 
begin

if(CSram==1'b1)
begin
    if (EscrMem==1'b1)
        begin
            RAM[Direc] = Datain;
        end  

end
end
endmodule