data/full_repos/permissive/175122930/mem2serial_tb.v
1: b'%Error: data/full_repos/permissive/175122930/mem2serial_tb.v:25: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("mem2serial_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/175122930/mem2serial_tb.v:26: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars (1, mem2serial_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/175122930/mem2serial_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/175122930/mem2serial_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/mem2serial_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/mem2serial_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/mem2serial_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/mem2serial_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/mem2serial_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175122930/mem2serial_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mem2serial_tb ();
	reg reset;
	reg clock;
	reg empty;
	wire read_clock_enable;
	reg [47:0] read_data;
	wire uart_clock_enable;
	reg uart_ready;
	wire [7:0] uart_data;
	reg read_clock;

	mem2serial MEM_SERIAL(
		.reset(reset),
		.clock(clock),
		.read_empty(empty),
		.read_clock_enable(read_clock_enable),
		.read_data(read_data),
		.uart_clock_enable(uart_clock_enable),
		.uart_ready(uart_ready),
		.uart_data(uart_data));

	initial begin
		$dumpfile ("mem2serial_tb.vcd");
		$dumpvars (1, mem2serial_tb);
		#1;
		read_data = 48'h0;
		empty = 1;
		clock = 0;
		reset = 0;
		uart_ready = 0;
		#1;
		clock = 1;
		#1;
		clock = 0;
		#1;
		reset = 1;
		#1;
		clock = 1;
		#1;

		clock = 0;
		empty = 0;
		read_data = 48'h123456789a;
		uart_ready = 0;
		#1;
		clock = 1;
		#1;
		clock = 0;
		read_data = 48'h0;

		if (read_clock_enable == 'b1) begin
			$display("read_clock_enable still high. Expected: low");
			$stop;
		end




		$finish;
	end
endmodule
module mem2serial_tb ();

	reg reset;
	reg clock;
	reg empty;
	wire read_clock_enable;
	reg [47:0] read_data;
	wire uart_clock_enable;
	reg uart_ready;
	wire [7:0] uart_data;
	reg read_clock;

	mem2serial MEM_SERIAL(
		.reset(reset),
		.clock(clock),
		.read_empty(empty),
		.read_clock_enable(read_clock_enable),
		.read_data(read_data),
		.uart_clock_enable(uart_clock_enable),
		.uart_ready(uart_ready),
		.uart_data(uart_data));

	initial begin
		$dumpfile ("mem2serial_tb.vcd");
		$dumpvars (1, mem2serial_tb);
		#1;
		read_data = 48'h0;
		empty = 1;
		clock = 0;
		reset = 0;
		uart_ready = 0;
		#1;
		clock = 1;
		#1;
		clock = 0;
		#1;
		reset = 1;
		#1;
		clock = 1;
		#1;

		clock = 0;
		empty = 0;
		read_data = 48'h123456789a;
		uart_ready = 0;
		#1;
		clock = 1;
		#1;
		clock = 0;
		read_data = 48'h0;

		if (read_clock_enable == 'b1) begin
			$display("read_clock_enable still high. Expected: low");
			$stop;
		end




		$finish;
	end
endmodule