data/full_repos/permissive/114643454/src/regfile.v
 line:6: before: "]"
1: b"%Error: data/full_repos/permissive/114643454/src/regfile.v:6: Define or directive not defined: '`RegAddrBus'\n    input   wire[`RegAddrBus]   waddr,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:6: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n    input   wire[`RegAddrBus]   waddr,\n                            ^\n%Error: data/full_repos/permissive/114643454/src/regfile.v:7: Define or directive not defined: '`RegBus'\n    input   wire[`RegBus]       wdata,\n                 ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegAddrBus]   raddr1,\n    ^~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:10: Define or directive not defined: '`RegAddrBus'\n    input   wire[`RegAddrBus]   raddr1,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:11: Define or directive not defined: '`RegBus'\n    output  reg[`RegBus]        rdata1,\n                ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegAddrBus]   raddr2,\n    ^~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:14: Define or directive not defined: '`RegAddrBus'\n    input   wire[`RegAddrBus]   raddr2,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:15: Define or directive not defined: '`RegBus'\n    output  reg[`RegBus]        rdata2\n                ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:19: Define or directive not defined: '`RegBus'\nreg[`RegBus]    regs[0 : `RegNum - 1];\n    ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:19: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\nreg[`RegBus]    regs[0 : `RegNum - 1];\n           ^\n%Error: data/full_repos/permissive/114643454/src/regfile.v:19: Define or directive not defined: '`RegNum'\nreg[`RegBus]    regs[0 : `RegNum - 1];\n                         ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:23: syntax error, unexpected always\n    always @ ( posedge clk ) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:24: Define or directive not defined: '`RstDisable'\n        if (rst == `RstDisable) begin\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:25: Define or directive not defined: '`WriteEnable'\n            if ((we == `WriteEnable) && (waddr != `RegNumLog2'h0)) begin\n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:25: Define or directive not defined: '`RegNumLog2'\n            if ((we == `WriteEnable) && (waddr != `RegNumLog2'h0)) begin\n                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:35: Define or directive not defined: '`RstEnable'\n        if (rst == `RstEnable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:36: Define or directive not defined: '`ZeroWord'\n            rdata1 <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:37: Define or directive not defined: '`RegNumLog2'\n        end else if (raddr1 == `RegNumLog2'h0) begin\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:38: Define or directive not defined: '`ZeroWord'\n            rdata1 <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:39: Define or directive not defined: '`WriteEnable'\n        end else if ((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `REG_READ)) begin\n                                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:39: Define or directive not defined: '`REG_READ'\n        end else if ((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `REG_READ)) begin\n                                                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:41: Define or directive not defined: '`REG_READ'\n        end else if (re1 == `REG_READ) begin\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:44: Define or directive not defined: '`ZeroWord'\n            rdata1 <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:51: Define or directive not defined: '`RstEnable'\n        if (rst == `RstEnable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:52: Define or directive not defined: '`ZeroWord'\n            rdata2 <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:53: Define or directive not defined: '`RegNumLog2'\n        end else if (raddr2 == `RegNumLog2'h0) begin\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:54: Define or directive not defined: '`ZeroWord'\n            rdata2 <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:55: Define or directive not defined: '`WriteEnable'\n        end else if ((raddr2 == waddr) && (we == `WriteEnable) && (re2 == `REG_READ)) begin\n                                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:55: Define or directive not defined: '`REG_READ'\n        end else if ((raddr2 == waddr) && (we == `WriteEnable) && (re2 == `REG_READ)) begin\n                                                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:57: Define or directive not defined: '`REG_READ'\n        end else if (re2 == `REG_READ) begin\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/regfile.v:60: Define or directive not defined: '`ZeroWord'\n            rdata2 <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: Exiting due to 32 error(s)\n"
module regfile (
    input   wire                clk,
    input   wire                rst,

    input   wire                we,
    input   wire[`RegAddrBus]   waddr,
    input   wire[`RegBus]       wdata,

    input   wire[1 : 0]         re1,
    input   wire[`RegAddrBus]   raddr1,
    output  reg[`RegBus]        rdata1,

    input   wire[1 : 0]         re2,
    input   wire[`RegAddrBus]   raddr2,
    output  reg[`RegBus]        rdata2

);

reg[`RegBus]    regs[0 : `RegNum - 1];
integer i;


    always @ ( posedge clk ) begin
        if (rst == `RstDisable) begin
            if ((we == `WriteEnable) && (waddr != `RegNumLog2'h0)) begin
                regs[waddr] <= wdata;
                $display("regfile : regs[%d] <= %h", waddr, wdata);
            end
        end
    end



    always @ ( * ) begin
        if (rst == `RstEnable) begin
            rdata1 <= `ZeroWord;
        end else if (raddr1 == `RegNumLog2'h0) begin
            rdata1 <= `ZeroWord;
        end else if ((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `REG_READ)) begin
            rdata1 <= wdata;
        end else if (re1 == `REG_READ) begin
            rdata1 <= regs[raddr1];
        end else begin
            rdata1 <= `ZeroWord;
        end
    end



    always @ ( * ) begin
        if (rst == `RstEnable) begin
            rdata2 <= `ZeroWord;
        end else if (raddr2 == `RegNumLog2'h0) begin
            rdata2 <= `ZeroWord;
        end else if ((raddr2 == waddr) && (we == `WriteEnable) && (re2 == `REG_READ)) begin
            rdata2 <= wdata;
        end else if (re2 == `REG_READ) begin
            rdata2 <= regs[raddr2];
        end else begin
            rdata2 <= `ZeroWord;
        end
    end

endmodule
module regfile (
    input   wire                clk,
    input   wire                rst,

    input   wire                we,
    input   wire[`RegAddrBus]   waddr,
    input   wire[`RegBus]       wdata,

    input   wire[1 : 0]         re1,
    input   wire[`RegAddrBus]   raddr1,
    output  reg[`RegBus]        rdata1,

    input   wire[1 : 0]         re2,
    input   wire[`RegAddrBus]   raddr2,
    output  reg[`RegBus]        rdata2

);


reg[`RegBus]    regs[0 : `RegNum - 1];
integer i;


    always @ ( posedge clk ) begin
        if (rst == `RstDisable) begin
            if ((we == `WriteEnable) && (waddr != `RegNumLog2'h0)) begin
                regs[waddr] <= wdata;
                $display("regfile : regs[%d] <= %h", waddr, wdata);
            end
        end
    end



    always @ ( * ) begin
        if (rst == `RstEnable) begin
            rdata1 <= `ZeroWord;
        end else if (raddr1 == `RegNumLog2'h0) begin
            rdata1 <= `ZeroWord;
        end else if ((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `REG_READ)) begin
            rdata1 <= wdata;
        end else if (re1 == `REG_READ) begin
            rdata1 <= regs[raddr1];
        end else begin
            rdata1 <= `ZeroWord;
        end
    end



    always @ ( * ) begin
        if (rst == `RstEnable) begin
            rdata2 <= `ZeroWord;
        end else if (raddr2 == `RegNumLog2'h0) begin
            rdata2 <= `ZeroWord;
        end else if ((raddr2 == waddr) && (we == `WriteEnable) && (re2 == `REG_READ)) begin
            rdata2 <= wdata;
        end else if (re2 == `REG_READ) begin
            rdata2 <= regs[raddr2];
        end else begin
            rdata2 <= `ZeroWord;
        end
    end

endmodule