data/full_repos/permissive/147690299/lab/28_latch/rtl/inferred_latch.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/147690299/lab/28_latch/rtl/inferred_latch.v:28: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'case_inferred_latch\'\nmodule case_inferred_latch\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'mux_case_correct\'\nmodule mux_case_correct\n       ^~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'mod_latch\'\nmodule mod_latch\n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module case_inferred_latch
(
    input      [1:0] d0, d1, d2, 
    input      [1:0] sel,
    output reg [1:0] y
);


    always @(*)
        case (sel)
            2'b00: y = d0;
            2'b01: y = d1;
            2'b10: y = d2;
        endcase
endmodule
module case_inferred_latch
(
    input      [1:0] d0, d1, d2, 
    input      [1:0] sel,
    output reg [1:0] y
);



    always @(*)
        case (sel)
            2'b00: y = d0;
            2'b01: y = d1;
            2'b10: y = d2;
        endcase
endmodule