data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/InstructionRegister.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/InstructionRegister.v\n%Error: Exiting due to 4 error(s)\n'
module InstructionRegister(
    input [15:0] Instruction_In,
    input Clk,
	 input InstrWrite,
    output reg [15:0] Instruction_Out
    );

	
	
	always@(posedge Clk) begin
		if (InstrWrite)
			Instruction_Out <= Instruction_In;
	end
	
endmodule
module InstructionRegister(
    input [15:0] Instruction_In,
    input Clk,
	 input InstrWrite,
    output reg [15:0] Instruction_Out
    );


	
	
	always@(posedge Clk) begin
		if (InstrWrite)
			Instruction_Out <= Instruction_In;
	end
	
endmodule