data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v
1: b'%Error: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:23: Cannot find include file: encoder_pl.v\n`include "encoder_pl.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3,data/full_repos/permissive/20688874/encoder_pl.v\n             data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3,data/full_repos/permissive/20688874/encoder_pl.v.v\n             data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3,data/full_repos/permissive/20688874/encoder_pl.v.sv\n             encoder_pl.v\n             encoder_pl.v.v\n             encoder_pl.v.sv\n             obj_dir/encoder_pl.v\n             obj_dir/encoder_pl.v.v\n             obj_dir/encoder_pl.v.sv\n%Error: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:24: Cannot find include file: decoder_pl.v\n`include "decoder_pl.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:25: Cannot find include file: pipelinedec.v\n`include "pipelinedec.v" \n         ^~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:101: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk = 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:102: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:184: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:191: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:199: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:206: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:213: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:219: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:225: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:231: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:237: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:243: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/zhiyang_extra_credit_2/scripts/test_case_3/pipelinedectb.v:250: Unsupported: Ignoring delay on this delayed statement.\n  #300;\n  ^\n%Error: Exiting due to 3 error(s), 13 warning(s)\n'
module tb_pipeline();

	


	wire [18:0] c;

	wire [18:0] cx;

	wire [5:0] q;

	
	


	reg [5:0] b;
	reg [5:0] r_b;
	reg [18:0] e;
	reg [18:0] r_e;

	reg [18:0] r_c;
	reg [18:0] rr_e;
	reg [5:0] rr_b;




	reg [18:0] r_qx;
	reg [5:0] rb;
	
	reg clk,reset;
	reg [18:0] e2;
	
	
	
	encoder enc (


		r_b,c);
	
	decoder dec (


		r_qx,q);
	
	large_xor xr (


		r_c,rr_e,cx);
	
	
	
	

	always begin

    	#10 clk = 0;
    	#10 clk = 1;
    end		
	
	
	
	
	
	
	

	always@(posedge clk)
	begin
		if(reset)
		begin
			r_b<=0;
			r_e<=0;
		end
		else
		begin
			r_e<=e;
			r_b<=b;
		end
	end
	
	

	always@(posedge clk)
	begin
		if(reset)
		begin
			r_c<=0;
			rr_e<=0;
			rr_b<=0;
		end
		else
		begin
			r_c<=c;
			rr_e<=r_e;
			rr_b<=r_b;
		end
	end
	
	
	

	always@(posedge clk)
	begin
		if(reset)
		begin
			rb<=0;
		end
		else
		begin
			r_qx<=cx;
			rb<=rr_b;
			e2<=rr_e;
		end
	end
	

	

	initial
	begin

		$display(" << Starting the simulation >>");
		reset=1;
		#20;
		reset=0;
		b = $random;
		e = 18'b000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 18'b000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		

		#20;
		b = $random;
		e = 18'b000001000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		
		#20;
		b = $random;
		e = 18'b000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		
		#20;
		b = $random;
		e = 18'b000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 18'b000010000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 18'b000000000010000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 18'b000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 18'b001000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 18'b000000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
				
		#300;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_pipeline();


	


	wire [18:0] c;

	wire [18:0] cx;

	wire [5:0] q;

	
	


	reg [5:0] b;
	reg [5:0] r_b;
	reg [18:0] e;
	reg [18:0] r_e;

	reg [18:0] r_c;
	reg [18:0] rr_e;
	reg [5:0] rr_b;




	reg [18:0] r_qx;
	reg [5:0] rb;
	
	reg clk,reset;
	reg [18:0] e2;
	
	
	
	encoder enc (


		r_b,c);
	
	decoder dec (


		r_qx,q);
	
	large_xor xr (


		r_c,rr_e,cx);
	
	
	
	

	always begin

    	#10 clk = 0;
    	#10 clk = 1;
    end		
	
	
	
	
	
	
	

	always@(posedge clk)
	begin
		if(reset)
		begin
			r_b<=0;
			r_e<=0;
		end
		else
		begin
			r_e<=e;
			r_b<=b;
		end
	end
	
	

	always@(posedge clk)
	begin
		if(reset)
		begin
			r_c<=0;
			rr_e<=0;
			rr_b<=0;
		end
		else
		begin
			r_c<=c;
			rr_e<=r_e;
			rr_b<=r_b;
		end
	end
	
	
	

	always@(posedge clk)
	begin
		if(reset)
		begin
			rb<=0;
		end
		else
		begin
			r_qx<=cx;
			rb<=rr_b;
			e2<=rr_e;
		end
	end
	

	

	initial
	begin

		$display(" << Starting the simulation >>");
		reset=1;
		#20;
		reset=0;
		b = $random;
		e = 18'b000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 18'b000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		

		#20;
		b = $random;
		e = 18'b000001000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		
		#20;
		b = $random;
		e = 18'b000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		
		#20;
		b = $random;
		e = 18'b000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 18'b000010000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 18'b000000000010000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 18'b000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 18'b001000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
		#20;
		b = $random;
		e = 18'b000000000000000000000;
		$display(q, "<< Displaying q >>");
		$display(rb, "<< Displaying rb >>");
		
				
		#300;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule