data/full_repos/permissive/152271286/OTM17.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152271286/OTM17.v:87: Operator ADD expects 19 bits on the RHS, but RHS\'s CONST \'16\'h1\' generates 16 bits.\n                                                               : ... In instance BFI.c8\n opx=opx+16\'b1;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module BFI(output [32:0]result,
	inout [16:0]x,
	inout [16:0]y,
	input clk);

wire [18:0]xtmp;
assign xtmp[16:0]=x;
assign xtmp[17]=x[16];
assign xtmp[18]=x[16];
wire [18:0]prtmp[8:0];
wire [15:0]ytmp[8:0];
wire ctmp[8:0];
wire [34:0]restmp;

assign x=17'b0_0010_0111_0010_0111;
assign y=17'b0_0010_0111_0010_0111;

assign prtmp[0]=0;
assign ytmp[0]=y[15:0];
assign ctmp[0]=0;


cho c1(prtmp[1],ytmp[1],ctmp[1],ctmp[0],prtmp[0],xtmp,ytmp[0],clk);
cho c2(prtmp[2],ytmp[2],ctmp[2],ctmp[1],prtmp[1],xtmp,ytmp[1],clk);
cho c3(prtmp[3],ytmp[3],ctmp[3],ctmp[2],prtmp[2],xtmp,ytmp[2],clk);
cho c4(prtmp[4],ytmp[4],ctmp[4],ctmp[3],prtmp[3],xtmp,ytmp[3],clk);
cho c5(prtmp[5],ytmp[5],ctmp[5],ctmp[4],prtmp[4],xtmp,ytmp[4],clk);
cho c6(prtmp[6],ytmp[6],ctmp[6],ctmp[5],prtmp[5],xtmp,ytmp[5],clk);
cho c7(prtmp[7],ytmp[7],ctmp[7],ctmp[6],prtmp[6],xtmp,ytmp[6],clk);
cho c8(prtmp[8],ytmp[8],ctmp[8],ctmp[7],prtmp[7],xtmp,ytmp[7],clk);

resch rc(result,ytmp[8],prtmp[8],ctmp[8],clk);

endmodule
module BFI(output [32:0]result,
	inout [16:0]x,
	inout [16:0]y,
	input clk);


wire [18:0]xtmp;
assign xtmp[16:0]=x;
assign xtmp[17]=x[16];
assign xtmp[18]=x[16];
wire [18:0]prtmp[8:0];
wire [15:0]ytmp[8:0];
wire ctmp[8:0];
wire [34:0]restmp;

assign x=17'b0_0010_0111_0010_0111;
assign y=17'b0_0010_0111_0010_0111;

assign prtmp[0]=0;
assign ytmp[0]=y[15:0];
assign ctmp[0]=0;


cho c1(prtmp[1],ytmp[1],ctmp[1],ctmp[0],prtmp[0],xtmp,ytmp[0],clk);
cho c2(prtmp[2],ytmp[2],ctmp[2],ctmp[1],prtmp[1],xtmp,ytmp[1],clk);
cho c3(prtmp[3],ytmp[3],ctmp[3],ctmp[2],prtmp[2],xtmp,ytmp[2],clk);
cho c4(prtmp[4],ytmp[4],ctmp[4],ctmp[3],prtmp[3],xtmp,ytmp[3],clk);
cho c5(prtmp[5],ytmp[5],ctmp[5],ctmp[4],prtmp[4],xtmp,ytmp[4],clk);
cho c6(prtmp[6],ytmp[6],ctmp[6],ctmp[5],prtmp[5],xtmp,ytmp[5],clk);
cho c7(prtmp[7],ytmp[7],ctmp[7],ctmp[6],prtmp[6],xtmp,ytmp[6],clk);
cho c8(prtmp[8],ytmp[8],ctmp[8],ctmp[7],prtmp[7],xtmp,ytmp[7],clk);

resch rc(result,ytmp[8],prtmp[8],ctmp[8],clk);

endmodule