data/full_repos/permissive/189158922/verilog_src/normalize.v
 line:106: before: "*"
1: b'%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:115: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$15  = val_in + (* src = "normalize.py:72" *) 2\'h3;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:118: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$20  = val_in + (* src = "normalize.py:67" *) 3\'h7;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:119: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$23  = val_in + (* src = "normalize.py:72" *) 4\'hf;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:122: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'5\'h1f\' generates 5 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$30  = val_in + (* src = "normalize.py:67" *) 5\'h1f;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:123: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'6\'h3f\' generates 6 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$33  = val_in + (* src = "normalize.py:72" *) 6\'h3f;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:125: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'7\'h7f\' generates 7 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$38  = val_in + (* src = "normalize.py:67" *) 7\'h7f;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:127: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$41  = val_in + (* src = "normalize.py:72" *) 8\'hff;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:131: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'9\'h1ff\' generates 9 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$50  = val_in + (* src = "normalize.py:67" *) 9\'h1ff;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:132: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$53  = val_in + (* src = "normalize.py:72" *) 10\'h3ff;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:134: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'11\'h7ff\' generates 11 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$58  = val_in + (* src = "normalize.py:67" *) 11\'h7ff;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:136: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'12\'hfff\' generates 12 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$61  = val_in + (* src = "normalize.py:72" *) 12\'hfff;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:139: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'13\'h1fff\' generates 13 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$68  = val_in + (* src = "normalize.py:67" *) 13\'h1fff;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:140: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$71  = val_in + (* src = "normalize.py:72" *) 14\'h3fff;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:142: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'15\'h7fff\' generates 15 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$76  = val_in + (* src = "normalize.py:67" *) 15\'h7fff;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/normalize.v:144: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'16\'hffff\' generates 16 bits.\n                                                                                : ... In instance top.__0246\n  assign \\$79  = val_in + (* src = "normalize.py:72" *) 16\'hffff;\n                        ^\n%Error: Exiting due to 15 warning(s)\n'
module top(valid_in, end_in, vals_in_mns, rst, clk, val_out, valid_out, ssss, end_out, val_in);
  (* src = "normalize.py:132" *)
  reg \$next\end_in$2 ;
  (* src = "normalize.py:208" *)
  reg \$next\end_out ;
  (* src = "normalize.py:201" *)
  reg [4:0] \$next\ssss ;
  (* src = "normalize.py:119" *)
  reg [16:0] \$next\val_in$1 ;
  (* src = "normalize.py:121" *)
  reg [16:0] \$next\val_in_mns ;
  (* src = "normalize.py:199" *)
  reg [15:0] \$next\val_out ;
  (* src = "normalize.py:128" *)
  reg \$next\valid ;
  (* src = "normalize.py:204" *)
  reg \$next\valid_out ;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* src = "normalize.py:207" *)
  input end_in;
  (* src = "normalize.py:132" *)
  wire \end_in$2 ;
  (* src = "normalize.py:208" *)
  output end_out;
  (* src = "normalize.py:133" *)
  wire \end_out$5 ;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "normalize.py:201" *)
  output [4:0] ssss;
  (* src = "normalize.py:126" *)
  wire [4:0] \ssss$4 ;
  (* src = "normalize.py:194" *)
  input [16:0] val_in;
  (* src = "normalize.py:119" *)
  wire [16:0] \val_in$1 ;
  (* src = "normalize.py:121" *)
  wire [16:0] val_in_mns;
  (* src = "normalize.py:199" *)
  output [15:0] val_out;
  (* src = "normalize.py:124" *)
  wire [15:0] \val_out$3 ;
  (* src = "normalize.py:128" *)
  wire valid;
  (* src = "normalize.py:203" *)
  input valid_in;
  (* src = "normalize.py:129" *)
  wire valid_o;
  (* src = "normalize.py:204" *)
  output valid_out;
  (* src = "normalize.py:196" *)
  input [16:0] vals_in_mns;
  anonymous \$6  (
    .clk(clk),
    .end_in(\end_in$2 ),
    .end_out(\end_out$5 ),
    .rst(rst),
    .ssss(\ssss$4 ),
    .val_in(\val_in$1 ),
    .val_in_mns(val_in_mns),
    .val_out(\val_out$3 ),
    .valid(valid),
    .valid_o(valid_o)
  );
  always @* begin
    \$next\val_in$1  = 17'h00000;
    \$next\val_in$1  = val_in;
  end
  always @* begin
    \$next\valid  = 1'h0;
    \$next\valid  = valid_in;
  end
  always @* begin
    \$next\end_in$2  = 1'h0;
    \$next\end_in$2  = end_in;
  end
  always @* begin
    \$next\val_in_mns  = 17'h00000;
    \$next\val_in_mns  = vals_in_mns;
  end
  always @* begin
    \$next\ssss  = 5'h00;
    \$next\ssss  = \ssss$4 ;
  end
  always @* begin
    \$next\val_out  = 16'h0000;
    \$next\val_out  = \val_out$3 ;
  end
  always @* begin
    \$next\valid_out  = 1'h0;
    \$next\valid_out  = valid_o;
  end
  always @* begin
    \$next\end_out  = 1'h0;
    \$next\end_out  = \end_out$5 ;
  end
  assign end_out = \$next\end_out ;
  assign valid_out = \$next\valid_out ;
  assign val_out = \$next\val_out ;
  assign ssss = \$next\ssss ;
  assign val_in_mns = \$next\val_in_mns ;
  assign \end_in$2  = \$next\end_in$2 ;
  assign valid = \$next\valid ;
  assign \val_in$1  = \$next\val_in$1 ;
endmodule
module top(valid_in, end_in, vals_in_mns, rst, clk, val_out, valid_out, ssss, end_out, val_in);

  (* src = "normalize.py:132" *)
  reg \$next\end_in$2 ;
  (* src = "normalize.py:208" *)
  reg \$next\end_out ;
  (* src = "normalize.py:201" *)
  reg [4:0] \$next\ssss ;
  (* src = "normalize.py:119" *)
  reg [16:0] \$next\val_in$1 ;
  (* src = "normalize.py:121" *)
  reg [16:0] \$next\val_in_mns ;
  (* src = "normalize.py:199" *)
  reg [15:0] \$next\val_out ;
  (* src = "normalize.py:128" *)
  reg \$next\valid ;
  (* src = "normalize.py:204" *)
  reg \$next\valid_out ;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* src = "normalize.py:207" *)
  input end_in;
  (* src = "normalize.py:132" *)
  wire \end_in$2 ;
  (* src = "normalize.py:208" *)
  output end_out;
  (* src = "normalize.py:133" *)
  wire \end_out$5 ;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "normalize.py:201" *)
  output [4:0] ssss;
  (* src = "normalize.py:126" *)
  wire [4:0] \ssss$4 ;
  (* src = "normalize.py:194" *)
  input [16:0] val_in;
  (* src = "normalize.py:119" *)
  wire [16:0] \val_in$1 ;
  (* src = "normalize.py:121" *)
  wire [16:0] val_in_mns;
  (* src = "normalize.py:199" *)
  output [15:0] val_out;
  (* src = "normalize.py:124" *)
  wire [15:0] \val_out$3 ;
  (* src = "normalize.py:128" *)
  wire valid;
  (* src = "normalize.py:203" *)
  input valid_in;
  (* src = "normalize.py:129" *)
  wire valid_o;
  (* src = "normalize.py:204" *)
  output valid_out;
  (* src = "normalize.py:196" *)
  input [16:0] vals_in_mns;
  anonymous \$6  (
    .clk(clk),
    .end_in(\end_in$2 ),
    .end_out(\end_out$5 ),
    .rst(rst),
    .ssss(\ssss$4 ),
    .val_in(\val_in$1 ),
    .val_in_mns(val_in_mns),
    .val_out(\val_out$3 ),
    .valid(valid),
    .valid_o(valid_o)
  );
  always @* begin
    \$next\val_in$1  = 17'h00000;
    \$next\val_in$1  = val_in;
  end
  always @* begin
    \$next\valid  = 1'h0;
    \$next\valid  = valid_in;
  end
  always @* begin
    \$next\end_in$2  = 1'h0;
    \$next\end_in$2  = end_in;
  end
  always @* begin
    \$next\val_in_mns  = 17'h00000;
    \$next\val_in_mns  = vals_in_mns;
  end
  always @* begin
    \$next\ssss  = 5'h00;
    \$next\ssss  = \ssss$4 ;
  end
  always @* begin
    \$next\val_out  = 16'h0000;
    \$next\val_out  = \val_out$3 ;
  end
  always @* begin
    \$next\valid_out  = 1'h0;
    \$next\valid_out  = valid_o;
  end
  always @* begin
    \$next\end_out  = 1'h0;
    \$next\end_out  = \end_out$5 ;
  end
  assign end_out = \$next\end_out ;
  assign valid_out = \$next\valid_out ;
  assign val_out = \$next\val_out ;
  assign ssss = \$next\ssss ;
  assign val_in_mns = \$next\val_in_mns ;
  assign \end_in$2  = \$next\end_in$2 ;
  assign valid = \$next\valid ;
  assign \val_in$1  = \$next\val_in$1 ;
endmodule