data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/sat14.v
data/verilator_xmls/76399544-127a-48d5-a053-a7606d79bcbc.xml
module sat14 #(
   parameter     RES = 14
)
(

    input  signed [RES-1:0] in,
    input         [RES-1:0] lim,
    output signed [RES-1:0] out
    );
    
    wire [RES-1:0] shifted_in_pos,shifted_in_neg, mask;
    wire pos_sat, neg_sat;
    
    assign mask = {RES{1'b1}}<<lim ;
    
    assign shifted_in_pos = in>>lim  ;
    assign shifted_in_neg = (~in)>>lim  ;
    
    assign pos_sat = ( 2'b01 == { in[RES-1] , |shifted_in_pos } ) ;
    assign neg_sat = ( 2'b11 == { in[RES-1] , |shifted_in_neg } ) ;
    
    
    assign out = pos_sat ?  ( ~mask )    : 
                 neg_sat ?     mask      : 
                 in ;
    
endmodule
module sat14 #(
   parameter     RES = 14
)
(

    input  signed [RES-1:0] in,
    input         [RES-1:0] lim,
    output signed [RES-1:0] out
    );

    
    wire [RES-1:0] shifted_in_pos,shifted_in_neg, mask;
    wire pos_sat, neg_sat;
    
    assign mask = {RES{1'b1}}<<lim ;
    
    assign shifted_in_pos = in>>lim  ;
    assign shifted_in_neg = (~in)>>lim  ;
    
    assign pos_sat = ( 2'b01 == { in[RES-1] , |shifted_in_pos } ) ;
    assign neg_sat = ( 2'b11 == { in[RES-1] , |shifted_in_neg } ) ;
    
    
    assign out = pos_sat ?  ( ~mask )    : 
                 neg_sat ?     mask      : 
                 in ;
    
endmodule