data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/cvita_hdr_encoder.v
data/verilator_xmls/994d4920-4cd3-4c06-863f-2c417607be3d.xml
module cvita_hdr_encoder (
  input [1:0] pkt_type, input eob, input has_time,
  input [11:0] seqnum,
  input [15:0] payload_length,
  input [15:0] src_sid, input [15:0] dst_sid,
  input [63:0] vita_time,
  output [127:0] header
);

  assign header = {pkt_type, has_time, eob, seqnum,
                   payload_length + (has_time ? 16'd16 : 16'd8),
                   src_sid, dst_sid, vita_time};

endmodule
module cvita_hdr_encoder (
  input [1:0] pkt_type, input eob, input has_time,
  input [11:0] seqnum,
  input [15:0] payload_length,
  input [15:0] src_sid, input [15:0] dst_sid,
  input [63:0] vita_time,
  output [127:0] header
);


  assign header = {pkt_type, has_time, eob, seqnum,
                   payload_length + (has_time ? 16'd16 : 16'd8),
                   src_sid, dst_sid, vita_time};

endmodule