data/full_repos/permissive/120518070/main/source/tb_RC4_Core_comb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_Core_comb.sv:15: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_Core_comb.sv:17: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_Core_comb.sv:47: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_Core_comb.sv:52: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_Core_comb.sv:58: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_Core_comb.sv:63: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_Core_comb.sv:69: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_Core_comb.sv:74: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_Core_comb.sv:80: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_Core_comb.sv:85: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_RC4_Core_comb();
	localparam CLK_PERIOD = 20;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	reg [7:0] tb_outputToXor_i;
	reg [19:0] tb_couterPixel_i;
	reg tb_ready_to_write_i;
	reg tb_xor_sig_i;
	reg tb_one_byte_dec_i;
	reg [31:0] tb_dataToDecrypt_i;
	reg tb_enable_write_o;
	reg [1:0] tb_writeLoc_o;
	reg [7:0] tb_data_o;
	reg [19:0] tb_rc4_pix_num_o;


	RC4_Core_comb DUT (.outputToXor_i(tb_outputToXor_i),.couterPixel_i(tb_couterPixel_i),.ready_to_write_i(tb_ready_to_write_i),
			   .xor_sig_i(tb_xor_sig_i),.one_byte_dec_i(tb_one_byte_dec_i),.dataToDecrypt_i(tb_dataToDecrypt_i),.enable_write_o(tb_enable_write_o),
			   .writeLoc_o(tb_writeLoc_o),.data_o(tb_data_o),.rc4_pix_num_o(tb_rc4_pix_num_o));
	initial
	begin
	tb_outputToXor_i = 0;
	tb_couterPixel_i = 0;
	tb_ready_to_write_i = 0;
	tb_xor_sig_i = 0;
	tb_one_byte_dec_i = 0;
	tb_dataToDecrypt_i = 0;
	tb_enable_write_o = 0;
	tb_writeLoc_o = 0;
	tb_data_o = 0;
	tb_rc4_pix_num_o = 0;
	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 55;
	tb_xor_sig_i = 1;
	tb_couterPixel_i = 0;
	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 556;
	tb_xor_sig_i = 0;
	tb_couterPixel_i = 0;

	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 41;
	tb_xor_sig_i = 1;
	tb_couterPixel_i = 1;
	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 556;
	tb_xor_sig_i = 0;
	tb_couterPixel_i = 0;

	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 42;
	tb_xor_sig_i = 1;
	tb_couterPixel_i = 2;
	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 32;
	tb_xor_sig_i = 0;
	tb_couterPixel_i = 0;

	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 55;
	tb_xor_sig_i = 1;
	tb_couterPixel_i = 3;
	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 556;
	tb_xor_sig_i = 0;
	tb_couterPixel_i = 2;
	

	end
endmodule
module tb_RC4_Core_comb();

	localparam CLK_PERIOD = 20;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	reg [7:0] tb_outputToXor_i;
	reg [19:0] tb_couterPixel_i;
	reg tb_ready_to_write_i;
	reg tb_xor_sig_i;
	reg tb_one_byte_dec_i;
	reg [31:0] tb_dataToDecrypt_i;
	reg tb_enable_write_o;
	reg [1:0] tb_writeLoc_o;
	reg [7:0] tb_data_o;
	reg [19:0] tb_rc4_pix_num_o;


	RC4_Core_comb DUT (.outputToXor_i(tb_outputToXor_i),.couterPixel_i(tb_couterPixel_i),.ready_to_write_i(tb_ready_to_write_i),
			   .xor_sig_i(tb_xor_sig_i),.one_byte_dec_i(tb_one_byte_dec_i),.dataToDecrypt_i(tb_dataToDecrypt_i),.enable_write_o(tb_enable_write_o),
			   .writeLoc_o(tb_writeLoc_o),.data_o(tb_data_o),.rc4_pix_num_o(tb_rc4_pix_num_o));
	initial
	begin
	tb_outputToXor_i = 0;
	tb_couterPixel_i = 0;
	tb_ready_to_write_i = 0;
	tb_xor_sig_i = 0;
	tb_one_byte_dec_i = 0;
	tb_dataToDecrypt_i = 0;
	tb_enable_write_o = 0;
	tb_writeLoc_o = 0;
	tb_data_o = 0;
	tb_rc4_pix_num_o = 0;
	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 55;
	tb_xor_sig_i = 1;
	tb_couterPixel_i = 0;
	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 556;
	tb_xor_sig_i = 0;
	tb_couterPixel_i = 0;

	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 41;
	tb_xor_sig_i = 1;
	tb_couterPixel_i = 1;
	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 556;
	tb_xor_sig_i = 0;
	tb_couterPixel_i = 0;

	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 42;
	tb_xor_sig_i = 1;
	tb_couterPixel_i = 2;
	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 32;
	tb_xor_sig_i = 0;
	tb_couterPixel_i = 0;

	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 55;
	tb_xor_sig_i = 1;
	tb_couterPixel_i = 3;
	@(negedge tb_clk);
	tb_dataToDecrypt_i = "HiPi";
	tb_outputToXor_i = 556;
	tb_xor_sig_i = 0;
	tb_couterPixel_i = 2;
	

	end
endmodule