data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v:1: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.sv\n             cmos_cells.v\n             cmos_cells.v.v\n             cmos_cells.v.sv\n             obj_dir/cmos_cells.v\n             obj_dir/cmos_cells.v.v\n             obj_dir/cmos_cells.v.sv\n%Error: Exiting due to 1 error(s)\n'
module ffd_s2p_synth(CLK, D, ENB, Q);
  wire _0_;
  wire _1_;
  wire _2_;
  input CLK;
  input D;
  input ENB;
  output Q;
  reg Q;
  NOT _3_ (
    .A(D),
    .Y(_1_)
  );
  NOT _4_ (
    .A(ENB),
    .Y(_2_)
  );
  NOR _5_ (
    .A(_2_),
    .B(_1_),
    .Y(_0_)
  );
  always @(posedge CLK)
      Q <= _0_;
endmodule
module ffd_s2p_synth(CLK, D, ENB, Q);

  wire _0_;
  wire _1_;
  wire _2_;
  input CLK;
  input D;
  input ENB;
  output Q;
  reg Q;
  NOT _3_ (
    .A(D),
    .Y(_1_)
  );
  NOT _4_ (
    .A(ENB),
    .Y(_2_)
  );
  NOR _5_ (
    .A(_2_),
    .B(_1_),
    .Y(_0_)
  );
  always @(posedge CLK)
      Q <= _0_;
endmodule