data/full_repos/permissive/136510272/projects/ny2018/marsohod2.v
 line:88: before: ")"
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/ny2018/marsohod2.v:68: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance marsohod2\nassign vga_red   = display ? r : 1\'b0;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/ny2018/marsohod2.v:69: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance marsohod2\nassign vga_green = display ? g : 1\'b0;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/ny2018/marsohod2.v:70: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance marsohod2\nassign vga_blue  = display ? b : 1\'b0;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/ny2018/marsohod2.v:73: Operator GT expects 11 bits on the RHS, but RHS\'s CONST \'10\'h2b0\' generates 10 bits.\n                                                                                   : ... In instance marsohod2\nassign vga_hs  = x > 10\'d688 && x <= 10\'d784;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/ny2018/marsohod2.v:73: Operator LTE expects 11 bits on the RHS, but RHS\'s CONST \'10\'h310\' generates 10 bits.\n                                                                                   : ... In instance marsohod2\nassign vga_hs  = x > 10\'d688 && x <= 10\'d784;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/ny2018/marsohod2.v:75: Operator LT expects 11 bits on the RHS, but RHS\'s CONST \'10\'h280\' generates 10 bits.\n                                                                                   : ... In instance marsohod2\nwire   display = x < 10\'d640 && y < 10\'d480;\n                   ^\n%Error: data/full_repos/permissive/136510272/projects/ny2018/marsohod2.v:83: Cannot find file containing module: \'img\'\nimg IMGROM(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/projects/ny2018,data/full_repos/permissive/136510272/img\n             data/full_repos/permissive/136510272/projects/ny2018,data/full_repos/permissive/136510272/img.v\n             data/full_repos/permissive/136510272/projects/ny2018,data/full_repos/permissive/136510272/img.sv\n             img\n             img.v\n             img.sv\n             obj_dir/img\n             obj_dir/img.v\n             obj_dir/img.sv\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/ny2018/marsohod2.v:94: Operator COND expects 32 or 11 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance marsohod2\n    x <= x == 11\'d799 ? 1\'b0 : x + 1;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/ny2018/marsohod2.v:95: Operator COND expects 32 or 10 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance marsohod2\n    y <= x == 11\'d799 ? (y == 10\'d524 ? 1\'b0 : y + 1) : y;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/ny2018/marsohod2.v:97: Operator ADD expects 32 or 17 bits on the LHS, but LHS\'s SEL generates 10 bits.\n                                                                                   : ... In instance marsohod2\n    addr <= (x[10:1] + y[9:1]*320);\n                     ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n'
module marsohod2(




    input   wire        clk,


    output  wire [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);


reg [1:0]  div25;
reg [10:0] x;
reg [9:0]  y;
reg [15:0] color;

wire [4:0] r = color[15:11];
wire [5:0] g = color[10:5];
wire [4:0] b = color[4:0];

assign vga_red   = display ? r : 1'b0;
assign vga_green = display ? g : 1'b0;
assign vga_blue  = display ? b : 1'b0;


assign vga_hs  = x > 10'd688 && x <= 10'd784;
assign vga_vs  = y > 10'd513 && y <= 10'd515;
wire   display = x < 10'd640 && y < 10'd480;


always @(posedge clk) div25 <= div25 + 1'b1;

reg [16:0] addr;
wire [3:0] q;

img IMGROM(

    .clock   (clk),
    .addr_rd (addr),
    .q       (q),
);

                                 

always @(posedge div25[1]) begin	

    x <= x == 11'd799 ? 1'b0 : x + 1;
    y <= x == 11'd799 ? (y == 10'd524 ? 1'b0 : y + 1) : y;
    
    addr <= (x[10:1] + y[9:1]*320);
    case (q)
    
        4'h0: color <= 16'b00000_000000_00000;
        4'h1: color <= 16'b00000_000000_00111;
        4'h2: color <= 16'b00000_001111_00000;
        4'h3: color <= 16'b00000_001111_00111;
        4'h4: color <= 16'b00111_000000_00000;
        4'h5: color <= 16'b00111_000000_00111;
        4'h6: color <= 16'b00111_001111_00000;
        4'h7: color <= 16'b01111_011111_01111;
        4'h8: color <= 16'b00111_001111_00111;
        4'h9: color <= 16'b00000_000000_11111;
        4'hA: color <= 16'b00000_111111_00000;
        4'hB: color <= 16'b00000_111111_11111;
        4'hC: color <= 16'b11111_000000_00000;
        4'hD: color <= 16'b11111_000000_11111;
        4'hE: color <= 16'b11111_111111_00000;
        4'hF: color <= 16'b11111_111111_11111;

    endcase
        
end

endmodule
module marsohod2(




    input   wire        clk,


    output  wire [3:0]  led,


    input   wire [1:0]  keys,


    output  wire        adc_clock_20mhz,
    input   wire [7:0]  adc_input,


    output  wire        sdram_clock,
    output  wire [11:0] sdram_addr,
    output  wire [1:0]  sdram_bank,
    inout   wire [15:0] sdram_dq,
    output  wire        sdram_ldqm,
    output  wire        sdram_udqm,
    output  wire        sdram_ras,
    output  wire        sdram_cas,
    output  wire        sdram_we,


    output  wire [4:0]  vga_red,
    output  wire [5:0]  vga_green,
    output  wire [4:0]  vga_blue,
    output  wire        vga_hs,
    output  wire        vga_vs,


    input   wire        ftdi_rx,
    output  wire        ftdi_tx,




    inout   wire [1:0]  usb,


    output  wire        sound_left,
    output  wire        sound_right,


    inout   wire [1:0]  ps2_keyb,
    inout   wire [1:0]  ps2_mouse
);



reg [1:0]  div25;
reg [10:0] x;
reg [9:0]  y;
reg [15:0] color;

wire [4:0] r = color[15:11];
wire [5:0] g = color[10:5];
wire [4:0] b = color[4:0];

assign vga_red   = display ? r : 1'b0;
assign vga_green = display ? g : 1'b0;
assign vga_blue  = display ? b : 1'b0;


assign vga_hs  = x > 10'd688 && x <= 10'd784;
assign vga_vs  = y > 10'd513 && y <= 10'd515;
wire   display = x < 10'd640 && y < 10'd480;


always @(posedge clk) div25 <= div25 + 1'b1;

reg [16:0] addr;
wire [3:0] q;

img IMGROM(

    .clock   (clk),
    .addr_rd (addr),
    .q       (q),
);

                                 

always @(posedge div25[1]) begin	

    x <= x == 11'd799 ? 1'b0 : x + 1;
    y <= x == 11'd799 ? (y == 10'd524 ? 1'b0 : y + 1) : y;
    
    addr <= (x[10:1] + y[9:1]*320);
    case (q)
    
        4'h0: color <= 16'b00000_000000_00000;
        4'h1: color <= 16'b00000_000000_00111;
        4'h2: color <= 16'b00000_001111_00000;
        4'h3: color <= 16'b00000_001111_00111;
        4'h4: color <= 16'b00111_000000_00000;
        4'h5: color <= 16'b00111_000000_00111;
        4'h6: color <= 16'b00111_001111_00000;
        4'h7: color <= 16'b01111_011111_01111;
        4'h8: color <= 16'b00111_001111_00111;
        4'h9: color <= 16'b00000_000000_11111;
        4'hA: color <= 16'b00000_111111_00000;
        4'hB: color <= 16'b00000_111111_11111;
        4'hC: color <= 16'b11111_000000_00000;
        4'hD: color <= 16'b11111_000000_11111;
        4'hE: color <= 16'b11111_111111_00000;
        4'hF: color <= 16'b11111_111111_11111;

    endcase
        
end

endmodule