data/full_repos/permissive/177039499/instruction-decode/control.v
None: at end of input
1: b'%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:5: Cannot find include file: const.v\n`include "const.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/177039499/instruction-decode,data/full_repos/permissive/177039499/const.v\n             data/full_repos/permissive/177039499/instruction-decode,data/full_repos/permissive/177039499/const.v.v\n             data/full_repos/permissive/177039499/instruction-decode,data/full_repos/permissive/177039499/const.v.sv\n             const.v\n             const.v.v\n             const.v.sv\n             obj_dir/const.v\n             obj_dir/const.v.v\n             obj_dir/const.v.sv\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:24: Define or directive not defined: \'`I_ORI\'\n    assign ExtType  = ~hazard & (opcode != `I_ORI);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign ExtType  = ~hazard & (opcode != `I_ORI);\n                                                 ^\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:25: Define or directive not defined: \'`I_JAL\'\n    assign Link     = ~hazard & (opcode == `I_JAL);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:25: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign Link     = ~hazard & (opcode == `I_JAL);\n                                                 ^\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:26: Define or directive not defined: \'`I_LW\'\n    assign MemRead  = ~hazard & (opcode == `I_LW);\n                                           ^~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:26: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign MemRead  = ~hazard & (opcode == `I_LW);\n                                                ^\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:27: Define or directive not defined: \'`I_SW\'\n    assign MemWrite = ~hazard & (opcode == `I_SW);\n                                           ^~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:27: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign MemWrite = ~hazard & (opcode == `I_SW);\n                                                ^\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:28: Define or directive not defined: \'`I_BNE\'\n    assign NotEqual = ~hazard & (opcode == `I_BNE);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:28: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign NotEqual = ~hazard & (opcode == `I_BNE);\n                                                 ^\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:37: Define or directive not defined: \'`I_ADD\'\n                `I_ADD:  begin ALUOp <= `ALU_ADD; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:37: syntax error, unexpected \':\', expecting endcase\n                `I_ADD:  begin ALUOp <= `ALU_ADD; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                      ^\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:37: Define or directive not defined: \'`ALU_ADD\'\n                `I_ADD:  begin ALUOp <= `ALU_ADD; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:37: syntax error, unexpected \';\', expecting \',\' or \':\'\n                `I_ADD:  begin ALUOp <= `ALU_ADD; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                                                            ^\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:38: Define or directive not defined: \'`I_AND\'\n                `I_AND:  begin ALUOp <= `ALU_AND; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:38: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `I_AND:  begin ALUOp <= `ALU_AND; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                         ^~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:38: Define or directive not defined: \'`ALU_AND\'\n                `I_AND:  begin ALUOp <= `ALU_AND; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:39: Define or directive not defined: \'`I_JR\'\n                `I_JR:   begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 3; RegWrite <= 0; end\n                ^~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:39: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `I_JR:   begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 3; RegWrite <= 0; end\n                         ^~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:40: Define or directive not defined: \'`I_OR\'\n                `I_OR:   begin ALUOp <= `ALU_OR;  IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                ^~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:40: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `I_OR:   begin ALUOp <= `ALU_OR;  IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                         ^~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:40: Define or directive not defined: \'`ALU_OR\'\n                `I_OR:   begin ALUOp <= `ALU_OR;  IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                                        ^~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:41: Define or directive not defined: \'`I_SUB\'\n                `I_SUB:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:41: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `I_SUB:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                         ^~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:41: Define or directive not defined: \'`ALU_SUB\'\n                `I_SUB:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:42: Define or directive not defined: \'`I_SLL\'\n                `I_SLL:  begin ALUOp <= `ALU_SLL; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end\n                ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:42: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `I_SLL:  begin ALUOp <= `ALU_SLL; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end\n                         ^~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:42: Define or directive not defined: \'`ALU_SLL\'\n                `I_SLL:  begin ALUOp <= `ALU_SLL; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:43: Define or directive not defined: \'`I_SLT\'\n                `I_SLT:  begin ALUOp <= `ALU_SLT; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:43: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `I_SLT:  begin ALUOp <= `ALU_SLT; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                         ^~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:43: Define or directive not defined: \'`ALU_SLT\'\n                `I_SLT:  begin ALUOp <= `ALU_SLT; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:44: Define or directive not defined: \'`I_SRA\'\n                `I_SRA:  begin ALUOp <= `ALU_SRA; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end\n                ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:44: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `I_SRA:  begin ALUOp <= `ALU_SRA; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end\n                         ^~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:44: Define or directive not defined: \'`ALU_SRA\'\n                `I_SRA:  begin ALUOp <= `ALU_SRA; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:45: Define or directive not defined: \'`I_SRL\'\n                `I_SRL:  begin ALUOp <= `ALU_SRL; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end\n                ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:45: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `I_SRL:  begin ALUOp <= `ALU_SRL; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end\n                         ^~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:45: Define or directive not defined: \'`ALU_SRL\'\n                `I_SRL:  begin ALUOp <= `ALU_SRL; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:46: syntax error, unexpected default\n                default: begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 0; end\n                ^~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:47: syntax error, unexpected endcase\n                endcase\n                ^~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:48: Define or directive not defined: \'`I_ADDI\'\n            `I_ADDI: begin ALUOp <= `ALU_ADD; IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n            ^~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:48: Define or directive not defined: \'`ALU_ADD\'\n            `I_ADDI: begin ALUOp <= `ALU_ADD; IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:49: Define or directive not defined: \'`I_BEQ\'\n            `I_BEQ:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 1; RegWrite <= 0; end\n            ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:49: Define or directive not defined: \'`ALU_SUB\'\n            `I_BEQ:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 1; RegWrite <= 0; end\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:50: Define or directive not defined: \'`I_BNE\'\n            `I_BNE:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 1; RegWrite <= 0; end\n            ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:50: Define or directive not defined: \'`ALU_SUB\'\n            `I_BNE:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 1; RegWrite <= 0; end\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:51: Define or directive not defined: \'`I_J\'\n            `I_J:    begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 2; RegWrite <= 0; end\n            ^~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:52: Define or directive not defined: \'`I_JAL\'\n            `I_JAL:  begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 2; RegWrite <= 0; end\n            ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:53: Define or directive not defined: \'`I_LUI\'\n            `I_LUI:  begin ALUOp <= `ALU_LUI; IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n            ^~~~~~\n%Error: data/full_repos/permissive/177039499/instruction-decode/control.v:53: Define or directive not defined: \'`ALU_LUI\'\n            `I_LUI:  begin ALUOp <= `ALU_LUI; IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end\n                                    ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ctrl(
    input  wire [5:0] opcode,
    input  wire [5:0] funct,
    input  wire       hazard,
    
    output reg  [3:0] ALUOp,
    output wire       ExtType,
    output reg        IsImd,
    output reg        IsShift,
    output wire       Link,
    output wire       MemRead,
    output wire       MemWrite,
    output wire       NotEqual,
    output reg  [1:0] PCSrc,
    output reg        RegWrite
);

    assign ExtType  = ~hazard & (opcode != `I_ORI);
    assign Link     = ~hazard & (opcode == `I_JAL);
    assign MemRead  = ~hazard & (opcode == `I_LW);
    assign MemWrite = ~hazard & (opcode == `I_SW);
    assign NotEqual = ~hazard & (opcode == `I_BNE);

    always @(*) begin
        if (hazard)
            begin ALUOp <= 0; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 0; end
        else begin
            case (opcode)
            6'b000000:
                case (funct)
                `I_ADD:  begin ALUOp <= `ALU_ADD; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
                `I_AND:  begin ALUOp <= `ALU_AND; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
                `I_JR:   begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 3; RegWrite <= 0; end
                `I_OR:   begin ALUOp <= `ALU_OR;  IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
                `I_SUB:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
                `I_SLL:  begin ALUOp <= `ALU_SLL; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end
                `I_SLT:  begin ALUOp <= `ALU_SLT; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
                `I_SRA:  begin ALUOp <= `ALU_SRA; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end
                `I_SRL:  begin ALUOp <= `ALU_SRL; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end
                default: begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 0; end
                endcase
            `I_ADDI: begin ALUOp <= `ALU_ADD; IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
            `I_BEQ:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 1; RegWrite <= 0; end
            `I_BNE:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 1; RegWrite <= 0; end
            `I_J:    begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 2; RegWrite <= 0; end
            `I_JAL:  begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 2; RegWrite <= 0; end
            `I_LUI:  begin ALUOp <= `ALU_LUI; IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
            `I_LW:   begin ALUOp <= `ALU_ADD; IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
            `I_ORI:  begin ALUOp <= `ALU_OR;  IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
            `I_SW:   begin ALUOp <= `ALU_ADD; IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 0; end
            default: begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 0; end
            endcase
        end
    end

endmodule
module ctrl(
    input  wire [5:0] opcode,
    input  wire [5:0] funct,
    input  wire       hazard,
    
    output reg  [3:0] ALUOp,
    output wire       ExtType,
    output reg        IsImd,
    output reg        IsShift,
    output wire       Link,
    output wire       MemRead,
    output wire       MemWrite,
    output wire       NotEqual,
    output reg  [1:0] PCSrc,
    output reg        RegWrite
);


    assign ExtType  = ~hazard & (opcode != `I_ORI);
    assign Link     = ~hazard & (opcode == `I_JAL);
    assign MemRead  = ~hazard & (opcode == `I_LW);
    assign MemWrite = ~hazard & (opcode == `I_SW);
    assign NotEqual = ~hazard & (opcode == `I_BNE);

    always @(*) begin
        if (hazard)
            begin ALUOp <= 0; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 0; end
        else begin
            case (opcode)
            6'b000000:
                case (funct)
                `I_ADD:  begin ALUOp <= `ALU_ADD; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
                `I_AND:  begin ALUOp <= `ALU_AND; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
                `I_JR:   begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 3; RegWrite <= 0; end
                `I_OR:   begin ALUOp <= `ALU_OR;  IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
                `I_SUB:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
                `I_SLL:  begin ALUOp <= `ALU_SLL; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end
                `I_SLT:  begin ALUOp <= `ALU_SLT; IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
                `I_SRA:  begin ALUOp <= `ALU_SRA; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end
                `I_SRL:  begin ALUOp <= `ALU_SRL; IsImd <= 0; IsShift <= 1; PCSrc <= 0; RegWrite <= 1; end
                default: begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 0; end
                endcase
            `I_ADDI: begin ALUOp <= `ALU_ADD; IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
            `I_BEQ:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 1; RegWrite <= 0; end
            `I_BNE:  begin ALUOp <= `ALU_SUB; IsImd <= 0; IsShift <= 0; PCSrc <= 1; RegWrite <= 0; end
            `I_J:    begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 2; RegWrite <= 0; end
            `I_JAL:  begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 2; RegWrite <= 0; end
            `I_LUI:  begin ALUOp <= `ALU_LUI; IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
            `I_LW:   begin ALUOp <= `ALU_ADD; IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
            `I_ORI:  begin ALUOp <= `ALU_OR;  IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 1; end
            `I_SW:   begin ALUOp <= `ALU_ADD; IsImd <= 1; IsShift <= 0; PCSrc <= 0; RegWrite <= 0; end
            default: begin ALUOp <= 0;        IsImd <= 0; IsShift <= 0; PCSrc <= 0; RegWrite <= 0; end
            endcase
        end
    end

endmodule