data/full_repos/permissive/106583614/Lab1/LEDtb.v
 line:39: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab1/LEDtb.v:30: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab1/LEDtb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab1/LEDtb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Error: data/full_repos/permissive/106583614/Lab1/LEDtb.v:12: Cannot find file containing module: \'LEDsystem\'\nLEDsystem sys0\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106583614/Lab1,data/full_repos/permissive/106583614/LEDsystem\n             data/full_repos/permissive/106583614/Lab1,data/full_repos/permissive/106583614/LEDsystem.v\n             data/full_repos/permissive/106583614/Lab1,data/full_repos/permissive/106583614/LEDsystem.sv\n             LEDsystem\n             LEDsystem.v\n             LEDsystem.sv\n             obj_dir/LEDsystem\n             obj_dir/LEDsystem.v\n             obj_dir/LEDsystem.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_LEDsystem;
reg clk;
reg rst_p;

wire an3, an2, an1, an0;
wire a, b, c, d, e, f, g, dp;

LEDsystem sys0
(
	.reset (rst_p),
	.clk (clk),
	.an3(an3),
	.an2(an2),
	.an1(an1),
	.an0(an0),
	.a(a),
	.b(b),
	.c(c),
	.d(d),
	.e(e),
	.f(f),
	.g(g),
	.dp(dp)
);

always #10 clk=~clk;
	
initial begin
	rst_p = 1'b1;
	clk = 1'b1;
	#10
	rst_p = 1'b0;

	#1000
	$finish;

end

endmodule
module tb_LEDsystem;

reg clk;
reg rst_p;

wire an3, an2, an1, an0;
wire a, b, c, d, e, f, g, dp;

LEDsystem sys0
(
	.reset (rst_p),
	.clk (clk),
	.an3(an3),
	.an2(an2),
	.an1(an1),
	.an0(an0),
	.a(a),
	.b(b),
	.c(c),
	.d(d),
	.e(e),
	.f(f),
	.g(g),
	.dp(dp)
);

always #10 clk=~clk;
	
initial begin
	rst_p = 1'b1;
	clk = 1'b1;
	#10
	rst_p = 1'b0;

	#1000
	$finish;

end

endmodule