data/full_repos/permissive/143278/ivltests/unary_minus2.v
 line:49: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/unary_minus2.v:49: Unsupported: Ignoring delay on this delayed statement.\n   initial #1 begin\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
   wire [9:0] out1, out2;

   U1 u1 (out1);
   U2 u2 (out2);

   initial #1 begin
      if (out1 !== 10'h280) begin
	 $display("FAILED -- out1 = %b", out1);
	 $finish;
      end

      if (out2 !== 10'h060) begin
	 $display("FAILED -- out2 = %b", out2);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;

   wire [9:0] out1, out2;

   U1 u1 (out1);
   U2 u2 (out2);

   initial #1 begin
      if (out1 !== 10'h280) begin
	 $display("FAILED -- out1 = %b", out1);
	 $finish;
      end

      if (out2 !== 10'h060) begin
	 $display("FAILED -- out2 = %b", out2);
	 $finish;
      end

      $display("PASSED");
   end
endmodule