data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_memory_monociclo.v
 line:63: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_memory_monociclo.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #500 $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_memory_monociclo.v:67: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/205673649/MIPS/Simulacion/tb_instruction_memory_monociclo.v:70: Cannot find file containing module: \'tl_memory\'\ntl_memory\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_memory\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_memory.v\n             data/full_repos/permissive/205673649/MIPS/Simulacion,data/full_repos/permissive/205673649/tl_memory.sv\n             tl_memory\n             tl_memory.v\n             tl_memory.sv\n             obj_dir/tl_memory\n             obj_dir/tl_memory.v\n             obj_dir/tl_memory.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_instruction_memory_monociclo();

localparam LEN=32;
localparam NB_ADDRESS_REGISTROS = 5;
localparam NB_CTRL_WB = 2;
localparam NB_CTRL_MEM = 3;

reg clk;
reg rst;
reg [LEN-1:0] address_ex;
reg [LEN-1:0] write_data;
reg [NB_CTRL_WB-1:0] ctrl_wb_ex;
reg [NB_CTRL_MEM-1:0] ctrl_mem_ex;
reg alu_zero_ex;            
reg [NB_ADDRESS_REGISTROS-1:0] write_reg_ex;
wire [LEN-1:0] address_mem;
wire [LEN-1:0] read_data_mem;
wire [NB_ADDRESS_REGISTROS-1:0] write_reg_mem;
wire [NB_CTRL_WB-1:0] ctrl_wb_mem;
wire PCSrc;

initial
begin
    clk = 1'b0;
    rst = 1'b1;
    address_ex = 32'b0;
    write_data = 32'b0;
    ctrl_wb_ex = 2'b0;
    ctrl_mem_ex = 3'b0;
    alu_zero_ex = 1'b0;
    write_reg_ex = 5'b0;
    



    



    
    #500 $finish;
end


always #2.5 clk=~clk;


tl_memory
#(
    .LEN(LEN),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM)
)
    u_tl_memory
(
    .i_clk(clk),
    .i_rst(rst),
    .i_address(address_ex),
    .i_write_data(write_data),
    .i_ctrl_wb(ctrl_wb_ex),
    .i_ctrl_mem(ctrl_mem_ex),
    .i_alu_zero(alu_zero_ex),
    .i_write_reg(write_reg_ex),
    .o_address(address_mem),
    .o_read_data(read_data_mem),
    .o_write_reg(write_reg_mem),
    .o_ctrl_wb(ctrl_wb_mem),
    .o_PCSrc(PCSrc)
);

endmodule
module tb_instruction_memory_monociclo();


localparam LEN=32;
localparam NB_ADDRESS_REGISTROS = 5;
localparam NB_CTRL_WB = 2;
localparam NB_CTRL_MEM = 3;

reg clk;
reg rst;
reg [LEN-1:0] address_ex;
reg [LEN-1:0] write_data;
reg [NB_CTRL_WB-1:0] ctrl_wb_ex;
reg [NB_CTRL_MEM-1:0] ctrl_mem_ex;
reg alu_zero_ex;            
reg [NB_ADDRESS_REGISTROS-1:0] write_reg_ex;
wire [LEN-1:0] address_mem;
wire [LEN-1:0] read_data_mem;
wire [NB_ADDRESS_REGISTROS-1:0] write_reg_mem;
wire [NB_CTRL_WB-1:0] ctrl_wb_mem;
wire PCSrc;

initial
begin
    clk = 1'b0;
    rst = 1'b1;
    address_ex = 32'b0;
    write_data = 32'b0;
    ctrl_wb_ex = 2'b0;
    ctrl_mem_ex = 3'b0;
    alu_zero_ex = 1'b0;
    write_reg_ex = 5'b0;
    



    



    
    #500 $finish;
end


always #2.5 clk=~clk;


tl_memory
#(
    .LEN(LEN),
    .NB_ADDRESS_REGISTROS(NB_ADDRESS_REGISTROS),
    .NB_CTRL_WB(NB_CTRL_WB),
    .NB_CTRL_MEM(NB_CTRL_MEM)
)
    u_tl_memory
(
    .i_clk(clk),
    .i_rst(rst),
    .i_address(address_ex),
    .i_write_data(write_data),
    .i_ctrl_wb(ctrl_wb_ex),
    .i_ctrl_mem(ctrl_mem_ex),
    .i_alu_zero(alu_zero_ex),
    .i_write_reg(write_reg_ex),
    .o_address(address_mem),
    .o_read_data(read_data_mem),
    .o_write_reg(write_reg_mem),
    .o_ctrl_wb(ctrl_wb_mem),
    .o_PCSrc(PCSrc)
);

endmodule