data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay_all_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay_all_tb.sv:20: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_replay,data/full_repos/permissive/214858095/test_exec.svh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_replay,data/full_repos/permissive/214858095/test_exec.svh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_replay,data/full_repos/permissive/214858095/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay_all_tb.sv:21: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgTestExec::*;\n         ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module rfnoc_block_replay_all_tb;

  `include "test_exec.svh"
  import PkgTestExec::*;






  typedef struct {
    int CHDR_W;
    int ITEM_W;
    int NUM_PORTS;
    int MEM_DATA_W;
    int MEM_ADDR_W;
    int TEST_REGS;
    int TEST_FULL;
    int STALL_PROB;
  } test_config_t;

  localparam NUM_TESTS = 15;

  localparam test_config_t test[NUM_TESTS] = '{

    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W:  32, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 1, STALL_PROB: 25},
    '{CHDR_W: 128, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W:  32, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 0, STALL_PROB: 25},
    '{CHDR_W: 256, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W:  32, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 1, STALL_PROB: 25},
    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 2, MEM_DATA_W:  64, MEM_ADDR_W: 16, TEST_REGS: 1, TEST_FULL: 1, STALL_PROB: 25},
    '{CHDR_W: 128, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W:  64, MEM_ADDR_W: 16, TEST_REGS: 1, TEST_FULL: 0, STALL_PROB: 25},
    '{CHDR_W: 256, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W:  64, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 0, STALL_PROB: 25},
    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W: 128, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 0, STALL_PROB: 25},
    '{CHDR_W: 128, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W: 128, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 0, STALL_PROB: 25},
    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W: 256, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 1, STALL_PROB: 25},
    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W: 512, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 0, STALL_PROB: 25},

    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 2, MEM_DATA_W:  64, MEM_ADDR_W: 16, TEST_REGS: 1, TEST_FULL: 1, STALL_PROB:  0},
    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 2, MEM_DATA_W:  64, MEM_ADDR_W: 16, TEST_REGS: 1, TEST_FULL: 1, STALL_PROB: 75},

    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 2, MEM_DATA_W:  64, MEM_ADDR_W: 34, TEST_REGS: 1, TEST_FULL: 0, STALL_PROB:  0},

    '{CHDR_W:  64, ITEM_W: 16, NUM_PORTS: 1, MEM_DATA_W:  32, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 1, STALL_PROB: 25},
    '{CHDR_W: 256, ITEM_W:  8, NUM_PORTS: 1, MEM_DATA_W:  32, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 1, STALL_PROB: 25}
  };






  genvar i;
  for (i = 0; i < NUM_TESTS; i++) begin : gen_test_config
    rfnoc_block_replay_tb #(
      .CHDR_W     (test[i].CHDR_W    ),
      .NUM_PORTS  (test[i].NUM_PORTS ),
      .MEM_DATA_W (test[i].MEM_DATA_W),
      .MEM_ADDR_W (test[i].MEM_ADDR_W),
      .TEST_FULL  (test[i].TEST_FULL )
    ) rfnoc_block_replay_tb_i ();
  end : gen_test_config

endmodule
module rfnoc_block_replay_all_tb;


  `include "test_exec.svh"
  import PkgTestExec::*;






  typedef struct {
    int CHDR_W;
    int ITEM_W;
    int NUM_PORTS;
    int MEM_DATA_W;
    int MEM_ADDR_W;
    int TEST_REGS;
    int TEST_FULL;
    int STALL_PROB;
  } test_config_t;

  localparam NUM_TESTS = 15;

  localparam test_config_t test[NUM_TESTS] = '{

    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W:  32, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 1, STALL_PROB: 25},
    '{CHDR_W: 128, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W:  32, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 0, STALL_PROB: 25},
    '{CHDR_W: 256, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W:  32, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 1, STALL_PROB: 25},
    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 2, MEM_DATA_W:  64, MEM_ADDR_W: 16, TEST_REGS: 1, TEST_FULL: 1, STALL_PROB: 25},
    '{CHDR_W: 128, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W:  64, MEM_ADDR_W: 16, TEST_REGS: 1, TEST_FULL: 0, STALL_PROB: 25},
    '{CHDR_W: 256, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W:  64, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 0, STALL_PROB: 25},
    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W: 128, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 0, STALL_PROB: 25},
    '{CHDR_W: 128, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W: 128, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 0, STALL_PROB: 25},
    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W: 256, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 1, STALL_PROB: 25},
    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 1, MEM_DATA_W: 512, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 0, STALL_PROB: 25},

    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 2, MEM_DATA_W:  64, MEM_ADDR_W: 16, TEST_REGS: 1, TEST_FULL: 1, STALL_PROB:  0},
    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 2, MEM_DATA_W:  64, MEM_ADDR_W: 16, TEST_REGS: 1, TEST_FULL: 1, STALL_PROB: 75},

    '{CHDR_W:  64, ITEM_W: 32, NUM_PORTS: 2, MEM_DATA_W:  64, MEM_ADDR_W: 34, TEST_REGS: 1, TEST_FULL: 0, STALL_PROB:  0},

    '{CHDR_W:  64, ITEM_W: 16, NUM_PORTS: 1, MEM_DATA_W:  32, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 1, STALL_PROB: 25},
    '{CHDR_W: 256, ITEM_W:  8, NUM_PORTS: 1, MEM_DATA_W:  32, MEM_ADDR_W: 16, TEST_REGS: 0, TEST_FULL: 1, STALL_PROB: 25}
  };






  genvar i;
  for (i = 0; i < NUM_TESTS; i++) begin : gen_test_config
    rfnoc_block_replay_tb #(
      .CHDR_W     (test[i].CHDR_W    ),
      .NUM_PORTS  (test[i].NUM_PORTS ),
      .MEM_DATA_W (test[i].MEM_DATA_W),
      .MEM_ADDR_W (test[i].MEM_ADDR_W),
      .TEST_FULL  (test[i].TEST_FULL )
    ) rfnoc_block_replay_tb_i ();
  end : gen_test_config

endmodule