data/full_repos/permissive/120024308/src/core/core.v
1: b"%Error: data/full_repos/permissive/120024308/src/core/core.v:30: Cannot find file containing module: 'CPU'\n   CPU CPU(\n   ^~~\n        ... Looked in:\n             data/full_repos/permissive/120024308/src/core,data/full_repos/permissive/120024308/CPU\n             data/full_repos/permissive/120024308/src/core,data/full_repos/permissive/120024308/CPU.v\n             data/full_repos/permissive/120024308/src/core,data/full_repos/permissive/120024308/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: data/full_repos/permissive/120024308/src/core/core.v:42: Cannot find file containing module: 'Ram'\n   Ram Ram(\n   ^~~\n%Error: Exiting due to 2 error(s)\n"
module Core(
	    input wire 	     Clock,
	    input wire 	     Reset,
	    output wire [7:0] Led
	    );
   wire                       cpu_read_en, cpu_write_en;
   wire [31:0] 		      cpu_address;
   wire [31:0] 		      cpu_read_data, cpu_write_data;
   
   CPU CPU(
	   .clk(Clock),
	   .reset(Reset),
	   .data(Led),
           .ram_enable_read(cpu_read_en),
           .ram_enable_write(cpu_write_en),
           .ram_data_write(cpu_write_data),
           .ram_data_read(cpu_read_data),
           .ram_address(cpu_address)
	   );
   
   
   Ram Ram(
	   .clk(Clock),
	   .write_en(cpu_write_en),
	   .read_en(cpu_read_en),
	   .address(cpu_address),
	   .data_in(cpu_write_data),
	   .data_out(cpu_read_data)
	   );   

endmodule
module Core(
	    input wire 	     Clock,
	    input wire 	     Reset,
	    output wire [7:0] Led
	    );

   wire                       cpu_read_en, cpu_write_en;
   wire [31:0] 		      cpu_address;
   wire [31:0] 		      cpu_read_data, cpu_write_data;
   
   CPU CPU(
	   .clk(Clock),
	   .reset(Reset),
	   .data(Led),
           .ram_enable_read(cpu_read_en),
           .ram_enable_write(cpu_write_en),
           .ram_data_write(cpu_write_data),
           .ram_data_read(cpu_read_data),
           .ram_address(cpu_address)
	   );
   
   
   Ram Ram(
	   .clk(Clock),
	   .write_en(cpu_write_en),
	   .read_en(cpu_read_en),
	   .address(cpu_address),
	   .data_in(cpu_write_data),
	   .data_out(cpu_read_data)
	   );   

endmodule