data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/sonic_vc.v
1: b"%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/sonic_vc.v:81: Cannot find file containing module: 'sonic_vc_multiplexer_0'\n sonic_vc_multiplexer_0 multiplexer_0 (\n ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis,data/full_repos/permissive/18477150/sonic_vc_multiplexer_0\n             data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis,data/full_repos/permissive/18477150/sonic_vc_multiplexer_0.v\n             data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis,data/full_repos/permissive/18477150/sonic_vc_multiplexer_0.sv\n             sonic_vc_multiplexer_0\n             sonic_vc_multiplexer_0.v\n             sonic_vc_multiplexer_0.sv\n             obj_dir/sonic_vc_multiplexer_0\n             obj_dir/sonic_vc_multiplexer_0.v\n             obj_dir/sonic_vc_multiplexer_0.sv\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/sonic_vc.v:108: Cannot find file containing module: 'sonic_vc_multiplexer_adapter'\n sonic_vc_multiplexer_adapter multiplexer_adapter (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/sonic_vc.v:129: Cannot find file containing module: 'altera_avalon_sc_fifo'\n altera_avalon_sc_fifo #(\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/sonic_vc.v:170: Cannot find file containing module: 'altera_avalon_sc_fifo'\n altera_avalon_sc_fifo #(\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/sonic_vc.v:211: Cannot find file containing module: 'sonic_vc_demultiplexer_0'\n sonic_vc_demultiplexer_0 sonic_vc_demultiplexer_custom_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/sonic_vc.v:241: Cannot find file containing module: 'altera_reset_controller'\n altera_reset_controller #(\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module sonic_vc (
		output wire         rx_vc_out0_valid,
		input  wire         rx_vc_out0_ready,
		output wire [127:0] rx_vc_out0_data,
		output wire         rx_vc_out0_startofpacket,
		output wire         rx_vc_out0_endofpacket,
		output wire         rx_vc_out0_empty,
		output wire         rx_vc_out1_valid,
		input  wire         rx_vc_out1_ready,
		output wire [127:0] rx_vc_out1_data,
		output wire         rx_vc_out1_startofpacket,
		output wire         rx_vc_out1_endofpacket,
		output wire         rx_vc_out1_empty,
		output wire [7:0]   rx_vc_out0_bardec_export,
		input  wire [7:0]   rx_vc_in_bardec_export,
		input  wire         clk_clk,
		input  wire         rx_vc_in_valid,
		output wire         rx_vc_in_ready,
		input  wire [127:0] rx_vc_in_data,
		input  wire         rx_vc_in_startofpacket,
		input  wire         rx_vc_in_endofpacket,
		input  wire         rx_vc_in_empty,
		input  wire         rx_vc_in_channel,
		input  wire [127:0] tx_vc_in0_data,
		input  wire         tx_vc_in0_valid,
		output wire         tx_vc_in0_ready,
		input  wire         tx_vc_in0_startofpacket,
		input  wire         tx_vc_in0_endofpacket,
		input  wire         tx_vc_in0_empty,
		input  wire         tx_vc_in0_error,
		input  wire [127:0] tx_vc_in1_data,
		input  wire         tx_vc_in1_valid,
		output wire         tx_vc_in1_ready,
		input  wire         tx_vc_in1_startofpacket,
		input  wire         tx_vc_in1_endofpacket,
		input  wire         tx_vc_in1_empty,
		input  wire         tx_vc_in1_error,
		input  wire         tx_vc_out_ready,
		output wire         tx_vc_out_valid,
		output wire [127:0] tx_vc_out_data,
		output wire         tx_vc_out_channel,
		output wire         tx_vc_out_error,
		output wire         tx_vc_out_startofpacket,
		output wire         tx_vc_out_endofpacket,
		output wire         tx_vc_out_empty,
		input  wire         reset_reset_n,
		output wire [15:0]  rx_vc_out0_be_export,
		output wire [7:0]   rx_vc_out1_bardec_export,
		input  wire [15:0]  rx_vc_in_be_export,
		output wire [15:0]  rx_vc_out1_be_export
	);

	wire          multiplexer_0_out_endofpacket;
	wire          multiplexer_0_out_valid;
	wire          multiplexer_0_out_startofpacket;
	wire    [0:0] multiplexer_0_out_error;
	wire          multiplexer_0_out_empty;
	wire  [127:0] multiplexer_0_out_data;
	wire          multiplexer_0_out_ready;
	wire          multiplexer_0_out_channel;
	wire          tx_fifo_p0_out_endofpacket;
	wire          tx_fifo_p0_out_valid;
	wire          tx_fifo_p0_out_startofpacket;
	wire          tx_fifo_p0_out_error;
	wire          tx_fifo_p0_out_empty;
	wire  [127:0] tx_fifo_p0_out_data;
	wire          tx_fifo_p0_out_ready;
	wire          tx_fifo_p1_out_endofpacket;
	wire          tx_fifo_p1_out_valid;
	wire          tx_fifo_p1_out_startofpacket;
	wire          tx_fifo_p1_out_error;
	wire          tx_fifo_p1_out_empty;
	wire  [127:0] tx_fifo_p1_out_data;
	wire          tx_fifo_p1_out_ready;
	wire          rst_controller_reset_out_reset;

	sonic_vc_multiplexer_0 multiplexer_0 (
		.clk               (clk_clk),
		.reset_n           (~rst_controller_reset_out_reset),
		.in0_valid         (tx_fifo_p0_out_valid),
		.in0_ready         (tx_fifo_p0_out_ready),
		.in0_data          (tx_fifo_p0_out_data),
		.in0_error         (tx_fifo_p0_out_error),
		.in0_startofpacket (tx_fifo_p0_out_startofpacket),
		.in0_endofpacket   (tx_fifo_p0_out_endofpacket),
		.in0_empty         (tx_fifo_p0_out_empty),
		.in1_valid         (tx_fifo_p1_out_valid),
		.in1_ready         (tx_fifo_p1_out_ready),
		.in1_data          (tx_fifo_p1_out_data),
		.in1_error         (tx_fifo_p1_out_error),
		.in1_startofpacket (tx_fifo_p1_out_startofpacket),
		.in1_endofpacket   (tx_fifo_p1_out_endofpacket),
		.in1_empty         (tx_fifo_p1_out_empty),
		.out_channel       (multiplexer_0_out_channel),
		.out_valid         (multiplexer_0_out_valid),
		.out_ready         (multiplexer_0_out_ready),
		.out_data          (multiplexer_0_out_data),
		.out_error         (multiplexer_0_out_error),
		.out_startofpacket (multiplexer_0_out_startofpacket),
		.out_endofpacket   (multiplexer_0_out_endofpacket),
		.out_empty         (multiplexer_0_out_empty)
	);

	sonic_vc_multiplexer_adapter multiplexer_adapter (
		.clk               (clk_clk),
		.reset_n           (~rst_controller_reset_out_reset),
		.in_ready          (multiplexer_0_out_ready),
		.in_valid          (multiplexer_0_out_valid),
		.in_data           (multiplexer_0_out_data),
		.in_channel        (multiplexer_0_out_channel),
		.in_error          (multiplexer_0_out_error),
		.in_startofpacket  (multiplexer_0_out_startofpacket),
		.in_endofpacket    (multiplexer_0_out_endofpacket),
		.in_empty          (multiplexer_0_out_empty),
		.out_ready         (tx_vc_out_ready),
		.out_valid         (tx_vc_out_valid),
		.out_data          (tx_vc_out_data),
		.out_channel       (tx_vc_out_channel),
		.out_error         (tx_vc_out_error),
		.out_startofpacket (tx_vc_out_startofpacket),
		.out_endofpacket   (tx_vc_out_endofpacket),
		.out_empty         (tx_vc_out_empty)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (2),
		.BITS_PER_SYMBOL     (64),
		.FIFO_DEPTH          (4096),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (1),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) tx_fifo_p0 (
		.clk               (clk_clk),
		.reset             (rst_controller_reset_out_reset),
		.in_data           (tx_vc_in0_data),
		.in_valid          (tx_vc_in0_valid),
		.in_ready          (tx_vc_in0_ready),
		.in_startofpacket  (tx_vc_in0_startofpacket),
		.in_endofpacket    (tx_vc_in0_endofpacket),
		.in_empty          (tx_vc_in0_empty),
		.in_error          (tx_vc_in0_error),
		.out_data          (tx_fifo_p0_out_data),
		.out_valid         (tx_fifo_p0_out_valid),
		.out_ready         (tx_fifo_p0_out_ready),
		.out_startofpacket (tx_fifo_p0_out_startofpacket),
		.out_endofpacket   (tx_fifo_p0_out_endofpacket),
		.out_empty         (tx_fifo_p0_out_empty),
		.out_error         (tx_fifo_p0_out_error),
		.csr_address       (2'b00),
		.csr_read          (1'b0),
		.csr_write         (1'b0),
		.csr_readdata      (),
		.csr_writedata     (32'b00000000000000000000000000000000),
		.almost_full_data  (),
		.almost_empty_data (),
		.in_channel        (1'b0),
		.out_channel       ()
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (2),
		.BITS_PER_SYMBOL     (64),
		.FIFO_DEPTH          (4096),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (1),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) tx_fifo_p1 (
		.clk               (clk_clk),
		.reset             (rst_controller_reset_out_reset),
		.in_data           (tx_vc_in1_data),
		.in_valid          (tx_vc_in1_valid),
		.in_ready          (tx_vc_in1_ready),
		.in_startofpacket  (tx_vc_in1_startofpacket),
		.in_endofpacket    (tx_vc_in1_endofpacket),
		.in_empty          (tx_vc_in1_empty),
		.in_error          (tx_vc_in1_error),
		.out_data          (tx_fifo_p1_out_data),
		.out_valid         (tx_fifo_p1_out_valid),
		.out_ready         (tx_fifo_p1_out_ready),
		.out_startofpacket (tx_fifo_p1_out_startofpacket),
		.out_endofpacket   (tx_fifo_p1_out_endofpacket),
		.out_empty         (tx_fifo_p1_out_empty),
		.out_error         (tx_fifo_p1_out_error),
		.csr_address       (2'b00),
		.csr_read          (1'b0),
		.csr_write         (1'b0),
		.csr_readdata      (),
		.csr_writedata     (32'b00000000000000000000000000000000),
		.almost_full_data  (),
		.almost_empty_data (),
		.in_channel        (1'b0),
		.out_channel       ()
	);

	sonic_vc_demultiplexer_0 sonic_vc_demultiplexer_custom_0 (
		.clk                (clk_clk),
		.in_valid           (rx_vc_in_valid),
		.in_ready           (rx_vc_in_ready),
		.in_data            (rx_vc_in_data),
		.in_startofpacket   (rx_vc_in_startofpacket),
		.in_endofpacket     (rx_vc_in_endofpacket),
		.in_empty           (rx_vc_in_empty),
		.in_channel         (rx_vc_in_channel),
		.out0_valid         (rx_vc_out0_valid),
		.out0_ready         (rx_vc_out0_ready),
		.out0_data          (rx_vc_out0_data),
		.out0_startofpacket (rx_vc_out0_startofpacket),
		.out0_endofpacket   (rx_vc_out0_endofpacket),
		.out0_empty         (rx_vc_out0_empty),
		.out1_valid         (rx_vc_out1_valid),
		.out1_ready         (rx_vc_out1_ready),
		.out1_data          (rx_vc_out1_data),
		.out1_startofpacket (rx_vc_out1_startofpacket),
		.out1_endofpacket   (rx_vc_out1_endofpacket),
		.out1_empty         (rx_vc_out1_empty),
		.in_bardec          (rx_vc_in_bardec_export),
		.in_be              (rx_vc_in_be_export),
		.out0_bardec        (rx_vc_out0_bardec_export),
		.out0_be            (rx_vc_out0_be_export),
		.out1_bardec        (rx_vc_out1_bardec_export),
		.out1_be            (rx_vc_out1_be_export),
		.reset_n            (~rst_controller_reset_out_reset)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~reset_reset_n),
		.clk        (clk_clk),
		.reset_out  (rst_controller_reset_out_reset),
		.reset_in1  (1'b0),
		.reset_in2  (1'b0),
		.reset_in3  (1'b0),
		.reset_in4  (1'b0),
		.reset_in5  (1'b0),
		.reset_in6  (1'b0),
		.reset_in7  (1'b0),
		.reset_in8  (1'b0),
		.reset_in9  (1'b0),
		.reset_in10 (1'b0),
		.reset_in11 (1'b0),
		.reset_in12 (1'b0),
		.reset_in13 (1'b0),
		.reset_in14 (1'b0),
		.reset_in15 (1'b0)
	);

endmodule
module sonic_vc (
		output wire         rx_vc_out0_valid,
		input  wire         rx_vc_out0_ready,
		output wire [127:0] rx_vc_out0_data,
		output wire         rx_vc_out0_startofpacket,
		output wire         rx_vc_out0_endofpacket,
		output wire         rx_vc_out0_empty,
		output wire         rx_vc_out1_valid,
		input  wire         rx_vc_out1_ready,
		output wire [127:0] rx_vc_out1_data,
		output wire         rx_vc_out1_startofpacket,
		output wire         rx_vc_out1_endofpacket,
		output wire         rx_vc_out1_empty,
		output wire [7:0]   rx_vc_out0_bardec_export,
		input  wire [7:0]   rx_vc_in_bardec_export,
		input  wire         clk_clk,
		input  wire         rx_vc_in_valid,
		output wire         rx_vc_in_ready,
		input  wire [127:0] rx_vc_in_data,
		input  wire         rx_vc_in_startofpacket,
		input  wire         rx_vc_in_endofpacket,
		input  wire         rx_vc_in_empty,
		input  wire         rx_vc_in_channel,
		input  wire [127:0] tx_vc_in0_data,
		input  wire         tx_vc_in0_valid,
		output wire         tx_vc_in0_ready,
		input  wire         tx_vc_in0_startofpacket,
		input  wire         tx_vc_in0_endofpacket,
		input  wire         tx_vc_in0_empty,
		input  wire         tx_vc_in0_error,
		input  wire [127:0] tx_vc_in1_data,
		input  wire         tx_vc_in1_valid,
		output wire         tx_vc_in1_ready,
		input  wire         tx_vc_in1_startofpacket,
		input  wire         tx_vc_in1_endofpacket,
		input  wire         tx_vc_in1_empty,
		input  wire         tx_vc_in1_error,
		input  wire         tx_vc_out_ready,
		output wire         tx_vc_out_valid,
		output wire [127:0] tx_vc_out_data,
		output wire         tx_vc_out_channel,
		output wire         tx_vc_out_error,
		output wire         tx_vc_out_startofpacket,
		output wire         tx_vc_out_endofpacket,
		output wire         tx_vc_out_empty,
		input  wire         reset_reset_n,
		output wire [15:0]  rx_vc_out0_be_export,
		output wire [7:0]   rx_vc_out1_bardec_export,
		input  wire [15:0]  rx_vc_in_be_export,
		output wire [15:0]  rx_vc_out1_be_export
	);


	wire          multiplexer_0_out_endofpacket;
	wire          multiplexer_0_out_valid;
	wire          multiplexer_0_out_startofpacket;
	wire    [0:0] multiplexer_0_out_error;
	wire          multiplexer_0_out_empty;
	wire  [127:0] multiplexer_0_out_data;
	wire          multiplexer_0_out_ready;
	wire          multiplexer_0_out_channel;
	wire          tx_fifo_p0_out_endofpacket;
	wire          tx_fifo_p0_out_valid;
	wire          tx_fifo_p0_out_startofpacket;
	wire          tx_fifo_p0_out_error;
	wire          tx_fifo_p0_out_empty;
	wire  [127:0] tx_fifo_p0_out_data;
	wire          tx_fifo_p0_out_ready;
	wire          tx_fifo_p1_out_endofpacket;
	wire          tx_fifo_p1_out_valid;
	wire          tx_fifo_p1_out_startofpacket;
	wire          tx_fifo_p1_out_error;
	wire          tx_fifo_p1_out_empty;
	wire  [127:0] tx_fifo_p1_out_data;
	wire          tx_fifo_p1_out_ready;
	wire          rst_controller_reset_out_reset;

	sonic_vc_multiplexer_0 multiplexer_0 (
		.clk               (clk_clk),
		.reset_n           (~rst_controller_reset_out_reset),
		.in0_valid         (tx_fifo_p0_out_valid),
		.in0_ready         (tx_fifo_p0_out_ready),
		.in0_data          (tx_fifo_p0_out_data),
		.in0_error         (tx_fifo_p0_out_error),
		.in0_startofpacket (tx_fifo_p0_out_startofpacket),
		.in0_endofpacket   (tx_fifo_p0_out_endofpacket),
		.in0_empty         (tx_fifo_p0_out_empty),
		.in1_valid         (tx_fifo_p1_out_valid),
		.in1_ready         (tx_fifo_p1_out_ready),
		.in1_data          (tx_fifo_p1_out_data),
		.in1_error         (tx_fifo_p1_out_error),
		.in1_startofpacket (tx_fifo_p1_out_startofpacket),
		.in1_endofpacket   (tx_fifo_p1_out_endofpacket),
		.in1_empty         (tx_fifo_p1_out_empty),
		.out_channel       (multiplexer_0_out_channel),
		.out_valid         (multiplexer_0_out_valid),
		.out_ready         (multiplexer_0_out_ready),
		.out_data          (multiplexer_0_out_data),
		.out_error         (multiplexer_0_out_error),
		.out_startofpacket (multiplexer_0_out_startofpacket),
		.out_endofpacket   (multiplexer_0_out_endofpacket),
		.out_empty         (multiplexer_0_out_empty)
	);

	sonic_vc_multiplexer_adapter multiplexer_adapter (
		.clk               (clk_clk),
		.reset_n           (~rst_controller_reset_out_reset),
		.in_ready          (multiplexer_0_out_ready),
		.in_valid          (multiplexer_0_out_valid),
		.in_data           (multiplexer_0_out_data),
		.in_channel        (multiplexer_0_out_channel),
		.in_error          (multiplexer_0_out_error),
		.in_startofpacket  (multiplexer_0_out_startofpacket),
		.in_endofpacket    (multiplexer_0_out_endofpacket),
		.in_empty          (multiplexer_0_out_empty),
		.out_ready         (tx_vc_out_ready),
		.out_valid         (tx_vc_out_valid),
		.out_data          (tx_vc_out_data),
		.out_channel       (tx_vc_out_channel),
		.out_error         (tx_vc_out_error),
		.out_startofpacket (tx_vc_out_startofpacket),
		.out_endofpacket   (tx_vc_out_endofpacket),
		.out_empty         (tx_vc_out_empty)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (2),
		.BITS_PER_SYMBOL     (64),
		.FIFO_DEPTH          (4096),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (1),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) tx_fifo_p0 (
		.clk               (clk_clk),
		.reset             (rst_controller_reset_out_reset),
		.in_data           (tx_vc_in0_data),
		.in_valid          (tx_vc_in0_valid),
		.in_ready          (tx_vc_in0_ready),
		.in_startofpacket  (tx_vc_in0_startofpacket),
		.in_endofpacket    (tx_vc_in0_endofpacket),
		.in_empty          (tx_vc_in0_empty),
		.in_error          (tx_vc_in0_error),
		.out_data          (tx_fifo_p0_out_data),
		.out_valid         (tx_fifo_p0_out_valid),
		.out_ready         (tx_fifo_p0_out_ready),
		.out_startofpacket (tx_fifo_p0_out_startofpacket),
		.out_endofpacket   (tx_fifo_p0_out_endofpacket),
		.out_empty         (tx_fifo_p0_out_empty),
		.out_error         (tx_fifo_p0_out_error),
		.csr_address       (2'b00),
		.csr_read          (1'b0),
		.csr_write         (1'b0),
		.csr_readdata      (),
		.csr_writedata     (32'b00000000000000000000000000000000),
		.almost_full_data  (),
		.almost_empty_data (),
		.in_channel        (1'b0),
		.out_channel       ()
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (2),
		.BITS_PER_SYMBOL     (64),
		.FIFO_DEPTH          (4096),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (1),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) tx_fifo_p1 (
		.clk               (clk_clk),
		.reset             (rst_controller_reset_out_reset),
		.in_data           (tx_vc_in1_data),
		.in_valid          (tx_vc_in1_valid),
		.in_ready          (tx_vc_in1_ready),
		.in_startofpacket  (tx_vc_in1_startofpacket),
		.in_endofpacket    (tx_vc_in1_endofpacket),
		.in_empty          (tx_vc_in1_empty),
		.in_error          (tx_vc_in1_error),
		.out_data          (tx_fifo_p1_out_data),
		.out_valid         (tx_fifo_p1_out_valid),
		.out_ready         (tx_fifo_p1_out_ready),
		.out_startofpacket (tx_fifo_p1_out_startofpacket),
		.out_endofpacket   (tx_fifo_p1_out_endofpacket),
		.out_empty         (tx_fifo_p1_out_empty),
		.out_error         (tx_fifo_p1_out_error),
		.csr_address       (2'b00),
		.csr_read          (1'b0),
		.csr_write         (1'b0),
		.csr_readdata      (),
		.csr_writedata     (32'b00000000000000000000000000000000),
		.almost_full_data  (),
		.almost_empty_data (),
		.in_channel        (1'b0),
		.out_channel       ()
	);

	sonic_vc_demultiplexer_0 sonic_vc_demultiplexer_custom_0 (
		.clk                (clk_clk),
		.in_valid           (rx_vc_in_valid),
		.in_ready           (rx_vc_in_ready),
		.in_data            (rx_vc_in_data),
		.in_startofpacket   (rx_vc_in_startofpacket),
		.in_endofpacket     (rx_vc_in_endofpacket),
		.in_empty           (rx_vc_in_empty),
		.in_channel         (rx_vc_in_channel),
		.out0_valid         (rx_vc_out0_valid),
		.out0_ready         (rx_vc_out0_ready),
		.out0_data          (rx_vc_out0_data),
		.out0_startofpacket (rx_vc_out0_startofpacket),
		.out0_endofpacket   (rx_vc_out0_endofpacket),
		.out0_empty         (rx_vc_out0_empty),
		.out1_valid         (rx_vc_out1_valid),
		.out1_ready         (rx_vc_out1_ready),
		.out1_data          (rx_vc_out1_data),
		.out1_startofpacket (rx_vc_out1_startofpacket),
		.out1_endofpacket   (rx_vc_out1_endofpacket),
		.out1_empty         (rx_vc_out1_empty),
		.in_bardec          (rx_vc_in_bardec_export),
		.in_be              (rx_vc_in_be_export),
		.out0_bardec        (rx_vc_out0_bardec_export),
		.out0_be            (rx_vc_out0_be_export),
		.out1_bardec        (rx_vc_out1_bardec_export),
		.out1_be            (rx_vc_out1_be_export),
		.reset_n            (~rst_controller_reset_out_reset)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~reset_reset_n),
		.clk        (clk_clk),
		.reset_out  (rst_controller_reset_out_reset),
		.reset_in1  (1'b0),
		.reset_in2  (1'b0),
		.reset_in3  (1'b0),
		.reset_in4  (1'b0),
		.reset_in5  (1'b0),
		.reset_in6  (1'b0),
		.reset_in7  (1'b0),
		.reset_in8  (1'b0),
		.reset_in9  (1'b0),
		.reset_in10 (1'b0),
		.reset_in11 (1'b0),
		.reset_in12 (1'b0),
		.reset_in13 (1'b0),
		.reset_in14 (1'b0),
		.reset_in15 (1'b0)
	);

endmodule