data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/prj/RTL/M0demo.v
1: b'%Error: data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/prj/RTL/M0demo.v:2: Cannot find include file: cmsdk_mcu_defs.v\n`include "cmsdk_mcu_defs.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/prj/RTL,data/full_repos/permissive/194847941/cmsdk_mcu_defs.v\n             data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/prj/RTL,data/full_repos/permissive/194847941/cmsdk_mcu_defs.v.v\n             data/full_repos/permissive/194847941/demo/13_EG4S20withM0/M0/prj/RTL,data/full_repos/permissive/194847941/cmsdk_mcu_defs.v.sv\n             cmsdk_mcu_defs.v\n             cmsdk_mcu_defs.v.v\n             cmsdk_mcu_defs.v.sv\n             obj_dir/cmsdk_mcu_defs.v\n             obj_dir/cmsdk_mcu_defs.v.v\n             obj_dir/cmsdk_mcu_defs.v.sv\n%Error: Exiting due to 1 error(s)\n'
module M0demo(
    input  wire          XTAL1,
    output wire          XTAL2,
    input  wire          NRST,
    output  wire  [15:0]  P0,

    
    input  wire          nTRST,
    input  wire          TDI,
    output wire          TDO,
    inout  wire          SWDIOTMS,
    input  wire          SWCLKTCK,
    
    inout  wire  [7:0]   b_pad_gpio_porta,

    input  wire          uart0_rxd,
    output wire          uart0_txd,
    output wire          uart0_txen


);
    wire XTAL1_wire;

  parameter BE              = 0;

  parameter BKPT            = 4;
  parameter DBG             = 1;
  parameter NUMIRQ          = 32;
  parameter SMUL            = 0;
  parameter SYST            = 1;
  parameter WIC             = 1;
  parameter WICLINES        = 34;
  parameter WPT             = 2;





  cmsdk_mcu
   #(.BE               (BE),
     .BKPT             (BKPT),
     .DBG              (DBG),
     .NUMIRQ           (NUMIRQ),
     .SMUL             (SMUL),
     .SYST             (SYST),
     .WIC              (WIC),
     .WICLINES         (WICLINES),
     .WPT              (WPT)
   )
   u_cmsdk_mcu (
  .XTAL1      (XTAL1_wire),
  .XTAL2      (XTAL2),
  .NRST       (NRST),
  .P0         (P0),

  .nTRST      (nTRST),
  .TDI        (TDI),
  .TDO        (TDO),
  .TMS        (SWDIOTMS),
  .TCK        (SWCLKTCK),
  
  .b_pad_gpio_porta (b_pad_gpio_porta),
                
  .uart0_rxd        (uart0_rxd),
  .uart0_txd        (uart0_txd),
  .uart0_txen       (uart0_txen)
  );
  


M0clkpll u_M0clkpll(
	.refclk	 (XTAL1    ),
	.clk0_out (XTAL1_wire)
);
  
  
  
endmodule
module M0demo(
    input  wire          XTAL1,
    output wire          XTAL2,
    input  wire          NRST,
    output  wire  [15:0]  P0,

    
    input  wire          nTRST,
    input  wire          TDI,
    output wire          TDO,
    inout  wire          SWDIOTMS,
    input  wire          SWCLKTCK,
    
    inout  wire  [7:0]   b_pad_gpio_porta,

    input  wire          uart0_rxd,
    output wire          uart0_txd,
    output wire          uart0_txen


);

    wire XTAL1_wire;

  parameter BE              = 0;

  parameter BKPT            = 4;
  parameter DBG             = 1;
  parameter NUMIRQ          = 32;
  parameter SMUL            = 0;
  parameter SYST            = 1;
  parameter WIC             = 1;
  parameter WICLINES        = 34;
  parameter WPT             = 2;





  cmsdk_mcu
   #(.BE               (BE),
     .BKPT             (BKPT),
     .DBG              (DBG),
     .NUMIRQ           (NUMIRQ),
     .SMUL             (SMUL),
     .SYST             (SYST),
     .WIC              (WIC),
     .WICLINES         (WICLINES),
     .WPT              (WPT)
   )
   u_cmsdk_mcu (
  .XTAL1      (XTAL1_wire),
  .XTAL2      (XTAL2),
  .NRST       (NRST),
  .P0         (P0),

  .nTRST      (nTRST),
  .TDI        (TDI),
  .TDO        (TDO),
  .TMS        (SWDIOTMS),
  .TCK        (SWCLKTCK),
  
  .b_pad_gpio_porta (b_pad_gpio_porta),
                
  .uart0_rxd        (uart0_rxd),
  .uart0_txd        (uart0_txd),
  .uart0_txen       (uart0_txen)
  );
  


M0clkpll u_M0clkpll(
	.refclk	 (XTAL1    ),
	.clk0_out (XTAL1_wire)
);
  
  
  
endmodule