data/full_repos/permissive/156129873/verilog/VitualSram.v
None: at end of input
1: b'%Warning-WIDTH: data/full_repos/permissive/156129873/verilog/VitualSram.v:14: Bit extraction of array[65535:0] requires 16 bit index, not 18 bits.\n                                                                            : ... In instance VirtualSram\n                rom[ramAddr[17:0]] = ramInputData;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/156129873/verilog/VitualSram.v:17: Bit extraction of array[65535:0] requires 16 bit index, not 18 bits.\n                                                                            : ... In instance VirtualSram\n                ramOutputData = rom[ramAddr[17:0]];\n                                   ^\n%Error: Exiting due to 2 warning(s)\n'
module VirtualSram(
    input wire[15:0] ramInputData,
    input wire[17:0] ramAddr,
    input wire ramOE,
    input wire ramWE,
    input wire ramEN,
	 output reg[15:0] ramOutputData
);
    reg [15:0] rom[65535:0];
    always @(*) begin
        if(ramEN==1'b0) begin
            if(ramOE == 1'b1 && ramWE == 1'b0) begin
                rom[ramAddr[17:0]] = ramInputData;
            end
            else if (ramOE == 1'b0 && ramWE == 1'b1) begin
                ramOutputData = rom[ramAddr[17:0]];
            end
        end
        else begin
            
        end
    end
endmodule
module VirtualSram(
    input wire[15:0] ramInputData,
    input wire[17:0] ramAddr,
    input wire ramOE,
    input wire ramWE,
    input wire ramEN,
	 output reg[15:0] ramOutputData
);

    reg [15:0] rom[65535:0];
    always @(*) begin
        if(ramEN==1'b0) begin
            if(ramOE == 1'b1 && ramWE == 1'b0) begin
                rom[ramAddr[17:0]] = ramInputData;
            end
            else if (ramOE == 1'b0 && ramWE == 1'b1) begin
                ramOutputData = rom[ramAddr[17:0]];
            end
        end
        else begin
            
        end
    end
endmodule