data/full_repos/permissive/174242803/alu_regf/src/regfile.v
1: b'%Warning-WIDTH: data/full_repos/permissive/174242803/alu_regf/src/regfile.v:33: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ra1\' generates 3 bits.\n                                                                              : ... In instance regfile\n   assign rd1 = ra1 ? REGS[ra1] : 0;    \n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/174242803/alu_regf/src/regfile.v:34: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ra2\' generates 3 bits.\n                                                                              : ... In instance regfile\n   assign rd2 = ra2 ? REGS[ra2] : 0;    \n                    ^\n%Error: Exiting due to 2 warning(s)\n'
module regfile (rd1, rd2, clk, regwrite, ra1, ra2, wa, wd) ;











   input        clk ;
   input        regwrite ;
   input  [2:0] ra1 ;
   input  [2:0] ra2 ;
   input  [2:0] wa  ;

   input  [7:0] wd  ;
   output [7:0]  rd1, rd2 ;


   reg  [7:0] REGS [7:0];



   always @(posedge clk)
      if (regwrite) REGS[wa] <= wd;	


   assign rd1 = ra1 ? REGS[ra1] : 0;
   assign rd2 = ra2 ? REGS[ra2] : 0;


endmodule
module regfile (rd1, rd2, clk, regwrite, ra1, ra2, wa, wd) ;












   input        clk ;
   input        regwrite ;
   input  [2:0] ra1 ;
   input  [2:0] ra2 ;
   input  [2:0] wa  ;

   input  [7:0] wd  ;
   output [7:0]  rd1, rd2 ;


   reg  [7:0] REGS [7:0];



   always @(posedge clk)
      if (regwrite) REGS[wa] <= wd;	


   assign rd1 = ra1 ? REGS[ra1] : 0;
   assign rd2 = ra2 ? REGS[ra2] : 0;


endmodule