data/full_repos/permissive/161029703/src/ticker/ticker.v
 line:54: before: ","
1: b'%Warning-WIDTH: data/full_repos/permissive/161029703/src/ticker/ticker.v:49: Operator ADD expects 32 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                           : ... In instance ticker\n    ticker <= ticker + (prescaler == 14\'d9999);   \n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ticker(

  input wire            clk_bus,
  input wire            rst_n,
  
  input wire            clk_tick,
  input wire            rst_tick_n,


  output wire[31:0]     bus_data_o,
  input wire[7:0]      bus_address,
  input wire[31:0]      bus_data_i,
  input wire            bus_read,
  input wire            bus_write

);

reg[31:0] ticker;
reg[31:0] ticker_d1;
reg[31:0] ticker_d2;

reg[13:0] prescaler;

assign bus_data_o = bus_read ? ticker_d2 : 32'd0;


always @(posedge clk_bus or negedge rst_n) begin
  if(!rst_n) begin
    ticker_d1 <= 32'd0;
  end else begin
    ticker_d1 <= ticker;
  end
end

always @(posedge clk_bus or negedge rst_n) begin
  if(!rst_n) begin
    ticker_d2 <= 32'd0;
  end else begin
    ticker_d2 <= ticker_d1;
  end
end

always @(posedge clk_tick or negedge rst_tick_n) begin
  if(!rst_tick_n) begin
    ticker <= 32'd0;
    prescaler <= 14'd0;
  end else begin
    prescaler <= (prescaler < 14'd9999) ? prescaler+1'b1 : 14'd0;
    ticker <= ticker + (prescaler == 14'd9999);
  end
end

endmodule
module ticker(

  input wire            clk_bus,
  input wire            rst_n,
  
  input wire            clk_tick,
  input wire            rst_tick_n,


  output wire[31:0]     bus_data_o,
  input wire[7:0]      bus_address,
  input wire[31:0]      bus_data_i,
  input wire            bus_read,
  input wire            bus_write

);


reg[31:0] ticker;
reg[31:0] ticker_d1;
reg[31:0] ticker_d2;

reg[13:0] prescaler;

assign bus_data_o = bus_read ? ticker_d2 : 32'd0;


always @(posedge clk_bus or negedge rst_n) begin
  if(!rst_n) begin
    ticker_d1 <= 32'd0;
  end else begin
    ticker_d1 <= ticker;
  end
end

always @(posedge clk_bus or negedge rst_n) begin
  if(!rst_n) begin
    ticker_d2 <= 32'd0;
  end else begin
    ticker_d2 <= ticker_d1;
  end
end

always @(posedge clk_tick or negedge rst_tick_n) begin
  if(!rst_tick_n) begin
    ticker <= 32'd0;
    prescaler <= 14'd0;
  end else begin
    prescaler <= (prescaler < 14'd9999) ? prescaler+1'b1 : 14'd0;
    ticker <= ticker + (prescaler == 14'd9999);
  end
end

endmodule