data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v
 line:31: before: "$"
1: b'%Error: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:3: Cannot find include file: piso_8bit.v\n`include "piso_8bit.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117880471/HW3,data/full_repos/permissive/117880471/piso_8bit.v\n             data/full_repos/permissive/117880471/HW3,data/full_repos/permissive/117880471/piso_8bit.v.v\n             data/full_repos/permissive/117880471/HW3,data/full_repos/permissive/117880471/piso_8bit.v.sv\n             piso_8bit.v\n             piso_8bit.v.v\n             piso_8bit.v.sv\n             obj_dir/piso_8bit.v\n             obj_dir/piso_8bit.v.v\n             obj_dir/piso_8bit.v.sv\n%Error: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:4: Cannot find include file: full_adder.v\n`include "full_adder.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:5: Cannot find include file: d_flip_flop.v\n`include "d_flip_flop.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:6: Cannot find include file: sipo_8bit.v\n`include "sipo_8bit.v" \n         ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:16: Unsupported: Ignoring delay on this delayed statement.\n #00 clock = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:17: Unsupported: Ignoring delay on this delayed statement.\n forever #20 clock = ~clock;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:22: Unsupported: Ignoring delay on this delayed statement.\n #00 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:23: Unsupported: Ignoring delay on this delayed statement.\n #50 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10 a = 8\'b0000_0000; b = 8\'b0000_0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:29: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b0000_0000; b = 8\'b0000_0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:30: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b0010_0000; b = 8\'b0000_0010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:31: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b1010_1010; b = 8\'b1010_0101;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b1111_1111; b = 8\'b0111_0100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:33: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b1111_1111; b = 8\'b1111_1111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:34: Unsupported: Ignoring delay on this delayed statement.\n #20 a = 8\'b0000_1000; b = 8\'b0100_0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:35: Unsupported: Ignoring delay on this delayed statement.\n #20 $stop;\n ^\n%Error: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:40: Unsupported or unknown PLI call: $monitor\n $monitor("time=%3d, sum=%8b, a=%8b, b=%8b, clock=%b, reset=%b", $time, sum, a, b, clock, reset);\n ^~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:45: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("serial_adder_8bit.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW3/serial_adder_8bit.v:46: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 7 error(s), 12 warning(s)\n'
module serial_adder_8bit(sum, a, b, clock, reset);

output wire [7:0] sum;
input wire [7:0] a, b;
input wire clock, reset;

wire piso_1_out, piso_2_out;
wire q, d;
wire cout, fa_out;

piso_8bit piso_1(piso_1_out, a, clock, reset);
piso_8bit piso_2(piso_2_out, b, clock, reset);
full_adder fa(fa_out, cout, piso_1_out, piso_2_out, q);
d_flip_flop dff(q, d, clock, reset);
sipo_8bit sipo(sum, fa_out, clock, reset);

endmodule
module serial_adder_8bit(sum, a, b, clock, reset);


output wire [7:0] sum;
input wire [7:0] a, b;
input wire clock, reset;

wire piso_1_out, piso_2_out;
wire q, d;
wire cout, fa_out;

piso_8bit piso_1(piso_1_out, a, clock, reset);
piso_8bit piso_2(piso_2_out, b, clock, reset);
full_adder fa(fa_out, cout, piso_1_out, piso_2_out, q);
d_flip_flop dff(q, d, clock, reset);
sipo_8bit sipo(sum, fa_out, clock, reset);

endmodule