data/full_repos/permissive/129155059/proyecto-02/fifo/fifo_synth.v
 line:291: before: "*"
data/verilator_xmls/6e635495-9760-4b45-af58-3044935ef022.xml
module fifo_synth(CLK, ENB, RST, sRead, sWrite, umbEmpty, umbFull, inputData, almostEmpty, almostFull, outEmpty, outFull, errorEmpty, errorFull, outputData);
  (* src = "fifo_synth.v:31" *)
  wire [2:0] _000_;
  (* src = "fifo_synth.v:31" *)
  wire [7:0] _001_;
  (* src = "fifo_synth.v:31" *)
  wire [7:0] _002_;
  (* src = "fifo_synth.v:31" *)
  wire _003_;
  (* src = "fifo_synth.v:31" *)
  wire _004_;
  (* src = "fifo_synth.v:31" *)
  wire [2:0] _005_;
  (* src = "fifo_synth.v:31" *)
  wire _006_;
  (* src = "fifo_synth.v:31" *)
  wire _007_;
  (* src = "fifo_synth.v:31" *)
  wire _008_;
  (* src = "fifo_synth.v:31" *)
  wire _009_;
  (* src = "fifo_synth.v:31" *)
  wire [7:0] _010_;
  (* src = "fifo_synth.v:31" *)
  wire [2:0] _011_;
  (* src = "fifo_synth.v:31" *)
  wire [2:0] _012_;
  (* src = "fifo_synth.v:49" *)
  wire [31:0] _013_;
  (* src = "fifo_synth.v:63" *)
  wire [31:0] _014_;
  (* src = "fifo_synth.v:69" *)
  wire [31:0] _015_;
  wire _016_;
  wire _017_;
  wire _018_;
  wire _019_;
  wire _020_;
  wire _021_;
  wire _022_;
  wire _023_;
  wire _024_;
  wire _025_;
  wire _026_;
  wire _027_;
  wire _028_;
  wire _029_;
  wire _030_;
  wire _031_;
  wire _032_;
  wire [15:0] _033_;
  wire [7:0] _034_;
  wire _035_;
  wire _036_;
  wire [15:0] _037_;
  wire [7:0] _038_;
  wire [3:0] _039_;
  wire [1:0] _040_;
  wire _041_;
  wire [2:0] _042_;
  wire _043_;
  wire _044_;
  (* src = "fifo_synth.v:59" *)
  wire _045_;
  (* src = "fifo_synth.v:88" *)
  wire _046_;
  (* src = "fifo_synth.v:94" *)
  wire _047_;
  (* src = "fifo_synth.v:94" *)
  wire _048_;
  (* src = "fifo_synth.v:99" *)
  wire _049_;
  (* src = "fifo_synth.v:88" *)
  wire _050_;
  (* src = "fifo_synth.v:94" *)
  wire _051_;
  (* src = "fifo_synth.v:99" *)
  wire _052_;
  (* src = "fifo_synth.v:88" *)
  wire _053_;
  (* src = "fifo_synth.v:99" *)
  wire _054_;
  wire [7:0] _055_;
  wire [7:0] _056_;
  wire [7:0] _057_;
  wire [7:0] _058_;
  wire [7:0] _059_;
  wire [7:0] _060_;
  wire _061_;
  wire _062_;
  wire _063_;
  wire _064_;
  wire _065_;
  wire _066_;
  wire _067_;
  wire _068_;
  wire [7:0] _069_;
  wire [7:0] _070_;
  wire [7:0] _071_;
  wire [7:0] _072_;
  wire [7:0] _073_;
  wire [7:0] _074_;
  wire [7:0] _075_;
  wire [7:0] _076_;
  (* src = "fifo_synth.v:68" *)
  wire [7:0] _077_;
  wire _078_;
  wire _079_;
  wire _080_;
  wire _081_;
  wire _082_;
  wire _083_;
  wire _084_;
  wire _085_;
  wire _086_;
  wire _087_;
  wire _088_;
  wire _089_;
  wire _090_;
  wire _091_;
  wire _092_;
  wire _093_;
  wire _094_;
  wire _095_;
  wire _096_;
  wire _097_;
  wire _098_;
  wire _099_;
  wire _100_;
  wire _101_;
  wire _102_;
  wire _103_;
  wire _104_;
  wire _105_;
  wire _106_;
  wire _107_;
  wire [7:0] _108_;
  wire [7:0] _109_;
  wire [7:0] _110_;
  wire [2:0] _111_;
  wire [2:0] _112_;
  wire [2:0] _113_;
  wire [2:0] _114_;
  wire [2:0] _115_;
  wire [2:0] _116_;
  wire [2:0] _117_;
  wire [2:0] _118_;
  wire [2:0] _119_;
  wire [2:0] _120_;
  wire [2:0] _121_;
  wire [7:0] _122_;
  wire [7:0] _123_;
  (* src = "fifo_synth.v:83" *)
  wire [31:0] _124_;
  (* src = "fifo_synth.v:94" *)
  wire [31:0] _125_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _126_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _127_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _128_;
  (* src = "<techmap.v>:258" *)
  wire [2:0] _129_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [2:0] _130_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [2:0] _131_;
  wire [2:0] _132_;
  wire _133_;
  wire _134_;
  (* src = "<techmap.v>:258" *)
  wire [2:0] _135_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [2:0] _136_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [2:0] _137_;
  wire [2:0] _138_;
  wire _139_;
  wire _140_;
  (* src = "<techmap.v>:258" *)
  wire [31:0] _141_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _142_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _143_;
  wire [31:0] _144_;
  wire _145_;
  wire _146_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [2:0] _147_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [2:0] _148_;
  wire [2:0] _149_;
  wire _150_;
  wire _151_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _152_;
  wire _153_;
  wire _154_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _155_;
  wire [31:0] _156_;
  (* src = "<techmap.v>:260" *)
  wire [2:0] _157_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _158_;
  (* src = "<techmap.v>:260|<techmap.v>:229" *)
  wire _159_;
  (* src = "<techmap.v>:260" *)
  wire [2:0] _160_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _161_;
  (* src = "<techmap.v>:260|<techmap.v>:229" *)
  wire _162_;
  (* src = "<techmap.v>:260" *)
  wire [31:0] _163_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _164_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _165_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _166_;
  (* src = "<techmap.v>:260" *)
  wire [2:0] _167_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _168_;
  (* src = "<techmap.v>:260|<techmap.v>:229" *)
  wire _169_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _170_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _171_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _172_;
  (* src = "fifo_synth.v:3" *)
  input CLK;
  (* src = "fifo_synth.v:4" *)
  input ENB;
  (* src = "fifo_synth.v:5" *)
  input RST;
  (* src = "fifo_synth.v:15" *)
  output almostEmpty;
  reg almostEmpty;
  (* src = "fifo_synth.v:16" *)
  output almostFull;
  reg almostFull;
  reg [7:0] \buffer[0] ;
  reg [7:0] \buffer[1] ;
  reg [7:0] \buffer[2] ;
  reg [7:0] \buffer[3] ;
  reg [7:0] \buffer[4] ;
  reg [7:0] \buffer[5] ;
  reg [7:0] \buffer[6] ;
  reg [7:0] \buffer[7] ;
  (* src = "fifo_synth.v:27" *)
  reg [2:0] cantWr;
  (* src = "fifo_synth.v:19" *)
  output errorEmpty;
  reg errorEmpty;
  (* src = "fifo_synth.v:20" *)
  output errorFull;
  reg errorFull;
  (* src = "fifo_synth.v:13" *)
  input [7:0] inputData;
  (* src = "fifo_synth.v:17" *)
  output outEmpty;
  reg outEmpty;
  (* src = "fifo_synth.v:18" *)
  output outFull;
  reg outFull;
  (* src = "fifo_synth.v:22" *)
  output [7:0] outputData;
  reg [7:0] outputData;
  (* src = "fifo_synth.v:26" *)
  reg [2:0] ptrRd;
  (* src = "fifo_synth.v:25" *)
  reg [2:0] ptrWr;
  (* src = "fifo_synth.v:6" *)
  input sRead;
  (* src = "fifo_synth.v:7" *)
  input sWrite;
  (* src = "fifo_synth.v:10" *)
  input [2:0] umbEmpty;
  (* src = "fifo_synth.v:11" *)
  input [2:0] umbFull;
  assign _031_ = _014_[0] |(* src = "fifo_synth.v:59" *)  _042_[1];
  assign _043_ = _031_ |(* src = "fifo_synth.v:59" *)  _033_[1];
  assign _032_ = _014_[0] |(* src = "fifo_synth.v:79" *)  cantWr[1];
  assign _044_ = _032_ |(* src = "fifo_synth.v:79" *)  cantWr[2];
  assign _034_[0] = _033_[0] & _033_[1];
  assign _035_ = _131_[0] & _132_[1];
  assign _134_ = _035_ & _132_[2];
  assign _046_ = _133_ | _134_;
  assign _036_ = _137_[0] & _138_[1];
  assign _140_ = _036_ & _138_[2];
  assign _047_ = _139_ | _140_;
  assign _037_[0] = _143_[0] & _144_[1];
  assign _037_[1] = _144_[2] & _141_[31];
  assign _038_[0] = _037_[0] & _037_[1];
  assign _039_[0] = _038_[0] & _038_[7];
  assign _039_[3] = _038_[7] & _038_[7];
  assign _040_[0] = _039_[0] & _039_[3];
  assign _040_[1] = _039_[3] & _039_[3];
  assign _146_ = _040_[0] & _040_[1];
  assign _048_ = _145_ | _146_;
  assign _041_ = _148_[0] & _149_[1];
  assign _151_ = _041_ & _149_[2];
  assign _049_ = _150_ | _151_;
  assign _045_ = ~(* src = "fifo_synth.v:59" *) _043_;
  assign _050_ = _053_ &(* src = "fifo_synth.v:88" *)  _046_;
  assign _051_ = _047_ &(* src = "fifo_synth.v:94" *)  _048_;
  assign _052_ = _049_ &(* src = "fifo_synth.v:99" *)  _054_;
  assign _071_[0] = _063_ ? _001_[0] : \buffer[2] [0];
  assign _071_[1] = _063_ ? _001_[1] : \buffer[2] [1];
  assign _071_[2] = _063_ ? _001_[2] : \buffer[2] [2];
  assign _071_[3] = _063_ ? _001_[3] : \buffer[2] [3];
  assign _071_[4] = _063_ ? _001_[4] : \buffer[2] [4];
  assign _071_[5] = _063_ ? _001_[5] : \buffer[2] [5];
  assign _071_[6] = _063_ ? _001_[6] : \buffer[2] [6];
  assign _071_[7] = _063_ ? _001_[7] : \buffer[2] [7];
  assign _108_[7] = ENB ? (* src = "fifo_synth.v:46" *) sWrite : 1'b0;
  assign _002_[7] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _108_[7];
  assign _109_[0] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[0] : 1'bx;
  assign _109_[1] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[1] : 1'bx;
  assign _109_[2] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[2] : 1'bx;
  assign _109_[3] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[3] : 1'bx;
  assign _109_[4] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[4] : 1'bx;
  assign _109_[5] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[5] : 1'bx;
  assign _109_[6] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[6] : 1'bx;
  assign _109_[7] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[7] : 1'bx;
  assign _110_[0] = ENB ? (* src = "fifo_synth.v:46" *) _109_[0] : 1'bx;
  assign _110_[1] = ENB ? (* src = "fifo_synth.v:46" *) _109_[1] : 1'bx;
  assign _110_[2] = ENB ? (* src = "fifo_synth.v:46" *) _109_[2] : 1'bx;
  assign _110_[3] = ENB ? (* src = "fifo_synth.v:46" *) _109_[3] : 1'bx;
  assign _110_[4] = ENB ? (* src = "fifo_synth.v:46" *) _109_[4] : 1'bx;
  assign _110_[5] = ENB ? (* src = "fifo_synth.v:46" *) _109_[5] : 1'bx;
  assign _110_[6] = ENB ? (* src = "fifo_synth.v:46" *) _109_[6] : 1'bx;
  assign _110_[7] = ENB ? (* src = "fifo_synth.v:46" *) _109_[7] : 1'bx;
  assign _001_[0] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[0];
  assign _001_[1] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[1];
  assign _001_[2] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[2];
  assign _001_[3] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[3];
  assign _001_[4] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[4];
  assign _001_[5] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[5];
  assign _001_[6] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[6];
  assign _001_[7] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[7];
  assign _111_[0] = sWrite ? (* src = "fifo_synth.v:47" *) ptrWr[0] : 1'bx;
  assign _111_[1] = sWrite ? (* src = "fifo_synth.v:47" *) ptrWr[1] : 1'bx;
  assign _111_[2] = sWrite ? (* src = "fifo_synth.v:47" *) ptrWr[2] : 1'bx;
  assign _112_[0] = ENB ? (* src = "fifo_synth.v:46" *) _111_[0] : 1'bx;
  assign _112_[1] = ENB ? (* src = "fifo_synth.v:46" *) _111_[1] : 1'bx;
  assign _112_[2] = ENB ? (* src = "fifo_synth.v:46" *) _111_[2] : 1'bx;
  assign _070_[0] = _062_ ? _001_[0] : \buffer[1] [0];
  assign _070_[1] = _062_ ? _001_[1] : \buffer[1] [1];
  assign _070_[2] = _062_ ? _001_[2] : \buffer[1] [2];
  assign _070_[3] = _062_ ? _001_[3] : \buffer[1] [3];
  assign _070_[4] = _062_ ? _001_[4] : \buffer[1] [4];
  assign _070_[5] = _062_ ? _001_[5] : \buffer[1] [5];
  assign _070_[6] = _062_ ? _001_[6] : \buffer[1] [6];
  assign _070_[7] = _062_ ? _001_[7] : \buffer[1] [7];
  assign _000_[0] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _112_[0];
  assign _000_[1] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _112_[1];
  assign _000_[2] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _112_[2];
  assign _113_[0] = sRead ? (* src = "fifo_synth.v:51" *) cantWr[0] : _014_[0];
  assign _113_[1] = sRead ? (* src = "fifo_synth.v:51" *) cantWr[1] : _014_[1];
  assign _113_[2] = sRead ? (* src = "fifo_synth.v:51" *) cantWr[2] : _014_[2];
  assign _114_[0] = sWrite ? (* src = "fifo_synth.v:47" *) _113_[0] : cantWr[0];
  assign _114_[1] = sWrite ? (* src = "fifo_synth.v:47" *) _113_[1] : cantWr[1];
  assign _114_[2] = sWrite ? (* src = "fifo_synth.v:47" *) _113_[2] : cantWr[2];
  assign _115_[0] = sWrite ? (* src = "fifo_synth.v:71" *) _114_[0] : _014_[0];
  assign _115_[1] = sWrite ? (* src = "fifo_synth.v:71" *) _114_[1] : _124_[1];
  assign _115_[2] = sWrite ? (* src = "fifo_synth.v:71" *) _114_[2] : _124_[2];
  assign _116_[0] = sRead ? (* src = "fifo_synth.v:67" *) _115_[0] : _114_[0];
  assign _116_[1] = sRead ? (* src = "fifo_synth.v:67" *) _115_[1] : _114_[1];
  assign _116_[2] = sRead ? (* src = "fifo_synth.v:67" *) _115_[2] : _114_[2];
  assign _117_[0] = ENB ? (* src = "fifo_synth.v:46" *) _116_[0] : cantWr[0];
  assign _117_[1] = ENB ? (* src = "fifo_synth.v:46" *) _116_[1] : cantWr[1];
  assign _117_[2] = ENB ? (* src = "fifo_synth.v:46" *) _116_[2] : cantWr[2];
  assign _069_[0] = _061_ ? _001_[0] : \buffer[0] [0];
  assign _069_[1] = _061_ ? _001_[1] : \buffer[0] [1];
  assign _069_[2] = _061_ ? _001_[2] : \buffer[0] [2];
  assign _069_[3] = _061_ ? _001_[3] : \buffer[0] [3];
  assign _069_[4] = _061_ ? _001_[4] : \buffer[0] [4];
  assign _069_[5] = _061_ ? _001_[5] : \buffer[0] [5];
  assign _069_[6] = _061_ ? _001_[6] : \buffer[0] [6];
  assign _069_[7] = _061_ ? _001_[7] : \buffer[0] [7];
  assign _005_[0] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _117_[0];
  assign _005_[1] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _117_[1];
  assign _005_[2] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _117_[2];
  assign _118_[0] = sRead ? (* src = "fifo_synth.v:67" *) _015_[0] : ptrRd[0];
  assign _118_[1] = sRead ? (* src = "fifo_synth.v:67" *) _015_[1] : ptrRd[1];
  assign _118_[2] = sRead ? (* src = "fifo_synth.v:67" *) _015_[2] : ptrRd[2];
  assign _119_[0] = ENB ? (* src = "fifo_synth.v:46" *) _118_[0] : ptrRd[0];
  assign _119_[1] = ENB ? (* src = "fifo_synth.v:46" *) _118_[1] : ptrRd[1];
  assign _119_[2] = ENB ? (* src = "fifo_synth.v:46" *) _118_[2] : ptrRd[2];
  assign _011_[0] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _119_[0];
  assign _011_[1] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _119_[1];
  assign _011_[2] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _119_[2];
  assign _120_[0] = sWrite ? (* src = "fifo_synth.v:47" *) _013_[0] : ptrWr[0];
  assign _120_[1] = sWrite ? (* src = "fifo_synth.v:47" *) _013_[1] : ptrWr[1];
  assign _120_[2] = sWrite ? (* src = "fifo_synth.v:47" *) _013_[2] : ptrWr[2];
  assign _121_[0] = ENB ? (* src = "fifo_synth.v:46" *) _120_[0] : ptrWr[0];
  assign _121_[1] = ENB ? (* src = "fifo_synth.v:46" *) _120_[1] : ptrWr[1];
  assign _121_[2] = ENB ? (* src = "fifo_synth.v:46" *) _120_[2] : ptrWr[2];
  assign _012_[0] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _121_[0];
  assign _012_[1] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _121_[1];
  assign _012_[2] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _121_[2];
  assign _122_[0] = sRead ? (* src = "fifo_synth.v:67" *) _077_[0] : outputData[0];
  assign _122_[1] = sRead ? (* src = "fifo_synth.v:67" *) _077_[1] : outputData[1];
  assign _122_[2] = sRead ? (* src = "fifo_synth.v:67" *) _077_[2] : outputData[2];
  assign _122_[3] = sRead ? (* src = "fifo_synth.v:67" *) _077_[3] : outputData[3];
  assign _122_[4] = sRead ? (* src = "fifo_synth.v:67" *) _077_[4] : outputData[4];
  assign _122_[5] = sRead ? (* src = "fifo_synth.v:67" *) _077_[5] : outputData[5];
  assign _122_[6] = sRead ? (* src = "fifo_synth.v:67" *) _077_[6] : outputData[6];
  assign _122_[7] = sRead ? (* src = "fifo_synth.v:67" *) _077_[7] : outputData[7];
  assign _123_[0] = ENB ? (* src = "fifo_synth.v:46" *) _122_[0] : outputData[0];
  assign _123_[1] = ENB ? (* src = "fifo_synth.v:46" *) _122_[1] : outputData[1];
  assign _123_[2] = ENB ? (* src = "fifo_synth.v:46" *) _122_[2] : outputData[2];
  assign _123_[3] = ENB ? (* src = "fifo_synth.v:46" *) _122_[3] : outputData[3];
  assign _123_[4] = ENB ? (* src = "fifo_synth.v:46" *) _122_[4] : outputData[4];
  assign _123_[5] = ENB ? (* src = "fifo_synth.v:46" *) _122_[5] : outputData[5];
  assign _123_[6] = ENB ? (* src = "fifo_synth.v:46" *) _122_[6] : outputData[6];
  assign _123_[7] = ENB ? (* src = "fifo_synth.v:46" *) _122_[7] : outputData[7];
  assign _010_[0] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[0];
  assign _010_[1] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[1];
  assign _010_[2] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[2];
  assign _010_[3] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[3];
  assign _010_[4] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[4];
  assign _010_[5] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[5];
  assign _010_[6] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[6];
  assign _010_[7] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[7];
  assign _078_ = outFull ? (* src = "fifo_synth.v:55" *) 1'b1 : errorFull;
  assign _079_ = sRead ? (* src = "fifo_synth.v:51" *) errorFull : _078_;
  assign _060_[0] = ptrRd[0] ? \buffer[7] [0] : \buffer[6] [0];
  assign _060_[1] = ptrRd[0] ? \buffer[7] [1] : \buffer[6] [1];
  assign _060_[2] = ptrRd[0] ? \buffer[7] [2] : \buffer[6] [2];
  assign _060_[3] = ptrRd[0] ? \buffer[7] [3] : \buffer[6] [3];
  assign _060_[4] = ptrRd[0] ? \buffer[7] [4] : \buffer[6] [4];
  assign _060_[5] = ptrRd[0] ? \buffer[7] [5] : \buffer[6] [5];
  assign _060_[6] = ptrRd[0] ? \buffer[7] [6] : \buffer[6] [6];
  assign _060_[7] = ptrRd[0] ? \buffer[7] [7] : \buffer[6] [7];
  assign _080_ = sWrite ? (* src = "fifo_synth.v:47" *) _079_ : errorFull;
  assign _081_ = ENB ? (* src = "fifo_synth.v:46" *) _080_ : errorFull;
  assign _059_[0] = ptrRd[0] ? \buffer[5] [0] : \buffer[4] [0];
  assign _059_[1] = ptrRd[0] ? \buffer[5] [1] : \buffer[4] [1];
  assign _059_[2] = ptrRd[0] ? \buffer[5] [2] : \buffer[4] [2];
  assign _059_[3] = ptrRd[0] ? \buffer[5] [3] : \buffer[4] [3];
  assign _059_[4] = ptrRd[0] ? \buffer[5] [4] : \buffer[4] [4];
  assign _059_[5] = ptrRd[0] ? \buffer[5] [5] : \buffer[4] [5];
  assign _059_[6] = ptrRd[0] ? \buffer[5] [6] : \buffer[4] [6];
  assign _059_[7] = ptrRd[0] ? \buffer[5] [7] : \buffer[4] [7];
  assign _007_ = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _081_;
  assign _082_ = outEmpty ? (* src = "fifo_synth.v:75" *) 1'b1 : errorEmpty;
  assign _083_ = sWrite ? (* src = "fifo_synth.v:71" *) errorEmpty : _082_;
  assign _058_[0] = ptrRd[0] ? \buffer[3] [0] : \buffer[2] [0];
  assign _058_[1] = ptrRd[0] ? \buffer[3] [1] : \buffer[2] [1];
  assign _058_[2] = ptrRd[0] ? \buffer[3] [2] : \buffer[2] [2];
  assign _058_[3] = ptrRd[0] ? \buffer[3] [3] : \buffer[2] [3];
  assign _058_[4] = ptrRd[0] ? \buffer[3] [4] : \buffer[2] [4];
  assign _058_[5] = ptrRd[0] ? \buffer[3] [5] : \buffer[2] [5];
  assign _058_[6] = ptrRd[0] ? \buffer[3] [6] : \buffer[2] [6];
  assign _058_[7] = ptrRd[0] ? \buffer[3] [7] : \buffer[2] [7];
  assign _084_ = sRead ? (* src = "fifo_synth.v:67" *) _083_ : errorEmpty;
  assign _085_ = ENB ? (* src = "fifo_synth.v:46" *) _084_ : errorEmpty;
  assign _057_[0] = ptrRd[0] ? \buffer[1] [0] : \buffer[0] [0];
  assign _057_[1] = ptrRd[0] ? \buffer[1] [1] : \buffer[0] [1];
  assign _057_[2] = ptrRd[0] ? \buffer[1] [2] : \buffer[0] [2];
  assign _057_[3] = ptrRd[0] ? \buffer[1] [3] : \buffer[0] [3];
  assign _057_[4] = ptrRd[0] ? \buffer[1] [4] : \buffer[0] [4];
  assign _057_[5] = ptrRd[0] ? \buffer[1] [5] : \buffer[0] [5];
  assign _057_[6] = ptrRd[0] ? \buffer[1] [6] : \buffer[0] [6];
  assign _057_[7] = ptrRd[0] ? \buffer[1] [7] : \buffer[0] [7];
  assign _006_ = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _085_;
  assign _086_ = outFull ? (* src = "fifo_synth.v:55" *) 1'b1 : _045_;
  assign _056_[0] = ptrRd[1] ? _060_[0] : _059_[0];
  assign _056_[1] = ptrRd[1] ? _060_[1] : _059_[1];
  assign _056_[2] = ptrRd[1] ? _060_[2] : _059_[2];
  assign _056_[3] = ptrRd[1] ? _060_[3] : _059_[3];
  assign _056_[4] = ptrRd[1] ? _060_[4] : _059_[4];
  assign _056_[5] = ptrRd[1] ? _060_[5] : _059_[5];
  assign _056_[6] = ptrRd[1] ? _060_[6] : _059_[6];
  assign _056_[7] = ptrRd[1] ? _060_[7] : _059_[7];
  assign _087_ = sRead ? (* src = "fifo_synth.v:51" *) outFull : _086_;
  assign _088_ = sWrite ? (* src = "fifo_synth.v:47" *) _087_ : outFull;
  assign _089_ = outFull ? (* src = "fifo_synth.v:72" *) 1'b0 : _088_;
  assign _055_[0] = ptrRd[1] ? _058_[0] : _057_[0];
  assign _055_[1] = ptrRd[1] ? _058_[1] : _057_[1];
  assign _055_[2] = ptrRd[1] ? _058_[2] : _057_[2];
  assign _055_[3] = ptrRd[1] ? _058_[3] : _057_[3];
  assign _055_[4] = ptrRd[1] ? _058_[4] : _057_[4];
  assign _055_[5] = ptrRd[1] ? _058_[5] : _057_[5];
  assign _055_[6] = ptrRd[1] ? _058_[6] : _057_[6];
  assign _055_[7] = ptrRd[1] ? _058_[7] : _057_[7];
  assign _090_ = sWrite ? (* src = "fifo_synth.v:71" *) _088_ : _089_;
  assign _091_ = sRead ? (* src = "fifo_synth.v:67" *) _090_ : _088_;
  assign _092_ = ENB ? (* src = "fifo_synth.v:46" *) _091_ : outFull;
  assign _077_[0] = ptrRd[2] ? _056_[0] : _055_[0];
  assign _077_[1] = ptrRd[2] ? _056_[1] : _055_[1];
  assign _077_[2] = ptrRd[2] ? _056_[2] : _055_[2];
  assign _077_[3] = ptrRd[2] ? _056_[3] : _055_[3];
  assign _077_[4] = ptrRd[2] ? _056_[4] : _055_[4];
  assign _077_[5] = ptrRd[2] ? _056_[5] : _055_[5];
  assign _077_[6] = ptrRd[2] ? _056_[6] : _055_[6];
  assign _077_[7] = ptrRd[2] ? _056_[7] : _055_[7];
  assign _093_ = _052_ ? (* src = "fifo_synth.v:99" *) 1'b0 : _092_;
  assign _009_ = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _093_;
  assign _094_ = sRead ? (* src = "fifo_synth.v:51" *) outEmpty : 1'b0;
  assign _095_ = sWrite ? (* src = "fifo_synth.v:47" *) _094_ : outEmpty;
  assign _096_ = _044_ ? (* src = "fifo_synth.v:79" *) _095_ : 1'b1;
  assign _097_ = outEmpty ? (* src = "fifo_synth.v:75" *) _095_ : _096_;
  assign _098_ = sWrite ? (* src = "fifo_synth.v:71" *) _095_ : _097_;
  assign _099_ = sRead ? (* src = "fifo_synth.v:67" *) _098_ : _095_;
  assign _100_ = ENB ? (* src = "fifo_synth.v:46" *) _099_ : outEmpty;
  assign _101_ = _050_ ? (* src = "fifo_synth.v:88" *) 1'b0 : _100_;
  assign _008_ = RST ? (* src = "fifo_synth.v:32" *) 1'b1 : _101_;
  assign _102_ = _050_ ? (* src = "fifo_synth.v:88" *) 1'b0 : almostFull;
  assign _103_ = _051_ ? (* src = "fifo_synth.v:94" *) 1'b0 : _102_;
  assign _104_ = _052_ ? (* src = "fifo_synth.v:99" *) 1'b1 : _103_;
  assign _004_ = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _104_;
  assign _105_ = _050_ ? (* src = "fifo_synth.v:88" *) 1'b1 : almostEmpty;
  assign _106_ = _051_ ? (* src = "fifo_synth.v:94" *) 1'b0 : _105_;
  assign _107_ = _052_ ? (* src = "fifo_synth.v:99" *) 1'b0 : _106_;
  assign _003_ = RST ? (* src = "fifo_synth.v:32" *) 1'b1 : _107_;
  assign _072_[0] = _064_ ? _001_[0] : \buffer[3] [0];
  assign _072_[1] = _064_ ? _001_[1] : \buffer[3] [1];
  assign _072_[2] = _064_ ? _001_[2] : \buffer[3] [2];
  assign _072_[3] = _064_ ? _001_[3] : \buffer[3] [3];
  assign _072_[4] = _064_ ? _001_[4] : \buffer[3] [4];
  assign _072_[5] = _064_ ? _001_[5] : \buffer[3] [5];
  assign _072_[6] = _064_ ? _001_[6] : \buffer[3] [6];
  assign _072_[7] = _064_ ? _001_[7] : \buffer[3] [7];
  assign _073_[0] = _065_ ? _001_[0] : \buffer[4] [0];
  assign _073_[1] = _065_ ? _001_[1] : \buffer[4] [1];
  assign _073_[2] = _065_ ? _001_[2] : \buffer[4] [2];
  assign _073_[3] = _065_ ? _001_[3] : \buffer[4] [3];
  assign _073_[4] = _065_ ? _001_[4] : \buffer[4] [4];
  assign _073_[5] = _065_ ? _001_[5] : \buffer[4] [5];
  assign _073_[6] = _065_ ? _001_[6] : \buffer[4] [6];
  assign _073_[7] = _065_ ? _001_[7] : \buffer[4] [7];
  assign _074_[0] = _066_ ? _001_[0] : \buffer[5] [0];
  assign _074_[1] = _066_ ? _001_[1] : \buffer[5] [1];
  assign _074_[2] = _066_ ? _001_[2] : \buffer[5] [2];
  assign _074_[3] = _066_ ? _001_[3] : \buffer[5] [3];
  assign _074_[4] = _066_ ? _001_[4] : \buffer[5] [4];
  assign _074_[5] = _066_ ? _001_[5] : \buffer[5] [5];
  assign _074_[6] = _066_ ? _001_[6] : \buffer[5] [6];
  assign _074_[7] = _066_ ? _001_[7] : \buffer[5] [7];
  assign _075_[0] = _067_ ? _001_[0] : \buffer[6] [0];
  assign _075_[1] = _067_ ? _001_[1] : \buffer[6] [1];
  assign _075_[2] = _067_ ? _001_[2] : \buffer[6] [2];
  assign _075_[3] = _067_ ? _001_[3] : \buffer[6] [3];
  assign _075_[4] = _067_ ? _001_[4] : \buffer[6] [4];
  assign _075_[5] = _067_ ? _001_[5] : \buffer[6] [5];
  assign _075_[6] = _067_ ? _001_[6] : \buffer[6] [6];
  assign _075_[7] = _067_ ? _001_[7] : \buffer[6] [7];
  assign _076_[0] = _068_ ? _001_[0] : \buffer[7] [0];
  assign _076_[1] = _068_ ? _001_[1] : \buffer[7] [1];
  assign _076_[2] = _068_ ? _001_[2] : \buffer[7] [2];
  assign _076_[3] = _068_ ? _001_[3] : \buffer[7] [3];
  assign _076_[4] = _068_ ? _001_[4] : \buffer[7] [4];
  assign _076_[5] = _068_ ? _001_[5] : \buffer[7] [5];
  assign _076_[6] = _068_ ? _001_[6] : \buffer[7] [6];
  assign _076_[7] = _068_ ? _001_[7] : \buffer[7] [7];
  assign _129_[0] = ~(* src = "<techmap.v>:258" *) umbEmpty[0];
  assign _129_[1] = ~(* src = "<techmap.v>:258" *) umbEmpty[1];
  assign _129_[2] = ~(* src = "<techmap.v>:258" *) umbEmpty[2];
  assign _141_[0] = ~(* src = "<techmap.v>:258" *) _125_[0];
  assign _141_[1] = ~(* src = "<techmap.v>:258" *) _125_[1];
  assign _141_[2] = ~(* src = "<techmap.v>:258" *) _125_[2];
  assign _141_[31] = ~(* src = "<techmap.v>:258" *) _125_[31];
  assign _135_[0] = ~(* src = "<techmap.v>:258" *) cantWr[0];
  assign _135_[1] = ~(* src = "<techmap.v>:258" *) cantWr[1];
  assign _135_[2] = ~(* src = "<techmap.v>:258" *) cantWr[2];
  assign _030_ = ~_000_[2];
  assign _029_ = ~_000_[1];
  assign _028_ = ~_000_[0];
  assign _153_ = ~_152_[31];
  assign _053_ = ~_154_;
  assign _133_ = ~_130_[2];
  assign _139_ = ~_136_[2];
  assign _145_ = ~_142_[31];
  assign _150_ = ~_147_[2];
  assign _054_ = ~_014_[3];
  always @(posedge CLK)
      \buffer[0] [0] <= _069_[0];
  always @(posedge CLK)
      \buffer[0] [1] <= _069_[1];
  always @(posedge CLK)
      \buffer[0] [2] <= _069_[2];
  always @(posedge CLK)
      \buffer[0] [3] <= _069_[3];
  always @(posedge CLK)
      \buffer[0] [4] <= _069_[4];
  always @(posedge CLK)
      \buffer[0] [5] <= _069_[5];
  always @(posedge CLK)
      \buffer[0] [6] <= _069_[6];
  always @(posedge CLK)
      \buffer[0] [7] <= _069_[7];
  always @(posedge CLK)
      \buffer[1] [0] <= _070_[0];
  always @(posedge CLK)
      \buffer[1] [1] <= _070_[1];
  always @(posedge CLK)
      \buffer[1] [2] <= _070_[2];
  always @(posedge CLK)
      \buffer[1] [3] <= _070_[3];
  always @(posedge CLK)
      \buffer[1] [4] <= _070_[4];
  always @(posedge CLK)
      \buffer[1] [5] <= _070_[5];
  always @(posedge CLK)
      \buffer[1] [6] <= _070_[6];
  always @(posedge CLK)
      \buffer[1] [7] <= _070_[7];
  always @(posedge CLK)
      ptrRd[0] <= _011_[0];
  always @(posedge CLK)
      ptrRd[1] <= _011_[1];
  always @(posedge CLK)
      ptrRd[2] <= _011_[2];
  always @(posedge CLK)
      \buffer[7] [0] <= _076_[0];
  always @(posedge CLK)
      \buffer[7] [1] <= _076_[1];
  always @(posedge CLK)
      \buffer[7] [2] <= _076_[2];
  always @(posedge CLK)
      \buffer[7] [3] <= _076_[3];
  always @(posedge CLK)
      \buffer[7] [4] <= _076_[4];
  always @(posedge CLK)
      \buffer[7] [5] <= _076_[5];
  always @(posedge CLK)
      \buffer[7] [6] <= _076_[6];
  always @(posedge CLK)
      \buffer[7] [7] <= _076_[7];
  always @(posedge CLK)
      \buffer[6] [0] <= _075_[0];
  always @(posedge CLK)
      \buffer[6] [1] <= _075_[1];
  always @(posedge CLK)
      \buffer[6] [2] <= _075_[2];
  always @(posedge CLK)
      \buffer[6] [3] <= _075_[3];
  always @(posedge CLK)
      \buffer[6] [4] <= _075_[4];
  always @(posedge CLK)
      \buffer[6] [5] <= _075_[5];
  always @(posedge CLK)
      \buffer[6] [6] <= _075_[6];
  always @(posedge CLK)
      \buffer[6] [7] <= _075_[7];
  always @(posedge CLK)
      \buffer[5] [0] <= _074_[0];
  always @(posedge CLK)
      \buffer[5] [1] <= _074_[1];
  always @(posedge CLK)
      \buffer[5] [2] <= _074_[2];
  always @(posedge CLK)
      \buffer[5] [3] <= _074_[3];
  always @(posedge CLK)
      \buffer[5] [4] <= _074_[4];
  always @(posedge CLK)
      \buffer[5] [5] <= _074_[5];
  always @(posedge CLK)
      \buffer[5] [6] <= _074_[6];
  always @(posedge CLK)
      \buffer[5] [7] <= _074_[7];
  always @(posedge CLK)
      \buffer[4] [0] <= _073_[0];
  always @(posedge CLK)
      \buffer[4] [1] <= _073_[1];
  always @(posedge CLK)
      \buffer[4] [2] <= _073_[2];
  always @(posedge CLK)
      \buffer[4] [3] <= _073_[3];
  always @(posedge CLK)
      \buffer[4] [4] <= _073_[4];
  always @(posedge CLK)
      \buffer[4] [5] <= _073_[5];
  always @(posedge CLK)
      \buffer[4] [6] <= _073_[6];
  always @(posedge CLK)
      \buffer[4] [7] <= _073_[7];
  always @(posedge CLK)
      \buffer[3] [0] <= _072_[0];
  always @(posedge CLK)
      \buffer[3] [1] <= _072_[1];
  always @(posedge CLK)
      \buffer[3] [2] <= _072_[2];
  always @(posedge CLK)
      \buffer[3] [3] <= _072_[3];
  always @(posedge CLK)
      \buffer[3] [4] <= _072_[4];
  always @(posedge CLK)
      \buffer[3] [5] <= _072_[5];
  always @(posedge CLK)
      \buffer[3] [6] <= _072_[6];
  always @(posedge CLK)
      \buffer[3] [7] <= _072_[7];
  always @(posedge CLK)
      \buffer[2] [0] <= _071_[0];
  always @(posedge CLK)
      \buffer[2] [1] <= _071_[1];
  always @(posedge CLK)
      \buffer[2] [2] <= _071_[2];
  always @(posedge CLK)
      \buffer[2] [3] <= _071_[3];
  always @(posedge CLK)
      \buffer[2] [4] <= _071_[4];
  always @(posedge CLK)
      \buffer[2] [5] <= _071_[5];
  always @(posedge CLK)
      \buffer[2] [6] <= _071_[6];
  always @(posedge CLK)
      \buffer[2] [7] <= _071_[7];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      almostFull <= _004_;
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      almostEmpty <= _003_;
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outEmpty <= _008_;
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outFull <= _009_;
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      errorEmpty <= _006_;
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      errorFull <= _007_;
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[0] <= _010_[0];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[1] <= _010_[1];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[2] <= _010_[2];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[3] <= _010_[3];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[4] <= _010_[4];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[5] <= _010_[5];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[6] <= _010_[6];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[7] <= _010_[7];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      ptrWr[0] <= _012_[0];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      ptrWr[1] <= _012_[1];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      ptrWr[2] <= _012_[2];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      cantWr[0] <= _005_[0];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      cantWr[1] <= _005_[1];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      cantWr[2] <= _005_[2];
  assign _014_[1] = cantWr[1] ^(* src = "<techmap.v>:263" *)  cantWr[0];
  assign _015_[0] = ptrRd[0] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign _015_[1] = ptrRd[1] ^(* src = "<techmap.v>:263" *)  ptrRd[0];
  assign _015_[2] = ptrRd[2] ^(* src = "<techmap.v>:263" *)  _128_[1];
  assign _042_[1] = cantWr[1] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign _033_[1] = cantWr[2] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign _124_[1] = _042_[1] ^(* src = "<techmap.v>:263" *)  cantWr[0];
  assign _124_[2] = _033_[1] ^(* src = "<techmap.v>:263" *)  _152_[1];
  assign _131_[0] = cantWr[0] ^(* src = "<techmap.v>:262" *)  _129_[0];
  assign _132_[1] = cantWr[1] ^(* src = "<techmap.v>:262" *)  _129_[1];
  assign _132_[2] = cantWr[2] ^(* src = "<techmap.v>:262" *)  _129_[2];
  assign _157_[0] = cantWr[0] &(* src = "<techmap.v>:260" *)  _129_[0];
  assign _157_[1] = cantWr[1] &(* src = "<techmap.v>:260" *)  _129_[1];
  assign _157_[2] = cantWr[2] &(* src = "<techmap.v>:260" *)  _129_[2];
  assign _137_[0] = umbEmpty[0] ^(* src = "<techmap.v>:262" *)  _135_[0];
  assign _138_[1] = umbEmpty[1] ^(* src = "<techmap.v>:262" *)  _135_[1];
  assign _138_[2] = umbEmpty[2] ^(* src = "<techmap.v>:262" *)  _135_[2];
  assign _160_[0] = umbEmpty[0] &(* src = "<techmap.v>:260" *)  _135_[0];
  assign _160_[1] = umbEmpty[1] &(* src = "<techmap.v>:260" *)  _135_[1];
  assign _160_[2] = umbEmpty[2] &(* src = "<techmap.v>:260" *)  _135_[2];
  assign _156_[1] = umbFull[1] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign _156_[2] = umbFull[2] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign _125_[0] = umbFull[0] ^(* src = "<techmap.v>:263" *)  1'b1;
  assign _125_[1] = _156_[1] ^(* src = "<techmap.v>:263" *)  umbFull[0];
  assign _125_[2] = _156_[2] ^(* src = "<techmap.v>:263" *)  _155_[1];
  assign _125_[31] = 1'b1 ^(* src = "<techmap.v>:263" *)  _155_[31];
  assign _143_[0] = cantWr[0] ^(* src = "<techmap.v>:262" *)  _141_[0];
  assign _144_[1] = cantWr[1] ^(* src = "<techmap.v>:262" *)  _141_[1];
  assign _144_[2] = cantWr[2] ^(* src = "<techmap.v>:262" *)  _141_[2];
  assign _163_[0] = cantWr[0] &(* src = "<techmap.v>:260" *)  _141_[0];
  assign _163_[1] = cantWr[1] &(* src = "<techmap.v>:260" *)  _141_[1];
  assign _163_[2] = cantWr[2] &(* src = "<techmap.v>:260" *)  _141_[2];
  assign _148_[0] = umbFull[0] ^(* src = "<techmap.v>:262" *)  _135_[0];
  assign _149_[1] = umbFull[1] ^(* src = "<techmap.v>:262" *)  _135_[1];
  assign _149_[2] = umbFull[2] ^(* src = "<techmap.v>:262" *)  _135_[2];
  assign _167_[0] = umbFull[0] &(* src = "<techmap.v>:260" *)  _135_[0];
  assign _167_[1] = umbFull[1] &(* src = "<techmap.v>:260" *)  _135_[1];
  assign _167_[2] = umbFull[2] &(* src = "<techmap.v>:260" *)  _135_[2];
  assign _014_[0] = cantWr[0] ^(* src = "<techmap.v>:263" *)  1'b1;
  assign _014_[2] = cantWr[2] ^(* src = "<techmap.v>:263" *)  _127_[1];
  assign _126_[1] = ptrWr[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  ptrWr[0];
  assign _136_[0] = _160_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *)  _137_[0];
  assign _162_ = _138_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _136_[1];
  assign _161_ = _138_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _136_[0];
  assign _130_[2] = _157_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *)  _159_;
  assign _130_[1] = _157_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _158_;
  assign _130_[0] = _157_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *)  _131_[0];
  assign _159_ = _132_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _130_[1];
  assign _158_ = _132_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _130_[0];
  assign _128_[1] = ptrRd[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  ptrRd[0];
  assign _170_ = _033_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _152_[1];
  assign _033_[0] = _042_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  cantWr[0];
  assign _152_[1] = cantWr[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _033_[0];
  assign _152_[31] = cantWr[2] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _170_;
  assign _136_[1] = _160_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _161_;
  assign _136_[2] = _160_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *)  _162_;
  assign _171_ = _156_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  umbFull[0];
  assign _172_ = _156_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _155_[1];
  assign _155_[1] = umbFull[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _171_;
  assign _155_[31] = umbFull[2] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _172_;
  assign _164_ = _144_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _142_[0];
  assign _165_ = _141_[31] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _163_[2];
  assign _166_ = _037_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _142_[1];
  assign _142_[7] = _038_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _142_[3];
  assign _142_[15] = _039_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _142_[7];
  assign _142_[31] = _040_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _142_[15];
  assign _037_[15] = _141_[31] &(* src = "<techmap.v>:260|<techmap.v>:222" *)  _141_[31];
  assign _038_[7] = _037_[15] &(* src = "<techmap.v>:260|<techmap.v>:222" *)  _037_[15];
  assign _142_[0] = _163_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *)  _143_[0];
  assign _142_[1] = _163_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _164_;
  assign _142_[3] = _165_ |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _166_;
  assign _168_ = _149_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _147_[0];
  assign _169_ = _149_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _147_[1];
  assign _147_[0] = _167_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *)  _148_[0];
  assign _147_[1] = _167_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _168_;
  assign _147_[2] = _167_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *)  _169_;
  assign _127_[1] = cantWr[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  cantWr[0];
  assign _014_[3] = cantWr[2] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _127_[1];
  assign _064_ = _021_ & _002_[7];
  assign _021_ = _000_[0] & _019_;
  assign _063_ = _020_ & _002_[7];
  assign _020_ = _028_ & _019_;
  assign _019_ = _000_[1] & _030_;
  assign _062_ = _018_ & _002_[7];
  assign _018_ = _000_[0] & _016_;
  assign _061_ = _017_ & _002_[7];
  assign _017_ = _028_ & _016_;
  assign _016_ = _029_ & _030_;
  assign _022_ = _029_ & _000_[2];
  assign _023_ = _028_ & _022_;
  assign _065_ = _023_ & _002_[7];
  assign _024_ = _000_[0] & _022_;
  assign _066_ = _024_ & _002_[7];
  assign _025_ = _000_[1] & _000_[2];
  assign _026_ = _028_ & _025_;
  assign _067_ = _026_ & _002_[7];
  assign _027_ = _000_[0] & _025_;
  assign _068_ = _027_ & _002_[7];
  assign _154_ = _153_ | _034_[0];
  assign _013_[0] = ptrWr[0] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign _013_[1] = ptrWr[1] ^(* src = "<techmap.v>:263" *)  ptrWr[0];
  assign _013_[2] = ptrWr[2] ^(* src = "<techmap.v>:263" *)  _126_[1];
endmodule
module fifo_synth(CLK, ENB, RST, sRead, sWrite, umbEmpty, umbFull, inputData, almostEmpty, almostFull, outEmpty, outFull, errorEmpty, errorFull, outputData);

  (* src = "fifo_synth.v:31" *)
  wire [2:0] _000_;
  (* src = "fifo_synth.v:31" *)
  wire [7:0] _001_;
  (* src = "fifo_synth.v:31" *)
  wire [7:0] _002_;
  (* src = "fifo_synth.v:31" *)
  wire _003_;
  (* src = "fifo_synth.v:31" *)
  wire _004_;
  (* src = "fifo_synth.v:31" *)
  wire [2:0] _005_;
  (* src = "fifo_synth.v:31" *)
  wire _006_;
  (* src = "fifo_synth.v:31" *)
  wire _007_;
  (* src = "fifo_synth.v:31" *)
  wire _008_;
  (* src = "fifo_synth.v:31" *)
  wire _009_;
  (* src = "fifo_synth.v:31" *)
  wire [7:0] _010_;
  (* src = "fifo_synth.v:31" *)
  wire [2:0] _011_;
  (* src = "fifo_synth.v:31" *)
  wire [2:0] _012_;
  (* src = "fifo_synth.v:49" *)
  wire [31:0] _013_;
  (* src = "fifo_synth.v:63" *)
  wire [31:0] _014_;
  (* src = "fifo_synth.v:69" *)
  wire [31:0] _015_;
  wire _016_;
  wire _017_;
  wire _018_;
  wire _019_;
  wire _020_;
  wire _021_;
  wire _022_;
  wire _023_;
  wire _024_;
  wire _025_;
  wire _026_;
  wire _027_;
  wire _028_;
  wire _029_;
  wire _030_;
  wire _031_;
  wire _032_;
  wire [15:0] _033_;
  wire [7:0] _034_;
  wire _035_;
  wire _036_;
  wire [15:0] _037_;
  wire [7:0] _038_;
  wire [3:0] _039_;
  wire [1:0] _040_;
  wire _041_;
  wire [2:0] _042_;
  wire _043_;
  wire _044_;
  (* src = "fifo_synth.v:59" *)
  wire _045_;
  (* src = "fifo_synth.v:88" *)
  wire _046_;
  (* src = "fifo_synth.v:94" *)
  wire _047_;
  (* src = "fifo_synth.v:94" *)
  wire _048_;
  (* src = "fifo_synth.v:99" *)
  wire _049_;
  (* src = "fifo_synth.v:88" *)
  wire _050_;
  (* src = "fifo_synth.v:94" *)
  wire _051_;
  (* src = "fifo_synth.v:99" *)
  wire _052_;
  (* src = "fifo_synth.v:88" *)
  wire _053_;
  (* src = "fifo_synth.v:99" *)
  wire _054_;
  wire [7:0] _055_;
  wire [7:0] _056_;
  wire [7:0] _057_;
  wire [7:0] _058_;
  wire [7:0] _059_;
  wire [7:0] _060_;
  wire _061_;
  wire _062_;
  wire _063_;
  wire _064_;
  wire _065_;
  wire _066_;
  wire _067_;
  wire _068_;
  wire [7:0] _069_;
  wire [7:0] _070_;
  wire [7:0] _071_;
  wire [7:0] _072_;
  wire [7:0] _073_;
  wire [7:0] _074_;
  wire [7:0] _075_;
  wire [7:0] _076_;
  (* src = "fifo_synth.v:68" *)
  wire [7:0] _077_;
  wire _078_;
  wire _079_;
  wire _080_;
  wire _081_;
  wire _082_;
  wire _083_;
  wire _084_;
  wire _085_;
  wire _086_;
  wire _087_;
  wire _088_;
  wire _089_;
  wire _090_;
  wire _091_;
  wire _092_;
  wire _093_;
  wire _094_;
  wire _095_;
  wire _096_;
  wire _097_;
  wire _098_;
  wire _099_;
  wire _100_;
  wire _101_;
  wire _102_;
  wire _103_;
  wire _104_;
  wire _105_;
  wire _106_;
  wire _107_;
  wire [7:0] _108_;
  wire [7:0] _109_;
  wire [7:0] _110_;
  wire [2:0] _111_;
  wire [2:0] _112_;
  wire [2:0] _113_;
  wire [2:0] _114_;
  wire [2:0] _115_;
  wire [2:0] _116_;
  wire [2:0] _117_;
  wire [2:0] _118_;
  wire [2:0] _119_;
  wire [2:0] _120_;
  wire [2:0] _121_;
  wire [7:0] _122_;
  wire [7:0] _123_;
  (* src = "fifo_synth.v:83" *)
  wire [31:0] _124_;
  (* src = "fifo_synth.v:94" *)
  wire [31:0] _125_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _126_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _127_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _128_;
  (* src = "<techmap.v>:258" *)
  wire [2:0] _129_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [2:0] _130_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [2:0] _131_;
  wire [2:0] _132_;
  wire _133_;
  wire _134_;
  (* src = "<techmap.v>:258" *)
  wire [2:0] _135_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [2:0] _136_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [2:0] _137_;
  wire [2:0] _138_;
  wire _139_;
  wire _140_;
  (* src = "<techmap.v>:258" *)
  wire [31:0] _141_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _142_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _143_;
  wire [31:0] _144_;
  wire _145_;
  wire _146_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [2:0] _147_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [2:0] _148_;
  wire [2:0] _149_;
  wire _150_;
  wire _151_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _152_;
  wire _153_;
  wire _154_;
  (* src = "<techmap.v>:260|<techmap.v>:203" *)
  wire [31:0] _155_;
  wire [31:0] _156_;
  (* src = "<techmap.v>:260" *)
  wire [2:0] _157_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _158_;
  (* src = "<techmap.v>:260|<techmap.v>:229" *)
  wire _159_;
  (* src = "<techmap.v>:260" *)
  wire [2:0] _160_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _161_;
  (* src = "<techmap.v>:260|<techmap.v>:229" *)
  wire _162_;
  (* src = "<techmap.v>:260" *)
  wire [31:0] _163_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _164_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _165_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _166_;
  (* src = "<techmap.v>:260" *)
  wire [2:0] _167_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _168_;
  (* src = "<techmap.v>:260|<techmap.v>:229" *)
  wire _169_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _170_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _171_;
  (* src = "<techmap.v>:260|<techmap.v>:221" *)
  wire _172_;
  (* src = "fifo_synth.v:3" *)
  input CLK;
  (* src = "fifo_synth.v:4" *)
  input ENB;
  (* src = "fifo_synth.v:5" *)
  input RST;
  (* src = "fifo_synth.v:15" *)
  output almostEmpty;
  reg almostEmpty;
  (* src = "fifo_synth.v:16" *)
  output almostFull;
  reg almostFull;
  reg [7:0] \buffer[0] ;
  reg [7:0] \buffer[1] ;
  reg [7:0] \buffer[2] ;
  reg [7:0] \buffer[3] ;
  reg [7:0] \buffer[4] ;
  reg [7:0] \buffer[5] ;
  reg [7:0] \buffer[6] ;
  reg [7:0] \buffer[7] ;
  (* src = "fifo_synth.v:27" *)
  reg [2:0] cantWr;
  (* src = "fifo_synth.v:19" *)
  output errorEmpty;
  reg errorEmpty;
  (* src = "fifo_synth.v:20" *)
  output errorFull;
  reg errorFull;
  (* src = "fifo_synth.v:13" *)
  input [7:0] inputData;
  (* src = "fifo_synth.v:17" *)
  output outEmpty;
  reg outEmpty;
  (* src = "fifo_synth.v:18" *)
  output outFull;
  reg outFull;
  (* src = "fifo_synth.v:22" *)
  output [7:0] outputData;
  reg [7:0] outputData;
  (* src = "fifo_synth.v:26" *)
  reg [2:0] ptrRd;
  (* src = "fifo_synth.v:25" *)
  reg [2:0] ptrWr;
  (* src = "fifo_synth.v:6" *)
  input sRead;
  (* src = "fifo_synth.v:7" *)
  input sWrite;
  (* src = "fifo_synth.v:10" *)
  input [2:0] umbEmpty;
  (* src = "fifo_synth.v:11" *)
  input [2:0] umbFull;
  assign _031_ = _014_[0] |(* src = "fifo_synth.v:59" *)  _042_[1];
  assign _043_ = _031_ |(* src = "fifo_synth.v:59" *)  _033_[1];
  assign _032_ = _014_[0] |(* src = "fifo_synth.v:79" *)  cantWr[1];
  assign _044_ = _032_ |(* src = "fifo_synth.v:79" *)  cantWr[2];
  assign _034_[0] = _033_[0] & _033_[1];
  assign _035_ = _131_[0] & _132_[1];
  assign _134_ = _035_ & _132_[2];
  assign _046_ = _133_ | _134_;
  assign _036_ = _137_[0] & _138_[1];
  assign _140_ = _036_ & _138_[2];
  assign _047_ = _139_ | _140_;
  assign _037_[0] = _143_[0] & _144_[1];
  assign _037_[1] = _144_[2] & _141_[31];
  assign _038_[0] = _037_[0] & _037_[1];
  assign _039_[0] = _038_[0] & _038_[7];
  assign _039_[3] = _038_[7] & _038_[7];
  assign _040_[0] = _039_[0] & _039_[3];
  assign _040_[1] = _039_[3] & _039_[3];
  assign _146_ = _040_[0] & _040_[1];
  assign _048_ = _145_ | _146_;
  assign _041_ = _148_[0] & _149_[1];
  assign _151_ = _041_ & _149_[2];
  assign _049_ = _150_ | _151_;
  assign _045_ = ~(* src = "fifo_synth.v:59" *) _043_;
  assign _050_ = _053_ &(* src = "fifo_synth.v:88" *)  _046_;
  assign _051_ = _047_ &(* src = "fifo_synth.v:94" *)  _048_;
  assign _052_ = _049_ &(* src = "fifo_synth.v:99" *)  _054_;
  assign _071_[0] = _063_ ? _001_[0] : \buffer[2] [0];
  assign _071_[1] = _063_ ? _001_[1] : \buffer[2] [1];
  assign _071_[2] = _063_ ? _001_[2] : \buffer[2] [2];
  assign _071_[3] = _063_ ? _001_[3] : \buffer[2] [3];
  assign _071_[4] = _063_ ? _001_[4] : \buffer[2] [4];
  assign _071_[5] = _063_ ? _001_[5] : \buffer[2] [5];
  assign _071_[6] = _063_ ? _001_[6] : \buffer[2] [6];
  assign _071_[7] = _063_ ? _001_[7] : \buffer[2] [7];
  assign _108_[7] = ENB ? (* src = "fifo_synth.v:46" *) sWrite : 1'b0;
  assign _002_[7] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _108_[7];
  assign _109_[0] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[0] : 1'bx;
  assign _109_[1] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[1] : 1'bx;
  assign _109_[2] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[2] : 1'bx;
  assign _109_[3] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[3] : 1'bx;
  assign _109_[4] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[4] : 1'bx;
  assign _109_[5] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[5] : 1'bx;
  assign _109_[6] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[6] : 1'bx;
  assign _109_[7] = sWrite ? (* src = "fifo_synth.v:47" *) inputData[7] : 1'bx;
  assign _110_[0] = ENB ? (* src = "fifo_synth.v:46" *) _109_[0] : 1'bx;
  assign _110_[1] = ENB ? (* src = "fifo_synth.v:46" *) _109_[1] : 1'bx;
  assign _110_[2] = ENB ? (* src = "fifo_synth.v:46" *) _109_[2] : 1'bx;
  assign _110_[3] = ENB ? (* src = "fifo_synth.v:46" *) _109_[3] : 1'bx;
  assign _110_[4] = ENB ? (* src = "fifo_synth.v:46" *) _109_[4] : 1'bx;
  assign _110_[5] = ENB ? (* src = "fifo_synth.v:46" *) _109_[5] : 1'bx;
  assign _110_[6] = ENB ? (* src = "fifo_synth.v:46" *) _109_[6] : 1'bx;
  assign _110_[7] = ENB ? (* src = "fifo_synth.v:46" *) _109_[7] : 1'bx;
  assign _001_[0] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[0];
  assign _001_[1] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[1];
  assign _001_[2] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[2];
  assign _001_[3] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[3];
  assign _001_[4] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[4];
  assign _001_[5] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[5];
  assign _001_[6] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[6];
  assign _001_[7] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _110_[7];
  assign _111_[0] = sWrite ? (* src = "fifo_synth.v:47" *) ptrWr[0] : 1'bx;
  assign _111_[1] = sWrite ? (* src = "fifo_synth.v:47" *) ptrWr[1] : 1'bx;
  assign _111_[2] = sWrite ? (* src = "fifo_synth.v:47" *) ptrWr[2] : 1'bx;
  assign _112_[0] = ENB ? (* src = "fifo_synth.v:46" *) _111_[0] : 1'bx;
  assign _112_[1] = ENB ? (* src = "fifo_synth.v:46" *) _111_[1] : 1'bx;
  assign _112_[2] = ENB ? (* src = "fifo_synth.v:46" *) _111_[2] : 1'bx;
  assign _070_[0] = _062_ ? _001_[0] : \buffer[1] [0];
  assign _070_[1] = _062_ ? _001_[1] : \buffer[1] [1];
  assign _070_[2] = _062_ ? _001_[2] : \buffer[1] [2];
  assign _070_[3] = _062_ ? _001_[3] : \buffer[1] [3];
  assign _070_[4] = _062_ ? _001_[4] : \buffer[1] [4];
  assign _070_[5] = _062_ ? _001_[5] : \buffer[1] [5];
  assign _070_[6] = _062_ ? _001_[6] : \buffer[1] [6];
  assign _070_[7] = _062_ ? _001_[7] : \buffer[1] [7];
  assign _000_[0] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _112_[0];
  assign _000_[1] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _112_[1];
  assign _000_[2] = RST ? (* src = "fifo_synth.v:32" *) 1'bx : _112_[2];
  assign _113_[0] = sRead ? (* src = "fifo_synth.v:51" *) cantWr[0] : _014_[0];
  assign _113_[1] = sRead ? (* src = "fifo_synth.v:51" *) cantWr[1] : _014_[1];
  assign _113_[2] = sRead ? (* src = "fifo_synth.v:51" *) cantWr[2] : _014_[2];
  assign _114_[0] = sWrite ? (* src = "fifo_synth.v:47" *) _113_[0] : cantWr[0];
  assign _114_[1] = sWrite ? (* src = "fifo_synth.v:47" *) _113_[1] : cantWr[1];
  assign _114_[2] = sWrite ? (* src = "fifo_synth.v:47" *) _113_[2] : cantWr[2];
  assign _115_[0] = sWrite ? (* src = "fifo_synth.v:71" *) _114_[0] : _014_[0];
  assign _115_[1] = sWrite ? (* src = "fifo_synth.v:71" *) _114_[1] : _124_[1];
  assign _115_[2] = sWrite ? (* src = "fifo_synth.v:71" *) _114_[2] : _124_[2];
  assign _116_[0] = sRead ? (* src = "fifo_synth.v:67" *) _115_[0] : _114_[0];
  assign _116_[1] = sRead ? (* src = "fifo_synth.v:67" *) _115_[1] : _114_[1];
  assign _116_[2] = sRead ? (* src = "fifo_synth.v:67" *) _115_[2] : _114_[2];
  assign _117_[0] = ENB ? (* src = "fifo_synth.v:46" *) _116_[0] : cantWr[0];
  assign _117_[1] = ENB ? (* src = "fifo_synth.v:46" *) _116_[1] : cantWr[1];
  assign _117_[2] = ENB ? (* src = "fifo_synth.v:46" *) _116_[2] : cantWr[2];
  assign _069_[0] = _061_ ? _001_[0] : \buffer[0] [0];
  assign _069_[1] = _061_ ? _001_[1] : \buffer[0] [1];
  assign _069_[2] = _061_ ? _001_[2] : \buffer[0] [2];
  assign _069_[3] = _061_ ? _001_[3] : \buffer[0] [3];
  assign _069_[4] = _061_ ? _001_[4] : \buffer[0] [4];
  assign _069_[5] = _061_ ? _001_[5] : \buffer[0] [5];
  assign _069_[6] = _061_ ? _001_[6] : \buffer[0] [6];
  assign _069_[7] = _061_ ? _001_[7] : \buffer[0] [7];
  assign _005_[0] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _117_[0];
  assign _005_[1] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _117_[1];
  assign _005_[2] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _117_[2];
  assign _118_[0] = sRead ? (* src = "fifo_synth.v:67" *) _015_[0] : ptrRd[0];
  assign _118_[1] = sRead ? (* src = "fifo_synth.v:67" *) _015_[1] : ptrRd[1];
  assign _118_[2] = sRead ? (* src = "fifo_synth.v:67" *) _015_[2] : ptrRd[2];
  assign _119_[0] = ENB ? (* src = "fifo_synth.v:46" *) _118_[0] : ptrRd[0];
  assign _119_[1] = ENB ? (* src = "fifo_synth.v:46" *) _118_[1] : ptrRd[1];
  assign _119_[2] = ENB ? (* src = "fifo_synth.v:46" *) _118_[2] : ptrRd[2];
  assign _011_[0] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _119_[0];
  assign _011_[1] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _119_[1];
  assign _011_[2] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _119_[2];
  assign _120_[0] = sWrite ? (* src = "fifo_synth.v:47" *) _013_[0] : ptrWr[0];
  assign _120_[1] = sWrite ? (* src = "fifo_synth.v:47" *) _013_[1] : ptrWr[1];
  assign _120_[2] = sWrite ? (* src = "fifo_synth.v:47" *) _013_[2] : ptrWr[2];
  assign _121_[0] = ENB ? (* src = "fifo_synth.v:46" *) _120_[0] : ptrWr[0];
  assign _121_[1] = ENB ? (* src = "fifo_synth.v:46" *) _120_[1] : ptrWr[1];
  assign _121_[2] = ENB ? (* src = "fifo_synth.v:46" *) _120_[2] : ptrWr[2];
  assign _012_[0] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _121_[0];
  assign _012_[1] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _121_[1];
  assign _012_[2] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _121_[2];
  assign _122_[0] = sRead ? (* src = "fifo_synth.v:67" *) _077_[0] : outputData[0];
  assign _122_[1] = sRead ? (* src = "fifo_synth.v:67" *) _077_[1] : outputData[1];
  assign _122_[2] = sRead ? (* src = "fifo_synth.v:67" *) _077_[2] : outputData[2];
  assign _122_[3] = sRead ? (* src = "fifo_synth.v:67" *) _077_[3] : outputData[3];
  assign _122_[4] = sRead ? (* src = "fifo_synth.v:67" *) _077_[4] : outputData[4];
  assign _122_[5] = sRead ? (* src = "fifo_synth.v:67" *) _077_[5] : outputData[5];
  assign _122_[6] = sRead ? (* src = "fifo_synth.v:67" *) _077_[6] : outputData[6];
  assign _122_[7] = sRead ? (* src = "fifo_synth.v:67" *) _077_[7] : outputData[7];
  assign _123_[0] = ENB ? (* src = "fifo_synth.v:46" *) _122_[0] : outputData[0];
  assign _123_[1] = ENB ? (* src = "fifo_synth.v:46" *) _122_[1] : outputData[1];
  assign _123_[2] = ENB ? (* src = "fifo_synth.v:46" *) _122_[2] : outputData[2];
  assign _123_[3] = ENB ? (* src = "fifo_synth.v:46" *) _122_[3] : outputData[3];
  assign _123_[4] = ENB ? (* src = "fifo_synth.v:46" *) _122_[4] : outputData[4];
  assign _123_[5] = ENB ? (* src = "fifo_synth.v:46" *) _122_[5] : outputData[5];
  assign _123_[6] = ENB ? (* src = "fifo_synth.v:46" *) _122_[6] : outputData[6];
  assign _123_[7] = ENB ? (* src = "fifo_synth.v:46" *) _122_[7] : outputData[7];
  assign _010_[0] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[0];
  assign _010_[1] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[1];
  assign _010_[2] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[2];
  assign _010_[3] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[3];
  assign _010_[4] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[4];
  assign _010_[5] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[5];
  assign _010_[6] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[6];
  assign _010_[7] = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _123_[7];
  assign _078_ = outFull ? (* src = "fifo_synth.v:55" *) 1'b1 : errorFull;
  assign _079_ = sRead ? (* src = "fifo_synth.v:51" *) errorFull : _078_;
  assign _060_[0] = ptrRd[0] ? \buffer[7] [0] : \buffer[6] [0];
  assign _060_[1] = ptrRd[0] ? \buffer[7] [1] : \buffer[6] [1];
  assign _060_[2] = ptrRd[0] ? \buffer[7] [2] : \buffer[6] [2];
  assign _060_[3] = ptrRd[0] ? \buffer[7] [3] : \buffer[6] [3];
  assign _060_[4] = ptrRd[0] ? \buffer[7] [4] : \buffer[6] [4];
  assign _060_[5] = ptrRd[0] ? \buffer[7] [5] : \buffer[6] [5];
  assign _060_[6] = ptrRd[0] ? \buffer[7] [6] : \buffer[6] [6];
  assign _060_[7] = ptrRd[0] ? \buffer[7] [7] : \buffer[6] [7];
  assign _080_ = sWrite ? (* src = "fifo_synth.v:47" *) _079_ : errorFull;
  assign _081_ = ENB ? (* src = "fifo_synth.v:46" *) _080_ : errorFull;
  assign _059_[0] = ptrRd[0] ? \buffer[5] [0] : \buffer[4] [0];
  assign _059_[1] = ptrRd[0] ? \buffer[5] [1] : \buffer[4] [1];
  assign _059_[2] = ptrRd[0] ? \buffer[5] [2] : \buffer[4] [2];
  assign _059_[3] = ptrRd[0] ? \buffer[5] [3] : \buffer[4] [3];
  assign _059_[4] = ptrRd[0] ? \buffer[5] [4] : \buffer[4] [4];
  assign _059_[5] = ptrRd[0] ? \buffer[5] [5] : \buffer[4] [5];
  assign _059_[6] = ptrRd[0] ? \buffer[5] [6] : \buffer[4] [6];
  assign _059_[7] = ptrRd[0] ? \buffer[5] [7] : \buffer[4] [7];
  assign _007_ = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _081_;
  assign _082_ = outEmpty ? (* src = "fifo_synth.v:75" *) 1'b1 : errorEmpty;
  assign _083_ = sWrite ? (* src = "fifo_synth.v:71" *) errorEmpty : _082_;
  assign _058_[0] = ptrRd[0] ? \buffer[3] [0] : \buffer[2] [0];
  assign _058_[1] = ptrRd[0] ? \buffer[3] [1] : \buffer[2] [1];
  assign _058_[2] = ptrRd[0] ? \buffer[3] [2] : \buffer[2] [2];
  assign _058_[3] = ptrRd[0] ? \buffer[3] [3] : \buffer[2] [3];
  assign _058_[4] = ptrRd[0] ? \buffer[3] [4] : \buffer[2] [4];
  assign _058_[5] = ptrRd[0] ? \buffer[3] [5] : \buffer[2] [5];
  assign _058_[6] = ptrRd[0] ? \buffer[3] [6] : \buffer[2] [6];
  assign _058_[7] = ptrRd[0] ? \buffer[3] [7] : \buffer[2] [7];
  assign _084_ = sRead ? (* src = "fifo_synth.v:67" *) _083_ : errorEmpty;
  assign _085_ = ENB ? (* src = "fifo_synth.v:46" *) _084_ : errorEmpty;
  assign _057_[0] = ptrRd[0] ? \buffer[1] [0] : \buffer[0] [0];
  assign _057_[1] = ptrRd[0] ? \buffer[1] [1] : \buffer[0] [1];
  assign _057_[2] = ptrRd[0] ? \buffer[1] [2] : \buffer[0] [2];
  assign _057_[3] = ptrRd[0] ? \buffer[1] [3] : \buffer[0] [3];
  assign _057_[4] = ptrRd[0] ? \buffer[1] [4] : \buffer[0] [4];
  assign _057_[5] = ptrRd[0] ? \buffer[1] [5] : \buffer[0] [5];
  assign _057_[6] = ptrRd[0] ? \buffer[1] [6] : \buffer[0] [6];
  assign _057_[7] = ptrRd[0] ? \buffer[1] [7] : \buffer[0] [7];
  assign _006_ = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _085_;
  assign _086_ = outFull ? (* src = "fifo_synth.v:55" *) 1'b1 : _045_;
  assign _056_[0] = ptrRd[1] ? _060_[0] : _059_[0];
  assign _056_[1] = ptrRd[1] ? _060_[1] : _059_[1];
  assign _056_[2] = ptrRd[1] ? _060_[2] : _059_[2];
  assign _056_[3] = ptrRd[1] ? _060_[3] : _059_[3];
  assign _056_[4] = ptrRd[1] ? _060_[4] : _059_[4];
  assign _056_[5] = ptrRd[1] ? _060_[5] : _059_[5];
  assign _056_[6] = ptrRd[1] ? _060_[6] : _059_[6];
  assign _056_[7] = ptrRd[1] ? _060_[7] : _059_[7];
  assign _087_ = sRead ? (* src = "fifo_synth.v:51" *) outFull : _086_;
  assign _088_ = sWrite ? (* src = "fifo_synth.v:47" *) _087_ : outFull;
  assign _089_ = outFull ? (* src = "fifo_synth.v:72" *) 1'b0 : _088_;
  assign _055_[0] = ptrRd[1] ? _058_[0] : _057_[0];
  assign _055_[1] = ptrRd[1] ? _058_[1] : _057_[1];
  assign _055_[2] = ptrRd[1] ? _058_[2] : _057_[2];
  assign _055_[3] = ptrRd[1] ? _058_[3] : _057_[3];
  assign _055_[4] = ptrRd[1] ? _058_[4] : _057_[4];
  assign _055_[5] = ptrRd[1] ? _058_[5] : _057_[5];
  assign _055_[6] = ptrRd[1] ? _058_[6] : _057_[6];
  assign _055_[7] = ptrRd[1] ? _058_[7] : _057_[7];
  assign _090_ = sWrite ? (* src = "fifo_synth.v:71" *) _088_ : _089_;
  assign _091_ = sRead ? (* src = "fifo_synth.v:67" *) _090_ : _088_;
  assign _092_ = ENB ? (* src = "fifo_synth.v:46" *) _091_ : outFull;
  assign _077_[0] = ptrRd[2] ? _056_[0] : _055_[0];
  assign _077_[1] = ptrRd[2] ? _056_[1] : _055_[1];
  assign _077_[2] = ptrRd[2] ? _056_[2] : _055_[2];
  assign _077_[3] = ptrRd[2] ? _056_[3] : _055_[3];
  assign _077_[4] = ptrRd[2] ? _056_[4] : _055_[4];
  assign _077_[5] = ptrRd[2] ? _056_[5] : _055_[5];
  assign _077_[6] = ptrRd[2] ? _056_[6] : _055_[6];
  assign _077_[7] = ptrRd[2] ? _056_[7] : _055_[7];
  assign _093_ = _052_ ? (* src = "fifo_synth.v:99" *) 1'b0 : _092_;
  assign _009_ = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _093_;
  assign _094_ = sRead ? (* src = "fifo_synth.v:51" *) outEmpty : 1'b0;
  assign _095_ = sWrite ? (* src = "fifo_synth.v:47" *) _094_ : outEmpty;
  assign _096_ = _044_ ? (* src = "fifo_synth.v:79" *) _095_ : 1'b1;
  assign _097_ = outEmpty ? (* src = "fifo_synth.v:75" *) _095_ : _096_;
  assign _098_ = sWrite ? (* src = "fifo_synth.v:71" *) _095_ : _097_;
  assign _099_ = sRead ? (* src = "fifo_synth.v:67" *) _098_ : _095_;
  assign _100_ = ENB ? (* src = "fifo_synth.v:46" *) _099_ : outEmpty;
  assign _101_ = _050_ ? (* src = "fifo_synth.v:88" *) 1'b0 : _100_;
  assign _008_ = RST ? (* src = "fifo_synth.v:32" *) 1'b1 : _101_;
  assign _102_ = _050_ ? (* src = "fifo_synth.v:88" *) 1'b0 : almostFull;
  assign _103_ = _051_ ? (* src = "fifo_synth.v:94" *) 1'b0 : _102_;
  assign _104_ = _052_ ? (* src = "fifo_synth.v:99" *) 1'b1 : _103_;
  assign _004_ = RST ? (* src = "fifo_synth.v:32" *) 1'b0 : _104_;
  assign _105_ = _050_ ? (* src = "fifo_synth.v:88" *) 1'b1 : almostEmpty;
  assign _106_ = _051_ ? (* src = "fifo_synth.v:94" *) 1'b0 : _105_;
  assign _107_ = _052_ ? (* src = "fifo_synth.v:99" *) 1'b0 : _106_;
  assign _003_ = RST ? (* src = "fifo_synth.v:32" *) 1'b1 : _107_;
  assign _072_[0] = _064_ ? _001_[0] : \buffer[3] [0];
  assign _072_[1] = _064_ ? _001_[1] : \buffer[3] [1];
  assign _072_[2] = _064_ ? _001_[2] : \buffer[3] [2];
  assign _072_[3] = _064_ ? _001_[3] : \buffer[3] [3];
  assign _072_[4] = _064_ ? _001_[4] : \buffer[3] [4];
  assign _072_[5] = _064_ ? _001_[5] : \buffer[3] [5];
  assign _072_[6] = _064_ ? _001_[6] : \buffer[3] [6];
  assign _072_[7] = _064_ ? _001_[7] : \buffer[3] [7];
  assign _073_[0] = _065_ ? _001_[0] : \buffer[4] [0];
  assign _073_[1] = _065_ ? _001_[1] : \buffer[4] [1];
  assign _073_[2] = _065_ ? _001_[2] : \buffer[4] [2];
  assign _073_[3] = _065_ ? _001_[3] : \buffer[4] [3];
  assign _073_[4] = _065_ ? _001_[4] : \buffer[4] [4];
  assign _073_[5] = _065_ ? _001_[5] : \buffer[4] [5];
  assign _073_[6] = _065_ ? _001_[6] : \buffer[4] [6];
  assign _073_[7] = _065_ ? _001_[7] : \buffer[4] [7];
  assign _074_[0] = _066_ ? _001_[0] : \buffer[5] [0];
  assign _074_[1] = _066_ ? _001_[1] : \buffer[5] [1];
  assign _074_[2] = _066_ ? _001_[2] : \buffer[5] [2];
  assign _074_[3] = _066_ ? _001_[3] : \buffer[5] [3];
  assign _074_[4] = _066_ ? _001_[4] : \buffer[5] [4];
  assign _074_[5] = _066_ ? _001_[5] : \buffer[5] [5];
  assign _074_[6] = _066_ ? _001_[6] : \buffer[5] [6];
  assign _074_[7] = _066_ ? _001_[7] : \buffer[5] [7];
  assign _075_[0] = _067_ ? _001_[0] : \buffer[6] [0];
  assign _075_[1] = _067_ ? _001_[1] : \buffer[6] [1];
  assign _075_[2] = _067_ ? _001_[2] : \buffer[6] [2];
  assign _075_[3] = _067_ ? _001_[3] : \buffer[6] [3];
  assign _075_[4] = _067_ ? _001_[4] : \buffer[6] [4];
  assign _075_[5] = _067_ ? _001_[5] : \buffer[6] [5];
  assign _075_[6] = _067_ ? _001_[6] : \buffer[6] [6];
  assign _075_[7] = _067_ ? _001_[7] : \buffer[6] [7];
  assign _076_[0] = _068_ ? _001_[0] : \buffer[7] [0];
  assign _076_[1] = _068_ ? _001_[1] : \buffer[7] [1];
  assign _076_[2] = _068_ ? _001_[2] : \buffer[7] [2];
  assign _076_[3] = _068_ ? _001_[3] : \buffer[7] [3];
  assign _076_[4] = _068_ ? _001_[4] : \buffer[7] [4];
  assign _076_[5] = _068_ ? _001_[5] : \buffer[7] [5];
  assign _076_[6] = _068_ ? _001_[6] : \buffer[7] [6];
  assign _076_[7] = _068_ ? _001_[7] : \buffer[7] [7];
  assign _129_[0] = ~(* src = "<techmap.v>:258" *) umbEmpty[0];
  assign _129_[1] = ~(* src = "<techmap.v>:258" *) umbEmpty[1];
  assign _129_[2] = ~(* src = "<techmap.v>:258" *) umbEmpty[2];
  assign _141_[0] = ~(* src = "<techmap.v>:258" *) _125_[0];
  assign _141_[1] = ~(* src = "<techmap.v>:258" *) _125_[1];
  assign _141_[2] = ~(* src = "<techmap.v>:258" *) _125_[2];
  assign _141_[31] = ~(* src = "<techmap.v>:258" *) _125_[31];
  assign _135_[0] = ~(* src = "<techmap.v>:258" *) cantWr[0];
  assign _135_[1] = ~(* src = "<techmap.v>:258" *) cantWr[1];
  assign _135_[2] = ~(* src = "<techmap.v>:258" *) cantWr[2];
  assign _030_ = ~_000_[2];
  assign _029_ = ~_000_[1];
  assign _028_ = ~_000_[0];
  assign _153_ = ~_152_[31];
  assign _053_ = ~_154_;
  assign _133_ = ~_130_[2];
  assign _139_ = ~_136_[2];
  assign _145_ = ~_142_[31];
  assign _150_ = ~_147_[2];
  assign _054_ = ~_014_[3];
  always @(posedge CLK)
      \buffer[0] [0] <= _069_[0];
  always @(posedge CLK)
      \buffer[0] [1] <= _069_[1];
  always @(posedge CLK)
      \buffer[0] [2] <= _069_[2];
  always @(posedge CLK)
      \buffer[0] [3] <= _069_[3];
  always @(posedge CLK)
      \buffer[0] [4] <= _069_[4];
  always @(posedge CLK)
      \buffer[0] [5] <= _069_[5];
  always @(posedge CLK)
      \buffer[0] [6] <= _069_[6];
  always @(posedge CLK)
      \buffer[0] [7] <= _069_[7];
  always @(posedge CLK)
      \buffer[1] [0] <= _070_[0];
  always @(posedge CLK)
      \buffer[1] [1] <= _070_[1];
  always @(posedge CLK)
      \buffer[1] [2] <= _070_[2];
  always @(posedge CLK)
      \buffer[1] [3] <= _070_[3];
  always @(posedge CLK)
      \buffer[1] [4] <= _070_[4];
  always @(posedge CLK)
      \buffer[1] [5] <= _070_[5];
  always @(posedge CLK)
      \buffer[1] [6] <= _070_[6];
  always @(posedge CLK)
      \buffer[1] [7] <= _070_[7];
  always @(posedge CLK)
      ptrRd[0] <= _011_[0];
  always @(posedge CLK)
      ptrRd[1] <= _011_[1];
  always @(posedge CLK)
      ptrRd[2] <= _011_[2];
  always @(posedge CLK)
      \buffer[7] [0] <= _076_[0];
  always @(posedge CLK)
      \buffer[7] [1] <= _076_[1];
  always @(posedge CLK)
      \buffer[7] [2] <= _076_[2];
  always @(posedge CLK)
      \buffer[7] [3] <= _076_[3];
  always @(posedge CLK)
      \buffer[7] [4] <= _076_[4];
  always @(posedge CLK)
      \buffer[7] [5] <= _076_[5];
  always @(posedge CLK)
      \buffer[7] [6] <= _076_[6];
  always @(posedge CLK)
      \buffer[7] [7] <= _076_[7];
  always @(posedge CLK)
      \buffer[6] [0] <= _075_[0];
  always @(posedge CLK)
      \buffer[6] [1] <= _075_[1];
  always @(posedge CLK)
      \buffer[6] [2] <= _075_[2];
  always @(posedge CLK)
      \buffer[6] [3] <= _075_[3];
  always @(posedge CLK)
      \buffer[6] [4] <= _075_[4];
  always @(posedge CLK)
      \buffer[6] [5] <= _075_[5];
  always @(posedge CLK)
      \buffer[6] [6] <= _075_[6];
  always @(posedge CLK)
      \buffer[6] [7] <= _075_[7];
  always @(posedge CLK)
      \buffer[5] [0] <= _074_[0];
  always @(posedge CLK)
      \buffer[5] [1] <= _074_[1];
  always @(posedge CLK)
      \buffer[5] [2] <= _074_[2];
  always @(posedge CLK)
      \buffer[5] [3] <= _074_[3];
  always @(posedge CLK)
      \buffer[5] [4] <= _074_[4];
  always @(posedge CLK)
      \buffer[5] [5] <= _074_[5];
  always @(posedge CLK)
      \buffer[5] [6] <= _074_[6];
  always @(posedge CLK)
      \buffer[5] [7] <= _074_[7];
  always @(posedge CLK)
      \buffer[4] [0] <= _073_[0];
  always @(posedge CLK)
      \buffer[4] [1] <= _073_[1];
  always @(posedge CLK)
      \buffer[4] [2] <= _073_[2];
  always @(posedge CLK)
      \buffer[4] [3] <= _073_[3];
  always @(posedge CLK)
      \buffer[4] [4] <= _073_[4];
  always @(posedge CLK)
      \buffer[4] [5] <= _073_[5];
  always @(posedge CLK)
      \buffer[4] [6] <= _073_[6];
  always @(posedge CLK)
      \buffer[4] [7] <= _073_[7];
  always @(posedge CLK)
      \buffer[3] [0] <= _072_[0];
  always @(posedge CLK)
      \buffer[3] [1] <= _072_[1];
  always @(posedge CLK)
      \buffer[3] [2] <= _072_[2];
  always @(posedge CLK)
      \buffer[3] [3] <= _072_[3];
  always @(posedge CLK)
      \buffer[3] [4] <= _072_[4];
  always @(posedge CLK)
      \buffer[3] [5] <= _072_[5];
  always @(posedge CLK)
      \buffer[3] [6] <= _072_[6];
  always @(posedge CLK)
      \buffer[3] [7] <= _072_[7];
  always @(posedge CLK)
      \buffer[2] [0] <= _071_[0];
  always @(posedge CLK)
      \buffer[2] [1] <= _071_[1];
  always @(posedge CLK)
      \buffer[2] [2] <= _071_[2];
  always @(posedge CLK)
      \buffer[2] [3] <= _071_[3];
  always @(posedge CLK)
      \buffer[2] [4] <= _071_[4];
  always @(posedge CLK)
      \buffer[2] [5] <= _071_[5];
  always @(posedge CLK)
      \buffer[2] [6] <= _071_[6];
  always @(posedge CLK)
      \buffer[2] [7] <= _071_[7];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      almostFull <= _004_;
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      almostEmpty <= _003_;
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outEmpty <= _008_;
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outFull <= _009_;
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      errorEmpty <= _006_;
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      errorFull <= _007_;
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[0] <= _010_[0];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[1] <= _010_[1];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[2] <= _010_[2];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[3] <= _010_[3];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[4] <= _010_[4];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[5] <= _010_[5];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[6] <= _010_[6];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      outputData[7] <= _010_[7];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      ptrWr[0] <= _012_[0];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      ptrWr[1] <= _012_[1];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      ptrWr[2] <= _012_[2];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      cantWr[0] <= _005_[0];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      cantWr[1] <= _005_[1];
  (* src = "fifo_synth.v:31" *)
  always @(posedge CLK)
      cantWr[2] <= _005_[2];
  assign _014_[1] = cantWr[1] ^(* src = "<techmap.v>:263" *)  cantWr[0];
  assign _015_[0] = ptrRd[0] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign _015_[1] = ptrRd[1] ^(* src = "<techmap.v>:263" *)  ptrRd[0];
  assign _015_[2] = ptrRd[2] ^(* src = "<techmap.v>:263" *)  _128_[1];
  assign _042_[1] = cantWr[1] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign _033_[1] = cantWr[2] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign _124_[1] = _042_[1] ^(* src = "<techmap.v>:263" *)  cantWr[0];
  assign _124_[2] = _033_[1] ^(* src = "<techmap.v>:263" *)  _152_[1];
  assign _131_[0] = cantWr[0] ^(* src = "<techmap.v>:262" *)  _129_[0];
  assign _132_[1] = cantWr[1] ^(* src = "<techmap.v>:262" *)  _129_[1];
  assign _132_[2] = cantWr[2] ^(* src = "<techmap.v>:262" *)  _129_[2];
  assign _157_[0] = cantWr[0] &(* src = "<techmap.v>:260" *)  _129_[0];
  assign _157_[1] = cantWr[1] &(* src = "<techmap.v>:260" *)  _129_[1];
  assign _157_[2] = cantWr[2] &(* src = "<techmap.v>:260" *)  _129_[2];
  assign _137_[0] = umbEmpty[0] ^(* src = "<techmap.v>:262" *)  _135_[0];
  assign _138_[1] = umbEmpty[1] ^(* src = "<techmap.v>:262" *)  _135_[1];
  assign _138_[2] = umbEmpty[2] ^(* src = "<techmap.v>:262" *)  _135_[2];
  assign _160_[0] = umbEmpty[0] &(* src = "<techmap.v>:260" *)  _135_[0];
  assign _160_[1] = umbEmpty[1] &(* src = "<techmap.v>:260" *)  _135_[1];
  assign _160_[2] = umbEmpty[2] &(* src = "<techmap.v>:260" *)  _135_[2];
  assign _156_[1] = umbFull[1] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign _156_[2] = umbFull[2] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign _125_[0] = umbFull[0] ^(* src = "<techmap.v>:263" *)  1'b1;
  assign _125_[1] = _156_[1] ^(* src = "<techmap.v>:263" *)  umbFull[0];
  assign _125_[2] = _156_[2] ^(* src = "<techmap.v>:263" *)  _155_[1];
  assign _125_[31] = 1'b1 ^(* src = "<techmap.v>:263" *)  _155_[31];
  assign _143_[0] = cantWr[0] ^(* src = "<techmap.v>:262" *)  _141_[0];
  assign _144_[1] = cantWr[1] ^(* src = "<techmap.v>:262" *)  _141_[1];
  assign _144_[2] = cantWr[2] ^(* src = "<techmap.v>:262" *)  _141_[2];
  assign _163_[0] = cantWr[0] &(* src = "<techmap.v>:260" *)  _141_[0];
  assign _163_[1] = cantWr[1] &(* src = "<techmap.v>:260" *)  _141_[1];
  assign _163_[2] = cantWr[2] &(* src = "<techmap.v>:260" *)  _141_[2];
  assign _148_[0] = umbFull[0] ^(* src = "<techmap.v>:262" *)  _135_[0];
  assign _149_[1] = umbFull[1] ^(* src = "<techmap.v>:262" *)  _135_[1];
  assign _149_[2] = umbFull[2] ^(* src = "<techmap.v>:262" *)  _135_[2];
  assign _167_[0] = umbFull[0] &(* src = "<techmap.v>:260" *)  _135_[0];
  assign _167_[1] = umbFull[1] &(* src = "<techmap.v>:260" *)  _135_[1];
  assign _167_[2] = umbFull[2] &(* src = "<techmap.v>:260" *)  _135_[2];
  assign _014_[0] = cantWr[0] ^(* src = "<techmap.v>:263" *)  1'b1;
  assign _014_[2] = cantWr[2] ^(* src = "<techmap.v>:263" *)  _127_[1];
  assign _126_[1] = ptrWr[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  ptrWr[0];
  assign _136_[0] = _160_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *)  _137_[0];
  assign _162_ = _138_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _136_[1];
  assign _161_ = _138_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _136_[0];
  assign _130_[2] = _157_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *)  _159_;
  assign _130_[1] = _157_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _158_;
  assign _130_[0] = _157_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *)  _131_[0];
  assign _159_ = _132_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _130_[1];
  assign _158_ = _132_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _130_[0];
  assign _128_[1] = ptrRd[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  ptrRd[0];
  assign _170_ = _033_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _152_[1];
  assign _033_[0] = _042_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  cantWr[0];
  assign _152_[1] = cantWr[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _033_[0];
  assign _152_[31] = cantWr[2] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _170_;
  assign _136_[1] = _160_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _161_;
  assign _136_[2] = _160_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *)  _162_;
  assign _171_ = _156_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  umbFull[0];
  assign _172_ = _156_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _155_[1];
  assign _155_[1] = umbFull[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _171_;
  assign _155_[31] = umbFull[2] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _172_;
  assign _164_ = _144_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _142_[0];
  assign _165_ = _141_[31] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _163_[2];
  assign _166_ = _037_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _142_[1];
  assign _142_[7] = _038_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _142_[3];
  assign _142_[15] = _039_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _142_[7];
  assign _142_[31] = _040_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _142_[15];
  assign _037_[15] = _141_[31] &(* src = "<techmap.v>:260|<techmap.v>:222" *)  _141_[31];
  assign _038_[7] = _037_[15] &(* src = "<techmap.v>:260|<techmap.v>:222" *)  _037_[15];
  assign _142_[0] = _163_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *)  _143_[0];
  assign _142_[1] = _163_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _164_;
  assign _142_[3] = _165_ |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _166_;
  assign _168_ = _149_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _147_[0];
  assign _169_ = _149_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *)  _147_[1];
  assign _147_[0] = _167_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *)  _148_[0];
  assign _147_[1] = _167_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *)  _168_;
  assign _147_[2] = _167_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *)  _169_;
  assign _127_[1] = cantWr[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  cantWr[0];
  assign _014_[3] = cantWr[2] &(* src = "<techmap.v>:260|<techmap.v>:221" *)  _127_[1];
  assign _064_ = _021_ & _002_[7];
  assign _021_ = _000_[0] & _019_;
  assign _063_ = _020_ & _002_[7];
  assign _020_ = _028_ & _019_;
  assign _019_ = _000_[1] & _030_;
  assign _062_ = _018_ & _002_[7];
  assign _018_ = _000_[0] & _016_;
  assign _061_ = _017_ & _002_[7];
  assign _017_ = _028_ & _016_;
  assign _016_ = _029_ & _030_;
  assign _022_ = _029_ & _000_[2];
  assign _023_ = _028_ & _022_;
  assign _065_ = _023_ & _002_[7];
  assign _024_ = _000_[0] & _022_;
  assign _066_ = _024_ & _002_[7];
  assign _025_ = _000_[1] & _000_[2];
  assign _026_ = _028_ & _025_;
  assign _067_ = _026_ & _002_[7];
  assign _027_ = _000_[0] & _025_;
  assign _068_ = _027_ & _002_[7];
  assign _154_ = _153_ | _034_[0];
  assign _013_[0] = ptrWr[0] ^(* src = "<techmap.v>:262" *)  1'b1;
  assign _013_[1] = ptrWr[1] ^(* src = "<techmap.v>:263" *)  ptrWr[0];
  assign _013_[2] = ptrWr[2] ^(* src = "<techmap.v>:263" *)  _126_[1];
endmodule