data/full_repos/permissive/201275379/test/stage/PC_tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:3: Cannot find include file: tb.v\n`include "tb.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/test/stage,data/full_repos/permissive/201275379/tb.v\n             data/full_repos/permissive/201275379/test/stage,data/full_repos/permissive/201275379/tb.v.v\n             data/full_repos/permissive/201275379/test/stage,data/full_repos/permissive/201275379/tb.v.sv\n             tb.v\n             tb.v.v\n             tb.v.sv\n             obj_dir/tb.v\n             obj_dir/tb.v.v\n             obj_dir/tb.v.sv\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:4: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:5: Cannot find include file: branch.v\n`include "branch.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:26: Define or directive not defined: \'`GEN_TICK\'\n  `GEN_TICK(clk, rst);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:26: syntax error, unexpected \'(\'\n  `GEN_TICK(clk, rst);\n            ^~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:30: Define or directive not defined: \'`GHR_BUS\'\n  reg[`GHR_BUS] last_pht_index;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`GHR_BUS] last_pht_index;\n              ^\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:31: Define or directive not defined: \'`ADDR_BUS\'\n  reg[`ADDR_BUS] inst_pc, target_in, exc_pc;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`ADDR_BUS] inst_pc, target_in, exc_pc;\n               ^\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:33: Define or directive not defined: \'`GHR_BUS\'\n  wire[`GHR_BUS] pht_index_out;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:33: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`GHR_BUS] pht_index_out;\n               ^\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:34: Define or directive not defined: \'`ADDR_BUS\'\n  wire[`ADDR_BUS] pc_out;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`ADDR_BUS] pc_out;\n                ^\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:37: Define or directive not defined: \'`GHR_BUS\'\n  wire[`GHR_BUS] mod_pht_index;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`GHR_BUS] mod_pht_index;\n               ^\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:38: Define or directive not defined: \'`ADDR_BUS\'\n  wire[`ADDR_BUS] mod_pc;\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`ADDR_BUS] mod_pc;\n                ^\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:89: Define or directive not defined: \'`TICK\'\n    if (`TICK >= 32\'h4a && `TICK <= 32\'h4e) stall <= 1;\n        ^~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:89: syntax error, unexpected >=, expecting TYPE-IDENTIFIER\n    if (`TICK >= 32\'h4a && `TICK <= 32\'h4e) stall <= 1;\n              ^~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:89: Define or directive not defined: \'`TICK\'\n    if (`TICK >= 32\'h4a && `TICK <= 32\'h4e) stall <= 1;\n                           ^~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:93: Define or directive not defined: \'`DISPLAY\'\n    `DISPLAY("*****  mod_pc  *****", mod_pc);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:93: syntax error, unexpected \',\'\n    `DISPLAY("*****  mod_pc  *****", mod_pc);\n                                   ^\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:94: Define or directive not defined: \'`END_AT_TICK\'\n    `END_AT_TICK(100);\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/test/stage/PC_tb.v:94: syntax error, unexpected \';\'\n    `END_AT_TICK(100);\n                     ^\n%Error: Exiting due to 24 error(s)\n'
module PC_tb(
  input clk,
  input rst
);


  `GEN_TICK(clk, rst);


  reg is_branch_in, is_jump_in, is_taken_in, flush, stall;
  reg[`GHR_BUS] last_pht_index;
  reg[`ADDR_BUS] inst_pc, target_in, exc_pc;
  wire is_branch_taken;
  wire[`GHR_BUS] pht_index_out;
  wire[`ADDR_BUS] pc_out;

  wire mod_is_branch_taken;
  wire[`GHR_BUS] mod_pht_index;
  wire[`ADDR_BUS] mod_pc;

  PC stage_pc(
    .clk                  (clk),
    .rst                  (rst),

    .is_branch_in         (is_branch_in),
    .is_jump_in           (is_jump_in),
    .is_taken_in          (is_taken_in),
    .last_pht_index       (last_pht_index),
    .inst_pc              (inst_pc),
    .target_in            (target_in),

    .flush                (flush),
    .stall                (stall),
    .exc_pc               (exc_pc),

    .is_branch_taken      (is_branch_taken),
    .pht_index_out        (pht_index_out),
    .pc_out               (pc_out)
  );

  PCIF pcif_mid(
    .clk                  (clk),
    .rst                  (rst),
    .flush                (flush),
    .stall_current_stage  (stall),
    .stall_next_stage     (stall),
    .is_branch_taken_in   (is_branch_taken),
    .pht_index_in         (pht_index_out),
    .pc_in                (pc_out),
    .is_branch_taken_out  (mod_is_branch_taken),
    .pht_index_out        (mod_pht_index),
    .pc_out               (mod_pc)
  );


  always @(*) begin
    is_branch_in <= 0;
    is_jump_in <= 0;
    is_taken_in <= 0;
    last_pht_index <= 0;
    inst_pc <= 0;
    target_in <= 0;
    flush <= 0;
    stall <= 0;
    exc_pc <= 0;

    `ADD_BRANCH_CHECK(32'hbfc00010, 32'hbfc00000, 0, 1);


    if (`TICK >= 32'h4a && `TICK <= 32'h4e) stall <= 1;



    `DISPLAY("*****  mod_pc  *****", mod_pc);
    `END_AT_TICK(100);
  end

endmodule
module PC_tb(
  input clk,
  input rst
);



  `GEN_TICK(clk, rst);


  reg is_branch_in, is_jump_in, is_taken_in, flush, stall;
  reg[`GHR_BUS] last_pht_index;
  reg[`ADDR_BUS] inst_pc, target_in, exc_pc;
  wire is_branch_taken;
  wire[`GHR_BUS] pht_index_out;
  wire[`ADDR_BUS] pc_out;

  wire mod_is_branch_taken;
  wire[`GHR_BUS] mod_pht_index;
  wire[`ADDR_BUS] mod_pc;

  PC stage_pc(
    .clk                  (clk),
    .rst                  (rst),

    .is_branch_in         (is_branch_in),
    .is_jump_in           (is_jump_in),
    .is_taken_in          (is_taken_in),
    .last_pht_index       (last_pht_index),
    .inst_pc              (inst_pc),
    .target_in            (target_in),

    .flush                (flush),
    .stall                (stall),
    .exc_pc               (exc_pc),

    .is_branch_taken      (is_branch_taken),
    .pht_index_out        (pht_index_out),
    .pc_out               (pc_out)
  );

  PCIF pcif_mid(
    .clk                  (clk),
    .rst                  (rst),
    .flush                (flush),
    .stall_current_stage  (stall),
    .stall_next_stage     (stall),
    .is_branch_taken_in   (is_branch_taken),
    .pht_index_in         (pht_index_out),
    .pc_in                (pc_out),
    .is_branch_taken_out  (mod_is_branch_taken),
    .pht_index_out        (mod_pht_index),
    .pc_out               (mod_pc)
  );


  always @(*) begin
    is_branch_in <= 0;
    is_jump_in <= 0;
    is_taken_in <= 0;
    last_pht_index <= 0;
    inst_pc <= 0;
    target_in <= 0;
    flush <= 0;
    stall <= 0;
    exc_pc <= 0;

    `ADD_BRANCH_CHECK(32'hbfc00010, 32'hbfc00000, 0, 1);


    if (`TICK >= 32'h4a && `TICK <= 32'h4e) stall <= 1;



    `DISPLAY("*****  mod_pc  *****", mod_pc);
    `END_AT_TICK(100);
  end

endmodule