data/full_repos/permissive/201488448/2_circuits/2_sequential/fsm/26_fsmlogic.v
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data/verilator_xmls/d2be2c0f-1b18-49d8-a363-8a8564f3aca4.xml
module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);

    reg	[2:0]	Y;
    
    always@(*) begin
        case({y, x})
            4'b0000:	Y = 3'b000;
            4'b0001:	Y = 3'b001;
            4'b0010:	Y = 3'b001;
            4'b0011:	Y = 3'b100;
            4'b0100:	Y = 3'b010;
            4'b0101:	Y = 3'b001;
            4'b0110:	Y = 3'b001;
            4'b0111:	Y = 3'b010;
            4'b1000:	Y = 3'b011;
            4'b1001:	Y = 3'b100;
        endcase
    end
    
    assign	z = (y == 3'b011 || y == 3'b100);
    assign Y0 = Y[0];
    
endmodule
module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);


    reg	[2:0]	Y;
    
    always@(*) begin
        case({y, x})
            4'b0000:	Y = 3'b000;
            4'b0001:	Y = 3'b001;
            4'b0010:	Y = 3'b001;
            4'b0011:	Y = 3'b100;
            4'b0100:	Y = 3'b010;
            4'b0101:	Y = 3'b001;
            4'b0110:	Y = 3'b001;
            4'b0111:	Y = 3'b010;
            4'b1000:	Y = 3'b011;
            4'b1001:	Y = 3'b100;
        endcase
    end
    
    assign	z = (y == 3'b011 || y == 3'b100);
    assign Y0 = Y[0];
    
endmodule