data/full_repos/permissive/106029354/verilog_source/mem_data.v
None: at end of input
1: b'%Error: data/full_repos/permissive/106029354/verilog_source/mem_data.v:10: Cannot find include file: params_proc.v\n`include "params_proc.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n             params_proc.v\n             params_proc.v.v\n             params_proc.v.sv\n             obj_dir/params_proc.v\n             obj_dir/params_proc.v.v\n             obj_dir/params_proc.v.sv\n%Error: Exiting due to 1 error(s)\n'
module mem_data(
	clk,
	we,
	addr,
	data_in,
	data_out
);


`include "params_proc.v"


input clk, we;
input [MEM_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data_in;

output reg [DATA_WIDTH-1:0] data_out;


reg [DATA_WIDTH-1:0] mem [0:(1<<MEM_WIDTH)-1];

always @(posedge clk) begin
	if (we) begin
		mem[addr] <= data_in;

		data_out  <= data_in;
	end else begin
		data_out <= mem[addr];
	end
end

endmodule
module mem_data(
	clk,
	we,
	addr,
	data_in,
	data_out
);



`include "params_proc.v"


input clk, we;
input [MEM_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data_in;

output reg [DATA_WIDTH-1:0] data_out;


reg [DATA_WIDTH-1:0] mem [0:(1<<MEM_WIDTH)-1];

always @(posedge clk) begin
	if (we) begin
		mem[addr] <= data_in;

		data_out  <= data_in;
	end else begin
		data_out <= mem[addr];
	end
end

endmodule