data/full_repos/permissive/201488448/2_circuits/2_sequential/30_lfsr5.v
1: b'%Warning-WIDTH: data/full_repos/permissive/201488448/2_circuits/2_sequential/30_lfsr5.v:15: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                          : ... In instance top_module\n  q_next = q[4:1];  \n         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top_module(
	input clk,
	input reset,
	output reg [4:0] q);
	
	reg [4:0] q_next;







	always @(*) begin
		q_next = q[4:1];
		q_next[4] = q[0];
		q_next[2] = q[3] ^ q[0];
	end
	
	




	always @(posedge clk) begin
		if (reset)
			q <= 5'h1;
		else
			q <= q_next;
	end
	
endmodule
module top_module(
	input clk,
	input reset,
	output reg [4:0] q);

	
	reg [4:0] q_next;







	always @(*) begin
		q_next = q[4:1];
		q_next[4] = q[0];
		q_next[2] = q[3] ^ q[0];
	end
	
	




	always @(posedge clk) begin
		if (reset)
			q <= 5'h1;
		else
			q <= q_next;
	end
	
endmodule