data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/220229160/ql-qlf-plugin/tests/qlf_k6n10f/bram_asymmetric_wider_write/bram_asymmetric_wider_write.v:45: Multiple top level modules\n                                                                                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                                   : ... Top module \'spram_16x1024_8x2048\'\nmodule spram_16x1024_8x2048 (\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                                                                                   : ... Top module \'spram_16x2048_8x4096\'\nmodule spram_16x2048_8x4096 (\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                                                                                   : ... Top module \'spram_32x1024_16x2048\'\nmodule spram_32x1024_16x2048 (\n       ^~~~~~~~~~~~~~~~~~~~~\n                                                                                                                                                   : ... Top module \'spram_32x1024_8x4096\'\nmodule spram_32x1024_8x4096 (\n       ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module spram_32x1024_16x2048 (
	clk,
	rce,
	ra,
	rq,
	wce,
	wa,
	wd
);
	input clk;
	input rce;
	input [10:0] ra;
	output reg [15:0] rq;
	input wce;
	input [9:0] wa;
	input [31:0] wd;
	reg [31:0] memory [0:1023];
	always @(posedge clk) begin
		if (rce)
			rq <= memory[ra / 2][(ra % 2) * 16+:16];
		if (wce)
			memory[wa] <= wd;
	end
	integer i;
	initial for (i = 0; i < 1024; i = i + 1)
		memory[i] = 0;
endmodule
module spram_32x1024_16x2048 (
	clk,
	rce,
	ra,
	rq,
	wce,
	wa,
	wd
);

	input clk;
	input rce;
	input [10:0] ra;
	output reg [15:0] rq;
	input wce;
	input [9:0] wa;
	input [31:0] wd;
	reg [31:0] memory [0:1023];
	always @(posedge clk) begin
		if (rce)
			rq <= memory[ra / 2][(ra % 2) * 16+:16];
		if (wce)
			memory[wa] <= wd;
	end
	integer i;
	initial for (i = 0; i < 1024; i = i + 1)
		memory[i] = 0;
endmodule