data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/xilinx/RAMB16X32X8_TDP.v
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/xilinx/RAMB16X32X8_TDP.v:122: Cannot find file containing module: 'RAMB16BWER'\n   RAMB16BWER\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/xilinx,data/full_repos/permissive/20430511/RAMB16BWER\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/xilinx,data/full_repos/permissive/20430511/RAMB16BWER.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/xilinx,data/full_repos/permissive/20430511/RAMB16BWER.sv\n             RAMB16BWER\n             RAMB16BWER.v\n             RAMB16BWER.sv\n             obj_dir/RAMB16BWER\n             obj_dir/RAMB16BWER.v\n             obj_dir/RAMB16BWER.sv\n%Error: Exiting due to 1 error(s)\n"
module RAMB16X32X8_TDP #(parameter DELAY = 3)
   (
    input         CLKA,
    input         ENA,
    input [3:0]   WEA,
    input [8:0]   ADDRA,
    input [31:0]  DIA,
    output [31:0] DOA,

    input         CLKB,
    input         ENB,
    input         WEB,
    input [10:0]  ADDRB,
    input [7:0]   DIB,
    output [7:0]  DOB
    );


`ifdef __icarus



   reg [7:0]     sram0[0:511];
   reg [7:0]     sram1[0:511];
   reg [7:0]     sram2[0:511];
   reg [7:0]     sram3[0:511];

   reg [31:0]    reg_DOA = 32'h0;
   reg [7:0]     reg_DOB = 8'h0;

   assign DOA = reg_DOA;
   assign DOB = reg_DOB;

   always @(posedge CLKA)
     if (ENA) begin
        if (WEA[0]) sram0[ADDRA] <= #DELAY DIA[7:0];
        if (WEA[1]) sram1[ADDRA] <= #DELAY DIA[15:8];
        if (WEA[2]) sram2[ADDRA] <= #DELAY DIA[23:16];
        if (WEA[3]) sram3[ADDRA] <= #DELAY DIA[31:24];
        reg_DOA <= #DELAY {sram3[ADDRA], sram2[ADDRA], sram1[ADDRA], sram0[ADDRA]};
     end

   always @(posedge CLKB)
     if (ENB) begin
        if (WEB)
          case (ADDRB[1:0])
            2'b00: sram0[ADDRB[10:2]] <= #DELAY DIB;
            2'b01: sram1[ADDRB[10:2]] <= #DELAY DIB;
            2'b10: sram2[ADDRB[10:2]] <= #DELAY DIB;
            2'b11: sram3[ADDRB[10:2]] <= #DELAY DIB;
          endcase
        case (ADDRB[1:0])
          2'b00: reg_DOB <= #DELAY sram0[ADDRB[10:2]];
          2'b01: reg_DOB <= #DELAY sram1[ADDRB[10:2]];
          2'b10: reg_DOB <= #DELAY sram2[ADDRB[10:2]];
          2'b11: reg_DOB <= #DELAY sram3[ADDRB[10:2]];
        endcase
     end


`else



   wire [13:0]   ADRA = {ADDRA, 5'b0};
   wire [13:0]   ADRB = {ADDRB, 3'b0};
   wire [31:0]   DOB_w;

   assign DOB = DOB_w[7:0];

   RAMB16BWER
     #(.DATA_WIDTH_A(36),
       .DATA_WIDTH_B(9),
       .DOA_REG(0),
       .DOB_REG(0),
       .EN_RSTRAM_A("FALSE"),
       .EN_RSTRAM_B("FALSE"),
       .INIT_A(36'h0),
       .INIT_B(36'h0),
       .INIT_FILE("NONE"),
       .RSTTYPE("SYNC"),
       .RST_PRIORITY_A("CE"),
       .RST_PRIORITY_B("CE"),
       .SIM_COLLISION_CHECK("NONE"),
       .SRVAL_A(36'h0),
       .SRVAL_B(36'h0),

       .WRITE_MODE_A("WRITE_FIRST"),
       .WRITE_MODE_B("WRITE_FIRST") 
   )
   SRAM0
     (
       .CLKA(CLKA),
       .RSTA(1'b0),
       .REGCEA(1'b0),
       .ENA(ENA),
       .WEA({2'b00, WEA}),
       .ADDRA(ADRA),
       .DIA({16'h0, DIA}),
       .DIPA(4'h0),
       .DOA(DOA),
       .DOPA(),

       .CLKB(CLKB),
       .RSTB(1'b0),
       .REGCEB(1'b0),
       .ENB(ENB),
       .WEB({3'h0, WEB}),
       .ADDRB(ADRB),
       .DIB({24'h0, DIB}),
       .DIPB(4'h0),
       .DOB(DOB_w),
       .DOPB()
       );
`endif


endmodule
module RAMB16X32X8_TDP #(parameter DELAY = 3)
   (
    input         CLKA,
    input         ENA,
    input [3:0]   WEA,
    input [8:0]   ADDRA,
    input [31:0]  DIA,
    output [31:0] DOA,

    input         CLKB,
    input         ENB,
    input         WEB,
    input [10:0]  ADDRB,
    input [7:0]   DIB,
    output [7:0]  DOB
    );



`ifdef __icarus



   reg [7:0]     sram0[0:511];
   reg [7:0]     sram1[0:511];
   reg [7:0]     sram2[0:511];
   reg [7:0]     sram3[0:511];

   reg [31:0]    reg_DOA = 32'h0;
   reg [7:0]     reg_DOB = 8'h0;

   assign DOA = reg_DOA;
   assign DOB = reg_DOB;

   always @(posedge CLKA)
     if (ENA) begin
        if (WEA[0]) sram0[ADDRA] <= #DELAY DIA[7:0];
        if (WEA[1]) sram1[ADDRA] <= #DELAY DIA[15:8];
        if (WEA[2]) sram2[ADDRA] <= #DELAY DIA[23:16];
        if (WEA[3]) sram3[ADDRA] <= #DELAY DIA[31:24];
        reg_DOA <= #DELAY {sram3[ADDRA], sram2[ADDRA], sram1[ADDRA], sram0[ADDRA]};
     end

   always @(posedge CLKB)
     if (ENB) begin
        if (WEB)
          case (ADDRB[1:0])
            2'b00: sram0[ADDRB[10:2]] <= #DELAY DIB;
            2'b01: sram1[ADDRB[10:2]] <= #DELAY DIB;
            2'b10: sram2[ADDRB[10:2]] <= #DELAY DIB;
            2'b11: sram3[ADDRB[10:2]] <= #DELAY DIB;
          endcase
        case (ADDRB[1:0])
          2'b00: reg_DOB <= #DELAY sram0[ADDRB[10:2]];
          2'b01: reg_DOB <= #DELAY sram1[ADDRB[10:2]];
          2'b10: reg_DOB <= #DELAY sram2[ADDRB[10:2]];
          2'b11: reg_DOB <= #DELAY sram3[ADDRB[10:2]];
        endcase
     end


`else



   wire [13:0]   ADRA = {ADDRA, 5'b0};
   wire [13:0]   ADRB = {ADDRB, 3'b0};
   wire [31:0]   DOB_w;

   assign DOB = DOB_w[7:0];

   RAMB16BWER
     #(.DATA_WIDTH_A(36),
       .DATA_WIDTH_B(9),
       .DOA_REG(0),
       .DOB_REG(0),
       .EN_RSTRAM_A("FALSE"),
       .EN_RSTRAM_B("FALSE"),
       .INIT_A(36'h0),
       .INIT_B(36'h0),
       .INIT_FILE("NONE"),
       .RSTTYPE("SYNC"),
       .RST_PRIORITY_A("CE"),
       .RST_PRIORITY_B("CE"),
       .SIM_COLLISION_CHECK("NONE"),
       .SRVAL_A(36'h0),
       .SRVAL_B(36'h0),

       .WRITE_MODE_A("WRITE_FIRST"),
       .WRITE_MODE_B("WRITE_FIRST") 
   )
   SRAM0
     (
       .CLKA(CLKA),
       .RSTA(1'b0),
       .REGCEA(1'b0),
       .ENA(ENA),
       .WEA({2'b00, WEA}),
       .ADDRA(ADRA),
       .DIA({16'h0, DIA}),
       .DIPA(4'h0),
       .DOA(DOA),
       .DOPA(),

       .CLKB(CLKB),
       .RSTB(1'b0),
       .REGCEB(1'b0),
       .ENB(ENB),
       .WEB({3'h0, WEB}),
       .ADDRB(ADRB),
       .DIB({24'h0, DIB}),
       .DIPB(4'h0),
       .DOB(DOB_w),
       .DOPB()
       );
`endif


endmodule