data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp/mac_cam_lut.v
 line:57: before: "integer"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp/mac_cam_lut.v:140: Signal definition not found, creating implicitly: \'entry_needs_update\'\n   assign entry_needs_update = ((rd_oq!=src_port_decoded) && !rd_wr_protect);\n          ^~~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp/mac_cam_lut.v:107: Cannot find file containing module: \'cam_16x48\'\n   cam_16x48 mac_cam\n   ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp,data/full_repos/permissive/121277233/cam_16x48\n             data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp,data/full_repos/permissive/121277233/cam_16x48.v\n             data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp,data/full_repos/permissive/121277233/cam_16x48.sv\n             cam_16x48\n             cam_16x48.v\n             cam_16x48.sv\n             obj_dir/cam_16x48\n             obj_dir/cam_16x48.v\n             obj_dir/cam_16x48.sv\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp/mac_cam_lut.v:165: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                     : ... In instance mac_cam_lut\n              cam_wr_addr_next = reset_count;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp/mac_cam_lut.v:169: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                     : ... In instance mac_cam_lut\n              lut_wr_addr_next = reset_count;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp/mac_cam_lut.v:175: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                     : ... In instance mac_cam_lut\n              cam_wr_addr_next = reset_count;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/121277233/ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp/mac_cam_lut.v:180: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'reset_count\' generates 5 bits.\n                                                                                                                                                     : ... In instance mac_cam_lut\n              lut_wr_addr_next = reset_count;\n                               ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction
function integer log2;

      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction