data/full_repos/permissive/137454634/rq_process.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/137454634/rq_process.v:88: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'rq_process\'\nmodule rq_process(eff_req,ud_mode,upReq_reg,downReq_reg,hst_down,clk,upReq,downReq,inEleReq,position);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'rq_interface\'\nmodule rq_interface(upReq,downReq,upInput,downInput);\n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module rq_process(eff_req,ud_mode,upReq_reg,downReq_reg,hst_down,clk,upReq,downReq,inEleReq,position);

input clk;
input [3:0] upReq,downReq,inEleReq,position;
output reg [1:0] ud_mode;
output reg [3:0] eff_req;
output reg [3:0] upReq_reg=4'd0;
output reg [3:0] downReq_reg=4'd0;
reg [3:0] inEleReq_reg=4'd0;
reg [3:0] allReq_reg;
output reg [3:0] hst_down;
reg [3:0] lst_up;

always @(posedge clk)
    begin
		if(|(4'b1000 & downReq_reg)==1) hst_down = 4'b1000;
		else if(|(4'b0100 & downReq_reg)==1) hst_down = 4'b0100;
		else if(|(4'b0010 & downReq_reg)==1) hst_down = 4'b0010;
		else hst_down = 4'b0000;
		if(|(4'b0001 & upReq_reg)==1) lst_up = 4'b0001;
		else if(|(4'b0010 & upReq_reg)==1) lst_up = 4'b0010;
		else if(|(4'b0100 & upReq_reg)==1) lst_up = 4'b0100;
		else lst_up = 4'b0000;

		upReq_reg=upReq | upReq_reg;     
        downReq_reg=downReq | downReq_reg; 
        inEleReq_reg=inEleReq | inEleReq_reg;
		allReq_reg = upReq_reg|downReq_reg|inEleReq_reg;
		if (allReq_reg==4'b0000) ud_mode=2'b00;

		if (ud_mode==2'b00)
		begin
			allReq_reg = upReq_reg|downReq_reg|inEleReq_reg;
			if (position<allReq_reg && allReq_reg!=4'b0000) ud_mode=2'b01;
            else if (position>allReq_reg && allReq_reg!=4'b0000) ud_mode=2'b10;
		end
		if (ud_mode==2'b01)
		begin
			upReq_reg    = upReq_reg    & (~position);
			inEleReq_reg = inEleReq_reg & (~position);
			if (position==hst_down && hst_down>upReq_reg) 
			begin				
				downReq_reg  = downReq_reg & (~position);
				eff_req = eff_req & (~position);
				ud_mode=2'b00;
			end
			eff_req = ((~(position-4'b0001)) & (upReq_reg | inEleReq_reg));
			if (hst_down>upReq_reg) eff_req = (hst_down | eff_req) & (~position);
			if (eff_req != 4'b0000) ud_mode = 2'b01;
			else ud_mode = 2'b00;
		end
		if (ud_mode==2'b10)
		begin
				downReq_reg  = (downReq_reg  & (~position));
				inEleReq_reg = (inEleReq_reg & (~position));
			if (position==lst_up && (lst_up<downReq_reg || downReq_reg==4'b0000))
			begin
				upReq_reg = upReq_reg & (~position);
				eff_req = eff_req & (~position);
				ud_mode=2'b00;
			end
			else
			begin
				eff_req = ((position-4'b0001) & (downReq_reg | inEleReq_reg));
				if (lst_up<downReq_reg || downReq_reg==4'b0000) eff_req = (lst_up | eff_req) & (~position);
				if (eff_req != 4'b0000) ud_mode = 2'b10;
				else ud_mode = 2'b00;
			end
		end
	end

endmodule
module rq_process(eff_req,ud_mode,upReq_reg,downReq_reg,hst_down,clk,upReq,downReq,inEleReq,position);


input clk;
input [3:0] upReq,downReq,inEleReq,position;
output reg [1:0] ud_mode;
output reg [3:0] eff_req;
output reg [3:0] upReq_reg=4'd0;
output reg [3:0] downReq_reg=4'd0;
reg [3:0] inEleReq_reg=4'd0;
reg [3:0] allReq_reg;
output reg [3:0] hst_down;
reg [3:0] lst_up;

always @(posedge clk)
    begin
		if(|(4'b1000 & downReq_reg)==1) hst_down = 4'b1000;
		else if(|(4'b0100 & downReq_reg)==1) hst_down = 4'b0100;
		else if(|(4'b0010 & downReq_reg)==1) hst_down = 4'b0010;
		else hst_down = 4'b0000;
		if(|(4'b0001 & upReq_reg)==1) lst_up = 4'b0001;
		else if(|(4'b0010 & upReq_reg)==1) lst_up = 4'b0010;
		else if(|(4'b0100 & upReq_reg)==1) lst_up = 4'b0100;
		else lst_up = 4'b0000;

		upReq_reg=upReq | upReq_reg;     
        downReq_reg=downReq | downReq_reg; 
        inEleReq_reg=inEleReq | inEleReq_reg;
		allReq_reg = upReq_reg|downReq_reg|inEleReq_reg;
		if (allReq_reg==4'b0000) ud_mode=2'b00;

		if (ud_mode==2'b00)
		begin
			allReq_reg = upReq_reg|downReq_reg|inEleReq_reg;
			if (position<allReq_reg && allReq_reg!=4'b0000) ud_mode=2'b01;
            else if (position>allReq_reg && allReq_reg!=4'b0000) ud_mode=2'b10;
		end
		if (ud_mode==2'b01)
		begin
			upReq_reg    = upReq_reg    & (~position);
			inEleReq_reg = inEleReq_reg & (~position);
			if (position==hst_down && hst_down>upReq_reg) 
			begin				
				downReq_reg  = downReq_reg & (~position);
				eff_req = eff_req & (~position);
				ud_mode=2'b00;
			end
			eff_req = ((~(position-4'b0001)) & (upReq_reg | inEleReq_reg));
			if (hst_down>upReq_reg) eff_req = (hst_down | eff_req) & (~position);
			if (eff_req != 4'b0000) ud_mode = 2'b01;
			else ud_mode = 2'b00;
		end
		if (ud_mode==2'b10)
		begin
				downReq_reg  = (downReq_reg  & (~position));
				inEleReq_reg = (inEleReq_reg & (~position));
			if (position==lst_up && (lst_up<downReq_reg || downReq_reg==4'b0000))
			begin
				upReq_reg = upReq_reg & (~position);
				eff_req = eff_req & (~position);
				ud_mode=2'b00;
			end
			else
			begin
				eff_req = ((position-4'b0001) & (downReq_reg | inEleReq_reg));
				if (lst_up<downReq_reg || downReq_reg==4'b0000) eff_req = (lst_up | eff_req) & (~position);
				if (eff_req != 4'b0000) ud_mode = 2'b10;
				else ud_mode = 2'b00;
			end
		end
	end

endmodule