data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:3: Cannot find include file: cpu.v\n`include "cpu.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/cpu,data/full_repos/permissive/200314387/cpu.v\n             data/full_repos/permissive/200314387/verilog/cpu,data/full_repos/permissive/200314387/cpu.v.v\n             data/full_repos/permissive/200314387/verilog/cpu,data/full_repos/permissive/200314387/cpu.v.sv\n             cpu.v\n             cpu.v.v\n             cpu.v.sv\n             obj_dir/cpu.v\n             obj_dir/cpu.v.v\n             obj_dir/cpu.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:4: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:5: Cannot find include file: psuedo_assembler.sv\n`include "psuedo_assembler.sv" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:6: Cannot find include file: control_lines.v\n`include "control_lines.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:54: Cannot find include file: ../lib/display_snippet.sv\n   `include "../lib/display_snippet.sv" \n            ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:16: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n    import alu_ops::*;\n           ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:64: Define or directive not defined: \'`DEFINE_CODE_VARS\'\n    `DEFINE_CODE_VARS(MAX_PC)\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:64: syntax error, unexpected \'(\'\n    `DEFINE_CODE_VARS(MAX_PC)\n                      ^~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:88: Define or directive not defined: \'`DEV_EQ_IMMED8\'\n        `DEV_EQ_IMMED8(icount, rega, 1); icount++;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:88: syntax error, unexpected \',\'\n        `DEV_EQ_IMMED8(icount, rega, 1); icount++;\n                             ^\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:89: Define or directive not defined: \'`DEV_EQ_IMMED8\'\n        `DEV_EQ_IMMED8(icount, regb, 2); icount++;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:89: syntax error, unexpected \',\'\n        `DEV_EQ_IMMED8(icount, regb, 2); icount++;\n                             ^\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:90: Define or directive not defined: \'`JMP_IMMED16\'\n        `JMP_IMMED16(icount, 1024); icount+=2; \n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:90: syntax error, unexpected \',\'\n        `JMP_IMMED16(icount, 1024); icount+=2; \n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:92: Define or directive not defined: \'`JMP_IMMED16\'\n        `JMP_IMMED16(icount, 0); icount+=2; \n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:92: syntax error, unexpected \',\'\n        `JMP_IMMED16(icount, 0); icount+=2; \n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:106: Define or directive not defined: \'`ROM\'\n            data = `ROM(addr);\n                   ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:108: Unsupported: Ignoring delay on this delayed statement.\n            #1000\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/200314387/verilog/cpu/prog_hardware_jumps.v:124: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                );\n                ^\n%Error: Exiting due to 18 error(s), 1 warning(s)\n'
function string disasm([47:0] INSTRUCTION);
         reg [4:0] i_aluop;
         reg [3:0] i_target;
         reg [2:0] i_srca;
         reg [2:0] i_srcb;
         reg [3:0] i_cond;
         reg i_flag;
         reg [2:0] i_nu;
         reg i_amode;
         reg [23:8] i_addr ;
         reg [7:0] i_immed;
    begin
         i_aluop = INSTRUCTION[47:43]; 
         i_target = INSTRUCTION[42:39]; 
         i_srca = INSTRUCTION[38:36]; 
         i_srcb = INSTRUCTION[35:33]; 
         i_cond = INSTRUCTION[32:29]; 
         i_flag = INSTRUCTION[28]; 
         i_nu   = INSTRUCTION[27:25]; 
         i_amode= INSTRUCTION[24]; 
         i_addr = INSTRUCTION[23:8]; 
         i_immed= INSTRUCTION[7:0]; 
        disasm = $sformatf("aluop:%-10ss(%d)  target:%-10s(%d) a:%-5s(%d)  b:%-10s(%d)  cond:%s(%d) setf:%s amode:%s addr:%4x immed8:%2x", 
                    aluopName(i_aluop), i_aluop,
                    tdevname(i_target), i_target,
                    adevname(i_srca),  i_srca,
                    bdevname(i_srcb),  i_srcb,
                    condname(i_cond),  i_cond,
                    (i_flag? "NOSET" : "SET"), 
                    (i_amode?  "DIR": "REG"), 
                    i_addr, 
                    i_immed); 
    end 
    endfunction
function string disasm([47:0] INSTRUCTION);

         reg [4:0] i_aluop;
         reg [3:0] i_target;
         reg [2:0] i_srca;
         reg [2:0] i_srcb;
         reg [3:0] i_cond;
         reg i_flag;
         reg [2:0] i_nu;
         reg i_amode;
         reg [23:8] i_addr ;
         reg [7:0] i_immed;
    begin
         i_aluop = INSTRUCTION[47:43]; 
         i_target = INSTRUCTION[42:39]; 
         i_srca = INSTRUCTION[38:36]; 
         i_srcb = INSTRUCTION[35:33]; 
         i_cond = INSTRUCTION[32:29]; 
         i_flag = INSTRUCTION[28]; 
         i_nu   = INSTRUCTION[27:25]; 
         i_amode= INSTRUCTION[24]; 
         i_addr = INSTRUCTION[23:8]; 
         i_immed= INSTRUCTION[7:0]; 
        disasm = $sformatf("aluop:%-10ss(%d)  target:%-10s(%d) a:%-5s(%d)  b:%-10s(%d)  cond:%s(%d) setf:%s amode:%s addr:%4x immed8:%2x", 
                    aluopName(i_aluop), i_aluop,
                    tdevname(i_target), i_target,
                    adevname(i_srca),  i_srca,
                    bdevname(i_srcb),  i_srcb,
                    condname(i_cond),  i_cond,
                    (i_flag? "NOSET" : "SET"), 
                    (i_amode?  "DIR": "REG"), 
                    i_addr, 
                    i_immed); 
    end 
    endfunction