data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/new/cu.v
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data/verilator_xmls/e0e1e79b-7896-49ad-a8d3-d3833a3fa435.xml
module cu(

    input clk,
    input resetn,
    

    input IF_over,
    input ID_over,
    input EXE_over,
    input MEM_over,
    input WB_over,
    input cancel, 



    output IFTOID,
    output IDTOEX,
    output EXTOMEM,
    output MEMTOWB,
    output MEM_allow_in,
    
    


    output reg IF_valid,
    output reg ID_valid,
    output reg EXE_valid,
    output reg MEM_valid,
    output reg WB_valid,
    output next_fetch,
    

    output[31:0]cpu_5_valid
    );

    



    wire IF_allow_in;
    wire ID_allow_in;
    wire EXE_allow_in;
    wire WB_allow_in;


    assign next_fetch = IF_allow_in;
    

    assign IF_allow_in  = (IF_over & ID_allow_in) | cancel;
    assign ID_allow_in  = ~ID_valid  | (ID_over  & EXE_allow_in);
    assign EXE_allow_in = ~EXE_valid | (EXE_over & MEM_allow_in);
    assign MEM_allow_in = ~MEM_valid | (MEM_over & WB_allow_in );
    assign WB_allow_in  = ~WB_valid  | WB_over;

   

   always @(posedge clk)
    begin
        if (!resetn) IF_valid <= 1'b0;
        else IF_valid <= 1'b1;

        if (!resetn || cancel)ID_valid <= 1'b0;
        else if (ID_allow_in) ID_valid <= IF_over;

        if (!resetn || cancel) EXE_valid <= 1'b0;
        else if (EXE_allow_in) EXE_valid <= ID_over;

        if (!resetn || cancel) MEM_valid <= 1'b0;
        else if (MEM_allow_in) MEM_valid <= EXE_over;

        if (!resetn || cancel)WB_valid <= 1'b0;
        else if (WB_allow_in) WB_valid <= MEM_over;
    end
    

    assign cpu_5_valid = {12'd0         ,{4{IF_valid }},{4{ID_valid}},
                          {4{EXE_valid}},{4{MEM_valid}},{4{WB_valid}}};




    assign IFTOID = IF_over && ID_allow_in;
    assign IDTOEX=ID_over && EXE_allow_in;
    assign EXTOMEM=EXE_over && MEM_allow_in;
    assign MEMTOWB=MEM_over && WB_allow_in;

endmodule
module cu(

    input clk,
    input resetn,
    

    input IF_over,
    input ID_over,
    input EXE_over,
    input MEM_over,
    input WB_over,
    input cancel, 



    output IFTOID,
    output IDTOEX,
    output EXTOMEM,
    output MEMTOWB,
    output MEM_allow_in,
    
    


    output reg IF_valid,
    output reg ID_valid,
    output reg EXE_valid,
    output reg MEM_valid,
    output reg WB_valid,
    output next_fetch,
    

    output[31:0]cpu_5_valid
    );


    



    wire IF_allow_in;
    wire ID_allow_in;
    wire EXE_allow_in;
    wire WB_allow_in;


    assign next_fetch = IF_allow_in;
    

    assign IF_allow_in  = (IF_over & ID_allow_in) | cancel;
    assign ID_allow_in  = ~ID_valid  | (ID_over  & EXE_allow_in);
    assign EXE_allow_in = ~EXE_valid | (EXE_over & MEM_allow_in);
    assign MEM_allow_in = ~MEM_valid | (MEM_over & WB_allow_in );
    assign WB_allow_in  = ~WB_valid  | WB_over;

   

   always @(posedge clk)
    begin
        if (!resetn) IF_valid <= 1'b0;
        else IF_valid <= 1'b1;

        if (!resetn || cancel)ID_valid <= 1'b0;
        else if (ID_allow_in) ID_valid <= IF_over;

        if (!resetn || cancel) EXE_valid <= 1'b0;
        else if (EXE_allow_in) EXE_valid <= ID_over;

        if (!resetn || cancel) MEM_valid <= 1'b0;
        else if (MEM_allow_in) MEM_valid <= EXE_over;

        if (!resetn || cancel)WB_valid <= 1'b0;
        else if (WB_allow_in) WB_valid <= MEM_over;
    end
    

    assign cpu_5_valid = {12'd0         ,{4{IF_valid }},{4{ID_valid}},
                          {4{EXE_valid}},{4{MEM_valid}},{4{WB_valid}}};




    assign IFTOID = IF_over && ID_allow_in;
    assign IDTOEX=ID_over && EXE_allow_in;
    assign EXTOMEM=EXE_over && MEM_allow_in;
    assign MEMTOWB=MEM_over && WB_allow_in;

endmodule