data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v
 line:64: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:29: Unsupported: Ignoring delay on this delayed statement.\n #step;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #step;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:40: Unsupported: Ignoring delay on this delayed statement.\n #(step*7);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:46: Unsupported: Ignoring delay on this delayed statement.\n #8 clk = !clk;\n ^\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:52: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("wf_n2one.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:53: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, tb_n2one);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:56: Unsupported: Ignoring delay on this delayed statement.\n #step;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:58: Unsupported: Ignoring delay on this delayed statement.\n #step;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:60: Unsupported: Ignoring delay on this delayed statement.\n #step;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:65: Unsupported: Ignoring delay on this delayed statement.\n   #(step*5);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #(step*10);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:70: Unsupported: Ignoring delay on this delayed statement.\n #(step*100);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:80: Unsupported: Ignoring delay on this delayed statement.\n   #(step*5);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #(step*10);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:86: Unsupported: Ignoring delay on this delayed statement.\n #(step*100);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:94: Unsupported: Ignoring delay on this delayed statement.\n   #(step*5);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #(step*10);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:100: Unsupported: Ignoring delay on this delayed statement.\n #(step*100);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:107: Unsupported: Ignoring delay on this delayed statement.\n   #(step*5);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #(step*10);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:111: Unsupported: Ignoring delay on this delayed statement.\n #(step*100);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:117: Unsupported: Ignoring delay on this delayed statement.\n   #(step*5);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #(step*10);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/219917900/rx_rtl_files/sim/tb_n2one.v:121: Unsupported: Ignoring delay on this delayed statement.\n#(step*33);\n^\n%Error: Exiting due to 2 error(s), 22 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_n2one;


reg clk,rst,rxen;
reg [7:0] rxd;

wire loss,en_out;
wire [7:0] data_out;
n2one uut(
	.clk(clk),
	.rst(rst),
	.rxd(rxd),
	.rxen(rxen),
	.redundancy(8'd5),

	.en_out_reg(en_out),
	.data_out_reg(data_out)
);

parameter step = 16;
parameter packetsize = 10;
parameter whereisid = 0;
integer i;
task onepacket;
	input [7:0] id;
	input [31:0] seed;
begin
	#step;
	rxen = 1;
	for (i=0; i<packetsize; i=i+1) begin
		if (i==whereisid)
			rxd = id;
		else if (i == packetsize - 1)
			rxd = 8'hef;
		else rxd = ((seed+3)*packetsize * 33 + i) % 255;
		#step;
	end
	rxen = 0;
	#(step*7);
end
endtask


always begin
	#8 clk = !clk;
	
end

integer j,k,l;
initial begin
	$dumpfile("wf_n2one.vcd");
	$dumpvars(0, tb_n2one);
	clk = 0; rst = 0; rxd = 0; rxen = 0;

	#step;
	rst = 1;
	#step;
	rst = 0;
	#step;
	l=1;
	for (k = 0; k <= 6; k=k+1) begin
		for (j = 1; j <= 5; j=j+1) begin
			onepacket(j,k);
			#(step*5);
		end
		#(step*10);
	end

	#(step*100);
	
	l=2;
	for (k = 0; k <= 6; k=k+1) begin
		for (j = 1; j <= 5; j=j+1) begin
			if (k == j)
			onepacket(j,k*k);
			else
			onepacket(j,k);

			#(step*5);
		end
		#(step*10);
	end
	l=3;

	#(step*100);

	for (k = 0; k <= 7; k=k+1) begin
		for (j = 1; j <= 5; j=j+1) begin
			if (k == j || k == j+1)
			onepacket(j,k*k);
			else 
			onepacket(j,k);
			#(step*5);
		end
		#(step*10);
	end
	l=4;

	#(step*100);
	for (k = 0; k <= 8; k=k+1) begin
		for (j = 1; j <= 5; j=j+1) begin
			if (k == j && k == j+2)
			onepacket(j,k*k);
			else
			onepacket(j,k);
			#(step*5);
		end
		#(step*10);
	end
	#(step*100);
	l=5;
	for (k = 0; k <= 9; k=k+1) begin
		for (j = 1; j <= 5; j=j+1) begin
			if (k != j && k != j+3)
			onepacket(j,k);
			#(step*5);
		end
		#(step*10);
	end
#(step*33);
	$finish;

end
endmodule
module tb_n2one;



reg clk,rst,rxen;
reg [7:0] rxd;

wire loss,en_out;
wire [7:0] data_out;
n2one uut(
	.clk(clk),
	.rst(rst),
	.rxd(rxd),
	.rxen(rxen),
	.redundancy(8'd5),

	.en_out_reg(en_out),
	.data_out_reg(data_out)
);

parameter step = 16;
parameter packetsize = 10;
parameter whereisid = 0;
integer i;
task onepacket;
	input [7:0] id;
	input [31:0] seed;
begin
	#step;
	rxen = 1;
	for (i=0; i<packetsize; i=i+1) begin
		if (i==whereisid)
			rxd = id;
		else if (i == packetsize - 1)
			rxd = 8'hef;
		else rxd = ((seed+3)*packetsize * 33 + i) % 255;
		#step;
	end
	rxen = 0;
	#(step*7);
end
endtask


always begin
	#8 clk = !clk;
	
end

integer j,k,l;
initial begin
	$dumpfile("wf_n2one.vcd");
	$dumpvars(0, tb_n2one);
	clk = 0; rst = 0; rxd = 0; rxen = 0;

	#step;
	rst = 1;
	#step;
	rst = 0;
	#step;
	l=1;
	for (k = 0; k <= 6; k=k+1) begin
		for (j = 1; j <= 5; j=j+1) begin
			onepacket(j,k);
			#(step*5);
		end
		#(step*10);
	end

	#(step*100);
	
	l=2;
	for (k = 0; k <= 6; k=k+1) begin
		for (j = 1; j <= 5; j=j+1) begin
			if (k == j)
			onepacket(j,k*k);
			else
			onepacket(j,k);

			#(step*5);
		end
		#(step*10);
	end
	l=3;

	#(step*100);

	for (k = 0; k <= 7; k=k+1) begin
		for (j = 1; j <= 5; j=j+1) begin
			if (k == j || k == j+1)
			onepacket(j,k*k);
			else 
			onepacket(j,k);
			#(step*5);
		end
		#(step*10);
	end
	l=4;

	#(step*100);
	for (k = 0; k <= 8; k=k+1) begin
		for (j = 1; j <= 5; j=j+1) begin
			if (k == j && k == j+2)
			onepacket(j,k*k);
			else
			onepacket(j,k);
			#(step*5);
		end
		#(step*10);
	end
	#(step*100);
	l=5;
	for (k = 0; k <= 9; k=k+1) begin
		for (j = 1; j <= 5; j=j+1) begin
			if (k != j && k != j+3)
			onepacket(j,k);
			#(step*5);
		end
		#(step*10);
	end
#(step*33);
	$finish;

end
endmodule