data/full_repos/permissive/129659500/PRBS_tb.v
 line:21: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/129659500/PRBS_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129659500/PRBS_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #1000000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/129659500/PRBS_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  always  #1  Clock_M = ~Clock_M;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/129659500/PRBS_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  always  #1  Clock_G = ~Clock_G;\n          ^\n%Error: data/full_repos/permissive/129659500/PRBS_tb.v:28: Cannot find file containing module: \'PRBS\'\n  PRBS DUT(\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/129659500,data/full_repos/permissive/129659500/PRBS\n             data/full_repos/permissive/129659500,data/full_repos/permissive/129659500/PRBS.v\n             data/full_repos/permissive/129659500,data/full_repos/permissive/129659500/PRBS.sv\n             PRBS\n             PRBS.v\n             PRBS.sv\n             obj_dir/PRBS\n             obj_dir/PRBS.v\n             obj_dir/PRBS.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PRBS_tb ();

 reg Clock_G;
 reg Clock_M;
 reg Reset;
 wire lock;
 wire bit_error;


initial begin

    Clock_G = 0;
    Clock_M = 0;
    Reset = 0;
    #10  
    Reset = 1;
    #1000000
    $finish;
  end
  
  always  #1  Clock_M = ~Clock_M;
 
  always  #1  Clock_G = ~Clock_G;

  PRBS DUT(
  	Clock_G,
    Clock_M,
  	Reset,
  	lock,
  	bit_error
    );
 
 endmodule
module PRBS_tb ();


 reg Clock_G;
 reg Clock_M;
 reg Reset;
 wire lock;
 wire bit_error;


initial begin

    Clock_G = 0;
    Clock_M = 0;
    Reset = 0;
    #10  
    Reset = 1;
    #1000000
    $finish;
  end
  
  always  #1  Clock_M = ~Clock_M;
 
  always  #1  Clock_G = ~Clock_G;

  PRBS DUT(
  	Clock_G,
    Clock_M,
  	Reset,
  	lock,
  	bit_error
    );
 
 endmodule