data/full_repos/permissive/1840016/lab2/proj2_testbench.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/1840016/lab2/proj2_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n   #5 clk =~clk;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/1840016/lab2/proj2_testbench.v:26: Cannot find file containing module: \'ripple_adder\'\n   ripple_adder DUT1(A[7:0],B[7:0], 1\'b0, sum[7:0], add1_to_add2);\n   ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/1840016/lab2,data/full_repos/permissive/1840016/ripple_adder\n             data/full_repos/permissive/1840016/lab2,data/full_repos/permissive/1840016/ripple_adder.v\n             data/full_repos/permissive/1840016/lab2,data/full_repos/permissive/1840016/ripple_adder.sv\n             ripple_adder\n             ripple_adder.v\n             ripple_adder.sv\n             obj_dir/ripple_adder\n             obj_dir/ripple_adder.v\n             obj_dir/ripple_adder.sv\n%Error: data/full_repos/permissive/1840016/lab2/proj2_testbench.v:27: Cannot find file containing module: \'ripple_adder\'\n   ripple_adder DUT2(A[15:8],B[15:8], add1_to_add2, sum[15:8], cout);\n   ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module proj2_testbench;

   wire [15:0] sum;
   wire cout;
   wire add1_to_add2;
   reg [15:0] A, B;
   reg clk;

   ripple_adder DUT1(A[7:0],B[7:0], 1'b0, sum[7:0], add1_to_add2);
   ripple_adder DUT2(A[15:8],B[15:8], add1_to_add2, sum[15:8], cout);
   
   always
   #5 clk =~clk;

   initial begin
      clk = 1'b0;
      A = 16'h00;
      B = 16'h00;
   end

   always @(posedge clk)
   A=A+1;

endmodule
module proj2_testbench;


   wire [15:0] sum;
   wire cout;
   wire add1_to_add2;
   reg [15:0] A, B;
   reg clk;

   ripple_adder DUT1(A[7:0],B[7:0], 1'b0, sum[7:0], add1_to_add2);
   ripple_adder DUT2(A[15:8],B[15:8], add1_to_add2, sum[15:8], cout);
   
   always
   #5 clk =~clk;

   initial begin
      clk = 1'b0;
      A = 16'h00;
      B = 16'h00;
   end

   always @(posedge clk)
   A=A+1;

endmodule