data/full_repos/permissive/185658197/src/step-4/verilog/multiplier.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/185658197/src/step-4/verilog/multiplier.v:124: Cell has missing pin: \'c\'\n  Subtractor #(.bits(16)) final_subtractor (\n                          ^~~~~~~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-4/verilog/multiplier.v:30: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                       : ... In instance Multiplier.register1\n  reg [(bits-1):0] state = \'hX;\n                           ^~~\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-4/verilog/multiplier.v:30: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                       : ... In instance Multiplier.register2\n  reg [(bits-1):0] state = \'hX;\n                           ^~~\n%Warning-WIDTH: data/full_repos/permissive/185658197/src/step-4/verilog/multiplier.v:30: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                       : ... In instance Multiplier.register3\n  reg [(bits-1):0] state = \'hX;\n                           ^~~\n%Error: Exiting due to 4 warning(s)\n'
module Register #(parameter bits = 1) (
  input clk,
  input [(bits-1):0]d,
  output [(bits-1):0]q
);
  reg [(bits-1):0] state = 'hX;
  assign q = state;

  always @ (posedge clk) 
    state <= d;
endmodule
module Register #(parameter bits = 1) (
  input clk,
  input [(bits-1):0]d,
  output [(bits-1):0]q
);

  reg [(bits-1):0] state = 'hX;
  assign q = state;

  always @ (posedge clk) 
    state <= d;
endmodule