data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog/okBTPipeOut.v
1: b'%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog/okBTPipeOut.v:23: Cannot find include file: parameters.v\n`include "parameters.v"  \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog,data/full_repos/permissive/120539939/parameters.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog,data/full_repos/permissive/120539939/parameters.v.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog,data/full_repos/permissive/120539939/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Simulation/USB3/Verilog/okBTPipeOut.v:24: Cannot find include file: mappings.v\n`include "mappings.v" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module okBTPipeOut(
	input  wire [112:0] okHE,
	output wire [64:0]  okEH,
	input  wire [7:0]   ep_addr,
	output wire         ep_read,
	output wire         ep_blockstrobe,
	input  wire [31:0]  ep_datain,
	input  wire         ep_ready
	);

`include "parameters.v" 
`include "mappings.v"

assign okEH[okEH_DATAH:okEH_DATAL]  = (ti_addr == ep_addr) ? (ep_datain) : (0);
assign okEH[okEH_READY]             = (ti_addr == ep_addr) ? (ep_ready) : (0);
assign ep_read                      = ((ti_read == 1) && (ti_addr == ep_addr)) ? (1) : (0);
assign ep_blockstrobe               = ti_blockstrobe & (ti_addr == ep_addr);
assign okEH[okEH_REGREADDATAH:okEH_REGREADDATAL] = 32'b0;

endmodule
module okBTPipeOut(
	input  wire [112:0] okHE,
	output wire [64:0]  okEH,
	input  wire [7:0]   ep_addr,
	output wire         ep_read,
	output wire         ep_blockstrobe,
	input  wire [31:0]  ep_datain,
	input  wire         ep_ready
	);


`include "parameters.v" 
`include "mappings.v"

assign okEH[okEH_DATAH:okEH_DATAL]  = (ti_addr == ep_addr) ? (ep_datain) : (0);
assign okEH[okEH_READY]             = (ti_addr == ep_addr) ? (ep_ready) : (0);
assign ep_read                      = ((ti_read == 1) && (ti_addr == ep_addr)) ? (1) : (0);
assign ep_blockstrobe               = ti_blockstrobe & (ti_addr == ep_addr);
assign okEH[okEH_REGREADDATAH:okEH_REGREADDATAL] = 32'b0;

endmodule