data/full_repos/permissive/125531440/core/src/main/verilog/loopback/channel_128.v
1: b'%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/channel_128.v:134: Cannot find include file: functions.vh\n`include "functions.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/functions.vh\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/functions.vh.v\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/functions.vh.sv\n             functions.vh\n             functions.vh.v\n             functions.vh.sv\n             obj_dir/functions.vh\n             obj_dir/functions.vh.v\n             obj_dir/functions.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module channel_128 #(
	parameter C_DATA_WIDTH = 9'd128,
	parameter C_MAX_READ_REQ = 2,

	parameter C_RX_FIFO_DEPTH = 1024,
	parameter C_TX_FIFO_DEPTH = 512,
	parameter C_SG_FIFO_DEPTH = 1024,
	parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
	input CLK,
	input RST,
	input [2:0] CONFIG_MAX_READ_REQUEST_SIZE,
	input [2:0] CONFIG_MAX_PAYLOAD_SIZE,

	input [31:0] PIO_DATA,
	input [C_DATA_WIDTH-1:0] ENG_DATA,

	output SG_RX_BUF_RECVD,
	input SG_RX_BUF_LEN_VALID,
	input SG_RX_BUF_ADDR_HI_VALID,
	input SG_RX_BUF_ADDR_LO_VALID,

	output SG_TX_BUF_RECVD,
	input SG_TX_BUF_LEN_VALID,
	input SG_TX_BUF_ADDR_HI_VALID,
	input SG_TX_BUF_ADDR_LO_VALID,

	input TXN_RX_LEN_VALID,
	input TXN_RX_OFF_LAST_VALID,
	output [31:0] TXN_RX_DONE_LEN,
	output TXN_RX_DONE,
	input TXN_RX_DONE_ACK,

	output TXN_TX,
	input TXN_TX_ACK,
	output [31:0] TXN_TX_LEN,
	output [31:0] TXN_TX_OFF_LAST,
	output [31:0] TXN_TX_DONE_LEN,
	output TXN_TX_DONE,
	input TXN_TX_DONE_ACK,

	output RX_REQ,
	input RX_REQ_ACK,
	output [1:0] RX_REQ_TAG,
	output [63:0] RX_REQ_ADDR,
	output [9:0] RX_REQ_LEN,

	output TX_REQ,
	input TX_REQ_ACK,
	output [63:0] TX_ADDR,
	output [9:0] TX_LEN,
	output [C_DATA_WIDTH-1:0] TX_DATA,
	input TX_DATA_REN,
	input TX_SENT,

	input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,
	input MAIN_DONE,
	input MAIN_ERR,

	input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,
	input SG_RX_DONE,
	input SG_RX_ERR,

	input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,
	input SG_TX_DONE,
	input SG_TX_ERR,

	input CHNL_RX_CLK,
	output CHNL_RX,
	input CHNL_RX_ACK,
	output CHNL_RX_LAST,
	output [31:0] CHNL_RX_LEN,
	output [30:0] CHNL_RX_OFF,
	output [C_DATA_WIDTH-1:0] CHNL_RX_DATA,
	output CHNL_RX_DATA_VALID,
	input CHNL_RX_DATA_REN,

	input CHNL_TX_CLK,
	input CHNL_TX,
	output CHNL_TX_ACK,
	input CHNL_TX_LAST,
	input [31:0] CHNL_TX_LEN,
	input [30:0] CHNL_TX_OFF,
	input [C_DATA_WIDTH-1:0] CHNL_TX_DATA,
	input CHNL_TX_DATA_VALID,
	output CHNL_TX_DATA_REN
);

`include "functions.vh"


wire	[C_DATA_WIDTH-1:0]	wTxSgData;
wire						wTxSgDataEmpty;
wire						wTxSgDataRen;
wire						wTxSgDataErr;
wire						wTxSgDataRst;



rx_port_128 #(
	.C_DATA_WIDTH(C_DATA_WIDTH), 
	.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH), 
	.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
	.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
	.RST(RST), 
	.CLK(CLK), 
	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE), 
	
	.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
	.SG_RX_BUF_DATA(PIO_DATA),
	.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
	.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
	.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
	
	.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
	.SG_TX_BUF_DATA(PIO_DATA),
	.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
	.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
	.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
	
	.SG_DATA(wTxSgData),
	.SG_DATA_EMPTY(wTxSgDataEmpty),
	.SG_DATA_REN(wTxSgDataRen),
	.SG_RST(wTxSgDataRst),
	.SG_ERR(wTxSgDataErr),
	
	.TXN_DATA(PIO_DATA), 
	.TXN_LEN_VALID(TXN_RX_LEN_VALID), 
	.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID), 
	.TXN_DONE_LEN(TXN_RX_DONE_LEN),
	.TXN_DONE(TXN_RX_DONE),
	.TXN_DONE_ACK(TXN_RX_DONE_ACK),
	
	.RX_REQ(RX_REQ),
	.RX_REQ_ACK(RX_REQ_ACK),
	.RX_REQ_TAG(RX_REQ_TAG),
	.RX_REQ_ADDR(RX_REQ_ADDR),
	.RX_REQ_LEN(RX_REQ_LEN),

	.MAIN_DATA(ENG_DATA),
	.MAIN_DATA_EN(MAIN_DATA_EN), 
	.MAIN_DONE(MAIN_DONE), 
	.MAIN_ERR(MAIN_ERR),
	
	.SG_RX_DATA(ENG_DATA),
	.SG_RX_DATA_EN(SG_RX_DATA_EN), 
	.SG_RX_DONE(SG_RX_DONE), 
	.SG_RX_ERR(SG_RX_ERR),

	.SG_TX_DATA(ENG_DATA),
	.SG_TX_DATA_EN(SG_TX_DATA_EN), 
	.SG_TX_DONE(SG_TX_DONE), 
	.SG_TX_ERR(SG_TX_ERR),

	.CHNL_CLK(CHNL_RX_CLK), 
	.CHNL_RX(CHNL_RX), 
	.CHNL_RX_ACK(CHNL_RX_ACK), 
	.CHNL_RX_LAST(CHNL_RX_LAST), 
	.CHNL_RX_LEN(CHNL_RX_LEN), 
	.CHNL_RX_OFF(CHNL_RX_OFF), 
	.CHNL_RX_DATA(CHNL_RX_DATA), 
	.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), 
	.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);



tx_port_128 #(
	.C_DATA_WIDTH(C_DATA_WIDTH), 
	.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
	.CLK(CLK), 
	.RST(RST), 
	.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE), 
	
	.TXN(TXN_TX),
	.TXN_ACK(TXN_TX_ACK),
	.TXN_LEN(TXN_TX_LEN),
	.TXN_OFF_LAST(TXN_TX_OFF_LAST),
	.TXN_DONE_LEN(TXN_TX_DONE_LEN),
	.TXN_DONE(TXN_TX_DONE),
	.TXN_DONE_ACK(TXN_TX_DONE_ACK),
	
	.SG_DATA(wTxSgData),
	.SG_DATA_EMPTY(wTxSgDataEmpty),
	.SG_DATA_REN(wTxSgDataRen),
	.SG_RST(wTxSgDataRst),
	.SG_ERR(wTxSgDataErr),
	
	.TX_REQ(TX_REQ), 
	.TX_REQ_ACK(TX_REQ_ACK),
	.TX_ADDR(TX_ADDR), 
	.TX_LEN(TX_LEN), 
	.TX_DATA(TX_DATA),
	.TX_DATA_REN(TX_DATA_REN), 
	.TX_SENT(TX_SENT),

	.CHNL_CLK(CHNL_TX_CLK), 
	.CHNL_TX(CHNL_TX), 
	.CHNL_TX_ACK(CHNL_TX_ACK),
	.CHNL_TX_LAST(CHNL_TX_LAST), 
	.CHNL_TX_LEN(CHNL_TX_LEN), 
	.CHNL_TX_OFF(CHNL_TX_OFF), 
	.CHNL_TX_DATA(CHNL_TX_DATA), 
	.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID), 
	.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);

endmodule
module channel_128 #(
	parameter C_DATA_WIDTH = 9'd128,
	parameter C_MAX_READ_REQ = 2,

	parameter C_RX_FIFO_DEPTH = 1024,
	parameter C_TX_FIFO_DEPTH = 512,
	parameter C_SG_FIFO_DEPTH = 1024,
	parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
	input CLK,
	input RST,
	input [2:0] CONFIG_MAX_READ_REQUEST_SIZE,
	input [2:0] CONFIG_MAX_PAYLOAD_SIZE,

	input [31:0] PIO_DATA,
	input [C_DATA_WIDTH-1:0] ENG_DATA,

	output SG_RX_BUF_RECVD,
	input SG_RX_BUF_LEN_VALID,
	input SG_RX_BUF_ADDR_HI_VALID,
	input SG_RX_BUF_ADDR_LO_VALID,

	output SG_TX_BUF_RECVD,
	input SG_TX_BUF_LEN_VALID,
	input SG_TX_BUF_ADDR_HI_VALID,
	input SG_TX_BUF_ADDR_LO_VALID,

	input TXN_RX_LEN_VALID,
	input TXN_RX_OFF_LAST_VALID,
	output [31:0] TXN_RX_DONE_LEN,
	output TXN_RX_DONE,
	input TXN_RX_DONE_ACK,

	output TXN_TX,
	input TXN_TX_ACK,
	output [31:0] TXN_TX_LEN,
	output [31:0] TXN_TX_OFF_LAST,
	output [31:0] TXN_TX_DONE_LEN,
	output TXN_TX_DONE,
	input TXN_TX_DONE_ACK,

	output RX_REQ,
	input RX_REQ_ACK,
	output [1:0] RX_REQ_TAG,
	output [63:0] RX_REQ_ADDR,
	output [9:0] RX_REQ_LEN,

	output TX_REQ,
	input TX_REQ_ACK,
	output [63:0] TX_ADDR,
	output [9:0] TX_LEN,
	output [C_DATA_WIDTH-1:0] TX_DATA,
	input TX_DATA_REN,
	input TX_SENT,

	input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN,
	input MAIN_DONE,
	input MAIN_ERR,

	input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN,
	input SG_RX_DONE,
	input SG_RX_ERR,

	input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN,
	input SG_TX_DONE,
	input SG_TX_ERR,

	input CHNL_RX_CLK,
	output CHNL_RX,
	input CHNL_RX_ACK,
	output CHNL_RX_LAST,
	output [31:0] CHNL_RX_LEN,
	output [30:0] CHNL_RX_OFF,
	output [C_DATA_WIDTH-1:0] CHNL_RX_DATA,
	output CHNL_RX_DATA_VALID,
	input CHNL_RX_DATA_REN,

	input CHNL_TX_CLK,
	input CHNL_TX,
	output CHNL_TX_ACK,
	input CHNL_TX_LAST,
	input [31:0] CHNL_TX_LEN,
	input [30:0] CHNL_TX_OFF,
	input [C_DATA_WIDTH-1:0] CHNL_TX_DATA,
	input CHNL_TX_DATA_VALID,
	output CHNL_TX_DATA_REN
);


`include "functions.vh"


wire	[C_DATA_WIDTH-1:0]	wTxSgData;
wire						wTxSgDataEmpty;
wire						wTxSgDataRen;
wire						wTxSgDataErr;
wire						wTxSgDataRst;



rx_port_128 #(
	.C_DATA_WIDTH(C_DATA_WIDTH), 
	.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH), 
	.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
	.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
	.RST(RST), 
	.CLK(CLK), 
	.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE), 
	
	.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
	.SG_RX_BUF_DATA(PIO_DATA),
	.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
	.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
	.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
	
	.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
	.SG_TX_BUF_DATA(PIO_DATA),
	.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
	.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
	.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
	
	.SG_DATA(wTxSgData),
	.SG_DATA_EMPTY(wTxSgDataEmpty),
	.SG_DATA_REN(wTxSgDataRen),
	.SG_RST(wTxSgDataRst),
	.SG_ERR(wTxSgDataErr),
	
	.TXN_DATA(PIO_DATA), 
	.TXN_LEN_VALID(TXN_RX_LEN_VALID), 
	.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID), 
	.TXN_DONE_LEN(TXN_RX_DONE_LEN),
	.TXN_DONE(TXN_RX_DONE),
	.TXN_DONE_ACK(TXN_RX_DONE_ACK),
	
	.RX_REQ(RX_REQ),
	.RX_REQ_ACK(RX_REQ_ACK),
	.RX_REQ_TAG(RX_REQ_TAG),
	.RX_REQ_ADDR(RX_REQ_ADDR),
	.RX_REQ_LEN(RX_REQ_LEN),

	.MAIN_DATA(ENG_DATA),
	.MAIN_DATA_EN(MAIN_DATA_EN), 
	.MAIN_DONE(MAIN_DONE), 
	.MAIN_ERR(MAIN_ERR),
	
	.SG_RX_DATA(ENG_DATA),
	.SG_RX_DATA_EN(SG_RX_DATA_EN), 
	.SG_RX_DONE(SG_RX_DONE), 
	.SG_RX_ERR(SG_RX_ERR),

	.SG_TX_DATA(ENG_DATA),
	.SG_TX_DATA_EN(SG_TX_DATA_EN), 
	.SG_TX_DONE(SG_TX_DONE), 
	.SG_TX_ERR(SG_TX_ERR),

	.CHNL_CLK(CHNL_RX_CLK), 
	.CHNL_RX(CHNL_RX), 
	.CHNL_RX_ACK(CHNL_RX_ACK), 
	.CHNL_RX_LAST(CHNL_RX_LAST), 
	.CHNL_RX_LEN(CHNL_RX_LEN), 
	.CHNL_RX_OFF(CHNL_RX_OFF), 
	.CHNL_RX_DATA(CHNL_RX_DATA), 
	.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), 
	.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);



tx_port_128 #(
	.C_DATA_WIDTH(C_DATA_WIDTH), 
	.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
	.CLK(CLK), 
	.RST(RST), 
	.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE), 
	
	.TXN(TXN_TX),
	.TXN_ACK(TXN_TX_ACK),
	.TXN_LEN(TXN_TX_LEN),
	.TXN_OFF_LAST(TXN_TX_OFF_LAST),
	.TXN_DONE_LEN(TXN_TX_DONE_LEN),
	.TXN_DONE(TXN_TX_DONE),
	.TXN_DONE_ACK(TXN_TX_DONE_ACK),
	
	.SG_DATA(wTxSgData),
	.SG_DATA_EMPTY(wTxSgDataEmpty),
	.SG_DATA_REN(wTxSgDataRen),
	.SG_RST(wTxSgDataRst),
	.SG_ERR(wTxSgDataErr),
	
	.TX_REQ(TX_REQ), 
	.TX_REQ_ACK(TX_REQ_ACK),
	.TX_ADDR(TX_ADDR), 
	.TX_LEN(TX_LEN), 
	.TX_DATA(TX_DATA),
	.TX_DATA_REN(TX_DATA_REN), 
	.TX_SENT(TX_SENT),

	.CHNL_CLK(CHNL_TX_CLK), 
	.CHNL_TX(CHNL_TX), 
	.CHNL_TX_ACK(CHNL_TX_ACK),
	.CHNL_TX_LAST(CHNL_TX_LAST), 
	.CHNL_TX_LEN(CHNL_TX_LEN), 
	.CHNL_TX_OFF(CHNL_TX_OFF), 
	.CHNL_TX_DATA(CHNL_TX_DATA), 
	.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID), 
	.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);

endmodule