data/full_repos/permissive/202237519/verilog/ripple_carry_adder/Demux.v
data/verilator_xmls/d96f0c0d-567f-43cf-8110-c2b3c695f393.xml
module DeMux (In,Out,Sel);

input In;
output [3:0] Out;
input [1:0] Sel;

always @(In,Sel)
begin
    case (Sel)
        2'b00: Out[0] <= In;
        2'b01: Out[1] <= In;
        2'b10: Out[2] <= In;
        2'b11: Out[3] <= In;
    endcase
end

endmodule
module DeMux (In,Out,Sel);


input In;
output [3:0] Out;
input [1:0] Sel;

always @(In,Sel)
begin
    case (Sel)
        2'b00: Out[0] <= In;
        2'b01: Out[1] <= In;
        2'b10: Out[2] <= In;
        2'b11: Out[3] <= In;
    endcase
end

endmodule