data/full_repos/permissive/117026779/src/PWMCapture.v
1: b"%Error: data/full_repos/permissive/117026779/src/PWMCapture.v:33: syntax error, unexpected int, expecting IDENTIFIER or do or final\n    output reg int,    \n               ^~~\n%Error: data/full_repos/permissive/117026779/src/PWMCapture.v:35: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/117026779/src/PWMCapture.v:54: syntax error, unexpected assign\nassign data       = oe ? out : 32'bz;\n^~~~~~\n%Error: data/full_repos/permissive/117026779/src/PWMCapture.v:68: syntax error, unexpected INTEGER NUMBER, expecting new or new-then-paren\n        int  = 0;\n               ^\n%Error: data/full_repos/permissive/117026779/src/PWMCapture.v:75: syntax error, unexpected INTEGER NUMBER, expecting new or new-then-paren\n        int     = 0;\n                  ^\n%Error: data/full_repos/permissive/117026779/src/PWMCapture.v:98: syntax error, unexpected INTEGER NUMBER, expecting new or new-then-paren\n           int = 1;\n                 ^\n%Error: Exiting due to 6 error(s)\n"
module PWMCapture #(
  parameter BUS_WIDTH = 32
)(
    input wire clk,
    input wire rst,
    input wire oe,
    input wire trigger,
    input wire ext_pwm,
    input wire int_clr,
    output reg int,
    inout wire [BUS_WIDTH-1:0] data
);



parameter LOOKING_FOR_HIGH_LEVEL 	= 0;
parameter IS_HIGH_LEVEL 			= 1;
parameter CAPTURE_AND_HOLD 			= 2;



reg [BUS_WIDTH-1:0] out;
reg [BUS_WIDTH-1:0] counter;
reg [1:0] state;






assign data       = oe ? out : 32'bz;






always @(posedge clk or posedge rst)
begin
    if (rst)
    begin
    	out 	= 0;
        counter = 0;
        state 	= CAPTURE_AND_HOLD;
        int 	= 0;
    end
    else if (trigger)
    begin

        counter = 0;
        state   = LOOKING_FOR_HIGH_LEVEL;
        int     = 0;
    end
    else if (int_clr)
    begin
    	int = 0;
    end
    else
    begin
        case(state)
        	LOOKING_FOR_HIGH_LEVEL:
        	begin
        		if(ext_pwm)
        		begin
        			state = IS_HIGH_LEVEL;
        		end
        	end
        	IS_HIGH_LEVEL:
        	begin
        		counter = counter + 1;
        		if(!ext_pwm)
        		begin
        			state = CAPTURE_AND_HOLD;
        			out = counter;
        			int = 1;
        		end
        	end
        endcase
    end
end
endmodule
module PWMCapture #(
  parameter BUS_WIDTH = 32
)(
    input wire clk,
    input wire rst,
    input wire oe,
    input wire trigger,
    input wire ext_pwm,
    input wire int_clr,
    output reg int,
    inout wire [BUS_WIDTH-1:0] data
);




parameter LOOKING_FOR_HIGH_LEVEL 	= 0;
parameter IS_HIGH_LEVEL 			= 1;
parameter CAPTURE_AND_HOLD 			= 2;



reg [BUS_WIDTH-1:0] out;
reg [BUS_WIDTH-1:0] counter;
reg [1:0] state;






assign data       = oe ? out : 32'bz;






always @(posedge clk or posedge rst)
begin
    if (rst)
    begin
    	out 	= 0;
        counter = 0;
        state 	= CAPTURE_AND_HOLD;
        int 	= 0;
    end
    else if (trigger)
    begin

        counter = 0;
        state   = LOOKING_FOR_HIGH_LEVEL;
        int     = 0;
    end
    else if (int_clr)
    begin
    	int = 0;
    end
    else
    begin
        case(state)
        	LOOKING_FOR_HIGH_LEVEL:
        	begin
        		if(ext_pwm)
        		begin
        			state = IS_HIGH_LEVEL;
        		end
        	end
        	IS_HIGH_LEVEL:
        	begin
        		counter = counter + 1;
        		if(!ext_pwm)
        		begin
        			state = CAPTURE_AND_HOLD;
        			out = counter;
        			int = 1;
        		end
        	end
        endcase
    end
end
endmodule