data/full_repos/permissive/106408053/verilog/sram_interface.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/sram_interface.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/sram_interface.v:189: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/106408053/verilog/sram_interface.v:89: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                : ... In instance sram_interface\n  rdvalid = 1\'b0;\n          ^\n%Error: data/full_repos/permissive/106408053/verilog/sram_interface.v:203: Cannot find file containing module: \'BRAM8k9bit\'\nBRAM8k9bit RAMBG0(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/BRAM8k9bit\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/BRAM8k9bit.v\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/BRAM8k9bit.sv\n             BRAM8k9bit\n             BRAM8k9bit.v\n             BRAM8k9bit.sv\n             obj_dir/BRAM8k9bit\n             obj_dir/BRAM8k9bit.v\n             obj_dir/BRAM8k9bit.sv\n%Error: data/full_repos/permissive/106408053/verilog/sram_interface.v:208: Cannot find file containing module: \'BRAM8k9bit\'\nBRAM8k9bit RAMBG1(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sram_interface.v:213: Cannot find file containing module: \'BRAM8k9bit\'\nBRAM8k9bit RAMBG2(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/106408053/verilog/sram_interface.v:218: Cannot find file containing module: \'BRAM8k9bit\'\nBRAM8k9bit RAMBG3(\n^~~~~~~~~~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sram_interface(
  clk, wrFlags, config_data,
  write, lastwrite, 
  read, wrdata, 

  rddata, rdvalid);

input clk;
input wrFlags;
input [3:0] config_data;
input read, write, lastwrite;
input [`BRAM_MAXDATA:0] wrdata;
output [`BRAM_MAXDATA:0] rddata;
output [3:0] rdvalid;





wire [`BRAM_MAXDATA:0] wrdata;
wire [`BRAM_MAXDATA:0] ram_dataout;





reg init, next_init;
reg [1:0] mode, next_mode;
reg [3:0] validmask, next_validmask;

reg [3:0] clkenb, next_clkenb;
reg [`BRAM_MAXINDEX:0] address, next_address;
reg [3:0] rdvalid, next_rdvalid;


wire maxaddr = &address[`BRAM_MAXINDEX:0];
wire addrzero = ~|address;





initial 
begin
  init = 1'b0;
  mode = 2'b00;
  validmask = 4'hF;
  clkenb = 4'b1111;
  address = 0;
  rdvalid = 1'b0;
end
always @ (posedge clk)
begin
  init = next_init;
  mode = next_mode;
  validmask = next_validmask;
  clkenb = next_clkenb;
  address = next_address;
  rdvalid = next_rdvalid;
end


always @*
begin
  #1;
  next_init = 1'b0;
  next_mode = mode;
  next_validmask = validmask;

  next_clkenb = clkenb;
  next_address = address;
  next_rdvalid = clkenb & validmask;







  if (wrFlags)
    begin
      next_init = 1'b1;
      next_mode = 0;
      case (config_data)
        4'b1100, 4'b0011, 4'b0110, 4'b1001, 4'b1010, 4'b0101 : next_mode = 2'b10;
        4'b1110, 4'b1101, 4'b1011, 4'b0111 : next_mode = 2'b01;
      endcase





      next_validmask = 4'hF;
      case (config_data)
        4'b0001, 4'b0010, 4'b0100, 4'b1000 : next_validmask = 4'h7;
      endcase
    end









  casex ({write && !lastwrite, read})
    2'b1x :
      begin
        next_clkenb = 4'b1111;
        casex (mode[1:0])
          2'bx1 : next_clkenb = {clkenb[2:0],clkenb[3]};
          2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]};
        endcase
        if (clkenb[3]) next_address = (maxaddr) ? 0 : address+1'b1;
      end

    2'bx1 : 
      begin
        next_clkenb = 4'b1111;
        casex (mode[1:0])
          2'bx1 : next_clkenb = {clkenb[0],clkenb[3:1]};
          2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]};
        endcase
        if (clkenb[0]) next_address = (addrzero) ? `BRAM_MAX_ADDRESS : address-1'b1;
      end
  endcase




  if (init) 
    begin
      next_clkenb = 4'b1111; 
      casex (mode[1:0])
        2'bx1 : next_clkenb = 4'b0001;
        2'b1x : next_clkenb = 4'b0011;
      endcase
      next_address = 0;
    end
end





reg [`BRAM_MAXDATA:0] ram_datain;
always @*
begin
  #1;
  ram_datain = wrdata;
  casex (mode[1:0])
    2'bx1 : ram_datain[31:0] = {wrdata[7:0],wrdata[7:0],wrdata[7:0],wrdata[7:0]};
    2'b1x : ram_datain[31:0] = {wrdata[15:0],wrdata[15:0]};
  endcase
end





wire [`BRAM_MAXINDEX:0] #1 ram_ADDR = address;
wire #1 ram_WE = write;
BRAM8k9bit RAMBG0(
  .CLK(clk), .WE(ram_WE), .EN(clkenb[0]), .ADDR(ram_ADDR),
  .DIN(ram_datain[7:0]), .DOUT(ram_dataout[7:0]),
  .DINP(ram_datain[32]), .DOUTP(ram_dataout[32]));

BRAM8k9bit RAMBG1(
  .CLK(clk), .WE(ram_WE), .EN(clkenb[1]), .ADDR(ram_ADDR),
  .DIN(ram_datain[15:8]), .DOUT(ram_dataout[15:8]),
  .DINP(ram_datain[33]), .DOUTP(ram_dataout[33]));

BRAM8k9bit RAMBG2(
  .CLK(clk), .WE(ram_WE), .EN(clkenb[2]), .ADDR(ram_ADDR),
  .DIN(ram_datain[23:16]), .DOUT(ram_dataout[23:16]),
  .DINP(ram_datain[34]), .DOUTP(ram_dataout[34]));

BRAM8k9bit RAMBG3(
  .CLK(clk), .WE(ram_WE), .EN(clkenb[3]), .ADDR(ram_ADDR),
  .DIN(ram_datain[31:24]), .DOUT(ram_dataout[31:24]),
  .DINP(ram_datain[35]), .DOUTP(ram_dataout[35]));

assign rddata = ram_dataout;

endmodule
module sram_interface(
  clk, wrFlags, config_data,
  write, lastwrite, 
  read, wrdata, 

  rddata, rdvalid);


input clk;
input wrFlags;
input [3:0] config_data;
input read, write, lastwrite;
input [`BRAM_MAXDATA:0] wrdata;
output [`BRAM_MAXDATA:0] rddata;
output [3:0] rdvalid;





wire [`BRAM_MAXDATA:0] wrdata;
wire [`BRAM_MAXDATA:0] ram_dataout;





reg init, next_init;
reg [1:0] mode, next_mode;
reg [3:0] validmask, next_validmask;

reg [3:0] clkenb, next_clkenb;
reg [`BRAM_MAXINDEX:0] address, next_address;
reg [3:0] rdvalid, next_rdvalid;


wire maxaddr = &address[`BRAM_MAXINDEX:0];
wire addrzero = ~|address;





initial 
begin
  init = 1'b0;
  mode = 2'b00;
  validmask = 4'hF;
  clkenb = 4'b1111;
  address = 0;
  rdvalid = 1'b0;
end
always @ (posedge clk)
begin
  init = next_init;
  mode = next_mode;
  validmask = next_validmask;
  clkenb = next_clkenb;
  address = next_address;
  rdvalid = next_rdvalid;
end


always @*
begin
  #1;
  next_init = 1'b0;
  next_mode = mode;
  next_validmask = validmask;

  next_clkenb = clkenb;
  next_address = address;
  next_rdvalid = clkenb & validmask;







  if (wrFlags)
    begin
      next_init = 1'b1;
      next_mode = 0;
      case (config_data)
        4'b1100, 4'b0011, 4'b0110, 4'b1001, 4'b1010, 4'b0101 : next_mode = 2'b10;
        4'b1110, 4'b1101, 4'b1011, 4'b0111 : next_mode = 2'b01;
      endcase





      next_validmask = 4'hF;
      case (config_data)
        4'b0001, 4'b0010, 4'b0100, 4'b1000 : next_validmask = 4'h7;
      endcase
    end









  casex ({write && !lastwrite, read})
    2'b1x :
      begin
        next_clkenb = 4'b1111;
        casex (mode[1:0])
          2'bx1 : next_clkenb = {clkenb[2:0],clkenb[3]};
          2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]};
        endcase
        if (clkenb[3]) next_address = (maxaddr) ? 0 : address+1'b1;
      end

    2'bx1 : 
      begin
        next_clkenb = 4'b1111;
        casex (mode[1:0])
          2'bx1 : next_clkenb = {clkenb[0],clkenb[3:1]};
          2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]};
        endcase
        if (clkenb[0]) next_address = (addrzero) ? `BRAM_MAX_ADDRESS : address-1'b1;
      end
  endcase




  if (init) 
    begin
      next_clkenb = 4'b1111; 
      casex (mode[1:0])
        2'bx1 : next_clkenb = 4'b0001;
        2'b1x : next_clkenb = 4'b0011;
      endcase
      next_address = 0;
    end
end





reg [`BRAM_MAXDATA:0] ram_datain;
always @*
begin
  #1;
  ram_datain = wrdata;
  casex (mode[1:0])
    2'bx1 : ram_datain[31:0] = {wrdata[7:0],wrdata[7:0],wrdata[7:0],wrdata[7:0]};
    2'b1x : ram_datain[31:0] = {wrdata[15:0],wrdata[15:0]};
  endcase
end





wire [`BRAM_MAXINDEX:0] #1 ram_ADDR = address;
wire #1 ram_WE = write;
BRAM8k9bit RAMBG0(
  .CLK(clk), .WE(ram_WE), .EN(clkenb[0]), .ADDR(ram_ADDR),
  .DIN(ram_datain[7:0]), .DOUT(ram_dataout[7:0]),
  .DINP(ram_datain[32]), .DOUTP(ram_dataout[32]));

BRAM8k9bit RAMBG1(
  .CLK(clk), .WE(ram_WE), .EN(clkenb[1]), .ADDR(ram_ADDR),
  .DIN(ram_datain[15:8]), .DOUT(ram_dataout[15:8]),
  .DINP(ram_datain[33]), .DOUTP(ram_dataout[33]));

BRAM8k9bit RAMBG2(
  .CLK(clk), .WE(ram_WE), .EN(clkenb[2]), .ADDR(ram_ADDR),
  .DIN(ram_datain[23:16]), .DOUT(ram_dataout[23:16]),
  .DINP(ram_datain[34]), .DOUTP(ram_dataout[34]));

BRAM8k9bit RAMBG3(
  .CLK(clk), .WE(ram_WE), .EN(clkenb[3]), .ADDR(ram_ADDR),
  .DIN(ram_datain[31:24]), .DOUT(ram_dataout[31:24]),
  .DINP(ram_datain[35]), .DOUTP(ram_dataout[35]));

assign rddata = ram_dataout;

endmodule