data/full_repos/permissive/133653839/i2c_fifo_TB.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #5 clk = !clk;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #10 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #20 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #10 addr_data =0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10 wr_en = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #100 wr_en = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #50 rd_en = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #100 rd_en = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/133653839/i2c_fifo_TB.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #500 $finish;\n  ^\n%Error: data/full_repos/permissive/133653839/i2c_fifo_TB.v:12: Cannot find file containing module: \'i2c_fifo\'\n i2c_fifo uut_1 (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133653839,data/full_repos/permissive/133653839/i2c_fifo\n             data/full_repos/permissive/133653839,data/full_repos/permissive/133653839/i2c_fifo.v\n             data/full_repos/permissive/133653839,data/full_repos/permissive/133653839/i2c_fifo.sv\n             i2c_fifo\n             i2c_fifo.v\n             i2c_fifo.sv\n             obj_dir/i2c_fifo\n             obj_dir/i2c_fifo.v\n             obj_dir/i2c_fifo.sv\n%Error: Exiting due to 1 error(s), 23 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module i2c_fifo_TB;

		reg	    clk,rst,wr_en,rd_en;
		reg 	addr_data;
	    wire	data_out;
		wire	empty,full;
	
	i2c_fifo uut_1 (
		.clk(clk), 
		.rst(rst),  
		.wr_en(wr_en),
		.rd_en(rd_en),
		.addr_data(addr_data),
		.data_out(data_out)
	);

	
	initial begin

		clk = 0;
		rst = 0;
		forever begin
			#5 clk = !clk;
		end
	end

	initial
		begin
		#10 rst = 1;
		#20 rst = 0;
			
		#10 addr_data =0;
		#10 addr_data =0;
		#10 addr_data =0;
		#10 addr_data =1;
		#10 addr_data =1;
		#10 addr_data =0;
		#10 addr_data =0;
		#10 addr_data =0;
		#10 addr_data =0;
		#10 addr_data =1;
		#10 addr_data =0;
		#10 addr_data =1;
		#10 addr_data =0;
		#10 addr_data =1;
		#10 addr_data =0;
		#10 wr_en = 1;
		#100 wr_en = 0;
		
		#50 rd_en = 1;
		#100 rd_en = 0;
		
		#500 $finish;


	end
      
endmodule
module i2c_fifo_TB;


		reg	    clk,rst,wr_en,rd_en;
		reg 	addr_data;
	    wire	data_out;
		wire	empty,full;
	
	i2c_fifo uut_1 (
		.clk(clk), 
		.rst(rst),  
		.wr_en(wr_en),
		.rd_en(rd_en),
		.addr_data(addr_data),
		.data_out(data_out)
	);

	
	initial begin

		clk = 0;
		rst = 0;
		forever begin
			#5 clk = !clk;
		end
	end

	initial
		begin
		#10 rst = 1;
		#20 rst = 0;
			
		#10 addr_data =0;
		#10 addr_data =0;
		#10 addr_data =0;
		#10 addr_data =1;
		#10 addr_data =1;
		#10 addr_data =0;
		#10 addr_data =0;
		#10 addr_data =0;
		#10 addr_data =0;
		#10 addr_data =1;
		#10 addr_data =0;
		#10 addr_data =1;
		#10 addr_data =0;
		#10 addr_data =1;
		#10 addr_data =0;
		#10 wr_en = 1;
		#100 wr_en = 0;
		
		#50 rd_en = 1;
		#100 rd_en = 0;
		
		#500 $finish;


	end
      
endmodule