data/full_repos/permissive/19384863/sixbitexp.v
1: b'%Error: data/full_repos/permissive/19384863/sixbitexp.v:4: Cannot find include file: sixbitadd.v\n`include "sixbitadd.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19384863,data/full_repos/permissive/19384863/sixbitadd.v\n             data/full_repos/permissive/19384863,data/full_repos/permissive/19384863/sixbitadd.v.v\n             data/full_repos/permissive/19384863,data/full_repos/permissive/19384863/sixbitadd.v.sv\n             sixbitadd.v\n             sixbitadd.v.v\n             sixbitadd.v.sv\n             obj_dir/sixbitadd.v\n             obj_dir/sixbitadd.v.v\n             obj_dir/sixbitadd.v.sv\n%Error: data/full_repos/permissive/19384863/sixbitexp.v:5: Cannot find include file: sixbitpow.v\n`include "sixbitpow.v" \n         ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module sixbitexp(ain, out, overflow);
    input[5:0] ain;
    output[5:0] out;
    output overflow;
    

    
    wire[5:0] sum;
    wire[3:0] ovf;
    wire[5:0] pow;
    wire[5:0] divisor;
    wire[5:0] remainder;
    
    sixbitadd add1 (1, ain, sum, ovf[0]);
    sixbitpow pow1 (ain, 2, pow, ovf[1]);
    sixbitdiv div1 (pow, 2, divisor, remainder, ovf[2]);
    sixbitadd add2 (sum, (ovf[1] || ovf[2]) ? 0 : divisor, out, ovf[3]);
    
    assign overflow = |ovf;
endmodule
module sixbitexp(ain, out, overflow);

    input[5:0] ain;
    output[5:0] out;
    output overflow;
    

    
    wire[5:0] sum;
    wire[3:0] ovf;
    wire[5:0] pow;
    wire[5:0] divisor;
    wire[5:0] remainder;
    
    sixbitadd add1 (1, ain, sum, ovf[0]);
    sixbitpow pow1 (ain, 2, pow, ovf[1]);
    sixbitdiv div1 (pow, 2, divisor, remainder, ovf[2]);
    sixbitadd add2 (sum, (ovf[1] || ovf[2]) ? 0 : divisor, out, ovf[3]);
    
    assign overflow = |ovf;
endmodule