data/full_repos/permissive/19572582/Lab2/lab2_part5.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part5.v:140: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] SSD;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part5.v:101: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] SSD;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part5.v:21: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;\n         ^\n%Error: Exiting due to 3 warning(s)\n'
module circuitB (z, SSD);
  input z;
  output [0:6] SSD;

  assign SSD[0] = z;
  assign SSD[1:2] = 2'b00;
  assign SSD[3:5] = {3{z}};
  assign SSD[6] = 1;
endmodule
module circuitB (z, SSD);

  input z;
  output [0:6] SSD;

  assign SSD[0] = z;
  assign SSD[1:2] = 2'b00;
  assign SSD[3:5] = {3{z}};
  assign SSD[6] = 1;
endmodule