data/full_repos/permissive/125927162/HC1645/piso_tb.v
 line:45: before: "$"
1: b'%Error: data/full_repos/permissive/125927162/HC1645/piso_tb.v:34: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("piso.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/HC1645/piso_tb.v:35: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, piso_tb);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/HC1645/piso_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/HC1645/piso_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/HC1645/piso_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #1000\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/HC1645/piso_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module piso_tb ();
   localparam WIDTH = 16;
   reg clk;
   reg shld;
   reg ser;
   reg [WIDTH-1:0] parin;
   wire 		   q_n;
   wire 		   q;

   piso #(.WIDTH(WIDTH)) DUT (
			  .clk(clk),
			  .shld(shld),
			  .ser(q),
			  .parin(parin),
			  .q(q),
			  .q_n(q_n)
			  );
   initial begin
      $dumpfile("piso.vcd");
      $dumpvars(0, piso_tb);
      clk = 0;
      shld = 1;
      ser = 0;
      parin = 16'h15AF;
      #1
	shld = 0;
      #5
	shld = 1;
      #1000
	$finish;
   end

   always #5 clk = ~clk;
   
endmodule
module piso_tb ();

   localparam WIDTH = 16;
   reg clk;
   reg shld;
   reg ser;
   reg [WIDTH-1:0] parin;
   wire 		   q_n;
   wire 		   q;

   piso #(.WIDTH(WIDTH)) DUT (
			  .clk(clk),
			  .shld(shld),
			  .ser(q),
			  .parin(parin),
			  .q(q),
			  .q_n(q_n)
			  );
   initial begin
      $dumpfile("piso.vcd");
      $dumpvars(0, piso_tb);
      clk = 0;
      shld = 1;
      ser = 0;
      parin = 16'h15AF;
      #1
	shld = 0;
      #5
	shld = 1;
      #1000
	$finish;
   end

   always #5 clk = ~clk;
   
endmodule