data/full_repos/permissive/20203077/robsparts.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/20203077/robsparts.v:19: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'register\'\nmodule register # (parameter N = 8)\n       ^~~~~~~~\n                                                                     : ... Top module \'register_hl\'\nmodule register_hl # (parameter N = 16)\n       ^~~~~~~~~~~\n                                                                     : ... Top module \'upcreg\'\nmodule upcreg(\n       ^~~~~~\n                                                                     : ... Top module \'mux5\'\nmodule mux5 (input      d0, d1, d2, d3, d4,\n       ^~~~\n                                                                     : ... Top module \'addsub\'\nmodule addsub\n       ^~~~~~\n                                                                     : ... Top module \'counter_down\'\nmodule counter_down\n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module register_hl # (parameter N = 16)
	(input clk,
	 input [N/2-1:0] inh,
	 input [N/2-1:0] inl,
	 input loadh,
	 input loadl,
	 input clear,
	 output reg [N-1:0] out
	);
	
	 always @ (posedge clk or posedge clear)
		if (clear)			out <= 0;
		else begin 
			if (loadh)	out[N-1:N/2] <= inh;
			if (loadl)	out[N/2-1:0] <= inl;
		end
	
endmodule
module register_hl # (parameter N = 16)
	(input clk,
	 input [N/2-1:0] inh,
	 input [N/2-1:0] inl,
	 input loadh,
	 input loadl,
	 input clear,
	 output reg [N-1:0] out
	);

	
	 always @ (posedge clk or posedge clear)
		if (clear)			out <= 0;
		else begin 
			if (loadh)	out[N-1:N/2] <= inh;
			if (loadl)	out[N/2-1:0] <= inl;
		end
	
endmodule