data/full_repos/permissive/123627914/src/main/modules/input-unit/inputUnit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/123627914/src/main/modules/input-unit/inputUnit.v:18: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 10 bits.\n                                                                                               : ... In instance inputUnit\nassign ODATA = (!KEYS[KEYS_WIDTH-1] || !KEYS[KEYS_WIDTH-2:0]) ? {1\'b0,{{DIFF_WIDTH{1\'b0}},KEYS[KEYS_WIDTH-2:0]}}\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module inputUnit(
KEYS    ,
ODATA
);

parameter KEYS_WIDTH = 11;
parameter DATA_WIDTH = 32;
parameter DIFF_WIDTH = DATA_WIDTH - KEYS_WIDTH;


input   [KEYS_WIDTH-1:0]    KEYS;


output wire  [DATA_WIDTH-1:0]   ODATA;



assign ODATA = (!KEYS[KEYS_WIDTH-1] || !KEYS[KEYS_WIDTH-2:0]) ? {1'b0,{{DIFF_WIDTH{1'b0}},KEYS[KEYS_WIDTH-2:0]}}
                                                    : {{DIFF_WIDTH{1'b1}},((~{1'b0,KEYS[KEYS_WIDTH-2:0]})+1'b1)};

endmodule
module inputUnit(
KEYS    ,
ODATA
);


parameter KEYS_WIDTH = 11;
parameter DATA_WIDTH = 32;
parameter DIFF_WIDTH = DATA_WIDTH - KEYS_WIDTH;


input   [KEYS_WIDTH-1:0]    KEYS;


output wire  [DATA_WIDTH-1:0]   ODATA;



assign ODATA = (!KEYS[KEYS_WIDTH-1] || !KEYS[KEYS_WIDTH-2:0]) ? {1'b0,{{DIFF_WIDTH{1'b0}},KEYS[KEYS_WIDTH-2:0]}}
                                                    : {{DIFF_WIDTH{1'b1}},((~{1'b0,KEYS[KEYS_WIDTH-2:0]})+1'b1)};

endmodule