data/full_repos/permissive/156609923/Arbitraje/probador.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/156609923/Arbitraje/probador.v:32: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/156609923/Arbitraje/probador.v:36: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");  \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/156609923/Arbitraje/probador.v:37: Unsupported or unknown PLI call: $dumpvars\n       $dumpvars(0,testbench);   \n       ^~~~~~~~~\n%Error: data/full_repos/permissive/156609923/Arbitraje/probador.v:52: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/156609923/Arbitraje/probador.v:55: syntax error, unexpected \'@\'\n    #4 @(posedge clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/Arbitraje/probador.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #4 @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/156609923/Arbitraje/probador.v:58: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/Arbitraje/probador.v:61: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/Arbitraje/probador.v:66: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/Arbitraje/probador.v:70: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/Arbitraje/probador.v:74: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/Arbitraje/probador.v:81: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/Arbitraje/probador.v:85: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/Arbitraje/probador.v:89: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/Arbitraje/probador.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #20 $finish;\n    ^\n%Error: Exiting due to 12 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador (	input popVC0_0_condu,
									input popVC1_0_condu,
									input popVC0_1_condu,
									input popVC1_1_condu,
									input [4:0] dataOut0_condu,
									input [4:0] dataOut1_condu,
									input [1:0] validBitsOut_condu,
									input popVC0_0_estru,
									input popVC1_0_estru,
									input popVC0_1_estru,
									input popVC1_1_estru,
									input [4:0] dataOut0_estru,
									input [4:0] dataOut1_estru,
									input [1:0] validBitsOut_estru,
									output reg clk,
									output reg reset_L,
									output reg [4:0] VC0_p0,
									output reg [4:0] VC1_p0,
									output reg [4:0] VC0_p1,
									output reg [4:0] VC1_p1,
									output reg [3:0] validBits,
                  output reg emptyVC0_p0,
                  output reg emptyVC1_p0,
                  output reg emptyVC0_p1,
                  output reg emptyVC1_p1);




	initial clk <= 0;
	always #1 clk = ~clk;

	initial
	begin
		$dumpfile("test.vcd");
     		$dumpvars(0,testbench);


	   reset_L <= 0;
		 VC0_p0 <= 5'b00001;
		 VC1_p0 <= 5'b00010;
		 VC0_p1 <= 5'b00011;
		 VC1_p1 <= 5'b00100;
		 validBits <=4'b1111;
		 emptyVC0_p0 <= 1;
		 emptyVC1_p0 <= 1;
		 emptyVC0_p1 <= 1;
		 emptyVC1_p1 <= 1;


	   @(posedge clk);
	   reset_L <= 1;

	   #4 @(posedge clk);
		 emptyVC0_p0 <= 0;

		 @(posedge clk);
		 VC0_p0 <= 5'b10010;

		 @(posedge clk);
		 VC0_p0 <= 5'b11111;
		 VC0_p1 <= 5'b00010;
		 emptyVC0_p1 <= 0;

		 @(posedge clk);
		 VC0_p1 <= 5'b11000;
		 VC0_p0 <= 5'b01011;

		 @(posedge clk);
		 VC0_p1 <= 5'b11001;
		 VC0_p0 <= 5'b01011;

		 @(posedge clk);
		 emptyVC0_p0 <= 1;
		 emptyVC0_p1 <= 1;
		 validBits <=4'b1100;
		 emptyVC1_p0 <= 0;
		 emptyVC1_p1 <= 0;

		 @(posedge clk);
		 VC1_p1 <= 5'b11001;
		 VC1_p0 <= 5'b01011;

		 @(posedge clk);
		 VC1_p1 <= 5'b01101;
		 VC1_p0 <= 5'b11001;

		 @(posedge clk);
		 VC1_p1 <= 5'b11111;
		 VC1_p0 <= 5'b01101;


	   #20 $finish;

	end

endmodule
module probador (	input popVC0_0_condu,
									input popVC1_0_condu,
									input popVC0_1_condu,
									input popVC1_1_condu,
									input [4:0] dataOut0_condu,
									input [4:0] dataOut1_condu,
									input [1:0] validBitsOut_condu,
									input popVC0_0_estru,
									input popVC1_0_estru,
									input popVC0_1_estru,
									input popVC1_1_estru,
									input [4:0] dataOut0_estru,
									input [4:0] dataOut1_estru,
									input [1:0] validBitsOut_estru,
									output reg clk,
									output reg reset_L,
									output reg [4:0] VC0_p0,
									output reg [4:0] VC1_p0,
									output reg [4:0] VC0_p1,
									output reg [4:0] VC1_p1,
									output reg [3:0] validBits,
                  output reg emptyVC0_p0,
                  output reg emptyVC1_p0,
                  output reg emptyVC0_p1,
                  output reg emptyVC1_p1);





	initial clk <= 0;
	always #1 clk = ~clk;

	initial
	begin
		$dumpfile("test.vcd");
     		$dumpvars(0,testbench);


	   reset_L <= 0;
		 VC0_p0 <= 5'b00001;
		 VC1_p0 <= 5'b00010;
		 VC0_p1 <= 5'b00011;
		 VC1_p1 <= 5'b00100;
		 validBits <=4'b1111;
		 emptyVC0_p0 <= 1;
		 emptyVC1_p0 <= 1;
		 emptyVC0_p1 <= 1;
		 emptyVC1_p1 <= 1;


	   @(posedge clk);
	   reset_L <= 1;

	   #4 @(posedge clk);
		 emptyVC0_p0 <= 0;

		 @(posedge clk);
		 VC0_p0 <= 5'b10010;

		 @(posedge clk);
		 VC0_p0 <= 5'b11111;
		 VC0_p1 <= 5'b00010;
		 emptyVC0_p1 <= 0;

		 @(posedge clk);
		 VC0_p1 <= 5'b11000;
		 VC0_p0 <= 5'b01011;

		 @(posedge clk);
		 VC0_p1 <= 5'b11001;
		 VC0_p0 <= 5'b01011;

		 @(posedge clk);
		 emptyVC0_p0 <= 1;
		 emptyVC0_p1 <= 1;
		 validBits <=4'b1100;
		 emptyVC1_p0 <= 0;
		 emptyVC1_p1 <= 0;

		 @(posedge clk);
		 VC1_p1 <= 5'b11001;
		 VC1_p0 <= 5'b01011;

		 @(posedge clk);
		 VC1_p1 <= 5'b01101;
		 VC1_p0 <= 5'b11001;

		 @(posedge clk);
		 VC1_p1 <= 5'b11111;
		 VC1_p0 <= 5'b01101;


	   #20 $finish;

	end

endmodule