data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v
 line:18: before: "reg"
1: b'%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #5 C = !C;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #4 CLR = CLEAR_VAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #4 CLR = ~CLEAR_VAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #36 CLR = CLEAR_VAL;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #4  CLR = ~CLEAR_VAL;\n        ^\n%Error: data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation/counter_testbench.v:25: Cannot find file containing module: \'counter\'\n    counter #(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation,data/full_repos/permissive/110143902/counter\n             data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation,data/full_repos/permissive/110143902/counter.v\n             data/full_repos/permissive/110143902/projects/counter_async_reset_n_clear_input/src/simulation,data/full_repos/permissive/110143902/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_testbench (  );

    parameter                          DATA_WIDTH   = 4;
    parameter reg [DATA_WIDTH - 1 : 0] CLEAR_DATA   = 0;
    parameter                          CLEAR_VAL    = 1;

    reg C, CLR;
    wire [DATA_WIDTH - 1 : 0] Q, notQ;
    wire overflow;

    counter #(
        .DATA_WIDTH(DATA_WIDTH),
        .CLEAR_VAL(CLEAR_VAL)
    ) counter_i (
        .DCLR(CLEAR_DATA),
        .C(C),
        .CLR(CLR),
        .Q(Q),
        .notQ(notQ),
        .overflow(overflow)
    );


    always
        #5 C = !C;


    initial begin
        C = 0;
        CLR = ~CLEAR_VAL;

        #4 CLR = CLEAR_VAL;
        #4 CLR = ~CLEAR_VAL;

        #36 CLR = CLEAR_VAL;
        #4  CLR = ~CLEAR_VAL;
    end

endmodule
module counter_testbench (  );


    parameter                          DATA_WIDTH   = 4;
    parameter reg [DATA_WIDTH - 1 : 0] CLEAR_DATA   = 0;
    parameter                          CLEAR_VAL    = 1;

    reg C, CLR;
    wire [DATA_WIDTH - 1 : 0] Q, notQ;
    wire overflow;

    counter #(
        .DATA_WIDTH(DATA_WIDTH),
        .CLEAR_VAL(CLEAR_VAL)
    ) counter_i (
        .DCLR(CLEAR_DATA),
        .C(C),
        .CLR(CLR),
        .Q(Q),
        .notQ(notQ),
        .overflow(overflow)
    );


    always
        #5 C = !C;


    initial begin
        C = 0;
        CLR = ~CLEAR_VAL;

        #4 CLR = CLEAR_VAL;
        #4 CLR = ~CLEAR_VAL;

        #36 CLR = CLEAR_VAL;
        #4  CLR = ~CLEAR_VAL;
    end

endmodule