data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v
 line:49: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v:6: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #0.1 csCount <= csCount + 1;\n    ^\n%Error: data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v:44: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("out.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v:45: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v:47: syntax error, unexpected \'@\'\n    @(posedge readedStrobe);\n    ^\n%Error: data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v:49: syntax error, unexpected \'@\'\n    @(posedge readedStrobe);  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1.1  \n        ^\n%Error: data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v:51: syntax error, unexpected \'@\'\n    @(negedge readedStrobe);\n    ^\n%Error: data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v:54: syntax error, unexpected \'@\'\n    @(posedge readedStrobe);  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #1.1\n        ^\n%Error: data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v:56: syntax error, unexpected \'@\'\n    @(negedge readedStrobe);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/160073872/fpga/tb/tb_mic_reader.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #1.1\n        ^\n%Error: Exiting due to 7 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mic_reader();

reg clk = 1;

always #1 clk = ~clk;

reg miso = 1'bX;
wire nCs;
wire[15:0] readedData;
wire readedStrobe;



`define assert(signal, value) \
        if (signal !== value) $display("ASSERTION FAILED in %m: signal != value"); \
        else $display("ASSERTION SUCCEEDED in %m: signal = value"); \

mic_reader readerInstance(
    .clk(clk),
    .nCs(nCs),
    .miso(miso),
    .outData(readedData),
    .outStrobe(readedStrobe)
);

integer csCount = 0;
always @(negedge nCs)
    #0.1 csCount <= csCount + 1;

reg [15:0] txData;

always @(negedge clk) begin
    miso <= txData[14];
    if (nCs) begin
        if (csCount==1) txData <= 16'hFABB;
        if (csCount==2) txData <= 16'hC792;
    end else begin
        txData <= (txData << 1);
    end
end

initial begin
    $dumpfile("out.vcd");
    $dumpvars;

    @(posedge readedStrobe);
        #1.1  
    @(posedge readedStrobe);  
        `assert(readedStrobe, 1'b1);
    @(negedge readedStrobe);
        `assert(readedData, 16'h7ABB);
        #1.1
    @(posedge readedStrobe);  
        `assert(readedStrobe, 1'b1);
    @(negedge readedStrobe);
        `assert(readedData, 16'h4792);
        #1.1


    

    $finish;
end

endmodule
module tb_mic_reader();


reg clk = 1;

always #1 clk = ~clk;

reg miso = 1'bX;
wire nCs;
wire[15:0] readedData;
wire readedStrobe;



`define assert(signal, value) \
        if (signal !== value) $display("ASSERTION FAILED in %m: signal != value"); \
        else $display("ASSERTION SUCCEEDED in %m: signal = value"); \

mic_reader readerInstance(
    .clk(clk),
    .nCs(nCs),
    .miso(miso),
    .outData(readedData),
    .outStrobe(readedStrobe)
);

integer csCount = 0;
always @(negedge nCs)
    #0.1 csCount <= csCount + 1;

reg [15:0] txData;

always @(negedge clk) begin
    miso <= txData[14];
    if (nCs) begin
        if (csCount==1) txData <= 16'hFABB;
        if (csCount==2) txData <= 16'hC792;
    end else begin
        txData <= (txData << 1);
    end
end

initial begin
    $dumpfile("out.vcd");
    $dumpvars;

    @(posedge readedStrobe);
        #1.1  
    @(posedge readedStrobe);  
        `assert(readedStrobe, 1'b1);
    @(negedge readedStrobe);
        `assert(readedData, 16'h7ABB);
        #1.1
    @(posedge readedStrobe);  
        `assert(readedStrobe, 1'b1);
    @(negedge readedStrobe);
        `assert(readedData, 16'h4792);
        #1.1


    

    $finish;
end

endmodule