data/full_repos/permissive/152249767/src/mem_simple/picosoc.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/152249767/src/mem_simple/picosoc.v:54: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/152249767/src/mem_simple/picosoc.v:55: Unsupported: Ignoring delay on this delayed statement.\n always #30 resetn=1;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/152249767/src/mem_simple/picosoc.v:107: Bit extraction of array[1023:0] requires 10 bit index, not 22 bits.\n                                                                                 : ... In instance picosoc.internal_sram\n  rdata <= mem[addr];\n              ^\n%Warning-WIDTH: data/full_repos/permissive/152249767/src/mem_simple/picosoc.v:108: Bit extraction of array[1023:0] requires 10 bit index, not 22 bits.\n                                                                                 : ... In instance picosoc.internal_sram\n  if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/152249767/src/mem_simple/picosoc.v:109: Bit extraction of array[1023:0] requires 10 bit index, not 22 bits.\n                                                                                 : ... In instance picosoc.internal_sram\n  if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/152249767/src/mem_simple/picosoc.v:110: Bit extraction of array[1023:0] requires 10 bit index, not 22 bits.\n                                                                                 : ... In instance picosoc.internal_sram\n  if (wen[2]) mem[addr][23:16] <= wdata[23:16];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/152249767/src/mem_simple/picosoc.v:111: Bit extraction of array[1023:0] requires 10 bit index, not 22 bits.\n                                                                                 : ... In instance picosoc.internal_sram\n  if (wen[3]) mem[addr][31:24] <= wdata[31:24];\n                 ^\n%Error: data/full_repos/permissive/152249767/src/mem_simple/picosoc.v:62: Cannot find file containing module: \'picorv32\'\n picorv32 #(\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/152249767/src/mem_simple,data/full_repos/permissive/152249767/picorv32\n             data/full_repos/permissive/152249767/src/mem_simple,data/full_repos/permissive/152249767/picorv32.v\n             data/full_repos/permissive/152249767/src/mem_simple,data/full_repos/permissive/152249767/picorv32.sv\n             picorv32\n             picorv32.v\n             picorv32.sv\n             obj_dir/picorv32\n             obj_dir/picorv32.v\n             obj_dir/picorv32.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module picosoc ();


	parameter integer MEM_WORDS = 1024;
	parameter [31:0] STACKADDR = (4*MEM_WORDS);
	parameter [31:0] PROGADDR_RESET = 32'h00000000;

    reg clk;
    reg resetn;
	reg sram_ready;
	

	wire mem_valid;
	wire mem_instr;
	wire mem_ready;
	wire [31:0] mem_addr;
	wire [31:0] mem_wdata;
	wire [3:0]  mem_wstrb;
	wire [31:0] mem_rdata;
	
	wire [31:0] sram_rdata;

	assign mem_rdata = sram_rdata;
	assign mem_ready = sram_ready;
	
	integer i;
	initial begin
		clk = 0;
        resetn = 0;
		$readmemh("/home/zhangshuai/develop/soft_core/vivado_project/test_picorv32/new_asm_main.data",internal_sram.mem,0);
		
		for(i=0;i<13;i=i+1)
			$display("internal_sram.mem[%d] = %h",i,internal_sram.mem[i]);
	end
	
	always #5 clk=~clk;
	always #30 resetn=1;
	
	always @(posedge clk)
		sram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
		
    

	picorv32 #(
		.STACKADDR(STACKADDR),
		.PROGADDR_RESET(PROGADDR_RESET),
		.BARREL_SHIFTER(1),
		.ENABLE_IRQ(1),
		.ENABLE_IRQ_QREGS(0)
		) 
		cpu (
			.clk         (clk        ),
			.resetn      (resetn     ),
			.mem_valid   (mem_valid  ),
			.mem_instr   (mem_instr  ),
			.mem_ready   (mem_ready  ),
			.mem_addr    (mem_addr   ),
			.mem_wdata   (mem_wdata  ),
			.mem_wstrb   (mem_wstrb  ),
			.mem_rdata   (mem_rdata  )
		);
		

	picosoc_mem #(.WORDS(MEM_WORDS)) internal_sram (
		.clk(clk),
		.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
		.addr(mem_addr[23:2]),
		.wdata(mem_wdata),
		.rdata(sram_rdata)
	);
endmodule
module picosoc ();



	parameter integer MEM_WORDS = 1024;
	parameter [31:0] STACKADDR = (4*MEM_WORDS);
	parameter [31:0] PROGADDR_RESET = 32'h00000000;

    reg clk;
    reg resetn;
	reg sram_ready;
	

	wire mem_valid;
	wire mem_instr;
	wire mem_ready;
	wire [31:0] mem_addr;
	wire [31:0] mem_wdata;
	wire [3:0]  mem_wstrb;
	wire [31:0] mem_rdata;
	
	wire [31:0] sram_rdata;

	assign mem_rdata = sram_rdata;
	assign mem_ready = sram_ready;
	
	integer i;
	initial begin
		clk = 0;
        resetn = 0;
		$readmemh("/home/zhangshuai/develop/soft_core/vivado_project/test_picorv32/new_asm_main.data",internal_sram.mem,0);
		
		for(i=0;i<13;i=i+1)
			$display("internal_sram.mem[%d] = %h",i,internal_sram.mem[i]);
	end
	
	always #5 clk=~clk;
	always #30 resetn=1;
	
	always @(posedge clk)
		sram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
		
    

	picorv32 #(
		.STACKADDR(STACKADDR),
		.PROGADDR_RESET(PROGADDR_RESET),
		.BARREL_SHIFTER(1),
		.ENABLE_IRQ(1),
		.ENABLE_IRQ_QREGS(0)
		) 
		cpu (
			.clk         (clk        ),
			.resetn      (resetn     ),
			.mem_valid   (mem_valid  ),
			.mem_instr   (mem_instr  ),
			.mem_ready   (mem_ready  ),
			.mem_addr    (mem_addr   ),
			.mem_wdata   (mem_wdata  ),
			.mem_wstrb   (mem_wstrb  ),
			.mem_rdata   (mem_rdata  )
		);
		

	picosoc_mem #(.WORDS(MEM_WORDS)) internal_sram (
		.clk(clk),
		.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
		.addr(mem_addr[23:2]),
		.wdata(mem_wdata),
		.rdata(sram_rdata)
	);
endmodule