data/full_repos/permissive/183345139/hba_sonar/hba_sonar.v
1: b"%Error: data/full_repos/permissive/183345139/hba_sonar/hba_sonar.v:183: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\n    .dist(reg_sonar0_in),   \n     ^~~~\n%Error: data/full_repos/permissive/183345139/hba_sonar/hba_sonar.v:183: syntax error, unexpected '('\n    .dist(reg_sonar0_in),   \n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/183345139/hba_sonar/hba_sonar.v:197: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\n    .dist(reg_sonar1_in),   \n     ^~~~\n%Error: data/full_repos/permissive/183345139/hba_sonar/hba_sonar.v:197: syntax error, unexpected '('\n    .dist(reg_sonar1_in),   \n          ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module hba_sonar #
(



    parameter integer DBUS_WIDTH = 8,
    parameter integer PERIPH_ADDR_WIDTH = 4,
    parameter integer REG_ADDR_WIDTH = 8,
    parameter integer ADDR_WIDTH = PERIPH_ADDR_WIDTH + REG_ADDR_WIDTH,
    parameter integer PERIPH_ADDR = 0
)
(

    input wire hba_clk,
    input wire hba_reset,
    input wire hba_rnw,
    input wire hba_select,
    input wire [ADDR_WIDTH-1:0] hba_abus,
    input wire [DBUS_WIDTH-1:0] hba_dbus,

    output wire [DBUS_WIDTH-1:0] hba_dbus_slave,
    output wire hba_xferack_slave,


    output wire slave_interrupt,


    output wire [1:0] sonar_trig,
    input wire [1:0] sonar_echo,
    input wire sonar_sync_in,
    output wire sonar_sync_out
);




wire [DBUS_WIDTH-1:0] reg_ctrl;

wire [DBUS_WIDTH-1:0] reg_sonar0_in;
wire [DBUS_WIDTH-1:0] reg_sonar1_in;

wire [DBUS_WIDTH-1:0] reg_delay0;
wire [DBUS_WIDTH-1:0] reg_delay1;
wire [DBUS_WIDTH-1:0] reg_period;


wire slv_wr_en;


wire [1:0] sonar_valid;


reg sonar_sync;

assign slave_interrupt = sonar_valid;
assign slv_wr_en = sonar_valid;

wire sonar0_en;
assign sonar0_en = reg_ctrl[0];

wire sonar1_en;
assign sonar1_en = reg_ctrl[1];



hba_reg_bank #
(
    .DBUS_WIDTH(DBUS_WIDTH),
    .PERIPH_ADDR_WIDTH(PERIPH_ADDR_WIDTH),
    .REG_ADDR_WIDTH(REG_ADDR_WIDTH),
    .PERIPH_ADDR(PERIPH_ADDR)
) hba_reg_bank_inst
(

    .hba_clk(hba_clk),
    .hba_reset(hba_reset),
    .hba_rnw(hba_rnw),
    .hba_select(hba_select),
    .hba_abus(hba_abus),
    .hba_dbus(hba_dbus),

    .hba_dbus_slave(hba_dbus_slave),
    .hba_xferack_slave(hba_xferack_slave),




    .slv_reg0(reg_ctrl),


    






    .slv_reg1_in(reg_sonar0_in),
    .slv_reg2_in(reg_sonar1_in),

    .slv_wr_en(slv_wr_en),
    .slv_wr_mask(4'b0110),
    .slv_autoclr_mask(4'b0000)
);

sr04 sr04_inst0
(
    .clk(hba_clk),
    .reset(hba_reset),
    .en(sonar0_en),
    .sync(sonar_sync),

    .trig(sonar_trig[0]),
    .echo(sonar_echo[0]),

    .dist(reg_sonar0_in),
    .valid(sonar_valid[0])
);

sr04 sr04_inst1
(
    .clk(hba_clk),
    .reset(hba_reset),
    .en(sonar1_en),
    .sync(sonar_sync),

    .trig(sonar_trig[1]),
    .echo(sonar_echo[1]),

    .dist(reg_sonar1_in),
    .valid(sonar_valid[1])
);







reg [22:0] sync_count;
localparam SYNC_COUNT_MAX = 5_000_000;
always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        sonar_sync <= 0;
        sync_count <= 0;
    end else begin
        sonar_sync <= 0;
        sync_count <= sync_count + 1;
        if (sync_count == (SYNC_COUNT_MAX-1)) begin
            sync_count <= 0;
            sonar_sync <= 1;
        end
    end
end


endmodule
module hba_sonar #
(



    parameter integer DBUS_WIDTH = 8,
    parameter integer PERIPH_ADDR_WIDTH = 4,
    parameter integer REG_ADDR_WIDTH = 8,
    parameter integer ADDR_WIDTH = PERIPH_ADDR_WIDTH + REG_ADDR_WIDTH,
    parameter integer PERIPH_ADDR = 0
)
(

    input wire hba_clk,
    input wire hba_reset,
    input wire hba_rnw,
    input wire hba_select,
    input wire [ADDR_WIDTH-1:0] hba_abus,
    input wire [DBUS_WIDTH-1:0] hba_dbus,

    output wire [DBUS_WIDTH-1:0] hba_dbus_slave,
    output wire hba_xferack_slave,


    output wire slave_interrupt,


    output wire [1:0] sonar_trig,
    input wire [1:0] sonar_echo,
    input wire sonar_sync_in,
    output wire sonar_sync_out
);





wire [DBUS_WIDTH-1:0] reg_ctrl;

wire [DBUS_WIDTH-1:0] reg_sonar0_in;
wire [DBUS_WIDTH-1:0] reg_sonar1_in;

wire [DBUS_WIDTH-1:0] reg_delay0;
wire [DBUS_WIDTH-1:0] reg_delay1;
wire [DBUS_WIDTH-1:0] reg_period;


wire slv_wr_en;


wire [1:0] sonar_valid;


reg sonar_sync;

assign slave_interrupt = sonar_valid;
assign slv_wr_en = sonar_valid;

wire sonar0_en;
assign sonar0_en = reg_ctrl[0];

wire sonar1_en;
assign sonar1_en = reg_ctrl[1];



hba_reg_bank #
(
    .DBUS_WIDTH(DBUS_WIDTH),
    .PERIPH_ADDR_WIDTH(PERIPH_ADDR_WIDTH),
    .REG_ADDR_WIDTH(REG_ADDR_WIDTH),
    .PERIPH_ADDR(PERIPH_ADDR)
) hba_reg_bank_inst
(

    .hba_clk(hba_clk),
    .hba_reset(hba_reset),
    .hba_rnw(hba_rnw),
    .hba_select(hba_select),
    .hba_abus(hba_abus),
    .hba_dbus(hba_dbus),

    .hba_dbus_slave(hba_dbus_slave),
    .hba_xferack_slave(hba_xferack_slave),




    .slv_reg0(reg_ctrl),


    






    .slv_reg1_in(reg_sonar0_in),
    .slv_reg2_in(reg_sonar1_in),

    .slv_wr_en(slv_wr_en),
    .slv_wr_mask(4'b0110),
    .slv_autoclr_mask(4'b0000)
);

sr04 sr04_inst0
(
    .clk(hba_clk),
    .reset(hba_reset),
    .en(sonar0_en),
    .sync(sonar_sync),

    .trig(sonar_trig[0]),
    .echo(sonar_echo[0]),

    .dist(reg_sonar0_in),
    .valid(sonar_valid[0])
);

sr04 sr04_inst1
(
    .clk(hba_clk),
    .reset(hba_reset),
    .en(sonar1_en),
    .sync(sonar_sync),

    .trig(sonar_trig[1]),
    .echo(sonar_echo[1]),

    .dist(reg_sonar1_in),
    .valid(sonar_valid[1])
);







reg [22:0] sync_count;
localparam SYNC_COUNT_MAX = 5_000_000;
always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        sonar_sync <= 0;
        sync_count <= 0;
    end else begin
        sonar_sync <= 0;
        sync_count <= sync_count + 1;
        if (sync_count == (SYNC_COUNT_MAX-1)) begin
            sync_count <= 0;
            sonar_sync <= 1;
        end
    end
end


endmodule