data/full_repos/permissive/107757225/audio/audio-altera/DE2_115_Audio.v
1: b"%Error: data/full_repos/permissive/107757225/audio/audio-altera/DE2_115_Audio.v:461: Cannot find file containing module: 'audio_nios'\naudio_nios nios_audio_ins(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/107757225/audio/audio-altera,data/full_repos/permissive/107757225/audio_nios\n             data/full_repos/permissive/107757225/audio/audio-altera,data/full_repos/permissive/107757225/audio_nios.v\n             data/full_repos/permissive/107757225/audio/audio-altera,data/full_repos/permissive/107757225/audio_nios.sv\n             audio_nios\n             audio_nios.v\n             audio_nios.sv\n             obj_dir/audio_nios\n             obj_dir/audio_nios.v\n             obj_dir/audio_nios.sv\n%Error: Exiting due to 1 error(s)\n"
module DE2_115_Audio( 


	CLOCK_50,
   CLOCK2_50,
   CLOCK3_50,
	ENETCLK_25,


	SMA_CLKIN,
	SMA_CLKOUT,


	LEDG,
	LEDR,


	KEY,


	SW,


	HEX0,
	HEX1,
	HEX2,
	HEX3,
	HEX4,
	HEX5,
	HEX6,
	HEX7,


	LCD_BLON,
	LCD_DATA,
	LCD_EN,
	LCD_ON,
	LCD_RS,
	LCD_RW,


	UART_CTS,
	UART_RTS,
	UART_RXD,
	UART_TXD,


	PS2_CLK,
	PS2_DAT,
	PS2_CLK2,
	PS2_DAT2,


	SD_CLK,
	SD_CMD,
	SD_DAT,
	SD_WP_N,


	VGA_B,
	VGA_BLANK_N,
	VGA_CLK,
	VGA_G,
	VGA_HS,
	VGA_R,
	VGA_SYNC_N,
	VGA_VS,


	AUD_ADCDAT,
	AUD_ADCLRCK,
	AUD_BCLK,
	AUD_DACDAT,
	AUD_DACLRCK,
	AUD_XCK,


	EEP_I2C_SCLK,
	EEP_I2C_SDAT,


	I2C_SCLK,
	I2C_SDAT,


	ENET0_GTX_CLK,
	ENET0_INT_N,
	ENET0_MDC,
	ENET0_MDIO,
	ENET0_RST_N,
	ENET0_RX_CLK,
	ENET0_RX_COL,
	ENET0_RX_CRS,
	ENET0_RX_DATA,
	ENET0_RX_DV,
	ENET0_RX_ER,
	ENET0_TX_CLK,
	ENET0_TX_DATA,
	ENET0_TX_EN,
	ENET0_TX_ER,
	ENET0_LINK100,


	ENET1_GTX_CLK,
	ENET1_INT_N,
	ENET1_MDC,
	ENET1_MDIO,
	ENET1_RST_N,
	ENET1_RX_CLK,
	ENET1_RX_COL,
	ENET1_RX_CRS,
	ENET1_RX_DATA,
	ENET1_RX_DV,
	ENET1_RX_ER,
	ENET1_TX_CLK,
	ENET1_TX_DATA,
	ENET1_TX_EN,
	ENET1_TX_ER,
	ENET1_LINK100,


	TD_CLK27,
	TD_DATA,
	TD_HS,
	TD_RESET_N,
	TD_VS,


   OTG_DATA,
   OTG_ADDR,
   OTG_CS_N,
   OTG_WR_N,
   OTG_RD_N,
   OTG_INT,
   OTG_RST_N,

	IRDA_RXD,


	DRAM_ADDR,
	DRAM_BA,
	DRAM_CAS_N,
	DRAM_CKE,
	DRAM_CLK,
	DRAM_CS_N,
	DRAM_DQ,
	DRAM_DQM,
	DRAM_RAS_N,
	DRAM_WE_N,


	SRAM_ADDR,
	SRAM_CE_N,
	SRAM_DQ,
	SRAM_LB_N,
	SRAM_OE_N,
	SRAM_UB_N,
	SRAM_WE_N,


	FL_ADDR,
	FL_CE_N,
	FL_DQ,
	FL_OE_N,
	FL_RST_N,
	FL_RY,
	FL_WE_N,
	FL_WP_N,


	GPIO,




	HSMC_CLKIN_P1,
	HSMC_CLKIN_P2,
	HSMC_CLKIN0,


	HSMC_CLKOUT_P1,
	HSMC_CLKOUT_P2,
	HSMC_CLKOUT0,
	HSMC_D,

	HSMC_RX_D_P,

	HSMC_TX_D_P,
	

   EX_IO	
);











input		          			CLOCK_50;
input		          			CLOCK2_50;
input		          			CLOCK3_50;
input		          			ENETCLK_25;


input		          			SMA_CLKIN;
output		          		SMA_CLKOUT;


output		     [8:0]		LEDG;
output		     [17:0]		LEDR;


input		     	  [3:0]		KEY;


input		        [17:0]		SW;


output		     [6:0]		HEX0;
output		     [6:0]		HEX1;
output		     [6:0]		HEX2;
output		     [6:0]		HEX3;
output		     [6:0]		HEX4;
output		     [6:0]		HEX5;
output		     [6:0]		HEX6;
output		     [6:0]		HEX7;


output		          		LCD_BLON;
inout		        [7:0]		LCD_DATA;
output		          		LCD_EN;
output		          		LCD_ON;
output		          		LCD_RS;
output		          		LCD_RW;


input		          		UART_CTS;
output		          			UART_RTS;
input		          			UART_RXD;
output		          		UART_TXD;


inout		          			PS2_CLK;
inout		          			PS2_DAT;
inout		          			PS2_CLK2;
inout		          			PS2_DAT2;


output		          		SD_CLK;
inout		          			SD_CMD;
inout		        [3:0]		SD_DAT;
input		          			SD_WP_N;


output		     [7:0]		VGA_B;
output		          		VGA_BLANK_N;
output		          		VGA_CLK;
output		     [7:0]		VGA_G;
output		          		VGA_HS;
output		     [7:0]		VGA_R;
output		          		VGA_SYNC_N;
output		          		VGA_VS;


input		          			AUD_ADCDAT;
inout		          			AUD_ADCLRCK;
inout		          			AUD_BCLK;
output		          		AUD_DACDAT;
inout		          			AUD_DACLRCK;
output		          		AUD_XCK;


output		          		EEP_I2C_SCLK;
inout		          			EEP_I2C_SDAT;


output		          		I2C_SCLK;
inout		          			I2C_SDAT;


output		          		ENET0_GTX_CLK;
input		          			ENET0_INT_N;
output		          		ENET0_MDC;
input		          			ENET0_MDIO;
output		          		ENET0_RST_N;
input		          			ENET0_RX_CLK;
input		          			ENET0_RX_COL;
input		          			ENET0_RX_CRS;
input		        [3:0]		ENET0_RX_DATA;
input		          			ENET0_RX_DV;
input		          			ENET0_RX_ER;
input		          			ENET0_TX_CLK;
output		     [3:0]		ENET0_TX_DATA;
output		          		ENET0_TX_EN;
output		          		ENET0_TX_ER;
input		          			ENET0_LINK100;


output		          		ENET1_GTX_CLK;
input		          			ENET1_INT_N;
output		          		ENET1_MDC;
input		          			ENET1_MDIO;
output		          		ENET1_RST_N;
input		          			ENET1_RX_CLK;
input		          			ENET1_RX_COL;
input		          			ENET1_RX_CRS;
input		        [3:0]		ENET1_RX_DATA;
input		          			ENET1_RX_DV;
input		          			ENET1_RX_ER;
input		          			ENET1_TX_CLK;
output		     [3:0]		ENET1_TX_DATA;
output		          		ENET1_TX_EN;
output		          		ENET1_TX_ER;
input		          			ENET1_LINK100;


input		          			TD_CLK27;
input		        [7:0]		TD_DATA;
input		          			TD_HS;
output		          		TD_RESET_N;
input		          			TD_VS;



inout            [15:0]    OTG_DATA;
output           [1:0]     OTG_ADDR;
output                     OTG_CS_N;
output                     OTG_WR_N;
output                     OTG_RD_N;
input                      OTG_INT;
output                     OTG_RST_N;


input		          			IRDA_RXD;


output		     [12:0]		DRAM_ADDR;
output		     [1:0]		DRAM_BA;
output		          		DRAM_CAS_N;
output		          		DRAM_CKE;
output		          		DRAM_CLK;
output		          		DRAM_CS_N;
inout		        [31:0]		DRAM_DQ;
output		     [3:0]		DRAM_DQM;
output		          		DRAM_RAS_N;
output		          		DRAM_WE_N;


output		     [19:0]		SRAM_ADDR;
output		           		SRAM_CE_N;
inout		        [15:0]		SRAM_DQ;
output		          		SRAM_LB_N;
output		          		SRAM_OE_N;
output		          		SRAM_UB_N;
output		          		SRAM_WE_N;


output		     [22:0]		FL_ADDR;
output		          		FL_CE_N;
inout		        [7:0]		FL_DQ;
output		          		FL_OE_N;
output		          		FL_RST_N;
input		          			FL_RY;
output		          		FL_WE_N;
output		          		FL_WP_N;


inout		       [35:0]		GPIO;





input		          			HSMC_CLKIN_P1;
input		          			HSMC_CLKIN_P2;
input		          			HSMC_CLKIN0;


output		          		HSMC_CLKOUT_P1;
output		          		HSMC_CLKOUT_P2;
output		          		HSMC_CLKOUT0;
inout		       [3:0]		HSMC_D;

input		       [16:0]		HSMC_RX_D_P;

output		    [16:0]		HSMC_TX_D_P;


inout		       [6:0]		EX_IO;






wire 								HEX0P;
wire 								HEX1P;
wire 								HEX2P;
wire 								HEX3P;
wire 								HEX4P;
wire 								HEX5P;
wire 								HEX6P;
wire 								HEX7P;





wire reset_n;

assign reset_n = 1'b1;

audio_nios nios_audio_ins(

                       .clk_clk(CLOCK_50),
                       .reset_reset_n(reset_n),
                       .altpll_c3_clk(),
                       .altpll_c1_clk(DRAM_CLK),                    


                       .audio_conduit_end_ADCDAT(AUD_ADCDAT),
                       .audio_conduit_end_ADCLRC(AUD_ADCLRCK),
                       .audio_conduit_end_BCLK(AUD_BCLK),
                       .audio_conduit_end_DACDAT(AUD_DACDAT),
                       .audio_conduit_end_DACLRC(AUD_DACLRCK),
                       .audio_conduit_end_XCK (AUD_XCK),


                       .epp_i2c_scl_external_connection_export(EEP_I2C_SCLK),


                       .epp_i2c_sda_external_connection_export(EEP_I2C_SDAT),
							  

                       .i2c_scl_external_connection_export(I2C_SCLK),


                       .i2c_sda_external_connection_export(I2C_SDAT),


                       .key_external_connection_export(KEY),


                       .lcd_external_E(LCD_EN),
                       .lcd_external_RS(LCD_RS),
                       .lcd_external_RW(LCD_RW),
                       .lcd_external_data(LCD_DATA),
                       

                       .sdram_wire_addr(DRAM_ADDR),
                       .sdram_wire_ba(DRAM_BA),
                       .sdram_wire_cas_n(DRAM_CAS_N),
                       .sdram_wire_cke(DRAM_CKE),
                       .sdram_wire_cs_n(DRAM_CS_N),
                       .sdram_wire_dq(DRAM_DQ),
                       .sdram_wire_dqm(DRAM_DQM),
                       .sdram_wire_ras_n(DRAM_RAS_N),
                       .sdram_wire_we_n(DRAM_WE_N),
                       

                       .seg7_conduit_end_export({
                              HEX7P, HEX7, HEX6P, HEX6,
                              HEX5P, HEX5, HEX4P, HEX4, 
                              HEX3P, HEX3, HEX2P, HEX2,
                              HEX1P, HEX1, HEX0P, HEX0}),


                       .sram_conduit_end_ADDR(SRAM_ADDR),
                       .sram_conduit_end_CE_n(SRAM_CE_N),
                       .sram_conduit_end_DQ(SRAM_DQ),
                       .sram_conduit_end_LB_n(SRAM_LB_N),
                       .sram_conduit_end_OE_n(SRAM_OE_N),
                       .sram_conduit_end_UB_n(SRAM_UB_N),
                       .sram_conduit_end_WE_n(SRAM_WE_N),
                       

                       .sw_external_connection_export(SW),
							  

                       .pio_0_external_connection_export({LEDG,LEDR[17:1]}),


                       .tri_state_bridge_flash_bridge_0_out_address_to_the_cfi_flash (FL_ADDR),
                       .tri_state_bridge_flash_bridge_0_out_read_n_to_the_cfi_flash(FL_OE_N),
                       .tri_state_bridge_flash_bridge_0_out_select_n_to_the_cfi_flash(FL_CE_N),
                       .tri_state_bridge_flash_bridge_0_out_tri_state_bridge_flash_data(FL_DQ),
                       .tri_state_bridge_flash_bridge_0_out_write_n_to_the_cfi_flash(FL_WE_N),
                       

                       .sd_clk_external_connection_export(SD_CLK),
                       .sd_cmd_external_connection_export(SD_CMD),
                       .sd_dat_external_connection_export(SD_DAT),
                       .sd_wp_n_external_connection_export (SD_WP_N)
                       
                    );
                    
                 


assign	FL_RST_N = reset_n;
assign	FL_WP_N = 1'b1;




assign   LCD_BLON = 0;
assign   LCD_ON = 1'b1;

wire 	   io_dir;
wire 	   action;
assign   io_dir = KEY[0] & action;



assign   GPIO[17:0] = (io_dir)?GPIO[35:18]:18'hz;
assign   GPIO[35:18] = (io_dir)?GPIO[17:0]:18'hz;



assign   HSMC_D[1:0] = (io_dir)?HSMC_D[3:2]:2'hz;
assign   HSMC_D[3:2] = (io_dir)?HSMC_D[1:0]:2'hz;
assign   HSMC_TX_D_P = HSMC_RX_D_P;
assign   HSMC_CLKOUT_P1 = HSMC_CLKIN_P1;
assign   HSMC_CLKOUT_P2 = HSMC_CLKIN_P2;
assign   HSMC_CLKOUT0 = HSMC_CLKIN0;



assign   VGA_BLANK_N = 1'b1;
assign   VGA_SYNC_N = 1'b1;




assign   ENET0_GTX_CLK = ENET0_INT_N;
assign   ENET0_MDC = ENET0_RX_COL;
assign   ENET0_RST_N = ENET0_RX_CRS;
assign   ENET0_TX_DATA = ENET0_RX_DATA;
assign   ENET0_TX_EN = ENET0_RX_ER;
assign   ENET0_TX_ER = ENET0_TX_CLK;
assign   ENET1_GTX_CLK = ENET1_INT_N; 
assign   ENET1_MDC = ENET1_RX_COL;
assign   ENET1_RST_N = ENET1_RX_CRS;
assign   ENET1_TX_DATA = ENET1_RX_DATA;
assign   ENET1_TX_EN = ENET1_RX_ER;
assign   ENET1_TX_ER = ENET1_TX_CLK;



assign   TD_RESET_N = TD_VS;
assign   action = FL_RY & TD_HS & TD_CLK27 & (TD_DATA == 8'hff);



assign   PS2_CLK = PS2_DAT;
assign   PS2_CLK2 = PS2_DAT2;

endmodule
module DE2_115_Audio( 


	CLOCK_50,
   CLOCK2_50,
   CLOCK3_50,
	ENETCLK_25,


	SMA_CLKIN,
	SMA_CLKOUT,


	LEDG,
	LEDR,


	KEY,


	SW,


	HEX0,
	HEX1,
	HEX2,
	HEX3,
	HEX4,
	HEX5,
	HEX6,
	HEX7,


	LCD_BLON,
	LCD_DATA,
	LCD_EN,
	LCD_ON,
	LCD_RS,
	LCD_RW,


	UART_CTS,
	UART_RTS,
	UART_RXD,
	UART_TXD,


	PS2_CLK,
	PS2_DAT,
	PS2_CLK2,
	PS2_DAT2,


	SD_CLK,
	SD_CMD,
	SD_DAT,
	SD_WP_N,


	VGA_B,
	VGA_BLANK_N,
	VGA_CLK,
	VGA_G,
	VGA_HS,
	VGA_R,
	VGA_SYNC_N,
	VGA_VS,


	AUD_ADCDAT,
	AUD_ADCLRCK,
	AUD_BCLK,
	AUD_DACDAT,
	AUD_DACLRCK,
	AUD_XCK,


	EEP_I2C_SCLK,
	EEP_I2C_SDAT,


	I2C_SCLK,
	I2C_SDAT,


	ENET0_GTX_CLK,
	ENET0_INT_N,
	ENET0_MDC,
	ENET0_MDIO,
	ENET0_RST_N,
	ENET0_RX_CLK,
	ENET0_RX_COL,
	ENET0_RX_CRS,
	ENET0_RX_DATA,
	ENET0_RX_DV,
	ENET0_RX_ER,
	ENET0_TX_CLK,
	ENET0_TX_DATA,
	ENET0_TX_EN,
	ENET0_TX_ER,
	ENET0_LINK100,


	ENET1_GTX_CLK,
	ENET1_INT_N,
	ENET1_MDC,
	ENET1_MDIO,
	ENET1_RST_N,
	ENET1_RX_CLK,
	ENET1_RX_COL,
	ENET1_RX_CRS,
	ENET1_RX_DATA,
	ENET1_RX_DV,
	ENET1_RX_ER,
	ENET1_TX_CLK,
	ENET1_TX_DATA,
	ENET1_TX_EN,
	ENET1_TX_ER,
	ENET1_LINK100,


	TD_CLK27,
	TD_DATA,
	TD_HS,
	TD_RESET_N,
	TD_VS,


   OTG_DATA,
   OTG_ADDR,
   OTG_CS_N,
   OTG_WR_N,
   OTG_RD_N,
   OTG_INT,
   OTG_RST_N,

	IRDA_RXD,


	DRAM_ADDR,
	DRAM_BA,
	DRAM_CAS_N,
	DRAM_CKE,
	DRAM_CLK,
	DRAM_CS_N,
	DRAM_DQ,
	DRAM_DQM,
	DRAM_RAS_N,
	DRAM_WE_N,


	SRAM_ADDR,
	SRAM_CE_N,
	SRAM_DQ,
	SRAM_LB_N,
	SRAM_OE_N,
	SRAM_UB_N,
	SRAM_WE_N,


	FL_ADDR,
	FL_CE_N,
	FL_DQ,
	FL_OE_N,
	FL_RST_N,
	FL_RY,
	FL_WE_N,
	FL_WP_N,


	GPIO,




	HSMC_CLKIN_P1,
	HSMC_CLKIN_P2,
	HSMC_CLKIN0,


	HSMC_CLKOUT_P1,
	HSMC_CLKOUT_P2,
	HSMC_CLKOUT0,
	HSMC_D,

	HSMC_RX_D_P,

	HSMC_TX_D_P,
	

   EX_IO	
);












input		          			CLOCK_50;
input		          			CLOCK2_50;
input		          			CLOCK3_50;
input		          			ENETCLK_25;


input		          			SMA_CLKIN;
output		          		SMA_CLKOUT;


output		     [8:0]		LEDG;
output		     [17:0]		LEDR;


input		     	  [3:0]		KEY;


input		        [17:0]		SW;


output		     [6:0]		HEX0;
output		     [6:0]		HEX1;
output		     [6:0]		HEX2;
output		     [6:0]		HEX3;
output		     [6:0]		HEX4;
output		     [6:0]		HEX5;
output		     [6:0]		HEX6;
output		     [6:0]		HEX7;


output		          		LCD_BLON;
inout		        [7:0]		LCD_DATA;
output		          		LCD_EN;
output		          		LCD_ON;
output		          		LCD_RS;
output		          		LCD_RW;


input		          		UART_CTS;
output		          			UART_RTS;
input		          			UART_RXD;
output		          		UART_TXD;


inout		          			PS2_CLK;
inout		          			PS2_DAT;
inout		          			PS2_CLK2;
inout		          			PS2_DAT2;


output		          		SD_CLK;
inout		          			SD_CMD;
inout		        [3:0]		SD_DAT;
input		          			SD_WP_N;


output		     [7:0]		VGA_B;
output		          		VGA_BLANK_N;
output		          		VGA_CLK;
output		     [7:0]		VGA_G;
output		          		VGA_HS;
output		     [7:0]		VGA_R;
output		          		VGA_SYNC_N;
output		          		VGA_VS;


input		          			AUD_ADCDAT;
inout		          			AUD_ADCLRCK;
inout		          			AUD_BCLK;
output		          		AUD_DACDAT;
inout		          			AUD_DACLRCK;
output		          		AUD_XCK;


output		          		EEP_I2C_SCLK;
inout		          			EEP_I2C_SDAT;


output		          		I2C_SCLK;
inout		          			I2C_SDAT;


output		          		ENET0_GTX_CLK;
input		          			ENET0_INT_N;
output		          		ENET0_MDC;
input		          			ENET0_MDIO;
output		          		ENET0_RST_N;
input		          			ENET0_RX_CLK;
input		          			ENET0_RX_COL;
input		          			ENET0_RX_CRS;
input		        [3:0]		ENET0_RX_DATA;
input		          			ENET0_RX_DV;
input		          			ENET0_RX_ER;
input		          			ENET0_TX_CLK;
output		     [3:0]		ENET0_TX_DATA;
output		          		ENET0_TX_EN;
output		          		ENET0_TX_ER;
input		          			ENET0_LINK100;


output		          		ENET1_GTX_CLK;
input		          			ENET1_INT_N;
output		          		ENET1_MDC;
input		          			ENET1_MDIO;
output		          		ENET1_RST_N;
input		          			ENET1_RX_CLK;
input		          			ENET1_RX_COL;
input		          			ENET1_RX_CRS;
input		        [3:0]		ENET1_RX_DATA;
input		          			ENET1_RX_DV;
input		          			ENET1_RX_ER;
input		          			ENET1_TX_CLK;
output		     [3:0]		ENET1_TX_DATA;
output		          		ENET1_TX_EN;
output		          		ENET1_TX_ER;
input		          			ENET1_LINK100;


input		          			TD_CLK27;
input		        [7:0]		TD_DATA;
input		          			TD_HS;
output		          		TD_RESET_N;
input		          			TD_VS;



inout            [15:0]    OTG_DATA;
output           [1:0]     OTG_ADDR;
output                     OTG_CS_N;
output                     OTG_WR_N;
output                     OTG_RD_N;
input                      OTG_INT;
output                     OTG_RST_N;


input		          			IRDA_RXD;


output		     [12:0]		DRAM_ADDR;
output		     [1:0]		DRAM_BA;
output		          		DRAM_CAS_N;
output		          		DRAM_CKE;
output		          		DRAM_CLK;
output		          		DRAM_CS_N;
inout		        [31:0]		DRAM_DQ;
output		     [3:0]		DRAM_DQM;
output		          		DRAM_RAS_N;
output		          		DRAM_WE_N;


output		     [19:0]		SRAM_ADDR;
output		           		SRAM_CE_N;
inout		        [15:0]		SRAM_DQ;
output		          		SRAM_LB_N;
output		          		SRAM_OE_N;
output		          		SRAM_UB_N;
output		          		SRAM_WE_N;


output		     [22:0]		FL_ADDR;
output		          		FL_CE_N;
inout		        [7:0]		FL_DQ;
output		          		FL_OE_N;
output		          		FL_RST_N;
input		          			FL_RY;
output		          		FL_WE_N;
output		          		FL_WP_N;


inout		       [35:0]		GPIO;





input		          			HSMC_CLKIN_P1;
input		          			HSMC_CLKIN_P2;
input		          			HSMC_CLKIN0;


output		          		HSMC_CLKOUT_P1;
output		          		HSMC_CLKOUT_P2;
output		          		HSMC_CLKOUT0;
inout		       [3:0]		HSMC_D;

input		       [16:0]		HSMC_RX_D_P;

output		    [16:0]		HSMC_TX_D_P;


inout		       [6:0]		EX_IO;






wire 								HEX0P;
wire 								HEX1P;
wire 								HEX2P;
wire 								HEX3P;
wire 								HEX4P;
wire 								HEX5P;
wire 								HEX6P;
wire 								HEX7P;





wire reset_n;

assign reset_n = 1'b1;

audio_nios nios_audio_ins(

                       .clk_clk(CLOCK_50),
                       .reset_reset_n(reset_n),
                       .altpll_c3_clk(),
                       .altpll_c1_clk(DRAM_CLK),                    


                       .audio_conduit_end_ADCDAT(AUD_ADCDAT),
                       .audio_conduit_end_ADCLRC(AUD_ADCLRCK),
                       .audio_conduit_end_BCLK(AUD_BCLK),
                       .audio_conduit_end_DACDAT(AUD_DACDAT),
                       .audio_conduit_end_DACLRC(AUD_DACLRCK),
                       .audio_conduit_end_XCK (AUD_XCK),


                       .epp_i2c_scl_external_connection_export(EEP_I2C_SCLK),


                       .epp_i2c_sda_external_connection_export(EEP_I2C_SDAT),
							  

                       .i2c_scl_external_connection_export(I2C_SCLK),


                       .i2c_sda_external_connection_export(I2C_SDAT),


                       .key_external_connection_export(KEY),


                       .lcd_external_E(LCD_EN),
                       .lcd_external_RS(LCD_RS),
                       .lcd_external_RW(LCD_RW),
                       .lcd_external_data(LCD_DATA),
                       

                       .sdram_wire_addr(DRAM_ADDR),
                       .sdram_wire_ba(DRAM_BA),
                       .sdram_wire_cas_n(DRAM_CAS_N),
                       .sdram_wire_cke(DRAM_CKE),
                       .sdram_wire_cs_n(DRAM_CS_N),
                       .sdram_wire_dq(DRAM_DQ),
                       .sdram_wire_dqm(DRAM_DQM),
                       .sdram_wire_ras_n(DRAM_RAS_N),
                       .sdram_wire_we_n(DRAM_WE_N),
                       

                       .seg7_conduit_end_export({
                              HEX7P, HEX7, HEX6P, HEX6,
                              HEX5P, HEX5, HEX4P, HEX4, 
                              HEX3P, HEX3, HEX2P, HEX2,
                              HEX1P, HEX1, HEX0P, HEX0}),


                       .sram_conduit_end_ADDR(SRAM_ADDR),
                       .sram_conduit_end_CE_n(SRAM_CE_N),
                       .sram_conduit_end_DQ(SRAM_DQ),
                       .sram_conduit_end_LB_n(SRAM_LB_N),
                       .sram_conduit_end_OE_n(SRAM_OE_N),
                       .sram_conduit_end_UB_n(SRAM_UB_N),
                       .sram_conduit_end_WE_n(SRAM_WE_N),
                       

                       .sw_external_connection_export(SW),
							  

                       .pio_0_external_connection_export({LEDG,LEDR[17:1]}),


                       .tri_state_bridge_flash_bridge_0_out_address_to_the_cfi_flash (FL_ADDR),
                       .tri_state_bridge_flash_bridge_0_out_read_n_to_the_cfi_flash(FL_OE_N),
                       .tri_state_bridge_flash_bridge_0_out_select_n_to_the_cfi_flash(FL_CE_N),
                       .tri_state_bridge_flash_bridge_0_out_tri_state_bridge_flash_data(FL_DQ),
                       .tri_state_bridge_flash_bridge_0_out_write_n_to_the_cfi_flash(FL_WE_N),
                       

                       .sd_clk_external_connection_export(SD_CLK),
                       .sd_cmd_external_connection_export(SD_CMD),
                       .sd_dat_external_connection_export(SD_DAT),
                       .sd_wp_n_external_connection_export (SD_WP_N)
                       
                    );
                    
                 


assign	FL_RST_N = reset_n;
assign	FL_WP_N = 1'b1;




assign   LCD_BLON = 0;
assign   LCD_ON = 1'b1;

wire 	   io_dir;
wire 	   action;
assign   io_dir = KEY[0] & action;



assign   GPIO[17:0] = (io_dir)?GPIO[35:18]:18'hz;
assign   GPIO[35:18] = (io_dir)?GPIO[17:0]:18'hz;



assign   HSMC_D[1:0] = (io_dir)?HSMC_D[3:2]:2'hz;
assign   HSMC_D[3:2] = (io_dir)?HSMC_D[1:0]:2'hz;
assign   HSMC_TX_D_P = HSMC_RX_D_P;
assign   HSMC_CLKOUT_P1 = HSMC_CLKIN_P1;
assign   HSMC_CLKOUT_P2 = HSMC_CLKIN_P2;
assign   HSMC_CLKOUT0 = HSMC_CLKIN0;



assign   VGA_BLANK_N = 1'b1;
assign   VGA_SYNC_N = 1'b1;




assign   ENET0_GTX_CLK = ENET0_INT_N;
assign   ENET0_MDC = ENET0_RX_COL;
assign   ENET0_RST_N = ENET0_RX_CRS;
assign   ENET0_TX_DATA = ENET0_RX_DATA;
assign   ENET0_TX_EN = ENET0_RX_ER;
assign   ENET0_TX_ER = ENET0_TX_CLK;
assign   ENET1_GTX_CLK = ENET1_INT_N; 
assign   ENET1_MDC = ENET1_RX_COL;
assign   ENET1_RST_N = ENET1_RX_CRS;
assign   ENET1_TX_DATA = ENET1_RX_DATA;
assign   ENET1_TX_EN = ENET1_RX_ER;
assign   ENET1_TX_ER = ENET1_TX_CLK;



assign   TD_RESET_N = TD_VS;
assign   action = FL_RY & TD_HS & TD_CLK27 & (TD_DATA == 8'hff);



assign   PS2_CLK = PS2_DAT;
assign   PS2_CLK2 = PS2_DAT2;

endmodule