data/full_repos/permissive/202237519/verilog/digitalsystem9/rgb.v
data/verilator_xmls/1804052b-bfab-4b35-b574-7818c8641c9d.xml
module HB_FULL_LED (RESETN, CLK, R_IN, G_IN, B_IN, R,G,B);

    input RESETN,CLK;
    input [1:0] R_IN,G_IN,B_IN;
    output [3:0] R,G,B;

    integer CNT;
    integer R_REG, G_REG, B_REG;

    reg[3:0] R, G, B;





    always @(posedge RESETN or posedge CLK) begin
        if(RESETN) R = 4'b0000;
        else if (CNT < R_REG) R = 4'b1111;
        else R = 4'b0000;
    end

    always @(posedge RESETN or posedge CLK) begin
        if(RESETN) G = 4'b0000;
        else if (CNT < G_REG) G = 4'b1111;
        else G = 4'b0000;
    end

    always @(posedge RESETN or posedge CLK) begin
        if(RESETN) B = 4'b0000;
        else if (CNT < B_REG) B = 4'b1111;
        else B = 4'b0000;
    end

endmodule
module HB_FULL_LED (RESETN, CLK, R_IN, G_IN, B_IN, R,G,B);


    input RESETN,CLK;
    input [1:0] R_IN,G_IN,B_IN;
    output [3:0] R,G,B;

    integer CNT;
    integer R_REG, G_REG, B_REG;

    reg[3:0] R, G, B;





    always @(posedge RESETN or posedge CLK) begin
        if(RESETN) R = 4'b0000;
        else if (CNT < R_REG) R = 4'b1111;
        else R = 4'b0000;
    end

    always @(posedge RESETN or posedge CLK) begin
        if(RESETN) G = 4'b0000;
        else if (CNT < G_REG) G = 4'b1111;
        else G = 4'b0000;
    end

    always @(posedge RESETN or posedge CLK) begin
        if(RESETN) B = 4'b0000;
        else if (CNT < B_REG) B = 4'b1111;
        else B = 4'b0000;
    end

endmodule