data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_mips24.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_mips24.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_mips24.v:20: Cannot find file containing module: \'MipsCPU_Top\'\n    MipsCPU_Top MIPS_CPU(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim,data/full_repos/permissive/171720620/MipsCPU_Top\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim,data/full_repos/permissive/171720620/MipsCPU_Top.v\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim,data/full_repos/permissive/171720620/MipsCPU_Top.sv\n             MipsCPU_Top\n             MipsCPU_Top.v\n             MipsCPU_Top.sv\n             obj_dir/MipsCPU_Top\n             obj_dir/MipsCPU_Top.v\n             obj_dir/MipsCPU_Top.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_mips24;
    reg clk, go, rst;
    reg [1:0] select;
    wire [31:0] LedData;

    MipsCPU_Top MIPS_CPU(
        .clk(clk),
        .rst(rst),
        .go(go),
        .select(select),
        .LedData_out(LedData)
    );

    initial begin
        select = 2'b01;
        clk = 0;
        go = 0;
        rst = 0;
    end

    always begin
        #10 clk = ~clk;
    end

endmodule
module test_mips24;

    reg clk, go, rst;
    reg [1:0] select;
    wire [31:0] LedData;

    MipsCPU_Top MIPS_CPU(
        .clk(clk),
        .rst(rst),
        .go(go),
        .select(select),
        .LedData_out(LedData)
    );

    initial begin
        select = 2'b01;
        clk = 0;
        go = 0;
        rst = 0;
    end

    always begin
        #10 clk = ~clk;
    end

endmodule