data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_combiner.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_combiner.v:182: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'one_hot_to_binary\' generates 32 bits.\n                                                                                                                                           : ... In instance ctrlport_combiner\n            slave_sel <= one_hot_to_binary(next_slave_one_hot);\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_combiner.v:185: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'slave_sel\' generates 1 bits.\n                                                                                                                                           : ... In instance ctrlport_combiner\n          else if(slave_sel == NUM_MASTERS-1)\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_combiner.v:199: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'one_hot_to_binary\' generates 32 bits.\n                                                                                                                                           : ... In instance ctrlport_combiner\n            slave_sel <= one_hot_to_binary(next_slave_one_hot);\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_combiner.v:201: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'slave_sel\' generates 1 bits.\n                                                                                                                                           : ... In instance ctrlport_combiner\n          else if (slave_sel == NUM_MASTERS-1)\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_combiner.v:251: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'slave_sel\' generates 1 bits.\n                                                                                                                                           : ... In instance ctrlport_combiner\n        if (i == slave_sel && m_ctrlport_resp_ack) begin\n              ^~\n%Error: Exiting due to 5 warning(s)\n'
module ctrlport_combiner #(
  parameter NUM_MASTERS = 2,
  parameter PRIORITY    = 0
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire [   NUM_MASTERS-1:0] s_ctrlport_req_wr,
  input  wire [   NUM_MASTERS-1:0] s_ctrlport_req_rd,
  input  wire [20*NUM_MASTERS-1:0] s_ctrlport_req_addr,
  input  wire [10*NUM_MASTERS-1:0] s_ctrlport_req_portid,
  input  wire [16*NUM_MASTERS-1:0] s_ctrlport_req_rem_epid,
  input  wire [10*NUM_MASTERS-1:0] s_ctrlport_req_rem_portid,
  input  wire [32*NUM_MASTERS-1:0] s_ctrlport_req_data,
  input  wire [ 4*NUM_MASTERS-1:0] s_ctrlport_req_byte_en,
  input  wire [   NUM_MASTERS-1:0] s_ctrlport_req_has_time,
  input  wire [64*NUM_MASTERS-1:0] s_ctrlport_req_time,

  output reg  [   NUM_MASTERS-1:0] s_ctrlport_resp_ack,
  output reg  [ 2*NUM_MASTERS-1:0] s_ctrlport_resp_status,
  output reg  [32*NUM_MASTERS-1:0] s_ctrlport_resp_data,


  output reg         m_ctrlport_req_wr,
  output reg         m_ctrlport_req_rd,
  output reg  [19:0] m_ctrlport_req_addr,
  output reg  [ 9:0] m_ctrlport_req_portid,
  output reg  [15:0] m_ctrlport_req_rem_epid,
  output reg  [ 9:0] m_ctrlport_req_rem_portid,
  output reg  [31:0] m_ctrlport_req_data,
  output reg  [ 3:0] m_ctrlport_req_byte_en,
  output reg         m_ctrlport_req_has_time,
  output reg  [63:0] m_ctrlport_req_time,

  input  wire        m_ctrlport_resp_ack,
  input  wire [ 1:0] m_ctrlport_resp_status,
  input  wire [31:0] m_ctrlport_resp_data
);

  reg [$clog2(NUM_MASTERS)-1:0] slave_sel = 0;

  reg req_load_output = 1'b0;



  function integer one_hot_to_binary(input [NUM_MASTERS-1:0] one_hot_vec);
    integer i, total;
  begin
    total = 0;
    for (i = 0; i <= NUM_MASTERS-1; i = i + 1) begin
      if (one_hot_vec[i]) begin
        total = total + i;
      end
    end
    one_hot_to_binary = total;
  end
  endfunction










  reg [   NUM_MASTERS-1:0] req_valid = 0;
  reg [   NUM_MASTERS-1:0] req_wr;
  reg [   NUM_MASTERS-1:0] req_rd;
  reg [20*NUM_MASTERS-1:0] req_addr;
  reg [10*NUM_MASTERS-1:0] req_portid;
  reg [16*NUM_MASTERS-1:0] req_rem_epid;
  reg [10*NUM_MASTERS-1:0] req_rem_portid;
  reg [32*NUM_MASTERS-1:0] req_data;
  reg [ 4*NUM_MASTERS-1:0] req_byte_en;
  reg [   NUM_MASTERS-1:0] req_has_time;
  reg [64*NUM_MASTERS-1:0] req_time;

  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      req_valid <= 0;
    end else begin : input_reg_gen
      integer i;
      for (i = 0; i < NUM_MASTERS; i = i + 1) begin
        if (s_ctrlport_req_wr[i] | s_ctrlport_req_rd[i]) begin

          req_valid[i]             <= 1'b1;
          req_wr[i]                <= s_ctrlport_req_wr[i];
          req_rd[i]                <= s_ctrlport_req_rd[i];
          req_addr[20*i+:20]       <= s_ctrlport_req_addr[20*i+:20];
          req_portid[10*i+:10]     <= s_ctrlport_req_portid[10*i+:10];
          req_rem_epid[16*i+:16]   <= s_ctrlport_req_rem_epid[16*i+:16];
          req_rem_portid[10*i+:10] <= s_ctrlport_req_rem_portid[10*i+:10];
          req_data[32*i+:32]       <= s_ctrlport_req_data[32*i+:32];
          req_byte_en[4*i+:4]      <= s_ctrlport_req_byte_en[4*i+:4];
          req_has_time[i]          <= s_ctrlport_req_has_time[i];
          req_time[64*i+:64]       <= s_ctrlport_req_time[64*i+:64];
        end
      end


      if (req_load_output) begin
        req_valid[slave_sel] <= 1'b0;
      end
    end
  end












  reg  req_active = 0;
  wire [NUM_MASTERS-1:0] next_slave_one_hot;


  generate
    genvar i;
    for (i = 0; i < NUM_MASTERS; i = i+1) begin : gen_next_slave_one_hot
      if (i == 0) begin
        assign next_slave_one_hot[i] = req_valid[i];
      end else begin
        assign next_slave_one_hot[i] = req_valid[i] & ~next_slave_one_hot[i-1];
      end
    end
  endgenerate

  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      slave_sel       <= 0;
      req_active      <= 1'b0;
      req_load_output <= 1'b0;
    end else begin
      req_load_output <= 1'b0;

      if (req_active) begin

        if (m_ctrlport_resp_ack) begin
          req_active <= 1'b0;


          if(PRIORITY == 1)
            slave_sel <= one_hot_to_binary(next_slave_one_hot);


          else if(slave_sel == NUM_MASTERS-1)
            slave_sel <= 0;
          else
            slave_sel <= slave_sel + 1;
        end
      end else begin


        if (req_valid[slave_sel]) begin
          req_active      <= 1'b1;
          req_load_output <= 1'b1;
        end else begin

          if(PRIORITY == 1)
            slave_sel <= one_hot_to_binary(next_slave_one_hot);

          else if (slave_sel == NUM_MASTERS-1)
            slave_sel <= 0;
          else
            slave_sel <= slave_sel + 1;
        end
      end
    end
  end











  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      m_ctrlport_req_wr <= 1'b0;
      m_ctrlport_req_rd <= 1'b0;
    end else begin : output_reg_gen
      integer i;


      if (req_load_output) begin
        m_ctrlport_req_wr         <= req_wr        [slave_sel];
        m_ctrlport_req_rd         <= req_rd        [slave_sel];
        m_ctrlport_req_addr       <= req_addr      [20*slave_sel +: 20];
        m_ctrlport_req_portid     <= req_portid    [10*slave_sel +: 10];
        m_ctrlport_req_rem_epid   <= req_rem_epid  [16*slave_sel +: 16];
        m_ctrlport_req_rem_portid <= req_rem_portid[10*slave_sel +: 10];
        m_ctrlport_req_data       <= req_data      [32*slave_sel +: 32];
        m_ctrlport_req_byte_en    <= req_byte_en   [ 4*slave_sel +: 4];
        m_ctrlport_req_has_time   <= req_has_time  [slave_sel];
        m_ctrlport_req_time       <= req_time      [64*slave_sel +: 64];
      end else begin
        m_ctrlport_req_wr <= 1'b0;
        m_ctrlport_req_rd <= 1'b0;
      end


      for (i = 0; i < NUM_MASTERS; i = i + 1) begin

        s_ctrlport_resp_status[2*i +: 2] <= m_ctrlport_resp_status;
        s_ctrlport_resp_data[32*i +: 32] <= m_ctrlport_resp_data;


        if (i == slave_sel && m_ctrlport_resp_ack) begin
          s_ctrlport_resp_ack[i] <= 1'b1;
        end else begin
          s_ctrlport_resp_ack[i] <= 1'b0;
        end
      end
    end
  end

endmodule
module ctrlport_combiner #(
  parameter NUM_MASTERS = 2,
  parameter PRIORITY    = 0
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire [   NUM_MASTERS-1:0] s_ctrlport_req_wr,
  input  wire [   NUM_MASTERS-1:0] s_ctrlport_req_rd,
  input  wire [20*NUM_MASTERS-1:0] s_ctrlport_req_addr,
  input  wire [10*NUM_MASTERS-1:0] s_ctrlport_req_portid,
  input  wire [16*NUM_MASTERS-1:0] s_ctrlport_req_rem_epid,
  input  wire [10*NUM_MASTERS-1:0] s_ctrlport_req_rem_portid,
  input  wire [32*NUM_MASTERS-1:0] s_ctrlport_req_data,
  input  wire [ 4*NUM_MASTERS-1:0] s_ctrlport_req_byte_en,
  input  wire [   NUM_MASTERS-1:0] s_ctrlport_req_has_time,
  input  wire [64*NUM_MASTERS-1:0] s_ctrlport_req_time,

  output reg  [   NUM_MASTERS-1:0] s_ctrlport_resp_ack,
  output reg  [ 2*NUM_MASTERS-1:0] s_ctrlport_resp_status,
  output reg  [32*NUM_MASTERS-1:0] s_ctrlport_resp_data,


  output reg         m_ctrlport_req_wr,
  output reg         m_ctrlport_req_rd,
  output reg  [19:0] m_ctrlport_req_addr,
  output reg  [ 9:0] m_ctrlport_req_portid,
  output reg  [15:0] m_ctrlport_req_rem_epid,
  output reg  [ 9:0] m_ctrlport_req_rem_portid,
  output reg  [31:0] m_ctrlport_req_data,
  output reg  [ 3:0] m_ctrlport_req_byte_en,
  output reg         m_ctrlport_req_has_time,
  output reg  [63:0] m_ctrlport_req_time,

  input  wire        m_ctrlport_resp_ack,
  input  wire [ 1:0] m_ctrlport_resp_status,
  input  wire [31:0] m_ctrlport_resp_data
);


  reg [$clog2(NUM_MASTERS)-1:0] slave_sel = 0;

  reg req_load_output = 1'b0;



  function integer one_hot_to_binary(input [NUM_MASTERS-1:0] one_hot_vec);
    integer i, total;
  begin
    total = 0;
    for (i = 0; i <= NUM_MASTERS-1; i = i + 1) begin
      if (one_hot_vec[i]) begin
        total = total + i;
      end
    end
    one_hot_to_binary = total;
  end
  endfunction










  reg [   NUM_MASTERS-1:0] req_valid = 0;
  reg [   NUM_MASTERS-1:0] req_wr;
  reg [   NUM_MASTERS-1:0] req_rd;
  reg [20*NUM_MASTERS-1:0] req_addr;
  reg [10*NUM_MASTERS-1:0] req_portid;
  reg [16*NUM_MASTERS-1:0] req_rem_epid;
  reg [10*NUM_MASTERS-1:0] req_rem_portid;
  reg [32*NUM_MASTERS-1:0] req_data;
  reg [ 4*NUM_MASTERS-1:0] req_byte_en;
  reg [   NUM_MASTERS-1:0] req_has_time;
  reg [64*NUM_MASTERS-1:0] req_time;

  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      req_valid <= 0;
    end else begin : input_reg_gen
      integer i;
      for (i = 0; i < NUM_MASTERS; i = i + 1) begin
        if (s_ctrlport_req_wr[i] | s_ctrlport_req_rd[i]) begin

          req_valid[i]             <= 1'b1;
          req_wr[i]                <= s_ctrlport_req_wr[i];
          req_rd[i]                <= s_ctrlport_req_rd[i];
          req_addr[20*i+:20]       <= s_ctrlport_req_addr[20*i+:20];
          req_portid[10*i+:10]     <= s_ctrlport_req_portid[10*i+:10];
          req_rem_epid[16*i+:16]   <= s_ctrlport_req_rem_epid[16*i+:16];
          req_rem_portid[10*i+:10] <= s_ctrlport_req_rem_portid[10*i+:10];
          req_data[32*i+:32]       <= s_ctrlport_req_data[32*i+:32];
          req_byte_en[4*i+:4]      <= s_ctrlport_req_byte_en[4*i+:4];
          req_has_time[i]          <= s_ctrlport_req_has_time[i];
          req_time[64*i+:64]       <= s_ctrlport_req_time[64*i+:64];
        end
      end


      if (req_load_output) begin
        req_valid[slave_sel] <= 1'b0;
      end
    end
  end












  reg  req_active = 0;
  wire [NUM_MASTERS-1:0] next_slave_one_hot;


  generate
    genvar i;
    for (i = 0; i < NUM_MASTERS; i = i+1) begin : gen_next_slave_one_hot
      if (i == 0) begin
        assign next_slave_one_hot[i] = req_valid[i];
      end else begin
        assign next_slave_one_hot[i] = req_valid[i] & ~next_slave_one_hot[i-1];
      end
    end
  endgenerate

  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      slave_sel       <= 0;
      req_active      <= 1'b0;
      req_load_output <= 1'b0;
    end else begin
      req_load_output <= 1'b0;

      if (req_active) begin

        if (m_ctrlport_resp_ack) begin
          req_active <= 1'b0;


          if(PRIORITY == 1)
            slave_sel <= one_hot_to_binary(next_slave_one_hot);


          else if(slave_sel == NUM_MASTERS-1)
            slave_sel <= 0;
          else
            slave_sel <= slave_sel + 1;
        end
      end else begin


        if (req_valid[slave_sel]) begin
          req_active      <= 1'b1;
          req_load_output <= 1'b1;
        end else begin

          if(PRIORITY == 1)
            slave_sel <= one_hot_to_binary(next_slave_one_hot);

          else if (slave_sel == NUM_MASTERS-1)
            slave_sel <= 0;
          else
            slave_sel <= slave_sel + 1;
        end
      end
    end
  end











  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      m_ctrlport_req_wr <= 1'b0;
      m_ctrlport_req_rd <= 1'b0;
    end else begin : output_reg_gen
      integer i;


      if (req_load_output) begin
        m_ctrlport_req_wr         <= req_wr        [slave_sel];
        m_ctrlport_req_rd         <= req_rd        [slave_sel];
        m_ctrlport_req_addr       <= req_addr      [20*slave_sel +: 20];
        m_ctrlport_req_portid     <= req_portid    [10*slave_sel +: 10];
        m_ctrlport_req_rem_epid   <= req_rem_epid  [16*slave_sel +: 16];
        m_ctrlport_req_rem_portid <= req_rem_portid[10*slave_sel +: 10];
        m_ctrlport_req_data       <= req_data      [32*slave_sel +: 32];
        m_ctrlport_req_byte_en    <= req_byte_en   [ 4*slave_sel +: 4];
        m_ctrlport_req_has_time   <= req_has_time  [slave_sel];
        m_ctrlport_req_time       <= req_time      [64*slave_sel +: 64];
      end else begin
        m_ctrlport_req_wr <= 1'b0;
        m_ctrlport_req_rd <= 1'b0;
      end


      for (i = 0; i < NUM_MASTERS; i = i + 1) begin

        s_ctrlport_resp_status[2*i +: 2] <= m_ctrlport_resp_status;
        s_ctrlport_resp_data[32*i +: 32] <= m_ctrlport_resp_data;


        if (i == slave_sel && m_ctrlport_resp_ack) begin
          s_ctrlport_resp_ack[i] <= 1'b1;
        end else begin
          s_ctrlport_resp_ack[i] <= 1'b0;
        end
      end
    end
  end

endmodule