data/full_repos/permissive/20759093/CPU_TOP.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/20759093/CPU_TOP.v:241: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'Single_Cycle_CPU\'\nmodule Single_Cycle_CPU(\n       ^~~~~~~~~~~~~~~~\n                                                                    : ... Top module \'mux_2_to_1_5\'\nmodule mux_2_to_1_5(\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/20759093/CPU_TOP.v:496: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                 : ... In instance Single_Cycle_CPU.M4\n            4\'b1001 : result <= (A < B);\n                             ^~\n%Error: data/full_repos/permissive/20759093/CPU_TOP.v:104: Cannot find file containing module: \'RAM_A\'\n    RAM_A M8(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A.v\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A.sv\n             RAM_A\n             RAM_A.v\n             RAM_A.sv\n             obj_dir/RAM_A\n             obj_dir/RAM_A.v\n             obj_dir/RAM_A.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module register_file(
    input clk,
    input [4:0]read_register_1,
    input [4:0]read_register_2,
    input [4:0]write_register,
    input [4:0]debug_input,
    input [31:0]write_data,
    input RegWrite,
    output [31:0]read_data_1,
    output [31:0]read_data_2,
    output [31:0]debug_output
);
    
    reg [31:0]registers[31:0];

    initial begin
        registers[0] = 32'h0;
        registers[1] = 32'h0;
        registers[2] = 32'h0;
        registers[3] = 32'h0;
        registers[4] = 32'h0;
        registers[5] = 32'h0;
        registers[6] = 32'h0;
        registers[7] = 32'h0;
        registers[8] = 32'h0;
        registers[9] = 32'h0;
        registers[10] = 32'h0;
        registers[11] = 32'h0;
        registers[12] = 32'h0;
        registers[13] = 32'h0;
        registers[14] = 32'h0;
        registers[15] = 32'h0;
        registers[16] = 32'h0;
        registers[17] = 32'h0;
        registers[18] = 32'h0;
        registers[19] = 32'h0;
        registers[20] = 32'h0;
        registers[21] = 32'h0;
        registers[22] = 32'h0;
        registers[23] = 32'h0;
        registers[24] = 32'h0;
        registers[25] = 32'h0;
        registers[26] = 32'h0;
        registers[27] = 32'h0;
        registers[28] = 32'h0;
        registers[29] = 32'h0;
        registers[30] = 32'h0;
        registers[31] = 32'h0;    
    end

    assign debug_output = registers[debug_input];
    assign read_data_1 = registers[read_register_1];
    assign read_data_2 = registers[read_register_2];
    
    always @(posedge clk) begin
        if (RegWrite) begin
            registers[write_register] = write_data;
        end
    end
endmodule
module register_file(
    input clk,
    input [4:0]read_register_1,
    input [4:0]read_register_2,
    input [4:0]write_register,
    input [4:0]debug_input,
    input [31:0]write_data,
    input RegWrite,
    output [31:0]read_data_1,
    output [31:0]read_data_2,
    output [31:0]debug_output
);

    
    reg [31:0]registers[31:0];

    initial begin
        registers[0] = 32'h0;
        registers[1] = 32'h0;
        registers[2] = 32'h0;
        registers[3] = 32'h0;
        registers[4] = 32'h0;
        registers[5] = 32'h0;
        registers[6] = 32'h0;
        registers[7] = 32'h0;
        registers[8] = 32'h0;
        registers[9] = 32'h0;
        registers[10] = 32'h0;
        registers[11] = 32'h0;
        registers[12] = 32'h0;
        registers[13] = 32'h0;
        registers[14] = 32'h0;
        registers[15] = 32'h0;
        registers[16] = 32'h0;
        registers[17] = 32'h0;
        registers[18] = 32'h0;
        registers[19] = 32'h0;
        registers[20] = 32'h0;
        registers[21] = 32'h0;
        registers[22] = 32'h0;
        registers[23] = 32'h0;
        registers[24] = 32'h0;
        registers[25] = 32'h0;
        registers[26] = 32'h0;
        registers[27] = 32'h0;
        registers[28] = 32'h0;
        registers[29] = 32'h0;
        registers[30] = 32'h0;
        registers[31] = 32'h0;    
    end

    assign debug_output = registers[debug_input];
    assign read_data_1 = registers[read_register_1];
    assign read_data_2 = registers[read_register_2];
    
    always @(posedge clk) begin
        if (RegWrite) begin
            registers[write_register] = write_data;
        end
    end
endmodule