data/full_repos/permissive/183345139/hba_qtr/hba_qtr.v
1: b'%Error: data/full_repos/permissive/183345139/hba_qtr/hba_qtr.v:140: Cannot find file containing module: \'hba_reg_bank\'\nhba_reg_bank #\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/183345139/hba_qtr,data/full_repos/permissive/183345139/hba_reg_bank\n             data/full_repos/permissive/183345139/hba_qtr,data/full_repos/permissive/183345139/hba_reg_bank.v\n             data/full_repos/permissive/183345139/hba_qtr,data/full_repos/permissive/183345139/hba_reg_bank.sv\n             hba_reg_bank\n             hba_reg_bank.v\n             hba_reg_bank.sv\n             obj_dir/hba_reg_bank\n             obj_dir/hba_reg_bank.v\n             obj_dir/hba_reg_bank.sv\n%Error: data/full_repos/permissive/183345139/hba_qtr/hba_qtr.v:176: Cannot find file containing module: \'hba_reg_bank\'\nhba_reg_bank #\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/183345139/hba_qtr/hba_qtr.v:214: Cannot find file containing module: \'qtr\'\nqtr #\n^~~\n%Error: data/full_repos/permissive/183345139/hba_qtr/hba_qtr.v:235: Cannot find file containing module: \'qtr\'\nqtr #\n^~~\n%Warning-WIDTH: data/full_repos/permissive/183345139/hba_qtr/hba_qtr.v:275: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'count_50ms\' generates 23 bits.\n                                                                          : ... In instance hba_qtr\n        if (count_50ms == (FIFTY_MS_COUNT-1)) begin\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module hba_qtr #
(



    parameter integer CLK_FREQUENCY = 60_000_000,
    parameter integer DBUS_WIDTH = 8,
    parameter integer PERIPH_ADDR_WIDTH = 4,
    parameter integer REG_ADDR_WIDTH = 8,
    parameter integer ADDR_WIDTH = PERIPH_ADDR_WIDTH + REG_ADDR_WIDTH,
    parameter integer PERIPH_ADDR = 0
)
(

    input wire hba_clk,
    input wire hba_reset,
    input wire hba_rnw,
    input wire hba_select,
    input wire [ADDR_WIDTH-1:0] hba_abus,
    input wire [DBUS_WIDTH-1:0] hba_dbus,

    output wire [DBUS_WIDTH-1:0] hba_dbus_slave,
    output wire hba_xferack_slave,


    output reg slave_interrupt,
    output reg slave_estop,


    output wire [1:0]  qtr_out_en,
    output wire [1:0] qtr_out_sig,
    input wire [1:0] qtr_in_sig,
    output wire [1:0] qtr_ctrl
);




wire [DBUS_WIDTH-1:0] reg_ctrl;

wire [DBUS_WIDTH-1:0] reg_qtr0_in;
wire [DBUS_WIDTH-1:0] reg_qtr1_in;

wire [DBUS_WIDTH-1:0] reg_period;

wire [DBUS_WIDTH-1:0] reg_thresh;


wire slv_wr_en;


wire [1:0] qtr_valid;


reg qtr_sync;


wire intr_en = reg_ctrl[1];

assign slv_wr_en = |qtr_valid;

wire qtr_en;
assign qtr_en = reg_ctrl[0] & qtr_sync;


localparam INTR_TYPE_PERIOD = 0;
localparam INTR_TYPE_THRESH = 1;
wire intr_type = reg_ctrl[2];


wire estop_en = reg_ctrl[3] && (intr_type==INTR_TYPE_THRESH);


wire [DBUS_WIDTH-1:0] hba_dbus_slave0;
wire [DBUS_WIDTH-1:0] hba_dbus_slave1;
wire hba_xferack_slave0;
wire hba_xferack_slave1;

assign hba_dbus_slave = hba_dbus_slave0 | hba_dbus_slave1;
assign hba_xferack_slave = hba_xferack_slave0 | hba_xferack_slave1;



hba_reg_bank #
(
    .DBUS_WIDTH(DBUS_WIDTH),
    .PERIPH_ADDR_WIDTH(PERIPH_ADDR_WIDTH),
    .REG_ADDR_WIDTH(REG_ADDR_WIDTH),
    .PERIPH_ADDR(PERIPH_ADDR)
) hba_reg_bank_inst0
(

    .hba_clk(hba_clk),
    .hba_reset(hba_reset),
    .hba_rnw(hba_rnw),
    .hba_select(hba_select),
    .hba_abus(hba_abus),
    .hba_dbus(hba_dbus),

    .hba_dbus_slave(hba_dbus_slave0),
    .hba_xferack_slave(hba_xferack_slave0),




    .slv_reg0(reg_ctrl),


    .slv_reg3(reg_period),


    .slv_reg1_in(reg_qtr0_in),
    .slv_reg2_in(reg_qtr1_in),

    .slv_wr_en(slv_wr_en),
    .slv_wr_mask(4'b0110),
    .slv_autoclr_mask(4'b0000)
);

hba_reg_bank #
(
    .DBUS_WIDTH(DBUS_WIDTH),
    .PERIPH_ADDR_WIDTH(PERIPH_ADDR_WIDTH),
    .REG_ADDR_WIDTH(REG_ADDR_WIDTH),
    .PERIPH_ADDR(PERIPH_ADDR),
    .REG_OFFSET(4)
) hba_reg_bank_inst1
(

    .hba_clk(hba_clk),
    .hba_reset(hba_reset),
    .hba_rnw(hba_rnw),
    .hba_select(hba_select),
    .hba_abus(hba_abus),
    .hba_dbus(hba_dbus),

    .hba_dbus_slave(hba_dbus_slave1),
    .hba_xferack_slave(hba_xferack_slave1),




    .slv_reg0(reg_thresh),








    .slv_wr_en(1'b0),
    .slv_wr_mask(4'b0000),
    .slv_autoclr_mask(4'b0000)
);


qtr #
(
    .CLK_FREQUENCY(CLK_FREQUENCY)
) qtr_inst0
(
    .clk(hba_clk),
    .reset(hba_reset),
    .en(qtr_en),

    .value(reg_qtr0_in),
    .valid(qtr_valid[0]),


    .qtr_out_en(qtr_out_en[0]),
    .qtr_out_sig(qtr_out_sig[0]),
    .qtr_in_sig(qtr_in_sig[0]),
    .qtr_ctrl(qtr_ctrl[0])

);


qtr #
(
    .CLK_FREQUENCY(CLK_FREQUENCY)
) qtr_inst1
(
    .clk(hba_clk),
    .reset(hba_reset),
    .en(qtr_en),

    .value(reg_qtr1_in),
    .valid(qtr_valid[1]),


    .qtr_out_en(qtr_out_en[1]),
    .qtr_out_sig(qtr_out_sig[1]),
    .qtr_in_sig(qtr_in_sig[1]),
    .qtr_ctrl(qtr_ctrl[1])

);





reg [22:0] count_50ms;
reg [7:0] count_period;
localparam FIFTY_MS_COUNT = ( CLK_FREQUENCY / 20 );
always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        qtr_sync <= 0;
        count_50ms <= 0;
        count_period <= 0;
    end else begin
        qtr_sync <= 0;
        count_50ms <= count_50ms + 1;
        if (count_50ms == (FIFTY_MS_COUNT-1)) begin
            count_50ms <= 0;
            count_period <= count_period + 1;
            if (count_period == reg_period) begin
                count_period <= 0;
                qtr_sync <= 1;
            end
        end
    end
end


reg thresh_side0;
reg thresh_side1;
wire thresh_comp0 = (reg_qtr0_in > reg_thresh) ? 1 : 0;
wire thresh_comp1 = (reg_qtr1_in > reg_thresh) ? 1 : 0;
always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        slave_interrupt <= 0;
        thresh_side0 <= 0;
        thresh_side1 <= 0;
    end else begin
        slave_interrupt <= 0;
        if ((slv_wr_en==1) && (intr_en==1)) begin
            if (intr_type == INTR_TYPE_PERIOD) begin
                slave_interrupt <= 1;
            end else begin

                thresh_side0 <= thresh_comp0;
                thresh_side1 <= thresh_comp1;
                if ( (thresh_side0 != thresh_comp0)  || 
                     (thresh_side1 != thresh_comp1) ) begin
                    slave_interrupt <= 1;
                end
            end
        end
    end
end


always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        slave_estop <= 0;
    end else begin
        slave_estop <= 0;
        if (estop_en && (reg_qtr0_in==8'hff || reg_qtr1_in==8'hff)) begin
            slave_estop <= 1;
        end
    end
end

endmodule
module hba_qtr #
(



    parameter integer CLK_FREQUENCY = 60_000_000,
    parameter integer DBUS_WIDTH = 8,
    parameter integer PERIPH_ADDR_WIDTH = 4,
    parameter integer REG_ADDR_WIDTH = 8,
    parameter integer ADDR_WIDTH = PERIPH_ADDR_WIDTH + REG_ADDR_WIDTH,
    parameter integer PERIPH_ADDR = 0
)
(

    input wire hba_clk,
    input wire hba_reset,
    input wire hba_rnw,
    input wire hba_select,
    input wire [ADDR_WIDTH-1:0] hba_abus,
    input wire [DBUS_WIDTH-1:0] hba_dbus,

    output wire [DBUS_WIDTH-1:0] hba_dbus_slave,
    output wire hba_xferack_slave,


    output reg slave_interrupt,
    output reg slave_estop,


    output wire [1:0]  qtr_out_en,
    output wire [1:0] qtr_out_sig,
    input wire [1:0] qtr_in_sig,
    output wire [1:0] qtr_ctrl
);





wire [DBUS_WIDTH-1:0] reg_ctrl;

wire [DBUS_WIDTH-1:0] reg_qtr0_in;
wire [DBUS_WIDTH-1:0] reg_qtr1_in;

wire [DBUS_WIDTH-1:0] reg_period;

wire [DBUS_WIDTH-1:0] reg_thresh;


wire slv_wr_en;


wire [1:0] qtr_valid;


reg qtr_sync;


wire intr_en = reg_ctrl[1];

assign slv_wr_en = |qtr_valid;

wire qtr_en;
assign qtr_en = reg_ctrl[0] & qtr_sync;


localparam INTR_TYPE_PERIOD = 0;
localparam INTR_TYPE_THRESH = 1;
wire intr_type = reg_ctrl[2];


wire estop_en = reg_ctrl[3] && (intr_type==INTR_TYPE_THRESH);


wire [DBUS_WIDTH-1:0] hba_dbus_slave0;
wire [DBUS_WIDTH-1:0] hba_dbus_slave1;
wire hba_xferack_slave0;
wire hba_xferack_slave1;

assign hba_dbus_slave = hba_dbus_slave0 | hba_dbus_slave1;
assign hba_xferack_slave = hba_xferack_slave0 | hba_xferack_slave1;



hba_reg_bank #
(
    .DBUS_WIDTH(DBUS_WIDTH),
    .PERIPH_ADDR_WIDTH(PERIPH_ADDR_WIDTH),
    .REG_ADDR_WIDTH(REG_ADDR_WIDTH),
    .PERIPH_ADDR(PERIPH_ADDR)
) hba_reg_bank_inst0
(

    .hba_clk(hba_clk),
    .hba_reset(hba_reset),
    .hba_rnw(hba_rnw),
    .hba_select(hba_select),
    .hba_abus(hba_abus),
    .hba_dbus(hba_dbus),

    .hba_dbus_slave(hba_dbus_slave0),
    .hba_xferack_slave(hba_xferack_slave0),




    .slv_reg0(reg_ctrl),


    .slv_reg3(reg_period),


    .slv_reg1_in(reg_qtr0_in),
    .slv_reg2_in(reg_qtr1_in),

    .slv_wr_en(slv_wr_en),
    .slv_wr_mask(4'b0110),
    .slv_autoclr_mask(4'b0000)
);

hba_reg_bank #
(
    .DBUS_WIDTH(DBUS_WIDTH),
    .PERIPH_ADDR_WIDTH(PERIPH_ADDR_WIDTH),
    .REG_ADDR_WIDTH(REG_ADDR_WIDTH),
    .PERIPH_ADDR(PERIPH_ADDR),
    .REG_OFFSET(4)
) hba_reg_bank_inst1
(

    .hba_clk(hba_clk),
    .hba_reset(hba_reset),
    .hba_rnw(hba_rnw),
    .hba_select(hba_select),
    .hba_abus(hba_abus),
    .hba_dbus(hba_dbus),

    .hba_dbus_slave(hba_dbus_slave1),
    .hba_xferack_slave(hba_xferack_slave1),




    .slv_reg0(reg_thresh),








    .slv_wr_en(1'b0),
    .slv_wr_mask(4'b0000),
    .slv_autoclr_mask(4'b0000)
);


qtr #
(
    .CLK_FREQUENCY(CLK_FREQUENCY)
) qtr_inst0
(
    .clk(hba_clk),
    .reset(hba_reset),
    .en(qtr_en),

    .value(reg_qtr0_in),
    .valid(qtr_valid[0]),


    .qtr_out_en(qtr_out_en[0]),
    .qtr_out_sig(qtr_out_sig[0]),
    .qtr_in_sig(qtr_in_sig[0]),
    .qtr_ctrl(qtr_ctrl[0])

);


qtr #
(
    .CLK_FREQUENCY(CLK_FREQUENCY)
) qtr_inst1
(
    .clk(hba_clk),
    .reset(hba_reset),
    .en(qtr_en),

    .value(reg_qtr1_in),
    .valid(qtr_valid[1]),


    .qtr_out_en(qtr_out_en[1]),
    .qtr_out_sig(qtr_out_sig[1]),
    .qtr_in_sig(qtr_in_sig[1]),
    .qtr_ctrl(qtr_ctrl[1])

);





reg [22:0] count_50ms;
reg [7:0] count_period;
localparam FIFTY_MS_COUNT = ( CLK_FREQUENCY / 20 );
always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        qtr_sync <= 0;
        count_50ms <= 0;
        count_period <= 0;
    end else begin
        qtr_sync <= 0;
        count_50ms <= count_50ms + 1;
        if (count_50ms == (FIFTY_MS_COUNT-1)) begin
            count_50ms <= 0;
            count_period <= count_period + 1;
            if (count_period == reg_period) begin
                count_period <= 0;
                qtr_sync <= 1;
            end
        end
    end
end


reg thresh_side0;
reg thresh_side1;
wire thresh_comp0 = (reg_qtr0_in > reg_thresh) ? 1 : 0;
wire thresh_comp1 = (reg_qtr1_in > reg_thresh) ? 1 : 0;
always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        slave_interrupt <= 0;
        thresh_side0 <= 0;
        thresh_side1 <= 0;
    end else begin
        slave_interrupt <= 0;
        if ((slv_wr_en==1) && (intr_en==1)) begin
            if (intr_type == INTR_TYPE_PERIOD) begin
                slave_interrupt <= 1;
            end else begin

                thresh_side0 <= thresh_comp0;
                thresh_side1 <= thresh_comp1;
                if ( (thresh_side0 != thresh_comp0)  || 
                     (thresh_side1 != thresh_comp1) ) begin
                    slave_interrupt <= 1;
                end
            end
        end
    end
end


always @ (posedge hba_clk)
begin
    if (hba_reset) begin
        slave_estop <= 0;
    end else begin
        slave_estop <= 0;
        if (estop_en && (reg_qtr0_in==8'hff || reg_qtr1_in==8'hff)) begin
            slave_estop <= 1;
        end
    end
end

endmodule