data/full_repos/permissive/183345139/verilog_tutorial/7_Latches/latch3.v
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data/verilator_xmls/3507f019-c245-4a8a-ba79-4221e3075a2b.xml
module latch3
(
    input wire clk_16mhz,
    input wire button0,
    input wire button1,
    output reg led
);

always @ (posedge clk_16mhz)
begin
    if (button0) begin
        led <= button1;
    end
end

endmodule
module latch3
(
    input wire clk_16mhz,
    input wire button0,
    input wire button1,
    output reg led
);


always @ (posedge clk_16mhz)
begin
    if (button0) begin
        led <= button1;
    end
end

endmodule