data/full_repos/permissive/143278/ivltests/pr224.v
 line:25: before: "("
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr224.v:11: syntax error, unexpected \'@\'\n         @(posedge clk); $display("got posedge clk");\n         ^\n%Error: data/full_repos/permissive/143278/ivltests/pr224.v:17: syntax error, unexpected \'@\'\n         @(posedge ack); $display("got posedge ack");\n         ^\n%Error: data/full_repos/permissive/143278/ivltests/pr224.v:19: syntax error, unexpected \'@\'\n         @(posedge clk); $display("got posedge clk");\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr224.v:25: Unsupported: Ignoring delay on this delayed statement.\n   initial #5 first(1);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr224.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10 clk <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr224.v:31: Unsupported: Ignoring delay on this delayed statement.\n #10 ack <= 3; clk <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr224.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10 clk <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr224.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10 $display("FAILED");\n ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module test;

   reg        clk;
   reg [3:0]  ack;

   task first;
      input [1:0]  p;
      begin
         @(posedge clk); $display("got posedge clk");
`ifdef LINE_A

	 @(posedge ack[p]); $display("got posedge ack[p]");
`else

         @(posedge ack); $display("got posedge ack");
`endif
         @(posedge clk); $display("got posedge clk");
	 $display("PASSED");
	 $finish;
      end
   endtask

   initial #5 first(1);

   initial
     begin
	ack <= 0; clk <= 0;
	#10 clk <= 1;
	#10 ack <= 3; clk <= 0;
	#10 clk <= 1;
	#10 $display("FAILED");
	$finish;
     end

endmodule
module test;


   reg        clk;
   reg [3:0]  ack;

   task first;
      input [1:0]  p;
      begin
         @(posedge clk); $display("got posedge clk");
`ifdef LINE_A

	 @(posedge ack[p]); $display("got posedge ack[p]");
`else

         @(posedge ack); $display("got posedge ack");
`endif
         @(posedge clk); $display("got posedge clk");
	 $display("PASSED");
	 $finish;
      end
   endtask

   initial #5 first(1);

   initial
     begin
	ack <= 0; clk <= 0;
	#10 clk <= 1;
	#10 ack <= 3; clk <= 0;
	#10 clk <= 1;
	#10 $display("FAILED");
	$finish;
     end

endmodule