data/full_repos/permissive/169258653/multicycle/MIPS_multi_cycle_32bit/MIPS_multi_cycle_32bit.srcs/sources_1/new/sl2.v
data/verilator_xmls/8336d042-0928-4637-b4a0-2c47c2b29372.xml
module sl2(
    input [29:0] in,
    output [31:0] out
    );
    

    assign out={in, 2'b00};
    
endmodule
module sl2(
    input [29:0] in,
    output [31:0] out
    );

    

    assign out={in, 2'b00};
    
endmodule