data/full_repos/permissive/109846502/reg.v
data/verilator_xmls/58bfc0ef-8b53-490d-adc7-93cede6791aa.xml
module red(  input clk, input rst, input en,
					output out
    );
reg[1:0] tmp;

always @(posedge clk, posedge rst)
begin
	if(rst)
		tmp <= 2'b0;
	else begin
		tmp[0] <= en;
		tmp[1] <= tmp[0];
	end
end

assign out = tmp[0] && ~tmp[1];

endmodule
module red(  input clk, input rst, input en,
					output out
    );

reg[1:0] tmp;

always @(posedge clk, posedge rst)
begin
	if(rst)
		tmp <= 2'b0;
	else begin
		tmp[0] <= en;
		tmp[1] <= tmp[0];
	end
end

assign out = tmp[0] && ~tmp[1];

endmodule