data/full_repos/permissive/104443190/chen_div.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:14: Unsupported: Ignoring delay on this delayed statement.\n initial #30 rst=1;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104443190/chen_div.v:15: Unsupported: Ignoring delay on this delayed statement.\n always#10 clk=~clk;\n       ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module chen_signed_div ( clk,rst_n,divide_en,dividend,divisor,divide_error,divide_done,quotient );

	parameter width = 16;   

	input clk;
	input rst_n;
	input divide_en;
	input[15:0] dividend;   
	input[15:0] divisor;  
	
	output reg divide_error;
	output reg divide_done;
	output reg [31:0] quotient;

	reg divide_en_temp;
	reg divide_sign_temp;
	reg [31:0] divide_dividend_temp;
	reg [31:0]divide_divisor_temp;

	reg [33:0] divide_sign_temp_shift_reg;

	wire divide_error_temp;
	wire divide_done_temp;
	wire [31:0] quotient_temp;

	always@(posedge clk)
	if(~rst_n)
		begin
			divide_en_temp <= 0;
			divide_sign_temp <= 0;
			divide_dividend_temp <= 0;
			divide_divisor_temp <= 0;
			divide_sign_temp_shift_reg <= 0;
			divide_done <= 0;
			divide_error <= 0;
			quotient <= 0;
		end
	else 
		begin
			divide_en_temp <= divide_en;
			divide_sign_temp <= dividend[15]^divisor[15];
			divide_dividend_temp <= { abs(dividend),16'sb0 };
			divide_divisor_temp <= { 16'sb0,abs(divisor) };

			divide_sign_temp_shift_reg <= {divide_sign_temp_shift_reg[32:0],divide_sign_temp};

			divide_done <= divide_done_temp;
			divide_error <= divide_error_temp;
			quotient <= divide_done_temp?unsignedtosigned(quotient_temp,divide_sign_temp_shift_reg[33]):0;
		end


	chen_unsigned_div#(
		.width (32) 
		) inst_chen_unsigned_div( 
		.clk(clk),
		.rst_n(rst_n),
		.divide_en(divide_en_temp),
		.dividend(divide_dividend_temp),
		.divisor(divide_divisor_temp),
		.divide_error(divide_error_temp),
		.divide_done(divide_done_temp),
		.quotient(quotient_temp),
		.remainde() 
		); 


	function [15:0] abs; 
	   input [15:0] x;  
	   begin
	   		abs = x[15]?~x+1'b1:x;
	   end
	endfunction

	function [31:0] unsignedtosigned; 
	   input [31:0] x;
	   input sign;  
	   begin
	   		unsignedtosigned = sign?~x+1'b1:x;
	   end
	endfunction

endmodule
module chen_signed_div ( clk,rst_n,divide_en,dividend,divisor,divide_error,divide_done,quotient );


	parameter width = 16;   

	input clk;
	input rst_n;
	input divide_en;
	input[15:0] dividend;   
	input[15:0] divisor;  
	
	output reg divide_error;
	output reg divide_done;
	output reg [31:0] quotient;

	reg divide_en_temp;
	reg divide_sign_temp;
	reg [31:0] divide_dividend_temp;
	reg [31:0]divide_divisor_temp;

	reg [33:0] divide_sign_temp_shift_reg;

	wire divide_error_temp;
	wire divide_done_temp;
	wire [31:0] quotient_temp;

	always@(posedge clk)
	if(~rst_n)
		begin
			divide_en_temp <= 0;
			divide_sign_temp <= 0;
			divide_dividend_temp <= 0;
			divide_divisor_temp <= 0;
			divide_sign_temp_shift_reg <= 0;
			divide_done <= 0;
			divide_error <= 0;
			quotient <= 0;
		end
	else 
		begin
			divide_en_temp <= divide_en;
			divide_sign_temp <= dividend[15]^divisor[15];
			divide_dividend_temp <= { abs(dividend),16'sb0 };
			divide_divisor_temp <= { 16'sb0,abs(divisor) };

			divide_sign_temp_shift_reg <= {divide_sign_temp_shift_reg[32:0],divide_sign_temp};

			divide_done <= divide_done_temp;
			divide_error <= divide_error_temp;
			quotient <= divide_done_temp?unsignedtosigned(quotient_temp,divide_sign_temp_shift_reg[33]):0;
		end


	chen_unsigned_div#(
		.width (32) 
		) inst_chen_unsigned_div( 
		.clk(clk),
		.rst_n(rst_n),
		.divide_en(divide_en_temp),
		.dividend(divide_dividend_temp),
		.divisor(divide_divisor_temp),
		.divide_error(divide_error_temp),
		.divide_done(divide_done_temp),
		.quotient(quotient_temp),
		.remainde() 
		); 


	function [15:0] abs; 
	   input [15:0] x;  
	   begin
	   		abs = x[15]?~x+1'b1:x;
	   end
	endfunction

	function [31:0] unsignedtosigned; 
	   input [31:0] x;
	   input sign;  
	   begin
	   		unsignedtosigned = sign?~x+1'b1:x;
	   end
	endfunction

endmodule