data/full_repos/permissive/2084115/rtl/bus/jelly2_wishbone_ff.sv
 line:16: before: "WB_ADR_WIDTH"
data/verilator_xmls/0004e822-bc6b-41dc-bf9d-f84dde1e7356.xml
module jelly2_wishbone_ff
        #(
            parameter   int     WB_ADR_WIDTH  = 30,
            parameter   int     WB_DAT_WIDTH  = 32,
            parameter   int     WB_SEL_WIDTH  = (WB_DAT_WIDTH / 8),
            parameter   bit     SREG          = 0,
            parameter   bit     MREG          = 0
        )
        (
            input   wire                        reset,
            input   wire                        clk,
            input   wire                        cke,
            
            input   wire    [WB_ADR_WIDTH-1:0]  s_wb_adr_i,
            output  reg     [WB_DAT_WIDTH-1:0]  s_wb_dat_o,
            input   wire    [WB_DAT_WIDTH-1:0]  s_wb_dat_i,
            input   wire    [WB_SEL_WIDTH-1:0]  s_wb_sel_i,
            input   wire                        s_wb_we_i,
            input   wire                        s_wb_stb_i,
            output  wire                        s_wb_ack_o,
            
            output  reg     [WB_ADR_WIDTH-1:0]  m_wb_adr_o,
            input   wire    [WB_DAT_WIDTH-1:0]  m_wb_dat_i,
            output  reg     [WB_DAT_WIDTH-1:0]  m_wb_dat_o,
            output  reg     [WB_SEL_WIDTH-1:0]  m_wb_sel_o,
            output  reg                         m_wb_we_o,
            output  reg                         m_wb_stb_o,
            input   wire                        m_wb_ack_i
        );
    

    logic   [WB_ADR_WIDTH-1:0]  wb_tmp_adr_o;
    logic   [WB_DAT_WIDTH-1:0]  wb_tmp_dat_i;
    logic   [WB_DAT_WIDTH-1:0]  wb_tmp_dat_o;
    logic   [WB_SEL_WIDTH-1:0]  wb_tmp_sel_o;
    logic                       wb_tmp_we_o;
    logic                       wb_tmp_stb_o;
    logic                       wb_tmp_ack_i;
    

    generate
    if ( SREG ) begin : s_ff

        always_ff @( posedge clk ) begin
            if ( reset ) begin
                s_wb_dat_o <= 'x;
                s_wb_ack_o <= 1'b0;
            end
            else if ( cke ) begin
                s_wb_dat_o <= wb_tmp_dat_i;
                s_wb_ack_o <= wb_tmp_stb_o & wb_tmp_ack_i;
            end
        end
        
        always_comb wb_tmp_adr_o = s_wb_adr_i;
        always_comb wb_tmp_dat_o = s_wb_dat_i;
        always_comb wb_tmp_sel_o = s_wb_sel_i;
        always_comb wb_tmp_we_o  = s_wb_we_i;
        always_comb wb_tmp_stb_o = s_wb_stb_i & !s_wb_ack_o;
    end
    else begin : s_bypass

        always_comb s_wb_dat_o   = wb_tmp_dat_i;
        always_comb s_wb_ack_o   = wb_tmp_ack_i;

        always_comb wb_tmp_adr_o = s_wb_adr_i;
        always_comb wb_tmp_dat_o = s_wb_dat_i;
        always_comb wb_tmp_sel_o = s_wb_sel_i;
        always_comb wb_tmp_we_o  = s_wb_we_i;
        always_comb wb_tmp_stb_o = s_wb_stb_i;
        
    end
    endgenerate
    
    

    generate
    if ( MREG ) begin

        always_ff @ ( posedge clk ) begin
            if ( reset ) begin
                m_wb_adr_o <= 'x;
                m_wb_dat_o <= 'x;
                m_wb_sel_o <= 'x;
                m_wb_we_o  <= 1'bx;
                m_wb_stb_o <= 1'b0;
            end
            else if ( cke ) begin
                m_wb_adr_o <= wb_tmp_adr_o;
                m_wb_dat_o <= wb_tmp_dat_o;
                m_wb_sel_o <= wb_tmp_sel_o;
                m_wb_we_o  <= wb_tmp_we_o;
                m_wb_stb_o <= wb_tmp_stb_o & !(m_wb_stb_o & wb_tmp_ack_i);
            end
        end
        
        always_comb wb_tmp_dat_i = m_wb_dat_i;
        always_comb wb_tmp_ack_i = m_wb_ack_i;
    end
    else begin

        always_comb m_wb_adr_o   = wb_tmp_adr_o;
        always_comb m_wb_dat_o   = wb_tmp_dat_o;
        always_comb m_wb_sel_o   = wb_tmp_sel_o;
        always_comb m_wb_we_o    = wb_tmp_we_o;
        always_comb m_wb_stb_o   = wb_tmp_stb_o;
                      
        always_comb wb_tmp_dat_i = m_wb_dat_i;
        always_comb wb_tmp_ack_i = m_wb_ack_i;
    end
    endgenerate

endmodule
module jelly2_wishbone_ff
        #(
            parameter   int     WB_ADR_WIDTH  = 30,
            parameter   int     WB_DAT_WIDTH  = 32,
            parameter   int     WB_SEL_WIDTH  = (WB_DAT_WIDTH / 8),
            parameter   bit     SREG          = 0,
            parameter   bit     MREG          = 0
        )
        (
            input   wire                        reset,
            input   wire                        clk,
            input   wire                        cke,
            
            input   wire    [WB_ADR_WIDTH-1:0]  s_wb_adr_i,
            output  reg     [WB_DAT_WIDTH-1:0]  s_wb_dat_o,
            input   wire    [WB_DAT_WIDTH-1:0]  s_wb_dat_i,
            input   wire    [WB_SEL_WIDTH-1:0]  s_wb_sel_i,
            input   wire                        s_wb_we_i,
            input   wire                        s_wb_stb_i,
            output  wire                        s_wb_ack_o,
            
            output  reg     [WB_ADR_WIDTH-1:0]  m_wb_adr_o,
            input   wire    [WB_DAT_WIDTH-1:0]  m_wb_dat_i,
            output  reg     [WB_DAT_WIDTH-1:0]  m_wb_dat_o,
            output  reg     [WB_SEL_WIDTH-1:0]  m_wb_sel_o,
            output  reg                         m_wb_we_o,
            output  reg                         m_wb_stb_o,
            input   wire                        m_wb_ack_i
        );

    

    logic   [WB_ADR_WIDTH-1:0]  wb_tmp_adr_o;
    logic   [WB_DAT_WIDTH-1:0]  wb_tmp_dat_i;
    logic   [WB_DAT_WIDTH-1:0]  wb_tmp_dat_o;
    logic   [WB_SEL_WIDTH-1:0]  wb_tmp_sel_o;
    logic                       wb_tmp_we_o;
    logic                       wb_tmp_stb_o;
    logic                       wb_tmp_ack_i;
    

    generate
    if ( SREG ) begin : s_ff

        always_ff @( posedge clk ) begin
            if ( reset ) begin
                s_wb_dat_o <= 'x;
                s_wb_ack_o <= 1'b0;
            end
            else if ( cke ) begin
                s_wb_dat_o <= wb_tmp_dat_i;
                s_wb_ack_o <= wb_tmp_stb_o & wb_tmp_ack_i;
            end
        end
        
        always_comb wb_tmp_adr_o = s_wb_adr_i;
        always_comb wb_tmp_dat_o = s_wb_dat_i;
        always_comb wb_tmp_sel_o = s_wb_sel_i;
        always_comb wb_tmp_we_o  = s_wb_we_i;
        always_comb wb_tmp_stb_o = s_wb_stb_i & !s_wb_ack_o;
    end
    else begin : s_bypass

        always_comb s_wb_dat_o   = wb_tmp_dat_i;
        always_comb s_wb_ack_o   = wb_tmp_ack_i;

        always_comb wb_tmp_adr_o = s_wb_adr_i;
        always_comb wb_tmp_dat_o = s_wb_dat_i;
        always_comb wb_tmp_sel_o = s_wb_sel_i;
        always_comb wb_tmp_we_o  = s_wb_we_i;
        always_comb wb_tmp_stb_o = s_wb_stb_i;
        
    end
    endgenerate
    
    

    generate
    if ( MREG ) begin

        always_ff @ ( posedge clk ) begin
            if ( reset ) begin
                m_wb_adr_o <= 'x;
                m_wb_dat_o <= 'x;
                m_wb_sel_o <= 'x;
                m_wb_we_o  <= 1'bx;
                m_wb_stb_o <= 1'b0;
            end
            else if ( cke ) begin
                m_wb_adr_o <= wb_tmp_adr_o;
                m_wb_dat_o <= wb_tmp_dat_o;
                m_wb_sel_o <= wb_tmp_sel_o;
                m_wb_we_o  <= wb_tmp_we_o;
                m_wb_stb_o <= wb_tmp_stb_o & !(m_wb_stb_o & wb_tmp_ack_i);
            end
        end
        
        always_comb wb_tmp_dat_i = m_wb_dat_i;
        always_comb wb_tmp_ack_i = m_wb_ack_i;
    end
    else begin

        always_comb m_wb_adr_o   = wb_tmp_adr_o;
        always_comb m_wb_dat_o   = wb_tmp_dat_o;
        always_comb m_wb_sel_o   = wb_tmp_sel_o;
        always_comb m_wb_we_o    = wb_tmp_we_o;
        always_comb m_wb_stb_o   = wb_tmp_stb_o;
                      
        always_comb wb_tmp_dat_i = m_wb_dat_i;
        always_comb wb_tmp_ack_i = m_wb_ack_i;
    end
    endgenerate

endmodule