data/full_repos/permissive/113839829/Source/CPU/mem_sim.v
'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte
1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/mem_sim.v:5: Cannot find include file: defines.v\n `include "defines.v" \n          ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/mem_sim.v:28: Define or directive not defined: \'`InstBus\'\n   reg [`InstBus]    mem_data[0:`MemNumber];\n        ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/mem_sim.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   reg [`InstBus]    mem_data[0:`MemNumber];\n                ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/mem_sim.v:28: Define or directive not defined: \'`MemNumber\'\n   reg [`InstBus]    mem_data[0:`MemNumber];\n                                ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module mem_sim
  (
   input wire 	     clk,
     
   input wire 	     if_ms_req_i,
   input wire [31:0] if_addr,

   input wire 	     mem_ms_req_i,
   input wire [31:0] mem_addr,
  
   input wire 	     ms_write_i,
   input wire [31:0] ms_write_data_i,
   input wire [3:0]  ms_write_mask_i,

   output reg 	     if_ms_rep_o,
   output reg [63:0] if_ms_rep_data_o,

   output reg 	     mem_ms_rep_o,
   output reg [63:0] mem_ms_rep_data_o
   );

   reg [`InstBus]    mem_data[0:`MemNumber];
   
   initial $readmemh("instr.data",mem_data);



   
   
   always @ (*)
     begin
	if_ms_rep_o <= 0;
	if_ms_rep_data_o <= 0;

	if (if_ms_req_i == 1'b1)
	  begin
	     if_ms_rep_o <= 1;
	     if_ms_rep_data_o <= {mem_data[((if_addr>>3)<<1)+1],mem_data[(if_addr>>3)<<1]};
	  end
     end
   
   always @ (*)
     begin	
	mem_ms_rep_o <= 0;
	mem_ms_rep_data_o <= 0;

	if (mem_ms_req_i == 1'b1)
	  begin


	     
	     mem_ms_rep_o <= 1;
	     mem_ms_rep_data_o <= {mem_data[((mem_addr>>3)<<1)+1],mem_data[(mem_addr>>3)<<1]};
	  end
     end

   always @ (posedge clk)
     begin
	if (ms_write_i == 1'b1)
	  begin
	     if (ms_write_mask_i[3] == 1)
	       mem_data[mem_addr>>2][7:0] <= ms_write_data_i[31:24];
	     if (ms_write_mask_i[2] == 1)
	       mem_data[mem_addr>>2][15:8] <= ms_write_data_i[23:16];
	     if (ms_write_mask_i[1] == 1)
	       mem_data[mem_addr>>2][23:16] <= ms_write_data_i[15:8];
	     if (ms_write_mask_i[0] == 1)
	       begin
		  mem_data[mem_addr>>2][31:24] <= ms_write_data_i[7:0];
		  if (mem_addr == 32'h00000104)
		    $display("Print (%c)",ms_write_data_i[7:0]);
	       end
	  end
     end   


      
endmodule
module mem_sim
  (
   input wire 	     clk,
     
   input wire 	     if_ms_req_i,
   input wire [31:0] if_addr,

   input wire 	     mem_ms_req_i,
   input wire [31:0] mem_addr,
  
   input wire 	     ms_write_i,
   input wire [31:0] ms_write_data_i,
   input wire [3:0]  ms_write_mask_i,

   output reg 	     if_ms_rep_o,
   output reg [63:0] if_ms_rep_data_o,

   output reg 	     mem_ms_rep_o,
   output reg [63:0] mem_ms_rep_data_o
   );


   reg [`InstBus]    mem_data[0:`MemNumber];
   
   initial $readmemh("instr.data",mem_data);



   
   
   always @ (*)
     begin
	if_ms_rep_o <= 0;
	if_ms_rep_data_o <= 0;

	if (if_ms_req_i == 1'b1)
	  begin
	     if_ms_rep_o <= 1;
	     if_ms_rep_data_o <= {mem_data[((if_addr>>3)<<1)+1],mem_data[(if_addr>>3)<<1]};
	  end
     end
   
   always @ (*)
     begin	
	mem_ms_rep_o <= 0;
	mem_ms_rep_data_o <= 0;

	if (mem_ms_req_i == 1'b1)
	  begin


	     
	     mem_ms_rep_o <= 1;
	     mem_ms_rep_data_o <= {mem_data[((mem_addr>>3)<<1)+1],mem_data[(mem_addr>>3)<<1]};
	  end
     end

   always @ (posedge clk)
     begin
	if (ms_write_i == 1'b1)
	  begin
	     if (ms_write_mask_i[3] == 1)
	       mem_data[mem_addr>>2][7:0] <= ms_write_data_i[31:24];
	     if (ms_write_mask_i[2] == 1)
	       mem_data[mem_addr>>2][15:8] <= ms_write_data_i[23:16];
	     if (ms_write_mask_i[1] == 1)
	       mem_data[mem_addr>>2][23:16] <= ms_write_data_i[15:8];
	     if (ms_write_mask_i[0] == 1)
	       begin
		  mem_data[mem_addr>>2][31:24] <= ms_write_data_i[7:0];
		  if (mem_addr == 32'h00000104)
		    $display("Print (%c)",ms_write_data_i[7:0]);
	       end
	  end
     end   


      
endmodule