data/full_repos/permissive/157494568/Part3/gated_d_latch.v
data/verilator_xmls/cf2405a7-473a-4d93-984b-fbc56fd4e048.xml
module gated_d_latch(clk, D, Q);

input clk, D;
output reg Q;

always @ (D, clk)
	if (clk)
		Q = D;

endmodule
module gated_d_latch(clk, D, Q);


input clk, D;
output reg Q;

always @ (D, clk)
	if (clk)
		Q = D;

endmodule