data/full_repos/permissive/117026779/sim/Test_Keyboard.v
 line:60: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Keyboard.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Keyboard.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Keyboard.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Keyboard.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Keyboard.v:103: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Keyboard.v:102: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Keyboard.v:107: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_Keyboard.v:108: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: data/full_repos/permissive/117026779/sim/Test_Keyboard.v:37: Cannot find file containing module: \'Keyboard\'\nKeyboard keyboard(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/Keyboard\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/Keyboard.v\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/Keyboard.sv\n             Keyboard\n             Keyboard.v\n             Keyboard.sv\n             obj_dir/Keyboard\n             obj_dir/Keyboard.v\n             obj_dir/Keyboard.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_Keyboard;

reg clk;
reg rst;
reg clr;
reg ps2_clk;
reg ps2_data;

wire [7:0] data;
wire cs;
wire ready;

assign cs = 1;

Keyboard keyboard(
    .clk(clk),
    .rst(rst),
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),
    .data(data),
    .cs(cs),
    .clr(clr),
    .ready(ready)
);

task RESET;
begin
    rst = 0;
    clk = 0;
    ps2_clk = 0;
    ps2_data = 0;
    clr = 0;
    #5
    rst = 1;
    #5
    rst = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
	end
end
endtask

reg [10:0] payload;

task PS2_TRANSMIT;
	input [7:0] send;
	integer k;
begin
    
    payload = {1'b1, ~^send, send[7], send[6], send[5], send[4], send[3], send[2], send[1], send[0], 1'b0};
    $display("payload = 0b%b",payload);
	for (k=0; k < 11; k = k + 1)
	begin
        ps2_data = payload[k];
        ps2_clk = 1;
        $display("payload = 0b%b :: send = 0b%b :: ps2_data = 0b%b :: k = %d", payload, send, ps2_data, k);
        CLOCK(1);
        ps2_clk = 0;
        CLOCK(1);
	end
    ps2_clk = 1;
    CLOCK(1);
end
endtask

parameter FULL_CYCLE = 32'd10_000_000;

initial begin
    #10
    #10
	RESET;
    PS2_TRANSMIT(8'h1C);
    CLOCK(10);
    #10 $stop;
    #5 $finish;
end

endmodule
module Test_Keyboard;


reg clk;
reg rst;
reg clr;
reg ps2_clk;
reg ps2_data;

wire [7:0] data;
wire cs;
wire ready;

assign cs = 1;

Keyboard keyboard(
    .clk(clk),
    .rst(rst),
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),
    .data(data),
    .cs(cs),
    .clr(clr),
    .ready(ready)
);

task RESET;
begin
    rst = 0;
    clk = 0;
    ps2_clk = 0;
    ps2_data = 0;
    clr = 0;
    #5
    rst = 1;
    #5
    rst = 0;
end
endtask;

task CLOCK;
	input [31:0] count;
	integer k;
begin
	for (k=0; k < count; k = k+1)
	begin
		#5
		clk = 1;
		#5
		clk = 0;
	end
end
endtask

reg [10:0] payload;

task PS2_TRANSMIT;
	input [7:0] send;
	integer k;
begin
    
    payload = {1'b1, ~^send, send[7], send[6], send[5], send[4], send[3], send[2], send[1], send[0], 1'b0};
    $display("payload = 0b%b",payload);
	for (k=0; k < 11; k = k + 1)
	begin
        ps2_data = payload[k];
        ps2_clk = 1;
        $display("payload = 0b%b :: send = 0b%b :: ps2_data = 0b%b :: k = %d", payload, send, ps2_data, k);
        CLOCK(1);
        ps2_clk = 0;
        CLOCK(1);
	end
    ps2_clk = 1;
    CLOCK(1);
end
endtask

parameter FULL_CYCLE = 32'd10_000_000;

initial begin
    #10
    #10
	RESET;
    PS2_TRANSMIT(8'h1C);
    CLOCK(10);
    #10 $stop;
    #5 $finish;
end

endmodule