data/full_repos/permissive/106029354/verilog_source/regs_testbench.v
1: b'%Error: data/full_repos/permissive/106029354/verilog_source/regs_testbench.v:4: Cannot find include file: params_proc.v\n`include "params_proc.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.v\n             data/full_repos/permissive/106029354/verilog_source,data/full_repos/permissive/106029354/params_proc.v.sv\n             params_proc.v\n             params_proc.v.v\n             params_proc.v.sv\n             obj_dir/params_proc.v\n             obj_dir/params_proc.v.v\n             obj_dir/params_proc.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/106029354/verilog_source/regs_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106029354/verilog_source/regs_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module regs_testbench();


`include "params_proc.v"


parameter N_TESTES = 11;


integer testes;


reg clk, en_write;
reg [REG_ADDR_WIDTH-1:0] addr_write, addr_read1, addr_read2;
reg signed [DATA_WIDTH-1:0] data_write;

wire signed [DATA_WIDTH-1:0] data_read1, data_read2;


regs regs0(
	.clk(clk),
	.en_write(en_write),
	.data_write(data_write),
	.addr_write(addr_write),
	.addr_read1(addr_read1),
	.addr_read2(addr_read2),
	.data_read1(data_read1),
	.data_read2(data_read2));


initial begin
    testes <= 0;

    clk <= 0;
end


always begin

	#2;
	clk = !clk;
end


always begin
	#4;
	testes = testes+1;

	case(testes)
	1: begin
		en_write = 1;
		addr_write = 0;
		data_write = 5;
		addr_read1 = 0;
		addr_read2 = 0;
	end
	2: begin
		en_write = 0;
		addr_write = 7;
		data_write = 65;
		addr_read1 = 0;
		addr_read2 = 1;
	end
	3: begin
		en_write = 1;
		addr_write = 8;
		data_write = 11;
		addr_read1 = 0;
		addr_read2 = 1;
	end
	4: begin
		en_write = 0;
		addr_write = 7;
		data_write = 18;
		addr_read1 = 8;
		addr_read2 = 1;
	end
	5: begin
		en_write = 1;
		addr_write = 1;
		data_write = 16;
		addr_read1 = 0;
		addr_read2 = 1;
	end
	6: begin
		en_write = 1;
		addr_write = 2;
		data_write = 24;
		addr_read1 = 0;
		addr_read2 = 1;
	end
	7: begin
		en_write = 0;
		addr_write = 2;
		data_write = 29;
		addr_read1 = 1;
		addr_read2 = 2;
	end
	8: begin
		en_write = 1;
		addr_write = 15;
		data_write = 20;
		addr_read1 = 1;
		addr_read2 = 2;
	end
	9: begin
		en_write = 0;
		addr_write = 21;
		data_write = 25400;
		addr_read1 = 15;
		addr_read2 = 0;
	end
	10: begin
		en_write = 1;
		addr_write = 31;
		data_write = 2000;
		addr_read1 = 15;
		addr_read2 = 0;
	end
	11: begin
		en_write = 0;
		addr_write = 20;
		data_write = 200;
		addr_read1 = 31;
		addr_read2 = 0;
	end
	default: begin

	end
	endcase
end


always @(posedge clk) begin
	if (testes > 0 && testes  <= N_TESTES) begin

		$display("  Teste # %2d  =>  ", testes);
		$display("\t WRITE  -  EN: %b  -  ADDR: %3d  -  DATA: %6d  ", en_write, addr_write, data_write);
	    $display("\t READ_1\n\t   ADDR: %3d  ", addr_read1);
	    $display("\t   DATA: %6d  ", data_read1);
	    $display("\t READ_2\n\t   ADDR: %3d  ", addr_read2);
	    $display("\t   DATA: %6d  ", data_read2);
	    $display(" ");
	end
end


endmodule
module regs_testbench();



`include "params_proc.v"


parameter N_TESTES = 11;


integer testes;


reg clk, en_write;
reg [REG_ADDR_WIDTH-1:0] addr_write, addr_read1, addr_read2;
reg signed [DATA_WIDTH-1:0] data_write;

wire signed [DATA_WIDTH-1:0] data_read1, data_read2;


regs regs0(
	.clk(clk),
	.en_write(en_write),
	.data_write(data_write),
	.addr_write(addr_write),
	.addr_read1(addr_read1),
	.addr_read2(addr_read2),
	.data_read1(data_read1),
	.data_read2(data_read2));


initial begin
    testes <= 0;

    clk <= 0;
end


always begin

	#2;
	clk = !clk;
end


always begin
	#4;
	testes = testes+1;

	case(testes)
	1: begin
		en_write = 1;
		addr_write = 0;
		data_write = 5;
		addr_read1 = 0;
		addr_read2 = 0;
	end
	2: begin
		en_write = 0;
		addr_write = 7;
		data_write = 65;
		addr_read1 = 0;
		addr_read2 = 1;
	end
	3: begin
		en_write = 1;
		addr_write = 8;
		data_write = 11;
		addr_read1 = 0;
		addr_read2 = 1;
	end
	4: begin
		en_write = 0;
		addr_write = 7;
		data_write = 18;
		addr_read1 = 8;
		addr_read2 = 1;
	end
	5: begin
		en_write = 1;
		addr_write = 1;
		data_write = 16;
		addr_read1 = 0;
		addr_read2 = 1;
	end
	6: begin
		en_write = 1;
		addr_write = 2;
		data_write = 24;
		addr_read1 = 0;
		addr_read2 = 1;
	end
	7: begin
		en_write = 0;
		addr_write = 2;
		data_write = 29;
		addr_read1 = 1;
		addr_read2 = 2;
	end
	8: begin
		en_write = 1;
		addr_write = 15;
		data_write = 20;
		addr_read1 = 1;
		addr_read2 = 2;
	end
	9: begin
		en_write = 0;
		addr_write = 21;
		data_write = 25400;
		addr_read1 = 15;
		addr_read2 = 0;
	end
	10: begin
		en_write = 1;
		addr_write = 31;
		data_write = 2000;
		addr_read1 = 15;
		addr_read2 = 0;
	end
	11: begin
		en_write = 0;
		addr_write = 20;
		data_write = 200;
		addr_read1 = 31;
		addr_read2 = 0;
	end
	default: begin

	end
	endcase
end


always @(posedge clk) begin
	if (testes > 0 && testes  <= N_TESTES) begin

		$display("  Teste # %2d  =>  ", testes);
		$display("\t WRITE  -  EN: %b  -  ADDR: %3d  -  DATA: %6d  ", en_write, addr_write, data_write);
	    $display("\t READ_1\n\t   ADDR: %3d  ", addr_read1);
	    $display("\t   DATA: %6d  ", data_read1);
	    $display("\t READ_2\n\t   ADDR: %3d  ", addr_read2);
	    $display("\t   DATA: %6d  ", data_read2);
	    $display(" ");
	end
end


endmodule