data/full_repos/permissive/162571337/multiplers/8x2_unsigned/pareto_pwr_mse/mul8x2u_0AJ.v
data/verilator_xmls/e5a2327b-6b6f-422f-b788-5c307b9c4f56.xml
module mul8x2u_0AJ (
    A,
    B,
    O
);

input [7:0] A;
input [1:0] B;
output [9:0] O;

wire sig_24,sig_25,sig_38,sig_50,sig_53;

assign sig_24 = A[6] & B[1];
assign sig_25 = A[7] & B[1];
assign sig_38 = sig_25 & A[6];
assign sig_50 = B[0] & A[7];
assign sig_53 = sig_25 ^ sig_24;

assign O[9] = sig_38;
assign O[8] = sig_53;
assign O[7] = sig_50;
assign O[6] = sig_50;
assign O[5] = 1'b0;
assign O[4] = sig_53;
assign O[3] = 1'b0;
assign O[2] = 1'b0;
assign O[1] = 1'b0;
assign O[0] = sig_50;

endmodule
module mul8x2u_0AJ (
    A,
    B,
    O
);


input [7:0] A;
input [1:0] B;
output [9:0] O;

wire sig_24,sig_25,sig_38,sig_50,sig_53;

assign sig_24 = A[6] & B[1];
assign sig_25 = A[7] & B[1];
assign sig_38 = sig_25 & A[6];
assign sig_50 = B[0] & A[7];
assign sig_53 = sig_25 ^ sig_24;

assign O[9] = sig_38;
assign O[8] = sig_53;
assign O[7] = sig_50;
assign O[6] = sig_50;
assign O[5] = 1'b0;
assign O[4] = sig_53;
assign O[3] = 1'b0;
assign O[2] = 1'b0;
assign O[1] = 1'b0;
assign O[0] = sig_50;

endmodule