data/full_repos/permissive/153023217/mfp_nexys4_ddr.v
1: b'%Error: data/full_repos/permissive/153023217/mfp_nexys4_ddr.v:15: Cannot find include file: mfp_ahb_const.vh\n`include "mfp_ahb_const.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/153023217,data/full_repos/permissive/153023217/mfp_ahb_const.vh\n             data/full_repos/permissive/153023217,data/full_repos/permissive/153023217/mfp_ahb_const.vh.v\n             data/full_repos/permissive/153023217,data/full_repos/permissive/153023217/mfp_ahb_const.vh.sv\n             mfp_ahb_const.vh\n             mfp_ahb_const.vh.v\n             mfp_ahb_const.vh.sv\n             obj_dir/mfp_ahb_const.vh\n             obj_dir/mfp_ahb_const.vh.v\n             obj_dir/mfp_ahb_const.vh.sv\n%Error: data/full_repos/permissive/153023217/mfp_nexys4_ddr.v:21: Define or directive not defined: \'`MFP_N_SW\'\n                        input  [`MFP_N_SW-1 :0] SW,\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/153023217/mfp_nexys4_ddr.v:22: Define or directive not defined: \'`MFP_N_LED\'\n                        output [`MFP_N_LED-1:0] LED,\n                                ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module mfp_nexys4_ddr( 
                        input                   CLK100MHZ,
                        input                   CPU_RESETN,
                        input                   BTNU, BTND, BTNL, BTNC, BTNR, 
                        input  [`MFP_N_SW-1 :0] SW,
                        output [`MFP_N_LED-1:0] LED,
                        inout  [ 8          :1] JB,
                        input                   UART_TXD_IN,
                        

                        output DP,CA,CB,CC,CD,CE,CF,CG,

                        output [7:0] AN);
                   


        
  wire clk_out; 

  wire tck_in, tck;
  
  
  clk_wiz_0 clk_wiz_0(.clk_in1(CLK100MHZ), .clk_out1(clk_out));
  IBUF IBUF1(.O(tck_in),.I(JB[4]));
  BUFG BUFG1(.O(tck), .I(tck_in));
                     
                     
  mfp_sys mfp_sys(
			        .SI_Reset_N(CPU_RESETN),
                    .SI_ClkIn(clk_out),
                    .HADDR(),
                    .HRDATA(),
                    .HWDATA(),
                    .HWRITE(),
					.HSIZE(),
                    .EJ_TRST_N_probe(JB[7]),
                    .EJ_TDI(JB[2]),
                    .EJ_TDO(JB[3]),
                    .EJ_TMS(JB[1]),
                    .EJ_TCK(tck),
                    .SI_ColdReset_N(JB[8]),
                    .EJ_DINT(1'b0),
                    .IO_Switch(SW),
                    .IO_PB({BTNU, BTND, BTNL, BTNC, BTNR}),
                    .IO_LED(LED),
                    .dispenout(AN),

                    .disout({DP,CA,CB,CC,CD,CE,CF,CG}),
                    .UART_RX(UART_TXD_IN));
          
endmodule
module mfp_nexys4_ddr( 
                        input                   CLK100MHZ,
                        input                   CPU_RESETN,
                        input                   BTNU, BTND, BTNL, BTNC, BTNR, 
                        input  [`MFP_N_SW-1 :0] SW,
                        output [`MFP_N_LED-1:0] LED,
                        inout  [ 8          :1] JB,
                        input                   UART_TXD_IN,
                        

                        output DP,CA,CB,CC,CD,CE,CF,CG,

                        output [7:0] AN);

                   


        
  wire clk_out; 

  wire tck_in, tck;
  
  
  clk_wiz_0 clk_wiz_0(.clk_in1(CLK100MHZ), .clk_out1(clk_out));
  IBUF IBUF1(.O(tck_in),.I(JB[4]));
  BUFG BUFG1(.O(tck), .I(tck_in));
                     
                     
  mfp_sys mfp_sys(
			        .SI_Reset_N(CPU_RESETN),
                    .SI_ClkIn(clk_out),
                    .HADDR(),
                    .HRDATA(),
                    .HWDATA(),
                    .HWRITE(),
					.HSIZE(),
                    .EJ_TRST_N_probe(JB[7]),
                    .EJ_TDI(JB[2]),
                    .EJ_TDO(JB[3]),
                    .EJ_TMS(JB[1]),
                    .EJ_TCK(tck),
                    .SI_ColdReset_N(JB[8]),
                    .EJ_DINT(1'b0),
                    .IO_Switch(SW),
                    .IO_PB({BTNU, BTND, BTNL, BTNC, BTNR}),
                    .IO_LED(LED),
                    .dispenout(AN),

                    .disout({DP,CA,CB,CC,CD,CE,CF,CG}),
                    .UART_RX(UART_TXD_IN));
          
endmodule