data/full_repos/permissive/172908596/Instruction Memory/IM_with_pc.v
1: b'%Error: Cannot find file containing module: Memory,data/full_repos/permissive/172908596\n        ... Looked in:\n             data/full_repos/permissive/172908596/Instruction/Memory,data/full_repos/permissive/172908596\n             data/full_repos/permissive/172908596/Instruction/Memory,data/full_repos/permissive/172908596.v\n             data/full_repos/permissive/172908596/Instruction/Memory,data/full_repos/permissive/172908596.sv\n             Memory,data/full_repos/permissive/172908596\n             Memory,data/full_repos/permissive/172908596.v\n             Memory,data/full_repos/permissive/172908596.sv\n             obj_dir/Memory,data/full_repos/permissive/172908596\n             obj_dir/Memory,data/full_repos/permissive/172908596.v\n             obj_dir/Memory,data/full_repos/permissive/172908596.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/172908596/Instruction\n%Error: Cannot find file containing module: Memory/IM_with_pc.v\n%Error: Exiting due to 3 error(s)\n'
module IM_with_pc(output reg[31:0] q,input clock,reset);
parameter addr_width=4,ins_width=8;
  reg [addr_width-1:0] pc;
  reg [ins_width-1:0] ins_memory[2**addr_width-1:0];
  initial
    begin
      pc=0;
      ins_memory[0]=8'b00000000;
      ins_memory[1]=8'b00000001;
      ins_memory[2]=8'b00000010;
      ins_memory[3]=8'b00000011;
      ins_memory[4]=8'b00000100;
      ins_memory[5]=8'b00000101;
      ins_memory[6]=8'b00000110;
      ins_memory[7]=8'b00000111;
      ins_memory[8]=8'b00001000;
      ins_memory[9]=8'b00001001;
      ins_memory[10]=8'b00001010;
      ins_memory[11]=8'b00001011;
      ins_memory[12]=8'b00001100;
      ins_memory[13]=8'b00001101;
      ins_memory[14]=8'b00001110;
      ins_memory[15]=8'b00001111;
    end
  always @(posedge clock)
    begin

      pc=pc+4;
      if(reset)
      begin
        pc=0;
      end
      q[7:0]=ins_memory[pc];
      q[15:8]=ins_memory[pc+1];
      q[23:16]=ins_memory[pc+2];
      q[31:24]=ins_memory[pc+3];
    end
endmodule
module IM_with_pc(output reg[31:0] q,input clock,reset);

parameter addr_width=4,ins_width=8;
  reg [addr_width-1:0] pc;
  reg [ins_width-1:0] ins_memory[2**addr_width-1:0];
  initial
    begin
      pc=0;
      ins_memory[0]=8'b00000000;
      ins_memory[1]=8'b00000001;
      ins_memory[2]=8'b00000010;
      ins_memory[3]=8'b00000011;
      ins_memory[4]=8'b00000100;
      ins_memory[5]=8'b00000101;
      ins_memory[6]=8'b00000110;
      ins_memory[7]=8'b00000111;
      ins_memory[8]=8'b00001000;
      ins_memory[9]=8'b00001001;
      ins_memory[10]=8'b00001010;
      ins_memory[11]=8'b00001011;
      ins_memory[12]=8'b00001100;
      ins_memory[13]=8'b00001101;
      ins_memory[14]=8'b00001110;
      ins_memory[15]=8'b00001111;
    end
  always @(posedge clock)
    begin

      pc=pc+4;
      if(reset)
      begin
        pc=0;
      end
      q[7:0]=ins_memory[pc];
      q[15:8]=ins_memory[pc+1];
      q[23:16]=ins_memory[pc+2];
      q[31:24]=ins_memory[pc+3];
    end
endmodule