data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO/fifo_updated.v
1: b'%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO/fifo_updated.v:35: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'INITIALIZE_FIFO\' generates 16 bits.\n                                                                                                                            : ... In instance fifo\n      if (INITIALIZE_FIFO == "yes") begin\n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO/fifo_updated.v:81: Bit extraction of array[31:0] requires 5 bit index, not 4 bits.\n                                                                                                                            : ... In instance fifo\n      mem[wr_pointer] <= data_in;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/150133337/designs/lenet_pu1_pe64/verilog/source/primitives/FIFO/fifo_updated.v:91: Bit extraction of array[31:0] requires 5 bit index, not 4 bits.\n                                                                                                                            : ... In instance fifo\n      data_out <= mem[rd_pointer];\n                     ^\n%Error: Exiting due to 3 warning(s)\n'
module fifo 
#(
    parameter   DATA_WIDTH          = 64,
    parameter   INIT                = "init.mif",
    parameter   ADDR_WIDTH          = 4,
    parameter   RAM_DEPTH           = (1 << ADDR_WIDTH),
    parameter   FIFO_DEPTH          = 32,
    parameter   INITIALIZE_FIFO     = "no",
    parameter   TYPE                = "MLAB"
)(
    input  wire                         clk,
    input  wire                         reset,
    input  wire                         push,
    input  wire                         pop,
    input  wire [ DATA_WIDTH -1 : 0 ]   data_in,
    output reg  [ DATA_WIDTH -1 : 0 ]   data_out,
    output reg                          empty,
    output reg                          full,
    output reg  [ ADDR_WIDTH    : 0 ]   fifo_count
);    
 




    reg     [ADDR_WIDTH-1:0]        wr_pointer;
    reg     [ADDR_WIDTH-1:0]        rd_pointer;

    reg     [DATA_WIDTH-1:0]        mem[0:FIFO_DEPTH-1];



    initial begin
      if (INITIALIZE_FIFO == "yes") begin
        $readmemh(INIT, mem, 0, RAM_DEPTH-1);
      end
    end

    always @ (fifo_count)
    begin : FIFO_STATUS
    	empty   = (fifo_count == 0);
    	full    = (fifo_count == RAM_DEPTH);
    end
    
    always @ (posedge clk)
    begin : FIFO_COUNTER
    	if (reset)
    		fifo_count <= 0;
    	
    	else if (push && !pop && !full)
    		fifo_count <= fifo_count + 1;
    		
    	else if (pop && !push && !empty)
    		fifo_count <= fifo_count - 1;
    end
    
    always @ (posedge clk)
    begin : WRITE_PTR
    	if (reset) begin
       		wr_pointer <= 0;
    	end 
    	else if (push && !full) begin
    		wr_pointer <= wr_pointer + 1;
    	end
    end
    
    always @ (posedge clk)
    begin : READ_PTR
    	if (reset) begin
    		rd_pointer <= 0;
    	end
    	else if (pop && !empty) begin
    		rd_pointer <= rd_pointer + 1;
    	end
    end
    
    always @ (posedge clk)
    begin : WRITE
        if (push & !full) begin
    		mem[wr_pointer] <= data_in;
        end
    end
    
    always @ (posedge clk)
    begin : READ
        if (reset) begin
	    	data_out <= 0;
        end
        if (pop && !empty) begin
    		data_out <= mem[rd_pointer];
        end
        else begin
    		data_out <= data_out;
        end
    end

endmodule
module fifo 
#(
    parameter   DATA_WIDTH          = 64,
    parameter   INIT                = "init.mif",
    parameter   ADDR_WIDTH          = 4,
    parameter   RAM_DEPTH           = (1 << ADDR_WIDTH),
    parameter   FIFO_DEPTH          = 32,
    parameter   INITIALIZE_FIFO     = "no",
    parameter   TYPE                = "MLAB"
)(
    input  wire                         clk,
    input  wire                         reset,
    input  wire                         push,
    input  wire                         pop,
    input  wire [ DATA_WIDTH -1 : 0 ]   data_in,
    output reg  [ DATA_WIDTH -1 : 0 ]   data_out,
    output reg                          empty,
    output reg                          full,
    output reg  [ ADDR_WIDTH    : 0 ]   fifo_count
);
    
 




    reg     [ADDR_WIDTH-1:0]        wr_pointer;
    reg     [ADDR_WIDTH-1:0]        rd_pointer;

    reg     [DATA_WIDTH-1:0]        mem[0:FIFO_DEPTH-1];



    initial begin
      if (INITIALIZE_FIFO == "yes") begin
        $readmemh(INIT, mem, 0, RAM_DEPTH-1);
      end
    end

    always @ (fifo_count)
    begin : FIFO_STATUS
    	empty   = (fifo_count == 0);
    	full    = (fifo_count == RAM_DEPTH);
    end
    
    always @ (posedge clk)
    begin : FIFO_COUNTER
    	if (reset)
    		fifo_count <= 0;
    	
    	else if (push && !pop && !full)
    		fifo_count <= fifo_count + 1;
    		
    	else if (pop && !push && !empty)
    		fifo_count <= fifo_count - 1;
    end
    
    always @ (posedge clk)
    begin : WRITE_PTR
    	if (reset) begin
       		wr_pointer <= 0;
    	end 
    	else if (push && !full) begin
    		wr_pointer <= wr_pointer + 1;
    	end
    end
    
    always @ (posedge clk)
    begin : READ_PTR
    	if (reset) begin
    		rd_pointer <= 0;
    	end
    	else if (pop && !empty) begin
    		rd_pointer <= rd_pointer + 1;
    	end
    end
    
    always @ (posedge clk)
    begin : WRITE
        if (push & !full) begin
    		mem[wr_pointer] <= data_in;
        end
    end
    
    always @ (posedge clk)
    begin : READ
        if (reset) begin
	    	data_out <= 0;
        end
        if (pop && !empty) begin
    		data_out <= mem[rd_pointer];
        end
        else begin
    		data_out <= data_out;
        end
    end

endmodule