data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #400 setpw = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #400 q[0] = ~q[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #400 q[0] = ~q[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #400 q[1] = ~q[1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #400 q[1] = ~q[1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #400 setpw = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #400 judge = ~judge;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #400 q[0] = ~q[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #400 q[0] = ~q[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #400 q[1] = ~q[1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #400 q[1] = ~q[1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #100 judge = ~judge;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #400 judge = ~judge;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #100 q[0] = ~q[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #100 q[0] = ~q[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #100 q[1] = ~q[1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #100 q[1] = ~q[1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #1000 judge = ~judge;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #400 judge = ~judge;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #50 q[0] = ~q[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #50 q[0] = ~q[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #200 rst =  1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #200 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #50 q[0] = ~q[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #50 q[0] = ~q[0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #50 q[1] = ~q[1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #50 q[1] = ~q[1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #1000 judge = ~judge;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:76: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new/main_sim.v:33: Cannot find file containing module: \'main\'\n    main m1(clk,q[0],q[1],q[2],q[3],rst,setpw,judge,pos,led,led_countdown,countdown,staus);\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new,data/full_repos/permissive/137633637/main\n             data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new,data/full_repos/permissive/137633637/main.v\n             data/full_repos/permissive/137633637/jingzhe.srcs/sim_1/new,data/full_repos/permissive/137633637/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 29 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_sim(

    );
    reg clk, rst, setpw, judge;
    reg [3:0]q;
    wire [6:0]led;
    wire [3:0]pos;
    wire [6:0]countdown;
    wire led_countdown;
    wire staus;
    main m1(clk,q[0],q[1],q[2],q[3],rst,setpw,judge,pos,led,led_countdown,countdown,staus);
    initial
    begin
        clk = 0; rst = 0; setpw = 0; judge = 0;
        q = 4'b0000;
        

        #400 setpw = 1;
        #400 q[0] = ~q[0];
        #400 q[0] = ~q[0];
        #400 q[1] = ~q[1];
        #400 q[1] = ~q[1];
        #400 setpw = 0;
        

        #400 judge = ~judge;
        #400 q[0] = ~q[0];
        #400 q[0] = ~q[0];
        #400 q[1] = ~q[1];
        #400 q[1] = ~q[1];
        #100 judge = ~judge;
        

        #400 judge = ~judge;
        #100 q[0] = ~q[0];
        #100 q[0] = ~q[0];
        #100 q[1] = ~q[1];
        #100 q[1] = ~q[1];
        #1000 judge = ~judge;
        

        #400 judge = ~judge;
        #50 q[0] = ~q[0];
        #50 q[0] = ~q[0];
        #200 rst =  1;
        #200 rst = 0;
        #50 q[0] = ~q[0];
        #50 q[0] = ~q[0];
        #50 q[1] = ~q[1];
        #50 q[1] = ~q[1];
        #1000 judge = ~judge;
    end
    
    always #1 clk = ~clk;
    
endmodule
module main_sim(

    );

    reg clk, rst, setpw, judge;
    reg [3:0]q;
    wire [6:0]led;
    wire [3:0]pos;
    wire [6:0]countdown;
    wire led_countdown;
    wire staus;
    main m1(clk,q[0],q[1],q[2],q[3],rst,setpw,judge,pos,led,led_countdown,countdown,staus);
    initial
    begin
        clk = 0; rst = 0; setpw = 0; judge = 0;
        q = 4'b0000;
        

        #400 setpw = 1;
        #400 q[0] = ~q[0];
        #400 q[0] = ~q[0];
        #400 q[1] = ~q[1];
        #400 q[1] = ~q[1];
        #400 setpw = 0;
        

        #400 judge = ~judge;
        #400 q[0] = ~q[0];
        #400 q[0] = ~q[0];
        #400 q[1] = ~q[1];
        #400 q[1] = ~q[1];
        #100 judge = ~judge;
        

        #400 judge = ~judge;
        #100 q[0] = ~q[0];
        #100 q[0] = ~q[0];
        #100 q[1] = ~q[1];
        #100 q[1] = ~q[1];
        #1000 judge = ~judge;
        

        #400 judge = ~judge;
        #50 q[0] = ~q[0];
        #50 q[0] = ~q[0];
        #200 rst =  1;
        #200 rst = 0;
        #50 q[0] = ~q[0];
        #50 q[0] = ~q[0];
        #50 q[1] = ~q[1];
        #50 q[1] = ~q[1];
        #1000 judge = ~judge;
    end
    
    always #1 clk = ~clk;
    
endmodule