data/full_repos/permissive/143278/ivltests/br_gh99x.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh99x.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh99x.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh99x.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/br_gh99x.v:11: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'value1\' generates 8 bits.\n                                                                        : ... In instance test\n  value2[3:0] <= value1;\n              ^~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

wire [7:0] value1;
reg  [7:0] value2;

reg clk;

assign value1[3:0] = 4'b1010;

always @(posedge clk) begin
  value2[3:0] <= value1;
end

(* ivl_synthesis_off *)
initial begin
  #1 clk = 0;
  #1 clk = 1;
  #1 clk = 0;
  $display("%b %b", value1, value2);
`ifdef __ICARUS_SYNTH__
  if (value2 === 8'bzzzz1010)
`else
  if (value2 === 8'bxxxx1010)
`endif
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module test();


wire [7:0] value1;
reg  [7:0] value2;

reg clk;

assign value1[3:0] = 4'b1010;

always @(posedge clk) begin
  value2[3:0] <= value1;
end

(* ivl_synthesis_off *)
initial begin
  #1 clk = 0;
  #1 clk = 1;
  #1 clk = 0;
  $display("%b %b", value1, value2);
`ifdef __ICARUS_SYNTH__
  if (value2 === 8'bzzzz1010)
`else
  if (value2 === 8'bxxxx1010)
`endif
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule