data/full_repos/permissive/170402453/UART.v
1: b'%Error: data/full_repos/permissive/170402453/UART.v:50: Wire inputs its own output, creating circular logic (wire x=x)\n                                                      : ... In instance UART\n assign RECV = RECV;\n             ^\n%Error: Exiting due to 1 error(s)\n'
module UART(
    input CLK,
    input BW,
	 inout SEND,
	 input [7:0] DATAOUT,
	 input RX,
    output TX,
    output [7:0] DATAIN,
	 output RECV
    );

	reg setSEND;
	reg [12:0] clkDiv, clkCounter;
	reg [7:0] DATAIN_, DATAOUT_;
	reg [3:0] rxCount, txCount;
	reg TX_D, RECV_;
	reg SEND_;
	
	assign DATAIN = DATAIN_;
	assign TX = TX_D;
	assign RECV = RECV;
	assign SEND = SEND_;
	

	initial begin
		clkDiv = 0;
		clkCounter = 0;
		DATAIN_ = 0;
		DATAOUT_= 0;
		rxCount = 0;
		txCount = 0;
	end


	always @(posedge CLK) begin
		RECV_ = 0;

		if(~BW) begin


			
			if(rxCount == 0) begin

			end else if(rxCount < 9) begin

				DATAIN_[7-(rxCount-1)] = RX;
			end else if(rxCount < 10)begin

			end else begin
				rxCount = -1;
				RECV_ = 1;
			end
			
			rxCount=rxCount+1;
		end else begin

			if(SEND || setSEND) begin

				setSEND = 1;
				
				if(txCount < 1) begin

					TX_D = 1;
				end else if(txCount < 9) begin
					TX_D = DATAOUT_[txCount-1];
				end else if(txCount < 11 && txCount >= 9) begin

					TX_D = 1;
				end else begin
					setSEND = 0;
					txCount = -1;
					SEND_ = 0;
					TX_D = 0;
				end
				
				
				
				txCount = txCount+1;
			end
		end
	end
	
	
endmodule
module UART(
    input CLK,
    input BW,
	 inout SEND,
	 input [7:0] DATAOUT,
	 input RX,
    output TX,
    output [7:0] DATAIN,
	 output RECV
    );


	reg setSEND;
	reg [12:0] clkDiv, clkCounter;
	reg [7:0] DATAIN_, DATAOUT_;
	reg [3:0] rxCount, txCount;
	reg TX_D, RECV_;
	reg SEND_;
	
	assign DATAIN = DATAIN_;
	assign TX = TX_D;
	assign RECV = RECV;
	assign SEND = SEND_;
	

	initial begin
		clkDiv = 0;
		clkCounter = 0;
		DATAIN_ = 0;
		DATAOUT_= 0;
		rxCount = 0;
		txCount = 0;
	end


	always @(posedge CLK) begin
		RECV_ = 0;

		if(~BW) begin


			
			if(rxCount == 0) begin

			end else if(rxCount < 9) begin

				DATAIN_[7-(rxCount-1)] = RX;
			end else if(rxCount < 10)begin

			end else begin
				rxCount = -1;
				RECV_ = 1;
			end
			
			rxCount=rxCount+1;
		end else begin

			if(SEND || setSEND) begin

				setSEND = 1;
				
				if(txCount < 1) begin

					TX_D = 1;
				end else if(txCount < 9) begin
					TX_D = DATAOUT_[txCount-1];
				end else if(txCount < 11 && txCount >= 9) begin

					TX_D = 1;
				end else begin
					setSEND = 0;
					txCount = -1;
					SEND_ = 0;
					TX_D = 0;
				end
				
				
				
				txCount = txCount+1;
			end
		end
	end
	
	
endmodule