data/full_repos/permissive/189193559/02/TrafficSignal.v
 line:23: before: "parameter"
data/verilator_xmls/af3dbdcf-f0a9-4981-836c-aa5f293d3d38.xml
module TrafficSignal(CLK, RST, CLED);

    input CLK, RST;
    output [2:0] CLED;
    

    reg [2:0] led_buf;

    reg [1:0] sig_state;

    reg [31:0] cnt_time;

    reg [31:0] cnt_clock;

    wire is_clk_max;
    

    assign CLED = led_buf;
    


    

    always @(posedge CLK) begin
        if(RST == 1) cnt_clock <= 0;
        else begin
            if(cnt_clock >= CLK_FREQ / 1000 - 1) cnt_clock <= 0;
            else cnt_clock <= cnt_clock + 1;
        end
    end
    assign is_clk_max = (cnt_clock == CLK_FREQ / 1000 - 1);
    

    always @(posedge CLK) begin
        if(RST == 1) begin
            cnt_time <= 0;
            sig_state <= S_RED;
        end
        else begin
            case(sig_state)
            S_RED: begin
                if(cnt_time >= R_PERIOD_MS) begin
                    cnt_time <= 0;
                    sig_state <= S_GREEN;
                end
                else if(is_clk_max) cnt_time <= cnt_time + 1;
            end
            S_GREEN: begin
                if(cnt_time >= G_PERIOD_MS) begin
                    cnt_time <= 0;
                    sig_state <= S_YELLOW;
                end
                else if(is_clk_max) cnt_time <= cnt_time + 1;
            end
            S_YELLOW: begin
                if(cnt_time >= Y_PERIOD_MS) begin
                    cnt_time <= 0;
                    sig_state <= S_RED;
                end
                else if(is_clk_max) cnt_time <= cnt_time + 1;
            end
            default:

                ;
            endcase
        end
    end
    

    always @(sig_state) begin
        case(sig_state)
        S_RED: led_buf = 3'b011;
        S_GREEN: led_buf = 3'b101;
        S_YELLOW:led_buf = 3'b001;
        default: led_buf = 3'b000;
        endcase
    end
    
endmodule
module TrafficSignal(CLK, RST, CLED);


    input CLK, RST;
    output [2:0] CLED;
    

    reg [2:0] led_buf;

    reg [1:0] sig_state;

    reg [31:0] cnt_time;

    reg [31:0] cnt_clock;

    wire is_clk_max;
    

    assign CLED = led_buf;
    


    

    always @(posedge CLK) begin
        if(RST == 1) cnt_clock <= 0;
        else begin
            if(cnt_clock >= CLK_FREQ / 1000 - 1) cnt_clock <= 0;
            else cnt_clock <= cnt_clock + 1;
        end
    end
    assign is_clk_max = (cnt_clock == CLK_FREQ / 1000 - 1);
    

    always @(posedge CLK) begin
        if(RST == 1) begin
            cnt_time <= 0;
            sig_state <= S_RED;
        end
        else begin
            case(sig_state)
            S_RED: begin
                if(cnt_time >= R_PERIOD_MS) begin
                    cnt_time <= 0;
                    sig_state <= S_GREEN;
                end
                else if(is_clk_max) cnt_time <= cnt_time + 1;
            end
            S_GREEN: begin
                if(cnt_time >= G_PERIOD_MS) begin
                    cnt_time <= 0;
                    sig_state <= S_YELLOW;
                end
                else if(is_clk_max) cnt_time <= cnt_time + 1;
            end
            S_YELLOW: begin
                if(cnt_time >= Y_PERIOD_MS) begin
                    cnt_time <= 0;
                    sig_state <= S_RED;
                end
                else if(is_clk_max) cnt_time <= cnt_time + 1;
            end
            default:

                ;
            endcase
        end
    end
    

    always @(sig_state) begin
        case(sig_state)
        S_RED: led_buf = 3'b011;
        S_GREEN: led_buf = 3'b101;
        S_YELLOW:led_buf = 3'b001;
        default: led_buf = 3'b000;
        endcase
    end
    
endmodule