data/full_repos/permissive/202776140/bidi_reg_stim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/202776140/bidi_reg_stim.v:31: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/202776140/bidi_reg_stim.v:39: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/202776140/bidi_reg_stim.v:47: Unsupported: Ignoring delay on this delayed statement.\n#10 \n^\n%Warning-STMTDLY: data/full_repos/permissive/202776140/bidi_reg_stim.v:57: Unsupported: Ignoring delay on this delayed statement.\nalways #5 CLOCK <= ~CLOCK;\n       ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bidi_reg_stim (
RESET,
CLOCK,
RW,
ENABLE,
COUNT,

DATA_OUT,
DATA_IN
);

output reg RESET;
output reg CLOCK;
output reg RW;
output reg ENABLE;
output reg COUNT;
output reg [15:0] DATA_OUT;
input wire [15:0] DATA_IN;


initial begin
    RESET = 1'b0;
    CLOCK = 1'b0;
    RW = 1'b1;
    ENABLE = 1'b0;
    COUNT = 1'b0;
    DATA_OUT = {16{1'bz}};

#10
    RESET = 1'b1;

    DATA_OUT = 16'hA5A5;
    RW = 1'b0;
    ENABLE = 1'b1;
    COUNT = 1'b0;

#10

    DATA_OUT = {16{1'bz}};
    RW = 1'b1;
    ENABLE = 1'b1;
    COUNT = 1'b0;
    $display(DATA_IN);

#10 

    DATA_OUT = {16{1'bz}};
    RW = 1'b1;
    ENABLE = 1'b1;
    COUNT = 1'b1;
    $display(DATA_IN);

end

always #5 CLOCK <= ~CLOCK;

endmodule
module bidi_reg_stim (
RESET,
CLOCK,
RW,
ENABLE,
COUNT,

DATA_OUT,
DATA_IN
);


output reg RESET;
output reg CLOCK;
output reg RW;
output reg ENABLE;
output reg COUNT;
output reg [15:0] DATA_OUT;
input wire [15:0] DATA_IN;


initial begin
    RESET = 1'b0;
    CLOCK = 1'b0;
    RW = 1'b1;
    ENABLE = 1'b0;
    COUNT = 1'b0;
    DATA_OUT = {16{1'bz}};

#10
    RESET = 1'b1;

    DATA_OUT = 16'hA5A5;
    RW = 1'b0;
    ENABLE = 1'b1;
    COUNT = 1'b0;

#10

    DATA_OUT = {16{1'bz}};
    RW = 1'b1;
    ENABLE = 1'b1;
    COUNT = 1'b0;
    $display(DATA_IN);

#10 

    DATA_OUT = {16{1'bz}};
    RW = 1'b1;
    ENABLE = 1'b1;
    COUNT = 1'b1;
    $display(DATA_IN);

end

always #5 CLOCK <= ~CLOCK;

endmodule