data/full_repos/permissive/209997170/Sound/pwm_tutorial/work/planAhead/PWM/PWM.srcs/sources_1/imports/verilog/mojo_top_0.v
 line:101: before: "/"
1: b"%Error: data/full_repos/permissive/209997170/Sound/pwm_tutorial/work/planAhead/PWM/PWM.srcs/sources_1/imports/verilog/mojo_top_0.v:32: Cannot find file containing module: 'pwm_1'\n  pwm_1 #(.CTR_LEN(3)) pwm_1 (   \n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/209997170/Sound/pwm_tutorial/work/planAhead/PWM/PWM.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170/pwm_1\n             data/full_repos/permissive/209997170/Sound/pwm_tutorial/work/planAhead/PWM/PWM.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170/pwm_1.v\n             data/full_repos/permissive/209997170/Sound/pwm_tutorial/work/planAhead/PWM/PWM.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170/pwm_1.sv\n             pwm_1\n             pwm_1.v\n             pwm_1.sv\n             obj_dir/pwm_1\n             obj_dir/pwm_1.v\n             obj_dir/pwm_1.sv\n%Error: data/full_repos/permissive/209997170/Sound/pwm_tutorial/work/planAhead/PWM/PWM.srcs/sources_1/imports/verilog/mojo_top_0.v:39: Cannot find file containing module: 'pwm_1'\n  pwm_1 #(.CTR_LEN(3)) pwm_2 (\n  ^~~~~\n%Error: data/full_repos/permissive/209997170/Sound/pwm_tutorial/work/planAhead/PWM/PWM.srcs/sources_1/imports/verilog/mojo_top_0.v:46: Cannot find file containing module: 'pwm_1'\n  pwm_1 #(.CTR_LEN(3)) pwm_3 (\n  ^~~~~\n%Error: data/full_repos/permissive/209997170/Sound/pwm_tutorial/work/planAhead/PWM/PWM.srcs/sources_1/imports/verilog/mojo_top_0.v:53: Cannot find file containing module: 'pwm_1'\n  pwm_1 #(.CTR_LEN(3)) pwm_4 (\n  ^~~~~\n%Error: data/full_repos/permissive/209997170/Sound/pwm_tutorial/work/planAhead/PWM/PWM.srcs/sources_1/imports/verilog/mojo_top_0.v:60: Cannot find file containing module: 'pwm_1'\n  pwm_1 #(.CTR_LEN(3)) pwm_5 (\n  ^~~~~\n%Error: data/full_repos/permissive/209997170/Sound/pwm_tutorial/work/planAhead/PWM/PWM.srcs/sources_1/imports/verilog/mojo_top_0.v:67: Cannot find file containing module: 'pwm_1'\n  pwm_1 #(.CTR_LEN(3)) pwm_6 (\n  ^~~~~\n%Error: data/full_repos/permissive/209997170/Sound/pwm_tutorial/work/planAhead/PWM/PWM.srcs/sources_1/imports/verilog/mojo_top_0.v:74: Cannot find file containing module: 'pwm_1'\n  pwm_1 #(.CTR_LEN(3)) pwm_7 (\n  ^~~~~\n%Error: data/full_repos/permissive/209997170/Sound/pwm_tutorial/work/planAhead/PWM/PWM.srcs/sources_1/imports/verilog/mojo_top_0.v:81: Cannot find file containing module: 'pwm_1'\n  pwm_1 #(.CTR_LEN(3)) pwm_8 (\n  ^~~~~\n%Error: Exiting due to 8 error(s)\n"
module mojo_top_0(

    input clk,

    input rst_n,

    input cclk,

    output[7:0]led,

    output spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,

    output [3:0] spi_channel,

    input avr_tx,
    output avr_rx,
    input avr_rx_busy
  );
 
  wire rst = ~rst_n;
 

  assign spi_miso = 1'bz;
  assign avr_rx = 1'bz;
  assign spi_channel = 4'bzzzz;
  

  
  pwm_1 #(.CTR_LEN(3)) pwm_1 (
    .rst(rst),
    .clk(clk),
    .compare(3'd0),
    .pwm(led[0])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_2 (
    .rst(rst),
    .clk(clk),
    .compare(3'd1),
    .pwm(led[1])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_3 (
    .rst(rst),
    .clk(clk),
    .compare(3'd2),
    .pwm(led[2])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_4 (
    .rst(rst),
    .clk(clk),
    .compare(3'd3),
    .pwm(led[3])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_5 (
    .rst(rst),
    .clk(clk),
    .compare(3'd4),
    .pwm(led[4])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_6 (
    .rst(rst),
    .clk(clk),
    .compare(3'd5),
    .pwm(led[5])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_7 (
    .rst(rst),
    .clk(clk),
    .compare(3'd6),
    .pwm(led[6])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_8 (
    .rst(rst),
    .clk(clk),
    .compare(3'd7),
    .pwm(led[7])
  );
 

endmodule
module mojo_top_0(

    input clk,

    input rst_n,

    input cclk,

    output[7:0]led,

    output spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,

    output [3:0] spi_channel,

    input avr_tx,
    output avr_rx,
    input avr_rx_busy
  );

 
  wire rst = ~rst_n;
 

  assign spi_miso = 1'bz;
  assign avr_rx = 1'bz;
  assign spi_channel = 4'bzzzz;
  

  
  pwm_1 #(.CTR_LEN(3)) pwm_1 (
    .rst(rst),
    .clk(clk),
    .compare(3'd0),
    .pwm(led[0])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_2 (
    .rst(rst),
    .clk(clk),
    .compare(3'd1),
    .pwm(led[1])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_3 (
    .rst(rst),
    .clk(clk),
    .compare(3'd2),
    .pwm(led[2])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_4 (
    .rst(rst),
    .clk(clk),
    .compare(3'd3),
    .pwm(led[3])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_5 (
    .rst(rst),
    .clk(clk),
    .compare(3'd4),
    .pwm(led[4])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_6 (
    .rst(rst),
    .clk(clk),
    .compare(3'd5),
    .pwm(led[5])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_7 (
    .rst(rst),
    .clk(clk),
    .compare(3'd6),
    .pwm(led[6])
  );
 
  pwm_1 #(.CTR_LEN(3)) pwm_8 (
    .rst(rst),
    .clk(clk),
    .compare(3'd7),
    .pwm(led[7])
  );
 

endmodule