data/full_repos/permissive/188024377/practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/mipstest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/188024377/practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/mipstest.v:19: Unsupported: Ignoring delay on this delayed statement.\n      reset <= 1; # 22; reset <= 0;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/188024377/practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/mipstest.v:25: Unsupported: Ignoring delay on this delayed statement.\n      clk <= 1; # 5; clk <= 0; # 5;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/188024377/practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/mipstest.v:25: Unsupported: Ignoring delay on this delayed statement.\n      clk <= 1; # 5; clk <= 0; # 5;\n                               ^\n%Error: data/full_repos/permissive/188024377/practical-training/tgdi-practical-training-2009-WiSe-solution/verilog/mipstest.v:14: Cannot find file containing module: \'top\'\n  top dut(clk, reset, leds);\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/188024377/practical-training/tgdi-practical-training-2009-WiSe-solution/verilog,data/full_repos/permissive/188024377/top\n             data/full_repos/permissive/188024377/practical-training/tgdi-practical-training-2009-WiSe-solution/verilog,data/full_repos/permissive/188024377/top.v\n             data/full_repos/permissive/188024377/practical-training/tgdi-practical-training-2009-WiSe-solution/verilog,data/full_repos/permissive/188024377/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

  reg         clk;
  reg         reset;

  wire [7:0] leds;


  top dut(clk, reset, leds);
  

  initial
    begin
      reset <= 1; # 22; reset <= 0;
    end


  always
    begin
      clk <= 1; # 5; clk <= 0; # 5;
    end

endmodule
module testbench();


  reg         clk;
  reg         reset;

  wire [7:0] leds;


  top dut(clk, reset, leds);
  

  initial
    begin
      reset <= 1; # 22; reset <= 0;
    end


  always
    begin
      clk <= 1; # 5; clk <= 0; # 5;
    end

endmodule