data/full_repos/permissive/2084115/testbench/sim/jfive/tb_jfive_simple_controller/tb_sim.sv
 line:14: before: "$"
1: b'%Error: data/full_repos/permissive/2084115/testbench/sim/jfive/tb_jfive_simple_controller/tb_sim.sv:10: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_sim.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/2084115/testbench/sim/jfive/tb_jfive_simple_controller/tb_sim.sv:11: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_sim);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/jfive/tb_jfive_simple_controller/tb_sim.sv:13: Unsupported: Ignoring delay on this delayed statement.\n    #1000000\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/jfive/tb_jfive_simple_controller/tb_sim.sv:18: Unsupported: Ignoring delay on this delayed statement.\n    always #(RATE*100)  reset = 1\'b0;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/2084115/testbench/sim/jfive/tb_jfive_simple_controller/tb_sim.sv:21: Unsupported: Ignoring delay on this delayed statement.\n    always #(RATE/2.0)  clk = ~clk;\n           ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sim();
    localparam RATE = 10.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #1000000
        $finish();
    end

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;
    





    tb_main
        i_main
            (
                .reset,
                .clk
            );



    
endmodule
module tb_sim();

    localparam RATE = 10.0;
    
    initial begin
        $dumpfile("tb_sim.vcd");
        $dumpvars(0, tb_sim);
        
    #1000000
        $finish();
    end

    reg     reset = 1'b1;
    always #(RATE*100)  reset = 1'b0;

    reg     clk = 1'b1;
    always #(RATE/2.0)  clk = ~clk;
    





    tb_main
        i_main
            (
                .reset,
                .clk
            );



    
endmodule