data/full_repos/permissive/165217789/FusionAccel/rtl/cmac.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/165217789/FusionAccel/rtl/cmac.v:28: Signal definition not found, creating implicitly: \'mult_ready\'\n        conv_ready <= mult_ready;\n                      ^~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/165217789/FusionAccel/rtl/cmac.v:16: Cannot find file containing module: \'multiplier\'\nmultiplier mult_ (.a(a_mult), .b(b_mult), .clk(clk), .operation_nd(data_ready), .operation_rfd(operation_rfd_mult),\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/165217789/FusionAccel/rtl,data/full_repos/permissive/165217789/multiplier\n             data/full_repos/permissive/165217789/FusionAccel/rtl,data/full_repos/permissive/165217789/multiplier.v\n             data/full_repos/permissive/165217789/FusionAccel/rtl,data/full_repos/permissive/165217789/multiplier.sv\n             multiplier\n             multiplier.v\n             multiplier.sv\n             obj_dir/multiplier\n             obj_dir/multiplier.v\n             obj_dir/multiplier.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module cmac(
    input  wire         clk,
    input  wire         rst,
    input  wire [15:0]  data,
    input  wire [15:0]  weight,
    output reg  [15:0]  result,
    input  wire         data_ready,
    output reg          data_valid,
    output reg          conv_ready
);

reg  [15:0] a_mult, b_mult;
wire        operation_rfd_mult;
wire [15:0] result_mult;

multiplier mult_ (.a(a_mult), .b(b_mult), .clk(clk), .operation_nd(data_ready), .operation_rfd(operation_rfd_mult),
.result(result_mult), .rdy(mult_ready));

always @ (posedge clk or posedge rst) begin
    if (rst) begin
        a_mult <= 16'h0000; b_mult <= 16'h0000;
        conv_ready <= 0;
        result <= 16'h0000;
        data_valid <= 0;
    end else begin
        data_valid <= operation_rfd_mult;
        if(data_ready) begin a_mult <= data; b_mult <= weight; end
        conv_ready <= mult_ready;
        result <= result_mult;
    end
end
endmodule
module cmac(
    input  wire         clk,
    input  wire         rst,
    input  wire [15:0]  data,
    input  wire [15:0]  weight,
    output reg  [15:0]  result,
    input  wire         data_ready,
    output reg          data_valid,
    output reg          conv_ready
);


reg  [15:0] a_mult, b_mult;
wire        operation_rfd_mult;
wire [15:0] result_mult;

multiplier mult_ (.a(a_mult), .b(b_mult), .clk(clk), .operation_nd(data_ready), .operation_rfd(operation_rfd_mult),
.result(result_mult), .rdy(mult_ready));

always @ (posedge clk or posedge rst) begin
    if (rst) begin
        a_mult <= 16'h0000; b_mult <= 16'h0000;
        conv_ready <= 0;
        result <= 16'h0000;
        data_valid <= 0;
    end else begin
        data_valid <= operation_rfd_mult;
        if(data_ready) begin a_mult <= data; b_mult <= weight; end
        conv_ready <= mult_ready;
        result <= result_mult;
    end
end
endmodule