data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v
 line:193: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:165: Unsupported: Ignoring delay on this delayed statement.\n      #RESET_TIME;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:170: Unsupported: Ignoring delay on this delayed statement.\n      #CLOCK_HALF_PERIOD;\n      ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:214: Unsupported: wait statements\n  wait (reset_n == 1);\n  ^~~~\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:215: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:222: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:226: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:229: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:231: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:235: syntax error, unexpected \'@\'\n  repeat (DEPTH-2) @(posedge clk);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:236: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:240: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:241: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:247: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:248: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:254: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:255: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:259: syntax error, unexpected \'@\'\n  repeat (DEPTH-2) @(posedge clk);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:260: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:264: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:265: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:281: syntax error, unexpected \'@\'\n     @(posedge clk);\n     ^\n%Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:282: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n     in_valid  <= ($random(23) && 1);\n                   ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/18477150/lib/sonic/vc/sonic_vc/synthesis/submodules/sonic_vc_timing_adapter_fifo.v:282: ../V3Ast.cpp:358: Null item passed to setOp1p\n     in_valid  <= ($random(23) && 1);\n                               ^~\n                        ... See the manual and https://verilator.org for more assistance.\n'
module test_sonic_vc_timing_adapter_fifo;
   
   parameter DEPTH = 8;
   parameter DATA_WIDTH = 133;
   parameter ADDR_WIDTH = 3;




   localparam CLOCK_HALF_PERIOD       = 10;
   localparam CLOCK_PERIOD            = 2*CLOCK_HALF_PERIOD;
   localparam RESET_TIME              = 25;
   



   reg 	                 clk          = 0;
   reg 			 reset_n      = 0;
   reg 			 test_success = 1;
   reg 			 success      = 1;
   wire 		 in_ready;
   reg 			 in_valid;
   reg [DATA_WIDTH-1:0]  in_data;
   reg 			 out_ready;
   wire 		 out_valid;
   wire [DATA_WIDTH-1:0] out_data;
   reg [DATA_WIDTH-1:0]  next_out_data;
			 



   sonic_vc_timing_adapter_fifo dut (
		.clk       (clk),
		.reset_n   (reset_n),
		.in_ready  (in_ready),
		.in_valid  (in_valid),      
		.in_data   (in_data),
		.out_ready (out_ready),
		.out_valid (out_valid),      
		.out_data  (out_data)
		);
   



   initial begin
      reset_n = 0;
      #RESET_TIME;
      reset_n = 1;
   end
   
   always begin
      #CLOCK_HALF_PERIOD;
      clk <= ~clk;
   end
   



   always @(posedge clk) begin
      if (reset_n == 0)
	in_data <= 0;
      else
	if (in_ready && in_valid)
	  in_data <= in_data + 1;
   end
   



   always @(posedge clk) begin
      if (reset_n == 0)
	next_out_data <= 0;
      else
	if (out_ready && out_valid) begin
	   test_assert ("Data Error",out_data == next_out_data);
	   next_out_data <= next_out_data + 1;
	end
   end
   



   initial begin
      test_exactly_full_and_empty();
      test_random();
      $finish;
   end
   



   task test_exactly_full_and_empty;
      begin
	 test_success = 1;
	 
	 wait (reset_n == 1);
	 @(posedge clk);
	 
	 empty_the_fifo();
	 
	 test_assert ("Empty: should be ready", in_ready == 1);
	 test_assert ("Empty: should not be valid", out_valid == 0);
	 
	 @(posedge clk);
	 in_valid <= 1;
	 out_ready <= 0;
	 
	 @(posedge clk);
	 in_valid <= 0;
	 
	 @(posedge clk);
	 in_valid <= 1;
	 #1;
	 test_assert ("Almost Empty: should be ready", in_ready == 1);
	 test_assert ("Almost Empty: should be valid", out_valid == 1);

	 repeat (DEPTH-2) @(posedge clk);
	 #1;
	 test_assert ("Almost Full: should be ready", in_ready == 1);
	 test_assert ("Almost Full: should be valid", out_valid == 1);
	 
	 @(posedge clk);
	 #1;
	 test_assert ("Full: should be NOT ready", in_ready == 0);
	 test_assert ("Full: should be valid", out_valid == 1);
	 
	 in_valid <= 0;
	 out_ready <= 0;
	 @(posedge clk);
	 #1;
	 test_assert ("Still Full: should be NOT ready", in_ready == 0);
	 test_assert ("Still Full: should be valid", out_valid == 1);

	 in_valid <= 0;
	 out_ready <= 1;
	 @(posedge clk);
	 #1;
	 test_assert ("Almost Full: should be ready", in_ready == 1);
	 test_assert ("Almost Full 2: should be valid", out_valid == 1);
	 
	 repeat (DEPTH-2) @(posedge clk);
	 #1;
	 test_assert ("Almost Empty: should be ready", in_ready == 1);
	 test_assert ("Almost Empty 2: should be valid", out_valid == 1);

	 @(posedge clk);
	 #1;
	 test_assert ("Empty: should be ready", in_ready == 1);
	 test_assert ("Empty 2: should not be valid", out_valid == 0);

	 endtest("test_exactly_full_and_empty");
	 
      end	 
   endtask




   task test_random;
      begin
	 test_success = 1;
	 repeat(20 * DEPTH) begin
	    @(posedge clk);
	    in_valid  <= ($random(23) && 1);
	    out_ready <= ($random(23) && 1);
	 end
	 endtest("test_random");
      end
   endtask




   task empty_the_fifo;
      begin
	 in_valid <= 0;
	 out_ready <= 1;
	 repeat (DEPTH) @(posedge clk);
	 out_ready = 0;
      end
   endtask
   



   task test_assert;
      input [256:0] message;
      input         condition;
      begin
	 if (! condition) begin
	    $display("(sim)%t: %s",$time, message);
	    success = 0;
	    test_success = 0;
	 end
      end
   endtask




   task endtest;
      input [256:0] message;
      begin
	 if (test_success) begin
	    $display("(sim)%t: %-40s: Pass",$time, message);
	 end else begin
	    $display("(sim)%t: %-40s: Fail",$time, message);
	 end
	 success = success & test_success;
      end
   endtask
     
endmodule
module test_sonic_vc_timing_adapter_fifo;

   
   parameter DEPTH = 8;
   parameter DATA_WIDTH = 133;
   parameter ADDR_WIDTH = 3;




   localparam CLOCK_HALF_PERIOD       = 10;
   localparam CLOCK_PERIOD            = 2*CLOCK_HALF_PERIOD;
   localparam RESET_TIME              = 25;
   



   reg 	                 clk          = 0;
   reg 			 reset_n      = 0;
   reg 			 test_success = 1;
   reg 			 success      = 1;
   wire 		 in_ready;
   reg 			 in_valid;
   reg [DATA_WIDTH-1:0]  in_data;
   reg 			 out_ready;
   wire 		 out_valid;
   wire [DATA_WIDTH-1:0] out_data;
   reg [DATA_WIDTH-1:0]  next_out_data;
			 



   sonic_vc_timing_adapter_fifo dut (
		.clk       (clk),
		.reset_n   (reset_n),
		.in_ready  (in_ready),
		.in_valid  (in_valid),      
		.in_data   (in_data),
		.out_ready (out_ready),
		.out_valid (out_valid),      
		.out_data  (out_data)
		);
   



   initial begin
      reset_n = 0;
      #RESET_TIME;
      reset_n = 1;
   end
   
   always begin
      #CLOCK_HALF_PERIOD;
      clk <= ~clk;
   end
   



   always @(posedge clk) begin
      if (reset_n == 0)
	in_data <= 0;
      else
	if (in_ready && in_valid)
	  in_data <= in_data + 1;
   end
   



   always @(posedge clk) begin
      if (reset_n == 0)
	next_out_data <= 0;
      else
	if (out_ready && out_valid) begin
	   test_assert ("Data Error",out_data == next_out_data);
	   next_out_data <= next_out_data + 1;
	end
   end
   



   initial begin
      test_exactly_full_and_empty();
      test_random();
      $finish;
   end
   



   task test_exactly_full_and_empty;
      begin
	 test_success = 1;
	 
	 wait (reset_n == 1);
	 @(posedge clk);
	 
	 empty_the_fifo();
	 
	 test_assert ("Empty: should be ready", in_ready == 1);
	 test_assert ("Empty: should not be valid", out_valid == 0);
	 
	 @(posedge clk);
	 in_valid <= 1;
	 out_ready <= 0;
	 
	 @(posedge clk);
	 in_valid <= 0;
	 
	 @(posedge clk);
	 in_valid <= 1;
	 #1;
	 test_assert ("Almost Empty: should be ready", in_ready == 1);
	 test_assert ("Almost Empty: should be valid", out_valid == 1);

	 repeat (DEPTH-2) @(posedge clk);
	 #1;
	 test_assert ("Almost Full: should be ready", in_ready == 1);
	 test_assert ("Almost Full: should be valid", out_valid == 1);
	 
	 @(posedge clk);
	 #1;
	 test_assert ("Full: should be NOT ready", in_ready == 0);
	 test_assert ("Full: should be valid", out_valid == 1);
	 
	 in_valid <= 0;
	 out_ready <= 0;
	 @(posedge clk);
	 #1;
	 test_assert ("Still Full: should be NOT ready", in_ready == 0);
	 test_assert ("Still Full: should be valid", out_valid == 1);

	 in_valid <= 0;
	 out_ready <= 1;
	 @(posedge clk);
	 #1;
	 test_assert ("Almost Full: should be ready", in_ready == 1);
	 test_assert ("Almost Full 2: should be valid", out_valid == 1);
	 
	 repeat (DEPTH-2) @(posedge clk);
	 #1;
	 test_assert ("Almost Empty: should be ready", in_ready == 1);
	 test_assert ("Almost Empty 2: should be valid", out_valid == 1);

	 @(posedge clk);
	 #1;
	 test_assert ("Empty: should be ready", in_ready == 1);
	 test_assert ("Empty 2: should not be valid", out_valid == 0);

	 endtest("test_exactly_full_and_empty");
	 
      end	 
   endtask




   task test_random;
      begin
	 test_success = 1;
	 repeat(20 * DEPTH) begin
	    @(posedge clk);
	    in_valid  <= ($random(23) && 1);
	    out_ready <= ($random(23) && 1);
	 end
	 endtest("test_random");
      end
   endtask




   task empty_the_fifo;
      begin
	 in_valid <= 0;
	 out_ready <= 1;
	 repeat (DEPTH) @(posedge clk);
	 out_ready = 0;
      end
   endtask
   



   task test_assert;
      input [256:0] message;
      input         condition;
      begin
	 if (! condition) begin
	    $display("(sim)%t: %s",$time, message);
	    success = 0;
	    test_success = 0;
	 end
      end
   endtask




   task endtest;
      input [256:0] message;
      begin
	 if (test_success) begin
	    $display("(sim)%t: %-40s: Pass",$time, message);
	 end else begin
	    $display("(sim)%t: %-40s: Fail",$time, message);
	 end
	 success = success & test_success;
      end
   endtask
     
endmodule