data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:5: Cannot find include file: vc-TestRandDelaySource.v\n`include "vc-TestRandDelaySource.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/23713597/lab4/vc,data/full_repos/permissive/23713597/vc-TestRandDelaySource.v\n             data/full_repos/permissive/23713597/lab4/vc,data/full_repos/permissive/23713597/vc-TestRandDelaySource.v.v\n             data/full_repos/permissive/23713597/lab4/vc,data/full_repos/permissive/23713597/vc-TestRandDelaySource.v.sv\n             vc-TestRandDelaySource.v\n             vc-TestRandDelaySource.v.v\n             vc-TestRandDelaySource.v.sv\n             obj_dir/vc-TestRandDelaySource.v\n             obj_dir/vc-TestRandDelaySource.v.v\n             obj_dir/vc-TestRandDelaySource.v.sv\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:6: Cannot find include file: vc-TestRandDelaySink.v\n`include "vc-TestRandDelaySink.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:7: Cannot find include file: vc-TestRandDelayMem_1port.v\n`include "vc-TestRandDelayMem_1port.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:8: Cannot find include file: vc-test.v\n`include "vc-test.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:9: Cannot find include file: vc-trace.v\n`include "vc-trace.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:33: Define or directive not defined: \'`VC_MEM_REQ_MSG_NBITS\'\n  localparam c_req_nbits  = `VC_MEM_REQ_MSG_NBITS(c_opaque_nbits,c_addr_nbits,c_data_nbits);\n                            ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:33: syntax error, unexpected \',\'\n  localparam c_req_nbits  = `VC_MEM_REQ_MSG_NBITS(c_opaque_nbits,c_addr_nbits,c_data_nbits);\n                                                                ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:34: Define or directive not defined: \'`VC_MEM_RESP_MSG_NBITS\'\n  localparam c_resp_nbits = `VC_MEM_RESP_MSG_NBITS(c_opaque_nbits,c_data_nbits);\n                            ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:34: syntax error, unexpected \',\'\n  localparam c_resp_nbits = `VC_MEM_RESP_MSG_NBITS(c_opaque_nbits,c_data_nbits);\n                                                                 ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:107: Define or directive not defined: \'`VC_TRACE_BEGIN\'\n  `VC_TRACE_BEGIN\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:108: syntax error, unexpected begin\n  begin\n  ^~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:111: syntax error, unexpected \'(\', expecting IDENTIFIER\n    vc_trace.append_str( trace_str, " > " );\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:113: syntax error, unexpected \'(\', expecting IDENTIFIER\n    mem.trace( trace_str );\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:115: syntax error, unexpected \'(\', expecting IDENTIFIER\n    vc_trace.append_str( trace_str, " > " );\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:116: syntax error, unexpected \'(\', expecting IDENTIFIER\n    sink.trace( trace_str );\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:119: Define or directive not defined: \'`VC_TRACE_END\'\n  `VC_TRACE_END\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:128: Define or directive not defined: \'`VC_TEST_SUITE_BEGIN\'\n  `VC_TEST_SUITE_BEGIN( "vc-TestRandDelayMem_1port" )\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:169: Define or directive not defined: \'`VC_MEM_REQ_MSG_NBITS\'\n  reg [`VC_MEM_REQ_MSG_NBITS(8,16,32)-1:0] th_port_memreq;\n       ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:169: syntax error, unexpected \',\'\n  reg [`VC_MEM_REQ_MSG_NBITS(8,16,32)-1:0] th_port_memreq;\n                              ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:170: Define or directive not defined: \'`VC_MEM_RESP_MSG_NBITS\'\n  reg [`VC_MEM_RESP_MSG_NBITS(8,32)-1:0]   th_port_memresp;\n       ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:170: syntax error, unexpected \',\'\n  reg [`VC_MEM_RESP_MSG_NBITS(8,32)-1:0]   th_port_memresp;\n                               ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:176: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_NBITS\'\n    input [`VC_MEM_REQ_MSG_TYPE_NBITS(8,16,32)-1:0]   memreq_type,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:176: syntax error, unexpected \',\'\n    input [`VC_MEM_REQ_MSG_TYPE_NBITS(8,16,32)-1:0]   memreq_type,\n                                       ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:177: Define or directive not defined: \'`VC_MEM_REQ_MSG_OPAQUE_NBITS\'\n    input [`VC_MEM_REQ_MSG_OPAQUE_NBITS(8,16,32)-1:0] memreq_opaque,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:178: Define or directive not defined: \'`VC_MEM_REQ_MSG_ADDR_NBITS\'\n    input [`VC_MEM_REQ_MSG_ADDR_NBITS(8,16,32)-1:0]   memreq_addr,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:179: Define or directive not defined: \'`VC_MEM_REQ_MSG_LEN_NBITS\'\n    input [`VC_MEM_REQ_MSG_LEN_NBITS(8,16,32)-1:0]    memreq_len,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:180: Define or directive not defined: \'`VC_MEM_REQ_MSG_DATA_NBITS\'\n    input [`VC_MEM_REQ_MSG_DATA_NBITS(8,16,32)-1:0]   memreq_data,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:182: Define or directive not defined: \'`VC_MEM_RESP_MSG_TYPE_NBITS\'\n    input [`VC_MEM_RESP_MSG_TYPE_NBITS(8,32)-1:0]     memresp_type,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:183: Define or directive not defined: \'`VC_MEM_RESP_MSG_OPAQUE_NBITS\'\n    input [`VC_MEM_RESP_MSG_OPAQUE_NBITS(8,32)-1:0]   memresp_opaque,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:184: Define or directive not defined: \'`VC_MEM_RESP_MSG_LEN_NBITS\'\n    input [`VC_MEM_RESP_MSG_LEN_NBITS(8,32)-1:0]      memresp_len,\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:185: Define or directive not defined: \'`VC_MEM_RESP_MSG_DATA_NBITS\'\n    input [`VC_MEM_RESP_MSG_DATA_NBITS(8,32)-1:0]     memresp_data\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:188: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_FIELD\'\n    th_port_memreq[`VC_MEM_REQ_MSG_TYPE_FIELD(8,16,32)]   = memreq_type;\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:189: Define or directive not defined: \'`VC_MEM_REQ_MSG_OPAQUE_FIELD\'\n    th_port_memreq[`VC_MEM_REQ_MSG_OPAQUE_FIELD(8,16,32)] = memreq_opaque;\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:190: Define or directive not defined: \'`VC_MEM_REQ_MSG_ADDR_FIELD\'\n    th_port_memreq[`VC_MEM_REQ_MSG_ADDR_FIELD(8,16,32)]   = memreq_addr;\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:191: Define or directive not defined: \'`VC_MEM_REQ_MSG_LEN_FIELD\'\n    th_port_memreq[`VC_MEM_REQ_MSG_LEN_FIELD(8,16,32)]    = memreq_len;\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:192: Define or directive not defined: \'`VC_MEM_REQ_MSG_DATA_FIELD\'\n    th_port_memreq[`VC_MEM_REQ_MSG_DATA_FIELD(8,16,32)]   = memreq_data;\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:194: Define or directive not defined: \'`VC_MEM_RESP_MSG_TYPE_FIELD\'\n    th_port_memresp[`VC_MEM_RESP_MSG_TYPE_FIELD(8,32)]    = memresp_type;\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:195: Define or directive not defined: \'`VC_MEM_RESP_MSG_OPAQUE_FIELD\'\n    th_port_memresp[`VC_MEM_RESP_MSG_OPAQUE_FIELD(8,32)]  = memresp_opaque;\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:196: Define or directive not defined: \'`VC_MEM_RESP_MSG_LEN_FIELD\'\n    th_port_memresp[`VC_MEM_RESP_MSG_LEN_FIELD(8,32)]     = memresp_len;\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:197: Define or directive not defined: \'`VC_MEM_RESP_MSG_DATA_FIELD\'\n    th_port_memresp[`VC_MEM_RESP_MSG_DATA_FIELD(8,32)]    = memresp_data;\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:199: syntax error, unexpected \'.\', expecting IDENTIFIER\n    th.src.src.m[index]   = th_port_memreq;\n          ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:200: syntax error, unexpected \'.\', expecting IDENTIFIER\n    th.sink.sink.m[index] = th_port_memresp;\n           ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:206: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_READ\'\n  localparam c_req_rd  = `VC_MEM_REQ_MSG_TYPE_READ;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:207: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_WRITE\'\n  localparam c_req_wr  = `VC_MEM_REQ_MSG_TYPE_WRITE;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:207: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam c_req_wr  = `VC_MEM_REQ_MSG_TYPE_WRITE;\n                                                   ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:208: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_WRITE_INIT\'\n  localparam c_req_wn  = `VC_MEM_REQ_MSG_TYPE_WRITE_INIT;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:208: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam c_req_wn  = `VC_MEM_REQ_MSG_TYPE_WRITE_INIT;\n                                                        ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:209: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_AMO_ADD\'\n  localparam c_req_ad  = `VC_MEM_REQ_MSG_TYPE_AMO_ADD;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:209: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  localparam c_req_ad  = `VC_MEM_REQ_MSG_TYPE_AMO_ADD;\n                                                     ^\n%Error: data/full_repos/permissive/23713597/lab4/vc/vc-TestRandDelayMem_1port.t.v:210: Define or directive not defined: \'`VC_MEM_REQ_MSG_TYPE_AMO_AND\'\n  localparam c_req_an  = `VC_MEM_REQ_MSG_TYPE_AMO_AND;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module top;
  `VC_TEST_SUITE_BEGIN( "vc-TestRandDelayMem_1port" )





  reg         th_reset = 1;
  reg         th_mem_clear;
  reg  [31:0] th_src_max_delay;
  reg  [31:0] th_mem_max_delay;
  reg  [31:0] th_sink_max_delay;
  wire        th_done;

  TestHarness th
  (
    .clk            (clk),
    .reset          (th_reset),
    .mem_clear      (th_mem_clear),
    .src_max_delay  (th_src_max_delay),
    .mem_max_delay  (th_mem_max_delay),
    .sink_max_delay (th_sink_max_delay),
    .done           (th_done)
  );



  task init_rand_delays
  (
    input [31:0] src_max_delay,
    input [31:0] mem_max_delay,
    input [31:0] sink_max_delay
  );
  begin
    th_src_max_delay  = src_max_delay;
    th_mem_max_delay  = mem_max_delay;
    th_sink_max_delay = sink_max_delay;
  end
  endtask



  reg [`VC_MEM_REQ_MSG_NBITS(8,16,32)-1:0] th_port_memreq;
  reg [`VC_MEM_RESP_MSG_NBITS(8,32)-1:0]   th_port_memresp;

  task init_port
  (
    input [1023:0] index,

    input [`VC_MEM_REQ_MSG_TYPE_NBITS(8,16,32)-1:0]   memreq_type,
    input [`VC_MEM_REQ_MSG_OPAQUE_NBITS(8,16,32)-1:0] memreq_opaque,
    input [`VC_MEM_REQ_MSG_ADDR_NBITS(8,16,32)-1:0]   memreq_addr,
    input [`VC_MEM_REQ_MSG_LEN_NBITS(8,16,32)-1:0]    memreq_len,
    input [`VC_MEM_REQ_MSG_DATA_NBITS(8,16,32)-1:0]   memreq_data,

    input [`VC_MEM_RESP_MSG_TYPE_NBITS(8,32)-1:0]     memresp_type,
    input [`VC_MEM_RESP_MSG_OPAQUE_NBITS(8,32)-1:0]   memresp_opaque,
    input [`VC_MEM_RESP_MSG_LEN_NBITS(8,32)-1:0]      memresp_len,
    input [`VC_MEM_RESP_MSG_DATA_NBITS(8,32)-1:0]     memresp_data
  );
  begin
    th_port_memreq[`VC_MEM_REQ_MSG_TYPE_FIELD(8,16,32)]   = memreq_type;
    th_port_memreq[`VC_MEM_REQ_MSG_OPAQUE_FIELD(8,16,32)] = memreq_opaque;
    th_port_memreq[`VC_MEM_REQ_MSG_ADDR_FIELD(8,16,32)]   = memreq_addr;
    th_port_memreq[`VC_MEM_REQ_MSG_LEN_FIELD(8,16,32)]    = memreq_len;
    th_port_memreq[`VC_MEM_REQ_MSG_DATA_FIELD(8,16,32)]   = memreq_data;

    th_port_memresp[`VC_MEM_RESP_MSG_TYPE_FIELD(8,32)]    = memresp_type;
    th_port_memresp[`VC_MEM_RESP_MSG_OPAQUE_FIELD(8,32)]  = memresp_opaque;
    th_port_memresp[`VC_MEM_RESP_MSG_LEN_FIELD(8,32)]     = memresp_len;
    th_port_memresp[`VC_MEM_RESP_MSG_DATA_FIELD(8,32)]    = memresp_data;

    th.src.src.m[index]   = th_port_memreq;
    th.sink.sink.m[index] = th_port_memresp;
  end
  endtask



  localparam c_req_rd  = `VC_MEM_REQ_MSG_TYPE_READ;
  localparam c_req_wr  = `VC_MEM_REQ_MSG_TYPE_WRITE;
  localparam c_req_wn  = `VC_MEM_REQ_MSG_TYPE_WRITE_INIT;
  localparam c_req_ad  = `VC_MEM_REQ_MSG_TYPE_AMO_ADD;
  localparam c_req_an  = `VC_MEM_REQ_MSG_TYPE_AMO_AND;
  localparam c_req_ao  = `VC_MEM_REQ_MSG_TYPE_AMO_OR;

  localparam c_resp_rd = `VC_MEM_RESP_MSG_TYPE_READ;
  localparam c_resp_wr = `VC_MEM_RESP_MSG_TYPE_WRITE;
  localparam c_resp_wn = `VC_MEM_RESP_MSG_TYPE_WRITE_INIT;
  localparam c_resp_ad = `VC_MEM_RESP_MSG_TYPE_AMO_ADD;
  localparam c_resp_an = `VC_MEM_RESP_MSG_TYPE_AMO_AND;
  localparam c_resp_ao = `VC_MEM_RESP_MSG_TYPE_AMO_OR;



  task init_common;
  begin


    #5;   th_mem_clear = 1'b1;
    #20;  th_mem_clear = 1'b0;






    init_port( 0,  c_req_wr, 8'h00, 16'h0000, 2'd0, 32'h0a0b0c0d, c_resp_wr, 8'h00, 2'd0, 32'h???????? );
    init_port( 1,  c_req_wn, 8'h01, 16'h0004, 2'd0, 32'h0e0f0102, c_resp_wn, 8'h01, 2'd0, 32'h???????? );
    init_port( 2,  c_req_rd, 8'h02, 16'h0000, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h02, 2'd0, 32'h0a0b0c0d );
    init_port( 3,  c_req_rd, 8'h03, 16'h0004, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h03, 2'd0, 32'h0e0f0102 );



    init_port( 4,  c_req_wr, 8'h04, 16'h0008, 2'd0, 32'h0a0b0c0d, c_resp_wr, 8'h04, 2'd0, 32'h???????? );
    init_port( 5,  c_req_wr, 8'h05, 16'h0008, 2'd1, 32'hdeadbeef, c_resp_wr, 8'h05, 2'd1, 32'h???????? );
    init_port( 6,  c_req_rd, 8'h06, 16'h0008, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h06, 2'd1, 32'h??????ef );
    init_port( 7,  c_req_rd, 8'h07, 16'h0009, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h07, 2'd1, 32'h??????0c );
    init_port( 8,  c_req_rd, 8'h08, 16'h000a, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h08, 2'd1, 32'h??????0b );
    init_port( 9,  c_req_rd, 8'h09, 16'h000b, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h09, 2'd1, 32'h??????0a );



    init_port(10,  c_req_wr, 8'h0a, 16'h000c, 2'd0, 32'h01020304, c_resp_wr, 8'h0a, 2'd0, 32'h???????? );
    init_port(11,  c_req_wr, 8'h0b, 16'h000c, 2'd2, 32'hdeadbeef, c_resp_wr, 8'h0b, 2'd2, 32'h???????? );
    init_port(12,  c_req_rd, 8'h0c, 16'h000c, 2'd2, 32'hxxxxxxxx, c_resp_rd, 8'h0c, 2'd2, 32'h????beef );
    init_port(13,  c_req_rd, 8'h0d, 16'h000e, 2'd2, 32'hxxxxxxxx, c_resp_rd, 8'h0d, 2'd2, 32'h????0102 );



    init_port(14,  c_req_wr, 8'h0e, 16'h0014, 2'd0, 32'ha0b0c0d0, c_resp_wr, 8'h0e, 2'd0, 32'h???????? );
    init_port(15,  c_req_wr, 8'h0f, 16'h1014, 2'd0, 32'he0102030, c_resp_wr, 8'h0f, 2'd0, 32'h???????? );
    init_port(16,  c_req_rd, 8'h00, 16'h0014, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h00, 2'd0, 32'he0102030 );
    init_port(17,  c_req_rd, 8'h01, 16'h1014, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h01, 2'd0, 32'he0102030 );



    init_port(18,  c_req_ao, 8'h02, 16'h0000, 2'd0, 32'hf0f0f0f0, c_resp_ao, 8'h02, 2'd0, 32'h0a0b0c0d );
    init_port(19,  c_req_rd, 8'h03, 16'h0000, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h03, 2'd0, 32'hfafbfcfd );
    init_port(20,  c_req_ad, 8'h04, 16'h0004, 2'd0, 32'h00000fff, c_resp_ad, 8'h04, 2'd0, 32'h0e0f0102 );
    init_port(21,  c_req_rd, 8'h05, 16'h0004, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h05, 2'd0, 32'h0e0f1101 );
    init_port(22,  c_req_an, 8'h06, 16'h0000, 2'd0, 32'h33333333, c_resp_an, 8'h06, 2'd0, 32'hfafbfcfd );
    init_port(23,  c_req_rd, 8'h07, 16'h0000, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h07, 2'd0, 32'h32333031 );

  end
  endtask



  task run_test;
  begin
    #5;   th_reset = 1'b1;
    #20;  th_reset = 1'b0;

    while ( !th_done && (th.vc_trace.cycles < 500) ) begin
      th.display_trace();
      #10;
    end

    `VC_TEST_NET( th_done, 1'b1 );
  end
  endtask





  `VC_TEST_CASE_BEGIN( 1, "src delay = 0, mem delay = 0, sink delay = 0" )
  begin
    init_rand_delays( 0, 0, 0 );
    init_common;
    run_test;
  end
  `VC_TEST_CASE_END





  `VC_TEST_CASE_BEGIN( 2, "src delay = 3, mem delay = 0, sink delay = 10" )
  begin
    init_rand_delays( 3, 0, 10 );
    init_common;
    run_test;
  end
  `VC_TEST_CASE_END





  `VC_TEST_CASE_BEGIN( 3, "src delay = 10, mem delay = 0, sink delay = 3" )
  begin
    init_rand_delays( 10, 0, 3 );
    init_common;
    run_test;
  end
  `VC_TEST_CASE_END





  `VC_TEST_CASE_BEGIN( 4, "src delay = 0, mem delay = 5, sink delay = 0" )
  begin
    init_rand_delays( 0, 5, 0 );
    init_common;
    run_test;
  end
  `VC_TEST_CASE_END





  `VC_TEST_CASE_BEGIN( 5, "src delay = 3, mem delay = 5, sink delay = 10" )
  begin
    init_rand_delays( 3, 5, 10 );
    init_common;
    run_test;
  end
  `VC_TEST_CASE_END





  `VC_TEST_CASE_BEGIN( 6, "src delay = 10, mem delay = 5, sink delay = 3" )
  begin
    init_rand_delays( 10, 5, 3 );
    init_common;
    run_test;
  end
  `VC_TEST_CASE_END

  `VC_TEST_SUITE_END
endmodule
module top;

  `VC_TEST_SUITE_BEGIN( "vc-TestRandDelayMem_1port" )





  reg         th_reset = 1;
  reg         th_mem_clear;
  reg  [31:0] th_src_max_delay;
  reg  [31:0] th_mem_max_delay;
  reg  [31:0] th_sink_max_delay;
  wire        th_done;

  TestHarness th
  (
    .clk            (clk),
    .reset          (th_reset),
    .mem_clear      (th_mem_clear),
    .src_max_delay  (th_src_max_delay),
    .mem_max_delay  (th_mem_max_delay),
    .sink_max_delay (th_sink_max_delay),
    .done           (th_done)
  );



  task init_rand_delays
  (
    input [31:0] src_max_delay,
    input [31:0] mem_max_delay,
    input [31:0] sink_max_delay
  );
  begin
    th_src_max_delay  = src_max_delay;
    th_mem_max_delay  = mem_max_delay;
    th_sink_max_delay = sink_max_delay;
  end
  endtask



  reg [`VC_MEM_REQ_MSG_NBITS(8,16,32)-1:0] th_port_memreq;
  reg [`VC_MEM_RESP_MSG_NBITS(8,32)-1:0]   th_port_memresp;

  task init_port
  (
    input [1023:0] index,

    input [`VC_MEM_REQ_MSG_TYPE_NBITS(8,16,32)-1:0]   memreq_type,
    input [`VC_MEM_REQ_MSG_OPAQUE_NBITS(8,16,32)-1:0] memreq_opaque,
    input [`VC_MEM_REQ_MSG_ADDR_NBITS(8,16,32)-1:0]   memreq_addr,
    input [`VC_MEM_REQ_MSG_LEN_NBITS(8,16,32)-1:0]    memreq_len,
    input [`VC_MEM_REQ_MSG_DATA_NBITS(8,16,32)-1:0]   memreq_data,

    input [`VC_MEM_RESP_MSG_TYPE_NBITS(8,32)-1:0]     memresp_type,
    input [`VC_MEM_RESP_MSG_OPAQUE_NBITS(8,32)-1:0]   memresp_opaque,
    input [`VC_MEM_RESP_MSG_LEN_NBITS(8,32)-1:0]      memresp_len,
    input [`VC_MEM_RESP_MSG_DATA_NBITS(8,32)-1:0]     memresp_data
  );
  begin
    th_port_memreq[`VC_MEM_REQ_MSG_TYPE_FIELD(8,16,32)]   = memreq_type;
    th_port_memreq[`VC_MEM_REQ_MSG_OPAQUE_FIELD(8,16,32)] = memreq_opaque;
    th_port_memreq[`VC_MEM_REQ_MSG_ADDR_FIELD(8,16,32)]   = memreq_addr;
    th_port_memreq[`VC_MEM_REQ_MSG_LEN_FIELD(8,16,32)]    = memreq_len;
    th_port_memreq[`VC_MEM_REQ_MSG_DATA_FIELD(8,16,32)]   = memreq_data;

    th_port_memresp[`VC_MEM_RESP_MSG_TYPE_FIELD(8,32)]    = memresp_type;
    th_port_memresp[`VC_MEM_RESP_MSG_OPAQUE_FIELD(8,32)]  = memresp_opaque;
    th_port_memresp[`VC_MEM_RESP_MSG_LEN_FIELD(8,32)]     = memresp_len;
    th_port_memresp[`VC_MEM_RESP_MSG_DATA_FIELD(8,32)]    = memresp_data;

    th.src.src.m[index]   = th_port_memreq;
    th.sink.sink.m[index] = th_port_memresp;
  end
  endtask



  localparam c_req_rd  = `VC_MEM_REQ_MSG_TYPE_READ;
  localparam c_req_wr  = `VC_MEM_REQ_MSG_TYPE_WRITE;
  localparam c_req_wn  = `VC_MEM_REQ_MSG_TYPE_WRITE_INIT;
  localparam c_req_ad  = `VC_MEM_REQ_MSG_TYPE_AMO_ADD;
  localparam c_req_an  = `VC_MEM_REQ_MSG_TYPE_AMO_AND;
  localparam c_req_ao  = `VC_MEM_REQ_MSG_TYPE_AMO_OR;

  localparam c_resp_rd = `VC_MEM_RESP_MSG_TYPE_READ;
  localparam c_resp_wr = `VC_MEM_RESP_MSG_TYPE_WRITE;
  localparam c_resp_wn = `VC_MEM_RESP_MSG_TYPE_WRITE_INIT;
  localparam c_resp_ad = `VC_MEM_RESP_MSG_TYPE_AMO_ADD;
  localparam c_resp_an = `VC_MEM_RESP_MSG_TYPE_AMO_AND;
  localparam c_resp_ao = `VC_MEM_RESP_MSG_TYPE_AMO_OR;



  task init_common;
  begin


    #5;   th_mem_clear = 1'b1;
    #20;  th_mem_clear = 1'b0;






    init_port( 0,  c_req_wr, 8'h00, 16'h0000, 2'd0, 32'h0a0b0c0d, c_resp_wr, 8'h00, 2'd0, 32'h???????? );
    init_port( 1,  c_req_wn, 8'h01, 16'h0004, 2'd0, 32'h0e0f0102, c_resp_wn, 8'h01, 2'd0, 32'h???????? );
    init_port( 2,  c_req_rd, 8'h02, 16'h0000, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h02, 2'd0, 32'h0a0b0c0d );
    init_port( 3,  c_req_rd, 8'h03, 16'h0004, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h03, 2'd0, 32'h0e0f0102 );



    init_port( 4,  c_req_wr, 8'h04, 16'h0008, 2'd0, 32'h0a0b0c0d, c_resp_wr, 8'h04, 2'd0, 32'h???????? );
    init_port( 5,  c_req_wr, 8'h05, 16'h0008, 2'd1, 32'hdeadbeef, c_resp_wr, 8'h05, 2'd1, 32'h???????? );
    init_port( 6,  c_req_rd, 8'h06, 16'h0008, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h06, 2'd1, 32'h??????ef );
    init_port( 7,  c_req_rd, 8'h07, 16'h0009, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h07, 2'd1, 32'h??????0c );
    init_port( 8,  c_req_rd, 8'h08, 16'h000a, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h08, 2'd1, 32'h??????0b );
    init_port( 9,  c_req_rd, 8'h09, 16'h000b, 2'd1, 32'hxxxxxxxx, c_resp_rd, 8'h09, 2'd1, 32'h??????0a );



    init_port(10,  c_req_wr, 8'h0a, 16'h000c, 2'd0, 32'h01020304, c_resp_wr, 8'h0a, 2'd0, 32'h???????? );
    init_port(11,  c_req_wr, 8'h0b, 16'h000c, 2'd2, 32'hdeadbeef, c_resp_wr, 8'h0b, 2'd2, 32'h???????? );
    init_port(12,  c_req_rd, 8'h0c, 16'h000c, 2'd2, 32'hxxxxxxxx, c_resp_rd, 8'h0c, 2'd2, 32'h????beef );
    init_port(13,  c_req_rd, 8'h0d, 16'h000e, 2'd2, 32'hxxxxxxxx, c_resp_rd, 8'h0d, 2'd2, 32'h????0102 );



    init_port(14,  c_req_wr, 8'h0e, 16'h0014, 2'd0, 32'ha0b0c0d0, c_resp_wr, 8'h0e, 2'd0, 32'h???????? );
    init_port(15,  c_req_wr, 8'h0f, 16'h1014, 2'd0, 32'he0102030, c_resp_wr, 8'h0f, 2'd0, 32'h???????? );
    init_port(16,  c_req_rd, 8'h00, 16'h0014, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h00, 2'd0, 32'he0102030 );
    init_port(17,  c_req_rd, 8'h01, 16'h1014, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h01, 2'd0, 32'he0102030 );



    init_port(18,  c_req_ao, 8'h02, 16'h0000, 2'd0, 32'hf0f0f0f0, c_resp_ao, 8'h02, 2'd0, 32'h0a0b0c0d );
    init_port(19,  c_req_rd, 8'h03, 16'h0000, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h03, 2'd0, 32'hfafbfcfd );
    init_port(20,  c_req_ad, 8'h04, 16'h0004, 2'd0, 32'h00000fff, c_resp_ad, 8'h04, 2'd0, 32'h0e0f0102 );
    init_port(21,  c_req_rd, 8'h05, 16'h0004, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h05, 2'd0, 32'h0e0f1101 );
    init_port(22,  c_req_an, 8'h06, 16'h0000, 2'd0, 32'h33333333, c_resp_an, 8'h06, 2'd0, 32'hfafbfcfd );
    init_port(23,  c_req_rd, 8'h07, 16'h0000, 2'd0, 32'hxxxxxxxx, c_resp_rd, 8'h07, 2'd0, 32'h32333031 );

  end
  endtask



  task run_test;
  begin
    #5;   th_reset = 1'b1;
    #20;  th_reset = 1'b0;

    while ( !th_done && (th.vc_trace.cycles < 500) ) begin
      th.display_trace();
      #10;
    end

    `VC_TEST_NET( th_done, 1'b1 );
  end
  endtask





  `VC_TEST_CASE_BEGIN( 1, "src delay = 0, mem delay = 0, sink delay = 0" )
  begin
    init_rand_delays( 0, 0, 0 );
    init_common;
    run_test;
  end
  `VC_TEST_CASE_END





  `VC_TEST_CASE_BEGIN( 2, "src delay = 3, mem delay = 0, sink delay = 10" )
  begin
    init_rand_delays( 3, 0, 10 );
    init_common;
    run_test;
  end
  `VC_TEST_CASE_END





  `VC_TEST_CASE_BEGIN( 3, "src delay = 10, mem delay = 0, sink delay = 3" )
  begin
    init_rand_delays( 10, 0, 3 );
    init_common;
    run_test;
  end
  `VC_TEST_CASE_END





  `VC_TEST_CASE_BEGIN( 4, "src delay = 0, mem delay = 5, sink delay = 0" )
  begin
    init_rand_delays( 0, 5, 0 );
    init_common;
    run_test;
  end
  `VC_TEST_CASE_END





  `VC_TEST_CASE_BEGIN( 5, "src delay = 3, mem delay = 5, sink delay = 10" )
  begin
    init_rand_delays( 3, 5, 10 );
    init_common;
    run_test;
  end
  `VC_TEST_CASE_END





  `VC_TEST_CASE_BEGIN( 6, "src delay = 10, mem delay = 5, sink delay = 3" )
  begin
    init_rand_delays( 10, 5, 3 );
    init_common;
    run_test;
  end
  `VC_TEST_CASE_END

  `VC_TEST_SUITE_END
endmodule