data/full_repos/permissive/20270692/labs/lab5/half_adder.v
data/verilator_xmls/0c9c0a2d-d818-4771-8274-914b68801161.xml
module half_adder(x, y, s, c);

  input x, y;

  output s, c;
  wire s, c;

  assign s=x^y;
  assign c=x&y;

endmodule
module half_adder(x, y, s, c);


  input x, y;

  output s, c;
  wire s, c;

  assign s=x^y;
  assign c=x&y;

endmodule