data/full_repos/permissive/211316121/lab5_1/FlipFlop.v
data/verilator_xmls/d8ef6967-f9c6-4ff4-9a6d-83398a96c8b5.xml
module JKFF(
	input j,
	input k,
	input clk,
	input clr,
	input set,
	output reg q,
	output nq
);

always@(posedge clk,posedge set,posedge clr)
begin
    if(set)
        q<=1;
    else if(clr)
        q<=0;
    else
    begin
        case({j,k})
                'b00:;
                'b10:q<=1;
                'b01:q<=0;
                'b11:q<=~q;
        endcase
    end
end

assign nq=~q;

endmodule
module JKFF(
	input j,
	input k,
	input clk,
	input clr,
	input set,
	output reg q,
	output nq
);


always@(posedge clk,posedge set,posedge clr)
begin
    if(set)
        q<=1;
    else if(clr)
        q<=0;
    else
    begin
        case({j,k})
                'b00:;
                'b10:q<=1;
                'b01:q<=0;
                'b11:q<=~q;
        endcase
    end
end

assign nq=~q;

endmodule