data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PCIF.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PCIF.v:3: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/src/cpu/core/stage/pc,data/full_repos/permissive/201275379/bus.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/pc,data/full_repos/permissive/201275379/bus.v.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/pc,data/full_repos/permissive/201275379/bus.v.sv\n             bus.v\n             bus.v.v\n             bus.v.sv\n             obj_dir/bus.v\n             obj_dir/bus.v.v\n             obj_dir/bus.v.sv\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PCIF.v:4: Cannot find include file: exception.v\n`include "exception.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PCIF.v:5: Cannot find include file: branch.v\n`include "branch.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PCIF.v:14: Define or directive not defined: \'`GHR_BUS\'\n  input   [`GHR_BUS]  pht_index_in,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PCIF.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  input   [`GHR_BUS]  pht_index_in,\n                   ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PCIF.v:15: Define or directive not defined: \'`ADDR_BUS\'\n  input   [`ADDR_BUS] pc_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PCIF.v:17: Define or directive not defined: \'`GHR_BUS\'\n  output  [`GHR_BUS]  pht_index_out,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PCIF.v:18: Define or directive not defined: \'`ADDR_BUS\'\n  output  [`ADDR_BUS] pc_out\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PCIF.v:27: Define or directive not defined: \'`GHR_WIDTH\'\n  PipelineDeliver #(`GHR_WIDTH) ff_pht_index(\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PCIF.v:33: Define or directive not defined: \'`ADDR_BUS_WIDTH\'\n  PipelineDeliver #(`ADDR_BUS_WIDTH, `INVALID_PC) ff_pc(\n                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/pc/PCIF.v:33: Define or directive not defined: \'`INVALID_PC\'\n  PipelineDeliver #(`ADDR_BUS_WIDTH, `INVALID_PC) ff_pc(\n                                     ^~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n'
module PCIF(
  input               clk,
  input               rst,
  input               flush,
  input               stall_current_stage,
  input               stall_next_stage,
  input               is_branch_taken_in,
  input   [`GHR_BUS]  pht_index_in,
  input   [`ADDR_BUS] pc_in,
  output              is_branch_taken_out,
  output  [`GHR_BUS]  pht_index_out,
  output  [`ADDR_BUS] pc_out
);

  PipelineDeliver #(1) ff_is_branch_taken(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    is_branch_taken_in, is_branch_taken_out
  );

  PipelineDeliver #(`GHR_WIDTH) ff_pht_index(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    pht_index_in, pht_index_out
  );

  PipelineDeliver #(`ADDR_BUS_WIDTH, `INVALID_PC) ff_pc(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    pc_in, pc_out
  );

endmodule
module PCIF(
  input               clk,
  input               rst,
  input               flush,
  input               stall_current_stage,
  input               stall_next_stage,
  input               is_branch_taken_in,
  input   [`GHR_BUS]  pht_index_in,
  input   [`ADDR_BUS] pc_in,
  output              is_branch_taken_out,
  output  [`GHR_BUS]  pht_index_out,
  output  [`ADDR_BUS] pc_out
);


  PipelineDeliver #(1) ff_is_branch_taken(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    is_branch_taken_in, is_branch_taken_out
  );

  PipelineDeliver #(`GHR_WIDTH) ff_pht_index(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    pht_index_in, pht_index_out
  );

  PipelineDeliver #(`ADDR_BUS_WIDTH, `INVALID_PC) ff_pc(
    clk, rst, flush,
    stall_current_stage, stall_next_stage,
    pc_in, pc_out
  );

endmodule