data/full_repos/permissive/160408009/components/COREDDR_TIP/1.6.106/rtl/vlog/core/PHY_SIG_MOD.v
data/verilator_xmls/ff74c011-53a7-4f72-92bf-2280fb021174.xml
module PHY_SIG_MOD( SCLK,
                    reset_n,
                    dfi_rdlvl_en,
                    dfi_rdlvl_gate_en,
                    dfi_wrdata_en_p0,
                    dfi_wrdata_en_p1,
                    dfi_wrdata_en_p2,
                    dfi_wrdata_en_p3,
                    dfi_wrlvl_en,
                    trn_delay_line_sel,
                    iog_oe_p0,
                    iog_oe_p1,
                    iog_oe_p2,
                    iog_oe_p3,
                    dqs_oe_p0,
                    dqs_oe_p1,
                    dqs_oe_p2,
                    dqs_oe_p3,

                    dm_oe_p0,
                    dm_oe_p1,
                    dm_oe_p2,
                    dm_oe_p3,
                    dfi_rddata_cs_0_n_p0,
                    dfi_rddata_cs_0_n_p1,
                    dfi_rddata_cs_0_n_p2,
                    dfi_rddata_cs_0_n_p3,
                    dfi_rddata_cs_1_n_p0,
                    dfi_rddata_cs_1_n_p1,
                    dfi_rddata_cs_1_n_p2,
                    dfi_rddata_cs_1_n_p3,
                    dfi_wrdata_cs_0_n_p0,
                    dfi_wrdata_cs_0_n_p1,
                    dfi_wrdata_cs_0_n_p2,
                    dfi_wrdata_cs_0_n_p3,
                    dfi_wrdata_cs_1_n_p0,
                    dfi_wrdata_cs_1_n_p1,
                    dfi_wrdata_cs_1_n_p2,
                    dfi_wrdata_cs_1_n_p3,
                    dfi_rddata_cs_0_n,
                    dfi_rddata_cs_1_n,
                    apb_ctrl_chip_sel,
                    apb_iog_on,
                    odt_dyn_lane,
                    dfi_rddata_en_p3,
                    iog_rddata_en_p0_p,
                    select_rank_1_gt,
                    select_rank_1,
                    dfi_init_complete,



                    iog_dq_txdata_in,
                    iog_dq_txdata_out,
                    iog_dm_txdata_in,
                    iog_dm_txdata_out,
                    write_callibration_offset
          
          
					);

parameter IOG_DQS_LANES = 9;
parameter HOLD_ODT_CYCLES = 2;

input          SCLK;
input          reset_n;



input          dfi_rdlvl_en;
input          dfi_rdlvl_gate_en;
input          dfi_wrdata_en_p0;
input          dfi_wrdata_en_p1;
input          dfi_wrdata_en_p2;
input          dfi_wrdata_en_p3;
input          dfi_wrlvl_en;



output [IOG_DQS_LANES-1:0]       trn_delay_line_sel;
output [IOG_DQS_LANES-1:0]       iog_oe_p0;
output [IOG_DQS_LANES-1:0]       iog_oe_p1;
output [IOG_DQS_LANES-1:0]       iog_oe_p2;
output [IOG_DQS_LANES-1:0]       iog_oe_p3;
output [IOG_DQS_LANES-1:0]       dqs_oe_p0;
output [IOG_DQS_LANES-1:0]       dqs_oe_p1;
output [IOG_DQS_LANES-1:0]       dqs_oe_p2;
output [IOG_DQS_LANES-1:0]       dqs_oe_p3;
output [IOG_DQS_LANES-1:0]       dm_oe_p0;
output [IOG_DQS_LANES-1:0]       dm_oe_p1;
output [IOG_DQS_LANES-1:0]       dm_oe_p2;
output [IOG_DQS_LANES-1:0]       dm_oe_p3;

reg    [IOG_DQS_LANES-1:0]       iog_oe_p0;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p1;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p2;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p3;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p0;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p1;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p2;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p3;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p0;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p1;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p2;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p3;

input  [IOG_DQS_LANES*64-1:0]    iog_dq_txdata_in;
output [IOG_DQS_LANES*64-1:0]    iog_dq_txdata_out;
reg    [IOG_DQS_LANES*64-1:0]    iog_dq_txdata_out;
input  [IOG_DQS_LANES*8-1:0]     iog_dm_txdata_in;
output [IOG_DQS_LANES*8-1:0]     iog_dm_txdata_out;
reg    [IOG_DQS_LANES*8-1:0]     iog_dm_txdata_out;



output          dfi_rddata_cs_0_n;
output          dfi_rddata_cs_1_n;

input          dfi_rddata_cs_0_n_p0;
input          dfi_rddata_cs_0_n_p1;
input          dfi_rddata_cs_0_n_p2;
input          dfi_rddata_cs_0_n_p3;
input          dfi_rddata_cs_1_n_p0;
input          dfi_rddata_cs_1_n_p1;
input          dfi_rddata_cs_1_n_p2;
input          dfi_rddata_cs_1_n_p3;

input          dfi_wrdata_cs_0_n_p0;
input          dfi_wrdata_cs_0_n_p1;
input          dfi_wrdata_cs_0_n_p2;
input          dfi_wrdata_cs_0_n_p3;
input          dfi_wrdata_cs_1_n_p0;
input          dfi_wrdata_cs_1_n_p1;
input          dfi_wrdata_cs_1_n_p2;
input          dfi_wrdata_cs_1_n_p3;





input apb_ctrl_chip_sel;
input apb_iog_on;


output 	[IOG_DQS_LANES-1:0] 	odt_dyn_lane;
wire 	[IOG_DQS_LANES-1:0] 	odt_dyn_lane;
input         					dfi_rddata_en_p3;
input  [IOG_DQS_LANES-1:0] 		iog_rddata_en_p0_p;
reg  [HOLD_ODT_CYCLES-1:0] 		odt_dyn_on [IOG_DQS_LANES-1:0];

input select_rank_1_gt;
output select_rank_1;
wire select_rank_1;


input dfi_init_complete;


input [IOG_DQS_LANES*3-1:0]          write_callibration_offset;





wire   [IOG_DQS_LANES-1:0]       iog_oe_p0_internal;
wire   [IOG_DQS_LANES-1:0]       iog_oe_p1_internal;
wire   [IOG_DQS_LANES-1:0]       iog_oe_p2_internal;
wire   [IOG_DQS_LANES-1:0]       iog_oe_p3_internal;
wire   [IOG_DQS_LANES-1:0]       dqs_oe_p0_internal;
wire   [IOG_DQS_LANES-1:0]       dqs_oe_p1_internal;
wire   [IOG_DQS_LANES-1:0]       dqs_oe_p2_internal;
wire   [IOG_DQS_LANES-1:0]       dqs_oe_p3_internal;
wire   [IOG_DQS_LANES-1:0]       dm_oe_p0_internal;
wire   [IOG_DQS_LANES-1:0]       dm_oe_p1_internal;
wire   [IOG_DQS_LANES-1:0]       dm_oe_p2_internal;
wire   [IOG_DQS_LANES-1:0]       dm_oe_p3_internal;


reg    [IOG_DQS_LANES-1:0]       iog_oe_p0_reg;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p1_reg;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p2_reg;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p3_reg;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p0_reg;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p1_reg;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p2_reg;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p3_reg;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p0_reg;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p1_reg;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p2_reg;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p3_reg;

reg    [IOG_DQS_LANES-1:0]       iog_oe_p0_reg_2;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p1_reg_2;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p2_reg_2;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p3_reg_2;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p0_reg_2;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p1_reg_2;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p2_reg_2;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p3_reg_2;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p0_reg_2;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p1_reg_2;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p2_reg_2;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p3_reg_2;

reg    [IOG_DQS_LANES*64-1:0]    iog_dq_txdata_in_reg;
reg    [IOG_DQS_LANES*8-1:0]     iog_dm_txdata_in_reg;
reg    [IOG_DQS_LANES*64-1:0]    iog_dq_txdata_in_reg_2;
reg    [IOG_DQS_LANES*8-1:0]     iog_dm_txdata_in_reg_2;






always @ (posedge SCLK or negedge reset_n)
begin : register_for_delay
  if (!reset_n)
  begin
    iog_oe_p0_reg           <= 0;
    iog_oe_p1_reg           <= 0;
    iog_oe_p2_reg           <= 0;
    iog_oe_p3_reg           <= 0;
    dqs_oe_p0_reg           <= 0;
    dqs_oe_p1_reg           <= 0;
    dqs_oe_p2_reg           <= 0;
    dqs_oe_p3_reg           <= 0;
    dm_oe_p0_reg            <= 0;
    dm_oe_p1_reg            <= 0;
    dm_oe_p2_reg            <= 0;
    dm_oe_p3_reg            <= 0;
    iog_oe_p0_reg_2         <= 0;
    iog_oe_p1_reg_2         <= 0;
    iog_oe_p2_reg_2         <= 0;
    iog_oe_p3_reg_2         <= 0;
    dqs_oe_p0_reg_2         <= 0;
    dqs_oe_p1_reg_2         <= 0;
    dqs_oe_p2_reg_2         <= 0;
    dqs_oe_p3_reg_2         <= 0;
    dm_oe_p0_reg_2          <= 0;
    dm_oe_p1_reg_2          <= 0;
    dm_oe_p2_reg_2          <= 0;
    dm_oe_p3_reg_2          <= 0;
    iog_dq_txdata_in_reg    <= 0;
    iog_dm_txdata_in_reg    <= 0;
    iog_dq_txdata_in_reg_2  <= 0;
    iog_dm_txdata_in_reg_2  <= 0;
  end
  else
  begin
    iog_oe_p0_reg           <= iog_oe_p0_internal; 
    iog_oe_p1_reg           <= iog_oe_p1_internal;
    iog_oe_p2_reg           <= iog_oe_p2_internal;
    iog_oe_p3_reg           <= iog_oe_p3_internal;
    dqs_oe_p0_reg           <= dqs_oe_p0_internal;
    dqs_oe_p1_reg           <= dqs_oe_p1_internal;
    dqs_oe_p2_reg           <= dqs_oe_p2_internal;
    dqs_oe_p3_reg           <= dqs_oe_p3_internal;
    dm_oe_p0_reg            <= dm_oe_p0_internal; 
    dm_oe_p1_reg            <= dm_oe_p1_internal; 
    dm_oe_p2_reg            <= dm_oe_p2_internal; 
    dm_oe_p3_reg            <= dm_oe_p3_internal; 
    iog_oe_p0_reg_2         <= iog_oe_p0_reg;
    iog_oe_p1_reg_2         <= iog_oe_p1_reg;
    iog_oe_p2_reg_2         <= iog_oe_p2_reg;
    iog_oe_p3_reg_2         <= iog_oe_p3_reg;
    dqs_oe_p0_reg_2         <= dqs_oe_p0_reg;
    dqs_oe_p1_reg_2         <= dqs_oe_p1_reg;
    dqs_oe_p2_reg_2         <= dqs_oe_p2_reg;
    dqs_oe_p3_reg_2         <= dqs_oe_p3_reg;
    dm_oe_p0_reg_2          <= dm_oe_p0_reg ;
    dm_oe_p1_reg_2          <= dm_oe_p1_reg ;
    dm_oe_p2_reg_2          <= dm_oe_p2_reg ;
    dm_oe_p3_reg_2          <= dm_oe_p3_reg ;
    iog_dq_txdata_in_reg    <= iog_dq_txdata_in;
    iog_dm_txdata_in_reg    <= iog_dm_txdata_in;
    iog_dq_txdata_in_reg_2  <= iog_dq_txdata_in_reg;
    iog_dm_txdata_in_reg_2  <= iog_dm_txdata_in_reg;
  end
end

genvar i;
generate 
for (i=0; i<IOG_DQS_LANES; i=i+1)
begin
  always@(*)
  begin : output_assignments
    case(write_callibration_offset[3*(i+1)-1:3*i])
      0:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            {iog_dq_txdata_in[64*i+8*8-1   :64*i+8*7 ]},
            {iog_dq_txdata_in[64*i+8*7-1   :64*i+8*6 ]},
            {iog_dq_txdata_in[64*i+8*6-1   :64*i+8*5 ]},
            {iog_dq_txdata_in[64*i+8*5-1   :64*i+8*4 ]},
            {iog_dq_txdata_in[64*i+8*4-1   :64*i+8*3 ]},
            {iog_dq_txdata_in[64*i+8*3-1   :64*i+8*2 ]},
            {iog_dq_txdata_in[64*i+8*2-1   :64*i+8*1 ]},
            {iog_dq_txdata_in[64*i+8*1-1   :64*i+8*0 ]}

          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in[8*(i+1)-1:(8*i)]
          };
          
          iog_oe_p0[i] <= iog_oe_p0_internal[i];
          iog_oe_p1[i] <= iog_oe_p1_internal[i];
          iog_oe_p2[i] <= iog_oe_p2_internal[i];
          iog_oe_p3[i] <= iog_oe_p3_internal[i];
          
          dqs_oe_p0[i] <= dqs_oe_p0_internal[i];
          dqs_oe_p1[i] <= dqs_oe_p1_internal[i];
          dqs_oe_p2[i] <= dqs_oe_p2_internal[i];
          dqs_oe_p3[i] <= dqs_oe_p3_internal[i];
          
          dm_oe_p0[i]  <= dm_oe_p0_internal[i];
          dm_oe_p1[i]  <= dm_oe_p1_internal[i];
          dm_oe_p2[i]  <= dm_oe_p2_internal[i];
          dm_oe_p3[i]  <= dm_oe_p3_internal[i];

        end
      1:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            { iog_dq_txdata_in[64*i+8*8-1-2   :64*i+8*7 ] , iog_dq_txdata_in_reg[64*i+8*8-1   :64*i+8*7+6 ]  },
            { iog_dq_txdata_in[64*i+8*7-1-2   :64*i+8*6 ] , iog_dq_txdata_in_reg[64*i+8*7-1   :64*i+8*6+6 ]  },
            { iog_dq_txdata_in[64*i+8*6-1-2   :64*i+8*5 ] , iog_dq_txdata_in_reg[64*i+8*6-1   :64*i+8*5+6 ]  },
            { iog_dq_txdata_in[64*i+8*5-1-2   :64*i+8*4 ] , iog_dq_txdata_in_reg[64*i+8*5-1   :64*i+8*4+6 ]  },
            { iog_dq_txdata_in[64*i+8*4-1-2   :64*i+8*3 ] , iog_dq_txdata_in_reg[64*i+8*4-1   :64*i+8*3+6 ]  },
            { iog_dq_txdata_in[64*i+8*3-1-2   :64*i+8*2 ] , iog_dq_txdata_in_reg[64*i+8*3-1   :64*i+8*2+6 ]  },
            { iog_dq_txdata_in[64*i+8*2-1-2   :64*i+8*1 ] , iog_dq_txdata_in_reg[64*i+8*2-1   :64*i+8*1+6 ]  },
            { iog_dq_txdata_in[64*i+8*1-1-2   :64*i+8*0 ] , iog_dq_txdata_in_reg[64*i+8*1-1   :64*i+8*0+6 ]  }
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in[8*(i+1)-1-2:(8*i)], iog_dm_txdata_in_reg[8*(i+1)-1:(8*i)+6]
          };


          iog_oe_p0[i] <= iog_oe_p3_reg     [i];
          iog_oe_p1[i] <= iog_oe_p0_internal[i];
          iog_oe_p2[i] <= iog_oe_p1_internal[i];
          iog_oe_p3[i] <= iog_oe_p2_internal[i];
          
          dqs_oe_p0[i] <= dqs_oe_p3_reg     [i];
          dqs_oe_p1[i] <= dqs_oe_p0_internal[i];
          dqs_oe_p2[i] <= dqs_oe_p1_internal[i];
          dqs_oe_p3[i] <= dqs_oe_p2_internal[i];
          
          dm_oe_p0[i]  <= dm_oe_p3_reg     [i];
          dm_oe_p1[i]  <= dm_oe_p0_internal[i];
          dm_oe_p2[i]  <= dm_oe_p1_internal[i];
          dm_oe_p3[i]  <= dm_oe_p2_internal[i];
          
        end
      2:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            { iog_dq_txdata_in[64*i+8*8-1-4   :64*i+8*7 ], iog_dq_txdata_in_reg[64*i+8*8-1   :64*i+8*7 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*7-1-4   :64*i+8*6 ], iog_dq_txdata_in_reg[64*i+8*7-1   :64*i+8*6 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*6-1-4   :64*i+8*5 ], iog_dq_txdata_in_reg[64*i+8*6-1   :64*i+8*5 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*5-1-4   :64*i+8*4 ], iog_dq_txdata_in_reg[64*i+8*5-1   :64*i+8*4 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*4-1-4   :64*i+8*3 ], iog_dq_txdata_in_reg[64*i+8*4-1   :64*i+8*3 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*3-1-4   :64*i+8*2 ], iog_dq_txdata_in_reg[64*i+8*3-1   :64*i+8*2 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*2-1-4   :64*i+8*1 ], iog_dq_txdata_in_reg[64*i+8*2-1   :64*i+8*1 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*1-1-4   :64*i+8*0 ], iog_dq_txdata_in_reg[64*i+8*1-1   :64*i+8*0 + 4 ]  }
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
             iog_dm_txdata_in[8*(i+1)-1-4:(8*i)], iog_dm_txdata_in_reg[8*(i+1)-1:(8*i)+4] 
          };
          
          iog_oe_p0[i] <= iog_oe_p2_reg     [i];
          iog_oe_p1[i] <= iog_oe_p3_reg     [i];
          iog_oe_p2[i] <= iog_oe_p0_internal[i];
          iog_oe_p3[i] <= iog_oe_p1_internal[i];
          
          dqs_oe_p0[i] <= dqs_oe_p2_reg     [i];
          dqs_oe_p1[i] <= dqs_oe_p3_reg     [i];
          dqs_oe_p2[i] <= dqs_oe_p0_internal[i];
          dqs_oe_p3[i] <= dqs_oe_p1_internal[i];
          
          dm_oe_p0[i]  <= dm_oe_p2_reg     [i];
          dm_oe_p1[i]  <= dm_oe_p3_reg     [i];
          dm_oe_p2[i]  <= dm_oe_p0_internal[i];
          dm_oe_p3[i]  <= dm_oe_p1_internal[i];
        end
      3:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            { iog_dq_txdata_in[64*i+8*8-1-6  :64*i+8*7 ], iog_dq_txdata_in_reg[64*i+8*8-1   :64*i+8*7 + 2 ] },
            { iog_dq_txdata_in[64*i+8*7-1-6  :64*i+8*6 ], iog_dq_txdata_in_reg[64*i+8*7-1   :64*i+8*6 + 2 ] },
            { iog_dq_txdata_in[64*i+8*6-1-6  :64*i+8*5 ], iog_dq_txdata_in_reg[64*i+8*6-1   :64*i+8*5 + 2 ] },
            { iog_dq_txdata_in[64*i+8*5-1-6  :64*i+8*4 ], iog_dq_txdata_in_reg[64*i+8*5-1   :64*i+8*4 + 2 ] },
            { iog_dq_txdata_in[64*i+8*4-1-6  :64*i+8*3 ], iog_dq_txdata_in_reg[64*i+8*4-1   :64*i+8*3 + 2 ] },
            { iog_dq_txdata_in[64*i+8*3-1-6  :64*i+8*2 ], iog_dq_txdata_in_reg[64*i+8*3-1   :64*i+8*2 + 2 ] },
            { iog_dq_txdata_in[64*i+8*2-1-6  :64*i+8*1 ], iog_dq_txdata_in_reg[64*i+8*2-1   :64*i+8*1 + 2 ] },
            { iog_dq_txdata_in[64*i+8*1-1-6  :64*i+8*0 ], iog_dq_txdata_in_reg[64*i+8*1-1   :64*i+8*0 + 2 ] }
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in[8*(i+1)-1-6:(8*i)], iog_dm_txdata_in_reg[8*(i+1)-1:(8*i)+2] 
          };
          
          iog_oe_p0[i] <= iog_oe_p1_reg     [i];
          iog_oe_p1[i] <= iog_oe_p2_reg     [i];
          iog_oe_p2[i] <= iog_oe_p3_reg     [i];
          iog_oe_p3[i] <= iog_oe_p0_internal[i];
          
          dqs_oe_p0[i] <= dqs_oe_p1_reg     [i];
          dqs_oe_p1[i] <= dqs_oe_p2_reg     [i];
          dqs_oe_p2[i] <= dqs_oe_p3_reg     [i];
          dqs_oe_p3[i] <= dqs_oe_p0_internal[i];
          
          dm_oe_p0[i]  <= dm_oe_p1_reg     [i];
          dm_oe_p1[i]  <= dm_oe_p2_reg     [i];
          dm_oe_p2[i]  <= dm_oe_p3_reg     [i];
          dm_oe_p3[i]  <= dm_oe_p0_internal[i];
          
        end
      4:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            {iog_dq_txdata_in_reg[64*i+8*8-1   :64*i+8*7 ]},
            {iog_dq_txdata_in_reg[64*i+8*7-1   :64*i+8*6 ]},
            {iog_dq_txdata_in_reg[64*i+8*6-1   :64*i+8*5 ]},
            {iog_dq_txdata_in_reg[64*i+8*5-1   :64*i+8*4 ]},
            {iog_dq_txdata_in_reg[64*i+8*4-1   :64*i+8*3 ]},
            {iog_dq_txdata_in_reg[64*i+8*3-1   :64*i+8*2 ]},
            {iog_dq_txdata_in_reg[64*i+8*2-1   :64*i+8*1 ]},
            {iog_dq_txdata_in_reg[64*i+8*1-1   :64*i+8*0 ]}
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in_reg[8*(i+1)-1:(8*i)]
          };
          
          iog_oe_p0[i] <= iog_oe_p0_reg[i];
          iog_oe_p1[i] <= iog_oe_p1_reg[i];
          iog_oe_p2[i] <= iog_oe_p2_reg[i];
          iog_oe_p3[i] <= iog_oe_p3_reg[i];
          
          dqs_oe_p0[i] <= dqs_oe_p0_reg[i];
          dqs_oe_p1[i] <= dqs_oe_p1_reg[i];
          dqs_oe_p2[i] <= dqs_oe_p2_reg[i];
          dqs_oe_p3[i] <= dqs_oe_p3_reg[i];
          
          dm_oe_p0[i]  <= dm_oe_p0_reg[i];
          dm_oe_p1[i]  <= dm_oe_p1_reg[i];
          dm_oe_p2[i]  <= dm_oe_p2_reg[i];
          dm_oe_p3[i]  <= dm_oe_p3_reg[i];

        end
      5:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            { iog_dq_txdata_in_reg[64*i+8*8-1-2   :64*i+8*7 ], iog_dq_txdata_in_reg_2[64*i+8*8-1   :64*i+8*7 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*7-1-2   :64*i+8*6 ], iog_dq_txdata_in_reg_2[64*i+8*7-1   :64*i+8*6 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*6-1-2   :64*i+8*5 ], iog_dq_txdata_in_reg_2[64*i+8*6-1   :64*i+8*5 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*5-1-2   :64*i+8*4 ], iog_dq_txdata_in_reg_2[64*i+8*5-1   :64*i+8*4 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*4-1-2   :64*i+8*3 ], iog_dq_txdata_in_reg_2[64*i+8*4-1   :64*i+8*3 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*3-1-2   :64*i+8*2 ], iog_dq_txdata_in_reg_2[64*i+8*3-1   :64*i+8*2 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*2-1-2   :64*i+8*1 ], iog_dq_txdata_in_reg_2[64*i+8*2-1   :64*i+8*1 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*1-1-2   :64*i+8*0 ], iog_dq_txdata_in_reg_2[64*i+8*1-1   :64*i+8*0 + 6 ] }
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in_reg[8*(i+1)-1-2:(8*i)], iog_dm_txdata_in_reg_2[8*(i+1)-1:(8*i)+6] 
          };

          
          iog_oe_p0[i] <= iog_oe_p3_reg_2[i];
          iog_oe_p1[i] <= iog_oe_p0_reg  [i];
          iog_oe_p2[i] <= iog_oe_p1_reg  [i];
          iog_oe_p3[i] <= iog_oe_p2_reg  [i];
          
          dqs_oe_p0[i] <= dqs_oe_p3_reg_2[i];
          dqs_oe_p1[i] <= dqs_oe_p0_reg  [i];
          dqs_oe_p2[i] <= dqs_oe_p1_reg  [i];
          dqs_oe_p3[i] <= dqs_oe_p2_reg  [i];
          
          dm_oe_p0[i]  <= dm_oe_p3_reg_2[i];
          dm_oe_p1[i]  <= dm_oe_p0_reg  [i];
          dm_oe_p2[i]  <= dm_oe_p1_reg  [i];
          dm_oe_p3[i]  <= dm_oe_p2_reg  [i];
          
        end
      6:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            { iog_dq_txdata_in_reg[64*i+8*8-1-4   :64*i+8*7 ], iog_dq_txdata_in_reg_2[64*i+8*8-1   :64*i+8*7 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*7-1-4   :64*i+8*6 ], iog_dq_txdata_in_reg_2[64*i+8*7-1   :64*i+8*6 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*6-1-4   :64*i+8*5 ], iog_dq_txdata_in_reg_2[64*i+8*6-1   :64*i+8*5 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*5-1-4   :64*i+8*4 ], iog_dq_txdata_in_reg_2[64*i+8*5-1   :64*i+8*4 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*4-1-4   :64*i+8*3 ], iog_dq_txdata_in_reg_2[64*i+8*4-1   :64*i+8*3 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*3-1-4   :64*i+8*2 ], iog_dq_txdata_in_reg_2[64*i+8*3-1   :64*i+8*2 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*2-1-4   :64*i+8*1 ], iog_dq_txdata_in_reg_2[64*i+8*2-1   :64*i+8*1 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*1-1-4   :64*i+8*0 ], iog_dq_txdata_in_reg_2[64*i+8*1-1   :64*i+8*0 + 4 ] }
          };

        


          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in_reg[8*(i+1)-1-4:(8*i)], iog_dm_txdata_in_reg_2[8*(i+1)-1:(8*i)+4]
          };
          
          iog_oe_p0[i] <= iog_oe_p2_reg_2[i];
          iog_oe_p1[i] <= iog_oe_p3_reg_2[i];
          iog_oe_p2[i] <= iog_oe_p0_reg  [i];
          iog_oe_p3[i] <= iog_oe_p1_reg  [i];
          
          dqs_oe_p0[i] <= dqs_oe_p2_reg_2[i];
          dqs_oe_p1[i] <= dqs_oe_p3_reg_2[i];
          dqs_oe_p2[i] <= dqs_oe_p0_reg  [i];
          dqs_oe_p3[i] <= dqs_oe_p1_reg  [i];
          
          dm_oe_p0[i]  <= dm_oe_p2_reg_2[i];
          dm_oe_p1[i]  <= dm_oe_p3_reg_2[i];
          dm_oe_p2[i]  <= dm_oe_p0_reg  [i];
          dm_oe_p3[i]  <= dm_oe_p1_reg  [i];
          
        end
      7:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            { iog_dq_txdata_in_reg[64*i+8*8-1-6   :64*i+8*7 ], iog_dq_txdata_in_reg_2[64*i+8*8-1   :64*i+8*7 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*7-1-6   :64*i+8*6 ], iog_dq_txdata_in_reg_2[64*i+8*7-1   :64*i+8*6 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*6-1-6   :64*i+8*5 ], iog_dq_txdata_in_reg_2[64*i+8*6-1   :64*i+8*5 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*5-1-6   :64*i+8*4 ], iog_dq_txdata_in_reg_2[64*i+8*5-1   :64*i+8*4 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*4-1-6   :64*i+8*3 ], iog_dq_txdata_in_reg_2[64*i+8*4-1   :64*i+8*3 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*3-1-6   :64*i+8*2 ], iog_dq_txdata_in_reg_2[64*i+8*3-1   :64*i+8*2 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*2-1-6   :64*i+8*1 ], iog_dq_txdata_in_reg_2[64*i+8*2-1   :64*i+8*1 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*1-1-6   :64*i+8*0 ], iog_dq_txdata_in_reg_2[64*i+8*1-1   :64*i+8*0 + 2 ] }
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in_reg[8*(i+1)-1-6:(8*i)], iog_dm_txdata_in_reg_2[8*(i+1)-1:(8*i)+2] 
          };
          
          iog_oe_p0[i] <= iog_oe_p1_reg_2[i];
          iog_oe_p1[i] <= iog_oe_p2_reg_2[i];
          iog_oe_p2[i] <= iog_oe_p3_reg_2[i];
          iog_oe_p3[i] <= iog_oe_p0_reg  [i];
          
          dqs_oe_p0[i] <= dqs_oe_p1_reg_2[i];
          dqs_oe_p1[i] <= dqs_oe_p2_reg_2[i];
          dqs_oe_p2[i] <= dqs_oe_p3_reg_2[i];
          dqs_oe_p3[i] <= dqs_oe_p0_reg  [i];
          
          dm_oe_p0[i]  <= dm_oe_p1_reg_2[i];
          dm_oe_p1[i]  <= dm_oe_p2_reg_2[i];
          dm_oe_p2[i]  <= dm_oe_p3_reg_2[i];
          dm_oe_p3[i]  <= dm_oe_p0_reg  [i];
          
        end
        
      default:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            {iog_dq_txdata_in[64*i+8*8-1   :64*i+8*7 ]},
            {iog_dq_txdata_in[64*i+8*7-1   :64*i+8*6 ]},
            {iog_dq_txdata_in[64*i+8*6-1   :64*i+8*5 ]},
            {iog_dq_txdata_in[64*i+8*5-1   :64*i+8*4 ]},
            {iog_dq_txdata_in[64*i+8*4-1   :64*i+8*3 ]},
            {iog_dq_txdata_in[64*i+8*3-1   :64*i+8*2 ]},
            {iog_dq_txdata_in[64*i+8*2-1   :64*i+8*1 ]},
            {iog_dq_txdata_in[64*i+8*1-1   :64*i+8*0 ]}
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in[8*(i+1)-1:(8*i)]
          };
          
          iog_oe_p0[i] <= iog_oe_p0_internal[i];
          iog_oe_p1[i] <= iog_oe_p1_internal[i];
          iog_oe_p2[i] <= iog_oe_p2_internal[i];
          iog_oe_p3[i] <= iog_oe_p3_internal[i];
          
          dqs_oe_p0[i] <= dqs_oe_p0_internal[i];
          dqs_oe_p1[i] <= dqs_oe_p1_internal[i];
          dqs_oe_p2[i] <= dqs_oe_p2_internal[i];
          dqs_oe_p3[i] <= dqs_oe_p3_internal[i];
          
          dm_oe_p0[i]  <= dm_oe_p0_internal[i];
          dm_oe_p1[i]  <= dm_oe_p1_internal[i];
          dm_oe_p2[i]  <= dm_oe_p2_internal[i];
          dm_oe_p3[i]  <= dm_oe_p3_internal[i];
        end
      
      
    endcase
  end
end
endgenerate







integer j;
generate

for (i=0; i<IOG_DQS_LANES; i=i+1) 
begin : per_lane	
	
	always @(posedge SCLK or negedge reset_n)
	begin
		if(!reset_n)
		begin
			odt_dyn_on[i][HOLD_ODT_CYCLES-1:0] <= 0;
		end	
		else
		begin

			if(iog_rddata_en_p0_p[i] || dfi_rddata_en_p3) 
			begin
				odt_dyn_on[i][0] <= 1;
			end
			else
			begin
				odt_dyn_on[i][0] <= 0;
			end
			
			for(j = 1 ; j<(HOLD_ODT_CYCLES); j=j+1)
				odt_dyn_on[i][j] <= odt_dyn_on[i][j-1];	
		end
	end


	assign odt_dyn_lane[i] = (|odt_dyn_on[i]) | dfi_rddata_en_p3;		
	
end
endgenerate







assign trn_delay_line_sel = (dfi_wrlvl_en | !dfi_init_complete) ? 'h0 : (2**IOG_DQS_LANES)-1;




reg dfi_wrdata_en_p3_reg;

always @( posedge SCLK or negedge reset_n )
begin   : wdata_en_registering

  if (!(reset_n))
  begin
    dfi_wrdata_en_p3_reg <= 0;
  end
  else
  begin
    dfi_wrdata_en_p3_reg <= dfi_wrdata_en_p3;
  end
end


assign iog_oe_p0_internal = (dfi_wrlvl_en) ? {IOG_DQS_LANES{1'b0}} : (dfi_wrdata_en_p0|dfi_wrdata_en_p3_reg) ? (2**IOG_DQS_LANES)-1:'h0;
assign iog_oe_p1_internal = (dfi_wrlvl_en) ? {IOG_DQS_LANES{1'b0}} : (dfi_wrdata_en_p1|dfi_wrdata_en_p0)	? (2**IOG_DQS_LANES)-1:'h0;
assign iog_oe_p2_internal = (dfi_wrlvl_en) ? {IOG_DQS_LANES{1'b0}} : (dfi_wrdata_en_p2|dfi_wrdata_en_p1)	? (2**IOG_DQS_LANES)-1:'h0;
assign iog_oe_p3_internal = (dfi_wrlvl_en) ? {IOG_DQS_LANES{1'b0}} : (dfi_wrdata_en_p3|dfi_wrdata_en_p2)	? (2**IOG_DQS_LANES)-1:'h0;

assign dm_oe_p0_internal = (!dfi_init_complete ) ? {IOG_DQS_LANES{1'b1}} : iog_oe_p0_internal;
assign dm_oe_p1_internal = (!dfi_init_complete ) ? {IOG_DQS_LANES{1'b1}} : iog_oe_p1_internal;
assign dm_oe_p2_internal = (!dfi_init_complete ) ? {IOG_DQS_LANES{1'b1}} : iog_oe_p2_internal;
assign dm_oe_p3_internal = (!dfi_init_complete ) ? {IOG_DQS_LANES{1'b1}} : iog_oe_p3_internal;


assign dqs_oe_p0_internal = (!dfi_init_complete | dfi_wrlvl_en) ?  {IOG_DQS_LANES{1'b1}} : (dfi_wrdata_en_p0|dfi_wrdata_en_p3_reg) ? (2**IOG_DQS_LANES)-1:'h0;
assign dqs_oe_p1_internal = (!dfi_init_complete | dfi_wrlvl_en) ?  {IOG_DQS_LANES{1'b1}} : (dfi_wrdata_en_p1|dfi_wrdata_en_p0)	? (2**IOG_DQS_LANES)-1:'h0;
assign dqs_oe_p2_internal = (!dfi_init_complete | dfi_wrlvl_en) ?  {IOG_DQS_LANES{1'b1}} : (dfi_wrdata_en_p2|dfi_wrdata_en_p1)	? (2**IOG_DQS_LANES)-1:'h0;
assign dqs_oe_p3_internal = (!dfi_init_complete | dfi_wrlvl_en) ?  {IOG_DQS_LANES{1'b1}} : (dfi_wrdata_en_p3|dfi_wrdata_en_p2)	? (2**IOG_DQS_LANES)-1:'h0;









assign dfi_rddata_cs_0_n = dfi_rddata_cs_0_n_p3;
assign dfi_rddata_cs_1_n = dfi_rddata_cs_1_n_p3;

assign select_rank_1 = apb_iog_on ? apb_ctrl_chip_sel : select_rank_1_gt;


endmodule
module PHY_SIG_MOD( SCLK,
                    reset_n,
                    dfi_rdlvl_en,
                    dfi_rdlvl_gate_en,
                    dfi_wrdata_en_p0,
                    dfi_wrdata_en_p1,
                    dfi_wrdata_en_p2,
                    dfi_wrdata_en_p3,
                    dfi_wrlvl_en,
                    trn_delay_line_sel,
                    iog_oe_p0,
                    iog_oe_p1,
                    iog_oe_p2,
                    iog_oe_p3,
                    dqs_oe_p0,
                    dqs_oe_p1,
                    dqs_oe_p2,
                    dqs_oe_p3,

                    dm_oe_p0,
                    dm_oe_p1,
                    dm_oe_p2,
                    dm_oe_p3,
                    dfi_rddata_cs_0_n_p0,
                    dfi_rddata_cs_0_n_p1,
                    dfi_rddata_cs_0_n_p2,
                    dfi_rddata_cs_0_n_p3,
                    dfi_rddata_cs_1_n_p0,
                    dfi_rddata_cs_1_n_p1,
                    dfi_rddata_cs_1_n_p2,
                    dfi_rddata_cs_1_n_p3,
                    dfi_wrdata_cs_0_n_p0,
                    dfi_wrdata_cs_0_n_p1,
                    dfi_wrdata_cs_0_n_p2,
                    dfi_wrdata_cs_0_n_p3,
                    dfi_wrdata_cs_1_n_p0,
                    dfi_wrdata_cs_1_n_p1,
                    dfi_wrdata_cs_1_n_p2,
                    dfi_wrdata_cs_1_n_p3,
                    dfi_rddata_cs_0_n,
                    dfi_rddata_cs_1_n,
                    apb_ctrl_chip_sel,
                    apb_iog_on,
                    odt_dyn_lane,
                    dfi_rddata_en_p3,
                    iog_rddata_en_p0_p,
                    select_rank_1_gt,
                    select_rank_1,
                    dfi_init_complete,



                    iog_dq_txdata_in,
                    iog_dq_txdata_out,
                    iog_dm_txdata_in,
                    iog_dm_txdata_out,
                    write_callibration_offset
          
          
					);


parameter IOG_DQS_LANES = 9;
parameter HOLD_ODT_CYCLES = 2;

input          SCLK;
input          reset_n;



input          dfi_rdlvl_en;
input          dfi_rdlvl_gate_en;
input          dfi_wrdata_en_p0;
input          dfi_wrdata_en_p1;
input          dfi_wrdata_en_p2;
input          dfi_wrdata_en_p3;
input          dfi_wrlvl_en;



output [IOG_DQS_LANES-1:0]       trn_delay_line_sel;
output [IOG_DQS_LANES-1:0]       iog_oe_p0;
output [IOG_DQS_LANES-1:0]       iog_oe_p1;
output [IOG_DQS_LANES-1:0]       iog_oe_p2;
output [IOG_DQS_LANES-1:0]       iog_oe_p3;
output [IOG_DQS_LANES-1:0]       dqs_oe_p0;
output [IOG_DQS_LANES-1:0]       dqs_oe_p1;
output [IOG_DQS_LANES-1:0]       dqs_oe_p2;
output [IOG_DQS_LANES-1:0]       dqs_oe_p3;
output [IOG_DQS_LANES-1:0]       dm_oe_p0;
output [IOG_DQS_LANES-1:0]       dm_oe_p1;
output [IOG_DQS_LANES-1:0]       dm_oe_p2;
output [IOG_DQS_LANES-1:0]       dm_oe_p3;

reg    [IOG_DQS_LANES-1:0]       iog_oe_p0;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p1;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p2;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p3;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p0;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p1;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p2;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p3;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p0;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p1;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p2;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p3;

input  [IOG_DQS_LANES*64-1:0]    iog_dq_txdata_in;
output [IOG_DQS_LANES*64-1:0]    iog_dq_txdata_out;
reg    [IOG_DQS_LANES*64-1:0]    iog_dq_txdata_out;
input  [IOG_DQS_LANES*8-1:0]     iog_dm_txdata_in;
output [IOG_DQS_LANES*8-1:0]     iog_dm_txdata_out;
reg    [IOG_DQS_LANES*8-1:0]     iog_dm_txdata_out;



output          dfi_rddata_cs_0_n;
output          dfi_rddata_cs_1_n;

input          dfi_rddata_cs_0_n_p0;
input          dfi_rddata_cs_0_n_p1;
input          dfi_rddata_cs_0_n_p2;
input          dfi_rddata_cs_0_n_p3;
input          dfi_rddata_cs_1_n_p0;
input          dfi_rddata_cs_1_n_p1;
input          dfi_rddata_cs_1_n_p2;
input          dfi_rddata_cs_1_n_p3;

input          dfi_wrdata_cs_0_n_p0;
input          dfi_wrdata_cs_0_n_p1;
input          dfi_wrdata_cs_0_n_p2;
input          dfi_wrdata_cs_0_n_p3;
input          dfi_wrdata_cs_1_n_p0;
input          dfi_wrdata_cs_1_n_p1;
input          dfi_wrdata_cs_1_n_p2;
input          dfi_wrdata_cs_1_n_p3;





input apb_ctrl_chip_sel;
input apb_iog_on;


output 	[IOG_DQS_LANES-1:0] 	odt_dyn_lane;
wire 	[IOG_DQS_LANES-1:0] 	odt_dyn_lane;
input         					dfi_rddata_en_p3;
input  [IOG_DQS_LANES-1:0] 		iog_rddata_en_p0_p;
reg  [HOLD_ODT_CYCLES-1:0] 		odt_dyn_on [IOG_DQS_LANES-1:0];

input select_rank_1_gt;
output select_rank_1;
wire select_rank_1;


input dfi_init_complete;


input [IOG_DQS_LANES*3-1:0]          write_callibration_offset;





wire   [IOG_DQS_LANES-1:0]       iog_oe_p0_internal;
wire   [IOG_DQS_LANES-1:0]       iog_oe_p1_internal;
wire   [IOG_DQS_LANES-1:0]       iog_oe_p2_internal;
wire   [IOG_DQS_LANES-1:0]       iog_oe_p3_internal;
wire   [IOG_DQS_LANES-1:0]       dqs_oe_p0_internal;
wire   [IOG_DQS_LANES-1:0]       dqs_oe_p1_internal;
wire   [IOG_DQS_LANES-1:0]       dqs_oe_p2_internal;
wire   [IOG_DQS_LANES-1:0]       dqs_oe_p3_internal;
wire   [IOG_DQS_LANES-1:0]       dm_oe_p0_internal;
wire   [IOG_DQS_LANES-1:0]       dm_oe_p1_internal;
wire   [IOG_DQS_LANES-1:0]       dm_oe_p2_internal;
wire   [IOG_DQS_LANES-1:0]       dm_oe_p3_internal;


reg    [IOG_DQS_LANES-1:0]       iog_oe_p0_reg;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p1_reg;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p2_reg;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p3_reg;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p0_reg;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p1_reg;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p2_reg;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p3_reg;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p0_reg;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p1_reg;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p2_reg;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p3_reg;

reg    [IOG_DQS_LANES-1:0]       iog_oe_p0_reg_2;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p1_reg_2;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p2_reg_2;
reg    [IOG_DQS_LANES-1:0]       iog_oe_p3_reg_2;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p0_reg_2;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p1_reg_2;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p2_reg_2;
reg    [IOG_DQS_LANES-1:0]       dqs_oe_p3_reg_2;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p0_reg_2;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p1_reg_2;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p2_reg_2;
reg    [IOG_DQS_LANES-1:0]       dm_oe_p3_reg_2;

reg    [IOG_DQS_LANES*64-1:0]    iog_dq_txdata_in_reg;
reg    [IOG_DQS_LANES*8-1:0]     iog_dm_txdata_in_reg;
reg    [IOG_DQS_LANES*64-1:0]    iog_dq_txdata_in_reg_2;
reg    [IOG_DQS_LANES*8-1:0]     iog_dm_txdata_in_reg_2;






always @ (posedge SCLK or negedge reset_n)
begin : register_for_delay
  if (!reset_n)
  begin
    iog_oe_p0_reg           <= 0;
    iog_oe_p1_reg           <= 0;
    iog_oe_p2_reg           <= 0;
    iog_oe_p3_reg           <= 0;
    dqs_oe_p0_reg           <= 0;
    dqs_oe_p1_reg           <= 0;
    dqs_oe_p2_reg           <= 0;
    dqs_oe_p3_reg           <= 0;
    dm_oe_p0_reg            <= 0;
    dm_oe_p1_reg            <= 0;
    dm_oe_p2_reg            <= 0;
    dm_oe_p3_reg            <= 0;
    iog_oe_p0_reg_2         <= 0;
    iog_oe_p1_reg_2         <= 0;
    iog_oe_p2_reg_2         <= 0;
    iog_oe_p3_reg_2         <= 0;
    dqs_oe_p0_reg_2         <= 0;
    dqs_oe_p1_reg_2         <= 0;
    dqs_oe_p2_reg_2         <= 0;
    dqs_oe_p3_reg_2         <= 0;
    dm_oe_p0_reg_2          <= 0;
    dm_oe_p1_reg_2          <= 0;
    dm_oe_p2_reg_2          <= 0;
    dm_oe_p3_reg_2          <= 0;
    iog_dq_txdata_in_reg    <= 0;
    iog_dm_txdata_in_reg    <= 0;
    iog_dq_txdata_in_reg_2  <= 0;
    iog_dm_txdata_in_reg_2  <= 0;
  end
  else
  begin
    iog_oe_p0_reg           <= iog_oe_p0_internal; 
    iog_oe_p1_reg           <= iog_oe_p1_internal;
    iog_oe_p2_reg           <= iog_oe_p2_internal;
    iog_oe_p3_reg           <= iog_oe_p3_internal;
    dqs_oe_p0_reg           <= dqs_oe_p0_internal;
    dqs_oe_p1_reg           <= dqs_oe_p1_internal;
    dqs_oe_p2_reg           <= dqs_oe_p2_internal;
    dqs_oe_p3_reg           <= dqs_oe_p3_internal;
    dm_oe_p0_reg            <= dm_oe_p0_internal; 
    dm_oe_p1_reg            <= dm_oe_p1_internal; 
    dm_oe_p2_reg            <= dm_oe_p2_internal; 
    dm_oe_p3_reg            <= dm_oe_p3_internal; 
    iog_oe_p0_reg_2         <= iog_oe_p0_reg;
    iog_oe_p1_reg_2         <= iog_oe_p1_reg;
    iog_oe_p2_reg_2         <= iog_oe_p2_reg;
    iog_oe_p3_reg_2         <= iog_oe_p3_reg;
    dqs_oe_p0_reg_2         <= dqs_oe_p0_reg;
    dqs_oe_p1_reg_2         <= dqs_oe_p1_reg;
    dqs_oe_p2_reg_2         <= dqs_oe_p2_reg;
    dqs_oe_p3_reg_2         <= dqs_oe_p3_reg;
    dm_oe_p0_reg_2          <= dm_oe_p0_reg ;
    dm_oe_p1_reg_2          <= dm_oe_p1_reg ;
    dm_oe_p2_reg_2          <= dm_oe_p2_reg ;
    dm_oe_p3_reg_2          <= dm_oe_p3_reg ;
    iog_dq_txdata_in_reg    <= iog_dq_txdata_in;
    iog_dm_txdata_in_reg    <= iog_dm_txdata_in;
    iog_dq_txdata_in_reg_2  <= iog_dq_txdata_in_reg;
    iog_dm_txdata_in_reg_2  <= iog_dm_txdata_in_reg;
  end
end

genvar i;
generate 
for (i=0; i<IOG_DQS_LANES; i=i+1)
begin
  always@(*)
  begin : output_assignments
    case(write_callibration_offset[3*(i+1)-1:3*i])
      0:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            {iog_dq_txdata_in[64*i+8*8-1   :64*i+8*7 ]},
            {iog_dq_txdata_in[64*i+8*7-1   :64*i+8*6 ]},
            {iog_dq_txdata_in[64*i+8*6-1   :64*i+8*5 ]},
            {iog_dq_txdata_in[64*i+8*5-1   :64*i+8*4 ]},
            {iog_dq_txdata_in[64*i+8*4-1   :64*i+8*3 ]},
            {iog_dq_txdata_in[64*i+8*3-1   :64*i+8*2 ]},
            {iog_dq_txdata_in[64*i+8*2-1   :64*i+8*1 ]},
            {iog_dq_txdata_in[64*i+8*1-1   :64*i+8*0 ]}

          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in[8*(i+1)-1:(8*i)]
          };
          
          iog_oe_p0[i] <= iog_oe_p0_internal[i];
          iog_oe_p1[i] <= iog_oe_p1_internal[i];
          iog_oe_p2[i] <= iog_oe_p2_internal[i];
          iog_oe_p3[i] <= iog_oe_p3_internal[i];
          
          dqs_oe_p0[i] <= dqs_oe_p0_internal[i];
          dqs_oe_p1[i] <= dqs_oe_p1_internal[i];
          dqs_oe_p2[i] <= dqs_oe_p2_internal[i];
          dqs_oe_p3[i] <= dqs_oe_p3_internal[i];
          
          dm_oe_p0[i]  <= dm_oe_p0_internal[i];
          dm_oe_p1[i]  <= dm_oe_p1_internal[i];
          dm_oe_p2[i]  <= dm_oe_p2_internal[i];
          dm_oe_p3[i]  <= dm_oe_p3_internal[i];

        end
      1:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            { iog_dq_txdata_in[64*i+8*8-1-2   :64*i+8*7 ] , iog_dq_txdata_in_reg[64*i+8*8-1   :64*i+8*7+6 ]  },
            { iog_dq_txdata_in[64*i+8*7-1-2   :64*i+8*6 ] , iog_dq_txdata_in_reg[64*i+8*7-1   :64*i+8*6+6 ]  },
            { iog_dq_txdata_in[64*i+8*6-1-2   :64*i+8*5 ] , iog_dq_txdata_in_reg[64*i+8*6-1   :64*i+8*5+6 ]  },
            { iog_dq_txdata_in[64*i+8*5-1-2   :64*i+8*4 ] , iog_dq_txdata_in_reg[64*i+8*5-1   :64*i+8*4+6 ]  },
            { iog_dq_txdata_in[64*i+8*4-1-2   :64*i+8*3 ] , iog_dq_txdata_in_reg[64*i+8*4-1   :64*i+8*3+6 ]  },
            { iog_dq_txdata_in[64*i+8*3-1-2   :64*i+8*2 ] , iog_dq_txdata_in_reg[64*i+8*3-1   :64*i+8*2+6 ]  },
            { iog_dq_txdata_in[64*i+8*2-1-2   :64*i+8*1 ] , iog_dq_txdata_in_reg[64*i+8*2-1   :64*i+8*1+6 ]  },
            { iog_dq_txdata_in[64*i+8*1-1-2   :64*i+8*0 ] , iog_dq_txdata_in_reg[64*i+8*1-1   :64*i+8*0+6 ]  }
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in[8*(i+1)-1-2:(8*i)], iog_dm_txdata_in_reg[8*(i+1)-1:(8*i)+6]
          };


          iog_oe_p0[i] <= iog_oe_p3_reg     [i];
          iog_oe_p1[i] <= iog_oe_p0_internal[i];
          iog_oe_p2[i] <= iog_oe_p1_internal[i];
          iog_oe_p3[i] <= iog_oe_p2_internal[i];
          
          dqs_oe_p0[i] <= dqs_oe_p3_reg     [i];
          dqs_oe_p1[i] <= dqs_oe_p0_internal[i];
          dqs_oe_p2[i] <= dqs_oe_p1_internal[i];
          dqs_oe_p3[i] <= dqs_oe_p2_internal[i];
          
          dm_oe_p0[i]  <= dm_oe_p3_reg     [i];
          dm_oe_p1[i]  <= dm_oe_p0_internal[i];
          dm_oe_p2[i]  <= dm_oe_p1_internal[i];
          dm_oe_p3[i]  <= dm_oe_p2_internal[i];
          
        end
      2:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            { iog_dq_txdata_in[64*i+8*8-1-4   :64*i+8*7 ], iog_dq_txdata_in_reg[64*i+8*8-1   :64*i+8*7 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*7-1-4   :64*i+8*6 ], iog_dq_txdata_in_reg[64*i+8*7-1   :64*i+8*6 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*6-1-4   :64*i+8*5 ], iog_dq_txdata_in_reg[64*i+8*6-1   :64*i+8*5 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*5-1-4   :64*i+8*4 ], iog_dq_txdata_in_reg[64*i+8*5-1   :64*i+8*4 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*4-1-4   :64*i+8*3 ], iog_dq_txdata_in_reg[64*i+8*4-1   :64*i+8*3 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*3-1-4   :64*i+8*2 ], iog_dq_txdata_in_reg[64*i+8*3-1   :64*i+8*2 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*2-1-4   :64*i+8*1 ], iog_dq_txdata_in_reg[64*i+8*2-1   :64*i+8*1 + 4 ]  },
            { iog_dq_txdata_in[64*i+8*1-1-4   :64*i+8*0 ], iog_dq_txdata_in_reg[64*i+8*1-1   :64*i+8*0 + 4 ]  }
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
             iog_dm_txdata_in[8*(i+1)-1-4:(8*i)], iog_dm_txdata_in_reg[8*(i+1)-1:(8*i)+4] 
          };
          
          iog_oe_p0[i] <= iog_oe_p2_reg     [i];
          iog_oe_p1[i] <= iog_oe_p3_reg     [i];
          iog_oe_p2[i] <= iog_oe_p0_internal[i];
          iog_oe_p3[i] <= iog_oe_p1_internal[i];
          
          dqs_oe_p0[i] <= dqs_oe_p2_reg     [i];
          dqs_oe_p1[i] <= dqs_oe_p3_reg     [i];
          dqs_oe_p2[i] <= dqs_oe_p0_internal[i];
          dqs_oe_p3[i] <= dqs_oe_p1_internal[i];
          
          dm_oe_p0[i]  <= dm_oe_p2_reg     [i];
          dm_oe_p1[i]  <= dm_oe_p3_reg     [i];
          dm_oe_p2[i]  <= dm_oe_p0_internal[i];
          dm_oe_p3[i]  <= dm_oe_p1_internal[i];
        end
      3:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            { iog_dq_txdata_in[64*i+8*8-1-6  :64*i+8*7 ], iog_dq_txdata_in_reg[64*i+8*8-1   :64*i+8*7 + 2 ] },
            { iog_dq_txdata_in[64*i+8*7-1-6  :64*i+8*6 ], iog_dq_txdata_in_reg[64*i+8*7-1   :64*i+8*6 + 2 ] },
            { iog_dq_txdata_in[64*i+8*6-1-6  :64*i+8*5 ], iog_dq_txdata_in_reg[64*i+8*6-1   :64*i+8*5 + 2 ] },
            { iog_dq_txdata_in[64*i+8*5-1-6  :64*i+8*4 ], iog_dq_txdata_in_reg[64*i+8*5-1   :64*i+8*4 + 2 ] },
            { iog_dq_txdata_in[64*i+8*4-1-6  :64*i+8*3 ], iog_dq_txdata_in_reg[64*i+8*4-1   :64*i+8*3 + 2 ] },
            { iog_dq_txdata_in[64*i+8*3-1-6  :64*i+8*2 ], iog_dq_txdata_in_reg[64*i+8*3-1   :64*i+8*2 + 2 ] },
            { iog_dq_txdata_in[64*i+8*2-1-6  :64*i+8*1 ], iog_dq_txdata_in_reg[64*i+8*2-1   :64*i+8*1 + 2 ] },
            { iog_dq_txdata_in[64*i+8*1-1-6  :64*i+8*0 ], iog_dq_txdata_in_reg[64*i+8*1-1   :64*i+8*0 + 2 ] }
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in[8*(i+1)-1-6:(8*i)], iog_dm_txdata_in_reg[8*(i+1)-1:(8*i)+2] 
          };
          
          iog_oe_p0[i] <= iog_oe_p1_reg     [i];
          iog_oe_p1[i] <= iog_oe_p2_reg     [i];
          iog_oe_p2[i] <= iog_oe_p3_reg     [i];
          iog_oe_p3[i] <= iog_oe_p0_internal[i];
          
          dqs_oe_p0[i] <= dqs_oe_p1_reg     [i];
          dqs_oe_p1[i] <= dqs_oe_p2_reg     [i];
          dqs_oe_p2[i] <= dqs_oe_p3_reg     [i];
          dqs_oe_p3[i] <= dqs_oe_p0_internal[i];
          
          dm_oe_p0[i]  <= dm_oe_p1_reg     [i];
          dm_oe_p1[i]  <= dm_oe_p2_reg     [i];
          dm_oe_p2[i]  <= dm_oe_p3_reg     [i];
          dm_oe_p3[i]  <= dm_oe_p0_internal[i];
          
        end
      4:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            {iog_dq_txdata_in_reg[64*i+8*8-1   :64*i+8*7 ]},
            {iog_dq_txdata_in_reg[64*i+8*7-1   :64*i+8*6 ]},
            {iog_dq_txdata_in_reg[64*i+8*6-1   :64*i+8*5 ]},
            {iog_dq_txdata_in_reg[64*i+8*5-1   :64*i+8*4 ]},
            {iog_dq_txdata_in_reg[64*i+8*4-1   :64*i+8*3 ]},
            {iog_dq_txdata_in_reg[64*i+8*3-1   :64*i+8*2 ]},
            {iog_dq_txdata_in_reg[64*i+8*2-1   :64*i+8*1 ]},
            {iog_dq_txdata_in_reg[64*i+8*1-1   :64*i+8*0 ]}
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in_reg[8*(i+1)-1:(8*i)]
          };
          
          iog_oe_p0[i] <= iog_oe_p0_reg[i];
          iog_oe_p1[i] <= iog_oe_p1_reg[i];
          iog_oe_p2[i] <= iog_oe_p2_reg[i];
          iog_oe_p3[i] <= iog_oe_p3_reg[i];
          
          dqs_oe_p0[i] <= dqs_oe_p0_reg[i];
          dqs_oe_p1[i] <= dqs_oe_p1_reg[i];
          dqs_oe_p2[i] <= dqs_oe_p2_reg[i];
          dqs_oe_p3[i] <= dqs_oe_p3_reg[i];
          
          dm_oe_p0[i]  <= dm_oe_p0_reg[i];
          dm_oe_p1[i]  <= dm_oe_p1_reg[i];
          dm_oe_p2[i]  <= dm_oe_p2_reg[i];
          dm_oe_p3[i]  <= dm_oe_p3_reg[i];

        end
      5:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            { iog_dq_txdata_in_reg[64*i+8*8-1-2   :64*i+8*7 ], iog_dq_txdata_in_reg_2[64*i+8*8-1   :64*i+8*7 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*7-1-2   :64*i+8*6 ], iog_dq_txdata_in_reg_2[64*i+8*7-1   :64*i+8*6 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*6-1-2   :64*i+8*5 ], iog_dq_txdata_in_reg_2[64*i+8*6-1   :64*i+8*5 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*5-1-2   :64*i+8*4 ], iog_dq_txdata_in_reg_2[64*i+8*5-1   :64*i+8*4 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*4-1-2   :64*i+8*3 ], iog_dq_txdata_in_reg_2[64*i+8*4-1   :64*i+8*3 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*3-1-2   :64*i+8*2 ], iog_dq_txdata_in_reg_2[64*i+8*3-1   :64*i+8*2 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*2-1-2   :64*i+8*1 ], iog_dq_txdata_in_reg_2[64*i+8*2-1   :64*i+8*1 + 6 ] },
            { iog_dq_txdata_in_reg[64*i+8*1-1-2   :64*i+8*0 ], iog_dq_txdata_in_reg_2[64*i+8*1-1   :64*i+8*0 + 6 ] }
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in_reg[8*(i+1)-1-2:(8*i)], iog_dm_txdata_in_reg_2[8*(i+1)-1:(8*i)+6] 
          };

          
          iog_oe_p0[i] <= iog_oe_p3_reg_2[i];
          iog_oe_p1[i] <= iog_oe_p0_reg  [i];
          iog_oe_p2[i] <= iog_oe_p1_reg  [i];
          iog_oe_p3[i] <= iog_oe_p2_reg  [i];
          
          dqs_oe_p0[i] <= dqs_oe_p3_reg_2[i];
          dqs_oe_p1[i] <= dqs_oe_p0_reg  [i];
          dqs_oe_p2[i] <= dqs_oe_p1_reg  [i];
          dqs_oe_p3[i] <= dqs_oe_p2_reg  [i];
          
          dm_oe_p0[i]  <= dm_oe_p3_reg_2[i];
          dm_oe_p1[i]  <= dm_oe_p0_reg  [i];
          dm_oe_p2[i]  <= dm_oe_p1_reg  [i];
          dm_oe_p3[i]  <= dm_oe_p2_reg  [i];
          
        end
      6:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            { iog_dq_txdata_in_reg[64*i+8*8-1-4   :64*i+8*7 ], iog_dq_txdata_in_reg_2[64*i+8*8-1   :64*i+8*7 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*7-1-4   :64*i+8*6 ], iog_dq_txdata_in_reg_2[64*i+8*7-1   :64*i+8*6 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*6-1-4   :64*i+8*5 ], iog_dq_txdata_in_reg_2[64*i+8*6-1   :64*i+8*5 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*5-1-4   :64*i+8*4 ], iog_dq_txdata_in_reg_2[64*i+8*5-1   :64*i+8*4 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*4-1-4   :64*i+8*3 ], iog_dq_txdata_in_reg_2[64*i+8*4-1   :64*i+8*3 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*3-1-4   :64*i+8*2 ], iog_dq_txdata_in_reg_2[64*i+8*3-1   :64*i+8*2 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*2-1-4   :64*i+8*1 ], iog_dq_txdata_in_reg_2[64*i+8*2-1   :64*i+8*1 + 4 ] },
            { iog_dq_txdata_in_reg[64*i+8*1-1-4   :64*i+8*0 ], iog_dq_txdata_in_reg_2[64*i+8*1-1   :64*i+8*0 + 4 ] }
          };

        


          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in_reg[8*(i+1)-1-4:(8*i)], iog_dm_txdata_in_reg_2[8*(i+1)-1:(8*i)+4]
          };
          
          iog_oe_p0[i] <= iog_oe_p2_reg_2[i];
          iog_oe_p1[i] <= iog_oe_p3_reg_2[i];
          iog_oe_p2[i] <= iog_oe_p0_reg  [i];
          iog_oe_p3[i] <= iog_oe_p1_reg  [i];
          
          dqs_oe_p0[i] <= dqs_oe_p2_reg_2[i];
          dqs_oe_p1[i] <= dqs_oe_p3_reg_2[i];
          dqs_oe_p2[i] <= dqs_oe_p0_reg  [i];
          dqs_oe_p3[i] <= dqs_oe_p1_reg  [i];
          
          dm_oe_p0[i]  <= dm_oe_p2_reg_2[i];
          dm_oe_p1[i]  <= dm_oe_p3_reg_2[i];
          dm_oe_p2[i]  <= dm_oe_p0_reg  [i];
          dm_oe_p3[i]  <= dm_oe_p1_reg  [i];
          
        end
      7:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            { iog_dq_txdata_in_reg[64*i+8*8-1-6   :64*i+8*7 ], iog_dq_txdata_in_reg_2[64*i+8*8-1   :64*i+8*7 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*7-1-6   :64*i+8*6 ], iog_dq_txdata_in_reg_2[64*i+8*7-1   :64*i+8*6 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*6-1-6   :64*i+8*5 ], iog_dq_txdata_in_reg_2[64*i+8*6-1   :64*i+8*5 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*5-1-6   :64*i+8*4 ], iog_dq_txdata_in_reg_2[64*i+8*5-1   :64*i+8*4 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*4-1-6   :64*i+8*3 ], iog_dq_txdata_in_reg_2[64*i+8*4-1   :64*i+8*3 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*3-1-6   :64*i+8*2 ], iog_dq_txdata_in_reg_2[64*i+8*3-1   :64*i+8*2 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*2-1-6   :64*i+8*1 ], iog_dq_txdata_in_reg_2[64*i+8*2-1   :64*i+8*1 + 2 ] },
            { iog_dq_txdata_in_reg[64*i+8*1-1-6   :64*i+8*0 ], iog_dq_txdata_in_reg_2[64*i+8*1-1   :64*i+8*0 + 2 ] }
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in_reg[8*(i+1)-1-6:(8*i)], iog_dm_txdata_in_reg_2[8*(i+1)-1:(8*i)+2] 
          };
          
          iog_oe_p0[i] <= iog_oe_p1_reg_2[i];
          iog_oe_p1[i] <= iog_oe_p2_reg_2[i];
          iog_oe_p2[i] <= iog_oe_p3_reg_2[i];
          iog_oe_p3[i] <= iog_oe_p0_reg  [i];
          
          dqs_oe_p0[i] <= dqs_oe_p1_reg_2[i];
          dqs_oe_p1[i] <= dqs_oe_p2_reg_2[i];
          dqs_oe_p2[i] <= dqs_oe_p3_reg_2[i];
          dqs_oe_p3[i] <= dqs_oe_p0_reg  [i];
          
          dm_oe_p0[i]  <= dm_oe_p1_reg_2[i];
          dm_oe_p1[i]  <= dm_oe_p2_reg_2[i];
          dm_oe_p2[i]  <= dm_oe_p3_reg_2[i];
          dm_oe_p3[i]  <= dm_oe_p0_reg  [i];
          
        end
        
      default:
        begin
          iog_dq_txdata_out[64*(i+1)-1    :64*i] <= {
            {iog_dq_txdata_in[64*i+8*8-1   :64*i+8*7 ]},
            {iog_dq_txdata_in[64*i+8*7-1   :64*i+8*6 ]},
            {iog_dq_txdata_in[64*i+8*6-1   :64*i+8*5 ]},
            {iog_dq_txdata_in[64*i+8*5-1   :64*i+8*4 ]},
            {iog_dq_txdata_in[64*i+8*4-1   :64*i+8*3 ]},
            {iog_dq_txdata_in[64*i+8*3-1   :64*i+8*2 ]},
            {iog_dq_txdata_in[64*i+8*2-1   :64*i+8*1 ]},
            {iog_dq_txdata_in[64*i+8*1-1   :64*i+8*0 ]}
          };
          
          iog_dm_txdata_out[8*(i+1)-1:(8*i)] <= {
            iog_dm_txdata_in[8*(i+1)-1:(8*i)]
          };
          
          iog_oe_p0[i] <= iog_oe_p0_internal[i];
          iog_oe_p1[i] <= iog_oe_p1_internal[i];
          iog_oe_p2[i] <= iog_oe_p2_internal[i];
          iog_oe_p3[i] <= iog_oe_p3_internal[i];
          
          dqs_oe_p0[i] <= dqs_oe_p0_internal[i];
          dqs_oe_p1[i] <= dqs_oe_p1_internal[i];
          dqs_oe_p2[i] <= dqs_oe_p2_internal[i];
          dqs_oe_p3[i] <= dqs_oe_p3_internal[i];
          
          dm_oe_p0[i]  <= dm_oe_p0_internal[i];
          dm_oe_p1[i]  <= dm_oe_p1_internal[i];
          dm_oe_p2[i]  <= dm_oe_p2_internal[i];
          dm_oe_p3[i]  <= dm_oe_p3_internal[i];
        end
      
      
    endcase
  end
end
endgenerate







integer j;
generate

for (i=0; i<IOG_DQS_LANES; i=i+1) 
begin : per_lane	
	
	always @(posedge SCLK or negedge reset_n)
	begin
		if(!reset_n)
		begin
			odt_dyn_on[i][HOLD_ODT_CYCLES-1:0] <= 0;
		end	
		else
		begin

			if(iog_rddata_en_p0_p[i] || dfi_rddata_en_p3) 
			begin
				odt_dyn_on[i][0] <= 1;
			end
			else
			begin
				odt_dyn_on[i][0] <= 0;
			end
			
			for(j = 1 ; j<(HOLD_ODT_CYCLES); j=j+1)
				odt_dyn_on[i][j] <= odt_dyn_on[i][j-1];	
		end
	end


	assign odt_dyn_lane[i] = (|odt_dyn_on[i]) | dfi_rddata_en_p3;		
	
end
endgenerate







assign trn_delay_line_sel = (dfi_wrlvl_en | !dfi_init_complete) ? 'h0 : (2**IOG_DQS_LANES)-1;




reg dfi_wrdata_en_p3_reg;

always @( posedge SCLK or negedge reset_n )
begin   : wdata_en_registering

  if (!(reset_n))
  begin
    dfi_wrdata_en_p3_reg <= 0;
  end
  else
  begin
    dfi_wrdata_en_p3_reg <= dfi_wrdata_en_p3;
  end
end


assign iog_oe_p0_internal = (dfi_wrlvl_en) ? {IOG_DQS_LANES{1'b0}} : (dfi_wrdata_en_p0|dfi_wrdata_en_p3_reg) ? (2**IOG_DQS_LANES)-1:'h0;
assign iog_oe_p1_internal = (dfi_wrlvl_en) ? {IOG_DQS_LANES{1'b0}} : (dfi_wrdata_en_p1|dfi_wrdata_en_p0)	? (2**IOG_DQS_LANES)-1:'h0;
assign iog_oe_p2_internal = (dfi_wrlvl_en) ? {IOG_DQS_LANES{1'b0}} : (dfi_wrdata_en_p2|dfi_wrdata_en_p1)	? (2**IOG_DQS_LANES)-1:'h0;
assign iog_oe_p3_internal = (dfi_wrlvl_en) ? {IOG_DQS_LANES{1'b0}} : (dfi_wrdata_en_p3|dfi_wrdata_en_p2)	? (2**IOG_DQS_LANES)-1:'h0;

assign dm_oe_p0_internal = (!dfi_init_complete ) ? {IOG_DQS_LANES{1'b1}} : iog_oe_p0_internal;
assign dm_oe_p1_internal = (!dfi_init_complete ) ? {IOG_DQS_LANES{1'b1}} : iog_oe_p1_internal;
assign dm_oe_p2_internal = (!dfi_init_complete ) ? {IOG_DQS_LANES{1'b1}} : iog_oe_p2_internal;
assign dm_oe_p3_internal = (!dfi_init_complete ) ? {IOG_DQS_LANES{1'b1}} : iog_oe_p3_internal;


assign dqs_oe_p0_internal = (!dfi_init_complete | dfi_wrlvl_en) ?  {IOG_DQS_LANES{1'b1}} : (dfi_wrdata_en_p0|dfi_wrdata_en_p3_reg) ? (2**IOG_DQS_LANES)-1:'h0;
assign dqs_oe_p1_internal = (!dfi_init_complete | dfi_wrlvl_en) ?  {IOG_DQS_LANES{1'b1}} : (dfi_wrdata_en_p1|dfi_wrdata_en_p0)	? (2**IOG_DQS_LANES)-1:'h0;
assign dqs_oe_p2_internal = (!dfi_init_complete | dfi_wrlvl_en) ?  {IOG_DQS_LANES{1'b1}} : (dfi_wrdata_en_p2|dfi_wrdata_en_p1)	? (2**IOG_DQS_LANES)-1:'h0;
assign dqs_oe_p3_internal = (!dfi_init_complete | dfi_wrlvl_en) ?  {IOG_DQS_LANES{1'b1}} : (dfi_wrdata_en_p3|dfi_wrdata_en_p2)	? (2**IOG_DQS_LANES)-1:'h0;









assign dfi_rddata_cs_0_n = dfi_rddata_cs_0_n_p3;
assign dfi_rddata_cs_1_n = dfi_rddata_cs_1_n_p3;

assign select_rank_1 = apb_iog_on ? apb_ctrl_chip_sel : select_rank_1_gt;


endmodule