data/full_repos/permissive/122777989/verilog/uart.v
1: b"%Error: data/full_repos/permissive/122777989/verilog/uart.v:57: Cannot find file containing module: 'UartTx'\nUartTx #(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122777989/verilog,data/full_repos/permissive/122777989/UartTx\n             data/full_repos/permissive/122777989/verilog,data/full_repos/permissive/122777989/UartTx.v\n             data/full_repos/permissive/122777989/verilog,data/full_repos/permissive/122777989/UartTx.sv\n             UartTx\n             UartTx.v\n             UartTx.sv\n             obj_dir/UartTx\n             obj_dir/UartTx.v\n             obj_dir/UartTx.sv\n%Error: data/full_repos/permissive/122777989/verilog/uart.v:73: Cannot find file containing module: 'UartRx'\nUartRx #(\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Uart #(






  parameter CLOCK_DIVIDER_WIDTH = 16
) (

  input reset_i,


  input clock_i,



  input [CLOCK_DIVIDER_WIDTH - 1:0] clock_divider_i,


  input serial_i,


  output serial_o,


  input [7:0] data_i,


  output [7:0] data_o,


  input write_i,


  output write_busy_o,



  output read_ready_o,


  input ack_i,


  input two_stop_bits_i,


  input parity_bit_i,


  input parity_even_i
);

UartTx #(
  .CLOCK_DIVIDER_WIDTH(CLOCK_DIVIDER_WIDTH)
)
uart_tx (
  .reset_i(reset_i),
  .clock_i(clock_i),
  .write_i(write_i),
  .two_stop_bits_i(two_stop_bits_i),
  .parity_bit_i(parity_bit_i),
  .parity_even_i(parity_even_i),
  .clock_divider_i(clock_divider_i),
  .data_i(data_i),
  .busy_o(write_busy_o),
  .serial_o(serial_o)
);

UartRx #(
  .CLOCK_DIVIDER_WIDTH(CLOCK_DIVIDER_WIDTH)
)
uart_rx (
  .reset_i(reset_i),
  .clock_i(clock_i),
  .ack_i(ack_i),
  .parity_bit_i(parity_bit_i),
  .parity_even_i(parity_even_i),
  .serial_i(serial_i),
  .clock_divider_i(clock_divider_i),
  .data_o(data_o),
  .ready_o(read_ready_o)
);

endmodule
module Uart #(






  parameter CLOCK_DIVIDER_WIDTH = 16
) (

  input reset_i,


  input clock_i,



  input [CLOCK_DIVIDER_WIDTH - 1:0] clock_divider_i,


  input serial_i,


  output serial_o,


  input [7:0] data_i,


  output [7:0] data_o,


  input write_i,


  output write_busy_o,



  output read_ready_o,


  input ack_i,


  input two_stop_bits_i,


  input parity_bit_i,


  input parity_even_i
);


UartTx #(
  .CLOCK_DIVIDER_WIDTH(CLOCK_DIVIDER_WIDTH)
)
uart_tx (
  .reset_i(reset_i),
  .clock_i(clock_i),
  .write_i(write_i),
  .two_stop_bits_i(two_stop_bits_i),
  .parity_bit_i(parity_bit_i),
  .parity_even_i(parity_even_i),
  .clock_divider_i(clock_divider_i),
  .data_i(data_i),
  .busy_o(write_busy_o),
  .serial_o(serial_o)
);

UartRx #(
  .CLOCK_DIVIDER_WIDTH(CLOCK_DIVIDER_WIDTH)
)
uart_rx (
  .reset_i(reset_i),
  .clock_i(clock_i),
  .ack_i(ack_i),
  .parity_bit_i(parity_bit_i),
  .parity_even_i(parity_even_i),
  .serial_i(serial_i),
  .clock_divider_i(clock_divider_i),
  .data_o(data_o),
  .ready_o(read_ready_o)
);

endmodule