data/full_repos/permissive/20688874/viterbi/cencodertb.v
1: b'%Error: data/full_repos/permissive/20688874/viterbi/cencodertb.v:25: Cannot find include file: cencoder.v\n`include "cencoder.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/cencoder.v\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/cencoder.v.v\n             data/full_repos/permissive/20688874/viterbi,data/full_repos/permissive/20688874/cencoder.v.sv\n             cencoder.v\n             cencoder.v.v\n             cencoder.v.sv\n             obj_dir/cencoder.v\n             obj_dir/cencoder.v.v\n             obj_dir/cencoder.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:68: Unsupported: Ignoring delay on this delayed statement.\n     #5 ck = 0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:69: Unsupported: Ignoring delay on this delayed statement.\n     #5 ck = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #7;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #9;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:137: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:143: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:149: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:155: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:161: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:167: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:173: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #9;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:185: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:191: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:197: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20688874/viterbi/cencodertb.v:202: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: Exiting due to 1 error(s), 18 warning(s)\n'
module tb_cencoder();

	

	wire [1:0] cout;
	

	reg bin;
	reg ck;
	reg rset;
	
	
	
	
	

	always begin

    	#5 ck = 0;
    	#5 ck = 1;
    end	
	
	
	
	
	

	conv_encoder enc (


		cout,bin,ck,rset);
	

	

	initial
	begin

		$display(" << Starting the simulation >>");

		bin = 1'b0;
		rset=0;
		

		#3;
		bin = 1'b1;
		rset=0;
		
		

		#7;
		bin = 1'b0;
		rset=0;
		
		

		#9;
		bin = 1'b1;
		rset=0;
		
		

		#10;
		bin = 1'b0;
		rset=0;
		
		

		#10;
		bin = 1'b1;
		rset=0;
		
		

		#10;
		bin = 1'b0;
		rset=0;
		
		

		#10;
		bin = 1'b1;
		rset=0;
		
		

		#10;
		bin = 1'b0;
		rset=0;
		
		

		#10;
		bin = 1'b0;
		rset=0;
		
		

		#10;
		bin = 1'b1;
		rset=0;
		
		

		#10;
		bin = 1'b1;
		rset=1;
		
		

		#9;
		bin = 1'b0;
		rset=0;
		
		

		#10;
		bin = 1'b1;
		rset=0;
		
		

		#10;
		bin = 1'b0;
		rset=0;
		
		

		#10;
		bin = 1'b1;
		rset=1;
		
		
		#20;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_cencoder();


	

	wire [1:0] cout;
	

	reg bin;
	reg ck;
	reg rset;
	
	
	
	
	

	always begin

    	#5 ck = 0;
    	#5 ck = 1;
    end	
	
	
	
	
	

	conv_encoder enc (


		cout,bin,ck,rset);
	

	

	initial
	begin

		$display(" << Starting the simulation >>");

		bin = 1'b0;
		rset=0;
		

		#3;
		bin = 1'b1;
		rset=0;
		
		

		#7;
		bin = 1'b0;
		rset=0;
		
		

		#9;
		bin = 1'b1;
		rset=0;
		
		

		#10;
		bin = 1'b0;
		rset=0;
		
		

		#10;
		bin = 1'b1;
		rset=0;
		
		

		#10;
		bin = 1'b0;
		rset=0;
		
		

		#10;
		bin = 1'b1;
		rset=0;
		
		

		#10;
		bin = 1'b0;
		rset=0;
		
		

		#10;
		bin = 1'b0;
		rset=0;
		
		

		#10;
		bin = 1'b1;
		rset=0;
		
		

		#10;
		bin = 1'b1;
		rset=1;
		
		

		#9;
		bin = 1'b0;
		rset=0;
		
		

		#10;
		bin = 1'b1;
		rset=0;
		
		

		#10;
		bin = 1'b0;
		rset=0;
		
		

		#10;
		bin = 1'b1;
		rset=1;
		
		
		#20;
		
		$display(" << Finishing the simulation >>");
		$finish;
	end

endmodule