data/full_repos/permissive/165160692/04.FPGA/5932_74HC148/stimulus/testbench148.v
 line:11: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC148/stimulus/testbench148.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #20 DataIn=$random;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/165160692/04.FPGA/5932_74HC148/stimulus/testbench148.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #20 EI=0;\n  ^\n%Error: data/full_repos/permissive/165160692/04.FPGA/5932_74HC148/stimulus/testbench148.v:7: Cannot find file containing module: \'HC148\'\nHC148 u1(DataIn,EO,Dataout,EI,GS);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC148/stimulus,data/full_repos/permissive/165160692/HC148\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC148/stimulus,data/full_repos/permissive/165160692/HC148.v\n             data/full_repos/permissive/165160692/04.FPGA/5932_74HC148/stimulus,data/full_repos/permissive/165160692/HC148.sv\n             HC148\n             HC148.v\n             HC148.sv\n             obj_dir/HC148\n             obj_dir/HC148.v\n             obj_dir/HC148.sv\n%Warning-WIDTH: data/full_repos/permissive/165160692/04.FPGA/5932_74HC148/stimulus/testbench148.v:12: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                    : ... In instance testbench\n  #20 DataIn=$random;\n            ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
reg[7:0]DataIn;reg EI;
wire[2:0]Dataout;

HC148 u1(DataIn,EO,Dataout,EI,GS);
initial
begin
  DataIn=0;
  repeat(20)
  #20 DataIn=$random;
end

initial
 begin
  EI=1;
  #20 EI=0;
 end
endmodule
module testbench();

reg[7:0]DataIn;reg EI;
wire[2:0]Dataout;

HC148 u1(DataIn,EO,Dataout,EI,GS);
initial
begin
  DataIn=0;
  repeat(20)
  #20 DataIn=$random;
end

initial
 begin
  EI=1;
  #20 EI=0;
 end
endmodule