data/full_repos/permissive/121770408/Master.v
 line:17: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/121770408/Master.v:13: Unsupported: Ignoring delay on this delayed statement.\n#10 ss1 = 0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/121770408/Master.v:24: Unsupported: Ignoring delay on this delayed statement.\n#2 scl = !scl;\n^\n%Error: data/full_repos/permissive/121770408/Master.v:28: syntax error, unexpected IDENTIFIER\nVerilog Code for Slave \n^~~~~~~\n%Error: data/full_repos/permissive/121770408/Master.v:65: Too many digits for 1 bit number: 1\'bx1\nmiso<=1\'bx1;\n      ^~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Slave1(clk,miso,mosi,ss);
input clk;
input [0:0]mosi;
input ss;
output reg[0:0]miso;
reg [7:0] address,data;reg x1;
reg [7:0] arr [0:199];
reg k;
reg [6:0] ione=0;
initial begin
arr[171]=185;
end
always @(mosi)begin
if(ione==0 && ss==0)begin
$display(ione,ss,x1,mosi);
x1 <= mosi;
end
end
always @(posedge clk or mosi)begin
if(ss==0)begin


if(ione>0 && ione<9)begin
address <= {address,mosi};
end


if(ione>8 && ione<17 && x1==1)begin
data <= {data,mosi};
end


else if(ione>8 && ione<17 && x1==0)begin
miso <= arr[address][7];
arr[address]<=arr[address]<<1;
if(ione==16)
miso<=1'bx1;
end


ione<=ione+1;
if(ione>16 && x1==1)
arr[address]<=data;
end

end
endmodule
module Slave1(clk,miso,mosi,ss);

input clk;
input [0:0]mosi;
input ss;
output reg[0:0]miso;
reg [7:0] address,data;reg x1;
reg [7:0] arr [0:199];
reg k;
reg [6:0] ione=0;
initial begin
arr[171]=185;
end
always @(mosi)begin
if(ione==0 && ss==0)begin
$display(ione,ss,x1,mosi);
x1 <= mosi;
end
end
always @(posedge clk or mosi)begin
if(ss==0)begin


if(ione>0 && ione<9)begin
address <= {address,mosi};
end


if(ione>8 && ione<17 && x1==1)begin
data <= {data,mosi};
end


else if(ione>8 && ione<17 && x1==0)begin
miso <= arr[address][7];
arr[address]<=arr[address]<<1;
if(ione==16)
miso<=1'bx1;
end


ione<=ione+1;
if(ione>16 && x1==1)
arr[address]<=data;
end

end
endmodule