data/full_repos/permissive/136009613/acceleratorTB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/136009613/acceleratorTB.v:35: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = !clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136009613/acceleratorTB.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #15 reset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/acceleratorTB.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #15 rwn = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/acceleratorTB.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #1000 rwn = 1; address_test = 16\'h0000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/acceleratorTB.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #100 rwn = 1; address_test = 16\'h0001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/acceleratorTB.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #100 rwn = 1; address_test = 16\'h0002;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/acceleratorTB.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #100 rwn = 1; address_test = 16\'h0003;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/acceleratorTB.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #100 rwn = 1; address_test = 16\'h0004;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/acceleratorTB.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #100 rwn = 1; address_test = 16\'h0005;\n  ^\n%Error: data/full_repos/permissive/136009613/acceleratorTB.v:18: Cannot find file containing module: \'accelerator\'\n accelerator TB(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136009613,data/full_repos/permissive/136009613/accelerator\n             data/full_repos/permissive/136009613,data/full_repos/permissive/136009613/accelerator.v\n             data/full_repos/permissive/136009613,data/full_repos/permissive/136009613/accelerator.sv\n             accelerator\n             accelerator.v\n             accelerator.sv\n             obj_dir/accelerator\n             obj_dir/accelerator.v\n             obj_dir/accelerator.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module acceleratorTB;

	parameter address_size = 16;

	reg clk;
	reg reset;
	reg rwn;
	reg [address_size - 1:0] address_test;
	wire [31:0] data;
	
	
	wire [7:0] rom_address;
	wire [7:0] data_from_rom;
	wire [31:0]	instruction_in;
	wire [31:0]	instruction_out;

	
	accelerator TB(
		.clk(clk),
		.reset(reset),
		.rwn(rwn),
		.address_test(address_test),
		.data(data),
		
		
		
		
		.rom_address(rom_address),
		.data_from_rom(data_from_rom),
		.instruction_in(instruction_in),
		.instruction_out(instruction_out)
	);
	
	initial clk = 0;
	always #5 clk = !clk;
	
	initial reset = 0;
	
	initial
	begin
	
		#15 reset = 1;
		
		#15 rwn = 0;
			
		#1000 rwn = 1; address_test = 16'h0000;
		#100 rwn = 1; address_test = 16'h0001;
		#100 rwn = 1; address_test = 16'h0002;
		#100 rwn = 1; address_test = 16'h0003;
		#100 rwn = 1; address_test = 16'h0004;
		#100 rwn = 1; address_test = 16'h0005;

				

	end
	
endmodule
module acceleratorTB;


	parameter address_size = 16;

	reg clk;
	reg reset;
	reg rwn;
	reg [address_size - 1:0] address_test;
	wire [31:0] data;
	
	
	wire [7:0] rom_address;
	wire [7:0] data_from_rom;
	wire [31:0]	instruction_in;
	wire [31:0]	instruction_out;

	
	accelerator TB(
		.clk(clk),
		.reset(reset),
		.rwn(rwn),
		.address_test(address_test),
		.data(data),
		
		
		
		
		.rom_address(rom_address),
		.data_from_rom(data_from_rom),
		.instruction_in(instruction_in),
		.instruction_out(instruction_out)
	);
	
	initial clk = 0;
	always #5 clk = !clk;
	
	initial reset = 0;
	
	initial
	begin
	
		#15 reset = 1;
		
		#15 rwn = 0;
			
		#1000 rwn = 1; address_test = 16'h0000;
		#100 rwn = 1; address_test = 16'h0001;
		#100 rwn = 1; address_test = 16'h0002;
		#100 rwn = 1; address_test = 16'h0003;
		#100 rwn = 1; address_test = 16'h0004;
		#100 rwn = 1; address_test = 16'h0005;

				

	end
	
endmodule