data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:96: Unsupported: Ignoring delay on this delayed statement.\n            #5 CLKIN = ~CLKIN;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:103: Unsupported: Ignoring delay on this delayed statement.\n             #10 outClk = ~outClk;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:110: Unsupported: Ignoring delay on this delayed statement.\n           #10 inClk = ~inClk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:127: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:131: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:136: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:145: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:147: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:149: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:152: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Error: data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new/Sync_245_Test_Bench.v:75: Cannot find file containing module: \'Sync_245_Controller\'\n    Sync_245_Controller uut( .D(d),\n    ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new,data/full_repos/permissive/123043192/Sync_245_Controller\n             data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new,data/full_repos/permissive/123043192/Sync_245_Controller.v\n             data/full_repos/permissive/123043192/FPGA/USB/Sync245/FT232H/FT232H.srcs/sim_1/new,data/full_repos/permissive/123043192/Sync_245_Controller.sv\n             Sync_245_Controller\n             Sync_245_Controller.v\n             Sync_245_Controller.sv\n             obj_dir/Sync_245_Controller\n             obj_dir/Sync_245_Controller.v\n             obj_dir/Sync_245_Controller.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Sync_245_Test_Bench(

    );
    

    wire [7:0] d;
    reg rxf, txe;
    wire wr, rd, oe;
    reg CLKIN;
    

    reg[7:0] inData;
    reg inClk, inEn;
    
    wire[7:0] outData;
    reg outClk, outEn;
    
    reg rst;
    

    wire [7:0] d_to_host;
    reg [7:0] d_from_host;
    reg d_output_mode;
    
    assign d_to_host = d;
    assign d = (d_output_mode==1'b1)? d_from_host : 8'hZZ;
    
    
    Sync_245_Controller uut( .D(d),
                             .RXF(rxf),
                             .TXE(txe),
                             .WR(wr),
                             .RD(rd),
                             .OE(oe),
                             .CLKOUT(CLKIN),
                             
                             .inputData(inData),
                             .inputClock(inClk),
                             .inputDataGood(inEn),
                             
                             .hostData(outData),
                             .outputClock(outClk),
                             .readData(outEn),
                             
                             .reset(rst));

    initial begin 
        CLKIN = 0;
        forever begin
            #5 CLKIN = ~CLKIN;
        end 
     end
    
    initial begin 
         outClk = 0;
         forever begin
             #10 outClk = ~outClk;
         end 
      end
    
    initial begin 
       inClk = 0;
       forever begin
           #10 inClk = ~inClk;
       end 
    end
    
    initial begin
        $display("Entering Initial state!");
        d_output_mode = 0;
        d_from_host = 8'h00;
        rst = 0;
        rxf = 1;
        txe = 1;
        
        inData = 8'h00;
        inEn = 0;
        
        outEn = 0;
        rst = 1;
        #50;
        rst = 0;
        #50;
        
        #100;
        

        txe = 0;
        inEn = 1;
        #1;

        inData = 8'hAA;
        #20;
        inData = 8'hBB;
        #20;
        inData = 8'hCC;
        #20;
        inData = 8'hDD;
        #20;
        inData = 8'hEE;
        #20;
        inData = 8'hFF;
        #20;
        
        inEn = 0;
        #1000;
        $finish;
    end
endmodule
module Sync_245_Test_Bench(

    );

    

    wire [7:0] d;
    reg rxf, txe;
    wire wr, rd, oe;
    reg CLKIN;
    

    reg[7:0] inData;
    reg inClk, inEn;
    
    wire[7:0] outData;
    reg outClk, outEn;
    
    reg rst;
    

    wire [7:0] d_to_host;
    reg [7:0] d_from_host;
    reg d_output_mode;
    
    assign d_to_host = d;
    assign d = (d_output_mode==1'b1)? d_from_host : 8'hZZ;
    
    
    Sync_245_Controller uut( .D(d),
                             .RXF(rxf),
                             .TXE(txe),
                             .WR(wr),
                             .RD(rd),
                             .OE(oe),
                             .CLKOUT(CLKIN),
                             
                             .inputData(inData),
                             .inputClock(inClk),
                             .inputDataGood(inEn),
                             
                             .hostData(outData),
                             .outputClock(outClk),
                             .readData(outEn),
                             
                             .reset(rst));

    initial begin 
        CLKIN = 0;
        forever begin
            #5 CLKIN = ~CLKIN;
        end 
     end
    
    initial begin 
         outClk = 0;
         forever begin
             #10 outClk = ~outClk;
         end 
      end
    
    initial begin 
       inClk = 0;
       forever begin
           #10 inClk = ~inClk;
       end 
    end
    
    initial begin
        $display("Entering Initial state!");
        d_output_mode = 0;
        d_from_host = 8'h00;
        rst = 0;
        rxf = 1;
        txe = 1;
        
        inData = 8'h00;
        inEn = 0;
        
        outEn = 0;
        rst = 1;
        #50;
        rst = 0;
        #50;
        
        #100;
        

        txe = 0;
        inEn = 1;
        #1;

        inData = 8'hAA;
        #20;
        inData = 8'hBB;
        #20;
        inData = 8'hCC;
        #20;
        inData = 8'hDD;
        #20;
        inData = 8'hEE;
        #20;
        inData = 8'hFF;
        #20;
        
        inEn = 0;
        #1000;
        $finish;
    end
endmodule