data/full_repos/permissive/143278/ivltests/vhdl_loop.v
 line:24: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_loop.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_loop.v:25: Cannot find file containing module: \'vhdl_loop\'\nvhdl_loop dut(start, counter);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_loop\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_loop.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_loop.sv\n             vhdl_loop\n             vhdl_loop.v\n             vhdl_loop.sv\n             obj_dir/vhdl_loop\n             obj_dir/vhdl_loop.v\n             obj_dir/vhdl_loop.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vhdl_loop_test;
logic start;
int counter;
vhdl_loop dut(start, counter);

initial begin
    for(int i = 0; i < 5; ++i) begin
        if(counter !== i) begin
            $display("FAILED");
            $finish();
        end

        #10;
    end

    $display("PASSED");
    $finish();
end
endmodule
module vhdl_loop_test;

logic start;
int counter;
vhdl_loop dut(start, counter);

initial begin
    for(int i = 0; i < 5; ++i) begin
        if(counter !== i) begin
            $display("FAILED");
            $finish();
        end

        #10;
    end

    $display("PASSED");
    $finish();
end
endmodule