data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v
1: b'%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:95: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:117: Define or directive not defined: \'`E203_PC_SIZE\'\n input  [`E203_PC_SIZE-1:0] pc_rtvec,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:126: Define or directive not defined: \'`E203_PC_SIZE\'\n output  [`E203_PC_SIZE-1:0] cmt_dpc,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:135: Define or directive not defined: \'`E203_PC_SIZE\'\n input  [`E203_PC_SIZE-1:0] dpc_r     ,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:149: Define or directive not defined: \'`E203_HART_ID_W\'\n input  [`E203_HART_ID_W-1:0] core_mhartid,  \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:161: Define or directive not defined: \'`E203_ADDR_SIZE\'\n output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:163: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:164: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:164: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,\n                   ^\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:170: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:177: Define or directive not defined: \'`E203_ADDR_SIZE\'\n output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:179: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:180: Define or directive not defined: \'`E203_XLEN\'\n output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:186: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_cpu_top.v:220: syntax error, unexpected assign\n assign plic_icb_rsp_excl_ok  = 1\'b0;\n ^~~~~~\n%Error: Exiting due to 15 error(s)\n'
module e203_cpu_top(

	output inspect_dbg_irq,

	output inspect_core_clk,

	output core_csr_clk,

	



	output core_wfi,




	output tm_stop,


	input  [`E203_PC_SIZE-1:0] pc_rtvec,





	output  dbg_irq_r,


	output  [`E203_PC_SIZE-1:0] cmt_dpc,
	output  cmt_dpc_ena,
	output  [3-1:0] cmt_dcause,
	output  cmt_dcause_ena,
	output  wr_dcsr_ena    ,
	output  wr_dpc_ena     ,
	output  wr_dscratch_ena,
	output  [32-1:0] wr_csr_nxt    ,
	input  [32-1:0] dcsr_r    ,
	input  [`E203_PC_SIZE-1:0] dpc_r     ,
	input  [32-1:0] dscratch_r,












	input  [`E203_HART_ID_W-1:0] core_mhartid,  


	input  ext_irq_a,

	input  sft_irq_a,

	input  tmr_irq_a,
  	

	output                         clint_icb_cmd_valid,
	input                          clint_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, 
	output                         clint_icb_cmd_read, 
	output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,


	input                          clint_icb_rsp_valid,
	output                         clint_icb_rsp_ready,
	input                          clint_icb_rsp_err  ,
	input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,




	output                         plic_icb_cmd_valid,
	input                          plic_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, 
	output                         plic_icb_cmd_read, 
	output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,


	input                          plic_icb_rsp_valid,
	output                         plic_icb_rsp_ready,
	input                          plic_icb_rsp_err  ,
	input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,



	input  clk,


	input  rst_n
);





`ifndef E203_HAS_LOCKSTEP

	wire plic_icb_rsp_excl_ok  ;
	wire clint_icb_rsp_excl_ok ;


`ifdef E203_HAS_PLIC
	wire plic_icb_enable;
	wire [`E203_ADDR_SIZE-1:0] plic_region_indic;
`endif

`ifdef E203_HAS_CLINT
	wire clint_icb_enable;
	wire [`E203_ADDR_SIZE-1:0] clint_region_indic;
`endif


`endif


	assign plic_icb_rsp_excl_ok  = 1'b0;
	assign clint_icb_rsp_excl_ok = 1'b0;


	`ifdef E203_HAS_PLIC
	assign plic_icb_enable = 1'b1;
	assign plic_region_indic = `E203_PLIC_ADDR_BASE;
	`else
	assign plic_icb_enable = 1'b0;
	`endif

	`ifdef E203_HAS_CLINT
	assign clint_icb_enable = 1'b1;
	assign clint_region_indic = `E203_CLINT_ADDR_BASE;
	`else
	assign clint_icb_enable = 1'b0;
	`endif



e203_cpu #(.MASTER(1)) u_e203_cpu(
	.inspect_dbg_irq          (inspect_dbg_irq      ),

	.inspect_core_clk         (inspect_core_clk     ),


	.core_csr_clk          (core_csr_clk      ),


	.tm_stop (tm_stop),
	.pc_rtvec(pc_rtvec),

	.core_wfi        (core_wfi),
	.dbg_irq_r       (dbg_irq_r      ),

	.cmt_dpc         (cmt_dpc        ),
	.cmt_dpc_ena     (cmt_dpc_ena    ),
	.cmt_dcause      (cmt_dcause     ),
	.cmt_dcause_ena  (cmt_dcause_ena ),

	.wr_dcsr_ena     (wr_dcsr_ena    ),
	.wr_dpc_ena      (wr_dpc_ena     ),
	.wr_dscratch_ena (wr_dscratch_ena),


									 
	.wr_csr_nxt      (wr_csr_nxt    ),
									 
	.dcsr_r          (dcsr_r         ),
	.dpc_r           (dpc_r          ),
	.dscratch_r      (dscratch_r     ),







	.core_mhartid    (core_mhartid),  

	.ext_irq_a       (ext_irq_a),
	.sft_irq_a       (sft_irq_a),
	.tmr_irq_a       (tmr_irq_a),

	.clint_region_indic      (clint_region_indic),
	.clint_icb_enable        (clint_icb_enable),
	.clint_icb_cmd_valid     (clint_icb_cmd_valid),
	.clint_icb_cmd_ready     (clint_icb_cmd_ready),
	.clint_icb_cmd_addr      (clint_icb_cmd_addr ),
	.clint_icb_cmd_read      (clint_icb_cmd_read ),
	.clint_icb_cmd_wdata     (clint_icb_cmd_wdata),
	.clint_icb_cmd_wmask     (clint_icb_cmd_wmask),
	.clint_icb_cmd_lock      (),
	.clint_icb_cmd_excl      (),
	.clint_icb_cmd_size      (),
	
	.clint_icb_rsp_valid     (clint_icb_rsp_valid),
	.clint_icb_rsp_ready     (clint_icb_rsp_ready),
	.clint_icb_rsp_err       (clint_icb_rsp_err  ),
	.clint_icb_rsp_excl_ok   (clint_icb_rsp_excl_ok  ),
	.clint_icb_rsp_rdata     (clint_icb_rsp_rdata),

	.plic_region_indic      (plic_region_indic),
	.plic_icb_enable        (plic_icb_enable),
	.plic_icb_cmd_valid     (plic_icb_cmd_valid),
	.plic_icb_cmd_ready     (plic_icb_cmd_ready),
	.plic_icb_cmd_addr      (plic_icb_cmd_addr ),
	.plic_icb_cmd_read      (plic_icb_cmd_read ),
	.plic_icb_cmd_wdata     (plic_icb_cmd_wdata),
	.plic_icb_cmd_wmask     (plic_icb_cmd_wmask),
	.plic_icb_cmd_lock      (),
	.plic_icb_cmd_excl      (),
	.plic_icb_cmd_size      (),
	
	.plic_icb_rsp_valid     (plic_icb_rsp_valid),
	.plic_icb_rsp_ready     (plic_icb_rsp_ready),
	.plic_icb_rsp_err       (plic_icb_rsp_err  ),
	.plic_icb_rsp_excl_ok   (plic_icb_rsp_excl_ok  ),
	.plic_icb_rsp_rdata     (plic_icb_rsp_rdata),




`ifndef E203_HAS_LOCKSTEP
`endif
	.rst_n         (rst_n),
	.clk           (clk  ) 

  );



		

		 


endmodule
module e203_cpu_top(

	output inspect_dbg_irq,

	output inspect_core_clk,

	output core_csr_clk,

	



	output core_wfi,




	output tm_stop,


	input  [`E203_PC_SIZE-1:0] pc_rtvec,





	output  dbg_irq_r,


	output  [`E203_PC_SIZE-1:0] cmt_dpc,
	output  cmt_dpc_ena,
	output  [3-1:0] cmt_dcause,
	output  cmt_dcause_ena,
	output  wr_dcsr_ena    ,
	output  wr_dpc_ena     ,
	output  wr_dscratch_ena,
	output  [32-1:0] wr_csr_nxt    ,
	input  [32-1:0] dcsr_r    ,
	input  [`E203_PC_SIZE-1:0] dpc_r     ,
	input  [32-1:0] dscratch_r,












	input  [`E203_HART_ID_W-1:0] core_mhartid,  


	input  ext_irq_a,

	input  sft_irq_a,

	input  tmr_irq_a,
  	

	output                         clint_icb_cmd_valid,
	input                          clint_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   clint_icb_cmd_addr, 
	output                         clint_icb_cmd_read, 
	output [`E203_XLEN-1:0]        clint_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      clint_icb_cmd_wmask,


	input                          clint_icb_rsp_valid,
	output                         clint_icb_rsp_ready,
	input                          clint_icb_rsp_err  ,
	input  [`E203_XLEN-1:0]        clint_icb_rsp_rdata,




	output                         plic_icb_cmd_valid,
	input                          plic_icb_cmd_ready,
	output [`E203_ADDR_SIZE-1:0]   plic_icb_cmd_addr, 
	output                         plic_icb_cmd_read, 
	output [`E203_XLEN-1:0]        plic_icb_cmd_wdata,
	output [`E203_XLEN/8-1:0]      plic_icb_cmd_wmask,


	input                          plic_icb_rsp_valid,
	output                         plic_icb_rsp_ready,
	input                          plic_icb_rsp_err  ,
	input  [`E203_XLEN-1:0]        plic_icb_rsp_rdata,



	input  clk,


	input  rst_n
);






`ifndef E203_HAS_LOCKSTEP

	wire plic_icb_rsp_excl_ok  ;
	wire clint_icb_rsp_excl_ok ;


`ifdef E203_HAS_PLIC
	wire plic_icb_enable;
	wire [`E203_ADDR_SIZE-1:0] plic_region_indic;
`endif

`ifdef E203_HAS_CLINT
	wire clint_icb_enable;
	wire [`E203_ADDR_SIZE-1:0] clint_region_indic;
`endif


`endif


	assign plic_icb_rsp_excl_ok  = 1'b0;
	assign clint_icb_rsp_excl_ok = 1'b0;


	`ifdef E203_HAS_PLIC
	assign plic_icb_enable = 1'b1;
	assign plic_region_indic = `E203_PLIC_ADDR_BASE;
	`else
	assign plic_icb_enable = 1'b0;
	`endif

	`ifdef E203_HAS_CLINT
	assign clint_icb_enable = 1'b1;
	assign clint_region_indic = `E203_CLINT_ADDR_BASE;
	`else
	assign clint_icb_enable = 1'b0;
	`endif



e203_cpu #(.MASTER(1)) u_e203_cpu(
	.inspect_dbg_irq          (inspect_dbg_irq      ),

	.inspect_core_clk         (inspect_core_clk     ),


	.core_csr_clk          (core_csr_clk      ),


	.tm_stop (tm_stop),
	.pc_rtvec(pc_rtvec),

	.core_wfi        (core_wfi),
	.dbg_irq_r       (dbg_irq_r      ),

	.cmt_dpc         (cmt_dpc        ),
	.cmt_dpc_ena     (cmt_dpc_ena    ),
	.cmt_dcause      (cmt_dcause     ),
	.cmt_dcause_ena  (cmt_dcause_ena ),

	.wr_dcsr_ena     (wr_dcsr_ena    ),
	.wr_dpc_ena      (wr_dpc_ena     ),
	.wr_dscratch_ena (wr_dscratch_ena),


									 
	.wr_csr_nxt      (wr_csr_nxt    ),
									 
	.dcsr_r          (dcsr_r         ),
	.dpc_r           (dpc_r          ),
	.dscratch_r      (dscratch_r     ),







	.core_mhartid    (core_mhartid),  

	.ext_irq_a       (ext_irq_a),
	.sft_irq_a       (sft_irq_a),
	.tmr_irq_a       (tmr_irq_a),

	.clint_region_indic      (clint_region_indic),
	.clint_icb_enable        (clint_icb_enable),
	.clint_icb_cmd_valid     (clint_icb_cmd_valid),
	.clint_icb_cmd_ready     (clint_icb_cmd_ready),
	.clint_icb_cmd_addr      (clint_icb_cmd_addr ),
	.clint_icb_cmd_read      (clint_icb_cmd_read ),
	.clint_icb_cmd_wdata     (clint_icb_cmd_wdata),
	.clint_icb_cmd_wmask     (clint_icb_cmd_wmask),
	.clint_icb_cmd_lock      (),
	.clint_icb_cmd_excl      (),
	.clint_icb_cmd_size      (),
	
	.clint_icb_rsp_valid     (clint_icb_rsp_valid),
	.clint_icb_rsp_ready     (clint_icb_rsp_ready),
	.clint_icb_rsp_err       (clint_icb_rsp_err  ),
	.clint_icb_rsp_excl_ok   (clint_icb_rsp_excl_ok  ),
	.clint_icb_rsp_rdata     (clint_icb_rsp_rdata),

	.plic_region_indic      (plic_region_indic),
	.plic_icb_enable        (plic_icb_enable),
	.plic_icb_cmd_valid     (plic_icb_cmd_valid),
	.plic_icb_cmd_ready     (plic_icb_cmd_ready),
	.plic_icb_cmd_addr      (plic_icb_cmd_addr ),
	.plic_icb_cmd_read      (plic_icb_cmd_read ),
	.plic_icb_cmd_wdata     (plic_icb_cmd_wdata),
	.plic_icb_cmd_wmask     (plic_icb_cmd_wmask),
	.plic_icb_cmd_lock      (),
	.plic_icb_cmd_excl      (),
	.plic_icb_cmd_size      (),
	
	.plic_icb_rsp_valid     (plic_icb_rsp_valid),
	.plic_icb_rsp_ready     (plic_icb_rsp_ready),
	.plic_icb_rsp_err       (plic_icb_rsp_err  ),
	.plic_icb_rsp_excl_ok   (plic_icb_rsp_excl_ok  ),
	.plic_icb_rsp_rdata     (plic_icb_rsp_rdata),




`ifndef E203_HAS_LOCKSTEP
`endif
	.rst_n         (rst_n),
	.clk           (clk  ) 

  );



		

		 


endmodule