data/full_repos/permissive/143278/ivltests/udp_dff.v
 line:74: before: "primitive"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_dff.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_dff.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (qq !== 1\'b0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_dff.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (qq !== 1\'b0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_dff.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (qq !== 1\'b1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_dff.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (qq !== 1\'b1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_dff.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (qq !== 1\'bx) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_dff.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (qq !== 1\'bx) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_dff.v:58: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (qq !== 1\'bx) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_dff.v:65: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (qq !== 1\'bx) begin\n      ^\n%Warning-PINMISSING: data/full_repos/permissive/143278/ivltests/udp_dff.v:12: Cell has missing pin: \'notifier\'\n   dff d1 (.Q(qq), .C(clk), .D(dd));\n       ^~\n%Error: Exiting due to 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

   reg dd, clk;
   wire qq;
   dff d1 (.Q(qq), .C(clk), .D(dd));

   initial begin
      dd = 1'b0;
      clk= 0;

      #1 clk = 1;
      #1 if (qq !== 1'b0) begin
	 $display("FAILED -- D=%b, Q=%b", dd, qq);
	 $finish;
      end
      dd = 1'b1;

      clk = 0;
      #1 if (qq !== 1'b0) begin
	 $display("FAILED -- D=%b (hold 0), Q=%b", dd, qq);
	 $finish;
      end

      clk = 1;
      #1 if (qq !== 1'b1) begin
	 $display("FAILED -- D=%b, Q=%b", dd, qq);
	 $finish;
      end
      dd = 1'bx;

      clk = 0;
      #1 if (qq !== 1'b1) begin
	 $display("FAILED -- D=%b (hold 1), Q=%b", dd, qq);
	 $finish;
      end

      clk = 1;
      #1 if (qq !== 1'bx) begin
	 $display("FAILED -- D=%b, Q=%b", dd, qq);
	 $finish;
      end
      dd = 1'bz;

      clk = 0;
      #1 if (qq !== 1'bx) begin
	 $display("FAILED -- D=%b (hold x), Q=%b", dd, qq);
	 $finish;
      end

      clk = 1;
      #1 if (qq !== 1'bx) begin
	 $display("FAILED -- D=%b, Q=%b", dd, qq);
	 $finish;
      end
      dd = 1'b0;

      clk = 0;
      #1 if (qq !== 1'bx) begin
	 $display("FAILED -- D=%b (hold x), Q=%b", dd, qq);
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module test;


   reg dd, clk;
   wire qq;
   dff d1 (.Q(qq), .C(clk), .D(dd));

   initial begin
      dd = 1'b0;
      clk= 0;

      #1 clk = 1;
      #1 if (qq !== 1'b0) begin
	 $display("FAILED -- D=%b, Q=%b", dd, qq);
	 $finish;
      end
      dd = 1'b1;

      clk = 0;
      #1 if (qq !== 1'b0) begin
	 $display("FAILED -- D=%b (hold 0), Q=%b", dd, qq);
	 $finish;
      end

      clk = 1;
      #1 if (qq !== 1'b1) begin
	 $display("FAILED -- D=%b, Q=%b", dd, qq);
	 $finish;
      end
      dd = 1'bx;

      clk = 0;
      #1 if (qq !== 1'b1) begin
	 $display("FAILED -- D=%b (hold 1), Q=%b", dd, qq);
	 $finish;
      end

      clk = 1;
      #1 if (qq !== 1'bx) begin
	 $display("FAILED -- D=%b, Q=%b", dd, qq);
	 $finish;
      end
      dd = 1'bz;

      clk = 0;
      #1 if (qq !== 1'bx) begin
	 $display("FAILED -- D=%b (hold x), Q=%b", dd, qq);
	 $finish;
      end

      clk = 1;
      #1 if (qq !== 1'bx) begin
	 $display("FAILED -- D=%b, Q=%b", dd, qq);
	 $finish;
      end
      dd = 1'b0;

      clk = 0;
      #1 if (qq !== 1'bx) begin
	 $display("FAILED -- D=%b (hold x), Q=%b", dd, qq);
	 $finish;
      end

      $display("PASSED");
   end
endmodule