data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_pipeline.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_pipeline.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim/test_pipeline.v:31: Cannot find file containing module: \'MipsCPU28_Pipeline\'\n    MipsCPU28_Pipeline MIPS_CPU(\n    ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim,data/full_repos/permissive/171720620/MipsCPU28_Pipeline\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim,data/full_repos/permissive/171720620/MipsCPU28_Pipeline.v\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sim,data/full_repos/permissive/171720620/MipsCPU28_Pipeline.sv\n             MipsCPU28_Pipeline\n             MipsCPU28_Pipeline.v\n             MipsCPU28_Pipeline.sv\n             obj_dir/MipsCPU28_Pipeline\n             obj_dir/MipsCPU28_Pipeline.v\n             obj_dir/MipsCPU28_Pipeline.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_pipeline;
    reg clk, go, rst;
    reg [1:0] select;
    wire [11:0] IF_PC;
    wire [11:0] ID_PC;
    wire [11:0] EX_PC;
    wire [11:0] MEM_PC;
    wire [11:0] WB_PC;
    wire [31:0] LedData_out;
    wire [31:0] EX_LedData;
    wire [31:0] WB_LedData;
    wire [31:0] forward1_out;
    wire [31:0] forward2_out;
    wire [1:0] EX_forward1;
    wire [1:0] EX_forward2;

    MipsCPU28_Pipeline MIPS_CPU(
        .clk(clk),
        .CPU_RESETN(rst),
        .go(go),
        .SW15(1),
        .SW(select),
        .IF_PC(IF_PC),
        .ID_PC(ID_PC),
        .EX_PC(EX_PC),
        .MEM_PC(MEM_PC),
        .WB_PC(WB_PC),
        .LedData_out(LedData_out),
        .pcEnable(pcEnable),
        .forward1_out(forward1_out),
        .forward2_out(forward2_out),
        .EX_forward1(EX_forward1),
        .EX_forward2(EX_forward2),
        .WB_LedData(WB_LedData),
        .EX_LedData(EX_LedData),
        .WB_show(WB_show),
        .WB_syscall(WB_syscall)
    );

    initial begin
        select = 2'b11;
        clk = 0;
        go = 1;
        rst = 1;
    end

    always begin
        #10 clk = ~clk;
    end

endmodule
module test_pipeline;

    reg clk, go, rst;
    reg [1:0] select;
    wire [11:0] IF_PC;
    wire [11:0] ID_PC;
    wire [11:0] EX_PC;
    wire [11:0] MEM_PC;
    wire [11:0] WB_PC;
    wire [31:0] LedData_out;
    wire [31:0] EX_LedData;
    wire [31:0] WB_LedData;
    wire [31:0] forward1_out;
    wire [31:0] forward2_out;
    wire [1:0] EX_forward1;
    wire [1:0] EX_forward2;

    MipsCPU28_Pipeline MIPS_CPU(
        .clk(clk),
        .CPU_RESETN(rst),
        .go(go),
        .SW15(1),
        .SW(select),
        .IF_PC(IF_PC),
        .ID_PC(ID_PC),
        .EX_PC(EX_PC),
        .MEM_PC(MEM_PC),
        .WB_PC(WB_PC),
        .LedData_out(LedData_out),
        .pcEnable(pcEnable),
        .forward1_out(forward1_out),
        .forward2_out(forward2_out),
        .EX_forward1(EX_forward1),
        .EX_forward2(EX_forward2),
        .WB_LedData(WB_LedData),
        .EX_LedData(EX_LedData),
        .WB_show(WB_show),
        .WB_syscall(WB_syscall)
    );

    initial begin
        select = 2'b11;
        clk = 0;
        go = 1;
        rst = 1;
    end

    always begin
        #10 clk = ~clk;
    end

endmodule