data/full_repos/permissive/159001439/src/pci_behavioral_target.v
 line:43: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/159001439/src/pci_behavioral_target.v:133: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SUB generates 33 bits.\n                                                                                    : ... In instance pci_behavioral_target\n bar0_mask = BAR0_SIZE-1;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/pci_behavioral_target.v:553: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                    : ... In instance pci_behavioral_target\n  write_addr <= (write_addr + 3\'b100) & bar0_mask;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/159001439/src/pci_behavioral_target.v:563: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                    : ... In instance pci_behavioral_target\n  read_addr <= (read_addr + 3\'b100) & bar0_mask;\n                          ^\n%Error: Exiting due to 3 warning(s)\n'
function [31:0] read(input [31:0] addr);
begin
	read = { 
		mem_b3[addr[MEM_ADDR_MSB:2]], 
		mem_b2[addr[MEM_ADDR_MSB:2]],
		mem_b1[addr[MEM_ADDR_MSB:2]],
		mem_b0[addr[MEM_ADDR_MSB:2]]
	};
end
endfunction
function [31:0] read(input [31:0] addr);

begin
	read = { 
		mem_b3[addr[MEM_ADDR_MSB:2]], 
		mem_b2[addr[MEM_ADDR_MSB:2]],
		mem_b1[addr[MEM_ADDR_MSB:2]],
		mem_b0[addr[MEM_ADDR_MSB:2]]
	};
end
endfunction