data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v
 line:150: before: "if"
1: b'%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:21: Cannot find include file: cpu.v\n`include "cpu.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/cpu,data/full_repos/permissive/200314387/cpu.v\n             data/full_repos/permissive/200314387/verilog/cpu,data/full_repos/permissive/200314387/cpu.v.v\n             data/full_repos/permissive/200314387/verilog/cpu,data/full_repos/permissive/200314387/cpu.v.sv\n             cpu.v\n             cpu.v.v\n             cpu.v.sv\n             obj_dir/cpu.v\n             obj_dir/cpu.v.v\n             obj_dir/cpu.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:22: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:23: Cannot find include file: psuedo_assembler.sv\n`include "psuedo_assembler.sv" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:39: Cannot find include file: ../lib/display_snippet.sv\n   `include "../lib/display_snippet.sv" \n            ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:37: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n    import alu_ops::*;\n           ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:63: Define or directive not defined: \'`DEFINE_CODE_VARS\'\n    `DEFINE_CODE_VARS(MAX_PC)\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:63: syntax error, unexpected \'(\'\n    `DEFINE_CODE_VARS(MAX_PC)\n                      ^~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:78: Define or directive not defined: \'`DEV_EQ_IMMED8\'\n        `DEV_EQ_IMMED8(icount, rega, 64); \n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:78: syntax error, unexpected \',\'\n        `DEV_EQ_IMMED8(icount, rega, 64); \n                             ^\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:79: Define or directive not defined: \'`INSTRUCTION\'\n        `INSTRUCTION(icount, B, pchitmp, not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 60>>8); \n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:79: syntax error, unexpected \',\'\n        `INSTRUCTION(icount, B, pchitmp, not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 60>>8); \n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:79: Define or directive not defined: \'`SET_FLAGS\'\n        `INSTRUCTION(icount, B, pchitmp, not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 60>>8); \n                                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:79: Number is missing value digits: \'C\n        `INSTRUCTION(icount, B, pchitmp, not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 60>>8); \n                                                                          ^~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:79: Define or directive not defined: \'`NA_AMODE\'\n        `INSTRUCTION(icount, B, pchitmp, not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 60>>8); \n                                                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:80: Define or directive not defined: \'`INSTRUCTION\'\n        `INSTRUCTION(icount, B, pc     , not_used, immed, DO, `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 60); \n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:80: syntax error, unexpected \',\'\n        `INSTRUCTION(icount, B, pc     , not_used, immed, DO, `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 60); \n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:80: Define or directive not defined: \'`SET_FLAGS\'\n        `INSTRUCTION(icount, B, pc     , not_used, immed, DO, `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 60); \n                                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:80: Number is missing value digits: \'C\n        `INSTRUCTION(icount, B, pc     , not_used, immed, DO, `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 60); \n                                                                          ^~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:80: Define or directive not defined: \'`NA_AMODE\'\n        `INSTRUCTION(icount, B, pc     , not_used, immed, DO, `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 60); \n                                                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:81: Define or directive not defined: \'`JMP_IMMED16\'\n        `JMP_IMMED16(icount, 0); \n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:81: syntax error, unexpected \',\'\n        `JMP_IMMED16(icount, 0); \n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:84: Define or directive not defined: \'`INSTRUCTION\'\n        `INSTRUCTION(icount, B, uart,   not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 66);\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:84: syntax error, unexpected \',\'\n        `INSTRUCTION(icount, B, uart,   not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 66);\n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:84: Define or directive not defined: \'`SET_FLAGS\'\n        `INSTRUCTION(icount, B, uart,   not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 66);\n                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:84: Number is missing value digits: \'C\n        `INSTRUCTION(icount, B, uart,   not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 66);\n                                                                         ^~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:84: Define or directive not defined: \'`NA_AMODE\'\n        `INSTRUCTION(icount, B, uart,   not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 66);\n                                                                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:85: Define or directive not defined: \'`INSTRUCTION\'\n        `INSTRUCTION(icount, B, halt,   not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 66);\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:85: syntax error, unexpected \',\'\n        `INSTRUCTION(icount, B, halt,   not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 66);\n                           ^\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:85: Define or directive not defined: \'`SET_FLAGS\'\n        `INSTRUCTION(icount, B, halt,   not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 66);\n                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:85: Number is missing value digits: \'C\n        `INSTRUCTION(icount, B, halt,   not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 66);\n                                                                         ^~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:85: Define or directive not defined: \'`NA_AMODE\'\n        `INSTRUCTION(icount, B, halt,   not_used, immed, A,  `SET_FLAGS, \'CM_STD, `NA_AMODE, \'z, 66);\n                                                                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:208: Define or directive not defined: \'`FINISH_AND_RETURN\'\n            `FINISH_AND_RETURN(1);\n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/demo_uart_check.v:208: syntax error, unexpected \';\'\n            `FINISH_AND_RETURN(1);\n                                 ^\n%Error: Exiting due to 33 error(s)\n'
module test();

    import alu_ops::*;

   `include "../lib/display_snippet.sv"

    localparam SETTLE_TOLERANCE=50;


    localparam TCLK=1380;


    logic _RESET_SWITCH;

    logic clk=0;
    
    int exec_count=0;

    cpu CPU(_RESET_SWITCH, clk);





    `define RAM(A) CPU.ram64.Mem[A]
    `define DATA(D) {40'bz, D}

    localparam MAX_PC=100;
    `DEFINE_CODE_VARS(MAX_PC)

    integer LOOP;
    integer ADD_ONE;
    `define WRITE_UART 60
    `define READ_UART 80


    integer icount;
    task INIT_ROM;
    begin


        icount = 0;

        `DEV_EQ_IMMED8(icount, rega, 64); 
        `INSTRUCTION(icount, B, pchitmp, not_used, immed, A,  `SET_FLAGS, 'CM_STD, `NA_AMODE, 'z, `WRITE_UART>>8); 
        `INSTRUCTION(icount, B, pc     , not_used, immed, DO, `SET_FLAGS, 'CM_STD, `NA_AMODE, 'z, `WRITE_UART); 
        `JMP_IMMED16(icount, 0); 

icount = `WRITE_UART;
        `INSTRUCTION(icount, B, uart,   not_used, immed, A,  `SET_FLAGS, 'CM_STD, `NA_AMODE, 'z, 66);
        `INSTRUCTION(icount, B, halt,   not_used, immed, A,  `SET_FLAGS, 'CM_STD, `NA_AMODE, 'z, 66);


    end
    endtask : INIT_ROM

    int HALF_CLK=1500;

    initial begin


        INIT_ROM();

        _RESET_SWITCH = 0;
        clk=0;

        #HALF_CLK
        _RESET_SWITCH = 1;

        #HALF_CLK
        clk=0;

        
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        #HALF_CLK
        clk=1;
        #HALF_CLK

        clk=1;
        #HALF_CLK
        clk=0;
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;

        $display("no more clocks");

    end

    integer pcval;
    assign pcval={CPU.PCHI, CPU.PCLO};
    string_bits currentCode;
    if (1) always @(CPU.PCHI or CPU.PCLO) begin
        $display("");
        $display("%9t ", $time, "INCREMENTED PC=%-d ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^", {CPU.PCHI, CPU.PCLO});
        currentCode = string_bits'(CODE[pcval]);
        $display ("%9t ", $time,  "OPERATION (cycle %1d): ", exec_count, " %-s", currentCode);
    end

    if (1) always @(CPU.phase_exec) begin
        $display("");
        if (CPU.phase_exec) begin
            $display("%9t ", $time, "PC=%-d    ====  ENTERED EXEC PHASE ", {CPU.PCHI, CPU.PCLO});
            $display("%9t ", $time, "_gates_regfie_in ", CPU._gated_regfile_in , " _phase_exec ",  CPU._phase_exec , " _REGA_IN ", CPU._rega_in);
        end
    end


    integer not_initialised = 16'hffff + 1;
    integer last_count = not_initialised;
    integer count;
    integer last_marlo;


    always @( CPU.uart._TXE )
    begin
        $display("%9t", $time, " UART: _TXE %1d ", CPU.uart._TXE);
    end
    always @( CPU.uart._TXE_SUPPRESS )
    begin
        $display("%9t", $time, " UART: _TXE_SUPPRESS %1d ", CPU.uart._TXE_SUPPRESS);
    end

    always @( CPU.uart.WR )
    begin
        $display("%9t", $time, " UART: WR %1d ", CPU.uart.WR);
    end
    always @( * )
    begin
        $display("%9t", $time, " UART: _gated_uart_wr %1d ", CPU._gated_uart_wr, " _uart_in %1d ", CPU._uart_in, " _phase_exec %1d ", CPU._phase_exec);
    end
    

    



    always @(*) begin
        if (CPU._mrPC && CPU.phase_exec && CPU.ctrl.instruction_6 === 'x) begin
            #1

            $display("rom value instruction_6", CPU.ctrl.instruction_6); 
            $error("ERROR END OF PROGRAM - PROGRAM BYTE = XX "); 
            `FINISH_AND_RETURN(1);
        end
    end


endmodule
module test();


    import alu_ops::*;

   `include "../lib/display_snippet.sv"

    localparam SETTLE_TOLERANCE=50;


    localparam TCLK=1380;


    logic _RESET_SWITCH;

    logic clk=0;
    
    int exec_count=0;

    cpu CPU(_RESET_SWITCH, clk);





    `define RAM(A) CPU.ram64.Mem[A]
    `define DATA(D) {40'bz, D}

    localparam MAX_PC=100;
    `DEFINE_CODE_VARS(MAX_PC)

    integer LOOP;
    integer ADD_ONE;
    `define WRITE_UART 60
    `define READ_UART 80


    integer icount;
    task INIT_ROM;
    begin


        icount = 0;

        `DEV_EQ_IMMED8(icount, rega, 64); 
        `INSTRUCTION(icount, B, pchitmp, not_used, immed, A,  `SET_FLAGS, 'CM_STD, `NA_AMODE, 'z, `WRITE_UART>>8); 
        `INSTRUCTION(icount, B, pc     , not_used, immed, DO, `SET_FLAGS, 'CM_STD, `NA_AMODE, 'z, `WRITE_UART); 
        `JMP_IMMED16(icount, 0); 

icount = `WRITE_UART;
        `INSTRUCTION(icount, B, uart,   not_used, immed, A,  `SET_FLAGS, 'CM_STD, `NA_AMODE, 'z, 66);
        `INSTRUCTION(icount, B, halt,   not_used, immed, A,  `SET_FLAGS, 'CM_STD, `NA_AMODE, 'z, 66);


    end
    endtask : INIT_ROM

    int HALF_CLK=1500;

    initial begin


        INIT_ROM();

        _RESET_SWITCH = 0;
        clk=0;

        #HALF_CLK
        _RESET_SWITCH = 1;

        #HALF_CLK
        clk=0;

        
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        #HALF_CLK
        clk=1;
        #HALF_CLK

        clk=1;
        #HALF_CLK
        clk=0;
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;
        #HALF_CLK
        clk=1;
        #HALF_CLK
        clk=0;

        $display("no more clocks");

    end

    integer pcval;
    assign pcval={CPU.PCHI, CPU.PCLO};
    string_bits currentCode;
    if (1) always @(CPU.PCHI or CPU.PCLO) begin
        $display("");
        $display("%9t ", $time, "INCREMENTED PC=%-d ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^", {CPU.PCHI, CPU.PCLO});
        currentCode = string_bits'(CODE[pcval]);
        $display ("%9t ", $time,  "OPERATION (cycle %1d): ", exec_count, " %-s", currentCode);
    end

    if (1) always @(CPU.phase_exec) begin
        $display("");
        if (CPU.phase_exec) begin
            $display("%9t ", $time, "PC=%-d    ====  ENTERED EXEC PHASE ", {CPU.PCHI, CPU.PCLO});
            $display("%9t ", $time, "_gates_regfie_in ", CPU._gated_regfile_in , " _phase_exec ",  CPU._phase_exec , " _REGA_IN ", CPU._rega_in);
        end
    end


    integer not_initialised = 16'hffff + 1;
    integer last_count = not_initialised;
    integer count;
    integer last_marlo;


    always @( CPU.uart._TXE )
    begin
        $display("%9t", $time, " UART: _TXE %1d ", CPU.uart._TXE);
    end
    always @( CPU.uart._TXE_SUPPRESS )
    begin
        $display("%9t", $time, " UART: _TXE_SUPPRESS %1d ", CPU.uart._TXE_SUPPRESS);
    end

    always @( CPU.uart.WR )
    begin
        $display("%9t", $time, " UART: WR %1d ", CPU.uart.WR);
    end
    always @( * )
    begin
        $display("%9t", $time, " UART: _gated_uart_wr %1d ", CPU._gated_uart_wr, " _uart_in %1d ", CPU._uart_in, " _phase_exec %1d ", CPU._phase_exec);
    end
    

    



    always @(*) begin
        if (CPU._mrPC && CPU.phase_exec && CPU.ctrl.instruction_6 === 'x) begin
            #1

            $display("rom value instruction_6", CPU.ctrl.instruction_6); 
            $error("ERROR END OF PROGRAM - PROGRAM BYTE = XX "); 
            `FINISH_AND_RETURN(1);
        end
    end


endmodule