data/full_repos/permissive/19435930/camera_test.v
 line:80: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #42;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #42;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #42;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #42;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #42;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:78: Unsupported: Ignoring delay on this delayed statement.\n always #5 PIXCLK <= ~PIXCLK;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/19435930/camera_test.v:80: Unsupported: Ignoring delay on this delayed statement.\n initial #360 $finish;\n         ^\n%Error: data/full_repos/permissive/19435930/camera_test.v:18: Cannot find file containing module: \'camera\'\n camera #(2,3) uut (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19435930,data/full_repos/permissive/19435930/camera\n             data/full_repos/permissive/19435930,data/full_repos/permissive/19435930/camera.v\n             data/full_repos/permissive/19435930,data/full_repos/permissive/19435930/camera.sv\n             camera\n             camera.v\n             camera.sv\n             obj_dir/camera\n             obj_dir/camera.v\n             obj_dir/camera.sv\n%Error: Exiting due to 1 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module camera_test;


	reg PIXCLK;
	reg LINE_VALID;
	reg FRAME_VALID;
	reg [9:0] DATA_IN;


	wire [9:0] DATA_OUT;
	wire [1:0] CURRENT_LINE;
	wire [0:0] CURRENT_COLUMN;
	wire PIXEL_VALID;


	camera #(2,3) uut (
		.PIXCLK(PIXCLK), 
		.LINE_VALID(LINE_VALID), 
		.FRAME_VALID(FRAME_VALID), 
		.DATA_IN(DATA_IN), 
		.DATA_OUT(DATA_OUT), 
		.CURRENT_LINE(CURRENT_LINE), 
		.CURRENT_COLUMN(CURRENT_COLUMN), 
		.PIXEL_VALID(PIXEL_VALID)
	);

	initial begin

		PIXCLK = 0;
		LINE_VALID = 1;
		FRAME_VALID = 1;
		DATA_IN = 0;

		#42;
		#42;
		#42;
		#42;
		#42;
		LINE_VALID = 0;
		FRAME_VALID = 0;
		#20;
		
		FRAME_VALID = 1;
		
		LINE_VALID = 1;
		DATA_IN = 11;
		#10
		LINE_VALID = 1;
		DATA_IN = 12;
		#10
		LINE_VALID = 0;
		#10
		
		LINE_VALID = 1;
		DATA_IN = 21;
		#10
		LINE_VALID = 1;
		DATA_IN = 22;
		#10
		LINE_VALID = 0;
		#10
		
		LINE_VALID = 1;
		DATA_IN = 31;
		#10
		LINE_VALID = 1;
		DATA_IN = 32;
		#10
		LINE_VALID = 0;
		#10
		
		FRAME_VALID = 0;

	end
      
	always #5 PIXCLK <= ~PIXCLK;
	
	initial #360 $finish;
endmodule
module camera_test;



	reg PIXCLK;
	reg LINE_VALID;
	reg FRAME_VALID;
	reg [9:0] DATA_IN;


	wire [9:0] DATA_OUT;
	wire [1:0] CURRENT_LINE;
	wire [0:0] CURRENT_COLUMN;
	wire PIXEL_VALID;


	camera #(2,3) uut (
		.PIXCLK(PIXCLK), 
		.LINE_VALID(LINE_VALID), 
		.FRAME_VALID(FRAME_VALID), 
		.DATA_IN(DATA_IN), 
		.DATA_OUT(DATA_OUT), 
		.CURRENT_LINE(CURRENT_LINE), 
		.CURRENT_COLUMN(CURRENT_COLUMN), 
		.PIXEL_VALID(PIXEL_VALID)
	);

	initial begin

		PIXCLK = 0;
		LINE_VALID = 1;
		FRAME_VALID = 1;
		DATA_IN = 0;

		#42;
		#42;
		#42;
		#42;
		#42;
		LINE_VALID = 0;
		FRAME_VALID = 0;
		#20;
		
		FRAME_VALID = 1;
		
		LINE_VALID = 1;
		DATA_IN = 11;
		#10
		LINE_VALID = 1;
		DATA_IN = 12;
		#10
		LINE_VALID = 0;
		#10
		
		LINE_VALID = 1;
		DATA_IN = 21;
		#10
		LINE_VALID = 1;
		DATA_IN = 22;
		#10
		LINE_VALID = 0;
		#10
		
		LINE_VALID = 1;
		DATA_IN = 31;
		#10
		LINE_VALID = 1;
		DATA_IN = 32;
		#10
		LINE_VALID = 0;
		#10
		
		FRAME_VALID = 0;

	end
      
	always #5 PIXCLK <= ~PIXCLK;
	
	initial #360 $finish;
endmodule