data/full_repos/permissive/197982986/cefb.v
1: b"%Error: data/full_repos/permissive/197982986/cefb.v:176: Cannot find file containing module: 'C5_DDR3'\n C5_DDR3 c5_ddr3_inst (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197982986,data/full_repos/permissive/197982986/C5_DDR3\n             data/full_repos/permissive/197982986,data/full_repos/permissive/197982986/C5_DDR3.v\n             data/full_repos/permissive/197982986,data/full_repos/permissive/197982986/C5_DDR3.sv\n             C5_DDR3\n             C5_DDR3.v\n             C5_DDR3.sv\n             obj_dir/C5_DDR3\n             obj_dir/C5_DDR3.v\n             obj_dir/C5_DDR3.sv\n%Error: data/full_repos/permissive/197982986/cefb.v:231: Cannot find file containing module: 'C5_ETH'\n C5_ETH C5_ETH_inst(\n ^~~~~~\n%Error: data/full_repos/permissive/197982986/cefb.v:282: Cannot find file containing module: 'C5_LVDS_RX'\n C5_LVDS_RX C5_LVDS_RX_inst (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/197982986/cefb.v:293: Cannot find file containing module: 'C5_LVDS_TX'\n C5_LVDS_TX C5_LVDS_TX_inst (\n ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module cefb(
	clk,
	hrst_,
	srst_,
	
	clk_to_c,
	c_hrst_,
	c_srst_,
	
	clk_33,
	
	dbg_sw_,
	
	status_led_,
	dig_,
	
	spi_sclk,
	spi_mosi,
	spi_miso,
	spi_ss_,
	
	cpld_sclk,
	cpld_mosi,
	cpld_miso,
	cpld_ss_,
	
	uart_a_rxd,
	uart_a_txd,
	
	uart_b_rxd,
	uart_b_txd,
	
	i2c_a_scl,
	i2c_a_sda,
	
	i2c_b_scl,
	i2c_b_sda,
	
	ib_lvds_rx_in,
	ib_lvds_tx_out,
	
	mezz_rxc,
	mezz_txc,
	
	mezz_rx_rst_,
	mezz_tx_rst_,
	
	mezz_rx_status,
	mezz_tx_status,
	
	mezz_rx_c,
	mezz_tx_c,
	
	eth_tx_clk,
	eth_rx_clk,

	eth_m_rx_d,
	eth_m_rx_en,
	eth_m_rx_err,
	eth_m_tx_d,
	eth_m_tx_en,
	eth_m_tx_err,
	eth_m_rx_crs,
	eth_m_rx_col,
	
	mem_pll_ref_clk_clk,
	
	mem_a,
	mem_ba,
	mem_ck,
	mem_ck_n,
	mem_cke,
	mem_cs_n,
	mem_dm,
	mem_ras_n,
	mem_cas_n,
	mem_we_n,
	mem_reset_n,
	mem_dq,
	mem_dqs,
	mem_dqs_n,
	mem_odt,
	
	oct_rzqin,
	local_init_done,
	local_cal_success,
	local_cal_fail
);
	input wire [3:0] clk;
	input wire hrst_;
	input wire srst_;
	
	output wire clk_to_c;
	input wire c_hrst_;
	input wire c_srst_;
	
	input wire clk_33;
	
	input wire [7:0] dbg_sw_;
	
	output wire [3:0] status_led_;
	output wire [7:0] dig_;
	
	output wire spi_sclk;
	output wire spi_mosi;
	input wire spi_miso;
	output wire spi_ss_;
	
	output wire cpld_sclk;
	output wire cpld_mosi;
	input wire cpld_miso;
	output wire cpld_ss_;
	
	input wire uart_a_rxd;
	output wire uart_a_txd;
	
	input wire uart_b_rxd;
	output wire uart_b_txd;
	
	output wire i2c_a_scl;
	inout wire i2c_a_sda;
	
	output wire i2c_b_scl;
	output wire i2c_b_sda;
	
	input wire [3:0] ib_lvds_rx_in;
	output wire [3:0] ib_lvds_tx_out;
	
	input wire mezz_rxc;
	output wire mezz_txc;
	
	input wire mezz_rx_rst_;
	output wire mezz_tx_rst_;
	
	input wire [3:0] mezz_rx_status;
	output wire [3:0] mezz_tx_status;
	
	input wire [15:0] mezz_rx_c;
	output wire [15:0] mezz_tx_c;
	
	input wire eth_tx_clk;
	input wire eth_rx_clk;

	input wire [3:0] eth_m_rx_d;
	input wire eth_m_rx_en;
	input wire eth_m_rx_err;
	output wire [3:0] eth_m_tx_d;
	output wire eth_m_tx_en;
	output wire eth_m_tx_err;
	input wire eth_m_rx_crs;
	input wire eth_m_rx_col;
	
	input wire mem_pll_ref_clk_clk;
	
	output wire [14:0] mem_a;
	output wire [2:0]  mem_ba;
	output wire [0:0]  mem_ck;
	output wire [0:0]  mem_ck_n;
	output wire [0:0]  mem_cke;
	output wire [0:0]  mem_cs_n;
	output wire [1:0]  mem_dm;
	output wire [0:0]  mem_ras_n;
	output wire [0:0]  mem_cas_n;
	output wire [0:0]  mem_we_n;
	output wire        mem_reset_n;
	inout  wire [15:0] mem_dq;
	inout  wire [1:0]  mem_dqs;
	inout  wire [1:0]  mem_dqs_n;
	output wire [0:0]  mem_odt;

	input wire oct_rzqin;
	output wire local_init_done;
	output wire local_cal_success;
	output wire local_cal_fail;
	
	C5_DDR3 c5_ddr3_inst (
		.pll_ref_clk                (mem_pll_ref_clk_clk),
		.global_reset_n             (hrst_),
		.soft_reset_n               (srst_),
		.afi_clk                    (),
		.afi_half_clk               (),
		.afi_reset_n                (),
		.afi_reset_export_n         (),
		.mem_a                      (mem_a),
		.mem_ba                     (mem_ba),
		.mem_ck                     (mem_ck),
		.mem_ck_n                   (mem_ck_n),
		.mem_cke                    (mem_cke),
		.mem_cs_n                   (mem_cs_n),
		.mem_dm                     (mem_dm),
		.mem_ras_n                  (mem_ras_n),
		.mem_cas_n                  (mem_cas_n),
		.mem_we_n                   (mem_we_n),
		.mem_reset_n                (mem_reset_n),
		.mem_dq                     (mem_dq),
		.mem_dqs                    (mem_dqs),
		.mem_dqs_n                  (mem_dqs_n),
		.mem_odt                    (mem_odt),
		.avl_ready_0                (),
		.avl_burstbegin_0           (),
		.avl_addr_0                 (),
		.avl_rdata_valid_0          (),
		.avl_rdata_0                (),
		.avl_wdata_0                (),
		.avl_be_0                   (),
		.avl_read_req_0             (),
		.avl_write_req_0            (),
		.avl_size_0                 (),
		.mp_cmd_clk_0_clk           (),
		.mp_cmd_reset_n_0_reset_n   (),
		.mp_rfifo_clk_0_clk         (),
		.mp_rfifo_reset_n_0_reset_n (),
		.mp_wfifo_clk_0_clk         (),
		.mp_wfifo_reset_n_0_reset_n (),
		.local_init_done            (local_init_done),
		.local_cal_success          (local_cal_success),
		.local_cal_fail             (local_cal_fail),
		.oct_rzqin                  (oct_rzqin),
		.pll_mem_clk                (),
		.pll_write_clk              (),
		.pll_locked                 (),
		.pll_write_clk_pre_phy_clk  (),
		.pll_addr_cmd_clk           (),
		.pll_avl_clk                (),
		.pll_config_clk             (),
		.pll_mem_phy_clk            (),
		.afi_phy_clk                (),
		.pll_avl_phy_clk            ()
	);

	C5_ETH C5_ETH_inst(
		.clk ( clk[2] ),
		.reset ( hrst_ ),
		.reg_addr (  ),
		.reg_data_out (  ),
		.reg_rd (  ),
		.reg_data_in (  ),
		.reg_wr (  ),
		.reg_busy (  ),
		.tx_clk ( tx_clk ),
		.rx_clk ( rx_clk ),
		.set_10 (  ),
		.set_1000 (  ),
		.eth_mode (  ),
		.ena_10 (  ),
		.m_rx_d ( eth_m_rx_d ),
		.m_rx_en ( eth_m_rx_en ),
		.m_rx_err ( eth_m_rx_err ),
		.m_tx_d ( eth_m_tx_d ),
		.m_tx_en ( eth_m_tx_en ),
		.m_tx_err ( eth_m_tx_err ),
		.m_rx_crs ( eth_m_rx_crs ),
		.m_rx_col ( eth_m_rx_col ),
		.ff_rx_clk (  ),
		.ff_tx_clk (  ),
		.ff_rx_data (  ),
		.ff_rx_eop (  ),
		.rx_err (  ),
		.ff_rx_mod (  ),
		.ff_rx_rdy (  ),
		.ff_rx_sop (  ),
		.ff_rx_dval (  ),
		.ff_tx_data (  ),
		.ff_tx_eop (  ),
		.ff_tx_err (  ),
		.ff_tx_mod (  ),
		.ff_tx_rdy (  ),
		.ff_tx_sop (  ),
		.ff_tx_wren (  ),
		.ff_tx_crc_fwd (  ),
		.ff_tx_septy (  ),
		.tx_ff_uflow (  ),
		.ff_tx_a_full (  ),
		.ff_tx_a_empty (  ),
		.rx_err_stat (  ),
		.rx_frm_type (  ),
		.ff_rx_dsav (  ),
		.ff_rx_a_full (  ),
		.ff_rx_a_empty (  )
	);

	C5_LVDS_RX	C5_LVDS_RX_inst (
		.pll_areset ( hrst_ ),
		.rx_channel_data_align (  ),
		.rx_in ( ib_lvds_rx_in ),
		.rx_inclock ( clk[0] ),
		.rx_cda_max (  ),
		.rx_locked (  ),
		.rx_out (  ),
		.rx_outclock (  )
	);
	
	C5_LVDS_TX	C5_LVDS_TX_inst (
		.pll_areset ( hrst_ ),
		.tx_in (  ),
		.tx_inclock ( clk[0] ),
		.tx_locked (  ),
		.tx_out ( ib_lvds_tx_out ),
		.tx_outclock (  )
	);
endmodule
module cefb(
	clk,
	hrst_,
	srst_,
	
	clk_to_c,
	c_hrst_,
	c_srst_,
	
	clk_33,
	
	dbg_sw_,
	
	status_led_,
	dig_,
	
	spi_sclk,
	spi_mosi,
	spi_miso,
	spi_ss_,
	
	cpld_sclk,
	cpld_mosi,
	cpld_miso,
	cpld_ss_,
	
	uart_a_rxd,
	uart_a_txd,
	
	uart_b_rxd,
	uart_b_txd,
	
	i2c_a_scl,
	i2c_a_sda,
	
	i2c_b_scl,
	i2c_b_sda,
	
	ib_lvds_rx_in,
	ib_lvds_tx_out,
	
	mezz_rxc,
	mezz_txc,
	
	mezz_rx_rst_,
	mezz_tx_rst_,
	
	mezz_rx_status,
	mezz_tx_status,
	
	mezz_rx_c,
	mezz_tx_c,
	
	eth_tx_clk,
	eth_rx_clk,

	eth_m_rx_d,
	eth_m_rx_en,
	eth_m_rx_err,
	eth_m_tx_d,
	eth_m_tx_en,
	eth_m_tx_err,
	eth_m_rx_crs,
	eth_m_rx_col,
	
	mem_pll_ref_clk_clk,
	
	mem_a,
	mem_ba,
	mem_ck,
	mem_ck_n,
	mem_cke,
	mem_cs_n,
	mem_dm,
	mem_ras_n,
	mem_cas_n,
	mem_we_n,
	mem_reset_n,
	mem_dq,
	mem_dqs,
	mem_dqs_n,
	mem_odt,
	
	oct_rzqin,
	local_init_done,
	local_cal_success,
	local_cal_fail
);

	input wire [3:0] clk;
	input wire hrst_;
	input wire srst_;
	
	output wire clk_to_c;
	input wire c_hrst_;
	input wire c_srst_;
	
	input wire clk_33;
	
	input wire [7:0] dbg_sw_;
	
	output wire [3:0] status_led_;
	output wire [7:0] dig_;
	
	output wire spi_sclk;
	output wire spi_mosi;
	input wire spi_miso;
	output wire spi_ss_;
	
	output wire cpld_sclk;
	output wire cpld_mosi;
	input wire cpld_miso;
	output wire cpld_ss_;
	
	input wire uart_a_rxd;
	output wire uart_a_txd;
	
	input wire uart_b_rxd;
	output wire uart_b_txd;
	
	output wire i2c_a_scl;
	inout wire i2c_a_sda;
	
	output wire i2c_b_scl;
	output wire i2c_b_sda;
	
	input wire [3:0] ib_lvds_rx_in;
	output wire [3:0] ib_lvds_tx_out;
	
	input wire mezz_rxc;
	output wire mezz_txc;
	
	input wire mezz_rx_rst_;
	output wire mezz_tx_rst_;
	
	input wire [3:0] mezz_rx_status;
	output wire [3:0] mezz_tx_status;
	
	input wire [15:0] mezz_rx_c;
	output wire [15:0] mezz_tx_c;
	
	input wire eth_tx_clk;
	input wire eth_rx_clk;

	input wire [3:0] eth_m_rx_d;
	input wire eth_m_rx_en;
	input wire eth_m_rx_err;
	output wire [3:0] eth_m_tx_d;
	output wire eth_m_tx_en;
	output wire eth_m_tx_err;
	input wire eth_m_rx_crs;
	input wire eth_m_rx_col;
	
	input wire mem_pll_ref_clk_clk;
	
	output wire [14:0] mem_a;
	output wire [2:0]  mem_ba;
	output wire [0:0]  mem_ck;
	output wire [0:0]  mem_ck_n;
	output wire [0:0]  mem_cke;
	output wire [0:0]  mem_cs_n;
	output wire [1:0]  mem_dm;
	output wire [0:0]  mem_ras_n;
	output wire [0:0]  mem_cas_n;
	output wire [0:0]  mem_we_n;
	output wire        mem_reset_n;
	inout  wire [15:0] mem_dq;
	inout  wire [1:0]  mem_dqs;
	inout  wire [1:0]  mem_dqs_n;
	output wire [0:0]  mem_odt;

	input wire oct_rzqin;
	output wire local_init_done;
	output wire local_cal_success;
	output wire local_cal_fail;
	
	C5_DDR3 c5_ddr3_inst (
		.pll_ref_clk                (mem_pll_ref_clk_clk),
		.global_reset_n             (hrst_),
		.soft_reset_n               (srst_),
		.afi_clk                    (),
		.afi_half_clk               (),
		.afi_reset_n                (),
		.afi_reset_export_n         (),
		.mem_a                      (mem_a),
		.mem_ba                     (mem_ba),
		.mem_ck                     (mem_ck),
		.mem_ck_n                   (mem_ck_n),
		.mem_cke                    (mem_cke),
		.mem_cs_n                   (mem_cs_n),
		.mem_dm                     (mem_dm),
		.mem_ras_n                  (mem_ras_n),
		.mem_cas_n                  (mem_cas_n),
		.mem_we_n                   (mem_we_n),
		.mem_reset_n                (mem_reset_n),
		.mem_dq                     (mem_dq),
		.mem_dqs                    (mem_dqs),
		.mem_dqs_n                  (mem_dqs_n),
		.mem_odt                    (mem_odt),
		.avl_ready_0                (),
		.avl_burstbegin_0           (),
		.avl_addr_0                 (),
		.avl_rdata_valid_0          (),
		.avl_rdata_0                (),
		.avl_wdata_0                (),
		.avl_be_0                   (),
		.avl_read_req_0             (),
		.avl_write_req_0            (),
		.avl_size_0                 (),
		.mp_cmd_clk_0_clk           (),
		.mp_cmd_reset_n_0_reset_n   (),
		.mp_rfifo_clk_0_clk         (),
		.mp_rfifo_reset_n_0_reset_n (),
		.mp_wfifo_clk_0_clk         (),
		.mp_wfifo_reset_n_0_reset_n (),
		.local_init_done            (local_init_done),
		.local_cal_success          (local_cal_success),
		.local_cal_fail             (local_cal_fail),
		.oct_rzqin                  (oct_rzqin),
		.pll_mem_clk                (),
		.pll_write_clk              (),
		.pll_locked                 (),
		.pll_write_clk_pre_phy_clk  (),
		.pll_addr_cmd_clk           (),
		.pll_avl_clk                (),
		.pll_config_clk             (),
		.pll_mem_phy_clk            (),
		.afi_phy_clk                (),
		.pll_avl_phy_clk            ()
	);

	C5_ETH C5_ETH_inst(
		.clk ( clk[2] ),
		.reset ( hrst_ ),
		.reg_addr (  ),
		.reg_data_out (  ),
		.reg_rd (  ),
		.reg_data_in (  ),
		.reg_wr (  ),
		.reg_busy (  ),
		.tx_clk ( tx_clk ),
		.rx_clk ( rx_clk ),
		.set_10 (  ),
		.set_1000 (  ),
		.eth_mode (  ),
		.ena_10 (  ),
		.m_rx_d ( eth_m_rx_d ),
		.m_rx_en ( eth_m_rx_en ),
		.m_rx_err ( eth_m_rx_err ),
		.m_tx_d ( eth_m_tx_d ),
		.m_tx_en ( eth_m_tx_en ),
		.m_tx_err ( eth_m_tx_err ),
		.m_rx_crs ( eth_m_rx_crs ),
		.m_rx_col ( eth_m_rx_col ),
		.ff_rx_clk (  ),
		.ff_tx_clk (  ),
		.ff_rx_data (  ),
		.ff_rx_eop (  ),
		.rx_err (  ),
		.ff_rx_mod (  ),
		.ff_rx_rdy (  ),
		.ff_rx_sop (  ),
		.ff_rx_dval (  ),
		.ff_tx_data (  ),
		.ff_tx_eop (  ),
		.ff_tx_err (  ),
		.ff_tx_mod (  ),
		.ff_tx_rdy (  ),
		.ff_tx_sop (  ),
		.ff_tx_wren (  ),
		.ff_tx_crc_fwd (  ),
		.ff_tx_septy (  ),
		.tx_ff_uflow (  ),
		.ff_tx_a_full (  ),
		.ff_tx_a_empty (  ),
		.rx_err_stat (  ),
		.rx_frm_type (  ),
		.ff_rx_dsav (  ),
		.ff_rx_a_full (  ),
		.ff_rx_a_empty (  )
	);

	C5_LVDS_RX	C5_LVDS_RX_inst (
		.pll_areset ( hrst_ ),
		.rx_channel_data_align (  ),
		.rx_in ( ib_lvds_rx_in ),
		.rx_inclock ( clk[0] ),
		.rx_cda_max (  ),
		.rx_locked (  ),
		.rx_out (  ),
		.rx_outclock (  )
	);
	
	C5_LVDS_TX	C5_LVDS_TX_inst (
		.pll_areset ( hrst_ ),
		.tx_in (  ),
		.tx_inclock ( clk[0] ),
		.tx_locked (  ),
		.tx_out ( ib_lvds_tx_out ),
		.tx_outclock (  )
	);
endmodule