data/full_repos/permissive/174323821/hdl/cpu/jtframe_68kdtack.v
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data/verilator_xmls/091a0c74-8fd8-4be6-a5d3-1cda3cc7e2cb.xml
module jtframe_68kdtack
#(parameter W=5,
            RECOVERY=1,
            WD=6,
            MFREQ=48_000
)(
    input         rst,
    input         clk,
    output   reg  cpu_cen,
    output   reg  cpu_cenb,
    input         bus_cs,
    input         bus_busy,
    input         bus_legit,
    input         ASn,
    input [1:0]   DSn,
    input [W-2:0] num,
    input [W-1:0] den,
    input         wait2,
    input         wait3,

    output reg    DTACKn,
    output reg [15:0] fave,
    output reg [15:0] fworst,
    input             frst
);


localparam CW=W+WD;

reg [CW-1:0] cencnt=0;
reg  [2:0]   wait1;
wire         halt;
wire [W-1:0] num2 = { num, 1'b0 };
wire over = cencnt>den-num2;
reg  [CW:0] cencnt_nx;
reg  risefall=0;

assign halt = RECOVERY==1 && !ASn && wait1==0 && (bus_cs && bus_busy && !bus_legit);

always @(posedge clk) begin : dtack_gen
    if( rst ) begin
        DTACKn <= 1;
        wait1  <= 3'b111;
    end else begin
        if( ASn | &DSn ) begin


            DTACKn <= 1;
            wait1  <= 3'b111;
        end else if( !ASn ) begin
            if( cpu_cen ) begin
                case( {wait3,wait2} )
                    0: wait1 <= 0;
                    1: wait1 <= {2'b0, wait1[1] };
                    2,3: wait1 <= {1'b0, wait1[2:1] };
                endcase
            end
            if( wait1==0 && (!bus_cs || (bus_cs && !bus_busy)) ) begin
                DTACKn <= 0;
            end
        end
    end
end

always @* begin
    cencnt_nx = over && !halt ? {1'b0,cencnt}+num2-den : { 1'b0, cencnt} +num2;
end

always @(posedge clk) begin
    cencnt  <= cencnt_nx[CW] ? {CW{1'b1}} : cencnt_nx[CW-1:0];
    if( over && !halt) begin
        cpu_cen  <= risefall;
        cpu_cenb <= ~risefall;
        risefall <= ~risefall;
    end else begin
        cpu_cen  <= 0;
        cpu_cenb <= 0;
    end



end



reg [15:0] freq_cnt=0, fout_cnt;
initial fworst = 16'hffff;

always @(posedge clk) begin
    freq_cnt <= freq_cnt + 1'd1;
    if(cpu_cen) fout_cnt<=fout_cnt+1'd1;
    if( freq_cnt == MFREQ-1 ) begin
        freq_cnt <= 0;
        fout_cnt <= 0;
        fave <= fout_cnt;
        if( fworst > fout_cnt ) fworst <= fout_cnt;
    end
    if( frst ) fworst <= 16'hffff;
end

endmodule
module jtframe_68kdtack
#(parameter W=5,
            RECOVERY=1,
            WD=6,
            MFREQ=48_000
)(
    input         rst,
    input         clk,
    output   reg  cpu_cen,
    output   reg  cpu_cenb,
    input         bus_cs,
    input         bus_busy,
    input         bus_legit,
    input         ASn,
    input [1:0]   DSn,
    input [W-2:0] num,
    input [W-1:0] den,
    input         wait2,
    input         wait3,

    output reg    DTACKn,
    output reg [15:0] fave,
    output reg [15:0] fworst,
    input             frst
);



localparam CW=W+WD;

reg [CW-1:0] cencnt=0;
reg  [2:0]   wait1;
wire         halt;
wire [W-1:0] num2 = { num, 1'b0 };
wire over = cencnt>den-num2;
reg  [CW:0] cencnt_nx;
reg  risefall=0;

assign halt = RECOVERY==1 && !ASn && wait1==0 && (bus_cs && bus_busy && !bus_legit);

always @(posedge clk) begin : dtack_gen
    if( rst ) begin
        DTACKn <= 1;
        wait1  <= 3'b111;
    end else begin
        if( ASn | &DSn ) begin


            DTACKn <= 1;
            wait1  <= 3'b111;
        end else if( !ASn ) begin
            if( cpu_cen ) begin
                case( {wait3,wait2} )
                    0: wait1 <= 0;
                    1: wait1 <= {2'b0, wait1[1] };
                    2,3: wait1 <= {1'b0, wait1[2:1] };
                endcase
            end
            if( wait1==0 && (!bus_cs || (bus_cs && !bus_busy)) ) begin
                DTACKn <= 0;
            end
        end
    end
end

always @* begin
    cencnt_nx = over && !halt ? {1'b0,cencnt}+num2-den : { 1'b0, cencnt} +num2;
end

always @(posedge clk) begin
    cencnt  <= cencnt_nx[CW] ? {CW{1'b1}} : cencnt_nx[CW-1:0];
    if( over && !halt) begin
        cpu_cen  <= risefall;
        cpu_cenb <= ~risefall;
        risefall <= ~risefall;
    end else begin
        cpu_cen  <= 0;
        cpu_cenb <= 0;
    end



end



reg [15:0] freq_cnt=0, fout_cnt;
initial fworst = 16'hffff;

always @(posedge clk) begin
    freq_cnt <= freq_cnt + 1'd1;
    if(cpu_cen) fout_cnt<=fout_cnt+1'd1;
    if( freq_cnt == MFREQ-1 ) begin
        freq_cnt <= 0;
        fout_cnt <= 0;
        fave <= fout_cnt;
        if( fworst > fout_cnt ) fworst <= fout_cnt;
    end
    if( frst ) fworst <= 16'hffff;
end

endmodule