data/full_repos/permissive/211235278/02. Multi-cycle CPU/control.v
1: b'%Error: Cannot find file containing module: Multi-cycle\n        ... Looked in:\n             data/full_repos/permissive/211235278/02./Multi-cycle\n             data/full_repos/permissive/211235278/02./Multi-cycle.v\n             data/full_repos/permissive/211235278/02./Multi-cycle.sv\n             Multi-cycle\n             Multi-cycle.v\n             Multi-cycle.sv\n             obj_dir/Multi-cycle\n             obj_dir/Multi-cycle.v\n             obj_dir/Multi-cycle.sv\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/211235278\n%Error: Cannot find file containing module: data/full_repos/permissive/211235278/02.\n%Error: Cannot find file containing module: CPU/control.v\n%Error: Exiting due to 4 error(s)\n'
module Control(
    input clk,
    input reset_n,
    input [3:0] opcode,
    input [5:0] func,
    output PCWriteCond,
    output PCWrite,
    output IorD,
    output ReadM,
    output WriteM,
    output [1:0] RegSrc,
    output IRWrite,
    output RegWrite,
    output [1:0] RegDst,
    output [1:0] PCSrc,
    output ALUSrcA,
    output [1:0] ALUSrcB,
    output Halt,
    output OpenPort,
    output reg [3:0] ALUOp,
    output increment_num_inst
    );

    
    reg [4:0] state, next_state;
    reg [3:0] one, two;
    wire [`NUM_CTRL-1:0] CTRL;
    

    assign {PCWriteCond, PCWrite, IorD, ReadM, WriteM, RegSrc, IRWrite, RegWrite, RegDst, PCSrc, ALUSrcA, ALUSrcB} = CTRL;
    

    assign Halt = (opcode==`OPCODE_R & func==`FUNC_HLT & state==2);
    assign OpenPort = (opcode==`OPCODE_R & func==`FUNC_WWD & state==2);
    
    assign increment_num_inst = (next_state == 0);
    

    always @(posedge clk) begin
        if (!reset_n) state <= 0;
        else state <= next_state;
    end
    

    always @(*) begin
        case (state)
             0: begin
                if (opcode==`OPCODE_ADI | opcode==`OPCODE_ORI | opcode==`OPCODE_LHI | opcode==`OPCODE_LWD) next_state = 1;
                else if ((opcode==`OPCODE_R & func!=`FUNC_JPR & func!=`FUNC_JRL) | opcode==`OPCODE_SWD) next_state = 2;
                else if (opcode==`OPCODE_BEQ | opcode==`OPCODE_BNE | opcode==`OPCODE_BGZ | opcode==`OPCODE_BLZ) next_state = 3;
                else if (opcode==`OPCODE_JMP) next_state = 4;
                else if (opcode==`OPCODE_JAL) next_state = 5;
                else if (opcode==`OPCODE_R & func==`FUNC_JPR) next_state = 6;
                else if (opcode==`OPCODE_R & func==`FUNC_JRL) next_state = 7;
            end
             1: begin
                if (opcode==`OPCODE_ADI | opcode==`OPCODE_ORI | opcode==`OPCODE_LHI) next_state = 8;
                else if (opcode==`OPCODE_LWD) next_state = 10;
            end
             2: begin
                if (opcode==`OPCODE_R & (func==`FUNC_WWD | func==`FUNC_HLT)) next_state = 0;
                else if (opcode==`OPCODE_R & func!=`FUNC_JPR & func!=`FUNC_JRL) next_state = 9;
                else if (opcode==`OPCODE_SWD) next_state = 10;
            end
             3: next_state = 11;
             4: next_state = 0;
             5: next_state = 0;
             6: next_state = 0;
             7: next_state = 0;
             8: next_state = 12;
             9: next_state = 13;
            10: begin
                if (opcode==`OPCODE_LWD) next_state = 14;
                else if (opcode==`OPCODE_SWD) next_state = 15;
            end
            11: next_state = 0;
            12: next_state = 0;
            13: next_state = 0;
            14: next_state = 16;
            15: next_state = 0;
            16: next_state = 0;
        endcase
    end
    

    always @(*) begin
        case (state)
             0: one = 0;
             1: one = `NUM_RT;
             2: one = `NUM_RT;
             3: one = 2;
             4: one = 3;
             5: one = 3;
             6: one = 5;
             7: one = 4;
             8: one = 6;
             9: one = 7;
             10: one = 6;
             11: one = 7;
             12: one = 9;
             13: one = 10;
             14: one = 11;
             15: one = 12;
             16: one = 13;
             default:  one = 0;
        endcase
    end
    

    always @(*) begin
        if (state==0) two = 1;
        else if (state==5) two = 4;
        else if (state==7) two = 5;
        else if (state==11) two = 8;
        else two = `NUM_RT;
    end
    

    always @(*) begin
        if (state==0 | state==3 | state==10) begin
            ALUOp = 0;
        end else if (state==8) begin
            if (opcode==`OPCODE_ADI) ALUOp = 0;
            else if (opcode==`OPCODE_ORI) ALUOp = 3;
            else if (opcode==`OPCODE_LHI) ALUOp = 8;
            else ALUOp = 15;
        end else if (state==9) begin
            if (opcode==`OPCODE_R & func<8) ALUOp = func[3:0];
            else ALUOp = 15;
        end else if (state==11) begin
            if (opcode==`OPCODE_BNE) ALUOp = 9;
            else if (opcode==`OPCODE_BEQ) ALUOp = 10;
            else if (opcode==`OPCODE_BGZ) ALUOp = 11;
            else if (opcode==`OPCODE_BLZ) ALUOp = 12;
            else ALUOp = 15;
        end else begin
            ALUOp = 15;
        end
    end
    

    ROM rom (.one(one),
         .two(two),
         .CTRL(CTRL));
    
endmodule
module Control(
    input clk,
    input reset_n,
    input [3:0] opcode,
    input [5:0] func,
    output PCWriteCond,
    output PCWrite,
    output IorD,
    output ReadM,
    output WriteM,
    output [1:0] RegSrc,
    output IRWrite,
    output RegWrite,
    output [1:0] RegDst,
    output [1:0] PCSrc,
    output ALUSrcA,
    output [1:0] ALUSrcB,
    output Halt,
    output OpenPort,
    output reg [3:0] ALUOp,
    output increment_num_inst
    );


    
    reg [4:0] state, next_state;
    reg [3:0] one, two;
    wire [`NUM_CTRL-1:0] CTRL;
    

    assign {PCWriteCond, PCWrite, IorD, ReadM, WriteM, RegSrc, IRWrite, RegWrite, RegDst, PCSrc, ALUSrcA, ALUSrcB} = CTRL;
    

    assign Halt = (opcode==`OPCODE_R & func==`FUNC_HLT & state==2);
    assign OpenPort = (opcode==`OPCODE_R & func==`FUNC_WWD & state==2);
    
    assign increment_num_inst = (next_state == 0);
    

    always @(posedge clk) begin
        if (!reset_n) state <= 0;
        else state <= next_state;
    end
    

    always @(*) begin
        case (state)
             0: begin
                if (opcode==`OPCODE_ADI | opcode==`OPCODE_ORI | opcode==`OPCODE_LHI | opcode==`OPCODE_LWD) next_state = 1;
                else if ((opcode==`OPCODE_R & func!=`FUNC_JPR & func!=`FUNC_JRL) | opcode==`OPCODE_SWD) next_state = 2;
                else if (opcode==`OPCODE_BEQ | opcode==`OPCODE_BNE | opcode==`OPCODE_BGZ | opcode==`OPCODE_BLZ) next_state = 3;
                else if (opcode==`OPCODE_JMP) next_state = 4;
                else if (opcode==`OPCODE_JAL) next_state = 5;
                else if (opcode==`OPCODE_R & func==`FUNC_JPR) next_state = 6;
                else if (opcode==`OPCODE_R & func==`FUNC_JRL) next_state = 7;
            end
             1: begin
                if (opcode==`OPCODE_ADI | opcode==`OPCODE_ORI | opcode==`OPCODE_LHI) next_state = 8;
                else if (opcode==`OPCODE_LWD) next_state = 10;
            end
             2: begin
                if (opcode==`OPCODE_R & (func==`FUNC_WWD | func==`FUNC_HLT)) next_state = 0;
                else if (opcode==`OPCODE_R & func!=`FUNC_JPR & func!=`FUNC_JRL) next_state = 9;
                else if (opcode==`OPCODE_SWD) next_state = 10;
            end
             3: next_state = 11;
             4: next_state = 0;
             5: next_state = 0;
             6: next_state = 0;
             7: next_state = 0;
             8: next_state = 12;
             9: next_state = 13;
            10: begin
                if (opcode==`OPCODE_LWD) next_state = 14;
                else if (opcode==`OPCODE_SWD) next_state = 15;
            end
            11: next_state = 0;
            12: next_state = 0;
            13: next_state = 0;
            14: next_state = 16;
            15: next_state = 0;
            16: next_state = 0;
        endcase
    end
    

    always @(*) begin
        case (state)
             0: one = 0;
             1: one = `NUM_RT;
             2: one = `NUM_RT;
             3: one = 2;
             4: one = 3;
             5: one = 3;
             6: one = 5;
             7: one = 4;
             8: one = 6;
             9: one = 7;
             10: one = 6;
             11: one = 7;
             12: one = 9;
             13: one = 10;
             14: one = 11;
             15: one = 12;
             16: one = 13;
             default:  one = 0;
        endcase
    end
    

    always @(*) begin
        if (state==0) two = 1;
        else if (state==5) two = 4;
        else if (state==7) two = 5;
        else if (state==11) two = 8;
        else two = `NUM_RT;
    end
    

    always @(*) begin
        if (state==0 | state==3 | state==10) begin
            ALUOp = 0;
        end else if (state==8) begin
            if (opcode==`OPCODE_ADI) ALUOp = 0;
            else if (opcode==`OPCODE_ORI) ALUOp = 3;
            else if (opcode==`OPCODE_LHI) ALUOp = 8;
            else ALUOp = 15;
        end else if (state==9) begin
            if (opcode==`OPCODE_R & func<8) ALUOp = func[3:0];
            else ALUOp = 15;
        end else if (state==11) begin
            if (opcode==`OPCODE_BNE) ALUOp = 9;
            else if (opcode==`OPCODE_BEQ) ALUOp = 10;
            else if (opcode==`OPCODE_BGZ) ALUOp = 11;
            else if (opcode==`OPCODE_BLZ) ALUOp = 12;
            else ALUOp = 15;
        end else begin
            ALUOp = 15;
        end
    end
    

    ROM rom (.one(one),
         .two(two),
         .CTRL(CTRL));
    
endmodule