data/full_repos/permissive/189013641/src/Errval.v
1: b'%Warning-WIDTH: data/full_repos/permissive/189013641/src/Errval.v:61: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'C_Q\' generates 8 bits.\n                                                                    : ... In instance Errval\n  assign #1 px01=(sign==0)?(Px+C_Q):(Px-C_Q);   \n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/Errval.v:61: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'C_Q\' generates 8 bits.\n                                                                    : ... In instance Errval\n  assign #1 px01=(sign==0)?(Px+C_Q):(Px-C_Q);   \n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/Errval.v:70: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'C_Q\' generates 8 bits.\n                                                                    : ... In instance Errval\n  assign #1 px11=(sign==0)?(Px+C_Q+1):(Px-C_Q-1);\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/Errval.v:70: Operator SUB expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'C_Q\' generates 8 bits.\n                                                                    : ... In instance Errval\n  assign #1 px11=(sign==0)?(Px+C_Q+1):(Px-C_Q-1);\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/Errval.v:78: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'C_Q\' generates 8 bits.\n                                                                    : ... In instance Errval\n  assign #1 px21=(sign==0)?(Px+C_Q-1):(Px-C_Q+1);\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/Errval.v:78: Operator SUB expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'C_Q\' generates 8 bits.\n                                                                    : ... In instance Errval\n  assign #1 px21=(sign==0)?(Px+C_Q-1):(Px-C_Q+1);\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/Errval.v:98: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'errval0_temp2\' generates 10 bits.\n                                                                    : ... In instance Errval\n   Errval0<=errval0_temp2;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/Errval.v:99: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'errval1_temp2\' generates 10 bits.\n                                                                    : ... In instance Errval\n   Errval1<=errval1_temp2;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/Errval.v:100: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'errval2_temp2\' generates 10 bits.\n                                                                     : ... In instance Errval\n   Errval2<=errval2_temp2;\n          ^~\n%Error: Exiting due to 9 warning(s)\n'
module Errval(clk, reset, en, Q, sign, C_Q, Ix, Px,
              C_sign,Q_out, Errval0, Errval1, Errval2, en_out);
    input clk;
    input reset;
    input en;
    input [8:0] Q;
    input sign;
	 input signed [7:0] C_Q;
    input  signed [8:0] Ix;
    input  signed [8:0] Px;

    output   C_sign;
	 output [8:0] Q_out;
    output [8:0] Errval0;
    output [8:0] Errval1;
    output [8:0] Errval2;
    output en_out;
   
	 reg  C_sign;
	 reg [8:0] Q_out;
    reg signed [8:0] Errval0;
    reg signed [8:0] Errval1;
    reg signed [8:0] Errval2;
    reg en_out;
	 
	 reg [8:0] Q_temp;
	 
 
	 wire signed [7:0] C_Q;
	 
	 wire signed [9:0] px01,px02,px03;
	 wire signed [9:0] px11,px12,px13;
	 wire signed [9:0] px21,px22,px23;
	 
	 wire signed [9:0] errval_0,errval0_temp1,errval0_temp2;
	 wire signed [9:0] errval_1,errval1_temp1,errval1_temp2;
	 wire signed [9:0] errval_2,errval2_temp1,errval2_temp2;
	 

	 
	 assign #1 px01=(sign==0)?(Px+C_Q):(Px-C_Q);
	 assign #1  px02=(px01<256)?px01:10'b00_1111_1111;
	 assign #1 px03=(px02<0)?10'b00_0000_0000:px02;
	 assign #1 errval_0=(sign==0)?(Ix-px03):(px03-Ix);
	 assign #1 errval0_temp1=(errval_0<0)?(errval_0+256):errval_0;

	 assign errval0_temp2=(errval0_temp1>127)?(errval0_temp1-256):errval0_temp1;
	 
	 
	 assign #1 px11=(sign==0)?(Px+C_Q+1):(Px-C_Q-1);
	 assign #1 px12=(px11<256)?px11:10'b00_1111_1111;
	 assign #1 px13=(px12<0)?10'b00_0000_0000:px12;
	 assign #1 errval_1=(sign==0)?(Ix-px13):(px13-Ix);
	 assign #1 errval1_temp1=(errval_1<0)?(errval_1+256):errval_1;
	 assign #1 errval1_temp2=(errval1_temp1>127)?(errval1_temp1-256):errval1_temp1;
	 
	 
	 assign #1 px21=(sign==0)?(Px+C_Q-1):(Px-C_Q+1);
	 assign #1 px22=(px21<256)?px21:10'b00_1111_1111;
	 assign #1 px23=(px22<0)?10'b00_0000_0000:px22;
	 assign #1 errval_2=(sign==0)?(Ix-px23):(px23-Ix);
	 assign #1 errval2_temp1=(errval_2<0)?(errval_2+256):errval_2;
	 assign #1 errval2_temp2=(errval2_temp1>127)?(errval2_temp1-256):errval2_temp1;
	 
	 
	 always@(posedge clk or negedge reset)
	 if(!reset)
	 begin
	 Errval0<=0;
	 Errval1<=0;
	 Errval2<=0;
	 en_out<=0;
	 end
	 else
	 if(en)
	  begin
	  en_out<=1;
	  Errval0<=errval0_temp2;
	  Errval1<=errval1_temp2;
	  Errval2<=errval2_temp2;
	  end
	 else
	  begin
	  en_out<=0;
	  Errval0<=0;
	  Errval1<=0;
	  Errval2<=0;
	  end
	 
	 always@(posedge clk or negedge reset)
	 if(!reset)
	 begin
	 Q_temp<=0;
	 Q_out<=0;
	 end
	 else if(en)
	 begin
	 Q_temp<=Q;
	 Q_out<=Q;
	 end
	 else
	 begin
	 Q_temp<=0;
	 Q_out<=0;
	 end
	 
	 always@(posedge clk or negedge reset)
	 if(!reset)
	 C_sign<=0;
	 else if(en)
	 C_sign<=(Q_temp==Q)?1:0;
	 else
	 C_sign<=0;
	 
	 


endmodule
module Errval(clk, reset, en, Q, sign, C_Q, Ix, Px,
              C_sign,Q_out, Errval0, Errval1, Errval2, en_out);

    input clk;
    input reset;
    input en;
    input [8:0] Q;
    input sign;
	 input signed [7:0] C_Q;
    input  signed [8:0] Ix;
    input  signed [8:0] Px;

    output   C_sign;
	 output [8:0] Q_out;
    output [8:0] Errval0;
    output [8:0] Errval1;
    output [8:0] Errval2;
    output en_out;
   
	 reg  C_sign;
	 reg [8:0] Q_out;
    reg signed [8:0] Errval0;
    reg signed [8:0] Errval1;
    reg signed [8:0] Errval2;
    reg en_out;
	 
	 reg [8:0] Q_temp;
	 
 
	 wire signed [7:0] C_Q;
	 
	 wire signed [9:0] px01,px02,px03;
	 wire signed [9:0] px11,px12,px13;
	 wire signed [9:0] px21,px22,px23;
	 
	 wire signed [9:0] errval_0,errval0_temp1,errval0_temp2;
	 wire signed [9:0] errval_1,errval1_temp1,errval1_temp2;
	 wire signed [9:0] errval_2,errval2_temp1,errval2_temp2;
	 

	 
	 assign #1 px01=(sign==0)?(Px+C_Q):(Px-C_Q);
	 assign #1  px02=(px01<256)?px01:10'b00_1111_1111;
	 assign #1 px03=(px02<0)?10'b00_0000_0000:px02;
	 assign #1 errval_0=(sign==0)?(Ix-px03):(px03-Ix);
	 assign #1 errval0_temp1=(errval_0<0)?(errval_0+256):errval_0;

	 assign errval0_temp2=(errval0_temp1>127)?(errval0_temp1-256):errval0_temp1;
	 
	 
	 assign #1 px11=(sign==0)?(Px+C_Q+1):(Px-C_Q-1);
	 assign #1 px12=(px11<256)?px11:10'b00_1111_1111;
	 assign #1 px13=(px12<0)?10'b00_0000_0000:px12;
	 assign #1 errval_1=(sign==0)?(Ix-px13):(px13-Ix);
	 assign #1 errval1_temp1=(errval_1<0)?(errval_1+256):errval_1;
	 assign #1 errval1_temp2=(errval1_temp1>127)?(errval1_temp1-256):errval1_temp1;
	 
	 
	 assign #1 px21=(sign==0)?(Px+C_Q-1):(Px-C_Q+1);
	 assign #1 px22=(px21<256)?px21:10'b00_1111_1111;
	 assign #1 px23=(px22<0)?10'b00_0000_0000:px22;
	 assign #1 errval_2=(sign==0)?(Ix-px23):(px23-Ix);
	 assign #1 errval2_temp1=(errval_2<0)?(errval_2+256):errval_2;
	 assign #1 errval2_temp2=(errval2_temp1>127)?(errval2_temp1-256):errval2_temp1;
	 
	 
	 always@(posedge clk or negedge reset)
	 if(!reset)
	 begin
	 Errval0<=0;
	 Errval1<=0;
	 Errval2<=0;
	 en_out<=0;
	 end
	 else
	 if(en)
	  begin
	  en_out<=1;
	  Errval0<=errval0_temp2;
	  Errval1<=errval1_temp2;
	  Errval2<=errval2_temp2;
	  end
	 else
	  begin
	  en_out<=0;
	  Errval0<=0;
	  Errval1<=0;
	  Errval2<=0;
	  end
	 
	 always@(posedge clk or negedge reset)
	 if(!reset)
	 begin
	 Q_temp<=0;
	 Q_out<=0;
	 end
	 else if(en)
	 begin
	 Q_temp<=Q;
	 Q_out<=Q;
	 end
	 else
	 begin
	 Q_temp<=0;
	 Q_out<=0;
	 end
	 
	 always@(posedge clk or negedge reset)
	 if(!reset)
	 C_sign<=0;
	 else if(en)
	 C_sign<=(Q_temp==Q)?1:0;
	 else
	 C_sign<=0;
	 
	 


endmodule