data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules/module_fadd.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules/module_fadd.v:14: Multiple top level modules\n                                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                         : ... Top module \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                                                                                                         : ... Top module \'add1\'\nmodule add1 ( input a, input b, input cin,   output sum, output cout );\n       ^~~~\n%Error: data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules/module_fadd.v:8: Cannot find file containing module: \'add16\'\n    add16 ins1(a[15:0],b[15:0],0,sum1,cout);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules,data/full_repos/permissive/199632300/add16\n             data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules,data/full_repos/permissive/199632300/add16.v\n             data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules,data/full_repos/permissive/199632300/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/199632300/HDLBits/Verilog_Language/Modules/module_fadd.v:9: Cannot find file containing module: \'add16\'\n    add16 ins2(a[31:16],b[31:16],cout,sum2,cout1);\n    ^~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire cout,cout1;
    wire [15:0] sum1, sum2;
    add16 ins1(a[15:0],b[15:0],0,sum1,cout);
    add16 ins2(a[31:16],b[31:16],cout,sum2,cout1);
    assign sum = {sum2[15:0],sum1[15:0]};

endmodule
module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

    wire cout,cout1;
    wire [15:0] sum1, sum2;
    add16 ins1(a[15:0],b[15:0],0,sum1,cout);
    add16 ins2(a[31:16],b[31:16],cout,sum2,cout1);
    assign sum = {sum2[15:0],sum1[15:0]};

endmodule