data/full_repos/permissive/206169433/pipeline/clockdivider.v
data/verilator_xmls/496430f8-c9c3-4a44-92fc-80693f17ae77.xml
module clockdivider(clock_out2,clock_in);
  input clock_in;
  output clock_out2;
  
  reg [17:0]R;
  reg clock_out1;
  reg clock_out2;
  always @ (posedge clock_in)begin
    if(R==200000)begin
          clock_out2<=1;
          R<=0;
    end
    else begin
          clock_out2<=0;
          R<=R+1;
    end
    
  end
endmodule
module clockdivider(clock_out2,clock_in);

  input clock_in;
  output clock_out2;
  
  reg [17:0]R;
  reg clock_out1;
  reg clock_out2;
  always @ (posedge clock_in)begin
    if(R==200000)begin
          clock_out2<=1;
          R<=0;
    end
    else begin
          clock_out2<=0;
          R<=R+1;
    end
    
  end
endmodule