data/full_repos/permissive/166558975/rtl/AUDIO_CLK.v
1: b'%Warning-WIDTH: data/full_repos/permissive/166558975/rtl/AUDIO_CLK.v:37: Operator GTE expects 32 or 25 bits on the LHS, but LHS\'s VARREF \'BCLK_DIV\' generates 4 bits.\n                                                                       : ... In instance AUDIO_CLOCK\n  if(BCLK_DIV >= REF_CLK/(SAMPLE_RATE*(DATA_WIDTH+2)*CHANNEL_NUM*2)-1 )\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module AUDIO_CLOCK (

					BCLK,
					BCLK_CONT,
					LRCK,

				    iCLK_18_4,
					iRST_N
					);				

parameter	REF_CLK			=	18432000;
parameter	SAMPLE_RATE		=	48000;
parameter	DATA_WIDTH		=	16;
parameter	CHANNEL_NUM		=	2;


output	reg				LRCK;
output	reg				BCLK;
output	reg		[4:0]	BCLK_CONT;

input					iCLK_18_4;
input					iRST_N;


reg	[3:0]	BCLK_DIV;


always@(posedge iCLK_18_4 or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		BCLK_DIV		<=	0;
		BCLK			<=	0;
	end
	else
	begin
		if(BCLK_DIV >= REF_CLK/(SAMPLE_RATE*(DATA_WIDTH+2)*CHANNEL_NUM*2)-1 )
		begin
			BCLK_DIV		<=	0;
			BCLK			<=	~BCLK;
		end
		else
			BCLK_DIV		<=	BCLK_DIV+1;
	end
end



always@(posedge BCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		BCLK_CONT	<=	0;
		LRCK		<=	0;
	end
	else
	begin
		if(BCLK_CONT==(DATA_WIDTH+1))
		begin
			BCLK_CONT	<=	0;
			LRCK		<=	~LRCK;
		end
		else
		begin
			BCLK_CONT	<=	BCLK_CONT+1;
		end
	end
end

endmodule
module AUDIO_CLOCK (

					BCLK,
					BCLK_CONT,
					LRCK,

				    iCLK_18_4,
					iRST_N
					);
				

parameter	REF_CLK			=	18432000;
parameter	SAMPLE_RATE		=	48000;
parameter	DATA_WIDTH		=	16;
parameter	CHANNEL_NUM		=	2;


output	reg				LRCK;
output	reg				BCLK;
output	reg		[4:0]	BCLK_CONT;

input					iCLK_18_4;
input					iRST_N;


reg	[3:0]	BCLK_DIV;


always@(posedge iCLK_18_4 or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		BCLK_DIV		<=	0;
		BCLK			<=	0;
	end
	else
	begin
		if(BCLK_DIV >= REF_CLK/(SAMPLE_RATE*(DATA_WIDTH+2)*CHANNEL_NUM*2)-1 )
		begin
			BCLK_DIV		<=	0;
			BCLK			<=	~BCLK;
		end
		else
			BCLK_DIV		<=	BCLK_DIV+1;
	end
end



always@(posedge BCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		BCLK_CONT	<=	0;
		LRCK		<=	0;
	end
	else
	begin
		if(BCLK_CONT==(DATA_WIDTH+1))
		begin
			BCLK_CONT	<=	0;
			LRCK		<=	~LRCK;
		end
		else
		begin
			BCLK_CONT	<=	BCLK_CONT+1;
		end
	end
end

endmodule