data/full_repos/permissive/134925232/src/fdiv.v
1: b'%Warning-WIDTH: data/full_repos/permissive/134925232/src/fdiv.v:14: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                  : ... In instance fdiv\n  initial out_clock = 32\'b0;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/134925232/src/fdiv.v:24: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                  : ... In instance fdiv\n        out_clock <= 32\'b0;\n                  ^~\n%Error: Exiting due to 2 warning(s)\n'
module fdiv(
  input clock, reset,
  output reg out_clock
  );
  
  reg [31:0] count;
  wire [31:0] hertz;
  
  parameter clock_hz = 32'd50000000;
  parameter hz = 32'd1;
  
  initial out_clock = 32'b0;
  initial count = 32'b0;
  
  assign hertz = clock_hz / (hz * 2);
  
  always @(posedge clock, posedge reset)
  begin
    if (reset == 1'b1) 
        begin
        count <= 32'b0;
        out_clock <= 32'b0;
      end
    else if (count == hertz) 
    begin
        count <= 32'b0;
        out_clock = ~out_clock;
    end
    else begin
        count <= count + 1;
        out_clock <= out_clock;
      end
  end  
  
endmodule
module fdiv(
  input clock, reset,
  output reg out_clock
  );

  
  reg [31:0] count;
  wire [31:0] hertz;
  
  parameter clock_hz = 32'd50000000;
  parameter hz = 32'd1;
  
  initial out_clock = 32'b0;
  initial count = 32'b0;
  
  assign hertz = clock_hz / (hz * 2);
  
  always @(posedge clock, posedge reset)
  begin
    if (reset == 1'b1) 
        begin
        count <= 32'b0;
        out_clock <= 32'b0;
      end
    else if (count == hertz) 
    begin
        count <= 32'b0;
        out_clock = ~out_clock;
    end
    else begin
        count <= count + 1;
        out_clock <= out_clock;
      end
  end  
  
endmodule