data/full_repos/permissive/177136805/eq1.v
data/verilator_xmls/bb2fea0c-3fdd-4033-a548-73bc9edad42f.xml
module eq1

(
input wire i0, i1,
output wire eq
);

wire p0, p1;


assign eq = p0 | p1;

assign p0 = ~i0 & ~i1;
assign p1 = i0 & i1;
endmodule
module eq1

(
input wire i0, i1,
output wire eq
);


wire p0, p1;


assign eq = p0 | p1;

assign p0 = ~i0 & ~i1;
assign p1 = i0 & i1;
endmodule