data/full_repos/permissive/123339956/Labtest_1/seqgen.v
 line:20: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:10: Unsupported: Ignoring delay on this delayed statement.\n always #10 clock = ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #20 reset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #40 reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #100 reset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #40 reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #800 \n  ^\n%Error: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:25: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("seqgen.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/123339956/Labtest_1/seqgen.v:26: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module seqgen(out, reset, clk);
	input clk, reset;
	output reg [3:0] out;
	
	always @ (posedge clk)
		begin
				if(reset) out <= 4'b0000;
				else
					case(out)
						4'b0000: out <= 4'b0001;
						4'b0001: out <= 4'b0011;
						4'b0011: out <= 4'b0010;
						4'b0010: out <= 4'b0110;
						4'b0110: out <= 4'b0111;
						4'b0111: out <= 4'b0101;
						4'b0101: out <= 4'b0100;
						4'b0100: out <= 4'b1100;
						4'b1100: out <= 4'b1101;
						4'b1101: out <= 4'b1111;
						4'b1111: out <= 4'b1110;
						4'b1110: out <= 4'b1010;
						4'b1010: out <= 4'b1011;
						4'b1011: out <= 4'b1001;
						4'b1001: out <= 4'b1000;
						4'b1000: out <= 4'b0000;
						default: out <= 4'b0000;
					endcase
		end

endmodule
module seqgen(out, reset, clk);

	input clk, reset;
	output reg [3:0] out;
	
	always @ (posedge clk)
		begin
				if(reset) out <= 4'b0000;
				else
					case(out)
						4'b0000: out <= 4'b0001;
						4'b0001: out <= 4'b0011;
						4'b0011: out <= 4'b0010;
						4'b0010: out <= 4'b0110;
						4'b0110: out <= 4'b0111;
						4'b0111: out <= 4'b0101;
						4'b0101: out <= 4'b0100;
						4'b0100: out <= 4'b1100;
						4'b1100: out <= 4'b1101;
						4'b1101: out <= 4'b1111;
						4'b1111: out <= 4'b1110;
						4'b1110: out <= 4'b1010;
						4'b1010: out <= 4'b1011;
						4'b1011: out <= 4'b1001;
						4'b1001: out <= 4'b1000;
						4'b1000: out <= 4'b0000;
						default: out <= 4'b0000;
					endcase
		end

endmodule