data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi/axi_extract_tlast_tkeep.v
data/verilator_xmls/ad7a0251-9236-40fd-a256-797e686aa427.xml
module axi_extract_tlast_tkeep #(
   parameter DATA_W = 64,
   parameter KEEP_W = DATA_W  /8
) (
   input clk,
   input rst,


   input      [DATA_W-1:0] i_tdata,
   input                   i_tvalid,
   output reg              i_tready,


   output reg [DATA_W-1:0] o_tdata,
   output reg [KEEP_W-1:0] o_tkeep,
   output reg              o_tlast,
   output reg              o_tvalid,
   input                   o_tready
);

  localparam                  ESC_WORD_W = 32;
  localparam [ESC_WORD_W-1:0] ESC_WORD   = 'hDEADBEEF;






  reg              save_flags;
  reg              tlast_saved;
  reg [KEEP_W-1:0] tkeep_saved;

  always @(posedge clk) begin
    if (save_flags) begin

      tlast_saved <= i_tdata[0];
      tkeep_saved <= i_tdata[1 +: KEEP_W];
    end
  end






  localparam ST_IDLE = 0;
  localparam ST_DATA = 1;

  reg [0:0] state = ST_IDLE;
  reg [0:0] next_state;

  always @(posedge clk) begin
    if (rst) begin
      state <= ST_IDLE;
    end else begin
      state <= next_state;
    end
  end

  always @(*) begin

    o_tdata    = i_tdata;
    o_tlast    = 1'b0;
    o_tkeep    = {KEEP_W{1'b1}};
    save_flags = 1'b0;
    next_state = state;
    o_tvalid   = i_tvalid;
    i_tready   = o_tready;

    case(state)




      ST_IDLE: begin
        if ((i_tdata[DATA_W-1 -: ESC_WORD_W] == ESC_WORD) && i_tvalid) begin
          save_flags = 1'b1;
          next_state = ST_DATA;
          o_tvalid   = 1'b0;
          i_tready   = 1'b1;
        end
      end




      ST_DATA: begin
        o_tlast = tlast_saved;
        o_tkeep = tkeep_saved;
        if (i_tvalid & o_tready) begin
          next_state = ST_IDLE;
        end
      end
    endcase
  end

endmodule
module axi_extract_tlast_tkeep #(
   parameter DATA_W = 64,
   parameter KEEP_W = DATA_W  /8
) (
   input clk,
   input rst,


   input      [DATA_W-1:0] i_tdata,
   input                   i_tvalid,
   output reg              i_tready,


   output reg [DATA_W-1:0] o_tdata,
   output reg [KEEP_W-1:0] o_tkeep,
   output reg              o_tlast,
   output reg              o_tvalid,
   input                   o_tready
);


  localparam                  ESC_WORD_W = 32;
  localparam [ESC_WORD_W-1:0] ESC_WORD   = 'hDEADBEEF;






  reg              save_flags;
  reg              tlast_saved;
  reg [KEEP_W-1:0] tkeep_saved;

  always @(posedge clk) begin
    if (save_flags) begin

      tlast_saved <= i_tdata[0];
      tkeep_saved <= i_tdata[1 +: KEEP_W];
    end
  end






  localparam ST_IDLE = 0;
  localparam ST_DATA = 1;

  reg [0:0] state = ST_IDLE;
  reg [0:0] next_state;

  always @(posedge clk) begin
    if (rst) begin
      state <= ST_IDLE;
    end else begin
      state <= next_state;
    end
  end

  always @(*) begin

    o_tdata    = i_tdata;
    o_tlast    = 1'b0;
    o_tkeep    = {KEEP_W{1'b1}};
    save_flags = 1'b0;
    next_state = state;
    o_tvalid   = i_tvalid;
    i_tready   = o_tready;

    case(state)




      ST_IDLE: begin
        if ((i_tdata[DATA_W-1 -: ESC_WORD_W] == ESC_WORD) && i_tvalid) begin
          save_flags = 1'b1;
          next_state = ST_DATA;
          o_tvalid   = 1'b0;
          i_tready   = 1'b1;
        end
      end




      ST_DATA: begin
        o_tlast = tlast_saved;
        o_tkeep = tkeep_saved;
        if (i_tvalid & o_tready) begin
          next_state = ST_IDLE;
        end
      end
    endcase
  end

endmodule