data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv
 line:6: before: "<"
1: b"%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:6: syntax error, unexpected '<', expecting TYPE-IDENTIFIER\n param1 = <value> ,\n          ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:9: syntax error, unexpected '.', expecting IDENTIFIER or '=' or do or final\n input  logic clk, rst, ...\n                        ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:10: syntax error, unexpected '.', expecting IDENTIFIER or '=' or do or final\n input  logic [7:0] inp1, inp2, ...\n                                ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:11: syntax error, unexpected '.', expecting IDENTIFIER or '=' or do or final\n output  logic [15:0] outp1, outp2, ...);\n                                    ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:16: syntax error, unexpected '.', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\n typedef enum logic [10:0] {A, B, C, ...} state;\n                                     ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:20: syntax error, unexpected '<', expecting TYPE-IDENTIFIER\n const logic [7:0] T1 = <value> ;\n                        ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:21: syntax error, unexpected '<', expecting TYPE-IDENTIFIER\n const logic [7:0] T2 = <value> ;\n                        ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:22: syntax error, unexpected '<', expecting TYPE-IDENTIFIER\n const logic [7:0] tmax = <value> ; \n                          ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:28: syntax error, unexpected always_ff\n always_ff @(posedge clk, posedge rst)\n ^~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module module_name
#(parameter
	param1 = <value> ,
	param2 = <value> )
(
	input 	logic clk, rst, ...
	input 	logic [7:0] inp1, inp2, ...
	output 	logic [15:0] outp1, outp2, ...);




 typedef enum logic [10:0] {A, B, C, ...} state;
 state pr_state, nx_state;


 const logic [7:0] T1 = <value> ;
 const logic [7:0] T2 = <value> ;
 const logic [7:0] tmax = <value> ;
 logic [7:0] t;




 always_ff @(posedge clk, posedge rst)
	if (rst) t < = 0;
	else if (pr_state != nx_state) t <= 0;
	else if (t != tmax) t <= t + 1;


 always_ff @(posedge clk, posedge rst)
	if (rst) pr_state <= A;
	else pr_state <= nx_state;
 

 always_comb
	case (pr_state)
		A: begin
			outp1 = <value> ;
			outp2 = <value> ;
			...
			if (... and t > =T1-1) nx_state = B;
			else if (... and t >= T2-1) nx_state = ...;
			else nx_state = A;
		end
 
		B: begin
			outp1 = <value> ;
			outp2 = <value> ;
			...
			if (... and t >= T3-1) nx_state = C;
			else if (...) nx_state = ...;
			else nx_state = B;
		end
 
		C: begin
			...
			end
		...
	endcase


	always_ff @(posedge clk)
		if (rst) begin
			new_outp1 <= ...;
			new_outp2 <= ...; ...
		end
		else begin
			new_outp1 <= outp1;
			new_outp2 <= outp2; ...
		end

 endmodule
module module_name
#(parameter
	param1 = <value> ,
	param2 = <value> )
(
	input 	logic clk, rst, ...
	input 	logic [7:0] inp1, inp2, ...
	output 	logic [15:0] outp1, outp2, ...);





 typedef enum logic [10:0] {A, B, C, ...} state;
 state pr_state, nx_state;


 const logic [7:0] T1 = <value> ;
 const logic [7:0] T2 = <value> ;
 const logic [7:0] tmax = <value> ;
 logic [7:0] t;




 always_ff @(posedge clk, posedge rst)
	if (rst) t < = 0;
	else if (pr_state != nx_state) t <= 0;
	else if (t != tmax) t <= t + 1;


 always_ff @(posedge clk, posedge rst)
	if (rst) pr_state <= A;
	else pr_state <= nx_state;
 

 always_comb
	case (pr_state)
		A: begin
			outp1 = <value> ;
			outp2 = <value> ;
			...
			if (... and t > =T1-1) nx_state = B;
			else if (... and t >= T2-1) nx_state = ...;
			else nx_state = A;
		end
 
		B: begin
			outp1 = <value> ;
			outp2 = <value> ;
			...
			if (... and t >= T3-1) nx_state = C;
			else if (...) nx_state = ...;
			else nx_state = B;
		end
 
		C: begin
			...
			end
		...
	endcase


	always_ff @(posedge clk)
		if (rst) begin
			new_outp1 <= ...;
			new_outp2 <= ...; ...
		end
		else begin
			new_outp1 <= outp1;
			new_outp2 <= outp2; ...
		end

 endmodule