data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI.v
1: b"%Error: data/full_repos/permissive/113268705/FPGA_SPI/FPGA_SPI.v:21: Cannot find file containing module: 'FPGA_SPI_MASTER'\nFPGA_SPI_MASTER MS(CLK,SCLK,MOSI,MISO,SS,\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113268705/FPGA_SPI,data/full_repos/permissive/113268705/FPGA_SPI_MASTER\n             data/full_repos/permissive/113268705/FPGA_SPI,data/full_repos/permissive/113268705/FPGA_SPI_MASTER.v\n             data/full_repos/permissive/113268705/FPGA_SPI,data/full_repos/permissive/113268705/FPGA_SPI_MASTER.sv\n             FPGA_SPI_MASTER\n             FPGA_SPI_MASTER.v\n             FPGA_SPI_MASTER.sv\n             obj_dir/FPGA_SPI_MASTER\n             obj_dir/FPGA_SPI_MASTER.v\n             obj_dir/FPGA_SPI_MASTER.sv\n%Error: Exiting due to 1 error(s)\n"
module FPGA_SPI(CLK,SCLK,MOSI,MISO,SS);

input CLK;

inout wire SCLK,MOSI,SS,MISO;

wire[7:0] DATA_IN;
reg[7:0] DATA_OUT;

reg START_BIT;
wire END_BIT;

integer counter;

initial begin
	DATA_OUT = 8'h0;
	START_BIT = 0;
	counter = 0;
end

FPGA_SPI_MASTER MS(CLK,SCLK,MOSI,MISO,SS,
						 DATA_IN,DATA_OUT,START_BIT,END_BIT);





	
always @(posedge CLK) begin
	counter = counter + 1;
	if(counter == 50_000_000) begin
		counter = 0;
	end
end

always @(posedge CLK) begin
	if(counter == 0) begin
		START_BIT = 0;
	end
	
	if(END_BIT == 1) begin
		START_BIT = 1;
	end
end

always @(posedge SS) begin
	DATA_OUT = DATA_OUT + 1;
end








endmodule
module FPGA_SPI(CLK,SCLK,MOSI,MISO,SS);


input CLK;

inout wire SCLK,MOSI,SS,MISO;

wire[7:0] DATA_IN;
reg[7:0] DATA_OUT;

reg START_BIT;
wire END_BIT;

integer counter;

initial begin
	DATA_OUT = 8'h0;
	START_BIT = 0;
	counter = 0;
end

FPGA_SPI_MASTER MS(CLK,SCLK,MOSI,MISO,SS,
						 DATA_IN,DATA_OUT,START_BIT,END_BIT);





	
always @(posedge CLK) begin
	counter = counter + 1;
	if(counter == 50_000_000) begin
		counter = 0;
	end
end

always @(posedge CLK) begin
	if(counter == 0) begin
		START_BIT = 0;
	end
	
	if(END_BIT == 1) begin
		START_BIT = 1;
	end
end

always @(posedge SS) begin
	DATA_OUT = DATA_OUT + 1;
end








endmodule