data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_clk_cross.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_clk_cross.v:59: Cannot find file containing module: 'reset_sync'\n  reset_sync master_reset_sync_inst (\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils,data/full_repos/permissive/214858095/reset_sync\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils,data/full_repos/permissive/214858095/reset_sync.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils,data/full_repos/permissive/214858095/reset_sync.sv\n             reset_sync\n             reset_sync.v\n             reset_sync.sv\n             obj_dir/reset_sync\n             obj_dir/reset_sync.v\n             obj_dir/reset_sync.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_clk_cross.v:62: Cannot find file containing module: 'reset_sync'\n  reset_sync slave_reset_sync_inst (\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_clk_cross.v:107: Cannot find file containing module: 'handshake'\n  handshake #(\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_clk_cross.v:163: Cannot find file containing module: 'handshake'\n  handshake #(\n  ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module ctrlport_clk_cross (
  input wire rst,





  input  wire        s_ctrlport_clk,
  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [ 9:0] s_ctrlport_req_portid,
  input  wire [15:0] s_ctrlport_req_rem_epid,
  input  wire [ 9:0] s_ctrlport_req_rem_portid,
  input  wire [31:0] s_ctrlport_req_data,
  input  wire [ 3:0] s_ctrlport_req_byte_en,
  input  wire        s_ctrlport_req_has_time,
  input  wire [63:0] s_ctrlport_req_time,
  output wire        s_ctrlport_resp_ack,
  output wire [ 1:0] s_ctrlport_resp_status,
  output wire [31:0] s_ctrlport_resp_data,





  input  wire        m_ctrlport_clk,
  output wire        m_ctrlport_req_wr,
  output wire        m_ctrlport_req_rd,
  output wire [19:0] m_ctrlport_req_addr,
  output wire [ 9:0] m_ctrlport_req_portid,
  output wire [15:0] m_ctrlport_req_rem_epid,
  output wire [ 9:0] m_ctrlport_req_rem_portid,
  output wire [31:0] m_ctrlport_req_data,
  output wire [ 3:0] m_ctrlport_req_byte_en,
  output wire        m_ctrlport_req_has_time,
  output wire [63:0] m_ctrlport_req_time,
  input  wire        m_ctrlport_resp_ack,
  input  wire [ 1:0] m_ctrlport_resp_status,
  input  wire [31:0] m_ctrlport_resp_data
);



  wire m_rst, s_rst;
  reset_sync master_reset_sync_inst (
    .clk(m_ctrlport_clk), .reset_in(rst), .reset_out(m_rst)
  );
  reset_sync slave_reset_sync_inst (
    .clk(s_ctrlport_clk), .reset_in(rst), .reset_out(s_rst)
  );





  localparam REQ_W =
    1  +
    1  +
    20 +
    10 +
    16 +
    10 +
    32 +
    4  +
    1  +
    64;

  wire [ REQ_W-1:0] s_req_flat;
  wire [ REQ_W-1:0] m_req_flat;
  wire              m_req_flat_valid;
  wire              m_ctrlport_req_wr_tmp;
  wire              m_ctrlport_req_rd_tmp;

  assign s_req_flat = {
    s_ctrlport_req_wr,
    s_ctrlport_req_rd,
    s_ctrlport_req_addr,
    s_ctrlport_req_portid,
    s_ctrlport_req_rem_epid,
    s_ctrlport_req_rem_portid,
    s_ctrlport_req_data,
    s_ctrlport_req_byte_en,
    s_ctrlport_req_has_time,
    s_ctrlport_req_time
  };







  handshake #(
    .WIDTH(REQ_W)
  ) req_handshake_inst (
    .clk_a(s_ctrlport_clk),
    .rst_a(s_rst),
    .valid_a((s_ctrlport_req_wr | s_ctrlport_req_rd) & ~s_rst),
    .data_a(s_req_flat),
    .busy_a(),
    .clk_b(m_ctrlport_clk),
    .valid_b(m_req_flat_valid),
    .data_b(m_req_flat)
  );

  assign {
    m_ctrlport_req_wr_tmp,
    m_ctrlport_req_rd_tmp,
    m_ctrlport_req_addr,
    m_ctrlport_req_portid,
    m_ctrlport_req_rem_epid,
    m_ctrlport_req_rem_portid,
    m_ctrlport_req_data,
    m_ctrlport_req_byte_en,
    m_ctrlport_req_has_time,
    m_ctrlport_req_time
  } = m_req_flat;

  assign m_ctrlport_req_wr = m_ctrlport_req_wr_tmp & m_req_flat_valid & ~m_rst;
  assign m_ctrlport_req_rd = m_ctrlport_req_rd_tmp & m_req_flat_valid & ~m_rst;






  localparam RESP_W =
    1  +
    2  +
    32;

  wire [RESP_W-1:0] m_resp_flat;
  wire [RESP_W-1:0] s_resp_flat;
  wire              s_resp_flat_valid;
  wire              s_ctrlport_resp_ack_tmp;

  assign m_resp_flat = {
    m_ctrlport_resp_ack,
    m_ctrlport_resp_status,
    m_ctrlport_resp_data
  };







  handshake #(
    .WIDTH(RESP_W)
  ) resp_handshake_inst (
    .clk_a(m_ctrlport_clk),
    .rst_a(m_rst),
    .valid_a(m_ctrlport_resp_ack & ~m_rst),
    .data_a(m_resp_flat),
    .busy_a(),
    .clk_b(s_ctrlport_clk),
    .valid_b(s_resp_flat_valid),
    .data_b(s_resp_flat)
  );

  assign {
    s_ctrlport_resp_ack_tmp,
    s_ctrlport_resp_status,
    s_ctrlport_resp_data
  } = s_resp_flat;

  assign s_ctrlport_resp_ack = s_ctrlport_resp_ack_tmp & s_resp_flat_valid & ~s_rst;

endmodule
module ctrlport_clk_cross (
  input wire rst,





  input  wire        s_ctrlport_clk,
  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [ 9:0] s_ctrlport_req_portid,
  input  wire [15:0] s_ctrlport_req_rem_epid,
  input  wire [ 9:0] s_ctrlport_req_rem_portid,
  input  wire [31:0] s_ctrlport_req_data,
  input  wire [ 3:0] s_ctrlport_req_byte_en,
  input  wire        s_ctrlport_req_has_time,
  input  wire [63:0] s_ctrlport_req_time,
  output wire        s_ctrlport_resp_ack,
  output wire [ 1:0] s_ctrlport_resp_status,
  output wire [31:0] s_ctrlport_resp_data,





  input  wire        m_ctrlport_clk,
  output wire        m_ctrlport_req_wr,
  output wire        m_ctrlport_req_rd,
  output wire [19:0] m_ctrlport_req_addr,
  output wire [ 9:0] m_ctrlport_req_portid,
  output wire [15:0] m_ctrlport_req_rem_epid,
  output wire [ 9:0] m_ctrlport_req_rem_portid,
  output wire [31:0] m_ctrlport_req_data,
  output wire [ 3:0] m_ctrlport_req_byte_en,
  output wire        m_ctrlport_req_has_time,
  output wire [63:0] m_ctrlport_req_time,
  input  wire        m_ctrlport_resp_ack,
  input  wire [ 1:0] m_ctrlport_resp_status,
  input  wire [31:0] m_ctrlport_resp_data
);




  wire m_rst, s_rst;
  reset_sync master_reset_sync_inst (
    .clk(m_ctrlport_clk), .reset_in(rst), .reset_out(m_rst)
  );
  reset_sync slave_reset_sync_inst (
    .clk(s_ctrlport_clk), .reset_in(rst), .reset_out(s_rst)
  );





  localparam REQ_W =
    1  +
    1  +
    20 +
    10 +
    16 +
    10 +
    32 +
    4  +
    1  +
    64;

  wire [ REQ_W-1:0] s_req_flat;
  wire [ REQ_W-1:0] m_req_flat;
  wire              m_req_flat_valid;
  wire              m_ctrlport_req_wr_tmp;
  wire              m_ctrlport_req_rd_tmp;

  assign s_req_flat = {
    s_ctrlport_req_wr,
    s_ctrlport_req_rd,
    s_ctrlport_req_addr,
    s_ctrlport_req_portid,
    s_ctrlport_req_rem_epid,
    s_ctrlport_req_rem_portid,
    s_ctrlport_req_data,
    s_ctrlport_req_byte_en,
    s_ctrlport_req_has_time,
    s_ctrlport_req_time
  };







  handshake #(
    .WIDTH(REQ_W)
  ) req_handshake_inst (
    .clk_a(s_ctrlport_clk),
    .rst_a(s_rst),
    .valid_a((s_ctrlport_req_wr | s_ctrlport_req_rd) & ~s_rst),
    .data_a(s_req_flat),
    .busy_a(),
    .clk_b(m_ctrlport_clk),
    .valid_b(m_req_flat_valid),
    .data_b(m_req_flat)
  );

  assign {
    m_ctrlport_req_wr_tmp,
    m_ctrlport_req_rd_tmp,
    m_ctrlport_req_addr,
    m_ctrlport_req_portid,
    m_ctrlport_req_rem_epid,
    m_ctrlport_req_rem_portid,
    m_ctrlport_req_data,
    m_ctrlport_req_byte_en,
    m_ctrlport_req_has_time,
    m_ctrlport_req_time
  } = m_req_flat;

  assign m_ctrlport_req_wr = m_ctrlport_req_wr_tmp & m_req_flat_valid & ~m_rst;
  assign m_ctrlport_req_rd = m_ctrlport_req_rd_tmp & m_req_flat_valid & ~m_rst;






  localparam RESP_W =
    1  +
    2  +
    32;

  wire [RESP_W-1:0] m_resp_flat;
  wire [RESP_W-1:0] s_resp_flat;
  wire              s_resp_flat_valid;
  wire              s_ctrlport_resp_ack_tmp;

  assign m_resp_flat = {
    m_ctrlport_resp_ack,
    m_ctrlport_resp_status,
    m_ctrlport_resp_data
  };







  handshake #(
    .WIDTH(RESP_W)
  ) resp_handshake_inst (
    .clk_a(m_ctrlport_clk),
    .rst_a(m_rst),
    .valid_a(m_ctrlport_resp_ack & ~m_rst),
    .data_a(m_resp_flat),
    .busy_a(),
    .clk_b(s_ctrlport_clk),
    .valid_b(s_resp_flat_valid),
    .data_b(s_resp_flat)
  );

  assign {
    s_ctrlport_resp_ack_tmp,
    s_ctrlport_resp_status,
    s_ctrlport_resp_data
  } = s_resp_flat;

  assign s_ctrlport_resp_ack = s_ctrlport_resp_ack_tmp & s_resp_flat_valid & ~s_rst;

endmodule