data/full_repos/permissive/210844779/lab5/5.2/dff.v
 line:12: before: "assign"
1: b'%Error: data/full_repos/permissive/210844779/lab5/5.2/dff.v:18: Unsupported: Verilog 1995 deassign\n      deassign q;\n      ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dff(d,clk,clr,preset,q);
  
  input d,clk,clr,preset;
  output reg q;
  
  always@(posedge clk)
  q<=d;
  
  always@(clr,preset)
  begin
    if(clr==0)
      assign q=0;
      
    else if (preset)
      assign q=1;
      
    else
      deassign q;
      
  end

endmodule
module dff(d,clk,clr,preset,q);

  
  input d,clk,clr,preset;
  output reg q;
  
  always@(posedge clk)
  q<=d;
  
  always@(clr,preset)
  begin
    if(clr==0)
      assign q=0;
      
    else if (preset)
      assign q=1;
      
    else
      deassign q;
      
  end

endmodule