data/full_repos/permissive/107007139/Project/mic_in_latch.v
data/verilator_xmls/92e0ca50-06da-46b3-9c72-0c5488d9f222.xml
module mic_in_latch(
    input  wire clk_20k,
    input  wire [11:0] mic_in,
    output reg  [11:0] led_out,
    output reg  [11:0] speaker_out
    );
    
    always @(posedge clk_20k) begin
        led_out <= mic_in;
        speaker_out <= mic_in;
    end
endmodule
module mic_in_latch(
    input  wire clk_20k,
    input  wire [11:0] mic_in,
    output reg  [11:0] led_out,
    output reg  [11:0] speaker_out
    );

    
    always @(posedge clk_20k) begin
        led_out <= mic_in;
        speaker_out <= mic_in;
    end
endmodule