data/full_repos/permissive/183345139/hba_motor/pwm_dir_tb/pwm_dir_tb.v
1: b'%Error: data/full_repos/permissive/183345139/hba_motor/pwm_dir_tb/pwm_dir_tb.v:88: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("pwm_dir.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/183345139/hba_motor/pwm_dir_tb/pwm_dir_tb.v:89: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, pwm_dir_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/183345139/hba_motor/pwm_dir_tb/pwm_dir_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/183345139/hba_motor/pwm_dir_tb/pwm_dir_tb.v:105: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/183345139/hba_motor/pwm_dir_tb/pwm_dir_tb.v:107: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/183345139/hba_motor/pwm_dir_tb/pwm_dir_tb.v:110: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/183345139/hba_motor/pwm_dir_tb/pwm_dir_tb.v:115: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/183345139/hba_motor/pwm_dir_tb/pwm_dir_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n    #8.33 clk = ~clk;\n    ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pwm_dir_tb;



localparam CLK_FREQUENCY = 60_000_000;
localparam PWM_FREQUENCY = 100_000;
localparam PERIOD_COUNT = (CLK_FREQUENCY / PWM_FREQUENCY);
localparam DUTY_1_PERCENT = (PERIOD_COUNT / 100);





reg clk;
reg reset;
reg en;
reg float;
reg [6:0] duty_cycle;
reg dir_in;


wire pwm;
wire dir_out;
wire float_n;


reg done;



pmw_dir # 
(
    .CLK_FREQUENCY(CLK_FREQUENCY),
    .PWM_FREQUENCY(PWM_FREQUENCY)
) pwm_dir_inst
(

    .clk(clk),
    .reset(reset),
    .en(en),
    .float(float),
    .duty_cycle(duty_cycle),
    .dir_in(dir_in),


    .pwm(pwm),
    .dir_out(dir_out),
    .float_n(float_n)
);



initial begin
    $dumpfile("pwm_dir.vcd");
    $dumpvars(0, pwm_dir_tb);

    clk         = 0;
    reset       = 0;
    en          = 0;
    float       = 0;
    duty_cycle  = 0;
    dir_in      = 0;


    #100;
    $display("CLK_FREQUENCY: %d",CLK_FREQUENCY);
    $display("PWM_FREQUENCY: %d",PWM_FREQUENCY);
    $display("PERIOD_COUNT: %d",PERIOD_COUNT);
    $display("DUTY_1_PERCENT: %d",DUTY_1_PERCENT);

    @(posedge clk);
    reset = 1;
    @(posedge clk);
    @(posedge clk);
    reset = 0;
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    duty_cycle = 50;
    en = 1;
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);

    @(posedge done);

    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    $finish;
end


always begin
    #8.33 clk = ~clk;
end


reg [9:0] pulse_100k_count;
reg [3:0] loops;
always @ (posedge clk)
begin
    if (reset) begin
        pulse_100k_count <= 0;
        loops <= 0;
        done <= 0;
    end else begin
        pulse_100k_count <= pulse_100k_count + 1;
        if (pulse_100k_count == PERIOD_COUNT) begin
            pulse_100k_count <= 0;
            loops <= loops + 1;
        end
        if (loops == 4) begin
            done <= 1;
        end
    end
end


endmodule
module pwm_dir_tb;




localparam CLK_FREQUENCY = 60_000_000;
localparam PWM_FREQUENCY = 100_000;
localparam PERIOD_COUNT = (CLK_FREQUENCY / PWM_FREQUENCY);
localparam DUTY_1_PERCENT = (PERIOD_COUNT / 100);





reg clk;
reg reset;
reg en;
reg float;
reg [6:0] duty_cycle;
reg dir_in;


wire pwm;
wire dir_out;
wire float_n;


reg done;



pmw_dir # 
(
    .CLK_FREQUENCY(CLK_FREQUENCY),
    .PWM_FREQUENCY(PWM_FREQUENCY)
) pwm_dir_inst
(

    .clk(clk),
    .reset(reset),
    .en(en),
    .float(float),
    .duty_cycle(duty_cycle),
    .dir_in(dir_in),


    .pwm(pwm),
    .dir_out(dir_out),
    .float_n(float_n)
);



initial begin
    $dumpfile("pwm_dir.vcd");
    $dumpvars(0, pwm_dir_tb);

    clk         = 0;
    reset       = 0;
    en          = 0;
    float       = 0;
    duty_cycle  = 0;
    dir_in      = 0;


    #100;
    $display("CLK_FREQUENCY: %d",CLK_FREQUENCY);
    $display("PWM_FREQUENCY: %d",PWM_FREQUENCY);
    $display("PERIOD_COUNT: %d",PERIOD_COUNT);
    $display("DUTY_1_PERCENT: %d",DUTY_1_PERCENT);

    @(posedge clk);
    reset = 1;
    @(posedge clk);
    @(posedge clk);
    reset = 0;
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    duty_cycle = 50;
    en = 1;
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);

    @(posedge done);

    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    @(posedge clk);
    $finish;
end


always begin
    #8.33 clk = ~clk;
end


reg [9:0] pulse_100k_count;
reg [3:0] loops;
always @ (posedge clk)
begin
    if (reset) begin
        pulse_100k_count <= 0;
        loops <= 0;
        done <= 0;
    end else begin
        pulse_100k_count <= pulse_100k_count + 1;
        if (pulse_100k_count == PERIOD_COUNT) begin
            pulse_100k_count <= 0;
            loops <= loops + 1;
        end
        if (loops == 4) begin
            done <= 1;
        end
    end
end


endmodule