data/full_repos/permissive/143278/ivltests/pr273.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr273.v:38: Unsupported: Ignoring delay on this delayed statement.\n     #8;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr273.v:40: Unsupported: Ignoring delay on this delayed statement.\n     #8;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr273.v:48: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dff2 (q,clk,d0,d1);

input clk,d0,d1;
output [1:0] q;

reg [1:0] q;

  always @(posedge clk)
	  q <= {d1,d0};

endmodule
module dff2 (q,clk,d0,d1);


input clk,d0,d1;
output [1:0] q;

reg [1:0] q;

  always @(posedge clk)
	  q <= {d1,d0};

endmodule