data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top.v
1: b"%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top.v:73: Cannot find file containing module: 'cmd_parser'\ncmd_parser cmd_parser_inst\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb,data/full_repos/permissive/150947952/cmd_parser\n             data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb,data/full_repos/permissive/150947952/cmd_parser.v\n             data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb,data/full_repos/permissive/150947952/cmd_parser.sv\n             cmd_parser\n             cmd_parser.v\n             cmd_parser.sv\n             obj_dir/cmd_parser\n             obj_dir/cmd_parser.v\n             obj_dir/cmd_parser.sv\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top.v:105: Cannot find file containing module: 'string_process_match'\nstring_process_match string_process_match_inst\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top.v:135: Cannot find file containing module: 'md5core'\nmd5core md5core_inst\n^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module sim_top
(
    input wire clk,
    input wire reset,


    input wire [7:0] rxd_data,
    input wire rxd_data_ready,


    input wire txd_busy,
    output wire txd_start,
    output wire [7:0] txd_data,


    output wire [7:0] led
);



wire proc_start;
wire [15:0] proc_num_bytes;
wire [7:0] proc_data;
wire proc_data_valid;
wire proc_match_char_next;
wire [127:0] proc_target_hash;

wire proc_done;
wire proc_match;
wire [15:0] proc_byte_pos;
wire [7:0] proc_match_char;

wire [31:0] a_ret;
wire [31:0] b_ret;
wire [31:0] c_ret;
wire [31:0] d_ret;
wire [151:0] md5_msg_ret;
wire md5_msg_ret_valid;

wire [151:0] md5_msg;
wire md5_msg_valid;



cmd_parser cmd_parser_inst
(
    .clk(clk),
    .reset(reset),


    .rxd_data(rxd_data),
    .rxd_data_ready(rxd_data_ready),


    .txd_busy(txd_busy),
    .txd_start(txd_start),
    .txd_data(txd_data),


    .proc_done(proc_done),
    .proc_match(proc_match),
    .proc_byte_pos(proc_byte_pos),
    .proc_match_char(proc_match_char),

    .proc_start(proc_start),
    .proc_num_bytes(proc_num_bytes),
    .proc_data(proc_data),
    .proc_data_valid(proc_data_valid),
    .proc_match_char_next(proc_match_char_next),
    .proc_target_hash(proc_target_hash),


    .led(led)
);


string_process_match string_process_match_inst
(
    .clk(clk),
    .reset(reset),


    .proc_start(proc_start),
    .proc_num_bytes(proc_num_bytes),
    .proc_data(proc_data),
    .proc_data_valid(proc_data_valid),
    .proc_match_char_next(proc_match_char_next),
    .proc_target_hash(proc_target_hash),

    .proc_done(proc_done),
    .proc_match(proc_match),
    .proc_byte_pos(proc_byte_pos),
    .proc_match_char(proc_match_char),


    .a_ret(a_ret),
    .b_ret(b_ret),
    .c_ret(c_ret),
    .d_ret(d_ret),
    .md5_msg_ret(md5_msg_ret),
    .md5_msg_ret_valid(md5_msg_ret_valid),

    .md5_msg(md5_msg),
    .md5_msg_valid(md5_msg_valid)
);

md5core md5core_inst
(
    .clk(clk),
    .reset(reset),
    .en(1'b1),

    .m_in(md5_msg),
    .valid_in(md5_msg_valid),

    .a_out(a_ret),
    .b_out(b_ret),
    .c_out(c_ret),
    .d_out(d_ret),
    .m_out(md5_msg_ret),
    .valid_out(md5_msg_ret_valid)
);

endmodule
module sim_top
(
    input wire clk,
    input wire reset,


    input wire [7:0] rxd_data,
    input wire rxd_data_ready,


    input wire txd_busy,
    output wire txd_start,
    output wire [7:0] txd_data,


    output wire [7:0] led
);




wire proc_start;
wire [15:0] proc_num_bytes;
wire [7:0] proc_data;
wire proc_data_valid;
wire proc_match_char_next;
wire [127:0] proc_target_hash;

wire proc_done;
wire proc_match;
wire [15:0] proc_byte_pos;
wire [7:0] proc_match_char;

wire [31:0] a_ret;
wire [31:0] b_ret;
wire [31:0] c_ret;
wire [31:0] d_ret;
wire [151:0] md5_msg_ret;
wire md5_msg_ret_valid;

wire [151:0] md5_msg;
wire md5_msg_valid;



cmd_parser cmd_parser_inst
(
    .clk(clk),
    .reset(reset),


    .rxd_data(rxd_data),
    .rxd_data_ready(rxd_data_ready),


    .txd_busy(txd_busy),
    .txd_start(txd_start),
    .txd_data(txd_data),


    .proc_done(proc_done),
    .proc_match(proc_match),
    .proc_byte_pos(proc_byte_pos),
    .proc_match_char(proc_match_char),

    .proc_start(proc_start),
    .proc_num_bytes(proc_num_bytes),
    .proc_data(proc_data),
    .proc_data_valid(proc_data_valid),
    .proc_match_char_next(proc_match_char_next),
    .proc_target_hash(proc_target_hash),


    .led(led)
);


string_process_match string_process_match_inst
(
    .clk(clk),
    .reset(reset),


    .proc_start(proc_start),
    .proc_num_bytes(proc_num_bytes),
    .proc_data(proc_data),
    .proc_data_valid(proc_data_valid),
    .proc_match_char_next(proc_match_char_next),
    .proc_target_hash(proc_target_hash),

    .proc_done(proc_done),
    .proc_match(proc_match),
    .proc_byte_pos(proc_byte_pos),
    .proc_match_char(proc_match_char),


    .a_ret(a_ret),
    .b_ret(b_ret),
    .c_ret(c_ret),
    .d_ret(d_ret),
    .md5_msg_ret(md5_msg_ret),
    .md5_msg_ret_valid(md5_msg_ret_valid),

    .md5_msg(md5_msg),
    .md5_msg_valid(md5_msg_valid)
);

md5core md5core_inst
(
    .clk(clk),
    .reset(reset),
    .en(1'b1),

    .m_in(md5_msg),
    .valid_in(md5_msg_valid),

    .a_out(a_ret),
    .b_out(b_ret),
    .c_out(c_ret),
    .d_out(d_ret),
    .m_out(md5_msg_ret),
    .valid_out(md5_msg_ret_valid)
);

endmodule