data/full_repos/permissive/207835546/Shift Register/Shift Register.v
1: b'%Error: Cannot find file containing module: Register,data/full_repos/permissive/207835546\n        ... Looked in:\n             data/full_repos/permissive/207835546/Shift/Register,data/full_repos/permissive/207835546\n             data/full_repos/permissive/207835546/Shift/Register,data/full_repos/permissive/207835546.v\n             data/full_repos/permissive/207835546/Shift/Register,data/full_repos/permissive/207835546.sv\n             Register,data/full_repos/permissive/207835546\n             Register,data/full_repos/permissive/207835546.v\n             Register,data/full_repos/permissive/207835546.sv\n             obj_dir/Register,data/full_repos/permissive/207835546\n             obj_dir/Register,data/full_repos/permissive/207835546.v\n             obj_dir/Register,data/full_repos/permissive/207835546.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/207835546/Shift\n%Error: Cannot find file containing module: Register/Shift\n%Error: Cannot find file containing module: Register.v\n%Error: Exiting due to 4 error(s)\n'
module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);
  output reg [7:0] op;
  input load;
  input [1:0] sh_ro_lt_rt;
  input [7:0] ip;
  input clk, rst_a;
  
  reg [7:0]temp;
  
  
  
  always @(posedge clk or posedge rst_a)
   begin
     if (rst_a)
       
       op = 0;
      
     else    
       case(load)
         1'b1: 
          begin
            temp = ip;

          end
         1'b0:
          case (sh_ro_lt_rt)
            2'b00:  op = temp<<1;
            2'b01:  op = temp>>1;
            2'b10:  op = {temp[6:0],temp[7]};
            2'b11:  op = {temp[0], temp[7:1]};
                   
            default: $display("Invalid Shift Control Input");
          endcase
      
        
         
        default: $display("Invalid Load Control Input");
        endcase
   
    end 
    
  endmodule
module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);

  output reg [7:0] op;
  input load;
  input [1:0] sh_ro_lt_rt;
  input [7:0] ip;
  input clk, rst_a;
  
  reg [7:0]temp;
  
  
  
  always @(posedge clk or posedge rst_a)
   begin
     if (rst_a)
       
       op = 0;
      
     else    
       case(load)
         1'b1: 
          begin
            temp = ip;

          end
         1'b0:
          case (sh_ro_lt_rt)
            2'b00:  op = temp<<1;
            2'b01:  op = temp>>1;
            2'b10:  op = {temp[6:0],temp[7]};
            2'b11:  op = {temp[0], temp[7:1]};
                   
            default: $display("Invalid Shift Control Input");
          endcase
      
        
         
        default: $display("Invalid Load Control Input");
        endcase
   
    end 
    
  endmodule