data/full_repos/permissive/109400221/hdl/nand/ACounter.v
data/verilator_xmls/1754c78f-9cb2-43df-8ed6-22ba872f3e0d.xml
module ACounter(
      clk,
      Res,
      Set835,
      CntEn ,
      CntOut,
      TC2048,
      TC3
   );
   input clk;
   input Res;
   input Set835;
   input CntEn;
   output [11:0]  CntOut;
   output  reg TC2048;
   output  reg TC3;

reg [11:0] cnt_state;

always@(posedge clk)
  if (Res)
    cnt_state <= 0;
  else if (Set835)
    cnt_state <=12'h835;
  else if (CntEn)
    cnt_state <= cnt_state + 1;


always@(cnt_state)
   if (cnt_state== 12'h7FF) begin
      TC2048 <= 1;
      TC3 <=0;
   end else if (cnt_state[7:0] == 8'h40) begin
     TC3 <= 1;
     TC2048 <= 0;
   end




   else begin
     TC3 <=0;
     TC2048 <= 0;
   end


assign CntOut = cnt_state;

endmodule
module ACounter(
      clk,
      Res,
      Set835,
      CntEn ,
      CntOut,
      TC2048,
      TC3
   );

   input clk;
   input Res;
   input Set835;
   input CntEn;
   output [11:0]  CntOut;
   output  reg TC2048;
   output  reg TC3;

reg [11:0] cnt_state;

always@(posedge clk)
  if (Res)
    cnt_state <= 0;
  else if (Set835)
    cnt_state <=12'h835;
  else if (CntEn)
    cnt_state <= cnt_state + 1;


always@(cnt_state)
   if (cnt_state== 12'h7FF) begin
      TC2048 <= 1;
      TC3 <=0;
   end else if (cnt_state[7:0] == 8'h40) begin
     TC3 <= 1;
     TC2048 <= 0;
   end




   else begin
     TC3 <=0;
     TC2048 <= 0;
   end


assign CntOut = cnt_state;

endmodule