data/full_repos/permissive/115035459/verilog/src/lib/easypll.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/115035459/verilog/src/lib/easypll.v:66: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                    : ... Top module \'easypll\'\nmodule easypll #(\n       ^~~~~~~\n                                                                                    : ... Top module \'pll_pad\'\nmodule pll_pad #(\n       ^~~~~~~\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/easypll.v:76: Cannot find file containing module: \'SB_PLL40_PAD\'\n SB_PLL40_PAD #(\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/SB_PLL40_PAD\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/SB_PLL40_PAD.v\n             data/full_repos/permissive/115035459/verilog/src/lib,data/full_repos/permissive/115035459/SB_PLL40_PAD.sv\n             SB_PLL40_PAD\n             SB_PLL40_PAD.v\n             SB_PLL40_PAD.sv\n             obj_dir/SB_PLL40_PAD\n             obj_dir/SB_PLL40_PAD.v\n             obj_dir/SB_PLL40_PAD.sv\n%Error: data/full_repos/permissive/115035459/verilog/src/lib/easypll.v:23: Cannot find file containing module: \'SB_PLL40_CORE\'\n SB_PLL40_CORE #(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module pll_pad #(
	parameter DIVR = 4'd3,
	parameter DIVF = 7'd40,
	parameter DIVQ = 3'd6
) (
	input clock_input_pad,
	input reset,
	output global_clock_output,
	output pll_is_locked
);
	SB_PLL40_PAD #(
		.FEEDBACK_PATH("SIMPLE"),
		.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
		.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
		.PLLOUT_SELECT("GENCLK"),
		.FDA_FEEDBACK(4'b1111),
		.FDA_RELATIVE(4'b1111),
		.DIVR(4'b0011),
		.DIVF(7'b0101000),
		.DIVQ(3'b110),
		.FILTER_RANGE(3'b010)
	) pll (
		.PACKAGEPIN   (clock_input_pad),
		.PLLOUTGLOBAL (global_clock_output),
		.LOCK         (pll_is_locked),
		.BYPASS       (1'b0),
		.RESETB       (~reset)
	);
endmodule
module pll_pad #(
	parameter DIVR = 4'd3,
	parameter DIVF = 7'd40,
	parameter DIVQ = 3'd6
) (
	input clock_input_pad,
	input reset,
	output global_clock_output,
	output pll_is_locked
);

	SB_PLL40_PAD #(
		.FEEDBACK_PATH("SIMPLE"),
		.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
		.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
		.PLLOUT_SELECT("GENCLK"),
		.FDA_FEEDBACK(4'b1111),
		.FDA_RELATIVE(4'b1111),
		.DIVR(4'b0011),
		.DIVF(7'b0101000),
		.DIVQ(3'b110),
		.FILTER_RANGE(3'b010)
	) pll (
		.PACKAGEPIN   (clock_input_pad),
		.PLLOUTGLOBAL (global_clock_output),
		.LOCK         (pll_is_locked),
		.BYPASS       (1'b0),
		.RESETB       (~reset)
	);
endmodule