data/full_repos/permissive/136009613/rom_tb.v
 line:40: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:7: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/136009613/rom_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Error: data/full_repos/permissive/136009613/rom_tb.v:4: Cannot find file containing module: \'rom\'\n rom rom1(address, data);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/136009613,data/full_repos/permissive/136009613/rom\n             data/full_repos/permissive/136009613,data/full_repos/permissive/136009613/rom.v\n             data/full_repos/permissive/136009613,data/full_repos/permissive/136009613/rom.sv\n             rom\n             rom.v\n             rom.sv\n             obj_dir/rom\n             obj_dir/rom.v\n             obj_dir/rom.sv\n%Error: Exiting due to 1 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rom_tb;
	reg [7:0] address;
	wire [7:0] data;
	rom rom1(address, data);
	initial begin
		address = 8'h00;
		#20
		address = 8'h01;
		#20
		address = 8'h02;
		#20
		address = 8'h03;
		#20
		address = 8'h04;
		#20
		address = 8'h05;
		#20
		address = 8'h06;
		#20
		address = 8'h07;
		#20
		address = 8'h08;
		#20
		address = 8'h09;
		#20
		address = 8'h0A;
		#20
		address = 8'h0B;
		#20
		address = 8'h0C;
		#20
		address = 8'h0D;
		#20
		address = 8'h0E;
		#20
		address = 8'h0F;
		#20
		address = 8'h10;
		#20
		$stop;
	end
endmodule
module rom_tb;

	reg [7:0] address;
	wire [7:0] data;
	rom rom1(address, data);
	initial begin
		address = 8'h00;
		#20
		address = 8'h01;
		#20
		address = 8'h02;
		#20
		address = 8'h03;
		#20
		address = 8'h04;
		#20
		address = 8'h05;
		#20
		address = 8'h06;
		#20
		address = 8'h07;
		#20
		address = 8'h08;
		#20
		address = 8'h09;
		#20
		address = 8'h0A;
		#20
		address = 8'h0B;
		#20
		address = 8'h0C;
		#20
		address = 8'h0D;
		#20
		address = 8'h0E;
		#20
		address = 8'h0F;
		#20
		address = 8'h10;
		#20
		$stop;
	end
endmodule