data/full_repos/permissive/193909872/Implementation/nexys2/sw_p.v
1: b'%Warning-WIDTH: data/full_repos/permissive/193909872/Implementation/nexys2/sw_p.v:36: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'sw\' generates 8 bits.\n                                                                                    : ... In instance sw_p\n   sw_p_r[0] <= sw;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sw_p(

	input clk,
	input rst,
	input [3:0] addra,
	output reg [31:0] douta,
	input [7:0] sw

	);

	reg [31:0] sw_p_r [0:15];

	always@(posedge clk) begin
	
		douta <= sw_p_r[addra];

		if(rst) begin
			sw_p_r[0] <= 0;
			sw_p_r[1] <= 0;
			sw_p_r[2] <= 0;
			sw_p_r[3] <= 0;
			sw_p_r[4] <= 0;
			sw_p_r[5] <= 0;
			sw_p_r[6] <= 0;
			sw_p_r[7] <= 0;
			sw_p_r[8] <= 0;
			sw_p_r[9] <= 0;
			sw_p_r[10] <= 0;
			sw_p_r[11] <= 0;
			sw_p_r[12] <= 0;
			sw_p_r[13] <= 0;
			sw_p_r[14] <= 0;
			sw_p_r[15] <= 0;
		end
		else begin
			sw_p_r[0] <= sw;
		end

	end

endmodule
module sw_p(

	input clk,
	input rst,
	input [3:0] addra,
	output reg [31:0] douta,
	input [7:0] sw

	);


	reg [31:0] sw_p_r [0:15];

	always@(posedge clk) begin
	
		douta <= sw_p_r[addra];

		if(rst) begin
			sw_p_r[0] <= 0;
			sw_p_r[1] <= 0;
			sw_p_r[2] <= 0;
			sw_p_r[3] <= 0;
			sw_p_r[4] <= 0;
			sw_p_r[5] <= 0;
			sw_p_r[6] <= 0;
			sw_p_r[7] <= 0;
			sw_p_r[8] <= 0;
			sw_p_r[9] <= 0;
			sw_p_r[10] <= 0;
			sw_p_r[11] <= 0;
			sw_p_r[12] <= 0;
			sw_p_r[13] <= 0;
			sw_p_r[14] <= 0;
			sw_p_r[15] <= 0;
		end
		else begin
			sw_p_r[0] <= sw;
		end

	end

endmodule