data/full_repos/permissive/196412397/clock_enable_tb.v
1: b'%Error: data/full_repos/permissive/196412397/clock_enable_tb.v:1: Cannot find include file: clock_enable_param.v\n`include "clock_enable_param.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/clock_enable_param.v\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/clock_enable_param.v.v\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/clock_enable_param.v.sv\n             clock_enable_param.v\n             clock_enable_param.v.v\n             clock_enable_param.v.sv\n             obj_dir/clock_enable_param.v\n             obj_dir/clock_enable_param.v.v\n             obj_dir/clock_enable_param.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/196412397/clock_enable_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk <= ~clk; \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/196412397/clock_enable_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/196412397/clock_enable_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("wave.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/196412397/clock_enable_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0);\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module clock_enable_tb();

reg clk = 1'b0;
wire enable0;
wire enable1;
wire enable2;
wire enable3;

always #1 clk <= ~clk; 

  initial
  begin
    #100;
    $finish();
  end
    
  initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
    $display("----------------------------------------------");
    $display(" ");
  end

clock_enable_param test_unit0(
    .clk(clk),
    .enable(enable0)
);

clock_enable_param #(
    .WAIT(2),
    .WIDTH(4)
   ) test_unit1(
    .clk(clk),
    .enable(enable1)
);

clock_enable_param #(
    .WAIT(3),
    .WIDTH(8)
   )test_unit2(
    .clk(clk),
    .enable(enable2)
);

clock_enable_param #(
    .WAIT(9),
    .WIDTH(8)
   )test_unit3(
    .clk(clk),
    .enable(enable3)
);



endmodule
module clock_enable_tb();


reg clk = 1'b0;
wire enable0;
wire enable1;
wire enable2;
wire enable3;

always #1 clk <= ~clk; 

  initial
  begin
    #100;
    $finish();
  end
    
  initial 
  begin 
    $display(" ");
    $display("----------------------------------------------");
    $display("          Starting Testbench...");
    $dumpfile("wave.vcd");
    $dumpvars(0);
    $display("----------------------------------------------");
    $display(" ");
  end

clock_enable_param test_unit0(
    .clk(clk),
    .enable(enable0)
);

clock_enable_param #(
    .WAIT(2),
    .WIDTH(4)
   ) test_unit1(
    .clk(clk),
    .enable(enable1)
);

clock_enable_param #(
    .WAIT(3),
    .WIDTH(8)
   )test_unit2(
    .clk(clk),
    .enable(enable2)
);

clock_enable_param #(
    .WAIT(9),
    .WIDTH(8)
   )test_unit3(
    .clk(clk),
    .enable(enable3)
);



endmodule