data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Finete_State_Machines/ece241_2013_q8.v
 line:32: before: "/"
1: b"%Error: data/full_repos/permissive/199632300/HDLBits/Circuits/Sequential_Logic/Finete_State_Machines/ece241_2013_q8.v:85: EOF in '/* ... */' block comment\n%Error: Exiting due to 1 error(s)\n"
module top_module (
        input clk,
        input aresetn,
        input x,
        output reg z
);



        parameter S=0, S1=1, S10=2;
        reg[1:0] state, next;




        always@(posedge clk, negedge aresetn)
                if (<= S;
                else
                        state <= next;






        always@(*) begin
                case (state)
                        S: next = x ? S1 : S;
                        S1: next = x ? S1 : S10;
                        S10: next = x ? S1 : S;
                        default: next = 'x;
                endcase
        end






        always@(*) begin
                case (state)
                        S: z = 0;
                        S1: z = 0;
                        S10: z = x;
                        default: z = 1'bx;
                endcase
        end

endmodule
module top_module (
        input clk,
        input aresetn,
        input x,
        output reg z
);




        parameter S=0, S1=1, S10=2;
        reg[1:0] state, next;




        always@(posedge clk, negedge aresetn)
                if (<= S;
                else
                        state <= next;






        always@(*) begin
                case (state)
                        S: next = x ? S1 : S;
                        S1: next = x ? S1 : S10;
                        S10: next = x ? S1 : S;
                        default: next = 'x;
                endcase
        end






        always@(*) begin
                case (state)
                        S: z = 0;
                        S1: z = 0;
                        S10: z = x;
                        default: z = 1'bx;
                endcase
        end

endmodule