data/full_repos/permissive/163759920/simple_cpu/alu/alu.v
data/verilator_xmls/167fe8b4-e78e-4371-8af5-0dd1d76f100a.xml
module alu(
in1, in2, control, out, zero, neg
);

input wire [31:0] in1;
input wire [31:0] in2;
input wire [3:0] control;
output wire [31:0] out;
output wire zero;
output wire neg;

reg [31:0] acc;
reg reg_zero;
reg reg_neg;

always @*
begin
   if (control == 4'b0000) begin
      acc = in1 + in2;

   end else if (control == 4'b1000) begin
      acc = in1 - in2;

   end else if (control == 4'b1001) begin
      acc = ($signed(in1) - $signed(in2));

   end else if (control == 4'b0001) begin
      acc = in1 << in2[4:0];

   end else if (control == 4'b0010) begin
      acc[0] = ($signed(in1) < $signed(in2));
      acc[31:1] = 31'h0;

   end else if (control == 4'b0011) begin
      acc[0] = (in1 < in2);
      acc[31:1] = 31'h0;

   end else if (control == 4'b0100) begin
      acc = in1 ^ in2;

   end else if (control == 4'b101) begin
      acc = in1 >> in2[4:0];

   end else if (control == 4'b1101) begin
      acc = $signed(in1) >>> in2[4:0];

   end else if (control == 4'b110) begin
      acc = in1 | in2;

   end else if (control == 4'b111) begin
      acc = in1 & in2;

   end else begin
      acc = 32'h0;
   end

   reg_neg = (acc[31] == 1'b1);
   reg_zero = (acc == 32'h0);

end


assign out  = acc;
assign neg  = reg_neg;
assign zero = reg_zero;

endmodule
module alu(
in1, in2, control, out, zero, neg
);


input wire [31:0] in1;
input wire [31:0] in2;
input wire [3:0] control;
output wire [31:0] out;
output wire zero;
output wire neg;

reg [31:0] acc;
reg reg_zero;
reg reg_neg;

always @*
begin
   if (control == 4'b0000) begin
      acc = in1 + in2;

   end else if (control == 4'b1000) begin
      acc = in1 - in2;

   end else if (control == 4'b1001) begin
      acc = ($signed(in1) - $signed(in2));

   end else if (control == 4'b0001) begin
      acc = in1 << in2[4:0];

   end else if (control == 4'b0010) begin
      acc[0] = ($signed(in1) < $signed(in2));
      acc[31:1] = 31'h0;

   end else if (control == 4'b0011) begin
      acc[0] = (in1 < in2);
      acc[31:1] = 31'h0;

   end else if (control == 4'b0100) begin
      acc = in1 ^ in2;

   end else if (control == 4'b101) begin
      acc = in1 >> in2[4:0];

   end else if (control == 4'b1101) begin
      acc = $signed(in1) >>> in2[4:0];

   end else if (control == 4'b110) begin
      acc = in1 | in2;

   end else if (control == 4'b111) begin
      acc = in1 & in2;

   end else begin
      acc = 32'h0;
   end

   reg_neg = (acc[31] == 1'b1);
   reg_zero = (acc == 32'h0);

end


assign out  = acc;
assign neg  = reg_neg;
assign zero = reg_zero;

endmodule