data/full_repos/permissive/105269489/src/verilog/Test benches/tb_memory.v
'utf-8' codec can't decode byte 0xed in position 216: invalid continuation byte
1: b'%Error: Cannot find file containing module: benches,data/full_repos/permissive/105269489\n        ... Looked in:\n             data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489\n             data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489.v\n             data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489.sv\n             benches,data/full_repos/permissive/105269489\n             benches,data/full_repos/permissive/105269489.v\n             benches,data/full_repos/permissive/105269489.sv\n             obj_dir/benches,data/full_repos/permissive/105269489\n             obj_dir/benches,data/full_repos/permissive/105269489.v\n             obj_dir/benches,data/full_repos/permissive/105269489.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/verilog/Test\n%Error: Cannot find file containing module: benches/tb_memory.v\n%Error: Exiting due to 3 error(s)\n'
module tb_memory();	
	
	parameter RAM_WIDTH = `RAM_WIDTH;
    parameter NB_ADDRESS= `NB_ADDRESS;    
	


	
	wire[RAM_WIDTH-1:0] output_data;
	
	reg[NB_ADDRESS-1:0] write_address;
	reg[NB_ADDRESS-1:0] read_address;
	reg	input_CLK;
	reg writeEnable;
	reg [RAM_WIDTH-1:0] input_data;
	
	
	
	
	initial	begin
		write_address =10'd0;
		read_address  =10'd0;
		writeEnable   =1'b0;
		input_data    =8'h0;				

		input_CLK= 1'b0;			
		#10 writeEnable=1'b1;
		#10 writeEnable = 1'b0;
		
		
		
		#50 input_data=8'hFF;
		#50 write_address = write_address + 1;
		#50 read_address = read_address + 1;
		#20 writeEnable = 1'b1;
		#20 writeEnable = 1'b0;
		
		
        #50 input_data=8'b10000001;
        #50 write_address = write_address + 1;
        #50 read_address = read_address + 1;
        #20 writeEnable = 1'b1;
        #20 writeEnable = 1'b0;
        

        #50 input_data=8'b11100111;
        #20 writeEnable = 1'b1;
        #20 writeEnable = 1'b0;
        
		
		     
        
                
		
		#10000000000 $finish;
	end
	
	always #2.5 input_CLK=~input_CLK;
	


memory
	#(  
	    .NB_ADDRESS(NB_ADDRESS),
		.RAM_WIDTH (RAM_WIDTH)
		)
	u_bram
		(
		.i_data(input_data),
		.i_writeAdd(write_address),
		.i_readAdd(read_address),
		.i_CLK(input_CLK),
		.i_wrEnable(writeEnable),
		.o_data(output_data)
		);
endmodule
module tb_memory();
	
	
	parameter RAM_WIDTH = `RAM_WIDTH;
    parameter NB_ADDRESS= `NB_ADDRESS;    
	


	
	wire[RAM_WIDTH-1:0] output_data;
	
	reg[NB_ADDRESS-1:0] write_address;
	reg[NB_ADDRESS-1:0] read_address;
	reg	input_CLK;
	reg writeEnable;
	reg [RAM_WIDTH-1:0] input_data;
	
	
	
	
	initial	begin
		write_address =10'd0;
		read_address  =10'd0;
		writeEnable   =1'b0;
		input_data    =8'h0;				

		input_CLK= 1'b0;			
		#10 writeEnable=1'b1;
		#10 writeEnable = 1'b0;
		
		
		
		#50 input_data=8'hFF;
		#50 write_address = write_address + 1;
		#50 read_address = read_address + 1;
		#20 writeEnable = 1'b1;
		#20 writeEnable = 1'b0;
		
		
        #50 input_data=8'b10000001;
        #50 write_address = write_address + 1;
        #50 read_address = read_address + 1;
        #20 writeEnable = 1'b1;
        #20 writeEnable = 1'b0;
        

        #50 input_data=8'b11100111;
        #20 writeEnable = 1'b1;
        #20 writeEnable = 1'b0;
        
		
		     
        
                
		
		#10000000000 $finish;
	end
	
	always #2.5 input_CLK=~input_CLK;
	


memory
	#(  
	    .NB_ADDRESS(NB_ADDRESS),
		.RAM_WIDTH (RAM_WIDTH)
		)
	u_bram
		(
		.i_data(input_data),
		.i_writeAdd(write_address),
		.i_readAdd(read_address),
		.i_CLK(input_CLK),
		.i_wrEnable(writeEnable),
		.o_data(output_data)
		);
endmodule