data/full_repos/permissive/162646941/src/reg16_ex1.v
data/verilator_xmls/a005524b-73fa-4543-bc51-66d0ad299d5b.xml
module reg16_ex1(clk,d,q);

  input clk;
  input [15:0] d;
  output reg [15:0] q;

  always @ (posedge clk)
  begin
    q <= d;
  end

endmodule
module reg16_ex1(clk,d,q);


  input clk;
  input [15:0] d;
  output reg [15:0] q;

  always @ (posedge clk)
  begin
    q <= d;
  end

endmodule