data/full_repos/permissive/205229557/new/lab5/no_CL/aocl_mat/device/mat_cl/mat_cl_system.v
None: at end of input
data/verilator_xmls/cc731fbe-e801-4c00-a0ac-448264019dc1.xml
module mat_cl_system
(
   input logic clock,
   input logic clock2x,
   input logic resetn
);
endmodule
module mat_cl_system
(
   input logic clock,
   input logic clock2x,
   input logic resetn
);

endmodule