data/full_repos/permissive/174369527/mem/rom_tb.v
 line:44: before: "$"
1: b'%Error: data/full_repos/permissive/174369527/mem/rom_tb.v:44: Unsupported or unknown PLI call: $monitor\n   #10 $monitor ("address = %h, data = %h, read_en = %b, ce = %b", address, data, read_en, ce);\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174369527/mem/rom_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n   #10 $monitor ("address = %h, data = %h, read_en = %b, ce = %b", address, data, read_en, ce);\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174369527/mem/rom_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n     #5 address = i;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/174369527/mem/rom_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n     #5 read_en = 0;\n     ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rom (
address ,
data    ,
read_en ,
ce
);
input [7:0] address;
output [7:0] data;
input        read_en;
input        ce;
   
  
reg [7:0]    mem [0:255] ;
integer file_pointer;

assign data = (ce && read_en) ? mem[address] : 8'b0;

integer i;

initial begin
  $readmemb("memory.list",mem);
end


endmodule
module rom (
address ,
data    ,
read_en ,
ce
);

input [7:0] address;
output [7:0] data;
input        read_en;
input        ce;
   
  
reg [7:0]    mem [0:255] ;
integer file_pointer;

assign data = (ce && read_en) ? mem[address] : 8'b0;

integer i;

initial begin
  $readmemb("memory.list",mem);
end


endmodule