data/full_repos/permissive/174642777/Experiments/Lab X4/Lab 12 SHREG_4bit/SHREG_4bit.v
 line:24 column:24: Illegal character "'"
1: b'%Error: Cannot find file containing module: X4/Lab\n        ... Looked in:\n             data/full_repos/permissive/174642777/Experiments/Lab/X4/Lab\n             data/full_repos/permissive/174642777/Experiments/Lab/X4/Lab.v\n             data/full_repos/permissive/174642777/Experiments/Lab/X4/Lab.sv\n             X4/Lab\n             X4/Lab.v\n             X4/Lab.sv\n             obj_dir/X4/Lab\n             obj_dir/X4/Lab.v\n             obj_dir/X4/Lab.sv\n%Error: Cannot find file containing module: 12\n%Error: Cannot find file containing module: SHREG_4bit,data/full_repos/permissive/174642777\n%Error: Cannot find file containing module: data/full_repos/permissive/174642777/Experiments/Lab\n%Error: Cannot find file containing module: SHREG_4bit/SHREG_4bit.v\n%Error: Exiting due to 5 error(s)\n'
module SHREG_4bit( input wire CLK, CLR, D,
                   output wire[3:0] Q );

  DFF dff3(CLK, CLR, 1'b 1, D, Q[3]);
  DFF dff2(CLK, CLR, 1'b 1, Q[3], Q[2]);
  DFF dff1(CLK, CLR, 1'b 1, Q[2], Q[1]);
  DFF dff0(CLK, CLR, 1'b 1, Q[1], Q[0]);

endmodule
module SHREG_4bit( input wire CLK, CLR, D,
                   output wire[3:0] Q );


  DFF dff3(CLK, CLR, 1'b 1, D, Q[3]);
  DFF dff2(CLK, CLR, 1'b 1, Q[3], Q[2]);
  DFF dff1(CLK, CLR, 1'b 1, Q[2], Q[1]);
  DFF dff0(CLK, CLR, 1'b 1, Q[1], Q[0]);

endmodule