data/full_repos/permissive/189158922/verilog_src/merge.v
 line:49: before: "*"
1: b'%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/merge.v:50: Operator SHIFTL expects 62 bits on the LHS, but LHS\'s VARREF \'enc_in1\' generates 31 bits.\n                                                                           : ... In instance top.__0249\n  assign \\$3  = enc_in1 <<< (* src = "merge.py:75" *) enc_in_ctr2;\n                        ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189158922/verilog_src/merge.v:51: Operator OR expects 62 bits on the RHS, but RHS\'s VARREF \'enc_in2\' generates 31 bits.\n                                                                           : ... In instance top.__0249\n  assign \\$5  = \\$3  | (* src = "merge.py:75" *) enc_in2;\n                     ^\n%Error: Exiting due to 2 warning(s)\n'
module anonymous(enc_in_ctr1, enc_in_ctr2, enc_in1, enc_in2, end_in, rst, clk, enc_out_ctr, enc_out, valid_out, end_out, valid_in);
  wire [5:0] \$1 ;
  wire [61:0] \$3 ;
  wire [61:0] \$5 ;
  (* src = "merge.py:49" *)
  reg [61:0] \$next\enc_out ;
  (* src = "merge.py:50" *)
  reg [5:0] \$next\enc_out_ctr ;
  (* src = "merge.py:58" *)
  reg \$next\end_out ;
  (* src = "merge.py:54" *)
  reg \$next\valid_out ;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* src = "merge.py:43" *)
  input [30:0] enc_in1;
  (* src = "merge.py:46" *)
  input [30:0] enc_in2;
  (* src = "merge.py:44" *)
  input [4:0] enc_in_ctr1;
  (* src = "merge.py:47" *)
  input [4:0] enc_in_ctr2;
  (* init = 62'h0000000000000000 *)
  (* src = "merge.py:49" *)
  output [61:0] enc_out;
  reg [61:0] enc_out = 62'h0000000000000000;
  (* init = 6'h00 *)
  (* src = "merge.py:50" *)
  output [5:0] enc_out_ctr;
  reg [5:0] enc_out_ctr = 6'h00;
  (* src = "merge.py:57" *)
  input end_in;
  (* init = 1'h0 *)
  (* src = "merge.py:58" *)
  output end_out;
  reg end_out = 1'h0;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "merge.py:53" *)
  input valid_in;
  (* init = 1'h0 *)
  (* src = "merge.py:54" *)
  output valid_out;
  reg valid_out = 1'h0;
  assign \$1  = enc_in_ctr1 + (* src = "merge.py:74" *) enc_in_ctr2;
  assign \$3  = enc_in1 <<< (* src = "merge.py:75" *) enc_in_ctr2;
  assign \$5  = \$3  | (* src = "merge.py:75" *) enc_in2;
  always @(posedge clk)
      end_out <= \$next\end_out ;
  always @(posedge clk)
      valid_out <= \$next\valid_out ;
  always @(posedge clk)
      enc_out <= \$next\enc_out ;
  always @(posedge clk)
      enc_out_ctr <= \$next\enc_out_ctr ;
  always @* begin
    \$next\enc_out_ctr  = enc_out_ctr;
    casez (valid_in)
      1'h1:
          \$next\enc_out_ctr  = \$1 ;
    endcase
    casez (rst)
      1'h1:
          \$next\enc_out_ctr  = 6'h00;
    endcase
  end
  always @* begin
    \$next\enc_out  = enc_out;
    casez (valid_in)
      1'h1:
          \$next\enc_out  = \$5 ;
    endcase
    casez (rst)
      1'h1:
          \$next\enc_out  = 62'h0000000000000000;
    endcase
  end
  always @* begin
    \$next\valid_out  = valid_out;
    \$next\valid_out  = valid_in;
    casez (rst)
      1'h1:
          \$next\valid_out  = 1'h0;
    endcase
  end
  always @* begin
    \$next\end_out  = end_out;
    \$next\end_out  = end_in;
    casez (rst)
      1'h1:
          \$next\end_out  = 1'h0;
    endcase
  end
endmodule
module anonymous(enc_in_ctr1, enc_in_ctr2, enc_in1, enc_in2, end_in, rst, clk, enc_out_ctr, enc_out, valid_out, end_out, valid_in);

  wire [5:0] \$1 ;
  wire [61:0] \$3 ;
  wire [61:0] \$5 ;
  (* src = "merge.py:49" *)
  reg [61:0] \$next\enc_out ;
  (* src = "merge.py:50" *)
  reg [5:0] \$next\enc_out_ctr ;
  (* src = "merge.py:58" *)
  reg \$next\end_out ;
  (* src = "merge.py:54" *)
  reg \$next\valid_out ;
  (* src = "nmigen/hdl/ir.py:329" *)
  input clk;
  (* src = "merge.py:43" *)
  input [30:0] enc_in1;
  (* src = "merge.py:46" *)
  input [30:0] enc_in2;
  (* src = "merge.py:44" *)
  input [4:0] enc_in_ctr1;
  (* src = "merge.py:47" *)
  input [4:0] enc_in_ctr2;
  (* init = 62'h0000000000000000 *)
  (* src = "merge.py:49" *)
  output [61:0] enc_out;
  reg [61:0] enc_out = 62'h0000000000000000;
  (* init = 6'h00 *)
  (* src = "merge.py:50" *)
  output [5:0] enc_out_ctr;
  reg [5:0] enc_out_ctr = 6'h00;
  (* src = "merge.py:57" *)
  input end_in;
  (* init = 1'h0 *)
  (* src = "merge.py:58" *)
  output end_out;
  reg end_out = 1'h0;
  (* src = "nmigen/hdl/ir.py:329" *)
  input rst;
  (* src = "merge.py:53" *)
  input valid_in;
  (* init = 1'h0 *)
  (* src = "merge.py:54" *)
  output valid_out;
  reg valid_out = 1'h0;
  assign \$1  = enc_in_ctr1 + (* src = "merge.py:74" *) enc_in_ctr2;
  assign \$3  = enc_in1 <<< (* src = "merge.py:75" *) enc_in_ctr2;
  assign \$5  = \$3  | (* src = "merge.py:75" *) enc_in2;
  always @(posedge clk)
      end_out <= \$next\end_out ;
  always @(posedge clk)
      valid_out <= \$next\valid_out ;
  always @(posedge clk)
      enc_out <= \$next\enc_out ;
  always @(posedge clk)
      enc_out_ctr <= \$next\enc_out_ctr ;
  always @* begin
    \$next\enc_out_ctr  = enc_out_ctr;
    casez (valid_in)
      1'h1:
          \$next\enc_out_ctr  = \$1 ;
    endcase
    casez (rst)
      1'h1:
          \$next\enc_out_ctr  = 6'h00;
    endcase
  end
  always @* begin
    \$next\enc_out  = enc_out;
    casez (valid_in)
      1'h1:
          \$next\enc_out  = \$5 ;
    endcase
    casez (rst)
      1'h1:
          \$next\enc_out  = 62'h0000000000000000;
    endcase
  end
  always @* begin
    \$next\valid_out  = valid_out;
    \$next\valid_out  = valid_in;
    casez (rst)
      1'h1:
          \$next\valid_out  = 1'h0;
    endcase
  end
  always @* begin
    \$next\end_out  = end_out;
    \$next\end_out  = end_in;
    casez (rst)
      1'h1:
          \$next\end_out  = 1'h0;
    endcase
  end
endmodule