data/full_repos/permissive/160437780/Source/sevensegment.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:33: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                             : ... In instance sevensegment\n     sseg = inBits[3:0];\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:39: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                             : ... In instance sevensegment\n     sseg = inBits[7:4];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:45: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                             : ... In instance sevensegment\n     sseg = inBits[11:8];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:51: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                             : ... In instance sevensegment\n     sseg = inBits[15:12];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h5\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h6\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h7\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'ha\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'hb\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'hd\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'he\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/160437780/Source/sevensegment.v:63: Operator CASE expects 7 bits on the Case Item, but Case Item\'s CONST \'4\'hf\' generates 4 bits.\n                                                                             : ... In instance sevensegment\n  case(sseg)\n  ^~~~\n%Error: Exiting due to 20 warning(s)\n'
module sevensegment(
 input CLK100MHZ, reset,
 input [15:0] inBits,
 output a, b, c, d, e, f, g, dp,
 output [3:0] an
 );
 
localparam N = 18;
 
reg [N-1:0]count;
 
always @ (posedge CLK100MHZ or posedge reset)
 begin
  if (reset)
   count <= 0;
  else
   count <= count + 1;
 end
 
reg [6:0]sseg;
reg [3:0]an_temp;
 
always @ (*)
 begin
  case(count[N-1:N-2])
    
   2'b00 :
    begin
     sseg = inBits[3:0];
     an_temp = 4'b1110;
    end
    
   2'b01:
    begin
     sseg = inBits[7:4];
     an_temp = 4'b1101;
    end
    
   2'b10:
    begin
     sseg = inBits[11:8];
     an_temp = 4'b1011;
    end
     
   2'b11:
    begin
     sseg = inBits[15:12];
     an_temp = 4'b0111;
    end
  endcase
 end
assign an = an_temp;
 
 
reg [6:0] sseg_temp;
 
always @ (*)
 begin
  case(sseg)

   4'd0 : sseg_temp = 7'b1000000;
   4'd1 : sseg_temp = 7'b1111001;
   4'd2 : sseg_temp = 7'b0100100;
   4'd3 : sseg_temp = 7'b0110000;
   4'd4 : sseg_temp = 7'b0011001;
   4'd5 : sseg_temp = 7'b0010010;
   4'd6 : sseg_temp = 7'b0000010;
   4'd7 : sseg_temp = 7'b1111000;
   4'd8 : sseg_temp = 7'b0000000;
   4'd9 : sseg_temp = 7'b0010000;
   4'd10 : sseg_temp = 7'b0001000;
   4'd11 : sseg_temp = 7'b0000011;
   4'd12 : sseg_temp = 7'b1000110;
   4'd13 : sseg_temp = 7'b0100001;
   4'd14 : sseg_temp = 7'b0000110;
   4'd15 : sseg_temp = 7'b0001110;
   default : sseg_temp = 7'b0111111;
  endcase
 end
assign {g, f, e, d, c, b, a} = sseg_temp;

 
assign dp = 1'b1;
 
 
endmodule
module sevensegment(
 input CLK100MHZ, reset,
 input [15:0] inBits,
 output a, b, c, d, e, f, g, dp,
 output [3:0] an
 );

 
localparam N = 18;
 
reg [N-1:0]count;
 
always @ (posedge CLK100MHZ or posedge reset)
 begin
  if (reset)
   count <= 0;
  else
   count <= count + 1;
 end
 
reg [6:0]sseg;
reg [3:0]an_temp;
 
always @ (*)
 begin
  case(count[N-1:N-2])
    
   2'b00 :
    begin
     sseg = inBits[3:0];
     an_temp = 4'b1110;
    end
    
   2'b01:
    begin
     sseg = inBits[7:4];
     an_temp = 4'b1101;
    end
    
   2'b10:
    begin
     sseg = inBits[11:8];
     an_temp = 4'b1011;
    end
     
   2'b11:
    begin
     sseg = inBits[15:12];
     an_temp = 4'b0111;
    end
  endcase
 end
assign an = an_temp;
 
 
reg [6:0] sseg_temp;
 
always @ (*)
 begin
  case(sseg)

   4'd0 : sseg_temp = 7'b1000000;
   4'd1 : sseg_temp = 7'b1111001;
   4'd2 : sseg_temp = 7'b0100100;
   4'd3 : sseg_temp = 7'b0110000;
   4'd4 : sseg_temp = 7'b0011001;
   4'd5 : sseg_temp = 7'b0010010;
   4'd6 : sseg_temp = 7'b0000010;
   4'd7 : sseg_temp = 7'b1111000;
   4'd8 : sseg_temp = 7'b0000000;
   4'd9 : sseg_temp = 7'b0010000;
   4'd10 : sseg_temp = 7'b0001000;
   4'd11 : sseg_temp = 7'b0000011;
   4'd12 : sseg_temp = 7'b1000110;
   4'd13 : sseg_temp = 7'b0100001;
   4'd14 : sseg_temp = 7'b0000110;
   4'd15 : sseg_temp = 7'b0001110;
   default : sseg_temp = 7'b0111111;
  endcase
 end
assign {g, f, e, d, c, b, a} = sseg_temp;

 
assign dp = 1'b1;
 
 
endmodule