data/full_repos/permissive/210844779/lab5/5.3/tb.v
1: b'%Error: data/full_repos/permissive/210844779/lab5/5.3/tb.v:7: Unsupported: SystemVerilog 2005 reserved word not implemented: \'sequence\'\nsequence u0(ip,rst,load,en,clk,y);\n^~~~~~~~\n%Error: data/full_repos/permissive/210844779/lab5/5.3/tb.v:7: syntax error, unexpected \'(\', expecting IDENTIFIER\nsequence u0(ip,rst,load,en,clk,y);\n            ^~\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.3/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.3/tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.3/tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.3/tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.3/tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.3/tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.3/tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.3/tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab5/5.3/tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Error: data/full_repos/permissive/210844779/lab5/5.3/tb.v:46: Unsupported or unknown PLI call: $monitor\n$monitor("counter value %b",y); \n^~~~~~~~\n%Error: Exiting due to 3 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  
  reg [3:0]ip;
  reg load,rst,en,clk;
  wire [3:0]y;
    
sequence u0(ip,rst,load,en,clk,y);


always

begin

clk=1;

#5

clk=0;

#5;

end

initial

begin

rst=1;
#20
rst=0;en=1;
#100
load=1;ip=4'b1100;
#20
load=0;
#100
rst=1;
#20
rst=0;en=0;
#20
en=1;
#100;

end

initial
$monitor("counter value %b",y); 

endmodule
module tb();

  
  reg [3:0]ip;
  reg load,rst,en,clk;
  wire [3:0]y;
    
sequence u0(ip,rst,load,en,clk,y);


always

begin

clk=1;

#5

clk=0;

#5;

end

initial

begin

rst=1;
#20
rst=0;en=1;
#100
load=1;ip=4'b1100;
#20
load=0;
#100
rst=1;
#20
rst=0;en=0;
#20
en=1;
#100;

end

initial
$monitor("counter value %b",y); 

endmodule