data/full_repos/permissive/171756809/clock_prescaler.v
data/verilator_xmls/b8552543-ec21-4944-867a-c85646577569.xml
module clock_prescaler(input wire clkin, output wire [WIDTH-1:0] clkout, input wire reset);
	parameter WIDTH=8;

	reg [WIDTH-2:0] prescaler = 0;

	always @(negedge clkin) begin
		if(reset) begin
			prescaler <= 0;
		end else begin
			prescaler <= prescaler + 1;
		end
	end

	assign clkout = { prescaler, clkin };
endmodule
module clock_prescaler(input wire clkin, output wire [WIDTH-1:0] clkout, input wire reset);

	parameter WIDTH=8;

	reg [WIDTH-2:0] prescaler = 0;

	always @(negedge clkin) begin
		if(reset) begin
			prescaler <= 0;
		end else begin
			prescaler <= prescaler + 1;
		end
	end

	assign clkout = { prescaler, clkin };
endmodule