data/full_repos/permissive/207111076/cps_video_beam.v
data/verilator_xmls/2da42811-7dd3-4dfb-ad70-24d17871cacf.xml
module cps_video_beam
(
    input         bus_rst,
    input         bus_clk,
    
    input         ram_ref,
    input   [3:0] ram_cyc,
    input   [3:0] ram_acc,
    input   [8:0] ram_slot,
    input         slot_rst,
    
    output        bus_eof,
    output  [6:0] bus_vbl,
    output  [8:0] bus_vpos,
    output        bus_dma_ena,
    output        bus_frd_ena,
    
    input         vid_rst,
    input         vid_clk,
    output  [2:0] vid_clk_ena,
    
    output        vid_eol,
    output        vid_eof,
    output [10:0] vid_hpos,
    output [10:0] vid_vpos,
    output        vid_hsync,
    output        vid_vsync,
    output        vid_dena
);




    
    reg [8:0] r_bus_vpos;
    reg [6:0] r_bus_vbl;
    reg       r_bus_frd;
    
    always@(posedge bus_rst or posedge bus_clk) begin : BUS_VPOS
    
        if (bus_rst) begin
            r_bus_vpos <= 9'd256;
            r_bus_vbl  <= 7'b0000001;
            r_bus_frd  <= 1'b0;
        end
        else begin

            if (slot_rst) begin
                r_bus_vpos <= (r_bus_vbl[6]) ? 9'd0 : r_bus_vpos + 9'd1;
            end

            if (slot_rst) begin
                r_bus_vbl  <= { r_bus_vbl[5:0], &r_bus_vpos[7:0] };
            end

            if (ram_acc[3] & ram_cyc[3]) begin
                if (ram_slot == 9'h1FF)
                    r_bus_frd <= ~r_bus_vpos[8];
                else if (ram_slot == 9'h0BF)
                    r_bus_frd <= 1'b0;
            end
        end
    end
    
    assign bus_eof       = r_bus_vbl[6] & slot_rst;
    assign bus_vpos      = r_bus_vpos;
    assign bus_vbl       = r_bus_vbl;
    assign bus_dma_ena   = ~r_bus_vpos[8];
    assign bus_frd_ena   = r_bus_frd;





    
    reg [10:0] r_vid_vpos;
    reg [10:0] r_vid_hpos;
    reg        r_vid_eol;
    reg        r_vid_eof;
    reg        r_vid_lock;
    reg  [2:0] r_vid_clk_ena;
    
    always@(posedge vid_rst or posedge vid_clk) begin : VID_HVPOS
        reg [2:0] v_ref_cc;
        reg [2:0] v_eof_cc;
    
        if (vid_rst) begin
            r_vid_vpos    <= 11'd0;
            r_vid_hpos    <= 11'd0;
            r_vid_eol     <= 1'b0;
            r_vid_eof     <= 1'b0;
            r_vid_lock    <= 1'b0;
            r_vid_clk_ena <= 3'b000;
            v_ref_cc      <= 3'b000;
            v_eof_cc      <= 3'b000;
        end
        else begin
            if (r_vid_lock) begin

                if (r_vid_eol) begin
                    r_vid_vpos <= (r_vid_eof) ? 11'd0 : r_vid_vpos + 11'd1;
                end

                r_vid_hpos    <= (r_vid_eol) ? 11'd0 : r_vid_hpos + 11'd1;

                r_vid_clk_ena <= { r_vid_clk_ena[1:0], r_vid_clk_ena[2] };
            end
            else begin
                r_vid_vpos    <= 11'd1024;
                r_vid_hpos    <= 11'd0;
                r_vid_clk_ena <= 3'b001;
            end
            

            if ((v_ref_cc[2:1] == 2'b01) && (v_eof_cc[2:1] == 2'b11)) begin
                r_vid_lock <= 1'b1;
            end
            

            r_vid_eof <= (r_vid_vpos == 11'd1051) ? 1'b1 : 1'b0;

            r_vid_eol <= (r_vid_hpos == 11'd1714) ? 1'b1 : 1'b0;
            

            v_ref_cc <= { v_ref_cc[1:0], ram_ref };
            v_eof_cc <= { v_eof_cc[1:0], r_bus_vbl[4] };
        end
    end
    
    assign vid_eof     = r_vid_eol & r_vid_eof;
    assign vid_eol     = r_vid_eol;
    assign vid_hpos    = r_vid_hpos;
    assign vid_vpos    = r_vid_vpos;
    assign vid_clk_ena = r_vid_clk_ena;
    









    
    reg        r_vid_vsync;
    reg        r_vid_hsync;
    reg        r_vid_dena;
    
    always@(posedge vid_rst or posedge vid_clk) begin : VID_HVSYNC
        reg v_vs_strt;
        reg v_vs_stop;
        reg v_hs_stop;
        reg v_de_strt;
        reg v_de_stop;
        
        if (vid_rst) begin
          r_vid_vsync <= 1'b0;
          r_vid_hsync <= 1'b0;
          r_vid_dena  <= 1'b0;
          v_vs_strt   <= 1'b0;
          v_vs_stop   <= 1'b0;
          v_hs_stop   <= 1'b0;
          v_de_strt   <= 1'b0;
          v_de_stop   <= 1'b0;
        end
        else begin

            if (r_vid_eol) begin
                r_vid_vsync <= (r_vid_vsync & ~v_vs_stop) | v_vs_strt;
            end
            v_vs_strt   <= (r_vid_vpos == 11'd1028) ? 1'b1 : 1'b0;
            v_vs_stop   <= (r_vid_vpos == 11'd1031) ? 1'b1 : 1'b0;

            r_vid_hsync <= (r_vid_hsync & ~v_hs_stop) | r_vid_eol;
            v_hs_stop   <= (r_vid_hpos ==  11'd138) ? 1'b1 : 1'b0;

            r_vid_dena  <= (r_vid_dena & ~v_de_stop)
                         | (v_de_strt & ~r_vid_vpos[10]);
            v_de_strt   <= (r_vid_hpos ==  11'd386) ? 1'b1 : 1'b0;
            v_de_stop   <= (r_vid_hpos == 11'd1666) ? 1'b1 : 1'b0;
        end
    end
    
    assign vid_dena  = r_vid_dena;
    assign vid_hsync = r_vid_hsync;
    assign vid_vsync = r_vid_vsync;

endmodule
module cps_video_beam
(
    input         bus_rst,
    input         bus_clk,
    
    input         ram_ref,
    input   [3:0] ram_cyc,
    input   [3:0] ram_acc,
    input   [8:0] ram_slot,
    input         slot_rst,
    
    output        bus_eof,
    output  [6:0] bus_vbl,
    output  [8:0] bus_vpos,
    output        bus_dma_ena,
    output        bus_frd_ena,
    
    input         vid_rst,
    input         vid_clk,
    output  [2:0] vid_clk_ena,
    
    output        vid_eol,
    output        vid_eof,
    output [10:0] vid_hpos,
    output [10:0] vid_vpos,
    output        vid_hsync,
    output        vid_vsync,
    output        vid_dena
);





    
    reg [8:0] r_bus_vpos;
    reg [6:0] r_bus_vbl;
    reg       r_bus_frd;
    
    always@(posedge bus_rst or posedge bus_clk) begin : BUS_VPOS
    
        if (bus_rst) begin
            r_bus_vpos <= 9'd256;
            r_bus_vbl  <= 7'b0000001;
            r_bus_frd  <= 1'b0;
        end
        else begin

            if (slot_rst) begin
                r_bus_vpos <= (r_bus_vbl[6]) ? 9'd0 : r_bus_vpos + 9'd1;
            end

            if (slot_rst) begin
                r_bus_vbl  <= { r_bus_vbl[5:0], &r_bus_vpos[7:0] };
            end

            if (ram_acc[3] & ram_cyc[3]) begin
                if (ram_slot == 9'h1FF)
                    r_bus_frd <= ~r_bus_vpos[8];
                else if (ram_slot == 9'h0BF)
                    r_bus_frd <= 1'b0;
            end
        end
    end
    
    assign bus_eof       = r_bus_vbl[6] & slot_rst;
    assign bus_vpos      = r_bus_vpos;
    assign bus_vbl       = r_bus_vbl;
    assign bus_dma_ena   = ~r_bus_vpos[8];
    assign bus_frd_ena   = r_bus_frd;





    
    reg [10:0] r_vid_vpos;
    reg [10:0] r_vid_hpos;
    reg        r_vid_eol;
    reg        r_vid_eof;
    reg        r_vid_lock;
    reg  [2:0] r_vid_clk_ena;
    
    always@(posedge vid_rst or posedge vid_clk) begin : VID_HVPOS
        reg [2:0] v_ref_cc;
        reg [2:0] v_eof_cc;
    
        if (vid_rst) begin
            r_vid_vpos    <= 11'd0;
            r_vid_hpos    <= 11'd0;
            r_vid_eol     <= 1'b0;
            r_vid_eof     <= 1'b0;
            r_vid_lock    <= 1'b0;
            r_vid_clk_ena <= 3'b000;
            v_ref_cc      <= 3'b000;
            v_eof_cc      <= 3'b000;
        end
        else begin
            if (r_vid_lock) begin

                if (r_vid_eol) begin
                    r_vid_vpos <= (r_vid_eof) ? 11'd0 : r_vid_vpos + 11'd1;
                end

                r_vid_hpos    <= (r_vid_eol) ? 11'd0 : r_vid_hpos + 11'd1;

                r_vid_clk_ena <= { r_vid_clk_ena[1:0], r_vid_clk_ena[2] };
            end
            else begin
                r_vid_vpos    <= 11'd1024;
                r_vid_hpos    <= 11'd0;
                r_vid_clk_ena <= 3'b001;
            end
            

            if ((v_ref_cc[2:1] == 2'b01) && (v_eof_cc[2:1] == 2'b11)) begin
                r_vid_lock <= 1'b1;
            end
            

            r_vid_eof <= (r_vid_vpos == 11'd1051) ? 1'b1 : 1'b0;

            r_vid_eol <= (r_vid_hpos == 11'd1714) ? 1'b1 : 1'b0;
            

            v_ref_cc <= { v_ref_cc[1:0], ram_ref };
            v_eof_cc <= { v_eof_cc[1:0], r_bus_vbl[4] };
        end
    end
    
    assign vid_eof     = r_vid_eol & r_vid_eof;
    assign vid_eol     = r_vid_eol;
    assign vid_hpos    = r_vid_hpos;
    assign vid_vpos    = r_vid_vpos;
    assign vid_clk_ena = r_vid_clk_ena;
    









    
    reg        r_vid_vsync;
    reg        r_vid_hsync;
    reg        r_vid_dena;
    
    always@(posedge vid_rst or posedge vid_clk) begin : VID_HVSYNC
        reg v_vs_strt;
        reg v_vs_stop;
        reg v_hs_stop;
        reg v_de_strt;
        reg v_de_stop;
        
        if (vid_rst) begin
          r_vid_vsync <= 1'b0;
          r_vid_hsync <= 1'b0;
          r_vid_dena  <= 1'b0;
          v_vs_strt   <= 1'b0;
          v_vs_stop   <= 1'b0;
          v_hs_stop   <= 1'b0;
          v_de_strt   <= 1'b0;
          v_de_stop   <= 1'b0;
        end
        else begin

            if (r_vid_eol) begin
                r_vid_vsync <= (r_vid_vsync & ~v_vs_stop) | v_vs_strt;
            end
            v_vs_strt   <= (r_vid_vpos == 11'd1028) ? 1'b1 : 1'b0;
            v_vs_stop   <= (r_vid_vpos == 11'd1031) ? 1'b1 : 1'b0;

            r_vid_hsync <= (r_vid_hsync & ~v_hs_stop) | r_vid_eol;
            v_hs_stop   <= (r_vid_hpos ==  11'd138) ? 1'b1 : 1'b0;

            r_vid_dena  <= (r_vid_dena & ~v_de_stop)
                         | (v_de_strt & ~r_vid_vpos[10]);
            v_de_strt   <= (r_vid_hpos ==  11'd386) ? 1'b1 : 1'b0;
            v_de_stop   <= (r_vid_hpos == 11'd1666) ? 1'b1 : 1'b0;
        end
    end
    
    assign vid_dena  = r_vid_dena;
    assign vid_hsync = r_vid_hsync;
    assign vid_vsync = r_vid_vsync;

endmodule