data/full_repos/permissive/110151336/lab_05/src/07_alu_structural/common/slt.v
data/verilator_xmls/5ddcec64-d869-4b44-a2e9-07e039b2c39f.xml
module slt
#( 
    parameter WIDTH = 8
)
(
    input  [WIDTH - 1:0] x,y,
    output [WIDTH - 1:0] z
);
    assign z = (x < y) ? 1 : 0;
endmodule
module slt
#( 
    parameter WIDTH = 8
)
(
    input  [WIDTH - 1:0] x,y,
    output [WIDTH - 1:0] z
);

    assign z = (x < y) ? 1 : 0;
endmodule