data/full_repos/permissive/112861986/src/testbench/3_tb.v
 line:75: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #(c_BIT_PERIOD);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #1000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n          #(c_BIT_PERIOD);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n      #(c_BIT_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;\n  ^\n%Error: data/full_repos/permissive/112861986/src/testbench/3_tb.v:74: syntax error, unexpected \'@\'\n      @(posedge r_Clock);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n#10000;\n^\n%Error: data/full_repos/permissive/112861986/src/testbench/3_tb.v:77: syntax error, unexpected \'@\'\n      @(posedge r_Clock);\n      ^\n%Error: data/full_repos/permissive/112861986/src/testbench/3_tb.v:84: syntax error, unexpected \'@\'\n      @(posedge r_Clock);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n#10000;\n^\n%Error: data/full_repos/permissive/112861986/src/testbench/3_tb.v:87: syntax error, unexpected \'@\'\n      @(posedge r_Clock);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/112861986/src/testbench/3_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n#10000;\n^\n%Error: data/full_repos/permissive/112861986/src/testbench/3_tb.v:95: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/112861986/src/testbench/3_tb.v:96: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0);\n    ^~~~~~~~~\n%Error: Exiting due to 6 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UART_RX_TB();




  parameter c_CLOCK_PERIOD_NS = 40;
  parameter c_CLKS_PER_BIT    = 217;
  parameter c_BIT_PERIOD      = 8600;
  
  reg r_Clock = 0;
  reg r_RX_Serial = 1;
  wire w_TX_Serial;
  reg rdv = 0;
  wire wdv;
  wire [7:0] w_RX_Byte;
  reg [7:0] w_TX_Byte = 8'h44;

assign wdv = rdv;


  task UART_WRITE_BYTE;
    input [7:0] i_Data;
    integer     ii;
    begin
      

      r_RX_Serial <= 1'b0;
      #(c_BIT_PERIOD);
      #1000;
      

      for (ii=0; ii<8; ii=ii+1)
        begin
          r_RX_Serial <= i_Data[ii];
          #(c_BIT_PERIOD);
        end
      

      r_RX_Serial <= 1'b1;
      #(c_BIT_PERIOD);
     end
  endtask

  uart_rx #(.clks_per_bit(c_CLKS_PER_BIT)) UART_RX_INST
    (.i_clock(r_Clock),
     .i_rx_uart(r_RX_Serial),
     .o_rx_dv(wdv),
     .o_rx_byte(w_RX_Byte)
     );

  uart_tx #(.clks_per_bit(c_CLKS_PER_BIT)) UART_TX_INST
    (.i_clock(r_Clock),
     .o_tx_uart(w_TX_Serial),
     .i_dv(wdv),
     .i_tx_byte(w_TX_Byte)
     );

always
  #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;

  

  initial
    begin

      @(posedge r_Clock);
      UART_WRITE_BYTE(8'h14);
#10000;
      @(posedge r_Clock);
            

      if (w_RX_Byte == 8'h14)
        $display("Test Passed - Correct Byte Received");
      else
        $display("Test Failed - Incorrect Byte Received");
      @(posedge r_Clock);
#10000;
      $display(w_TX_Byte);
      @(posedge r_Clock);
#10000;
    $finish();
    end
  
  initial 
  begin

    $dumpfile("dump.vcd");
    $dumpvars(0);
  end
  
endmodule
module UART_RX_TB();





  parameter c_CLOCK_PERIOD_NS = 40;
  parameter c_CLKS_PER_BIT    = 217;
  parameter c_BIT_PERIOD      = 8600;
  
  reg r_Clock = 0;
  reg r_RX_Serial = 1;
  wire w_TX_Serial;
  reg rdv = 0;
  wire wdv;
  wire [7:0] w_RX_Byte;
  reg [7:0] w_TX_Byte = 8'h44;

assign wdv = rdv;


  task UART_WRITE_BYTE;
    input [7:0] i_Data;
    integer     ii;
    begin
      

      r_RX_Serial <= 1'b0;
      #(c_BIT_PERIOD);
      #1000;
      

      for (ii=0; ii<8; ii=ii+1)
        begin
          r_RX_Serial <= i_Data[ii];
          #(c_BIT_PERIOD);
        end
      

      r_RX_Serial <= 1'b1;
      #(c_BIT_PERIOD);
     end
  endtask

  uart_rx #(.clks_per_bit(c_CLKS_PER_BIT)) UART_RX_INST
    (.i_clock(r_Clock),
     .i_rx_uart(r_RX_Serial),
     .o_rx_dv(wdv),
     .o_rx_byte(w_RX_Byte)
     );

  uart_tx #(.clks_per_bit(c_CLKS_PER_BIT)) UART_TX_INST
    (.i_clock(r_Clock),
     .o_tx_uart(w_TX_Serial),
     .i_dv(wdv),
     .i_tx_byte(w_TX_Byte)
     );

always
  #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;

  

  initial
    begin

      @(posedge r_Clock);
      UART_WRITE_BYTE(8'h14);
#10000;
      @(posedge r_Clock);
            

      if (w_RX_Byte == 8'h14)
        $display("Test Passed - Correct Byte Received");
      else
        $display("Test Failed - Incorrect Byte Received");
      @(posedge r_Clock);
#10000;
      $display(w_TX_Byte);
      @(posedge r_Clock);
#10000;
    $finish();
    end
  
  initial 
  begin

    $dumpfile("dump.vcd");
    $dumpvars(0);
  end
  
endmodule