data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #2 rst_b_func = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #1 rst_b = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = !clk;   \n       ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:68: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                        : ... In instance IDCTTop_tb\n        temp_mode <= 7\'b0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:77: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s FGETS generates 32 bits.\n                                                                        : ... In instance IDCTTop_tb\n  input_line = $fgets(data_file,file_r);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:78: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                        : ... In instance IDCTTop_tb\n  temp_mode <= data_file[51:48];\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:93: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                        : ... In instance IDCTTop_tb\n   data_input = ~(temp1*10\'d1000 + temp2*7\'d100 + temp3*4\'d10 + temp4) + 1; end\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:94: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                        : ... In instance IDCTTop_tb\n  else data_input = (temp1*10\'d1000 + temp2*7\'d100 + temp3*4\'d10 + temp4); end\n                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:98: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                        : ... In instance IDCTTop_tb\n    data_input = ~(temp1*10\'d1000 + temp2*7\'d100 + temp3*4\'d10 + temp4) + 1; end\n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:99: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                        : ... In instance IDCTTop_tb\n   else data_input = (temp1*10\'d1000 + temp2*7\'d100 + temp3*4\'d10 + temp4); end\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:103: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n    data_input = ~(temp2*7\'d100 + temp3*4\'d10 + temp4) + 1; end\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:104: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n   else data_input = (temp1*10\'d1000 + temp2*7\'d100 + temp3*4\'d10 + temp4); end\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:108: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n    data_input = ~(temp2*7\'d100 + temp3*4\'d10 + temp4) + 1; end\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:109: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n   else data_input = (temp1*10\'d1000 + temp2*7\'d100 + temp3*4\'d10 + temp4); end\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:113: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n    data_input = ~(temp3*4\'d10 + temp4) + 1; end\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:114: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n   else data_input = (temp2*7\'d100 + temp3*4\'d10 + temp4); end\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:118: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n    data_input = ~(temp3*4\'d10 + temp4) + 1; end\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:119: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n   else data_input = (temp2*7\'d100 + temp3*4\'d10 + temp4); end\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:123: Operator NOT expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n    data_input = ~(temp4) + 1; end\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:124: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n   else data_input = (temp3*4\'d10 + temp4); end\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:128: Operator NOT expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n    data_input = ~(temp4) + 1; end\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:129: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n   else data_input = (temp3*4\'d10 + temp4); end\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:132: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n   data_input = temp4; end\n              ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:135: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'temp4\' generates 4 bits.\n                                                                         : ... In instance IDCTTop_tb\n   data_input = temp4; end\n              ^\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:95: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'hb\' generates 4 bits.\n                                                                        : ... In instance IDCTTop_tb\n  else if(temp_mode == 4\'h0b) begin\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:90: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'ha\' generates 4 bits.\n                                                                        : ... In instance IDCTTop_tb\n if(temp_mode == 4\'h0a) begin\n              ^~\n%Error: data/full_repos/permissive/174917352/RTL/IDCTTop_tb.v:145: Cannot find file containing module: \'IDCTTop\'\nIDCTTop IDCTTop1(.clk(clk), \n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174917352/RTL,data/full_repos/permissive/174917352/IDCTTop\n             data/full_repos/permissive/174917352/RTL,data/full_repos/permissive/174917352/IDCTTop.v\n             data/full_repos/permissive/174917352/RTL,data/full_repos/permissive/174917352/IDCTTop.sv\n             IDCTTop\n             IDCTTop.v\n             IDCTTop.sv\n             obj_dir/IDCTTop\n             obj_dir/IDCTTop.v\n             obj_dir/IDCTTop.sv\n%Error: Exiting due to 1 error(s), 26 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module IDCTTop_tb();


wire [7:0]data_out;
wire out_mode;
wire output_start;



reg clk;
reg rst_b;
reg rst_b_func;
reg [15:0]data_input;
reg mode_input;


reg [55:0]data_file;
reg [3:0]temp0;
reg [3:0]temp1;
reg [3:0]temp2;
reg [3:0]temp3;
reg [3:0]temp4;
reg [7:0]temp_mode;


integer file_r;
integer file_w;
reg input_line;


initial 
begin
  clk = 1;
  rst_b = 0;
  rst_b_func = 0;

  file_r = $fopen("../TestFile/file_input_new_1.txt","r");
  file_w = $fopen("../TestFile/file1_myOutput.txt","w");

  if(file_r == 0)
    begin
        $display("Failure to open INPUT File!");
        $stop;
    end
  if(file_w == 0)
    begin
        $display("Failure to open OUTPUT File!");
        $stop;
    end

  #2 rst_b_func = 1;
  #1 rst_b = 1;
  
end

always #1 clk = !clk;

always @(posedge clk)
begin
if(!rst_b)
    begin
        temp_mode <= 7'b0;
        temp0 <= 0;
        temp1 <= 0;
        temp2 <= 0;
        temp3 <= 0;
        temp4 <= 0;
    end
else
    begin
		input_line = $fgets(data_file,file_r);
		temp_mode <= data_file[51:48];
		temp0 <= data_file[43:40];
		temp1 <= data_file[35:32];
		temp2 <= data_file[27:24];
		temp3 <= data_file[19:16];
		temp4 <= data_file[11:8];
    end
end


always @(temp_mode or temp0 or temp1 or temp2 or temp3 or temp4) 
begin
	if(temp_mode == 4'h0a) begin
		mode_input = 0;
		if(temp0 == 4'h0d) begin
			data_input = ~(temp1*10'd1000 + temp2*7'd100 + temp3*4'd10 + temp4) + 1; end
		else data_input = (temp1*10'd1000 + temp2*7'd100 + temp3*4'd10 + temp4); end
		else if(temp_mode == 4'h0b) begin
			mode_input = 1; 
			if(temp0 == 4'h0d) begin
				data_input = ~(temp1*10'd1000 + temp2*7'd100 + temp3*4'd10 + temp4) + 1; end
			else data_input = (temp1*10'd1000 + temp2*7'd100 + temp3*4'd10 + temp4); end
		else if(temp0 == 4'h0a) begin
			mode_input = 0; 
			if(temp1 == 4'h0d) begin
				data_input = ~(temp2*7'd100 + temp3*4'd10 + temp4) + 1; end
			else data_input = (temp1*10'd1000 + temp2*7'd100 + temp3*4'd10 + temp4); end
		else if(temp0 == 4'h0b) begin
			mode_input = 1; 
			if(temp1 == 4'h0d) begin
				data_input = ~(temp2*7'd100 + temp3*4'd10 + temp4) + 1; end
			else data_input = (temp1*10'd1000 + temp2*7'd100 + temp3*4'd10 + temp4); end
		else if(temp1 == 4'h0a) begin
			mode_input = 0; 
			if(temp2 == 4'h0d) begin
				data_input = ~(temp3*4'd10 + temp4) + 1; end
			else data_input = (temp2*7'd100 + temp3*4'd10 + temp4); end
		else if(temp1 == 4'h0b) begin
			mode_input = 1; 
			if(temp2 == 4'h0d) begin
				data_input = ~(temp3*4'd10 + temp4) + 1; end
			else data_input = (temp2*7'd100 + temp3*4'd10 + temp4); end
		else if(temp2 == 4'h0a) begin
			mode_input = 0; 
			if(temp3 == 4'h0d) begin
				data_input = ~(temp4) + 1; end
			else data_input = (temp3*4'd10 + temp4); end
		else if(temp2 == 4'h0b) begin
			mode_input = 1; 
			if(temp3 == 4'h0d) begin
				data_input = ~(temp4) + 1; end
			else data_input = (temp3*4'd10 + temp4); end
		else if(temp3 == 4'h0a) begin
			mode_input = 0; 
			data_input = temp4; end
		else if(temp3 == 4'h0b) begin	
			mode_input = 1;
			data_input = temp4; end
	end

always @(posedge clk)
if(output_start & (out_mode == 0))
    $fdisplay(file_w,"j %d",$signed(data_out));

else if(output_start & out_mode)
    $fdisplay(file_w,"k %d",$signed(data_out));

IDCTTop IDCTTop1(.clk(clk), 
                 .rst_b(rst_b),
                 .data_in(data_input),
                 .mode_flag(mode_input),
                 .data_out(data_out),
                 .out_mode_flag(out_mode),
                 .output_start(output_start));

endmodule
module IDCTTop_tb();



wire [7:0]data_out;
wire out_mode;
wire output_start;



reg clk;
reg rst_b;
reg rst_b_func;
reg [15:0]data_input;
reg mode_input;


reg [55:0]data_file;
reg [3:0]temp0;
reg [3:0]temp1;
reg [3:0]temp2;
reg [3:0]temp3;
reg [3:0]temp4;
reg [7:0]temp_mode;


integer file_r;
integer file_w;
reg input_line;


initial 
begin
  clk = 1;
  rst_b = 0;
  rst_b_func = 0;

  file_r = $fopen("../TestFile/file_input_new_1.txt","r");
  file_w = $fopen("../TestFile/file1_myOutput.txt","w");

  if(file_r == 0)
    begin
        $display("Failure to open INPUT File!");
        $stop;
    end
  if(file_w == 0)
    begin
        $display("Failure to open OUTPUT File!");
        $stop;
    end

  #2 rst_b_func = 1;
  #1 rst_b = 1;
  
end

always #1 clk = !clk;

always @(posedge clk)
begin
if(!rst_b)
    begin
        temp_mode <= 7'b0;
        temp0 <= 0;
        temp1 <= 0;
        temp2 <= 0;
        temp3 <= 0;
        temp4 <= 0;
    end
else
    begin
		input_line = $fgets(data_file,file_r);
		temp_mode <= data_file[51:48];
		temp0 <= data_file[43:40];
		temp1 <= data_file[35:32];
		temp2 <= data_file[27:24];
		temp3 <= data_file[19:16];
		temp4 <= data_file[11:8];
    end
end


always @(temp_mode or temp0 or temp1 or temp2 or temp3 or temp4) 
begin
	if(temp_mode == 4'h0a) begin
		mode_input = 0;
		if(temp0 == 4'h0d) begin
			data_input = ~(temp1*10'd1000 + temp2*7'd100 + temp3*4'd10 + temp4) + 1; end
		else data_input = (temp1*10'd1000 + temp2*7'd100 + temp3*4'd10 + temp4); end
		else if(temp_mode == 4'h0b) begin
			mode_input = 1; 
			if(temp0 == 4'h0d) begin
				data_input = ~(temp1*10'd1000 + temp2*7'd100 + temp3*4'd10 + temp4) + 1; end
			else data_input = (temp1*10'd1000 + temp2*7'd100 + temp3*4'd10 + temp4); end
		else if(temp0 == 4'h0a) begin
			mode_input = 0; 
			if(temp1 == 4'h0d) begin
				data_input = ~(temp2*7'd100 + temp3*4'd10 + temp4) + 1; end
			else data_input = (temp1*10'd1000 + temp2*7'd100 + temp3*4'd10 + temp4); end
		else if(temp0 == 4'h0b) begin
			mode_input = 1; 
			if(temp1 == 4'h0d) begin
				data_input = ~(temp2*7'd100 + temp3*4'd10 + temp4) + 1; end
			else data_input = (temp1*10'd1000 + temp2*7'd100 + temp3*4'd10 + temp4); end
		else if(temp1 == 4'h0a) begin
			mode_input = 0; 
			if(temp2 == 4'h0d) begin
				data_input = ~(temp3*4'd10 + temp4) + 1; end
			else data_input = (temp2*7'd100 + temp3*4'd10 + temp4); end
		else if(temp1 == 4'h0b) begin
			mode_input = 1; 
			if(temp2 == 4'h0d) begin
				data_input = ~(temp3*4'd10 + temp4) + 1; end
			else data_input = (temp2*7'd100 + temp3*4'd10 + temp4); end
		else if(temp2 == 4'h0a) begin
			mode_input = 0; 
			if(temp3 == 4'h0d) begin
				data_input = ~(temp4) + 1; end
			else data_input = (temp3*4'd10 + temp4); end
		else if(temp2 == 4'h0b) begin
			mode_input = 1; 
			if(temp3 == 4'h0d) begin
				data_input = ~(temp4) + 1; end
			else data_input = (temp3*4'd10 + temp4); end
		else if(temp3 == 4'h0a) begin
			mode_input = 0; 
			data_input = temp4; end
		else if(temp3 == 4'h0b) begin	
			mode_input = 1;
			data_input = temp4; end
	end

always @(posedge clk)
if(output_start & (out_mode == 0))
    $fdisplay(file_w,"j %d",$signed(data_out));

else if(output_start & out_mode)
    $fdisplay(file_w,"k %d",$signed(data_out));

IDCTTop IDCTTop1(.clk(clk), 
                 .rst_b(rst_b),
                 .data_in(data_input),
                 .mode_flag(mode_input),
                 .data_out(data_out),
                 .out_mode_flag(out_mode),
                 .output_start(output_start));

endmodule