data/full_repos/permissive/11584509/ICARUS-LX150/serial.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/11584509/ICARUS-LX150/serial.v:92: Multiple top level modules\n                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                               : ... Top module \'serial_receive\'\nmodule serial_receive # (\n       ^~~~~~~~~~~~~~\n                                                                               : ... Top module \'serial_transmit\'\nmodule serial_transmit # (\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/ICARUS-LX150/serial.v:148: Cannot find file containing module: \'uart_transmitter\'\n   uart_transmitter #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) utx (.clk(clk), .uart_tx(TxD), .rx_new_byte(TxD_start), .rx_byte(out_byte), .tx_ready(TxD_ready));\n   ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/11584509/ICARUS-LX150,data/full_repos/permissive/11584509/uart_transmitter\n             data/full_repos/permissive/11584509/ICARUS-LX150,data/full_repos/permissive/11584509/uart_transmitter.v\n             data/full_repos/permissive/11584509/ICARUS-LX150,data/full_repos/permissive/11584509/uart_transmitter.sv\n             uart_transmitter\n             uart_transmitter.v\n             uart_transmitter.sv\n             obj_dir/uart_transmitter\n             obj_dir/uart_transmitter.v\n             obj_dir/uart_transmitter.sv\n%Error: data/full_repos/permissive/11584509/ICARUS-LX150/serial.v:26: Cannot find file containing module: \'uart_receiver\'\n   uart_receiver #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) urx (.clk(clk), .uart_rx(RxD), .tx_new_byte(RxD_data_ready), .tx_byte(RxD_data));\n   ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module serial_receive # (
   parameter baud_rate = 115_200,
   parameter comm_clk_frequency = 100_000_000 )
  ( clk, RxD, data1, data2, data3, target, rx_done );
   input      clk;
   input      RxD;
   
   wire       RxD_data_ready;
   wire [7:0] RxD_data;


   `ifdef CONFIG_SERIAL_TIMEOUT
	parameter SERIAL_TIMEOUT = `CONFIG_SERIAL_TIMEOUT;
   `else


	parameter SERIAL_TIMEOUT = 24'h800000;
   `endif

   uart_receiver #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) urx (.clk(clk), .uart_rx(RxD), .tx_new_byte(RxD_data_ready), .tx_byte(RxD_data));
      
   output [255:0] data1;
   output [255:0] data2;
   output [127:0] data3;
   output [31:0] target;

   output reg rx_done = 1'b0;
   

   
   reg [671:0] input_buffer = 0;
   reg [671:0] input_copy = 0;
   reg [6:0]   demux_state = 7'b0000000;
   reg [23:0]  timer = 0;


`ifdef SIM
   assign target = input_copy[671:640];
   assign data1 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
   assign data2 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
   assign data3 = 128'h0000318f7e71441b141fe951b2b0c7df;
`else   
   assign target = input_copy[671:640];
   assign data3 = input_copy[639:512];
   assign data2 = input_copy[511:256];
   assign data1 = input_copy[255:0];
`endif







   
   always @(posedge clk)
     case (demux_state)
       7'd84:
	 begin
		rx_done <= 1;
	    input_copy <= input_buffer;
	    demux_state <= 0;
	 end
       
       default:
     begin
        rx_done <= 0;
	    if(RxD_data_ready)
	      begin
	         input_buffer <= input_buffer << 8;
             input_buffer[7:0] <= RxD_data;
             demux_state <= demux_state + 1;
	         timer <= 0;
	      end
	      else
	      begin
	         timer <= timer + 1;
	         if (timer == SERIAL_TIMEOUT)
	           demux_state <= 0;
	      end
     end
     endcase
   
endmodule
module serial_receive # (
   parameter baud_rate = 115_200,
   parameter comm_clk_frequency = 100_000_000 )
  ( clk, RxD, data1, data2, data3, target, rx_done );

   input      clk;
   input      RxD;
   
   wire       RxD_data_ready;
   wire [7:0] RxD_data;


   `ifdef CONFIG_SERIAL_TIMEOUT
	parameter SERIAL_TIMEOUT = `CONFIG_SERIAL_TIMEOUT;
   `else


	parameter SERIAL_TIMEOUT = 24'h800000;
   `endif

   uart_receiver #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) urx (.clk(clk), .uart_rx(RxD), .tx_new_byte(RxD_data_ready), .tx_byte(RxD_data));
      
   output [255:0] data1;
   output [255:0] data2;
   output [127:0] data3;
   output [31:0] target;

   output reg rx_done = 1'b0;
   

   
   reg [671:0] input_buffer = 0;
   reg [671:0] input_copy = 0;
   reg [6:0]   demux_state = 7'b0000000;
   reg [23:0]  timer = 0;


`ifdef SIM
   assign target = input_copy[671:640];
   assign data1 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
   assign data2 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
   assign data3 = 128'h0000318f7e71441b141fe951b2b0c7df;
`else   
   assign target = input_copy[671:640];
   assign data3 = input_copy[639:512];
   assign data2 = input_copy[511:256];
   assign data1 = input_copy[255:0];
`endif







   
   always @(posedge clk)
     case (demux_state)
       7'd84:
	 begin
		rx_done <= 1;
	    input_copy <= input_buffer;
	    demux_state <= 0;
	 end
       
       default:
     begin
        rx_done <= 0;
	    if(RxD_data_ready)
	      begin
	         input_buffer <= input_buffer << 8;
             input_buffer[7:0] <= RxD_data;
             demux_state <= demux_state + 1;
	         timer <= 0;
	      end
	      else
	      begin
	         timer <= timer + 1;
	         if (timer == SERIAL_TIMEOUT)
	           demux_state <= 0;
	      end
     end
     endcase
   
endmodule