data/full_repos/permissive/129155059/06-fsm/cmos_cells_delay.v
 line:9: before: ":"
1: b'%Warning-MULTITOP: data/full_repos/permissive/129155059/06-fsm/cmos_cells_delay.v:12: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                    : ... Top module \'BUF_delay\'\nmodule BUF_delay(A, Y);\n       ^~~~~~~~~\n                                                                                    : ... Top module \'NOT_delay\'\nmodule NOT_delay(A, Y);\n       ^~~~~~~~~\n                                                                                    : ... Top module \'NAND_delay\'\nmodule NAND_delay(A, B, Y);\n       ^~~~~~~~~~\n                                                                                    : ... Top module \'NOR_delay\'\nmodule NOR_delay(A, B, Y);\n       ^~~~~~~~~\n                                                                                    : ... Top module \'DFF_delay\'\nmodule DFF_delay(C, D, Q);\n       ^~~~~~~~~\n                                                                                    : ... Top module \'DFFSR_delay\'\nmodule DFFSR_delay(C, D, Q, S, R);\n       ^~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module NAND_delay(A, B, Y);
input A, B;
output Y;




assign #(8:8:9) Y = ~(A & B);
endmodule
module NAND_delay(A, B, Y);

input A, B;
output Y;




assign #(8:8:9) Y = ~(A & B);
endmodule