data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v
 line:186: before: "("
1: b'%Error: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:1: Cannot find include file: fp32_adder.v\n`include "fp32_adder.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/198139336/FPAdder,data/full_repos/permissive/198139336/fp32_adder.v\n             data/full_repos/permissive/198139336/FPAdder,data/full_repos/permissive/198139336/fp32_adder.v.v\n             data/full_repos/permissive/198139336/FPAdder,data/full_repos/permissive/198139336/fp32_adder.v.sv\n             fp32_adder.v\n             fp32_adder.v.v\n             fp32_adder.v.sv\n             obj_dir/fp32_adder.v\n             obj_dir/fp32_adder.v.v\n             obj_dir/fp32_adder.v.sv\n%Error: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:22: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("adder32.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:23: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #0\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #1  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #10 \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #1  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #10 \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #1  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #10 \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #1  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #10 \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #1  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #10 \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #1  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #10 \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #1  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #10 \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #1  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #10 \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #1  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/198139336/FPAdder/testbench_32bits.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #10 \n  ^\n%Error: Exiting due to 3 error(s), 19 warning(s)\n'
module test_bench;


	reg[31:0] testInput_a;
	reg[31:0] testInput_b;
	reg [31:0] correct_ans;
	wire [31:0] adder_ans;



	fpadder test(
		.a(testInput_a),
		.b(testInput_b),
		.sub(1'b0),
		.s(adder_ans));

	reg [4:0] cnt_test, cnt_right;
	initial begin
		$dumpfile("adder32.vcd");
		$dumpvars;

		#0
			cnt_test = 0;
			cnt_right = 0;
		
		#1
			testInput_a = 32'hBA9DBB67;
			testInput_b = 32'h4148F5CB;
			correct_ans = 32'h4148F0DD;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
		
		#1
			testInput_a = 32'h43E20FCC;
			testInput_b = 32'hC1AC8ADB;
			correct_ans = 32'h43D7471E;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
		
		#1
			testInput_a = 32'hC49A522C;
			testInput_b = 32'h442987E6;
			correct_ans = 32'hC40B1C72;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
		
		#1
			testInput_a = 32'hA6AD6DA0;
			testInput_b = 32'h2BADAB89;
			correct_ans = 32'h2BAD802E;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
        #1
			testInput_a = 32'hD6DA0A6A;
			testInput_b = 32'hDAB892BA;
			correct_ans = 32'hDAB96CC4;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
        #1
			testInput_a = 32'h522CC49A;
			testInput_b = 32'h87E64429;
			correct_ans = 32'h522CC49A;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
        #1
			testInput_a = 32'h0FCC43E2;
			testInput_b = 32'hC9DBC1AC;
			correct_ans = 32'hC9DBC1AC;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
        #1
			testInput_a = 32'hBB67BA9D;
			testInput_b = 32'hF5CB4148;
			correct_ans = 32'hF5CB4148;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
		#1
			testInput_a = 32'h3B67BA9D;
			testInput_b = 32'hBB67BA9D;
			correct_ans = 32'h00000000;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end

		$finish;
	end




task success_case;
input [31:0] testInput_a, testInput_b, correct_ans;
begin
	cnt_right = cnt_right + 1;

	$display ("Test %d ", cnt_test);
	$display ("///////////////////////");
	$display ("//// Successful %d ////", cnt_right);
	$display ("///////////////////////");
	$display ("%h + %h = ?", testInput_a, testInput_b);
	$display ("Answer = %h\n", correct_ans);
end endtask





task failure_case;
input [31:0] testInput_a, testInput_b, correct_ans, result;
begin
	$display ("Test %d ", cnt_test);
	$display ("///////////////////////");
	$display ("///////// Fail ////////");
	$display ("///////////////////////");
	$display ("%h + %h = ?", testInput_a, testInput_b);
	$display ("your answer = %h", result);
	$display ("correct answer = %h\n", correct_ans);
end endtask


endmodule
module test_bench;



	reg[31:0] testInput_a;
	reg[31:0] testInput_b;
	reg [31:0] correct_ans;
	wire [31:0] adder_ans;



	fpadder test(
		.a(testInput_a),
		.b(testInput_b),
		.sub(1'b0),
		.s(adder_ans));

	reg [4:0] cnt_test, cnt_right;
	initial begin
		$dumpfile("adder32.vcd");
		$dumpvars;

		#0
			cnt_test = 0;
			cnt_right = 0;
		
		#1
			testInput_a = 32'hBA9DBB67;
			testInput_b = 32'h4148F5CB;
			correct_ans = 32'h4148F0DD;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
		
		#1
			testInput_a = 32'h43E20FCC;
			testInput_b = 32'hC1AC8ADB;
			correct_ans = 32'h43D7471E;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
		
		#1
			testInput_a = 32'hC49A522C;
			testInput_b = 32'h442987E6;
			correct_ans = 32'hC40B1C72;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
		
		#1
			testInput_a = 32'hA6AD6DA0;
			testInput_b = 32'h2BADAB89;
			correct_ans = 32'h2BAD802E;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
        #1
			testInput_a = 32'hD6DA0A6A;
			testInput_b = 32'hDAB892BA;
			correct_ans = 32'hDAB96CC4;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
        #1
			testInput_a = 32'h522CC49A;
			testInput_b = 32'h87E64429;
			correct_ans = 32'h522CC49A;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
        #1
			testInput_a = 32'h0FCC43E2;
			testInput_b = 32'hC9DBC1AC;
			correct_ans = 32'hC9DBC1AC;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
        #1
			testInput_a = 32'hBB67BA9D;
			testInput_b = 32'hF5CB4148;
			correct_ans = 32'hF5CB4148;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end
		#1
			testInput_a = 32'h3B67BA9D;
			testInput_b = 32'hBB67BA9D;
			correct_ans = 32'h00000000;
			cnt_test = cnt_test + 1;
		#10 
			if (adder_ans == correct_ans) begin
				success_case (testInput_a, testInput_b, correct_ans);
			end else begin
				failure_case (testInput_a, testInput_b, correct_ans, adder_ans);
			end

		$finish;
	end




task success_case;
input [31:0] testInput_a, testInput_b, correct_ans;
begin
	cnt_right = cnt_right + 1;

	$display ("Test %d ", cnt_test);
	$display ("///////////////////////");
	$display ("//// Successful %d ////", cnt_right);
	$display ("///////////////////////");
	$display ("%h + %h = ?", testInput_a, testInput_b);
	$display ("Answer = %h\n", correct_ans);
end endtask





task failure_case;
input [31:0] testInput_a, testInput_b, correct_ans, result;
begin
	$display ("Test %d ", cnt_test);
	$display ("///////////////////////");
	$display ("///////// Fail ////////");
	$display ("///////////////////////");
	$display ("%h + %h = ?", testInput_a, testInput_b);
	$display ("your answer = %h", result);
	$display ("correct answer = %h\n", correct_ans);
end endtask


endmodule