data/full_repos/permissive/205673649/BIP/Source/baudrate_gen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/205673649/BIP/Source/baudrate_gen.v:49: Operator EQ expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'contador\' generates 10 bits.\n                                                                                 : ... In instance baudrate_gen\n   if (contador == (RATE_CLK_OUT))  \n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module baudrate_gen(
    input i_clk,
	input i_rst,	
	output reg o_tick
    );
    
localparam BAUD_RATE = 9600;
localparam CLK_RATE = 100000000;
localparam NUM_TICKS = 16;

localparam RATE_CLK_OUT = CLK_RATE / (BAUD_RATE * NUM_TICKS);
localparam LEN_ACUM = $clog2(RATE_CLK_OUT);

reg [LEN_ACUM - 1 : 0] contador = 0;

always @(posedge i_clk) 
begin
	if (!i_rst)
		begin
			contador <= 0;
			o_tick <= 0;
		end
	else
		begin			
			contador <= contador + 1;
			
			if (contador == (RATE_CLK_OUT))
				begin
					o_tick <= 1;
					contador <= 0;
				end
			else
			   o_tick <= 0;
		end
end
endmodule
module baudrate_gen(
    input i_clk,
	input i_rst,	
	output reg o_tick
    );

    
localparam BAUD_RATE = 9600;
localparam CLK_RATE = 100000000;
localparam NUM_TICKS = 16;

localparam RATE_CLK_OUT = CLK_RATE / (BAUD_RATE * NUM_TICKS);
localparam LEN_ACUM = $clog2(RATE_CLK_OUT);

reg [LEN_ACUM - 1 : 0] contador = 0;

always @(posedge i_clk) 
begin
	if (!i_rst)
		begin
			contador <= 0;
			o_tick <= 0;
		end
	else
		begin			
			contador <= contador + 1;
			
			if (contador == (RATE_CLK_OUT))
				begin
					o_tick <= 1;
					contador <= 0;
				end
			else
			   o_tick <= 0;
		end
end
endmodule