data/full_repos/permissive/11455462/9052229_1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/11455462/9052229_1_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11455462/9052229_1_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/9052229_1_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Error: data/full_repos/permissive/11455462/9052229_1_tb.v:23: Cannot find file containing module: \'Mux4_1\'\nMux4_1 ramin(z,a0,a1,a2,a3,ctr0,ctr1);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/Mux4_1\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/Mux4_1.v\n             data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/Mux4_1.sv\n             Mux4_1\n             Mux4_1.v\n             Mux4_1.sv\n             obj_dir/Mux4_1\n             obj_dir/Mux4_1.v\n             obj_dir/Mux4_1.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
reg a0,a1,a2,a3,ctr0,ctr1;
wire z;

initial begin
a0 = 0;
ctr0 = 1;
ctr1 = 1;
#100
a1 = 1;
ctr0 = 1;
ctr1 = 1;
#100
a2 = 1;
ctr0 = 1;
ctr1 = 1;
#100
a3 = 1;
ctr0 = 1;
ctr1 = 1;
end
 
Mux4_1 ramin(z,a0,a1,a2,a3,ctr0,ctr1);
endmodule
module tb();

reg a0,a1,a2,a3,ctr0,ctr1;
wire z;

initial begin
a0 = 0;
ctr0 = 1;
ctr1 = 1;
#100
a1 = 1;
ctr0 = 1;
ctr1 = 1;
#100
a2 = 1;
ctr0 = 1;
ctr1 = 1;
#100
a3 = 1;
ctr0 = 1;
ctr1 = 1;
end
 
Mux4_1 ramin(z,a0,a1,a2,a3,ctr0,ctr1);
endmodule