data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v
 line:40: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nalways #1 CLK <= ~CLK;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("pruebashift.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,pruebashift);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:25: Unsupported or unknown PLI call: $monitor\n $monitor("%t: %b \\t Q: %b\\t Load: %b Sale: %b entra: %b enable %b Dir: %b", $time, CLK, Q, D,S_OUT, S_IN, ENB, DIR);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #3 ENB = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #1 ENB = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #25\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #25\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #4 ENB = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #6 ENB = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #15\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #4\n ^\n%Error: Exiting due to 3 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pruebashift;
reg [3:0] D;
reg [1:0] MODE;
reg ENB;
reg S_IN;
reg CLK;
reg DIR;
wire [3:0] Q;
wire S_OUT;

rdesplazante r1(CLK,ENB, DIR, S_IN, MODE,D,Q,S_OUT);

always #1 CLK <= ~CLK;

initial begin
	$dumpfile("pruebashift.vcd");
	$dumpvars(0,pruebashift);
	CLK = 0;
	D = 4'b0001;
	S_IN = 1;
	MODE = 2'b00;
	DIR = 1;
	ENB = 0;

	$monitor("%t: %b \t Q: %b\t Load: %b Sale: %b entra: %b enable %b Dir: %b", $time, CLK, Q, D,S_OUT, S_IN, ENB, DIR);
	$display("Desplazamiento hacia la derecha:");
	#3 ENB = 1;
	#1 ENB = 1;
	#25
	S_IN = 0;
	$display("Desplazamiento hacia la izquierda:");
	DIR = 0;
	#25
	S_IN = 1;
	#4 ENB = 0;
	#6 ENB = 1;
	$display("Rotación circular hacia la izquierda:");
	MODE = 2'b01;
	#15
	$display("Rotación circular hacia la derecha:");
	DIR = 1;
	#10
	$display("Carga en paralelo:");
	MODE = 22'b10;
	D = 4'b1010;
	#3;
	D = 4'b0000;
	#3;
	D = 4'b1011;
	#3;
	D = 4'b1111;
	#3;
	D = 4'b1001;
	#3;
	S_IN = 0;
	D = 4'b1111;
	#4

	$finish;
end
endmodule
module pruebashift;

reg [3:0] D;
reg [1:0] MODE;
reg ENB;
reg S_IN;
reg CLK;
reg DIR;
wire [3:0] Q;
wire S_OUT;

rdesplazante r1(CLK,ENB, DIR, S_IN, MODE,D,Q,S_OUT);

always #1 CLK <= ~CLK;

initial begin
	$dumpfile("pruebashift.vcd");
	$dumpvars(0,pruebashift);
	CLK = 0;
	D = 4'b0001;
	S_IN = 1;
	MODE = 2'b00;
	DIR = 1;
	ENB = 0;

	$monitor("%t: %b \t Q: %b\t Load: %b Sale: %b entra: %b enable %b Dir: %b", $time, CLK, Q, D,S_OUT, S_IN, ENB, DIR);
	$display("Desplazamiento hacia la derecha:");
	#3 ENB = 1;
	#1 ENB = 1;
	#25
	S_IN = 0;
	$display("Desplazamiento hacia la izquierda:");
	DIR = 0;
	#25
	S_IN = 1;
	#4 ENB = 0;
	#6 ENB = 1;
	$display("Rotación circular hacia la izquierda:");
	MODE = 2'b01;
	#15
	$display("Rotación circular hacia la derecha:");
	DIR = 1;
	#10
	$display("Carga en paralelo:");
	MODE = 22'b10;
	D = 4'b1010;
	#3;
	D = 4'b0000;
	#3;
	D = 4'b1011;
	#3;
	D = 4'b1111;
	#3;
	D = 4'b1001;
	#3;
	S_IN = 0;
	D = 4'b1111;
	#4

	$finish;
end
endmodule