data/full_repos/permissive/106966316/pc_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n       #100\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n       #100 \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n       #100  \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n       #100  \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n       #100 \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n       #100 \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/106966316/pc_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n       #100;\n       ^\n%Error: data/full_repos/permissive/106966316/pc_tb.v:33: Cannot find file containing module: \'pc\'\n pc uut(\n ^~\n        ... Looked in:\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/pc\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/pc.v\n             data/full_repos/permissive/106966316,data/full_repos/permissive/106966316/pc.sv\n             pc\n             pc.v\n             pc.sv\n             obj_dir/pc\n             obj_dir/pc.v\n             obj_dir/pc.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pc_tb();
 reg clk;
 reg SaltoCond;
 reg [31:0] extSigno;
 reg oZero;
 reg reset;

 
 wire  [31:0] direinstru;
 
 pc uut(
    .clk(clk),
    .SaltoCond(SaltoCond),
    .extSigno(extSigno),
    .oZero(oZero),
	.direinstru(direinstru),  
	.reset(reset) 
    
 
 );
    always 
    begin        
        clk=1'b1;
        #50
        clk=1'b0;
        #50;
    end
    
    initial begin

       reset = 1'b1;
       extSigno = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
       oZero=1'b0;
       SaltoCond = 1'b0;
       #100
       reset = 1'b0;
       
       #100
       oZero=1'b0;
       SaltoCond = 1'b0;
       extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;

       
       #100
       oZero = 1'b1;
       SaltoCond=1'b0;
       extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
       
       #100
       oZero=1'b0;
       SaltoCond=1'b1;
       extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
       
       #100
       oZero=1'b1;
       SaltoCond=1'b1;
       extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
       
       #100
       oZero=1'b1;
       SaltoCond=1'b1;
       extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001; 
       #100;
            
        
    end
endmodule
module pc_tb();

 reg clk;
 reg SaltoCond;
 reg [31:0] extSigno;
 reg oZero;
 reg reset;

 
 wire  [31:0] direinstru;
 
 pc uut(
    .clk(clk),
    .SaltoCond(SaltoCond),
    .extSigno(extSigno),
    .oZero(oZero),
	.direinstru(direinstru),  
	.reset(reset) 
    
 
 );
    always 
    begin        
        clk=1'b1;
        #50
        clk=1'b0;
        #50;
    end
    
    initial begin

       reset = 1'b1;
       extSigno = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
       oZero=1'b0;
       SaltoCond = 1'b0;
       #100
       reset = 1'b0;
       
       #100
       oZero=1'b0;
       SaltoCond = 1'b0;
       extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;

       
       #100
       oZero = 1'b1;
       SaltoCond=1'b0;
       extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
       
       #100
       oZero=1'b0;
       SaltoCond=1'b1;
       extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
       
       #100
       oZero=1'b1;
       SaltoCond=1'b1;
       extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
       
       #100
       oZero=1'b1;
       SaltoCond=1'b1;
       extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001; 
       #100;
            
        
    end
endmodule