data/full_repos/permissive/143278/ivltests/ca_mult.v
 line:9: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/ca_mult.v:9: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display(tmp, " %.5f", in);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  real in;
  wire signed [31:0] tmp;

  assign tmp = $rtoi(in*2.0);

  initial begin
    for (in=-1.0; in <= 1.0; in=in+1.0) begin
      #1 $display(tmp, " %.5f", in);
    end

  end
endmodule
module top;

  real in;
  wire signed [31:0] tmp;

  assign tmp = $rtoi(in*2.0);

  initial begin
    for (in=-1.0; in <= 1.0; in=in+1.0) begin
      #1 $display(tmp, " %.5f", in);
    end

  end
endmodule