data/full_repos/permissive/211316121/lab7_1_nexys4/Traffic.v
data/verilator_xmls/ca577149-9261-4fa3-876c-03fa47d393ac.xml
module oneSecond(
    input clk,
    input clr,
    output oneSec
    );
    reg [27:0]q;
    always@(posedge clk)
    if(clr) q<=0;
    else q<=q+1;
    assign oneSec=q[25];    
endmodule
module oneSecond(
    input clk,
    input clr,
    output oneSec
    );

    reg [27:0]q;
    always@(posedge clk)
    if(clr) q<=0;
    else q<=q+1;
    assign oneSec=q[25];    
endmodule