data/full_repos/permissive/181082280/lab_4/tb.v
 line:18: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/181082280/lab_4/tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n            #10 clk <= ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/181082280/lab_4/tb.v:18: syntax error, unexpected \'@\'\n        repeat(3) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/181082280/lab_4/tb.v:29: syntax error, unexpected \'@\'\n        repeat(50) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/181082280/lab_4/tb.v:36: Unsupported or unknown PLI call: $monitor\n        $monitor ("%0d clk %b rst %b q %b %d", $time, clk, rst, value, value);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/181082280/lab_4/tb.v:40: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;   \n        ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;


    reg        clk, rst;

    initial begin
        clk <= 0;
        forever
            #10 clk <= ~clk;
    end

    initial begin
        rst <= 'b1;
        repeat(3) @(posedge clk);
        rst <= 'b0;
    end

    wire [3:0] value;


    counter dut (clk, rst, value);


    initial begin
        repeat(50) @(posedge clk);
        $finish;
    end



    initial
        $monitor ("%0d clk %b rst %b q %b %d", $time, clk, rst, value, value);


    initial 
        $dumpvars;

endmodule
module tb;



    reg        clk, rst;

    initial begin
        clk <= 0;
        forever
            #10 clk <= ~clk;
    end

    initial begin
        rst <= 'b1;
        repeat(3) @(posedge clk);
        rst <= 'b0;
    end

    wire [3:0] value;


    counter dut (clk, rst, value);


    initial begin
        repeat(50) @(posedge clk);
        $finish;
    end



    initial
        $monitor ("%0d clk %b rst %b q %b %d", $time, clk, rst, value, value);


    initial 
        $dumpvars;

endmodule