data/full_repos/permissive/143278/ivltests/pr3296466d.v
 line:21: before: "$"
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr3296466d.v:11: Unsupported: Verilog 1995 gate primitive: tran\ntran t1(a[0], a[1]);\n     ^~\n%Error: data/full_repos/permissive/143278/ivltests/pr3296466d.v:12: Unsupported: Verilog 1995 gate primitive: tran\ntran t2(b[0], b[1]);\n     ^~\n%Error: data/full_repos/permissive/143278/ivltests/pr3296466d.v:14: Unsupported: Verilog 1995 gate primitive: tran\ntran t3[1:0](a, c[1:0]);\n     ^~\n%Error: data/full_repos/permissive/143278/ivltests/pr3296466d.v:15: Unsupported: Verilog 1995 gate primitive: tran\ntran t4[1:0](b, c[3:2]);\n     ^~\n%Error: data/full_repos/permissive/143278/ivltests/pr3296466d.v:17: Unsupported: Verilog 1995 gate primitive: tran\ntran t5(c[1], c[3]);\n     ^~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3296466d.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%b %b %b", a, b, c);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 5 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top();

reg foo;

tri [1:0] a;
tri [1:0] b;
tri [3:0] c;

assign a[0] = foo;

tran t1(a[0], a[1]);
tran t2(b[0], b[1]);

tran t3[1:0](a, c[1:0]);
tran t4[1:0](b, c[3:2]);

tran t5(c[1], c[3]);

initial begin
  foo = 1'b1;
  #1 $display("%b %b %b", a, b, c);
  if ((a === 2'b11) && (b === 2'b11) && (c === 4'b1111))
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module top();


reg foo;

tri [1:0] a;
tri [1:0] b;
tri [3:0] c;

assign a[0] = foo;

tran t1(a[0], a[1]);
tran t2(b[0], b[1]);

tran t3[1:0](a, c[1:0]);
tran t4[1:0](b, c[3:2]);

tran t5(c[1], c[3]);

initial begin
  foo = 1'b1;
  #1 $display("%b %b %b", a, b, c);
  if ((a === 2'b11) && (b === 2'b11) && (c === 4'b1111))
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule