data/full_repos/permissive/212495825/src/gaplus_io.v
1: b'%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:356: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'INP\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h0: out <= INP;  \n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:357: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h1: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'hF;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:357: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h1: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'hF;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'4\'hf\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:358: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'he\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h2: out <= ( mode == 4\'h2 ) ?       4\'hF : 4\'hE;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:359: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h3: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'h1;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:359: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'h1\' generates 4 bits.\n                                                                        : ... In instance GAPLUS_IO.iocust\n    4\'h3: out <= ( mode == 4\'h2 ) ? regs[adrs] : 4\'h1;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:276: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_add\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp1\n    regs[4\'h0] <= credit_add;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:277: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_sub\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp1\n    regs[4\'h1] <= credit_sub;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:144: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_add\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp0\n    regs[4\'h2] <= credit_add;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:145: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'credit_sub\' generates 8 bits.\n                                                                        : ... In instance GAPLUS_IO.iochp0\n    regs[4\'h3] <= credit_sub;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/gaplus_io.v:46: Output port connection \'rd\' expects 8 bits on the pin connection, but pin connection\'s VARREF \'iocust_rd\' generates 4 bits.\n                                                                       : ... In instance GAPLUS_IO\nGAPLUS_IO_CUS2 iocust( reset, clk, iocust_cs, cpu_ad[3:0], iocust_rd, cpu_wd, cpu_wr,  pcm_kick, INP2 );\n                                                           ^~~~~~~~~\n%Error: Exiting due to 13 warning(s)\n'
module GAPLUS_IO_CUS2
(
	input			 reset,
	input			 clk,
	input			 cs,
	input  [3:0] adrs,
	output [7:0] rd,
	input  [7:0] wd,
	input			 we,
	output		 kickpcm,
	
	input	 [3:0] INP
);

reg [7:0] mode;
reg [7:0] regs [0:15];
reg [7:0] out;

reg [8:0] nkick;

always @ ( posedge clk or posedge reset ) begin

	if ( reset ) begin
		nkick <= 0;
		out <= 8'hFF;
	end
	else begin
		if ( cs ) begin
			if ( we ) begin
				regs[adrs] <= wd;
				if ( adrs == 4'h8 ) mode <= wd;
				else if ( adrs == 4'h9 ) nkick <= 9'h1FF;
			end
			else begin
				case ( adrs )
				4'h0: out <= INP;
				4'h1: out <= ( mode == 4'h2 ) ? regs[adrs] : 4'hF;
				4'h2: out <= ( mode == 4'h2 ) ?       4'hF : 4'hE;
				4'h3: out <= ( mode == 4'h2 ) ? regs[adrs] : 4'h1;
				default: out <= regs[adrs];
				endcase
			end
		end
		if ( nkick != 0 ) nkick <= nkick - 1;
	end

end

assign rd = out;
assign kickpcm = ( nkick != 0 );

endmodule
module GAPLUS_IO_CUS2
(
	input			 reset,
	input			 clk,
	input			 cs,
	input  [3:0] adrs,
	output [7:0] rd,
	input  [7:0] wd,
	input			 we,
	output		 kickpcm,
	
	input	 [3:0] INP
);


reg [7:0] mode;
reg [7:0] regs [0:15];
reg [7:0] out;

reg [8:0] nkick;

always @ ( posedge clk or posedge reset ) begin

	if ( reset ) begin
		nkick <= 0;
		out <= 8'hFF;
	end
	else begin
		if ( cs ) begin
			if ( we ) begin
				regs[adrs] <= wd;
				if ( adrs == 4'h8 ) mode <= wd;
				else if ( adrs == 4'h9 ) nkick <= 9'h1FF;
			end
			else begin
				case ( adrs )
				4'h0: out <= INP;
				4'h1: out <= ( mode == 4'h2 ) ? regs[adrs] : 4'hF;
				4'h2: out <= ( mode == 4'h2 ) ?       4'hF : 4'hE;
				4'h3: out <= ( mode == 4'h2 ) ? regs[adrs] : 4'h1;
				default: out <= regs[adrs];
				endcase
			end
		end
		if ( nkick != 0 ) nkick <= nkick - 1;
	end

end

assign rd = out;
assign kickpcm = ( nkick != 0 );

endmodule