data/full_repos/permissive/206437232/TP2-UART-2019/Verilog/baud_rate_gen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/206437232/TP2-UART-2019/Verilog/baud_rate_gen.v:47: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n                                                                                             : ... In instance baud_rate_gen\n        baudRateReg <= {BAUDRATE_DIVISOR_BITS{1\'b0}};\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/206437232/TP2-UART-2019/Verilog/baud_rate_gen.v:49: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n                                                                                             : ... In instance baud_rate_gen\n        baudRateReg <= {BAUDRATE_DIVISOR_BITS{1\'b0}};\n                    ^~\n%Error: Exiting due to 2 warning(s)\n'
module baud_rate_gen
    #(
    parameter   BAUDRATE_DIVISOR = 326,
                BAUDRATE_DIVISOR_BITS = 10
    )
    (
    input   wire            i_clk,
    input   wire            i_reset,

    output  wire            o_tick
    );

reg [BAUDRATE_DIVISOR_BITS:0] baudRateReg;


always @(posedge i_clk or negedge i_reset) begin
    if (!i_reset) begin
        baudRateReg <= {BAUDRATE_DIVISOR_BITS{1'b0}};
    end else if (o_tick) begin
        baudRateReg <= {BAUDRATE_DIVISOR_BITS{1'b0}};
    end else begin
        baudRateReg <= baudRateReg + 1;
    end
end
assign o_tick = (baudRateReg == BAUDRATE_DIVISOR);
endmodule
module baud_rate_gen
    #(
    parameter   BAUDRATE_DIVISOR = 326,
                BAUDRATE_DIVISOR_BITS = 10
    )
    (
    input   wire            i_clk,
    input   wire            i_reset,

    output  wire            o_tick
    );


reg [BAUDRATE_DIVISOR_BITS:0] baudRateReg;


always @(posedge i_clk or negedge i_reset) begin
    if (!i_reset) begin
        baudRateReg <= {BAUDRATE_DIVISOR_BITS{1'b0}};
    end else if (o_tick) begin
        baudRateReg <= {BAUDRATE_DIVISOR_BITS{1'b0}};
    end else begin
        baudRateReg <= baudRateReg + 1;
    end
end
assign o_tick = (baudRateReg == BAUDRATE_DIVISOR);
endmodule