data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:44: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/dbg_if,data/full_repos/permissive/17099167/timescale.v\n             data/full_repos/permissive/17099167/system/hardware/cores/dbg_if,data/full_repos/permissive/17099167/timescale.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/dbg_if,data/full_repos/permissive/17099167/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:46: Cannot find include file: dbg_wb_defines.v\n`include "dbg_wb_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:115: Define or directive not defined: \'`DBG_WB_DR_LEN\'\nreg    [`DBG_WB_DR_LEN -1 :0] dr;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:118: Define or directive not defined: \'`DBG_WB_CMD_CNT_WIDTH\'\nreg     [`DBG_WB_CMD_CNT_WIDTH -1:0] cmd_cnt;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:126: Define or directive not defined: \'`DBG_WB_CRC_CNT_WIDTH\'\nreg     [`DBG_WB_CRC_CNT_WIDTH -1:0] crc_cnt;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:130: Define or directive not defined: \'`DBG_WB_DATA_CNT_WIDTH\'\nreg    [`DBG_WB_DATA_CNT_WIDTH:0] data_cnt;\n        ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:130: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg    [`DBG_WB_DATA_CNT_WIDTH:0] data_cnt;\n                              ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:131: Define or directive not defined: \'`DBG_WB_DATA_CNT_LIM_WIDTH\'\nreg    [`DBG_WB_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:131: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg    [`DBG_WB_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;\n                                  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:137: Define or directive not defined: \'`DBG_WB_ACC_TYPE_LEN\'\nreg    [`DBG_WB_ACC_TYPE_LEN -1:0] acc_type;\n        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:138: Define or directive not defined: \'`DBG_WB_ADR_LEN\'\nreg    [`DBG_WB_ADR_LEN -1:0] adr;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:139: Define or directive not defined: \'`DBG_WB_LEN_LEN\'\nreg    [`DBG_WB_LEN_LEN -1:0] len;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:140: Define or directive not defined: \'`DBG_WB_LEN_LEN\'\nreg    [`DBG_WB_LEN_LEN:0]    len_var;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:140: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg    [`DBG_WB_LEN_LEN:0]    len_var;\n                       ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:154: syntax error, unexpected \',\', expecting IDENTIFIER or do or final\nwire          byte, half, long;\n                  ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:157: Define or directive not defined: \'`DBG_WB_STATUS_CNT_WIDTH\'\nreg [`DBG_WB_STATUS_CNT_WIDTH -1:0] status_cnt;\n     ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:159: Define or directive not defined: \'`DBG_WB_STATUS_LEN\'\nreg [`DBG_WB_STATUS_LEN -1:0] status;\n     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:190: Define or directive not defined: \'`DBG_WB_CMD_LEN_INT\'\nreg [`DBG_WB_CMD_LEN_INT -1: 0] curr_cmd;\n     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:206: Define or directive not defined: \'`DBG_WB_GO\'\nassign curr_cmd_go      = (curr_cmd == `DBG_WB_GO) && cmd_cnt_end;\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:206: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign curr_cmd_go      = (curr_cmd == `DBG_WB_GO) && cmd_cnt_end;\n                                                 ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:207: Define or directive not defined: \'`DBG_WB_WR_COMM\'\nassign curr_cmd_wr_comm = (curr_cmd == `DBG_WB_WR_COMM) && cmd_cnt_end;\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:207: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign curr_cmd_wr_comm = (curr_cmd == `DBG_WB_WR_COMM) && cmd_cnt_end;\n                                                      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:208: Define or directive not defined: \'`DBG_WB_RD_COMM\'\nassign curr_cmd_rd_comm = (curr_cmd == `DBG_WB_RD_COMM) && cmd_cnt_end;\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:208: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign curr_cmd_rd_comm = (curr_cmd == `DBG_WB_RD_COMM) && cmd_cnt_end;\n                                                      ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:210: Define or directive not defined: \'`DBG_WB_READ8\'\nassign acc_type_read    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_READ16  || acc_type == `DBG_WB_READ32);\n                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:210: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\nassign acc_type_read    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_READ16  || acc_type == `DBG_WB_READ32);\n                                                      ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:210: Define or directive not defined: \'`DBG_WB_READ16\'\nassign acc_type_read    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_READ16  || acc_type == `DBG_WB_READ32);\n                                                                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:210: Define or directive not defined: \'`DBG_WB_READ32\'\nassign acc_type_read    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_READ16  || acc_type == `DBG_WB_READ32);\n                                                                                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:211: Define or directive not defined: \'`DBG_WB_WRITE8\'\nassign acc_type_write   = (acc_type == `DBG_WB_WRITE8 || acc_type == `DBG_WB_WRITE16 || acc_type == `DBG_WB_WRITE32);\n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:211: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\nassign acc_type_write   = (acc_type == `DBG_WB_WRITE8 || acc_type == `DBG_WB_WRITE16 || acc_type == `DBG_WB_WRITE32);\n                                                      ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:211: Define or directive not defined: \'`DBG_WB_WRITE16\'\nassign acc_type_write   = (acc_type == `DBG_WB_WRITE8 || acc_type == `DBG_WB_WRITE16 || acc_type == `DBG_WB_WRITE32);\n                                                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:211: Define or directive not defined: \'`DBG_WB_WRITE32\'\nassign acc_type_write   = (acc_type == `DBG_WB_WRITE8 || acc_type == `DBG_WB_WRITE16 || acc_type == `DBG_WB_WRITE32);\n                                                                                                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:213: Define or directive not defined: \'`DBG_WB_READ8\'\nassign acc_type_8bit    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_WRITE8);\n                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:213: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\nassign acc_type_8bit    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_WRITE8);\n                                                      ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:213: Define or directive not defined: \'`DBG_WB_WRITE8\'\nassign acc_type_8bit    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_WRITE8);\n                                                                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:214: Define or directive not defined: \'`DBG_WB_READ16\'\nassign acc_type_16bit   = (acc_type == `DBG_WB_READ16 || acc_type == `DBG_WB_WRITE16);\n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:214: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\nassign acc_type_16bit   = (acc_type == `DBG_WB_READ16 || acc_type == `DBG_WB_WRITE16);\n                                                      ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:214: Define or directive not defined: \'`DBG_WB_WRITE16\'\nassign acc_type_16bit   = (acc_type == `DBG_WB_READ16 || acc_type == `DBG_WB_WRITE16);\n                                                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:215: Define or directive not defined: \'`DBG_WB_READ32\'\nassign acc_type_32bit   = (acc_type == `DBG_WB_READ32 || acc_type == `DBG_WB_WRITE32);\n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:215: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\nassign acc_type_32bit   = (acc_type == `DBG_WB_READ32 || acc_type == `DBG_WB_WRITE32);\n                                                      ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:215: Define or directive not defined: \'`DBG_WB_WRITE32\'\nassign acc_type_32bit   = (acc_type == `DBG_WB_READ32 || acc_type == `DBG_WB_WRITE32);\n                                                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:227: syntax error, unexpected &&, expecting "\'{"\n  else if (curr_cmd_go && acc_type_read && byte && (!byte_q))\n                                                ^~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:238: Define or directive not defined: \'`DBG_WB_DR_LEN\'\n      dr <=  {`DBG_WB_DR_LEN{1\'b0}};\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:242: Define or directive not defined: \'`DBG_WB_ACC_TYPE_LEN\'\n      dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <=  {acc_type, adr, len};\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:242: Define or directive not defined: \'`DBG_WB_ADR_LEN\'\n      dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <=  {acc_type, adr, len};\n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:242: Define or directive not defined: \'`DBG_WB_LEN_LEN\'\n      dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <=  {acc_type, adr, len};\n                                                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:257: Define or directive not defined: \'`DBG_WB_READ8\'\n      if (acc_type == `DBG_WB_READ8)\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:257: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (acc_type == `DBG_WB_READ8)\n                                   ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:276: syntax error, unexpected else\n      else if (acc_type == `DBG_WB_READ16)\n      ^~~~\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/dbg_if/dbg_wb.v:276: Define or directive not defined: \'`DBG_WB_READ16\'\n      else if (acc_type == `DBG_WB_READ16)\n                           ^~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module dbg_wb(

                tck_i,
                tdi_i,
                tdo_o,


                shift_dr_i,
                pause_dr_i,
                update_dr_i,

                wishbone_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
                rst_i,


                wb_clk_i,
                                                                                

                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o 

              );


input         tck_i;
input         tdi_i;
output        tdo_o;


input         shift_dr_i;
input         pause_dr_i;
input         update_dr_i;

input         wishbone_ce_i;
input         crc_match_i;
output        crc_en_o;
output        shift_crc_o;
input         rst_i;

input         wb_clk_i;
                                                                                

output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
output  [2:0] wb_cti_o;
output  [1:0] wb_bte_o;

reg           wb_cyc_o;

reg           tdo_o;

reg    [31:0] wb_dat_tmp, wb_dat_dsff;
reg    [31:0] wb_adr_dsff;
reg     [3:0] wb_sel_dsff;
reg           wb_we_dsff;
reg    [`DBG_WB_DR_LEN -1 :0] dr;
wire          enable;
wire          cmd_cnt_en;
reg     [`DBG_WB_CMD_CNT_WIDTH -1:0] cmd_cnt;
wire          cmd_cnt_end;
reg           cmd_cnt_end_q;
reg           addr_len_cnt_en;
reg     [5:0] addr_len_cnt;
wire          addr_len_cnt_end;
reg           addr_len_cnt_end_q;
reg           crc_cnt_en;
reg     [`DBG_WB_CRC_CNT_WIDTH -1:0] crc_cnt;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
reg           data_cnt_en;
reg    [`DBG_WB_DATA_CNT_WIDTH:0] data_cnt;
reg    [`DBG_WB_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;
wire          data_cnt_end;
reg           data_cnt_end_q;

reg           crc_match_reg;

reg    [`DBG_WB_ACC_TYPE_LEN -1:0] acc_type;
reg    [`DBG_WB_ADR_LEN -1:0] adr;
reg    [`DBG_WB_LEN_LEN -1:0] len;
reg    [`DBG_WB_LEN_LEN:0]    len_var;
reg           start_rd_tck;
reg           rd_tck_started;
reg           start_rd_csff;
reg           start_wb_rd;
reg           start_wb_rd_q;
reg           start_wr_tck;
reg           start_wr_csff;
reg           start_wb_wr;
reg           start_wb_wr_q;

reg           status_cnt_en;
wire          status_cnt_end;

wire          byte, half, long;
reg           byte_q, half_q, long_q;

reg [`DBG_WB_STATUS_CNT_WIDTH -1:0] status_cnt;

reg [`DBG_WB_STATUS_LEN -1:0] status;

reg           wb_error, wb_error_csff, wb_error_tck;
reg           wb_overrun, wb_overrun_csff, wb_overrun_tck;
reg           underrun_tck;

reg           busy_wb;
reg           busy_tck;
reg           wb_end;
reg           wb_end_rst;
reg           wb_end_rst_csff;
reg           wb_end_csff;
reg           wb_end_tck, wb_end_tck_q;
reg           busy_csff;
reg           latch_data;
reg           update_dr_csff, update_dr_wb;

reg           set_addr, set_addr_csff, set_addr_wb, set_addr_wb_q;
wire   [31:0] input_data;

wire          len_eq_0;
wire          crc_cnt_31;

reg     [1:0] ptr;
reg     [2:0] fifo_cnt;
wire          fifo_full;
wire          fifo_empty;
reg     [7:0] mem [0:3];
reg     [2:0] mem_ptr_dsff;
reg           wishbone_ce_csff;
reg           mem_ptr_init;
reg [`DBG_WB_CMD_LEN_INT -1: 0] curr_cmd;
wire          curr_cmd_go;
reg           curr_cmd_go_q;
wire          curr_cmd_wr_comm;
wire          curr_cmd_rd_comm;
wire          acc_type_read;
wire          acc_type_write;
wire          acc_type_8bit;
wire          acc_type_16bit;
wire          acc_type_32bit;


assign enable = wishbone_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end;

assign curr_cmd_go      = (curr_cmd == `DBG_WB_GO) && cmd_cnt_end;
assign curr_cmd_wr_comm = (curr_cmd == `DBG_WB_WR_COMM) && cmd_cnt_end;
assign curr_cmd_rd_comm = (curr_cmd == `DBG_WB_RD_COMM) && cmd_cnt_end;

assign acc_type_read    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_READ16  || acc_type == `DBG_WB_READ32);
assign acc_type_write   = (acc_type == `DBG_WB_WRITE8 || acc_type == `DBG_WB_WRITE16 || acc_type == `DBG_WB_WRITE32);

assign acc_type_8bit    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_WRITE8);
assign acc_type_16bit   = (acc_type == `DBG_WB_READ16 || acc_type == `DBG_WB_WRITE16);
assign acc_type_32bit   = (acc_type == `DBG_WB_READ32 || acc_type == `DBG_WB_WRITE32);



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    ptr <=  2'h0;
  else if (update_dr_i)
    ptr <=  2'h0;
  else if (curr_cmd_go && acc_type_read && crc_cnt_31)
    ptr <=  ptr + 1'b1;
  else if (curr_cmd_go && acc_type_read && byte && (!byte_q))
    ptr <= ptr + 1'd1;
end
                                                                                           


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      latch_data <=  1'b0;
      dr <=  {`DBG_WB_DR_LEN{1'b0}};
    end
  else if (curr_cmd_rd_comm && crc_cnt_31)
    begin
      dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <=  {acc_type, adr, len};
    end
  else if (acc_type_read && curr_cmd_go && crc_cnt_31 && !busy_tck)
    begin
      dr[31:0] <=  input_data[31:0];
      latch_data <=  1'b1;
    end
  else if (acc_type_read && curr_cmd_go && crc_cnt_end && !busy_tck && wb_end_tck_q)  
    begin

       dr[31:0] <=  input_data[31:0];
       latch_data <=  1'b1;
    end
  else if (acc_type_read && curr_cmd_go && crc_cnt_end && !busy_tck)
    begin
      if (acc_type == `DBG_WB_READ8)
        begin
          if(byte & (~byte_q))
            begin
              case (ptr)
                2'b00 : dr[31:24] <=  input_data[31:24];
                2'b01 : dr[31:24] <=  input_data[23:16];
                2'b10 : dr[31:24] <=  input_data[15:8];
                2'b11 : dr[31:24] <=  input_data[7:0];
              endcase
              latch_data <=  1'b1;
            end
          else
            begin
	       if (enable)
		 dr[31:24] <=  {dr[30:24], 1'b0};
              latch_data <=  1'b0;
            end
        end
      else if (acc_type == `DBG_WB_READ16)
        begin
          if(half & (~half_q))
            begin
              if (ptr[1])
                dr[31:16] <=  input_data[15:0];
              else
                dr[31:16] <=  input_data[31:16];
              latch_data <=  1'b1;
            end
          else
            begin
	       if (enable)
		 dr[31:16] <=  {dr[30:16], 1'b0};
              latch_data <=  1'b0;
            end
        end
      else if (acc_type == `DBG_WB_READ32)
        begin
          if(long & (~long_q))
            begin
              dr[31:0] <=  input_data[31:0];
              latch_data <=  1'b1;
            end
          else
            begin
	       if (enable)
		 dr[31:0] <=  {dr[30:0], 1'b0};
              latch_data <=  1'b0;
            end
        end
    end
  else if (enable && (!addr_len_cnt_end))
    begin
      dr <=  {dr[`DBG_WB_DR_LEN -2:0], tdi_i};
    end
end



assign cmd_cnt_en = enable & (~cmd_cnt_end);



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    cmd_cnt <=  {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
  else if (update_dr_i)
    cmd_cnt <=  {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
  else if (cmd_cnt_en)
    cmd_cnt <=  cmd_cnt + `DBG_WB_CMD_CNT_WIDTH'd1;
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    curr_cmd <=  {`DBG_WB_CMD_LEN_INT{1'b0}};
  else if (update_dr_i)
    curr_cmd <=  {`DBG_WB_CMD_LEN_INT{1'b0}};
  else if (cmd_cnt == (`DBG_WB_CMD_LEN_INT -1))
    curr_cmd <=  {dr[`DBG_WB_CMD_LEN_INT-2 :0], tdi_i};
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    curr_cmd_go_q <=  1'b0;
  else
    curr_cmd_go_q <=  curr_cmd_go;
end


always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_rd_comm or crc_cnt_end)
begin
  if (enable && (!addr_len_cnt_end))
    begin
      if (cmd_cnt_end && curr_cmd_wr_comm)
        addr_len_cnt_en = 1'b1;
      else if (crc_cnt_end && curr_cmd_rd_comm)
        addr_len_cnt_en = 1'b1;
      else
        addr_len_cnt_en = 1'b0;
    end
  else
    addr_len_cnt_en = 1'b0;
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    addr_len_cnt <=  6'd0;
  else if (update_dr_i)
    addr_len_cnt <=  6'd0;
  else if (addr_len_cnt_en)
    addr_len_cnt <=  addr_len_cnt + 6'd1;
end


always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
begin
  if (enable && (!data_cnt_end))
    begin
      if (cmd_cnt_end && curr_cmd_go && acc_type_write)
        data_cnt_en = 1'b1;
      else if (crc_cnt_end && curr_cmd_go && acc_type_read)
        data_cnt_en = 1'b1;
      else
        data_cnt_en = 1'b0;
    end
  else
    data_cnt_en = 1'b0;
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt <=  {`DBG_WB_DATA_CNT_WIDTH+1{1'b0}};
  else if (update_dr_i)
    data_cnt <=  {`DBG_WB_DATA_CNT_WIDTH+1{1'b0}};
  else if (data_cnt_en)
    data_cnt <=  data_cnt + 1;
end




always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt_limit <=  {`DBG_WB_DATA_CNT_LIM_WIDTH+1{1'b0}};
  else if (update_dr_i)
    data_cnt_limit <=  len + 1;
end


always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
begin
  if (enable && (!crc_cnt_end) && cmd_cnt_end)
    begin
      if (addr_len_cnt_end && curr_cmd_wr_comm)
        crc_cnt_en = 1'b1;
      else if (data_cnt_end && curr_cmd_go && acc_type_write)
        crc_cnt_en = 1'b1;
      else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm))
        crc_cnt_en = 1'b1;
      else
        crc_cnt_en = 1'b0;
    end
  else
    crc_cnt_en = 1'b0;
end
   


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_cnt <=  {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
  else if(crc_cnt_en)
    crc_cnt <=  crc_cnt + 1;
  else if (update_dr_i)
    crc_cnt <=  {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
end

assign cmd_cnt_end      = cmd_cnt      == `DBG_WB_CMD_LEN;
assign addr_len_cnt_end = addr_len_cnt == `DBG_WB_DR_LEN;
assign crc_cnt_end      = crc_cnt      == `DBG_WB_CRC_CNT_WIDTH'd32;
assign crc_cnt_31       = crc_cnt      == `DBG_WB_CRC_CNT_WIDTH'd31;
assign data_cnt_end     = (data_cnt    == {data_cnt_limit, 3'b000});

always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      crc_cnt_end_q       <=  1'b0;
      cmd_cnt_end_q       <=  1'b0;
      data_cnt_end_q      <=  1'b0;
      addr_len_cnt_end_q  <=  1'b0;
    end
  else
    begin
      crc_cnt_end_q       <=  crc_cnt_end;
      cmd_cnt_end_q       <=  cmd_cnt_end;
      data_cnt_end_q      <=  data_cnt_end;
      addr_len_cnt_end_q  <=  addr_len_cnt_end;
    end
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    status_cnt <=  {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
  else if (update_dr_i)
    status_cnt <=  {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
  else if (status_cnt_en)
    status_cnt <=  status_cnt + `DBG_WB_STATUS_CNT_WIDTH'd1;
end


always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or acc_type_write or acc_type_read or data_cnt_end or addr_len_cnt_end)
begin
  if (enable && (!status_cnt_end))
    begin
      if (crc_cnt_end && curr_cmd_wr_comm)
        status_cnt_en = 1'b1;
      else if (crc_cnt_end && curr_cmd_go && acc_type_write)
        status_cnt_en = 1'b1;
      else if (data_cnt_end && curr_cmd_go && acc_type_read)
        status_cnt_en = 1'b1;
      else if (addr_len_cnt_end && curr_cmd_rd_comm)
        status_cnt_en = 1'b1;
      else
        status_cnt_en = 1'b0;
    end
  else
    status_cnt_en = 1'b0;
end


assign status_cnt_end = status_cnt == `DBG_WB_STATUS_LEN;



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      acc_type  <=  {`DBG_WB_ACC_TYPE_LEN{1'b0}};
      adr       <=  {`DBG_WB_ADR_LEN{1'b0}};
      len       <=  {`DBG_WB_LEN_LEN{1'b0}};
      set_addr  <=  1'b0;
    end
  else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
    begin
      acc_type  <=  dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1 : `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN];
      adr       <=  dr[`DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1 : `DBG_WB_LEN_LEN];
      len       <=  dr[`DBG_WB_LEN_LEN -1:0];
      set_addr  <=  1'b1;
    end
  else if(wb_end_tck)
    begin
      adr  <=  wb_adr_dsff;
    end
  else
    set_addr <=  1'b0;
end


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_match_reg <=  1'b0;
  else if(crc_cnt_end & (~crc_cnt_end_q))
    crc_match_reg <=  crc_match_i;
end


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    len_var <=  {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
  else if(update_dr_i)
    len_var <=  len + 1;
  else if (start_rd_tck)
    begin
      case (acc_type)
        `DBG_WB_READ8 : 
                    if (len_var > 'd1)
                      len_var <=  len_var - 1;
                    else
                      len_var <=  {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
        `DBG_WB_READ16: 
                    if (len_var > 'd2)
                      len_var <=  len_var - 2; 
                    else
                      len_var <=  {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
        `DBG_WB_READ32: 
                    if (len_var > 'd4)
                      len_var <=  len_var - 4; 
                    else
                      len_var <=  {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
        default:      len_var <=  {1'bx, {`DBG_WB_LEN_LEN{1'bx}}};
      endcase
    end
end


assign len_eq_0 = !(|len_var);
   


assign byte = data_cnt[2:0] == 3'd7;
assign half = data_cnt[3:0] == 4'd15;
assign long = data_cnt[4:0] == 5'd31;


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      byte_q <=   1'b0;
      half_q <=   1'b0;
      long_q <=   1'b0;
    end
  else
    begin
      byte_q <=  byte;
      half_q <=  half;
      long_q <=  long;
    end
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      start_wr_tck <=  1'b0;
      wb_dat_tmp <=  32'h0;
    end
  else if (curr_cmd_go && acc_type_write)
    begin
      case (acc_type)
        `DBG_WB_WRITE8  : begin
                        if (byte_q)
                          begin
                            start_wr_tck <=  1'b1;
                            wb_dat_tmp <=  {4{dr[7:0]}};
                          end
                        else
                          begin
                            start_wr_tck <=  1'b0;
                          end
                      end
        `DBG_WB_WRITE16 : begin
                        if (half_q)
                          begin
                            start_wr_tck <=  1'b1;
                            wb_dat_tmp <=  {2{dr[15:0]}};
                          end
                        else
                          begin
                            start_wr_tck <=  1'b0;
                          end
                      end
        `DBG_WB_WRITE32 : begin
                        if (long_q)
                          begin
                            start_wr_tck <=  1'b1;
                            wb_dat_tmp <=  dr[31:0];
                          end
                        else
                          begin
                            start_wr_tck <=  1'b0;
                          end
                       end
	default: begin

	end
      endcase
    end
  else
    start_wr_tck <=  1'b0;
end



always @ (posedge wb_clk_i)
begin
  wb_dat_dsff <=  wb_dat_tmp;
end

assign wb_dat_o = wb_dat_dsff;



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    start_rd_tck <=  1'b0;
  else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read)
    start_rd_tck <=  1'b1;
  else if ((!start_rd_tck) && curr_cmd_go && acc_type_read  && (!len_eq_0) && (!fifo_full) && (!rd_tck_started))
    start_rd_tck <=  1'b1;
  else
    start_rd_tck <=  1'b0;
end


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    rd_tck_started <=  1'b0;
  else if (update_dr_i || wb_end_tck && (!wb_end_tck_q))
    rd_tck_started <=  1'b0;
  else if (start_rd_tck)
    rd_tck_started <=  1'b1;
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      start_rd_csff   <=  1'b0;
      start_wb_rd     <=  1'b0;
      start_wb_rd_q   <=  1'b0;

      start_wr_csff   <=  1'b0;
      start_wb_wr     <=  1'b0;
      start_wb_wr_q   <=  1'b0;

      set_addr_csff   <=  1'b0;
      set_addr_wb     <=  1'b0;
      set_addr_wb_q   <=  1'b0;
    end
  else
    begin
      start_rd_csff   <=  start_rd_tck;
      start_wb_rd     <=  start_rd_csff;
      start_wb_rd_q   <=  start_wb_rd;

      start_wr_csff   <=  start_wr_tck;
      start_wb_wr     <=  start_wr_csff;
      start_wb_wr_q   <=  start_wb_wr;

      set_addr_csff   <=  set_addr;
      set_addr_wb     <=  set_addr_csff;
      set_addr_wb_q   <=  set_addr_wb;
    end
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_cyc_o <=  1'b0;
  else if ((start_wb_wr && (!start_wb_wr_q)) || (start_wb_rd && (!start_wb_rd_q)))
    wb_cyc_o <=  1'b1;
  else if (wb_ack_i || wb_err_i)
    wb_cyc_o <=  1'b0;
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_adr_dsff <=  32'd0;
  else if (set_addr_wb && (!set_addr_wb_q))
    wb_adr_dsff <=  adr;
  else if (wb_ack_i)
    begin
      if ((acc_type == `DBG_WB_WRITE8) || (acc_type == `DBG_WB_READ8))
        wb_adr_dsff <=  wb_adr_dsff + 32'd1;
      else if ((acc_type == `DBG_WB_WRITE16) || (acc_type == `DBG_WB_READ16))
        wb_adr_dsff <=  wb_adr_dsff + 32'd2;
      else
        wb_adr_dsff <=  wb_adr_dsff + 32'd4;
    end
end


assign wb_adr_o = wb_adr_dsff;









always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_sel_dsff[3:0] <=  4'h0;
  else if ((start_wb_wr && (!start_wb_wr_q)))
    begin
      case ({wb_adr_dsff[1:0], acc_type_8bit, acc_type_16bit, acc_type_32bit})
        {2'd0, 3'b100} : wb_sel_dsff[3:0] <=  4'h8;
        {2'd0, 3'b010} : wb_sel_dsff[3:0] <=  4'hC;
        {2'd0, 3'b001} : wb_sel_dsff[3:0] <=  4'hF;
        {2'd1, 3'b100} : wb_sel_dsff[3:0] <=  4'h4;
        {2'd2, 3'b100} : wb_sel_dsff[3:0] <=  4'h2;
        {2'd2, 3'b010} : wb_sel_dsff[3:0] <=  4'h3;
        {2'd3, 3'b100} : wb_sel_dsff[3:0] <=  4'h1;
        default:         wb_sel_dsff[3:0] <=  4'hx;
      endcase
    end
end


assign wb_sel_o = wb_sel_dsff;



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
     wb_we_dsff <=  1'b0;
  else if ((start_wb_wr && (!start_wb_wr_q)))
    wb_we_dsff <=  1'b1;
  else if (wb_ack_i || wb_err_i)
    wb_we_dsff <=  1'b0;
end


assign wb_we_o = wb_we_dsff;
assign wb_cab_o = 1'b0;
assign wb_stb_o = wb_cyc_o;
assign wb_cti_o = 3'h0;
assign wb_bte_o = 2'h0;
                                                                                               
                                                                                               
                                                                                               

always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_end <=  1'b0;
  else if (wb_ack_i || wb_err_i)
    wb_end <=  1'b1;
  else if (wb_end_rst)
    wb_end <=  1'b0;
end
                                                                                               
                                                                                               
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      wb_end_csff  <=  1'b0;
      wb_end_tck   <=  1'b0;
      wb_end_tck_q <=  1'b0;
    end
  else
    begin
      wb_end_csff  <=  wb_end;
      wb_end_tck   <=  wb_end_csff;
      wb_end_tck_q <=  wb_end_tck;
    end
end


always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      wb_end_rst_csff <=  1'b0;
      wb_end_rst      <=  1'b0;
    end
  else
    begin
      wb_end_rst_csff <=  wb_end_tck;
      wb_end_rst      <=  wb_end_rst_csff;
    end
end


always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    busy_wb <=  1'b0;
  else if (wb_end_rst)
    busy_wb <=  1'b0;
  else if (wb_cyc_o)
    busy_wb <=  1'b1;
end


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      busy_csff       <=  1'b0;
      busy_tck        <=  1'b0;

      update_dr_csff  <=  1'b0;
      update_dr_wb    <=  1'b0;
    end
  else
    begin
      busy_csff       <=  busy_wb;
      busy_tck        <=  busy_csff;

      update_dr_csff  <=  update_dr_i;
      update_dr_wb    <=  update_dr_csff;
    end
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_error <=  1'b0;
  else if(wb_err_i)
    wb_error <=  1'b1;
  else if(update_dr_wb)
    wb_error <=  1'b0;
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_overrun <=  1'b0;
  else if(start_wb_wr && (!start_wb_wr_q) && wb_cyc_o)
    wb_overrun <=  1'b1;
  else if(update_dr_wb)
    wb_overrun <=  1'b0;
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    underrun_tck <=  1'b0;
  else if(latch_data && fifo_empty && (!data_cnt_end))
    underrun_tck <=  1'b1;
  else if(update_dr_i)
    underrun_tck <=  1'b0;
end


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      wb_error_csff   <=  1'b0;
      wb_error_tck    <=  1'b0;

      wb_overrun_csff <=  1'b0;
      wb_overrun_tck  <=  1'b0;
    end
  else
    begin
      wb_error_csff   <=  wb_error;
      wb_error_tck    <=  wb_error_csff;

      wb_overrun_csff <=  wb_overrun;
      wb_overrun_tck  <=  wb_overrun_csff;
    end
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      wishbone_ce_csff  <=  1'b0;
      mem_ptr_init      <=  1'b0;
    end
  else
    begin
      wishbone_ce_csff  <=   wishbone_ce_i;
      mem_ptr_init      <=  ~wishbone_ce_csff;
    end
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    mem_ptr_dsff <=  3'h0;
  else if(mem_ptr_init)
    mem_ptr_dsff <=  3'h0;
  else if (wb_ack_i)
    begin
      if (acc_type == `DBG_WB_READ8)
        mem_ptr_dsff <=  mem_ptr_dsff + 3'd1;
      else if (acc_type == `DBG_WB_READ16)
        mem_ptr_dsff <=  mem_ptr_dsff + 3'd2;
    end
end



always @ (posedge wb_clk_i)
begin
  if (wb_ack_i)
    begin
      case (wb_sel_dsff)
        4'b1000  :  mem[mem_ptr_dsff[1:0]] <=  wb_dat_i[31:24];
        4'b0100  :  mem[mem_ptr_dsff[1:0]] <=  wb_dat_i[23:16];
        4'b0010  :  mem[mem_ptr_dsff[1:0]] <=  wb_dat_i[15:08];
        4'b0001  :  mem[mem_ptr_dsff[1:0]] <=  wb_dat_i[07:00];
        
	4'b1100  :
                    begin
                      mem[mem_ptr_dsff[1:0]]      <=  wb_dat_i[31:24];
                      mem[mem_ptr_dsff[1:0]+1'b1] <=  wb_dat_i[23:16];
                    end
        4'b0011  :
                    begin
                      mem[mem_ptr_dsff[1:0]]      <=  wb_dat_i[15:08];
                      mem[mem_ptr_dsff[1:0]+1'b1] <=  wb_dat_i[07:00];
                    end

	default:
                    begin
                      mem[0] <=  wb_dat_i[31:24];
                      mem[1] <=  wb_dat_i[23:16];
                      mem[2] <=  wb_dat_i[15:08];
                      mem[3] <=  wb_dat_i[07:00];
                    end

      endcase
    end
end



assign input_data = {mem[0], mem[1], mem[2], mem[3]};



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    fifo_cnt <=  3'h0;
  else if (update_dr_i)
    fifo_cnt <=  3'h0;
  else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full))
    begin
      case (acc_type)
        `DBG_WB_READ8 : fifo_cnt <=  fifo_cnt + 3'd1;
        `DBG_WB_READ16: fifo_cnt <=  fifo_cnt + 3'd2;
        `DBG_WB_READ32: fifo_cnt <=  fifo_cnt + 3'd4;
        default:        fifo_cnt <=  3'bxxx;
      endcase
    end
  else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty))
    begin
      case (acc_type)
        `DBG_WB_READ8 : fifo_cnt <=  fifo_cnt - 3'd1;
        `DBG_WB_READ16: fifo_cnt <=  fifo_cnt - 3'd2;
        `DBG_WB_READ32: fifo_cnt <=  fifo_cnt - 3'd4;
        default:        fifo_cnt <=  3'bxxx;
      endcase
    end
end


assign fifo_full  = fifo_cnt == 3'h4;
assign fifo_empty = fifo_cnt == 3'h0;



always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or 
          curr_cmd_rd_comm or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i
          or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status 
          or addr_len_cnt_end or addr_len_cnt_end_q)
begin
  if (pause_dr_i)
    begin
    tdo_o = busy_tck;
    end
  else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_go && acc_type_write ))
    begin
      tdo_o = ~crc_match_i;
    end
  else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
    begin
      tdo_o = dr[31];
    end
  else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
    begin
      tdo_o = ~crc_match_reg;
    end
  else if (curr_cmd_rd_comm && addr_len_cnt_end && (!addr_len_cnt_end_q))
    begin
      tdo_o = ~crc_match_reg;
    end
  else if (curr_cmd_rd_comm && crc_cnt_end && (!addr_len_cnt_end))
    begin
      tdo_o = dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1];
    end
  else if (status_cnt_en)
    begin
      tdo_o = status[3];
    end
  else
    begin
      tdo_o = 1'b0;
    end
end


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
    status <=  {`DBG_WB_STATUS_LEN{1'b0}};
    end
  else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
    begin
    status <=  {1'b0, wb_error_tck, wb_overrun_tck, crc_match_i};
    end
  else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
    begin
    status <=  {1'b0, wb_error_tck, underrun_tck, crc_match_reg};
    end
  else if (addr_len_cnt_end && (!addr_len_cnt_end) && curr_cmd_rd_comm)
    begin
    status <=  {1'b0, 1'b0, 1'b0, crc_match_reg};
    end
  else if (shift_dr_i && (!status_cnt_end))
    begin
    status <=  {status[`DBG_WB_STATUS_LEN -2:0], status[`DBG_WB_STATUS_LEN -1]};
    end
end








endmodule
module dbg_wb(

                tck_i,
                tdi_i,
                tdo_o,


                shift_dr_i,
                pause_dr_i,
                update_dr_i,

                wishbone_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
                rst_i,


                wb_clk_i,
                                                                                

                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o 

              );



input         tck_i;
input         tdi_i;
output        tdo_o;


input         shift_dr_i;
input         pause_dr_i;
input         update_dr_i;

input         wishbone_ce_i;
input         crc_match_i;
output        crc_en_o;
output        shift_crc_o;
input         rst_i;

input         wb_clk_i;
                                                                                

output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
output  [2:0] wb_cti_o;
output  [1:0] wb_bte_o;

reg           wb_cyc_o;

reg           tdo_o;

reg    [31:0] wb_dat_tmp, wb_dat_dsff;
reg    [31:0] wb_adr_dsff;
reg     [3:0] wb_sel_dsff;
reg           wb_we_dsff;
reg    [`DBG_WB_DR_LEN -1 :0] dr;
wire          enable;
wire          cmd_cnt_en;
reg     [`DBG_WB_CMD_CNT_WIDTH -1:0] cmd_cnt;
wire          cmd_cnt_end;
reg           cmd_cnt_end_q;
reg           addr_len_cnt_en;
reg     [5:0] addr_len_cnt;
wire          addr_len_cnt_end;
reg           addr_len_cnt_end_q;
reg           crc_cnt_en;
reg     [`DBG_WB_CRC_CNT_WIDTH -1:0] crc_cnt;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
reg           data_cnt_en;
reg    [`DBG_WB_DATA_CNT_WIDTH:0] data_cnt;
reg    [`DBG_WB_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;
wire          data_cnt_end;
reg           data_cnt_end_q;

reg           crc_match_reg;

reg    [`DBG_WB_ACC_TYPE_LEN -1:0] acc_type;
reg    [`DBG_WB_ADR_LEN -1:0] adr;
reg    [`DBG_WB_LEN_LEN -1:0] len;
reg    [`DBG_WB_LEN_LEN:0]    len_var;
reg           start_rd_tck;
reg           rd_tck_started;
reg           start_rd_csff;
reg           start_wb_rd;
reg           start_wb_rd_q;
reg           start_wr_tck;
reg           start_wr_csff;
reg           start_wb_wr;
reg           start_wb_wr_q;

reg           status_cnt_en;
wire          status_cnt_end;

wire          byte, half, long;
reg           byte_q, half_q, long_q;

reg [`DBG_WB_STATUS_CNT_WIDTH -1:0] status_cnt;

reg [`DBG_WB_STATUS_LEN -1:0] status;

reg           wb_error, wb_error_csff, wb_error_tck;
reg           wb_overrun, wb_overrun_csff, wb_overrun_tck;
reg           underrun_tck;

reg           busy_wb;
reg           busy_tck;
reg           wb_end;
reg           wb_end_rst;
reg           wb_end_rst_csff;
reg           wb_end_csff;
reg           wb_end_tck, wb_end_tck_q;
reg           busy_csff;
reg           latch_data;
reg           update_dr_csff, update_dr_wb;

reg           set_addr, set_addr_csff, set_addr_wb, set_addr_wb_q;
wire   [31:0] input_data;

wire          len_eq_0;
wire          crc_cnt_31;

reg     [1:0] ptr;
reg     [2:0] fifo_cnt;
wire          fifo_full;
wire          fifo_empty;
reg     [7:0] mem [0:3];
reg     [2:0] mem_ptr_dsff;
reg           wishbone_ce_csff;
reg           mem_ptr_init;
reg [`DBG_WB_CMD_LEN_INT -1: 0] curr_cmd;
wire          curr_cmd_go;
reg           curr_cmd_go_q;
wire          curr_cmd_wr_comm;
wire          curr_cmd_rd_comm;
wire          acc_type_read;
wire          acc_type_write;
wire          acc_type_8bit;
wire          acc_type_16bit;
wire          acc_type_32bit;


assign enable = wishbone_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end;

assign curr_cmd_go      = (curr_cmd == `DBG_WB_GO) && cmd_cnt_end;
assign curr_cmd_wr_comm = (curr_cmd == `DBG_WB_WR_COMM) && cmd_cnt_end;
assign curr_cmd_rd_comm = (curr_cmd == `DBG_WB_RD_COMM) && cmd_cnt_end;

assign acc_type_read    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_READ16  || acc_type == `DBG_WB_READ32);
assign acc_type_write   = (acc_type == `DBG_WB_WRITE8 || acc_type == `DBG_WB_WRITE16 || acc_type == `DBG_WB_WRITE32);

assign acc_type_8bit    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_WRITE8);
assign acc_type_16bit   = (acc_type == `DBG_WB_READ16 || acc_type == `DBG_WB_WRITE16);
assign acc_type_32bit   = (acc_type == `DBG_WB_READ32 || acc_type == `DBG_WB_WRITE32);



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    ptr <=  2'h0;
  else if (update_dr_i)
    ptr <=  2'h0;
  else if (curr_cmd_go && acc_type_read && crc_cnt_31)
    ptr <=  ptr + 1'b1;
  else if (curr_cmd_go && acc_type_read && byte && (!byte_q))
    ptr <= ptr + 1'd1;
end
                                                                                           


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      latch_data <=  1'b0;
      dr <=  {`DBG_WB_DR_LEN{1'b0}};
    end
  else if (curr_cmd_rd_comm && crc_cnt_31)
    begin
      dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <=  {acc_type, adr, len};
    end
  else if (acc_type_read && curr_cmd_go && crc_cnt_31 && !busy_tck)
    begin
      dr[31:0] <=  input_data[31:0];
      latch_data <=  1'b1;
    end
  else if (acc_type_read && curr_cmd_go && crc_cnt_end && !busy_tck && wb_end_tck_q)  
    begin

       dr[31:0] <=  input_data[31:0];
       latch_data <=  1'b1;
    end
  else if (acc_type_read && curr_cmd_go && crc_cnt_end && !busy_tck)
    begin
      if (acc_type == `DBG_WB_READ8)
        begin
          if(byte & (~byte_q))
            begin
              case (ptr)
                2'b00 : dr[31:24] <=  input_data[31:24];
                2'b01 : dr[31:24] <=  input_data[23:16];
                2'b10 : dr[31:24] <=  input_data[15:8];
                2'b11 : dr[31:24] <=  input_data[7:0];
              endcase
              latch_data <=  1'b1;
            end
          else
            begin
	       if (enable)
		 dr[31:24] <=  {dr[30:24], 1'b0};
              latch_data <=  1'b0;
            end
        end
      else if (acc_type == `DBG_WB_READ16)
        begin
          if(half & (~half_q))
            begin
              if (ptr[1])
                dr[31:16] <=  input_data[15:0];
              else
                dr[31:16] <=  input_data[31:16];
              latch_data <=  1'b1;
            end
          else
            begin
	       if (enable)
		 dr[31:16] <=  {dr[30:16], 1'b0};
              latch_data <=  1'b0;
            end
        end
      else if (acc_type == `DBG_WB_READ32)
        begin
          if(long & (~long_q))
            begin
              dr[31:0] <=  input_data[31:0];
              latch_data <=  1'b1;
            end
          else
            begin
	       if (enable)
		 dr[31:0] <=  {dr[30:0], 1'b0};
              latch_data <=  1'b0;
            end
        end
    end
  else if (enable && (!addr_len_cnt_end))
    begin
      dr <=  {dr[`DBG_WB_DR_LEN -2:0], tdi_i};
    end
end



assign cmd_cnt_en = enable & (~cmd_cnt_end);



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    cmd_cnt <=  {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
  else if (update_dr_i)
    cmd_cnt <=  {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
  else if (cmd_cnt_en)
    cmd_cnt <=  cmd_cnt + `DBG_WB_CMD_CNT_WIDTH'd1;
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    curr_cmd <=  {`DBG_WB_CMD_LEN_INT{1'b0}};
  else if (update_dr_i)
    curr_cmd <=  {`DBG_WB_CMD_LEN_INT{1'b0}};
  else if (cmd_cnt == (`DBG_WB_CMD_LEN_INT -1))
    curr_cmd <=  {dr[`DBG_WB_CMD_LEN_INT-2 :0], tdi_i};
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    curr_cmd_go_q <=  1'b0;
  else
    curr_cmd_go_q <=  curr_cmd_go;
end


always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_rd_comm or crc_cnt_end)
begin
  if (enable && (!addr_len_cnt_end))
    begin
      if (cmd_cnt_end && curr_cmd_wr_comm)
        addr_len_cnt_en = 1'b1;
      else if (crc_cnt_end && curr_cmd_rd_comm)
        addr_len_cnt_en = 1'b1;
      else
        addr_len_cnt_en = 1'b0;
    end
  else
    addr_len_cnt_en = 1'b0;
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    addr_len_cnt <=  6'd0;
  else if (update_dr_i)
    addr_len_cnt <=  6'd0;
  else if (addr_len_cnt_en)
    addr_len_cnt <=  addr_len_cnt + 6'd1;
end


always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
begin
  if (enable && (!data_cnt_end))
    begin
      if (cmd_cnt_end && curr_cmd_go && acc_type_write)
        data_cnt_en = 1'b1;
      else if (crc_cnt_end && curr_cmd_go && acc_type_read)
        data_cnt_en = 1'b1;
      else
        data_cnt_en = 1'b0;
    end
  else
    data_cnt_en = 1'b0;
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt <=  {`DBG_WB_DATA_CNT_WIDTH+1{1'b0}};
  else if (update_dr_i)
    data_cnt <=  {`DBG_WB_DATA_CNT_WIDTH+1{1'b0}};
  else if (data_cnt_en)
    data_cnt <=  data_cnt + 1;
end




always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt_limit <=  {`DBG_WB_DATA_CNT_LIM_WIDTH+1{1'b0}};
  else if (update_dr_i)
    data_cnt_limit <=  len + 1;
end


always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
begin
  if (enable && (!crc_cnt_end) && cmd_cnt_end)
    begin
      if (addr_len_cnt_end && curr_cmd_wr_comm)
        crc_cnt_en = 1'b1;
      else if (data_cnt_end && curr_cmd_go && acc_type_write)
        crc_cnt_en = 1'b1;
      else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm))
        crc_cnt_en = 1'b1;
      else
        crc_cnt_en = 1'b0;
    end
  else
    crc_cnt_en = 1'b0;
end
   


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_cnt <=  {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
  else if(crc_cnt_en)
    crc_cnt <=  crc_cnt + 1;
  else if (update_dr_i)
    crc_cnt <=  {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
end

assign cmd_cnt_end      = cmd_cnt      == `DBG_WB_CMD_LEN;
assign addr_len_cnt_end = addr_len_cnt == `DBG_WB_DR_LEN;
assign crc_cnt_end      = crc_cnt      == `DBG_WB_CRC_CNT_WIDTH'd32;
assign crc_cnt_31       = crc_cnt      == `DBG_WB_CRC_CNT_WIDTH'd31;
assign data_cnt_end     = (data_cnt    == {data_cnt_limit, 3'b000});

always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      crc_cnt_end_q       <=  1'b0;
      cmd_cnt_end_q       <=  1'b0;
      data_cnt_end_q      <=  1'b0;
      addr_len_cnt_end_q  <=  1'b0;
    end
  else
    begin
      crc_cnt_end_q       <=  crc_cnt_end;
      cmd_cnt_end_q       <=  cmd_cnt_end;
      data_cnt_end_q      <=  data_cnt_end;
      addr_len_cnt_end_q  <=  addr_len_cnt_end;
    end
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    status_cnt <=  {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
  else if (update_dr_i)
    status_cnt <=  {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
  else if (status_cnt_en)
    status_cnt <=  status_cnt + `DBG_WB_STATUS_CNT_WIDTH'd1;
end


always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or acc_type_write or acc_type_read or data_cnt_end or addr_len_cnt_end)
begin
  if (enable && (!status_cnt_end))
    begin
      if (crc_cnt_end && curr_cmd_wr_comm)
        status_cnt_en = 1'b1;
      else if (crc_cnt_end && curr_cmd_go && acc_type_write)
        status_cnt_en = 1'b1;
      else if (data_cnt_end && curr_cmd_go && acc_type_read)
        status_cnt_en = 1'b1;
      else if (addr_len_cnt_end && curr_cmd_rd_comm)
        status_cnt_en = 1'b1;
      else
        status_cnt_en = 1'b0;
    end
  else
    status_cnt_en = 1'b0;
end


assign status_cnt_end = status_cnt == `DBG_WB_STATUS_LEN;



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      acc_type  <=  {`DBG_WB_ACC_TYPE_LEN{1'b0}};
      adr       <=  {`DBG_WB_ADR_LEN{1'b0}};
      len       <=  {`DBG_WB_LEN_LEN{1'b0}};
      set_addr  <=  1'b0;
    end
  else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
    begin
      acc_type  <=  dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1 : `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN];
      adr       <=  dr[`DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1 : `DBG_WB_LEN_LEN];
      len       <=  dr[`DBG_WB_LEN_LEN -1:0];
      set_addr  <=  1'b1;
    end
  else if(wb_end_tck)
    begin
      adr  <=  wb_adr_dsff;
    end
  else
    set_addr <=  1'b0;
end


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_match_reg <=  1'b0;
  else if(crc_cnt_end & (~crc_cnt_end_q))
    crc_match_reg <=  crc_match_i;
end


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    len_var <=  {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
  else if(update_dr_i)
    len_var <=  len + 1;
  else if (start_rd_tck)
    begin
      case (acc_type)
        `DBG_WB_READ8 : 
                    if (len_var > 'd1)
                      len_var <=  len_var - 1;
                    else
                      len_var <=  {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
        `DBG_WB_READ16: 
                    if (len_var > 'd2)
                      len_var <=  len_var - 2; 
                    else
                      len_var <=  {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
        `DBG_WB_READ32: 
                    if (len_var > 'd4)
                      len_var <=  len_var - 4; 
                    else
                      len_var <=  {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
        default:      len_var <=  {1'bx, {`DBG_WB_LEN_LEN{1'bx}}};
      endcase
    end
end


assign len_eq_0 = !(|len_var);
   


assign byte = data_cnt[2:0] == 3'd7;
assign half = data_cnt[3:0] == 4'd15;
assign long = data_cnt[4:0] == 5'd31;


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      byte_q <=   1'b0;
      half_q <=   1'b0;
      long_q <=   1'b0;
    end
  else
    begin
      byte_q <=  byte;
      half_q <=  half;
      long_q <=  long;
    end
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      start_wr_tck <=  1'b0;
      wb_dat_tmp <=  32'h0;
    end
  else if (curr_cmd_go && acc_type_write)
    begin
      case (acc_type)
        `DBG_WB_WRITE8  : begin
                        if (byte_q)
                          begin
                            start_wr_tck <=  1'b1;
                            wb_dat_tmp <=  {4{dr[7:0]}};
                          end
                        else
                          begin
                            start_wr_tck <=  1'b0;
                          end
                      end
        `DBG_WB_WRITE16 : begin
                        if (half_q)
                          begin
                            start_wr_tck <=  1'b1;
                            wb_dat_tmp <=  {2{dr[15:0]}};
                          end
                        else
                          begin
                            start_wr_tck <=  1'b0;
                          end
                      end
        `DBG_WB_WRITE32 : begin
                        if (long_q)
                          begin
                            start_wr_tck <=  1'b1;
                            wb_dat_tmp <=  dr[31:0];
                          end
                        else
                          begin
                            start_wr_tck <=  1'b0;
                          end
                       end
	default: begin

	end
      endcase
    end
  else
    start_wr_tck <=  1'b0;
end



always @ (posedge wb_clk_i)
begin
  wb_dat_dsff <=  wb_dat_tmp;
end

assign wb_dat_o = wb_dat_dsff;



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    start_rd_tck <=  1'b0;
  else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read)
    start_rd_tck <=  1'b1;
  else if ((!start_rd_tck) && curr_cmd_go && acc_type_read  && (!len_eq_0) && (!fifo_full) && (!rd_tck_started))
    start_rd_tck <=  1'b1;
  else
    start_rd_tck <=  1'b0;
end


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    rd_tck_started <=  1'b0;
  else if (update_dr_i || wb_end_tck && (!wb_end_tck_q))
    rd_tck_started <=  1'b0;
  else if (start_rd_tck)
    rd_tck_started <=  1'b1;
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      start_rd_csff   <=  1'b0;
      start_wb_rd     <=  1'b0;
      start_wb_rd_q   <=  1'b0;

      start_wr_csff   <=  1'b0;
      start_wb_wr     <=  1'b0;
      start_wb_wr_q   <=  1'b0;

      set_addr_csff   <=  1'b0;
      set_addr_wb     <=  1'b0;
      set_addr_wb_q   <=  1'b0;
    end
  else
    begin
      start_rd_csff   <=  start_rd_tck;
      start_wb_rd     <=  start_rd_csff;
      start_wb_rd_q   <=  start_wb_rd;

      start_wr_csff   <=  start_wr_tck;
      start_wb_wr     <=  start_wr_csff;
      start_wb_wr_q   <=  start_wb_wr;

      set_addr_csff   <=  set_addr;
      set_addr_wb     <=  set_addr_csff;
      set_addr_wb_q   <=  set_addr_wb;
    end
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_cyc_o <=  1'b0;
  else if ((start_wb_wr && (!start_wb_wr_q)) || (start_wb_rd && (!start_wb_rd_q)))
    wb_cyc_o <=  1'b1;
  else if (wb_ack_i || wb_err_i)
    wb_cyc_o <=  1'b0;
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_adr_dsff <=  32'd0;
  else if (set_addr_wb && (!set_addr_wb_q))
    wb_adr_dsff <=  adr;
  else if (wb_ack_i)
    begin
      if ((acc_type == `DBG_WB_WRITE8) || (acc_type == `DBG_WB_READ8))
        wb_adr_dsff <=  wb_adr_dsff + 32'd1;
      else if ((acc_type == `DBG_WB_WRITE16) || (acc_type == `DBG_WB_READ16))
        wb_adr_dsff <=  wb_adr_dsff + 32'd2;
      else
        wb_adr_dsff <=  wb_adr_dsff + 32'd4;
    end
end


assign wb_adr_o = wb_adr_dsff;









always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_sel_dsff[3:0] <=  4'h0;
  else if ((start_wb_wr && (!start_wb_wr_q)))
    begin
      case ({wb_adr_dsff[1:0], acc_type_8bit, acc_type_16bit, acc_type_32bit})
        {2'd0, 3'b100} : wb_sel_dsff[3:0] <=  4'h8;
        {2'd0, 3'b010} : wb_sel_dsff[3:0] <=  4'hC;
        {2'd0, 3'b001} : wb_sel_dsff[3:0] <=  4'hF;
        {2'd1, 3'b100} : wb_sel_dsff[3:0] <=  4'h4;
        {2'd2, 3'b100} : wb_sel_dsff[3:0] <=  4'h2;
        {2'd2, 3'b010} : wb_sel_dsff[3:0] <=  4'h3;
        {2'd3, 3'b100} : wb_sel_dsff[3:0] <=  4'h1;
        default:         wb_sel_dsff[3:0] <=  4'hx;
      endcase
    end
end


assign wb_sel_o = wb_sel_dsff;



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
     wb_we_dsff <=  1'b0;
  else if ((start_wb_wr && (!start_wb_wr_q)))
    wb_we_dsff <=  1'b1;
  else if (wb_ack_i || wb_err_i)
    wb_we_dsff <=  1'b0;
end


assign wb_we_o = wb_we_dsff;
assign wb_cab_o = 1'b0;
assign wb_stb_o = wb_cyc_o;
assign wb_cti_o = 3'h0;
assign wb_bte_o = 2'h0;
                                                                                               
                                                                                               
                                                                                               

always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_end <=  1'b0;
  else if (wb_ack_i || wb_err_i)
    wb_end <=  1'b1;
  else if (wb_end_rst)
    wb_end <=  1'b0;
end
                                                                                               
                                                                                               
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      wb_end_csff  <=  1'b0;
      wb_end_tck   <=  1'b0;
      wb_end_tck_q <=  1'b0;
    end
  else
    begin
      wb_end_csff  <=  wb_end;
      wb_end_tck   <=  wb_end_csff;
      wb_end_tck_q <=  wb_end_tck;
    end
end


always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      wb_end_rst_csff <=  1'b0;
      wb_end_rst      <=  1'b0;
    end
  else
    begin
      wb_end_rst_csff <=  wb_end_tck;
      wb_end_rst      <=  wb_end_rst_csff;
    end
end


always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    busy_wb <=  1'b0;
  else if (wb_end_rst)
    busy_wb <=  1'b0;
  else if (wb_cyc_o)
    busy_wb <=  1'b1;
end


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      busy_csff       <=  1'b0;
      busy_tck        <=  1'b0;

      update_dr_csff  <=  1'b0;
      update_dr_wb    <=  1'b0;
    end
  else
    begin
      busy_csff       <=  busy_wb;
      busy_tck        <=  busy_csff;

      update_dr_csff  <=  update_dr_i;
      update_dr_wb    <=  update_dr_csff;
    end
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_error <=  1'b0;
  else if(wb_err_i)
    wb_error <=  1'b1;
  else if(update_dr_wb)
    wb_error <=  1'b0;
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    wb_overrun <=  1'b0;
  else if(start_wb_wr && (!start_wb_wr_q) && wb_cyc_o)
    wb_overrun <=  1'b1;
  else if(update_dr_wb)
    wb_overrun <=  1'b0;
end



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    underrun_tck <=  1'b0;
  else if(latch_data && fifo_empty && (!data_cnt_end))
    underrun_tck <=  1'b1;
  else if(update_dr_i)
    underrun_tck <=  1'b0;
end


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      wb_error_csff   <=  1'b0;
      wb_error_tck    <=  1'b0;

      wb_overrun_csff <=  1'b0;
      wb_overrun_tck  <=  1'b0;
    end
  else
    begin
      wb_error_csff   <=  wb_error;
      wb_error_tck    <=  wb_error_csff;

      wb_overrun_csff <=  wb_overrun;
      wb_overrun_tck  <=  wb_overrun_csff;
    end
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      wishbone_ce_csff  <=  1'b0;
      mem_ptr_init      <=  1'b0;
    end
  else
    begin
      wishbone_ce_csff  <=   wishbone_ce_i;
      mem_ptr_init      <=  ~wishbone_ce_csff;
    end
end



always @ (posedge wb_clk_i or posedge rst_i)
begin
  if (rst_i)
    mem_ptr_dsff <=  3'h0;
  else if(mem_ptr_init)
    mem_ptr_dsff <=  3'h0;
  else if (wb_ack_i)
    begin
      if (acc_type == `DBG_WB_READ8)
        mem_ptr_dsff <=  mem_ptr_dsff + 3'd1;
      else if (acc_type == `DBG_WB_READ16)
        mem_ptr_dsff <=  mem_ptr_dsff + 3'd2;
    end
end



always @ (posedge wb_clk_i)
begin
  if (wb_ack_i)
    begin
      case (wb_sel_dsff)
        4'b1000  :  mem[mem_ptr_dsff[1:0]] <=  wb_dat_i[31:24];
        4'b0100  :  mem[mem_ptr_dsff[1:0]] <=  wb_dat_i[23:16];
        4'b0010  :  mem[mem_ptr_dsff[1:0]] <=  wb_dat_i[15:08];
        4'b0001  :  mem[mem_ptr_dsff[1:0]] <=  wb_dat_i[07:00];
        
	4'b1100  :
                    begin
                      mem[mem_ptr_dsff[1:0]]      <=  wb_dat_i[31:24];
                      mem[mem_ptr_dsff[1:0]+1'b1] <=  wb_dat_i[23:16];
                    end
        4'b0011  :
                    begin
                      mem[mem_ptr_dsff[1:0]]      <=  wb_dat_i[15:08];
                      mem[mem_ptr_dsff[1:0]+1'b1] <=  wb_dat_i[07:00];
                    end

	default:
                    begin
                      mem[0] <=  wb_dat_i[31:24];
                      mem[1] <=  wb_dat_i[23:16];
                      mem[2] <=  wb_dat_i[15:08];
                      mem[3] <=  wb_dat_i[07:00];
                    end

      endcase
    end
end



assign input_data = {mem[0], mem[1], mem[2], mem[3]};



always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    fifo_cnt <=  3'h0;
  else if (update_dr_i)
    fifo_cnt <=  3'h0;
  else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full))
    begin
      case (acc_type)
        `DBG_WB_READ8 : fifo_cnt <=  fifo_cnt + 3'd1;
        `DBG_WB_READ16: fifo_cnt <=  fifo_cnt + 3'd2;
        `DBG_WB_READ32: fifo_cnt <=  fifo_cnt + 3'd4;
        default:        fifo_cnt <=  3'bxxx;
      endcase
    end
  else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty))
    begin
      case (acc_type)
        `DBG_WB_READ8 : fifo_cnt <=  fifo_cnt - 3'd1;
        `DBG_WB_READ16: fifo_cnt <=  fifo_cnt - 3'd2;
        `DBG_WB_READ32: fifo_cnt <=  fifo_cnt - 3'd4;
        default:        fifo_cnt <=  3'bxxx;
      endcase
    end
end


assign fifo_full  = fifo_cnt == 3'h4;
assign fifo_empty = fifo_cnt == 3'h0;



always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or 
          curr_cmd_rd_comm or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i
          or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status 
          or addr_len_cnt_end or addr_len_cnt_end_q)
begin
  if (pause_dr_i)
    begin
    tdo_o = busy_tck;
    end
  else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_go && acc_type_write ))
    begin
      tdo_o = ~crc_match_i;
    end
  else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
    begin
      tdo_o = dr[31];
    end
  else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
    begin
      tdo_o = ~crc_match_reg;
    end
  else if (curr_cmd_rd_comm && addr_len_cnt_end && (!addr_len_cnt_end_q))
    begin
      tdo_o = ~crc_match_reg;
    end
  else if (curr_cmd_rd_comm && crc_cnt_end && (!addr_len_cnt_end))
    begin
      tdo_o = dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1];
    end
  else if (status_cnt_en)
    begin
      tdo_o = status[3];
    end
  else
    begin
      tdo_o = 1'b0;
    end
end


always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
    status <=  {`DBG_WB_STATUS_LEN{1'b0}};
    end
  else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
    begin
    status <=  {1'b0, wb_error_tck, wb_overrun_tck, crc_match_i};
    end
  else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
    begin
    status <=  {1'b0, wb_error_tck, underrun_tck, crc_match_reg};
    end
  else if (addr_len_cnt_end && (!addr_len_cnt_end) && curr_cmd_rd_comm)
    begin
    status <=  {1'b0, 1'b0, 1'b0, crc_match_reg};
    end
  else if (shift_dr_i && (!status_cnt_end))
    begin
    status <=  {status[`DBG_WB_STATUS_LEN -2:0], status[`DBG_WB_STATUS_LEN -1]};
    end
end








endmodule