data/full_repos/permissive/160895047/MIPS.v
 line:103: before: "posedge"
1: b'%Error: data/full_repos/permissive/160895047/MIPS.v:1: Cannot find include file: ALU.v\n`include "ALU.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160895047,data/full_repos/permissive/160895047/ALU.v\n             data/full_repos/permissive/160895047,data/full_repos/permissive/160895047/ALU.v.v\n             data/full_repos/permissive/160895047,data/full_repos/permissive/160895047/ALU.v.sv\n             ALU.v\n             ALU.v.v\n             ALU.v.sv\n             obj_dir/ALU.v\n             obj_dir/ALU.v.v\n             obj_dir/ALU.v.sv\n%Error: data/full_repos/permissive/160895047/MIPS.v:2: Cannot find include file: Register.v\n`include "Register.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:3: Cannot find include file: Register_File.v\n`include "Register_File.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:4: Cannot find include file: Mux_2_1.v\n`include "Mux_2_1.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:5: Cannot find include file: Control_Unit.v\n`include "Control_Unit.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:6: Cannot find include file: Memory.v\n`include "Memory.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:7: Cannot find include file: Sign_Extend.v\n`include "Sign_Extend.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:8: Cannot find include file: Control_Unit.v\n`include "Control_Unit.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:9: Cannot find include file: funct.v\n`include "funct.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:10: Cannot find include file: Instruction_Memory.v\n`include "Instruction_Memory.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:53: Define or directive not defined: \'`NOOP\'\n Instruction_Memory.MEM[0][31:26] = `NOOP;\n                                    ^~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[0][31:26] = `NOOP;\n                                         ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:55: Define or directive not defined: \'`R_TYPE\'\n Instruction_Memory.MEM[4][31:26] = `R_TYPE;\n                                    ^~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:55: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[4][31:26] = `R_TYPE;\n                                           ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:59: Define or directive not defined: \'`FUNCT_ADD\'\n Instruction_Memory.MEM[4][5:0] = `FUNCT_ADD;\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:59: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[4][5:0] = `FUNCT_ADD;\n                                            ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:61: Define or directive not defined: \'`R_TYPE\'\n Instruction_Memory.MEM[8][31:26] = `R_TYPE;\n                                    ^~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:61: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[8][31:26] = `R_TYPE;\n                                           ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:65: Define or directive not defined: \'`FUNCT_ADD\'\n Instruction_Memory.MEM[8][5:0] = `FUNCT_ADD;\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[8][5:0] = `FUNCT_ADD;\n                                            ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:67: Define or directive not defined: \'`R_TYPE\'\n Instruction_Memory.MEM[12][31:26] = `R_TYPE;\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:67: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[12][31:26] = `R_TYPE;\n                                            ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:71: Define or directive not defined: \'`FUNCT_ADD\'\n Instruction_Memory.MEM[12][5:0] = `FUNCT_ADD;\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:71: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[12][5:0] = `FUNCT_ADD;\n                                             ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:73: Define or directive not defined: \'`R_TYPE\'\n Instruction_Memory.MEM[16][31:26] = `R_TYPE;\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:73: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[16][31:26] = `R_TYPE;\n                                            ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:77: Define or directive not defined: \'`FUNCT_ADD\'\n Instruction_Memory.MEM[16][5:0] = `FUNCT_ADD;\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:77: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[16][5:0] = `FUNCT_ADD;\n                                             ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:79: Define or directive not defined: \'`R_TYPE\'\n Instruction_Memory.MEM[20][31:26] = `R_TYPE;\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[20][31:26] = `R_TYPE;\n                                            ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:83: Define or directive not defined: \'`FUNCT_ADD\'\n Instruction_Memory.MEM[20][5:0] = `FUNCT_ADD;\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[20][5:0] = `FUNCT_ADD;\n                                             ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:85: Define or directive not defined: \'`R_TYPE\'\n Instruction_Memory.MEM[24][31:26] = `R_TYPE;\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:85: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[24][31:26] = `R_TYPE;\n                                            ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:89: Define or directive not defined: \'`FUNCT_ADD\'\n Instruction_Memory.MEM[24][5:0] = `FUNCT_ADD;\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:89: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[24][5:0] = `FUNCT_ADD;\n                                             ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:91: Define or directive not defined: \'`R_TYPE\'\n Instruction_Memory.MEM[28][31:26] = `R_TYPE;\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:91: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[28][31:26] = `R_TYPE;\n                                            ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:95: Define or directive not defined: \'`FUNCT_SUBTRACT\'\n Instruction_Memory.MEM[28][5:0] = `FUNCT_SUBTRACT;\n                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:95: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[28][5:0] = `FUNCT_SUBTRACT;\n                                                  ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:97: Define or directive not defined: \'`R_TYPE\'\n Instruction_Memory.MEM[32][31:26] = `R_TYPE;\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:97: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[32][31:26] = `R_TYPE;\n                                            ^\n%Error: data/full_repos/permissive/160895047/MIPS.v:101: Define or directive not defined: \'`FUNCT_SUBTRACT\'\n Instruction_Memory.MEM[32][5:0] = `FUNCT_SUBTRACT;\n                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160895047/MIPS.v:101: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n Instruction_Memory.MEM[32][5:0] = `FUNCT_SUBTRACT;\n                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/160895047/MIPS.v:105: Unsupported: Ignoring delay on this delayed statement.\n #1 CLOCK <= 1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/160895047/MIPS.v:107: Unsupported: Ignoring delay on this delayed statement.\n #1 CLOCK <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/160895047/MIPS.v:110: Unsupported: Ignoring delay on this delayed statement.\n #91 for (i = 0; i < 32; ++i)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/160895047/MIPS.v:125: Unsupported: Ignoring delay on this delayed statement.\n #5 CLOCK <= ~CLOCK;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/160895047/MIPS.v:133: Unsupported: Ignoring delay on this delayed statement.\n #10 for (i = 0; i < 32; ++i)\n ^\n%Error: Exiting due to 44 error(s), 5 warning(s)\n'
module MIPS();
reg CLOCK;

wire [31:0] PC_Next;
wire [31:0] PC;
wire [31:0] PCPlus4;
wire [31:0] PCJump;
wire [31:0] Instr;
wire [31:0] SrcA;
wire [31:0] SrcB;
wire [31:0] RD1;
wire [31:0] RD2;
wire [4:0] WriteReg;
wire [31:0] SignImm;
wire [31:0] PCBranch;
wire [31:0] WriteData;
wire Zero;
wire [31:0] ALUResult;
wire [31:0] ReadData;
wire [31:0] Result;
wire PCSrc;
wire [31:0] PCSrcQ;

wire Jump;
wire MemToReg;
wire MemWrite;
wire Branch;
wire [2:0] ALUControl;
wire ALUSrc;
wire RegDst;
wire RegWrite;

integer i;
initial
begin
	CLOCK <= 0;
	PC_Register.Q = 0;


	for (i = 0; i < 32; ++i)
		Register_File.REGS[i] = i * 2 + 5;

	Instruction_Memory.MEM[0][31:26] = `NOOP;

	Instruction_Memory.MEM[4][31:26] = `R_TYPE;
	Instruction_Memory.MEM[4][25:21] = 0;
	Instruction_Memory.MEM[4][20:16] = 0;
	Instruction_Memory.MEM[4][15:11] = 0;
	Instruction_Memory.MEM[4][5:0] = `FUNCT_ADD;

	Instruction_Memory.MEM[8][31:26] = `R_TYPE;
	Instruction_Memory.MEM[8][25:21] = 0;
	Instruction_Memory.MEM[8][20:16] = 0;
	Instruction_Memory.MEM[8][15:11] = 0;
	Instruction_Memory.MEM[8][5:0] = `FUNCT_ADD;

	Instruction_Memory.MEM[12][31:26] = `R_TYPE;
	Instruction_Memory.MEM[12][25:21] = 0;
	Instruction_Memory.MEM[12][20:16] = 0;
	Instruction_Memory.MEM[12][15:11] = 0;
	Instruction_Memory.MEM[12][5:0] = `FUNCT_ADD;

	Instruction_Memory.MEM[16][31:26] = `R_TYPE;
	Instruction_Memory.MEM[16][25:21] = 0;
	Instruction_Memory.MEM[16][20:16] = 0;
	Instruction_Memory.MEM[16][15:11] = 0;
	Instruction_Memory.MEM[16][5:0] = `FUNCT_ADD;

	Instruction_Memory.MEM[20][31:26] = `R_TYPE;
	Instruction_Memory.MEM[20][25:21] = 0;
	Instruction_Memory.MEM[20][20:16] = 0;
	Instruction_Memory.MEM[20][15:11] = 0;
	Instruction_Memory.MEM[20][5:0] = `FUNCT_ADD;

	Instruction_Memory.MEM[24][31:26] = `R_TYPE;
	Instruction_Memory.MEM[24][25:21] = 0;
	Instruction_Memory.MEM[24][20:16] = 0;
	Instruction_Memory.MEM[24][15:11] = 0;
	Instruction_Memory.MEM[24][5:0] = `FUNCT_ADD;

	Instruction_Memory.MEM[28][31:26] = `R_TYPE;
	Instruction_Memory.MEM[28][25:21] = 0;
	Instruction_Memory.MEM[28][20:16] = 1;
	Instruction_Memory.MEM[28][15:11] = 0;
	Instruction_Memory.MEM[28][5:0] = `FUNCT_SUBTRACT;

	Instruction_Memory.MEM[32][31:26] = `R_TYPE;
	Instruction_Memory.MEM[32][25:21] = 0;
	Instruction_Memory.MEM[32][20:16] = 1;
	Instruction_Memory.MEM[32][15:11] = 0;
	Instruction_Memory.MEM[32][5:0] = `FUNCT_SUBTRACT;



	#1 CLOCK <= 1;
	PC_Register.Q = 0;
	#1 CLOCK <= 0;


	#91 for (i = 0; i < 32; ++i)
		$write("%g ", Register_File.REGS[i]);
	$finish;
end

always
begin








	#5 CLOCK <= ~CLOCK;


end

always
begin
	$display("PC: %g (%b)", PC, PC);
	#10 for (i = 0; i < 32; ++i)
		$write("%g ", Register_File.REGS[i]);
	$display("");
end



assign SrcA = RD1;
assign WriteData = RD2;
assign PCPlus4 = PC + 4;
assign PCBranch = PCPlus4 + (SignImm << 2);
assign PCJump = {PCPlus4[31:28], Instr[25:0], 2'b0};
assign PCSrc = Branch && Zero;

Control_Unit Control_Unit(
	.Op(Instr[31:26]),
	.Funct(Instr[5:0]),
	.Jump(Jump),
	.MemToReg(MemToReg),
	.MemWrite(MemWrite),
	.Branch(Branch),
	.ALUControl(ALUControl),
	.ALUSrc(ALUSrc),
	.RegDst(RegDst),
	.RegWrite(RegWrite)
);

Register PC_Register(
	.CLOCK(CLOCK),
	.D(PC_Next),
	.Q(PC)
);

Memory Instruction_Memory(
	.CLOCK(CLOCK),
	.A(PC),
	.D(Instr),
	.WE(1'b0),
	.WD(32'bx)
);

Register_File Register_File(
	.CLOCK(CLOCK),
	.A1(Instr[25:21]),
	.A2(Instr[20:16]),
	.A3(WriteReg),
	.RD1(RD1),
	.RD2(RD2),
	.WE(RegWrite),
	.WD(Result)
);

Mux_2_1 SrcB_Mux(
	.A(RD2),
	.B(SignImm),
	.S(ALUSrc),
	.Q(SrcB)
);

assign WriteReg = RegDst ? Instr[15:11] : Instr[20:16];








ALU ALU(
	.A(SrcA),
	.B(SrcB),
	.Result(ALUResult),
	.Zero(Zero),
	.Control(ALUControl)
);

Memory Data_Memory(
	.CLOCK(CLOCK),
	.A(ALUResult),
	.WE(MemWrite),
	.WD(WriteData),
	.D(ReadData)
);

Mux_2_1 Result_Mux(
	.A(ALUResult),
	.B(ReadData),
	.S(MemToReg),
	.Q(Result)
);

Sign_Extend Sign_Extend(
	.v(Instr[15:0]),
	.sv(SignImm)
);


Mux_2_1 PCSrc_Mux(
	.A(PCPlus4),
	.B(PCBranch),
	.S(PCSrc),
	.Q(PCSrcQ)
);

Mux_2_1 Jump_Mux(
	.A(PCSrcQ),
	.B(PCJump),
	.S(Jump),
	.Q(PC_Next)
);

endmodule
module MIPS();

reg CLOCK;

wire [31:0] PC_Next;
wire [31:0] PC;
wire [31:0] PCPlus4;
wire [31:0] PCJump;
wire [31:0] Instr;
wire [31:0] SrcA;
wire [31:0] SrcB;
wire [31:0] RD1;
wire [31:0] RD2;
wire [4:0] WriteReg;
wire [31:0] SignImm;
wire [31:0] PCBranch;
wire [31:0] WriteData;
wire Zero;
wire [31:0] ALUResult;
wire [31:0] ReadData;
wire [31:0] Result;
wire PCSrc;
wire [31:0] PCSrcQ;

wire Jump;
wire MemToReg;
wire MemWrite;
wire Branch;
wire [2:0] ALUControl;
wire ALUSrc;
wire RegDst;
wire RegWrite;

integer i;
initial
begin
	CLOCK <= 0;
	PC_Register.Q = 0;


	for (i = 0; i < 32; ++i)
		Register_File.REGS[i] = i * 2 + 5;

	Instruction_Memory.MEM[0][31:26] = `NOOP;

	Instruction_Memory.MEM[4][31:26] = `R_TYPE;
	Instruction_Memory.MEM[4][25:21] = 0;
	Instruction_Memory.MEM[4][20:16] = 0;
	Instruction_Memory.MEM[4][15:11] = 0;
	Instruction_Memory.MEM[4][5:0] = `FUNCT_ADD;

	Instruction_Memory.MEM[8][31:26] = `R_TYPE;
	Instruction_Memory.MEM[8][25:21] = 0;
	Instruction_Memory.MEM[8][20:16] = 0;
	Instruction_Memory.MEM[8][15:11] = 0;
	Instruction_Memory.MEM[8][5:0] = `FUNCT_ADD;

	Instruction_Memory.MEM[12][31:26] = `R_TYPE;
	Instruction_Memory.MEM[12][25:21] = 0;
	Instruction_Memory.MEM[12][20:16] = 0;
	Instruction_Memory.MEM[12][15:11] = 0;
	Instruction_Memory.MEM[12][5:0] = `FUNCT_ADD;

	Instruction_Memory.MEM[16][31:26] = `R_TYPE;
	Instruction_Memory.MEM[16][25:21] = 0;
	Instruction_Memory.MEM[16][20:16] = 0;
	Instruction_Memory.MEM[16][15:11] = 0;
	Instruction_Memory.MEM[16][5:0] = `FUNCT_ADD;

	Instruction_Memory.MEM[20][31:26] = `R_TYPE;
	Instruction_Memory.MEM[20][25:21] = 0;
	Instruction_Memory.MEM[20][20:16] = 0;
	Instruction_Memory.MEM[20][15:11] = 0;
	Instruction_Memory.MEM[20][5:0] = `FUNCT_ADD;

	Instruction_Memory.MEM[24][31:26] = `R_TYPE;
	Instruction_Memory.MEM[24][25:21] = 0;
	Instruction_Memory.MEM[24][20:16] = 0;
	Instruction_Memory.MEM[24][15:11] = 0;
	Instruction_Memory.MEM[24][5:0] = `FUNCT_ADD;

	Instruction_Memory.MEM[28][31:26] = `R_TYPE;
	Instruction_Memory.MEM[28][25:21] = 0;
	Instruction_Memory.MEM[28][20:16] = 1;
	Instruction_Memory.MEM[28][15:11] = 0;
	Instruction_Memory.MEM[28][5:0] = `FUNCT_SUBTRACT;

	Instruction_Memory.MEM[32][31:26] = `R_TYPE;
	Instruction_Memory.MEM[32][25:21] = 0;
	Instruction_Memory.MEM[32][20:16] = 1;
	Instruction_Memory.MEM[32][15:11] = 0;
	Instruction_Memory.MEM[32][5:0] = `FUNCT_SUBTRACT;



	#1 CLOCK <= 1;
	PC_Register.Q = 0;
	#1 CLOCK <= 0;


	#91 for (i = 0; i < 32; ++i)
		$write("%g ", Register_File.REGS[i]);
	$finish;
end

always
begin








	#5 CLOCK <= ~CLOCK;


end

always
begin
	$display("PC: %g (%b)", PC, PC);
	#10 for (i = 0; i < 32; ++i)
		$write("%g ", Register_File.REGS[i]);
	$display("");
end



assign SrcA = RD1;
assign WriteData = RD2;
assign PCPlus4 = PC + 4;
assign PCBranch = PCPlus4 + (SignImm << 2);
assign PCJump = {PCPlus4[31:28], Instr[25:0], 2'b0};
assign PCSrc = Branch && Zero;

Control_Unit Control_Unit(
	.Op(Instr[31:26]),
	.Funct(Instr[5:0]),
	.Jump(Jump),
	.MemToReg(MemToReg),
	.MemWrite(MemWrite),
	.Branch(Branch),
	.ALUControl(ALUControl),
	.ALUSrc(ALUSrc),
	.RegDst(RegDst),
	.RegWrite(RegWrite)
);

Register PC_Register(
	.CLOCK(CLOCK),
	.D(PC_Next),
	.Q(PC)
);

Memory Instruction_Memory(
	.CLOCK(CLOCK),
	.A(PC),
	.D(Instr),
	.WE(1'b0),
	.WD(32'bx)
);

Register_File Register_File(
	.CLOCK(CLOCK),
	.A1(Instr[25:21]),
	.A2(Instr[20:16]),
	.A3(WriteReg),
	.RD1(RD1),
	.RD2(RD2),
	.WE(RegWrite),
	.WD(Result)
);

Mux_2_1 SrcB_Mux(
	.A(RD2),
	.B(SignImm),
	.S(ALUSrc),
	.Q(SrcB)
);

assign WriteReg = RegDst ? Instr[15:11] : Instr[20:16];








ALU ALU(
	.A(SrcA),
	.B(SrcB),
	.Result(ALUResult),
	.Zero(Zero),
	.Control(ALUControl)
);

Memory Data_Memory(
	.CLOCK(CLOCK),
	.A(ALUResult),
	.WE(MemWrite),
	.WD(WriteData),
	.D(ReadData)
);

Mux_2_1 Result_Mux(
	.A(ALUResult),
	.B(ReadData),
	.S(MemToReg),
	.Q(Result)
);

Sign_Extend Sign_Extend(
	.v(Instr[15:0]),
	.sv(SignImm)
);


Mux_2_1 PCSrc_Mux(
	.A(PCPlus4),
	.B(PCBranch),
	.S(PCSrc),
	.Q(PCSrcQ)
);

Mux_2_1 Jump_Mux(
	.A(PCSrcQ),
	.B(PCJump),
	.S(Jump),
	.Q(PC_Next)
);

endmodule