data/full_repos/permissive/208113388/dlx/ocx_dlx_top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/208113388/dlx/ocx_dlx_top.v:294: Cannot find file containing module: 'ocx_dlx_rxdf'\nocx_dlx_rxdf rx (\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208113388/dlx,data/full_repos/permissive/208113388/ocx_dlx_rxdf\n             data/full_repos/permissive/208113388/dlx,data/full_repos/permissive/208113388/ocx_dlx_rxdf.v\n             data/full_repos/permissive/208113388/dlx,data/full_repos/permissive/208113388/ocx_dlx_rxdf.sv\n             ocx_dlx_rxdf\n             ocx_dlx_rxdf.v\n             ocx_dlx_rxdf.sv\n             obj_dir/ocx_dlx_rxdf\n             obj_dir/ocx_dlx_rxdf.v\n             obj_dir/ocx_dlx_rxdf.sv\n%Error: data/full_repos/permissive/208113388/dlx/ocx_dlx_top.v:367: Cannot find file containing module: 'ocx_dlx_txdf'\nocx_dlx_txdf tx (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/208113388/dlx/ocx_dlx_top.v:437: Cannot find file containing module: 'ocx_dlx_xlx_if'\nocx_dlx_xlx_if xlx_if (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module ocx_dlx_top (





 dlx_tlx_flit_valid
,dlx_tlx_flit
,dlx_tlx_flit_crc_err
,dlx_tlx_link_up
,dlx_config_info
,ro_dlx_version
,ln0_rx_valid
,ln0_rx_header
,ln0_rx_data
,ln0_rx_slip
,ln1_rx_valid
,ln1_rx_header
,ln1_rx_data
,ln1_rx_slip
,ln2_rx_valid
,ln2_rx_header
,ln2_rx_data
,ln2_rx_slip
,ln3_rx_valid
,ln3_rx_header
,ln3_rx_data
,ln3_rx_slip
,ln4_rx_valid
,ln4_rx_header
,ln4_rx_data
,ln4_rx_slip
,ln5_rx_valid
,ln5_rx_header
,ln5_rx_data
,ln5_rx_slip
,ln6_rx_valid
,ln6_rx_header
,ln6_rx_data
,ln6_rx_slip
,ln7_rx_valid
,ln7_rx_header
,ln7_rx_data
,ln7_rx_slip




,dlx_tlx_init_flit_depth
,dlx_tlx_flit_credit
,tlx_dlx_flit_valid
,tlx_dlx_flit
   

,dlx_l0_tx_data
,dlx_l1_tx_data
,dlx_l2_tx_data
,dlx_l3_tx_data
,dlx_l4_tx_data
,dlx_l5_tx_data
,dlx_l6_tx_data
,dlx_l7_tx_data
,dlx_l0_tx_header
,dlx_l1_tx_header
,dlx_l2_tx_header
,dlx_l3_tx_header
,dlx_l4_tx_header
,dlx_l5_tx_header
,dlx_l6_tx_header
,dlx_l7_tx_header
,dlx_l0_tx_seq
,dlx_l1_tx_seq
,dlx_l2_tx_seq
,dlx_l3_tx_seq
,dlx_l4_tx_seq
,dlx_l5_tx_seq
,dlx_l6_tx_seq
,dlx_l7_tx_seq

,tlx_dlx_debug_encode
,tlx_dlx_debug_info
 
,opt_gckn
,ocde                                                                 





,clk_156_25MHz
,gtwiz_reset_all_out
,hb_gtwiz_reset_all_in
,gtwiz_reset_tx_done_in
,gtwiz_reset_rx_done_in
,gtwiz_buffbypass_tx_done_in
,gtwiz_buffbypass_rx_done_in
,gtwiz_userclk_tx_active_in
,gtwiz_userclk_rx_active_in
,send_first
,gtwiz_reset_rx_datapath_out
);




output            dlx_tlx_flit_valid;
output [511:0]    dlx_tlx_flit;
output            dlx_tlx_flit_crc_err;

output            dlx_tlx_link_up;
output [31:0]     dlx_config_info;
output [31:0]     ro_dlx_version;


input             ln0_rx_valid;
input  [1:0]      ln0_rx_header;                              
input  [63:0]     ln0_rx_data;                               
output            ln0_rx_slip;                        
input             ln1_rx_valid;
input  [1:0]      ln1_rx_header;                              
input  [63:0]     ln1_rx_data;                               
output            ln1_rx_slip;                        
input             ln2_rx_valid;
input  [1:0]      ln2_rx_header;                              
input  [63:0]     ln2_rx_data;                               
output            ln2_rx_slip;                        
input             ln3_rx_valid;
input  [1:0]      ln3_rx_header;                              
input  [63:0]     ln3_rx_data;                               
output            ln3_rx_slip;                        
input             ln4_rx_valid;
input  [1:0]      ln4_rx_header;                              
input  [63:0]     ln4_rx_data;                               
output            ln4_rx_slip;                        
input             ln5_rx_valid;
input  [1:0]      ln5_rx_header;                              
input  [63:0]     ln5_rx_data;                               
output            ln5_rx_slip;                        
input             ln6_rx_valid;
input  [1:0]      ln6_rx_header;                              
input  [63:0]     ln6_rx_data;                               
output            ln6_rx_slip;                        
input             ln7_rx_valid;
input  [1:0]      ln7_rx_header;                              
input  [63:0]     ln7_rx_data;                               
output            ln7_rx_slip;                        






output            dlx_tlx_flit_credit;
output [2:0]      dlx_tlx_init_flit_depth;
input             tlx_dlx_flit_valid;
input  [511:0]    tlx_dlx_flit;

output [63:0]     dlx_l0_tx_data;
output [63:0]     dlx_l1_tx_data;
output [63:0]     dlx_l2_tx_data;
output [63:0]     dlx_l3_tx_data;
output [63:0]     dlx_l4_tx_data;
output [63:0]     dlx_l5_tx_data;
output [63:0]     dlx_l6_tx_data;
output [63:0]     dlx_l7_tx_data;
output [1:0]      dlx_l0_tx_header;
output [1:0]      dlx_l1_tx_header;
output [1:0]      dlx_l2_tx_header;
output [1:0]      dlx_l3_tx_header;
output [1:0]      dlx_l4_tx_header;
output [1:0]      dlx_l5_tx_header;
output [1:0]      dlx_l6_tx_header;
output [1:0]      dlx_l7_tx_header;
output [5:0]      dlx_l0_tx_seq;
output [5:0]      dlx_l1_tx_seq;
output [5:0]      dlx_l2_tx_seq;
output [5:0]      dlx_l3_tx_seq;
output [5:0]      dlx_l4_tx_seq;
output [5:0]      dlx_l5_tx_seq;
output [5:0]      dlx_l6_tx_seq;
output [5:0]      dlx_l7_tx_seq;


input  [3:0]      tlx_dlx_debug_encode;
input  [31:0]     tlx_dlx_debug_info;

input             opt_gckn;
input             ocde;









wire            dlx_reset; 
wire [7:0]      pb_io_o0_rx_run_lane;
wire [7:0]      io_pb_o0_rx_init_done;
input           clk_156_25MHz;
input           hb_gtwiz_reset_all_in;
output          gtwiz_reset_all_out;
output          gtwiz_reset_rx_datapath_out;
input           gtwiz_reset_tx_done_in;
input           gtwiz_reset_rx_done_in;
input           gtwiz_buffbypass_tx_done_in;
input           gtwiz_buffbypass_rx_done_in;
input           gtwiz_userclk_tx_active_in;
input           gtwiz_userclk_rx_active_in;
input           send_first;

wire            tx_rx_reset;
wire            train_ts2;
wire            train_ts67;
wire            rx_tx_crc_error;
wire            rx_tx_retrain;
wire            rx_tx_nack;
wire [4:0]      rx_tx_tx_ack_rtn;
wire [3:0]      rx_tx_rx_ack_inc;
wire            rx_tx_tx_ack_ptr_vld;
wire [6:0]      rx_tx_tx_ack_ptr;
wire            rx_tx_tx_lane_swap;
wire            rx_tx_deskew_done;
wire            rx_tx_linkup;
wire [7:0]      ln0_rx_tx_last_byte_ts3;
wire [7:0]      ln1_rx_tx_last_byte_ts3;
wire [7:0]      ln2_rx_tx_last_byte_ts3;
wire [7:0]      ln3_rx_tx_last_byte_ts3;
wire            tx_rx_training;
wire [7:0]      tx_rx_disabled_rx_lanes;
wire            tx_rx_phy_training;
wire [7:0]      rx_tx_pattern_a;
wire [7:0]      rx_tx_pattern_b;
wire [7:0]      rx_tx_sync;
wire [7:0]      rx_tx_TS1;
wire [7:0]      rx_tx_TS2;
wire [7:0]      rx_tx_TS3;
wire [7:0]      rx_tx_block_lock;
wire [7:0]      rx_tx_lane_inverted;










wire      ln0_rx_valid_int;
wire      ln1_rx_valid_int;
wire      ln2_rx_valid_int;
wire      ln3_rx_valid_int;
wire      ln4_rx_valid_int;
wire      ln5_rx_valid_int;
wire      ln6_rx_valid_int;
wire      ln7_rx_valid_int;

wire            cfg_transmit_order;
assign          cfg_transmit_order = 1'b1;

    

ocx_dlx_rxdf rx (
 .ln0_rx_valid                  (ln0_rx_valid_int)
,.ln0_rx_data                   (ln0_rx_data)
,.ln0_rx_header                 (ln0_rx_header)
,.ln0_rx_slip                   (ln0_rx_slip)
,.ln1_rx_valid                  (ln1_rx_valid_int)
,.ln1_rx_data                   (ln1_rx_data)
,.ln1_rx_header                 (ln1_rx_header)
,.ln1_rx_slip                   (ln1_rx_slip)
,.ln2_rx_valid                  (ln2_rx_valid_int)
,.ln2_rx_data                   (ln2_rx_data)
,.ln2_rx_header                 (ln2_rx_header)
,.ln2_rx_slip                   (ln2_rx_slip)
,.ln3_rx_valid                  (ln3_rx_valid_int)
,.ln3_rx_data                   (ln3_rx_data)
,.ln3_rx_header                 (ln3_rx_header)
,.ln3_rx_slip                   (ln3_rx_slip)
,.ln4_rx_valid                  (ln4_rx_valid_int)
,.ln4_rx_data                   (ln4_rx_data)
,.ln4_rx_header                 (ln4_rx_header)
,.ln4_rx_slip                   (ln4_rx_slip)
,.ln5_rx_valid                  (ln5_rx_valid_int)
,.ln5_rx_data                   (ln5_rx_data)
,.ln5_rx_header                 (ln5_rx_header)
,.ln5_rx_slip                   (ln5_rx_slip)
,.ln6_rx_valid                  (ln6_rx_valid_int)
,.ln6_rx_data                   (ln6_rx_data)
,.ln6_rx_slip                   (ln6_rx_slip)
,.ln6_rx_header                 (ln6_rx_header)
,.ln7_rx_valid                  (ln7_rx_valid_int)
,.ln7_rx_data                   (ln7_rx_data)
,.ln7_rx_header                 (ln7_rx_header)
,.ln7_rx_slip                   (ln7_rx_slip)
,.dlx_tlx_flit_valid            (dlx_tlx_flit_valid)
,.dlx_tlx_flit                  (dlx_tlx_flit)
,.dlx_tlx_flit_crc_err          (dlx_tlx_flit_crc_err)
,.dlx_tlx_link_up               (dlx_tlx_link_up)
,.dlx_config_info               (dlx_config_info)
,.cfg_transmit_order            (cfg_transmit_order)
,.tx_rx_reset                   (tx_rx_reset)
,.train_ts2                     (train_ts2)
,.train_ts67                    (train_ts67)
,.rx_tx_retrain                 (rx_tx_retrain)
,.rx_tx_crc_error               (rx_tx_crc_error)
,.rx_tx_nack                    (rx_tx_nack)
,.rx_tx_tx_ack_rtn              (rx_tx_tx_ack_rtn)
,.rx_tx_rx_ack_inc              (rx_tx_rx_ack_inc)
,.rx_tx_tx_ack_ptr_vld          (rx_tx_tx_ack_ptr_vld)
,.rx_tx_tx_ack_ptr              (rx_tx_tx_ack_ptr)
,.ln0_rx_tx_last_byte_ts3       (ln0_rx_tx_last_byte_ts3)
,.ln1_rx_tx_last_byte_ts3       (ln1_rx_tx_last_byte_ts3)
,.ln2_rx_tx_last_byte_ts3       (ln2_rx_tx_last_byte_ts3)
,.ln3_rx_tx_last_byte_ts3       (ln3_rx_tx_last_byte_ts3)
,.rx_tx_tx_lane_swap            (rx_tx_tx_lane_swap)
,.rx_tx_deskew_done             (rx_tx_deskew_done)
,.tx_rx_training                (tx_rx_training)
,.tx_rx_phy_training            (tx_rx_phy_training)
,.tx_rx_disabled_rx_lanes       (tx_rx_disabled_rx_lanes)
,.rx_tx_pattern_a               (rx_tx_pattern_a)
,.rx_tx_pattern_b               (rx_tx_pattern_b)
,.rx_tx_lane_inverted           (rx_tx_lane_inverted)
,.rx_tx_sync                    (rx_tx_sync)
,.rx_tx_TS1                     (rx_tx_TS1)
,.rx_tx_TS2                     (rx_tx_TS2)
,.rx_tx_TS3                     (rx_tx_TS3)
,.rx_tx_block_lock              (rx_tx_block_lock)
,.rx_tx_linkup                  (rx_tx_linkup)
,.opt_gckn                      (opt_gckn)


);


ocx_dlx_txdf tx (
 .dlx_tlx_init_flit_depth       (dlx_tlx_init_flit_depth)
,.dlx_tlx_flit_credit           (dlx_tlx_flit_credit)
,.tlx_dlx_flit_valid            (tlx_dlx_flit_valid)
,.tlx_dlx_flit                  (tlx_dlx_flit)
,.ro_dlx_version                (ro_dlx_version)
,.dlx_l0_tx_data                (dlx_l0_tx_data)
,.dlx_l1_tx_data                (dlx_l1_tx_data)
,.dlx_l2_tx_data                (dlx_l2_tx_data)
,.dlx_l3_tx_data                (dlx_l3_tx_data)
,.dlx_l4_tx_data                (dlx_l4_tx_data)
,.dlx_l5_tx_data                (dlx_l5_tx_data)
,.dlx_l6_tx_data                (dlx_l6_tx_data)
,.dlx_l7_tx_data                (dlx_l7_tx_data)
,.dlx_l0_tx_header              (dlx_l0_tx_header)
,.dlx_l1_tx_header              (dlx_l1_tx_header)
,.dlx_l2_tx_header              (dlx_l2_tx_header)
,.dlx_l3_tx_header              (dlx_l3_tx_header)
,.dlx_l4_tx_header              (dlx_l4_tx_header)
,.dlx_l5_tx_header              (dlx_l5_tx_header)
,.dlx_l6_tx_header              (dlx_l6_tx_header)
,.dlx_l7_tx_header              (dlx_l7_tx_header)
,.dlx_l0_tx_seq                 (dlx_l0_tx_seq)
,.dlx_l1_tx_seq                 (dlx_l1_tx_seq)
,.dlx_l2_tx_seq                 (dlx_l2_tx_seq)
,.dlx_l3_tx_seq                 (dlx_l3_tx_seq)
,.dlx_l4_tx_seq                 (dlx_l4_tx_seq)
,.dlx_l5_tx_seq                 (dlx_l5_tx_seq)
,.dlx_l6_tx_seq                 (dlx_l6_tx_seq)
,.dlx_l7_tx_seq                 (dlx_l7_tx_seq)
,.cfg_transmit_order            (cfg_transmit_order)
,.pb_io_o0_rx_run_lane          (pb_io_o0_rx_run_lane)
,.io_pb_o0_rx_init_done         (io_pb_o0_rx_init_done)
,.tlx_dlx_debug_encode          (tlx_dlx_debug_encode)
,.tlx_dlx_debug_info            (tlx_dlx_debug_info)
,.rx_tx_tx_lane_swap            (rx_tx_tx_lane_swap)
,.rx_tx_crc_error               (rx_tx_crc_error)
,.rx_tx_retrain                 (rx_tx_retrain)
,.rx_tx_nack                    (rx_tx_nack)
,.rx_tx_tx_ack_rtn              (rx_tx_tx_ack_rtn)
,.rx_tx_rx_ack_inc              (rx_tx_rx_ack_inc)
,.rx_tx_tx_ack_ptr_vld          (rx_tx_tx_ack_ptr_vld)
,.rx_tx_tx_ack_ptr              (rx_tx_tx_ack_ptr)
,.tx_rx_reset                   (tx_rx_reset)
,.train_ts2                     (train_ts2)
,.train_ts67                    (train_ts67)
,.tx_rx_phy_training            (tx_rx_phy_training)
,.rx_tx_pattern_a               (rx_tx_pattern_a)
,.rx_tx_pattern_b               (rx_tx_pattern_b)
,.rx_tx_lane_inverted           (rx_tx_lane_inverted)
,.rx_tx_sync                    (rx_tx_sync)
,.rx_tx_TS1                     (rx_tx_TS1)
,.rx_tx_TS2                     (rx_tx_TS2)
,.rx_tx_TS3                     (rx_tx_TS3)
,.rx_tx_block_lock              (rx_tx_block_lock)
,.rx_tx_deskew_done             (rx_tx_deskew_done)
,.rx_tx_linkup                  (rx_tx_linkup)
,.ln0_rx_tx_last_byte_ts3       (ln0_rx_tx_last_byte_ts3)
,.ln1_rx_tx_last_byte_ts3       (ln1_rx_tx_last_byte_ts3)
,.ln2_rx_tx_last_byte_ts3       (ln2_rx_tx_last_byte_ts3)
,.ln3_rx_tx_last_byte_ts3       (ln3_rx_tx_last_byte_ts3)
,.dlx_reset                     (dlx_reset)
,.tx_rx_training                (tx_rx_training)
,.tx_rx_disabled_rx_lanes       (tx_rx_disabled_rx_lanes)
,.dlx_clk                       (opt_gckn)


);


ocx_dlx_xlx_if xlx_if (
 .clk_156_25MHz                 (clk_156_25MHz)
,.opt_gckn                      (opt_gckn)
,.ocde                          (ocde)
,.hb_gtwiz_reset_all_in         (hb_gtwiz_reset_all_in)
,.gtwiz_reset_all_out           (gtwiz_reset_all_out)
,.gtwiz_reset_rx_datapath_out   (gtwiz_reset_rx_datapath_out)
,.gtwiz_reset_tx_done_in        (gtwiz_reset_tx_done_in)
,.gtwiz_reset_rx_done_in        (gtwiz_reset_rx_done_in)
,.gtwiz_buffbypass_tx_done_in   (gtwiz_buffbypass_tx_done_in)
,.gtwiz_buffbypass_rx_done_in   (gtwiz_buffbypass_rx_done_in)
,.gtwiz_userclk_tx_active_in    (gtwiz_userclk_tx_active_in)
,.gtwiz_userclk_rx_active_in    (gtwiz_userclk_rx_active_in)
,.dlx_reset                     (dlx_reset)
,.pb_io_o0_rx_run_lane          (pb_io_o0_rx_run_lane)
,.io_pb_o0_rx_init_done         (io_pb_o0_rx_init_done)
,.send_first                    (send_first)
,.ln0_rx_valid_in               (ln0_rx_valid)
,.ln1_rx_valid_in               (ln1_rx_valid)
,.ln2_rx_valid_in               (ln2_rx_valid)
,.ln3_rx_valid_in               (ln3_rx_valid)
,.ln4_rx_valid_in               (ln4_rx_valid)
,.ln5_rx_valid_in               (ln5_rx_valid)
,.ln6_rx_valid_in               (ln6_rx_valid)
,.ln7_rx_valid_in               (ln7_rx_valid)
,.ln0_rx_valid_out              (ln0_rx_valid_int)
,.ln1_rx_valid_out              (ln1_rx_valid_int)
,.ln2_rx_valid_out              (ln2_rx_valid_int)
,.ln3_rx_valid_out              (ln3_rx_valid_int)
,.ln4_rx_valid_out              (ln4_rx_valid_int)
,.ln5_rx_valid_out              (ln5_rx_valid_int)
,.ln6_rx_valid_out              (ln6_rx_valid_int)
,.ln7_rx_valid_out              (ln7_rx_valid_int)
);

endmodule
module ocx_dlx_top (





 dlx_tlx_flit_valid
,dlx_tlx_flit
,dlx_tlx_flit_crc_err
,dlx_tlx_link_up
,dlx_config_info
,ro_dlx_version
,ln0_rx_valid
,ln0_rx_header
,ln0_rx_data
,ln0_rx_slip
,ln1_rx_valid
,ln1_rx_header
,ln1_rx_data
,ln1_rx_slip
,ln2_rx_valid
,ln2_rx_header
,ln2_rx_data
,ln2_rx_slip
,ln3_rx_valid
,ln3_rx_header
,ln3_rx_data
,ln3_rx_slip
,ln4_rx_valid
,ln4_rx_header
,ln4_rx_data
,ln4_rx_slip
,ln5_rx_valid
,ln5_rx_header
,ln5_rx_data
,ln5_rx_slip
,ln6_rx_valid
,ln6_rx_header
,ln6_rx_data
,ln6_rx_slip
,ln7_rx_valid
,ln7_rx_header
,ln7_rx_data
,ln7_rx_slip




,dlx_tlx_init_flit_depth
,dlx_tlx_flit_credit
,tlx_dlx_flit_valid
,tlx_dlx_flit
   

,dlx_l0_tx_data
,dlx_l1_tx_data
,dlx_l2_tx_data
,dlx_l3_tx_data
,dlx_l4_tx_data
,dlx_l5_tx_data
,dlx_l6_tx_data
,dlx_l7_tx_data
,dlx_l0_tx_header
,dlx_l1_tx_header
,dlx_l2_tx_header
,dlx_l3_tx_header
,dlx_l4_tx_header
,dlx_l5_tx_header
,dlx_l6_tx_header
,dlx_l7_tx_header
,dlx_l0_tx_seq
,dlx_l1_tx_seq
,dlx_l2_tx_seq
,dlx_l3_tx_seq
,dlx_l4_tx_seq
,dlx_l5_tx_seq
,dlx_l6_tx_seq
,dlx_l7_tx_seq

,tlx_dlx_debug_encode
,tlx_dlx_debug_info
 
,opt_gckn
,ocde                                                                 





,clk_156_25MHz
,gtwiz_reset_all_out
,hb_gtwiz_reset_all_in
,gtwiz_reset_tx_done_in
,gtwiz_reset_rx_done_in
,gtwiz_buffbypass_tx_done_in
,gtwiz_buffbypass_rx_done_in
,gtwiz_userclk_tx_active_in
,gtwiz_userclk_rx_active_in
,send_first
,gtwiz_reset_rx_datapath_out
);





output            dlx_tlx_flit_valid;
output [511:0]    dlx_tlx_flit;
output            dlx_tlx_flit_crc_err;

output            dlx_tlx_link_up;
output [31:0]     dlx_config_info;
output [31:0]     ro_dlx_version;


input             ln0_rx_valid;
input  [1:0]      ln0_rx_header;                              
input  [63:0]     ln0_rx_data;                               
output            ln0_rx_slip;                        
input             ln1_rx_valid;
input  [1:0]      ln1_rx_header;                              
input  [63:0]     ln1_rx_data;                               
output            ln1_rx_slip;                        
input             ln2_rx_valid;
input  [1:0]      ln2_rx_header;                              
input  [63:0]     ln2_rx_data;                               
output            ln2_rx_slip;                        
input             ln3_rx_valid;
input  [1:0]      ln3_rx_header;                              
input  [63:0]     ln3_rx_data;                               
output            ln3_rx_slip;                        
input             ln4_rx_valid;
input  [1:0]      ln4_rx_header;                              
input  [63:0]     ln4_rx_data;                               
output            ln4_rx_slip;                        
input             ln5_rx_valid;
input  [1:0]      ln5_rx_header;                              
input  [63:0]     ln5_rx_data;                               
output            ln5_rx_slip;                        
input             ln6_rx_valid;
input  [1:0]      ln6_rx_header;                              
input  [63:0]     ln6_rx_data;                               
output            ln6_rx_slip;                        
input             ln7_rx_valid;
input  [1:0]      ln7_rx_header;                              
input  [63:0]     ln7_rx_data;                               
output            ln7_rx_slip;                        






output            dlx_tlx_flit_credit;
output [2:0]      dlx_tlx_init_flit_depth;
input             tlx_dlx_flit_valid;
input  [511:0]    tlx_dlx_flit;

output [63:0]     dlx_l0_tx_data;
output [63:0]     dlx_l1_tx_data;
output [63:0]     dlx_l2_tx_data;
output [63:0]     dlx_l3_tx_data;
output [63:0]     dlx_l4_tx_data;
output [63:0]     dlx_l5_tx_data;
output [63:0]     dlx_l6_tx_data;
output [63:0]     dlx_l7_tx_data;
output [1:0]      dlx_l0_tx_header;
output [1:0]      dlx_l1_tx_header;
output [1:0]      dlx_l2_tx_header;
output [1:0]      dlx_l3_tx_header;
output [1:0]      dlx_l4_tx_header;
output [1:0]      dlx_l5_tx_header;
output [1:0]      dlx_l6_tx_header;
output [1:0]      dlx_l7_tx_header;
output [5:0]      dlx_l0_tx_seq;
output [5:0]      dlx_l1_tx_seq;
output [5:0]      dlx_l2_tx_seq;
output [5:0]      dlx_l3_tx_seq;
output [5:0]      dlx_l4_tx_seq;
output [5:0]      dlx_l5_tx_seq;
output [5:0]      dlx_l6_tx_seq;
output [5:0]      dlx_l7_tx_seq;


input  [3:0]      tlx_dlx_debug_encode;
input  [31:0]     tlx_dlx_debug_info;

input             opt_gckn;
input             ocde;









wire            dlx_reset; 
wire [7:0]      pb_io_o0_rx_run_lane;
wire [7:0]      io_pb_o0_rx_init_done;
input           clk_156_25MHz;
input           hb_gtwiz_reset_all_in;
output          gtwiz_reset_all_out;
output          gtwiz_reset_rx_datapath_out;
input           gtwiz_reset_tx_done_in;
input           gtwiz_reset_rx_done_in;
input           gtwiz_buffbypass_tx_done_in;
input           gtwiz_buffbypass_rx_done_in;
input           gtwiz_userclk_tx_active_in;
input           gtwiz_userclk_rx_active_in;
input           send_first;

wire            tx_rx_reset;
wire            train_ts2;
wire            train_ts67;
wire            rx_tx_crc_error;
wire            rx_tx_retrain;
wire            rx_tx_nack;
wire [4:0]      rx_tx_tx_ack_rtn;
wire [3:0]      rx_tx_rx_ack_inc;
wire            rx_tx_tx_ack_ptr_vld;
wire [6:0]      rx_tx_tx_ack_ptr;
wire            rx_tx_tx_lane_swap;
wire            rx_tx_deskew_done;
wire            rx_tx_linkup;
wire [7:0]      ln0_rx_tx_last_byte_ts3;
wire [7:0]      ln1_rx_tx_last_byte_ts3;
wire [7:0]      ln2_rx_tx_last_byte_ts3;
wire [7:0]      ln3_rx_tx_last_byte_ts3;
wire            tx_rx_training;
wire [7:0]      tx_rx_disabled_rx_lanes;
wire            tx_rx_phy_training;
wire [7:0]      rx_tx_pattern_a;
wire [7:0]      rx_tx_pattern_b;
wire [7:0]      rx_tx_sync;
wire [7:0]      rx_tx_TS1;
wire [7:0]      rx_tx_TS2;
wire [7:0]      rx_tx_TS3;
wire [7:0]      rx_tx_block_lock;
wire [7:0]      rx_tx_lane_inverted;










wire      ln0_rx_valid_int;
wire      ln1_rx_valid_int;
wire      ln2_rx_valid_int;
wire      ln3_rx_valid_int;
wire      ln4_rx_valid_int;
wire      ln5_rx_valid_int;
wire      ln6_rx_valid_int;
wire      ln7_rx_valid_int;

wire            cfg_transmit_order;
assign          cfg_transmit_order = 1'b1;

    

ocx_dlx_rxdf rx (
 .ln0_rx_valid                  (ln0_rx_valid_int)
,.ln0_rx_data                   (ln0_rx_data)
,.ln0_rx_header                 (ln0_rx_header)
,.ln0_rx_slip                   (ln0_rx_slip)
,.ln1_rx_valid                  (ln1_rx_valid_int)
,.ln1_rx_data                   (ln1_rx_data)
,.ln1_rx_header                 (ln1_rx_header)
,.ln1_rx_slip                   (ln1_rx_slip)
,.ln2_rx_valid                  (ln2_rx_valid_int)
,.ln2_rx_data                   (ln2_rx_data)
,.ln2_rx_header                 (ln2_rx_header)
,.ln2_rx_slip                   (ln2_rx_slip)
,.ln3_rx_valid                  (ln3_rx_valid_int)
,.ln3_rx_data                   (ln3_rx_data)
,.ln3_rx_header                 (ln3_rx_header)
,.ln3_rx_slip                   (ln3_rx_slip)
,.ln4_rx_valid                  (ln4_rx_valid_int)
,.ln4_rx_data                   (ln4_rx_data)
,.ln4_rx_header                 (ln4_rx_header)
,.ln4_rx_slip                   (ln4_rx_slip)
,.ln5_rx_valid                  (ln5_rx_valid_int)
,.ln5_rx_data                   (ln5_rx_data)
,.ln5_rx_header                 (ln5_rx_header)
,.ln5_rx_slip                   (ln5_rx_slip)
,.ln6_rx_valid                  (ln6_rx_valid_int)
,.ln6_rx_data                   (ln6_rx_data)
,.ln6_rx_slip                   (ln6_rx_slip)
,.ln6_rx_header                 (ln6_rx_header)
,.ln7_rx_valid                  (ln7_rx_valid_int)
,.ln7_rx_data                   (ln7_rx_data)
,.ln7_rx_header                 (ln7_rx_header)
,.ln7_rx_slip                   (ln7_rx_slip)
,.dlx_tlx_flit_valid            (dlx_tlx_flit_valid)
,.dlx_tlx_flit                  (dlx_tlx_flit)
,.dlx_tlx_flit_crc_err          (dlx_tlx_flit_crc_err)
,.dlx_tlx_link_up               (dlx_tlx_link_up)
,.dlx_config_info               (dlx_config_info)
,.cfg_transmit_order            (cfg_transmit_order)
,.tx_rx_reset                   (tx_rx_reset)
,.train_ts2                     (train_ts2)
,.train_ts67                    (train_ts67)
,.rx_tx_retrain                 (rx_tx_retrain)
,.rx_tx_crc_error               (rx_tx_crc_error)
,.rx_tx_nack                    (rx_tx_nack)
,.rx_tx_tx_ack_rtn              (rx_tx_tx_ack_rtn)
,.rx_tx_rx_ack_inc              (rx_tx_rx_ack_inc)
,.rx_tx_tx_ack_ptr_vld          (rx_tx_tx_ack_ptr_vld)
,.rx_tx_tx_ack_ptr              (rx_tx_tx_ack_ptr)
,.ln0_rx_tx_last_byte_ts3       (ln0_rx_tx_last_byte_ts3)
,.ln1_rx_tx_last_byte_ts3       (ln1_rx_tx_last_byte_ts3)
,.ln2_rx_tx_last_byte_ts3       (ln2_rx_tx_last_byte_ts3)
,.ln3_rx_tx_last_byte_ts3       (ln3_rx_tx_last_byte_ts3)
,.rx_tx_tx_lane_swap            (rx_tx_tx_lane_swap)
,.rx_tx_deskew_done             (rx_tx_deskew_done)
,.tx_rx_training                (tx_rx_training)
,.tx_rx_phy_training            (tx_rx_phy_training)
,.tx_rx_disabled_rx_lanes       (tx_rx_disabled_rx_lanes)
,.rx_tx_pattern_a               (rx_tx_pattern_a)
,.rx_tx_pattern_b               (rx_tx_pattern_b)
,.rx_tx_lane_inverted           (rx_tx_lane_inverted)
,.rx_tx_sync                    (rx_tx_sync)
,.rx_tx_TS1                     (rx_tx_TS1)
,.rx_tx_TS2                     (rx_tx_TS2)
,.rx_tx_TS3                     (rx_tx_TS3)
,.rx_tx_block_lock              (rx_tx_block_lock)
,.rx_tx_linkup                  (rx_tx_linkup)
,.opt_gckn                      (opt_gckn)


);


ocx_dlx_txdf tx (
 .dlx_tlx_init_flit_depth       (dlx_tlx_init_flit_depth)
,.dlx_tlx_flit_credit           (dlx_tlx_flit_credit)
,.tlx_dlx_flit_valid            (tlx_dlx_flit_valid)
,.tlx_dlx_flit                  (tlx_dlx_flit)
,.ro_dlx_version                (ro_dlx_version)
,.dlx_l0_tx_data                (dlx_l0_tx_data)
,.dlx_l1_tx_data                (dlx_l1_tx_data)
,.dlx_l2_tx_data                (dlx_l2_tx_data)
,.dlx_l3_tx_data                (dlx_l3_tx_data)
,.dlx_l4_tx_data                (dlx_l4_tx_data)
,.dlx_l5_tx_data                (dlx_l5_tx_data)
,.dlx_l6_tx_data                (dlx_l6_tx_data)
,.dlx_l7_tx_data                (dlx_l7_tx_data)
,.dlx_l0_tx_header              (dlx_l0_tx_header)
,.dlx_l1_tx_header              (dlx_l1_tx_header)
,.dlx_l2_tx_header              (dlx_l2_tx_header)
,.dlx_l3_tx_header              (dlx_l3_tx_header)
,.dlx_l4_tx_header              (dlx_l4_tx_header)
,.dlx_l5_tx_header              (dlx_l5_tx_header)
,.dlx_l6_tx_header              (dlx_l6_tx_header)
,.dlx_l7_tx_header              (dlx_l7_tx_header)
,.dlx_l0_tx_seq                 (dlx_l0_tx_seq)
,.dlx_l1_tx_seq                 (dlx_l1_tx_seq)
,.dlx_l2_tx_seq                 (dlx_l2_tx_seq)
,.dlx_l3_tx_seq                 (dlx_l3_tx_seq)
,.dlx_l4_tx_seq                 (dlx_l4_tx_seq)
,.dlx_l5_tx_seq                 (dlx_l5_tx_seq)
,.dlx_l6_tx_seq                 (dlx_l6_tx_seq)
,.dlx_l7_tx_seq                 (dlx_l7_tx_seq)
,.cfg_transmit_order            (cfg_transmit_order)
,.pb_io_o0_rx_run_lane          (pb_io_o0_rx_run_lane)
,.io_pb_o0_rx_init_done         (io_pb_o0_rx_init_done)
,.tlx_dlx_debug_encode          (tlx_dlx_debug_encode)
,.tlx_dlx_debug_info            (tlx_dlx_debug_info)
,.rx_tx_tx_lane_swap            (rx_tx_tx_lane_swap)
,.rx_tx_crc_error               (rx_tx_crc_error)
,.rx_tx_retrain                 (rx_tx_retrain)
,.rx_tx_nack                    (rx_tx_nack)
,.rx_tx_tx_ack_rtn              (rx_tx_tx_ack_rtn)
,.rx_tx_rx_ack_inc              (rx_tx_rx_ack_inc)
,.rx_tx_tx_ack_ptr_vld          (rx_tx_tx_ack_ptr_vld)
,.rx_tx_tx_ack_ptr              (rx_tx_tx_ack_ptr)
,.tx_rx_reset                   (tx_rx_reset)
,.train_ts2                     (train_ts2)
,.train_ts67                    (train_ts67)
,.tx_rx_phy_training            (tx_rx_phy_training)
,.rx_tx_pattern_a               (rx_tx_pattern_a)
,.rx_tx_pattern_b               (rx_tx_pattern_b)
,.rx_tx_lane_inverted           (rx_tx_lane_inverted)
,.rx_tx_sync                    (rx_tx_sync)
,.rx_tx_TS1                     (rx_tx_TS1)
,.rx_tx_TS2                     (rx_tx_TS2)
,.rx_tx_TS3                     (rx_tx_TS3)
,.rx_tx_block_lock              (rx_tx_block_lock)
,.rx_tx_deskew_done             (rx_tx_deskew_done)
,.rx_tx_linkup                  (rx_tx_linkup)
,.ln0_rx_tx_last_byte_ts3       (ln0_rx_tx_last_byte_ts3)
,.ln1_rx_tx_last_byte_ts3       (ln1_rx_tx_last_byte_ts3)
,.ln2_rx_tx_last_byte_ts3       (ln2_rx_tx_last_byte_ts3)
,.ln3_rx_tx_last_byte_ts3       (ln3_rx_tx_last_byte_ts3)
,.dlx_reset                     (dlx_reset)
,.tx_rx_training                (tx_rx_training)
,.tx_rx_disabled_rx_lanes       (tx_rx_disabled_rx_lanes)
,.dlx_clk                       (opt_gckn)


);


ocx_dlx_xlx_if xlx_if (
 .clk_156_25MHz                 (clk_156_25MHz)
,.opt_gckn                      (opt_gckn)
,.ocde                          (ocde)
,.hb_gtwiz_reset_all_in         (hb_gtwiz_reset_all_in)
,.gtwiz_reset_all_out           (gtwiz_reset_all_out)
,.gtwiz_reset_rx_datapath_out   (gtwiz_reset_rx_datapath_out)
,.gtwiz_reset_tx_done_in        (gtwiz_reset_tx_done_in)
,.gtwiz_reset_rx_done_in        (gtwiz_reset_rx_done_in)
,.gtwiz_buffbypass_tx_done_in   (gtwiz_buffbypass_tx_done_in)
,.gtwiz_buffbypass_rx_done_in   (gtwiz_buffbypass_rx_done_in)
,.gtwiz_userclk_tx_active_in    (gtwiz_userclk_tx_active_in)
,.gtwiz_userclk_rx_active_in    (gtwiz_userclk_rx_active_in)
,.dlx_reset                     (dlx_reset)
,.pb_io_o0_rx_run_lane          (pb_io_o0_rx_run_lane)
,.io_pb_o0_rx_init_done         (io_pb_o0_rx_init_done)
,.send_first                    (send_first)
,.ln0_rx_valid_in               (ln0_rx_valid)
,.ln1_rx_valid_in               (ln1_rx_valid)
,.ln2_rx_valid_in               (ln2_rx_valid)
,.ln3_rx_valid_in               (ln3_rx_valid)
,.ln4_rx_valid_in               (ln4_rx_valid)
,.ln5_rx_valid_in               (ln5_rx_valid)
,.ln6_rx_valid_in               (ln6_rx_valid)
,.ln7_rx_valid_in               (ln7_rx_valid)
,.ln0_rx_valid_out              (ln0_rx_valid_int)
,.ln1_rx_valid_out              (ln1_rx_valid_int)
,.ln2_rx_valid_out              (ln2_rx_valid_int)
,.ln3_rx_valid_out              (ln3_rx_valid_int)
,.ln4_rx_valid_out              (ln4_rx_valid_int)
,.ln5_rx_valid_out              (ln5_rx_valid_int)
,.ln6_rx_valid_out              (ln6_rx_valid_int)
,.ln7_rx_valid_out              (ln7_rx_valid_int)
);

endmodule