data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v
1: b'%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:16: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_19, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:17: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(net_19, net_0, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:18: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(gnd, net_0, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:19: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(gnd, y, net_0);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:20: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_0, net_11, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:21: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_11, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:22: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(net_11, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:23: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(y, vdd, net_0);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:35: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_5, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:36: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_5, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:37: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:38: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(y, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:51: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_7, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:52: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_7, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:53: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_7, y, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:54: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, net_35, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:55: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_35, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:56: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(y, vdd, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:70: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_7, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:71: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_7, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:72: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_7, y, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:73: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(net_7, y, d);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:74: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, net_35, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:75: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_35, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:76: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, net_34, d);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:77: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_34, vdd, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:89: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_3, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:90: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_4, ab);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:91: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_3, net_5, bb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:92: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(net_4, net_5, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:93: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(gnd, bb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:94: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, ab, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:95: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, y, net_5);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:96: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_5, net_7, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:97: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_7, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:98: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(net_5, net_8, bb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:99: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_8, vdd, ab);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:100: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(bb, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:101: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(ab, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCgoto.v:102: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_6(y, vdd, net_5);\n          ^~~~~~\n%Error: Exiting due to 40 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module muddlib07__a2o1_1x(a, b, c, y);
  input a;
  input b;
  input c;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_0, net_11, net_19;

  tranif1 nmos_0(gnd, net_19, a);
  tranif1 nmos_1(net_19, net_0, b);
  tranif1 nmos_2(gnd, net_0, c);
  tranif1 nmos_3(gnd, y, net_0);
  tranif0 pmos_0(net_0, net_11, c);
  tranif0 pmos_1(net_11, vdd, b);
  tranif0 pmos_2(net_11, vdd, a);
  tranif0 pmos_3(y, vdd, net_0);
endmodule
module muddlib07__a2o1_1x(a, b, c, y);

  input a;
  input b;
  input c;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_0, net_11, net_19;

  tranif1 nmos_0(gnd, net_19, a);
  tranif1 nmos_1(net_19, net_0, b);
  tranif1 nmos_2(gnd, net_0, c);
  tranif1 nmos_3(gnd, y, net_0);
  tranif0 pmos_0(net_0, net_11, c);
  tranif0 pmos_1(net_11, vdd, b);
  tranif0 pmos_2(net_11, vdd, a);
  tranif0 pmos_3(y, vdd, net_0);
endmodule