data/full_repos/permissive/213361049/Multiplier.v
 line:16: before: "20"
1: b"%Error: data/full_repos/permissive/213361049/Multiplier.v:6: Duplicate declaration of signal: 'O'\n                                                           : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg [7:0] O;\n          ^\n        data/full_repos/permissive/213361049/Multiplier.v:4: ... Location of original declaration\n         output [7:0] O, output Finish\n                      ^\n%Error: data/full_repos/permissive/213361049/Multiplier.v:7: Duplicate declaration of signal: 'Finish'\nwire Finish;  \n     ^~~~~~\n        data/full_repos/permissive/213361049/Multiplier.v:4: ... Location of original declaration\n         output [7:0] O, output Finish\n                                ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mult_4x4(
         input reset,start, 
         input[3:0] A,B, 
         output [7:0] O, output Finish
             );
reg [7:0] O;
wire Finish;  
wire Phi0,Phi1;
wire m1,m2,m3,m4;

reg[3:0] State;

reg [8:0] ACC;

nand u0(m1,start,m2);
buf #20 u1(m2,m1);
buf #10 u2(Phi0,m1);
not #2 u5(m4,Phi0);
assign m3=~m1; 
and #2 u4(Phi1,m3,m4);
assign Finish = (State==9)? 1'b1:1'b0;

always @(posedge Phi0 or posedge Phi1 or posedge reset)
begin
 if(reset) begin
 State <= 0; 
 ACC <= 0; 
 O <= 0; 
 end
 else if((Phi0==1'b1) || (Phi1==1'b1)) begin
 if(State==0)
 begin
 ACC[8:4] <= 5'b00000;
 ACC[3:0] <= A;
 State <= 1;
 end
 else if(State==1 || State == 3 || State ==5 || State ==7) 

 begin
 if(ACC[0] == 1'b1) begin
 ACC[8:4] <= {1'b0,ACC[7:4]} + B; 
 State <= State + 1;
 end
 else
 begin
 ACC <= {1'b0,ACC[8:1]};
 State <= State + 2;
 end
 end
 else if(State==2 || State == 4 || State ==6 || State ==8) 

 begin
 ACC <= {1'b0,ACC[8:1]};
 State <= State + 1;
 end 
 else if(State == 9) begin
 State <= 0;
 O <= ACC[7:0]; 
 end
 end
end 
 
endmodule
module mult_4x4(
         input reset,start, 
         input[3:0] A,B, 
         output [7:0] O, output Finish
             );

reg [7:0] O;
wire Finish;  
wire Phi0,Phi1;
wire m1,m2,m3,m4;

reg[3:0] State;

reg [8:0] ACC;

nand u0(m1,start,m2);
buf #20 u1(m2,m1);
buf #10 u2(Phi0,m1);
not #2 u5(m4,Phi0);
assign m3=~m1; 
and #2 u4(Phi1,m3,m4);
assign Finish = (State==9)? 1'b1:1'b0;

always @(posedge Phi0 or posedge Phi1 or posedge reset)
begin
 if(reset) begin
 State <= 0; 
 ACC <= 0; 
 O <= 0; 
 end
 else if((Phi0==1'b1) || (Phi1==1'b1)) begin
 if(State==0)
 begin
 ACC[8:4] <= 5'b00000;
 ACC[3:0] <= A;
 State <= 1;
 end
 else if(State==1 || State == 3 || State ==5 || State ==7) 

 begin
 if(ACC[0] == 1'b1) begin
 ACC[8:4] <= {1'b0,ACC[7:4]} + B; 
 State <= State + 1;
 end
 else
 begin
 ACC <= {1'b0,ACC[8:1]};
 State <= State + 2;
 end
 end
 else if(State==2 || State == 4 || State ==6 || State ==8) 

 begin
 ACC <= {1'b0,ACC[8:1]};
 State <= State + 1;
 end 
 else if(State == 9) begin
 State <= 0;
 O <= ACC[7:0]; 
 end
 end
end 
 
endmodule