data/full_repos/permissive/174263347/JamaOneChip/hdl/vga.v
data/verilator_xmls/66e0ae9c-46d6-4e72-81ca-83f49c2a9003.xml
module vga ( clk, video, hsync, vsync, dVga, aVga, wrVga, wrVgaReq );
    

    input   clk;
    input   hsync, vsync;
    output  wrVga;
    input   wrVgaReq;
    input   video;
    output  [7:0] dVga;
    output  [15:0] aVga;


    reg     [6:0] h;
    reg     [8:0] v;
    reg     [3:0] pixel;
    reg     [7:0] shifter;







always @ ( posedge clk or posedge hsync)
begin
    if (hsync)
        pixel <= 0;
    else 
        pixel <= pixel + 1;
end

assign wrVga = (pixel == 7);






     
always @ ( posedge clk or posedge hsync)
begin
    if (hsync)
        h <= 0;
    else if (wrVgaReq)
        h <= h + 1;
end

assign aVga[6:0] = h;







always @ ( posedge hsync or posedge vsync)
begin
    if (vsync)
        v <= 0;
    else if (v != 9'b111111111)
        v <= v + 1;
end

assign aVga[15:7] = v;







always @ ( posedge clk )
begin
    shifter <= { shifter[6:0], video };
end

assign dVga = shifter;

endmodule
module vga ( clk, video, hsync, vsync, dVga, aVga, wrVga, wrVgaReq );

    

    input   clk;
    input   hsync, vsync;
    output  wrVga;
    input   wrVgaReq;
    input   video;
    output  [7:0] dVga;
    output  [15:0] aVga;


    reg     [6:0] h;
    reg     [8:0] v;
    reg     [3:0] pixel;
    reg     [7:0] shifter;







always @ ( posedge clk or posedge hsync)
begin
    if (hsync)
        pixel <= 0;
    else 
        pixel <= pixel + 1;
end

assign wrVga = (pixel == 7);






     
always @ ( posedge clk or posedge hsync)
begin
    if (hsync)
        h <= 0;
    else if (wrVgaReq)
        h <= h + 1;
end

assign aVga[6:0] = h;







always @ ( posedge hsync or posedge vsync)
begin
    if (vsync)
        v <= 0;
    else if (v != 9'b111111111)
        v <= v + 1;
end

assign aVga[15:7] = v;







always @ ( posedge clk )
begin
    shifter <= { shifter[6:0], video };
end

assign dVga = shifter;

endmodule