data/full_repos/permissive/140493787/src/hdl/pi_estimator_vga.v
 line:80: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/140493787/src/hdl/pi_estimator_vga.v:74: Unsupported: Ignoring delay on this delayed statement.\n      forever #(CLK_PER / 2) clk <= ~clk;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/140493787/src/hdl/pi_estimator_vga.v:78: syntax error, unexpected \'@\'\n      reset <= 1; @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/140493787/src/hdl/pi_estimator_vga.v:79: syntax error, unexpected \'@\'\n      reset <= 0; @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/140493787/src/hdl/pi_estimator_vga.v:80: syntax error, unexpected \'@\'\n      repeat (1680400) @(posedge clk);\n                       ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pi_estimator_vga_testbench ();
   wire HS, VS, vidSel;
   reg  clk, reset;

   pi_estimator_vga dut (
      .HS(HS),
      .VS(VS),
      .vidSel(vidSel),
      .clk25(clk),
      .reset(reset)
   );

   parameter CLK_PER = 40;
   initial begin
      clk <= 1;
      forever #(CLK_PER / 2) clk <= ~clk;
   end

   initial begin
      reset <= 1; @(posedge clk);
      reset <= 0; @(posedge clk);
      repeat (1680400) @(posedge clk);
      $stop;
   end
endmodule
module pi_estimator_vga_testbench ();

   wire HS, VS, vidSel;
   reg  clk, reset;

   pi_estimator_vga dut (
      .HS(HS),
      .VS(VS),
      .vidSel(vidSel),
      .clk25(clk),
      .reset(reset)
   );

   parameter CLK_PER = 40;
   initial begin
      clk <= 1;
      forever #(CLK_PER / 2) clk <= ~clk;
   end

   initial begin
      reset <= 1; @(posedge clk);
      reset <= 0; @(posedge clk);
      repeat (1680400) @(posedge clk);
      $stop;
   end
endmodule