data/full_repos/permissive/169380436/mem.v
data/verilator_xmls/016bb592-7b4b-4f6b-a5bb-03b0d8a9f452.xml
module mem(
    input clk,
    input [32:0] mem,
    output [32:0] wave
);

assign wave = mem;

endmodule
module mem(
    input clk,
    input [32:0] mem,
    output [32:0] wave
);


assign wave = mem;

endmodule