data/full_repos/permissive/104784866/CBox/Verilog/src/CBox.v
1: b"%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox.v:117: Cannot find file containing module: 'FromChannelBusToCLBJunction'\n   FromChannelBusToCLBJunction#(DIMENSION, CH_UP_WIDTH + CH_DN_WIDTH, DIMENSION_WIDTH) inst(\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104784866/CBox/Verilog/src,data/full_repos/permissive/104784866/FromChannelBusToCLBJunction\n             data/full_repos/permissive/104784866/CBox/Verilog/src,data/full_repos/permissive/104784866/FromChannelBusToCLBJunction.v\n             data/full_repos/permissive/104784866/CBox/Verilog/src,data/full_repos/permissive/104784866/FromChannelBusToCLBJunction.sv\n             FromChannelBusToCLBJunction\n             FromChannelBusToCLBJunction.v\n             FromChannelBusToCLBJunction.sv\n             obj_dir/FromChannelBusToCLBJunction\n             obj_dir/FromChannelBusToCLBJunction.v\n             obj_dir/FromChannelBusToCLBJunction.sv\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox.v:130: Cannot find file containing module: 'FromCLBToChannelBusJunction'\n   FromCLBToChannelBusJunction#(DIMENSION, CH_UP_WIDTH, CH_DN_WIDTH, DIMENSION_WIDTH) inst(\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module CBox#(

		parameter UID = 0,

		parameter DIMENSION = 4,

		parameter CH_UP_WIDTH = 2,

		parameter CH_DN_WIDTH = 2,

		parameter CLB_IN_WIDTH = 2,

		parameter CLB_OUT_WIDTH = 2,

		parameter CLB_WIDTH_WIDTH = 2,

		parameter UID_WIDTH = 16,

		parameter DIMENSION_WIDTH = 2
	) (

		mode,
		c_clk,
		c_bus,
		c_uid,
		c_dimension,


		ch_up_n,
		ch_up_s,
		ch_dn_n,
		ch_dn_s,


		clb_in,
		clb_out
	);


	parameter CONFIG_WORD_WIDTH = (DIMENSION*(CH_UP_WIDTH+CH_DN_WIDTH))+CLB_WIDTH_WIDTH;


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [UID_WIDTH-1:0] c_uid;
	input [DIMENSION_WIDTH-1:0] c_dimension;


	output [CH_UP_WIDTH-1:0] ch_up_n;
	input [CH_UP_WIDTH-1:0] ch_up_s;
	input [CH_DN_WIDTH-1:0] ch_dn_n;
	output [CH_DN_WIDTH-1:0] ch_dn_s;


	output [CLB_IN_WIDTH-1:0] clb_in;
	input [CLB_OUT_WIDTH-1:0] clb_out;

	wire [CH_UP_WIDTH-1:0] w_ch_up [0:CLB_OUT_WIDTH];
	wire [CH_DN_WIDTH-1:0] w_ch_dn [0:CLB_OUT_WIDTH];


	genvar i;
	generate

		for(i = 0; i < CLB_IN_WIDTH; i = i+1) begin : FromChannelBusToCLBJunctionGen
			wire filteredClk = c_clk && (i == `C_BUS_JN_ADDR) && (UID == c_uid);
			FromChannelBusToCLBJunction#(DIMENSION, CH_UP_WIDTH + CH_DN_WIDTH, DIMENSION_WIDTH) inst(
				.mode(mode),
				.c_clk(filteredClk),
				.c_bus({`C_BUS_CLB_DN_JUNCTION, `C_BUS_CLB_UP_JUNCTION}),
				.c_dimension(c_dimension),

				.ch({ch_dn_n, w_ch_up[0]}),
				.clb_in(clb_in[i])
			);
		end

		for(i = 0; i < CLB_OUT_WIDTH; i = i+1) begin : FromCLBToChannelBusJunctionGen
			wire filteredClk = c_clk && ((i + CLB_IN_WIDTH) == `C_BUS_JN_ADDR) && (UID == c_uid);
			FromCLBToChannelBusJunction#(DIMENSION, CH_UP_WIDTH, CH_DN_WIDTH, DIMENSION_WIDTH) inst(
				.mode(mode),
				.c_clk(filteredClk),
				.c_bus({`C_BUS_CLB_DN_JUNCTION, `C_BUS_CLB_UP_JUNCTION}),
				.c_dimension(c_dimension),

				.ch_up_n(w_ch_up[i]),
				.ch_up_s(w_ch_up[i+1]),
				.ch_dn_n(w_ch_dn[i]),
				.ch_dn_s(w_ch_dn[i+1]),
				.clb_out(clb_out[i])
			);
		end
	endgenerate


	assign ch_up_n = w_ch_up[0];
	assign w_ch_up[CLB_OUT_WIDTH] = ch_up_s;
	assign w_ch_dn[0] = ch_dn_n;
	assign ch_dn_s = w_ch_dn[CLB_OUT_WIDTH];

endmodule
module CBox#(

		parameter UID = 0,

		parameter DIMENSION = 4,

		parameter CH_UP_WIDTH = 2,

		parameter CH_DN_WIDTH = 2,

		parameter CLB_IN_WIDTH = 2,

		parameter CLB_OUT_WIDTH = 2,

		parameter CLB_WIDTH_WIDTH = 2,

		parameter UID_WIDTH = 16,

		parameter DIMENSION_WIDTH = 2
	) (

		mode,
		c_clk,
		c_bus,
		c_uid,
		c_dimension,


		ch_up_n,
		ch_up_s,
		ch_dn_n,
		ch_dn_s,


		clb_in,
		clb_out
	);



	parameter CONFIG_WORD_WIDTH = (DIMENSION*(CH_UP_WIDTH+CH_DN_WIDTH))+CLB_WIDTH_WIDTH;


	input mode;
	input c_clk;
	input [CONFIG_WORD_WIDTH-1:0] c_bus;
	input [UID_WIDTH-1:0] c_uid;
	input [DIMENSION_WIDTH-1:0] c_dimension;


	output [CH_UP_WIDTH-1:0] ch_up_n;
	input [CH_UP_WIDTH-1:0] ch_up_s;
	input [CH_DN_WIDTH-1:0] ch_dn_n;
	output [CH_DN_WIDTH-1:0] ch_dn_s;


	output [CLB_IN_WIDTH-1:0] clb_in;
	input [CLB_OUT_WIDTH-1:0] clb_out;

	wire [CH_UP_WIDTH-1:0] w_ch_up [0:CLB_OUT_WIDTH];
	wire [CH_DN_WIDTH-1:0] w_ch_dn [0:CLB_OUT_WIDTH];


	genvar i;
	generate

		for(i = 0; i < CLB_IN_WIDTH; i = i+1) begin : FromChannelBusToCLBJunctionGen
			wire filteredClk = c_clk && (i == `C_BUS_JN_ADDR) && (UID == c_uid);
			FromChannelBusToCLBJunction#(DIMENSION, CH_UP_WIDTH + CH_DN_WIDTH, DIMENSION_WIDTH) inst(
				.mode(mode),
				.c_clk(filteredClk),
				.c_bus({`C_BUS_CLB_DN_JUNCTION, `C_BUS_CLB_UP_JUNCTION}),
				.c_dimension(c_dimension),

				.ch({ch_dn_n, w_ch_up[0]}),
				.clb_in(clb_in[i])
			);
		end

		for(i = 0; i < CLB_OUT_WIDTH; i = i+1) begin : FromCLBToChannelBusJunctionGen
			wire filteredClk = c_clk && ((i + CLB_IN_WIDTH) == `C_BUS_JN_ADDR) && (UID == c_uid);
			FromCLBToChannelBusJunction#(DIMENSION, CH_UP_WIDTH, CH_DN_WIDTH, DIMENSION_WIDTH) inst(
				.mode(mode),
				.c_clk(filteredClk),
				.c_bus({`C_BUS_CLB_DN_JUNCTION, `C_BUS_CLB_UP_JUNCTION}),
				.c_dimension(c_dimension),

				.ch_up_n(w_ch_up[i]),
				.ch_up_s(w_ch_up[i+1]),
				.ch_dn_n(w_ch_dn[i]),
				.ch_dn_s(w_ch_dn[i+1]),
				.clb_out(clb_out[i])
			);
		end
	endgenerate


	assign ch_up_n = w_ch_up[0];
	assign w_ch_up[CLB_OUT_WIDTH] = ch_up_s;
	assign w_ch_dn[0] = ch_dn_n;
	assign ch_dn_s = w_ch_dn[CLB_OUT_WIDTH];

endmodule