data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/mips.v
1: b"%Error: data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/mips.v:57: Cannot find file containing module: 'controller'\n    controller c(clk,reset,opD,functD,flushE,cmpD,\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/controller\n             data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/controller.v\n             data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/controller.sv\n             controller\n             controller.v\n             controller.sv\n             obj_dir/controller\n             obj_dir/controller.v\n             obj_dir/controller.sv\n%Error: data/full_repos/permissive/169258653/pipeline/MIPS_pipeline_32bit/MIPS_pipeline_32bit.srcs/sources_1/new/mips.v:64: Cannot find file containing module: 'datapath'\n    datapath dp(clk,reset,memtoregE,memtoregM,memtoregW,\n    ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mips(
    input clk,reset,
    output [31:0] pcF,
    input [31:0] instrF,
    output memwriteM,
    output [31:0] aluoutM,writedataM,
    input [31:0] readdataM,
    input [2:0] lsrc,
    output reg [15:0] led,
    input beep,
    input [9:0] SW,
    output [31:0] t,
    output [7:0] disop    
    );
    
    wire [5:0] opD,functD;
    wire [1:0] regdstE;
    wire pcsrcD,memtoregE,memtoregM,
         memtoregW,regwriteE,regwriteM,regwriteW;
    wire [1:0] alusrcbE,alusrcaE;
         
    wire [3:0] alucontrolE;
    wire flushE,cmpD;
    
    wire [1:0] jumpD;
    wire branchD;
    
    wire [15:0] ledc,leddp;
    
    wire [15:0] BEEP;
    
    wire extend;
    wire [2:0] cmpcontrolD;
     
    controller c(clk,reset,opD,functD,flushE,cmpD,
                 memtoregE,memtoregM,memtoregW,memwriteM,
                 pcsrcD,branchD,alusrcaE,alusrcbE,regdstE,regwriteE,
                 regwriteM,regwriteW,jumpD,alucontrolE,
                 lsrc,ledc,beep,
                 extend,cmpcontrolD);
                    
    datapath dp(clk,reset,memtoregE,memtoregM,memtoregW,
                pcsrcD,branchD,alusrcaE,alusrcbE,regdstE,regwriteE,
                regwriteM,regwriteW,jumpD,alucontrolE,
                cmpD,pcF,instrF,aluoutM,writedataM,
                readdataM,opD,functD,flushE,
                leddp,beep,
                extend,cmpcontrolD,
                SW,t,disop);
                 

    assign BEEP={beep,beep,beep,beep,
                 beep,beep,beep,beep,
                 beep,beep,beep,beep,
                 beep,beep,beep,beep}; 

    always@(*)
    case(lsrc)

    3'b0:led<=ledc;
    3'b1:led<=ledc;
    3'b10:led<=ledc;
    3'b11:led<=ledc;
    3'b100:led<=ledc;

    3'b101:led<=leddp;

    default:led<=BEEP;
    endcase
    
endmodule
module mips(
    input clk,reset,
    output [31:0] pcF,
    input [31:0] instrF,
    output memwriteM,
    output [31:0] aluoutM,writedataM,
    input [31:0] readdataM,
    input [2:0] lsrc,
    output reg [15:0] led,
    input beep,
    input [9:0] SW,
    output [31:0] t,
    output [7:0] disop    
    );

    
    wire [5:0] opD,functD;
    wire [1:0] regdstE;
    wire pcsrcD,memtoregE,memtoregM,
         memtoregW,regwriteE,regwriteM,regwriteW;
    wire [1:0] alusrcbE,alusrcaE;
         
    wire [3:0] alucontrolE;
    wire flushE,cmpD;
    
    wire [1:0] jumpD;
    wire branchD;
    
    wire [15:0] ledc,leddp;
    
    wire [15:0] BEEP;
    
    wire extend;
    wire [2:0] cmpcontrolD;
     
    controller c(clk,reset,opD,functD,flushE,cmpD,
                 memtoregE,memtoregM,memtoregW,memwriteM,
                 pcsrcD,branchD,alusrcaE,alusrcbE,regdstE,regwriteE,
                 regwriteM,regwriteW,jumpD,alucontrolE,
                 lsrc,ledc,beep,
                 extend,cmpcontrolD);
                    
    datapath dp(clk,reset,memtoregE,memtoregM,memtoregW,
                pcsrcD,branchD,alusrcaE,alusrcbE,regdstE,regwriteE,
                regwriteM,regwriteW,jumpD,alucontrolE,
                cmpD,pcF,instrF,aluoutM,writedataM,
                readdataM,opD,functD,flushE,
                leddp,beep,
                extend,cmpcontrolD,
                SW,t,disop);
                 

    assign BEEP={beep,beep,beep,beep,
                 beep,beep,beep,beep,
                 beep,beep,beep,beep,
                 beep,beep,beep,beep}; 

    always@(*)
    case(lsrc)

    3'b0:led<=ledc;
    3'b1:led<=ledc;
    3'b10:led<=ledc;
    3'b11:led<=ledc;
    3'b100:led<=ledc;

    3'b101:led<=leddp;

    default:led<=BEEP;
    endcase
    
endmodule