data/full_repos/permissive/200104480/Processor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/200104480/Processor.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:440: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'singleBit\' generates 1 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.A.ze\n assign dataOut = 32\'b0 + singleBit;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/200104480/Processor.v:361: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'dataIn\' generates 16 bits.\n                                                                    : ... In instance ProcessorTest1.DUT.ZE\n assign dataOut = 32\'b0 + dataIn;\n                        ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU(input [31:0] A,
			input [31:0] B,
			input [2:0] F,
			output [31:0] Y);

	wire [31:0] notB;
	wire [31:0] mx1out;
	wire [31:0] orout;
	wire [31:0] andout;
	wire [31:0] S;
	wire Cout;
	wire [31:0] zeroex;

	assign notB = ~B;
	mux2to1 mx1(F[2], B, notB, mx1out);
	assign orout = A | mx1out;
	assign andout = A & mx1out;
	adder32 add(A, mx1out, F[2], S, Cout);
	zeroExtender ze(S[31], zeroex);
	mux4to1 mx2(F[1:0], andout, orout, S, zeroex, Y);
endmodule
module ALU(input [31:0] A,
			input [31:0] B,
			input [2:0] F,
			output [31:0] Y);


	wire [31:0] notB;
	wire [31:0] mx1out;
	wire [31:0] orout;
	wire [31:0] andout;
	wire [31:0] S;
	wire Cout;
	wire [31:0] zeroex;

	assign notB = ~B;
	mux2to1 mx1(F[2], B, notB, mx1out);
	assign orout = A | mx1out;
	assign andout = A & mx1out;
	adder32 add(A, mx1out, F[2], S, Cout);
	zeroExtender ze(S[31], zeroex);
	mux4to1 mx2(F[1:0], andout, orout, S, zeroex, Y);
endmodule