data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:16: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window,data/full_repos/permissive/214858095/test_exec.svh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window,data/full_repos/permissive/214858095/test_exec.svh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window,data/full_repos/permissive/214858095/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:23: Cannot find include file: rfnoc_block_window_regs.vh\n  `include "rfnoc_block_window_regs.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:18: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgTestExec::*;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:73: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);\n                                               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:76: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t  chdr_word_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:77: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::item_t       item_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:78: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(CHDR_W, ITEM_W)::item_queue_t item_queue_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:192: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test($sformatf("Test registers, port %0d", port), 10us);\n                                                                 ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:195: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(value == MAX_WINDOW_SIZE, "REG_WINDOW_MAX_SIZE reports incorrect value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:195: syntax error, unexpected \',\'\n    `ASSERT_ERROR(value == MAX_WINDOW_SIZE, "REG_WINDOW_MAX_SIZE reports incorrect value");\n                                          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:200: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(value == expected, "REG_WINDOW_SIZE did not update");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:200: syntax error, unexpected \',\'\n    `ASSERT_ERROR(value == expected, "REG_WINDOW_SIZE did not update");\n                                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:205: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(value == expected, "REG_WINDOW_SIZE did not update");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:205: syntax error, unexpected \',\'\n    `ASSERT_ERROR(value == expected, "REG_WINDOW_SIZE did not update");\n                                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:219: syntax error, unexpected IDENTIFIER\n    item_t coefficients[$];\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:230: syntax error, unexpected IDENTIFIER\n      item_t coeff;\n             ^~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:232: Unsupported or unknown PLI call: $urandom\n      coeff = $urandom();\n              ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:247: syntax error, unexpected IDENTIFIER\n      item_t payload[$];\n             ^~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:249: Unsupported: empty queues ("{ }")\n      payload = {};\n                ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:251: Unsupported or unknown PLI call: $urandom\n        payload.push_back($urandom());\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:259: syntax error, unexpected IDENTIFIER\n      item_t sent[$], received[$], expected[$];\n             ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:273: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:274: syntax error, unexpected \',\'\n        expected.size() == received.size(), \n                                          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:280: Define or directive not defined: \'`ASSERT_ERROR\'\n        `ASSERT_ERROR(\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:281: syntax error, unexpected \',\'\n          received[i] == expected[i], \n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:303: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test("Test random", 10ms);\n                                   ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:313: Unsupported or unknown PLI call: $urandom_range\n      window_size = $urandom_range(1, MAX_WINDOW_SIZE);\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:314: Unsupported or unknown PLI call: $urandom_range\n      packet_len  = $urandom_range(1, SPP);\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:318: Unsupported or unknown PLI call: $urandom_range\n      num_packets = $urandom_range(1, 2*packets_per_window);\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:330: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test("Test directed", 100us);\n                                     ^~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:347: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test("Test back pressure", 1ms);\n                                          ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:358: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test("Test underflow", 1ms);\n                                      ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:383: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test("Flush block then reset it", 10us);\n                                                 ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:391: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test("Verify Block Info", 2us);\n                                         ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:392: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:392: syntax error, unexpected \',\'\n    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");\n                                                 ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:393: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:393: syntax error, unexpected \',\'\n    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");\n                                                          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:394: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:394: syntax error, unexpected \',\'\n    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");\n                                                          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:395: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/blocks/rfnoc_block_window/rfnoc_block_window_tb.sv:395: syntax error, unexpected \',\'\n    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");\n                                           ^\n%Error: Exiting due to 42 error(s)\n'
module rfnoc_block_window_tb;

  `include "test_exec.svh"

  import PkgTestExec::*;
  import PkgChdrUtils::*;
  import PkgRfnocBlockCtrlBfm::*;
  import PkgRfnocItemUtils::*;

  `include "rfnoc_block_window_regs.vh"





  localparam [31:0] NOC_ID          = 32'hD0530000;
  localparam [ 9:0] THIS_PORTID     = 10'h123;
  localparam int    CHDR_W          = 64;
  localparam int    MTU             = 10;
  localparam int    NUM_PORTS       = 2;
  localparam int    NUM_PORTS_I     = NUM_PORTS;
  localparam int    NUM_PORTS_O     = NUM_PORTS;
  localparam int    ITEM_W          = 32;
  localparam int    SPP             = 256;
  localparam int    PKT_SIZE_BYTES  = SPP * (ITEM_W/8);
  localparam int    STALL_PROB      = 25;
  localparam real   CHDR_CLK_PER    = 5.0;
  localparam real   CTRL_CLK_PER    = 8.0;
  localparam real   CE_CLK_PER      = 4.0;
  localparam int    MAX_WINDOW_SIZE = 128;





  bit rfnoc_chdr_clk;
  bit rfnoc_ctrl_clk;
  bit ce_clk;

  sim_clock_gen #(CHDR_CLK_PER) rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
  sim_clock_gen #(CTRL_CLK_PER) rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
  sim_clock_gen #(CE_CLK_PER) ce_clk_gen (.clk(ce_clk), .rst());






  RfnocBackendIf backend (rfnoc_chdr_clk, rfnoc_ctrl_clk);


  AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, 1'b0);
  AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, 1'b0);


  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS_I] (rfnoc_chdr_clk, 1'b0);
  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS_O] (rfnoc_chdr_clk, 1'b0);


  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);


  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t  chdr_word_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_t       item_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_queue_t item_queue_t;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_bfm_input_connections
    initial begin
      blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
    end
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_bfm_output_connections
    initial begin
      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
    end
  end






  logic [CHDR_W*NUM_PORTS_I-1:0] s_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tready;


  logic [CHDR_W*NUM_PORTS_O-1:0] m_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tready;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_dut_input_connections

    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_dut_output_connections

    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
  end

  rfnoc_block_window #(
    .THIS_PORTID         (THIS_PORTID),
    .CHDR_W              (CHDR_W),
    .MTU                 (MTU),
    .NUM_PORTS           (NUM_PORTS),
    .MAX_WINDOW_SIZE     (MAX_WINDOW_SIZE)
  ) dut (
    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
    .ce_clk              (ce_clk),
    .rfnoc_core_config   (backend.cfg),
    .rfnoc_core_status   (backend.sts),
    .s_rfnoc_chdr_tdata  (s_rfnoc_chdr_tdata),
    .s_rfnoc_chdr_tlast  (s_rfnoc_chdr_tlast),
    .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
    .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
    .m_rfnoc_chdr_tdata  (m_rfnoc_chdr_tdata),
    .m_rfnoc_chdr_tlast  (m_rfnoc_chdr_tlast),
    .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
    .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
    .s_rfnoc_ctrl_tdata  (m_ctrl.tdata),
    .s_rfnoc_ctrl_tlast  (m_ctrl.tlast),
    .s_rfnoc_ctrl_tvalid (m_ctrl.tvalid),
    .s_rfnoc_ctrl_tready (m_ctrl.tready),
    .m_rfnoc_ctrl_tdata  (s_ctrl.tdata),
    .m_rfnoc_ctrl_tlast  (s_ctrl.tlast),
    .m_rfnoc_ctrl_tvalid (s_ctrl.tvalid),
    .m_rfnoc_ctrl_tready (s_ctrl.tready)
  );






  task automatic write_reg(int port, bit [19:0] addr, bit [31:0] value);
    blk_ctrl.reg_write(port * (2**WINDOW_ADDR_W) + addr, value);
  endtask : write_reg

  task automatic read_reg(int port, bit [19:0] addr, output logic [31:0] value);
    blk_ctrl.reg_read(port * (2**WINDOW_ADDR_W) + addr, value);
  endtask : read_reg









  function bit [31:0] mult_rc(bit signed [15:0] real_data, bit signed [31:0] complex_data);
    bit [47:0] temp;
    bit [31:0] result;
    temp = (real_data * signed'(complex_data[31:16])) >> 15;
    result[31:16] = temp;
    temp = (real_data * signed'(complex_data[15: 0])) >> 15;
    result[15: 0] = temp;
    return result;
  endfunction : mult_rc



  task automatic test_registers(int port);
    int unsigned value, expected;

    test.start_test($sformatf("Test registers, port %0d", port), 10us);

    read_reg(port, REG_WINDOW_MAX_SIZE, value);
    `ASSERT_ERROR(value == MAX_WINDOW_SIZE, "REG_WINDOW_MAX_SIZE reports incorrect value");

    expected = 2**$clog2(MAX_WINDOW_SIZE+1)-1;
    write_reg(port, REG_WINDOW_SIZE, expected);
    read_reg(port, REG_WINDOW_SIZE, value);
    `ASSERT_ERROR(value == expected, "REG_WINDOW_SIZE did not update");

    expected = 0;
    write_reg(port, REG_WINDOW_SIZE, expected);
    read_reg(port, REG_WINDOW_SIZE, value);
    `ASSERT_ERROR(value == expected, "REG_WINDOW_SIZE did not update");

    test.end_test();
  endtask : test_registers









  task automatic test_window(int port, int window_size, int packet_len, int num_packets);
    item_t coefficients[$];
    int coeff_index;
    mailbox #(item_queue_t) packets = new();

    $display("Testing: window_size=%04d, packet_len=%04d, num_packets=%04d",
      window_size, packet_len, num_packets);

    write_reg(port, REG_WINDOW_SIZE, window_size);


    for (int count=0; count < window_size; count++) begin
      item_t coeff;

      coeff = $urandom();
      coefficients.push_back(coeff);


      if (count == window_size-1)
        write_reg(port, REG_LOAD_COEFF_LAST, coeff);
      else
        write_reg(port, REG_LOAD_COEFF, coeff);
    end


    coeff_index = 0;


    for (int packet_count = 0; packet_count < num_packets; packet_count++) begin
      item_t payload[$];

      payload = {};
      for (int sample_count = 0; sample_count < packet_len; sample_count++) begin
        payload.push_back($urandom());
      end
      packets.put(payload);
      blk_ctrl.send_items(port, payload);
    end


    for (int packet_count = 0; packet_count < num_packets; packet_count++) begin
      item_t sent[$], received[$], expected[$];
      packets.get(sent);


      foreach(sent[i]) begin
        expected[i] = mult_rc(coefficients[coeff_index], sent[i]);
        if (coeff_index >= window_size-1) coeff_index = 0;
        else coeff_index++;
      end


      blk_ctrl.recv_items(port, received);


      `ASSERT_ERROR(
        expected.size() == received.size(), 
        $sformatf("For packet %0d, received length was incorrect", packet_count)
      );


      foreach(received[i]) begin
        `ASSERT_ERROR(
          received[i] == expected[i], 
          $sformatf("Unexpected result for packet %0d, sample %0d", packet_count, i)
        );
      end
    end

  endtask : test_window









  task automatic test_random(
    int port,
    int num_iterations  = 100,
    int max_window_size = MAX_WINDOW_SIZE,
    int max_packet_len  = SPP
  );
    test.start_test("Test random", 10ms);


    for (int iteration = 0; iteration < num_iterations; iteration++) begin
      int window_size;
      int packet_len;
      int num_packets;
      int packets_per_window;


      window_size = $urandom_range(1, MAX_WINDOW_SIZE);
      packet_len  = $urandom_range(1, SPP);


      packets_per_window = $ceil(real'(window_size) / real'(packet_len));
      num_packets = $urandom_range(1, 2*packets_per_window);


      test_window(port, window_size, packet_len, num_packets);
    end

    test.end_test();
  endtask : test_random



  task automatic test_directed(int port);
    test.start_test("Test directed", 100us);
    test_window(port, 16,   1, 33);
    test_window(port, 16,   8,  5);
    test_window(port, 16,  16,  3);
    test_window(port, 16,  31,  3);
    test_window(port, 16, SPP,  3);
    if (MAX_WINDOW_SIZE <= SPP) begin
      test_window(port, MAX_WINDOW_SIZE, MAX_WINDOW_SIZE, 2);
      test_window(port, MAX_WINDOW_SIZE, SPP, 2);
    end else begin
      test_window(port, MAX_WINDOW_SIZE, SPP, 2);
    end
    test.end_test();
  endtask : test_directed


  task automatic test_back_pressure(int port);
    test.start_test("Test back pressure", 1ms);
    blk_ctrl.set_slave_stall_prob(port, 90);
    test_window(port, 16, SPP, 20);
    blk_ctrl.set_slave_stall_prob(port, STALL_PROB);
    test.end_test();
  endtask : test_back_pressure




  task automatic test_underflow(int port);
    test.start_test("Test underflow", 1ms);
    blk_ctrl.set_master_stall_prob(port, 90);
    test_window(port, 16, SPP, 20);
    blk_ctrl.set_master_stall_prob(port, STALL_PROB);
    test.end_test();
  endtask : test_underflow






  initial begin : tb_main
    int port;


    test.start_tb("rfnoc_block_window_tb");


    blk_ctrl.run();





    test.start_test("Flush block then reset it", 10us);
    blk_ctrl.flush_and_reset();
    test.end_test();





    test.start_test("Verify Block Info", 2us);
    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");
    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
    test.end_test();






    for (port = 0; port < NUM_PORTS; port++) begin
      test_registers(port);
      test_directed(port);
    end

    port = NUM_PORTS-1;
    test_random(port, 100);
    test_back_pressure(port);
    test_underflow(port);






    test.end_tb();
  end : tb_main

endmodule
module rfnoc_block_window_tb;


  `include "test_exec.svh"

  import PkgTestExec::*;
  import PkgChdrUtils::*;
  import PkgRfnocBlockCtrlBfm::*;
  import PkgRfnocItemUtils::*;

  `include "rfnoc_block_window_regs.vh"





  localparam [31:0] NOC_ID          = 32'hD0530000;
  localparam [ 9:0] THIS_PORTID     = 10'h123;
  localparam int    CHDR_W          = 64;
  localparam int    MTU             = 10;
  localparam int    NUM_PORTS       = 2;
  localparam int    NUM_PORTS_I     = NUM_PORTS;
  localparam int    NUM_PORTS_O     = NUM_PORTS;
  localparam int    ITEM_W          = 32;
  localparam int    SPP             = 256;
  localparam int    PKT_SIZE_BYTES  = SPP * (ITEM_W/8);
  localparam int    STALL_PROB      = 25;
  localparam real   CHDR_CLK_PER    = 5.0;
  localparam real   CTRL_CLK_PER    = 8.0;
  localparam real   CE_CLK_PER      = 4.0;
  localparam int    MAX_WINDOW_SIZE = 128;





  bit rfnoc_chdr_clk;
  bit rfnoc_ctrl_clk;
  bit ce_clk;

  sim_clock_gen #(CHDR_CLK_PER) rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
  sim_clock_gen #(CTRL_CLK_PER) rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
  sim_clock_gen #(CE_CLK_PER) ce_clk_gen (.clk(ce_clk), .rst());






  RfnocBackendIf backend (rfnoc_chdr_clk, rfnoc_ctrl_clk);


  AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, 1'b0);
  AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, 1'b0);


  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS_I] (rfnoc_chdr_clk, 1'b0);
  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS_O] (rfnoc_chdr_clk, 1'b0);


  RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl);


  typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t  chdr_word_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_t       item_t;
  typedef ChdrData #(CHDR_W, ITEM_W)::item_queue_t item_queue_t;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_bfm_input_connections
    initial begin
      blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
    end
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_bfm_output_connections
    initial begin
      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
    end
  end






  logic [CHDR_W*NUM_PORTS_I-1:0] s_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tready;


  logic [CHDR_W*NUM_PORTS_O-1:0] m_rfnoc_chdr_tdata;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tlast;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tvalid;
  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tready;


  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_dut_input_connections

    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
  end
  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_dut_output_connections

    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
  end

  rfnoc_block_window #(
    .THIS_PORTID         (THIS_PORTID),
    .CHDR_W              (CHDR_W),
    .MTU                 (MTU),
    .NUM_PORTS           (NUM_PORTS),
    .MAX_WINDOW_SIZE     (MAX_WINDOW_SIZE)
  ) dut (
    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
    .ce_clk              (ce_clk),
    .rfnoc_core_config   (backend.cfg),
    .rfnoc_core_status   (backend.sts),
    .s_rfnoc_chdr_tdata  (s_rfnoc_chdr_tdata),
    .s_rfnoc_chdr_tlast  (s_rfnoc_chdr_tlast),
    .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
    .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
    .m_rfnoc_chdr_tdata  (m_rfnoc_chdr_tdata),
    .m_rfnoc_chdr_tlast  (m_rfnoc_chdr_tlast),
    .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
    .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
    .s_rfnoc_ctrl_tdata  (m_ctrl.tdata),
    .s_rfnoc_ctrl_tlast  (m_ctrl.tlast),
    .s_rfnoc_ctrl_tvalid (m_ctrl.tvalid),
    .s_rfnoc_ctrl_tready (m_ctrl.tready),
    .m_rfnoc_ctrl_tdata  (s_ctrl.tdata),
    .m_rfnoc_ctrl_tlast  (s_ctrl.tlast),
    .m_rfnoc_ctrl_tvalid (s_ctrl.tvalid),
    .m_rfnoc_ctrl_tready (s_ctrl.tready)
  );






  task automatic write_reg(int port, bit [19:0] addr, bit [31:0] value);
    blk_ctrl.reg_write(port * (2**WINDOW_ADDR_W) + addr, value);
  endtask : write_reg

  task automatic read_reg(int port, bit [19:0] addr, output logic [31:0] value);
    blk_ctrl.reg_read(port * (2**WINDOW_ADDR_W) + addr, value);
  endtask : read_reg









  function bit [31:0] mult_rc(bit signed [15:0] real_data, bit signed [31:0] complex_data);
    bit [47:0] temp;
    bit [31:0] result;
    temp = (real_data * signed'(complex_data[31:16])) >> 15;
    result[31:16] = temp;
    temp = (real_data * signed'(complex_data[15: 0])) >> 15;
    result[15: 0] = temp;
    return result;
  endfunction : mult_rc



  task automatic test_registers(int port);
    int unsigned value, expected;

    test.start_test($sformatf("Test registers, port %0d", port), 10us);

    read_reg(port, REG_WINDOW_MAX_SIZE, value);
    `ASSERT_ERROR(value == MAX_WINDOW_SIZE, "REG_WINDOW_MAX_SIZE reports incorrect value");

    expected = 2**$clog2(MAX_WINDOW_SIZE+1)-1;
    write_reg(port, REG_WINDOW_SIZE, expected);
    read_reg(port, REG_WINDOW_SIZE, value);
    `ASSERT_ERROR(value == expected, "REG_WINDOW_SIZE did not update");

    expected = 0;
    write_reg(port, REG_WINDOW_SIZE, expected);
    read_reg(port, REG_WINDOW_SIZE, value);
    `ASSERT_ERROR(value == expected, "REG_WINDOW_SIZE did not update");

    test.end_test();
  endtask : test_registers









  task automatic test_window(int port, int window_size, int packet_len, int num_packets);
    item_t coefficients[$];
    int coeff_index;
    mailbox #(item_queue_t) packets = new();

    $display("Testing: window_size=%04d, packet_len=%04d, num_packets=%04d",
      window_size, packet_len, num_packets);

    write_reg(port, REG_WINDOW_SIZE, window_size);


    for (int count=0; count < window_size; count++) begin
      item_t coeff;

      coeff = $urandom();
      coefficients.push_back(coeff);


      if (count == window_size-1)
        write_reg(port, REG_LOAD_COEFF_LAST, coeff);
      else
        write_reg(port, REG_LOAD_COEFF, coeff);
    end


    coeff_index = 0;


    for (int packet_count = 0; packet_count < num_packets; packet_count++) begin
      item_t payload[$];

      payload = {};
      for (int sample_count = 0; sample_count < packet_len; sample_count++) begin
        payload.push_back($urandom());
      end
      packets.put(payload);
      blk_ctrl.send_items(port, payload);
    end


    for (int packet_count = 0; packet_count < num_packets; packet_count++) begin
      item_t sent[$], received[$], expected[$];
      packets.get(sent);


      foreach(sent[i]) begin
        expected[i] = mult_rc(coefficients[coeff_index], sent[i]);
        if (coeff_index >= window_size-1) coeff_index = 0;
        else coeff_index++;
      end


      blk_ctrl.recv_items(port, received);


      `ASSERT_ERROR(
        expected.size() == received.size(), 
        $sformatf("For packet %0d, received length was incorrect", packet_count)
      );


      foreach(received[i]) begin
        `ASSERT_ERROR(
          received[i] == expected[i], 
          $sformatf("Unexpected result for packet %0d, sample %0d", packet_count, i)
        );
      end
    end

  endtask : test_window









  task automatic test_random(
    int port,
    int num_iterations  = 100,
    int max_window_size = MAX_WINDOW_SIZE,
    int max_packet_len  = SPP
  );
    test.start_test("Test random", 10ms);


    for (int iteration = 0; iteration < num_iterations; iteration++) begin
      int window_size;
      int packet_len;
      int num_packets;
      int packets_per_window;


      window_size = $urandom_range(1, MAX_WINDOW_SIZE);
      packet_len  = $urandom_range(1, SPP);


      packets_per_window = $ceil(real'(window_size) / real'(packet_len));
      num_packets = $urandom_range(1, 2*packets_per_window);


      test_window(port, window_size, packet_len, num_packets);
    end

    test.end_test();
  endtask : test_random



  task automatic test_directed(int port);
    test.start_test("Test directed", 100us);
    test_window(port, 16,   1, 33);
    test_window(port, 16,   8,  5);
    test_window(port, 16,  16,  3);
    test_window(port, 16,  31,  3);
    test_window(port, 16, SPP,  3);
    if (MAX_WINDOW_SIZE <= SPP) begin
      test_window(port, MAX_WINDOW_SIZE, MAX_WINDOW_SIZE, 2);
      test_window(port, MAX_WINDOW_SIZE, SPP, 2);
    end else begin
      test_window(port, MAX_WINDOW_SIZE, SPP, 2);
    end
    test.end_test();
  endtask : test_directed


  task automatic test_back_pressure(int port);
    test.start_test("Test back pressure", 1ms);
    blk_ctrl.set_slave_stall_prob(port, 90);
    test_window(port, 16, SPP, 20);
    blk_ctrl.set_slave_stall_prob(port, STALL_PROB);
    test.end_test();
  endtask : test_back_pressure




  task automatic test_underflow(int port);
    test.start_test("Test underflow", 1ms);
    blk_ctrl.set_master_stall_prob(port, 90);
    test_window(port, 16, SPP, 20);
    blk_ctrl.set_master_stall_prob(port, STALL_PROB);
    test.end_test();
  endtask : test_underflow






  initial begin : tb_main
    int port;


    test.start_tb("rfnoc_block_window_tb");


    blk_ctrl.run();





    test.start_test("Flush block then reset it", 10us);
    blk_ctrl.flush_and_reset();
    test.end_test();





    test.start_test("Verify Block Info", 2us);
    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");
    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");
    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
    test.end_test();






    for (port = 0; port < NUM_PORTS; port++) begin
      test_registers(port);
      test_directed(port);
    end

    port = NUM_PORTS-1;
    test_random(port, 100);
    test_back_pressure(port);
    test_underflow(port);






    test.end_tb();
  end : tb_main

endmodule