data/full_repos/permissive/116476954/iobuffer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/116476954/iobuffer.v:13: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'alu_out\' generates 8 bits.\n                                                                  : ... In instance iobuffer\nassign mdat = (en1) ?  alu_out : \'hzz ;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/116476954/iobuffer.v:13: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                  : ... In instance iobuffer\nassign mdat = (en1) ?  alu_out : \'hzz ;\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module iobuffer(clk2,mrd,fch,alu_out,mdat);

input clk2,mrd,fch;
input [7:0] alu_out;
output [7:0] mdat;

wire en, en1;


assign en = mrd || fch || clk2;
assign en1 = ~en;

assign mdat = (en1) ?  alu_out : 'hzz ;


endmodule
module iobuffer(clk2,mrd,fch,alu_out,mdat);


input clk2,mrd,fch;
input [7:0] alu_out;
output [7:0] mdat;

wire en, en1;


assign en = mrd || fch || clk2;
assign en1 = ~en;

assign mdat = (en1) ?  alu_out : 'hzz ;


endmodule