data/full_repos/permissive/112626266/Data_Memory.v
data/verilator_xmls/d9c5b3ac-98d7-43f8-8904-e849203c5050.xml
module Data_Memory(Address , Write_Data , MemWrite , MemRead , Read_Data, Clock);

	input wire[31:0] Address;
	input wire[31:0] Write_Data;
	input MemWrite;
	input MemRead;
	output reg[31:0] Read_Data;
	reg[31:0] D_Memory [0:255];
        input wire Clock;

	always@(*)
	begin
        Read_Data <= (MemRead && ~MemWrite)? D_Memory[Address] : Read_Data;
        D_Memory[Address] <= (MemWrite && ~MemRead)? Write_Data : D_Memory[Address];




	end

	initial
	begin
		D_Memory[3] = 4;
		D_Memory[7] = 8;
	end
	
endmodule
module Data_Memory(Address , Write_Data , MemWrite , MemRead , Read_Data, Clock);


	input wire[31:0] Address;
	input wire[31:0] Write_Data;
	input MemWrite;
	input MemRead;
	output reg[31:0] Read_Data;
	reg[31:0] D_Memory [0:255];
        input wire Clock;

	always@(*)
	begin
        Read_Data <= (MemRead && ~MemWrite)? D_Memory[Address] : Read_Data;
        D_Memory[Address] <= (MemWrite && ~MemRead)? Write_Data : D_Memory[Address];




	end

	initial
	begin
		D_Memory[3] = 4;
		D_Memory[7] = 8;
	end
	
endmodule