data/full_repos/permissive/110151336/lab_05/src/13_carry_lookahead_adder_unwind/common/carry_lookahead_adder.v
1: b"%Error: data/full_repos/permissive/110151336/lab_05/src/13_carry_lookahead_adder_unwind/common/carry_lookahead_adder.v:19: Cannot find file containing module: 'carry_lookahead_generator'\n    carry_lookahead_generator #(.WIDTH(WIDTH)) i_CLG\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110151336/lab_05/src/13_carry_lookahead_adder_unwind/common,data/full_repos/permissive/110151336/carry_lookahead_generator\n             data/full_repos/permissive/110151336/lab_05/src/13_carry_lookahead_adder_unwind/common,data/full_repos/permissive/110151336/carry_lookahead_generator.v\n             data/full_repos/permissive/110151336/lab_05/src/13_carry_lookahead_adder_unwind/common,data/full_repos/permissive/110151336/carry_lookahead_generator.sv\n             carry_lookahead_generator\n             carry_lookahead_generator.v\n             carry_lookahead_generator.sv\n             obj_dir/carry_lookahead_generator\n             obj_dir/carry_lookahead_generator.v\n             obj_dir/carry_lookahead_generator.sv\n%Error: Exiting due to 1 error(s)\n"
module carry_lookahead_adder
# (
    parameter WIDTH = 8
)
(
    input                  carry_in,
    input  [WIDTH - 1 : 0] x,
    input  [WIDTH - 1 : 0] y,
    output [WIDTH - 1 : 0] z,
    output                 carry_out,
    output                 group_generate,
    output                 group_propagate
);
    wire [WIDTH : 0] carry;
    wire [WIDTH - 1 : 0] generate_wire, propagate_wire; 
    
    assign carry[0] = carry_in; 
    
    carry_lookahead_generator #(.WIDTH(WIDTH)) i_CLG
    (
        .carry_in       (carry_in        ),
        .generate_in    (generate_wire   ),
        .propagate_in   (propagate_wire  ),
        .carry          (carry[WIDTH : 1]),
        .group_generate (group_generate  ),
        .group_propagate(group_propagate )        
    );
    
    generate
        
        genvar i;
        
        for (i = 0; i <= WIDTH - 1; i = i + 1)
        begin : stage

            assign generate_wire [i] = x[i] & y[i];
            assign propagate_wire[i] = x[i] ^ y[i];

            assign z[i] = carry[i] ^ propagate_wire[i];
        end
    endgenerate
    
    assign carry_out = carry[WIDTH];

endmodule
module carry_lookahead_adder
# (
    parameter WIDTH = 8
)
(
    input                  carry_in,
    input  [WIDTH - 1 : 0] x,
    input  [WIDTH - 1 : 0] y,
    output [WIDTH - 1 : 0] z,
    output                 carry_out,
    output                 group_generate,
    output                 group_propagate
);

    wire [WIDTH : 0] carry;
    wire [WIDTH - 1 : 0] generate_wire, propagate_wire; 
    
    assign carry[0] = carry_in; 
    
    carry_lookahead_generator #(.WIDTH(WIDTH)) i_CLG
    (
        .carry_in       (carry_in        ),
        .generate_in    (generate_wire   ),
        .propagate_in   (propagate_wire  ),
        .carry          (carry[WIDTH : 1]),
        .group_generate (group_generate  ),
        .group_propagate(group_propagate )        
    );
    
    generate
        
        genvar i;
        
        for (i = 0; i <= WIDTH - 1; i = i + 1)
        begin : stage

            assign generate_wire [i] = x[i] & y[i];
            assign propagate_wire[i] = x[i] ^ y[i];

            assign z[i] = carry[i] ^ propagate_wire[i];
        end
    endgenerate
    
    assign carry_out = carry[WIDTH];

endmodule