data/full_repos/permissive/218779832/test/dpreg.v
data/verilator_xmls/b95db876-1157-4545-8eb5-cb5594bde92a.xml
module dpreg 
(
  input      [7:0] data,
  input      [2:0] read_addr,
  input      [2:0] write_addr,
  input            we,
  input clk,
  output reg [7:0] q
);
    
  reg [7:0] ram [7:0];
    
  always @(posedge clk) begin
    if (we) begin 
      ram[write_addr] <= data;
    end
  end
    
  always @(posedge clk) 
  begin
    q <= ram[read_addr];
  end

endmodule
module dpreg 
(
  input      [7:0] data,
  input      [2:0] read_addr,
  input      [2:0] write_addr,
  input            we,
  input clk,
  output reg [7:0] q
);

    
  reg [7:0] ram [7:0];
    
  always @(posedge clk) begin
    if (we) begin 
      ram[write_addr] <= data;
    end
  end
    
  always @(posedge clk) 
  begin
    q <= ram[read_addr];
  end

endmodule