data/full_repos/permissive/184332405/accumulator_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/184332405/accumulator_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("accumulator.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/184332405/accumulator_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,DUT);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/184332405/accumulator_tb.v:13: Unsupported or unknown PLI call: $monitor\n  $monitor("%d %d | %d", in, clk, s);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #0  in = 8\'d10;  #50 clk = 1; #50 clk = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #0  in = 8\'d10;  #50 clk = 1; #50 clk = 0;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #0  in = 8\'d10;  #50 clk = 1; #50 clk = 0;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #50 in = 8\'d20;  #50 clk = 1; #50 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #50 in = 8\'d20;  #50 clk = 1; #50 clk = 0;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #50 in = 8\'d20;  #50 clk = 1; #50 clk = 0;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #50 in = 8\'d127; #50 clk = 1; #50 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #50 in = 8\'d127; #50 clk = 1; #50 clk = 0;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #50 in = 8\'d127; #50 clk = 1; #50 clk = 0;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #50 in = -8\'d50; #50 clk = 1; #50 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #50 in = -8\'d50; #50 clk = 1; #50 clk = 0;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #50 in = -8\'d50; #50 clk = 1; #50 clk = 0;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/184332405/accumulator_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #50 $finish;\n  ^\n%Error: Exiting due to 3 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module accumulator_tb;
reg signed [7:0] in;
reg unsigned clk;
wire signed [7:0] s;

initial
	begin
		$dumpfile("accumulator.vcd");
		$dumpvars(0,DUT);
		$display("  in   clk    s");
		$monitor("%d %d | %d", in, clk, s);
		clk <= 0;
		in  <= 0;
		
		#0  in = 8'd10;  #50 clk = 1; #50 clk = 0;
		#50 in = 8'd20;  #50 clk = 1; #50 clk = 0;
		#50 in = 8'd127; #50 clk = 1; #50 clk = 0;
		#50 in = -8'd50; #50 clk = 1; #50 clk = 0;
		
		#50 $finish;
	end

accumulator DUT( s, clk, in);

endmodule
module accumulator_tb;

reg signed [7:0] in;
reg unsigned clk;
wire signed [7:0] s;

initial
	begin
		$dumpfile("accumulator.vcd");
		$dumpvars(0,DUT);
		$display("  in   clk    s");
		$monitor("%d %d | %d", in, clk, s);
		clk <= 0;
		in  <= 0;
		
		#0  in = 8'd10;  #50 clk = 1; #50 clk = 0;
		#50 in = 8'd20;  #50 clk = 1; #50 clk = 0;
		#50 in = 8'd127; #50 clk = 1; #50 clk = 0;
		#50 in = -8'd50; #50 clk = 1; #50 clk = 0;
		
		#50 $finish;
	end

accumulator DUT( s, clk, in);

endmodule