data/full_repos/permissive/170402453/RISC/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:44: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'Cout_\' generates 16 bits.\n                                                                  : ... In instance ALU\n  assign Cout= Cout_;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:51: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'A\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b0000: {{Cout_}, {Out_}} = A;   \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:52: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'A\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b0001: {{Cout_}, {Out_}} = A+1;   \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:53: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'A\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b0010: {{Cout_}, {Out_}} = A+B;   \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:53: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'B\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b0010: {{Cout_}, {Out_}} = A+B;   \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:54: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'A\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b0011: {{Cout_}, {Out_}} = A+B+1;  \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:54: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'B\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b0011: {{Cout_}, {Out_}} = A+B+1;  \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:55: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'A\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b0100: {{Cout_}, {Out_}} = A+~B;  \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:55: Operator NOT expects 32 bits on the LHS, but LHS\'s VARREF \'B\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b0100: {{Cout_}, {Out_}} = A+~B;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:56: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'A\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b0101: {{Cout_}, {Out_}} = A+~B+1;  \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:56: Operator NOT expects 32 bits on the LHS, but LHS\'s VARREF \'B\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b0101: {{Cout_}, {Out_}} = A+~B+1;  \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:57: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'A\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b0110: {{Cout_}, {Out_}} = A-1;   \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:58: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'A\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b0111: {{Cout_}, {Out_}} = A;   \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:59: Operator AND expects 32 bits on the LHS, but LHS\'s VARREF \'A\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b100x: {{Cout_}, {Out_}} = A&B;   \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:59: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'B\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b100x: {{Cout_}, {Out_}} = A&B;   \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:60: Operator OR expects 32 bits on the LHS, but LHS\'s VARREF \'A\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b101x: {{Cout_}, {Out_}} = A|B;   \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:60: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'B\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b101x: {{Cout_}, {Out_}} = A|B;   \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:61: Operator XOR expects 32 bits on the LHS, but LHS\'s VARREF \'A\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b110x: {{Cout_}, {Out_}} = A^B;   \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:61: Operator XOR expects 32 bits on the RHS, but RHS\'s VARREF \'B\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b110x: {{Cout_}, {Out_}} = A^B;   \n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:62: Operator NOT expects 32 bits on the LHS, but LHS\'s VARREF \'A\' generates 16 bits.\n                                                                  : ... In instance ALU\n   4\'b111x: {{Cout_}, {Out_}} = ~A;   \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC/ALU.v:74: Operator LTE expects 4 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                  : ... In instance ALU\n  if(1 <= {{Sel},{Cin}} <= 4\'b0101) begin\n                        ^~\n%Error: Exiting due to 21 warning(s)\n'
module ALU(
    input Cin,
    input [2:0] Sel,
    input [BITS-1:0] A,
    input [BITS-1:0] B,
    output [BITS-1:0] Out,
	 output statV,
    output Cout
    );
	 
	 parameter BITS = 16;
	 
	 reg [BITS-1:0] Cout_;
	 reg [BITS-1:0] Out_;
	 reg statV_;
	 
	 initial begin
		Cout_ 	= 	0;
		Out_ 		= 	0;
		statV_	=	0;
	 end
	 
	 assign Out = Out_;
	 assign Cout= Cout_;
	 assign statV=statV_;
	 

	 
	 always @(*) begin
		case({{Sel}, {Cin}})
			4'b0000: {{Cout_}, {Out_}} = A;
			4'b0001: {{Cout_}, {Out_}} = A+1;
			4'b0010: {{Cout_}, {Out_}} = A+B;
			4'b0011: {{Cout_}, {Out_}} = A+B+1;
			4'b0100: {{Cout_}, {Out_}} = A+~B;
			4'b0101: {{Cout_}, {Out_}} = A+~B+1;
			4'b0110: {{Cout_}, {Out_}} = A-1;
			4'b0111: {{Cout_}, {Out_}} = A;
			4'b100x: {{Cout_}, {Out_}} = A&B;
			4'b101x: {{Cout_}, {Out_}} = A|B;
			4'b110x: {{Cout_}, {Out_}} = A^B;
			4'b111x: {{Cout_}, {Out_}} = ~A;
		endcase
		







		

		if(1 <= {{Sel},{Cin}} <= 4'b0101) begin
			if(((A+B) > 1<<BITS) && A[BITS-1] == 0) begin

				statV_ = 1;
			end else statV_ = 0;
		end else if({{Sel}, {Cin}} == 4'b0101 && A<B) begin
			if((A-B)>0 && A[BITS-1] == 1) begin

				statV_ = 1;
			end else statV_ = 0;
		end else statV_ = 0;
	 end
endmodule
module ALU(
    input Cin,
    input [2:0] Sel,
    input [BITS-1:0] A,
    input [BITS-1:0] B,
    output [BITS-1:0] Out,
	 output statV,
    output Cout
    );

	 
	 parameter BITS = 16;
	 
	 reg [BITS-1:0] Cout_;
	 reg [BITS-1:0] Out_;
	 reg statV_;
	 
	 initial begin
		Cout_ 	= 	0;
		Out_ 		= 	0;
		statV_	=	0;
	 end
	 
	 assign Out = Out_;
	 assign Cout= Cout_;
	 assign statV=statV_;
	 

	 
	 always @(*) begin
		case({{Sel}, {Cin}})
			4'b0000: {{Cout_}, {Out_}} = A;
			4'b0001: {{Cout_}, {Out_}} = A+1;
			4'b0010: {{Cout_}, {Out_}} = A+B;
			4'b0011: {{Cout_}, {Out_}} = A+B+1;
			4'b0100: {{Cout_}, {Out_}} = A+~B;
			4'b0101: {{Cout_}, {Out_}} = A+~B+1;
			4'b0110: {{Cout_}, {Out_}} = A-1;
			4'b0111: {{Cout_}, {Out_}} = A;
			4'b100x: {{Cout_}, {Out_}} = A&B;
			4'b101x: {{Cout_}, {Out_}} = A|B;
			4'b110x: {{Cout_}, {Out_}} = A^B;
			4'b111x: {{Cout_}, {Out_}} = ~A;
		endcase
		







		

		if(1 <= {{Sel},{Cin}} <= 4'b0101) begin
			if(((A+B) > 1<<BITS) && A[BITS-1] == 0) begin

				statV_ = 1;
			end else statV_ = 0;
		end else if({{Sel}, {Cin}} == 4'b0101 && A<B) begin
			if((A-B)>0 && A[BITS-1] == 1) begin

				statV_ = 1;
			end else statV_ = 0;
		end else statV_ = 0;
	 end
endmodule