data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_auto_bitwise_xor.v
'utf-8' codec can't decode byte 0xb0 in position 486: invalid start byte
1: b'%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_auto_bitwise_xor.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #delay ab_xor = a ^b;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_auto_bitwise_xor.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #50 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_auto_bitwise_xor.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #25 clk2=~clk2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/task_and_func/task_and_func.srcs/sources_1/new/task_auto_bitwise_xor.v:60: Unsupported: Ignoring delay on this delayed statement.\n   #200 $finish;\n   ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module task_auto_bitwise_xor;

parameter delay = 10;
reg [15:0] cd_xor, ef_xor;
reg [15:0] c,d,e,f;
reg clk=0,clk2=0;

task automatic bitwise_xor;
output [15:0] ab_xor;
input [15:0] a,b;
begin
    #delay ab_xor = a ^b;
end
endtask



always @(posedge clk)
    bitwise_xor(ef_xor, e, f);

always @(posedge clk2)
    bitwise_xor(cd_xor, c, d);


always
    #50 clk=~clk;
always
    #25 clk2=~clk2;

initial
begin
    c = 16'b0101_1010_1111_0000;
    d = 16'b1100_0011_0011_1100;
    e = 16'b1010_1010_1010_1010;
    f = 16'b1100_1100_0011_0011;
   #200 $finish;
end

endmodule
module task_auto_bitwise_xor;


parameter delay = 10;
reg [15:0] cd_xor, ef_xor;
reg [15:0] c,d,e,f;
reg clk=0,clk2=0;

task automatic bitwise_xor;
output [15:0] ab_xor;
input [15:0] a,b;
begin
    #delay ab_xor = a ^b;
end
endtask



always @(posedge clk)
    bitwise_xor(ef_xor, e, f);

always @(posedge clk2)
    bitwise_xor(cd_xor, c, d);


always
    #50 clk=~clk;
always
    #25 clk2=~clk2;

initial
begin
    c = 16'b0101_1010_1111_0000;
    d = 16'b1100_0011_0011_1100;
    e = 16'b1010_1010_1010_1010;
    f = 16'b1100_1100_0011_0011;
   #200 $finish;
end

endmodule