data/full_repos/permissive/127241521/blinker/blinker.v
data/verilator_xmls/c1a24491-81dd-45e1-bb33-cdafdf3fbceb.xml
module blinker(
    input clk,
	 input rst,
	 input sclk,	 
    output ld1,
    output ld2
);

reg [1:0] counter;

always @(posedge clk)
    if(rst)
	     counter <= 0;
	 else 
	     if(sclk)
		      counter <= counter + 1;


assign ld1 = counter[1];
assign ld2 = counter[0];

endmodule
module blinker(
    input clk,
	 input rst,
	 input sclk,	 
    output ld1,
    output ld2
);


reg [1:0] counter;

always @(posedge clk)
    if(rst)
	     counter <= 0;
	 else 
	     if(sclk)
		      counter <= counter + 1;


assign ld1 = counter[1];
assign ld2 = counter[0];

endmodule