data/full_repos/permissive/116048589/Xilinx_Project/Main Xilinx Project/bitshift.v
1: b'%Error: Cannot find file containing module: Xilinx\n        ... Looked in:\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.v\n             data/full_repos/permissive/116048589/Xilinx_Project/Main/Xilinx.sv\n             Xilinx\n             Xilinx.v\n             Xilinx.sv\n             obj_dir/Xilinx\n             obj_dir/Xilinx.v\n             obj_dir/Xilinx.sv\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/116048589\n%Error: Cannot find file containing module: data/full_repos/permissive/116048589/Xilinx_Project/Main\n%Error: Cannot find file containing module: Project/bitshift.v\n%Error: Exiting due to 4 error(s)\n'
module bitshift(
	 input reset,
	 input clk,
    input [15:0] word1,
    input [15:0] word2,
    output SPI_MOSI,
	 output reg DAC_CS,
	 output DAC_CLK
    );
	 
	reg [31:0] bits;
	reg [5:0] cnt;
	
	assign DAC_CLK = clk;
	assign SPI_MOSI = bits[31];
	
	always@(posedge DAC_CLK) begin
		DAC_CS <= 0;
		if (reset) begin
			cnt <= 0;
			bits <= 0;
		end
		else begin
			if (cnt == 0)
				bits <= {word1,word2};
			if (cnt == 32) begin
				cnt <= 0;
				DAC_CS <= 1;
			end
			else bits <= bits << 1;
			
			cnt <= cnt + 1;
		end
	end
	
endmodule
module bitshift(
	 input reset,
	 input clk,
    input [15:0] word1,
    input [15:0] word2,
    output SPI_MOSI,
	 output reg DAC_CS,
	 output DAC_CLK
    );

	 
	reg [31:0] bits;
	reg [5:0] cnt;
	
	assign DAC_CLK = clk;
	assign SPI_MOSI = bits[31];
	
	always@(posedge DAC_CLK) begin
		DAC_CS <= 0;
		if (reset) begin
			cnt <= 0;
			bits <= 0;
		end
		else begin
			if (cnt == 0)
				bits <= {word1,word2};
			if (cnt == 32) begin
				cnt <= 0;
				DAC_CS <= 1;
			end
			else bits <= bits << 1;
			
			cnt <= cnt + 1;
		end
	end
	
endmodule