data/full_repos/permissive/173943530/jt_gng/modules/jt12/hdl/deprecated/jt12_mod24.v
1: b'%Warning-WIDTH: data/full_repos/permissive/173943530/jt_gng/modules/jt12/hdl/deprecated/jt12_mod24.v:9: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'extra\' generates 4 bits.\n                                                                                                      : ... In instance jt12_mod24\nwire [5:0]  sum = base+extra;\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module jt12_mod24(
	input	[4:0] base,
	input	[3:0] extra,
	output  [4:0] mod
);

wire [5:0]  sum = base+extra;
wire [4:0] wrap = base+extra-5'd24;

assign mod = sum > 6'd23 ? wrap : sum[4:0];

endmodule
module jt12_mod24(
	input	[4:0] base,
	input	[3:0] extra,
	output  [4:0] mod
);


wire [5:0]  sum = base+extra;
wire [4:0] wrap = base+extra-5'd24;

assign mod = sum > 6'd23 ? wrap : sum[4:0];

endmodule