data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/cclk_detector_4.v
 line:23: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/cclk_detector_4.v:23: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                    : ... In instance cclk_detector_4\n  reg [13:0] M_ctr_d, M_ctr_q = 1\'h0;\n                                ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/cclk_detector_4.v:30: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                    : ... In instance cclk_detector_4\n      M_ctr_d = 1\'h0;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/cclk_detector_4.v:40: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                    : ... In instance cclk_detector_4\n      M_ctr_q <= 1\'h0;\n              ^~\n%Error: Exiting due to 3 warning(s)\n'
module cclk_detector_4 (
    input clk,
    input rst,
    input cclk,
    output reg ready
  );
  
  localparam CLK_FREQ = 26'h2faf080;
  
  
  localparam CTR_SIZE = 4'he;
  
  reg [13:0] M_ctr_d, M_ctr_q = 1'h0;
  
  always @* begin
    M_ctr_d = M_ctr_q;
    
    ready = (&M_ctr_q);
    if (cclk == 1'h0) begin
      M_ctr_d = 1'h0;
    end else begin
      if (!(&M_ctr_q)) begin
        M_ctr_d = M_ctr_q + 1'h1;
      end
    end
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_ctr_q <= 1'h0;
    end else begin
      M_ctr_q <= M_ctr_d;
    end
  end
  
endmodule
module cclk_detector_4 (
    input clk,
    input rst,
    input cclk,
    output reg ready
  );

  
  localparam CLK_FREQ = 26'h2faf080;
  
  
  localparam CTR_SIZE = 4'he;
  
  reg [13:0] M_ctr_d, M_ctr_q = 1'h0;
  
  always @* begin
    M_ctr_d = M_ctr_q;
    
    ready = (&M_ctr_q);
    if (cclk == 1'h0) begin
      M_ctr_d = 1'h0;
    end else begin
      if (!(&M_ctr_q)) begin
        M_ctr_d = M_ctr_q + 1'h1;
      end
    end
  end
  
  always @(posedge clk) begin
    if (rst == 1'b1) begin
      M_ctr_q <= 1'h0;
    end else begin
      M_ctr_q <= M_ctr_d;
    end
  end
  
endmodule