data/full_repos/permissive/123649059/SegAdder.v
1: b'%Error: data/full_repos/permissive/123649059/SegAdder.v:29: Cannot find file containing module: \'SegDrv\'\nSegDrv m_seg(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123649059,data/full_repos/permissive/123649059/SegDrv\n             data/full_repos/permissive/123649059,data/full_repos/permissive/123649059/SegDrv.v\n             data/full_repos/permissive/123649059,data/full_repos/permissive/123649059/SegDrv.sv\n             SegDrv\n             SegDrv.v\n             SegDrv.sv\n             obj_dir/SegDrv\n             obj_dir/SegDrv.v\n             obj_dir/SegDrv.sv\n%Warning-WIDTH: data/full_repos/permissive/123649059/SegAdder.v:49: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                  : ... In instance SegAdder\n     cur_cal <= 1\'B0;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/123649059/SegAdder.v:55: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                  : ... In instance SegAdder\n    if(cur_cal == 1\'B0) begin\n               ^~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module SegAdder(
	clk,
	rst_n,
	opt_add,
	opt_dec,
	sig_add,
	sig_dec,
	data_out
);

parameter DATA_FORMAT = 4'D10;
parameter ORG_VALUE   = 4'D0;

input       clk;
input       rst_n;
input       opt_add;
input       opt_dec;
output      sig_add;
output      sig_dec;
output[7:0] data_out;

reg       sig_add;
reg       sig_dec;
reg [3:0] cur_cal;
wire[1:0] opt_line;

SegDrv m_seg(
	.clk     (clk),
	.rst_n   (rst_n),
	.data_in (cur_cal),
	.data_out(data_out)
);

assign opt_line = {opt_add, opt_dec};

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cur_cal <= ORG_VALUE;
		sig_add <= 1'B0;
		sig_dec <= 1'B0;
	end else begin
		sig_add <= 1'B0;
		sig_dec <= 1'B0;
		casex(opt_line)
			2'B1x:
				if(cur_cal == (DATA_FORMAT - 1'B1)) begin
					cur_cal <= 1'B0;
					sig_add <= 1'B1;
				end else begin
					cur_cal <= cur_cal + 1'B1;
				end
			2'B01:
				if(cur_cal == 1'B0) begin
					cur_cal <= DATA_FORMAT - 1'B1;
					sig_dec <= 1'B1;
				end else begin
					cur_cal <= cur_cal - 1'B1;
				end
			default:;
		endcase
	end
end

endmodule
module SegAdder(
	clk,
	rst_n,
	opt_add,
	opt_dec,
	sig_add,
	sig_dec,
	data_out
);


parameter DATA_FORMAT = 4'D10;
parameter ORG_VALUE   = 4'D0;

input       clk;
input       rst_n;
input       opt_add;
input       opt_dec;
output      sig_add;
output      sig_dec;
output[7:0] data_out;

reg       sig_add;
reg       sig_dec;
reg [3:0] cur_cal;
wire[1:0] opt_line;

SegDrv m_seg(
	.clk     (clk),
	.rst_n   (rst_n),
	.data_in (cur_cal),
	.data_out(data_out)
);

assign opt_line = {opt_add, opt_dec};

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cur_cal <= ORG_VALUE;
		sig_add <= 1'B0;
		sig_dec <= 1'B0;
	end else begin
		sig_add <= 1'B0;
		sig_dec <= 1'B0;
		casex(opt_line)
			2'B1x:
				if(cur_cal == (DATA_FORMAT - 1'B1)) begin
					cur_cal <= 1'B0;
					sig_add <= 1'B1;
				end else begin
					cur_cal <= cur_cal + 1'B1;
				end
			2'B01:
				if(cur_cal == 1'B0) begin
					cur_cal <= DATA_FORMAT - 1'B1;
					sig_dec <= 1'B1;
				end else begin
					cur_cal <= cur_cal - 1'B1;
				end
			default:;
		endcase
	end
end

endmodule