data/full_repos/permissive/179980995/FPU/before roll.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/179980995/FPU/before\n        ... Looked in:\n             data/full_repos/permissive/179980995/FPU,data/full_repos/permissive/179980995/data/full_repos/permissive/179980995/FPU/before\n             data/full_repos/permissive/179980995/FPU,data/full_repos/permissive/179980995/data/full_repos/permissive/179980995/FPU/before.v\n             data/full_repos/permissive/179980995/FPU,data/full_repos/permissive/179980995/data/full_repos/permissive/179980995/FPU/before.sv\n             data/full_repos/permissive/179980995/FPU/before\n             data/full_repos/permissive/179980995/FPU/before.v\n             data/full_repos/permissive/179980995/FPU/before.sv\n             obj_dir/data/full_repos/permissive/179980995/FPU/before\n             obj_dir/data/full_repos/permissive/179980995/FPU/before.v\n             obj_dir/data/full_repos/permissive/179980995/FPU/before.sv\n%Error: Cannot find file containing module: roll.v\n%Error: Exiting due to 2 error(s)\n'
module adder(a, b, out);
  input  [31:0] a, b;
  output [31:0] out;

  wire [31:0] out;
	reg a_sign;
	reg [7:0] a_exponent;
	reg [23:0] a_mantissa;
	reg b_sign;
	reg [7:0] b_exponent;
	reg [23:0] b_mantissa;

  reg o_sign;
  reg [7:0] o_exponent;
  reg [24:0] o_mantissa;

  reg [7:0] diff;
  reg [23:0] tmp_mantissa;
  reg [7:0] tmp_exponent;


  reg  [7:0] i_e;
  reg  [24:0] i_m;
  wire [7:0] o_e;
  wire [24:0] o_m;
  
    reg [23:0] add_a_in0;
	reg [23:0] add_b_in0;
	wire [24:0] add_out0;

	fa_24b add0
	(
		.a(add_a_in0),
		.b(add_b_in0),
		.out(add_out0)
	);

	reg [23:0] add_a_in1;
	reg [23:0] add_b_in1;
	wire [24:0] add_out1;

	fa_24b add1
	(
		.a(add_a_in1),
		.b(add_b_in1),
		.out(add_out1)
	);

	reg [23:0] add_a_in2;
	reg [23:0] add_b_in2;
	wire [24:0] add_out2;

	fa_24b add2
	(
		.a(add_a_in2),
		.b(add_b_in2),
		.out(add_out2)
	);

	reg [23:0] add_a_in3;
	reg [23:0] add_b_in3;
	wire [24:0] add_out3;

	fa_24b add3
	(
		.a(add_a_in3),
		.b(add_b_in3),
		.out(add_out3)
	);

	reg [23:0] add_a_in4;
	reg [23:0] add_b_in4;
	wire [24:0] add_out4;

	fa_24b add4
	(
		.a(add_a_in4),
		.b(add_b_in4),
		.out(add_out4)
	);

	reg [23:0] add_a_in5;
	reg [23:0] add_b_in5;
	wire [24:0] add_out5;

	fa_24b add5
	(
		.a(add_a_in5),
		.b(add_b_in5),
		.out(add_out5)
	);

	reg [23:0] add_a_in6;
	reg [23:0] add_b_in6;
	wire [24:0] add_out6;

	fa_24b add6
	(
		.a(add_a_in6),
		.b(add_b_in6),
		.out(add_out6)
	);

	reg [23:0] add_a_in7;
	reg [23:0] add_b_in7;
	wire [24:0] add_out7;

	fa_24b add7
	(
		.a(add_a_in7),
		.b(add_b_in7),
		.out(add_out7)
	);

	reg [23:0] add_a_in8;
	reg [23:0] add_b_in8;
	wire [24:0] add_out8;

	fa_24b add8
	(
		.a(add_a_in8),
		.b(add_b_in8),
		.out(add_out8)
	);

	reg [23:0] add_a_in9;
	reg [23:0] add_b_in9;
	wire [24:0] add_out9;

	fa_24b add9
	(
		.a(add_a_in9),
		.b(add_b_in9),
		.out(add_out9)
	);
	
	reg [2:0] shift_n0;
	reg [7:0] shift_in0;
	wire [7:0] shift_out0;
	
	barrel_shifter_8bit_R sh0
	(
		.in(shift_in0),
		.ctrl(shift_n0),
		.out(shift_out0)
	);
	
	reg [2:0] shift_n1;
	reg [7:0] shift_in1;
	wire [7:0] shift_out1;
	
	barrel_shifter_8bit_R sh1
	(
		.in(shift_in1),
		.ctrl(shift_n1),
		.out(shift_out1)
	);
  

  assign out[31] = o_sign;
  assign out[30:23] = o_exponent;
  assign out[22:0] = o_mantissa[22:0];

  always @ ( * ) begin
		a_sign = a[31];
		if(a[30:23] == 0) begin
			a_exponent = 8'b00000001;
			a_mantissa = {1'b0, a[22:0]};
		end else begin
			a_exponent = a[30:23];
			a_mantissa = {1'b1, a[22:0]};
		end
		b_sign = b[31];
		if(b[30:23] == 0) begin
			b_exponent = 8'b00000001;
			b_mantissa = {1'b0, b[22:0]};
		end else begin
			b_exponent = b[30:23];
			b_mantissa = {1'b1, b[22:0]};
		end
    if (a_exponent == b_exponent) begin
      o_exponent = a_exponent;
      if (a_sign == b_sign) begin

		add_a_in0 = a_mantissa;
		add_b_in0 = b_mantissa;
		o_mantissa = add_out0;

        o_mantissa[24] = 1;
        o_sign = a_sign;
      end else begin
        if(a_mantissa > b_mantissa) begin

		  add_a_in1 = a_mantissa;
		  add_b_in1 = ~b_mantissa;
		  o_mantissa = add_out1;		
          o_sign = a_sign;
        end else begin

		  add_a_in2 = ~a_mantissa;
		  add_b_in2 = b_mantissa;
		  o_mantissa = add_out2;
          o_sign = b_sign;
        end
      end
    end else begin
      if (a_exponent > b_exponent) begin
        o_exponent = a_exponent;
        o_sign = a_sign;

		add_a_in3 = {16'h00, a_exponent};
		add_b_in3 = {16'h00, ~b_exponent};
		diff = add_out3[7:0];

		if (diff > 8) begin
			o_sign = a_sign;
			o_exponent = a_exponent;
			o_mantissa = a_mantissa;
			end
		else begin
		shift_n0 = diff[2:0];
		shift_in0 = {24'h00, b_mantissa};
		tmp_mantissa = {16'h00, shift_out0};
        if (a_sign == b_sign) begin

		  add_a_in4 = a_mantissa;
		  add_b_in4 = tmp_mantissa;
		  o_mantissa = add_out4;
		  end
        else begin

			add_a_in5 = a_mantissa;
			add_b_in5 = ~tmp_mantissa;
			o_mantissa = add_out5;
			end
		end
      end
	  else if (a_exponent < b_exponent) begin
        o_exponent = b_exponent;
        o_sign = b_sign;

		add_a_in6 = {16'h00, ~a_exponent};
		add_b_in6 = {16'h00, b_exponent};
		diff = add_out6[7:0];
		if (diff > 8) begin
			o_sign = b_sign;
			o_exponent = b_exponent;
			o_mantissa = b_mantissa;
		end
		else begin
		tmp_mantissa = a_mantissa >> diff;



        if (a_sign == b_sign) begin

		  add_a_in7 = b_mantissa;
		  add_b_in7 = tmp_mantissa;
		  o_mantissa = add_out7;
        end else begin

		  add_a_in8 = b_mantissa;
		  add_b_in8 = ~tmp_mantissa;
		  o_mantissa = add_out8;
        end
		end
      end
    end
    if(o_mantissa[24] == 1) begin

	  add_a_in9 = {16'h00, o_exponent};
	  add_b_in9 = 24'h01;
	  o_exponent = add_out9[7:0];

	  tmp_mantissa = o_mantissa[24:1];
	  o_mantissa = {1'b0, tmp_mantissa};
    end else if((o_mantissa[23] != 1) && (o_exponent != 0)) begin
      i_e = o_exponent;
      i_m = o_mantissa;
      o_exponent = o_e;
      o_mantissa = o_m;
    end
  end
endmodule
module adder(a, b, out);

  input  [31:0] a, b;
  output [31:0] out;

  wire [31:0] out;
	reg a_sign;
	reg [7:0] a_exponent;
	reg [23:0] a_mantissa;
	reg b_sign;
	reg [7:0] b_exponent;
	reg [23:0] b_mantissa;

  reg o_sign;
  reg [7:0] o_exponent;
  reg [24:0] o_mantissa;

  reg [7:0] diff;
  reg [23:0] tmp_mantissa;
  reg [7:0] tmp_exponent;


  reg  [7:0] i_e;
  reg  [24:0] i_m;
  wire [7:0] o_e;
  wire [24:0] o_m;
  
    reg [23:0] add_a_in0;
	reg [23:0] add_b_in0;
	wire [24:0] add_out0;

	fa_24b add0
	(
		.a(add_a_in0),
		.b(add_b_in0),
		.out(add_out0)
	);

	reg [23:0] add_a_in1;
	reg [23:0] add_b_in1;
	wire [24:0] add_out1;

	fa_24b add1
	(
		.a(add_a_in1),
		.b(add_b_in1),
		.out(add_out1)
	);

	reg [23:0] add_a_in2;
	reg [23:0] add_b_in2;
	wire [24:0] add_out2;

	fa_24b add2
	(
		.a(add_a_in2),
		.b(add_b_in2),
		.out(add_out2)
	);

	reg [23:0] add_a_in3;
	reg [23:0] add_b_in3;
	wire [24:0] add_out3;

	fa_24b add3
	(
		.a(add_a_in3),
		.b(add_b_in3),
		.out(add_out3)
	);

	reg [23:0] add_a_in4;
	reg [23:0] add_b_in4;
	wire [24:0] add_out4;

	fa_24b add4
	(
		.a(add_a_in4),
		.b(add_b_in4),
		.out(add_out4)
	);

	reg [23:0] add_a_in5;
	reg [23:0] add_b_in5;
	wire [24:0] add_out5;

	fa_24b add5
	(
		.a(add_a_in5),
		.b(add_b_in5),
		.out(add_out5)
	);

	reg [23:0] add_a_in6;
	reg [23:0] add_b_in6;
	wire [24:0] add_out6;

	fa_24b add6
	(
		.a(add_a_in6),
		.b(add_b_in6),
		.out(add_out6)
	);

	reg [23:0] add_a_in7;
	reg [23:0] add_b_in7;
	wire [24:0] add_out7;

	fa_24b add7
	(
		.a(add_a_in7),
		.b(add_b_in7),
		.out(add_out7)
	);

	reg [23:0] add_a_in8;
	reg [23:0] add_b_in8;
	wire [24:0] add_out8;

	fa_24b add8
	(
		.a(add_a_in8),
		.b(add_b_in8),
		.out(add_out8)
	);

	reg [23:0] add_a_in9;
	reg [23:0] add_b_in9;
	wire [24:0] add_out9;

	fa_24b add9
	(
		.a(add_a_in9),
		.b(add_b_in9),
		.out(add_out9)
	);
	
	reg [2:0] shift_n0;
	reg [7:0] shift_in0;
	wire [7:0] shift_out0;
	
	barrel_shifter_8bit_R sh0
	(
		.in(shift_in0),
		.ctrl(shift_n0),
		.out(shift_out0)
	);
	
	reg [2:0] shift_n1;
	reg [7:0] shift_in1;
	wire [7:0] shift_out1;
	
	barrel_shifter_8bit_R sh1
	(
		.in(shift_in1),
		.ctrl(shift_n1),
		.out(shift_out1)
	);
  

  assign out[31] = o_sign;
  assign out[30:23] = o_exponent;
  assign out[22:0] = o_mantissa[22:0];

  always @ ( * ) begin
		a_sign = a[31];
		if(a[30:23] == 0) begin
			a_exponent = 8'b00000001;
			a_mantissa = {1'b0, a[22:0]};
		end else begin
			a_exponent = a[30:23];
			a_mantissa = {1'b1, a[22:0]};
		end
		b_sign = b[31];
		if(b[30:23] == 0) begin
			b_exponent = 8'b00000001;
			b_mantissa = {1'b0, b[22:0]};
		end else begin
			b_exponent = b[30:23];
			b_mantissa = {1'b1, b[22:0]};
		end
    if (a_exponent == b_exponent) begin
      o_exponent = a_exponent;
      if (a_sign == b_sign) begin

		add_a_in0 = a_mantissa;
		add_b_in0 = b_mantissa;
		o_mantissa = add_out0;

        o_mantissa[24] = 1;
        o_sign = a_sign;
      end else begin
        if(a_mantissa > b_mantissa) begin

		  add_a_in1 = a_mantissa;
		  add_b_in1 = ~b_mantissa;
		  o_mantissa = add_out1;		
          o_sign = a_sign;
        end else begin

		  add_a_in2 = ~a_mantissa;
		  add_b_in2 = b_mantissa;
		  o_mantissa = add_out2;
          o_sign = b_sign;
        end
      end
    end else begin
      if (a_exponent > b_exponent) begin
        o_exponent = a_exponent;
        o_sign = a_sign;

		add_a_in3 = {16'h00, a_exponent};
		add_b_in3 = {16'h00, ~b_exponent};
		diff = add_out3[7:0];

		if (diff > 8) begin
			o_sign = a_sign;
			o_exponent = a_exponent;
			o_mantissa = a_mantissa;
			end
		else begin
		shift_n0 = diff[2:0];
		shift_in0 = {24'h00, b_mantissa};
		tmp_mantissa = {16'h00, shift_out0};
        if (a_sign == b_sign) begin

		  add_a_in4 = a_mantissa;
		  add_b_in4 = tmp_mantissa;
		  o_mantissa = add_out4;
		  end
        else begin

			add_a_in5 = a_mantissa;
			add_b_in5 = ~tmp_mantissa;
			o_mantissa = add_out5;
			end
		end
      end
	  else if (a_exponent < b_exponent) begin
        o_exponent = b_exponent;
        o_sign = b_sign;

		add_a_in6 = {16'h00, ~a_exponent};
		add_b_in6 = {16'h00, b_exponent};
		diff = add_out6[7:0];
		if (diff > 8) begin
			o_sign = b_sign;
			o_exponent = b_exponent;
			o_mantissa = b_mantissa;
		end
		else begin
		tmp_mantissa = a_mantissa >> diff;



        if (a_sign == b_sign) begin

		  add_a_in7 = b_mantissa;
		  add_b_in7 = tmp_mantissa;
		  o_mantissa = add_out7;
        end else begin

		  add_a_in8 = b_mantissa;
		  add_b_in8 = ~tmp_mantissa;
		  o_mantissa = add_out8;
        end
		end
      end
    end
    if(o_mantissa[24] == 1) begin

	  add_a_in9 = {16'h00, o_exponent};
	  add_b_in9 = 24'h01;
	  o_exponent = add_out9[7:0];

	  tmp_mantissa = o_mantissa[24:1];
	  o_mantissa = {1'b0, tmp_mantissa};
    end else if((o_mantissa[23] != 1) && (o_exponent != 0)) begin
      i_e = o_exponent;
      i_m = o_mantissa;
      o_exponent = o_e;
      o_mantissa = o_m;
    end
  end
endmodule