data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-IMPLICIT: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161.v:25: Signal definition not found, creating implicitly: \'feedback_qd\'\nassign feedback_qd = ent_and_enp & qc & qb & qa;\n       ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161.v:36: Signal definition not found, creating implicitly: \'feedback_qc\'\n                                                                                                              : ... Suggested alternative: \'feedback_qd\'\nassign feedback_qc =  ent_and_enp & qb & qa;\n       ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161.v:47: Signal definition not found, creating implicitly: \'feedback_qb\'\n                                                                                                              : ... Suggested alternative: \'feedback_qc\'\nassign feedback_qb = ent_and_enp & qa;\n       ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161.v:58: Signal definition not found, creating implicitly: \'feedback_qa\'\n                                                                                                              : ... Suggested alternative: \'feedback_qb\'\nassign feedback_qa = ent_and_enp;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161.v:27: Cannot find file containing module: \'output_section\'\noutput_section OUTPUT_QD (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161,data/full_repos/permissive/174155074/output_section\n             data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161,data/full_repos/permissive/174155074/output_section.v\n             data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161,data/full_repos/permissive/174155074/output_section.sv\n             output_section\n             output_section.v\n             output_section.sv\n             obj_dir/output_section\n             obj_dir/output_section.v\n             obj_dir/output_section.sv\n%Error: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161.v:38: Cannot find file containing module: \'output_section\'\noutput_section OUTPUT_QC (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161.v:49: Cannot find file containing module: \'output_section\'\noutput_section OUTPUT_QB (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/jeff-74x161.v:60: Cannot find file containing module: \'output_section\'\noutput_section OUTPUT_QA (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module jeff_74x161(
    input           clr_bar,
    input           ld_bar,
    input           ent,
    input           enp,
    input           clk,
    input           a, b, c, d,
    output          qa, qb, qc, qd,
    output          rco
);

wire ld;
wire ent_and_enp;

assign rco = ent & qd & qc & qb & qa;

assign ld = ~ld_bar;
assign ent_and_enp = ent & enp;

assign feedback_qd = ent_and_enp & qc & qb & qa;

output_section OUTPUT_QD (
    .clr_bar(clr_bar),
    .ld(ld),
    .feedback(feedback_qd),
    .clk(clk),
    .data(d),
    .q(qd)
);

assign feedback_qc =  ent_and_enp & qb & qa;

output_section OUTPUT_QC (
    .clr_bar(clr_bar),
    .ld(ld),
    .feedback(feedback_qc),
    .clk(clk),
    .data(c),
    .q(qc)
);

assign feedback_qb = ent_and_enp & qa;

output_section OUTPUT_QB (
    .clr_bar(clr_bar),
    .ld(ld),
    .feedback(feedback_qb),
    .clk(clk),
    .data(b),
    .q(qb)
);

assign feedback_qa = ent_and_enp;

output_section OUTPUT_QA (
    .clr_bar(clr_bar),
    .ld(ld),
    .feedback(feedback_qa),
    .clk(clk),
    .data(a),
    .q(qa)
);

endmodule
module jeff_74x161(
    input           clr_bar,
    input           ld_bar,
    input           ent,
    input           enp,
    input           clk,
    input           a, b, c, d,
    output          qa, qb, qc, qd,
    output          rco
);


wire ld;
wire ent_and_enp;

assign rco = ent & qd & qc & qb & qa;

assign ld = ~ld_bar;
assign ent_and_enp = ent & enp;

assign feedback_qd = ent_and_enp & qc & qb & qa;

output_section OUTPUT_QD (
    .clr_bar(clr_bar),
    .ld(ld),
    .feedback(feedback_qd),
    .clk(clk),
    .data(d),
    .q(qd)
);

assign feedback_qc =  ent_and_enp & qb & qa;

output_section OUTPUT_QC (
    .clr_bar(clr_bar),
    .ld(ld),
    .feedback(feedback_qc),
    .clk(clk),
    .data(c),
    .q(qc)
);

assign feedback_qb = ent_and_enp & qa;

output_section OUTPUT_QB (
    .clr_bar(clr_bar),
    .ld(ld),
    .feedback(feedback_qb),
    .clk(clk),
    .data(b),
    .q(qb)
);

assign feedback_qa = ent_and_enp;

output_section OUTPUT_QA (
    .clr_bar(clr_bar),
    .ld(ld),
    .feedback(feedback_qa),
    .clk(clk),
    .data(a),
    .q(qa)
);

endmodule