data/full_repos/permissive/18082343/subleq.v
1: b"%Error: data/full_repos/permissive/18082343/subleq.v:69: Cannot find file containing module: 'mem'\nmem mem0(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/18082343,data/full_repos/permissive/18082343/mem\n             data/full_repos/permissive/18082343,data/full_repos/permissive/18082343/mem.v\n             data/full_repos/permissive/18082343,data/full_repos/permissive/18082343/mem.sv\n             mem\n             mem.v\n             mem.sv\n             obj_dir/mem\n             obj_dir/mem.v\n             obj_dir/mem.sv\n%Error: Exiting due to 1 error(s)\n"
module subleq(
	input iClock,
	input iReset,
	output [2:0] ocounter,
	output [31:0] oIP,
	output [31:0] oA,
	output [31:0] oB,
	output [31:0] oJ,
	output [31:0] oq,
	output [31:0] osub,
	output oleq
);




assign ocounter = counter;
assign oIP = IP;
assign oA = A;
assign oB = B;
assign oJ = J;
assign oq = q;
assign osub = sub;
assign oleq = leq;




reg [2:0] counter;
initial begin
	counter <= 3'd0;
end
always @(posedge iClock) begin
	counter <= (iReset || counter == 3'd5) ? 3'd0 : counter + 3'd1;
end




reg [31:0] IP;
initial begin
	IP <= 32'd0;
end
always @(posedge iClock) begin
	if (iReset) begin
		IP <= 32'd0;
	end else if (counter <= 3'd2) begin
		IP <= IP + 32'd1;
	end else if (counter == 3'd5) begin
		IP <= leq ? J : IP;
	end
end




wire [31:0] address;
wire [31:0] q;
always @(counter, IP, A, B) begin
	if (counter <= 3'd2) begin
		address <= IP;
	end else if (counter == 3'd3) begin
		address <= A;
	end else begin
		address <= B;
	end
end
mem mem0(
	.address(address[12:0]),
	.clock(iClock),
	.data(sub),
	.wren(counter == 3'd5),
	.q(q)
);




reg [31:0] A, B, J;
always @(posedge iClock) begin

	if (counter == 3'd1 || counter == 3'd4) begin
		A <= q;
	end
	

	if (counter == 3'd2) begin
		B <= q;
	end
	

	if (counter == 3'd3) begin
		J <= q;
	end
end




wire [31:0] sub;
assign sub = q - A;
wire leq;
assign leq = sub[31] || sub == 32'b0;

endmodule
module subleq(
	input iClock,
	input iReset,
	output [2:0] ocounter,
	output [31:0] oIP,
	output [31:0] oA,
	output [31:0] oB,
	output [31:0] oJ,
	output [31:0] oq,
	output [31:0] osub,
	output oleq
);





assign ocounter = counter;
assign oIP = IP;
assign oA = A;
assign oB = B;
assign oJ = J;
assign oq = q;
assign osub = sub;
assign oleq = leq;




reg [2:0] counter;
initial begin
	counter <= 3'd0;
end
always @(posedge iClock) begin
	counter <= (iReset || counter == 3'd5) ? 3'd0 : counter + 3'd1;
end




reg [31:0] IP;
initial begin
	IP <= 32'd0;
end
always @(posedge iClock) begin
	if (iReset) begin
		IP <= 32'd0;
	end else if (counter <= 3'd2) begin
		IP <= IP + 32'd1;
	end else if (counter == 3'd5) begin
		IP <= leq ? J : IP;
	end
end




wire [31:0] address;
wire [31:0] q;
always @(counter, IP, A, B) begin
	if (counter <= 3'd2) begin
		address <= IP;
	end else if (counter == 3'd3) begin
		address <= A;
	end else begin
		address <= B;
	end
end
mem mem0(
	.address(address[12:0]),
	.clock(iClock),
	.data(sub),
	.wren(counter == 3'd5),
	.q(q)
);




reg [31:0] A, B, J;
always @(posedge iClock) begin

	if (counter == 3'd1 || counter == 3'd4) begin
		A <= q;
	end
	

	if (counter == 3'd2) begin
		B <= q;
	end
	

	if (counter == 3'd3) begin
		J <= q;
	end
end




wire [31:0] sub;
assign sub = q - A;
wire leq;
assign leq = sub[31] || sub == 32'b0;

endmodule