data/full_repos/permissive/136510272/sketchs/divisor/icarus.v
 line:10: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/136510272/sketchs/divisor/icarus.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #0.5 clk         = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136510272/sketchs/divisor/icarus.v:10: Unsupported: Ignoring delay on this delayed statement.\ninitial begin clk = 1; #2000 $finish; end\n                       ^\n%Error: data/full_repos/permissive/136510272/sketchs/divisor/icarus.v:11: Unsupported or unknown PLI call: $dumpfile\ninitial begin $dumpfile("result.vcd"); $dumpvars(0, main); end\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/136510272/sketchs/divisor/icarus.v:11: Unsupported or unknown PLI call: $dumpvars\ninitial begin $dumpfile("result.vcd"); $dumpvars(0, main); end\n                                       ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;



reg         clk;
always #0.5 clk         = ~clk;

initial begin clk = 1; #2000 $finish; end
initial begin $dumpfile("result.vcd"); $dumpvars(0, main); end






reg     [31:0] operand_A        = 32'h0080BABA;
reg     [31:0] operand_B        = 32'h00000002;


reg     [31:0] remainder        = 32'h00000000;
reg     [31:0] result           = 32'h00000000;
wire    [32:0] subtract         = remainder - operand_B;
wire    [30:0] remainder_next   = subtract[32] ? remainder[30:0] : subtract[30:0];
reg     [5:0]  ticker           = 1'b0;

always @(posedge clk) begin


    if (ticker != 6'd33) begin     


        remainder <= {remainder_next, operand_A[31]};
        result    <= {result[30:0], subtract[32] ^ 1'b1};
        operand_A <= {operand_A[30:0], 1'b0};
        

        ticker    <= ticker + 1'b1;
    
    end

end

endmodule
module main;




reg         clk;
always #0.5 clk         = ~clk;

initial begin clk = 1; #2000 $finish; end
initial begin $dumpfile("result.vcd"); $dumpvars(0, main); end






reg     [31:0] operand_A        = 32'h0080BABA;
reg     [31:0] operand_B        = 32'h00000002;


reg     [31:0] remainder        = 32'h00000000;
reg     [31:0] result           = 32'h00000000;
wire    [32:0] subtract         = remainder - operand_B;
wire    [30:0] remainder_next   = subtract[32] ? remainder[30:0] : subtract[30:0];
reg     [5:0]  ticker           = 1'b0;

always @(posedge clk) begin


    if (ticker != 6'd33) begin     


        remainder <= {remainder_next, operand_A[31]};
        result    <= {result[30:0], subtract[32] ^ 1'b1};
        operand_A <= {operand_A[30:0], 1'b0};
        

        ticker    <= ticker + 1'b1;
    
    end

end

endmodule