data/full_repos/permissive/16507090/uart/uart.v
 line:9: before: "["
1: b"%Error: data/full_repos/permissive/16507090/uart/uart.v:21: Can't find definition of variable: 'bytastart'\n                                                          : ... Suggested alternative: 'bytestart'\n initial bytastart=1;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/16507090/uart/uart.v:29: Can't find definition of variable: 'skip'\n  if (clkdivcnt==skip) begin\n                 ^~~~\n%Error: Exiting due to 2 error(s)\n"
module uart_tx
#(
	parameter	clock_speed=100_000_000,
	parameter	baud_rate=115200
)
(
	output	reg			tx,
	input				clk,
	input		[7:0][63:0]	data_buffer,
	input				endianness,
	input				proceed,
	input		[19:0]		skipcycles,
	output	reg	[2:0]		bytepos,
	output	reg	[5:0]		bufferpos,
	output	reg			bytestart,
	output	reg			byteend
);
	initial tx=1;
	initial bytepos=0;
	initial bufferpos=0;
	initial bytastart=1;
	initial byteend=0;

	reg [19:0] clkdivcnt=0;
	reg preamble=1;

	always @(posedge clk) begin
		clkdivcnt<=proceed? clkdivcnt+1 : 0;
		if (clkdivcnt==skip) begin
			clkdivcnt<=0;

			tx<=data_buffer[bytepos][bufferpos];
			bytepos<=bytepos==7? 0 : bytepos+1;
			bufferpos<=bufferpos==63? 0 : bytepos==7? bufferpos+1 : bufferpos;
		end
	end
endmodule
module uart_tx
#(
	parameter	clock_speed=100_000_000,
	parameter	baud_rate=115200
)
(
	output	reg			tx,
	input				clk,
	input		[7:0][63:0]	data_buffer,
	input				endianness,
	input				proceed,
	input		[19:0]		skipcycles,
	output	reg	[2:0]		bytepos,
	output	reg	[5:0]		bufferpos,
	output	reg			bytestart,
	output	reg			byteend
);

	initial tx=1;
	initial bytepos=0;
	initial bufferpos=0;
	initial bytastart=1;
	initial byteend=0;

	reg [19:0] clkdivcnt=0;
	reg preamble=1;

	always @(posedge clk) begin
		clkdivcnt<=proceed? clkdivcnt+1 : 0;
		if (clkdivcnt==skip) begin
			clkdivcnt<=0;

			tx<=data_buffer[bytepos][bufferpos];
			bytepos<=bytepos==7? 0 : bytepos+1;
			bufferpos<=bufferpos==63? 0 : bytepos==7? bufferpos+1 : bufferpos;
		end
	end
endmodule