data/full_repos/permissive/174155074/basic-code/combinational-logic/not1/not1-tb.v
 line:38: before: "$"
1: b'%Error: data/full_repos/permissive/174155074/basic-code/combinational-logic/not1/not1-tb.v:19: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("not1-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/basic-code/combinational-logic/not1/not1-tb.v:20: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, not1_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/basic-code/combinational-logic/not1/not1-tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #15; A = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174155074/basic-code/combinational-logic/not1/not1-tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #20; A = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/basic-code/combinational-logic/not1/not1-tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #20; A = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/basic-code/combinational-logic/not1/not1-tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #20; A = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/basic-code/combinational-logic/not1/not1-tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #20; A = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/basic-code/combinational-logic/not1/not1-tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module not1_tb;


reg        A;
wire       Y;


not1 uut(
    .a(A),
    .y(Y)
);


initial begin
    $dumpfile("not1-tb.vcd");
    $dumpvars(0, not1_tb);
end


initial begin
    $display("test start");
    A = 0;

    #15; A = 0;
    #20; A = 1;
    #20; A = 0;
    #20; A = 1;

    #20; A = 0;


    #20

    $display("test complete");
    $finish;
end

endmodule
module not1_tb;



reg        A;
wire       Y;


not1 uut(
    .a(A),
    .y(Y)
);


initial begin
    $dumpfile("not1-tb.vcd");
    $dumpvars(0, not1_tb);
end


initial begin
    $display("test start");
    A = 0;

    #15; A = 0;
    #20; A = 1;
    #20; A = 0;
    #20; A = 1;

    #20; A = 0;


    #20

    $display("test complete");
    $finish;
end

endmodule