data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_rp_ep_sim/testbench/sonic_rp_ep_sim_tb/simulation/submodules/sonic_rp_ep_sim_tb_sonic_rp_ep_sim_inst.v
1: b"%Error: data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_rp_ep_sim/testbench/sonic_rp_ep_sim_tb/simulation/submodules/sonic_rp_ep_sim_tb_sonic_rp_ep_sim_inst.v:16: Cannot find file containing module: 'sonic_fast_sim_top'\n sonic_fast_sim_top sonic_rp_ep_top_0 (\n ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_rp_ep_sim/testbench/sonic_rp_ep_sim_tb/simulation/submodules,data/full_repos/permissive/18477150/sonic_fast_sim_top\n             data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_rp_ep_sim/testbench/sonic_rp_ep_sim_tb/simulation/submodules,data/full_repos/permissive/18477150/sonic_fast_sim_top.v\n             data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_rp_ep_sim/testbench/sonic_rp_ep_sim_tb/simulation/submodules,data/full_repos/permissive/18477150/sonic_fast_sim_top.sv\n             sonic_fast_sim_top\n             sonic_fast_sim_top.v\n             sonic_fast_sim_top.sv\n             obj_dir/sonic_fast_sim_top\n             obj_dir/sonic_fast_sim_top.v\n             obj_dir/sonic_fast_sim_top.sv\n%Error: data/full_repos/permissive/18477150/testsuite/mg_sim/sonic_rp_ep/sonic_rp_ep_sim/testbench/sonic_rp_ep_sim_tb/simulation/submodules/sonic_rp_ep_sim_tb_sonic_rp_ep_sim_inst.v:25: Cannot find file containing module: 'altera_reset_controller'\n altera_reset_controller #(\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module sonic_rp_ep_sim_tb_sonic_rp_ep_sim_inst (
		input  wire        reset_0_reset_n,
		output wire [39:0] xcvr_tx_datain_data,
		input  wire        reset_reset_n,
		input  wire [39:0] xcvr_rx_dataout_data,
		input  wire        clk_clk,
		input  wire        clk_0_clk
	);

	wire    rst_controller_reset_out_reset;

	sonic_fast_sim_top sonic_rp_ep_top_0 (
		.pld_clk         (clk_clk),
		.rstn            (~rst_controller_reset_out_reset),
		.xcvr_rx_clkout  (clk_0_clk),
		.xcvr_tx_clkout  (clk_0_clk),
		.xcvr_tx_datain  (xcvr_tx_datain_data),
		.xcvr_rx_dataout (xcvr_rx_dataout_data)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~reset_reset_n),
		.clk        (clk_clk),
		.reset_out  (rst_controller_reset_out_reset),
		.reset_in1  (1'b0),
		.reset_in2  (1'b0),
		.reset_in3  (1'b0),
		.reset_in4  (1'b0),
		.reset_in5  (1'b0),
		.reset_in6  (1'b0),
		.reset_in7  (1'b0),
		.reset_in8  (1'b0),
		.reset_in9  (1'b0),
		.reset_in10 (1'b0),
		.reset_in11 (1'b0),
		.reset_in12 (1'b0),
		.reset_in13 (1'b0),
		.reset_in14 (1'b0),
		.reset_in15 (1'b0)
	);

endmodule
module sonic_rp_ep_sim_tb_sonic_rp_ep_sim_inst (
		input  wire        reset_0_reset_n,
		output wire [39:0] xcvr_tx_datain_data,
		input  wire        reset_reset_n,
		input  wire [39:0] xcvr_rx_dataout_data,
		input  wire        clk_clk,
		input  wire        clk_0_clk
	);


	wire    rst_controller_reset_out_reset;

	sonic_fast_sim_top sonic_rp_ep_top_0 (
		.pld_clk         (clk_clk),
		.rstn            (~rst_controller_reset_out_reset),
		.xcvr_rx_clkout  (clk_0_clk),
		.xcvr_tx_clkout  (clk_0_clk),
		.xcvr_tx_datain  (xcvr_tx_datain_data),
		.xcvr_rx_dataout (xcvr_rx_dataout_data)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~reset_reset_n),
		.clk        (clk_clk),
		.reset_out  (rst_controller_reset_out_reset),
		.reset_in1  (1'b0),
		.reset_in2  (1'b0),
		.reset_in3  (1'b0),
		.reset_in4  (1'b0),
		.reset_in5  (1'b0),
		.reset_in6  (1'b0),
		.reset_in7  (1'b0),
		.reset_in8  (1'b0),
		.reset_in9  (1'b0),
		.reset_in10 (1'b0),
		.reset_in11 (1'b0),
		.reset_in12 (1'b0),
		.reset_in13 (1'b0),
		.reset_in14 (1'b0),
		.reset_in15 (1'b0)
	);

endmodule