data/full_repos/permissive/158845296/tests/tb_processor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/158845296/tests/tb_processor.v:7: Unsupported: Ignoring delay on this delayed statement.\n            #1; clock = 1\'b1;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/158845296/tests/tb_processor.v:8: Unsupported: Ignoring delay on this delayed statement.\n            #1; clock = 1\'b0;\n            ^\n%Error: data/full_repos/permissive/158845296/tests/tb_processor.v:12: Cannot find file containing module: \'processor\'\n    processor DUT\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158845296/tests,data/full_repos/permissive/158845296/processor\n             data/full_repos/permissive/158845296/tests,data/full_repos/permissive/158845296/processor.v\n             data/full_repos/permissive/158845296/tests,data/full_repos/permissive/158845296/processor.sv\n             processor\n             processor.v\n             processor.sv\n             obj_dir/processor\n             obj_dir/processor.v\n             obj_dir/processor.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_processor();

    reg clock = 1'b0;
    
    initial begin
        while(1) begin
            #1; clock = 1'b1;
            #1; clock = 1'b0;
        end
    end
    
    processor DUT
    (
        .clock  (clock),
        .reset  (1'b0)
    );

endmodule
module tb_processor();


    reg clock = 1'b0;
    
    initial begin
        while(1) begin
            #1; clock = 1'b1;
            #1; clock = 1'b0;
        end
    end
    
    processor DUT
    (
        .clock  (clock),
        .reset  (1'b0)
    );

endmodule