data/full_repos/permissive/143278/ivltests/pr991.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr991.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/pr991.v:15: Unsupported: Use $display with %b format instead: $displayb\n    $displayb(_d2);    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr991.v:16: Unsupported: Use $display with %b format instead: $displayb\n    $displayb(test);   \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr991.v:17: Unsupported: Use $display with %b format instead: $displayb\n    $displayb(test1);  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr991.v:18: Unsupported: Use $display with %b format instead: $displayb\n    $displayb(test2);  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr991.v:19: Unsupported: Use $display with %b format instead: $displayb\n    $displayb(test3);  \n    ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bug();
  wire _d1,_d2,test,test1,test2,test3;
  assign _d1 = 1;
  assign _d2 = 0;
  assign test = (_d1 && _d2) != 0;
  assign test1 = (_d1 && _d2) == 0;
  assign test2 = (_d1 && _d2) !== 0;
  assign test3 = (_d1 && _d2) === 0;
  initial begin
    #1;
    $displayb(_d2);
    $displayb(test);
    $displayb(test1);
    $displayb(test2);
    $displayb(test3);
  end

endmodule
module bug();

  wire _d1,_d2,test,test1,test2,test3;
  assign _d1 = 1;
  assign _d2 = 0;
  assign test = (_d1 && _d2) != 0;
  assign test1 = (_d1 && _d2) == 0;
  assign test2 = (_d1 && _d2) !== 0;
  assign test3 = (_d1 && _d2) === 0;
  initial begin
    #1;
    $displayb(_d2);
    $displayb(test);
    $displayb(test1);
    $displayb(test2);
    $displayb(test3);
  end

endmodule