data/full_repos/permissive/159902111/PCPU_INT/Keep.v
1: b'%Warning-WIDTH: data/full_repos/permissive/159902111/PCPU_INT/Keep.v:17: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'Cause_i\' generates 2 bits.\n                                                                       : ... In instance Keep\n    else if (CauseEPCWrite_i && !Cause_i)\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Keep(
  input      clk,
  input      rst,
  input      enable_i,
  input      Jump_i,
  input      CauseEPCWrite_i,
  input[1:0] Cause_i,
  output     Key_o
  );
  reg [1:0] Key;
  always@(posedge clk or posedge rst)
  begin
    if (rst) Key = 2'b0;
    else if (CauseEPCWrite_i && !Cause_i)
    begin

    end
    else begin
      Key[1] = Key[0];
      Key[0] = enable_i | Jump_i;
    end
  end
  assign Key_o = Key[0];
endmodule
module Keep(
  input      clk,
  input      rst,
  input      enable_i,
  input      Jump_i,
  input      CauseEPCWrite_i,
  input[1:0] Cause_i,
  output     Key_o
  );

  reg [1:0] Key;
  always@(posedge clk or posedge rst)
  begin
    if (rst) Key = 2'b0;
    else if (CauseEPCWrite_i && !Cause_i)
    begin

    end
    else begin
      Key[1] = Key[0];
      Key[0] = enable_i | Jump_i;
    end
  end
  assign Key_o = Key[0];
endmodule