data/full_repos/permissive/21051978/processor/unsmultb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/21051978/processor/unsmultb.v:25: Cannot find include file: unsmul.v\n`include "unsmul.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/unsmul.v\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/unsmul.v.v\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/unsmul.v.sv\n             unsmul.v\n             unsmul.v.v\n             unsmul.v.sv\n             obj_dir/unsmul.v\n             obj_dir/unsmul.v.v\n             obj_dir/unsmul.v.sv\n%Error: data/full_repos/permissive/21051978/processor/unsmultb.v:26: Cannot find include file: control.h\n`include "control.h" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/unsmultb.v:130: Define or directive not defined: \'`w8\'\n  c_ww=(`w8+2\'b01);\n        ^~~\n%Error: data/full_repos/permissive/21051978/processor/unsmultb.v:131: Define or directive not defined: \'`aluwmulou\'\n  a_op=`aluwmulou;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/unsmultb.v:131: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmulou;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/unsmultb.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/21051978/processor/unsmultb.v:139: Define or directive not defined: \'`w16\'\n  c_ww=(`w16+2\'b01);\n        ^~~~\n%Error: data/full_repos/permissive/21051978/processor/unsmultb.v:140: Define or directive not defined: \'`aluwmulou\'\n  a_op=`aluwmulou;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/unsmultb.v:140: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmulou;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/unsmultb.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n'
module tb_arrmul();


	


wire [0:127] res;
	
	
	
	
	
	
	

	


reg [0:127] r_A;

reg [0:127] r_B;

	reg [0:1] c_ww;

	reg [0:4] a_op;

reg [0:127] e_r;
	
	
	
	
	
	

	


	
	

	
	

	

	arrmul am (



		r_A,r_B,c_ww,a_op,res);
		
	
	



	initial
	begin

		$display($time, " << Starting the simulation >>");	
		
		

		r_A=128'h0102030405060708090aff0c0dff0fff;
		r_B=128'h01010202030303031004040508000fff;
		e_r=128'h00020008001200180028003c0000fe01;
		c_ww=(`w8+2'b01);
		a_op=`aluwmulou;
		
		
		#10

		r_A=128'h0001000200000008000f10bff103ffff;
		r_B=128'h0002000400060008000c001000120014;
		e_r=128'h000000080000004000010bf00013ffec;
		c_ww=(`w16+2'b01);
		a_op=`aluwmulou;
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_arrmul();



	


wire [0:127] res;
	
	
	
	
	
	
	

	


reg [0:127] r_A;

reg [0:127] r_B;

	reg [0:1] c_ww;

	reg [0:4] a_op;

reg [0:127] e_r;
	
	
	
	
	
	

	


	
	

	
	

	

	arrmul am (



		r_A,r_B,c_ww,a_op,res);
		
	
	



	initial
	begin

		$display($time, " << Starting the simulation >>");	
		
		

		r_A=128'h0102030405060708090aff0c0dff0fff;
		r_B=128'h01010202030303031004040508000fff;
		e_r=128'h00020008001200180028003c0000fe01;
		c_ww=(`w8+2'b01);
		a_op=`aluwmulou;
		
		
		#10

		r_A=128'h0001000200000008000f10bff103ffff;
		r_B=128'h0002000400060008000c001000120014;
		e_r=128'h000000080000004000010bf00013ffec;
		c_ww=(`w16+2'b01);
		a_op=`aluwmulou;
		
		
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule