data/full_repos/permissive/174155074/basic-code/combinational-logic/nand4/nand4.v
data/verilator_xmls/ef308575-ff00-46bc-8a69-44a7a911524a.xml
module nand4(
    input           a, b, c, d,
    output          y
);


assign y = ~(a & b & c & d);

endmodule
module nand4(
    input           a, b, c, d,
    output          y
);



assign y = ~(a & b & c & d);

endmodule