data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v
1: b'%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:63: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v.v\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:65: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:81: Define or directive not defined: \'`OR1200_OPERAND_WIDTH\'\nparameter dw = `OR1200_OPERAND_WIDTH;\n               ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter dw = `OR1200_OPERAND_WIDTH;\n                                    ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:82: Define or directive not defined: \'`OR1200_REGFILE_ADDR_WIDTH\'\nparameter aw = `OR1200_REGFILE_ADDR_WIDTH;\n               ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:82: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter aw = `OR1200_REGFILE_ADDR_WIDTH;\n                                         ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:203: Define or directive not defined: \'`OR1200_RST_EVENT\'\nalways @(posedge clk or `OR1200_RST_EVENT rst)\n                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:204: Define or directive not defined: \'`OR1200_RST_VALUE\'\n if (rst == `OR1200_RST_VALUE) begin\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:204: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `OR1200_RST_VALUE) begin\n                             ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:249: Define or directive not defined: \'`OR1200_RST_EVENT\'\nalways @(posedge clk or `OR1200_RST_EVENT rst)\n                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:250: Define or directive not defined: \'`OR1200_RST_VALUE\'\n if (rst == `OR1200_RST_VALUE) begin\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:298: Define or directive not defined: \'`OR1200_RST_EVENT\'\nalways @(posedge clk or `OR1200_RST_EVENT rst)\n                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:299: Define or directive not defined: \'`OR1200_RST_VALUE\'\n if (rst == `OR1200_RST_VALUE) begin\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_rfram_generic.v:299: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `OR1200_RST_VALUE) begin\n                             ^\n%Error: Exiting due to 14 error(s)\n'
module or1200_rfram_generic(

	clk, rst,


	ce_a, addr_a, do_a,


	ce_b, addr_b, do_b,


	ce_w, we_w, addr_w, di_w
);

parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;








input				clk;
input				rst;




input				ce_a;
input	[aw-1:0]		addr_a;
output	[dw-1:0]		do_a;




input				ce_b;
input	[aw-1:0]		addr_b;
output	[dw-1:0]		do_b;




input				ce_w;
input				we_w;
input	[aw-1:0]		addr_w;
input	[dw-1:0]		di_w;




reg	[aw-1:0]		intaddr_a;
reg	[aw-1:0]		intaddr_b;
`ifdef OR1200_RFRAM_16REG
reg	[16*dw-1:0]		mem;
`else
reg	[32*dw-1:0]		mem;
`endif
reg	[dw-1:0]		do_a;
reg	[dw-1:0]		do_b;

`ifdef verilator


   function [31:0] get_gpr;

      input [aw-1:0] 		gpr_no;

      get_gpr = { mem[gpr_no*32 + 31], mem[gpr_no*32 + 30],
                  mem[gpr_no*32 + 29], mem[gpr_no*32 + 28],
                  mem[gpr_no*32 + 27], mem[gpr_no*32 + 26],
                  mem[gpr_no*32 + 25], mem[gpr_no*32 + 24],
                  mem[gpr_no*32 + 23], mem[gpr_no*32 + 22],
                  mem[gpr_no*32 + 21], mem[gpr_no*32 + 20],
                  mem[gpr_no*32 + 19], mem[gpr_no*32 + 18],
                  mem[gpr_no*32 + 17], mem[gpr_no*32 + 16],
                  mem[gpr_no*32 + 15], mem[gpr_no*32 + 14],
                  mem[gpr_no*32 + 13], mem[gpr_no*32 + 12],
                  mem[gpr_no*32 + 11], mem[gpr_no*32 + 10],
                  mem[gpr_no*32 +  9], mem[gpr_no*32 +  8],
                  mem[gpr_no*32 +  7], mem[gpr_no*32 +  6],
                  mem[gpr_no*32 +  5], mem[gpr_no*32 +  4],
                  mem[gpr_no*32 +  3], mem[gpr_no*32 +  2],
                  mem[gpr_no*32 +  1], mem[gpr_no*32 +  0] };
      
   endfunction



   function [31:0] set_gpr;

      input [aw-1:0] 		gpr_no;
      input [dw-1:0] 		value;

      mem[gpr_no*32 + 31]   = value[31];
      mem[gpr_no*32 + 30] = value[30];
      mem[gpr_no*32 + 29]  = value[29];
      mem[gpr_no*32 + 28] = value[28];
      mem[gpr_no*32 + 27]  = value[27];
      mem[gpr_no*32 + 26] = value[26];
      mem[gpr_no*32 + 25]  = value[25];
      mem[gpr_no*32 + 24] = value[24];
      mem[gpr_no*32 + 23]  = value[23];
      mem[gpr_no*32 + 22] = value[22];
      mem[gpr_no*32 + 21]  = value[21];
      mem[gpr_no*32 + 20] = value[20];
      mem[gpr_no*32 + 19]  = value[19];
      mem[gpr_no*32 + 18] = value[18];
      mem[gpr_no*32 + 17]  = value[17];
      mem[gpr_no*32 + 16] = value[16];
      mem[gpr_no*32 + 15]  = value[15];
      mem[gpr_no*32 + 14] = value[14];
      mem[gpr_no*32 + 13]  = value[13];
      mem[gpr_no*32 + 12] = value[12];
      mem[gpr_no*32 + 11]  = value[11];
      mem[gpr_no*32 + 10] = value[10];
      mem[gpr_no*32 +  9]  = value[ 9];
      mem[gpr_no*32 +  8] = value[ 8];
      mem[gpr_no*32 +  7]  = value[ 7];
      mem[gpr_no*32 +  6] = value[ 6];
      mem[gpr_no*32 +  5]  = value[ 5];
      mem[gpr_no*32 +  4] = value[ 4];
      mem[gpr_no*32 +  3]  = value[ 3];
      mem[gpr_no*32 +  2] = value[ 2];
      mem[gpr_no*32 +  1]  = value[ 1];
      mem[gpr_no*32 +  0] = value[ 0];

      set_gpr = 0;
      
   endfunction
`endif
   



always @(posedge clk or `OR1200_RST_EVENT rst)
	if (rst == `OR1200_RST_VALUE) begin
		mem <=  {512'h0, 512'h0};
	end
	else if (ce_w & we_w)
		case (addr_w)
			5'd01: mem[32*1+31:32*1] <=  di_w;
			5'd02: mem[32*2+31:32*2] <=  di_w;
			5'd03: mem[32*3+31:32*3] <=  di_w;
			5'd04: mem[32*4+31:32*4] <=  di_w;
			5'd05: mem[32*5+31:32*5] <=  di_w;
			5'd06: mem[32*6+31:32*6] <=  di_w;
			5'd07: mem[32*7+31:32*7] <=  di_w;
			5'd08: mem[32*8+31:32*8] <=  di_w;
			5'd09: mem[32*9+31:32*9] <=  di_w;
			5'd10: mem[32*10+31:32*10] <=  di_w;
			5'd11: mem[32*11+31:32*11] <=  di_w;
			5'd12: mem[32*12+31:32*12] <=  di_w;
			5'd13: mem[32*13+31:32*13] <=  di_w;
			5'd14: mem[32*14+31:32*14] <=  di_w;
			5'd15: mem[32*15+31:32*15] <=  di_w;
`ifdef OR1200_RFRAM_16REG
`else
			5'd16: mem[32*16+31:32*16] <=  di_w;
			5'd17: mem[32*17+31:32*17] <=  di_w;
			5'd18: mem[32*18+31:32*18] <=  di_w;
			5'd19: mem[32*19+31:32*19] <=  di_w;
			5'd20: mem[32*20+31:32*20] <=  di_w;
			5'd21: mem[32*21+31:32*21] <=  di_w;
			5'd22: mem[32*22+31:32*22] <=  di_w;
			5'd23: mem[32*23+31:32*23] <=  di_w;
			5'd24: mem[32*24+31:32*24] <=  di_w;
			5'd25: mem[32*25+31:32*25] <=  di_w;
			5'd26: mem[32*26+31:32*26] <=  di_w;
			5'd27: mem[32*27+31:32*27] <=  di_w;
			5'd28: mem[32*28+31:32*28] <=  di_w;
			5'd29: mem[32*29+31:32*29] <=  di_w;
			5'd30: mem[32*30+31:32*30] <=  di_w;
			5'd31: mem[32*31+31:32*31] <=  di_w;
`endif
			default: mem[32*0+31:32*0] <=  32'h0000_0000;
		endcase




always @(posedge clk or `OR1200_RST_EVENT rst)
	if (rst == `OR1200_RST_VALUE) begin
		intaddr_a <=  5'h00;
	end
	else if (ce_a)
		intaddr_a <=  addr_a;

always @(mem or intaddr_a)
	case (intaddr_a)
		5'd01: do_a = mem[32*1+31:32*1];
		5'd02: do_a = mem[32*2+31:32*2];
		5'd03: do_a = mem[32*3+31:32*3];
		5'd04: do_a = mem[32*4+31:32*4];
		5'd05: do_a = mem[32*5+31:32*5];
		5'd06: do_a = mem[32*6+31:32*6];
		5'd07: do_a = mem[32*7+31:32*7];
		5'd08: do_a = mem[32*8+31:32*8];
		5'd09: do_a = mem[32*9+31:32*9];
		5'd10: do_a = mem[32*10+31:32*10];
		5'd11: do_a = mem[32*11+31:32*11];
		5'd12: do_a = mem[32*12+31:32*12];
		5'd13: do_a = mem[32*13+31:32*13];
		5'd14: do_a = mem[32*14+31:32*14];
		5'd15: do_a = mem[32*15+31:32*15];
`ifdef OR1200_RFRAM_16REG
`else
		5'd16: do_a = mem[32*16+31:32*16];
		5'd17: do_a = mem[32*17+31:32*17];
		5'd18: do_a = mem[32*18+31:32*18];
		5'd19: do_a = mem[32*19+31:32*19];
		5'd20: do_a = mem[32*20+31:32*20];
		5'd21: do_a = mem[32*21+31:32*21];
		5'd22: do_a = mem[32*22+31:32*22];
		5'd23: do_a = mem[32*23+31:32*23];
		5'd24: do_a = mem[32*24+31:32*24];
		5'd25: do_a = mem[32*25+31:32*25];
		5'd26: do_a = mem[32*26+31:32*26];
		5'd27: do_a = mem[32*27+31:32*27];
		5'd28: do_a = mem[32*28+31:32*28];
		5'd29: do_a = mem[32*29+31:32*29];
		5'd30: do_a = mem[32*30+31:32*30];
		5'd31: do_a = mem[32*31+31:32*31];
`endif
		default: do_a = 32'h0000_0000;
	endcase




always @(posedge clk or `OR1200_RST_EVENT rst)
	if (rst == `OR1200_RST_VALUE) begin
		intaddr_b <=  5'h00;
	end
	else if (ce_b)
		intaddr_b <=  addr_b;

always @(mem or intaddr_b)
	case (intaddr_b)
		5'd01: do_b = mem[32*1+31:32*1];
		5'd02: do_b = mem[32*2+31:32*2];
		5'd03: do_b = mem[32*3+31:32*3];
		5'd04: do_b = mem[32*4+31:32*4];
		5'd05: do_b = mem[32*5+31:32*5];
		5'd06: do_b = mem[32*6+31:32*6];
		5'd07: do_b = mem[32*7+31:32*7];
		5'd08: do_b = mem[32*8+31:32*8];
		5'd09: do_b = mem[32*9+31:32*9];
		5'd10: do_b = mem[32*10+31:32*10];
		5'd11: do_b = mem[32*11+31:32*11];
		5'd12: do_b = mem[32*12+31:32*12];
		5'd13: do_b = mem[32*13+31:32*13];
		5'd14: do_b = mem[32*14+31:32*14];
		5'd15: do_b = mem[32*15+31:32*15];
`ifdef OR1200_RFRAM_16REG
`else
		5'd16: do_b = mem[32*16+31:32*16];
		5'd17: do_b = mem[32*17+31:32*17];
		5'd18: do_b = mem[32*18+31:32*18];
		5'd19: do_b = mem[32*19+31:32*19];
		5'd20: do_b = mem[32*20+31:32*20];
		5'd21: do_b = mem[32*21+31:32*21];
		5'd22: do_b = mem[32*22+31:32*22];
		5'd23: do_b = mem[32*23+31:32*23];
		5'd24: do_b = mem[32*24+31:32*24];
		5'd25: do_b = mem[32*25+31:32*25];
		5'd26: do_b = mem[32*26+31:32*26];
		5'd27: do_b = mem[32*27+31:32*27];
		5'd28: do_b = mem[32*28+31:32*28];
		5'd29: do_b = mem[32*29+31:32*29];
		5'd30: do_b = mem[32*30+31:32*30];
		5'd31: do_b = mem[32*31+31:32*31];
`endif
		default: do_b = 32'h0000_0000;
	endcase

endmodule
module or1200_rfram_generic(

	clk, rst,


	ce_a, addr_a, do_a,


	ce_b, addr_b, do_b,


	ce_w, we_w, addr_w, di_w
);


parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;








input				clk;
input				rst;




input				ce_a;
input	[aw-1:0]		addr_a;
output	[dw-1:0]		do_a;




input				ce_b;
input	[aw-1:0]		addr_b;
output	[dw-1:0]		do_b;




input				ce_w;
input				we_w;
input	[aw-1:0]		addr_w;
input	[dw-1:0]		di_w;




reg	[aw-1:0]		intaddr_a;
reg	[aw-1:0]		intaddr_b;
`ifdef OR1200_RFRAM_16REG
reg	[16*dw-1:0]		mem;
`else
reg	[32*dw-1:0]		mem;
`endif
reg	[dw-1:0]		do_a;
reg	[dw-1:0]		do_b;

`ifdef verilator


   function [31:0] get_gpr;

      input [aw-1:0] 		gpr_no;

      get_gpr = { mem[gpr_no*32 + 31], mem[gpr_no*32 + 30],
                  mem[gpr_no*32 + 29], mem[gpr_no*32 + 28],
                  mem[gpr_no*32 + 27], mem[gpr_no*32 + 26],
                  mem[gpr_no*32 + 25], mem[gpr_no*32 + 24],
                  mem[gpr_no*32 + 23], mem[gpr_no*32 + 22],
                  mem[gpr_no*32 + 21], mem[gpr_no*32 + 20],
                  mem[gpr_no*32 + 19], mem[gpr_no*32 + 18],
                  mem[gpr_no*32 + 17], mem[gpr_no*32 + 16],
                  mem[gpr_no*32 + 15], mem[gpr_no*32 + 14],
                  mem[gpr_no*32 + 13], mem[gpr_no*32 + 12],
                  mem[gpr_no*32 + 11], mem[gpr_no*32 + 10],
                  mem[gpr_no*32 +  9], mem[gpr_no*32 +  8],
                  mem[gpr_no*32 +  7], mem[gpr_no*32 +  6],
                  mem[gpr_no*32 +  5], mem[gpr_no*32 +  4],
                  mem[gpr_no*32 +  3], mem[gpr_no*32 +  2],
                  mem[gpr_no*32 +  1], mem[gpr_no*32 +  0] };
      
   endfunction



   function [31:0] set_gpr;

      input [aw-1:0] 		gpr_no;
      input [dw-1:0] 		value;

      mem[gpr_no*32 + 31]   = value[31];
      mem[gpr_no*32 + 30] = value[30];
      mem[gpr_no*32 + 29]  = value[29];
      mem[gpr_no*32 + 28] = value[28];
      mem[gpr_no*32 + 27]  = value[27];
      mem[gpr_no*32 + 26] = value[26];
      mem[gpr_no*32 + 25]  = value[25];
      mem[gpr_no*32 + 24] = value[24];
      mem[gpr_no*32 + 23]  = value[23];
      mem[gpr_no*32 + 22] = value[22];
      mem[gpr_no*32 + 21]  = value[21];
      mem[gpr_no*32 + 20] = value[20];
      mem[gpr_no*32 + 19]  = value[19];
      mem[gpr_no*32 + 18] = value[18];
      mem[gpr_no*32 + 17]  = value[17];
      mem[gpr_no*32 + 16] = value[16];
      mem[gpr_no*32 + 15]  = value[15];
      mem[gpr_no*32 + 14] = value[14];
      mem[gpr_no*32 + 13]  = value[13];
      mem[gpr_no*32 + 12] = value[12];
      mem[gpr_no*32 + 11]  = value[11];
      mem[gpr_no*32 + 10] = value[10];
      mem[gpr_no*32 +  9]  = value[ 9];
      mem[gpr_no*32 +  8] = value[ 8];
      mem[gpr_no*32 +  7]  = value[ 7];
      mem[gpr_no*32 +  6] = value[ 6];
      mem[gpr_no*32 +  5]  = value[ 5];
      mem[gpr_no*32 +  4] = value[ 4];
      mem[gpr_no*32 +  3]  = value[ 3];
      mem[gpr_no*32 +  2] = value[ 2];
      mem[gpr_no*32 +  1]  = value[ 1];
      mem[gpr_no*32 +  0] = value[ 0];

      set_gpr = 0;
      
   endfunction
`endif
   



always @(posedge clk or `OR1200_RST_EVENT rst)
	if (rst == `OR1200_RST_VALUE) begin
		mem <=  {512'h0, 512'h0};
	end
	else if (ce_w & we_w)
		case (addr_w)
			5'd01: mem[32*1+31:32*1] <=  di_w;
			5'd02: mem[32*2+31:32*2] <=  di_w;
			5'd03: mem[32*3+31:32*3] <=  di_w;
			5'd04: mem[32*4+31:32*4] <=  di_w;
			5'd05: mem[32*5+31:32*5] <=  di_w;
			5'd06: mem[32*6+31:32*6] <=  di_w;
			5'd07: mem[32*7+31:32*7] <=  di_w;
			5'd08: mem[32*8+31:32*8] <=  di_w;
			5'd09: mem[32*9+31:32*9] <=  di_w;
			5'd10: mem[32*10+31:32*10] <=  di_w;
			5'd11: mem[32*11+31:32*11] <=  di_w;
			5'd12: mem[32*12+31:32*12] <=  di_w;
			5'd13: mem[32*13+31:32*13] <=  di_w;
			5'd14: mem[32*14+31:32*14] <=  di_w;
			5'd15: mem[32*15+31:32*15] <=  di_w;
`ifdef OR1200_RFRAM_16REG
`else
			5'd16: mem[32*16+31:32*16] <=  di_w;
			5'd17: mem[32*17+31:32*17] <=  di_w;
			5'd18: mem[32*18+31:32*18] <=  di_w;
			5'd19: mem[32*19+31:32*19] <=  di_w;
			5'd20: mem[32*20+31:32*20] <=  di_w;
			5'd21: mem[32*21+31:32*21] <=  di_w;
			5'd22: mem[32*22+31:32*22] <=  di_w;
			5'd23: mem[32*23+31:32*23] <=  di_w;
			5'd24: mem[32*24+31:32*24] <=  di_w;
			5'd25: mem[32*25+31:32*25] <=  di_w;
			5'd26: mem[32*26+31:32*26] <=  di_w;
			5'd27: mem[32*27+31:32*27] <=  di_w;
			5'd28: mem[32*28+31:32*28] <=  di_w;
			5'd29: mem[32*29+31:32*29] <=  di_w;
			5'd30: mem[32*30+31:32*30] <=  di_w;
			5'd31: mem[32*31+31:32*31] <=  di_w;
`endif
			default: mem[32*0+31:32*0] <=  32'h0000_0000;
		endcase




always @(posedge clk or `OR1200_RST_EVENT rst)
	if (rst == `OR1200_RST_VALUE) begin
		intaddr_a <=  5'h00;
	end
	else if (ce_a)
		intaddr_a <=  addr_a;

always @(mem or intaddr_a)
	case (intaddr_a)
		5'd01: do_a = mem[32*1+31:32*1];
		5'd02: do_a = mem[32*2+31:32*2];
		5'd03: do_a = mem[32*3+31:32*3];
		5'd04: do_a = mem[32*4+31:32*4];
		5'd05: do_a = mem[32*5+31:32*5];
		5'd06: do_a = mem[32*6+31:32*6];
		5'd07: do_a = mem[32*7+31:32*7];
		5'd08: do_a = mem[32*8+31:32*8];
		5'd09: do_a = mem[32*9+31:32*9];
		5'd10: do_a = mem[32*10+31:32*10];
		5'd11: do_a = mem[32*11+31:32*11];
		5'd12: do_a = mem[32*12+31:32*12];
		5'd13: do_a = mem[32*13+31:32*13];
		5'd14: do_a = mem[32*14+31:32*14];
		5'd15: do_a = mem[32*15+31:32*15];
`ifdef OR1200_RFRAM_16REG
`else
		5'd16: do_a = mem[32*16+31:32*16];
		5'd17: do_a = mem[32*17+31:32*17];
		5'd18: do_a = mem[32*18+31:32*18];
		5'd19: do_a = mem[32*19+31:32*19];
		5'd20: do_a = mem[32*20+31:32*20];
		5'd21: do_a = mem[32*21+31:32*21];
		5'd22: do_a = mem[32*22+31:32*22];
		5'd23: do_a = mem[32*23+31:32*23];
		5'd24: do_a = mem[32*24+31:32*24];
		5'd25: do_a = mem[32*25+31:32*25];
		5'd26: do_a = mem[32*26+31:32*26];
		5'd27: do_a = mem[32*27+31:32*27];
		5'd28: do_a = mem[32*28+31:32*28];
		5'd29: do_a = mem[32*29+31:32*29];
		5'd30: do_a = mem[32*30+31:32*30];
		5'd31: do_a = mem[32*31+31:32*31];
`endif
		default: do_a = 32'h0000_0000;
	endcase




always @(posedge clk or `OR1200_RST_EVENT rst)
	if (rst == `OR1200_RST_VALUE) begin
		intaddr_b <=  5'h00;
	end
	else if (ce_b)
		intaddr_b <=  addr_b;

always @(mem or intaddr_b)
	case (intaddr_b)
		5'd01: do_b = mem[32*1+31:32*1];
		5'd02: do_b = mem[32*2+31:32*2];
		5'd03: do_b = mem[32*3+31:32*3];
		5'd04: do_b = mem[32*4+31:32*4];
		5'd05: do_b = mem[32*5+31:32*5];
		5'd06: do_b = mem[32*6+31:32*6];
		5'd07: do_b = mem[32*7+31:32*7];
		5'd08: do_b = mem[32*8+31:32*8];
		5'd09: do_b = mem[32*9+31:32*9];
		5'd10: do_b = mem[32*10+31:32*10];
		5'd11: do_b = mem[32*11+31:32*11];
		5'd12: do_b = mem[32*12+31:32*12];
		5'd13: do_b = mem[32*13+31:32*13];
		5'd14: do_b = mem[32*14+31:32*14];
		5'd15: do_b = mem[32*15+31:32*15];
`ifdef OR1200_RFRAM_16REG
`else
		5'd16: do_b = mem[32*16+31:32*16];
		5'd17: do_b = mem[32*17+31:32*17];
		5'd18: do_b = mem[32*18+31:32*18];
		5'd19: do_b = mem[32*19+31:32*19];
		5'd20: do_b = mem[32*20+31:32*20];
		5'd21: do_b = mem[32*21+31:32*21];
		5'd22: do_b = mem[32*22+31:32*22];
		5'd23: do_b = mem[32*23+31:32*23];
		5'd24: do_b = mem[32*24+31:32*24];
		5'd25: do_b = mem[32*25+31:32*25];
		5'd26: do_b = mem[32*26+31:32*26];
		5'd27: do_b = mem[32*27+31:32*27];
		5'd28: do_b = mem[32*28+31:32*28];
		5'd29: do_b = mem[32*29+31:32*29];
		5'd30: do_b = mem[32*30+31:32*30];
		5'd31: do_b = mem[32*31+31:32*31];
`endif
		default: do_b = 32'h0000_0000;
	endcase

endmodule