data/full_repos/permissive/149769583/mac1_tb.v
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1: b'%Error: data/full_repos/permissive/149769583/mac1_tb.v:8: syntax error, unexpected \'.\', expecting \')\'\n    mac1 DUT (.clk(clk), .acc(acc), .a(inputattr), .b(inputcoeff). rst_in(rst));\n                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/mac1_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #20 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/149769583/mac1_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #20 inputattr=16\'d30;             \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/mac1_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #20 inputattr=16\'d14;             \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/mac1_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #20 inputattr=16\'d47;             \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/mac1_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #20 inputattr=16\'d32;             \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/mac1_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #20 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/mac1_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #20 inputattr=16\'d30;             \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/149769583/mac1_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #20 inputattr=16\'d13;             \n        ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n'
module mac1_tb();

    reg [15:0] inputattr;
    reg [15:0] inputcoeff;
    reg clk,rst;
    wire [31:0] acc;

    mac1 DUT (.clk(clk), .acc(acc), .a(inputattr), .b(inputcoeff). rst_in(rst));

    always begin
        #20 clk = ~clk;
    end

    initial begin
        clk=1;
        inputattr=16'd49;
        inputcoeff=16'd10;
        #20 inputattr=16'd30;
        inputcoeff=16'd10;
        #20 inputattr=16'd14;
        inputcoeff=16'd0;
        #20 inputattr=16'd47;
        inputcoeff=16'd10;
        #20 inputattr=16'd32;
        inputcoeff=16'd10;
        rst = 1;
        #20 rst = 0;
        inputattr=16'd49;
        inputcoeff=16'd10;
        #20 inputattr=16'd30;
        inputcoeff=16'd10;
        #20 inputattr=16'd13;
        inputcoeff=16'd10;


        end
endmodule
module mac1_tb();


    reg [15:0] inputattr;
    reg [15:0] inputcoeff;
    reg clk,rst;
    wire [31:0] acc;

    mac1 DUT (.clk(clk), .acc(acc), .a(inputattr), .b(inputcoeff). rst_in(rst));

    always begin
        #20 clk = ~clk;
    end

    initial begin
        clk=1;
        inputattr=16'd49;
        inputcoeff=16'd10;
        #20 inputattr=16'd30;
        inputcoeff=16'd10;
        #20 inputattr=16'd14;
        inputcoeff=16'd0;
        #20 inputattr=16'd47;
        inputcoeff=16'd10;
        #20 inputattr=16'd32;
        inputcoeff=16'd10;
        rst = 1;
        #20 rst = 0;
        inputattr=16'd49;
        inputcoeff=16'd10;
        #20 inputattr=16'd30;
        inputcoeff=16'd10;
        #20 inputattr=16'd13;
        inputcoeff=16'd10;


        end
endmodule