data/full_repos/permissive/137738911/src/ConvKernel.v
1: b'%Error: data/full_repos/permissive/137738911/src/ConvKernel.v:43: Cannot find file containing module: \'Mult\'\n            Mult#(BITWIDTH) mult(data[(i + 1) * BITWIDTH - 1 : i * BITWIDTH], weight[(i + 1) * BITWIDTH - 1 : i * BITWIDTH], out[i]);\n            ^~~~\n        ... Looked in:\n             data/full_repos/permissive/137738911/src,data/full_repos/permissive/137738911/Mult\n             data/full_repos/permissive/137738911/src,data/full_repos/permissive/137738911/Mult.v\n             data/full_repos/permissive/137738911/src,data/full_repos/permissive/137738911/Mult.sv\n             Mult\n             Mult.v\n             Mult.sv\n             obj_dir/Mult\n             obj_dir/Mult.v\n             obj_dir/Mult.sv\n%Warning-WIDTH: data/full_repos/permissive/137738911/src/ConvKernel.v:53: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'bias\' generates 8 bits.\n                                                                        : ... In instance ConvKernel\n        result = result + bias;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module ConvKernel#(
    parameter integer BITWIDTH = 8,   
    
    parameter integer DATACHANNEL = 3, 
    
    parameter integer FILTERHEIGHT = 5,
    parameter integer FILTERWIDTH = 5
    )
    (
    input [BITWIDTH * DATACHANNEL * FILTERHEIGHT * FILTERWIDTH - 1 : 0]data,
    input [BITWIDTH * DATACHANNEL * FILTERHEIGHT * FILTERWIDTH - 1 : 0]weight,
    input [BITWIDTH - 1 : 0] bias,
    output reg signed [BITWIDTH * 2 -1 : 0]result
    );
    
    wire signed [BITWIDTH * 2 - 1 : 0]out[FILTERHEIGHT * FILTERWIDTH * DATACHANNEL - 1 : 0];
    
    generate
        genvar i;
        for(i = 0; i < FILTERHEIGHT * FILTERWIDTH * DATACHANNEL; i = i + 1) begin
            Mult#(BITWIDTH) mult(data[(i + 1) * BITWIDTH - 1 : i * BITWIDTH], weight[(i + 1) * BITWIDTH - 1 : i * BITWIDTH], out[i]);
        end
    endgenerate
    
    integer j;
    always @(*) begin
        result = 0;
        for(j = 0; j < FILTERHEIGHT * FILTERWIDTH * DATACHANNEL; j = j + 1) begin
            result = result + out[j];
        end
        result = result + bias;
    end
    
endmodule
module ConvKernel#(
    parameter integer BITWIDTH = 8,   
    
    parameter integer DATACHANNEL = 3, 
    
    parameter integer FILTERHEIGHT = 5,
    parameter integer FILTERWIDTH = 5
    )
    (
    input [BITWIDTH * DATACHANNEL * FILTERHEIGHT * FILTERWIDTH - 1 : 0]data,
    input [BITWIDTH * DATACHANNEL * FILTERHEIGHT * FILTERWIDTH - 1 : 0]weight,
    input [BITWIDTH - 1 : 0] bias,
    output reg signed [BITWIDTH * 2 -1 : 0]result
    );

    
    wire signed [BITWIDTH * 2 - 1 : 0]out[FILTERHEIGHT * FILTERWIDTH * DATACHANNEL - 1 : 0];
    
    generate
        genvar i;
        for(i = 0; i < FILTERHEIGHT * FILTERWIDTH * DATACHANNEL; i = i + 1) begin
            Mult#(BITWIDTH) mult(data[(i + 1) * BITWIDTH - 1 : i * BITWIDTH], weight[(i + 1) * BITWIDTH - 1 : i * BITWIDTH], out[i]);
        end
    endgenerate
    
    integer j;
    always @(*) begin
        result = 0;
        for(j = 0; j < FILTERHEIGHT * FILTERWIDTH * DATACHANNEL; j = j + 1) begin
            result = result + out[j];
        end
        result = result + bias;
    end
    
endmodule