data/full_repos/permissive/135111770/arbiter4_TB.v
 line:41: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = !clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10 req0 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 req0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10 req2 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10 req2 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10 req1 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 req1 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 req3 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 req3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/135111770/arbiter4_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #300 $finish;\n    ^\n%Error: data/full_repos/permissive/135111770/arbiter4_TB.v:6: Cannot find file containing module: \'arbiter4\'\n arbiter4 uut(\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135111770,data/full_repos/permissive/135111770/arbiter4\n             data/full_repos/permissive/135111770,data/full_repos/permissive/135111770/arbiter4.v\n             data/full_repos/permissive/135111770,data/full_repos/permissive/135111770/arbiter4.sv\n             arbiter4\n             arbiter4.v\n             arbiter4.sv\n             obj_dir/arbiter4\n             obj_dir/arbiter4.v\n             obj_dir/arbiter4.sv\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module arbiter4_TB;
	reg req0,req1,req2,req3;
	reg clk,rst;
	wire gnt0,gnt1,gnt2,gnt3;
	
	arbiter4 uut(
					.clk(clk),
					.rst(rst),
					.req0(req0),
					.req1(req1),
					.req2(req2),
					.req3(req3),
					.gnt0(gnt0),
					.gnt1(gnt1),
					.gnt2(gnt2),
					.gnt3(gnt3));
					
	always #5 clk = !clk;
		initial
			begin
				clk  = 0;
				req0 = 0;
				req1 = 0;
				req2 = 0;
				req3 = 0;
				rst  = 0;
			
				#100;
			
				#10 rst = 1;
				#10 rst = 0;
				#10 req0 = 1;
				#10 req0 = 0;
				#10 req2 = 1;
				#10 req2 = 0;
				#10 req1 = 1;
				#10 req1 = 0;
				#10 req3 = 1;
				#10 req3 = 0;
			
				#300 $finish;
			end
endmodule
module arbiter4_TB;

	reg req0,req1,req2,req3;
	reg clk,rst;
	wire gnt0,gnt1,gnt2,gnt3;
	
	arbiter4 uut(
					.clk(clk),
					.rst(rst),
					.req0(req0),
					.req1(req1),
					.req2(req2),
					.req3(req3),
					.gnt0(gnt0),
					.gnt1(gnt1),
					.gnt2(gnt2),
					.gnt3(gnt3));
					
	always #5 clk = !clk;
		initial
			begin
				clk  = 0;
				req0 = 0;
				req1 = 0;
				req2 = 0;
				req3 = 0;
				rst  = 0;
			
				#100;
			
				#10 rst = 1;
				#10 rst = 0;
				#10 req0 = 1;
				#10 req0 = 0;
				#10 req2 = 1;
				#10 req2 = 0;
				#10 req1 = 1;
				#10 req1 = 0;
				#10 req3 = 1;
				#10 req3 = 0;
			
				#300 $finish;
			end
endmodule