data/full_repos/permissive/162400762/Transmitter.v
1: b"%Error: data/full_repos/permissive/162400762/Transmitter.v:80: Cannot find file containing module: 'fifo_134_256'\nfifo_134_256 pkt_buffer (\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162400762,data/full_repos/permissive/162400762/fifo_134_256\n             data/full_repos/permissive/162400762,data/full_repos/permissive/162400762/fifo_134_256.v\n             data/full_repos/permissive/162400762,data/full_repos/permissive/162400762/fifo_134_256.sv\n             fifo_134_256\n             fifo_134_256.v\n             fifo_134_256.sv\n             obj_dir/fifo_134_256\n             obj_dir/fifo_134_256.v\n             obj_dir/fifo_134_256.sv\n%Error: Exiting due to 1 error(s)\n"
module Transmitter(
	clk,
	reset,

	pktin_data_wr,
	pktin_data,
	pktin_ready,
	pktout_data_wr,
	pktout_data,
	pktout_data_valid_wr,
	pktout_data_valid,
	pktout_ready,

	cin_data_wr,
	cin_data,
	cin_ready,
	cout_data_wr,
	cout_data,
	cout_ready
);

parameter 	LMID = 9,
			MID_IDS_UA = 132,
			w_pkt = 134;


input								clk;
input								reset;
input								pktin_data_wr;
input			[w_pkt-1:0]			pktin_data;
output	reg							pktin_ready;
output	reg		    				pktout_data_wr;	
output	reg	     [w_pkt-1:0]		pktout_data;
output	reg						    pktout_data_valid_wr;
output	reg						    pktout_data_valid;
input								pktout_ready;

input								cin_data_wr;
input			[w_pkt-1:0]			cin_data;
output	wire						cin_ready;
output	wire						cout_data_wr;
output	wire	[w_pkt-1:0]			cout_data;
input								cout_ready;





reg						rdreq_pkt;
wire	[w_pkt-1:0]		q_pkt;
wire					empty_pkt;
wire 	[7:0]			usedw_pkt;



reg 		[w_pkt-1:0]		metadata_temp;
reg 						packetIN_tag;

reg		[3:0]			state_proc;
parameter	IDLE_S						= 4'd0,
			READ_META_0_S			= 4'd1,
			READ_META_1_S			= 4'd2,
			WAIT_PKT_TAIL_S			= 4'd3;


fifo_134_256 pkt_buffer (
  .clk(clk),
  .srst(!reset),
  .din(pktin_data),
  .wr_en(pktin_data_wr),
  .rd_en(rdreq_pkt),
  .dout(q_pkt),
  .full(),
  .empty(empty_pkt),
  .data_count(usedw_pkt)
);

assign cout_data_wr = cin_data_wr;
assign cout_data = cin_data;
assign cin_ready = cout_ready;



always @(posedge clk or negedge reset) begin
	if (!reset) begin

		pktout_data_wr<= 1'b0;
		pktout_data <= {w_pkt{1'b0}};
		pktout_data_valid_wr <= 1'b0;
		pktout_data_valid <= 1'b0;
		pktin_ready <= 1'b1;

		rdreq_pkt <= 1'b0;
		metadata_temp <= {w_pkt{1'b0}};
		packetIN_tag <= 1'b0;

		state_proc <= IDLE_S;
	end
	else begin
		if(usedw_pkt < 8'd200) pktin_ready <= 1'b1;
		else pktin_ready <= 1'b0;

		case(state_proc)
			IDLE_S: begin

				pktout_data_wr <= 1'b0;
				pktout_data_valid_wr <= 1'b0;

				if((empty_pkt == 1'b0)&&(pktout_ready == 1'b1)) begin
					rdreq_pkt <= 1'b1;
					state_proc <= READ_META_0_S;
				end
				else begin
					rdreq_pkt <= 1'b0;
					state_proc <= IDLE_S;
				end
			end
			READ_META_0_S: begin
				metadata_temp <= q_pkt;
				packetIN_tag <= q_pkt[34];
				if(q_pkt[127] == 1'b1) begin


					state_proc <= READ_META_1_S;
				end
				else begin
					state_proc <= READ_META_1_S;
				end
			end
			READ_META_1_S: begin
				pktout_data_wr <= 1'b1;
				if(packetIN_tag == 1'b1) begin

					pktout_data <= {metadata_temp[133:127],1'b1,metadata_temp[125:96],LMID[7:0],MID_IDS_UA[7:0],
						metadata_temp[79:0]};
				end
				else begin
					pktout_data <= metadata_temp;
				end
				state_proc <= WAIT_PKT_TAIL_S;
			end
			WAIT_PKT_TAIL_S: begin
				pktout_data <= q_pkt;
				if(q_pkt[133:132] == 2'b10) begin
					state_proc <= IDLE_S;
					rdreq_pkt <= 1'b0;
					pktout_data_valid_wr <= 1'b1;
					pktout_data_valid <= 1'b1;
				end
				else begin
					state_proc <= WAIT_PKT_TAIL_S;
				end
			end
			default: begin
				state_proc <= IDLE_S;
			end
		endcase
	end
end



endmodule
module Transmitter(
	clk,
	reset,

	pktin_data_wr,
	pktin_data,
	pktin_ready,
	pktout_data_wr,
	pktout_data,
	pktout_data_valid_wr,
	pktout_data_valid,
	pktout_ready,

	cin_data_wr,
	cin_data,
	cin_ready,
	cout_data_wr,
	cout_data,
	cout_ready
);


parameter 	LMID = 9,
			MID_IDS_UA = 132,
			w_pkt = 134;


input								clk;
input								reset;
input								pktin_data_wr;
input			[w_pkt-1:0]			pktin_data;
output	reg							pktin_ready;
output	reg		    				pktout_data_wr;	
output	reg	     [w_pkt-1:0]		pktout_data;
output	reg						    pktout_data_valid_wr;
output	reg						    pktout_data_valid;
input								pktout_ready;

input								cin_data_wr;
input			[w_pkt-1:0]			cin_data;
output	wire						cin_ready;
output	wire						cout_data_wr;
output	wire	[w_pkt-1:0]			cout_data;
input								cout_ready;





reg						rdreq_pkt;
wire	[w_pkt-1:0]		q_pkt;
wire					empty_pkt;
wire 	[7:0]			usedw_pkt;



reg 		[w_pkt-1:0]		metadata_temp;
reg 						packetIN_tag;

reg		[3:0]			state_proc;
parameter	IDLE_S						= 4'd0,
			READ_META_0_S			= 4'd1,
			READ_META_1_S			= 4'd2,
			WAIT_PKT_TAIL_S			= 4'd3;


fifo_134_256 pkt_buffer (
  .clk(clk),
  .srst(!reset),
  .din(pktin_data),
  .wr_en(pktin_data_wr),
  .rd_en(rdreq_pkt),
  .dout(q_pkt),
  .full(),
  .empty(empty_pkt),
  .data_count(usedw_pkt)
);

assign cout_data_wr = cin_data_wr;
assign cout_data = cin_data;
assign cin_ready = cout_ready;



always @(posedge clk or negedge reset) begin
	if (!reset) begin

		pktout_data_wr<= 1'b0;
		pktout_data <= {w_pkt{1'b0}};
		pktout_data_valid_wr <= 1'b0;
		pktout_data_valid <= 1'b0;
		pktin_ready <= 1'b1;

		rdreq_pkt <= 1'b0;
		metadata_temp <= {w_pkt{1'b0}};
		packetIN_tag <= 1'b0;

		state_proc <= IDLE_S;
	end
	else begin
		if(usedw_pkt < 8'd200) pktin_ready <= 1'b1;
		else pktin_ready <= 1'b0;

		case(state_proc)
			IDLE_S: begin

				pktout_data_wr <= 1'b0;
				pktout_data_valid_wr <= 1'b0;

				if((empty_pkt == 1'b0)&&(pktout_ready == 1'b1)) begin
					rdreq_pkt <= 1'b1;
					state_proc <= READ_META_0_S;
				end
				else begin
					rdreq_pkt <= 1'b0;
					state_proc <= IDLE_S;
				end
			end
			READ_META_0_S: begin
				metadata_temp <= q_pkt;
				packetIN_tag <= q_pkt[34];
				if(q_pkt[127] == 1'b1) begin


					state_proc <= READ_META_1_S;
				end
				else begin
					state_proc <= READ_META_1_S;
				end
			end
			READ_META_1_S: begin
				pktout_data_wr <= 1'b1;
				if(packetIN_tag == 1'b1) begin

					pktout_data <= {metadata_temp[133:127],1'b1,metadata_temp[125:96],LMID[7:0],MID_IDS_UA[7:0],
						metadata_temp[79:0]};
				end
				else begin
					pktout_data <= metadata_temp;
				end
				state_proc <= WAIT_PKT_TAIL_S;
			end
			WAIT_PKT_TAIL_S: begin
				pktout_data <= q_pkt;
				if(q_pkt[133:132] == 2'b10) begin
					state_proc <= IDLE_S;
					rdreq_pkt <= 1'b0;
					pktout_data_valid_wr <= 1'b1;
					pktout_data_valid <= 1'b1;
				end
				else begin
					state_proc <= WAIT_PKT_TAIL_S;
				end
			end
			default: begin
				state_proc <= IDLE_S;
			end
		endcase
	end
end



endmodule