data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v
 line:225: before: ";"
1: b'%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:187: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("sim_top.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:188: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:215: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:217: syntax error, unexpected \'@\'\n    @(posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:219: syntax error, unexpected \'@\'\n    @(posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:222: syntax error, unexpected \'@\'\n    @(posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:226: syntax error, unexpected \'@\'\n    @(posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:231: syntax error, unexpected \'@\'\n    @(posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:236: syntax error, unexpected \'@\'\n    @(posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:241: syntax error, unexpected \'@\'\n    @(posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:248: syntax error, unexpected \'@\'\n    @(posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:278: syntax error, unexpected \'@\'\n    @ (posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:285: syntax error, unexpected \'@\'\n    @ (posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:292: syntax error, unexpected \'@\'\n    @ (posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:305: syntax error, unexpected \'@\'\n    @ (posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:311: syntax error, unexpected \'@\'\n    @ (posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:315: syntax error, unexpected \'@\'\n    @ (posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:321: syntax error, unexpected \'@\'\n    @ (posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:337: syntax error, unexpected \'@\'\n    @ (posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:343: syntax error, unexpected \'@\'\n    @ (posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:349: syntax error, unexpected \'@\'\n    @ (posedge clk_100mhz);\n    ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:376: syntax error, unexpected \'@\'\n        @(posedge clk_100mhz);\n        ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:402: syntax error, unexpected \'@\'\n        @(posedge clk_100mhz);\n        ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:444: syntax error, unexpected \'@\'\n        @(posedge clk_100mhz);\n        ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:549: syntax error, unexpected \'@\'\n        @(posedge clk_100mhz);\n        ^\n%Error: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:578: syntax error, unexpected \'@\'\n        @(posedge clk_100mhz);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/150947952/scratch/Level_4_Blinky/fpga/sim/top_tb/sim_top_tb.v:590: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk_100mhz <= ~clk_100mhz;\n    ^\n%Error: Exiting due to 25 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_top_tb;




reg clk_100mhz;
reg reset;


reg [7:0] bus_data_in;
reg bus_clk;
reg bus_rnw;


wire [7:0] bus_data;

assign bus_data = (bus_rnw) ? 8'bz : bus_data_in;




wire serial_out;
wire match_led;
wire [3:0] led;

wire bus_done;
wire bus_match;



integer file, r;
integer i,j,k;

reg finished;
reg done;
reg ret;
reg ack;


reg sf_done=0;
reg [7:0] sf_ack=0;
integer sf_i;
integer sf_j=0;
integer sf_k=0;

reg match;
reg[15:0] match_pos;
reg[`STR_LEN*8:0] match_str;

reg [7:0] rchar;



parameter NUM_LEDS = 4;
parameter FILE_SIZE_IN_BYTES = 163_185;



parameter CMD_SET_HASH_OP       = 8'h01;
parameter CMD_SEND_TEXT_OP      = 8'h02;
parameter CMD_READ_MATCH_OP     = 8'h03;
parameter CMD_TEST_OP           = 8'h04;
parameter CMD_STR_LEN           = 8'h05;

parameter BUFFER_SIZE           = 200;





reg [7:0] tv_mem [0:FILE_SIZE_IN_BYTES-1];



















reg [15:0] str_len = `STR_LEN*8;
reg [127:0] target_hash = 128'h0a4db18ed352b277c1292e9ef323d450;







reg [(BUFFER_SIZE*8)-1:0] text_str;




top_md5 #
(
    .NUM_LEDS(NUM_LEDS)
) top_md5_inst
(
    .clk(clk_100mhz),
    .reset(reset),


    .bus_clk(bus_clk),
    .bus_data(bus_data),
    .bus_rnw(bus_rnw),

    .bus_done(bus_done),
    .bus_match(bus_match),

    .match_led(match_led),
    .led(led)
);





initial begin

    $dumpfile("sim_top.vcd");
    $dumpvars;


    file = $fopen("alice30.txt", "rb");

    if (file == `NULL)
    begin
        $display("data_file handle was NULL");
        $finish;
    end
    r = $fread(tv_mem, file);
    $display("r: ",r);
    $display("feof: ",$feof(file));
    $fclose(file);


    clk_100mhz      = 0;
    reset           = 0;
    text_str        = 0;
    match_pos       = 0;
    match_str       = 0;
    match           = 0;
    bus_data_in     = 0;
    bus_rnw         = 0;
    rchar           = 0;


    #100;

    @(posedge clk_100mhz);
    reset   = 1;
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    reset   = 0;
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    sync_bus;
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    cmd_str_len(str_len,ret);
    $display("%t: ***cmd_str_len ret %x",$time,ret);
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);

    cmd_set_hash(ret);
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);


    send_file(match);
    @(posedge clk_100mhz);
    if (match == 1)
    begin
        cmd_read_match;
    end


    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    $finish;
end






task sync_bus;
begin

    bus_clk = 1;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    $display("%t: Send 1st sync workd ",$time);
    bus_data_in = 8'hB8;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    $display("%t: Send 2nd sync workd ",$time);
    bus_data_in = 8'h8B;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);

end
endtask


task send_char;
    input [7:0] char;
begin

    bus_rnw = 0;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    bus_clk = 0;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    bus_data_in = char;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    bus_clk = 1;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);

end
endtask


task read_char;
    output [7:0] char;
begin

    bus_rnw = 1;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    bus_clk = 0;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    bus_clk = 1;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    char = bus_data;
end
endtask



task cmd_test;
begin
    $display("\n%t: BEGIN cmd_test",$time);

    send_char(CMD_TEST_OP);


    for (i=0; i<10; i++)
    begin
        read_char(rchar);
        $display("%t: %d val=%d",$time,i,rchar);
    end


    while(!bus_done)
    begin
        @(posedge clk_100mhz);
    end

    $display("\n%t: END cmd_test",$time);
end
endtask


task cmd_set_hash;
    output [7:0] ack;
begin
    $display("\n%t: BEGIN cmd_set_hash",$time);


    send_char(CMD_SET_HASH_OP);


    for (i=15; i>=0; i=i-1)
    begin
        send_char(target_hash[8*i +: 8]);

    end


    while(!bus_done)
    begin
        @(posedge clk_100mhz);
    end


    $display("%t cmd_state=%x",$time,top_md5_inst.cmd_parser_inst.cmd_state);
    $display("%t target_hash=%x",$time,top_md5_inst.cmd_parser_inst.target_hash);
    $display("%t: END cmd_set_hash",$time);
end
endtask



task cmd_send_text;
    input [15:0] text_str_len;
    output [7:0] ack;
begin
    $display("\n%t: BEGIN cmd_send_text",$time);


    send_char(CMD_SEND_TEXT_OP);



    send_char(text_str_len[15:8]);
    $display("%t: MSB len=%x",$time,bus_data);

    send_char(text_str_len[7:0]);
    $display("%t: LSB len=%x",$time,bus_data);


    $display("");
    for (i=0; i <text_str_len; i++)
    begin
        send_char(text_str[8*i +: 8]);

        $write("%c",bus_data);
    end
    $display("\n");


    while(!bus_done)
    begin
        @(posedge clk_100mhz);
    end

    ack = bus_match;

    $display("%t: END cmd_send_text",$time);
end
endtask


task send_file;
    output match;
begin
    $display("\n%t: BEGIN send_file",$time);
    match = 0;

    sf_done=0; sf_i=0; sf_j=0; sf_k=0; sf_ack=0;
    while(!sf_done)
    begin
        if (sf_i+BUFFER_SIZE-1 > FILE_SIZE_IN_BYTES)
        begin

            sf_j= FILE_SIZE_IN_BYTES -sf_i;
            $display("%t: last transfer: %d:%d %d",$time,sf_i,FILE_SIZE_IN_BYTES-1,sf_j);


            for (sf_k=0; sf_k<sf_j; sf_k=sf_k+1)
            begin
                text_str[sf_k*8 +: 8] = tv_mem[sf_i];
                sf_i=sf_i+1;
            end

            cmd_send_text(sf_j,sf_ack);


            if (sf_ack == 1)
            begin
                $display("%t: MATCH FOUND!!",$time);
                match = 1;
            end
            else
            begin
                $display("%t: MATCH NOT found",$time);
            end
            sf_i=sf_j;
            sf_done = 1;
        end
        else
        begin

            sf_j= sf_i + BUFFER_SIZE;
            $display("%t: full transfer: %d:%d",$time,sf_i,sf_j-1);

            for (sf_k=0; sf_k<BUFFER_SIZE; sf_k=sf_k+1)
            begin
                text_str[sf_k*8 +: 8] = tv_mem[sf_i];
                sf_i=sf_i+1;
            end

            cmd_send_text(BUFFER_SIZE,sf_ack);
            

            if (sf_ack == 1)
            begin
                $display("%t: MATCH FOUND!!",$time);
                match = 1;
                sf_done = 1;
            end
            else
            begin
                $display("%t: MATCH NOT found",$time);
            end
        end
    end

    $display("%t: END send_file",$time);
end
endtask


task cmd_read_match;
begin
    $display("\n%t: BEGIN cmd_read_match",$time);


    send_char(CMD_READ_MATCH_OP);



    $display("%t: Read byte position",$time);
    read_char(match_pos[15:8]);

    read_char(match_pos[7:0]);
    match_pos = match_pos - (`STR_LEN-1);


    $display("%t: Read match string",$time);
    for (j=(`STR_LEN-1); j>=0; j=j-1)
    begin
        read_char(match_str[j*8 +: 8]);
    end


    while(!bus_done)
    begin
        @(posedge clk_100mhz);
    end

    $display("%t: match_pos: %d",$time,match_pos);
    $display("%t: match_str: '%s'",$time,match_str);

    $display("%t: END cmd_read_match",$time);
end
endtask


task cmd_str_len;
    input [15:0] length;
    output [7:0] ack;
begin
    $display("\n%t: BEGIN cmd_str_len",$time);
    $display("%t: set str char length=%d",$time,(length>>3));
    $display("%t: set str bit length=0x%x",$time,length);


    send_char(CMD_STR_LEN);


    send_char(length[15:8]);
    send_char(length[7:0]);


    while(!bus_done)
    begin
        @(posedge clk_100mhz);
    end


    $display("%t cmd_state=%x",$time,top_md5_inst.cmd_parser_inst.cmd_state);
    $display("%t target_hash=%x",$time,top_md5_inst.cmd_parser_inst.target_hash);
    $display("%t: END cmd_str_len",$time);
end
endtask


always begin
    #5 clk_100mhz <= ~clk_100mhz;
end

endmodule
module sim_top_tb;





reg clk_100mhz;
reg reset;


reg [7:0] bus_data_in;
reg bus_clk;
reg bus_rnw;


wire [7:0] bus_data;

assign bus_data = (bus_rnw) ? 8'bz : bus_data_in;




wire serial_out;
wire match_led;
wire [3:0] led;

wire bus_done;
wire bus_match;



integer file, r;
integer i,j,k;

reg finished;
reg done;
reg ret;
reg ack;


reg sf_done=0;
reg [7:0] sf_ack=0;
integer sf_i;
integer sf_j=0;
integer sf_k=0;

reg match;
reg[15:0] match_pos;
reg[`STR_LEN*8:0] match_str;

reg [7:0] rchar;



parameter NUM_LEDS = 4;
parameter FILE_SIZE_IN_BYTES = 163_185;



parameter CMD_SET_HASH_OP       = 8'h01;
parameter CMD_SEND_TEXT_OP      = 8'h02;
parameter CMD_READ_MATCH_OP     = 8'h03;
parameter CMD_TEST_OP           = 8'h04;
parameter CMD_STR_LEN           = 8'h05;

parameter BUFFER_SIZE           = 200;





reg [7:0] tv_mem [0:FILE_SIZE_IN_BYTES-1];



















reg [15:0] str_len = `STR_LEN*8;
reg [127:0] target_hash = 128'h0a4db18ed352b277c1292e9ef323d450;







reg [(BUFFER_SIZE*8)-1:0] text_str;




top_md5 #
(
    .NUM_LEDS(NUM_LEDS)
) top_md5_inst
(
    .clk(clk_100mhz),
    .reset(reset),


    .bus_clk(bus_clk),
    .bus_data(bus_data),
    .bus_rnw(bus_rnw),

    .bus_done(bus_done),
    .bus_match(bus_match),

    .match_led(match_led),
    .led(led)
);





initial begin

    $dumpfile("sim_top.vcd");
    $dumpvars;


    file = $fopen("alice30.txt", "rb");

    if (file == `NULL)
    begin
        $display("data_file handle was NULL");
        $finish;
    end
    r = $fread(tv_mem, file);
    $display("r: ",r);
    $display("feof: ",$feof(file));
    $fclose(file);


    clk_100mhz      = 0;
    reset           = 0;
    text_str        = 0;
    match_pos       = 0;
    match_str       = 0;
    match           = 0;
    bus_data_in     = 0;
    bus_rnw         = 0;
    rchar           = 0;


    #100;

    @(posedge clk_100mhz);
    reset   = 1;
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    reset   = 0;
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    sync_bus;
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    cmd_str_len(str_len,ret);
    $display("%t: ***cmd_str_len ret %x",$time,ret);
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);

    cmd_set_hash(ret);
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);


    send_file(match);
    @(posedge clk_100mhz);
    if (match == 1)
    begin
        cmd_read_match;
    end


    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    @(posedge clk_100mhz);
    $finish;
end






task sync_bus;
begin

    bus_clk = 1;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    $display("%t: Send 1st sync workd ",$time);
    bus_data_in = 8'hB8;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    $display("%t: Send 2nd sync workd ",$time);
    bus_data_in = 8'h8B;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);

end
endtask


task send_char;
    input [7:0] char;
begin

    bus_rnw = 0;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    bus_clk = 0;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    bus_data_in = char;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    bus_clk = 1;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);

end
endtask


task read_char;
    output [7:0] char;
begin

    bus_rnw = 1;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    bus_clk = 0;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    bus_clk = 1;
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);
    @ (posedge clk_100mhz);


    char = bus_data;
end
endtask



task cmd_test;
begin
    $display("\n%t: BEGIN cmd_test",$time);

    send_char(CMD_TEST_OP);


    for (i=0; i<10; i++)
    begin
        read_char(rchar);
        $display("%t: %d val=%d",$time,i,rchar);
    end


    while(!bus_done)
    begin
        @(posedge clk_100mhz);
    end

    $display("\n%t: END cmd_test",$time);
end
endtask


task cmd_set_hash;
    output [7:0] ack;
begin
    $display("\n%t: BEGIN cmd_set_hash",$time);


    send_char(CMD_SET_HASH_OP);


    for (i=15; i>=0; i=i-1)
    begin
        send_char(target_hash[8*i +: 8]);

    end


    while(!bus_done)
    begin
        @(posedge clk_100mhz);
    end


    $display("%t cmd_state=%x",$time,top_md5_inst.cmd_parser_inst.cmd_state);
    $display("%t target_hash=%x",$time,top_md5_inst.cmd_parser_inst.target_hash);
    $display("%t: END cmd_set_hash",$time);
end
endtask



task cmd_send_text;
    input [15:0] text_str_len;
    output [7:0] ack;
begin
    $display("\n%t: BEGIN cmd_send_text",$time);


    send_char(CMD_SEND_TEXT_OP);



    send_char(text_str_len[15:8]);
    $display("%t: MSB len=%x",$time,bus_data);

    send_char(text_str_len[7:0]);
    $display("%t: LSB len=%x",$time,bus_data);


    $display("");
    for (i=0; i <text_str_len; i++)
    begin
        send_char(text_str[8*i +: 8]);

        $write("%c",bus_data);
    end
    $display("\n");


    while(!bus_done)
    begin
        @(posedge clk_100mhz);
    end

    ack = bus_match;

    $display("%t: END cmd_send_text",$time);
end
endtask


task send_file;
    output match;
begin
    $display("\n%t: BEGIN send_file",$time);
    match = 0;

    sf_done=0; sf_i=0; sf_j=0; sf_k=0; sf_ack=0;
    while(!sf_done)
    begin
        if (sf_i+BUFFER_SIZE-1 > FILE_SIZE_IN_BYTES)
        begin

            sf_j= FILE_SIZE_IN_BYTES -sf_i;
            $display("%t: last transfer: %d:%d %d",$time,sf_i,FILE_SIZE_IN_BYTES-1,sf_j);


            for (sf_k=0; sf_k<sf_j; sf_k=sf_k+1)
            begin
                text_str[sf_k*8 +: 8] = tv_mem[sf_i];
                sf_i=sf_i+1;
            end

            cmd_send_text(sf_j,sf_ack);


            if (sf_ack == 1)
            begin
                $display("%t: MATCH FOUND!!",$time);
                match = 1;
            end
            else
            begin
                $display("%t: MATCH NOT found",$time);
            end
            sf_i=sf_j;
            sf_done = 1;
        end
        else
        begin

            sf_j= sf_i + BUFFER_SIZE;
            $display("%t: full transfer: %d:%d",$time,sf_i,sf_j-1);

            for (sf_k=0; sf_k<BUFFER_SIZE; sf_k=sf_k+1)
            begin
                text_str[sf_k*8 +: 8] = tv_mem[sf_i];
                sf_i=sf_i+1;
            end

            cmd_send_text(BUFFER_SIZE,sf_ack);
            

            if (sf_ack == 1)
            begin
                $display("%t: MATCH FOUND!!",$time);
                match = 1;
                sf_done = 1;
            end
            else
            begin
                $display("%t: MATCH NOT found",$time);
            end
        end
    end

    $display("%t: END send_file",$time);
end
endtask


task cmd_read_match;
begin
    $display("\n%t: BEGIN cmd_read_match",$time);


    send_char(CMD_READ_MATCH_OP);



    $display("%t: Read byte position",$time);
    read_char(match_pos[15:8]);

    read_char(match_pos[7:0]);
    match_pos = match_pos - (`STR_LEN-1);


    $display("%t: Read match string",$time);
    for (j=(`STR_LEN-1); j>=0; j=j-1)
    begin
        read_char(match_str[j*8 +: 8]);
    end


    while(!bus_done)
    begin
        @(posedge clk_100mhz);
    end

    $display("%t: match_pos: %d",$time,match_pos);
    $display("%t: match_str: '%s'",$time,match_str);

    $display("%t: END cmd_read_match",$time);
end
endtask


task cmd_str_len;
    input [15:0] length;
    output [7:0] ack;
begin
    $display("\n%t: BEGIN cmd_str_len",$time);
    $display("%t: set str char length=%d",$time,(length>>3));
    $display("%t: set str bit length=0x%x",$time,length);


    send_char(CMD_STR_LEN);


    send_char(length[15:8]);
    send_char(length[7:0]);


    while(!bus_done)
    begin
        @(posedge clk_100mhz);
    end


    $display("%t cmd_state=%x",$time,top_md5_inst.cmd_parser_inst.cmd_state);
    $display("%t target_hash=%x",$time,top_md5_inst.cmd_parser_inst.target_hash);
    $display("%t: END cmd_str_len",$time);
end
endtask


always begin
    #5 clk_100mhz <= ~clk_100mhz;
end

endmodule