data/full_repos/permissive/214278225/1_7SegmentDisplay/BuildingBlocks/fourDigitSevenSegment/SevenSegFourDig_tb.v
 line:26: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/214278225/1_7SegmentDisplay/BuildingBlocks/fourDigitSevenSegment/SevenSegFourDig_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/BuildingBlocks/fourDigitSevenSegment/SevenSegFourDig_tb.v:26: syntax error, unexpected \'@\'\n repeat(5) @(posedge clk);\n           ^\n%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/BuildingBlocks/fourDigitSevenSegment/SevenSegFourDig_tb.v:28: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/BuildingBlocks/fourDigitSevenSegment/SevenSegFourDig_tb.v:32: syntax error, unexpected \'@\'\n  repeat(5)@(designOut, anodeOut) begin\n           ^\n%Error: data/full_repos/permissive/214278225/1_7SegmentDisplay/BuildingBlocks/fourDigitSevenSegment/SevenSegFourDig_tb.v:44: syntax error, unexpected $display\n  $display("No ERRORs Found!");\n  ^~~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module SevenSegFourDig_tb;

reg clk, rst;
wire [7:0] designOut;
wire [3:0] anodeOut;
reg [15:0] dataIn [0:63];
reg [15:0] in;
reg [7:0] refOut;
reg [3:0] refIn;

integer errorFlag, ii;

SevenSegFourDig DUT(.clk(clk), .rst(rst), .in(in), .sevenSeg(designOut), .anode(anodeOut));

initial begin
	clk = 1;
	forever
		#5 clk = ~clk;
end

initial begin
	errorFlag = #1 0;
	rst       = #1 0;
	in    	 = #1 0;
	repeat(5) @(posedge clk);
	rst       = #1 1;
	@(posedge clk);
	rst       = #1 0;
	for(ii = 1; ii<=50; ii = ii +1) begin
		in = #1 $random;
		repeat(5)@(designOut, anodeOut) begin
			@(negedge clk);
			if(designOut !== refOut) begin
				$display("Output ERROR at time %d, expected %b, received %b", $time, refOut, designOut);
				errorFlag = errorFlag +1;
			end
			else
				$display("Output CORRECT at time %d, expected %b, received %b", $time, refOut, designOut);
		end
	end

	if(errorFlag == 0)
		$display("No ERRORs Found!");
	else
		$display("%d ERRORs Found!", errorFlag);
	$finish;
end


always@(*) begin
	case(anodeOut)
		4'b0111:refIn = in[15:12];
		4'b1011:refIn = in[11:8];
		4'b1101:refIn = in[7:4];
		default:refIn = in[3:0];
	endcase

	case(refIn[3:0])
		0: refOut = 8'b00000010;
		1: refOut = 8'b10011110;
		2: refOut = 8'b00100100;
		3: refOut = 8'b00001100;
		4: refOut = 8'b10011000;
		5: refOut = 8'b01001000;
		6: refOut = 8'b01000000;
		7: refOut = 8'b00011110;
		8: refOut = 8'b00000000;
		9: refOut = 8'b00001000;
		10: refOut = 8'b00010000;
		11: refOut = 8'b11000000;
		12: refOut = 8'b01100010;
		13: refOut = 8'b10000100;
		14: refOut = 8'b01100000;
		15: refOut = 8'b01110000;
	endcase
end


endmodule
module SevenSegFourDig_tb;


reg clk, rst;
wire [7:0] designOut;
wire [3:0] anodeOut;
reg [15:0] dataIn [0:63];
reg [15:0] in;
reg [7:0] refOut;
reg [3:0] refIn;

integer errorFlag, ii;

SevenSegFourDig DUT(.clk(clk), .rst(rst), .in(in), .sevenSeg(designOut), .anode(anodeOut));

initial begin
	clk = 1;
	forever
		#5 clk = ~clk;
end

initial begin
	errorFlag = #1 0;
	rst       = #1 0;
	in    	 = #1 0;
	repeat(5) @(posedge clk);
	rst       = #1 1;
	@(posedge clk);
	rst       = #1 0;
	for(ii = 1; ii<=50; ii = ii +1) begin
		in = #1 $random;
		repeat(5)@(designOut, anodeOut) begin
			@(negedge clk);
			if(designOut !== refOut) begin
				$display("Output ERROR at time %d, expected %b, received %b", $time, refOut, designOut);
				errorFlag = errorFlag +1;
			end
			else
				$display("Output CORRECT at time %d, expected %b, received %b", $time, refOut, designOut);
		end
	end

	if(errorFlag == 0)
		$display("No ERRORs Found!");
	else
		$display("%d ERRORs Found!", errorFlag);
	$finish;
end


always@(*) begin
	case(anodeOut)
		4'b0111:refIn = in[15:12];
		4'b1011:refIn = in[11:8];
		4'b1101:refIn = in[7:4];
		default:refIn = in[3:0];
	endcase

	case(refIn[3:0])
		0: refOut = 8'b00000010;
		1: refOut = 8'b10011110;
		2: refOut = 8'b00100100;
		3: refOut = 8'b00001100;
		4: refOut = 8'b10011000;
		5: refOut = 8'b01001000;
		6: refOut = 8'b01000000;
		7: refOut = 8'b00011110;
		8: refOut = 8'b00000000;
		9: refOut = 8'b00001000;
		10: refOut = 8'b00010000;
		11: refOut = 8'b11000000;
		12: refOut = 8'b01100010;
		13: refOut = 8'b10000100;
		14: refOut = 8'b01100000;
		15: refOut = 8'b01110000;
	endcase
end


endmodule