data/full_repos/permissive/146618947/mux_21/mycells.v
 line:3: before: ":"
1: b'%Warning-STMTDLY: data/full_repos/permissive/146618947/mux_21/mycells.v:16: Unsupported: Ignoring delay on this delayed statement.\n     #(1.4:3:4.6) Q <= D;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/146618947/mux_21/mycells.v:6: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                          : ... Top module \'NOT\'\nmodule NOT(input A, output Y);\n       ^~~\n                                                                          : ... Top module \'NAND\'\nmodule NAND(input A, input B, output Y);\n       ^~~~\n                                                                          : ... Top module \'NOR\'\nmodule NOR(input A, input B, output Y);\n       ^~~\n                                                                          : ... Top module \'DFF\'\nmodule DFF(input C, input D, output reg Q);\n       ^~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module NOT(input A, output Y);
   assign #(1.5:5.05:7.1) Y = ~A;
endmodule
module NOT(input A, output Y);

   assign #(1.5:5.05:7.1) Y = ~A;
endmodule