data/full_repos/permissive/208113388/afu/afp/afp3_eng_fsm_cpy_st.v
1: b"%Error: data/full_repos/permissive/208113388/afu/afp/afp3_eng_fsm_cpy_st.v:223: Cannot find file containing module: 'mcp3_ohc05'\n  mcp3_ohc05  cpy_rtry_st_seq_err (\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208113388/afu/afp,data/full_repos/permissive/208113388/mcp3_ohc05\n             data/full_repos/permissive/208113388/afu/afp,data/full_repos/permissive/208113388/mcp3_ohc05.v\n             data/full_repos/permissive/208113388/afu/afp,data/full_repos/permissive/208113388/mcp3_ohc05.sv\n             mcp3_ohc05\n             mcp3_ohc05.v\n             mcp3_ohc05.sv\n             obj_dir/mcp3_ohc05\n             obj_dir/mcp3_ohc05.v\n             obj_dir/mcp3_ohc05.sv\n%Error: data/full_repos/permissive/208113388/afu/afp/afp3_eng_fsm_cpy_st.v:325: Cannot find file containing module: 'mcp3_ram512x025'\n  mcp3_ram512x025  rtry_queue\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/208113388/afu/afp/afp3_eng_fsm_cpy_st.v:424: Cannot find file containing module: 'mcp3_decoder9x512'\n  mcp3_decoder9x512  decode_afutag\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/208113388/afu/afp/afp3_eng_fsm_cpy_st.v:439: Cannot find file containing module: 'mcp3_decoder9x512'\n  mcp3_decoder9x512  rtry_decode_afutag\n  ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module afp3_eng_fsm_cpy_st
  (

    input                 clock                                           
  , input                 reset




  , input           [1:0] mmio_eng_st_size
  , input                 cpy_st_type_sel
  , input                 rtry_backoff_timer_disable_q













  , input           [8:0] cpy_rtry_xx_afutag_q
  , input           [1:0] cpy_rtry_xx_dl_q



  , input          [11:0] eng_actag
  , input           [7:0] cfg_afu_bdf_bus 
  , input           [4:0] cfg_afu_bdf_device
  , input           [2:0] cfg_afu_bdf_function



  , input          [63:6] cpy_st_ea_q

  , input                 rspi_cpy_st_resp_val_q
  , input          [1:0]  rspi_resp_dl_q
  , input          [8:0]  rspi_resp_afutag_q


  , input                 arb_eng_st_gnt
  , input           [8:0] arb_eng_st_tag
  , output        [511:0] eng_arb_set_st_tag_avail
  , output                eng_arb_st_fastpath_valid
  , output          [8:0] eng_arb_st_fastpath_tag












  , input                 start_cpy_rtry_st_seq
  , input                 rtry_decode_is_immediate
  , input                 rtry_decode_is_backoff
  , input                 rtry_decode_is_abort
  , input           [8:0] rtry_queue_afutag_q     
  , input           [1:0] rtry_queue_dl_q
  , input                 cpy_rtry_st_backoff_done
  , input                 cpy_rtry_st_backoff_done_q

  , output                eng_arb_rtry_st_req
  , output                cpy_rtry_st_req
  , input                 arb_eng_rtry_st_gnt


  , output                cpy_rtry_st_seq_error

  , output          [4:0] cpy_rtry_st_state
  , output                cpy_rtry_st_idle_st
  , output                cpy_rtry_st_wt4bckoff_st
  , output                cpy_rtry_st_req_st
  , output                cpy_rtry_st_wt4gnt_st
  , output                cpy_rtry_st_abort_st


  , output reg            cpy_st_valid
  , output reg      [7:0] cpy_st_opcode
  , output reg     [11:0] cpy_st_actag
  , output reg      [3:0] cpy_st_stream_id 
  , output reg     [67:0] cpy_st_ea_or_obj
  , output reg     [15:0] cpy_st_afutag
  , output reg      [1:0] cpy_st_dl
  , output reg      [2:0] cpy_st_pl
  , output reg            cpy_st_os
  , output reg     [63:0] cpy_st_be
  , output reg      [3:0] cpy_st_flag
  , output reg            cpy_st_endian
  , output reg     [15:0] cpy_st_bdf

  , output reg      [5:0] cpy_st_pg_size





  , output                cpy_st_size_256_q

  );






  wire     [11:0] cpy_rtry_st_seq_sel;
  reg       [5:0] cpy_rtry_st_seq;
  wire            cpy_rtry_st_seq_err_int;

  wire            cpy_rtry_st_idle_state;
  wire            cpy_rtry_st_wt4bckoff_state;
  wire            cpy_rtry_st_req_state;
  wire            cpy_rtry_st_wt4gnt_state;
  wire            cpy_rtry_st_abort_state;

  wire            cpy_rtry_st_req_int;


  wire            rtry_ea_wren;
  wire      [8:0] rtry_ea_wraddr;
  wire     [31:7] rtry_ea_wrdata;

  wire            rtry_ea_rden;
  wire      [8:0] rtry_ea_rdaddr;
  wire     [31:7] rtry_ea_rddata;

  wire            cpy_rtry_st_ea_bit7;
  wire     [63:6] cpy_rtry_st_ea;


  reg       [7:0] cpy_st_opcode_int;


  wire      [8:0] afutag_masked;
  wire    [511:0] afutag_decoded;
  wire    [511:0] afutag_decoded_valid;

  wire            rtry_abort_valid;
  wire      [8:0] rtry_afutag_masked;
  wire    [511:0] rtry_afutag_decoded;
  wire    [511:0] rtry_afutag_decoded_abort;


  wire            curr_resp_length;
  wire            fastpath_valid;






  wire      [4:0] cpy_rtry_st_seq_d;
`ifdef MARK_DEBUG_ACTIVE (* mark_debug = "TRUE" *) `endif
  reg       [4:0] cpy_rtry_st_seq_q;
         
  wire            cpy_st_resp_length_en;
  reg     [255:0] cpy_st_resp_length_d;
  reg     [255:0] cpy_st_resp_length_q;

  reg       [1:0] mmio_eng_st_size_q;

  wire            resp_valid_dly1_d;
  reg             resp_valid_dly1_q;

  wire            resp_valid_dly2_d;
  reg             resp_valid_dly2_q;






  localparam    [7:0] AFU_TLX_CMD_ENCODE_DMA_W                 = 8'b00100000;
  localparam    [7:0] AFU_TLX_CMD_ENCODE_DMA_W_N               = 8'b00100100;

















  mcp3_ohc05  cpy_rtry_st_seq_err (
    .one_hot_vector   ( cpy_rtry_st_seq_q[4:0] ),
    .one_hot_error    ( cpy_rtry_st_seq_err_int )
  );


  assign  cpy_rtry_st_idle_state      =  cpy_rtry_st_seq_q[0];
  assign  cpy_rtry_st_wt4bckoff_state =  cpy_rtry_st_seq_q[1];
  assign  cpy_rtry_st_req_state       =  cpy_rtry_st_seq_q[2];
  assign  cpy_rtry_st_wt4gnt_state    =  cpy_rtry_st_seq_q[3];
  assign  cpy_rtry_st_abort_state     =  cpy_rtry_st_seq_q[4];


  assign  cpy_rtry_st_seq_sel[11:0] = { start_cpy_rtry_st_seq, ( rtry_decode_is_immediate || rtry_backoff_timer_disable_q ), rtry_decode_is_backoff, rtry_decode_is_abort,
                                        cpy_rtry_st_backoff_done_q, cpy_rtry_st_backoff_done, arb_eng_rtry_st_gnt, cpy_rtry_st_seq_q[4:0] };

  always @*
    begin
      casez ( cpy_rtry_st_seq_sel[11:0] )














           12'b0??????_00001 :  cpy_rtry_st_seq[5:0] =  6'b0_00001 ;
           12'b11?????_00001 :  cpy_rtry_st_seq[5:0] =  6'b1_00100 ;
           12'b101?00?_00001 :  cpy_rtry_st_seq[5:0] =  6'b0_00010 ;
           12'b101?1??_00001 :  cpy_rtry_st_seq[5:0] =  6'b1_00100 ;
           12'b101?01?_00001 :  cpy_rtry_st_seq[5:0] =  6'b1_00100 ;
           12'b1001???_00001 :  cpy_rtry_st_seq[5:0] =  6'b0_10000 ;

           12'b?????0?_00010 :  cpy_rtry_st_seq[5:0] =  6'b0_00010 ;
           12'b?????1?_00010 :  cpy_rtry_st_seq[5:0] =  6'b1_00100 ;

           12'b???????_00100 :  cpy_rtry_st_seq[5:0] =  6'b0_01000 ;

           12'b??????0_01000 :  cpy_rtry_st_seq[5:0] =  6'b0_01000 ;
           12'b??????1_01000 :  cpy_rtry_st_seq[5:0] =  6'b0_00001 ;

           12'b???????_10000 :  cpy_rtry_st_seq[5:0] =  6'b0_00001 ;

            default          :  cpy_rtry_st_seq[5:0] =  6'b0_00001 ;

      endcase
    end


  assign  eng_arb_rtry_st_req  =  cpy_rtry_st_seq[5];
  assign  cpy_rtry_st_req      =  cpy_rtry_st_seq[5];
  assign  cpy_rtry_st_req_int  =  cpy_rtry_st_seq[5];


  assign  cpy_rtry_st_state[4:0]   =  cpy_rtry_st_seq_q[4:0];
  assign  cpy_rtry_st_idle_st      =  cpy_rtry_st_idle_state;
  assign  cpy_rtry_st_wt4bckoff_st =  cpy_rtry_st_wt4bckoff_state;
  assign  cpy_rtry_st_req_st       =  cpy_rtry_st_req_state;
  assign  cpy_rtry_st_wt4gnt_st    =  cpy_rtry_st_wt4gnt_state;
  assign  cpy_rtry_st_abort_st     =  cpy_rtry_st_abort_state;


  assign  cpy_rtry_st_seq_error    =  cpy_rtry_st_seq_err_int;


  assign  cpy_rtry_st_seq_d[4:0] = ( reset || cpy_rtry_st_seq_err_int ) ? 5'b1 : cpy_rtry_st_seq[4:0];













  assign  rtry_ea_wren         =  arb_eng_st_gnt;
  assign  rtry_ea_wraddr[8:0]  =  arb_eng_st_tag[8:0];
  assign  rtry_ea_wrdata[31:7] =  cpy_st_ea_q[31:7];

  assign  rtry_ea_rden         =  cpy_rtry_st_req_int;







  assign  rtry_ea_rdaddr[8:0]  =  {cpy_rtry_xx_afutag_q[8:1], (cpy_rtry_xx_afutag_q[0] & ~(mmio_eng_st_size_q[1:0] == 2'b11)) };

  

  mcp3_ram512x025  rtry_queue
    ( .clk   ( clock ),

      .wren  ( rtry_ea_wren ),
      .wrad  ( rtry_ea_wraddr[8:0] ),
      .data  ( rtry_ea_wrdata[31:7] ),

      .rden  ( rtry_ea_rden ),
      .rdad  ( rtry_ea_rdaddr[8:0] ),
      .q     ( rtry_ea_rddata[31:7] )
    );





  assign  cpy_rtry_st_ea_bit7   = rtry_ea_rddata[7] || ((mmio_eng_st_size_q[1:0] == 2'b11) && cpy_rtry_xx_afutag_q[0]);
  assign  cpy_rtry_st_ea[63:6]  = { cpy_st_ea_q[63:32],  rtry_ea_rddata[31:8], cpy_rtry_st_ea_bit7, 1'b0 };






  always @*
    begin
      if ( cpy_st_type_sel == 1'b0 )
        cpy_st_opcode_int[7:0] =  AFU_TLX_CMD_ENCODE_DMA_W[7:0];
      else
        cpy_st_opcode_int[7:0] =  AFU_TLX_CMD_ENCODE_DMA_W_N[7:0];
    end

   

  always @*
    begin
      if ( arb_eng_st_gnt || arb_eng_rtry_st_gnt )
        begin
          cpy_st_valid           =   (( arb_eng_st_gnt ) || ( arb_eng_rtry_st_gnt ));
          cpy_st_opcode[7:0]     =     cpy_st_opcode_int[7:0];
          cpy_st_actag[11:0]     =     eng_actag[11:0];
          cpy_st_stream_id[3:0]  =     4'b0;
          if ( arb_eng_rtry_st_gnt )
            begin
              cpy_st_ea_or_obj[67:0] = { 4'b0, cpy_rtry_st_ea[63:6], 6'b0 };
              cpy_st_afutag[15:0]    = { cpy_rtry_xx_dl_q[1:0], 4'b1000, 1'b1, cpy_rtry_xx_afutag_q[8:0] };
              cpy_st_dl[1:0]         =   cpy_rtry_xx_dl_q[1:0];
            end 
          else
            begin
              cpy_st_ea_or_obj[67:0] = { 4'b0, cpy_st_ea_q[63:6], 6'b0 };
              cpy_st_afutag[15:0]    = { mmio_eng_st_size_q[1:0], 5'b10000, arb_eng_st_tag[8:0] };
              cpy_st_dl[1:0]         =   mmio_eng_st_size_q[1:0];
            end
          cpy_st_pl[2:0]         =     3'b000;
          cpy_st_os              =     1'b0;
          cpy_st_be[63:0]        =    64'b0;
          cpy_st_flag[3:0]       =     4'b0;
          cpy_st_endian          =     1'b0;
          cpy_st_bdf[15:0]       =  { cfg_afu_bdf_bus[7:0], cfg_afu_bdf_device[4:0], cfg_afu_bdf_function[2:0] };

          cpy_st_pg_size[5:0]    =     6'b0;
        end
      else
        begin
          cpy_st_valid           =    1'b0;
          cpy_st_opcode[7:0]     =    8'b0;
          cpy_st_actag[11:0]     =   12'b0;
          cpy_st_stream_id[3:0]  =    4'b0;
          cpy_st_ea_or_obj[67:0] =   68'b0;
          cpy_st_afutag[15:0]    =   16'b0;
          cpy_st_dl[1:0]         =    2'b0;
          cpy_st_pl[2:0]         =    3'b0;
          cpy_st_os              =    1'b0;
          cpy_st_be[63:0]        =   64'b0;
          cpy_st_flag[3:0]       =    4'b0;
          cpy_st_endian          =    1'b0;
          cpy_st_bdf[15:0]       =   16'b0;

          cpy_st_pg_size[5:0]    =    6'b0;
        end

    end



  assign  cpy_st_size_256_q    =  (mmio_eng_st_size_q == 2'b11);







  assign  cpy_st_resp_length_en =  reset || ((rspi_cpy_st_resp_val_q || rtry_abort_valid) && (mmio_eng_st_size_q == 2'b11));

  assign  afutag_masked[8:1] = rspi_resp_afutag_q[8:1];
  assign  afutag_masked[0]   = rspi_resp_afutag_q[0] && (mmio_eng_st_size_q != 2'b11);

  mcp3_decoder9x512  decode_afutag
    (
      .din        ( afutag_masked[8:0] ),
      .dout       ( afutag_decoded[511:0] )
    );

  assign  afutag_decoded_valid[511:0]  =  rspi_cpy_st_resp_val_q ?  afutag_decoded[511:0]
                                                                 :  512'b0;


  assign  rtry_abort_valid  = start_cpy_rtry_st_seq & rtry_decode_is_abort;

  assign  rtry_afutag_masked[8:1] = rtry_queue_afutag_q[8:1];
  assign  rtry_afutag_masked[0]   = rtry_queue_afutag_q[0] && (mmio_eng_st_size_q != 2'b11);

  mcp3_decoder9x512  rtry_decode_afutag
    (
      .din        ( rtry_afutag_masked[8:0] ),
      .dout       ( rtry_afutag_decoded[511:0] )
    );

  assign  rtry_afutag_decoded_abort[511:0]  =  rtry_abort_valid  ?  rtry_afutag_decoded[511:0]
                                                                 :  512'b0;

  genvar i;
  generate
    for (i = 0; i < 256; i = i+1)
      begin: cpy_st_resp_length_gen
        always @*
          begin
            if ( reset )
              cpy_st_resp_length_d[i] = 1'b0;
            else
              begin
                if (( afutag_decoded_valid[i*2] == 1'b1 ) && (rtry_afutag_decoded_abort[i*2]))
                  begin
                      cpy_st_resp_length_d[i] = 1'b0;
                  end
                else if ( afutag_decoded_valid[i*2] == 1'b1 )
                  begin
                    if (rspi_resp_dl_q[1:0] == 2'b11)
                      cpy_st_resp_length_d[i] = 1'b0;
                    else
	              cpy_st_resp_length_d[i] = ~cpy_st_resp_length_q[i];
                  end
                else if ( rtry_afutag_decoded_abort[i*2] == 1'b1 )
                  begin
                    if (rtry_queue_dl_q[1:0] == 2'b11)
                      cpy_st_resp_length_d[i] = 1'b0;
                    else
	              cpy_st_resp_length_d[i] = ~cpy_st_resp_length_q[i];
                  end
                else
                  cpy_st_resp_length_d[i] = cpy_st_resp_length_q[i];
              end
          end

        assign eng_arb_set_st_tag_avail[i*2]   = (afutag_decoded_valid[i*2] & ((~cpy_st_resp_length_d[i]) | (mmio_eng_st_size_q != 2'b11))) |
                                            (rtry_afutag_decoded_abort[i*2] & ((~cpy_st_resp_length_d[i]) | (mmio_eng_st_size_q != 2'b11)));
        assign eng_arb_set_st_tag_avail[i*2+1] = afutag_decoded_valid[i*2+1] | rtry_afutag_decoded_abort[i*2+1];
      end
  endgenerate










  assign resp_valid_dly1_d  =  rspi_cpy_st_resp_val_q  |  rtry_abort_valid;
  assign resp_valid_dly2_d  =  resp_valid_dly1_q;

  assign curr_resp_length = cpy_st_resp_length_q[ afutag_masked[8:1] ];

  assign fastpath_valid  = rspi_cpy_st_resp_val_q &
                           ~resp_valid_dly1_q & ~resp_valid_dly2_q &
                           ~rtry_abort_valid &
                           ((mmio_eng_st_size_q != 2'b11) |
                            (rspi_resp_dl_q[1:0] == 2'b11) |
                            (curr_resp_length == 1'b1));

  assign eng_arb_st_fastpath_valid     =  fastpath_valid;
  assign eng_arb_st_fastpath_tag[8:0]  =  afutag_masked[8:0];





  always @ ( posedge clock )
    begin


      cpy_rtry_st_seq_q[4:0]                       <= cpy_rtry_st_seq_d[4:0];


      if ( cpy_st_resp_length_en )
        cpy_st_resp_length_q[255:0]                <= cpy_st_resp_length_d[255:0];


      mmio_eng_st_size_q[1:0]                      <= mmio_eng_st_size[1:0];


      resp_valid_dly1_q                            <= resp_valid_dly1_d;
      resp_valid_dly2_q                            <= resp_valid_dly2_d;

    end

endmodule
module afp3_eng_fsm_cpy_st
  (

    input                 clock                                           
  , input                 reset




  , input           [1:0] mmio_eng_st_size
  , input                 cpy_st_type_sel
  , input                 rtry_backoff_timer_disable_q













  , input           [8:0] cpy_rtry_xx_afutag_q
  , input           [1:0] cpy_rtry_xx_dl_q



  , input          [11:0] eng_actag
  , input           [7:0] cfg_afu_bdf_bus 
  , input           [4:0] cfg_afu_bdf_device
  , input           [2:0] cfg_afu_bdf_function



  , input          [63:6] cpy_st_ea_q

  , input                 rspi_cpy_st_resp_val_q
  , input          [1:0]  rspi_resp_dl_q
  , input          [8:0]  rspi_resp_afutag_q


  , input                 arb_eng_st_gnt
  , input           [8:0] arb_eng_st_tag
  , output        [511:0] eng_arb_set_st_tag_avail
  , output                eng_arb_st_fastpath_valid
  , output          [8:0] eng_arb_st_fastpath_tag












  , input                 start_cpy_rtry_st_seq
  , input                 rtry_decode_is_immediate
  , input                 rtry_decode_is_backoff
  , input                 rtry_decode_is_abort
  , input           [8:0] rtry_queue_afutag_q     
  , input           [1:0] rtry_queue_dl_q
  , input                 cpy_rtry_st_backoff_done
  , input                 cpy_rtry_st_backoff_done_q

  , output                eng_arb_rtry_st_req
  , output                cpy_rtry_st_req
  , input                 arb_eng_rtry_st_gnt


  , output                cpy_rtry_st_seq_error

  , output          [4:0] cpy_rtry_st_state
  , output                cpy_rtry_st_idle_st
  , output                cpy_rtry_st_wt4bckoff_st
  , output                cpy_rtry_st_req_st
  , output                cpy_rtry_st_wt4gnt_st
  , output                cpy_rtry_st_abort_st


  , output reg            cpy_st_valid
  , output reg      [7:0] cpy_st_opcode
  , output reg     [11:0] cpy_st_actag
  , output reg      [3:0] cpy_st_stream_id 
  , output reg     [67:0] cpy_st_ea_or_obj
  , output reg     [15:0] cpy_st_afutag
  , output reg      [1:0] cpy_st_dl
  , output reg      [2:0] cpy_st_pl
  , output reg            cpy_st_os
  , output reg     [63:0] cpy_st_be
  , output reg      [3:0] cpy_st_flag
  , output reg            cpy_st_endian
  , output reg     [15:0] cpy_st_bdf

  , output reg      [5:0] cpy_st_pg_size





  , output                cpy_st_size_256_q

  );







  wire     [11:0] cpy_rtry_st_seq_sel;
  reg       [5:0] cpy_rtry_st_seq;
  wire            cpy_rtry_st_seq_err_int;

  wire            cpy_rtry_st_idle_state;
  wire            cpy_rtry_st_wt4bckoff_state;
  wire            cpy_rtry_st_req_state;
  wire            cpy_rtry_st_wt4gnt_state;
  wire            cpy_rtry_st_abort_state;

  wire            cpy_rtry_st_req_int;


  wire            rtry_ea_wren;
  wire      [8:0] rtry_ea_wraddr;
  wire     [31:7] rtry_ea_wrdata;

  wire            rtry_ea_rden;
  wire      [8:0] rtry_ea_rdaddr;
  wire     [31:7] rtry_ea_rddata;

  wire            cpy_rtry_st_ea_bit7;
  wire     [63:6] cpy_rtry_st_ea;


  reg       [7:0] cpy_st_opcode_int;


  wire      [8:0] afutag_masked;
  wire    [511:0] afutag_decoded;
  wire    [511:0] afutag_decoded_valid;

  wire            rtry_abort_valid;
  wire      [8:0] rtry_afutag_masked;
  wire    [511:0] rtry_afutag_decoded;
  wire    [511:0] rtry_afutag_decoded_abort;


  wire            curr_resp_length;
  wire            fastpath_valid;






  wire      [4:0] cpy_rtry_st_seq_d;
`ifdef MARK_DEBUG_ACTIVE (* mark_debug = "TRUE" *) `endif
  reg       [4:0] cpy_rtry_st_seq_q;
         
  wire            cpy_st_resp_length_en;
  reg     [255:0] cpy_st_resp_length_d;
  reg     [255:0] cpy_st_resp_length_q;

  reg       [1:0] mmio_eng_st_size_q;

  wire            resp_valid_dly1_d;
  reg             resp_valid_dly1_q;

  wire            resp_valid_dly2_d;
  reg             resp_valid_dly2_q;






  localparam    [7:0] AFU_TLX_CMD_ENCODE_DMA_W                 = 8'b00100000;
  localparam    [7:0] AFU_TLX_CMD_ENCODE_DMA_W_N               = 8'b00100100;

















  mcp3_ohc05  cpy_rtry_st_seq_err (
    .one_hot_vector   ( cpy_rtry_st_seq_q[4:0] ),
    .one_hot_error    ( cpy_rtry_st_seq_err_int )
  );


  assign  cpy_rtry_st_idle_state      =  cpy_rtry_st_seq_q[0];
  assign  cpy_rtry_st_wt4bckoff_state =  cpy_rtry_st_seq_q[1];
  assign  cpy_rtry_st_req_state       =  cpy_rtry_st_seq_q[2];
  assign  cpy_rtry_st_wt4gnt_state    =  cpy_rtry_st_seq_q[3];
  assign  cpy_rtry_st_abort_state     =  cpy_rtry_st_seq_q[4];


  assign  cpy_rtry_st_seq_sel[11:0] = { start_cpy_rtry_st_seq, ( rtry_decode_is_immediate || rtry_backoff_timer_disable_q ), rtry_decode_is_backoff, rtry_decode_is_abort,
                                        cpy_rtry_st_backoff_done_q, cpy_rtry_st_backoff_done, arb_eng_rtry_st_gnt, cpy_rtry_st_seq_q[4:0] };

  always @*
    begin
      casez ( cpy_rtry_st_seq_sel[11:0] )














           12'b0??????_00001 :  cpy_rtry_st_seq[5:0] =  6'b0_00001 ;
           12'b11?????_00001 :  cpy_rtry_st_seq[5:0] =  6'b1_00100 ;
           12'b101?00?_00001 :  cpy_rtry_st_seq[5:0] =  6'b0_00010 ;
           12'b101?1??_00001 :  cpy_rtry_st_seq[5:0] =  6'b1_00100 ;
           12'b101?01?_00001 :  cpy_rtry_st_seq[5:0] =  6'b1_00100 ;
           12'b1001???_00001 :  cpy_rtry_st_seq[5:0] =  6'b0_10000 ;

           12'b?????0?_00010 :  cpy_rtry_st_seq[5:0] =  6'b0_00010 ;
           12'b?????1?_00010 :  cpy_rtry_st_seq[5:0] =  6'b1_00100 ;

           12'b???????_00100 :  cpy_rtry_st_seq[5:0] =  6'b0_01000 ;

           12'b??????0_01000 :  cpy_rtry_st_seq[5:0] =  6'b0_01000 ;
           12'b??????1_01000 :  cpy_rtry_st_seq[5:0] =  6'b0_00001 ;

           12'b???????_10000 :  cpy_rtry_st_seq[5:0] =  6'b0_00001 ;

            default          :  cpy_rtry_st_seq[5:0] =  6'b0_00001 ;

      endcase
    end


  assign  eng_arb_rtry_st_req  =  cpy_rtry_st_seq[5];
  assign  cpy_rtry_st_req      =  cpy_rtry_st_seq[5];
  assign  cpy_rtry_st_req_int  =  cpy_rtry_st_seq[5];


  assign  cpy_rtry_st_state[4:0]   =  cpy_rtry_st_seq_q[4:0];
  assign  cpy_rtry_st_idle_st      =  cpy_rtry_st_idle_state;
  assign  cpy_rtry_st_wt4bckoff_st =  cpy_rtry_st_wt4bckoff_state;
  assign  cpy_rtry_st_req_st       =  cpy_rtry_st_req_state;
  assign  cpy_rtry_st_wt4gnt_st    =  cpy_rtry_st_wt4gnt_state;
  assign  cpy_rtry_st_abort_st     =  cpy_rtry_st_abort_state;


  assign  cpy_rtry_st_seq_error    =  cpy_rtry_st_seq_err_int;


  assign  cpy_rtry_st_seq_d[4:0] = ( reset || cpy_rtry_st_seq_err_int ) ? 5'b1 : cpy_rtry_st_seq[4:0];













  assign  rtry_ea_wren         =  arb_eng_st_gnt;
  assign  rtry_ea_wraddr[8:0]  =  arb_eng_st_tag[8:0];
  assign  rtry_ea_wrdata[31:7] =  cpy_st_ea_q[31:7];

  assign  rtry_ea_rden         =  cpy_rtry_st_req_int;







  assign  rtry_ea_rdaddr[8:0]  =  {cpy_rtry_xx_afutag_q[8:1], (cpy_rtry_xx_afutag_q[0] & ~(mmio_eng_st_size_q[1:0] == 2'b11)) };

  

  mcp3_ram512x025  rtry_queue
    ( .clk   ( clock ),

      .wren  ( rtry_ea_wren ),
      .wrad  ( rtry_ea_wraddr[8:0] ),
      .data  ( rtry_ea_wrdata[31:7] ),

      .rden  ( rtry_ea_rden ),
      .rdad  ( rtry_ea_rdaddr[8:0] ),
      .q     ( rtry_ea_rddata[31:7] )
    );





  assign  cpy_rtry_st_ea_bit7   = rtry_ea_rddata[7] || ((mmio_eng_st_size_q[1:0] == 2'b11) && cpy_rtry_xx_afutag_q[0]);
  assign  cpy_rtry_st_ea[63:6]  = { cpy_st_ea_q[63:32],  rtry_ea_rddata[31:8], cpy_rtry_st_ea_bit7, 1'b0 };






  always @*
    begin
      if ( cpy_st_type_sel == 1'b0 )
        cpy_st_opcode_int[7:0] =  AFU_TLX_CMD_ENCODE_DMA_W[7:0];
      else
        cpy_st_opcode_int[7:0] =  AFU_TLX_CMD_ENCODE_DMA_W_N[7:0];
    end

   

  always @*
    begin
      if ( arb_eng_st_gnt || arb_eng_rtry_st_gnt )
        begin
          cpy_st_valid           =   (( arb_eng_st_gnt ) || ( arb_eng_rtry_st_gnt ));
          cpy_st_opcode[7:0]     =     cpy_st_opcode_int[7:0];
          cpy_st_actag[11:0]     =     eng_actag[11:0];
          cpy_st_stream_id[3:0]  =     4'b0;
          if ( arb_eng_rtry_st_gnt )
            begin
              cpy_st_ea_or_obj[67:0] = { 4'b0, cpy_rtry_st_ea[63:6], 6'b0 };
              cpy_st_afutag[15:0]    = { cpy_rtry_xx_dl_q[1:0], 4'b1000, 1'b1, cpy_rtry_xx_afutag_q[8:0] };
              cpy_st_dl[1:0]         =   cpy_rtry_xx_dl_q[1:0];
            end 
          else
            begin
              cpy_st_ea_or_obj[67:0] = { 4'b0, cpy_st_ea_q[63:6], 6'b0 };
              cpy_st_afutag[15:0]    = { mmio_eng_st_size_q[1:0], 5'b10000, arb_eng_st_tag[8:0] };
              cpy_st_dl[1:0]         =   mmio_eng_st_size_q[1:0];
            end
          cpy_st_pl[2:0]         =     3'b000;
          cpy_st_os              =     1'b0;
          cpy_st_be[63:0]        =    64'b0;
          cpy_st_flag[3:0]       =     4'b0;
          cpy_st_endian          =     1'b0;
          cpy_st_bdf[15:0]       =  { cfg_afu_bdf_bus[7:0], cfg_afu_bdf_device[4:0], cfg_afu_bdf_function[2:0] };

          cpy_st_pg_size[5:0]    =     6'b0;
        end
      else
        begin
          cpy_st_valid           =    1'b0;
          cpy_st_opcode[7:0]     =    8'b0;
          cpy_st_actag[11:0]     =   12'b0;
          cpy_st_stream_id[3:0]  =    4'b0;
          cpy_st_ea_or_obj[67:0] =   68'b0;
          cpy_st_afutag[15:0]    =   16'b0;
          cpy_st_dl[1:0]         =    2'b0;
          cpy_st_pl[2:0]         =    3'b0;
          cpy_st_os              =    1'b0;
          cpy_st_be[63:0]        =   64'b0;
          cpy_st_flag[3:0]       =    4'b0;
          cpy_st_endian          =    1'b0;
          cpy_st_bdf[15:0]       =   16'b0;

          cpy_st_pg_size[5:0]    =    6'b0;
        end

    end



  assign  cpy_st_size_256_q    =  (mmio_eng_st_size_q == 2'b11);







  assign  cpy_st_resp_length_en =  reset || ((rspi_cpy_st_resp_val_q || rtry_abort_valid) && (mmio_eng_st_size_q == 2'b11));

  assign  afutag_masked[8:1] = rspi_resp_afutag_q[8:1];
  assign  afutag_masked[0]   = rspi_resp_afutag_q[0] && (mmio_eng_st_size_q != 2'b11);

  mcp3_decoder9x512  decode_afutag
    (
      .din        ( afutag_masked[8:0] ),
      .dout       ( afutag_decoded[511:0] )
    );

  assign  afutag_decoded_valid[511:0]  =  rspi_cpy_st_resp_val_q ?  afutag_decoded[511:0]
                                                                 :  512'b0;


  assign  rtry_abort_valid  = start_cpy_rtry_st_seq & rtry_decode_is_abort;

  assign  rtry_afutag_masked[8:1] = rtry_queue_afutag_q[8:1];
  assign  rtry_afutag_masked[0]   = rtry_queue_afutag_q[0] && (mmio_eng_st_size_q != 2'b11);

  mcp3_decoder9x512  rtry_decode_afutag
    (
      .din        ( rtry_afutag_masked[8:0] ),
      .dout       ( rtry_afutag_decoded[511:0] )
    );

  assign  rtry_afutag_decoded_abort[511:0]  =  rtry_abort_valid  ?  rtry_afutag_decoded[511:0]
                                                                 :  512'b0;

  genvar i;
  generate
    for (i = 0; i < 256; i = i+1)
      begin: cpy_st_resp_length_gen
        always @*
          begin
            if ( reset )
              cpy_st_resp_length_d[i] = 1'b0;
            else
              begin
                if (( afutag_decoded_valid[i*2] == 1'b1 ) && (rtry_afutag_decoded_abort[i*2]))
                  begin
                      cpy_st_resp_length_d[i] = 1'b0;
                  end
                else if ( afutag_decoded_valid[i*2] == 1'b1 )
                  begin
                    if (rspi_resp_dl_q[1:0] == 2'b11)
                      cpy_st_resp_length_d[i] = 1'b0;
                    else
	              cpy_st_resp_length_d[i] = ~cpy_st_resp_length_q[i];
                  end
                else if ( rtry_afutag_decoded_abort[i*2] == 1'b1 )
                  begin
                    if (rtry_queue_dl_q[1:0] == 2'b11)
                      cpy_st_resp_length_d[i] = 1'b0;
                    else
	              cpy_st_resp_length_d[i] = ~cpy_st_resp_length_q[i];
                  end
                else
                  cpy_st_resp_length_d[i] = cpy_st_resp_length_q[i];
              end
          end

        assign eng_arb_set_st_tag_avail[i*2]   = (afutag_decoded_valid[i*2] & ((~cpy_st_resp_length_d[i]) | (mmio_eng_st_size_q != 2'b11))) |
                                            (rtry_afutag_decoded_abort[i*2] & ((~cpy_st_resp_length_d[i]) | (mmio_eng_st_size_q != 2'b11)));
        assign eng_arb_set_st_tag_avail[i*2+1] = afutag_decoded_valid[i*2+1] | rtry_afutag_decoded_abort[i*2+1];
      end
  endgenerate










  assign resp_valid_dly1_d  =  rspi_cpy_st_resp_val_q  |  rtry_abort_valid;
  assign resp_valid_dly2_d  =  resp_valid_dly1_q;

  assign curr_resp_length = cpy_st_resp_length_q[ afutag_masked[8:1] ];

  assign fastpath_valid  = rspi_cpy_st_resp_val_q &
                           ~resp_valid_dly1_q & ~resp_valid_dly2_q &
                           ~rtry_abort_valid &
                           ((mmio_eng_st_size_q != 2'b11) |
                            (rspi_resp_dl_q[1:0] == 2'b11) |
                            (curr_resp_length == 1'b1));

  assign eng_arb_st_fastpath_valid     =  fastpath_valid;
  assign eng_arb_st_fastpath_tag[8:0]  =  afutag_masked[8:0];





  always @ ( posedge clock )
    begin


      cpy_rtry_st_seq_q[4:0]                       <= cpy_rtry_st_seq_d[4:0];


      if ( cpy_st_resp_length_en )
        cpy_st_resp_length_q[255:0]                <= cpy_st_resp_length_d[255:0];


      mmio_eng_st_size_q[1:0]                      <= mmio_eng_st_size[1:0];


      resp_valid_dly1_q                            <= resp_valid_dly1_d;
      resp_valid_dly2_q                            <= resp_valid_dly2_d;

    end

endmodule