data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:45: Cannot find include file: openMSP430_defines.v\n`include "openMSP430_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/185287750/openmsp430/msp_core,data/full_repos/permissive/185287750/openMSP430_defines.v\n             data/full_repos/permissive/185287750/openmsp430/msp_core,data/full_repos/permissive/185287750/openMSP430_defines.v.v\n             data/full_repos/permissive/185287750/openmsp430/msp_core,data/full_repos/permissive/185287750/openMSP430_defines.v.sv\n             openMSP430_defines.v\n             openMSP430_defines.v.v\n             openMSP430_defines.v.sv\n             obj_dir/openMSP430_defines.v\n             obj_dir/openMSP430_defines.v.v\n             obj_dir/openMSP430_defines.v.sv\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:388: Cannot find include file: openMSP430_undefines.v\n`include "openMSP430_undefines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:102: Define or directive not defined: \'`DMEM_MSB\'\noutput [`DMEM_MSB:0] dmem_addr;          \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:102: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\noutput [`DMEM_MSB:0] dmem_addr;          \n                 ^\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:116: Define or directive not defined: \'`PMEM_MSB\'\noutput [`PMEM_MSB:0] pmem_addr;          \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:116: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\noutput [`PMEM_MSB:0] pmem_addr;          \n                 ^\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:224: Define or directive not defined: \'`DMEM_BASE\'\nparameter          DMEM_END      = `DMEM_BASE+`DMEM_SIZE;\n                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:224: Define or directive not defined: \'`DMEM_SIZE\'\nparameter          DMEM_END      = `DMEM_BASE+`DMEM_SIZE;\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:224: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter          DMEM_END      = `DMEM_BASE+`DMEM_SIZE;\n                                                        ^\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:227: Define or directive not defined: \'`DMEM_BASE\'\nwire               eu_dmem_sel   = (eu_mab>=(`DMEM_BASE>>1)) &\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:227: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nwire               eu_dmem_sel   = (eu_mab>=(`DMEM_BASE>>1)) &\n                                                       ^~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:230: Define or directive not defined: \'`DMEM_BASE\'\nwire        [15:0] eu_dmem_addr  = {1\'b0, eu_mab}-(`DMEM_BASE>>1);\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:230: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nwire        [15:0] eu_dmem_addr  = {1\'b0, eu_mab}-(`DMEM_BASE>>1);\n                                                             ^~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:236: Define or directive not defined: \'`DMEM_BASE\'\nassign             ext_dmem_sel  = (ext_mem_addr[15:1]>=(`DMEM_BASE>>1)) &\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:236: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nassign             ext_dmem_sel  = (ext_mem_addr[15:1]>=(`DMEM_BASE>>1)) &\n                                                                   ^~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:239: Define or directive not defined: \'`DMEM_BASE\'\nwire        [15:0] ext_dmem_addr = {1\'b0, ext_mem_addr[15:1]}-(`DMEM_BASE>>1);\n                                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:239: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nwire        [15:0] ext_dmem_addr = {1\'b0, ext_mem_addr[15:1]}-(`DMEM_BASE>>1);\n                                                                         ^~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:245: Define or directive not defined: \'`DMEM_MSB\'\nwire [`DMEM_MSB:0] dmem_addr     =   ext_dmem_en ?  ext_dmem_addr[`DMEM_MSB:0] :  eu_dmem_addr[`DMEM_MSB:0];\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:245: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`DMEM_MSB:0] dmem_addr     =   ext_dmem_en ?  ext_dmem_addr[`DMEM_MSB:0] :  eu_dmem_addr[`DMEM_MSB:0];\n               ^\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:245: Define or directive not defined: \'`DMEM_MSB\'\nwire [`DMEM_MSB:0] dmem_addr     =   ext_dmem_en ?  ext_dmem_addr[`DMEM_MSB:0] :  eu_dmem_addr[`DMEM_MSB:0];\n                                                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:245: Define or directive not defined: \'`DMEM_MSB\'\nwire [`DMEM_MSB:0] dmem_addr     =   ext_dmem_en ?  ext_dmem_addr[`DMEM_MSB:0] :  eu_dmem_addr[`DMEM_MSB:0];\n                                                                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:253: Define or directive not defined: \'`PMEM_SIZE\'\nparameter          PMEM_OFFSET   = (16\'hFFFF-`PMEM_SIZE+1);\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:274: Define or directive not defined: \'`PMEM_MSB\'\nwire [`PMEM_MSB:0] pmem_addr     =  ext_pmem_en ?  ext_pmem_addr[`PMEM_MSB:0] :\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:274: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`PMEM_MSB:0] pmem_addr     =  ext_pmem_en ?  ext_pmem_addr[`PMEM_MSB:0] :\n               ^\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:274: Define or directive not defined: \'`PMEM_MSB\'\nwire [`PMEM_MSB:0] pmem_addr     =  ext_pmem_en ?  ext_pmem_addr[`PMEM_MSB:0] :\n                                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:275: Define or directive not defined: \'`PMEM_MSB\'\n                                    eu_pmem_en  ?  eu_pmem_addr[`PMEM_MSB:0]  : fe_pmem_addr[`PMEM_MSB:0];\n                                                                ^~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:275: Define or directive not defined: \'`PMEM_MSB\'\n                                    eu_pmem_en  ?  eu_pmem_addr[`PMEM_MSB:0]  : fe_pmem_addr[`PMEM_MSB:0];\n                                                                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:286: Define or directive not defined: \'`PER_SIZE\'\nwire               eu_per_sel    =  (eu_mab<(`PER_SIZE>>1));\n                                             ^~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:286: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nwire               eu_per_sel    =  (eu_mab<(`PER_SIZE>>1));\n                                                      ^~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:293: Define or directive not defined: \'`PER_SIZE\'\nassign             ext_per_sel   =  (ext_mem_addr[15:1]<(`PER_SIZE>>1));\n                                                         ^~~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:293: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\nassign             ext_per_sel   =  (ext_mem_addr[15:1]<(`PER_SIZE>>1));\n                                                                  ^~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:299: Define or directive not defined: \'`PER_MSB\'\nwire  [`PER_MSB:0] per_addr_mux  =  ext_per_en ? ext_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];\n       ^~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:299: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire  [`PER_MSB:0] per_addr_mux  =  ext_per_en ? ext_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];\n               ^\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:299: Define or directive not defined: \'`PER_MSB\'\nwire  [`PER_MSB:0] per_addr_mux  =  ext_per_en ? ext_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];\n                                                              ^~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:299: Define or directive not defined: \'`PER_MSB\'\nwire  [`PER_MSB:0] per_addr_mux  =  ext_per_en ? ext_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];\n                                                                                     ^~~~~~~~\n%Error: data/full_repos/permissive/185287750/openmsp430/msp_core/omsp_mem_backbone_unmodif.v:300: Define or directive not defined: \'`PER_AWIDTH\'\nwire        [14:0] per_addr_ful  =  {{15-`PER_AWIDTH{1\'b0}}, per_addr_mux};\n                                         ^~~~~~~~~~~\n%Error: Exiting due to 36 error(s)\n'
module  omsp_mem_backbone_unmodif (


    cpu_halt_cmd,
    dbg_mem_din,
    dmem_addr,
    dmem_cen,
    dmem_din,
    dmem_wen,
    eu_mdb_in,
    fe_mdb_in,
    fe_pmem_wait,
    dma_dout,
    dma_ready,
    dma_resp,
    per_addr,
    per_din,
    per_we,
    per_en,
    pmem_addr,
    pmem_cen,
    pmem_din,
    pmem_wen,


    cpu_halt_st,
    dbg_halt_cmd,
    dbg_mem_addr,
    dbg_mem_dout,
    dbg_mem_en,
    dbg_mem_wr,
    dmem_dout,
    eu_mab,
    eu_mb_en,
    eu_mb_wr,
    eu_mdb_out,
    fe_mab,
    fe_mb_en,
    mclk,
    dma_addr,
    dma_din,
    dma_en,
    dma_priority,
    dma_we,
    per_dout,
    pmem_dout,
    puc_rst,
    scan_enable
);



output               cpu_halt_cmd;
output        [15:0] dbg_mem_din;
output [`DMEM_MSB:0] dmem_addr;
output               dmem_cen;
output        [15:0] dmem_din;
output         [1:0] dmem_wen;
output        [15:0] eu_mdb_in;
output        [15:0] fe_mdb_in;
output               fe_pmem_wait;
output        [15:0] dma_dout;
output               dma_ready;
output               dma_resp;
output        [13:0] per_addr;
output        [15:0] per_din;
output         [1:0] per_we;
output               per_en;
output [`PMEM_MSB:0] pmem_addr;
output               pmem_cen;
output        [15:0] pmem_din;
output         [1:0] pmem_wen;



input                cpu_halt_st;
input                dbg_halt_cmd;
input         [15:1] dbg_mem_addr;
input         [15:0] dbg_mem_dout;
input                dbg_mem_en;
input          [1:0] dbg_mem_wr;
input         [15:0] dmem_dout;
input         [14:0] eu_mab;
input                eu_mb_en;
input          [1:0] eu_mb_wr;
input         [15:0] eu_mdb_out;
input         [14:0] fe_mab;
input                fe_mb_en;
input                mclk;
input         [15:1] dma_addr;
input         [15:0] dma_din;
input                dma_en;
input                dma_priority;
input          [1:0] dma_we;
input         [15:0] per_dout;
input         [15:0] pmem_dout;
input                puc_rst;
input                scan_enable;

wire                 ext_mem_en;
wire          [15:0] ext_mem_din;
wire                 ext_dmem_sel;
wire                 ext_dmem_en;
wire                 ext_pmem_sel;
wire                 ext_pmem_en;
wire                 ext_per_sel;
wire                 ext_per_en;









`ifdef DMA_IF_EN



assign      cpu_halt_cmd  =  dbg_halt_cmd | (dma_en & dma_priority);


assign      dma_resp      = ~dbg_mem_en & ~(ext_dmem_sel | ext_pmem_sel | ext_per_sel) & dma_en;


assign      dma_ready     = ~dbg_mem_en &  (ext_dmem_en  | ext_pmem_en  | ext_per_en | dma_resp);



reg         dma_ready_dly;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)  dma_ready_dly <=  1'b0;
  else          dma_ready_dly <=  dma_ready;


assign      ext_mem_en    =  dbg_mem_en | dma_en;
wire  [1:0] ext_mem_wr    =  dbg_mem_en ? dbg_mem_wr    :  dma_we;
wire [15:1] ext_mem_addr  =  dbg_mem_en ? dbg_mem_addr  :  dma_addr;
wire [15:0] ext_mem_dout  =  dbg_mem_en ? dbg_mem_dout  :  dma_din;


assign      dbg_mem_din   =  ext_mem_din;
assign      dma_dout      =  ext_mem_din & {16{dma_ready_dly}};


`else

assign      cpu_halt_cmd  =  dbg_halt_cmd;


assign      dma_resp      =  1'b1;
assign      dma_ready     =  1'b1;


assign      ext_mem_en    =  dbg_mem_en;
wire  [1:0] ext_mem_wr    =  dbg_mem_wr;
wire [15:1] ext_mem_addr  =  dbg_mem_addr;
wire [15:0] ext_mem_dout  =  dbg_mem_dout;


assign      dbg_mem_din   =  ext_mem_din;
assign      dma_dout      =  16'h0000;


wire [15:1] UNUSED_dma_addr     = dma_addr;
wire [15:0] UNUSED_dma_din      = dma_din;
wire        UNUSED_dma_en       = dma_en;
wire        UNUSED_dma_priority = dma_priority;
wire  [1:0] UNUSED_dma_we       = dma_we;

`endif




parameter          DMEM_END      = `DMEM_BASE+`DMEM_SIZE;


wire               eu_dmem_sel   = (eu_mab>=(`DMEM_BASE>>1)) &
                                   (eu_mab< ( DMEM_END >>1));
wire               eu_dmem_en    = eu_mb_en & eu_dmem_sel;
wire        [15:0] eu_dmem_addr  = {1'b0, eu_mab}-(`DMEM_BASE>>1);





assign             ext_dmem_sel  = (ext_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
                                   (ext_mem_addr[15:1]< ( DMEM_END >>1));
assign             ext_dmem_en   = ext_mem_en &  ext_dmem_sel & ~eu_dmem_en;
wire        [15:0] ext_dmem_addr = {1'b0, ext_mem_addr[15:1]}-(`DMEM_BASE>>1);



wire               dmem_cen      = ~(ext_dmem_en | eu_dmem_en);
wire         [1:0] dmem_wen      =   ext_dmem_en ? ~ext_mem_wr                 : ~eu_mb_wr;
wire [`DMEM_MSB:0] dmem_addr     =   ext_dmem_en ?  ext_dmem_addr[`DMEM_MSB:0] :  eu_dmem_addr[`DMEM_MSB:0];
wire        [15:0] dmem_din      =   ext_dmem_en ?  ext_mem_dout               :  eu_mdb_out;






parameter          PMEM_OFFSET   = (16'hFFFF-`PMEM_SIZE+1);


wire               eu_pmem_sel   = (eu_mab>=(PMEM_OFFSET>>1));
wire               eu_pmem_en    = eu_mb_en & ~|eu_mb_wr & eu_pmem_sel;
wire        [15:0] eu_pmem_addr  = eu_mab-(PMEM_OFFSET>>1);


wire               fe_pmem_sel   = (fe_mab>=(PMEM_OFFSET>>1));
wire               fe_pmem_en    = fe_mb_en & fe_pmem_sel;
wire        [15:0] fe_pmem_addr  = fe_mab-(PMEM_OFFSET>>1);


assign             ext_pmem_sel  = (ext_mem_addr[15:1]>=(PMEM_OFFSET>>1));
assign             ext_pmem_en   = ext_mem_en & ext_pmem_sel & ~eu_pmem_en & ~fe_pmem_en;
wire        [15:0] ext_pmem_addr = {1'b0, ext_mem_addr[15:1]}-(PMEM_OFFSET>>1);



wire               pmem_cen      = ~(fe_pmem_en | eu_pmem_en | ext_pmem_en);
wire         [1:0] pmem_wen      =  ext_pmem_en ? ~ext_mem_wr                 : 2'b11;
wire [`PMEM_MSB:0] pmem_addr     =  ext_pmem_en ?  ext_pmem_addr[`PMEM_MSB:0] :
                                    eu_pmem_en  ?  eu_pmem_addr[`PMEM_MSB:0]  : fe_pmem_addr[`PMEM_MSB:0];
wire        [15:0] pmem_din      =  ext_mem_dout;

wire               fe_pmem_wait  = (fe_pmem_en & eu_pmem_en);







wire               eu_per_sel    =  (eu_mab<(`PER_SIZE>>1));
wire               eu_per_en     =  eu_mb_en & eu_per_sel;





assign             ext_per_sel   =  (ext_mem_addr[15:1]<(`PER_SIZE>>1));
assign             ext_per_en    =  ext_mem_en & ext_per_sel & ~eu_per_en;


wire               per_en        =  ext_per_en | eu_per_en;
wire         [1:0] per_we        =  ext_per_en ? ext_mem_wr                 : eu_mb_wr;
wire  [`PER_MSB:0] per_addr_mux  =  ext_per_en ? ext_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];
wire        [14:0] per_addr_ful  =  {{15-`PER_AWIDTH{1'b0}}, per_addr_mux};
wire        [13:0] per_addr      =  per_addr_ful[13:0];
wire        [15:0] per_din       =  ext_per_en ? ext_mem_dout               : eu_mdb_out;


reg   [15:0] per_dout_val;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)  per_dout_val    <=  16'h0000;
  else          per_dout_val    <=  per_dout;








reg         fe_pmem_en_dly;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst) fe_pmem_en_dly <=  1'b0;
  else         fe_pmem_en_dly <=  fe_pmem_en;

wire fe_pmem_save    = (~fe_pmem_en &  fe_pmem_en_dly) & ~cpu_halt_st;
wire fe_pmem_restore = ( fe_pmem_en & ~fe_pmem_en_dly) |  cpu_halt_st;

`ifdef CLOCK_GATING
wire mclk_bckup_gated;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup_gated),
                                  .clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
`define MCLK_BCKUP           mclk_bckup_gated
`else
wire    UNUSED_scan_enable = scan_enable;
`define MCLK_BCKUP           mclk
`endif

reg  [15:0] pmem_dout_bckup;
always @(posedge `MCLK_BCKUP or posedge puc_rst)
  if (puc_rst)              pmem_dout_bckup     <=  16'h0000;
`ifdef CLOCK_GATING
  else                      pmem_dout_bckup     <=  pmem_dout;
`else
  else if (fe_pmem_save)    pmem_dout_bckup     <=  pmem_dout;
`endif


reg         pmem_dout_bckup_sel;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)              pmem_dout_bckup_sel <=  1'b0;
  else if (fe_pmem_save)    pmem_dout_bckup_sel <=  1'b1;
  else if (fe_pmem_restore) pmem_dout_bckup_sel <=  1'b0;

assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;







reg [1:0] eu_mdb_in_sel;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)  eu_mdb_in_sel  <= 2'b00;
  else          eu_mdb_in_sel  <= {eu_pmem_en, eu_per_en};


assign          eu_mdb_in       = eu_mdb_in_sel[1] ? pmem_dout    :
                                  eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;







reg   [1:0] ext_mem_din_sel;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)  ext_mem_din_sel <= 2'b00;
  else          ext_mem_din_sel <= {ext_pmem_en, ext_per_en};


assign          ext_mem_din      = ext_mem_din_sel[1] ? pmem_dout    :
                                   ext_mem_din_sel[0] ? per_dout_val : dmem_dout;


endmodule
module  omsp_mem_backbone_unmodif (


    cpu_halt_cmd,
    dbg_mem_din,
    dmem_addr,
    dmem_cen,
    dmem_din,
    dmem_wen,
    eu_mdb_in,
    fe_mdb_in,
    fe_pmem_wait,
    dma_dout,
    dma_ready,
    dma_resp,
    per_addr,
    per_din,
    per_we,
    per_en,
    pmem_addr,
    pmem_cen,
    pmem_din,
    pmem_wen,


    cpu_halt_st,
    dbg_halt_cmd,
    dbg_mem_addr,
    dbg_mem_dout,
    dbg_mem_en,
    dbg_mem_wr,
    dmem_dout,
    eu_mab,
    eu_mb_en,
    eu_mb_wr,
    eu_mdb_out,
    fe_mab,
    fe_mb_en,
    mclk,
    dma_addr,
    dma_din,
    dma_en,
    dma_priority,
    dma_we,
    per_dout,
    pmem_dout,
    puc_rst,
    scan_enable
);




output               cpu_halt_cmd;
output        [15:0] dbg_mem_din;
output [`DMEM_MSB:0] dmem_addr;
output               dmem_cen;
output        [15:0] dmem_din;
output         [1:0] dmem_wen;
output        [15:0] eu_mdb_in;
output        [15:0] fe_mdb_in;
output               fe_pmem_wait;
output        [15:0] dma_dout;
output               dma_ready;
output               dma_resp;
output        [13:0] per_addr;
output        [15:0] per_din;
output         [1:0] per_we;
output               per_en;
output [`PMEM_MSB:0] pmem_addr;
output               pmem_cen;
output        [15:0] pmem_din;
output         [1:0] pmem_wen;



input                cpu_halt_st;
input                dbg_halt_cmd;
input         [15:1] dbg_mem_addr;
input         [15:0] dbg_mem_dout;
input                dbg_mem_en;
input          [1:0] dbg_mem_wr;
input         [15:0] dmem_dout;
input         [14:0] eu_mab;
input                eu_mb_en;
input          [1:0] eu_mb_wr;
input         [15:0] eu_mdb_out;
input         [14:0] fe_mab;
input                fe_mb_en;
input                mclk;
input         [15:1] dma_addr;
input         [15:0] dma_din;
input                dma_en;
input                dma_priority;
input          [1:0] dma_we;
input         [15:0] per_dout;
input         [15:0] pmem_dout;
input                puc_rst;
input                scan_enable;

wire                 ext_mem_en;
wire          [15:0] ext_mem_din;
wire                 ext_dmem_sel;
wire                 ext_dmem_en;
wire                 ext_pmem_sel;
wire                 ext_pmem_en;
wire                 ext_per_sel;
wire                 ext_per_en;









`ifdef DMA_IF_EN



assign      cpu_halt_cmd  =  dbg_halt_cmd | (dma_en & dma_priority);


assign      dma_resp      = ~dbg_mem_en & ~(ext_dmem_sel | ext_pmem_sel | ext_per_sel) & dma_en;


assign      dma_ready     = ~dbg_mem_en &  (ext_dmem_en  | ext_pmem_en  | ext_per_en | dma_resp);



reg         dma_ready_dly;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)  dma_ready_dly <=  1'b0;
  else          dma_ready_dly <=  dma_ready;


assign      ext_mem_en    =  dbg_mem_en | dma_en;
wire  [1:0] ext_mem_wr    =  dbg_mem_en ? dbg_mem_wr    :  dma_we;
wire [15:1] ext_mem_addr  =  dbg_mem_en ? dbg_mem_addr  :  dma_addr;
wire [15:0] ext_mem_dout  =  dbg_mem_en ? dbg_mem_dout  :  dma_din;


assign      dbg_mem_din   =  ext_mem_din;
assign      dma_dout      =  ext_mem_din & {16{dma_ready_dly}};


`else

assign      cpu_halt_cmd  =  dbg_halt_cmd;


assign      dma_resp      =  1'b1;
assign      dma_ready     =  1'b1;


assign      ext_mem_en    =  dbg_mem_en;
wire  [1:0] ext_mem_wr    =  dbg_mem_wr;
wire [15:1] ext_mem_addr  =  dbg_mem_addr;
wire [15:0] ext_mem_dout  =  dbg_mem_dout;


assign      dbg_mem_din   =  ext_mem_din;
assign      dma_dout      =  16'h0000;


wire [15:1] UNUSED_dma_addr     = dma_addr;
wire [15:0] UNUSED_dma_din      = dma_din;
wire        UNUSED_dma_en       = dma_en;
wire        UNUSED_dma_priority = dma_priority;
wire  [1:0] UNUSED_dma_we       = dma_we;

`endif




parameter          DMEM_END      = `DMEM_BASE+`DMEM_SIZE;


wire               eu_dmem_sel   = (eu_mab>=(`DMEM_BASE>>1)) &
                                   (eu_mab< ( DMEM_END >>1));
wire               eu_dmem_en    = eu_mb_en & eu_dmem_sel;
wire        [15:0] eu_dmem_addr  = {1'b0, eu_mab}-(`DMEM_BASE>>1);





assign             ext_dmem_sel  = (ext_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
                                   (ext_mem_addr[15:1]< ( DMEM_END >>1));
assign             ext_dmem_en   = ext_mem_en &  ext_dmem_sel & ~eu_dmem_en;
wire        [15:0] ext_dmem_addr = {1'b0, ext_mem_addr[15:1]}-(`DMEM_BASE>>1);



wire               dmem_cen      = ~(ext_dmem_en | eu_dmem_en);
wire         [1:0] dmem_wen      =   ext_dmem_en ? ~ext_mem_wr                 : ~eu_mb_wr;
wire [`DMEM_MSB:0] dmem_addr     =   ext_dmem_en ?  ext_dmem_addr[`DMEM_MSB:0] :  eu_dmem_addr[`DMEM_MSB:0];
wire        [15:0] dmem_din      =   ext_dmem_en ?  ext_mem_dout               :  eu_mdb_out;






parameter          PMEM_OFFSET   = (16'hFFFF-`PMEM_SIZE+1);


wire               eu_pmem_sel   = (eu_mab>=(PMEM_OFFSET>>1));
wire               eu_pmem_en    = eu_mb_en & ~|eu_mb_wr & eu_pmem_sel;
wire        [15:0] eu_pmem_addr  = eu_mab-(PMEM_OFFSET>>1);


wire               fe_pmem_sel   = (fe_mab>=(PMEM_OFFSET>>1));
wire               fe_pmem_en    = fe_mb_en & fe_pmem_sel;
wire        [15:0] fe_pmem_addr  = fe_mab-(PMEM_OFFSET>>1);


assign             ext_pmem_sel  = (ext_mem_addr[15:1]>=(PMEM_OFFSET>>1));
assign             ext_pmem_en   = ext_mem_en & ext_pmem_sel & ~eu_pmem_en & ~fe_pmem_en;
wire        [15:0] ext_pmem_addr = {1'b0, ext_mem_addr[15:1]}-(PMEM_OFFSET>>1);



wire               pmem_cen      = ~(fe_pmem_en | eu_pmem_en | ext_pmem_en);
wire         [1:0] pmem_wen      =  ext_pmem_en ? ~ext_mem_wr                 : 2'b11;
wire [`PMEM_MSB:0] pmem_addr     =  ext_pmem_en ?  ext_pmem_addr[`PMEM_MSB:0] :
                                    eu_pmem_en  ?  eu_pmem_addr[`PMEM_MSB:0]  : fe_pmem_addr[`PMEM_MSB:0];
wire        [15:0] pmem_din      =  ext_mem_dout;

wire               fe_pmem_wait  = (fe_pmem_en & eu_pmem_en);







wire               eu_per_sel    =  (eu_mab<(`PER_SIZE>>1));
wire               eu_per_en     =  eu_mb_en & eu_per_sel;





assign             ext_per_sel   =  (ext_mem_addr[15:1]<(`PER_SIZE>>1));
assign             ext_per_en    =  ext_mem_en & ext_per_sel & ~eu_per_en;


wire               per_en        =  ext_per_en | eu_per_en;
wire         [1:0] per_we        =  ext_per_en ? ext_mem_wr                 : eu_mb_wr;
wire  [`PER_MSB:0] per_addr_mux  =  ext_per_en ? ext_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];
wire        [14:0] per_addr_ful  =  {{15-`PER_AWIDTH{1'b0}}, per_addr_mux};
wire        [13:0] per_addr      =  per_addr_ful[13:0];
wire        [15:0] per_din       =  ext_per_en ? ext_mem_dout               : eu_mdb_out;


reg   [15:0] per_dout_val;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)  per_dout_val    <=  16'h0000;
  else          per_dout_val    <=  per_dout;








reg         fe_pmem_en_dly;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst) fe_pmem_en_dly <=  1'b0;
  else         fe_pmem_en_dly <=  fe_pmem_en;

wire fe_pmem_save    = (~fe_pmem_en &  fe_pmem_en_dly) & ~cpu_halt_st;
wire fe_pmem_restore = ( fe_pmem_en & ~fe_pmem_en_dly) |  cpu_halt_st;

`ifdef CLOCK_GATING
wire mclk_bckup_gated;
omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup_gated),
                                  .clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
`define MCLK_BCKUP           mclk_bckup_gated
`else
wire    UNUSED_scan_enable = scan_enable;
`define MCLK_BCKUP           mclk
`endif

reg  [15:0] pmem_dout_bckup;
always @(posedge `MCLK_BCKUP or posedge puc_rst)
  if (puc_rst)              pmem_dout_bckup     <=  16'h0000;
`ifdef CLOCK_GATING
  else                      pmem_dout_bckup     <=  pmem_dout;
`else
  else if (fe_pmem_save)    pmem_dout_bckup     <=  pmem_dout;
`endif


reg         pmem_dout_bckup_sel;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)              pmem_dout_bckup_sel <=  1'b0;
  else if (fe_pmem_save)    pmem_dout_bckup_sel <=  1'b1;
  else if (fe_pmem_restore) pmem_dout_bckup_sel <=  1'b0;

assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;







reg [1:0] eu_mdb_in_sel;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)  eu_mdb_in_sel  <= 2'b00;
  else          eu_mdb_in_sel  <= {eu_pmem_en, eu_per_en};


assign          eu_mdb_in       = eu_mdb_in_sel[1] ? pmem_dout    :
                                  eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;







reg   [1:0] ext_mem_din_sel;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)  ext_mem_din_sel <= 2'b00;
  else          ext_mem_din_sel <= {ext_pmem_en, ext_per_en};


assign          ext_mem_din      = ext_mem_din_sel[1] ? pmem_dout    :
                                   ext_mem_din_sel[0] ? per_dout_val : dmem_dout;


endmodule