data/full_repos/permissive/158824477/submodules/PulseRain_MCU/memory/lattice/MXO2_4K/single_port_ram.v
None: at end of input
1: b'%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/memory/lattice/MXO2_4K/single_port_ram.v:21: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/memory/lattice/MXO2_4K,data/full_repos/permissive/158824477/config.vh\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/memory/lattice/MXO2_4K,data/full_repos/permissive/158824477/config.vh.v\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/memory/lattice/MXO2_4K,data/full_repos/permissive/158824477/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module single_port_ram #(parameter ADDR_WIDTH = 12, DATA_WIDTH = 16) (
			input  wire                               clk,
            input  wire [ADDR_WIDTH - 1 : 0]         addr,
            input  wire [DATA_WIDTH - 1 : 0]         din,
            input  wire [DATA_WIDTH / 8 - 1 : 0]     write_en, 
            output reg  [DATA_WIDTH - 1 : 0]         dout
);

    reg [7 : 0] mem_hi [(1<<ADDR_WIDTH)-1:0];
	reg [7 : 0] mem_low [(1<<ADDR_WIDTH)-1:0];
	always @(posedge clk) begin
		if (write_en[0]) begin
			mem_low[addr] <= din[7 : 0];
		end
		if (write_en[1]) begin
			mem_hi[addr] <= din[15 : 8];
		end
	end
 
    always @(posedge clk) begin
        dout <= {mem_hi[addr], mem_low[addr]};
    end
                
endmodule
module single_port_ram #(parameter ADDR_WIDTH = 12, DATA_WIDTH = 16) (
			input  wire                               clk,
            input  wire [ADDR_WIDTH - 1 : 0]         addr,
            input  wire [DATA_WIDTH - 1 : 0]         din,
            input  wire [DATA_WIDTH / 8 - 1 : 0]     write_en, 
            output reg  [DATA_WIDTH - 1 : 0]         dout
);


    reg [7 : 0] mem_hi [(1<<ADDR_WIDTH)-1:0];
	reg [7 : 0] mem_low [(1<<ADDR_WIDTH)-1:0];
	always @(posedge clk) begin
		if (write_en[0]) begin
			mem_low[addr] <= din[7 : 0];
		end
		if (write_en[1]) begin
			mem_hi[addr] <= din[15 : 8];
		end
	end
 
    always @(posedge clk) begin
        dout <= {mem_hi[addr], mem_low[addr]};
    end
                
endmodule