data/full_repos/permissive/136584400/digital_logic_labs/lab04/1/sources/counter_mod8.v
1: b"%Error: data/full_repos/permissive/136584400/digital_logic_labs/lab04/1/sources/counter_mod8.v:25: Cannot find file containing module: 'divider'\n  divider divider1(.clk(cp), .clk_N(clk_N));\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136584400/digital_logic_labs/lab04/1/sources,data/full_repos/permissive/136584400/divider\n             data/full_repos/permissive/136584400/digital_logic_labs/lab04/1/sources,data/full_repos/permissive/136584400/divider.v\n             data/full_repos/permissive/136584400/digital_logic_labs/lab04/1/sources,data/full_repos/permissive/136584400/divider.sv\n             divider\n             divider.v\n             divider.sv\n             obj_dir/divider\n             obj_dir/divider.v\n             obj_dir/divider.sv\n%Error: data/full_repos/permissive/136584400/digital_logic_labs/lab04/1/sources/counter_mod8.v:26: Cannot find file containing module: 'counter4'\n  counter4 counter1(.cp(clk_N), .clr(1), .qcc(qcc), .m(1), .ld(ld), .A(A), .Q(Q));\n  ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module counter_mod8(cp, qcc, Q);
  input cp;
  output qcc;
  output [3:0] Q;

  reg [3:0] A;
  wire ld;
  wire clk_N;

  assign ld = (Q[3] & Q[0]) ? 0 : 1;
  
initial begin
  A <= 4'b0010;
end

  divider divider1(.clk(cp), .clk_N(clk_N));
  counter4 counter1(.cp(clk_N), .clr(1), .qcc(qcc), .m(1), .ld(ld), .A(A), .Q(Q));
endmodule
module counter_mod8(cp, qcc, Q);

  input cp;
  output qcc;
  output [3:0] Q;

  reg [3:0] A;
  wire ld;
  wire clk_N;

  assign ld = (Q[3] & Q[0]) ? 0 : 1;
  
initial begin
  A <= 4'b0010;
end

  divider divider1(.clk(cp), .clk_N(clk_N));
  counter4 counter1(.cp(clk_N), .clr(1), .qcc(qcc), .m(1), .ld(ld), .A(A), .Q(Q));
endmodule