data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v
1: b'%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:1: Cannot find include file: ctrl_encode_def.v\n`include "ctrl_encode_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131249673/MIPS_L_MultiCycle,data/full_repos/permissive/131249673/ctrl_encode_def.v\n             data/full_repos/permissive/131249673/MIPS_L_MultiCycle,data/full_repos/permissive/131249673/ctrl_encode_def.v.v\n             data/full_repos/permissive/131249673/MIPS_L_MultiCycle,data/full_repos/permissive/131249673/ctrl_encode_def.v.sv\n             ctrl_encode_def.v\n             ctrl_encode_def.v.v\n             ctrl_encode_def.v.sv\n             obj_dir/ctrl_encode_def.v\n             obj_dir/ctrl_encode_def.v.v\n             obj_dir/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:14: Define or directive not defined: \'`ALUOp_NOP\'\n          `ALUOp_NOP:  C = B;                         \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:14: syntax error, unexpected \':\', expecting endcase\n          `ALUOp_NOP:  C = B;                         \n                    ^\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:15: Define or directive not defined: \'`ALUOp_ADD\'\n        `ALUOp_ADD:  C = A + B;                     \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:16: Define or directive not defined: \'`ALUOp_ADDU\'\n          `ALUOp_ADDU: C = A + B;                     \n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:17: Define or directive not defined: \'`ALUOp_SUB\'\n        `ALUOp_SUB:  C = A - B;                     \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:18: Define or directive not defined: \'`ALUOp_SUBU\'\n          `ALUOp_SUBU: C = A - B;                     \n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:19: Define or directive not defined: \'`ALUOp_AND\'\n          `ALUOp_AND:  C = A & B;                     \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:20: Define or directive not defined: \'`ALUOp_OR\'\n          `ALUOp_OR:   C = A | B;                     \n          ^~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:21: Define or directive not defined: \'`ALUOp_XOR\'\n          `ALUOp_XOR:  C = A ^ B;                     \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:22: Define or directive not defined: \'`ALUOp_NOR\'\n        `ALUOp_NOR:  C = ~(A | B);                  \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:23: Define or directive not defined: \'`ALUOp_SLL\'\n          `ALUOp_SLL:  C = (B << A[4:0]);             \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:24: Define or directive not defined: \'`ALUOp_SRL\'\n          `ALUOp_SRL:  C = (B >> A[4:0]);             \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:25: Define or directive not defined: \'`ALUOp_SLT\'\n          `ALUOp_SLT:  C = (A < B) ? 32\'d1 : 32\'d0;   \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:26: Define or directive not defined: \'`ALUOp_SLTU\'\n          `ALUOp_SLTU: C = ({1\'b0, A} < {1\'b0, B}) ? 32\'d1 : 32\'d0;  \n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:27: Define or directive not defined: \'`ALUOp_EQL\'\n          `ALUOp_EQL:  C = (A == B) ? 32\'d1 : 32\'d0;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:28: Define or directive not defined: \'`ALUOp_BNE\'\n          `ALUOp_BNE:  C = (A != B) ? 32\'d1 : 32\'d0;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:29: Define or directive not defined: \'`ALUOp_GT0\'\n          `ALUOp_GT0:  C = (A >  0) ? 32\'d1 : 32\'d0;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:30: Define or directive not defined: \'`ALUOp_GE0\'\n          `ALUOp_GE0:  C = (A >= 0) ? 32\'d1 : 32\'d0;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:31: Define or directive not defined: \'`ALUOp_LT0\'\n          `ALUOp_LT0:  C = (A <  0) ? 32\'d1 : 32\'d0;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:32: Define or directive not defined: \'`ALUOp_LE0\'\n          `ALUOp_LE0:  C = (A <= 0) ? 32\'d1 : 32\'d0;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:33: Define or directive not defined: \'`ALUOp_SRA\'\n          `ALUOp_SRA: begin                           \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:34: syntax error, unexpected \')\', expecting \';\'\n        for(i=1; i<=A[4:0]; i=i+1)\n                                 ^\n%Error: data/full_repos/permissive/131249673/MIPS_L_MultiCycle/alu.v:39: syntax error, unexpected \':\', expecting clocking\n          default:   C = 32\'d0;                     \n                 ^\n%Error: Exiting due to 24 error(s)\n'
module alu(A, B, ALUOp, C, Compare);
           
   input  signed [31:0] A, B;
   input  signed [4:0]  ALUOp;
   output signed [31:0] C;
   output 				Compare;
   
   reg [31:0] C;
   integer    i;
       
   always @( A or B or ALUOp ) begin
      case ( ALUOp )
          `ALUOp_NOP:  C = B;
		      `ALUOp_ADD:  C = A + B;
          `ALUOp_ADDU: C = A + B;
		      `ALUOp_SUB:  C = A - B;
          `ALUOp_SUBU: C = A - B;
          `ALUOp_AND:  C = A & B;
          `ALUOp_OR:   C = A | B;
          `ALUOp_XOR:  C = A ^ B;
		      `ALUOp_NOR:  C = ~(A | B);
          `ALUOp_SLL:  C = (B << A[4:0]);
          `ALUOp_SRL:  C = (B >> A[4:0]);
          `ALUOp_SLT:  C = (A < B) ? 32'd1 : 32'd0;
          `ALUOp_SLTU: C = ({1'b0, A} < {1'b0, B}) ? 32'd1 : 32'd0;
          `ALUOp_EQL:  C = (A == B) ? 32'd1 : 32'd0;
          `ALUOp_BNE:  C = (A != B) ? 32'd1 : 32'd0;
          `ALUOp_GT0:  C = (A >  0) ? 32'd1 : 32'd0;
          `ALUOp_GE0:  C = (A >= 0) ? 32'd1 : 32'd0;
          `ALUOp_LT0:  C = (A <  0) ? 32'd1 : 32'd0;
          `ALUOp_LE0:  C = (A <= 0) ? 32'd1 : 32'd0;
          `ALUOp_SRA: begin
		      for(i=1; i<=A[4:0]; i=i+1)
			     C[32-i] = B[31];
			    for(i=31-A[4:0]; i>=0; i=i-1)
			     C[i] = B[i+A[4:0]];
          end                             
          default:   C = 32'd0;
      endcase
   end
   
   assign Compare = C[0];

endmodule
module alu(A, B, ALUOp, C, Compare);

           
   input  signed [31:0] A, B;
   input  signed [4:0]  ALUOp;
   output signed [31:0] C;
   output 				Compare;
   
   reg [31:0] C;
   integer    i;
       
   always @( A or B or ALUOp ) begin
      case ( ALUOp )
          `ALUOp_NOP:  C = B;
		      `ALUOp_ADD:  C = A + B;
          `ALUOp_ADDU: C = A + B;
		      `ALUOp_SUB:  C = A - B;
          `ALUOp_SUBU: C = A - B;
          `ALUOp_AND:  C = A & B;
          `ALUOp_OR:   C = A | B;
          `ALUOp_XOR:  C = A ^ B;
		      `ALUOp_NOR:  C = ~(A | B);
          `ALUOp_SLL:  C = (B << A[4:0]);
          `ALUOp_SRL:  C = (B >> A[4:0]);
          `ALUOp_SLT:  C = (A < B) ? 32'd1 : 32'd0;
          `ALUOp_SLTU: C = ({1'b0, A} < {1'b0, B}) ? 32'd1 : 32'd0;
          `ALUOp_EQL:  C = (A == B) ? 32'd1 : 32'd0;
          `ALUOp_BNE:  C = (A != B) ? 32'd1 : 32'd0;
          `ALUOp_GT0:  C = (A >  0) ? 32'd1 : 32'd0;
          `ALUOp_GE0:  C = (A >= 0) ? 32'd1 : 32'd0;
          `ALUOp_LT0:  C = (A <  0) ? 32'd1 : 32'd0;
          `ALUOp_LE0:  C = (A <= 0) ? 32'd1 : 32'd0;
          `ALUOp_SRA: begin
		      for(i=1; i<=A[4:0]; i=i+1)
			     C[32-i] = B[31];
			    for(i=31-A[4:0]; i>=0; i=i-1)
			     C[i] = B[i+A[4:0]];
          end                             
          default:   C = 32'd0;
      endcase
   end
   
   assign Compare = C[0];

endmodule