data/full_repos/permissive/107757225/audio/square-wave.sv
data/verilator_xmls/7655614e-c32f-4f08-a8e5-4b6b76136bfb.xml
module square_wave(clk,rst,dac_out);
   input clk;
   input rst;
   output reg dac_out;
   reg [11:0]  counter;

   always @(posedge clk)
     begin
        if (rst == 1'b1  ||  counter == 12'd3999)
          counter <= 0;
        else
          counter <= counter + 1'b1;


        if (rst == 1'b0  &&  counter < 12'd2000)
          dac_out = 1'b1;
        else
          dac_out = 1'b0;
      end
endmodule
module square_wave(clk,rst,dac_out);

   input clk;
   input rst;
   output reg dac_out;
   reg [11:0]  counter;

   always @(posedge clk)
     begin
        if (rst == 1'b1  ||  counter == 12'd3999)
          counter <= 0;
        else
          counter <= counter + 1'b1;


        if (rst == 1'b0  &&  counter < 12'd2000)
          dac_out = 1'b1;
        else
          dac_out = 1'b0;
      end
endmodule