data/full_repos/permissive/210918583/boards/tf530r2/tf530r2_ram_top.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/210918583/boards/tf530r2/tf530r2_ram_top.v:119: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'tf530r2_ram_top\'\nmodule tf530r2_ram_top(\n       ^~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'intreqr\'\nmodule intreqr(\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/210918583/boards/tf530r2/tf530r2_ram_top.v:112: Signal definition not found, creating implicitly: \'IDEWAIT_INT\'\n                                                                                            : ... Suggested alternative: \'IDEWAIT\'\nassign IDEWAIT = IDEWAIT_INT ? 1\'b1 : 1\'b0;\n                 ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/210918583/boards/tf530r2/tf530r2_ram_top.v:113: Signal definition not found, creating implicitly: \'INT2_INT\'\nassign INT2 = INT2_INT ? 1\'bz : 1\'b0;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/210918583/boards/tf530r2/tf530r2_ram_top.v:72: Cannot find file containing module: \'ram_top\'\n ram_top RAMTOP (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210918583/boards/tf530r2,data/full_repos/permissive/210918583/ram_top\n             data/full_repos/permissive/210918583/boards/tf530r2,data/full_repos/permissive/210918583/ram_top.v\n             data/full_repos/permissive/210918583/boards/tf530r2,data/full_repos/permissive/210918583/ram_top.sv\n             ram_top\n             ram_top.v\n             ram_top.sv\n             obj_dir/ram_top\n             obj_dir/ram_top.v\n             obj_dir/ram_top.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module intreqr(
    
    input CLK, 
    
    input [31:0] A,
    inout [15:0] D,
    
    input AS20, 
    input RW20, 
    input INT2, 

    input DTACK,

    output ACK, 
    output INTCYCLE, 
    output IDEWAIT
);

assign INTCYCLE = 1'b1;
assign ACK = 1'b1;
assign IDEWAIT = 1'b1;

endmodule
module intreqr(
    
    input CLK, 
    
    input [31:0] A,
    inout [15:0] D,
    
    input AS20, 
    input RW20, 
    input INT2, 

    input DTACK,

    output ACK, 
    output INTCYCLE, 
    output IDEWAIT
);


assign INTCYCLE = 1'b1;
assign ACK = 1'b1;
assign IDEWAIT = 1'b1;

endmodule