data/full_repos/permissive/128100618/SV/FP_operations_design.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/128100618/SV/FP_operations_design.v:280: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                     : ... Top module \'DE2_Top\'\nmodule DE2_Top (\n       ^~~~~~~\n                                                                                     : ... Top module \'fpneg\'\nmodule fpneg(fout, f1) ;\n       ^~~~~\n                                                                                     : ... Top module \'int2fp\'\nmodule int2fp(fp_out, int_in, scale_in) ;\n       ^~~~~~\n                                                                                     : ... Top module \'fp2int\'\nmodule fp2int(int_out, fp_in, scale_in) ;\n       ^~~~~~\n                                                                                     : ... Top module \'fpinv\'\nmodule fpinv (fout, f1);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FP_operations_design.v:263: Input port connection \'num\' expects 4 bits on the pin connection, but pin connection\'s SEL generates 1 bits.\n                                                                                  : ... In instance DE2_Top\n HexDigit d2(HEX2, disp[8]);\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/128100618/SV/FP_operations_design.v:619: Operator SHIFTR expects 10 bits on the LHS, but LHS\'s VARREF \'m_in\' generates 9 bits.\n                                                                                  : ... In instance fp2int\n assign abs_int = (e_in>8\'h80)? (m_in >> (8\'h89 - e_in)) : 10\'d0 ;\n                                      ^~\n%Error: Exiting due to 3 warning(s)\n'
module DE2_Top (


    input         CLOCK_27,
    input         CLOCK_50,
    input         EXT_CLOCK,

    input  [3:0]  KEY,

    input  [17:0] SW,

    output [6:0]  HEX0,
    output [6:0]  HEX1,
    output [6:0]  HEX2,
    output [6:0]  HEX3,
    output [6:0]  HEX4,
    output [6:0]  HEX5,
    output [6:0]  HEX6,
    output [6:0]  HEX7,

    output [8:0]  LEDG,
    output [17:0] LEDR,

    output        UART_TXD,
    input         UART_RXD,

    output        IRDA_TXD,
    input         IRDA_RXD,

    inout  [15:0] DRAM_DQ,
    output [11:0] DRAM_ADDR,
    output        DRAM_LDQM,
    output        DRAM_UDQM,
    output        DRAM_WE_N,
    output        DRAM_CAS_N,
    output        DRAM_RAS_N,
    output        DRAM_CS_N,
    output        DRAM_BA_0,
    output        DRAM_BA_1,
    output        DRAM_CLK,
    output        DRAM_CKE,

    inout  [7:0]  FL_DQ,
    output [21:0] FL_ADDR,
    output        FL_WE_N,
    output        FL_RST_N,
    output        FL_OE_N,
    output        FL_CE_N,

    inout  [15:0] SRAM_DQ,
    output [17:0] SRAM_ADDR,
    output        SRAM_UB_N,
    output        SRAM_LB_N,
    output        SRAM_WE_N,
    output        SRAM_CE_N,
    output        SRAM_OE_N,

    inout  [15:0] OTG_DATA,
    output [1:0]  OTG_ADDR,
    output        OTG_CS_N,
    output        OTG_RD_N,
    output        OTG_WR_N,
    output        OTG_RST_N,
    output        OTG_FSPEED,
    output        OTG_LSPEED,
    input         OTG_INT0,
    input         OTG_INT1,
    input         OTG_DREQ0,
    input         OTG_DREQ1,
    output        OTG_DACK0_N,
    output        OTG_DACK1_N,

    inout  [7:0]  LCD_DATA,
    output        LCD_ON,
    output        LCD_BLON,
    output        LCD_RW,
    output        LCD_EN,
    output        LCD_RS,

    inout         SD_DAT,
    inout         SD_DAT3,
    inout         SD_CMD,
    output        SD_CLK,

    inout         I2C_SDAT,
    output        I2C_SCLK,

    input         PS2_DAT,
    input         PS2_CLK,

    input         TDI,
    input         TCK,
    input         TCS,
    output        TDO,

    output        VGA_CLK,
    output        VGA_HS,
    output        VGA_VS,
    output        VGA_BLANK,
    output        VGA_SYNC,
    output [9:0]  VGA_R,
    output [9:0]  VGA_G,
    output [9:0]  VGA_B,

    inout  [15:0] ENET_DATA,
    output        ENET_CMD,
    output        ENET_CS_N,
    output        ENET_WR_N,
    output        ENET_RD_N,
    output        ENET_RST_N,
    input         ENET_INT,
    output        ENET_CLK,

    inout         AUD_ADCLRCK,
    input         AUD_ADCDAT,
    inout         AUD_DACLRCK,
    output        AUD_DACDAT,
    inout         AUD_BCLK,
    output        AUD_XCK,

    input  [7:0]  TD_DATA,
    input         TD_HS,
    input         TD_VS,
    output        TD_RESET,

    inout  [35:0] GPIO_0,
    inout  [35:0] GPIO_1
);





   assign HEX3 = 7'h7F;


   assign HEX6 = 7'h7F;
   assign HEX7 = 7'h7F;
 




   assign GPIO_0 = 36'hzzzzzzzzz;
   assign GPIO_1 = 36'hzzzzzzzzz;






   assign DRAM_ADDR  = 12'h0;
   assign DRAM_BA_0  = 1'b0;
   assign DRAM_BA_1  = 1'b0;
   assign DRAM_CAS_N = 1'b1;
   assign DRAM_CKE   = 1'b0;
   assign DRAM_CLK   = 1'b0;
   assign DRAM_CS_N  = 1'b1;
   assign DRAM_DQ    = 16'hzzzz;
   assign DRAM_LDQM  = 1'b0;
   assign DRAM_RAS_N = 1'b1;
   assign DRAM_UDQM  = 1'b0;
   assign DRAM_WE_N  = 1'b1;


   assign ENET_CLK   = 1'b0;
   assign ENET_CS_N  = 1'b1;
   assign ENET_CMD   = 1'b0;
   assign ENET_DATA  = 16'hzzzz;
   assign ENET_RD_N  = 1'b1;
   assign ENET_RST_N = 1'b1;
   assign ENET_WR_N  = 1'b1;


   assign FL_ADDR  = 22'h0;
   assign FL_CE_N  = 1'b1;
   assign FL_DQ    = 8'hzz;
   assign FL_OE_N  = 1'b1;
   assign FL_RST_N = 1'b1;
   assign FL_WE_N  = 1'b1;


   assign LCD_BLON = 1'b0;
   assign LCD_DATA = 8'hzz;
   assign LCD_EN   = 1'b0;
   assign LCD_ON   = 1'b0;
   assign LCD_RS   = 1'b0;
   assign LCD_RW   = 1'b0;


   assign OTG_ADDR    = 2'h0;
   assign OTG_CS_N    = 1'b1;
   assign OTG_DACK0_N = 1'b1;
   assign OTG_DACK1_N = 1'b1;
   assign OTG_FSPEED  = 1'b1;
   assign OTG_DATA    = 16'hzzzz;
   assign OTG_LSPEED  = 1'b1;
   assign OTG_RD_N    = 1'b1;
   assign OTG_RST_N   = 1'b1;
   assign OTG_WR_N    = 1'b1;


   assign SD_DAT = 1'bz;
   assign SD_CLK = 1'b0;


   assign SRAM_ADDR = 18'h0;
   assign SRAM_CE_N = 1'b1;
   assign SRAM_DQ   = 16'hzzzz;
   assign SRAM_LB_N = 1'b1;
   assign SRAM_OE_N = 1'b1;
   assign SRAM_UB_N = 1'b1;
   assign SRAM_WE_N = 1'b1;


   assign VGA_CLK   = 1'b0;
   assign VGA_BLANK = 1'b0;
   assign VGA_SYNC  = 1'b0;
   assign VGA_HS    = 1'b0;
   assign VGA_VS    = 1'b0;
   assign VGA_R     = 10'h0;
   assign VGA_G     = 10'h0;
   assign VGA_B     = 10'h0;
   



   assign IRDA_TXD = 1'b0;

   assign TDO = 1'b0;
   assign UART_TXD = 1'b0;
	





	wire [17:0] f1, invsqrtout, multout1, multout2	;
	assign f1 = SW ;
	fpinvsqrt test1(invsqrtout, f1);
	fpmult test2(multout1, invsqrtout, f1) ;
	fpmult test3(multout2, multout1, multout1);
	assign LEDR = (KEY[3])? invsqrtout : invsqrtout ;

	
	wire [17:0] disp ;
	assign disp = KEY[1]? invsqrtout : SW ;
	HexDigit d0(HEX0, disp[3:0]) ;
	HexDigit d1(HEX1, disp[7:4]);
	HexDigit d2(HEX2, disp[8]);
	HexDigit d4(HEX4, disp[12:9]);
	HexDigit d5(HEX5, disp[16:13]);
	
	
	
endmodule
module DE2_Top (


    input         CLOCK_27,
    input         CLOCK_50,
    input         EXT_CLOCK,

    input  [3:0]  KEY,

    input  [17:0] SW,

    output [6:0]  HEX0,
    output [6:0]  HEX1,
    output [6:0]  HEX2,
    output [6:0]  HEX3,
    output [6:0]  HEX4,
    output [6:0]  HEX5,
    output [6:0]  HEX6,
    output [6:0]  HEX7,

    output [8:0]  LEDG,
    output [17:0] LEDR,

    output        UART_TXD,
    input         UART_RXD,

    output        IRDA_TXD,
    input         IRDA_RXD,

    inout  [15:0] DRAM_DQ,
    output [11:0] DRAM_ADDR,
    output        DRAM_LDQM,
    output        DRAM_UDQM,
    output        DRAM_WE_N,
    output        DRAM_CAS_N,
    output        DRAM_RAS_N,
    output        DRAM_CS_N,
    output        DRAM_BA_0,
    output        DRAM_BA_1,
    output        DRAM_CLK,
    output        DRAM_CKE,

    inout  [7:0]  FL_DQ,
    output [21:0] FL_ADDR,
    output        FL_WE_N,
    output        FL_RST_N,
    output        FL_OE_N,
    output        FL_CE_N,

    inout  [15:0] SRAM_DQ,
    output [17:0] SRAM_ADDR,
    output        SRAM_UB_N,
    output        SRAM_LB_N,
    output        SRAM_WE_N,
    output        SRAM_CE_N,
    output        SRAM_OE_N,

    inout  [15:0] OTG_DATA,
    output [1:0]  OTG_ADDR,
    output        OTG_CS_N,
    output        OTG_RD_N,
    output        OTG_WR_N,
    output        OTG_RST_N,
    output        OTG_FSPEED,
    output        OTG_LSPEED,
    input         OTG_INT0,
    input         OTG_INT1,
    input         OTG_DREQ0,
    input         OTG_DREQ1,
    output        OTG_DACK0_N,
    output        OTG_DACK1_N,

    inout  [7:0]  LCD_DATA,
    output        LCD_ON,
    output        LCD_BLON,
    output        LCD_RW,
    output        LCD_EN,
    output        LCD_RS,

    inout         SD_DAT,
    inout         SD_DAT3,
    inout         SD_CMD,
    output        SD_CLK,

    inout         I2C_SDAT,
    output        I2C_SCLK,

    input         PS2_DAT,
    input         PS2_CLK,

    input         TDI,
    input         TCK,
    input         TCS,
    output        TDO,

    output        VGA_CLK,
    output        VGA_HS,
    output        VGA_VS,
    output        VGA_BLANK,
    output        VGA_SYNC,
    output [9:0]  VGA_R,
    output [9:0]  VGA_G,
    output [9:0]  VGA_B,

    inout  [15:0] ENET_DATA,
    output        ENET_CMD,
    output        ENET_CS_N,
    output        ENET_WR_N,
    output        ENET_RD_N,
    output        ENET_RST_N,
    input         ENET_INT,
    output        ENET_CLK,

    inout         AUD_ADCLRCK,
    input         AUD_ADCDAT,
    inout         AUD_DACLRCK,
    output        AUD_DACDAT,
    inout         AUD_BCLK,
    output        AUD_XCK,

    input  [7:0]  TD_DATA,
    input         TD_HS,
    input         TD_VS,
    output        TD_RESET,

    inout  [35:0] GPIO_0,
    inout  [35:0] GPIO_1
);






   assign HEX3 = 7'h7F;


   assign HEX6 = 7'h7F;
   assign HEX7 = 7'h7F;
 




   assign GPIO_0 = 36'hzzzzzzzzz;
   assign GPIO_1 = 36'hzzzzzzzzz;






   assign DRAM_ADDR  = 12'h0;
   assign DRAM_BA_0  = 1'b0;
   assign DRAM_BA_1  = 1'b0;
   assign DRAM_CAS_N = 1'b1;
   assign DRAM_CKE   = 1'b0;
   assign DRAM_CLK   = 1'b0;
   assign DRAM_CS_N  = 1'b1;
   assign DRAM_DQ    = 16'hzzzz;
   assign DRAM_LDQM  = 1'b0;
   assign DRAM_RAS_N = 1'b1;
   assign DRAM_UDQM  = 1'b0;
   assign DRAM_WE_N  = 1'b1;


   assign ENET_CLK   = 1'b0;
   assign ENET_CS_N  = 1'b1;
   assign ENET_CMD   = 1'b0;
   assign ENET_DATA  = 16'hzzzz;
   assign ENET_RD_N  = 1'b1;
   assign ENET_RST_N = 1'b1;
   assign ENET_WR_N  = 1'b1;


   assign FL_ADDR  = 22'h0;
   assign FL_CE_N  = 1'b1;
   assign FL_DQ    = 8'hzz;
   assign FL_OE_N  = 1'b1;
   assign FL_RST_N = 1'b1;
   assign FL_WE_N  = 1'b1;


   assign LCD_BLON = 1'b0;
   assign LCD_DATA = 8'hzz;
   assign LCD_EN   = 1'b0;
   assign LCD_ON   = 1'b0;
   assign LCD_RS   = 1'b0;
   assign LCD_RW   = 1'b0;


   assign OTG_ADDR    = 2'h0;
   assign OTG_CS_N    = 1'b1;
   assign OTG_DACK0_N = 1'b1;
   assign OTG_DACK1_N = 1'b1;
   assign OTG_FSPEED  = 1'b1;
   assign OTG_DATA    = 16'hzzzz;
   assign OTG_LSPEED  = 1'b1;
   assign OTG_RD_N    = 1'b1;
   assign OTG_RST_N   = 1'b1;
   assign OTG_WR_N    = 1'b1;


   assign SD_DAT = 1'bz;
   assign SD_CLK = 1'b0;


   assign SRAM_ADDR = 18'h0;
   assign SRAM_CE_N = 1'b1;
   assign SRAM_DQ   = 16'hzzzz;
   assign SRAM_LB_N = 1'b1;
   assign SRAM_OE_N = 1'b1;
   assign SRAM_UB_N = 1'b1;
   assign SRAM_WE_N = 1'b1;


   assign VGA_CLK   = 1'b0;
   assign VGA_BLANK = 1'b0;
   assign VGA_SYNC  = 1'b0;
   assign VGA_HS    = 1'b0;
   assign VGA_VS    = 1'b0;
   assign VGA_R     = 10'h0;
   assign VGA_G     = 10'h0;
   assign VGA_B     = 10'h0;
   



   assign IRDA_TXD = 1'b0;

   assign TDO = 1'b0;
   assign UART_TXD = 1'b0;
	





	wire [17:0] f1, invsqrtout, multout1, multout2	;
	assign f1 = SW ;
	fpinvsqrt test1(invsqrtout, f1);
	fpmult test2(multout1, invsqrtout, f1) ;
	fpmult test3(multout2, multout1, multout1);
	assign LEDR = (KEY[3])? invsqrtout : invsqrtout ;

	
	wire [17:0] disp ;
	assign disp = KEY[1]? invsqrtout : SW ;
	HexDigit d0(HEX0, disp[3:0]) ;
	HexDigit d1(HEX1, disp[7:4]);
	HexDigit d2(HEX2, disp[8]);
	HexDigit d4(HEX4, disp[12:9]);
	HexDigit d5(HEX5, disp[16:13]);
	
	
	
endmodule