data/full_repos/permissive/143278/ivltests/pr1637208.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1637208.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #1 pixel0 = \'h55555555;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1637208.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #1 clock = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1637208.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #1 clock = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1637208.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #1 pixel0 = \'haaaaaaaa;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1637208.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #1 clock = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1637208.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 clock = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1637208.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (mem[0] !== 32\'haaaaaaaa) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1637208.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (foo !== mem[1]) begin\n      ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
   reg clock;
   reg [31:0] pixel0;
   reg [31:0] mem [0:1];

   always @(posedge clock) begin
      mem[0] <= pixel0;
   end

   always @(posedge clock) begin
      mem[1] <= mem[0];
   end

   reg sel;
   wire [31:0] foo = sel? mem[1] : mem[0];

   initial begin
      clock = 1;
      sel = 0;
      #1 pixel0 = 'h55555555;
      #1 clock = 0;
      #1 clock = 1;
      #1 pixel0 = 'haaaaaaaa;
      #1 clock = 0;
      #1 clock = 1;
      #1 if (mem[0] !== 32'haaaaaaaa) begin
	 $display("FAILED -- mem[0] = %h", mem[0]);
	 $finish;
      end

      if (mem[1] !== 32'h55555555) begin
	 $display("FAILED == mem[1] = %h", mem[1]);
	 $finish;
      end

      if (foo !== mem[0]) begin
	 $display("FAILED -- mem[sel=0] != %h", foo);
	 $finish;
      end

      sel = 1;

      #1 if (foo !== mem[1]) begin
	 $display("FAILED -- mem[sel=1] != %h", foo);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;

   reg clock;
   reg [31:0] pixel0;
   reg [31:0] mem [0:1];

   always @(posedge clock) begin
      mem[0] <= pixel0;
   end

   always @(posedge clock) begin
      mem[1] <= mem[0];
   end

   reg sel;
   wire [31:0] foo = sel? mem[1] : mem[0];

   initial begin
      clock = 1;
      sel = 0;
      #1 pixel0 = 'h55555555;
      #1 clock = 0;
      #1 clock = 1;
      #1 pixel0 = 'haaaaaaaa;
      #1 clock = 0;
      #1 clock = 1;
      #1 if (mem[0] !== 32'haaaaaaaa) begin
	 $display("FAILED -- mem[0] = %h", mem[0]);
	 $finish;
      end

      if (mem[1] !== 32'h55555555) begin
	 $display("FAILED == mem[1] = %h", mem[1]);
	 $finish;
      end

      if (foo !== mem[0]) begin
	 $display("FAILED -- mem[sel=0] != %h", foo);
	 $finish;
      end

      sel = 1;

      #1 if (foo !== mem[1]) begin
	 $display("FAILED -- mem[sel=1] != %h", foo);
	 $finish;
      end

      $display("PASSED");
   end

endmodule