data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic/adder_tree.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic/adder_tree.v:22: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/arithmetic,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module adder_tree (clk, en, din_data, dout_data);
`include "util.vh"
  parameter  DataBits = 8;
  parameter  NumWords = 4;

  localparam Stages   = clog2(NumWords);
  localparam SumBits  = DataBits + Stages;

  input                          clk;
  input                          en;

  input  [DataBits*NumWords-1:0] din_data;

  output reg [SumBits-1:0]       dout_data;


  localparam HalfBits = DataBits * NumWords / 2;
  localparam TreeBits = (NumWords == 2) ? DataBits :
                                          (DataBits + clog2(NumWords/2));

  wire [HalfBits-1:0]  din_data_0,  din_data_1;
  wire [TreeBits-1:0]  tree_data_0, tree_data_1;


  assign {din_data_1, din_data_0} = din_data;

  generate if (NumWords > 2) begin: add_trees

    adder_tree #(
      .DataBits (DataBits),
      .NumWords (NumWords/2))
    tree_0 (
      .clk      (clk),
      .en       (en),
      .din_data (din_data_0),
      .dout_data(tree_data_0));

    adder_tree #(
      .DataBits (DataBits),
      .NumWords (NumWords/2))
    tree_1 (
      .clk      (clk),
      .en       (en),
      .din_data (din_data_1),
      .dout_data(tree_data_1));

  end else begin: no_trees
    assign tree_data_0 = din_data_0;
    assign tree_data_1 = din_data_1;
  end endgenerate


  always @(posedge clk) begin
    if (en)
      dout_data <= tree_data_0 + tree_data_1;
  end

endmodule
module adder_tree (clk, en, din_data, dout_data);

`include "util.vh"
  parameter  DataBits = 8;
  parameter  NumWords = 4;

  localparam Stages   = clog2(NumWords);
  localparam SumBits  = DataBits + Stages;

  input                          clk;
  input                          en;

  input  [DataBits*NumWords-1:0] din_data;

  output reg [SumBits-1:0]       dout_data;


  localparam HalfBits = DataBits * NumWords / 2;
  localparam TreeBits = (NumWords == 2) ? DataBits :
                                          (DataBits + clog2(NumWords/2));

  wire [HalfBits-1:0]  din_data_0,  din_data_1;
  wire [TreeBits-1:0]  tree_data_0, tree_data_1;


  assign {din_data_1, din_data_0} = din_data;

  generate if (NumWords > 2) begin: add_trees

    adder_tree #(
      .DataBits (DataBits),
      .NumWords (NumWords/2))
    tree_0 (
      .clk      (clk),
      .en       (en),
      .din_data (din_data_0),
      .dout_data(tree_data_0));

    adder_tree #(
      .DataBits (DataBits),
      .NumWords (NumWords/2))
    tree_1 (
      .clk      (clk),
      .en       (en),
      .din_data (din_data_1),
      .dout_data(tree_data_1));

  end else begin: no_trees
    assign tree_data_0 = din_data_0;
    assign tree_data_1 = din_data_1;
  end endgenerate


  always @(posedge clk) begin
    if (en)
      dout_data <= tree_data_0 + tree_data_1;
  end

endmodule