data/full_repos/permissive/193790231/lab08/lab08part03.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/193790231/lab08/lab08part03.v:22: Unsupported: Ignoring delay on this delayed statement.\n  forever #50 clk=~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab08/lab08part03.v:31: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/193790231/lab08/lab08part03.v:37: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: data/full_repos/permissive/193790231/lab08/lab08part03.v:7: Cannot find file containing module: \'genericRAM\'\n    genericRAM #(8, 5) ram_inst(.Q(q), .dataIN(data), .addr(addr), .pCLK(clk), .enWR(wren));\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193790231/lab08,data/full_repos/permissive/193790231/genericRAM\n             data/full_repos/permissive/193790231/lab08,data/full_repos/permissive/193790231/genericRAM.v\n             data/full_repos/permissive/193790231/lab08,data/full_repos/permissive/193790231/genericRAM.sv\n             genericRAM\n             genericRAM.v\n             genericRAM.sv\n             obj_dir/genericRAM\n             obj_dir/genericRAM.v\n             obj_dir/genericRAM.sv\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab08/lab08part03.v:29: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                           : ... In instance tbtestl8p3\n   addr = i;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab08/lab08part03.v:30: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                           : ... In instance tbtestl8p3\n   data = i;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/193790231/lab08/lab08part03.v:36: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                           : ... In instance tbtestl8p3\n   addr = i;\n        ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tbtestl8p3;
	reg  [4:0]addr;
	reg  wren, clk;
	reg  [7:0]data;
	wire [7:0]q;
	lab08part03 testl8p1(q, data, addr, clk, wren);

	initial begin
		clk = 1'b0;
	end
	initial begin
		forever #50 clk=~clk;
	end

	integer i;
	initial begin
		for (i=0; i<32; i=i+1) begin
			wren = 1'b1;
			addr = i;
			data = i;
			#100;
		end
		data = 0;
		for (i=0; i<32; i=i+1) begin
			wren = 1'b0;
			addr = i;
			#100;
		end
	end

endmodule
module tbtestl8p3;

	reg  [4:0]addr;
	reg  wren, clk;
	reg  [7:0]data;
	wire [7:0]q;
	lab08part03 testl8p1(q, data, addr, clk, wren);

	initial begin
		clk = 1'b0;
	end
	initial begin
		forever #50 clk=~clk;
	end

	integer i;
	initial begin
		for (i=0; i<32; i=i+1) begin
			wren = 1'b1;
			addr = i;
			data = i;
			#100;
		end
		data = 0;
		for (i=0; i<32; i=i+1) begin
			wren = 1'b0;
			addr = i;
			#100;
		end
	end

endmodule