data/full_repos/permissive/109608368/memory/Select16to1.v
data/verilator_xmls/ed6c2b03-a1c3-4db0-b0a1-d262e92210e6.xml
module Select16to1(in, select, out);
    input [31:0] in;
    input [3:0] select;
    output [1:0] out;
    reg [1:0] reg_out;

    always @ (*)
    begin
        case (select[3:0])
            4'd0: reg_out[1:0] <= in[1:0];
            4'd1: reg_out[1:0] <= in[3:2];
            4'd2: reg_out[1:0] <= in[5:4];
            4'd3: reg_out[1:0] <= in[7:6];
            4'd4: reg_out[1:0] <= in[9:8];
            4'd5: reg_out[1:0] <= in[11:10];
            4'd6: reg_out[1:0] <= in[13:12];
            4'd7: reg_out[1:0] <= in[15:14];
            4'd8: reg_out[1:0] <= in[17:16];
            4'd9: reg_out[1:0] <= in[19:18];
            4'd10: reg_out[1:0] <= in[21:20];
            4'd11: reg_out[1:0] <= in[23:22];
            4'd12: reg_out[1:0] <= in[25:24];
            4'd13: reg_out[1:0] <= in[27:26];
            4'd14: reg_out[1:0] <= in[29:28];
            4'd15: reg_out[1:0] <= in[31:30];

       endcase
    end

    assign out[1:0] = reg_out[1:0];
    
endmodule
module Select16to1(in, select, out);

    input [31:0] in;
    input [3:0] select;
    output [1:0] out;
    reg [1:0] reg_out;

    always @ (*)
    begin
        case (select[3:0])
            4'd0: reg_out[1:0] <= in[1:0];
            4'd1: reg_out[1:0] <= in[3:2];
            4'd2: reg_out[1:0] <= in[5:4];
            4'd3: reg_out[1:0] <= in[7:6];
            4'd4: reg_out[1:0] <= in[9:8];
            4'd5: reg_out[1:0] <= in[11:10];
            4'd6: reg_out[1:0] <= in[13:12];
            4'd7: reg_out[1:0] <= in[15:14];
            4'd8: reg_out[1:0] <= in[17:16];
            4'd9: reg_out[1:0] <= in[19:18];
            4'd10: reg_out[1:0] <= in[21:20];
            4'd11: reg_out[1:0] <= in[23:22];
            4'd12: reg_out[1:0] <= in[25:24];
            4'd13: reg_out[1:0] <= in[27:26];
            4'd14: reg_out[1:0] <= in[29:28];
            4'd15: reg_out[1:0] <= in[31:30];

       endcase
    end

    assign out[1:0] = reg_out[1:0];
    
endmodule