data/full_repos/permissive/143278/ivltests/task_mem.v
 line:45: before: ";"
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/task_mem.v:33: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                        : ... In instance test\n     tempram[i] = i;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/task_mem.v:36: Operator NEQCASE expects 32 bits on the LHS, but LHS\'s ARRAYSEL generates 16 bits.\n                                                                        : ... In instance test\n    if (tempram[i] !== i) begin\n                   ^~~\n%Error: Exiting due to 2 warning(s)\n'
module test;
   parameter addrsiz = 14;
   parameter ramsiz = 1 << addrsiz;

   task loadram;
      integer i, j;
      reg [15:0] memword;
      reg [15:0] tempram[0:(2*ramsiz)-1];
      begin
	 for (i = 0; i < 16; i = i + 2)
	    tempram[i] = i;

	 for (i = 0; i < 16; i = i + 2)
	   if (tempram[i] !== i) begin
	      $display("FAILED -- %m.tempram[%d] = %b", i, tempram[i]);
	      $finish;
	   end

	 $display("PASSED");
      end
   endtask

   initial loadram;

endmodule
module test;

   parameter addrsiz = 14;
   parameter ramsiz = 1 << addrsiz;

   task loadram;
      integer i, j;
      reg [15:0] memword;
      reg [15:0] tempram[0:(2*ramsiz)-1];
      begin
	 for (i = 0; i < 16; i = i + 2)
	    tempram[i] = i;

	 for (i = 0; i < 16; i = i + 2)
	   if (tempram[i] !== i) begin
	      $display("FAILED -- %m.tempram[%d] = %b", i, tempram[i]);
	      $finish;
	   end

	 $display("PASSED");
      end
   endtask

   initial loadram;

endmodule