data/full_repos/permissive/114943225/vga_fillarea.v
 line:66: before: "mainder"
1: b"%Error: data/full_repos/permissive/114943225/vga_fillarea.v:37: Cannot find file containing module: 'vga_colour'\nvga_colour vgacol0(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114943225,data/full_repos/permissive/114943225/vga_colour\n             data/full_repos/permissive/114943225,data/full_repos/permissive/114943225/vga_colour.v\n             data/full_repos/permissive/114943225,data/full_repos/permissive/114943225/vga_colour.sv\n             vga_colour\n             vga_colour.v\n             vga_colour.sv\n             obj_dir/vga_colour\n             obj_dir/vga_colour.v\n             obj_dir/vga_colour.sv\n%Error: Exiting due to 1 error(s)\n"
module vga_fillarea(
	xin, yin,
	x0, y0, x1, y1,
	colour,
	writeout_r, writeout_g, writeout_b
);


input [9:0] xin;
input [9:0] yin;
input [9:0] x0;
input [9:0] y0;
input [9:0] x1;
input [9:0] y1;
input [4:0] colour;


output reg [7:0] writeout_r;
output reg [7:0] writeout_g;
output reg [7:0] writeout_b;


wire [7:0] col_r_gen;
wire [7:0] col_g_gen;
wire [7:0] col_b_gen;
wire cm;

vga_colour vgacol0(
	.cin(colour),
	.cout_r(col_r_gen),
	.cout_g(col_g_gen),
	.cout_b(col_b_gen),
	.c_mask(cm)
);



always @(*) begin


	writeout_r = 8'bZZZZZZZZ;
	writeout_g = 8'bZZZZZZZZ;
	writeout_b = 8'bZZZZZZZZ;
	

	if ((xin >= x0) && (yin >= y0) && (xin <= x1) && (yin <= y1)) begin
		if (cm) begin
			writeout_r = col_r_gen;
			writeout_g = col_g_gen;
			writeout_b = col_b_gen;
		end
	end 

end

endmodule
module vga_fillarea(
	xin, yin,
	x0, y0, x1, y1,
	colour,
	writeout_r, writeout_g, writeout_b
);



input [9:0] xin;
input [9:0] yin;
input [9:0] x0;
input [9:0] y0;
input [9:0] x1;
input [9:0] y1;
input [4:0] colour;


output reg [7:0] writeout_r;
output reg [7:0] writeout_g;
output reg [7:0] writeout_b;


wire [7:0] col_r_gen;
wire [7:0] col_g_gen;
wire [7:0] col_b_gen;
wire cm;

vga_colour vgacol0(
	.cin(colour),
	.cout_r(col_r_gen),
	.cout_g(col_g_gen),
	.cout_b(col_b_gen),
	.c_mask(cm)
);



always @(*) begin


	writeout_r = 8'bZZZZZZZZ;
	writeout_g = 8'bZZZZZZZZ;
	writeout_b = 8'bZZZZZZZZ;
	

	if ((xin >= x0) && (yin >= y0) && (xin <= x1) && (yin <= y1)) begin
		if (cm) begin
			writeout_r = col_r_gen;
			writeout_g = col_g_gen;
			writeout_b = col_b_gen;
		end
	end 

end

endmodule