data/full_repos/permissive/192276289/source/SI5345_SPI/si5345_config_top.v
1: b"%Error: data/full_repos/permissive/192276289/source/SI5345_SPI/si5345_config_top.v:40: Cannot find file containing module: 'spi_sys_clock_gen'\n    spi_sys_clock_gen top_clock_gen(\n    ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/192276289/source/SI5345_SPI,data/full_repos/permissive/192276289/spi_sys_clock_gen\n             data/full_repos/permissive/192276289/source/SI5345_SPI,data/full_repos/permissive/192276289/spi_sys_clock_gen.v\n             data/full_repos/permissive/192276289/source/SI5345_SPI,data/full_repos/permissive/192276289/spi_sys_clock_gen.sv\n             spi_sys_clock_gen\n             spi_sys_clock_gen.v\n             spi_sys_clock_gen.sv\n             obj_dir/spi_sys_clock_gen\n             obj_dir/spi_sys_clock_gen.v\n             obj_dir/spi_sys_clock_gen.sv\n%Error: data/full_repos/permissive/192276289/source/SI5345_SPI/si5345_config_top.v:71: Cannot find file containing module: 'si5345_reg_write_read_spi'\n    si5345_reg_write_read_spi\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/192276289/source/SI5345_SPI/si5345_config_top.v:95: Cannot find file containing module: 'si5345_spi_configuration_vio'\n    si5345_spi_configuration_vio top_si5345_vio(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module si5345_config_top(
    input OSC_CLK_40M_PIN,
    input FPGA_RESET_N_PIN,

    output SI5345_MOSI_POUT,
    input SI5345_MISO_PIN,
    output SPI_CS_N_POUT,
    output SCLK_POUT,
    output [1:0] IN_SEL,
    output I2C_OR_SPI_POUT,
    output SI5345_RST_N_POUT

    );

    wire reset_n;
    wire top_clk40m;
    wire clock_good_to_vio_w;
    spi_sys_clock_gen top_clock_gen(
        .osc_clk_i(OSC_CLK_40M_PIN),
        .fpga_rst_n_i(FPGA_RESET_N_PIN),
        .clk_40m_o(top_clk40m),
        .reset_n_o(reset_n),
        .clock_good_o(clock_good_to_vio_w)

        );

    wire start_configuration_from_vio_w;
    wire si5345_rw_from_vio_w;
    wire [15:0] si5345_reg_addr_from_vio_w;
    wire [7:0] si5345_reg_wr_value_from_vio_w;
    wire [7:0] si5345_reg_rd_value_to_vio_w;
    wire si5345_spi_busy_to_vio_w;
    wire si5345_spi_done_to_vio;
    wire reset_n_from_vio;




    wire start_configuration_pulse_w;
    reg [1:0] start_configuration_r;
    always @(posedge top_clk40m or negedge reset_n)
        if(~reset_n)
            start_configuration_r <= 2'b00;
        else
            start_configuration_r <= {start_configuration_r[0], start_configuration_from_vio_w};

    assign start_configuration_pulse_w = start_configuration_r[0]
                                         && (~start_configuration_r[1]);
    si5345_reg_write_read_spi
    #(
        .SPI_DOUT_WIDTH(16),
        .SPI_DIN_WIDTH(8)
    )top_si5345_reg_wr_rd(
        .sys_clk(top_clk40m),
        .reset_n(reset_n && reset_n_from_vio),

        .start_i(start_configuration_pulse_w),
        .rw_i(si5345_rw_from_vio_w),
        .spi_clk_div2(12'h13),
        .reg_addr_i(si5345_reg_addr_from_vio_w),
        .reg_value_wr_i(si5345_reg_wr_value_from_vio_w),
        .reg_value_rd_o(si5345_reg_rd_value_to_vio_w),

        .busy_o(si5345_spi_busy_to_vio_w),
        .done_o(si5345_spi_done_to_vio),

        .cs_n_o(SPI_CS_N_POUT),
        .sclk_o(SCLK_POUT),
        .sdo_o(SI5345_MOSI_POUT),
        .sdi_i(SI5345_MISO_PIN)
        );
    wire [1:0] si5345_in_sel_from_vio_w;
    si5345_spi_configuration_vio top_si5345_vio(
        .clk(top_clk40m),
        .probe_in0(si5345_spi_busy_to_vio_w),
        .probe_in1(si5345_spi_done_to_vio),
        .probe_in2(si5345_reg_rd_value_to_vio_w),
        .probe_out0(si5345_rw_from_vio_w),
        .probe_out1(start_configuration_from_vio_w),
        .probe_out2(si5345_reg_addr_from_vio_w),
        .probe_out3(si5345_reg_wr_value_from_vio_w),
        .probe_out4(reset_n_from_vio),
        .probe_out5(si5345_in_sel_from_vio_w)
        );

    assign I2C_OR_SPI_POUT = 1'b0;
    assign SI5345_RST_N_POUT = 1'b1;
    assign IN_SEL = si5345_in_sel_from_vio_w;
endmodule
module si5345_config_top(
    input OSC_CLK_40M_PIN,
    input FPGA_RESET_N_PIN,

    output SI5345_MOSI_POUT,
    input SI5345_MISO_PIN,
    output SPI_CS_N_POUT,
    output SCLK_POUT,
    output [1:0] IN_SEL,
    output I2C_OR_SPI_POUT,
    output SI5345_RST_N_POUT

    );


    wire reset_n;
    wire top_clk40m;
    wire clock_good_to_vio_w;
    spi_sys_clock_gen top_clock_gen(
        .osc_clk_i(OSC_CLK_40M_PIN),
        .fpga_rst_n_i(FPGA_RESET_N_PIN),
        .clk_40m_o(top_clk40m),
        .reset_n_o(reset_n),
        .clock_good_o(clock_good_to_vio_w)

        );

    wire start_configuration_from_vio_w;
    wire si5345_rw_from_vio_w;
    wire [15:0] si5345_reg_addr_from_vio_w;
    wire [7:0] si5345_reg_wr_value_from_vio_w;
    wire [7:0] si5345_reg_rd_value_to_vio_w;
    wire si5345_spi_busy_to_vio_w;
    wire si5345_spi_done_to_vio;
    wire reset_n_from_vio;




    wire start_configuration_pulse_w;
    reg [1:0] start_configuration_r;
    always @(posedge top_clk40m or negedge reset_n)
        if(~reset_n)
            start_configuration_r <= 2'b00;
        else
            start_configuration_r <= {start_configuration_r[0], start_configuration_from_vio_w};

    assign start_configuration_pulse_w = start_configuration_r[0]
                                         && (~start_configuration_r[1]);
    si5345_reg_write_read_spi
    #(
        .SPI_DOUT_WIDTH(16),
        .SPI_DIN_WIDTH(8)
    )top_si5345_reg_wr_rd(
        .sys_clk(top_clk40m),
        .reset_n(reset_n && reset_n_from_vio),

        .start_i(start_configuration_pulse_w),
        .rw_i(si5345_rw_from_vio_w),
        .spi_clk_div2(12'h13),
        .reg_addr_i(si5345_reg_addr_from_vio_w),
        .reg_value_wr_i(si5345_reg_wr_value_from_vio_w),
        .reg_value_rd_o(si5345_reg_rd_value_to_vio_w),

        .busy_o(si5345_spi_busy_to_vio_w),
        .done_o(si5345_spi_done_to_vio),

        .cs_n_o(SPI_CS_N_POUT),
        .sclk_o(SCLK_POUT),
        .sdo_o(SI5345_MOSI_POUT),
        .sdi_i(SI5345_MISO_PIN)
        );
    wire [1:0] si5345_in_sel_from_vio_w;
    si5345_spi_configuration_vio top_si5345_vio(
        .clk(top_clk40m),
        .probe_in0(si5345_spi_busy_to_vio_w),
        .probe_in1(si5345_spi_done_to_vio),
        .probe_in2(si5345_reg_rd_value_to_vio_w),
        .probe_out0(si5345_rw_from_vio_w),
        .probe_out1(start_configuration_from_vio_w),
        .probe_out2(si5345_reg_addr_from_vio_w),
        .probe_out3(si5345_reg_wr_value_from_vio_w),
        .probe_out4(reset_n_from_vio),
        .probe_out5(si5345_in_sel_from_vio_w)
        );

    assign I2C_OR_SPI_POUT = 1'b0;
    assign SI5345_RST_N_POUT = 1'b1;
    assign IN_SEL = si5345_in_sel_from_vio_w;
endmodule