data/full_repos/permissive/143278/ivltests/pr1598445.v
 line:25: before: "sig"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1598445.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #1 en1 = 0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1598445.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (sig2 !== 1\'b1) begin\n      ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1598445.v:25: Unsupported: Verilog 1995 force\n      force sig = 0;\n      ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1598445.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (sig2 !== 1\'b0) begin\n      ^\n%Error: data/full_repos/permissive/143278/ivltests/pr1598445.v:32: Unsupported: Verilog 1995 release\n      release sig;\n      ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1598445.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (sig2 !== 1\'b1) begin\n      ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

   wire sig;
   reg	en0, en1;

   pullup (sig);
   assign sig = en0 ? 1'b0 : 1'bz;
   assign sig = en1 ? 1'b1 : 1'bz;

   reg	sig2;
   always @(sig)
     sig2 = sig;

   initial begin

      en0 = 0;
      en1 = 1;
      #1 en1 = 0;

      #1 if (sig2 !== 1'b1) begin
	 $display("FAILED -- sig2=%b, sig=%b", sig2, sig);
	 $finish;
      end

      force sig = 0;

      #1 if (sig2 !== 1'b0) begin
	 $display("FAILED -- sig2=%b, sig=%b", sig2, sig);
	 $finish;
      end

      release sig;

      #1 if (sig2 !== 1'b1) begin
	 $display("FAILED -- sig2=%b, sig=%b", sig2, sig);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module test();


   wire sig;
   reg	en0, en1;

   pullup (sig);
   assign sig = en0 ? 1'b0 : 1'bz;
   assign sig = en1 ? 1'b1 : 1'bz;

   reg	sig2;
   always @(sig)
     sig2 = sig;

   initial begin

      en0 = 0;
      en1 = 1;
      #1 en1 = 0;

      #1 if (sig2 !== 1'b1) begin
	 $display("FAILED -- sig2=%b, sig=%b", sig2, sig);
	 $finish;
      end

      force sig = 0;

      #1 if (sig2 !== 1'b0) begin
	 $display("FAILED -- sig2=%b, sig=%b", sig2, sig);
	 $finish;
      end

      release sig;

      #1 if (sig2 !== 1'b1) begin
	 $display("FAILED -- sig2=%b, sig=%b", sig2, sig);
	 $finish;
      end

      $display("PASSED");
   end

endmodule