data/full_repos/permissive/157490365/buildV1.1/tb_stack3_el.v
 line:35: before: "for"
1: b'%Error: data/full_repos/permissive/157490365/buildV1.1/tb_stack3_el.v:12: Unsupported or unknown PLI call: $dumpfile\n  initial begin $dumpfile("tb_stack3.vcd"); $dumpvars(0,tb); end\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/157490365/buildV1.1/tb_stack3_el.v:12: Unsupported or unknown PLI call: $dumpvars\n  initial begin $dumpfile("tb_stack3.vcd"); $dumpvars(0,tb); end\n                                            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/157490365/buildV1.1/tb_stack3_el.v:13: Unsupported: Ignoring delay on this delayed statement.\n  initial begin reset = 1\'b1; #12.5 reset = 1\'b0; end\n                              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/157490365/buildV1.1/tb_stack3_el.v:14: Unsupported: Ignoring delay on this delayed statement.\n  initial clk = 1\'b0; always #5 clk = ~clk;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/157490365/buildV1.1/tb_stack3_el.v:36: Unsupported: Ignoring delay on this delayed statement.\n      begin #10 {push, pop, value_in}=test_vecs[i]; end\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/157490365/buildV1.1/tb_stack3_el.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #4 for(i=0;i<15;i=i+1)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/157490365/buildV1.1/tb_stack3_el.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
  reg clk, reset, push, pop;

  reg [15:0] value_in;
  wire [15:0] value_out;
  reg [17:0] test_vecs [0:(`TESTVECS-1)];

  integer i;
  initial begin $dumpfile("tb_stack3.vcd"); $dumpvars(0,tb); end
  initial begin reset = 1'b1; #12.5 reset = 1'b0; end
  initial clk = 1'b0; always #5 clk = ~clk;
  initial begin
    test_vecs[0][17] = 1'b1; test_vecs[0][16] = 1'b0; test_vecs[0][15:0] = 15'h13;
    test_vecs[1][17] = 1'b1; test_vecs[1][16] = 1'b0; test_vecs[1][15:0] = 15'ha5;
    test_vecs[2][17] = 1'b1; test_vecs[2][16] = 1'b0; test_vecs[2][15:0] = 15'h12;
    test_vecs[3][17] = 1'b1; test_vecs[3][16] = 1'b0; test_vecs[3][15:0] = 15'h14;
    test_vecs[4][17] = 1'b1; test_vecs[4][16] = 1'b0; test_vecs[4][15:0] = 15'ha5;
    test_vecs[5][17] = 1'b1; test_vecs[5][16] = 1'b0; test_vecs[5][15:0] = 15'h13;
    test_vecs[6][17] = 1'b1; test_vecs[6][16] = 1'b0; test_vecs[6][15:0] = 15'ha5;
    test_vecs[7][17] = 1'b1; test_vecs[7][16] = 1'b0; test_vecs[7][15:0] = 15'h12;
    test_vecs[8][17] = 1'b1; test_vecs[8][16] = 1'b0; test_vecs[8][15:0] = 15'h13;
    test_vecs[9][17] = 1'b1; test_vecs[9][16] = 1'b0; test_vecs[9][15:0] = 15'h14;
    test_vecs[10][17] = 1'b1; test_vecs[10][16] = 1'b0; test_vecs[10][15:0] = 15'h13;
    test_vecs[11][17] = 1'b1; test_vecs[11][16] = 1'b0; test_vecs[11][15:0] = 15'ha5;
    test_vecs[12][17] = 1'b0; test_vecs[12][16] = 1'b1; test_vecs[12][15:0] = 15'hxx;
    test_vecs[13][17] = 1'b0; test_vecs[13][16] = 1'b1; test_vecs[13][15:0] = 15'hxx;
    test_vecs[14][17] = 1'b1; test_vecs[14][16] = 1'b0; test_vecs[14][15:0] = 15'h14;
  end
  initial {push, pop, value_in} = 0;
  stack stk_0(clk, reset, push, pop, value_in, value_out);
initial begin
    #4 for(i=0;i<`TESTVECS;i=i+1)
      begin #10 {push, pop, value_in}=test_vecs[i]; end
    #100 $finish;
end
endmodule
module tb;

  reg clk, reset, push, pop;

  reg [15:0] value_in;
  wire [15:0] value_out;
  reg [17:0] test_vecs [0:(`TESTVECS-1)];

  integer i;
  initial begin $dumpfile("tb_stack3.vcd"); $dumpvars(0,tb); end
  initial begin reset = 1'b1; #12.5 reset = 1'b0; end
  initial clk = 1'b0; always #5 clk = ~clk;
  initial begin
    test_vecs[0][17] = 1'b1; test_vecs[0][16] = 1'b0; test_vecs[0][15:0] = 15'h13;
    test_vecs[1][17] = 1'b1; test_vecs[1][16] = 1'b0; test_vecs[1][15:0] = 15'ha5;
    test_vecs[2][17] = 1'b1; test_vecs[2][16] = 1'b0; test_vecs[2][15:0] = 15'h12;
    test_vecs[3][17] = 1'b1; test_vecs[3][16] = 1'b0; test_vecs[3][15:0] = 15'h14;
    test_vecs[4][17] = 1'b1; test_vecs[4][16] = 1'b0; test_vecs[4][15:0] = 15'ha5;
    test_vecs[5][17] = 1'b1; test_vecs[5][16] = 1'b0; test_vecs[5][15:0] = 15'h13;
    test_vecs[6][17] = 1'b1; test_vecs[6][16] = 1'b0; test_vecs[6][15:0] = 15'ha5;
    test_vecs[7][17] = 1'b1; test_vecs[7][16] = 1'b0; test_vecs[7][15:0] = 15'h12;
    test_vecs[8][17] = 1'b1; test_vecs[8][16] = 1'b0; test_vecs[8][15:0] = 15'h13;
    test_vecs[9][17] = 1'b1; test_vecs[9][16] = 1'b0; test_vecs[9][15:0] = 15'h14;
    test_vecs[10][17] = 1'b1; test_vecs[10][16] = 1'b0; test_vecs[10][15:0] = 15'h13;
    test_vecs[11][17] = 1'b1; test_vecs[11][16] = 1'b0; test_vecs[11][15:0] = 15'ha5;
    test_vecs[12][17] = 1'b0; test_vecs[12][16] = 1'b1; test_vecs[12][15:0] = 15'hxx;
    test_vecs[13][17] = 1'b0; test_vecs[13][16] = 1'b1; test_vecs[13][15:0] = 15'hxx;
    test_vecs[14][17] = 1'b1; test_vecs[14][16] = 1'b0; test_vecs[14][15:0] = 15'h14;
  end
  initial {push, pop, value_in} = 0;
  stack stk_0(clk, reset, push, pop, value_in, value_out);
initial begin
    #4 for(i=0;i<`TESTVECS;i=i+1)
      begin #10 {push, pop, value_in}=test_vecs[i]; end
    #100 $finish;
end
endmodule