data/full_repos/permissive/141525667/Source/hdl/clockSynthsizer.v
data/verilator_xmls/22177be7-ef90-4871-9022-84025ec9cfc3.xml
module clockDivider #(parameter frequencySel = 5000)
(
    input clk,
    input rst,

    output reg slowerClock
);

    reg[15:0] counter;
    always@(posedge clk, posedge rst)
    begin
        if(rst == 1'b1)
        begin
            slowerClock <= 1'b0;
            counter <= 16'b0;
        end

        else
        begin
            if(counter == frequencySel)
            begin
                counter <= 16'b0;
                slowerClock <= ~slowerClock;
            end

            else
            begin
                counter <= counter + 1'b1;
            end
        end
    end

endmodule
module clockDivider #(parameter frequencySel = 5000)
(
    input clk,
    input rst,

    output reg slowerClock
);


    reg[15:0] counter;
    always@(posedge clk, posedge rst)
    begin
        if(rst == 1'b1)
        begin
            slowerClock <= 1'b0;
            counter <= 16'b0;
        end

        else
        begin
            if(counter == frequencySel)
            begin
                counter <= 16'b0;
                slowerClock <= ~slowerClock;
            end

            else
            begin
                counter <= counter + 1'b1;
            end
        end
    end

endmodule