data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/Register.v
data/verilator_xmls/5cdd8810-7141-44b6-b895-1c09870425b4.xml
module Register(
clk,en,clr,in,
out
    );
    
        parameter WIDTH = 32;
        input clk;
        input en;
        input clr;
        input  [WIDTH-1:0]in;
        output  reg [WIDTH-1:0]out;
    initial begin
        out = 0;
    end

    always@(posedge clk or posedge clr)begin
        if(clr == 1)
            out <= 0;
        else if(en == 1)
            out <= in;
        else
            ;
    end
endmodule
module Register(
clk,en,clr,in,
out
    );

    
        parameter WIDTH = 32;
        input clk;
        input en;
        input clr;
        input  [WIDTH-1:0]in;
        output  reg [WIDTH-1:0]out;
    initial begin
        out = 0;
    end

    always@(posedge clk or posedge clr)begin
        if(clr == 1)
            out <= 0;
        else if(en == 1)
            out <= in;
        else
            ;
    end
endmodule