data/full_repos/permissive/134057391/cpld/m6502_db/testbench/rs_latch_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/rs_latch_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/rs_latch_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/rs_latch_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/rs_latch_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/rs_latch_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/134057391/cpld/m6502_db/testbench/rs_latch_tb.v:36: Cannot find file containing module: \'rs_latch\'\n rs_latch uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/134057391/cpld/m6502_db/testbench,data/full_repos/permissive/134057391/rs_latch\n             data/full_repos/permissive/134057391/cpld/m6502_db/testbench,data/full_repos/permissive/134057391/rs_latch.v\n             data/full_repos/permissive/134057391/cpld/m6502_db/testbench,data/full_repos/permissive/134057391/rs_latch.sv\n             rs_latch\n             rs_latch.v\n             rs_latch.sv\n             obj_dir/rs_latch\n             obj_dir/rs_latch.v\n             obj_dir/rs_latch.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rs_latch_tb;


	reg s_n;
	reg r_n;


	wire q;
	wire q_n;


	rs_latch uut (
		.s_n(s_n), 
		.r_n(r_n), 
		.q(q), 
		.q_n(q_n)
	);

	initial begin

		s_n = 1;
		r_n = 1;


		#100;
        

      s_n = 0;
		#100;
      s_n = 1;
		#100;
		

      r_n = 0;
		#100;
      r_n = 1;
		#100;
		
	end
      
endmodule
module rs_latch_tb;



	reg s_n;
	reg r_n;


	wire q;
	wire q_n;


	rs_latch uut (
		.s_n(s_n), 
		.r_n(r_n), 
		.q(q), 
		.q_n(q_n)
	);

	initial begin

		s_n = 1;
		r_n = 1;


		#100;
        

      s_n = 0;
		#100;
      s_n = 1;
		#100;
		

      r_n = 0;
		#100;
      r_n = 1;
		#100;
		
	end
      
endmodule