data/full_repos/permissive/155713836/tb/tb_fifos_interface.v
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1: b'%Error: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:37: Unsupported or unknown PLI call: $monitor\n    $monitor ("%g i_mc_sreq_wen:%h o_mc_sreq_fifo_empty:%h o_mc_sreq_fifo_full:%h i_mc_sreq_inbits:%h", \n    ^~~~~~~~\n%Error: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:39: Unsupported or unknown PLI call: $monitor\n    $monitor ("%g i_sc_rreq_ren:%h o_sc_rreq_outbits:%h", \n    ^~~~~~~~\n%Error: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:41: Unsupported or unknown PLI call: $monitor\n    $monitor ("%g i_sc_sresp_wen:%h o_sc_sresp_fifo_empty:%h o_sc_sresp_fifo_full:%h i_sc_sresp_inbits:%h", \n    ^~~~~~~~\n%Error: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:43: Unsupported or unknown PLI call: $monitor\n    $monitor ("%g i_mc_rresp_ren:%h o_mc_rresp_outbits:%h", \n    ^~~~~~~~\n%Error: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:48: syntax error, unexpected \'@\'\n    @ (negedge clk);\n    ^\n%Error: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:53: syntax error, unexpected \'@\'\n      @ (negedge clk);\n      ^\n%Error: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:56: syntax error, unexpected \'@\'\n    @ (negedge clk);\n    ^\n%Error: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:60: syntax error, unexpected \'@\'\n      @ (negedge clk);\n      ^\n%Error: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:64: syntax error, unexpected \'@\'\n    @ (negedge clk);\n    ^\n%Error: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:69: syntax error, unexpected \'@\'\n      @ (negedge clk);\n      ^\n%Error: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:72: syntax error, unexpected \'@\'\n    @ (negedge clk);\n    ^\n%Error: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:76: syntax error, unexpected \'@\'\n      @ (negedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/155713836/tb/tb_fifos_interface.v:84: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = !clk;\n         ^\n%Error: Exiting due to 12 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_fifos_interface ();


  parameter FIFO_DEPTH = 32;
  parameter LOG2_FIFO_DEPTH = 5;
  parameter DATA_LINE_WIDTH = 40;
  parameter CONTROL_LINE_WIDTH = 0;

  reg clk = 0;

  reg i_mc_sreq_wen = 0;
  wire o_mc_sreq_fifo_empty = 0, o_mc_sreq_fifo_full = 0;
  reg [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_mc_sreq_inbits;

  reg i_sc_rreq_ren = 0;
  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] o_sc_rreq_outbits;

  reg i_sc_sresp_wen = 0;
  wire o_sc_sresp_fifo_empty = 0, o_sc_sresp_fifo_full = 0;
  reg [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_sc_sresp_inbits;

  reg i_mc_rresp_ren = 0;
  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] o_mc_rresp_outbits;


  integer i;

  initial begin

    $monitor ("%g i_mc_sreq_wen:%h o_mc_sreq_fifo_empty:%h o_mc_sreq_fifo_full:%h i_mc_sreq_inbits:%h", 
    $time, i_mc_sreq_wen, o_mc_sreq_fifo_empty, o_mc_sreq_fifo_full, i_mc_sreq_inbits);
    $monitor ("%g i_sc_rreq_ren:%h o_sc_rreq_outbits:%h", 
    $time, i_sc_rreq_ren, o_sc_rreq_outbits);
    $monitor ("%g i_sc_sresp_wen:%h o_sc_sresp_fifo_empty:%h o_sc_sresp_fifo_full:%h i_sc_sresp_inbits:%h", 
    $time, i_sc_sresp_wen, o_sc_sresp_fifo_empty, o_sc_sresp_fifo_full, i_sc_sresp_inbits);
    $monitor ("%g i_mc_rresp_ren:%h o_mc_rresp_outbits:%h", 
    $time, i_mc_rresp_ren, o_mc_rresp_outbits);

    clk = 0;

    @ (negedge clk);
    i_mc_sreq_wen = 1;

    for (i = 0 ; i < 70; i = i + 1) begin
      i_mc_sreq_inbits  = i;
      @ (negedge clk);
    end
    i_mc_sreq_wen  = 0;
    @ (negedge clk);
    i_sc_rreq_ren = 1;

    for (i = 0 ; i < 70; i = i + 1) begin
      @ (negedge clk);
    end
    i_sc_rreq_ren = 0;

    @ (negedge clk);
    i_sc_sresp_wen = 1;

    for (i = 70 ; i < 140; i = i + 1) begin
      i_sc_sresp_inbits  = i;
      @ (negedge clk);
    end
    i_sc_sresp_wen = 0;
    @ (negedge clk);
    i_mc_rresp_ren = 1;

    for (i = 70 ; i < 140; i = i + 1) begin
      @ (negedge clk);
    end
    i_mc_rresp_ren = 0;

    #100 $finish;
  end  


  always #1 clk = !clk;


  fifos_interface strawfifo(
    .clk(clk),

    .i_mc_sreq_inbits(i_mc_sreq_inbits),
    .i_mc_sreq_wen(i_mc_sreq_wen),
    .o_mc_sreq_fifo_empty(o_mc_sreq_fifo_empty),
    .o_mc_sreq_fifo_full(o_mc_sreq_fifo_full),
  
    .i_sc_rreq_ren(i_sc_rreq_ren),
    .o_sc_rreq_outbits(o_sc_rreq_outbits),

    .i_sc_sresp_inbits(i_sc_sresp_inbits),
    .i_sc_sresp_wen(i_sc_sresp_wen),
    .o_sc_sresp_fifo_empty(o_sc_sresp_fifo_empty),
    .o_sc_sresp_fifo_full(o_sc_sresp_fifo_full),

    .i_mc_rresp_ren(i_mc_rresp_ren),
    .o_mc_rresp_outbits(o_mc_rresp_outbits)

  );   


  endmodule
module tb_fifos_interface ();



  parameter FIFO_DEPTH = 32;
  parameter LOG2_FIFO_DEPTH = 5;
  parameter DATA_LINE_WIDTH = 40;
  parameter CONTROL_LINE_WIDTH = 0;

  reg clk = 0;

  reg i_mc_sreq_wen = 0;
  wire o_mc_sreq_fifo_empty = 0, o_mc_sreq_fifo_full = 0;
  reg [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_mc_sreq_inbits;

  reg i_sc_rreq_ren = 0;
  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] o_sc_rreq_outbits;

  reg i_sc_sresp_wen = 0;
  wire o_sc_sresp_fifo_empty = 0, o_sc_sresp_fifo_full = 0;
  reg [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_sc_sresp_inbits;

  reg i_mc_rresp_ren = 0;
  wire [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] o_mc_rresp_outbits;


  integer i;

  initial begin

    $monitor ("%g i_mc_sreq_wen:%h o_mc_sreq_fifo_empty:%h o_mc_sreq_fifo_full:%h i_mc_sreq_inbits:%h", 
    $time, i_mc_sreq_wen, o_mc_sreq_fifo_empty, o_mc_sreq_fifo_full, i_mc_sreq_inbits);
    $monitor ("%g i_sc_rreq_ren:%h o_sc_rreq_outbits:%h", 
    $time, i_sc_rreq_ren, o_sc_rreq_outbits);
    $monitor ("%g i_sc_sresp_wen:%h o_sc_sresp_fifo_empty:%h o_sc_sresp_fifo_full:%h i_sc_sresp_inbits:%h", 
    $time, i_sc_sresp_wen, o_sc_sresp_fifo_empty, o_sc_sresp_fifo_full, i_sc_sresp_inbits);
    $monitor ("%g i_mc_rresp_ren:%h o_mc_rresp_outbits:%h", 
    $time, i_mc_rresp_ren, o_mc_rresp_outbits);

    clk = 0;

    @ (negedge clk);
    i_mc_sreq_wen = 1;

    for (i = 0 ; i < 70; i = i + 1) begin
      i_mc_sreq_inbits  = i;
      @ (negedge clk);
    end
    i_mc_sreq_wen  = 0;
    @ (negedge clk);
    i_sc_rreq_ren = 1;

    for (i = 0 ; i < 70; i = i + 1) begin
      @ (negedge clk);
    end
    i_sc_rreq_ren = 0;

    @ (negedge clk);
    i_sc_sresp_wen = 1;

    for (i = 70 ; i < 140; i = i + 1) begin
      i_sc_sresp_inbits  = i;
      @ (negedge clk);
    end
    i_sc_sresp_wen = 0;
    @ (negedge clk);
    i_mc_rresp_ren = 1;

    for (i = 70 ; i < 140; i = i + 1) begin
      @ (negedge clk);
    end
    i_mc_rresp_ren = 0;

    #100 $finish;
  end  


  always #1 clk = !clk;


  fifos_interface strawfifo(
    .clk(clk),

    .i_mc_sreq_inbits(i_mc_sreq_inbits),
    .i_mc_sreq_wen(i_mc_sreq_wen),
    .o_mc_sreq_fifo_empty(o_mc_sreq_fifo_empty),
    .o_mc_sreq_fifo_full(o_mc_sreq_fifo_full),
  
    .i_sc_rreq_ren(i_sc_rreq_ren),
    .o_sc_rreq_outbits(o_sc_rreq_outbits),

    .i_sc_sresp_inbits(i_sc_sresp_inbits),
    .i_sc_sresp_wen(i_sc_sresp_wen),
    .o_sc_sresp_fifo_empty(o_sc_sresp_fifo_empty),
    .o_sc_sresp_fifo_full(o_sc_sresp_fifo_full),

    .i_mc_rresp_ren(i_mc_rresp_ren),
    .o_mc_rresp_outbits(o_mc_rresp_outbits)

  );   


  endmodule