data/full_repos/permissive/164484080/rtl/intercon.v
1: b'%Error: data/full_repos/permissive/164484080/rtl/intercon.v:22: Cannot find include file: wishbone.v\n`include "wishbone.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/164484080/rtl,data/full_repos/permissive/164484080/wishbone.v\n             data/full_repos/permissive/164484080/rtl,data/full_repos/permissive/164484080/wishbone.v.v\n             data/full_repos/permissive/164484080/rtl,data/full_repos/permissive/164484080/wishbone.v.sv\n             wishbone.v\n             wishbone.v.v\n             wishbone.v.sv\n             obj_dir/wishbone.v\n             obj_dir/wishbone.v.v\n             obj_dir/wishbone.v.sv\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:37: Define or directive not defined: \'`ADR_WIDTH\'\n    input wire [MASTERS_NUM*`ADR_WIDTH-1:0] m2i_adr_i,\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:38: Define or directive not defined: \'`DAT_WIDTH\'\n    input wire [MASTERS_NUM*`DAT_WIDTH-1:0] m2i_dat_i,\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:39: Define or directive not defined: \'`SEL_WIDTH\'\n    input wire [MASTERS_NUM*`SEL_WIDTH-1:0] m2i_sel_i,\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:46: Define or directive not defined: \'`DAT_WIDTH\'\n    output wire [`DAT_WIDTH-1:0] i2m_dat_o,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:52: Define or directive not defined: \'`DAT_WIDTH\'\n    input wire [SLAVES_NUM*`DAT_WIDTH-1:0] s2i_dat_i,\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:60: Define or directive not defined: \'`ADR_WIDTH\'\n    output wire [`ADR_WIDTH-1:0] i2s_adr_o,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:61: Define or directive not defined: \'`DAT_WIDTH\'\n    output wire [`DAT_WIDTH-1:0] i2s_dat_o,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:62: Define or directive not defined: \'`SEL_WIDTH\'\n    output wire [`SEL_WIDTH-1:0] i2s_sel_o,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:73: Define or directive not defined: \'`ADR_WIDTH\'\n    wire [`ADR_WIDTH-1:0] granted_masters_adr_i = m2i_adr_i[`ADR_WIDTH*grant+:`ADR_WIDTH];\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:73: Define or directive not defined: \'`ADR_WIDTH\'\n    wire [`ADR_WIDTH-1:0] granted_masters_adr_i = m2i_adr_i[`ADR_WIDTH*grant+:`ADR_WIDTH];\n                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:73: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n    wire [`ADR_WIDTH-1:0] granted_masters_adr_i = m2i_adr_i[`ADR_WIDTH*grant+:`ADR_WIDTH];\n                                                                      ^\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:73: Define or directive not defined: \'`ADR_WIDTH\'\n    wire [`ADR_WIDTH-1:0] granted_masters_adr_i = m2i_adr_i[`ADR_WIDTH*grant+:`ADR_WIDTH];\n                                                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:79: Define or directive not defined: \'`ADR_WIDTH\'\n    assign i2s_adr_o = m2i_adr_i[`ADR_WIDTH*grant+:`ADR_WIDTH] & 12\'hfff;\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:79: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n    assign i2s_adr_o = m2i_adr_i[`ADR_WIDTH*grant+:`ADR_WIDTH] & 12\'hfff;\n                                           ^\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:79: Define or directive not defined: \'`ADR_WIDTH\'\n    assign i2s_adr_o = m2i_adr_i[`ADR_WIDTH*grant+:`ADR_WIDTH] & 12\'hfff;\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:80: Define or directive not defined: \'`DAT_WIDTH\'\n    assign i2s_dat_o = m2i_dat_i[`DAT_WIDTH*grant+:`DAT_WIDTH];\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:80: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n    assign i2s_dat_o = m2i_dat_i[`DAT_WIDTH*grant+:`DAT_WIDTH];\n                                           ^\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:80: Define or directive not defined: \'`DAT_WIDTH\'\n    assign i2s_dat_o = m2i_dat_i[`DAT_WIDTH*grant+:`DAT_WIDTH];\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:81: Define or directive not defined: \'`SEL_WIDTH\'\n    assign i2s_sel_o = m2i_sel_i[`SEL_WIDTH*grant+:`SEL_WIDTH];\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:81: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n    assign i2s_sel_o = m2i_sel_i[`SEL_WIDTH*grant+:`SEL_WIDTH];\n                                           ^\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:81: Define or directive not defined: \'`SEL_WIDTH\'\n    assign i2s_sel_o = m2i_sel_i[`SEL_WIDTH*grant+:`SEL_WIDTH];\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:88: Define or directive not defined: \'`DAT_WIDTH\'\n    assign i2m_dat_o = s2i_dat_i[`DAT_WIDTH*selected_slave+:`DAT_WIDTH];\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:88: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n    assign i2m_dat_o = s2i_dat_i[`DAT_WIDTH*selected_slave+:`DAT_WIDTH];\n                                           ^\n%Error: data/full_repos/permissive/164484080/rtl/intercon.v:88: Define or directive not defined: \'`DAT_WIDTH\'\n    assign i2m_dat_o = s2i_dat_i[`DAT_WIDTH*selected_slave+:`DAT_WIDTH];\n                                                            ^~~~~~~~~~\n%Error: Exiting due to 25 error(s)\n'
module intercon (
    input wire rst_i,
    input wire clk_i,




    input wire [MASTERS_NUM-1:0] m2i_cyc_i,
    input wire [MASTERS_NUM-1:0] m2i_stb_i,
    input wire [MASTERS_NUM-1:0] m2i_we_i,
    input wire [MASTERS_NUM*`ADR_WIDTH-1:0] m2i_adr_i,
    input wire [MASTERS_NUM*`DAT_WIDTH-1:0] m2i_dat_i,
    input wire [MASTERS_NUM*`SEL_WIDTH-1:0] m2i_sel_i,



    output wire [MASTERS_NUM-1:0] i2m_ack_o,
    output wire [MASTERS_NUM-1:0] i2m_err_o,

    output wire [`DAT_WIDTH-1:0] i2m_dat_o,



    input wire [SLAVES_NUM-1:0] s2i_ack_i,
    input wire [SLAVES_NUM-1:0] s2i_err_i,
    input wire [SLAVES_NUM*`DAT_WIDTH-1:0] s2i_dat_i,




    output wire [SLAVES_NUM-1:0] i2s_stb_o,

    output wire i2s_cyc_o,
    output wire [`ADR_WIDTH-1:0] i2s_adr_o,
    output wire [`DAT_WIDTH-1:0] i2s_dat_o,
    output wire [`SEL_WIDTH-1:0] i2s_sel_o,
    output wire i2s_we_o
);

    parameter MASTERS_NUM = 2;
    parameter SLAVES_NUM = 2;

    reg [0:0] state = `STATE_WAIT_FOR_BUS_CLAIM;
    reg [$clog2(MASTERS_NUM)-1:0] grant = 0;

    reg [$clog2(SLAVES_NUM)-1:0] selected_slave;
    wire [`ADR_WIDTH-1:0] granted_masters_adr_i = m2i_adr_i[`ADR_WIDTH*grant+:`ADR_WIDTH];


    assign i2s_stb_o = m2i_stb_i[grant] << selected_slave;

    assign i2s_cyc_o = {SLAVES_NUM{m2i_cyc_i[grant]}};
    assign i2s_adr_o = m2i_adr_i[`ADR_WIDTH*grant+:`ADR_WIDTH] & 12'hfff;
    assign i2s_dat_o = m2i_dat_i[`DAT_WIDTH*grant+:`DAT_WIDTH];
    assign i2s_sel_o = m2i_sel_i[`SEL_WIDTH*grant+:`SEL_WIDTH];
    assign i2s_we_o = m2i_we_i[grant];


    assign i2m_ack_o = s2i_ack_i[selected_slave] << grant;
    assign i2m_err_o = s2i_err_i[selected_slave] << grant;

    assign i2m_dat_o = s2i_dat_i[`DAT_WIDTH*selected_slave+:`DAT_WIDTH];

    reg [7:0] n, i;
    reg found_next_master;

    always @* begin
        if (rst_i) begin
            selected_slave <= 0;
        end else begin
            if (granted_masters_adr_i >= 64'h0000800000000000 &&
                granted_masters_adr_i <  64'h0000800000000400)

                selected_slave <= 1;
            else
            if (granted_masters_adr_i >= 64'h0000800080000000 &&
                granted_masters_adr_i <  64'h0000800080000400)

                selected_slave <= 3;
            else
            if (granted_masters_adr_i >= 64'h0000800100000000 &&
                granted_masters_adr_i <  64'h0000800100400000)

                selected_slave <= 2;
            else
            if (granted_masters_adr_i >= 64'h0000801000000000 &&
                granted_masters_adr_i <  64'h0000801000000400)

                selected_slave <= 0;
            else
                selected_slave <= 0;
        end
    end

    always @(posedge clk_i) begin
        if (rst_i) begin
            state <= `STATE_WAIT_FOR_BUS_CLAIM;
            grant <= 0;
        end else begin
            case (state)
                `STATE_WAIT_FOR_BUS_CLAIM: begin

                    if (|m2i_cyc_i) begin
                        found_next_master = 0;

                        i = grant;
                        for (n = 0; n < MASTERS_NUM && !found_next_master; n = n + 1) begin
                            if (m2i_cyc_i[i]) begin
                                found_next_master = 1;
                                state <= `STATE_WAIT_FOR_CYCLE_END;
                                grant <= i;
                            end

                            i = (i + 1) % MASTERS_NUM;
                        end
                    end
                end
                `STATE_WAIT_FOR_CYCLE_END: begin
                    if (~m2i_cyc_i[grant]) begin
                        state <= `STATE_WAIT_FOR_BUS_CLAIM;
                        grant <= (grant + 1) % MASTERS_NUM;
                    end
                end
            endcase
        end
    end

endmodule
module intercon (
    input wire rst_i,
    input wire clk_i,




    input wire [MASTERS_NUM-1:0] m2i_cyc_i,
    input wire [MASTERS_NUM-1:0] m2i_stb_i,
    input wire [MASTERS_NUM-1:0] m2i_we_i,
    input wire [MASTERS_NUM*`ADR_WIDTH-1:0] m2i_adr_i,
    input wire [MASTERS_NUM*`DAT_WIDTH-1:0] m2i_dat_i,
    input wire [MASTERS_NUM*`SEL_WIDTH-1:0] m2i_sel_i,



    output wire [MASTERS_NUM-1:0] i2m_ack_o,
    output wire [MASTERS_NUM-1:0] i2m_err_o,

    output wire [`DAT_WIDTH-1:0] i2m_dat_o,



    input wire [SLAVES_NUM-1:0] s2i_ack_i,
    input wire [SLAVES_NUM-1:0] s2i_err_i,
    input wire [SLAVES_NUM*`DAT_WIDTH-1:0] s2i_dat_i,




    output wire [SLAVES_NUM-1:0] i2s_stb_o,

    output wire i2s_cyc_o,
    output wire [`ADR_WIDTH-1:0] i2s_adr_o,
    output wire [`DAT_WIDTH-1:0] i2s_dat_o,
    output wire [`SEL_WIDTH-1:0] i2s_sel_o,
    output wire i2s_we_o
);


    parameter MASTERS_NUM = 2;
    parameter SLAVES_NUM = 2;

    reg [0:0] state = `STATE_WAIT_FOR_BUS_CLAIM;
    reg [$clog2(MASTERS_NUM)-1:0] grant = 0;

    reg [$clog2(SLAVES_NUM)-1:0] selected_slave;
    wire [`ADR_WIDTH-1:0] granted_masters_adr_i = m2i_adr_i[`ADR_WIDTH*grant+:`ADR_WIDTH];


    assign i2s_stb_o = m2i_stb_i[grant] << selected_slave;

    assign i2s_cyc_o = {SLAVES_NUM{m2i_cyc_i[grant]}};
    assign i2s_adr_o = m2i_adr_i[`ADR_WIDTH*grant+:`ADR_WIDTH] & 12'hfff;
    assign i2s_dat_o = m2i_dat_i[`DAT_WIDTH*grant+:`DAT_WIDTH];
    assign i2s_sel_o = m2i_sel_i[`SEL_WIDTH*grant+:`SEL_WIDTH];
    assign i2s_we_o = m2i_we_i[grant];


    assign i2m_ack_o = s2i_ack_i[selected_slave] << grant;
    assign i2m_err_o = s2i_err_i[selected_slave] << grant;

    assign i2m_dat_o = s2i_dat_i[`DAT_WIDTH*selected_slave+:`DAT_WIDTH];

    reg [7:0] n, i;
    reg found_next_master;

    always @* begin
        if (rst_i) begin
            selected_slave <= 0;
        end else begin
            if (granted_masters_adr_i >= 64'h0000800000000000 &&
                granted_masters_adr_i <  64'h0000800000000400)

                selected_slave <= 1;
            else
            if (granted_masters_adr_i >= 64'h0000800080000000 &&
                granted_masters_adr_i <  64'h0000800080000400)

                selected_slave <= 3;
            else
            if (granted_masters_adr_i >= 64'h0000800100000000 &&
                granted_masters_adr_i <  64'h0000800100400000)

                selected_slave <= 2;
            else
            if (granted_masters_adr_i >= 64'h0000801000000000 &&
                granted_masters_adr_i <  64'h0000801000000400)

                selected_slave <= 0;
            else
                selected_slave <= 0;
        end
    end

    always @(posedge clk_i) begin
        if (rst_i) begin
            state <= `STATE_WAIT_FOR_BUS_CLAIM;
            grant <= 0;
        end else begin
            case (state)
                `STATE_WAIT_FOR_BUS_CLAIM: begin

                    if (|m2i_cyc_i) begin
                        found_next_master = 0;

                        i = grant;
                        for (n = 0; n < MASTERS_NUM && !found_next_master; n = n + 1) begin
                            if (m2i_cyc_i[i]) begin
                                found_next_master = 1;
                                state <= `STATE_WAIT_FOR_CYCLE_END;
                                grant <= i;
                            end

                            i = (i + 1) % MASTERS_NUM;
                        end
                    end
                end
                `STATE_WAIT_FOR_CYCLE_END: begin
                    if (~m2i_cyc_i[grant]) begin
                        state <= `STATE_WAIT_FOR_BUS_CLAIM;
                        grant <= (grant + 1) % MASTERS_NUM;
                    end
                end
            endcase
        end
    end

endmodule