data/full_repos/permissive/199399537/sdram_top.v
1: b"%Error: data/full_repos/permissive/199399537/sdram_top.v:83: Cannot find file containing module: 'sdram_ctrl'\nsdram_ctrl  module_001(   \n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/sdram_ctrl\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/sdram_ctrl.v\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/sdram_ctrl.sv\n             sdram_ctrl\n             sdram_ctrl.v\n             sdram_ctrl.sv\n             obj_dir/sdram_ctrl\n             obj_dir/sdram_ctrl.v\n             obj_dir/sdram_ctrl.sv\n%Error: data/full_repos/permissive/199399537/sdram_top.v:95: Cannot find file containing module: 'sdram_cmd'\nsdram_cmd  module_002(   \n^~~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_top.v:110: Cannot find file containing module: 'sdram_wr_data'\nsdram_wr_data module_003(   \n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module sdram_top(
				clk,
				rst_n,
				
				sdram_wr_req,
				sdram_rd_req,
				
				sdram_wr_ack,
				sdram_rd_ack,
				
				sys_addr,
				sys_data_in,
				sys_data_out,

				sdram_cke,
				sdram_cs_n,
				sdram_ras_n,
				sdram_cas_n,
				sdram_we_n,
				
				sdram_ba,
				sdram_addr,
				sdram_data,
				sdram_udqm,
				sdram_ldqm
			);

input clk;
input rst_n;


input sdram_wr_req;
input sdram_rd_req;

output sdram_wr_ack;
output sdram_rd_ack;

input[21:0] 		sys_addr;
input[15:0] 		sys_data_in;
output[15:0] 	sys_data_out;



output sdram_cke;
output sdram_cs_n;
output sdram_ras_n;
output sdram_cas_n;
output sdram_we_n;
output[1:0] sdram_ba;
output[12:0] sdram_addr;
output sdram_udqm;
output sdram_ldqm;
inout[15:0] sdram_data;


wire[4:0] init_state;
wire[3:0] work_state;
wire[8:0] cnt_clk;

reg dqm;
always @ (posedge clk or negedge rst_n )
	if(!rst_n)
			dqm<=1'b1;
	else
			dqm<=1'b0;

assign 		sdram_udqm=dqm;
assign 		sdram_ldqm=	dqm;

sdram_ctrl		module_001(
									.clk(clk),						
									.rst_n(rst_n),												
									.sdram_wr_req(sdram_wr_req),
									.sdram_rd_req(sdram_rd_req),
									.sdram_wr_ack(sdram_wr_ack),
									.sdram_rd_ack(sdram_rd_ack),						
									.init_state(init_state),
									.work_state(work_state),
									.cnt_clk(cnt_clk)
								);

sdram_cmd		module_002(
									.clk(clk),
									.rst_n(rst_n),
									.sdram_cke(sdram_cke),		
									.sdram_cs_n(sdram_cs_n),	
									.sdram_ras_n(sdram_ras_n),	
									.sdram_cas_n(sdram_cas_n),	
									.sdram_we_n(sdram_we_n),	
									.sdram_ba(sdram_ba),			
									.sdram_addr(sdram_addr),									
									.sys_addr(sys_addr),			
									.init_state(init_state),	
									.work_state(work_state)
								);

sdram_wr_data	module_003(
									.clk(clk),
									.rst_n(rst_n),
									.sdram_data(sdram_data),
									.sys_data_in(sys_data_in),
									.sys_data_out(sys_data_out),
									.work_state(work_state),
									.cnt_clk(cnt_clk)
								);


endmodule
module sdram_top(
				clk,
				rst_n,
				
				sdram_wr_req,
				sdram_rd_req,
				
				sdram_wr_ack,
				sdram_rd_ack,
				
				sys_addr,
				sys_data_in,
				sys_data_out,

				sdram_cke,
				sdram_cs_n,
				sdram_ras_n,
				sdram_cas_n,
				sdram_we_n,
				
				sdram_ba,
				sdram_addr,
				sdram_data,
				sdram_udqm,
				sdram_ldqm
			);


input clk;
input rst_n;


input sdram_wr_req;
input sdram_rd_req;

output sdram_wr_ack;
output sdram_rd_ack;

input[21:0] 		sys_addr;
input[15:0] 		sys_data_in;
output[15:0] 	sys_data_out;



output sdram_cke;
output sdram_cs_n;
output sdram_ras_n;
output sdram_cas_n;
output sdram_we_n;
output[1:0] sdram_ba;
output[12:0] sdram_addr;
output sdram_udqm;
output sdram_ldqm;
inout[15:0] sdram_data;


wire[4:0] init_state;
wire[3:0] work_state;
wire[8:0] cnt_clk;

reg dqm;
always @ (posedge clk or negedge rst_n )
	if(!rst_n)
			dqm<=1'b1;
	else
			dqm<=1'b0;

assign 		sdram_udqm=dqm;
assign 		sdram_ldqm=	dqm;

sdram_ctrl		module_001(
									.clk(clk),						
									.rst_n(rst_n),												
									.sdram_wr_req(sdram_wr_req),
									.sdram_rd_req(sdram_rd_req),
									.sdram_wr_ack(sdram_wr_ack),
									.sdram_rd_ack(sdram_rd_ack),						
									.init_state(init_state),
									.work_state(work_state),
									.cnt_clk(cnt_clk)
								);

sdram_cmd		module_002(
									.clk(clk),
									.rst_n(rst_n),
									.sdram_cke(sdram_cke),		
									.sdram_cs_n(sdram_cs_n),	
									.sdram_ras_n(sdram_ras_n),	
									.sdram_cas_n(sdram_cas_n),	
									.sdram_we_n(sdram_we_n),	
									.sdram_ba(sdram_ba),			
									.sdram_addr(sdram_addr),									
									.sys_addr(sys_addr),			
									.init_state(init_state),	
									.work_state(work_state)
								);

sdram_wr_data	module_003(
									.clk(clk),
									.rst_n(rst_n),
									.sdram_data(sdram_data),
									.sys_data_in(sys_data_in),
									.sys_data_out(sys_data_out),
									.work_state(work_state),
									.cnt_clk(cnt_clk)
								);


endmodule