data/full_repos/permissive/209997170/Sound/sound_ref/source/blinker.v
data/verilator_xmls/88fa54bf-ded7-4a69-af5c-e32a1de54e4a.xml
module blinker(
  input clk,
  input rst,
  output blink
    );


reg [24:0] counter_q, counter_d;


reg dir;


assign blink = counter_d[24];


always@(counter_q) begin
    if (dir) begin
	     counter_d = counter_q - 1'b1;
    end else begin
	     counter_d = counter_q + 1'b1;
	 end
end


always@(posedge clk) begin
   if (rst) begin
	   counter_q <= 25'b0;
		dir <= 1'b0;
	end else begin
	    counter_q <= counter_d;
	end
end

endmodule
module blinker(
  input clk,
  input rst,
  output blink
    );



reg [24:0] counter_q, counter_d;


reg dir;


assign blink = counter_d[24];


always@(counter_q) begin
    if (dir) begin
	     counter_d = counter_q - 1'b1;
    end else begin
	     counter_d = counter_q + 1'b1;
	 end
end


always@(posedge clk) begin
   if (rst) begin
	   counter_q <= 25'b0;
		dir <= 1'b0;
	end else begin
	    counter_q <= counter_d;
	end
end

endmodule