data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v:37: Little bit endian vector: MSB < LSB of bit range: 0:9\n  input [0:9] waddr,\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v:38: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input [0:7] data_in,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v:41: Little bit endian vector: MSB < LSB of bit range: 0:9\n  input [0:9] raddr,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v:42: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output [0:7] data_out );\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v:44: Little bit endian vector: MSB < LSB of bit range: 0:7\n  reg[0:7] ram[0:1023];\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v:45: Little bit endian vector: MSB < LSB of bit range: 0:7\n  reg[0:7] internal;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v:11: Little bit endian vector: MSB < LSB of bit range: 0:9\n  input[0:9] waddr,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v:12: Little bit endian vector: MSB < LSB of bit range: 0:9\n  input[0:9] raddr,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v:13: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input[0:7] data_in,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/137416811/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v:14: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output[0:7] data_out );\n        ^\n%Error: Exiting due to 10 warning(s)\n'
module dpram_1024x8_core (
  input wclk,
  input wen,
  input [0:9] waddr,
  input [0:7] data_in,
  input rclk,
  input ren,
  input [0:9] raddr,
  output [0:7] data_out );

  reg[0:7] ram[0:1023];
  reg[0:7] internal;

  assign data_out = internal;

  always @(posedge wclk) begin
    if(wen) begin
      ram[waddr] <= data_in;
    end
  end

  always @(posedge rclk) begin
    if(ren) begin
      internal <= ram[raddr];
    end
  end

endmodule
module dpram_1024x8_core (
  input wclk,
  input wen,
  input [0:9] waddr,
  input [0:7] data_in,
  input rclk,
  input ren,
  input [0:9] raddr,
  output [0:7] data_out );


  reg[0:7] ram[0:1023];
  reg[0:7] internal;

  assign data_out = internal;

  always @(posedge wclk) begin
    if(wen) begin
      ram[waddr] <= data_in;
    end
  end

  always @(posedge rclk) begin
    if(ren) begin
      internal <= ram[raddr];
    end
  end

endmodule