data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/单周期CPU代码/dataPipe.v
'utf-8' codec can't decode byte 0xd6 in position 66: invalid continuation byte
1: b"%Error-ASSIGNIN: data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/\xe5\x8d\x95\xe5\x91\xa8\xe6\x9c\x9fCPU\xe4\xbb\xa3\xe7\xa0\x81/dataPipe.v:50: Assigning to input/const variable: 'rs'\n      assign rs = IDataOut[25:21]; \n             ^~\n%Error-ASSIGNIN: data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/\xe5\x8d\x95\xe5\x91\xa8\xe6\x9c\x9fCPU\xe4\xbb\xa3\xe7\xa0\x81/dataPipe.v:52: Assigning to input/const variable: 'rt'\n   assign rt = IDataOut[20:16];\n          ^~\n%Error-ASSIGNIN: data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/\xe5\x8d\x95\xe5\x91\xa8\xe6\x9c\x9fCPU\xe4\xbb\xa3\xe7\xa0\x81/dataPipe.v:54: Assigning to input/const variable: 'rd'\n   assign rd = IDataOut[15:11];\n          ^~\n%Error-ASSIGNIN: data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/\xe5\x8d\x95\xe5\x91\xa8\xe6\x9c\x9fCPU\xe4\xbb\xa3\xe7\xa0\x81/dataPipe.v:57: Assigning to input/const variable: 'sa'\n   assign sa = {{26{1'b0}},IDataOut[10:6]};\n          ^~\n%Error-ASSIGNIN: data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/\xe5\x8d\x95\xe5\x91\xa8\xe6\x9c\x9fCPU\xe4\xbb\xa3\xe7\xa0\x81/dataPipe.v:59: Assigning to input/const variable: 'opcode'\n   assign opcode = IDataOut[31:26];\n          ^~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/\xe5\x8d\x95\xe5\x91\xa8\xe6\x9c\x9fCPU\xe4\xbb\xa3\xe7\xa0\x81/dataPipe.v:63: Assigning to input/const variable: 'toExtendAddress'\n   assign toExtendAddress = IDataOut[25:0];\n          ^~~~~~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/\xe5\x8d\x95\xe5\x91\xa8\xe6\x9c\x9fCPU\xe4\xbb\xa3\xe7\xa0\x81/dataPipe.v:65: Assigning to input/const variable: 'immediate'\n   assign immediate = IDataOut[15:0];\n          ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module DataPipe(
	    clk,
		 reset,
	     zero,
		 CurrentAddress,
		 NextAddress,
		 ALUOp,
		 ReadData1,
         ReadData2,
         dataA,
         dataB,
		 ALUResult,
	     IDataOut,
	     DataOut,
	     WriteData,
	     rs,        
	     rt,
	     rd,
	     sa,
	     opcode,
	     PCSrc,
         PCPlusFourAddress,
         immediate,
         ExtendResult,
         toExtendAddress,
         JumpAddress,
         WriteReg
);  
        input clk, reset, zero;
		output [31:0] DataOut;
		output [31:0] NextAddress;
	    input wire [4:0] WriteReg;
		output [2:0] ALUOp;
        wire mRD, mWR;
        output [1:0] PCSrc;
	    wire InsMemRW;    
		output wire[31:0] IDataOut;  
		output wire [31:0] WriteData;
		

		wire ExtSel, PCWre,  RegDst, RegWre, ALUSrcA, ALUSrcB, DBDataSrc;
        output wire[31:0] ReadData1;
        output wire[31:0] ReadData2;
        output wire[31:0] CurrentAddress;
        output wire[31:0] ALUResult;
         output wire[31:0] ExtendResult;

	     input wire[4:0] rs;
	     assign rs = IDataOut[25:21]; 
		 input wire[4:0] rt;
		 assign rt = IDataOut[20:16];
		 input wire[4:0] rd;
		 assign rd = IDataOut[15:11];

		 input wire[31:0] sa;
		 assign sa = {{26{1'b0}},IDataOut[10:6]};
		 input wire[5:0] opcode;
		 assign opcode = IDataOut[31:26];
		 wire[15:0] toSignZeroExtend;
		 assign toSignZeroExtend = IDataOut[15:0];
		 input wire[25:0]toExtendAddress;
		 assign toExtendAddress = IDataOut[25:0];
		 input wire[15:0] immediate;
		 assign immediate = IDataOut[15:0];
         input wire[31:0] dataA, dataB;


                

	PC _PC(clk, reset, NextAddress, CurrentAddress, PCWre);



	ROM _ROM(InsMemRW, CurrentAddress, IDataOut);


	controlUnit _controlUnit(opcode, zero, ExtSel, PCWre, InsMemRW, RegDst,RegWre, ALUOp, PCSrc, ALUSrcA, ALUSrcB, mRD, mWR, DBDataSrc);


	selector5 _selector5(RegDst, rt, rd, WriteReg);


	RegFile  _RegFile(clk, reset, RegWre, rs, rt, WriteReg, WriteData, ReadData1, ReadData2);


   RAM _RAM(clk, ALUResult, ReadData2, mRD, mWR, DataOut);


	SignZeroExtend _SignZeroExtend(ExtSel, immediate, ExtendResult);


	selector32 _selector32_A(ALUSrcA, ReadData1, sa, dataA);
	selector32 _selector32_B(ALUSrcB, ReadData2, ExtendResult, dataB);
    selector32 _selector32_DB(DBDataSrc, ALUResult, DataOut, WriteData);

	ALU32 _ALU32(ALUOp, dataA, dataB, ALUResult, zero);
	
    input wire[31:0] PCPlusFourAddress;

	PCplus4 _PCplus4(CurrentAddress, PCPlusFourAddress);
	
	input wire[31:0] JumpAddress;

	extendAddress _extendAddress(toExtendAddress,PCPlusFourAddress,JumpAddress);
	

	selector3to1 _selector3to1(PCPlusFourAddress, ExtendResult, JumpAddress, PCSrc, NextAddress);
	
endmodule
module DataPipe(
	    clk,
		 reset,
	     zero,
		 CurrentAddress,
		 NextAddress,
		 ALUOp,
		 ReadData1,
         ReadData2,
         dataA,
         dataB,
		 ALUResult,
	     IDataOut,
	     DataOut,
	     WriteData,
	     rs,        
	     rt,
	     rd,
	     sa,
	     opcode,
	     PCSrc,
         PCPlusFourAddress,
         immediate,
         ExtendResult,
         toExtendAddress,
         JumpAddress,
         WriteReg
);
  
        input clk, reset, zero;
		output [31:0] DataOut;
		output [31:0] NextAddress;
	    input wire [4:0] WriteReg;
		output [2:0] ALUOp;
        wire mRD, mWR;
        output [1:0] PCSrc;
	    wire InsMemRW;    
		output wire[31:0] IDataOut;  
		output wire [31:0] WriteData;
		

		wire ExtSel, PCWre,  RegDst, RegWre, ALUSrcA, ALUSrcB, DBDataSrc;
        output wire[31:0] ReadData1;
        output wire[31:0] ReadData2;
        output wire[31:0] CurrentAddress;
        output wire[31:0] ALUResult;
         output wire[31:0] ExtendResult;

	     input wire[4:0] rs;
	     assign rs = IDataOut[25:21]; 
		 input wire[4:0] rt;
		 assign rt = IDataOut[20:16];
		 input wire[4:0] rd;
		 assign rd = IDataOut[15:11];

		 input wire[31:0] sa;
		 assign sa = {{26{1'b0}},IDataOut[10:6]};
		 input wire[5:0] opcode;
		 assign opcode = IDataOut[31:26];
		 wire[15:0] toSignZeroExtend;
		 assign toSignZeroExtend = IDataOut[15:0];
		 input wire[25:0]toExtendAddress;
		 assign toExtendAddress = IDataOut[25:0];
		 input wire[15:0] immediate;
		 assign immediate = IDataOut[15:0];
         input wire[31:0] dataA, dataB;


                

	PC _PC(clk, reset, NextAddress, CurrentAddress, PCWre);



	ROM _ROM(InsMemRW, CurrentAddress, IDataOut);


	controlUnit _controlUnit(opcode, zero, ExtSel, PCWre, InsMemRW, RegDst,RegWre, ALUOp, PCSrc, ALUSrcA, ALUSrcB, mRD, mWR, DBDataSrc);


	selector5 _selector5(RegDst, rt, rd, WriteReg);


	RegFile  _RegFile(clk, reset, RegWre, rs, rt, WriteReg, WriteData, ReadData1, ReadData2);


   RAM _RAM(clk, ALUResult, ReadData2, mRD, mWR, DataOut);


	SignZeroExtend _SignZeroExtend(ExtSel, immediate, ExtendResult);


	selector32 _selector32_A(ALUSrcA, ReadData1, sa, dataA);
	selector32 _selector32_B(ALUSrcB, ReadData2, ExtendResult, dataB);
    selector32 _selector32_DB(DBDataSrc, ALUResult, DataOut, WriteData);

	ALU32 _ALU32(ALUOp, dataA, dataB, ALUResult, zero);
	
    input wire[31:0] PCPlusFourAddress;

	PCplus4 _PCplus4(CurrentAddress, PCPlusFourAddress);
	
	input wire[31:0] JumpAddress;

	extendAddress _extendAddress(toExtendAddress,PCPlusFourAddress,JumpAddress);
	

	selector3to1 _selector3to1(PCPlusFourAddress, ExtendResult, JumpAddress, PCSrc, NextAddress);
	
endmodule