data/full_repos/permissive/121803953/Lab2/lab2.v
data/verilator_xmls/d30f6656-4afb-4621-883b-a3d78d745bea.xml
module part1(a, b, c, d, X);
    input a, b, c, d;
    output X;
    supply1 X;
endmodule
module part1(a, b, c, d, X);

    input a, b, c, d;
    output X;
    supply1 X;
endmodule