data/full_repos/permissive/142990562/FPGA Ethernet Mac.py/Verilog/Top.v
 line:39: before: ","
1: b'%Error: Cannot find file containing module: Ethernet\n        ... Looked in:\n             data/full_repos/permissive/142990562/FPGA/Ethernet\n             data/full_repos/permissive/142990562/FPGA/Ethernet.v\n             data/full_repos/permissive/142990562/FPGA/Ethernet.sv\n             Ethernet\n             Ethernet.v\n             Ethernet.sv\n             obj_dir/Ethernet\n             obj_dir/Ethernet.v\n             obj_dir/Ethernet.sv\n%Error: Cannot find file containing module: Mac.py/Verilog,data/full_repos/permissive/142990562\n%Error: Cannot find file containing module: data/full_repos/permissive/142990562/FPGA\n%Error: Cannot find file containing module: Mac.py/Verilog/Top.v\n%Error: Exiting due to 4 error(s)\n'
module Top(
  input               sys_clk,
  output			        vga_hs,
  output			        vga_vs,
  output  [4:0]	      vga_r,
  output	[5:0]	      vga_g,
  output	[4:0] 	    vga_b,
  input               key1,
  input               key2,
  input               key3,
  input               key4,
  
  output              e_reset,


  input	               e_rxc,
	input	               e_rxdv,
	input	               e_rxer,
	input      [7:0]     e_rxd,

	input	               e_txc,
	output               e_gtxc,
	output               e_txen,
	output               e_txer,
	output     [7:0]     e_txd
  
  
  );
  wire [11:0] X_5,Y,Width,Height;
  wire [7 :0] R,G,B,RO,GO,BO;  
  
  assign e_gtxc = e_rxc;	 
  assign e_reset = 1'b1; 
  
  assign vga_r = RO[7:3],
         vga_g = GO[7:2],
         vga_b = BO[7:3];
  
  assign SendEn = !key3Reg[1] && key3Reg[2];  
  assign ClearMac = !key1Reg[1] && key1Reg[2]; 
  
  wire  CLK_VGA = CLK_107;
  
  wire [10:0] Ram_MacText_addr;
  wire [8 :0] Ram_MacText_din; 
  wire [23:0] TxCNT,RxCNT,TxLimit;
  wire [15:0] Data_Length,Gapength;
  wire [7 :0] FrameRate;
  Mac_Ctrl iMac_Ctrl(
    .clk             (e_rxc),
    .TxEn            (e_txen),
    .TxErr           (e_txer),
    .TxData          (e_txd),
    .RxEn            (e_rxdv),
    .RxData          (e_rxd),
    .SendEn          (SendEn),
    .Dkey2           (!key2Reg[2]),
    .Clear           (ClearMac),
    .DataLength     (Data_Length),
    .GapLength       (GapLength),
    .TxCNT           (TxCNT),
    .RxCNT           (RxCNT),
    .TxLimit         (TxLimit),
    .FrameRate       (FrameRate),
    .Ram_MacText_we  (Ram_MacText_we),
    .Ram_MacText_addr(Ram_MacText_addr),
    .Ram_MacText_din (Ram_MacText_din),
    .Ram_MacText_dout(0)
);
  
  VGA_HDMI iVGA_HDMI(
    .clk          (CLK_VGA),
    .Vsync        (vga_vs),
    .Hsync        (vga_hs),
    .DataEn       (),
    .X            (),
    .X_5          (X_5),
    .Y            (Y),
    .Width        (Width),
    .Height       (Height),
    .ResolutionSel(`WH1280x1024),
    .RGBI_R       (R),
    .RGBI_G       (G),
    .RGBI_B       (B),
    .RGBO_R       (RO),
    .RGBO_G       (GO),
    .RGBO_B       (BO)
    );
  KeyDetect (
    .clk  (CLK_VGA),
    .key1 (key1 ),
    .key2 (key2 ),
    .key3 (key3 ),
    .key4 (key4 ),
    .Dkey1(Dkey1),
    .Dkey2(Dkey2),
    .Dkey3(Dkey3),
    .Dkey4(Dkey4),
    .Clear(Clear),
    .Dkey1Down(Dkey1Down)
  );  
    
  
  wire [11:0] TextBox0_Ram_addr;
  wire [8 :0] TextBox0_Ram_dout;  
  wire [10:0] Char0_Rom_addr;
  wire [15:0] Char0_Rom_dout;
  FPGA_GUI iFPGA_GUI(
    .clk   (CLK_VGA),
    .X_5   (X_5),
    .Y     (Y),
    .Width (Width),
    .Height(Height),
    .Clear(Clear),
    .Dkey1Down(Dkey1Down),
    .Arbiter0_RGBO_R(R),
    .Arbiter0_RGBO_G(G),
    .Arbiter0_RGBO_B(B),
    .Char0_Rom_we     (),
    .Char0_Rom_addr   (Char0_Rom_addr),
    .Char0_Rom_din    (),
    .Char0_Rom_dout   (Char0_Rom_dout),
    .TextBox0_Ram_we  (TextBox0_Ram_we),
    .TextBox0_Ram_addr(TextBox0_Ram_addr),
    .TextBox0_Ram_din (),
    .TextBox0_Ram_dout(TextBox0_Ram_dout)  
    
  );
 
 
  reg [2 :0] key3Reg = 1,key2Reg = 1,key1Reg = 1;    
  reg [10:0] TRaddrb = 0; 
  reg  TRweb;
  
  always@(posedge e_rxc)
  begin 
  	key3Reg[0] <= Dkey3;
  	key3Reg[2:1] <= key3Reg[1:0];   
  	key2Reg[0] <= Dkey2;         
  	key2Reg[2:1] <= key2Reg[1:0];   
  	key1Reg[0] <= Dkey1;         
  	key1Reg[2:1] <= key1Reg[1:0];





  	
  end
  
  
  TextRam9x2048 iTextRam9x2048 (
    .clka(CLK_VGA),
    .wea(TextBox0_Ram_we),
    .addra(TextBox0_Ram_addr),
    .dina(0),
    .douta(TextBox0_Ram_dout),
    .clkb (e_rxc),
    .web  (Ram_MacText_we),
    .addrb(Ram_MacText_addr),
    .dinb (Ram_MacText_din),
    .doutb()
   );  
    

   
   
   FontRam16x2048  iFontRam16x2048(
    .clka(CLK_VGA),
    .wea(0),
    .addra(Char0_Rom_addr),
    .dina(0),
    .douta(Char0_Rom_dout),
    .clkb(CLK_VGA),
    .web(0),
    .addrb(0),
    .dinb(0),
    .doutb()
   );
  

  PLL2 iPLL2
   (
    .CLK_IN1(sys_clk),

    .CLK_150(CLK_150),
    .CLK_107(CLK_107),
    .CLK_50(CLK_50));
  wire [35:0] CONTROL0,CONTROL1;
  wire [127:0] SYNC_IN,SYNC_OUT;
  reg        RxReg ;
  reg [7:0]  RxData;   
  wire [7:0] TRIG0;
  always@(posedge e_rxc)
  begin
  	RxReg  <= e_rxdv;
  	RxData <= e_rxd ;
  end
  

  ICON2 iICON2 (                    
      .CONTROL0(CONTROL0),
      .CONTROL1(CONTROL1)
  );                                          
  
  VIO1 iVIO1 (
    .CONTROL(CONTROL0),
    .CLK(e_rxc),
    .SYNC_IN(SYNC_IN),
    .SYNC_OUT(SYNC_OUT)
  );
  
  ILA1 iILA1 (                   
      .CONTROL(CONTROL1),
      .CLK(e_rxc),
      .DATA({RxReg,RxData}),
      .TRIG0(TRIG0)
  );                                        
  assign SYNC_IN = {0,
                    FrameRate,
                    TxCNT,
						  RxCNT};
  assign Data_Length = SYNC_OUT[15:0];
  assign GapLength = SYNC_OUT[31:16]; 
  assign TxLimit = SYNC_OUT[55:32]; 
  assign TRIG0 = {0,e_txen,e_rxdv};
  
endmodule
module Top(
  input               sys_clk,
  output			        vga_hs,
  output			        vga_vs,
  output  [4:0]	      vga_r,
  output	[5:0]	      vga_g,
  output	[4:0] 	    vga_b,
  input               key1,
  input               key2,
  input               key3,
  input               key4,
  
  output              e_reset,


  input	               e_rxc,
	input	               e_rxdv,
	input	               e_rxer,
	input      [7:0]     e_rxd,

	input	               e_txc,
	output               e_gtxc,
	output               e_txen,
	output               e_txer,
	output     [7:0]     e_txd
  
  
  );

  wire [11:0] X_5,Y,Width,Height;
  wire [7 :0] R,G,B,RO,GO,BO;  
  
  assign e_gtxc = e_rxc;	 
  assign e_reset = 1'b1; 
  
  assign vga_r = RO[7:3],
         vga_g = GO[7:2],
         vga_b = BO[7:3];
  
  assign SendEn = !key3Reg[1] && key3Reg[2];  
  assign ClearMac = !key1Reg[1] && key1Reg[2]; 
  
  wire  CLK_VGA = CLK_107;
  
  wire [10:0] Ram_MacText_addr;
  wire [8 :0] Ram_MacText_din; 
  wire [23:0] TxCNT,RxCNT,TxLimit;
  wire [15:0] Data_Length,Gapength;
  wire [7 :0] FrameRate;
  Mac_Ctrl iMac_Ctrl(
    .clk             (e_rxc),
    .TxEn            (e_txen),
    .TxErr           (e_txer),
    .TxData          (e_txd),
    .RxEn            (e_rxdv),
    .RxData          (e_rxd),
    .SendEn          (SendEn),
    .Dkey2           (!key2Reg[2]),
    .Clear           (ClearMac),
    .DataLength     (Data_Length),
    .GapLength       (GapLength),
    .TxCNT           (TxCNT),
    .RxCNT           (RxCNT),
    .TxLimit         (TxLimit),
    .FrameRate       (FrameRate),
    .Ram_MacText_we  (Ram_MacText_we),
    .Ram_MacText_addr(Ram_MacText_addr),
    .Ram_MacText_din (Ram_MacText_din),
    .Ram_MacText_dout(0)
);
  
  VGA_HDMI iVGA_HDMI(
    .clk          (CLK_VGA),
    .Vsync        (vga_vs),
    .Hsync        (vga_hs),
    .DataEn       (),
    .X            (),
    .X_5          (X_5),
    .Y            (Y),
    .Width        (Width),
    .Height       (Height),
    .ResolutionSel(`WH1280x1024),
    .RGBI_R       (R),
    .RGBI_G       (G),
    .RGBI_B       (B),
    .RGBO_R       (RO),
    .RGBO_G       (GO),
    .RGBO_B       (BO)
    );
  KeyDetect (
    .clk  (CLK_VGA),
    .key1 (key1 ),
    .key2 (key2 ),
    .key3 (key3 ),
    .key4 (key4 ),
    .Dkey1(Dkey1),
    .Dkey2(Dkey2),
    .Dkey3(Dkey3),
    .Dkey4(Dkey4),
    .Clear(Clear),
    .Dkey1Down(Dkey1Down)
  );  
    
  
  wire [11:0] TextBox0_Ram_addr;
  wire [8 :0] TextBox0_Ram_dout;  
  wire [10:0] Char0_Rom_addr;
  wire [15:0] Char0_Rom_dout;
  FPGA_GUI iFPGA_GUI(
    .clk   (CLK_VGA),
    .X_5   (X_5),
    .Y     (Y),
    .Width (Width),
    .Height(Height),
    .Clear(Clear),
    .Dkey1Down(Dkey1Down),
    .Arbiter0_RGBO_R(R),
    .Arbiter0_RGBO_G(G),
    .Arbiter0_RGBO_B(B),
    .Char0_Rom_we     (),
    .Char0_Rom_addr   (Char0_Rom_addr),
    .Char0_Rom_din    (),
    .Char0_Rom_dout   (Char0_Rom_dout),
    .TextBox0_Ram_we  (TextBox0_Ram_we),
    .TextBox0_Ram_addr(TextBox0_Ram_addr),
    .TextBox0_Ram_din (),
    .TextBox0_Ram_dout(TextBox0_Ram_dout)  
    
  );
 
 
  reg [2 :0] key3Reg = 1,key2Reg = 1,key1Reg = 1;    
  reg [10:0] TRaddrb = 0; 
  reg  TRweb;
  
  always@(posedge e_rxc)
  begin 
  	key3Reg[0] <= Dkey3;
  	key3Reg[2:1] <= key3Reg[1:0];   
  	key2Reg[0] <= Dkey2;         
  	key2Reg[2:1] <= key2Reg[1:0];   
  	key1Reg[0] <= Dkey1;         
  	key1Reg[2:1] <= key1Reg[1:0];





  	
  end
  
  
  TextRam9x2048 iTextRam9x2048 (
    .clka(CLK_VGA),
    .wea(TextBox0_Ram_we),
    .addra(TextBox0_Ram_addr),
    .dina(0),
    .douta(TextBox0_Ram_dout),
    .clkb (e_rxc),
    .web  (Ram_MacText_we),
    .addrb(Ram_MacText_addr),
    .dinb (Ram_MacText_din),
    .doutb()
   );  
    

   
   
   FontRam16x2048  iFontRam16x2048(
    .clka(CLK_VGA),
    .wea(0),
    .addra(Char0_Rom_addr),
    .dina(0),
    .douta(Char0_Rom_dout),
    .clkb(CLK_VGA),
    .web(0),
    .addrb(0),
    .dinb(0),
    .doutb()
   );
  

  PLL2 iPLL2
   (
    .CLK_IN1(sys_clk),

    .CLK_150(CLK_150),
    .CLK_107(CLK_107),
    .CLK_50(CLK_50));
  wire [35:0] CONTROL0,CONTROL1;
  wire [127:0] SYNC_IN,SYNC_OUT;
  reg        RxReg ;
  reg [7:0]  RxData;   
  wire [7:0] TRIG0;
  always@(posedge e_rxc)
  begin
  	RxReg  <= e_rxdv;
  	RxData <= e_rxd ;
  end
  

  ICON2 iICON2 (                    
      .CONTROL0(CONTROL0),
      .CONTROL1(CONTROL1)
  );                                          
  
  VIO1 iVIO1 (
    .CONTROL(CONTROL0),
    .CLK(e_rxc),
    .SYNC_IN(SYNC_IN),
    .SYNC_OUT(SYNC_OUT)
  );
  
  ILA1 iILA1 (                   
      .CONTROL(CONTROL1),
      .CLK(e_rxc),
      .DATA({RxReg,RxData}),
      .TRIG0(TRIG0)
  );                                        
  assign SYNC_IN = {0,
                    FrameRate,
                    TxCNT,
						  RxCNT};
  assign Data_Length = SYNC_OUT[15:0];
  assign GapLength = SYNC_OUT[31:16]; 
  assign TxLimit = SYNC_OUT[55:32]; 
  assign TRIG0 = {0,e_txen,e_rxdv};
  
endmodule