data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v
1: b'%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:50: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v.v\n             data/full_repos/permissive/162856122/cores/or1200,data/full_repos/permissive/162856122/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:52: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:63: Define or directive not defined: \'`OR1200_OPERAND_WIDTH\'\nparameter width = `OR1200_OPERAND_WIDTH;\n                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:63: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter width = `OR1200_OPERAND_WIDTH;\n                                       ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:77: Define or directive not defined: \'`OR1200_SEL_WIDTH\'\ninput [`OR1200_SEL_WIDTH-1:0] sel_a;\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:78: Define or directive not defined: \'`OR1200_SEL_WIDTH\'\ninput [`OR1200_SEL_WIDTH-1:0] sel_b;\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:97: Define or directive not defined: \'`OR1200_RST_EVENT\'\nalways @(posedge clk or `OR1200_RST_EVENT rst) begin\n                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:98: Define or directive not defined: \'`OR1200_RST_VALUE\'\n if (rst == `OR1200_RST_VALUE) begin\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:98: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `OR1200_RST_VALUE) begin\n                             ^\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:101: syntax error, unexpected else\n end else if (!ex_freeze && id_freeze && !saved_a) begin\n     ^~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:113: Define or directive not defined: \'`OR1200_RST_EVENT\'\nalways @(posedge clk or `OR1200_RST_EVENT rst) begin\n                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:114: Define or directive not defined: \'`OR1200_RST_VALUE\'\n if (rst == `OR1200_RST_VALUE) begin\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:135: Define or directive not defined: \'`OR1200_SEL_EX_FORW\'\n  `OR1200_SEL_EX_FORW:\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:137: Define or directive not defined: \'`OR1200_SEL_WB_FORW\'\n  `OR1200_SEL_WB_FORW:\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:153: Define or directive not defined: \'`OR1200_SEL_IMM\'\n  `OR1200_SEL_IMM:\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:155: Define or directive not defined: \'`OR1200_SEL_EX_FORW\'\n  `OR1200_SEL_EX_FORW:\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/162856122/cores/or1200/or1200_operandmuxes.v:157: Define or directive not defined: \'`OR1200_SEL_WB_FORW\'\n  `OR1200_SEL_WB_FORW:\n  ^~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module or1200_operandmuxes(

	clk, rst,


	id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
	simm, sel_a, sel_b, operand_a, operand_b, muxed_a, muxed_b
);

parameter width = `OR1200_OPERAND_WIDTH;




input				clk;
input				rst;
input				id_freeze;
input				ex_freeze;
input	[width-1:0]		rf_dataa;
input	[width-1:0]		rf_datab;
input	[width-1:0]		ex_forw;
input	[width-1:0]		wb_forw;
input	[width-1:0]		simm;
input	[`OR1200_SEL_WIDTH-1:0]	sel_a;
input	[`OR1200_SEL_WIDTH-1:0]	sel_b;
output	[width-1:0]		operand_a;
output	[width-1:0]		operand_b;
output	[width-1:0]		muxed_a;
output	[width-1:0]		muxed_b;




reg	[width-1:0]		operand_a;
reg	[width-1:0]		operand_b;
reg	[width-1:0]		muxed_a;
reg	[width-1:0]		muxed_b;
reg				saved_a;
reg				saved_b;




always @(posedge clk or `OR1200_RST_EVENT rst) begin
	if (rst == `OR1200_RST_VALUE) begin
		operand_a <=  32'd0;
		saved_a <=  1'b0;
	end else if (!ex_freeze && id_freeze && !saved_a) begin
		operand_a <=  muxed_a;
		saved_a <=  1'b1;
	end else if (!ex_freeze && !saved_a) begin
		operand_a <=  muxed_a;
	end else if (!ex_freeze && !id_freeze)
		saved_a <=  1'b0;
end




always @(posedge clk or `OR1200_RST_EVENT rst) begin
	if (rst == `OR1200_RST_VALUE) begin
		operand_b <=  32'd0;
		saved_b <=  1'b0;
	end else if (!ex_freeze && id_freeze && !saved_b) begin
		operand_b <=  muxed_b;
		saved_b <=  1'b1;
	end else if (!ex_freeze && !saved_b) begin
		operand_b <=  muxed_b;
	end else if (!ex_freeze && !id_freeze)
		saved_b <=  1'b0;
end




always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
	casez (sel_a)
`else
	casez (sel_a)
`endif
		`OR1200_SEL_EX_FORW:
			muxed_a = ex_forw;
		`OR1200_SEL_WB_FORW:
			muxed_a = wb_forw;
		default:
			muxed_a = rf_dataa;
	endcase
end




always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
	casez (sel_b)
`else
	casez (sel_b)
`endif
		`OR1200_SEL_IMM:
			muxed_b = simm;
		`OR1200_SEL_EX_FORW:
			muxed_b = ex_forw;
		`OR1200_SEL_WB_FORW:
			muxed_b = wb_forw;
		default:
			muxed_b = rf_datab;
	endcase
end

endmodule
module or1200_operandmuxes(

	clk, rst,


	id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
	simm, sel_a, sel_b, operand_a, operand_b, muxed_a, muxed_b
);


parameter width = `OR1200_OPERAND_WIDTH;




input				clk;
input				rst;
input				id_freeze;
input				ex_freeze;
input	[width-1:0]		rf_dataa;
input	[width-1:0]		rf_datab;
input	[width-1:0]		ex_forw;
input	[width-1:0]		wb_forw;
input	[width-1:0]		simm;
input	[`OR1200_SEL_WIDTH-1:0]	sel_a;
input	[`OR1200_SEL_WIDTH-1:0]	sel_b;
output	[width-1:0]		operand_a;
output	[width-1:0]		operand_b;
output	[width-1:0]		muxed_a;
output	[width-1:0]		muxed_b;




reg	[width-1:0]		operand_a;
reg	[width-1:0]		operand_b;
reg	[width-1:0]		muxed_a;
reg	[width-1:0]		muxed_b;
reg				saved_a;
reg				saved_b;




always @(posedge clk or `OR1200_RST_EVENT rst) begin
	if (rst == `OR1200_RST_VALUE) begin
		operand_a <=  32'd0;
		saved_a <=  1'b0;
	end else if (!ex_freeze && id_freeze && !saved_a) begin
		operand_a <=  muxed_a;
		saved_a <=  1'b1;
	end else if (!ex_freeze && !saved_a) begin
		operand_a <=  muxed_a;
	end else if (!ex_freeze && !id_freeze)
		saved_a <=  1'b0;
end




always @(posedge clk or `OR1200_RST_EVENT rst) begin
	if (rst == `OR1200_RST_VALUE) begin
		operand_b <=  32'd0;
		saved_b <=  1'b0;
	end else if (!ex_freeze && id_freeze && !saved_b) begin
		operand_b <=  muxed_b;
		saved_b <=  1'b1;
	end else if (!ex_freeze && !saved_b) begin
		operand_b <=  muxed_b;
	end else if (!ex_freeze && !id_freeze)
		saved_b <=  1'b0;
end




always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
	casez (sel_a)
`else
	casez (sel_a)
`endif
		`OR1200_SEL_EX_FORW:
			muxed_a = ex_forw;
		`OR1200_SEL_WB_FORW:
			muxed_a = wb_forw;
		default:
			muxed_a = rf_dataa;
	endcase
end




always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
	casez (sel_b)
`else
	casez (sel_b)
`endif
		`OR1200_SEL_IMM:
			muxed_b = simm;
		`OR1200_SEL_EX_FORW:
			muxed_b = ex_forw;
		`OR1200_SEL_WB_FORW:
			muxed_b = wb_forw;
		default:
			muxed_b = rf_datab;
	endcase
end

endmodule