data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:98: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:102: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:107: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:108: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:110: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:111: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:113: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:114: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:116: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:117: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Error: data/full_repos/permissive/17099167/system/hardware/cores/fabric/unitTestDelta.v:120: Cannot find file containing module: \'ovl_delta_wrapped\'\n  ovl_delta_wrapped oad(\n  ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_delta_wrapped\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_delta_wrapped.v\n             data/full_repos/permissive/17099167/system/hardware/cores/fabric,data/full_repos/permissive/17099167/ovl_delta_wrapped.sv\n             ovl_delta_wrapped\n             ovl_delta_wrapped.v\n             ovl_delta_wrapped.sv\n             obj_dir/ovl_delta_wrapped\n             obj_dir/ovl_delta_wrapped.v\n             obj_dir/ovl_delta_wrapped.sv\n%Error: Exiting due to 1 error(s), 36 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module unitTestDelta();
  reg clk;
  wire rst;
  reg [31:0] b;
  wire inv;
  wire assert_delta;
  
  initial begin
    clk = 1'b0;
    b = 32'b0;
  end
   
  assign rst = 1'b0;
  assign inv = 1'b0;
  
  always begin
    #10 clk = ~clk;
    #10 clk = ~clk;
    b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h5;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h3;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
  end

  ovl_delta_wrapped oad(
    .clk(clk),
    .rst(rst),
    .min(8'h0),
    .max(8'h4),
    .test_expr(b),
    .prevConfigInvalid(inv),
    .out(assert_edge)
  );
endmodule
module unitTestDelta();

  reg clk;
  wire rst;
  reg [31:0] b;
  wire inv;
  wire assert_delta;
  
  initial begin
    clk = 1'b0;
    b = 32'b0;
  end
   
  assign rst = 1'b0;
  assign inv = 1'b0;
  
  always begin
    #10 clk = ~clk;
    #10 clk = ~clk;
    b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h5;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h3;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
     b = b + 32'h4;
    #10 clk = ~clk;
    #10 clk = ~clk;
  end

  ovl_delta_wrapped oad(
    .clk(clk),
    .rst(rst),
    .min(8'h0),
    .max(8'h4),
    .test_expr(b),
    .prevConfigInvalid(inv),
    .out(assert_edge)
  );
endmodule