data/full_repos/permissive/19905110/minsoc/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/minsoc/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v:58: Cannot find include file: minsoc_defines.v\n`include "minsoc_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/utils/contributions/initialized_onchip_ram,data/full_repos/permissive/19905110/minsoc_defines.v\n             data/full_repos/permissive/19905110/minsoc/utils/contributions/initialized_onchip_ram,data/full_repos/permissive/19905110/minsoc_defines.v.v\n             data/full_repos/permissive/19905110/minsoc/utils/contributions/initialized_onchip_ram,data/full_repos/permissive/19905110/minsoc_defines.v.sv\n             minsoc_defines.v\n             minsoc_defines.v.v\n             minsoc_defines.v.sv\n             obj_dir/minsoc_defines.v\n             obj_dir/minsoc_defines.v.v\n             obj_dir/minsoc_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module minsoc_onchip_ram_top ( 
  wb_clk_i, wb_rst_i, 
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, 
  wb_stb_i, wb_ack_o, wb_err_o 
); 
 



parameter    adr_width = 13;
localparam    aw_int = 11;
localparam    blocks = (1<<(adr_width-aw_int));




input      wb_clk_i; 
input      wb_rst_i; 
 



input  [31:0]   wb_dat_i; 
output [31:0]   wb_dat_o; 
input  [31:0]   wb_adr_i; 
input  [3:0]    wb_sel_i; 
input      wb_we_i; 
input      wb_cyc_i; 
input      wb_stb_i; 
output     wb_ack_o; 
output     wb_err_o; 
 



wire    we; 
wire [3:0]  be_i; 
wire [31:0]  wb_dat_o; 
reg    ack_we; 
reg    ack_re; 



assign wb_ack_o = ack_re | ack_we; 
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]);
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); 
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; 
 



always @ (negedge wb_clk_i or posedge wb_rst_i) 
begin 
if (wb_rst_i) 
    ack_we <= 1'b0; 
  else 
  if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) 
    ack_we <= #1 1'b1; 
  else 
    ack_we <= #1 1'b0; 
end 
 



always @ (posedge wb_clk_i or posedge wb_rst_i) 
begin 
  if (wb_rst_i) 
    ack_re <= 1'b0; 
  else 
  if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) 
    ack_re <= #1 1'b1; 
  else 
    ack_re <= #1 1'b0; 
end 


localparam mux_in_nr = blocks;
localparam slices = adr_width-aw_int;
localparam mux_out_nr = blocks-1;

wire [31:0] int_dat_o[0:mux_in_nr-1];
wire [31:0] mux_out[0:mux_out_nr-1];

generate
genvar j, k;
	for (j=0; j<slices; j=j+1) begin : SLICES
		for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
			if (j==0) begin
				mux21 #
                (
                    .dw(32)
                ) 
                mux_int(
                    .sel( wb_adr_i[aw_int+2+j] ), 
                    .in1( int_dat_o[k*2] ),
				    .in2( int_dat_o[k*2+1] ), 
                    .out( mux_out[k] )
                );
			end
			else begin
				mux21 #
                (
                    .dw(32)
                ) 
                mux_int(
                    .sel( wb_adr_i[aw_int+2+j] ), 
				    .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), 
				    .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), 
				    .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
                );
			end
		end
	end
endgenerate


assign wb_dat_o = mux_out[mux_out_nr-1];





wire [blocks-1:0] bank;
 
generate 
genvar i;
    for (i=0; i < blocks; i=i+1) begin : MEM

        assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;



		  RAMB16_S9 block_ram_0(
				.CLK(wb_clk_i),
				.SSR(wb_rst_i),
				.ADDR(wb_adr_i[aw_int+1:2]),
				.DI(wb_dat_i[7:0]),
				.DIP(1'b0),
				.EN(be_i[0]),
				.WE(we & bank[i]),
				.DO(int_dat_o[i][7:0]),
				.DOP()
			);


		  RAMB16_S9 block_ram_1(
				.CLK(wb_clk_i),
				.SSR(wb_rst_i),
				.ADDR(wb_adr_i[aw_int+1:2]),
				.DI(wb_dat_i[15:8]),
				.DIP(1'b0),
				.EN(be_i[1]),
				.WE(we & bank[i]),
				.DO(int_dat_o[i][15:8]),
				.DOP()
			);

		  RAMB16_S9 block_ram_2(
				.CLK(wb_clk_i),
				.SSR(wb_rst_i),
				.ADDR(wb_adr_i[aw_int+1:2]),
				.DI(wb_dat_i[23:16]),
				.DIP(1'b0),
				.EN(be_i[2]),
				.WE(we & bank[i]),
				.DO(int_dat_o[i][23:16]),
				.DOP()
			);


		  RAMB16_S9 block_ram_3(
				.CLK(wb_clk_i),
				.SSR(wb_rst_i),
				.ADDR(wb_adr_i[aw_int+1:2]),
				.DI(wb_dat_i[31:24]),
				.DIP(1'b0),
				.EN(be_i[3]),
				.WE(we & bank[i]),
				.DO(int_dat_o[i][31:24]),
				.DOP()
			);

    end
endgenerate

`ifdef BLOCK_RAM_INIT
`include "block_ram.init"
`endif

endmodule
module minsoc_onchip_ram_top ( 
  wb_clk_i, wb_rst_i, 
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, 
  wb_stb_i, wb_ack_o, wb_err_o 
);
 
 



parameter    adr_width = 13;
localparam    aw_int = 11;
localparam    blocks = (1<<(adr_width-aw_int));




input      wb_clk_i; 
input      wb_rst_i; 
 



input  [31:0]   wb_dat_i; 
output [31:0]   wb_dat_o; 
input  [31:0]   wb_adr_i; 
input  [3:0]    wb_sel_i; 
input      wb_we_i; 
input      wb_cyc_i; 
input      wb_stb_i; 
output     wb_ack_o; 
output     wb_err_o; 
 



wire    we; 
wire [3:0]  be_i; 
wire [31:0]  wb_dat_o; 
reg    ack_we; 
reg    ack_re; 



assign wb_ack_o = ack_re | ack_we; 
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]);
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); 
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; 
 



always @ (negedge wb_clk_i or posedge wb_rst_i) 
begin 
if (wb_rst_i) 
    ack_we <= 1'b0; 
  else 
  if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) 
    ack_we <= #1 1'b1; 
  else 
    ack_we <= #1 1'b0; 
end 
 



always @ (posedge wb_clk_i or posedge wb_rst_i) 
begin 
  if (wb_rst_i) 
    ack_re <= 1'b0; 
  else 
  if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) 
    ack_re <= #1 1'b1; 
  else 
    ack_re <= #1 1'b0; 
end 


localparam mux_in_nr = blocks;
localparam slices = adr_width-aw_int;
localparam mux_out_nr = blocks-1;

wire [31:0] int_dat_o[0:mux_in_nr-1];
wire [31:0] mux_out[0:mux_out_nr-1];

generate
genvar j, k;
	for (j=0; j<slices; j=j+1) begin : SLICES
		for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
			if (j==0) begin
				mux21 #
                (
                    .dw(32)
                ) 
                mux_int(
                    .sel( wb_adr_i[aw_int+2+j] ), 
                    .in1( int_dat_o[k*2] ),
				    .in2( int_dat_o[k*2+1] ), 
                    .out( mux_out[k] )
                );
			end
			else begin
				mux21 #
                (
                    .dw(32)
                ) 
                mux_int(
                    .sel( wb_adr_i[aw_int+2+j] ), 
				    .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), 
				    .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), 
				    .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
                );
			end
		end
	end
endgenerate


assign wb_dat_o = mux_out[mux_out_nr-1];





wire [blocks-1:0] bank;
 
generate 
genvar i;
    for (i=0; i < blocks; i=i+1) begin : MEM

        assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;



		  RAMB16_S9 block_ram_0(
				.CLK(wb_clk_i),
				.SSR(wb_rst_i),
				.ADDR(wb_adr_i[aw_int+1:2]),
				.DI(wb_dat_i[7:0]),
				.DIP(1'b0),
				.EN(be_i[0]),
				.WE(we & bank[i]),
				.DO(int_dat_o[i][7:0]),
				.DOP()
			);


		  RAMB16_S9 block_ram_1(
				.CLK(wb_clk_i),
				.SSR(wb_rst_i),
				.ADDR(wb_adr_i[aw_int+1:2]),
				.DI(wb_dat_i[15:8]),
				.DIP(1'b0),
				.EN(be_i[1]),
				.WE(we & bank[i]),
				.DO(int_dat_o[i][15:8]),
				.DOP()
			);

		  RAMB16_S9 block_ram_2(
				.CLK(wb_clk_i),
				.SSR(wb_rst_i),
				.ADDR(wb_adr_i[aw_int+1:2]),
				.DI(wb_dat_i[23:16]),
				.DIP(1'b0),
				.EN(be_i[2]),
				.WE(we & bank[i]),
				.DO(int_dat_o[i][23:16]),
				.DOP()
			);


		  RAMB16_S9 block_ram_3(
				.CLK(wb_clk_i),
				.SSR(wb_rst_i),
				.ADDR(wb_adr_i[aw_int+1:2]),
				.DI(wb_dat_i[31:24]),
				.DIP(1'b0),
				.EN(be_i[3]),
				.WE(we & bank[i]),
				.DO(int_dat_o[i][31:24]),
				.DOP()
			);

    end
endgenerate

`ifdef BLOCK_RAM_INIT
`include "block_ram.init"
`endif

endmodule