data/full_repos/permissive/174323821/hdl/ram/jtframe_dual_nvram.v
1: b"%Error: data/full_repos/permissive/174323821/hdl/ram/jtframe_dual_nvram.v:47: Cannot find file containing module: 'jtframe_dual_ram'\njtframe_dual_ram #(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174323821/hdl/ram,data/full_repos/permissive/174323821/jtframe_dual_ram\n             data/full_repos/permissive/174323821/hdl/ram,data/full_repos/permissive/174323821/jtframe_dual_ram.v\n             data/full_repos/permissive/174323821/hdl/ram,data/full_repos/permissive/174323821/jtframe_dual_ram.sv\n             jtframe_dual_ram\n             jtframe_dual_ram.v\n             jtframe_dual_ram.sv\n             obj_dir/jtframe_dual_ram\n             obj_dir/jtframe_dual_ram.v\n             obj_dir/jtframe_dual_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module jtframe_dual_nvram #(parameter dw=8, aw=10,
    simfile="", simhexfile="", synfile="", dumpfile="dump.hex"
)(

    input   clk0,
    input   [dw-1:0] data0,
    input   [aw-1:0] addr0,
    input   we0,
    output  [dw-1:0] q0,

    input   clk1,
    input   [aw-1:0] addr1a,
    input   [aw-1:0] addr1b,
    input   sel_b,
    input   we_b,
    input   [dw-1:0] data1,
    output  [dw-1:0] q1
);

wire [aw-1:0] a_mux;
wire          w_mux;

assign a_mux = sel_b ? addr1b : addr1a;
assign w_mux = sel_b & we_b;

jtframe_dual_ram #(
    .dw        ( dw         ),
    .aw        ( aw         ),
    .simfile   ( simfile    ),
    .simhexfile( simhexfile ),
    .synfile   ( synfile    ),
    .dumpfile  ( dumpfile   )
) u_dual(

    .clk0   ( clk0  ),
    .data0  ( data0 ),
    .addr0  ( addr0 ),
    .we0    ( we0   ),
    .q0     ( q0    ),

    .clk1   ( clk1  ),
    .data1  ( data1 ),
    .addr1  ( a_mux ),
    .we1    ( w_mux ),
    .q1     ( q1    )
);

endmodule
module jtframe_dual_nvram #(parameter dw=8, aw=10,
    simfile="", simhexfile="", synfile="", dumpfile="dump.hex"
)(

    input   clk0,
    input   [dw-1:0] data0,
    input   [aw-1:0] addr0,
    input   we0,
    output  [dw-1:0] q0,

    input   clk1,
    input   [aw-1:0] addr1a,
    input   [aw-1:0] addr1b,
    input   sel_b,
    input   we_b,
    input   [dw-1:0] data1,
    output  [dw-1:0] q1
);


wire [aw-1:0] a_mux;
wire          w_mux;

assign a_mux = sel_b ? addr1b : addr1a;
assign w_mux = sel_b & we_b;

jtframe_dual_ram #(
    .dw        ( dw         ),
    .aw        ( aw         ),
    .simfile   ( simfile    ),
    .simhexfile( simhexfile ),
    .synfile   ( synfile    ),
    .dumpfile  ( dumpfile   )
) u_dual(

    .clk0   ( clk0  ),
    .data0  ( data0 ),
    .addr0  ( addr0 ),
    .we0    ( we0   ),
    .q0     ( q0    ),

    .clk1   ( clk1  ),
    .data1  ( data1 ),
    .addr1  ( a_mux ),
    .we1    ( w_mux ),
    .q1     ( q1    )
);

endmodule