data/full_repos/permissive/219228794/src/FPGA_GreenBeret.v
1: b"%Error: data/full_repos/permissive/219228794/src/FPGA_GreenBeret.v:47: Cannot find file containing module: 'MAIN'\nMAIN cpu\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/219228794/src,data/full_repos/permissive/219228794/MAIN\n             data/full_repos/permissive/219228794/src,data/full_repos/permissive/219228794/MAIN.v\n             data/full_repos/permissive/219228794/src,data/full_repos/permissive/219228794/MAIN.sv\n             MAIN\n             MAIN.v\n             MAIN.sv\n             obj_dir/MAIN\n             obj_dir/MAIN.v\n             obj_dir/MAIN.sv\n%Error: data/full_repos/permissive/219228794/src/FPGA_GreenBeret.v:62: Cannot find file containing module: 'VIDEO'\nVIDEO vid\n^~~~~\n%Error: data/full_repos/permissive/219228794/src/FPGA_GreenBeret.v:78: Cannot find file containing module: 'SOUND'\nSOUND snd\n^~~~~\n%Error: Exiting due to 3 error(s)\n"
module FPGA_GreenBeret
(
	input				clk48M,
	input				reset,

	input	  [5:0]	INP0,
	input	  [5:0]	INP1,
	input	  [2:0]	INP2,

	input   [8:0]  PH,
	input   [8:0]  PV,
	output         PCLK,
	output [11:0]	POUT,

	output  [7:0]	SND,


	input				ROMCL,
	input  [17:0]  ROMAD,
	input   [7:0]	ROMDT,
	input				ROMEN
);


wire clk24M, clk12M, clk6M, clk3M;
CLKGEN clks( clk48M, clk24M, clk12M, clk6M, clk3M );

wire   VCLKx8 = clk48M;
wire   VCLKx4 = clk24M;
wire   VCLKx2 = clk12M;
wire	   VCLK = clk6M;

wire   CPUCLK = clk3M;
wire    CPUCL = ~clk3M; 



wire			CPUMX, CPUWR, VIDDV;
wire  [7:0]	CPUWD, VIDRD;
wire [15:0]	CPUAD;

MAIN cpu
(
	CPUCLK, reset,
	PH,PV,
	INP0,INP1,INP2,

	CPUMX, CPUAD,
	CPUWR, CPUWD,
	VIDDV, VIDRD,
	
	ROMCL,ROMAD,ROMDT,ROMEN
);



VIDEO vid
(
	VCLKx8, VCLKx4, VCLKx2, VCLK,
	PH, PV, 1'b0, 1'b0,
	PCLK, POUT,

	CPUCL,
	CPUMX, CPUAD,
	CPUWR, CPUWD,
	VIDDV, VIDRD,

	ROMCL,ROMAD,ROMDT,ROMEN
);



SOUND snd
(
	clk48M, reset,
	SND,

	CPUCL,
	CPUMX, CPUAD,
	CPUWR, CPUWD
);

endmodule
module FPGA_GreenBeret
(
	input				clk48M,
	input				reset,

	input	  [5:0]	INP0,
	input	  [5:0]	INP1,
	input	  [2:0]	INP2,

	input   [8:0]  PH,
	input   [8:0]  PV,
	output         PCLK,
	output [11:0]	POUT,

	output  [7:0]	SND,


	input				ROMCL,
	input  [17:0]  ROMAD,
	input   [7:0]	ROMDT,
	input				ROMEN
);



wire clk24M, clk12M, clk6M, clk3M;
CLKGEN clks( clk48M, clk24M, clk12M, clk6M, clk3M );

wire   VCLKx8 = clk48M;
wire   VCLKx4 = clk24M;
wire   VCLKx2 = clk12M;
wire	   VCLK = clk6M;

wire   CPUCLK = clk3M;
wire    CPUCL = ~clk3M; 



wire			CPUMX, CPUWR, VIDDV;
wire  [7:0]	CPUWD, VIDRD;
wire [15:0]	CPUAD;

MAIN cpu
(
	CPUCLK, reset,
	PH,PV,
	INP0,INP1,INP2,

	CPUMX, CPUAD,
	CPUWR, CPUWD,
	VIDDV, VIDRD,
	
	ROMCL,ROMAD,ROMDT,ROMEN
);



VIDEO vid
(
	VCLKx8, VCLKx4, VCLKx2, VCLK,
	PH, PV, 1'b0, 1'b0,
	PCLK, POUT,

	CPUCL,
	CPUMX, CPUAD,
	CPUWR, CPUWD,
	VIDDV, VIDRD,

	ROMCL,ROMAD,ROMDT,ROMEN
);



SOUND snd
(
	clk48M, reset,
	SND,

	CPUCL,
	CPUMX, CPUAD,
	CPUWR, CPUWD
);

endmodule