data/full_repos/permissive/13111265/verilog/src/receivers/test/RxUart_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/13111265/verilog/src/receivers/test/RxUart_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/13111265/verilog/src/receivers/test/RxUart_tb.v:34: Cannot find file containing module: \'RxUart\'\nRxUart #(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/13111265/verilog/src/receivers/test,data/full_repos/permissive/13111265/RxUart\n             data/full_repos/permissive/13111265/verilog/src/receivers/test,data/full_repos/permissive/13111265/RxUart.v\n             data/full_repos/permissive/13111265/verilog/src/receivers/test,data/full_repos/permissive/13111265/RxUart.sv\n             RxUart\n             RxUart.v\n             RxUart.sv\n             obj_dir/RxUart\n             obj_dir/RxUart.v\n             obj_dir/RxUart.sv\n%Error: data/full_repos/permissive/13111265/verilog/src/receivers/test/RxUart_tb.v:50: Cannot find file containing module: \'TxUart\'\nTxUart #(\n^~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RxUart_tb ();

reg clk;
reg rst;
reg x16BaudStrobe;
reg read;
reg write;
reg [7:0] dataIn;

wire [7:0] dataOut;
wire rxDataPresent;
wire rxHalfFull;
wire rxFull;
wire serial;
wire txDataPresent;
wire txHalfFull;
wire txFull;

reg [2:0] baudStrobeCount;

integer i;

always #1 clk = ~clk;
always @(posedge clk) baudStrobeCount <= baudStrobeCount + 2'd1;
always @(posedge clk) x16BaudStrobe <= baudStrobeCount == 'd0;

initial begin
    clk = 1'b0;
    rst = 1'b1;
    x16BaudStrobe = 1'b0;
    read = 1'b0;
end

RxUart #(
    .LOG2_DEPTH(4)
)
uut
(
    .clk(clk),
    .rst(rst),
    .x16BaudStrobe(x16BaudStrobe),
    .read(read),
    .serialIn(serial),
    .dataOut(dataOut),
    .dataPresent(rxDataPresent),
    .halfFull(rxHalfFull),
    .full(rxFull)
);

TxUart #(
    .LOG2_DEPTH(4)
)
stimulus
(

    .clk(clk),
    .rst(rst),
    .x16BaudStrobe(x16BaudStrobe),
    .dataIn(dataIn),
    .write(write),

    .serialOut(serial),
    .dataPresent(txDataPresent),
    .halfFull(txHalfFull),
    .full(txFull)
);

endmodule
module RxUart_tb ();


reg clk;
reg rst;
reg x16BaudStrobe;
reg read;
reg write;
reg [7:0] dataIn;

wire [7:0] dataOut;
wire rxDataPresent;
wire rxHalfFull;
wire rxFull;
wire serial;
wire txDataPresent;
wire txHalfFull;
wire txFull;

reg [2:0] baudStrobeCount;

integer i;

always #1 clk = ~clk;
always @(posedge clk) baudStrobeCount <= baudStrobeCount + 2'd1;
always @(posedge clk) x16BaudStrobe <= baudStrobeCount == 'd0;

initial begin
    clk = 1'b0;
    rst = 1'b1;
    x16BaudStrobe = 1'b0;
    read = 1'b0;
end

RxUart #(
    .LOG2_DEPTH(4)
)
uut
(
    .clk(clk),
    .rst(rst),
    .x16BaudStrobe(x16BaudStrobe),
    .read(read),
    .serialIn(serial),
    .dataOut(dataOut),
    .dataPresent(rxDataPresent),
    .halfFull(rxHalfFull),
    .full(rxFull)
);

TxUart #(
    .LOG2_DEPTH(4)
)
stimulus
(

    .clk(clk),
    .rst(rst),
    .x16BaudStrobe(x16BaudStrobe),
    .dataIn(dataIn),
    .write(write),

    .serialOut(serial),
    .dataPresent(txDataPresent),
    .halfFull(txHalfFull),
    .full(txFull)
);

endmodule