data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/stream_split.v
data/verilator_xmls/f1d6e4f8-b30b-480c-98d6-b58b4428aa77.xml
module stream_split #(
  parameter NumStreams = 2)
  (
    input                       in_valid,
    output                      in_ready,

    output reg [NumStreams-1:0] out_valid,
    input      [NumStreams-1:0] out_ready
  );


  assign in_ready = &out_ready;



  reg       other_readys;
  integer   i, j;
  always @(*) begin
    for (i=0; i < NumStreams; i=i+1) begin
      other_readys = 1'b1;
      for (j=0; j < NumStreams; j=j+1)
        if (j != i)
          other_readys = other_readys & out_ready[j];

      out_valid[i] = other_readys & in_valid;
    end
  end

endmodule
module stream_split #(
  parameter NumStreams = 2)
  (
    input                       in_valid,
    output                      in_ready,

    output reg [NumStreams-1:0] out_valid,
    input      [NumStreams-1:0] out_ready
  );



  assign in_ready = &out_ready;



  reg       other_readys;
  integer   i, j;
  always @(*) begin
    for (i=0; i < NumStreams; i=i+1) begin
      other_readys = 1'b1;
      for (j=0; j < NumStreams; j=j+1)
        if (j != i)
          other_readys = other_readys & out_ready[j];

      out_valid[i] = other_readys & in_valid;
    end
  end

endmodule