data/full_repos/permissive/177289247/IFIDReg.v
data/verilator_xmls/54b5807d-85ec-4883-9bee-bc887526e41f.xml
module IFIDReg (
    input       clk,

    input       rst,

    input       Hazard,

    input[31:0] PC_in,
    input[31:0] Instr_in,


    output[31:0]PC_out,
    output[31:0]Instr_out
);


reg[63:0] StageReg;
assign {
    PC_out   [31:0],
    Instr_out[31:0]
} = StageReg [63:0];

always @(posedge rst) begin
    StageReg <= 64'b0;
end

initial begin
    StageReg <= 64'b0;
end

always @(posedge clk) begin
    if(Hazard) begin
        StageReg[63:0] <= 64'b0;
    end else begin
        StageReg[63:0] <= {
            PC_in   [31:0],
            Instr_in[31:0]
        };
    end
end



endmodule
module IFIDReg (
    input       clk,

    input       rst,

    input       Hazard,

    input[31:0] PC_in,
    input[31:0] Instr_in,


    output[31:0]PC_out,
    output[31:0]Instr_out
);



reg[63:0] StageReg;
assign {
    PC_out   [31:0],
    Instr_out[31:0]
} = StageReg [63:0];

always @(posedge rst) begin
    StageReg <= 64'b0;
end

initial begin
    StageReg <= 64'b0;
end

always @(posedge clk) begin
    if(Hazard) begin
        StageReg[63:0] <= 64'b0;
    end else begin
        StageReg[63:0] <= {
            PC_in   [31:0],
            Instr_in[31:0]
        };
    end
end



endmodule