data/full_repos/permissive/211316121/lab5_3_nexys4/74LS173.v
1: b'%Warning-WIDTH: data/full_repos/permissive/211316121/lab5_3_nexys4/74LS173.v:35: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n                                                                               : ... In instance Top_74LS173.top_173\n        Q<=\'bzzzz;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module LS173(
	input [3:0] D,
	input CP,
	input CR,
	input G1,
	input G2,
	input M,
	input N,
	output reg [3:0] Q
);

wire G;
wire EN;

assign G=G1|G2;
assign EN=(~M)&(~N);

always@(posedge CP,posedge CR,negedge EN)
begin
    if(~EN)
        Q<='bzzzz;
    else if(CR) 
        Q<='b0000;
	else if(G);
	else
		Q<=D;
end

endmodule
module LS173(
	input [3:0] D,
	input CP,
	input CR,
	input G1,
	input G2,
	input M,
	input N,
	output reg [3:0] Q
);


wire G;
wire EN;

assign G=G1|G2;
assign EN=(~M)&(~N);

always@(posedge CP,posedge CR,negedge EN)
begin
    if(~EN)
        Q<='bzzzz;
    else if(CR) 
        Q<='b0000;
	else if(G);
	else
		Q<=D;
end

endmodule