data/full_repos/permissive/18770871/control.v
None: at end of input
1: b'%Error: data/full_repos/permissive/18770871/control.v:4: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18770871,data/full_repos/permissive/18770871/define.v\n             data/full_repos/permissive/18770871,data/full_repos/permissive/18770871/define.v.v\n             data/full_repos/permissive/18770871,data/full_repos/permissive/18770871/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/18770871/control.v:26: syntax error, unexpected \')\', expecting \'[\'\n  );\n  ^\n%Error: data/full_repos/permissive/18770871/control.v:34: syntax error, unexpected output\n output reg rf_wen;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:35: syntax error, unexpected output\n output reg[2:0] alu_op;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:36: syntax error, unexpected output\n output reg alusrc;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:37: syntax error, unexpected output\n output reg regdest;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:38: syntax error, unexpected output\n output reg branch;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:39: syntax error, unexpected output\n output reg mem2reg;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:40: syntax error, unexpected output\n output reg lhb_llb_con1;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:41: syntax error, unexpected output\n output reg s5;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:42: syntax error, unexpected output\n output reg s6;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:43: syntax error, unexpected output\n output reg s7;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:44: syntax error, unexpected output\n output reg jal;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:45: syntax error, unexpected output\n output reg jr;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:46: syntax error, unexpected output\n output reg exec;\n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:47: syntax error, unexpected output\n output reg lw; \n ^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:51: syntax error, unexpected always\nalways @ (*)\n^~~~~~\n%Error: data/full_repos/permissive/18770871/control.v:55: Define or directive not defined: \'`ADD\'\n  if ( (opcode==`ADD) || (opcode==`SUB) || (opcode==`AND) || (opcode==`OR) )\n                ^~~~\n%Error: data/full_repos/permissive/18770871/control.v:55: Define or directive not defined: \'`SUB\'\n  if ( (opcode==`ADD) || (opcode==`SUB) || (opcode==`AND) || (opcode==`OR) )\n                                  ^~~~\n%Error: data/full_repos/permissive/18770871/control.v:55: Define or directive not defined: \'`AND\'\n  if ( (opcode==`ADD) || (opcode==`SUB) || (opcode==`AND) || (opcode==`OR) )\n                                                    ^~~~\n%Error: data/full_repos/permissive/18770871/control.v:55: Define or directive not defined: \'`OR\'\n  if ( (opcode==`ADD) || (opcode==`SUB) || (opcode==`AND) || (opcode==`OR) )\n                                                                      ^~~\n%Error: data/full_repos/permissive/18770871/control.v:73: Define or directive not defined: \'`SLL\'\n  if ( (opcode==`SLL) || (opcode==`SRL) || (opcode==`SRA) || (opcode==`RL) )\n                ^~~~\n%Error: data/full_repos/permissive/18770871/control.v:73: Define or directive not defined: \'`SRL\'\n  if ( (opcode==`SLL) || (opcode==`SRL) || (opcode==`SRA) || (opcode==`RL) )\n                                  ^~~~\n%Error: data/full_repos/permissive/18770871/control.v:73: Define or directive not defined: \'`SRA\'\n  if ( (opcode==`SLL) || (opcode==`SRL) || (opcode==`SRA) || (opcode==`RL) )\n                                                    ^~~~\n%Error: data/full_repos/permissive/18770871/control.v:73: Define or directive not defined: \'`RL\'\n  if ( (opcode==`SLL) || (opcode==`SRL) || (opcode==`SRA) || (opcode==`RL) )\n                                                                      ^~~\n%Error: data/full_repos/permissive/18770871/control.v:91: Define or directive not defined: \'`LW\'\n  if (opcode==`LW)\n              ^~~\n%Error: data/full_repos/permissive/18770871/control.v:109: Define or directive not defined: \'`SW\'\n  if (opcode==`SW)\n              ^~~\n%Error: data/full_repos/permissive/18770871/control.v:127: Define or directive not defined: \'`LHB\'\n  if((opcode == `LHB)) \n                ^~~~\n%Error: data/full_repos/permissive/18770871/control.v:145: Define or directive not defined: \'`LLB\'\n  if(opcode == `LLB)\n               ^~~~\n%Error: data/full_repos/permissive/18770871/control.v:158: Define or directive not defined: \'`JAL\'\n  if(opcode == `JAL)\n               ^~~~\n%Error: data/full_repos/permissive/18770871/control.v:177: Define or directive not defined: \'`JR\'\n  if(opcode == `JR)\n               ^~~\n%Error: data/full_repos/permissive/18770871/control.v:192: Define or directive not defined: \'`EXEC\'\n  if(opcode == `EXEC)\n               ^~~~~\n%Error: data/full_repos/permissive/18770871/control.v:220: Define or directive not defined: \'`BR\'\n  if((opcode == `BR))\n                ^~~\n%Error: Exiting due to 33 error(s)\n'
module control(
    opcode,


    dmem_wen,
    rf_wen,
    alu_op,
    alusrc,
    regdest,
    branch,
    mem2reg,
    lhb_llb_con1,
    s5,
    s6,
    s7,
    jal,
    jr,
    exec, 
    lw,

  );
 
 input[3:0] opcode;




 output reg dmem_wen;
 output reg rf_wen;
 output reg[2:0] alu_op;
 output reg alusrc;
 output reg regdest;
 output reg branch;
 output reg mem2reg;
 output reg lhb_llb_con1;
 output reg s5;
 output reg s6;
 output reg s7;
 output reg jal;
 output reg jr;
 output reg exec;
 output reg lw; 



always @ (*)
begin


  if ( (opcode==`ADD) || (opcode==`SUB) || (opcode==`AND) || (opcode==`OR) )
  begin
    dmem_wen=1;
    rf_wen=1;
    alu_op=opcode[2:0];
    alusrc=0;
    regdest=1;
    branch=0;
    mem2reg=0;
    lhb_llb_con1 = 0;
    s5 = 0;
    s6 = 1;
    s7 = 0;
    jal = 0; 
    jr = 0;
    exec = 0;
    lw=0;
  end
  if ( (opcode==`SLL) || (opcode==`SRL) || (opcode==`SRA) || (opcode==`RL) )
  begin
    dmem_wen=1;
    rf_wen=1;
    alu_op=opcode[2:0];
    alusrc=1;
    regdest=1;
    branch=0;
    mem2reg=0;
    lhb_llb_con1 = 0;
    s5 = 0;
    s6 = 1;
    s7 = 0;
    jal=0;
    jr = 0;
    exec = 0;
    lw=0;
  end
  if (opcode==`LW)
  begin
    dmem_wen=1;
    rf_wen=1;
    alu_op=3'b000;
    alusrc=1;
    regdest=1;
    branch=0;
    mem2reg=1;
    lhb_llb_con1 = 0;
    s5 = 0;
    s6 = 1;
    s7 = 0;
    jal=0;
    jr = 0;
    exec =0;
    lw=1;
  end
  if (opcode==`SW)
  begin
    dmem_wen=0;
    rf_wen=0;
    alu_op=3'b000;
    alusrc=1;
    regdest=0;
    branch=0;

    lhb_llb_con1 = 1;
    s5 = 0;
    s6 = 1;
    jal=0;
    jr = 0;
    exec = 0;
    lw=0;
    mem2reg=0;
  end
  if((opcode == `LHB)) 
  begin
    dmem_wen = 1;
    alu_op = 3'b010;
    rf_wen = 1;
    regdest = 1;
    branch = 0;
    lhb_llb_con1 = 1;
    mem2reg=0;
    alusrc = 0;
    s5 = 1;
    s6 = 0;
    s7 = 0;
    jal=0;
    jr = 0;
    exec = 0;
    lw=0;
  end
  if(opcode == `LLB)
  begin
    dmem_wen = 1;
    rf_wen = 1;
    regdest = 1;
    mem2reg=0;
    s7 = 1;
    branch = 0;
    jal=0;
    jr = 0;
    exec = 0;
    lw=0;
  end 
  if(opcode == `JAL)
  begin
    dmem_wen=1;
    rf_wen=1;
    alu_op=3'b000;


    branch=0;
    jal = 1;
    mem2reg=0;
    lhb_llb_con1 = 0;
    s5 = 0;
    s6 = 1;
    s7 = 0;
    jr = 0;
    exec = 0;
    lw=0;
  end
  
  if(opcode == `JR)
  begin
    dmem_wen = 1;
    rf_wen = 0;
    branch = 0;
    lhb_llb_con1 = 1;
    mem2reg=0;
    jal = 0;
    s5 = 0;
    s6 = 1;
    s7 = 0;
    jr = 1;
    exec = 0;
    lw=0;
  end
  if(opcode == `EXEC)
  begin
    dmem_wen = 1;
    rf_wen = 0;
    branch = 0;
    mem2reg=0;
    lhb_llb_con1 = 1;
    jal = 0;
    s5 = 0;
    s6 = 1;
    s7 = 0;
    jr = 0;
    exec = 1;
    lw=0;
  end

  
  if((opcode == `BR))
  begin






    
    s7 = 0;
    dmem_wen=1;
    rf_wen=0;
    branch=1;
    jal=0;
    jr = 0;
    mem2reg=0;

  end
end
endmodule
module control(
    opcode,


    dmem_wen,
    rf_wen,
    alu_op,
    alusrc,
    regdest,
    branch,
    mem2reg,
    lhb_llb_con1,
    s5,
    s6,
    s7,
    jal,
    jr,
    exec, 
    lw,

  );

 
 input[3:0] opcode;




 output reg dmem_wen;
 output reg rf_wen;
 output reg[2:0] alu_op;
 output reg alusrc;
 output reg regdest;
 output reg branch;
 output reg mem2reg;
 output reg lhb_llb_con1;
 output reg s5;
 output reg s6;
 output reg s7;
 output reg jal;
 output reg jr;
 output reg exec;
 output reg lw; 



always @ (*)
begin


  if ( (opcode==`ADD) || (opcode==`SUB) || (opcode==`AND) || (opcode==`OR) )
  begin
    dmem_wen=1;
    rf_wen=1;
    alu_op=opcode[2:0];
    alusrc=0;
    regdest=1;
    branch=0;
    mem2reg=0;
    lhb_llb_con1 = 0;
    s5 = 0;
    s6 = 1;
    s7 = 0;
    jal = 0; 
    jr = 0;
    exec = 0;
    lw=0;
  end
  if ( (opcode==`SLL) || (opcode==`SRL) || (opcode==`SRA) || (opcode==`RL) )
  begin
    dmem_wen=1;
    rf_wen=1;
    alu_op=opcode[2:0];
    alusrc=1;
    regdest=1;
    branch=0;
    mem2reg=0;
    lhb_llb_con1 = 0;
    s5 = 0;
    s6 = 1;
    s7 = 0;
    jal=0;
    jr = 0;
    exec = 0;
    lw=0;
  end
  if (opcode==`LW)
  begin
    dmem_wen=1;
    rf_wen=1;
    alu_op=3'b000;
    alusrc=1;
    regdest=1;
    branch=0;
    mem2reg=1;
    lhb_llb_con1 = 0;
    s5 = 0;
    s6 = 1;
    s7 = 0;
    jal=0;
    jr = 0;
    exec =0;
    lw=1;
  end
  if (opcode==`SW)
  begin
    dmem_wen=0;
    rf_wen=0;
    alu_op=3'b000;
    alusrc=1;
    regdest=0;
    branch=0;

    lhb_llb_con1 = 1;
    s5 = 0;
    s6 = 1;
    jal=0;
    jr = 0;
    exec = 0;
    lw=0;
    mem2reg=0;
  end
  if((opcode == `LHB)) 
  begin
    dmem_wen = 1;
    alu_op = 3'b010;
    rf_wen = 1;
    regdest = 1;
    branch = 0;
    lhb_llb_con1 = 1;
    mem2reg=0;
    alusrc = 0;
    s5 = 1;
    s6 = 0;
    s7 = 0;
    jal=0;
    jr = 0;
    exec = 0;
    lw=0;
  end
  if(opcode == `LLB)
  begin
    dmem_wen = 1;
    rf_wen = 1;
    regdest = 1;
    mem2reg=0;
    s7 = 1;
    branch = 0;
    jal=0;
    jr = 0;
    exec = 0;
    lw=0;
  end 
  if(opcode == `JAL)
  begin
    dmem_wen=1;
    rf_wen=1;
    alu_op=3'b000;


    branch=0;
    jal = 1;
    mem2reg=0;
    lhb_llb_con1 = 0;
    s5 = 0;
    s6 = 1;
    s7 = 0;
    jr = 0;
    exec = 0;
    lw=0;
  end
  
  if(opcode == `JR)
  begin
    dmem_wen = 1;
    rf_wen = 0;
    branch = 0;
    lhb_llb_con1 = 1;
    mem2reg=0;
    jal = 0;
    s5 = 0;
    s6 = 1;
    s7 = 0;
    jr = 1;
    exec = 0;
    lw=0;
  end
  if(opcode == `EXEC)
  begin
    dmem_wen = 1;
    rf_wen = 0;
    branch = 0;
    mem2reg=0;
    lhb_llb_con1 = 1;
    jal = 0;
    s5 = 0;
    s6 = 1;
    s7 = 0;
    jr = 0;
    exec = 1;
    lw=0;
  end

  
  if((opcode == `BR))
  begin






    
    s7 = 0;
    dmem_wen=1;
    rf_wen=0;
    branch=1;
    jal=0;
    jr = 0;
    mem2reg=0;

  end
end
endmodule