data/full_repos/permissive/146618947/sintestis_tarea5/mux.v
data/verilator_xmls/a23c055a-0777-414d-bb1e-9323b1967b5c.xml
module mux (
            input clk,
            input reset_L,
            input [3:0] data_0,
            input [3:0] data_1,
            output reg [3:0] data_out
            );

   reg                       selector;

   always @ (posedge clk)
     begin


        if (!reset_L) begin
           data_out <= 4'b0;
           selector <= 'b0;
        end

        if (reset_L) begin
           selector <= ~selector;
           if (selector) begin
              data_out <= data_0;

           end else begin
              data_out <= data_1;

           end
        end

     end

   endmodule
module mux (
            input clk,
            input reset_L,
            input [3:0] data_0,
            input [3:0] data_1,
            output reg [3:0] data_out
            );


   reg                       selector;

   always @ (posedge clk)
     begin


        if (!reset_L) begin
           data_out <= 4'b0;
           selector <= 'b0;
        end

        if (reset_L) begin
           selector <= ~selector;
           if (selector) begin
              data_out <= data_0;

           end else begin
              data_out <= data_1;

           end
        end

     end

   endmodule