data/full_repos/permissive/175261487/src/ps2.v
1: b"%Error: data/full_repos/permissive/175261487/src/ps2.v:41: Cannot find file containing module: 'ps2_tx'\n ps2_tx utx(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175261487/src,data/full_repos/permissive/175261487/ps2_tx\n             data/full_repos/permissive/175261487/src,data/full_repos/permissive/175261487/ps2_tx.v\n             data/full_repos/permissive/175261487/src,data/full_repos/permissive/175261487/ps2_tx.sv\n             ps2_tx\n             ps2_tx.v\n             ps2_tx.sv\n             obj_dir/ps2_tx\n             obj_dir/ps2_tx.v\n             obj_dir/ps2_tx.sv\n%Error: data/full_repos/permissive/175261487/src/ps2.v:58: Cannot find file containing module: 'ps2_rx'\n ps2_rx urx(\n ^~~~~~\n%Error: data/full_repos/permissive/175261487/src/ps2.v:72: Cannot find file containing module: 'ps2_decode'\n ps2_decode udecode(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/175261487/src/ps2.v:149: Cannot find file containing module: 'SB_IO'\n SB_IO #(\n ^~~~~\n%Error: data/full_repos/permissive/175261487/src/ps2.v:168: Cannot find file containing module: 'SB_IO'\n SB_IO #(\n ^~~~~\n%Error: Exiting due to 5 error(s)\n"
module ps2(
	input clk,
	input rst,
	input cs,
	input we,
	input [1:0] addr,
	input [7:0] din,
	output reg [7:0] dout,
	output [3:0] diag,
	inout ps2_clk,
	inout ps2_dat
);

	localparam PS2_CTRL = 2'd0;
	localparam PS2_DATA = 2'd1;
	localparam PS2_RSTA = 2'd2;
	localparam PS2_RDAT = 2'd3;


	wire ps2_clk_in, ps2_dat_in, clrerr;
	

	reg [2:0] clk_pipe, dat_pipe;
	reg ps2_clk_ena, ps2_clk_sync, ps2_dat_sync;
	always @(posedge clk)
	begin
		clk_pipe <= {clk_pipe[1:0], ps2_clk_in};
		dat_pipe <= {dat_pipe[1:0], ps2_dat_in};
		ps2_clk_ena <= clk_pipe[2] & !clk_pipe[1];
		ps2_clk_sync <= clk_pipe[2]; 
		ps2_dat_sync <= dat_pipe[2];
	end
	

	wire tx_active, tx_err, ps2_clk_oe, ps2_dat_oe;
	ps2_tx utx(
		.clk(clk),
		.rst(rst | clrerr),
		.tx_ena(cs & (addr == PS2_DATA) & we),
		.tx_data(din),
		.ps2_clk_ena(ps2_clk_ena),
		.ps2_clk_sync(ps2_clk_sync),
		.ps2_dat_sync(ps2_dat_sync),
		.tx_active(tx_active),
		.tx_err(tx_err),
		.ps2_clk_oe(ps2_clk_oe),
		.ps2_dat_oe(ps2_dat_oe)
	);
	

	wire [7:0] rx_code;
	wire rx_done, rx_frmerr, rx_parerr;
	ps2_rx urx(
		.clk(clk),
		.rst(rst | clrerr | tx_active),
		.ps2_clk_ena(ps2_clk_ena),
		.ps2_dat_sync(ps2_dat_sync),
		.rx_code(rx_code),
		.rx_done(rx_done),
		.rx_frmerr(rx_frmerr),
		.rx_parerr(rx_parerr)
	);
	

	wire [7:0] ascii;
	wire valid, caps_lock;
	ps2_decode udecode(
		.clk(clk),
		.rst(rst | clrerr),
		.ena(rx_done),
		.code(rx_code),
		.ascii(ascii),
		.valid(valid),
		.caps_lock(caps_lock)
	);
		

	reg [7:0] raw_data;
	reg raw_rdy;
	always @(posedge clk)
		if(rst | clrerr)
			raw_rdy <= 1'b0;
		else
		begin
			if(rx_done)
			begin
				raw_data <= rx_code;
				raw_rdy <= 1'b1;
			end
			else if(cs & !we & (addr == PS2_RDAT))
				raw_rdy <= 1'b0;
		end
		

	reg rx_rdy, rx_ovfl;
	always @(posedge clk)
		if(rst | clrerr)
		begin
			rx_rdy <= 1'b0;
			rx_ovfl <= 1'b0;
		end
		else if(valid)
		begin

			rx_rdy <= 1'b1;

			rx_ovfl <= rx_rdy;
		end
		else if(cs & !we & (addr == PS2_DATA))
		begin

			rx_rdy <= 1'b0;
		end
	

	reg cr;
	always @(posedge clk)
		if(rst)
			cr <= 1'b0;
		else if(cs & we & (addr == PS2_CTRL))
			cr <= din[0];
	assign clrerr = cr;
		

	always @(posedge clk)
		if(cs & !we)
			case(addr)
				PS2_CTRL: dout <= {
							1'b0,
							tx_err,
							~tx_active,
							caps_lock,
							rx_parerr,
							rx_frmerr,
							rx_ovfl,
							rx_rdy
						};
				PS2_DATA: dout <= ascii;
				PS2_RSTA: dout <= {7'h00,raw_rdy};
				PS2_RDAT: dout <= raw_data;
			endcase
	

	SB_IO #(
		.PIN_TYPE(6'b101001),
		.PULLUP(1'b0),
		.NEG_TRIGGER(1'b0),
		.IO_STANDARD("SB_LVCMOS")
	) uclk (
		.PACKAGE_PIN(ps2_clk),
		.LATCH_INPUT_VALUE(1'b0),
		.CLOCK_ENABLE(1'b0),
		.INPUT_CLK(1'b0),
		.OUTPUT_CLK(1'b0),
		.OUTPUT_ENABLE(ps2_clk_oe),
		.D_OUT_0(1'b0),
		.D_OUT_1(1'b0),
		.D_IN_0(ps2_clk_in),
		.D_IN_1()
	);


	SB_IO #(
		.PIN_TYPE(6'b101001),
		.PULLUP(1'b0),
		.NEG_TRIGGER(1'b0),
		.IO_STANDARD("SB_LVCMOS")
	) udat (
		.PACKAGE_PIN(ps2_dat),
		.LATCH_INPUT_VALUE(1'b0),
		.CLOCK_ENABLE(1'b0),
		.INPUT_CLK(1'b0),
		.OUTPUT_CLK(1'b0),
		.OUTPUT_ENABLE(ps2_dat_oe),
		.D_OUT_0(1'b0),
		.D_OUT_1(1'b0),
		.D_IN_0(ps2_dat_in),
		.D_IN_1()
	);


	assign diag = {ps2_dat_oe,ps2_clk_oe,tx_err,tx_active};
endmodule
module ps2(
	input clk,
	input rst,
	input cs,
	input we,
	input [1:0] addr,
	input [7:0] din,
	output reg [7:0] dout,
	output [3:0] diag,
	inout ps2_clk,
	inout ps2_dat
);


	localparam PS2_CTRL = 2'd0;
	localparam PS2_DATA = 2'd1;
	localparam PS2_RSTA = 2'd2;
	localparam PS2_RDAT = 2'd3;


	wire ps2_clk_in, ps2_dat_in, clrerr;
	

	reg [2:0] clk_pipe, dat_pipe;
	reg ps2_clk_ena, ps2_clk_sync, ps2_dat_sync;
	always @(posedge clk)
	begin
		clk_pipe <= {clk_pipe[1:0], ps2_clk_in};
		dat_pipe <= {dat_pipe[1:0], ps2_dat_in};
		ps2_clk_ena <= clk_pipe[2] & !clk_pipe[1];
		ps2_clk_sync <= clk_pipe[2]; 
		ps2_dat_sync <= dat_pipe[2];
	end
	

	wire tx_active, tx_err, ps2_clk_oe, ps2_dat_oe;
	ps2_tx utx(
		.clk(clk),
		.rst(rst | clrerr),
		.tx_ena(cs & (addr == PS2_DATA) & we),
		.tx_data(din),
		.ps2_clk_ena(ps2_clk_ena),
		.ps2_clk_sync(ps2_clk_sync),
		.ps2_dat_sync(ps2_dat_sync),
		.tx_active(tx_active),
		.tx_err(tx_err),
		.ps2_clk_oe(ps2_clk_oe),
		.ps2_dat_oe(ps2_dat_oe)
	);
	

	wire [7:0] rx_code;
	wire rx_done, rx_frmerr, rx_parerr;
	ps2_rx urx(
		.clk(clk),
		.rst(rst | clrerr | tx_active),
		.ps2_clk_ena(ps2_clk_ena),
		.ps2_dat_sync(ps2_dat_sync),
		.rx_code(rx_code),
		.rx_done(rx_done),
		.rx_frmerr(rx_frmerr),
		.rx_parerr(rx_parerr)
	);
	

	wire [7:0] ascii;
	wire valid, caps_lock;
	ps2_decode udecode(
		.clk(clk),
		.rst(rst | clrerr),
		.ena(rx_done),
		.code(rx_code),
		.ascii(ascii),
		.valid(valid),
		.caps_lock(caps_lock)
	);
		

	reg [7:0] raw_data;
	reg raw_rdy;
	always @(posedge clk)
		if(rst | clrerr)
			raw_rdy <= 1'b0;
		else
		begin
			if(rx_done)
			begin
				raw_data <= rx_code;
				raw_rdy <= 1'b1;
			end
			else if(cs & !we & (addr == PS2_RDAT))
				raw_rdy <= 1'b0;
		end
		

	reg rx_rdy, rx_ovfl;
	always @(posedge clk)
		if(rst | clrerr)
		begin
			rx_rdy <= 1'b0;
			rx_ovfl <= 1'b0;
		end
		else if(valid)
		begin

			rx_rdy <= 1'b1;

			rx_ovfl <= rx_rdy;
		end
		else if(cs & !we & (addr == PS2_DATA))
		begin

			rx_rdy <= 1'b0;
		end
	

	reg cr;
	always @(posedge clk)
		if(rst)
			cr <= 1'b0;
		else if(cs & we & (addr == PS2_CTRL))
			cr <= din[0];
	assign clrerr = cr;
		

	always @(posedge clk)
		if(cs & !we)
			case(addr)
				PS2_CTRL: dout <= {
							1'b0,
							tx_err,
							~tx_active,
							caps_lock,
							rx_parerr,
							rx_frmerr,
							rx_ovfl,
							rx_rdy
						};
				PS2_DATA: dout <= ascii;
				PS2_RSTA: dout <= {7'h00,raw_rdy};
				PS2_RDAT: dout <= raw_data;
			endcase
	

	SB_IO #(
		.PIN_TYPE(6'b101001),
		.PULLUP(1'b0),
		.NEG_TRIGGER(1'b0),
		.IO_STANDARD("SB_LVCMOS")
	) uclk (
		.PACKAGE_PIN(ps2_clk),
		.LATCH_INPUT_VALUE(1'b0),
		.CLOCK_ENABLE(1'b0),
		.INPUT_CLK(1'b0),
		.OUTPUT_CLK(1'b0),
		.OUTPUT_ENABLE(ps2_clk_oe),
		.D_OUT_0(1'b0),
		.D_OUT_1(1'b0),
		.D_IN_0(ps2_clk_in),
		.D_IN_1()
	);


	SB_IO #(
		.PIN_TYPE(6'b101001),
		.PULLUP(1'b0),
		.NEG_TRIGGER(1'b0),
		.IO_STANDARD("SB_LVCMOS")
	) udat (
		.PACKAGE_PIN(ps2_dat),
		.LATCH_INPUT_VALUE(1'b0),
		.CLOCK_ENABLE(1'b0),
		.INPUT_CLK(1'b0),
		.OUTPUT_CLK(1'b0),
		.OUTPUT_ENABLE(ps2_dat_oe),
		.D_OUT_0(1'b0),
		.D_OUT_1(1'b0),
		.D_IN_0(ps2_dat_in),
		.D_IN_1()
	);


	assign diag = {ps2_dat_oe,ps2_clk_oe,tx_err,tx_active};
endmodule