data/full_repos/permissive/129659500/PRBS_Gen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/129659500/PRBS_Gen.v:15: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                  : ... In instance PRBS_Gen\n  LFSR <= { LFSR[8-1:0], ~(LFSR[8-1] ^ LFSR[8/2-1]) } ;\n       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module PRBS_Gen (
	input 							Clock,
	input 							Reset,
	output reg [`OUTLENGTH-1:0]  	LFSR  
);


always @(posedge Clock or negedge Reset) begin 
	if(~Reset) begin
		LFSR <= 0;
	end else begin
		LFSR <= { LFSR[`OUTLENGTH-1:0], ~(LFSR[`OUTLENGTH-1] ^ LFSR[`OUTLENGTH/2-1]) } ;
		$display("Monitor %h",LFSR);

	end
end
endmodule
module PRBS_Gen (
	input 							Clock,
	input 							Reset,
	output reg [`OUTLENGTH-1:0]  	LFSR  
);



always @(posedge Clock or negedge Reset) begin 
	if(~Reset) begin
		LFSR <= 0;
	end else begin
		LFSR <= { LFSR[`OUTLENGTH-1:0], ~(LFSR[`OUTLENGTH-1] ^ LFSR[`OUTLENGTH/2-1]) } ;
		$display("Monitor %h",LFSR);

	end
end
endmodule