data/full_repos/permissive/217697217/problems/05_hex_counter/top.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/217697217/problems/05_hex_counter/top.v:20: Cannot find file containing module: 'clk_div'\n  clk_div #(.x(24)) div_for_counter(.clk(CLK),.clk_out(clk1));\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/217697217/problems/05_hex_counter,data/full_repos/permissive/217697217/clk_div\n             data/full_repos/permissive/217697217/problems/05_hex_counter,data/full_repos/permissive/217697217/clk_div.v\n             data/full_repos/permissive/217697217/problems/05_hex_counter,data/full_repos/permissive/217697217/clk_div.sv\n             clk_div\n             clk_div.v\n             clk_div.sv\n             obj_dir/clk_div\n             obj_dir/clk_div.v\n             obj_dir/clk_div.sv\n%Error: data/full_repos/permissive/217697217/problems/05_hex_counter/top.v:21: Cannot find file containing module: 'clk_div'\n  clk_div #(.x(16)) div_for_display(.clk(CLK),. clk_out(clk2));\n  ^~~~~~~\n%Error: data/full_repos/permissive/217697217/problems/05_hex_counter/top.v:22: Cannot find file containing module: 'counter'\n  counter #(.W(16))data_gen(.clk(clk1),.q(data));\n  ^~~~~~~\n%Error: data/full_repos/permissive/217697217/problems/05_hex_counter/top.v:23: Cannot find file containing module: 'hex_display'\n  hex_display display(.clk(clk2),.data(data),.anodes(anodes),.segments(segments));\n  ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module top(
    input CLK,

    output DS_EN1, DS_EN2, DS_EN3, DS_EN4,
    output DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G
);

wire [3:0]anodes;
assign {DS_EN1, DS_EN2, DS_EN3, DS_EN4} = ~anodes;

wire [6:0]segments;
assign {DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G} = segments;

wire [15:0]data;
wire clk1, clk2;


  clk_div #(.x(24)) div_for_counter(.clk(CLK),.clk_out(clk1));
  clk_div #(.x(16)) div_for_display(.clk(CLK),. clk_out(clk2));
  counter #(.W(16))data_gen(.clk(clk1),.q(data));
  hex_display display(.clk(clk2),.data(data),.anodes(anodes),.segments(segments));

endmodule
module top(
    input CLK,

    output DS_EN1, DS_EN2, DS_EN3, DS_EN4,
    output DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G
);


wire [3:0]anodes;
assign {DS_EN1, DS_EN2, DS_EN3, DS_EN4} = ~anodes;

wire [6:0]segments;
assign {DS_A, DS_B, DS_C, DS_D, DS_E, DS_F, DS_G} = segments;

wire [15:0]data;
wire clk1, clk2;


  clk_div #(.x(24)) div_for_counter(.clk(CLK),.clk_out(clk1));
  clk_div #(.x(16)) div_for_display(.clk(CLK),. clk_out(clk2));
  counter #(.W(16))data_gen(.clk(clk1),.q(data));
  hex_display display(.clk(clk2),.data(data),.anodes(anodes),.segments(segments));

endmodule