data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v
 line:150: before: "$"
1: b'%Error: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:8: Cannot find include file: hw1_A.v\n`include "hw1_A.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A,data/full_repos/permissive/18921956/hw1_A.v\n             data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A,data/full_repos/permissive/18921956/hw1_A.v.v\n             data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A,data/full_repos/permissive/18921956/hw1_A.v.sv\n             hw1_A.v\n             hw1_A.v.v\n             hw1_A.v.sv\n             obj_dir/hw1_A.v\n             obj_dir/hw1_A.v.v\n             obj_dir/hw1_A.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n #0 rst_n = 1\'b0; clk = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20 rst_n = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n #20 data = 16\'h1234;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n #20 control = 7\'b111_0010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n #20 data = 16\'h8888;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n #20 control = 7\'b111_0100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:63: Unsupported: Ignoring delay on this delayed statement.\n #20 control = 7\'b010_0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:70: Unsupported: Ignoring delay on this delayed statement.\n #20 control = 7\'b001_0010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:76: Unsupported: Ignoring delay on this delayed statement.\n #20 control = 7\'b100_0100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:82: Unsupported: Ignoring delay on this delayed statement.\n #20 control = 7\'b001_0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:88: Unsupported: Ignoring delay on this delayed statement.\n #20 control = 7\'b001_1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:94: Unsupported: Ignoring delay on this delayed statement.\n #20 control = 7\'b100_0001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:99: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:105: Unsupported: Ignoring delay on this delayed statement.\n #40 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:109: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:112: Unsupported or unknown PLI call: $fsdbDumpfile\n $fsdbDumpfile("hw1_A_testbench.fsdb");\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18921956/DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A_testbench.v:113: Unsupported or unknown PLI call: $fsdbDumpvars\n $fsdbDumpvars;\n ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 15 warning(s)\n'
module hw1_A_testbench ;

reg [15:0] data;
reg [6:0] control;
reg clk, rst_n;
wire [15:0] R0, R1, R2, R3;

hw1_A testA(data, 
			control, 
			clk, 
			rst_n, 
			R0, 
			R1, 
			R2, 
			R3);
			
initial begin
	#0 rst_n = 1'b0; clk = 1'b0;
	$display ("====================================================================");
	$display ("Simulate hw1_A");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);
	#20 rst_n = 1'b1;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 data = 16'h1234;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b111_0010;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 data = 16'h8888;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b111_0100;
	$display ("====================================================================");
	$display ("#### R1 = 0x1234");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b010_0000;
	$display ("====================================================================");
	$display ("#### R2 = 0x8888");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b001_0010;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b100_0100;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b001_0000;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b001_1000;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b100_0001;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);
	#20
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);
	$display ("====================================================================");
	#40 $finish;
end

always begin
	#10 clk = ~clk;
end
initial begin
	$fsdbDumpfile("hw1_A_testbench.fsdb");
	$fsdbDumpvars;
end

endmodule
module hw1_A_testbench ;


reg [15:0] data;
reg [6:0] control;
reg clk, rst_n;
wire [15:0] R0, R1, R2, R3;

hw1_A testA(data, 
			control, 
			clk, 
			rst_n, 
			R0, 
			R1, 
			R2, 
			R3);
			
initial begin
	#0 rst_n = 1'b0; clk = 1'b0;
	$display ("====================================================================");
	$display ("Simulate hw1_A");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);
	#20 rst_n = 1'b1;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 data = 16'h1234;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b111_0010;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 data = 16'h8888;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b111_0100;
	$display ("====================================================================");
	$display ("#### R1 = 0x1234");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b010_0000;
	$display ("====================================================================");
	$display ("#### R2 = 0x8888");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b001_0010;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b100_0100;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b001_0000;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b001_1000;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);

	#20 control = 7'b100_0001;
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);
	#20
	$display ("====================================================================");
	$display ("Time %t status", $time);
	$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
				rst_n, data, control, R0, R1, R2, R3);
	$display ("====================================================================");
	#40 $finish;
end

always begin
	#10 clk = ~clk;
end
initial begin
	$fsdbDumpfile("hw1_A_testbench.fsdb");
	$fsdbDumpvars;
end

endmodule