data/full_repos/permissive/129155059/proyecto-01/byte_joining/memoria.v
 line:9: before: "negedge"
data/verilator_xmls/eb9ad0d8-8730-4c45-a206-50b4fca9bad3.xml
module memTrans (dir, LE, dato);
  input [2:0] dir;
  input LE;
  inout [31:0] dato;
  reg [31:0] PwrCntr [5:0];

  assign dato = (LE)? PwrCntr[dir] : 32'bz;

  always @(dir or negedge LE or dato) begin
    if (~LE)
    PwrCntr[dir] = dato;
  end
endmodule
module memTrans (dir, LE, dato);

  input [2:0] dir;
  input LE;
  inout [31:0] dato;
  reg [31:0] PwrCntr [5:0];

  assign dato = (LE)? PwrCntr[dir] : 32'bz;

  always @(dir or negedge LE or dato) begin
    if (~LE)
    PwrCntr[dir] = dato;
  end
endmodule