data/full_repos/permissive/157608247/src/candy_pc.v
 line:133: before: "/"
1: b'%Error: data/full_repos/permissive/157608247/src/candy_pc.v:1: Cannot find include file: candy_defines.v\n`include "candy_defines.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157608247/src,data/full_repos/permissive/157608247/candy_defines.v\n             data/full_repos/permissive/157608247/src,data/full_repos/permissive/157608247/candy_defines.v.v\n             data/full_repos/permissive/157608247/src,data/full_repos/permissive/157608247/candy_defines.v.sv\n             candy_defines.v\n             candy_defines.v.v\n             candy_defines.v.sv\n             obj_dir/candy_defines.v\n             obj_dir/candy_defines.v.v\n             obj_dir/candy_defines.v.sv\n%Error: data/full_repos/permissive/157608247/src/candy_pc.v:8: Define or directive not defined: \'`SRAMAddrWidth\'\n    output reg [`SRAMAddrWidth] pc\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_pc.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    output reg [`SRAMAddrWidth] pc\n                              ^\n%Error: data/full_repos/permissive/157608247/src/candy_pc.v:12: Define or directive not defined: \'`RstEnable\'\n    if(rst == `RstEnable) begin\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/157608247/src/candy_pc.v:13: Define or directive not defined: \'`ZeroWord\'\n        pc <= `ZeroWord;\n              ^~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module candy_pc(
    input wire clk,
    input wire rst,

    input wire pc_enable,
    output reg [`SRAMAddrWidth] pc
);

always @(posedge clk) begin
    if(rst == `RstEnable) begin
        pc <= `ZeroWord;
    end
    else if(pc_enable) begin
        pc <= pc + 1'b1;
    end
end

endmodule
module candy_pc(
    input wire clk,
    input wire rst,

    input wire pc_enable,
    output reg [`SRAMAddrWidth] pc
);


always @(posedge clk) begin
    if(rst == `RstEnable) begin
        pc <= `ZeroWord;
    end
    else if(pc_enable) begin
        pc <= pc + 1'b1;
    end
end

endmodule