data/full_repos/permissive/157005262/verilog/spoilers/serial.v
1: b'%Warning-WIDTH: data/full_repos/permissive/157005262/verilog/spoilers/serial.v:16: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'counter\' generates 4 bits.\n                                                                                 : ... In instance serial\n    end else if (counter) begin\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module serial(input wire clk,
              input wire in,
              input wire [7:0] data,
              output wire ready,
              output wire out);

  reg [3:0] counter = 0;
  reg [7:0] shift = 0;
  assign ready = counter > 0;
  assign out = shift[7];

  always @(posedge clk) begin
    if (in) begin
      shift <= data;
      counter <= 8;
    end else if (counter) begin
      counter <= counter - 1;
      shift <= shift << 1;
    end
  end
endmodule
module serial(input wire clk,
              input wire in,
              input wire [7:0] data,
              output wire ready,
              output wire out);


  reg [3:0] counter = 0;
  reg [7:0] shift = 0;
  assign ready = counter > 0;
  assign out = shift[7];

  always @(posedge clk) begin
    if (in) begin
      shift <= data;
      counter <= 8;
    end else if (counter) begin
      counter <= counter - 1;
      shift <= shift << 1;
    end
  end
endmodule