data/full_repos/permissive/156609923/fifo/fifo.v
1: b'%Error: data/full_repos/permissive/156609923/fifo/fifo.v:1: Cannot find include file: memoria.v\n`include "memoria.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156609923/fifo,data/full_repos/permissive/156609923/memoria.v\n             data/full_repos/permissive/156609923/fifo,data/full_repos/permissive/156609923/memoria.v.v\n             data/full_repos/permissive/156609923/fifo,data/full_repos/permissive/156609923/memoria.v.sv\n             memoria.v\n             memoria.v.v\n             memoria.v.sv\n             obj_dir/memoria.v\n             obj_dir/memoria.v.v\n             obj_dir/memoria.v.sv\n%Error: Exiting due to 1 error(s)\n'
module fifo#(
		parameter BUS_SIZE = 5,
		parameter ADDR_WIDTH = 3,
		parameter MEM_LENGTH = 1 << ADDR_WIDTH
		
	) (
	input 		      clk,
	input 		      reset, 
	input 		      pop,
	input 		      push,
	input 		      valid,
	input [BUS_SIZE-1:0]  data_in,

	output 		      pause,
	output 		      continua,
	output 		      empty,
	output reg		      valid_out,
	output [BUS_SIZE-1:0] data_out

);

   reg [ADDR_WIDTH-1:0]       wr_ptr;
   reg [MEM_LENGTH-1:0]       valid_bus;
   wire[ADDR_WIDTH-1:0]  wr_add;
   reg [ADDR_WIDTH-1:0] 	  rd_ptr;
   wire	[ADDR_WIDTH:0]			 filled;
   
   wire 				  almost_full , almost_empty,write_en;
   wire [BUS_SIZE-1:0] 			  to_fifo;

   
 			  
   
   
   memoria channel(

	       .data_out		(data_out),

	
	       .clk			(clk),
	       .reset                   (reset),
	       .read			(pop),
	       .write			(write_en), 
	       .data_in			(to_fifo),
	       .addressR		(rd_ptr),
	       .addressW		(wr_add));
   
   
   always@(posedge clk)begin
      if (reset)begin
	 rd_ptr<=0;
	 wr_ptr<=0;
	 valid_out <= 0;
      end
      else begin
	 rd_ptr<= pop ? (rd_ptr == 3'b111 ? 0 : rd_ptr+1 ): rd_ptr;
	 
	 wr_ptr<= push ? (wr_ptr == 3'b111 ? 0 : wr_ptr+1) : wr_ptr;
	 
	 if (push)  valid_bus[wr_ptr] <= valid;
	 if (pop)   valid_out <= valid_bus[rd_ptr];
	 
      end
   end

   assign pause = almost_full ;
   assign continua = pause ? 0 : 1 ;
    
   assign filled = (rd_ptr > wr_ptr) ?	8-rd_ptr+wr_ptr : wr_ptr-rd_ptr;
   assign empty  = filled == 0 ? 1 :0 ;

   assign wr_add = pop ? rd_ptr : wr_ptr;
 
   assign almost_full = filled > 5 ? 1:0;

   assign almost_empty = filled < 3 ? 1:0;

   assign write_en = pop || push ? 1 : 0;

   assign to_fifo= push ? data_in : 'b0;
   
  
   
   endmodule
module fifo#(
		parameter BUS_SIZE = 5,
		parameter ADDR_WIDTH = 3,
		parameter MEM_LENGTH = 1 << ADDR_WIDTH
		
	) (
	input 		      clk,
	input 		      reset, 
	input 		      pop,
	input 		      push,
	input 		      valid,
	input [BUS_SIZE-1:0]  data_in,

	output 		      pause,
	output 		      continua,
	output 		      empty,
	output reg		      valid_out,
	output [BUS_SIZE-1:0] data_out

);


   reg [ADDR_WIDTH-1:0]       wr_ptr;
   reg [MEM_LENGTH-1:0]       valid_bus;
   wire[ADDR_WIDTH-1:0]  wr_add;
   reg [ADDR_WIDTH-1:0] 	  rd_ptr;
   wire	[ADDR_WIDTH:0]			 filled;
   
   wire 				  almost_full , almost_empty,write_en;
   wire [BUS_SIZE-1:0] 			  to_fifo;

   
 			  
   
   
   memoria channel(

	       .data_out		(data_out),

	
	       .clk			(clk),
	       .reset                   (reset),
	       .read			(pop),
	       .write			(write_en), 
	       .data_in			(to_fifo),
	       .addressR		(rd_ptr),
	       .addressW		(wr_add));
   
   
   always@(posedge clk)begin
      if (reset)begin
	 rd_ptr<=0;
	 wr_ptr<=0;
	 valid_out <= 0;
      end
      else begin
	 rd_ptr<= pop ? (rd_ptr == 3'b111 ? 0 : rd_ptr+1 ): rd_ptr;
	 
	 wr_ptr<= push ? (wr_ptr == 3'b111 ? 0 : wr_ptr+1) : wr_ptr;
	 
	 if (push)  valid_bus[wr_ptr] <= valid;
	 if (pop)   valid_out <= valid_bus[rd_ptr];
	 
      end
   end

   assign pause = almost_full ;
   assign continua = pause ? 0 : 1 ;
    
   assign filled = (rd_ptr > wr_ptr) ?	8-rd_ptr+wr_ptr : wr_ptr-rd_ptr;
   assign empty  = filled == 0 ? 1 :0 ;

   assign wr_add = pop ? rd_ptr : wr_ptr;
 
   assign almost_full = filled > 5 ? 1:0;

   assign almost_empty = filled < 3 ? 1:0;

   assign write_en = pop || push ? 1 : 0;

   assign to_fifo= push ? data_in : 'b0;
   
  
   
   endmodule