data/full_repos/permissive/134057391/tutorials/01-basics/testbench/example01_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/134057391/tutorials/01-basics/testbench/example01_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #100;                   \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/134057391/tutorials/01-basics/testbench/example01_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        a = 0; #100;            \n               ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/tutorials/01-basics/testbench/example01_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        b = 0; #100;            \n               ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/tutorials/01-basics/testbench/example01_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        b = 0; a = 1; #100;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/tutorials/01-basics/testbench/example01_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        b = 1; a = 0; #100;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/134057391/tutorials/01-basics/testbench/example01_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        b = 1; a = 1; #100;\n                      ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module example01_tb;


    reg a, b;


    wire a_and_b, a_or_b;


    and u1 ( a_and_b, a, b );
    or  u2 ( a_or_b,  a, b );

    initial begin
        #100;
        a = 0; #100;
        b = 0; #100;
        b = 0; a = 1; #100;
        b = 1; a = 0; #100;
        b = 1; a = 1; #100;
        $stop();
    end

endmodule
module example01_tb;



    reg a, b;


    wire a_and_b, a_or_b;


    and u1 ( a_and_b, a, b );
    or  u2 ( a_or_b,  a, b );

    initial begin
        #100;
        a = 0; #100;
        b = 0; #100;
        b = 0; a = 1; #100;
        b = 1; a = 0; #100;
        b = 1; a = 1; #100;
        $stop();
    end

endmodule