data/full_repos/permissive/174783592/FloatAdd/Shifters/rshifter.v
 line:2 column:2: Illegal character '\x00'
1: b'%Error: data/full_repos/permissive/174783592/FloatAdd/Shifters/rshifter.v:2: Cannot find include file: Shifters/Mux2x1.v\n`include "Shifters/Mux2x1.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174783592/FloatAdd/Shifters,data/full_repos/permissive/174783592/Shifters/Mux2x1.v\n             data/full_repos/permissive/174783592/FloatAdd/Shifters,data/full_repos/permissive/174783592/Shifters/Mux2x1.v.v\n             data/full_repos/permissive/174783592/FloatAdd/Shifters,data/full_repos/permissive/174783592/Shifters/Mux2x1.v.sv\n             Shifters/Mux2x1.v\n             Shifters/Mux2x1.v.v\n             Shifters/Mux2x1.v.sv\n             obj_dir/Shifters/Mux2x1.v\n             obj_dir/Shifters/Mux2x1.v.v\n             obj_dir/Shifters/Mux2x1.v.sv\n%Error: Exiting due to 1 error(s)\n'
module rshifter(in,sel,out);

	input [10:0] in;

	input [3:0] sel;
        output  [10:0] out;

	wire [10:0] l1;
	wire [10:0] l2;
	wire [10:0] l3; 
	wire  [10:0] shifted;

	parameter zero = 1'b0;





	generate
		genvar i;
		for(i=0;i<10;i=i+1)
		begin

			Mux2x1 ml0(in[i+1],in[i],sel[0],l1[i]);
		end
	endgenerate
	
			Mux2x1 m00(zero,in[10],sel[0],l1[10]);
	
	generate
		genvar j;
		for(j=0;j<9;j=j+1)
		begin

			Mux2x1 ml1(l1[j+2],l1[j],sel[1],l2[j]);
		end
	endgenerate

 			Mux2x1 m10(zero,l1[10],sel[1],l2[10]);
			Mux2x1 m11(zero,l1[9],sel[1],l2[9]);
			
	generate

		for(j=0;j<7;j=j+1)
		begin

			Mux2x1 ml2(l2[j+4],l2[j],sel[2],l3[j]);
		end
	endgenerate

	generate
		genvar k;
		for(k=0;k<4;k=k+1)
		begin

			Mux2x1 ml2(zero,l2[k+7],sel[2],l3[k+7]);
		end
	endgenerate

			
	generate

		for(j=0;j<3;j=j+1)
		begin

			Mux2x1 ml2(l3[j+8],l3[j],sel[3],shifted[j]);
		end
	endgenerate

	generate

		for(k=0;k<8;k=k+1)
		begin

			Mux2x1 ml2(zero,l3[k+3],sel[3],shifted[k+3]);
		end
	endgenerate




		assign	out = shifted;

	
endmodule
module rshifter(in,sel,out);


	input [10:0] in;

	input [3:0] sel;
        output  [10:0] out;

	wire [10:0] l1;
	wire [10:0] l2;
	wire [10:0] l3; 
	wire  [10:0] shifted;

	parameter zero = 1'b0;





	generate
		genvar i;
		for(i=0;i<10;i=i+1)
		begin

			Mux2x1 ml0(in[i+1],in[i],sel[0],l1[i]);
		end
	endgenerate
	
			Mux2x1 m00(zero,in[10],sel[0],l1[10]);
	
	generate
		genvar j;
		for(j=0;j<9;j=j+1)
		begin

			Mux2x1 ml1(l1[j+2],l1[j],sel[1],l2[j]);
		end
	endgenerate

 			Mux2x1 m10(zero,l1[10],sel[1],l2[10]);
			Mux2x1 m11(zero,l1[9],sel[1],l2[9]);
			
	generate

		for(j=0;j<7;j=j+1)
		begin

			Mux2x1 ml2(l2[j+4],l2[j],sel[2],l3[j]);
		end
	endgenerate

	generate
		genvar k;
		for(k=0;k<4;k=k+1)
		begin

			Mux2x1 ml2(zero,l2[k+7],sel[2],l3[k+7]);
		end
	endgenerate

			
	generate

		for(j=0;j<3;j=j+1)
		begin

			Mux2x1 ml2(l3[j+8],l3[j],sel[3],shifted[j]);
		end
	endgenerate

	generate

		for(k=0;k<8;k=k+1)
		begin

			Mux2x1 ml2(zero,l3[k+3],sel[3],shifted[k+3]);
		end
	endgenerate




		assign	out = shifted;

	
endmodule