data/full_repos/permissive/157101210/alu.v
data/verilator_xmls/37bfacbe-b9ac-4c25-bf23-ddd091e41228.xml
module AdderAndSubtractor
(
    output res, 
    output carryout,
    input a, 
    input b, 
    input isSubtract,
    input carryin
);
    wire BxorSub;
    wire xAorB;
    wire AandB;
    wire xAorBandCin;
    xor  xorgate(BxorSub, b, isSubtract);
    xor  xorgate(xAorB, a, BxorSub);
    xor  xorgate(res, xAorB, carryin);
    and  andgate(AandB, a, BxorSub);
    and  andgate(xAorBandCin, xAorB, carryin);
    or   orgate(carryout, AandB, xAorBandCin);
endmodule
module AdderAndSubtractor
(
    output res, 
    output carryout,
    input a, 
    input b, 
    input isSubtract,
    input carryin
);

    wire BxorSub;
    wire xAorB;
    wire AandB;
    wire xAorBandCin;
    xor  xorgate(BxorSub, b, isSubtract);
    xor  xorgate(xAorB, a, BxorSub);
    xor  xorgate(res, xAorB, carryin);
    and  andgate(AandB, a, BxorSub);
    and  andgate(xAorBandCin, xAorB, carryin);
    or   orgate(carryout, AandB, xAorBandCin);
endmodule