data/full_repos/permissive/167746421/pe_core/genesis/test_debug_reg.svp
 line:2: before: "parameter"
1: b"%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_debug_reg.svp:1: Define or directive not defined: '`mname'\nmodule  `mname`  #(\n        ^~~~~~\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_debug_reg.svp:1: syntax error, unexpected $undefined, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule  `mname`  #(\n              ^\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_debug_reg.svp:3: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_debug_reg.svp:12: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output [31:0]          read_data\n  ^~~~~~\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_debug_reg.svp:17: syntax error, unexpected always_ff\nalways_ff @(posedge cfg_clk or negedge cfg_rst_n) begin\n^~~~~~~~~\n%Error: data/full_repos/permissive/167746421/pe_core/genesis/test_debug_reg.svp:29: syntax error, unexpected assign\nassign nc_cfg_d = cfg_d;\n^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module  `mname`  #(
  parameter DataWidth = 16
) (
  input                  cfg_clk,
  input                  cfg_rst_n,
  input  [DataWidth-1:0] cfg_d,
  input                  cfg_en,

  input  [DataWidth-1:0] data_in,

  output logic           debug_irq,
  output [31:0]          read_data
);

logic [DataWidth-1:0] debug_val;

always_ff @(posedge cfg_clk or negedge cfg_rst_n) begin
  if(~cfg_rst_n) begin
    debug_val <= {DataWidth{1'b0}};
  end else if(cfg_en) begin
    debug_val <= cfg_d[DataWidth-1:0];
  end
end

assign read_data = debug_val;
assign debug_irq = (data_in != debug_val);

logic [15:0] nc_cfg_d;
assign nc_cfg_d = cfg_d;

endmodule
module  `mname`  #(
  parameter DataWidth = 16
) (
  input                  cfg_clk,
  input                  cfg_rst_n,
  input  [DataWidth-1:0] cfg_d,
  input                  cfg_en,

  input  [DataWidth-1:0] data_in,

  output logic           debug_irq,
  output [31:0]          read_data
);


logic [DataWidth-1:0] debug_val;

always_ff @(posedge cfg_clk or negedge cfg_rst_n) begin
  if(~cfg_rst_n) begin
    debug_val <= {DataWidth{1'b0}};
  end else if(cfg_en) begin
    debug_val <= cfg_d[DataWidth-1:0];
  end
end

assign read_data = debug_val;
assign debug_irq = (data_in != debug_val);

logic [15:0] nc_cfg_d;
assign nc_cfg_d = cfg_d;

endmodule