data/full_repos/permissive/205673649/UART/Simulacion/tb_interfaz_tx.v
 line:59: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_interfaz_tx.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #0\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_interfaz_tx.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #2  rst = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_interfaz_tx.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10  done_alu =1\'b1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_interfaz_tx.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #2 done_alu =1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_interfaz_tx.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10 done_tx = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_interfaz_tx.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #2 done_tx =1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_interfaz_tx.v:55: Unsupported: Ignoring delay on this delayed statement.\n   #10  done_alu =1\'b1; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_interfaz_tx.v:57: Unsupported: Ignoring delay on this delayed statement.\n   #2 done_alu =1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_interfaz_tx.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #1000 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/205673649/UART/Simulacion/tb_interfaz_tx.v:62: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/205673649/UART/Simulacion/tb_interfaz_tx.v:64: Cannot find file containing module: \'interfaz_tx\'\n    interfaz_tx  \n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/interfaz_tx\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/interfaz_tx.v\n             data/full_repos/permissive/205673649/UART/Simulacion,data/full_repos/permissive/205673649/interfaz_tx.sv\n             interfaz_tx\n             interfaz_tx.v\n             interfaz_tx.sv\n             obj_dir/interfaz_tx\n             obj_dir/interfaz_tx.v\n             obj_dir/interfaz_tx.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_interfaz_tx();


localparam  NB_DBIT_01    =  8;


reg  clk;
reg  rst;
reg [NB_DBIT_01-1:0] resultado;
reg done_alu;
reg done_tx;


wire  signed       [NB_DBIT_01-1:0]        o_data;
wire tx_start;

initial begin
  #0
  rst = 1'b0;
  clk = 1'b0;
  done_alu = 1'b0;
  done_tx = 1'b0;
  resultado = 8'b0;
   
  #2  rst = 1'b1;
  #10  done_alu =1'b1; 
  resultado= 8'b00000100;
  #2 done_alu =1'b0;
  
  #10 done_tx = 1'b1;
  #2 done_tx =1'b0;
  
   #10  done_alu =1'b1; 
   resultado= 8'b00000110;
   #2 done_alu =1'b0;
  
  #1000 $finish;
end

always #1 clk = ~clk;

    interfaz_tx  
    #(.NB_DATA           (NB_DBIT_01))
    u_interfaz_01
    (
      .i_clk (clk),
      .i_rst (rst),
      .i_resultado (resultado),
      .i_done_alu (done_alu),
      .i_done_tx(done_tx),
      .o_data (o_data),
      .o_int_tx (tx_start)
    );


endmodule
module tb_interfaz_tx();



localparam  NB_DBIT_01    =  8;


reg  clk;
reg  rst;
reg [NB_DBIT_01-1:0] resultado;
reg done_alu;
reg done_tx;


wire  signed       [NB_DBIT_01-1:0]        o_data;
wire tx_start;

initial begin
  #0
  rst = 1'b0;
  clk = 1'b0;
  done_alu = 1'b0;
  done_tx = 1'b0;
  resultado = 8'b0;
   
  #2  rst = 1'b1;
  #10  done_alu =1'b1; 
  resultado= 8'b00000100;
  #2 done_alu =1'b0;
  
  #10 done_tx = 1'b1;
  #2 done_tx =1'b0;
  
   #10  done_alu =1'b1; 
   resultado= 8'b00000110;
   #2 done_alu =1'b0;
  
  #1000 $finish;
end

always #1 clk = ~clk;

    interfaz_tx  
    #(.NB_DATA           (NB_DBIT_01))
    u_interfaz_01
    (
      .i_clk (clk),
      .i_rst (rst),
      .i_resultado (resultado),
      .i_done_alu (done_alu),
      .i_done_tx(done_tx),
      .o_data (o_data),
      .o_int_tx (tx_start)
    );


endmodule