data/full_repos/permissive/154352170/Control.v
data/verilator_xmls/c77982b4-eab5-4625-831a-5088134dc8fd.xml
module Control(
    input [31:0] IR_In,
    output reg RegWrite,
    output reg MemToReg,
    output reg MemWrite,
    output reg [2:0] ALUOp,
    output reg ALUSrcA,
	 output reg ALUSrcB,
    output reg RegDst,
    output reg Branch,
	 output reg [1:0] Jump,
	 output reg [2:0] EXTOp
    );
	 
	 wire [5:0] Op;
	 wire [5:0] Func;
	 
	 assign Op = IR_In[31:26];
	 assign Func = IR_In[5:0];
	 
	 initial begin
	    RegWrite <= 0;
		 MemToReg <= 0;
		 MemWrite <= 0;
		 ALUOp <= 3'b000;
		 ALUSrcA <= 0;
		 ALUSrcB <= 0;
		 RegDst <= 0;
		 Branch <= 0;
		 Jump <= 2'b00;
		 EXTOp <= 3'b000;
	 end
	 
	 always @ (*) begin
	    
		 if(Op == 6'b000000) begin
		 
		    if(Func == 6'b100001) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 1;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b000;
			 end
			 
			 if(Func == 6'b100011) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b001;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 1;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b000;
			 end
			 
			 if(Func == 6'b001000) begin
			    RegWrite <= 0;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b100;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 0;
		       Branch <= 1;
				 Jump <= 2'b10;
				 EXTOp <= 3'b000;
			 end
			 
			 if(Func == 6'b000000) begin
			    RegWrite <= 0;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 0;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b000;
			 end
			 
		 end
		 
		 else begin
		    
			 if(Op == 6'b001101) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b010;
		       ALUSrcA <= 0;
		       ALUSrcB <= 1;
		       RegDst <= 0;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b000;
			 end
			 
			 if(Op == 6'b100011) begin
			    RegWrite <= 1;
		       MemToReg <= 1;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 1;
		       RegDst <= 0;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b011;
			 end
			 
			 if(Op == 6'b101011) begin
			    RegWrite <= 0;
		       MemToReg <= 0;
		       MemWrite <= 1;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 1;
		       RegDst <= 0;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b011;
			 end
			 
			 if(Op == 6'b000100) begin
			    RegWrite <= 0;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 0;
		       Branch <= 1;
				 Jump <= 2'b00;
				 EXTOp <= 3'b010;
			 end
			 
			 if(Op == 6'b001111) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b011;
		       ALUSrcA <= 0;
		       ALUSrcB <= 1;
		       RegDst <= 0;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b001;
			 end
			 
			 if(Op == 6'b000010) begin
			    RegWrite <= 0;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 0;
		       Branch <= 1;
				 Jump <= 2'b01;
				 EXTOp <= 3'b100;
			 end
			 
			 if(Op == 6'b000011) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 0;
		       Branch <= 1;
				 Jump <= 2'b01;
				 EXTOp <= 3'b100;
			 end
			 
			 if(Op == 6'b111111) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 1;
		       Branch <= 1;
				 Jump <= 2'b11;
				 EXTOp <= 3'b000;
			 end
			 
			 if(Op == 6'b011111) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b101;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 1;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b000;
			 end

       end
    
	 end
	 
endmodule
module Control(
    input [31:0] IR_In,
    output reg RegWrite,
    output reg MemToReg,
    output reg MemWrite,
    output reg [2:0] ALUOp,
    output reg ALUSrcA,
	 output reg ALUSrcB,
    output reg RegDst,
    output reg Branch,
	 output reg [1:0] Jump,
	 output reg [2:0] EXTOp
    );

	 
	 wire [5:0] Op;
	 wire [5:0] Func;
	 
	 assign Op = IR_In[31:26];
	 assign Func = IR_In[5:0];
	 
	 initial begin
	    RegWrite <= 0;
		 MemToReg <= 0;
		 MemWrite <= 0;
		 ALUOp <= 3'b000;
		 ALUSrcA <= 0;
		 ALUSrcB <= 0;
		 RegDst <= 0;
		 Branch <= 0;
		 Jump <= 2'b00;
		 EXTOp <= 3'b000;
	 end
	 
	 always @ (*) begin
	    
		 if(Op == 6'b000000) begin
		 
		    if(Func == 6'b100001) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 1;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b000;
			 end
			 
			 if(Func == 6'b100011) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b001;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 1;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b000;
			 end
			 
			 if(Func == 6'b001000) begin
			    RegWrite <= 0;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b100;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 0;
		       Branch <= 1;
				 Jump <= 2'b10;
				 EXTOp <= 3'b000;
			 end
			 
			 if(Func == 6'b000000) begin
			    RegWrite <= 0;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 0;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b000;
			 end
			 
		 end
		 
		 else begin
		    
			 if(Op == 6'b001101) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b010;
		       ALUSrcA <= 0;
		       ALUSrcB <= 1;
		       RegDst <= 0;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b000;
			 end
			 
			 if(Op == 6'b100011) begin
			    RegWrite <= 1;
		       MemToReg <= 1;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 1;
		       RegDst <= 0;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b011;
			 end
			 
			 if(Op == 6'b101011) begin
			    RegWrite <= 0;
		       MemToReg <= 0;
		       MemWrite <= 1;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 1;
		       RegDst <= 0;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b011;
			 end
			 
			 if(Op == 6'b000100) begin
			    RegWrite <= 0;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 0;
		       Branch <= 1;
				 Jump <= 2'b00;
				 EXTOp <= 3'b010;
			 end
			 
			 if(Op == 6'b001111) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b011;
		       ALUSrcA <= 0;
		       ALUSrcB <= 1;
		       RegDst <= 0;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b001;
			 end
			 
			 if(Op == 6'b000010) begin
			    RegWrite <= 0;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 0;
		       Branch <= 1;
				 Jump <= 2'b01;
				 EXTOp <= 3'b100;
			 end
			 
			 if(Op == 6'b000011) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 0;
		       Branch <= 1;
				 Jump <= 2'b01;
				 EXTOp <= 3'b100;
			 end
			 
			 if(Op == 6'b111111) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b000;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 1;
		       Branch <= 1;
				 Jump <= 2'b11;
				 EXTOp <= 3'b000;
			 end
			 
			 if(Op == 6'b011111) begin
			    RegWrite <= 1;
		       MemToReg <= 0;
		       MemWrite <= 0;
		       ALUOp <= 3'b101;
		       ALUSrcA <= 0;
		       ALUSrcB <= 0;
		       RegDst <= 1;
		       Branch <= 0;
				 Jump <= 2'b00;
				 EXTOp <= 3'b000;
			 end

       end
    
	 end
	 
endmodule