data/full_repos/permissive/172995952/src/random_num_gen.v
data/verilator_xmls/b259b1c4-1240-4abd-9fa1-951f433f16a6.xml
module random_num_gen(
        input RESET,
        input CLK,
        input TARGET_REACHED,
        output reg [7:0] TARGET_ADDR_H,
        output reg [6:0] TARGET_ADDR_V
    );
    
    wire R_INPUT_1 = (LFSR_1[3] ~^ (LFSR_1[4] ~^ (LFSR_1[5] ~^ LFSR_1[7])));
    wire R_INPUT_2 = LFSR_2[6] ~^ LFSR_2[5];
    
    reg [7:0] LFSR_1;
    reg [6:0] LFSR_2;
   





    initial begin
    LFSR_1 = 8'b0001000;
    TARGET_ADDR_H = 8'b01010000;
    end
    
    initial begin
    LFSR_2 = 7'b0001000;
    TARGET_ADDR_V = 7'b0111100;
    end
    



    
    always@(posedge CLK) begin
        if(RESET)
        LFSR_1 <= 8'b00000000;
        else begin
        LFSR_1[7] <= LFSR_1[6];
        LFSR_1[6] <= LFSR_1[5];
        LFSR_1[5] <= LFSR_1[4];
        LFSR_1[4] <= LFSR_1[3];
        LFSR_1[3] <= LFSR_1[2];
        LFSR_1[2] <= LFSR_1[1];
        LFSR_1[1] <= LFSR_1[0];
        LFSR_1[0] <= R_INPUT_1;
        end
    end    
    


    
    always@(posedge CLK) begin
        if(RESET) 
        LFSR_2 <= 7'b0000000;
        
        else begin
        LFSR_2[6] <= LFSR_2[5];
        LFSR_2[5] <= LFSR_2[4];
        LFSR_2[4] <= LFSR_2[3];
        LFSR_2[3] <= LFSR_2[2];
        LFSR_2[2] <= LFSR_2[1];
        LFSR_2[1] <= LFSR_2[0];
        LFSR_2[0] <= R_INPUT_2;
        end
     end
 




 
     always@(posedge CLK) begin
        if (TARGET_REACHED) begin
            if (LFSR_1 < 160)
            TARGET_ADDR_H <= LFSR_1;
            else
            TARGET_ADDR_H <= 80;
            
            if(LFSR_2 < 120)
            TARGET_ADDR_V <= LFSR_2;
            else 
            TARGET_ADDR_V <= 60;
            end
        else if(RESET) begin
            TARGET_ADDR_H <= 80;
            TARGET_ADDR_V <= 60;
            end
     end
     
    
endmodule
module random_num_gen(
        input RESET,
        input CLK,
        input TARGET_REACHED,
        output reg [7:0] TARGET_ADDR_H,
        output reg [6:0] TARGET_ADDR_V
    );

    
    wire R_INPUT_1 = (LFSR_1[3] ~^ (LFSR_1[4] ~^ (LFSR_1[5] ~^ LFSR_1[7])));
    wire R_INPUT_2 = LFSR_2[6] ~^ LFSR_2[5];
    
    reg [7:0] LFSR_1;
    reg [6:0] LFSR_2;
   





    initial begin
    LFSR_1 = 8'b0001000;
    TARGET_ADDR_H = 8'b01010000;
    end
    
    initial begin
    LFSR_2 = 7'b0001000;
    TARGET_ADDR_V = 7'b0111100;
    end
    



    
    always@(posedge CLK) begin
        if(RESET)
        LFSR_1 <= 8'b00000000;
        else begin
        LFSR_1[7] <= LFSR_1[6];
        LFSR_1[6] <= LFSR_1[5];
        LFSR_1[5] <= LFSR_1[4];
        LFSR_1[4] <= LFSR_1[3];
        LFSR_1[3] <= LFSR_1[2];
        LFSR_1[2] <= LFSR_1[1];
        LFSR_1[1] <= LFSR_1[0];
        LFSR_1[0] <= R_INPUT_1;
        end
    end    
    


    
    always@(posedge CLK) begin
        if(RESET) 
        LFSR_2 <= 7'b0000000;
        
        else begin
        LFSR_2[6] <= LFSR_2[5];
        LFSR_2[5] <= LFSR_2[4];
        LFSR_2[4] <= LFSR_2[3];
        LFSR_2[3] <= LFSR_2[2];
        LFSR_2[2] <= LFSR_2[1];
        LFSR_2[1] <= LFSR_2[0];
        LFSR_2[0] <= R_INPUT_2;
        end
     end
 




 
     always@(posedge CLK) begin
        if (TARGET_REACHED) begin
            if (LFSR_1 < 160)
            TARGET_ADDR_H <= LFSR_1;
            else
            TARGET_ADDR_H <= 80;
            
            if(LFSR_2 < 120)
            TARGET_ADDR_V <= LFSR_2;
            else 
            TARGET_ADDR_V <= 60;
            end
        else if(RESET) begin
            TARGET_ADDR_H <= 80;
            TARGET_ADDR_V <= 60;
            end
     end
     
    
endmodule