data/full_repos/permissive/170402453/SubClock.v
 line:210: before: "/"
data/verilator_xmls/32ad43e6-73da-4251-bcfe-d21da3b190a9.xml
module SubClock(
		input CLK,
		output OUTCLK
    );
	 
	 parameter Divider = 1;

	 integer wait1;
	 reg CLK_;
	 
	 assign OUTCLK = CLK_;
	 

	 initial begin
		wait1 = 0;
		CLK_ = 0;
	 end
	 
	 always @(posedge CLK) begin

		if(wait1 >= (Divider/2)) begin
			wait1 = 0;
			CLK_ = ~CLK_;
		end
		
		wait1 = wait1+1;
	 end
endmodule
module SubClock(
		input CLK,
		output OUTCLK
    );

	 
	 parameter Divider = 1;

	 integer wait1;
	 reg CLK_;
	 
	 assign OUTCLK = CLK_;
	 

	 initial begin
		wait1 = 0;
		CLK_ = 0;
	 end
	 
	 always @(posedge CLK) begin

		if(wait1 >= (Divider/2)) begin
			wait1 = 0;
			CLK_ = ~CLK_;
		end
		
		wait1 = wait1+1;
	 end
endmodule