data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v
1: b'%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:131: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_IDLE\' generates 2 bits.\n                                                                                       : ... In instance eth_tx_fifo_wraper\n      eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;\n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:152: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_DATA_AVAIL\' generates 2 bits.\n                                                                                       : ... In instance eth_tx_fifo_wraper\n            eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_DATA_AVAIL;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:160: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_PULL_PKT\' generates 2 bits.\n                                                                                       : ... In instance eth_tx_fifo_wraper\n       eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_PULL_PKT;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:168: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_WAIT3\' generates 2 bits.\n                                                                                       : ... In instance eth_tx_fifo_wraper\n         eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_WAIT3;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:171: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_PULL_PKT\' generates 2 bits.\n                                                                                       : ... In instance eth_tx_fifo_wraper\n         eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_PULL_PKT;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:179: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_IDLE\' generates 2 bits.\n                                                                                       : ... In instance eth_tx_fifo_wraper\n       eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:184: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'TX_CTRL_FSM_IDLE\' generates 2 bits.\n                                                                                       : ... In instance eth_tx_fifo_wraper\n       eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:143: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'TX_CTRL_FSM_IDLE\' generates 2 bits.\n                                                                                       : ... In instance eth_tx_fifo_wraper\n   case (eth_txfifo_ctrl_fsm)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:143: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'TX_CTRL_FSM_DATA_AVAIL\' generates 2 bits.\n                                                                                       : ... In instance eth_tx_fifo_wraper\n   case (eth_txfifo_ctrl_fsm)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:143: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'TX_CTRL_FSM_PULL_PKT\' generates 2 bits.\n                                                                                       : ... In instance eth_tx_fifo_wraper\n   case (eth_txfifo_ctrl_fsm)\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:143: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'TX_CTRL_FSM_WAIT3\' generates 2 bits.\n                                                                                       : ... In instance eth_tx_fifo_wraper\n   case (eth_txfifo_ctrl_fsm)\n   ^~~~\n%Error: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:197: Cannot find file containing module: \'async_fifo\'\n  async_fifo #(16, 10)\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/115771353/rtl/hworb,data/full_repos/permissive/115771353/async_fifo\n             data/full_repos/permissive/115771353/rtl/hworb,data/full_repos/permissive/115771353/async_fifo.v\n             data/full_repos/permissive/115771353/rtl/hworb,data/full_repos/permissive/115771353/async_fifo.sv\n             async_fifo\n             async_fifo.v\n             async_fifo.sv\n             obj_dir/async_fifo\n             obj_dir/async_fifo.v\n             obj_dir/async_fifo.sv\n%Error: data/full_repos/permissive/115771353/rtl/hworb/eth_tx_fifo_wraper.v:215: Cannot find file containing module: \'async_fifo\'\n  async_fifo #(16, 10)\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 11 warning(s)\n'
module eth_tx_fifo_wraper
(
  input              clk_i,
  input              reset_n,
  input              clk_en,
  input [15:0]       tx_len_fifo_data,
  input [7:0]        tx_data_fifo_data,

  input              tx_len_fifo_write,
  input              tx_data_fifo_write,

  input              tx_macread,
  input              txmac_clk,


  output reg         tx_fifoempty,
  output wire [7:0]  tx_fifodata,
  output reg         tx_fifoeof
);



  reg [15:0]  tx_len_fifo_data_1d;
  reg [7:0]   tx_data_fifo_data_1d;
  reg         tx_len_fifo_write_1d;
  reg         tx_data_fifo_write_1d;
  reg         mac_rd_tx_len_fifo;
  reg [15:0]  byte_cnt;
  reg         load_cnt;
  reg [2:0]   eth_txfifo_ctrl_fsm;

  wire        mac_rd_tx_data_fifo;

  wire [7:0]  tx_fifo_data;
  wire [15:0] tx_fifo_len;
  reg  [15:0] tx_fifo_len_minus1;

  wire        mac_rd_tx_len_fifo_x;
  wire        mac_rd_tx_data_fifo_x;

  wire        tx_len_fifo_empty;

  wire        tx_data_fifo_full;
  wire        tx_data_fifo_empty;  



  parameter [1:0]
	TX_CTRL_FSM_IDLE    	= 2'd0,
	TX_CTRL_FSM_DATA_AVAIL  = 2'd1,
	TX_CTRL_FSM_PULL_PKT   	= 2'd2,
	TX_CTRL_FSM_WAIT3   	= 2'd3;


  assign mac_rd_tx_data_fifo = tx_macread;

  assign mac_rd_tx_len_fifo_x = mac_rd_tx_len_fifo & clk_en;
  assign mac_rd_tx_data_fifo_x = (mac_rd_tx_data_fifo) & clk_en;
   


  always @(posedge clk_i or negedge reset_n) 
  begin
    if (!reset_n) begin
      tx_len_fifo_data_1d   <= 16'h0000;
      tx_data_fifo_data_1d  <= 8'h00;
      tx_len_fifo_write_1d  <= 1'b0;
      tx_data_fifo_write_1d <= 1'b0;
    end
    else begin
      tx_len_fifo_data_1d   <= tx_len_fifo_data;
      tx_data_fifo_data_1d  <= tx_data_fifo_data;
      tx_len_fifo_write_1d  <= tx_len_fifo_write;
      tx_data_fifo_write_1d <= tx_data_fifo_write;
    end
  end

  assign tx_fifodata[7:0] = tx_fifo_data[7:0];
  


  always @(posedge txmac_clk or negedge reset_n) 
  begin
    if (!reset_n) begin
      byte_cnt <= 16'd0;
    end
	else if (clk_en) begin
      if (load_cnt) begin
        byte_cnt <= tx_fifo_len_minus1[15:0];
      end
      else if (tx_macread) begin
        byte_cnt <= byte_cnt - 1;
      end
	end
  end

  always @(posedge txmac_clk or negedge reset_n) 
  begin
    if (!reset_n) begin
      tx_fifo_len_minus1 <= 16'd0;
    end
	else if (clk_en) begin
	  tx_fifo_len_minus1 <= (tx_fifo_len - 1);
	end
  end
   


  always @(posedge txmac_clk or negedge reset_n) 
  begin
    if (!reset_n) begin
      eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;
      tx_fifoempty <= 1'b1;
      load_cnt <= 1'b0;
      tx_fifoeof <= 1'b0;
      mac_rd_tx_len_fifo <= 1'b0;
    end
    else if (clk_en) begin

	  load_cnt <= 1'b0;
	  tx_fifoeof <= 1'b0;
	  mac_rd_tx_len_fifo <= 1'b0;

	  case (eth_txfifo_ctrl_fsm)

	    TX_CTRL_FSM_IDLE:
	    begin
	      tx_fifoempty <= 1'b1;

	      if (!tx_len_fifo_empty) begin
	        mac_rd_tx_len_fifo <= 1'b1;
	      load_cnt <= 1'b1;
            eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_DATA_AVAIL;
	        
	      end
	    end
				 
	    TX_CTRL_FSM_DATA_AVAIL:
	    begin
	      tx_fifoempty <= 1'b0;
	      eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_PULL_PKT;
	    end
				 
	    TX_CTRL_FSM_PULL_PKT:
	    begin
	      if (byte_cnt == 16'd0) begin
	        tx_fifoeof <= 1'b1;
	        tx_fifoempty <= 1'b1;
	        eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_WAIT3;
	      end
	      else begin
	        eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_PULL_PKT;

	      end
	    end
				 
	    TX_CTRL_FSM_WAIT3:
	    begin

	      eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;
	    end
				 
	    default:
	    begin
	      eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;
	      tx_fifoempty <= 1'b1;
	      load_cnt <= 1'b0;
	      tx_fifoeof <= 1'b0;
	      mac_rd_tx_len_fifo <= 1'b0;
	    end
	  endcase 
	end
  end

 


  async_fifo #(16, 10)
  u_tx_len_fifo
  (
    .wclk(clk_i),
    .wrst_n(reset_n),
    .winc(tx_len_fifo_write_1d),
    .wdata(tx_len_fifo_data_1d),
    .wfull(),
    
    .rclk(txmac_clk),
    .rrst_n(reset_n),
    .rinc(mac_rd_tx_len_fifo_x),
    .rdata(tx_fifo_len[15:0]),
    .rempty(tx_len_fifo_empty)
  );



  async_fifo #(16, 10)
  u_tx_data_fifo
  (
    .wclk(clk_i),
    .wrst_n(reset_n),
    .winc(tx_data_fifo_write_1d),
    .wdata(tx_data_fifo_data_1d),
    .wfull(tx_data_fifo_full),
    
    .rclk(txmac_clk),
    .rrst_n(reset_n),
    .rinc(mac_rd_tx_data_fifo_x),
    .rdata(tx_fifo_data[7:0]),
    .rempty(tx_data_fifo_empty)
  );

endmodule
module eth_tx_fifo_wraper
(
  input              clk_i,
  input              reset_n,
  input              clk_en,
  input [15:0]       tx_len_fifo_data,
  input [7:0]        tx_data_fifo_data,

  input              tx_len_fifo_write,
  input              tx_data_fifo_write,

  input              tx_macread,
  input              txmac_clk,


  output reg         tx_fifoempty,
  output wire [7:0]  tx_fifodata,
  output reg         tx_fifoeof
);




  reg [15:0]  tx_len_fifo_data_1d;
  reg [7:0]   tx_data_fifo_data_1d;
  reg         tx_len_fifo_write_1d;
  reg         tx_data_fifo_write_1d;
  reg         mac_rd_tx_len_fifo;
  reg [15:0]  byte_cnt;
  reg         load_cnt;
  reg [2:0]   eth_txfifo_ctrl_fsm;

  wire        mac_rd_tx_data_fifo;

  wire [7:0]  tx_fifo_data;
  wire [15:0] tx_fifo_len;
  reg  [15:0] tx_fifo_len_minus1;

  wire        mac_rd_tx_len_fifo_x;
  wire        mac_rd_tx_data_fifo_x;

  wire        tx_len_fifo_empty;

  wire        tx_data_fifo_full;
  wire        tx_data_fifo_empty;  



  parameter [1:0]
	TX_CTRL_FSM_IDLE    	= 2'd0,
	TX_CTRL_FSM_DATA_AVAIL  = 2'd1,
	TX_CTRL_FSM_PULL_PKT   	= 2'd2,
	TX_CTRL_FSM_WAIT3   	= 2'd3;


  assign mac_rd_tx_data_fifo = tx_macread;

  assign mac_rd_tx_len_fifo_x = mac_rd_tx_len_fifo & clk_en;
  assign mac_rd_tx_data_fifo_x = (mac_rd_tx_data_fifo) & clk_en;
   


  always @(posedge clk_i or negedge reset_n) 
  begin
    if (!reset_n) begin
      tx_len_fifo_data_1d   <= 16'h0000;
      tx_data_fifo_data_1d  <= 8'h00;
      tx_len_fifo_write_1d  <= 1'b0;
      tx_data_fifo_write_1d <= 1'b0;
    end
    else begin
      tx_len_fifo_data_1d   <= tx_len_fifo_data;
      tx_data_fifo_data_1d  <= tx_data_fifo_data;
      tx_len_fifo_write_1d  <= tx_len_fifo_write;
      tx_data_fifo_write_1d <= tx_data_fifo_write;
    end
  end

  assign tx_fifodata[7:0] = tx_fifo_data[7:0];
  


  always @(posedge txmac_clk or negedge reset_n) 
  begin
    if (!reset_n) begin
      byte_cnt <= 16'd0;
    end
	else if (clk_en) begin
      if (load_cnt) begin
        byte_cnt <= tx_fifo_len_minus1[15:0];
      end
      else if (tx_macread) begin
        byte_cnt <= byte_cnt - 1;
      end
	end
  end

  always @(posedge txmac_clk or negedge reset_n) 
  begin
    if (!reset_n) begin
      tx_fifo_len_minus1 <= 16'd0;
    end
	else if (clk_en) begin
	  tx_fifo_len_minus1 <= (tx_fifo_len - 1);
	end
  end
   


  always @(posedge txmac_clk or negedge reset_n) 
  begin
    if (!reset_n) begin
      eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;
      tx_fifoempty <= 1'b1;
      load_cnt <= 1'b0;
      tx_fifoeof <= 1'b0;
      mac_rd_tx_len_fifo <= 1'b0;
    end
    else if (clk_en) begin

	  load_cnt <= 1'b0;
	  tx_fifoeof <= 1'b0;
	  mac_rd_tx_len_fifo <= 1'b0;

	  case (eth_txfifo_ctrl_fsm)

	    TX_CTRL_FSM_IDLE:
	    begin
	      tx_fifoempty <= 1'b1;

	      if (!tx_len_fifo_empty) begin
	        mac_rd_tx_len_fifo <= 1'b1;
	      load_cnt <= 1'b1;
            eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_DATA_AVAIL;
	        
	      end
	    end
				 
	    TX_CTRL_FSM_DATA_AVAIL:
	    begin
	      tx_fifoempty <= 1'b0;
	      eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_PULL_PKT;
	    end
				 
	    TX_CTRL_FSM_PULL_PKT:
	    begin
	      if (byte_cnt == 16'd0) begin
	        tx_fifoeof <= 1'b1;
	        tx_fifoempty <= 1'b1;
	        eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_WAIT3;
	      end
	      else begin
	        eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_PULL_PKT;

	      end
	    end
				 
	    TX_CTRL_FSM_WAIT3:
	    begin

	      eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;
	    end
				 
	    default:
	    begin
	      eth_txfifo_ctrl_fsm <= TX_CTRL_FSM_IDLE;
	      tx_fifoempty <= 1'b1;
	      load_cnt <= 1'b0;
	      tx_fifoeof <= 1'b0;
	      mac_rd_tx_len_fifo <= 1'b0;
	    end
	  endcase 
	end
  end

 


  async_fifo #(16, 10)
  u_tx_len_fifo
  (
    .wclk(clk_i),
    .wrst_n(reset_n),
    .winc(tx_len_fifo_write_1d),
    .wdata(tx_len_fifo_data_1d),
    .wfull(),
    
    .rclk(txmac_clk),
    .rrst_n(reset_n),
    .rinc(mac_rd_tx_len_fifo_x),
    .rdata(tx_fifo_len[15:0]),
    .rempty(tx_len_fifo_empty)
  );



  async_fifo #(16, 10)
  u_tx_data_fifo
  (
    .wclk(clk_i),
    .wrst_n(reset_n),
    .winc(tx_data_fifo_write_1d),
    .wdata(tx_data_fifo_data_1d),
    .wfull(tx_data_fifo_full),
    
    .rclk(txmac_clk),
    .rrst_n(reset_n),
    .rinc(mac_rd_tx_data_fifo_x),
    .rdata(tx_fifo_data[7:0]),
    .rempty(tx_data_fifo_empty)
  );

endmodule