data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v
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1: b'%Warning-IMPLICIT: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:138: Signal definition not found, creating implicitly: \'a\'\n assign a = (counter<<1);\n        ^\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:53: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'countertmp1\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign counter = countertmp1;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:55: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[0][0] = 16\'b0000000001011010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:56: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[0][1] = 16\'b0000000001011010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:57: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[0][2] = 16\'b0000000001011010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:58: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[0][3] = 16\'b0000000001011010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:59: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[0][4] = 16\'b0000000001011010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:60: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[0][5] = 16\'b0000000001011010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:61: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[0][7] = 16\'b0000000001011010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:62: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[0][6] = 16\'b0000000001011010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:64: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h7d\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[1][0] = 16\'b0000000001111101;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:65: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h6a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[1][1] = 16\'b0000000001101010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:66: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h47\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[1][2] = 16\'b0000000001000111;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:67: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h18\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[1][3] = 16\'b0000000000011000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:68: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffe7\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[1][4] = 16\'b1111111111100111;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:69: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffb8\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[1][5] = 16\'b1111111110111000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:70: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hff82\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[1][7] = 16\'b1111111110000010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:71: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hff95\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[1][6] = 16\'b1111111110010101;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:73: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h76\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[2][0] = 16\'b0000000001110110;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:74: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h30\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[2][1] = 16\'b0000000000110000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:75: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffcf\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[2][2] = 16\'b1111111111001111;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:76: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hff89\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[2][3] = 16\'b1111111110001001;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:77: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hff89\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[2][4] = 16\'b1111111110001001;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:78: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffcf\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[2][5] = 16\'b1111111111001111;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:79: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h76\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[2][7] = 16\'b0000000001110110;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:80: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h30\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[2][6] = 16\'b0000000000110000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:82: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h6a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[3][0] = 16\'b0000000001101010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:83: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffe7\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[3][1] = 16\'b1111111111100111;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:84: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hff82\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[3][2] = 16\'b1111111110000010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:85: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffb8\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[3][3] = 16\'b1111111110111000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:86: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h47\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[3][4] = 16\'b0000000001000111;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:87: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h7d\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[3][5] = 16\'b0000000001111101;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:88: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h6a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[3][7] = 16\'b0000000001101010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:89: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h18\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[3][6] = 16\'b0000000000011000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:92: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[4][0] = 16\'b0000000001011010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:93: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffa5\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[4][1] = 16\'b1111111110100101;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:94: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffa5\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[4][2] = 16\'b1111111110100101;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:95: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[4][3] = 16\'b0000000001011010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:96: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[4][4] = 16\'b0000000001011010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:97: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffa5\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[4][5] = 16\'b1111111110100101;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:98: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffa5\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[4][6] = 16\'b1111111110100101;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:99: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5a\' generates 16 bits.\n                                                                                                          : ... In instance Matrix_Multiplier1_8X8\n assign D[4][7] = 16\'b0000000001011010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:101: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h47\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[5][0] = 16\'b0000000001000111;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:102: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hff82\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[5][1] = 16\'b1111111110000010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:103: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h18\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[5][2] = 16\'b0000000000011000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:104: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h6a\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[5][3] = 16\'b0000000001101010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:105: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hff95\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[5][4] = 16\'b1111111110010101;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:106: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffe7\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[5][5] = 16\'b1111111111100111;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:107: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h7d\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[5][6] = 16\'b0000000001111101;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:108: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffb8\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[5][7] = 16\'b1111111110111000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:110: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h30\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[6][0] = 16\'b0000000000110000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:111: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hff89\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[6][1] = 16\'b1111111110001001;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:112: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h76\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[6][2] = 16\'b0000000001110110;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:113: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffcf\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[6][3] = 16\'b1111111111001111;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:114: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffcf\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[6][4] = 16\'b1111111111001111;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:115: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h76\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[6][5] = 16\'b0000000001110110;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:116: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hff89\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[6][6] = 16\'b1111111110001001;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:117: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h30\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[6][7] = 16\'b0000000000110000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:119: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h18\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[7][0] = 16\'b0000000000011000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:120: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffb8\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[7][1] = 16\'b1111111110111000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:121: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h6a\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[7][2] = 16\'b0000000001101010;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:122: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hfb18\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[7][3] = 16\'b1111101100011000;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:123: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h7d\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[7][4] = 16\'b0000000001111101;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:124: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hff95\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[7][5] = 16\'b1111111110010101;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:125: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h47\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[7][6] = 16\'b0000000001000111;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:126: Operator ASSIGNW expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'hffe7\' generates 16 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign D[7][7] = 16\'b1111111111100111;\n                ^\n%Error: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:129: Cannot find file containing module: \'IMG_ROM\'\n IMG_ROM IMG (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/IMG_ROM\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/IMG_ROM.v\n             data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG,data/full_repos/permissive/212390735/IMG_ROM.sv\n             IMG_ROM\n             IMG_ROM.v\n             IMG_ROM.sv\n             obj_dir/IMG_ROM\n             obj_dir/IMG_ROM.v\n             obj_dir/IMG_ROM.sv\n%Warning-WIDTH: data/full_repos/permissive/212390735/IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v:138: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTL generates 4 bits.\n                                                                                                           : ... In instance Matrix_Multiplier1_8X8\n assign a = (counter<<1);\n          ^\n%Error: Exiting due to 1 error(s), 67 warning(s)\n'
module Matrix_Multiplier1_8X8(





	 output reg [31:0] DIMGtmp0,
	 output reg [31:0] DIMGtmp1,
	 output reg [31:0] DIMGtmp2,
	 output reg [31:0] DIMGtmp3,
	 output reg [31:0] DIMGtmp4,
	 output reg [31:0] DIMGtmp5,
	 output reg [31:0] DIMGtmp6,
	 output reg [31:0] DIMGtmp7,
	 output [3:0] counter,
	 output [15:0] IMG_add_a,
	 input clk
	 );
	 
	wire [15:0]  IMG_add_b;
	reg [15:0] tmp[7:0];

	wire [7:0] IMGouta, IMGoutb;
	wire [16:0] D[7:0][7:0];
	reg[15:0]  countertmp1 = 0, counter1 = 0, counter2 = 1;




	
	assign IMG_add_a = counter1;
	assign IMG_add_b = counter2;
	assign counter = countertmp1;
	
	assign D[0][0] = 16'b0000000001011010;
	assign D[0][1] = 16'b0000000001011010;
	assign D[0][2] = 16'b0000000001011010;
	assign D[0][3] = 16'b0000000001011010;
	assign D[0][4] = 16'b0000000001011010;
	assign D[0][5] = 16'b0000000001011010;
	assign D[0][7] = 16'b0000000001011010;
	assign D[0][6] = 16'b0000000001011010;

	assign D[1][0] = 16'b0000000001111101;
	assign D[1][1] = 16'b0000000001101010;
	assign D[1][2] = 16'b0000000001000111;
	assign D[1][3] = 16'b0000000000011000;
	assign D[1][4] = 16'b1111111111100111;
	assign D[1][5] = 16'b1111111110111000;
	assign D[1][7] = 16'b1111111110000010;
	assign D[1][6] = 16'b1111111110010101;

	assign D[2][0] = 16'b0000000001110110;
	assign D[2][1] = 16'b0000000000110000;
	assign D[2][2] = 16'b1111111111001111;
	assign D[2][3] = 16'b1111111110001001;
	assign D[2][4] = 16'b1111111110001001;
	assign D[2][5] = 16'b1111111111001111;
	assign D[2][7] = 16'b0000000001110110;
	assign D[2][6] = 16'b0000000000110000;

	assign D[3][0] = 16'b0000000001101010;
	assign D[3][1] = 16'b1111111111100111;
	assign D[3][2] = 16'b1111111110000010;
	assign D[3][3] = 16'b1111111110111000;
	assign D[3][4] = 16'b0000000001000111;
	assign D[3][5] = 16'b0000000001111101;
	assign D[3][7] = 16'b0000000001101010;
	assign D[3][6] = 16'b0000000000011000;

	
	assign D[4][0] = 16'b0000000001011010;
	assign D[4][1] = 16'b1111111110100101;
	assign D[4][2] = 16'b1111111110100101;
	assign D[4][3] = 16'b0000000001011010;
	assign D[4][4] = 16'b0000000001011010;
	assign D[4][5] = 16'b1111111110100101;
	assign D[4][6] = 16'b1111111110100101;
	assign D[4][7] = 16'b0000000001011010;

	assign D[5][0] = 16'b0000000001000111;
	assign D[5][1] = 16'b1111111110000010;
	assign D[5][2] = 16'b0000000000011000;
	assign D[5][3] = 16'b0000000001101010;
	assign D[5][4] = 16'b1111111110010101;
	assign D[5][5] = 16'b1111111111100111;
	assign D[5][6] = 16'b0000000001111101;
	assign D[5][7] = 16'b1111111110111000;

	assign D[6][0] = 16'b0000000000110000;
	assign D[6][1] = 16'b1111111110001001;
	assign D[6][2] = 16'b0000000001110110;
	assign D[6][3] = 16'b1111111111001111;
	assign D[6][4] = 16'b1111111111001111;
	assign D[6][5] = 16'b0000000001110110;
	assign D[6][6] = 16'b1111111110001001;
	assign D[6][7] = 16'b0000000000110000;

	assign D[7][0] = 16'b0000000000011000;
	assign D[7][1] = 16'b1111111110111000;
	assign D[7][2] = 16'b0000000001101010;
	assign D[7][3] = 16'b1111101100011000;
	assign D[7][4] = 16'b0000000001111101;
	assign D[7][5] = 16'b1111111110010101;
	assign D[7][6] = 16'b0000000001000111;
	assign D[7][7] = 16'b1111111111100111;


	IMG_ROM IMG (
	  .clka(clk),
	  .addra(IMG_add_a),
	  .douta(IMGouta),
	  .clkb(clk),
	  .addrb(IMG_add_b),
	  .doutb(IMGoutb)
	);	
	
	assign a = (counter<<1);

	



	
	always@(posedge clk)
	begin
			if((counter<<1) - 2 >= 0)
			begin
				tmp[(counter<<1) - 2] = {IMGouta, 8'b0000_0000};
				tmp[(counter<<1) - 1] = {IMGoutb, 8'h00};
			end
			if(counter == 4)
			begin
				DIMGtmp0 = (tmp[0] * D[0][0]) + (tmp[1] * D[1][0]) + (tmp[2] * D[2][0]) + (tmp[3] * D[3][0])
							+ (tmp[4] * D[4][0]) + (tmp[5] * D[5][0]) + (tmp[6] * D[6][0]) + (tmp[7] * D[7][0]);
				DIMGtmp1 = (tmp[0] * D[0][1]) + (tmp[1] * D[1][1]) + (tmp[2] * D[2][1]) + (tmp[3] * D[3][1])
							+ (tmp[4] * D[4][1]) + (tmp[5] * D[5][1]) + (tmp[6] * D[6][1]) + (tmp[7] * D[7][1]);
				DIMGtmp2 = (tmp[0] * D[0][2]) + (tmp[1] * D[1][2]) + (tmp[2] * D[2][2]) + (tmp[3] * D[3][2])
							+ (tmp[4] * D[4][2]) + (tmp[5] * D[5][2]) + (tmp[6] * D[6][2]) + (tmp[7] * D[7][2]);
				DIMGtmp3 = (tmp[0] * D[0][3]) + (tmp[1] * D[1][3]) + (tmp[2] * D[2][3]) + (tmp[3] * D[3][3])
							+ (tmp[4] * D[4][3]) + (tmp[5] * D[5][3]) + (tmp[6] * D[6][3]) + (tmp[7] * D[7][3]);
				DIMGtmp4 = (tmp[0] * D[0][4]) + (tmp[1] * D[1][4]) + (tmp[2] * D[2][4]) + (tmp[3] * D[3][4])
							+ (tmp[4] * D[4][4]) + (tmp[5] * D[5][4]) + (tmp[6] * D[6][4]) + (tmp[7] * D[7][4]);
				DIMGtmp5 = (tmp[0] * D[0][5]) + (tmp[1] * D[1][5]) + (tmp[2] * D[2][5]) + (tmp[3] * D[3][5])
							+ (tmp[4] * D[4][5]) + (tmp[5] * D[5][5]) + (tmp[6] * D[6][5]) + (tmp[7] * D[7][5]);
				DIMGtmp6 = (tmp[0] * D[0][6]) + (tmp[1] * D[1][6]) + (tmp[2] * D[2][6]) + (tmp[3] * D[3][6])
							+ (tmp[4] * D[4][6]) + (tmp[5] * D[5][6]) + (tmp[6] * D[6][6]) + (tmp[7] * D[7][6]);
				DIMGtmp7 = (tmp[0] * D[0][7]) + (tmp[1] * D[1][7]) + (tmp[2] * D[2][7]) + (tmp[3] * D[3][7])
							+ (tmp[4] * D[4][7]) + (tmp[5] * D[5][7]) + (tmp[6] * D[6][7]) + (tmp[7] * D[7][7]);









			end

			if(countertmp1 < 4)
			begin
				
				counter1 <= counter1 + 2;
				counter2 <= counter2 + 2;
				countertmp1 <= countertmp1 + 1;
			end
			
			if(countertmp1 == 4)
			begin
				
				countertmp1 <= 0;
			end

	
	end






endmodule
module Matrix_Multiplier1_8X8(





	 output reg [31:0] DIMGtmp0,
	 output reg [31:0] DIMGtmp1,
	 output reg [31:0] DIMGtmp2,
	 output reg [31:0] DIMGtmp3,
	 output reg [31:0] DIMGtmp4,
	 output reg [31:0] DIMGtmp5,
	 output reg [31:0] DIMGtmp6,
	 output reg [31:0] DIMGtmp7,
	 output [3:0] counter,
	 output [15:0] IMG_add_a,
	 input clk
	 );

	 
	wire [15:0]  IMG_add_b;
	reg [15:0] tmp[7:0];

	wire [7:0] IMGouta, IMGoutb;
	wire [16:0] D[7:0][7:0];
	reg[15:0]  countertmp1 = 0, counter1 = 0, counter2 = 1;




	
	assign IMG_add_a = counter1;
	assign IMG_add_b = counter2;
	assign counter = countertmp1;
	
	assign D[0][0] = 16'b0000000001011010;
	assign D[0][1] = 16'b0000000001011010;
	assign D[0][2] = 16'b0000000001011010;
	assign D[0][3] = 16'b0000000001011010;
	assign D[0][4] = 16'b0000000001011010;
	assign D[0][5] = 16'b0000000001011010;
	assign D[0][7] = 16'b0000000001011010;
	assign D[0][6] = 16'b0000000001011010;

	assign D[1][0] = 16'b0000000001111101;
	assign D[1][1] = 16'b0000000001101010;
	assign D[1][2] = 16'b0000000001000111;
	assign D[1][3] = 16'b0000000000011000;
	assign D[1][4] = 16'b1111111111100111;
	assign D[1][5] = 16'b1111111110111000;
	assign D[1][7] = 16'b1111111110000010;
	assign D[1][6] = 16'b1111111110010101;

	assign D[2][0] = 16'b0000000001110110;
	assign D[2][1] = 16'b0000000000110000;
	assign D[2][2] = 16'b1111111111001111;
	assign D[2][3] = 16'b1111111110001001;
	assign D[2][4] = 16'b1111111110001001;
	assign D[2][5] = 16'b1111111111001111;
	assign D[2][7] = 16'b0000000001110110;
	assign D[2][6] = 16'b0000000000110000;

	assign D[3][0] = 16'b0000000001101010;
	assign D[3][1] = 16'b1111111111100111;
	assign D[3][2] = 16'b1111111110000010;
	assign D[3][3] = 16'b1111111110111000;
	assign D[3][4] = 16'b0000000001000111;
	assign D[3][5] = 16'b0000000001111101;
	assign D[3][7] = 16'b0000000001101010;
	assign D[3][6] = 16'b0000000000011000;

	
	assign D[4][0] = 16'b0000000001011010;
	assign D[4][1] = 16'b1111111110100101;
	assign D[4][2] = 16'b1111111110100101;
	assign D[4][3] = 16'b0000000001011010;
	assign D[4][4] = 16'b0000000001011010;
	assign D[4][5] = 16'b1111111110100101;
	assign D[4][6] = 16'b1111111110100101;
	assign D[4][7] = 16'b0000000001011010;

	assign D[5][0] = 16'b0000000001000111;
	assign D[5][1] = 16'b1111111110000010;
	assign D[5][2] = 16'b0000000000011000;
	assign D[5][3] = 16'b0000000001101010;
	assign D[5][4] = 16'b1111111110010101;
	assign D[5][5] = 16'b1111111111100111;
	assign D[5][6] = 16'b0000000001111101;
	assign D[5][7] = 16'b1111111110111000;

	assign D[6][0] = 16'b0000000000110000;
	assign D[6][1] = 16'b1111111110001001;
	assign D[6][2] = 16'b0000000001110110;
	assign D[6][3] = 16'b1111111111001111;
	assign D[6][4] = 16'b1111111111001111;
	assign D[6][5] = 16'b0000000001110110;
	assign D[6][6] = 16'b1111111110001001;
	assign D[6][7] = 16'b0000000000110000;

	assign D[7][0] = 16'b0000000000011000;
	assign D[7][1] = 16'b1111111110111000;
	assign D[7][2] = 16'b0000000001101010;
	assign D[7][3] = 16'b1111101100011000;
	assign D[7][4] = 16'b0000000001111101;
	assign D[7][5] = 16'b1111111110010101;
	assign D[7][6] = 16'b0000000001000111;
	assign D[7][7] = 16'b1111111111100111;


	IMG_ROM IMG (
	  .clka(clk),
	  .addra(IMG_add_a),
	  .douta(IMGouta),
	  .clkb(clk),
	  .addrb(IMG_add_b),
	  .doutb(IMGoutb)
	);	
	
	assign a = (counter<<1);

	



	
	always@(posedge clk)
	begin
			if((counter<<1) - 2 >= 0)
			begin
				tmp[(counter<<1) - 2] = {IMGouta, 8'b0000_0000};
				tmp[(counter<<1) - 1] = {IMGoutb, 8'h00};
			end
			if(counter == 4)
			begin
				DIMGtmp0 = (tmp[0] * D[0][0]) + (tmp[1] * D[1][0]) + (tmp[2] * D[2][0]) + (tmp[3] * D[3][0])
							+ (tmp[4] * D[4][0]) + (tmp[5] * D[5][0]) + (tmp[6] * D[6][0]) + (tmp[7] * D[7][0]);
				DIMGtmp1 = (tmp[0] * D[0][1]) + (tmp[1] * D[1][1]) + (tmp[2] * D[2][1]) + (tmp[3] * D[3][1])
							+ (tmp[4] * D[4][1]) + (tmp[5] * D[5][1]) + (tmp[6] * D[6][1]) + (tmp[7] * D[7][1]);
				DIMGtmp2 = (tmp[0] * D[0][2]) + (tmp[1] * D[1][2]) + (tmp[2] * D[2][2]) + (tmp[3] * D[3][2])
							+ (tmp[4] * D[4][2]) + (tmp[5] * D[5][2]) + (tmp[6] * D[6][2]) + (tmp[7] * D[7][2]);
				DIMGtmp3 = (tmp[0] * D[0][3]) + (tmp[1] * D[1][3]) + (tmp[2] * D[2][3]) + (tmp[3] * D[3][3])
							+ (tmp[4] * D[4][3]) + (tmp[5] * D[5][3]) + (tmp[6] * D[6][3]) + (tmp[7] * D[7][3]);
				DIMGtmp4 = (tmp[0] * D[0][4]) + (tmp[1] * D[1][4]) + (tmp[2] * D[2][4]) + (tmp[3] * D[3][4])
							+ (tmp[4] * D[4][4]) + (tmp[5] * D[5][4]) + (tmp[6] * D[6][4]) + (tmp[7] * D[7][4]);
				DIMGtmp5 = (tmp[0] * D[0][5]) + (tmp[1] * D[1][5]) + (tmp[2] * D[2][5]) + (tmp[3] * D[3][5])
							+ (tmp[4] * D[4][5]) + (tmp[5] * D[5][5]) + (tmp[6] * D[6][5]) + (tmp[7] * D[7][5]);
				DIMGtmp6 = (tmp[0] * D[0][6]) + (tmp[1] * D[1][6]) + (tmp[2] * D[2][6]) + (tmp[3] * D[3][6])
							+ (tmp[4] * D[4][6]) + (tmp[5] * D[5][6]) + (tmp[6] * D[6][6]) + (tmp[7] * D[7][6]);
				DIMGtmp7 = (tmp[0] * D[0][7]) + (tmp[1] * D[1][7]) + (tmp[2] * D[2][7]) + (tmp[3] * D[3][7])
							+ (tmp[4] * D[4][7]) + (tmp[5] * D[5][7]) + (tmp[6] * D[6][7]) + (tmp[7] * D[7][7]);









			end

			if(countertmp1 < 4)
			begin
				
				counter1 <= counter1 + 2;
				counter2 <= counter2 + 2;
				countertmp1 <= countertmp1 + 1;
			end
			
			if(countertmp1 == 4)
			begin
				
				countertmp1 <= 0;
			end

	
	end






endmodule