data/full_repos/permissive/131921633/tv/Util/Counter/counter.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.v:1: Cannot find include file: Util/Math.v\n`include "Util/Math.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Util/Counter,data/full_repos/permissive/131921633/Util/Math.v\n             data/full_repos/permissive/131921633/tv/Util/Counter,data/full_repos/permissive/131921633/Util/Math.v.v\n             data/full_repos/permissive/131921633/tv/Util/Counter,data/full_repos/permissive/131921633/Util/Math.v.sv\n             Util/Math.v\n             Util/Math.v.v\n             Util/Math.v.sv\n             obj_dir/Util/Math.v\n             obj_dir/Util/Math.v.v\n             obj_dir/Util/Math.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.v:2: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.v:12: Define or directive not defined: \'`Data_Control_Control_T\'\n , `Data_Control_Control_T(input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.v:12: syntax error, unexpected \'(\', expecting \'[\'\n , `Data_Control_Control_T(input) ctrl\n                           ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.v:17: Define or directive not defined: \'`Util_Math_log2_expr\'\n`Util_Math_log2_expr\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.v:21: syntax error, unexpected assign\nassign n = q$ + 1;\n^~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.v:23: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways @(posedge `Data_Control_Control_Clock(ctrl))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Util/Counter/counter.v:24: Define or directive not defined: \'`Data_Control_Control_Reset\'\n if(`Data_Control_Control_Reset(ctrl))\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module Counter_counter #
	( parameter MAX   = 16
	, parameter WIDTH = Util_Math_log2(MAX)
	, parameter DELAY = 0
	)
	( input  [WIDTH-1:0] d
	, output [WIDTH-1:0] q
	, `Data_Control_Control_T(input) ctrl
	, input load
	, input enable
	);

`Util_Math_log2_expr

reg  [WIDTH-1:0] q$;
wire [WIDTH-1:0] n;
assign n = q$ + 1;

always @(posedge `Data_Control_Control_Clock(ctrl))
	if(`Data_Control_Control_Reset(ctrl))
		q$ <= 0;
	else if(load)
		q$ <= d;
	else if(enable)
		if(MAX == 2**WIDTH)
			q$ <= n;
		else if(n == WIDTH'(MAX))
			q$ <= 0;
		else
			q$ <= n;

Delay_arr #
	( .WIDTH (WIDTH)
	, .DELAY (DELAY)
	) dl
	( .ctrl (ctrl)
	, .in   (q$)
	, .out  (q)
	);

endmodule
module Counter_counter #
	( parameter MAX   = 16
	, parameter WIDTH = Util_Math_log2(MAX)
	, parameter DELAY = 0
	)
	( input  [WIDTH-1:0] d
	, output [WIDTH-1:0] q
	, `Data_Control_Control_T(input) ctrl
	, input load
	, input enable
	);


`Util_Math_log2_expr

reg  [WIDTH-1:0] q$;
wire [WIDTH-1:0] n;
assign n = q$ + 1;

always @(posedge `Data_Control_Control_Clock(ctrl))
	if(`Data_Control_Control_Reset(ctrl))
		q$ <= 0;
	else if(load)
		q$ <= d;
	else if(enable)
		if(MAX == 2**WIDTH)
			q$ <= n;
		else if(n == WIDTH'(MAX))
			q$ <= 0;
		else
			q$ <= n;

Delay_arr #
	( .WIDTH (WIDTH)
	, .DELAY (DELAY)
	) dl
	( .ctrl (ctrl)
	, .in   (q$)
	, .out  (q)
	);

endmodule