data/full_repos/permissive/187705377/Camera Reduced/pixel_counter.sv
1: b'%Error: Cannot find file containing module: Reduced,data/full_repos/permissive/187705377\n        ... Looked in:\n             data/full_repos/permissive/187705377/Camera/Reduced,data/full_repos/permissive/187705377\n             data/full_repos/permissive/187705377/Camera/Reduced,data/full_repos/permissive/187705377.v\n             data/full_repos/permissive/187705377/Camera/Reduced,data/full_repos/permissive/187705377.sv\n             Reduced,data/full_repos/permissive/187705377\n             Reduced,data/full_repos/permissive/187705377.v\n             Reduced,data/full_repos/permissive/187705377.sv\n             obj_dir/Reduced,data/full_repos/permissive/187705377\n             obj_dir/Reduced,data/full_repos/permissive/187705377.v\n             obj_dir/Reduced,data/full_repos/permissive/187705377.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/187705377/Camera\n%Error: Cannot find file containing module: Reduced/pixel_counter.sv\n%Error: Exiting due to 3 error(s)\n'
module pixel_counter(
	input logic clk,
	input logic reset, 
	input logic iVGA_HS,
	input logic iVGA_VS,
    input logic iVGA_BLANK_N,
   output logic [12:0] x_count,
   output logic [12:0] y_count);
	

    reg new_frame;
    reg iVGA_BLANK_N_last_clk;
    

	always_ff @(posedge clk) begin
        iVGA_BLANK_N_last_clk <= iVGA_BLANK_N;
    
        if(reset || !iVGA_VS) begin
			x_count <= 13'b0;
			y_count <= 13'b0;
            new_frame <= 1'b1;
        end else begin


            if(iVGA_HS && iVGA_BLANK_N) begin
                x_count <= x_count + 13'b1;
            end
            


            if(new_frame && iVGA_BLANK_N_last_clk && !iVGA_BLANK_N) begin
                x_count <= 13'b0;
                y_count <= y_count + 13'b1;
            end
        end
	end

endmodule
module pixel_counter(
	input logic clk,
	input logic reset, 
	input logic iVGA_HS,
	input logic iVGA_VS,
    input logic iVGA_BLANK_N,
   output logic [12:0] x_count,
   output logic [12:0] y_count);

	

    reg new_frame;
    reg iVGA_BLANK_N_last_clk;
    

	always_ff @(posedge clk) begin
        iVGA_BLANK_N_last_clk <= iVGA_BLANK_N;
    
        if(reset || !iVGA_VS) begin
			x_count <= 13'b0;
			y_count <= 13'b0;
            new_frame <= 1'b1;
        end else begin


            if(iVGA_HS && iVGA_BLANK_N) begin
                x_count <= x_count + 13'b1;
            end
            


            if(new_frame && iVGA_BLANK_N_last_clk && !iVGA_BLANK_N) begin
                x_count <= 13'b0;
                y_count <= y_count + 13'b1;
            end
        end
	end

endmodule