data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:2: Cannot find include file: xcfi_macros.sv\n`include "xcfi_macros.sv" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201267735/verif/rvfi/models,data/full_repos/permissive/201267735/xcfi_macros.sv\n             data/full_repos/permissive/201267735/verif/rvfi/models,data/full_repos/permissive/201267735/xcfi_macros.sv.v\n             data/full_repos/permissive/201267735/verif/rvfi/models,data/full_repos/permissive/201267735/xcfi_macros.sv.sv\n             xcfi_macros.sv\n             xcfi_macros.sv.v\n             xcfi_macros.sv.sv\n             obj_dir/xcfi_macros.sv\n             obj_dir/xcfi_macros.sv.v\n             obj_dir/xcfi_macros.sv.sv\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:6: Define or directive not defined: \'`XCFI_TRACE_INPUTS\'\n    `XCFI_TRACE_INPUTS,\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:6: syntax error, unexpected \',\', expecting \'[\'\n    `XCFI_TRACE_INPUTS,\n                      ^\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:8: Define or directive not defined: \'`XCFI_SPEC_OUTPUTS\'\n    `XCFI_SPEC_OUTPUTS\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:12: Define or directive not defined: \'`XCFI_INSN_CHECK_COMMON\'\n`XCFI_INSN_CHECK_COMMON\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:23: syntax error, unexpected genvar\ngenvar i;\n^~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:26: Define or directive not defined: \'`RS3\'\n    wire [2:0] lut_in = {`RS3[i], `RS2[i], `RS1[i]};\n                         ^~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:26: syntax error, unexpected \'[\', expecting TYPE-IDENTIFIER\n    wire [2:0] lut_in = {`RS3[i], `RS2[i], `RS1[i]};\n                             ^\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:26: Define or directive not defined: \'`RS2\'\n    wire [2:0] lut_in = {`RS3[i], `RS2[i], `RS1[i]};\n                                  ^~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:26: Define or directive not defined: \'`RS1\'\n    wire [2:0] lut_in = {`RS3[i], `RS2[i], `RS1[i]};\n                                           ^~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:34: Define or directive not defined: \'`FIELD_RS1_ADDR\'\nassign spec_rs1_addr    = `FIELD_RS1_ADDR;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:35: Define or directive not defined: \'`FIELD_RS2_ADDR\'\nassign spec_rs2_addr    = `FIELD_RS2_ADDR;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201267735/verif/rvfi/models/insn_xc_bop.v:37: Define or directive not defined: \'`FIELD_RD_ADDR\'\nassign spec_rd_addr     = `FIELD_RD_ADDR;\n                          ^~~~~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module xcfi_insn_spec (

    `XCFI_TRACE_INPUTS,

    `XCFI_SPEC_OUTPUTS

);

`XCFI_INSN_CHECK_COMMON

localparam BOP_LUT_SEL  = 31;

wire [ 7:0] uxcrypto_b0 = rvfi_aux[ 7:0];
wire [ 7:0] uxcrypto_b1 = rvfi_aux[15:8];

wire [ 7:0] lut         = rvfi_insn[BOP_LUT_SEL] ? uxcrypto_b1 : uxcrypto_b0;

wire [31:0] insn_result ;

genvar i;
generate for(i = 0; i < 32; i = i + 1) begin

    wire [2:0] lut_in = {`RS3[i], `RS2[i], `RS1[i]};

    assign     insn_result[i] = lut[lut_in];

end endgenerate

assign spec_valid       = rvfi_valid && dec_xc_bop;
assign spec_trap        = 1'b0   ;
assign spec_rs1_addr    = `FIELD_RS1_ADDR;
assign spec_rs2_addr    = `FIELD_RS2_ADDR;
assign spec_rs3_addr    = 0;
assign spec_rd_addr     = `FIELD_RD_ADDR;
assign spec_rd_wdata    = spec_rd_addr ? insn_result : {XLEN{1'b0}};
assign spec_rd_wide     = 1'b0;
assign spec_rd_wdatahi  = 32'b0;
assign spec_pc_wdata    = rvfi_pc_rdata + 4;
assign spec_mem_addr    = 0;
assign spec_mem_rmask   = 0;
assign spec_mem_wmask   = 0;
assign spec_mem_wdata   = 0;

endmodule
module xcfi_insn_spec (

    `XCFI_TRACE_INPUTS,

    `XCFI_SPEC_OUTPUTS

);


`XCFI_INSN_CHECK_COMMON

localparam BOP_LUT_SEL  = 31;

wire [ 7:0] uxcrypto_b0 = rvfi_aux[ 7:0];
wire [ 7:0] uxcrypto_b1 = rvfi_aux[15:8];

wire [ 7:0] lut         = rvfi_insn[BOP_LUT_SEL] ? uxcrypto_b1 : uxcrypto_b0;

wire [31:0] insn_result ;

genvar i;
generate for(i = 0; i < 32; i = i + 1) begin

    wire [2:0] lut_in = {`RS3[i], `RS2[i], `RS1[i]};

    assign     insn_result[i] = lut[lut_in];

end endgenerate

assign spec_valid       = rvfi_valid && dec_xc_bop;
assign spec_trap        = 1'b0   ;
assign spec_rs1_addr    = `FIELD_RS1_ADDR;
assign spec_rs2_addr    = `FIELD_RS2_ADDR;
assign spec_rs3_addr    = 0;
assign spec_rd_addr     = `FIELD_RD_ADDR;
assign spec_rd_wdata    = spec_rd_addr ? insn_result : {XLEN{1'b0}};
assign spec_rd_wide     = 1'b0;
assign spec_rd_wdatahi  = 32'b0;
assign spec_pc_wdata    = rvfi_pc_rdata + 4;
assign spec_mem_addr    = 0;
assign spec_mem_rmask   = 0;
assign spec_mem_wmask   = 0;
assign spec_mem_wdata   = 0;

endmodule