data/full_repos/permissive/175070965/lib/OPENCORES/ETH/eth_fifo_memory.v
1: b"%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/eth_fifo_memory.v:68: Cannot find file containing module: 'dftmem'\ndftmem #(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175070965/lib/OPENCORES/ETH,data/full_repos/permissive/175070965/dftmem\n             data/full_repos/permissive/175070965/lib/OPENCORES/ETH,data/full_repos/permissive/175070965/dftmem.v\n             data/full_repos/permissive/175070965/lib/OPENCORES/ETH,data/full_repos/permissive/175070965/dftmem.sv\n             dftmem\n             dftmem.v\n             dftmem.sv\n             obj_dir/dftmem\n             obj_dir/dftmem.v\n             obj_dir/dftmem.sv\n%Error: data/full_repos/permissive/175070965/lib/OPENCORES/ETH/eth_fifo_memory.v:159: Cannot find file containing module: 'ram_mem_sim_dp'\n        ram_mem_sim_dp #(\n        ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module eth_fifo_memory
#(
    parameter [31:0]    DATA_WIDTH    = 32'd32,
    parameter [31:0]    SIZE          = 32'd8,
    parameter [31:0]    DFT_MEM       = 32'd0,
    parameter [31:0]    TARGET_FPGA   = 32'd0,
    parameter [31:0]    TARGET_ASIC   = 32'd0
)(
    data_out,
    we,
    re,
    data_in,
    read_address,
    write_address,
    wclk,
    test_mode
);





output wire [DATA_WIDTH-1:0]    data_out;
input wire                      we;
input wire                      re;
input wire  [DATA_WIDTH-1:0]    data_in;
input wire  [SIZE-1:0]          read_address;
input wire  [SIZE-1:0]          write_address;
input wire                      wclk;
input wire                      test_mode;





wire    [DATA_WIDTH-1:0]    dft_data_out;
wire                        dft_re;
wire                        dft_we;





dftmem #(
    .DWIDTH(DATA_WIDTH),
    .CWIDTH(2*SIZE+2),
    .DFT_MEM(DFT_MEM),
    .WE_WIDTH(1))
dftmem_u (
    .clk(wclk),
    .data_mem_in(data_in),
    .data_mem_out(dft_data_out),
    .ctrl_in({we,re,read_address,write_address}),
    .test_mode(test_mode),
    .en(test_mode|re|we),
    .data_out(data_out),
    .re_in(re),
    .re_out(dft_re),
    .we_in(we),
    .we_out(dft_we));

generate
    if (TARGET_FPGA == 1) begin : virtex6

        if (SIZE == 6) begin

            blk_dp_fifo_256B
            ram_memory (
                .clka(wclk),
                .wea(dft_we),
                .addra(write_address),
                .dina(data_in),
                .clkb(wclk),
                .enb(dft_re),
                .addrb(read_address),
                .doutb(dft_data_out));
        end
        else if (SIZE == 7) begin

            blk_dp_fifo_512B
            ram_memory (
                .clka(wclk),
                .wea(dft_we),
                .addra(write_address),
                .dina(data_in),
                .clkb(wclk),
                .enb(dft_re),
                .addrb(read_address),
                .doutb(dft_data_out));
        end
        else if (SIZE == 8) begin

            blk_dp_fifo_1kB
            ram_memory (
                .clka(wclk),
                .wea(dft_we),
                .addra(write_address),
                .dina(data_in),
                .clkb(wclk),
                .enb(dft_re),
                .addrb(read_address),
                .doutb(dft_data_out));
        end
        else if (SIZE == 9) begin

            blk_dp_fifo_2kB
            ram_memory (
                .clka(wclk),
                .wea(dft_we),
                .addra(write_address),
                .dina(data_in),
                .clkb(wclk),
                .enb(dft_re),
                .addrb(read_address),
                .doutb(dft_data_out));
        end





        else begin
            `ifndef GATE
                initial begin
                    $display("CONFIG_ERROR: Not supported Virtex6 blk_dp_fifo memory size configuration!\n");
                    $finish;
                end
            `endif
        end

    end
    else if ((TARGET_ASIC == 0) && (TARGET_FPGA == 0)) begin : sim


        ram_mem_sim_dp #(
            .SIZE(SIZE+2))
        eth_fifo_mem (
            .clk(wclk),
            .rena(dft_re),
            .wea(4'd0),
            .addra(read_address),
            .dina({DATA_WIDTH{1'b0}}),
            .douta(dft_data_out),
            .renb(1'b0),
            .web({4{dft_we}}),
            .addrb(write_address),
            .dinb(data_in),
            .doutb());

    end





    else begin : memory_error
        `ifndef GATE
            initial begin
                $display("CONFIG_ERROR: Not supported eth_fifo memory technology!\n");
                $finish;
            end
        `endif
    end
endgenerate

endmodule
module eth_fifo_memory
#(
    parameter [31:0]    DATA_WIDTH    = 32'd32,
    parameter [31:0]    SIZE          = 32'd8,
    parameter [31:0]    DFT_MEM       = 32'd0,
    parameter [31:0]    TARGET_FPGA   = 32'd0,
    parameter [31:0]    TARGET_ASIC   = 32'd0
)(
    data_out,
    we,
    re,
    data_in,
    read_address,
    write_address,
    wclk,
    test_mode
);






output wire [DATA_WIDTH-1:0]    data_out;
input wire                      we;
input wire                      re;
input wire  [DATA_WIDTH-1:0]    data_in;
input wire  [SIZE-1:0]          read_address;
input wire  [SIZE-1:0]          write_address;
input wire                      wclk;
input wire                      test_mode;





wire    [DATA_WIDTH-1:0]    dft_data_out;
wire                        dft_re;
wire                        dft_we;





dftmem #(
    .DWIDTH(DATA_WIDTH),
    .CWIDTH(2*SIZE+2),
    .DFT_MEM(DFT_MEM),
    .WE_WIDTH(1))
dftmem_u (
    .clk(wclk),
    .data_mem_in(data_in),
    .data_mem_out(dft_data_out),
    .ctrl_in({we,re,read_address,write_address}),
    .test_mode(test_mode),
    .en(test_mode|re|we),
    .data_out(data_out),
    .re_in(re),
    .re_out(dft_re),
    .we_in(we),
    .we_out(dft_we));

generate
    if (TARGET_FPGA == 1) begin : virtex6

        if (SIZE == 6) begin

            blk_dp_fifo_256B
            ram_memory (
                .clka(wclk),
                .wea(dft_we),
                .addra(write_address),
                .dina(data_in),
                .clkb(wclk),
                .enb(dft_re),
                .addrb(read_address),
                .doutb(dft_data_out));
        end
        else if (SIZE == 7) begin

            blk_dp_fifo_512B
            ram_memory (
                .clka(wclk),
                .wea(dft_we),
                .addra(write_address),
                .dina(data_in),
                .clkb(wclk),
                .enb(dft_re),
                .addrb(read_address),
                .doutb(dft_data_out));
        end
        else if (SIZE == 8) begin

            blk_dp_fifo_1kB
            ram_memory (
                .clka(wclk),
                .wea(dft_we),
                .addra(write_address),
                .dina(data_in),
                .clkb(wclk),
                .enb(dft_re),
                .addrb(read_address),
                .doutb(dft_data_out));
        end
        else if (SIZE == 9) begin

            blk_dp_fifo_2kB
            ram_memory (
                .clka(wclk),
                .wea(dft_we),
                .addra(write_address),
                .dina(data_in),
                .clkb(wclk),
                .enb(dft_re),
                .addrb(read_address),
                .doutb(dft_data_out));
        end





        else begin
            `ifndef GATE
                initial begin
                    $display("CONFIG_ERROR: Not supported Virtex6 blk_dp_fifo memory size configuration!\n");
                    $finish;
                end
            `endif
        end

    end
    else if ((TARGET_ASIC == 0) && (TARGET_FPGA == 0)) begin : sim


        ram_mem_sim_dp #(
            .SIZE(SIZE+2))
        eth_fifo_mem (
            .clk(wclk),
            .rena(dft_re),
            .wea(4'd0),
            .addra(read_address),
            .dina({DATA_WIDTH{1'b0}}),
            .douta(dft_data_out),
            .renb(1'b0),
            .web({4{dft_we}}),
            .addrb(write_address),
            .dinb(data_in),
            .doutb());

    end





    else begin : memory_error
        `ifndef GATE
            initial begin
                $display("CONFIG_ERROR: Not supported eth_fifo memory technology!\n");
                $finish;
            end
        `endif
    end
endgenerate

endmodule