data/full_repos/permissive/146479393/TB/TB_top2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/146479393/TB/TB_top2.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/146479393/TB/TB_top2.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #100; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/146479393/TB/TB_top2.v:69: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/146479393/TB/TB_top2.v:38: Cannot find file containing module: \'top\'\n top uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/146479393/TB,data/full_repos/permissive/146479393/top\n             data/full_repos/permissive/146479393/TB,data/full_repos/permissive/146479393/top.v\n             data/full_repos/permissive/146479393/TB,data/full_repos/permissive/146479393/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Warning-WIDTH: data/full_repos/permissive/146479393/TB/TB_top2.v:53: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'97\'h1ffc9549442212007fff8bfbf\' generates 97 bits.\n                                                                    : ... In instance TB_top2\n  data = 97\'b1111111111100100101010100100101000100001000100001001000000000011111111111111110001011111110111111;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/146479393/TB/TB_top2.v:65: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                    : ... In instance TB_top2\n  SPI_Data_In = data >> i;\n              ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_top2;


	reg clk;
	reg reset;
	reg SPI_Data_In;


	wire SPI_clk;
	wire SPI_cs;
	wire data_out;


	top uut (
		.clk(clk), 
		.reset(reset), 
		.SPI_clk(SPI_clk), 
		.SPI_cs(SPI_cs), 
		.SPI_Data_In(SPI_Data_In), 
		.data_out(data_out)
	);
reg [31:0] data;
integer i;
	initial begin

		clk = 0;
		reset = 1;
		SPI_Data_In = 0;
		data = 97'b1111111111100100101010100100101000100001000100001001000000000011111111111111110001011111110111111;
		i=-1;

		#100;
        		reset =0;



	end

	always@(posedge clk)begin
		#100; 
		SPI_Data_In = data >> i;
		i = i + 1;
	end
	
			always #5 clk = ~clk;

      
endmodule
module TB_top2;



	reg clk;
	reg reset;
	reg SPI_Data_In;


	wire SPI_clk;
	wire SPI_cs;
	wire data_out;


	top uut (
		.clk(clk), 
		.reset(reset), 
		.SPI_clk(SPI_clk), 
		.SPI_cs(SPI_cs), 
		.SPI_Data_In(SPI_Data_In), 
		.data_out(data_out)
	);
reg [31:0] data;
integer i;
	initial begin

		clk = 0;
		reset = 1;
		SPI_Data_In = 0;
		data = 97'b1111111111100100101010100100101000100001000100001001000000000011111111111111110001011111110111111;
		i=-1;

		#100;
        		reset =0;



	end

	always@(posedge clk)begin
		#100; 
		SPI_Data_In = data >> i;
		i = i + 1;
	end
	
			always #5 clk = ~clk;

      
endmodule