data/full_repos/permissive/100597706/testing/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n   always # 5 clk = ~ clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[4] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[4] = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[14] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[14] = 1\'b0;\n    ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_tb_ahbl;


    localparam ioN = 1;
    localparam selBitLn = 5;



    reg HCLK, HRST;
   initial begin HCLK = 0; end

   always # 5 HCLK = ~ HCLK;

   initial begin
	   HRST = 0;
	   #50;
	   @(negedge HCLK);
	   HRST = 1;
	   #50;
	   @(negedge HCLK);
	   HRST = 0;
       $display("initialized");
   end   

    

    wire [31:0] HADDR, HWDATA, HRDATA;
    wire [1:0]  HSIZE;
    wire HREADY, HTRANS, HWRITE;

    reg [15:0] INT;

    AHBLMASTER AHBM (
        .HCLK(HCLK), .HRST(HRST),
     
        .HRDATA(HRDATA),
        .HREADY(HREADY),

        
        .HADDR(HADDR),
        .HSIZE(HSIZE),
        .HTRANS(HTRANS),
        .HWDATA(HWDATA),
        .HWRITE(HWRITE),
        
        

        .INT(INT)
    );
    

    wire [0:2+ioN] HSEL; 
    AHBLDEC  #(12, ioN) AHBLD (
        .HADDR(HADDR),
        .HSEL(HSEL)
    );
    

    wire [0:2+ioN] HREADYout;
    wire [31:0] HRDATAout [0:2+ioN];

    assign HREADYout[0] = 1'b1;
    assign HRDATAout[0] = 32'h40404040;
    

	AHBSLAVE_M #(12) M (
            .HSEL(HSEL[1]),

            .HCLK(HCLK),
            .HRST(HRST),

            .HREADY(HREADY),
			.HADDR(HADDR),
			.HTRANS(HTRANS),
			.HWRITE(HWRITE),
			.HSIZE(HSIZE),
			
            .HWDATA(HWDATA),

            .HREADYout(HREADYout[1]),
            .HRDATA(HRDATAout[1])
	
    );


    assign HREADYout[2] = 1'b1;
    assign HRDATAout[2] = `INST_NOP;
    


    AHBSLAVE_IO io1 (
        .HSEL(HSEL[3]),
        .HCLK(HCLK),
        .HRST(HRST),
        .HTRANS(HTRANS),
        .HWDATA(HWDATA),
        .HSIZE(HSIZE),
        .HWRITE(HWRITE),
        .HREADY(HREADY),
        
        .HREADYout(HREADYout[3]),
        .HRDATA(HRDATAout[3])
    );
    

    reg [selBitLn-1:0] HREADY_sel, HRDATA_sel;
    
    integer i;
    always@ (posedge HCLK, posedge HRST) begin
        if(HRST) begin
            HREADY_sel <= 0;
            HRDATA_sel <= 0;
        end
        else if(HREADY) begin
            for (i = 0; i < 3+ioN; i = i + 1)
                if (HSEL[i] & HTRANS) begin
                    HREADY_sel <= i[selBitLn-1:0];
                    HRDATA_sel <= i[selBitLn-1:0];
                end
        end
    end
    assign HREADY = HREADYout[HREADY_sel];
    assign HRDATA = HRDATAout[HRDATA_sel];





`ifdef _DBUG_
    always @ *
        $display ("HRDATA_tb = %h", HRDATA);
    always @ *
        $display ("HRDATA_sel = %h", HRDATA_sel);
`endif

endmodule
module cpu_tb_ahbl;



    localparam ioN = 1;
    localparam selBitLn = 5;



    reg HCLK, HRST;
   initial begin HCLK = 0; end

   always # 5 HCLK = ~ HCLK;

   initial begin
	   HRST = 0;
	   #50;
	   @(negedge HCLK);
	   HRST = 1;
	   #50;
	   @(negedge HCLK);
	   HRST = 0;
       $display("initialized");
   end   

    

    wire [31:0] HADDR, HWDATA, HRDATA;
    wire [1:0]  HSIZE;
    wire HREADY, HTRANS, HWRITE;

    reg [15:0] INT;

    AHBLMASTER AHBM (
        .HCLK(HCLK), .HRST(HRST),
     
        .HRDATA(HRDATA),
        .HREADY(HREADY),

        
        .HADDR(HADDR),
        .HSIZE(HSIZE),
        .HTRANS(HTRANS),
        .HWDATA(HWDATA),
        .HWRITE(HWRITE),
        
        

        .INT(INT)
    );
    

    wire [0:2+ioN] HSEL; 
    AHBLDEC  #(12, ioN) AHBLD (
        .HADDR(HADDR),
        .HSEL(HSEL)
    );
    

    wire [0:2+ioN] HREADYout;
    wire [31:0] HRDATAout [0:2+ioN];

    assign HREADYout[0] = 1'b1;
    assign HRDATAout[0] = 32'h40404040;
    

	AHBSLAVE_M #(12) M (
            .HSEL(HSEL[1]),

            .HCLK(HCLK),
            .HRST(HRST),

            .HREADY(HREADY),
			.HADDR(HADDR),
			.HTRANS(HTRANS),
			.HWRITE(HWRITE),
			.HSIZE(HSIZE),
			
            .HWDATA(HWDATA),

            .HREADYout(HREADYout[1]),
            .HRDATA(HRDATAout[1])
	
    );


    assign HREADYout[2] = 1'b1;
    assign HRDATAout[2] = `INST_NOP;
    


    AHBSLAVE_IO io1 (
        .HSEL(HSEL[3]),
        .HCLK(HCLK),
        .HRST(HRST),
        .HTRANS(HTRANS),
        .HWDATA(HWDATA),
        .HSIZE(HSIZE),
        .HWRITE(HWRITE),
        .HREADY(HREADY),
        
        .HREADYout(HREADYout[3]),
        .HRDATA(HRDATAout[3])
    );
    

    reg [selBitLn-1:0] HREADY_sel, HRDATA_sel;
    
    integer i;
    always@ (posedge HCLK, posedge HRST) begin
        if(HRST) begin
            HREADY_sel <= 0;
            HRDATA_sel <= 0;
        end
        else if(HREADY) begin
            for (i = 0; i < 3+ioN; i = i + 1)
                if (HSEL[i] & HTRANS) begin
                    HREADY_sel <= i[selBitLn-1:0];
                    HRDATA_sel <= i[selBitLn-1:0];
                end
        end
    end
    assign HREADY = HREADYout[HREADY_sel];
    assign HRDATA = HRDATAout[HRDATA_sel];





`ifdef _DBUG_
    always @ *
        $display ("HRDATA_tb = %h", HRDATA);
    always @ *
        $display ("HRDATA_sel = %h", HRDATA_sel);
`endif

endmodule