data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/vmac/mac_ram.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/vmac/mac_ram.v:67: Multiple top level modules\n                                                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                               : ... Top module \'RF2_64x16\'\nmodule RF2_64x16 (\n       ^~~~~~~~~\n                                                                                                               : ... Top module \'RF2_512x32\'\nmodule RF2_512x32 (\n       ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/vmac/mac_ram.v:59: Signal definition not found, creating implicitly: \'NOT_CENA\'\n   not (NOT_CENA, CENA);\n        ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/200650987/project/display/soc_up/simu/testbench/vmac/mac_ram.v:62: Signal definition not found, creating implicitly: \'NOT_CENB\'\n                                                                                                               : ... Suggested alternative: \'NOT_CENA\'\n   not (NOT_CENB, CENB);\n        ^~~~~~~~\n%Error: Exiting due to 3 warning(s)\n'
module RF2_64x16 (
   QA,
   AA,
   CLKA,
   CENA,
   AB,
   DB,
   CLKB,
   CENB
);
   parameter		   BITS = 16;
   parameter		   word_depth = 64;
   parameter		   addr_width = 6;
   output [15:0] QA;
   input [5:0] AA;
   input CLKA;
   input CENA;
   input [5:0] AB;
   input [15:0] DB;
   input CLKB;
   input CENB;
   reg [15:0] QA;

   reg [BITS-1:0] mem [word_depth-1:0];

   not (NOT_CENA, CENA);
   always @ ( posedge CLKA ) if ( NOT_CENA ) QA<=mem[AA];

   not (NOT_CENB, CENB);
   always @ ( posedge CLKB ) if ( NOT_CENB ) mem[AB]<=DB;

endmodule
module RF2_64x16 (
   QA,
   AA,
   CLKA,
   CENA,
   AB,
   DB,
   CLKB,
   CENB
);

   parameter		   BITS = 16;
   parameter		   word_depth = 64;
   parameter		   addr_width = 6;
   output [15:0] QA;
   input [5:0] AA;
   input CLKA;
   input CENA;
   input [5:0] AB;
   input [15:0] DB;
   input CLKB;
   input CENB;
   reg [15:0] QA;

   reg [BITS-1:0] mem [word_depth-1:0];

   not (NOT_CENA, CENA);
   always @ ( posedge CLKA ) if ( NOT_CENA ) QA<=mem[AA];

   not (NOT_CENB, CENB);
   always @ ( posedge CLKB ) if ( NOT_CENB ) mem[AB]<=DB;

endmodule