data/full_repos/permissive/175132042/rtl/picorv32/picosoc/picosoc.v
 line:80 column:39: Illegal character "'"
1: b'%Warning-MULTITOP: data/full_repos/permissive/175132042/rtl/picorv32/picosoc/picosoc.v:222: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'picosoc\'\nmodule picosoc (\n       ^~~~~~~\n                                                                                          : ... Top module \'picosoc_regs\'\nmodule picosoc_regs (\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/picorv32/picosoc/picosoc.v:252: Bit extraction of array[255:0] requires 8 bit index, not 22 bits.\n                                                                                       : ... In instance picosoc.memory\n  rdata <= mem[addr];\n              ^\n%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/picorv32/picosoc/picosoc.v:253: Bit extraction of array[255:0] requires 8 bit index, not 22 bits.\n                                                                                       : ... In instance picosoc.memory\n  if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/picorv32/picosoc/picosoc.v:254: Bit extraction of array[255:0] requires 8 bit index, not 22 bits.\n                                                                                       : ... In instance picosoc.memory\n  if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/picorv32/picosoc/picosoc.v:255: Bit extraction of array[255:0] requires 8 bit index, not 22 bits.\n                                                                                       : ... In instance picosoc.memory\n  if (wen[2]) mem[addr][23:16] <= wdata[23:16];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/175132042/rtl/picorv32/picosoc/picosoc.v:256: Bit extraction of array[255:0] requires 8 bit index, not 22 bits.\n                                                                                       : ... In instance picosoc.memory\n  if (wen[3]) mem[addr][31:24] <= wdata[31:24];\n                 ^\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/picosoc/picosoc.v:132: Cannot find file containing module: \'picorv32\'\n picorv32 #(\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175132042/rtl/picorv32/picosoc,data/full_repos/permissive/175132042/picorv32\n             data/full_repos/permissive/175132042/rtl/picorv32/picosoc,data/full_repos/permissive/175132042/picorv32.v\n             data/full_repos/permissive/175132042/rtl/picorv32/picosoc,data/full_repos/permissive/175132042/picorv32.sv\n             picorv32\n             picorv32.v\n             picorv32.sv\n             obj_dir/picorv32\n             obj_dir/picorv32.v\n             obj_dir/picorv32.sv\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/picosoc/picosoc.v:156: Cannot find file containing module: \'spimemio\'\n spimemio spimemio (\n ^~~~~~~~\n%Error: data/full_repos/permissive/175132042/rtl/picorv32/picosoc/picosoc.v:187: Cannot find file containing module: \'simpleuart\'\n simpleuart simpleuart (\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s), 6 warning(s)\n'
module picosoc_regs (
	input clk, wen,
	input [5:0] waddr,
	input [5:0] raddr1,
	input [5:0] raddr2,
	input [31:0] wdata,
	output [31:0] rdata1,
	output [31:0] rdata2
);
	reg [31:0] regs [0:31];

	always @(posedge clk)
		if (wen) regs[waddr[4:0]] <= wdata;

	assign rdata1 = regs[raddr1[4:0]];
	assign rdata2 = regs[raddr2[4:0]];
endmodule
module picosoc_regs (
	input clk, wen,
	input [5:0] waddr,
	input [5:0] raddr1,
	input [5:0] raddr2,
	input [31:0] wdata,
	output [31:0] rdata1,
	output [31:0] rdata2
);

	reg [31:0] regs [0:31];

	always @(posedge clk)
		if (wen) regs[waddr[4:0]] <= wdata;

	assign rdata1 = regs[raddr1[4:0]];
	assign rdata2 = regs[raddr2[4:0]];
endmodule