data/full_repos/permissive/143278/ivltests/rptconcat2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/rptconcat2.v:6: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main();
  reg [3:0] d, e;
  initial begin
    d <= {4{1'b1}};
    e = {4{1'b1}};
    #1;
    $display("%b %b",d,e);
    if (d !== e) begin
       $display("FAILED -- %b !== %b", d, e);
       $finish;
    end
     $display("PASSED");

  end
endmodule
module main();

  reg [3:0] d, e;
  initial begin
    d <= {4{1'b1}};
    e = {4{1'b1}};
    #1;
    $display("%b %b",d,e);
    if (d !== e) begin
       $display("FAILED -- %b !== %b", d, e);
       $finish;
    end
     $display("PASSED");

  end
endmodule