data/full_repos/permissive/21051978/processor/arrmultb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:25: Cannot find include file: arrmul.v\n`include "arrmul.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/arrmul.v\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/arrmul.v.v\n             data/full_repos/permissive/21051978/processor,data/full_repos/permissive/21051978/arrmul.v.sv\n             arrmul.v\n             arrmul.v.v\n             arrmul.v.sv\n             obj_dir/arrmul.v\n             obj_dir/arrmul.v.v\n             obj_dir/arrmul.v.sv\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:26: Cannot find include file: control.h\n`include "control.h" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:131: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:131: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:132: Define or directive not defined: \'`aluwmuleu\'\n  a_op=`aluwmuleu;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:132: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmuleu;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/arrmultb.v:136: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:141: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:141: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:142: Define or directive not defined: \'`aluwmuleu\'\n  a_op=`aluwmuleu;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:142: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmuleu;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/arrmultb.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:150: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:150: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:151: Define or directive not defined: \'`aluwmuleu\'\n  a_op=`aluwmuleu;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:151: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmuleu;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/arrmultb.v:155: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:160: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:160: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:161: Define or directive not defined: \'`aluwmuleu\'\n  a_op=`aluwmuleu;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:161: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmuleu;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/arrmultb.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:169: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:169: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:170: Define or directive not defined: \'`aluwmuleu\'\n  a_op=`aluwmuleu;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:170: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmuleu;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/arrmultb.v:187: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:192: Define or directive not defined: \'`w16\'\n  c_ww=`w16;\n       ^~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:192: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w16;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:193: Define or directive not defined: \'`aluwmuleu\'\n  a_op=`aluwmuleu;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:193: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmuleu;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/arrmultb.v:202: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:207: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:207: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:208: Define or directive not defined: \'`aluwmulou\'\n  a_op=`aluwmulou;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:208: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmulou;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/arrmultb.v:211: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:216: Define or directive not defined: \'`w16\'\n  c_ww=`w16;\n       ^~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:216: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w16;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:217: Define or directive not defined: \'`aluwmulou\'\n  a_op=`aluwmulou;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:217: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmulou;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/arrmultb.v:225: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:234: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:234: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:235: Define or directive not defined: \'`aluwmulos\'\n  a_op=`aluwmulos;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:235: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmulos;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/arrmultb.v:239: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:245: Define or directive not defined: \'`w16\'\n  c_ww=`w16;\n       ^~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:245: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w16;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:246: Define or directive not defined: \'`aluwmulos\'\n  a_op=`aluwmulos;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:246: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmulos;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/arrmultb.v:258: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:267: Define or directive not defined: \'`w8\'\n  c_ww=`w8;\n       ^~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:267: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w8;\n          ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:268: Define or directive not defined: \'`aluwmules\'\n  a_op=`aluwmules;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:268: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmules;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/21051978/processor/arrmultb.v:273: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:282: Define or directive not defined: \'`w16\'\n  c_ww=`w16;\n       ^~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:282: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  c_ww=`w16;\n           ^\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:283: Define or directive not defined: \'`aluwmules\'\n  a_op=`aluwmules;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/21051978/processor/arrmultb.v:283: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  a_op=`aluwmules;\n                 ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module tb_arrmul();


	


wire [0:127] res;
	
	
	
	
	
	
	

	


reg [0:127] r_A;

reg [0:127] r_B;

	reg [0:1] c_ww;

	reg [0:4] a_op;

reg [0:127] e_r;
	
	
	
	
	
	

	


	
	

	
	

	

	arrmul am (



		r_A,r_B,c_ww,a_op,res);
		
	
	



	initial
	begin

		$display($time, " << Starting the simulation >>");	
		
		


		r_A=128'h0402030405060708f00a0b0cff0eff00;
		r_B=128'h03010202030303031004f505ff09fe10;
		e_r=128'h000c0006000f00150f000a87fe01fd02;
		c_ww=`w8;
		a_op=`aluwmuleu;
		
		
		
		#10

		r_A=128'hff02030405060708f00a0b0cff0eff00;
		r_B=128'hfe010202030303031004f505ff09fe10;
		e_r=128'hfd020006000f00150f000a87fe01fd02;
		c_ww=`w8;
		a_op=`aluwmuleu;
		
		
		#10

		r_A=128'hf502030405060708f00a0b0cff0eff00;
		r_B=128'h0b010202030303031004f505ff09fe10;
		e_r=128'h0a870006000f00150f000a87fe01fd02;
		c_ww=`w8;
		a_op=`aluwmuleu;
		
		
		
		#10

		r_A=128'h1002030405060708f00a0b0cff0eff00;
		r_B=128'hf0010202030303031004f505ff09fe10;
		e_r=128'h0f000006000f00150f000a87fe01fd02;
		c_ww=`w8;
		a_op=`aluwmuleu;
		
		
		#10

		r_A=128'h0402030405060708f00a0b0cff0eff00;
		r_B=128'h00010202030303031004f505ff09fe10;
		e_r=128'h00000006000f00150f000a87fe01fd02;
		c_ww=`w8;
		a_op=`aluwmuleu;
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		#10

		r_A=128'h000100020000ffff000f10bff103ffff;
		r_B=128'h000200040006ffff000c100000120014;
		e_r=128'h0000000200000000000000b40010f236;
		c_ww=`w16;
		a_op=`aluwmuleu;
		
		
		
		

		
		
		
		#10

		r_A=128'h0102030405060708090aff0c0dff0fff;
		r_B=128'h01010202030303031004040508000fff;
		e_r=128'h00020008001200180028003c0000fe01;
		c_ww=`w8;
		a_op=`aluwmulou;
		
		
		#10

		r_A=128'h0001000200000008000f10bff103ffff;
		r_B=128'h0002000400060008000c001000120014;
		e_r=128'h000000080000004000010bf00013ffec;
		c_ww=`w16;
		a_op=`aluwmulou;
		
		
		

		
		
		
		#10


		r_A=128'h0180010501f9015301040100013c0100;
		r_B=128'h017f010901fa010001fd01f101b80100;
		e_r=128'hc080002d002a0000fff40000ef200000;
		c_ww=`w8;
		a_op=`aluwmulos;
		
		
		
		#10


		r_A=128'h1111000211118000111120541111fff9;
		r_B=128'hffff0004ffff7fffffff0000fffffffd;
		e_r=128'h00000008c00080000000000000000015;
		c_ww=`w16;
		a_op=`aluwmulos;
	
		
		
		
		
		
		

		
		
		
		#10


		r_A=128'h80010501f9015301040100013c010001;
		r_B=128'h7f010901fa010001fd01f101b8010001;
		e_r=128'hc080002d002a0000fff40000ef200000;
		c_ww=`w8;
		a_op=`aluwmules;
		
		
		
		
		#10


		r_A=128'h000211118000111120541111fff91111;
		r_B=128'h0004ffff7fffffff0000fffffffdffff;
		e_r=128'h00000008c00080000000000000000015;
		c_ww=`w16;
		a_op=`aluwmules;
	
		
		
	
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule
module tb_arrmul();



	


wire [0:127] res;
	
	
	
	
	
	
	

	


reg [0:127] r_A;

reg [0:127] r_B;

	reg [0:1] c_ww;

	reg [0:4] a_op;

reg [0:127] e_r;
	
	
	
	
	
	

	


	
	

	
	

	

	arrmul am (



		r_A,r_B,c_ww,a_op,res);
		
	
	



	initial
	begin

		$display($time, " << Starting the simulation >>");	
		
		


		r_A=128'h0402030405060708f00a0b0cff0eff00;
		r_B=128'h03010202030303031004f505ff09fe10;
		e_r=128'h000c0006000f00150f000a87fe01fd02;
		c_ww=`w8;
		a_op=`aluwmuleu;
		
		
		
		#10

		r_A=128'hff02030405060708f00a0b0cff0eff00;
		r_B=128'hfe010202030303031004f505ff09fe10;
		e_r=128'hfd020006000f00150f000a87fe01fd02;
		c_ww=`w8;
		a_op=`aluwmuleu;
		
		
		#10

		r_A=128'hf502030405060708f00a0b0cff0eff00;
		r_B=128'h0b010202030303031004f505ff09fe10;
		e_r=128'h0a870006000f00150f000a87fe01fd02;
		c_ww=`w8;
		a_op=`aluwmuleu;
		
		
		
		#10

		r_A=128'h1002030405060708f00a0b0cff0eff00;
		r_B=128'hf0010202030303031004f505ff09fe10;
		e_r=128'h0f000006000f00150f000a87fe01fd02;
		c_ww=`w8;
		a_op=`aluwmuleu;
		
		
		#10

		r_A=128'h0402030405060708f00a0b0cff0eff00;
		r_B=128'h00010202030303031004f505ff09fe10;
		e_r=128'h00000006000f00150f000a87fe01fd02;
		c_ww=`w8;
		a_op=`aluwmuleu;
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		
		#10

		r_A=128'h000100020000ffff000f10bff103ffff;
		r_B=128'h000200040006ffff000c100000120014;
		e_r=128'h0000000200000000000000b40010f236;
		c_ww=`w16;
		a_op=`aluwmuleu;
		
		
		
		

		
		
		
		#10

		r_A=128'h0102030405060708090aff0c0dff0fff;
		r_B=128'h01010202030303031004040508000fff;
		e_r=128'h00020008001200180028003c0000fe01;
		c_ww=`w8;
		a_op=`aluwmulou;
		
		
		#10

		r_A=128'h0001000200000008000f10bff103ffff;
		r_B=128'h0002000400060008000c001000120014;
		e_r=128'h000000080000004000010bf00013ffec;
		c_ww=`w16;
		a_op=`aluwmulou;
		
		
		

		
		
		
		#10


		r_A=128'h0180010501f9015301040100013c0100;
		r_B=128'h017f010901fa010001fd01f101b80100;
		e_r=128'hc080002d002a0000fff40000ef200000;
		c_ww=`w8;
		a_op=`aluwmulos;
		
		
		
		#10


		r_A=128'h1111000211118000111120541111fff9;
		r_B=128'hffff0004ffff7fffffff0000fffffffd;
		e_r=128'h00000008c00080000000000000000015;
		c_ww=`w16;
		a_op=`aluwmulos;
	
		
		
		
		
		
		

		
		
		
		#10


		r_A=128'h80010501f9015301040100013c010001;
		r_B=128'h7f010901fa010001fd01f101b8010001;
		e_r=128'hc080002d002a0000fff40000ef200000;
		c_ww=`w8;
		a_op=`aluwmules;
		
		
		
		
		#10


		r_A=128'h000211118000111120541111fff91111;
		r_B=128'h0004ffff7fffffff0000fffffffdffff;
		e_r=128'h00000008c00080000000000000000015;
		c_ww=`w16;
		a_op=`aluwmules;
	
		
		
	
		

		#30
		
		$display($time, " << Finishing the simulation >>");
		$finish;
	end

endmodule