data/full_repos/permissive/154352170/ALU.v
 line:1 column:1: Illegal character '\x00'
data/verilator_xmls/431d06e7-b5fe-47e0-b473-d0bbbb99adbd.xml
module ALU(
    input [31:0] A,
    input [31:0] B,
	 input [2:0] ALUOp,
	 output reg [31:0] ALU_Out
    );
	 
	 initial begin
	    ALU_Out = 32'h00000000;
	 end
	 
	 always @ (*) begin
	    
		 case(ALUOp)
		 
		    3'b000: ALU_Out <= A + B;
          
          3'b001: ALU_Out <= A - B;
			 
			 3'b010: ALU_Out <= A | B;
			 
			 3'b011: ALU_Out <= B;
			 
			 3'b100: ALU_Out <= A;
		 
			 3'b101: begin
			    if(B[7] == 1)
				    ALU_Out <= {24'hffffff, B[7:0]};
				 else
				    ALU_Out <= {24'h000000, B[7:0]};
			 end			 
			 
			 
		 endcase
		 
	 end
			  			 
endmodule
module ALU(
    input [31:0] A,
    input [31:0] B,
	 input [2:0] ALUOp,
	 output reg [31:0] ALU_Out
    );

	 
	 initial begin
	    ALU_Out = 32'h00000000;
	 end
	 
	 always @ (*) begin
	    
		 case(ALUOp)
		 
		    3'b000: ALU_Out <= A + B;
          
          3'b001: ALU_Out <= A - B;
			 
			 3'b010: ALU_Out <= A | B;
			 
			 3'b011: ALU_Out <= B;
			 
			 3'b100: ALU_Out <= A;
		 
			 3'b101: begin
			    if(B[7] == 1)
				    ALU_Out <= {24'hffffff, B[7:0]};
				 else
				    ALU_Out <= {24'h000000, B[7:0]};
			 end			 
			 
			 
		 endcase
		 
	 end
			  			 
endmodule