data/full_repos/permissive/173099254/lab6/cod.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/173099254/lab6/cod.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #5 clock = ~clock; load =0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab6/cod.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #5 clock = ~clock;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab6/cod.v:105: Unsupported: Ignoring delay on this delayed statement.\n       #5 reset =0;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab6/cod.v:110: Unsupported: Ignoring delay on this delayed statement.\n       #5 load =0;\n       ^\n%Warning-MULTITOP: data/full_repos/permissive/173099254/lab6/cod.v:77: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                     : ... Top module \'numarator_test\'\nmodule numarator_test();\n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'desc_numarator_test\'\nmodule desc_numarator_test();\n       ^~~~~~~~~~~~~~~~~~~\n%Warning-INFINITELOOP: data/full_repos/permissive/173099254/lab6/cod.v:69: Infinite loop (condition always true)\n                                                                         : ... In instance numarator_test\n  forever\n  ^~~~~~~\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module numarator4(data, up_down, enable, load, clock, reset, result, terminal_count);
input [3:0] data;
input up_down;
input enable;
input load;
input clock;
input reset;
output reg [3:0] result;
output reg terminal_count;


always @(posedge clock or posedge load or posedge reset) begin
  if(load)
   result = data;
  else
   result = 0;
   
  if(reset)
  begin
    result = 0;
    terminal_count =0;
  end

  if(enable == 1)
  begin
    if (up_down == 1)
    begin
      result = result + 1;
      if( result == 15)
         terminal_count = 1;
      else
         terminal_count = 0;
    end
    if(up_down == 0)
    begin  
      result = result - 1;
      if( result == 0)
         terminal_count = 1;
      else
         terminal_count = 0;
    end
  end
end
endmodule
module numarator4(data, up_down, enable, load, clock, reset, result, terminal_count);

input [3:0] data;
input up_down;
input enable;
input load;
input clock;
input reset;
output reg [3:0] result;
output reg terminal_count;


always @(posedge clock or posedge load or posedge reset) begin
  if(load)
   result = data;
  else
   result = 0;
   
  if(reset)
  begin
    result = 0;
    terminal_count =0;
  end

  if(enable == 1)
  begin
    if (up_down == 1)
    begin
      result = result + 1;
      if( result == 15)
         terminal_count = 1;
      else
         terminal_count = 0;
    end
    if(up_down == 0)
    begin  
      result = result - 1;
      if( result == 0)
         terminal_count = 1;
      else
         terminal_count = 0;
    end
  end
end
endmodule