data/full_repos/permissive/167580717/sys/sysmem.sv
1: b"%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:224: Cannot find file containing module: 'cyclonev_hps_interface_clocks_resets'\ncyclonev_hps_interface_clocks_resets clocks_resets(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167580717/sys,data/full_repos/permissive/167580717/cyclonev_hps_interface_clocks_resets\n             data/full_repos/permissive/167580717/sys,data/full_repos/permissive/167580717/cyclonev_hps_interface_clocks_resets.v\n             data/full_repos/permissive/167580717/sys,data/full_repos/permissive/167580717/cyclonev_hps_interface_clocks_resets.sv\n             cyclonev_hps_interface_clocks_resets\n             cyclonev_hps_interface_clocks_resets.v\n             cyclonev_hps_interface_clocks_resets.sv\n             obj_dir/cyclonev_hps_interface_clocks_resets\n             obj_dir/cyclonev_hps_interface_clocks_resets.v\n             obj_dir/cyclonev_hps_interface_clocks_resets.sv\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:246: Cannot find file containing module: 'cyclonev_hps_interface_dbg_apb'\ncyclonev_hps_interface_dbg_apb debug_apb(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:256: Cannot find file containing module: 'cyclonev_hps_interface_tpiu_trace'\ncyclonev_hps_interface_tpiu_trace tpiu(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:263: Cannot find file containing module: 'cyclonev_hps_interface_boot_from_fpga'\ncyclonev_hps_interface_boot_from_fpga boot_from_fpga(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:285: Cannot find file containing module: 'cyclonev_hps_interface_fpga2hps'\ncyclonev_hps_interface_fpga2hps fpga2hps(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:292: Cannot find file containing module: 'cyclonev_hps_interface_hps2fpga'\ncyclonev_hps_interface_hps2fpga hps2fpga(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:299: Cannot find file containing module: 'cyclonev_hps_interface_fpga2sdram'\ncyclonev_hps_interface_fpga2sdram f2sdram(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:464: Cannot find file containing module: 'cyclonev_hps_interface_peripheral_uart'\ncyclonev_hps_interface_peripheral_uart peripheral_uart1\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/167580717/sys/sysmem.sv:109: Cannot find file containing module: 'reset_source'\nreset_source reset_source (\n^~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module sysmem_lite
(
	input          ramclk1_clk,
	input   [28:0] ram1_address,
	input    [7:0] ram1_burstcount,
	output         ram1_waitrequest,
	output  [63:0] ram1_readdata,
	output         ram1_readdatavalid,
	input          ram1_read,
	input   [63:0] ram1_writedata,
	input    [7:0] ram1_byteenable,
	input          ram1_write,

	input          ramclk2_clk,
	input   [28:0] ram2_address,
	input    [7:0] ram2_burstcount,
	output         ram2_waitrequest,
	output  [63:0] ram2_readdata,
	output         ram2_readdatavalid,
	input          ram2_read,
	input   [63:0] ram2_writedata,
	input    [7:0] ram2_byteenable,
	input          ram2_write,

	output         ctl_clock,
	input          reset_cold_req,
	output         reset_reset,
	input          reset_reset_req,
	input          reset_warm_req,

	input          vbuf_clk,
	input   [27:0] vbuf_address,
	input    [7:0] vbuf_burstcount,
	output         vbuf_waitrequest,
	output [127:0] vbuf_readdata,
	output         vbuf_readdatavalid,
	input          vbuf_read,
	input  [127:0] vbuf_writedata,
	input   [15:0] vbuf_byteenable,
	input          vbuf_write,

	input          uart_cts,
	input          uart_dsr,
	input          uart_dcd,
	input          uart_ri,
	output         uart_dtr,
	output         uart_rts,
	output         uart_out1_n,
	output         uart_out2_n,
	input          uart_rxd,
	output         uart_txd
);

assign ctl_clock = clk_vip_clk;

wire hps_h2f_reset_reset;
wire reset_source_reset_cold_reset;
wire reset_source_reset_warm_reset;
wire clk_vip_clk;

sysmem_HPS_fpga_interfaces fpga_interfaces (
	.f2h_cold_rst_req_n       (~reset_source_reset_cold_reset),
	.f2h_warm_rst_req_n       (~reset_source_reset_warm_reset),
	.h2f_user0_clk            (clk_vip_clk),
	.h2f_rst_n                (hps_h2f_reset_reset),
	.f2h_sdram0_clk           (vbuf_clk),
	.f2h_sdram0_ADDRESS       (vbuf_address),
	.f2h_sdram0_BURSTCOUNT    (vbuf_burstcount),
	.f2h_sdram0_WAITREQUEST   (vbuf_waitrequest),
	.f2h_sdram0_READDATA      (vbuf_readdata),
	.f2h_sdram0_READDATAVALID (vbuf_readdatavalid),
	.f2h_sdram0_READ          (vbuf_read),
	.f2h_sdram0_WRITEDATA     (vbuf_writedata),
	.f2h_sdram0_BYTEENABLE    (vbuf_byteenable),
	.f2h_sdram0_WRITE         (vbuf_write),
	.f2h_sdram1_clk           (ramclk1_clk),
	.f2h_sdram1_ADDRESS       (ram1_address),
	.f2h_sdram1_BURSTCOUNT    (ram1_burstcount),
	.f2h_sdram1_WAITREQUEST   (ram1_waitrequest),
	.f2h_sdram1_READDATA      (ram1_readdata),
	.f2h_sdram1_READDATAVALID (ram1_readdatavalid),
	.f2h_sdram1_READ          (ram1_read),
	.f2h_sdram1_WRITEDATA     (ram1_writedata),
	.f2h_sdram1_BYTEENABLE    (ram1_byteenable),
	.f2h_sdram1_WRITE         (ram1_write),
	.f2h_sdram2_clk           (ramclk2_clk),
	.f2h_sdram2_ADDRESS       (ram2_address),
	.f2h_sdram2_BURSTCOUNT    (ram2_burstcount),
	.f2h_sdram2_WAITREQUEST   (ram2_waitrequest),
	.f2h_sdram2_READDATA      (ram2_readdata),
	.f2h_sdram2_READDATAVALID (ram2_readdatavalid),
	.f2h_sdram2_READ          (ram2_read),
	.f2h_sdram2_WRITEDATA     (ram2_writedata),
	.f2h_sdram2_BYTEENABLE    (ram2_byteenable),
	.f2h_sdram2_WRITE         (ram2_write),
	.uart_cts                 (uart_cts),
	.uart_dsr                 (uart_dsr),
	.uart_dcd                 (uart_dcd),
	.uart_ri                  (uart_ri),
	.uart_dtr                 (uart_dtr),
	.uart_rts                 (uart_rts),
	.uart_out1_n              (uart_out1_n),
	.uart_out2_n              (uart_out2_n),
	.uart_rxd                 (uart_rxd),
	.uart_txd                 (uart_txd)
);

reset_source reset_source (
	.clk        (clk_vip_clk),
	.reset_hps  (~hps_h2f_reset_reset),
	.reset_sys  (),
	.cold_req   (reset_cold_req),
	.reset      (reset_reset),
	.reset_req  (reset_reset_req),
	.reset_vip  (0),
	.warm_req   (reset_warm_req),
	.reset_warm (reset_source_reset_warm_reset),
	.reset_cold (reset_source_reset_cold_reset)
);

endmodule
module sysmem_lite
(
	input          ramclk1_clk,
	input   [28:0] ram1_address,
	input    [7:0] ram1_burstcount,
	output         ram1_waitrequest,
	output  [63:0] ram1_readdata,
	output         ram1_readdatavalid,
	input          ram1_read,
	input   [63:0] ram1_writedata,
	input    [7:0] ram1_byteenable,
	input          ram1_write,

	input          ramclk2_clk,
	input   [28:0] ram2_address,
	input    [7:0] ram2_burstcount,
	output         ram2_waitrequest,
	output  [63:0] ram2_readdata,
	output         ram2_readdatavalid,
	input          ram2_read,
	input   [63:0] ram2_writedata,
	input    [7:0] ram2_byteenable,
	input          ram2_write,

	output         ctl_clock,
	input          reset_cold_req,
	output         reset_reset,
	input          reset_reset_req,
	input          reset_warm_req,

	input          vbuf_clk,
	input   [27:0] vbuf_address,
	input    [7:0] vbuf_burstcount,
	output         vbuf_waitrequest,
	output [127:0] vbuf_readdata,
	output         vbuf_readdatavalid,
	input          vbuf_read,
	input  [127:0] vbuf_writedata,
	input   [15:0] vbuf_byteenable,
	input          vbuf_write,

	input          uart_cts,
	input          uart_dsr,
	input          uart_dcd,
	input          uart_ri,
	output         uart_dtr,
	output         uart_rts,
	output         uart_out1_n,
	output         uart_out2_n,
	input          uart_rxd,
	output         uart_txd
);


assign ctl_clock = clk_vip_clk;

wire hps_h2f_reset_reset;
wire reset_source_reset_cold_reset;
wire reset_source_reset_warm_reset;
wire clk_vip_clk;

sysmem_HPS_fpga_interfaces fpga_interfaces (
	.f2h_cold_rst_req_n       (~reset_source_reset_cold_reset),
	.f2h_warm_rst_req_n       (~reset_source_reset_warm_reset),
	.h2f_user0_clk            (clk_vip_clk),
	.h2f_rst_n                (hps_h2f_reset_reset),
	.f2h_sdram0_clk           (vbuf_clk),
	.f2h_sdram0_ADDRESS       (vbuf_address),
	.f2h_sdram0_BURSTCOUNT    (vbuf_burstcount),
	.f2h_sdram0_WAITREQUEST   (vbuf_waitrequest),
	.f2h_sdram0_READDATA      (vbuf_readdata),
	.f2h_sdram0_READDATAVALID (vbuf_readdatavalid),
	.f2h_sdram0_READ          (vbuf_read),
	.f2h_sdram0_WRITEDATA     (vbuf_writedata),
	.f2h_sdram0_BYTEENABLE    (vbuf_byteenable),
	.f2h_sdram0_WRITE         (vbuf_write),
	.f2h_sdram1_clk           (ramclk1_clk),
	.f2h_sdram1_ADDRESS       (ram1_address),
	.f2h_sdram1_BURSTCOUNT    (ram1_burstcount),
	.f2h_sdram1_WAITREQUEST   (ram1_waitrequest),
	.f2h_sdram1_READDATA      (ram1_readdata),
	.f2h_sdram1_READDATAVALID (ram1_readdatavalid),
	.f2h_sdram1_READ          (ram1_read),
	.f2h_sdram1_WRITEDATA     (ram1_writedata),
	.f2h_sdram1_BYTEENABLE    (ram1_byteenable),
	.f2h_sdram1_WRITE         (ram1_write),
	.f2h_sdram2_clk           (ramclk2_clk),
	.f2h_sdram2_ADDRESS       (ram2_address),
	.f2h_sdram2_BURSTCOUNT    (ram2_burstcount),
	.f2h_sdram2_WAITREQUEST   (ram2_waitrequest),
	.f2h_sdram2_READDATA      (ram2_readdata),
	.f2h_sdram2_READDATAVALID (ram2_readdatavalid),
	.f2h_sdram2_READ          (ram2_read),
	.f2h_sdram2_WRITEDATA     (ram2_writedata),
	.f2h_sdram2_BYTEENABLE    (ram2_byteenable),
	.f2h_sdram2_WRITE         (ram2_write),
	.uart_cts                 (uart_cts),
	.uart_dsr                 (uart_dsr),
	.uart_dcd                 (uart_dcd),
	.uart_ri                  (uart_ri),
	.uart_dtr                 (uart_dtr),
	.uart_rts                 (uart_rts),
	.uart_out1_n              (uart_out1_n),
	.uart_out2_n              (uart_out2_n),
	.uart_rxd                 (uart_rxd),
	.uart_txd                 (uart_txd)
);

reset_source reset_source (
	.clk        (clk_vip_clk),
	.reset_hps  (~hps_h2f_reset_reset),
	.reset_sys  (),
	.cold_req   (reset_cold_req),
	.reset      (reset_reset),
	.reset_req  (reset_reset_req),
	.reset_vip  (0),
	.warm_req   (reset_warm_req),
	.reset_warm (reset_source_reset_warm_reset),
	.reset_cold (reset_source_reset_cold_reset)
);

endmodule