data/full_repos/permissive/143278/vhdl_tests/pr2529315b.v
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/vhdl_tests/pr2529315b.v:70: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'CI\' generates 1 bits.\n                                                                            : ... In instance test.car0\nassign    {CO, unused} = A + B + CI;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/vhdl_tests/pr2529315b.v:55: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'CI\' generates 1 bits.\n                                                                            : ... In instance test.add2\nassign Z = A + B + CI;\n                 ^\n%Error: Exiting due to 2 warning(s)\n'
module test (
   Z,
   CO32,
   A,
   B,
   CI);

input[63:0]  A;
input[63:0]  B;
input	     CI;
output[63:0] Z;
output       CO32;

wire[31:0] Z1;
wire[31:0] Z2;

adder32 add0(
   .Z(Z[31:0]),
   .A(A[31:0]),
   .B(B[31:0]),
   .CI(CI));

carry32 car0(
   .CO (CO32),
   .A  (A[31:0]),
   .B  (B[31:0]),
   .CI (CI));

adder32 add1(
   .Z  (Z1),
   .A  (A[63:32]),
   .B  (B[63:32]),
   .CI (1'b0));

adder32 add2(
   .Z  (Z2),
   .A  (A[63:32]),
   .B  (B[63:32]),
   .CI (1'b1));

assign Z[63:32] = CO32 ? Z2 : Z1;

endmodule
module test (
   Z,
   CO32,
   A,
   B,
   CI);


input[63:0]  A;
input[63:0]  B;
input	     CI;
output[63:0] Z;
output       CO32;

wire[31:0] Z1;
wire[31:0] Z2;

adder32 add0(
   .Z(Z[31:0]),
   .A(A[31:0]),
   .B(B[31:0]),
   .CI(CI));

carry32 car0(
   .CO (CO32),
   .A  (A[31:0]),
   .B  (B[31:0]),
   .CI (CI));

adder32 add1(
   .Z  (Z1),
   .A  (A[63:32]),
   .B  (B[63:32]),
   .CI (1'b0));

adder32 add2(
   .Z  (Z2),
   .A  (A[63:32]),
   .B  (B[63:32]),
   .CI (1'b1));

assign Z[63:32] = CO32 ? Z2 : Z1;

endmodule