data/full_repos/permissive/189013641/src/mode_decide.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/189013641/src/mode_decide.v:75: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s VARREF \'a\' generates 8 bits.\n                                                                         : ... In instance mode_decide\n assign #1 Max=(a>=b)?a:b;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/mode_decide.v:75: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s VARREF \'b\' generates 8 bits.\n                                                                         : ... In instance mode_decide\n assign #1 Max=(a>=b)?a:b;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/mode_decide.v:76: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s VARREF \'b\' generates 8 bits.\n                                                                         : ... In instance mode_decide\n assign #1 Min=(a>=b)?b:a;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/mode_decide.v:76: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s VARREF \'a\' generates 8 bits.\n                                                                         : ... In instance mode_decide\n assign #1 Min=(a>=b)?b:a;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/mode_decide.v:93: Operator LTE expects 9 bits on the LHS, but LHS\'s VARREF \'c\' generates 8 bits.\n                                                                         : ... In instance mode_decide\n  else if(c<=Min)\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/mode_decide.v:91: Operator GTE expects 9 bits on the LHS, but LHS\'s VARREF \'c\' generates 8 bits.\n                                                                         : ... In instance mode_decide\n  if(c>=Max)\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/mode_decide.v:108: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'Ix_in\' generates 8 bits.\n                                                                          : ... In instance mode_decide\n Ix_out<=Ix_in;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/mode_decide.v:109: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 8 bits.\n                                                                          : ... In instance mode_decide\n Ra<=a;\n   ^~\n%Warning-WIDTH: data/full_repos/permissive/189013641/src/mode_decide.v:110: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'b\' generates 8 bits.\n                                                                          : ... In instance mode_decide\n Rb<=b;\n   ^~\n%Error: Exiting due to 9 warning(s)\n'
module mode_decide(clk, reset, en,END_LINE,
                   Ix_in, a, b, c, d,
				   D1,D2,D3,
				   mode,Px,Ix_out,Runcnt,Ra,Rb,en_out);
    input clk;
    input reset;
    input en;
	input END_LINE;
    input  [7:0] Ix_in;
    input  [7:0] a;
	input  [7:0] b;
	input  [7:0] c;
	input  [7:0] d;
	
	output [8:0] D1;
	output [8:0] D2;
	output [8:0] D3;
    output [1:0] mode;
    output [8:0] Px;
	output [8:0] Ix_out;
	output [9:0] Runcnt;
	output [8:0] Ra;
	output [8:0] Rb;
	output en_out;
	 
	reg [8:0] D1;
	reg [8:0] D2;
	reg [8:0] D3;
    reg [1:0] mode;



    reg [8:0] Px;
	reg [8:0] Ix_out;
	reg [9:0] Runcnt;
	reg [9:0] Runcnt_tmp;
	reg [8:0] Ra;
	reg [8:0] Rb;
	reg en_out;
	
	wire [8:0] Max;
	wire [8:0] Min;
	 
	wire value1;
	wire value2;
	wire value3;
	wire [2:0] cont;
	
	reg [1:0] state;
	 
	parameter  Idle=2'b01,
	           Run=2'b10;

	
	assign #1 Max=(a>=b)?a:b;
	assign #1 Min=(a>=b)?b:a;
	 
	assign #1 value1=(d==c)?1:0;
	assign #1 value2=(b==d)?1:0;
	assign #1 value3=(d==a)?1:0;
	assign #1 cont={value1,value2,value3};
	
	
	

	 always@(posedge clk or negedge reset)
	 if(!reset)
		Px<=0;
	 else if(en)
	 begin      
		if(c>=Max)
			Px<=Min;
		else if(c<=Min)
			Px<=Max;
         else
			Px<=a+b-c;			
	 end	
	 else Px<=0;
	

	always@(posedge clk or negedge reset)
	if(!reset) begin
	Ix_out<=0;
	Ra<=0;
	Rb<=0;
	end
	else if(en) begin
	Ix_out<=Ix_in;
	Ra<=a;
	Rb<=b;
	end
	else begin
	Ix_out<=0;
	Ra<=0;
	Rb<=0;
	end
	

	always@(posedge clk or negedge reset)
	if(!reset) begin
		D1<=0;
		D2<=0;
		D3<=0;
		end
	else if(en) begin
		D1<=d-b;
		D2<=b-c;
		D3<=c-a;
		end
	else begin
		D1<=0;
		D2<=0;
		D3<=0;
		end

	always@(posedge clk or negedge reset)
	if(!reset)
	  en_out<=0;
	 else if(en)
		case(state)
		Idle:begin
	      if(cont==3'b111)
				begin
			   if((Ix_in==a)&&(END_LINE==0))
			       en_out<=0;
			    else
				   en_out<=1;
				end
			 else
			    en_out<=1;
			end
		 Run:begin
	     if((Ix_in==a)&&(END_LINE==0))
			  en_out<=0;
			 else
			  en_out<=1;
			  end
	   default: en_out<=0;
		endcase
	 else
	    en_out<=0;
	
	

always@(posedge clk or negedge reset)
	 if(!reset)
	 begin
	 state<=Idle;
	 mode<=0;
	 Runcnt<=0;
	 Runcnt_tmp<=0;
	 end
	 else
	 if(en) begin 
	 case(state)
	 Idle:begin
	      if(cont==3'b111) begin
			    if(Ix_in==a)
				  begin				  
				  if(END_LINE)
				    begin
				    mode<=2'b10;
					 state<=Idle;
					 Runcnt<=1;
					 end
					else
					 begin
					 mode<=2'b01;
					 state<=Run;
					 Runcnt_tmp<=1;
					 end
				  end
				 else
				  begin
					mode<=2'b11;
				   Runcnt_tmp<=0;
			      Runcnt<=0; 				  
			      state<=Idle;
				  end
				end
         else
            begin
				  mode<=2'b00;
				  Runcnt_tmp<=0; 
			     Runcnt<=0;
				  state<=Idle;
            end 
			end
	 Run:begin
	     if(Ix_in==a)
		
			if(END_LINE)
			 begin
			 Runcnt<=Runcnt_tmp+1;
			 Runcnt_tmp<=0;
			 mode<=2'b10;
			 state<=Idle;
			 end
		   else
			 begin
			 Runcnt_tmp<=Runcnt_tmp+1;
			 mode<=2'b01;
			 state<=Run;
			 end
			 
		  else
		   begin		 
			Runcnt<=Runcnt_tmp;
			Runcnt_tmp<=0;
			mode<=2'b11;
			state<=Idle;
		   end
	          		  
		 end
	 default:
	        begin
	        state<=Idle;
			  Runcnt<=0;
	        Runcnt_tmp<=0;
	        mode<=0;
			  end
			endcase
	 
	 
	 end
endmodule
module mode_decide(clk, reset, en,END_LINE,
                   Ix_in, a, b, c, d,
				   D1,D2,D3,
				   mode,Px,Ix_out,Runcnt,Ra,Rb,en_out);

    input clk;
    input reset;
    input en;
	input END_LINE;
    input  [7:0] Ix_in;
    input  [7:0] a;
	input  [7:0] b;
	input  [7:0] c;
	input  [7:0] d;
	
	output [8:0] D1;
	output [8:0] D2;
	output [8:0] D3;
    output [1:0] mode;
    output [8:0] Px;
	output [8:0] Ix_out;
	output [9:0] Runcnt;
	output [8:0] Ra;
	output [8:0] Rb;
	output en_out;
	 
	reg [8:0] D1;
	reg [8:0] D2;
	reg [8:0] D3;
    reg [1:0] mode;



    reg [8:0] Px;
	reg [8:0] Ix_out;
	reg [9:0] Runcnt;
	reg [9:0] Runcnt_tmp;
	reg [8:0] Ra;
	reg [8:0] Rb;
	reg en_out;
	
	wire [8:0] Max;
	wire [8:0] Min;
	 
	wire value1;
	wire value2;
	wire value3;
	wire [2:0] cont;
	
	reg [1:0] state;
	 
	parameter  Idle=2'b01,
	           Run=2'b10;

	
	assign #1 Max=(a>=b)?a:b;
	assign #1 Min=(a>=b)?b:a;
	 
	assign #1 value1=(d==c)?1:0;
	assign #1 value2=(b==d)?1:0;
	assign #1 value3=(d==a)?1:0;
	assign #1 cont={value1,value2,value3};
	
	
	

	 always@(posedge clk or negedge reset)
	 if(!reset)
		Px<=0;
	 else if(en)
	 begin      
		if(c>=Max)
			Px<=Min;
		else if(c<=Min)
			Px<=Max;
         else
			Px<=a+b-c;			
	 end	
	 else Px<=0;
	

	always@(posedge clk or negedge reset)
	if(!reset) begin
	Ix_out<=0;
	Ra<=0;
	Rb<=0;
	end
	else if(en) begin
	Ix_out<=Ix_in;
	Ra<=a;
	Rb<=b;
	end
	else begin
	Ix_out<=0;
	Ra<=0;
	Rb<=0;
	end
	

	always@(posedge clk or negedge reset)
	if(!reset) begin
		D1<=0;
		D2<=0;
		D3<=0;
		end
	else if(en) begin
		D1<=d-b;
		D2<=b-c;
		D3<=c-a;
		end
	else begin
		D1<=0;
		D2<=0;
		D3<=0;
		end

	always@(posedge clk or negedge reset)
	if(!reset)
	  en_out<=0;
	 else if(en)
		case(state)
		Idle:begin
	      if(cont==3'b111)
				begin
			   if((Ix_in==a)&&(END_LINE==0))
			       en_out<=0;
			    else
				   en_out<=1;
				end
			 else
			    en_out<=1;
			end
		 Run:begin
	     if((Ix_in==a)&&(END_LINE==0))
			  en_out<=0;
			 else
			  en_out<=1;
			  end
	   default: en_out<=0;
		endcase
	 else
	    en_out<=0;
	
	

always@(posedge clk or negedge reset)
	 if(!reset)
	 begin
	 state<=Idle;
	 mode<=0;
	 Runcnt<=0;
	 Runcnt_tmp<=0;
	 end
	 else
	 if(en) begin 
	 case(state)
	 Idle:begin
	      if(cont==3'b111) begin
			    if(Ix_in==a)
				  begin				  
				  if(END_LINE)
				    begin
				    mode<=2'b10;
					 state<=Idle;
					 Runcnt<=1;
					 end
					else
					 begin
					 mode<=2'b01;
					 state<=Run;
					 Runcnt_tmp<=1;
					 end
				  end
				 else
				  begin
					mode<=2'b11;
				   Runcnt_tmp<=0;
			      Runcnt<=0; 				  
			      state<=Idle;
				  end
				end
         else
            begin
				  mode<=2'b00;
				  Runcnt_tmp<=0; 
			     Runcnt<=0;
				  state<=Idle;
            end 
			end
	 Run:begin
	     if(Ix_in==a)
		
			if(END_LINE)
			 begin
			 Runcnt<=Runcnt_tmp+1;
			 Runcnt_tmp<=0;
			 mode<=2'b10;
			 state<=Idle;
			 end
		   else
			 begin
			 Runcnt_tmp<=Runcnt_tmp+1;
			 mode<=2'b01;
			 state<=Run;
			 end
			 
		  else
		   begin		 
			Runcnt<=Runcnt_tmp;
			Runcnt_tmp<=0;
			mode<=2'b11;
			state<=Idle;
		   end
	          		  
		 end
	 default:
	        begin
	        state<=Idle;
			  Runcnt<=0;
	        Runcnt_tmp<=0;
	        mode<=0;
			  end
			endcase
	 
	 
	 end
endmodule