data/full_repos/permissive/128659832/verilog/IR_tb.v
 line:53: before: "$"
1: b'%Error: data/full_repos/permissive/128659832/verilog/IR_tb.v:25: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("IR_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/128659832/verilog/IR_tb.v:26: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, IR_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #1  nIR = 8\'h00;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #1  wIR = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #1  clk  = 1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #1  clk  = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #1  wIR = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #1  nIR = 8\'h10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #1  wIR = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #1  clk  = 1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #1  clk  = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #1  wIR = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #1  nIR = 8\'h20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #1  wIR = 0;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #1  clk  = 1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #1  clk  = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #1  wIR = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #1  nIR = 8\'h30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1  wIR = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #1  clk  = 1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #1  clk  = 0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #1  wIR = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128659832/verilog/IR_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 21 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module IR_tb;

    reg clk  = 0;
    reg wIR = 0;

    reg  [7:0] nIR;
    wire [7:0] rIR;


    IR IR0 (
        .clk(clk),
        .wIR(wIR),
        .nIR(nIR),
        .rIR(rIR)
    );





    initial begin

        $dumpfile("IR_tb.vcd");
        $dumpvars(0, IR_tb);

        #1  nIR = 8'h00;
        #1  wIR = 1;
        #1  clk  = 1;
        #1  clk  = 0; 
        #1  wIR = 0;

        #1  nIR = 8'h10;
        #1  wIR = 1;
        #1  clk  = 1;
        #1  clk  = 0; 
        #1  wIR = 0;

        #1  nIR = 8'h20;
        #1  wIR = 0;

        #1  clk  = 1;
        #1  clk  = 0; 
        #1  wIR = 0;

        #1  nIR = 8'h30;
        #1  wIR = 1;
        #1  clk  = 1;
        #1  clk  = 0; 
        #1  wIR = 0;

        #10 $finish;
    end


endmodule
module IR_tb;


    reg clk  = 0;
    reg wIR = 0;

    reg  [7:0] nIR;
    wire [7:0] rIR;


    IR IR0 (
        .clk(clk),
        .wIR(wIR),
        .nIR(nIR),
        .rIR(rIR)
    );





    initial begin

        $dumpfile("IR_tb.vcd");
        $dumpvars(0, IR_tb);

        #1  nIR = 8'h00;
        #1  wIR = 1;
        #1  clk  = 1;
        #1  clk  = 0; 
        #1  wIR = 0;

        #1  nIR = 8'h10;
        #1  wIR = 1;
        #1  clk  = 1;
        #1  clk  = 0; 
        #1  wIR = 0;

        #1  nIR = 8'h20;
        #1  wIR = 0;

        #1  clk  = 1;
        #1  clk  = 0; 
        #1  wIR = 0;

        #1  nIR = 8'h30;
        #1  wIR = 1;
        #1  clk  = 1;
        #1  clk  = 0; 
        #1  wIR = 0;

        #10 $finish;
    end


endmodule