data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v
1: b'%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:22: Cannot find include file: urv_defs.v\n`include "urv_defs.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl,data/full_repos/permissive/161356276/urv_defs.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl,data/full_repos/permissive/161356276/urv_defs.v.v\n             data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl,data/full_repos/permissive/161356276/urv_defs.v.sv\n             urv_defs.v\n             urv_defs.v.v\n             urv_defs.v.sv\n             obj_dir/urv_defs.v\n             obj_dir/urv_defs.v.v\n             obj_dir/urv_defs.v.sv\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:87: Define or directive not defined: \'`EXCEPT_ILLEGAL_INSN\'\n csr_mip[`EXCEPT_ILLEGAL_INSN] <= except_vec_masked[0];\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:87: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n csr_mip[`EXCEPT_ILLEGAL_INSN] <= except_vec_masked[0];\n                             ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:88: Define or directive not defined: \'`EXCEPT_BREAKPOINT\'\n csr_mip[`EXCEPT_BREAKPOINT] <= except_vec_masked[1];\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:88: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n csr_mip[`EXCEPT_BREAKPOINT] <= except_vec_masked[1];\n                           ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:89: Define or directive not defined: \'`EXCEPT_UNALIGNED_LOAD\'\n csr_mip[`EXCEPT_UNALIGNED_LOAD]<= except_vec_masked[2];\n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:89: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n csr_mip[`EXCEPT_UNALIGNED_LOAD]<= except_vec_masked[2];\n                               ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:90: Define or directive not defined: \'`EXCEPT_UNALIGNED_STORE\'\n csr_mip[`EXCEPT_UNALIGNED_STORE] <= except_vec_masked[3];\n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:90: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n csr_mip[`EXCEPT_UNALIGNED_STORE] <= except_vec_masked[3];\n                                ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:91: Define or directive not defined: \'`EXCEPT_TIMER\'\n csr_mip[`EXCEPT_TIMER] <= except_vec_masked[4];\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:91: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n csr_mip[`EXCEPT_TIMER] <= except_vec_masked[4];\n                      ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:92: Define or directive not defined: \'`EXCEPT_IRQ\'\n csr_mip[`EXCEPT_IRQ] <= except_vec_masked[5];\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:92: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n csr_mip[`EXCEPT_IRQ] <= except_vec_masked[5];\n                    ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:104: Define or directive not defined: \'`CSR_ID_MIP\'\n if(!x_stall_i && !x_kill_i && d_is_csr_i && d_csr_sel_i == `CSR_ID_MIP) begin\n                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:104: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(!x_stall_i && !x_kill_i && d_is_csr_i && d_csr_sel_i == `CSR_ID_MIP) begin\n                                                                       ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:105: Define or directive not defined: \'`EXCEPT_ILLEGAL_INSN\'\n    except_vec_masked[0] <= x_csr_write_value_i [`EXCEPT_ILLEGAL_INSN];\n                                                 ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:106: Define or directive not defined: \'`EXCEPT_BREAKPOINT\'\n    except_vec_masked[1] <= x_csr_write_value_i [`EXCEPT_BREAKPOINT];\n                                                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:106: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    except_vec_masked[1] <= x_csr_write_value_i [`EXCEPT_BREAKPOINT];\n                                                                   ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:107: Define or directive not defined: \'`EXCEPT_UNALIGNED_LOAD\'\n    except_vec_masked[2] <= x_csr_write_value_i [`EXCEPT_UNALIGNED_LOAD];\n                                                 ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:107: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    except_vec_masked[2] <= x_csr_write_value_i [`EXCEPT_UNALIGNED_LOAD];\n                                                                       ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:108: Define or directive not defined: \'`EXCEPT_UNALIGNED_STORE\'\n    except_vec_masked[3] <= x_csr_write_value_i [`EXCEPT_UNALIGNED_STORE];\n                                                 ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:108: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    except_vec_masked[3] <= x_csr_write_value_i [`EXCEPT_UNALIGNED_STORE];\n                                                                        ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:109: Define or directive not defined: \'`EXCEPT_TIMER\'\n    except_vec_masked[4] <= x_csr_write_value_i [`EXCEPT_TIMER];\n                                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:109: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    except_vec_masked[4] <= x_csr_write_value_i [`EXCEPT_TIMER];\n                                                              ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:110: Define or directive not defined: \'`EXCEPT_IRQ\'\n    except_vec_masked[5] <= x_csr_write_value_i [`EXCEPT_IRQ];\n                                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:110: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    except_vec_masked[5] <= x_csr_write_value_i [`EXCEPT_IRQ];\n                                                            ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:116: syntax error, unexpected \'[\', expecting IDENTIFIER\n      except_vec_masked[1] <= 1\'b1;\n                       ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:119: syntax error, unexpected \'[\', expecting IDENTIFIER\n      except_vec_masked[2] <= 1\'b1;\n                       ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:122: syntax error, unexpected \'[\', expecting IDENTIFIER\n      except_vec_masked[3] <= 1\'b1;\n                       ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:125: syntax error, unexpected \'[\', expecting IDENTIFIER\n      except_vec_masked[4] <= csr_mie[`EXCEPT_TIMER] & csr_ie;\n                       ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:125: Define or directive not defined: \'`EXCEPT_TIMER\'\n      except_vec_masked[4] <= csr_mie[`EXCEPT_TIMER] & csr_ie;\n                                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:128: syntax error, unexpected \'[\', expecting IDENTIFIER\n      except_vec_masked[5] <= csr_mie[`EXCEPT_IRQ] & csr_ie;\n                       ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:128: Define or directive not defined: \'`EXCEPT_IRQ\'\n      except_vec_masked[5] <= csr_mie[`EXCEPT_IRQ] & csr_ie;\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:141: Define or directive not defined: \'`EXCEPT_ILLEGAL_INSN\'\n       cause <= `EXCEPT_ILLEGAL_INSN;\n                ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:141: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       cause <= `EXCEPT_ILLEGAL_INSN;\n                                    ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:143: Define or directive not defined: \'`EXCEPT_BREAKPOINT\'\n       cause <= `EXCEPT_BREAKPOINT;\n                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:143: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       cause <= `EXCEPT_BREAKPOINT;\n                                  ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:145: Define or directive not defined: \'`EXCEPT_UNALIGNED_LOAD\'\n       cause <= `EXCEPT_UNALIGNED_LOAD;\n                ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:145: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       cause <= `EXCEPT_UNALIGNED_LOAD;\n                                      ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:147: Define or directive not defined: \'`EXCEPT_UNALIGNED_STORE\'\n       cause <= `EXCEPT_UNALIGNED_STORE;\n                ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:147: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       cause <= `EXCEPT_UNALIGNED_STORE;\n                                       ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:149: Define or directive not defined: \'`EXCEPT_TIMER\'\n       cause <= `EXCEPT_TIMER;\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:149: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       cause <= `EXCEPT_TIMER;\n                             ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:151: Define or directive not defined: \'`EXCEPT_IRQ\'\n       cause <= `EXCEPT_IRQ;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:151: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       cause <= `EXCEPT_IRQ;\n                           ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:174: Define or directive not defined: \'`CSR_ID_MSTATUS\'\n        `CSR_ID_MSTATUS: \n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:174: syntax error, unexpected \':\', expecting endcase\n        `CSR_ID_MSTATUS: \n                       ^\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:176: Define or directive not defined: \'`CSR_ID_MEPC\'\n        `CSR_ID_MEPC: \n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:178: Define or directive not defined: \'`CSR_ID_MIE\'\n        `CSR_ID_MIE:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/ip_cores/urv-core/rtl/urv_exceptions.v:180: Define or directive not defined: \'`EXCEPT_ILLEGAL_INSN\'\n      csr_mie[`EXCEPT_ILLEGAL_INSN] <= 1;\n              ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module urv_exceptions
  (
   input 	 clk_i,
   input 	 rst_i,

   input 	 x_stall_i,
   input 	 x_kill_i,
  
   input 	 d_is_csr_i,
   input 	 d_is_eret_i,
  
   input [2:0] 	 d_fun_i,
   input [4:0] 	 d_csr_imm_i,
   input [11:0]  d_csr_sel_i,
  
   input 	 exp_irq_i,
   input 	 exp_tick_i,
   input 	 exp_breakpoint_i,
   input 	 exp_unaligned_load_i,
   input 	 exp_unaligned_store_i,
   input 	 exp_invalid_insn_i,

   input [31:0]  x_csr_write_value_i,
  
   output 	 x_exception_o,
   input [31:0]  x_exception_pc_i,
   output [31:0] x_exception_pc_o,
   output [31:0] x_exception_vector_o,
  
   output [31:0] csr_mstatus_o,
   output [31:0] csr_mip_o,
   output [31:0] csr_mie_o,
   output [31:0] csr_mepc_o,
   output [31:0] csr_mcause_o

   );

   

   reg [31:0] 	 csr_mepc;
   reg [31:0] 	 csr_mie;
   reg 		 csr_ie;

   reg [3:0] 	 csr_mcause;
   
   reg 		 exception;
   reg [3:0] 	 cause;

   reg [5:0] 	 except_vec_masked;

   assign csr_mcause_o = {28'h0, csr_mcause};
   assign csr_mepc_o = csr_mepc;
   assign csr_mie_o = csr_mie;
   assign csr_mstatus_o[0] = csr_ie;
   assign csr_mstatus_o[31:1] = 0;
   
   reg [31:0] 	 csr_mip;

   always@*
     begin
	csr_mip <= 0;
	csr_mip[`EXCEPT_ILLEGAL_INSN] <= except_vec_masked[0];
	csr_mip[`EXCEPT_BREAKPOINT] <= except_vec_masked[1];
	csr_mip[`EXCEPT_UNALIGNED_LOAD]<= except_vec_masked[2];
	csr_mip[`EXCEPT_UNALIGNED_STORE] <= except_vec_masked[3];
	csr_mip[`EXCEPT_TIMER] <= except_vec_masked[4];
	csr_mip[`EXCEPT_IRQ] <= except_vec_masked[5];
     end
   

   assign csr_mip_o = csr_mip;
   
   
   
   always@(posedge clk_i)
     if (rst_i)
       except_vec_masked <= 0;
     else begin
	if(!x_stall_i && !x_kill_i && d_is_csr_i && d_csr_sel_i == `CSR_ID_MIP) begin
	   except_vec_masked[0] <= x_csr_write_value_i [`EXCEPT_ILLEGAL_INSN];
	   except_vec_masked[1] <= x_csr_write_value_i [`EXCEPT_BREAKPOINT];
	   except_vec_masked[2] <= x_csr_write_value_i [`EXCEPT_UNALIGNED_LOAD];
	   except_vec_masked[3] <= x_csr_write_value_i [`EXCEPT_UNALIGNED_STORE];
	   except_vec_masked[4] <= x_csr_write_value_i [`EXCEPT_TIMER];
	   except_vec_masked[5] <= x_csr_write_value_i [`EXCEPT_IRQ];
	end else begin
	   if ( exp_invalid_insn_i )
	     except_vec_masked[0] <= 1'b1;

	   if ( exp_breakpoint_i )
	     except_vec_masked[1] <= 1'b1;

	   if ( exp_unaligned_load_i )
	     except_vec_masked[2] <= 1'b1;

	   if ( exp_unaligned_store_i )
	     except_vec_masked[3] <= 1'b1;

	   if ( exp_tick_i )
	     except_vec_masked[4] <= csr_mie[`EXCEPT_TIMER] & csr_ie;

	   if( exp_irq_i )
	     except_vec_masked[5] <= csr_mie[`EXCEPT_IRQ] & csr_ie;
	end
     end
   
   always@*
     exception <= |except_vec_masked | exp_invalid_insn_i;

   reg exception_pending;

   assign x_exception_vector_o = 'h8;
   
   always@*
     if(exp_invalid_insn_i || except_vec_masked[0])
       cause <= `EXCEPT_ILLEGAL_INSN;
     else if (except_vec_masked[1])
       cause <= `EXCEPT_BREAKPOINT;
     else if (except_vec_masked[2])
       cause <= `EXCEPT_UNALIGNED_LOAD;
     else if (except_vec_masked[3])
       cause <= `EXCEPT_UNALIGNED_STORE;
     else if (except_vec_masked[4])
       cause <= `EXCEPT_TIMER;
     else
       cause <= `EXCEPT_IRQ;
   
   always@(posedge clk_i)
     if(rst_i) 
       begin
	  csr_mepc <= 0;
	  csr_mie <= 0;
	  csr_ie <= 0;
	  exception_pending <= 0;
	  
       end else if(!x_stall_i && !x_kill_i) begin
	  if ( d_is_eret_i )
	    exception_pending <= 0;

          if ( !exception_pending && exception )
	    begin
	       csr_mepc <= x_exception_pc_i;
	       csr_mcause <= cause;
	       exception_pending <= 1;
	    end 

	  if(d_is_csr_i) begin
	     case (d_csr_sel_i)
	       `CSR_ID_MSTATUS: 
		 csr_ie <= x_csr_write_value_i[0];
	       `CSR_ID_MEPC: 
		 csr_mepc <= x_csr_write_value_i;
	       `CSR_ID_MIE:
		 begin
		    csr_mie[`EXCEPT_ILLEGAL_INSN] <= 1;
		    csr_mie[`EXCEPT_BREAKPOINT] <= 1;
		    csr_mie[`EXCEPT_UNALIGNED_LOAD] <= 1;
		    csr_mie[`EXCEPT_UNALIGNED_STORE] <= 1;
		    csr_mie[`EXCEPT_TIMER] <= x_csr_write_value_i [`EXCEPT_TIMER];
		    csr_mie[`EXCEPT_IRQ] <= x_csr_write_value_i [`EXCEPT_IRQ];
		 end
	     endcase

	  end
       end
   

   assign x_exception_pc_o = csr_mepc;
   assign x_exception_o = exception & !exception_pending;
   
endmodule
module urv_exceptions
  (
   input 	 clk_i,
   input 	 rst_i,

   input 	 x_stall_i,
   input 	 x_kill_i,
  
   input 	 d_is_csr_i,
   input 	 d_is_eret_i,
  
   input [2:0] 	 d_fun_i,
   input [4:0] 	 d_csr_imm_i,
   input [11:0]  d_csr_sel_i,
  
   input 	 exp_irq_i,
   input 	 exp_tick_i,
   input 	 exp_breakpoint_i,
   input 	 exp_unaligned_load_i,
   input 	 exp_unaligned_store_i,
   input 	 exp_invalid_insn_i,

   input [31:0]  x_csr_write_value_i,
  
   output 	 x_exception_o,
   input [31:0]  x_exception_pc_i,
   output [31:0] x_exception_pc_o,
   output [31:0] x_exception_vector_o,
  
   output [31:0] csr_mstatus_o,
   output [31:0] csr_mip_o,
   output [31:0] csr_mie_o,
   output [31:0] csr_mepc_o,
   output [31:0] csr_mcause_o

   );


   

   reg [31:0] 	 csr_mepc;
   reg [31:0] 	 csr_mie;
   reg 		 csr_ie;

   reg [3:0] 	 csr_mcause;
   
   reg 		 exception;
   reg [3:0] 	 cause;

   reg [5:0] 	 except_vec_masked;

   assign csr_mcause_o = {28'h0, csr_mcause};
   assign csr_mepc_o = csr_mepc;
   assign csr_mie_o = csr_mie;
   assign csr_mstatus_o[0] = csr_ie;
   assign csr_mstatus_o[31:1] = 0;
   
   reg [31:0] 	 csr_mip;

   always@*
     begin
	csr_mip <= 0;
	csr_mip[`EXCEPT_ILLEGAL_INSN] <= except_vec_masked[0];
	csr_mip[`EXCEPT_BREAKPOINT] <= except_vec_masked[1];
	csr_mip[`EXCEPT_UNALIGNED_LOAD]<= except_vec_masked[2];
	csr_mip[`EXCEPT_UNALIGNED_STORE] <= except_vec_masked[3];
	csr_mip[`EXCEPT_TIMER] <= except_vec_masked[4];
	csr_mip[`EXCEPT_IRQ] <= except_vec_masked[5];
     end
   

   assign csr_mip_o = csr_mip;
   
   
   
   always@(posedge clk_i)
     if (rst_i)
       except_vec_masked <= 0;
     else begin
	if(!x_stall_i && !x_kill_i && d_is_csr_i && d_csr_sel_i == `CSR_ID_MIP) begin
	   except_vec_masked[0] <= x_csr_write_value_i [`EXCEPT_ILLEGAL_INSN];
	   except_vec_masked[1] <= x_csr_write_value_i [`EXCEPT_BREAKPOINT];
	   except_vec_masked[2] <= x_csr_write_value_i [`EXCEPT_UNALIGNED_LOAD];
	   except_vec_masked[3] <= x_csr_write_value_i [`EXCEPT_UNALIGNED_STORE];
	   except_vec_masked[4] <= x_csr_write_value_i [`EXCEPT_TIMER];
	   except_vec_masked[5] <= x_csr_write_value_i [`EXCEPT_IRQ];
	end else begin
	   if ( exp_invalid_insn_i )
	     except_vec_masked[0] <= 1'b1;

	   if ( exp_breakpoint_i )
	     except_vec_masked[1] <= 1'b1;

	   if ( exp_unaligned_load_i )
	     except_vec_masked[2] <= 1'b1;

	   if ( exp_unaligned_store_i )
	     except_vec_masked[3] <= 1'b1;

	   if ( exp_tick_i )
	     except_vec_masked[4] <= csr_mie[`EXCEPT_TIMER] & csr_ie;

	   if( exp_irq_i )
	     except_vec_masked[5] <= csr_mie[`EXCEPT_IRQ] & csr_ie;
	end
     end
   
   always@*
     exception <= |except_vec_masked | exp_invalid_insn_i;

   reg exception_pending;

   assign x_exception_vector_o = 'h8;
   
   always@*
     if(exp_invalid_insn_i || except_vec_masked[0])
       cause <= `EXCEPT_ILLEGAL_INSN;
     else if (except_vec_masked[1])
       cause <= `EXCEPT_BREAKPOINT;
     else if (except_vec_masked[2])
       cause <= `EXCEPT_UNALIGNED_LOAD;
     else if (except_vec_masked[3])
       cause <= `EXCEPT_UNALIGNED_STORE;
     else if (except_vec_masked[4])
       cause <= `EXCEPT_TIMER;
     else
       cause <= `EXCEPT_IRQ;
   
   always@(posedge clk_i)
     if(rst_i) 
       begin
	  csr_mepc <= 0;
	  csr_mie <= 0;
	  csr_ie <= 0;
	  exception_pending <= 0;
	  
       end else if(!x_stall_i && !x_kill_i) begin
	  if ( d_is_eret_i )
	    exception_pending <= 0;

          if ( !exception_pending && exception )
	    begin
	       csr_mepc <= x_exception_pc_i;
	       csr_mcause <= cause;
	       exception_pending <= 1;
	    end 

	  if(d_is_csr_i) begin
	     case (d_csr_sel_i)
	       `CSR_ID_MSTATUS: 
		 csr_ie <= x_csr_write_value_i[0];
	       `CSR_ID_MEPC: 
		 csr_mepc <= x_csr_write_value_i;
	       `CSR_ID_MIE:
		 begin
		    csr_mie[`EXCEPT_ILLEGAL_INSN] <= 1;
		    csr_mie[`EXCEPT_BREAKPOINT] <= 1;
		    csr_mie[`EXCEPT_UNALIGNED_LOAD] <= 1;
		    csr_mie[`EXCEPT_UNALIGNED_STORE] <= 1;
		    csr_mie[`EXCEPT_TIMER] <= x_csr_write_value_i [`EXCEPT_TIMER];
		    csr_mie[`EXCEPT_IRQ] <= x_csr_write_value_i [`EXCEPT_IRQ];
		 end
	     endcase

	  end
       end
   

   assign x_exception_pc_o = csr_mepc;
   assign x_exception_o = exception & !exception_pending;
   
endmodule