data/full_repos/permissive/216615048/src/simulation/rca_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/216615048/src/simulation/rca_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/216615048/src/simulation/rca_tb.v:9: Cannot find file containing module: \'ripple\'\nripple rca(a,b,out,cout);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/ripple\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/ripple.v\n             data/full_repos/permissive/216615048/src/simulation,data/full_repos/permissive/216615048/ripple.sv\n             ripple\n             ripple.v\n             ripple.sv\n             obj_dir/ripple\n             obj_dir/ripple.v\n             obj_dir/ripple.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rca_tb();
reg [31:0]a;
reg [31:0]b;
wire [31:0]out;
wire cout;

ripple rca(a,b,out,cout);

initial begin

a=2;
b=2;
#100
a=2;
b=3;



end
endmodule
module rca_tb();

reg [31:0]a;
reg [31:0]b;
wire [31:0]out;
wire cout;

ripple rca(a,b,out,cout);

initial begin

a=2;
b=2;
#100
a=2;
b=3;



end
endmodule