data/full_repos/permissive/157049472/Verilog Test Benches/Data_memory_tb.v
None: at end of input
1: b'%Error: Cannot find file containing module: Test\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Test\n             data/full_repos/permissive/157049472/Verilog/Test.v\n             data/full_repos/permissive/157049472/Verilog/Test.sv\n             Test\n             Test.v\n             Test.sv\n             obj_dir/Test\n             obj_dir/Test.v\n             obj_dir/Test.sv\n%Error: Cannot find file containing module: Benches,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Benches/Data_memory_tb.v\n%Error: Exiting due to 4 error(s)\n'
module Data_memory_tb;


	reg clk;
	reg rst;
	reg [9:0] address;
	reg [31:0] data_in;
	reg MemRead;
	reg MemWrite;


	wire [31:0] data_out;


	Data_memory uut (
		.clk(clk), 
		.rst(rst), 
		.address(address), 
		.data_in(data_in), 
		.MemRead(MemRead), 
		.MemWrite(MemWrite), 
		.data_out(data_out)
	);

	initial begin

		clk = 0;
		rst = 0;
		address = 0;
		data_in = 0;
		MemRead = 0;
		MemWrite = 0;


		#100;
        

		rst = 1;
		#10 rst = 0;

		#10;
		address = 12;
		data_in = 32'd798;
		MemRead = 1;
		MemWrite = 0;

		#10;
		address = 9;
		data_in = 32'd748;
		MemRead = 0;
		MemWrite = 1;

		#10;
		address = 14;
		data_in = 32'd543;
		MemRead = 0;
		MemWrite = 0;



		#10;
		address = 0;
		data_in = 32'd2;
		MemRead = 1;
		MemWrite = 0;

		#10;
		address = 0;
		data_in = 32'd2;
		MemRead = 0;
		MemWrite = 1;

		#10;
		address = 0;
		data_in = 32'd2;
		MemRead = 1;
		MemWrite = 0;

	end
     always
     begin
     	#5 clk = ~clk;
     end
endmodule
module Data_memory_tb;



	reg clk;
	reg rst;
	reg [9:0] address;
	reg [31:0] data_in;
	reg MemRead;
	reg MemWrite;


	wire [31:0] data_out;


	Data_memory uut (
		.clk(clk), 
		.rst(rst), 
		.address(address), 
		.data_in(data_in), 
		.MemRead(MemRead), 
		.MemWrite(MemWrite), 
		.data_out(data_out)
	);

	initial begin

		clk = 0;
		rst = 0;
		address = 0;
		data_in = 0;
		MemRead = 0;
		MemWrite = 0;


		#100;
        

		rst = 1;
		#10 rst = 0;

		#10;
		address = 12;
		data_in = 32'd798;
		MemRead = 1;
		MemWrite = 0;

		#10;
		address = 9;
		data_in = 32'd748;
		MemRead = 0;
		MemWrite = 1;

		#10;
		address = 14;
		data_in = 32'd543;
		MemRead = 0;
		MemWrite = 0;



		#10;
		address = 0;
		data_in = 32'd2;
		MemRead = 1;
		MemWrite = 0;

		#10;
		address = 0;
		data_in = 32'd2;
		MemRead = 0;
		MemWrite = 1;

		#10;
		address = 0;
		data_in = 32'd2;
		MemRead = 1;
		MemWrite = 0;

	end
     always
     begin
     	#5 clk = ~clk;
     end
endmodule