data/full_repos/permissive/191834901/VerilogHDL/mainMemory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/191834901/VerilogHDL/mainMemory.v:20: Multiple top level modules\n                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                  : ... Top module \'instMemory\'\nmodule instMemory #(parameter instructionW=32, parameter addrW=16) (\n       ^~~~~~~~~~\n                                                                                  : ... Top module \'dataMemory\'\nmodule dataMemory #(parameter dataW=32, parameter addrW=16) (\n       ^~~~~~~~~~\n                                                                                  : ... Top module \'controlPathDriver\'\nmodule controlPathDriver #(parameter controlWordWidth=16, parameter caddrW=16) (\n       ^~~~~~~~~~~~~~~~~\n                                                                                  : ... Top module \'registerFile\'\nmodule registerFile #(parameter dataWidth=32, parameter addrWidth=5) (\n       ^~~~~~~~~~~~\n                                                                                  : ... Top module \'registerNx\'\nmodule registerNx #(parameter regWidth=8)(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module CP_RFormatDecoder(
	output [3:0]ALUSelr,
	input  [3:0]CW
);
	assign ALUSelr[3] = ((CW[3] & ~CW[2]));
	assign ALUSelr[2] = ((CW[3]) | (~CW[1] & CW[0]) | (~CW[2] & CW[1]));
	assign ALUSelr[1] = ((~CW[2] & CW[0]) | (~CW[2] & CW[1]) | (CW[2] & ~CW[0]));
	assign ALUSelr[0] = ((~CW[2] & CW[1]) | (CW[1] & CW[0]) | (CW[3] & CW[0]) | (CW[2] & ~CW[1] & ~CW[0]));
endmodule
module CP_RFormatDecoder(
	output [3:0]ALUSelr,
	input  [3:0]CW
);

	assign ALUSelr[3] = ((CW[3] & ~CW[2]));
	assign ALUSelr[2] = ((CW[3]) | (~CW[1] & CW[0]) | (~CW[2] & CW[1]));
	assign ALUSelr[1] = ((~CW[2] & CW[0]) | (~CW[2] & CW[1]) | (CW[2] & ~CW[0]));
	assign ALUSelr[0] = ((~CW[2] & CW[1]) | (CW[1] & CW[0]) | (CW[3] & CW[0]) | (CW[2] & ~CW[1] & ~CW[0]));
endmodule