data/full_repos/permissive/113839829/Source/CPU/inst_rom.v
'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte
1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:5: Cannot find include file: defines.v\n `include "defines.v" \n          ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n             data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:9: Define or directive not defined: \'`InstAddrBus\'\n  input wire [`InstAddrBus]  addr,\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  input wire [`InstAddrBus]  addr,\n                          ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:11: Define or directive not defined: \'`InstBus\'\n  output reg [`InstBus]     inst,\n              ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:14: Define or directive not defined: \'`InstAddrBus\'\n  output wire [`InstAddrBus] pdt_pc,\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:15: Define or directive not defined: \'`InstBus\'\n  output reg [`InstBus]     pdt_inst\n              ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:20: Define or directive not defined: \'`InstBus\'\n   reg[`InstBus]  inst_mem[0:`InstMemNum];\n       ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   reg[`InstBus]  inst_mem[0:`InstMemNum];\n               ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:20: Define or directive not defined: \'`InstMemNum\'\n   reg[`InstBus]  inst_mem[0:`InstMemNum];\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:26: Define or directive not defined: \'`ChipDisable\'\n if (ce == `ChipDisable) inst <= `ZeroWord;\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:26: Define or directive not defined: \'`ZeroWord\'\n if (ce == `ChipDisable) inst <= `ZeroWord;\n                                 ^~~~~~~~~\n%Error: Exiting due to 11 error(s)\n'
module inst_rom(
		input wire 		   ce,
		input wire [`InstAddrBus]  addr,

		output reg [`InstBus] 	   inst,


		output wire [`InstAddrBus] pdt_pc,
		output reg [`InstBus] 	   pdt_inst
	      );

   assign pdt_pc = addr;
   
   reg[`InstBus]  inst_mem[0:`InstMemNum];
   
   initial $readmemh ("instr.data",inst_mem);

   always @ (*)
     begin
	if (ce == `ChipDisable) inst <= `ZeroWord;
	else
	  begin
	     inst <= {inst_mem[addr>>2][7:0],inst_mem[addr>>2][15:8],
		      inst_mem[addr>>2][23:16],inst_mem[addr>>2][31:24]};
	     pdt_inst <= {inst_mem[addr>>2][7:0],inst_mem[addr>>2][15:8],
			  inst_mem[addr>>2][23:16],inst_mem[addr>>2][31:24]};
	  end
     end

endmodule
module inst_rom(
		input wire 		   ce,
		input wire [`InstAddrBus]  addr,

		output reg [`InstBus] 	   inst,


		output wire [`InstAddrBus] pdt_pc,
		output reg [`InstBus] 	   pdt_inst
	      );


   assign pdt_pc = addr;
   
   reg[`InstBus]  inst_mem[0:`InstMemNum];
   
   initial $readmemh ("instr.data",inst_mem);

   always @ (*)
     begin
	if (ce == `ChipDisable) inst <= `ZeroWord;
	else
	  begin
	     inst <= {inst_mem[addr>>2][7:0],inst_mem[addr>>2][15:8],
		      inst_mem[addr>>2][23:16],inst_mem[addr>>2][31:24]};
	     pdt_inst <= {inst_mem[addr>>2][7:0],inst_mem[addr>>2][15:8],
			  inst_mem[addr>>2][23:16],inst_mem[addr>>2][31:24]};
	  end
     end

endmodule