data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/control/binary_encoder.v
data/verilator_xmls/ad209284-e4a9-4c56-8f6b-cdf16c3d0c3e.xml
module binary_encoder
#(
      parameter SIZE = 16
)
(
       input [SIZE-1:0] in,
       output [`log2(SIZE)-1:0] out
);

  genvar m,n;

  generate

  for (m = 0; m <= `log2(SIZE-1); m = m + 1)  begin: expand_or_tree
    wire [SIZE-1:0] encoding;

     for (n = 0; n < SIZE ; n = n + 1) begin: encode_this_bit
       assign encoding[n] = n[m];
     end

     assign out[m] = |(encoding & in);
   end
 endgenerate

endmodule
module binary_encoder
#(
      parameter SIZE = 16
)
(
       input [SIZE-1:0] in,
       output [`log2(SIZE)-1:0] out
);


  genvar m,n;

  generate

  for (m = 0; m <= `log2(SIZE-1); m = m + 1)  begin: expand_or_tree
    wire [SIZE-1:0] encoding;

     for (n = 0; n < SIZE ; n = n + 1) begin: encode_this_bit
       assign encoding[n] = n[m];
     end

     assign out[m] = |(encoding & in);
   end
 endgenerate

endmodule