data/full_repos/permissive/111901713/testbench/test_aes_192.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/111901713/testbench/test_aes_192.v:48: syntax error, unexpected \'@\'\n        @ (negedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #230;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/111901713/testbench/test_aes_192.v:68: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_aes_192;


	reg clk;
	reg [127:0] state;
	reg [191:0] key;


	wire [127:0] out;


	aes_192 uut (
		.clk(clk), 
		.state(state), 
		.key(key), 
		.out(out)
	);

	initial begin
		clk = 0;
		state = 0;
		key = 0;

		#100;

        @ (negedge clk);
        #2;
        state = 128'h3243f6a8885a308d313198a2e0370734;
        key   = 192'h2b7e151628aed2a6abf7158809cf4f3c762e7160f38b4da5;
        #10;
        state = 128'h00112233445566778899aabbccddeeff;
        key   = 192'h000102030405060708090a0b0c0d0e0f1011121314151617;
        #10;
        state = 128'h0;
        key   = 192'h0;
        #230;
        if (out !== 128'hf9fb29aefc384a250340d833b87ebc00)
          begin $display("E"); $finish; end
        #10;
        if (out !== 128'hdda97ca4864cdfe06eaf70a0ec0d7191)
          begin $display("E"); $finish; end
        $display("Good.");
        $finish;
	end
      
    always #5 clk = ~clk;
endmodule
module test_aes_192;



	reg clk;
	reg [127:0] state;
	reg [191:0] key;


	wire [127:0] out;


	aes_192 uut (
		.clk(clk), 
		.state(state), 
		.key(key), 
		.out(out)
	);

	initial begin
		clk = 0;
		state = 0;
		key = 0;

		#100;

        @ (negedge clk);
        #2;
        state = 128'h3243f6a8885a308d313198a2e0370734;
        key   = 192'h2b7e151628aed2a6abf7158809cf4f3c762e7160f38b4da5;
        #10;
        state = 128'h00112233445566778899aabbccddeeff;
        key   = 192'h000102030405060708090a0b0c0d0e0f1011121314151617;
        #10;
        state = 128'h0;
        key   = 192'h0;
        #230;
        if (out !== 128'hf9fb29aefc384a250340d833b87ebc00)
          begin $display("E"); $finish; end
        #10;
        if (out !== 128'hdda97ca4864cdfe06eaf70a0ec0d7191)
          begin $display("E"); $finish; end
        $display("Good.");
        $finish;
	end
      
    always #5 clk = ~clk;
endmodule