data/full_repos/permissive/11584509/ICARUS-LX150/serial.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/11584509/ICARUS-LX150/serial.v:92: Multiple top level modules\n                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                               : ... Top module \'serial_receive\'\nmodule serial_receive # (\n       ^~~~~~~~~~~~~~\n                                                                               : ... Top module \'serial_transmit\'\nmodule serial_transmit # (\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/ICARUS-LX150/serial.v:148: Cannot find file containing module: \'uart_transmitter\'\n   uart_transmitter #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) utx (.clk(clk), .uart_tx(TxD), .rx_new_byte(TxD_start), .rx_byte(out_byte), .tx_ready(TxD_ready));\n   ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/11584509/ICARUS-LX150,data/full_repos/permissive/11584509/uart_transmitter\n             data/full_repos/permissive/11584509/ICARUS-LX150,data/full_repos/permissive/11584509/uart_transmitter.v\n             data/full_repos/permissive/11584509/ICARUS-LX150,data/full_repos/permissive/11584509/uart_transmitter.sv\n             uart_transmitter\n             uart_transmitter.v\n             uart_transmitter.sv\n             obj_dir/uart_transmitter\n             obj_dir/uart_transmitter.v\n             obj_dir/uart_transmitter.sv\n%Error: data/full_repos/permissive/11584509/ICARUS-LX150/serial.v:26: Cannot find file containing module: \'uart_receiver\'\n   uart_receiver #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) urx (.clk(clk), .uart_rx(RxD), .tx_new_byte(RxD_data_ready), .tx_byte(RxD_data));\n   ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module serial_transmit # (
   parameter baud_rate = 115_200,
   parameter comm_clk_frequency = 100_000_000 )
  (clk, TxD, busy, send, word);
   


   wire TxD_start;
   wire TxD_ready;
   
   reg [7:0]  out_byte = 0;
   reg        serial_start = 0;
   reg [3:0]  mux_state = 4'b0000;

   assign TxD_start = serial_start;

   input      clk;
   output     TxD;
   
   input [31:0] word;
   input 	send;
   output 	busy;

   reg [31:0] 	word_copy = 0;
   
   assign busy = (|mux_state);

   always @(posedge clk)
     begin




	if (!busy && send)
	  begin
	     mux_state <= 4'b1000;
	     word_copy <= word;
	  end  

	else if (mux_state[3] && ~mux_state[0] && TxD_ready)
	  begin
	     serial_start <= 1;
	     mux_state <= mux_state + 1;

	     out_byte <= word_copy[31:24];
	     word_copy <= (word_copy << 8);
	  end
	

	else if (mux_state[3] && mux_state[0])
	  begin
	     serial_start <= 0;
	     if (TxD_ready) mux_state <= mux_state + 1;
	  end
     end

   uart_transmitter #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) utx (.clk(clk), .uart_tx(TxD), .rx_new_byte(TxD_start), .rx_byte(out_byte), .tx_ready(TxD_ready));

endmodule
module serial_transmit # (
   parameter baud_rate = 115_200,
   parameter comm_clk_frequency = 100_000_000 )
  (clk, TxD, busy, send, word);

   


   wire TxD_start;
   wire TxD_ready;
   
   reg [7:0]  out_byte = 0;
   reg        serial_start = 0;
   reg [3:0]  mux_state = 4'b0000;

   assign TxD_start = serial_start;

   input      clk;
   output     TxD;
   
   input [31:0] word;
   input 	send;
   output 	busy;

   reg [31:0] 	word_copy = 0;
   
   assign busy = (|mux_state);

   always @(posedge clk)
     begin




	if (!busy && send)
	  begin
	     mux_state <= 4'b1000;
	     word_copy <= word;
	  end  

	else if (mux_state[3] && ~mux_state[0] && TxD_ready)
	  begin
	     serial_start <= 1;
	     mux_state <= mux_state + 1;

	     out_byte <= word_copy[31:24];
	     word_copy <= (word_copy << 8);
	  end
	

	else if (mux_state[3] && mux_state[0])
	  begin
	     serial_start <= 0;
	     if (TxD_ready) mux_state <= mux_state + 1;
	  end
     end

   uart_transmitter #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) utx (.clk(clk), .uart_tx(TxD), .rx_new_byte(TxD_start), .rx_byte(out_byte), .tx_ready(TxD_ready));

endmodule