data/full_repos/permissive/15431697/src/bridge_tb.v
 line:1051: before: "else"
1: b'%Error: data/full_repos/permissive/15431697/src/bridge_tb.v:1: Cannot find include file: bridge.v\n`include "bridge.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/15431697/src,data/full_repos/permissive/15431697/bridge.v\n             data/full_repos/permissive/15431697/src,data/full_repos/permissive/15431697/bridge.v.v\n             data/full_repos/permissive/15431697/src,data/full_repos/permissive/15431697/bridge.v.sv\n             bridge.v\n             bridge.v.v\n             bridge.v.sv\n             obj_dir/bridge.v\n             obj_dir/bridge.v.v\n             obj_dir/bridge.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/15431697/src/bridge_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk <= ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module bridge_tb();
reg clk;

bridge U0(
);

initial begin
  clk <= 0;

  forever begin
    #10 clk <= ~clk;
  end
end
endmodule
module bridge_tb();

reg clk;

bridge U0(
);

initial begin
  clk <= 0;

  forever begin
    #10 clk <= ~clk;
  end
end
endmodule