data/full_repos/permissive/100975158/MIPS32_Full/UART/UART_Clock_Generator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/100975158/MIPS32_Full/UART/UART_Clock_Generator.v:22: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'uart_tick_16\' generates 1 bits.\n                                                                                               : ... In instance UART_Clock_Generator\n    assign uart_tick = (uart_tick_16 == 4\'d1 && counter == 4\'d15);\n                                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module UART_Clock_Generator (
    input   clock,
    output  uart_tick,
    output  uart_tick_16
);

    reg [12:0] accumulator = 13'd0;
    always @ (posedge clock) begin

        accumulator <= accumulator[11:0] + 12'd151;
    end

    assign uart_tick_16 = (accumulator[12]);


    reg [3:0] counter = 4'd0;
    always @ (posedge clock) begin
        counter <= (uart_tick_16) ? counter + 1'b1 : counter;
    end
    assign uart_tick = (uart_tick_16 == 4'd1 && counter == 4'd15);


endmodule
module UART_Clock_Generator (
    input   clock,
    output  uart_tick,
    output  uart_tick_16
);


    reg [12:0] accumulator = 13'd0;
    always @ (posedge clock) begin

        accumulator <= accumulator[11:0] + 12'd151;
    end

    assign uart_tick_16 = (accumulator[12]);


    reg [3:0] counter = 4'd0;
    always @ (posedge clock) begin
        counter <= (uart_tick_16) ? counter + 1'b1 : counter;
    end
    assign uart_tick = (uart_tick_16 == 4'd1 && counter == 4'd15);


endmodule