data/full_repos/permissive/153866423/_magiccubeImageProcess.srcs/magiccubeImageProcess.srcs_18_12_07/sources_1/imports/MyScripts/sram/image_in_sram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/153866423/_magiccubeImageProcess.srcs/magiccubeImageProcess.srcs_18_12_07/sources_1/imports/MyScripts/sram/image_in_sram.v:120: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s VARREF \'cam_addr\' generates 17 bits.\n                                                                                                                                                                         : ... In instance image_in_sram\n                    addr_wr_in_sram <= cam_addr;\n                                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module image_in_sram #(parameter H_cnt_max=320,
                       parameter V_cnt_max=240) (
    input wclk, 
    input rst,

    input enable,

    input[16:0] cam_addr,
    input[15:0] cam_data,
    input cam_we,

    output reg selec_in_sram,
    output reg write_in_sram,
    output reg read_in_sram,
    output reg[15:0] data_wr_in_in_sram,
    output reg[18:0] addr_wr_in_sram,


    output reg done
);

    reg[9:0] H_cnt;
    reg[9:0] V_cnt;
    
localparam address_count_max = H_cnt_max * V_cnt_max - 1;


localparam s_idle           = 4'b0000;
localparam s_init           = 4'b0001;
localparam s_write1         = 4'b0011;
localparam s_write2         = 4'b0010;
localparam s_done           = 4'b0110;
localparam s_ready          = 4'b0111;
reg [3:0] status = s_idle;

localparam[9:0] h_zuoshang=40,
                h_zhongshang=120, 
                h_youshang=200,     
                h_zuozhong=40,
                h_zhongzhong=120,
                h_youzhong=200,
                h_zuoxia=40,
                h_zhongxia=120, 
                h_youxia=200;
localparam[9:0] v_zuoshang=40,
                v_zhongshang=40,
                v_youshang=40,
                v_zuozhong=120,
                v_zhongzhong=120,
                v_youzhong=120,
                v_zuoxia=200,
                v_zhongxia=200,
                v_youxia=200;
localparam[15:0] red = 16'b1111100000000000;
localparam[15:0] green = 16'b0000011111100000;
localparam[15:0] blue = 16'b0000000000011111;
localparam[15:0] AAA = 16'b1111100000011111;
localparam[15:0] BBB = 16'b0000011111111111;
localparam[15:0] CCC = 16'b1111111111100000;
localparam[15:0] white = 16'b1111111111111111;
localparam[15:0] black = 16'b0000000000000000;

always@(posedge wclk) begin
    if(rst) begin
        selec_in_sram <= 0;
        write_in_sram <= 0;
        read_in_sram <= 0;
        data_wr_in_in_sram <= 0;
        addr_wr_in_sram <= 0;
        done <= 0;

        status <= s_idle;
    end else begin
        case(status) 
            s_idle: begin
                done <= 0;            
                selec_in_sram <= 0;
                write_in_sram <= 0;
                read_in_sram <= 0;
                data_wr_in_in_sram <= 0;
                addr_wr_in_sram <= 0;

                if(enable) begin
                    status <= s_init;
                end else begin
                    status <= s_idle;
                end
            end
            s_init: begin
                if(enable) begin
                    status <= s_init;
                end else if(cam_addr == 0) begin
                    status <= s_write1;
                end else begin
                    status <= s_init;
                end
            end
            s_write1: begin
                if(cam_we) begin
                    addr_wr_in_sram <= cam_addr;
                    data_wr_in_in_sram <= cam_data;


                end

                if(addr_wr_in_sram == address_count_max) begin
                    selec_in_sram <= 0;
                    write_in_sram <= 0;
                    read_in_sram <= 0;

                    status <= s_done;
                end else if(cam_we) begin
                    selec_in_sram <= 1;
                    write_in_sram <= 1;
                    read_in_sram  <= 0;

                    status <= s_write2;    
                end else begin
                    selec_in_sram <= 0;
                    write_in_sram <= 0;
                    read_in_sram <= 0;

                    status <= s_write1;
                end                
            end
            s_write2: begin
                status <= s_write1;
            end
            s_done: begin
                done <= 1'b1;

                status <= s_ready;
            end
            s_ready: begin
                done <= 0;
                status <= s_idle;
            end
            default: begin
                status <= s_idle;
            end
        endcase
    end
end

endmodule
module image_in_sram #(parameter H_cnt_max=320,
                       parameter V_cnt_max=240) (
    input wclk, 
    input rst,

    input enable,

    input[16:0] cam_addr,
    input[15:0] cam_data,
    input cam_we,

    output reg selec_in_sram,
    output reg write_in_sram,
    output reg read_in_sram,
    output reg[15:0] data_wr_in_in_sram,
    output reg[18:0] addr_wr_in_sram,


    output reg done
);


    reg[9:0] H_cnt;
    reg[9:0] V_cnt;
    
localparam address_count_max = H_cnt_max * V_cnt_max - 1;


localparam s_idle           = 4'b0000;
localparam s_init           = 4'b0001;
localparam s_write1         = 4'b0011;
localparam s_write2         = 4'b0010;
localparam s_done           = 4'b0110;
localparam s_ready          = 4'b0111;
reg [3:0] status = s_idle;

localparam[9:0] h_zuoshang=40,
                h_zhongshang=120, 
                h_youshang=200,     
                h_zuozhong=40,
                h_zhongzhong=120,
                h_youzhong=200,
                h_zuoxia=40,
                h_zhongxia=120, 
                h_youxia=200;
localparam[9:0] v_zuoshang=40,
                v_zhongshang=40,
                v_youshang=40,
                v_zuozhong=120,
                v_zhongzhong=120,
                v_youzhong=120,
                v_zuoxia=200,
                v_zhongxia=200,
                v_youxia=200;
localparam[15:0] red = 16'b1111100000000000;
localparam[15:0] green = 16'b0000011111100000;
localparam[15:0] blue = 16'b0000000000011111;
localparam[15:0] AAA = 16'b1111100000011111;
localparam[15:0] BBB = 16'b0000011111111111;
localparam[15:0] CCC = 16'b1111111111100000;
localparam[15:0] white = 16'b1111111111111111;
localparam[15:0] black = 16'b0000000000000000;

always@(posedge wclk) begin
    if(rst) begin
        selec_in_sram <= 0;
        write_in_sram <= 0;
        read_in_sram <= 0;
        data_wr_in_in_sram <= 0;
        addr_wr_in_sram <= 0;
        done <= 0;

        status <= s_idle;
    end else begin
        case(status) 
            s_idle: begin
                done <= 0;            
                selec_in_sram <= 0;
                write_in_sram <= 0;
                read_in_sram <= 0;
                data_wr_in_in_sram <= 0;
                addr_wr_in_sram <= 0;

                if(enable) begin
                    status <= s_init;
                end else begin
                    status <= s_idle;
                end
            end
            s_init: begin
                if(enable) begin
                    status <= s_init;
                end else if(cam_addr == 0) begin
                    status <= s_write1;
                end else begin
                    status <= s_init;
                end
            end
            s_write1: begin
                if(cam_we) begin
                    addr_wr_in_sram <= cam_addr;
                    data_wr_in_in_sram <= cam_data;


                end

                if(addr_wr_in_sram == address_count_max) begin
                    selec_in_sram <= 0;
                    write_in_sram <= 0;
                    read_in_sram <= 0;

                    status <= s_done;
                end else if(cam_we) begin
                    selec_in_sram <= 1;
                    write_in_sram <= 1;
                    read_in_sram  <= 0;

                    status <= s_write2;    
                end else begin
                    selec_in_sram <= 0;
                    write_in_sram <= 0;
                    read_in_sram <= 0;

                    status <= s_write1;
                end                
            end
            s_write2: begin
                status <= s_write1;
            end
            s_done: begin
                done <= 1'b1;

                status <= s_ready;
            end
            s_ready: begin
                done <= 0;
                status <= s_idle;
            end
            default: begin
                status <= s_idle;
            end
        endcase
    end
end

endmodule