data/full_repos/permissive/207111076/sdram_ctrl/sdram_ctrl_64b.v
1: b"%Error: data/full_repos/permissive/207111076/sdram_ctrl/sdram_ctrl_64b.v:122: Cannot find file containing module: 'sdram_cmd_gen'\n    sdram_cmd_gen\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207111076/sdram_ctrl,data/full_repos/permissive/207111076/sdram_cmd_gen\n             data/full_repos/permissive/207111076/sdram_ctrl,data/full_repos/permissive/207111076/sdram_cmd_gen.v\n             data/full_repos/permissive/207111076/sdram_ctrl,data/full_repos/permissive/207111076/sdram_cmd_gen.sv\n             sdram_cmd_gen\n             sdram_cmd_gen.v\n             sdram_cmd_gen.sv\n             obj_dir/sdram_cmd_gen\n             obj_dir/sdram_cmd_gen.v\n             obj_dir/sdram_cmd_gen.sv\n%Error: data/full_repos/permissive/207111076/sdram_ctrl/sdram_ctrl_64b.v:181: Cannot find file containing module: 'sdram_data_64b'\n    sdram_data_64b\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module sdram_ctrl_64b
(



    input             rst,
    input             clk,
    
    output            ram_rdy_n,
    output            ram_ref,
    output      [3:0] ram_cyc,
    output      [3:0] ram_acc,
    output      [8:0] ram_slot,
    output            slot_rst,
    
    output     [63:0] rd_data,



    input             rden_b0,
    input             wren_b0,
    input      [31:0] addr_b0,
    output            valid_b0,
    output            fetch_b0,
    input       [7:0] wr_bena_b0,
    input      [63:0] wr_data_b0,
    



    input             rden_b1,
    input             wren_b1,
    input      [31:0] addr_b1,
    output            valid_b1,
    output            fetch_b1,
    input       [7:0] wr_bena_b1,
    input      [63:0] wr_data_b1,
    



    input             rden_b2,
    input             wren_b2,
    input      [31:0] addr_b2,
    output            valid_b2,
    output            fetch_b2,
    input       [7:0] wr_bena_b2,
    input      [63:0] wr_data_b2,
    



    input             rden_b3,
    input             wren_b3,
    input      [31:0] addr_b3,
    output            valid_b3,
    output            fetch_b3,
    input       [7:0] wr_bena_b3,
    input      [63:0] wr_data_b3,
    




    output            sdram_cs_n,
    output reg        sdram_ras_n,
    output reg        sdram_cas_n,
    output reg        sdram_we_n,

    output reg  [1:0] sdram_ba,
    output reg [12:0] sdram_addr,

    output reg  [7:0] sdram_dqm_n,
    output reg        sdram_dq_oe,
    output reg [63:0] sdram_dq_o,
    input      [63:0] sdram_dq_i
);

    parameter Tco_dly        = 4.5;

    parameter SLOT_CTR_REFR  = 284;

    parameter NUM_REFR_LINE  = 9;

    parameter SLOT_CTR_START = 3;

    parameter SLOT_CTR_STOP  = 288;
    parameter ACC_CTR_STOP   = 3;

    parameter INIT_LINES     = 4;

    `ifdef SDR_ROW_WIDTH
    parameter SDR_ROW_WIDTH  = `SDR_ROW_WIDTH;
    `else
    parameter SDR_ROW_WIDTH  = 12;
    `endif

    `ifdef SDR_COL_WIDTH
    parameter SDR_COL_WIDTH  = `SDR_COL_WIDTH;
    `else
    parameter SDR_COL_WIDTH  =  9;
    `endif

    `ifdef SDR_CLOCK_FREQ
    parameter SDR_CLOCK_FREQ = `SDR_CLOCK_FREQ;
    `else
    parameter SDR_CLOCK_FREQ = 50;
    `endif

    `ifdef SDR_BURST_LEN
    parameter SDR_BURST_LEN = `SDR_BURST_LEN;
    `else
    parameter SDR_BURST_LEN = 2;
    `endif

    sdram_cmd_gen
    #(
        .Tco_dly        (Tco_dly),
        .SLOT_CTR_REFR  (SLOT_CTR_REFR),
        .NUM_REFR_LINE  (NUM_REFR_LINE),
        .SLOT_CTR_START (SLOT_CTR_START),
        .SLOT_CTR_STOP  (SLOT_CTR_STOP),
        .ACC_CTR_STOP   (ACC_CTR_STOP),
        .INIT_LINES     (INIT_LINES),
        .SDR_ROW_WIDTH  (SDR_ROW_WIDTH),
        .SDR_COL_WIDTH  (SDR_COL_WIDTH),
        .SDR_BUS_WIDTH  (64),
        .SDR_CLOCK_FREQ (SDR_CLOCK_FREQ),
        .SDR_BURST_LEN  (SDR_BURST_LEN)
    )
    U_sdram_cmd_gen
    (
        .rst         (rst),
        .clk         (clk),

        .ram_rdy_n   (ram_rdy_n),
        .ram_ref     (ram_ref),
        .ram_cyc     (ram_cyc),
        .ram_acc     (ram_acc),
        .ram_slot    (ram_slot),
        .slot_rst    (slot_rst),

        .rden_b0     (rden_b0),
        .wren_b0     (wren_b0),
        .addr_b0     (addr_b0),
        .valid_b0    (valid_b0),
        .fetch_b0    (fetch_b0),

        .rden_b1     (rden_b1),
        .wren_b1     (wren_b1),
        .addr_b1     (addr_b1),
        .valid_b1    (valid_b1),
        .fetch_b1    (fetch_b1),

        .rden_b2     (rden_b2),
        .wren_b2     (wren_b2),
        .addr_b2     (addr_b2),
        .valid_b2    (valid_b2),
        .fetch_b2    (fetch_b2),

        .rden_b3     (rden_b3),
        .wren_b3     (wren_b3),
        .addr_b3     (addr_b3),
        .valid_b3    (valid_b3),
        .fetch_b3    (fetch_b3),

        .sdram_cs_n  (sdram_cs_n),
        .sdram_ras_n (sdram_ras_n),
        .sdram_cas_n (sdram_cas_n),
        .sdram_we_n  (sdram_we_n),
        .sdram_ba    (sdram_ba),
        .sdram_addr  (sdram_addr) 
    );
    
    sdram_data_64b
    #(
        .Tco_dly     (Tco_dly)
    )
    U_sdram_data
    (
        .clk         (clk),

        .rd_data     (rd_data),
        .data_fetch  ({ fetch_b3, fetch_b2, fetch_b1, fetch_b0 }),
        .wr_bena_b0  (wr_bena_b0),
        .wr_data_b0  (wr_data_b0),
        .wr_bena_b1  (wr_bena_b1),
        .wr_data_b1  (wr_data_b1),
        .wr_bena_b2  (wr_bena_b2),
        .wr_data_b2  (wr_data_b2),
        .wr_bena_b3  (wr_bena_b3),
        .wr_data_b3  (wr_data_b3),

        .sdram_dqm_n (sdram_dqm_n),
        .sdram_dq_oe (sdram_dq_oe),
        .sdram_dq_o  (sdram_dq_o), 
        .sdram_dq_i  (sdram_dq_i)
    );
    
endmodule
module sdram_ctrl_64b
(



    input             rst,
    input             clk,
    
    output            ram_rdy_n,
    output            ram_ref,
    output      [3:0] ram_cyc,
    output      [3:0] ram_acc,
    output      [8:0] ram_slot,
    output            slot_rst,
    
    output     [63:0] rd_data,



    input             rden_b0,
    input             wren_b0,
    input      [31:0] addr_b0,
    output            valid_b0,
    output            fetch_b0,
    input       [7:0] wr_bena_b0,
    input      [63:0] wr_data_b0,
    



    input             rden_b1,
    input             wren_b1,
    input      [31:0] addr_b1,
    output            valid_b1,
    output            fetch_b1,
    input       [7:0] wr_bena_b1,
    input      [63:0] wr_data_b1,
    



    input             rden_b2,
    input             wren_b2,
    input      [31:0] addr_b2,
    output            valid_b2,
    output            fetch_b2,
    input       [7:0] wr_bena_b2,
    input      [63:0] wr_data_b2,
    



    input             rden_b3,
    input             wren_b3,
    input      [31:0] addr_b3,
    output            valid_b3,
    output            fetch_b3,
    input       [7:0] wr_bena_b3,
    input      [63:0] wr_data_b3,
    




    output            sdram_cs_n,
    output reg        sdram_ras_n,
    output reg        sdram_cas_n,
    output reg        sdram_we_n,

    output reg  [1:0] sdram_ba,
    output reg [12:0] sdram_addr,

    output reg  [7:0] sdram_dqm_n,
    output reg        sdram_dq_oe,
    output reg [63:0] sdram_dq_o,
    input      [63:0] sdram_dq_i
);


    parameter Tco_dly        = 4.5;

    parameter SLOT_CTR_REFR  = 284;

    parameter NUM_REFR_LINE  = 9;

    parameter SLOT_CTR_START = 3;

    parameter SLOT_CTR_STOP  = 288;
    parameter ACC_CTR_STOP   = 3;

    parameter INIT_LINES     = 4;

    `ifdef SDR_ROW_WIDTH
    parameter SDR_ROW_WIDTH  = `SDR_ROW_WIDTH;
    `else
    parameter SDR_ROW_WIDTH  = 12;
    `endif

    `ifdef SDR_COL_WIDTH
    parameter SDR_COL_WIDTH  = `SDR_COL_WIDTH;
    `else
    parameter SDR_COL_WIDTH  =  9;
    `endif

    `ifdef SDR_CLOCK_FREQ
    parameter SDR_CLOCK_FREQ = `SDR_CLOCK_FREQ;
    `else
    parameter SDR_CLOCK_FREQ = 50;
    `endif

    `ifdef SDR_BURST_LEN
    parameter SDR_BURST_LEN = `SDR_BURST_LEN;
    `else
    parameter SDR_BURST_LEN = 2;
    `endif

    sdram_cmd_gen
    #(
        .Tco_dly        (Tco_dly),
        .SLOT_CTR_REFR  (SLOT_CTR_REFR),
        .NUM_REFR_LINE  (NUM_REFR_LINE),
        .SLOT_CTR_START (SLOT_CTR_START),
        .SLOT_CTR_STOP  (SLOT_CTR_STOP),
        .ACC_CTR_STOP   (ACC_CTR_STOP),
        .INIT_LINES     (INIT_LINES),
        .SDR_ROW_WIDTH  (SDR_ROW_WIDTH),
        .SDR_COL_WIDTH  (SDR_COL_WIDTH),
        .SDR_BUS_WIDTH  (64),
        .SDR_CLOCK_FREQ (SDR_CLOCK_FREQ),
        .SDR_BURST_LEN  (SDR_BURST_LEN)
    )
    U_sdram_cmd_gen
    (
        .rst         (rst),
        .clk         (clk),

        .ram_rdy_n   (ram_rdy_n),
        .ram_ref     (ram_ref),
        .ram_cyc     (ram_cyc),
        .ram_acc     (ram_acc),
        .ram_slot    (ram_slot),
        .slot_rst    (slot_rst),

        .rden_b0     (rden_b0),
        .wren_b0     (wren_b0),
        .addr_b0     (addr_b0),
        .valid_b0    (valid_b0),
        .fetch_b0    (fetch_b0),

        .rden_b1     (rden_b1),
        .wren_b1     (wren_b1),
        .addr_b1     (addr_b1),
        .valid_b1    (valid_b1),
        .fetch_b1    (fetch_b1),

        .rden_b2     (rden_b2),
        .wren_b2     (wren_b2),
        .addr_b2     (addr_b2),
        .valid_b2    (valid_b2),
        .fetch_b2    (fetch_b2),

        .rden_b3     (rden_b3),
        .wren_b3     (wren_b3),
        .addr_b3     (addr_b3),
        .valid_b3    (valid_b3),
        .fetch_b3    (fetch_b3),

        .sdram_cs_n  (sdram_cs_n),
        .sdram_ras_n (sdram_ras_n),
        .sdram_cas_n (sdram_cas_n),
        .sdram_we_n  (sdram_we_n),
        .sdram_ba    (sdram_ba),
        .sdram_addr  (sdram_addr) 
    );
    
    sdram_data_64b
    #(
        .Tco_dly     (Tco_dly)
    )
    U_sdram_data
    (
        .clk         (clk),

        .rd_data     (rd_data),
        .data_fetch  ({ fetch_b3, fetch_b2, fetch_b1, fetch_b0 }),
        .wr_bena_b0  (wr_bena_b0),
        .wr_data_b0  (wr_data_b0),
        .wr_bena_b1  (wr_bena_b1),
        .wr_data_b1  (wr_data_b1),
        .wr_bena_b2  (wr_bena_b2),
        .wr_data_b2  (wr_data_b2),
        .wr_bena_b3  (wr_bena_b3),
        .wr_data_b3  (wr_data_b3),

        .sdram_dqm_n (sdram_dqm_n),
        .sdram_dq_oe (sdram_dq_oe),
        .sdram_dq_o  (sdram_dq_o), 
        .sdram_dq_i  (sdram_dq_i)
    );
    
endmodule