data/full_repos/permissive/106596430/clockReset.v
1: b"%Error: data/full_repos/permissive/106596430/clockReset.v:39: Cannot find file containing module: 'IBUF'\n    IBUF clkin_ibuf\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/IBUF\n             data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/IBUF.v\n             data/full_repos/permissive/106596430,data/full_repos/permissive/106596430/IBUF.sv\n             IBUF\n             IBUF.v\n             IBUF.sv\n             obj_dir/IBUF\n             obj_dir/IBUF.v\n             obj_dir/IBUF.sv\n%Error: data/full_repos/permissive/106596430/clockReset.v:45: Cannot find file containing module: 'MMCME2_BASE'\n   MMCME2_BASE #(\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/106596430/clockReset.v:81: Cannot find file containing module: 'BUFG'\n    BUFG clkout1_bufg\n    ^~~~\n%Error: Exiting due to 3 error(s)\n"
module clockReset(
    input clk100,
    input rstPBn,
    output clk5,
    output reset
    );
 

    wire        clk100buf;
    wire        clk5_0;
    wire        clkfbout;
    wire        locked;
    wire        reset_high;
    wire        clkfboutb_unused;
    wire        clkout0b_unused;
    wire        clkout1_unused;
    wire        clkout1b_unused;
    wire        clkout2_unused;
    wire        clkout2b_unused;
    wire        clkout3_unused;
    wire        clkout3b_unused;
    wire        clkout4_unused;
    wire        clkout5_unused;
    wire        clkout6_unused;


    IBUF clkin_ibuf
     (.O (clk100buf),
      .I (clk100));
      


   MMCME2_BASE #(
      .BANDWIDTH("OPTIMIZED"),
      .CLKOUT4_CASCADE("FALSE"),
      .STARTUP_WAIT("FALSE"),
      .DIVCLK_DIVIDE(5),
      .CLKFBOUT_MULT_F(32.0),
      .CLKFBOUT_PHASE(0.0),
      .CLKIN1_PERIOD(10.0),
      .REF_JITTER1(0.01),
      .CLKOUT0_DIVIDE_F(128.0),
      .CLKOUT0_DUTY_CYCLE(0.5),
      .CLKOUT0_PHASE(0.0)
   )
   MMCME2_BASE_inst (
      .CLKFBOUT            (clkfbout),
      .CLKFBOUTB           (clkfboutb_unused),
      .CLKOUT0             (clk5_0),
      .CLKOUT0B            (clkout0b_unused),
      .CLKOUT1             (clkout1_unused),
      .CLKOUT1B            (clkout1b_unused),
      .CLKOUT2             (clkout2_unused),
      .CLKOUT2B            (clkout2b_unused),
      .CLKOUT3             (clkout3_unused),
      .CLKOUT3B            (clkout3b_unused),
      .CLKOUT4             (clkout4_unused),
      .CLKOUT5             (clkout5_unused),
      .CLKOUT6             (clkout6_unused),
      .CLKFBIN             (clkfbout),
      .CLKIN1              (clk100buf),
      .LOCKED              (locked),
      .PWRDWN              (1'b0),
      .RST                 (1'b0)
      );



    BUFG clkout1_bufg
     (.O   (clk5),
      .I   (clk5_0));
      


    wire resetIn = ~rstPBn | ~locked;
    



    reg  resetFFn;
    always @ (posedge clk5, posedge resetIn)
      if (resetIn) resetFFn <= 1'b0;
      else resetFFn <= 1'b1;

    assign reset = ~resetFFn;

endmodule
module clockReset(
    input clk100,
    input rstPBn,
    output clk5,
    output reset
    );

 

    wire        clk100buf;
    wire        clk5_0;
    wire        clkfbout;
    wire        locked;
    wire        reset_high;
    wire        clkfboutb_unused;
    wire        clkout0b_unused;
    wire        clkout1_unused;
    wire        clkout1b_unused;
    wire        clkout2_unused;
    wire        clkout2b_unused;
    wire        clkout3_unused;
    wire        clkout3b_unused;
    wire        clkout4_unused;
    wire        clkout5_unused;
    wire        clkout6_unused;


    IBUF clkin_ibuf
     (.O (clk100buf),
      .I (clk100));
      


   MMCME2_BASE #(
      .BANDWIDTH("OPTIMIZED"),
      .CLKOUT4_CASCADE("FALSE"),
      .STARTUP_WAIT("FALSE"),
      .DIVCLK_DIVIDE(5),
      .CLKFBOUT_MULT_F(32.0),
      .CLKFBOUT_PHASE(0.0),
      .CLKIN1_PERIOD(10.0),
      .REF_JITTER1(0.01),
      .CLKOUT0_DIVIDE_F(128.0),
      .CLKOUT0_DUTY_CYCLE(0.5),
      .CLKOUT0_PHASE(0.0)
   )
   MMCME2_BASE_inst (
      .CLKFBOUT            (clkfbout),
      .CLKFBOUTB           (clkfboutb_unused),
      .CLKOUT0             (clk5_0),
      .CLKOUT0B            (clkout0b_unused),
      .CLKOUT1             (clkout1_unused),
      .CLKOUT1B            (clkout1b_unused),
      .CLKOUT2             (clkout2_unused),
      .CLKOUT2B            (clkout2b_unused),
      .CLKOUT3             (clkout3_unused),
      .CLKOUT3B            (clkout3b_unused),
      .CLKOUT4             (clkout4_unused),
      .CLKOUT5             (clkout5_unused),
      .CLKOUT6             (clkout6_unused),
      .CLKFBIN             (clkfbout),
      .CLKIN1              (clk100buf),
      .LOCKED              (locked),
      .PWRDWN              (1'b0),
      .RST                 (1'b0)
      );



    BUFG clkout1_bufg
     (.O   (clk5),
      .I   (clk5_0));
      


    wire resetIn = ~rstPBn | ~locked;
    



    reg  resetFFn;
    always @ (posedge clk5, posedge resetIn)
      if (resetIn) resetFFn <= 1'b0;
      else resetFFn <= 1'b1;

    assign reset = ~resetFFn;

endmodule