data/full_repos/permissive/169258653/multicycle/MIPS_multi_cycle_32bit/MIPS_multi_cycle_32bit.srcs/sources_1/new/adr_MUX2.v
data/verilator_xmls/b132e57a-844a-4647-b0b8-92393360002c.xml
module adr_MUX2(
    input [5:0] pcadr,
    input [31:0] aluout,
    input iord,
    output reg [31:0] adr 
    );
    
    always@(*)
    if(iord)
        adr<=aluout;
    else
        adr<={24'h000000,pcadr,2'b00};
    
endmodule
module adr_MUX2(
    input [5:0] pcadr,
    input [31:0] aluout,
    input iord,
    output reg [31:0] adr 
    );

    
    always@(*)
    if(iord)
        adr<=aluout;
    else
        adr<={24'h000000,pcadr,2'b00};
    
endmodule