data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:26: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb,data/full_repos/permissive/214858095/test_exec.svh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb,data/full_repos/permissive/214858095/test_exec.svh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb,data/full_repos/permissive/214858095/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:31: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgTestExec::*;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:72: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  ChdrBfm #(I_CHDR_W) m_bfm = new(m_chdr, null);\n                            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:73: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  ChdrBfm #(O_CHDR_W) s_bfm = new(null, s_chdr);\n                            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:76: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrPacket #(I_CHDR_W)::ChdrPacket_t      IChdrPacket_t;\n                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:77: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrPacket #(O_CHDR_W)::ChdrPacket_t      OChdrPacket_t;\n                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:78: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(I_CHDR_W, ITEM_W)::chdr_word_t i_chdr_word_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:79: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef ChdrData #(O_CHDR_W, ITEM_W)::chdr_word_t o_chdr_word_t;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:252: syntax error, unexpected IDENTIFIER\n      chdr_header_t header;\n                    ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:315: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:316: syntax error, unexpected \',\'\n        o_data_tuser == o_user_count,\n                                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:334: syntax error, unexpected IDENTIFIER, expecting \'(\' or \';\'\n  function automatic OChdrPacket_t convert_packet(IChdrPacket_t i_packet);\n                                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:335: syntax error, unexpected \'=\', expecting \',\' or \';\'\n    OChdrPacket_t o_packet = new;\n                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:343: syntax error, unexpected \'=\', expecting IDENTIFIER\n      o_packet = OChdrPacket_t\'(i_packet.copy());\n               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:350: syntax error, unexpected \'=\', expecting IDENTIFIER\n    o_packet.header = i_packet.header;\n                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:355: syntax error, unexpected \'=\', expecting IDENTIFIER\n      num_mdata = i_packet.header.num_mdata * I_CHDR_W / O_CHDR_W;\n                ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:356: syntax error, unexpected \'=\', expecting IDENTIFIER\n      if (num_mdata > max_num_mdata) num_mdata = max_num_mdata;\n                                               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:359: syntax error, unexpected \'=\', expecting IDENTIFIER\n      num_mdata = (((i_packet.header.num_mdata * I_CHDR_W)+(O_CHDR_W)-1)/(O_CHDR_W));\n                ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:361: syntax error, unexpected \'.\', expecting IDENTIFIER\n    o_packet.header.num_mdata = num_mdata;\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:364: syntax error, unexpected \'.\', expecting IDENTIFIER\n    o_packet.header.length =\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:377: syntax error, unexpected \'=\', expecting IDENTIFIER\n    o_packet.timestamp = i_packet.timestamp;\n                       ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:384: syntax error, unexpected \'=\', expecting IDENTIFIER\n      o_packet.metadata = ChdrData#(I_CHDR_W, O_CHDR_W)::chdr_to_item(i_packet.metadata,\n                        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:387: syntax error, unexpected \'=\', expecting IDENTIFIER\n      o_packet.data = ChdrData#(I_CHDR_W, O_CHDR_W)::chdr_to_item(i_packet.data,\n                    ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:391: syntax error, unexpected \'=\', expecting IDENTIFIER\n      o_packet.metadata = ChdrData#(O_CHDR_W, I_CHDR_W)::item_to_chdr(i_packet.metadata);\n                        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:392: syntax error, unexpected \'=\', expecting IDENTIFIER\n      o_packet.data     = ChdrData#(O_CHDR_W, I_CHDR_W)::item_to_chdr(i_packet.data);\n                        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:397: syntax error, unexpected \'=\', expecting IDENTIFIER\n        last_mdata = o_packet.metadata[$];\n                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:398: syntax error, unexpected int, expecting IDENTIFIER or genvar\n        for (int i = 0; i < o_packet.mdata_bytes()-i_packet.mdata_bytes(); i++) begin\n             ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:401: syntax error, unexpected \'[\', expecting IDENTIFIER\n        o_packet.metadata[$] = last_mdata;\n                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:412: syntax error, unexpected int, expecting IDENTIFIER or genvar\n      for (int i = 0; i < i_packet.data.size(); i++) begin\n           ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:418: syntax error, unexpected \'.\', expecting IDENTIFIER\n          o_packet.data.push_back(word);\n                       ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:438: syntax error, unexpected \'=\', expecting IDENTIFIER\n      msg = { msg, "Headers do not match\\n" };\n          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:444: syntax error, unexpected \'=\', expecting IDENTIFIER\n        msg = { msg, "Timestamps do not match\\n" };\n            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:452: syntax error, unexpected \'=\', expecting IDENTIFIER\n      msg = { msg, "Metadata does not match\\n" };\n          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:459: syntax error, unexpected \'=\', expecting IDENTIFIER\n      msg = { msg, "Payloads do not match\\n" };\n          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:476: syntax error, unexpected \'=\', expecting \',\' or \';\'\n    mailbox #(IChdrPacket_t) packets = new;\n                                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:480: syntax error, unexpected \'(\', expecting IDENTIFIER\n    test.start_test(msg, 10ms);\n                    ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:482: syntax error, unexpected \'(\', expecting IDENTIFIER\n    m_bfm.set_master_stall_prob(in_stall_prob);\n                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:483: syntax error, unexpected \'(\', expecting IDENTIFIER\n    s_bfm.set_slave_stall_prob(out_stall_prob);\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:499: syntax error, unexpected repeat\n        repeat (NUM_PACKETS) begin\n        ^~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:511: syntax error, unexpected \'=\', expecting IDENTIFIER\n            if (USE_RANDOM) timestamp = Rand#($bits(chdr_header_t))::rand_logic();\n                                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:512: syntax error, unexpected \'=\', expecting IDENTIFIER\n            else timestamp = 64\'h0123456789ABCDEF;\n                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:514: syntax error, unexpected \'=\', expecting IDENTIFIER\n            timestamp = 0;\n                      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:518: syntax error, unexpected \'=\', expecting IDENTIFIER\n          mdata = {};\n                ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:519: Unsupported or unknown PLI call: $urandom_range\n          if ($urandom_range(0, 1)) begin\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:520: syntax error, unexpected \'=\', expecting IDENTIFIER\n            count = 0;\n                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:521: Unsupported or unknown PLI call: $urandom_range\n            repeat ($urandom_range(1, MAX_MDATA_WORDS)) begin\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:530: Unsupported or unknown PLI call: $urandom_range\n          repeat ($urandom_range(1, MAX_PYLD_WORDS)) begin\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:544: syntax error, unexpected +=, expecting IDENTIFIER\n            data_byte_length += $urandom_range(1, I_CHDR_W/64) * 8;\n                             ^~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:544: Unsupported or unknown PLI call: $urandom_range\n            data_byte_length += $urandom_range(1, I_CHDR_W/64) * 8;\n                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/sim/chdr_resize_tb/chdr_resize_tb.sv:546: syntax error, unexpected +=, expecting IDENTIFIER\n            data_byte_length += $urandom_range(1, I_CHDR_W/8);\n                             ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module chdr_resize_tb #(
  parameter I_CHDR_W = 64,
  parameter O_CHDR_W = 128,
  parameter I_DATA_W = I_CHDR_W,
  parameter O_DATA_W = O_CHDR_W,
  parameter USER_W   = 4,
  parameter PIPELINE = "NONE"
);


  `include "test_exec.svh"

  `define MIN(A, B)      ((A)<(B)?(A):(B))
  `define DIV_CEIL(N, D) (((N)+(D)-1)/(D))

  import PkgTestExec::*;
  import PkgChdrUtils::*;
  import PkgChdrBfm::*;
  import PkgRandom::*;


  localparam real CLK_PERIOD = 10.0;


  localparam ITEM_W = 8;


  localparam NUM_PACKETS     = 1000;
  localparam MAX_MDATA_WORDS = 31;

  localparam MAX_PYLD_WORDS  = 64;
  localparam USE_RANDOM      = 1;
  localparam DEBUG           = 0;






  bit clk;
  bit rst;

  sim_clock_gen #(.PERIOD(CLK_PERIOD), .AUTOSTART(0))
    clk_gen (.clk(clk), .rst(rst));







  AxiStreamIf #(I_CHDR_W) m_chdr (clk, 1'b0);
  AxiStreamIf #(O_CHDR_W) s_chdr (clk, 1'b0);



  ChdrBfm #(I_CHDR_W) m_bfm = new(m_chdr, null);
  ChdrBfm #(O_CHDR_W) s_bfm = new(null, s_chdr);


  typedef ChdrPacket #(I_CHDR_W)::ChdrPacket_t      IChdrPacket_t;
  typedef ChdrPacket #(O_CHDR_W)::ChdrPacket_t      OChdrPacket_t;
  typedef ChdrData #(I_CHDR_W, ITEM_W)::chdr_word_t i_chdr_word_t;
  typedef ChdrData #(O_CHDR_W, ITEM_W)::chdr_word_t o_chdr_word_t;














  wire [I_DATA_W-1:0] i_data_tdata;
  wire [  USER_W-1:0] i_data_tuser;
  wire                i_data_tlast;
  wire                i_data_tvalid;
  wire                i_data_tready;

  wire [O_DATA_W-1:0] o_data_tdata;
  wire [  USER_W-1:0] o_data_tuser;
  wire                o_data_tlast;
  wire                o_data_tvalid;
  wire                o_data_tready;

  chdr_resize #(
    .I_CHDR_W (I_CHDR_W),
    .O_CHDR_W (O_CHDR_W),
    .I_DATA_W (I_DATA_W),
    .O_DATA_W (O_DATA_W),
    .USER_W   (USER_W),
    .PIPELINE (PIPELINE)
  ) chdr_resize_i (
    .clk           (clk),
    .rst           (rst),
    .i_chdr_tdata  (i_data_tdata),
    .i_chdr_tuser  (i_data_tuser),
    .i_chdr_tlast  (i_data_tlast),
    .i_chdr_tvalid (i_data_tvalid),
    .i_chdr_tready (i_data_tready),
    .o_chdr_tdata  (o_data_tdata),
    .o_chdr_tuser  (o_data_tuser),
    .o_chdr_tlast  (o_data_tlast),
    .o_chdr_tvalid (o_data_tvalid),
    .o_chdr_tready (o_data_tready)
  );










  localparam IN_WORD_W  = `MIN(I_CHDR_W, I_DATA_W);
  localparam OUT_WORD_W = `MIN(O_CHDR_W, O_DATA_W);
  localparam OUT_KEEP_W = O_CHDR_W/OUT_WORD_W;

  wire [I_CHDR_W-1:0] i_chdr_tdata;
  wire                i_chdr_tlast;
  wire                i_chdr_tvalid;
  wire                i_chdr_tready;

  wire [  O_CHDR_W-1:0] o_chdr_tdata_unmasked;
  wire [  O_CHDR_W-1:0] o_chdr_tdata;
  wire [OUT_KEEP_W-1:0] o_chdr_tkeep;
  wire                  o_chdr_tlast;
  wire                  o_chdr_tvalid;
  wire                  o_chdr_tready;

  axis_width_conv #(
    .WORD_W    (IN_WORD_W),
    .IN_WORDS  (I_CHDR_W/IN_WORD_W),
    .OUT_WORDS (I_DATA_W/IN_WORD_W),
    .SYNC_CLKS (1),
    .PIPELINE  ("NONE")
  ) axis_width_conv_in (
    .s_axis_aclk   (clk),
    .s_axis_rst    (rst),
    .s_axis_tdata  (i_chdr_tdata),
    .s_axis_tkeep  ('1),
    .s_axis_tlast  (i_chdr_tlast),
    .s_axis_tvalid (i_chdr_tvalid),
    .s_axis_tready (i_chdr_tready),
    .m_axis_aclk   (clk),
    .m_axis_rst    (rst),
    .m_axis_tdata  (i_data_tdata),
    .m_axis_tkeep  (),
    .m_axis_tlast  (i_data_tlast),
    .m_axis_tvalid (i_data_tvalid),
    .m_axis_tready (i_data_tready)
  );

  axis_width_conv #(
    .WORD_W    (OUT_WORD_W),
    .IN_WORDS  (O_DATA_W/OUT_WORD_W),
    .OUT_WORDS (O_CHDR_W/OUT_WORD_W),
    .SYNC_CLKS (1),
    .PIPELINE  ("NONE")
  ) axis_width_conv_out (
    .s_axis_aclk   (clk),
    .s_axis_rst    (rst),
    .s_axis_tdata  (o_data_tdata),
    .s_axis_tkeep  ('1),
    .s_axis_tlast  (o_data_tlast),
    .s_axis_tvalid (o_data_tvalid),
    .s_axis_tready (o_data_tready),
    .m_axis_aclk   (clk),
    .m_axis_rst    (rst),
    .m_axis_tdata  (o_chdr_tdata_unmasked),
    .m_axis_tkeep  (o_chdr_tkeep),
    .m_axis_tlast  (o_chdr_tlast),
    .m_axis_tvalid (o_chdr_tvalid),
    .m_axis_tready (o_chdr_tready)
  );





  reg [O_CHDR_W-1:0] o_chdr_keep_mask;

  always_comb begin
    for (int w = 0; w < OUT_KEEP_W; w++) begin
      if (o_chdr_tkeep[w] == 1'b1) begin
        o_chdr_keep_mask[w*OUT_WORD_W+:OUT_WORD_W] = {OUT_WORD_W{1'b1}};
      end else begin
        o_chdr_keep_mask[w*OUT_WORD_W+:OUT_WORD_W] = {OUT_WORD_W{1'bX}};
      end
    end
  end



  assign o_chdr_tdata = o_chdr_tdata_unmasked & o_chdr_keep_mask;







  assign i_chdr_tdata  = m_chdr.tdata;
  assign i_chdr_tlast  = m_chdr.tlast;
  assign i_chdr_tvalid = m_chdr.tvalid;
  assign m_chdr.tready = i_chdr_tready;


  assign s_chdr.tdata  = o_chdr_tdata;
  assign s_chdr.tlast  = o_chdr_tlast;
  assign s_chdr.tvalid = o_chdr_tvalid;
  assign o_chdr_tready = s_chdr.tready;











  if (DEBUG) begin
    bit i_chdr_sop   = 1;
    bit mid_chdr_sop = 1;
    bit o_chdr_sop   = 1;

    always @(posedge clk) begin
      chdr_header_t header;

      if (i_chdr_tvalid && i_chdr_tready) begin
        if (i_chdr_sop) begin
          header = i_chdr_tdata;
          $display("In  packet, @%0t: 0x%16X %p", $realtime, header, header);
          i_chdr_sop <= 0;
        end
        i_chdr_sop <= i_chdr_tlast;
      end

      if (o_chdr_tvalid && o_chdr_tready) begin
        if (o_chdr_sop) begin
          header = o_chdr_tdata;
          $display("Out packet, @%0t: 0x%16X %p", $realtime, header, header);
          o_chdr_sop <= 0;
        end
        o_chdr_sop <= o_chdr_tlast;
      end
    end
  end










  reg [USER_W-1:0] i_user_count = 0;

  always @(posedge clk) begin
    if (rst) begin
      i_user_count <= 0;
    end else if (i_data_tvalid && i_data_tready) begin
      if (i_data_tlast) begin
        i_user_count <= i_user_count + 1;
      end
    end
  end



  assign i_data_tuser =
    (i_data_tvalid && i_data_tready) ? i_user_count : 'X;










  reg [USER_W-1:0] o_user_count = 0;

  always @(posedge clk) begin
    if (rst) begin
      o_user_count <= 0;
    end else if (o_data_tvalid && o_data_tready) begin
      `ASSERT_ERROR(
        o_data_tuser == o_user_count,
        "TUSER output doesn't match expected count."
      );
      if (o_data_tlast) begin
        o_user_count <= o_user_count+1;
      end
    end
  end










  function automatic OChdrPacket_t convert_packet(IChdrPacket_t i_packet);
    OChdrPacket_t o_packet = new;
    int num_mdata;
    int max_num_mdata = 2**$bits(o_packet.header.num_mdata)-1;


    if (I_CHDR_W == O_CHDR_W && I_CHDR_W == I_DATA_W && O_CHDR_W == O_DATA_W) begin


      o_packet = OChdrPacket_t'(i_packet.copy());
      return o_packet;
    end




    o_packet.header = i_packet.header;


    if (I_CHDR_W > O_CHDR_W) begin

      num_mdata = i_packet.header.num_mdata * I_CHDR_W / O_CHDR_W;
      if (num_mdata > max_num_mdata) num_mdata = max_num_mdata;
    end else begin

      num_mdata = `DIV_CEIL(i_packet.header.num_mdata * I_CHDR_W, O_CHDR_W);
    end
    o_packet.header.num_mdata = num_mdata;


    o_packet.header.length =

      (O_CHDR_W/8) +

      ((o_packet.header.pkt_type == CHDR_DATA_WITH_TS && O_CHDR_W == 64) ? (O_CHDR_W/8) : 0) +

      (O_CHDR_W/8)*o_packet.header.num_mdata +


      ((o_packet.header.pkt_type == CHDR_MANAGEMENT) ?
        `DIV_CEIL(i_packet.data_bytes(), I_CHDR_W/8) * (O_CHDR_W/8) : i_packet.data_bytes());


    o_packet.timestamp = i_packet.timestamp;




    if (I_CHDR_W > O_CHDR_W) begin

      o_packet.metadata = ChdrData#(I_CHDR_W, O_CHDR_W)::chdr_to_item(i_packet.metadata,
        num_mdata * O_CHDR_W/8);

      o_packet.data = ChdrData#(I_CHDR_W, O_CHDR_W)::chdr_to_item(i_packet.data,
        `DIV_CEIL(i_packet.data_bytes(), O_CHDR_W/8) * O_CHDR_W/8);
    end else begin
      o_chdr_word_t last_mdata;
      o_packet.metadata = ChdrData#(O_CHDR_W, I_CHDR_W)::item_to_chdr(i_packet.metadata);
      o_packet.data     = ChdrData#(O_CHDR_W, I_CHDR_W)::item_to_chdr(i_packet.data);



      if (o_packet.metadata.size() > 0) begin
        last_mdata = o_packet.metadata[$];
        for (int i = 0; i < o_packet.mdata_bytes()-i_packet.mdata_bytes(); i++) begin
          last_mdata[$bits(o_chdr_word_t)-i*8-1 -: 8] = 8'd0;
        end
        o_packet.metadata[$] = last_mdata;
      end
    end




    if (o_packet.header.pkt_type == CHDR_MANAGEMENT) begin


      o_packet.data = {};
      for (int i = 0; i < i_packet.data.size(); i++) begin
        if (i == 0) begin

          o_chdr_word_t word;
          word = i_packet.data[i];
          word[47:45] = translate_chdr_w(O_CHDR_W);
          o_packet.data.push_back(word);
        end else begin
          o_packet.data.push_back(i_packet.data[i]);
        end
      end
    end

    return o_packet;
  endfunction : convert_packet



  function automatic string compare_packets(
    input OChdrPacket_t packet,
    input OChdrPacket_t exp_packet
  );
    string msg = "";


    if(packet.header != exp_packet.header) begin
      msg = { msg, "Headers do not match\n" };
    end


    if (exp_packet.header.pkt_type == CHDR_DATA_WITH_TS) begin
      if(packet.timestamp != exp_packet.timestamp) begin
        msg = { msg, "Timestamps do not match\n" };
      end
    end


    if(!exp_packet.chdr_word_queues_equal(
      packet.metadata, exp_packet.metadata, packet.mdata_bytes())
    ) begin
      msg = { msg, "Metadata does not match\n" };
    end


    if(!exp_packet.chdr_word_queues_equal(
      packet.data, exp_packet.data, exp_packet.data_bytes())
    ) begin
      msg = { msg, "Payloads do not match\n" };
    end

    return msg;
  endfunction : compare_packets








  task automatic test_random(int in_stall_prob, int out_stall_prob);
    longint word_count = 0;
    bit enable_input = 0;
    string msg;
    mailbox #(IChdrPacket_t) packets = new;

    msg = $sformatf("Test Random Packets (%0d%%, %0d%%)",
      in_stall_prob, out_stall_prob);
    test.start_test(msg, 10ms);

    m_bfm.set_master_stall_prob(in_stall_prob);
    s_bfm.set_slave_stall_prob(out_stall_prob);

    fork




      begin : input_process
        IChdrPacket_t    chdr_packet = new;
        i_chdr_word_t    data[$];
        i_chdr_word_t    mdata[$];
        chdr_header_t    header;
        chdr_timestamp_t timestamp;
        int              data_byte_length;
        int              count;

        repeat (NUM_PACKETS) begin





          do begin
            header = Rand#($bits(chdr_header_t))::rand_logic();
          end while (header.pkt_type == CHDR_RESERVED_0 || header.pkt_type == CHDR_RESERVED_1);


          if (header.pkt_type == CHDR_DATA_WITH_TS) begin
            if (USE_RANDOM) timestamp = Rand#($bits(chdr_header_t))::rand_logic();
            else timestamp = 64'h0123456789ABCDEF;
          end else begin
            timestamp = 0;
          end


          mdata = {};
          if ($urandom_range(0, 1)) begin
            count = 0;
            repeat ($urandom_range(1, MAX_MDATA_WORDS)) begin
              if (USE_RANDOM) mdata.push_back(Rand#(I_CHDR_W)::rand_logic());
              else mdata.push_back(64'hA1000000 + count++);
            end
          end


          data = {};
          count = 0;
          repeat ($urandom_range(1, MAX_PYLD_WORDS)) begin
            if (USE_RANDOM) data.push_back(Rand#(I_CHDR_W)::rand_logic());
            else data.push_back(64'hB2000000 + count++);
          end


          data_byte_length = (data.size()-1) * (I_CHDR_W/8);


          if (header.pkt_type == CHDR_MANAGEMENT) begin




            data_byte_length += $urandom_range(1, I_CHDR_W/64) * 8;
          end else begin
            data_byte_length += $urandom_range(1, I_CHDR_W/8);
          end


          chdr_packet.write_raw(
            header,
            data,
            mdata,
            timestamp,
            data_byte_length
          );


          m_bfm.put_chdr(chdr_packet);


          packets.put(chdr_packet.copy());
        end
        $display("Done inputting packets.");
      end : input_process





      begin : output_process
        IChdrPacket_t i_packet;
        OChdrPacket_t o_packet;
        OChdrPacket_t exp_packet;
        int packet_count;
        string msg;

        repeat (NUM_PACKETS) begin
          s_bfm.get_chdr(o_packet);
          packets.get(i_packet);
          exp_packet = convert_packet(i_packet);
          msg = compare_packets(o_packet, exp_packet);
          if(msg != "") begin
            $display("Sent packet:");
            i_packet.print(0);
            $display("Received packet:");
            o_packet.print(0);
            $display("Expected packet:");
            exp_packet.print(0);
            `ASSERT_ERROR(0, $sformatf(
              "Output packet is incorrect for the following reasons:\n%s", msg)
            );
          end
        end
        $display("Done processing packets.");
      end : output_process
    join

    test.end_test();

  endtask : test_random






  initial begin : tb_main
    string msg;
    string tb_name;

    tb_name = $sformatf( {
      "chdr_resize_tb\n",
      "I_CHDR_W = %03d\n",
      "O_CHDR_W = %03d\n",
      "I_DATA_W = %03d\n",
      "O_DATA_W = %03d\n",
      "PIPLINE  = %s" },
      I_CHDR_W, O_CHDR_W, I_DATA_W, O_DATA_W, PIPELINE
    );
    test.start_tb(tb_name, 100ms);




    clk_gen.start();


    m_bfm.run();
    s_bfm.run();





    test.start_test("Reset", 10us);
    clk_gen.reset();
    if (rst) @rst;
    test.end_test();





    test_random(50, 50);
    test_random( 0,  0);
    test_random(50,  0);
    test_random( 0, 50);







    test.end_tb(0);


    clk_gen.kill();

  end : tb_main

endmodule
module chdr_resize_tb #(
  parameter I_CHDR_W = 64,
  parameter O_CHDR_W = 128,
  parameter I_DATA_W = I_CHDR_W,
  parameter O_DATA_W = O_CHDR_W,
  parameter USER_W   = 4,
  parameter PIPELINE = "NONE"
);



  `include "test_exec.svh"

  `define MIN(A, B)      ((A)<(B)?(A):(B))
  `define DIV_CEIL(N, D) (((N)+(D)-1)/(D))

  import PkgTestExec::*;
  import PkgChdrUtils::*;
  import PkgChdrBfm::*;
  import PkgRandom::*;


  localparam real CLK_PERIOD = 10.0;


  localparam ITEM_W = 8;


  localparam NUM_PACKETS     = 1000;
  localparam MAX_MDATA_WORDS = 31;

  localparam MAX_PYLD_WORDS  = 64;
  localparam USE_RANDOM      = 1;
  localparam DEBUG           = 0;






  bit clk;
  bit rst;

  sim_clock_gen #(.PERIOD(CLK_PERIOD), .AUTOSTART(0))
    clk_gen (.clk(clk), .rst(rst));







  AxiStreamIf #(I_CHDR_W) m_chdr (clk, 1'b0);
  AxiStreamIf #(O_CHDR_W) s_chdr (clk, 1'b0);



  ChdrBfm #(I_CHDR_W) m_bfm = new(m_chdr, null);
  ChdrBfm #(O_CHDR_W) s_bfm = new(null, s_chdr);


  typedef ChdrPacket #(I_CHDR_W)::ChdrPacket_t      IChdrPacket_t;
  typedef ChdrPacket #(O_CHDR_W)::ChdrPacket_t      OChdrPacket_t;
  typedef ChdrData #(I_CHDR_W, ITEM_W)::chdr_word_t i_chdr_word_t;
  typedef ChdrData #(O_CHDR_W, ITEM_W)::chdr_word_t o_chdr_word_t;














  wire [I_DATA_W-1:0] i_data_tdata;
  wire [  USER_W-1:0] i_data_tuser;
  wire                i_data_tlast;
  wire                i_data_tvalid;
  wire                i_data_tready;

  wire [O_DATA_W-1:0] o_data_tdata;
  wire [  USER_W-1:0] o_data_tuser;
  wire                o_data_tlast;
  wire                o_data_tvalid;
  wire                o_data_tready;

  chdr_resize #(
    .I_CHDR_W (I_CHDR_W),
    .O_CHDR_W (O_CHDR_W),
    .I_DATA_W (I_DATA_W),
    .O_DATA_W (O_DATA_W),
    .USER_W   (USER_W),
    .PIPELINE (PIPELINE)
  ) chdr_resize_i (
    .clk           (clk),
    .rst           (rst),
    .i_chdr_tdata  (i_data_tdata),
    .i_chdr_tuser  (i_data_tuser),
    .i_chdr_tlast  (i_data_tlast),
    .i_chdr_tvalid (i_data_tvalid),
    .i_chdr_tready (i_data_tready),
    .o_chdr_tdata  (o_data_tdata),
    .o_chdr_tuser  (o_data_tuser),
    .o_chdr_tlast  (o_data_tlast),
    .o_chdr_tvalid (o_data_tvalid),
    .o_chdr_tready (o_data_tready)
  );










  localparam IN_WORD_W  = `MIN(I_CHDR_W, I_DATA_W);
  localparam OUT_WORD_W = `MIN(O_CHDR_W, O_DATA_W);
  localparam OUT_KEEP_W = O_CHDR_W/OUT_WORD_W;

  wire [I_CHDR_W-1:0] i_chdr_tdata;
  wire                i_chdr_tlast;
  wire                i_chdr_tvalid;
  wire                i_chdr_tready;

  wire [  O_CHDR_W-1:0] o_chdr_tdata_unmasked;
  wire [  O_CHDR_W-1:0] o_chdr_tdata;
  wire [OUT_KEEP_W-1:0] o_chdr_tkeep;
  wire                  o_chdr_tlast;
  wire                  o_chdr_tvalid;
  wire                  o_chdr_tready;

  axis_width_conv #(
    .WORD_W    (IN_WORD_W),
    .IN_WORDS  (I_CHDR_W/IN_WORD_W),
    .OUT_WORDS (I_DATA_W/IN_WORD_W),
    .SYNC_CLKS (1),
    .PIPELINE  ("NONE")
  ) axis_width_conv_in (
    .s_axis_aclk   (clk),
    .s_axis_rst    (rst),
    .s_axis_tdata  (i_chdr_tdata),
    .s_axis_tkeep  ('1),
    .s_axis_tlast  (i_chdr_tlast),
    .s_axis_tvalid (i_chdr_tvalid),
    .s_axis_tready (i_chdr_tready),
    .m_axis_aclk   (clk),
    .m_axis_rst    (rst),
    .m_axis_tdata  (i_data_tdata),
    .m_axis_tkeep  (),
    .m_axis_tlast  (i_data_tlast),
    .m_axis_tvalid (i_data_tvalid),
    .m_axis_tready (i_data_tready)
  );

  axis_width_conv #(
    .WORD_W    (OUT_WORD_W),
    .IN_WORDS  (O_DATA_W/OUT_WORD_W),
    .OUT_WORDS (O_CHDR_W/OUT_WORD_W),
    .SYNC_CLKS (1),
    .PIPELINE  ("NONE")
  ) axis_width_conv_out (
    .s_axis_aclk   (clk),
    .s_axis_rst    (rst),
    .s_axis_tdata  (o_data_tdata),
    .s_axis_tkeep  ('1),
    .s_axis_tlast  (o_data_tlast),
    .s_axis_tvalid (o_data_tvalid),
    .s_axis_tready (o_data_tready),
    .m_axis_aclk   (clk),
    .m_axis_rst    (rst),
    .m_axis_tdata  (o_chdr_tdata_unmasked),
    .m_axis_tkeep  (o_chdr_tkeep),
    .m_axis_tlast  (o_chdr_tlast),
    .m_axis_tvalid (o_chdr_tvalid),
    .m_axis_tready (o_chdr_tready)
  );





  reg [O_CHDR_W-1:0] o_chdr_keep_mask;

  always_comb begin
    for (int w = 0; w < OUT_KEEP_W; w++) begin
      if (o_chdr_tkeep[w] == 1'b1) begin
        o_chdr_keep_mask[w*OUT_WORD_W+:OUT_WORD_W] = {OUT_WORD_W{1'b1}};
      end else begin
        o_chdr_keep_mask[w*OUT_WORD_W+:OUT_WORD_W] = {OUT_WORD_W{1'bX}};
      end
    end
  end



  assign o_chdr_tdata = o_chdr_tdata_unmasked & o_chdr_keep_mask;







  assign i_chdr_tdata  = m_chdr.tdata;
  assign i_chdr_tlast  = m_chdr.tlast;
  assign i_chdr_tvalid = m_chdr.tvalid;
  assign m_chdr.tready = i_chdr_tready;


  assign s_chdr.tdata  = o_chdr_tdata;
  assign s_chdr.tlast  = o_chdr_tlast;
  assign s_chdr.tvalid = o_chdr_tvalid;
  assign o_chdr_tready = s_chdr.tready;











  if (DEBUG) begin
    bit i_chdr_sop   = 1;
    bit mid_chdr_sop = 1;
    bit o_chdr_sop   = 1;

    always @(posedge clk) begin
      chdr_header_t header;

      if (i_chdr_tvalid && i_chdr_tready) begin
        if (i_chdr_sop) begin
          header = i_chdr_tdata;
          $display("In  packet, @%0t: 0x%16X %p", $realtime, header, header);
          i_chdr_sop <= 0;
        end
        i_chdr_sop <= i_chdr_tlast;
      end

      if (o_chdr_tvalid && o_chdr_tready) begin
        if (o_chdr_sop) begin
          header = o_chdr_tdata;
          $display("Out packet, @%0t: 0x%16X %p", $realtime, header, header);
          o_chdr_sop <= 0;
        end
        o_chdr_sop <= o_chdr_tlast;
      end
    end
  end










  reg [USER_W-1:0] i_user_count = 0;

  always @(posedge clk) begin
    if (rst) begin
      i_user_count <= 0;
    end else if (i_data_tvalid && i_data_tready) begin
      if (i_data_tlast) begin
        i_user_count <= i_user_count + 1;
      end
    end
  end



  assign i_data_tuser =
    (i_data_tvalid && i_data_tready) ? i_user_count : 'X;










  reg [USER_W-1:0] o_user_count = 0;

  always @(posedge clk) begin
    if (rst) begin
      o_user_count <= 0;
    end else if (o_data_tvalid && o_data_tready) begin
      `ASSERT_ERROR(
        o_data_tuser == o_user_count,
        "TUSER output doesn't match expected count."
      );
      if (o_data_tlast) begin
        o_user_count <= o_user_count+1;
      end
    end
  end










  function automatic OChdrPacket_t convert_packet(IChdrPacket_t i_packet);
    OChdrPacket_t o_packet = new;
    int num_mdata;
    int max_num_mdata = 2**$bits(o_packet.header.num_mdata)-1;


    if (I_CHDR_W == O_CHDR_W && I_CHDR_W == I_DATA_W && O_CHDR_W == O_DATA_W) begin


      o_packet = OChdrPacket_t'(i_packet.copy());
      return o_packet;
    end




    o_packet.header = i_packet.header;


    if (I_CHDR_W > O_CHDR_W) begin

      num_mdata = i_packet.header.num_mdata * I_CHDR_W / O_CHDR_W;
      if (num_mdata > max_num_mdata) num_mdata = max_num_mdata;
    end else begin

      num_mdata = `DIV_CEIL(i_packet.header.num_mdata * I_CHDR_W, O_CHDR_W);
    end
    o_packet.header.num_mdata = num_mdata;


    o_packet.header.length =

      (O_CHDR_W/8) +

      ((o_packet.header.pkt_type == CHDR_DATA_WITH_TS && O_CHDR_W == 64) ? (O_CHDR_W/8) : 0) +

      (O_CHDR_W/8)*o_packet.header.num_mdata +


      ((o_packet.header.pkt_type == CHDR_MANAGEMENT) ?
        `DIV_CEIL(i_packet.data_bytes(), I_CHDR_W/8) * (O_CHDR_W/8) : i_packet.data_bytes());


    o_packet.timestamp = i_packet.timestamp;




    if (I_CHDR_W > O_CHDR_W) begin

      o_packet.metadata = ChdrData#(I_CHDR_W, O_CHDR_W)::chdr_to_item(i_packet.metadata,
        num_mdata * O_CHDR_W/8);

      o_packet.data = ChdrData#(I_CHDR_W, O_CHDR_W)::chdr_to_item(i_packet.data,
        `DIV_CEIL(i_packet.data_bytes(), O_CHDR_W/8) * O_CHDR_W/8);
    end else begin
      o_chdr_word_t last_mdata;
      o_packet.metadata = ChdrData#(O_CHDR_W, I_CHDR_W)::item_to_chdr(i_packet.metadata);
      o_packet.data     = ChdrData#(O_CHDR_W, I_CHDR_W)::item_to_chdr(i_packet.data);



      if (o_packet.metadata.size() > 0) begin
        last_mdata = o_packet.metadata[$];
        for (int i = 0; i < o_packet.mdata_bytes()-i_packet.mdata_bytes(); i++) begin
          last_mdata[$bits(o_chdr_word_t)-i*8-1 -: 8] = 8'd0;
        end
        o_packet.metadata[$] = last_mdata;
      end
    end




    if (o_packet.header.pkt_type == CHDR_MANAGEMENT) begin


      o_packet.data = {};
      for (int i = 0; i < i_packet.data.size(); i++) begin
        if (i == 0) begin

          o_chdr_word_t word;
          word = i_packet.data[i];
          word[47:45] = translate_chdr_w(O_CHDR_W);
          o_packet.data.push_back(word);
        end else begin
          o_packet.data.push_back(i_packet.data[i]);
        end
      end
    end

    return o_packet;
  endfunction : convert_packet



  function automatic string compare_packets(
    input OChdrPacket_t packet,
    input OChdrPacket_t exp_packet
  );
    string msg = "";


    if(packet.header != exp_packet.header) begin
      msg = { msg, "Headers do not match\n" };
    end


    if (exp_packet.header.pkt_type == CHDR_DATA_WITH_TS) begin
      if(packet.timestamp != exp_packet.timestamp) begin
        msg = { msg, "Timestamps do not match\n" };
      end
    end


    if(!exp_packet.chdr_word_queues_equal(
      packet.metadata, exp_packet.metadata, packet.mdata_bytes())
    ) begin
      msg = { msg, "Metadata does not match\n" };
    end


    if(!exp_packet.chdr_word_queues_equal(
      packet.data, exp_packet.data, exp_packet.data_bytes())
    ) begin
      msg = { msg, "Payloads do not match\n" };
    end

    return msg;
  endfunction : compare_packets








  task automatic test_random(int in_stall_prob, int out_stall_prob);
    longint word_count = 0;
    bit enable_input = 0;
    string msg;
    mailbox #(IChdrPacket_t) packets = new;

    msg = $sformatf("Test Random Packets (%0d%%, %0d%%)",
      in_stall_prob, out_stall_prob);
    test.start_test(msg, 10ms);

    m_bfm.set_master_stall_prob(in_stall_prob);
    s_bfm.set_slave_stall_prob(out_stall_prob);

    fork




      begin : input_process
        IChdrPacket_t    chdr_packet = new;
        i_chdr_word_t    data[$];
        i_chdr_word_t    mdata[$];
        chdr_header_t    header;
        chdr_timestamp_t timestamp;
        int              data_byte_length;
        int              count;

        repeat (NUM_PACKETS) begin





          do begin
            header = Rand#($bits(chdr_header_t))::rand_logic();
          end while (header.pkt_type == CHDR_RESERVED_0 || header.pkt_type == CHDR_RESERVED_1);


          if (header.pkt_type == CHDR_DATA_WITH_TS) begin
            if (USE_RANDOM) timestamp = Rand#($bits(chdr_header_t))::rand_logic();
            else timestamp = 64'h0123456789ABCDEF;
          end else begin
            timestamp = 0;
          end


          mdata = {};
          if ($urandom_range(0, 1)) begin
            count = 0;
            repeat ($urandom_range(1, MAX_MDATA_WORDS)) begin
              if (USE_RANDOM) mdata.push_back(Rand#(I_CHDR_W)::rand_logic());
              else mdata.push_back(64'hA1000000 + count++);
            end
          end


          data = {};
          count = 0;
          repeat ($urandom_range(1, MAX_PYLD_WORDS)) begin
            if (USE_RANDOM) data.push_back(Rand#(I_CHDR_W)::rand_logic());
            else data.push_back(64'hB2000000 + count++);
          end


          data_byte_length = (data.size()-1) * (I_CHDR_W/8);


          if (header.pkt_type == CHDR_MANAGEMENT) begin




            data_byte_length += $urandom_range(1, I_CHDR_W/64) * 8;
          end else begin
            data_byte_length += $urandom_range(1, I_CHDR_W/8);
          end


          chdr_packet.write_raw(
            header,
            data,
            mdata,
            timestamp,
            data_byte_length
          );


          m_bfm.put_chdr(chdr_packet);


          packets.put(chdr_packet.copy());
        end
        $display("Done inputting packets.");
      end : input_process





      begin : output_process
        IChdrPacket_t i_packet;
        OChdrPacket_t o_packet;
        OChdrPacket_t exp_packet;
        int packet_count;
        string msg;

        repeat (NUM_PACKETS) begin
          s_bfm.get_chdr(o_packet);
          packets.get(i_packet);
          exp_packet = convert_packet(i_packet);
          msg = compare_packets(o_packet, exp_packet);
          if(msg != "") begin
            $display("Sent packet:");
            i_packet.print(0);
            $display("Received packet:");
            o_packet.print(0);
            $display("Expected packet:");
            exp_packet.print(0);
            `ASSERT_ERROR(0, $sformatf(
              "Output packet is incorrect for the following reasons:\n%s", msg)
            );
          end
        end
        $display("Done processing packets.");
      end : output_process
    join

    test.end_test();

  endtask : test_random






  initial begin : tb_main
    string msg;
    string tb_name;

    tb_name = $sformatf( {
      "chdr_resize_tb\n",
      "I_CHDR_W = %03d\n",
      "O_CHDR_W = %03d\n",
      "I_DATA_W = %03d\n",
      "O_DATA_W = %03d\n",
      "PIPLINE  = %s" },
      I_CHDR_W, O_CHDR_W, I_DATA_W, O_DATA_W, PIPELINE
    );
    test.start_tb(tb_name, 100ms);




    clk_gen.start();


    m_bfm.run();
    s_bfm.run();





    test.start_test("Reset", 10us);
    clk_gen.reset();
    if (rst) @rst;
    test.end_test();





    test_random(50, 50);
    test_random( 0,  0);
    test_random(50,  0);
    test_random( 0, 50);







    test.end_tb(0);


    clk_gen.kill();

  end : tb_main

endmodule