data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/reg_w_det.v
1: b"%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/reg_w_det.v:29: Can't find definition of variable: 'bitmask'\n   assign pulse = (state == bitmask) && (!gotwrite_d && gotwrite);\n                            ^~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module reg_w_det(
	      input wire clk,
	      input wire [18:0] bus_a,
	      input wire [18:0] my_a,
	      input wire [15:0] bus_d,
	      input wire ena,
	      input wire [7:0] trigger,
	      output wire pulse

	      );

   reg 			  gotwrite, gotwrite_d;
   reg [7:0] 		  state;
   
   always @(posedge clk) begin
      if( (bus_a[18:1] == my_a[18:1]) && ena ) begin
	 state <= bus_d;
	 gotwrite <= 1'b0;
      end else begin
	 state <= state;
	 gotwrite <= 1'b1;
      end
   end

   always @(posedge clk) begin
      gotwrite_d <= gotwrite;
   end

   assign pulse = (state == bitmask) && (!gotwrite_d && gotwrite);

endmodule
module reg_w_det(
	      input wire clk,
	      input wire [18:0] bus_a,
	      input wire [18:0] my_a,
	      input wire [15:0] bus_d,
	      input wire ena,
	      input wire [7:0] trigger,
	      output wire pulse

	      );


   reg 			  gotwrite, gotwrite_d;
   reg [7:0] 		  state;
   
   always @(posedge clk) begin
      if( (bus_a[18:1] == my_a[18:1]) && ena ) begin
	 state <= bus_d;
	 gotwrite <= 1'b0;
      end else begin
	 state <= state;
	 gotwrite <= 1'b1;
      end
   end

   always @(posedge clk) begin
      gotwrite_d <= gotwrite;
   end

   assign pulse = (state == bitmask) && (!gotwrite_d && gotwrite);

endmodule