data/full_repos/permissive/207610706/src/key_scheduler/double_scheduler.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/207610706/src/key_scheduler/double_scheduler.sv:11: Little bit endian vector: MSB < LSB of bit range: 0:255\ninput [0:255] aes_key_input;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/207610706/src/key_scheduler/double_scheduler.sv:14: Little bit endian vector: MSB < LSB of bit range: 0:127\noutput reg [0:127] round_key_material;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/207610706/src/key_scheduler/double_scheduler.sv:15: Little bit endian vector: MSB < LSB of bit range: 0:127\noutput [0:127] inv_round_key_material;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/207610706/src/key_scheduler/double_scheduler.sv:20: Little bit endian vector: MSB < LSB of bit range: 0:127\nwire [0:127] next_direct_round_key, next_inverse_round_key;\n     ^\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/double_scheduler.sv:35: Cannot find file containing module: \'hp_key_sched\'\nhp_key_sched aes_key_scheduler(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/207610706/src/key_scheduler,data/full_repos/permissive/207610706/hp_key_sched\n             data/full_repos/permissive/207610706/src/key_scheduler,data/full_repos/permissive/207610706/hp_key_sched.v\n             data/full_repos/permissive/207610706/src/key_scheduler,data/full_repos/permissive/207610706/hp_key_sched.sv\n             hp_key_sched\n             hp_key_sched.v\n             hp_key_sched.sv\n             obj_dir/hp_key_sched\n             obj_dir/hp_key_sched.v\n             obj_dir/hp_key_sched.sv\n%Error: data/full_repos/permissive/207610706/src/key_scheduler/double_scheduler.sv:41: Cannot find file containing module: \'inv_mix_columns\'\ninv_mix_columns inverse_scheduler(round_key_material, next_inverse_round_key);\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module double_scheduler(
        clk, rst,
        new_key_schedule, input_key_length,
        aes_key_input,
        valid_key_out, round_key_material, inv_round_key_material);

input clk, rst;

input new_key_schedule;
input [1:0] input_key_length;
input [0:255] aes_key_input;

output reg valid_key_out;
output reg [0:127] round_key_material;
output [0:127] inv_round_key_material;


wire [0:127] next_direct_round_key, next_inverse_round_key;
wire next_valid_key_out;
reg first_last_selector;

always@(posedge clk)
begin
    round_key_material <= next_direct_round_key;
    first_last_selector <= valid_key_out & next_valid_key_out;

    if(rst)
        valid_key_out <= 1'b0;
    else
        valid_key_out <= next_valid_key_out;
end

hp_key_sched aes_key_scheduler(
    .clk(clk), .rst(rst),
    .new_key_schedule(new_key_schedule), .input_key_length(input_key_length),
    .aes_key_input(aes_key_input),
    .valid_key_out(next_valid_key_out), .round_key_material(next_direct_round_key));

inv_mix_columns inverse_scheduler(round_key_material, next_inverse_round_key);

assign inv_round_key_material = first_last_selector & next_valid_key_out ? next_inverse_round_key : round_key_material;

endmodule
module double_scheduler(
        clk, rst,
        new_key_schedule, input_key_length,
        aes_key_input,
        valid_key_out, round_key_material, inv_round_key_material);


input clk, rst;

input new_key_schedule;
input [1:0] input_key_length;
input [0:255] aes_key_input;

output reg valid_key_out;
output reg [0:127] round_key_material;
output [0:127] inv_round_key_material;


wire [0:127] next_direct_round_key, next_inverse_round_key;
wire next_valid_key_out;
reg first_last_selector;

always@(posedge clk)
begin
    round_key_material <= next_direct_round_key;
    first_last_selector <= valid_key_out & next_valid_key_out;

    if(rst)
        valid_key_out <= 1'b0;
    else
        valid_key_out <= next_valid_key_out;
end

hp_key_sched aes_key_scheduler(
    .clk(clk), .rst(rst),
    .new_key_schedule(new_key_schedule), .input_key_length(input_key_length),
    .aes_key_input(aes_key_input),
    .valid_key_out(next_valid_key_out), .round_key_material(next_direct_round_key));

inv_mix_columns inverse_scheduler(round_key_material, next_inverse_round_key);

assign inv_round_key_material = first_last_selector & next_valid_key_out ? next_inverse_round_key : round_key_material;

endmodule