data/full_repos/permissive/166008742/src/tb_top.v
 line:134: before: "("
1: b'%Error: data/full_repos/permissive/166008742/src/tb_top.v:21: Cannot find include file: globals.vh\n    `include "globals.vh" \n             ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/globals.vh\n             data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/globals.vh.v\n             data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/globals.vh.sv\n             globals.vh\n             globals.vh.v\n             globals.vh.sv\n             obj_dir/globals.vh\n             obj_dir/globals.vh.v\n             obj_dir/globals.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_top.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/166008742/src/tb_top.v:56: syntax error, unexpected \'@\'\n        repeat (100) @(posedge CLK_50M);\n                     ^\n%Error: data/full_repos/permissive/166008742/src/tb_top.v:58: Define or directive not defined: \'`IMG_WIDTH\'\n        repeat (3 * `IMG_WIDTH * `IMG_HEIGHT) begin\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/166008742/src/tb_top.v:58: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n        repeat (3 * `IMG_WIDTH * `IMG_HEIGHT) begin\n                               ^\n%Error: data/full_repos/permissive/166008742/src/tb_top.v:58: Define or directive not defined: \'`IMG_HEIGHT\'\n        repeat (3 * `IMG_WIDTH * `IMG_HEIGHT) begin\n                                 ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_top.v:65: Unsupported: Ignoring delay on this delayed statement.\n                #301;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_top.v:67: Unsupported: Ignoring delay on this delayed statement.\n                #301;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/166008742/src/tb_top.v:70: Unsupported: Ignoring delay on this delayed statement.\n            #25;\n            ^\n%Error: data/full_repos/permissive/166008742/src/tb_top.v:73: syntax error, unexpected end\n    end\n    ^~~\n%Error: Cannot continue\n'
module tb_top();
    `include "globals.vh"

    reg CLK_50M;
    wire [0:0] PMOD4;


    reg  mosi;
    reg  ss;
    reg  sclk;
    wire miso;

    top dut
    (
        .CLK_50M(CLK_50M),
        .PMOD4(PMOD4),


        .SYS_SPI_MOSI(mosi),
        .SYS_SPI_MISO(miso),
        .SYS_SPI_SCK(sclk),
        .RP_SPI_CE0N(ss)
    );


    always begin
        #10;
        CLK_50M <= ~CLK_50M;
    end

    initial begin
            CLK_50M <= 0;
            mosi <= 0;
            ss <= 1;
            sclk <= 1;

        repeat (100) @(posedge CLK_50M);

        repeat (3 * `IMG_WIDTH * `IMG_HEIGHT) begin

            @(posedge CLK_50M);
            ss <= 0;
            repeat (8) begin
                mosi <= $random() % 2;
                sclk <= 0;
                #301;
                sclk <= 1;
                #301;
            end
            ss <= 1;
            #25;
        end

    end

endmodule
module tb_top();

    `include "globals.vh"

    reg CLK_50M;
    wire [0:0] PMOD4;


    reg  mosi;
    reg  ss;
    reg  sclk;
    wire miso;

    top dut
    (
        .CLK_50M(CLK_50M),
        .PMOD4(PMOD4),


        .SYS_SPI_MOSI(mosi),
        .SYS_SPI_MISO(miso),
        .SYS_SPI_SCK(sclk),
        .RP_SPI_CE0N(ss)
    );


    always begin
        #10;
        CLK_50M <= ~CLK_50M;
    end

    initial begin
            CLK_50M <= 0;
            mosi <= 0;
            ss <= 1;
            sclk <= 1;

        repeat (100) @(posedge CLK_50M);

        repeat (3 * `IMG_WIDTH * `IMG_HEIGHT) begin

            @(posedge CLK_50M);
            ss <= 0;
            repeat (8) begin
                mosi <= $random() % 2;
                sclk <= 0;
                #301;
                sclk <= 1;
                #301;
            end
            ss <= 1;
            #25;
        end

    end

endmodule