data/full_repos/permissive/157436936/ex2/Uart_Top.v
 line:1 column:1: Illegal character '\ufeff'
1: b'%Warning-WIDTH: data/full_repos/permissive/157436936/ex2/Uart_Top.v:46: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                      : ... In instance Uart_Top\n  cnt = 1\'b0;\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/157436936/ex2/Uart_Top.v:84: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                      : ... In instance Uart_Top\n          Data_Reg[Data_Cnt] = Data_Rx;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/157436936/ex2/Uart_Top.v:119: Bit extraction of array[3:0] requires 2 bit index, not 4 bits.\n                                                                       : ... In instance Uart_Top\n           Data_Tx = Error_Char[Char_Cnt];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/157436936/ex2/Uart_Top.v:146: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                       : ... In instance Uart_Top\n        State = 2\'b0;\n              ^\n%Error: data/full_repos/permissive/157436936/ex2/Uart_Top.v:157: Cannot find file containing module: \'Uart_ClkDiv\'\nUart_ClkDiv uart_clkdiv(.Sys_CLK(Sys_CLK), .Sys_RST(Sys_RST), .Uart_CLK(Uart_CLK));\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157436936/ex2,data/full_repos/permissive/157436936/Uart_ClkDiv\n             data/full_repos/permissive/157436936/ex2,data/full_repos/permissive/157436936/Uart_ClkDiv.v\n             data/full_repos/permissive/157436936/ex2,data/full_repos/permissive/157436936/Uart_ClkDiv.sv\n             Uart_ClkDiv\n             Uart_ClkDiv.v\n             Uart_ClkDiv.sv\n             obj_dir/Uart_ClkDiv\n             obj_dir/Uart_ClkDiv.v\n             obj_dir/Uart_ClkDiv.sv\n%Error: data/full_repos/permissive/157436936/ex2/Uart_Top.v:158: Cannot find file containing module: \'Uart_Tx\'\nUart_Tx uart_tx(.Uart_CLK(Uart_CLK), .Data_Tx(Data_Tx), .Wrsig(Wrsig), .Idle(Idle), .Signal_Tx(Signal_Tx));\n^~~~~~~\n%Error: data/full_repos/permissive/157436936/ex2/Uart_Top.v:159: Cannot find file containing module: \'Uart_Rx\'\nUart_Rx uart_rx(.Uart_CLK(Uart_CLK), .Uart_RST(Sys_RST), .Signal_Rx(Signal_Rx), .Data_Rx(Data_Rx), .Rdsig(Rdsig), .DataError_Flag(Rx_DataError_Flag), .FrameError_Flag(Rx_FrameError_Flag));\n^~~~~~~\n%Error: data/full_repos/permissive/157436936/ex2/Uart_Top.v:162: Cannot find file containing module: \'Chr2Bin\'\n  Chr2Bin convA(Data_Reg[j], Num[7-j]);\n  ^~~~~~~\n%Error: data/full_repos/permissive/157436936/ex2/Uart_Top.v:166: Cannot find file containing module: \'Bin2Chr\'\nBin2Chr convB0({2\'b0, F[7]}, Print_Reg[0]);\n^~~~~~~\n%Error: data/full_repos/permissive/157436936/ex2/Uart_Top.v:169: Cannot find file containing module: \'Bin2Chr\'\n  Bin2Chr convB({2\'b0, F[6-j]}, Print_Reg[j+2]);\n  ^~~~~~~\n%Error: data/full_repos/permissive/157436936/ex2/Uart_Top.v:172: Cannot find file containing module: \'Bin2Chr\'\nBin2Chr convBx(P, Print_Reg[10]);\n^~~~~~~\n%Error: Exiting due to 7 error(s), 4 warning(s)\n'
module Uart_Top(Sys_CLK, Sys_RST, Signal_Tx, Signal_Rx, Num, F, P);

input Sys_CLK;
input Sys_RST;
input Signal_Rx;
input [7:0] F;
input [2:0] P;
output Signal_Tx;
output [7:0] Num;

wire Uart_CLK;
reg [7:0] Data_Tx;
wire [7:0] Data_Rx;
reg Wrsig;
wire Rdsig;
wire Rx_DataError_Flag;
wire Rx_FrameError_Flag;
reg Error_Flag;
reg [2:0] State;
reg [7:0] cnt;
reg [7:0] Data_Reg[0:7];
reg [3:0] Data_Cnt;
wire [7:0] Print_Reg[0:10];
reg [3:0] Print_Cnt;
reg [7:0] Error_Char[0:3];
reg [3:0] Char_Cnt;
wire Idle;


parameter Wait_Rdsig = 3'b000;
parameter Check_Data = 3'b001;
parameter Save_Data = 3'b010;
parameter Trans_Data = 3'b011;
parameter State_Delay = 3'b100;

assign Print_Reg[1] = 8'd46;
assign Print_Reg[9] = 8'd69;


integer i;
genvar j;

always @(posedge Uart_CLK or negedge Sys_RST) begin
	if (!Sys_RST) begin
		Wrsig = 1'b0;
		cnt = 1'b0;
		State = 3'b0;
		Char_Cnt = 4'b0;
		Data_Cnt = 4'b0;
		Print_Cnt = 4'b0;
		Data_Tx = 8'b0;
		cnt = 8'b0;
		for (i=0; i<8; i=i+1)
			Data_Reg[i] = 8'd48;
		Error_Char[0] = 8'd69;
		Error_Char[1] = 8'd114;
		Error_Char[2] = 8'd114;
		Error_Char[3] = 8'd33;
	end
	else begin
		case(State)
			Wait_Rdsig:	begin
								if (!Rdsig)
									State = Wait_Rdsig;
								else
									State = Check_Data;
							end
			Check_Data:	begin
								if (Rdsig)
									State = Check_Data;
								else begin
									Error_Flag = Rx_DataError_Flag || Rx_FrameError_Flag;
									State = Save_Data;
								end
							end
			Save_Data:	begin
								if (!Error_Flag) begin
									if (Data_Cnt == 4'd8) begin
										Data_Cnt = 4'd0;
										State = Trans_Data;
									end
									else begin
										State = Wait_Rdsig;
										Data_Reg[Data_Cnt] = Data_Rx;
										Data_Cnt = Data_Cnt + 1;
									end
								end
								else
									State = Trans_Data;
							end
			Trans_Data:	begin
								if (!Error_Flag) begin
									if (Print_Cnt == 4'd11) begin
										Print_Cnt = 4'd0;
										State = State_Delay;
									end
									else begin
										State = Trans_Data;
										if (cnt == 254) begin
											Data_Tx = Print_Reg[Print_Cnt];
											Wrsig = 1'b1;
											cnt = 8'd0;
											Print_Cnt = Print_Cnt + 1;
										end
										else begin
											Wrsig = 1'b0;
											cnt = cnt + 8'd1;
										end
									end
								end
								else begin
									if (Char_Cnt == 4'd4) begin
										Char_Cnt = 4'd0;
										State = State_Delay;
									end
									else begin
										State = Trans_Data;
										if (cnt == 254) begin
											Data_Tx = Error_Char[Char_Cnt];
											Wrsig = 1'b1;
											cnt = 8'd0;
											Char_Cnt = Char_Cnt + 1;
										end
										else begin
											Wrsig = 1'b0;
											cnt = cnt + 8'd1;
										end
									end
								end
							end
			State_Delay:begin
								if (cnt == 254) begin
									Data_Tx = 8'd13;
									Wrsig = 1'b1;
									cnt = 8'd0;
									State = Wait_Rdsig;
								end
								else begin
									Wrsig = 1'b0;
									cnt = cnt + 8'd1;
								end
							end
			default:		begin
								Wrsig = 1'b0;
								cnt = 8'd0;
								State = 2'b0;
								Char_Cnt = 4'b0;
								Data_Cnt = 4'b0;
								Print_Cnt = 4'b0;
								for (i=0; i<8; i=i+1)
									Data_Reg[i] = 8'd48;
							end
		endcase
	end
end

Uart_ClkDiv uart_clkdiv(.Sys_CLK(Sys_CLK), .Sys_RST(Sys_RST), .Uart_CLK(Uart_CLK));
Uart_Tx uart_tx(.Uart_CLK(Uart_CLK), .Data_Tx(Data_Tx), .Wrsig(Wrsig), .Idle(Idle), .Signal_Tx(Signal_Tx));
Uart_Rx uart_rx(.Uart_CLK(Uart_CLK), .Uart_RST(Sys_RST), .Signal_Rx(Signal_Rx), .Data_Rx(Data_Rx), .Rdsig(Rdsig), .DataError_Flag(Rx_DataError_Flag), .FrameError_Flag(Rx_FrameError_Flag));
generate
	for (j = 0; j < 8; j=j+1) begin:chr2bin
		Chr2Bin convA(Data_Reg[j], Num[7-j]);
	end
endgenerate

Bin2Chr convB0({2'b0, F[7]}, Print_Reg[0]);
generate
	for (j = 0; j < 7; j=j+1) begin:bin2chr
		Bin2Chr convB({2'b0, F[6-j]}, Print_Reg[j+2]);
	end
endgenerate
Bin2Chr convBx(P, Print_Reg[10]);

endmodule
module Uart_Top(Sys_CLK, Sys_RST, Signal_Tx, Signal_Rx, Num, F, P);


input Sys_CLK;
input Sys_RST;
input Signal_Rx;
input [7:0] F;
input [2:0] P;
output Signal_Tx;
output [7:0] Num;

wire Uart_CLK;
reg [7:0] Data_Tx;
wire [7:0] Data_Rx;
reg Wrsig;
wire Rdsig;
wire Rx_DataError_Flag;
wire Rx_FrameError_Flag;
reg Error_Flag;
reg [2:0] State;
reg [7:0] cnt;
reg [7:0] Data_Reg[0:7];
reg [3:0] Data_Cnt;
wire [7:0] Print_Reg[0:10];
reg [3:0] Print_Cnt;
reg [7:0] Error_Char[0:3];
reg [3:0] Char_Cnt;
wire Idle;


parameter Wait_Rdsig = 3'b000;
parameter Check_Data = 3'b001;
parameter Save_Data = 3'b010;
parameter Trans_Data = 3'b011;
parameter State_Delay = 3'b100;

assign Print_Reg[1] = 8'd46;
assign Print_Reg[9] = 8'd69;


integer i;
genvar j;

always @(posedge Uart_CLK or negedge Sys_RST) begin
	if (!Sys_RST) begin
		Wrsig = 1'b0;
		cnt = 1'b0;
		State = 3'b0;
		Char_Cnt = 4'b0;
		Data_Cnt = 4'b0;
		Print_Cnt = 4'b0;
		Data_Tx = 8'b0;
		cnt = 8'b0;
		for (i=0; i<8; i=i+1)
			Data_Reg[i] = 8'd48;
		Error_Char[0] = 8'd69;
		Error_Char[1] = 8'd114;
		Error_Char[2] = 8'd114;
		Error_Char[3] = 8'd33;
	end
	else begin
		case(State)
			Wait_Rdsig:	begin
								if (!Rdsig)
									State = Wait_Rdsig;
								else
									State = Check_Data;
							end
			Check_Data:	begin
								if (Rdsig)
									State = Check_Data;
								else begin
									Error_Flag = Rx_DataError_Flag || Rx_FrameError_Flag;
									State = Save_Data;
								end
							end
			Save_Data:	begin
								if (!Error_Flag) begin
									if (Data_Cnt == 4'd8) begin
										Data_Cnt = 4'd0;
										State = Trans_Data;
									end
									else begin
										State = Wait_Rdsig;
										Data_Reg[Data_Cnt] = Data_Rx;
										Data_Cnt = Data_Cnt + 1;
									end
								end
								else
									State = Trans_Data;
							end
			Trans_Data:	begin
								if (!Error_Flag) begin
									if (Print_Cnt == 4'd11) begin
										Print_Cnt = 4'd0;
										State = State_Delay;
									end
									else begin
										State = Trans_Data;
										if (cnt == 254) begin
											Data_Tx = Print_Reg[Print_Cnt];
											Wrsig = 1'b1;
											cnt = 8'd0;
											Print_Cnt = Print_Cnt + 1;
										end
										else begin
											Wrsig = 1'b0;
											cnt = cnt + 8'd1;
										end
									end
								end
								else begin
									if (Char_Cnt == 4'd4) begin
										Char_Cnt = 4'd0;
										State = State_Delay;
									end
									else begin
										State = Trans_Data;
										if (cnt == 254) begin
											Data_Tx = Error_Char[Char_Cnt];
											Wrsig = 1'b1;
											cnt = 8'd0;
											Char_Cnt = Char_Cnt + 1;
										end
										else begin
											Wrsig = 1'b0;
											cnt = cnt + 8'd1;
										end
									end
								end
							end
			State_Delay:begin
								if (cnt == 254) begin
									Data_Tx = 8'd13;
									Wrsig = 1'b1;
									cnt = 8'd0;
									State = Wait_Rdsig;
								end
								else begin
									Wrsig = 1'b0;
									cnt = cnt + 8'd1;
								end
							end
			default:		begin
								Wrsig = 1'b0;
								cnt = 8'd0;
								State = 2'b0;
								Char_Cnt = 4'b0;
								Data_Cnt = 4'b0;
								Print_Cnt = 4'b0;
								for (i=0; i<8; i=i+1)
									Data_Reg[i] = 8'd48;
							end
		endcase
	end
end

Uart_ClkDiv uart_clkdiv(.Sys_CLK(Sys_CLK), .Sys_RST(Sys_RST), .Uart_CLK(Uart_CLK));
Uart_Tx uart_tx(.Uart_CLK(Uart_CLK), .Data_Tx(Data_Tx), .Wrsig(Wrsig), .Idle(Idle), .Signal_Tx(Signal_Tx));
Uart_Rx uart_rx(.Uart_CLK(Uart_CLK), .Uart_RST(Sys_RST), .Signal_Rx(Signal_Rx), .Data_Rx(Data_Rx), .Rdsig(Rdsig), .DataError_Flag(Rx_DataError_Flag), .FrameError_Flag(Rx_FrameError_Flag));
generate
	for (j = 0; j < 8; j=j+1) begin:chr2bin
		Chr2Bin convA(Data_Reg[j], Num[7-j]);
	end
endgenerate

Bin2Chr convB0({2'b0, F[7]}, Print_Reg[0]);
generate
	for (j = 0; j < 7; j=j+1) begin:bin2chr
		Bin2Chr convB({2'b0, F[6-j]}, Print_Reg[j+2]);
	end
endgenerate
Bin2Chr convBx(P, Print_Reg[10]);

endmodule