data/full_repos/permissive/158845296/execute_to_memory.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/efdf5b87-33ad-46a0-b57c-11ed9b25c7b1.xml
module execute_to_memory
(
    input clock,
    input reset,


    input  [4:0] x_dst_reg,
    input        x_mem_read,
    input        x_mem_write,
    input        x_mem_byte,
    input        x_reg_write,
    input        x_mem_to_reg,
    input [31:0] x_mem_write_data,
    input [31:0] x_alu_result,
    input        x_stall,


    input             m_stall,
    output reg  [4:0] m_dst_reg,
    output reg        m_mem_read,
    output reg        m_mem_write,
    output reg        m_mem_byte,
    output reg        m_reg_write,
    output reg        m_mem_to_reg,
    output reg [31:0] m_mem_write_data,
    output reg [31:0] m_alu_result
);

    always @(posedge clock) begin
        m_dst_reg        <= (reset) ?  5'b0 : (m_stall ? m_dst_reg                      : x_dst_reg);
        m_mem_read       <= (reset) ?  1'b0 : (m_stall ? m_mem_read   : (x_stall ? 1'b0 : x_mem_read));
        m_mem_write      <= (reset) ?  1'b0 : (m_stall ? m_mem_write  : (x_stall ? 1'b0 : x_mem_write));
        m_mem_byte       <= (reset) ?  1'b0 : (m_stall ? m_mem_byte                     : x_mem_byte);
        m_reg_write      <= (reset) ?  1'b0 : (m_stall ? m_reg_write  : (x_stall ? 1'b0 : x_reg_write));
        m_mem_to_reg     <= (reset) ?  1'b0 : (m_stall ? m_mem_to_reg                   : x_mem_to_reg);
        m_alu_result     <= (reset) ? 32'b0 : (m_stall ? m_alu_result                   : x_alu_result);
        m_mem_write_data <= (reset) ? 32'b0 : (m_stall ? m_mem_write_data               : x_mem_write_data);
    end

endmodule
module execute_to_memory
(
    input clock,
    input reset,


    input  [4:0] x_dst_reg,
    input        x_mem_read,
    input        x_mem_write,
    input        x_mem_byte,
    input        x_reg_write,
    input        x_mem_to_reg,
    input [31:0] x_mem_write_data,
    input [31:0] x_alu_result,
    input        x_stall,


    input             m_stall,
    output reg  [4:0] m_dst_reg,
    output reg        m_mem_read,
    output reg        m_mem_write,
    output reg        m_mem_byte,
    output reg        m_reg_write,
    output reg        m_mem_to_reg,
    output reg [31:0] m_mem_write_data,
    output reg [31:0] m_alu_result
);


    always @(posedge clock) begin
        m_dst_reg        <= (reset) ?  5'b0 : (m_stall ? m_dst_reg                      : x_dst_reg);
        m_mem_read       <= (reset) ?  1'b0 : (m_stall ? m_mem_read   : (x_stall ? 1'b0 : x_mem_read));
        m_mem_write      <= (reset) ?  1'b0 : (m_stall ? m_mem_write  : (x_stall ? 1'b0 : x_mem_write));
        m_mem_byte       <= (reset) ?  1'b0 : (m_stall ? m_mem_byte                     : x_mem_byte);
        m_reg_write      <= (reset) ?  1'b0 : (m_stall ? m_reg_write  : (x_stall ? 1'b0 : x_reg_write));
        m_mem_to_reg     <= (reset) ?  1'b0 : (m_stall ? m_mem_to_reg                   : x_mem_to_reg);
        m_alu_result     <= (reset) ? 32'b0 : (m_stall ? m_alu_result                   : x_alu_result);
        m_mem_write_data <= (reset) ? 32'b0 : (m_stall ? m_mem_write_data               : x_mem_write_data);
    end

endmodule