data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v
None: at end of input
1: b'%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:2: Cannot find include file: modulos/ternarioDoble.v\n  `include "modulos/ternarioDoble.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/ternarioDoble.v\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/ternarioDoble.v.v\n             data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/ternarioDoble.v.sv\n             modulos/ternarioDoble.v\n             modulos/ternarioDoble.v.v\n             modulos/ternarioDoble.v.sv\n             obj_dir/modulos/ternarioDoble.v\n             obj_dir/modulos/ternarioDoble.v.v\n             obj_dir/modulos/ternarioDoble.v.sv\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:5: Cannot find include file: ../tarea3/modulos/mux.v\n  `include "../tarea3/modulos/mux.v" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:34: Unsupported: Ignoring delay on this delayed statement.\n  initial # 50 clk = 0;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:41: Unsupported: Ignoring delay on this delayed statement.\n  always # 45 clk = ~clk;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:46: Unsupported: Ignoring delay on this delayed statement.\n    # 150;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:47: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:56: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:57: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:59: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:60: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:62: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:63: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:67: Unsupported: Ignoring delay on this delayed statement.\n    # 150;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:68: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:76: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:77: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:79: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:80: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:82: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:83: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:88: Unsupported: Ignoring delay on this delayed statement.\n    # 150;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:89: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:98: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:99: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:101: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:102: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:104: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:105: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:109: Unsupported: Ignoring delay on this delayed statement.\n    # 150;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:110: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:118: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:119: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:121: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:122: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:124: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:125: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:130: Unsupported: Ignoring delay on this delayed statement.\n    # 150;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:131: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:140: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:141: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:143: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:144: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:146: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:147: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:151: Unsupported: Ignoring delay on this delayed statement.\n    # 150;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:152: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:160: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:161: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:163: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:164: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:166: Unsupported: Ignoring delay on this delayed statement.\n      # 150;\n      ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:167: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:169: Unsupported: Ignoring delay on this delayed statement.\n    # 150;\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:170: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:176: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./tests/testternarioDoble.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:177: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:182: Unsupported or unknown PLI call: $monitor\n    $monitor            ("%t| %b | %b | %b | %b  | %b  | %b | %f ns",\n    ^~~~~~~~\n%Error: Exiting due to 30 error(s), 27 warning(s)\n'
module testternarioDoble ();



  reg a, b, c, s1, s2, clk;


  wire y;


  ternarioDoble tester(
    .a(a),
    .b(b),
    .c(c),
    .s1(s1),
    .s2(s2),
    .y(y)
  );


  initial # 50 clk = 0;






  always # 45 clk = ~clk;

  initial begin


    # 150;
    @(posedge clk);
      $display("Eleccion de señal a=0, entonces s1=0 y s2=0");
      a <= 1'b0;
      b <= 1'b0;
      c <= 1'b0;
      s1 <= 1'b0;
      s2 <= 1'b0;


      # 150;
      @(posedge clk);
        b <= 1'b1;
      # 150;
      @(posedge clk);
        c <= 1'b1;
      # 150;
      @(posedge clk);
        b <= 1'b0;


    # 150;
    @(posedge clk);
    $display("Eleccion de señal a=1, entonces s1=0 y s2=0");
      a <= 1'b1;
      b <= 1'b0;
      c <= 1'b0;
      s1 <= 1'b0;
      s2 <= 1'b0;

      # 150;
      @(posedge clk);
        b <= 1'b1;
      # 150;
      @(posedge clk);
        c <= 1'b1;
      # 150;
      @(posedge clk);
        b <= 1'b0;



    # 150;
    @(posedge clk);
      $display("Eleccion de señal b=0, entonces s1=0 y s2=0");
      a <= 1'b0;
      b <= 1'b0;
      c <= 1'b0;
      s1 <= 1'b1;
      s2 <= 1'b0;


      # 150;
      @(posedge clk);
        a <= 1'b1;
      # 150;
      @(posedge clk);
        c <= 1'b1;
      # 150;
      @(posedge clk);
        a <= 1'b0;


    # 150;
    @(posedge clk);
    $display("Eleccion de señal b=1, entonces s1=1 y s2=0");
      a <= 1'b0;
      b <= 1'b1;
      c <= 1'b0;
      s1 <= 1'b1;
      s2 <= 1'b0;

      # 150;
      @(posedge clk);
        a <= 1'b1;
      # 150;
      @(posedge clk);
        c <= 1'b1;
      # 150;
      @(posedge clk);
        a <= 1'b0;



    # 150;
    @(posedge clk);
      $display("Eleccion de señal c=0, entonces s1=x y s2=1");
      a <= 1'b0;
      b <= 1'b0;
      c <= 1'b0;
      s1 <= 1'bx;
      s2 <= 1'b1;


      # 150;
      @(posedge clk);
        a <= 1'b1;
      # 150;
      @(posedge clk);
        b <= 1'b1;
      # 150;
      @(posedge clk);
        a <= 1'b0;


    # 150;
    @(posedge clk);
    $display("Eleccion de señal c=1, entonces s0=x y s1=1");
      a <= 1'b0;
      b <= 1'b0;
      c <= 1'b1;
      s1 <= 1'bx;
      s2 <= 1'b1;

      # 150;
      @(posedge clk);
        a <= 1'b1;
      # 150;
      @(posedge clk);
        b <= 1'b1;
      # 150;
      @(posedge clk);
        a <= 1'b0;
    # 150;
    @(posedge clk);
    $finish;
  end

  initial
    begin
    $dumpfile("./tests/testternarioDoble.vcd");
    $dumpvars;
    $display("------------------------------------");
    $display("-- Test para modulo ternarioDoble --");
    $display("------------------------------------");
    $display ("\t     tiempo | a | b | c | s1 | s2 | y | tiempo");
    $monitor            ("%t| %b | %b | %b | %b  | %b  | %b | %f ns",
                          $time, a, b, c, s1, s2, y, $realtime);
  end
endmodule
module testternarioDoble ();




  reg a, b, c, s1, s2, clk;


  wire y;


  ternarioDoble tester(
    .a(a),
    .b(b),
    .c(c),
    .s1(s1),
    .s2(s2),
    .y(y)
  );


  initial # 50 clk = 0;






  always # 45 clk = ~clk;

  initial begin


    # 150;
    @(posedge clk);
      $display("Eleccion de señal a=0, entonces s1=0 y s2=0");
      a <= 1'b0;
      b <= 1'b0;
      c <= 1'b0;
      s1 <= 1'b0;
      s2 <= 1'b0;


      # 150;
      @(posedge clk);
        b <= 1'b1;
      # 150;
      @(posedge clk);
        c <= 1'b1;
      # 150;
      @(posedge clk);
        b <= 1'b0;


    # 150;
    @(posedge clk);
    $display("Eleccion de señal a=1, entonces s1=0 y s2=0");
      a <= 1'b1;
      b <= 1'b0;
      c <= 1'b0;
      s1 <= 1'b0;
      s2 <= 1'b0;

      # 150;
      @(posedge clk);
        b <= 1'b1;
      # 150;
      @(posedge clk);
        c <= 1'b1;
      # 150;
      @(posedge clk);
        b <= 1'b0;



    # 150;
    @(posedge clk);
      $display("Eleccion de señal b=0, entonces s1=0 y s2=0");
      a <= 1'b0;
      b <= 1'b0;
      c <= 1'b0;
      s1 <= 1'b1;
      s2 <= 1'b0;


      # 150;
      @(posedge clk);
        a <= 1'b1;
      # 150;
      @(posedge clk);
        c <= 1'b1;
      # 150;
      @(posedge clk);
        a <= 1'b0;


    # 150;
    @(posedge clk);
    $display("Eleccion de señal b=1, entonces s1=1 y s2=0");
      a <= 1'b0;
      b <= 1'b1;
      c <= 1'b0;
      s1 <= 1'b1;
      s2 <= 1'b0;

      # 150;
      @(posedge clk);
        a <= 1'b1;
      # 150;
      @(posedge clk);
        c <= 1'b1;
      # 150;
      @(posedge clk);
        a <= 1'b0;



    # 150;
    @(posedge clk);
      $display("Eleccion de señal c=0, entonces s1=x y s2=1");
      a <= 1'b0;
      b <= 1'b0;
      c <= 1'b0;
      s1 <= 1'bx;
      s2 <= 1'b1;


      # 150;
      @(posedge clk);
        a <= 1'b1;
      # 150;
      @(posedge clk);
        b <= 1'b1;
      # 150;
      @(posedge clk);
        a <= 1'b0;


    # 150;
    @(posedge clk);
    $display("Eleccion de señal c=1, entonces s0=x y s1=1");
      a <= 1'b0;
      b <= 1'b0;
      c <= 1'b1;
      s1 <= 1'bx;
      s2 <= 1'b1;

      # 150;
      @(posedge clk);
        a <= 1'b1;
      # 150;
      @(posedge clk);
        b <= 1'b1;
      # 150;
      @(posedge clk);
        a <= 1'b0;
    # 150;
    @(posedge clk);
    $finish;
  end

  initial
    begin
    $dumpfile("./tests/testternarioDoble.vcd");
    $dumpvars;
    $display("------------------------------------");
    $display("-- Test para modulo ternarioDoble --");
    $display("------------------------------------");
    $display ("\t     tiempo | a | b | c | s1 | s2 | y | tiempo");
    $monitor            ("%t| %b | %b | %b | %b  | %b  | %b | %f ns",
                          $time, a, b, c, s1, s2, y, $realtime);
  end
endmodule