data/full_repos/permissive/128426084/src/sources_1/new/image_rom.v
data/verilator_xmls/d472dede-d4f7-4460-a439-cb9aa6e62d61.xml
module image_rom (
    input wire clk ,
    input wire [11:0] address,
    output reg [11:0] rgb
);


reg [11:0] rom [0:4095];

initial $readmemh("image_rom.data", rom); 

always @(posedge clk)
    rgb <= rom[address];

endmodule
module image_rom (
    input wire clk ,
    input wire [11:0] address,
    output reg [11:0] rgb
);



reg [11:0] rom [0:4095];

initial $readmemh("image_rom.data", rom); 

always @(posedge clk)
    rgb <= rom[address];

endmodule