data/full_repos/permissive/143278/blif/blif02a.v
 line:21: before: "for"
data/verilator_xmls/77d5873e-fd1f-4d80-a1a3-14f1910ac09f.xml
module add1(input A, input B, input Cin, output reg Q, output reg Cout);

   always @* begin
      Q = A ^ B ^ Cin;
      Cout = A&B | A&Cin | B&Cin;
   end

endmodule
module add1(input A, input B, input Cin, output reg Q, output reg Cout);


   always @* begin
      Q = A ^ B ^ Cin;
      Cout = A&B | A&Cin | B&Cin;
   end

endmodule