data/full_repos/permissive/143278/ivltests/lh_catadd.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/lh_catadd.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

   wire [3:0] a = 7, b = 13 ;
   wire [3:0] sum ;
   wire carry ;
   assign {carry,sum} = a + b ;

   initial begin
      #1
      if (carry !== 1'b1) begin
	 $display("FAILED: carry === %b", carry);
	 $finish;
      end

      if (sum !== 4'b0100) begin
	 $display("FAILED: sum === %b", sum);
	 $finish;
      end

      $display("Correct results {carry,sum} === %b,%b", carry, sum);
      $display("PASSED");
   end
endmodule
module test;


   wire [3:0] a = 7, b = 13 ;
   wire [3:0] sum ;
   wire carry ;
   assign {carry,sum} = a + b ;

   initial begin
      #1
      if (carry !== 1'b1) begin
	 $display("FAILED: carry === %b", carry);
	 $finish;
      end

      if (sum !== 4'b0100) begin
	 $display("FAILED: sum === %b", sum);
	 $finish;
      end

      $display("Correct results {carry,sum} === %b,%b", carry, sum);
      $display("PASSED");
   end
endmodule