data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl/tart_v1_0.v
None: at end of input
1: b'%Error: data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl/tart_v1_0.v:4: Cannot find include file: tartcfg.v\n`include "tartcfg.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl,data/full_repos/permissive/20430511/tartcfg.v\n             data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl,data/full_repos/permissive/20430511/tartcfg.v.v\n             data/full_repos/permissive/20430511/hardware/FPGA/zynq/tart_1.0/hdl,data/full_repos/permissive/20430511/tartcfg.v.sv\n             tartcfg.v\n             tartcfg.v.v\n             tartcfg.v.sv\n             obj_dir/tartcfg.v\n             obj_dir/tartcfg.v.v\n             obj_dir/tartcfg.v.sv\n%Error: Exiting due to 1 error(s)\n'
module tart_v1_0 #
(		

    parameter integer ANTENNAE = 24,
    parameter integer NSB      = 23,
    parameter integer ALIGN    = 1,
    
    parameter integer ACCUM_BITS = 24,
    parameter integer VISB_LOG2  = 20,
    
    parameter integer READ_BANKS  = 16,
    parameter integer BANK_BITS  = 4,
    
    parameter integer WBADR_BITS = 12,
    parameter integer WBBUS_BITS =  8,
    
    parameter integer TMUX_RATE  = 12,
    parameter integer TMUX_BITS  =  4,
    
    parameter integer READ_COUNT = 576,
    parameter integer READ_BITS  =  10,
    

    parameter integer DEBUG    = 0,
    parameter integer MULTI    = 1,
    parameter integer RNG      = 1,
    parameter integer CONST    = 0,
    parameter integer CDATA    = 24'h0,
    

    parameter integer ASYNC    = 0,
    parameter integer PIPED    = 1,
    parameter integer RESET    = 0,
    parameter integer CHECK    = 1,

    parameter integer VIZWR    = 0,
    

    parameter integer DELAY    = 3,
    


    parameter integer C_S00_AXI_DATA_WIDTH	= 32,
    parameter integer C_S00_AXI_ADDR_WIDTH	= 10,
    

    parameter integer C_M00_AXIS_TDATA_WIDTH    = 32
)
(

    input [NSB:0]      antenna,

    input clk_locked,
    input clk_i,
    input clk6x_i,
    input clk6n_i,
    input clk12x_i,
   

    input wire  s00_axi_aclk,
    input wire  s00_axi_aresetn,
    input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
    input wire [2 : 0] s00_axi_awprot,
    input wire  s00_axi_awvalid,
    output wire  s00_axi_awready,
    input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
    input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
    input wire  s00_axi_wvalid,
    output wire  s00_axi_wready,
    output wire [1 : 0] s00_axi_bresp,
    output wire  s00_axi_bvalid,
    input wire  s00_axi_bready,
    input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
    input wire [2 : 0] s00_axi_arprot,
    input wire  s00_axi_arvalid,
    output wire  s00_axi_arready,
    output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
    output wire [1 : 0] s00_axi_rresp,
    output wire  s00_axi_rvalid,
    input wire  s00_axi_rready,
    
    

    input wire  m00_axis_aclk,
    input wire  m00_axis_aresetn,
    output wire  m00_axis_tvalid,
    output wire [C_M00_AXIS_TDATA_WIDTH-1 : 0] m00_axis_tdata,
    output wire [(C_M00_AXIS_TDATA_WIDTH/8)-1 : 0] m00_axis_tstrb,
    output wire  m00_axis_tlast,
    input wire  m00_axis_tready
);






    parameter ACCUM = ACCUM_BITS;
    parameter BLOCK = ACCUM;
    parameter MSB   = BLOCK-1;
    parameter TRATE = TMUX_RATE;
    parameter TBITS = TMUX_BITS;
    parameter COUNT = VISB_LOG2;
    parameter NREAD = READ_COUNT;
    parameter RBITS = READ_BITS;
    parameter RSB   = RBITS-1;
    

    parameter BBITS = WBBUS_BITS;
    parameter BSB   = BBITS-1;
    parameter WSB   = BBITS-2;
    parameter ABITS = WBADR_BITS;
    parameter ASB   = ABITS-1;


    parameter XBITS = BANK_BITS;
    parameter XSB   = XBITS-1;
    

    parameter CBITS = XBITS+RBITS;
    parameter CSB   = CBITS-1;
    





    wire fpga_clk;
    wire clk_x;
    wire reset;
    
    wire                clock_n, reset_n;
    wire                clock_b, reset_b;
    
    wire                rx_clk_16_buf;
    
    


    wire         axi_cyc, axi_stb, axi_we;
    wire         axi_ack, axi_wat, axi_rty, axi_err;
    wire [WSB:0] axi_adr;
    wire [BSB:0] axi_dtx, axi_drx;
    


    wire         cap_cyc, cap_stb, cap_we;
    wire         cap_ack, cap_wat, cap_rty, cap_err;
    wire [1:0]   cap_adr;
    wire [BSB:0] cap_drx, cap_dtx;

    wire         acq_cyc, acq_stb, acq_we;
    wire         acq_ack, acq_wat, acq_rty, acq_err;
    wire [1:0]   acq_adr;
    wire [BSB:0] acq_drx, acq_dtx;
    

    wire         dsp_cyc, dsp_stb, dsp_we;
    wire         dsp_ack, dsp_wat, dsp_rty, dsp_err;
    wire [1:0]   dsp_adr;
    wire [BSB:0] dsp_drx, dsp_dtx;
    

    wire         sys_cyc, sys_stb, sys_we;
    wire         sys_ack, sys_wat, sys_rty, sys_err;
    wire [1:0]   sys_adr;
    wire [BSB:0] sys_drx, sys_dtx;
    


    wire                vx_enabled, vx_pending, vx_overflow, vx_overwrite;
    wire                vx_newblock, vx_streamed, vx_switching, vx_accessed;
    wire [MSB:0]        vx_checksum;
    wire                vx_stuck, vx_limp;
    wire [XSB:0]        vx_bank;
    


    wire                cx_enabled, cx_debug;
    wire                cx_strobe, cx_middle, cx_locked;
    wire [MSB:0]        cx_signal;
    


    wire                aq_enabled;
    wire [2:0]          aq_state;
    


    wire                axi_busy, request_from_axi;
    wire                axi_uflow, axi_oflow;
    wire [7:0]          sys_status, axi_status;
    


    assign clock_b = fpga_clk;
    assign reset_b = reset;
   



    assign sys_status =  {vx_enabled, vx_pending,
                          cx_enabled,   cx_debug,
                          aq_enabled,  aq_state};
    assign axi_status = {axi_oflow, axi_uflow, 5'h0, axi_busy};



    
    assign fpga_clk = clk6x_i;
    assign clock_n = clk6n_i;
    assign rx_clk_16_buf = clk_i;
    assign clk_x = clk12x_i;

    assign reset_n = !clk_locked;







    (* NOMERGE *) reg reset_tartwb = 1'b1;

    always @(posedge clock_b)
	    reset_tartwb <= #DELAY reset_b;












    tart_wishbone
    #(  
	    .XBITS(2),
	    .ASYNC(1),
	    .RESET(RESET),
	    .PIPED(PIPED),
	    .CHECK(CHECK),

	    .CAPEN(1),
	    .ACQEN(1),
	    .DSPEN(1),
	    .SYSEN(1),

	    .DELAY(DELAY)
    ) ARB
    (
	    .bus_clk_i(clock_b),
	    .bus_rst_i(reset_tartwb),



	    .master_cyc_i(axi_cyc),
	    .master_stb_i(axi_stb),
	    .master_we_i (axi_we),
	    .master_ack_o(axi_ack),
	    .master_wat_o(axi_wat),
	    .master_rty_o(axi_rty),
	    .master_err_o(axi_err),
	    .master_adr_i(axi_adr),
	    .master_dat_i(axi_drx),
	    .master_dat_o(axi_dtx),



	    .cap_cyc_o(cap_cyc),
	    .cap_stb_o(cap_stb),
	    .cap_we_o (cap_we),
	    .cap_ack_i(cap_ack),
	    .cap_wat_i(cap_wat),
	    .cap_rty_i(cap_rty),
	    .cap_err_i(cap_err),
	    .cap_adr_o(cap_adr),
	    .cap_dat_i(cap_drx),
	    .cap_dat_o(cap_dtx),


	    .acq_cyc_o(acq_cyc),
	    .acq_stb_o(acq_stb),
	    .acq_we_o (acq_we),
	    .acq_ack_i(acq_ack),
	    .acq_wat_i(acq_wat),
	    .acq_rty_i(acq_rty),
	    .acq_err_i(acq_err),
	    .acq_adr_o(acq_adr),
	    .acq_dat_i(acq_drx),
	    .acq_dat_o(acq_dtx),


	    .dsp_cyc_o(dsp_cyc),
	    .dsp_stb_o(dsp_stb),
	    .dsp_we_o (dsp_we),
	    .dsp_ack_i(dsp_ack),
	    .dsp_wat_i(dsp_wat),
	    .dsp_rty_i(dsp_rty),
	    .dsp_err_i(dsp_err),
	    .dsp_adr_o(dsp_adr),
	    .dsp_dat_i(dsp_drx),
	    .dsp_dat_o(dsp_dtx),


	    .sys_cyc_o(sys_cyc),
	    .sys_stb_o(sys_stb),
	    .sys_we_o (sys_we),
	    .sys_ack_i(sys_ack),
	    .sys_wat_i(sys_wat),
	    .sys_rty_i(sys_rty),
	    .sys_err_i(sys_err),
	    .sys_adr_o(sys_adr),
	    .sys_dat_i(sys_drx),
	    .sys_dat_o(sys_dtx)

    );







    (* NOMERGE *) reg reset_axi = 1'b1;

    always @(posedge clock_b)
	    reset_axi <= #DELAY reset_b;






    tart_v1_0_S00_AXI # (
	    .WIDTH(BBITS),
	    .ASYNC(1),
	    .PIPED(PIPED),
	    .CHECK(CHECK),
	    .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
	    .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
    ) tart_v1_0_S00_AXI_inst (
	    .clk_i     (clock_b),
	    .rst_i     (reset_axi),


	    .cyc_o     (axi_cyc),
	    .stb_o     (axi_stb),
	    .we_o      (axi_we),
	    .ack_i     (axi_ack),
	    .wat_i     (axi_wat),
	    .rty_i     (axi_rty),
	    .err_i     (axi_err),
	    .adr_o     (axi_adr),
	    .dat_i     (axi_dtx),
	    .dat_o     (axi_drx),

	    .busy_o    (axi_busy),

	    .S_AXI_ACLK(s00_axi_aclk),
	    .S_AXI_ARESETN(s00_axi_aresetn),
	    .S_AXI_AWADDR(s00_axi_awaddr),
	    .S_AXI_AWPROT(s00_axi_awprot),
	    .S_AXI_AWVALID(s00_axi_awvalid),
	    .S_AXI_AWREADY(s00_axi_awready),
	    .S_AXI_WDATA(s00_axi_wdata),
	    .S_AXI_WSTRB(s00_axi_wstrb),
	    .S_AXI_WVALID(s00_axi_wvalid),
	    .S_AXI_WREADY(s00_axi_wready),
	    .S_AXI_BRESP(s00_axi_bresp),
	    .S_AXI_BVALID(s00_axi_bvalid),
	    .S_AXI_BREADY(s00_axi_bready),
	    .S_AXI_ARADDR(s00_axi_araddr),
	    .S_AXI_ARPROT(s00_axi_arprot),
	    .S_AXI_ARVALID(s00_axi_arvalid),
	    .S_AXI_ARREADY(s00_axi_arready),
	    .S_AXI_RDATA(s00_axi_rdata),
	    .S_AXI_RRESP(s00_axi_rresp),
	    .S_AXI_RVALID(s00_axi_rvalid),
	    .S_AXI_RREADY(s00_axi_rready)
    );







    (* NOMERGE *) reg reset_capture = 1'b1;

    always @(posedge clock_b)
	    reset_capture <= #DELAY reset_b;











    tart_capture
    #( 
	    .AXNUM(ANTENNAE),

	    .ALIGN(ALIGN),
	    .RATIO(TRATE),
	    .RBITS(TBITS),
	    .TICKS(4),

	    .RESET(RESET),
		    .PIPED(PIPED),
		    .CHECK(CHECK),

		    .MULTI(MULTI),
		    .RNG  (RNG),
		    .CONST(CONST),
		    .CDATA(CDATA),

		    .DELAY(DELAY)
	    ) CAPTURE
	    (


		    .clock_e   (rx_clk_16_buf),
		    .clock_n   (clock_n),
		    .clock_i   (clock_b),
		    .reset_i   (reset_capture),



		    .cyc_i     (cap_cyc),
		    .stb_i     (cap_stb),
		    .we_i      (cap_we ),
		    .ack_o     (cap_ack),
		    .wat_o     (cap_wat),
		    .rty_o     (cap_rty),
		    .err_o     (cap_err),
		    .adr_i     (cap_adr),
		    .dat_i     (cap_dtx),
		    .dat_o     (cap_drx),



		    .signal_e_i(antenna),



		    .enabled_o(cx_enabled),
		    .strobe_o (cx_strobe),
		    .middle_o (cx_middle),
		    .signal_o (cx_signal),
		    .centred_o(cx_locked),
		    .debug_o  (cx_debug)
	    );









	    (* NOMERGE *) reg reset_acquire = 1'b1;

	    always @(posedge clock_b)
		    reset_acquire <= #DELAY reset_b;







	    tart_acquire
	    #( 
		    .AXNUM    (ANTENNAE),

		    .BBITS    (BBITS),
		    .PIPED    (PIPED),
		    .RESET    (0),
		    .CHECK    (CHECK),
		    .DELAY    (DELAY),
		    
		    .C_M_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH)
	    ) ACQUIRE
	    ( 
		    .clock_i  (clock_b),
		    .reset_i  (reset_acquire),


		    .locked_i (cx_enabled),
		    .strobe_i (cx_strobe),
		    .middle_i (cx_middle),
		    .signal_i (cx_signal),


		    .cyc_i    (acq_cyc),
		    .stb_i    (acq_stb),
		    .we_i     (acq_we),
		    .ack_o    (acq_ack),
		    .wat_o    (acq_wat),
		    .rty_o    (acq_rty),
		    .err_o    (acq_err),
		    .adr_i    (acq_adr),
		    .dat_i    (acq_dtx),
		    .dat_o    (acq_drx),

		    .M_AXIS_ACLK(m00_axis_aclk),
		    .M_AXIS_ARESETN(m00_axis_aresetn),
		    .M_AXIS_TVALID(m00_axis_tvalid),
		    .M_AXIS_TDATA(m00_axis_tdata),
		    .M_AXIS_TSTRB(m00_axis_tstrb),
		    .M_AXIS_TLAST(m00_axis_tlast),
		    .M_AXIS_TREADY(m00_axis_tready),


		    .enabled_o(aq_enabled),
		    .state_o  (aq_state)
	    );


	    `ifdef __USE_CORRELATORS






		    (* NOMERGE *) reg reset_dsp = 1'b1;

		    always @(posedge clock_b)
			    reset_dsp <= #DELAY reset_b;





		    tart_dsp
		    #( 
			    .AXNUM(ANTENNAE),
			    .ACCUM(ACCUM),
			    .TRATE(TRATE),
			    .TBITS(TBITS),
			    .NREAD(NREAD),
			    .RBITS(RBITS),
			    .XBITS(XBITS),
			    .CBITS(CBITS),

			    .PIPED(PIPED),
			    .CHECK(CHECK),
			    .VIZWR(VIZWR),

			    .DELAY(DELAY)
		    ) DSP
		    (

			    .clk_x(clk_x),
			    .clk_i(clock_b),
			    .rst_i(reset_dsp),



			    .vld_i(cx_enabled),
			    .new_i(cx_strobe),
			    .sig_i(cx_signal),



			    .cyc_i(dsp_cyc),
			    .stb_i(dsp_stb),
			    .we_i (dsp_we),
			    .ack_o(dsp_ack),
			    .wat_o(dsp_wat),
			    .rty_o(dsp_rty),
			    .err_o(dsp_err),
			    .adr_i(dsp_adr),
			    .dat_i(dsp_dtx),
			    .dat_o(dsp_drx),



			    .sce_i(axi_busy),


			    .enabled_o  (vx_enabled ),
			    .pending_o  (vx_pending ),
			    .newblock_o (vx_newblock),
			    .checksum_o (vx_checksum),
			    .streamed_o (vx_streamed),



			    .bank_o     (vx_bank),
			    .overflow_o (vx_overflow),
			    .stuck_o    (vx_stuck),
			    .limp_o     (vx_limp)
		    );


	    `else



		    assign vx_streamed = 1'b0;
		    assign vx_newblock = 1'b0;
		    assign vx_pending  = 1'b0;
		    assign vx_checksum = 24'h0ff1ce;

	    `endif










	    tart_control
	    #( 
		    .WIDTH(BBITS),
		    .RTIME(4),
		    .CHECK(0),
		    .PIPED(1),
		    .DELAY(DELAY)
	    ) CONTROL
	    (
		    .clk_i(clock_b),
		    .rst_i(reset_b),

		    .cyc_i(sys_cyc),
		    .stb_i(sys_stb),
		    .we_i (sys_we),
		    .ack_o(sys_ack),
		    .wat_o(sys_wat),
		    .rty_o(sys_rty),
		    .err_o(sys_err),
		    .adr_i(sys_adr),
		    .dat_i(sys_dtx),
		    .dat_o(sys_drx),

		    .status_i(sys_status),
		    .extra_i (axi_status),
		    .reset_ni(reset_n),
		    .reset_o (reset)
	    );


	    endmodule
module tart_v1_0 #
(		

    parameter integer ANTENNAE = 24,
    parameter integer NSB      = 23,
    parameter integer ALIGN    = 1,
    
    parameter integer ACCUM_BITS = 24,
    parameter integer VISB_LOG2  = 20,
    
    parameter integer READ_BANKS  = 16,
    parameter integer BANK_BITS  = 4,
    
    parameter integer WBADR_BITS = 12,
    parameter integer WBBUS_BITS =  8,
    
    parameter integer TMUX_RATE  = 12,
    parameter integer TMUX_BITS  =  4,
    
    parameter integer READ_COUNT = 576,
    parameter integer READ_BITS  =  10,
    

    parameter integer DEBUG    = 0,
    parameter integer MULTI    = 1,
    parameter integer RNG      = 1,
    parameter integer CONST    = 0,
    parameter integer CDATA    = 24'h0,
    

    parameter integer ASYNC    = 0,
    parameter integer PIPED    = 1,
    parameter integer RESET    = 0,
    parameter integer CHECK    = 1,

    parameter integer VIZWR    = 0,
    

    parameter integer DELAY    = 3,
    


    parameter integer C_S00_AXI_DATA_WIDTH	= 32,
    parameter integer C_S00_AXI_ADDR_WIDTH	= 10,
    

    parameter integer C_M00_AXIS_TDATA_WIDTH    = 32
)
(

    input [NSB:0]      antenna,

    input clk_locked,
    input clk_i,
    input clk6x_i,
    input clk6n_i,
    input clk12x_i,
   

    input wire  s00_axi_aclk,
    input wire  s00_axi_aresetn,
    input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
    input wire [2 : 0] s00_axi_awprot,
    input wire  s00_axi_awvalid,
    output wire  s00_axi_awready,
    input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
    input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
    input wire  s00_axi_wvalid,
    output wire  s00_axi_wready,
    output wire [1 : 0] s00_axi_bresp,
    output wire  s00_axi_bvalid,
    input wire  s00_axi_bready,
    input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
    input wire [2 : 0] s00_axi_arprot,
    input wire  s00_axi_arvalid,
    output wire  s00_axi_arready,
    output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
    output wire [1 : 0] s00_axi_rresp,
    output wire  s00_axi_rvalid,
    input wire  s00_axi_rready,
    
    

    input wire  m00_axis_aclk,
    input wire  m00_axis_aresetn,
    output wire  m00_axis_tvalid,
    output wire [C_M00_AXIS_TDATA_WIDTH-1 : 0] m00_axis_tdata,
    output wire [(C_M00_AXIS_TDATA_WIDTH/8)-1 : 0] m00_axis_tstrb,
    output wire  m00_axis_tlast,
    input wire  m00_axis_tready
);







    parameter ACCUM = ACCUM_BITS;
    parameter BLOCK = ACCUM;
    parameter MSB   = BLOCK-1;
    parameter TRATE = TMUX_RATE;
    parameter TBITS = TMUX_BITS;
    parameter COUNT = VISB_LOG2;
    parameter NREAD = READ_COUNT;
    parameter RBITS = READ_BITS;
    parameter RSB   = RBITS-1;
    

    parameter BBITS = WBBUS_BITS;
    parameter BSB   = BBITS-1;
    parameter WSB   = BBITS-2;
    parameter ABITS = WBADR_BITS;
    parameter ASB   = ABITS-1;


    parameter XBITS = BANK_BITS;
    parameter XSB   = XBITS-1;
    

    parameter CBITS = XBITS+RBITS;
    parameter CSB   = CBITS-1;
    





    wire fpga_clk;
    wire clk_x;
    wire reset;
    
    wire                clock_n, reset_n;
    wire                clock_b, reset_b;
    
    wire                rx_clk_16_buf;
    
    


    wire         axi_cyc, axi_stb, axi_we;
    wire         axi_ack, axi_wat, axi_rty, axi_err;
    wire [WSB:0] axi_adr;
    wire [BSB:0] axi_dtx, axi_drx;
    


    wire         cap_cyc, cap_stb, cap_we;
    wire         cap_ack, cap_wat, cap_rty, cap_err;
    wire [1:0]   cap_adr;
    wire [BSB:0] cap_drx, cap_dtx;

    wire         acq_cyc, acq_stb, acq_we;
    wire         acq_ack, acq_wat, acq_rty, acq_err;
    wire [1:0]   acq_adr;
    wire [BSB:0] acq_drx, acq_dtx;
    

    wire         dsp_cyc, dsp_stb, dsp_we;
    wire         dsp_ack, dsp_wat, dsp_rty, dsp_err;
    wire [1:0]   dsp_adr;
    wire [BSB:0] dsp_drx, dsp_dtx;
    

    wire         sys_cyc, sys_stb, sys_we;
    wire         sys_ack, sys_wat, sys_rty, sys_err;
    wire [1:0]   sys_adr;
    wire [BSB:0] sys_drx, sys_dtx;
    


    wire                vx_enabled, vx_pending, vx_overflow, vx_overwrite;
    wire                vx_newblock, vx_streamed, vx_switching, vx_accessed;
    wire [MSB:0]        vx_checksum;
    wire                vx_stuck, vx_limp;
    wire [XSB:0]        vx_bank;
    


    wire                cx_enabled, cx_debug;
    wire                cx_strobe, cx_middle, cx_locked;
    wire [MSB:0]        cx_signal;
    


    wire                aq_enabled;
    wire [2:0]          aq_state;
    


    wire                axi_busy, request_from_axi;
    wire                axi_uflow, axi_oflow;
    wire [7:0]          sys_status, axi_status;
    


    assign clock_b = fpga_clk;
    assign reset_b = reset;
   



    assign sys_status =  {vx_enabled, vx_pending,
                          cx_enabled,   cx_debug,
                          aq_enabled,  aq_state};
    assign axi_status = {axi_oflow, axi_uflow, 5'h0, axi_busy};



    
    assign fpga_clk = clk6x_i;
    assign clock_n = clk6n_i;
    assign rx_clk_16_buf = clk_i;
    assign clk_x = clk12x_i;

    assign reset_n = !clk_locked;







    (* NOMERGE *) reg reset_tartwb = 1'b1;

    always @(posedge clock_b)
	    reset_tartwb <= #DELAY reset_b;












    tart_wishbone
    #(  
	    .XBITS(2),
	    .ASYNC(1),
	    .RESET(RESET),
	    .PIPED(PIPED),
	    .CHECK(CHECK),

	    .CAPEN(1),
	    .ACQEN(1),
	    .DSPEN(1),
	    .SYSEN(1),

	    .DELAY(DELAY)
    ) ARB
    (
	    .bus_clk_i(clock_b),
	    .bus_rst_i(reset_tartwb),



	    .master_cyc_i(axi_cyc),
	    .master_stb_i(axi_stb),
	    .master_we_i (axi_we),
	    .master_ack_o(axi_ack),
	    .master_wat_o(axi_wat),
	    .master_rty_o(axi_rty),
	    .master_err_o(axi_err),
	    .master_adr_i(axi_adr),
	    .master_dat_i(axi_drx),
	    .master_dat_o(axi_dtx),



	    .cap_cyc_o(cap_cyc),
	    .cap_stb_o(cap_stb),
	    .cap_we_o (cap_we),
	    .cap_ack_i(cap_ack),
	    .cap_wat_i(cap_wat),
	    .cap_rty_i(cap_rty),
	    .cap_err_i(cap_err),
	    .cap_adr_o(cap_adr),
	    .cap_dat_i(cap_drx),
	    .cap_dat_o(cap_dtx),


	    .acq_cyc_o(acq_cyc),
	    .acq_stb_o(acq_stb),
	    .acq_we_o (acq_we),
	    .acq_ack_i(acq_ack),
	    .acq_wat_i(acq_wat),
	    .acq_rty_i(acq_rty),
	    .acq_err_i(acq_err),
	    .acq_adr_o(acq_adr),
	    .acq_dat_i(acq_drx),
	    .acq_dat_o(acq_dtx),


	    .dsp_cyc_o(dsp_cyc),
	    .dsp_stb_o(dsp_stb),
	    .dsp_we_o (dsp_we),
	    .dsp_ack_i(dsp_ack),
	    .dsp_wat_i(dsp_wat),
	    .dsp_rty_i(dsp_rty),
	    .dsp_err_i(dsp_err),
	    .dsp_adr_o(dsp_adr),
	    .dsp_dat_i(dsp_drx),
	    .dsp_dat_o(dsp_dtx),


	    .sys_cyc_o(sys_cyc),
	    .sys_stb_o(sys_stb),
	    .sys_we_o (sys_we),
	    .sys_ack_i(sys_ack),
	    .sys_wat_i(sys_wat),
	    .sys_rty_i(sys_rty),
	    .sys_err_i(sys_err),
	    .sys_adr_o(sys_adr),
	    .sys_dat_i(sys_drx),
	    .sys_dat_o(sys_dtx)

    );







    (* NOMERGE *) reg reset_axi = 1'b1;

    always @(posedge clock_b)
	    reset_axi <= #DELAY reset_b;






    tart_v1_0_S00_AXI # (
	    .WIDTH(BBITS),
	    .ASYNC(1),
	    .PIPED(PIPED),
	    .CHECK(CHECK),
	    .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
	    .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
    ) tart_v1_0_S00_AXI_inst (
	    .clk_i     (clock_b),
	    .rst_i     (reset_axi),


	    .cyc_o     (axi_cyc),
	    .stb_o     (axi_stb),
	    .we_o      (axi_we),
	    .ack_i     (axi_ack),
	    .wat_i     (axi_wat),
	    .rty_i     (axi_rty),
	    .err_i     (axi_err),
	    .adr_o     (axi_adr),
	    .dat_i     (axi_dtx),
	    .dat_o     (axi_drx),

	    .busy_o    (axi_busy),

	    .S_AXI_ACLK(s00_axi_aclk),
	    .S_AXI_ARESETN(s00_axi_aresetn),
	    .S_AXI_AWADDR(s00_axi_awaddr),
	    .S_AXI_AWPROT(s00_axi_awprot),
	    .S_AXI_AWVALID(s00_axi_awvalid),
	    .S_AXI_AWREADY(s00_axi_awready),
	    .S_AXI_WDATA(s00_axi_wdata),
	    .S_AXI_WSTRB(s00_axi_wstrb),
	    .S_AXI_WVALID(s00_axi_wvalid),
	    .S_AXI_WREADY(s00_axi_wready),
	    .S_AXI_BRESP(s00_axi_bresp),
	    .S_AXI_BVALID(s00_axi_bvalid),
	    .S_AXI_BREADY(s00_axi_bready),
	    .S_AXI_ARADDR(s00_axi_araddr),
	    .S_AXI_ARPROT(s00_axi_arprot),
	    .S_AXI_ARVALID(s00_axi_arvalid),
	    .S_AXI_ARREADY(s00_axi_arready),
	    .S_AXI_RDATA(s00_axi_rdata),
	    .S_AXI_RRESP(s00_axi_rresp),
	    .S_AXI_RVALID(s00_axi_rvalid),
	    .S_AXI_RREADY(s00_axi_rready)
    );







    (* NOMERGE *) reg reset_capture = 1'b1;

    always @(posedge clock_b)
	    reset_capture <= #DELAY reset_b;











    tart_capture
    #( 
	    .AXNUM(ANTENNAE),

	    .ALIGN(ALIGN),
	    .RATIO(TRATE),
	    .RBITS(TBITS),
	    .TICKS(4),

	    .RESET(RESET),
		    .PIPED(PIPED),
		    .CHECK(CHECK),

		    .MULTI(MULTI),
		    .RNG  (RNG),
		    .CONST(CONST),
		    .CDATA(CDATA),

		    .DELAY(DELAY)
	    ) CAPTURE
	    (


		    .clock_e   (rx_clk_16_buf),
		    .clock_n   (clock_n),
		    .clock_i   (clock_b),
		    .reset_i   (reset_capture),



		    .cyc_i     (cap_cyc),
		    .stb_i     (cap_stb),
		    .we_i      (cap_we ),
		    .ack_o     (cap_ack),
		    .wat_o     (cap_wat),
		    .rty_o     (cap_rty),
		    .err_o     (cap_err),
		    .adr_i     (cap_adr),
		    .dat_i     (cap_dtx),
		    .dat_o     (cap_drx),



		    .signal_e_i(antenna),



		    .enabled_o(cx_enabled),
		    .strobe_o (cx_strobe),
		    .middle_o (cx_middle),
		    .signal_o (cx_signal),
		    .centred_o(cx_locked),
		    .debug_o  (cx_debug)
	    );









	    (* NOMERGE *) reg reset_acquire = 1'b1;

	    always @(posedge clock_b)
		    reset_acquire <= #DELAY reset_b;







	    tart_acquire
	    #( 
		    .AXNUM    (ANTENNAE),

		    .BBITS    (BBITS),
		    .PIPED    (PIPED),
		    .RESET    (0),
		    .CHECK    (CHECK),
		    .DELAY    (DELAY),
		    
		    .C_M_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH)
	    ) ACQUIRE
	    ( 
		    .clock_i  (clock_b),
		    .reset_i  (reset_acquire),


		    .locked_i (cx_enabled),
		    .strobe_i (cx_strobe),
		    .middle_i (cx_middle),
		    .signal_i (cx_signal),


		    .cyc_i    (acq_cyc),
		    .stb_i    (acq_stb),
		    .we_i     (acq_we),
		    .ack_o    (acq_ack),
		    .wat_o    (acq_wat),
		    .rty_o    (acq_rty),
		    .err_o    (acq_err),
		    .adr_i    (acq_adr),
		    .dat_i    (acq_dtx),
		    .dat_o    (acq_drx),

		    .M_AXIS_ACLK(m00_axis_aclk),
		    .M_AXIS_ARESETN(m00_axis_aresetn),
		    .M_AXIS_TVALID(m00_axis_tvalid),
		    .M_AXIS_TDATA(m00_axis_tdata),
		    .M_AXIS_TSTRB(m00_axis_tstrb),
		    .M_AXIS_TLAST(m00_axis_tlast),
		    .M_AXIS_TREADY(m00_axis_tready),


		    .enabled_o(aq_enabled),
		    .state_o  (aq_state)
	    );


	    `ifdef __USE_CORRELATORS






		    (* NOMERGE *) reg reset_dsp = 1'b1;

		    always @(posedge clock_b)
			    reset_dsp <= #DELAY reset_b;





		    tart_dsp
		    #( 
			    .AXNUM(ANTENNAE),
			    .ACCUM(ACCUM),
			    .TRATE(TRATE),
			    .TBITS(TBITS),
			    .NREAD(NREAD),
			    .RBITS(RBITS),
			    .XBITS(XBITS),
			    .CBITS(CBITS),

			    .PIPED(PIPED),
			    .CHECK(CHECK),
			    .VIZWR(VIZWR),

			    .DELAY(DELAY)
		    ) DSP
		    (

			    .clk_x(clk_x),
			    .clk_i(clock_b),
			    .rst_i(reset_dsp),



			    .vld_i(cx_enabled),
			    .new_i(cx_strobe),
			    .sig_i(cx_signal),



			    .cyc_i(dsp_cyc),
			    .stb_i(dsp_stb),
			    .we_i (dsp_we),
			    .ack_o(dsp_ack),
			    .wat_o(dsp_wat),
			    .rty_o(dsp_rty),
			    .err_o(dsp_err),
			    .adr_i(dsp_adr),
			    .dat_i(dsp_dtx),
			    .dat_o(dsp_drx),



			    .sce_i(axi_busy),


			    .enabled_o  (vx_enabled ),
			    .pending_o  (vx_pending ),
			    .newblock_o (vx_newblock),
			    .checksum_o (vx_checksum),
			    .streamed_o (vx_streamed),



			    .bank_o     (vx_bank),
			    .overflow_o (vx_overflow),
			    .stuck_o    (vx_stuck),
			    .limp_o     (vx_limp)
		    );


	    `else



		    assign vx_streamed = 1'b0;
		    assign vx_newblock = 1'b0;
		    assign vx_pending  = 1'b0;
		    assign vx_checksum = 24'h0ff1ce;

	    `endif










	    tart_control
	    #( 
		    .WIDTH(BBITS),
		    .RTIME(4),
		    .CHECK(0),
		    .PIPED(1),
		    .DELAY(DELAY)
	    ) CONTROL
	    (
		    .clk_i(clock_b),
		    .rst_i(reset_b),

		    .cyc_i(sys_cyc),
		    .stb_i(sys_stb),
		    .we_i (sys_we),
		    .ack_o(sys_ack),
		    .wat_o(sys_wat),
		    .rty_o(sys_rty),
		    .err_o(sys_err),
		    .adr_i(sys_adr),
		    .dat_i(sys_dtx),
		    .dat_o(sys_drx),

		    .status_i(sys_status),
		    .extra_i (axi_status),
		    .reset_ni(reset_n),
		    .reset_o (reset)
	    );


	    endmodule