data/full_repos/permissive/143278/vhdl_tests/partpv.v
data/verilator_xmls/64e596a5-29a8-4306-8d37-2399fedd5a4c.xml
module top;

  wire [7:0] foo;

  bot b( .q(foo[3:0]) );

endmodule
module top;


  wire [7:0] foo;

  bot b( .q(foo[3:0]) );

endmodule