data/full_repos/permissive/201488448/2_circuits/3_larger/1_counter.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/3_larger/1_counter.v:8: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                          : ... In instance top_module\n            q <= 10'd0;\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/3_larger/1_counter.v:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                           : ... In instance top_module\n            q <= 10'd0;\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/201488448/2_circuits/3_larger/1_counter.v:12: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'q'\n                                                                                           : ... In instance top_module\n            q <= q + 1'b1;\n            ^\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module (
    input clk,
    input reset,
    output [9:0] q);

    always@(posedge clk) begin
        if(reset)
            q <= 10'd0;
        else if(q == 10'd999)
            q <= 10'd0;
        else
            q <= q + 1'b1;
    end
    
endmodule
module top_module (
    input clk,
    input reset,
    output [9:0] q);


    always@(posedge clk) begin
        if(reset)
            q <= 10'd0;
        else if(q == 10'd999)
            q <= 10'd0;
        else
            q <= q + 1'b1;
    end
    
endmodule