data/full_repos/permissive/192905282/ethernet.v
1: b"%Error: data/full_repos/permissive/192905282/ethernet.v:121: Cannot find file containing module: 'io_buf'\nio_buf io_inst\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/192905282,data/full_repos/permissive/192905282/io_buf\n             data/full_repos/permissive/192905282,data/full_repos/permissive/192905282/io_buf.v\n             data/full_repos/permissive/192905282,data/full_repos/permissive/192905282/io_buf.sv\n             io_buf\n             io_buf.v\n             io_buf.sv\n             obj_dir/io_buf\n             obj_dir/io_buf.v\n             obj_dir/io_buf.sv\n%Error: data/full_repos/permissive/192905282/ethernet.v:129: Cannot find file containing module: 'udp_send'\nudp_send\n^~~~~~~~\n%Error: data/full_repos/permissive/192905282/ethernet.v:163: Cannot find file containing module: 'crc'\ncrc crc_inst\n^~~\n%Error: data/full_repos/permissive/192905282/ethernet.v:184: Cannot find file containing module: 'udp_receive'\nudp_receive\n^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module ethernet
#
(
parameter	UDP_SEND_OPEN = 1,
parameter	UDP_RECEIVE_OPEN = 1,
parameter	TTL = 8'd128,

parameter	TX_SRC_ADDR = 32'hc0a80002,
parameter	TX_SRC_PORT = 16'd8000,
parameter	TX_SRC_MAC = 48'h000a3501fec0,


parameter	RX_CAN_RECEIVE_BROADCAST = 1,
parameter	RX_DST_ADDR = 32'hc0a80002,
parameter	RX_DST_PORT = 16'd8000,
parameter	RX_DST_MAC	= 48'h000a3501fec0
)
(

	input					clk		,
	input					rst_n	,

	input					e_rxc	,
	input					e_rxdv	,
	input					e_rxer	,
	input	[7:0]			e_rxd	,

	input					e_txc	,
	output				e_gtxc	,
	output				e_txen	,
	output				e_txer	,
	output	[7:0]		e_txd	,

	output				e_reset	,
	output				e_mdc	,
	inout					e_mdio  ,


	input	[7:0]			data_tx	,
	input	[15:0]		data_len_tx,
	input					cvt_tx	,
	output				busy_tx	,
	output				dv_tx	,
	input	[47:0]		dst_mac	,
	input	[31:0]		dst_addr,
	input	[15:0]		dst_port,
	input					DF_tx	,
	input					MF_tx	,

	output	[15:0]		rx_data_len,
	output	[15:0]		rx_total_len,
	output					update_rx,
	output	[7:0]			data_rx	 ,
	output	[47:0]		src_mac	,
	output	[31:0]		src_addr,
	output	[15:0]		src_port,
	output					DF_rx	,
	output					MF_rx	,
	output	[159:0]		r_ip	,
	output	[63:0]		r_udp	,
	output	[111:0]		r_mac	
);

assign e_gtxc = e_rxc;


assign	e_reset = 1'b1;
assign  	e_mdio = 1'bz;

wire	[31:0]		crc;
wire				crcen;
wire 				crcrst;

wire	[7:0]		txd_r;


io_buf io_inst
	( 
	.datain(txd_r),
	.dataout(e_txd)
	);
	
generate if (UDP_SEND_OPEN == 1)
begin	
udp_send
#
(
.TTL 		(TTL)			,
.SRC_ADDR (TX_SRC_ADDR)	,
.SRC_PORT (TX_SRC_PORT)	,
.SRC_MAC  (TX_SRC_MAC)
)
udp_s_inst(

	.clk		(e_gtxc),
	.rst_n		(rst_n),

	.data_i		(data_tx),
	.tx_data_len(data_len_tx),
	.crc			(crc),
	.crcen		(crcen),
	.crcrst		(crcrst),
	
	.start		(cvt_tx),
	.busy			(busy_tx),
	.tx_dv		(dv_tx),
	.dst_mac		(dst_mac),
	.dst_addr	(dst_addr),
	.dst_port	(dst_port),
	.DF			(DF_tx),
	.MF			(MF_tx),

	.tx_en		(e_txen),
	.txer			(e_txer),

	.txd		(txd_r)
);

crc crc_inst
(
.Clk	(e_gtxc), 
.Reset	(crcrst), 
.Data_in(e_txd), 
.Enable	(crcen), 
.Crc	(crc),
.CrcNext()
);
end
else
begin
assign e_gtxc	= 1'b0;
assign e_txen	= 1'b0;
assign e_txer	= 1'b0;
assign e_txd	= 8'd0;
end
endgenerate

generate if (UDP_RECEIVE_OPEN == 1)
begin
udp_receive
#
(
.CAN_RECEIVE_BROADCAST (RX_CAN_RECEIVE_BROADCAST),
.DST_ADDR 			   (RX_DST_ADDR)			,
.DST_PORT 			   (RX_DST_PORT)			,
.DST_MAC			   (RX_DST_MAC)
)
udp_r_inst(

	.clk		(e_rxc),
	.rst_n		(rst_n),

	.rx_data_len(rx_data_len),
	.rx_total_len(rx_total_len),
	.update		(update_rx),
	.ip_header	(r_ip),
	.udp_header	(r_udp),
	.mac		(r_mac),
	.data_o		(data_rx),
	.src_mac	(src_mac),
	.src_addr	(src_addr),
	.src_port	(src_port),
	.DF			(DF_rx),
	.MF			(MF_rx),

	.e_rxdv		(e_rxdv),	
	.rxd		(e_rxd)
);
end
else
begin
assign rx_data_len = 0;
assign rx_total_len = 0;
assign data_rx = 0;
assign src_mac = 0;
assign src_addr = 0;
assign src_port = 0;
assign r_ip = 0;
assign r_udp = 0;
assign update_rx = 0;
assign DF_rx = 0;
assign MF_rx = 0;
assign r_mac = 0;
end
endgenerate 


endmodule
module ethernet
#
(
parameter	UDP_SEND_OPEN = 1,
parameter	UDP_RECEIVE_OPEN = 1,
parameter	TTL = 8'd128,

parameter	TX_SRC_ADDR = 32'hc0a80002,
parameter	TX_SRC_PORT = 16'd8000,
parameter	TX_SRC_MAC = 48'h000a3501fec0,


parameter	RX_CAN_RECEIVE_BROADCAST = 1,
parameter	RX_DST_ADDR = 32'hc0a80002,
parameter	RX_DST_PORT = 16'd8000,
parameter	RX_DST_MAC	= 48'h000a3501fec0
)
(

	input					clk		,
	input					rst_n	,

	input					e_rxc	,
	input					e_rxdv	,
	input					e_rxer	,
	input	[7:0]			e_rxd	,

	input					e_txc	,
	output				e_gtxc	,
	output				e_txen	,
	output				e_txer	,
	output	[7:0]		e_txd	,

	output				e_reset	,
	output				e_mdc	,
	inout					e_mdio  ,


	input	[7:0]			data_tx	,
	input	[15:0]		data_len_tx,
	input					cvt_tx	,
	output				busy_tx	,
	output				dv_tx	,
	input	[47:0]		dst_mac	,
	input	[31:0]		dst_addr,
	input	[15:0]		dst_port,
	input					DF_tx	,
	input					MF_tx	,

	output	[15:0]		rx_data_len,
	output	[15:0]		rx_total_len,
	output					update_rx,
	output	[7:0]			data_rx	 ,
	output	[47:0]		src_mac	,
	output	[31:0]		src_addr,
	output	[15:0]		src_port,
	output					DF_rx	,
	output					MF_rx	,
	output	[159:0]		r_ip	,
	output	[63:0]		r_udp	,
	output	[111:0]		r_mac	
);


assign e_gtxc = e_rxc;


assign	e_reset = 1'b1;
assign  	e_mdio = 1'bz;

wire	[31:0]		crc;
wire				crcen;
wire 				crcrst;

wire	[7:0]		txd_r;


io_buf io_inst
	( 
	.datain(txd_r),
	.dataout(e_txd)
	);
	
generate if (UDP_SEND_OPEN == 1)
begin	
udp_send
#
(
.TTL 		(TTL)			,
.SRC_ADDR (TX_SRC_ADDR)	,
.SRC_PORT (TX_SRC_PORT)	,
.SRC_MAC  (TX_SRC_MAC)
)
udp_s_inst(

	.clk		(e_gtxc),
	.rst_n		(rst_n),

	.data_i		(data_tx),
	.tx_data_len(data_len_tx),
	.crc			(crc),
	.crcen		(crcen),
	.crcrst		(crcrst),
	
	.start		(cvt_tx),
	.busy			(busy_tx),
	.tx_dv		(dv_tx),
	.dst_mac		(dst_mac),
	.dst_addr	(dst_addr),
	.dst_port	(dst_port),
	.DF			(DF_tx),
	.MF			(MF_tx),

	.tx_en		(e_txen),
	.txer			(e_txer),

	.txd		(txd_r)
);

crc crc_inst
(
.Clk	(e_gtxc), 
.Reset	(crcrst), 
.Data_in(e_txd), 
.Enable	(crcen), 
.Crc	(crc),
.CrcNext()
);
end
else
begin
assign e_gtxc	= 1'b0;
assign e_txen	= 1'b0;
assign e_txer	= 1'b0;
assign e_txd	= 8'd0;
end
endgenerate

generate if (UDP_RECEIVE_OPEN == 1)
begin
udp_receive
#
(
.CAN_RECEIVE_BROADCAST (RX_CAN_RECEIVE_BROADCAST),
.DST_ADDR 			   (RX_DST_ADDR)			,
.DST_PORT 			   (RX_DST_PORT)			,
.DST_MAC			   (RX_DST_MAC)
)
udp_r_inst(

	.clk		(e_rxc),
	.rst_n		(rst_n),

	.rx_data_len(rx_data_len),
	.rx_total_len(rx_total_len),
	.update		(update_rx),
	.ip_header	(r_ip),
	.udp_header	(r_udp),
	.mac		(r_mac),
	.data_o		(data_rx),
	.src_mac	(src_mac),
	.src_addr	(src_addr),
	.src_port	(src_port),
	.DF			(DF_rx),
	.MF			(MF_rx),

	.e_rxdv		(e_rxdv),	
	.rxd		(e_rxd)
);
end
else
begin
assign rx_data_len = 0;
assign rx_total_len = 0;
assign data_rx = 0;
assign src_mac = 0;
assign src_addr = 0;
assign src_port = 0;
assign r_ip = 0;
assign r_udp = 0;
assign update_rx = 0;
assign DF_rx = 0;
assign MF_rx = 0;
assign r_mac = 0;
end
endgenerate 


endmodule