data/full_repos/permissive/182885969/test/cla_adder_4bit_tb.v
1: b'%Error: data/full_repos/permissive/182885969/test/cla_adder_4bit_tb.v:2: Cannot find include file: cla_adder_4bit.v\n`include "cla_adder_4bit.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/182885969/test,data/full_repos/permissive/182885969/cla_adder_4bit.v\n             data/full_repos/permissive/182885969/test,data/full_repos/permissive/182885969/cla_adder_4bit.v.v\n             data/full_repos/permissive/182885969/test,data/full_repos/permissive/182885969/cla_adder_4bit.v.sv\n             cla_adder_4bit.v\n             cla_adder_4bit.v.v\n             cla_adder_4bit.v.sv\n             obj_dir/cla_adder_4bit.v\n             obj_dir/cla_adder_4bit.v.v\n             obj_dir/cla_adder_4bit.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/182885969/test/cla_adder_4bit_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/182885969/test/cla_adder_4bit_tb.v:22: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("cla_adder_4bit_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/182885969/test/cla_adder_4bit_tb.v:23: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, cla_adder_4bit_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/182885969/test/cla_adder_4bit_tb.v:29: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/182885969/test/cla_adder_4bit_tb.v:33: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/182885969/test/cla_adder_4bit_tb.v:37: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/182885969/test/cla_adder_4bit_tb.v:41: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/182885969/test/cla_adder_4bit_tb.v:44: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module cla_adder_4bit_tb;

	integer i = 0;

	reg clk;

	reg [3:0] a, b;
	wire [3:0] s;
	wire c;

	cla_adder_4bit add0(.a(a), .b(b), .c_in(1'b0), .s(s), .c_out(c));

	always begin
		clk <= ~clk;
		#5;
	end

	initial begin
		$dumpfile("cla_adder_4bit_tb.vcd");
		$dumpvars(0, cla_adder_4bit_tb);

		clk <= 1'b0;

		a <= 4'd7;
		b <= 4'd6;
		@(posedge clk);

		a <= 4'd7;
		b <= 4'd8;
		@(posedge clk);

		a <= 4'd8;
		b <= 4'd8;
		@(posedge clk);

		a <= 4'd15;
		b <= 4'd8;
		@(posedge clk);

		for (i = 0; i < 3; i = i + 1) begin
			@(posedge clk);
		end

		$finish;
	end

endmodule
module cla_adder_4bit_tb;


	integer i = 0;

	reg clk;

	reg [3:0] a, b;
	wire [3:0] s;
	wire c;

	cla_adder_4bit add0(.a(a), .b(b), .c_in(1'b0), .s(s), .c_out(c));

	always begin
		clk <= ~clk;
		#5;
	end

	initial begin
		$dumpfile("cla_adder_4bit_tb.vcd");
		$dumpvars(0, cla_adder_4bit_tb);

		clk <= 1'b0;

		a <= 4'd7;
		b <= 4'd6;
		@(posedge clk);

		a <= 4'd7;
		b <= 4'd8;
		@(posedge clk);

		a <= 4'd8;
		b <= 4'd8;
		@(posedge clk);

		a <= 4'd15;
		b <= 4'd8;
		@(posedge clk);

		for (i = 0; i < 3; i = i + 1) begin
			@(posedge clk);
		end

		$finish;
	end

endmodule