data/full_repos/permissive/162696624/Traffic Light.v
 line:32: before: "["
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/162696624/Traffic\n        ... Looked in:\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624,data/full_repos/permissive/162696624/data/full_repos/permissive/162696624/Traffic.sv\n             data/full_repos/permissive/162696624/Traffic\n             data/full_repos/permissive/162696624/Traffic.v\n             data/full_repos/permissive/162696624/Traffic.sv\n             obj_dir/data/full_repos/permissive/162696624/Traffic\n             obj_dir/data/full_repos/permissive/162696624/Traffic.v\n             obj_dir/data/full_repos/permissive/162696624/Traffic.sv\n%Error: Cannot find file containing module: Light.v\n%Error: Exiting due to 2 error(s)\n'
module two_bit_bcd(Q1,Q0,load,count,D1,D0,CLK,RST);
  output [3:0]Q1;
  output [3:0]Q0;
  input load,count,CLK,RST;
  input [3:0]D1;
  input [3:0]D0;
  wire cnt0,cnt1;
  assign cnt1= ~(Q1[0]|Q1[1]|Q1[2]|Q1[3]);
  assign cnt0= ~(Q0[0]|Q0[1]|Q0[2]|Q0[3]);
  reverse rv1(D0,CLK,RST,cnt0,load,count,Q0);
  reverse rv2(D1,CLK,RST,cnt1&cnt0,load,cnt0,Q1);
  
endmodule
module two_bit_bcd(Q1,Q0,load,count,D1,D0,CLK,RST);

  output [3:0]Q1;
  output [3:0]Q0;
  input load,count,CLK,RST;
  input [3:0]D1;
  input [3:0]D0;
  wire cnt0,cnt1;
  assign cnt1= ~(Q1[0]|Q1[1]|Q1[2]|Q1[3]);
  assign cnt0= ~(Q0[0]|Q0[1]|Q0[2]|Q0[3]);
  reverse rv1(D0,CLK,RST,cnt0,load,count,Q0);
  reverse rv2(D1,CLK,RST,cnt1&cnt0,load,cnt0,Q1);
  
endmodule