data/full_repos/permissive/170067905/hw3_2/fullAdder_1b_bench.v
 line:20: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/170067905/hw3_2/fullAdder_1b_bench.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #3200 $finish;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/170067905/hw3_2/fullAdder_1b_bench.v:6: Cannot find file containing module: \'clkrst\'\n   clkrst my_clkrst( .clk(Clk), .rst(rst), .err(err));\n   ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170067905/hw3_2,data/full_repos/permissive/170067905/clkrst\n             data/full_repos/permissive/170067905/hw3_2,data/full_repos/permissive/170067905/clkrst.v\n             data/full_repos/permissive/170067905/hw3_2,data/full_repos/permissive/170067905/clkrst.sv\n             clkrst\n             clkrst.v\n             clkrst.sv\n             obj_dir/clkrst\n             obj_dir/clkrst.v\n             obj_dir/clkrst.sv\n%Error: data/full_repos/permissive/170067905/hw3_2/fullAdder_1b_bench.v:7: Cannot find file containing module: \'fullAdder_1b\'\n   fullAdder_1b a( \n   ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/170067905/hw3_2/fullAdder_1b_bench.v:30: Operator CASE expects 2 bits on the Case expression, but Case expression\'s VARREF \'S\' generates 1 bits.\n                                                                                  : ... In instance fullAdder_1b_bench\n      case (S)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/170067905/hw3_2/fullAdder_1b_bench.v:39: Operator CASE expects 2 bits on the Case expression, but Case expression\'s VARREF \'C_out\' generates 1 bits.\n                                                                                  : ... In instance fullAdder_1b_bench\n      case (C_out)\n      ^~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fullAdder_1b_bench;
   wire Clk, rst, err;
   reg A, B, C_in;
   wire S, C_out;
   
   clkrst my_clkrst( .clk(Clk), .rst(rst), .err(err));
   fullAdder_1b a(

		  .S			(S),
		  .C_out		(C_out),

		  .A			(A),
		  .B			(B),
		  .C_in			(C_in));

   initial begin
      A = 1'b0;
      B = 1'b0;
      C_in = 1'b0;
      #3200 $finish;
   end
   
   always @(posedge Clk) begin
      C_in <= (C_in ^ (A & B));
      B <= (B ^ A);
      A <= ~A;
     end

   always @(negedge Clk) begin
      case (S)
	2'b0 :
	  if ((A & ~B & ~C_in) || (~A & B & ~C_in) || (~A & ~B & C_in) || (A & B & C_in))
	    $display ("Error: Sum=0");
	2'b1 :
	  if ((A & B & ~C_in) || (~A & B & C_in) || (A & ~B & C_in) || (~A & ~B & ~C_in))
	    $display ("Error: Sum=1");
      endcase

      case (C_out)
	2'b0 :
	  if ((~A & B & C_in) || (A & ~B & C_in) || (A & B & ~C_in) || (A & B & C_in))
	    $display ("Error: C_out=0");
	2'b1 :
	  if ((~A & ~B & ~C_in) || (~A & ~B & C_in) || (~A & B & ~C_in) || (A & ~B & ~C_in))
	    $display ("Error: C_out=1");
      endcase
   end

endmodule
module fullAdder_1b_bench;

   wire Clk, rst, err;
   reg A, B, C_in;
   wire S, C_out;
   
   clkrst my_clkrst( .clk(Clk), .rst(rst), .err(err));
   fullAdder_1b a(

		  .S			(S),
		  .C_out		(C_out),

		  .A			(A),
		  .B			(B),
		  .C_in			(C_in));

   initial begin
      A = 1'b0;
      B = 1'b0;
      C_in = 1'b0;
      #3200 $finish;
   end
   
   always @(posedge Clk) begin
      C_in <= (C_in ^ (A & B));
      B <= (B ^ A);
      A <= ~A;
     end

   always @(negedge Clk) begin
      case (S)
	2'b0 :
	  if ((A & ~B & ~C_in) || (~A & B & ~C_in) || (~A & ~B & C_in) || (A & B & C_in))
	    $display ("Error: Sum=0");
	2'b1 :
	  if ((A & B & ~C_in) || (~A & B & C_in) || (A & ~B & C_in) || (~A & ~B & ~C_in))
	    $display ("Error: Sum=1");
      endcase

      case (C_out)
	2'b0 :
	  if ((~A & B & C_in) || (A & ~B & C_in) || (A & B & ~C_in) || (A & B & C_in))
	    $display ("Error: C_out=0");
	2'b1 :
	  if ((~A & ~B & ~C_in) || (~A & ~B & C_in) || (~A & B & ~C_in) || (A & ~B & ~C_in))
	    $display ("Error: C_out=1");
      endcase
   end

endmodule