data/full_repos/permissive/161004496/control_unit.v
None: at end of input
1: b'%Error: data/full_repos/permissive/161004496/control_unit.v:50: Cannot find file containing module: \'serial\'\n    serial serial_in(clk,reset,rxD,s_in,signal,counter); \n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161004496,data/full_repos/permissive/161004496/serial\n             data/full_repos/permissive/161004496,data/full_repos/permissive/161004496/serial.v\n             data/full_repos/permissive/161004496,data/full_repos/permissive/161004496/serial.sv\n             serial\n             serial.v\n             serial.sv\n             obj_dir/serial\n             obj_dir/serial.v\n             obj_dir/serial.sv\n%Error: data/full_repos/permissive/161004496/control_unit.v:51: Cannot find file containing module: \'multiplication_unit\'\n    multiplication_unit fft_1(pattern, ~s_in, clk, signal, fft_op1);\n    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161004496/control_unit.v:52: Cannot find file containing module: \'multiplication_unit\'\n    multiplication_unit fft_2(~pattern, s_in, clk, signal, fft_op2);\n    ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161004496/control_unit.v:53: Cannot find file containing module: \'ledDisplay\'\n    ledDisplay display(led_display, clk,0, seg, an,nul); \n    ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/161004496/control_unit.v:146: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'d_count\' generates 1 bits.\n                                                                       : ... In instance control_unit\n           led_display = led_display - d_count;     \n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module control_unit(clk,seg,an,reset,rxD,signal,state,counter);
    input clk;
    input reset;
    input rxD;
    output [6:0]seg;
    output [3:0]an;
    output [9:0]counter;

    reg [15:0]led_display;
    
    parameter n = 30;
    
    output reg [2:0]state;
    wire [n:1]s_in;
    output wire signal;
    reg [n:1]pattern;
    wire [2*n:1]fft_op1;
     wire [2*n:1]fft_op2;
     reg [2*n:1]count1;
     reg [2*n:1]count2;

    reg [2*n:1]temp;
    reg [2*n:1]count;
   
    reg d_count;
    
    reg [1:0]fsm;
    
    integer k;
    
    serial serial_in(clk,reset,rxD,s_in,signal,counter);
    multiplication_unit fft_1(pattern, ~s_in, clk, signal, fft_op1);
    multiplication_unit fft_2(~pattern, s_in, clk, signal, fft_op2);
    ledDisplay display(led_display, clk,0, seg, an,nul);

always @(negedge signal, posedge reset)
begin
    if(reset)
    begin
        state <= 3'b000;
    end
    else
    begin
        if((state==3'b000) && (s_in[n:(n-2)] == 3'b100))
            state <= 3'b001;
        else if(state==3'b001)
            state <= 3'b011;
        else if(state==3'b011)
            state <= 3'b111;
        else if(state==3'b111)
            state <= 3'b110;
        else if(state==3'b110 && (s_in[n:(n-2)] == 3'b111))
        begin
            state <= 3'b100;
        end
    end
end

always @(posedge clk)
begin
    if(reset)
    begin
        k = 0;
        temp = 0;
        count = 0;
        count1=0;
        count2=0;
        led_display = 0;
        d_count = 0;
        fsm = 2'b00;
    end
    else
    begin
        if((state==3'b000) && (s_in[n:(n-2)] == 3'b100))
        begin
            led_display = 0;
            d_count = 0;
        end
        else if(state==3'b011)
           fsm = 2'b10;
        else if(state==3'b111)
            fsm = 2'b01;
        else if(state==3'b110 && (s_in[n:(n-2)] != 3'b111))
        begin
            count1 = count2;
            fsm = 2'b11;
        end
    end

    if (signal==1) begin
        k = 0;
    end
    else if(fsm==2'b00)
       fsm <=fsm;
    else if(fsm==2'b01)
    begin
        if(k<(n+2))

            k = k + 1;
        else
        begin
            count2 = fft_op1 | fft_op2;
            fsm = 2'b00;
        end
    end
    else if(fsm==2'b11)
    begin
        if(k<(n+2))

            k = k+1;
        else if(k==n+2)
        begin
            count2 = fft_op1 | fft_op2;
            temp = count2 >> n-1;
            count1 = count1 << 1;
            count = count1 | temp;
            k=k+1;
        end
        else if(k<2*n+4)
        begin
           if(count[k-n-2] == 0)
                    led_display = led_display+1;
           k = k+3;
        end
        else if(k==2*n+6)
        begin
           led_display = led_display - d_count;
            if(count[1]==0)
                d_count = 1;
            else
                d_count = 0;
           k = k+1;
           fsm = 2'b00;
        end
    end
    else if(fsm==2'b10)
    begin

        if(k<n)
        begin
            pattern[n-k] = s_in[k+1];
            k = k+1;
        end
        else
            fsm = 2'b00;
    end

end

endmodule
module control_unit(clk,seg,an,reset,rxD,signal,state,counter);

    input clk;
    input reset;
    input rxD;
    output [6:0]seg;
    output [3:0]an;
    output [9:0]counter;

    reg [15:0]led_display;
    
    parameter n = 30;
    
    output reg [2:0]state;
    wire [n:1]s_in;
    output wire signal;
    reg [n:1]pattern;
    wire [2*n:1]fft_op1;
     wire [2*n:1]fft_op2;
     reg [2*n:1]count1;
     reg [2*n:1]count2;

    reg [2*n:1]temp;
    reg [2*n:1]count;
   
    reg d_count;
    
    reg [1:0]fsm;
    
    integer k;
    
    serial serial_in(clk,reset,rxD,s_in,signal,counter);
    multiplication_unit fft_1(pattern, ~s_in, clk, signal, fft_op1);
    multiplication_unit fft_2(~pattern, s_in, clk, signal, fft_op2);
    ledDisplay display(led_display, clk,0, seg, an,nul);

always @(negedge signal, posedge reset)
begin
    if(reset)
    begin
        state <= 3'b000;
    end
    else
    begin
        if((state==3'b000) && (s_in[n:(n-2)] == 3'b100))
            state <= 3'b001;
        else if(state==3'b001)
            state <= 3'b011;
        else if(state==3'b011)
            state <= 3'b111;
        else if(state==3'b111)
            state <= 3'b110;
        else if(state==3'b110 && (s_in[n:(n-2)] == 3'b111))
        begin
            state <= 3'b100;
        end
    end
end

always @(posedge clk)
begin
    if(reset)
    begin
        k = 0;
        temp = 0;
        count = 0;
        count1=0;
        count2=0;
        led_display = 0;
        d_count = 0;
        fsm = 2'b00;
    end
    else
    begin
        if((state==3'b000) && (s_in[n:(n-2)] == 3'b100))
        begin
            led_display = 0;
            d_count = 0;
        end
        else if(state==3'b011)
           fsm = 2'b10;
        else if(state==3'b111)
            fsm = 2'b01;
        else if(state==3'b110 && (s_in[n:(n-2)] != 3'b111))
        begin
            count1 = count2;
            fsm = 2'b11;
        end
    end

    if (signal==1) begin
        k = 0;
    end
    else if(fsm==2'b00)
       fsm <=fsm;
    else if(fsm==2'b01)
    begin
        if(k<(n+2))

            k = k + 1;
        else
        begin
            count2 = fft_op1 | fft_op2;
            fsm = 2'b00;
        end
    end
    else if(fsm==2'b11)
    begin
        if(k<(n+2))

            k = k+1;
        else if(k==n+2)
        begin
            count2 = fft_op1 | fft_op2;
            temp = count2 >> n-1;
            count1 = count1 << 1;
            count = count1 | temp;
            k=k+1;
        end
        else if(k<2*n+4)
        begin
           if(count[k-n-2] == 0)
                    led_display = led_display+1;
           k = k+3;
        end
        else if(k==2*n+6)
        begin
           led_display = led_display - d_count;
            if(count[1]==0)
                d_count = 1;
            else
                d_count = 0;
           k = k+1;
           fsm = 2'b00;
        end
    end
    else if(fsm==2'b10)
    begin

        if(k<n)
        begin
            pattern[n-k] = s_in[k+1];
            k = k+1;
        end
        else
            fsm = 2'b00;
    end

end

endmodule