data/full_repos/permissive/117179686/src/inst_rom.v
1: b'%Error: data/full_repos/permissive/117179686/src/inst_rom.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117179686/src,data/full_repos/permissive/117179686/defines.v\n             data/full_repos/permissive/117179686/src,data/full_repos/permissive/117179686/defines.v.v\n             data/full_repos/permissive/117179686/src,data/full_repos/permissive/117179686/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/117179686/src/inst_rom.v:6: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/inst_rom.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] addr,\n                        ^\n%Error: data/full_repos/permissive/117179686/src/inst_rom.v:7: Define or directive not defined: \'`InstBus\'\n output reg[`InstBus] inst\n            ^~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/inst_rom.v:11: Define or directive not defined: \'`InstBus\'\n reg[`InstBus]  inst_mem[0:`InstMemNum-1];\n     ^~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/inst_rom.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`InstBus]  inst_mem[0:`InstMemNum-1];\n             ^\n%Error: data/full_repos/permissive/117179686/src/inst_rom.v:11: Define or directive not defined: \'`InstMemNum\'\n reg[`InstBus]  inst_mem[0:`InstMemNum-1];\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/inst_rom.v:23: Define or directive not defined: \'`ChipDisable\'\n  if (ce == `ChipDisable) begin\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/117179686/src/inst_rom.v:24: Define or directive not defined: \'`ZeroWord\'\n   inst <= `ZeroWord;\n           ^~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module inst_rom(

	input wire ce,
	input wire[`InstAddrBus] addr,
	output reg[`InstBus] inst

);

	reg[`InstBus]  inst_mem[0:`InstMemNum-1];


	initial begin
		$readmemh ( "temp.data", inst_mem);


	end
	
	always @ (*) begin
		if (ce == `ChipDisable) begin
			inst <= `ZeroWord;
		end else begin
			inst <= {
				inst_mem[addr[31:2]][7:0],
				inst_mem[addr[31:2]][15:8],
				inst_mem[addr[31:2]][23:16],
				inst_mem[addr[31:2]][31:24]
			};
		end
	end
	
	

endmodule
module inst_rom(

	input wire ce,
	input wire[`InstAddrBus] addr,
	output reg[`InstBus] inst

);


	reg[`InstBus]  inst_mem[0:`InstMemNum-1];


	initial begin
		$readmemh ( "temp.data", inst_mem);


	end
	
	always @ (*) begin
		if (ce == `ChipDisable) begin
			inst <= `ZeroWord;
		end else begin
			inst <= {
				inst_mem[addr[31:2]][7:0],
				inst_mem[addr[31:2]][15:8],
				inst_mem[addr[31:2]][23:16],
				inst_mem[addr[31:2]][31:24]
			};
		end
	end
	
	

endmodule