data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:25: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb,data/full_repos/permissive/214858095/test_exec.svh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb,data/full_repos/permissive/214858095/test_exec.svh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb,data/full_repos/permissive/214858095/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:27: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgAxiStreamBfm::*;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:38: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef AxiStreamPacket #(WIDTH, UWIDTH) AxisPacket_t;\n                          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:39: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef XportStreamPacket #(WIDTH) XportPacket_t;\n                            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:65: syntax error, unexpected \'=\', expecting \',\' or \';\'\n    axis = new(.master(i), .slave(o));\n         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:79: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test("Wait for Reset", 10us);\n                                      ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:81: Unsupported: wait statements\n    wait(!reset);\n    ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:82: syntax error, unexpected \'@\'\n    repeat (10) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:96: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n    automatic raw_pkt_t    raw;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:100: syntax error, unexpected \'{\', expecting STRING\n    test_str = $sformatf({TEST_NAME,"::Remove Bytes L=%3d"},num_samples);\n                         ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:101: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test(test_str, 10us);\n                              ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:142: Unsupported: fork statements\n    fork\n    ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:152: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n          automatic AxisPacket_t  actual_a = new();\n                    ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:154: Unsupported: Ignoring delay on this delayed statement.\n          #(2*WIDTH);  \n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:157: Unsupported: Ignoring delay on this delayed statement.\n          #(2*WIDTH);  \n          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:164: Define or directive not defined: \'`ASSERT_ERROR\'\n            `ASSERT_ERROR(actual_a.data.size() == 0,str);\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:164: syntax error, unexpected \',\'\n            `ASSERT_ERROR(actual_a.data.size() == 0,str);\n                                                   ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:170: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n          automatic AxisPacket_t  actual_a = new();\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:176: syntax error, unexpected \'{\', expecting STRING\n            str = $sformatf({"L= %3d REM =%2d:%1d WORD=%1d:%1d ERROR_LIM=%1d<%1d %1d<=%1d WIDTH=%3d","\\nSEND\\n%s"},\n                            ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:182: Define or directive not defined: \'`ASSERT_ERROR\'\n            `ASSERT_ERROR(!actual.compare_w_error(expected[i],.COMPARE_ERROR_PACKETS(0)),str);\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv:182: syntax error, unexpected \',\'\n            `ASSERT_ERROR(!actual.compare_w_error(expected[i],.COMPARE_ERROR_PACKETS(0)),str);\n                                                                                        ^\n%Error: Exiting due to 19 error(s), 2 warning(s)\n'
module axi4s_remove_bytes_tb #(
  parameter TEST_NAME = "axi_remove_bytes",
  parameter WIDTH     = 32,
  parameter REM_START = 0,
  parameter REM_END   = 7
);

  `include "test_exec.svh"

  import PkgAxiStreamBfm::*;
  import PkgTestExec::*;
  import PkgEthernet::*;





  localparam UWIDTH = $clog2((WIDTH/8)+1);
  localparam MAX_PACKET_BYTES = 16*1024;

  typedef AxiStreamPacket #(WIDTH, UWIDTH) AxisPacket_t;
  typedef XportStreamPacket #(WIDTH) XportPacket_t;





  bit clk;
  bit reset;

  sim_clock_gen #(.PERIOD(5.0), .AUTOSTART(0))
    clk_gen (.clk(clk), .rst(reset));





  AxiStreamIf #(.DATA_WIDTH(WIDTH),.USER_WIDTH(UWIDTH),.TKEEP(0),
                .MAX_PACKET_BYTES(MAX_PACKET_BYTES)) 
    i (clk, reset);
  AxiStreamIf #(.DATA_WIDTH(WIDTH),.USER_WIDTH(UWIDTH),.TKEEP(0),
                .MAX_PACKET_BYTES(MAX_PACKET_BYTES)) 
    o (clk, reset);


  AxiStreamBfm #(.DATA_WIDTH(WIDTH),.USER_WIDTH(UWIDTH),.TKEEP(0),
                 .MAX_PACKET_BYTES(MAX_PACKET_BYTES)) 
    axis = new(.master(i), .slave(o));





  axi4s_remove_bytes #(.REM_START(REM_START),.REM_END(REM_END))
    DUT (.*);





  task test_reset();
    test.start_test("Wait for Reset", 10us);
    clk_gen.reset();
    wait(!reset);
    repeat (10) @(posedge clk);
    test.end_test();
  endtask : test_reset





  task automatic test_samples(int num_samples);
    localparam PKTS_TO_SEND = 10;
    localparam LOW_LIM  = DUT.EXACT?DUT.START_WORD-1:DUT.START_WORD;
    localparam HIGH_LIM = REM_END;

    automatic string       test_str;
    automatic raw_pkt_t    raw;
    automatic XportPacket_t send[$];
    automatic XportPacket_t expected[$];
    automatic integer last_word_index;
    test_str = $sformatf({TEST_NAME,"::Remove Bytes L=%3d"},num_samples);
    test.start_test(test_str, 10us);

    for (int i= 0 ; i < PKTS_TO_SEND; i++) begin

      expected[i] = new;
      send[i] = new;

      get_ramp_raw_pkt(.num_samps(num_samples),.ramp_start((i*num_samples)%256),.ramp_inc(1),.pkt(raw),.SWIDTH(8));
      send[i].push_bytes(raw);

      if (REM_END < 0) begin
        raw = raw[0:REM_START-1];
      end else begin
        for (int i = 0 ; i < REM_END-REM_START+1 ; ++i) begin
          if (raw.size()-1 >= REM_START) begin
            raw.delete(REM_START);
          end
        end
      end
      expected[i].push_bytes(raw);
      send[i].tkeep_to_tuser(.ERROR_PROB(10));
      expected[i].tkeep_to_tuser();
      if (send[i].has_error())
        expected[i].set_error();




      last_word_index = send[i].data.size()-1;
      if (last_word_index > LOW_LIM &&
        num_samples-1 <= HIGH_LIM) begin
        if (!DUT.TRUNCATE)
          if (DUT.START_WORD != DUT.END_WORD || DUT.EXACT)
            expected[i].set_error();
      end
    end

    for (int i=  PKTS_TO_SEND-1 ; i >= 0; i--) begin
      if (expected[i].data.size() == 0) expected.delete(i);
    end

    fork
      begin : send_thread
        foreach(send[i])begin
          axis.put(send[i]);
        end
      end
      begin : expected_thread

        if (expected.size() == 0) begin : no_expected
          automatic string str;
          automatic AxisPacket_t  actual_a = new();

          #(2*WIDTH);
          o.tready = 1;
          axis.wait_send();
          #(2*WIDTH);
            str = $sformatf("UNEXPECTED_PACKET L=%3d\nREM_START=%3d:%1d REM_END=%3d:%1d SIZE =%3d WIDTH=%3d\nSEND\n%s",
                            num_samples,REM_START,DUT.START_WORD,REM_END,DUT.END_WORD,send[0].data.size(),WIDTH,
                            send[0].sprint());
          if (axis.try_get(actual_a)) begin
            $display("ACTUAL");
            actual_a.print();
            `ASSERT_ERROR(actual_a.data.size() == 0,str);
          end
          $display("Wait completed");

        end else begin : get_expected
          automatic string str;
          automatic AxisPacket_t  actual_a = new();
          automatic XportPacket_t actual   = new();
          foreach(expected[i]) begin
            axis.get(actual_a);
            actual.import_axis(actual_a);
            actual.tuser_to_tkeep();
            str = $sformatf({"L= %3d REM =%2d:%1d WORD=%1d:%1d ERROR_LIM=%1d<%1d %1d<=%1d WIDTH=%3d","\nSEND\n%s"},
                            num_samples,
                            REM_START,REM_END,
                            DUT.START_WORD,DUT.END_WORD,
                            LOW_LIM,last_word_index,num_samples-1,HIGH_LIM,WIDTH,
                            send[i].sprint());
            `ASSERT_ERROR(!actual.compare_w_error(expected[i],.COMPARE_ERROR_PACKETS(0)),str);
          end
        end
      end
    join
    test.end_test();

  endtask : test_samples





  initial begin : tb_main
    automatic integer min_length;

    test.start_tb(TEST_NAME);
    clk_gen.start();

    if (REM_END == -1)
      min_length = REM_START-4;
    else
      min_length = REM_END-4;

    if ( min_length < 1) min_length = 1;

    axis.run();

    test_reset();

    for (int i=0 ; i < 6 ; ++i) begin
      test_samples(2**i);
    end

    for (int i=1 ; i < (WIDTH/8)*3 ; ++i) begin
      test_samples(min_length+i);
    end


    axis.set_slave_stall_prob(0);
    axis.set_master_stall_prob(0);

    for (int i=1 ; i < (WIDTH/8)*3 ; ++i) begin
      test_samples(min_length+i);
    end



    test.end_tb(0);


    clk_gen.kill();

  end

endmodule
module axi4s_remove_bytes_tb #(
  parameter TEST_NAME = "axi_remove_bytes",
  parameter WIDTH     = 32,
  parameter REM_START = 0,
  parameter REM_END   = 7
);


  `include "test_exec.svh"

  import PkgAxiStreamBfm::*;
  import PkgTestExec::*;
  import PkgEthernet::*;





  localparam UWIDTH = $clog2((WIDTH/8)+1);
  localparam MAX_PACKET_BYTES = 16*1024;

  typedef AxiStreamPacket #(WIDTH, UWIDTH) AxisPacket_t;
  typedef XportStreamPacket #(WIDTH) XportPacket_t;





  bit clk;
  bit reset;

  sim_clock_gen #(.PERIOD(5.0), .AUTOSTART(0))
    clk_gen (.clk(clk), .rst(reset));





  AxiStreamIf #(.DATA_WIDTH(WIDTH),.USER_WIDTH(UWIDTH),.TKEEP(0),
                .MAX_PACKET_BYTES(MAX_PACKET_BYTES)) 
    i (clk, reset);
  AxiStreamIf #(.DATA_WIDTH(WIDTH),.USER_WIDTH(UWIDTH),.TKEEP(0),
                .MAX_PACKET_BYTES(MAX_PACKET_BYTES)) 
    o (clk, reset);


  AxiStreamBfm #(.DATA_WIDTH(WIDTH),.USER_WIDTH(UWIDTH),.TKEEP(0),
                 .MAX_PACKET_BYTES(MAX_PACKET_BYTES)) 
    axis = new(.master(i), .slave(o));





  axi4s_remove_bytes #(.REM_START(REM_START),.REM_END(REM_END))
    DUT (.*);





  task test_reset();
    test.start_test("Wait for Reset", 10us);
    clk_gen.reset();
    wait(!reset);
    repeat (10) @(posedge clk);
    test.end_test();
  endtask : test_reset





  task automatic test_samples(int num_samples);
    localparam PKTS_TO_SEND = 10;
    localparam LOW_LIM  = DUT.EXACT?DUT.START_WORD-1:DUT.START_WORD;
    localparam HIGH_LIM = REM_END;

    automatic string       test_str;
    automatic raw_pkt_t    raw;
    automatic XportPacket_t send[$];
    automatic XportPacket_t expected[$];
    automatic integer last_word_index;
    test_str = $sformatf({TEST_NAME,"::Remove Bytes L=%3d"},num_samples);
    test.start_test(test_str, 10us);

    for (int i= 0 ; i < PKTS_TO_SEND; i++) begin

      expected[i] = new;
      send[i] = new;

      get_ramp_raw_pkt(.num_samps(num_samples),.ramp_start((i*num_samples)%256),.ramp_inc(1),.pkt(raw),.SWIDTH(8));
      send[i].push_bytes(raw);

      if (REM_END < 0) begin
        raw = raw[0:REM_START-1];
      end else begin
        for (int i = 0 ; i < REM_END-REM_START+1 ; ++i) begin
          if (raw.size()-1 >= REM_START) begin
            raw.delete(REM_START);
          end
        end
      end
      expected[i].push_bytes(raw);
      send[i].tkeep_to_tuser(.ERROR_PROB(10));
      expected[i].tkeep_to_tuser();
      if (send[i].has_error())
        expected[i].set_error();




      last_word_index = send[i].data.size()-1;
      if (last_word_index > LOW_LIM &&
        num_samples-1 <= HIGH_LIM) begin
        if (!DUT.TRUNCATE)
          if (DUT.START_WORD != DUT.END_WORD || DUT.EXACT)
            expected[i].set_error();
      end
    end

    for (int i=  PKTS_TO_SEND-1 ; i >= 0; i--) begin
      if (expected[i].data.size() == 0) expected.delete(i);
    end

    fork
      begin : send_thread
        foreach(send[i])begin
          axis.put(send[i]);
        end
      end
      begin : expected_thread

        if (expected.size() == 0) begin : no_expected
          automatic string str;
          automatic AxisPacket_t  actual_a = new();

          #(2*WIDTH);
          o.tready = 1;
          axis.wait_send();
          #(2*WIDTH);
            str = $sformatf("UNEXPECTED_PACKET L=%3d\nREM_START=%3d:%1d REM_END=%3d:%1d SIZE =%3d WIDTH=%3d\nSEND\n%s",
                            num_samples,REM_START,DUT.START_WORD,REM_END,DUT.END_WORD,send[0].data.size(),WIDTH,
                            send[0].sprint());
          if (axis.try_get(actual_a)) begin
            $display("ACTUAL");
            actual_a.print();
            `ASSERT_ERROR(actual_a.data.size() == 0,str);
          end
          $display("Wait completed");

        end else begin : get_expected
          automatic string str;
          automatic AxisPacket_t  actual_a = new();
          automatic XportPacket_t actual   = new();
          foreach(expected[i]) begin
            axis.get(actual_a);
            actual.import_axis(actual_a);
            actual.tuser_to_tkeep();
            str = $sformatf({"L= %3d REM =%2d:%1d WORD=%1d:%1d ERROR_LIM=%1d<%1d %1d<=%1d WIDTH=%3d","\nSEND\n%s"},
                            num_samples,
                            REM_START,REM_END,
                            DUT.START_WORD,DUT.END_WORD,
                            LOW_LIM,last_word_index,num_samples-1,HIGH_LIM,WIDTH,
                            send[i].sprint());
            `ASSERT_ERROR(!actual.compare_w_error(expected[i],.COMPARE_ERROR_PACKETS(0)),str);
          end
        end
      end
    join
    test.end_test();

  endtask : test_samples





  initial begin : tb_main
    automatic integer min_length;

    test.start_tb(TEST_NAME);
    clk_gen.start();

    if (REM_END == -1)
      min_length = REM_START-4;
    else
      min_length = REM_END-4;

    if ( min_length < 1) min_length = 1;

    axis.run();

    test_reset();

    for (int i=0 ; i < 6 ; ++i) begin
      test_samples(2**i);
    end

    for (int i=1 ; i < (WIDTH/8)*3 ; ++i) begin
      test_samples(min_length+i);
    end


    axis.set_slave_stall_prob(0);
    axis.set_master_stall_prob(0);

    for (int i=1 ; i < (WIDTH/8)*3 ; ++i) begin
      test_samples(min_length+i);
    end



    test.end_tb(0);


    clk_gen.kill();

  end

endmodule