data/full_repos/permissive/149848590/src/cpu/core/stage/if/IFID.v
1: b'%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/if/IFID.v:3: Cannot find include file: ../../define/bus.v\n`include "../../define/bus.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/149848590/src/cpu/core/stage/if,data/full_repos/permissive/149848590/../../define/bus.v\n             data/full_repos/permissive/149848590/src/cpu/core/stage/if,data/full_repos/permissive/149848590/../../define/bus.v.v\n             data/full_repos/permissive/149848590/src/cpu/core/stage/if,data/full_repos/permissive/149848590/../../define/bus.v.sv\n             ../../define/bus.v\n             ../../define/bus.v.v\n             ../../define/bus.v.sv\n             obj_dir/../../define/bus.v\n             obj_dir/../../define/bus.v.v\n             obj_dir/../../define/bus.v.sv\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/if/IFID.v:11: Define or directive not defined: \'`ADDR_BUS\'\n    input [`ADDR_BUS] addr_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/if/IFID.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`ADDR_BUS] addr_in,\n                    ^\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/if/IFID.v:12: Define or directive not defined: \'`INST_BUS\'\n    input [`INST_BUS] inst_in,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/if/IFID.v:13: Define or directive not defined: \'`ADDR_BUS\'\n    output [`ADDR_BUS] addr_out,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/if/IFID.v:14: Define or directive not defined: \'`INST_BUS\'\n    output [`INST_BUS] inst_out\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/if/IFID.v:17: Define or directive not defined: \'`ADDR_BUS_WIDTH\'\n    PipelineDeliver #(`ADDR_BUS_WIDTH) ff_addr(\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/149848590/src/cpu/core/stage/if/IFID.v:23: Define or directive not defined: \'`INST_BUS_WIDTH\'\n    PipelineDeliver #(`INST_BUS_WIDTH) ff_inst(\n                      ^~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module IFID(
    input clk,
    input rst,
    input flush,
    input stall_current_stage,
    input stall_next_stage,
    input [`ADDR_BUS] addr_in,
    input [`INST_BUS] inst_in,
    output [`ADDR_BUS] addr_out,
    output [`INST_BUS] inst_out
);

    PipelineDeliver #(`ADDR_BUS_WIDTH) ff_addr(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        addr_in, addr_out
    );

    PipelineDeliver #(`INST_BUS_WIDTH) ff_inst(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        inst_in, inst_out
    );

endmodule
module IFID(
    input clk,
    input rst,
    input flush,
    input stall_current_stage,
    input stall_next_stage,
    input [`ADDR_BUS] addr_in,
    input [`INST_BUS] inst_in,
    output [`ADDR_BUS] addr_out,
    output [`INST_BUS] inst_out
);


    PipelineDeliver #(`ADDR_BUS_WIDTH) ff_addr(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        addr_in, addr_out
    );

    PipelineDeliver #(`INST_BUS_WIDTH) ff_inst(
        clk, rst, flush,
        stall_current_stage, stall_next_stage,
        inst_in, inst_out
    );

endmodule