data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v
 line:20: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:11: Unsupported: Ignoring delay on this delayed statement.\n #00 clock = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:12: Unsupported: Ignoring delay on this delayed statement.\n forever #20 clock = ~clock;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:17: Unsupported: Ignoring delay on this delayed statement.\n #00 ud = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:18: Unsupported: Ignoring delay on this delayed statement.\n #1250 ud = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:19: Unsupported: Ignoring delay on this delayed statement.\n #1250 ud = 1\'b0;\n ^\n%Error: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:21: syntax error, unexpected end, expecting \';\'\nend\n^~~\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:20: Unsupported: Ignoring delay on this delayed statement.\n #1250 $stop\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:26: Unsupported: Ignoring delay on this delayed statement.\n #30 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:27: Unsupported: Ignoring delay on this delayed statement.\n #2000 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:28: Unsupported: Ignoring delay on this delayed statement.\n #30 reset = 1\'b1;\n ^\n%Error: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:33: Unsupported or unknown PLI call: $monitor\n $monitor("time=%3d, high=%4b, low=%4b, ud=%b, clock=%b, reset=%b", $time, high, low, ud, clock, reset);\n ^~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:38: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("bcd_ud_counter_8bit.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:39: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:51: Value too large for 1 bit number: 5\nparameter limit_msb = 1\'d5;\n                      ^~~~\n%Error: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:53: syntax error, unexpected negedge, expecting TYPE-IDENTIFIER\nalways@*(negedge clock, ~reset)\n         ^~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module bcd_ud_counter_8bit(high, low, ud, clock, reset);

output reg [3:0] high, low;

input wire ud, clock ,reset;

parameter limit_msb = 1'd5;

always@*(negedge clock, ~reset)
begin
	if(!reset)
	begin
		if(ud)
		begin
			if(high==limit_msb && low==4'b1001)
			begin
				low = 4'b0000;
				high = 4'b0000;
			end
			else if (high != limit_msb && low==4'b1001)
			begin
				low = 4'b0000;
				high = high + 4'b0001;
			end
			else if(high==limit_msb && low!=4'b1001)
			begin
				low = low+4'b0001;
			end
			else 
			begin
				low = low+4'b0001;	
			end
		end
		else 
		begin
			if(high==4'b0000 && low==4'b0000)
			begin
				low = 4'b1001;
				high = limit_msb;
			end
			else if (high != 4'b0000 && low==4'b0000)
			begin
				low = 4'b1001;
				high = high - 4'b0001;
			end
			else if(high==4'b0000 && low!=4'b0000)
			begin
				low = low-4'b0001;
			end
			else 
			begin
				low = low-4'b0001;	
			end
		end
	end
	else 
	begin
		high = 4'b0000;
		low = 4'b0000;	
	end
end
endmodule
module bcd_ud_counter_8bit(high, low, ud, clock, reset);


output reg [3:0] high, low;

input wire ud, clock ,reset;

parameter limit_msb = 1'd5;

always@*(negedge clock, ~reset)
begin
	if(!reset)
	begin
		if(ud)
		begin
			if(high==limit_msb && low==4'b1001)
			begin
				low = 4'b0000;
				high = 4'b0000;
			end
			else if (high != limit_msb && low==4'b1001)
			begin
				low = 4'b0000;
				high = high + 4'b0001;
			end
			else if(high==limit_msb && low!=4'b1001)
			begin
				low = low+4'b0001;
			end
			else 
			begin
				low = low+4'b0001;	
			end
		end
		else 
		begin
			if(high==4'b0000 && low==4'b0000)
			begin
				low = 4'b1001;
				high = limit_msb;
			end
			else if (high != 4'b0000 && low==4'b0000)
			begin
				low = 4'b1001;
				high = high - 4'b0001;
			end
			else if(high==4'b0000 && low!=4'b0000)
			begin
				low = low-4'b0001;
			end
			else 
			begin
				low = low-4'b0001;	
			end
		end
	end
	else 
	begin
		high = 4'b0000;
		low = 4'b0000;	
	end
end
endmodule