data/full_repos/permissive/132304455/src/amp_control.v
1: b'%Error: data/full_repos/permissive/132304455/src/amp_control.v:14: Cannot find file containing module: \'clock_divider\'\n    clock_divider #(.rate(5)) div5M(micro_clk, clk);\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132304455/src,data/full_repos/permissive/132304455/clock_divider\n             data/full_repos/permissive/132304455/src,data/full_repos/permissive/132304455/clock_divider.v\n             data/full_repos/permissive/132304455/src,data/full_repos/permissive/132304455/clock_divider.sv\n             clock_divider\n             clock_divider.v\n             clock_divider.sv\n             obj_dir/clock_divider\n             obj_dir/clock_divider.v\n             obj_dir/clock_divider.sv\n%Warning-WIDTH: data/full_repos/permissive/132304455/src/amp_control.v:22: Operator GTE expects 14 bits on the RHS, but RHS\'s VARREF \'sound\' generates 13 bits.\n                                                                         : ... In instance amp_control\n        if(counter >= sound)\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module amp_control(audio,
                   gain,
                   not_shutdown,
                   sound,
                   play,
                   reset,
                   clk);
    output reg    audio;
    output        gain, not_shutdown;
    input  [12:0] sound;
    input         play, reset, clk;

    wire micro_clk;
    clock_divider #(.rate(5)) div5M(micro_clk, clk);

    assign gain = 1'b1;
    assign not_shutdown = play;

    reg [13:0] counter = 1;
    always@(posedge micro_clk)
    begin
        if(counter >= sound)
        begin
            counter <= 1;
            audio <= (~audio & play);
        end
        else
        begin
            counter <= counter + 1;
        end
    end

endmodule
module amp_control(audio,
                   gain,
                   not_shutdown,
                   sound,
                   play,
                   reset,
                   clk);

    output reg    audio;
    output        gain, not_shutdown;
    input  [12:0] sound;
    input         play, reset, clk;

    wire micro_clk;
    clock_divider #(.rate(5)) div5M(micro_clk, clk);

    assign gain = 1'b1;
    assign not_shutdown = play;

    reg [13:0] counter = 1;
    always@(posedge micro_clk)
    begin
        if(counter >= sound)
        begin
            counter <= 1;
            audio <= (~audio & play);
        end
        else
        begin
            counter <= counter + 1;
        end
    end

endmodule