data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/axi_repeat.v
data/verilator_xmls/b9b4ea6a-ba12-44d6-b507-139270932990.xml
module axi_repeat
#(
  parameter WIDTH = 16) 
(
  input clk, input reset,
  input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
  output reg [WIDTH-1:0] o_tdata, output reg o_tlast, output reg o_tvalid, input o_tready
);

  assign i_tready = 1'b1;

  always @(posedge clk) begin
    if (reset) begin
      o_tdata  <= 'd0;
      o_tlast  <= 'd0;
      o_tvalid <= 'd0;
    end else begin
      if (i_tvalid) begin
        o_tvalid <= 1'b1;
        o_tlast  <= i_tlast;
        o_tdata  <= o_tdata;
      end
    end
  end

endmodule
module axi_repeat
#(
  parameter WIDTH = 16) 
(
  input clk, input reset,
  input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
  output reg [WIDTH-1:0] o_tdata, output reg o_tlast, output reg o_tvalid, input o_tready
);


  assign i_tready = 1'b1;

  always @(posedge clk) begin
    if (reset) begin
      o_tdata  <= 'd0;
      o_tlast  <= 'd0;
      o_tvalid <= 'd0;
    end else begin
      if (i_tvalid) begin
        o_tvalid <= 1'b1;
        o_tlast  <= i_tlast;
        o_tdata  <= o_tdata;
      end
    end
  end

endmodule