data/full_repos/permissive/158845296/register_file.v
data/verilator_xmls/b33602b8-c5d2-4a2e-bee6-c73333187660.xml
module register_file
(
    input  clock,
    input  reset,
    input  reg_write,
    input  [4:0] reg_to_write,
    input  [31:0] write_data,
    input  [4:0]  reg_to_read_1, reg_to_read_2,
    output [31:0] read_data_1, read_data_2
);


    reg [31:0] registers [1:31];


    integer i;
    initial begin
        for (i = 1; i < 32; i = i + 1) begin
            registers[i] <= 0;
        end
    end


    always @(posedge clock) begin
        if (reset) begin
            for (i = 1; i < 32; i = i + 1) begin
                registers[i] <= 0;
            end
        end
        else begin
            if (reg_to_write != 0)
                registers[reg_to_write] <= (reg_write) ? write_data : registers[reg_to_write];
        end
    end


    assign read_data_1 = (reg_to_read_1 == 0) ? 32'h00000000 : registers[reg_to_read_1];
    assign read_data_2 = (reg_to_read_2 == 0) ? 32'h00000000 : registers[reg_to_read_2];

endmodule
module register_file
(
    input  clock,
    input  reset,
    input  reg_write,
    input  [4:0] reg_to_write,
    input  [31:0] write_data,
    input  [4:0]  reg_to_read_1, reg_to_read_2,
    output [31:0] read_data_1, read_data_2
);



    reg [31:0] registers [1:31];


    integer i;
    initial begin
        for (i = 1; i < 32; i = i + 1) begin
            registers[i] <= 0;
        end
    end


    always @(posedge clock) begin
        if (reset) begin
            for (i = 1; i < 32; i = i + 1) begin
                registers[i] <= 0;
            end
        end
        else begin
            if (reg_to_write != 0)
                registers[reg_to_write] <= (reg_write) ? write_data : registers[reg_to_write];
        end
    end


    assign read_data_1 = (reg_to_read_1 == 0) ? 32'h00000000 : registers[reg_to_read_1];
    assign read_data_2 = (reg_to_read_2 == 0) ? 32'h00000000 : registers[reg_to_read_2];

endmodule