data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/neek/rtl/verilog/clkgen.v
None: at end of input
1: b'%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/neek/rtl/verilog/clkgen.v:35: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/neek/rtl/verilog,data/full_repos/permissive/19905110/timescale.v\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/neek/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.v\n             data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/neek/rtl/verilog,data/full_repos/permissive/19905110/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/19905110/fusesoc/orpsoc-cores/systems/neek/rtl/verilog/clkgen.v:36: Cannot find include file: orpsoc-defines.v\n`include "orpsoc-defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module clkgen
(

	input	sys_clk_pad_i,

	input	rst_n_pad_i,

	input	ddr_init_done,

	output	async_rst_o,


	output	wb_clk_o,
	output	wb_rst_o,
	output	ddr_rst_o,
	output	pixel_clock,
	output	pixel_clock_x3
);


wire	async_rst;
wire	async_rst_n;

assign	async_rst_n  = rst_n_pad_i;
assign	async_rst  = ~async_rst_n;


assign	async_rst_o = ~async_rst_n;






wire	sync_rst_n;

wire	pll_lock;

pll pll0 (
	.areset	(async_rst),
	.inclk0	(sys_clk_pad_i),
	.c0	(wb_clk_o),
	.c1	(pixel_clock),
	.c2	(pixel_clock_x3),
	.locked	(pll_lock)
);

assign sync_rst_n = pll_lock;







reg [15:0]	wb_rst_shr;

always @(posedge wb_clk_o or posedge async_rst)
	if (async_rst)
		wb_rst_shr <= 16'hffff;
	else if (!ddr_init_done)
		wb_rst_shr <= 16'hffff;
	else
		wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};

assign wb_rst_o = wb_rst_shr[15];


reg [15:0]	ddr_rst_shr;

always @(posedge wb_clk_o or posedge async_rst)
	if (async_rst)
		ddr_rst_shr <= 16'hffff;
	else
		ddr_rst_shr <= {ddr_rst_shr[14:0], ~(sync_rst_n)};

assign ddr_rst_o = ddr_rst_shr[15];

endmodule
module clkgen
(

	input	sys_clk_pad_i,

	input	rst_n_pad_i,

	input	ddr_init_done,

	output	async_rst_o,


	output	wb_clk_o,
	output	wb_rst_o,
	output	ddr_rst_o,
	output	pixel_clock,
	output	pixel_clock_x3
);



wire	async_rst;
wire	async_rst_n;

assign	async_rst_n  = rst_n_pad_i;
assign	async_rst  = ~async_rst_n;


assign	async_rst_o = ~async_rst_n;






wire	sync_rst_n;

wire	pll_lock;

pll pll0 (
	.areset	(async_rst),
	.inclk0	(sys_clk_pad_i),
	.c0	(wb_clk_o),
	.c1	(pixel_clock),
	.c2	(pixel_clock_x3),
	.locked	(pll_lock)
);

assign sync_rst_n = pll_lock;







reg [15:0]	wb_rst_shr;

always @(posedge wb_clk_o or posedge async_rst)
	if (async_rst)
		wb_rst_shr <= 16'hffff;
	else if (!ddr_init_done)
		wb_rst_shr <= 16'hffff;
	else
		wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};

assign wb_rst_o = wb_rst_shr[15];


reg [15:0]	ddr_rst_shr;

always @(posedge wb_clk_o or posedge async_rst)
	if (async_rst)
		ddr_rst_shr <= 16'hffff;
	else
		ddr_rst_shr <= {ddr_rst_shr[14:0], ~(sync_rst_n)};

assign ddr_rst_o = ddr_rst_shr[15];

endmodule