data/full_repos/permissive/128117771/Automaton-VGA-80bit/top_tb.v
 line:17: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/128117771/Automaton-VGA-80bit/top_tb.v:6: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/128117771/Automaton-VGA-80bit/top_tb.v:14: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("top_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/128117771/Automaton-VGA-80bit/top_tb.v:15: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, top_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128117771/Automaton-VGA-80bit/top_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  # 85 $display("FIN de la simulacion");\n  ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb();


	reg clk = 0;

	always #1 clk = ~clk;

	top #( .N(1) ) uut ( .clk(clk)	);


	initial begin


		$dumpfile("top_tb.vcd");
		$dumpvars(0, top_tb);

		# 85 $display("FIN de la simulacion");
		$finish;

	end

endmodule
module top_tb();



	reg clk = 0;

	always #1 clk = ~clk;

	top #( .N(1) ) uut ( .clk(clk)	);


	initial begin


		$dumpfile("top_tb.vcd");
		$dumpvars(0, top_tb);

		# 85 $display("FIN de la simulacion");
		$finish;

	end

endmodule