data/full_repos/permissive/143278/blif/blif02h.v
data/verilator_xmls/cb8a65cd-f5ce-4dec-8c00-e9579f23901b.xml
module test_mux
   (input wire [1:0] D0, D1,
    input wire [1:0] S,
    output reg [1:0] Q);

   always @(*) begin
      case (S)
	2'b00: Q = D0;
	2'b01: Q = D1;
	default: Q = 0;
      endcase
   end

endmodule
module test_mux
   (input wire [1:0] D0, D1,
    input wire [1:0] S,
    output reg [1:0] Q);


   always @(*) begin
      case (S)
	2'b00: Q = D0;
	2'b01: Q = D1;
	default: Q = 0;
      endcase
   end

endmodule