data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v
None: at end of input
1: b'%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:20: Cannot find include file: RV2T_common.vh\n`include "RV2T_common.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source,data/full_repos/permissive/158824477/RV2T_common.vh\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source,data/full_repos/permissive/158824477/RV2T_common.vh.v\n             data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source,data/full_repos/permissive/158824477/RV2T_common.vh.sv\n             RV2T_common.vh\n             RV2T_common.vh.v\n             RV2T_common.vh.sv\n             obj_dir/RV2T_common.vh\n             obj_dir/RV2T_common.vh.v\n             obj_dir/RV2T_common.vh.sv\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:42: Define or directive not defined: \'`XLEN\'\n        input wire [`XLEN - 1 : 0]                              IR_in,\n                    ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:43: Define or directive not defined: \'`PC_BITWIDTH\'\n        input wire [`PC_BITWIDTH - 1 : 0]                       PC_in,\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:48: Define or directive not defined: \'`REG_ADDR_BITS\'\n        output wire [`REG_ADDR_BITS - 1 : 0]                    rs1,\n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:49: Define or directive not defined: \'`REG_ADDR_BITS\'\n        output wire [`REG_ADDR_BITS - 1 : 0]                    rs2,\n                     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:54: Define or directive not defined: \'`CSR_BITS\'\n        output  wire [`CSR_BITS - 1 : 0]                        csr,\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:61: Define or directive not defined: \'`XLEN\'\n        output reg [`XLEN - 1 : 2]                              IR_out,\n                    ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:62: Define or directive not defined: \'`PC_BITWIDTH\'\n        output reg [`PC_BITWIDTH - 1 : 0]                       PC_out,\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:91: Define or directive not defined: \'`REG_ADDR_BITS\'\n        wire    [`REG_ADDR_BITS - 1 : 0]                        rs1_32;\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:92: Define or directive not defined: \'`REG_ADDR_BITS\'\n        wire    [`REG_ADDR_BITS - 1 : 0]                        rs2_32;\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:94: Define or directive not defined: \'`REG_ADDR_BITS\'\n        wire    [`REG_ADDR_BITS - 1 : 0]                        rd;\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:144: Define or directive not defined: \'`XLEN\'\n                    IR_out <= IR_in[`XLEN - 1 : 2];\n                                    ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:185: Define or directive not defined: \'`CMD_OP_IMM\'\n                    `CMD_OP_IMM : begin\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:185: syntax error, unexpected \':\', expecting endcase\n                    `CMD_OP_IMM : begin\n                                ^\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:192: Define or directive not defined: \'`CMD_OP\'\n                    `CMD_OP : begin\n                    ^~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:192: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                    `CMD_OP : begin\n                              ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:200: Define or directive not defined: \'`CMD_LUI\'\n                    `CMD_LUI : begin\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:200: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                    `CMD_LUI : begin\n                               ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:205: Define or directive not defined: \'`CMD_AUIPC\'\n                    `CMD_AUIPC : begin\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:205: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                    `CMD_AUIPC : begin\n                                 ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:210: Define or directive not defined: \'`CMD_JAL\'\n                    `CMD_JAL : begin\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:210: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                    `CMD_JAL : begin\n                               ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:215: Define or directive not defined: \'`CMD_JALR\'\n                    `CMD_JALR : begin\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:215: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                    `CMD_JALR : begin\n                                ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:221: Define or directive not defined: \'`CMD_BRANCH\'\n                    `CMD_BRANCH : begin\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:221: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                    `CMD_BRANCH : begin\n                                  ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:227: Define or directive not defined: \'`CMD_LOAD\'\n                    `CMD_LOAD : begin\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:227: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                    `CMD_LOAD : begin\n                                ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:233: Define or directive not defined: \'`CMD_STORE\'\n                    `CMD_STORE : begin\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:233: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                    `CMD_STORE : begin\n                                 ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:239: Define or directive not defined: \'`CMD_SYSTEM\'\n                    `CMD_SYSTEM : begin\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:239: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                    `CMD_SYSTEM : begin\n                                  ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:258: Define or directive not defined: \'`CMD_MISC_MEM\'\n                    `CMD_MISC_MEM : begin\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:258: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                    `CMD_MISC_MEM : begin\n                                    ^~~~~\n%Error: data/full_repos/permissive/158824477/submodules/PulseRain_MCU/PulseRain_processor_core/source/RV2T_instruction_decode.v:264: syntax error, unexpected \':\', expecting clocking\n                    default : begin\n                            ^\n%Error: Cannot continue\n'
module RV2T_instruction_decode (




        input wire                                              clk,                          
        input wire                                              reset_n,                      
        input wire                                              sync_reset,
   



        input wire                                              decode_enable,
        



        input wire                                              enable_in,
        input wire [`XLEN - 1 : 0]                              IR_in,
        input wire [`PC_BITWIDTH - 1 : 0]                       PC_in,




        output wire [`REG_ADDR_BITS - 1 : 0]                    rs1,
        output wire [`REG_ADDR_BITS - 1 : 0]                    rs2,
     



        output  wire [`CSR_BITS - 1 : 0]                        csr,
        output  reg                                             csr_read_enable,
         




        output reg [`XLEN - 1 : 2]                              IR_out,
        output reg [`PC_BITWIDTH - 1 : 0]                       PC_out,
        
        output reg                                              ctl_load_X_from_rs1,
        output reg                                              ctl_load_Y_from_rs2,
        output reg                                              ctl_load_Y_from_imm_12,
        output reg                                              ctl_load_Y_from_store_offset_12,
        output reg                                              ctl_save_to_rd,
        output reg                                              ctl_ALU_FUNCT3,
        output reg                                              ctl_MUL_DIV_FUNCT3,
        output reg                                              ctl_LUI,
        output reg                                              ctl_AUIPC,
        output reg                                              ctl_JAL,
        output reg                                              ctl_JALR,
        output reg                                              ctl_BRANCH,
        output reg                                              ctl_LOAD,
        output reg                                              ctl_STORE,
        output reg                                              ctl_SYSTEM,
        output reg                                              ctl_CSR,
        output reg                                              ctl_CSR_write,
        output reg                                              ctl_MISC_MEM,
        output reg                                              ctl_MRET,
        output reg                                              ctl_WFI,

        output reg                                              exception_illegal_instruction
);
    



        wire    [`REG_ADDR_BITS - 1 : 0]                        rs1_32;
        wire    [`REG_ADDR_BITS - 1 : 0]                        rs2_32;
        
        wire    [`REG_ADDR_BITS - 1 : 0]                        rd;
        wire    [2 : 0]                                         funct3;
        wire    [11 : 0]                                        funct12;
        reg                                                     illegal;
        



    



            
            assign rs1_32 = IR_in [19 : 15];
            assign rs2_32 = IR_in [24 : 20];

            assign rd = IR_in [11 : 7];
            
            assign rs1 = rs1_32;
            assign rs2 = rs2_32;





            assign funct3  = IR_in [14 : 12];
            assign funct12 = IR_in [31 : 20];





            assign csr     = IR_in [31 : 20];

            always @(*) begin : csr_read_enable_proc
                csr_read_enable = ctl_CSR;
            end
            
            



            
            
            always @(posedge clk, negedge reset_n) begin
                if (!reset_n) begin
                    IR_out <= 0;
                    PC_out <= 0;
                    illegal <= 0;
                end else begin
                    IR_out <= IR_in[`XLEN - 1 : 2];
                    PC_out <= PC_in;

                    if (|IR_in == 1'b0 || &IR_in == 1'b1)
                        illegal <= 1'b1;
                    else
                        illegal <= 1'b0;
                end
            end
            




            always @(*) begin : decode_proc
                ctl_load_X_from_rs1 = 0;
                ctl_load_Y_from_rs2 = 0;
                ctl_load_Y_from_imm_12 = 0;
                
                ctl_save_to_rd = 0;
                
                ctl_ALU_FUNCT3 = 0;
                ctl_MUL_DIV_FUNCT3 = 0;
                ctl_LUI = 0;
                ctl_AUIPC = 0;
                
                ctl_JAL = 0;
                ctl_JALR = 0;
                
                ctl_BRANCH = 0;
                ctl_LOAD = 0;
                ctl_STORE = 0;
                ctl_SYSTEM = 0;
                ctl_CSR = 0;
                ctl_CSR_write = 0;
                ctl_MISC_MEM = 0;
                ctl_MRET = 0;
                ctl_WFI = 0;
                exception_illegal_instruction = illegal;

                case (IR_out [6 : 2])
                    `CMD_OP_IMM : begin
                        ctl_load_X_from_rs1 = 1'b1;
                        ctl_load_Y_from_imm_12 = 1'b1;
                        ctl_save_to_rd = 1'b1;
                        ctl_ALU_FUNCT3 = 1'b1;
                    end
                        
                    `CMD_OP : begin
                        ctl_load_X_from_rs1 = 1'b1;
                        ctl_load_Y_from_rs2 = 1'b1;
                        ctl_save_to_rd = 1'b1;
                        ctl_ALU_FUNCT3 = ~IR_out[25];
                        ctl_MUL_DIV_FUNCT3 = IR_out[25];
                    end
                        
                    `CMD_LUI : begin
                        ctl_LUI = 1'b1;
                        ctl_save_to_rd = 1'b1;
                    end
                        
                    `CMD_AUIPC : begin
                        ctl_AUIPC = 1'b1;
                        ctl_save_to_rd = 1'b1;
                    end
                        
                    `CMD_JAL : begin
                        ctl_JAL = 1'b1;
                        ctl_save_to_rd = 1'b1;
                    end
                    
                    `CMD_JALR : begin
                        ctl_JALR = 1'b1;
                        ctl_save_to_rd = 1'b1;
                        ctl_load_X_from_rs1 = 1'b1;
                    end
                    
                    `CMD_BRANCH : begin
                        ctl_BRANCH = 1'b1;
                        ctl_load_X_from_rs1 = 1'b1;
                        ctl_load_Y_from_rs2 = 1'b1;
                    end
                    
                    `CMD_LOAD : begin
                        ctl_LOAD = 1'b1;
                        ctl_load_X_from_rs1 = 1'b1;

                    end

                    `CMD_STORE : begin
                        ctl_STORE = 1'b1;
                        ctl_load_X_from_rs1 = 1'b1;
                        ctl_load_Y_from_rs2 = 1'b1;
                    end
                    
                    `CMD_SYSTEM : begin
                        ctl_SYSTEM = 1'b1;
                        
                        if ((funct12 [4 : 0] == 5'b00010) && (funct3 == 3'b000)) begin
                            ctl_MRET = 1'b1;
                        end else if ((funct12 [4 : 0] == 5'b00101) && (funct3 == 3'b000)) begin
                            ctl_WFI = 1'b1;
                        end else begin


                            ctl_CSR = |funct3;
                        end 
                        
                        ctl_save_to_rd = ctl_CSR;
                        ctl_CSR_write = |rs1;
                        ctl_load_X_from_rs1 = 1'b1;
                        
                    end

                    `CMD_MISC_MEM : begin

                        if (IR_out[14:12] == 3'b001)
                            ctl_MISC_MEM = 1'b1;
                    end
                        
                    default : begin
                        exception_illegal_instruction = 1'b1;
                    end
                        
                endcase

            end

endmodule
module RV2T_instruction_decode (




        input wire                                              clk,                          
        input wire                                              reset_n,                      
        input wire                                              sync_reset,
   



        input wire                                              decode_enable,
        



        input wire                                              enable_in,
        input wire [`XLEN - 1 : 0]                              IR_in,
        input wire [`PC_BITWIDTH - 1 : 0]                       PC_in,




        output wire [`REG_ADDR_BITS - 1 : 0]                    rs1,
        output wire [`REG_ADDR_BITS - 1 : 0]                    rs2,
     



        output  wire [`CSR_BITS - 1 : 0]                        csr,
        output  reg                                             csr_read_enable,
         




        output reg [`XLEN - 1 : 2]                              IR_out,
        output reg [`PC_BITWIDTH - 1 : 0]                       PC_out,
        
        output reg                                              ctl_load_X_from_rs1,
        output reg                                              ctl_load_Y_from_rs2,
        output reg                                              ctl_load_Y_from_imm_12,
        output reg                                              ctl_load_Y_from_store_offset_12,
        output reg                                              ctl_save_to_rd,
        output reg                                              ctl_ALU_FUNCT3,
        output reg                                              ctl_MUL_DIV_FUNCT3,
        output reg                                              ctl_LUI,
        output reg                                              ctl_AUIPC,
        output reg                                              ctl_JAL,
        output reg                                              ctl_JALR,
        output reg                                              ctl_BRANCH,
        output reg                                              ctl_LOAD,
        output reg                                              ctl_STORE,
        output reg                                              ctl_SYSTEM,
        output reg                                              ctl_CSR,
        output reg                                              ctl_CSR_write,
        output reg                                              ctl_MISC_MEM,
        output reg                                              ctl_MRET,
        output reg                                              ctl_WFI,

        output reg                                              exception_illegal_instruction
);

    



        wire    [`REG_ADDR_BITS - 1 : 0]                        rs1_32;
        wire    [`REG_ADDR_BITS - 1 : 0]                        rs2_32;
        
        wire    [`REG_ADDR_BITS - 1 : 0]                        rd;
        wire    [2 : 0]                                         funct3;
        wire    [11 : 0]                                        funct12;
        reg                                                     illegal;
        



    



            
            assign rs1_32 = IR_in [19 : 15];
            assign rs2_32 = IR_in [24 : 20];

            assign rd = IR_in [11 : 7];
            
            assign rs1 = rs1_32;
            assign rs2 = rs2_32;





            assign funct3  = IR_in [14 : 12];
            assign funct12 = IR_in [31 : 20];





            assign csr     = IR_in [31 : 20];

            always @(*) begin : csr_read_enable_proc
                csr_read_enable = ctl_CSR;
            end
            
            



            
            
            always @(posedge clk, negedge reset_n) begin
                if (!reset_n) begin
                    IR_out <= 0;
                    PC_out <= 0;
                    illegal <= 0;
                end else begin
                    IR_out <= IR_in[`XLEN - 1 : 2];
                    PC_out <= PC_in;

                    if (|IR_in == 1'b0 || &IR_in == 1'b1)
                        illegal <= 1'b1;
                    else
                        illegal <= 1'b0;
                end
            end
            




            always @(*) begin : decode_proc
                ctl_load_X_from_rs1 = 0;
                ctl_load_Y_from_rs2 = 0;
                ctl_load_Y_from_imm_12 = 0;
                
                ctl_save_to_rd = 0;
                
                ctl_ALU_FUNCT3 = 0;
                ctl_MUL_DIV_FUNCT3 = 0;
                ctl_LUI = 0;
                ctl_AUIPC = 0;
                
                ctl_JAL = 0;
                ctl_JALR = 0;
                
                ctl_BRANCH = 0;
                ctl_LOAD = 0;
                ctl_STORE = 0;
                ctl_SYSTEM = 0;
                ctl_CSR = 0;
                ctl_CSR_write = 0;
                ctl_MISC_MEM = 0;
                ctl_MRET = 0;
                ctl_WFI = 0;
                exception_illegal_instruction = illegal;

                case (IR_out [6 : 2])
                    `CMD_OP_IMM : begin
                        ctl_load_X_from_rs1 = 1'b1;
                        ctl_load_Y_from_imm_12 = 1'b1;
                        ctl_save_to_rd = 1'b1;
                        ctl_ALU_FUNCT3 = 1'b1;
                    end
                        
                    `CMD_OP : begin
                        ctl_load_X_from_rs1 = 1'b1;
                        ctl_load_Y_from_rs2 = 1'b1;
                        ctl_save_to_rd = 1'b1;
                        ctl_ALU_FUNCT3 = ~IR_out[25];
                        ctl_MUL_DIV_FUNCT3 = IR_out[25];
                    end
                        
                    `CMD_LUI : begin
                        ctl_LUI = 1'b1;
                        ctl_save_to_rd = 1'b1;
                    end
                        
                    `CMD_AUIPC : begin
                        ctl_AUIPC = 1'b1;
                        ctl_save_to_rd = 1'b1;
                    end
                        
                    `CMD_JAL : begin
                        ctl_JAL = 1'b1;
                        ctl_save_to_rd = 1'b1;
                    end
                    
                    `CMD_JALR : begin
                        ctl_JALR = 1'b1;
                        ctl_save_to_rd = 1'b1;
                        ctl_load_X_from_rs1 = 1'b1;
                    end
                    
                    `CMD_BRANCH : begin
                        ctl_BRANCH = 1'b1;
                        ctl_load_X_from_rs1 = 1'b1;
                        ctl_load_Y_from_rs2 = 1'b1;
                    end
                    
                    `CMD_LOAD : begin
                        ctl_LOAD = 1'b1;
                        ctl_load_X_from_rs1 = 1'b1;

                    end

                    `CMD_STORE : begin
                        ctl_STORE = 1'b1;
                        ctl_load_X_from_rs1 = 1'b1;
                        ctl_load_Y_from_rs2 = 1'b1;
                    end
                    
                    `CMD_SYSTEM : begin
                        ctl_SYSTEM = 1'b1;
                        
                        if ((funct12 [4 : 0] == 5'b00010) && (funct3 == 3'b000)) begin
                            ctl_MRET = 1'b1;
                        end else if ((funct12 [4 : 0] == 5'b00101) && (funct3 == 3'b000)) begin
                            ctl_WFI = 1'b1;
                        end else begin


                            ctl_CSR = |funct3;
                        end 
                        
                        ctl_save_to_rd = ctl_CSR;
                        ctl_CSR_write = |rs1;
                        ctl_load_X_from_rs1 = 1'b1;
                        
                    end

                    `CMD_MISC_MEM : begin

                        if (IR_out[14:12] == 3'b001)
                            ctl_MISC_MEM = 1'b1;
                    end
                        
                    default : begin
                        exception_illegal_instruction = 1'b1;
                    end
                        
                endcase

            end

endmodule