data/full_repos/permissive/161473991/source/clock.v
data/verilator_xmls/0a7b17a1-ed93-46e3-9123-60eac9a88d01.xml
module clock(
    input clk, 
    rst,
    h,
    min,
    output reg[5:0] hour, 
    output reg[5:0] minute, 
    output reg[5:0] second
);




wire clk_bps;
wire clk_fbps;
reg [5:0] reg_hour, reg_minute, reg_second;
    
counter u_c(clk,rst,clk_bps);
counter_tube u_t(clk,rst,clk_fbps);



always @(posedge clk)
    begin
        hour = reg_hour;
        minute = reg_minute;
        second = reg_second;
    end






always @(posedge clk_bps or posedge rst)
    begin
        if(rst)
            reg_second <= 6'b000000;
        else if(reg_second == 6'd59)
            reg_second <= 6'd0;
        else
            reg_second <= reg_second + 1'b1;
    end



reg [2:0] mm;
reg [2:0] mh;
reg cm;
reg ch;
reg [1:0] c1;
reg [1:0] c2;





always @(posedge clk_fbps or posedge rst)
begin
    c1 = c1 + 1;
    if(c1 == 2'b00 && ~min)
        begin
            if(rst)
                reg_minute <= 6'b000000;
            else if(reg_minute == 6'd59 )
            begin
                if(reg_second == 6'd59)
                reg_minute <= 6'd0;
            end
            else if(reg_second == 6'd59)
                reg_minute <= reg_minute + 1'b1;
        end
        else if(min)
        begin
            if(rst)
                reg_minute <= 6'b000000;
            else if(reg_minute == 6'd59)
                reg_minute <= 6'd0;
            else
                reg_minute <= reg_minute+1;
        end
end






always @(posedge clk_fbps , posedge rst)
begin
    c2=c2+1;
    if(~h && c2 == 2'b00)
    begin
        if(rst)
            reg_hour <= 6'b000000;
        else if(reg_hour == 6'd23 )
        begin
            if(reg_minute == 6'd59)
            begin
                if(reg_second == 6'd59)
                    reg_hour <= 6'd0;
            end
        end
        else if(reg_minute == 6'd59)
        begin
            if(reg_second == 6'd59)
                reg_hour <= reg_hour + 1'b1;
        end   
    end
    else if(h)
    begin
        if(rst)
            reg_hour <= 6'b000000;
        else if(reg_hour == 6'd23)
            reg_hour <= 6'd0;
        else
            reg_hour <= reg_hour + 1;
    end     
end


endmodule
module clock(
    input clk, 
    rst,
    h,
    min,
    output reg[5:0] hour, 
    output reg[5:0] minute, 
    output reg[5:0] second
);





wire clk_bps;
wire clk_fbps;
reg [5:0] reg_hour, reg_minute, reg_second;
    
counter u_c(clk,rst,clk_bps);
counter_tube u_t(clk,rst,clk_fbps);



always @(posedge clk)
    begin
        hour = reg_hour;
        minute = reg_minute;
        second = reg_second;
    end






always @(posedge clk_bps or posedge rst)
    begin
        if(rst)
            reg_second <= 6'b000000;
        else if(reg_second == 6'd59)
            reg_second <= 6'd0;
        else
            reg_second <= reg_second + 1'b1;
    end



reg [2:0] mm;
reg [2:0] mh;
reg cm;
reg ch;
reg [1:0] c1;
reg [1:0] c2;





always @(posedge clk_fbps or posedge rst)
begin
    c1 = c1 + 1;
    if(c1 == 2'b00 && ~min)
        begin
            if(rst)
                reg_minute <= 6'b000000;
            else if(reg_minute == 6'd59 )
            begin
                if(reg_second == 6'd59)
                reg_minute <= 6'd0;
            end
            else if(reg_second == 6'd59)
                reg_minute <= reg_minute + 1'b1;
        end
        else if(min)
        begin
            if(rst)
                reg_minute <= 6'b000000;
            else if(reg_minute == 6'd59)
                reg_minute <= 6'd0;
            else
                reg_minute <= reg_minute+1;
        end
end






always @(posedge clk_fbps , posedge rst)
begin
    c2=c2+1;
    if(~h && c2 == 2'b00)
    begin
        if(rst)
            reg_hour <= 6'b000000;
        else if(reg_hour == 6'd23 )
        begin
            if(reg_minute == 6'd59)
            begin
                if(reg_second == 6'd59)
                    reg_hour <= 6'd0;
            end
        end
        else if(reg_minute == 6'd59)
        begin
            if(reg_second == 6'd59)
                reg_hour <= reg_hour + 1'b1;
        end   
    end
    else if(h)
    begin
        if(rst)
            reg_hour <= 6'b000000;
        else if(reg_hour == 6'd23)
            reg_hour <= 6'd0;
        else
            reg_hour <= reg_hour + 1;
    end     
end


endmodule