data/full_repos/permissive/193530477/source codes/arykeyscan.v
1: b'%Error: Cannot find file containing module: codes,data/full_repos/permissive/193530477\n        ... Looked in:\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.v\n             data/full_repos/permissive/193530477/source/codes,data/full_repos/permissive/193530477.sv\n             codes,data/full_repos/permissive/193530477\n             codes,data/full_repos/permissive/193530477.v\n             codes,data/full_repos/permissive/193530477.sv\n             obj_dir/codes,data/full_repos/permissive/193530477\n             obj_dir/codes,data/full_repos/permissive/193530477.v\n             obj_dir/codes,data/full_repos/permissive/193530477.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/193530477/source\n%Error: Cannot find file containing module: codes/arykeyscan.v\n%Error: Exiting due to 3 error(s)\n'
module arykeyscan(
	input clk,
	input rst_n,
	input[3:0] key_v,
	output reg[3:0] key_h,
	output reg[15:0] display_num

);

wire[3:0] keyv_value;
wire keydown ;
wire keyup ;

sigkeyscan uut_sigkeyscan(
	.clk(clk),
	.rst_n(rst_n),
	.key_v(key_v),
	.keyv_value(keyv_value),
	.key_neg(keydown),
	.key_pos(keyup)
);


reg[3:0] nstate, cstate;
parameter K_IDLE  = 4'd0;
parameter K_H1OL  = 4'd1;
parameter K_H2OL  = 4'd2;
parameter K_H3OL  = 4'd3;
parameter K_H4OL  = 4'd4;
parameter K_CHCK  = 4'd5;


always @ (posedge clk or negedge rst_n)
	if(!rst_n)	cstate <= K_IDLE;
	else			cstate <= nstate;

always @ (posedge clk or negedge rst_n)
	case(cstate)
		K_IDLE:	if(keyv_value != 4'b0000)	nstate <= K_H1OL;
					else 	nstate <= K_IDLE;
		K_H1OL:	nstate <= K_H2OL;
		K_H2OL:	if(key_v!= 4'b1111)	nstate <= K_IDLE;
					else 	nstate <= K_H3OL;
		K_H3OL:	if(key_v!= 4'b1111)	nstate <= K_IDLE;
					else 	nstate <= K_H4OL;
		K_H4OL:	if(key_v!= 4'b1111)	nstate <= K_IDLE;
					else 	nstate <= K_CHCK;
		K_CHCK:	nstate <= K_IDLE;
		default: ;
	endcase



reg[3:0] new_value;
reg new_rdy = 1'b0;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) begin
		key_h <= 4'b0000;
		new_value <= 4'd0;
		new_rdy <= 1'b0;
	end
	else begin
		case(cstate)
			K_IDLE:	begin	
					key_h <= 4'b0000;
					new_value <= 4'd0;
					new_rdy <= 1'b0;
				end	
			K_H1OL:	begin	
					key_h <= 4'b1110;
					new_value <= 4'd0;
					new_rdy <= 1'b0;
				end
			K_H2OL:	begin 
					case(key_v)
						4'b1110:  begin
								key_h <= 4'b0000;
								new_value <= 4'd0;
								new_rdy <= 1'b1;
							end
						4'b1101:  begin
								key_h <= 4'b0000;
								new_value <= 4'd1;
								new_rdy <= 1'b1;
							end
						4'b1011:  begin
								key_h <= 4'b0000;
								new_value <= 4'd2;
								new_rdy <= 1'b1;
							end
						4'b0111:  begin
								key_h <= 4'b0000;
								new_value <= 4'd3;
								new_rdy <= 1'b1;
							end
						default:  begin
								key_h <= 4'b1101;
								new_value <= 4'd0;
								new_rdy <= 1'b0;
							end
					endcase
				end
			K_H3OL:	begin 
					case(key_v)
						4'b1110:  begin
								key_h <= 4'b0000;
								new_value <= 4'd4;
								new_rdy <= 1'b1;
							end
						4'b1101:  begin
								key_h <= 4'b0000;
								new_value <= 4'd5;
								new_rdy <= 1'b1;
							end
						4'b1011:  begin
								key_h <= 4'b0000;
								new_value <= 4'd6;
								new_rdy <= 1'b1;
							end
						4'b0111:  begin
								key_h <= 4'b0000;
								new_value <= 4'd7;
								new_rdy <= 1'b1;
							end
						default:  begin
								key_h <= 4'b1011;
								new_value <= 4'd0;
								new_rdy <= 1'b0;
							end
					endcase
				end
			K_H4OL:	begin 
					case(key_v)
						4'b1110:  begin
								key_h <= 4'b0000;
								new_value <= 4'd8;
								new_rdy <= 1'b1;
							end
						4'b1101:  begin
								key_h <= 4'b0000;
								new_value <= 4'd9;
								new_rdy <= 1'b1;
							end
						4'b1011:  begin
								key_h <= 4'b0000;
								new_value <= 4'd10;
								new_rdy <= 1'b1;
							end
						4'b0111:  begin
								key_h <= 4'b0000;
								new_value <= 4'd11;
								new_rdy <= 1'b1;
							end
						default:  begin
								key_h <= 4'b0111;
								new_value <= 4'd0;
								new_rdy <= 1'b0;
							end
					endcase
				end
			K_CHCK:	begin 
					case(key_v)
						4'b1110:  begin
								key_h <= 4'b0000;
								new_value <= 4'd12;
								new_rdy <= 1'b1;
							end
						4'b1101:  begin
								key_h <= 4'b0000;
								new_value <= 4'd13;
								new_rdy <= 1'b1;
							end
						4'b1011:  begin
								key_h <= 4'b0000;
								new_value <= 4'd14;
								new_rdy <= 1'b1;
							end
						4'b0111:  begin
								key_h <= 4'b0000;
								new_value <= 4'd15;
								new_rdy <= 1'b1;
							end
						default:  begin
								key_h <= 4'b0000;
								new_value <= 4'd0;
								new_rdy <= 1'b0;
							end
					endcase
				end
			default: ;
		endcase
	end
		


always @ (posedge clk or negedge rst_n) begin
	if(!rst_n)	display_num <= 16'h0000;
	else if(new_rdy)
		begin
			display_num <= {display_num[11:0],new_value};

		end	


	end
endmodule
module arykeyscan(
	input clk,
	input rst_n,
	input[3:0] key_v,
	output reg[3:0] key_h,
	output reg[15:0] display_num

);


wire[3:0] keyv_value;
wire keydown ;
wire keyup ;

sigkeyscan uut_sigkeyscan(
	.clk(clk),
	.rst_n(rst_n),
	.key_v(key_v),
	.keyv_value(keyv_value),
	.key_neg(keydown),
	.key_pos(keyup)
);


reg[3:0] nstate, cstate;
parameter K_IDLE  = 4'd0;
parameter K_H1OL  = 4'd1;
parameter K_H2OL  = 4'd2;
parameter K_H3OL  = 4'd3;
parameter K_H4OL  = 4'd4;
parameter K_CHCK  = 4'd5;


always @ (posedge clk or negedge rst_n)
	if(!rst_n)	cstate <= K_IDLE;
	else			cstate <= nstate;

always @ (posedge clk or negedge rst_n)
	case(cstate)
		K_IDLE:	if(keyv_value != 4'b0000)	nstate <= K_H1OL;
					else 	nstate <= K_IDLE;
		K_H1OL:	nstate <= K_H2OL;
		K_H2OL:	if(key_v!= 4'b1111)	nstate <= K_IDLE;
					else 	nstate <= K_H3OL;
		K_H3OL:	if(key_v!= 4'b1111)	nstate <= K_IDLE;
					else 	nstate <= K_H4OL;
		K_H4OL:	if(key_v!= 4'b1111)	nstate <= K_IDLE;
					else 	nstate <= K_CHCK;
		K_CHCK:	nstate <= K_IDLE;
		default: ;
	endcase



reg[3:0] new_value;
reg new_rdy = 1'b0;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) begin
		key_h <= 4'b0000;
		new_value <= 4'd0;
		new_rdy <= 1'b0;
	end
	else begin
		case(cstate)
			K_IDLE:	begin	
					key_h <= 4'b0000;
					new_value <= 4'd0;
					new_rdy <= 1'b0;
				end	
			K_H1OL:	begin	
					key_h <= 4'b1110;
					new_value <= 4'd0;
					new_rdy <= 1'b0;
				end
			K_H2OL:	begin 
					case(key_v)
						4'b1110:  begin
								key_h <= 4'b0000;
								new_value <= 4'd0;
								new_rdy <= 1'b1;
							end
						4'b1101:  begin
								key_h <= 4'b0000;
								new_value <= 4'd1;
								new_rdy <= 1'b1;
							end
						4'b1011:  begin
								key_h <= 4'b0000;
								new_value <= 4'd2;
								new_rdy <= 1'b1;
							end
						4'b0111:  begin
								key_h <= 4'b0000;
								new_value <= 4'd3;
								new_rdy <= 1'b1;
							end
						default:  begin
								key_h <= 4'b1101;
								new_value <= 4'd0;
								new_rdy <= 1'b0;
							end
					endcase
				end
			K_H3OL:	begin 
					case(key_v)
						4'b1110:  begin
								key_h <= 4'b0000;
								new_value <= 4'd4;
								new_rdy <= 1'b1;
							end
						4'b1101:  begin
								key_h <= 4'b0000;
								new_value <= 4'd5;
								new_rdy <= 1'b1;
							end
						4'b1011:  begin
								key_h <= 4'b0000;
								new_value <= 4'd6;
								new_rdy <= 1'b1;
							end
						4'b0111:  begin
								key_h <= 4'b0000;
								new_value <= 4'd7;
								new_rdy <= 1'b1;
							end
						default:  begin
								key_h <= 4'b1011;
								new_value <= 4'd0;
								new_rdy <= 1'b0;
							end
					endcase
				end
			K_H4OL:	begin 
					case(key_v)
						4'b1110:  begin
								key_h <= 4'b0000;
								new_value <= 4'd8;
								new_rdy <= 1'b1;
							end
						4'b1101:  begin
								key_h <= 4'b0000;
								new_value <= 4'd9;
								new_rdy <= 1'b1;
							end
						4'b1011:  begin
								key_h <= 4'b0000;
								new_value <= 4'd10;
								new_rdy <= 1'b1;
							end
						4'b0111:  begin
								key_h <= 4'b0000;
								new_value <= 4'd11;
								new_rdy <= 1'b1;
							end
						default:  begin
								key_h <= 4'b0111;
								new_value <= 4'd0;
								new_rdy <= 1'b0;
							end
					endcase
				end
			K_CHCK:	begin 
					case(key_v)
						4'b1110:  begin
								key_h <= 4'b0000;
								new_value <= 4'd12;
								new_rdy <= 1'b1;
							end
						4'b1101:  begin
								key_h <= 4'b0000;
								new_value <= 4'd13;
								new_rdy <= 1'b1;
							end
						4'b1011:  begin
								key_h <= 4'b0000;
								new_value <= 4'd14;
								new_rdy <= 1'b1;
							end
						4'b0111:  begin
								key_h <= 4'b0000;
								new_value <= 4'd15;
								new_rdy <= 1'b1;
							end
						default:  begin
								key_h <= 4'b0000;
								new_value <= 4'd0;
								new_rdy <= 1'b0;
							end
					endcase
				end
			default: ;
		endcase
	end
		


always @ (posedge clk or negedge rst_n) begin
	if(!rst_n)	display_num <= 16'h0000;
	else if(new_rdy)
		begin
			display_num <= {display_num[11:0],new_value};

		end	


	end
endmodule