data/full_repos/permissive/201488448/2_circuits/1_combinational/18_mux21.v
data/verilator_xmls/0fc2364c-0ec1-4888-a263-99d7e1b4b916.xml
module top_module (
	input a,
	input b,
	input sel,
	output out
);

	assign out = (sel & b) | (~sel & a);
	


	
endmodule
module top_module (
	input a,
	input b,
	input sel,
	output out
);


	assign out = (sel & b) | (~sel & a);
	


	
endmodule