data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/IIC_driver_ASM2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/IIC_driver_ASM2.v:133: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'index_r\' generates 4 bits.\n                                                                                                                       : ... In instance IIC_driver_ASM2\n assign TEST2  = index_r;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/IIC_driver_ASM2.v:149: Bit extraction of var[31:0] requires 5 bit index, not 3 bits.\n                                                                                                                       : ... In instance IIC_driver_ASM2\n    ACK[index_ack]<=SDA_io_I;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/156971787/IP_core/video_processing_v2_00_a/hdl/verilog/IIC_driver_ASM2.v:310: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                                                       : ... In instance IIC_driver_ASM2\n      data_o<=data_temp[7:0];\n            ^~\n%Error: Exiting due to 3 warning(s)\n'
module IIC_driver_ASM2(
	rst_i,
	clk_i,
	DA_i,
	RA_i,
	data_i,
	SDA_io_I,
	SDA_io_O,
	SDA_io_T,
	SCL_o,
	vld_i,
	rdy_o,
	data_o,
	ACK_o,
	TEST2
	);


	localparam
				  VALID=2'b10,	

				  READ=1'b1,
				  WRITE=1'b0,

				  IN=1'b1,
				  OUT=1'b0,

				  IDLE=4'b0000,
				  START=4'b0001,
				  DAB=4'b0010,
				  SACK=4'b0011,
				  RAB=4'b0100,
				  SACK2=4'b0101,
				  RESTART=4'b0110,
				  DATA_W=4'b0111,
				  SACK3=4'b1000,
				  DAB_R=4'b1001,
				  SACK4=4'b1010,
				  DATA_R=4'b1011,
				  MACK=4'b1100,
				  STOP=4'b1101,
				  SLACK=4'b1110;
				  

	input wire rst_i,clk_i,vld_i;
	input wire [7:0] DA_i,data_i,RA_i;
	output wire [31:0] TEST2;

	output reg rdy_o				=	1'b1;
	output reg [31:0] data_o	=	32'd0;
	output reg [31:0] ACK_o		=	32'd0; 
	

	output wire SCL_o;
	input SDA_io_I; 	
	output reg SDA_io_O;
	output wire SDA_io_T;
	

	reg dir=OUT;
	reg start_out=1'b0;
	reg [8:0] data_temp=9'h000;
	reg [3:0] state=IDLE;
	reg [2:0] index_w = 3'h7;
	reg [3:0] index_r = 4'h8;
	reg [2:0] index_ack =3'b000;
	reg SCL_o_en=1'b0;
	reg [1:0] vld_temp=2'b11;
	reg [31:0] ACK=32'd0;
	

	assign SCL_o    = (SCL_o_en==1'b1) ? ~clk_i : (start_out==1'b0 && state==DAB)? 1'b0 :1'b1 ;
	assign SDA_io_T = dir;
	assign TEST2	 = index_r;


	always @(negedge clk_i or posedge rst_i)
	begin
		if(rst_i)
		begin
			data_temp<=9'h000;
			ACK<=32'd0;
		end
		else
		begin
			if(state==DATA_R) data_temp[index_r]<=SDA_io_I;
			
			if((state==RAB && index_w==3'h7 ) || (state==DATA_W && index_w==3'h7)  || (state==DATA_R && index_r==4'h8 )||state==SLACK)
			begin
				ACK[index_ack]<=SDA_io_I;
				index_ack<=index_ack+1'b1;
			end
			else
			begin
				if(state==IDLE || state==STOP)
				begin
					index_ack<=0;
				end
			end	
		end
	end
	

	always@( posedge clk_i or posedge rst_i)
	begin
		if(rst_i)
		begin
			index_r<=4'h8;
			index_w<=3'h7;
			state<=IDLE;
			SDA_io_O<=1'b1; 
			dir<=OUT;
			vld_temp<=2'b11;
			rdy_o<=1;
			data_o<=32'd0;
			SCL_o_en<=1'b0;
			ACK_o<=32'd0;
			start_out<=1'b0;
		end
		else
		begin
			vld_temp[0]<=vld_i;
			vld_temp[1]<=vld_temp[0];
			
			if(vld_temp==VALID)
			begin
				rdy_o<=1'b0;
			end
			case(state)
			IDLE:	begin
						dir<=OUT;
						SDA_io_O<=1'b1;
						start_out<=1'b0;
						if(~rdy_o) state<=START;
						else state<=IDLE;
					end
			START:begin
						SDA_io_O<=1'b0;
						index_w<=3'h7;
						if(start_out)
						begin
							state<=DAB;
							start_out<=1'b0;
						end
						else
						begin
							start_out<=1'b1;
						end
					end
			DAB:	begin
						SDA_io_O<=DA_i[index_w];
						if(index_w>3'h0) 
						begin
							state<=DAB;
							index_w<=index_w-1;
						end
						else
						begin
							SDA_io_O<=1'b0;
							state<=SACK;	
						end								
					end
			SACK:	begin
						dir<=IN;
						index_w<=3'h7;
						state<=RAB;
					end	
			RAB:	begin
						dir<=OUT;
						SDA_io_O<=RA_i[index_w];
						if(index_w>3'h0) 
						begin
							state<=RAB;
							index_w<=index_w-1;
						end
						else state<=SACK2;
					end
			SACK2:begin
						dir<=IN;
						if(DA_i[0]==WRITE) 
						begin
							state<=DATA_W;
							index_w<=3'h7;
						end
						else state<=SLACK;							
					end
			DATA_W:begin
						dir<=OUT;
						SDA_io_O<=data_i[index_w];
						if(index_w>3'h0)
						begin
							state<=DATA_W;
							index_w<=index_w-1;
						end
						else state<=SACK3;
					end
			SACK3:begin
						dir<=IN;
						state<=STOP;
					end
			
			SLACK:begin
						dir<=OUT;
						SDA_io_O<=1'b1;
						state<=RESTART;
					end
			RESTART:begin
						dir<=OUT;
						SDA_io_O<=1'b1; 
						if(index_w==3'h1)
						begin
							SDA_io_O<=1'b0; 
							index_w<=3'h7;
							state<=DAB_R;
						end
						else
						begin
							index_w<=3'h1;
							state<=RESTART;
						end
					end
			DAB_R:begin
						SDA_io_O<=DA_i[index_w]; 
						if(index_w>3'h0)
						begin
							state<=DAB_R;
							index_w<=index_w-1;
						end
						else state<=SACK4;
					end
			SACK4:begin
						dir<=IN;
						index_r<=4'h8;
						state<=DATA_R;
					end
			DATA_R:begin
						if(index_r>4'h0)
						begin
							state<=DATA_R;
							index_r<=index_r-1;
						end
						else 
						begin
							state<=STOP;
							dir<=OUT;
							SDA_io_O<=1'b1; 
						end	
					end
			STOP:	begin
						dir<=OUT;
						data_o<=data_temp[7:0];
						ACK_o<=ACK;
						SDA_io_O<=1'b0; 
						rdy_o<=1'b1;
						state<=IDLE;
					end		
			default : begin
							rdy_o<=1'b1;
							state<=IDLE;
						 end
			endcase	
			

			if(ACK[index_ack-1]) 
			begin
				state<=STOP;
			end
			

			if((state==IDLE)||(state==START)||(state==RESTART))
			begin
				SCL_o_en<=1'b0;
			end
			else SCL_o_en<=1'b1;		
		end
	end
endmodule
module IIC_driver_ASM2(
	rst_i,
	clk_i,
	DA_i,
	RA_i,
	data_i,
	SDA_io_I,
	SDA_io_O,
	SDA_io_T,
	SCL_o,
	vld_i,
	rdy_o,
	data_o,
	ACK_o,
	TEST2
	);



	localparam
				  VALID=2'b10,	

				  READ=1'b1,
				  WRITE=1'b0,

				  IN=1'b1,
				  OUT=1'b0,

				  IDLE=4'b0000,
				  START=4'b0001,
				  DAB=4'b0010,
				  SACK=4'b0011,
				  RAB=4'b0100,
				  SACK2=4'b0101,
				  RESTART=4'b0110,
				  DATA_W=4'b0111,
				  SACK3=4'b1000,
				  DAB_R=4'b1001,
				  SACK4=4'b1010,
				  DATA_R=4'b1011,
				  MACK=4'b1100,
				  STOP=4'b1101,
				  SLACK=4'b1110;
				  

	input wire rst_i,clk_i,vld_i;
	input wire [7:0] DA_i,data_i,RA_i;
	output wire [31:0] TEST2;

	output reg rdy_o				=	1'b1;
	output reg [31:0] data_o	=	32'd0;
	output reg [31:0] ACK_o		=	32'd0; 
	

	output wire SCL_o;
	input SDA_io_I; 	
	output reg SDA_io_O;
	output wire SDA_io_T;
	

	reg dir=OUT;
	reg start_out=1'b0;
	reg [8:0] data_temp=9'h000;
	reg [3:0] state=IDLE;
	reg [2:0] index_w = 3'h7;
	reg [3:0] index_r = 4'h8;
	reg [2:0] index_ack =3'b000;
	reg SCL_o_en=1'b0;
	reg [1:0] vld_temp=2'b11;
	reg [31:0] ACK=32'd0;
	

	assign SCL_o    = (SCL_o_en==1'b1) ? ~clk_i : (start_out==1'b0 && state==DAB)? 1'b0 :1'b1 ;
	assign SDA_io_T = dir;
	assign TEST2	 = index_r;


	always @(negedge clk_i or posedge rst_i)
	begin
		if(rst_i)
		begin
			data_temp<=9'h000;
			ACK<=32'd0;
		end
		else
		begin
			if(state==DATA_R) data_temp[index_r]<=SDA_io_I;
			
			if((state==RAB && index_w==3'h7 ) || (state==DATA_W && index_w==3'h7)  || (state==DATA_R && index_r==4'h8 )||state==SLACK)
			begin
				ACK[index_ack]<=SDA_io_I;
				index_ack<=index_ack+1'b1;
			end
			else
			begin
				if(state==IDLE || state==STOP)
				begin
					index_ack<=0;
				end
			end	
		end
	end
	

	always@( posedge clk_i or posedge rst_i)
	begin
		if(rst_i)
		begin
			index_r<=4'h8;
			index_w<=3'h7;
			state<=IDLE;
			SDA_io_O<=1'b1; 
			dir<=OUT;
			vld_temp<=2'b11;
			rdy_o<=1;
			data_o<=32'd0;
			SCL_o_en<=1'b0;
			ACK_o<=32'd0;
			start_out<=1'b0;
		end
		else
		begin
			vld_temp[0]<=vld_i;
			vld_temp[1]<=vld_temp[0];
			
			if(vld_temp==VALID)
			begin
				rdy_o<=1'b0;
			end
			case(state)
			IDLE:	begin
						dir<=OUT;
						SDA_io_O<=1'b1;
						start_out<=1'b0;
						if(~rdy_o) state<=START;
						else state<=IDLE;
					end
			START:begin
						SDA_io_O<=1'b0;
						index_w<=3'h7;
						if(start_out)
						begin
							state<=DAB;
							start_out<=1'b0;
						end
						else
						begin
							start_out<=1'b1;
						end
					end
			DAB:	begin
						SDA_io_O<=DA_i[index_w];
						if(index_w>3'h0) 
						begin
							state<=DAB;
							index_w<=index_w-1;
						end
						else
						begin
							SDA_io_O<=1'b0;
							state<=SACK;	
						end								
					end
			SACK:	begin
						dir<=IN;
						index_w<=3'h7;
						state<=RAB;
					end	
			RAB:	begin
						dir<=OUT;
						SDA_io_O<=RA_i[index_w];
						if(index_w>3'h0) 
						begin
							state<=RAB;
							index_w<=index_w-1;
						end
						else state<=SACK2;
					end
			SACK2:begin
						dir<=IN;
						if(DA_i[0]==WRITE) 
						begin
							state<=DATA_W;
							index_w<=3'h7;
						end
						else state<=SLACK;							
					end
			DATA_W:begin
						dir<=OUT;
						SDA_io_O<=data_i[index_w];
						if(index_w>3'h0)
						begin
							state<=DATA_W;
							index_w<=index_w-1;
						end
						else state<=SACK3;
					end
			SACK3:begin
						dir<=IN;
						state<=STOP;
					end
			
			SLACK:begin
						dir<=OUT;
						SDA_io_O<=1'b1;
						state<=RESTART;
					end
			RESTART:begin
						dir<=OUT;
						SDA_io_O<=1'b1; 
						if(index_w==3'h1)
						begin
							SDA_io_O<=1'b0; 
							index_w<=3'h7;
							state<=DAB_R;
						end
						else
						begin
							index_w<=3'h1;
							state<=RESTART;
						end
					end
			DAB_R:begin
						SDA_io_O<=DA_i[index_w]; 
						if(index_w>3'h0)
						begin
							state<=DAB_R;
							index_w<=index_w-1;
						end
						else state<=SACK4;
					end
			SACK4:begin
						dir<=IN;
						index_r<=4'h8;
						state<=DATA_R;
					end
			DATA_R:begin
						if(index_r>4'h0)
						begin
							state<=DATA_R;
							index_r<=index_r-1;
						end
						else 
						begin
							state<=STOP;
							dir<=OUT;
							SDA_io_O<=1'b1; 
						end	
					end
			STOP:	begin
						dir<=OUT;
						data_o<=data_temp[7:0];
						ACK_o<=ACK;
						SDA_io_O<=1'b0; 
						rdy_o<=1'b1;
						state<=IDLE;
					end		
			default : begin
							rdy_o<=1'b1;
							state<=IDLE;
						 end
			endcase	
			

			if(ACK[index_ack-1]) 
			begin
				state<=STOP;
			end
			

			if((state==IDLE)||(state==START)||(state==RESTART))
			begin
				SCL_o_en<=1'b0;
			end
			else SCL_o_en<=1'b1;		
		end
	end
endmodule