data/full_repos/permissive/168189509/hdl/i2s_tx.v
data/verilator_xmls/ce3e4ef3-ae2e-41e4-93bd-1d2feeb5d778.xml
module i2s_tx #(
    parameter WIDTH = 32
) (
    input wire lrck,
    input wire sclk,

    output wire sdout,

    input wire [WIDTH - 1 : 0] pldin,
    input wire [WIDTH - 1 : 0] prdin
);

    reg lrck_d1;

    reg lrck_d2;

    always @(posedge sclk) begin
        lrck_d1 <= lrck;
        lrck_d2 <= lrck_d1;
    end


    wire lrck_p;

    assign lrck_p = lrck_d1 ^ lrck_d2;


    reg [WIDTH - 1 : 0] pdata;

    always @(*) begin
        if (lrck_d1) begin
            pdata = prdin;
        end else begin
            pdata = pldin;
        end
    end


    reg [WIDTH - 1 : 0] piso;

    always @(negedge sclk) begin
        if (lrck_p) begin
            piso <= pdata;
        end else begin
            piso <= {piso[WIDTH - 2 : 0], 1'b0};
        end
    end


    assign sdout = piso[WIDTH - 1 : WIDTH - 1];

endmodule
module i2s_tx #(
    parameter WIDTH = 32
) (
    input wire lrck,
    input wire sclk,

    output wire sdout,

    input wire [WIDTH - 1 : 0] pldin,
    input wire [WIDTH - 1 : 0] prdin
);


    reg lrck_d1;

    reg lrck_d2;

    always @(posedge sclk) begin
        lrck_d1 <= lrck;
        lrck_d2 <= lrck_d1;
    end


    wire lrck_p;

    assign lrck_p = lrck_d1 ^ lrck_d2;


    reg [WIDTH - 1 : 0] pdata;

    always @(*) begin
        if (lrck_d1) begin
            pdata = prdin;
        end else begin
            pdata = pldin;
        end
    end


    reg [WIDTH - 1 : 0] piso;

    always @(negedge sclk) begin
        if (lrck_p) begin
            piso <= pdata;
        end else begin
            piso <= {piso[WIDTH - 2 : 0], 1'b0};
        end
    end


    assign sdout = piso[WIDTH - 1 : WIDTH - 1];

endmodule