data/full_repos/permissive/133862949/src/sig_gen_tb.v
 line:28: before: "begin"
1: b'%Error: data/full_repos/permissive/133862949/src/sig_gen_tb.v:22: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n      sig_gen_output = $fopen("{{ sig_gen_output }}");\n                       ^~~~~~\n%Error: data/full_repos/permissive/133862949/src/sig_gen_tb.v:28: syntax error, unexpected \'@\'\n      @(posedge clk) begin\n      ^\n%Error: data/full_repos/permissive/133862949/src/sig_gen_tb.v:33: syntax error, unexpected end\n   end  \n   ^~~\n%Error: data/full_repos/permissive/133862949/src/sig_gen_tb.v:36: Unsupported: Verilog 2001-config reserved word not implemented; suggest you want `include instead: include\n   {% include "sig_gen_inst.v" %}\n      ^~~~~~~\n%Error: data/full_repos/permissive/133862949/src/sig_gen_tb.v:47: syntax error, unexpected $fclose\n            $fclose(sig_gen_output);\n            ^~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module sig_gen_tb();
   reg clk;
   integer sig_gen_output;

   reg     m_axis_freq_step_tvalid;
   reg [{{phase_bits}}-1: 0] freq_step;
   reg                       m_axis_data_tready;
   wire signed [{{n_bits}}-1:0] cosine;
   wire signed [{{n_bits}}-1:0] sine;
   wire                         s_axis_data_tvalid;
   integer                      icounter;

   initial begin
      clk = 1'b0;
      freq_step = {{ freq_step_str }};
      m_axis_data_tready = 1'b0;
      m_axis_freq_step_tvalid = 1'b0;
      icounter = 'd0;
      sig_gen_output = $fopen("{{ sig_gen_output }}");
      if (sig_gen_output == `NULL) begin
         $display("sig_gen_output handle was NULL");
         $finish;
      end

      @(posedge clk) begin
         m_axis_data_tready = 1'b1;
         m_axis_freq_step_tvalid = 1'b1;
      end

   end


   {% include "sig_gen_inst.v" %}
   
   always begin
      #10 clk = ~clk;
   end

   always @(posedge clk) begin
      if (s_axis_data_tvalid & m_axis_data_tready) begin
         $fwrite(sig_gen_output, "%d,%d\n", cosine, sine);
         icounter = icounter + 1'b1;
         if (icounter == 50000) begin
            $fclose(sig_gen_output);
            $finish;
         end
      end
   end
endmodule
module sig_gen_tb();

   reg clk;
   integer sig_gen_output;

   reg     m_axis_freq_step_tvalid;
   reg [{{phase_bits}}-1: 0] freq_step;
   reg                       m_axis_data_tready;
   wire signed [{{n_bits}}-1:0] cosine;
   wire signed [{{n_bits}}-1:0] sine;
   wire                         s_axis_data_tvalid;
   integer                      icounter;

   initial begin
      clk = 1'b0;
      freq_step = {{ freq_step_str }};
      m_axis_data_tready = 1'b0;
      m_axis_freq_step_tvalid = 1'b0;
      icounter = 'd0;
      sig_gen_output = $fopen("{{ sig_gen_output }}");
      if (sig_gen_output == `NULL) begin
         $display("sig_gen_output handle was NULL");
         $finish;
      end

      @(posedge clk) begin
         m_axis_data_tready = 1'b1;
         m_axis_freq_step_tvalid = 1'b1;
      end

   end


   {% include "sig_gen_inst.v" %}
   
   always begin
      #10 clk = ~clk;
   end

   always @(posedge clk) begin
      if (s_axis_data_tvalid & m_axis_data_tready) begin
         $fwrite(sig_gen_output, "%d,%d\n", cosine, sine);
         icounter = icounter + 1'b1;
         if (icounter == 50000) begin
            $fclose(sig_gen_output);
            $finish;
         end
      end
   end
endmodule