data/full_repos/permissive/20726090/hw/vlog/amber23/a23_barrel_shift_fpga.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/20726090/hw/vlog/amber23/a23_barrel_shift_fpga.v:59: Cannot find include file: a23_localparams.v\n`include "a23_localparams.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20726090/hw/vlog/amber23,data/full_repos/permissive/20726090/a23_localparams.v\n             data/full_repos/permissive/20726090/hw/vlog/amber23,data/full_repos/permissive/20726090/a23_localparams.v.v\n             data/full_repos/permissive/20726090/hw/vlog/amber23,data/full_repos/permissive/20726090/a23_localparams.v.sv\n             a23_localparams.v\n             a23_localparams.v.v\n             a23_localparams.v.sv\n             obj_dir/a23_localparams.v\n             obj_dir/a23_localparams.v.v\n             obj_dir/a23_localparams.v.sv\n%Error: Exiting due to 1 error(s)\n'
module a23_barrel_shift_fpga (

input       [31:0]          i_in,
input                       i_carry_in,
input       [7:0]           i_shift_amount,
input                       i_shift_imm_zero,
input       [1:0]           i_function,

output      [31:0]          o_out,
output                      o_carry_out

);

`include "a23_localparams.v"

wire [31:0] rot_prod;

wire [1:0]  lsl_out;
wire [1:0]  lsr_out;
wire [1:0]  asr_out;
wire [1:0]  ror_out;

reg [32:0]  lsl_mask;
reg [32:0]  lsr_mask;
reg [15:0]  low_mask;

reg [4:0]   shift_amount;

reg [2:0]   lsl_selector;
reg [2:0]   lsr_selector;
reg [3:0]   low_selector;

reg         shift_nzero;
reg         shift_over;
reg         shift_32;
reg         asr_sign;
reg         direction;

wire [31:0] p_r;
wire [31:0] p_l;








always @*
begin
	shift_32 = i_shift_amount == 32;

	shift_over = |i_shift_amount[7:5];

	shift_nzero = |i_shift_amount[7:0];

	shift_amount = i_shift_amount[4:0];

	if (i_shift_imm_zero) begin
		if (i_function == LSR || i_function == ASR) begin




			shift_nzero = 1'b1;
			shift_over = 1'b1;


		end else if (i_function == ROR) begin

			shift_amount[0] = 1'b1;
			shift_nzero = 1'b1;
		end
	end




	case (i_function)
		LSL: low_selector = shift_amount[3:0];
		LSR: low_selector = shift_amount[3:0];
		ASR: low_selector = shift_amount[3:0];
		ROR: low_selector = 4'b0000;
	endcase


	case (i_function)
		LSL: lsl_selector = {shift_32, shift_over, shift_amount[4]};
		LSR: lsl_selector = 3'b0_1_0;
		ASR: lsl_selector = 3'b0_1_0;
		ROR: lsl_selector = 3'b0_1_0;
	endcase


	case (i_function)
		LSL: lsr_selector = 3'b0_1_0;
		LSR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
		ASR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
		ROR: lsr_selector = 3'b0_0_0;
	endcase


	case (i_function)
		LSL: direction = 1'b0;
		LSR: direction = 1'b1;
		ASR: direction = 1'b1;
		ROR: direction = 1'b1;
	endcase


	asr_sign = 1'b0;
	if (i_function == ASR && i_in[31])
		asr_sign = 1'b1;
end



generate
genvar i, j;
	for (i = 0; i < 5; i = i + 1)
	begin : netgen
		wire [31:0] in;
		reg [31:0] out;
		for (j = 0; j < 32; j = j + 1)
		begin : net
			always @*
				out[j] = in[j] & (~shift_amount[i] ^ direction) |
					 in[wrap(j, i)] & (shift_amount[i] ^ direction);
		end
	end


	assign netgen[4].in = i_in;
	for (i = 1; i < 5; i = i + 1)
	begin : router
		assign netgen[i-1].in = netgen[i].out;
	end
endgenerate


assign rot_prod = netgen[0].out;



always @*
case (low_selector)
	4'b0000:	low_mask = 16'hffff;
	4'b0001:	low_mask = 16'hfffe;
	4'b0010:	low_mask = 16'hfffc;
	4'b0011:	low_mask = 16'hfff8;
	4'b0100:	low_mask = 16'hfff0;
	4'b0101:	low_mask = 16'hffe0;
	4'b0110:	low_mask = 16'hffc0;
	4'b0111:	low_mask = 16'hff80;
	4'b1000:	low_mask = 16'hff00;
	4'b1001:	low_mask = 16'hfe00;
	4'b1010:	low_mask = 16'hfc00;
	4'b1011:	low_mask = 16'hf800;
	4'b1100:	low_mask = 16'hf000;
	4'b1101:	low_mask = 16'he000;
	4'b1110:	low_mask = 16'hc000;
	4'b1111:	low_mask = 16'h8000;
endcase



always @*
casez (lsl_selector)
	7'b1??:	lsl_mask =  33'h_1_0000_0000;
	7'b01?:	lsl_mask =  33'h_0_0000_0000;
	7'b001:	lsl_mask = { 1'h_1, low_mask, 16'h_0000};
	7'b000:	lsl_mask = {17'h_1_ffff, low_mask};
endcase



always @*
casez (lsr_selector)
	7'b1??:	lsr_mask =  33'h_1_0000_0000;
	7'b01?:	lsr_mask =  33'h_0_0000_0000;
	7'b000:	lsr_mask = { 1'h_1, bit_swap(low_mask), 16'h_ffff};
	7'b001:	lsr_mask = {17'h_1_0000, bit_swap(low_mask)};
endcase


assign p_r = {rot_prod[30:0], rot_prod[31]};


assign p_l = rot_prod[31:0];


assign ror_out[0] = i_shift_imm_zero ?	i_carry_in :
					p_r[31];


assign ror_out[1] = i_shift_imm_zero ?	i_in[0] :
			shift_nzero ?	p_r[31] :
					i_carry_in;


assign lsl_out[0] = 	p_l[31] & lsl_mask[31];


assign lsl_out[1] = 	shift_nzero ?	p_l[0] & lsl_mask[32]:
					i_carry_in;


assign lsr_out[0] = 	p_r[31] & lsr_mask[31];


assign lsr_out[1] = i_shift_imm_zero ?	i_in[31] :
			shift_nzero ?	p_r[31] & lsr_mask[32]:
					i_carry_in;


assign asr_out[0] = 	i_in[31] ?	i_in[31] :
					p_r[31] & lsr_mask[31] ;


assign asr_out[1] =	shift_over ?	i_in[31] :
			shift_nzero ?	p_r[31] :
					i_carry_in;


assign {o_carry_out, o_out[31]} = i_function == LSL ? lsl_out :
                              i_function == LSR ? lsr_out :
                              i_function == ASR ? asr_out :
                                                  ror_out ;


assign o_out[30:0] =	(p_l[30:0] & lsl_mask[30:0]) |
			(p_r[30:0] & lsr_mask[30:0]) |
			(~lsr_mask[30:0] & {31{asr_sign}});


function [4:0] wrap;
input integer pos;
input integer level;
integer out;
begin
	out = pos - (1 << level);
	wrap = out[4:0];
end
endfunction


function [15:0] bit_swap;
input [15:0] value;
integer i;
begin
	for (i = 0; i < 16; i = i + 1)
		bit_swap[i] = value[15 - i];
end
endfunction

endmodule
module a23_barrel_shift_fpga (

input       [31:0]          i_in,
input                       i_carry_in,
input       [7:0]           i_shift_amount,
input                       i_shift_imm_zero,
input       [1:0]           i_function,

output      [31:0]          o_out,
output                      o_carry_out

);


`include "a23_localparams.v"

wire [31:0] rot_prod;

wire [1:0]  lsl_out;
wire [1:0]  lsr_out;
wire [1:0]  asr_out;
wire [1:0]  ror_out;

reg [32:0]  lsl_mask;
reg [32:0]  lsr_mask;
reg [15:0]  low_mask;

reg [4:0]   shift_amount;

reg [2:0]   lsl_selector;
reg [2:0]   lsr_selector;
reg [3:0]   low_selector;

reg         shift_nzero;
reg         shift_over;
reg         shift_32;
reg         asr_sign;
reg         direction;

wire [31:0] p_r;
wire [31:0] p_l;








always @*
begin
	shift_32 = i_shift_amount == 32;

	shift_over = |i_shift_amount[7:5];

	shift_nzero = |i_shift_amount[7:0];

	shift_amount = i_shift_amount[4:0];

	if (i_shift_imm_zero) begin
		if (i_function == LSR || i_function == ASR) begin




			shift_nzero = 1'b1;
			shift_over = 1'b1;


		end else if (i_function == ROR) begin

			shift_amount[0] = 1'b1;
			shift_nzero = 1'b1;
		end
	end




	case (i_function)
		LSL: low_selector = shift_amount[3:0];
		LSR: low_selector = shift_amount[3:0];
		ASR: low_selector = shift_amount[3:0];
		ROR: low_selector = 4'b0000;
	endcase


	case (i_function)
		LSL: lsl_selector = {shift_32, shift_over, shift_amount[4]};
		LSR: lsl_selector = 3'b0_1_0;
		ASR: lsl_selector = 3'b0_1_0;
		ROR: lsl_selector = 3'b0_1_0;
	endcase


	case (i_function)
		LSL: lsr_selector = 3'b0_1_0;
		LSR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
		ASR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
		ROR: lsr_selector = 3'b0_0_0;
	endcase


	case (i_function)
		LSL: direction = 1'b0;
		LSR: direction = 1'b1;
		ASR: direction = 1'b1;
		ROR: direction = 1'b1;
	endcase


	asr_sign = 1'b0;
	if (i_function == ASR && i_in[31])
		asr_sign = 1'b1;
end



generate
genvar i, j;
	for (i = 0; i < 5; i = i + 1)
	begin : netgen
		wire [31:0] in;
		reg [31:0] out;
		for (j = 0; j < 32; j = j + 1)
		begin : net
			always @*
				out[j] = in[j] & (~shift_amount[i] ^ direction) |
					 in[wrap(j, i)] & (shift_amount[i] ^ direction);
		end
	end


	assign netgen[4].in = i_in;
	for (i = 1; i < 5; i = i + 1)
	begin : router
		assign netgen[i-1].in = netgen[i].out;
	end
endgenerate


assign rot_prod = netgen[0].out;



always @*
case (low_selector)
	4'b0000:	low_mask = 16'hffff;
	4'b0001:	low_mask = 16'hfffe;
	4'b0010:	low_mask = 16'hfffc;
	4'b0011:	low_mask = 16'hfff8;
	4'b0100:	low_mask = 16'hfff0;
	4'b0101:	low_mask = 16'hffe0;
	4'b0110:	low_mask = 16'hffc0;
	4'b0111:	low_mask = 16'hff80;
	4'b1000:	low_mask = 16'hff00;
	4'b1001:	low_mask = 16'hfe00;
	4'b1010:	low_mask = 16'hfc00;
	4'b1011:	low_mask = 16'hf800;
	4'b1100:	low_mask = 16'hf000;
	4'b1101:	low_mask = 16'he000;
	4'b1110:	low_mask = 16'hc000;
	4'b1111:	low_mask = 16'h8000;
endcase



always @*
casez (lsl_selector)
	7'b1??:	lsl_mask =  33'h_1_0000_0000;
	7'b01?:	lsl_mask =  33'h_0_0000_0000;
	7'b001:	lsl_mask = { 1'h_1, low_mask, 16'h_0000};
	7'b000:	lsl_mask = {17'h_1_ffff, low_mask};
endcase



always @*
casez (lsr_selector)
	7'b1??:	lsr_mask =  33'h_1_0000_0000;
	7'b01?:	lsr_mask =  33'h_0_0000_0000;
	7'b000:	lsr_mask = { 1'h_1, bit_swap(low_mask), 16'h_ffff};
	7'b001:	lsr_mask = {17'h_1_0000, bit_swap(low_mask)};
endcase


assign p_r = {rot_prod[30:0], rot_prod[31]};


assign p_l = rot_prod[31:0];


assign ror_out[0] = i_shift_imm_zero ?	i_carry_in :
					p_r[31];


assign ror_out[1] = i_shift_imm_zero ?	i_in[0] :
			shift_nzero ?	p_r[31] :
					i_carry_in;


assign lsl_out[0] = 	p_l[31] & lsl_mask[31];


assign lsl_out[1] = 	shift_nzero ?	p_l[0] & lsl_mask[32]:
					i_carry_in;


assign lsr_out[0] = 	p_r[31] & lsr_mask[31];


assign lsr_out[1] = i_shift_imm_zero ?	i_in[31] :
			shift_nzero ?	p_r[31] & lsr_mask[32]:
					i_carry_in;


assign asr_out[0] = 	i_in[31] ?	i_in[31] :
					p_r[31] & lsr_mask[31] ;


assign asr_out[1] =	shift_over ?	i_in[31] :
			shift_nzero ?	p_r[31] :
					i_carry_in;


assign {o_carry_out, o_out[31]} = i_function == LSL ? lsl_out :
                              i_function == LSR ? lsr_out :
                              i_function == ASR ? asr_out :
                                                  ror_out ;


assign o_out[30:0] =	(p_l[30:0] & lsl_mask[30:0]) |
			(p_r[30:0] & lsr_mask[30:0]) |
			(~lsr_mask[30:0] & {31{asr_sign}});


function [4:0] wrap;
input integer pos;
input integer level;
integer out;
begin
	out = pos - (1 << level);
	wrap = out[4:0];
end
endfunction


function [15:0] bit_swap;
input [15:0] value;
integer i;
begin
	for (i = 0; i < 16; i = i + 1)
		bit_swap[i] = value[15 - i];
end
endfunction

endmodule