data/full_repos/permissive/190426879/extension/source/sc_computer.v
1: b"%Error: data/full_repos/permissive/190426879/extension/source/sc_computer.v:16: Cannot find file containing module: 'sc_cpu'\n sc_cpu  cpu (clock,resetn,inst,memout,pc,wmem,aluout,data);   \n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/190426879/extension/source,data/full_repos/permissive/190426879/sc_cpu\n             data/full_repos/permissive/190426879/extension/source,data/full_repos/permissive/190426879/sc_cpu.v\n             data/full_repos/permissive/190426879/extension/source,data/full_repos/permissive/190426879/sc_cpu.sv\n             sc_cpu\n             sc_cpu.v\n             sc_cpu.sv\n             obj_dir/sc_cpu\n             obj_dir/sc_cpu.v\n             obj_dir/sc_cpu.sv\n%Error: data/full_repos/permissive/190426879/extension/source/sc_computer.v:19: Cannot find file containing module: 'sc_instmem'\n sc_instmem  imem (pc,inst,clock,mem_clk,imem_clk);       \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/190426879/extension/source/sc_computer.v:21: Cannot find file containing module: 'sc_datamem'\n sc_datamem  dmem (aluout,data,memout,wmem,clock,mem_clk,dmem_clk,resetn,\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module  sc_computer ( resetn, clock, mem_clk, pc, inst, aluout, memout,
						in_port0,hex5); 

	input	  [7:0]  in_port0;
	input  resetn,clock,mem_clk;  


	output  [31:0]  pc, inst, aluout, memout;  
	output [6:0] hex5;
	
			
	wire   [31:0]   data;   
	wire   [31:0]	 out_port;
	wire          wmem;  
	wire			  imem_clk,dmem_clk; 
	sc_cpu  cpu (clock,resetn,inst,memout,pc,wmem,aluout,data);   


	sc_instmem  imem (pc,inst,clock,mem_clk,imem_clk);       

	sc_datamem  dmem (aluout,data,memout,wmem,clock,mem_clk,dmem_clk,resetn,
							out_port,in_port0); 				
	sevenseg sevenseg5(out_port[3:0],hex5);

endmodule
module  sc_computer ( resetn, clock, mem_clk, pc, inst, aluout, memout,
						in_port0,hex5);
 

	input	  [7:0]  in_port0;
	input  resetn,clock,mem_clk;  


	output  [31:0]  pc, inst, aluout, memout;  
	output [6:0] hex5;
	
			
	wire   [31:0]   data;   
	wire   [31:0]	 out_port;
	wire          wmem;  
	wire			  imem_clk,dmem_clk; 
	sc_cpu  cpu (clock,resetn,inst,memout,pc,wmem,aluout,data);   


	sc_instmem  imem (pc,inst,clock,mem_clk,imem_clk);       

	sc_datamem  dmem (aluout,data,memout,wmem,clock,mem_clk,dmem_clk,resetn,
							out_port,in_port0); 				
	sevenseg sevenseg5(out_port[3:0],hex5);

endmodule