data/full_repos/permissive/136422019/src/alu.v
1: b"%Error: data/full_repos/permissive/136422019/src/alu.v:38: Cannot find file containing module: 'add32'\nadd32 add1(a_in, b_in, add_out);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/add32\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/add32.v\n             data/full_repos/permissive/136422019/src,data/full_repos/permissive/136422019/add32.sv\n             add32\n             add32.v\n             add32.sv\n             obj_dir/add32\n             obj_dir/add32.v\n             obj_dir/add32.sv\n%Error: data/full_repos/permissive/136422019/src/alu.v:39: Cannot find file containing module: 'sub32'\nsub32 sub1(a_in, b_in, sub_out);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/alu.v:40: Cannot find file containing module: 'mul32'\nmul32 mul1(b_in, a_in, mul_out);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/alu.v:41: Cannot find file containing module: 'div32'\ndiv32 div1(b_in, a_in, div_out, remainder);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/alu.v:42: Cannot find file containing module: 'and32'\nand32 and1(and_out, a_in, b_in);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/alu.v:43: Cannot find file containing module: 'or32'\nor32 or1(or_out, a_in, b_in);\n^~~~\n%Error: data/full_repos/permissive/136422019/src/alu.v:44: Cannot find file containing module: 'shr32'\nshr32 shr1(a_in, b_in[4:0], shr_out);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/alu.v:45: Cannot find file containing module: 'shl32'\nshl32 shl1(a_in, b_in[4:0], shl_out);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/alu.v:46: Cannot find file containing module: 'ror32'\nror32 ror1(a_in, b_in[4:0], ror_out);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/alu.v:47: Cannot find file containing module: 'rol32'\nrol32 rol1(a_in, b_in[4:0], rol_out);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/alu.v:48: Cannot find file containing module: 'neg32'\nneg32 neg1(neg_out, b_in);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/alu.v:49: Cannot find file containing module: 'not32'\nnot32 not1(not_out, b_in);\n^~~~~\n%Error: data/full_repos/permissive/136422019/src/alu.v:50: Cannot find file containing module: 'addOne'\naddOne add2(b_in, PC_out);\n^~~~~~\n%Error: data/full_repos/permissive/136422019/src/alu.v:51: Cannot find file containing module: 'addOne'\naddOne add3(b_in, inc_out);\n^~~~~~\n%Error: Exiting due to 14 error(s)\n"
module alu (
	output reg [63:0] z,
	input wire [31:0] a_in, b_in,
	input wire [4:0] opcode,
	input wire incPC
);

wire [31:0] add_out;
wire [31:0] sub_out;
wire [63:0] mul_out;
wire [31:0] div_out, remainder;
wire [31:0] and_out;
wire [31:0] or_out;
wire [31:0] shr_out;
wire [31:0] shl_out;
wire [31:0] ror_out;
wire [31:0] rol_out;
wire [31:0] neg_out;
wire [31:0] not_out;
wire [31:0] PC_out;
wire [31:0] inc_out;
add32 add1(a_in, b_in, add_out);
sub32 sub1(a_in, b_in, sub_out);
mul32 mul1(b_in, a_in, mul_out);
div32 div1(b_in, a_in, div_out, remainder);
and32 and1(and_out, a_in, b_in);
or32 or1(or_out, a_in, b_in);
shr32 shr1(a_in, b_in[4:0], shr_out);
shl32 shl1(a_in, b_in[4:0], shl_out);
ror32 ror1(a_in, b_in[4:0], ror_out);
rol32 rol1(a_in, b_in[4:0], rol_out);
neg32 neg1(neg_out, b_in);
not32 not1(not_out, b_in);
addOne add2(b_in, PC_out);
addOne add3(b_in, inc_out);



initial begin
	z <= 0;
end

always@(*) begin
		if (incPC == 1) begin
			z[31:0] <= PC_out;
			z[63:32] <= 0;
		end

		else if (opcode == 5'b00101 || opcode == 5'b01101) begin
			z[31:0] <= add_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b00110) begin
			z[31:0] <= sub_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b10000) begin
			z <= mul_out;
		end
		

		else if (opcode == 5'b10001) begin
			z[31:0] <= div_out;
			z[63:32] <= remainder;
		end
		

		else if (opcode == 5'b00111 || opcode == 5'b01110) begin
			z[31:0] <= and_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b01000 || opcode == 5'b01111) begin
			z[31:0] <= or_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b01001) begin
			z[31:0] <= shr_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b01010) begin
			z[31:0] <= shl_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b01011) begin
			z[31:0] <= ror_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b01100) begin
			z[31:0] <= rol_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b10010) begin
			z[31:0] <= neg_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b10011) begin
			z[31:0] <= not_out;
			z[63:32] <= 0;
		end
		

		else if(opcode == 5'b11101) begin
			z[31:0] <= inc_out;
			z[63:32] <= 0;
		end
		
		else
			z[63:0] <= 0;
end
endmodule
module alu (
	output reg [63:0] z,
	input wire [31:0] a_in, b_in,
	input wire [4:0] opcode,
	input wire incPC
);


wire [31:0] add_out;
wire [31:0] sub_out;
wire [63:0] mul_out;
wire [31:0] div_out, remainder;
wire [31:0] and_out;
wire [31:0] or_out;
wire [31:0] shr_out;
wire [31:0] shl_out;
wire [31:0] ror_out;
wire [31:0] rol_out;
wire [31:0] neg_out;
wire [31:0] not_out;
wire [31:0] PC_out;
wire [31:0] inc_out;
add32 add1(a_in, b_in, add_out);
sub32 sub1(a_in, b_in, sub_out);
mul32 mul1(b_in, a_in, mul_out);
div32 div1(b_in, a_in, div_out, remainder);
and32 and1(and_out, a_in, b_in);
or32 or1(or_out, a_in, b_in);
shr32 shr1(a_in, b_in[4:0], shr_out);
shl32 shl1(a_in, b_in[4:0], shl_out);
ror32 ror1(a_in, b_in[4:0], ror_out);
rol32 rol1(a_in, b_in[4:0], rol_out);
neg32 neg1(neg_out, b_in);
not32 not1(not_out, b_in);
addOne add2(b_in, PC_out);
addOne add3(b_in, inc_out);



initial begin
	z <= 0;
end

always@(*) begin
		if (incPC == 1) begin
			z[31:0] <= PC_out;
			z[63:32] <= 0;
		end

		else if (opcode == 5'b00101 || opcode == 5'b01101) begin
			z[31:0] <= add_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b00110) begin
			z[31:0] <= sub_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b10000) begin
			z <= mul_out;
		end
		

		else if (opcode == 5'b10001) begin
			z[31:0] <= div_out;
			z[63:32] <= remainder;
		end
		

		else if (opcode == 5'b00111 || opcode == 5'b01110) begin
			z[31:0] <= and_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b01000 || opcode == 5'b01111) begin
			z[31:0] <= or_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b01001) begin
			z[31:0] <= shr_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b01010) begin
			z[31:0] <= shl_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b01011) begin
			z[31:0] <= ror_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b01100) begin
			z[31:0] <= rol_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b10010) begin
			z[31:0] <= neg_out;
			z[63:32] <= 0;
		end
		

		else if (opcode == 5'b10011) begin
			z[31:0] <= not_out;
			z[63:32] <= 0;
		end
		

		else if(opcode == 5'b11101) begin
			z[31:0] <= inc_out;
			z[63:32] <= 0;
		end
		
		else
			z[63:0] <= 0;
end
endmodule