data/full_repos/permissive/100597706/testing/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n   always # 5 clk = ~ clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[4] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[4] = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[14] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[14] = 1\'b0;\n    ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module AHBLMASTER (
    input HCLK, HRST,

    input [31:0]    HRDATA,
    input           HREADY,


    output [31:0]   HADDR,
    output [1:0]    HSIZE,
    output          HTRANS,
    output [31:0]   HWDATA,
    output          HWRITE,



    input [15:0] INT
);

    localparam IDLE     = 1'b0;
    localparam NONSEQ   = 1'b1;
    
    localparam SZ_BYTE = 2'b00;
    localparam SZ_HW   = 2'b01;
    localparam SZ_W    = 2'b10;



    

	wire[4:0] rfrd, rfrs1, rfrs2;
	wire rfwr;
	wire[31:0] rfD;
	wire[31:0] rfRS1, rfRS2;
	wire simdone;

	wire[31:0] extA, extB;
	wire[31:0] extR;
	wire extStart;
	wire extDone;
	wire[2:0] extFunc3;

	wire IRQ;
	wire [3:0] IRQnum;
	wire [15:0] IRQen;


    rv32_CPU_v2 CPU(
		.clk(HCLK),
		.rst(HRST),
		.bdi(HWDATA), .bdo(HRDATA), .baddr(HADDR), .bsz(HSIZE), .bwr(HWRITE),
		.brdy(HREADY),

		.rfwr(rfwr), .rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2), .rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2),

		.extA(extA), .extB(extB), .extR(extR), .extStart(extStart), .extDone(extDone), .extFunc3(extFunc3),

		.IRQ(IRQ), .IRQnum(IRQnum), .IRQen(IRQen),
		.simdone(simdone)
	);
    

    assign HTRANS = NONSEQ;    

	IntCtrl INTCU(
		.clk(HCLK), .rst(HRST),
		.INT(INT), .IRQen(IRQen),
		.IRQ(IRQ), .IRQnum(IRQnum)
	);

	mul MULEXT (
		.clk(HCLK),
		.rst(HRST),
		.done(extDone),
		.start(extStart),
		.a(extA), .b(extB),
		.p(extR)
	);


    regFile RF (.clk(HCLK), .rst(HRST),
               .rfwr(rfwr),	
               .rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2),
               .rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2)

			   ,.simdone(simdone)
   );
    
      


endmodule
module AHBLMASTER (
    input HCLK, HRST,

    input [31:0]    HRDATA,
    input           HREADY,


    output [31:0]   HADDR,
    output [1:0]    HSIZE,
    output          HTRANS,
    output [31:0]   HWDATA,
    output          HWRITE,



    input [15:0] INT
);


    localparam IDLE     = 1'b0;
    localparam NONSEQ   = 1'b1;
    
    localparam SZ_BYTE = 2'b00;
    localparam SZ_HW   = 2'b01;
    localparam SZ_W    = 2'b10;



    

	wire[4:0] rfrd, rfrs1, rfrs2;
	wire rfwr;
	wire[31:0] rfD;
	wire[31:0] rfRS1, rfRS2;
	wire simdone;

	wire[31:0] extA, extB;
	wire[31:0] extR;
	wire extStart;
	wire extDone;
	wire[2:0] extFunc3;

	wire IRQ;
	wire [3:0] IRQnum;
	wire [15:0] IRQen;


    rv32_CPU_v2 CPU(
		.clk(HCLK),
		.rst(HRST),
		.bdi(HWDATA), .bdo(HRDATA), .baddr(HADDR), .bsz(HSIZE), .bwr(HWRITE),
		.brdy(HREADY),

		.rfwr(rfwr), .rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2), .rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2),

		.extA(extA), .extB(extB), .extR(extR), .extStart(extStart), .extDone(extDone), .extFunc3(extFunc3),

		.IRQ(IRQ), .IRQnum(IRQnum), .IRQen(IRQen),
		.simdone(simdone)
	);
    

    assign HTRANS = NONSEQ;    

	IntCtrl INTCU(
		.clk(HCLK), .rst(HRST),
		.INT(INT), .IRQen(IRQen),
		.IRQ(IRQ), .IRQnum(IRQnum)
	);

	mul MULEXT (
		.clk(HCLK),
		.rst(HRST),
		.done(extDone),
		.start(extStart),
		.a(extA), .b(extB),
		.p(extR)
	);


    regFile RF (.clk(HCLK), .rst(HRST),
               .rfwr(rfwr),	
               .rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2),
               .rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2)

			   ,.simdone(simdone)
   );
    
      


endmodule