data/full_repos/permissive/143638862/rtl/memio/usbfifo/usbfifo.v
data/verilator_xmls/0db58690-c1a5-4e4e-92d9-6c5cc7ab408c.xml
module usbfifo
    (

        input rxf,
        input txe,
        output rd,
        output wr,
        inout [7:0] data_tristate,

        input clock
    );


    reg datavalid = 0;
    reg [7:0] data;

    assign data_tristate = (state == TXDATA || state == TXWRLO) ? data : 8'bZ;
    assign rd = (state == RXRDLO || state == RXDATA) ? 0 : 1;
    assign wr = (state == TXWRLO || state == TXWAIT) ? 0 : 1;




    localparam TIMERDEF = 2;
    reg [1:0] timer = TIMERDEF;

    always @ (posedge clock)
    begin
        if (state == WAIT)
            timer <= (timer > 0) ? timer - 1 : TIMERDEF;
    end




    localparam STATEWIDTH = 3;
    localparam IDLE = 0;
    localparam TXDATA = 1, TXWRLO = 2, TXWAIT = 3, TXWRHI = 4;
    localparam RXRDLO = 5, RXDATA = 6;
    localparam WAIT = 7;
    reg [STATEWIDTH-1:0] state = IDLE;
    reg [STATEWIDTH-1:0] nextstate;
    always @ (posedge clock)
    begin
        state <= nextstate;
    end
    always @ ( * )
    begin
        case (state)
            IDLE:   nextstate = (txe == 0 && datavalid == 1) ? TXDATA : (rxf == 0) ? RXRDLO : state;
            TXDATA: nextstate = TXWRLO;
            TXWRLO: nextstate = TXWAIT;
            TXWAIT: nextstate = TXWRHI;
            TXWRHI: nextstate = WAIT;
            RXRDLO: nextstate = RXDATA;
            RXDATA: nextstate = WAIT;
            WAIT:   nextstate = (timer == 0) ? IDLE : state;
        endcase
    end

    always @ (posedge clock)
    begin
        if (state == RXDATA)
        begin
            datavalid <= 1;
            data <= data_tristate;
        end
        if (state == TXDATA)
            datavalid <= 0;
    end

endmodule
module usbfifo
    (

        input rxf,
        input txe,
        output rd,
        output wr,
        inout [7:0] data_tristate,

        input clock
    );



    reg datavalid = 0;
    reg [7:0] data;

    assign data_tristate = (state == TXDATA || state == TXWRLO) ? data : 8'bZ;
    assign rd = (state == RXRDLO || state == RXDATA) ? 0 : 1;
    assign wr = (state == TXWRLO || state == TXWAIT) ? 0 : 1;




    localparam TIMERDEF = 2;
    reg [1:0] timer = TIMERDEF;

    always @ (posedge clock)
    begin
        if (state == WAIT)
            timer <= (timer > 0) ? timer - 1 : TIMERDEF;
    end




    localparam STATEWIDTH = 3;
    localparam IDLE = 0;
    localparam TXDATA = 1, TXWRLO = 2, TXWAIT = 3, TXWRHI = 4;
    localparam RXRDLO = 5, RXDATA = 6;
    localparam WAIT = 7;
    reg [STATEWIDTH-1:0] state = IDLE;
    reg [STATEWIDTH-1:0] nextstate;
    always @ (posedge clock)
    begin
        state <= nextstate;
    end
    always @ ( * )
    begin
        case (state)
            IDLE:   nextstate = (txe == 0 && datavalid == 1) ? TXDATA : (rxf == 0) ? RXRDLO : state;
            TXDATA: nextstate = TXWRLO;
            TXWRLO: nextstate = TXWAIT;
            TXWAIT: nextstate = TXWRHI;
            TXWRHI: nextstate = WAIT;
            RXRDLO: nextstate = RXDATA;
            RXDATA: nextstate = WAIT;
            WAIT:   nextstate = (timer == 0) ? IDLE : state;
        endcase
    end

    always @ (posedge clock)
    begin
        if (state == RXDATA)
        begin
            datavalid <= 1;
            data <= data_tristate;
        end
        if (state == TXDATA)
            datavalid <= 0;
    end

endmodule