data/full_repos/permissive/127311496/src/v/Cache/ICache.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:93: Cannot find file containing module: 'ICacheTag'\n ICacheTag cacheTag(.clka(clk), .wea(tagWe), .addra(tagAddr), .dina(tagDin), .douta({_tag1, _tag0}),\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/ICacheTag\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/ICacheTag.v\n             data/full_repos/permissive/127311496/src/v/Cache,data/full_repos/permissive/127311496/ICacheTag.sv\n             ICacheTag\n             ICacheTag.v\n             ICacheTag.sv\n             obj_dir/ICacheTag\n             obj_dir/ICacheTag.v\n             obj_dir/ICacheTag.sv\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:95: Cannot find file containing module: 'CacheLRUBit'\n CacheLRUBit cacheLRU(.clk(clk), .req(req), .addr(addrIn[14:6]), .hit({hit1, hit0}), .flag(LRUBit));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:43: Cannot find file containing module: 'ICacheData'\n ICacheData way0Data(.addra(PCIn[14:2]), .clka(~clkCPU), .douta(douta0), .ena(1'b1),\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:45: Cannot find file containing module: 'ICacheData'\n ICacheData way1Data(.addra(PCIn[14:2]), .clka(~clkCPU), .douta(douta1), .ena(1'b1),\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:55: Cannot find file containing module: 'AsyncHandshake'\n AsyncHandshake #(.STB_FREQ(1000 / CLKDDR_PERIOD), .ACK_FREQ(1000 / CLKCPU_PERIOD))\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:59: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) replaceStbCross(.clki(clkCPU), .clko(clkDDR), .i(replaceStb_CPU), .o(replaceStb_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/127311496/src/v/Cache/ICache.v:60: Cannot find file containing module: 'ClockDomainCross'\n ClockDomainCross #(0, 1) replaceBlockCross[26:0](.clki(clkCPU), .clko(clkDDR), .i(replaceBlock_CPU), .o(replaceBlock_DDR));\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module ICacheFSM_CPU(
	input clk, input rst,

	input [31:0] addrIn, input req, output [31:0] dataOut, output stall,
	input [31:0] invalidateAddr, input invalidateReq,

	output reg replaceStb, output reg [26:0] replaceBlock,
	input completeStb,

	input [31:0] douta0, input [31:0] douta1
);
	
	wire [17:0] tag0, tag1;
	wire [17:0] _tag0, _tag1;
	wire LRUBit;
	wire tagWSel;
	
	reg [35:0] tagDin;
	reg [1:0] tagWe;
	
	wire hit0 = (tag0[16:0] == addrIn[31:15]) & tag0[17];
	wire hit1 = (tag1[16:0] == addrIn[31:15]) & tag1[17];
	assign dataOut = hit1? douta1: douta0;
	
	reg [8:0] tagAddr = 0;
	reg [16:0] invalidateTag;
	


	ICacheTag cacheTag(.clka(clk), .wea(tagWe), .addra(tagAddr), .dina(tagDin), .douta({_tag1, _tag0}),
		.addrb(addrIn[14:6]), .doutb({tag1, tag0}));
	CacheLRUBit cacheLRU(.clk(clk), .req(req), .addr(addrIn[14:6]), .hit({hit1, hit0}), .flag(LRUBit));
	
	localparam STATE_IDLE = 2'h0;
	localparam STATE_WAIT = 2'h1;
	localparam STATE_INVALIDATE = 2'h2;
	reg [1:0] state;
	
	assign stall = (req & ~(hit0 | hit1)) | (state == STATE_INVALIDATE);
	assign tagWSel = rst | (state == STATE_INVALIDATE);
	
	always @ (posedge clk)
	if(rst)
	begin
		state <= STATE_IDLE;
		tagAddr <= tagAddr + 1'b1;
		replaceStb <= 1'b0;
	end
	else
	case(state)
	STATE_IDLE: begin
		if(invalidateReq)
		begin
			state <= STATE_INVALIDATE;
			tagAddr <= invalidateAddr[14:6];
			invalidateTag <= invalidateAddr[31:15];
		end
		else if(stall)
		begin
			state <= STATE_WAIT;
			tagAddr <= addrIn[14:6];
			replaceStb <= 1'b1;
			replaceBlock <= {LRUBit, addrIn[31:6]};
		end
	end
	STATE_WAIT: begin
		replaceStb <= 1'b0;
		if(completeStb)
			state <= STATE_IDLE;
	end
	STATE_INVALIDATE: begin
		state <= STATE_IDLE;
	end
	endcase
	
	always @*
	case(state)
	STATE_WAIT: begin

		tagDin <= {2{1'b1, replaceBlock[25:9]}};
		tagWe <= {2{completeStb}} & {replaceBlock[26], ~replaceBlock[26]};
	end
	STATE_INVALIDATE: begin
		tagWe <= 2'b11;
		tagDin[35] <= _tag1[17] & (_tag1[16:0] != invalidateTag);
		tagDin[17] <= _tag0[17] & (_tag0[16:0] != invalidateTag);
		tagDin[34:18] <= _tag1[16:0];
		tagDin[16: 0] <= _tag0[16:0];
	end
	default: begin
		tagDin <= 36'h000040000;
		tagWe <= {2{rst}};
	end
	endcase
	
endmodule
module ICacheFSM_CPU(
	input clk, input rst,

	input [31:0] addrIn, input req, output [31:0] dataOut, output stall,
	input [31:0] invalidateAddr, input invalidateReq,

	output reg replaceStb, output reg [26:0] replaceBlock,
	input completeStb,

	input [31:0] douta0, input [31:0] douta1
);

	
	wire [17:0] tag0, tag1;
	wire [17:0] _tag0, _tag1;
	wire LRUBit;
	wire tagWSel;
	
	reg [35:0] tagDin;
	reg [1:0] tagWe;
	
	wire hit0 = (tag0[16:0] == addrIn[31:15]) & tag0[17];
	wire hit1 = (tag1[16:0] == addrIn[31:15]) & tag1[17];
	assign dataOut = hit1? douta1: douta0;
	
	reg [8:0] tagAddr = 0;
	reg [16:0] invalidateTag;
	


	ICacheTag cacheTag(.clka(clk), .wea(tagWe), .addra(tagAddr), .dina(tagDin), .douta({_tag1, _tag0}),
		.addrb(addrIn[14:6]), .doutb({tag1, tag0}));
	CacheLRUBit cacheLRU(.clk(clk), .req(req), .addr(addrIn[14:6]), .hit({hit1, hit0}), .flag(LRUBit));
	
	localparam STATE_IDLE = 2'h0;
	localparam STATE_WAIT = 2'h1;
	localparam STATE_INVALIDATE = 2'h2;
	reg [1:0] state;
	
	assign stall = (req & ~(hit0 | hit1)) | (state == STATE_INVALIDATE);
	assign tagWSel = rst | (state == STATE_INVALIDATE);
	
	always @ (posedge clk)
	if(rst)
	begin
		state <= STATE_IDLE;
		tagAddr <= tagAddr + 1'b1;
		replaceStb <= 1'b0;
	end
	else
	case(state)
	STATE_IDLE: begin
		if(invalidateReq)
		begin
			state <= STATE_INVALIDATE;
			tagAddr <= invalidateAddr[14:6];
			invalidateTag <= invalidateAddr[31:15];
		end
		else if(stall)
		begin
			state <= STATE_WAIT;
			tagAddr <= addrIn[14:6];
			replaceStb <= 1'b1;
			replaceBlock <= {LRUBit, addrIn[31:6]};
		end
	end
	STATE_WAIT: begin
		replaceStb <= 1'b0;
		if(completeStb)
			state <= STATE_IDLE;
	end
	STATE_INVALIDATE: begin
		state <= STATE_IDLE;
	end
	endcase
	
	always @*
	case(state)
	STATE_WAIT: begin

		tagDin <= {2{1'b1, replaceBlock[25:9]}};
		tagWe <= {2{completeStb}} & {replaceBlock[26], ~replaceBlock[26]};
	end
	STATE_INVALIDATE: begin
		tagWe <= 2'b11;
		tagDin[35] <= _tag1[17] & (_tag1[16:0] != invalidateTag);
		tagDin[17] <= _tag0[17] & (_tag0[16:0] != invalidateTag);
		tagDin[34:18] <= _tag1[16:0];
		tagDin[16: 0] <= _tag0[16:0];
	end
	default: begin
		tagDin <= 36'h000040000;
		tagWe <= {2{rst}};
	end
	endcase
	
endmodule