data/full_repos/permissive/143278/ivltests/br_gh99t.v
 line:6: before: "("
1: b'%Error: data/full_repos/permissive/143278/ivltests/br_gh99t.v:6: Unsupported: Verilog 1995 strength specifiers\nassign (strong1,weak0) value1[3:0] = 4\'b1010;\n        ^~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/br_gh99t.v:6: Unsupported: Verilog 1995 strength specifiers\nassign (strong1,weak0) value1[3:0] = 4\'b1010;\n                ^~~~~\n%Error: data/full_repos/permissive/143278/ivltests/br_gh99t.v:10: Unsupported: Verilog 1995 strength specifiers\nassign (strong1,weak0) value2 = 8\'b00110011;\n        ^~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/br_gh99t.v:10: Unsupported: Verilog 1995 strength specifiers\nassign (strong1,weak0) value2 = 8\'b00110011;\n                ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/br_gh99t.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #2 $display("%b %b", value1, value2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

wire [7:0] value1;
wire [7:0] value2;

assign (strong1,weak0) value1[3:0] = 4'b1010;

nmos buffer[7:0](value2, value1, 1'b1);

assign (strong1,weak0) value2 = 8'b00110011;

initial begin
  #2 $display("%b %b", value1, value2);
  if (value2 === 8'b00111011)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module test();


wire [7:0] value1;
wire [7:0] value2;

assign (strong1,weak0) value1[3:0] = 4'b1010;

nmos buffer[7:0](value2, value1, 1'b1);

assign (strong1,weak0) value2 = 8'b00110011;

initial begin
  #2 $display("%b %b", value1, value2);
  if (value2 === 8'b00111011)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule