data/full_repos/permissive/103257524/sim/sim_memory.v
1: b'%Error: data/full_repos/permissive/103257524/sim/sim_memory.v:36: Cannot find file containing module: \'uart_comm\'\n uart_comm #(.BAUDRATE(5000000)) uart(CLK, RST, send_flag, send_data, recv_flag, recv_data, sendable, recvable, Tx, Rx);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/103257524/sim,data/full_repos/permissive/103257524/uart_comm\n             data/full_repos/permissive/103257524/sim,data/full_repos/permissive/103257524/uart_comm.v\n             data/full_repos/permissive/103257524/sim,data/full_repos/permissive/103257524/uart_comm.sv\n             uart_comm\n             uart_comm.v\n             uart_comm.sv\n             obj_dir/uart_comm\n             obj_dir/uart_comm.v\n             obj_dir/uart_comm.sv\n%Error: data/full_repos/permissive/103257524/sim/sim_memory.v:71: Cannot find file containing module: \'multchan_comm\'\n multchan_comm #(.CHANNEL_BIT(1), .MESSAGE_BIT(72)) comm(\n ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/103257524/sim/sim_memory.v:88: Operator ASSIGNDLY expects 72 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'getDWORD\' generates 32 bits.\n                                                                        : ... In instance sim_memory\n     write_data <= getDWORD(read_data[31:0]);\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
function [15:0] getWORD;
		input [31:0] addr;
		getWORD = {memory[addr+1], memory[addr]};
	endfunction
function [15:0] getWORD;

		input [31:0] addr;
		getWORD = {memory[addr+1], memory[addr]};
	endfunction