data/full_repos/permissive/172908596/Load and store Instruction/alu+cu.v
1: b'%Error: Cannot find file containing module: and\n        ... Looked in:\n             data/full_repos/permissive/172908596/Load/and\n             data/full_repos/permissive/172908596/Load/and.v\n             data/full_repos/permissive/172908596/Load/and.sv\n             and\n             and.v\n             and.sv\n             obj_dir/and\n             obj_dir/and.v\n             obj_dir/and.sv\n%Error: Cannot find file containing module: store\n%Error: Cannot find file containing module: Instruction,data/full_repos/permissive/172908596\n%Error: Cannot find file containing module: data/full_repos/permissive/172908596/Load\n%Error: Cannot find file containing module: Instruction/alu+cu.v\n%Error: Exiting due to 5 error(s)\n'
module alu(a,b,cin,control,result,cout);

	input a,b,cin;
	input [3:0]control;
	output result,cout;
	wire t1,t2;
	wire ain,bin;
	wire sum,slt;
	wire t3,t4;

	assign ain=control[3] ? ~a:a;
	assign bin=control[2] ? ~b:b;
	
	and (t1,ain,bin);
	or (t2,ain,bin);
	FA a0(ain,bin,cin,sum,cout);
	assign slt=~cout;
	
	assign t3 = control[0]?t2:t1;
	assign t4 = control[0]?slt:sum;
	assign result = control[1]?t4:t3;

endmodule
module alu(a,b,cin,control,result,cout);


	input a,b,cin;
	input [3:0]control;
	output result,cout;
	wire t1,t2;
	wire ain,bin;
	wire sum,slt;
	wire t3,t4;

	assign ain=control[3] ? ~a:a;
	assign bin=control[2] ? ~b:b;
	
	and (t1,ain,bin);
	or (t2,ain,bin);
	FA a0(ain,bin,cin,sum,cout);
	assign slt=~cout;
	
	assign t3 = control[0]?t2:t1;
	assign t4 = control[0]?slt:sum;
	assign result = control[1]?t4:t3;

endmodule