data/full_repos/permissive/109846502/main_controller.v
1: b"%Error: data/full_repos/permissive/109846502/main_controller.v:34: syntax error, unexpected ref, expecting IDENTIFIER\nref = 3'd4,\n^~~\n%Error: data/full_repos/permissive/109846502/main_controller.v:87: syntax error, unexpected ref, expecting endcase\n ref:\n ^~~\n%Error: data/full_repos/permissive/109846502/main_controller.v:96: syntax error, unexpected begin, expecting assert or assume or cover or restrict\n begin\n ^~~~~\n%Error: data/full_repos/permissive/109846502/main_controller.v:108: syntax error, unexpected <=, expecting IDENTIFIER\n  idle: nst <= init;\n            ^~\n%Error: data/full_repos/permissive/109846502/main_controller.v:109: syntax error, unexpected <=, expecting IDENTIFIER\n  init: nst <= lcd_finish ? addr : init;\n            ^~\n%Error: data/full_repos/permissive/109846502/main_controller.v:110: syntax error, unexpected <=, expecting IDENTIFIER\n  addr: nst <= addr1;\n            ^~\n%Error: data/full_repos/permissive/109846502/main_controller.v:111: syntax error, unexpected <=, expecting IDENTIFIER\n  addr1: nst <= lcd_finish ? ref : addr1;\n             ^~\n%Error: data/full_repos/permissive/109846502/main_controller.v:113: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n  ref1: nst <= lcd_finish ? addr : ref1;\n        ^~~\n%Error: Cannot continue\n"
module main_controller(
			input rst, clk,
			input lcd_finish,
			output reg mode,
			output reg data_sel, db_sel, lcd_enable, reg_sel,
			output reg [1:0] lcd_cnt
    );
reg [2:0] st, nst;
localparam
idle = 3'd0,
init = 3'd1,
addr = 3'd2,
addr1 = 3'd3,
ref = 3'd4,
ref1 = 3'd5;

localparam
LCD_INIT = 1,
LCD_REF = 0,
REF_DATA_NO = 4;

always @(posedge clk, posedge rst)
begin
	if(rst)
	begin
		st <= idle;

	end
	else
	begin
		st <= nst;
		


	end
end

always @*
begin
lcd_enable = 1'b0;
db_sel = 1'b1;
lcd_cnt = 2'd3;
data_sel = 1'b0;
reg_sel = 1'b0;
data_sel = 1'b0;
mode = LCD_INIT;
	case(st) 
	idle:
	begin
		lcd_enable = 1'b1;
	end
	init: begin
	end
	addr:
	begin
				lcd_enable = 1'b1;
				db_sel = 1'b0;
				lcd_cnt = 2'd0;
	end
	
	addr1:
	begin
		db_sel = 1'b0;
		lcd_cnt = 2'd0;
	end
	
	ref:
	begin
		lcd_enable = 1'b1;
		reg_sel = 1'b1;
		data_sel = 1'b1;
		mode = LCD_REF;
	end
	
	ref1:
	begin
		reg_sel = ~lcd_finish;
		data_sel = 1'b1;
		mode = LCD_REF;
	end
	
	endcase
end

always @* begin
	nst <= idle;
	case(st)
		idle: nst <= init;
		init: nst <= lcd_finish ? addr : init;
		addr: nst <= addr1;
		addr1: nst <= lcd_finish ? ref : addr1;
		ref: 	nst <= ref1;
		ref1: nst <= lcd_finish ? addr : ref1;
	endcase
end

endmodule
module main_controller(
			input rst, clk,
			input lcd_finish,
			output reg mode,
			output reg data_sel, db_sel, lcd_enable, reg_sel,
			output reg [1:0] lcd_cnt
    );

reg [2:0] st, nst;
localparam
idle = 3'd0,
init = 3'd1,
addr = 3'd2,
addr1 = 3'd3,
ref = 3'd4,
ref1 = 3'd5;

localparam
LCD_INIT = 1,
LCD_REF = 0,
REF_DATA_NO = 4;

always @(posedge clk, posedge rst)
begin
	if(rst)
	begin
		st <= idle;

	end
	else
	begin
		st <= nst;
		


	end
end

always @*
begin
lcd_enable = 1'b0;
db_sel = 1'b1;
lcd_cnt = 2'd3;
data_sel = 1'b0;
reg_sel = 1'b0;
data_sel = 1'b0;
mode = LCD_INIT;
	case(st) 
	idle:
	begin
		lcd_enable = 1'b1;
	end
	init: begin
	end
	addr:
	begin
				lcd_enable = 1'b1;
				db_sel = 1'b0;
				lcd_cnt = 2'd0;
	end
	
	addr1:
	begin
		db_sel = 1'b0;
		lcd_cnt = 2'd0;
	end
	
	ref:
	begin
		lcd_enable = 1'b1;
		reg_sel = 1'b1;
		data_sel = 1'b1;
		mode = LCD_REF;
	end
	
	ref1:
	begin
		reg_sel = ~lcd_finish;
		data_sel = 1'b1;
		mode = LCD_REF;
	end
	
	endcase
end

always @* begin
	nst <= idle;
	case(st)
		idle: nst <= init;
		init: nst <= lcd_finish ? addr : init;
		addr: nst <= addr1;
		addr1: nst <= lcd_finish ? ref : addr1;
		ref: 	nst <= ref1;
		ref1: nst <= lcd_finish ? addr : ref1;
	endcase
end

endmodule