data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.v\n             data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new,data/full_repos/permissive/114896735/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:4: Define or directive not defined: \'`ADDR_BUS\'\n    input wire [`ADDR_BUS] addr,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:4: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`ADDR_BUS] addr,\n                         ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:5: Define or directive not defined: \'`INST_BUS\'\n    output reg [`INST_BUS] inst,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:9: Define or directive not defined: \'`BYTE0\'\n    reg [`BYTE0]mem[0:`MEM_SIZE];\n         ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`BYTE0]mem[0:`MEM_SIZE];\n               ^\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:9: Define or directive not defined: \'`MEM_SIZE\'\n    reg [`BYTE0]mem[0:`MEM_SIZE];\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:13: Define or directive not defined: \'`FALSE\'\n            error = `FALSE;\n                    ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:14: Define or directive not defined: \'`NONE_INST\'\n            inst = `NONE_INST;\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:20: Define or directive not defined: \'`MEM_SIZE\'\n            if(addr <= `MEM_SIZE - 9)\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:24: Define or directive not defined: \'`FALSE\'\n                error = `FALSE;\n                        ^~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:26: Define or directive not defined: \'`MEM_SIZE\'\n            else if(addr <= `MEM_SIZE)\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:29: Define or directive not defined: \'`MEM_SIZE\'\n                    `MEM_SIZE - 8:\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:32: Define or directive not defined: \'`BYTE_ZERO\'\n                                    mem[addr + 5], mem[addr + 6], mem[addr + 7], mem[addr + 8], `BYTE_ZERO};\n                                                                                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:34: Define or directive not defined: \'`MEM_SIZE\'\n                    `MEM_SIZE - 7:\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:37: Define or directive not defined: \'`BYTE_ZERO\'\n                                    mem[addr + 5], mem[addr + 6], mem[addr + 7], `BYTE_ZERO, `BYTE_ZERO};\n                                                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:37: Define or directive not defined: \'`BYTE_ZERO\'\n                                    mem[addr + 5], mem[addr + 6], mem[addr + 7], `BYTE_ZERO, `BYTE_ZERO};\n                                                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:39: Define or directive not defined: \'`MEM_SIZE\'\n                    `MEM_SIZE - 6:\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:42: Define or directive not defined: \'`BYTE_ZERO\'\n                                    mem[addr + 5], mem[addr + 6], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:42: Define or directive not defined: \'`BYTE_ZERO\'\n                                    mem[addr + 5], mem[addr + 6], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:42: Define or directive not defined: \'`BYTE_ZERO\'\n                                    mem[addr + 5], mem[addr + 6], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:44: Define or directive not defined: \'`MEM_SIZE\'\n                    `MEM_SIZE - 5:\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:47: Define or directive not defined: \'`BYTE_ZERO\'\n                                    mem[addr + 5], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:47: Define or directive not defined: \'`BYTE_ZERO\'\n                                    mem[addr + 5], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:47: Define or directive not defined: \'`BYTE_ZERO\'\n                                    mem[addr + 5], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:47: Define or directive not defined: \'`BYTE_ZERO\'\n                                    mem[addr + 5], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:49: Define or directive not defined: \'`MEM_SIZE\'\n                    `MEM_SIZE - 4:\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:52: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:52: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:52: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:52: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:52: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:54: Define or directive not defined: \'`MEM_SIZE\'\n                    `MEM_SIZE - 3:\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:56: Define or directive not defined: \'`BYTE_ZERO\'\n                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], `BYTE_ZERO,\n                                                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:57: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:57: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:57: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:57: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:57: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:59: Define or directive not defined: \'`MEM_SIZE\'\n                    `MEM_SIZE - 2:\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:61: Define or directive not defined: \'`BYTE_ZERO\'\n                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], `BYTE_ZERO, `BYTE_ZERO,\n                                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:61: Define or directive not defined: \'`BYTE_ZERO\'\n                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], `BYTE_ZERO, `BYTE_ZERO,\n                                                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:62: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:62: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:62: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:62: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:62: Define or directive not defined: \'`BYTE_ZERO\'\n                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};\n                                                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:64: Define or directive not defined: \'`MEM_SIZE\'\n                    `MEM_SIZE - 1:\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:66: Define or directive not defined: \'`BYTE_ZERO\'\n                            inst = {mem[addr], mem[addr + 1], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO,\n                                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/114896735/y86cpu.srcs/sources_1/new/i_mem.v:66: Define or directive not defined: \'`BYTE_ZERO\'\n                            inst = {mem[addr], mem[addr + 1], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO,\n                                                                          ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module i_mem(
    input wire [`ADDR_BUS] addr,
    output reg [`INST_BUS] inst,
    output reg error
    );
    
    reg [`BYTE0]mem[0:`MEM_SIZE];
    
    initial
        begin
            error = `FALSE;
            inst = `NONE_INST;
            $readmemh("F:/Projects/Verilog/y86cpu/y86cpu.srcs/sim_1/new/insts.data", mem);
        end
    
    always @(*)
        begin
            if(addr <= `MEM_SIZE - 9)
            begin
                inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
                        mem[addr + 5], mem[addr + 6], mem[addr + 7], mem[addr + 8], mem[addr + 9]};
                error = `FALSE;
            end
            else if(addr <= `MEM_SIZE)
            begin
                case(addr)
                    `MEM_SIZE - 8:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
                                    mem[addr + 5], mem[addr + 6], mem[addr + 7], mem[addr + 8], `BYTE_ZERO};
                        end
                    `MEM_SIZE - 7:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
                                    mem[addr + 5], mem[addr + 6], mem[addr + 7], `BYTE_ZERO, `BYTE_ZERO};
                        end
                    `MEM_SIZE - 6:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
                                    mem[addr + 5], mem[addr + 6], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                    `MEM_SIZE - 5:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
                                    mem[addr + 5], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                    `MEM_SIZE - 4:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                    `MEM_SIZE - 3:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], `BYTE_ZERO,
                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                    `MEM_SIZE - 2:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], `BYTE_ZERO, `BYTE_ZERO,
                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                    `MEM_SIZE - 1:
                        begin   
                            inst = {mem[addr], mem[addr + 1], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO,
                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                    default:
                        begin
                            inst = {mem[addr], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO,
                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                endcase
                error = `FALSE;
            end
            else
            begin
                error = `TRUE;
            end
        end
endmodule
module i_mem(
    input wire [`ADDR_BUS] addr,
    output reg [`INST_BUS] inst,
    output reg error
    );

    
    reg [`BYTE0]mem[0:`MEM_SIZE];
    
    initial
        begin
            error = `FALSE;
            inst = `NONE_INST;
            $readmemh("F:/Projects/Verilog/y86cpu/y86cpu.srcs/sim_1/new/insts.data", mem);
        end
    
    always @(*)
        begin
            if(addr <= `MEM_SIZE - 9)
            begin
                inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
                        mem[addr + 5], mem[addr + 6], mem[addr + 7], mem[addr + 8], mem[addr + 9]};
                error = `FALSE;
            end
            else if(addr <= `MEM_SIZE)
            begin
                case(addr)
                    `MEM_SIZE - 8:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
                                    mem[addr + 5], mem[addr + 6], mem[addr + 7], mem[addr + 8], `BYTE_ZERO};
                        end
                    `MEM_SIZE - 7:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
                                    mem[addr + 5], mem[addr + 6], mem[addr + 7], `BYTE_ZERO, `BYTE_ZERO};
                        end
                    `MEM_SIZE - 6:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
                                    mem[addr + 5], mem[addr + 6], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                    `MEM_SIZE - 5:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
                                    mem[addr + 5], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                    `MEM_SIZE - 4:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], mem[addr + 4],
                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                    `MEM_SIZE - 3:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], mem[addr + 3], `BYTE_ZERO,
                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                    `MEM_SIZE - 2:
                        begin
                            inst = {mem[addr], mem[addr + 1], mem[addr + 2], `BYTE_ZERO, `BYTE_ZERO,
                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                    `MEM_SIZE - 1:
                        begin   
                            inst = {mem[addr], mem[addr + 1], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO,
                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                    default:
                        begin
                            inst = {mem[addr], `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO,
                                    `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO, `BYTE_ZERO};
                        end
                endcase
                error = `FALSE;
            end
            else
            begin
                error = `TRUE;
            end
        end
endmodule