data/full_repos/permissive/147974511/uvm/aes_tb_top.sv
 line:1: before: "package"
1: b'%Error: data/full_repos/permissive/147974511/uvm/aes_tb_top.sv:1: Cannot find include file: aes_pkg.sv\n`include "aes_pkg.sv" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147974511/uvm,data/full_repos/permissive/147974511/aes_pkg.sv\n             data/full_repos/permissive/147974511/uvm,data/full_repos/permissive/147974511/aes_pkg.sv.v\n             data/full_repos/permissive/147974511/uvm,data/full_repos/permissive/147974511/aes_pkg.sv.sv\n             aes_pkg.sv\n             aes_pkg.sv.v\n             aes_pkg.sv.sv\n             obj_dir/aes_pkg.sv\n             obj_dir/aes_pkg.sv.v\n             obj_dir/aes_pkg.sv.sv\n%Error: data/full_repos/permissive/147974511/uvm/aes_tb_top.sv:2: Cannot find include file: dut/AES_Encrypt_top.v\n`include "dut/AES_Encrypt_top.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_tb_top.sv:3: Cannot find include file: aes_if.sv\n`include "aes_if.sv" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_tb_top.sv:6: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n        ^~~~~~~\n%Error: data/full_repos/permissive/147974511/uvm/aes_tb_top.sv:33: syntax error, unexpected \'#\'\n  uvm_resource_db#(virtual aes_if)::set\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/147974511/uvm/aes_tb_top.sv:47: Unsupported: Ignoring delay on this delayed statement.\n  #5 vif.sig_clock = ~vif.sig_clock;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module aes_tb_top;
	import uvm_pkg::*;
    import aes_pkg::*;
	

	aes_if vif();



	AES_Encrypt aes(
			.key_byte(vif.in_key_byte),
			.state_byte(vif.in_state_byte),
			.clk(vif.sig_clock),
			.rst(vif.sig_rst),
			.enable(vif.sig_enable),
			.state_out_byte(vif.out_state_byte),
			.load(vif.sig_load),
			.ready(vif.sig_ready)
			);

	initial begin


		uvm_resource_db#(virtual aes_if)::set
			(.scope("ifs"), .name("aes_if"), .val(vif));


		run_test();
	end


	initial begin
		vif.sig_clock <= 1'b1;
	end


	always
		#5 vif.sig_clock = ~vif.sig_clock;
endmodule
module aes_tb_top;

	import uvm_pkg::*;
    import aes_pkg::*;
	

	aes_if vif();



	AES_Encrypt aes(
			.key_byte(vif.in_key_byte),
			.state_byte(vif.in_state_byte),
			.clk(vif.sig_clock),
			.rst(vif.sig_rst),
			.enable(vif.sig_enable),
			.state_out_byte(vif.out_state_byte),
			.load(vif.sig_load),
			.ready(vif.sig_ready)
			);

	initial begin


		uvm_resource_db#(virtual aes_if)::set
			(.scope("ifs"), .name("aes_if"), .val(vif));


		run_test();
	end


	initial begin
		vif.sig_clock <= 1'b1;
	end


	always
		#5 vif.sig_clock = ~vif.sig_clock;
endmodule