data/full_repos/permissive/143278/ivltests/pr1478988.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1478988.v:9: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (test !== 4\'b1_000) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1478988.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (test !== 4\'b0_111) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1478988.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (test !== 4\'b1_000) begin\n      ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [23:20] foo;
   wire [3:0]  test = {foo[22:20] == 3'd0, foo[22:20]};

   initial begin

      foo = 4'b1_000;
      #1 if (test !== 4'b1_000) begin
	 $display("FAILED -- foo=%b, test=%b", foo, test);
	 $finish;
      end

      foo = 4'b0_111;
      #1 if (test !== 4'b0_111) begin
	 $display("FAILED -- foo=%b, test=%b", foo, test);
	 $finish;
      end

      foo = 4'b0_000;
      #1 if (test !== 4'b1_000) begin
	 $display("FAILED -- foo=%b, test=%b", foo, test);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg [23:20] foo;
   wire [3:0]  test = {foo[22:20] == 3'd0, foo[22:20]};

   initial begin

      foo = 4'b1_000;
      #1 if (test !== 4'b1_000) begin
	 $display("FAILED -- foo=%b, test=%b", foo, test);
	 $finish;
      end

      foo = 4'b0_111;
      #1 if (test !== 4'b0_111) begin
	 $display("FAILED -- foo=%b, test=%b", foo, test);
	 $finish;
      end

      foo = 4'b0_000;
      #1 if (test !== 4'b1_000) begin
	 $display("FAILED -- foo=%b, test=%b", foo, test);
	 $finish;
      end

      $display("PASSED");
   end

endmodule