data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/encryption.v
1: b"%Error: data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/encryption.v:79: Cannot find file containing module: 'key_creation'\nkey_creation keyGen(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design,data/full_repos/permissive/217756734/key_creation\n             data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design,data/full_repos/permissive/217756734/key_creation.v\n             data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design,data/full_repos/permissive/217756734/key_creation.sv\n             key_creation\n             key_creation.v\n             key_creation.sv\n             obj_dir/key_creation\n             obj_dir/key_creation.v\n             obj_dir/key_creation.sv\n%Error: data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/encryption.v:105: Cannot find file containing module: 'add_round_key'\n add_round_key AddRoundKeyInitRound(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/encryption.v:114: Cannot find file containing module: 'sub_byte'\n  sub_byte SubByte(\n  ^~~~~~~~\n%Error: data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/encryption.v:121: Cannot find file containing module: 'shift_row'\n  shift_row shiftRow(\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/encryption.v:128: Cannot find file containing module: 'mix_columns'\n  mix_columns #(\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/encryption.v:137: Cannot find file containing module: 'add_round_key'\n  add_round_key AddRoundKey(\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/encryption.v:147: Cannot find file containing module: 'sub_byte'\n sub_byte SubByteLastRound(\n ^~~~~~~~\n%Error: data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/encryption.v:154: Cannot find file containing module: 'shift_row'\n shift_row shiftRowLastRound(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/217756734/Verilog2001/Pipelined_Design/encryption.v:161: Cannot find file containing module: 'add_round_key'\n add_round_key AddRoundKeyLastRound(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module encryption #(


	parameter numRounds = 32
)(
	input  [127:0] inputData,
	input  [127:0] key,
	input clock,
	input inputsLoadedFlag,
	input resetModule,
	output reg [127:0] outputData
);

reg startKeyGenFlag;
reg keyCreatedFlag;

reg [5:0] counterOut;
reg [3:0] state;
reg [4:0] keyGenCounter;

reg [127:0] inputDataIn;


reg startTransition;

reg [3:0] IDLE					= 4'd0;
reg [3:0] KEY_GEN				= 4'd1;
reg [3:0] START_ENCRYPTION = 4'd2;

wire [127:0] roundKey [0:10];
wire [127:0] tempData [0:39];
wire [3:0] counter [0:32];





assign counter[0]  = 1;
assign counter[4]  = 2;
assign counter[8]  = 3;
assign counter[12] = 4;
assign counter[16] = 5;
assign counter[20] = 6;
assign counter[24] = 7;
assign counter[28] = 8;
assign counter[32] = 9;

initial begin

	state = 4'd0;
	keyCreatedFlag = 0;

	startKeyGenFlag = 0;
	keyGenCounter = 5'd0;
	counterOut = 6'd0;
	
	inputDataIn = 128'd0;
	outputData = 128'h0;
	
	startTransition = 1'b0;
end


key_creation keyGen(
	.clock				(clock),
	.startTransition	(startKeyGenFlag),
	.roundKeyInput		(key),
	.roundKeyOutput1	(roundKey[0]),	
	.roundKeyOutput2	(roundKey[1]),
	.roundKeyOutput3	(roundKey[2]),
	.roundKeyOutput4	(roundKey[3]),
	.roundKeyOutput5	(roundKey[4]),
	.roundKeyOutput6	(roundKey[5]),
	.roundKeyOutput7	(roundKey[6]),
	.roundKeyOutput8	(roundKey[7]),
	.roundKeyOutput9	(roundKey[8]),
	.roundKeyOutput10	(roundKey[9]),
	.roundKeyOutput11	(roundKey[10])
);







genvar currentValue;
generate

	add_round_key AddRoundKeyInitRound(
		.inputData 			(inputDataIn),
		.roundKey			(roundKey[0]),
		.startTransition	(startTransition),
		.clock				(clock),
		.outputData  		(tempData[0])
	);

	for (currentValue = 0; currentValue <= numRounds; currentValue = currentValue + 4) begin : EncryptionLoop
		sub_byte SubByte(
			.subByteInput 		(tempData[currentValue]),
			.startTransition	(startTransition),
			.clock				(clock),
			.subByteOutput 	(tempData[currentValue + 1])
		);

		shift_row shiftRow(
			.inputData			(tempData[currentValue + 1]),
			.startTransition	(startTransition),
			.clock				(clock),
			.outputData 		(tempData[currentValue + 2])
		);

		mix_columns #(
		.ENCRYPT 				 (1)
		) MixColumns (
			.inputData			 (tempData[currentValue + 2]),
			.startTransition	 (startTransition),
			.clock				 (clock),
			.outputData 		 (tempData[currentValue + 3])
		);

		add_round_key AddRoundKey(
			.inputData			(tempData[currentValue + 3]),
			.roundKey   		(roundKey[counter[currentValue]]),
			.startTransition	(startTransition),
			.clock				(clock),
			.outputData			(tempData[currentValue + 4])
		);

	end

	sub_byte SubByteLastRound(
		.subByteInput 		(tempData[36]),
		.startTransition	(startTransition),
		.clock				(clock),
		.subByteOutput 	(tempData[37])
	);

	shift_row shiftRowLastRound(
		.inputData			(tempData[37]),
		.startTransition	(startTransition),
		.clock				(clock),
		.outputData			 (tempData[38])
	);

	add_round_key AddRoundKeyLastRound(
		.inputData			(tempData[38]),
		.roundKey  			(roundKey[10]),
		.startTransition	(startTransition),
		.clock				(clock),
		.outputData 		(tempData[39])
	);
endgenerate


always @(posedge clock) begin
	case(state)
	


		IDLE: begin		
			if(inputsLoadedFlag == 1) begin
				if(keyCreatedFlag == 0) begin
					state = KEY_GEN;
				end
			end
		end
		


		KEY_GEN: begin
			startKeyGenFlag = 1'b1;
			if(keyGenCounter == 5'd2) begin
				keyGenCounter = 5'd0;
				startKeyGenFlag = 1'b0;
				keyCreatedFlag = 1'b1;
				state = START_ENCRYPTION;
			end
			keyGenCounter = keyGenCounter + 5'd1;
		end
		



		START_ENCRYPTION: begin
			inputDataIn = inputData;
			startTransition = 1'b1;
			
			if(counterOut <= 31) begin
				counterOut = counterOut + 6'd1;
			end 
			if(counterOut == 32) begin
				outputData = tempData[39];
			end
		end	
		
		default: begin
			state = IDLE;
		end
	endcase

end
endmodule
module encryption #(


	parameter numRounds = 32
)(
	input  [127:0] inputData,
	input  [127:0] key,
	input clock,
	input inputsLoadedFlag,
	input resetModule,
	output reg [127:0] outputData
);


reg startKeyGenFlag;
reg keyCreatedFlag;

reg [5:0] counterOut;
reg [3:0] state;
reg [4:0] keyGenCounter;

reg [127:0] inputDataIn;


reg startTransition;

reg [3:0] IDLE					= 4'd0;
reg [3:0] KEY_GEN				= 4'd1;
reg [3:0] START_ENCRYPTION = 4'd2;

wire [127:0] roundKey [0:10];
wire [127:0] tempData [0:39];
wire [3:0] counter [0:32];





assign counter[0]  = 1;
assign counter[4]  = 2;
assign counter[8]  = 3;
assign counter[12] = 4;
assign counter[16] = 5;
assign counter[20] = 6;
assign counter[24] = 7;
assign counter[28] = 8;
assign counter[32] = 9;

initial begin

	state = 4'd0;
	keyCreatedFlag = 0;

	startKeyGenFlag = 0;
	keyGenCounter = 5'd0;
	counterOut = 6'd0;
	
	inputDataIn = 128'd0;
	outputData = 128'h0;
	
	startTransition = 1'b0;
end


key_creation keyGen(
	.clock				(clock),
	.startTransition	(startKeyGenFlag),
	.roundKeyInput		(key),
	.roundKeyOutput1	(roundKey[0]),	
	.roundKeyOutput2	(roundKey[1]),
	.roundKeyOutput3	(roundKey[2]),
	.roundKeyOutput4	(roundKey[3]),
	.roundKeyOutput5	(roundKey[4]),
	.roundKeyOutput6	(roundKey[5]),
	.roundKeyOutput7	(roundKey[6]),
	.roundKeyOutput8	(roundKey[7]),
	.roundKeyOutput9	(roundKey[8]),
	.roundKeyOutput10	(roundKey[9]),
	.roundKeyOutput11	(roundKey[10])
);







genvar currentValue;
generate

	add_round_key AddRoundKeyInitRound(
		.inputData 			(inputDataIn),
		.roundKey			(roundKey[0]),
		.startTransition	(startTransition),
		.clock				(clock),
		.outputData  		(tempData[0])
	);

	for (currentValue = 0; currentValue <= numRounds; currentValue = currentValue + 4) begin : EncryptionLoop
		sub_byte SubByte(
			.subByteInput 		(tempData[currentValue]),
			.startTransition	(startTransition),
			.clock				(clock),
			.subByteOutput 	(tempData[currentValue + 1])
		);

		shift_row shiftRow(
			.inputData			(tempData[currentValue + 1]),
			.startTransition	(startTransition),
			.clock				(clock),
			.outputData 		(tempData[currentValue + 2])
		);

		mix_columns #(
		.ENCRYPT 				 (1)
		) MixColumns (
			.inputData			 (tempData[currentValue + 2]),
			.startTransition	 (startTransition),
			.clock				 (clock),
			.outputData 		 (tempData[currentValue + 3])
		);

		add_round_key AddRoundKey(
			.inputData			(tempData[currentValue + 3]),
			.roundKey   		(roundKey[counter[currentValue]]),
			.startTransition	(startTransition),
			.clock				(clock),
			.outputData			(tempData[currentValue + 4])
		);

	end

	sub_byte SubByteLastRound(
		.subByteInput 		(tempData[36]),
		.startTransition	(startTransition),
		.clock				(clock),
		.subByteOutput 	(tempData[37])
	);

	shift_row shiftRowLastRound(
		.inputData			(tempData[37]),
		.startTransition	(startTransition),
		.clock				(clock),
		.outputData			 (tempData[38])
	);

	add_round_key AddRoundKeyLastRound(
		.inputData			(tempData[38]),
		.roundKey  			(roundKey[10]),
		.startTransition	(startTransition),
		.clock				(clock),
		.outputData 		(tempData[39])
	);
endgenerate


always @(posedge clock) begin
	case(state)
	


		IDLE: begin		
			if(inputsLoadedFlag == 1) begin
				if(keyCreatedFlag == 0) begin
					state = KEY_GEN;
				end
			end
		end
		


		KEY_GEN: begin
			startKeyGenFlag = 1'b1;
			if(keyGenCounter == 5'd2) begin
				keyGenCounter = 5'd0;
				startKeyGenFlag = 1'b0;
				keyCreatedFlag = 1'b1;
				state = START_ENCRYPTION;
			end
			keyGenCounter = keyGenCounter + 5'd1;
		end
		



		START_ENCRYPTION: begin
			inputDataIn = inputData;
			startTransition = 1'b1;
			
			if(counterOut <= 31) begin
				counterOut = counterOut + 6'd1;
			end 
			if(counterOut == 32) begin
				outputData = tempData[39];
			end
		end	
		
		default: begin
			state = IDLE;
		end
	endcase

end
endmodule