data/full_repos/permissive/191467986/rtl/Register.v
data/verilator_xmls/4c116a0a-480b-4076-a708-b5f2645aceeb.xml
module Register
(
    input                           i_CLOCK,
    inout   [DATA_WIDTH - 1:0]      BUS,
    input                           i_CLEAR,
    input                           i_READ_BUS,
    input                           i_WRITE_BUS,

    output [DATA_WIDTH - 1:0]       o_DATA
);

    parameter DATA_WIDTH = 8;

    reg     [DATA_WIDTH - 1:0]      r_VALUE = 0;

    always @(posedge i_CLOCK, posedge i_CLEAR)
    begin
        if (i_CLEAR)
            r_VALUE <= 0;
        else if(i_READ_BUS)
            r_VALUE <= BUS;
    end

    assign o_DATA   = r_VALUE;
    assign BUS      = (i_WRITE_BUS) ? r_VALUE : {DATA_WIDTH {1'bz}};
endmodule
module Register
(
    input                           i_CLOCK,
    inout   [DATA_WIDTH - 1:0]      BUS,
    input                           i_CLEAR,
    input                           i_READ_BUS,
    input                           i_WRITE_BUS,

    output [DATA_WIDTH - 1:0]       o_DATA
);


    parameter DATA_WIDTH = 8;

    reg     [DATA_WIDTH - 1:0]      r_VALUE = 0;

    always @(posedge i_CLOCK, posedge i_CLEAR)
    begin
        if (i_CLEAR)
            r_VALUE <= 0;
        else if(i_READ_BUS)
            r_VALUE <= BUS;
    end

    assign o_DATA   = r_VALUE;
    assign BUS      = (i_WRITE_BUS) ? r_VALUE : {DATA_WIDTH {1'bz}};
endmodule