data/full_repos/permissive/183345139/common/hba_or_masters.v
data/verilator_xmls/cd8b3b14-d618-4271-9335-570c2b3b9a7f.xml
module hba_or_masters #
(
    parameter integer DBUS_WIDTH = 8,
    parameter integer ADDR_WIDTH = 12
)
(
    input wire [3:0] hba_rnw_master,
    input wire [3:0] hba_select_master,


    input wire [DBUS_WIDTH-1:0] hba_dbus_slave,
    input wire [DBUS_WIDTH-1:0] hba_dbus_master0,
    input wire [DBUS_WIDTH-1:0] hba_dbus_master1,
    input wire [DBUS_WIDTH-1:0] hba_dbus_master2,
    input wire [DBUS_WIDTH-1:0] hba_dbus_master3,

    input wire [ADDR_WIDTH-1:0] hba_abus_master0,
    input wire [ADDR_WIDTH-1:0] hba_abus_master1,
    input wire [ADDR_WIDTH-1:0] hba_abus_master2,
    input wire [ADDR_WIDTH-1:0] hba_abus_master3,

    output wire hba_rnw,
    output wire hba_select,
    output wire [DBUS_WIDTH-1:0] hba_dbus,
    output wire [ADDR_WIDTH-1:0] hba_abus
);



assign hba_rnw = | hba_rnw_master;



assign hba_select = | hba_select_master;



assign hba_dbus = hba_dbus_slave |
        (hba_dbus_master0 | hba_dbus_master1 | hba_dbus_master2 | hba_dbus_master3);


assign hba_abus = (hba_abus_master0 | hba_abus_master1 | hba_abus_master2 | hba_abus_master3);

endmodule
module hba_or_masters #
(
    parameter integer DBUS_WIDTH = 8,
    parameter integer ADDR_WIDTH = 12
)
(
    input wire [3:0] hba_rnw_master,
    input wire [3:0] hba_select_master,


    input wire [DBUS_WIDTH-1:0] hba_dbus_slave,
    input wire [DBUS_WIDTH-1:0] hba_dbus_master0,
    input wire [DBUS_WIDTH-1:0] hba_dbus_master1,
    input wire [DBUS_WIDTH-1:0] hba_dbus_master2,
    input wire [DBUS_WIDTH-1:0] hba_dbus_master3,

    input wire [ADDR_WIDTH-1:0] hba_abus_master0,
    input wire [ADDR_WIDTH-1:0] hba_abus_master1,
    input wire [ADDR_WIDTH-1:0] hba_abus_master2,
    input wire [ADDR_WIDTH-1:0] hba_abus_master3,

    output wire hba_rnw,
    output wire hba_select,
    output wire [DBUS_WIDTH-1:0] hba_dbus,
    output wire [ADDR_WIDTH-1:0] hba_abus
);




assign hba_rnw = | hba_rnw_master;



assign hba_select = | hba_select_master;



assign hba_dbus = hba_dbus_slave |
        (hba_dbus_master0 | hba_dbus_master1 | hba_dbus_master2 | hba_dbus_master3);


assign hba_abus = (hba_abus_master0 | hba_abus_master1 | hba_abus_master2 | hba_abus_master3);

endmodule