data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/general/sim_file_io.svh
 line:11: before: "typedef"
data/verilator_xmls/9a97c5e6-126e-4508-894c-6f3081eab81f.xml
function void writeline(logic [DWIDTH-1:0] word);
    if (FORMAT == HEX)
      $fdisplay(handle, "%x", word);
    else if (FORMAT == DEC)
      $fdisplay(handle, "%d", word);
    else if (FORMAT == OCT)
      $fdisplay(handle, "%o", word);
    else if (FORMAT == BIN)
      $fdisplay(handle, "%b", word);
    else if (FORMAT == DEC)
      $fdisplay(handle, "%g", word);
    else
      $error("Invalid format");
  endfunction
function void writeline(logic [DWIDTH-1:0] word);

    if (FORMAT == HEX)
      $fdisplay(handle, "%x", word);
    else if (FORMAT == DEC)
      $fdisplay(handle, "%d", word);
    else if (FORMAT == OCT)
      $fdisplay(handle, "%o", word);
    else if (FORMAT == BIN)
      $fdisplay(handle, "%b", word);
    else if (FORMAT == DEC)
      $fdisplay(handle, "%g", word);
    else
      $error("Invalid format");
  endfunction