data/full_repos/permissive/169496369/alu_pc.v
data/verilator_xmls/93845f3f-69dd-4206-a61d-d388d4ef375c.xml
module alu_pc(pc, stop, pcnext);
    input [31:0] pc;
    input stop;
    
    output [31:0] pcnext;
    
    assign pcnext = (stop ? pc : (pc + 32'd4));
endmodule
module alu_pc(pc, stop, pcnext);

    input [31:0] pc;
    input stop;
    
    output [31:0] pcnext;
    
    assign pcnext = (stop ? pc : (pc + 32'd4));
endmodule