data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/topenc_decx2.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/topenc_decx2.v:25: Cannot find file containing module: \'encoder128\'\nencoder128 U01(.datain(data_encin),.dataout(enc_out));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl,data/full_repos/permissive/137416811/encoder128\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl,data/full_repos/permissive/137416811/encoder128.v\n             data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl,data/full_repos/permissive/137416811/encoder128.sv\n             encoder128\n             encoder128.v\n             encoder128.sv\n             obj_dir/encoder128\n             obj_dir/encoder128.v\n             obj_dir/encoder128.sv\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/topenc_decx2.v:26: Cannot find file containing module: \'decoder128\'\ndecoder128 U02(.datain(data_encout),.dataout(dataout));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/topenc_decx2.v:28: Cannot find file containing module: \'encoder128\'\nencoder128 U011(.datain(data_encin1),.dataout(enc_out1));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/topenc_decx2.v:29: Cannot find file containing module: \'decoder128\'\ndecoder128 U021(.datain(data_encout1),.dataout(dataout1));\n^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/topenc_decx2.v:39: Operator ASSIGNDLY expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'127\'h0\' generates 127 bits.\n                                                                                                                                      : ... In instance top\n    data_encin <= 127\'h00000;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/topenc_decx2.v:72: Operator ASSIGNDLY expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'127\'h0\' generates 127 bits.\n                                                                                                                                      : ... In instance top\n    data_encin1 <= 127\'h00000;\n                ^~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module top(clock,reset,datain,dataout,datain1,dataout1);


input clock,reset;

input [127:0] datain;
output [127:0] dataout;
                          
input [127:0] datain1;   
output [127:0] dataout1; 
                          
wire [6:0] enc_out;
reg  [127:0] data_encin;
reg  [6:0] data_encout;

wire [6:0] enc_out1;
reg  [127:0] data_encin1;
reg  [6:0] data_encout1;





encoder128 U01(.datain(data_encin),.dataout(enc_out));
decoder128 U02(.datain(data_encout),.dataout(dataout));

encoder128 U011(.datain(data_encin1),.dataout(enc_out1));
decoder128 U021(.datain(data_encout1),.dataout(dataout1));



	always @(posedge clock)
		
		begin
		
			if (reset)
			
				data_encin <= 127'h00000;
				
			else
			
				data_encin <= datain;
				
				
		end
		
		
	always @(posedge clock)
		
		begin
		
			if (reset)
			
				data_encout <= 7'h0;
				
			else
			
				data_encout<= enc_out;
				
				
		end
			
			
			
		always @(posedge clock)
		
		begin
		
			if (reset)
			
				data_encin1 <= 127'h00000;
				
			else
			
				data_encin1 <= datain1;
				
				
		end
		
		
	always @(posedge clock)
		
		begin
		
			if (reset)
			
				data_encout1 <= 7'h0;
				
			else
			
				data_encout1<= enc_out1;
				
				
		end		
			
			
			
			
			
			
			
endmodule
module top(clock,reset,datain,dataout,datain1,dataout1);



input clock,reset;

input [127:0] datain;
output [127:0] dataout;
                          
input [127:0] datain1;   
output [127:0] dataout1; 
                          
wire [6:0] enc_out;
reg  [127:0] data_encin;
reg  [6:0] data_encout;

wire [6:0] enc_out1;
reg  [127:0] data_encin1;
reg  [6:0] data_encout1;





encoder128 U01(.datain(data_encin),.dataout(enc_out));
decoder128 U02(.datain(data_encout),.dataout(dataout));

encoder128 U011(.datain(data_encin1),.dataout(enc_out1));
decoder128 U021(.datain(data_encout1),.dataout(dataout1));



	always @(posedge clock)
		
		begin
		
			if (reset)
			
				data_encin <= 127'h00000;
				
			else
			
				data_encin <= datain;
				
				
		end
		
		
	always @(posedge clock)
		
		begin
		
			if (reset)
			
				data_encout <= 7'h0;
				
			else
			
				data_encout<= enc_out;
				
				
		end
			
			
			
		always @(posedge clock)
		
		begin
		
			if (reset)
			
				data_encin1 <= 127'h00000;
				
			else
			
				data_encin1 <= datain1;
				
				
		end
		
		
	always @(posedge clock)
		
		begin
		
			if (reset)
			
				data_encout1 <= 7'h0;
				
			else
			
				data_encout1<= enc_out1;
				
				
		end		
			
			
			
			
			
			
			
endmodule