data/full_repos/permissive/160924877/analysis/rtl/e203/perips/sirv_plic_top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160924877/analysis/rtl/e203/perips/sirv_plic_top.v:131: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n                                                                                                 : ... In instance sirv_plic_top\nwire [PLIC_IRQ_NUM-1:0] plic_irq_i = { \n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/perips/sirv_plic_top.v:193: Cannot find file containing module: \'sirv_plic_man\'\nsirv_plic_man #(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160924877/analysis/rtl/e203/perips,data/full_repos/permissive/160924877/sirv_plic_man\n             data/full_repos/permissive/160924877/analysis/rtl/e203/perips,data/full_repos/permissive/160924877/sirv_plic_man.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/perips,data/full_repos/permissive/160924877/sirv_plic_man.sv\n             sirv_plic_man\n             sirv_plic_man.v\n             sirv_plic_man.sv\n             obj_dir/sirv_plic_man\n             obj_dir/sirv_plic_man.v\n             obj_dir/sirv_plic_man.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module sirv_plic_top(
  input   clk,
  input   rst_n,

  input                      i_icb_cmd_valid,
  output                     i_icb_cmd_ready,
  input  [32-1:0]            i_icb_cmd_addr, 
  input                      i_icb_cmd_read, 
  input  [32-1:0]            i_icb_cmd_wdata,
  
  output                     i_icb_rsp_valid,
  input                      i_icb_rsp_ready,
  output [32-1:0]            i_icb_rsp_rdata,





















































  output  io_harts_0_0
);

wire plic_irq;
assign io_harts_0_0 = plic_irq;

localparam PLIC_IRQ_NUM = 3;
wire [PLIC_IRQ_NUM-1:0] plic_irq_i = { 


























































                  1'b0 };


sirv_plic_man #(
    .PLIC_PRIO_WIDTH   (3),
    .PLIC_IRQ_NUM      (PLIC_IRQ_NUM),
    .PLIC_IRQ_NUM_LOG2 (6),
    .PLIC_ICB_RSP_FLOP (1),
    .PLIC_IRQ_I_FLOP   (1),
    .PLIC_IRQ_O_FLOP   (1) 
) u_sirv_plic_man(
    .clk              (clk            ),      
    .rst_n            (rst_n          ),

    .icb_cmd_valid  (i_icb_cmd_valid),
    .icb_cmd_addr   (i_icb_cmd_addr[24-1:0] ),
    .icb_cmd_read   (i_icb_cmd_read ),
    .icb_cmd_wdata  (i_icb_cmd_wdata),
    .icb_rsp_ready  (i_icb_rsp_ready),
                    
    .icb_rsp_valid  (i_icb_rsp_valid),
    .icb_cmd_ready  (i_icb_cmd_ready),
    .icb_rsp_rdata  (i_icb_rsp_rdata),

    .plic_irq_i (plic_irq_i),
    .plic_irq_o (plic_irq   ) 
);


endmodule
module sirv_plic_top(
  input   clk,
  input   rst_n,

  input                      i_icb_cmd_valid,
  output                     i_icb_cmd_ready,
  input  [32-1:0]            i_icb_cmd_addr, 
  input                      i_icb_cmd_read, 
  input  [32-1:0]            i_icb_cmd_wdata,
  
  output                     i_icb_rsp_valid,
  input                      i_icb_rsp_ready,
  output [32-1:0]            i_icb_rsp_rdata,





















































  output  io_harts_0_0
);


wire plic_irq;
assign io_harts_0_0 = plic_irq;

localparam PLIC_IRQ_NUM = 3;
wire [PLIC_IRQ_NUM-1:0] plic_irq_i = { 


























































                  1'b0 };


sirv_plic_man #(
    .PLIC_PRIO_WIDTH   (3),
    .PLIC_IRQ_NUM      (PLIC_IRQ_NUM),
    .PLIC_IRQ_NUM_LOG2 (6),
    .PLIC_ICB_RSP_FLOP (1),
    .PLIC_IRQ_I_FLOP   (1),
    .PLIC_IRQ_O_FLOP   (1) 
) u_sirv_plic_man(
    .clk              (clk            ),      
    .rst_n            (rst_n          ),

    .icb_cmd_valid  (i_icb_cmd_valid),
    .icb_cmd_addr   (i_icb_cmd_addr[24-1:0] ),
    .icb_cmd_read   (i_icb_cmd_read ),
    .icb_cmd_wdata  (i_icb_cmd_wdata),
    .icb_rsp_ready  (i_icb_rsp_ready),
                    
    .icb_rsp_valid  (i_icb_rsp_valid),
    .icb_cmd_ready  (i_icb_cmd_ready),
    .icb_rsp_rdata  (i_icb_rsp_rdata),

    .plic_irq_i (plic_irq_i),
    .plic_irq_o (plic_irq   ) 
);


endmodule