data/full_repos/permissive/203650831/hd44780_timer_tb.v
 line:100: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = (clk === 1\'b0);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/203650831/hd44780_timer_tb.v:66: Define or directive not defined: \'`H4_TIMER_BITS\'\n    reg[`H4_TIMER_BITS-1:0] time_len = 0;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer_tb.v:81: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("hd44780_timer_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer_tb.v:82: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, hd44780_timer_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer_tb.v:100: Define or directive not defined: \'`H4_DELAY_100US\'\n        #90 time_len = `H4_DELAY_100US;\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer_tb.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #90 time_len = `H4_DELAY_100US;\n                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #90 time_len = `H4_DELAY_100US;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #10 ststrobe = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #50 ststrobe = 0;        \n        ^\n%Error: data/full_repos/permissive/203650831/hd44780_timer_tb.v:120: Define or directive not defined: \'`H4_DELAY_100US\'\n        #((`H4_DELAY_100US * 10) + 250) time_len = 1;    \n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer_tb.v:120: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n        #((`H4_DELAY_100US * 10) + 250) time_len = 1;    \n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #10 ststrobe = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #20 ststrobe = 0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n        #250 time_len = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n        #10 ststrobe = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n        #10 ststrobe = 0;  \n        ^\n%Error: data/full_repos/permissive/203650831/hd44780_timer_tb.v:132: Define or directive not defined: \'`H4_DELAY_100US\'\n        #100 time_len = `H4_DELAY_100US;\n                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer_tb.v:132: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #100 time_len = `H4_DELAY_100US;\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n        #100 time_len = `H4_DELAY_100US;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n        #10 ststrobe = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n        #10 ststrobe = 0;\n        ^\n%Error: data/full_repos/permissive/203650831/hd44780_timer_tb.v:137: Define or directive not defined: \'`H4_DELAY_100US\'\n        #((`H4_DELAY_100US / 2) * 10) time_len = 7;\n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/203650831/hd44780_timer_tb.v:137: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n        #((`H4_DELAY_100US / 2) * 10) time_len = 7;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n        #10 ststrobe = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #100 ststrobe = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/203650831/hd44780_timer_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #1000 $finish;\n        ^\n%Error: Exiting due to 11 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hd44780_timer_tb;











    reg clk = 1;


    always #5 clk = (clk === 1'b0);


    wire wb_reset;
    wire wb_clk;
    hd44780_syscon syscon(
        .i_clk(clk),
        .RST_O(wb_reset),
        .CLK_O(wb_clk)
        );

    reg[`H4_TIMER_BITS-1:0] time_len = 0;
    reg ststrobe = 0;

    wire tmr_busy;
    hd44780_state_timer stimey(
        .RST_I(wb_reset),
        .CLK_I(wb_clk),
        .DAT_I(time_len),
        .start_strobe(ststrobe),
        .busy(tmr_busy)
        );



    initial begin
        $dumpfile("hd44780_timer_tb.vcd");
        $dumpvars(0, hd44780_timer_tb);
    end






    initial begin









        #90 time_len = `H4_DELAY_100US;
        #10 ststrobe = 1;





        #50 ststrobe = 0;












        #((`H4_DELAY_100US * 10) + 250) time_len = 1;
        #10 ststrobe = 1;
        #20 ststrobe = 0;



        #250 time_len = 0;
        #10 ststrobe = 1;
        #10 ststrobe = 0;



        #100 time_len = `H4_DELAY_100US;
        #10 ststrobe = 1;
        #10 ststrobe = 0;


        #((`H4_DELAY_100US / 2) * 10) time_len = 7;
        #10 ststrobe = 1;

        #100 ststrobe = 0;


        #1000 $finish;
    end


endmodule
module hd44780_timer_tb;












    reg clk = 1;


    always #5 clk = (clk === 1'b0);


    wire wb_reset;
    wire wb_clk;
    hd44780_syscon syscon(
        .i_clk(clk),
        .RST_O(wb_reset),
        .CLK_O(wb_clk)
        );

    reg[`H4_TIMER_BITS-1:0] time_len = 0;
    reg ststrobe = 0;

    wire tmr_busy;
    hd44780_state_timer stimey(
        .RST_I(wb_reset),
        .CLK_I(wb_clk),
        .DAT_I(time_len),
        .start_strobe(ststrobe),
        .busy(tmr_busy)
        );



    initial begin
        $dumpfile("hd44780_timer_tb.vcd");
        $dumpvars(0, hd44780_timer_tb);
    end






    initial begin









        #90 time_len = `H4_DELAY_100US;
        #10 ststrobe = 1;





        #50 ststrobe = 0;












        #((`H4_DELAY_100US * 10) + 250) time_len = 1;
        #10 ststrobe = 1;
        #20 ststrobe = 0;



        #250 time_len = 0;
        #10 ststrobe = 1;
        #10 ststrobe = 0;



        #100 time_len = `H4_DELAY_100US;
        #10 ststrobe = 1;
        #10 ststrobe = 0;


        #((`H4_DELAY_100US / 2) * 10) time_len = 7;
        #10 ststrobe = 1;

        #100 ststrobe = 0;


        #1000 $finish;
    end


endmodule