data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v
 line:48: before: "."
1: b'%Error: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:196: Duplicate declaration of signal: \'scan_done\'\n                                                                             : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire scan_done = dotclk_done;\n       ^~~~~~~~~\n        data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:186: ... Location of original declaration\n   output scan_done,  \n          ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:52: Signal definition not found, creating implicitly: \'clk\'\n           .clk(clk),\n                ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:54: Signal definition not found, creating implicitly: \'ten_us\'\n           .timer_pulse(ten_us));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:60: Signal definition not found, creating implicitly: \'two_ms\'\n           .timer_pulse(two_ms));\n                        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:66: Signal definition not found, creating implicitly: \'one_second\'\n           .timer_pulse(one_second));\n                        ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:76: Signal definition not found, creating implicitly: \'switch_pushed\'\n      .switch_pushed(switch_pushed),     \n                     ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/192010622/src/WF_RGB_dot_matrix_demo.v:105: Signal definition not found, creating implicitly: \'scan_done\'\n     .scan_done(scan_done),\n                ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module fpga_top(
    output wire RGB_CLK_OUT,
    output wire RGB_DOUT,
    output wire RGB_LOAD,
    input  wire WF_BUTTON,
    input  wire WF_CPU1,
    input  wire WF_CPU2,
    input  wire WF_CPU3
);



   wire      cpuin_pa0_toggled;
   reg       cpuin_pa0_d;


   reg         updates;
   reg [15:0]  ram_wr_pixels;
   reg [5:0]   ram_wr_addr;
   reg         ram_wr_en;
   wire [15:0]  ram_rd_pixels;
   wire [5:0]   ram_rd_addr;
   wire [4:0]  random_num;
   wire        colR;
   wire        colG;
   wire        colB;
   reg  [2:0]  cnt;





   wire      clk_en = 1'b1;
    

  SB_HFOSC OSC_i (
        .CLKHFEN(clk_en),
        .CLKHFPU(clk_en),
        .CLKHF(clk));


   defparam OSC_i.CLKHF_DIV = "0b10";


     WF_timer #(.COUNT(119), .EVERY_CLK(1'b1)) ten_usec( 
           .clk(clk),
           .enable(1'b1),
           .timer_pulse(ten_us));
 

     WF_timer #(.COUNT(199)) two_msec(   
           .clk(clk),
           .enable(ten_us),
           .timer_pulse(two_ms));


     WF_timer #(.COUNT(499)) one_sec( 
           .clk(clk),
           .enable(two_ms),
           .timer_pulse(one_second));




    WF_switch_debounce switch_deb1 (
      .clk(clk),
      .sample_en(two_ms),
      .switch_in(WF_BUTTON),
      .switch_out(),
      .switch_pushed(switch_pushed),
      .switch_released()
     );




   always @ (posedge clk)
       cpuin_pa0_d        <= WF_CPU1;

     assign cpuin_pa0_toggled = ~cpuin_pa0_d &&  WF_CPU1 ||
                                 cpuin_pa0_d && ~WF_CPU1;




   WF_bram256x16 dot_memory (
     .clk(clk),
     .wen(ram_wr_en),
     .ren(1'b1),
     .waddr({2'b0,ram_wr_addr}),
     .raddr({2'b0,ram_rd_addr}),
     .wdata(ram_wr_pixels),
     .rdata(ram_rd_pixels));


    WF_RGB_if RGB_if_inst(
     .clk(clk),
     .scan_en(two_ms),
     .scan_done(scan_done),
     .ram_rd_addr(ram_rd_addr),
     .ram_rd_pixels(ram_rd_pixels),
     .CLK_OUT(RGB_CLK_OUT),
     .LOAD(RGB_LOAD),
     .DOUT(RGB_DOUT)
     );






    



     always @ (posedge clk)
       if (two_ms)
         updates <= 1'b0;
       else if (scan_done)
           updates <= 1'b1;
         else if (~WF_CPU2)
           updates <= 1'b0;

     always @ (posedge clk)
       if (updates)
        begin
            ram_wr_addr <= ram_wr_addr + 1;
            ram_wr_pixels <= {1'b0,4'b0,colR, 4'b0,colG,4'b0, colB}; 

            ram_wr_en <= 1'b1;
        end
        else
            ram_wr_en <= 1'b0;

     always @ (posedge clk)
       if (switch_pushed || cpuin_pa0_toggled)
         cnt <= cnt + 1;



     WF_random_5 random5 (
           .clk(clk),
           .enable(two_ms),
    	   .data(random_num));

    assign colR = WF_CPU2 ? cnt[0] : random_num[0];
    assign colG = WF_CPU2 ? cnt[1] : random_num[1];
    assign colB = WF_CPU2 ? cnt[2] : random_num[2];



endmodule
module fpga_top(
    output wire RGB_CLK_OUT,
    output wire RGB_DOUT,
    output wire RGB_LOAD,
    input  wire WF_BUTTON,
    input  wire WF_CPU1,
    input  wire WF_CPU2,
    input  wire WF_CPU3
);




   wire      cpuin_pa0_toggled;
   reg       cpuin_pa0_d;


   reg         updates;
   reg [15:0]  ram_wr_pixels;
   reg [5:0]   ram_wr_addr;
   reg         ram_wr_en;
   wire [15:0]  ram_rd_pixels;
   wire [5:0]   ram_rd_addr;
   wire [4:0]  random_num;
   wire        colR;
   wire        colG;
   wire        colB;
   reg  [2:0]  cnt;





   wire      clk_en = 1'b1;
    

  SB_HFOSC OSC_i (
        .CLKHFEN(clk_en),
        .CLKHFPU(clk_en),
        .CLKHF(clk));


   defparam OSC_i.CLKHF_DIV = "0b10";


     WF_timer #(.COUNT(119), .EVERY_CLK(1'b1)) ten_usec( 
           .clk(clk),
           .enable(1'b1),
           .timer_pulse(ten_us));
 

     WF_timer #(.COUNT(199)) two_msec(   
           .clk(clk),
           .enable(ten_us),
           .timer_pulse(two_ms));


     WF_timer #(.COUNT(499)) one_sec( 
           .clk(clk),
           .enable(two_ms),
           .timer_pulse(one_second));




    WF_switch_debounce switch_deb1 (
      .clk(clk),
      .sample_en(two_ms),
      .switch_in(WF_BUTTON),
      .switch_out(),
      .switch_pushed(switch_pushed),
      .switch_released()
     );




   always @ (posedge clk)
       cpuin_pa0_d        <= WF_CPU1;

     assign cpuin_pa0_toggled = ~cpuin_pa0_d &&  WF_CPU1 ||
                                 cpuin_pa0_d && ~WF_CPU1;




   WF_bram256x16 dot_memory (
     .clk(clk),
     .wen(ram_wr_en),
     .ren(1'b1),
     .waddr({2'b0,ram_wr_addr}),
     .raddr({2'b0,ram_rd_addr}),
     .wdata(ram_wr_pixels),
     .rdata(ram_rd_pixels));


    WF_RGB_if RGB_if_inst(
     .clk(clk),
     .scan_en(two_ms),
     .scan_done(scan_done),
     .ram_rd_addr(ram_rd_addr),
     .ram_rd_pixels(ram_rd_pixels),
     .CLK_OUT(RGB_CLK_OUT),
     .LOAD(RGB_LOAD),
     .DOUT(RGB_DOUT)
     );






    



     always @ (posedge clk)
       if (two_ms)
         updates <= 1'b0;
       else if (scan_done)
           updates <= 1'b1;
         else if (~WF_CPU2)
           updates <= 1'b0;

     always @ (posedge clk)
       if (updates)
        begin
            ram_wr_addr <= ram_wr_addr + 1;
            ram_wr_pixels <= {1'b0,4'b0,colR, 4'b0,colG,4'b0, colB}; 

            ram_wr_en <= 1'b1;
        end
        else
            ram_wr_en <= 1'b0;

     always @ (posedge clk)
       if (switch_pushed || cpuin_pa0_toggled)
         cnt <= cnt + 1;



     WF_random_5 random5 (
           .clk(clk),
           .enable(two_ms),
    	   .data(random_num));

    assign colR = WF_CPU2 ? cnt[0] : random_num[0];
    assign colG = WF_CPU2 ? cnt[1] : random_num[1];
    assign colB = WF_CPU2 ? cnt[2] : random_num[2];



endmodule