data/full_repos/permissive/175100691/gpu/sim/BlockRam.v
 line:4: before: ")"
1: b"%Error: data/full_repos/permissive/175100691/gpu/sim/BlockRam.v:4: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'ADDRESS_WIDTH'\n                                                                 : ... In instance BlockRam\n    #(parameter WORD_WIDTH=32, ADDRESS_WIDTH) \n                               ^~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module BlockRam
    #(parameter WORD_WIDTH=32, ADDRESS_WIDTH) 
(
    input wire clock,


    input wire [ADDRESS_WIDTH-1:0] write_address,
    input wire write,
    input wire [WORD_WIDTH-1:0] write_data,


    input wire [ADDRESS_WIDTH-1:0] read_address,
    output reg [WORD_WIDTH-1:0] read_data
);

    reg [WORD_WIDTH-1:0] memory [2**ADDRESS_WIDTH-1:0];

    always @(posedge clock) begin

        if (write) begin
            memory[write_address] <= write_data;
        end




        read_data <= memory[read_address];
    end

endmodule
module BlockRam
    #(parameter WORD_WIDTH=32, ADDRESS_WIDTH) 
(
    input wire clock,


    input wire [ADDRESS_WIDTH-1:0] write_address,
    input wire write,
    input wire [WORD_WIDTH-1:0] write_data,


    input wire [ADDRESS_WIDTH-1:0] read_address,
    output reg [WORD_WIDTH-1:0] read_data
);


    reg [WORD_WIDTH-1:0] memory [2**ADDRESS_WIDTH-1:0];

    always @(posedge clock) begin

        if (write) begin
            memory[write_address] <= write_data;
        end




        read_data <= memory[read_address];
    end

endmodule