data/full_repos/permissive/188580251/Project4/DM.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-WIDTH: data/full_repos/permissive/188580251/Project4/DM.v:46: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                     : ... In instance DM\n    memory[i] = 7\'h0;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module DM(
    input Clk,
	 input Reset,
    input WE,
	 input [1:0] MemDst,
    input [11:0] A,
    input [31:0] WD,
	 input [31:0] pc,
	 input [31:0] addr,
    output[31:0] RD
    );

	reg [7:0] memory[4095:0];
	integer i;
	parameter w = 2'b00,
				 h = 2'b01,
				 b = 2'b10;

	assign RD = (MemDst == w) ? {memory[A+3],memory[A+2],memory[A+1],memory[A]} :
					(MemDst == h) ? {{16{memory[A+1][7]}},memory[A+1],memory[A]} :
										 {{24{memory[A][7]}},memory[A]};
	
	always @ (posedge Clk) begin
		if(Reset == 1)
			for(i = 0; i < 4095; i = i + 1)
				memory[i] = 7'h0;
		else if(WE == 1) begin
			case(MemDst)
				w:	begin
							{memory[A+3],memory[A+2],memory[A+1],memory[A]} = WD;
							$display("@%h: *%h <= %h",pc, addr,{memory[A+3],memory[A+2],memory[A+1],memory[A]});
						end
				h:	begin
							{memory[A+1],memory[A]} = WD[15:0];
							$display("@%h: *%h <= %h",pc, addr,{memory[A+3],memory[A+2],memory[A+1],memory[A]});
						end
				b:	begin
							memory[A] = WD[7:0];
							$display("@%h: *%h <= %h",pc, addr,{memory[A+3],memory[A+2],memory[A+1],memory[A]});
						end
			endcase
		end
	end

endmodule
module DM(
    input Clk,
	 input Reset,
    input WE,
	 input [1:0] MemDst,
    input [11:0] A,
    input [31:0] WD,
	 input [31:0] pc,
	 input [31:0] addr,
    output[31:0] RD
    );


	reg [7:0] memory[4095:0];
	integer i;
	parameter w = 2'b00,
				 h = 2'b01,
				 b = 2'b10;

	assign RD = (MemDst == w) ? {memory[A+3],memory[A+2],memory[A+1],memory[A]} :
					(MemDst == h) ? {{16{memory[A+1][7]}},memory[A+1],memory[A]} :
										 {{24{memory[A][7]}},memory[A]};
	
	always @ (posedge Clk) begin
		if(Reset == 1)
			for(i = 0; i < 4095; i = i + 1)
				memory[i] = 7'h0;
		else if(WE == 1) begin
			case(MemDst)
				w:	begin
							{memory[A+3],memory[A+2],memory[A+1],memory[A]} = WD;
							$display("@%h: *%h <= %h",pc, addr,{memory[A+3],memory[A+2],memory[A+1],memory[A]});
						end
				h:	begin
							{memory[A+1],memory[A]} = WD[15:0];
							$display("@%h: *%h <= %h",pc, addr,{memory[A+3],memory[A+2],memory[A+1],memory[A]});
						end
				b:	begin
							memory[A] = WD[7:0];
							$display("@%h: *%h <= %h",pc, addr,{memory[A+3],memory[A+2],memory[A+1],memory[A]});
						end
			endcase
		end
	end

endmodule