data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:86: Multiple top level modules\n                                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                     : ... Top module \'b2_mux_2_1_case\'\nmodule b2_mux_2_1_case\n       ^~~~~~~~~~~~~~~\n                                                                                                     : ... Top module \'lab4\'\nmodule lab4\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n                                                                                                 : ... In instance lab4.b2_mux_2_1_comb_incorrect\n    assign y = (sel & d1) | ((~sel) & d0);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/110151336/lab_04/src/2_lab4_hdl_2bit_2in1_mux/lab4.v:9: Operator NOT expects 2 bits on the LHS, but LHS\'s VARREF \'sel\' generates 1 bits.\n                                                                                                 : ... In instance lab4.b2_mux_2_1_comb_incorrect\n    assign y = (sel & d1) | ((~sel) & d0);\n                              ^\n%Error: Exiting due to 3 warning(s)\n'
module b2_mux_2_1_case
(
    input  [1:0] d0,
    input  [1:0] d1,
    input        sel,
    output reg [1:0] y
);
	always@(*)
	begin
		case (sel)
			0: y = d0;
			1: y = d1;
		endcase
	end

endmodule
module b2_mux_2_1_case
(
    input  [1:0] d0,
    input  [1:0] d1,
    input        sel,
    output reg [1:0] y
);

	always@(*)
	begin
		case (sel)
			0: y = d0;
			1: y = d1;
		endcase
	end

endmodule