data/full_repos/permissive/157550807/src/idvr_addsub.v
 line:37: before: ","
1: b"%Error: data/full_repos/permissive/157550807/src/idvr_addsub.v:37: syntax error, unexpected ',', expecting '}'\n    assign O = S[1] == 1'b0 ? adder_o[W-1:0] : {{W-1}{1'b0},adder_o[W]};\n                                                           ^\n%Error: Exiting due to 1 error(s)\n"
module idvr_addsub #(
    parameter W=1
) (
    input  [W-1:0]  I0,
    input  [W-1:0]  I1,
    output [W-1:0]  O,
    input  [3:0]    S
);


    wire adder_i0_s = (S[1] == 1'b0 || S[0] == 1'b1) ? 1'b0 : I0[W-1];
    wire [W:0] adder_i0 = {adder_i0_s,I0};
    wire adder_i1_s = (S[1:0] == 2'b10) ? I1[W-1] : 1'b0;
    wire [W:0] adder_i1 = {adder_i1_s,(S == 4'b0) ? I1 : ~I1};
    wire adder_c    = (S == 4'b0) ? 1'b1 : 1'b0;
    wire [W:0] adder_o = adder_i0 + adder_i1 + adder_c;
    assign O = S[1] == 1'b0 ? adder_o[W-1:0] : {{W-1}{1'b0},adder_o[W]};

endmodule
module idvr_addsub #(
    parameter W=1
) (
    input  [W-1:0]  I0,
    input  [W-1:0]  I1,
    output [W-1:0]  O,
    input  [3:0]    S
);



    wire adder_i0_s = (S[1] == 1'b0 || S[0] == 1'b1) ? 1'b0 : I0[W-1];
    wire [W:0] adder_i0 = {adder_i0_s,I0};
    wire adder_i1_s = (S[1:0] == 2'b10) ? I1[W-1] : 1'b0;
    wire [W:0] adder_i1 = {adder_i1_s,(S == 4'b0) ? I1 : ~I1};
    wire adder_c    = (S == 4'b0) ? 1'b1 : 1'b0;
    wire [W:0] adder_o = adder_i0 + adder_i1 + adder_c;
    assign O = S[1] == 1'b0 ? adder_o[W-1:0] : {{W-1}{1'b0},adder_o[W]};

endmodule