data/full_repos/permissive/190595283/Main.v
 line:321: before: "RegWrite"
1: b'%Error: data/full_repos/permissive/190595283/Main.v:1: Cannot find include file: Modulos/ALU.v\n`include "Modulos/ALU.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/190595283,data/full_repos/permissive/190595283/Modulos/ALU.v\n             data/full_repos/permissive/190595283,data/full_repos/permissive/190595283/Modulos/ALU.v.v\n             data/full_repos/permissive/190595283,data/full_repos/permissive/190595283/Modulos/ALU.v.sv\n             Modulos/ALU.v\n             Modulos/ALU.v.v\n             Modulos/ALU.v.sv\n             obj_dir/Modulos/ALU.v\n             obj_dir/Modulos/ALU.v.v\n             obj_dir/Modulos/ALU.v.sv\n%Error: data/full_repos/permissive/190595283/Main.v:2: Cannot find include file: Modulos/AND.v\n`include "Modulos/AND.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:3: Cannot find include file: Modulos/ControleALU.v\n`include "Modulos/ControleALU.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:4: Cannot find include file: Modulos/Controller.v\n`include "Modulos/Controller.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:5: Cannot find include file: Modulos/Data_Memory.v\n`include "Modulos/Data_Memory.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:6: Cannot find include file: Modulos/Ext_Sinal.v\n`include "Modulos/Ext_Sinal.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:7: Cannot find include file: Modulos/LeftShift2.v\n`include "Modulos/LeftShift2.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:8: Cannot find include file: Modulos/Memoria_instrucoes.v\n`include "Modulos/Memoria_instrucoes.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:9: Cannot find include file: Modulos/MUX.v\n`include "Modulos/MUX.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:10: Cannot find include file: Modulos/PC.v\n`include "Modulos/PC.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:11: Cannot find include file: Modulos/Registradores.v\n`include "Modulos/Registradores.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:12: Cannot find include file: Modulos/Somador.v\n`include "Modulos/Somador.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:13: Cannot find include file: Modulos/Somador4.v\n`include "Modulos/Somador4.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:77: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("MIPS.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/190595283/Main.v:78: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = 0;\n  ^\n%Error: data/full_repos/permissive/190595283/Main.v:135: Unsupported or unknown PLI call: $monitor\n  $monitor("\\nInstrucao: %b\\nSaida PC:  %b\\nSaida ALU: %b\\n",Instrucao,PCOut,ALUResult);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/190595283/Main.v:139: Unsupported: Ignoring delay on this delayed statement.\n #2 PCIn <= NextPC;\n ^\n%Error: Exiting due to 16 error(s), 51 warning(s)\n'
module main();
  reg clk;
  reg [31:0] PCIn = 0;
  wire [31:0] PCOut;
  wire [31:0] Saida_Somador4;
  wire [31:0] Instrucao;
  wire [1:0] branch;
  wire MemRead;
  wire RegDst;
  wire memToReg;
  wire [1:0] ALUOp;
  wire regWrite;
  wire memWrite;
  wire ALUSrc;
  wire [4:0] writeRegister;
  wire [31:0] Read_Data1_Regs_Out;
  wire [31:0] Read_Data2_Regs_Out;
  wire [31:0] writeData;
  wire [31:0] Signal_Extented;
  wire [31:0] ALUIn;
  wire [3:0] OP_ALU_IN;
  wire [31:0] ALUResult;
  wire FlagZero;
  wire [31:0] Read_DataMemory_Out;
  wire [31:0] Left_Shifted2;
  wire [31:0] Somador2_Out;
  wire Door_Out;
  wire [31:0] NextPC;

  PC pc(.clk(clk),.entrada(PCIn),.saida(PCOut));

  Somador4 Soma4(.a(PCOut),.saida(Saida_Somador4));

  Memoria_instrucoes Inst_Mem(.endereco(PCOut),.instrucao(Instrucao));

  Controller controll(.Opcode(Instrucao[31:26]),.RegDst(RegDst),.Branch(branch),.MemRead(MemRead),.MemtoReg(memToReg),.ALUOp(ALUOp),.MemWrite(memWrite),.ALUSrc(ALUSrc),.RegWrite(regWrite));

  MUX_5b mux5b_1(.controle(RegDst),.entrada1(Instrucao[20:16]),.entrada2(Instrucao[15:11]),.saida(writeRegister));

  Registradores Regs(.clk(clk),.RegWrite(regWrite),.ReadReg1(Instrucao[25:21]),.ReadReg2(Instrucao[20:16]),.WriteReg(writeRegister),.WriteData(writeData),.ReadData1(Read_Data1_Regs_Out),.ReadData2(Read_Data2_Regs_Out));

  Ext_Sinal Signal_Extenteder(.entrada(Instrucao[15:0]),.saida(Signal_Extented));

  MUX_32b mux32b_2(.controle(ALUSrc),.entrada1(Read_Data2_Regs_Out),.entrada2(Signal_Extented),.saida(ALUIn));

  ControleALU Control_ALU(.OpCode_ALU(ALUOp),.Func_Code(Instrucao[5:0]),.Controle_ALU(OP_ALU_IN));

  ALU ALU_1(.controle(OP_ALU_IN),.a(Read_Data1_Regs_Out),.b(ALUIn),.zero(FlagZero),.saida(ALUResult));

  Data_Memory Data_Mem(.Clk(clk),.MemWrite(memWrite),.MemRead(MemRead),.Address(ALUResult),.WriteData(Read_Data2_Regs_Out),.ReadData(Read_DataMemory_Out));

  MUX_32b mux32b_3 (.controle(memToReg),.entrada1(ALUResult),.entrada2(Read_DataMemory_Out),.saida(writeData));

  LeftShift2 Left_shift(.entrada(Signal_Extented),.saida(Left_Shifted2));

  Somador ADD_1(.a(Saida_Somador4),.b(Left_Shifted2),.saida(Somador2_Out));

  Door_BNE_BEQ Door1(.branch(branch),.flag(FlagZero),.out(Door_Out));

  MUX_32b mux32b_4(.controle(Door_Out),.entrada1(Saida_Somador4),.entrada2(Somador2_Out),.saida(NextPC));

initial begin
  $dumpfile("MIPS.vcd");
  $dumpvars;
end

initial begin
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
end

initial begin
  $monitor("\nInstrucao: %b\nSaida PC:  %b\nSaida ALU: %b\n",Instrucao,PCOut,ALUResult);
end

always @ (negedge clk) begin
	#2 PCIn <= NextPC;
end
endmodule
module main();

  reg clk;
  reg [31:0] PCIn = 0;
  wire [31:0] PCOut;
  wire [31:0] Saida_Somador4;
  wire [31:0] Instrucao;
  wire [1:0] branch;
  wire MemRead;
  wire RegDst;
  wire memToReg;
  wire [1:0] ALUOp;
  wire regWrite;
  wire memWrite;
  wire ALUSrc;
  wire [4:0] writeRegister;
  wire [31:0] Read_Data1_Regs_Out;
  wire [31:0] Read_Data2_Regs_Out;
  wire [31:0] writeData;
  wire [31:0] Signal_Extented;
  wire [31:0] ALUIn;
  wire [3:0] OP_ALU_IN;
  wire [31:0] ALUResult;
  wire FlagZero;
  wire [31:0] Read_DataMemory_Out;
  wire [31:0] Left_Shifted2;
  wire [31:0] Somador2_Out;
  wire Door_Out;
  wire [31:0] NextPC;

  PC pc(.clk(clk),.entrada(PCIn),.saida(PCOut));

  Somador4 Soma4(.a(PCOut),.saida(Saida_Somador4));

  Memoria_instrucoes Inst_Mem(.endereco(PCOut),.instrucao(Instrucao));

  Controller controll(.Opcode(Instrucao[31:26]),.RegDst(RegDst),.Branch(branch),.MemRead(MemRead),.MemtoReg(memToReg),.ALUOp(ALUOp),.MemWrite(memWrite),.ALUSrc(ALUSrc),.RegWrite(regWrite));

  MUX_5b mux5b_1(.controle(RegDst),.entrada1(Instrucao[20:16]),.entrada2(Instrucao[15:11]),.saida(writeRegister));

  Registradores Regs(.clk(clk),.RegWrite(regWrite),.ReadReg1(Instrucao[25:21]),.ReadReg2(Instrucao[20:16]),.WriteReg(writeRegister),.WriteData(writeData),.ReadData1(Read_Data1_Regs_Out),.ReadData2(Read_Data2_Regs_Out));

  Ext_Sinal Signal_Extenteder(.entrada(Instrucao[15:0]),.saida(Signal_Extented));

  MUX_32b mux32b_2(.controle(ALUSrc),.entrada1(Read_Data2_Regs_Out),.entrada2(Signal_Extented),.saida(ALUIn));

  ControleALU Control_ALU(.OpCode_ALU(ALUOp),.Func_Code(Instrucao[5:0]),.Controle_ALU(OP_ALU_IN));

  ALU ALU_1(.controle(OP_ALU_IN),.a(Read_Data1_Regs_Out),.b(ALUIn),.zero(FlagZero),.saida(ALUResult));

  Data_Memory Data_Mem(.Clk(clk),.MemWrite(memWrite),.MemRead(MemRead),.Address(ALUResult),.WriteData(Read_Data2_Regs_Out),.ReadData(Read_DataMemory_Out));

  MUX_32b mux32b_3 (.controle(memToReg),.entrada1(ALUResult),.entrada2(Read_DataMemory_Out),.saida(writeData));

  LeftShift2 Left_shift(.entrada(Signal_Extented),.saida(Left_Shifted2));

  Somador ADD_1(.a(Saida_Somador4),.b(Left_Shifted2),.saida(Somador2_Out));

  Door_BNE_BEQ Door1(.branch(branch),.flag(FlagZero),.out(Door_Out));

  MUX_32b mux32b_4(.controle(Door_Out),.entrada1(Saida_Somador4),.entrada2(Somador2_Out),.saida(NextPC));

initial begin
  $dumpfile("MIPS.vcd");
  $dumpvars;
end

initial begin
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
  #1	clk = 1;
  #1	clk = 0;
end

initial begin
  $monitor("\nInstrucao: %b\nSaida PC:  %b\nSaida ALU: %b\n",Instrucao,PCOut,ALUResult);
end

always @ (negedge clk) begin
	#2 PCIn <= NextPC;
end
endmodule