data/full_repos/permissive/201275379/src/cpu/cache/CacheLine.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/src/cpu/cache/CacheLine.v:3: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/src/cpu/cache,data/full_repos/permissive/201275379/bus.v\n             data/full_repos/permissive/201275379/src/cpu/cache,data/full_repos/permissive/201275379/bus.v.v\n             data/full_repos/permissive/201275379/src/cpu/cache,data/full_repos/permissive/201275379/bus.v.sv\n             bus.v\n             bus.v.v\n             bus.v.sv\n             obj_dir/bus.v\n             obj_dir/bus.v.v\n             obj_dir/bus.v.sv\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/CacheLine.v:4: Cannot find include file: cache.v\n`include "cache.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/CacheLine.v:21: Define or directive not defined: \'`DATA_BUS\'\n  input [`DATA_BUS]             data_in,\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/CacheLine.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  input [`DATA_BUS]             data_in,\n                  ^\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/CacheLine.v:26: Define or directive not defined: \'`DATA_BUS\'\n  output [`DATA_BUS]            data_out\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/CacheLine.v:32: Define or directive not defined: \'`DATA_BUS\'\n  reg[`DATA_BUS] data[2 ** OFFSET_WIDTH - 1 :0];\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/cache/CacheLine.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`DATA_BUS] data[2 ** OFFSET_WIDTH - 1 :0];\n               ^\n%Error: Exiting due to 7 error(s)\n'
module CacheLine #(parameter
  TAG_WIDTH = 20,
  INDEX_WIDTH = 6,
  OFFSET_WIDTH = 4
) (
  input                         clk,
  input                         rst,  


  input                         write_en,
  input                         valid_in,
  input                         dirty_in,
  input [TAG_WIDTH - 1:0]       tag_in,
  input [OFFSET_WIDTH - 1:0]    offset_in,
  input [3:0]                   data_byte_en,
  input [`DATA_BUS]             data_in,

  output                        valid_out,
  output                        dirty_out,
  output [TAG_WIDTH - 1:0]      tag_out,
  output [`DATA_BUS]            data_out
);

  reg[TAG_WIDTH - 1:0] tag;
  reg valid;
  reg dirty;
  reg[`DATA_BUS] data[2 ** OFFSET_WIDTH - 1 :0];

  assign valid_out = valid;
  assign dirty_out = valid ? dirty : 0;
  assign tag_out = tag;
  assign data_out = valid ? data[offset_in] : 0;

  always @(posedge clk) begin
    if (!rst) begin
      valid <= 0;
      dirty <= 0;
      tag <= 0;
    end
    else if (write_en) begin
      valid <= valid_in;
      dirty <= dirty_in;
      tag <= tag_in;
    end
  end

  always @(posedge clk) begin
    if (write_en) begin
      if (data_byte_en[0]) data[offset_in][7:0] <= data_in[7:0];
      if (data_byte_en[1]) data[offset_in][15:8] <= data_in[15:8];
      if (data_byte_en[2]) data[offset_in][23:16] <= data_in[23:16];
      if (data_byte_en[3]) data[offset_in][31:24] <= data_in[31:24];
    end
  end

endmodule
module CacheLine #(parameter
  TAG_WIDTH = 20,
  INDEX_WIDTH = 6,
  OFFSET_WIDTH = 4
) (
  input                         clk,
  input                         rst,  


  input                         write_en,
  input                         valid_in,
  input                         dirty_in,
  input [TAG_WIDTH - 1:0]       tag_in,
  input [OFFSET_WIDTH - 1:0]    offset_in,
  input [3:0]                   data_byte_en,
  input [`DATA_BUS]             data_in,

  output                        valid_out,
  output                        dirty_out,
  output [TAG_WIDTH - 1:0]      tag_out,
  output [`DATA_BUS]            data_out
);


  reg[TAG_WIDTH - 1:0] tag;
  reg valid;
  reg dirty;
  reg[`DATA_BUS] data[2 ** OFFSET_WIDTH - 1 :0];

  assign valid_out = valid;
  assign dirty_out = valid ? dirty : 0;
  assign tag_out = tag;
  assign data_out = valid ? data[offset_in] : 0;

  always @(posedge clk) begin
    if (!rst) begin
      valid <= 0;
      dirty <= 0;
      tag <= 0;
    end
    else if (write_en) begin
      valid <= valid_in;
      dirty <= dirty_in;
      tag <= tag_in;
    end
  end

  always @(posedge clk) begin
    if (write_en) begin
      if (data_byte_en[0]) data[offset_in][7:0] <= data_in[7:0];
      if (data_byte_en[1]) data[offset_in][15:8] <= data_in[15:8];
      if (data_byte_en[2]) data[offset_in][23:16] <= data_in[23:16];
      if (data_byte_en[3]) data[offset_in][31:24] <= data_in[31:24];
    end
  end

endmodule