data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v
1: b"%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:48: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    .do({open_n18,open_n19,open_n20,led_pad[15]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:48: syntax error, unexpected '(', expecting ')'\n    .do({open_n18,open_n19,open_n20,led_pad[15]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:60: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n35,open_n36,open_n37,led_pad[14]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:60: syntax error, unexpected '(', expecting ')'\n    .do({open_n35,open_n36,open_n37,led_pad[14]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:72: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n52,open_n53,open_n54,led_pad[13]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:72: syntax error, unexpected '(', expecting ')'\n    .do({open_n52,open_n53,open_n54,led_pad[13]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:84: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n69,open_n70,open_n71,led_pad[12]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:84: syntax error, unexpected '(', expecting ')'\n    .do({open_n69,open_n70,open_n71,led_pad[12]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:96: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n86,open_n87,open_n88,led_pad[11]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:96: syntax error, unexpected '(', expecting ')'\n    .do({open_n86,open_n87,open_n88,led_pad[11]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:108: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n103,open_n104,open_n105,led_pad[10]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:108: syntax error, unexpected '(', expecting ')'\n    .do({open_n103,open_n104,open_n105,led_pad[10]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:120: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n120,open_n121,open_n122,led_pad[9]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:120: syntax error, unexpected '(', expecting ')'\n    .do({open_n120,open_n121,open_n122,led_pad[9]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:132: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n137,open_n138,open_n139,led_pad[8]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:132: syntax error, unexpected '(', expecting ')'\n    .do({open_n137,open_n138,open_n139,led_pad[8]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:144: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n154,open_n155,open_n156,led_pad[7]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:144: syntax error, unexpected '(', expecting ')'\n    .do({open_n154,open_n155,open_n156,led_pad[7]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:156: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n171,open_n172,open_n173,led_pad[6]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:156: syntax error, unexpected '(', expecting ')'\n    .do({open_n171,open_n172,open_n173,led_pad[6]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:168: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n188,open_n189,open_n190,led_pad[5]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:168: syntax error, unexpected '(', expecting ')'\n    .do({open_n188,open_n189,open_n190,led_pad[5]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:180: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n205,open_n206,open_n207,led_pad[4]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:180: syntax error, unexpected '(', expecting ')'\n    .do({open_n205,open_n206,open_n207,led_pad[4]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:192: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n222,open_n223,open_n224,led_pad[3]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:192: syntax error, unexpected '(', expecting ')'\n    .do({open_n222,open_n223,open_n224,led_pad[3]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:204: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n239,open_n240,open_n241,led_pad[2]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:204: syntax error, unexpected '(', expecting ')'\n    .do({open_n239,open_n240,open_n241,led_pad[2]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:216: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n256,open_n257,open_n258,led_pad[1]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:216: syntax error, unexpected '(', expecting ')'\n    .do({open_n256,open_n257,open_n258,led_pad[1]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:228: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n273,open_n274,open_n275,led_pad[0]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:228: syntax error, unexpected '(', expecting ')'\n    .do({open_n273,open_n274,open_n275,led_pad[0]}),\n        ^\n%Error: Exiting due to 32 error(s)\n"
module \debounce(N=5)
  (
  clk,
  key,
  rst_n,
  key_pulse
  );

  input clk;
  input [4:0] key;
  input rst_n;
  output [4:0] key_pulse;

  parameter CNT_20MS = 19'b1110101011000000001;
  parameter N = 5;
  wire [18:0] cnt;
  wire [4:0] key_sec;
  wire [4:0] key_sec_pre;
  wire [18:0] n2;
  wire _al_u10_o;
  wire _al_u5_o;
  wire _al_u6_o;
  wire _al_u7_o;
  wire _al_u8_o;
  wire _al_u9_o;
  wire \add0/c11 ;
  wire \add0/c15 ;
  wire \add0/c3 ;
  wire \add0/c7 ;
  wire n1;


  EG_PHY_LSLICE #(




    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUTF0(16'b0000111100000000),
    .INIT_LUTF1(16'b1100000000000000),
    .INIT_LUTG0(16'b0000111100000000),
    .INIT_LUTG1(16'b1100000000000000),
    .LSFMUX0("FUNC5"),
    .LSFMUX1("FUNC5"),
    .MODE("LOGIC"),
    .REG0_REGSET("SET"),
    .REG0_SD("MI"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \_al_u10|reg0_b2  (
    .b({_al_u8_o,open_n2}),
    .c({_al_u9_o,key_sec[2]}),
    .clk(clk),
    .d({_al_u7_o,key_sec_pre[2]}),
    .mi({open_n7,key_sec[2]}),
    .sr(rst_n),
    .f({_al_u10_o,key_pulse[2]}),
    .q({open_n22,key_sec_pre[2]}));
  EG_PHY_LSLICE #(




    .INIT_LUTF0(16'b1100000000000000),
    .INIT_LUTF1(16'b0000000000100000),
    .INIT_LUTG0(16'b1100000000000000),
    .INIT_LUTG1(16'b0000000000100000),
    .LSFMUX0("FUNC5"),
    .LSFMUX1("FUNC5"),
    .MODE("LOGIC"))
    \_al_u5|_al_u11  (
    .a({cnt[12],open_n23}),
    .b({cnt[13],_al_u5_o}),
    .c({cnt[14],_al_u6_o}),
    .d({cnt[15],_al_u10_o}),
    .f({_al_u5_o,n1}));
  EG_PHY_LSLICE #(


    .INIT_LUTF0(16'b0000000000100000),
    .INIT_LUTG0(16'b0000000000100000),
    .LSFMUX0("FUNC5"),
    .MODE("LOGIC"))
    _al_u6 (
    .a({open_n48,cnt[0]}),
    .b({open_n49,cnt[1]}),
    .c({open_n50,cnt[10]}),
    .d({open_n53,cnt[11]}),
    .f({open_n71,_al_u6_o}));

  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0000000000110000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \_al_u7|reg1_b9  (
    .a({open_n77,_al_u10_o}),
    .b({cnt[8],_al_u5_o}),
    .c({cnt[9],_al_u6_o}),
    .clk(clk),
    .d({cnt[7],n2[9]}),
    .sr(rst_n),
    .f({_al_u7_o,open_n91}),
    .q({open_n95,cnt[9]}));

  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0000000000000001),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \_al_u8|reg1_b6  (
    .a({cnt[3],_al_u10_o}),
    .b({cnt[4],_al_u5_o}),
    .c({cnt[5],_al_u6_o}),
    .clk(clk),
    .d({cnt[6],n2[6]}),
    .sr(rst_n),
    .f({_al_u8_o,open_n109}),
    .q({open_n113,cnt[6]}));

  EG_PHY_LSLICE #(




    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUTF0(16'b0111111100000000),
    .INIT_LUTF1(16'b0000000010000000),
    .INIT_LUTG0(16'b0111111100000000),
    .INIT_LUTG1(16'b0000000010000000),
    .LSFMUX0("FUNC5"),
    .LSFMUX1("FUNC5"),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \_al_u9|reg1_b2  (
    .a({cnt[16],_al_u10_o}),
    .b({cnt[17],_al_u5_o}),
    .c({cnt[18],_al_u6_o}),
    .clk(clk),
    .d({cnt[2],n2[2]}),
    .sr(rst_n),
    .f({_al_u9_o,open_n131}),
    .q({open_n135,cnt[2]}));
  EG_PHY_LSLICE #(


    .DEMUX0("E"),
    .DEMUX1("E"),
    .INIT_LUTF0(16'hA55A),
    .INIT_LUTF1(16'hA55A),
    .INIT_LUTG0(16'hC33C),
    .INIT_LUTG1(16'hC33C),
    .LSFMUX0("SUM"),
    .LSFMUX1("SUM"),
    .LSFXMUX0("SUM"),
    .LSFXMUX1("SUM"),
    .MODE("RIPPLE"))
    \add0/u11_al_u34  (
    .a({cnt[13],cnt[11]}),
    .b({cnt[14],cnt[12]}),
    .c(2'b00),
    .d(2'b00),
    .e(2'b00),
    .fci(\add0/c11 ),
    .f({n2[13],n2[11]}),
    .fco(\add0/c15 ),
    .fx({n2[14],n2[12]}));
  EG_PHY_LSLICE #(


    .DEMUX0("E"),
    .DEMUX1("E"),
    .INIT_LUTF0(16'hA55A),
    .INIT_LUTF1(16'hA55A),
    .INIT_LUTG0(16'hC33C),
    .INIT_LUTG1(16'hC33C),
    .LSFMUX0("SUM"),
    .LSFMUX1("SUM"),
    .LSFXMUX0("SUM"),
    .LSFXMUX1("SUM"),
    .MODE("RIPPLE"))
    \add0/u15_al_u35  (
    .a({cnt[17],cnt[15]}),
    .b({cnt[18],cnt[16]}),
    .c(2'b00),
    .d(2'b00),
    .e(2'b00),
    .fci(\add0/c15 ),
    .f({n2[17],n2[15]}),
    .fx({n2[18],n2[16]}));
  EG_PHY_LSLICE #(


    .DEMUX0("E"),
    .DEMUX1("E"),
    .INIT_LUTF0(16'hA55A),
    .INIT_LUTF1(16'hA55A),
    .INIT_LUTG0(16'hC33C),
    .INIT_LUTG1(16'hC33C),
    .LSFMUX0("SUM"),
    .LSFMUX1("SUM"),
    .LSFXMUX0("SUM"),
    .LSFXMUX1("SUM"),
    .MODE("RIPPLE"))
    \add0/u3_al_u32  (
    .a({cnt[5],cnt[3]}),
    .b({cnt[6],cnt[4]}),
    .c(2'b00),
    .d(2'b00),
    .e(2'b00),
    .fci(\add0/c3 ),
    .f({n2[5],n2[3]}),
    .fco(\add0/c7 ),
    .fx({n2[6],n2[4]}));
  EG_PHY_LSLICE #(


    .DEMUX0("E"),
    .DEMUX1("E"),
    .INIT_LUTF0(16'hA55A),
    .INIT_LUTF1(16'hA55A),
    .INIT_LUTG0(16'hC33C),
    .INIT_LUTG1(16'hC33C),
    .LSFMUX0("SUM"),
    .LSFMUX1("SUM"),
    .LSFXMUX0("SUM"),
    .LSFXMUX1("SUM"),
    .MODE("RIPPLE"))
    \add0/u7_al_u33  (
    .a({cnt[9],cnt[7]}),
    .b({cnt[10],cnt[8]}),
    .c(2'b00),
    .d(2'b00),
    .e(2'b00),
    .fci(\add0/c7 ),
    .f({n2[9],n2[7]}),
    .fco(\add0/c11 ),
    .fx({n2[10],n2[8]}));
  EG_PHY_LSLICE #(


    .DEMUX0("E"),
    .DEMUX1("E"),
    .INIT_LUTF0(16'h000A),
    .INIT_LUTF1(16'hA55A),
    .INIT_LUTG0(16'hC33C),
    .INIT_LUTG1(16'hC33C),
    .LSFMUX0("SUM"),
    .LSFMUX1("SUM"),
    .LSFXMUX0("SUM"),
    .LSFXMUX1("SUM"),
    .MODE("RIPPLE"))
    \add0/ucin_al_u31  (
    .a({cnt[1],1'b0}),
    .b({cnt[2],cnt[0]}),
    .c(2'b00),
    .d(2'b01),
    .e(2'b01),
    .f({n2[1],open_n226}),
    .fco(\add0/c3 ),
    .fx({n2[2],n2[0]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0000111100000000),
    .INIT_LUT1(16'b0000111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("SET"),
    .REG0_SD("MI"),
    .REG1_REGSET("SET"),
    .REG1_SD("MI"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg0_b0|reg0_b4  (
    .c({key_sec[0],key_sec[4]}),
    .clk(clk),
    .d({key_sec_pre[0],key_sec_pre[4]}),
    .mi({key_sec[0],key_sec[4]}),
    .sr(rst_n),
    .f({key_pulse[0],key_pulse[4]}),
    .q({key_sec_pre[0],key_sec_pre[4]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0000111100000000),
    .INIT_LUT1(16'b0000111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("SET"),
    .REG0_SD("MI"),
    .REG1_REGSET("SET"),
    .REG1_SD("MI"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg0_b1|reg0_b3  (
    .c({key_sec[1],key_sec[3]}),
    .clk(clk),
    .d({key_sec_pre[1],key_sec_pre[3]}),
    .mi({key_sec[1],key_sec[3]}),
    .sr(rst_n),
    .f({key_pulse[1],key_pulse[3]}),
    .q({key_sec_pre[1],key_sec_pre[3]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0111111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b0|reg1_b8  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[0],n2[8]}),
    .sr(rst_n),
    .q({cnt[0],cnt[8]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0111111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b10|reg1_b7  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[10],n2[7]}),
    .sr(rst_n),
    .q({cnt[10],cnt[7]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0111111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b11|reg1_b5  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[11],n2[5]}),
    .sr(rst_n),
    .q({cnt[11],cnt[5]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0111111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b12|reg1_b4  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[12],n2[4]}),
    .sr(rst_n),
    .q({cnt[12],cnt[4]}));


  EG_PHY_LSLICE #(




    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUTF0(16'b0111111100000000),
    .INIT_LUTF1(16'b0111111100000000),
    .INIT_LUTG0(16'b0111111100000000),
    .INIT_LUTG1(16'b0111111100000000),
    .LSFMUX0("FUNC5"),
    .LSFMUX1("FUNC5"),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b13|reg1_b3  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[13],n2[3]}),
    .sr(rst_n),
    .q({cnt[13],cnt[3]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0111111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b14|reg1_b18  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[14],n2[18]}),
    .sr(rst_n),
    .q({cnt[14],cnt[18]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0111111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b15|reg1_b17  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[15],n2[17]}),
    .sr(rst_n),
    .q({cnt[15],cnt[17]}));


  EG_PHY_LSLICE #(




    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUTF0(16'b0111111100000000),
    .INIT_LUTF1(16'b0111111100000000),
    .INIT_LUTG0(16'b0111111100000000),
    .INIT_LUTG1(16'b0111111100000000),
    .LSFMUX0("FUNC5"),
    .LSFMUX1("FUNC5"),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b1|reg1_b16  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[1],n2[16]}),
    .sr(rst_n),
    .q({cnt[1],cnt[16]}));
  EG_PHY_PAD #(




    .IDDRPIPEMODE("NONE"),
    .INCEMUX("CE"),
    .INPCLKMUX("CLK"),
    .INRSTMUX("INV"),
    .IN_DFFMODE("FF"),
    .IN_REGSET("SET"),
    .IOTYPE("LVCMOS25"),
    .MODE("IN"),
    .SRMODE("ASYNC"),
    .TSMUX("1"))
    reg2_b0_IN (
    .ce(n1),
    .ipad(key[0]),
    .ipclk(clk),
    .rst(rst_n),
    .diq({open_n426,open_n427,open_n428,key_sec[0]}));
  EG_PHY_PAD #(




    .IDDRPIPEMODE("NONE"),
    .INCEMUX("CE"),
    .INPCLKMUX("CLK"),
    .INRSTMUX("INV"),
    .IN_DFFMODE("FF"),
    .IN_REGSET("SET"),
    .IOTYPE("LVCMOS25"),
    .MODE("IN"),
    .SRMODE("ASYNC"),
    .TSMUX("1"))
    reg2_b1_IN (
    .ce(n1),
    .ipad(key[1]),
    .ipclk(clk),
    .rst(rst_n),
    .diq({open_n440,open_n441,open_n442,key_sec[1]}));
  EG_PHY_PAD #(




    .IDDRPIPEMODE("NONE"),
    .INCEMUX("CE"),
    .INPCLKMUX("CLK"),
    .INRSTMUX("INV"),
    .IN_DFFMODE("FF"),
    .IN_REGSET("SET"),
    .IOTYPE("LVCMOS25"),
    .MODE("IN"),
    .SRMODE("ASYNC"),
    .TSMUX("1"))
    reg2_b2_IN (
    .ce(n1),
    .ipad(key[2]),
    .ipclk(clk),
    .rst(rst_n),
    .diq({open_n454,open_n455,open_n456,key_sec[2]}));
  EG_PHY_PAD #(




    .IDDRPIPEMODE("NONE"),
    .INCEMUX("CE"),
    .INPCLKMUX("CLK"),
    .INRSTMUX("INV"),
    .IN_DFFMODE("FF"),
    .IN_REGSET("SET"),
    .IOTYPE("LVCMOS25"),
    .MODE("IN"),
    .SRMODE("ASYNC"),
    .TSMUX("1"))
    reg2_b3_IN (
    .ce(n1),
    .ipad(key[3]),
    .ipclk(clk),
    .rst(rst_n),
    .diq({open_n468,open_n469,open_n470,key_sec[3]}));
  EG_PHY_PAD #(




    .IDDRPIPEMODE("NONE"),
    .INCEMUX("CE"),
    .INPCLKMUX("CLK"),
    .INRSTMUX("INV"),
    .IN_DFFMODE("FF"),
    .IN_REGSET("SET"),
    .IOTYPE("LVCMOS25"),
    .MODE("IN"),
    .SRMODE("ASYNC"),
    .TSMUX("1"))
    reg2_b4_IN (
    .ce(n1),
    .ipad(key[4]),
    .ipclk(clk),
    .rst(rst_n),
    .diq({open_n482,open_n483,open_n484,key_sec[4]}));

endmodule
module \debounce(N=5)
  (
  clk,
  key,
  rst_n,
  key_pulse
  );


  input clk;
  input [4:0] key;
  input rst_n;
  output [4:0] key_pulse;

  parameter CNT_20MS = 19'b1110101011000000001;
  parameter N = 5;
  wire [18:0] cnt;
  wire [4:0] key_sec;
  wire [4:0] key_sec_pre;
  wire [18:0] n2;
  wire _al_u10_o;
  wire _al_u5_o;
  wire _al_u6_o;
  wire _al_u7_o;
  wire _al_u8_o;
  wire _al_u9_o;
  wire \add0/c11 ;
  wire \add0/c15 ;
  wire \add0/c3 ;
  wire \add0/c7 ;
  wire n1;


  EG_PHY_LSLICE #(




    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUTF0(16'b0000111100000000),
    .INIT_LUTF1(16'b1100000000000000),
    .INIT_LUTG0(16'b0000111100000000),
    .INIT_LUTG1(16'b1100000000000000),
    .LSFMUX0("FUNC5"),
    .LSFMUX1("FUNC5"),
    .MODE("LOGIC"),
    .REG0_REGSET("SET"),
    .REG0_SD("MI"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \_al_u10|reg0_b2  (
    .b({_al_u8_o,open_n2}),
    .c({_al_u9_o,key_sec[2]}),
    .clk(clk),
    .d({_al_u7_o,key_sec_pre[2]}),
    .mi({open_n7,key_sec[2]}),
    .sr(rst_n),
    .f({_al_u10_o,key_pulse[2]}),
    .q({open_n22,key_sec_pre[2]}));
  EG_PHY_LSLICE #(




    .INIT_LUTF0(16'b1100000000000000),
    .INIT_LUTF1(16'b0000000000100000),
    .INIT_LUTG0(16'b1100000000000000),
    .INIT_LUTG1(16'b0000000000100000),
    .LSFMUX0("FUNC5"),
    .LSFMUX1("FUNC5"),
    .MODE("LOGIC"))
    \_al_u5|_al_u11  (
    .a({cnt[12],open_n23}),
    .b({cnt[13],_al_u5_o}),
    .c({cnt[14],_al_u6_o}),
    .d({cnt[15],_al_u10_o}),
    .f({_al_u5_o,n1}));
  EG_PHY_LSLICE #(


    .INIT_LUTF0(16'b0000000000100000),
    .INIT_LUTG0(16'b0000000000100000),
    .LSFMUX0("FUNC5"),
    .MODE("LOGIC"))
    _al_u6 (
    .a({open_n48,cnt[0]}),
    .b({open_n49,cnt[1]}),
    .c({open_n50,cnt[10]}),
    .d({open_n53,cnt[11]}),
    .f({open_n71,_al_u6_o}));

  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0000000000110000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \_al_u7|reg1_b9  (
    .a({open_n77,_al_u10_o}),
    .b({cnt[8],_al_u5_o}),
    .c({cnt[9],_al_u6_o}),
    .clk(clk),
    .d({cnt[7],n2[9]}),
    .sr(rst_n),
    .f({_al_u7_o,open_n91}),
    .q({open_n95,cnt[9]}));

  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0000000000000001),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \_al_u8|reg1_b6  (
    .a({cnt[3],_al_u10_o}),
    .b({cnt[4],_al_u5_o}),
    .c({cnt[5],_al_u6_o}),
    .clk(clk),
    .d({cnt[6],n2[6]}),
    .sr(rst_n),
    .f({_al_u8_o,open_n109}),
    .q({open_n113,cnt[6]}));

  EG_PHY_LSLICE #(




    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUTF0(16'b0111111100000000),
    .INIT_LUTF1(16'b0000000010000000),
    .INIT_LUTG0(16'b0111111100000000),
    .INIT_LUTG1(16'b0000000010000000),
    .LSFMUX0("FUNC5"),
    .LSFMUX1("FUNC5"),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \_al_u9|reg1_b2  (
    .a({cnt[16],_al_u10_o}),
    .b({cnt[17],_al_u5_o}),
    .c({cnt[18],_al_u6_o}),
    .clk(clk),
    .d({cnt[2],n2[2]}),
    .sr(rst_n),
    .f({_al_u9_o,open_n131}),
    .q({open_n135,cnt[2]}));
  EG_PHY_LSLICE #(


    .DEMUX0("E"),
    .DEMUX1("E"),
    .INIT_LUTF0(16'hA55A),
    .INIT_LUTF1(16'hA55A),
    .INIT_LUTG0(16'hC33C),
    .INIT_LUTG1(16'hC33C),
    .LSFMUX0("SUM"),
    .LSFMUX1("SUM"),
    .LSFXMUX0("SUM"),
    .LSFXMUX1("SUM"),
    .MODE("RIPPLE"))
    \add0/u11_al_u34  (
    .a({cnt[13],cnt[11]}),
    .b({cnt[14],cnt[12]}),
    .c(2'b00),
    .d(2'b00),
    .e(2'b00),
    .fci(\add0/c11 ),
    .f({n2[13],n2[11]}),
    .fco(\add0/c15 ),
    .fx({n2[14],n2[12]}));
  EG_PHY_LSLICE #(


    .DEMUX0("E"),
    .DEMUX1("E"),
    .INIT_LUTF0(16'hA55A),
    .INIT_LUTF1(16'hA55A),
    .INIT_LUTG0(16'hC33C),
    .INIT_LUTG1(16'hC33C),
    .LSFMUX0("SUM"),
    .LSFMUX1("SUM"),
    .LSFXMUX0("SUM"),
    .LSFXMUX1("SUM"),
    .MODE("RIPPLE"))
    \add0/u15_al_u35  (
    .a({cnt[17],cnt[15]}),
    .b({cnt[18],cnt[16]}),
    .c(2'b00),
    .d(2'b00),
    .e(2'b00),
    .fci(\add0/c15 ),
    .f({n2[17],n2[15]}),
    .fx({n2[18],n2[16]}));
  EG_PHY_LSLICE #(


    .DEMUX0("E"),
    .DEMUX1("E"),
    .INIT_LUTF0(16'hA55A),
    .INIT_LUTF1(16'hA55A),
    .INIT_LUTG0(16'hC33C),
    .INIT_LUTG1(16'hC33C),
    .LSFMUX0("SUM"),
    .LSFMUX1("SUM"),
    .LSFXMUX0("SUM"),
    .LSFXMUX1("SUM"),
    .MODE("RIPPLE"))
    \add0/u3_al_u32  (
    .a({cnt[5],cnt[3]}),
    .b({cnt[6],cnt[4]}),
    .c(2'b00),
    .d(2'b00),
    .e(2'b00),
    .fci(\add0/c3 ),
    .f({n2[5],n2[3]}),
    .fco(\add0/c7 ),
    .fx({n2[6],n2[4]}));
  EG_PHY_LSLICE #(


    .DEMUX0("E"),
    .DEMUX1("E"),
    .INIT_LUTF0(16'hA55A),
    .INIT_LUTF1(16'hA55A),
    .INIT_LUTG0(16'hC33C),
    .INIT_LUTG1(16'hC33C),
    .LSFMUX0("SUM"),
    .LSFMUX1("SUM"),
    .LSFXMUX0("SUM"),
    .LSFXMUX1("SUM"),
    .MODE("RIPPLE"))
    \add0/u7_al_u33  (
    .a({cnt[9],cnt[7]}),
    .b({cnt[10],cnt[8]}),
    .c(2'b00),
    .d(2'b00),
    .e(2'b00),
    .fci(\add0/c7 ),
    .f({n2[9],n2[7]}),
    .fco(\add0/c11 ),
    .fx({n2[10],n2[8]}));
  EG_PHY_LSLICE #(


    .DEMUX0("E"),
    .DEMUX1("E"),
    .INIT_LUTF0(16'h000A),
    .INIT_LUTF1(16'hA55A),
    .INIT_LUTG0(16'hC33C),
    .INIT_LUTG1(16'hC33C),
    .LSFMUX0("SUM"),
    .LSFMUX1("SUM"),
    .LSFXMUX0("SUM"),
    .LSFXMUX1("SUM"),
    .MODE("RIPPLE"))
    \add0/ucin_al_u31  (
    .a({cnt[1],1'b0}),
    .b({cnt[2],cnt[0]}),
    .c(2'b00),
    .d(2'b01),
    .e(2'b01),
    .f({n2[1],open_n226}),
    .fco(\add0/c3 ),
    .fx({n2[2],n2[0]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0000111100000000),
    .INIT_LUT1(16'b0000111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("SET"),
    .REG0_SD("MI"),
    .REG1_REGSET("SET"),
    .REG1_SD("MI"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg0_b0|reg0_b4  (
    .c({key_sec[0],key_sec[4]}),
    .clk(clk),
    .d({key_sec_pre[0],key_sec_pre[4]}),
    .mi({key_sec[0],key_sec[4]}),
    .sr(rst_n),
    .f({key_pulse[0],key_pulse[4]}),
    .q({key_sec_pre[0],key_sec_pre[4]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0000111100000000),
    .INIT_LUT1(16'b0000111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("SET"),
    .REG0_SD("MI"),
    .REG1_REGSET("SET"),
    .REG1_SD("MI"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg0_b1|reg0_b3  (
    .c({key_sec[1],key_sec[3]}),
    .clk(clk),
    .d({key_sec_pre[1],key_sec_pre[3]}),
    .mi({key_sec[1],key_sec[3]}),
    .sr(rst_n),
    .f({key_pulse[1],key_pulse[3]}),
    .q({key_sec_pre[1],key_sec_pre[3]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0111111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b0|reg1_b8  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[0],n2[8]}),
    .sr(rst_n),
    .q({cnt[0],cnt[8]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0111111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b10|reg1_b7  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[10],n2[7]}),
    .sr(rst_n),
    .q({cnt[10],cnt[7]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0111111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b11|reg1_b5  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[11],n2[5]}),
    .sr(rst_n),
    .q({cnt[11],cnt[5]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0111111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b12|reg1_b4  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[12],n2[4]}),
    .sr(rst_n),
    .q({cnt[12],cnt[4]}));


  EG_PHY_LSLICE #(




    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUTF0(16'b0111111100000000),
    .INIT_LUTF1(16'b0111111100000000),
    .INIT_LUTG0(16'b0111111100000000),
    .INIT_LUTG1(16'b0111111100000000),
    .LSFMUX0("FUNC5"),
    .LSFMUX1("FUNC5"),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b13|reg1_b3  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[13],n2[3]}),
    .sr(rst_n),
    .q({cnt[13],cnt[3]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0111111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b14|reg1_b18  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[14],n2[18]}),
    .sr(rst_n),
    .q({cnt[14],cnt[18]}));


  EG_PHY_MSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0111111100000000),
    .INIT_LUT1(16'b0111111100000000),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b15|reg1_b17  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[15],n2[17]}),
    .sr(rst_n),
    .q({cnt[15],cnt[17]}));


  EG_PHY_LSLICE #(




    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUTF0(16'b0111111100000000),
    .INIT_LUTF1(16'b0111111100000000),
    .INIT_LUTG0(16'b0111111100000000),
    .INIT_LUTG1(16'b0111111100000000),
    .LSFMUX0("FUNC5"),
    .LSFMUX1("FUNC5"),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .REG1_REGSET("RESET"),
    .REG1_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("INV"))
    \reg1_b1|reg1_b16  (
    .a({_al_u10_o,_al_u10_o}),
    .b({_al_u5_o,_al_u5_o}),
    .c({_al_u6_o,_al_u6_o}),
    .clk(clk),
    .d({n2[1],n2[16]}),
    .sr(rst_n),
    .q({cnt[1],cnt[16]}));
  EG_PHY_PAD #(




    .IDDRPIPEMODE("NONE"),
    .INCEMUX("CE"),
    .INPCLKMUX("CLK"),
    .INRSTMUX("INV"),
    .IN_DFFMODE("FF"),
    .IN_REGSET("SET"),
    .IOTYPE("LVCMOS25"),
    .MODE("IN"),
    .SRMODE("ASYNC"),
    .TSMUX("1"))
    reg2_b0_IN (
    .ce(n1),
    .ipad(key[0]),
    .ipclk(clk),
    .rst(rst_n),
    .diq({open_n426,open_n427,open_n428,key_sec[0]}));
  EG_PHY_PAD #(




    .IDDRPIPEMODE("NONE"),
    .INCEMUX("CE"),
    .INPCLKMUX("CLK"),
    .INRSTMUX("INV"),
    .IN_DFFMODE("FF"),
    .IN_REGSET("SET"),
    .IOTYPE("LVCMOS25"),
    .MODE("IN"),
    .SRMODE("ASYNC"),
    .TSMUX("1"))
    reg2_b1_IN (
    .ce(n1),
    .ipad(key[1]),
    .ipclk(clk),
    .rst(rst_n),
    .diq({open_n440,open_n441,open_n442,key_sec[1]}));
  EG_PHY_PAD #(




    .IDDRPIPEMODE("NONE"),
    .INCEMUX("CE"),
    .INPCLKMUX("CLK"),
    .INRSTMUX("INV"),
    .IN_DFFMODE("FF"),
    .IN_REGSET("SET"),
    .IOTYPE("LVCMOS25"),
    .MODE("IN"),
    .SRMODE("ASYNC"),
    .TSMUX("1"))
    reg2_b2_IN (
    .ce(n1),
    .ipad(key[2]),
    .ipclk(clk),
    .rst(rst_n),
    .diq({open_n454,open_n455,open_n456,key_sec[2]}));
  EG_PHY_PAD #(




    .IDDRPIPEMODE("NONE"),
    .INCEMUX("CE"),
    .INPCLKMUX("CLK"),
    .INRSTMUX("INV"),
    .IN_DFFMODE("FF"),
    .IN_REGSET("SET"),
    .IOTYPE("LVCMOS25"),
    .MODE("IN"),
    .SRMODE("ASYNC"),
    .TSMUX("1"))
    reg2_b3_IN (
    .ce(n1),
    .ipad(key[3]),
    .ipclk(clk),
    .rst(rst_n),
    .diq({open_n468,open_n469,open_n470,key_sec[3]}));
  EG_PHY_PAD #(




    .IDDRPIPEMODE("NONE"),
    .INCEMUX("CE"),
    .INPCLKMUX("CLK"),
    .INRSTMUX("INV"),
    .IN_DFFMODE("FF"),
    .IN_REGSET("SET"),
    .IOTYPE("LVCMOS25"),
    .MODE("IN"),
    .SRMODE("ASYNC"),
    .TSMUX("1"))
    reg2_b4_IN (
    .ce(n1),
    .ipad(key[4]),
    .ipclk(clk),
    .rst(rst_n),
    .diq({open_n482,open_n483,open_n484,key_sec[4]}));

endmodule