data/full_repos/permissive/154371523/Code/rtl/xoper.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/154371523/Code/rtl/xoper.v:55: Cannot find file containing module: \'booth_mult\'\nbooth_mult mult(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/booth_mult\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/booth_mult.v\n             data/full_repos/permissive/154371523/Code/rtl,data/full_repos/permissive/154371523/booth_mult.sv\n             booth_mult\n             booth_mult.v\n             booth_mult.sv\n             obj_dir/booth_mult\n             obj_dir/booth_mult.v\n             obj_dir/booth_mult.sv\n%Warning-WIDTH: data/full_repos/permissive/154371523/Code/rtl/xoper.v:127: Operator GTS expects 32 bits on the LHS, but LHS\'s SIGNED generates 11 bits.\n                                                                         : ... In instance xoper\n      if (($signed(operand1+operand2) > $signed(999)) || ($signed(operand1+operand2) < $signed(-999))) begin\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154371523/Code/rtl/xoper.v:127: Operator LTS expects 32 bits on the LHS, but LHS\'s SIGNED generates 11 bits.\n                                                                         : ... In instance xoper\n      if (($signed(operand1+operand2) > $signed(999)) || ($signed(operand1+operand2) < $signed(-999))) begin\n                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/154371523/Code/rtl/xoper.v:135: Operator GTS expects 32 bits on the LHS, but LHS\'s SIGNED generates 11 bits.\n                                                                         : ... In instance xoper\n      if (($signed(operand1-operand2) > $signed(999)) || ($signed(operand1-operand2) < $signed(-999)) )  begin\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/154371523/Code/rtl/xoper.v:135: Operator LTS expects 32 bits on the LHS, but LHS\'s SIGNED generates 11 bits.\n                                                                         : ... In instance xoper\n      if (($signed(operand1-operand2) > $signed(999)) || ($signed(operand1-operand2) < $signed(-999)) )  begin\n                                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/154371523/Code/rtl/xoper.v:165: Operator GTS expects 32 bits on the LHS, but LHS\'s SIGNED generates 24 bits.\n                                                                         : ... In instance xoper\n   if (($signed(mult_prod) > $signed(999)) || ($signed(mult_prod) < $signed(-999)) ) begin\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/154371523/Code/rtl/xoper.v:165: Operator LTS expects 32 bits on the LHS, but LHS\'s SIGNED generates 24 bits.\n                                                                         : ... In instance xoper\n   if (($signed(mult_prod) > $signed(999)) || ($signed(mult_prod) < $signed(-999)) ) begin\n                                                                  ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module xoper(

			input			clk,
			input			sel,
			input			rst,
			input [10:0] data_in,
			output reg [10:0] data_out = 0,
			output reg	[7:0] led = 0
			

    );
	 
	 

reg [10:0] operand1 = 11'b0;
reg [10:0] operand2 = 11'b0;
reg negative1;
reg negative2; 
reg [3:0] counter = 4'b0;
reg[1:0] operator = 2'b0;





reg [11:0] mult_x = 0;
reg [11:0] mult_y = 0;
wire [23:0] mult_prod;

wire mult_ready;
reg mult_start = 0;
reg multiply =0;


booth_mult mult(
	.prod(mult_prod),
	.ready(mult_ready),
	.multiplicand(mult_x),
	.multiplier(mult_y),
	.start(mult_start),
	.clk(clk)
	);


always @(posedge(clk)) begin

	if (rst) begin
			operand1 = 11'b0;
			operand2 = 11'b0;
			negative1 <= 1'b0;
			negative2 <= 1'b0;
			counter = 4'b0;
			operator <= 2'b0;
			
			led = 0;
		end

	else if (sel) begin
	
			if (data_in == 14 && counter < 4) counter = 4;
			else if (data_in == 14 && counter > 6 && counter < 9) counter = 9;
			
			case(counter)
				0: begin 
				if (data_in == 10) negative1 <= 0;
				else if (data_in == 11) negative1 <= 1;
				end
				
				1: operand1 = data_in;
				
				2: begin
					operand1 = (operand1 * 10) + data_in;
				end

				3: begin
					operand1 = (operand1 * 10) + data_in;
				end
				
				4: begin 
					case (data_in)
						10: operator <= 0;
						11: operator <= 1;
						12: operator <= 2;
					endcase
				end
				
				5: begin
					if (data_in == 10) negative2 <= 1'b0;
					else if (data_in == 11) negative2 <= 1'b1;
				end
				
				6: operand2 = data_in; 
				
				7: begin
					operand2 = (operand2 * 10) + data_in; 
				end	
				
				8: begin 
					operand2 = (operand2 * 10) + data_in;
				end
				
				9: begin 
					if (negative2 == 1'b1) operand2 = -operand2;
					if (negative1 == 1'b1) operand1 = -operand1;
					case (operator)
						0 : begin 
						if (($signed(operand1+operand2) > $signed(999)) || ($signed(operand1+operand2) < $signed(-999))) begin
								data_out <= 0;
								led=8'hFF;
						end
						else
								data_out <= operand1 + operand2;
						end
						1 : begin 
						if (($signed(operand1-operand2) > $signed(999)) || ($signed(operand1-operand2) < $signed(-999)) )  begin
								data_out <= 0;
								led=8'hFF;
							end
						else
								data_out <= operand1 - operand2;
						end
						
						2 : begin


							mult_x <= {operand1[10], operand1};
							mult_y <= {operand2[10], operand2};
							mult_start <= 1;
							multiply = 1;
							end
					
					endcase
				end
			endcase
		
			if (data_in != 14) counter = counter+1;
	
		end
	
	else if (mult_start)
		mult_start <= 0;
	else if (mult_ready && multiply)
		begin
		multiply =0;
			if (($signed(mult_prod) > $signed(999)) || ($signed(mult_prod) < $signed(-999)) ) begin
					data_out <= 0;
					led=8'hFF;
				end
			else
				data_out <= mult_prod[10:0];
		end
	
		
end

endmodule
module xoper(

			input			clk,
			input			sel,
			input			rst,
			input [10:0] data_in,
			output reg [10:0] data_out = 0,
			output reg	[7:0] led = 0
			

    );

	 
	 

reg [10:0] operand1 = 11'b0;
reg [10:0] operand2 = 11'b0;
reg negative1;
reg negative2; 
reg [3:0] counter = 4'b0;
reg[1:0] operator = 2'b0;





reg [11:0] mult_x = 0;
reg [11:0] mult_y = 0;
wire [23:0] mult_prod;

wire mult_ready;
reg mult_start = 0;
reg multiply =0;


booth_mult mult(
	.prod(mult_prod),
	.ready(mult_ready),
	.multiplicand(mult_x),
	.multiplier(mult_y),
	.start(mult_start),
	.clk(clk)
	);


always @(posedge(clk)) begin

	if (rst) begin
			operand1 = 11'b0;
			operand2 = 11'b0;
			negative1 <= 1'b0;
			negative2 <= 1'b0;
			counter = 4'b0;
			operator <= 2'b0;
			
			led = 0;
		end

	else if (sel) begin
	
			if (data_in == 14 && counter < 4) counter = 4;
			else if (data_in == 14 && counter > 6 && counter < 9) counter = 9;
			
			case(counter)
				0: begin 
				if (data_in == 10) negative1 <= 0;
				else if (data_in == 11) negative1 <= 1;
				end
				
				1: operand1 = data_in;
				
				2: begin
					operand1 = (operand1 * 10) + data_in;
				end

				3: begin
					operand1 = (operand1 * 10) + data_in;
				end
				
				4: begin 
					case (data_in)
						10: operator <= 0;
						11: operator <= 1;
						12: operator <= 2;
					endcase
				end
				
				5: begin
					if (data_in == 10) negative2 <= 1'b0;
					else if (data_in == 11) negative2 <= 1'b1;
				end
				
				6: operand2 = data_in; 
				
				7: begin
					operand2 = (operand2 * 10) + data_in; 
				end	
				
				8: begin 
					operand2 = (operand2 * 10) + data_in;
				end
				
				9: begin 
					if (negative2 == 1'b1) operand2 = -operand2;
					if (negative1 == 1'b1) operand1 = -operand1;
					case (operator)
						0 : begin 
						if (($signed(operand1+operand2) > $signed(999)) || ($signed(operand1+operand2) < $signed(-999))) begin
								data_out <= 0;
								led=8'hFF;
						end
						else
								data_out <= operand1 + operand2;
						end
						1 : begin 
						if (($signed(operand1-operand2) > $signed(999)) || ($signed(operand1-operand2) < $signed(-999)) )  begin
								data_out <= 0;
								led=8'hFF;
							end
						else
								data_out <= operand1 - operand2;
						end
						
						2 : begin


							mult_x <= {operand1[10], operand1};
							mult_y <= {operand2[10], operand2};
							mult_start <= 1;
							multiply = 1;
							end
					
					endcase
				end
			endcase
		
			if (data_in != 14) counter = counter+1;
	
		end
	
	else if (mult_start)
		mult_start <= 0;
	else if (mult_ready && multiply)
		begin
		multiply =0;
			if (($signed(mult_prod) > $signed(999)) || ($signed(mult_prod) < $signed(-999)) ) begin
					data_out <= 0;
					led=8'hFF;
				end
			else
				data_out <= mult_prod[10:0];
		end
	
		
end

endmodule