data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v
 line:22: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #5 reset <= 1\'b0;  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #320 W <= 1\'b0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #320 $stop;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #5 clock <= ~clock;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #5 D <= {$random, $random};  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #5 ;\n  ^\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:45: Can\'t find definition of \'reg0\' in dotted variable: \'dut.reg0\'\n assign R00 = dut.reg0;\n                  ^~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:46: Can\'t find definition of \'reg1\' in dotted variable: \'dut.reg1\'\n assign R01 = dut.reg1;\n                  ^~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:47: Can\'t find definition of \'reg2\' in dotted variable: \'dut.reg2\'\n assign R02 = dut.reg2;\n                  ^~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:48: Can\'t find definition of \'reg3\' in dotted variable: \'dut.reg3\'\n assign R03 = dut.reg3;\n                  ^~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:49: Can\'t find definition of \'reg4\' in dotted variable: \'dut.reg4\'\n assign R04 = dut.reg4;\n                  ^~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:50: Can\'t find definition of \'reg5\' in dotted variable: \'dut.reg5\'\n assign R05 = dut.reg5;\n                  ^~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:51: Can\'t find definition of \'reg6\' in dotted variable: \'dut.reg6\'\n assign R06 = dut.reg6;\n                  ^~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:52: Can\'t find definition of \'reg7\' in dotted variable: \'dut.reg7\'\n assign R07 = dut.reg7;\n                  ^~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:53: Can\'t find definition of \'reg8\' in dotted variable: \'dut.reg8\'\n assign R08 = dut.reg8;\n                  ^~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:54: Can\'t find definition of \'reg9\' in dotted variable: \'dut.reg9\'\n assign R09 = dut.reg9;\n                  ^~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:55: Can\'t find definition of \'reg10\' in dotted variable: \'dut.reg10\'\n assign R10 = dut.reg10;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:56: Can\'t find definition of \'reg11\' in dotted variable: \'dut.reg11\'\n assign R11 = dut.reg11;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:57: Can\'t find definition of \'reg12\' in dotted variable: \'dut.reg12\'\n assign R12 = dut.reg12;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:58: Can\'t find definition of \'reg13\' in dotted variable: \'dut.reg13\'\n assign R13 = dut.reg13;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:59: Can\'t find definition of \'reg14\' in dotted variable: \'dut.reg14\'\n assign R14 = dut.reg14;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:60: Can\'t find definition of \'reg15\' in dotted variable: \'dut.reg15\'\n assign R15 = dut.reg15;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:61: Can\'t find definition of \'reg16\' in dotted variable: \'dut.reg16\'\n assign R16 = dut.reg16;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:62: Can\'t find definition of \'reg17\' in dotted variable: \'dut.reg17\'\n assign R17 = dut.reg17;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:63: Can\'t find definition of \'reg18\' in dotted variable: \'dut.reg18\'\n assign R18 = dut.reg18;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:64: Can\'t find definition of \'reg19\' in dotted variable: \'dut.reg19\'\n assign R19 = dut.reg19;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:65: Can\'t find definition of \'reg20\' in dotted variable: \'dut.reg20\'\n assign R20 = dut.reg20;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:66: Can\'t find definition of \'reg21\' in dotted variable: \'dut.reg21\'\n assign R21 = dut.reg21;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:67: Can\'t find definition of \'reg22\' in dotted variable: \'dut.reg22\'\n assign R22 = dut.reg22;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:68: Can\'t find definition of \'reg23\' in dotted variable: \'dut.reg23\'\n assign R23 = dut.reg23;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:69: Can\'t find definition of \'reg24\' in dotted variable: \'dut.reg24\'\n assign R24 = dut.reg24;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:70: Can\'t find definition of \'reg25\' in dotted variable: \'dut.reg25\'\n assign R25 = dut.reg25;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:71: Can\'t find definition of \'reg26\' in dotted variable: \'dut.reg26\'\n assign R26 = dut.reg26;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:72: Can\'t find definition of \'reg27\' in dotted variable: \'dut.reg27\'\n assign R27 = dut.reg27;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:73: Can\'t find definition of \'reg28\' in dotted variable: \'dut.reg28\'\n assign R28 = dut.reg28;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:74: Can\'t find definition of \'reg29\' in dotted variable: \'dut.reg29\'\n assign R29 = dut.reg29;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:75: Can\'t find definition of \'reg30\' in dotted variable: \'dut.reg30\'\n assign R30 = dut.reg30;\n                  ^~~~~\n%Error: data/full_repos/permissive/167489907/Testbenches/Supplied/regfile32x64_testbench.v:76: Can\'t find definition of \'reg31\' in dotted variable: \'dut.reg31\'\n assign R31 = dut.reg31;\n                  ^~~~~\n%Error: Exiting due to 32 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module regfile32x64_testbench;

	reg [4:0]SA, SB, DA;
	reg [63:0]D;
	reg W, reset, clock;

	wire [63:0]A, B;
	
	regfile32x64 dut (.rdDataA(A), .rdDataB(B), .rdAddrA(SA), .rdAddrB(SB), .wrData(D), .wrAddr(DA), .write(W), .reset(reset), .clk(clock));
	

	initial begin
		clock <= 1'b1;
		reset <= 1'b1;
		D <= 64'b0;
		W <= 1'b1;
		DA <= 5'd31;
		SA <= 5'd30;
		SB <= 5'd29;
		#5 reset <= 1'b0;
		#320 W <= 1'b0;
		#320 $stop;
	end
	

	always
		#5 clock <= ~clock;
		

	always begin
		#5 D <= {$random, $random};
		DA <= DA + 5'b1;
		SA <= SA + 5'b1;
		SB <= SB + 5'b1;
		#5 ;
	end
	


	wire [63:0]R00, R01, R02, R03, R04, R05, R06, R07, R08, R09;
	wire [63:0]R10, R11, R12, R13, R14, R15, R16, R17, R18, R19;
	wire [63:0]R20, R21, R22, R23, R24, R25, R26, R27, R28, R29;
	wire [63:0]R30, R31;
	
	assign R00 = dut.reg0;
	assign R01 = dut.reg1;
	assign R02 = dut.reg2;
	assign R03 = dut.reg3;
	assign R04 = dut.reg4;
	assign R05 = dut.reg5;
	assign R06 = dut.reg6;
	assign R07 = dut.reg7;
	assign R08 = dut.reg8;
	assign R09 = dut.reg9;
	assign R10 = dut.reg10;
	assign R11 = dut.reg11;
	assign R12 = dut.reg12;
	assign R13 = dut.reg13;
	assign R14 = dut.reg14;
	assign R15 = dut.reg15;
	assign R16 = dut.reg16;
	assign R17 = dut.reg17;
	assign R18 = dut.reg18;
	assign R19 = dut.reg19;
	assign R20 = dut.reg20;
	assign R21 = dut.reg21;
	assign R22 = dut.reg22;
	assign R23 = dut.reg23;
	assign R24 = dut.reg24;
	assign R25 = dut.reg25;
	assign R26 = dut.reg26;
	assign R27 = dut.reg27;
	assign R28 = dut.reg28;
	assign R29 = dut.reg29;
	assign R30 = dut.reg30;
	assign R31 = dut.reg31;
	
endmodule
module regfile32x64_testbench;


	reg [4:0]SA, SB, DA;
	reg [63:0]D;
	reg W, reset, clock;

	wire [63:0]A, B;
	
	regfile32x64 dut (.rdDataA(A), .rdDataB(B), .rdAddrA(SA), .rdAddrB(SB), .wrData(D), .wrAddr(DA), .write(W), .reset(reset), .clk(clock));
	

	initial begin
		clock <= 1'b1;
		reset <= 1'b1;
		D <= 64'b0;
		W <= 1'b1;
		DA <= 5'd31;
		SA <= 5'd30;
		SB <= 5'd29;
		#5 reset <= 1'b0;
		#320 W <= 1'b0;
		#320 $stop;
	end
	

	always
		#5 clock <= ~clock;
		

	always begin
		#5 D <= {$random, $random};
		DA <= DA + 5'b1;
		SA <= SA + 5'b1;
		SB <= SB + 5'b1;
		#5 ;
	end
	


	wire [63:0]R00, R01, R02, R03, R04, R05, R06, R07, R08, R09;
	wire [63:0]R10, R11, R12, R13, R14, R15, R16, R17, R18, R19;
	wire [63:0]R20, R21, R22, R23, R24, R25, R26, R27, R28, R29;
	wire [63:0]R30, R31;
	
	assign R00 = dut.reg0;
	assign R01 = dut.reg1;
	assign R02 = dut.reg2;
	assign R03 = dut.reg3;
	assign R04 = dut.reg4;
	assign R05 = dut.reg5;
	assign R06 = dut.reg6;
	assign R07 = dut.reg7;
	assign R08 = dut.reg8;
	assign R09 = dut.reg9;
	assign R10 = dut.reg10;
	assign R11 = dut.reg11;
	assign R12 = dut.reg12;
	assign R13 = dut.reg13;
	assign R14 = dut.reg14;
	assign R15 = dut.reg15;
	assign R16 = dut.reg16;
	assign R17 = dut.reg17;
	assign R18 = dut.reg18;
	assign R19 = dut.reg19;
	assign R20 = dut.reg20;
	assign R21 = dut.reg21;
	assign R22 = dut.reg22;
	assign R23 = dut.reg23;
	assign R24 = dut.reg24;
	assign R25 = dut.reg25;
	assign R26 = dut.reg26;
	assign R27 = dut.reg27;
	assign R28 = dut.reg28;
	assign R29 = dut.reg29;
	assign R30 = dut.reg30;
	assign R31 = dut.reg31;
	
endmodule