data/full_repos/permissive/175122930/test/helloworld_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/175122930/test/helloworld_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #1 ext_clock = ~ext_clock;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/175122930/test/helloworld_tb.v:15: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("helloworld_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/175122930/test/helloworld_tb.v:16: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars (0, helloworld_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/175122930/test/helloworld_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #5000000 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module helloworld_tb #(parameter CLOCK_FREQ = 4800, parameter BAUD_RATE = 1200) ();

	reg ext_clock;
	wire uart_tx_pin;
	wire uart_tx_led;
	wire uart_clock_led;

	always
		#1 ext_clock = ~ext_clock;

	initial begin
		ext_clock = 0;
		$dumpfile ("helloworld_tb.vcd");
		$dumpvars (0, helloworld_tb);
		#5000000 $finish;
	end

	helloworld #(.CLOCK_FREQ(CLOCK_FREQ), .BAUD_RATE(BAUD_RATE))
		HELLOWORLD (.ext_clock(ext_clock),
			.uart_tx_pin(uart_tx_pin),
			.uart_tx_led(uart_tx_led),
			.uart_clock_led(uart_clock_led));
endmodule
module helloworld_tb #(parameter CLOCK_FREQ = 4800, parameter BAUD_RATE = 1200) ();


	reg ext_clock;
	wire uart_tx_pin;
	wire uart_tx_led;
	wire uart_clock_led;

	always
		#1 ext_clock = ~ext_clock;

	initial begin
		ext_clock = 0;
		$dumpfile ("helloworld_tb.vcd");
		$dumpvars (0, helloworld_tb);
		#5000000 $finish;
	end

	helloworld #(.CLOCK_FREQ(CLOCK_FREQ), .BAUD_RATE(BAUD_RATE))
		HELLOWORLD (.ext_clock(ext_clock),
			.uart_tx_pin(uart_tx_pin),
			.uart_tx_led(uart_tx_led),
			.uart_clock_led(uart_clock_led));
endmodule