data/full_repos/permissive/119758565/Register.v
1: b"%Error: data/full_repos/permissive/119758565/Register.v:32: syntax error, unexpected '(', expecting IDENTIFIER\n      Bit(data[i], load, clk, out[i]);\n          ^~~~\n%Error: Exiting due to 1 error(s)\n"
module Register(
    input [0:15] data,
    input load,
    input clk,
    output [0:15] out
    );
	 
	 generate
	   genvar i;
		for (i=0; i<16; i=i+1)
		  begin
		    Bit(data[i], load, clk, out[i]);
		  end
    endgenerate


endmodule
module Register(
    input [0:15] data,
    input load,
    input clk,
    output [0:15] out
    );

	 
	 generate
	   genvar i;
		for (i=0; i<16; i=i+1)
		  begin
		    Bit(data[i], load, clk, out[i]);
		  end
    endgenerate


endmodule