data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v
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1: b"%Error: data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v:45: Duplicate declaration of signal: 'a'\n                                                                         : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire a, b, y;\n       ^\n        data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v:33: ... Location of original declaration\n  input a,   \n        ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v:45: Duplicate declaration of signal: 'b'\n  wire a, b, y;\n          ^\n        data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v:34: ... Location of original declaration\n  input b,   \n        ^\n%Error: data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v:45: Duplicate declaration of signal: 'y'\n  wire a, b, y;\n             ^\n        data/full_repos/permissive/100331186/tarea3/modulos/nandGate.v:35: ... Location of original declaration\n  output y   \n         ^\n%Error: Exiting due to 3 error(s)\n"
module nandGate (
  input a,
  input b,
  output y
);

  parameter tpdmin = 1.5;
  parameter tpdmax = 11.1;

  parameter Vcc = 3.3;
  parameter Cl = 0.05;


  wire a, b, y;

  integer c;
  initial c=0;

  assign #(tpdmin:tpdmax:tpdmax) y = !(a & b);

  always @ (y) begin
    c=c+1;

  end
endmodule
module nandGate (
  input a,
  input b,
  output y
);


  parameter tpdmin = 1.5;
  parameter tpdmax = 11.1;

  parameter Vcc = 3.3;
  parameter Cl = 0.05;


  wire a, b, y;

  integer c;
  initial c=0;

  assign #(tpdmin:tpdmax:tpdmax) y = !(a & b);

  always @ (y) begin
    c=c+1;

  end
endmodule