data/full_repos/permissive/205841227/verilog/xilinx/clkgen.v
1: b"%Error: data/full_repos/permissive/205841227/verilog/xilinx/clkgen.v:5: Cannot find file containing module: 'ODDR2'\nODDR2 ODDR2_inst0 (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/205841227/verilog/xilinx,data/full_repos/permissive/205841227/ODDR2\n             data/full_repos/permissive/205841227/verilog/xilinx,data/full_repos/permissive/205841227/ODDR2.v\n             data/full_repos/permissive/205841227/verilog/xilinx,data/full_repos/permissive/205841227/ODDR2.sv\n             ODDR2\n             ODDR2.v\n             ODDR2.sv\n             obj_dir/ODDR2\n             obj_dir/ODDR2.v\n             obj_dir/ODDR2.sv\n%Error: data/full_repos/permissive/205841227/verilog/xilinx/clkgen.v:15: Cannot find file containing module: 'ODDR2'\nODDR2 ODDR2_inst1 (\n^~~~~\n%Error: data/full_repos/permissive/205841227/verilog/xilinx/clkgen.v:25: Cannot find file containing module: 'ODDR2'\nODDR2 ODDR2_inst2 (\n^~~~~\n%Error: data/full_repos/permissive/205841227/verilog/xilinx/clkgen.v:35: Cannot find file containing module: 'ODDR2'\nODDR2 ODDR2_inst3 (\n^~~~~\n%Error: data/full_repos/permissive/205841227/verilog/xilinx/clkgen.v:45: Cannot find file containing module: 'ODDR2'\nODDR2 ODDR2_inst4 (\n^~~~~\n%Error: data/full_repos/permissive/205841227/verilog/xilinx/clkgen.v:55: Cannot find file containing module: 'ODDR2'\nODDR2 ODDR2_inst5 (\n^~~~~\n%Error: data/full_repos/permissive/205841227/verilog/xilinx/clkgen.v:65: Cannot find file containing module: 'ODDR2'\nODDR2 ODDR2_inst6 (\n^~~~~\n%Error: data/full_repos/permissive/205841227/verilog/xilinx/clkgen.v:75: Cannot find file containing module: 'ODDR2'\nODDR2 ODDR2_inst7 (\n^~~~~\n%Error: data/full_repos/permissive/205841227/verilog/xilinx/clkgen.v:87: Cannot find file containing module: 'cpm_ctrl5'\ncpm_ctrl5 cpm_ctrl5(\n^~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module clkgen(input wire clkin, input wire [7:0] clk25m_on, output wire clkout, output wire [7:0] clk25m, output wire locked, output wire mcu_clk);

wire clkout_div ;

ODDR2 ODDR2_inst0 (
   .Q (clk25m[0]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[0]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst1 (
   .Q (clk25m[1]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[1]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst2 (
   .Q (clk25m[2]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[2]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst3 (
   .Q (clk25m[3]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[3]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst4 (
   .Q (clk25m[4]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[4]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst5 (
   .Q (clk25m[5]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[5]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst6 (
   .Q (clk25m[6]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[6]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst7 (
   .Q (clk25m[7]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[7]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);

wire clkfb;
cpm_ctrl5 cpm_ctrl5(
.CLK_IN1  (clkin     ),
.CLKFB_IN (clkfb     ),
.core_clk (clkout    ),
.chip_clk (clkout_div),
.mcu_clk  (mcu_clk   ),
.CLKFB_OUT(clkfb     ),
.LOCKED   (locked    )
);

endmodule
module clkgen(input wire clkin, input wire [7:0] clk25m_on, output wire clkout, output wire [7:0] clk25m, output wire locked, output wire mcu_clk);


wire clkout_div ;

ODDR2 ODDR2_inst0 (
   .Q (clk25m[0]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[0]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst1 (
   .Q (clk25m[1]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[1]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst2 (
   .Q (clk25m[2]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[2]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst3 (
   .Q (clk25m[3]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[3]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst4 (
   .Q (clk25m[4]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[4]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst5 (
   .Q (clk25m[5]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[5]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst6 (
   .Q (clk25m[6]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[6]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);
ODDR2 ODDR2_inst7 (
   .Q (clk25m[7]),
   .C0(clkout_div),
   .C1(~clkout_div),
   .CE(clk25m_on[7]),
   .D0(1'b0),
   .D1(1'b1),
   .R (1'b0),
   .S (1'b0)
);

wire clkfb;
cpm_ctrl5 cpm_ctrl5(
.CLK_IN1  (clkin     ),
.CLKFB_IN (clkfb     ),
.core_clk (clkout    ),
.chip_clk (clkout_div),
.mcu_clk  (mcu_clk   ),
.CLKFB_OUT(clkfb     ),
.LOCKED   (locked    )
);

endmodule