data/full_repos/permissive/125927162/SIPO/sipo_tb.v
 line:77: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:43: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("sipo_test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:44: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, sipo_tb);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n      #25\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n      #15\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n      #50\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n      #5\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n      #15\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/SIPO/sipo_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n%Error: Exiting due to 2 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sipo_tb ();
   reg clk;
   reg d;
   wire [15:0] out;
   reg rst;
   reg oe;
   reg ie;
   
   sipo #(.WIDTH(8)) DUT (
			  .clk(clk),
			  .d(d),
			  .q(out[7:0]),
			  .rst(rst),
			  .oe(oe),
			  .ie(ie)
			  );
   sipo #(.WIDTH(8)) DUT1 (
			   .clk(clk),
			   .d(out[7]),
			   .q(out[15:8]),
			   .rst(rst),
			   .oe(oe),
			   .ie(ie)
			   );
   always #5 clk = ~clk;

   initial begin
      $dumpfile("sipo_test.vcd");
      $dumpvars(0, sipo_tb);
      ie = 1;
      oe = 1;
      rst = 0;
      d = 0;
      clk = 0;
      #5
	rst = 1;
      #5
	rst = 0;
      #5
	oe = 1;
      #5
      d = 1;
      #25
	d = 0;
      #15
	d = 1;
      #50
	oe = 0;
      #10
	ie = 0;
      #5
	rst =1;
      #5
	rst = 0;
      #5
	oe = 1;
      #5
	ie = 1;
      #5
	rst = 1;
      #15
      $finish;
   end

   always #5 clk = ~clk;
endmodule
module sipo_tb ();

   reg clk;
   reg d;
   wire [15:0] out;
   reg rst;
   reg oe;
   reg ie;
   
   sipo #(.WIDTH(8)) DUT (
			  .clk(clk),
			  .d(d),
			  .q(out[7:0]),
			  .rst(rst),
			  .oe(oe),
			  .ie(ie)
			  );
   sipo #(.WIDTH(8)) DUT1 (
			   .clk(clk),
			   .d(out[7]),
			   .q(out[15:8]),
			   .rst(rst),
			   .oe(oe),
			   .ie(ie)
			   );
   always #5 clk = ~clk;

   initial begin
      $dumpfile("sipo_test.vcd");
      $dumpvars(0, sipo_tb);
      ie = 1;
      oe = 1;
      rst = 0;
      d = 0;
      clk = 0;
      #5
	rst = 1;
      #5
	rst = 0;
      #5
	oe = 1;
      #5
      d = 1;
      #25
	d = 0;
      #15
	d = 1;
      #50
	oe = 0;
      #10
	ie = 0;
      #5
	rst =1;
      #5
	rst = 0;
      #5
	oe = 1;
      #5
	ie = 1;
      #5
	rst = 1;
      #15
      $finish;
   end

   always #5 clk = ~clk;
endmodule