data/full_repos/permissive/143278/ivltests/vhdl_while.v
 line:24: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_while.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_while.v:25: Cannot find file containing module: \'vhdl_while\'\nvhdl_while dut(start, out);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_while\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_while.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/vhdl_while.sv\n             vhdl_while\n             vhdl_while.v\n             vhdl_while.sv\n             obj_dir/vhdl_while\n             obj_dir/vhdl_while.v\n             obj_dir/vhdl_while.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vhdl_while_test;
logic start;
int out;
vhdl_while dut(start, out);

initial begin
    start = 1;
    #1;

    if(out !== 10) begin
        $display("FAILED");
        $finish();
    end

    $display("PASSED");
end
endmodule
module vhdl_while_test;

logic start;
int out;
vhdl_while dut(start, out);

initial begin
    start = 1;
    #1;

    if(out !== 10) begin
        $display("FAILED");
        $finish();
    end

    $display("PASSED");
end
endmodule