data/full_repos/permissive/173814379/implementation/core/machine_v1r0.v
 line:1 column:1: Illegal character '\x00'
1: b'%Error: data/full_repos/permissive/173814379/implementation/core/machine_v1r0.v:132: version control conflict marker in file\n<<<<<<< Updated upstream\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/173814379/implementation/core/machine_v1r0.v:135: version control conflict marker in file\n=======\n^~~~~~~\n%Error: data/full_repos/permissive/173814379/implementation/core/machine_v1r0.v:138: version control conflict marker in file\n>>>>>>> Stashed changes\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module EmulatedPLL(iIn, oOut, oOutNinety, oOutFast);
    input iIn;
    output reg oOut, oOutNinety;
    output wire oOutFast;

    reg [1:0] rClockSplit;

    assign oOutFast = iIn;
    
    initial begin
        rClockSplit <= 0;
    end

    always @(posedge iIn) begin
        rClockSplit <= rClockSplit + 1;
        
        if(rClockSplit == 0)
            oOut = 1;
        if(rClockSplit == 1)
            oOutNinety = 1;
        if(rClockSplit == 2)
            oOut = 0;
        if(rClockSplit == 3)
            oOutNinety = 0;
    end

endmodule
module EmulatedPLL(iIn, oOut, oOutNinety, oOutFast);

    input iIn;
    output reg oOut, oOutNinety;
    output wire oOutFast;

    reg [1:0] rClockSplit;

    assign oOutFast = iIn;
    
    initial begin
        rClockSplit <= 0;
    end

    always @(posedge iIn) begin
        rClockSplit <= rClockSplit + 1;
        
        if(rClockSplit == 0)
            oOut = 1;
        if(rClockSplit == 1)
            oOutNinety = 1;
        if(rClockSplit == 2)
            oOut = 0;
        if(rClockSplit == 3)
            oOutNinety = 0;
    end

endmodule