data/full_repos/permissive/214278225/1_7SegmentDisplay/display2/stateMachine.v
data/verilator_xmls/846ba446-b513-47af-bd8b-f2ffa9c44198.xml
module stateMachine(clk, rst, en, state);

input clk, rst, en;
output reg [2:0] state;

reg [2:0] stateNxt;

always @(posedge clk) begin
	state <= #1 stateNxt;
end

always @(*) begin
	stateNxt = state;
	if(rst)
		stateNxt = 0;
	else begin
		if(en)
			stateNxt = state+1;
	end


end

endmodule
module stateMachine(clk, rst, en, state);


input clk, rst, en;
output reg [2:0] state;

reg [2:0] stateNxt;

always @(posedge clk) begin
	state <= #1 stateNxt;
end

always @(*) begin
	stateNxt = state;
	if(rst)
		stateNxt = 0;
	else begin
		if(en)
			stateNxt = state+1;
	end


end

endmodule