data/full_repos/permissive/194376374/0521_LJX_lab5/0521_LJX_lab0501/lab5.srcs/sources_1/imports/new/Ctr.v
data/verilator_xmls/413c52dc-975d-4e03-8856-cde7551fd52e.xml
module Ctr(
    input [5:0] OpCode,
    output reg RegDst,
    output reg ALUSrc,
    output reg MemToReg,
    output reg RegWrite,
    output reg MemRead,
    output reg MemWrite,
    output reg Branch,
    output reg [1:0] ALUOp,
    output reg Jump
    );
       
    initial begin
    Branch=0;
    Jump=0;
    end
    
    always @ (OpCode)
    begin
        case (OpCode)
        6'b000000:
        begin
            RegDst=1;
            ALUSrc=0;
            MemToReg=0;
            RegWrite=1;
            MemRead=0;
            MemWrite=0;
            Branch=0;
            ALUOp=2'b10;
            Jump=0;
        end
        
        6'b100011:
        begin
            RegDst=0;
            ALUSrc=1;
            MemToReg=1;
            RegWrite=1;
            MemRead=1;
            MemWrite=0;
            Branch=0;
            ALUOp=2'b00;
            Jump=0;
        end        
        
        6'b101011:
         begin

            ALUSrc=1;

            RegWrite=0;
            MemRead=0;
            MemWrite=1;
            Branch=0;
            ALUOp=2'b00;
            Jump=0;
        end           
                
        6'b000100:
        begin

            ALUSrc=0;

            RegWrite=0;
            MemRead=0;
            MemWrite=0;
            Branch=1;
            ALUOp=2'b01;
            Jump=0;
        end
          
        6'b000010:
        begin
            RegDst=0;
            ALUSrc=0;
            MemToReg=0;
            RegWrite=0;
            MemRead=0;
            MemWrite=0;
            Branch=0;
            ALUOp=2'b00;
            Jump=1;
        end         
        
        default:
        begin
            RegDst=0;
            ALUSrc=0;
            MemToReg=0;
            RegWrite=0;
            MemRead=0;
            MemWrite=0;
            Branch=0;
            ALUOp=2'b00;
            Jump=0;
        end
    endcase
    end
endmodule
module Ctr(
    input [5:0] OpCode,
    output reg RegDst,
    output reg ALUSrc,
    output reg MemToReg,
    output reg RegWrite,
    output reg MemRead,
    output reg MemWrite,
    output reg Branch,
    output reg [1:0] ALUOp,
    output reg Jump
    );

       
    initial begin
    Branch=0;
    Jump=0;
    end
    
    always @ (OpCode)
    begin
        case (OpCode)
        6'b000000:
        begin
            RegDst=1;
            ALUSrc=0;
            MemToReg=0;
            RegWrite=1;
            MemRead=0;
            MemWrite=0;
            Branch=0;
            ALUOp=2'b10;
            Jump=0;
        end
        
        6'b100011:
        begin
            RegDst=0;
            ALUSrc=1;
            MemToReg=1;
            RegWrite=1;
            MemRead=1;
            MemWrite=0;
            Branch=0;
            ALUOp=2'b00;
            Jump=0;
        end        
        
        6'b101011:
         begin

            ALUSrc=1;

            RegWrite=0;
            MemRead=0;
            MemWrite=1;
            Branch=0;
            ALUOp=2'b00;
            Jump=0;
        end           
                
        6'b000100:
        begin

            ALUSrc=0;

            RegWrite=0;
            MemRead=0;
            MemWrite=0;
            Branch=1;
            ALUOp=2'b01;
            Jump=0;
        end
          
        6'b000010:
        begin
            RegDst=0;
            ALUSrc=0;
            MemToReg=0;
            RegWrite=0;
            MemRead=0;
            MemWrite=0;
            Branch=0;
            ALUOp=2'b00;
            Jump=1;
        end         
        
        default:
        begin
            RegDst=0;
            ALUSrc=0;
            MemToReg=0;
            RegWrite=0;
            MemRead=0;
            MemWrite=0;
            Branch=0;
            ALUOp=2'b00;
            Jump=0;
        end
    endcase
    end
endmodule