data/full_repos/permissive/119126104/myCPU/tlb.v
data/verilator_xmls/8a72b614-e306-4e11-a3b3-f7f476d54827.xml
module encoder(
    input  wire [31:0] in,
    output reg  [ 4:0] out
);
    always @(*) begin
        case(in)
        32'h8000_0000: out = 5'd31;
        32'h4000_0000: out = 5'd30;
        32'h2000_0000: out = 5'd29;
        32'h1000_0000: out = 5'd28;
        32'h0800_0000: out = 5'd27;
        32'h0400_0000: out = 5'd26;
        32'h0200_0000: out = 5'd25;
        32'h0100_0000: out = 5'd24;
        32'h0080_0000: out = 5'd23;
        32'h0040_0000: out = 5'd22;
        32'h0020_0000: out = 5'd21;
        32'h0010_0000: out = 5'd20;
        32'h0008_0000: out = 5'd19;
        32'h0004_0000: out = 5'd18;
        32'h0002_0000: out = 5'd17;
        32'h0001_0000: out = 5'd16;
        32'h0000_8000: out = 5'd15;
        32'h0000_4000: out = 5'd14;
        32'h0000_2000: out = 5'd13;
        32'h0000_1000: out = 5'd12;
        32'h0000_0800: out = 5'd11;
        32'h0000_0400: out = 5'd10;
        32'h0000_0200: out = 5'd9 ;
        32'h0000_0100: out = 5'd8 ;
        32'h0000_0080: out = 5'd7 ;
        32'h0000_0040: out = 5'd6 ;
        32'h0000_0020: out = 5'd5 ;
        32'h0000_0010: out = 5'd4 ;
        32'h0000_0008: out = 5'd3 ;
        32'h0000_0004: out = 5'd2 ;
        32'h0000_0002: out = 5'd1 ;
        32'h0000_0001: out = 5'd0 ;
        default      : out = 5'd0 ;
        endcase
    end
endmodule
module encoder(
    input  wire [31:0] in,
    output reg  [ 4:0] out
);

    always @(*) begin
        case(in)
        32'h8000_0000: out = 5'd31;
        32'h4000_0000: out = 5'd30;
        32'h2000_0000: out = 5'd29;
        32'h1000_0000: out = 5'd28;
        32'h0800_0000: out = 5'd27;
        32'h0400_0000: out = 5'd26;
        32'h0200_0000: out = 5'd25;
        32'h0100_0000: out = 5'd24;
        32'h0080_0000: out = 5'd23;
        32'h0040_0000: out = 5'd22;
        32'h0020_0000: out = 5'd21;
        32'h0010_0000: out = 5'd20;
        32'h0008_0000: out = 5'd19;
        32'h0004_0000: out = 5'd18;
        32'h0002_0000: out = 5'd17;
        32'h0001_0000: out = 5'd16;
        32'h0000_8000: out = 5'd15;
        32'h0000_4000: out = 5'd14;
        32'h0000_2000: out = 5'd13;
        32'h0000_1000: out = 5'd12;
        32'h0000_0800: out = 5'd11;
        32'h0000_0400: out = 5'd10;
        32'h0000_0200: out = 5'd9 ;
        32'h0000_0100: out = 5'd8 ;
        32'h0000_0080: out = 5'd7 ;
        32'h0000_0040: out = 5'd6 ;
        32'h0000_0020: out = 5'd5 ;
        32'h0000_0010: out = 5'd4 ;
        32'h0000_0008: out = 5'd3 ;
        32'h0000_0004: out = 5'd2 ;
        32'h0000_0002: out = 5'd1 ;
        32'h0000_0001: out = 5'd0 ;
        default      : out = 5'd0 ;
        endcase
    end
endmodule