data/full_repos/permissive/169382915/rtl/coprocessor/scarv_cop_cprs.v
1: b'%Warning-WIDTH: data/full_repos/permissive/169382915/rtl/coprocessor/scarv_cop_cprs.v:53: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'crd_wen\' generates 4 bits.\n                                                                                        : ... In instance scarv_cop_cprs\nassign g_clk_req = crd_wen;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/169382915/rtl/coprocessor/scarv_cop_cprs.v:97: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'crd_addr\' generates 4 bits.\n                                                                                        : ... In instance scarv_cop_cprs\nwire [ 3:0] addr    = cprs_init ? init_fsm  : crd_addr;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/169382915/rtl/coprocessor/scarv_cop_cprs.v:97: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 5 bits.\n                                                                                        : ... In instance scarv_cop_cprs\nwire [ 3:0] addr    = cprs_init ? init_fsm  : crd_addr;\n                    ^\n%Error: Exiting due to 3 warning(s)\n'
module scarv_cop_cprs (

input  wire             g_clk         ,
output wire             g_clk_req     ,
input  wire             g_resetn      ,

`ifdef FORMAL
`VTX_REGISTER_PORTS_OUT(cprs_snoop)
`endif

input  wire             cprs_init     ,
output wire             cprs_init_done,

input  wire             crs1_ren      ,
input  wire [ 3:0]      crs1_addr     ,
output wire [31:0]      crs1_rdata    ,

input  wire             crs2_ren      ,
input  wire [ 3:0]      crs2_addr     ,
output wire [31:0]      crs2_rdata    ,

input  wire             crs3_ren      ,
input  wire [ 3:0]      crs3_addr     ,
output wire [31:0]      crs3_rdata    ,

input  wire [ 3:0]      crd_wen       ,
input  wire [ 3:0]      crd_addr      ,
input  wire [31:0]      crd_wdata

);


assign g_clk_req = crd_wen;


reg [7:0] cprs_0 [15:0];
reg [7:0] cprs_1 [15:0];
reg [7:0] cprs_2 [15:0];
reg [7:0] cprs_3 [15:0];

`ifdef FORMAL


genvar i;
wire [31:0] cprs[15:0];

generate for(i = 0; i < 16; i = i + 1) begin
    assign cprs[i] = {cprs_3[i],cprs_2[i],cprs_1[i],cprs_0[i]};

    always @(posedge g_clk) if(!g_resetn) cprs_0[i] <= $anyconst;
    always @(posedge g_clk) if(!g_resetn) cprs_1[i] <= $anyconst;
    always @(posedge g_clk) if(!g_resetn) cprs_2[i] <= $anyconst;
    always @(posedge g_clk) if(!g_resetn) cprs_3[i] <= $anyconst;

end endgenerate


`VTX_REGISTER_PORTS_ASSIGNR(cprs_snoop,cprs)
`endif


reg  [4:0] init_fsm;
wire [4:0] n_init_fsm = init_fsm + 1;

assign cprs_init_done = init_fsm == 15;

always @(posedge g_clk) begin
    if(cprs_init) begin
        init_fsm <= init_fsm == 15 ? 15 : n_init_fsm;
    end else begin
        init_fsm <= 0;
    end
end

wire [ 3:0] wen     = cprs_init ? 4'hF      : crd_wen;
wire [31:0] wdata   = cprs_init ? 32'b0     : crd_wdata;
wire [ 3:0] addr    = cprs_init ? init_fsm  : crd_addr;





assign crs1_rdata = {32{crs1_ren}} & 
    {cprs_3[crs1_addr],cprs_2[crs1_addr],cprs_1[crs1_addr],cprs_0[crs1_addr]};

assign crs2_rdata = {32{crs2_ren}} &
    {cprs_3[crs2_addr],cprs_2[crs2_addr],cprs_1[crs2_addr],cprs_0[crs2_addr]};

assign crs3_rdata = {32{crs3_ren}} &
    {cprs_3[crs3_addr],cprs_2[crs3_addr],cprs_1[crs3_addr],cprs_0[crs3_addr]};





always @(posedge g_clk) if(wen[3]) cprs_3[addr] <= wdata[31:24];
always @(posedge g_clk) if(wen[2]) cprs_2[addr] <= wdata[23:16];
always @(posedge g_clk) if(wen[1]) cprs_1[addr] <= wdata[15: 8];
always @(posedge g_clk) if(wen[0]) cprs_0[addr] <= wdata[ 7: 0];

endmodule
module scarv_cop_cprs (

input  wire             g_clk         ,
output wire             g_clk_req     ,
input  wire             g_resetn      ,

`ifdef FORMAL
`VTX_REGISTER_PORTS_OUT(cprs_snoop)
`endif

input  wire             cprs_init     ,
output wire             cprs_init_done,

input  wire             crs1_ren      ,
input  wire [ 3:0]      crs1_addr     ,
output wire [31:0]      crs1_rdata    ,

input  wire             crs2_ren      ,
input  wire [ 3:0]      crs2_addr     ,
output wire [31:0]      crs2_rdata    ,

input  wire             crs3_ren      ,
input  wire [ 3:0]      crs3_addr     ,
output wire [31:0]      crs3_rdata    ,

input  wire [ 3:0]      crd_wen       ,
input  wire [ 3:0]      crd_addr      ,
input  wire [31:0]      crd_wdata

);



assign g_clk_req = crd_wen;


reg [7:0] cprs_0 [15:0];
reg [7:0] cprs_1 [15:0];
reg [7:0] cprs_2 [15:0];
reg [7:0] cprs_3 [15:0];

`ifdef FORMAL


genvar i;
wire [31:0] cprs[15:0];

generate for(i = 0; i < 16; i = i + 1) begin
    assign cprs[i] = {cprs_3[i],cprs_2[i],cprs_1[i],cprs_0[i]};

    always @(posedge g_clk) if(!g_resetn) cprs_0[i] <= $anyconst;
    always @(posedge g_clk) if(!g_resetn) cprs_1[i] <= $anyconst;
    always @(posedge g_clk) if(!g_resetn) cprs_2[i] <= $anyconst;
    always @(posedge g_clk) if(!g_resetn) cprs_3[i] <= $anyconst;

end endgenerate


`VTX_REGISTER_PORTS_ASSIGNR(cprs_snoop,cprs)
`endif


reg  [4:0] init_fsm;
wire [4:0] n_init_fsm = init_fsm + 1;

assign cprs_init_done = init_fsm == 15;

always @(posedge g_clk) begin
    if(cprs_init) begin
        init_fsm <= init_fsm == 15 ? 15 : n_init_fsm;
    end else begin
        init_fsm <= 0;
    end
end

wire [ 3:0] wen     = cprs_init ? 4'hF      : crd_wen;
wire [31:0] wdata   = cprs_init ? 32'b0     : crd_wdata;
wire [ 3:0] addr    = cprs_init ? init_fsm  : crd_addr;





assign crs1_rdata = {32{crs1_ren}} & 
    {cprs_3[crs1_addr],cprs_2[crs1_addr],cprs_1[crs1_addr],cprs_0[crs1_addr]};

assign crs2_rdata = {32{crs2_ren}} &
    {cprs_3[crs2_addr],cprs_2[crs2_addr],cprs_1[crs2_addr],cprs_0[crs2_addr]};

assign crs3_rdata = {32{crs3_ren}} &
    {cprs_3[crs3_addr],cprs_2[crs3_addr],cprs_1[crs3_addr],cprs_0[crs3_addr]};





always @(posedge g_clk) if(wen[3]) cprs_3[addr] <= wdata[31:24];
always @(posedge g_clk) if(wen[2]) cprs_2[addr] <= wdata[23:16];
always @(posedge g_clk) if(wen[1]) cprs_1[addr] <= wdata[15: 8];
always @(posedge g_clk) if(wen[0]) cprs_0[addr] <= wdata[ 7: 0];

endmodule