data/full_repos/permissive/102388603/uart_tx.v
 line:17: before: "integer"
1: b'%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:48: Operator EQ expects 3 bits on the LHS, but LHS\'s VARREF \'state\' generates 2 bits.\n                                                                 : ... In instance uart_tx\nassign ready = (state == idle) ? 1:0;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:56: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 3 bits.\n                                                                 : ... In instance uart_tx\n state <= idle;\n       ^~\n%Warning-SELRANGE: data/full_repos/permissive/102388603/uart_tx.v:73: Selection index out of range: 12:11 outside 10:0\n                                                                    : ... In instance uart_tx\n     dataUart[dataLen + 4:dataLen + 3] <= 2\'b11;\n             ^\n%Warning-SELRANGE: data/full_repos/permissive/102388603/uart_tx.v:80: Selection index out of range: 11:10 outside 10:0\n                                                                    : ... In instance uart_tx\n     dataUart[dataLen + 3:dataLen + 2] <= 2\'b11;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:82: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'send\' generates 3 bits.\n                                                                 : ... In instance uart_tx\n   state <= send;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:92: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle\' generates 3 bits.\n                                                                 : ... In instance uart_tx\n   state <= idle;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:99: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'waitSnd\' generates 3 bits.\n                                                                 : ... In instance uart_tx\n   state <= waitSnd;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:108: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'send\' generates 3 bits.\n                                                                  : ... In instance uart_tx\n   state <= send;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:105: Operator GT expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'waitSndTimer\' generates 14 bits.\n                                                                  : ... In instance uart_tx\n  if(waitSndTimer > periodUart)\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/102388603/uart_tx.v:61: Operator CASE expects 3 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 2 bits.\n                                                                 : ... In instance uart_tx\n case(state)\n ^~~~\n%Error: Exiting due to 10 warning(s)\n'
function integer log2;
input integer value;
begin
	for (log2=0; value>0; log2=log2+1)
		value = value>>1;
end
endfunction
function integer log2;

input integer value;
begin
	for (log2=0; value>0; log2=log2+1)
		value = value>>1;
end
endfunction