data/full_repos/permissive/147265957/src/counter3.v
data/verilator_xmls/ae40ee19-e54e-47d7-8810-b5d557e3e430.xml
module counter3(
    clk,out
    );
    input clk;
    output reg [2:0] out;
    initial out = 0;
    always @(posedge clk) begin
      out = out + 1;
    end
endmodule
module counter3(
    clk,out
    );

    input clk;
    output reg [2:0] out;
    initial out = 0;
    always @(posedge clk) begin
      out = out + 1;
    end
endmodule