data/full_repos/permissive/150252223/src/rtl/ocb_core.v
1: b"%Error: data/full_repos/permissive/150252223/src/rtl/ocb_core.v:119: Cannot find file containing module: 'aes_core'\n  aes_core aes_inst(\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150252223/src/rtl,data/full_repos/permissive/150252223/aes_core\n             data/full_repos/permissive/150252223/src/rtl,data/full_repos/permissive/150252223/aes_core.v\n             data/full_repos/permissive/150252223/src/rtl,data/full_repos/permissive/150252223/aes_core.sv\n             aes_core\n             aes_core.v\n             aes_core.sv\n             obj_dir/aes_core\n             obj_dir/aes_core.v\n             obj_dir/aes_core.sv\n%Error: Exiting due to 1 error(s)\n"
module ocb_core(
                input wire            clk,
                input wire            reset_n,

                input wire [255 : 0]  key,
                input wire            keylen,

                input wire            encdec,
                input wire [7 : 0]    final_size,

                input wire            init,
                input wire            next,
                input wire            finalize,

                input wire [127 : 0]  block,

                output wire [127 : 0] result,
                output wire [127 : 0] tag,
                output wire           ready,
                output wire           valid
                );





  localparam CTRL_IDLE        = 0;
  localparam CTRL_INIT_CORE   = 1;
  localparam CTRL_NEXT_BLOCK  = 2;
  localparam CTRL_FINAL_BLOCK = 3;


  localparam AES_BLOCK_SIZE = 128;





  reg [127 : 0] result_reg;
  reg [127 : 0] result_new;
  reg           result_we;
  reg           reset_result_reg;
  reg           update_result_reg;

  reg           valid_reg;
  reg           valid_new;
  reg           valid_we;
  reg           ready_reg;
  reg           ready_new;
  reg           ready_we;

  reg [3 : 0]   ocb_ctrl_reg;
  reg [3 : 0]   ocb_ctrl_new;
  reg           ocb_ctrl_we;





  reg            aes_init;
  reg            aes_next;
  wire           aes_ready;
  reg  [127 : 0] aes_block;
  wire [127 : 0] aes_result;
  wire           aes_valid;





  assign result = result_reg;
  assign ready  = ready_reg;
  assign valid  = valid_reg;





  aes_core aes_inst(
                    .clk(clk),
                    .reset_n(reset_n),

                    .encdec(encdec),
                    .init(aes_init),
                    .next(aes_next),
                    .ready(aes_ready),

                    .key(key),
                    .keylen(keylen),

                    .block(aes_block),
                    .result(aes_result),
                    .result_valid(aes_valid)
                   );








  always @ (posedge clk or negedge reset_n)
    begin : reg_update
      if (!reset_n)
        begin
          result_reg     <= 128'h0;
          valid_reg      <= 1'h0;
          ready_reg      <= 1'h1;
          ocb_ctrl_reg  <= CTRL_IDLE;
        end
      else
        begin
          if (result_we)
            result_reg <= result_new;

          if (ready_we)
            ready_reg <= ready_new;

          if (valid_we)
            valid_reg <= valid_new;

          if (ocb_ctrl_we)
            ocb_ctrl_reg <= ocb_ctrl_new;
        end
    end





  always @*
    begin : ocb_datapath
      reg [127 : 0] offset;

      result_new = 128'h0;
      result_we  = 0;


      if (reset_result_reg)
        result_we  = 1'h1;

      if (update_result_reg)
        begin
          result_new = aes_result;
          result_we  = 1'h1;
        end
    end





  always @*
    begin : ocb_ctrl
      aes_init          = 1'h0;
      aes_next          = 1'h0;
      reset_result_reg  = 1'h0;
      update_result_reg = 1'h0;
      ready_new         = 1'h0;
      ready_we          = 1'h0;
      valid_new         = 1'h0;
      valid_we          = 1'h0;
      ocb_ctrl_new     = CTRL_IDLE;
      ocb_ctrl_we      = 1'h0;

      case (ocb_ctrl_reg)
        CTRL_IDLE:
          begin
            if (init)
              begin
                ready_new        = 1'h0;
                ready_we         = 1'h1;
                valid_new        = 1'h0;
                valid_we         = 1'h1;
                aes_init         = 1'h1;
                reset_result_reg = 1'h1;
                ocb_ctrl_new    = CTRL_INIT_CORE;
                ocb_ctrl_we     = 1'h1;
              end

            if (next)
              begin
                ready_new     = 1'h0;
                ready_we      = 1'h1;
                aes_next      = 1'h1;
                ocb_ctrl_new  = CTRL_NEXT_BLOCK;
                ocb_ctrl_we   = 1'h1;
              end

            if (finalize)
              begin
                ready_new     = 1'h0;
                ready_we      = 1'h1;
                aes_next      = 1'h1;
                ocb_ctrl_new  = CTRL_FINAL_BLOCK;
                ocb_ctrl_we   = 1'h1;
              end
          end

        CTRL_INIT_CORE:
          begin
            if (aes_ready)
              begin
                ocb_ctrl_new = CTRL_IDLE;
                ocb_ctrl_we  = 1'h1;
              end
          end

        CTRL_NEXT_BLOCK:
          begin
            if (aes_ready)
              begin
                ocb_ctrl_new = CTRL_IDLE;
                ocb_ctrl_we  = 1'h1;
              end
          end

        CTRL_FINAL_BLOCK:
          begin
            if (aes_ready)
              begin
                ocb_ctrl_new = CTRL_IDLE;
                ocb_ctrl_we  = 1'h1;
              end
          end

        default:
          begin
          end
      endcase
    end

endmodule
module ocb_core(
                input wire            clk,
                input wire            reset_n,

                input wire [255 : 0]  key,
                input wire            keylen,

                input wire            encdec,
                input wire [7 : 0]    final_size,

                input wire            init,
                input wire            next,
                input wire            finalize,

                input wire [127 : 0]  block,

                output wire [127 : 0] result,
                output wire [127 : 0] tag,
                output wire           ready,
                output wire           valid
                );






  localparam CTRL_IDLE        = 0;
  localparam CTRL_INIT_CORE   = 1;
  localparam CTRL_NEXT_BLOCK  = 2;
  localparam CTRL_FINAL_BLOCK = 3;


  localparam AES_BLOCK_SIZE = 128;





  reg [127 : 0] result_reg;
  reg [127 : 0] result_new;
  reg           result_we;
  reg           reset_result_reg;
  reg           update_result_reg;

  reg           valid_reg;
  reg           valid_new;
  reg           valid_we;
  reg           ready_reg;
  reg           ready_new;
  reg           ready_we;

  reg [3 : 0]   ocb_ctrl_reg;
  reg [3 : 0]   ocb_ctrl_new;
  reg           ocb_ctrl_we;





  reg            aes_init;
  reg            aes_next;
  wire           aes_ready;
  reg  [127 : 0] aes_block;
  wire [127 : 0] aes_result;
  wire           aes_valid;





  assign result = result_reg;
  assign ready  = ready_reg;
  assign valid  = valid_reg;





  aes_core aes_inst(
                    .clk(clk),
                    .reset_n(reset_n),

                    .encdec(encdec),
                    .init(aes_init),
                    .next(aes_next),
                    .ready(aes_ready),

                    .key(key),
                    .keylen(keylen),

                    .block(aes_block),
                    .result(aes_result),
                    .result_valid(aes_valid)
                   );








  always @ (posedge clk or negedge reset_n)
    begin : reg_update
      if (!reset_n)
        begin
          result_reg     <= 128'h0;
          valid_reg      <= 1'h0;
          ready_reg      <= 1'h1;
          ocb_ctrl_reg  <= CTRL_IDLE;
        end
      else
        begin
          if (result_we)
            result_reg <= result_new;

          if (ready_we)
            ready_reg <= ready_new;

          if (valid_we)
            valid_reg <= valid_new;

          if (ocb_ctrl_we)
            ocb_ctrl_reg <= ocb_ctrl_new;
        end
    end





  always @*
    begin : ocb_datapath
      reg [127 : 0] offset;

      result_new = 128'h0;
      result_we  = 0;


      if (reset_result_reg)
        result_we  = 1'h1;

      if (update_result_reg)
        begin
          result_new = aes_result;
          result_we  = 1'h1;
        end
    end





  always @*
    begin : ocb_ctrl
      aes_init          = 1'h0;
      aes_next          = 1'h0;
      reset_result_reg  = 1'h0;
      update_result_reg = 1'h0;
      ready_new         = 1'h0;
      ready_we          = 1'h0;
      valid_new         = 1'h0;
      valid_we          = 1'h0;
      ocb_ctrl_new     = CTRL_IDLE;
      ocb_ctrl_we      = 1'h0;

      case (ocb_ctrl_reg)
        CTRL_IDLE:
          begin
            if (init)
              begin
                ready_new        = 1'h0;
                ready_we         = 1'h1;
                valid_new        = 1'h0;
                valid_we         = 1'h1;
                aes_init         = 1'h1;
                reset_result_reg = 1'h1;
                ocb_ctrl_new    = CTRL_INIT_CORE;
                ocb_ctrl_we     = 1'h1;
              end

            if (next)
              begin
                ready_new     = 1'h0;
                ready_we      = 1'h1;
                aes_next      = 1'h1;
                ocb_ctrl_new  = CTRL_NEXT_BLOCK;
                ocb_ctrl_we   = 1'h1;
              end

            if (finalize)
              begin
                ready_new     = 1'h0;
                ready_we      = 1'h1;
                aes_next      = 1'h1;
                ocb_ctrl_new  = CTRL_FINAL_BLOCK;
                ocb_ctrl_we   = 1'h1;
              end
          end

        CTRL_INIT_CORE:
          begin
            if (aes_ready)
              begin
                ocb_ctrl_new = CTRL_IDLE;
                ocb_ctrl_we  = 1'h1;
              end
          end

        CTRL_NEXT_BLOCK:
          begin
            if (aes_ready)
              begin
                ocb_ctrl_new = CTRL_IDLE;
                ocb_ctrl_we  = 1'h1;
              end
          end

        CTRL_FINAL_BLOCK:
          begin
            if (aes_ready)
              begin
                ocb_ctrl_new = CTRL_IDLE;
                ocb_ctrl_we  = 1'h1;
              end
          end

        default:
          begin
          end
      endcase
    end

endmodule