data/full_repos/permissive/122184933/FPGA/data_lane.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/122184933/FPGA/data_lane.v:104: Signal definition not found, creating implicitly: \'ser_hi_z\'\nassign ser_hi_z = (state == LP11) | (state == LP01) | (state == LP00);\n       ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/122184933/FPGA/data_lane.v:111: Signal definition not found, creating implicitly: \'ser_enable\'\n                                                                            : ... Suggested alternative: \'enable\'\nassign ser_enable = ((state == HS) & enable) | (state == SOT) | (state == EOT);\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/122184933/FPGA/data_lane.v:120: Cannot find file containing module: \'data_hs_phy\'\ndata_hs_phy data_hs_phy_i ( \n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/data_hs_phy\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/data_hs_phy.v\n             data/full_repos/permissive/122184933/FPGA,data/full_repos/permissive/122184933/data_hs_phy.sv\n             data_hs_phy\n             data_hs_phy.v\n             data_hs_phy.sv\n             obj_dir/data_hs_phy\n             obj_dir/data_hs_phy.v\n             obj_dir/data_hs_phy.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module data_lane (

	input wire byte_clk, 

	input wire bit_clk, 

	input wire byte_rst, bit_rst,
	

	input wire [7:0] data,

	input wire enable,

	output wire ack,
	

	input wire hs_req,

	output wire hs_rdy, lane_idle,
	

	output wire lp_p, lp_n, hs
);


localparam LP11 		= 0;
localparam LP01 		= 1;
localparam LP00 		= 2;
localparam HS_ZERO 		= 3;
localparam SOT 			= 4;
localparam HS 			= 5;
localparam EOT 			= 6;


reg [2:0] state;

reg [2:0] cnt;

reg last_bit;


wire [7:0] ser_data;


always @ (posedge byte_clk or posedge byte_rst)
begin

	if (byte_rst) begin
		state <= LP11; cnt <= 0; last_bit <= 0;

	end else begin

		case (state)

		LP11 : begin
			if (hs_req)
				state <= LP01;
		end

		LP01 : begin
			state <= LP00;
		end

		LP00 : begin
			state <= HS_ZERO;
		end

		HS_ZERO : begin

			cnt <= cnt + 1'b1;
			if (cnt == 3'b111)
				state <= SOT;
		end

		SOT : begin
			state <= HS;
		end

		HS : begin

			if (enable)
				last_bit <= data[7];

			else if (!hs_req)
				state <= EOT;
		end

		EOT : begin

			cnt <= cnt + 1'b1;
			if (cnt == 3'b111)
				state <= LP11;
		end
		endcase 
	end
end


assign {lp_p, lp_n} = (state == LP11) ? 2'b11 :
					  (state == LP01) ? 2'b01 :
					  2'b00;

assign ser_hi_z = (state == LP11) | (state == LP01) | (state == LP00);

assign ser_data = (state == SOT) ? 8'hB8 :
				  (state == HS) ? data :
				  (state == EOT) ? { (8) { ~last_bit } } :
				  8'h00;

assign ser_enable = ((state == HS) & enable) | (state == SOT) | (state == EOT);

assign hs_rdy = (state == HS);

assign ack = ((state == HS) & enable);

assign lane_idle = (state == LP11);


data_hs_phy data_hs_phy_i ( 

	.byte_clk(byte_clk), .bit_clk(bit_clk),

	.byte_rst(byte_rst), .bit_rst(bit_rst),

	.data(ser_data), .enable(ser_enable), .hi_z(ser_hi_z),

	.out(hs)
);

endmodule
module data_lane (

	input wire byte_clk, 

	input wire bit_clk, 

	input wire byte_rst, bit_rst,
	

	input wire [7:0] data,

	input wire enable,

	output wire ack,
	

	input wire hs_req,

	output wire hs_rdy, lane_idle,
	

	output wire lp_p, lp_n, hs
);



localparam LP11 		= 0;
localparam LP01 		= 1;
localparam LP00 		= 2;
localparam HS_ZERO 		= 3;
localparam SOT 			= 4;
localparam HS 			= 5;
localparam EOT 			= 6;


reg [2:0] state;

reg [2:0] cnt;

reg last_bit;


wire [7:0] ser_data;


always @ (posedge byte_clk or posedge byte_rst)
begin

	if (byte_rst) begin
		state <= LP11; cnt <= 0; last_bit <= 0;

	end else begin

		case (state)

		LP11 : begin
			if (hs_req)
				state <= LP01;
		end

		LP01 : begin
			state <= LP00;
		end

		LP00 : begin
			state <= HS_ZERO;
		end

		HS_ZERO : begin

			cnt <= cnt + 1'b1;
			if (cnt == 3'b111)
				state <= SOT;
		end

		SOT : begin
			state <= HS;
		end

		HS : begin

			if (enable)
				last_bit <= data[7];

			else if (!hs_req)
				state <= EOT;
		end

		EOT : begin

			cnt <= cnt + 1'b1;
			if (cnt == 3'b111)
				state <= LP11;
		end
		endcase 
	end
end


assign {lp_p, lp_n} = (state == LP11) ? 2'b11 :
					  (state == LP01) ? 2'b01 :
					  2'b00;

assign ser_hi_z = (state == LP11) | (state == LP01) | (state == LP00);

assign ser_data = (state == SOT) ? 8'hB8 :
				  (state == HS) ? data :
				  (state == EOT) ? { (8) { ~last_bit } } :
				  8'h00;

assign ser_enable = ((state == HS) & enable) | (state == SOT) | (state == EOT);

assign hs_rdy = (state == HS);

assign ack = ((state == HS) & enable);

assign lane_idle = (state == LP11);


data_hs_phy data_hs_phy_i ( 

	.byte_clk(byte_clk), .bit_clk(bit_clk),

	.byte_rst(byte_rst), .bit_rst(bit_rst),

	.data(ser_data), .enable(ser_enable), .hi_z(ser_hi_z),

	.out(hs)
);

endmodule