data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:39: Operator VAR \'S_IDLE\' expects 2 bits on the Initial value, but Initial value\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                                 : ... In instance everloop_fsm\n  localparam [1:0] S_IDLE = 3\'d0;\n                   ^~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:40: Operator VAR \'S_READ\' expects 2 bits on the Initial value, but Initial value\'s CONST \'3\'h1\' generates 3 bits.\n                                                                                                 : ... In instance everloop_fsm\n  localparam [1:0] S_READ = 3\'d1;\n                   ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:41: Operator VAR \'S_DATA\' expects 2 bits on the Initial value, but Initial value\'s CONST \'3\'h2\' generates 3 bits.\n                                                                                                 : ... In instance everloop_fsm\n  localparam [1:0] S_DATA = 3\'d2;\n                   ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:44: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'S_IDLE\' generates 2 bits.\n                                                                                                 : ... In instance everloop_fsm\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:44: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'S_READ\' generates 2 bits.\n                                                                                                 : ... In instance everloop_fsm\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:44: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'S_DATA\' generates 2 bits.\n                                                                                                 : ... In instance everloop_fsm\n    case(state)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:86: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_IDLE\' generates 2 bits.\n                                                                                                 : ... In instance everloop_fsm\n      state <= S_IDLE;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:91: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_READ\' generates 2 bits.\n                                                                                                 : ... In instance everloop_fsm\n            state <= S_READ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:93: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_IDLE\' generates 2 bits.\n                                                                                                 : ... In instance everloop_fsm\n            state <= S_IDLE;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:97: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_IDLE\' generates 2 bits.\n                                                                                                 : ... In instance everloop_fsm\n            state <= S_IDLE;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:99: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_DATA\' generates 2 bits.\n                                                                                                 : ... In instance everloop_fsm\n          state <= S_DATA;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:96: Operator EQ expects 72 bits on the LHS, but LHS\'s VARREF \'read_count\' generates 8 bits.\n                                                                                                 : ... In instance everloop_fsm\n          if(read_count == 2*N_LEDS)\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:102: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_READ\' generates 2 bits.\n                                                                                                  : ... In instance everloop_fsm\n            state <= S_READ;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:104: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_DATA\' generates 2 bits.\n                                                                                                  : ... In instance everloop_fsm\n          state <= S_DATA;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:106: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_IDLE\' generates 2 bits.\n                                                                                                  : ... In instance everloop_fsm\n          state <= S_IDLE;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:88: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'S_IDLE\' generates 2 bits.\n                                                                                                 : ... In instance everloop_fsm\n      case(state)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:88: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'S_READ\' generates 2 bits.\n                                                                                                 : ... In instance everloop_fsm\n      case(state)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/141596082/voice_core/rtl/wb_everloop/everloop_fsm.v:88: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'S_DATA\' generates 2 bits.\n                                                                                                 : ... In instance everloop_fsm\n      case(state)\n      ^~~~\n%Error: Exiting due to 18 warning(s)\n'
module everloop_fsm #(
  parameter SYS_FREQ_HZ = "mandatory",
  parameter N_LEDS = "mandatory",
  parameter RESET_COUNTER = 12000
) (
  input            clk           ,
  input            resetn        ,
  input            send_complete ,
  output reg       read_en       ,
  output reg [7:0] read_count    ,
  output           reset_everloop
);

  reg [2:0] state         ;
  reg       reset_count_en;

  assign reset_everloop = reset_count_en;

  localparam [1:0] S_IDLE = 3'd0;
  localparam [1:0] S_READ = 3'd1;
  localparam [1:0] S_DATA = 3'd2;

  always @(state) begin
    case(state)
      S_IDLE : begin
        read_en        = 0;
        reset_count_en = 1;
      end
      S_READ : begin
        read_en        = 1;
        reset_count_en = 0;
      end
      S_DATA : begin
        read_en        = 0;
        reset_count_en = 0;
      end
      default : begin
        read_en        = 0;
        reset_count_en = 0;
      end
    endcase
  end

  reg [13:0] reset_count;

  always @(posedge clk or posedge resetn) begin
    if(resetn | ~reset_count_en) begin
      reset_count <= 0;
    end else begin
      if(reset_count_en)
        reset_count <= reset_count + 1;
    end
  end

  always @(posedge clk or posedge resetn) begin
    if(resetn | reset_count_en) begin
      read_count <= 0;
    end else begin
      if(read_en)
        read_count <= read_count + 1;
    end
  end

  always @(posedge clk or posedge resetn) begin
    if(resetn)
      state <= S_IDLE;
    else begin
      case(state)
        S_IDLE : begin
          if(reset_count == RESET_COUNTER)
            state <= S_READ;
          else
            state <= S_IDLE;
        end
        S_READ :
          if(read_count == 2*N_LEDS)
            state <= S_IDLE;
        else
          state <= S_DATA;
        S_DATA :
          if(send_complete)
            state <= S_READ;
        else
          state <= S_DATA;
        default :
          state <= S_IDLE;
      endcase
    end
  end

endmodule
module everloop_fsm #(
  parameter SYS_FREQ_HZ = "mandatory",
  parameter N_LEDS = "mandatory",
  parameter RESET_COUNTER = 12000
) (
  input            clk           ,
  input            resetn        ,
  input            send_complete ,
  output reg       read_en       ,
  output reg [7:0] read_count    ,
  output           reset_everloop
);


  reg [2:0] state         ;
  reg       reset_count_en;

  assign reset_everloop = reset_count_en;

  localparam [1:0] S_IDLE = 3'd0;
  localparam [1:0] S_READ = 3'd1;
  localparam [1:0] S_DATA = 3'd2;

  always @(state) begin
    case(state)
      S_IDLE : begin
        read_en        = 0;
        reset_count_en = 1;
      end
      S_READ : begin
        read_en        = 1;
        reset_count_en = 0;
      end
      S_DATA : begin
        read_en        = 0;
        reset_count_en = 0;
      end
      default : begin
        read_en        = 0;
        reset_count_en = 0;
      end
    endcase
  end

  reg [13:0] reset_count;

  always @(posedge clk or posedge resetn) begin
    if(resetn | ~reset_count_en) begin
      reset_count <= 0;
    end else begin
      if(reset_count_en)
        reset_count <= reset_count + 1;
    end
  end

  always @(posedge clk or posedge resetn) begin
    if(resetn | reset_count_en) begin
      read_count <= 0;
    end else begin
      if(read_en)
        read_count <= read_count + 1;
    end
  end

  always @(posedge clk or posedge resetn) begin
    if(resetn)
      state <= S_IDLE;
    else begin
      case(state)
        S_IDLE : begin
          if(reset_count == RESET_COUNTER)
            state <= S_READ;
          else
            state <= S_IDLE;
        end
        S_READ :
          if(read_count == 2*N_LEDS)
            state <= S_IDLE;
        else
          state <= S_DATA;
        S_DATA :
          if(send_complete)
            state <= S_READ;
        else
          state <= S_DATA;
        default :
          state <= S_IDLE;
      endcase
    end
  end

endmodule