data/full_repos/permissive/212897440/io_module.v
1: b"%Error: data/full_repos/permissive/212897440/io_module.v:39: Cannot find file containing module: 'i2s_sender'\ni2s_sender  #(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/i2s_sender\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/i2s_sender.v\n             data/full_repos/permissive/212897440,data/full_repos/permissive/212897440/i2s_sender.sv\n             i2s_sender\n             i2s_sender.v\n             i2s_sender.sv\n             obj_dir/i2s_sender\n             obj_dir/i2s_sender.v\n             obj_dir/i2s_sender.sv\n%Error: data/full_repos/permissive/212897440/io_module.v:55: Cannot find file containing module: 'i2s_receicer'\ni2s_receicer  #(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/212897440/io_module.v:71: Cannot find file containing module: 'JXADC_controler'\nJXADC_controler JXADC_controler(\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module io_module #( parameter
    sclk_ws_ratio = 64,
    mclk_sclk_ratio = 4,
    d_width = 24
)(

    input  mclk,
    output ad_sclk,
    output ad_ws,
    output da_sclk,
    output da_ws,
    output sd_tx,
    input  sd_rx,

    input signed [d_width-1: 0] l_data_tx,
    input signed [d_width-1: 0] r_data_tx,

    output signed [d_width-1: 0] l_data_rx,
    output signed [d_width-1: 0] r_data_rx,

    input reset,
    










    output  [7: 0]  JXADC

    );



i2s_sender  #(
    .mclk_sclk_ratio(mclk_sclk_ratio),
    .sclk_ws_ratio(sclk_ws_ratio),
    .d_width(d_width)
) i2s_sender (
    .reset_n(reset),
    .mclk(mclk),
    .sclk(da_sclk),
    .ws(da_ws),
    .sd_tx(sd_tx),
    .l_data_tx(l_data_tx),
    .r_data_tx(r_data_tx)
);



i2s_receicer  #(
    .mclk_sclk_ratio(mclk_sclk_ratio),
    .sclk_ws_ratio(sclk_ws_ratio),
    .d_width(d_width)
) i2s_receicer (
    .reset_n(reset),
    .mclk(mclk),
    .sclk(ad_sclk),
    .ws(ad_ws),
    .sd_rx(sd_rx),
    .l_data_rx(l_data_rx),
    .r_data_rx(r_data_rx)
);



JXADC_controler JXADC_controler(
    .ch0(mclk),
    .ch1(ad_sclk),
    .ch2(ad_ws),
    .ch3(sd_rx),
    .ch4(mclk),
    .ch5(da_sclk),
    .ch6(da_ws),
    .ch7(sd_tx),
    .JXADC(JXADC)
);








endmodule
module io_module #( parameter
    sclk_ws_ratio = 64,
    mclk_sclk_ratio = 4,
    d_width = 24
)(

    input  mclk,
    output ad_sclk,
    output ad_ws,
    output da_sclk,
    output da_ws,
    output sd_tx,
    input  sd_rx,

    input signed [d_width-1: 0] l_data_tx,
    input signed [d_width-1: 0] r_data_tx,

    output signed [d_width-1: 0] l_data_rx,
    output signed [d_width-1: 0] r_data_rx,

    input reset,
    










    output  [7: 0]  JXADC

    );




i2s_sender  #(
    .mclk_sclk_ratio(mclk_sclk_ratio),
    .sclk_ws_ratio(sclk_ws_ratio),
    .d_width(d_width)
) i2s_sender (
    .reset_n(reset),
    .mclk(mclk),
    .sclk(da_sclk),
    .ws(da_ws),
    .sd_tx(sd_tx),
    .l_data_tx(l_data_tx),
    .r_data_tx(r_data_tx)
);



i2s_receicer  #(
    .mclk_sclk_ratio(mclk_sclk_ratio),
    .sclk_ws_ratio(sclk_ws_ratio),
    .d_width(d_width)
) i2s_receicer (
    .reset_n(reset),
    .mclk(mclk),
    .sclk(ad_sclk),
    .ws(ad_ws),
    .sd_rx(sd_rx),
    .l_data_rx(l_data_rx),
    .r_data_rx(r_data_rx)
);



JXADC_controler JXADC_controler(
    .ch0(mclk),
    .ch1(ad_sclk),
    .ch2(ad_ws),
    .ch3(sd_rx),
    .ch4(mclk),
    .ch5(da_sclk),
    .ch6(da_ws),
    .ch7(sd_tx),
    .JXADC(JXADC)
);








endmodule