data/full_repos/permissive/196412397/imag_transform.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/196412397/imag_transform.v:124: Operator GTE expects 18 bits on the RHS, but RHS\'s VARREF \'TRA_IMG_WIDTH\' generates 10 bits.\n                                                                         : ... In instance imag_transform\n    if (r_temp_x3 < 0 || r_temp_x3[37:20] >= TRA_IMG_WIDTH) begin\n                                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/196412397/imag_transform.v:130: Operator GTE expects 18 bits on the RHS, but RHS\'s VARREF \'TRA_IMG_DEPTH\' generates 9 bits.\n                                                                         : ... In instance imag_transform\n    if (r_temp_y3 < 0 || r_temp_y3[37:20] >= TRA_IMG_DEPTH) begin\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/196412397/imag_transform.v:138: Operator GTE expects 18 bits on the RHS, but RHS\'s VARREF \'TRA_IMG_DEPTH\' generates 9 bits.\n                                                                         : ... In instance imag_transform\n    if (r_temp_y3 < 0 || r_temp_y3[37:20] >= TRA_IMG_DEPTH ||\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/196412397/imag_transform.v:139: Operator GTE expects 18 bits on the RHS, but RHS\'s VARREF \'TRA_IMG_WIDTH\' generates 10 bits.\n                                                                         : ... In instance imag_transform\n        r_temp_x3 < 0 || r_temp_x3[37:20] >= TRA_IMG_WIDTH) begin\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/196412397/imag_transform.v:166: Operator ASSIGNDLY expects 30 bits on the Assign RHS, but Assign RHS\'s ADD generates 48 bits.\n                                                                         : ... In instance imag_transform\n    r_temp_summ11 <= r_temp_11 + r_temp_21;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/196412397/imag_transform.v:167: Operator ASSIGNDLY expects 30 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_temp_31\' generates 48 bits.\n                                                                         : ... In instance imag_transform\n    r_temp_summ12 <= r_temp_31;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/196412397/imag_transform.v:168: Operator ASSIGNDLY expects 30 bits on the Assign RHS, but Assign RHS\'s ADD generates 48 bits.\n                                                                         : ... In instance imag_transform\n    r_temp_summ21 <= r_temp_12 + r_temp_22;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/196412397/imag_transform.v:169: Operator ASSIGNDLY expects 30 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_temp_32\' generates 48 bits.\n                                                                         : ... In instance imag_transform\n    r_temp_summ22 <= r_temp_32;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/196412397/imag_transform.v:170: Operator ASSIGNDLY expects 30 bits on the Assign RHS, but Assign RHS\'s ADD generates 48 bits.\n                                                                         : ... In instance imag_transform\n    r_temp_summ31 <= r_temp_13 + r_temp_23;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/196412397/imag_transform.v:171: Operator ASSIGNDLY expects 30 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_temp_33\' generates 48 bits.\n                                                                         : ... In instance imag_transform\n    r_temp_summ32 <= r_temp_33;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/196412397/imag_transform.v:191: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'i_pixel\' generates 10 bits.\n                                                                         : ... In instance imag_transform\n    r_x     <=  i_pixel;      \n            ^~\n%Warning-WIDTH: data/full_repos/permissive/196412397/imag_transform.v:192: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'i_line\' generates 9 bits.\n                                                                         : ... In instance imag_transform\n    r_y     <=  i_line;\n            ^~\n%Error: data/full_repos/permissive/196412397/imag_transform.v:217: Cannot find file containing module: \'lookuptable\'\nlookuptable lookuptable(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/lookuptable\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/lookuptable.v\n             data/full_repos/permissive/196412397,data/full_repos/permissive/196412397/lookuptable.sv\n             lookuptable\n             lookuptable.v\n             lookuptable.sv\n             obj_dir/lookuptable\n             obj_dir/lookuptable.v\n             obj_dir/lookuptable.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n'
module imag_transform #(
    parameter   CAM_DATA_WIDTH  = 12,
                CAM_LINE        = 9,
                CAM_PIXEL       = 10












) (
    input           clk,
    input [1:0]     im_p,

    input                           i_we,
    input  [CAM_DATA_WIDTH-1:0]      i_data,
    input  [CAM_LINE-1:0]            i_line,
    input  [CAM_PIXEL-1:0]           i_pixel,

    output                          o_we,
    output [CAM_DATA_WIDTH-1:0]     o_data,
    output [CAM_LINE-1:0]           o_line,
    output [CAM_PIXEL-1:0]          o_pixel,

    output [CAM_LINE-1:0]           o_imag_depth,
    output [CAM_PIXEL-1:0]          o_imag_width,
    output                          o_imag_resized,

    input  [CAM_PIXEL-1:0]       TRA_IMG_WIDTH ,
    input  [CAM_LINE-1:0]        TRA_IMG_DEPTH ,
    input   [24:0]               T11 ,
    input   [24:0]               T12 ,
    input   [24:0]               T13 ,
    input   [24:0]               T21 ,
    input   [24:0]               T22 ,
    input   [24:0]               T23 ,
    input   [24:0]               T31 ,
    input   [24:0]               T32 ,
    input   [24:0]               T33 
);


(* KEEP = "TRUE" *) reg r_we1 = 0,
    r_we2 = 0,
    r_we3 = 0,
    r_we4 = 0,
    r_we5 = 0,
    r_we6 = 0,
    r_we7 = 0;

(* KEEP = "TRUE" *) reg [CAM_DATA_WIDTH-1:0]      
    r_data1 = 0,
    r_data2 = 0,
    r_data3 = 0,
    r_data4 = 0,
    r_data5 = 0,
    r_data6 = 0,
    r_data7 = 0;

(* KEEP = "TRUE" *) reg signed [24:0] 
    r_T11 = 0,
    r_T12 = 0,
    r_T13 = 0,
    r_T21 = 0,
    r_T22 = 0,
    r_T23 = 0,
    r_T31 = 0,
    r_T32 = 0,
    r_T33 = 0;

(* KEEP = "TRUE" *) wire signed [11:0] w_w_inv;

(* KEEP = "TRUE" *) reg [CAM_PIXEL-1:0]  r_new_x = 0;
(* KEEP = "TRUE" *) reg [CAM_LINE-1:0]   r_new_y = 0;

(* KEEP = "TRUE" *) reg signed [37:0]  
    r_temp_x3 = 0,
    r_temp_y3 = 0;

(* KEEP = "TRUE" *) reg signed [24:0]  
    r_temp_w2 = 0,
    r_temp_x2 = 0,
    r_temp_y2 = 0;

(* KEEP = "TRUE" *) reg signed [29:0] 
    r_temp_x1 = 0,
    r_temp_y1 = 0,
    r_temp_w1 = 0;

(* KEEP = "TRUE" *) reg signed [29:0] 
    r_temp_summ11= 0,
    r_temp_summ21= 0,
    r_temp_summ31= 0;

(* KEEP = "TRUE" *) reg signed [29:0] 
    r_temp_summ12= 0,
    r_temp_summ22= 0,
    r_temp_summ32= 0;

(* KEEP = "TRUE" *) reg signed [47:0]  
    r_temp_11 = 0,
    r_temp_12 = 0,
    r_temp_13 = 0,
    r_temp_21 = 0,
    r_temp_22 = 0,
    r_temp_23 = 0,
    r_temp_31 = 0,
    r_temp_32 = 0,
    r_temp_33 = 0;

(* KEEP = "TRUE" *) reg signed [CAM_PIXEL:0]    r_x = 0;
(* KEEP = "TRUE" *) reg signed [CAM_LINE :0]    r_y = 0;
(* KEEP = "TRUE" *) reg signed [1 :0]           r_w = 0;


always@(posedge clk) begin

    if (r_temp_x3 < 0 || r_temp_x3[37:20] >= TRA_IMG_WIDTH) begin
        r_new_x <= 0;
    end else begin
        r_new_x <= r_temp_x3[20+CAM_PIXEL-1:20];
    end 

    if (r_temp_y3 < 0 || r_temp_y3[37:20] >= TRA_IMG_DEPTH) begin
        r_new_y <= 0;
    end else begin
        r_new_y <= r_temp_y3[20 + CAM_LINE-1:20];
    end  

    r_data7 <= r_data6;

    if (r_temp_y3 < 0 || r_temp_y3[37:20] >= TRA_IMG_DEPTH ||
        r_temp_x3 < 0 || r_temp_x3[37:20] >= TRA_IMG_WIDTH) begin
        r_we7 <= 0;
    end else begin
        r_we7 <= r_we6;
    end


    r_temp_x3 <= r_temp_x2 * w_w_inv;
    r_temp_y3 <= r_temp_y2 * w_w_inv;      

    r_data6 <= r_data5;
    r_we6 <= r_we5;

    r_temp_x2 <= r_temp_x1[24:0];
    r_temp_y2 <= r_temp_y1[24:0];
    r_temp_w2 <= r_temp_w1[24:0] ;

    r_data5 <= r_data4;
    r_we5 <= r_we4;

    r_temp_x1 <= r_temp_summ11 + r_temp_summ12;
    r_temp_y1 <= r_temp_summ21 + r_temp_summ22;
    r_temp_w1 <= r_temp_summ31 + r_temp_summ32;

    r_data4 <= r_data3;
    r_we4 <= r_we3;

    r_temp_summ11 <= r_temp_11 + r_temp_21;
    r_temp_summ12 <= r_temp_31;
    r_temp_summ21 <= r_temp_12 + r_temp_22;
    r_temp_summ22 <= r_temp_32;
    r_temp_summ31 <= r_temp_13 + r_temp_23;
    r_temp_summ32 <= r_temp_33;

    r_data3 <= r_data2;
    r_we3 <= r_we2;

    r_temp_11 <= r_x * r_T11;
    r_temp_21 <= r_y * r_T21;
    r_temp_31 <= r_w * r_T31;

    r_temp_12 <= r_x * r_T12;
    r_temp_22 <= r_y * r_T22;
    r_temp_32 <= r_w * r_T32;

    r_temp_13 <= r_x * r_T13;
    r_temp_23 <= r_y * r_T23;
    r_temp_33 <= r_w * r_T33;

    r_data2 <= r_data1;
    r_we2   <= r_we1;

    r_x     <=  i_pixel;
    r_y     <=  i_line;
    r_w     <= 2'sd1;
    r_data1 <= i_data;
    r_we1   <= i_we;
    r_T11 <= T11;
    r_T12 <= T12;
    r_T13 <= T13;
    r_T21 <= T21;
    r_T22 <= T22;
    r_T23 <= T23;
    r_T31 <= T31;
    r_T32 <= T32;
    r_T33 <= T33;









end


lookuptable lookuptable(
    .clk(clk),
    .w(r_temp_w2[15:4]),
    .r_w_inv(w_w_inv)
);













assign o_we =           r_we7;
assign o_data =         r_data7;

assign o_line =         r_new_y;
assign o_pixel =        r_new_x;

assign o_imag_depth =   TRA_IMG_DEPTH;
assign o_imag_width =   TRA_IMG_WIDTH;
assign o_imag_resized = 1'b1;

endmodule
module imag_transform #(
    parameter   CAM_DATA_WIDTH  = 12,
                CAM_LINE        = 9,
                CAM_PIXEL       = 10












) (
    input           clk,
    input [1:0]     im_p,

    input                           i_we,
    input  [CAM_DATA_WIDTH-1:0]      i_data,
    input  [CAM_LINE-1:0]            i_line,
    input  [CAM_PIXEL-1:0]           i_pixel,

    output                          o_we,
    output [CAM_DATA_WIDTH-1:0]     o_data,
    output [CAM_LINE-1:0]           o_line,
    output [CAM_PIXEL-1:0]          o_pixel,

    output [CAM_LINE-1:0]           o_imag_depth,
    output [CAM_PIXEL-1:0]          o_imag_width,
    output                          o_imag_resized,

    input  [CAM_PIXEL-1:0]       TRA_IMG_WIDTH ,
    input  [CAM_LINE-1:0]        TRA_IMG_DEPTH ,
    input   [24:0]               T11 ,
    input   [24:0]               T12 ,
    input   [24:0]               T13 ,
    input   [24:0]               T21 ,
    input   [24:0]               T22 ,
    input   [24:0]               T23 ,
    input   [24:0]               T31 ,
    input   [24:0]               T32 ,
    input   [24:0]               T33 
);



(* KEEP = "TRUE" *) reg r_we1 = 0,
    r_we2 = 0,
    r_we3 = 0,
    r_we4 = 0,
    r_we5 = 0,
    r_we6 = 0,
    r_we7 = 0;

(* KEEP = "TRUE" *) reg [CAM_DATA_WIDTH-1:0]      
    r_data1 = 0,
    r_data2 = 0,
    r_data3 = 0,
    r_data4 = 0,
    r_data5 = 0,
    r_data6 = 0,
    r_data7 = 0;

(* KEEP = "TRUE" *) reg signed [24:0] 
    r_T11 = 0,
    r_T12 = 0,
    r_T13 = 0,
    r_T21 = 0,
    r_T22 = 0,
    r_T23 = 0,
    r_T31 = 0,
    r_T32 = 0,
    r_T33 = 0;

(* KEEP = "TRUE" *) wire signed [11:0] w_w_inv;

(* KEEP = "TRUE" *) reg [CAM_PIXEL-1:0]  r_new_x = 0;
(* KEEP = "TRUE" *) reg [CAM_LINE-1:0]   r_new_y = 0;

(* KEEP = "TRUE" *) reg signed [37:0]  
    r_temp_x3 = 0,
    r_temp_y3 = 0;

(* KEEP = "TRUE" *) reg signed [24:0]  
    r_temp_w2 = 0,
    r_temp_x2 = 0,
    r_temp_y2 = 0;

(* KEEP = "TRUE" *) reg signed [29:0] 
    r_temp_x1 = 0,
    r_temp_y1 = 0,
    r_temp_w1 = 0;

(* KEEP = "TRUE" *) reg signed [29:0] 
    r_temp_summ11= 0,
    r_temp_summ21= 0,
    r_temp_summ31= 0;

(* KEEP = "TRUE" *) reg signed [29:0] 
    r_temp_summ12= 0,
    r_temp_summ22= 0,
    r_temp_summ32= 0;

(* KEEP = "TRUE" *) reg signed [47:0]  
    r_temp_11 = 0,
    r_temp_12 = 0,
    r_temp_13 = 0,
    r_temp_21 = 0,
    r_temp_22 = 0,
    r_temp_23 = 0,
    r_temp_31 = 0,
    r_temp_32 = 0,
    r_temp_33 = 0;

(* KEEP = "TRUE" *) reg signed [CAM_PIXEL:0]    r_x = 0;
(* KEEP = "TRUE" *) reg signed [CAM_LINE :0]    r_y = 0;
(* KEEP = "TRUE" *) reg signed [1 :0]           r_w = 0;


always@(posedge clk) begin

    if (r_temp_x3 < 0 || r_temp_x3[37:20] >= TRA_IMG_WIDTH) begin
        r_new_x <= 0;
    end else begin
        r_new_x <= r_temp_x3[20+CAM_PIXEL-1:20];
    end 

    if (r_temp_y3 < 0 || r_temp_y3[37:20] >= TRA_IMG_DEPTH) begin
        r_new_y <= 0;
    end else begin
        r_new_y <= r_temp_y3[20 + CAM_LINE-1:20];
    end  

    r_data7 <= r_data6;

    if (r_temp_y3 < 0 || r_temp_y3[37:20] >= TRA_IMG_DEPTH ||
        r_temp_x3 < 0 || r_temp_x3[37:20] >= TRA_IMG_WIDTH) begin
        r_we7 <= 0;
    end else begin
        r_we7 <= r_we6;
    end


    r_temp_x3 <= r_temp_x2 * w_w_inv;
    r_temp_y3 <= r_temp_y2 * w_w_inv;      

    r_data6 <= r_data5;
    r_we6 <= r_we5;

    r_temp_x2 <= r_temp_x1[24:0];
    r_temp_y2 <= r_temp_y1[24:0];
    r_temp_w2 <= r_temp_w1[24:0] ;

    r_data5 <= r_data4;
    r_we5 <= r_we4;

    r_temp_x1 <= r_temp_summ11 + r_temp_summ12;
    r_temp_y1 <= r_temp_summ21 + r_temp_summ22;
    r_temp_w1 <= r_temp_summ31 + r_temp_summ32;

    r_data4 <= r_data3;
    r_we4 <= r_we3;

    r_temp_summ11 <= r_temp_11 + r_temp_21;
    r_temp_summ12 <= r_temp_31;
    r_temp_summ21 <= r_temp_12 + r_temp_22;
    r_temp_summ22 <= r_temp_32;
    r_temp_summ31 <= r_temp_13 + r_temp_23;
    r_temp_summ32 <= r_temp_33;

    r_data3 <= r_data2;
    r_we3 <= r_we2;

    r_temp_11 <= r_x * r_T11;
    r_temp_21 <= r_y * r_T21;
    r_temp_31 <= r_w * r_T31;

    r_temp_12 <= r_x * r_T12;
    r_temp_22 <= r_y * r_T22;
    r_temp_32 <= r_w * r_T32;

    r_temp_13 <= r_x * r_T13;
    r_temp_23 <= r_y * r_T23;
    r_temp_33 <= r_w * r_T33;

    r_data2 <= r_data1;
    r_we2   <= r_we1;

    r_x     <=  i_pixel;
    r_y     <=  i_line;
    r_w     <= 2'sd1;
    r_data1 <= i_data;
    r_we1   <= i_we;
    r_T11 <= T11;
    r_T12 <= T12;
    r_T13 <= T13;
    r_T21 <= T21;
    r_T22 <= T22;
    r_T23 <= T23;
    r_T31 <= T31;
    r_T32 <= T32;
    r_T33 <= T33;









end


lookuptable lookuptable(
    .clk(clk),
    .w(r_temp_w2[15:4]),
    .r_w_inv(w_w_inv)
);













assign o_we =           r_we7;
assign o_data =         r_data7;

assign o_line =         r_new_y;
assign o_pixel =        r_new_x;

assign o_imag_depth =   TRA_IMG_DEPTH;
assign o_imag_width =   TRA_IMG_WIDTH;
assign o_imag_resized = 1'b1;

endmodule