data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v
 line:94: before: "/"
1: b'%Warning-STMTDLY: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n       #(CLK_PERIOD/2) Clk_tb = ~Clk_tb;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #(2 * CLK_PERIOD) Reset_tb = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n       #(CLK_PERIOD) Clk_cnt = Clk_cnt + 1;\n       ^\n%Error: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:60: Unsupported: wait statements\n wait (!Reset_tb);     \n ^~~~\n%Error: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:61: syntax error, unexpected \'@\'\n @(posedge Clk_tb);     \n ^\n%Warning-STMTDLY: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #1;   \n ^\n%Error: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:67: syntax error, unexpected \'@\'\n @(posedge Clk_tb);  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:70: syntax error, unexpected \'@\'\n @(posedge PWM_tb);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #15;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/180199545/PlaySound/play_sound_test_tb.v:88: syntax error, unexpected \'@\'\n  @(posedge PWM_tb);\n  ^\n%Error: Exiting due to 5 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module servo_test_tb ;

reg Clk_tb, Reset_tb;
reg [7:0] sw_tb;
wire PWM_tb;
integer  Clk_cnt;

parameter CLK_PERIOD = 20;


generate_pwm gen(
	.sw(sw_tb),
	.reset(Reset_tb),
	.sys_clk(Clk_tb),
	.PWM(PWM_tb)
	);

initial
  begin  : CLK_GENERATOR
    Clk_tb = 0;
    forever
       begin
	      #(CLK_PERIOD/2) Clk_tb = ~Clk_tb;
       end 
  end

initial
  begin  : RESET_GENERATOR
    Reset_tb = 1;
    #(2 * CLK_PERIOD) Reset_tb = 0;
  end

initial
  begin  : CLK_COUNTER
    Clk_cnt = 0;
    forever
       begin
	      #(CLK_PERIOD) Clk_cnt = Clk_cnt + 1;
       end 
  end

initial
  begin  : STIMULUS
	   sw_tb = 8'b00000000;

	wait (!Reset_tb);
	@(posedge Clk_tb);


	@(posedge Clk_tb);
	#1;
	sw_tb = 8'b00000000;
	@(posedge Clk_tb);
	#1;
	sw_tb = 8'b00000001;
	@(posedge PWM_tb);
	@(posedge PWM_tb);
	#5;
	sw_tb = 8'b00000000;
	#10;
	sw_tb = 8'b10000001;
	#15;
	sw_tb = 8'b10000000;
	#20;
	sw_tb = 8'b00000000;

  end
  
task APPLY_STIMULUS;
	input [7:0] switch;
	begin
		#1;
		sw_tb = 8'b00000001;
		@(posedge PWM_tb);
		@(posedge PWM_tb);
	end
endtask


endmodule
module servo_test_tb ;


reg Clk_tb, Reset_tb;
reg [7:0] sw_tb;
wire PWM_tb;
integer  Clk_cnt;

parameter CLK_PERIOD = 20;


generate_pwm gen(
	.sw(sw_tb),
	.reset(Reset_tb),
	.sys_clk(Clk_tb),
	.PWM(PWM_tb)
	);

initial
  begin  : CLK_GENERATOR
    Clk_tb = 0;
    forever
       begin
	      #(CLK_PERIOD/2) Clk_tb = ~Clk_tb;
       end 
  end

initial
  begin  : RESET_GENERATOR
    Reset_tb = 1;
    #(2 * CLK_PERIOD) Reset_tb = 0;
  end

initial
  begin  : CLK_COUNTER
    Clk_cnt = 0;
    forever
       begin
	      #(CLK_PERIOD) Clk_cnt = Clk_cnt + 1;
       end 
  end

initial
  begin  : STIMULUS
	   sw_tb = 8'b00000000;

	wait (!Reset_tb);
	@(posedge Clk_tb);


	@(posedge Clk_tb);
	#1;
	sw_tb = 8'b00000000;
	@(posedge Clk_tb);
	#1;
	sw_tb = 8'b00000001;
	@(posedge PWM_tb);
	@(posedge PWM_tb);
	#5;
	sw_tb = 8'b00000000;
	#10;
	sw_tb = 8'b10000001;
	#15;
	sw_tb = 8'b10000000;
	#20;
	sw_tb = 8'b00000000;

  end
  
task APPLY_STIMULUS;
	input [7:0] switch;
	begin
		#1;
		sw_tb = 8'b00000001;
		@(posedge PWM_tb);
		@(posedge PWM_tb);
	end
endtask


endmodule