data/full_repos/permissive/124591763/debounce/sig_deb_tb.v
 line:25: before: "#"
1: b'%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk <= ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:20: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("sig_deb_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:21: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #1 i_sig <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #2 i_sig <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #1 i_sig <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #3 i_sig <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #1 i_sig <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1 i_sig <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1 i_sig <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #2 i_sig <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #1 i_sig <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #1 i_sig <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #1 i_sig <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #3 i_sig <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #1 i_sig <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #1 i_sig <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #2 i_sig <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #1 i_sig <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #2 i_sig <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #88 i_sig <= 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #5  i_sig <= 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124591763/debounce/sig_deb_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #150\n  ^\n%Error: Exiting due to 2 error(s), 22 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sig_deb_tb;

	reg  clk   = 1'b0;
	reg  i_sig = 1'b0;

	wire o_sig;

	sig_deb #(
		.CLKS_PER_SMPL (2),
		.SMPL_CNT      (2)
	) uut (
		.clk   (clk  ),
		.i_sig (i_sig),
		.o_sig (o_sig)
	);

	always #5 clk <= ~clk;

	initial begin
		$dumpfile("sig_deb_tb.vcd");
		$dumpvars;

		#50

		#1 i_sig <= 1'b1;
		#2 i_sig <= 1'b0;
		#1 i_sig <= 1'b1;
		#3 i_sig <= 1'b0;
		#1 i_sig <= 1'b1;
		#1 i_sig <= 1'b0;
		#1 i_sig <= 1'b1;
		#2 i_sig <= 1'b0;
		#1 i_sig <= 1'b1;
		#1 i_sig <= 1'b0;
		#1 i_sig <= 1'b1;
		#3 i_sig <= 1'b0;
		#1 i_sig <= 1'b1;
		#1 i_sig <= 1'b0;
		#2 i_sig <= 1'b1;
		#1 i_sig <= 1'b0;
		#2 i_sig <= 1'b1;

		#88 i_sig <= 1'b0;
		#5  i_sig <= 1'b1;

		#150

		$display("simulation done");
		$finish;
	end

endmodule
module sig_deb_tb;


	reg  clk   = 1'b0;
	reg  i_sig = 1'b0;

	wire o_sig;

	sig_deb #(
		.CLKS_PER_SMPL (2),
		.SMPL_CNT      (2)
	) uut (
		.clk   (clk  ),
		.i_sig (i_sig),
		.o_sig (o_sig)
	);

	always #5 clk <= ~clk;

	initial begin
		$dumpfile("sig_deb_tb.vcd");
		$dumpvars;

		#50

		#1 i_sig <= 1'b1;
		#2 i_sig <= 1'b0;
		#1 i_sig <= 1'b1;
		#3 i_sig <= 1'b0;
		#1 i_sig <= 1'b1;
		#1 i_sig <= 1'b0;
		#1 i_sig <= 1'b1;
		#2 i_sig <= 1'b0;
		#1 i_sig <= 1'b1;
		#1 i_sig <= 1'b0;
		#1 i_sig <= 1'b1;
		#3 i_sig <= 1'b0;
		#1 i_sig <= 1'b1;
		#1 i_sig <= 1'b0;
		#2 i_sig <= 1'b1;
		#1 i_sig <= 1'b0;
		#2 i_sig <= 1'b1;

		#88 i_sig <= 1'b0;
		#5  i_sig <= 1'b1;

		#150

		$display("simulation done");
		$finish;
	end

endmodule