data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/单周期CPU代码/controlUnit.v
'utf-8' codec can't decode bytes in position 626-627: invalid continuation byte
1: b"%Error: data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/\xe5\x8d\x95\xe5\x91\xa8\xe6\x9c\x9fCPU\xe4\xbb\xa3\xe7\xa0\x81/controlUnit.v:88: syntax error, unexpected INTEGER NUMBER\n    InsMemRW 1;\n             ^\n%Error: data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/\xe5\x8d\x95\xe5\x91\xa8\xe6\x9c\x9fCPU\xe4\xbb\xa3\xe7\xa0\x81/controlUnit.v:181: syntax error, unexpected '?'\n    RegDst  = 0;  ?\n                  ^\n%Error: data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/imports/\xe5\x8d\x95\xe5\x91\xa8\xe6\x9c\x9fCPU\xe4\xbb\xa3\xe7\xa0\x81/controlUnit.v:255: syntax error, unexpected end, expecting endcase\n end\n ^~~\n%Error: Cannot continue\n"
module controlUnit(
	input [5:0]ops,
	input zero,
	input sign,
	output ExtSel,
	output PCWre,
	output insMenRW,
	output RegDst,
	output RegWre,
	output AlUOp,
	output PCSrc,
	output ALUSrcA,
	output ALUSrcB,
	output mRD,
	output mWR,
	output DBDataSrc
);
	input reg[5:0] ops;
	input wire zero, sign;

	output reg ExtSel;
	output reg PCWre;
	output reg insMenRW;
	output reg RegDst;
	output reg RegWre;
	output reg[2:0] AlUOp;
	output reg PCSrc;
	output reg ALUSrcA;
	output reg ALUSrcB;
	output reg mRD;
	output reg mWR;
	output reg DBDataSrc;

	initial begin
		ExtSel = 0;
		PCWre = 1;
		insMenRW = 0;
		RegDst = 0;    
		RegWre = 0;
		ALUop = 0;
		PCSrc = 0;
		ALUSrcA = 0;
		ALUSrcB = 0;
		mRD = 0;
		mWR = 0;
		DBDataSrc = 0;
	end

	always@ (zero or sign or ops)begin
		case(ops)
			6'b000000:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 0;
				PCSrc = 00;
				ALUop = 000;
			end
			6'b000001:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 0;
				ExtSel = 1;
				PCSrc = 00;
				ALUop = 000;
			end
			6'b000010:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 0;
				PCSrc = 00;
				ALUop = 001;
			end
			6'b010000:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 0;
				ExtSel = 0;
				PCSrc = 00;
				ALUop = 011;
			end
			6'b010001:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 0;
				PCSrc = 00;
				ALUop = 100;
			end
			6'b010010:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 0;
				PCSrc = 00;
				ALUop = 011;
			end
			6'b011000:
			begin
				PCWre = 1;
				ALUSrcA = 1;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 1;
				PCSrc = 00;
				ALUop = 010;
			end
			6'b011011:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 1;
				PCSrc = 00;
				ALUop = 101;
			end
			6'b100110:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				mRD = 0;
				mWR = 1;
				RegDst  = 0;  ?
				ExtSel = 1;
				PCSrc = 00;
				ALUop = 000;
			end
			6'b100111:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 1;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 1;
				mWR = 0;
				RegDst  = 0;
				ExtSel = 1;
				PCSrc = 00;
				ALUop = 100;
			end
			6'b110000:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 1;
				if(zero == 0)
					PCSrc = 00;
				else if(zero == 1)
					PCSrc = 01;
				ALUop = 101;
			end
			6'b110001:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst = 1;
				ExtSel = 1;
				if(zero == 1)
					PCSrc = 00;
				else if(zero == 1)
					PCSrc = 00;
				ALUop = 100;
			end
			6'b111000:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 1;
				PCSrc = 10;		ALUop = 101;
			end
			6'b111111:
			begin
				PCWre = 0;
			end
	end



endmodule
module controlUnit(
	input [5:0]ops,
	input zero,
	input sign,
	output ExtSel,
	output PCWre,
	output insMenRW,
	output RegDst,
	output RegWre,
	output AlUOp,
	output PCSrc,
	output ALUSrcA,
	output ALUSrcB,
	output mRD,
	output mWR,
	output DBDataSrc
);

	input reg[5:0] ops;
	input wire zero, sign;

	output reg ExtSel;
	output reg PCWre;
	output reg insMenRW;
	output reg RegDst;
	output reg RegWre;
	output reg[2:0] AlUOp;
	output reg PCSrc;
	output reg ALUSrcA;
	output reg ALUSrcB;
	output reg mRD;
	output reg mWR;
	output reg DBDataSrc;

	initial begin
		ExtSel = 0;
		PCWre = 1;
		insMenRW = 0;
		RegDst = 0;    
		RegWre = 0;
		ALUop = 0;
		PCSrc = 0;
		ALUSrcA = 0;
		ALUSrcB = 0;
		mRD = 0;
		mWR = 0;
		DBDataSrc = 0;
	end

	always@ (zero or sign or ops)begin
		case(ops)
			6'b000000:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 0;
				PCSrc = 00;
				ALUop = 000;
			end
			6'b000001:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 0;
				ExtSel = 1;
				PCSrc = 00;
				ALUop = 000;
			end
			6'b000010:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 0;
				PCSrc = 00;
				ALUop = 001;
			end
			6'b010000:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 0;
				ExtSel = 0;
				PCSrc = 00;
				ALUop = 011;
			end
			6'b010001:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 0;
				PCSrc = 00;
				ALUop = 100;
			end
			6'b010010:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 0;
				PCSrc = 00;
				ALUop = 011;
			end
			6'b011000:
			begin
				PCWre = 1;
				ALUSrcA = 1;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 1;
				PCSrc = 00;
				ALUop = 010;
			end
			6'b011011:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 0;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 1;
				PCSrc = 00;
				ALUop = 101;
			end
			6'b100110:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				mRD = 0;
				mWR = 1;
				RegDst  = 0;  ?
				ExtSel = 1;
				PCSrc = 00;
				ALUop = 000;
			end
			6'b100111:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 1;
				DBDataSrc = 1;
				RegWre = 1;
				InsMemRW = 1;
				mRD = 1;
				mWR = 0;
				RegDst  = 0;
				ExtSel = 1;
				PCSrc = 00;
				ALUop = 100;
			end
			6'b110000:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 1;
				if(zero == 0)
					PCSrc = 00;
				else if(zero == 1)
					PCSrc = 01;
				ALUop = 101;
			end
			6'b110001:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst = 1;
				ExtSel = 1;
				if(zero == 1)
					PCSrc = 00;
				else if(zero == 1)
					PCSrc = 00;
				ALUop = 100;
			end
			6'b111000:
			begin
				PCWre = 1;
				ALUSrcA = 0;
				ALUSrcB = 0;
				DBDataSrc = 0;
				RegWre = 0;
				InsMemRW = 1;
				mRD = 0;
				mWR = 0;
				RegDst  = 1;
				ExtSel = 1;
				PCSrc = 10;		ALUop = 101;
			end
			6'b111111:
			begin
				PCWre = 0;
			end
	end



endmodule