data/full_repos/permissive/214823094/lab_6/project_2/project_2.srcs/sources_1/new/traffic_lights_2.v
data/verilator_xmls/4e60f4d5-05cb-41f5-84ae-4a8cd8665f26.xml
module counter(
    input myclk,
    input ST,
    output reg TS,
    output reg TL
    );
    
    reg [3:0] counter;
    always@(posedge myclk, posedge ST)
    begin
    if(ST)
    begin
        TS<=0;
        TL<=0;
        counter<=4'b0000;
    end
    else
        case(counter)
        4'b0000:
            begin
            TS<=1;
            TL<=0;
            end
        4'b0101:
            begin
            TS<=0;
            TL<=1;
            end
        default: 
            begin
            TS<=0;
            TL<=0;
            end
        endcase
    end
    
endmodule
module counter(
    input myclk,
    input ST,
    output reg TS,
    output reg TL
    );

    
    reg [3:0] counter;
    always@(posedge myclk, posedge ST)
    begin
    if(ST)
    begin
        TS<=0;
        TL<=0;
        counter<=4'b0000;
    end
    else
        case(counter)
        4'b0000:
            begin
            TS<=1;
            TL<=0;
            end
        4'b0101:
            begin
            TS<=0;
            TL<=1;
            end
        default: 
            begin
            TS<=0;
            TL<=0;
            end
        endcase
    end
    
endmodule