data/full_repos/permissive/197224897/Controller/synchronize.v
data/verilator_xmls/37c15684-a514-490d-8b1a-b955faec359b.xml
module synchronize(clk,in,out);
	parameter NSYNC = 2 ;
	input clk;
	input in;
	output out;
	
	reg [NSYNC-2:0] sync;
	reg out;
	
	always @ (posedge clk)
	begin
		{out,sync} <= {sync[NSYNC-2:0],in};
	end
endmodule
module synchronize(clk,in,out);

	parameter NSYNC = 2 ;
	input clk;
	input in;
	output out;
	
	reg [NSYNC-2:0] sync;
	reg out;
	
	always @ (posedge clk)
	begin
		{out,sync} <= {sync[NSYNC-2:0],in};
	end
endmodule