data/full_repos/permissive/185914332/wash_fsm_tb.v
 line:86: before: "reset"
1: b'%Warning-STMTDLY: data/full_repos/permissive/185914332/wash_fsm_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n   #10.0 clk = ~clk;  \n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/185914332/wash_fsm_tb.v:85: syntax error, unexpected \'@\'\n      @(negedge clk) \n      ^\n%Error: data/full_repos/permissive/185914332/wash_fsm_tb.v:88: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Error: data/full_repos/permissive/185914332/wash_fsm_tb.v:91: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Error: data/full_repos/permissive/185914332/wash_fsm_tb.v:94: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Error: data/full_repos/permissive/185914332/wash_fsm_tb.v:97: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/185914332/wash_fsm_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n  while(drain != 1) begin #1; end\n                          ^\n%Error: data/full_repos/permissive/185914332/wash_fsm_tb.v:101: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/185914332/wash_fsm_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n      while(ready != 1) begin #1; end\n                              ^\n%Error: data/full_repos/permissive/185914332/wash_fsm_tb.v:107: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Error: data/full_repos/permissive/185914332/wash_fsm_tb.v:110: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Error: data/full_repos/permissive/185914332/wash_fsm_tb.v:113: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Error: data/full_repos/permissive/185914332/wash_fsm_tb.v:116: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/185914332/wash_fsm_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n  while(drain != 1) begin #1; end\n                          ^\n%Error: data/full_repos/permissive/185914332/wash_fsm_tb.v:120: syntax error, unexpected \'@\'\n      @(negedge clk)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/185914332/wash_fsm_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n      while(ready != 1) begin #1; end\n                              ^\n%Error: Exiting due to 11 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;


	reg reset;
	reg clk;
	reg start;
	reg full;
	reg empty;
	reg cold;


	wire ready;
	wire water_in;
	wire heat_r;
	wire wash;
	wire drain;
	wire speed;


	wash_fsm uut (
		.reset(reset), 
		.clk(clk), 
		.start(start), 
		.full(full), 
		.empty(empty), 
		.cold(cold), 
		.ready(ready), 
		.water_in(water_in), 
		.heat_r(heat_r), 
		.wash(wash), 
		.drain(drain), 
		.speed(speed)
	);
   

   always
   #10.0 clk = ~clk;

   initial begin

		reset = 1;
		clk = 1;
		start = 0;
		full = 0;
		empty = 0;
		cold = 0;
      

      $display("Washing Machine FSM");
		

      @(negedge clk) 
         reset = 0;
		$display("Time = %t ns, reset assigned '0'", $time*10);
      @(negedge clk)
         start = 1;
      $display("Time = %t ns, start assigned '1'", $time*10);
      @(negedge clk)
         full = 1;
      $display("Time = %t ns, full assigned '1'", $time*10);
      @(negedge clk)
         cold = 1;
      $display("Time = %t ns, cold assigned '1'", $time*10);
      @(negedge clk)
         cold = 0;
      $display("Time = %t ns, cold assigned '0'", $time*10);
		while(drain != 1) begin #1; end
      @(negedge clk)
         empty = 1;
      while(ready != 1) begin #1; end
      $stop;		
  
				
      @(negedge clk)
         start = 1;
      $display("Time = %t ns, start assigned '1'", $time*10);
      @(negedge clk)
         full = 1;
      $display("Time = %t ns, full assigned '1'", $time*10);
      @(negedge clk)
         cold = 1;
      $display("Time = %t ns, cold assigned '1'", $time*10);
      @(negedge clk)
         cold = 0;
      $display("Time = %t ns, cold assigned '0'", $time*10);
		while(drain != 1) begin #1; end
      @(negedge clk)
         empty = 1;
      while(ready != 1) begin #1; end
      $stop;		
		end 
		
      always @(posedge ready)
         $display("Time = %t ns, entering Ready state", $time*10);
      always @(posedge water_in)
         $display("Time = %t ns, entering Water In state", $time*10);
      always @(posedge wash)
         $display("Time = %t ns, entering Wash state", $time*10);	
      always @(posedge drain)
         $display("Time = %t ns, entering Drain state", $time*10);
      always @(posedge speed)
         $display("Time = %t ns, entering Speed state", $time*10);
      always @(posedge heat_r)
         $display("Time = %t ns, heat_r asserted", $time*10);
      always @(negedge heat_r)
         $display("Time = %t ns, heat_r de-asserted", $time*10);
			
endmodule
module testbench;



	reg reset;
	reg clk;
	reg start;
	reg full;
	reg empty;
	reg cold;


	wire ready;
	wire water_in;
	wire heat_r;
	wire wash;
	wire drain;
	wire speed;


	wash_fsm uut (
		.reset(reset), 
		.clk(clk), 
		.start(start), 
		.full(full), 
		.empty(empty), 
		.cold(cold), 
		.ready(ready), 
		.water_in(water_in), 
		.heat_r(heat_r), 
		.wash(wash), 
		.drain(drain), 
		.speed(speed)
	);
   

   always
   #10.0 clk = ~clk;

   initial begin

		reset = 1;
		clk = 1;
		start = 0;
		full = 0;
		empty = 0;
		cold = 0;
      

      $display("Washing Machine FSM");
		

      @(negedge clk) 
         reset = 0;
		$display("Time = %t ns, reset assigned '0'", $time*10);
      @(negedge clk)
         start = 1;
      $display("Time = %t ns, start assigned '1'", $time*10);
      @(negedge clk)
         full = 1;
      $display("Time = %t ns, full assigned '1'", $time*10);
      @(negedge clk)
         cold = 1;
      $display("Time = %t ns, cold assigned '1'", $time*10);
      @(negedge clk)
         cold = 0;
      $display("Time = %t ns, cold assigned '0'", $time*10);
		while(drain != 1) begin #1; end
      @(negedge clk)
         empty = 1;
      while(ready != 1) begin #1; end
      $stop;		
  
				
      @(negedge clk)
         start = 1;
      $display("Time = %t ns, start assigned '1'", $time*10);
      @(negedge clk)
         full = 1;
      $display("Time = %t ns, full assigned '1'", $time*10);
      @(negedge clk)
         cold = 1;
      $display("Time = %t ns, cold assigned '1'", $time*10);
      @(negedge clk)
         cold = 0;
      $display("Time = %t ns, cold assigned '0'", $time*10);
		while(drain != 1) begin #1; end
      @(negedge clk)
         empty = 1;
      while(ready != 1) begin #1; end
      $stop;		
		end 
		
      always @(posedge ready)
         $display("Time = %t ns, entering Ready state", $time*10);
      always @(posedge water_in)
         $display("Time = %t ns, entering Water In state", $time*10);
      always @(posedge wash)
         $display("Time = %t ns, entering Wash state", $time*10);	
      always @(posedge drain)
         $display("Time = %t ns, entering Drain state", $time*10);
      always @(posedge speed)
         $display("Time = %t ns, entering Speed state", $time*10);
      always @(posedge heat_r)
         $display("Time = %t ns, heat_r asserted", $time*10);
      always @(negedge heat_r)
         $display("Time = %t ns, heat_r de-asserted", $time*10);
			
endmodule