data/full_repos/permissive/211316121/lab7_1/Traffic.v
data/verilator_xmls/d80df452-d447-43cb-b1a0-9552c0d2c2a2.xml
module Traffic_Top(
    input clk,
    input [1:0] sw,
    output [5:0] led
    );
    wire clr=sw[0];
    wire resetDIV;
    wire resetTRA=sw[1];
    wire oneSec,sec15,sec45;
    
    oneSecond top_1s(clk,clr,oneSec);
    
    clkdiv top_15_45(oneSec,resetDIV,sec15,sec45);
    
    Traffic top_tra(sec15,sec45,oneSec,resetTRA,led,resetDIV);
    
endmodule
module Traffic_Top(
    input clk,
    input [1:0] sw,
    output [5:0] led
    );

    wire clr=sw[0];
    wire resetDIV;
    wire resetTRA=sw[1];
    wire oneSec,sec15,sec45;
    
    oneSecond top_1s(clk,clr,oneSec);
    
    clkdiv top_15_45(oneSec,resetDIV,sec15,sec45);
    
    Traffic top_tra(sec15,sec45,oneSec,resetTRA,led,resetDIV);
    
endmodule