data/full_repos/permissive/123796236/alu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/123796236/alu.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alu.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alu.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alu.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/123796236/alu.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu(alu_Result, alu_zeroFlag, input1, input2, aluCtrl);

output reg [31:0] alu_Result;
input [31:0] input1, input2;
output reg alu_zeroFlag;
input [3:0] aluCtrl;

always@(input1 or input2 or aluCtrl)
begin

	case (aluCtrl)
		4'b0000 : alu_Result = input1 & input2;
		4'b0001 : alu_Result = input1 | input2;
		4'b0010 : alu_Result = input1 + input2;
		4'b0110 : alu_Result = input1 - input2;
		4'b0111 : if (input1 < input2) alu_Result = 32'd1; 
			else alu_Result = 32'd0;
		default : alu_Result = 32'hxxxxxxxx;
	endcase

	if (alu_Result == 32'd0)
		alu_zeroFlag = 1;
	else 
		alu_zeroFlag = 0;

end
endmodule
module alu(alu_Result, alu_zeroFlag, input1, input2, aluCtrl);


output reg [31:0] alu_Result;
input [31:0] input1, input2;
output reg alu_zeroFlag;
input [3:0] aluCtrl;

always@(input1 or input2 or aluCtrl)
begin

	case (aluCtrl)
		4'b0000 : alu_Result = input1 & input2;
		4'b0001 : alu_Result = input1 | input2;
		4'b0010 : alu_Result = input1 + input2;
		4'b0110 : alu_Result = input1 - input2;
		4'b0111 : if (input1 < input2) alu_Result = 32'd1; 
			else alu_Result = 32'd0;
		default : alu_Result = 32'hxxxxxxxx;
	endcase

	if (alu_Result == 32'd0)
		alu_zeroFlag = 1;
	else 
		alu_zeroFlag = 0;

end
endmodule