data/full_repos/permissive/176378198/src/alu.v
1: b"%Error: data/full_repos/permissive/176378198/src/alu.v:3: Expecting include filename. Found: TEXT\n`include `GRVM_PATH(arithmetic/alu/add_sub_alu.v) \n                   ^\n%Error: data/full_repos/permissive/176378198/src/alu.v:4: Expecting include filename. Found: TEXT\n`include `GRVM_PATH(interfacing/register.v) \n                   ^\n%Error: data/full_repos/permissive/176378198/src/alu.v:5: Expecting include filename. Found: TEXT\n`include `GRVM_PATH(interfacing/tri_state_buffer.v) \n                   ^\n%Error: data/full_repos/permissive/176378198/src/alu.v:3: Define or directive not defined: '`GRVM_PATHarithmetic'\n `GRVM_PATHarithmetic/alu/add_sub_alu.v)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/176378198/src/alu.v:3: syntax error, unexpected '/'\n `GRVM_PATHarithmetic/alu/add_sub_alu.v)\n                     ^\n%Error: data/full_repos/permissive/176378198/src/alu.v:4: Define or directive not defined: '`GRVM_PATHinterfacing'\n `GRVM_PATHinterfacing/register.v)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/176378198/src/alu.v:5: Define or directive not defined: '`GRVM_PATHinterfacing'\n `GRVM_PATHinterfacing/tri_state_buffer.v)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module alu(
    inout [7 : 0] bus,
    input clk,
    input rst,

    input AI,
    input BI,
    input AO,
    input BO,

    input EO,
    input SU,

    output CY,
    output Z
    );

    wire [7 : 0] reg_A_out;
    register reg_A [7 : 0] (
        .in(bus),
        .clk(clk),
        .clr(rst),
        .load(AI),
        .out(reg_A_out)
    );

    wire [7 : 0] reg_B_out;
    register reg_B [7 : 0] (
        .in(bus),
        .clk(clk),
        .clr(rst),
        .load(BI),
        .out(reg_B_out)
    );

    add_sub_alu #(.SIZE(8)) add_sub_alu_inst (
        .A(reg_A_out),
        .B(reg_B_out),
        .bus(bus),

        .subtract(SU),
        .output_enable(EO),
        .carry(carry),
        .zero(zero)
    );

    tri_state_buffer buffer_A [7 : 0] (
        .in(reg_A_out),
        .enable(AO),
        .out(bus)
    );

    tri_state_buffer buffer_B [7 : 0] (
        .in(reg_B_out),
        .enable(BO),
        .out(bus)
    );

endmodule
module alu(
    inout [7 : 0] bus,
    input clk,
    input rst,

    input AI,
    input BI,
    input AO,
    input BO,

    input EO,
    input SU,

    output CY,
    output Z
    );


    wire [7 : 0] reg_A_out;
    register reg_A [7 : 0] (
        .in(bus),
        .clk(clk),
        .clr(rst),
        .load(AI),
        .out(reg_A_out)
    );

    wire [7 : 0] reg_B_out;
    register reg_B [7 : 0] (
        .in(bus),
        .clk(clk),
        .clr(rst),
        .load(BI),
        .out(reg_B_out)
    );

    add_sub_alu #(.SIZE(8)) add_sub_alu_inst (
        .A(reg_A_out),
        .B(reg_B_out),
        .bus(bus),

        .subtract(SU),
        .output_enable(EO),
        .carry(carry),
        .zero(zero)
    );

    tri_state_buffer buffer_A [7 : 0] (
        .in(reg_A_out),
        .enable(AO),
        .out(bus)
    );

    tri_state_buffer buffer_B [7 : 0] (
        .in(reg_B_out),
        .enable(BO),
        .out(bus)
    );

endmodule