data/full_repos/permissive/132304455/src/alu1.v
data/verilator_xmls/08501cab-b376-455c-ab93-4e15e0decd47.xml
module full_adder(sum, cout, a, b, cin);
    output sum, cout;
    input  a, b, cin;
    wire   partial_s, partial_c1, partial_c2;

    assign sum  = a ^ b ^ cin;
    assign cout = (a & b) | ((a ^ b) & cin);

endmodule
module full_adder(sum, cout, a, b, cin);

    output sum, cout;
    input  a, b, cin;
    wire   partial_s, partial_c1, partial_c2;

    assign sum  = a ^ b ^ cin;
    assign cout = (a & b) | ((a ^ b) & cin);

endmodule