data/full_repos/permissive/188434311/verilog/fifo/async_fifo/async_fifo_grey_code.vh
 line:9: before: "localparam"
1: b"%Error: data/full_repos/permissive/188434311/verilog/fifo/async_fifo/async_fifo_grey_code.vh:98: syntax error, unexpected ':'\n    { GREY_6 , GREY_0 } :\n                        ^\n%Error: data/full_repos/permissive/188434311/verilog/fifo/async_fifo/async_fifo_grey_code.vh:121: syntax error, unexpected ':'\n    { GREY_1  , GREY_1 } : \n                         ^\n%Error: Exiting due to 2 error(s)\n"
function bin_to_grey;
  input [ 3: 0 ] inbin;
  case( inbin )
    BIN_0  :  bin_to_grey = GREY_0 ;
    BIN_1  :  bin_to_grey = GREY_1 ;
    BIN_2  :  bin_to_grey = GREY_2 ;
    BIN_3  :  bin_to_grey = GREY_3 ;
    BIN_4  :  bin_to_grey = GREY_4 ;
    BIN_5  :  bin_to_grey = GREY_5 ;
    BIN_6  :  bin_to_grey = GREY_6 ;
    BIN_7  :  bin_to_grey = GREY_7 ;
    BIN_8  :  bin_to_grey = GREY_8 ;
    BIN_9  :  bin_to_grey = GREY_9 ;
    BIN_10  :  bin_to_grey = GREY_10 ;
    BIN_11  :  bin_to_grey = GREY_11 ;
    default : bin_to_grey = GREY_0 ;

  endcase
endfunction
function bin_to_grey;

  input [ 3: 0 ] inbin;
  case( inbin )
    BIN_0  :  bin_to_grey = GREY_0 ;
    BIN_1  :  bin_to_grey = GREY_1 ;
    BIN_2  :  bin_to_grey = GREY_2 ;
    BIN_3  :  bin_to_grey = GREY_3 ;
    BIN_4  :  bin_to_grey = GREY_4 ;
    BIN_5  :  bin_to_grey = GREY_5 ;
    BIN_6  :  bin_to_grey = GREY_6 ;
    BIN_7  :  bin_to_grey = GREY_7 ;
    BIN_8  :  bin_to_grey = GREY_8 ;
    BIN_9  :  bin_to_grey = GREY_9 ;
    BIN_10  :  bin_to_grey = GREY_10 ;
    BIN_11  :  bin_to_grey = GREY_11 ;
    default : bin_to_grey = GREY_0 ;

  endcase
endfunction