data/full_repos/permissive/109936328/pipeline/id.v
None: at end of input
1: b'%Error: data/full_repos/permissive/109936328/pipeline/id.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.v\n             data/full_repos/permissive/109936328/pipeline,data/full_repos/permissive/109936328/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:2: Cannot find include file: alu_op.vh\n`include "alu_op.vh" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:3: Cannot find include file: opcodes.vh\n`include "opcodes.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:70: Define or directive not defined: \'`ADDR_W\'\n  input [`ADDR_W - 1:0] i_pc;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:71: Define or directive not defined: \'`INSTR_W\'\n  input [`INSTR_W - 1:0] i_instr;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:73: Define or directive not defined: \'`INSTR_W\'\n  wire [`INSTR_W - 1:0] s_instr;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:75: Define or directive not defined: \'`REG_IDX_W\'\n  input [`REG_IDX_W - 1:0] i_ex_dest_reg;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:76: Define or directive not defined: \'`DEST_SRC_W\'\n  input [`DEST_SRC_W - 1:0] i_ex_dest_src;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:77: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_ex_alu_eval;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:79: Define or directive not defined: \'`REG_IDX_W\'\n  input [`REG_IDX_W - 1:0] i_me_dest_reg;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:80: Define or directive not defined: \'`DEST_SRC_W\'\n  input [`DEST_SRC_W - 1:0] i_me_dest_src;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:81: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_me_dest_data;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:85: Define or directive not defined: \'`REG_IDX_W\'\n  input [`REG_IDX_W - 1:0] i_wb_dest_reg;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:86: Define or directive not defined: \'`WORD_W\'\n  input [`WORD_W - 1:0] i_wb_dest_data;\n         ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:89: Define or directive not defined: \'`ADDR_W\'\n  output [`ADDR_W - 1:0] o_pc;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:90: Define or directive not defined: \'`INSTR_W\'\n  output [`INSTR_W - 1:0] o_instr;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:93: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] r_pc;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:94: Define or directive not defined: \'`INSTR_W\'\n  reg [`INSTR_W - 1:0] r_instr;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:97: Define or directive not defined: \'`ALU_OP_W\'\n  output [`ALU_OP_W - 1:0] o_alu_op;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:100: Define or directive not defined: \'`WORD_W\'\n  output reg[`WORD_W - 1:0] o_alu_data_a;\n             ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:101: Define or directive not defined: \'`WORD_W\'\n  output reg[`WORD_W - 1:0] o_alu_data_b;\n             ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:103: Define or directive not defined: \'`WORD_W\'\n  output [`WORD_W - 1:0] o_imm;\n          ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:105: Define or directive not defined: \'`MEM_OP_W\'\n  output [`MEM_OP_W - 1:0] o_mem_op;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:110: Define or directive not defined: \'`DEST_SRC_W\'\n  output [`DEST_SRC_W - 1:0] o_dest_src;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:111: Define or directive not defined: \'`REG_IDX_W\'\n  output [`REG_IDX_W - 1:0] o_dest_reg;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:112: Define or directive not defined: \'`INSTR_XPR_DEST\'\n  assign o_dest_reg = `INSTR_XPR_DEST(s_instr);\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:117: Define or directive not defined: \'`ALU_SRC_A_W\'\n  wire [`ALU_SRC_A_W - 1:0] s_alu_src_a;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:118: Define or directive not defined: \'`ALU_SRC_B_W\'\n  wire [`ALU_SRC_B_W - 1:0] s_alu_src_b;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:120: Define or directive not defined: \'`MEM_OP_W\'\n  wire [`MEM_OP_W - 1:0] s_mem_op;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:121: Define or directive not defined: \'`DEST_SRC_W\'\n  wire [`DEST_SRC_W - 1:0] s_dest_src;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:125: Define or directive not defined: \'`REG_IDX_W\'\n  wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:125: Define or directive not defined: \'`INSTR_XPR_A\'\n  wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);\n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:126: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] s_reg_data_a;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:127: Define or directive not defined: \'`REG_IDX_W\'\n  wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:127: Define or directive not defined: \'`INSTR_XPR_B\'\n  wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);\n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:128: Define or directive not defined: \'`WORD_W\'\n  wire [`WORD_W - 1:0] s_reg_data_b;\n        ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:133: Define or directive not defined: \'`ADDR_W\'\n  reg [`ADDR_W - 1:0] r_temp_pc;\n       ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:134: Define or directive not defined: \'`INSTR_W\'\n  reg [`INSTR_W - 1:0] r_temp_instr;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:166: Define or directive not defined: \'`MEM_OP_NOP\'\n  assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:166: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;\n                                        ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:167: Define or directive not defined: \'`DEST_SRC_NONE\'\n  assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;\n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:167: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;\n                                             ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:212: Define or directive not defined: \'`WORD_W\'\n  function [`WORD_W - 1:0] fwd_alu_data;\n            ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:213: Define or directive not defined: \'`REG_IDX_W\'\n    input [`REG_IDX_W - 1:0] reg_num;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:214: Define or directive not defined: \'`WORD_W\'\n    input [`WORD_W - 1:0] reg_data;\n           ^~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:217: Define or directive not defined: \'`DEST_SRC_ALU\'\n      i_ex_dest_src == `DEST_SRC_ALU) begin\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:217: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      i_ex_dest_src == `DEST_SRC_ALU) begin\n                                    ^\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:221: Define or directive not defined: \'`DEST_SRC_NONE\'\n      i_me_dest_src != `DEST_SRC_NONE) begin\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:236: Define or directive not defined: \'`REG_IDX_W\'\n    input [`REG_IDX_W - 1:0] reg_num;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipeline/id.v:239: Define or directive not defined: \'`DEST_SRC_MEM\'\n      i_ex_dest_src == `DEST_SRC_MEM) begin\n                       ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module id(

  clk,

  clr,

  stall,

  rf_reset,


  i_pc,

  i_instr,


  i_ex_alu_eval,
  i_ex_dest_reg,
  i_ex_dest_src,


  i_me_dest_reg,
  i_me_dest_src,
  i_me_dest_data,


  i_wb_dest_en,
  i_wb_dest_reg,
  i_wb_dest_data,


  o_pc,

  o_instr,


  o_alu_op,


  o_alu_data_a,
  o_alu_data_b,

  o_imm,


  o_mem_op,


  o_dest_src,

  o_dest_reg,

  o_branch_op,

  o_mem_hazard
);

  parameter DUMP_VARS = 0;
  parameter DUMP_FILE = "a.vcd";

  input clk;
  input clr;
  input stall;
  input rf_reset;

  input [`ADDR_W - 1:0] i_pc;
  input [`INSTR_W - 1:0] i_instr;

  wire [`INSTR_W - 1:0] s_instr;

  input [`REG_IDX_W - 1:0] i_ex_dest_reg;
  input [`DEST_SRC_W - 1:0] i_ex_dest_src;
  input [`WORD_W - 1:0] i_ex_alu_eval;

  input [`REG_IDX_W - 1:0] i_me_dest_reg;
  input [`DEST_SRC_W - 1:0] i_me_dest_src;
  input [`WORD_W - 1:0] i_me_dest_data;


  input i_wb_dest_en;
  input [`REG_IDX_W - 1:0] i_wb_dest_reg;
  input [`WORD_W - 1:0] i_wb_dest_data;


  output [`ADDR_W - 1:0] o_pc;
  output [`INSTR_W - 1:0] o_instr;


  reg [`ADDR_W - 1:0] r_pc;
  reg [`INSTR_W - 1:0] r_instr;


  output [`ALU_OP_W - 1:0] o_alu_op;


  output reg[`WORD_W - 1:0] o_alu_data_a;
  output reg[`WORD_W - 1:0] o_alu_data_b;

  output [`WORD_W - 1:0] o_imm;

  output [`MEM_OP_W - 1:0] o_mem_op;

  output o_branch_op;


  output [`DEST_SRC_W - 1:0] o_dest_src;
  output [`REG_IDX_W - 1:0] o_dest_reg;
  assign o_dest_reg = `INSTR_XPR_DEST(s_instr);

  output o_mem_hazard;


  wire [`ALU_SRC_A_W - 1:0] s_alu_src_a;
  wire [`ALU_SRC_B_W - 1:0] s_alu_src_b;

  wire [`MEM_OP_W - 1:0] s_mem_op;
  wire [`DEST_SRC_W - 1:0] s_dest_src;
  wire s_branch_op;


  wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);
  wire [`WORD_W - 1:0] s_reg_data_a;
  wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);
  wire [`WORD_W - 1:0] s_reg_data_b;

  reg s_mem_hazard_reg_a;
  reg s_mem_hazard_reg_b;

  reg [`ADDR_W - 1:0] r_temp_pc;
  reg [`INSTR_W - 1:0] r_temp_instr;
  reg r_temp_valid;

  always@(posedge clk) begin
    if(clr == 1) begin
      r_pc <= 0;
      r_instr <= 0;
      r_temp_valid <= 0;

    end else begin
      if(r_temp_valid == 0) begin
        r_pc <= i_pc;
        r_instr <= i_instr;
      end

      if(stall == 1) begin
        r_temp_pc <= r_pc;
        r_temp_instr <= r_instr;
      end
      r_temp_valid <= stall;
    end
  end


  assign o_pc = (~stall & r_temp_valid) ? r_temp_pc : r_pc;
  assign o_instr = (~stall & r_temp_valid) ? r_temp_instr : r_instr;

  assign s_instr = o_instr;


  assign o_mem_hazard = s_mem_hazard_reg_a | s_mem_hazard_reg_b;

  assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;
  assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;
  assign o_branch_op = ~stall & s_branch_op;


  id_decoder dec(
    .instr(s_instr),

    .alu_op(o_alu_op),
    .imm(o_imm),

    .mem_op(s_mem_op),

    .alu_a_src(s_alu_src_a),
    .alu_b_src(s_alu_src_b),
    .dest_src(s_dest_src),

    .branch_op(s_branch_op)
  );


  register_file#(
    .DUMP_VARS(DUMP_VARS),
    .DUMP_FILE(DUMP_FILE)
  ) rf(
    .clk(clk),
    .aresetn(rf_reset),


    .rd_reg_a(s_reg_a),
    .rd_reg_b(s_reg_b),


    .rd_data_a(s_reg_data_a),
    .rd_data_b(s_reg_data_b),


    .wr_en(i_wb_dest_en),

    .wr_reg(i_wb_dest_reg),

    .wr_data(i_wb_dest_data)
  );


  function [`WORD_W - 1:0] fwd_alu_data;
    input [`REG_IDX_W - 1:0] reg_num;
    input [`WORD_W - 1:0] reg_data;
  begin
    if(reg_num != 0 && reg_num == i_ex_dest_reg &&
      i_ex_dest_src == `DEST_SRC_ALU) begin

      fwd_alu_data = i_ex_alu_eval;
    end else if(reg_num != 0 && reg_num == i_me_dest_reg &&
      i_me_dest_src != `DEST_SRC_NONE) begin

      fwd_alu_data = i_me_dest_data;
    end else if(reg_num != 0 && reg_num == i_wb_dest_reg &&
      i_wb_dest_en == 1) begin

      fwd_alu_data = i_wb_dest_data;
    end else begin
      fwd_alu_data = reg_data;
    end
  end
  endfunction


  function mem_hazard_stall;
    input [`REG_IDX_W - 1:0] reg_num;
  begin
    if(reg_num != 0 && reg_num == i_ex_dest_reg &&
      i_ex_dest_src == `DEST_SRC_MEM) begin

      mem_hazard_stall = 1;
    end else begin
      mem_hazard_stall = 0;
    end
  end
  endfunction


  always@(s_reg_a, s_reg_data_a, s_reg_b, s_reg_data_b,
    i_ex_alu_eval, i_ex_dest_reg, i_ex_dest_src,
    i_me_dest_data, i_me_dest_reg, i_me_dest_src,
    i_wb_dest_data, i_wb_dest_reg, i_wb_dest_en,
    r_pc, o_imm) begin

    s_mem_hazard_reg_a = 0;
    case(s_alu_src_a)
      `ALU_SRC_A_XPR: begin
        o_alu_data_a = fwd_alu_data(s_reg_a, s_reg_data_a);
        s_mem_hazard_reg_a = mem_hazard_stall(s_reg_a);
      end
      `ALU_SRC_A_PC: o_alu_data_a = r_pc;
      `ALU_SRC_A_NONE: o_alu_data_a = 0;
      default: o_alu_data_a = 0;
    endcase

    s_mem_hazard_reg_b = 0;
    case(s_alu_src_b)
      `ALU_SRC_B_XPR: begin
        o_alu_data_b = fwd_alu_data(s_reg_b, s_reg_data_b);
        s_mem_hazard_reg_b = mem_hazard_stall(s_reg_b);
      end
      `ALU_SRC_B_IMM: o_alu_data_b = o_imm;
      `ALU_SRC_B_INSTR_SIZE: o_alu_data_b = `INSTR_W / 8;
      `ALU_SRC_B_NONE: o_alu_data_b = 0;
      default: o_alu_data_b = 0;
    endcase
  end
endmodule
module id(

  clk,

  clr,

  stall,

  rf_reset,


  i_pc,

  i_instr,


  i_ex_alu_eval,
  i_ex_dest_reg,
  i_ex_dest_src,


  i_me_dest_reg,
  i_me_dest_src,
  i_me_dest_data,


  i_wb_dest_en,
  i_wb_dest_reg,
  i_wb_dest_data,


  o_pc,

  o_instr,


  o_alu_op,


  o_alu_data_a,
  o_alu_data_b,

  o_imm,


  o_mem_op,


  o_dest_src,

  o_dest_reg,

  o_branch_op,

  o_mem_hazard
);


  parameter DUMP_VARS = 0;
  parameter DUMP_FILE = "a.vcd";

  input clk;
  input clr;
  input stall;
  input rf_reset;

  input [`ADDR_W - 1:0] i_pc;
  input [`INSTR_W - 1:0] i_instr;

  wire [`INSTR_W - 1:0] s_instr;

  input [`REG_IDX_W - 1:0] i_ex_dest_reg;
  input [`DEST_SRC_W - 1:0] i_ex_dest_src;
  input [`WORD_W - 1:0] i_ex_alu_eval;

  input [`REG_IDX_W - 1:0] i_me_dest_reg;
  input [`DEST_SRC_W - 1:0] i_me_dest_src;
  input [`WORD_W - 1:0] i_me_dest_data;


  input i_wb_dest_en;
  input [`REG_IDX_W - 1:0] i_wb_dest_reg;
  input [`WORD_W - 1:0] i_wb_dest_data;


  output [`ADDR_W - 1:0] o_pc;
  output [`INSTR_W - 1:0] o_instr;


  reg [`ADDR_W - 1:0] r_pc;
  reg [`INSTR_W - 1:0] r_instr;


  output [`ALU_OP_W - 1:0] o_alu_op;


  output reg[`WORD_W - 1:0] o_alu_data_a;
  output reg[`WORD_W - 1:0] o_alu_data_b;

  output [`WORD_W - 1:0] o_imm;

  output [`MEM_OP_W - 1:0] o_mem_op;

  output o_branch_op;


  output [`DEST_SRC_W - 1:0] o_dest_src;
  output [`REG_IDX_W - 1:0] o_dest_reg;
  assign o_dest_reg = `INSTR_XPR_DEST(s_instr);

  output o_mem_hazard;


  wire [`ALU_SRC_A_W - 1:0] s_alu_src_a;
  wire [`ALU_SRC_B_W - 1:0] s_alu_src_b;

  wire [`MEM_OP_W - 1:0] s_mem_op;
  wire [`DEST_SRC_W - 1:0] s_dest_src;
  wire s_branch_op;


  wire [`REG_IDX_W - 1:0] s_reg_a = `INSTR_XPR_A(s_instr);
  wire [`WORD_W - 1:0] s_reg_data_a;
  wire [`REG_IDX_W - 1:0] s_reg_b = `INSTR_XPR_B(s_instr);
  wire [`WORD_W - 1:0] s_reg_data_b;

  reg s_mem_hazard_reg_a;
  reg s_mem_hazard_reg_b;

  reg [`ADDR_W - 1:0] r_temp_pc;
  reg [`INSTR_W - 1:0] r_temp_instr;
  reg r_temp_valid;

  always@(posedge clk) begin
    if(clr == 1) begin
      r_pc <= 0;
      r_instr <= 0;
      r_temp_valid <= 0;

    end else begin
      if(r_temp_valid == 0) begin
        r_pc <= i_pc;
        r_instr <= i_instr;
      end

      if(stall == 1) begin
        r_temp_pc <= r_pc;
        r_temp_instr <= r_instr;
      end
      r_temp_valid <= stall;
    end
  end


  assign o_pc = (~stall & r_temp_valid) ? r_temp_pc : r_pc;
  assign o_instr = (~stall & r_temp_valid) ? r_temp_instr : r_instr;

  assign s_instr = o_instr;


  assign o_mem_hazard = s_mem_hazard_reg_a | s_mem_hazard_reg_b;

  assign o_mem_op = stall ? `MEM_OP_NOP : s_mem_op;
  assign o_dest_src = stall ? `DEST_SRC_NONE : s_dest_src;
  assign o_branch_op = ~stall & s_branch_op;


  id_decoder dec(
    .instr(s_instr),

    .alu_op(o_alu_op),
    .imm(o_imm),

    .mem_op(s_mem_op),

    .alu_a_src(s_alu_src_a),
    .alu_b_src(s_alu_src_b),
    .dest_src(s_dest_src),

    .branch_op(s_branch_op)
  );


  register_file#(
    .DUMP_VARS(DUMP_VARS),
    .DUMP_FILE(DUMP_FILE)
  ) rf(
    .clk(clk),
    .aresetn(rf_reset),


    .rd_reg_a(s_reg_a),
    .rd_reg_b(s_reg_b),


    .rd_data_a(s_reg_data_a),
    .rd_data_b(s_reg_data_b),


    .wr_en(i_wb_dest_en),

    .wr_reg(i_wb_dest_reg),

    .wr_data(i_wb_dest_data)
  );


  function [`WORD_W - 1:0] fwd_alu_data;
    input [`REG_IDX_W - 1:0] reg_num;
    input [`WORD_W - 1:0] reg_data;
  begin
    if(reg_num != 0 && reg_num == i_ex_dest_reg &&
      i_ex_dest_src == `DEST_SRC_ALU) begin

      fwd_alu_data = i_ex_alu_eval;
    end else if(reg_num != 0 && reg_num == i_me_dest_reg &&
      i_me_dest_src != `DEST_SRC_NONE) begin

      fwd_alu_data = i_me_dest_data;
    end else if(reg_num != 0 && reg_num == i_wb_dest_reg &&
      i_wb_dest_en == 1) begin

      fwd_alu_data = i_wb_dest_data;
    end else begin
      fwd_alu_data = reg_data;
    end
  end
  endfunction


  function mem_hazard_stall;
    input [`REG_IDX_W - 1:0] reg_num;
  begin
    if(reg_num != 0 && reg_num == i_ex_dest_reg &&
      i_ex_dest_src == `DEST_SRC_MEM) begin

      mem_hazard_stall = 1;
    end else begin
      mem_hazard_stall = 0;
    end
  end
  endfunction


  always@(s_reg_a, s_reg_data_a, s_reg_b, s_reg_data_b,
    i_ex_alu_eval, i_ex_dest_reg, i_ex_dest_src,
    i_me_dest_data, i_me_dest_reg, i_me_dest_src,
    i_wb_dest_data, i_wb_dest_reg, i_wb_dest_en,
    r_pc, o_imm) begin

    s_mem_hazard_reg_a = 0;
    case(s_alu_src_a)
      `ALU_SRC_A_XPR: begin
        o_alu_data_a = fwd_alu_data(s_reg_a, s_reg_data_a);
        s_mem_hazard_reg_a = mem_hazard_stall(s_reg_a);
      end
      `ALU_SRC_A_PC: o_alu_data_a = r_pc;
      `ALU_SRC_A_NONE: o_alu_data_a = 0;
      default: o_alu_data_a = 0;
    endcase

    s_mem_hazard_reg_b = 0;
    case(s_alu_src_b)
      `ALU_SRC_B_XPR: begin
        o_alu_data_b = fwd_alu_data(s_reg_b, s_reg_data_b);
        s_mem_hazard_reg_b = mem_hazard_stall(s_reg_b);
      end
      `ALU_SRC_B_IMM: o_alu_data_b = o_imm;
      `ALU_SRC_B_INSTR_SIZE: o_alu_data_b = `INSTR_W / 8;
      `ALU_SRC_B_NONE: o_alu_data_b = 0;
      default: o_alu_data_b = 0;
    endcase
  end
endmodule