data/full_repos/permissive/143278/ivltests/pr2117488.v
 line:20: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2117488.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("%0d + %0d + %0d = %0d", A, B, C, Y);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr2117488.v:13: Operator ADD expects 32 or 9 bits on the RHS, but RHS\'s VARREF \'C\' generates 1 bits.\n                                                                         : ... In instance ternary_add\nassign Y = Enable ? A + B + C : 0;\n                          ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ternary_add();

reg        Enable;

reg  [7:0] A;
reg  [7:0] B;
reg        C;
wire [8:0] Y;

assign Y = Enable ? A + B + C : 0;

initial begin
  Enable = 1'b1;
  A = 8'd1;
  B = 8'd254;
  C = 1'd1;
  #1 $display("%0d + %0d + %0d = %0d", A, B, C, Y);
  if (Y !== 9'd256) begin
     $display("FAILED");
     $finish;
  end
  $display("PASSED");
end

endmodule
module ternary_add();


reg        Enable;

reg  [7:0] A;
reg  [7:0] B;
reg        C;
wire [8:0] Y;

assign Y = Enable ? A + B + C : 0;

initial begin
  Enable = 1'b1;
  A = 8'd1;
  B = 8'd254;
  C = 1'd1;
  #1 $display("%0d + %0d + %0d = %0d", A, B, C, Y);
  if (Y !== 9'd256) begin
     $display("FAILED");
     $finish;
  end
  $display("PASSED");
end

endmodule