data/full_repos/permissive/155713836/src/fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/155713836/src/fifo.v:52: Operator LT expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'tail_pointer\' generates 5 bits.\n                                                                  : ... In instance fifo\n      if (tail_pointer < (FIFO_DEPTH-1)) begin\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/155713836/src/fifo.v:71: Operator LT expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'head_pointer\' generates 5 bits.\n                                                                  : ... In instance fifo\n      if (head_pointer < (FIFO_DEPTH-1)) begin\n                       ^\n%Error: Exiting due to 2 warning(s)\n'
module fifo (
  clk,

  i_read_packet_en,
  i_write_packet_en,
  i_write_packet,

  o_read_packet,
  o_empty_flag,
  o_full_flag
);

  parameter FIFO_DEPTH = 32;
  parameter LOG2_FIFO_DEPTH = 5;
  parameter DATA_LINE_WIDTH = 40;
  parameter CONTROL_LINE_WIDTH = 0;


  input clk;
  input i_read_packet_en;
  input i_write_packet_en;
  input [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_write_packet;


  output reg [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] o_read_packet;
  output o_empty_flag;
  output o_full_flag;


  reg [(DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1):0] FIFO [0:(FIFO_DEPTH-1)];
  reg [FIFO_DEPTH-1:0] FIFOvalid = 'd0;

  reg [LOG2_FIFO_DEPTH-1:0] head_pointer = 'd0;
  reg [LOG2_FIFO_DEPTH-1:0] tail_pointer = 'd0;


  always @ (posedge clk) begin

    if ( (i_write_packet_en == 1'b1) && (FIFOvalid[tail_pointer] == 1'b0) ) begin
      FIFO[tail_pointer] = i_write_packet;
      FIFOvalid[tail_pointer] = 1'b1;


      if (tail_pointer < (FIFO_DEPTH-1)) begin
        tail_pointer = tail_pointer + 1'b1;
      end else begin
        tail_pointer = 'd0;
      end

    end


    if ( (i_read_packet_en == 1'b1) && (FIFOvalid[head_pointer] == 1'b1) ) begin



        o_read_packet = FIFO[head_pointer];


      FIFOvalid[head_pointer] = 1'b0;


      if (head_pointer < (FIFO_DEPTH-1)) begin
        head_pointer = head_pointer + 1'b1;
      end else begin
        head_pointer = 'd0;
      end

    end else begin
      o_read_packet = 'b0;
    end

  end



  assign o_empty_flag = !FIFOvalid[head_pointer];
  assign o_full_flag = FIFOvalid[tail_pointer];
  
endmodule
module fifo (
  clk,

  i_read_packet_en,
  i_write_packet_en,
  i_write_packet,

  o_read_packet,
  o_empty_flag,
  o_full_flag
);


  parameter FIFO_DEPTH = 32;
  parameter LOG2_FIFO_DEPTH = 5;
  parameter DATA_LINE_WIDTH = 40;
  parameter CONTROL_LINE_WIDTH = 0;


  input clk;
  input i_read_packet_en;
  input i_write_packet_en;
  input [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] i_write_packet;


  output reg [DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1:0] o_read_packet;
  output o_empty_flag;
  output o_full_flag;


  reg [(DATA_LINE_WIDTH+CONTROL_LINE_WIDTH-1):0] FIFO [0:(FIFO_DEPTH-1)];
  reg [FIFO_DEPTH-1:0] FIFOvalid = 'd0;

  reg [LOG2_FIFO_DEPTH-1:0] head_pointer = 'd0;
  reg [LOG2_FIFO_DEPTH-1:0] tail_pointer = 'd0;


  always @ (posedge clk) begin

    if ( (i_write_packet_en == 1'b1) && (FIFOvalid[tail_pointer] == 1'b0) ) begin
      FIFO[tail_pointer] = i_write_packet;
      FIFOvalid[tail_pointer] = 1'b1;


      if (tail_pointer < (FIFO_DEPTH-1)) begin
        tail_pointer = tail_pointer + 1'b1;
      end else begin
        tail_pointer = 'd0;
      end

    end


    if ( (i_read_packet_en == 1'b1) && (FIFOvalid[head_pointer] == 1'b1) ) begin



        o_read_packet = FIFO[head_pointer];


      FIFOvalid[head_pointer] = 1'b0;


      if (head_pointer < (FIFO_DEPTH-1)) begin
        head_pointer = head_pointer + 1'b1;
      end else begin
        head_pointer = 'd0;
      end

    end else begin
      o_read_packet = 'b0;
    end

  end



  assign o_empty_flag = !FIFOvalid[head_pointer];
  assign o_full_flag = FIFOvalid[tail_pointer];
  
endmodule