data/full_repos/permissive/195073547/verilog_source/add_2_1/Input_Port.v
 line:35: before: "localparam"
1: b"%Error: data/full_repos/permissive/195073547/verilog_source/add_2_1/Input_Port.v:117: Cannot find file containing module: 'write_b_in'\n    write_b_in #(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/195073547/verilog_source/add_2_1,data/full_repos/permissive/195073547/write_b_in\n             data/full_repos/permissive/195073547/verilog_source/add_2_1,data/full_repos/permissive/195073547/write_b_in.v\n             data/full_repos/permissive/195073547/verilog_source/add_2_1,data/full_repos/permissive/195073547/write_b_in.sv\n             write_b_in\n             write_b_in.v\n             write_b_in.sv\n             obj_dir/write_b_in\n             obj_dir/write_b_in.v\n             obj_dir/write_b_in.sv\n%Error: data/full_repos/permissive/195073547/verilog_source/add_2_1/Input_Port.v:160: Cannot find file containing module: 'xpm_memory_tdpram_yosys'\n        xpm_memory_tdpram_yosys # (\n        ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/195073547/verilog_source/add_2_1/Input_Port.v:224: Cannot find file containing module: 'xpm_memory_tdpram_yosys'\n        xpm_memory_tdpram_yosys # (\n        ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/195073547/verilog_source/add_2_1/Input_Port.v:422: Cannot find file containing module: 'read_b_in'\n    read_b_in #(\n    ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module Input_Port#(
    parameter PACKET_BITS = 97,
    parameter NUM_LEAF_BITS = 6,
    parameter NUM_PORT_BITS = 4,
    parameter NUM_ADDR_BITS = 7,
    parameter PAYLOAD_BITS = 64, 
    parameter NUM_IN_PORTS = 1, 
    parameter NUM_OUT_PORTS = 1,
    parameter NUM_BRAM_ADDR_BITS = 7,
    parameter PORT_No = 2,
    parameter SYN_TYPE = "yosys",
    parameter FREESPACE_UPDATE_SIZE = 64,
    localparam BRAM_DEPTH = 2**(NUM_BRAM_ADDR_BITS-1)*(PAYLOAD_BITS+1)
    )(
    input clk_bft,
    input clk_user,
    input reset,
    

    output freespace_update,
    output [PACKET_BITS-1:0] packet_from_input_port,
    input [PACKET_BITS-1:0] din_leaf_bft2interface,
    input [NUM_LEAF_BITS-1:0] src_leaf,
    input [NUM_PORT_BITS-1:0] src_port,
    

    output [PAYLOAD_BITS-1:0] dout2user,
    output vld2user,
    input ack_user2b_in
    
    );

    wire vldBit;
    wire [NUM_PORT_BITS-1:0] port;
    wire [NUM_ADDR_BITS-1:0] addr;
    wire [PAYLOAD_BITS-1:0] payload;
    
    wire [PACKET_BITS-1-NUM_LEAF_BITS-NUM_PORT_BITS-PAYLOAD_BITS-1:0] red_bits;
    wire [PAYLOAD_BITS-1:0] update_data;
    
    wire [NUM_ADDR_BITS-1:0] addra;

    wire [PAYLOAD_BITS:0] dina;
    wire wea;
    wire wea_0;
    wire wea_1;
    
    
    wire [NUM_ADDR_BITS-2:0] addrb_0;

    wire [PAYLOAD_BITS:0] doutb_0;
    wire web_0;
    
        
    wire [NUM_ADDR_BITS-2:0] addrb_1;

    wire [PAYLOAD_BITS:0] doutb_1;
    wire web_1;
    
    
    assign wea_0 = addra[0] ? 0 : wea;
    assign wea_1 = addra[0] ? wea : 0;
    
    

    
    assign red_bits = 0;
    assign update_data = 1;
    assign packet_from_input_port = {1'b1, src_leaf, src_port, red_bits, update_data};
    
    
    assign vldBit = din_leaf_bft2interface[PACKET_BITS-1];
    assign port = din_leaf_bft2interface[PACKET_BITS-2-NUM_LEAF_BITS:PACKET_BITS-2-NUM_LEAF_BITS-NUM_PORT_BITS+1];
    assign addr = din_leaf_bft2interface[PAYLOAD_BITS+NUM_ADDR_BITS-1:PAYLOAD_BITS];
    assign payload = din_leaf_bft2interface[PAYLOAD_BITS-1:0];



    
    

    write_b_in #(
        .NUM_PORT_BITS(NUM_PORT_BITS),
        .PAYLOAD_BITS(PAYLOAD_BITS),
        .NUM_ADDR_BITS(NUM_ADDR_BITS),
        .PORT_No(PORT_No)
        )wbi(
        .clk(clk_bft), 
        .reset(reset), 
        .port(port), 
        .addr(addr), 
        .vldBit(vldBit), 
        .payload(payload), 
        .wea(wea), 
        .addra(addra), 
        .dina(dina)
        );




   
    

wire [PAYLOAD_BITS:0] b_in_dinb;
assign b_in_dinb = 0;

generate
    if(SYN_TYPE == "yosys")
    begin      
        xpm_memory_tdpram_yosys # (

          .MEMORY_SIZE        (BRAM_DEPTH),
          .MEMORY_PRIMITIVE   ("block"),
          .CLOCKING_MODE      ("independent_clock"),
          .MEMORY_INIT_FILE   ("none"),
          .MEMORY_INIT_PARAM  (""    ),
          .USE_MEM_INIT       (1),
          .WAKEUP_TIME        ("disable_sleep"),
          .MESSAGE_CONTROL    (0),
          .ECC_MODE           ("no_ecc"),
          .AUTO_SLEEP_TIME    (0),
        

          .WRITE_DATA_WIDTH_A (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_A  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_A (PAYLOAD_BITS+1),
          .ADDR_WIDTH_A       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_A ("0"),
          .READ_LATENCY_A     (1),
          .WRITE_MODE_A       ("write_first"),
        

          .WRITE_DATA_WIDTH_B (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_B  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_B (PAYLOAD_BITS+1),
          .ADDR_WIDTH_B       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_B ("0"),
          .READ_LATENCY_B     (1),
          .WRITE_MODE_B       ("write_first")
        
        ) xpm_memory_tdpram_inst_0 (

          .sleep          (1'b0),

          .clka           (clk_bft),
          .rsta           (reset),
          .ena            (1'b1),
          .regcea         (1'b1),
          .wea            (wea_0),
          .addra          (addra[NUM_ADDR_BITS-1:1]),
          .dina           (dina),
          .injectsbiterra (1'b0),
          .injectdbiterra (1'b0),
          .douta          (),
          .sbiterra       (),
          .dbiterra       (),

          .clkb           (clk_user),
          .rstb           (reset),
          .enb            (1'b1),
          .regceb         (1'b1),
          .web            (web_0),
          .addrb          (addrb_0),
          .dinb           (0),
          .injectsbiterrb (1'b0),
          .injectdbiterrb (1'b0),
          .doutb          (doutb_0),
          .sbiterrb       (),
          .dbiterrb       ()
        );
        
        
        
        xpm_memory_tdpram_yosys # (

          .MEMORY_SIZE        (BRAM_DEPTH),
          .MEMORY_PRIMITIVE   ("block"),
          .CLOCKING_MODE      ("independent_clock"),
          .MEMORY_INIT_FILE   ("none"),
          .MEMORY_INIT_PARAM  (""    ),
          .USE_MEM_INIT       (1),
          .WAKEUP_TIME        ("disable_sleep"),
          .MESSAGE_CONTROL    (0),
          .ECC_MODE           ("no_ecc"),
          .AUTO_SLEEP_TIME    (0),
        

          .WRITE_DATA_WIDTH_A (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_A  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_A (PAYLOAD_BITS+1),
          .ADDR_WIDTH_A       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_A ("0"),
          .READ_LATENCY_A     (1),
          .WRITE_MODE_A       ("write_first"),
        

          .WRITE_DATA_WIDTH_B (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_B  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_B (PAYLOAD_BITS+1),
          .ADDR_WIDTH_B       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_B ("0"),
          .READ_LATENCY_B     (1),
          .WRITE_MODE_B       ("write_first")
        
        ) xpm_memory_tdpram_inst_1 (

          .sleep          (1'b0),

          .clka           (clk_bft),
          .rsta           (reset),
          .ena            (1'b1),
          .regcea         (1'b1),
          .wea            (wea_1),
          .addra          (addra[NUM_ADDR_BITS-1:1]),
          .dina           (dina),
          .injectsbiterra (1'b0),
          .injectdbiterra (1'b0),
          .douta          (),
          .sbiterra       (),
          .dbiterra       (),

          .clkb           (clk_user),
          .rstb           (reset),
          .enb            (1'b1),
          .regceb         (1'b1),
          .web            (web_1),
          .addrb          (addrb_1),
          .dinb           (0),
          .injectsbiterrb (1'b0),
          .injectdbiterrb (1'b0),
          .doutb          (doutb_1),
          .sbiterrb       (),
          .dbiterrb       ()
        );

    end else begin

        
              
        xpm_memory_tdpram # (

          .MEMORY_SIZE        (BRAM_DEPTH),
          .MEMORY_PRIMITIVE   ("block"),
          .CLOCKING_MODE      ("independent_clock"),
          .MEMORY_INIT_FILE   ("none"),
          .MEMORY_INIT_PARAM  (""    ),
          .USE_MEM_INIT       (1),
          .WAKEUP_TIME        ("disable_sleep"),
          .MESSAGE_CONTROL    (0),
          .ECC_MODE           ("no_ecc"),
          .AUTO_SLEEP_TIME    (0),
        

          .WRITE_DATA_WIDTH_A (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_A  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_A (PAYLOAD_BITS+1),
          .ADDR_WIDTH_A       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_A ("0"),
          .READ_LATENCY_A     (1),
          .WRITE_MODE_A       ("write_first"),
        

          .WRITE_DATA_WIDTH_B (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_B  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_B (PAYLOAD_BITS+1),
          .ADDR_WIDTH_B       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_B ("0"),
          .READ_LATENCY_B     (1),
          .WRITE_MODE_B       ("write_first")
        
        ) xpm_memory_tdpram_inst_0 (

          .sleep          (1'b0),

          .clka           (clk_bft),
          .rsta           (reset),
          .ena            (1'b1),
          .regcea         (1'b1),
          .wea            (wea_0),
          .addra          (addra[NUM_ADDR_BITS-1:1]),
          .dina           (dina),
          .injectsbiterra (1'b0),
          .injectdbiterra (1'b0),
          .douta          (),
          .sbiterra       (),
          .dbiterra       (),

          .clkb           (clk_user),
          .rstb           (reset),
          .enb            (1'b1),
          .regceb         (1'b1),
          .web            (web_0),
          .addrb          (addrb_0),
          .dinb           (0),
          .injectsbiterrb (1'b0),
          .injectdbiterrb (1'b0),
          .doutb          (doutb_0),
          .sbiterrb       (),
          .dbiterrb       ()
        );
        
        
        
        xpm_memory_tdpram # (

          .MEMORY_SIZE        (BRAM_DEPTH),
          .MEMORY_PRIMITIVE   ("block"),
          .CLOCKING_MODE      ("independent_clock"),
          .MEMORY_INIT_FILE   ("none"),
          .MEMORY_INIT_PARAM  (""    ),
          .USE_MEM_INIT       (1),
          .WAKEUP_TIME        ("disable_sleep"),
          .MESSAGE_CONTROL    (0),
          .ECC_MODE           ("no_ecc"),
          .AUTO_SLEEP_TIME    (0),
        

          .WRITE_DATA_WIDTH_A (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_A  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_A (PAYLOAD_BITS+1),
          .ADDR_WIDTH_A       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_A ("0"),
          .READ_LATENCY_A     (1),
          .WRITE_MODE_A       ("write_first"),
        

          .WRITE_DATA_WIDTH_B (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_B  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_B (PAYLOAD_BITS+1),
          .ADDR_WIDTH_B       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_B ("0"),
          .READ_LATENCY_B     (1),
          .WRITE_MODE_B       ("write_first")
        
        ) xpm_memory_tdpram_inst_1 (

          .sleep          (1'b0),

          .clka           (clk_bft),
          .rsta           (reset),
          .ena            (1'b1),
          .regcea         (1'b1),
          .wea            (wea_1),
          .addra          (addra[NUM_ADDR_BITS-1:1]),
          .dina           (dina),
          .injectsbiterra (1'b0),
          .injectdbiterra (1'b0),
          .douta          (),
          .sbiterra       (),
          .dbiterra       (),

          .clkb           (clk_user),
          .rstb           (reset),
          .enb            (1'b1),
          .regceb         (1'b1),
          .web            (web_1),
          .addrb          (addrb_1),
          .dinb           (0),
          .injectsbiterrb (1'b0),
          .injectdbiterrb (1'b0),
          .doutb          (doutb_1),
          .sbiterrb       (),
          .dbiterrb       ()
        );
        
    end
endgenerate

  


    read_b_in #(
        .FREESPACE_UPDATE_SIZE(FREESPACE_UPDATE_SIZE),
        .PAYLOAD_BITS(PAYLOAD_BITS),
        .NUM_ADDR_BITS(NUM_ADDR_BITS)        
        )rbi(
        .clk(clk_user), 
        .reset(reset), 
        .ack_user2b_in(ack_user2b_in), 
        .doutb_0(doutb_0),
        .doutb_1(doutb_1),
        .addrb_0(addrb_0), 
        .addrb_1(addrb_1), 
        .dout_leaf_interface2user(dout2user), 
        .vld_bram_in2user(vld2user), 
        .freespace_update(freespace_update), 
        .web_0(web_0),
        .web_1(web_1));

    
endmodule
module Input_Port#(
    parameter PACKET_BITS = 97,
    parameter NUM_LEAF_BITS = 6,
    parameter NUM_PORT_BITS = 4,
    parameter NUM_ADDR_BITS = 7,
    parameter PAYLOAD_BITS = 64, 
    parameter NUM_IN_PORTS = 1, 
    parameter NUM_OUT_PORTS = 1,
    parameter NUM_BRAM_ADDR_BITS = 7,
    parameter PORT_No = 2,
    parameter SYN_TYPE = "yosys",
    parameter FREESPACE_UPDATE_SIZE = 64,
    localparam BRAM_DEPTH = 2**(NUM_BRAM_ADDR_BITS-1)*(PAYLOAD_BITS+1)
    )(
    input clk_bft,
    input clk_user,
    input reset,
    

    output freespace_update,
    output [PACKET_BITS-1:0] packet_from_input_port,
    input [PACKET_BITS-1:0] din_leaf_bft2interface,
    input [NUM_LEAF_BITS-1:0] src_leaf,
    input [NUM_PORT_BITS-1:0] src_port,
    

    output [PAYLOAD_BITS-1:0] dout2user,
    output vld2user,
    input ack_user2b_in
    
    );


    wire vldBit;
    wire [NUM_PORT_BITS-1:0] port;
    wire [NUM_ADDR_BITS-1:0] addr;
    wire [PAYLOAD_BITS-1:0] payload;
    
    wire [PACKET_BITS-1-NUM_LEAF_BITS-NUM_PORT_BITS-PAYLOAD_BITS-1:0] red_bits;
    wire [PAYLOAD_BITS-1:0] update_data;
    
    wire [NUM_ADDR_BITS-1:0] addra;

    wire [PAYLOAD_BITS:0] dina;
    wire wea;
    wire wea_0;
    wire wea_1;
    
    
    wire [NUM_ADDR_BITS-2:0] addrb_0;

    wire [PAYLOAD_BITS:0] doutb_0;
    wire web_0;
    
        
    wire [NUM_ADDR_BITS-2:0] addrb_1;

    wire [PAYLOAD_BITS:0] doutb_1;
    wire web_1;
    
    
    assign wea_0 = addra[0] ? 0 : wea;
    assign wea_1 = addra[0] ? wea : 0;
    
    

    
    assign red_bits = 0;
    assign update_data = 1;
    assign packet_from_input_port = {1'b1, src_leaf, src_port, red_bits, update_data};
    
    
    assign vldBit = din_leaf_bft2interface[PACKET_BITS-1];
    assign port = din_leaf_bft2interface[PACKET_BITS-2-NUM_LEAF_BITS:PACKET_BITS-2-NUM_LEAF_BITS-NUM_PORT_BITS+1];
    assign addr = din_leaf_bft2interface[PAYLOAD_BITS+NUM_ADDR_BITS-1:PAYLOAD_BITS];
    assign payload = din_leaf_bft2interface[PAYLOAD_BITS-1:0];



    
    

    write_b_in #(
        .NUM_PORT_BITS(NUM_PORT_BITS),
        .PAYLOAD_BITS(PAYLOAD_BITS),
        .NUM_ADDR_BITS(NUM_ADDR_BITS),
        .PORT_No(PORT_No)
        )wbi(
        .clk(clk_bft), 
        .reset(reset), 
        .port(port), 
        .addr(addr), 
        .vldBit(vldBit), 
        .payload(payload), 
        .wea(wea), 
        .addra(addra), 
        .dina(dina)
        );




   
    

wire [PAYLOAD_BITS:0] b_in_dinb;
assign b_in_dinb = 0;

generate
    if(SYN_TYPE == "yosys")
    begin      
        xpm_memory_tdpram_yosys # (

          .MEMORY_SIZE        (BRAM_DEPTH),
          .MEMORY_PRIMITIVE   ("block"),
          .CLOCKING_MODE      ("independent_clock"),
          .MEMORY_INIT_FILE   ("none"),
          .MEMORY_INIT_PARAM  (""    ),
          .USE_MEM_INIT       (1),
          .WAKEUP_TIME        ("disable_sleep"),
          .MESSAGE_CONTROL    (0),
          .ECC_MODE           ("no_ecc"),
          .AUTO_SLEEP_TIME    (0),
        

          .WRITE_DATA_WIDTH_A (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_A  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_A (PAYLOAD_BITS+1),
          .ADDR_WIDTH_A       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_A ("0"),
          .READ_LATENCY_A     (1),
          .WRITE_MODE_A       ("write_first"),
        

          .WRITE_DATA_WIDTH_B (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_B  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_B (PAYLOAD_BITS+1),
          .ADDR_WIDTH_B       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_B ("0"),
          .READ_LATENCY_B     (1),
          .WRITE_MODE_B       ("write_first")
        
        ) xpm_memory_tdpram_inst_0 (

          .sleep          (1'b0),

          .clka           (clk_bft),
          .rsta           (reset),
          .ena            (1'b1),
          .regcea         (1'b1),
          .wea            (wea_0),
          .addra          (addra[NUM_ADDR_BITS-1:1]),
          .dina           (dina),
          .injectsbiterra (1'b0),
          .injectdbiterra (1'b0),
          .douta          (),
          .sbiterra       (),
          .dbiterra       (),

          .clkb           (clk_user),
          .rstb           (reset),
          .enb            (1'b1),
          .regceb         (1'b1),
          .web            (web_0),
          .addrb          (addrb_0),
          .dinb           (0),
          .injectsbiterrb (1'b0),
          .injectdbiterrb (1'b0),
          .doutb          (doutb_0),
          .sbiterrb       (),
          .dbiterrb       ()
        );
        
        
        
        xpm_memory_tdpram_yosys # (

          .MEMORY_SIZE        (BRAM_DEPTH),
          .MEMORY_PRIMITIVE   ("block"),
          .CLOCKING_MODE      ("independent_clock"),
          .MEMORY_INIT_FILE   ("none"),
          .MEMORY_INIT_PARAM  (""    ),
          .USE_MEM_INIT       (1),
          .WAKEUP_TIME        ("disable_sleep"),
          .MESSAGE_CONTROL    (0),
          .ECC_MODE           ("no_ecc"),
          .AUTO_SLEEP_TIME    (0),
        

          .WRITE_DATA_WIDTH_A (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_A  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_A (PAYLOAD_BITS+1),
          .ADDR_WIDTH_A       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_A ("0"),
          .READ_LATENCY_A     (1),
          .WRITE_MODE_A       ("write_first"),
        

          .WRITE_DATA_WIDTH_B (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_B  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_B (PAYLOAD_BITS+1),
          .ADDR_WIDTH_B       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_B ("0"),
          .READ_LATENCY_B     (1),
          .WRITE_MODE_B       ("write_first")
        
        ) xpm_memory_tdpram_inst_1 (

          .sleep          (1'b0),

          .clka           (clk_bft),
          .rsta           (reset),
          .ena            (1'b1),
          .regcea         (1'b1),
          .wea            (wea_1),
          .addra          (addra[NUM_ADDR_BITS-1:1]),
          .dina           (dina),
          .injectsbiterra (1'b0),
          .injectdbiterra (1'b0),
          .douta          (),
          .sbiterra       (),
          .dbiterra       (),

          .clkb           (clk_user),
          .rstb           (reset),
          .enb            (1'b1),
          .regceb         (1'b1),
          .web            (web_1),
          .addrb          (addrb_1),
          .dinb           (0),
          .injectsbiterrb (1'b0),
          .injectdbiterrb (1'b0),
          .doutb          (doutb_1),
          .sbiterrb       (),
          .dbiterrb       ()
        );

    end else begin

        
              
        xpm_memory_tdpram # (

          .MEMORY_SIZE        (BRAM_DEPTH),
          .MEMORY_PRIMITIVE   ("block"),
          .CLOCKING_MODE      ("independent_clock"),
          .MEMORY_INIT_FILE   ("none"),
          .MEMORY_INIT_PARAM  (""    ),
          .USE_MEM_INIT       (1),
          .WAKEUP_TIME        ("disable_sleep"),
          .MESSAGE_CONTROL    (0),
          .ECC_MODE           ("no_ecc"),
          .AUTO_SLEEP_TIME    (0),
        

          .WRITE_DATA_WIDTH_A (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_A  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_A (PAYLOAD_BITS+1),
          .ADDR_WIDTH_A       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_A ("0"),
          .READ_LATENCY_A     (1),
          .WRITE_MODE_A       ("write_first"),
        

          .WRITE_DATA_WIDTH_B (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_B  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_B (PAYLOAD_BITS+1),
          .ADDR_WIDTH_B       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_B ("0"),
          .READ_LATENCY_B     (1),
          .WRITE_MODE_B       ("write_first")
        
        ) xpm_memory_tdpram_inst_0 (

          .sleep          (1'b0),

          .clka           (clk_bft),
          .rsta           (reset),
          .ena            (1'b1),
          .regcea         (1'b1),
          .wea            (wea_0),
          .addra          (addra[NUM_ADDR_BITS-1:1]),
          .dina           (dina),
          .injectsbiterra (1'b0),
          .injectdbiterra (1'b0),
          .douta          (),
          .sbiterra       (),
          .dbiterra       (),

          .clkb           (clk_user),
          .rstb           (reset),
          .enb            (1'b1),
          .regceb         (1'b1),
          .web            (web_0),
          .addrb          (addrb_0),
          .dinb           (0),
          .injectsbiterrb (1'b0),
          .injectdbiterrb (1'b0),
          .doutb          (doutb_0),
          .sbiterrb       (),
          .dbiterrb       ()
        );
        
        
        
        xpm_memory_tdpram # (

          .MEMORY_SIZE        (BRAM_DEPTH),
          .MEMORY_PRIMITIVE   ("block"),
          .CLOCKING_MODE      ("independent_clock"),
          .MEMORY_INIT_FILE   ("none"),
          .MEMORY_INIT_PARAM  (""    ),
          .USE_MEM_INIT       (1),
          .WAKEUP_TIME        ("disable_sleep"),
          .MESSAGE_CONTROL    (0),
          .ECC_MODE           ("no_ecc"),
          .AUTO_SLEEP_TIME    (0),
        

          .WRITE_DATA_WIDTH_A (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_A  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_A (PAYLOAD_BITS+1),
          .ADDR_WIDTH_A       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_A ("0"),
          .READ_LATENCY_A     (1),
          .WRITE_MODE_A       ("write_first"),
        

          .WRITE_DATA_WIDTH_B (PAYLOAD_BITS+1),
          .READ_DATA_WIDTH_B  (PAYLOAD_BITS+1),
          .BYTE_WRITE_WIDTH_B (PAYLOAD_BITS+1),
          .ADDR_WIDTH_B       (NUM_BRAM_ADDR_BITS-1),
          .READ_RESET_VALUE_B ("0"),
          .READ_LATENCY_B     (1),
          .WRITE_MODE_B       ("write_first")
        
        ) xpm_memory_tdpram_inst_1 (

          .sleep          (1'b0),

          .clka           (clk_bft),
          .rsta           (reset),
          .ena            (1'b1),
          .regcea         (1'b1),
          .wea            (wea_1),
          .addra          (addra[NUM_ADDR_BITS-1:1]),
          .dina           (dina),
          .injectsbiterra (1'b0),
          .injectdbiterra (1'b0),
          .douta          (),
          .sbiterra       (),
          .dbiterra       (),

          .clkb           (clk_user),
          .rstb           (reset),
          .enb            (1'b1),
          .regceb         (1'b1),
          .web            (web_1),
          .addrb          (addrb_1),
          .dinb           (0),
          .injectsbiterrb (1'b0),
          .injectdbiterrb (1'b0),
          .doutb          (doutb_1),
          .sbiterrb       (),
          .dbiterrb       ()
        );
        
    end
endgenerate

  


    read_b_in #(
        .FREESPACE_UPDATE_SIZE(FREESPACE_UPDATE_SIZE),
        .PAYLOAD_BITS(PAYLOAD_BITS),
        .NUM_ADDR_BITS(NUM_ADDR_BITS)        
        )rbi(
        .clk(clk_user), 
        .reset(reset), 
        .ack_user2b_in(ack_user2b_in), 
        .doutb_0(doutb_0),
        .doutb_1(doutb_1),
        .addrb_0(addrb_0), 
        .addrb_1(addrb_1), 
        .dout_leaf_interface2user(dout2user), 
        .vld_bram_in2user(vld2user), 
        .freespace_update(freespace_update), 
        .web_0(web_0),
        .web_1(web_1));

    
endmodule