data/full_repos/permissive/192041249/zynet/db/Weight_Memory.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/192041249/zynet/db/Weight_Memory.v:21: Cannot find include file: include.v\n`include "include.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/192041249/zynet/db,data/full_repos/permissive/192041249/include.v\n             data/full_repos/permissive/192041249/zynet/db,data/full_repos/permissive/192041249/include.v.v\n             data/full_repos/permissive/192041249/zynet/db,data/full_repos/permissive/192041249/include.v.sv\n             include.v\n             include.v.v\n             include.v.sv\n             obj_dir/include.v\n             obj_dir/include.v.v\n             obj_dir/include.v.sv\n%Error: Exiting due to 1 error(s)\n'
module Weight_Memory #(parameter numWeight = 3, neuronNo=5,layerNo=1,addressWidth=10,dataWidth=16,weightFile="w_1_15.mif") 
    ( 
    input clk,
    input wen,
    input ren,
    input [addressWidth-1:0] wadd,
    input [addressWidth-1:0] radd,
    input [dataWidth-1:0] win,
    output reg [dataWidth-1:0] wout);
    
    reg [dataWidth-1:0] mem [numWeight-1:0];

    `ifdef pretrained
        initial
		begin
	        $readmemb(weightFile, mem);
	    end
	`else
		always @(posedge clk)
		begin
			if (wen)
			begin
				mem[wadd] <= win;
			end
		end 
    `endif
    
    always @(posedge clk)
    begin
        if (ren)
        begin
            wout <= mem[radd];
        end
    end 
endmodule
module Weight_Memory #(parameter numWeight = 3, neuronNo=5,layerNo=1,addressWidth=10,dataWidth=16,weightFile="w_1_15.mif") 
    ( 
    input clk,
    input wen,
    input ren,
    input [addressWidth-1:0] wadd,
    input [addressWidth-1:0] radd,
    input [dataWidth-1:0] win,
    output reg [dataWidth-1:0] wout);

    
    reg [dataWidth-1:0] mem [numWeight-1:0];

    `ifdef pretrained
        initial
		begin
	        $readmemb(weightFile, mem);
	    end
	`else
		always @(posedge clk)
		begin
			if (wen)
			begin
				mem[wadd] <= win;
			end
		end 
    `endif
    
    always @(posedge clk)
    begin
        if (ren)
        begin
            wout <= mem[radd];
        end
    end 
endmodule