data/full_repos/permissive/134057391/2018_cpu/code/rtl/prog1.v
data/verilator_xmls/52fc5709-4146-44b6-bdeb-9a4827f7ebb2.xml
module prog1(
    input      [3:0]  a,
    output reg [15:0] dout
    );

    always @*
        case(a)

            4'h0: dout = 16'hea05;
            4'h1: dout = 16'he01f;
            4'h2: dout = 16'h2301;

            default: dout = 16'h0000;
        endcase

endmodule
module prog1(
    input      [3:0]  a,
    output reg [15:0] dout
    );


    always @*
        case(a)

            4'h0: dout = 16'hea05;
            4'h1: dout = 16'he01f;
            4'h2: dout = 16'h2301;

            default: dout = 16'h0000;
        endcase

endmodule