data/full_repos/permissive/179439333/src/sound-module/MidiByteReader.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/179439333/src/sound-module/MidiByteReader.v:37: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance MidiByteReader\n        midiCount <= 1\'b0;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/179439333/src/sound-module/MidiByteReader.v:38: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance MidiByteReader\n        bitNumber <= 1\'b0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/179439333/src/sound-module/MidiByteReader.v:39: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance MidiByteReader\n        byteValue <= 1\'b0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/179439333/src/sound-module/MidiByteReader.v:33: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance MidiByteReader\n      if (debounceCountDown == 1\'b0)\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/179439333/src/sound-module/MidiByteReader.v:51: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance MidiByteReader\n      midiCount <= 1\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/179439333/src/sound-module/MidiByteReader.v:56: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                         : ... In instance MidiByteReader\n       byteValue <= byteValue | (1\'b1 << bitNumber);\n                                      ^~\n%Error: Exiting due to 6 warning(s)\n'
module MidiByteReader(
	input CLOCK_50,
	input MIDI_RX,
	output reg isByteAvailable = 0,
	output reg [7:0] byteValue = 0
);

localparam
	midiTicks = 12'd1600,
	debounceTicks = 8'd10;

localparam
	stateWaitingForSignal = 8'd0,
	stateSignalAvailable = 8'd1,
	stateByteComplete = 8'd2;

reg [7:0] midiState = stateWaitingForSignal;
reg [7:0] bitNumber = 0;
reg [11:0] midiCount = 0;
reg [7:0] debounceCountDown = debounceTicks;

always @(posedge CLOCK_50)
begin
	case (midiState)
		stateWaitingForSignal:
			begin
				isByteAvailable <= 1'b0;
			
				if (MIDI_RX == 1'b0)
					begin
						debounceCountDown <= debounceCountDown - 1'b1;
						
						if (debounceCountDown == 1'b0)
							begin
								debounceCountDown <= debounceTicks;
								midiState <= stateSignalAvailable;
								midiCount <= 1'b0;
								bitNumber <= 1'b0;
								byteValue <= 1'b0;
							end
					end
				else
					debounceCountDown <= debounceTicks;
			end
		stateSignalAvailable:
			begin
				midiCount <= midiCount + 1'b1;
			
				if (midiCount == midiTicks)
					begin
						midiCount <= 1'b0;
					
						bitNumber <= bitNumber + 1'b1;	

						if (MIDI_RX == 1'b1)
							byteValue <= byteValue | (1'b1 << bitNumber);
		
						if (bitNumber == 8'd7)
							midiState <= stateByteComplete;					
					end
			end
		stateByteComplete:
			begin
				midiCount <= midiCount + 1'b1;
			
				if (midiCount == midiTicks)
					begin
						isByteAvailable <= 1'b1;				
						midiState <= stateWaitingForSignal;
					end			
			end
	endcase
end

endmodule
module MidiByteReader(
	input CLOCK_50,
	input MIDI_RX,
	output reg isByteAvailable = 0,
	output reg [7:0] byteValue = 0
);


localparam
	midiTicks = 12'd1600,
	debounceTicks = 8'd10;

localparam
	stateWaitingForSignal = 8'd0,
	stateSignalAvailable = 8'd1,
	stateByteComplete = 8'd2;

reg [7:0] midiState = stateWaitingForSignal;
reg [7:0] bitNumber = 0;
reg [11:0] midiCount = 0;
reg [7:0] debounceCountDown = debounceTicks;

always @(posedge CLOCK_50)
begin
	case (midiState)
		stateWaitingForSignal:
			begin
				isByteAvailable <= 1'b0;
			
				if (MIDI_RX == 1'b0)
					begin
						debounceCountDown <= debounceCountDown - 1'b1;
						
						if (debounceCountDown == 1'b0)
							begin
								debounceCountDown <= debounceTicks;
								midiState <= stateSignalAvailable;
								midiCount <= 1'b0;
								bitNumber <= 1'b0;
								byteValue <= 1'b0;
							end
					end
				else
					debounceCountDown <= debounceTicks;
			end
		stateSignalAvailable:
			begin
				midiCount <= midiCount + 1'b1;
			
				if (midiCount == midiTicks)
					begin
						midiCount <= 1'b0;
					
						bitNumber <= bitNumber + 1'b1;	

						if (MIDI_RX == 1'b1)
							byteValue <= byteValue | (1'b1 << bitNumber);
		
						if (bitNumber == 8'd7)
							midiState <= stateByteComplete;					
					end
			end
		stateByteComplete:
			begin
				midiCount <= midiCount + 1'b1;
			
				if (midiCount == midiTicks)
					begin
						isByteAvailable <= 1'b1;				
						midiState <= stateWaitingForSignal;
					end			
			end
	endcase
end

endmodule