data/full_repos/permissive/100597706/testing/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n   always # 5 clk = ~ clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[4] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[4] = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[14] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[14] = 1\'b0;\n    ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module io_wrapper #(parameter targ_addr = 32'h80000000) (
	input clk, rst,
	input [31:0] baddr,
	input [31:0] bdi,
	input [31:0] bdi_m,
	input [1:0] bsz,
	input bwr,
	output [31:0] bdo,
	input brdy_m,
	output brdy,
	output CS
);

	reg [31:0] ioreg;

	assign CS = (targ_addr == baddr);
	wire mwr = CS & bwr;

	always @ (posedge clk) begin
		if (rst)
			ioreg <= 32'b0;

		else if (mwr)
			ioreg <= bdi;
		else if (brdy_m)
			ioreg <= bdi_m;
	end


    assign bdo = CS? (brdy_m ? bdi_m : ioreg) : 32'hZZZZZZZZ;
	assign brdy = CS? 1'b1 : 1'bz;

endmodule
module io_wrapper #(parameter targ_addr = 32'h80000000) (
	input clk, rst,
	input [31:0] baddr,
	input [31:0] bdi,
	input [31:0] bdi_m,
	input [1:0] bsz,
	input bwr,
	output [31:0] bdo,
	input brdy_m,
	output brdy,
	output CS
);


	reg [31:0] ioreg;

	assign CS = (targ_addr == baddr);
	wire mwr = CS & bwr;

	always @ (posedge clk) begin
		if (rst)
			ioreg <= 32'b0;

		else if (mwr)
			ioreg <= bdi;
		else if (brdy_m)
			ioreg <= bdi_m;
	end


    assign bdo = CS? (brdy_m ? bdi_m : ioreg) : 32'hZZZZZZZZ;
	assign brdy = CS? 1'b1 : 1'bz;

endmodule