data/full_repos/permissive/177038316/project.v
1: b'%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:457: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'HUNDREDS\' generates 2 bits.\n                                                                  : ... In instance top.m3\n    case(HUNDREDS)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:344: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'data_y\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y - data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:344: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'data_x\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y - data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:349: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'data_y\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y + data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:349: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'data_x\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y + data_x;\n                  ^\n%Error: Exiting due to 5 warning(s)\n'
module top(A,PS2_Data, PS2_Clock, clk, seg1, seg2, seg3, overflow, sinal);
input [7:0] A;
input PS2_Data;
input PS2_Clock;
input clk;
output [6:0] seg1, seg2, seg3;
output sinal, overflow;
wire tula, new_instruction, ready, overflow_in;
wire [7:0] Z, Y, X, data_ula;
wire [1:0] tx, ty, tz;
wire [2:0] instruction;

keyboard m0 (PS2_Clock, PS2_Data, instruction, new_instruction, ready);
controle m1 (new_instruction, instruction, clk, ready, tx, ty, tz, tula);
special_register x  (A, tx, clk, X);
register y  (data_ula, ty, clk, Y);
ula m2(X, Y, tula, data_ula, overflow_in, new_instruction);
register_overflow z (Y, tz, clk, Z, overflow_in, overflow);
binary_to_BCD m3 (Z, seg1, seg2, seg3, sinal);

endmodule
module top(A,PS2_Data, PS2_Clock, clk, seg1, seg2, seg3, overflow, sinal);

input [7:0] A;
input PS2_Data;
input PS2_Clock;
input clk;
output [6:0] seg1, seg2, seg3;
output sinal, overflow;
wire tula, new_instruction, ready, overflow_in;
wire [7:0] Z, Y, X, data_ula;
wire [1:0] tx, ty, tz;
wire [2:0] instruction;

keyboard m0 (PS2_Clock, PS2_Data, instruction, new_instruction, ready);
controle m1 (new_instruction, instruction, clk, ready, tx, ty, tz, tula);
special_register x  (A, tx, clk, X);
register y  (data_ula, ty, clk, Y);
ula m2(X, Y, tula, data_ula, overflow_in, new_instruction);
register_overflow z (Y, tz, clk, Z, overflow_in, overflow);
binary_to_BCD m3 (Z, seg1, seg2, seg3, sinal);

endmodule