data/full_repos/permissive/105869704/top_test_fibonacci.v
1: b'%Error: data/full_repos/permissive/105869704/top_test_fibonacci.v:19: Cannot find include file: top.v\n`include "top.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105869704,data/full_repos/permissive/105869704/top.v\n             data/full_repos/permissive/105869704,data/full_repos/permissive/105869704/top.v.v\n             data/full_repos/permissive/105869704,data/full_repos/permissive/105869704/top.v.sv\n             top.v\n             top.v.v\n             top.v.sv\n             obj_dir/top.v\n             obj_dir/top.v.v\n             obj_dir/top.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/105869704/top_test_fibonacci.v:50: Unsupported: Ignoring delay on this delayed statement.\n  always #2 clk = !clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105869704/top_test_fibonacci.v:51: Unsupported: Ignoring delay on this delayed statement.\n  always #4 uart_clk = !uart_clk;\n         ^\n%Error: data/full_repos/permissive/105869704/top_test_fibonacci.v:58: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("top_test_fibonacci.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/105869704/top_test_fibonacci.v:59: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module top_test_fibonacci;

  localparam WIDTH = 8;
  localparam UART_WIDTH = $clog2(WIDTH);
  localparam OUTPUT_CNT = 12;

  reg clk = 1;
  reg uart_clk = 0;
  reg receiving = 0;
  reg display = 0;
  reg [UART_WIDTH-1 : 0] serial_cnt = 0;
  reg [WIDTH-1 : 0] serial_data;
  reg [WIDTH-1 : 0] expected_output [OUTPUT_CNT-1 : 0];
  wire uart_tx;

  reg [WIDTH-1 : 0] i, j, k, l;
  initial begin
    j = 1;
    k = 1;
    l = 0;
    for (i = 0; i < OUTPUT_CNT; i = i + 1) begin
      expected_output[i] = k;
      l = k;
      k = k + j;
      j = l;
    end
    i = 0;
  end

  always #2 clk = !clk;
  always #4 uart_clk = !uart_clk;

  top t(
    .clk(clk),
    .uart_tx_line(uart_tx));

  initial begin
    $dumpfile("top_test_fibonacci.vcd");
    $dumpvars;
  end

  always @ (posedge uart_clk) begin
    if (receiving) begin

      if (serial_cnt == WIDTH - 1 ) begin
        receiving <= 0;
        display <= 1;
      end

      serial_data[serial_cnt] <= uart_tx;
      serial_cnt <= serial_cnt + 1;

    end else if (display) begin

      if (i >= OUTPUT_CNT) begin
        $display("Fibonacci test passed, computed results match the expected output!\n");
        $finish;
      end

      if (serial_data != expected_output[i]) begin
        $display("Fibonacci test failed!\n");
        $display("Serial output:%d doesn't match expected_output[%d]:%d\n",
          serial_data, i, expected_output[i]);
        $finish;
      end

      i <= i + 1;
      display <= 0;

    end else begin

      if (uart_tx == 0) begin
        receiving <= 1;
      end

    end
  end

endmodule
module top_test_fibonacci;


  localparam WIDTH = 8;
  localparam UART_WIDTH = $clog2(WIDTH);
  localparam OUTPUT_CNT = 12;

  reg clk = 1;
  reg uart_clk = 0;
  reg receiving = 0;
  reg display = 0;
  reg [UART_WIDTH-1 : 0] serial_cnt = 0;
  reg [WIDTH-1 : 0] serial_data;
  reg [WIDTH-1 : 0] expected_output [OUTPUT_CNT-1 : 0];
  wire uart_tx;

  reg [WIDTH-1 : 0] i, j, k, l;
  initial begin
    j = 1;
    k = 1;
    l = 0;
    for (i = 0; i < OUTPUT_CNT; i = i + 1) begin
      expected_output[i] = k;
      l = k;
      k = k + j;
      j = l;
    end
    i = 0;
  end

  always #2 clk = !clk;
  always #4 uart_clk = !uart_clk;

  top t(
    .clk(clk),
    .uart_tx_line(uart_tx));

  initial begin
    $dumpfile("top_test_fibonacci.vcd");
    $dumpvars;
  end

  always @ (posedge uart_clk) begin
    if (receiving) begin

      if (serial_cnt == WIDTH - 1 ) begin
        receiving <= 0;
        display <= 1;
      end

      serial_data[serial_cnt] <= uart_tx;
      serial_cnt <= serial_cnt + 1;

    end else if (display) begin

      if (i >= OUTPUT_CNT) begin
        $display("Fibonacci test passed, computed results match the expected output!\n");
        $finish;
      end

      if (serial_data != expected_output[i]) begin
        $display("Fibonacci test failed!\n");
        $display("Serial output:%d doesn't match expected_output[%d]:%d\n",
          serial_data, i, expected_output[i]);
        $finish;
      end

      i <= i + 1;
      display <= 0;

    end else begin

      if (uart_tx == 0) begin
        receiving <= 1;
      end

    end
  end

endmodule