data/full_repos/permissive/135701568/mux8bit3to1.v
data/verilator_xmls/4eba6b04-5dc0-4e71-8c5b-6d1fc24d76c2.xml
module mux8bit3to1 (in1, in2, in3, sel, out);
  input [7:0] in1, in2, in3;
  input[1:0] sel;
  output reg [7:0] out;
  always @ (in1, in2, in3, sel) begin
    case(sel)
    0:begin out = in1; end
    1:begin out = in2; end
    2:begin out = in3; end
    endcase
  end
endmodule
module mux8bit3to1 (in1, in2, in3, sel, out);

  input [7:0] in1, in2, in3;
  input[1:0] sel;
  output reg [7:0] out;
  always @ (in1, in2, in3, sel) begin
    case(sel)
    0:begin out = in1; end
    1:begin out = in2; end
    2:begin out = in3; end
    endcase
  end
endmodule