data/full_repos/permissive/143278/ivltests/resolv1.v
 line:16: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/resolv1.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/resolv1.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/resolv1.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #30\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/resolv1.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #40\n    ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

wire w;
wire q;
reg g;

pullup(w);
bufif1(w, 1'b1, g);
pmos(q, w, 1'b0);
bufif0(q, 1'b0, g);

initial
  begin
    g = 1;
    #10
    $display(q, w);
    #20
    g = 0;
    #30
    $display(q, w);
    if (q == 1'b0)
      $display("PASSED");
    else
      $display("FAILED");
    #40
    $finish;
  end

endmodule
module test;


wire w;
wire q;
reg g;

pullup(w);
bufif1(w, 1'b1, g);
pmos(q, w, 1'b0);
bufif0(q, 1'b0, g);

initial
  begin
    g = 1;
    #10
    $display(q, w);
    #20
    g = 0;
    #30
    $display(q, w);
    if (q == 1'b0)
      $display("PASSED");
    else
      $display("FAILED");
    #40
    $finish;
  end

endmodule