data/full_repos/permissive/185386477/verilog/ww.v
None: at end of input
1: b'%Warning-PINMISSING: data/full_repos/permissive/185386477/verilog/ww.v:638: Cell has missing pin: \'zero_to_right\'\n ww_br_slice br_15(.clk(clk), .brn(br[15]),\n             ^~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/185386477/verilog/ww.v:638: Cell has missing pin: \'one_to_right\'\n ww_br_slice br_15(.clk(clk), .brn(br[15]),\n             ^~~~~\n%Warning-MULTITOP: data/full_repos/permissive/185386477/verilog/ww.v:22: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                       : ... Top module \'edgedet\'\nmodule edgedet(clk, reset, in, p);\n       ^~~~~~~\n                                                                       : ... Top module \'ww\'\nmodule ww(\n       ^~\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:66: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ff0 = \'o3740;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:67: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ff1 = \'o3741;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:68: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ff2 = \'o3742;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:69: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ff3 = \'o3743;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:70: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ff4 = \'o3744;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:71: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts0 = \'o3745;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:72: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts1 = \'o3746;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:73: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts2 = \'o3747;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:74: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts3 = \'o3750;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:75: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts4 = \'o3751;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:76: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts5 = \'o3752;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:77: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts6 = \'o3753;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:78: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts7 = \'o3754;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:79: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts8 = \'o3755;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:80: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts9 = \'o3756;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:81: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts10 = \'o3757;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:82: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts11 = \'o3760;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:83: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts12 = \'o3761;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:84: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts13 = \'o3762;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:85: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts14 = \'o3763;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:86: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts15 = \'o3764;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:87: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts16 = \'o3765;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:88: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts17 = \'o3766;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:89: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts18 = \'o3767;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:90: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts19 = \'o3770;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:91: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts20 = \'o3771;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:92: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts21 = \'o3772;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:93: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts22 = \'o3773;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:94: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts23 = \'o3774;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:95: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts24 = \'o3775;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:96: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts25 = \'o3776;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:97: Little bit endian vector: MSB < LSB of bit range: 5:15\n parameter [5:15] addr_ts26 = \'o3777;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:939: Little bit endian vector: MSB < LSB of bit range: 0:15\n input wire [0:15] sw_input,\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:944: Little bit endian vector: MSB < LSB of bit range: 0:15\n input wire [0:15] in,\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:945: Little bit endian vector: MSB < LSB of bit range: 0:15\n output wire [0:15] out\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:947: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] storage_ff;  \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:32: Little bit endian vector: MSB < LSB of bit range: 5:15\n reg [5:15] sw_pc = \'o3740;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:33: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ff_0 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:34: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ff_1 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:35: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ff_2 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:36: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ff_3 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:37: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ff_4 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:38: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_0 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:39: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_1 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:40: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_2 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:41: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_3 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:42: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_4 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:43: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_5 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:44: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_6 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:45: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_7 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:46: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_8 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:47: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_9 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:48: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_10 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:49: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_11 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:50: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_12 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:51: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_13 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:52: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_14 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:53: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_15 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:54: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_16 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:55: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_17 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:56: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_18 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:57: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_19 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:58: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_20 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:59: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_21 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:60: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_22 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:61: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_23 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:62: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_24 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:63: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_25 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:64: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] sw_ts_26 = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:101: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] bus =\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:132: Little bit endian vector: MSB < LSB of bit range: 5:15\n reg [5:15] pc = 0;  \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:159: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] pr;   \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:169: Little bit endian vector: MSB < LSB of bit range: 0:4\n reg [0:4] cs;   \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:365: Little bit endian vector: MSB < LSB of bit range: 5:15\n reg [5:15] ss;   \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:464: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ff = out_ff0 | out_ff1 | out_ff2 | out_ff3 | out_ff4;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:375: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ts =\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:668: Little bit endian vector: MSB < LSB of bit range: 11:15\n reg [11:15] sc;   \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:472: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] ar;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:494: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] ac;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:102: Operator AND expects 16 bits on the LHS, but LHS\'s REPLICATE generates 11 bits.\n                                                                     : ... In instance ww\n  {11{pc_to_bus}}&pc |\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:102: Operator AND expects 16 bits on the RHS, but RHS\'s VARREF \'pc\' generates 11 bits.\n                                                                     : ... In instance ww\n  {11{pc_to_bus}}&pc |\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:105: Operator AND expects 16 bits on the RHS, but RHS\'s VARREF \'ss\' generates 11 bits.\n                                                                     : ... In instance ww\n  {16{ss_to_bus}}&ss |\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:107: Operator AND expects 16 bits on the RHS, but RHS\'s VARREF \'sc\' generates 5 bits.\n                                                                     : ... In instance ww\n  {16{sc_to_bus}}&sc |\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:110: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] check_bus =\n      ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:111: Operator AND expects 16 bits on the LHS, but LHS\'s REPLICATE generates 11 bits.\n                                                                     : ... In instance ww\n  {11{pc_to_check}}&pc |\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:111: Operator AND expects 16 bits on the RHS, but RHS\'s VARREF \'pc\' generates 11 bits.\n                                                                     : ... In instance ww\n  {11{pc_to_check}}&pc |\n                   ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:141: Little bit endian vector: MSB < LSB of bit range: 0:1\n reg [0:1] pc_end_carry_dly = 0;  \n     ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:154: Operator OR expects 16 bits on the LHS, but LHS\'s VARREF \'pc\' generates 11 bits.\n                                                                     : ... In instance ww\n  if(pc_from_bus | pc_read_in_ff) pc <= pc | bus;  \n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:154: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s OR generates 16 bits.\n                                                                     : ... In instance ww\n  if(pc_from_bus | pc_read_in_ff) pc <= pc | bus;  \n                                     ^~\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:264: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg [0:2] pulse_cnt = 0;  \n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:268: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg [0:2] delay_counter = 0;  \n     ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:371: Operator OR expects 16 bits on the LHS, but LHS\'s VARREF \'ss\' generates 11 bits.\n                                                                     : ... In instance ww\n  if(ss_from_bus) ss <= ss | bus;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:371: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s OR generates 16 bits.\n                                                                     : ... In instance ww\n  if(ss_from_bus) ss <= ss | bus;\n                     ^~\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:458: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] in_to_ff = {{5{storage_from_bus&~cs_td}}, {11{storage_from_bus}}}&bus;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:459: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ff0;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:460: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ff1;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:461: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ff2;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:462: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ff3;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:463: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] out_ff4;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:473: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] ar_neg = ~ar;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:480: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] ar_to_ac = {16{add_ar_to_ac}}&ar | {16{sub_ar_to_ac}}&~ar;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:495: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] ac_neg = ~ac;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:496: Little bit endian vector: MSB < LSB of bit range: 1:15\n wire [1:15] cry;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:503: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] ac_to_br16 = {16{ac_to_br}}&ac;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:506: Little bit endian vector: MSB < LSB of bit range: 1:15\n wire [1:15] carry_out;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:508: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] carry_to_left;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:509: Little bit endian vector: MSB < LSB of bit range: 1:15\n wire [1:15] zero_to_left;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:510: Little bit endian vector: MSB < LSB of bit range: 1:15\n wire [1:15] one_to_left;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:513: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] shift_left_n = {16{div_shift_left_pulse}} | {14{shift_left_pulse}};\n      ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:513: Operator OR expects 16 bits on the RHS, but RHS\'s REPLICATE generates 14 bits.\n                                                                     : ... In instance ww\n wire [0:15] shift_left_n = {16{div_shift_left_pulse}} | {14{shift_left_pulse}};\n                                                       ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:600: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] br_zero_to_left;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:601: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] br_one_to_left;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:592: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] br;   \n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:598: Little bit endian vector: MSB < LSB of bit range: 0:14\n wire [0:14] br_zero_to_right;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:599: Little bit endian vector: MSB < LSB of bit range: 0:14\n wire [0:14] br_one_to_right;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:678: Operator OR expects 16 bits on the LHS, but LHS\'s VARREF \'sc\' generates 5 bits.\n                                                                     : ... In instance ww\n  if(sc_from_bus) sc <= sc | bus;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/185386477/verilog/ww.v:678: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s OR generates 16 bits.\n                                                                     : ... In instance ww\n  if(sc_from_bus) sc <= sc | bus;\n                     ^~\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:743: Little bit endian vector: MSB < LSB of bit range: 0:1\n reg [0:1] end_around_carry_dly = 0;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/185386477/verilog/ww.v:774: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] cr = 0;  \n     ^\n%Error: Exiting due to 122 warning(s)\n'
module ww(
	input wire clk,
	input wire reset
);


	reg sw_reset = 0;
	reg sw_restart = 0;
	reg sw_enable_oscillator = 0;
	reg sw_pc_reset = 1;
	reg [5:15] sw_pc = 'o3740;
	reg [0:15] sw_ff_0 = 0;
	reg [0:15] sw_ff_1 = 0;
	reg [0:15] sw_ff_2 = 0;
	reg [0:15] sw_ff_3 = 0;
	reg [0:15] sw_ff_4 = 0;
	reg [0:15] sw_ts_0 = 0;
	reg [0:15] sw_ts_1 = 0;
	reg [0:15] sw_ts_2 = 0;
	reg [0:15] sw_ts_3 = 0;
	reg [0:15] sw_ts_4 = 0;
	reg [0:15] sw_ts_5 = 0;
	reg [0:15] sw_ts_6 = 0;
	reg [0:15] sw_ts_7 = 0;
	reg [0:15] sw_ts_8 = 0;
	reg [0:15] sw_ts_9 = 0;
	reg [0:15] sw_ts_10 = 0;
	reg [0:15] sw_ts_11 = 0;
	reg [0:15] sw_ts_12 = 0;
	reg [0:15] sw_ts_13 = 0;
	reg [0:15] sw_ts_14 = 0;
	reg [0:15] sw_ts_15 = 0;
	reg [0:15] sw_ts_16 = 0;
	reg [0:15] sw_ts_17 = 0;
	reg [0:15] sw_ts_18 = 0;
	reg [0:15] sw_ts_19 = 0;
	reg [0:15] sw_ts_20 = 0;
	reg [0:15] sw_ts_21 = 0;
	reg [0:15] sw_ts_22 = 0;
	reg [0:15] sw_ts_23 = 0;
	reg [0:15] sw_ts_24 = 0;
	reg [0:15] sw_ts_25 = 0;
	reg [0:15] sw_ts_26 = 0;

	parameter [5:15] addr_ff0 = 'o3740;
	parameter [5:15] addr_ff1 = 'o3741;
	parameter [5:15] addr_ff2 = 'o3742;
	parameter [5:15] addr_ff3 = 'o3743;
	parameter [5:15] addr_ff4 = 'o3744;
	parameter [5:15] addr_ts0 = 'o3745;
	parameter [5:15] addr_ts1 = 'o3746;
	parameter [5:15] addr_ts2 = 'o3747;
	parameter [5:15] addr_ts3 = 'o3750;
	parameter [5:15] addr_ts4 = 'o3751;
	parameter [5:15] addr_ts5 = 'o3752;
	parameter [5:15] addr_ts6 = 'o3753;
	parameter [5:15] addr_ts7 = 'o3754;
	parameter [5:15] addr_ts8 = 'o3755;
	parameter [5:15] addr_ts9 = 'o3756;
	parameter [5:15] addr_ts10 = 'o3757;
	parameter [5:15] addr_ts11 = 'o3760;
	parameter [5:15] addr_ts12 = 'o3761;
	parameter [5:15] addr_ts13 = 'o3762;
	parameter [5:15] addr_ts14 = 'o3763;
	parameter [5:15] addr_ts15 = 'o3764;
	parameter [5:15] addr_ts16 = 'o3765;
	parameter [5:15] addr_ts17 = 'o3766;
	parameter [5:15] addr_ts18 = 'o3767;
	parameter [5:15] addr_ts19 = 'o3770;
	parameter [5:15] addr_ts20 = 'o3771;
	parameter [5:15] addr_ts21 = 'o3772;
	parameter [5:15] addr_ts22 = 'o3773;
	parameter [5:15] addr_ts23 = 'o3774;
	parameter [5:15] addr_ts24 = 'o3775;
	parameter [5:15] addr_ts25 = 'o3776;
	parameter [5:15] addr_ts26 = 'o3777;

	wire restart = sw_restart;

	wire [0:15] bus =
		{11{pc_to_bus}}&pc |
		{16{pr_to_bus}}&pr |
		{16{cs_to_bus}}&{cs,11'b0} |
		{16{ss_to_bus}}&ss |
		{16{storage_to_bus}}&(out_ff|out_ts) |
		{16{sc_to_bus}}&sc |
		{16{ar_to_bus}}&ar |
		{16{ac_to_bus}}&ac;
	wire [0:15] check_bus =
		{11{pc_to_check}}&pc |
		{16{storage_to_check}}&(out_ff|out_ts) |
		{16{ac_to_check}}&ac;




	wire reset_pulse = sw_reset | pc_reset;


	reg [2:0] oscillator = 0;
	always @(posedge clk)
		if(sw_enable_oscillator)
			oscillator <= oscillator + 1;

	wire hfcp = ~reset & oscillator[0];
	wire lfcp = ~reset & oscillator == 1;


	reg [5:15] pc = 0;
	wire pc_from_bus;
	wire pc_to_bus;
	reg pc_read_in_ff = 0;
	wire pc_to_check;
	wire pc_add;
	wire pc_clear;
	wire pc_end_carry = pc_add & (&pc);
	reg pc_add_dly = 0;
	reg [0:1] pc_end_carry_dly = 0;
	reg pc_read_in_dly = 0;
	wire pc_reset = pc_end_carry_dly[0] & sw_pc_reset;
	always @(posedge clk) begin
		pc_add_dly <= pc_add;
		pc_read_in_dly <= pc_from_bus;
		pc_end_carry_dly <= {pc_end_carry_dly[1], pc_end_carry};

		if(pc_from_bus) pc_read_in_ff <= 1;
		if(pc_read_in_dly) pc_read_in_ff <= 0;

		if(pc_clear | change_control) pc <= 0;
		if(pc_add_dly) pc <= pc + 1;
		if(pc_from_bus | pc_read_in_ff) pc <= pc | bus;
		if(reset_pulse) pc <= pc | sw_pc;
	end


	reg [0:15] pr;
	wire pr_from_bus;
	wire pr_to_bus;
	wire pr_clear;
	always @(posedge clk) begin
		if(pr_clear) pr <= 0;
		if(pr_from_bus) pr <= pr | bus;
	end


	reg [0:4] cs;
	wire cs_from_bus;
	wire cs_to_bus;
	wire cs_clear;
	wire change_to_sp = change_control;
	always @(posedge clk) begin
		if(cs_clear) cs <= 0;
		if(cs_from_bus) cs <= cs | bus[0:4];
		if(change_to_sp) cs[4] <= 1;
	end
	wire cs_0 = cs == 'o0;
	wire cs_1 = cs == 'o1;
	wire cs_2 = cs == 'o2;
	wire cs_3 = cs == 'o3;
	wire cs_4 = cs == 'o4;
	wire cs_5 = cs == 'o5;
	wire cs_6 = cs == 'o6;
	wire cs_7 = cs == 'o7;
	wire cs_ts = cs == 'o10;
	wire cs_td = cs == 'o11;
	wire cs_12 = cs == 'o12;
	wire cs_13 = cs == 'o13;
	wire cs_14 = cs == 'o14;
	wire cs_15 = cs == 'o15;
	wire cs_cp = cs == 'o16;
	wire cs_sp = cs == 'o17;
	wire cs_ca = cs == 'o20;
	wire cs_cs = cs == 'o21;
	wire cs_ad = cs == 'o22;
	wire cs_su = cs == 'o23;
	wire cs_24 = cs == 'o24;
	wire cs_sa = cs == 'o25;
	wire cs_26 = cs == 'o26;
	wire cs_27 = cs == 'o27;
	wire cs_mr = cs == 'o30;
	wire cs_mh = cs == 'o31;
	wire cs_dv = cs == 'o32;
	wire cs_sl = cs == 'o33;
	wire cs_sr = cs == 'o34;
	wire cs_35 = cs == 'o35;
	wire cs_36 = cs == 'o36;
	wire cs_37 = cs == 'o37;
	wire cs_sd = 0;


	wire stop_clock_tp1 = cs_mr | cs_mh | cs_sr | cs_sl;
	wire cr_from_bus_tp8 = cs_ad | cs_ca | cs_su | cs_cs |
		cs_mr | cs_mh | cs_ts | cs_sd | cs_sr | cs_sl |
		cs_td | cs_sa | cs_dv;
	wire bus_to_output_tp7 = cs_sd;
	wire pr_to_bus_tp7 = cs_sr | cs_sl | cs_sp;
	wire pc_clear_tp6 = cs_sp;
	wire pc_from_bus_tp7 = cs_sp;
	wire pc_to_bus_tp8 = 0;
	wire storage_from_bus_tp7 = cs_ts | cs_sd | cs_td;
	wire storage_to_bus_tp8 = cs_ts | cs_sd | cs_td;
	wire storage_to_bus_tp7 = cs_ad | cs_ca | cs_su | cs_cs |
		cs_mr | cs_mh | cs_sa | cs_dv;
	wire storage_to_check_tp7 = cs_ad | cs_ca | cs_su | cs_cs |
		cs_mr | cs_mh | cs_sa | cs_dv;
	wire storage_clear_tp6 = cs_ts | cs_sd;
	wire stop_clock_tp2 = cs_dv;
	wire special_carry_tp7 = cs_ca;

	wire sub_ar_to_ac_tp1 = cs_dv;
	wire ar_from_bus_tp7 = cs_ad | cs_ca | cs_su | cs_cs |
		cs_mr | cs_mh | cs_sa | cs_dv;
	wire ar_to_bus_tp8 = cs_ad | cs_ca | cs_su | cs_cs |
		cs_mr | cs_mh | cs_sa | cs_dv;
	wire sub_ar_to_ac_tp8 = cs_su | cs_cs;
	wire add_ar_to_ac_tp8 = cs_ad | cs_ca | cs_sa;
	wire ac_to_bus_tp7 = cs_ts | cs_sd | cs_td;
	wire ac_to_check_tp7 = cs_ts | cs_sd | cs_td;
	wire ac_to_br_tp7 = cs_mr | cs_mh;
	wire carry_tp2 = cs_ad | cs_ca | cs_su | cs_mr | cs_mh | cs_sa;
	wire roundoff_tp2 = cs_mr | cs_sr | cs_sl;
	wire product_sign_tp4 = cs_mr | cs_mh | cs_sr | cs_sl | cs_dv;
	wire ac_sign_tp6 = cs_mr | cs_mh | cs_sr | cs_sl | cs_dv;
	wire ar_sign_tp8 = cs_mr | cs_mh | cs_dv;
	wire compare_tp6 = cs_cp;
	wire clear_br_tp3 = cs_mr | cs_sr | cs_sl;
	wire multiply_tp1 = cs_mr | cs_mh;
	wire shift_left_tp1 = cs_sl;
	wire shift_right_tp1 = cs_sr;
	wire divide_tp2 = cs_dv;
	wire special_add_tp3 = cs_sa;
	wire arithmetic_check_tp3 = cs_ad | cs_ca | cs_su | cs_cs | cs_sl;
	wire clear_ac_tp6 = cs_ca | cs_cs;
	wire clear_ac_tp3 = cs_dv;
	wire clear_br_tp6 = cs_mr | cs_mh;
	wire clear_ac_tp8 = cs_mr | cs_mh;


	wire time_pulse = lfcp & ~clock_disabled;
	wire time_pulse_dly = lfcp & ~clock_no_dly;
	reg [0:2] pulse_cnt = 0;
	reg clock_disabled = 0;
	reg clock_no_dly = 1;
	reg warning_signal = 0;
	reg [0:2] delay_counter = 0;
	wire tp1 = time_pulse & pulse_cnt == 0;
	wire tp2 = time_pulse & pulse_cnt == 1;
	wire tp3 = time_pulse & pulse_cnt == 2;
	wire tp4 = time_pulse & pulse_cnt == 3;
	wire tp5 = time_pulse & pulse_cnt == 4;
	wire tp6 = time_pulse & pulse_cnt == 5;
	wire tp7 = time_pulse & pulse_cnt == 6;
	wire tp8 = time_pulse & pulse_cnt == 7;
	wire start_delay = tp2 | tp5;
	wire delay_counter_end_carry = (&delay_counter) & time_pulse_dly;
	always @(posedge clk) begin
		if(time_pulse) pulse_cnt <= pulse_cnt + 1;
		if(start_delay) clock_no_dly <= 0;
		if(start_delay | stop_clock | alarm) clock_disabled <= 1;
		if(delay_counter_end_carry | sc_end_carry | restart) begin
			clock_disabled <= 0;
			clock_no_dly <= 1;
		end
		if(time_pulse_dly) delay_counter <= delay_counter + 1;
		if(restart) warning_signal <= 0;
		if(alarm) warning_signal <= 1;
	end





	wire stop_clock = stop_clock_tp1 & tp1 | stop_clock_tp2 & tp1;

	wire bus_to_output = bus_to_output_tp7 & tp7;
	assign pc_clear = pc_clear_tp6 & tp6;
	assign pc_from_bus = pc_from_bus_tp7 & tp7;
	assign storage_from_bus = storage_from_bus_tp7 & tp7;
	assign storage_clear = storage_clear_tp6 & tp6;

	wire storage_clear_low = cs_td & tp6;
	assign ar_from_bus = ar_from_bus_tp7 & tp7;
	assign clear_ac = clear_ac_tp6 & tp6 | clear_ac_tp3 & tp3 | clear_ac_tp8 & tp8;
	wire start_multiply = multiply_tp1 & tp1;
	wire start_shift_left = shift_left_tp1 & tp1;
	wire start_shift_right = shift_right_tp1 & tp1;

	wire start_divide = divide_tp2 & tp1;

	wire special_add = special_add_tp3 & tp3;
	wire special_carry = special_carry_tp7 & tp7;

	wire add_ar_to_ac_ctl = add_ar_to_ac_tp8 & tp8;
	wire sub_ar_to_ac_ctl = sub_ar_to_ac_tp8 & tp8 | sub_ar_to_ac_tp1 & tp1;
	assign ar_to_bus = ar_to_bus_tp8 & tp8;
	assign ac_to_bus = ac_to_bus_tp7 & tp7;
	assign ac_to_check = ac_to_check_tp7 & tp7;
	assign ac_to_br = ac_to_br_tp7 & tp7;
	wire carry_ctl = carry_tp2 & tp2;
	wire roundoff_ctl = roundoff_tp2 & tp2;
	wire product_sign_ctl = product_sign_tp4 & tp4;
	wire ac_sign_ctl = ac_sign_tp6 & tp6;
	wire ar_sign_ctl = ar_sign_tp8 & tp8;
	wire compare_ctl = compare_tp6 & tp6;
	assign clear_br = clear_br_tp3 & tp3 | clear_br_tp6 & tp6;




	assign pc_to_bus = tp2 | pc_to_bus_tp8&tp8;
	assign pc_to_check = tp2;
	assign pr_from_bus = tp4;
	assign pr_to_bus = tp5 | pr_to_bus_tp7 & tp7;
	assign cs_from_bus = tp5;
	assign cs_to_bus = tp6;
	assign ss_from_bus = tp2 | tp5;
	assign ss_to_bus = tp3 | tp6;
	assign storage_to_bus = tp4 | storage_to_bus_tp7 & tp7 | storage_to_bus_tp8 & tp8;
	assign storage_to_check = tp4 | storage_to_check_tp7 & tp7;
	assign sc_from_bus = tp5;
	assign sc_to_bus = tp6;
	assign cr_from_bus = tp3 | tp6 | cr_from_bus_tp8 & tp8;
	assign ss_clear = tp1 | tp4;
	assign cs_clear = tp4;
	assign pc_add = tp3;
	assign clear_ar = tp5;
	assign pr_clear = tp3;
	assign sc_clear = tp4;
	assign transfer_check = tp3 | tp6 | tp8;










	reg [5:15] ss;
	wire ss_from_bus;
	wire ss_to_bus;
	wire ss_clear;
	always @(posedge clk) begin
		if(ss_clear) ss <= 0;
		if(ss_from_bus) ss <= ss | bus;
	end


	wire [0:15] out_ts =
		{16{ss == addr_ts0}}&sw_ts_0 |
		{16{ss == addr_ts1}}&sw_ts_1 |
		{16{ss == addr_ts2}}&sw_ts_2 |
		{16{ss == addr_ts3}}&sw_ts_3 |
		{16{ss == addr_ts4}}&sw_ts_4 |
		{16{ss == addr_ts5}}&sw_ts_5 |
		{16{ss == addr_ts6}}&sw_ts_6 |
		{16{ss == addr_ts7}}&sw_ts_7 |
		{16{ss == addr_ts8}}&sw_ts_8 |
		{16{ss == addr_ts9}}&sw_ts_9 |
		{16{ss == addr_ts10}}&sw_ts_10 |
		{16{ss == addr_ts11}}&sw_ts_11 |
		{16{ss == addr_ts12}}&sw_ts_12 |
		{16{ss == addr_ts13}}&sw_ts_13 |
		{16{ss == addr_ts14}}&sw_ts_14 |
		{16{ss == addr_ts15}}&sw_ts_15 |
		{16{ss == addr_ts16}}&sw_ts_16 |
		{16{ss == addr_ts17}}&sw_ts_17 |
		{16{ss == addr_ts18}}&sw_ts_18 |
		{16{ss == addr_ts19}}&sw_ts_19 |
		{16{ss == addr_ts20}}&sw_ts_20 |
		{16{ss == addr_ts21}}&sw_ts_21 |
		{16{ss == addr_ts22}}&sw_ts_22 |
		{16{ss == addr_ts23}}&sw_ts_23 |
		{16{ss == addr_ts24}}&sw_ts_24 |
		{16{ss == addr_ts25}}&sw_ts_25 |
		{16{ss == addr_ts26}}&sw_ts_26;


	ww_ff_storage ff0(.clk(clk),
		.sw_input(sw_ff_0),
		.initial_value(storage_reset),
		.clear(storage_clear),
		.clear_low(storage_clear_low),
		.select(ss == addr_ff0),
		.in(in_to_ff),
		.out(out_ff0)
	);
	ww_ff_storage ff1(.clk(clk),
		.sw_input(sw_ff_1),
		.initial_value(storage_reset),
		.clear(storage_clear),
		.clear_low(storage_clear_low),
		.select(ss == addr_ff1),
		.in(in_to_ff),
		.out(out_ff1)
	);
	ww_ff_storage ff2(.clk(clk),
		.sw_input(sw_ff_2),
		.initial_value(storage_reset),
		.clear(storage_clear),
		.clear_low(storage_clear_low),
		.select(ss == addr_ff2),
		.in(in_to_ff),
		.out(out_ff2)
	);
	ww_ff_storage ff3(.clk(clk),
		.sw_input(sw_ff_3),
		.initial_value(storage_reset),
		.clear(storage_clear),
		.clear_low(storage_clear_low),
		.select(ss == addr_ff3),
		.in(in_to_ff),
		.out(out_ff3)
	);
	ww_ff_storage ff4(.clk(clk),
		.sw_input(sw_ff_4),
		.initial_value(storage_reset),
		.clear(storage_clear),
		.clear_low(storage_clear_low),
		.select(ss == addr_ff4),
		.in(in_to_ff),
		.out(out_ff4)
	);

	wire storage_from_bus;
	wire storage_to_bus;
	wire storage_to_check;
	wire storage_clear;
	reg storage_reset = 0;


	wire [0:15] in_to_ff = {{5{storage_from_bus&~cs_td}}, {11{storage_from_bus}}}&bus;
	wire [0:15] out_ff0;
	wire [0:15] out_ff1;
	wire [0:15] out_ff2;
	wire [0:15] out_ff3;
	wire [0:15] out_ff4;
	wire [0:15] out_ff = out_ff0 | out_ff1 | out_ff2 | out_ff3 | out_ff4;





	reg [0:15] ar;
	wire [0:15] ar_neg = ~ar;
	wire ar_from_bus;
	wire ar_to_bus;
	wire add_ar_to_ac = add_ar_to_ac_ctl | from_br15_one | div_add_dly;
	wire sub_ar_to_ac = sub_ar_to_ac_ctl | div_sub_dly;
	wire clear_ar;
	wire complement_ar = ar_sign;
	wire [0:15] ar_to_ac = {16{add_ar_to_ac}}&ar | {16{sub_ar_to_ac}}&~ar;

	reg div_add_dly = 0;
	reg div_sub_dly = 0;
	always @(posedge clk) begin
		div_add_dly <= divide_1;
		div_sub_dly <= divide_0;

		if(clear_ar) ar <= 0;
		if(complement_ar) ar <= ~ar;
		if(ar_from_bus) ar <= ar | bus;
	end


	wire [0:15] ac;
	wire [0:15] ac_neg = ~ac;
	wire [1:15] cry;
	wire ac_to_bus;
	wire ac_to_check;
	wire ac_to_br;
	wire carry = carry_ctl | div_carry_pulse;
	wire clear_ac;
	wire complement_ac = product_sign | ac_sign;
	wire [0:15] ac_to_br16 = {16{ac_to_br}}&ac;

	wire left_digit_carry;
	wire [1:15] carry_out;
	wire end_around_carry = carry_to_left[0];
	wire [0:15] carry_to_left;
	wire [1:15] zero_to_left;
	wire [1:15] one_to_left;
	wire divide_0;
	wire divide_1;
	wire [0:15] shift_left_n = {16{div_shift_left_pulse}} | {14{shift_left_pulse}};
	wire ac_zero_to_br0 = shift_carry_pulse & ~ac[15];
	wire ac_one_to_br0 = shift_carry_pulse & ac[15];

	reg to_ac0_dly = 0;

	ww_ac0 ac_0(.clk(clk), .acn(ac[0]),
		.from_ar(ar_to_ac[0] | to_ac0_dly),
		.clear(clear_ac),
		.complement(complement_ac | neg1_special_add),
		.shift_left(shift_left_n[0]),
		.shift_carry(shift_carry_pulse),


		.zero_to_left(divide_0),
		.one_to_left(divide_1),

		.zero_from_right(zero_to_left[1]),
		.one_from_right(one_to_left[1]),
		.zero_from_left(1'b0),
		.one_from_left(1'b0),

		.carry_in(carry_out[1]),
		.carry_out(left_digit_carry),
		.carry_from_right(carry_to_left[1]),
		.carry_to_left(carry_to_left[0])
	);
	genvar i;
	generate
		for(i = 1; i < 15; i = i + 1) begin : acgen
			ww_ac_slice ac_n(.clk(clk), .acn(ac[i]), .cryn(cry[i]),
				.left_digit(ac[(i+15)%16]),
				.from_ar(ar_to_ac[i]),
				.clear(clear_ac),
				.carry_clear(carry),
				.complement(complement_ac | neg1_special_add),
				.shift_left(shift_left_n[i]),
				.shift_carry(shift_carry_pulse),

				.zero_to_left(zero_to_left[i]),
				.one_to_left(one_to_left[i]),

				.zero_from_right(zero_to_left[(i+1)%16]),
				.one_from_right(one_to_left[(i+1)%16]),

				.carry_in(carry_out[(i+1)%16]),
				.carry_out(carry_out[i]),
				.carry_from_right(carry_to_left[(i+1)%16]),
				.carry_to_left(carry_to_left[i])
			);
		end
	endgenerate
	ww_ac_slice ac_15(.clk(clk), .acn(ac[15]), .cryn(cry[15]),
		.left_digit(ac[14]),
		.from_ar(ar_to_ac[15]),
		.clear(clear_ac),
		.carry_clear(carry),
		.complement(complement_ac),
		.shift_left(shift_left_n[15]),
		.shift_carry(shift_carry_pulse),


		.zero_to_left(zero_to_left[15]),
		.one_to_left(one_to_left[15]),

		.zero_from_right(br_zero_to_left[0]),
		.one_from_right(br_one_to_left[0]),

		.carry_in(1'b0),
		.carry_out(carry_out[15]),
		.carry_from_right(end_around_carry_roundoff),
		.carry_to_left(carry_to_left[15])
	);

	always @(posedge clk) begin
		to_ac0_dly <= special_add_ov;
	end


	wire [0:15] br;
	wire roundoff = roundoff_ctl & br[0];
	wire clear_br;
	wire from_br15_zero = multiply_pulse & ~br[15];
	wire from_br15_one = multiply_pulse & br[15];
	reg clear_br15_dly = 0;
	wire [0:14] br_zero_to_right;
	wire [0:14] br_one_to_right;
	wire [0:15] br_zero_to_left;
	wire [0:15] br_one_to_left;
	ww_br_slice br_0(.clk(clk), .brn(br[0]),
		.from_ac(ac_to_br16[0]),
		.clear(clear_br),
		.shift_left(shift_left_pulse),
		.shift_right(shift_carry_pulse),

		.zero_to_left(br_zero_to_left[0]),
		.one_to_left(br_one_to_left[0]),
		.zero_to_right(br_zero_to_right[0]),
		.one_to_right(br_one_to_right[0]),

		.zero_from_right(br_zero_to_left[1]),
		.one_from_right(br_one_to_left[1]),
		.zero_from_left(ac_zero_to_br0),
		.one_from_left(ac_one_to_br0)
	);
	generate
		for(i = 1; i < 15; i = i + 1) begin : brgen
			ww_br_slice br_n(.clk(clk), .brn(br[i]),
				.from_ac(ac_to_br16[i]),
				.clear(clear_br),
				.shift_left(shift_left_pulse | div_shift_left_pulse),
				.shift_right(shift_carry_pulse),

				.zero_to_left(br_zero_to_left[i]),
				.one_to_left(br_one_to_left[i]),
				.zero_to_right(br_zero_to_right[i]),
				.one_to_right(br_one_to_right[i]),

				.zero_from_right(br_zero_to_left[(i+1)%16]),
				.one_from_right(br_one_to_left[(i+1)%16]),
				.zero_from_left(br_zero_to_right[(i+15)%16]),
				.one_from_left(br_one_to_right[(i+15)%16])
			);
		end
	endgenerate
	ww_br_slice br_15(.clk(clk), .brn(br[15]),
		.from_ac(ac_to_br16[15]),
		.clear(clear_br),
		.shift_left(shift_left_pulse | div_shift_left_pulse),
		.shift_right(shift_carry_pulse),

		.zero_to_left(br_zero_to_left[15]),
		.one_to_left(br_one_to_left[15]),



		.zero_from_right(clear_br15_dly | divide_1),
		.one_from_right(divide_0),
		.zero_from_left(br_zero_to_right[14]),
		.one_from_left(br_one_to_right[14])
	);
	always @(posedge clk)
		clear_br15_dly <= from_br15_one;


	reg sign_control = 0;
	wire product_sign = product_sign_ctl & sign_control;
	wire ac_sign = ac_sign_ctl & ac[0];
	wire ar_sign = ar_sign_ctl & ar[0];
	wire change_control = compare_ctl & ~ac[0];
	always @(posedge clk) begin
		if(complement_ac | complement_ar) sign_control <= ~sign_control;
	end


	reg [11:15] sc;
	wire sc_from_bus;
	wire sc_to_bus;
	wire sc_clear;
	wire sc_add = shift_left_pulse | shift_carry_pulse | div_shift_left_pulse;
	wire sc_end_carry = ~(|sc) & sc_add;
	wire sc_reset_multiply = start_multiply;
	wire sc_reset_divide = start_divide;
	always @(posedge clk) begin
		if(sc_clear) sc <= 0;
		if(sc_from_bus) sc <= sc | bus;
		if(sc_add) sc <= sc + 1;

		if(sc_reset_multiply) sc <= 5'o22;
		if(sc_reset_divide) sc <= 5'o20;
	end


	reg multiply = 0;
	wire multiply_pulse = multiply & hfcp;
	always @(posedge clk) begin
		if(start_multiply) multiply <= 1;
		if(sc_end_carry) multiply <= 0;
	end


	reg shift_left = 0;
	reg shift_right = 0;
	wire shift_left_pulse = shift_left & hfcp;
	wire shift_right_pulse = shift_right & hfcp;
	wire shift_carry_pulse = shift_right_pulse | from_br15_zero;
	always @(posedge clk) begin
		if(start_shift_left) shift_left <= 1;
		if(start_shift_right) shift_right <= 1;
		if(sc_end_carry) begin
			shift_left <= 0;
			shift_right <= 0;
		end
	end


	reg divide = 0;
	reg div_time_dist = 0;
	reg divide_error = 0;
	wire divide_pulse = divide & lfcp;
	wire div_carry_pulse = divide_pulse & ~div_time_dist;
	wire div_shift_left_pulse = divide_pulse & div_time_dist;
	reg divide_pulse_dly = 0;
	wire divide_alarm = divide_0 & divide_error;
	always @(posedge clk) begin
		divide_pulse_dly <= divide_pulse;

		if(start_divide) begin
			divide <= 1;
			div_time_dist <= 0;
		end
		if(sc_end_carry) divide <= 0;
		if(divide_pulse_dly)
			div_time_dist <= ~div_time_dist;
		if(ac_sign_ctl) divide_error <= 1;
		if(divide_1) divide_error <= 0;
	end


	reg ac0_carry = 0;
	reg special_add_mem = 0;
	wire add_ac0_carry = ac0_carry & (special_carry | carry);
	wire special_add_ov = special_add & ac0_carry;
	wire neg1_special_add = special_add_mem & special_carry;
	wire end_around_carry_roundoff = end_around_carry | roundoff | add_ac0_carry;
	wire clear_c0_carry = div_shift_left_pulse | restart;

	reg clear_ac0_carry_dly = 0;
	reg clear_special_add_mem_dly = 0;
	reg left_digit_carry_dly = 0;
	reg [0:1] end_around_carry_dly = 0;
	always @(posedge clk) begin
		clear_ac0_carry_dly <= special_add_ov | special_carry;
		clear_special_add_mem_dly <= neg1_special_add;
		left_digit_carry_dly <= left_digit_carry;
		end_around_carry_dly <= {end_around_carry_dly[1], end_around_carry};

		if(clear_c0_carry | clear_ac0_carry_dly) ac0_carry <= 0;
		if(left_digit_carry_dly | end_around_carry_dly[0]) ac0_carry <= ~ac0_carry;
		if(left_digit_carry_dly | clear_special_add_mem_dly) special_add_mem <= 0;
		if(special_add_ov) special_add_mem <= 1;
	end







	wire arithmetic_check = arithmetic_check_tp3 & tp3;
	wire arithmetic_alarm = arithmetic_check & ac0_carry;

	wire alarm = arithmetic_alarm | divide_alarm;


	reg [0:15] cr = 0;
	wire cr_clear = 0;
	wire cr_from_bus;
	wire transfer_check;
	reg check_cr = 0;

	wire cr_alarm = (|cr)&check_cr;
	always @(posedge clk) begin

		check_cr <= transfer_check;

		cr <= cr ^ check_bus;
		if(cr_from_bus) cr <= cr ^ bus;
		if(cr_clear) cr <= 0;
	end
endmodule
module ww(
	input wire clk,
	input wire reset
);



	reg sw_reset = 0;
	reg sw_restart = 0;
	reg sw_enable_oscillator = 0;
	reg sw_pc_reset = 1;
	reg [5:15] sw_pc = 'o3740;
	reg [0:15] sw_ff_0 = 0;
	reg [0:15] sw_ff_1 = 0;
	reg [0:15] sw_ff_2 = 0;
	reg [0:15] sw_ff_3 = 0;
	reg [0:15] sw_ff_4 = 0;
	reg [0:15] sw_ts_0 = 0;
	reg [0:15] sw_ts_1 = 0;
	reg [0:15] sw_ts_2 = 0;
	reg [0:15] sw_ts_3 = 0;
	reg [0:15] sw_ts_4 = 0;
	reg [0:15] sw_ts_5 = 0;
	reg [0:15] sw_ts_6 = 0;
	reg [0:15] sw_ts_7 = 0;
	reg [0:15] sw_ts_8 = 0;
	reg [0:15] sw_ts_9 = 0;
	reg [0:15] sw_ts_10 = 0;
	reg [0:15] sw_ts_11 = 0;
	reg [0:15] sw_ts_12 = 0;
	reg [0:15] sw_ts_13 = 0;
	reg [0:15] sw_ts_14 = 0;
	reg [0:15] sw_ts_15 = 0;
	reg [0:15] sw_ts_16 = 0;
	reg [0:15] sw_ts_17 = 0;
	reg [0:15] sw_ts_18 = 0;
	reg [0:15] sw_ts_19 = 0;
	reg [0:15] sw_ts_20 = 0;
	reg [0:15] sw_ts_21 = 0;
	reg [0:15] sw_ts_22 = 0;
	reg [0:15] sw_ts_23 = 0;
	reg [0:15] sw_ts_24 = 0;
	reg [0:15] sw_ts_25 = 0;
	reg [0:15] sw_ts_26 = 0;

	parameter [5:15] addr_ff0 = 'o3740;
	parameter [5:15] addr_ff1 = 'o3741;
	parameter [5:15] addr_ff2 = 'o3742;
	parameter [5:15] addr_ff3 = 'o3743;
	parameter [5:15] addr_ff4 = 'o3744;
	parameter [5:15] addr_ts0 = 'o3745;
	parameter [5:15] addr_ts1 = 'o3746;
	parameter [5:15] addr_ts2 = 'o3747;
	parameter [5:15] addr_ts3 = 'o3750;
	parameter [5:15] addr_ts4 = 'o3751;
	parameter [5:15] addr_ts5 = 'o3752;
	parameter [5:15] addr_ts6 = 'o3753;
	parameter [5:15] addr_ts7 = 'o3754;
	parameter [5:15] addr_ts8 = 'o3755;
	parameter [5:15] addr_ts9 = 'o3756;
	parameter [5:15] addr_ts10 = 'o3757;
	parameter [5:15] addr_ts11 = 'o3760;
	parameter [5:15] addr_ts12 = 'o3761;
	parameter [5:15] addr_ts13 = 'o3762;
	parameter [5:15] addr_ts14 = 'o3763;
	parameter [5:15] addr_ts15 = 'o3764;
	parameter [5:15] addr_ts16 = 'o3765;
	parameter [5:15] addr_ts17 = 'o3766;
	parameter [5:15] addr_ts18 = 'o3767;
	parameter [5:15] addr_ts19 = 'o3770;
	parameter [5:15] addr_ts20 = 'o3771;
	parameter [5:15] addr_ts21 = 'o3772;
	parameter [5:15] addr_ts22 = 'o3773;
	parameter [5:15] addr_ts23 = 'o3774;
	parameter [5:15] addr_ts24 = 'o3775;
	parameter [5:15] addr_ts25 = 'o3776;
	parameter [5:15] addr_ts26 = 'o3777;

	wire restart = sw_restart;

	wire [0:15] bus =
		{11{pc_to_bus}}&pc |
		{16{pr_to_bus}}&pr |
		{16{cs_to_bus}}&{cs,11'b0} |
		{16{ss_to_bus}}&ss |
		{16{storage_to_bus}}&(out_ff|out_ts) |
		{16{sc_to_bus}}&sc |
		{16{ar_to_bus}}&ar |
		{16{ac_to_bus}}&ac;
	wire [0:15] check_bus =
		{11{pc_to_check}}&pc |
		{16{storage_to_check}}&(out_ff|out_ts) |
		{16{ac_to_check}}&ac;




	wire reset_pulse = sw_reset | pc_reset;


	reg [2:0] oscillator = 0;
	always @(posedge clk)
		if(sw_enable_oscillator)
			oscillator <= oscillator + 1;

	wire hfcp = ~reset & oscillator[0];
	wire lfcp = ~reset & oscillator == 1;


	reg [5:15] pc = 0;
	wire pc_from_bus;
	wire pc_to_bus;
	reg pc_read_in_ff = 0;
	wire pc_to_check;
	wire pc_add;
	wire pc_clear;
	wire pc_end_carry = pc_add & (&pc);
	reg pc_add_dly = 0;
	reg [0:1] pc_end_carry_dly = 0;
	reg pc_read_in_dly = 0;
	wire pc_reset = pc_end_carry_dly[0] & sw_pc_reset;
	always @(posedge clk) begin
		pc_add_dly <= pc_add;
		pc_read_in_dly <= pc_from_bus;
		pc_end_carry_dly <= {pc_end_carry_dly[1], pc_end_carry};

		if(pc_from_bus) pc_read_in_ff <= 1;
		if(pc_read_in_dly) pc_read_in_ff <= 0;

		if(pc_clear | change_control) pc <= 0;
		if(pc_add_dly) pc <= pc + 1;
		if(pc_from_bus | pc_read_in_ff) pc <= pc | bus;
		if(reset_pulse) pc <= pc | sw_pc;
	end


	reg [0:15] pr;
	wire pr_from_bus;
	wire pr_to_bus;
	wire pr_clear;
	always @(posedge clk) begin
		if(pr_clear) pr <= 0;
		if(pr_from_bus) pr <= pr | bus;
	end


	reg [0:4] cs;
	wire cs_from_bus;
	wire cs_to_bus;
	wire cs_clear;
	wire change_to_sp = change_control;
	always @(posedge clk) begin
		if(cs_clear) cs <= 0;
		if(cs_from_bus) cs <= cs | bus[0:4];
		if(change_to_sp) cs[4] <= 1;
	end
	wire cs_0 = cs == 'o0;
	wire cs_1 = cs == 'o1;
	wire cs_2 = cs == 'o2;
	wire cs_3 = cs == 'o3;
	wire cs_4 = cs == 'o4;
	wire cs_5 = cs == 'o5;
	wire cs_6 = cs == 'o6;
	wire cs_7 = cs == 'o7;
	wire cs_ts = cs == 'o10;
	wire cs_td = cs == 'o11;
	wire cs_12 = cs == 'o12;
	wire cs_13 = cs == 'o13;
	wire cs_14 = cs == 'o14;
	wire cs_15 = cs == 'o15;
	wire cs_cp = cs == 'o16;
	wire cs_sp = cs == 'o17;
	wire cs_ca = cs == 'o20;
	wire cs_cs = cs == 'o21;
	wire cs_ad = cs == 'o22;
	wire cs_su = cs == 'o23;
	wire cs_24 = cs == 'o24;
	wire cs_sa = cs == 'o25;
	wire cs_26 = cs == 'o26;
	wire cs_27 = cs == 'o27;
	wire cs_mr = cs == 'o30;
	wire cs_mh = cs == 'o31;
	wire cs_dv = cs == 'o32;
	wire cs_sl = cs == 'o33;
	wire cs_sr = cs == 'o34;
	wire cs_35 = cs == 'o35;
	wire cs_36 = cs == 'o36;
	wire cs_37 = cs == 'o37;
	wire cs_sd = 0;


	wire stop_clock_tp1 = cs_mr | cs_mh | cs_sr | cs_sl;
	wire cr_from_bus_tp8 = cs_ad | cs_ca | cs_su | cs_cs |
		cs_mr | cs_mh | cs_ts | cs_sd | cs_sr | cs_sl |
		cs_td | cs_sa | cs_dv;
	wire bus_to_output_tp7 = cs_sd;
	wire pr_to_bus_tp7 = cs_sr | cs_sl | cs_sp;
	wire pc_clear_tp6 = cs_sp;
	wire pc_from_bus_tp7 = cs_sp;
	wire pc_to_bus_tp8 = 0;
	wire storage_from_bus_tp7 = cs_ts | cs_sd | cs_td;
	wire storage_to_bus_tp8 = cs_ts | cs_sd | cs_td;
	wire storage_to_bus_tp7 = cs_ad | cs_ca | cs_su | cs_cs |
		cs_mr | cs_mh | cs_sa | cs_dv;
	wire storage_to_check_tp7 = cs_ad | cs_ca | cs_su | cs_cs |
		cs_mr | cs_mh | cs_sa | cs_dv;
	wire storage_clear_tp6 = cs_ts | cs_sd;
	wire stop_clock_tp2 = cs_dv;
	wire special_carry_tp7 = cs_ca;

	wire sub_ar_to_ac_tp1 = cs_dv;
	wire ar_from_bus_tp7 = cs_ad | cs_ca | cs_su | cs_cs |
		cs_mr | cs_mh | cs_sa | cs_dv;
	wire ar_to_bus_tp8 = cs_ad | cs_ca | cs_su | cs_cs |
		cs_mr | cs_mh | cs_sa | cs_dv;
	wire sub_ar_to_ac_tp8 = cs_su | cs_cs;
	wire add_ar_to_ac_tp8 = cs_ad | cs_ca | cs_sa;
	wire ac_to_bus_tp7 = cs_ts | cs_sd | cs_td;
	wire ac_to_check_tp7 = cs_ts | cs_sd | cs_td;
	wire ac_to_br_tp7 = cs_mr | cs_mh;
	wire carry_tp2 = cs_ad | cs_ca | cs_su | cs_mr | cs_mh | cs_sa;
	wire roundoff_tp2 = cs_mr | cs_sr | cs_sl;
	wire product_sign_tp4 = cs_mr | cs_mh | cs_sr | cs_sl | cs_dv;
	wire ac_sign_tp6 = cs_mr | cs_mh | cs_sr | cs_sl | cs_dv;
	wire ar_sign_tp8 = cs_mr | cs_mh | cs_dv;
	wire compare_tp6 = cs_cp;
	wire clear_br_tp3 = cs_mr | cs_sr | cs_sl;
	wire multiply_tp1 = cs_mr | cs_mh;
	wire shift_left_tp1 = cs_sl;
	wire shift_right_tp1 = cs_sr;
	wire divide_tp2 = cs_dv;
	wire special_add_tp3 = cs_sa;
	wire arithmetic_check_tp3 = cs_ad | cs_ca | cs_su | cs_cs | cs_sl;
	wire clear_ac_tp6 = cs_ca | cs_cs;
	wire clear_ac_tp3 = cs_dv;
	wire clear_br_tp6 = cs_mr | cs_mh;
	wire clear_ac_tp8 = cs_mr | cs_mh;


	wire time_pulse = lfcp & ~clock_disabled;
	wire time_pulse_dly = lfcp & ~clock_no_dly;
	reg [0:2] pulse_cnt = 0;
	reg clock_disabled = 0;
	reg clock_no_dly = 1;
	reg warning_signal = 0;
	reg [0:2] delay_counter = 0;
	wire tp1 = time_pulse & pulse_cnt == 0;
	wire tp2 = time_pulse & pulse_cnt == 1;
	wire tp3 = time_pulse & pulse_cnt == 2;
	wire tp4 = time_pulse & pulse_cnt == 3;
	wire tp5 = time_pulse & pulse_cnt == 4;
	wire tp6 = time_pulse & pulse_cnt == 5;
	wire tp7 = time_pulse & pulse_cnt == 6;
	wire tp8 = time_pulse & pulse_cnt == 7;
	wire start_delay = tp2 | tp5;
	wire delay_counter_end_carry = (&delay_counter) & time_pulse_dly;
	always @(posedge clk) begin
		if(time_pulse) pulse_cnt <= pulse_cnt + 1;
		if(start_delay) clock_no_dly <= 0;
		if(start_delay | stop_clock | alarm) clock_disabled <= 1;
		if(delay_counter_end_carry | sc_end_carry | restart) begin
			clock_disabled <= 0;
			clock_no_dly <= 1;
		end
		if(time_pulse_dly) delay_counter <= delay_counter + 1;
		if(restart) warning_signal <= 0;
		if(alarm) warning_signal <= 1;
	end





	wire stop_clock = stop_clock_tp1 & tp1 | stop_clock_tp2 & tp1;

	wire bus_to_output = bus_to_output_tp7 & tp7;
	assign pc_clear = pc_clear_tp6 & tp6;
	assign pc_from_bus = pc_from_bus_tp7 & tp7;
	assign storage_from_bus = storage_from_bus_tp7 & tp7;
	assign storage_clear = storage_clear_tp6 & tp6;

	wire storage_clear_low = cs_td & tp6;
	assign ar_from_bus = ar_from_bus_tp7 & tp7;
	assign clear_ac = clear_ac_tp6 & tp6 | clear_ac_tp3 & tp3 | clear_ac_tp8 & tp8;
	wire start_multiply = multiply_tp1 & tp1;
	wire start_shift_left = shift_left_tp1 & tp1;
	wire start_shift_right = shift_right_tp1 & tp1;

	wire start_divide = divide_tp2 & tp1;

	wire special_add = special_add_tp3 & tp3;
	wire special_carry = special_carry_tp7 & tp7;

	wire add_ar_to_ac_ctl = add_ar_to_ac_tp8 & tp8;
	wire sub_ar_to_ac_ctl = sub_ar_to_ac_tp8 & tp8 | sub_ar_to_ac_tp1 & tp1;
	assign ar_to_bus = ar_to_bus_tp8 & tp8;
	assign ac_to_bus = ac_to_bus_tp7 & tp7;
	assign ac_to_check = ac_to_check_tp7 & tp7;
	assign ac_to_br = ac_to_br_tp7 & tp7;
	wire carry_ctl = carry_tp2 & tp2;
	wire roundoff_ctl = roundoff_tp2 & tp2;
	wire product_sign_ctl = product_sign_tp4 & tp4;
	wire ac_sign_ctl = ac_sign_tp6 & tp6;
	wire ar_sign_ctl = ar_sign_tp8 & tp8;
	wire compare_ctl = compare_tp6 & tp6;
	assign clear_br = clear_br_tp3 & tp3 | clear_br_tp6 & tp6;




	assign pc_to_bus = tp2 | pc_to_bus_tp8&tp8;
	assign pc_to_check = tp2;
	assign pr_from_bus = tp4;
	assign pr_to_bus = tp5 | pr_to_bus_tp7 & tp7;
	assign cs_from_bus = tp5;
	assign cs_to_bus = tp6;
	assign ss_from_bus = tp2 | tp5;
	assign ss_to_bus = tp3 | tp6;
	assign storage_to_bus = tp4 | storage_to_bus_tp7 & tp7 | storage_to_bus_tp8 & tp8;
	assign storage_to_check = tp4 | storage_to_check_tp7 & tp7;
	assign sc_from_bus = tp5;
	assign sc_to_bus = tp6;
	assign cr_from_bus = tp3 | tp6 | cr_from_bus_tp8 & tp8;
	assign ss_clear = tp1 | tp4;
	assign cs_clear = tp4;
	assign pc_add = tp3;
	assign clear_ar = tp5;
	assign pr_clear = tp3;
	assign sc_clear = tp4;
	assign transfer_check = tp3 | tp6 | tp8;










	reg [5:15] ss;
	wire ss_from_bus;
	wire ss_to_bus;
	wire ss_clear;
	always @(posedge clk) begin
		if(ss_clear) ss <= 0;
		if(ss_from_bus) ss <= ss | bus;
	end


	wire [0:15] out_ts =
		{16{ss == addr_ts0}}&sw_ts_0 |
		{16{ss == addr_ts1}}&sw_ts_1 |
		{16{ss == addr_ts2}}&sw_ts_2 |
		{16{ss == addr_ts3}}&sw_ts_3 |
		{16{ss == addr_ts4}}&sw_ts_4 |
		{16{ss == addr_ts5}}&sw_ts_5 |
		{16{ss == addr_ts6}}&sw_ts_6 |
		{16{ss == addr_ts7}}&sw_ts_7 |
		{16{ss == addr_ts8}}&sw_ts_8 |
		{16{ss == addr_ts9}}&sw_ts_9 |
		{16{ss == addr_ts10}}&sw_ts_10 |
		{16{ss == addr_ts11}}&sw_ts_11 |
		{16{ss == addr_ts12}}&sw_ts_12 |
		{16{ss == addr_ts13}}&sw_ts_13 |
		{16{ss == addr_ts14}}&sw_ts_14 |
		{16{ss == addr_ts15}}&sw_ts_15 |
		{16{ss == addr_ts16}}&sw_ts_16 |
		{16{ss == addr_ts17}}&sw_ts_17 |
		{16{ss == addr_ts18}}&sw_ts_18 |
		{16{ss == addr_ts19}}&sw_ts_19 |
		{16{ss == addr_ts20}}&sw_ts_20 |
		{16{ss == addr_ts21}}&sw_ts_21 |
		{16{ss == addr_ts22}}&sw_ts_22 |
		{16{ss == addr_ts23}}&sw_ts_23 |
		{16{ss == addr_ts24}}&sw_ts_24 |
		{16{ss == addr_ts25}}&sw_ts_25 |
		{16{ss == addr_ts26}}&sw_ts_26;


	ww_ff_storage ff0(.clk(clk),
		.sw_input(sw_ff_0),
		.initial_value(storage_reset),
		.clear(storage_clear),
		.clear_low(storage_clear_low),
		.select(ss == addr_ff0),
		.in(in_to_ff),
		.out(out_ff0)
	);
	ww_ff_storage ff1(.clk(clk),
		.sw_input(sw_ff_1),
		.initial_value(storage_reset),
		.clear(storage_clear),
		.clear_low(storage_clear_low),
		.select(ss == addr_ff1),
		.in(in_to_ff),
		.out(out_ff1)
	);
	ww_ff_storage ff2(.clk(clk),
		.sw_input(sw_ff_2),
		.initial_value(storage_reset),
		.clear(storage_clear),
		.clear_low(storage_clear_low),
		.select(ss == addr_ff2),
		.in(in_to_ff),
		.out(out_ff2)
	);
	ww_ff_storage ff3(.clk(clk),
		.sw_input(sw_ff_3),
		.initial_value(storage_reset),
		.clear(storage_clear),
		.clear_low(storage_clear_low),
		.select(ss == addr_ff3),
		.in(in_to_ff),
		.out(out_ff3)
	);
	ww_ff_storage ff4(.clk(clk),
		.sw_input(sw_ff_4),
		.initial_value(storage_reset),
		.clear(storage_clear),
		.clear_low(storage_clear_low),
		.select(ss == addr_ff4),
		.in(in_to_ff),
		.out(out_ff4)
	);

	wire storage_from_bus;
	wire storage_to_bus;
	wire storage_to_check;
	wire storage_clear;
	reg storage_reset = 0;


	wire [0:15] in_to_ff = {{5{storage_from_bus&~cs_td}}, {11{storage_from_bus}}}&bus;
	wire [0:15] out_ff0;
	wire [0:15] out_ff1;
	wire [0:15] out_ff2;
	wire [0:15] out_ff3;
	wire [0:15] out_ff4;
	wire [0:15] out_ff = out_ff0 | out_ff1 | out_ff2 | out_ff3 | out_ff4;





	reg [0:15] ar;
	wire [0:15] ar_neg = ~ar;
	wire ar_from_bus;
	wire ar_to_bus;
	wire add_ar_to_ac = add_ar_to_ac_ctl | from_br15_one | div_add_dly;
	wire sub_ar_to_ac = sub_ar_to_ac_ctl | div_sub_dly;
	wire clear_ar;
	wire complement_ar = ar_sign;
	wire [0:15] ar_to_ac = {16{add_ar_to_ac}}&ar | {16{sub_ar_to_ac}}&~ar;

	reg div_add_dly = 0;
	reg div_sub_dly = 0;
	always @(posedge clk) begin
		div_add_dly <= divide_1;
		div_sub_dly <= divide_0;

		if(clear_ar) ar <= 0;
		if(complement_ar) ar <= ~ar;
		if(ar_from_bus) ar <= ar | bus;
	end


	wire [0:15] ac;
	wire [0:15] ac_neg = ~ac;
	wire [1:15] cry;
	wire ac_to_bus;
	wire ac_to_check;
	wire ac_to_br;
	wire carry = carry_ctl | div_carry_pulse;
	wire clear_ac;
	wire complement_ac = product_sign | ac_sign;
	wire [0:15] ac_to_br16 = {16{ac_to_br}}&ac;

	wire left_digit_carry;
	wire [1:15] carry_out;
	wire end_around_carry = carry_to_left[0];
	wire [0:15] carry_to_left;
	wire [1:15] zero_to_left;
	wire [1:15] one_to_left;
	wire divide_0;
	wire divide_1;
	wire [0:15] shift_left_n = {16{div_shift_left_pulse}} | {14{shift_left_pulse}};
	wire ac_zero_to_br0 = shift_carry_pulse & ~ac[15];
	wire ac_one_to_br0 = shift_carry_pulse & ac[15];

	reg to_ac0_dly = 0;

	ww_ac0 ac_0(.clk(clk), .acn(ac[0]),
		.from_ar(ar_to_ac[0] | to_ac0_dly),
		.clear(clear_ac),
		.complement(complement_ac | neg1_special_add),
		.shift_left(shift_left_n[0]),
		.shift_carry(shift_carry_pulse),


		.zero_to_left(divide_0),
		.one_to_left(divide_1),

		.zero_from_right(zero_to_left[1]),
		.one_from_right(one_to_left[1]),
		.zero_from_left(1'b0),
		.one_from_left(1'b0),

		.carry_in(carry_out[1]),
		.carry_out(left_digit_carry),
		.carry_from_right(carry_to_left[1]),
		.carry_to_left(carry_to_left[0])
	);
	genvar i;
	generate
		for(i = 1; i < 15; i = i + 1) begin : acgen
			ww_ac_slice ac_n(.clk(clk), .acn(ac[i]), .cryn(cry[i]),
				.left_digit(ac[(i+15)%16]),
				.from_ar(ar_to_ac[i]),
				.clear(clear_ac),
				.carry_clear(carry),
				.complement(complement_ac | neg1_special_add),
				.shift_left(shift_left_n[i]),
				.shift_carry(shift_carry_pulse),

				.zero_to_left(zero_to_left[i]),
				.one_to_left(one_to_left[i]),

				.zero_from_right(zero_to_left[(i+1)%16]),
				.one_from_right(one_to_left[(i+1)%16]),

				.carry_in(carry_out[(i+1)%16]),
				.carry_out(carry_out[i]),
				.carry_from_right(carry_to_left[(i+1)%16]),
				.carry_to_left(carry_to_left[i])
			);
		end
	endgenerate
	ww_ac_slice ac_15(.clk(clk), .acn(ac[15]), .cryn(cry[15]),
		.left_digit(ac[14]),
		.from_ar(ar_to_ac[15]),
		.clear(clear_ac),
		.carry_clear(carry),
		.complement(complement_ac),
		.shift_left(shift_left_n[15]),
		.shift_carry(shift_carry_pulse),


		.zero_to_left(zero_to_left[15]),
		.one_to_left(one_to_left[15]),

		.zero_from_right(br_zero_to_left[0]),
		.one_from_right(br_one_to_left[0]),

		.carry_in(1'b0),
		.carry_out(carry_out[15]),
		.carry_from_right(end_around_carry_roundoff),
		.carry_to_left(carry_to_left[15])
	);

	always @(posedge clk) begin
		to_ac0_dly <= special_add_ov;
	end


	wire [0:15] br;
	wire roundoff = roundoff_ctl & br[0];
	wire clear_br;
	wire from_br15_zero = multiply_pulse & ~br[15];
	wire from_br15_one = multiply_pulse & br[15];
	reg clear_br15_dly = 0;
	wire [0:14] br_zero_to_right;
	wire [0:14] br_one_to_right;
	wire [0:15] br_zero_to_left;
	wire [0:15] br_one_to_left;
	ww_br_slice br_0(.clk(clk), .brn(br[0]),
		.from_ac(ac_to_br16[0]),
		.clear(clear_br),
		.shift_left(shift_left_pulse),
		.shift_right(shift_carry_pulse),

		.zero_to_left(br_zero_to_left[0]),
		.one_to_left(br_one_to_left[0]),
		.zero_to_right(br_zero_to_right[0]),
		.one_to_right(br_one_to_right[0]),

		.zero_from_right(br_zero_to_left[1]),
		.one_from_right(br_one_to_left[1]),
		.zero_from_left(ac_zero_to_br0),
		.one_from_left(ac_one_to_br0)
	);
	generate
		for(i = 1; i < 15; i = i + 1) begin : brgen
			ww_br_slice br_n(.clk(clk), .brn(br[i]),
				.from_ac(ac_to_br16[i]),
				.clear(clear_br),
				.shift_left(shift_left_pulse | div_shift_left_pulse),
				.shift_right(shift_carry_pulse),

				.zero_to_left(br_zero_to_left[i]),
				.one_to_left(br_one_to_left[i]),
				.zero_to_right(br_zero_to_right[i]),
				.one_to_right(br_one_to_right[i]),

				.zero_from_right(br_zero_to_left[(i+1)%16]),
				.one_from_right(br_one_to_left[(i+1)%16]),
				.zero_from_left(br_zero_to_right[(i+15)%16]),
				.one_from_left(br_one_to_right[(i+15)%16])
			);
		end
	endgenerate
	ww_br_slice br_15(.clk(clk), .brn(br[15]),
		.from_ac(ac_to_br16[15]),
		.clear(clear_br),
		.shift_left(shift_left_pulse | div_shift_left_pulse),
		.shift_right(shift_carry_pulse),

		.zero_to_left(br_zero_to_left[15]),
		.one_to_left(br_one_to_left[15]),



		.zero_from_right(clear_br15_dly | divide_1),
		.one_from_right(divide_0),
		.zero_from_left(br_zero_to_right[14]),
		.one_from_left(br_one_to_right[14])
	);
	always @(posedge clk)
		clear_br15_dly <= from_br15_one;


	reg sign_control = 0;
	wire product_sign = product_sign_ctl & sign_control;
	wire ac_sign = ac_sign_ctl & ac[0];
	wire ar_sign = ar_sign_ctl & ar[0];
	wire change_control = compare_ctl & ~ac[0];
	always @(posedge clk) begin
		if(complement_ac | complement_ar) sign_control <= ~sign_control;
	end


	reg [11:15] sc;
	wire sc_from_bus;
	wire sc_to_bus;
	wire sc_clear;
	wire sc_add = shift_left_pulse | shift_carry_pulse | div_shift_left_pulse;
	wire sc_end_carry = ~(|sc) & sc_add;
	wire sc_reset_multiply = start_multiply;
	wire sc_reset_divide = start_divide;
	always @(posedge clk) begin
		if(sc_clear) sc <= 0;
		if(sc_from_bus) sc <= sc | bus;
		if(sc_add) sc <= sc + 1;

		if(sc_reset_multiply) sc <= 5'o22;
		if(sc_reset_divide) sc <= 5'o20;
	end


	reg multiply = 0;
	wire multiply_pulse = multiply & hfcp;
	always @(posedge clk) begin
		if(start_multiply) multiply <= 1;
		if(sc_end_carry) multiply <= 0;
	end


	reg shift_left = 0;
	reg shift_right = 0;
	wire shift_left_pulse = shift_left & hfcp;
	wire shift_right_pulse = shift_right & hfcp;
	wire shift_carry_pulse = shift_right_pulse | from_br15_zero;
	always @(posedge clk) begin
		if(start_shift_left) shift_left <= 1;
		if(start_shift_right) shift_right <= 1;
		if(sc_end_carry) begin
			shift_left <= 0;
			shift_right <= 0;
		end
	end


	reg divide = 0;
	reg div_time_dist = 0;
	reg divide_error = 0;
	wire divide_pulse = divide & lfcp;
	wire div_carry_pulse = divide_pulse & ~div_time_dist;
	wire div_shift_left_pulse = divide_pulse & div_time_dist;
	reg divide_pulse_dly = 0;
	wire divide_alarm = divide_0 & divide_error;
	always @(posedge clk) begin
		divide_pulse_dly <= divide_pulse;

		if(start_divide) begin
			divide <= 1;
			div_time_dist <= 0;
		end
		if(sc_end_carry) divide <= 0;
		if(divide_pulse_dly)
			div_time_dist <= ~div_time_dist;
		if(ac_sign_ctl) divide_error <= 1;
		if(divide_1) divide_error <= 0;
	end


	reg ac0_carry = 0;
	reg special_add_mem = 0;
	wire add_ac0_carry = ac0_carry & (special_carry | carry);
	wire special_add_ov = special_add & ac0_carry;
	wire neg1_special_add = special_add_mem & special_carry;
	wire end_around_carry_roundoff = end_around_carry | roundoff | add_ac0_carry;
	wire clear_c0_carry = div_shift_left_pulse | restart;

	reg clear_ac0_carry_dly = 0;
	reg clear_special_add_mem_dly = 0;
	reg left_digit_carry_dly = 0;
	reg [0:1] end_around_carry_dly = 0;
	always @(posedge clk) begin
		clear_ac0_carry_dly <= special_add_ov | special_carry;
		clear_special_add_mem_dly <= neg1_special_add;
		left_digit_carry_dly <= left_digit_carry;
		end_around_carry_dly <= {end_around_carry_dly[1], end_around_carry};

		if(clear_c0_carry | clear_ac0_carry_dly) ac0_carry <= 0;
		if(left_digit_carry_dly | end_around_carry_dly[0]) ac0_carry <= ~ac0_carry;
		if(left_digit_carry_dly | clear_special_add_mem_dly) special_add_mem <= 0;
		if(special_add_ov) special_add_mem <= 1;
	end







	wire arithmetic_check = arithmetic_check_tp3 & tp3;
	wire arithmetic_alarm = arithmetic_check & ac0_carry;

	wire alarm = arithmetic_alarm | divide_alarm;


	reg [0:15] cr = 0;
	wire cr_clear = 0;
	wire cr_from_bus;
	wire transfer_check;
	reg check_cr = 0;

	wire cr_alarm = (|cr)&check_cr;
	always @(posedge clk) begin

		check_cr <= transfer_check;

		cr <= cr ^ check_bus;
		if(cr_from_bus) cr <= cr ^ bus;
		if(cr_clear) cr <= 0;
	end
endmodule