data/full_repos/permissive/143278/ivltests/test_varray1.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:11: syntax error, unexpected \'@\'\n  @(negedge reset);\n  ^\n%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:13: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_varray1.v:43: Unsupported: Ignoring delay on this delayed statement.\n  initial forever #T clk = ~clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:55: syntax error, unexpected \'@\'\n  @(negedge reset);\n  ^\n%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:57: syntax error, unexpected \'@\'\n  repeat (D) @(negedge clk);\n             ^\n%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:59: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_varray1.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_varray1.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #S;\n    ^\n%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:90: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Error: data/full_repos/permissive/143278/ivltests/test_varray1.v:92: syntax error, unexpected \'@\'\n repeat (5) @(negedge clk);\n            ^\n%Error: Exiting due to 7 error(s), 3 warning(s)\n'
module stimulus #(parameter W = 8, M = 200, MAX = 256) (
                  input bit clk, reset,
                 output reg [W-1:0] x
                 );

int i;

initial begin
  @(negedge reset);
  for (i = 0; i < M; i=i+1) begin
    @(negedge clk);
    x = {$random} % MAX;
  end

end


endmodule
module stimulus #(parameter W = 8, M = 200, MAX = 256) (
                  input bit clk, reset,
                 output reg [W-1:0] x
                 );


int i;

initial begin
  @(negedge reset);
  for (i = 0; i < M; i=i+1) begin
    @(negedge clk);
    x = {$random} % MAX;
  end

end


endmodule