data/full_repos/permissive/181013988/src/reg_mux.v
data/verilator_xmls/125903e4-b47a-4d53-b001-028d5a700033.xml
module reg_mux(
    input wire [4:0] in0,
    input wire [4:0] in1,
    input wire sel,
    output reg[4:0] out
);

    always @(*) begin
        if(sel == 0)
            out <= in0;
        else
            out <= in1;
    end

endmodule
module reg_mux(
    input wire [4:0] in0,
    input wire [4:0] in1,
    input wire sel,
    output reg[4:0] out
);


    always @(*) begin
        if(sel == 0)
            out <= in0;
        else
            out <= in1;
    end

endmodule